From 97c5f6505e37752cc33289eb4d16106c20cfe736 Mon Sep 17 00:00:00 2001
From: CarlWachter <carlwachter@web.de>
Date: Sun, 3 Dec 2023 09:16:05 +0100
Subject: [PATCH] Working send WIP

---
 .DS_Store                                     |   Bin 0 -> 6148 bytes
 .cproject                                     |    10 +-
 .mxproject                                    |    50 +-
 .settings/language.settings.xml               |     4 +-
 .settings/stm32cubeide.project.prefs          |     4 +-
 App/Src/test.cpp                              |    26 +-
 CAN-Card_Module_Software Debug.launch         |    83 +
 can-tests.ioc => CAN-Card_Module_Software.ioc |   112 +-
 Core/Inc/main.h                               |   138 +-
 Core/Inc/stm32f4xx_hal_conf.h                 |   990 +-
 Core/Inc/stm32f4xx_it.h                       |   133 +-
 Core/Src/main.c                               |   693 +-
 Core/Src/stm32f4xx_hal_msp.c                  |   487 +-
 Core/Src/stm32f4xx_it.c                       |   420 +-
 Debug/App/Src/subdir.mk                       |     2 +-
 Debug/App/Src/test.d                          |    28 +-
 Debug/App/Src/test.o                          |   Bin 1081864 -> 1081916 bytes
 Debug/App/Src/test.su                         |     2 +-
 Debug/Core/Src/main.cyclo                     |    13 +-
 Debug/Core/Src/main.o                         |   Bin 1073728 -> 1076848 bytes
 Debug/Core/Src/main.su                        |    13 +-
 Debug/Core/Src/stm32f4xx_hal_msp.cyclo        |     6 +-
 Debug/Core/Src/stm32f4xx_hal_msp.o            |   Bin 1071124 -> 1073916 bytes
 Debug/Core/Src/stm32f4xx_hal_msp.su           |     6 +-
 Debug/Core/Src/stm32f4xx_it.cyclo             |     1 +
 Debug/Core/Src/stm32f4xx_it.o                 |   Bin 1064268 -> 1067092 bytes
 Debug/Core/Src/stm32f4xx_it.su                |     1 +
 Debug/Core/Src/subdir.mk                      |     2 +-
 Debug/Core/Src/syscalls.o                     |   Bin 83104 -> 83012 bytes
 Debug/Core/Src/sysmem.o                       |   Bin 47796 -> 47700 bytes
 Debug/Core/Src/system_stm32f4xx.o             |   Bin 1065204 -> 1065104 bytes
 Debug/Core/Src/test.cyclo                     |     0
 Debug/Core/Src/test.d                         |    74 -
 Debug/Core/Src/test.su                        |     0
 Debug/Core/Startup/startup_stm32f407zgtx.o    |   Bin 7244 -> 7264 bytes
 .../STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o  |   Bin 1078604 -> 1078508 bytes
 .../Src/stm32f4xx_hal_can.o                   |   Bin 1086112 -> 1086016 bytes
 .../Src/stm32f4xx_hal_cortex.o                |   Bin 1081728 -> 1081628 bytes
 .../Src/stm32f4xx_hal_dma.o                   |   Bin 1076820 -> 1076720 bytes
 .../Src/stm32f4xx_hal_dma_ex.o                |   Bin 1074092 -> 1073992 bytes
 .../Src/stm32f4xx_hal_exti.o                  |   Bin 1068248 -> 1068148 bytes
 .../Src/stm32f4xx_hal_flash.o                 |   Bin 1072424 -> 1072324 bytes
 .../Src/stm32f4xx_hal_flash_ex.o              |   Bin 1072380 -> 1072284 bytes
 .../Src/stm32f4xx_hal_flash_ramfunc.o         |   Bin 1061180 -> 1061084 bytes
 .../Src/stm32f4xx_hal_gpio.o                  |   Bin 1069852 -> 1069756 bytes
 .../Src/stm32f4xx_hal_pwr.o                   |   Bin 1070916 -> 1070816 bytes
 .../Src/stm32f4xx_hal_pwr_ex.o                |   Bin 1066224 -> 1066124 bytes
 .../Src/stm32f4xx_hal_rcc.o                   |   Bin 1075872 -> 1075904 bytes
 .../Src/stm32f4xx_hal_rcc.su                  |     2 +-
 .../Src/stm32f4xx_hal_rcc_ex.o                |   Bin 1068640 -> 1068544 bytes
 .../Src/stm32f4xx_hal_uart.o                  |   Bin 1119704 -> 1119604 bytes
 .../STM32F4xx_HAL_Driver/Src/subdir.mk        |     2 +-
 Debug/Libs/sta-core/src/atomic/mutex.d        |     4 +-
 Debug/Libs/sta-core/src/atomic/mutex.o        |   Bin 21996 -> 22016 bytes
 Debug/Libs/sta-core/src/atomic/signal.d       |     4 +-
 Debug/Libs/sta-core/src/atomic/signal.o       |   Bin 22004 -> 22024 bytes
 Debug/Libs/sta-core/src/atomic/subdir.mk      |     2 +-
 Debug/Libs/sta-core/src/bus/device.d          |    16 +-
 Debug/Libs/sta-core/src/bus/device.o          |   Bin 55108 -> 55016 bytes
 Debug/Libs/sta-core/src/bus/i2c/device.d      |    24 +-
 Debug/Libs/sta-core/src/bus/i2c/device.o      |   Bin 53024 -> 52940 bytes
 Debug/Libs/sta-core/src/bus/i2c/i2c.d         |    12 +-
 Debug/Libs/sta-core/src/bus/i2c/i2c.o         |   Bin 49352 -> 49260 bytes
 Debug/Libs/sta-core/src/bus/i2c/subdir.mk     |     2 +-
 Debug/Libs/sta-core/src/bus/interface.d       |    12 +-
 Debug/Libs/sta-core/src/bus/interface.o       |   Bin 51908 -> 51812 bytes
 Debug/Libs/sta-core/src/bus/spi/device.d      |    32 +-
 Debug/Libs/sta-core/src/bus/spi/device.o      |   Bin 55108 -> 55024 bytes
 Debug/Libs/sta-core/src/bus/spi/settings.d    |    12 +-
 Debug/Libs/sta-core/src/bus/spi/settings.o    |   Bin 48808 -> 48712 bytes
 Debug/Libs/sta-core/src/bus/spi/spi.d         |    16 +-
 Debug/Libs/sta-core/src/bus/spi/spi.o         |   Bin 80128 -> 80040 bytes
 Debug/Libs/sta-core/src/bus/spi/subdir.mk     |     2 +-
 Debug/Libs/sta-core/src/bus/subdir.mk         |     2 +-
 Debug/Libs/sta-core/src/bus/uart/settings.o   |   Bin 21404 -> 21416 bytes
 Debug/Libs/sta-core/src/bus/uart/subdir.mk    |     2 +-
 Debug/Libs/sta-core/src/bus/uart/uart.d       |    16 +-
 Debug/Libs/sta-core/src/bus/uart/uart.o       |   Bin 49532 -> 49436 bytes
 Debug/Libs/sta-core/src/can/id.d              |     4 +-
 Debug/Libs/sta-core/src/can/id.o              |   Bin 46516 -> 46404 bytes
 Debug/Libs/sta-core/src/can/iter.d            |     8 +-
 Debug/Libs/sta-core/src/can/iter.o            |   Bin 53756 -> 53652 bytes
 Debug/Libs/sta-core/src/can/subdir.mk         |     2 +-
 Debug/Libs/sta-core/src/debug/assert.d        |    12 +-
 Debug/Libs/sta-core/src/debug/assert.o        |   Bin 79364 -> 79268 bytes
 .../sta-core/src/debug/printing/printable.d   |    12 +-
 .../sta-core/src/debug/printing/printable.o   |   Bin 101232 -> 101144 bytes
 .../src/debug/printing/printable_printf.cyclo |     2 +-
 .../src/debug/printing/printable_printf.d     |    12 +-
 .../src/debug/printing/printable_printf.o     |   Bin 84068 -> 83968 bytes
 .../src/debug/printing/printable_printf.su    |     2 +-
 .../src/debug/printing/printable_uart.cyclo   |     2 +-
 .../src/debug/printing/printable_uart.d       |    32 +-
 .../src/debug/printing/printable_uart.o       |   Bin 95156 -> 95084 bytes
 .../src/debug/printing/printable_uart.su      |     2 +-
 .../sta-core/src/debug/printing/subdir.mk     |     2 +-
 Debug/Libs/sta-core/src/debug/subdir.mk       |     2 +-
 .../sta-core/src/devices/arduino/bus/i2c.d    |     4 +-
 .../sta-core/src/devices/arduino/bus/i2c.o    |   Bin 22028 -> 22048 bytes
 .../sta-core/src/devices/arduino/bus/spi.o    |   Bin 21408 -> 21420 bytes
 .../src/devices/arduino/bus/subdir.mk         |     2 +-
 .../Libs/sta-core/src/devices/arduino/delay.d |     4 +-
 .../Libs/sta-core/src/devices/arduino/delay.o |   Bin 22024 -> 22044 bytes
 .../sta-core/src/devices/arduino/gpio_pin.d   |     4 +-
 .../sta-core/src/devices/arduino/gpio_pin.o   |   Bin 22040 -> 22060 bytes
 .../sta-core/src/devices/arduino/subdir.mk    |     2 +-
 .../Libs/sta-core/src/devices/raspi/bus/i2c.d |     4 +-
 .../Libs/sta-core/src/devices/raspi/bus/i2c.o |   Bin 22016 -> 22036 bytes
 .../Libs/sta-core/src/devices/raspi/bus/spi.d |     4 +-
 .../Libs/sta-core/src/devices/raspi/bus/spi.o |   Bin 22020 -> 22040 bytes
 .../sta-core/src/devices/raspi/bus/subdir.mk  |     2 +-
 Debug/Libs/sta-core/src/devices/raspi/delay.d |     4 +-
 Debug/Libs/sta-core/src/devices/raspi/delay.o |   Bin 22016 -> 22036 bytes
 .../sta-core/src/devices/raspi/gpio_pin.d     |     4 +-
 .../sta-core/src/devices/raspi/gpio_pin.o     |   Bin 22032 -> 22052 bytes
 .../Libs/sta-core/src/devices/raspi/subdir.mk |     2 +-
 Debug/Libs/sta-core/src/devices/stm32/adc.d   |     8 +-
 Debug/Libs/sta-core/src/devices/stm32/adc.o   |   Bin 1063796 -> 1063708 bytes
 .../Libs/sta-core/src/devices/stm32/bus/i2c.d |    12 +-
 .../Libs/sta-core/src/devices/stm32/bus/i2c.o |   Bin 1100260 -> 1100172 bytes
 .../Libs/sta-core/src/devices/stm32/bus/spi.d |     8 +-
 .../Libs/sta-core/src/devices/stm32/bus/spi.o |   Bin 1063904 -> 1063828 bytes
 .../sta-core/src/devices/stm32/bus/subdir.mk  |     2 +-
 .../sta-core/src/devices/stm32/bus/uart.d     |    28 +-
 .../sta-core/src/devices/stm32/bus/uart.o     |   Bin 1111736 -> 1111676 bytes
 .../Libs/sta-core/src/devices/stm32/can.cyclo |    24 +-
 Debug/Libs/sta-core/src/devices/stm32/can.d   |    36 +-
 Debug/Libs/sta-core/src/devices/stm32/can.o   |   Bin 1101292 -> 1101208 bytes
 Debug/Libs/sta-core/src/devices/stm32/can.su  |    24 +-
 Debug/Libs/sta-core/src/devices/stm32/delay.d |    20 +-
 Debug/Libs/sta-core/src/devices/stm32/delay.o |   Bin 1080260 -> 1080164 bytes
 .../sta-core/src/devices/stm32/gpio_pin.cyclo |     2 +-
 .../sta-core/src/devices/stm32/gpio_pin.d     |    20 +-
 .../sta-core/src/devices/stm32/gpio_pin.o     |   Bin 1087972 -> 1087876 bytes
 .../sta-core/src/devices/stm32/gpio_pin.su    |     2 +-
 Debug/Libs/sta-core/src/devices/stm32/init.d  |     8 +-
 Debug/Libs/sta-core/src/devices/stm32/init.o  |   Bin 45524 -> 45420 bytes
 .../Libs/sta-core/src/devices/stm32/subdir.mk |     2 +-
 .../src/devices/template/custom_printable.d   |     4 +-
 .../src/devices/template/custom_printable.o   |   Bin 22088 -> 22108 bytes
 .../sta-core/src/devices/template/delay.d     |     4 +-
 .../sta-core/src/devices/template/delay.o     |   Bin 22032 -> 22052 bytes
 .../sta-core/src/devices/template/subdir.mk   |     2 +-
 Debug/Libs/sta-core/src/mutex.d               |     4 +-
 Debug/Libs/sta-core/src/mutex.o               |   Bin 24928 -> 24948 bytes
 Debug/Libs/sta-core/src/subdir.mk             |     2 +-
 Debug/can-tests.elf                           |   Bin 1218972 -> 0 bytes
 Debug/can-tests.list                          |  6978 ----
 Debug/can-tests.map                           |  5926 ---
 Debug/makefile                                |    20 +-
 .../Device/ST/STM32F4xx/Include/stm32f407xx.h | 31214 ++++++++--------
 .../Device/ST/STM32F4xx/Include/stm32f4xx.h   |   602 +-
 .../ST/STM32F4xx/Include/system_stm32f4xx.h   |   208 +-
 Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt |    12 +-
 Drivers/CMSIS/Include/cmsis_armcc.h           |  1730 +-
 Drivers/CMSIS/Include/cmsis_armclang.h        |  3738 +-
 Drivers/CMSIS/Include/cmsis_compiler.h        |   532 +-
 Drivers/CMSIS/Include/cmsis_gcc.h             |  4170 +--
 Drivers/CMSIS/Include/cmsis_iccarm.h          |  1870 +-
 Drivers/CMSIS/Include/cmsis_version.h         |    78 +-
 Drivers/CMSIS/Include/core_armv8mbl.h         |  3836 +-
 Drivers/CMSIS/Include/core_armv8mml.h         |  5854 +--
 Drivers/CMSIS/Include/core_cm0.h              |  1898 +-
 Drivers/CMSIS/Include/core_cm0plus.h          |  2166 +-
 Drivers/CMSIS/Include/core_cm1.h              |  1952 +-
 Drivers/CMSIS/Include/core_cm23.h             |  3986 +-
 Drivers/CMSIS/Include/core_cm3.h              |  3882 +-
 Drivers/CMSIS/Include/core_cm33.h             |  6004 +--
 Drivers/CMSIS/Include/core_cm4.h              |  4258 +--
 Drivers/CMSIS/Include/core_cm7.h              |  5342 +--
 Drivers/CMSIS/Include/core_sc000.h            |  2044 +-
 Drivers/CMSIS/Include/core_sc300.h            |  3830 +-
 Drivers/CMSIS/Include/mpu_armv7.h             |   540 +-
 Drivers/CMSIS/Include/mpu_armv8.h             |   666 +-
 Drivers/CMSIS/Include/tz_context.h            |   140 +-
 Drivers/CMSIS/LICENSE.txt                     |   402 +-
 .../Inc/Legacy/stm32_hal_legacy.h             |  8028 ++--
 .../STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h  |   594 +-
 .../Inc/stm32f4xx_hal_can.h                   |  1688 +-
 .../Inc/stm32f4xx_hal_cortex.h                |   814 +-
 .../Inc/stm32f4xx_hal_def.h                   |   420 +-
 .../Inc/stm32f4xx_hal_dma.h                   |  1604 +-
 .../Inc/stm32f4xx_hal_dma_ex.h                |   204 +-
 .../Inc/stm32f4xx_hal_exti.h                  |   732 +-
 .../Inc/stm32f4xx_hal_flash.h                 |   850 +-
 .../Inc/stm32f4xx_hal_flash_ex.h              |  2126 +-
 .../Inc/stm32f4xx_hal_flash_ramfunc.h         |   152 +-
 .../Inc/stm32f4xx_hal_gpio.h                  |   650 +-
 .../Inc/stm32f4xx_hal_gpio_ex.h               |  3180 +-
 .../Inc/stm32f4xx_hal_pwr.h                   |   854 +-
 .../Inc/stm32f4xx_hal_pwr_ex.h                |   680 +-
 .../Inc/stm32f4xx_hal_rcc.h                   |  2918 +-
 .../Inc/stm32f4xx_hal_rcc_ex.h                | 14222 +++----
 .../Inc/stm32f4xx_hal_uart.h                  |  1768 +-
 .../Inc/stm32f4xx_ll_bus.h                    |  4210 +--
 .../Inc/stm32f4xx_ll_cortex.h                 |  1274 +-
 .../Inc/stm32f4xx_ll_dma.h                    |  5736 +--
 .../Inc/stm32f4xx_ll_exti.h                   |  1908 +-
 .../Inc/stm32f4xx_ll_gpio.h                   |  1962 +-
 .../Inc/stm32f4xx_ll_pwr.h                    |  1970 +-
 .../Inc/stm32f4xx_ll_rcc.h                    | 14192 +++----
 .../Inc/stm32f4xx_ll_system.h                 |  3422 +-
 .../Inc/stm32f4xx_ll_usart.h                  |  5042 +--
 .../Inc/stm32f4xx_ll_utils.h                  |   614 +-
 Drivers/STM32F4xx_HAL_Driver/LICENSE.txt      |    12 +-
 .../STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c  |  1230 +-
 .../Src/stm32f4xx_hal_can.c                   |  4924 +--
 .../Src/stm32f4xx_hal_cortex.c                |  1004 +-
 .../Src/stm32f4xx_hal_dma.c                   |  2610 +-
 .../Src/stm32f4xx_hal_dma_ex.c                |   626 +-
 .../Src/stm32f4xx_hal_exti.c                  |  1094 +-
 .../Src/stm32f4xx_hal_flash.c                 |  1550 +-
 .../Src/stm32f4xx_hal_flash_ex.c              |  2694 +-
 .../Src/stm32f4xx_hal_flash_ramfunc.c         |   344 +-
 .../Src/stm32f4xx_hal_gpio.c                  |  1066 +-
 .../Src/stm32f4xx_hal_pwr.c                   |  1142 +-
 .../Src/stm32f4xx_hal_pwr_ex.c                |  1200 +-
 .../Src/stm32f4xx_hal_rcc.c                   |  2244 +-
 .../Src/stm32f4xx_hal_rcc_ex.c                |  7568 ++--
 .../Src/stm32f4xx_hal_uart.c                  |  7502 ++--
 Libs/.DS_Store                                |   Bin 0 -> 6148 bytes
 Libs/driver-mcp2515                           |     1 -
 222 files changed, 106713 insertions(+), 119592 deletions(-)
 create mode 100644 .DS_Store
 create mode 100644 CAN-Card_Module_Software Debug.launch
 rename can-tests.ioc => CAN-Card_Module_Software.ioc (61%)
 delete mode 100644 Debug/Core/Src/test.cyclo
 delete mode 100644 Debug/Core/Src/test.d
 delete mode 100644 Debug/Core/Src/test.su
 delete mode 100644 Debug/can-tests.elf
 delete mode 100644 Debug/can-tests.list
 delete mode 100644 Debug/can-tests.map
 create mode 100644 Libs/.DS_Store
 delete mode 160000 Libs/driver-mcp2515

diff --git a/.DS_Store b/.DS_Store
new file mode 100644
index 0000000000000000000000000000000000000000..bd4e70961f3734476483b546225fd03eab7a5f4d
GIT binary patch
literal 6148
zcmeHKPfNov6i>G5HipoH!j1v21GnKs@lxu%d9tDhmD$pv#oCOuvxhS1S-+5<#Lwe<
zNh%KKRm8mq$?yG5njbWO7-QU>hkeFu##j>?B1dI~pnGMgW|9#(juGVPG>ByY_M3_Q
zb--`8*cpphz|ybZA57yY&3e6eUaMOhn+=e5<JNnSxtICbJazrqHCh)^#zCd~!DTeb
z$M*J#Ofo-8CNotKg%e1*xr&ld=B}J4VXA699cY1!?M_h)`UhPx81@%kQ5+3=T`}B0
zTr676o!!0T^YLT+l*kuNC<nfkY#FTJ6_n5QJbSYwmdQQ%s{AUCkQg8ahyh|?eHk!k
zLbJWT6wu0v0b<|>25^56&=4JirAD=NK!?|7j9Z8(pyOKtQ5bX#mKq@f!gVR2F6HKl
z!F4(Kg~@XamKt?A<7#FY$IM(kUbvba{6eKO?r5Z*7$63g8K`U1#`FIaewmez{N)m|
zhyh~YpE1C#kvDQ-QRZy@wmdv*1++V8D418G0s{KdB>)WEM>;B~;{tWaa}1UmaTN5c
QazMHWC_<<s27ZBo569t34gdfE

literal 0
HcmV?d00001

diff --git a/.cproject b/.cproject
index f0397b8..389d8a0 100644
--- a/.cproject
+++ b/.cproject
@@ -48,9 +48,8 @@
 									<listOptionValue builtIn="false" value="../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy"/>
 									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32F4xx/Include"/>
 									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/can-tests/Libs/sta-core/include}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/can-tests/App/Inc}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/can-tests/Libs/driver-mcp2515/include}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/CAN-Card_Module_Software/App/Inc}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/CAN-Card_Module_Software/Libs/sta-core/include}&quot;"/>
 								</option>
 								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1002361924" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
 							</tool>
@@ -63,9 +62,8 @@
 									<listOptionValue builtIn="false" value="../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy"/>
 									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32F4xx/Include"/>
 									<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/can-tests/Libs/sta-core/include}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/can-tests/App/Inc}&quot;"/>
-									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/can-tests/Libs/driver-mcp2515/include}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/CAN-Card_Module_Software/Libs/sta-core/include}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/CAN-Card_Module_Software/App/Inc}&quot;"/>
 								</option>
 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.definedsymbols.2087867384" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
 									<listOptionValue builtIn="false" value="DEBUG"/>
diff --git a/.mxproject b/.mxproject
index 07a0ab2..c46b770 100644
--- a/.mxproject
+++ b/.mxproject
@@ -1,25 +1,25 @@
-[PreviousLibFiles]
-LibFiles=Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usart.h;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_can.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_rcc_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_bus.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_rcc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_system.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_utils.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_flash_ramfunc.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_gpio_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_gpio.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dma.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_dmamux.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_pwr_ex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_pwr.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_cortex.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal.h;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_def.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_exti.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_hal_uart.h;Drivers\STM32F4xx_HAL_Driver\Inc\stm32f4xx_ll_usart.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f407xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Include\system_stm32f4xx.h;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
-
-[PreviousUsedCubeIDEFiles]
-SourceFiles=Core\Src\main.c;Core\Src\stm32f4xx_it.c;Core\Src\stm32f4xx_hal_msp.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Core\Src\system_stm32f4xx.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_can.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Core\Src\system_stm32f4xx.c;;;
-HeaderPath=Drivers\STM32F4xx_HAL_Driver\Inc;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32F4xx\Include;Drivers\CMSIS\Include;Core\Inc;
-CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
-
-[PreviousGenFiles]
-AdvancedFolderStructure=true
-HeaderFileListSize=3
-HeaderFiles#0=..\Core\Inc\stm32f4xx_it.h
-HeaderFiles#1=..\Core\Inc\stm32f4xx_hal_conf.h
-HeaderFiles#2=..\Core\Inc\main.h
-HeaderFolderListSize=1
-HeaderPath#0=..\Core\Inc
-HeaderFiles=;
-SourceFileListSize=3
-SourceFiles#0=..\Core\Src\stm32f4xx_it.c
-SourceFiles#1=..\Core\Src\stm32f4xx_hal_msp.c
-SourceFiles#2=..\Core\Src\main.c
-SourceFolderListSize=1
-SourcePath#0=..\Core\Src
-SourceFiles=;
-
+[PreviousLibFiles]
+LibFiles=Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dmamux.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dmamux.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h;Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Drivers/CMSIS/Include/core_cm7.h;Drivers/CMSIS/Include/tz_context.h;Drivers/CMSIS/Include/core_cm3.h;Drivers/CMSIS/Include/cmsis_compiler.h;Drivers/CMSIS/Include/cmsis_armclang.h;Drivers/CMSIS/Include/mpu_armv7.h;Drivers/CMSIS/Include/cmsis_armcc.h;Drivers/CMSIS/Include/core_cm4.h;Drivers/CMSIS/Include/core_cm0.h;Drivers/CMSIS/Include/cmsis_iccarm.h;Drivers/CMSIS/Include/core_armv8mml.h;Drivers/CMSIS/Include/core_sc000.h;Drivers/CMSIS/Include/core_cm1.h;Drivers/CMSIS/Include/mpu_armv8.h;Drivers/CMSIS/Include/core_sc300.h;Drivers/CMSIS/Include/cmsis_gcc.h;Drivers/CMSIS/Include/cmsis_version.h;Drivers/CMSIS/Include/core_cm23.h;Drivers/CMSIS/Include/core_cm33.h;Drivers/CMSIS/Include/core_cm0plus.h;Drivers/CMSIS/Include/core_armv8mbl.h;
+
+[PreviousUsedCubeIDEFiles]
+SourceFiles=Core/Src/main.c;Core/Src/stm32f4xx_it.c;Core/Src/stm32f4xx_hal_msp.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Core/Src/system_stm32f4xx.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c;Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c;Drivers/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c;Core/Src/system_stm32f4xx.c;;;
+HeaderPath=Drivers/STM32F4xx_HAL_Driver/Inc;Drivers/STM32F4xx_HAL_Driver/Inc/Legacy;Drivers/CMSIS/Device/ST/STM32F4xx/Include;Drivers/CMSIS/Include;Core/Inc;
+CDefines=USE_HAL_DRIVER;STM32F407xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
+
+[PreviousGenFiles]
+AdvancedFolderStructure=true
+HeaderFileListSize=3
+HeaderFiles#0=../Core/Inc/stm32f4xx_it.h
+HeaderFiles#1=../Core/Inc/stm32f4xx_hal_conf.h
+HeaderFiles#2=../Core/Inc/main.h
+HeaderFolderListSize=1
+HeaderPath#0=../Core/Inc
+HeaderFiles=;
+SourceFileListSize=3
+SourceFiles#0=../Core/Src/stm32f4xx_it.c
+SourceFiles#1=../Core/Src/stm32f4xx_hal_msp.c
+SourceFiles#2=../Core/Src/main.c
+SourceFolderListSize=1
+SourcePath#0=../Core/Src
+SourceFiles=;
+
diff --git a/.settings/language.settings.xml b/.settings/language.settings.xml
index 4c81558..5aede8f 100644
--- a/.settings/language.settings.xml
+++ b/.settings/language.settings.xml
@@ -5,7 +5,7 @@
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="-333662596449102967" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="1691560592812839866" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
@@ -16,7 +16,7 @@
 			<provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
 			<provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
 			<provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
-			<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="-333662596449102967" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
+			<provider class="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" console="false" env-hash="1691560592812839866" id="com.st.stm32cube.ide.mcu.toolchain.armnone.setup.CrossBuiltinSpecsDetector" keep-relative-paths="false" name="MCU ARM GCC Built-in Compiler Settings" parameter="${COMMAND} ${FLAGS} -E -P -v -dD &quot;${INPUTS}&quot;" prefer-non-shared="true">
 				<language-scope id="org.eclipse.cdt.core.gcc"/>
 				<language-scope id="org.eclipse.cdt.core.g++"/>
 			</provider>
diff --git a/.settings/stm32cubeide.project.prefs b/.settings/stm32cubeide.project.prefs
index 0d7d288..959b373 100644
--- a/.settings/stm32cubeide.project.prefs
+++ b/.settings/stm32cubeide.project.prefs
@@ -1,5 +1,5 @@
 635E684B79701B039C64EA45C3F84D30=44DBEC1DE4EBA9B0485911FBE58BFC80
 66BE74F758C12D739921AEA421D593D3=3
-8DF89ED150041C4CBC7CB9A9CAA90856=7B5B92F1162457C6ECACD202698061B0
-DC22A860405A8BF2F2C095E5B6529F12=7B5B92F1162457C6ECACD202698061B0
+8DF89ED150041C4CBC7CB9A9CAA90856=84EF3C290D485BA5E95DA5C0811FD966
+DC22A860405A8BF2F2C095E5B6529F12=84EF3C290D485BA5E95DA5C0811FD966
 eclipse.preferences.version=1
diff --git a/App/Src/test.cpp b/App/Src/test.cpp
index 0abe144..de428a7 100644
--- a/App/Src/test.cpp
+++ b/App/Src/test.cpp
@@ -15,20 +15,34 @@
 
 		sta::STM32CanController canController(handle);
 
-		canController.start();
+		//canController.start();
 
+
+		CAN_TxHeaderTypeDef txHeader;
+		txHeader.DLC = 8;
+		  txHeader.IDE = CAN_ID_STD;
+		  txHeader.RTR = CAN_RTR_DATA;
+		  txHeader.StdId = 0x030;
+		  txHeader.ExtId = 0x02;
+		  txHeader.TransmitGlobalTime = DISABLE;
+
+		  HAL_CAN_Start(handle);
 		// Create a CanTxHeader for your message
-		sta::CanTxHeader txHeader;
-		txHeader.id.format = sta::CanIdFormat::EXT; // Set to EXT for extended ID
-		txHeader.id.eid = 0xCAFE; // Set the standard ID or extended ID
-		txHeader.payloadLength = 8; // Set the payload length (max 8 bytes)
+		/*sta::CanTxHeader txHeader;
+		txHeader.id.format = sta::CanIdFormat::STD; // Set to EXT for extended ID
+		txHeader.id.sid = 0x123; // Set the standard ID or extended ID
+		txHeader.payloadLength = 8; // Set the payload length (max 8 bytes)*/
 
 		// Create your message payload
 		uint8_t payload[8] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08};
 
+		bool okay;
+		uint32_t canMailbox; //CAN Bus Mail box variable
 		// Send the CAN message
 		while (true){
-			canController.sendFrame(txHeader, payload);
+			//okay = canController.sendFrame(txHeader, payload);
+			HAL_CAN_AddTxMessage(handle,&txHeader,payload,&canMailbox);
+			HAL_Delay(1000);
 		}
 
 	}
diff --git a/CAN-Card_Module_Software Debug.launch b/CAN-Card_Module_Software Debug.launch
new file mode 100644
index 0000000..adfcf07
--- /dev/null
+++ b/CAN-Card_Module_Software Debug.launch	
@@ -0,0 +1,83 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<launchConfiguration type="com.st.stm32cube.ide.mcu.debug.launch.launchConfigurationType">
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.access_port_id" value="0"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.cubeprog_external_loaders" value="[]"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.debug_auth_certif_path" value=""/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.debug_auth_check_enable" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.debug_auth_key_path" value=""/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.debug_auth_permission" value="debug_non_secure_L3"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_live_expr" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.enable_swv" value="false"/>
+    <intAttribute key="com.st.stm32cube.ide.mcu.debug.launch.formatVersion" value="2"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.ip_address_local" value="localhost"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.limit_swo_clock.enabled" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.limit_swo_clock.value" value=""/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.loadList" value="{&quot;fItems&quot;:[{&quot;fIsFromMainTab&quot;:true,&quot;fPath&quot;:&quot;Debug/CAN-Card_Module_Software.elf&quot;,&quot;fProjectName&quot;:&quot;CAN-Card_Module_Software&quot;,&quot;fPerformBuild&quot;:true,&quot;fDownload&quot;:true,&quot;fLoadSymbols&quot;:true}]}"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.override_start_address_mode" value="default"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.remoteCommand" value="target remote"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startServer" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.exception.divby0" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.exception.unaligned" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.startuptab.haltonexception" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swd_mode" value="true"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_port" value="61235"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.swv_trace_hclk" value="16000000"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.useRemoteTarget" value="true"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.launch.vector_table" value=""/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.launch.verify_flash_download" value="true"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.cti_allow_halt" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.cti_signal_halt" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_logging" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_max_halt_delay" value="false"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.enable_shared_stlink" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.frequency" value="100"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.halt_all_on_reset" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.log_file" value="/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Debug/st-link_gdbserver_log.txt"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.low_power_debug" value="enable"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.max_halt_delay" value="2"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.reset_strategy" value="connect_under_reset"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_check_serial_number" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.stlink_txt_serial_number" value=""/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlink.watchdog_config" value="none"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.debug.stlinkenable_rtos" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.debug.stlinkrestart_configurations" value="{&quot;fVersion&quot;:1,&quot;fItems&quot;:[{&quot;fDisplayName&quot;:&quot;Reset&quot;,&quot;fIsSuppressible&quot;:false,&quot;fResetAttribute&quot;:&quot;Software system reset&quot;,&quot;fResetStrategies&quot;:[{&quot;fDisplayName&quot;:&quot;Software system reset&quot;,&quot;fLaunchAttribute&quot;:&quot;system_reset&quot;,&quot;fGdbCommands&quot;:[&quot;monitor reset\n&quot;],&quot;fCmdOptions&quot;:[&quot;-g&quot;]},{&quot;fDisplayName&quot;:&quot;Hardware reset&quot;,&quot;fLaunchAttribute&quot;:&quot;hardware_reset&quot;,&quot;fGdbCommands&quot;:[&quot;monitor reset hardware\n&quot;],&quot;fCmdOptions&quot;:[&quot;-g&quot;]},{&quot;fDisplayName&quot;:&quot;Core reset&quot;,&quot;fLaunchAttribute&quot;:&quot;core_reset&quot;,&quot;fGdbCommands&quot;:[&quot;monitor reset core\n&quot;],&quot;fCmdOptions&quot;:[&quot;-g&quot;]},{&quot;fDisplayName&quot;:&quot;None&quot;,&quot;fLaunchAttribute&quot;:&quot;no_reset&quot;,&quot;fGdbCommands&quot;:[],&quot;fCmdOptions&quot;:[&quot;-g&quot;]}],&quot;fGdbCommandGroup&quot;:{&quot;name&quot;:&quot;Additional commands&quot;,&quot;commands&quot;:[]},&quot;fStartApplication&quot;:true}]}"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.enableRtosProxy" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyCustomProperties" value=""/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriver" value="threadx"/>
+    <booleanAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriverAuto" value="false"/>
+    <stringAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyDriverPort" value="cortex_m0"/>
+    <intAttribute key="com.st.stm32cube.ide.mcu.rtosproxy.rtosProxyPort" value="60000"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="false"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value=""/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDeviceId" value="com.st.stm32cube.ide.mcu.debug.stlink"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
+    <intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="61234"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
+    <booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="false"/>
+    <booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
+    <intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
+    <stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
+    <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="remote"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="Debug/CAN-Card_Module_Software.elf"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="CAN-Card_Module_Software"/>
+    <booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
+    <stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1763458346"/>
+    <booleanAttribute key="org.eclipse.debug.core.ATTR_FORCE_SYSTEM_CONSOLE_ENCODING" value="false"/>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
+        <listEntry value="/CAN-Card_Module_Software"/>
+    </listAttribute>
+    <listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
+        <listEntry value="4"/>
+    </listAttribute>
+    <stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&lt;memoryBlockExpressionList context=&quot;reserved-for-future-use&quot;/&gt;"/>
+    <stringAttribute key="process_factory_id" value="com.st.stm32cube.ide.mcu.debug.launch.HardwareDebugProcessFactory"/>
+</launchConfiguration>
diff --git a/can-tests.ioc b/CAN-Card_Module_Software.ioc
similarity index 61%
rename from can-tests.ioc
rename to CAN-Card_Module_Software.ioc
index 0f28f64..5650f82 100644
--- a/can-tests.ioc
+++ b/CAN-Card_Module_Software.ioc
@@ -3,53 +3,49 @@ CAD.formats=
 CAD.pinconfig=
 CAD.provider=
 CAN1.BS1=CAN_BS1_2TQ
-CAN1.CalculateBaudRate=500000
-CAN1.CalculateTimeBit=2000
+CAN1.BS2=CAN_BS2_7TQ
+CAN1.CalculateBaudRate=200000
+CAN1.CalculateTimeBit=5000
 CAN1.CalculateTimeQuantum=500.0
-CAN1.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,Prescaler,SJW,BS1,NART
+CAN1.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,Prescaler,SJW,NART,BS2,BS1
 CAN1.NART=ENABLE
 CAN1.Prescaler=8
 CAN1.SJW=CAN_SJW_1TQ
-CAN2.BS1=CAN_BS1_2TQ
-CAN2.CalculateBaudRate=500000
-CAN2.CalculateTimeBit=2000
-CAN2.CalculateTimeQuantum=500.0
-CAN2.IPParameters=CalculateTimeQuantum,CalculateTimeBit,CalculateBaudRate,Prescaler,BS1,NART
-CAN2.NART=ENABLE
-CAN2.Prescaler=8
 File.Version=6
 KeepUserPlacement=false
 Mcu.CPN=STM32F407ZGT6
 Mcu.Family=STM32F4
 Mcu.IP0=CAN1
-Mcu.IP1=CAN2
-Mcu.IP2=NVIC
-Mcu.IP3=RCC
-Mcu.IP4=UART4
-Mcu.IPNb=5
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=UART4
+Mcu.IPNb=4
 Mcu.Name=STM32F407Z(E-G)Tx
 Mcu.Package=LQFP144
-Mcu.Pin0=PA0-WKUP
-Mcu.Pin1=PA1
-Mcu.Pin10=PC11
-Mcu.Pin11=PC12
-Mcu.Pin12=PB3
-Mcu.Pin13=PB5
-Mcu.Pin2=PB12
-Mcu.Pin3=PB13
-Mcu.Pin4=PA11
-Mcu.Pin5=PA12
-Mcu.Pin6=PA13
-Mcu.Pin7=PA14
-Mcu.Pin8=PA15
-Mcu.Pin9=PC10
-Mcu.PinsNb=14
+Mcu.Pin0=PH0-OSC_IN
+Mcu.Pin1=PH1-OSC_OUT
+Mcu.Pin10=PA14
+Mcu.Pin11=PA15
+Mcu.Pin12=PC10
+Mcu.Pin13=PC11
+Mcu.Pin14=PC12
+Mcu.Pin15=PB3
+Mcu.Pin2=PA0-WKUP
+Mcu.Pin3=PA1
+Mcu.Pin4=PB12
+Mcu.Pin5=PB13
+Mcu.Pin6=PD8
+Mcu.Pin7=PA11
+Mcu.Pin8=PA12
+Mcu.Pin9=PA13
+Mcu.PinsNb=16
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32F407ZGTx
 MxCube.Version=6.9.2
 MxDb.Version=DB.6.0.92
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.CAN1_RX0_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.ForceEnableDMAVector=true
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
@@ -77,22 +73,30 @@ PA14.Signal=SYS_JTCK-SWCLK
 PA15.Locked=true
 PA15.Signal=SYS_JTDI
 PB12.GPIOParameters=GPIO_Speed,PinState
-PB12.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
+PB12.GPIO_Speed=GPIO_SPEED_FREQ_LOW
 PB12.Locked=true
 PB12.PinState=GPIO_PIN_RESET
 PB12.Signal=GPIO_Output
-PB13.Mode=CAN_Activate
-PB13.Signal=CAN2_TX
+PB13.GPIOParameters=PinState
+PB13.Locked=true
+PB13.PinState=GPIO_PIN_RESET
+PB13.Signal=GPIO_Output
 PB3.Locked=true
 PB3.Signal=SYS_JTDO-SWO
-PB5.Mode=CAN_Activate
-PB5.Signal=CAN2_RX
 PC10.Locked=true
 PC10.Signal=SPI3_SCK
 PC11.Locked=true
 PC11.Signal=SPI3_MISO
 PC12.Locked=true
 PC12.Signal=SPI3_MOSI
+PD8.Locked=true
+PD8.Signal=GPIO_Output
+PH0-OSC_IN.Locked=true
+PH0-OSC_IN.Mode=HSE-External-Oscillator
+PH0-OSC_IN.Signal=RCC_OSC_IN
+PH1-OSC_OUT.Locked=true
+PH1-OSC_OUT.Mode=HSE-External-Oscillator
+PH1-OSC_OUT.Signal=RCC_OSC_OUT
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
 ProjectManager.BackupPrevious=false
@@ -114,8 +118,8 @@ ProjectManager.MainLocation=Core/Src
 ProjectManager.NoMain=false
 ProjectManager.PreviousToolchain=
 ProjectManager.ProjectBuild=false
-ProjectManager.ProjectFileName=can-tests.ioc
-ProjectManager.ProjectName=can-tests
+ProjectManager.ProjectFileName=CAN-Card_Module_Software.ioc
+ProjectManager.ProjectName=CAN-Card_Module_Software
 ProjectManager.ProjectStructure=
 ProjectManager.RegisterCallBack=
 ProjectManager.StackSize=0x400
@@ -125,26 +129,38 @@ ProjectManager.UAScriptAfterPath=
 ProjectManager.UAScriptBeforePath=
 ProjectManager.UnderRoot=true
 ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_UART4_Init-UART4-false-HAL-true,4-MX_CAN1_Init-CAN1-false-HAL-true
+RCC.48MHZClocksFreq_Value=32000000
+RCC.AHBCLKDivider=RCC_SYSCLK_DIV4
 RCC.AHBFreq_Value=16000000
 RCC.APB1Freq_Value=16000000
+RCC.APB1TimFreq_Value=16000000
 RCC.APB2Freq_Value=16000000
+RCC.APB2TimFreq_Value=16000000
 RCC.CortexFreq_Value=16000000
+RCC.EthernetFreq_Value=16000000
+RCC.FCLKCortexFreq_Value=16000000
 RCC.FamilyName=M
-RCC.HSE_VALUE=25000000
+RCC.HCLKFreq_Value=16000000
+RCC.HSE_VALUE=8000000
 RCC.HSI_VALUE=16000000
-RCC.I2SClocksFreq_Value=96000000
-RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB2Freq_Value,CortexFreq_Value,FamilyName,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,PLLCLKFreq_Value,PLLQCLKFreq_Value,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S
+RCC.I2SClocksFreq_Value=192000000
+RCC.IPParameters=48MHZClocksFreq_Value,AHBCLKDivider,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CortexFreq_Value,EthernetFreq_Value,FCLKCortexFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI_VALUE,I2SClocksFreq_Value,LSE_VALUE,LSI_VALUE,MCO2PinFreq_Value,PLLCLKFreq_Value,PLLM,PLLN,PLLQCLKFreq_Value,PLLSourceVirtual,RTCFreq_Value,RTCHSEDivFreq_Value,SYSCLKFreq_VALUE,SYSCLKSource,VCOI2SOutputFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VcooutputI2S
 RCC.LSE_VALUE=32768
 RCC.LSI_VALUE=32000
-RCC.PLLCLKFreq_Value=96000000
-RCC.PLLQCLKFreq_Value=48000000
+RCC.MCO2PinFreq_Value=64000000
+RCC.PLLCLKFreq_Value=64000000
+RCC.PLLM=4
+RCC.PLLN=64
+RCC.PLLQCLKFreq_Value=32000000
+RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
 RCC.RTCFreq_Value=32000
-RCC.RTCHSEDivFreq_Value=12500000
-RCC.SYSCLKFreq_VALUE=16000000
-RCC.VCOI2SOutputFreq_Value=192000000
-RCC.VCOInputFreq_Value=1000000
-RCC.VCOOutputFreq_Value=192000000
-RCC.VcooutputI2S=96000000
+RCC.RTCHSEDivFreq_Value=4000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.VCOI2SOutputFreq_Value=384000000
+RCC.VCOInputFreq_Value=2000000
+RCC.VCOOutputFreq_Value=128000000
+RCC.VcooutputI2S=192000000
 UART4.IPParameters=VirtualMode
 UART4.VirtualMode=Asynchronous
 board=custom
diff --git a/Core/Inc/main.h b/Core/Inc/main.h
index 34673e2..ea5d7bc 100644
--- a/Core/Inc/main.h
+++ b/Core/Inc/main.h
@@ -1,69 +1,69 @@
-/* USER CODE BEGIN Header */
-/**
-  ******************************************************************************
-  * @file           : main.h
-  * @brief          : Header for main.c file.
-  *                   This file contains the common defines of the application.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2023 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-/* USER CODE END Header */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MAIN_H
-#define __MAIN_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/* Private includes ----------------------------------------------------------*/
-/* USER CODE BEGIN Includes */
-
-/* USER CODE END Includes */
-
-/* Exported types ------------------------------------------------------------*/
-/* USER CODE BEGIN ET */
-
-/* USER CODE END ET */
-
-/* Exported constants --------------------------------------------------------*/
-/* USER CODE BEGIN EC */
-
-/* USER CODE END EC */
-
-/* Exported macro ------------------------------------------------------------*/
-/* USER CODE BEGIN EM */
-
-/* USER CODE END EM */
-
-/* Exported functions prototypes ---------------------------------------------*/
-void Error_Handler(void);
-
-/* USER CODE BEGIN EFP */
-
-/* USER CODE END EFP */
-
-/* Private defines -----------------------------------------------------------*/
-
-/* USER CODE BEGIN Private defines */
-
-/* USER CODE END Private defines */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __MAIN_H */
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.h
+  * @brief          : Header for main.c file.
+  *                   This file contains the common defines of the application.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MAIN_H
+#define __MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void Error_Handler(void);
+
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+/* Private defines -----------------------------------------------------------*/
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MAIN_H */
diff --git a/Core/Inc/stm32f4xx_hal_conf.h b/Core/Inc/stm32f4xx_hal_conf.h
index dc04f1e..c026ca8 100644
--- a/Core/Inc/stm32f4xx_hal_conf.h
+++ b/Core/Inc/stm32f4xx_hal_conf.h
@@ -1,495 +1,495 @@
-/* USER CODE BEGIN Header */
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @brief   HAL configuration template file.
-  *          This file should be copied to the application folder and renamed
-  *          to stm32f4xx_hal_conf.h.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-/* USER CODE END Header */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CONF_H
-#define __STM32F4xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver
-  */
-#define HAL_MODULE_ENABLED
-
-  /* #define HAL_CRYP_MODULE_ENABLED */
-/* #define HAL_ADC_MODULE_ENABLED */
-#define HAL_CAN_MODULE_ENABLED
-/* #define HAL_CRC_MODULE_ENABLED */
-/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
-/* #define HAL_DAC_MODULE_ENABLED */
-/* #define HAL_DCMI_MODULE_ENABLED */
-/* #define HAL_DMA2D_MODULE_ENABLED */
-/* #define HAL_ETH_MODULE_ENABLED */
-/* #define HAL_ETH_LEGACY_MODULE_ENABLED */
-/* #define HAL_NAND_MODULE_ENABLED */
-/* #define HAL_NOR_MODULE_ENABLED */
-/* #define HAL_PCCARD_MODULE_ENABLED */
-/* #define HAL_SRAM_MODULE_ENABLED */
-/* #define HAL_SDRAM_MODULE_ENABLED */
-/* #define HAL_HASH_MODULE_ENABLED */
-/* #define HAL_I2C_MODULE_ENABLED */
-/* #define HAL_I2S_MODULE_ENABLED */
-/* #define HAL_IWDG_MODULE_ENABLED */
-/* #define HAL_LTDC_MODULE_ENABLED */
-/* #define HAL_RNG_MODULE_ENABLED */
-/* #define HAL_RTC_MODULE_ENABLED */
-/* #define HAL_SAI_MODULE_ENABLED */
-/* #define HAL_SD_MODULE_ENABLED */
-/* #define HAL_MMC_MODULE_ENABLED */
-/* #define HAL_SPI_MODULE_ENABLED */
-/* #define HAL_TIM_MODULE_ENABLED */
-#define HAL_UART_MODULE_ENABLED
-/* #define HAL_USART_MODULE_ENABLED */
-/* #define HAL_IRDA_MODULE_ENABLED */
-/* #define HAL_SMARTCARD_MODULE_ENABLED */
-/* #define HAL_SMBUS_MODULE_ENABLED */
-/* #define HAL_WWDG_MODULE_ENABLED */
-/* #define HAL_PCD_MODULE_ENABLED */
-/* #define HAL_HCD_MODULE_ENABLED */
-/* #define HAL_DSI_MODULE_ENABLED */
-/* #define HAL_QSPI_MODULE_ENABLED */
-/* #define HAL_QSPI_MODULE_ENABLED */
-/* #define HAL_CEC_MODULE_ENABLED */
-/* #define HAL_FMPI2C_MODULE_ENABLED */
-/* #define HAL_FMPSMBUS_MODULE_ENABLED */
-/* #define HAL_SPDIFRX_MODULE_ENABLED */
-/* #define HAL_DFSDM_MODULE_ENABLED */
-/* #define HAL_LPTIM_MODULE_ENABLED */
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_EXTI_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-
-/* ########################## HSE/HSI Values adaptation ##################### */
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSE_VALUE)
-  #define HSE_VALUE    25000000U /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    100U   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL).
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief Internal Low Speed oscillator (LSI) value.
-  */
-#if !defined  (LSI_VALUE)
- #define LSI_VALUE  32000U       /*!< LSI Typical Value in Hz*/
-#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
-                                             The real value may vary depending on the variations
-                                             in voltage and temperature.*/
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  */
-#if !defined  (LSE_VALUE)
- #define LSE_VALUE  32768U    /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    5000U   /*!< Time out for LSE start up, in ms */
-#endif /* LSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief External clock source for I2S peripheral
-  *        This value is used by the I2S HAL module to compute the I2S clock source
-  *        frequency, this source is inserted directly through I2S_CKIN pad.
-  */
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External audio frequency in Hz*/
-#endif /* EXTERNAL_CLOCK_VALUE */
-
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */
-#define  VDD_VALUE		      3300U /*!< Value of VDD in mv */
-#define  TICK_INT_PRIORITY            15U   /*!< tick interrupt priority */
-#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     1U
-#define  DATA_CACHE_ENABLE            1U
-
-#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
-#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
-#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
-#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
-#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
-#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
-#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
-#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
-#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
-#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
-#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
-#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
-#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
-#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
-#define  USE_HAL_FMPSMBUS_REGISTER_CALLBACKS    0U /* FMPSMBUS register callback disabled  */
-#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
-#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
-#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
-#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
-#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
-#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
-#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
-#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
-#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
-#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
-#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
-#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
-#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
-#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
-#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
-#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
-#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
-#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
-#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
-#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
-#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
-#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
-#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
-#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the
-  *        HAL drivers code
-  */
-/* #define USE_FULL_ASSERT    1U */
-
-/* ################## Ethernet peripheral configuration ##################### */
-
-/* Section 1 : Ethernet peripheral configuration */
-
-/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
-#define MAC_ADDR0   2U
-#define MAC_ADDR1   0U
-#define MAC_ADDR2   0U
-#define MAC_ADDR3   0U
-#define MAC_ADDR4   0U
-#define MAC_ADDR5   0U
-
-/* Definition of the Ethernet driver buffers size and count */
-#define ETH_RX_BUF_SIZE                 /* buffer size for receive               */
-#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
-#define ETH_RXBUFNB                    4U       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
-#define ETH_TXBUFNB                    4U       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
-
-/* Section 2: PHY configuration section */
-
-/* DP83848_PHY_ADDRESS Address*/
-#define DP83848_PHY_ADDRESS
-/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
-#define PHY_RESET_DELAY                 0x000000FFU
-/* PHY Configuration delay */
-#define PHY_CONFIG_DELAY                0x00000FFFU
-
-#define PHY_READ_TO                     0x0000FFFFU
-#define PHY_WRITE_TO                    0x0000FFFFU
-
-/* Section 3: Common PHY Registers */
-
-#define PHY_BCR                         ((uint16_t)0x0000U)    /*!< Transceiver Basic Control Register   */
-#define PHY_BSR                         ((uint16_t)0x0001U)    /*!< Transceiver Basic Status Register    */
-
-#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
-#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */
-#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */
-#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */
-#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */
-#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */
-#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
-#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */
-#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */
-#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */
-
-#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
-#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
-#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */
-
-/* Section 4: Extended PHY Registers */
-#define PHY_SR                          ((uint16_t))    /*!< PHY status register Offset                      */
-
-#define PHY_SPEED_STATUS                ((uint16_t))  /*!< PHY Speed mask                                  */
-#define PHY_DUPLEX_STATUS               ((uint16_t))  /*!< PHY Duplex mask                                 */
-
-/* ################## SPI peripheral configuration ########################## */
-
-/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
-* Activated: CRC code is present inside driver
-* Deactivated: CRC code cleaned from driver
-*/
-
-#define USE_SPI_CRC                     0U
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-  #include "stm32f4xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-  #include "stm32f4xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-  #include "stm32f4xx_hal_exti.h"
-#endif /* HAL_EXTI_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-  #include "stm32f4xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-  #include "stm32f4xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-  #include "stm32f4xx_hal_can.h"
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #include "stm32f4xx_hal_can_legacy.h"
-#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-  #include "stm32f4xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-  #include "stm32f4xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DMA2D_MODULE_ENABLED
-  #include "stm32f4xx_hal_dma2d.h"
-#endif /* HAL_DMA2D_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
-  #include "stm32f4xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_DCMI_MODULE_ENABLED
-  #include "stm32f4xx_hal_dcmi.h"
-#endif /* HAL_DCMI_MODULE_ENABLED */
-
-#ifdef HAL_ETH_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth.h"
-#endif /* HAL_ETH_MODULE_ENABLED */
-
-#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
-  #include "stm32f4xx_hal_eth_legacy.h"
-#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-  #include "stm32f4xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
-  #include "stm32f4xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */
-
-#ifdef HAL_NAND_MODULE_ENABLED
-  #include "stm32f4xx_hal_nand.h"
-#endif /* HAL_NAND_MODULE_ENABLED */
-
-#ifdef HAL_PCCARD_MODULE_ENABLED
-  #include "stm32f4xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
-#ifdef HAL_SDRAM_MODULE_ENABLED
-  #include "stm32f4xx_hal_sdram.h"
-#endif /* HAL_SDRAM_MODULE_ENABLED */
-
-#ifdef HAL_HASH_MODULE_ENABLED
- #include "stm32f4xx_hal_hash.h"
-#endif /* HAL_HASH_MODULE_ENABLED */
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32f4xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_SMBUS_MODULE_ENABLED
- #include "stm32f4xx_hal_smbus.h"
-#endif /* HAL_SMBUS_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32f4xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LTDC_MODULE_ENABLED
- #include "stm32f4xx_hal_ltdc.h"
-#endif /* HAL_LTDC_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32f4xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RNG_MODULE_ENABLED
- #include "stm32f4xx_hal_rng.h"
-#endif /* HAL_RNG_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32f4xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SAI_MODULE_ENABLED
- #include "stm32f4xx_hal_sai.h"
-#endif /* HAL_SAI_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32f4xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32f4xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32f4xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32f4xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32f4xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32f4xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32f4xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32f4xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32f4xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-
-#ifdef HAL_HCD_MODULE_ENABLED
- #include "stm32f4xx_hal_hcd.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
-
-#ifdef HAL_DSI_MODULE_ENABLED
- #include "stm32f4xx_hal_dsi.h"
-#endif /* HAL_DSI_MODULE_ENABLED */
-
-#ifdef HAL_QSPI_MODULE_ENABLED
- #include "stm32f4xx_hal_qspi.h"
-#endif /* HAL_QSPI_MODULE_ENABLED */
-
-#ifdef HAL_CEC_MODULE_ENABLED
- #include "stm32f4xx_hal_cec.h"
-#endif /* HAL_CEC_MODULE_ENABLED */
-
-#ifdef HAL_FMPI2C_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpi2c.h"
-#endif /* HAL_FMPI2C_MODULE_ENABLED */
-
-#ifdef HAL_FMPSMBUS_MODULE_ENABLED
- #include "stm32f4xx_hal_fmpsmbus.h"
-#endif /* HAL_FMPSMBUS_MODULE_ENABLED */
-
-#ifdef HAL_SPDIFRX_MODULE_ENABLED
- #include "stm32f4xx_hal_spdifrx.h"
-#endif /* HAL_SPDIFRX_MODULE_ENABLED */
-
-#ifdef HAL_DFSDM_MODULE_ENABLED
- #include "stm32f4xx_hal_dfsdm.h"
-#endif /* HAL_DFSDM_MODULE_ENABLED */
-
-#ifdef HAL_LPTIM_MODULE_ENABLED
- #include "stm32f4xx_hal_lptim.h"
-#endif /* HAL_LPTIM_MODULE_ENABLED */
-
-#ifdef HAL_MMC_MODULE_ENABLED
- #include "stm32f4xx_hal_mmc.h"
-#endif /* HAL_MMC_MODULE_ENABLED */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed.
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CONF_H */
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_conf_template.h
+  * @author  MCD Application Team
+  * @brief   HAL configuration template file.
+  *          This file should be copied to the application folder and renamed
+  *          to stm32f4xx_hal_conf.h.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CONF_H
+#define __STM32F4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+  * @brief This is the list of modules to be used in the HAL driver
+  */
+#define HAL_MODULE_ENABLED
+
+  /* #define HAL_CRYP_MODULE_ENABLED */
+/* #define HAL_ADC_MODULE_ENABLED */
+#define HAL_CAN_MODULE_ENABLED
+/* #define HAL_CRC_MODULE_ENABLED */
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
+/* #define HAL_DAC_MODULE_ENABLED */
+/* #define HAL_DCMI_MODULE_ENABLED */
+/* #define HAL_DMA2D_MODULE_ENABLED */
+/* #define HAL_ETH_MODULE_ENABLED */
+/* #define HAL_ETH_LEGACY_MODULE_ENABLED */
+/* #define HAL_NAND_MODULE_ENABLED */
+/* #define HAL_NOR_MODULE_ENABLED */
+/* #define HAL_PCCARD_MODULE_ENABLED */
+/* #define HAL_SRAM_MODULE_ENABLED */
+/* #define HAL_SDRAM_MODULE_ENABLED */
+/* #define HAL_HASH_MODULE_ENABLED */
+/* #define HAL_I2C_MODULE_ENABLED */
+/* #define HAL_I2S_MODULE_ENABLED */
+/* #define HAL_IWDG_MODULE_ENABLED */
+/* #define HAL_LTDC_MODULE_ENABLED */
+/* #define HAL_RNG_MODULE_ENABLED */
+/* #define HAL_RTC_MODULE_ENABLED */
+/* #define HAL_SAI_MODULE_ENABLED */
+/* #define HAL_SD_MODULE_ENABLED */
+/* #define HAL_MMC_MODULE_ENABLED */
+/* #define HAL_SPI_MODULE_ENABLED */
+/* #define HAL_TIM_MODULE_ENABLED */
+#define HAL_UART_MODULE_ENABLED
+/* #define HAL_USART_MODULE_ENABLED */
+/* #define HAL_IRDA_MODULE_ENABLED */
+/* #define HAL_SMARTCARD_MODULE_ENABLED */
+/* #define HAL_SMBUS_MODULE_ENABLED */
+/* #define HAL_WWDG_MODULE_ENABLED */
+/* #define HAL_PCD_MODULE_ENABLED */
+/* #define HAL_HCD_MODULE_ENABLED */
+/* #define HAL_DSI_MODULE_ENABLED */
+/* #define HAL_QSPI_MODULE_ENABLED */
+/* #define HAL_QSPI_MODULE_ENABLED */
+/* #define HAL_CEC_MODULE_ENABLED */
+/* #define HAL_FMPI2C_MODULE_ENABLED */
+/* #define HAL_FMPSMBUS_MODULE_ENABLED */
+/* #define HAL_SPDIFRX_MODULE_ENABLED */
+/* #define HAL_DFSDM_MODULE_ENABLED */
+/* #define HAL_LPTIM_MODULE_ENABLED */
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+
+/* ########################## HSE/HSI Values adaptation ##################### */
+/**
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSE is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSE_VALUE)
+  #define HSE_VALUE    8000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSE_STARTUP_TIMEOUT)
+  #define HSE_STARTUP_TIMEOUT    100U   /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief Internal High Speed oscillator (HSI) value.
+  *        This value is used by the RCC HAL module to compute the system frequency
+  *        (when HSI is used as system clock source, directly or through the PLL).
+  */
+#if !defined  (HSI_VALUE)
+  #define HSI_VALUE    ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+  * @brief Internal Low Speed oscillator (LSI) value.
+  */
+#if !defined  (LSI_VALUE)
+ #define LSI_VALUE  32000U       /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
+                                             The real value may vary depending on the variations
+                                             in voltage and temperature.*/
+/**
+  * @brief External Low Speed oscillator (LSE) value.
+  */
+#if !defined  (LSE_VALUE)
+ #define LSE_VALUE  32768U    /*!< Value of the External Low Speed oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSE_STARTUP_TIMEOUT)
+  #define LSE_STARTUP_TIMEOUT    5000U   /*!< Time out for LSE start up, in ms */
+#endif /* LSE_STARTUP_TIMEOUT */
+
+/**
+  * @brief External clock source for I2S peripheral
+  *        This value is used by the I2S HAL module to compute the I2S clock source
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
+  */
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External audio frequency in Hz*/
+#endif /* EXTERNAL_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+  * @brief This is the HAL system configuration section
+  */
+#define  VDD_VALUE		      3300U /*!< Value of VDD in mv */
+#define  TICK_INT_PRIORITY            15U   /*!< tick interrupt priority */
+#define  USE_RTOS                     0U
+#define  PREFETCH_ENABLE              1U
+#define  INSTRUCTION_CACHE_ENABLE     1U
+#define  DATA_CACHE_ENABLE            1U
+
+#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
+#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
+#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
+#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
+#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
+#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
+#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
+#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
+#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
+#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
+#define  USE_HAL_FMPSMBUS_REGISTER_CALLBACKS    0U /* FMPSMBUS register callback disabled  */
+#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
+#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
+#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
+#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
+#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
+#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
+#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
+#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
+#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
+#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
+#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
+#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
+#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
+
+/* ########################## Assert Selection ############################## */
+/**
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
+  *        HAL drivers code
+  */
+/* #define USE_FULL_ASSERT    1U */
+
+/* ################## Ethernet peripheral configuration ##################### */
+
+/* Section 1 : Ethernet peripheral configuration */
+
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
+#define MAC_ADDR0   2U
+#define MAC_ADDR1   0U
+#define MAC_ADDR2   0U
+#define MAC_ADDR3   0U
+#define MAC_ADDR4   0U
+#define MAC_ADDR5   0U
+
+/* Definition of the Ethernet driver buffers size and count */
+#define ETH_RX_BUF_SIZE                 /* buffer size for receive               */
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
+#define ETH_RXBUFNB                    4U       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
+#define ETH_TXBUFNB                    4U       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
+
+/* Section 2: PHY configuration section */
+
+/* DP83848_PHY_ADDRESS Address*/
+#define DP83848_PHY_ADDRESS
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
+#define PHY_RESET_DELAY                 0x000000FFU
+/* PHY Configuration delay */
+#define PHY_CONFIG_DELAY                0x00000FFFU
+
+#define PHY_READ_TO                     0x0000FFFFU
+#define PHY_WRITE_TO                    0x0000FFFFU
+
+/* Section 3: Common PHY Registers */
+
+#define PHY_BCR                         ((uint16_t)0x0000U)    /*!< Transceiver Basic Control Register   */
+#define PHY_BSR                         ((uint16_t)0x0001U)    /*!< Transceiver Basic Status Register    */
+
+#define PHY_RESET                       ((uint16_t)0x8000U)  /*!< PHY Reset */
+#define PHY_LOOPBACK                    ((uint16_t)0x4000U)  /*!< Select loop-back mode */
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100U)  /*!< Set the full-duplex mode at 100 Mb/s */
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000U)  /*!< Set the half-duplex mode at 100 Mb/s */
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100U)  /*!< Set the full-duplex mode at 10 Mb/s  */
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000U)  /*!< Set the half-duplex mode at 10 Mb/s  */
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000U)  /*!< Enable auto-negotiation function     */
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200U)  /*!< Restart auto-negotiation function    */
+#define PHY_POWERDOWN                   ((uint16_t)0x0800U)  /*!< Select the power down mode           */
+#define PHY_ISOLATE                     ((uint16_t)0x0400U)  /*!< Isolate PHY from MII                 */
+
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020U)  /*!< Auto-Negotiation process completed   */
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004U)  /*!< Valid link established               */
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002U)  /*!< Jabber condition detected            */
+
+/* Section 4: Extended PHY Registers */
+#define PHY_SR                          ((uint16_t))    /*!< PHY status register Offset                      */
+
+#define PHY_SPEED_STATUS                ((uint16_t))  /*!< PHY Speed mask                                  */
+#define PHY_DUPLEX_STATUS               ((uint16_t))  /*!< PHY Duplex mask                                 */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+* Activated: CRC code is present inside driver
+* Deactivated: CRC code cleaned from driver
+*/
+
+#define USE_SPI_CRC                     0U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+  * @brief Include module's header file
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+  #include "stm32f4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+  #include "stm32f4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+  #include "stm32f4xx_hal_exti.h"
+#endif /* HAL_EXTI_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+  #include "stm32f4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+  #include "stm32f4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+  #include "stm32f4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+  #include "stm32f4xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+  #include "stm32f4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+  #include "stm32f4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DMA2D_MODULE_ENABLED
+  #include "stm32f4xx_hal_dma2d.h"
+#endif /* HAL_DMA2D_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+  #include "stm32f4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_DCMI_MODULE_ENABLED
+  #include "stm32f4xx_hal_dcmi.h"
+#endif /* HAL_DCMI_MODULE_ENABLED */
+
+#ifdef HAL_ETH_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth.h"
+#endif /* HAL_ETH_MODULE_ENABLED */
+
+#ifdef HAL_ETH_LEGACY_MODULE_ENABLED
+  #include "stm32f4xx_hal_eth_legacy.h"
+#endif /* HAL_ETH_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+  #include "stm32f4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+  #include "stm32f4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+  #include "stm32f4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_PCCARD_MODULE_ENABLED
+  #include "stm32f4xx_hal_pccard.h"
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
+#ifdef HAL_SDRAM_MODULE_ENABLED
+  #include "stm32f4xx_hal_sdram.h"
+#endif /* HAL_SDRAM_MODULE_ENABLED */
+
+#ifdef HAL_HASH_MODULE_ENABLED
+ #include "stm32f4xx_hal_hash.h"
+#endif /* HAL_HASH_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_I2S_MODULE_ENABLED
+ #include "stm32f4xx_hal_i2s.h"
+#endif /* HAL_I2S_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LTDC_MODULE_ENABLED
+ #include "stm32f4xx_hal_ltdc.h"
+#endif /* HAL_LTDC_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32f4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32f4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32f4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32f4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32f4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32f4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32f4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32f4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32f4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32f4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32f4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+#ifdef HAL_DSI_MODULE_ENABLED
+ #include "stm32f4xx_hal_dsi.h"
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32f4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_CEC_MODULE_ENABLED
+ #include "stm32f4xx_hal_cec.h"
+#endif /* HAL_CEC_MODULE_ENABLED */
+
+#ifdef HAL_FMPI2C_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpi2c.h"
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
+
+#ifdef HAL_FMPSMBUS_MODULE_ENABLED
+ #include "stm32f4xx_hal_fmpsmbus.h"
+#endif /* HAL_FMPSMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
+ #include "stm32f4xx_hal_spdifrx.h"
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32f4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+ #include "stm32f4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_MMC_MODULE_ENABLED
+ #include "stm32f4xx_hal_mmc.h"
+#endif /* HAL_MMC_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed.
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CONF_H */
diff --git a/Core/Inc/stm32f4xx_it.h b/Core/Inc/stm32f4xx_it.h
index 37f04b4..f4ba1b9 100644
--- a/Core/Inc/stm32f4xx_it.h
+++ b/Core/Inc/stm32f4xx_it.h
@@ -1,66 +1,67 @@
-/* USER CODE BEGIN Header */
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_it.h
-  * @brief   This file contains the headers of the interrupt handlers.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2023 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
- ******************************************************************************
-  */
-/* USER CODE END Header */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_IT_H
-#define __STM32F4xx_IT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Private includes ----------------------------------------------------------*/
-/* USER CODE BEGIN Includes */
-
-/* USER CODE END Includes */
-
-/* Exported types ------------------------------------------------------------*/
-/* USER CODE BEGIN ET */
-
-/* USER CODE END ET */
-
-/* Exported constants --------------------------------------------------------*/
-/* USER CODE BEGIN EC */
-
-/* USER CODE END EC */
-
-/* Exported macro ------------------------------------------------------------*/
-/* USER CODE BEGIN EM */
-
-/* USER CODE END EM */
-
-/* Exported functions prototypes ---------------------------------------------*/
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void MemManage_Handler(void);
-void BusFault_Handler(void);
-void UsageFault_Handler(void);
-void SVC_Handler(void);
-void DebugMon_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-/* USER CODE BEGIN EFP */
-
-/* USER CODE END EFP */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_IT_H */
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_it.h
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+ ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_IT_H
+#define __STM32F4xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Exported types ------------------------------------------------------------*/
+/* USER CODE BEGIN ET */
+
+/* USER CODE END ET */
+
+/* Exported constants --------------------------------------------------------*/
+/* USER CODE BEGIN EC */
+
+/* USER CODE END EC */
+
+/* Exported macro ------------------------------------------------------------*/
+/* USER CODE BEGIN EM */
+
+/* USER CODE END EM */
+
+/* Exported functions prototypes ---------------------------------------------*/
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+void CAN1_RX0_IRQHandler(void);
+/* USER CODE BEGIN EFP */
+
+/* USER CODE END EFP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_IT_H */
diff --git a/Core/Src/main.c b/Core/Src/main.c
index 175eed6..4a706b7 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -1,335 +1,358 @@
-/* USER CODE BEGIN Header */
-/**
-  ******************************************************************************
-  * @file           : main.c
-  * @brief          : Main program body
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2023 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-/* USER CODE END Header */
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-
-/* Private includes ----------------------------------------------------------*/
-/* USER CODE BEGIN Includes */
-//#include <sta/devices/stm32/can.hpp>
-extern void testCan(CAN_HandleTypeDef * handle);
-/* USER CODE END Includes */
-
-/* Private typedef -----------------------------------------------------------*/
-/* USER CODE BEGIN PTD */
-
-/* USER CODE END PTD */
-
-/* Private define ------------------------------------------------------------*/
-/* USER CODE BEGIN PD */
-/* USER CODE END PD */
-
-/* Private macro -------------------------------------------------------------*/
-/* USER CODE BEGIN PM */
-
-/* USER CODE END PM */
-
-/* Private variables ---------------------------------------------------------*/
-CAN_HandleTypeDef hcan1;
-CAN_HandleTypeDef hcan2;
-
-UART_HandleTypeDef huart4;
-
-/* USER CODE BEGIN PV */
-
-/* USER CODE END PV */
-
-/* Private function prototypes -----------------------------------------------*/
-void SystemClock_Config(void);
-static void MX_GPIO_Init(void);
-static void MX_UART4_Init(void);
-static void MX_CAN1_Init(void);
-static void MX_CAN2_Init(void);
-/* USER CODE BEGIN PFP */
-
-/* USER CODE END PFP */
-
-/* Private user code ---------------------------------------------------------*/
-/* USER CODE BEGIN 0 */
-
-/* USER CODE END 0 */
-
-/**
-  * @brief  The application entry point.
-  * @retval int
-  */
-int main(void)
-{
-  /* USER CODE BEGIN 1 */
-
-  /* USER CODE END 1 */
-
-  /* MCU Configuration--------------------------------------------------------*/
-
-  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
-  HAL_Init();
-
-  /* USER CODE BEGIN Init */
-
-  /* USER CODE END Init */
-
-  /* Configure the system clock */
-  SystemClock_Config();
-
-  /* USER CODE BEGIN SysInit */
-
-  /* USER CODE END SysInit */
-
-  /* Initialize all configured peripherals */
-  MX_GPIO_Init();
-  MX_UART4_Init();
-  MX_CAN1_Init();
-  MX_CAN2_Init();
-  /* USER CODE BEGIN 2 */
-  testCan(&hcan2);
-  HAL_GPIO_TogglePin(GPIOB,GPIO_PIN_12);
-  /* USER CODE END 2 */
-
-  /* Infinite loop */
-  /* USER CODE BEGIN WHILE */
-  while (1)
-  {
-    /* USER CODE END WHILE */
-
-    /* USER CODE BEGIN 3 */
-
-  }
-  /* USER CODE END 3 */
-}
-
-/**
-  * @brief System Clock Configuration
-  * @retval None
-  */
-void SystemClock_Config(void)
-{
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
-
-  /** Configure the main internal regulator output voltage
-  */
-  __HAL_RCC_PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-
-  /** Initializes the RCC Oscillators according to the specified parameters
-  * in the RCC_OscInitTypeDef structure.
-  */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    Error_Handler();
-  }
-
-  /** Initializes the CPU, AHB and APB buses clocks
-  */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
-                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
-  {
-    Error_Handler();
-  }
-}
-
-/**
-  * @brief CAN1 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_CAN1_Init(void)
-{
-
-  /* USER CODE BEGIN CAN1_Init 0 */
-
-  /* USER CODE END CAN1_Init 0 */
-
-  /* USER CODE BEGIN CAN1_Init 1 */
-
-  /* USER CODE END CAN1_Init 1 */
-  hcan1.Instance = CAN1;
-  hcan1.Init.Prescaler = 8;
-  hcan1.Init.Mode = CAN_MODE_NORMAL;
-  hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ;
-  hcan1.Init.TimeSeg1 = CAN_BS1_2TQ;
-  hcan1.Init.TimeSeg2 = CAN_BS2_1TQ;
-  hcan1.Init.TimeTriggeredMode = DISABLE;
-  hcan1.Init.AutoBusOff = DISABLE;
-  hcan1.Init.AutoWakeUp = DISABLE;
-  hcan1.Init.AutoRetransmission = ENABLE;
-  hcan1.Init.ReceiveFifoLocked = DISABLE;
-  hcan1.Init.TransmitFifoPriority = DISABLE;
-  if (HAL_CAN_Init(&hcan1) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN CAN1_Init 2 */
-
-  /* USER CODE END CAN1_Init 2 */
-
-}
-
-/**
-  * @brief CAN2 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_CAN2_Init(void)
-{
-
-  /* USER CODE BEGIN CAN2_Init 0 */
-
-  /* USER CODE END CAN2_Init 0 */
-
-  /* USER CODE BEGIN CAN2_Init 1 */
-
-  /* USER CODE END CAN2_Init 1 */
-  hcan2.Instance = CAN2;
-  hcan2.Init.Prescaler = 8;
-  hcan2.Init.Mode = CAN_MODE_NORMAL;
-  hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ;
-  hcan2.Init.TimeSeg1 = CAN_BS1_2TQ;
-  hcan2.Init.TimeSeg2 = CAN_BS2_1TQ;
-  hcan2.Init.TimeTriggeredMode = DISABLE;
-  hcan2.Init.AutoBusOff = DISABLE;
-  hcan2.Init.AutoWakeUp = DISABLE;
-  hcan2.Init.AutoRetransmission = ENABLE;
-  hcan2.Init.ReceiveFifoLocked = DISABLE;
-  hcan2.Init.TransmitFifoPriority = DISABLE;
-  if (HAL_CAN_Init(&hcan2) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN CAN2_Init 2 */
-
-  /* USER CODE END CAN2_Init 2 */
-
-}
-
-/**
-  * @brief UART4 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_UART4_Init(void)
-{
-
-  /* USER CODE BEGIN UART4_Init 0 */
-
-  /* USER CODE END UART4_Init 0 */
-
-  /* USER CODE BEGIN UART4_Init 1 */
-
-  /* USER CODE END UART4_Init 1 */
-  huart4.Instance = UART4;
-  huart4.Init.BaudRate = 115200;
-  huart4.Init.WordLength = UART_WORDLENGTH_8B;
-  huart4.Init.StopBits = UART_STOPBITS_1;
-  huart4.Init.Parity = UART_PARITY_NONE;
-  huart4.Init.Mode = UART_MODE_TX_RX;
-  huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
-  huart4.Init.OverSampling = UART_OVERSAMPLING_16;
-  if (HAL_UART_Init(&huart4) != HAL_OK)
-  {
-    Error_Handler();
-  }
-  /* USER CODE BEGIN UART4_Init 2 */
-
-  /* USER CODE END UART4_Init 2 */
-
-}
-
-/**
-  * @brief GPIO Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_GPIO_Init(void)
-{
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
-/* USER CODE BEGIN MX_GPIO_Init_1 */
-/* USER CODE END MX_GPIO_Init_1 */
-
-  /* GPIO Ports Clock Enable */
-  __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOB_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
-
-  /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET);
-
-  /*Configure GPIO pin : PB12 */
-  GPIO_InitStruct.Pin = GPIO_PIN_12;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
-  /*Configure GPIO pins : PC10 PC11 PC12 */
-  GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-  GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
-  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
-
-/* USER CODE BEGIN MX_GPIO_Init_2 */
-/* USER CODE END MX_GPIO_Init_2 */
-}
-
-/* USER CODE BEGIN 4 */
-
-/* USER CODE END 4 */
-
-/**
-  * @brief  This function is executed in case of error occurrence.
-  * @retval None
-  */
-void Error_Handler(void)
-{
-  /* USER CODE BEGIN Error_Handler_Debug */
-  /* User can add his own implementation to report the HAL error return state */
-  __disable_irq();
-  while (1)
-  {
-  }
-  /* USER CODE END Error_Handler_Debug */
-}
-
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  Reports the name of the source file and the source line number
-  *         where the assert_param error has occurred.
-  * @param  file: pointer to the source file name
-  * @param  line: assert_param error line source number
-  * @retval None
-  */
-void assert_failed(uint8_t *file, uint32_t line)
-{
-  /* USER CODE BEGIN 6 */
-  /* User can add his own implementation to report the file name and line number,
-     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
-  /* USER CODE END 6 */
-}
-#endif /* USE_FULL_ASSERT */
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file           : main.c
+  * @brief          : Main program body
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+//#include <sta/devices/stm32/can.hpp>
+extern void testCan(CAN_HandleTypeDef * handle);
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN PTD */
+
+/* USER CODE END PTD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+CAN_RxHeaderTypeDef rxHeader; //CAN Bus Transmit Header
+CAN_TxHeaderTypeDef txHeader; //CAN Bus Receive Header
+uint8_t canRX[8] = {0,0,0,0,0,0,0,0};  //CAN Bus Receive Buffer
+CAN_FilterTypeDef canfil; //CAN Bus Filter
+uint32_t canMailbox; //CAN Bus Mail box variable
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+CAN_HandleTypeDef hcan1;
+
+UART_HandleTypeDef huart4;
+
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+void SystemClock_Config(void);
+static void MX_GPIO_Init(void);
+static void MX_UART4_Init(void);
+static void MX_CAN1_Init(void);
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/**
+  * @brief  The application entry point.
+  * @retval int
+  */
+int main(void)
+{
+  /* USER CODE BEGIN 1 */
+
+  /* USER CODE END 1 */
+
+  /* MCU Configuration--------------------------------------------------------*/
+
+  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
+  HAL_Init();
+
+  /* USER CODE BEGIN Init */
+
+  /* USER CODE END Init */
+
+  /* Configure the system clock */
+  SystemClock_Config();
+
+  /* USER CODE BEGIN SysInit */
+
+  /* USER CODE END SysInit */
+
+  /* Initialize all configured peripherals */
+  MX_GPIO_Init();
+  MX_UART4_Init();
+  MX_CAN1_Init();
+  /* USER CODE BEGIN 2 */
+
+  txHeader.DLC = 8;
+  txHeader.IDE = CAN_ID_STD;
+  txHeader.RTR = CAN_RTR_DATA;
+  txHeader.StdId = 0x030;
+  txHeader.ExtId = 0x02;
+  txHeader.TransmitGlobalTime = DISABLE;
+
+  HAL_CAN_ConfigFilter(&hcan1,&canfil);
+  HAL_CAN_Start(&hcan1);
+  //HAL_CAN_ActivateNotification(&hcan1,CAN_IT_RX_FIFO0_MSG_PENDING);
+
+  //HAL_GPIO_WritePin(GPIOB,GPIO_PIN_12, GPIO_PIN_SET);
+  //testCan(&hcan1);
+
+  /* USER CODE END 2 */
+
+  /* Infinite loop */
+  /* USER CODE BEGIN WHILE */
+  while (1)
+  {
+
+	  //HAL_Delay(1);
+	  //HAL_GPIO_WritePin(GPIOB,GPIO_PIN_12, GPIO_PIN_RESET);
+	  //HAL_Delay(100);
+	  //HAL_GPIO_WritePin(GPIOB,GPIO_PIN_12, GPIO_PIN_SET);#
+
+	  HAL_CAN_GetRxMessage(&hcan1, CAN_RX_FIFO0, &rxHeader, canRX);
+	  if (canRX[0] != 0){
+		  HAL_GPIO_TogglePin(GPIOD,GPIO_PIN_8);
+		  		HAL_Delay(1000);
+	  }
+
+	  uint8_t csend[] = {0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08};
+	  HAL_CAN_AddTxMessage(&hcan1,&txHeader,csend,&canMailbox);
+	  /*HAL_GPIO_WritePin(GPIOD,GPIO_PIN_8, GPIO_PIN_RESET);
+	  HAL_Delay(100);
+	  HAL_GPIO_WritePin(GPIOD,GPIO_PIN_8, GPIO_PIN_SET);*/
+	  HAL_Delay(1000);
+    /* USER CODE END WHILE */
+
+    /* USER CODE BEGIN 3 */
+
+  }
+  /* USER CODE END 3 */
+}
+
+/**
+  * @brief System Clock Configuration
+  * @retval None
+  */
+void SystemClock_Config(void)
+{
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+  /** Configure the main internal regulator output voltage
+  */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+
+  /** Initializes the RCC Oscillators according to the specified parameters
+  * in the RCC_OscInitTypeDef structure.
+  */
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = 4;
+  RCC_OscInitStruct.PLL.PLLN = 64;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = 4;
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Initializes the CPU, AHB and APB buses clocks
+  */
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV4;
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+  {
+    Error_Handler();
+  }
+}
+
+/**
+  * @brief CAN1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_CAN1_Init(void)
+{
+
+  /* USER CODE BEGIN CAN1_Init 0 */
+
+  /* USER CODE END CAN1_Init 0 */
+
+  /* USER CODE BEGIN CAN1_Init 1 */
+
+  /* USER CODE END CAN1_Init 1 */
+  hcan1.Instance = CAN1;
+  hcan1.Init.Prescaler = 8;
+  hcan1.Init.Mode = CAN_MODE_NORMAL;
+  hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ;
+  hcan1.Init.TimeSeg1 = CAN_BS1_2TQ;
+  hcan1.Init.TimeSeg2 = CAN_BS2_7TQ;
+  hcan1.Init.TimeTriggeredMode = DISABLE;
+  hcan1.Init.AutoBusOff = DISABLE;
+  hcan1.Init.AutoWakeUp = DISABLE;
+  hcan1.Init.AutoRetransmission = ENABLE;
+  hcan1.Init.ReceiveFifoLocked = DISABLE;
+  hcan1.Init.TransmitFifoPriority = DISABLE;
+  if (HAL_CAN_Init(&hcan1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN CAN1_Init 2 */
+
+  /* USER CODE END CAN1_Init 2 */
+
+}
+
+/**
+  * @brief UART4 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_UART4_Init(void)
+{
+
+  /* USER CODE BEGIN UART4_Init 0 */
+
+  /* USER CODE END UART4_Init 0 */
+
+  /* USER CODE BEGIN UART4_Init 1 */
+
+  /* USER CODE END UART4_Init 1 */
+  huart4.Instance = UART4;
+  huart4.Init.BaudRate = 115200;
+  huart4.Init.WordLength = UART_WORDLENGTH_8B;
+  huart4.Init.StopBits = UART_STOPBITS_1;
+  huart4.Init.Parity = UART_PARITY_NONE;
+  huart4.Init.Mode = UART_MODE_TX_RX;
+  huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart4.Init.OverSampling = UART_OVERSAMPLING_16;
+  if (HAL_UART_Init(&huart4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN UART4_Init 2 */
+
+  /* USER CODE END UART4_Init 2 */
+
+}
+
+/**
+  * @brief GPIO Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_GPIO_Init(void)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+/* USER CODE BEGIN MX_GPIO_Init_1 */
+/* USER CODE END MX_GPIO_Init_1 */
+
+  /* GPIO Ports Clock Enable */
+  __HAL_RCC_GPIOH_CLK_ENABLE();
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12|GPIO_PIN_13, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOD, GPIO_PIN_8, GPIO_PIN_RESET);
+
+  /*Configure GPIO pins : PB12 PB13 */
+  GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : PD8 */
+  GPIO_InitStruct.Pin = GPIO_PIN_8;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : PC10 PC11 PC12 */
+  GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+  GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
+  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+/* USER CODE BEGIN MX_GPIO_Init_2 */
+/* USER CODE END MX_GPIO_Init_2 */
+}
+
+/* USER CODE BEGIN 4 */
+
+void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan1)
+{
+
+	HAL_GPIO_TogglePin(GPIOD,GPIO_PIN_8);
+		HAL_Delay(1000);
+
+	HAL_CAN_GetRxMessage(hcan1, CAN_RX_FIFO0, &rxHeader, canRX);
+
+
+}
+
+/* USER CODE END 4 */
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @retval None
+  */
+void Error_Handler(void)
+{
+  /* USER CODE BEGIN Error_Handler_Debug */
+  /* User can add his own implementation to report the HAL error return state */
+  __disable_irq();
+  while (1)
+  {
+  }
+  /* USER CODE END Error_Handler_Debug */
+}
+
+#ifdef  USE_FULL_ASSERT
+/**
+  * @brief  Reports the name of the source file and the source line number
+  *         where the assert_param error has occurred.
+  * @param  file: pointer to the source file name
+  * @param  line: assert_param error line source number
+  * @retval None
+  */
+void assert_failed(uint8_t *file, uint32_t line)
+{
+  /* USER CODE BEGIN 6 */
+  /* User can add his own implementation to report the file name and line number,
+     ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
+  /* USER CODE END 6 */
+}
+#endif /* USE_FULL_ASSERT */
diff --git a/Core/Src/stm32f4xx_hal_msp.c b/Core/Src/stm32f4xx_hal_msp.c
index 4fe53bd..7737668 100644
--- a/Core/Src/stm32f4xx_hal_msp.c
+++ b/Core/Src/stm32f4xx_hal_msp.c
@@ -1,270 +1,217 @@
-/* USER CODE BEGIN Header */
-/**
-  ******************************************************************************
-  * @file         stm32f4xx_hal_msp.c
-  * @brief        This file provides code for the MSP Initialization
-  *               and de-Initialization codes.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2023 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-/* USER CODE END Header */
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-
-/* USER CODE BEGIN Includes */
-
-/* USER CODE END Includes */
-
-/* Private typedef -----------------------------------------------------------*/
-/* USER CODE BEGIN TD */
-
-/* USER CODE END TD */
-
-/* Private define ------------------------------------------------------------*/
-/* USER CODE BEGIN Define */
-
-/* USER CODE END Define */
-
-/* Private macro -------------------------------------------------------------*/
-/* USER CODE BEGIN Macro */
-
-/* USER CODE END Macro */
-
-/* Private variables ---------------------------------------------------------*/
-/* USER CODE BEGIN PV */
-
-/* USER CODE END PV */
-
-/* Private function prototypes -----------------------------------------------*/
-/* USER CODE BEGIN PFP */
-
-/* USER CODE END PFP */
-
-/* External functions --------------------------------------------------------*/
-/* USER CODE BEGIN ExternalFunctions */
-
-/* USER CODE END ExternalFunctions */
-
-/* USER CODE BEGIN 0 */
-
-/* USER CODE END 0 */
-/**
-  * Initializes the Global MSP.
-  */
-void HAL_MspInit(void)
-{
-  /* USER CODE BEGIN MspInit 0 */
-
-  /* USER CODE END MspInit 0 */
-
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
-  __HAL_RCC_PWR_CLK_ENABLE();
-
-  /* System interrupt init*/
-
-  /* USER CODE BEGIN MspInit 1 */
-
-  /* USER CODE END MspInit 1 */
-}
-
-static uint32_t HAL_RCC_CAN1_CLK_ENABLED=0;
-
-/**
-* @brief CAN MSP Initialization
-* This function configures the hardware resources used in this example
-* @param hcan: CAN handle pointer
-* @retval None
-*/
-void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
-{
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
-  if(hcan->Instance==CAN1)
-  {
-  /* USER CODE BEGIN CAN1_MspInit 0 */
-
-  /* USER CODE END CAN1_MspInit 0 */
-    /* Peripheral clock enable */
-    HAL_RCC_CAN1_CLK_ENABLED++;
-    if(HAL_RCC_CAN1_CLK_ENABLED==1){
-      __HAL_RCC_CAN1_CLK_ENABLE();
-    }
-
-    __HAL_RCC_GPIOA_CLK_ENABLE();
-    /**CAN1 GPIO Configuration
-    PA11     ------> CAN1_RX
-    PA12     ------> CAN1_TX
-    */
-    GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-    GPIO_InitStruct.Alternate = GPIO_AF9_CAN1;
-    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* USER CODE BEGIN CAN1_MspInit 1 */
-
-  /* USER CODE END CAN1_MspInit 1 */
-  }
-  else if(hcan->Instance==CAN2)
-  {
-  /* USER CODE BEGIN CAN2_MspInit 0 */
-
-  /* USER CODE END CAN2_MspInit 0 */
-    /* Peripheral clock enable */
-    __HAL_RCC_CAN2_CLK_ENABLE();
-    HAL_RCC_CAN1_CLK_ENABLED++;
-    if(HAL_RCC_CAN1_CLK_ENABLED==1){
-      __HAL_RCC_CAN1_CLK_ENABLE();
-    }
-
-    __HAL_RCC_GPIOB_CLK_ENABLE();
-    /**CAN2 GPIO Configuration
-    PB13     ------> CAN2_TX
-    PB5     ------> CAN2_RX
-    */
-    GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_5;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-    GPIO_InitStruct.Alternate = GPIO_AF9_CAN2;
-    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-
-  /* USER CODE BEGIN CAN2_MspInit 1 */
-
-  /* USER CODE END CAN2_MspInit 1 */
-  }
-
-}
-
-/**
-* @brief CAN MSP De-Initialization
-* This function freeze the hardware resources used in this example
-* @param hcan: CAN handle pointer
-* @retval None
-*/
-void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
-{
-  if(hcan->Instance==CAN1)
-  {
-  /* USER CODE BEGIN CAN1_MspDeInit 0 */
-
-  /* USER CODE END CAN1_MspDeInit 0 */
-    /* Peripheral clock disable */
-    HAL_RCC_CAN1_CLK_ENABLED--;
-    if(HAL_RCC_CAN1_CLK_ENABLED==0){
-      __HAL_RCC_CAN1_CLK_DISABLE();
-    }
-
-    /**CAN1 GPIO Configuration
-    PA11     ------> CAN1_RX
-    PA12     ------> CAN1_TX
-    */
-    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);
-
-  /* USER CODE BEGIN CAN1_MspDeInit 1 */
-
-  /* USER CODE END CAN1_MspDeInit 1 */
-  }
-  else if(hcan->Instance==CAN2)
-  {
-  /* USER CODE BEGIN CAN2_MspDeInit 0 */
-
-  /* USER CODE END CAN2_MspDeInit 0 */
-    /* Peripheral clock disable */
-    __HAL_RCC_CAN2_CLK_DISABLE();
-    HAL_RCC_CAN1_CLK_ENABLED--;
-    if(HAL_RCC_CAN1_CLK_ENABLED==0){
-      __HAL_RCC_CAN1_CLK_DISABLE();
-    }
-
-    /**CAN2 GPIO Configuration
-    PB13     ------> CAN2_TX
-    PB5     ------> CAN2_RX
-    */
-    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13|GPIO_PIN_5);
-
-  /* USER CODE BEGIN CAN2_MspDeInit 1 */
-
-  /* USER CODE END CAN2_MspDeInit 1 */
-  }
-
-}
-
-/**
-* @brief UART MSP Initialization
-* This function configures the hardware resources used in this example
-* @param huart: UART handle pointer
-* @retval None
-*/
-void HAL_UART_MspInit(UART_HandleTypeDef* huart)
-{
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
-  if(huart->Instance==UART4)
-  {
-  /* USER CODE BEGIN UART4_MspInit 0 */
-
-  /* USER CODE END UART4_MspInit 0 */
-    /* Peripheral clock enable */
-    __HAL_RCC_UART4_CLK_ENABLE();
-
-    __HAL_RCC_GPIOA_CLK_ENABLE();
-    /**UART4 GPIO Configuration
-    PA0-WKUP     ------> UART4_TX
-    PA1     ------> UART4_RX
-    */
-    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-    GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
-    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
-
-  /* USER CODE BEGIN UART4_MspInit 1 */
-
-  /* USER CODE END UART4_MspInit 1 */
-  }
-
-}
-
-/**
-* @brief UART MSP De-Initialization
-* This function freeze the hardware resources used in this example
-* @param huart: UART handle pointer
-* @retval None
-*/
-void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
-{
-  if(huart->Instance==UART4)
-  {
-  /* USER CODE BEGIN UART4_MspDeInit 0 */
-
-  /* USER CODE END UART4_MspDeInit 0 */
-    /* Peripheral clock disable */
-    __HAL_RCC_UART4_CLK_DISABLE();
-
-    /**UART4 GPIO Configuration
-    PA0-WKUP     ------> UART4_TX
-    PA1     ------> UART4_RX
-    */
-    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_1);
-
-  /* USER CODE BEGIN UART4_MspDeInit 1 */
-
-  /* USER CODE END UART4_MspDeInit 1 */
-  }
-
-}
-
-/* USER CODE BEGIN 1 */
-
-/* USER CODE END 1 */
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file         stm32f4xx_hal_msp.c
+  * @brief        This file provides code for the MSP Initialization
+  *               and de-Initialization codes.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN Define */
+
+/* USER CODE END Define */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN Macro */
+
+/* USER CODE END Macro */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* External functions --------------------------------------------------------*/
+/* USER CODE BEGIN ExternalFunctions */
+
+/* USER CODE END ExternalFunctions */
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+/**
+  * Initializes the Global MSP.
+  */
+void HAL_MspInit(void)
+{
+  /* USER CODE BEGIN MspInit 0 */
+
+  /* USER CODE END MspInit 0 */
+
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+  __HAL_RCC_PWR_CLK_ENABLE();
+
+  /* System interrupt init*/
+
+  /* USER CODE BEGIN MspInit 1 */
+
+  /* USER CODE END MspInit 1 */
+}
+
+/**
+* @brief CAN MSP Initialization
+* This function configures the hardware resources used in this example
+* @param hcan: CAN handle pointer
+* @retval None
+*/
+void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hcan->Instance==CAN1)
+  {
+  /* USER CODE BEGIN CAN1_MspInit 0 */
+
+  /* USER CODE END CAN1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_CAN1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**CAN1 GPIO Configuration
+    PA11     ------> CAN1_RX
+    PA12     ------> CAN1_TX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF9_CAN1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* CAN1 interrupt Init */
+    HAL_NVIC_SetPriority(CAN1_RX0_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(CAN1_RX0_IRQn);
+  /* USER CODE BEGIN CAN1_MspInit 1 */
+
+  /* USER CODE END CAN1_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief CAN MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param hcan: CAN handle pointer
+* @retval None
+*/
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
+{
+  if(hcan->Instance==CAN1)
+  {
+  /* USER CODE BEGIN CAN1_MspDeInit 0 */
+
+  /* USER CODE END CAN1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_CAN1_CLK_DISABLE();
+
+    /**CAN1 GPIO Configuration
+    PA11     ------> CAN1_RX
+    PA12     ------> CAN1_TX
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11|GPIO_PIN_12);
+
+    /* CAN1 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(CAN1_RX0_IRQn);
+  /* USER CODE BEGIN CAN1_MspDeInit 1 */
+
+  /* USER CODE END CAN1_MspDeInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP Initialization
+* This function configures the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(huart->Instance==UART4)
+  {
+  /* USER CODE BEGIN UART4_MspInit 0 */
+
+  /* USER CODE END UART4_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_UART4_CLK_ENABLE();
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**UART4 GPIO Configuration
+    PA0-WKUP     ------> UART4_TX
+    PA1     ------> UART4_RX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN UART4_MspInit 1 */
+
+  /* USER CODE END UART4_MspInit 1 */
+  }
+
+}
+
+/**
+* @brief UART MSP De-Initialization
+* This function freeze the hardware resources used in this example
+* @param huart: UART handle pointer
+* @retval None
+*/
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==UART4)
+  {
+  /* USER CODE BEGIN UART4_MspDeInit 0 */
+
+  /* USER CODE END UART4_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_UART4_CLK_DISABLE();
+
+    /**UART4 GPIO Configuration
+    PA0-WKUP     ------> UART4_TX
+    PA1     ------> UART4_RX
+    */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_0|GPIO_PIN_1);
+
+  /* USER CODE BEGIN UART4_MspDeInit 1 */
+
+  /* USER CODE END UART4_MspDeInit 1 */
+  }
+
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/stm32f4xx_it.c b/Core/Src/stm32f4xx_it.c
index 1490637..4f4b663 100644
--- a/Core/Src/stm32f4xx_it.c
+++ b/Core/Src/stm32f4xx_it.c
@@ -1,203 +1,217 @@
-/* USER CODE BEGIN Header */
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_it.c
-  * @brief   Interrupt Service Routines.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2023 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-/* USER CODE END Header */
-
-/* Includes ------------------------------------------------------------------*/
-#include "main.h"
-#include "stm32f4xx_it.h"
-/* Private includes ----------------------------------------------------------*/
-/* USER CODE BEGIN Includes */
-/* USER CODE END Includes */
-
-/* Private typedef -----------------------------------------------------------*/
-/* USER CODE BEGIN TD */
-
-/* USER CODE END TD */
-
-/* Private define ------------------------------------------------------------*/
-/* USER CODE BEGIN PD */
-
-/* USER CODE END PD */
-
-/* Private macro -------------------------------------------------------------*/
-/* USER CODE BEGIN PM */
-
-/* USER CODE END PM */
-
-/* Private variables ---------------------------------------------------------*/
-/* USER CODE BEGIN PV */
-
-/* USER CODE END PV */
-
-/* Private function prototypes -----------------------------------------------*/
-/* USER CODE BEGIN PFP */
-
-/* USER CODE END PFP */
-
-/* Private user code ---------------------------------------------------------*/
-/* USER CODE BEGIN 0 */
-
-/* USER CODE END 0 */
-
-/* External variables --------------------------------------------------------*/
-
-/* USER CODE BEGIN EV */
-
-/* USER CODE END EV */
-
-/******************************************************************************/
-/*           Cortex-M4 Processor Interruption and Exception Handlers          */
-/******************************************************************************/
-/**
-  * @brief This function handles Non maskable interrupt.
-  */
-void NMI_Handler(void)
-{
-  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
-
-  /* USER CODE END NonMaskableInt_IRQn 0 */
-  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
-  while (1)
-  {
-  }
-  /* USER CODE END NonMaskableInt_IRQn 1 */
-}
-
-/**
-  * @brief This function handles Hard fault interrupt.
-  */
-void HardFault_Handler(void)
-{
-  /* USER CODE BEGIN HardFault_IRQn 0 */
-
-  /* USER CODE END HardFault_IRQn 0 */
-  while (1)
-  {
-    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
-    /* USER CODE END W1_HardFault_IRQn 0 */
-  }
-}
-
-/**
-  * @brief This function handles Memory management fault.
-  */
-void MemManage_Handler(void)
-{
-  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
-
-  /* USER CODE END MemoryManagement_IRQn 0 */
-  while (1)
-  {
-    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
-    /* USER CODE END W1_MemoryManagement_IRQn 0 */
-  }
-}
-
-/**
-  * @brief This function handles Pre-fetch fault, memory access fault.
-  */
-void BusFault_Handler(void)
-{
-  /* USER CODE BEGIN BusFault_IRQn 0 */
-
-  /* USER CODE END BusFault_IRQn 0 */
-  while (1)
-  {
-    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
-    /* USER CODE END W1_BusFault_IRQn 0 */
-  }
-}
-
-/**
-  * @brief This function handles Undefined instruction or illegal state.
-  */
-void UsageFault_Handler(void)
-{
-  /* USER CODE BEGIN UsageFault_IRQn 0 */
-
-  /* USER CODE END UsageFault_IRQn 0 */
-  while (1)
-  {
-    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
-    /* USER CODE END W1_UsageFault_IRQn 0 */
-  }
-}
-
-/**
-  * @brief This function handles System service call via SWI instruction.
-  */
-void SVC_Handler(void)
-{
-  /* USER CODE BEGIN SVCall_IRQn 0 */
-
-  /* USER CODE END SVCall_IRQn 0 */
-  /* USER CODE BEGIN SVCall_IRQn 1 */
-
-  /* USER CODE END SVCall_IRQn 1 */
-}
-
-/**
-  * @brief This function handles Debug monitor.
-  */
-void DebugMon_Handler(void)
-{
-  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
-
-  /* USER CODE END DebugMonitor_IRQn 0 */
-  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
-
-  /* USER CODE END DebugMonitor_IRQn 1 */
-}
-
-/**
-  * @brief This function handles Pendable request for system service.
-  */
-void PendSV_Handler(void)
-{
-  /* USER CODE BEGIN PendSV_IRQn 0 */
-
-  /* USER CODE END PendSV_IRQn 0 */
-  /* USER CODE BEGIN PendSV_IRQn 1 */
-
-  /* USER CODE END PendSV_IRQn 1 */
-}
-
-/**
-  * @brief This function handles System tick timer.
-  */
-void SysTick_Handler(void)
-{
-  /* USER CODE BEGIN SysTick_IRQn 0 */
-
-  /* USER CODE END SysTick_IRQn 0 */
-  HAL_IncTick();
-  /* USER CODE BEGIN SysTick_IRQn 1 */
-
-  /* USER CODE END SysTick_IRQn 1 */
-}
-
-/******************************************************************************/
-/* STM32F4xx Peripheral Interrupt Handlers                                    */
-/* Add here the Interrupt Handlers for the used peripherals.                  */
-/* For the available peripheral interrupt handler names,                      */
-/* please refer to the startup file (startup_stm32f4xx.s).                    */
-/******************************************************************************/
-
-/* USER CODE BEGIN 1 */
-
-/* USER CODE END 1 */
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_it.c
+  * @brief   Interrupt Service Routines.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+#include "stm32f4xx_it.h"
+/* Private includes ----------------------------------------------------------*/
+/* USER CODE BEGIN Includes */
+/* USER CODE END Includes */
+
+/* Private typedef -----------------------------------------------------------*/
+/* USER CODE BEGIN TD */
+
+/* USER CODE END TD */
+
+/* Private define ------------------------------------------------------------*/
+/* USER CODE BEGIN PD */
+
+/* USER CODE END PD */
+
+/* Private macro -------------------------------------------------------------*/
+/* USER CODE BEGIN PM */
+
+/* USER CODE END PM */
+
+/* Private variables ---------------------------------------------------------*/
+/* USER CODE BEGIN PV */
+
+/* USER CODE END PV */
+
+/* Private function prototypes -----------------------------------------------*/
+/* USER CODE BEGIN PFP */
+
+/* USER CODE END PFP */
+
+/* Private user code ---------------------------------------------------------*/
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+/* External variables --------------------------------------------------------*/
+extern CAN_HandleTypeDef hcan1;
+/* USER CODE BEGIN EV */
+
+/* USER CODE END EV */
+
+/******************************************************************************/
+/*           Cortex-M4 Processor Interruption and Exception Handlers          */
+/******************************************************************************/
+/**
+  * @brief This function handles Non maskable interrupt.
+  */
+void NMI_Handler(void)
+{
+  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
+
+  /* USER CODE END NonMaskableInt_IRQn 0 */
+  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
+  while (1)
+  {
+  }
+  /* USER CODE END NonMaskableInt_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Hard fault interrupt.
+  */
+void HardFault_Handler(void)
+{
+  /* USER CODE BEGIN HardFault_IRQn 0 */
+
+  /* USER CODE END HardFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_HardFault_IRQn 0 */
+    /* USER CODE END W1_HardFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Memory management fault.
+  */
+void MemManage_Handler(void)
+{
+  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
+
+  /* USER CODE END MemoryManagement_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
+    /* USER CODE END W1_MemoryManagement_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Pre-fetch fault, memory access fault.
+  */
+void BusFault_Handler(void)
+{
+  /* USER CODE BEGIN BusFault_IRQn 0 */
+
+  /* USER CODE END BusFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_BusFault_IRQn 0 */
+    /* USER CODE END W1_BusFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles Undefined instruction or illegal state.
+  */
+void UsageFault_Handler(void)
+{
+  /* USER CODE BEGIN UsageFault_IRQn 0 */
+
+  /* USER CODE END UsageFault_IRQn 0 */
+  while (1)
+  {
+    /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
+    /* USER CODE END W1_UsageFault_IRQn 0 */
+  }
+}
+
+/**
+  * @brief This function handles System service call via SWI instruction.
+  */
+void SVC_Handler(void)
+{
+  /* USER CODE BEGIN SVCall_IRQn 0 */
+
+  /* USER CODE END SVCall_IRQn 0 */
+  /* USER CODE BEGIN SVCall_IRQn 1 */
+
+  /* USER CODE END SVCall_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Debug monitor.
+  */
+void DebugMon_Handler(void)
+{
+  /* USER CODE BEGIN DebugMonitor_IRQn 0 */
+
+  /* USER CODE END DebugMonitor_IRQn 0 */
+  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
+
+  /* USER CODE END DebugMonitor_IRQn 1 */
+}
+
+/**
+  * @brief This function handles Pendable request for system service.
+  */
+void PendSV_Handler(void)
+{
+  /* USER CODE BEGIN PendSV_IRQn 0 */
+
+  /* USER CODE END PendSV_IRQn 0 */
+  /* USER CODE BEGIN PendSV_IRQn 1 */
+
+  /* USER CODE END PendSV_IRQn 1 */
+}
+
+/**
+  * @brief This function handles System tick timer.
+  */
+void SysTick_Handler(void)
+{
+  /* USER CODE BEGIN SysTick_IRQn 0 */
+
+  /* USER CODE END SysTick_IRQn 0 */
+  HAL_IncTick();
+  /* USER CODE BEGIN SysTick_IRQn 1 */
+
+  /* USER CODE END SysTick_IRQn 1 */
+}
+
+/******************************************************************************/
+/* STM32F4xx Peripheral Interrupt Handlers                                    */
+/* Add here the Interrupt Handlers for the used peripherals.                  */
+/* For the available peripheral interrupt handler names,                      */
+/* please refer to the startup file (startup_stm32f4xx.s).                    */
+/******************************************************************************/
+
+/**
+  * @brief This function handles CAN1 RX0 interrupts.
+  */
+void CAN1_RX0_IRQHandler(void)
+{
+  /* USER CODE BEGIN CAN1_RX0_IRQn 0 */
+
+  /* USER CODE END CAN1_RX0_IRQn 0 */
+  HAL_CAN_IRQHandler(&hcan1);
+  /* USER CODE BEGIN CAN1_RX0_IRQn 1 */
+
+  /* USER CODE END CAN1_RX0_IRQn 1 */
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Debug/App/Src/subdir.mk b/Debug/App/Src/subdir.mk
index fb49026..9aae30a 100644
--- a/Debug/App/Src/subdir.mk
+++ b/Debug/App/Src/subdir.mk
@@ -16,7 +16,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 App/Src/%.o App/Src/%.su App/Src/%.cyclo: ../App/Src/%.cpp App/Src/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-App-2f-Src
 
diff --git a/Debug/App/Src/test.d b/Debug/App/Src/test.d
index afa82df..bab6b88 100644
--- a/Debug/App/Src/test.d
+++ b/Debug/App/Src/test.d
@@ -1,7 +1,7 @@
 App/Src/test.o: ../App/Src/test.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/can.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/can.hpp \
  ../Core/Inc/sta/config.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
  ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
  ../Core/Inc/stm32f4xx_hal_conf.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
@@ -29,14 +29,14 @@ App/Src/test.o: ../App/Src/test.cpp \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/controller.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/filter.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/id.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/headers.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/iter.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/can.hpp:
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/controller.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/filter.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/id.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/headers.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/iter.hpp
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/can.hpp:
 ../Core/Inc/sta/config.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
 ../Core/Inc/main.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
 ../Core/Inc/stm32f4xx_hal_conf.h:
@@ -65,8 +65,8 @@ C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/controller.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/filter.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/id.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/headers.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/iter.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/controller.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/filter.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/id.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/headers.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/iter.hpp:
diff --git a/Debug/App/Src/test.o b/Debug/App/Src/test.o
index b217029837c50fe0afb6b426f71967bcce6b0adc..fc1ae9f8b692099ff0c8790c98a2463df1433cad 100644
GIT binary patch
delta 135888
zcmY&=2S5}_(C*Cc&Q9FCi<omdv!`dy>GaGwoaxll(>rrI^;|_%k^xjuL=aGdA}AP8
z41kJ?0Yx#OU_ucEL<KP*ysuXO_x{J7(^J(|Usd<?bg1rGH`ku0U3+e=#d;m7-9lxr
z@*fk!msD94T2gtD^OXO&<KMMZRi0(+TTxnG@ttQ~B-E)g^?&Y}I{rUot&5mCng92`
zWt}Sj_g+<J{QtdY>Qq_sKiJN*{vWE7eUUuC=argShkyJ#Ma{o6s`z)#EQIIpEvY=8
zaR?77UNN7P3UZlq4F2kg48t+3hVIQl4b@ETbtkpV3@?#Ui1okzw5+z*K$&6x-o-Gg
z#+80T78|`$&8V6<_s6}~&I+4bi41$nO=MK<oPQ^tikrMv&9L3CfYqV$JO_)<x-2m4
z^4UD28szLkEDiUs1&Tew!5UI|hl9m4?NtmrpdZJmW;#a@OW;0UhhnlPSbtScaIpAx
z`8>nUzM^4N8|>8`E{Ro<?^c6cVq0F(GOE2b$Q3p=7jB2tBp=wuflxSJgN(Diu1kz6
zz9v~^-}<N+)#Vywj{PlCU{t9!$qxJRS76?)?BE~i0p08>4*sZGz<gP`FUv3%jh*{z
z?qY@=oFy}=S5?M=r`7OptHR|9otjZw&8-OPLwlJ~J6pQYeP{=cQP;8zrTgyfB}QG(
zI*so8jba&fQ_E7i|MU*`Ev@djHwFNc)fY32y1gZUGP524tg|(S?z8QGg6L(fLqe;z
zL+DpqbGom-P|K(XSv%7G<(~vbJ=`{k?sL4fjK=1iOv)?9$c)CR@(sFof&op{%9(Wk
zx<6#9Re4GGv17rnUHLuTyAP2VO`R&`bg%xCWi$;dOLhVcF{>C&qbg1gW5vk$xdzn^
zJK4rFnl?45R@l%}xbITa!S}3y;jXnD{B>O*-|q+ivdCzD{my^7Qq5?F)pXSU>v-r6
zuSK;lQFUBYF^oXkJY!dk-2I17HH=mba%BJE4EMkkfh<Nn{|?7+nGQmuP7MO_&_M|5
z1?xaOau5o`_HM~DT$Y+Z0hV)qH_wb9u;B#u;s+QziDkH#Kft1!fyi|bc0qmB0_xTO
zp!o)>7%oq327)4RMf&Ruvw_h14sXS9@4lmfXw7i%zoVgQCW#F9K|L8_)>>-r3tM?0
z&z!@{$q(uU7rxeTl!qTQ0z{dE(C{OP_*Nr=>R(VNXQ&yj+>xcICq4vG;UJ9q{(Xj{
z@(IAI?*kpyaqq0}IdV9oa@<$5eHtk<oSLmcCTnSGj?*w2HVyY{Sk1{0l!ko_;xMaG
zjglEH`xeAa)~W9xIKZ>^@6M?-zW3pX15l&VD3BCcdQ^f+6PY40k|Re^X`GNFJ93OF
z&FWm9Q5-o|m8KSQbdDTnl_sht$LPPir_%g{90Pj{&!?73bB*H}BU=F{x~tF{sQl!s
zqdAOWBx(lau7idEJxTJ|L9^eR4=FonnUUz(7`PvFRi@I(c!}XmtlEe8jvnq@tNJX{
z9wJ;XbPf!+BZ_74pHPg-NLJgcAxA4{J{Gc!^X1n3cO|~z#rguXoRsV)SmQig(PMFJ
zBlI-f!OiFx81`B%Jm9A4p%8Ky5?VxjWtn)=>HCVubs(AH+^e8B<4T{Rqu_!z;br8W
zH9>PhmoP%b2<_}@S7;bXO{peyX>vwjW@yp)k9}krp{qiVfKiWg0nx)jXw<`kK=gJH
zg8KSEjuC!!5Q_RP5x+SIquR(qY_Nq2ZdEt0A~3=*2VqlRe<(A;NC)AhwwHeaHO4_z
zQeW3-7-77Fa8`4&$Osc1L}i9G*+ETFUm-`Gg`Ic0%FH!#^zA{|+2t_GsGB|4GD3iZ
z(D40x_hEz}2O;po(O!iR2chu22lirw{SLxzR4@7h<OqiyE5kl1L$yS!7XZ8R-1{8U
zNVsXNg6dS~2EftuT6E8-%Uh}$;Z9AeDvdfO1ORtyUVv-0)Lv&HcE2XQG4&Xkng+|D
z!i7TheF)2cgI{IQ;^~a!#L6$x|1hc+Q@~TTTu#?kTj|>R5MA4hLW@<k{fDl<tfy<c
zJ#_6*Lb)Avbl<5yT|0N7YuAg!@0LZ^9%M(=)0M8h=pm|lpQLNwsU+F&U%LM4jjLVN
zKaz;wSh^0ZOxHoJ=sLJRU5DNxwPAU<GF2BXp32CwjEBio8(USwRHuv5Mx1_EWLAR7
z>TqFd(5*OzZqc+^)wfCvQ*+o36{E}3{!CepMrC@2CK;x(FGmfLtV2Qko$i{Tip8m<
zFW1DaOwU;+CDZJaDkfM(D*w-h{2ns3h^}3VJJ)Cp;|n4R|LRmZsAksSrfyz!^b~Dc
zI-IH(-d{rVH<Nquc3jwisv^VGCmB}XoMhDA+gIwi0EsbHC3LlS;!52~^pUnojyC5V
zu~O&NNoMNHq^S1ZyRyO5EX+k33RE>ZLxP5B<Y--L?|_v|LwXjD{sK^}6QkC5lsm~C
z<o*`a?6#Y-h84GE$j$AIkW)=Ym7(3pU1hZ%@3)Ro3;!dHIRGQnX8K!N;6~(dgW-&2
z`&(Gt$OcBPts$0TVP)B&Q=6Tur#xL7vRRw`ZdB#WFnR}WZLSm7p>~b_7D6`IHEh?~
zyj&ZA|DU$8t;3S3Ioqu=!3d;e>2K*=nXt_!w!Yp1XRGQ*RWh;0O8??%TYi)Pm0^W9
z-1icEcg6<OQ~?}S02y}rQO2>~Ie4~}e$<hJ!7$F9pn<p1!m9N@N+y%(Djiry<v@(c
zsy|57ERoez5bs=>VXAM7(p9n7p!#Y9vgVI+I3B_GGSq6|C}Hj9Y%9xL{d7lt*1;r8
z|6QXl-F`0u)o;E34Pau;+V0M)992>Of6GxVH*nOu!w^TB4Y$?SS7qb3b<tNF8;>!c
z!3&0GOc(U$YEj|DtA}uJ)jN0^wUdF<uF_yCXEAb>Zr=ue4ISsSb_#B)o4)I9Q<*vI
zk~x^HRpmLSHi6rY=$-5qu9mmJGwM3l??R%6lj_&QsG+Dh?T%_98kLQ68r~mMziLk3
zZT;`7T36{isn)CiH=omG&cUQg-Oc%ban&JgWv)ufQGm8|^o@+hu5sk6BMeo)3v%m?
z@-a-=)ZuJ3u4W}nY`;tVkPA}jG#Ygcyngu8sB6~vU+^HQ4*>s1uAi!w<4&Ey*8cx8
zcB|_A5U~fT>VB80(A48>za7VP^hZ{xs{W6=gDTXJ!(N)I!FTC!Rl^^w2vsA_IzfwB
z;}1rKs_}Q3t*W2CvwmdkR#R^U_qbQ;dw*am3JQISMx)`J@2o?m)NIOW-&DuwYiP!4
z&o;-6Aah#(fAO3Jk*l!_6FqeU$$_Cx)imd7K1&4(M#2`~alc=G_@Pl7TXNc86p}Et
z;<WuoqAKx+wuJwaj9OgVx!Z~MEF?l-K<%vAb>g^B!CZ{F>V(M}<MNFZ4tyh-EFEUE
z%#vqxUFDDI3v*;K@rR!laP9kq<cB?`Ypgq6-yR~grT@}(g{0sbiIow@1dS&7PS4eL
zB;!*_G$D-ODh(oIbu46{e_u>4nQQHd(+ra>jyZOL-0C!$<O4DN;F!N|lh*HBh~r+D
zWEg>_EDsjaeWeQ|bEy|0JgY{!ZPt?HZvo`Q+gvSU=a{nsmEg=<5`Bo72!#G4^JjOG
zXmEGpbVHZTF)5n~;`lp~oSj87y?YSn{xG`txko0eEh71X&tzb3OUnHeMfb5C>H2ye
z$t({g{va%UI6D(RiQqy$k&l1-V0pk)#;O1&i-=QcC#fa%AT{L_ac+i@Tf3K#({oPK
zec2Ln&gv-TG<VWvF|ct=QxhRipF}c!|0aY7+vytnjOuLVb8^()?G7nyx<NvDbxCbq
z5nYcODSOgqGFiJ7snrT0xY$4{>)_hNzo#dy><?6$$-j^jr#ez@l|tgEy-8+3AmNu^
zBuu6u@mp;ooZ<qKKVg4L*_QKUpu88c)@bS4Wg=al_>iYJ&XICP5tX>-0y62hf^rvj
zBA^cq>6(#1lDUt_eAGBX8_<L9KMbd0+<8gza}N=JTRyo}=RL_^wqvHqF=1GhbIgd#
zlySO<gp{6SMm?LZ4N8bJZxh`|(E5uRcZ=i)G$Dr`eIqm3w02>76p>7a5RwrmlUsi{
zs(s%k;(V}EQBPvF&oL!;NpfktmfHW?S>(j~Tg0+XBfqBebZzZ;Z5AD)+|<?taW9cv
z<f92<`6)6yv@P8ibRk!6)gqIDp~P?RM)$>k(=}5~xeFZCp5ky+s!C{2n@H6D{jZbn
z^WKojl{w_&I7c~_W6a^0`~{Axt4wAhZxA$lh$N>SC5XC?w?^_Ow+`N-YtdCQw#Csm
zERqRrb{&#jSwMWNFUh>xPyDTwfNy7-I-cC@m6W}tANd=ULfKU?Gvb&DL&)T#cVynj
z@%$FnBbn@B1QZlb_bZmsHU1}(sS!%oIq8HJ_%AtHC!7#QI^KvO@2QU4&36>WnXY#C
zMI?GXf<)csk?5t3#0hCfpqFY9=SXA9jowHO{W6mv8nDE_FH?^eh|m(=kz#@i?m=4p
z(TAhMalE1tkBOhok))GDKHp*3S0J22_8>}Xza_W_eW~1wYY-=xR@uy!9ICpPyD2xk
z3qj{Gl<T9T($A?w_x8<nzxWY3J)(>ZZ@5hl?z)b06GcLZw-e`AN3~afLia5(#B<EI
zG>ktSGb4`FvJl0>>-UMWho2ymHCq$^{eA-Ku!{I2+L0N9j`-YI;ux?Dzz8yn;AU*1
z>wu#q-`$D$9}~&^SjVHh{wo!4AxE_}!;h{3O?Ybmw)s@D5>JQuLnL(VByl=Ax|%<*
zPUD!)7J@!{m2!_&r`(LIWI#8XuFb}hjQTH<xpjd|e*R1{N+@0TJSF67)k)^3I5OO@
z7TvFDCR6*baP;kEpULaPhe^4$OjjqFgdSv5P4o$-+@&5=?sl)~UP!0buxc1dX3iqF
zw(KPN_Z>+lI*(+AZ6cYqBIRZeAm@g9Qf{4dbnX5W&e@r8g@k6jCZRzkbiXE@Ocu5!
zxTF73`93`$e)X<YnsX*HSvQ0XM71Uvk2Z8&G?sFk^`o**m_S-pml1zfJJK~%7>aS7
zNSyS!bX|;9J6g}QNFv%SA~j_iiN3f@%Eqze<6D-zo<u<#W`G;rPu@@R7Zy`BI=3N{
zTQ<}E6BmLji6)%feuNXVjyM$v8Uihi?(3W&-TypEt5!GSSFy*DG5^kVooOJUSS-?!
zJ&>-`E|TcHo&+~KkIb*GLXx}xAfP4q$1zjgD7R?`GTdRBqm+mm!qG)kqr*OvR?Ds=
z|2&^``8bF9MB;cR;`!s%x<h4Ml0@0Ro*~0u9i3>43Igh0Oa{(dsg&ywE#sJp>qvgn
za+23lu#Wl1F#~uLOY-lx6Q)NwT_;r|$(wV@i4XS(CvP%oT^UCFE&n>&|Hn!M{pTc7
z?y=6{br30sAQ+C(9g!h4#xrz1)P(re90QD}7r{LqO+a%W($(NcW(re?|HoLm|KviY
z9Opv1wLOVnX#pYpyOEHG)xz^f!@<%*%d~Gptb6U~zBiWYTBhFy0oM~ZSX{%-l3OJK
zYTPGWlW^^iX|tATG?GehIYd?JA3^eidy|1BugGvU#EtQa7OBAZET%$c<&YEhTtZl>
zg_fQ9)6w1bWeDOHrs<d_R3_0O&IJ8=7(!o+-(o7w<wgV=tk8AhOD*`fKa%{6Jh~4V
zKn_VW$;G&#<aAPBGE;33<+>iB8v6Pb4~((&B$>iUy4o}Tr02n<IG&JWF59FEdF_I}
zOv|)hL45Dwq}-_uT}NV~re%hGBqwswwzZ5KX2V!D3?Y*q5v0}mCYkhkNag;i8<n`9
zqctoFBjk8Tiz$jFyFKl(RPE!gU~x<Haxo<y2K7z@0B^{VAYvR(GbHneUKHBH|CK+i
zLhUs8o5-IWa=mJ;#QjL|IOIlEF~G^udOzHc`RM?#$8H`ElyRQFfIogAHQ8y5JML#@
z(R6&iy;Uuge%V2qUfW|jLSY^2(+4&0#dgNxg7anhbTIwcBi~Sto$S~bpmwplwj=Rp
zZ{X2#yV;F%;nE&<iyF@`kmdWr`5?AD9O`>n&&e<r%wEibWC%N8DqIa^+tM6%9~-Y%
zq5t2{TK@nyjQwjfOoX#_Xs!{#Zkd8IM6y+X1@-~9=`?5@WL>wwL=@}u2H1z#>eRhQ
zv%SwkJ%;`H9GHjMit3<_uv762xLCIRztD?gJL!;jl>OZw(8t)|*Kp=ITi42>{hwfa
zP*)z$rtb&ZNjCpDs8j5K2QZ(&TF=1zX|_>3m}gjPCX%ykl~Vvc$EK)(mdI|U4l9Xm
zl?=&bwrvp1pJ$&@)4#=DA-n19MYK5XHf#7Bb$y2w4+1)a-G2`X_PcD*4S4#1tv(&t
zne2rWC_ZFcQ2+Ocor4V)?kT%WhiCPiwN(Mk3--J}6mr=h8g*W=k@dmMXY1^TUI9DX
zh(f$&-M;{=h%GR}#5=bBDoDO(OZCY6z<&J-W-)v17N`<Cdvy#lKe9t6L!*?9)qwkn
zjr;|keqp`Kfc=$i{tfk2#?HJ6$qM#-ADCaOGB!b;i)w){JoHq>R{ha}8+`QuP@9ZF
zP?`INrcCorqylq(tEn)%AbTC|7pl8s8BDFYj=e!!h_rCtiW+UXGXd9D4bTU1txbq;
zb3Z%LK(?11j#VDXYc<CYz#RALD_$_I=T2bp0rK}ePSd<QnwmDT2SE5%ZDCE=aTy$O
ztiXP^R(mjwe2u~f0BIe2l|upSuIyY46k0cS&~+5qoz-IAr}bbvA&SI#vXg$syB)}G
zSqQWs_I(jVO4%WU;qo_j0!=d4t2Ru5q=)J}!jaq#)yXtayHvHe!|x!~FdujuqiVer
zdgoMy-q5?MnkpmKMTIxyuSWmJRdJaQsoKfY0oP)U8#1~S=pZ@bP<w#<Q+Fw@UTiqR
zhj>Tk%!2G`Hpd@@yutRngAS;e%{%s^3Zw?JVad1&gNU|C+HDlGX#oZoZL@mo&=)l~
z_+ZDe1#Kc~TQ>O(C2Q5ro{Mg)_2GJ`r=L%kpa^YLM^N!?n~s7Xzr4eC2iNY;<EW_i
zuTpXCpzQ?7j;S;S>UDD~atDk(49AAgr7>n=a&yScIy)XX3#R>y+~xHVI_1`~hxedx
zZtR#1z~08Tw?W;HooChH{R?3$VcP<4^M!ig9%l>3!tHq0;r&V0;r=Ps;eP__D8Omf
zQGzopd96)m9VI!>wnIrA)hh8i7_)uIMO9SxCSR%sT!7cL|GNoK>pwtMa1Bq_LOnJ+
zG!}b0T&s86p!st(3<z9@x69y67bkj*-7+bL(R<}Tfa~9h7FvTZI0J6PJ`e2J&=ahb
z^a_yGhc?B1-546v8+Y`>we9Y%Fy5_{R+RmZ(eib~e0n3-ut78*U(0U8_73O5Mol66
zJ6TT^GIz1Pyx^KYd-q?|QV2T%`_Sksd#RA@W2<72Lths|iZSdJG<x)PZL1?Mo;~&!
zzMW(noCL}#wmAg?F0hgZ6fUw$ufxL>Ht7<Ia)*6MZ+QmW>K@GAWwX0b`+Lb=pd~~u
z+lLDCik;sCq90k)UFesxBRj(2C)Rl%m>X25szP$3YK9gtZmRXI!1PspMQE1uQ&rjz
zXLhOtn#YH!3gQ74t{S%)c@e77qrp6`igJU<3Duu2P>)x6AV6;CQdDujpuCq<hv~7U
zsX{3-bx)Pr7R)TwFnVU$s#T=_Otm@<#eS(;RSN2jO0=T7KB^WkL1EUYgYD2;uije+
z3SR1v{gB+GK9>oRo$BHFu)9lLsXiq4saH_V>{s8LfW&@8UHAx=V%7cr0%(%@^&ikr
zR)3MOkwA~QR$M<Q)vaHM`+D8mqoV7Vy8X!OnT!b$*DE?2wt6Sg6rx{p0j@JYs(-Y_
zD!rGY{Ea943(%(e_qeub+a1@|8MT4e_HF}On6>{0vj(oy+1X%q9q|qI-Q&dsINZD5
zdWa76rRmVfWq#oQzJV5a)BoY&`QJ51KxUr%7a%O$Q-CrgXje}|#%Zlb1dN{1ZXSlL
z3))6huvD$l33=(--CJPmf%a|#0A1tf+E+vL10UZRGHb<94K%#PJ;Nb-RDY4i)dc-?
z9qfA>$Bh8B-PkkfN868PdkMgJz;+BrlEn%*n!#nWKhfa!lpWm?%x7#^B%bthw&77E
z+f|2hVQh!0FbPHRQ$447mVKuxg2Gz<s&oV~x!tPw*rnq3sEW#w1gb`717@#k+3%o&
zRW7F?8LCPfje_q}9SMY&$5gkIkQ`T)(i;7iYETrsNLNXZVd9Re;uG{TR4491@19CU
z>;C(ysy)HXR3+1D_@P~Om|AF-YVdJ9=4{pO`w)Ginn+Q+rz$hW;GU~~UJKA1)yT&v
z#Y<Hr5A(UIQDeZ&Q#mgH+H2JZHAd)sRnOK?C{U&25CNK`dOh;is&k(sS*H%53UXEJ
zXF`30+V2aT*{HTpqRD)O+5>yLT%<aE7WC8A*_T1xR?k9AoXb#uDS+L(>KA9hyssWZ
zi_iz^V2WEjRBxsQ`6Kn#c}TL=>`bUXR*$@a<eB>K#i)em>f@21UZ@9QCyRTj9*_#K
zSLz-`pz_pX?KCRCQ6HgoP`>&dnJ-lH;h^5Cn@LFCsoOLG%zO3X-jFO-H>c%fiF$n`
zs8V%vdQ6|xakS|DqV7=$g|F(7IbeQMH>?cFa&@Z(DBxO+;UdcGqVZn==6a1lk>w4V
zYT*=raMMJ*K|$R$oBu;8JT(myVbDv{&mGieO%EETw`hjEf}*!3BnFZ`n)BW;zg;sP
zJKx+6&6WPh^V5WPL9$a*Z7j_1)~ri~NPy-P#r6U<_DAp{NK=91DO|ATcq#HiG$)cM
z{=8pPPLawmO*l4;xd=_8Z758nCfEZS2Q^hjLL*9J=m08OBU0;((WLH!7e_Qtx<W5j
zGp`SrM>YN>DAO@bjW<w;*O=zPnUk8o1_CTW<9`I|r#1b%L*%UH0l9rn6P8H*Uy`Oe
zmJVF9W^M*FE@)ml!;6a=LpvmwG=Dz<^RlM!4(cLR^Q0O4zN$G;9m#b~-N6vKp$Wlh
zC+?=EQcs}V(s=vBncJFC6kfffNy$Rx-PIiG1C)E3)Ot{Opt(pLb*5%5#pdmgG*#ar
z&C<jK0Oql#u?5K!%{*FxKG(#(08EZ%f<Ka%nr?lNm#caC6ejXCy}E+=T2u7{k^)T*
zjgN&IZUL&KNMoUe+&fJlnhSo=tj8u5SFCY=jJ%JU1z}Jq)%@xXu+MhQ@1v3VMPteU
zXqm=i1M2IWCgvn$)^ICn(Xp1}Uqf*nw|+J%!IgX360U9FM$bcCZsc~<gk5(oxEAz0
zxTXf6cyVWNkb&F81ulSzE!^g}u&|ZOrWenL+cO2sZQR#Xi1>2$IwN7ikJEjF!Cl;M
zG#B^hrcVWS05`k?ME7uiL_$A^Yj_D2yq62^2ayo&6NMc@xfR(kzn?QZ!)_R-I}Iw5
z3m6Ma2RP@(kc{GL$3gNC7n%tVW4QLTFgVN|bOtkyn`|!!_E9dFM$6-zb203m;JOvV
z?n$mmJoHa-r$)f;Y3`qVh@9b)mqGs==f4m7iCh<&eBI*)hl0A#g`NiWkn1}XdXKo2
z3OJL^-5G<t$6U{IU_RyAML_)-mq(idIT#~o{CUA8QQRq)n?z&oD=zE>JYA!0pM_+t
z_P?QEuG98d1D{;AM`^*oL0i@v3LCWvG<vveC)|N04{bQ@-E7kKq3GFWt??Ha^wut>
zQO!rYA{B;qXrt>x!B@M@5038C&dQ_t$1ZKZ3y|5Z9Zxa70PXV!uzOSM(+|`w?X39_
zy`wEJ1eKv3vjBPbwADI6;l6gsK2VujX9`O{)b{NQ$t>-<&Y-fjUc=z;6K$pq)Kl&2
zKaf1v`qzU`Ioc)^&3LKZ^qU&*U#|Aja*%o2_c-;#z1DVH55;`#)L9TM(3W0>r6R3!
z6=1*9UQPx~v3A>CI8&nCa0!y1wB20c#b*RFpirhY)12{}))i3)u0op@3z0Sa6ak3~
zKj<y;*6|+|P|<upV%lT)r5|D92tR8aOvLiDjsoo{&z(mFALH-Se#!}c=?hTt{1g-H
zp5p)80hk1S<4<6o;SbSv+gX0fMC2v%T`5|S#0wr^p69ntg~$c|PYS4~@WG$Jyu@3x
zVdx6KDimf@?feJoQLpihDA;tJFYN_`X*`c39^6fSC=DIyd=v!)Zu14y5Ht8%?UCH&
zm(lG1KHvW>s0aLV0SXWK)n=eP;yYqy$7S;mucL&I`86}(+EYGh0_;BHTdTl)!CQhr
zz2xmxP5~y5-~NCqpWiVBNdX@+8q7kzHf`;^<Hsezi}!p;D<ma+jS?t+<ev?N$Y<W$
z9SUD~AB1wbZ@htC|8oAfNvOj$!d;v><kkuT#rD?;Mx2`BT!q%h;LHZ0_GKg+1rK{u
zXt)c_U%--wkh=w-Uc!ZKP~0R8c#33;uy_YVw+d;iq3<KOQY+aeoVbK!hajwnPriaF
z9X=%sONOA>=LMHxNK%AM4=^tY*D2(iDp)BTc~zL02}9R~XXU`WA&j!vVeqE#U=Fyq
z1h2k8yDc1Bjc0I2$PNe0Jz)-Qpxqa)(~d)?&|o2$4~5CTFrO_1#6$0~@R{}*p9xpP
z0s34hBkUK#FJ;JkDV*H}^;g1+Zh+1cW>X*dMzFm`S@MM*Nh03ALcwngG~NndT0-WX
z@L&j%_rmLPxL+)E7EuW$!j@mb{3OV<d;3|~N|T<i!m>-C%7m^>fmR`u%|o(A+&3JO
zE@J0vpw@{Gs9CNTqiJt>gBX4jiJRzh1ch)HE4fho(NmmYfC(?L+ZTAcS!_d#u`S}N
z$q@AxTe*Sq5f_F5W{0?y=7_#x$J?;GQyfge`d#8wT7?9NGg48sJ>ud(F!zdqxey5!
zH`78VRP47CW!WdjJc8R{;;kV-2^SM7a$%1YLqCH&ApX@0&nZe=M6<L*;+$GYV#E__
zU>_C_Q?D5(-s%G{j*27y1om+;>l2a_V$yOH=C1hk3{W13mogxdDb{}o^+#f}i%7CW
z_i?cMSll)UU{A!GSdnwj#jD++mtz;_(OmDP7_bhCx#GqN0L>E@-+{(!v2TAc3&dI7
zAyOzR383DI)ex8E-i!V2L%&!o9fPDqtQ~~BQn3kbZhjIU^+(aZiWwJRsZ3nB6eTMc
zbIt&>LiD}}^|eyTPAIrYcFhxDyGkEuEwx_yjW!)NO3YozxJk2<py(k@c?nTZ$>S?T
zHc3ObLS(a4ownq*O3P_>=PgBUK;AYf0w=M!?Nam-==n-tDO}|z#T<e{tW<d}m~ql&
z>aLDS^RiK0$E9rh6gV6&{jw5XoRq@pl}V63c7(=hX+8oN+*!$s!rJE~zh9xBB%KL>
zrDW;kdQcan=Z&CnQJUKWl9#0B6v4kN)&2mVQl+yLb-6079s}xzG@Dj=X;Q`SP)L`y
ztU%sv>0lP^$!18r88UaJ2OVJPzGSG2XYfGsUk(!wrBAgW`bcW>3L=lCCCx!Skw%__
z-ZQCXJ0#Dg4^$T~q-`{lc`1FPA^nx~A8q~SNtHr?@<y`K&Q-otj{>HJQuRqF;9F_h
zR2u)@N#jl<^SzWrgL$zO_zspzBu~V!xlhsyFC?F(4#QDxU#0j`fR;&aG(jkr#(suE
zh19${m}}*Z>0r9Z3v0l8fB6?$p6r%841oF`dBReN1j@@^!kN8tukP?7SZ<$0?_a1K
zLvzf1@<Q6J3X?zTk%Y@b6Co2R*KH2!fV_p42~l!KS~?w)pFD@982K1Y5Dv@ZXjvO8
z&sSh6PA;RZ>tpi8p%6JPPih9c@p4iM%6n2S%fe$ykgwfAa$3%b2Gf2{?$j5eiSl+@
z$0f^g6#YFfHx2`pB5%8hnz<w|i~)5;UhogFQ)PEEp20QwlO5D``NSbmX>xm-wA_>z
z(Xf&(@1b4B+j1N|`wTgJFVyeKpJ}FgUq0mn>VaI?6nYQs@>n<2>?64oEfurn&;20t
zSgvsbicjTNxp3y09J~V9Idb7{`29luFBc-Y@@i^cuVj~>q5fJPO1rji<lWbie3PA{
z0k&QVpN+&vnNL&9ZOYPMlykc>w?EA9P)r|?_$u})IJwICDgDBbxl?I!6B@geAe{Z-
zb}MHn`Wc{ns|qjnC_)f?3RHq=5geqn3_!A1Y2F`t!Ai^ephA@H*I;SC60JcJru4@t
zGcHm&P8;k8l$6mxxu$5<U|v^hQTKX7$+Tyog42}zjnKcT%>Eh4EhVW8NxE{M_7!d`
zHE49WqqMD!Bt!W-5y@RehZ9)bJ!J(2EuSbOa59N|s;uI%2+mO|Qc(%7l-SB}El-)H
z1@pC%xtl6T38HXszB2bdk^&{m6+xTtVV04!15wAd6gqWp6roP)C7(y>>-#)~zYY9n
zz}<$sJA&URo!U#|LkEHP(<<5)YvOkcGEEa{an&sU6iVBC9o24&&)5>;T1MI+->Mj2
z18}W<vVr+?J945;Zybl_>}@R*q40}v4d&ZLYH;6vLkzARwz>kYqc0+?T&L<Lz;%A%
z3%D+QDN5R{{xe*=f2Nk$<Jbkr^i*bp)9Z65NcNtv3vT`9J`wz}O|Ij9<^|frTpscS
z1#n?6PC>GXb#5Wz{qtwjTR<*|ojnr(``84W1jD|^4tj>s?2P9))J1V95595?#60<f
z)Q@`c!?Iy|6Yop&iOu{#8vM5K%t7RB<sVYG#GAiQF<c*hCQV1S@mE6txSe;Vkl_yg
zA1^R{`4oFKi2CteOOWj3f7y>(*v)^WBNhRC>tDbO;;Y{PwU;lW>1r_FfVP%G_}jFO
z-_Ki?K_QI)xCgF<^Y;^x7s2luhrCGsNH-)0_=2hM;vm0ZG3-Y1p|yc|h@Z_PiRP#1
z?070Md}G=&I?Nwi2JR95g#lD7Ka%3Ear_V+OdREBSdkp#H{kp<cbuP3bBz<c7XuUV
z{305lPV#$bjc|%@?G0xVcowI6xzqfnz3}M_&tE~_S$>-u3g`HD*T78XhyG6cPv`mN
z)xo{M*SZIpi~N<o@FE4@L%_r({?$SFeVGpuQL|V0+&Cy+<%f)hiEI3Y?{nrFIGxPh
z;H$NRdK&*B8+teSCuX4B;!li&WIDg=4MZ~d`h<CxpOp*Dd;Daa>#$=AT|vF-1Ky2J
zM`iLoyFv6JKZ_zdkNEutfM)S2WImhEevRZY&#y+6KH(Gkz?r9fSZkm?<L&h9pYwjN
zfRe-a^hVwb-u(}h>?J>~9_;4wztZ;jE504<V#=L)6IE${&3~XJ-5b8@awz8WI(&(Q
z8Tj?;pfCf^hxxbs_+TVOyvtpHzT>A-6#qS+-34BJ;QP?7Y%%|H0Q5@u(>G!8Bfs$*
zn5F!<IuQB74}F2;E3dtdymH<g3CRk6>StiCu?wYT;I0)G(^$4%7)T~I3U~3P7Uw2(
zHA2)wc=0FnJ%!3Nw0H@lP9SfSaN-z}&4Pw%c8lPO&pR+lf3pCf-oouYpnQb%Qc&B3
ztIwgnU8qVeXot{#E+{`ClA;hh1$$NUZI__X2Ry;TyhTVtgoS(IQ>ftfD>U{A^RTnP
z?H8C;kPH)UH=?#KL~xLd5JuGpOr$W2LZt_Um%l*oprE@7pQ3~XbR6=K(3lQeMGNkW
zAQB@iuL<U1q1R<3M}$^(I>!_%w73k#IH5gN=~1DV3qX$vA+*#uE{rcgU7iruP=q61
zc!Gno+)3eN9L%2*sw!Y62%Tx>aas_6f%+NY#yu#U6-J!{$~j>l1sD^BEh(Uqgu&Dg
zB@1T?0DWF~??&(61>s&_c#|T8(%$_gq1y<cT^4fxh0GNpicVOj3d1Q3epOhVkGJZY
zP@jT<*M(Y-VDN_U3wf9(99#nCO~Il;a!Y7A9G21rEp0;I7Md1A<c=_82rx5*V0@gy
z-4z~;)!_ZRCn&doeP0NsGdmB2FBBNc6yp8i#Y5rLUqE{#czwd7$P)7C<VChHWD6X9
zEL^g|{1c&n1hAh9Urqz%nZQ!e=DAQo@s1oJ#}$$<gj@L55R0M9iJ)?YFBFY?CAhW}
z@c!iqx30jO*MiqISb8H|qD_K)VGOMt3Iypf>=p{I+d}`Xu$cvDk#K~jBkzRAm!R-o
zXfy|)AB2R*aIIJfn+C}e!9+cTi};=nUHFMtwn5Tg>@C5y-QqghJqr-sH5eG}d&Di&
z&jpGVji4VSesqlM;*2Sf2^P2h2aOQ1KJAc&ik<2B>prncD<u2H0d#U9O#FK;l5p|A
z|DYZro@fZLNO2r>?+3(uf4Fu~6wV<pTD)=qNsJgso0*5jvB98@*v01yArmVutqZ^7
z#4}N#j*6A{z~C{lfaa;k#mU#9aY8JmcROAjPqE08;^KagJSBEvk(VF_(ahnrxPc}&
zXT-+y;nP`h37v5`Cq}-7NTPUQAd)1pDUAooV!s4Po)_&?M<Kl+j-;T^MbVqa>J-rl
zyD!`&@nTPiUKT5EK=FzgUKdr8DrR0nySOU$q2BhIxS2-p>*AbfNZt@@(I#}7*oh*k
zH^uE|;NdN?YG*vjbg}3kK;ITUd;oSwTtE?u4DpPe_GIshyXa)nJ+X{H?~A{;f#?JA
z>PlG36nT6@!aWoZ(1FfJVvHZklqJ@qf@X_JH1l{YHhl=mCt@$!wRtLr2f?QtG3IxG
zy$}!5Eb66LzX&3^V)RJpy%OV30VPk29%F~hYjG*H%QxaF+Q7>f)82t95VI)OTqv?#
zq4-wZO$XzO#A4ccdnf*O9%Xtj{&NkIAH*y=WmGKY<bx^^tJ0Z+k7Dh=!7LR!H-^F|
zan=Y>pT&kvQHNi|^9|s|S8?<_djHDAz+tG9Z(?R9^vgwOob16m@$@8^Un5nc72#TG
z)LwwPNPQ23xlU?8D|T1u747w`msUoD+8|w>1(c1Fe;6d)B<>iB?Jg}(hFuRyO>1RO
zsS%y_@{&}mP?ejc%sn*zZI-T{g~k?X6Gi&AN>gdO%3I2ztv(;=%O4QkCe5JvxUZDp
z0!w~U$aduIl)~qM+9e&mjl^I2XB?c_Es23BM1WL+BTU>Lsnc#GfzoLj_=2R>V^Q0C
zr85Jd9xQcS4$2-P{dXKDLZyyv0kcoC(mG<lbZiic9VT_@2D{<XLpll`A^koORHXED
z2Ru9=xzV)#pyb~JZbwOh-9a6a#?zWNS}I!rW{i|P0(ys~YWO;tJ0i_#54~6^{{kG1
zlMJ-adDJdh-+??PwHXB$k4sGlLjQzhs*22bss1JyJSnB|&_5*wtpGDY`t~<KPfNw8
z;Px45#u+frO6lhyc}{9hCrlHi3yG-bBx(9wU?xkiyMa0{WyJvHg5*Zw=!?=CHyBEh
z>?;nzsY}xAFGwy+Go#_m6-hn_DpmTe1x#F(Le|5?4QUp&z%;2V1><i@>?+jLEvYZP
zo9R;8AV}VpW>$rzJCYaei)2XRJve$-8ovt$?@15o-MlY#aDv_gsrqkVW=d*%4$_BG
zR0F^~l2ZEsCQDj!4TZ^;n$SApv6P{K`6tp~I`{Ncny>|V&!loH=yNG~ElQCi-KH(z
z7n0{Cl=r11P<7=>>giB_CG9#3kvu8A1@c}?*%U*0BL&cjrF?0O7p?ybr27{5T_`y(
z1@%@6UxK7aYI+==zLWOR39a{1O$A<jkRDRsTP&s19(jqhpblU@N*TYve5v%APOE>C
zekbogOO2=t{vyRrg~C_qDxJA6lWY_$`X>EZ6JC@{zmK8!uR=<hh^kp5+sVXQ+294r
zMSfl#Cf3QDsMB?o+unlydU-E}(KpDgDA2!AeojGCH+ew{6x`*;9#Hp^yDWghCRv;U
zYO{Qnf@9utLz-Rr$j@mFxJ~|-wjzAx=l|0Flb`H73=Z#<>(Ue5ExTAC8Xzx@L$XKi
zwH3);c?_M<3YK?ohQSaycLgeFzkDklRG9ohfr)V0gSPt)$Y16nIViutNADCcpn2dS
zc`XIrqUCE}@pxn85wwIjEXO9p8T%1=I6abBxx;^eiIZ=JLG-9xGZrw%WFOjPIW8}z
zXwM1xQy(}JFFVCT;iMdY63HofQV#MG<VPGpPs=q8FmXn9y$HK!W$#yT`<#4&19YMs
zH3>~1Nxt$EB$MTceaJg+moHOX>4N-UWsnzT%R=a<$bZDZi%asWpHVZH<;k?&cSSCr
z2=l3OAO-HO%KS*^U6XrJzkXfLeF5wnvOi7h(quioO*iHI)$s7PJf6b3cVw?VNHXMs
zivfLC?zk6*?#cFQLjiMNzQsfTf&5?t^fTr6w4iw?`!<KnBiWx;M_KZ0AJj#*{1<JV
zK9(`p##<q`Yz?%ha!Lslp2@r?{CzHeqTpwaJfIi!UdRn74E|EiJqoZ~xuz2gy^<@@
zslGfp#2yTd*K#>6dEdz8m64e*{~8L=0(rt+FbidE3>4qWA}uV6WM4Y0^iDoN^Yr&}
z0*$60<QFwzuvqq{)?FeyBd)}Kl<WQl^-_8KHspPh=e351pXGV(Q1~Lxq3O|A*}ahV
zoy!olLFPBPZ8G%B<!N*<phDhr6Vw{zCPk;#D$9O@hKthZ8}imG1v2zDDE<<d8<kXg
zOm2#P6%^c+1<&B9htj+!L_C$Ie?Y`b@uTBeo0LVgB;Ty$$q?D1jA}*k@2yJ3E|~XL
zB9{W&M`=v6yKTzLxzO0IOxJ<hp|qqpfUjbsQ#^jkw0%f+DrNLh#x6zjMVb7SQM4nm
zTPdmqg#e`!Z87gr`qAt=P;sGV6{K{ckz=oN#t8GlN>o35)60b@pZ|nRsPckh`umj8
zy&$t+xkbkl!jwtNP>OJ+tPpt-%F@+fMk@V&hou9`XM6$59aMVJBs@xSq5Z)_${t$A
zMJp5N6l09yG8xRnigOL198m&kwjZn9rfxk>IZFY4`%xvs2GA4A$TlG3l``7FIjL+d
z0q7|uG7(9Fa`HXObXqCi2$(ZU(g%o~RqDk7?VM6f@sLC%YBB0CNtt*W4?S7AK-)6s
zm3de-aTk=t-mq{{=@<!x6h+?_$t5MHJrpk672g}kyrN{#^eR=E|1<o)s`Q{$-8ChJ
zu&*m$r$F?E5>GqhY05O(6uzl!Jp?aqDf4Q>wRELmDU#dD2K+1qVpRz^5QkV*O+6Iu
zDudFHcTd?u<KKOy&mh=)pe*u+NTy;RO_QF7%E@s^vX#z}@cXechnCw<luFB>@mwic
z2=h70uZ@xSLb2UI-Yccq2{7}N8uX#WYvm_eUlb^}*TA(xrPpofy;bIqKtbOt&VRt*
z2c^e(NERzysWT{11nRXuD*1LgA6Kfxo`Q>ClvWgD`Kr|V3ovC$dpbk&O^K0Vsa%O@
z1Ca`4k_0c-=oV9Sc&*OsA}AMKG`-vFboOM}b=8e%0`>K}{oYX6pzA7txl!j%-Ibee
z{YTWAyY3P#zCCnf40dFC>OOe_#!DyD7YUnmoh#t*X5H52(BGmvISFW6b(8kPQE%Pl
zcTn)r6;WrfO&8V!BHMMRXj5v3ZVr97=BpdM5h#AThy+kOb$;~K$1YuJIZE%Zs}c<L
z-MTAu!XrS}w3UGOZ;vjT4%r6k3i`msARTiQ)LvaFy*a_UBwFf)=<@x*4An(V1+`CC
zk2a<D>$E+99j04P@%nIGgbGQ7&LAU+)NP=Hk_U9r7a@62_aB`QiPAlr3WY;Dp2q8F
zUBzTN{~M$8djrr|-9742<8%|K(><z_{(!*~I+iv);&m}J8lKc$q+ausPNdIo5_GfD
zAbDEX;SR9R=&E)_-dSC}j;Psly4sbYm#8c90A`ZzIs=2rx~2Fz7Vf;xs0VdHcYy5K
zFY26VS(c(ppaykGx2`*q%en!_kzCQOyaA0=T_gpkuj=AeNUrIs(s{e<y2dna-q7{u
z;7pqC+h0Jtsq3E#uv@yGt>9C-Zhc26+}6$Oh2)MdkHQiex|-V|c~|GZ4G-;}U3cR!
zVD9UlbqDvM?mTT@KhoW%c9o_3n|9c;b^U9D`B>-iCnTTf!fzmXuKSrfgB;ypM<iEQ
ziDC|gx{OVzr?)yaF^hC(Xc&8^n@$n2_qtECW%@zK(m9o4-5eI`B|3YTa#Z3+-Jtp?
zMXAod9$tLX-KHIl&${0!4D&@dbPcGly56+ND${+#;a2XOZZv&~QLYPkg}e&gLHfpK
zjsE2^D6G{7Z-gZm{Sn$xU#G7@aaC7+GwSu$>tC-0bA!I~Oe7oiyX;XYnw$Qh4eq<^
z-)F-M5B*vnFun9E8vtgLKE5kJH|w{2K<#bOzojEqTlE9!h4<Fa9E3a{eT{`E(>DD;
zI$*Y4UvD~`*`eP?5eQ$sUp;{N>EHE-!JYa~G~3vvzv2m|zkYfit^aoGg@%9$(6>wj
zwMQRJr&j{?<sv|X^gR~C@4b4}4%An$zAGI-4bf}pO%K)oLtk<2)Ayp;-G2R;!B7a(
zyHUg?Qtvw%m<RMv_n{C6_3C2y6r~?m6C#K7P4O!eT(mx*gx<dx{puqi59?dfH0Ox^
zkJBhxte$TTFXHs#Z=jCqmsW+}$MiX0;l*+N!yQmKp<mMr&cy3|egX5O-uG`fb4tI5
zA_xh39}#v>>-$GR{fu6uG4-r|D22k#=@;z>SfXB9P2V3T=|g^l-DLf5v`2hiuc8l9
zFX+op!Nf(qW-Ihl^kZomc}c&z3`M)Ff8vC^EBY4nv{Us@dqLr<zVQ*5zo!32W8-!G
ze%kK4p+C73m}&a>#&Gneel~swgS(}dXyTZzx4FYn`)$4Jui)O%Puvb}hF-SA#9h79
zO(@>epP)#>eSLkJ#AoW0cfpH?dg~RSJ<_+Qt;8(7osJD>>;DOb<YWDko?t%F`%p;u
zsr~>RF@2^#Kuh@N`XzMwHAlY;=fAlZ`Z2T?&b8|+U4_9{`WsCklc)C{0gc!CpN-Ie
zqaRP>cE0`{MJEdMTPT28sBcO~u;1#_TR^`^pGV>1clz^GGw<~SD}yT0H(CP8kNObm
zL`wBlDesg1#V*+Wtgk`egnrRG`JiII>g^{-!S6DChavF$o4)mSfR^i5|AEq1=mVmV
ztTB92z+7iYqYn^W4W4wOX1yUY50*9<##BMF(O{+b&&?2Y7%1+B^xq)jVHmj(Oix2j
zLx^}8rWFHali~Gwh-@}&q6w?F;i^3fGCqd!7vaS=!*e=4w%yQ{&e`uURBno5`x;)P
zgXw2*#}6-YI}Oo)!HZo6)oCRD27l^UcN@0z$O|yI?gh2S&?5i_0}Z#|!(fnM)K=u}
zHO%}Mc7qM)zM?Kd3=3$c8fw_MpXQ(Y3}>jd>^HQOpcrO2)EhG4hPWswMi}^gU`84?
z41(kV!^AKo2MxYdK~aXTLs5!Dh8OfhKG6mjYF;sh;bu^W4L5>d;)o&C47;(0Dzujp
zXV~SBvK%$sp-%6ZK{nC;!*PT20mz&%cv1U^H#|BD^Cu0X76ay#A$%fSOZe{7Sp!e!
zr_LFQbYLbLE>e?EGFTSFQnH~7Ef~)mx^@N11;da{FnH0haTF}27`8Nph0BJQbO_~&
zVOL{#k!o0jzSGWKHJm5_dCl-F0gBfRD<(lS&Cqr<sGElQeyD_7hHJFZoo)!CFE4K!
zChUTxJBIyqpy!^UK{_10Z;0v%FCG{)-N4K=RJ4S`LqokqkbGpA(Hqs3Wyqzo<k^OS
z{g6C1ETK&@`xC>3Y4G%^L9xK#GlL7_1l)7OkW!%K7|v=zy)e|J(<d(tB8>;RhE<`!
zer1TE9mPCD1ohdk4S&8yUA!^;UWz2&FonL&E-*|gL{ey2>5Am7!AM^`6&a3Dko}#Z
z&PVw4(QbI;1aC?W8z^}8$<V6^+|Pz4R6}13KQ{*2SA&Y?AZ3Qd0VvuxLwjH3l^goe
z*SZykrlhdOIP?HqTWefJ8y+skZugP5&ba9<^jwW~UxK;OIDpo&ZpJZ5P;fWa`wNMO
z(VjxHQcq)y0u3*tFHI>n88g+W(#^(q6s6c=#1VPCBgPh^;LJ8-;bJhi8+kfyy2JQP
z0n^vmk;3DC#v@Guy3^Rc6GV0y|K16M{>GZKfVtb)JQ;Zb#`SazYL9UYZ2;^w-nP@e
zb+EBq0yo6C`vf#Xjcf8j?K2L?&j4}zjXj&dnJ{Ct8$1j*HvI#N5k^xK3`QEah^W#7
zM&AlB4;niO5Q#S4&qoqtEPsYtKWt2&2@6Mzb12#tYy6vftvF+K6KdwDvF9Cn|Be}p
zX29X&M&Gj#Jz+f20W$H%W7N%_G?viW(^E!?4&)>l_m=|uw6Wa`_;k*gc@0z|iiQeK
zGTx&vB9o1a{sDE~xU>??Uoa-Egx!nA4dVfwV*KX_@-7(*BuJ(jXIH257gvo>X)oxS
zu?4+q*Nvu+@acxJgofBOW6VWp+%%?-LS5W4{yrOa(~V1MMSk0OE*p|}jCYN|&M;O=
zMsnXcpMp6LjC*q+l4-n3`<)Ms`7NOS$mrq@3t7e*v^kfJJo^6lv2jl=6!eL4CoOHC
z8avUB(lcXw`oQnG@s0~%UK&5rfSqex_yCHpj2`!(kZ0WfGxA;=D`*||#(13eN%M_&
z=zL6p(UW2%g~qsMDCk>bi3U`WF>w+w-x*750_DB2(ifD){=qn8HL#0~f6(-*)L7I8
zrTAoYrghwBqe9`=FUDdz*ZS2MQ3K2}<9V8<d^7sdU|w!490(H?#(vSDTugmw;<(QA
z#1$g0rktk8TW_jG>%R@A&_FOZniBWIo|`G?Bl6tsrf!{(dYJmtRL0ZfM4J;{rpei0
zZZZw83~H<CY<GZqoAw-r`#z?hXd<@F6lI3Oc9ZWA*xg}jKqno2O$X^iJ3o_|g2y{e
z{q943muVWcTz}IcnhEVTu}>iqXo@f*FUVx?uf;RmYx+j<mtd1?J~Bg0T}nWOnkLg8
z#XeIzT6yg^`O-TQW{NI?Vz}u&?NmgVX6o?*M4GCfhruY5fet(#GR-JQ9Y&j;(K+iF
z)07~%cGy%#1LhIaaN1&zHNC{zgNrjQwXcU$M@{2HQM41LM4E%dn|`OD&Pmht`G7fP
zDky}0f+^<~n5Rw3b5LhYNep~CYx<XFoaam<=v+^tY55u?Nv0A5M3PMbj#alQi^8BO
zrjBorTrx$|qVBS(U31vGVj5<r^Y^KyKO>NN)#O8)gV#)9wc*=!QzGrv-7qENceuDT
z(`PyWf79ee{l#rl2z_LK$K;oUn$0lnQo-(BQ};HY?wJ%iNO#}#55?0Tm`1FG!Aw&>
zZ-6~C71Na9k*V%<)M1us$5s~aU$!ZdzA$)dx?zAb&rE@|$M@V+ht^>^roB6%_`>vO
z29lR1Hw*0Mn&wm2|H{;SFR=4W4H)F*n=Vg8br+Z_e}subQ_*FpzcppiQL-Y_WnWP5
zObZ4<^1Vr@gj)Mxs*W@6cCOgeg;uI1Cf6Fs{AgN4NB2riZ>fY|Oa~Le{A%JBqGrlW
zwdv!TZ>9ySkXLR}(d@3m<Uu=NYs~d&4zbq!tPD&S^Kg2u>&%5CP$XA#0G*auZ*ER=
z7kBfy2~hVi&!=FU-P0UH;c74Q-_)))nfI)L{$_J4DyX-45k&%g%o~=0xy>Bh9U|M!
zDfH>c4zmySY`*4+iD3GfSM~+kPIKH6NbWKhH;1~vSvLoEcbnJJVkf{X(TlUke1bN@
z0?mUa!?hs0IgSF6d(HWDRxsE+auoayF~6gtg_>7jLyg;KKJpaQesczmCt>EY!H^6$
zueO7VFt4IBN|EM8x8ckI^G|62J!p=n=zNs9yfT=F%z3m?5^bJI>-re;6M9n*o12b>
zYe&rXPfL)-nltYqi8GIy0{x@r=`>|LW<E^M>A2ZIJ<JL7+?Oa*ytz3=2~L`;9E97a
z%vI@Q`vi0Kl}JvT=hBktj5&?gT4&Ake*)M!v)2MJ6V1sKlT9*f{(+%nbF<M9Id5KQ
zr!BV&W|#da#YJ<^y5Odmx6J_dCG&s3g1T%Tu?E;z%+G5=Kh+$)4hmPz^ByDbn)$*L
zczE4BBnkC&!~AL}P}0m*cfiC=^R)v|xMl9@2vC_T(<14%x#3LY-7)`4N5C`8^NQ?9
z@0yqGh2lMPK_g_|H@Dae#Rul1tDrK?8Po|qG=CclyN}Gf@*$aJ7U&c~w%MeE`eSq5
z)1aQ1uRnw{PtBeKA@a=pFdur)&Ev-dCC8li4wx^@S{i;|n%^ftA=f;iC(S=!o2%1V
z_c!Jm^sP$1xz!hd7MSOeYlY?>)M30ej~arc$o%Uq6#Jd|7zLr;o8Qt@^Mm<hbD$NQ
zbII)z^Qv1g_|a_n3aZo`KxdLanOo99^3Ud_G<o=9{um6fujVJyY5iAb?iLN1Z)WRO
zV3(VBSz))rTuhPHH5Sf@hqu<!mBM8%mOq9<ah)Z}iab|K6;J4`w?xo%aDye#g1n8E
zKifdT&GO_uP~0uUsAux99QlOA)6%auyzsK*cYx$3i-C?_*f(3c(s7n87CRlK*lH1J
zO5tru?hH?TENTBC*=D)Y6U^<F>VLw+9hURApzmwhLZE(@ebl}0v_uDj+GY6^3k83R
z8^zprTb4M!Xs}eJ4rY%f))RVxmf3WQEyxl?%Y?mlOFVTn!In1zp%G#U+5sxm^7c70
z_gTi!ENj1I+iKKvnC0mKP~jG5`nn{-5=QabNK4u<BnK?c^l9Be%UF6-qbx)2f;wcm
z-wm!sTc+*>Sd7JBfER}?v#5TLSWM&LXspHlhBja0ET<QvGLBj#+G{&zS^6_f9Jdrc
zg8m81(pZ>?w=8Y|>ZHXf7W$_w3qC?W!BS3VKu=qW^guad`Kvbc&RRO?fpX3=z8HFm
zmfjDbaNZ(O%e`P(eh{u*w9KO!eTwC*{V^0TSsu_Cwab>yG?-tpEIkLsR7>0Xz`kk`
zH^S~UO9I7KuUmq>VB&_QtPMcZEanVQH!U~wpnl78k3MinxAba?g5I_)r*PLDOLb~p
z8J58m&cAD!L0_%kvxqYwa^K=N*bbQomg^fqW?Cv$f&N3wd-_)Fk!8#bP+68W>F_(-
z68aVnKej{;2ld1fu>l63T1u$5d}i^l1nlRQy{!S3WBHq6Brhz3X28-*%LwX%b1jn_
z0rQom|6eFsp5^XsfW5YSnn>}NH<puX6fNI!n2tgeSjy-pj0!EMXfgWMav=>~6j`eO
z2I`$<RW(Syw{-6U6CW(&ae$sHws?<2UWuhIo!0(n38RhoQp-B}PVbXt0iECdY*|m^
z?iWi!4~TrV<otxB%+mCb3h&=HORr&&DYvXR2)h-QW%LtoYpgw=Az5pET?G!iSQp%f
z#yYDDoda{V+Rvic>#d2aAhN;wDHI|bt$k?W=4MT#8MeE%XBS|4So8Wp#M3Iifq5_M
zrT#$KWDTUf!Ohm^)aTl_SeFb&y46~h=7HYU_Gv)#v9_26nQd18|A4mL+LyL_c39Ug
zfrzg)a60PA&w7qJ-JRB>8zH&N`f?ARL4dW{BY3#SI;Ioy0<AIBf`Y7b=;Y*H>y3JN
z2Eo?!i(rOW=i^tXxlp^c!V}p0tbfv%Q2VVnssTI9`qMOc5pFG|Wn_ePZX?)@w081=
z;sI+?Ch`ti>(kCmlr{b*h#a!MqCiu$_2zX@F;;i_n(VN(5taUkHHL~EYZd0fLY#Fq
zgS?~GI}4B;v)V_|p4V}!Ar{`8u(qSkg?Q_nFeE3fKJ8GLQ`SSYN04C6e1a05w)$5?
za>nXb8_8MgPt?zyvnJ3cccQh3BD6`?WjvB(YqMrBao(Ckum1&W5*;+YXuU=qREqT=
z?T%ftcCpum=w<7$<9I+<tYayJo@#v&3DK)ouOO7^nzdagn7?j)Lff@BtXr1BV4Ai0
z0>Ip~4nB(HmNklEEa}!L3Jc!0-phvM9cxcoo@7`{sb{)t-SrH4_pCAWo$P%p&Zy(P
zv#u|t_-Ced{Xg*Lp*5Ah>waXNK#QF$Yc932Y^yOAu06J<)6D*fby5SEe`>Ar7J1LC
z)2|_UZuL0;M{}(6C>Hg?`s-9kzO)wOCmy+6YsVXK?UnW4*TBrPE~UNo*VaIqpS-cI
ztf22d^Q~j(m!1l&KHZ>EXx+pC=B?FvJ^U`RmeczFowe8*Fz>BjsL6k{R*Zu}sde}O
zSo&mb5eLc7*2!0q_r)6V8IoVEkr4nZvu1RL!Ee^Roj{daA6JD!h4lsvv}<gG3h4aV
zTH9QAkS;a@O~TjNIvxV$YMZ_eCf3^)Qfy{}Ej0-G8*Lf1L+NG<8i8WF+jMl=!o%kJ
z1V!_-O-O~KUbdnEFu%$6-!M3{+4gq<s4cdo)U9u|?dc5>Z(BwWP(HS)G%DG**-j*&
zO1Im#?gsV_+a~%j*w<D!1&N<6jkdLS+SW{jrCqjebi~=;W~U(GZkrFyI0I~}C`z}-
zCQ{5H(AN4YM1pLeb5PK|w%Pv33%1210xZNfZWqjl+SXFYeV=U~ow(d@w>20EGR#((
z4bgC$KtZSo+beoWB5kW`!O{WSUK(-^+NRPbS(NSEIKUjTEu&dsv~67pk{DZb1q>dx
zO{7i5Beq`xp&n}stqHqvwkPAkJZc-JgXA&WMGDazx1Fa6%?X?RGkw(=Z>ykfo0GQa
zUQj$`tFi(<CD<4muut2f>9?iM*lI0<{#jd15;<qvehCVRwiNnJt|Xf?O@@<go@b$O
z-nQBw)CF7hpMi4GrlH|8#U@c5Ua~d)3nG_o=O`|I#n#$>5)UEOHYgNcT(zB|-Op>b
zE61R5-KJ1@{f2EZEvwROQ>UP2ZrV;K0`!)xXe5~Fw#pPQx^0u(z`SECItP&q+dV7t
z?%R%p!qNkqg-)Ji+T3mM_n~cL0rDQ%CVIkrmW`c7?_aiUM0Xf`Y&%Bn>WQr_E!m#h
zF3~ZzXSRRV!>8xAB8my+*k04=tQWSPePHROZQv;A<=S>$LEbCd;6h;M+3pTN-fNqg
z+WH&YxDbfs+mcQ|ufVo$8o&x|Z(hUSx3)jxX#6X(NvELk&bBNBFz;=5Xl4DuHr@iX
zVq580z?9hX>3GIR+h57hFSRv{g@>PPhDyNxY?GG&?ThVq8i&5xE>bYI%r=2``oGyC
zs8yHS9=bxW!sbj%h&4_#>w#M96xo-?KNqLb9x%AhX-Y#Fbais4NWglhl2q8;;Kb8j
z%tj}LO5x_zT?0^er>hEJJe)MN&*SMdgFZm<a@uYL=q4wTK4IGIl#>O!Tb#;#AhOkI
zg&r2Xot9?+%*W{iZ9Q*uiuo5J_U%qvjnLTPbS(~CUnltmu>G70F2ejyr-t;~Lc5&W
z(|Xt6soOV*>~?w(2ulG@mVVIN<8+1gX#$<9(UIpMrv*Hcy-w#7p&sn?hL#B-PQN+A
zdQP9{w}JLKIa5e#zthNXNW$z+A6mjhxYG;+N)h4Im9}{!onE=Y(gCNMH6e4*Nk0`-
zl+&D65IN-3f_BHEotB$`7UPsd=Uopwt)TV&5vLt#5Q%lFITo04PF0V9`F}XN?zk+g
zFK#(1vtio1_uh*vv&?K+Hhx)Frj?c2u%TAkvR<};$`(WcSt5vlipUTdGG*_L$dn-)
z0hzz=>96y-_nh-R=U(3DKKGt;?!y&EqXj-CG9K`S!d1pE%iwPkW94t?Ol4TF9ss?@
zc#Q(`X$+S>=wD|@D7v4{NS1(PFs5lrG8x~~20e>$j?U*d7_U(hG@J47_aHe8`h@b*
zT!x7XnDZD%C{UEoIMD#T0>&MRA>U-oO3*4~TsV%IDPlZKug_w}N7k>=EMWxw2$@nw
z7FE2IG1@O+g3B49c5tnN@v<Lym5e_gfQMC#egn)`Gb$;uTf<1EQ*13`;~@0v7@rOU
zte){3T|I7K2x8z&BV(M-VNHzFe&97T-phb%EsQV2VBr>H>w4OMwlYF)0p>R2$vv2_
zHim|-O0+W;C==De=y?Phos2K&G}*;aJ3yqHu|5-C++jRHr^z11nIE9g%UExVRv%+$
z2t@iBo)o&f%eW>08DK2A357w1$2c&D7{C7pXNDQ~7XNqujInPR8lwzf9%g8a(MX5G
zaYkh)K<_bbP$p}Fv3)H@G0E6OFOn(7zGvXfea4TiFgVSyn}vxPMjREO%ra61z@B61
z7l1O)*m)iz3yjok@NAjy&~jtPtf3Q(JyW+p-~Vx7KBhp^k@+A+3!In<w83y@CjJPG
zBTP2k{dHkJa|d=^nQl}&?8a25z~7_HW);XWX7zW_JI-YM3F6M|q4SUjbAJ~UJeg4g
zfc9eMP}QtA^AFm&`7jUDnbenALoaIU38wE1di|J=iy-RHT&shLlgw_a{|sQ7GGQW+
zSwYu6f|zfy&<bY8P#M}8=7z-}Axv%_&_bDA6i5hTj(mve3TLjQdjt{8Nvfkf%e2#i
zL^8ih2Ff|+^BfE?iusu%W;@!-oc#_k=b3MCpdZ8ZX@!Xk%&#cV6U!{4Z<E9^`IH`x
zXFgj2n2SuQ0x*}DyhAW?nW>^>Hh~!$0e`PB<4%GkGTVxvaFrQ63H2oA{)b^HnJG8|
zUJCQ%c92wN7#+p0F|CJoz<e6h!51>unRh5{lg^yVLo0*1XBn_Fna613n#Ej9^~^Vz
zHB@Sy&HTa#dO1upEor&TEQ*WgF`wH6yZOwmh2Rx1FH#ZtO{VX!04roJ&|k8Mxti*2
zikUy)e*i5lVJ=uH<X_5c@&tAnbAlpc<;<7fh8GpgOuA@Z$=pVH%POYLi!f2m6vcv9
z!+fj}3bo7}TD<C*`_4n8p2?zNH!$C&_-7;Y13Ex8G2f@U!e-{7YACcY`MFTP#oU?*
z^R3L{kF03kX1=)?%{JzPLqKb1K0@V@9nAD=(CB2A`T)C&`5N6(=w^292D!tusR6Ht
z>GL%P+RL<PV4{zC`%#d7=7t-<yvr=Ahu#1);blM%GUYkI9AXwwIAfTZ)rGkjVJ@`N
z_a8@@(XYYbF=iU=?8liqmIC`8a|I>PCzxCoOiVJPKg6_6F@M+v-hKQ!p)k$td=m;Y
z%xL=H!aQ@?A+#2li%`|M)RvXOhY35@ts<z~vlhOBYYr?fo&6nI$baKWV{JsV%(~Q>
z^}ojfdW7}*KJ>b<9;7srD{IXWXt=TdC<XRW*0&GB{4v&BW57Pnau-9yofSoqDGycw
zrH(yWu~hi!#X9s2On9?SY{PhcSR1LZ-Iw)b5?Uu%-gLnAW3Av|g8W&Jehz!qldO5#
zJp{1M(9M!lEDsrmeVSE5%WNR4jseghmMc}W1+!}DuyTgAe;kq_ET=c27s`6A2ryx+
zcV}TKob@<WenqhM90fVcVrw80$@=jM)X%Zjt^<i;{YjN((X3x(P&jX8h1tQW7}n3U
zY+Yb=(!&|c`hm_`ajY%0QIBUGqI$iHtRz=RUSb_`fZ}CVC>5$Eu;RlpPght6%<v+S
z^(s|qTxIQ{MJS17OX=2R*35B$rLbzBL@Sjww+*dptjqBrX)NorUxHp|{Yu4n>8y9@
zD3QUsB!;C-mS7V|7Hb(D*>14z(oa5{Rr?Q2<gk|M!OLa6;DHh5vC`=Hn9q7q1e5~S
z>{~#&$r4f?u8@^|7M(?`mPr^YX0@FISP83#hFi+|*h)L8GL~mKWXf5E6i}~V{rM!A
zl`Pv8uvEn|cz{>U+8qPM8rC6iSgK`RrwgNXtaa~$)UyU@H`~B6(mSe=^++U8npn@>
zf%#_Eop^w?utpBRr`xRhEO^nzYIqLN?X21(^g`%hNmpT>J6YmUD0Z<1D6rPea-r4h
z4(my(A?#sYr`KpNi}N`ChJ7sQ2wMFt!}sv%F6(wM$N<Ys#eajWTU($$#5&Rs=wa5Q
zJHZ=aJxT?xqpX8;fnbcanPME{to$34f4Ikbj($56tkLTrldJ?K#yiD2+yeLSvjmiI
zoM!za0&j-(Egh+6S?U;&Io4P1FgVY0i-*Vp>*3{S*|Kw~7RZi0PT?+lws|GIaA3z<
zVAqkojtMWE*h`keduO&^JDvZIu=6gX*M)tXYVlmz2dQqrjlGD9XpgeFe*yFuTS5=~
zakgSTEV;AAwgB~D53Ga<Pxc3gLA=;s({u05o}{RV54)QSFkkk&rvQC|ow^?_KlU~X
z#QU>%_5$-HTWSQDHGsXv2O6i?qXPgv&F-ONMj-q7!;lGLyV02`n0-12*k{<A)<PqM
zZCU{m%4Qq}FN~dZ2<F4tsk1N<!G4V5rf1oo(Xt-NwspW<oMXF{0xXJMN`r`ISN;QX
zo?T28eKA(H>v4!)U_bCTKx5g#bc-X7ok6uz@$BJW;QmFn;vzsVu?r5M^D_J996%G;
zVf*0k74~=-ejbVJ)q?=N$}Vk#dJ=nza(v0`6P;+Kuy+lEm&$gi0=dS1hrV!`#vb;B
z+3Rd;M<GDd*^v*UnZaI5)eAS+i{;SIW)~I1?;Q4<J0X(Ge!U0I<gsNZ;7mTdno5ES
z*gAUdZ?d~L0JM;8X@X=C+m6bxi`f;FNG@SN^*&mq?2o#kP{z*FL$aK0N4Lx>*ris=
zkXEugyI{A9y-5sG%@)ujUc+8@7CzOo*?thIV|P{pyPjS5E)*NsN{S0Kvfr47LKEBM
z4}Y84w<#^%!v2>wG`HAC>5SIO-gym@x7p8C0IZGu$j_LPc6KS{r8?Nlm(%;NlO04G
z{4Vx7I&yWh*QLP39rnW?g7mPnsJyC|9oq-L``F$saHgM~Jq~gg{(=m!>!}!gkj?Q$
zYlzKi0N5~lbrZ-4+q4~)M%fb&!?iK?;!0qSvxTd{yT>kCL(ks?`wP@CE}ditw?Jl!
zy@>Shv)_Li2B+D5R3R|K4$@<Uv+SD97{wg>!I#mRXP>1@J`3!p_oCC5^Aw%B?Km}5
zMPtty-;3#X;5dH<;>a1L7rYZEZ7X=roKNU;sz*3Wv3amAb>aLx2lrh$578wbH%>B@
z3m)anH=uQllX3{W<DC3h7<A`M)dS6g^C7)DJUJIWf}>uX?VrQ0H>YDSM0_|A$HDXE
zM229XCpeu?f%tKbrehNPIghLdImvm;9SQ-QRa_Xdp5k!cfZ}ORr5&1qoa<kK1aY=~
zi_T!q`_IGgGn|Mhv_d#P)4L*+^E(BDA~==`{F%>kcF{gRlH-+v);Z1tSK)RP=OK!G
zL~~}eaOOOxl=cZRobqPyE^s0Q@F|w_C2auXteh?{G~+o|Z^&Ha<j}WGE^#)N!{BAk
zQSvl_b88yp3Wq~!h(yk2y3l`>^UrVSOyWHCBAiL)<c)%)aJ(rOlgiN#0_++m_eY?l
zaSAC$d7aZ@g86ig?i-K{&JqemXL77xG-6J&ICiBN=nc-|AE1%VIYFt49F7B33+Hkq
z=OCKLX-a|le2#J#cm<pyiu~W?e0&kug`BtPB7PA^OsiHgr^p0S!uhcRBP`_vra_^M
zGw>{+%Q;K_0I!0xZW_Ew&Wx2_qg9;G%rH^S`G(@fH5?W_hP9mSJy5LU<kE|?o|7B`
z#Rksr6cTRae6|^+iSsTUC7L->3U{?|+-To=i<2J;UMuHE3JKrlbW*0GjpIl6wAwj;
z&BAU6=Wi;8>*PFsk=Fb!&VBl@MK`D70Zh#u&Wm(v=;18+5}myq{>K<vAIFs{diy!k
zbV2Jb2Nf82@Ho?SvL58rQI+rz=LxDv8s^x^pf|$#_y~L&<v7uSag3A0hBM=w<3^Bs
z98W3CPH^so(fy-I&b~2dOmPOb!^C~g6}mA$%}EZ0-!q(T6ndED^n^lWj&t}kjAEX%
z+5zSlIGdb6Y`LqiL&1*QLs#tWxsTH7;lTZ2FMM+5Mo={K2zM<Vz+AX#UQlr5-k$@e
z8<*`u_m7Tp*HZlD7<b*vP(02}p=72zcY;FE9^4w5XHPCq0*Af00d%PJ=0*;~k`LFH
z&i=mKn`a?;f*bTA4Ek~Rt^|rd_Z<CXPjXk&c_@JUEnSp4#r^Y5ICGjiy$kjNxjbix
zScAAMO7H}8ds1QI40l;JG(xyXsAM{nyM_r9VcfiZ&<N+&(AR(>xK&h7a+do!En<<}
z_h|Jv$DPlCLKOE)+KWeX+v!@sd2Se`dt$ilRAF<0+x08lj^&=Bvws|SFBJjBTe+=N
zMstz-d@Haoar<cFdYSt=ow^ga&%48!E8Jh`sF=t-Nm0$K+*FEKCUO7x7cj}(ZrUTJ
zaAWC5n#w&e4bW>`(<1QFxDPCc!gVft9$@L*jAZC#aEmDIlF6-`M=OhKb^IB2Z*aS5
zxy$CJQ06X&dp{F@r(EuHPXR5DJ50N!d~TyXU<$ZzQXSb%?y{F4Qpi0-RT@Ry%k+pB
zb2ao*E#W>-<qD<TNJ^WOarb$`U^(|KI>c6R-=cD`O6~y)q*rk{|K<Oxxo@n5Mh*A%
z{eY?Edehg9>$t=Ccb!Y?xj#_Kpn<D+1A}SgZlhC96ZicW(Q4)vEQ5zFT<IFj>@Du<
zQGm8`U!c>%ZEogmwA#2)1l`WvLC;7Bcgrq7cXGEs0`)F#Vg>C#d$_OuhTdN8o=}iJ
z?pw3y?B~W00p>0@k1oCsa9!!L=^*!83Z4ydzkC8B!(6-XV19%f@-tea+=tVlFvd-4
zg2*_x_Xn7`$4#VqkO}U46_~t9ZhHYlrnu@@4B|d_`4;;BFVozYDU372jsF%hv)rK<
zpg+eQj)TlR*GQ4A1umCr4{dpZ2Owg{(=@^-d)_RaHXL~W`x34>@@}pIwi8c6|H8<b
zXD>nL5nkr^5OLu#8bDlmj-S98H{LwGM~?Dd@TB_BW4zASp>dqY9D{~CZwsBeJ$M&r
z+4AH)Lx~nI-Z!(b>&?4L;btG6qyuQaylyjmI>Gy$wy%CX6Gg)Pc|o*KKgsL*2qFQz
z`bJ=$;+2HLwbQ&ct{6)oFLNiRD~PvjH=wP-yf+Il`ZK&)x)~k9L)Zro9&dy~4`IAQ
zigAYX)=)w?f>&Zj=UJX+FIthjaTT!7@mgqwiQ@Tv3B73EgLLXX&oj2dd<-v`-l7+H
zwLXB3<=v!bGmdA|fmS?kIUTw$T6sH~fOd)ZJFO{~dD|X_QwhB2MQB~&?V^ZFBJcYo
zSh~tPtAnK^-mW_El6gPwfnExabsI3LymZ>PUgL#PY$lD@yb^lXd4rpwkj`8AB@{Av
z4^hZIlUKO`US#psu+VvfXPtZz4rlX<zd&yeuZu2k=JGDhz>7TI80{7Fd3%T9a3OE7
z6P-o8B@{g_=KU3h&Jvy@-SsKut#N{S8E;)9TIIa1zcBg=-cuh#vXUn}4ZSMfrV1!j
z^In>P7d5;!^!V2DHdv!zqK@ZGMXB|?%TpLr1Mf51RW|bOR)W{WtGEJ<X5Jn;=(g}|
z>8ZHITeKS{T6uL8Ucb$|LA&5K-rEX{sU5#S80_HL?}tJsubwvlT|D9c!0YB+IRM@r
zULB3PhbL^Iyh$(bW--k7@doQ*sh=11I5h6^_EKhbfEP&N*FoOy_rV+DInnw!%yTOM
z%m^=H8OSK_-FTpk@m{1o;yCZ0)d0K4+vETf6TD?AC`|I++YON^-aaM3?(?3$1CeQ-
z`0S&2{$_YRi=jBn+d=g{bG+pr!0tS6oFa$|JonA$wB@gHg@zsfiEQZG^K)k4p#wjd
zGG~r_?J1}`@oyGD#F;;F0SZU>_dbNA3%{3QV6OaSUx2vr18UHDl>aRy6^`-0J45xK
z$N57hFx~mDNzm)TFQRLYp8Q10IC$~<=@0A8f7u?yhp*fXyT1IJR7-S%UwQ@R{rDS7
zpzhCSkDzsupFIL+0{ABvFkPqkej!je&HpP3lMu*{nMW&#|NEy<2<FGu1I2oV@Afrl
z2;cEB=!f!sm%vgO-~R^8hx5xz;cx{1(BqirvwXL6;6?I>_knkgub}_<6~+IDw${=7
zC?R+k__wHHC6+Jz2<GGX4>MsYp0B4!>qUO<qu^cQpD2UmWq#Fr&`YrLRf|Bc@R54L
zqsIR>6pB~*&rZRaB)<RW;3f0V(9lx&AK!;FseJCA5V^*GbOXke#$WswK(F)rDTbWR
zU!dJe20w=?;xqY+=xmt9XSM_S2LD;A-pS@4_Cza(?=}QpF5fyyQK&rrH09{?`Q_wr
z0pGC~pf~v&=3%LjKTX$`i}-Il!bCB@;|df?_}49vEalsE0JMxh*o#&<e>JUI6@1^V
zn666x`Yv=<@g-DJP|at^Kx+71?eMUc{~Ntk>iAPuXV|UhhtmPBfxlrE1{?X8DR$7r
z_xc}N&HSHV0<VSt0ji~z-r}EF3jJ38+5KqU=AROy)yDrU0}Ac@Eqr*`!5^`QLMMN0
z9}IT!H@*jdyZJlQF^D_-XXs$i!@o>>kY2ta!wUUA{%9dA_47Yyh3H+r*9qtk@Sl4S
zpo9EbN~sR<7Y#vVn7?&BS|j|Qs9JE8|M6xhjPX|wz|uIMw;v++_!3%@CitNjU}=)?
zO-tw$Urv_-@AH*Q(VFJ(rtHZKzo85N|8VInf1J)^bNnrIL2RBspAY>7K9^D)wt~$g
zAa;T%+OgUTK0SnKa}d}?K*Ui{>xPz-;F2E0b`~&b%|9YI_&JD+Acj^;SAjo82i*jp
z(hb9-f-CeQa2Ko^!XP{Zt@jt<`STRSQ4GyX5dQ)cy>U1KwvT{ECrw|$q#ra+2>K>L
z`~;PM1IAzQ4js8p3W5(~gaLy0DYt)0P@4?iX~D_w0Tw8DdH^Uvf`F%i5-iyHGg@Z^
z@f1P}5v--3T&Q3h9mTC-g2NO;3m3#*gJOh0_%%S!3VxyBb)=w#_8I2{-M!#N3D#5a
zI$ALN3DC|9Ot(N{1g}ya;DTU>2T)=Kaa4>NCkR!*-*|zRirFp-Hc+|IB|%p;c$WqH
z=`l<Yq$EK7idA6p0d}IGg_f<Wf{^cFH%aj8Mt~*@dix-gB6xx-bW#N$({pf5;6|Nk
zg4lB~ab55Sh5ph7U0=Xbh9LM6j5kxz|1LVS1h1`z-VMQXJs{bF3smxzBUnN^w_L#z
z3M=FZtTpw}$QP7RX-|QmHUh1ig8lAru~4wd1sX+y1OK8`EclIrxg`QU1D&OU9h7-1
z6Bzz`@C4)3st~M5hI*yojZ<*6N>EF63e^G@#gJ<Rj6jIg3gXwme4QY1FGT7EE3FjZ
zY7iWp!gw16w_gW#lVGzqM4JUERH)D*NRNfcEy2{EXtfHew_(_~1rIz1m^K0X8MxLi
zc*+~DbqEq~L%maQ=@am}1QFRV(JknB4bXQ4UE!G69>D>!*DG)pK%`Ib*E%Y)>=z_`
zi{86}P}=7Y2nyQa_po4bDmq654?cv}sNi3k*)ak0F_<40bWr@|p5T#Ws80wSshVw4
zaKHi+Q-aC}blw-tUI3XEd`er}8No#=0iG3T7C~fA@aiAHoENn3r~1zYfovyaY=zH!
z1yAjS{i`twd*Q3$AP&MKJ%Di(9-=&glkh>>9ytql_dwx@u!*iSxCk#&VA@r9@D6xx
zLe*NJ92G8>gB%lDDcy5i$f6C6yKw3X-1ZQjrRnk%KIuj8KQG}MwDI&7Ds-^qBaD6%
zXuiTeM`)Z7I@3bqC#<-SVfzcWHbC*DFzFfa0)$nRRX8R5=wXPQ7Jg69cAzkGKX^gH
zPzgw|aAp@o&In7m;DrcxPM{SkRJ{#enD99ok~Lh|OZ$un;nr}Fv%*#MqK_2vY1uj_
z+(rriDB&_1Q?#(M53TdUmEXX_7~$u1=D8rurZixz(0M)PB2HLs175sv+d2&NqHq=7
z@JlZV-+C8zFAG1T(wYRJ-5(ISBK&C;yhyYPFVcJAs_^kk&`%P|C<dJ@%%+%Oig2kB
zUZe^yAApH#LjF-0OcUl%dh5FI8LHAx7w&okXc@v^c7vBG9Df?EEaCFMVd;kOt9+<u
z3#0#ndX8{97SOrEZRen#CzMkyY`)MM^$BQ!P)LOtH-&ep60uPD&t_m333oSvS1f!o
z9<37LVrQ5r6~3|oFlEA>pMg{g6OX~|D&a3;7_1fs`(R8p!e!^6S1Vl6iqY2z#g5?B
z3ty#hbAzy257H>SMBg}S6254qDywE;B$bc12#e_o=q=$C#a&y43R}qB7Jfmc+HJy}
zW?;7qb^qO^6kd57yiQ>)Ee%~l$w7#83kQ>-cSpF1QtdrLdy2XD3O#9;)F)&`W19Pg
zU%7#ISLjO{-2tJ`IK@8)g&&0hdr0UJ1dU<gPxL*85uslLWJZN^lt360e#8RIxG;r&
z7x#pY<o<+k@C%?#3e~jTm=dPPpmksPt{=ubEgaqs=o#U26h)mCenD5i=Y$zl#yKy1
zn!*YT!Uuk)_n)muNkJ?-Q9&Mvy=W;_V>^g0Q!>+0w8IfCC(-xc!V727_>(YyMAT~o
zo{Q++WAM;b6jcCFH&M<oEFBf$KLg{z6Fo^g`r{%dRXe$h95P_uL-chkIz2^i(0kKM
zwBb8?|9Oi#YoOsHx_1MjzM>1h@a=?X^*eCJPt-RC;xEdkXZxgRWE*$^qL1mbM5jdG
zQ%&4y(F@za3lyd8Kr2X8>;p@|qQ*ZUc}BE}j>{pUzaGR3K2&s=1{fw{QYboHbkzcT
z)(BB@2V~BQj1(k^6wOhI&N<Pqw4aL-Eu*I@TEt<1oEQ0BMQ4oYRXT!P5Q!*OA1iX9
z2R2UhCzXcBiwY<Neo^#19aJxgA}H*1MPyqF^+Zu3)s|fq{n-zaB>IGw;AE?4_wQh)
zh??n%OBHRS5ZpD<lhI(NiFVLchwGw$7h{6cMN>b3mmzvC3!s^zRkRt-5-nK;azkWH
zz+kdPaz03osHO=+$`vh<z>7SQhEAIKqCNCAiUN^Ngw{<Fn{K2OimaoQS}77O_6K&c
z=qoxsmx#m%z$_Jc9ffOUBF1xQm5X-j;YEe$=py{eDn%(&rc@;|Ql)maD1hQNHKJ8(
zVZK(hF%b%NqJIxVvR?H45O@uu7COW>ic%;x(<ItNPgAof+nNa4BKrI#VBZq0*^cqH
zijGAB^tR|GMKIb#RTS257kN>EZHFjY1D`rYh8B=6kzptFx<!{8AaY04V+-sa(RRw7
z^onjRg+ia`OA0&ni|X0n-4%JQhlc|q;WqFFMd?pc{Bub38$FK0qNnLe9})fX1UwxT
zbx^2gOcYHq=y8#~3X1nc`>9xJLS$D2-lS;p6<C@Q_2mQmzUatbAk(5}VnJp^QxqSY
z73tT({G2G6VrTQB!y7Q%1yNHw%-f3F{OI|!6aO>}G<)&qv<Y_*?+`-KQJhF&R44HZ
zl_1XIFfqn^MBLv5;v!y5XC7Da;+5dJiQ7CeT}Q>)RKR>p-1ZO*9v5%g0x);6;vghF
z#MM+i;3<AB8X{ieRSq!kEnbFKt97Z5IN(P(<tILP621OnKU#ZFinBt{86f8N!|zjK
ze@Y{s7LU-DAW$4Y`Q0G#>#xFYu=ooZX6B6eq&rB6IA<OPL&f%#TnH04Qq^9#xGf&7
z2=Nph#m|ZpHvlYBTtQns>p5|m2hgI#fk%NIEoOv5=Dc`r1~4&V)?Sbc;^!%u5-a}f
zcfiDnFQ#G=;>B;#zUrbli#Dv6#F?~qUKSrLf=>zJV>_UCMSM&K?-Rw3I|K8oxNHv;
zlEhV6=u8&pK803_Rs5(1*s0=zRnWgC{(L2{)5LoyZggGjO2N%^v4J`>#A;_KW{O`O
z1X`B(G!+Zq5Wl$zyln9)1zgJ!U!%}nuK43gVCRW#C?%6G_N2O~0<r&97`iF$ZU<(e
zxcpDJT_m=CN%@vyan>8~yF`46mi|)l&KNMu#E1TdiE{A|v^%R1=h2E-DSrJ|h*XIu
zK7ohTV(UftR3jb`f>$d>@gN>N@zr4P>c!Xgz<h()?;7kjidRwwxk<eJ44|9EVUMA+
zMf{YNjw!dq85Est6*pXmrQ6~ylw5BU*B%6E7k@#il@9UW8==@K9;3&<OFT*0v2L*w
zWvB0mBgcT!Bd+@wq*vUj0ZN~^$``Kni(mK_(09e@KS6ImysHwtLGhW-p*|!QKW)We
zhQ%H?Au}T0Z;#$l@c~!BjEQ3=V18WuHhq%no;bvS)|B{3+GpGs&-H^$i?<2TIV0}K
zforqkZkn|@v7JABnip46Aa6mOS`T6?>GptmJBcO<diIh*J779Uetv-BFOHI*ufw2|
zWb_hzbCz^ak;xHB3nj^2B;5ZVHOW=lxVlLM6jnSc*|Qcf$0UB+(Ro}_8V5;tNf~Vd
zJR}E8K|Ce<?!yZ&$?!#3@|GMZ#5jE<Mel;=E3u=O=?O`Kk-op|CkaS_i~f>FDcp5Z
z5>g6gfFybx`lloxQF#2c<ovG?36vyW0xw81O$AZGlDBIxrZbWk8vz<3`R-G=7AooP
zfL@rSaWz`ul2z{lGeRN=LhGzVPpej>M0X41oTOw2)U8pH5&A}2w1iEiljkK{o6(Aq
z?52h4f~2nkow1Vsd<-;B@(z`X#Y>*b2k1q~!Y3e?Br7NhdRdZH0MG=<ego96NDQ6u
zH&J5kMdww?N_Y5_Bss2uda~p@I*z4CdMIC#YL%>V0P~uJ^EDLHBn$IkUY9(z79?Hr
z{^PKlA^BQ|*~^qvQEhjY<nwoceM1sE1YWj8L7(W&kuW~SU~(ltQ7KWL<c+Pcn=dIU
z17?B5n~qF3CEp<3v$Rmskqa-1B<ACAyI5k~K>L&u$=G#(mP&Z^cPf*7Oabb0$?rKp
ztB~wD475tg@z0=GB~k2#Yt@n-+KAOi+Pff9D{-J5a-Af^A3ilorlZhml7#&Y$!3YX
z2CWuJ*F!+LC0QAX;kHT|??dvo<d~HP(<TxB41?{G04mPzkbHCjUUW*H&_Je3GDAfs
z-I5l1@a{;mXi9q|^_0)<mGEfk?vtz!g+jk1H6L?vSJJ8iZ$Ps56DSNyCTQ}8B({fP
zcUWSg>q{e&b1L{WDj8ow@s}~ld$fj*OFSdMyeBzF_ZTK5oA1M?Ny%e$u%D8QeT@0K
zFL8MtpwkllKLDMPI8tnMR??9PgL9JDci_ytWO)Hv3zFrDFkvg5r$C^cbcSy1*-N)w
z1ek*~hKidVr3*63zdK2-^cr=R>SjQWNE0ad<sx;-hlZ=vJpq>7r1lhOIx0Ot(bQwo
zzbWH>T<S%umb-K-C6qm+xhxp;lxiq8>Ls0{x2U)Db|wblBRx--h<&9(D%Ct8J$M8>
zKWU+so<D!-g$;1=q|~JcXaUlL^cOuPeU&aCoR&TohE||d&WFJu>C#ux3YK1>%C9rh
z#vX`-NJAe0TBx++F^Ggozo1nsT)HD3m=V(PG}t{WeS0&;5-BaCBA|0pFRGM@lJ@Nf
zm^E4|u>teE^l@4>W26#FCtQ%W3*k(x)I__{IO(JBp%pKEs}mv@rJ;eabV<6@9+oak
z_mXP~QdSv8e??kI3u>aYZ38;5N-up0FOsCT3GgCW8nhmUQl#HfB}JNahaC)Ew@Uw|
zct*Ok^h-FEA?>PyVy5(ydcb5!uT_KGkiPpH>}E@^9EHO<(nNZH=1NDcK+BW9QUKTT
zr8j6FSRh^W4aiOD&si{0D1Ai%^&)BYU0@bV7g6m}iBv_wky2?3MF-2IR`CGbD3@CN
zVWL7>ngNF^rLXa!SS7_?4Ud{M;Rz_#NPnOLmRhM3Ev$9Yy>zm!mwI|ZuR*%>H@Ma)
z)l>eiNje__UbD2c6DTcG&qVNUNmt9D-YTt(gvf2_UD`OdVY(=B-!A=|R-X=Oz;|GF
zN<AI{>5?kxe9<jkOsCj8Qg5m!>5=|QJE>l2l|8)ZlRoe|hSo1lp?B0>X<0f<3`n=w
z0dr6~7YDmT(w#l<eps4Mak&v`&>#$rN@D{7Jtm#{o1VXM=|DJ|_oNebXiZ3WJP5@}
zX~#D}o06X4gLhx*8idxg^ndB#%}8yM&^aqTO8--FPP%(Bc=OWB6dPTT;%i5E@MK3Q
zHfkr^+>VyL%ytP{4zjkLXgSI@^WdSA%sZLtubpM~|7|X1Us2S|Mb@+kpsuoCDqzA*
z*18-6Ju1sN48>!zS19ywTqc|VahEB7gMx?byEP!5vM@W$nwRXEzrpjCy*vm7AK4}e
zP<&-S(l+#jtRMzpeljm6%=^n$;2R*;r6*-Q%ODyc`;}I&Q?h@Y&^j&aqpK{zvdKcs
z`We~5t56J)wb7l^P#K3#p<%L-)tIhuS&|NV5wiTxFu`YKdu8a1lsy;#k#n-0S(uq9
z8Hc`}5iPq&rL^Z|&P8a&$SSDb+j>EE=MlIVE89Wax;U8~9be;Rf%LB=F3R@P`R|e}
z@J+y6mR+FuOM=Yo445mj1C)J9lm+)d;i}A*PU}gsRkgrQmIbxK?G)Lk&q5(p_LdaT
z*JM9W!C;!~B%Noj%RZtbe7aTk{t9Sh$ljx1d!{UlavNE)A_t8AhU^S|7cX13YXSN>
zvhZtA%$2=&2_kv2!5@H@FO$%ot3dYtfAJGpH2sbXWm`7^yGXW(qM60AZ(5*GB2$ou
zrLqCaQkBUDs)1Q9v%WxOT@|wJ&hVmAHs1thl`QQfoT-)>Q!&CCStn(LYGvIIfmbJc
z;T}l6EbV=aut9c+4bVneIE6u*WbfTUt6AnNf=?|nK5av9$zDDWlvY_?Ia;@6f73g;
zO*TmWw#$C9{sWB;na3(<bjnJ<hutpO=P!bE%NVq5-I1k5!nGcm*B~@{Wg96^+9xaD
z0)>9r%QW40Wv&`v56H&rAu=d)`~X86l3lICBn-<g{f*8MnY#nXsBG6_D2&Nose$+7
zvYFQ?{&`Q<`~t{?>|P0&lQJ9H`Ax|d=*M<n#u-BAv}|B6e43GY3ji}K`?v#SPIin^
zleY4wPQbjK{KkiH&0fBiDpVchtyEa#D1Yezc;O_^q{FDQyot*5kI27y0KYC5`LGk6
z|6Jwn6clok@4E+?qw?`KXdIIV(wX+Sd_5HuyUT<3!IFpkAtPM#l;5SIHZS=H7a-{^
z*U}EkN8UgoM_+k6U6nl{uPOzYpFH6Mp!myICW4%l8!1c{AYW#Ok)4wFzedmBX?YIC
zN&@9J*?<X>9}NdHSbo3^jWhDyFJbf{@~`RC9V&l`iV(u&TzW>r<x=u6LZ0w8d^#&%
z^%^82<);GR#W{K88)!wz*V4u@S}w`L0ME-)X@!W9FUbJ!f_!iihODvjL$qwg$#+pw
zF<x$_DZMCPu@8!u<kg+PzAR_&0xv<n?<~j_`Mb}+i$uAr9C}yfw=yA_B+sL_XtLbv
z17N4fU-bY=s(kf%C|r}j#ehPZeC{yJUzb1sGCI@cO?xqi8CH2n8elTzwmD#C$)D6h
z^oIPWae!vacjuv%BVR$M?p*ohGf>Qv2hy67FVCV=cY&Ny4w#$r{3~b`%Kv;HU`6uP
zW`GsThiovy5_$Fa=q#0A%Y|N<e6J1)<?^0%Sg4R&)x(gfl-JYeX{+SAuc25iA6Ejc
zMjk*Lxmx)S`UTg?KfMiS>g5-CP-u`>HAA6Mo^casP4d+*p|e@ec?Nnda^4c4+>$T7
z241WD$2&l2m;aBBv>ozT+O%}az2~6bB`>rJF<;&ChkPJ<NB$0_%zNZM&hWHXuK66K
zPrjOpO8eyjmC(2=Po#bGfZW&u-k^LFMQVoR|GW;7VR`a;V2{X)Y2!I6e|G}2HYR^v
z31`OTFTDzKPd<Gf_9o;vDWp3ozkHJ7FH>?kU4ObSul=vqS^fuw$!FwD5}lR*vJxid
z<Xc{Vhx78&UjchTE-M7KtzvBvh@IlxX<*wcCa5aKL2=|`v>X*89u%Auuf6~UXT@`C
zfO$kQK^6QiipS}A;;MMRm+H^l6q!u8e^hb%JY<e3ia1~%S2)tH!(DN$4deAtyuA^`
zQ}G<tSbHfvDGTDQNIHp0@KMZo0@PQrIv?bOVq_ik{1o@;?xw%u0xh#A6_vDu3Q#;s
ztKBJub06G3t@z*)<sSkSozsvBQtax2-@%H{b^-K^V#Nt`hA94e89s$7cAzX}X_z93
z_5$IGW}4XuMU@XE&nmXkBOa-!xrli>rzlT_WR#+mPEOH^u})0vd4($#V#O#lOEEzg
z6d^Srv5MLl@T_r)B_7a^SFE6L*G0vCx(9nnv7h4VmlZq;FefNfp3u0WxN`)ciHbKV
z+;vs)*bVrbq_Cr-K(b;Rg}YJ|h4WBIRg5m6bxqOr5<E;(tQ|q?x}qr=ymUnog~u}#
za{7L5rd9F$YQSVEI4=VxN5MahVdpAt(4~kxMR^rSzJikk_X`v^wUE52NUZ{Bp<>s2
zfGJX3?f|b?(Tl&#(h^1RDOf616j1d*nWCEh1!%dVYY;P2q1b*K7Ah6n>1S1?xJ8@0
zYK67x1Yl|ut5-pzR#AHlCh8QUpFpNwp?VaG4T@J=!E02g7l78Jc!8oK%?h&|6V#&6
zt_AOwBAy<ORz<Qcc()Y|^aE~Ftm{E%yP|&t1MN_>OrzDQ@YxR1rEpV2y<4%#`Y-4m
zg%9m2dlWp%FZC+!wt)004%6b<ulV~Rn7FIZ?m_2(!v6<&IH=IQ1owv&Cny&)thmDj
z8Bq*U9p$LvCS80OQy6xmb6k-Y2laajT_1Q8iX=LmO)CCJ8=@)2hAuiT+*eG{0exEW
zDeZe_6j#qcV^(qZb+qObbDQDtydrxGS_=v#)p*(}w>=MRJEdU+Eqmn<J%0{Lm)|f@
zN97}wsB}_3MyGCP<sK=>5#{s$;E(2_G(8SIS7qV<VAf6fVj9I?jw<7BqIpa?LZ8Mt
zt}NURG<RkF-+=K@`p{9)Q@L*dEidI+3L$ta7btk<qipI2sIT%2Rmz-DuA{f1pYo4Z
z5PzlXX;?a`ywQxmNPx1V3Ye#qfnPx3w6dBu|AERQi|PAIK}uwM@Zc$1j)I&~vZr7v
zL|IE$!9taaT$m42UZ$K`xbjRic#%r?zW{Si`HBH1qLgn?Rv}us<qqtgS3YgRAYzoy
zxj^KCvV?N;vC3L{@5U*Uqo5G4R5?N6qB1iE7Oa<)vp+!evXWJgp(QB)?gqJ{G|?6}
zQF)kNbyt-UL4Zk8ZqEZRS^50m;H4;A>5DI^%0Vaat|>pE#V<`+OR3H4%60T2NLOw*
z!0im>*AyekR5IwtlBMkb6Xb@n^dWeWZB@P-2(%pKlg02NSGk`GzVnpYUtl+1xzGS!
zfzl%smToF%wLmLW{_X>VMau8!FIueBH$tIA`C~a+rOGd;$g52GW&jk*m2c8iRw&=6
zKYFFoNS`jLQp)4ds#e;iLb66_{caw<)hf?C3TB;hZz|lcS8Aykpg|cgg{4NN??LdI
zlr~hN)~wXhqtc>$mo6^cQcloGrd8?oAQWyZPd$h+wJBXFlGd)Q9Y<$}GA|4woyu2e
zOWmccq0>UQ^34rUzoRr;jqtQbnfoOM+N)e148=a>-?ZiHR}S-G{;u+4I^_%~J?ZT~
zs8sHNGegRO8t{gdJs-lvh%%mDW24Ht=RwAl8)=U@uDsC)a!<LQK20;Be3qV=N#zK=
zVW*UF`vG=eX}wGNziH*_bMS3O>0bf;S>^vIk3Oeda|M>>l`p*tvY^bP?2D~RwG}Np
z)mu+N!CrOD1K19#UKWU>>YW!soK%0Mf#;$co`oe>6^HWRZmJyGI388i(r3z#sY19I
z=W*4xja2{Xt~yWG0X<Z8^y~IiozTLBmnx?OGTy31=g{&|#WsQGt2!ox7bjFDRQTzq
zde{a2`m4784&F)CR(B`_sH)yT=P6Y#T{J$eTKo%0pz8V*Mjxc=KM$~A)mIGskj|*o
z2(((4hN$A{L=mb|Jqq8#RM9)35w6<)3QR<(d?~wqRu#g8-AGm92DHwpBF8|YREf0!
zjaI#4fZg+|EIK5`sG{g_c0u(|B7BNfF|GkKP9>zew|Lb<J!oB2MbV|COR9G$++@A1
ziVMcHC8*ZUz_%-^pC}KWs8SaL=Bnz&Pti(JoymuOvg+@LU@%4X1SNJ;Rjb6%zoxRI
zja-__$qTLPDh{2M(p4pgftjJIrx$&uO8pcRvQ#4+bly;f6{D4{s->TLj#V`yh230L
zloHr^Dpo(3`KpZ+Vl7ZjQ$5yARY3@_3st{72$3R{-wq74SheXB@JdwQyaa_(RrL+<
z%2a_X&?;ATQ7EfIwI~hqRH-_;5f-XcSE(+sTD9mN)N53s^ir%<S#vhSQk|-!6QihC
zxdlR_LA7TE3^uCvn$X##5@tfQS+$d1u`MdiPPA^Ric&#ZRlFZTZmVSU%WqT3X-m+q
zdi_UCLWgQq2|7DfGY8P>Qr$WW^WCcFXiIQMwMhi9KGkd1KOxhv8i;|+UDfn?*d0*$
z(O+gzh5u!OM@^M|2a3b0$&J7sQ7wNQlB23xO81PZ@V~9_sHw(ILE)b2-?!14P{q<~
za8k8XgbA8bZCr_&xv%<n9fm!vvUvi$85O4rowKSce|rDTsluN{@4V^}ZwzKZ6+<=0
zw(6zJA!DcBD~6)IdVVch4(cM>7dfhbpvBrro#F-sXEnnG>POVMe&D&N>$d^ZRXune
z#7!+;2i{S2o-e#Vrhb+xFOREtEr92)&RM<!&!30-1Ik2us(qq?=B3_2^$OnV)0Fr3
zQNQ;&EcvQ)DfN6pJ#rQLe(KksfWE)_^>rX8)w3+jMSyyL2|PTd?g)Vwr`4nPpdP56
zrLAI+dUGpU!RoI*MC**Y_(`CIsCQu1vMvo(7bQSHO#S%^^oFaSNCQlSx|hzRXVp*8
zHYZa3(<PWcr#{e)R+KuQ!VA&rC(odDUfn_uM~wO|Ex{MmPE@B5tKLa*pExy#wy5!H
zCEb6xsP_IByi4jm{eZr#Zg>FWv?i#J(dTEbsAtLVM0E@mDqK~6O)teH^^VVgova?B
z3Y`@7$8@PMRXs(?$ZP8DS}3Hc+lDZC*VSKA3_4w%Bm*x)T~F7QGu2!E0(6#oBURhq
zP^bC8r)>57vw+S~zcz=?T&uc+zIc|W*3<DQU+qZY!2)&hIP`C-pY}$pSiOA!trGRK
z^i-6p5A1^7GWF$GK+4t0XJMj3Ei*!-QZ06aLX}z*0L*IjbN>Y{)jch+RI46-8X|S-
zpYq^nz52^_u-Blr`mKOQqgs)G-X`^S`aoo}`rMOXwy3vl!O(80M}9_UtNPMYAh*@K
zhrnx7Z~h8{X;*J{0%(VN?j%ffs+V=cnJ)EL{{XXF?YsjX-cj3a2Xv3RoI;Jg>fOts
z(5KFwhI+sHCF`$f-c_%mve^N3DV<FR)#7TP4XMk&hW@bHi9!z}>PKFO`BC*QCSb<Y
z?X+r*tLM%D`=0tS`gu*LW8Q(@q<Z5acrm4Rr<%6=>Jt=fpH}DJg2;?IBN8IBY9Fd&
zo>Tw0j^2Os>Yz_CUkmEcUw~$-DW{;0on|u&`u3VO+OIok-k=Dtqeek*B_~Y{ZF-zF
z|D(c+BO3j`aN9-mYca50H9yd6!A<ibWlxT3{<cHwn5MuP>c=%}=$-7YS+oqqL$l*H
z-GBGgJbfCLyfh(0Fz>B#rjw?RX5)XkI?YyEwoYi$!U5x_Nv?r;e@!86Cr@hD9Rvx`
z<kAy!N^_XDSEn`obx;q~T%u5Nkmk=^coD4mmufrDXr7~Lm=I0LJ+wkK@eF$Y!Ze#`
z)eP78(+5H#H1~c3IjfnZEM}ypfnLVvG=@NkL}}QR)QHwBq1euO%{Q?aZ;a;IF|-mi
zziolS70t9a2AZfbw8K)0#`rkqIaTvH{noE(oa`Wyp$VmES*AuxMOxM@%`;9gQKb2e
z>Pbp8uOEa=sV0E33T2u*^y@Cyd{2L$3e7|Zuq!n>3QSjNBIqn#tr?>ONsUH95w$wa
zosS_|uW3Guscg__=%v`GSx%J&O`5+SM%1fW^D}*{<d#Mq1w*Y?jXWP?x~+LL4s+6`
z@wo;4c1?XgTAiAoXld!vB+{oBx;4YTK)a(kP4&G!np|J#_i9{d^7=GS`at2X#z^b(
zfaWKPObu%OiUV&*bJ>8-Va*sNR!1}zilUBc{-V9~n8td6eo5mRuS_uSX#|OAO=vv4
zfHtX-ya&5enq(P#y07_(Hp<hQg4fZS)kMDt>^V(0CFSQe;Sa*m1<mzwpxA2FHbAk{
zenx=^2d!rr+;-GHW{)Xx(mLA0uCvyIwoXU1`>cHcb=Cg36Z&pib0b<uwUcxu`It7k
z8|1k5>$joruJxyrjEDA_Yam|QYRVCKYXd4_$w&LlPr&xo26e#v32kC8h@V!s8{P+K
zf0e@0DeZtGoH?!KQr0z4tN9naAZ>fO6==a)GwlgNwe^`8TA22;mmm|aT}G98k=or-
zcyUg9Yz=r(+G-z=7_Ghz1}|tg{{{20+LeWnyr{iD3du{_t2kCIy{x@XL9;|{0>!nj
zY8_GQyfjI>NrhIbHl`NdU(@mq(f60qv`amJmZ2TYgJP!kpSR(Dme%?(S~s-cMZ;jW
zR^5wMj`nN%CFE<9;?P;3T~dP9P3^P)#on}GSAkumZKi+XTdXaV!<jN|9o?BJ*OpN>
zuR?n=0h3UvZPvkjmG&)Xdj6`l{H<u#X`ARUTdx%@gG_^V1#QoowVeW>wP*te@T0k<
zeJ}~FHtmZFIMc2@OTmH;?E%WvcWPg$g^4ch)?FBAw>FyIse{^Ive7xDohgUNuy%~b
zGNLUk!e3-m>#PLNI;Lf=L33RDI&BN@Y3F0mn$WKO7%-FCO=*ys(%zu8_rA7qD@3NX
zdt%`4jP||&XtUbS=nENh+Urll#JqN%>Yx|2l~l=Vt9#9giM7-HF^^7r-2{Dq-a+^0
z0f0H`O6hLAlT~-Q6N7QqWxj>pBRXj=#^j>&ryZ-S?!<TCx#`YQ^!TXm2|8dO(|var
z=8x;DgMsa?3;Y+vLwA@iuzKrOUx&Jn?ke3h^wsUA%=Zc1Ga(>;y6U^&`RgLCgLhJQ
z{A<_?&{=&J!KqWa;`L|->At69Rj_Wudmv|Y!gRP8qBGB8E<$x1DQ6v~>%0Lk!gXsY
zvl^lMa1}((>iX#!iPX&q(0NX$-2?R~ot7?WMeC%r6FRT^FbXI!y635OB38Fa0EIZ+
zlr<7GUROea#EZK6+rYl03!?A)T-H@n7&TF6>j{{vx=)P|Nzxsm+R|j5Nd;btZYgcF
zQ+1mtQF2Y^v;`if>6o<fysk^gz?7uxl=QpE(495{B~$0G#dKxqyk3Td8@i2uS~0WP
zy2SG!xw<GyK^5p8por&9T{pel3U$%v0a~Qn8V!wN9j_d%65Tr~P$<=<)BC<m*Ze7X
z<+{H&fmG<C>1AB0({(_-O6Npp=xUvQ14xZ7<-a0yo%U<YT7xb&o6diYx(%0s)}&i`
z5Tsd`xfGx+x`!9w@NM0i2hnQNG02&Aoe$*}J9Oz0(C^fhJpz#~ok|UnZrwSmL%E|{
zVuu;+(Z$m_s#h04f!aQubP}EYx{gO-;jV7`Af{_T_cE4O>(W8pOE05$M0eGUsTtQv
zPDAvbuKg$!Cv^5@;7#h{TA?weE2ib@zV6;fur#e}{~5d)-4pA<o7H_t^#*gg+TBo}
z*L~WC&IR2P+LqbtSN#U!pwEkjqmFv^UQCdaKA)=Ktj>D;BSZZ1_3u!a+(o}Q44|(1
zC3Gls)8D1l>!`ls8Gs(shkl0Eas9?Z=zHq__apSZ^rIJ{=dDko(hVQIgDr@!-ZcrB
zC-hzv966~klf!O+zNrn~pVIgK0F=}ECs#r}(5m-wLvN7&6ir)*K8QjOq54kxU4-dZ
zbVDXwf1v;dBlK#TgtPi}VE~QP+bhsIr(g0M6r%KN-iJc8zB?RX=k;Bo7;lXJ^VQHx
z(0}qFM6T%fBHX+*QNN4g@mKXbPJoxBx8C;xTC#rg70h0W-mwabsrnH5WbQTnKQF-V
zG`;6ukn8%<??BS^f6yi%L*E&NR;E5`29jC&CCh<*L;uBbfMx4Hr4=nlzttBea`jXG
z=*-hc($b%=PoVf`f&SlZFmzLIvC=82P(M%4QIS6E8-Nz;ga3eNi9UmB0891J`!KXJ
zy}dm^%k}xRZK%+{M=NTj{{1&#qDmh-4ZUjpr)Mzw8hxAz&eZA~sCc1H|CAZf_4=7N
z;An&XP#(-T>YeC$Z_;P4pars7zfugD7X9gep?FJwoYu)!{k6v-b6c;cKvSFE(H)lB
z^;hZoREPdI3d3~j&(LYGOaCjSkh=BzsZ`~T-su7Gdh|9_2-2&cD??|W{`?&D`t^Bn
zAb0g6ze8a_zv2yg{|)LJjc5+(lR6<ftgpHZnGt>S4%i*l@1#pyWBP4tG5T?R^s^Yn
zJ^lTq@OMJbqd>-_-iB(#ru46rg51};^g?o4KTA2fIX#26`}6v5BpBy{zK{;8_J&0t
zK*YgNy@;MaM?=*z^g0>#--C>^p@$Z~BZh-+KyxunaWM*4!zC65>Snm{H588;mh&NU
z%y94vC>%E^$x(MhT?SenhCtfldK$i>EvlDc=WkH(HbnNp3m?O0v=;dq_&;K}{)V3^
z4R1YZcqa_z0}QXIp>fJkmJZR=hDLlFcxj*^iLPG+8OB$kGuW_eA4JX=-k>u?h@q5%
zU!jKi*MJsgNVNqo-0&11ya+?!*YN(Vf%hzUk%kW1@SZbVG63_u;c=>Vk1<TphV_Eg
z@LDmPiZwXBi&4ZG%H|*wZ|Hs&qqt~TPVbXThIT5gyKLC+0+9s6S9GGdVz}80{X|2;
zcW7NT1g?W*lHsRSn1p1*fmyhgVo+~@UaH|FP3$$pCdxRZ8SYR);&nr*2tK77tO<0D
zH^VSMZ_`Xe**KV41_|97yI~kQ57)8{A$3s9F{J(kgSmzW80gG1d`VIAe1l*uItvU(
z{s78NgESc47aG3%6zW9=hY*-AHatULekd_0E~8ay&`>RTnW4cS>g9%ytyGs>VVEGr
zO2dzIOT5ak^BxRV8^l6r)EHu`AX00XTn)Q*h6TD|TyJ=YLPHIP(MZ5F8ut7SgH47D
zRG-vrD0vuQErtP#o8B^nQ)H^ukUj*k+lDsU)wLO#X%pUV_{5G5r5%P)id=RYe)$E=
zF2fMr&+ajB>E?Q`p(Pn6`V0oj2=yCUWN6(r*wC(H!0>$~)CUb4X)ixy@ZAEvVMC(@
zU?T=C?WaZ!51fL(V}>faqc?7Nnii;ghVlnse!?I)MfvwhgSR^rrwk9bqxZhytunYj
zZ8-EN6lV+>J!s7uhH15)Gnj5eWZv-6c3>|UCLBR*jfZ>zYG+J13cL13+e~yi7-zP?
zprf%Y94#l~%l%MyHhz!;%p=CMzc4c{#@nkX|L1DF-v{$<#*%ZuK5A_G4CI*6^<|9d
zxbfNx0ChLM{TB2+j1_y}jHmH)Tflf3onC`oZzF3t{uDmO_FQ!O8lV3idMAu)DgWnZ
z{D2KTf8+Q^uyE2CL9PWDhsV%5W&CCfM69Qczonx$(D+3%u!D?~RGAcPbS(urV_dZx
z=0l86XT#x8W6C~|FymKyp&xF1XcZJ9jq7R4cg~nbPeqh5EgfD&8-ur@b>1kGLnOwS
za0@<NFuwZ{Bx8;IooK}wU!W@Rc&qV=ScqOUK1-iZykxYa1^u!yq8gnE#*uM!UNN%i
zW^<xZ`WB}2s<G~C@RE!PdW=5V_!`w!r5H7jLNC?mM>BiPsI|b0G~@CN7`$%GtA}2?
zQS1Y|8ODd|FzigD{4J0yqxIZbh~6-cQ93=_=u7*m9OGk;f|+X!FF<FW@ft;#@{O_Q
z0aIXnaVreoG_tAspwPJT7ffD}arPyM6dOPI9tKN{A`^I}#+N9IUuJCn4XtwH`!*1%
zFjiHeRcZY2bC|6%?z2*6w%X{RL2r%m-YSq<V-!Ux>Wtg2K%?H6O&3`kjE^3MMx*iO
z0!Wkbh1IazY}^wF6D`KBcQ6;Xj8P>Ztwu{C=Hj+7IS8c9c=&r*=rktMMy$*D^GR6f
zHa<EHNADOP9I>L=W8C%vM0<@37XaF4T(cjd{l>n2kh@0N9HwNzXr_GFpm7_WjE9Ub
zP_f3a(YO;LBgQq;aCFpol0Gy%W(;YA!nkog9ewT@v#3~c!nm1Mh)H8B)htdKzoY7%
z`^Ks->Hgoe@$d(LnK5qmK<}*4kt)6CjBQT?X5P4u0;dZ`(<Kbe*5s#!zjmg~Ntm}c
zooB(IgQ@0o=sB7KH-I>q-aZ0JXHz<b$&Q%fJ^_l0>Gu>k<7(2!f#+u0Nw;f`nhqxZ
z_x%Y|KSfTCn-~<KayPBp4-F5KFa72`O%Cob?`7JR2%o%7arB1wF>$Gg-Pg2?5401e
z9q+-CpK0ZOxaMzqg^SLUCI+nu0j5;C(0R)A64hUyHr0Fuut3ueTA6}O&Q#lC4L0>M
z0eZ${L$zXIrURXT2{*-_2Z=DL=!baD^bGCHqfC3L%s1Nf&l>o9!Sw8A@M29IdXdDL
z8jeFD$s}=srDRhSrBYK&O%w=BHE~*C>6*#J!LZXzTZQPnZaPmVm~^XYAH6CwOeK`1
z&NSukgJ_ni;t^Q7VRHQnFxjThn_(%()Jh9uuIbAiu#{&K(|Ic2boL*(R$wYBg2+u%
z`wEB@nzGgarO0HW(0Q?GfD}qh;orbusp*q75GgZlSqi;!ll6Hi6e~>4lvt`X$)@3c
zm1*WSoT)bbNF_EkrVk$lOs(k+x|&#Lx=pn}^(L<@C^VRAUci_dO?w;w+GKJiUb88K
z9yNUKNeyz#^z})QR+Duzytr*TMmKfaOk3!n*=|~Gb%SDuX)EPDI!$TxshBR4JRI(K
zo77D}yJMQ9>VqEBpAmrRHQk|*R-egz9Pam<MD%C6Yw~{{(=}i^LJ71%)5-{_519_l
z!^2^d1C`H=n1ZQ1c+@2S7LsEo9&KO8O|K_V;_#m74f-=rn2ytJ>q(PG94t+l8iZ)w
zH+@6pe$ytA2b`HPE&Uy2-sDDshy_!JC$MeJp0v5NGuP551?<fo7XjvAe(DxF9nHrc
zgh3~BD4h+R&ENb2%p>O1t&nsv2POPhe`c0Eh{3p--%SVFQFGWl3?4JDNP!o}%{w0g
z&)vM@eK_o4_NCo}r#a+T=zE!SC|2)n&ZFuOAM>kkLDJWpLFwTW<`F(D`I+CO+A@Fh
za$88AGQYhSou|#s^MDRCA9#fB9|f76sd6RQyfYUro-s=tAQNJ~D~C*|`BjQjhnW`>
zOt|?$ibzM8FHo@jta)!YNTj(m8qS<Eum21r%KUFU6r#;by8w3H{M~nejxnF1N9BU~
z)DED;nm?iXz&P^@w9~Z4n}3kQ{flNlE;KHgKcs8$m(8>EyGSs9QwV3SnCHcql0@_4
z^=Mr+H`3oA$sEN6NjCe_uQSE$@exR>`K8Z5u9;7bfux!1=}3Fs9QriOr<-rBfQK38
z!}aLQG*6UZELm1_lN#7J%$}4i%QjEi0W`;a^Gl2(*ZgEIVDijAZ-m`^b1Mh#7nmO_
zLhGivv=_WW^C%@xi_Ahgs1}>I(ciwrTuKS0Qgic5XqB1!0-#rJuF}DLh1vNT46xFC
zWi`C0GF!je2mNYu!E-QJW8OkJ`dV`v#X9QD6(6Cq-W*7Op9V97R`N#kW0VqYGJiJ;
zy=J%#m=^P0S|M(kLn)BZW;S_4q}}{jIt+H0y#_F{PV?1xsCSvCtKeF<`4zg#b;taS
z^;N+1m>ph$ey{ltsu}4sbH9Xszxlf?Xxud~dl(`EW+DB#2F*WHnrX=FLzQ{M=2MS>
zH)7sRk;7554^_&HnU4>FjGJFg2G~9GfkiMlVSZ{qIw#E>`Xx-8UEhTIjM;Iy6^gUw
z;(ox)nNyELbl&W^2)-?tCn?BbYx({zh@IuxSV-Di<ex*)!SVoYUK}k4mtne`Eb|Wo
z+u5?5Zm=D(#L&;f#qv}Z%)44RRL$vT`H_MJM=d}74v}M)C+P;;aZB#6RR7{`3Hu44
z9+sa8#?#_V0ZcE;&R%qSTheyGVIRvEw0-uq9Ot8T!ZLmZJU>g_9f0~<oM<gOX?djy
zjs{rvQ=asc#gPgyPh0j=dN<ILNsCvI<vrTy23sEX06Al6#jDl2G{o|S3!0&pTZO<5
zv%K61jd07KKSCqIQu+hzp0#{H+t5hM_e!{b&hi&MaZ#3Bs=bJ|I5fljd5d=oNQ~v1
zzc7dkmeQ?g#af=GRUpoCvkU6+mR#DPU$peo1%gYKtYoNLFIys)K{Ua#nf4i1EZ;HU
zMWW?T3Z7lH?4?XelI4$i=qFpQ&;~NavV{^Qsg}-<F~Qd??^C5rn#HyrDAz5ED4UmV
zY4b#9mgO4})NfcG*p61VrAGwy9Lwd$Ad+iYPelZIR?7<dyjQ+u%_cAlEKl45=uOMV
z6ooCcyc+~kWND|mjAF~$pJAfJl0avOQj78(w8|`bv<j44N;kknh2_u|45HHV3vDH;
zET#0muC~-u*0sj6mbP=XmP_>CIO{COU&jFJE!I^O(QdFDTo1)Y%k8z$XtGTG24|Wr
z^|a=<SUPjSyJZ=D7Is@LPtrd9w&h=nDYaQ*mq4N265a+6J1jL6HSV<7(UGgma>Wm%
z+Y;Xgy*rkTba?KuG*sZH(`#8@4D~)slvM+be#`ddaPh9Ch_+V)mS^Y&&Y;CP1=vHD
ze_X&Dw%nr{q!G*W&jV)E(zFLKW0taQAmf%qF)ZD)9L<K_geCoPkV(tuA>d6}9;1Zt
zearXsa+$XL{Rqg6<!g%i&RT?rtZ-w_;=O?0d5e}dYYUd1)zGlDdHNG{+Sx4Eqh)Us
zUkfw`o6S@t>1Z=SPpXrR_fc4Kv03>VI$dpE+Y1pl8y+37kJ_9Lz?2-bSwoTg<2Ix8
z<rH_DGAds1uqmN(Jx`l|q!j=3vax>=8s0YLFQC`Qrl$xK>}!)x5x^5Rb6Y_CY;IBP
zz~5%c7|2PR0~DwYuo2Kgamq$XYuRa=A<CBo+Vn@jV35sOswoY&Nu&!RXKXI62TF*I
zY#-(@)F$Io7z(p#Md_k-X}Ha$6zE6T{7Y5YXKhxxLow3kek&Bu*&L)$>Hj&p?zpV0
zE^dP~ZJU~zTG?yaw4S~9o|Fx<H?7pvmgT5Sdyp+CAVW3+%2Yr$f=t;PWC$vtAR?$B
zf(VGb-}Ca%`J8*t_ndR@^Beb`bMB9LhJOhBPGFp-zC^|k9q2p7xUPb>(~M~<HA`Z=
zK(}u);|E$2q%f8~0PYMU=S}ELWgI_-zBEQ6<#p2;|9K9584UJE@Yj~fI7y`+S&TK5
z0LW&vb;Hvf#)})#c$P7z8-vMZlsyKA^B8$b^qph;+6XS6@q85e3K;bd;6))Li?$F&
zj0hdf7c;K$AyUGKT?D{+hJtnyrHtR!08qyGU>(L%&bTlEK!uIr^dkmS$#}g4h$_aX
zbj?;XzI_pDY8ZRcAydnkCjr;MxcMF&Ze)}cK%|Lro-#_!jQqtAxxfgaY+wt+g}yt}
z%7~{Ra2sR$CJdsTv4!5=7a6b9%AkWWLXw?~raRy+F>KqO0OB&^z{_B-Fs9EzTNh&`
zWzM@9%YK2H9>)4c^j&4-pTx9XW30Esn0gsQ7s2&0`p2RBIwSHOSn6l=9|8OZ;}6Qy
z3@~cTp!z1`2t_Oh8LffvcZhM*8-QDk1BKvjGuXE0q5BRaV=d-nn6Zmar;jjV48Y%I
zym1kIql^KH`Q2k=(W7vTvECO-#~CZr;o5zM13d~S82cy${(x~Y5x7YP=PPhijMn?G
zG|kvbRcsF#^Iid9hS5(egGY?mm%+_4+EjG^IWV6Yhnj=T*Brq)GLz`~aAJmx0O-uz
zz7Ganm^*0lU73b2;DsA=4ZRfIncL{}@gXLA14KNSo|Js`WIp&5@Wagg8v!`Nl+t3@
zi@7Hd2ECa-?1oMs=0z`%qs-!$=HveJWyZb^pdT~-3CM&pohW7z#vIebQaE$NC@e)V
zAHR>eIL`cK9~vW>xdMnpF{Ax3-e~40bcXo^Glw==Cz<@4=!;>#PEpi&<_q%xPhei6
z&q60Mf210dQ_OEhA$gkl{l8TInZ*2iJJ@9A>p#KM6lNynP0lbspp```vr7k(#(YHQ
zXw#W{sWF3jl2!(p%%AAxmc=Zmt2>)HnG6#-%%3R4bCy|n7+fy1W(jb4O#fO)o?|Y{
z09VMoIs;O~EahX=wqj<I610RVj{!N)R8uUulzDFsd@5spv<7O*nL!kNs$d3C_NJ04
zUWCRf=84t#wW^sbC|y&-+(}!XTILlxom$6S*9Jg6v*`?eg9hg7RIAm<JU~&lCg$4;
zh%_@B{zl&g8`Dt%+Q$5X7R>F;7yb*Gi_9=B5FO0tDM-@E{ICahFEQs(5bHAYkpbii
zQ%#?i>S7+D>`6CMBF5zPF#nYTca>Sv4|0v^vK7jDnK|pArH`2t04>*<SyGUGCVvp)
zyuq|3M8fU>^Es;XyUBcv(zS!k8&rof#Qe4h+%2Z!JBZw7N<RVO4imw7+$zjJ0$^f<
z$$tUb?lKo<KxCBpIaPVwV_w?@XU3Qlqi}Sb`8e%<?=x!_!<h-D>pQrRrkJ15>U)~`
zlr0YQA+u`~mS&iSd~lDLKQZCVEc4Hwz#U|L*AC8+<wV4Z^<V~eoms!okM6>H>jvz)
zvX)WBwHxaNDdxhRwSc0ihgb)xoWz55mW4)7)}^Q5%wg6yRH}J|<wr+CyjY!Qss7BH
z)l(0I56fpiOdMs^{SJgL>w^{y)Q@$OVl4iwk0@^vz<Q$+jmKE$p9B}kay|?bL9DDM
zj47DKpjcxF>nRx;Ls|QJpfim1?~5Setn6zr6v6Ue4cu{7LN&NZ)-#P1e~DtfdKP1f
zW<5nY(G&P4Hn@|l!?cWzVZ~FeS1c?26)25kZTx>73hOK_B2KaHeG6w!vmT>ZVG?V}
z6dX-viIUKl!s?@fj5Dlfm%~yjYtJWur?D3N2a}M_a_)v?25S$taW=b5mWZBZS*%Ng
zn9FR|{PO_ju<YrgIm=3Lf@m@8;}@Z{gjGsUrt>UsT7i|ac$AwcV|@{XzH(M@7~qwx
zRhuw}RjlR?h*Y!EXhTuMN{EL@Elar#BK53$?a<l4O7}pYt&w%U60J?FelD~%vs~z>
zXkqOMLT4-MV|sYDv6fOfOFJv-|Dgxg2D%<QSiez0Mkni5B}6W<91cO`GRyNi%wJ*s
zrote)SQ`|u+s%qSg8}xiLTL|hmG$I*Aaaexrx$InjrHJT;QLs=c0%cO)}y_c%YN1-
zN(0_tt)aEv04wJUkejT{A}AeX1w95b#L9gYxLd4odJ5cT1-8Nb9oF8T(KyWdITPFn
z>*!o?cUjI9*B)hkX@&WFtOlwu9b?U{Lf<&cR!-}M`>ax0=1i~-s^Hrc%l-!_on|@E
zX7nK|dkE%dSo3M&`iRAO5t6g4vfWT~ke&D%8XegmQTWG+?K}zM%>ImlJ{LBQ0^qJ-
z8&`pIXFvG~%pYR^Mk!Gbb}j`VJ=x1_l;AnSK1taOFZT2Wh<dYAD4^%VerFE)j<V-$
zfl^=g)iD75*g2!<^Jni~3KGEfr>OHW_W1k21+w!>Ari#Splxq3dut;aL)h185gy8Z
zYC9~1vA-F|u*2E$bc`W_z5Xd1T930ecoWz~viI%>7sWpF4DiwHE%b&z!5*K57bn?)
zR39J1{(}BBQ!M-W%OG)V)_RD<v*j8964=LTF&Bw!4^NO&Z2v_dr`cVn@Y^S`AE*3m
zGW*7_@Gymae<8Rt>>3l*pQW?yBO#i>mYjjZnQSEmN3+<B_uzLnJC1ULIqW?YzRhL#
zQtB*^y@&^Lj(zh5NanN0=%HD_E~0>55xe0kaK-GGC=*=5uKX2!=h^Bi46u~_L=8mB
z*(c*Mqzd*^C=|EZRkDXYAXCL=Ed{Weoi_r}8uks!uGO;BU0|t>tuKH`J-dSvjt%VA
zCn3_vp0ficn%J%X-}A83;?a14{lQA;ZehPoE1_2Q@<}wdv7NIpvUc`!D*?F3=Ka6O
zn7wWjL~Nbx3EF#HVo!{s^D^5%22*o|y?+*#y4VBL@S>Z&pRT|j_A`{!xXNbG2KgHM
z!vxG_FFU#dW9nl+*8@kdvxl9bte^c#3hdrsFET)6fZZVnxyi0mpz#))L)GrL*}@{I
zzGGwCEd+j;9YB%G5w<r2GI!Zeya_Mvv5&tE;21lbiN<lZ_Z#5uv)@~b5l*n*JqJsZ
zY#t@arr7mMK&IK+XQAaGTS=9OGwdq5n`YTBae#B+oOgoVgPi4jaE_dgY`~p3w(Ebu
z4QI~Vv@&twd_dU<SI*Vt(B{U8raB{c&PK{K9^&kzbJ-po&RuYxoT&fTh;dfZ^>~Ey
z?owFt;tV_u;?3!P9gRMmuslr3QO@$Uu;9y4Q!dkw^DdQ|_;bFa{6PR`)J74tW1OKR
z=nmvaUWV=<PU2=Df;o$1a5#kX{*&kn<s>7JVi(3K`y2Rh&XNe=A~<93LCtZ_x?f>8
zk`wwaB%?UN_hBiTbB1DtF`Vya;YBRx_4B~RaV}7JJD$T+0-nJ6teMuIiJUJ!Me8Zf
z_OGEPi4*(-M3Xr?&Z04e(@(jlGo1bOa!cjZP--QOvyH;2=^PnFcr!W6<p5-Hme3Y6
zn=`)%zd;V?DcWD0<-A@9OSzmrieKh&>f7PkIZnSTCN`h5FqZP~1)OyQU<)}nsc@#4
z!|a7mB^*ckCfj+=;1-Zlj+9bCWt>7fYE;gtr~PgPr)oaDsN#I8h3;yOh)RiSIM2}2
zr<SwwP3WxS_?(8pdd?gwWoY1(Q7X2HbDi=Q&77xE_hPfVz`1w@h!&1{6rHV{fV=2y
z<CsbTZ0DS$!uk%*#&B?*9C;~BT;lvnkMPT!_19qc3a70OjXj(I84O<K{Ba!0u5p51
z#LV<^c6dUvk8_!dJ+5<@pTggMPB-n!1~{&%0N8GFGHKsA$Z^hx%n;|*Ezow0v-2jL
zxy=dw5Hfc-%l`ry;rzZBjdwX8j9~PmoC9wFaF26167Vt3dk)~nIeahZzRx-A4=od%
z3`#9N;GEkEZj!S;06tA|jBWrt<U}x_WyZ$wPJ_dbIFHj}ZI<%^eH+7pyJRUE4{}+X
zFhWOeyBea-+@x*L=E8mXci>&QZf*d$aZ@QE;Le?<XVD>UTnTU<T<_a3c$oVd9r`@N
zt)-fOFK)|2DD&nz<$?3z9--~-QLgP2)eie|o9J5i=X&fyX8>2{2@}V-?@}Hikn8_8
zNDy};2TDV^3n<(b#+@vMWH|Tv3UCqJtT}M)I5)K!-bZq6uVT8QxOH7{`vmu@D@0Cm
zE58FghWmXw8e_S?Q5rptn`=vjns}~_MxVgt(3ap7cP0=rr@4+)Y@EbhR*c4EZX)gP
zQ@9UTgFC~WlZC!it}E>Z)3^tAgQRnV7D6P0+w>)dmdVYRK}$9l&llVd+#M7>I?K(P
z4=-}LU&TO69`_d=tv}CkcLW2N&;4x*GKJjVXdhO@U1R_$<`z)&sf7FRIMkfyhOGrx
z%H8A&6J^|@dXNh43d+`2a&J)BsEXS~o1JRzQ#SO~a98cY%+zwLln|-o{`V+I19vPG
zeT`i4cKZLfO<XgDW16`etI&FZYub;gY2$AE5+iKq3fXY&B6r?n0CsTm=sN?Q-1T8-
zyu@vxo#JI~a0o~jcZgnY-Q2ab>geGP^uph(+#Nr|{57ugUa0Qn{;L7JkNe+o^!0Oh
zpm@P%cY|9_ANUyH@@Mg@-Q+%^0{21gcQ@eE5O?PukXzhW9szipTS2SYJKSDc@D6kD
zQ|MuY`!c<%M!8&ih}`2|FM-GycgP=JjB{75gX;TSM@n{0a1XN4_ker)JpiV-9dBZs
zwrOtQB8WcZCjA1@8Scb)5Pih`=MFk&xfw$IA`ZNET3kBvzM@KRCtehlWjXT}&|=Gl
z7ezm;D{l`if!ugCbOO$uw@VA+!Q1-*`aF55AH%|7-cM9)afFwC2CBVyKD326YU4>a
zU=+T*YI=kC@%sM(!k-uX0y+bDR~NwHW4w6!U+sasu~v8(%u^PF3*l9)2OyMZ*N$O_
z@l-FOF`Sny1ula3JB7)P^V%r|6~&WKsyv!^gx(w{c+qdbwUfO2|H6wHo-LM&!ee>k
zNf=BV?=M=V#q;h`;y!^FOOLHYo-bvMPVtVt3y~xqmkBk=yvOO2jw!ruI!$qgcbN9>
zsl4^Sqc4rOi$VbDyss|6L?*AH3nYsd*#LjDc`=m3$>A;D3b)Vlx@|9^^&Bs81%Uay
z{r|#X0Z*C)L?JJmND)s!TjFA#J{jgqc*m(Ozm&(Lil#DN8D%=kc?l&jU%~q+7j`Ro
zp0q8h;`N6@bu~{lAAPmFZS+#B<3)T7E%m%<XK)R?-3q$@8hPWdp|y!uNsIqx-UchY
zxWKzj`TG{$9~9qi<*lGSX&Z0t6A-z`o1v9Z2d_>D^PRl9uP~-dyie%lz-69;3ugTa
zFERqobn#5TqpyeeXBs50^8R@ejn{bow1Dg7eYu?Se|@|S4UoCPJHHvN1H7sT7`(~5
z+6mD?o{d(zLp%!wGH&s7UqR$HZ!^Wkhk2h}1UJHq=78MgrQd~#QQp<RpzI#6atXAI
z@ti4zG|qd6l8F<%PwAEOfXC>8vPoVS&NSKVrg+hm+n?q|Q}pT~FR25=p5e(U<nf3%
zm$G`Zyj&{(cHr03WqFX#{R*RZ;>S~Uh%^6^9f%A6V>&A2%74Nc05^Uy6&<?sf5}GQ
zA^!D)0C@6+R)`$t&!$7!5xyfW#B5&taM~(*^XIri#+NV12It2gGJ*5w`_2am;CH?P
zpN{eGe2c*Z@{6CvV1oGb9>XMr@V(#0utWJjO#m0hUqxRW4CfmuVIRSN^CEtc<9xq`
zup7w_kAZ8^{Bn99oZv5C0CLjCe~iNOG5jQ|)r{p!*ucl}zo-O0o*znU@dW<r0f;8@
z@6m$y6#vdr^quDa#{i|t{Pk2!p2ELOpSU=~fB9QTrt)8)^+_849Mzkr^Xn+qpTTcF
z3}spT?Z0A5viUC!f#mRQ0Xu;>%YWP-qPhH6Q~>7lmr!)1fd3@bsuc1+rJYO>UqMl`
zVtyoL#Y_0FI6>)oe!m!FD&<SA!;3QhK6)uu@C}P0Qppef4n9@!L#ST0n*XF6A~pPY
z9aPux-xUH^&%bB;2AvK3AL;gQ;?KSU(#-ENVJ<H4zo+<V3;(tAaIKXe$^dEOXG}qN
zJO5AGQg`s1{XjbTPY*)(C4Suk050>H51{1=|1H`(bn)+gg}!e78QPUy<tyhy^)>!K
z5fJI+pVCqOy^r5c;pXf7^^`#G=Vy!H;!XbUF}Od-Px}^Ri2p%9fVcRs(fR1x{KLzk
z?GC?mGbD%ktoaZb;YZR^@h<<vZ$R$x*M0_NWBk4K@Nk@eghE;O`Ku{8H^Dz$4=t1Y
z70*A7`)`W>0o8>}^B2#cb%sBf1^gp^Q5Lva{w#gc%0aN^U;Ho!1!HAU<0v>c4bDlh
zObFdBf=#WEbQO$Kh}BKdKxcd11;I7&>5$-Z9h7+p-jBvOJp~)u;Pw%LoduF!0(BC7
z|HWJI7QOv_1X6lv9~B&-?2WJBulJxPK#+R~+%duOKQPch!H4_71qt#ug9HmcprC4q
zz?KUxRPgl|;KBqySHYQZ!E8L>#|5G|co8XhNPGV%K?*HQq6KT{xqL#frv<;HEk@8v
zVdGfA`v>4foWPOJ@g)eJrU!DOVCrq)PYEKu;rD65bva0qU{(pqWI=}-_!Pl=_==5P
zs$lyOXh{?NL-$X*K*E7YhJZtNYNo)4&KqY5=F?^)TW~iE*Tq>u#4CX3+5|u30iP#0
zOlO1739{+6pD)M|qp?7cKxx2Y!G9?%Um^&-1^jtICDn$O3Owm{Dids|11T3Uo`t^^
zf}OOKuM`|gfJl|Vk1qLYLBhWvHG(~JF_v1vn#&+{0#B;4s2AAYq*E&mf|ZmnZ4@+6
zI-yD6+Y2w61)J7^ToCNo2}FzFw-S(6!9U$FaZ%t!`^FAICvEII1^hoDc}b8!HMo}r
zo-r_gMIfR2h%Ui~IpDelLG-HX5p1KN*;T<J9>_Jpr#4Do_6k(?u-hltd>Xp13nD0(
z+b>vKgE8F@2wAW+AXvW(Q*u+lD+X{-ke>->h6J780)9(yg>HvoK|Kpzj0lcJfx9c1
zPhZa%6>Pr+yY~c(y+OtVFVSx|E=c<jI`0d1?59QIgusJVoDT%g)5SI^2t;1mZb~rK
z057Hm3#b6)p<oRyLuUl0&j5HNsBi)|E6D#HY8-^2GAKPL{Df-E9EIc0!8Ir0*IUr%
zD(t7#j+@XXMx(pXp2}bj37-vvY7gOaR?7c*3e#x4epu*729F3gc7u2c|M>tWyoGn@
z>huwAd<JTKg>LjgXFuWh6jJsVE_fUyKp62IEFBXbx&bc&g?>~RA0(VlvBqFwHLZ3+
zgnbnI4iz5HKwp^f@CP6f!pe|2xc`m|<+M?b6vopEE=rh4`><$XIMu(L5Juca<4K_<
z5i=7b{E&(mVuf2fpfpZcI)%P?;p~2pMB(CZ;l(MTjMh`9g>l^&Qj#!i8&oF?k1Yd9
z5pJST<r(1%I!LAp_fx9PmL~jV8m;NVoh#9rAym-il`U+dXK0S_$ZE)(74F*tXL5ya
zQlutN*hUp3=Y-GBMPt73<$vK!flx(RszTvK3icHV_t1N!Sor91jODyg>;bn+g-bs}
zW0~+1O5BwTH~XQl!X`XV|IV*c=*k7KO1SO-23jq=Dg~lO*p~pMwZidQ^wkO1`U2k|
zjCu;Q-Y8si2#rm`74Ly-7OtlgWfz3yVz|~KT)zh<T7}Xg0NR9GDErwi{FxH|7lo^T
zfJleXo%S=AgtmFjpqGUSw5PoyyiTPMUBYWr;MXlIqJr-pVT1v|tHNj_B(DiSp)GZ<
zu$M}<`h)^{MP3)qqtNVtu&Ekjx+$EY75$)a@+F823B4%seoMG{4ajZb-AC~Ej<ANx
zU5AC|Y$-sD2wzg5^{y~M0^Os+>jMxS6P{fKnQ`HZEpYh0@OLvzObC}%LiYpV+g@;H
zQYg`YObPk^aCBOzd=<(b3KPm8G9&E2guX|@pS}li5dB3JR0l=8KOpHS`r-}fbP^r=
z-iBY)SrkAqLl@DR;~=i0?LDyMCi<8PcHBiJG*O2{+t|?UAzGaSk;9@4+AbdvC0&Lk
zFVUCzX!I71R07~5a-r+-sAwJC>As@*^hoj(@%MxHi%j$~4iIgi?AS5Uw;#~@Gg!1W
z7;K2B>?MphRJ4`y!(k$kKS;P}Gi9P8MET3$_i>T<FziN(eyxUyDA6%`-b9PaDIs-2
z)G!w&Vnj=6lN2lZ>~l!Qi7F|F8ZR29kbQ#4MtO@wQ9i}aPKgTV(fNndqE~4TkR<wW
z7l6s4ro{lJh+65*l`1mPo+nL|I2V@EMN)dXWr%W4fXfuMQ6Wi|sJ#jz*`mmo;b@Mi
zbUlWBR&=!xI&(#iUqd8Mq^9pp<%@1pHljeZ<2(!%indUS-c}^?q}6b-=r2Ez64CNs
z@Qa)m{e2ZCN<|gHAZ4P>{{mPpT6qUPRfzmd&|NL!(CWKJWS9V;R`eNd?CV6A>GrP|
z@i{QqAYvbaGmWBO-5}B=O3s0nX3<Swz%PjYHUrRN6a9AtqHQ7t6}+{Jp4X%EqA0Ww
zx;sRU^jhf@sjorglIUbO$YoK~H<;2ZqItB7?Gjl@Tes-tk1)_45jz_q*F-;cgY=57
zOu*kh(SI7ycU_cC9}n*rZK74f4UzR88V5u+Q35R86!G^#bWrq}8@M6S=XQ{}CAvnt
zqdTIlbY^u}bW96NBcixijN-1StsSn7ivBnZa!>Tu4*-mb?zF(Canbo{NZuDEZv=co
zBnklFf#`1u%ukCxrmf3EQ8E1@GoqWecOmmgbdX|iv!d5dgE)x0cf#O7u?M;6C|-UV
z#7X?D2k_3~3yHwHh~L|WDRmP^QdZAh{4wo94~aeBf-@fCYeyjIDGrgsnZx1@k05eH
zEc+Wey~I~O#W=mi3Hj*r5r5K5BRndOrYEwWIN}0i{KeT@VIn|$s0zSi;?52<28!*r
z!QmkBe;0xa7EjR9I7ECS1-MYL<w^YLVd5q9wS#c+u9KLH<Ki$XcZd{MX~9K_SLwk;
zi%({QJ0YHT2Nq6>-!7o|XN=gJ(oC`9UU~+`iN9;c(Bj44Qwd{&crCrMPK$deE}kUb
zN89{laXn=PQp8Iiz>72D30i8Vit}mHo+e&PkDYY!A_}2ph!>p(mnp8K1$ve^w+nzA
z@rhpmKPz6<LiN|V;wpM5<cW>zfIlbRMsL%6@$!DyEfDWrhrU8_9|akU#DWjuTCw<R
ziU*d618C1vD!xG(gEDbHmFJg>qu&Cl5U<XFrAqN2z4oibQ>}nkivvyrUL)SI7o=7k
zxd)QAI<a{L##Aq6UWWNb@qeC%!%gD#26Q%yzn?<m1+gEU=V=l5Qb}K{IL02NO+5V#
z)U=C>L!kSjxG)7=hxqX!IMXS9lfDpqMV$H)%y)_ZqSa`(xalXTz9wG12YtO_yALr5
zeKzs$G?%x;?U68eTfCiiS9ip`de|KnD=3maB3`@&<gU1%o)DvALk>*b6W^f9yfN{*
z%`h=8E_cTu?u!Ehz)grfRzl=~czih;C&jOBf#j6<XBWVy#k0O>d?@~ksw!v1w)=7*
z9*M8g{WmLK_%>P{B<6pBI4F5?4@4a$eVrJZlVrCe8l5F;s9x1YQo0#qa+O%67>t`_
ztqlg<C7D!ddPuV5GY}8S`x@XpC6`uV*oP$>sLcI{<X{xEcuD%H=)qfZ%0>@3A4wys
zXzh+l0`t)7EBQVHoS)>Wjp*~2g#HYCfTZeu^c|DDw;7WkC|P|DYJwz!O=t|3d{1xa
z5Q#JW%%PH37XTL~SxNc7aLGA(hDAtL^<nhKB?<IqkCfbb8s0}q8ZJ@(FIrMXE9DcC
zy(}m_DH#y~5hM9E5BONgNBf{OPBQQm1`{t?_&TN}K@$8CNTTFN3aFowXeiisTCy(|
zB1w{S_n|vkQhN|?r$}1py?I8GMwdXUq@N0P(j>naAek;H{F~}OGbE;XIF%`Jqr^j&
zgiG<NY)LIGUUDR9RCaJy@@6$$%auGyCyw$YPdKBoKr%pe!G)6CaNvq00kqgEmUvJN
zLy4q;&P1J;^ln05spP;}z{@0mx1g_FGQfmnh2$<0_Q?N95+A`*l|)H(bJdb;s`{&u
zXlW5%E7`^bzD_ciD$MI8U(*L98YC-@fiz0yJP-3t5_K%#&62GaG+vN6pMvfdiHZ_5
zt&+vN;YFKd`D=i;OJ2W?#*315C1~uBID8I(ty7Xa05z8+jg)M@Ea{w&&MT6LO;Fk;
z@yG+BTjFjHFM1>{lTdS2;&Bruu1RitgX@*FP(ZFv5>yPpb;)ORdGt%7Hlpu_WI7Gp
zfMm~hXt^o*jg7`Z$qV$p9+LD^J=HCn<R>b8xh>iLCDh!Jd`NfWuw+sJZbVX51DU&$
z7pDOnmE_n#+davb{{>)7QquvEamj&x*u5_~>;n%cB=YM3Jdk`tv5HB_2^!&)q@@de
z(~>pIFtUe|gT)Y;k^FQDUObZ6KB3ySSqXm`lsZW7W&m+eI({57j?%*`A>$-HB0!(B
z)blMUb&+18*nz85yAL96((fYRn!8l`2Dn4g6sn5$kZ#xr&QrQ%J;-5cJk?Gdk=_i3
zqdwB0`>=3STDTOAzS3G-CdTV0eVJ-a{H69Qfe4U3OM#nX(xe3V9Vnek1uQ{Q-~Shx
zNDCf-3z2qG@k6L|EiLlGq+RqOqHw8^?)wPo*m>wYF7=6o+mX^CTFymD?|g#MM@t88
zq3?vWn!@rYrSE0Y{x3$V<w7P_`ogauang5}<I;<lHd5_Hg7g(vh$c!mzY6zHNsn$s
z-)X7CE0}~NsY5tKlBIKN!KFyw-vsy>>E5S6Ql;NL57lW>F0BgFrRG1uWk|;;Jdi1^
zqpeStRMAZLU$*oyN*Cown<$EVR@#*cnOx~|`hY~9bRkt#oRg+gus&a!w;mz|(yyO@
z7lqQV=&4sC-IN2sdFg>?0VtK`>M%29(v|dtD3?CF3#u!mh1rm-lvY#WN|p3N6O>g;
z7viO6v#XJs>3dbR(&H3{sgrI_fM~t+-7A>V2I+zAXl#_SpM$n0Y1Lc6w@5$#6r@#J
zLOG;1Y5C`{+b(@;JuF?6)=+f5L&{OWr%q`n?O85K_x3@{W$85Kysk+1Qw>s=bRMk{
zZQas2__OPgI{prstJ0t_aMz?k^FVr~vlL<KlSWez>bmq>y2$&bJ7|M_L%M4ZxB;o|
zV>okD`qVJo9+c*;fZZYKicyeT(raG=ep`BSAsoFUz55mH4og?Gfg6!7{uDaz+N2B1
z!H!CGbYa|+Hc&8WO!`&<@Z-|`^tH<S(ibQcHX;3%0xu7ww<)PVDP8y}M5d%KKESU%
zE&YK)jt`~cXegbLzFdKUK9X+#2_m!77sBA0gX{-Ks6HrrbRUwAGA|AW;Uu%AQ!$>i
z%$r_^F0u!E0d$ome}GOm*-MnRahG-e0fUERZIpKLkh%N?FFa-S^e8+mo1s<15t+|1
z49!dSEPbNMTUJ^JoR4e)l`|ieWfr5)R~DQJNk7@p=TPP^`{fn579dNveSpqmGW$@p
z2FeQPbE`qJGqlPImictRQi$xoE)Wfs*}Vz#VKQF_kZ>7)0wNKzqa#pyTxO=Cwn$lf
z8%UIFl$H|FvcIM9@PzEtpMb~8g!C|olWnVjp?KNjlwnMeEhwgxP@=3|h1OFt?HnjQ
zEz78fi6q&xD!7&`TigSY6xrSmG@g;w{01&nR>^|WG+EJls7aUoKpT<_*{yJB$&{7#
zfy<H|rDt!p%$K%tIkMxl-#sg{&;~45mb@1vPj+lS)xVsRX{o$FU$%qxj|H+Ks#GnM
zb*~3kBr6L9S1daljDeQOyiS3fmtAmy?o!#iaWG#d8x4YM<+9}m;eCaSu?>BdG7*K8
zs$`>7vtKP6{shWuWU+(bYGuwB!PUtaQ?&l9m(|fcH^>4ipsi8nQvef9vNvc&(kv@T
z!(cAR_8x(UEwb<Uu+%Cu(PH|dEVKzGI%GL%Af2)zO3`1E&E18*%d);nSh^zHejd(r
z$&zXy(k*+1A}u|#NChOX%EBoSXuBrkWx_<S?C~D~?2|F+y1Fh)iGxr5vah*lydlfi
zf(*!VD57>#c54%q4$7813vNgj+yrg6WQ!>vep|LM8I5;j*AoFBmYuwTz7bhAt)TA8
zdKvJ3RF*|ciF>j)XkjsCllf7|WL!3M0VeLtOv_+?LdKwDfDdGH`k>IH%s&o@DcLm^
z`le+rzrxZ(*&K=s%*dKMfO{n4AAq)5S#TSOgFIY_zJv02De2@We}W!6PI8|cFyt&>
zv<=E!<lircq^sN}rc9-qJmn1_+~t>)uzN`UgePP?<hNE}hCJn$6!817yo3jBN912F
zh8i!q)3?BR%jKhJ^pSr})!awrhd+a)uiTrC_WQ{#bV2ybb+kVSkjGN=>6rW|ona1?
z>nW`jBp<X<^eR}cq@_%Vd^xTBLgj9Y;aiwI_zu*B%QJ>yFhbrzbzsNk`qu%Bl#k}X
z!zlS16X2rdwUmKAA?HPbJ1PJBUjSm{u3KR~R=$Oj199@@sUV5+Jc^{9lD|RGnA7sn
zaf-hr$pa|}l`OwXWiTo7Js*Rdk*`_-rK$2)DR-47|Me@7borW605jz8Q%O;#ypBFM
zkR^XD5Uyp*S5UAaM?Sb4UYwQt`~%gw@>*|b$&+u~0dh`05(ap_{8SYz6v!tNDF0q4
z7t&`EisZvnFi|WoqqAHk@@ZPUoR>SUfr(Q2N54U7nfwWwl5%--1uRv_-RR*}Dc`Au
zNR`~1N+GJ{UO&K@8u{ASF{E1g_cBaEo!qSx7V71n(F&?T?hy%R8s$4A6n|-wn>L}d
zS*}_NazV~Zhou&|zaFBk@~e~;Xp?j4W!x_JpsVDfeD^&_cF3D)5pY>vuSMe(`54uM
zbjb^-@TFU>OoVGa^5%EZcvZf7KFBq>;SrqamDgT_hkf#0&d_4JE>E&RO}~62Ew*mR
zFT4uifc$tUe&3t&qut;J<%e%TWJrGXHpngca{&O}md~SQ=pFgia_AnGKa>M7B9Ah_
z-@EeC#UP{dE%a)>Cznu~c1(W!cW~o!M-I&2m$y)8cETo~p^(V~`Ct-SC*_@SAXD<^
zccXDy{>D5Y9?GM;F(otdO*KF~k{8n`X63QbFzBGjng%(jSW3%5N5vQ|U!4?3-+|lC
zikB$z=%VnYV7seg>I%GYQ+V%zPItuts(3!6u;oz^yN6;PebU%d@hbf?UW%`%y3$*5
zWG}q%QS_z*e^kL5M5C|5YayKRQ`DV7qrZar5K|JMNcazM#}p<i;0jbY2SRs{B9<=F
zV8u7xun?l?rg4TU?j8gerdUF2t#Cz#?H?c_74s=r5vAC|fr)5^4<#o~D3mKOrjv?_
z+YpIS95@H1u?pWPxF4rzJ`EDD2ug;w1jU>5_D)nh9D+}$6fDZ*o>mOHfFvnCh(ceo
z!tWJ~K1J~cCH&4PB8^a;s%TkhgBxiI@d^Ob73UGsw#!g#q-!oyk?Ra+vJ|a(7+SU>
z|5Y^RD0(SXepc}X)%)Zsto^{{DVTH+?wq2Umh}0Gzs)dFpx844K%v5x3{s?s+z*jr
zg&SQ~C5qLtz@1kd7t;M#syIqd@-l_%3$RqKn5NKFg(BV#T&3dd%OF*X=jhl-wPL>-
z=4%v6+E3Lg66sVzonl}Jef5d~+CnraRzHs+H7R`RV4_*UdJ5!%;u!<_S`<CI;7qHc
z-3=mbiWiZ4wb`{RHc)EjqT+KJXouo7g=#t#TWEqWDRTb>;<6%~0-skDpRb0aU5X8q
zhVNF`zl<NPM^W)#z<U)%l+o=|gq?%rb;YXp(b%u}D+=%%iaW{BIiM)L1i(#2(`_^k
zDui@d+J+Pfq44dN;u#i(eOvJh6&T%7I7+|`D_%VcnGwaGR3m*?@yry|j4Dd$LcFJ#
zzY1!`6lN<L#}(rr19x9hN5Q%YMHiJaJW!aPg)@_ir>SIQN@1hm#<XJpRw#R@SaTd?
z#-<2vfTc%@?MZNdR^b#0r4GvIS1|g6%6+s0a#X%k1<pz7zYrqM%1K%txhP{+L8+^9
zrUiX&$^?q$xGRU~Fw`OC9!g|+C^zyT>8bqlOISFpe2RidN0bp)A>yU{tpIRurS1F#
zWPFr6Db{~f8BPH%UnMIIBlJ_wNd)m%s>(qEl=Epva7_8<1&lXP`4PQ<f|MWo!F;gN
z^c=VlWf^U6LY3R4AYsZ1dRK%iH_<t-2ql9`5RWUrYJp^=@<$4tM=7Ul6xWMZzHuL-
zCzSkW;LJ(os{1e)qntbeM67aQ479~5U!aXaymELu013)1^ioY!KKcTHQ%ddvh@4jb
z5d)=3%FFb$O;)Ze0+*tcB!Qe!8mb_Ys@zWBkxo;_Qw%FzS@bX6ju}cJ-SC;polC%F
zDXS@#oUQz+6eLH<A41<*Wf|=+a+RycpgT_~rDVuC<>0R{pRY7+fMkL4EImRCm5o$$
zRiuo@7RIhv`L8<$QKI~auGKPSS_qseSAO^<8Y`6l`cwYBQmL{4QKhs*qqACBbq$?0
z%9>zkt5qgkL0_G6HXeQT$_I3CqCvUV2R~DzGK2PUP0HuPV5wR8em}?s<@4l4i;_1E
z(yCll4nUi7#}n|kUFmZkfQw4oGnj-9W#M|tzjrGCdK#UVl-_FKFDrM_cKwR7b|Zd+
zF6ACtK6fh}+X3uR{!QtgtIEcOP<l<NUk}o&tmi?p50@7_yslha1bDyFjY@cLD19aH
zVnBKBDfHb`T91PaDo<08Vo14wLTI*I%2ofr@szi{pyrM;at;u~%F~zN%!qRBd(d`Q
z$tnXGRmS}d#62a8Ui4#1|7W0WTq*k#+<j%u518NyWe{!79w@WvB-y0$_8fRIr3`rr
zI;WM{6f=LQ+<X$;jB+(CB_7$7KfeQ|v&uzg03B4XQV!^#>H=MCj;i(J@X1LvnvX_j
zRgW7u7uCQ{09{q<X-n*;^4Jd(?kY3A_7ABR(092!RHKwK^HhCL>yyK(Q_BE9qAJ-B
z^Ij_J4TyNF;=V_tkIJ@VFYF#wy+#RTUzO+EAbzSEDn9a8mA{X^V=5lq9D%9}Z^7>%
zRUzG6!73gXx<gcPMIfOni3p8hs&x_29j+RtbGs3$r@3f6t|}gcrAXD2h2Wx8bqtVb
zRRV<?PpHn@sJiQ<>In->#Hb#l)pxAwhboLPPUTGN*Lc<N1~`+Ts`wU-iK^uv!KYIy
z2JK5utJYUSBuN!;1zfVK?RjWPQSEsLTF$6mh=gmYs*UvYNmC8X0G_UTOb5Fesw~>w
zWU7XD+rVb2*3#xKTeX;;@;Rz^C_Q#ol}=IiT-Em7P?M)x;|s}isyk#NU$vX|VFjx9
z-h%Ezl@~3Wi&Swm&|+00)m4?KWH&+1t3uucpj6fU8aymh&CP<p<*H{XI$xp6c!%D9
zl`2jMWU5thRN!8tT6+X)YE{c9lU1kky#hqNDwOs-4XWaEFxaT-z6;lyRNh74npK~^
z3+{qynG7acRDaMmp;eVrfg!c2GU?K5SM9KXTvSE9fW8jZI;!97R25*?Y_q$hO7TSN
zWtCkNEL~9*Yz44O_0lQ~yIVD<0<QI_l=RfQs)~38!@j1{-2lE<wdMtoK9!Afzt>fb
z9w7ayi?;!|p?by+gBVb0#-Qw`%0l&2gQ{AJs|~46)A@&6s?Grr+ig{i67-I$`9q9w
zSoMnzCPq|m9>vh^s?<EF8C6}TYyF<;>00<Srn>eE0OP8GIsopgPG-XHgo-&I&OA^x
ziP1NyYU)Pglq!K1@6)RP(&FKv>W@9}Vn)TI71$%y(q@Rv+Eii+ZaS!Yx$yL$+K<kH
zIIGwHztmdY9S(!8YQatrH?@|sRPO4rH6Vx7`)M2Lp%$0HUr#l&66CO&5em1DsLfx2
z^HTd#(9B!?9QN6EKI#hE0~}RH1VhAE{rEok>!-Hm(X!58{l#nWG(f$bUT4SDq9Diw
zs$ZePwIFpJZJmPEi9HYrQUAUi=0nvxDXAEye(nUk2v^7bj=l)>d0GM;SI^LK)=0H$
zGf0&BCaqMX)lz>bJE0z?JN2Zxn1Zn}>JM!c{)tsTO^>@cb?92)<JCUD!?y&r+ys)S
z=29WZDYY>ImXg&!i=ZY&EfN55M*Zd|XiQa~Bc*BTQhKeVt9h@&-wd_KR*+2f1A4M#
zsc)PE$yRgeBFj<B;^5O+HFFK!f4S=G`!F?m>UuHAIrUtc*?jdM<*-zsHqQgFQ2ksW
zbQh@;sieJF9YwcciTc!c=sT}Y%mJ=c{cr=gGWEX&nDuh?TPtCrLS3msW2HLF1zeR{
z@)zLMYFQ5eHR?B3Q2xDE?e{fg>eME>TI$tfpF*ZVy*>bH8r63XqOVE4I|&Ax)piMR
z|AKm978+aBp7acCRR_P1U#m^+^9lOe)jkxBxv2h-UQQkAXL~R+o$6ppl3h~YqN2mg
z>J<+maz%YVpYjh~YE3w_b*lqCf#^{`qBQSSb$1(NuBpR6M`N$L`7N05Q%lV-aa}!~
zj=lkPMLi^Ms;j@lbPcM1$cL68wL1m-ZmH+|19DrP^*!Ks)aQKQ;jsGPuOK7pZUe|&
z^|22?Y@_M}?NEA8J@pZM8&fZ-0&raY>0|hP@2gWO&^w`igX&Nos9Stsa8lh*q39_!
za}MlItMLQj=2H6~gO(X}*<AEJQXh{&->iCt9&_lRX{X%NLCrVIFu#tP-SitcX*N6$
z^UgNS<CHLQ(G1Wo$yM_b9RqaJtnGywcg;Oos2>6lcn{6SH_+&*S&<0tu!c?Xu_GF{
zL2zE0pJ@^8t#PDvRgh-!DcB9xY+MWyqPatrGNBqPZ6?DsZF}KbxTfbh*o)BE-d6&D
zTyvM6dXbt%2f#&X$|<88t@$Pj=1*vto57vbe18Xs7|lak-NkC2+JnA0&5ksTB3`rg
z3D`~0%u<z9qUNJ+ICDy~l-}2;HA9YQOwt^n=xwql<uypAXtr$uIipFp9f7t~&9{5O
zrfIxsE1s_TmsS=Tnt4?9kf}+f^0zF_v$QeD*8JrGlB02;vrT6;p%M%xSF<AwCh{~Z
zmx7$r{7H9XzGf|zV-{%qC}vlv={bSMBF!W{!HYGY&?)UwO{k0__+^@{DQGR%c+=9l
zLUZQ;lvZjIb^~9f3HL=`wdVK_P*bCE{~dj`nzw!fSFe$aAkv_b%>mb_`JK+@Hfdh0
z1!>m&O$RJ5Xcp66xJ9#zN~c;ijZ`7fra46AT<x0Ea{B*c7d4MjtyhQUI&B3yHQ|)h
zzoc<%$FMJJ4*ZF}Zq4)|^z~@m=`7?m&CWXDdo}XiaHdbwHvy6B8UrQl`!%jR;O`BM
zYaz4@Xy(&V=$jhTA5b=^*>w+nLmG!-ICD$WiUHc}Zfkx>g3KMwx|cBeVNK>OC>_!K
zNDq^{nuDVl;ix8_uHbu`2d{%0(+m_q+qfpN59GdPg7T~rn%Ku-@PUR;x6!0#h@wwZ
zntyHsFs*se3Y`x%2Ph6Qqp{;a^&`!EO6}WbHK`Q4JE+Z~Jb<HCn+8!Q?Q;~7cGX(W
zpwCUaxduaX*E)s5i$mIir$IclLJF39YD@SaURtlq0C;ON-$I{{mh%^s`Dve~S^|IV
z{8oqrXdhBQ`<OO^e!@U)`Vb_8Y})RR(HgAX@-|F_Xiw1P6{_7$^(0~14HFOz*Ro#*
zK0-T}K3#NNYo@?hq&CAJT$DDC?wDw8{5+UHp`E0i=1J{|agZ1-?*>K~tG!Jz**NX(
z8W@V#zHNrG1g-oK`VzIazbWN?O8fEuQ^?u}uF#gG?V?JXWbJ0E_D#|L^(LG-qkW#P
z^;GQ_KcX>BYonxXy0*><T!!}UPH>r8&VA_4(tdUhI<vKhuffqA?K6~*KC7+z79Qqm
zUyA_A({7{4?m6vT+fpbk)E=V9W0BTCtIA@nU^&c}Xg^&Ka$XxOgzi$UEgf8$*4hB2
z<=W@Y!qEzC)G$b;_F@A>s<aC#VX0c1L~D>5?WdbTYPF9~fYfQT1%TIU&lbXNgZ6ET
zYd31$xfFkC(k}cOUNmcS_Cfar?Y|eGv_<>M0nAsc)^rlUHtm)Z;5xMJbgOh~gQ?`}
zl6H#LK9{xUsBY$p_7i&Cb!ms`x!$e4cNHdjw5#dh!d0#KNpOAIdMbpxu3dH%X8W~E
zLh1e+)~5Xjx<|Clb|81P;ZFcRrmYi0W?bt|5BvLCCVggkLi?W~SbCt%pg8lScHJs)
z54FEi(fy2e5v_I}Y0uHn4(iGSFl<NN6YoHalkRhh%Q@@X=Ah3-7rzb4Ty@*7(fZRz
z_bTndkLnsJ(c-I9zXS7ry7pT5?XOc@f~5dmx;Ofc>EslI3e<hQ3TlFMj`v|ASZDV-
zBtvwW6l@RG4biqYOt*w0F5$Y5$I%#}GtpE=>I&&vi_-nnfZrfm=SRT}+X>wWWhzhV
ze4c=b7+okmZ{l_81OO9s*GkcssB8NYqNjB1NjQ31x0GT^NxHB#u#~LxpbE$o-O&Mv
zoY94z10Yp*_Y1(&bnd6om#&+73tWcoNi9S&b)QqHF-zA)L6vNqZrL=P%F(fyu$!mb
zNOjN!y0&(3g}StFK#Fu7FQTzn=khnW5?#tDl%Cgp?tn=s)rBF5Wml%-QAtC&?%ikL
zQ-$sx#hEL0y93~8m2O!vB&&6I9Du9QedG_jwYtnr0MzMh`)H|IuVa1*(x7Xl>bpkW
zeS2_Cy2%dUn{{=60^h1jNCml~6aNZ-yL2tD!BV$wmI@7ebQdXidsSCSrBl~*+{e(^
zr^`49a$P653(0=n67ukdE{qG+1G>QXKyK>(w$UlKLEXq4kRjc{7$9!zPEwNKj&9B|
zI6SNiqs7aJZk*=wu5K|MEgsbwC=Y&5_i_uAj_DE(!?khUUvysTzOJ$YeG|Gl2Qdkg
zx_flTP3bK3l9<*dc%kp1u9nVH&FF3kY#8Aq-MjA4J*(U62I8P!Nh`R6`pPo&IqH{x
z4!o0INiS+=eTgF)UG(=Khls0QbsI|E^r}M`w!3~iU1f*#ac3aup}$1w3om_;9A5b7
ziyw!FNA){bV}QQ;6He&!(;q!T`#*oZmSWKX`nMY(8l-o;4bfozu>?31qQ7W_?od6O
zPPv8Y*EIteu2260BtoA-fzRXmb%VGpBlY2OXo=Q0QrPx{{_+#(JE?y%5z1opz1sng
z)%z-7K2AS63%BF-XRzwF*(K;}^C6n3FQnSTQ~L7vfH<wMn+r8b`h8!5r09PQMdKO$
zus^s|{n#$3Nz==Npfp{-kM>HLdKTSyS^BzRc#*A7sfDr}eMvP$&gyrk0+*|go&cAp
ze~gmb`FajznQR668&@%Hh58d;fi2QIeFEQ#^<FZJzC`cjg1+<m`QO4srM`}jxv0`l
zx}vXIzmrm;HTr8*5nrqSc@g^R^{*EJ(4e20KwqPt*@M0ddKG=Nu0=o84hyaNpXuCE
zoBnOufVJE7lFI;g=s#?P-A?^GbYA(Aejg8Ny7Z}^ps!n>_dN#Fqkr}pAg=1uDUx?h
zf1(tCUVZz=0QBh(ctEmWzbg@vH}o%3{(L~6c?*3v^(QIfGN>1~V`hf*>pMYi=^vvD
z;<nzlYZolt(VwC;)m{B7olrWe*U<L$p8n+@p=M0~)=$tqu0MYRefRa<v;%sef8k}!
z<)r=+<rb&(FK{3-t)KY}jSuxZe!&FI>JzR)(!sEe3v$q4ehrO|hPhwDdndzn3R*iG
z{<a0fysM%8L&&%p#<M}(4bMzN^pK&0;u#)>f6hVlh@o!;l3s=*RO;z%czPW?^f3%q
zK;)?5k4+%Hh9B(Uub*KfrPKTkD{nv~(BMzOoFGFvg;9bHO4<*F7#2`;BGl0EGTndS
z2FEZUA`DN`vhKKHX)H*TA)Z1*(T2pEn3)rX)j^oAlZL`yU_Qn$F#<KQhTk~oi#M?7
zP*Q^7?L{z{Xt<(B<0-@5QxG|Actr+WlHndb-BS#kR>R&ILp`PcQw<ys`u<XyA(#sM
z(hXZ^zOoDwcZg;iE^LFE97E=NnBcPp2NKCOT%hf1o*|Fyo-?eChKKovg*hMvhIlF^
zDl{l4fLLUxpkt54hJUl+Q;8vvN(0UtoKm2=)bL#+43!yPR?+#ta>JFcp|rxFrbug*
zVSP97)rQ~c7p*b$@Zf2!p^G-rb%x7y(y88%o{hc+gCPvM8x0>*aafaK$CEJMZ1|)U
zu3a!(q?|^JVcCz+*=l%~mgH@QIg~hPH(37xchOM!1DvsS7_QSstkV#xhMG%;1)szG
zWy9=GAXf~lsIs=(uxSpat;g_PCCF8S_ebcvX4p#^mR^J9C0Ob+e9;B-*A4rALtnqa
zfx-$m3=vciHDFk=2;`=ra}&s*;W*_ch75*N0Nk<}rXFBuw+*3PXuV_j^i7aqgO=h7
zBZjTNLd~e*2py5QXBeiJ%$VUtI&(8&&{MMNf#K9eOv$7nw*X|yu$5ji(}rw%JU=v4
zZN$iC4A~Uod}J7-X!WeYk)9<E#utA;-$A48#Z55pXk2_2emfZ_$O~tq>oJJB7&}*@
z(bbqm<q~ejpQ@qM-N=bT-y!4B`*6*}czp_!;Axyo%iqIB=P$q=G3K=b=Vd&5AF92L
z4zzRfF&?6g=27FA8Fqb*DHOK#Gy2*#0_bn_NrB%1M)f4PW5#$oN*!nnq2E5p7)&P~
zf{lZe7Y;E-(IPz5XlMi=%;@(yCNbPNe=&4N7%v=x$Z_LePr+cMal^A9CyY+?hCXS0
zRshv8#<I8JeXP-g;ze=Bmp-sTO}sIc9!&{GGhG6S#zI;XpE5pA5z{1NB|XxTjeq5V
zq!>pi+MRB^O_B5rBZs~^kZIgUd-p7(J(VtI8%vcim}5+=N8edv3T^sxjg_HLmS_B=
z0QSxqU!cn)-{|%K@4plnJLy<Yq4BeS&{<?GNJVF{aZe?bmKbGfOw@VfAy?QfHExlC
zlo@q5V4~bOOe?7h<By8~uQX0yfrnMb_2D4Z#vODJyvAswE3noms|HtRENKOx-WZh%
z*BXo~@HVvBH5zw)gK29rN}h*Iv$2utP%an?X!cr+=O~NWYD~mZ)vnFR@CIo&zCn?I
zi^j(&kI-R^;XqrbaS?qW^^);RXE<}&sQVtnzG6H=mvfi#$Q+1t8$*&|p~v`0jlQc!
zJ=K=kt{H#d0-0XpnaAK;pYcr!pj<b8Lb?5ZBcc+xkBl?lL3F@)AP?M4qc|3mFlf9^
z@unf;Rt6+*85eAXmfOZ9Ss3pf<8y4dJ#4%}=MG1VKQ2JyUE{rL;6{x?C(P(Q<1_UB
z8nYQSkKpjQvFsg?`^J}O=Qd$nB7nguW9S8N(?+g4bU!pY(MM%wjD^|I_Q?2%0TZ*v
z>JOpR!E`YmjR#E*eNgIXns^r;I+@&7!Zl~p7(K3BOgkP2=W6Qy32wWY+?^olZn9l^
z2Cauoo9M#uFx64Q($h3}6Ntm6@76>25!0E6AYLY~?Lc^&=KcgPd`#b8f`>;<X%ss5
zHO=<G89!4EeOklc^m;r-7+`vh60FBe3VOK&niiMALXfHLISeV-^mGLbg_tsIuR$i<
z^bJ+hM4BdbXpJ&$q_u6dX-++KpD;c91azM?Wm6?pjA?{IEwQHc^ze%_4N|Z@-c&{>
zu@g*BQ|dX<RQE5)DO0!-{+>4F(CwRKT3-OSlTFKBhq4sYuit>2G5HTs{aLE%iy4Tf
znLIU+NjI%%go_!bXi5QRn)DP#%`)v>jK*x!C_VFYOk-47an{7Y4!gOgioNhR&oqa&
znCDDi4#TH>(@-otEHI_50j|)L)`P|((=j^kQEcj8j>ZyGU<TEHo;RtfGNROUT8Gv$
zlerU0%T151h2IsXS`?|+Rhr_dCZNhx{T}eurmTnXqQ<mAf`QhWKKu@Sb*7jU0P0OF
z+5t6~hE*Vqrp6!PT9awdez?|bTH_4B1=AziOtzR_ewW^Vt)^RaceI)QOUwOsQ;Y(@
zi>APZFwtSUo(6oUDdba(_mV03NA&fWjxB}3YbHKLn0ig$oJ3!rDUWWW>!x`)RAJX|
zDtrPaZkPgSRXAXJ(jFtbX}VztGHB|xLUP3P1RWEzjhZ~^%D-odqM-Sh>9+#lCrp-D
zn0R3FSpnB3O;NPKm@=8j{IqGoVTe35U8XGYjL95}zDFh{t*~cJJL#G2U_MAwa?srK
zDL6-SE5$0D%(C|Za5fiBVn{A#hjMt~YBN983+iV6l@_(`<`cAsKV*KHb{ih%5Iu(G
zX?CGR^kMT8R9Sn(yvP%}z050Tq0QUOrE(M>^Fvw$95sJ51>$SoNf(5l`3ov_@i&hQ
zp)tU0a)6d&<~7SP+(2`l2Jj%WZKV}5!REPkc*Ta8uX@6ZQ1jd!@F~pvM+yvvn~RnJ
zA7Q@N2TRAz&rJdtX-@eWjZx;GeL<qlU++ZY2{Y$O=ss!QWdRps&Q8LN#+pCxMPr<K
zcpe(#%|Bb9I>G!W6__WQ^KH98Pno^ng~O-KQFKHj$*dE@r)2Xi-P<YVH>L3DjCpqm
z@TulE&1g(BJJSL%-Ms7y%x9RB)6th{j?|(r%lv5r`m)Upw2I9!`+f#5&YEM&!R4B3
zc489p%sh%(6`0#Tr}Gbm=7lzN7MXvPLQS#xI!#T9+20+bKX3Mmf=H?PbJ|3gnLqj!
zedT5^UyP!{{CW~ZD$R#pLt~YB&0I8An|JSn7d7TN-(h66=4PtduQUHfHR1K<yPv?{
z2J_$VL$cBQE`!#eO=jO`;9|4+FWRtPFdvNo*J2*|4-l>9aH{ocGe=*6ns)Pd;~*E!
zt7y;DVNUl$U#EFE6G|_c|DmHDm(6DSp7Ry+2Y;Zi%Y1~+Qgxe`PzipI`4##a#Z|Lg
zANsDDXOJ4P+4Y)3b78R0+?om9H_ZK5mD&xM8&^Z-rg`~G=o>U&q_FXjxt{hlx6B>s
zaP+pBI}N3G%)hUL$gugJGR(z@IlT$oU9;aFaHHmXn<076TupT|W9Ge)fRCHM--o{Y
z=9y_skZr=;Spqc=%<?4=oiww^(<yTog`%g;)(;{2(7ZJbN@vWAX;=5ioJ6~vS@SQn
zCU&r7Qq|Bw%U}u`9WCh}fpfClN`h`@3-fI#bFoz3ffiTGVlQ~%X5oaR(cQAY4&;!{
z((@NAd05s_%D~g|3WaYETeQcZ=7?nxg)F@+5)n9Wi+UOceJpl#p6;lnC=hsGOY0#3
z{46J)M5DhYZ3;h3fTdIl+%Ze}T<8q4B*z0DY}vzy`4CG1Eoee5f6;z3%wpS^3mR^j
zqAJM<%k;PCJZ>q?2O`oUql|8prN0r4(H0eLO;1?9IgiGZmUpfK5MwEchrw72cOyug
zWnC$JinoMO8Crs+G#!A`mLvu2CRvIp(35Og76*S*EL-R+L1!#7+cW4)wVa_71ZkGk
z-56oIWiS#l8I}(TpKZC}3t*1r)f5cotVP@f$#a%q+EnISTub0uf#nM2?F%i7={hd5
zjQkC**m5HP@DfWCg=WuNlJe14YB}{9aAlTB14PO#9eb(%v%;c2g~3!>s_D62WqFeh
zdQ@9ppdfIKWdU9fcC{9FI-*o(aiIl%y=7l1xCRS%EhHN)^Hu=YWSLqC(ro#Qf>#$T
zTPSSXVp%W>uGO;mA6RI!_)*HN-LiHaBrjUt`h&jz*<ndP2)5JWTnw2@mQ8Aq%a%e1
zxOT<z5|ylUS(KB|)@_NQ(*GXIZ&c-Y)zbSl$TiEEP$=!SyduG@^;tgL1#;ceLkYNk
zOWPj6Z&+d}i8)~DHe$AKTH<M(gO<tnDgH8Ksk{aDmPPs-fVVBd_$r0n9m|FVKnz<B
z(PnnU(n4ng?^?d3C(NiNlZj#9vqY_e<d~&`g1O_CIC_EHw+vHaX~Ht}JM2ENbbJro
zq$Q1lgj1HU|AzO|7WroMJ+yo!gBIJ2B^7B%yGNEO+H%cW+^NjM!5VT4+MKMGP5_;)
zSEydW#TrTR2v_SL8zAXs4VZ-`cdI)c5j<r5hq5*vR(IM9ds;QLI6Q29wE{D9#JYk3
zNiXZx1!(lP?xxCCAM4~JXgO-LrcuS2uhnfCME$JGD7E5m{d@`31X%5#g6J{px3uI7
zv~HtkQIPc)A4mpU+q}SqSbw2MVW?H)hsH1~$|!L+S#xQ-9bpZmd-J$;R1J|x>mvG@
zqO5E>4<2oung^XHtTs7SNuIO@(Onf|{dfpUW34ABr4wgeNK2V`>%nOt60FZrtm3rw
z=4k+utUh}%>}0D81^ZI0GohHnGgb#bh@@IaSHXOm_3>DkNVkSx0GDAsxfGL-W&PI!
zjoH>FdgJ6+x7joRp0zS*J(p`;)&=}IYw7c7%(s3;pL{5=TFPO*&>He3`iiW)vj7%b
zf1)5%sWo^rM9Qqn3MehNswiz)Vcj1BuF|@ds=}(QDk|itw$7y+w#J%lhQGDeZB(0G
zXLX3C{9nDb?<2U_VC~@n*l3NR`=H5sYatNL*0}?~U$Ev<q_xGGOkYK6waSCRwORKq
zf@|&8H!Xl)v<~e8*J1sUR#~0abRm>ovIZ*9ciF0}gTGg-Uzp&1m$l(Z=<K$>IEUh&
zJ=UcTuyobB&;prW>+6p}O`o;@0LTsN_sPHySe;scxM{sc2MGqPrVn6#$eKV=$y?Tc
zDH(a&+Wr=}J61s#aKlzErQ=4dzO;M2YYmTu+oRS$Z$a6(_3yI~xo>U7`30NZgw=^|
z+y~Z*)xb|$pQOk1lvU@9-(cE0`U~dbp>^K70M1xF)&ls*>f#DVXRS|A62`&aZXCqX
zzV&?=bh6)k9RO$h$6kO>F7~m%0^n*db%F&q`@~>a@Uj2S2y)c^t8r+t`PzT}3uOH4
z`wC&u-#)qq<^$~2tD!W=et9VxgYA2Ufe*2Nld>S8_BZDN7-k>%4J5<u&r{km!rq<I
z|Htk9=?qw;y@2wLQT8FU7KpZg;}*CR_Hhl+a?-vv6*^<=ONP-HYqOuA(BB#R7as#K
z)!t<ZOr+b(doh>{d;Tsc&9rZ!Vt_3BzdiuTwx9bdNRItQ86?lz?^*(-x%LS+F^D|-
zH54X0Xa9vKMDp!@o1wG7{&zV<3hf`h44p;xyIzE3vAwki=1c5tGyl(K*#Cz%9i{ej
zDMVXle~gwQ<@V*yP*Y)_P2urM`-r9Bs_cKHyh*jaizo0k_8|r6tF=!*3cGdoWiLT@
zz5Ra5_BPmuJO@CdeFas`HrWS}qs{hWihW<Oe@M^V7W=I>`hr8N{c*~Gwb{FqGwt@>
zYtVVoK87|s9rmM3p{>*Ye;i$RT$a@rSJNB~OWUTEWvNZgQJJY(sc9<j-h1!YvTZL*
zP=+8wP(+la43(vTELnnpihzOxQI-fY1O$}z`<~xl=X1}#_kEr_&N=sa-<S^MEvNtJ
z*nG!nC++SUoETIreAg-XAJFbOU5LhTH9F1T57(NUHqHiUc4CwO+2XX4(&(*D1I|F+
zcUrq2Bh%(2siybufz$6a(X=~FSp(4Fw7d_<hfZgy0JGDn_$L_ba@v;#gWXOus5-L8
z=^CXrA31%q1g&1D{txkV_Bs6;1Z2OHM;pW+JN2D_+<;RUB`gM=w7WqYa$30zUOaJH
zI~M{^oi5eU`#0?L-z-RsIQ7w2DMp>9%>r@E$(PO$<4y({1f3cE%i*vKBmM|lu8cAd
zu(&ZgC<W!tI7{h|-HdLkL-Al#3o#a+j9KwOdNHoFpcCE<OAEa4VSH_boG;_MQ;^%o
z`1BavfAC{$+yfqehK(+W?Polu*lGY{HXYys8P8F?H;D1#_do_S7WYE%0OJvv4`HyM
zgNaavl<FJ~GFFQ5+Z|%06oVGVSWMMqhZ$Y;+lMnmRKIeBv65oB5sd0AAdfO6l)!cz
zV_c)cs7OY{a%hWUypaRJXvW|uBw`r;_tB?V#?Cz0J<j-*@*XD`KhgF#j`5HpMDYy4
z4zMIJ$|$~;$QU-ki<6911>iiz2!9hMPBX&KKy?yh(?yt1X1q(Os}#oSU?5W+jBkDi
zOk>=n!|WM`?H7Qvj4wZh(sYLB7XTTIzXyQKWJJ-a;T)rI65P*X?53K6Y{u8LWy@hS
zQD<@)$qbBI9^){DI?pqtA~=)JcuWQh7zuB}d?CX~+utGvlh(#!hC}uo)LdW)6i`#b
zxV`|oOBvgQXkBF7&jM>1gLMwt${C!E&|SgUMAx=1F|vIjSIL+}k+^EcK{~J2FcwlM
z`5I$6WrVIX)~tfTTE@%_=&WO;QSSE!<E{o;ZZdv&1oO8TKRWin#BD|?9h>VJ9wQjU
zI}Ep8@H8-H(`0g&(Mm-K_ZZ6kP}9hGCK#Mej5!oHZDy>YC_xLuQwwdajGGk2xzE`D
z7QAR<6w-eA0ppPl0_}_yX#gDz#&m#(j7h2Ru#@3=#sM{5jG5K&qMP9#2!lNg%NAIA
z#9%B2PcP%(YoPTp{At?hXJp@orN<1<MzjVPM<|9p$avu)lnycGQbhU*WBHe$J!RNt
z!Td0zj>4EDjF&!ymQhCGCD6tgTj<jCIOF6ny?@TkWs||`!kkW(-mc78G5WNd`S>lk
z=E2PS7{HTxQv-=T%<;RR?PczwSfdy77aZWG_%aj5!LpBeo+6Ka%-m7X0+;~{p)-(~
z{0>?{%my(=G?*#P0OtYb+Lyo?!i>$Q_{$;YI@<n*F>Nn_c$ispA4<cSEfh{U!dy(1
z2@%YFA4B3O^94Fz9Ao}M+sR1g0h-XGm}To=DVq7`Hgqk9>G?BQVwp>+4*EDV{}x&&
znD0`^KaOb-fis?|b;6J&FqcsF(virFrK=JrnWE`ft4=Yu(K~jU8A&&+l9-}#w33-^
z3!p89d75h3Q<)FXLokimOsAtW%<K>Fl$~WZR>4v_bC6ci4CZ_qgiPilJy^~$zo(sB
z7IQbn%(I!BX&;!we47@`Tn97iHDL3YZjT{xo@sjukk9<*I6wjO6$U^d^TwyJTf}UN
zgYIJHx6wdeV1Drcu9Yy4j{#ZA{Oe0}?IP2gmXk83D}5WZoOzYz&I;z&6j{2&<WWJ>
zW#*l9(5^5iJw&UL>G*ykx_y<oo{E5~nA6UISk1ioFHF=huU13w8uQ{+bnQCRmI!1m
za~|b3>X^rFfp&x0Ktbf2%>U@K8@HIE78tzETuSeKJ=3udZr^3r)2{FyGwwBb*vM>J
z4!I`gNeWCiGqdsk^LT-ny$z6WWxoDA#^OHn75XXKn0ci80rS}gsA*@;plD17Q)q?2
zLniwRXzOIYOdlZYVye=ht(*A^#kYHy?@@H|5wnvIXL^~-DgpYK-S0tlKQoj*!S$GV
zlGeQers!1%1P7T#v@8uVt7sGcgc%bJ@Ra#H1wMzF#g8F4!kpa+&QWF<J*#8Pu2|5<
znf%${bY@}qi}!~$`DOU)%GyoYH8<9KRQBr5DyFg6%?cldT@Tiu5-9Uz{X*ZB+{1Fu
zr~40kS^Ra7@M4wFXJEWp6(57>!^)?qnJ?=Q#mDxs9!0~1AA$s6@n`M44}bTwCPt$b
zz|zfur9hSk#iD{(^C==0%sMj;<N;QEEjUA1SEzP3lr_f)XAZLJ>9lZ&H48I@V@epS
zXAVppX8l8}S~x3U4O&N7uKj35u)d>u^`or$*MU67YR!bUNR~%5)I_nqy$+UGRy##E
zj<Z7PB!7aXre8aOwL2ZOMAo|504G_sGzTWJKBtvEndL<>gA|qzMTQ-zthIE~Ok=%D
zQ`#BU#TK}q!TNp*KqhOz2yl*7L<L}3ED4<fvRNOkLf3LwJ+uMLWxYuGzdTmx|Lb#E
zI+|beSz0!nDPSGp!QVpGte3!9#EJ-mvSQX>bk4oN%I^cM#KHQ4!oH=fVk)}0$XYfL
zpp5m!WyqJan*U#I$V%S}gO^xAl=;5Q+AtZkE3A1O*sWxB_n`MzS+iPTw~F=Ao9JOR
zOKyduHLQkfpj~5aqJY|U)>jnasbyXH9ke=D-Y}3iSdJVzpWI~q-3H<<*1zQGZPt!_
z2-dTDY4dT1rQQY5z)GR#>Mm<nEND%v-gLO%%=(Dd#uk?0BPeZUz3BvSpLPEPJZxiq
zM5m(%tbP%Y?W`;0QwQq-B?TX{{-#;0lO_BA|8I7&UVIh0yIE(cGPj4d?=pOQ#OjHL
z-Cou^6r=28SvNwWpLLr;vyWN3i8jC*ph<U-<>d;cL#(eT-}!`fk!oR|vfN5Q8)iBG
zhj(Oz^(q}2Mp;ZJs2*cId=GBBu-hL{{?C=IYyfa$U;PfcJ=l{bK+u!DZ3C3<VKbs3
zv6sDf33Pk0mr^$0oBa+&wtU!X+SvHAr|ZD7kNx{h06*-?;IBXXKT7=VXDi=FD}b&1
z2fuP4`=d~(4r0GgyUAeow)=Gd{Q$fF7_cGi@Bn~Nb_7k~2iXyNfJ5xxCIK1F{$Lx-
zA7NL7L1_fLksgSn?0artImV8pP-i52(|q(Wirqt}!D#l6bQw5?Z7BdtEZc1%I(VF2
z+zw|>us<t@mN<6q5~}}<XHQ)U`2_ah5r9PYMcRg*WbgVGJg3;clq5LKzE3rAN$e~E
zoJnS{_!lFS!e&qbODg*`ZQj$^v94e_!(NvOxwGsZ3Phx{6*J*X277ZdkeTezy%0ag
zUO_)$7JI1)a*k~F@bj>n!`^ZnJh|)-y5MjgJF^-l&a+)8+?>yz5d~xcJC5d!LblKy
zYKquDP%NsLy__!6U0}zE;7keoXa!oO?00TJ*+uqv8&sFECo4g_#5Ph$x03x4U8lRs
zW`7M2s~qepv~#Rx7g`}$!|vn4#5MM&9Y9`ZE2u`amfgAt$U62nv^L&gZ~GCn+w5d|
z<LcR0sp{ws`v7HD8`y~pfV|6INCAv{>?JASY-Hc2ip?hW5lWynvs>sIU<+GAH*MS4
zj(IE4e87H-wsq}n!B$9gvVFb;=weStDdLoF_To@<rk9<t7AE@GTi*rfXP;dQmO=Kv
zB~UuVp8hhlJYmbm;o%5-bs1=*?6+P3=NNmI3oN;C{?bB=D`!JAoN?o<egsYr&T9_Z
z&3ba)48;iT;pD}k<;{7ID%*WH8^^%v%ZYgjYWz8zlTfptv+hF}4B-4U8=S$M>r{z&
zfMfaqx<fdNXtq7X$@hR<80V|!v5Fq%Or@H(2+luL&wrF-q(|o%=T!kXqd8xSXdR5<
ztfUNfEXVIT^dgRv+=W&==bxPb37o&FF!vNEoi5az=FC3^*OEAFfB2NjIkgu)rE#98
znfwfgu?hkioU7FBOiuf9fODM0r;y9xZ2A9DoRdXGT6vtRb8x1B({+~aKNNCari^_N
z=NN7IN;tci@U4_{?I@hN$oZWzU=^HIUqH<@P7y6`*Ew&}EMLpnM@N`Cj+Z~=Zg9@f
zMdRBX0}poVIWJP(=p9bLaR@YUo~1;|U5?-<n7_yQlB#AKIj<b2^{<IjWP_z<j#mNX
zTR6>LFyG3V?2p!cj-CPe2b|T{(Q4-`+X2oFPWE=#eaP|r4N5yXQOD5jZVvAgbfSlI
zQVP3|IDcM;iC#`uGX(lL-~9<>KS%Hd<OVtXod83em7~z<c*0pq=j;*Aa~WVA<!Jtb
z!7&bh0ea!g{hIbgF5D;zD7bP9?T~QezDN(EJNFc&5k0tWGr;1>Wz#~xhnq+}+{=w7
zWnSEWx1ulJTouKle7I{5!Czl)-6DwZ<IZt~PCo~CjB0}XxxO3V#eQz~a_|Ij@BRQw
zfn0$If<atx;9=uFOV>sYa1Wk`-4O0R8$c*`EoDCsaw|Uv?GX2o2ROsIjr7bM;Xcy>
z^AX(jl&Fm4cFq7x6gO`k<f6H4U&GPkTt^F)W1ryONdYmAJHZ>;61ne9g)=9)*O#Je
zr?_!HKut3D#b2N%g=?q%Ybw`5Nw%}xs6oi3bGL7SmJF_iW}hr>5!GmBbH%X`$l?C;
z04(RZ7pS}`pZlo-gI~a%MPZ3z?imM#_bzbr>Af%EcH9SRDYvg1UR>n%y$EC(_g{K{
z%ehN_gSHCpReHrQaVI6f(q-<vPr!18TlWLBRdQEJ;YAg<kfK)A++UBwiyAJADk83N
zhZX=_=dR>|vzE)%L9UMb?tXgzZgO8HFK%&n&4B!EZmtbp)N?1K!R{Sy3<dNWxE9JL
z-sP^P^yNM7H<aCO<bGBL6HVL$G*L8jM`M6&;eHzk(8fJSRqGG9_o%+8og1h@w>!Cu
zY4_a4)zK!Po6DO)-yiJZmKvb@5%;?#0KHs4Dp%^`F8drj{oGGqgo(%8!(1Q-xbYv+
z6U?onsPPato{A2iaNT}GpPq8(?m}yr``vWd9pTnK3uU9+3B~Y!jJr1sV4R!%BOG<+
z^_b8J7v69eo&Q{UTAHEUc&8~@=Fa2MQDQeQl`2m>cu^mM=E=MC3Y6~Qd3eFnUS8WD
z;Pm2c*$hr^-lj-s^Wm-837RkOE~W4H@lMmC=Eqxc6f}R{tp>QZpSSN_fB;_57<2~m
z!dk)N2;#k81c_jt)0Y4Tc$NgH3E`<I(-_L@m<kgIdD}n6PjQHMxCC~?cuy$UcbFGL
z)j#39`gn}Y5#FE<AcE&Y@9k0EAOHV639sg7bRv=$_6KxE@iOUT8_oN)06xX=UPwnP
z*1;S49c~=wReS{#CwQe4rH|t+P+-*Kc{w{^FoAdHZ6FhQYx{vb$-BA+@~3z+&qMcV
z-Yay+Hi>tT7W!n~oFAbjg?D`%0;#-j>ByDF+Z+R0I?oi3E@ki*1_NaB{yqaO=Xj1W
zIvQv3xR>C5HZPw%&EcJV7P@nJn`oDo$GfxzeLBzkum+s@JU*r93wRk-P+G|AqUc}|
z@820<Ddvq(SmOfkHs!oZc+OPxRLU!-n9xOD7Tx_U<4s!$xpLmrgP>LLra4$(y~OiP
z1Gvm<ZUOcRFWU;%O5R)<lwRe%e*_X$ytnA5tmf_HqH8rgJDtO>@mS43UgwR`dAF9=
zMHjj2c-MXg%MIS-wP@Ys<$ncbw|JjSfZMlubLo>B^}JqR_;i<d`9C`U-Q#ut1fE9T
zv>5O-@!F{xrkS@o9VS|M8!rIa$}6ON&3)dhE5O;t8-E|P2fTK7aJKV)PXe-oXZ{Ju
zhrDh|qj&Onli@`d?_Elqck?DYLrV{DCoPJPct1pevzMpR(fO~B_wGTc>E{Vb(EG={
zSLj<-1H4Q7ATh|x?}gnVp6xMOPk1{hm->|FPt~u(yp(@nX@r+<g4`%?9S2Isc<a9b
z80Q61y^k|rO23^8Kl=!rapk{4Ke`)#qY47<{C;c~98-4lx2%P34}L6tJHeA*bRT26
zho3?DhrRq1n#8>Lg%-$r^H<z}ybnLN2m-$Ruw+=;$5%gr7k>PqO+fnd^Y!TOe*SZm
zs}A5ZrlS?ezx6%36vY4G99V++8-IY#1N>et#2q30Hz}+b%D<lqPY?2gzrk1>;wSBZ
zi(!11v*0<*|K$)&g!BEWvf&87gA#ZV{C!kLdX#^OYP*l|$9F?%B>xTvttkFxny#Yx
zTVDl;;a4Aqg;@U3a}YnyXD<YZ=g*>GU4nz(u^lE7`5%PBx6}O1Z=u^s{C}3f;bi`t
zQGg8o3+KU-#ozQP)MWD`Uj#CT?_LCu%MYZZL>_;TXy^H3-$7|Uzky=N1^k!jl4>FU
z*=Fc0=DSk)+Xa5sRd`s!&q#)NDc?~u8`z8d28y|t@pI`aO9g-13+T)x{xlc#@G^fs
zeLe09zoQ?tO8$$baQ`Zw=?PH9KR~&SYX0URbhL&azaPkJ{Mw&k;yQnSC<JQx<-xE}
z$8TGW)(!q|pFr77{(r~Ny2W4bV8X<0zH1%aujgy1#QP5a0aeO1@N4O@yvtu(2&MP<
z;yifR$oHimwuzrX*8-aPS!uA;!spZ0sg>Wm7p?pJ@+io)@sCo)^aFk>otz%>r#%au
zo&2U`aCY%oO#t2eZ?ouZ*~9<74B8&?U0y-Ad-;o~B%zQ0&&!bL=l`%7$jAKERX`5#
zbIG+q{?-rR(-6O!zU1|UuWQ6uKIONr1#OuB{Q@9I_<=n@j`DQ}VQGvX82~WOuh)a-
zET|N~o||CX8p^-B3w(FM#BPBLt>PX6%RCT01x@q^H+uw1if``~%zh4C^AarIh;i~3
zO#TX%d<2^Vpv_m{LJ6sTf)A*sz)$cGWmf$K&rv1De!)lcAs!&OHXQ<if}nbE1_`!P
zNo=s-D?|buQw|7H=<Ns*oV7qORPf*TkT@vVNXL{zg1aeD8YY-Zp|Hb(`4Ny07i_1H
z{ZYZcRPc68!21KVNI`QK48{l!?gEGv>=MDmaRG~pOyUI(Qo)iS$ld|DL_vEeRG$_s
zxCf*oNnkyXX0jkS0WPKqHqeIoj39_M%x48ZKMxZb0`ok8Oo8t^kUuBrW5Gn0pn;AF
z*@CU>p(a=G(^Am#1i#W%=<|XXDBx2dn9&b^3k8wup|eOZPSLVr!M{`@b3yRlI@l|9
z2<B3K{Y60*9V*KNhNG}sA+Y~})+Iq875`lp+#UwFB3R6a(n`T0$_-WtmeGZpYC-2d
zaMlP`QD*g;pyoVU*9BWC2wW@pl>y{U!4WEIxg`jpDfqTvQ7>5P1tKzgN8oVK5vD<4
zr4z|rL3kN{-+O|6Z=r{cg2^<Yw+r^s)~!Pj*aq-W@YzIo(J2TXgIt#YcOdZq3!*54
z^+?e8Hd?)c1Lf#wzo6k1#0LdaeLx!$_|nq+L{LxB=BEPtHPD6yFFFc991(=jseM$?
z@FL8Q394yL9~XQ^^PIDA6+LV&!nRK#;VR5mqU9l+HU>+cLOUPGJ;JB-l<XD$Mv*Bm
zVQ4r#q(U(zF@1zZR1@bb{FGwm`-HRTl0cv^Xdyt5aC{!cUxI~yPk_M#!fHy_h6vXT
zKxwG3lP&@r6qeFS=8$j&rBuU&XX)U0RQLkzVU7t;uLFn_o+?8pqJ+QEek@uzp%%Jh
zgpITdjum=0!@_Z)#sF|anB59PCxtS~teg@?O``Shw9t)`6G_4aJUE;zyh?l26k%f`
zcv6MVmm!!Ytm=f)Gs68Z!C;0^{xWoD3TtXWJ12ZS540?y@fT>x7H-)HEjhw&CXl(p
zi~w-v34f;&;Pb*;_aTrk+(4xP1;UpXQvF$>aKad{rNa5NVZJDI*dbpg49`P<%Z0Kx
z(BBH-BszIr5<bj?YnO!;RGDx^Xrb%QmBPLC&~{CD<qKH4E-Y*XvR3$j;%jxnlqu-%
z4dDd}Xx|iGc?!8(!k1eyu(yT9w_(9iFBDO-tWlUsXSF7witbW23%An^krrWfEkLXA
zKOVq+VJg+lwF&3x0UiiDDS_TDjCl!4yM@0JvPZa(a+!~WVc9_T3a?Xmu20xJ1h@Nz
z#Z<8USXe_f`vXGH&jAJ<!r8PqJ{2yXh32p@EFVsd2tzkOVpO<#BeabP|6T@`abZm>
zv^k6Zq===9sE>A1uA)CFW9KFckVCh-DAomFw@5_wI$ol?acFsq0w_J@Bl>a!IDJKH
zVnEv`DjI@4Kat~0n*97laq)0?zi8kQ#v(v8Z37I3h}^Ou7%Ezt2G)b3zfMBiA<>cu
z2!x4rRKI;#)a(YI!bR`=3GpMMG8Ifjh@2ScM6~D<J$f-B4|?=sMYrkEJ1)wmxZDX*
zStG>bL~Rbb>K8A{9)y|%kuOa<i6ZVOv?YsH{{b&jL>{qlI8_uq6|^)_55*47i0Wp6
z<*cX#CHzy;Mcc&Ck|CN*yUI+_rc4;j7VXS|c#deG53O9$8roUsiK6K$$$61y8XV0R
zIS$kMS0ECX!bG8H#u9)c(TXzkw^%fr(*GAkKhoWq5>dGl1}j8wQLN&UC}se5FN+?&
z4)H6Z^%hvF6s@R&rK_SDlzyxdJ^L$6REx4MLT8=m2CaWLM9=zy<)$c_;uyC?yOk7w
zxh=|}Oh>&)KMdj>QT=)dHi*0_C(<lZQ7pMd)VBzrRrCM_PE+oSb}s{H6IEwJ=>ySr
z+Jm%<rk6pyL-h7`fF4mQRgOFowbHZRE9!b4-uH>tQEs7M^dS!(J{EoLF%j?Ifanly
zA_hfgXx?}#T0-HUVNuFzfDutXMK?x8{uI|66S2imGcH<ShBKbxxPvgUM=Vc*_+IfO
z${2Ww!|7hPw>atn#C^nH`~wzW@ex1R-6sxj1gD?){gW`{FCMysmSev-f(pR`#P<;m
zni42pb_Tu$iI3ceV6d2#2sI(%<ENlBRQ&1zs5vP9m~KxV5*vPle3-a}9{F&wlBU@s
z;we<r79qYhADqX;Ntd7{QaqxB&M0vNMQ@|UpVQGNMm%vYzzK)g=~D>Ci94tOI$m5t
z%YK4*k{wDD#for9oD|o51mr34TeLwxEsk)7V3Jt22)#%V$I*^4Rot-$AWeLBG33sO
zmr>;7toZdW0Mf;!qv%AYc$i9^&xxhZ5YG}ne-Ns(#SW<+x^u)eTQLZ^V(BJ~bDr3h
zzR-AHTyhh%eDN0A$Q6jY12Mpb;&Cb_FB0FNBCTTaC_T>?#Pu|5m55bzyRKC1Ns-oz
z;`h!%yiDw%Abq)bs1qy|;%lW~xg`FJKCE+DywX9toh#xoin3RVzoXx&TKxSzI9wxs
z<yG)p6VIm5(sl73DmJbaPo%t5o%k)fbbV7CLW%QR;($(c^tL#E0$A$BzkUpZcf=Fu
z;MX8dppEi9aXKBR8pYyIz}X~zo30kNh@Xw1{Clf-2Bqchizg<+nKm(h5V{|TcV&Ur
zE}lX)bsgdq`ZQvv*i41UUE=Rr(V1@XKpf2Xh)>b9@ksnNEv9|qMdzWVUtBy7;ITOQ
zG*|}2rE_3#Q0zm${gC+mg&2fk@szLV{=<kk{a*-<ig!E%HDh80U3ncBf8Y;!XUSs<
zOSnjOQqixg<P)l3c9T3q(PMYXURv>XOYWZl%|r4*GiaWY*WZS~9*LL+f3IYSCPptw
z##uap-jXk9q4kl>-HMU%mDCK<`EQ>@eGl6FBo0b8`%5~H!R~&^tE&M5B>$?RCQu^u
zg2O?QF8Wqcuq6E#m^dJLgRUQjNDiz3GE|cB|J<TvY!Z5SNb=4Vm<W?3Oatd($(s}*
z3YTPl3vfiT*cWmUlB2YXbsUv+Zh*uwNoyobL`rs3$}UQBhCb97EqR9?))+|*8$FDb
zcu@@cxa0u`obi&<_aUDknNKISM9HgM=sqbqwGX;aNq(V&?rDk3d*Dox<k9tuWXXC;
z5vEAGX>*q<nMu`IX%0yT7p!L_jZZ;5D@m(GXVN9#P%U4EWYz<;G9|ycW7y6~o(@4<
zmgMwC7|fQ;>VTRY$$m3vxsq@%aOO!0>Bw|mlIsWYe8~rNJSmXed<`sxk^`@UrAYEN
z)r}TQa!-Ntg2eGJg-lA&ZRjqQe6|o?T$FHWcULA^O;c&PMDr$E6%s%CtjZ+`XBo^_
zN;a+mxGK4@3f@;qo|_JqYKiIvfEvjyAvmu|N@@VEOBPeQwN`Rq1cvG)?^C4nhQxO=
zkT)eBjyEx+w<HTF@o-y`_Aw;tCA(?Pzax2e5PmmEzWfNCxhs*<x_eL3@h#*VB|={a
zG)dxV{c4tcPETNqWM3eVt&+);!FgXYr2@2eNkk@E9g?L~KJ!rW1|@AfC5LuHXO|?{
zmtL73N&JtHe<W$3kV&t^i7xB(Ns6C`e7{690NP{8)|F5*C`o()^UaW?m6FX*Br(Gn
zgr|~7ia-oYw*Lv_h=lhwOpHmspq$mXWW_dg&{^6+SzcFZAw@pir12Zja+j8FqW>S;
zEv=0OtB3R~<u>+6|G5INS9*^sM!lq6Yz%_8G?^AvAL$OdYv(JydKU72(#J1D&R^>O
zBMk1Bu6Yf}0O|X*GYFL4eF2t&q$VjkctFaauu+Kg^Vgv>RBEGYn8VTx93~x8!lfY$
zV2?=CGawNmE&T!Ds5Fn_Mv>A5bnK0iPNzg#wDjC1Xp51y(uOKldglg^$E9Ob4SGV_
zN^!k-X$Gyy3DS+1pe0fI8SVT|N;l5}?UeM{NQfs%PrL&0Wa%$2!%;_yG><x(D*avw
zi8SeCE5`DSbRN|koRy{tz>_K6PKW4o(m+byW=U62gf?3`?HkDDNPndiMV?f?1*3Le
z`rJnV`O;1F`xZzQAHravw2$JDMN;ny&@M<vInYuf&7ilq)FI7JNAsfed&=*YNyEN?
z!E$Nc4#;1U&ZD^AW$6q%T34ixXcD?AZQcTwD(R^i7}9EK?gTs#HPTloj&V&INYyO0
z(x0o*-#V!qC6aGQUzrGSQ@YC;owy~fr<}%ZsgoGa+>tt(Z$Wp1bj?l>?@HZiiM=QF
zrh`SJv~L4go21WC<g!IN^&LpGO5a-z^Y^8l6qoCervC`JhtglCpog8(JPo|)l0JM5
zW7sY2y$9qYse3+@^-ASb5Y;D5Hv;raFCKuF$I`zX9%v3oBWde4DDBz_`6p8CN_6z8
zw0JpO8<yrS1{jgf4FGafYNV?f<I;}r;ghq>Ru2zdWb!re!c~?;g&=OS_EYGuyKF!N
z4|mJ*=;F{GnJ5|-_R3a=fW=F;khU4#vcRQOndBoYqcgFu?3u^l*(Zyq<bt2<pSRHq
zf7u*L<L{S!R1MbxWYcM443vHG5W0h8x#i#tmId!a>wv6|q8lNyoQVLTvhWW0bWrvw
z6(${$Wp<*!VX^~rVehakpCVe}vJN*o{~eJ9E`x~(SqtSKj>;xdnZ_|$pdb1hDGQ)=
zH%gXL2@oxdrMlA?nTGNJu`(`Iyd0NF=<?PH+3MdQ5GR}U0UV8&JxBTT1lgKWa3;!9
z>GeM;v-+TQN~WW&#A#V|HJ$&GWb4Kum@I4G4v7?5LI9Me%1(X*)-;)5JG7<CR#R?1
zLl!6lXQoU-OGmcs1InW0$jay^%#}?UL@Qs`bPZ!sAe#{lP$(OuE%gQ2B6@O5Wd3vn
zDV5DW2Z3_g?{i_uQ6alW*CsE?0%*fqDVt5H=c}?>E99$Wi?3j0uE}0K2{qSc>uHgx
zmG!bAe^Ztn0G3;_f8GbUEz^AkmIm3)WQgCD{Yk-<d$Je`s5Q!xW<a1xW}s^y&9c{N
zkJlm_rju=}LpJXdbnU)uG5OslTk8)OAIR8+;OUT+#iR95=KB>|ow9cfP}3#bZo_ZT
zEgL!kXCBEW)91{3Wyfe{>ytUrlix3^TnC+xWqUf|%z#Y$CuoDR-px=pBzu`M22W&H
z)4}po<~ZvOr-o%+_n>q{Hu+;%8kG%FN@q;AneHf!%l>iDvo3#c56rvBmv4eLSGn5*
zu<VvEh=f58xsuMpp7N4fnAjuNjzITbd7uhNFL~lFaC*z#3c=|kANGK<eeydL&GeJM
z;Gl4szr0caOZ(*$Uk5Qj9!#%spnNOUkp;=u-v9`fzuX5kq4In>f*h3J{}q-F$=~mQ
zK)8GnEk{S>LqgCZ<lcn<N9C_mx!y7P*YuP`$wQt;D_Z_C1+QY{+x*drm9PE50pfA_
z{%!E$ggh+{tvLDCAJM~jIfEk0335A4;feCMpFrY_{8O5x&&oS|K}(nWn1RfY&lo^|
zGv$g+&~i@RZ9+%0<h@jqkS!0k0huFTG8L^{xquEbdGa7Dz<GIA>=e9z`En73aSG)5
zR0mclPo@h~Me_NtLus-6GjEu`Am6A1ONsn<+PId=OQ<~YqWq0vI8!FCr3`1eyq~IO
zE98uR2wak1Gyr*7{`)z2ctxI^4$eyX@=hSH%6C$6WtH4I|Nr-I<!N+v=eqnQN?+E>
zMHAuvP5HMpncR{upr`D%TzwS=>*ZOL$GaoHMD<Ax^0jnPqfySFlC37Wlxj4a<q^XG
zEpoqU5O0+qJ_qsp@+umOHn}?;mmkO-w*cDZ&whgrIy&T^anO7yUqe+(o$|45(AFhi
zG!?{d`HDUm?2&JzkjW$YCOV<^%Ab(ZKKW^1j77hE>jkhpmcM-s&J4(_D?l5RU!?To
zki6$3uso6X(zltO%72*w+OYg>EewswFH!n%)FD4P4P6_P?_3EmE+3&X7-xmI8S*ZQ
z*RR2ESH%%}$J`WoG$ihdzD^k2t@xZ?H4nvamtoga@w*7fJqjDWTzeIdsDju_F`*SE
zycMl}K>8@YY6sF+v5~en`xJ_=;LLu7qxJ}t1}OXt;0aXtyaG>y6wB$DAFODkJo*7e
z+F#HeqTo(|!BB-H5b_5VzLYsTr056&XPBZS7XBVqY^Oq<aK*FfpdC>>IS%s?ifvTZ
zaa3_53F5~TO$-={RLo6+`6xxYqaG%r6}wMBO^o8y=a4_HxK7`hJE6EpbAFuSQ8QTL
z72E!UV1h#D2@g*yzNS?9DaE#02%J`MPCy_<@g5bRq$)Txm8B`h4?+BlqQV`mvx@t>
zVK7~hAB+*rP%!9}lBxJr>wwa8iUm|Qo2BSfLLyt?^A}ii6wgz*ELY(^7bfx)5vySE
zyy7se2l)yq1zZah6;wA<sQ886%_7AH$^;iHd}vpALBS4zi4w&oTJ}p7C3FtEsK}sl
zp)y6?-{34)IG>n^_pd_Hb`d<66y23Daamyvh21NPU^-+~DzfRga8=RM1Bohy2kp13
z6|Hx{S)<6M>sr?ohYzDwr>LQb%MHc*{||aAx)pHrmZGW}$lHpPVt{%@GX>r5C<a$z
zv>O!R-_Z9z?<&U5!_qxPD_t{dRNSMDQL|#=Tj*Mg;`eD_ZB<O9%N$(_?*f2sMHS_)
zdK9S?TzRCB6`<9tsCXY9_9?uGvtKbx(Xz*i_$nwHP<*)=U{LW4O_NU)k-O=2Q2Zf)
zS;w&A#S)kpQD`i{jw%*Y6lqK`^KIxJS9G@k>7ta=(Z^Le@q5U-Dc^n_NDt*^y7J?x
ze48$f?NMeoptV=2cpEJ*r9uJVt&F=1*L;+2OVILFenbz;KIL0fVdJM<PT}$W4&}Gb
zFdv}IP6AJ$GN}>02vUB20OK62JbM9l4=C+fP!pmoS_BgZm0@|1Kcw72PjHy>+iu7m
zRwkL@cDT}wB3lv4Rtk|GRj$7V@kpf$ZN#FK=OZxq(aI1iXFjfcmk;q1O2@Pw5aX1K
zC|HrAOpJo1RHY#vf@w;x`S9Y5@(s$VoK;p*>0`Pwj3(A|$~X4HQkJrgKID+C^mqYs
zIZ8R@U~`r2JK;>8vW&ul=aqge7|d6?QwY02Y41gM3zbi|L!d}0cJ#n*v6A~LBubR8
zy#<L<<v7KHFDl1wqgAF%rl5DZ(kTs`mz7(lz_lyN-)Q?=sZ1?^hgX&2)zDU@Y^Qa%
zS~<B10yWBols&noJmLho>&kM9%hf7h4hOPMxv(CbH<Vk79O%qV<@5l6Tgty^D{@=8
zr5!HTD`(w-;2q^BYXKUR#T4egtGpEt+C3%vYiMg!cE`a|ld^!eip|QmDM!$vJV`m@
zR^^v;!o9DY^f^?wDQC7p?txNBw07mgiJ)~TpE*JGFAtTU)}k|=${~7xyOh_5(5G(Y
zI~M?Ylu|yFK2p}*f|_3CkE7^lpYl%%p!6$c@520JC2ImW2b2ddfHtVytbwv2WzIsd
zJW<Yj0dh~3TkT*ORu1iig%PF8OvsHYKMkYzZ%p}BBZ%Y5qm*xPR+Uip(^a*V!Z^EC
z5(+tbsJ!WC_EgRE0m~kh8^!$gs*Y29%u6+64rt!0wKpK(qxzr@NMF?idh++F-lxgW
zPqmmnY2&Zz`UkZAD(^ec5}>+6Ym6gMb(8{-VXEiKVfV1gj|!2)RnxbEctll`0%U}0
zT@G{~Rq2&*=9ns#e#%Hy7v0y0QZ0UjR<x>zPPj3ukVe>zRTb0ge_W+l2=NmtA1W7$
zQ++OnK)foK0^$j(breoabf~7#v~^PTW)NIFrRw_#t<$Rc6<|$L?Vbp2$*LUM$fc;h
z-3Vl=YV!#Qrm6OM!oxGF<1}fWRb@?p7wM`C`v5Xj%GFSosS;4&^PDP!II~nTSE$Zb
zJ?{*VqY9)MJXhs7`8;^?RQx{x&Z{PF12$iEo~pD8R59Doi$ax+&Id)RDYUODR=pI0
zK3z}+t^;SOs%r)Y_@e5&<zOjOt^XEw%T-$!!NUqw<pu~`QmtDDfy*k@QYgEks-&8Y
zN|o*&EL>H6=hy;RrP@I`zG_wdDLkb$s^2I)QLFlEA!v0f28AVVs18tQ_oga+9J+6*
zIwQeyTa`QjFX~m1D<F4A6-5D%2Gvcvcyw1aaV^B}sa~YibE9haWXLtCIH8bhR$YDr
ztrk_$|Kl&MDla<o+*jrAgPJx~@*eO!P;H$BzuQ%g2x#k2Y1V@FQ02w|=u}xLCflW2
z{xy8+R;{F1aF1#u1+5>cDqPU&RV|<xWuGdP-k5$>rwO#js&cwBGoYHY9bizkS4Hv9
zA=R`G;o=k3W{PJ#RsGBb7*;u?ur#6yp!<@es&fyaW=yqo2U_E*uNy&gR_~%9u$wv}
z69Vq){1j-}tqyX>knB+pjl<wxwci<7@=||3339&bTsFWy^*PFM`>FYxDgW-T{)WmM
z_p8776n+P&f2VU?pgKa0R*+h~7a&;u6TK@3)UVKXFhsp-8Cs$0IX{8(pgMX2I(kTb
zo)QOP>UU|fKddgNqU><BC++BusF%J0EfH#aJCH}!U%!LaF|~v)zB(e+(G-V?Qp;)K
zi&lUCEI^FfgEE}4>d-3m>A3m^MNUqrfAvHwK|SSXc#){Cp}_V@wUK7MBy|ZrbIIyE
zRPmCcW>DxaRqbAhR+@Sp3p&rJH-7-+S+)5UIGV1WI}gYVhkA7!u$k&jG!vgwA6pOI
zS?Y`Q6`O4JcT_Wyqi$0H<f>26nKn<ooz7wB)o-?dC13rGE9@4ipHRl2P~Amqa*=xL
zNqAqZzI7M03+fZ;K$fVx=fIg#wd;HMB`>PODdAA2b_i&iE?2+28`ui<QW}d(>O~Qd
zzpS1_U;ewQo<!%cD)m+!3|6b%s79<tZJY)9Yij@bpj}s2n_=RHdV4xLaZ_!a1LQ6B
z)$3?IP#=zk&UW<%G0b<Uv#Gf2q55@N%{tXBj&m^IrB>1otXsW_3L1OVZFK5>q<*#@
ztzPviii7m2KWIj)Uu~j!?y=f@7$yePM+?9?s5aAwN{7^2AA<HoeVWcnPt^r$pn6!n
zp%x=EqRxFDoTKV(XCUXSIk+F3E}EU^X+P(xQADF_ZW>2Cu<n}8;Q+fezrG3y56zQZ
zVDZ!pQ(@B{&EH#~d#~o(&(QMHwAaBkZ%zLo1bj5JN5JW;`HvDq`!xMD>-lNkc^xeN
zngL4F?$^BW2#yA5^z^U<YFZRj{}QCBVu3YS^G6+&9?;k)pcSIYrz;_$nnjeqIH<{?
zP3<9#jG|Xz8kQ7l4r>ac&<fZ5QH<6RjVb`*5t=zPO&--0DWK(;=1bb-MQUQ`d5Y3Z
zqjPSwW(K9$V>JGFe;iX{HUD|Tx8s^x`q0J+&1^c!#A!a944!z+V~QmwX!bq_`9#eI
z+NYn?EOdg2Q<{@1u$<P6QVD&Mrijjs$(rhE(2}D0>v@1w%`+4TOw+is;OH66YC2(_
z)x5j~%F;D|--Cc7LlaB!#7qtACUl?E1k=BdW@)z44UcS1BQ0P#ni3}Db2TfEKq60*
zPj|l0Ys%w+%-3|%99W?F{y%_1O(-3?iZrD-+D<9fybz6F`+`RG4s@1i4j%=wRO5!~
z$|)B$FHk*lnL`u*4kXGomrH=H(ELKfeMz%}qTQ96Ka<e9syR=&oGQ(~R6km+3786j
z8qFvrHLhuVzCvfNYgSWXVXdYs0sXDhETD?d8yaV4n7FCQqq{n{G;!rX-qzI7Uaekp
zREuH0qj9XJ-QhjWC$k~gsNqo(wMip*4ceMD)5kz-(RjZHzgsoie?sel=Hw^nOuJ^`
zcF1>VcGJCyE=}hHAiFh3DbmxUVQ4_>(`=@KnSRZyi_v<l@v+010nLLR_&caMy$Q4-
z%>u_fG@ocz_(S(o&EHg+G^`n*ZTE;~3Du;IYBV3ir!mdy3y>Js#87pXvo>}M?7C?E
z=wRWh<x@bxO&gvAq`S6Qh#$sNyNLpjd$jAWL2j@1b=t!CXqWcE3t#PG%6{(CKIYLW
z)=yhVg$DjwJB9W4YhR;sqX6yfYp@ikWzcCONIUH#I1{XWLj?H)+OxD}3(=0yqZ6v#
zx)ij7+QcVNdPqC98?7*H$|Cr5SX(v;7Q(g9+ywHdc8LrYj%nR#3XRli{-yY5jP^x}
zlf`OrX2E-){bwGCC$w*QLNHGI@f@_`wYFxo614xkjgd*z4qIXAq?Wq}eLAIOJOS;r
z_OpM`O49nM!IG@a{0Wv)v>A`VnW|k(b5WZ1xmRJ~jP@nkV4u|*6Dj|msa;JKiRZL$
z3DDmx?X$F}F3=81(6vJCc?uI0Y2V0#7sXoryFgyh$|=27qK&u-xl-+af5G5IZQSRO
zE7K;gfivaWAj)7>XqQigz$NXUN5FDfJK+z2E833(VW?6oUx5K~T-EYRp}R_3eHNfv
z+w?qmu4`x0d{e8POQ*Uz?XOosyP>^KtHVw0TzYnHX`i8>^=+;810d_QBNUpwqrDOV
z^Y^q)O#qErT@(hPN&7<tIGeS9(GIFbtD#@ARU1#03HKe^uPG_grrnc^<^wI`U9djX
zzCk<XPOYm19qrOKQHr8l+eR_$9_{)MAn-^VA_THm`^&#@txx;b9T@D_KK=!64{CQ)
zP-RH#MVZYf+PyTDJ=IoHb@H%weksh4XkBt3KB{#*a~^O^%RdC3aqT?HCc5f2w?fcO
zw}a+<cb%~VgW#$A)(x~hx^ePwukJFPS$uT2Cc#5rT@Afz`*aEo+}^L7aty5i-ER{h
z5U2~GRO|uWM>9bS(V4bFb*OF*eH$iBm*AjN&SBj*RAC;j3-p1(XkCRJ5;3};8=)pv
zmv|Aa<GMU|u$<6+k_La{bbW)+7O!J^z(j&>IaTQ=>IzGMJgJMKgYGHav|liyr*)ZM
zfh9@zHv=rmI$I)opQ7^^hWS+8GdF4dOVd?TY55u5cN8{0tD8iJmUNx{8yL*c`B%bx
zrfwzO#X6^3M|Htjy1M_MG+VcQDOx!?&F2uv)!F>ueV#6qz<FKxQV8Vh$|K=#p^kG3
zts>oaBub|g>yqAt7Z-G|ETa8qiLNUe+Ddgc$`4=E6}<>;WxDA1G3w>Iwu6wU(78~|
z?~-l{MW!z6no&76<%%woz7toed*TD#S9Ns?h*#-0J42vaH;@4@YIJY7!F;W5!b2eI
zbbb^jyP><c9~N%we#J#L$CP^Afflgd(e=B6^`4GNTkA&M=m5+&=?d?o)vWVdhE|Ji
zMl95{>gp&S|3K$MDf)KZC-u<Qp*u(sgf3kbh5Wm9t~(&tqnp1Iv`0Dvl`!?{UR?rO
zpROYj$N}BQry$@M)J^;ha7cHR;+Vs_O|*?2(VeCg)TnOvvvAm1Ka=|8q7Pz$=BnRu
z5svQGzc>d-551gj+I#A&C^^1IFRg)=y?W0$uz2a0P_%8o{`&K9CO|)%;y!`;7bu7u
zq|crVFM=I<Gd<P^^zYKXH$<QM6$Us|pHAhg2lZo=Ry(Bkq)0%R-uo>$b6B60fmXQw
zZ!b7=ME}xi$VKQEeF)l7eU%E%9MfA50z~S+x(U@$`q-18Me9B9!kHNTO)EgG{vZby
zj_VySHG+6TpSug%;`HkmfEcf@I|jQ6`jKu}O4Lt!5#xMP|M~N<bV`5WGLWbBIiEmx
zl0Kh;^vU}7=;~>Tp0x|KRQ(M4sCAm&kDksm`l;{2nX~$^4z$wsFIGTVhJH&3lx6B0
z97S;Boc^;TFrTHb$^$lAf3phmIr_oN(4DJK`WP&E`tg})o!1|ss=<8y9Se{J`UdJ+
zp}vCRCq?@Ien+cV-$%3M1^wCmXqD&>MZsXHelcZ6FY4!A2C_{59&H}V^?!05_|+=(
zPmjazOL`wlu3y#%P$c|{ek&DXRqE#-M5|hVjPflt`j%qozNTMBZ+e~n`Vk;+=$CN;
zZt9!v!|i(gPd~w#JNj@p$TjGvsDW(MtLH*llYY{lu-mNnxeI&u_1o@I{IgBJiP8}d
z^qP%O+ODq*2TzAS@)+bF>VKejyHj7f3@lyx^%Q37*7s62zDNHbg@hmJuP?z*(W_te
z4&?gv(&x~L$NCdAUkvEiNMLtRzlaU-A${*haOR2rhqVxRs%Iiq;FvP3*MA1$h+d%s
zc2plq1;u0fvj<>lTz_E=`s-{My8@bv;g3NeT@CAKS#UE1Tmo=6G}6Ifw;?15G!H}6
zPf+G*2%%%q9s~OswDuYnYT=BR;lXcE?QNJ}2c15K3<F$q_!@#<0o-ROlfgGX12YSP
z{sx8#tose8V}J}WG;KvI(C~B_ID-ss^MDLCY)gZh1BNS<ya_P~C=nKFxJE~&g9gnE
zupBZZegY4}44)Lj{9%KR3Jk&x5w&pih@tBRxEA3sT&B1AsA1x2*ga;*@d7c@Af?Z4
zL>X>T)nBw>9o^%LF|1`kcdS8E0dU+fNUohQ6w*8uXP8A{#dyO)TJ{qRDw;164ds6W
zoHXP%LG>v^IZYI&4Y!{KXOiJXs-I3aICv^Zq!|9&25qSZ*ICe=W{8>&htC*X4#SzV
zhW?kql5SW=+p7%2&PvE<8dg$iz&XPwRI;39;G_YWZ3tQgmK?*!lv&L+w0sZm^9<D#
z`8aPFri&K&hU`G-EHKDu7h7mp>xhJ4k)drR>=qk-e;%z12In0xUt;))BFm+Q*Oh2p
zG^A2;q0F$K&dKG5f;e=h!my9#qDzL$w47ZwY&ZnnR}6`t!BUmsk2oN!4d>UQRb#kI
zapG%+^;8Lb-S8&ua%v6lE}{HiouSMQ;tj*9H=*sOp_31ZTZWmGioI>v6p7x~8;YrF
z;*O#FH3&2qj^)9pyM{_F)Z8<KeFwXZ2DiD;(q!nfLcH0qfnvxlhS$DE?^_LbshaG*
zq4jUH+6>d2A@IQ9I*;zZw;LvGgozGA$vy}^G%Pv}OPz-IegaRIVGRpDbsJVw+Ox;N
zIS$T8hDIfjy@r`|k*?2hh8Em@gOR4Y$A$%TC3(Qma0D!ahWB3vZOGtE2Z|?#jC&A&
zYPdnQ<imzfvB7ps88L9^%H62pZD$PWnBhYeh~tL8Mxoo;_=gTi7vm@!U2`|CqMXWZ
z;~Wc+9>$B00X&UaUjw<v7!m=4dyOlo7SGGrz5)Jv8~>zmh>uZ|38b%aHvJU)j8lJt
zGC$)z`nJ5o-}o_wcJ~{(i-8R=enGXGfyOQh5d|5){SV_DY<!K%un!pjq;z<Qag>7m
zp~kHrqfZBoD>lHyA>*5q!5L;O$OQ7RaWmC=g&Ub{$Q>~@*&q;Ml+dNXqegc=Xvd7x
z*TCOMhjBZ}M;VJZ!MA9mQyW?_MxReWj5V%*7G4}Te%J~%Cyb+1cot`5w1G3;xO5$y
zNig1X1ufCoKo8qVW4Q%C`YEFeoq0|hV}FJ-NyekOU`aJjErWQPamnwnaK@P5kJeeE
zV=MWcZuE19iy6kKb5N6MjCvIk=ZtU8K`YDX69R47Ml~A}ImQBtW#t+l(^)CsxQH&K
z6&U}V0;PpU_h(@6f>GOtR*6xS1C~-_D?Re%#=oeXtHSu@_wewNv4?8nDvk3Ud!X&A
z@d1_nR2lu20o*jMatHF3F(eZPZyOc)&{l7Jts8=Oj1wvH(O~@WXXw6b%;dq*d&Vi0
z_h>Y3pj}~;aSB!WHyanxbk|~JQ>}8VaVJ$2-8X(#2bMPDXLQ5jf$`u&s()!WMqUQ7
z!`Qn6b{`twYl3{Iaf20I>oS&7*0$UDWEuo}jNX(OdSv{Ps=IoP3W|F58E4IhmVRSh
zD_9;IJ)QzNV0_;QErZ7D8{ix^&ZGx%#JJ}+SVoPp6v`Si))Z3x*|>3}3=+<!Km5>N
z7t?R$AiA1bj>0Do(=J+$JWX5ZGY5N2uJl&zHSMME?0A`mXrl2p9eoDoeN1<Mf}F4E
z3KvK}Q~b{W{w6tHzu#~Ax)48afa!D*v;>-rdWZ*^JaG1QObIq6#lq47Q$PuLLQJts
zKnyiK#{@WJ3KBzim?`x<JUnb_qtimTsj~?_9WmLdqW7pNnQq!2Gp(AAR-|b+MHiz@
zei`U*jA{ELfLPOiw6>ivy-LTxI8(YeMkd}=Kou*F1e4$pBoa;SJ!qabP5Kb6BvTPZ
zVUtb!X}_Lgx}pU#)pS@7mNZi!y((u+izy3v*0il3oav^}ezeY+hMu5@S*Fboz?p6O
zYXLZOOf&x<zA@D$0hwod>tE<RZ<@Rroyd2X2I$;cVA@D=^+MAf5r{=5?|yWq*u>>S
z;)3ZNTJK9tn|}ta)U>M=0vAmmv(dFOQ$O{h-1PP@(018$g%V3wOxI4qnMzX;)iqr;
zrR{`xm8p$RztyId6y&Qh?JWlKn#pn20*UJ;)_QnaYr0FD#5z-<7_2u;QMsVqGNnv_
zw%euzdUWeenf?HGOef|*O@k>U1uS<>J0GKU&$Q-O&>Btc?eM<I<R1hNn@xwbu+(C5
z8wIk}^dVJD-#1-JfLxoY-$5THd0_I}4{W>XHHt%anA+&R$3xQ>(V%sjBHl!+%TyB$
zpSn#q(*Sx+37r6arhknP=r=tR1M`EXftLV=OpDsli6^FAD*&FFGN}x7*z_trRwJfu
zJ0Ul2s-p$S*}QiPo&Q|SUp#{$bu(vg2G-sDI_)fWo0pL@9_C<rt~|{RBDD6H@6Z8x
zuh}pHHD2btzaZdkuBWxa$NU>@4t>pBx{l{>j;7$`esexmmIs(WGe9oTd~G_ALFN^d
z!VNa}xKsS)fVrLOl0(c(hcHl~=Bad5;-L92noJIvOTUBPVP>SF@B*0cQr&mBc_1E2
zkC?wP!HWp<&{VJ-HEZ67z%lc(VVH<C_p#BXDD%P<0LRTvS0H}Eyo&A=#+l!y9BRCI
zBVuQcDGBDeHTazp%?%W@IB8~Fg%_vHpD%{sX|rD_K$3Y?HdvC)v#&#UiaDeO+EUFQ
z(Xlnn{A@qK8S{0D&73vsDI=S1p86#^kzvM(3-h`8I%Va~nb%X*P?lLoyQ^$-#dUb$
z$T3IJ&LY>Gn*hN)v&#nn=gl4kFqm)7Gofn*=J)1-wa{#$lT4ABXTmran@i{@al!0K
z6)Pp?EZQ}cnzKHI!HZ_s_c1_a=G=aOa&so_peoGQ=#Ql?nfoeX;j(%5At<}zFsGCQ
zR+>j>V!diEr8%X_TthjPYV+$?AW>t^qxt5V`E|+-UN_IB=tQmg%PN36b0S6OZ<uG&
z+IZ94ITw!JGJDgja@+h9O*Hl9c@&<zW8U!)${NfQ>F|Bm%%>pVJ+q^ls+JnfL6jwH
zGB=I^+iKn(3c>qkpVvTZGh2l~J}`S5AlPnR`#xwLW^*+J9-5P>+OX3+aT{n|=1&^X
z(QfnFEwI#Mc5_FU9+@9m!P0BK^E^E4Gk>xY$bR!|N)Hd3T^#R%b;x{h0NS3Ir{0JA
zPt7lp`C+r~AE1qx&rs3DsCmf&I5TE0S_#f^^X!k{ld~m|er6ZTR0^)RTAoP-i<>1m
z1}%3>LKfsaEgp1@Xpf~O69RiJQPf>8%S<}mcw6?0ss6>sVw1s=uO*)rseKmLjcEB<
z(icOGzh#phKJB;kUj;3|(oEM}0xhm@K~0e54n-G(Eq5sbc)*hN4orkte*G0bg<4+d
z0qvmW_Hy+1kVQ=8Bw?2P7h&(PWi{;)!!4bQss8MUC1Vz}9kXmd4PvAvk*3lp3x~8t
zTbA9#$i`SIM=@TpmW9XQ#c_)>?Y>V~ex>&>&a!wRSmG`5Rj`y``H1d4C0fihiJY_)
z8o_zWBBUrml0}yTEy)%M9W7HVk=WchrleZ7QXNa0Wtax|jHT8C#Iu$)w*k^E8-9gP
z8J4J-P?Kqy*Z`l-S=yyAm}B|*MZC?qmZR-J=2@o4!tDafNB;s8TE^F65Q;2k?C5B*
z<>*sbxM0axf>w#8=>Pj7%fn+}aa^=??10~8mcmk4D!0680jRKKQ>^2XrDO%PUADB+
zLw?0#p`byf#VZ>ES1pB9%vxpnf<BQ}ZHf39x@#=@`Ji3149^Aax+NqE%4#i2x?5Cd
zS@kJsH!MSxtG;Q`)BV3&4ojF5I&<5S{}y!DTV_)_?vBNW3x^vlA)c^%*Rqyw5Ztpg
zP-v*pl0hHnZ?asVrM=m*I1r%4vUxAe-?u1rkZZGSq|n0y%fE{t*KRS>V%lNxpbMc7
zEzA3X?6hpU1!R}Sac3vo@3u_+7uX)lk+~3j1Q*fmUP}ZOa`jolsG_3Zl11RLrQHNC
z1}v>qj5=s>&xX<=%flDZrze(0bnbj=5#NQDVaw(x&^cmRNimL5%YtMW8nd`}L-n{N
z$_PiDt;Zb+z`9t~zF>8=eo9$&H|qtuM(=L@mUjKStw94AOAqVvPtj3Nt6Tt<J=Xqm
zDBWw#K7p2(wR<*LysaB3N$q1@MVnGz>%SDo*k|o20*jw@5<O4;)|r&2*>Cl40WH8<
zZ*stVpw*cYa6#6ua-cNWYNx2m0qX~pzzeZ%I}3?WYg`?4AGE3up!bKYv3Y2PS^ab1
z=wa)8S`EXkyb|>3h&6gM<RYwZdV=$))j`wMG3#pq@IKP|Y9v%gS^trPCE6O`pznXi
zSl3b|N32!U0oLQz-xA^52`fVirEykQ%DBf{7t?Q;U>$h~WTG{UR?3ssb-zIFly%82
zfYVkPU5rk$UJn3Bwk|u3-zUZTA!S`tt<Oz_!8B{-IJ%o|^{2Hw!}>i6&X9kwo=bu5
zb5=Wrma?qB3_&8>I*&>TbF3U1{9NlRPau(JEu(YId22hx1@f)>U^r7?eQp(6g;uW~
z$Q4=5w3#ioJ}w031?$qI5HGR5O;Mau>$yE>U9{R{kSnuxQOLqkZe6(<PE}a<r2<^C
z9;N{1W$P9tv|X_#&4Zds>$c^fUA6vY0;sZfQl`Gz8XOH;jWwPYl55r`Dt@?bJww%9
zwbs!F7_76_mV$P}T2AlnO>6RL^z)W=&MT0+ZOx8CtKMN<M{eA)zVHB`!TOU5F5b23
zDV=c78n1(=jn<2i@TtkVSq-JlR+~3kE!LG;U}?2>t%HgC)>Yx4wOJSbf2p#*l?s-2
z>yZMmbXb26gqDZa_zP%tTBlKNz03O7Cj745R>v3haJa|%)iez7BWn{CQ1@EdZ=ls@
zU3wa=erxIk=zeVVpj_&Jb?zY43|d!8(5E45`Ws+*VwF-p>?z9Y!7^+u8HV{0YX^mG
zN3Gjd!@`)g)f=4S)}RhJ<7`u;zzY}KzYYnsx!RKc1JTWPlH#`RHW6)OJ#Cu{z_Z8Z
zv=m^kEn5$Vy=?x+VZz&XPz(=!Y~z&B^0TGV9X)^B%$1<+w<S~UQjqO+8GH)1t^Wo(
z57>UV4P=Ndn(ldo+G;5YbI>+}Pxt>0*_O^lXTogjR>7IWwgn#mgxliAz<R`H_XbOZ
z&Es!$CepT@68=#(?_jV*+rF)Vi5T1Ssc6O8e#(F|$8BGj!4hw~NgLh-n>Y5hQxa_-
ze+AlU+q@AVlWgsDgh;l1<4WhhG~1kE$e*#fuY$I-HbE|U(rue*znx(-P`o$Oc6buJ
zIA`mP0W!-roC5i5+ffQ@<k(zJfR<|uri(3kws{*NP+*%uF|0ycUJVAX$oBI45Gb)_
zIRTW~e!2m0(e@f5!;UHCHa(rJD{OCu!tN#8a|4jSY!lvswkx&(ItEtS!f4vLYV-9+
ztI9TqPKwpGJ-=eqYHVw)Kwh&6X((%LpDOX&)!AO7ec%n7?pG+gY4e$m)-9WY>PT+e
z4vj#r-e&q9Eyo?(KMF`R*b>)b5boM;ya8;J&HN+GH{04DqK7TEicEOeYE#h@c;D7f
zl?iP&nG!7Rwo=+zbl5KBL;RsFc?0^}X&ZO}2D@w{R1no|QyhhBJ+?Q3FeHy`*%T@5
zwLMRdRiDH5OFg{lx6MdG^RaE_F7OQ4KBGv{psn&<w1#YxsDS0EZ6h6<hixA}120Bw
zAJS|&YRjW*W@EOOKLc{yHkSthXM4j}@X5uVOT~Mx_A0v1=4M|_g=6maMO4bS+ulZ7
zY7e_($v((?+7Hp;VUK;qN%YCv&Zp_a$NqFVeDbwNQJ~7-UO~Ic{r0{H*bT7nq7!+b
z{bQ=M39{!=_A=PM;2*R??JK5$<)GdBceD=KS5JrPFuQ#et{t{#oB}P}p0ETXbHu*f
z;SHV$`#~%09<{GO54*?gSE$A%(jIvOf>HKKY=CHc!CZ7E#(p>v^0D@2$|fGScTzp&
z3A;28v^aZT9+V~8FH`3Gq`jQZET`-pZUCq4Z~XzCN%r^V0VLb=#sJdnLvFPHJY&Ci
z3u?~Vm!5!AnRYK)2G801DMFlOuXz&&v+Z$I43}fyqlSrGdnGM7dG?ZzA%5Qe+b(F!
zw{tJUivs)Z<DeDVnJH)$*%!YK@nXAx@^BaI$7r%Gu}^*$v{L)<hgAQ0(Y`Se@@4jF
zHTqO;@28kUg}r+lbYHUHpu)h*cDWW3SL{`kLawwwM@0-*?G<z$s<J2FL#x{E<_y|(
zd%Y7lYwdrIqc3&#GZdG*VJ`{-@}_-NFgS17Up)>Bx9z{Ip!&0VdwU}U@7TAyKwE>o
znT4^qYj2?&VfXB>(C9VV-)(|mlf9}PJ~i9d$3a_*okx>Nt9|M^aNf5M-AAj<UUUVm
z2X=ci2Cv=z&<CKyzIg=QerW%3D#SbOODVF{W#5<uPDi)h<sEp_V;`rPvDYr21!AAw
zM%5|(_RC_(Keo>(0~oOXO$XIM``U>BL-z7D5O`v*p?7T9p6UWHVn0Otz)}0cHz6=)
z52t*~xLxu*EIIGsZUfR~$7dfy&TWUC<`Q?uj)#RH?%wg%w-EH$F+@Y-xg-2@X!F`}
zGXX8{9sgtLJHVp4p0~YsSzwp4u(#|k3ut0YV%MlijK&sCVvU+;EQuv1(Zn>js6@?D
zrB^G`R1iUtUZg96N|9niQHla0sHmu@DEhtg`+v{l<2dKcyff$QE$7V4xeoD$Xn@Xq
zBlH7xoe2O9(k<VHNeI^2n?o{0_rm~4hU!kx8KW@Whbn;W()|z&h26T3D8{iz=U5EM
zy}ASbkld$RO~t<Zb*5u<Y$ROwmX6LH(5=3VVMpkOQBWsRr@jhLqjZUj@ry+3HeLpa
z(d|0{{e!ycd*Ra|-8X*%^ssL0`%sV76;Q+_PIvYzpd8W7eE<*RbvI4{<*2T?2qZz*
zWedGTopCHI9K-+rL!03fx{goLnyfp$7uYE}mIs%rYt8_dru%*bMACI-kr-2!u3ZYy
zY+dvda5=iQmFPRE`*btR=jyC4z?nSVfdH7#*TvDwtw0wwAB}~&hxCvy(tS)8igokp
z<Bg|uN#&HyDAB!7WkY9lUsKq(RQKpKJT22*jYi{H-K8*yp3{xX205?WFdLIluB&$j
zsnlgswy8=Nc^#4$bUP`9RIPjZ8`Nubo9Vn%t?mp5kviR|ax`Al*-V1SCEbUVIJm4^
z_&5FkV^?%fk6;v6b-CRbMZGSC@(9;--B&S}*L4jP6Kc>swSxW)-2kexx~U7k1kgs^
zRJvH2bpKINTeGh7HOAYb`-sBDw{+8~Q0}(w-<`13s^jyZen(fE4UrCAMj#aK>h_PL
z`>#uv{V~{kI-EAaO`;2Mh4}|M1MM2Rb-z-g<)QBAS{Qt!Gu{UFW1UA8Kzno(zk|pV
z-6}dM_*6HZ0zS`l!EPYEx?%K=dZDv6hu%xwdU^}@={%*7e5E@=%bV9a`68&B-smpU
zK;P;(`kh?$uS#LwO&|XQ2I{Vl&Vi_>e%(Xpd+G0|L1d>sn%;Qc`Y%OT^3hl8!1?OG
zpbx0{=_7W7^Vd64xln+96kV%<`cpJPLHaa$Bn9gye+d$zkEE1ns7b$#?$|K>fT@t#
zrMIMdgWdW+>0sF&ePA5OUcEW3K@RBcAAv;Zx5a@(>bui02~qm%2Otuye>ofKG5X7t
zaX+X}n+wcCdY|LyJFJh@!C<UjR*oSZ(Pz<h5wE|u8<I!$CV2zgNYJM(g=nH)K{v@U
zeOMVfkL#D$V1!BfJ)?kjLciJy`pNoDxiFuqA51ZaH2s(ykaYc=5tzda{f$YG%+%-2
z1z47TayI(1^^g8VUygpsd2lE7#oj>4)mKn>El(e4qAIIGeeN8{6zTWWgB0u2T44T^
zUZe}^wEmxDD3<8^sTS{yK65MdOZ7j{1HDZD;Zi7^)#tB(-E;aRIuv+b|9CpMa{W3w
zwN;@%k_C}U{TZr>tJ2>+3(O1p?T^7#>t_!zVZ1f^Y+51I>H}#@U8jFRyPS*q*cRwt
z(odq(SC{o>3xIt^-%szctNIPJTd3FPQQh}7JrfF%>-zoA;aY?K&X;iXhW^wjVBXYc
zP=R`*el}gXE&3OG(RWL~ib_px>yHhk`p;JVjBa?*rk`X7yY2dY8!_HH`qg2W=MMd*
z84$gzA9V`)o%#$av*^+<p+)#Ty%}8|_x0{`KpyDlQf#MNzqtwIq5cgOA3f4fdLLkq
z^+S1(9(@^QWS{8WDfIVLKQoo`f6w%{?gF$|uNnx0&-It+z3@Umk9LeN^-Jj6U48m5
zXu<qSKQS8PeXV!D0g-<F;x*`dqt8u7<6C_{mF>71ygmSmn;}sJ1$RTi7)*(W;qiJj
zdK%_@0!c4}J#EK!8s4WstI5~!(Q=6T8ES^Xpub`L&u9%WXkUN}G=$ML8)TSY4-#ys
zv4z19!@x4QA8Po3sx86{dt$)tGW07j!rg{V*U-4f&_xGn_8N?KP}pbqX)2~`zae`W
z8p92L`hpxVSdN6D2$Ny{c1%>HVW>Aqlp%UPTB8lqZi9<4)KGTppdpO5uZIj36pK1+
z&|U%;YiLLGSQ=*tzlOOuVsN7xm3Turd2!Sb{5?p5;ahrUCmPcC0Of??^}pbf4PLb5
zN-=y-`;t_Hsqh>`(+q<?!3fh0QJ3IwhQaY2j49KglE6}yVL%7C977r9s!tl6JD`|r
zIPf#{@(g;q<MIt5y}&LojHM@Oq2aw5Fj!=WCxgX?FOGqnG90GZ%xS}oub^IHm_RR=
zGX`JN9dwo&K3|E>bB6D`(R$u6mP+%=4KtU)Zk6Fjx>qh3meNYK+MxUjGgD`{TLw!P
z4eZxYxMUa<0+g$UZz<SUZ`efUuNk-_P`GZG-2&2J=(&Oc-Y_hD4UuNUHadsUVwkR@
z_{%LrZym^O!=DseZ8hAZU!=_tJqVt*8w|stc*o#-7X~{FceaDvHT*mfK6M%%P-eBu
zP&^VM_Y6-9Fthg!oev@M!0?KSc)AU<17Yc*Vd%HOd}LTcpE7=IxJ%_tJ%+T)wEufz
zh@^w>PYp@m0qvRLTiPi18cJUP?YUtjRZG1vJfwB=OT!%{evv-I-fWOphG?o<cx`B;
zd#vAJL7B!khFaQ(y)_8S!MPe!C`aICw54fwH$ESNMi1j)s$KFlPROGB&)b-_4+edV
zPCvrDuknL5u<K|1nzA7N#>ta`7GQi}1rlgf(Od)>rS!dxU}KIY?1mT@XFxsF=rR|2
zVaAUo5ZPr6pqJuqqiPp0_ZYvYRmWaq<Vy7IGftsey8XtXlnXV58@JMi^MElp4{U^S
zk`XeI#v>F^k23C{&sanozorCUjIp1pgby0ER4;ePXhB(l!^RiqVItNzU@1tP@g8N&
zj~LHWIy>I@FP$hkYJ7+Ovyfv(CrXYVH}=!Ton%b0g2D-tahV_3WMe&D>nX+xO3S4g
zeRsfoy0P3DFd4>8wHQpM@mV&eJIlDf4R%i&*S-UiYg|V;_B`Y3dr-(X4(7oX7z5S=
zv(UJaGCD=ZkrY-hHV$CHoifhx11U9fM`5VUXwqK?d)DZC2WaPvHz_!C-Z-}f8s$bY
z0B99Pmg)v7jf=H#rpmag45PSUY}yQk8lw*#Q>is>A-y`IX*nFdXdF<1#!E)8aq#zw
zaU_+{Uo~nw!POfdxdZH)QT0BCd)+wCv=?lHalIupZWt$TfM}z!hc-J+#t=$*Hydj{
z0@q@kNq5yPWBU|Xx@|0vf)}mE-!H<acH@9}%<~;%86}oFjN7Qn<E}Ac5(d#}3}V1_
z8F3B?_lU8RmZ&d{?KFA)#;bY%yI74s=^*O9dGHWmdu=X!1P!0fA%DR||IMEC><-%e
z!7mUwxVfVRQ*wNBO9#+WH!q?9Rp#aiS0Hk7^K|--O8(|kw9_owTzUoGpWd8K11;P9
zhPDuun*;X%<;Ldt&FJgg{J~YqKRnrNH4>e#Hs5TAQyyDBr)$T1%a#Io8oZ^j3I@Zs
z*j9oZ+VZaw`iWac)5+$vEsM-yK7UI$Rfv~vc`_8{&u_Um9U`?`m{H)aZ0Y?CBEeg4
z4u*w@tyTvyL9tr{X9GHIYq*K-zwE8Yynt4;)zbi&^IM0~smt1}8MLEl*!q4T6x+6T
zP+k7rtv{&Y+T*Rd?J)6T>si_|z23TA0d;qmcUmz}KbHq|#|65S(vvjIWdW5e?{UeX
zvZ@G|&v!yS&gIPlNG7;E6k*7e<RVxgypZDJLyGAxQ+Go&%cY8*H`y+_yU@sSc~6VJ
zlP(Dq9w>C#Mce!$7st04;VG9yD(^V$(jSh#5|>*~LC(00{0jpuby3mC%3Q__0y*mv
z-$xVVBAbVimAee0|DK@I<kA%ijVhPbU!wJb%S;oTs&+{eVWP(6n@|k2&Lyf3UR-o>
z`v`rPT-+&+a@l3S9v)tG*<yvpdY6?HY`Es)V+nHI#g}5Tw_V=Q+pOJXBmx4+C&DiV
zi$6dxRf%x#3X_{d`QLh``cJrUooS$D)D7nBFlaS07o8!~%uE-+-C~Xm25>v`av&PJ
z8M{0T=s8nC?*v!2=Lv`}``RBUVXRXMCA0BI97Bnc!H?4L@ApP}W9&op^evY6|DaXo
z2glv<_e4__ZPq?pLf_n*G<OQnCl5B@@6Q(np?k`ol-8Wu{2PAEX_bosH~m}sT)>Pt
zIVSImPAUwa`3u!|&&pT_=r3P6Liej7ccA<ArdQCKjWY8A(mB81ht}Lf^^lymEeVq|
zU-23(3$!L$>V6Y84;>4S4#B7v{Y4vr#q%%Y?{Du_K<K;06kJ+THx8gnZRoM{eF;?{
zE?Y^@hvo4OXj$<c)lIBypg`yk%1)U4F_h}mSIwYM{p$I?XjxNs0akvhq^JM7gY*rQ
zpFbQ-Kld+&V08bwi3*F>j~R%6Z-}Pc*7kr@{O!fOPi3h)na)0_cr!ETlJsF(=(|6@
z3|j}ge#~{e%B23x#4q4c0P~pysDaGq=KvVWB%gp@3-ce<);?su-iXFW%xfA)A5&+d
z%IH_jcv`4=u_s1@>}1tcZSBogR$wxH*bVM5;mcN$tA1>9KVbaX>lCjGU?))_Y9RY_
zBPKtRb@(1$M6nNxK#sDZ^c+fHSI>c^MD{WdL&w;a>i~9~{hQ7_B(bYhw5B@2CgcJ;
znGHDwgDLFLSjeQZGg^V2#@2iV{dBgL63rQG(`(qxWYazbm(Aw8!kHZQX&6LKvbFC5
zEKBmqhZsb*B%11JawJQ)1M{S$-vS16B}04Am?sIRTK;^=9v8a)3nbN))hU!5GytYZ
zQgQ(%iY0$<0n8~${@-xzwB#n0XO~D`4#$|zNPhVh3Z;@}+5neH=EeZ~tYq3~h@6uc
zvw(eGGH)}ua!EHOS1KeKR25VyY5xMGO43LP+Y6GlFRbwVtCqZ^Ek=!Ga~V9Xl{C;Y
zq)zhBPq1`R(iMZgOOg)S0AH3=B*W4b$;ejNy($^B6ej8=c|U<%lSl^v`?@5t2?iS^
z))WW6AsK%Fk~bwuJQ^D%Q@@3UCdnMS|C%M?12J4vi=;3bmTpN(=pwu=nMx-CTO|V>
zLE0q8sPe8|GMcjHcO)(G5b2Nv+rr>o$vxW9bxJBe2WXe1E)ae9Bva^3c3)CtK;HvN
z;8)P=mh7UG=R?UZs#bX<`JGD5A4~3ij7jJ*NrqGP@)Jor<$a$@t{sBI&m@<rnyFXv
z(G>JOmz++A7cV6F$ASG)a&G{*KFOX+kXMpNLjdDy=C%WaaWgwki_TQDRdkvw&1~sr
zV5Xb376K*1Y$m<AGtH8zI4{fWG({A%%}n#&pf$&A=o#2OX{MmtwZ?2zKJ;tNRzHSf
zotgR~L@%11r)bzsvyVT(&>GFIU4mr0nPm;o?wBnb1BFgAVJMvGGJAI_^t`3-JO#9m
zbV)pX@|BLKEl~hc<Cxe$=^r6z43h3Jc|ku|+D%_Qijmf=f<~_N4Q+z*q{r`p<V)|-
z{aYaYjt;yOO2^TvuSh!mADAeXCd%N&Dd|U5aP748#v?SIk>36c9+paH(y@#(sedvo
zos|yx5$flpBOajdymaYXm@StsTtS<m3aK~6>zm9IY1qx?y+4DrnEMof+%k6`0sY(N
z7wF~FYW^!tcbj?4ODMFPYiH4~WqwEw(rZ4+9(`}km4xYP@mW38-7Hd?;Dx(I7iG5m
zEe7AmkOC}Z;b;uB81fm_-v(LK)3PnZBK3c{VT<J~#uR3uJ`b|nLZIi|9*cpr;n-_2
z`YAy7SuCc?$Owzabd){PqKu+xQ5KysAh8zDsV*kd;(OW`W?6K*fn-~Zw?bczg>Na%
zuf?n!n9sL(cQLI$3M_v63ceLuJevl;i!AKvTvM?{i6gjk7JFzdcHZK(7QaEc#m;b`
zRamT_gvLsXh91CNu#oJ8dbLIKQjEUdVzU}<U$Zz&%i8M}bGu--!6KVNr#CIOd<XSL
zix^rKH(9*D3Mi&#i_u4ceak{aG3whEU8!hov)Di-&FvOR^n~fKI9UjdyB1@wLZr*$
zIIZ~aTR6{w<O7R!LqNJMMtlG-+%3QT3EuCw{Llsl!!6&rg~kJxc_+X{Sbj*M@kq;6
z^t6n!9GVD}Xp?0OrA%Wir#^$|LCd!7kcqYY`x-#wEXPt6#u3Z!DHb1ZIa2{I5-clS
zK@u(RegT+cmh)bKJ8t>c5=bUlUR@59EKA)4c#&->Yyk90%hmLb%C$Uo8kl*OAJdhP
zZ#jZqm4%k38T0}!vfO<foyC?ewBbKxIg}o=r!61+i^emSwUml0wG?TERA%|J575q9
zE|`tJ^OnW*5G%Ko*n(78Mty_6DoaHvOkA+MLlMPl%Vh>|ot6Rnq26WL{lB^;OJCZ4
zJg^KkQ2@Ey(w9C}_t281SKVVv_8Js>EEnE@;!{f}dWb!<6e)uA#?p-5QEx3RuRz~b
z*26>6O?I;w&bZ4`D0b-~i+c|!o-*J4@X1SNNe|tfvNJL?ddu$9H{5+>8DlWO5Lu$h
z1es7-3>`GxC5!Hb%x>Ace}e3lz3&UfeKJ?t$fn5l(Y7g7wwm5}>9Qs7pf5wVkm{B)
zWwV08Wy$tXWFlMkH@(DjWa(5>aZ;B04D*{S>!V7tJXu~Z)bnLQ^!6{1^)%A?uR@uU
z4uuxUa%qQCEL-yr^iRo3tzq!AY!$8QOJuP{^i#;*j)pU(GB+x9D3g7?5ZGsBiP7jg
zC;OLTwdZBhmFO#%9oY=Y3YisMkCn1j-+)xf%ylqdEz`C^q(=6e4c&jWGA0e4*2#XL
zy6}s#Xahtq$+m@{@v_Y89f)3$y`@Xws%&}($TgY29+KB(=V_1JAj{&x-H<s90J$kE
zN`SwOvYX>zzDc(1JGj;?n?qMZi|q7eh}@E;d!g~R%+nu@rdC<C2ERp{Y|d(scG;oF
zFnC9{k;c>^d#4gIcV%N(fOg6zQT;=x{9Q|kgvp~OL*anj{w_cx<ZItxXp!<j+M-9v
zk6NNHM*jCqNFJ1bbQ;bamTxqI#LBliqAyOqgG%*|nB>EP(0Ww9{#U>x$Qg>lCCcC3
z1aeG%dp$st<lhcQU$UGv04+s6g3j0G$@yn+EnoiCEcjF?|8^`ui{vMF0Q9VU{e588
z$Sr9hRV)9JHtcnBtFxHAi}Ls1LEj~L37w0$EH}L<1lkpOX(q;dRX)2CGWGJ}MA*G1
zZ=ikUZTWJFd$-DeqXl4_d=k}Hx68Hv!QdTv1-%bC<SQw@c~^d_8E$vVPaOjGJ^9A<
zXuL09N^747^7lT4p>DZ*IG`WOo9PtGBYC@NHw-?O$Nq`V9{ITMfc-@NjE>?xmH&1S
z*w5sD&^!IP{0-$gU&yVZp#M_tOUuDN`CW=(zLK~82J%{dpGs}}<*B>Dy^){!58PY%
zcXZ6i)vASuYi?GZ<3Zf59@DPF!>Z(Oia&c=1<GO2%gV156SdPSpH^_*R&FQZzMoY%
z{jmO4C7+`)z-lZlY=W$&dw>hJ+Gh{fLageN(HLs=aULv%S*6q6w99JUN^rZacu%ND
zSyfQjA=+vLLcY=%tKc+{gI4>tQ~dd`)tDDxW38?ag)?zhU(w-`TUHk-EcD#UhQipc
z)`njI<7Vv^3xn>~UnG<J)>~de#MAmYr4YQVU4Dd~uXPFS#{8^5Sq~5WtuL$xW`Omm
zjZg@(enp|zVCx)8(S}+_S`Wbe7iK*n7BYLSPtqB$eb!-1(7E3_%?0j<Tl>;uE5iC~
zs)LQR&RGX8%G!dWc+uATzk$L*>#LOZI%IA49`p`d$4!BySnEhiOCGVF`8^urt#9pv
z$WiMoN`NL<&zcF6ZheOy)}{>WmsCfaY3)h@{w(Xw^m5C#UP7fTIo3CRhUiJ_0xB5J
zv))d3dcL*AL^xAqy<;}?PFXkqj>gm0&uD~o){FXK_oDTxVK8{fI_@v@UAA7>3hs(^
zsSm)eS|1{x>aCa2Q>Vpb{SvEi=`HJfZ_#<%dM%}8TCGP?&3C)C@DB#sX??5%q|18J
zYe?R+t|@`}`_|*Ae(9k#M**`()(fa;^Rad4`}mo9tltj7SbD7^)`L8^{#pge7uH)R
z0Oh51Y9$=)v;M0JhF)2l3Prf_+S-NcO8c#!(8eOrW+Uaaf^613f_|{g-M1hiHrtn?
zG1TTuI%pbZv+Nx7cG+a!g!$bzqv@{LWAiQt?7cRtr(i7mY(|zsZ@&#sS4p_dSPO_8
zu(_E75@9oXJ|rV;9+-UKTeMB)J&4BG6tW-(ZA5z79<mwv9$Y+ZGw>`#V{MK!VT5ru
zcF#fLZA#lP2}f<F(LIu2b2|tqi8gPkX6?9*axDg$WV4kPL?>*z==qjxvtbEHijC3-
zV5v6cAA?J?=^aP+U%HLgY$#^f82e#2(`Gys183XBWP|wFa&;iSwt=f5>1XRe<z8X7
zZ9%Ymz}9;r4aWBCKhYRz+ZqJyC|mQdp%7#H>@XZXXuE@wSch!?YlVfwwk4G0kF}ka
z1M_jV?e9|k!wK8Vx8Z4)t&0~(w(Xl(Xyn*V7a)4l_SflvskHr=!kksM-irWp!M2zJ
z30G`g>D_qMwuHWZQg1t!;wIN@eQD`+-S*KCh&0%KNtHV{Y_Dgc@uuxpPl4HJYZwX(
zO|~7kss5<hcJ3m0(_)+C1<_l!Yu3R1+qUc`kT%<uBLLHGJB?ERcWi^N0;a>(o1)-%
zZI`D&p~rSn5iWrzwjR&X_tf^@E;#zkcB2w~y|yP7fqQN{))|9%VY^^IL|)ov4nkv}
z?S}=>Grh7sG#{<6Z3k1xq2IRJ6~4W(oj})|t0Kk`if)QNI?d^>m`^WN4~3qpA3YU{
z73lL))Y7StoeCicoVTLT7m_}TCmN{xDkKk};HS{jsXKo~;Y!SJfMRhq%m*rtQ@vu4
zN#RGCkYGjgL9~V_QfNv;6~ifS9Hxjkg2r8n2kDr$J&LwJ(6?9dw+F~RML1P`?N=0b
zgM=%#Qx4#O;?RBQMJOKG!(gQ1jur-^6zNpd9<3O$20k5B47>;KkYdQ+P&lkG?WfR8
ztm0ET1sbRD_!*r?6dPwkF<vpc1>~qAKL;if6*HG&Fvk?qk05efabyuDAxUw8awR7e
zR}z4dtl0IxH?$%R8w+WwLKg?jG{u87h@>m}XoH)fP||iPQxV*SA!RGRGD!iNqbQ-%
z$tM+Rs+G-E@Kmdwr<nB_%;zf>xPmKCT&AaOp`!01oH?sVeFn61inVLu#d$?Q9p<TA
zF{>Er7ZtN2A#zDE?jc5aSuux>s9aGboCnxdMFeH7>lKZc;o&vK0&~jpUsvou2aN_r
z=P97wP}ou_^i73=wwR5IYT73>DH3WS*{l%#fYzeuKMI9gip@(P(yFlBipDlY>JAL8
zU9naH>^q9B5m4w*RDKANyNWOA<<hD6?*Jsb6s{D6x~CZJK<A(DE4mf{?SbOGiD>Os
zG|&f<9x6s3gvKMqyHp(XL~(Bh(4H#Zt47~5MKC=RdKHd0L7pp={t$Vgh@}<dOGU|U
z475+-kp~4gyJSx^y4&T_p(78w&#BPD({9@~3~8rbEY=>#|JcRS=Rkby0%pRXuiZRa
zHu%{&c*2suoj<+W1MIRsLt~&_$98Z*cH_>#Zm^v!5SBvhLNh@^?E;p<QiA<|LotYB
z_Q&jjnPfk?7JA9{<{!bCRD16|u#j$FLA9ot_UmcGXUewk9}7!)_GTYK^s4>yYtX-K
zFQ;<$R{OJM;M(l{Hh^olkN+F`ckEY;hrtf}JM?yWY|qnvs>i-yE+l*Hr%|%vg}pbW
ze_z^TnlTslf2c4)uk2qvgBP#uzokG#zrAG^8sC`gKUxL5Z|y%y2b!z$54xV+l=Epp
z<*qzVB^DmaeaoQ{pnN|Q*n!I01%QcAcBP{+Qdu93!9*+T=?NaARMUTlaZp*m0Nf#^
z{pXO3RqmKilb|fP1%(u4+A-M8Rpw-a<S9*K>9d#l$`!L9Q>OH4h268t!aa0#D?6#K
z`@C`xEj-JW7rzFnP|it%Vx=;s4tiC}|L8Zkpv>`tYt_mdTR>`*$r4OSt#TSIc<YpL
z6wtk)>|G8=Zz^|CNU2eIYdZ`zDHBYGpwX=S=m6LjWpgLIxTS2O5}4acxd76tT>b`%
zZAwQwaP3OtV{mtro2a_HL-}MJ)bA>LWoYbFPNdUsUCQKcNZwPPnFG7`mCF`F<bg7m
ziUhiqVN@{jQ0eg@8XqYiMA7^2v9g5{gFVWzFX7u0<<Q6Ao+>x31I#n!UV5AMDixdI
z;dAAhhY)$8>~BNgOJxVuZuTk9QULOm@(cySUn`GtXzW-1ZK5BPbEUw$8~3jqDDK>8
z8ALp|D$0y`a;L7){kMnPcMaHkx$l1g_I@s&3TVT*y>yNwl8YFG36A0h&>J(F+qnw<
z#&Dw|;r>BxExnTuao^GE?l5O8pkJFyrT|DBHzFC_5w3hD<|&@@m<aWwoNW^9CUA-O
z(U{2ng%mpe|8K6e3G8t$j0zZ%xM%OdnG;;@L6}J9x^}@t3ddIiEtUI~!d+>cMgUAY
zH;cyzGdRu@TqgIgJ5aK?)!$*D+1zE?_U3Svw2VB-Z9NIeTyDTLH0E*Jv%uwZpHNww
zserqa3loLh3p!O<#CeB9qnJDQ2%x99?w`?jnrj^hyCs|}MdHqIThBnhl#|m7tc;sY
z;h(ddKb`S9$IYVK@I3cd14PQXt(3>C;2zVbJ}S9$vEZt>4q9Yg;QHF3P;KI#P?cN_
z=M#ou*K*V8<yOZXbb{zb?&)cWUgGA_t$LZ;^#taxaG#Rht6ZiNK<l~7Hh{UtRr^8x
zI(P0rkOnR{19NeM%SpuuZ*p0bQfTBlk3zDEi=|SqX712+46ubWh0uoP7I$+fKyP#X
z>%p~hA5&zjjob1WTx;iSDROd$n@$I1I=Dl$gSyL&YlcE6ci=e;c5%M+g`j(!jDkq_
zxv9l)^Z|F9HvQck*N!1Q<Vv5wnMYg*#S9*E$LKfc;oh1kdG~}XRDpfU&7u^~GtQho
z@6^k!_JA|bIiDtgzTp0$(<m>w$bBGv+(mlTz2c_2L-IBE-BPIcb57Nee8WvSf$_fO
z7H2@+mG?*0r__x%Qe51f-$rF(9{i`2u<+!K8>#-mi!W=2!#jB{5}Y@G_+$9w!*^c;
zs4t(~0H6GLbJ`gA^L^(*0{E6LSPJC5r~)8}ci0P&V18~i`a<}jS7APsw-kU9#%~CQ
zhr9Svd-%JXAN~y79zORE^zG$Gl~MiQK0c3PmHYYUF(Bc5dkjDi@F5W}5yAgK>7_{i
zw+-+xiocu*#c2MAB#6ZDr@x1#gM3Ld26KqFpkp_O`5+HC6U(oo6<8d<H3}j}_!-B5
z63_Si2EC*FxIG{VykjiY|0VJZs66f%e`+aYj`No)K$3WWn%NWl#t-2|GT-tkKvQ@d
zx{y=(cl2mX<3&3EmCh?^^_;=qpM?=-@=pJ|4f#xZ<z(~nu|Ub;xnoc`$zP%vWiIbV
zB_VlySuQwJK0o;!*aH5X57<IJbtN>4_``pJE9R#dK~C{L28f*I$NdUNOZY!#VxG?M
zxoa`BQa(qDVVCh{FTtJV%Y&eBj(;8rh4XyfXpnNgltP9TyyXudl{}Y)sjT8%=?uXI
z6aP91pw;}!0KnAnVm3xm%Wup9SI2Ls`~D(-VKqQ6@z!6$waa{;74)z0|8Vf)DsQ_J
zq@Le%9%$G25gs7d`7f`-QUgDMzL9!^|H1;8H~Ci|qOp;0re{$Tzab2b&Ah4Q3TO*I
z-w~a+`0$0`Zu6&>0j8C|mjL}XzK22&?R+w=`tR_ADDc_ACr87zyL@#8`Z{_3Q|NW^
zPhX?)9v}S_VE6e~v<H8{4`QI#&0l>C@{rG>Q2!%7KNQ#MW4^|;9z*Nl!zqCIg!iHq
z!c+cf3Sge`we29i{7ovZea;Ua35^&0T-r~)<Y&-z)yFI7ned9=F$0pX`Q01P*w1&2
zg4=KSPa{Fz^50ZL&sF%#7AS5)o(OyH!f*<RdkBA))BDd;xFAB*OSnx*k)49?NpyM(
zjkJpP5t<$V+gCVGm$jcThSG@sLaq&l9Uy$L5Mv4yKK&XfLBb{_%m)i6TA&aj<kCtt
zR5+jjW|$EA5fpX_LD>-5EodlVu}9c=h0cHN6|SxT=ssb(1q|*NuE)btxN!C+6b}f4
z8(<<ru%%shq)>DKeNn<&3XYr*2GK_el7+e-pqC<8(7Gs9XrY*Uny`#wI_W|w<!&<s
z7us%T3TtSMm?b#SYBF1>*+%zYj&Q9CzMT{nxI!jZuug>CJVCYr7hArts0pA2!sJRQ
z77Ca8Ftj3JHANSTg|S0m>6Boz6AGt=-r)c(5ge$h{frQN3|y%&z5!gB5c&jQXNATX
z_<K&sqTS7Tp^l#QrgFi8DupYAO`~9<Qb>FQv?^iD_fWhb82$lFweTz505!sMx<_h-
zf22^T6Pz}~wTptsF*IHhD&9ijvJmADOIL(S`bDk^*5@EuFI3Vl@|xgIaqa8E6<TRF
z2uWwqc*7)2EyJ*H3Ii#U-Y9fThNUK9oEoCd!tYB!T7+;awz(z94#321VLn|RtwMnw
zuC)m)U7hX1<arReBRH)E*CA+cV`z7UhwA{=DJbYc(<QL&XuKz6Swr%^aOxe{dmxym
z)4}I%p&}oh4~74#KpqLNhGR^Rg=Q+1?-9PE*!dITr=zg@R2X&~+%w@uEx2Cc<!X5U
zTv*c!v=_pM<6!=!Fkvt-`-B-(v;9i=oR0Fm7QP(=k$&OxDv&oq+awrzD;P|%7=^1C
zvJOLY6FaNHxr=4As`L<N?}Q~!F`ib1USe(vxSir$x?#OVC))e_h^17y>MI6QQqWKQ
zl7qUxSa2TL0pfnTfCI&i^dZt9(T?8t!Qww;H$*&{4X{wLS7w4nn3zew%r3Ep(jU9U
zcpEhC5qtK-r@dlz4Y++`j1##1;-C!>2^V{&VH5{Mvw0YOg!r`<9!83P(i0|1v?_$b
zXmOhhL}J7qiohQf=TdaykoYl`S05I4C&S-ZF(lXw_g|d&Jq3Y}h+b4i7%vJG<2)+9
zPak$k5T~z)exi7ac2LK}j%bkM;)_B^CW&bYkUSyQrT{Hj>=VJIh-+WKM5;J=HPq9@
zvGi6-7u&vpLWVeL5JWP?)pR>#iPKOVi~1vR@aLG)95L_~T2G284N%M#7w>{-o;ZL)
z_xWNJEldi;#A`5LC=PoF&>}IQ1`5SuBkgxjiORX?J1zb<0_r7V6n%H=j5r|<T&Y+)
z3X)~wLlqj&ieJnF<~h+b6eBa87dr{NT%2$cFcspcZpc)M?j7i?5*N@5=z_SAQr^|#
zyy5VvM*Qm*Bx}Vl>0w_dy2^oeQLOzM<}ZoWYe6oH*EgZ@ia2Nn9K9-9(fXoZY_|i-
zHL-$znCoJD6y~YHB+jBO!3{CwGl<?4H~B%oQCvVX+a%UcgNbJGk~I`t#GxO+r(5E}
zr||H$C}%)g#g^R|TASF`1C(}gChc<Wi2jGr*CDElVB)U$n8LoD;)VktUE(uKDBKh8
zJch`9(eyKIB_4=HwJ_f;G8968C^o(X_egws5Zq&N5<Opg#8_H`JQ3&92K%YlOsD3a
ziAl7w=oOV`;r4TJ&|PpZ#Pj>Xy%bMc!TUaOJ{_@qC4NVHp4Z}%DG=!ww|ohaH{w21
zCI<Rev|I}rSCw9bi*BmTl+AZn1&jpep&C!86FpVQbKui%)ehRP?omZwLf>B1rWxql
zr!vlj!hY3{tI-#(s!)Q9P(6)+LZqr93nEdf%e421R)vg)`50A3C(IvIS(;2>52^eo
zK;y7#D}6d6R^?-Y-*Kwx1bReug`%+Ws^t`7J*s**2_!*fpx|?&YGN)Fj;RjO!sNKh
z))7BblFExhcPCV-v?NGYDLv7cs=BiQ3Tdj}wt=Lp;`)J^p^A2<{6nV7&<}%Is(lo&
z%~m~m37>LQhlgUmPO7TMLo`>FM)8+C)#^{tn6G;84zLSUJEy^Jp=yR3`ifK&zCd5G
zs+@|=PN^PHs^GM$m5S?1RBqIGM)i<Rc9*I?8w3kwssfzjH%ZT`%m>5#IaN?EES*>N
z1pua8<w(KU3Ki3X!Bnb-e-2Wm>I(tr1(pANn6FlSMxognl?QE2YgKg#Aa$y-r_gv&
zwP**_FR7-|(X`8|fyY6vs4D3w>s8g@r?6138bYO`rfaH&6l1xrT1q?f231@i$PHBx
zB?WJ){$2{78dd53n8YU4&xZlptm>ol7%i$#P6G6n>f5j2(`{7`m7KS#(rLHfrkb_~
z&a|uM(?0BuD*ZkbI#j*q(0EsM5>Xjxr|PE?fOVNvM+d>uJypq{XuYp;S_ASxweB&{
zx>Z)R8+@o*pn?7))uBNkk5$#d@UTZUj5c>qRAt{`@}8=AKTOaw)wNuJ^{U(!Lh`w)
zWC%Qbq1rVNc3-OgraFT@6&nQ1SE|q6hsbM{X~B4)^{d+G+~*tBQ2IX1Th%bSJYChf
z$#Bt4y=*EtclB4aDD_Y$3<2k<HikmaOFg9t=69-pq^fjpbsxFrqrOZP9KPy2N=y5x
zYb}B4uYT_-)C1ICw4pIjT^@+WAhlqkmwB-I1wH&i)HQVAB~%?ramX<Blg*IXrG8B>
z^WExSC>^jzT}zcGd(|t*!+q*vigE5&Kc{NzaJA0_s2@=KU&I_ns4or$N~C(t1du58
z^05GmR{ySqy%_a|XHYn(Hr%B3=OOj=!GJle-f$I)vFeVS;NsLKTZkS}5A=umc=Z|z
zWE@o=T#dd2_1cfnn5aI!9iYe5&#q#;$JL1xyh>7g&|db0dhEaOH(5R10tzYWb+ZAT
zs{ZaDh@`2#oiVZL>Y1;o{wza%a2q-^)q(WX%TlNP2>opJA8N?tsE50w@ua$s4n*Xt
ze+)olp4#6J2J_X+=yY&_y7dm6DO9I;!eEhlIMs0#tJj=C<0<vcEHs{0KT3xeCF;XT
z04q~RR)9OJ{&emD+<)iQ`{+w*<?3NS!M6(as5&TCs$J<LjaBONqtJIj{V!dX)#^%G
z`PHan9ne^-K1zkCb!t1h)-S4^Y@v5ay>>syW%V(Nkz7%4`4$RS)f$SC)T@h(K)I%V
z#~j>s_0EeJlBq#GaxVsRLp^5!S{v1GenV@MI?)D-&FW4{wYR8?mxA0<yHf$>ZFO`!
zU|Q7<w=s$~^-d}aZ&%yXgYk~KI~vY(sO#*&-BmB@g=DAt1?82x)IUsx`aSjiP2ldU
zgR(&$nAFF9hiJFDiPqE))jz619;u(uroTsh|9ANGM17bRfKS!CSu{RVdrX32ue$I9
zSbDBrcOU+~P+y>8f|u$wv_0ul{}2Z5mAWJs=3lGFQsA>+y?zPw-l+Xwq4BMHqa6&n
zYD|qQ(CVhSN~;HVO<q5UhsJdiIz2Tj?*iLPGo=i_+D^@;#W3it8FLjPKAIu47WdW6
zngxS?n!qDy^w%8d!dwJs{-Doz1Zrjtf<lmH)jjkDYm6<J<`B(=a_EI>N-Y2#rWs?R
zb;d4@`4qUgTQiK7v3oQNDaW^0V|0YfK27O&FtK0L+6*pS;~fl<1DX>0Zyq8v%X*+5
zsi~ujElM--YnX`EDE<VA(X62z!9mSy+9@8=44((?ux8zKn2*&YEC3g$sl7w>pGP#4
zoq-*%*+pf;M>Stk!G3}!g+7&>sF^tt+%e7cOCZNJ!)f!Kq?xu0<b>v!14yza(E@!b
znz?iZrfQZ&03}TmPsNJq8b3PSl%ZL(0v0kgyFUh(r5R9x3Ch+)+@SL(IT~lWNlt2#
zt>ILz#(yv7D^D}&2u7H%8J`F20?lbU`%tL4_%UFLG!9f|T&y`9gvL{vX|#qvt??}f
zc8R8gzDaUMbAw_@r5bevNSWrJ9Q2*lNR1%pG(FW2Ij>3CL;1gQO=A-5R%o_G!;4Cd
z?lR0*X>xu9cR{1{!30%nek_Bf8clr(6l*mz-i1P)MtTUYUDS-Hddf?hxhe4XvPMT!
zc}25`LNr%3DBs16rwOGG)Lzrfq^jxb8m%R`22B-ZPfRy7_Fu!qO<Z0OZPZLuVQ5X7
zA84)EteG?lqAePRe%M=@Hxto#TO+(dW2@%hFW_jKrtw{vZ`VAfk2gHl%r1gYJ(>@X
zL*a>LJmrU;YHB<|o@qK(L7`V8rL#`YHH&G%`NE{BErtF|&5PS$`!s29(fLaAh$=o`
zYks1FoqkOc?aJP0>Wcw$!a=WuWU|BObRnlY$iISmx`X9A=*w`JdmLV5I$W&8(6Ss<
ziD=Ar_>?w&CmqCWxSi+l_7u2$hZ<Li6grrAFQ64U?4S&1v4cj7&QlH}s8av5!*}jL
zD{*M$z@2dzn-5az@C{W4l{tL(HT2IpJf`Kwd577BaHibh-9ZqkbhxnqdQ}d27a@7U
z;n>G$tag}0MH4j+e^3Oy)`6jjNu9%a6V=9Dba+aU)=Li0SHk>d2L*jR@QTCP25?s$
z)>Bbwy@QStCf6L2GSPV5;d|P#H8{LJ2NO3OifCqUI-K>xAQ~P1HbSz=A&u7Q%?_!X
z(AeTIbQpYUci0{dNAEg_v|R6WxG2(6v&+Ha2F%}c_>DsT_Z^IMt37aVR)cgqv_?SV
zp+nOuNIrH5nGCcZ2hRxTKXG_759FysssQz84qI~}((CZ4HS9ijh<g{3FC5gK@bIO>
zzi-gk=a5$hFJ3t`QBlilhqx-rKlD2!Qh~%9hp*m)%v%TZnSgQC?&<|`(|$JseeT*_
zbj;R6dzRuTp4tF<je2R_UP5H2cB=<Ky|o9axY|cMGZ~V;+OlC7i=Q^)DhA=NO^Zik
zfc6JUt_5n>&{``<`v*d3CTXyC0DTT5M9aGZG)%jjsw8)56MlxqZtWM8YS^Py8)0Iv
zwz3mH-ac(~2t@X4hf$~`T)XK3EFI7er&7KM?WY>_MQZ#0hF+9bMxnoG?Kk6LAx8W6
z1V|p#D(IDdNPBW1IMZS6*hj#Q)ApXid>zrw{~6<r*IH2m@2GYFMKBVyEfkJCrakur
zib>jJdVHMF4y8O#iZ=OIkW}sF9S}*=F06#zbnQ?A%g|1wt$3z3`z|bGYZp`WC`WtC
z6@4eQ<#eOxnzVBd!i_xbHaCFgYd3^pOa<Csz64C6_CEb0McP%9p<k?3ccJl=w#^YD
zr?o8<ohZ@1w;pI`w40AWvQ*m^kH#`>;RhJRS?v|NF3xEqsbJ>3)`1pF<=Xocc&XHW
zsenS2)^v?BZx^&0OZZl;b(sRLM$1z0x>h@wD#z-yTiejsr#*27mb@KJ6sz}jd`K})
zKS#$P^zCy@rrp8;N85V<jdHw9vFn45@4OH7SjVcxkW6qKL9>?V7}f^KV~#r7-5hru
zX0n8(B*&@yAalZT)O>i6?5LpkZi?fQpJ`?tgQ#vb&2c@gX44(>=)Z2taAYXalIdum
zQnM^a{ZxSFIKHNX?I#`U>493}IGeUUXB<T;@Tqa!M|EJejz4rmvd-}tl|^239J`h-
znoEwO^zi1gW8E4I?TX`63iMuebnXC5z2o9c=wEZ(_ZJkeJEot3GYyV*1argjeLX;L
zI<A`vg+|AsKA<!?u1-K>v*Vl*&}(u0VJ&>R<+!vQeYYK_KZ5sdj<pVeZg+gQXaMd%
z52qdmGM-N9p99p(=}#9Z?sQ7@2WX_zlvPlSa@tr7F4`%c*77k<T@*As==8;G^c`}#
zFd3k+POW`Vk8^6E_ei|cCl`Q{;&fI6e^Z@`dokWLryX=WFx_cXAk;IQ&fpzml4d&n
zb`@-v(;`~=WjoD^gNb6Nm6Xjt<<z?ieW#s5M}ky3{a6CDDyP_`AQzlsZ$PBl>E0_0
zrq(I4fu_{y=s-wbati(s&NMmAI|>h*os{&Qq82B6${*Zvn&ARNtxlSiKryvBO_PB>
zbvjGQ^<JmEWe|PtbhQU#df}Aghu`O=(<yp9zjFG6uJzYWOT*FE@AM&6HoS3a`VZ=^
z&Vlqqb#pH0fTX+gr_14mhw}wL^m#fD{uRW_IpYpSzth>5a_c_MMYJ&SH8~$>0QGa`
zcVaO9&W&T?cYyQneSisc?xI7+LCzmjP9)g*FfHpsoh5XSg*n&Ppl_FRE`9rDxAXdT
z=<RX7LZ_YfI){D?$$ieXgD~Fx&I%p+4md~9cQhiLC(@@JqMQx!=!<qX-I@=Wc;^$|
z=sfED?Pgd?bWWuU;+V5PJ+G3SOQ_-{*?9u(j8mK|>LHTqe27*LY0h!$VKCkKES2YH
zI3K5{K&JD#bMP?Bc?p#QW;>6jW5GGjE4Kjbq;uTgn1o#C!S-m(cb;sjgWXc+*>ua4
zIp1l4{#oa*KY;t^oY&B^`@Hi*I<8Xge2-RH70&Z%tyksTy#_EBoVO>VuiE+URrFnT
zR#Jsdy>pWs>dns8RL{}k>`A58x16h1!|mJ7zdpiTv^ob-xVX)^qle-z?apQk(R#<Z
z(hK?>&bb-Tzw10?6!bftUDu+q%X!9pkbBPa?m_at^OWuIB4l9ya~8wEpAXLaz{-aW
zbRQ3UNO5Wp<`cR*Jek{c8p?~w|KCQLiKGHsZ)TYXM0}V#2TV}*Wm4&#<HxkokKoT-
zTVXc9Jc1cdOZzOwiz>*nnHdxV$YCZ>g6JgUPZv!t(?gY;d5i;<Zsjv0eIZi7oS@S5
zLgptG^op3*zrx{SW-vY8PcawEp>UdU`~)H;OvxU~f1F{Sl%unhv7szmCDZiFfC1(m
z%m#W~d$Mtlq3^|Re-8$Cvffq@@n)N1py0y}q<ULl_SZi#QGRSxCkE=zJ_$x+0DEXU
z6av}rY9SfKT5f_~FuTebLkeNf&^t1e-I74}e;AvO5R-WfTTz8!UuMTN$_AM4lvL1s
z`$+7t|1=MkBrOB>UP;zSxE~?;X#@<WN&?#@uz^1lJ*)8dq_S=p`FwUPM5j!kHT5*N
zGZ^QRyOfh(*~#GV^_R*ZxjBfgMHin>>HY7++^2GXe<qBMYUMCYJtnh+k$?FAe_Fna
z*1&HhlCiM;Rubh5zg*2KPS8lq0)_)L)GW*o+#!qKlA(IoqKdK>u@;;!@Zu~6{RZ_G
zg`pK99SVoXu-~n4{vLhL6c%kJh`v^2ECcId_swXy>t|O$C265{_H^)Vzg@{za4~jm
z|3Wg}?whrMIcn$pDZEIqOW6p$M7t3&=sRXNj+VQ}?RIU%(39*|P#pV&-32PROtzaB
z2$Ev=^ASu=rrjqdNaow^I86EH61!_Z0Il5aC<O;=?JAZ*|GM2W0WuACpXCAOhTZaZ
za5wGNkA?Y0yH$UHblZh4gyciJtOjt8?B-CU@v&XY0dPHbQaZ=-#IE9N4C1NXr?X)9
znVsqbDD>J@!~^WP-Fq0BN&3?6YAVe4*&U{e@>h1vRN400Zt71MQ@`B_`nb~@JGm4v
zZ|!b<1Z-FP6|}r}vu~w5zq@_uesJFQGv@-u$6ie_K3{vaFZBHE=h(rLzkRS2T&VrO
zR9F*cKWY=kxy$}bJS?TA-S!{RhG38Vofe?Q**~W52PfG7MX&i|_QmzkNV6ZQf%#1P
zEn6|deEXIMki2O>@-y@`+Sd|jv;6@i)1@u;^L_(qwO<|zg*N-uBVp;K{f1s#I<88k
z2!jF2cv|EKqDlxP+@w^FgQbJYVe{bkQRN~PT9cI<=x}hBa>zfhRG`fI1wNfo>L}4y
zp*&1wa&^iyN-keho;m@pS^1XYj(3!&DV+U4IpGi3eX2|hg)^^|Cy&rParF)0e7Q&O
z!jK=goPsF+oaq(CYXZ0^+)L6xZdeXvg18Oz77OMUZo}+_a2`G2Lb;h#g&D>LzkoBl
zxSwXj?cLl*{pj1nRgQq(Ue137!1i$~yP&t9>#Id$9A`r}{Sof+4JgEOea$pZZXq4B
zNZ@Qt6k|x_!sx@$$GA%y;Qn#WW&}i&xS(Q?6I>OoV3N6ZIvk(E{hExSrE(1vUrOT^
z(GEPFYi1ys!CABLFpJxD5R%#4%0B4jaN}vZPjV+{!<EZ@6a<pTsp<WS5}<N={uXd2
zXrP5$2faUvI2YPk7IWbSSUSaxnFZ0)TyP>_O1Q*EG@juaheEHETNVX_wVZP*##GPQ
zx&yn3`|L0j+PU?E;o*HQj*6<DaH(`Y@fFwjEudd>T{j`w&v{Rw=kFVCLo+(xa(=W;
zcI7`Q1a<)5ZUdP>J|Gj=LA>{O5DDgIrvWsCx2H1mP<{<P@OJSFjPPkUAG;sU?BQQg
zpmHxidIj|M@wlh(Q}8aWAcuH!TZkOy|2+&YmamY|^DmD7?HjZn;U9GZCZ2zfzC&@8
zze4Au6ZmNi3?Ab@O9gkF4@iaGB>ufQn5Pr``2v_v=5JF4Q3@Y%51^_1<V_%H{L30(
z=J9(}7;irR3q6gC_=bsqF6Orqso-mW1&XPXH#S1_0?$o`Vl|)n3AlPb-wL4D_-VNi
zZQ!*j(7(Y4(Vg1H#}9)u?R+q;?e6d!pMZ4m+n+(?F8{|q_}j^E^8wez%c#`&9)F*r
z5%>8ldUrqIHSSR8=0!UgdT8R!7Qu~2e0DO}$NU4TVCvy3-2n51_o0~eGk(<X(CFnC
zjmB^AoF7It;4k>4ls<pS4<3UN_VE*}>G$P_d(-dB520d(em>+1z~1mhMX>OeH_<ZL
zRd~GtdTzqOG>Ethrj=Ay?;-fnrRymixq{9>;q)Xl1__UNXaozrbO<R#aQ6UOm@t>p
z?z@C7cR_XwsqezkJ;Em1yB-!EhQU&-u!ltAgi$xZ9T65k#315@2id?pDvX^9E<xy^
zXi=h2V`_)uF<}aoH60g%!qAx{Y(55ZLMXTkXOe|^_c41Zf{y`csX{6}!qbE^hai$6
z4EYA2nL_bha9P4P^T1^bUr=9;5KY_MlR`J;>2rl1`m$r5&`kl(e4*zW`U-@WfmEbe
zC@4NbYmu;RGq_?QlYY@tLf8_xcv`Tc^4Jn##4u>o2#Oe(uN7XpqVJ+`{Up4<B=ihN
z<5fX55F+)$eVWP#!nHI^SGQ0}$BteJ$LKKZYhnF!80r^7*TKRYL9vqVzqi6dZ|J*<
z4?l#bZsIxG7r2YxcfqcQc<Xn}jHj4HCuh9G8afiVQyl$0`n<(eQ-J0p&Kw79U-5n<
z)cwRUiQodnd9)e|6c;$5F-VNx0KH(bXd$3O#N|`a7b>nrOdsnXv4XOeyTtVlXx%NA
zdtpp_#NP(N#9ndhA#nS|SAhWCFRrHDU%05i0ukAFD_Utqh<V}gK0$nQ6pe|Z{R%W5
z6OF%uJ1%lj_(hV$5hg&N5GRg-dWzUsk0GUs9TbK)rHM0XXPPb+HG<6$7e~WVrf5xj
ztAit#|Bex+j~w+MoXHsZxCJmiqm+Nb#I@0nc$l~~y7nSwrhoijlnj3}J|Yv1VG|_3
zgY2JROOLDY3A^Z(6EQ(316byS!*5}}bi&^EAW~+UFlHfSswRZeo!&9wPg;p5e4=?w
zmCN|^djn<3H%_B3c>ghZ4s85+#1UTnHM}2xZ{AFcwJq5(z~6e{HdI|1<y7FhG1DG^
zb7y#}!S`cQ2LZ*O`G-mo0~vQ(l<r~HET;2^dzl4)VXV>2k`$oCFuVl%2N@qKNlIYK
zDfXAhWIY2p#waP)a-7-pDL^xr6?9fTlX-_uW)?8TF5n6oC%Vgvn2`@KN5xD(h3U$f
zwUoN9U^3|NbtSXxF6>n?W!KSXy2`{;!CgHw>m5wMHHM`Z)OF^sAegwtOrQ+UZRRAU
zDqES)8=&9D%$N)h+ZpFQ0KLOp84tHRn8KInyUTn;{&q4GbJ6#hnP>yd9wv)!{U^*B
z3YR@){-x~NGp1VwuHVG;(DUyNb7MAU=q;0c78<T>2UT>qvAI{!=+2IP2y74biw%(U
zWZMbGi#<$xuAS_czrdh3+m!|pA2yA0NWScJs@nBqH_<cIpN(D#$pAKl5|)AN)>rU1
zh}}OGB$zd=iUSQ{EhodpQ1;doaAE8nDu3O@_BaD=H>(*B>^*GeyAavS22nM^KK8B=
zef!zCH82s*R!@VY2iUt*ZWzH9CBmmjcFY3IVHEqWh{kBP>kH_`vsk&}G05s~!kHBI
zvWcE2sqCCmXr!^uGLUpOf{s7tv92s+^4Z-K*C=2se*#P)yH5wZMQkKhPn>0={zl(9
z);kV*=UHnCI+U}Y{0sF8Hf0%Ht7KnM9ZMD4QVR1o*eg{1aFca93ew1q(b4+9iT#V>
z^S9XjJy2|8O>>~p&TiWa{X6Wjk1&c3_UB*d_hnl?gZrIqqB|72*t>S<yT=};1fZ)V
z%L5ADlDTvUEJ)%!0S5O-_Rm9Oq~y5+48}_I8(`tMWChjmCP~Jm((~_x1pjvp9`uq*
z+FPbb%)K!AsS>Uo8U>QNR+uQ1Y_mdRk))13+Ey$X+6C^EWaj@Ofsz^T!u%OY$O0&o
zN?KQdlu2IFuXR?^MLEKAlB1geeO^*<7wVTKpHaT_hUA+u^#9M@mQ18ViB8GIt!RBD
zSy%y$=aQWin0q5h{TUiN%^Z$ny1mVw&}ziT?7cPMe9gK$VZzVMK-+bHv#%-O8(<c_
z7~FodPb}eKxS1P0Hx8K1d<&Eavk4nOBF$Qp&=+MEyaID*iZ=UZE8IV5)<lnpLuT6h
zfH`cYO#n=+ndA*foY`wyCLS^K7)+Ot*>+DTrki<Dfp4zaFLb8)l$qHKh@3N9oelMB
zvsk)hub36nMSjyP#2yN*W~&rXzh`!dk_7k7W>SUv1C!ZgGth1`FWPlIGz&6fgpbTd
zQpL?<vv<7!(_`kd8v1X{e)<L`-kSYGUj}rQX2gNGNq?pHs=M^L53oI?XY-)oDQ(&T
z6JFA;GE9)SbeJ3Ze55z%h2|?=M+fiyq|6u)f2rwxdYT4EjkMqils4wWM38him5%L`
zh9V&+-7ihL04`iQJ{vFx@Tm^?8zFtRpXO2;PEp_}sTHkeVx-knY<Up>Lm5yGNo`{w
zd06@hoy3Wiw(f#6andR80Og4EY%jQEsk!M9WKyJdwBSjVx_*n!H0g4x1x!aB0!W5*
zG)1;ErJJctI7=Fk0e^F(mud5LQrb<Wz`0U4$~xsqU2nr~zSNQ~fdc6yN(C26kNkwj
zBI)9PfpQKtC@^$h+K>f>a%uG=6J#o+Oaw@!^fX2JtE8T^xVRua)Cies=@*;u8`el`
zra`|>`uqX7i_+>*FmXwG?iSE4OM@s2dPTaT5!_Yj>+?{rmyV#E%r&VErC+W~FOi`;
z(rZIOI;0h!0qm~ym)G?Dtxl;`F$U8m-M$B%_pnC-_5<lZKSIA-x-=T152e2(L*$XP
zGYgH6rN7^SWRKJ_4R+s3*HO8XtND#ExaMZ=O@UW;bJs|C;bEQ>fId(2yPred%RDv}
z9(tQk9Sunz^K<<afAKXBUkKLEoN0ohzxm^_01Yso{4cmb^M7dPd%*mS7BCU!t7zpA
zY5ukwB2nhM={Afu*DU}SWB!x^)CbK2DDQd5e8?eq7;D~A1?V{Q$pW||<`E$Pi#PZE
z5kop^K4%j8ObO;=x-rj*=3EjKkC}TlK&HezZZ&?`Gv-y4fvYk%oQ3;M=Jy$J&E|J@
zK%w8<hwAJTEH<P9t<++%Ezrs=#)Y8qrbR~s8k;SCJPd^{i;ctK+GC3sl*)Z!QAQQA
zFD<Si`h@taWmGLR{494+LVUO7=nF6(V_8mHxiriFWRNMaEUASvrIw4R1oEb3bvGm*
zTh2cYP;Xh`Kj_;n6M8X0hh>X3@FG?A-wI%6$wG%fq+FInOVA2g$^z*5%MUrCF-U$Z
z1YEG(bcO>PA|Fiou`v0P>2P?L{PHDq?vc09rMFkU=oS1vAph7Ok`eL=A3-EizRnzu
zM$22M#ydv-jUx=k%4-hbM~jo+8v(r|az|PgCCK}%p?+L`;ve)S%ZJ^EdYU{j7XD_)
zcbk@>GgGeo51rX^>ja?X$TO{A{-oR~95T6b7rMnO<<~y|xgZa}hDoTE$Gn5SOY%=k
zVd9GX_;P^O%g4FFi|g{AzXjM$c|KjFx8$eaLd4ywlv2T-Ruiv-+i6w$3(Wdhz3`{}
zN03#CFGNGER#9o~ZmaN#(BEtIt_2#yt<-d0EYj)|mR{WWBh2|1e=qT({L#|UtKjhW
z20FdGY{Yc@d-*szHnAd`gYHV#Y54aKy_snLv4)B$R_#tf`|6hMu)0P`hhj}@Z&OC|
zr`ez4?{#A*;m7=WN-^B{#X^n0*ZWYa(6}`iquu;;KK{KW_b4E?rqB!A<?{sq-L{4n
zTRYZG!oUAJ;RGC05LHvTF||AxcV-;b+IuhsW1twwjK2<NgP1^i{0B3p1*5@+Ft?*Y
z!WpNpAaj7p+643nMn-vq6h=uEaXHLy6qGM!hS3L1&N1idxn09dO`r`vP0P6t@OKP*
zxCN#UvK)OM^bk9l5}t?IlnkiGvV|RRG=V*~4vmRy7JVwxl*}sVxLOKpaRp;cWk*wa
zWfp6#0hi5otN_Vjd!s;3vVBxJTFCZLhNg&pO4X>vY&=EUN?HBiFki;DQ|;AR_R<YV
zR<ia7VWNuF4TM4+yWbTe7g-BBJbj5BPHU#iCf0vAWUjNLmVs?xhbM!(!9Jn#%of(y
z0o*P2M_P5<W_^c2zm<JTmCSAItSZ>;WWy*D+Qq&biD5rve?N!Dr)*&i6rQn3<xuZs
zU%No>6}$Um=($P)>B06ywj~nN_)KnU?`6=7KW`Wddd9wGylHw|*?m;b@5UB{VkGYD
z!cU;=!8TREnkT!g5X6gh)1q%Ddxh!&y;+AXm=7OzN)FV0*?sBg^JDucJ>$>TKLJ<(
zJ8ub$2C_fU`!R^U{NjK4XLi#l$b_?X_E0>)I?@q^2-ds=&KzYwe+x^AY~f@1|9L5#
z84CB84x~)u_XfIomo0h<_2p@Hu(x6<ZQxh79|Y15i@JdDW1JQKy~=?S=Brm-0@#|I
zV92kno(hkC8e^iB&AP(t0R7o79Dn~ZgB~ouDk#*lzVQ=4{I+;M)c%?=6UOxQl-J%e
zpI(hyW2d0qlbN*?YF^AIRK&fLxxNG{!OY{iFc`wDY=d|xb9n?X!<g5!B#mISYRp0;
z)BhA6o1&QL61Wh<<eJcWn0fsLV2&`0lpqPrR&(edXO_|0JDG{2?>5yiJLr*H%gm>G
zj5=ml6D(b1%3s0mC1%<daMu{`X;5!uVrWlwn|Yru|1PGKz7hP48GjLa`1D;1M6mz4
zK~-UInSoyc+l?JQ3@|b5!9!@wX5EnI_`kdBmKOiWWxkyNr95WOHu##)L|9=21<co!
z<1A#pr0T;WCQm?PF|&q_uAgFxX_H;fOkrWVf;nFS^-5+3T^m)5ayXrTyubugYc*rm
z0ht<Roc4dCOQoPdE7Q6VQ`W{jplYCY=ItVYb~EV|uzSetra6AWMAFm#B~wSC4R>~G
z9=z~im5U(a$!^*Pg+TVA2_%S3To1d!?DZx{?q}s`Af|Bk^HrGK1MI)_9gJA^$9R~J
zW51=X$Psn~t!(1i8+0G0uy*u#Ol7Spd6vs=r6S@yw%`mb<+Hn5pkBbvrOiVbdzlJ^
z&$3f#S9p%SN&(9A>^o$zj%}n6`9-#C8Wb*>*kXF*U1l?AW7EjayoAms_U2i1HnY3v
zQf*;nZ~tF!-yK)g(XD-Eb~zkQ5v3Vp0%AiARbx$jV*z^u>;(}}RGJh;6Fqi`73<i$
z#x5vvTTn6fj<LkvyNF^pw(nVoo%bt$-QWH0y^1`0)~q(OXV0FpW{bRAd>oywc+3Nm
zk@tk}Rv}l&d(raHQ(o8+P{aq()ax0))EF$!x$6Z~P%-zU0I3&z0d1DO<gpi^^A(>?
z2g6@;`^5lcBGhCCe0$3qzJ;gnxR`*Vz2`}lK>VARqY%Fj+)5#*A9+F)1U~V)8q`dd
z&cB4feCY!XvzAHq$HJ#IlBpA%$&uE~100l&4*~I#<V#B;PbFgph@<4MCPU{UIlxZy
z-p%s3Ch#U--g6I1Ps>N>?9X-iWi&Y~Z<`4D53+ZG-USpW$+V(=S-Dt+*p$CdK;un(
zO&vwQqbyqmq5DeIOz3~Ce7*^zMaqj&Q1L<unhwsl_zxK2^WVw|U!?3`l=C#J8LM8a
zXF$R5<7T3;i!NR-p|4xHLYV52?+!J+9#EU=eR4Z;`_CPV0uLDOhu>)pXqu3IzZlnp
zzw?CBA!})ub0jM`hT@E3KFi?euPldRsVB0Iw4gJC9ZZM%nasYoH-s0kDvyv{$Vx>b
zb0w=myCAFBD0&5NWUcza!A&fYzI3#i#nB>)#wve=Guv5rdQ<LT$L2$PC#!0J-CZoj
z0$1{w=QN~tv(*QoWe?jr0xWykB4?!XS=yfv-^bS3X;|<Fo4)~e_p|*2q5A+^+ZhHA
zvThWGd59gNmAu1DrcZ|)VUGor9%a`W0gkbsCBSiZh?ad%u*K71_au8eAIeU#inNe-
znzcU#xdQgb6%fy`ab=PElO4PPXD+jWE9q$a6}Fhde6F(5)nVxx>q^7q>+I=AcyWX6
z(!lb7t)Q^&hwL3qRv)p`b0Pnjb)?n7Cv0K@bQiMMzR>cNS!q|ah;^dbd^T@063Vvm
ziPVp5=gTRqVJEh6p(T&EoJsK?`TQ2mQTFpW(J0IzUhyuKkZ*hr!4o`o2`ruFiV>-^
zJR=6WFY~|&V7Y@83b-~>${$G)6!>vBQCS!AlOq9(`1O2<F6L86(GuR9)(MyLZz!5{
z8F!rxN0#&6cG{j?!7JQ?dn<WYFR-rSi}1EXuT$6@R(|953<$2_ffQ!7mb+0$ypCU?
zar%1xq%t@+@J@HYxsmtU3(igaA`J&O^D`A-DVx`zh^8FAXFT$@@F`~0n8p{-rffcc
zv6sf5`*@4)P<oWl9tXdV@pm*JI?kUIgXaX_+YS=v`Mq&4e}T`ZF!I0nl%q&p<Vz1h
z?k2C(3<bT#Gikbgn;)dboICt`S~0%MkJ6I-JzmradH4CD@sNAKe?JYM9&-Ny6o2}N
zm#6#pn4h7w;wRkC1=<R^^9`^*<v$04wTMrolVQ(zY#!h(A4bF5cl`P9@b^70UI|No
zb5AU%pqpy&1;mfM$2G8g;_e**pE+BByzx@k2B@wH(k|*Vr%7SxyX;Dq6i92ubEOv5
z!81>?K1XVqRGHRxmP>z7u-H0DqTS8)QXK7KZI#k!=OtHK{R*6UQk^+~-O?Ib7Cb2V
zUP4(8Nn0tP_^`w`g0n!%{|<0QvX6mle@fp!gimLsQq+;!&q>SUk$GMk7=p|TQs>#Q
z`<Ik856)baqVr+!lGJS`ST0My#lV>>((O{veN`H5#@fy`Y2aG0T$lbu!?hbyLwc*<
zl+GQ1vRhI=df4wuNwlkZPs*e@<$WppBFsOKUbKUS$9Cxe4UnEl)2+xXlp3D{>r-i6
z4&;lZ@YjH1seT{83#m;Mbib4aZ-L+^>GO2x9w}R$Auvi->Cnw+`6985k)=_{8!J1}
z((E{S^JWw@Q~tFYy#H06(H-7TmivE!y(zLihK@l_l@qB2PLunOf~72Z^#o+Dl~;tp
z)2(vmNl4_${W2kcK;A_0U?=3H{UAP(c^2JYW!f`%k*SXT5y~d3jVUf;s`~qBu*^{}
z+<@x&>c_*-xj-E}4ylFeR$7%@q)xE!1TI#~yoA!Fs#g^_yj;E56P8x0Ez3aZYPFUd
zIin`80CAl<)(cA4tBJHkx<Nfw2)T{wlOrhhW;Ku|9ocI6+khOk{78Ld?I!gDbC-uS
zL+`rI6$ZO`(*kez8_D$jr5=SL@VaMVOEC4i-4?(5UVaS?{pv2ob=<%dT=(Be!E`AJ
ztx>Sl6BLk<=0hWe^nQ!*d+?F_DAbV3RJ5NrVOJBQQeK1Vo-L#yz!bJ51!b7Z`c;Re
zY3w4^c@`U5MF0QkbT-}-C7Z_@(lXb4mQPRk0=EAqU?EefjW1$TA3=3C3p)Va8vAJ;
zwC!fkXb8QZy~_mP^Fh8~In4r^L)m#I(IU_l7TFi6+w964IP-*MzXS0NdsPNHM{<u^
zuxFpnx6<z7GVU^sLjiu=-Uon?#a!k??{wx&OXBm`{vycEXC8F0b^)u_5U`LH*8%@Z
zmfaGZtC*c$KO5N#3Ip22p6-OeX4Z2DShATLg^z4!cbg-%gB8(1jGb)87dn4}uYyxV
z!2$O06-sx4`O_QYB-`!>FD|fLT4?)=J#GbUH(2K_NZn-J$D?v?v7r=gaGRZ{Er9j>
zR2K+r;G<trli-^oQSwdv1a<72c}tqxWb=w`K+NH#sMp@YpCAkn|NkEUhKBVw_^Nu4
zUm}&I?bW4{*I*QTnG`^=$jhbgOt8B`+D36pE2X-0RAd#pG03f!BB&|<CZ!Dl%NnU`
zU6gRG)Fli4u9JSC-55Mpbh0!{u0~VF>2fH&W@pGzv*D9{rreN1qG!nq=?g`(<>CFI
zdyZW35QsuPN<qwX<tIgS59F#8KR;hC*AsRZ$bv>0<J1N*RC@Jj3hZuDy9FY(RlQ0h
z^lfS<f0)>=&N9Gmp89}JgY8kr&<rVGtxYfVKkRBUoh5jq{<s~ilZ~C|TT>g1D=UC_
z*mxC(>F~W-zuEBOyzz5aeFXT3&!_3pQ(m+WUKaB=^g4gdhpj<fzvn|}ooRwp=e8al
z<@UBU3^wVWhZ<=WP#)K<KR$--HhX-j|8Kiv7>u-w+6Nu&^CuyrLv%T454-&v-0i+1
z21<KGS@FAPOWNb><@Onzk*9Wo(tB5XI1u%sAEXAj*TeO|`n0*9+MI^2X{YIA-Y-*V
z3_84G8%T{~?ddq-cy{k9awf2gPwk*)vTtd+^((6u1*r|J{c#B7va)}H2aS}r!1CF_
zHpn}~hUS2Hg8BFW{$#1g;QB?jj^>Ql*>qZ)y~kXgkt$@}nxdqynehzdKCvm@$Q#4$
zKSAzS?v<gBSlsNt)0yXxjTKQjq0guxrem=W?^yO5MfkpBo&BNa1IzjmN<XsQ`yu~@
zz1abuM)G#8KpeyOd4Y2*&$|Up6L|4tSjyzu7qHCao%5l17GGKwsf|1<6{+1k<DNd$
zKF#gzego+u&z%n)mw1hP(0G}*^hSML;d3$|b(PO-fV}&BTU&5G;4Nz-^_YjAhhI<l
zP)9HW|4ftTXZ-P3sNMJc2RfGhH$S@+&Q6qUrQz39>A)_io*^y%1!bIt4}-(PY{|*q
zQ17JO&(Ub>B@4}jrdMnY4SHX*15;u14KuHYinr`+XTUplk@i%_@TrN8V*AX2&B^@E
zPtZGs&!%DSZ0>Uo;&XUinmGyn`Z9=1czxP0UCP7hLukwRHmaxPcAmlD<vM=09+a-<
z1KLAk18=qk#9Z!g1<&ui6ODv-b345>_HdgFyN9^^4r&hbaDh5H&2t&V3wU*!%UtH`
zYJ&3$uk;qmuJY!z_I{1e3WbN)`Tgz4yTQw)LGC8EKOKX5yv4^}g#2y3<SW1(9+e6c
zFSscgrGLr4Jqvinuh1amHNT$+!8bg;Dv0m+0{V{B-+XEoiuQqbdx_K-sSAa&jFp-M
zfn}*QjJAT;OPgiL?UmNjQGmasm2{5jhLmA{51yw|BF*t$OQph)`APD41i#10$5y}@
zA@^wurR(MN)=2G<-_f}4wA`QwZr_pD?gQsrxmjhnHc9yxby~BP!5@)Yp!ltUPs^1g
z3PoO{eE1c_g{nrIF^kpft}weqwYH_@pQWmg3c<DNP1+G#ulm*iY*3q0-?vFUKpjJl
zI_?!x+f-W*c%i8e5>b~s)Q5OyDZA9^)gX|k`Zk7Zd(^4#U@%|(LZ^xMsrRTU?^lP{
zg!loq<JXWosOH3icvOu)NALfW>W`gZ{*>CQ2b?*r22F$fS@mk3-rF@>xfeCpJcXv_
zE$;b3LCaEQA>Yca4=AnAWx<Cw=jj1%8?qjv?cU1pqkTpZq&iI40)NA1(TFj;o-2Ha
z*hpS>G}nNwPHZ&=LUtZV+uU8^Gr`)m?p>(pc9X{U-EYuAwjM7YAh%Zq+KY}{>;Xl+
z8yA8S<)z@d&&`?OjBdLCdSYfif`-_W<ab}u43vKRm*YBaD{VygFZKcFfQ5B%J<xp%
za^wAX)AyGXCT~DS;(*^lO6o`fV#zVjP|86&p23xr>`%B(U0n<GAtSou`sdlrK_A85
zQ=~^G3+aM#<})m&!4!VH-qr@e=gws)t=#W0l=^@1fv3TTbD*O3Xc}!axkvXl^jRT&
zf4$3{HxTRbik579*38Fs?0#CX?dw+nSCeCD-aIH`5Uw+18uJeIua4g%5=X;}acm+D
zPo}Z)6ycD?j@LtK9y=BY^(&YcO?KC_#2loyvW*mrvXlMGAH-ekcyB-+v(H}#e|EFc
zHDTp2t4{;xQ|vAUykB4)6Oi{8YuO5{cUd<S58cN>nt89`z7impht&b`ckW8xLfFQ;
zEP;T=r_4qn^0^CrRPj3B`wE4*!ILXP^*pJtJyg$^n$Ly!0*TpsqncJq?diE+C0(5h
z`PGtNE<%vkOFso6E;(D;O}hoBq>+cfa#}i56#@m)tFcI(lk87XwDZ!}^o(4PDsBL0
zp|tNBEX|NtQ5@d}Ikh~9o8?{)A+S~cdO7lP<;y7`Zj<Ye#r}WET|09PdMk#)mLvVA
zTz?WueMvsI3G`d?`SCDRB)9t;WqBqaL~t_pesfkrS*CIbaZh}blF&cVz$YsSQ5mqV
z*e=4tY~^R#sh_J{e+jh<lr_CUT&#533tx^ZQB^4Zs6ZL_9%?Qs!+!_QHRUi(qHie~
zSHXHu2^$A^q<FSK0iP<hFmzF$E3GHOwHfM0nldd`f5HknW(ynX4CrsFe>z~JI-EjQ
zx2l(p!TUUQQ5CTKp-!W<wu9;mFZgss{q+ZEvENkZ&;g43>hQgw7OIbEruj^rMhm|m
z)T6^-{<He<6x570E}(8B%XpQxG3FQt(OJxS#%DtyzR);tEW}qC57DWYHO4Ntp=G^s
zm=$?B##Guz$u)kUvBOd0fRW%lVSGZ%^{4H|2ABoogZ)9np!<q(3C$|58=I5|>n&sY
zQRLk<#yo(f2gY4A#e8XeavR#-7_|rpd^EQD0)f#^Eh*e#oKww7P@3s<=`K=}oI(yl
zV5-xykAPWD6KT+}!|BZkz(J>U8sYurWDlaVf|s3MXT#DRC-r++dgL@SjVi%u3XPgy
zIC)rL>9y0h8Gv_A(`jn@+3ECS2#hklpy9(<(<$0Qm|&_zGozWNLrWmH)-;jgBsZ8Y
zQQ+P#Q@wo1?K8c94$cFnn=Qa{($w019S#?m)&?PY))dthE#a!^6m0|EGYz6P_r%2A
zkXLM~wHt!3OvC&k@Yduz6WabZZOcU7CzI)0<c)NGNFf+woQExf!ST+ca#4t@=BB+-
z-M7tgRI&HW`==xCq4~fw2s|-|@3g~Gk-6PcB#X_xyTSYzOW2>N;E9&jG*=Op@wCpn
zz~Vux{YxwpXeDxm#iIx8Zm{g_gS>1@{WLh5Yq=E;OWQ53EkN95X`cdtKP;YfCh~~o
z(-p`SSSD>m>XKz@WpLiG+#gKypWDz4>OISvAK>Cc%c2)ZWm<!+ke_T#xDOArto~)-
z%q;8c^(g&Zt44#Bh1Mq&wwPo6kc?EW^~OS^G;4NElx4qlIW5~gvRbo{dTos#guD;d
z+uk6Kv)!!%4>N7&@liy~KW(Eh*l|4cv6F4M7#Q9dW3mtE7$n1X{O0U~&1zuygB~9L
zn7@BOqvYg(@RVo+UBvf~j!NsFl$aV29?_;|aFg^tu`Qa0_(y@INm623Y+_n!KuC0a
z|K!xzfaLh}e*M82os{68nuZ^-<1_ogJ0U7MDYbU3$RL0E8ypy1Gq7Gz&7j)BwFA<U
zlHyZmdvlLQ0pN=3pBVd}HY&0|vylIgtsetYho=7b+lj0DpRK?Dcu_=e#x4ItcFb`B
zQ7H+2iAjmEez8$~`Uj-Nr6=?W7+fdTFQG=?<bb%Sl$d}%{nJpj9aCdd&<vtd;*(MX
znkGf3Cpg+kSm%i50jbGR(Xo+fu~7*DO&YcJYXYgrHc2t*@v)KNNqy6XM5V-v;hb0e
z>AynD*P@v7CjZS9Bq}iet#~5w1>z@#n?y4sw~6sG_bVSAmFORroNU0DEj2BnW^mtH
z85xmrQStt922~uFd9ZL%xR2IC;hniPE;cF#)#eZ|iN!|l<>#_eDbuf?;)Z_}`YC1N
z6!R}iSp%1uP^<(;OHwVc|Hqgp?jXBr4~;xe5|PuL74iK**;Q!Yn9FE+W`4GOndXgJ
zM~0_GrKP7v3{8%08r#<(T=tke#IbBsHSLry|GS1~WMtzO&6<UTM?^Mi-J)6BHX&^z
zA|t))YL6oLTOV;@fXODNEp%4Jg;Zk);oaY&h+#$62+@ANENewWcu-l9xzX826z#UE
zTJ<cx{97UQP`$Kgn|MflQE3l%6VY?6RkRL|csn04r><H>)E;Opt=%<CM@`}Zm#pIF
z6HaEa!QEoh&bmwAxN5G|q??LJYGx^~`36YGWifZ6;_B2sDb?FIxNb+yyO#7}gc6<>
z(;`MZ|B8RDP1!2hjarLcQk+%0bwsLY6x%*3F5+>3?4eaDkZPO7q&8+>k#j}z)UvNg
zWy^{79!4*%;I)*&Ma~f^P>X*jCDw7G%4*y(ysP#lKo0X2-<RcO#L;AD4-rtwViO~Z
zjn3lwH14D&b&+#qQTc@upmpvkU$=@63%E(^G*EsJWFj3+W8<TSYCkNJLnRTq$n2@@
zSSpt{iDxyXn%eoba*U^yxbP&<tw~AK>h6=v8MVwKa*T&a@<dfv*eZpIn_m=njopw(
zRQ`%sBQlyh8p}WTF*346a1#;KUintrEh|YCMDpJjC$X!p$t2btS1M|4t0*3-__2Xn
zQ;Yddk?M=UTaqHK478YqTWM=$ZCYO?IlxSgM6_rV(yn8KR%edV=X((`O|7n-JdXWT
z?d&O~Q$^9_uBoyX@j@|{_8>n(gM!0?BSRYpMLKRsP{(RoH%UF~u9B*Dt+emHQU`d6
zDTT5{J5pCo=UQ?DHQlV4o2l>IG#|7KCsF&F#YN0mDp%DS#i*?+io$E=0B!OF^@vd$
zF-`5Gh#l`O-rCJs>Npo6ez3ZTtllc_=_$oW8?Z|4?fF$`9fu2byd4hdiO4po1GR&B
z>Mg|u&tRLV{_%a1G7OQCp{*mtzFd>5w&xFZM!2xc%GY9Mp5m&F@-Uw4Ad(BEvLg34
zw8+76#?7~dyH#}&uR~Q2tw}4Vhl7M`qN%h{m&l%T-kVhMWw_DEs%h1CJB9fvAsJ~c
zVzi$hJFW5%!-JiS;%TwTT?=BSd7fg*73Uzat*u%{yIR(?sFF7QN7FCHis9{BL^cTv
ziVW-0u5IhCdJP74tY&D`v<WhTBbzoAjgCuYwYU(IR~2#pyxFEL9cZfW?PymaVPWmU
zv`dprV?4!?2y`MnR+xIah^kfOGTP0prpQ3iHqPj$CEPWoT1Ds*G#}3wrsOi>j>YC$
zs&#k^@4$?}l0SHgmdef<zOF%a=(hb|J%r}z=X|=mXgbtfR=c0+JlI2YUZIu}1=EeP
zspJ_9#ywA3;{27(6dK;9No3=Quv%i|K-E)>`ovwuO)p6n=U+Oxh<<)bDbem8H;Nit
zj3%vkqw^v^ZSNK5*B;``5Y<h%&QU6h+!xN%gk_i1P@C}588`gICSFl1E1O$OV$2+8
zckPJLJk?c;`Py7HSe)J@E86xp=E*fgP!+U>9z)HO%Z2{`zBB@w#`a0?CzjRY<wW*1
zMHL0vimw(h%j{{=dM+|g`$;S{OEpDYeZ^e_UN<in{x)Ze$h&TK5@ib{oA&2*bDkn6
z4a74)<*wQGO__+4sKnHS{%OtPllnx(NAypK)lM<XBb!*vEI~4EbxqMB+*)2c=VHm1
zMeGdIH{yq_(l=u143pIs(za3K)*(#|j;38#jB=O17E5P3soGU{OB=Im`_5r#D3MJ%
zcML6QKEWNeeiba?(c*5fR7QA(n5qh)DW$ZdV=XS`GR?z7B0Du|-7&<wZpoeRs9l_9
zSzbr5v)1Zr$>Sp`<V$Yaw8NH*PNH1}i@Ru8!BRs!$ikatSb=4)r`tchRil`gh>SL|
zsi{%@VzsD;mM*15m3vYt(R{zvQ@j4&QpHoNSK3;?mU~b=()|DQSXxSm^;($tBT8`<
zonATziU)TU5AnRFV$@d8wa%=rb;B69lyK|sTv}xGRXoLkM^2?hb|XpFemZNtR!+N8
zWR3qu8*8!MGC9=?3ib=C9T+GQJZu3r1P~Y+*_<ZusjRW>xmf36JH>Lfp`NyvPHekK
z@U~Sg{TbulfBv}O!d1-nw$1VmitZCtJ1VAjRA6A8x<SEFfwh9`)Qt{~{ysXWPjKzp
zb+i^0Y^_Wk{;2^+e{J|D^?%lfgXrk^$%+sDInOf~G6=DGzmjl)!GNFugY!azAy+G1
z!&Zmchhp^2;m$Z65l-PqFVb<7j)*gL(6M6Rz&~}wT+5M0AhrW3^o;az?EDbgbS$T1
z6&-_1&~9j`6R=h05a^_19~~2QL==o8f4q(}bX=_CIvtPdh-d@{f1!@p%5|ji^%4hq
zI1p=vm|Z&vh|qK(mQ)=Wp(B?49q9==&eidVj`-NIBOmLH4s_G8f{uu!bI@Dr*jY!M
z0x)nps%Vf-z~a1vagvURMt7uF>4@(KInpjz5~Hfc@}L9pH5ms6>sU|6W;(Xk5qtO!
zzTP_a1uCQ{UhI2Q%F~WmTu1&a9p~$~RL9jiZqN}CUk-kRiaHQmx(>Xc;~gEJ>-b4W
zXSIY6Uk-KfS1Lif0SB=i1T4Qfu$7KobnL5Rx{f1soTMXGTO4vHbwpgQBYj`TmpU4-
z8$#vAT8{&<oC`!#c&QWK>4^Po2Lpl_9Ecqn2iDRNK|GE$R=OQ1bi^iwBfU|_Tteu=
zPK$$%m_-NP*0Gq-3XcplHwIcv6Sf4{@UN7%CBS8MU4Gc4b&GS^Nu7!NAeV|tVRf6q
zSNw=eRYv>sHHp51TznL_8aBg4F@-q3vlt8w#qYRe1H`34E>&5fU@3r!q8h<R(ScyG
z7z*HWpje*bQiZ(}M~PZX6a&<Z^3;)tQz<S!Y^-RM3etR#7Vr|%1~HvT-+LJh{yJB#
zxJ9IBkOFj4p$JL?X$DB;OGwsAAvS|IN{jx;5GppNxO}Z{LiRtVnu;?dQ2^3ZT}iyC
zkPcEWNOjPaSVC=v-nx?3B}z6UTVf^7p;42>mI?;L0A0yKQF<^)<$Vl>8zo%UO3hJ^
z=o!e9uo5L7D*oG1)>`C{glDDy?Ho?y4gskiNSAcIvqT3Xm8onn__>r=UnrIl>0jR)
z3|_h^w_Y{_R#hCPdN@oOd(}1=M)zXkbc#y_s^AQW+(gW2f?h<o=cODSIC<B*#Je_#
zB^gn>#K>fEizJR8XNI43BbERcL$+=trbHqXF#tVuPxHj6p^#V((m<0#iS@f67ehX#
ziew|MM8f(PGkh+|Mx&`P3=-yB%;2uqY!5MrNZtsEXsDBN#XchSy2A{sbl=OjbTQCd
zk@O~)=#>zKm8MIa6Hz}yVhA<|C+N*-mdGK}=LgIXsr#EI*e@XU#6ojzo$IRTK%|*?
z;gpj9xz)>vw7iHJzWb*hI=dL+^m_QE#QLdc%<!$QBuz9L4vE5I_V1Q^RZJ&Rxfje(
z?jI%HT?`0Eb`)WBiIQ3`QT@7eF(POLB({L`t4?|)MiHsOD`uFjo0=@n5UBt!MnApm
zzlaKUkUqU-hAp}&xeuOty&X<2F}3+UGq~uLDaW|ry2O*ICE0tC{ZuNshi=HmIWUK#
zStZ#UKK)yo{UV}9!d@OoUrb`^NIcDxMGi>#4`aDuuDCW5okX}`qwwU<71apPqzR6Q
gp#Xeh*k&jYt45()IpJ+Hd?QZclC2cQqg*`y7rTF8eE<Le

delta 135945
zcmY(r2V7J~_db5_?%ut1`!0gL_g-V~u^W5T#2RCXi5fM=#IhnPh?OE>1rZPx1;m0B
z!2%*63W5az8(0Csu2}xhS@Zq;-(TL>JNKM9&vVYqZ8K+PNm$p<V_m=Pb=is0_1dWH
zPOF$m{*BX;18;0goTvZa8DCjf<ucd!{nvM2zT#Z%{O!zPXI{eAufFJ;rFqHlw_ob-
z`VVJbBGj+G<Xeq(2|v{PiJEc4KfY2>@s&pQ|7Uvhn8AM)0%K=5hSiW@Ytcl_)cYK(
zW!$f`j6$ma`Hy3@?}o|@>l(l?s%F)iql#_iu4Ys%oQL3?V};u7M24N~Au_5i&Oeh%
z#TBhlGwj(ksJgl=bg1}dX#&H(n#VJ$5zcF&vU3`)$_(W8Fz9}8*+FI+zTS5#gf)m`
zRCAoeNhNUot^m1W6IAnD;vFjf>~o%B>s{6`stvUq5nZT`YLD6!5qmgI%cz2CQz-1Q
zM~FJO4#mKV`(S^nHaTZgGVBtgimgLlS*?$XQKi);cdUQ7z^KyekRLW`Fi3B>IP|K1
z02ftv==;|N=_8l#S%z`aaPt-{W!QQJGNXD@eG*h?#2+;f@im>AQCrRJh$*p)%&46$
zJ#nu54jXn#S3Ae3>sm%p?W!&kqi$&Zh0gblV;OZz%Q8CuREhJp){Qtf?<bV>iec2>
zS@uw6)Gbi<utw6k_pdnbZ>>)@UOuoHY->&DS$}F7^$2S>I&a@xVANx5Bj|j`W-Vja
z*qqN3xb*~?(Kxwe(YYB8G&NlE>3sJPEu*Pf9UaK90TZFG=kk)yQ%6dSrhfG=bUyi4
zmeDkEk%%<RtYS1xt2@zo=4<FX)TSO{{jEHs=~#!lhUMdM-m?zr?QG4jaNMh|qawct
z0D~MAtcd$YGx(c+`U*9p8C}P52}Z^OJf<#P0+G5SUBxg0p?O9!a<{ziYZzJ0FxqiL
z#xUG%(^1qg>Snnd!{s{!joK{`!X1Yo*wxM5AQd<yg<)5=;Tf(_O{8Ee?zo$0CKB5i
zVk`NNZQ>M`;U4|R#<ha*_#2x#*9_sw|B+qTr((FL>S`d61g@e<Cc|tZvhT;VW4KC(
zm7S#a4EORI8^iuIRb;qV>RGU>R#(k^WH%1unTvQrwIli?gsR$(25Co(h49HCXtd)<
z`0Nk_bwr+;;l4NoMLp;ags%?4s2ehH3_73iR^32ASe)A###z^I+!#jXsHo{2F;-?c
zHCvlp*41pAq+v8{F3#7mnwVfThb@K>#cEE$PRqWAaE*2Oegp#GS%)7+rHQ<WOXA?u
zs5Hqi6j{1bf=V+#MPejJjiS<|qsA^fs*Ebl!$&-$II65FO)jc*jv8l`W_BHp(SHk1
zr71#<fsMoUsjJd-;&{f$YB+}JqxyC?P^gZ(;YUWK+km2V$f&0aNdY@#_M5$(zzzkX
zq>E$yKe+}|{qSjt;Y_UBA9@SDRJ2J`8nR4JnDE>1hG6(!5iEoM?R<sKIIpgU3Qo{y
zU$9IKrak`+!?%g3VwsJEIr5mtaqw4q1o~CS>xtiDzlVpOKd~7P7QeU!E<M9?V^s{_
zMLiw}Gr^>qe9ylV1g5hVH}aXcEW9ezos2rl6+&N!pizhKgD}7$2x|A?92_|WMZKMb
zVGhBl#y!sPBQ4Yht2)BPE-?IPhh$R+<;x5|&LKFdw|#{0qeG~s4%28DezHSwR=Z0g
z!%uMtE)1Kr8q#$2F7WA_+~Sy~{59h`iqv~I2y*JuIivP$i?2{_9cqF`-6|N68+CR7
zQrE7Ym<YRDb?CNi$jH?F?Dpm`C|CD`wY(hqnoE|>Vnioa9)<o>wV4i;s_iN|w%b9+
z_Q&biaWZZSRj0*t?CeR$F1TUw?fFQx-SA#wRNb4?u}42T_DYA|uIl}Os{7LWSk-SM
z9s5)7ss@~;<M*@4bkJ%#4)&wtkYjWlrlsTX+H@SznT{hz(s9%cLX9rRk*T$0=?q4a
z<x#j(YIpgBo@U95<YHWbc38)b8vy^-ffL8!lIV~Bg4<ter$nJj{i=**qz<;9an5L$
z%$vnX9c>hpM*AxXog9L|=vR(XF-Ez%aubGH)W|ihM9rvOEg~b=vXVQ6ad6gYUPHsw
zl@~!VSie}KFccN5vKyHKAXpV7GyWNV#KAa&4m;?|)w_y&U+JY^Qi0pN3Dm9r&xol{
zj7mrGL7vDEitUfXe*|;r6b}QddR`3|kz6Qb(?CO^${Ru5keFuKk7<}yIPt;1MyZF@
z%+EM!T(1^7qhnhKOOxWk62t1v#J2|j*gcP7(v(bCeQPpNdxfkpz1<}-#v0^E?UlU3
zbO3Kbo7K^oUQsJd6S~Pv4Vi#yukaO2GwK+}Q}5GEsm2OEeU;XB+<kH{S*=G`>KL`q
zP3|stm4{fqlkv<pWz_nbI1%bGLo97@BC_ld3v0pEw6L=5u&u`~(33_sFmgT35S%HE
zVa+f)2VFg`JJ+>d?Qev73#-=uhm#3p;F`j=qYL_-bAU`8;j&vj_FE7tXI!36jtYxU
zxl+w;MMMHcWHYgi^cI9&LqEQni8WUH2OaM8Ut7@LYKV{f)|PMKIU^c96x{zc&gH+>
zepBH2tM2qa77SCPJ48H$U0Fw`z>Kxvvr+3m8J$E8sI5VZ{&49f%jmOj{zzR%1$7TJ
zt8Qzyw~NCu01Na(EW_my&b2J<<sL4x935Hj|26pkE9(Eh6+;MP2dFMu-@u5AMt$6{
zHQUazK>v-Z5e8N8K)u<RPQQgiW=;N=%fy<seVkXiP@GNw*N%F-8C_u9ZZ+`_4>tb8
zm*c<x)-XP6^fl~j@U8z=hr14U7Q?DVg%gV-aBkH(bQ-mjp3^Q@V+3b0aMd<nhnw0)
z&Z+x!oYXRX!}+MpoVD?M4AN>?IHyf}VO&f5t!f>MFC1})u~x3`N1kWY^=;oYB0gPG
zaRZDl6&0s#R8zza;lw#<2V)Revzo(3^S?*6&iR|D)~o+l&*>)3$LLDk+vR_>>R`4y
zSAD<<khZPyP5+Hd9d4-kP39V}H=c^Y*iC(qt;N-OqJZRo83I*CjYeI&wojJ9$zG@K
z|5Rzz{;GNoS)Iq$|9>iWs~UWh)q$#p-%P%08gaIilNg2mS93ts_`kCwDs%|`)2Oei
zntZc9sA~G3DqPi!vtC5^0f*ZaMqgFUzZq>;wfJWApXqLO%Wr4g6LssE7=nJ2G#bu%
ztsA<aPAg8^v=%<phSr?6sufNIiPL5-$8`||uJ&(cT!hA=1EfyZwBhQ!#-~N2zM^US
zjff}zjOPDn)kc}q_Lj-S)Q;2UjYZGlKio|C|G!2pj`KH?__d7AJK<x%F~ymr@tBSw
z7_-BMF&eY_6WLonlZ~$qgIK2Z13Lb(6QdSp=2Ft{ix+TovEL;?!y-D)_Mqd{qeK_^
z4;=?f3XU5wFX9++0s$I5#ITWRe3>jGLWwS<6UN0%fteiS4W!!e@5ucZj?Qmhq_AF0
zA^T?-s&LHnY(g2gl4fuNI~lFzX?QbnF`fT%fs79HCyGZk3H-!PrqlLN5WhU8*#8#j
z$iE=VoA^X>Oxa3uKhK{m-}fese*tk8ZY2h$k}Mk(lFhGuN#i}5&R5=4(=2z%VgiJG
zAP3vpQuVC}Ixp--$9W4Wti=aN|79>au0NIN_PwJJ3%#iIp1bJS{RL@S1Q2ROUqUrH
zLz)$#6xQ&+2<sG2=ZF8I;41pzE6*{x9t6Jc==Q@#qIPz4R|+0Jj#=+Z$HDih(}EvT
zpa-s#{q!qD6yJcHb*rFbqJe5BzbBVRF{(o7`-yG-K5A?8dZgd4BUJb+YRrpH2*S=R
z?MBtbWu$W6PDVTTl7o{eM5<{*dbiC)G^mWCu6dtolg^Wat^G-(($ewG&veZ8qCnRt
z5q3xgwfOBqayjr{sx9b7JX4y`F*S}X?Lh_P{<}#;r|C=QL&s1%nmi&v^`oTU_MF0s
ztsuZMJLwa>DXiZwkv^h=Y?Awso6~dY==6p(4K~wxG|ju171?C3Zb1R<_)K1I(UgVB
zvA-ar?HEGgK5$&u`;Km}+Dw`Sc53Ud-b9y{N0t?*iK6RV3L@niX-3baux@GTIN$Nq
zRO02xG4<LLLq!sW7~^P0yEt-O(2>}}dJ@kMbur53m>&;Ng{M26PyL;aK5DAI;OO>b
zN2HeOL|3~7xk<P}v2)Mp{N6(f@tLC;EAh?Ym|cI8dwf!HoS8+;FOQJrkQ2o4M>+A=
z*-2qtyynRA{FXt^);L}c1rpKu)g#jvrKE3$6bQ$32_?O6HF8kPaph{PpxV3N6P-Gh
zYO~|$s@r}bmzkC1zL%rj6%EMd;%MS|9!BTI%jh_uxti|(^k6bA$tJox%PG=3VMNgp
z13<K|k~;a6<01UlnJl|4A<MG|$+GW4vRv*?8l?-7y4EF4c~h!=;7$zBko>@diht;K
znO<mhF$U%s(`&HV8M!aPHq<15kK-BjzDsU`I5I7Eya5v(j$80VG;tpt^UH~D$oJIl
zUbRTGiDuW#sbcE6z}-}9>PgJ2zY_Br9ksqwJ+k!OLg(doC}{hWk5nCgojTTEq3X*5
zQCzh<G$G{R@m)H9fiF7l?W+WyaGX#Vkix?A@}6qt)8z8!cBJ1MLOi2Zl3wXTZhlZm
zubD_1iwhm4xx`j%-%Q1u;{+Js<N%x__l9`tx}Jl{{c8<%*F!%#=Hf$%s25Vpq)p_$
zID$0JXGrsEF9mVq0lCy!h}k)VYCF`T+IJZa{t0v}`jKqb&UL*1A73Pw{XdY=_+UDo
zx<}OOYmrg-adLdG4xJBeNr8?jB+Zr&bUrDHu-%biLZ3-w<6T5SR0LA(oQ>4(w5N2Q
zlub>#K8h^I&!w>X1Ze5~-=-TG^>!Hjy2WwJ2vq&sP-;P6PpY+?rDNhf3T}-;HtA2v
zM)QWwyXKI~gPq8I#wu!G<ZaTsJMMrqBe~29q9A^4Pd5EK(y<Wp9^C)pAZqL6p9q$@
zj4FJ(5IAEkk#?Fw8n*>>T#hL|$5;>1`Rv7n8u$xY@|Oua;ztTGnWdo3$c5leLK+sI
z+EB7zyp;NEZ3k+=+bwk7Wi8n3jQ$uAeK(khv~J`e#__<^ze?wOP7(O3C&6-i5~($Y
zoW=K`<03uTh)3x7_b@s}UL?z8Bty}?Ps#n->SQ^5Ch@eyKfHiFs8;Aoe(f)3l4{Lo
z67m;Qm-hWYu&0g}<k3<Bk3CMLyOM}vKr-1kyH0KOKS#B#6Up%j$2+tIvW~dXUXg>b
zR%+!dB*{2t##*uuSx)v-C`ZRMaf|>o_TvON;!C9cztC}a4Kn><0R?gRCJ{ZEMlkJY
z(o6pk-G*vJJ$x!*6V{SO3MA}=VbnvnkPyOMl|aWiEl9t_@qJ0!Ol&nL5KqNzI>!4s
z?*GtKswn@FTpn6Wt=!~F;PIPCe{B&_wAw(_a$N@<rX9!;bs$Yl7dm&sgj>t(Trc2w
zIg7<nI!j^g-=oHP&kPAiR}83;)*VZ&pB6zq`skp5EF&WfAkwFfp;afx-Ei}T3i_f~
z)Jk6@%J5cyL=+!5f>m?8ZZCc%2O@^+_<lN*<-}@4eRLEuUX0UHYK&`BYRqJXj@czz
z=qJA=``b_G+&mQHZ!NQNHpM96xzsXW29ldA!>RhODC(jURp@#q5W^`gv+EEYOObd%
z*QJny5XV^7r8@N%yM=0_{~>*r<6<rEKn$ZWP}4FgZzzb}xV5!RUyO#e%ugfX(av-Z
zC)la0<nre`)b16%sl^z;;^+}d)P||lvS-K1aaj~~d!sbWF=<#XE{=sm{Us#BIl~hP
z7RID|Xrp<+089(X!e#$T^iJc+BsO>0^&j&u&d2?667A>4x6~ub33fk#e#{F8`NS>A
zS8<clIzc~qBi*yVxcj5y=NzGr(W2*d5ZK=<wQy_yrz`B;*rx*!-)43sCKsF^n@{5s
ze|GL?G$Vj*Q4DD(JHQ9UE;gV7bi3K!3lP#?R;Q-%$38Z8AfgXs#~%bfh)tUc$NSlB
zg)j|f+s;6&2iSY`O$lKW^iYPfA4wU;uG$J02iaHjc?@U2PD2w8vDXKI`!IWN1^`Fc
z8(ZNaf<5yb)JNIb^maeSPDunjl66T!mYIuU%W6T4X7At{aL3uwzX6P42Pi<CV1-@a
zKFQ912EV7+mKG>av+wCu9?RAU1=|_+*eOVH?6F&LAJ2Lxz<mPy>@<{#YzDoD&$218
z;7nru)gVh|A0GzGIX3c~i2gs%4&4X$7uYJg^|RR=@|(ks?g!KBY}$Nub}l>dFu3#B
z&o{t*gLTP5ptsoxv%sCt7N!7qhuuK$zXJArD-`$HfjV5OhwLL7g_W>NcLDI2txjK^
zCv2xiP?oY?LV&ZEu}=(W#S6C2N3d0}3ypA5$p#@?$Gv3#(xdJbyRZt%*Q|3kq&IB$
zA5r&~^_T|0JGQL`%J=Lqoe}6q_P0;qu42D_LU(;)Gp@q&E4!2~ud8Yg##`K4RT?s*
z+$Pn^>U0NV{>e3NL+_c6Z$|*Lpbov97pl`iy6EY2xc#%O8_pNs?Tv{l-Olw#cY;Nm
zOq#&8?H`9@I~CqRT>ByI;H-m<zGFdbZnoqw*J^as+1%(VJYU*ex{dh)>02GAnco|$
zY@Bu}jotZk9pO#*@e(xR44(bwt=`u^5PMU%p?HSf*gZ6-T*p4ecS7sIYOkQl8`(vj
z@z(QXn;{d$ZDO4};Mv~C_FN3IK=w!lOy03UBN6gvHjl=b>s7x`hoz^g6%vY^eTOP1
z3*t`IcfJTbP!;Zla3fXE{{k>crSb+aLv>d|zKj}g2we?*_1g<!RBy>F(6u@44t>v5
z9Sp~2eFu&|x-G+TGux#GLI`8e&w*_MyKN`hn8jAVju+5tHvhzbU0|2)&I6-Sa6^+?
zJjp>bTdu;_Mcb;o8{S2&XLw<`u?;ODYTK3!Mbp|%eT>&u`?3b;rViRSXhO%?NM>@K
z%;OP9=kTkDql@_z`surzbR4_(r_oKfpPs>e|Kjba9eN`YfsF~GPs|ki$ks5L+jKIB
z{`{!}s+U`kP~}|N8GF$>4>oN*$bDFq6?lKPuN4--Y=sfUQFdzsC{MAu6A^VR>j?e~
z>xe#%b%Y<!I^s`Y9SuliDQfL`*3pm)EVYEjUkoQD(<j0f@fcm<QZ)&&)R=k!Vb`m=
ziclL>pewj0DRt11tuzyHY^U`BszVxH-CWnE%Mnb^HgpwxZ}mV#16tBOGvpFYv_|%G
z2HV&Mo=8@cr)t(GV64@$CC(d^j*{TNSqne7>NLI=ocA`Sp<>AIG=Cl2gr3MXY&ea_
zUD>->*5TH&>gkXI*jXyn?PMo!Mr6C#(KIRuX02F*#;fupiz0;GhL0THbyb9mWJMWH
zqSzNTQ5VaGzCdhe*e9`e(8RG4r8_RN@yLF2DeUV^gqX^1Nkv<7**eo<lE+TG3BNbk
z04&dNkJ#HZg?P*cJci{Hwp(*pzGXM%0sf9X+Z7JqvloJ)+@K1t0ZVsPFD+O+R6n$Z
z(odCw<z~)bbu9$XKNp~?<q4ZG)%;kn9aQPIpfX(5V*-??RKI$_;c3;PwZO-!G?{Rb
zs#14GdoQWx=^$NI{Y;6en<^D0f(lhv>5>(xW)l2?ipfH=AE}nVh4fsdv!c7+sxp?M
zEo;<c@bR~E>(y=R1F>1{69UsM>W%rZ2~f+W@VispzadOR)Ga*WB2?}16N+f{7$oz#
z<LXxPKzdFcJQMKq>KF|E9hbPSGzgdm^~xYN%<O`WZWQkEUtPZi7!Yy&1CPShfWK2|
z{yFG)8B}v#s{VW9RDZt|?QbUj1J;%^DsgO+(i_M2(e*&sDZeqo`_6^#yzU{tLDOpk
z)^E7Jfj=SM0XgenIlQq8j^i%-LH~1&D!7`}m`C8h-yQ>-g=0U0VR6GUv>{$=Z}SUk
z611HT!fB#*{b<x()at2a>DtRS)a7UgZG*GhT1#UvW%Bh`!SWUF+XE)9;z11nUgF3x
zusoqJqVH<F{*eOzUdG;IA^951lmEN-kFlqDP~2u)grO*81KQH}uZaDJK5q9}pEl4w
zU^g7Xm43+bCs6pRdOe1>9jb2U&=!AHHVw1_ROcwIwM!+@iui8T+eQdsuj<?v6#G=S
z3cwPiTJ|%f{i@wqjOPxhHcmjpLsT>OA<C1g5$8~xQgv(wOMA8|;|QY7QMnhvMXu`d
zdjRuP*KPoKQ{_tY{#%Y^IWAviq9nu})hxO}3soIY;W8JgPTYj$J=F<H;@wy2DF^pZ
zb$<;wi&gSnG~$tJIuG}cRk|Oce5z{mCp<h;t;2#RS87+)ZVyD6sxvkZ;GV3$9+j@@
z=!YoW)Ge`dg<Ge-G#mI0YWI%_#$A1q2J_+S0rVsvQpe5(JV))H2I;yws5)5k)X`<|
zdqchNER?s@gJ}|aTRn#I7I)NxXhL3~?z<30k=p)vHt=`Ve_TQFKz(BgI^m)EYB;14
zwI|lMxJPO>9c)k3H_IVCRU2m@rswM4FmvQe)i=p~xjLCLCNI>*B8p1&zUE+gsn!gD
z<!kjMnoYh@s}DhXr~djGEqkx7=nArr>W}s^Aga{0i=q9j{@@JLFKUlPXrZen<s#a<
zR&)JdDA#Lp=nJqx(=H4SJv42eqoEr$y;q?Xn>0(3;Bd3%JsvY|tHw-U>1`VA6X3iw
z+DKS>Ynpq(y|3n0Ls;(6R3C~ue@#wLdjADzYD|Rt-5NF>HhVPLl-%2=2`fMpftq>L
znEe{@9qNKLznlYisK(-jD8e+;FC+SJjf*!Lb4c?ZYqZ=E&APDwL}+Gz2kDqbM|WqW
z#)T3o(VB!_z#Z3Y9|+|MO^Y`&-hU@GyPp9Os~Nfw!JN^A4Fg-erhhc>37XHn(Co9C
z{*7Rgq^X;X7M{~A#ngd2uW6JAz(q}vGonb*T&5A&B~62SP^M|-=E5>vv#1rq&d_wL
zh2n~)a0E=UH075-c1^ROFTQ_Vw&v_EL~~seUJ9FBO;jOTcti7LAZTuC)-?p;wq|uG
zihRusN)i`nawy+hsCmB|G<P)zu{z7$(=??S=tGUR1T4jx+dEM_(i|Fqy2qNR`|$8o
zbG;{&&om2OqA1fW>I6sja!nVk{BjkVVOWUaDmDLjg8P-G9II5^YfW$w>fUNzgaYwS
zv&#c)A2gZcQTI{PArGXVG+WoByFP1Loq@?3u02gUTsieq;M};*zo8S>al6|hv<;lJ
z0A1<MjjIE{8@Zx7z<Juawg%8_=9XdC1Gj|}{)CHdob3f%Z0G#v0O-x})1ma?{z`|5
zALl&|F8n#yPjI-COSuB&F3x#6xc6`g-@$S(7ab0GAlLH}E>jRUW)Mt*xt6qYa)6sv
zM0XJ9<P5iAoc&BZ#6#SKiSTro%WewO2#$?`=~1o`P0}N|(KIoL;#Sea5yKUJ2KNcB
z4t*?7afe>P?`dx1EBHObg;I7njx*65JAq4n4wFRg^)kSdxPL<cPv+uj@O6`GeE`xe
zuAZG{D|fheKLA+31%5>^McjaisJzQ1oQ3i}H|ikp54gRwC{WCu!}bEMgj-H|r^lRM
zM+EbP>rsqA*J$JJpm5ce{Q#w#_6W`G)@fyI7~?i*N6`J`u3bo9kB!=axp3sE-7<p4
z|68;pDSft8dzlhgUfRj@S@YKJNr$H$+T{&_@Y9<75omz6-c$6`PVMvyFxjnbK{>uX
z+Fx(M?=@}hL6EYwbr-=hS6f~VDNpOW2z58L@4EqTOFR1jq<n2Qjoj~OzYG-d{1s|@
z_JCNVeT$6;+&!(Y4bpw>0ZI%#)Q)Y4n2NRA649ndT9;uUeXQ-b9MV&5=}AQROzX7{
zxKgcoE-cHm#te9>(1z1DxKitS9xSi5t8M`IMw^og%lF#;ZiwQ8_S{$GpSVxjRCl!S
zv$oR+;J<2XP_k(aU&NzW%NLcS&W&HHKsv^!kTQ~A{01(f`MQ(f;y6Dk25cwzg!Aa&
zle{-Ar<~?nl|YK++nL}uj&JG<mUw<rb0`z}HMH7xmM{Gob@pWb0Hq7g@d-3^y})0d
z0h^0_dJ2@OeEauMUgGCa!t*lk6%4=W{EzfT&EyNP>yo>|NB4)rtGvvjFRt<P=*yAA
zs|VtOUgrnUjhM&(-37%BeiM!UZ}F2}K)TJZ6actm=LefWQ^22~MSvo{3HDNQcloc_
zWyam-|M>}iAMjBulqI~^K1h%Ff-|6b%1^ybozMGDM^VO`e}uA}-_#hEmHgslMDdbe
zjlGTB8~)GNz`f-=jE2bvK71npANijtllz&sTj=rs!h1|XC$14ZvDc7u6+X}a#Z9PN
zj!4%DMJEu<20>0k;Vv9$3BX3-NHIKl3RT-cx>;E04cr!?);$#4gt|Lmxm{?y8gOr6
zHQgmX!tF~ab_m_pAtpazTQ*`kFEqB(gLgsbFd9Xw;Nc1FCE+ZkeA9((l#a|0@^8b_
z6(Rl$NV9|{7C5{n^q&u9wlMd5uw54x(5x_5*me*sH-$J_Kf5Jhg&z01aPv<n?+Cy9
z!F`eN<TP-1h3f4fJrMprNcq2qLLPCK2y3cP`ABH96Zj{>In21Zr$PgI2R;{iJVRqj
zg`{LeSS~c6T;U7hMq8Lv3Q0epcqvT%g1Xm2HZ4=U5#|qu^1bkUFZH@`kOn<fLhDPA
zJ_&9uK=xG_yO8oPYedg6FkLH-%!JlW{B;Vr*Nb_yxV%9;a}9-u*dZFN*eG6eMKGJh
zMtZo|ET(=ypj*Wu-hgituTzrDOZ<iA!`@=;FtF?p(^|vCPpr&=-vIGlBusXSEoc_9
zN35Mr&);4#1N$1dAaVR-*z6Zi(nRNgm_qNH5b>V^#2qH~rB~WPv6>(14vEdl?_n{l
zA1+gbsHQ>MQL(BHib!#|3fxiRWqN7Gh*Jh4iWB0N*`Pip`o2eTT3oywZMh*1q*sdl
zwirzdH~HeKeBcYjBNtH=iXM~T_pUf-IN0uq)2l)GP+Zpsz+$l}jrAUhHQa!EEWY~*
zq)$b^TmYVlIfJ1r6YKYZNx2vs2dPqAfV?dCQapDP@YiBEEq%NZuk1tJJG<EAIU;>8
zb{K-DRf%KC{U<T<FEs6ocr6j6U&X?Uz`IKO1Atg7CEf-1I_VwFrPfOtdS|;!tMXvt
zA+<~f&Qlut2$q|qaaAzcBC*?HvQ^U2lH7LbDh=+uq~r~#^O5Z4836i9&zAz|CuLTL
zjlVSgC=kb`34cHtBkiX5)k!J05dC#Zx;P#2#!4^#MHFYG@$|&ROOf3GNRT$>pzf^n
z9kxYsNmA}0z|Tp~_Q2D5DRCX7i_(&&0HjDm`@-^)G|EmX{4}Z2D+HA;{k;sN8B*Q^
zNLf<W9XPxyo&Fh!9BD8)ye=6jiag0^g2@f(*RJq%OS)el*Wk8v^KZDgBOR{`%K~Z4
z6PVnU+O&prPl}~{_ycJT&0HT!52-IoB=rPZ;C&>m_=4hz^of>!pGv}h&^(uxr$bpP
zl_M9<l}lN)4)a2)IRk8!Qer&nUP`^A5ZY@g82hlfH`0S2P`sCV(9-b-scaN_tx5`i
z2hLAY4h;~#NJriS@KyR+6G~TkLpJj7+*)}+ZG^u|E}wwP-ST$26ZXpaf5B#-tSdn<
zLGr9Vh+@B7nGE*_<k>XF43Rg`VpW)YRgdDJ+#?w#hvYY{ARU$m(KI1K{;407N98FG
z;XYFCLX)#7IieDE$K`)y8h^&fi)dDOQf@<^-&69lmhc-ZcTYuo&&akyT&H-s<T{E3
zdB-s*ljP8WuuPWqG><zkucI921vx(yQmXv!B6{YM+#nLtW%=0epiY<j)9#Q=`O|7h
zSL8)UAzhWT9zwETlPl@7k|WpQP+XU#AJO_ed14UoH{{{81aV8A?+xj;9NrSZJF-IG
z>jIghnPQO~P3h*lvgR~!_vM_&2<CxY^bfd;W%X`^T_Rtjy#$ZtE_8Q2k%zYj{Fz+6
z7K-O~c|j)1&$1btH@Wr7+22rjEB9!O>7yhCp`pG?9ZK%+P}aXh;iv48z~--Pr{r^h
zGU6HlJCy?L{o!^i36%ZZqh!@U6nm9v`w-JUC5|S+fyzJ%CP)bw4BUQ2X#^=)vA@fJ
zr%=URgCa~(V}lxZNI6I=?1z;x6F`%xB&wjiqWn$o*DR$sJpfmg+Vq;erhMN4MYfVy
zg(63hR-m}9941_@^13dHJjEIFf9{4d5WBOun@S5xTHaF{VrLR}Um0rWF$*qMGH653
z6Q!*SVtcA|)<XGAS-*>VNJ*!BZ>iGg7K$=u>$?9^DRmoZK~X>JEg%i*RiIBA7GFT?
z8x6aUa2r?7LbOd<bc4QW585QqY~o?iHQzzYVl75x!=~lZ-ZcMeRd@!iZT*gVx6M4P
z32|+k*Z^oZ3_k<l+W%Yx(hf5zh>l-qZ$YO~Kf}KB%M7^hQcHvL@BTi9W7h$0aL{cY
zGOS$p8<dmkF@Y9UdTxIWw%)<_aqJUAcVb`H3$W?8Y#yz@_CMYorUMoQAg*COe@4Z`
z0oabu&9U`|%jIwGq6KT&Rg?<f!iKj-v5Vc)8fJlP?rczou=B7J4C@{X=n@`d(;x6a
z<Nu!g#iKCW#6O|e=w@Cjg6l23B_E)zJco}Tw~e<~9zx}IKA-X>Ui?`~;(GJWG#v5a
zj|79!m(QV0!w$aoW+?sm^qR2r=Y=;Y0{90Z=!M<<(uN@2!;kF@WgtI~25~|BzXFQ=
zygzk9Ft4ltSt#$l41h3x{~m;Pkne%<CuY#Rh}9|X5U=Wk;xK=G2BJ8^H(v_B5&Xe=
zAU(=2;87go=h5;=B%e=93Q>IK-%v*L`wWnd^V}aOV)(i`xH!RgwxT%6Yp|!AJH=mG
z0NiQ*R|Xzp`6={)I>T=%r}0l5|7aVciRVWgLBI)oK_FsE<SS{scb5NM4MY+@J`>9G
z{14Pm7x<yIpuEUSH(`>(Kl>iaR6e91TwLP!A3@k@{9OSZdzl{=16&5L9uE(h{Bl~L
zy}}3GMO_vj-kJ7)UFECa1@IbQYz9p>KYt=@a`-m1y(W)eNu)RUdX$>J$ve}=j$3@)
z{;<5wZ>G&r`MkXsEbs6x3(@)lewhI=74ljU$|8R0QxtdkuB*_a_xKhA5zKvldV8=u
z;1?a1aQ{8zXFLH-F(0!Xl_mW7nP}Q0ep>_heay4J!1M`Uu?xjhe&RLs<uiULP3fNV
z?Uw^r%3m6Ux-vey7Nm0CR0{Vmc<p`^75t+-a8~j;l*E6@$Mr-MulO%b5a?^Zl-go{
z!!Nl8hj00cPtd;OJJpBHM}BxQiYh*l_7;BOGs0o|l^^{9q-%s@pP+OVF44Day%0q%
z+=WI5QFsXN4Y2eSGAOIHN!X%A>o*H$PN8m#P~#+ut->zql5N7%N07GLh2Q=Jsh3cH
zFGO$QJbf;Ggi8;A_Z3QMez`-ay#SKG&?F2F1B7Z6+D;(_J7&54LenKEf`u_bi0Ob}
zrQuhI;D?n3E>vhwufs55ZxdY5gTgcpmf=E4L$DkYTq#w0Sg@NYJ9b3ab{RoM2m@$4
z<WZqLZMHfl#4m<Tq|mQ6lu?4=5{hV{8tr2`E<B=<bc|r7E<GVsx`Oniu!p7^r-ZCh
zbmeIwkun^yf-~g=&j^cS;66_HiPiz)g^2M`CI}_=PQWJ$gK21ZR=9o^G)Y1gWf+qM
zT`Ht=LSR35Ixo1>4!sM)5D(N{6gCY+FsZ^6TDrd^M2-Pln(*Zxm|PZG=fFj}aEM-?
z8A94~JXD#&N!qG+Md*45{<4I_6ya52(qFWj?wYVejUroc9Rp7}LNqNxUl)R2!6sK&
z^aDuqg!4^N+z^ILg2_#xb~d<g3D4hy`?fHABZ_>X8SR3+BP^Z=vI1e{dt8b_p^SE3
z6bZsM1bSCEX@mQF!bh4Y-52g9(EQ_pFrTtE4~2hdgGaHjcO6Vigd_!~j|5j5@jMm|
zP&V#~P~HZXPlZ>s;pLei(L%{{;T5eBlnSe9;!q~Mru<I1kV+l<LKwt?vqG3j!;wm1
z$|V3^3ip2l=PRLS5j}seh0VXf^o@`*4$WRGHl|$~{$g7nnC=qKi*UGGw9@j~9<e%p
z9f1i;A9~O26MN7mvp`Ya19*_=G7TpC#g8ii2o}E>!E!*HO50yU#O^fR3l(R~MiC~u
zEkJQlj9Uq~JzQKwkK-XxqSyOjF_fP4BjSfdR2~!K4xzxLhE_A9#34bDqQyOnVRBp?
z(*S;B#AOkXPKd2&o_A8*Hx(?W#6s$s)8a9Dv}48G>rkE%ThogoPE2A@7cZ`$kwb!A
z>_UT^M6u5z1a($iNP8TT#82h0NfuWQM{!Ox)A!)KcrFf>7ew=T6c@!CHxW#VXrNDZ
zs(4j|@{+i}A1u?vRawAY7XPe|E=d=AUBZ2lA!c{Rg~=2%=<9t&Tz3?fS)v^?N!*Fz
z%UncyO&pPk5VOU_-Ek>%#L0hv`?^?3spDMnIb|sF#B48E-ViO6YP%_VbOGrtF|`9M
zZ;Rj4s(HSc{5M$ch}LOP7KjP{Xi}k=HyD5-@n0Hw+!eRy!}6Z^**+QKeKBAkf+`lf
zQ%a^pETrujkHiQ{LOvF!jRWwB7!n7Xr((AsVe(9DL$~E~aV6zKN=1)KNM+)E$~BjZ
zfA$3Kh4?iBMTK~UR^BSb85hu`mtx~gSiTag*Mz^<;@(m_#5ZC?`l!AYr_P7=ov3dH
z#CtJx45SZYB`xlK6jwGz6jkCj%29t3CyYjyd=`E30skV7!p<H{6XU1C{TeB+BP?B|
zh(K_zmHI?M=_Xas#@}^Pmm{!TFEyrt$p*=7F6H0crOHs4dPucTpxGOxZs*|FQ;K^B
zPn)FrwB2j7^!p0*<rc|@Hu!CoqR#@bO&Um<zU|T=TCMVuX46uiw=`=eEPbS5G#>Yp
z7P`WdzvSbCx&Y~?1(0@1?l~xSNre+>|I2RaJdy5^E@2N7w^#aMH;R4IU-aP%l%$F1
z?jY&o5a9PqXa0s1EL}bc7Y8IwN6>^whiM)WD$O2&W`{|>z2Nttw1KvQhf6WEDdUjz
z))x^Tmfq8-{)p7PFT#$HUeI92epG5fbKYap;Xk2`l$MPFFiP5$1}Rz^L|fU9OQUE~
z6C<V3Fz1A{y8_ZlseBwFJSD|aO7gUnPWkItX(dhm&Pbzqz~iJ*|3VorMb8Ikg48Dt
zVJAv=6QDdR#U{Zr$u51OO+Crdqh$2+IjPnHke-+1K9DX*KT)#yqBNJ%(J9hb+Rm3M
z`QTS1m^#n?fFe!GIEr8{OAQZ0N|#QyhKmeo?0UG!k}~NIyef60Wc)R$*9!Dgwsi3d
zICG?~BVc)5vd^ypPr1@uS{TWb3TTt_4QatnIJ_xgQh<j`8fF9VwzOavl=)KJLlk$U
z9*sd$Aa$gvV4>umiN+L3@6rIjD{a-l{XOZ^3YgrNj&DWX11XcX-aeH2x}p)qQuDu{
zERhD-FQL7UBu_0&A4{ia0{=uBcosHKrOj<n_e}Dn4E=Ly+ya=CN@<(WrZTC(g0Raa
zpT8izkm^%WA=NsGKr5vmqQUY~x+NouSJEeX_r8|)&|~yQVri}Ut<<tJ+`p5adC~rp
z_tF9i|ATaU6A&Mz=ovs%Ni*)F?vs@IH<X{HMzm`2MarZ+=T|9W3VLRZ{GEb2SGnOP
zNNeSz_|+BXCJ&&O?mGGORlwKF=P8T6L5_@vUw8Q^B~3kK&lCVQ%J~~<|LJCV*`Gjc
zk>jR;ZL91-*)cEqUm9L{%L{2P=Ob59irr84{Rbxg^1@MwH$a|FS9G_mq3z6j<d?Kh
zcCUPR8;T&g=S;ZRFCV8LKm^M(|3wFd%CB-Dg~^FBJRFpNcG2MZJ1lpgcghiYPA1qQ
z<O4JgJSq<>fax*WiBgi0@<p0MM9EWW*MGG9h0<Eb<+2r^iILO8V0l9R8V#0{aw_c~
zIwdcsY|m-gV<3WwmCr{5a7LbW21T6w`T^?V<$)YH?FsT;+T)Zcf4K<1XXP!A5qFY2
zTm$Z8dG=J?0_SA5IZV&Xi3d=3LFQ;#^rAf91yYK<idKwL<)0%F#U;6S2lPyueCz-K
zm*rDa;67dck@9vK@_@0xWy<OFTE8L(m4G_SF3+Z6-Bnql$LX3pe>Fn9E_bH9Zmv9c
zAc{Qsm!;soA-e^_(@lBO51_dvd+@;Dmba`2JYO!L3C$guq35qa9`-#P7Rsw>_fV1C
zfqs;8SKj;@e(%Yn+k@=BeCiDV4`lmPPXzo>j-=!#5*GadERpkRw(>~sZ~|<P<=eC%
z@<e`i4a%qThado+$uDTi`&^E7L0zfb?*K^4<icDi%jGf0fO{cde+*@XTt=IfDrNl*
zxPK|v_ePhzl26xxzt?g<JLN*($l3Hcdn-?$3;a8Ife$L*%T?_V;s?3bMj$@QbttAP
zxgTwO|0LH5MBQgOl2Sll<k7S*;HzBi8l*Lf`#r#2l@>z*SgSPrgu3-ghz#5YWtIq~
zyHbxXlZTSD0$V`1jY@ZH6yZFTCw*bFNx4UBd7BlM_GfKTn$VPdt5PPzWSdgb7Qt*+
zj_ibcFXhf(;PzJXDJ|urj9LJIuTo0~X@{bwJb<5)`2oTBEB$HpEkGGdKg!stc<cbn
zE+uS~2G8Ga<xpK9_9$E5Lc3SlN2Bk3N-5n}fyyZQbOb5qjBvkSsW}Lp7_5w%4U+@P
zOUmhoDDC^hBvh#zin=hR8Vx=UDyikD3s)*vL3v17^E2EZRxZ>)Oh=TTX%HTv<Y9f#
z&K*@w&^+##Qj4}RMk?K=A&Mv^rxs|Ul{c&5>A2F9#=S90d&=;iP;@qso>q!GK#EmT
zX#wYqviUVg<CODBDB_h?lub!cj=F;-Q5i$4lxLMI$3d2)^m+rbWTnMY^r8KnGBO?)
z{k(FA)@3dzu_36usI(mb7b%KYI1s7IuN_fbQWkv&M4IyP3hFK^y=i!ruI%oBurrjK
zG^@*0jKqCK`FA=jvy{cOGJaL5PK(0Vl<pCTB3o%%5258K`)I5Cb-S|L2Lb0Q5!exj
zWYrBF5I2-dw8QeIqNDHME#>5JIJ~XQ+76R^#Xy6eJIaztD2kNMhY<E%CG`U=?<pzE
zP&`zY(oe~Xm3hrjSEBgSi|vVW`xKN<m7Ax4d!{(k^rB3$7p_5U<;uAn0ADDV#-O1u
z6^|Kk_)7WcSUgm!)63wEvX5R{Z<TyAq<2b78Vr9_B56giN|`hdET5FWXba6}WsM9^
zUz8a%5c{gkln})lT?S=`U3JG&Ag$GXi~-I~_t}09e%I+5wE%v-Zh{vO8+6GudT`gJ
z()-Fo=kylcwo!MQCf}aA+j`V((iv#u*=C&w{UBkBE{^ioTXjQP1HMi7aw^ES>z2^|
zQZHQ%O7?o|;wZ`Bqnp+jCce7)i&5;*73`w?x1TP218Dqp3T3qebo^ixJ9Tbf&{4Z|
z0YSj;*4dI_vPb9F7R6p&%S0&m>6&A^HW#Q{9Rn#yH!>J4+^_qWrh37;-)I5nfbLgH
zn1|@j@MuJ+Zdo5thv|N7fCvxjTvhb^h3lS35D)1J=Kz0L_wPlR9?@kDfigljhAzcX
z-PBH~JEog34Mn7G)N_y?*G+wcx)@zbE5vj{cb+odr*#>$y((7MiefsW3&;jpobDZ6
z?RedZELbM!Dz1Y%QCHFfe`SI@tBdN2o=ws<ase<|H^UR8=X9690&!l~wktec(7EW~
z_oA*HIZV;<G%HKh%{dL+C7q!UiZtEZlPE6hI%WZou3JLM=?q<h3Pq-_q%)$pqRXT2
zW|poCWe2b7mg8^TApfn)NCR88u3I|<m7@#m2E=vUcFHj2>gK1TE>E}J2c|c4!+dbn
zZtDJx0?jSm80yPAy1!}NxIp)Y?yEwbEee4a>F6iW++CeG8<zKUURfv}>Pj~tv|=6S
zNaX6gZh)-ZuIoWR26>^2y9xIdx`Xr`tJG~O0?kWZ^)!&a(oMuh74EgJJ`4OC-J;Lv
z#J9R;jnImBx{7s(;=L}U7H}VQJtz(HQFoQndR4k`nq+;_Eyvzg?z1kHeu?o#x8Vuu
zzUr*_RV=qgZx25SgsVQ*9iG<e=h2e7o8E&GtLyas^fg_t51{1A2L0>VDBSe}j-Y8C
z`dPF$ZlhkN4Jw}cmR?Y9*4rC{WsCk{FK}+vH++fC+osQ(1C#CgZgdNH>0?Kr&RhT2
zpJ<YgKEqBM%zX8}zaW|&dL3mT{PZ(uU#q|V&=5Eb(08KY#!mezPbhckN79d4cI)#S
zgJzGu`c+7K^^<AvzfaGLAPv+XS%R>G^zrnglKuLGYLJ5UYw1Bhpl{g_fDpYO4emnq
z$41zJ2-9~s1nxuntJ6SwSbrx3tvI6he1(`I^fPP2<fuNOIS|M6k0_TNss9uODN1jr
zVNSGuMLe2zT%X(yQN-v=hC(`_kExEZPwMwpA&OJ_e)PpVt$)@J@L2tD+NyL$Z~L9{
zpK<yLltPHt`-$+Ipr3gJ_(XjieN@ltCs8UaNk1zDY{`24Dir7RX1bK;^^0kV_=0{m
z{UG(Ceq|h7r089?0iLR_PP52Mdc!BQEKR@233ZqCl_$`^bp7c50A%R%a39;bOnv7m
z&|cAtw5u~qZwvtGRek+ti1eC%fetZc>rcg^+j8_-9tiZhK6EgYxq8tT$~=7%ZE3lo
zZ+Z>5oB9QLAiJe+NMrbXeM|tNxTBw*2C@Qu1#M?2)VILTNVp>Xhy$>+-_>*dpuMNJ
z-h=6V{ZF*T^nt#5F9h>Y-<lj2>)%Mgm*_{+T==p6p<}T`uWbR7r}}<l0eGe#XaM}V
z-dY=gQvH0&PL%1VQwqFXKaaLxztF#G19*kLac@YK`f=1VFYWrN&Jf?|57O88t$rkZ
zq~7Txs!;h}-+Cwfe$ac+W`mFV7PRTDO5bb(;{K$s9Eq?$>xcM)^ou@k23r4BKQIEt
z8p9_AN;gAS`uW*9!$2B8t~d040!JGRzAh--4XfxUZXO1EExMC78a5Auji=%2pU`eH
z)N2Bp&4yO5L9@j$_X13|8dlMW)yvR^CY9a>QwpN+G1&e@OumNl7l7|D<g`Gu{S05S
zq4YQO!5>`W0u0Xc5XDZz$aoaH41V-p-EH`TN8KL79Xn+y_8QvnhQob^y)WS~&@gX1
zDuWERf8ck&VHEX6u%SMUR1X;X&`!7zLp{1#LJf;V;KB?u`orX)!6yQ^aKrmxC=VI>
zjDY1~gA;9yJYp!L4vH|O|A0muHQYE2lVgSrI{KAmq+yl`VwAxi2p7?YMrQauZs<;n
zDKUm)I}z{+1OEl#pEMXuP@XdQ(PqlihJkc@#2VaV;QoxkdkI+L4ArI}wD@l^oi$|B
zyClgliT2Ya8~&t;&^g1!C2(}!z}KYpuM39vJwbEPFnbHQQw){k;3?HmrzKpZ8D=a2
z@Ur2rW{4u)@Eg56GYm1MkTMOs<AJ+kXg?K}R}C-5L%L>I=Z{XvHq`6_T#lhuEs$L|
zXaf*Mu3-v205=Wc*AVC}!>{-=I(F{1!M7K*`Gzj|n*`h)!>vDIT3|@%kNzq&jHX{~
z7a2~`3f^6VCoPiQGu-(Ff!;Ty(puUB!}xpv9vUvZMVpEZV>w7AhOdKQ`N;4z5Wze)
zWCVlyiD5D=C_XiuD@5Hh!*6s6?avLv-=R&V1{b<_$_zPWD9Q~jvCPQ5FcgVM8dMmz
zP?o*Y(D*H4dTW^MgkatodY8ied&AfYC_fl@>Y$H?q^2ONGQ@91-6zA#-Dufo!-yTI
z`(ijvt1n*-JqWPI*!D0&bF~{M(t^iY;{p8n8P3i4J>AIbjCD$&bT_W1$*hO*k8?n5
zG_IJ7!qYf_2Bn*f&I$mVjSpx@vBfx2jV|44JVZ%~ZN?_4=pb)n{5S;TW8AY8N?&8Z
zYqWlcF$RAQgYz>se~-f7Xn#vvaRQ8Kv{1U!xF!G&cNsU%0qJhzfb*!^W86X8p!OQ;
z(E>n_aWAb~?>F+aWiQw`<um{Xj0a00g&4m(gCf*uZ;oKXjCDK^;Xz}InZSh`6OX{*
zA>$P4(Zj|$U!go=46*aDIcA(ziXzguoPN0*W!x|uE~1UkDBE`2xP@L@F~*zt^E2ED
zV-+pCoHU02ig-^MXC}h(wDDF~n8X^{%Lx07amg;!#Tj?ehMag~%XgqoFfN^in39aW
zG9e`!2c1Lzo--C#QvT(<anc_UFBscYgZqodJ}cli#n^2UxKoWAqEL6qm`Y>BbYnxB
z7G)Txg@HTM82B^Tt{BtbK$&G+avsX7#<Yt7Tr)NskG{w@?wkh?ImRY5BfoB3PHV8a
z#vlWz^NbIZ>G`{5oIu%}+eT|KZ1Rm)X}$A~v40!j3yiO*6AO*oXmPH{xWh57GS;Yz
zhTb#!($x08F@si=9vCqqz;j?+Pe0&%WZXc1vg@(&2K^}QiIKkvz*FOh4yb!(EQta2
zbE7-fN$p&zk=+Z2WyUVY(d=^LdfLD7!kDUoRACI83erkrn>wI*X^eP}#=J6qUIp&g
z##9<!y)(vjKx5t;MViKaFfOD0JRglg34m7_OYpZzxKGBTG)(zy45DxO7h`W40(~`B
z9ED_GYnn?VM>o^7b+B1yI@J=D>rLC~6TQLo18q`rH}#@9fQM<qThwhd{nj0Yr%9lp
z%qG)C%A0OBITb;<#q_`#(st9`KH&5+or*;C-lpVAMB!svMSBi>O=TnDcZX>jZFKa*
z`WyYw&fnyF1vUYuz?;DDH08R({Vvl%8VT(-J--K&eWvC{)CHOtEv{jZ=>+9p_M4W{
zdS|fd?Q2K}Ot)!P7GkQPehxJS(s(S)#8v=z(6oqFD#A^j^mqUcneNi~B*J9>DHGbG
zrnjHbiN{R4>FW|{>O-%sD3dpRF{4diLg3=KsVB`nVoY1sBc>Ckg~4drY18jC28lJT
zqNL6llj}mT#F;|M0gpFnDchD{y6^x}qUm1-F`YHNrvYb@>1i>jlT9n_^Z=YQWf@>|
z-lRBY-6pSJK$B|9c!uJVX%5Zm(oB}taCq6|wi-pc$#f8P8K#G{HkfIOtc%dDnC{b3
zU6!dOErwh*jp_>JHPZxoUtBlEUWAlus-pG&Jd;iZw>M17JJ9^^rfEn&h__5#D4~Aa
zq*(!n`KGB}V7p^lNV^~lOm}`kCl;DYw}Ga}WN85x_e}`~1oOZYycY0>rp+`DD>nT}
zL(LMCM;_phOkQRH9-C^=tN)4VE`4F2nwm4HD>bd1Lcc#MGX>GKs@&9rMrkihe%)YG
zVX96)pQ$u?kAUe*(`_eo+bh$JeYifaP5a{jcw_RYjk>p{jC?qJXTmS1aOaz@Btuzc
z>a`d>^T~8&D{!ApX)93o#S}9c)L%^s3&0xlM(i)MbFSuLl<{0^o<|qf&73<HZCYo}
ztqB+F%>i=}#YVH!Pr!Scn^U%Jlerzu&o`TsUZB`w9=Qhat>$jjP%m=?Wdgj-T_|hp
zV{X?6CcfrV9}&e4vx#18e&#z#Q2LuYeGf8wfO*zmFx_b$)*AR-W{=<CcelCg9N6qJ
z2ho$W*IbVl!uFXvOhaga=1-J|3^M;lTLt%<M?C{+usN8<tq05l>Y$%P%q{Li3N=5a
z&q<j11Pv7rnycMF5pG^Vdz22Dr(6f_u-)9BemHl;yn)j55$3Bd&>l5U8V}$xa|unN
zBh4<fB_YbZhkkb&ZC>&hisR;9^udfVcb^XU3G@EO2=t`cwHn~3%+rShaN4}%5t<Zh
zo<9I}XUww?BkVYHt`C|WZ@%#_iUhO$Zvi%mW_Oxvoiz_{4z?uo!$nXgo6k~C_MF-N
zJ3O5?myCzW1#?GQa=U0=8H!e<m~$wfpKAU*3*48?od!cnGb?Mrec7B{2k>-rtQ!Cs
z=JQ3U%QPROcgYoVjb!vwmiexI6lkuRH~YfHHFL=!AhONxC?A+(zTOEm*UiDRQI~5@
zmEj`KeC7p;8|IK8;BJ~5HAUSm^MF9$ZkxwtK*~4&5D)kr^B<Gox4`^MDJ%=kIrJD7
znYYnK^1J4&I7s)*r|-~2`Mx<~IBXu6f1p+QhvxK2peZ(&RDiU^+=M>AkIZ`s@z}hQ
z_VYb6XU&1-bMsI1Q<YNliVq+yGv8i~qTKwk73yA?wLhS!FsEKavn$PKC<*n_e5e<i
z^vdkk3S_TwBhl|K-<a=RgTuFG!$&xLXC8bIF}*hrp`GL(%zx47;iLKBey~-UYtdKy
zlll2kn0z*`prwW{=4w{>{c1kq__?G-Z@{&4wd6j4<ywnn6mV`9A1nG|on<F}hRLnB
zyrbdZ2Fs5Y8h^T55*^84OY@hY*=R{&0ra$d{|?0_OM?N3VzVW*D`>V@-i(5@)e=eD
zS+-e{Xe-5b%OBM1UY3VF5U981(JB-^mahGv^tI&CFlC3OXExw|mWIUXZ&^og_W(=a
zUP$(xmY2tY*k$QKThDh}zIXhj!D6R3%wEecv?8?6^06yu0xi)rO$f4N(W`X7C2$x3
z!IrnakPcYZQ+q=!>Ik$j)G~ZE`Z>(9<uIg!mYg3Ug<Cq)51bEK+-dFhu;qCP;79D1
zoO^H)VX03mZ$~Z7Xi@T*WlSL0A}!1Hh$71J$bz1UwiqWP(Bqcuvv3$=DPMxVIAOU!
ze<|psrELeeIAsYf0Q|J&bu?VWTE3?w#Tm=YXu#tv-QNNpZ&_0S>IBON%4j88><#Jx
zc-HcglIBU4qptu=ww${K#05+4b098S8XQJwDVAZhp*+=6au>i$7EjuumS*vxkNIWG
z>$AY6TNXD2cZS8{4!@a}6iTgLu}t0!4_TJk9l?3kl93DPnq|OKz_TrL?eqhO9Loxt
zOJBEqybOG<<uct~d6rmu>)o(aHivZ6vThbkZdr0iz~r{27Yz{dE%%)PzhiMJL=*)U
zc^0HXOE7(Ri!6cVi1)4~Xbhx#mPs4n@V@2sct{T{&XkmSXen$*pWk9jBTAB#STbk9
z(<4h3y@DTGLYjc|iG`hqraiU1psmf%EHkG7_}t>HM$<|yGiWPBnI-%HaOIYdG#Pzi
z@y|jO6_&|EAyryN)`aCt%SZZ&%PWgzEsEEctcj?5V-b?+_s4H7Nwo0(&T^~^Oy67j
zw?^^7!q9j3qvd@cm{wWp(UAU=rSVaO|JmX@8YW*XjcG{#)zX@B=4-4~_ffc7|E-RA
z*IHlQ0Km=Kn)ZRMv(7&Y+<NOjD`B$1y6gZ<+^x>}l>hXw-lh@uM(ZCvLF#EeFbFoA
ztlOW#{bs9X2xzug>rx7RtF@3`y4$RNBT;O(eox~-FYBo+uz6d5p92#gYvxLj`C30q
zVA)}f`wJ$1)*oh}pZu+x=%pKAjokptoz^yc(UtZ+)@lU^aj&&rH&pJkmeMU0XmvUU
zDaiVfcERnp`d)-G*!ue`a38S7ZUT3RbrsFsL#^&L!5wCOFcVQ6v_{b^GThpyDf}L?
zw)6t-u+@bI2uG|%wEs84`e$>P9JThQJkv3|b?6m{k=D=jbFwJw1NtaOTT3bDcidWM
zAzZ{*83uJHtZQkcd(wLK8~~@RO`{RaY3mv4nON)3p(xH+Yj;6g;;g%AjUe9oBW33k
ztj;x2BwDrgP@J_ctwfPzokMHf$yWP9O3|LP4(3suw<gl0|AIA-9{-Eh{xYN#Ybw2<
zQmw!CLui+*pX$Rh&3f`AuFqv_I~5w5ZvBPw5gFEp`_QILtED^KU$Jhc)!HoUhh=bh
z)jIG`uw1haK7k_JnoKE{9IM4ngSG3{b44)CwN|x9)AFnykJ0%ztflu+chlO3ekgm(
zs?hZ2w)HQXt>;^N{efWaSX1eD-38X?l$<QIUZ=aP$htHdq20AkrGfoDYg!|?zi%z3
z^{@xl4Vfq&TAv<5pv6}Fm0>ir#CmBuOdnZW(ms~Q*2*i0?TIz>DM+7MH__tyGwbg(
zK6!2(_Z60<R-=qS%dD#20F+x<4lFOMnQjQX!m6qSccnGe87wcYF?7qnwMI<>;GMN-
z2;lFn`O&caV0F%*@#jbDG+HC9vc5kEwolgR9&q^CTG0*C7i$!4<^F1whr`7hn|~=9
z<7%7c0cou*E(|nowiXeP*4b=saIxODfO0b%Y%YO-yW4pB@t=pyZ!DU<(PpB}7M`}7
zchRy<wm;Ho|NUlLU)or)#ny%XBGFb`gEC0lY;81P+irVJX&5itR$8|4wx!Tl$;YOq
zRGP0XbQidH*c!Zmdp}zVJtO`$4_ej^u-T`;(@xtV%DwHf`B9Q^w{1Ax+<R=DT7qn^
zZD%(`Vc%z4oerBo+rwfsG{{zC7b^GLnq;79!L}%RNDkOqQqDcZHih2Zp|*V5A`@nt
zTLjC4wsUb%hTDFlXXKD=O<j08Y%8Tt&Jo+4Gcbv;IpL46b4P7yG%7r1>-Gjkq|KeK
zWR%_ZlpdLA+ljrvAGh7BjaJ0iexD5G30rd=Oi$YOQ;O!4Z7GdtPTLG=V2ibF>IRcD
zwqE^#i?d}dM@;dyXiu0V*gU%ekZ7CqH{fS&k(A&~vaP-ZK(eiEFNAi^HrkH5^ERyi
z0CB<Qy$j+++v9eiNwKY^?`Nt_q)xnKE2JM5rrB;$Ui`AnkA5hgZVREst_)iVt$t?O
z2Au@piftLC*RyO99bj_RR%1GP=9<kT37pxs>EocxvHeQ<qU*M^8=%a!9kM6ECeLQD
zqVkq)<^g!RZ97D%=zQB`8v?##)0d&Hz_!>E?h9>e=0I6wd)ONe@7f~hzPe|7^e=Gt
zZLzeA?Sbv@^@!=Atr}(Li*48D0as%CL_0+v*)%kWer!8@8Ff!=d1W;JdurQ06qV0x
z537Uwx$WkD*p%AxPXSnFOZWwB<+hbH8GT_pM!$}%uw6I<K&35fKWJXs#?Z|AmCf4>
zve!1ZiC}qS%Xb0%t*!2Pz~9+!MI*xZwm@13_+U#~0<w>`{9xLDR%JUy+1O7u1FiIb
zwk6VS{l!+Y4#2Or-ZY0;<J7ewBv+^O@6q11PT?Ej(9J2JF&wUQ>O+};^-g!w;dg^m
zvI{)9J9$zgJe>0A=U^M1a`96a&eLfrE%R)0s(loI%}#$9Y5&U>r_&o@y4C4(0sL-r
z`okMG+nwI);KIx4WiHsfor-Dc*~jVra+vr!nJE#m!zuANlzvX_OTg{#bRY%p1DsYL
zhP2b^A^o|RT~4`GFxl;NW*?&8<CO6|aC@EB(pz?))BHVfWDj)8*P;w^T9^#{ey5YP
z**Mrq=g8|hEu+5&8sb!wQc|H#jXt9Ya~j$fE)F`?F`yOUPGdt5(;=r)cX&GN)SwPb
zjyMgQ4k^N^Q9GC%b;{ok&SOq*i7e77owmD1IeF3aKHBay@+xeOJ1zSWq%lsmXlPG3
zncE|#lTQC1N7o(KW%d2lvSnJPefHjap=G)1SC$RiWoc?=!%?<}W_{R0WN&0CvWEi!
z5kW)&1=%2b3NlncrtIJQeE&MHd(S!VbMEEy+~?kN&VBgU4;mQ^?PG8_lW~kf(H9wJ
z$`NEU#^{85iScSb)N>dIX-UduydVL&%n;KbEsv2v8}uuTd3yckGnUauN3Jp~dqJ)-
zhM4f8fMM;Y>#K!~D2fynF)lSg@jBxO1(9zsR1&m`8Cnm_ObNr8f^Ih%HM`L&Wqf!5
zB4v!%YGI<Bk)MnSu3+%&;94c)u0MEH4D&*GSk3sy0P{7B*C?-B%TS@{aPcih-96~l
zG2XJ$$3yEGt#tRPfl-$TXBruM=^WO?cry^ZX2$oqaIJ;$%1M}LW%#UvVjBac{dn*g
z%5O1U9gN$*L9dgM_8;utX5g5O2aoX=9VWXOuQ)*D4kMcm{XLAMbeQaAe0~55eT)lM
zdj9$u$D$x}moY`LyL*h61R(br_Eds6zz|W`c#tvv8=M(pBtHVh2aK17pfJn`=VF3J
z7*2FH9A&t7fj7o@omP)=#)>r<!~_FhhR1`)cxM%ynPgOw+f$4Zs_L3%EWAh0-wflB
z0NAsP+&RF^F;WvCGtXE<Ssz<w$$#M4F}>)1ygl>w945hmStLixky*_G&xy(Z3uw;F
zAAf*?3)7MZORmiLJFx4<{FzFJk20lM@YkI=OGV_zm>=(jo(D7FZ;F3<GNb4~<i+fw
z@T)g-_kCddFvF>A)|Xk)0G=OHMQ2if<}rFv2QZ(QMrR;%?E**!F<0tfBA6Mp1?nM8
zULH(@F;}Ny5aG-%EVLq+YpDz^l6hqjNEEY@p41b}I0__KPcjWuW)aOSrmE^w%x7tp
zk74f6g2XZlG656E%%po!@ys*_Om_nF{9eE$GFcqxCoy-l!9+4sOV{L6m<}Ewsmwt-
zd7WmyUjdXe%<XcZoMqPj0So7tleEgFF+Vy5f6rT)yMjT}nZYH{$Y2^Lpr6S+^f)YC
zV3yONC5!nMg{>|!PtZ|3n`xjV&Lw7}A4GDPLdx3YGM5#hb(#6XW5CX1M$^9a3e#&l
zTKUWYDz(1KEbxWiHD(g6Xa&qUii;OAt*&pvZV|KU2AJ2G-c&_?gL(H?pcOM&6s0d=
zmNvleo6PPDP%LGZ<iNu+ri(YQ%b8m!Fjm1#eH&g>GMV(vjVk7eU`$sv^XIiNQNwgh
z2CtSm(Ex>8OfD^6b<FGph}1L7t;I0dz*JEDvytgbC#WXoqeoz(nfX->G+LN;*P!3Z
zT$~Q`ZOnC_qSek^NXOm|=5vEU>twpuL+>_oe>N1lm?B!Wx|yF<f_I0xjxM70F!{CM
z^)la~V?rNuMg<G~%*3axpm&+kR{(mCxtWf=_nAMu0_*{1Pd-2gnUxgJ7-HshVJ;pp
zziETyFmvj4_&dUUnRfQ0OdWmjWQ_SN<<G~NNlciSVD9-Cv-XhL|224%%opE-!W8qp
z%}|(To}=W=9P{Tt=>F$C^DLz{ZCNRNn6P7gSpt1~R@zr^&4Cp{XMaal)+69KvEHU=
znKMhY44^J7?N8`*WqDGX$&J-Vm54`KN6R4M&Jxh2!DFl(ssr<2Z4pDnlO>_Zlo!kP
zeOT~j-8o3_KOa{6w=m($s@jV2`mv^HN8-;~n1NOR>oq#z2C`mfW7t8g2VcTqFzZ=t
zTo;G1`sij!D9cZVVIODhpk+3UmB7G2!&&cSfJCqY=$o~XtcxR%jAAvv3B41n9mPO7
z$$D%ChOE)7`7~HM#ro_hNDOPI8Zxo0cd1e!j<x4yka*VZozPEU>1EJJWPNN0pORP`
zY1K+*ea!(ch1J^zlFIU=h}db?VJg=<!`kZx$+Ik@1N6?Zj#Hs(8f)80%+q<+7Bjp^
zx3XraOe2HEr$s1}HT^3FdV#gY187;SjnATWk@fxOXl1kJQb8`UqNwgIht)F+g<RG{
zI!at-?H9vR9;^HfkSnYObYjbA-D-q~S6N>F!ooGyW!iQZuzWo+z(Q6n9UqHW)|*1W
zTxXrx4450N*t;-T%z8Bjoh2;g1T5WTHN^p~lodzgEn_`?4lw1cWfa$|VEq$?Rwe80
zXThstz4$aNRkH#-!K-2IOoCo5%iRZ-Zm|ZPLF!l{3Zd1r9!~~oU~RV2ORAA|kuL8x
zvBK`ad^5}MG|*aDF+annc9!f4yy#&0p=@b!C+kxe@NTnKKZkklVg)>aUN_600&90z
zY+Af}SYJ>HVK2)}Z_z&12<_qfSwTZ+-DPds2cPb-mPUfyXT9NPh4}#%_e1Cpvi`aY
z>><`uyTE+Fnn^+DFiTB02u4^7DabL(YN3?q7;A_EHsh?M9FPgtYf6mwA*+KD%9E^^
zagZt2iz4u*Src@ko?*o$g3Pl1^nkrN)<7ym=2_#Yzr=&b=FxIz$Ihiltv!3ua(Lmu
zK14?WNA|l6c;Up(q1UK0dqpRP=EBZAi%wUzrxl=XYy~AXj<U1zV9=et<q%99WB;}V
z!}ehRxek^**-;ed^<qC*4h!DweMdli*eecE{L`0xmBJ!^>_53c^Ji}e0d@fU*Pqb}
zWM8K%3qkDdy#NhnZ>O&*gs^9Ppb*OLybsXh>=Sg%2xA}k2O{C@Jv7}B?B}n+r$~0t
zi%^JShb#d(!G8Y;cqiFqf5Ln;+dvTy>nXN@0;e%-6|L*B>^ghQMI1Z26ln2mAuU@8
z>?Qw!B(mS8lD;JN`eTqxW*<2W&=mGEidLtxU!u~f(`@~(@cs;2bOxAb*@u2X=Q(!i
zEHKm9VoH6TXRkkrIZS7l+y`ccm2J}j{Y-Xe2bdSwQ@7E|VsnPTyvTl;3iYzt#g9Pa
z68jY063t=npw9s1ve!~Y;br!9DqhHEdr>m-D!Z!$ZeL?h(k-Y0cGDd=Q^;N$0B4HW
z)l?F6o&5wo_cz!dYy@U8+nU@6(Gqt3QMh=MeRLdiS<2q`K3ZjL;T>p{vrT%4R<Kj(
znpq_~N(Y~+*e`a&ZZ*431X9DUqbNfyyE_^_-D2wlAyUWQSq12NwqXnO8rV{b3pBDr
zCZW*8ZvNlilI>%q1*3&MJcZs?_NGmMX=DF=5u)wvr>Nk&gYEburlga7p7K(+*}qZU
zTo=2MHu&A_U!Ozk4qHTd{~q?Pk3f3aX3E|6u{HEntA6%dEpX;8`|v2pJvLhma-Y49
ziopli27fvQ53)n+fHuSqYyf${W^99{VfN`K;MxfL`6_^pvdt^N8)HkT4s)E%dJB$D
zuvsk-dC0aW^-1<cn$jtDG~H>MW~=r1i_Eay-ohYe*`6EGnq&V(cYNmAH|Pvt%Ta_<
z{ihwrlgeo9IZF;;x*a%9UxGMtlIRWZ#QF0R@SHhv`ktx_=Sw5ZyK?T$z<oE)xj?`i
z<w&Sn!ktrDkJd5Hsz1T=;QU50WKT|hJ;1y;OX<zw&FT9Dj{0!?sNl?(^Ywn(fBJED
zc!258nWa*s0M7m8Ac34yIhceXPB#UEf;l@pp%KFIp?6IvCzie{a-1WxLo1A<q+NSB
zr;Y-75u7Jqg4>at58}~^;?&c-;smEK0zRGMoS`*4hEqxkv7BeJ(6YvHlF!5Mc+Tq-
z`AFcTYvD{HXANx>k~q=0Qm{Cglfs8jDV$xj0Ziqr^Fix0r_u)^XE?Lp!L_p-Z3PUT
z<3y69X`Fy5kn@~sdh?`nSahF1gOl+)Ix{(6uZ1%gI9rB6vaFmAO2%B|{B<8_*__vZ
z0L&%MO3KCLaN>+GpUY{dxcX(ztFOSrJkDPYn35};X^NZXbL=sRi?4F#C{uBbvye{R
z1)LSJkSyf*Q<R{H6ZAEB*Ex>0Xx-qPJPqh#&SEMaD&bf^re*6UC(Z;?%JHnk2+KGN
zE<vN5bLa(NS8!hV3%p9sqg2>i#W}Bs-D*yV2_|Yd(G)JO<;2rtc#Ctn2YPj!XXw3I
z&nf+1R*qw$kZ>bs>DwSpoXJ>VHglFzw5x?PWu=X4E9dVMV776t24QB~Iqy-bqJ#5n
z4mvwIug}2lZO$ethU?-Sqw1e-&I>=n?j6o|3otW1oKF+sVK3*^UFhuN)P0Jf^>gf~
zp!Y6kC%tR#akf*<)P0V{g4O`Xo2rBdIo3^d{u|=tN}>3GQ|k<;hB;w$VjSU=vf#`p
zr;GB!V;qqbcE>qIbPAo|JW8dl4>>!wqlNQC6i}ux`EYxh^GGOsn&C7=L1dPr{}O|k
z<Gf)H59c|D96@Zkf7AThajR}n{ii+m!3CIb;L7&HDQ9i~g)?2a%jp2-%B}Q<h8y?j
zEI^NPi(P=`&OJ);mt$O?jnMPpI%R|B$t|Z)v=`Tz=GmK@EQY^6T+KXqzT7}MX8UnB
z({u07O^AVH0C(#;`u<NK_qS&O6U5y~zu91JK@jvqxaI~-LMS)mO*nI$`^_F04C5-C
zArj7gnG!q^-0v>JL?qWX9|}?2_}9>Rf;;~_Oq}GJeu6?YcRz)HPH|tSBAyuTPqc=`
za&OY=5yur3K*1W%-A9}81n%)nj6RXOZ683BxZeMPBy+!^Q+EpYFwJ@@w~2~?PIG&y
zjOGmY=~iH$<u=j2^&GdT4J3`*?*V7db8pZ|F`dhZ07?e8f(~by+_Ur+y}%866CzpM
ziE(&%(aL>DA2Z6vyC2L;T!$y2k;6@$0a`9MhW;>@xdoJV$>TQ7p>>73=117g=VsAz
zca{6=GN4`KK9`3-Qvvs<<p3+>#?fY}h}&uhl<VA`v}d}(?W7{QVs1OV%}Tg4l!my;
zwYGW!rj*-Hw=v4Ne^cJ1oa^ijgB4t^60J(^?6(l9;%ev}SIvEu@_#kldHTRcE%!9d
z^DXXr3U}3U-&_w~J$Ggi)|&=yE1kL<x%q!Uq>0<U7OiHknW9}S+|#Qtv8~)vE8U!J
z<IbkTQakrhJ6avw-OGX9$z4eg$!+f9uYujgZGHm!-Q37ZDE4wEenn>=_t_|rey(H&
zop-t44FcsJmruux``q<(*>r$=fMREZT=O#!8RE`-5AzSW!h>iHb1&!6`)`D6*94hS
z?ui31F~${8J;*q>q8zg~!40_%k%!zrk}--&ZZ_q!r?}Y^#+l~c`wk*A+-GSAHOpN`
z=Yu&epM`mz=Y|{ym@UtD0YvP0A2z}#dtQ0~hUCC|WEWg><Q-o@?>{G=U;&uUym#rp
zgShYx?SqUfue=__jkkI$3?Aj}{R-IbydE$3eT=u3KJVtiiywx9Cold*w7hr>TD81+
zbChWD;Z0A$t}ky<IXeA#O`QPq=lyAhPXWBWw0#Zag`zyzx;TipoHpvgyhvKMLU>6H
z01f4(oWQV;^WJvFV8VDCcfoErkN*v@BY4S07=0u!<rC;d@wQR8>jW>KLJuc-_HV*O
zG%t-3!l!s&&=s;6UMD?NvAkR*pyPODw7|skj(i0@YXZ+&2Nx50y;Pc)#N$(ZJDKO=
z2kaDH6+N4&yf~^$Jk8rqr|vVnv__zv<$X_U$~oSbPr#=%-r)sko#!2)h)X(eWd<x|
z@H(}yl*!vt2i^sq>|5w%@ygqPa*=1CeQUOr*GR#cOT6OcP|V?JDQla{^QQ4$=Kb|C
zczHZEt#em+k5RZQpSOD*{JqMP?nLJ`o`C9%3V8oa!;3=R4tltXc&&r*x0rXK3!Npr
zF)v`=<Y`Z$vy}H4UG*vB9dm?wInVl_0nG|t1eL>7^4|XxqE)<ik3+GVcclUvHN1i;
zcu~t+z5yQI;<?AcL>(`TYEtWYxF?QBjdz-Mm5sbLRp2%8R-cDLGw)eC=(g})q^F{l
zmqiz<+j#dVy57!<pj~hWug)sRm^yiig)n%V_X5?gb@3k1=D(Yl^d5M3cqPAp*TZ|2
zhTY4%MHL2pye7Ia+t2%m${X+U0+&JI9#5))zxR1>1^{J%S3}=y8|3{->*EkFnXZyN
z;Ke@%GR)JT2FeKUx{l68qdeyoKpW$Q*u%s)?=`AEpWwNC1DS`smlQyo<gM$0$Q17;
z?XahLS@a?Q8Qu!2_nGBoe+avCyuIBZ^Sn3SMyD<Rm@5?Q_)S-!V9(E+f`<<Le!7C~
z$gc~5x)Z<YI(>h_ng4q-G+g)zl-F|Q-=G+n8-L?YkfZz`YS8J<7jb}njK3lREf0Q=
z2|Q2!EFJp2_?zg@<juD^2^1gx|2e^~FF(i*#E-x98`$;dJJ5xT06ynD%m?zvZ$dqY
zzh{V^zhHja19%g{XUt>1LitIwYdOw85Qj+!<HyaS70&PZ0vZwg?`Tbk<iGYcNECn3
zQlOpSdp`n8C;89k!+bP9x)dIs;vZgyd5+<C#DW*gkN*k0IDW=zka+$Jw6jj&pA~>-
zP39k^l9d#`7v-l?`Hd96InD2S2y%uWNH^Ke^5e=OdXDe-9u(8~9rG}Mo{!WM9yNXj
zZ9X#iwzTKU<Zq_Wq+Q_mVQ7o9_&pEd%te0S-w?^>Z{C0*UE<px0%i_BMgf#uD?gF8
zE0_6y{0_xD{#&$%xxzPf06U*QKu_#dzK<7L*Z4I9;1%#&cA!<re~~H^iufm)aP&I=
zAYIG3!Oxk6rDFc;6yGl4Kk5h*H~BMZP$=c6TOe7+ujvG4IX|WktqQ)in__pBeD_Z<
zUse3kF7#IOo49bMhF>lPspVhjfQPsEC2wF7>i9EGuv^c6KL~ma{K9D%Y~&xI&_NS_
zA^qf=`BUq`YvFtCfn+OR^C;BY_?<tY)z1G$gjNTC^JOS>@|Retp7}QaXM1RL@lX8(
zgWY`PdvN#;KPd;J=;8lD2ZLU|FYQ74_)~OD@8^G33`=+U2U;O{kH0<u>i79;7XfsD
z@45!9LB7iXM27h7>(F|@zf0l#VZP;UD2(u3X~`eu2mM6*&oTa}2H4|#-y~R?;3v@<
z`jGz@T?(A!KTo&SruemPkeue%QW$iGpHIiJS^jTDFgV9gFM|3!KZH^owu0~>5Ieyd
z+OXOS&isK{a}ex41rbMqo{rg0f&+St+F4NEO8IvefpG_#u7W>kxpWhpq43~QK^=V=
z*In=}y$C!7j|^fIUV^5F;CTxcdjZBrux~B&d<Bj3;Q0wED1_!Oh!2E9fMDkYNT9&>
zAD{#YGU&(^ENJ=%0}K&FQEER_@W}<be|uaoxEE+)f}8i?Vz^+>O29-2f)An<DM+9g
zT9iOQzqu2FYC4La6ny;wTG0Z(Z0Ma5e7PH-F@kdxyN(q^&^{whu(Th%c)<yZT_*^>
z`W#@1f*v}GCkbZ$fZNG}pFM$MO%a$D!o^g<HU%6$E%2ghwljjysodzSU{4Kr=LE0P
zW0)ogNrV1*fr~G&(*@gU)yfdG?1kM-f&Nv1UJyj}LnKRJq6(dhf~YABJ6rH7bzTze
zjDv+7fe&Rkas{96grUn;fz1;bZ=RrX3wo~zHm`(YzF=W5$W?(Wm3&<j_|w*{K=3=&
z)D;Ti>!461c;ZihUKiNWf_y_TNIAM<!66qYln93YMeC*@i(<K@0xkocWr7kaA1xPj
z_d>5i@D1hRDh1X|dQ(>kyy&J=wctJ#D%1%2pNCAXVB}pW-V$u2Wvfmg+z*j@LI2a>
zH3$q3G2TYOrA-iN5@h=Tty%C5)hV<HB2pmIDoCc9fHr~C=NNXoz~O12bO>T>;993(
zADy9Z3(Bl*(C-rL+X`m4U??9Z?g+wP2X>F()=A84ui$NpsPzfh0*Lerx?Y0FUBS@z
z=)5O*Nc;Tz0^d%!JtQcgjM4+aV~?XXELcGkJ0hrf8s<j@p%i}^6MUKp^>M*G6|+qU
zQvX+f_E5m3i0PzYGwm^_1WPG9J}uZwCBQR+h<T7%!8W=iJ|~#`8Dw5izXKw+!uu5Z
zvlBL;LTRzR@N+6jcMv|>3lvBEr%~uR2_K{Fk+X1&N_t#`@6uE3Dh#E-w3~2a&mug3
zM}?gf+I1J^P>|%9a1GtB_7HZ`aobZ^e;$5&31?`&yoJ{&1m`2Hqm8Gp(3`5j{e-JG
z1I=H!&<P3w!bhnrIZ(KyAC`iI|4>3VSXjRbyb$3vN-Bg3>mG;5aUlnfwsmosu#UzQ
zE{u_YL<rZ=su?MCrX@H^I68{f3E^AsfOk@uPGgD|o}_)oDdFO1kQm{9deO%UU!YYh
zPI#YAeDT6O8d8FA4^=HB3cbIDhe^UXI`bq8H$4KB6ydFP@X(qn{EB`Nr-crbYB(dz
z4Tr{Aq4T@2drmk^-`r0VE<mPo@p<7dE8s=CaGwlzGlajMfqtg2<q|Ai5OO|%7g@p%
z1H8B>+)A<fY~fEwVepbLoU&Uv!u2AE<O&BVdURRXOh?*0tFVBoJgx}eJPb?u!o!8o
zzbf2%7%pBDrlkP8K)5Cj`h~)UuY*@4^xO(^UHCcGW!w-JP$goqu;wjbmk9rD1n;IW
zD;2F$;ipb8Q6`+(0F-he`%922q2d_at`?pa!CsBfn(l`&)e5<>P`o8<Yr*L2gmMQk
z>xKVNxVb_2v>v2UxSx({O~N6nvT7E3SHtZV;XljJ*(zLq6Y6ckHVXZ<3mKom`wpS4
z8PJ`=u=P;CEj&m!47-G%Qa-s`SV4E9?g$^ZUVvhcaD-l9y~1}X=H4f4PJ`e5!W;3J
z=expoH}LKWdnTZ9U&t8++JNx=lfWJnz8nUHA>p-eG2RElfqIAx3uh>QFe0pG0%cTK
zMZb$N;d=6ZTzGgVz$S!^zXAH8aDNi*KPQD70x;ew;aA&$JuUR4FzSqu^%68@g)?*_
zm=m^9Twz|=^CQq~MZZxH%TBbi5X4@TLDkp}qJ5OYbre1Ah?bMc_Ir5YEb4p~3NE6R
ztH5&=O}oQGH_`qgU>+4+AEN!IyXfK#Fpr58w59hDjfkP)DOz_K=DkF2blmn9g}Z_H
zh~#_0^A#Phg@T`GSw33+qOE>#EkN|&J8&jYw2E?VK_ZVHm=6}kYy~ewlyVH}p`x`^
z6L(zn^5@`%iF995{x4kQL>2iFBG11d8Yy~*&dX7vC3J>AA-Y}ww3DL#a`2)>z7`lf
zC9=N_kr+`6T|<f$$!KRDC(_e?E?)E*Jyi*!kDdof6uqB;&Lq*)0PH4<&TN1}il~hq
z*i?~*j?&iCqC*q{KO=G~gQc^ge<|#AUer|z{dCbmy5X21vfKs96!q|-e?inn5#B73
z4LxxeMfc}1m)RoEc<?TXR=fw2BN|?W&RkLQez<*EG>`|(JkfsI3||o~eGVjFwD}yy
za@8tY!3Vu2ilh)gfyiDAFA7Efybg^b5s!Y|*F|$ev~GwF1b|m8`hij_C8AV1<=hn2
z-bJfa<o+{wWuisyaIIWq`vO`OqA(r2s1$v<06(%S(a%(-R4wYWfYgXSqPR`1$U68U
z%-<4u(8-`qG)p%`>P0OBU^a+c>D|~U+E0}>O`^T@I5mrM=o^DAqR{ogZWZ1C0^@BH
zZHfhGyU30L7#*S>fB4%eY77JBZBd6BK6Q!wnnAin2X;d5j%XhpJ9|VSR$E~AitbSQ
zq)+taVrcY>-k`A4U6Bt}Qr#2%xE>zf7rAW(Z$R|QvoJ9zDx#-xNK{JYWDi8^mch|s
zQ4mFHMnpNDz#bLtR6%b{H2e%i#zk9-!J81BPJ^L`qHl@-Jt<mq*a|u&>P`lk7MUp;
zGb3_*3Fc=-FHrDoP87Zo<DD0M-U;)z;&HmlX(yf=1e(40N!o-vi1qaMaTE_rF*GM}
zP6ddwxKV`hx`^M$C7;Ev;!BHQ!A<=9v)~;Shk9eW+{FWHDgJUy-2WI1dWfq(0Gg+`
zj!q(8;yab-^cKq!fbApxmX4;rVuv0OKk=C#;8UPDHwdjD@qJo*gT(_;=nN4b?1$T-
z;=PnbJT6YV2=y@W7TTMJi|79jb|b_u%P@#Yaf-(RJbzJQ{TvLQ5HH{Y?WA}imF-1~
z^|ZpA5-%@<XpH#PjX;YPFQcN3II#o8?Bc~0?!ZnEYoj2NDE@95C`sZQ`#_S#AMA%S
zDdIw^{Y@3GyogCSE#}hM?u>YjHmqmG2WaiIo)a5N;8dD;{dOpx7xU;cW4ibiCxB*%
zpP=MIruf4v=)52fdJe5Du}%Z*i(=pBpr0)+q#XGr@fr#n<%nOV;AXBkh&nHe>ztsM
zC*F7;U{}OJR4kk?zVHTkSH+Ji;Mz5-*q>r|1>&U>z%CS@+lN+>c!@1!u8Vy#VCjbV
zD+>P<i<cgP-zDN=3WePi|3k&BrSK5bRVMx*5xjD7{9%}=5TBymS*6(YE+nhOVZTD8
zTAcV9JggDVQUJeJd_V}^EwR;wLc?|9-Spb87r#s!g$A*GHtaTvON21dBz`9X*v;bD
zrRZ!CH`C(RD*l^-lWk(}99U`>J5X}HL;M7NkEm1J{Q#J^#TQ<IUYGb9J^tO|-LJsl
z9r4o>;Pr@q9sx?Pc)<D}XrDNP4q*M_m;K?}UGeC5z`iG5|05Ldi#b)`4Tztln+Jnp
z%}NYrNW7W;^UVWsz8yM;#jb8Z84<^g!ThLr-VtLN6Ca_i$V2gA+Gk9PU!`J=De)Tu
zbWV$7uEMn$aa|(SU(bq%1L4%1IFBNE^Wy3{5L<~a#TxA-e`Y|@UUJeFpbnBp7JxWP
zw&lQ}lcb8i`Q<FxI)cBCizIL{h^wULe~+3(LxInul6uPDxl77l1j;c<^%v;$kXTb8
z=_&d552`=&l8n$N>AWT558;K6<oIcr@Rc|eW1xN#hb`dwOM>Zb8X$Sih*qHF9PJu{
zBwH&18Z5~#1205kqMbpg<VgyTAD1-$3Xw3$>9gR4OP13XGeWYOihv>|{tZBhl1RRw
z{KE;!JCt)iDe+$kPopLO(vRkpq%I7t7|A4k>mgP$-wYBb`GN|n;w9T=;eLXoihcr#
zlCmbWk|a*FP9;mCE76%ENh!oYQzeg5sn}`BPTD7&k?f--^sJ<ngIPN#@hAeOHBF*6
zK>xf%a~lq)OP=jRZ-&I)13qO+_!{V6kXYzAmL)m44%inZp7!8nOG<V_?~<fq4!j(R
z%^HwgiT6_2y)22NTjhBYVF?Ugk-S9bsC>z5w3)psX{Wl;Ym$?nVk`w#$p)$=DwIr7
z@T*9&sT`o!C9lz$>4t>q3Q{cDT>vjiB%3_o_f5&Cv`s0MJe>p3GKqoyOy!b1N_198
z^w$7ZDPjKuuqw$W`f`7@WIaWVYa|ORp-?Ni*$t6flC{5pS0}Oh1j4CC$=~$)ZjxmE
z1JPzlG#z_eB!?dZOsnLp7>u_~@)KQtZkOz(!E{L6e}utK$=kHt-ImNH!HX`*yK0DZ
zOP-^}?~Wvu9=smOM>M0o5+6!u_epGM>F$^KM?vAP<hTEQfAF3pSOw;N$@pi`7?5ny
zfjKCd{s(r4Bz^9fuLqJBRq$z8;`Rv8MkMaEhK@?!ItAXCq>GK#xWxY<e43C*JmKL(
z$)2s4u1U#C+U`$D9FG8VT4JPK!;EA{9_-CZ%HFlYn>mRiy$<IkuIFLGR(ga2fp*e)
zy0T|4{e>!H9i#zN-RvmUQW1iaRC^vRXDM$Q#6=oT!7o>7Vi6SFq`#*@<f!yr3N*P(
zQz@8wOlsVRmWT9h`pJ4qcThgrOZq8`o<DD?f`X$y(sFu@`bu?q7=@p7r45L`G=k#s
z0n!8)@B*dVwD2%U%G(GJgQc(b0xd+ki~gdaQhcEj51usZ1X^LzK`so2OMU(itqAFo
z%`g}#{kaDsQPRT;0d_)~@-*E)Iw{>o%T~1XG9^k+Nng1HyD`!q-o{{JrFrz3yEy6p
zp;TsZyma5sKueImW&>WLv|SCDB<TuDCnQV5Xt7R_ZoLCbsnUWiXq}cWpm^RH>AT0_
z%vtG+b})2Kx{8NZnl!KsW3ir>imlK{mj-M=Z-!L-6}-rl-lRJB3)0;6u#_e3>O<?2
zbeAnG<w$>^ct)<&`W1Y-EWJ<#y*%lE^+35I?W_UGmpcCryH}+)?(p}T)P`Q41=1&N
z0ahrTE`n=C(j#<Z@48i*^)2WP=|!6LV(CFS^h>1Q-UH}OsW%lbl}dl1;7FO&lcIy=
z(#*T?qC)yc5KL4`EtlbMm2?Xadeu^F)$piESJR%WR=S$%S8hq4rVL}9H12EY)k{zL
zK(9gS_#0enlv;x*f!8D*j0Ce;I@Sf47U{ZlFk7W88T8wvf>?;OOVzs|(jj&H-&a4R
zy078PZRsO)Ke|i0^huCz=_CbX??`!ci0zTCY=lCu)QL7yebV=6)#{g~zlM?BmHtS@
ziua`1R=P5Te+z1dNf?kOq{8l?^jr_zACe08LGgifIc<iArB}j$Jt9p$48>7tX*616
z(i^wX8kg!8L2p7j^&P+-N`K*lHz~~sM{7ztode#qbSwj%Gt$=?0GpNWeFVHY>4x=m
z{+pL>Tn2--vON?WwUdQ+pk*&R_$XQqvXEV9Im#a8!9yq6I~PElWf%Xqxs<(0K{HpG
z{{n!z$<&oFaa6YXDGbzI_UjSo9g|(59fgPNnQ;(L*%x$a(@XaHY7lSP{$J?%^O2<;
z2GdvOcOM#lGPVRT{xUvY3lESnlYkZ|dxr_TL9$yEXAYL_e+-f#G9CSrLS<UoWgVA&
zLpNC>WQT5G)+1#NbU!Rg_RA{pPRO31Q|L)q_6kf_wCooh^iIhHU()@f7}+W*dShkG
zV93PD?5@B>yzG}xF!>3xMSl3hCdz_K&`Oe>WW&*9S>BWIFh#bNwsonpHN|M1mhGqi
zBymQTN9Vt@vYgF8IVW3B@s~820|g?^%W^3Dk}ms{B7hmPdOEFJGi5K|0`>)&uoZr1
z$)u~HaZx6h0y|r_^C1jgk|ooDCP%i6&hWXiFX%GIWm)cfu#_h|^b=sN$c{K*^!c(3
zci6ou+cgLEYqD+G&?}JLJOhzJ*^dVRRwR3gwp`a`ZvTs)SY_Mjhg>XM_9n1PWJ#1W
zyD7_RhDNFEKXS25c1RD!a@k`w0IiUvS3;puc9!xyRkGeD@Tz6{U^r7F`zH${td;Gg
zjL<Dv=HuYi$+Tl2^|HzLF~A1dV{BkH%C_~vwI-SM#2qx7Wx*mi)grr2d-7J<F{+Mk
zlO@uryInR`2DA>D@*8M$%D8muzAf{kSX7tnt$ncDElZ)Ao;$LyY1QhHt)PQ$uWa)G
z6#8Ul%9HlXiavzGUD@|E+xKK2s{wsqmSnAm%z$kFM;O|m?58?R!jP>0A9OyD1v`KY
z%XTe-#)#}%HQXPSefv60jLF_u3o<TyoQjPnWcMD0hYw|5^kbWpX$H|bCEL3nK26KM
z5ddXIw)8g0tZazt@@?fg6tb|BzxOdcfA;b%J}~bfe@K-@j`Fbu@WM&Hfexe2a@NPN
z>mr|6fS;GETtep(H~G?|&^s#68ik0vJcVw)9+Q7eXIc-rfxaZ^DQEu#OJ4Fk+Fg0e
ztF}SUN4_K(lD_g-T8sSTEfR`<`pdte`n3SLkRlL)@<%@gOpyG8*Ps|I|3L&^i2S@Q
zh88M+dJ`t`xcqMlm4wNI@&OYre=-`p2>Cv$_lcBeQw>CvJd{q|C*;Gl8$Btnx&dCa
zypd-6l>D1_039RW{~A4ivGSr2fX2yZH$gF8K1Hw51bJB=Mwlpnnl|`J^8Q@#lI5?`
zsXIl!i1JIRay}&$Ps;;nO3%pOItab9^37eqJ}0lD6k(cN6$5f!&a{CS>GJ30(94iV
zU4~?)yocVR)(i694}qN}Kko^ci}KP0Xk^P*P`K-o{QDy?pCcdHh|XO3mHn8+%kp<G
z0VYp=^D1~(<c;)8%9k%10q9k^sQ|5O@}C<4Rv<qR3B5vjE-fiV^22oMzAiVG1LcO?
z_B>j}R{3H&b(hHhGXd?U+-idnmdZb-V_=!Qg-UeF<!|VqQ6X>0fr(1_kwJ)5$-l8c
zq*@-h8+tYJR3*@A<sZ>L?v~u2e!z8dT^pRKm%qY;LW4Y~848W^`s)B|lAl_S&Str_
zhF-%h^3X>B(<&ES1hY-veg`m}atWPjZ_8h!T}zkzz%2B;<<*ony(33q2Oc%~f}bGL
zD^GNWqkVGq4v>DiC)JeRl{-{H;hy{kZJY1QC!4_=kS~aZy+OHQ6GVpOV^+FO^g#ak
zR)`MEYsN5bBl6R9G#-`5{~ySh{KG^T9GCxk8e~Fl3Wnbg<qZ_snw0OL)8v$V=@?L^
z<p&cWG9%Y5hlyFao^Aop$vL|LJui2?0ZCg$808J^6honawpZ|*Xz$~oc<?Ejj*4YG
zXgDd#UxtRW;`dbmby1{K3BRl2DLS6GDITX~>!{)o6Yje!Dia`bOp(O_&qMJT?K(Ua
zzji>xOA+=eh_^!i6nH+0x0XV|SJ4%WN$^v|c>~j5F;__SX8{Vkm!TM_NOXrxkfNX(
z8o`Pse?UJ(kwvf3P{rLo_<dY4OJ~C{Mf)T~!WHdZa63Zr+a7>MD#ZTij8bH7gij|F
zD}I39NrfBj1)>#u#-V;n(eDSz7)8uS=!{i(o}u$!oZ`KU5RF%~)6pqGQFt3B5*16H
zLT8e~=21*gvZAOKBt>DD2wtj!<purIioD%uol*2t5$st-2ZjF5DdKlvXlV*7Whl=p
z?m7cAU6Ef1kqpHbSKx1^qMnWd7Zg5J4ra|#M9)Fvq9S1)&1}VEbd0>D7^DK|9EHmT
z@NyM@QMK@8MFpj|@)VgX0CPq0%SOOlQ&>VV>;lDab}&(>c)J>;ND-U?@2@LtC_!^W
z(OeD8V#VMVpp+=^kL>WIDHJclwNk6%TqrD+Dc+#+fpUe%3(&7nL=503RH?9Qhlwi1
zS^8a7E6z~#xJF?O08FhSkiL?4OQAXj6LpHW==xy2qU|Z@H7EjG!E03bQedk|@#F9C
zuvxKBh6!p>WWNYrt0IIRjy8q0-wI~C;voHkI~1~B^mZzaJitJ2D@v!(>QV@|fpjbK
z>02vz6#4&x^eAFzSJ|t0jq*!<iWRLO{fZ5A>b|R(rR~u@h5a|^ysubz03Hq~wr+s;
zgNlQciy2a6(N6V&!of;~l*0-G6^@Q5zNc60sN&^R=#MG#>GMzH3iEZ0VnPv18={Ab
z@47)I72nfpIi;w30@%}vRgqAbQGB)utyzWJ+wgZzq5lxAc}37BNZKkLUIMh8GJOaw
zd*zzr;5jJQ{bt2L9hEusK5<g!QmvP>QXmC!QGW0*{%WquCznCdO(}jKc8@B1=&GN)
zGVcaj$CN)%KH5XMY8%izmB(mn?4|sdPKw^j1^3bNQLd&4g0FHN#m@YcF?WIKuUtWu
zG6BkwB+9=BD$Q;9s|6{;kHb>1vZ)Dwkr1V^8la)d<2#{oT)CV!|6$4vbp0?~iEIxZ
zJmv6FkVs|X1S~}<^>h{NgtD1J04J4ZN|{9~-;M__RvB{`C~?Y_23Uw!`W65>LHSe<
zJ%5SHEk=wYN%@{DWRjJ9+RCITSBPOSRT&%)jnm4*j?g%xWYRJJta1gN;m;|5uEWsM
zlx5u@=amB5;-)L#pjTanawH5WnaX;KTwG8dI1FBvvVy+&a#6X<3A}9Oe^ioZy`<Fp
zg61ek=|zyMyhD4v%Ss-7?JiF_NRxj>DLV|3uYC7$cyU$v^>LtGQ(A7qivp#Z3cd@K
zZFE_tNXeot%yp%06fE6Px@rMdtnBrL!4jpF{-8INaSc!?ReDySRc2Mz(_XP$`BE@6
zDwGX0mz7F2*{xD4=-VaLO8gsZJb23KEJ)TW#dC1&mNI$?cy-DTF2ehIWkM1L+Mw)_
zz*3_!=@0Ollt*`f*Q{Jmk4lSDNEa7cm1pQ6)24iS5fs{$R@NensY6*qp|nn=dKA64
zmDZDx=~9l^!(g}4i;fF-lp!0T-=jQefTO+2q^~g0KIO;s5s!YQJ8k*yDph=#zo&Gi
zQ_g+mTlDrHP%5^=nL*`;wcrgYqdta(2g)5*kYVNb)|Ws>l<R4aIjZdI2N_eoLEoks
zSMH`qW<nW5uh@sm?|%l`r1G(QfSFPj#KN^{<@1$LpHUt&!>3uL@jNWeDR;dFGOv6@
zk4{^a@DsG`REwU2g1zcC-M(^A4KqO;Rncqd{pX|_%?8s|Wj6y$ZmJr}gCAA>Yec8J
z%7rRpkEsL{o%c{Je-$lHRV<akc&Y5^*X^y!(87d|>e*6=_^PI2(ehK-HiGA`x<S=D
z0V-!I{0vlOxWL~a)v`aq3s%K?(EYy<l{?)F4^_410`$0Q^)Db{s^1@C^x>-RM4&~e
zEDZdTB30pZoi9oiNhgXEs*b17I;ry71%+tUN=h!AQZXpI9iuwOfZbTtrj2ODsV0X(
z;#EJ~0%n3LnW_{MRXI2$Sr;d%rs#B*tWwcEgcOzcMS!NNhO5y!t@@`2tuv~S5TKn^
zt)qC;Io09_%vzdi(KK8;ud1Xxc)IEjiZy1alBupEQ+1#a>K9a>JPw0dss<BU7gbdv
zsAsEwrG4BbmDvX^YmUmFLXNpA8NC%Rt9DV{K%Q#kS!i5QO|j9L4{WrqsxHxQ{hDfC
z3cCfW!%AQmsuJjkS)}ry5bJgP388*N^?MYsi&gI|f=G$#$aYN7O;zS+;FYRO>!DDl
za?b~^+^YI+37QqE2#RG@s{YHyL{+JhUxkTk)n%$ntWnL3K)+VCjb4hkRED=<sZMq1
zHbzmedLj%84XPKOhQUTvoDrQ(s`|^2Y*vN6fL4pDYbRQ*Do6TIMw_bk07$#){2J(W
zsI0%xo}g1TegKnjTjg^Ty<Mtgx;NFWS{(!PcT}HmfHOTRM<LMqRl|Qn<gO|r2_pAY
zv5ByIU$toxtpQc&I79|j{gja%Qtf^f&<|8sY3nttvZJHrh{_=l>Z7X2Q0R@RUa-D{
z=D6zr=ruT@3KC+59;!IYF*TE_Z7*ZkQ>snNz?)W8QW|1Lr3nJ|tg3xAI_FgRJ{Zir
z>W@KqXsd3exPYDd4N73!tJU=QI;huCy@8|pDlOJd>R*pS!CB35fx3(Og+MEqu4?1w
z0CiK><bWJi?|cbNcQwl&?jKVRvf;jm`ulnCJk`GR-*UXv1`AAhtKX%=ijR7i0~CDK
zp}XLPpZc*Ku;j1)k5bP8>H`^24^+Rm4C+DZFiI^3s|%T!ix9Q4l=6R}YD*NnIIg}l
z2K_L#1ML;V)hpZ3icnX6gjS^5=~=);sh^}}>xBBxbI?DjW>9HQw7QU@45!q4=}a1<
zev`I2v1-Lxn2%H6>P9PGZAa0C1obYu2b8Ezpob$#eGp5qb#b!#5f%oTqBc|9Csl2x
zJ?d%ogL;rN>Y0DRJFEWmF0jw3w=Bd!)71ac=V#8V-yyft)!$N`LWcU#0VrgupV<!V
z3u@aDkSz5b4*b2SzCp>zY_+cj3YXL^1DL!VbtB!_v*xP*q}=aiweQD($y0mMM&XM3
z>Jw1RS6BGKr>kn=i@?67zA%H%0`<!Qn8ZT$0y-TPsVidO;dQmsDAaGLzxP4wrh3JF
zv`W>F(^FBV?)VyZ%hi(q1F29aoPvc)b*lj)RaW(HbeE)BZ5IsC8g&*$;%e1vTR?89
z6H$D)xK7<u08i`HnwMa(LA~;6C^V|;=pJm7`XBl}WV8C0XTWPwZ}<>HYgIo%_ut#p
z>Cb_*tH%bw>rgxF##lPlk2nGIw)!7BM|G*KVO{X1TU|m2-8<@WssQOxTebnaSMB&8
z6#LX%+SK-|k4!=Tu6lyL6L3%6k%Xb$S0~cZbU+<h4YWb^D>Tp{^#Te#JWy*WSTL;C
zGk`LpzC)|ls5+G{i;k)5TG1L;@3FoM#R>I)f53}}>NlyVZBl)Mg6&gkACj3?uaAYu
zjCxl-U}n{qUIO-<dX%1+dG$xX0?k%4K|vim&7&-++iTX)fzd%zKoMR?&965xGAGR&
zwCQoyq)}aki)PoqaNAY$poD(UZW;-_7mjKUQToJP<79`{G0mHF8_7fSCB2h9HBT-E
z@zUhALEl?b779x~nw5hv@2mNmPMUt2Ng9j4Cg~I;12kb2p$*imu7&v^4TE-*!J1RQ
zgM?^~Tmmmt^XW76{2kXkN(sj>4VPlc;hMGdA)^S*8Y=FL)U1$z7o~9?L+gZQBLgN*
zYW!%?jMiKg!_q0uyT60PX!ZudwOGv*y^P~Df6)#*UUQeCPYIe2=+&I4=}LxrlE#*9
zx20*iKA`V^p4Y_sVxZ}oH#=Y{OEZbA#NvyZO8Tv5YZlNKMJ{U&P>>@}^A#0oUD3Ql
zm2M@P5(=}GYVv-ENSS62WfjUb_4Mnm(B#qIr&7~?8_-pn*C;Sut=U6I=^D)rI*`<A
z;whkJt<!Ay45IZKj~L8lgXR_;jT<#zQfWbx=B+2N+%;<+y${h=&EIjb)TU`J#F*MO
z3sW&A9h!@D^y$?26rt6nd5M;mZp|=#df|>H%pYJqnjh)PL9gZof2j9qYH0HMH8*^r
zaL=l7p@sRrMn=K20Zm~Fn1h=CGoW)w^L#n{exT{Q2;Q*fA#J8dG<^CcjcU^Jz#G%p
zpGRw4vzcB56PjIHVE3V>OA4PRHTJYop3(>@ur;Guu@2C)nhz+yI;UB)5RT4ktS+N~
zvDNOTdvSK!LJCAUXb+deZ%1t|ooSu47K*(&YuCGixM&ab0n|+^+6n!m+P7)H?XFFt
zE6K;SN4h~gv;%Yi^VFVc0?$jk<syiWHimKpzS`MJ81mD0{{U!z?f2H(Fdv|`_JIUy
z_w9lEA=*czuoSA@NQaK&+FJS{hG`A|f)}oxrs!3KRzC`ILYte1p`Fw+sKPE<d+#%J
z#%c``coC<)y$ZZ|t=11DNgH<y29vb~hhRQMtGNNmGuorWbpAW5{gIAU=d@y~RY})M
zsfs*9YfH7xnOdt7t&7@#TW~*H>--0Nx}?qU1lnb7Tp{%Gv=Q&X`zzWPo<J*KdpRBk
zuWCDKLvu|VNxy_5?N?M0cwOsUg4PY~U>bPE+Q%{;$MaXB9iji?dsFLApD-!cuB57^
z3at;tAuF|A6jH9z?$yD3wRVD14K><?kI|~reob`__1cKV5NXg3XTe0XwpReK7VXFP
z@tbMY&QJwMhjv^JgPqz5cSzpWJ{*Bwm-bo>{r}Bw?aO;G&^y{s=%qTKU6l{JgW6pc
zkQvgxO`(Se+RY`fJFLB`0B=MaM{(v+?Q+@`j%kn3(PvyMpvj-muE~bTL+x!^dndJ?
zA46nHyPOv5Y3(8k-OXqZQqX!<JGK%QtaI9fR0ut<RXd{BRyXz^X4XzOK8sF!-8I^7
zIOx280h*&uPSw6nx&vJpjI*xeEp)o*e!7M+x$1T=hb1@Ndwan<s{5Yqv$^Z8C!uvr
z_xU}T_s}^-0NPWxg)DgKvP^K)*Q)!9@|}LV)wEjs>pE*Nm;l|mNRU9C;2wBEx(_IY
z6|6h<H4KL6WE2Sx)!ko@R=BRT298GPPHzE;)Gf}1hfzBHH0I)ju2Kn<le+MHcoD60
z%m&yg-IrAU7Nh&?9bm@ltcU1hLvgxTDoBpkjVUmS1l@glC=+!*!~rHr_W`|4Q*<n<
zX-(Cgq6@UAb>{!osq1{`#@<<-8-3sBobIDX0hX>?<pq=sosR*SnYu74Exn)%Rf3nL
z%f+F8@kN~<B}%e&>#ZNc#Y?*PY2%rrJC%z$$<-y`hq3sw?pp(3@^l|)F<)17=U#z{
zeBI$gnAxkkfJBf2-6={zUDsvPY5j)o?J}Sg>y(MWEYZD}0EL^n&~mg&b<47#P^SB&
z8_?ytrZ2#&(1pE8`S(iQZ?xB|()n~kzgm|g0jbf2Zvd&)JwcI#TRQvQn6?I;@+zEZ
z)Ctc4tx5Mb#VDI~s}=*aMHey$f7^8lv`OpG9i}&Jr|x;$(A?HNPcOwT-8WPd-mUvq
z1(7?t`3B1W_2?XIF{Qn_6=$K*r<<inZNF~C1Um2PE-itHdl)F@>%Q(^T3-irUaz3@
zf$k?WoEg=X{ckU?`<Mcd<GPp1!JE)&+o14JH}@YVXi}F#b$U}e?oZ%N>kiRMJfo{T
zPy5eV-KXEc(wy#AJ9_7JxwJ2{*WdgN#6h1K4}*?+6IE0=>Ddktan@&1^43M4M^SQD
z{p}L~b<=MT#|V$=zof;>UB83wcOKI({}L?^{hnf|d+W34#pk1sJ_9{p{az~Fu=?p&
zQ3;~IepLoQ1N2KMb{?#M8gb*rA^OpFxF4$j<^W)h>ph=^ewaSq4V~e7wjE4F=~F25
za6&&|g%>CFZru=x)|Xv}!BhI!R<vUDcTWH_R)0^9R-AtO3s8vHJAVL$1gn0Us^$~*
z5hpO-B>nD{P)yUOegv8G`sdHUr*wTO#p5&dd+9q8nfgQ@pk2^kPs5aE>DO07@1maH
z0Fi9{#h2msC4K2WkQ}{nFG#NbYuW@{*4M_Nm8T!3I~iB>A@obg*IS>V3&U6SeYB)q
z(;x7Mi2{8>5IPI>t+ezP={HjR^SXY`=dg4`&!R(8u|AWQ_Y!^Ew*bAVXa5b!QoV|5
z0L%29^k**Do9uyEp=ZQ{SE)Z&4pOE6<qcS<*8krm^lJ16tq~Y~t^RK#yt$=cKw<7W
z{Y?|F>-FEh0Z$wBx<Z(5)b~;5ph<s(&OFWf5)njN^zZ)*y;l8pS|;1{vSkoy*U!^-
zqeFk(6P7ylZghL<w*J5;Xm#nIrPE-yUPvjVJ9>5+#b0{#ZVSQe)f=f0q)-1$1v>ln
zYiFT&SN}^2$UXhfe?jBE{?ASDX+Zy-5v@UeYZoMk^#7fO$OHYmsApb0tY>tCjOcqQ
z&OEALL8Z83`ZJ5+@3?*`#W5!IJwHI<q5k<&`u`7;`leopPU+Jqkv*#~eG;N`dZ7dZ
zo!6JqN!8wPfz~Mp!)7XKb2Pm97>JXhYZM~Rh8kM@TnuVAfVvv)a4`rsLmv|ZJ!&}o
zHT2vK%lHsEW>D;ef`=h!I}CXmKEwgcy4cI`H*Imf4Jouo^)W2{9U8udUH$OF&)`pM
zk-s7A0LB|+u%$G7uwnfPm=7@|tDq2SaLt9}aYGG#8aT|bnyz1j8&X%GGr~}M5F(L=
zYcc4IGRP?@al&x)b%32T$ZWy0MjKA@z&vI6fU+4ehWOQB#u`#+!y9L)G5|Euu#JjQ
zlMH{;x}0o?r=>r|aBB-jk!pyVg~(|`{tFny8G|byl4lKJD6Lz3&Tz^VB58&Lbf7qI
z*wqX5bi=*9Xk{24dl{0MR)b;%=H!Cmj~V!uWw=c{sf&iE$IzK=U{l87l3_tTuyYK-
zLim(xIPfj}y=;h}w`rcCgkm#S3~P%)@(mjj;o4Qh);j22Gfeydg9V0{s207@Q2Yf9
z78$lv-s8GqHHA@b7_1*e!2M#wdtX4m#IP<3=5HEOF9EyM&_-wYGDE~7Xp|eYv?Z@F
z)PzH^(jbk5UX@{>9K31+V+;ms3{3(k)EcyO8oXsN(gvf>@S*~w-tanwh8heTVu8|V
z2>KKDnhblaRG`#ssC)uwEe0WFN?HxuC^Xe(_-hbo?S^35)^!;CD9X@jSVDD}w+#>1
zV!FBvS~`q&8xHQmAFbEmNRNM?L45%x`VDQguHH3lm!Wmf(Dg4`_YLbRp*~=^Ok4Ru
zgXlxbzYiJA7N9*aOcaATZ1^<<4v!c-=#t*3q3{?K#|#MzVSe0T69Nw>49h*C_t0>;
z1D%tG19VK7GCZI~XxiY`i`I<c;BwfVHT1MWWX|y97l58OBszfD8kPRQv@<^CPWK<|
zjqhGYuY)oDLl|^49;OluCu2@O^qq|vR{`o`95@8KuExaYz;iS9^~3y8V@e#b-Hj`E
zfE+WjU%{9>jL*@`cpB3;L*2{R`z@UDHr7*|$;bG@>#*x<{QOD$Dg2CY6wvw4-`Mjf
z6a$QZFGX*lv4Wy8K}Oq8VItW0Gr1OGY#%`@)ENB%M2;I@$w6nB@$(D74mU0dhxrKO
zD`g;&#{GL>KFVmwhrcI`kw1Z)G`3SZJKDHp1r%b9ZnWczGZxZQVU0J6a^YKoaoHDW
zCK^?8$RrsbqYPTIG4m6MrWk8?qLpea+5ni-#=&Gro-w9VhUKjBBrWLYjN5C_nP%)5
zMdx|rVih{mjV+roqZ!6$snjLY_=6s!zhFGR7anFA4ND+$(Q3R-Gn;MPV}=)(jGyJg
zV2;sR55-)gD}6HXveB&;!_G5)y&2?+ar_h{^NlT(PQPmWjP_O6j9Z=pufXVW9i4^7
zOo}iS8NW*e%5|gP$1r%q7(;QUVq*a%N=l6N8z6GiXuU*-{!(KyE$C&&hYDzv8@K<C
zR)tY#1DQ%=PBmIp#;dfKs5U;JFJ#mhpV6SR)>ya#<d(6Vf)sVeU(%pZZ#+-;SR0Ja
zRKMA1d~+V8$+&n0>^2((RM*>L415=J(Q1@fOF`R=I=WQRZtM;R=`gOM&lPkT+4RQi
zHgbYt;*RmtNjTbL9HwfTUgM#)knA%iQbxAlc!mN#ca6W?1-WNzn!%LZH@a?vPXor~
zbTS?^j;#h6GDgy2<AKpU2}g&GjB^x!88L39=V;V8e+7Pz8GoQ^#c|^iS|TQl%k4oP
z8h26o&ZM#GE08JUy$=C1ZQSjJ){OBh14L$xY0m>?&Ul4Nw&sl;w9B$JNwo0S&U9!3
z=Iu={vtZA`RI>wmj;5TARR7{+nsJ7xv+4ao*mW@pJ_n4eY3~I%<7R420q>}(B_4|I
zCUH8@j+wTTc@I;23t&7=zx@maFH`JwjMv*#>jCpVrX%O!lds7?4V`|bDk_chH(lld
zEWq^478nXNdH+P;UkWl!bI==XD)IvfF$L0%&QQ|?{hf}RHtq&mn8}x}ZH1erZbKx(
zG|T{Kq-k~)U{0F0cYzme`XUkJlxZ*h5aUcg(#|~IbR`Os38wT_@Hg4?+gsqJn7Rbe
zOErD&0R?NOsmTSFE|{d0OU*KEqJZl~lYcWTWt;M-SnHChiVjIRrj_)<%{58sO?lb0
zlakbVroX8w^NOkQ30TTEO;Y*jRZ|<4K3+2|q#R#?=^kz13QaH5ajMAF`Y&9&ZrV}|
zksDUiou?sFY&yIeFeRp^DRzF-bchPgOHE6^gTXS>->V@~Zqh7<Vuk5X2^1?$Y)S`I
znOY{{eYL5q4bIe<<lbo2nqFN3lv}3xOK8=ZLiT{vn?BBiLWAjBy3E^XI^qD#CX@C5
zh}mp9PLEoPsfX_Dw3_}30%<cXp*TvrX=W?N)L}}elV+z$dlZVdO;yJM(`BmmMyuO&
z>m<CtW9p=<qdlfSGQsOLc}4@J&*VpWo_^D&QFwpXbTa|1d!~Ukn6CRKi<L5H1E&0F
z=ntBf%)-SX(=43<9+>u0ByQMrgl>3@m~3hPI%>Ll4%lNRXZkabn|3|}v<Xvu3M@S|
z1q;!dG<8wA-;}Ar6V6PVa{mOGGdX6$(Rq`<H=u3JV%l5UnMH$EOt8JV<}}b8%-zlC
zbu_y!gh3~B{+rNnHh2F5P#3d|R$^Ck#yMDWGf&go@Tj>c2WakQ#vBYDGt22#f`@qx
z<-9!2N9Z8rWq#rjKzo~?`VHzn=Km;G?`!6J!-AjL|1FAt`kPID5DhTr^I<8_JVVLB
zAoEo#L_^KR^y)ZnuAc>Vn0fFCz=WGOo&hhyY*zpeBh4r5ArfW2E{Dho^VB5FpEPF@
zO0@ac-GDx2-jN1JW6Z6T_m4GmsJt-F9JigmKM`-<c^VoC=5o4zpJ*0S1S84ZOwUTP
z`Mqs`Ninad`oL84D1C47v^huy_s^I^xllN3eu=KZpEIv;M=Q<zK{1>;Z}t>pO47{_
z>(I(D`~3yIO!L=VkPBv<9`U4^|M(QddeJPSkBVlS1BXE_nSJO?n`2H}3G=z;FQ0~|
zm(AmK=*%;3qa*bd^8q!m^UcfX*2q=!87dvVW?r-#gD5bouK}gdJoO6f7MbzoLOg2b
z3G(TNxwsd+Vsj@YPfN^R?*Z(l)%+Iy?Muyxlu;@(vp1ksZVm{BVug9V4(2P(EjAco
zmHEe&@S@t>eh~UK=8+d+u-3epQuMdXY$MR>%&&fi&U*8w^!I5nUkL?DqxoM-i8h%(
zABJAD`6+tiw3rVz!BDH&YDbZT4)X~g$aI>&$brGz=B|4fT9<iuD)hU}E2`nz9dk0>
z<?1o#QAK^PIqy~I_nFmnQKR4Nz6<Ji&8zaDaL-&vb*J~u_4L;oFb^#R*r0hARpt$u
z4=e@mftgQ{!(sFD*2lpdF}DwZjGA*Yfi`AF0vZpOxtJ<zC(K*vmoQ~s|0eXO&1)$c
zGGo4U7cjHt@?(&kGcQ^I*XGUdQINyd;!XdI(9SYQwU+jl21-adSUhO&;%GVa7^cg~
zVoT{IXUhh6I<>o4zM<cTtL0c8%)42tDW-JPa*Lt`?v~iUAacy|dlp9MVL9|G&^#@l
z(E-lOGDO~cTf!-R>0=q{MW?T2avS{hvoLA*>~AUNp%q|>Oam{_@(JDF3$palQWk94
z*F^iz5KH4L=nb_rQJng?rSUDa!YsA4dWBm`=`9gqIZqqjNQ;?rl2Mix7qm`TzPbVI
zla`#@=!~}P`T+{3EH0Gajj<%W46s<sT1ryKSqkGJ5^u3m?L~s6hvK}6mWgKCe<oR0
z(q->t%Z5+Tn_{`c19qxqs2lpHEgyb}))~vbD-bzrIeY>7=Pb|AH?-0$3ul3S-g5YP
zc#&?|PqDKMi<A;2nU*7SP`_XiP&_@$@-HPyE?NRU!~AAjHc+L^B}-QwP^>wYt^Q!<
zTE@N5d&MH6gMGfG=L@v1TD}uO|C%NHX^0e9ys3(y&=O8pgNrPY6dt&4aij9L8<rXh
zx)obWC>>s6`HJc?Zd%glomy)7#seZ{mY{dgD!16uDo|lb+z1PmR!h-`7)6z39VNS}
zE%FnvRAbrvF+^)EAJTsAmL;Vdq|Q?OI!0J;`G6wY4VI|&&}+23NH3Bm%h!}xYPR@z
z0lUR={2F+zmZTS8x6Set?bF*W*)r&LSP~wALZ@ZC9Uk7cShFc?++|rqN3L$m^+1q2
z7HK~edn`$GdhWF(SKznPXSqx-?0$=*1`2mASD%E3_bgj!dv)I;=mQzB{6Hb_LCb&(
zcte)g!$BTcqSpXr*y2SWQ5>;2Yy}y$xQJnB%<`i3Dip^pUduoxEKfv&`OxCdgvO-h
zHoaY@EUTUbnYN6~gEwROk}`#}mgzZk&RLFc1<btVyOmI|wJD^(ubs{Bv})Pg*w;eA
z!KSDSEk~Or9&p>qX1O~Ix!U~m8amx<9`3b5=BUkTO2E0>utP8>$87G=hfq9hqW(e4
z)5dKVrqs(Olj`-nZC;?-G#{It^jS<_n=jX*)6eE9s)X{l5kz400XCmdJ#nDTJcSN|
zY|4f~f^B}JKy8Rk812PFZG31cJ8o0EmA=0lW>azs2E%Q3GJzdov+s5I6lwGLdcZ{4
zL>`3337dDmfTfc*7OGv0wwa|9?kO9c9a=Fq`SkOOwYk{}y*Qi86e*3j*+Lo01e+a{
zC`q(=fj*X(Wb^4JfF;{JN7p4&Y<#a%{vp+7CG81L+w7Tu;u)LG5`dny@eaT|pR-X>
zJU-1PdMSA4|DU5PkL&sV<FjGE*=#c##%wdjPG;ZxzVF-EFq>m$b}+^^#(aw;QFKVB
ziXw$nbn4W7NTt$Ek`7Y3==?oj>z~)-^?tvu_xt-fUf25*<BcU)#Z?BMT0i0$dMW@U
zFh-kTXd=V>JqD8)35{4wGQ(#A>`h_3p~T!Z#>$((QW=j!Fqg(y@f231GpZ?suxBtV
zI;hWNY~_O{ixK@MIIc4aJ3y1okbMk}9L9sMu$Wv%&>%SS7@SR5Og^JH6AT56O?1f?
zGG<PLlp@COaUdyXWQu{6GIBnJy*C-V(?C+jNT-5QIU{ohNGcdFdqcx5J43t>q?L?C
zlmxC~oTWa$YDWM2SoUqkbL1J+FxC@kEyJY?SRG^D3t*^cSl$HIz<6*C(i$1ZsBqrI
z@c#``?l4}ziMhLs$zj;FX2ynzSkgVl=G(wp7`%RnzRze_1Vyb3`=}fEA21eDp{9+Y
zrb>T1qn-+#9gGei7~ILQ9s|cihEE!>M~v5AgX}KGR?1O6W>|3IX;L?1l^*OpjN6p=
zdBRvmIlo@U@AN3_V@&ac%zj2uEKD0<T%bqcAfts+;7=I`?B~Jwj1l?`&>_Z01JE?g
zIQ0(Hk1%Rxf@74CMV`SJ<L@_tjWedJV7CMF^?rzPWWMhRY(MkUSHXUOIggq<otU%#
zfx?4KHEq5#bJEwa;t<nHFGUw-Ycw<*W<FRA5?AKEYKs4kFgGj%|54@!YUFZb_K-8|
z&YX7=3Xd@xcR=WIrp_I}gIO^R3O$)@`hC2ZyI%lF0CU3IU=L(o(nC`abL|soI>k()
zlvFTt;XfD*VJ;AWB$R3L#BxtFN2uy~hPge6`ai>%32m4RXBJVmJA(Q4i{L-c9HEaI
zMl$1rp*M>8))R=iz?`!W;3D(Op8+m0%YK2O(ahO&e)ckRjG8@Sn7`-%VwsywkQv9+
zkh^h(IeZ2(uQG+?;l?vf6elMzdoMkY`!A7MN-3TsX4O$BOlIon;g`bPR}9i?%%9?b
zr8D0g1;}77r$+Hirbr2p#moo;xXyf%0?KS=<a4kohiUy7QgWFyDEpMhYzctqe5U*@
z3>Gl&P*I_f={XUgi1{%^KK5c}A01CEVU|&&!VP9eG=76pW=#?%Z!&LDGO3KIRe+?N
zIe}6o70mAy09DNQ?_;o<`O_MZ+-81Fsg@e1k#Z!pOs^*Btz-U6Ijnl-W&=P2^L6^N
zR3lU74A8`UD#GU7u`{_+Fy3YEX$5Fz*8d1;_n7^3=%t1E@d=2z&s-=4Xk{+wz(OA|
zt3sf+jd>j1LzCK>;!i=@!Msj=D4k48I<SXK`FfB%Viqq2Ll+YtVZ*J${PYAgbTiMq
z24OwSsaHVqglWHZ5H!6^uN|<ak13<hh<@f?ihc)}x88y=gUpp5;Yu1}`V@n4n7QIC
zzzB0^4>XN3qptxQV-7Q5%sBJOFTfmGbydLjvzAao-~cOT6ndRlee^^-$m(i^UT2m=
zE3iYXY`Ykn;lgsGH0ohie;4$+vJOySe}uJaGK@LO`jL7y-B@o>Amq-<pjYfM)`k)=
z9A}C5LX!u}k#b6&EHydGUaVE*412Ru=#_DT#m~c_56gQZu#+qnWix$QTPPpl$7&3v
z_n$v2U5e2F)<`3S2C|ORM<Rk)jm^+>iuL|NFb1<y3W0^N7E?qY%Bmno>@=&IuIDqX
zWV$QDSSs>j!&w`s*Xu0nw^@*Rjur7=9}4Rz`4Ca8n(txE1y*7S)L&$sdPep4ORP4^
zB1N-;yuf&wHRBy<ieWAO68y2O!<4>_W3@M8O;=b8DUQ3!YNuyeJS)5d#w4(=Q++p)
z<xba35^KQ$P-e1*UxUmnmYkkU*I80}MP{=WQEeiJHQ^-Ya#^{7bpPeE>egZt3s}Y)
z&=j(MpopS~wfr1tido-ohKd`kZ^&0HWo>lD+)dW~d<>Scvbc~|&U%r4id(FOzL=|I
z{Y=l!Dpp|_uxi%o|56XE)pR}9uw1Aiqn2gO2T2`k>0yxA>sgI0P~X7%ScO$IvR;!z
zZxd_TWvuWHYtnBp|1QgW0Z5uz>*-B<kM+e;@VBtIwGeur#i971m9>q^fDc&n$=7RR
zC43Fg&U#k_nH?<41b|M~lefY5ko6@s5j<i|qlSzwJFDkcj6P<~y$ZCOHAJp;4@=Mt
zp-)(u7O3xKt?PtMeXL)}?ta$a<Sq=b=8&5+$eN~tX+tdc4G=oa;!!X<!gB0{`cc+o
z@>|DP($_&b&f2{LQXJX7bjW5uJBDJ118n=-bgJEnJ@-pY9%R2s75hW%8Pq}I!rr<R
z>JPKq>4$M;Po%=(5w_oTkhrm5{jcYreWM(d$Jm!Bp?949?Knt0*rJV)>B(L}<tZ=r
ze)7P)*}L8bIKe*Uh?V)U(?12@NjA%#4H{o|j|d!oY+flw{n<it!UNdbHbYt<`(7WG
z9mJlc1~|p8re=>|_H%T}hp_ML0T#;cei`hi+0E6!&ai(ThlOG6B=QQw*=)*IpJnIP
z0i0t8uLMa1+pY$~d3JOWo&Jbq2h%}<DE9uh04}gyqww2bWPe2k+DmNTt*|hfoj)De
zWwyWsE8^Ijf<bwO-9Z8JRkna~qw(xrpTO({HiJ^hiR>CGqbIXBkVlfj4&?$|V?TNw
zl&S2c)Z&uH{^TR-zs_I}+y!GMdl6NFv)Gg9Al-HLcs^E`&9)T6;9T|xl>f|QJ5Zx|
zKKssLkQA`Rv%pu#-q{VxBDR>SYsKs@>493p7NmmY2D^|7j-~9Q6G3v5-TE^$l(84m
z`J;07uMu?qp@N<IE@a<gi^&tJWLG@}X%&0PRV=NVJ@PI%ZnG08+g8K=Y8^;w+3TiY
zX?5)09?aFVchc9i8`#svpsA7la2QrJvDI`1-eDW5rg4|8rvSN`-4p@q@3Fgbv7{FE
z(<T^dzt3Lh1Zl18GHNG#z|Pf!rj6|>2WV#>Qef~Qn?ddFkJuk%Kz0}Vz#HIy%=V+i
zWj9;L07(zKk^-7u_R2-z>tk<cVz8gBod;}yow5Yh53=1;py(O9mx^RVY?qk;!*-Ym
zF(d3O>hKw5ucF&&oLxkbn**nxa^H@eDju-?98m)J4{(HkzzQeMU*wn^<m{ztgfk~#
zE~FjetfBgW3#b19mVKD>@pIsF<&-=Ic7(IyzaBBpcoYnE<0Mli+?`|pg~|!XI5F>I
z^f*ULzJv#7=Mt#!<YZGZ(~C2OdQH4JpHczg1ZM;Fc=~VxFGBW7j%_+*`*J311cM)^
zM+$rWIrqs!4&dC`1}u;>wj1n0oJ|xBp5ml^0x7|qSGGcJ2xqzd6Oe{-?)5{{Y0d&l
z7KU^9<FMi^r<!8YbDUJlZ%1&>E5LuAQ+X34k(_4A3q*0|t%jJ3oN_AgT;j|~!eBIK
zoN7;(Ig6-{7Q^}G3k=3`(kY7?$C>*v=B{$K%E1uN@kpibFC}mW((xN4a&8U)BypUm
zAeGEnj`qk&DI5dc)Ymw{&e+*h&YEywX`HETz|uK!)HjpKDZC4tvN(HB1G~<dun8cW
z^9hxLaySf1Ip%Ug=<>+pl)nTk3OHFBh%V%`htv7LB94xpKE<4xc@SE{sgHt+8=Rkq
zz*x$WP!L?k`ICOGa?WaMe5v59t_Q;{PF4@*DmiWR!O<#?-*xa+bC`6Zq=pj_2&|U#
zl;Z0;&Nv+ssOO~7{~BrFWRzg=4#y&+`|mF2hf|Q&%yFKEt+~f}*A=8Koc0q~#eL2Z
zddjzQ+9)b(<4C9=+|K!d;?54vwp5UGa{MTAddO*MgE5adUs3x^7pIDRfo{$xGcef0
zX?YB@pKu)KfuWZ(B?Rn!9JvE9dq2m+4YCI~TyKaO<Ty}m@hL~J3D`5vR&Ure#2Io1
z#|Wo@0WqT-hZxv9#xeF_h2xyYT~Oh`{dg7z9l7D;`|Rg_qyeQ9cl}Qgc92`V4eZX`
z8fP#Z;x4`q;KIH83q&8bbAP6ylPlN$2nvsKS22OPaT}@U-<|vI2&5h3?o0-DoO_Al
zT@P*p^$vS-FUkPCxq0*tUrulbU7^B<JDGvOliY2K0DQTfY{(4Y{!ZzxKyJ!)PzG^#
z<N`azHH-rb=Gs3khxs8~-fZkwDA$Ri=QG@8&Y%h7YUt={I9DEr!L!_RA7bzvH|jDN
zBe(^$`t#g8`n99D(|kd4fjfQ+gBQ7e85q38{fu6*(cGg8fnDYruVOBS%b{p6mb-W-
zKpZ#H{sw5SaBqHtrCsH|O1DJ<7Y`WR4&3?l5K7`6ngT15xm6Txq;Rvf__eNazop|^
zsodMoK$6atQXH1S4b=l=a{r|4Qx<m`y`!#kw|)UEoBOvjG~{rbZvf<RD=RRV&n;`G
z`g;L4pMsr2?p!-2i@4R~C=_#Nt3Xr2-R=QU%AE&iZPHC{>Sj=uak-R@Dd##CV6cLl
zzXv;0#Vz<6E3D@3X2G=E+`G?#uZH^v9oVhq>H{!X$6ZE|Vm-In51^6DDWdmZ6E}l)
z=nl7~83y0wzWXcGH**92g6w<TQo52_xT~n&wUrx77sLZ@6Mf*LjoUj$w*xnS1{gZH
zh6k{zllz!zw-33cl$?CTy-Ch&7uTPP<Bz#RlzQmqo~JU;6K)S$0qv7|xx-nY>EkZ*
zh86wXmzG2J0QXxeb`5fGvoQCR+x`hShPczH8)lfh=q*r=aJ{yGa+LeU22hT1pYOul
zICqN>zla0Rg`CU%yweoV9N;xlTb2_qWDwvWZ#Dg{&O8aZK=wmC9i4!4;WcOgTzN}A
z$K(;7Y$;S6<-NBLG;X|^mm%Aox1M4M51!;(tiqGGnreeyypwyt;LZExb<CaMbxeW1
zKD=|QL2{BewGtNk@it`w^XJ)DfgymGR)t*)<mskiFv!m1Q>o$<PtXfAm>1aqg`vEn
z1sFWd%cWPx8Q%NzU|JY&`#x9^&f7^n;b(cR^x2zpyk>IJB6y;7fb+aKdTK@Tru_o;
zC|<?KAi2o<fe9&>cwQ607tLFh3wtl~M0DUNhG+NOj>%YFH>CjLc-P9I;wq0x(MCM)
z-BK8wz&myu(h_;4Kf>-L-ugE%c#XH08tYSeUi+XhjTd$S4C%Z%7XdPOo)i*i@&p&5
zK8yGINepK5p0tBKhsUO~kh#41Sx}$HORy(FZ$583#YF|YjpXJO^2R9RS<DNiw^|9W
z?hA;y!JBjtSShba4%s((Us77Xj5mRt|8m~H8L*;)H=BBSZt>Ppe!G%)iDJ?!-b*il
z<Tmd$dZN|v<_e*{mbYppmQ=?(yo37B>Um5j?0N&QJqX4$@`|@%@(!;q2Bdd+&tAY_
zGtWRC+&!LZE@ZdxRHYz!z}veKgKfOVAPlzizOMyk2ajD3g`K>T8NeR$URVi|N4#dr
zi$CVQavNATZw&{ahsW=s`0ojC-7ZM$<;Bm0m_A<L3h?*yWK>NY<h@L<oTt3Y)Xw>g
zcajb@4e`E;!3GWUOq9GD;r(5MWsmYQs5^3uw;ffzN#nd7wA~K;V7e?F`G0<c)gR#d
z_5pL^Uzh}NkbfVwJ^LhQ{)z+OIK=;hnhss~Zzo{#Fu&aa97p)wW~eyIPmF^!H@<)m
z5_kSg3P_IeCmsZeC;w_ZFfaZ`CSczD@|OTk@Ed2rCLjKywOGqZe)LqV#h35;95%t9
zpSKVj8^CWG0G~aOA4lExLHvVMu|LJv-Nr8x%>V8U=ndhwQU>ufpF{71Gkj<Ad&BsD
zwu3R8A49F0XZfWpu%F{k%?En~e>wT$=lMq-fHIOFb{>>b{EW9TcY$A{gUn0(>OwF?
z^Uu;3E-u^oPTzqvhTlvMU@U(+^_$1>Ek#(x75<T<kQUEx+k!1g;6G0_uSEXq+rW^-
zU*!eLWd6_eluqUEq2x#!zl)yB>3k^#G8z1l9<XQfSJeSz@!#1Gnb-MNF_x6g_oS#d
zhi@0sTQQG6X$ENW`IdDss(^2xa(W@(TLzjU{wy72m+-wQg?ED=wgz*h{FQY3m+`03
zYrmX7Zo*zv@arj>yT$+VI!vqNKcTL!D*l!sh_2?(zYNoA`1`y7YWZv0A-az5Y=0RX
z_51=lIM~4dh=PYk{`r-dY~troRCbrIodVg-{NI8=a*zLm4s$L1<CJc`&p*=zn_BrV
zieO<oe^MW;@8ECx4xp1iNcpjc{7Nn;AMyX88>fpep+57+{6gw}?dB)^NN>Cz{^x4|
zdinm82JPdoy8#pX`THoBHNZbk#koQL!W$6tj2}Yn)I<D}>o7RXw~t_Ol;08$_Ax%6
zF2r&E&-5u)2f>DY_+cCc@!62FU$A2s*a5*gDp(v8)ZPN6vmo>&`Jaabra9nn5&T#P
zqYewkN+8Wu5E%+hM+7_R5$-1NFoV%uAiapWV}iHn?SEV_g`U|Sg72w#<0)wV1X4~2
zc!z=c2z<9=p(h0w_W<)12+2qE6PPKd>M!^-8CZZ|)z_4N2^6%_2L^%!h6wNn3);eA
zMTlV2m%u^=m&h?WEpVgf@)^P6Tlgu%1)txBX=epL?}ZiT1S52g@4TRHE>;*R$fged
zD8W^Cn0-NzDF?VH5Gp}=N#Lahd$ho)gv=Ph&7+WFj}^Sk28<KzWrOC5;6u7quL{=F
zdE<D&tNSpRAgGSVb&(`kISc&B0!s?`Qv}bE!+T8-O0WG?L8TajX@W&`7$Z}_6G2Lr
zU}-1VuM5K1z_JBOx|?zYZ<YY$3SOBCd-LpqCsYW}7o3g&O@Uy(9Q=iXZ}tHc38qZO
zVu}SLbd<V8Fg}XG8v^I6*o#uZF)9(>6nsGCgfhY2d$6Kh@bD{u3c<U-gW;AykO@#J
z7;S)t+k*Ssv4|RhR{_-53X=W;Wu3r2pLVZa5E2IU4T3m|RvHE0J_oEx@DjbN?g+l7
ztl3>b52d@B1+P%~@}6MS3cW3Y6;Y6VU+@jpTUrGVsDt={z>7})v<bHDz?QTNmSupi
zL$LV@jOi43e-HMDf+D&d9t&36sol0)5ETNnN03Ry^(TUE%8&O74pGX#Phe3%MZe&s
z#Sl6maNG-_gMx3#<9sS`cL8`NXs4F1A;C^MNj)rRp-(7}2<}`57!@eL0>hY~>;SNF
z!JD)R4#L|~$aEBL{EPB0`-SOKVcP*=3`McdLOppqhlDy223>@IP#er)VOjuWy9(1S
z07rzsk-L6WIF%H-32Pbw+=Zskq2icOO;_h}VgAdI;wfB5#&`+qDWmKy%$@*nLfF3!
zihP9cwNAnPcT(s?o$<cHd6aAP6KcuZ@fWV3+;@QRcpT;eg$0zcIVEiHgT2AR_~(Iz
z2>&1tE>!44aoB0$Zt8zIBV0n?y$BNypU2LG3tNAOF=vJMsP=SDxMB!%5yH4V0FlBi
z-_iG%qJ*!JLv=y8t_f?pD6IJjvM&iMW&=bEv-4oZW#Lcc^~VU0Q>`sl*f)g1IN@$O
zPIN_>Lzh>Aa1%L~iNduDL6Rg~_alr+79OE0af<MBx*)Cz(VmN2MY!)@7?UQ9W&zmK
zg{LXmmm$oh7fGh@`4_O5>%xbJVRyFhm#;9GBV0_CyIkQOFU;i$J?P*0<qNGG@D&Iv
z_F|!h!tGKp6bZke)}CTvei7zMgi24amkL);#;)HKHXOoWnXsBt4&_1x9Vn}?3+IYq
z+b!XdolsFJ983pCmGEn-epU<9so;NG`0oag)Chx4fuv42uMD7GxUL(N4Z@9d1vU!(
z%7HZr`>5gjj__*(`0fh#89~`BY&{IU_k{B)N!TL%kh(eV3$ujS?KYvkmyU+C3*E@2
z?-0IB;aI2eDHYxy3U7P_@JP6tYTaEz{cbQm7RE<|p<7r)39269cT_)kBHTdkYoBn}
ze30}Dxwl~Nfbdf@R16CJ@*w)DQ0N9@o(bn@0EUESZx}i()Y@l5+K6xw^+S&e$7?Y;
zCbVq;a1ed=H)K1C{`do=`$cQthtLC}$&~(a5?!N|;X%=h!2r&p52$11kf@%HD!7QM
zX`c>@4znTJRrE?CNREn*Q@HFVnp6)(?jjK#;y5O{mPhr6<02kikRBory3;*HPH9-0
zm#Fi<z(O>MUdAUxe^7PIN5uaeV*Es2e!%=iK5t;X0iySpLw%rVfa(W9qIanhbxL$>
z4$KY~eRTv3AtHVOG=z#ipvTQ=(HB&ZIwNv<aWd||aM2GGC7l)VR)F-J=)X_GMTmMR
zXMbL_j0zW#qV1GCixM&Z2MaHV0;j>Iiz44Yz;{WMJ_CHwB8Rgei4kqO1uRyyhkB6W
zM9K7SyCT|n2G~_m6ZMhAi@Nhck|0|BCdGe=q6w=YG)c5J9YT{uHLF0AB9h+&O{(Y=
zRU^_w@mbK6E{Yxm$PoSS4nU@;&=Vj_<og?bk?W!#?m|VjXonv_j_9p@;L8<VriVeE
z$Uq+vE);cFV`qv)<#fQmShRrRdV7f|l5YPSq8S`0EEO$sfiX8lP2_Qwi9Sk%m~xTT
z6Z{pTN#q3F60Ld+$|})nYJ{v7<&i^lTeO@$`A{R8@Ha?mMgJU!-a1iIASmlawRAA0
zL8PJ}wo#Pe0fr{guk<{>V;5QCLDMX9Y6Q3^+Byiv77?cullMit>ELav$dTNJ2cqS@
z7;F;_AZ<LUUDQSY-K0bG3U#k`idIbm$wLv3;+Zbd`*d?X7MZos)Gb<h7K`W+WmLno
zC!!we0O=LY{{akrBKx)q7}YQ041;t)G-)mP2Sr`p;CL!3ltBHkD4JrI5m74rBBP?k
zlw}_i^;7O`TvS4zp>PoUZi7Ncu{&9~Uz|&y={X>lxq{tEY@^PggW|J4VMh;%-=(6S
zi#Uo3{fEVRI|aI~;sH019uZedV9ZgmJ5_t##6!Cv)Lrah!$OaV{jXu}xL8>Z*&gC&
z^g#9!e^UVxZ}IP&pyGtMG9P?CVy_wuo)mZf1bcnOGp7Ud6K^Ml{^H}&;0qAnc>%w9
zpm_OiJA?*_w}fFcg2j8O-62HWp#>Hy-l+$6T6`)2*ctJ+^l{EG@s3oe2p1owGSgYH
zKRpA_iF3-Zv<UI{)WLXOJdfU37sUPy=)EZ3M`8XYv5Bez(PFnjSaDf=ojlDL@k{BH
ze~A_A=&=(gzD_x`E8@jbz^;ntbO4JNGwI!$DE@##kR<WcTL8&oM|vith~vM4G1tWD
z^fpZu$F)Fjnt1VY%%zJrP?9l2yyJ72mMM->!_X}8T8eqH#d+bta>T)rbpPdw*DQdg
zdE#oSE#`|)(QCgzysHxYh2m#X;4c#2{}Z5Cyy{O-mWY?Vi#6R4$J9anP4V=XU~idt
zx&d?L;tS6(SRp<+0-J7$zsrQoO7Yh=fGY8?YapdsEb)iv+v54r!0a{Rqz+h9E8eXE
zM}v6JG^lSBUnOs}Nu2O2WH*cd-HEw-Vvo<U`WA7w6Tn09@en9{B>sS+t1j`u66k#_
zcB4dkx7cALK#!P9e$f;0)I@0L6^Bq~UZ41XKR`pjxWNUB7_f`w-arS%Yu*FRQ}MI8
z7=0$Lpum1eoaO}nVet%l?~aH+{vY&?iX+ioJ!wpQVmH9JIGD=A4w4u5fWc8R=TA`X
zmuTtphX*8|@5i8%B<Ulp_n>3~Rpp!|=OkFmA<55n=yQ?S*HNeGVM!5P<gSuHH5iXb
z66RysM<pAn&)rSJ4}}<a$zMu{IVSmr9&pDcdwjs)A$cnWgPxM9alpJJOI`x-mN-%;
z;t9#B&oJjBss90+e^Szv0x7<dUMlwbNoLa<+8_P@^fL!YI_X&$D0y-N{6P`{J;Y8)
zLhfPp!IE|KY7dbtrocW_Vx%Aav_#Yjp=Tstupl%{vR4F#aLL=rU_UEq*bSNIB(}*|
zON3<R``D86lH?@-k&-mZr$<RHd4c4Dq#)c5nu`)!KV)B$j5)yWXh}c4I4?^c(<Kli
zv5KHDR??scWt?OOJ@u|gK97J+S0!_sK@u+sYQS8A<Uj@n6D3pVg9b^GI`Z?AC5ijN
zkRpjWfWb7$P8keMmqZ1EFGJ$@Je_~YlyqGKf0o3Q3!3Ya_t#-ETf(LekQ_-v1?F-k
zFR@@#o@5t!e)*F1W6)F}`HtG=3ME0*l29b^r;Dvv63zg7iNu$_C3Qnm=>UdO$uV+f
zZ%WE2QY@1!JPY=6NtK!UKPx2rq9FU0B#<gJm6Gfou%b%xU^e)xB^vr~5Vs}enHa2*
zbW@9Htt6}sV(KJ^9bsX;WX%-JHAt%0L1?378+BthNph^P;*Mm-Gf25BS>6r}&5}@e
zVD}^{O31ZHESX@i-<M3>h@Y}mvf_J8K9F391=c1h-V8DA5*`bK9g>gfh21F$riQAA
z5*7vak0dqpIi)ViMY<awOMa&ERJUY*5lDI@r^(TNBH2C(!g?iNQ+2vevZMwi{Ssy?
z^bSb=Jq8O0?ULaZa6FZuofS8pWcmuw3`xEwpL$r5G#g7Bk?=D?GAeP3gcW0wPBDaz
zOT^TD?jT)p1q_bTOTi%7Fa75|kQ|U+qSiVmX~KNSJSbg3sRL)}1nPu3Bz+|arnyLm
z-UoJAYTrX`(XP_BsLSz)v}`57QRyGAW6(`H>IX}YOWz}Z!9#j@76v_~yXXjvm-KV$
zHSw0d{2mxiNHf=B&PRGG0%o6-mN9_&N_GD=nMf^9f%!{&srey5x`lkaKq-sbgM*~c
z*_UDRlr-czga%7fLtuA^G@SgoQ0cxevHH`}+Yd2!M!N4;P=-lAq+Cb1^m#5w&Pofm
z0GyLXyn{<GLi)eCF!a2%n6jCXQub_EA0-|B9&;C@yjj?Ui_+3SkX({F76FTvwyw2<
z|FZP+$pA6ZA76v)SZNQ13vtpPsc3vf>O|>*tJ1p^`ov3TltFfaw1;d;lo}|Dn<QNm
z1CnIv1Nx41iqxGNDy~U8=K-Wje_I8TH0f<hvZqTu=&6?_ZKMMt*QJ_Q==^QA)JKP{
z$&pIw5s@oB`Uhm^NgWeFnlIf$oht=W4!vRvr5?dxERt?afu>^VaZ1CKNR{V7c|&Sz
zz?POulQ(1Vrj-9Ggq2D6F97>3>EvYqmC_+9AyrBLSq}DU>18B=?UQaxA5nU~Mw&;d
zhgxYo1ub>bSMEVfz4RSD<{G32sRyZ1+CqtpCh2qdn{-E-z6~UIr56K$HA_)k!_6f<
zB82rV(pM-6bzf?si@a6Jr1<)Q^zu$%ZPMqL!kBhxDz#JEJEVFl|948a_W(SUZv6)Q
zkEHc)z|t<Mb|v&amhP_v)-83gL1>TkZ=744^hC;|-=J5zhmuKs($lG6@0SkHe-apw
zx>7gGpp;McK9!y_0DC4avVmksS~!RwdssS`GL9p5>7h^v9hI`_p9hRd=lu$rap{6U
z*ybQ>c7$w4S;7EF_sdqYv5Et-))6o`$=1=^@SyB9x=Ng7yFSC*Az9}{@VUs2`~iiB
zWz(rs+f|nEH>@}!(>cQIqq2YM!R{t|Z~`lHm)WPi0sdpMJ=76(T(;*M01sJFCMG>)
z_pgA|OBT2S(!6D(Ghx~Z*_6*Q=OcTb@)0LxdO8^9E4xBomY?kWZD{hBy?hXq0W$eK
zs1KC+{O9AzCJut+l&tPCWCqLLr=GSDnY+CTFjN*rzQk!+y96elk*)e0{AXnY^e{Ll
zYtDtH2-%F2pgb?DPRBwcWiBcVM#+rNLFfe;n_8eQ$~IEB?<HA#BS@lUPpdI_S!Uk~
zEJn7H1(~t3FIGcJoNNvSBv)iXK~#UgDw{>g;CPvwp1lb&gE#ah%HE}TH%ayZ1z^dt
z4Sxcp$foUuh1X<8YVS{#vGXvPCi9pD%5<66N?;kX?I(d{%AThhUzV&k65zVb=^#XB
z%ch)z`W)H4lQ1n;#&o3jU!JVxCrswcUZtE;fo#iGs3?>rErqlq+2_=@S1kLc8d!;J
z{t!rR$XaQiOJ&A9NV_SkC!e@XR(t{^<uYL`)>0uWISLDJ$xiX0sZw@|eCgY=gJoc^
zk!_3xsFl4GMCXs{WYQg&te5@z44N8b_vo3@C_7mMnkHE=y>RcyrYNA|u54Q!R5Z&H
zu0X{-ncyezwaB9B6?<QnO`jQQl^x__@PX`A9YCAx_m{Di?XsYCkl7)-@d~g`+5MXk
z_E44;4Gs23vf_&v?UIe12mfQ)JUSuLEej$Ssz>%dz09A;elG+`uPlK28vA4&)S2Ed
zJ54p*0olRXP(LVZp*E$bvRCfmf_Nq~odd&=Y&HvX!?KB6p=m_+7Ucy-Wru6PHzsS_
z3t{7SS<wrS<{;lq9rccKcPcvVmoK1F`vG|ZeaO#Ae&Z)dJ1Bqh4mh0U5mcx=BtJ3_
z3@-AcO6WZ-zvc=OS9$zgY|s(;EPBZtmA}D*FgN)+YU6a5Kl%=Q$K(Y)7(6bYMo%9P
zxxHW+NIm7#ZUK17H#tJDxBO!Y5KhPkDf{Fj|ND1nIw_w(buC}{@_i8FCx44h-ucVV
z)8j5cK63_43zRQ;1SvuC?8i`eN^YV)uweN+R9Oj;M<v3-Q2FfvV5jA8`9sPX`P=qT
zpkeZx|AHf29z?ApXXQgw9XKb?j|Pa8hf*pnN?u6^+Ahd<_rv^)^2?Njx+LGS4C<rh
z6R6SkvOIJygvQ9<rP5WbJc?>waq|8w@LiGLr=sswx$|^@c)7n1OiPgexr*ZDMEQKG
zJtfIsraF4E{M};^lOiwp8Q_{cAOQTS@)HG6ktPqPv|_qEpYkXfa;Ildktx?u3Oh^w
zEBP+h<${l)B3r)scgW0<`#r>5uDmS|it^-*p8@2{=V?JwAn(nk`d^`3{R6BilE3>t
z)>JG%Aj2k<$hX%*#SQr@<U*CoD}rInP5C)7q?O5w*J7?*KI3hG3i;b{&~!_#qRy>K
z`F*MiRLP%T0JE#*o9HUJE#KG+${P6*asuk*ky;Ek$km7F{%e$9pvIRbc>tBZ?#P8y
z#<(jFdkLUf{>~VTxhH?G85Xw4pB#Xg`||H83EV0-k+bzcUjH`u+T<$(@cXvQ6Pti_
z$e*L{hIYzVJOX$qPp00MNAmJE2<wu^=0NmgdAuA9_HKEj9tQWwtKI^5B7d9S&Aswt
z0_<g<{Htxi`sHtMpngC;jb818@)-%x`&7R9A_kwySDphHlFN2ra9AEs6@wA^swQm7
zsJxjvK*r>rw1{!}+S5?zp!j_lz)?}Y8(_a(v4bM>1B$9eu-i$omokqB747traaOFQ
zz~YcXu@gdF6w|5Y`LN<BHT}9O-lI<%A5r{3Ka9I#4Ru!@Q>6b1D~>A);=t~q7$>*e
zQ?YJ3jPX+Zbs2-+iXdcxC!J6%`Vf3R3i~AL;5w=J(+9GB6>B+|^i!y*HP2u1lu|<h
zif!~34pewhEFGlSum=nwijGSV8me&SK*edrZ#+<*QH)U+T$o}u<toAzTT>wOtU?q5
z>(43vjRJ^JC@(?Sc||X!=OPvJ?Q|?5O2MO2?gd4c6Tn49O$a70DT-!d_0ft_s>NJZ
ztTsY+jKb|bSP`qx%mrVZ;<KqBxuOW9YwoI|%n8QCE9RwOX$gv<w=tNgD4|k$lA?1A
zShC{pR`8`Ly5>OGHO0M1JM2zXEHy(#n&M?@)Js=vqrQO*#j3ra$y7+`y2?`g8xF?n
zicjfzldaHB#bAzNB9**z6@!$S%2O<y1T0^{p~FxGia*^UvrzFrH5iH%ug<~hixqFu
zse}@Rpc8X96c6Xn`>#~d^eWa=rZ`;!73B)?B!CLV=LRh1mSXM>7*nZmIRug_Mb@_f
z)rw-O%-mLlCPP{cer8CkRlH6cT&GC;7Yy}^nFXM1P`pMBiH(ZSs0`nvm``VB?kG6l
zf&HH16CvGyEs7b}Kzd*C?WY)RRs0+R{s)TRE<tFUVh^>=wkv+3r$~pwi!RGfMO6Sy
zd#Gq*V%d)r5^6B&QhYA~_E@o<juv+-qQ8K!9>v;ckn%*~-T{VQh2{fD=~GOm(pA6W
z(Ngf)2NZu@0LP%>B&9r_Dke{bG0zlC>KPeQyu1i@4=V<LgtQUGu2TS`ir5>_G^V(E
z0jnQZ><orb2jy=wv3f`4uM`38SN4%(azOdUbdWeH_mF#ZQ2F<K$aGfTtiaqMC2KK6
zyV#X~&}pc{%08+ixGDp=AU&e|?i;8$s+>YuBsb*?)VAlYT$l#_W6G5SAUUpFG9L^c
z%1TObc`BF0VufDHq4NOV%AaxpPAHdBMBt<BFUNXMD%%pUKwo9O2h{s1C%y{IUuj=K
z;Z1<@nFJtE>2)2GK}sQ=^E#yrq!z?r<+NKM4N>+op)gc=h4Ol*m9hPxJfr-FiW*_c
zNBvM3u8gFUJ7<+1)GBsP`5^@c5z2_4!Ej!wqIYVfQt&kxqLj%Lv|muZYY&Iei^|ng
zuu+$k&t(9MR(4(hxU4M52ThDpSPM<D%3mmn6{p-vcjFc1EV|*ZDxV{tI9@q#2^N~5
zbj$`wRI)oTm!#ZFO^3<KZM_hkq8u{8ifhV6)ZCn^45M#Tq$xQU?ch&W#xDm)hO+Y{
zNHdj7T(F8P<pjD|bClov!<bxU)7KcxQ{Jb<O}_F|3m6KN!=acfR4SS=SESVWVXj!2
zRgbw6WmE*_ZYZbFCyPpzp~vtu-Biw^Fs@9wG60IomFMqM{<A{qb^(mHlt=pjDwVuk
za8xPhy#Rx&m3>*@xUJN^j7_Lfrmez0*D9C1gt<E9GZn<tEBO?yHz<qNVy;oSn7rpE
zWos4q?kHDKx#zC3<_*YfR)$hIbx--22g(*@(=f$<_m$0Q;BQqn{(#8`$`9yDXj8gP
zhWYKvky8L2${+7TXs0qe1>m7_{J$GdIq?|8bSXceu9nBjk0~+MtsMFo!g`bwvH_kb
z*U?L+SLv4vWBQaoz5-$W%4>fC8&FQ%i2bz>Ds>c{JyoVS;+J`*Y#)cgL&|q1L+G&b
z%grDiQ8u3eHmbZvPk}Mz!jB+yT$yVEpM$D%8iYEk+UR22ubNL6;sMpER17+)1`h!{
zsQQosRcF<A6cQg&-Q9zAx~PQo)<0}lJx?Fza#g)uiP0mfByv!Ws`kzSzne-#(T2Nf
z_5+X{Q!U(p!Q-kqe?hN@Y9SSrJyqW=0`OAlreXEoD*I=c^HCMj&2duo!vdJ?tFlmO
z(oc1q1JV8}w+w&)RjCkzfhxP>DaZ~|MbN?BQz}1t(FdzyI-n^;wLcA5sOmcgz-iSF
zlxsYrilOeVFjayHD#BGf^1jciKFr4o&#3~)eT`79`WD8VS55pLgORGL#jq(#6+=mi
z3#vW&Ai1b&s|R*T6=HuCVxm<S7eUNr)lb2&Ek>oHr%$Zv-x2V~sZyw(c15+G60TQO
z5j%m!t70j*OHduB@>Zg%{s`uhR1-DWi)2;C4oFE+HPeS*uBj49L#ir+;;=N;iwht+
zT{W8$rWvY}9n}AssrrHXs<Kp9+W@YsHqHY_w(56s_j6PeDB+W<N~7$2o=W-=81hxk
zz91=7t)m9_B31NJ3>K@}=|6ClsMa)q;fBgcF;A(gHU$cAs(gB2TA3;$9ay<)!6(2f
zR8dm;{@^WD78k3pRQ;2SHC3rNbm>*AKCl4XR!w;wb2X}$se!Xrb)3THI@S9}Fj%kp
zG8CE`RKq`luTdrb0LyMt6;nd(j%su>R)1IZ&MYjuS@qll@Zp=BuLHEGcyui1zUnYy
z7W<@D)z4I<d!TBVh*h+y>YqSbyDE+vsyb8-)DYFF`Xms>JXC$&2JlGrEoH*HR7dEC
zeXOe1LPfWVa~w<SQI&Hc<%#MJUF*H7ImNK4PvyS_4E?GNC14m(eRmb=2USz2z!>{e
z)p{`|pQ&7%Fgm2#K;HYXDx18A5!Iueuwqn|=m4Q(s`4_BjH^m1x#^&OpI%jtYNx{h
zPU@-uwOXs$K~U(d_WT{-kUE&ER4!`X#{h@bEQ%ss)vnpF_lVjd58$X>t@Vf9ZtBEu
zfV!&-DQk92J@yO=kE>%S2JleF`GUk#E%*lpd#NvwTj#BQ?Hw3;Lj9&EjPX$~I|-7L
zYJWPT?yKH)8H0Z61$RK=ul|R6a0Ar)O92AadE^BLsaI~t+$ps^kJ6~Y>Inmw3{m@1
zbuCowNv`T?^-?cLJEOLXuoq!!+Z=#!^?FMGoK-thv*S7SwJ*RPp)Q~<((`IB6F{VT
z3N?a6sVAL+rc3JcLP&{LpW}n!vbugL24mDlk{PT1)BX+2h*Q5nAL_WG7XJuvRsFmZ
z_~X^5t^p*df26A{QSEycHYKUM=;4>F-uMr8CPlrPzAAA|ok6+&R5ddPn$pyZ{s+Ev
zb-E8kXQ&@gM|-CFSGo<e)Gg~VcU}E;BKWe^7k#P!EJxj(ie1lDe@+b@dFr>RSeCDz
zdJtHFdhg%hFI0be2OLG}*WSfG7pq_R79=I=$#k*YP%otzx>Q~04JkL(!;Y9MQ@?is
z3d_~w5ztVfuDpuDTk2+d23D&7{0vg6)G=R@|5>eeq;$+}^+9?&)u`7sVQXsDGpR~e
zr>>`_!+Lex5J(!-tI5zt^|wKg)}-!o1;ZV6Je7Ixs@GS7q*>j!9E11Nfs~AGQLi^c
z{eAVrSj@GlRX0G{u0F6H+ts0-ol5`zy;B`X$-akb-X4HQ>Z#Q1(WNds1`{8vf7%Mr
ztxhoj^r-)!?t>?4O*Mq}s-2g>v_AEXeDL+FZ$5|LcR;=51%N^ImI#2SYQb?Re5OvM
zRP>O#a~xn;eVLr_5p}2!q}WH*r(VS9n0jS6j2c(FQ?sLkW_b%}95rvv!3OWw#L#bW
zK%;vN>YX$rkzhQiDW@RGSyNvF?2zU`Go-j^!pKiQtf`$1c2~{Pc^EvR`GuNdj%qr-
z!IrpbCUyXG*Z7eWeax;=l3(Sk`7siD{WK@v0`S+Ib^&RC<~~J}ftq7~!L%Sv3{`JV
zX?!Rb6|7mj2{wgj?0bQQYCNf;ds;I!6zb1t+BN_S(=6)(L%8N2a_-J*66namIn99>
zEFwZ9c>!wAYwVj}fx<}5vqo4GrTKzh*cUXL_G9p(W)-DxFKHa#0co@*^hbcpnn`Yu
z7Na@&7qD23ltS@1jfFgmE1IN#fnC-7NbPU&nx-WnNzhzy1xVC<mI9I_%?b(DlB`Jz
zfQA&!H}+Y8*EBEE?U<_3{0Q}FnwylgOV@l)UPp%JZ+e7hYJ9GPGF$Ud25C8(*h?79
z)l97bNuK81zYv<Q$=C_@0?lI&%oS?tH$X~}Mz$Su#hUfxc;3+bAOcCL=IS{3Zfacf
zDE=$cd{P8Zu4$kHmKB;8DHgt^si)qlO3h{l6jo_ikubknGfF2kZfhFoHCm(jheCl`
zjXD~aY@KFx6_#DEiT(?7O`3-;n7gCNp{i@MW_1bJ?`ej2z?c@zodJ;C*Jz&5_a|C4
z-IVEhp!qEwV%jt*l)P@&OxO--9hy|?jp@|1WWbn*nuoN)N18V;f}~4RH4UqHtl9by
zLc2B9^i1f{80fg=6U~Qo0rzS~-UrsFxsnQD{hEL80Sssg>6qo9=JW*WKYOalrAX+R
zW)o$fhBT^2;274#R6^*8riAh!qna-`kUgf!`U(oiHJd4S=ct`cUgdu6gji4>(56!&
z&{@0WGUg6x|1HD{U9`piu;Q>*NXZ;mZT@#qbVO_B1GsDdM=g2wV_L=nOdi+9{tanf
z+I8!&3EtX1YBV^Z{YnMQN4tf7!;{)Ux^sNB?4=m=)5_?OkH5B>F0TOX5$Y!i)V@i@
zg&^&VZ-V`l_Wg2@1Z&f%Y#E|0@B$X9{qSE%Ijvp)Kd3)r*DhdzKTNy2A0S+Nv=u8n
zt36AH5zlGIDR_v`#+e}Pytdl~bCKG?WPm8GFGV63w0b(!bWz(&oi>-W3$yWSM{D<f
z0Ans|3&fBTqxGUYHCD@}qHUbEY(KCo+E3_>byaI$GyvK0+A^x6Cun;p(oEEb_JJlz
z`_K0<F<Dy@1dyWrl2W_Zw3)LYG+p}^WgauM1>{v`YCooS&MYl=6~J|Ewh*$jwZ5^y
za<o@&KxVFXbs`MS({@tFbiVdjDM$*mC3f<;3bi8gL5j3fHUboDR}27@XuSmBzo89J
zhu%`{GD>XU)XKOprc7J13RaYB8UH|bg|@I9LT_n*-;3?4)NVKfzAEjt)4*!9anu%B
zt9^l5zUs7b<oncX|EvIL(Eft&KjD3%Eu!aolQ!}$RNT>q(aD9o+L=_#Y0<ts2NvGf
z7SpNcR_&(&7<{a4TmaeK+PaAVJ=&lbz}}~IrowE$b~Qch2ee1nm>bkKc0kipZ4bR7
zpJ`v64{Su+NC}Wpt!W<RKgYBWXlahR&re|4`*qhALCgW&EvhR!>7t**+(F&=Pmt!U
zdyk&-$91>9gcuLqnI_yvp1Kb{f_g9A{9>5xt;?x_rW3lK+%e~)YoY#?le*6+_28?k
z?1u(F-GTQ&>92b`mg?^TI;JnsK-~$-CkE*f`@nHZ7e;#-q7%_|5vp@5#cyz0=S10!
zGrDQy^n~d?d>$&obtUw?iO`*h0N;7t#2m~;>ZX4K$|&9Ar!e$_?gL6GUDQqf7>X|G
zc2Wmqv~Cd{Qng>!9l8dN7~Og*r^o7;6#K{NzFYw8icY2h%~joRlxvLFMdm|cg6`N5
zY)aHkqbM{*S4w@*X}ZT%z|wWTYXCBI)23lCQ<ty{Se7pM31nW^t#!aAWa~_8u)jIF
z)lA6Dwd*2YhEaLC3zTQh*A;og(gIz121pBaTO7bxq^l(#vsia!9XLvK$H>*Zp_@%X
zQmM|m1)6T^>TSTvbnn-Ky<9hW7uYLxhhqR5bOYplH|mzX14T``IO;RFqbs1=?OmPy
zGwN(_)|HF{ZP9IZz~p`1!ETVY>bPX$1KlnzWVh*dd<xL6yGN(oI&@pf-RRVP76yh#
zI#;R@bm=affW41(G32{+>q2QOdvxAKQ2#`CmFnQVI`%Ed?9(+Ig=zh|gZ2|Z2Xt?e
zGd`$`alj@#(>2i@H>5MrTVhx@OfTFK-AmNHH>y(zu);Cj`9qLBuIqOOaL~U_4xFRD
zF$Z(|^>3~K`vJYrQSdqG-`<bGgZf{d2Z^&@_7E};>Em6nY8QRRUaCJF*7rt()K$Og
zT>y8zO%5xL>;0dHi5`0XhghMfzJEXFy!5ZTL7}(4u^ZA(=tFOS(pS%W1WG@>oN5#P
zdaV(%1N4tsm<!a0lz}fuKbLmxl>S9Zd<N^M(oGqnua!~%^=bVB%G;hnDHW4p`W7mu
zhwHt62LD;TS`PK+^j%}HJ3_yN-0t&wJr$cH^}DF|FiP)B-}}CxFMAPEF6wuG0}!p>
zPY;UA`pLAvG5Ux<ASG7cOGk|2^ouE0x~gA$_c`2u@%kUSu$Tn>=3+=o)C&tilce7o
z1IA?i3~HE5(c4L3sy^>6fHeK9&Dgbc{kPNwm!V%v-{;BH&z8ZoEPbsL=C140)<8wR
zel8z-QJ~*NKU1MTiEi{FeGPTQ7wf~`#GL(xesTslO7$A*ExoB9Yr<rO{@J(Szol1H
zLq(;&i&8vQ`gIh5RqM~xfw4xfDTUrz{Z2ZrT&FMNLQ12)eJSRe^gB0TEqC;-^zr_?
z`lSV6Z`NPC4u*Sr*-|jH=(`SsvemBtEE1#-^mU&?VVi!u6O--wt(0-;&}WcK->I*=
z4e(H3I|0%j=?njWrY`-cJ1BefOKTwXiT*i?UVHWV6hQUqgMWeSetmi?<_7fdu)zLQ
zUqGd=XZjH;Ee`3|u|YDdw_o}Sqa*tE->^gD`cLnG)WHzW0dO?D_YMa48`8gq`3DRu
z=%MXoxakY^&W1M^gXEB*H6FmlFfs(n!-fLN+qfE<Qb6fuXzK>0yWvHupC2<^{|Xi!
zH`L^T#KX|D7QoZ+)cyht_A+!*J<Z#2yA?Di4PR3>$Ja2Iy8iqOCn+BCH<VCt7ht$O
z9fLuJ#erZrW#}pf2sY$U7B$r1L#d(DhDGhznKK5yFSaYpux$&}ha2?WkaE^g!^T{M
zp^M(4=M8t?r2dykgGP_hC_`T)Xf7CjCKvaj!G#|0(T1ZRLg8gYGnM~i3?EUnA8Qz;
zR;D<^gC=0{hF)h-CKyDUAtljJ^(i(u$<RV1$%fgKP)jj<$idt-gDMmjrW!s=07x?|
zze?wi(hYx&V=}|wFa<_s8aR}v&N67p>$q-Md<n9%4fk$9Q;y+=5_7qRdOBX3XIM*_
z)&j$YMwne_$fRGi$nY{Bh87#zC_PtV__`8OZWv}JV6N0KF%axG4O^`cR%Q?&;bNau
zZrFDn>MIO7O3~gjOrW;eN`r!2@+w0im9VM}`~LxU+pw47ni@j|#bLDuB!_V28?G;h
z`g%hGb&fO`u25%flVJ^|G4B|5<YV=B4e!whAes#>RA9MhI7Ba}7K5}AKbrl%;Y&KA
z(Q1gJyut&+vSm=wW@wuZ&~9+2zN!wxN~%qC8U`r_cxZ@uilsd=EN{eMm*JHU03I8j
zCzqhxaB~Z!JTZJrM<jX;cjzV4XDIp(bAyIB3bmdZKD>=Bd1hdy0Sws<hv+3UZ1|L(
z&m)HDwXl2Cu$gk4V}_NKt{ykAzk?MH#z8t3;AqsZgZlkO??jk=z<8Oga54^_0OdjB
zFYjT{*?5?`B@P)M(RJ)%bPmDXVdIL=V4AD3eF&Ry#F+6SG#oYB>sA1DGx93I=x*Fb
z)$wD-R0^Gr8+$3z^f1<%q1V$mnLH9Nqhc)>y^XHXF#Cit`6)0T<N7vOanhK>1G}$r
zCKV3+jD=Je_BSSz6CPmPauW=J#`jiW4}**@Z$b1a<BN9k-h+(~CqZF|G2j(|Ge!=*
zqQi{2l$8uOjxL1xXN>|%7@adRK8KhHBclqG=Z#0`5{NYJejDnejA6sTE*c%_iFV1j
zl#=Dq#$PF}h%@>HL+=&i++SeKRpUmA-Q$fF|NTF`1mi9R6eb$4mtZo<xS4|fWMh&)
zq@@_&O@qQ~Mg?6Ssm3vSxuqFBw_%0p#$WbeF2gt_26LIlwfPX5W%Q+(<+^d`ASknq
zl~RBl<2$X;kZYVw40*=EH^H87ywX75KPxc45d=#MjcpSkrpU;kE3nw;RsgKT*is3O
z8^+|zFs;;BPQAZ3jThEn*UF5kuY#o9_|j%z6~-~zyj#X)RK%<_t|w2m%BVR8P;Hz>
znSk5IWa@RSF*<S}tk!tr0_8vJjFX&TO}%kwJ(k^I)X??ZXmooHG)>0Vi%@aL7_G+K
zU1OC1Vw#Pg&`Ioj#w!zGT8nXbGF03*cFqJzt8w`h@I5f@T@T7OqfauhcB5N3Hlf2f
znE{4Q<9iHHJ~ZZh4=MIX#;hw?Q<u>|Z;8i7&6iNvZCpA9gFVJ=&A^@*y~u~@HGW7h
zus&nTDD3SwuJ{OGz*x`+^@GMU6jTlwmsJ28HujKbFk%!&1B@DfiHEQ;qkx)e#*NIy
zkm+DLa1MixcGKQ_5W3&A<P(^9z$B&evXf~gJ+BU$=06Y2*);Gg>^@{l-VaI_llLna
zJZv)3b>V7qo(k-U$<hvnqo$&jknLs~8U}DT?fe-G$4nW&z>4E0V;wB?Fn#9-y`CmV
zdUSi4?7I(P72c-5&tZipOgpH+>SKBw0Me5tF8T7lrs!9(CO^{wdXM>=Qs;mq$dpUn
zG$E!)9R@>94Re5<HdPcu_8F5SJxjt&Us5AgxJg1SmuF4C(!=kZiBCN_5vHqs&~V<A
zWv9|}q-ozifGE>$B@Dh`V$=P5(ey?d?7n1L`5vT2o1(r2xNQ2c6Dnd%%SJ#MYf@=I
z5@)KUX!43_p9F(fO=BBD5^vJZz+i$Yik|t2rU>e*NHQ(B5538zrGLTR6jME)@-Np+
zja@J*)g-4BYnsXFV=$(hX5PVIhN+H{*O{h7I$oM(l2fDkbyHM5=CVzr)Mb@p;?_cF
zuE~R*@_DA0Brr7J#1(<0!1UUuU@tWNJ_0L>Om9lC&SKNA>p)UsnjcN|ha0AO6akf*
zURML$H1U6eZDpo&dth3*srCRkDoiUVaeB*i<70@aG{K3+&1HJY2YRbbxeD;zHrb|Q
zuEw-97VNbqvkivUnR0%@+#OTIEGTR?ouUNOJ=2S4FxO(*iQ5SEKhqP6$68G(&qKun
zQwh0+ZKf4AEUn#?F$ti<6l8_$Zj)m+R`|p;hpzlyQ+PiZ`b=}uz&>b_hC{_u(>_WN
zKQpc7!R#T^Mp8d)a-}mjBc`(hz(!5u;g}mU^=}5SkDCJMq3vK!qdjpnFZ~MGe)CaE
zRva*I_zWCQ<|%Zj;-HzA3oD$>>CFI#%#WyX#l>7l8Oy`wO%!don$0>a?TDF8h3KQ^
zCTjF?Gf#GfXm@k>7=#@&PnizU$IUz&20iTN?5BX9=Gs5O?`57stuEeX=MD^>Fpt?G
z#>bpQm8g^EdJXt}%@t;l_?asw;uY&}UPns{FlYP>n*z;8E<s_CxqJrLPnjcIpefjV
z`ziQB%nyIXV5s>!4}jC=?b|ST#%xdeFX%9PTY!d}*ImSxo;62MyU{sw@Bc6uVP0r~
z?DOUaax65`%%$&PMwy>cEPcV;>jZGoJY58vE}0|g-i|h3lE9|R=1_mI$C#^(7>qSn
zKZeXWb5I@BUol6-VeYDVxm|<Fc=Jt4j3<~QhQXL<ZeIo~lFZ-c0!udU-G)s_F`uDC
zZ<<-U0wCS&xes$0W)~^MWSS>y0kX`whp_tV=IRiTWSd{f#Oia*>aCc|HETSvh&(gz
z0!Z@BZtq~Qz<g&i`JaX6k9Na~BJ;L&SX#09hiAY_%yX_o#SQb~FJW-0neiDYZ<>E1
ztjrwnGAt}Nf9wd;D$H$Ebh>5U`ym)A&2H4|Rb~E@K4xESe$oeU+dP|Mo*MI7FU-}N
z?_7bDI`fz1^!@pIa}#~gxxsv4J0=^=s!iC7CbM5XXzrL@R$vu(&D&cr*K9UZY2=>S
zF&PS5%ntPCcwi1u!L&B>nuQ=~H!qxqxeoK!v#<%BX5Y_1^3d!`)yqfb66%-hGUtB<
zlE-H6?B{U*b(?d_fcBVkc4BLun8P-LwAbuJjWd1bdBNcCH+%2K+<@6>7#lQb4$Op@
zr{>`qpnPUdAVY`DYbX^xZ2oL9C`Zh%#X{z&dEEf47&CuQLC(1OZ}N#9EDY)za<l|Q
zW6-|eGIt5k0~YH=$ab=9UkGUjE!mGC#@SNp1}hF(J_^L3i)E|`;IPGg7c{wA&QQhR
zh$W1&w?{4hCm_YmvWPO4?w0dHV8<+@Lr{3!5>LnJJS;IjVE42vKMV#h%bJN8^tM~}
z4&j$MVVNTZqmO0DixBE-89E1kKg$w6)cafBQe!T_;z0ptpk-GQK#(Py&ib6PEc+gF
z!Isxk!4P68qf&dQ<>^ffp0;>UXnMv{n}xwJ%P?ij!Y$XRAa&NlSqpH^VxMsxMnzbb
zQybcO%j<FAxM2B70lgP3Rg~$uWXU@VgQG3|3qf)jrx`F8WBH^Q=Eqt(c4CEb7M~E1
zT(SH^&)x*fhzIx*E&DEEElHNd22ftJR8dTsY6;AOX=#?X=3p+}@}8Y8<P6KNyMbm}
zc(jRGmMN5*y>9VJ#ay<fjS`SKmY)qE$+aw}=7~H@&v`5+-%?M{^#Y4|J}3(<A5s#y
z$ns(*K(S@yKJ=DY&XRwB!_s#hSgGY0b;{hdsOEyN%))uk4p?sap0ZaJmgAJSy=8f^
z2Uw-0kZ#H<%QSj4R9m)u1<KnN!5@%TV@YrTR%@|lfTYgyrV60m!gqja4VJ&M02(dB
z6s0s-ey7&|JC+N2Fx<7gzZ#&~vN!-T?^(jc6#unYF8+btyKi}WFF0B)wm-rDz+$H=
zW}C&&i0y8-B-27WEC)XWWvAu)PGAo$>05z4vUt%)DY`67N;W*U^y;vO-4^k3fF8@M
zFM|Dv<rOBD-D?S-56V8vE)VQQzhxn^BKAoGmX9`panQ19JM=!aC^mrcndJw{5)N5j
z-39Z9EvY|XZp0Ez7wM?wEviC}S*}pXHEzlI4#qfGT_3`j1J(liHjI<i{R+TA>+(%t
zceZ}^EhrCJja2`0v6j=@?67qKRc-99)=&zDk64}P$#&H0n~SY+v(8|E)ZKb^3I>l^
zKcv>y<JQ<Qi1DzV3C5tObtcuLy{r$eL4~(fF%wcwSf@+|rH^$c9rZhD-A>OUU+b-7
zp!BnT?hee~x{)4*0oE`&(;H~FqLhl;$@(jW+o!BE=;jQzPN!F0h}DZ~u%Xs>DDXRN
zjrkvhp0TQ_Nixhj<2vTTtt&er^sMzSD(RfFj;DYx!uszJ7|vUN+=saf*4ijAT(l1D
z#Ii40%P7|uZQUAxJ-lqSS9^jc#u_yr>SL`bR0NH)&a41-#roIV*o1g1#}$JKR;wMR
zC0cK*!I)%i`w9w^t@1{&U$cHrAN5VOzLpJ!H0$OZs86@{e2uvb>wT(qXIk6Ism!*P
zZv;t>b(CC*T<bJD)h+X^EPtT+)>LW>E3j_=0HDySq&v3AI?D`$i>-F*%`UO7I}QFD
z)}SS@u+-|$1K&;ScDfJBtYdG0q1?K-4eS-xddjrkvVKa90+rU^{eV?jH`AAKs;w1f
zu-~@M-9i3mja5osR;_i55Yp<buS<Z{TeFH`aD%nk2=g1QnbhUjWNjXYm^;?Fbl={!
z7MVeE&-(rZNNKUo`WN7Vb^0a9ZnH+-f)(x7;v%qjShrHx+G$OttmH#$3Kb(CS<f$^
z_g|NFc>@?9TbZcGP3pE9D17a)wui&+C)UnRNb9$HCW2(Znob882Cc7=gYnerw-C~v
zS<`3}hOF5K@EZ(U&;EwJ7_nwjYrv>=(-+_yvof4v=(u$Y<(V98mOg;}w%b#w{&&E}
zX#t0mZTf34>Y(i?RotCz>GV%s4%yQDpyIeK)(GHXi=qxWPn%#1NW5&?bSU(;eM?8~
zPS`F}L$R;Tk;=4wwwsT^?r*DdgXjR;um1yIpv|@hltDJt8^BK4Bq;w+vIpDD>o6K(
zn?!ZTP}`@Jzd3E|>;!hk=0VN7VK!b2gofLWKE~i#8<SFhmu>mafiK2pnE@4Xwx91|
z^RC!-?10d#wq+Db$J?4I<&j`J_%=YI?Wh!#NjBw7$V|3{w_y<}cAFdJ$*$QVTtSm+
zGn7MUnr)Plx#_k^Z$fB>ZT&QmX4+=of%+`lqyMTIw$~`=$hJ9FVKF&28Mz|4wprv3
z=Gjctshw|ohx8WM7*sYXv;`gkdy(x(D&~r93p}8<#Ac6s1F~<}zMyJvscjZT^fzq+
zs<4#VekM!HZG6goSJ*u1p?k}gR)@JtTM<>js%*Q+m}=WQA7k#et%J_S*VwMjg0NcK
z(f?tv&UTWb=0@9na_*XJ;nXaA$5#Fi=I+|g+QYD4%{HC~Y`bSOP6ueQy_AQ+`?kYW
zM{l)FrKYwAwr9t&Gi|oFDlpe>+dv^xhi#z*pwss72?ih9nACvz$QG)G!Y<pBWGH-W
zyY(83>9+Bkf%VuXegW)>?czdQoxQgIb9CKtSyo@%QY+1dm6oO1GSk$u)NE)r&8*CK
z@4feHTeBC$!BhcR3ZiVpfyxpP*@y^&Y#A~H6l4e}8-CyO`|Et}z2|$*x%YjZJI*=x
zdGGjA{BLmkhP%K&+&(7;z(?ErozaV-?KSjW*x~IbKZX?}+eawfXmopW4f;E_{nr-&
z7~ekI3+gAfXU#?1<n|#tLQHMHB?ZojahB5coEak_DD7eF+7A{N#zP80?PV+_-}gR7
zjGX*0`x(#E(e?mC9*bIc##?RZg$Kj04OVzEIt>7NF<z&1_k)brPk{3f;}IR&4>Qse
zpwOEkCEuzK<2gFN`7+W?032cb{S_+x7|joW^Jj#S`T$18Y-k8%{7GpJL5v&`t$#-u
zEAr5IjM2IhB$%O~-#&y9LkTR$89Z|4hBCHO81Mw+xBo}58TphK6~?Gu18Lz5pLF0N
z7|SOBh-7T(K)0h9E3QCqG-D~nJz^L`bg?UzvEmuvPBC8G0hTz1%jc+coM!AaVMxy~
zp3DO4S%${~{08S3k0nBOJi}NB_2(Jx6uY{>IC}(@7a57PK}cY1ECfkpG?7OviP25x
zgJi~6AA+PX9(#n!OAIkprZT>J9M-2XHd0DKI%5ZI*)B7NsV^B0##40Ixx$!6uFgzG
zmk`EeF{Dx`%x0Wh0QETx5p92S88=<gmdALRHh}pIUj@VzFf>ab`zqs#5T!y!O)5CA
zF;Xr;SP|pQW{AGdSV*_FiWz^<Ub>V~*@jX%ql?a~6%5CG@+DU??$Jh}iXr<P3ac4j
z$q-t@@R|mpwTw?R5Oa&M<^j~#F}56lih9NXothgMy<-@}M#h1Du-s<+MRQ3LBb1U5
zni<z9`KX2QvL85G8P_S8e}^&h0@~UbPiP^mo$;-MMz(|DcokOMWjuEprF)F!dLTL(
z^AkY281K&lxz9Lr9u{^p*3-?(9)@=rtmtJt<_m>=jCX&6rU#6Ll>6Jyh?|GD0fvaC
zok2!aJv2RJ2%1rP#P~4|r6ERc7i11I_RpdBZ-g<m8jYijp1Dvz#>gf=<~ZZ$B@i>g
z@F$<rBx8Cz5L1l(bV7AvUYHI}XXeaKn7xN7Bmee3=Gj+a+J5HW?}Hp*zNiJjm6_6n
zHaF(FGa&BF<KLmui}}(NSPn8Rd&&QDi22t98hx1KOCi*kX<Urb5#~BEhSZN)n+#Te
zX7+RFVE|J~H?fa0zoYH%G3K)8(H6|~pybXF=5g{$9%tU6%!E+p>+b__f_WnwoF|!+
zLU4vLLn(L@&Rj$9W(0Eu90`t@k<8pJ;E7_k(k3sO`OPhqVwkl`h>2xZP%7^!=D@G$
zb{unWCxo76HquRrGtA|)uvDF8PN#S595bZ=vg4WElPH~Mo?HT97nm|vkc&)1CU6PN
z-|2gLiOkG*@Q@`jRrC`&l9@tUMpKw|<e|F6Y}SD%l^H}^w=`xnInC3Vg|rX6%q&kw
zM>Ckw^HF()`Ncy3GMURpL9&=@qCv8mCEG!Am_9U@<T5{^87+_bFdUWn%&faGt$?{?
z5|vk(t>kDebTC_KJ-NpGj1N-8{ObQM0OkgAEfq80r;Mf&rifmL8%$qv{gpDy>Hpu$
zn4=W*y~*5v32o&}-+!T^f;n6cTqSdBDY{n0Ty`3j)l8qqP^w{GtwUQa)A$93@)mO~
zJ%M#hN7fx!Q_swx_r8Jo;X&Bl#Ehj~VKZ~-e3;n6{A?|NtxPRBrtdJzeDKV*F=KB7
z-_CrEJ_6psY@u)H++}Vh+4q=EjgZpGOr#{`F6LKO0PZud&@sE4sk1>?4|7ohg!M9m
z9OU2bV-75Yv<FNvAI9`E18;x~FbCd*>_O%@eS+&DGuZ)_N6h*2032ejS_9lL^H<u0
zk1*ek02yUwlH+rXdFUZ<<IL;#!8ySUrDt`L85D`ODP|q*eVkZ{Ghvf6tMYl;Q}1Ct
zc>_EytZQ^4*~{9Fbz$Z{)@u{cyPx%!1kw($p6G)#SJvb7AqF>=|0V$3Sy}WM7!TI|
z_tECb;*!(Mi}lMkXgbJxA_6K7vCcgSmcy+6cG&C98Vg6shh={iihNm5)l>Za2<t_1
ziTSZEO`+DGwX_<n0jw>Qyc@_mYJf38tY7H3aFlhJW{6{~RQfnXFlz;^Y9XxeH==Z$
z^=JU4P}cAdFy;j7VFfBrvOc;5Kp5+z2uKNMB~dgmiq%fejcC@kIpqJ0VXdZLJB~G#
zgvQgX(HB6@u%4$mFrIanmiF_kz2r2wz>+LO<we#4I%y`b?lu9J$dcZH^(m~R86cNf
z9~(hZS$>oNmd0|TGeA1)zt7OK%d8060A{ehpNqa+VQryg07oY4E1F-kSZ}gncQ)%O
z^5EyN>YoK`F6;17NXugl(?K_%^)y{&DPYx8md90A5+z*}vSOxzTw~oU2E2$B^8ai@
z*0XL<Sj;M;+}{$`<aD&%U>#&bZz-#*7rifI6_RuEri0b=3d|^H{cVM%6|CV3G*+@s
zkVmbGb%0zv)vWeE(N@FC8AD|)%km8Xw^+A3&{oI#p0-!@ERRg!8d%{JY;I)D-wkq`
zwT2$6CYDbm+FDr~lVSZGmItkkZ7j=D$ZTghp5G4I!8#EG6YsL-(edaWYe0m`PF6eF
z)WteMLBad1|7hCkX8lE<o$6t|@e*YBvV67z(8oGa0@EI_PDVg)Kg;buXc}N0Ca>fm
z%a6hz4_WJ|?Gft~d2feUNA^JGFza;(#XCn>kB)(Ll(j7%jbp4;|KTAYX9YY7GQm3a
zD`Zcy-l5ENXLbSwg!iyl-Ue}Ddu)X4{p<j`+;@O|Vl#xgvSY&maAT`iL$o`4umEiy
zY}Y3M_hc6)fOxTGl+JaK?Rb{*Uk<U|=%Y}F*`HA0&zs%+7D_(smYw*Sec3ntVbc+I
z!y0JvV<)r&@6QfBfyw~(58fbw?CCUv2eDt(gB)egdJL5z?AhC({y2O0F~|&Me@YL;
z3ATvNXeZfklEWp8UHc}jf8p$vR+t#U4yG@UMY3;ZfhUR`@g8~@&HkEl9%I-s*B~aA
zeS0-3PqBSh10Tl@KMr!5JueX~XV~k$0LxkS)AT91bL`6LP#@2>@?p$*wv}8v7uYS7
zzjBd%j5hBH>>B53c>faFX(<3Eu^Y(|k<9-6Ss0VT9*;-mCH7CQz^Af%$-SP&-eLkU
zoqc@{^j>C9M1duP9oG$eudr=&Fvw&FlDj#J%@0FmHv3hYHged{xj;%T`&sfu<+1P6
z!7raJ7Qq-t0h@ar#jETf3X2!A@7;y$YwUCd8jIOO<WeqWZ=w5iW$e|T!or*ES83;1
z&K|b{SHV_tp`wz#%Z|z__VR-ORI^`ShRPcDzzEE)WxxL&+UnW5HUJvf&wh;#HnLMF
zuzK6U{%;9to7mpZ0@2L=@jO^t*bB7aX=N{<2-+R?y>a|7ZR~S&)%Gs?4_c1yu~*Ty
zu9Llqg5%w6-Nzt3?8IQG?`7A~)Y8wsz6mM@*o-$o2H8HFz%s;c%7@Hh_6yHL$_U%B
zU<xLVvpI!moM6BH3|J@G|2jdFGiSLLV)k&>hr<{b&Ldg@_H*vhb-V+dfB+1TE5{In
zk_V?|3dVSH8pgrt#fg0$QVw&%XgBH2`DY0f`f#3q0i1rE7|KNS=PY>#q60WB4w`L`
za`N^8c#QMJ94w>3oC_463gt{xpz;JKf}Wj|oP7F_N(9FwLMf6{KoRUHPT*|xB9=3w
z2c=V-Wq*LgaX6HidzRxm6Jv3XQ+EPp$8$`FVbev<G&k6kz-fFBQW7~WpE-a?;Z#z$
zFL9n;2a?JO9tH3+XXgKp;+z?jG<AiOa|y;|bDm6s>>N%WWrgK(1hnNV;H)C|`c=+~
z6ELQbqx%092~Gjs4yfcL(%M$V=_hYyHD`)WFg2WS=qy{yk)I_0XFW&HgWd*C6S=z@
zIWAE^+~zE%NJ$eXm+tsAb9VQDv~XlmAg!F&XcKXVvo0Gd+BkmhP~XmpKZH^TCu%$3
z_c%-G^Ol_)4?8%!I4gdI-us+Ozd>d<=gpJobuZ^Fq+B8Xz-gC4?*q=mO33c#%%gMX
z0Ov1CVI1W6d;s7Or{Z^zVb1dt5IVw%4+MUk^B@_V6P)nBp>UETUV=_Iar^KZ&vfQ;
z$)B)?`?Vba7w!l2AnxVrex)afE24`>2e>z@pwHpTo&P<k8`nJr(%iW#$us7`m60#X
zlgkc*!Cu^vWxyZg-f)7@L)_T2Acwi%ZH5)z+`zS9@!^`jg(hF_c_DB|xFJuY(vN#=
z6sGxe8JW-<z};*E3FLN#0UpGC<^!}Hb#UL_57rQF20b*#xqsb(`cUpO6sZj3t|a$s
zIQO5|0gT`>K82ytT>CH36vMr79&NGQ1UE=K%?*D7#+>1ne1xu@<qE!ql=IvVeuk6_
z+}<R#UF6;;M|u)>{UhL#x%FEiC57u)LbFdA_iJ+YrE|GaKwRd|y$ha9?rq9%%HoE|
zG5FbBJ-H?FxEgZr<#VIyy)WQ8w}bO4cW*DODC9Oji^^-<c6xn_xIg?3Vb{6t^oAF6
zTTVey33v2;u-xE&@GXRua#I}=m~oRkPHwAm?t>^;QNf)eXHq3M`yG%f?m;eCtGOF=
z0M>BVc!Tp6H~S2%sN?=J8}NGW7%d<T+@C0V(#ZXr{CT&z5<03iaYyMZq|IF6cQB@f
zdzw-KTe<H~0C0yp6zM>18<*(|a+jMyY3uj6ugamKll!a&-R|Z-Puu4n?qb>m^m40a
zK}8>TGwli=aIbv`($C#Q*-8W4Cq4knAotueQ1OuaGZ&SQxGnF}1I+zlGd;lE*W5uy
zxVL^omqxjP|5E<-829U0&^ykJc>>ZVxYu)F{v>zJQIIL_$hWZ6i5F`^FPwP^Js^8{
zFGQftg?FD~WqWzg(NSU_?<8fO?B|)6pzQ#!>?O!_<u%Z{>&9F17dYK{AzQ)e!FxOm
zQapM7$nSH^^x{4CEm#looM=@$#On=3<6+*W+pyG|m%kXqhqr`Ib-uiP?O-{=`z{v%
zKi-ayLHv1nr=TK$w~8W-fxO%&p(2Qvx*X$llqboD-eWuiIs1Zn>6Att!aH~hBXgV=
z^Z)pJC~qIVxF>iY{{Q<Vy!ao{i!fgQpAZ_(v(eEug4a&R-bmh!B$T3ffBgw7qIv7q
zLq!blD9u{2yaqW&{S<H14ux^NcskFV=J^hw@(j=8OTf?a-n#<P=XgfS2#n{&(K>(L
z!Q1yO#9ZKc(F$^rmpTun1l|`BXiVn4Oi`{BUb!#GCEmw4waiTAB~vn78n283aOu2P
z{(`j2JnV9?7vMR+fsS6`_56e`W%6!QmVXwn#vS%%^FAws%pBe|@($+moMwY1kLQTK
z0NMGxng^&Y;9W0-`m4OR$R||Ddx!3RUgLeY4!|Pbue1<c=k+kbS<H*N2vWk6x1sU|
z?-MIHOL+@r5L(82DFlF<ymI;_%Xw{F^sIvS2c5$zdCyP^R246Yj=R;oNXIM`Yk2R{
zgHg-Npn<x@n@jgm>v$97>#yf+qi<?7@V0otrY7Ej|G?7BlYS4D7G46KYg&2jlnrx-
zw<-xL+IW+BsBGu$q;O3K@8`APyvzIIZM5CvE!+#vPTs9^sO;jM`i|lV_jxBMj^52%
zJp)$s@CL|V)ys3Cvtb|4e=V$dz*`#z&VJrPat{pf*3ym4L0(iodjF7T^n+=Sc>mDe
zXNb46A9{y*vWF;*@K#VLb(Hrb3uKI^+yzDByf;n2P4NC>)A?_b=S26drg%SRfX9jN
zL_eN0KlnI|*~2fUgR%?%f)a?m{4*~CzmH!-@rV8VmGtR^1N@geV3R9<8To77_#Z~2
z<jx<r0Pex>tpVJVFUkeLi|-i^MF;t{lr(sVzjq7yKM(W&(4oKH{A>zV`|vxSM9G)`
z(bwqH5q{q#0R8wi-$1B8{{t@Y0sL}0?*{UlFT&6uzWp<d#ZmsNJ7D24{*FYj1oJ0@
zpdy6-EyYle^MlE?6Uxur3C<Jzg7d(g<e#ChbUDKK4IC81`Qse$MDU-S2NKEm42Fs*
zem13{Me`Rg1v$n4mvXM+`0r8r>S=x{edp>N-(>;19nZh{A?!WRUpxVl!k^3l3;qCd
zC8VVD;}B?>d6|DS7bJuK^IBA1;h(3rOb1`L5kj;0TgZu=&EHA4RCD;oRtU}GPc@^I
z&u=J$g#~>1dEl?|884!;kncZ$;kw3OB?0Gke%Ty!rkMYk6M9&}PicYr8~h!EXe;I4
zqEl5F|H=IzH~DXU4YSMn<G$!;1>Ye#jM_^6@Q+YY#eX~yh-&^KKd7kTzrGX-Yx(Ej
zhqPP#;uC1A<1eH4ub%%o{jd#uMLSB3{4h$CyUo8(k7W~oPBvsV^Iy6G3tRZ#j)AoD
z-y=Wq9e!d06t(eZ($=Y+Kg&U<$qs%~7=U;A34vg}#}A^T(|vx{ObG4fA36`#9{$Ew
zkY2uPDopF+N0IaS0e>!SL;Lw(Q%b@Be+@Yc2KnPZqVgf1Q-;b%{J+SwA^t0G!=_>W
z21;oi;U8*2&qn#7n<&9(jGswY(8l=zeW;z_zZ3*bll)(NK&JSc^=NYvY!X1Bi@-(!
zkG+D=cSFTKLCrS+>=#5WLfZks@07;kDhMY3wwvJPr@`qi=%oxf55eV6pvY4YLLn6|
z!4w6C4hoL^NbBDr!6+s392QiL0O2hdc@uaa!NFNT_zLDWfc1!A2BpOM3AT|Zz+W(n
zUXB34T5?MS3T}K2K#<@kI;9*He2ZH}Gmi;;KSx`zz<3<+5J3^S>`w?r&%*4Jf@)eo
z!USh~=>H!g1@XHfG)l0Vt{g-Qs*3PypAz_81W%mclN|t_7L0a7_Bp|G&8UnQurpCQ
zFZezV7A6SR(|$QoaEA8FNrLN7Lq&>UViCwCLEh_trwTe*(2yqhh>i*Af?M<iW(fXU
zjW)*>!D5OJX9~X8p%>W#7Wr6m1h?ssmMb{)A`p3k_Eo6N7u?zeg;xbf@1j&Fu+pLO
zn!phXz1Iax{zR!*P`VMg5`mpIo;L(X`H)#E$fDTbO~HqBpQc=Jl46n-f^!sDt#k-Z
zTtTr);6YB{YQZ}U)ZP+2B<FLTV7?Pfs~4m`084|Qmh?6X%3MKi3uJU4X%cX*;rDG8
z_`Hf9wg|qWeB@36k9KZdf_KQ_dSCG5W3ZxIaFqfyJpyd_@Bj<`pa|9jfunRGiv5C@
ziqO$PK`DKDXh`rm-3}TS4AIg&BAB-V12rlbC`a3vAdk|z#szaP!O#go(6dlKDOkP|
z_D%_IQ#PoRaF8B0XW^2S0PGR&P@=S7IAa2e4hYZkQ0Xd^&{N_jeBUtxcz5A;%0TuI
zK1CZ(PvQ47V2qcrQ3&8cVMYQ5!B_akdmu-I(-)(oe!@SeAkAN>qG)Y^uwoEG1BILD
zrbLkNJ33e#6}nPH^_WmAfRq!$eA>dC6zabM2@|TXp%dZ4ysZw<2w^83mLi3((VG(`
zWZ!{`XyI-HNQ|(x9bG#k%%#xES>X~2C7lyyQfwk#Sj&OE=Y`3%MZF;W{xn!F3d2f(
zOAuyvLuR6I>+?{UBK&MFL|+m<sz6(+Fed|TX~LMFX#GnUPNO8e%feku)Mf~;`+)U|
z@KzF}WeOuZfXEU)_65Xb3tN|>Ek{^3fy%4GcWJ*|DE!z4_%-3Z4D`21xPbh5*M-hD
z2rCxOq?xHi*hrZPH-u4i+qqQubpwP|3Qr=Xz%jE*_+C3|tA*X<U#k(O%|L%^g-0m3
za7(D7jI}zUiei%W!msP0qCuEh3P6icMMt$(;Ud~)-4Uwjf=HXty&9xl*uw+q5Qf}=
z6?cUpI*@z9WQw163X`9M%wAzXRXX~FRR<vZfzUGzwf#bO^3M$jn}%Tbps@WTARY>3
zl(hdy_#z#thlJOULE)(Ii5E~B6Lw_6rg7o#n*o>*KBPn8q;L&+%cg|U6l-%5ttOA9
zvuMemVA&&jiXwI{B5yfF?{$bSQ+Row=ow1baTnc+Mae_7<vz^!6m@+MRxeQ>xegDC
z5{9AhkjVWj4A5cG(OB5)E!zD6W8ovp{vHYgM4zPr7bt3^$ty_o+ZhNuDsnvzz%kKL
zO5Y9^1@3`OAtDi-2#$*!dsI*nDoWdqUPOoj=+TQ5h0voHC7Rv=V6^B(%1Vh5<>R{8
z%ve#08swDd=OKuR6MaR~&S}y8F-SWvdPEoXFNi)N$Jj;Dr%#|QLG)QKL??<m=Yl0k
zw2M3!$)dGlNJ$Y19iEVVN%YMnC`=cvx(xhfQRV<j86tl=16&d9pt~fQqL~RWG)r{#
z7^G#3stceZN0jp+NUrFOYv^yDh)3c7e37IGvI|5{DWUMX$Zkbtv1r{R=q(W$UIzSz
zXxt1%r6S%<I{%f4h8F;FQ<Sg+D#}G`3n8>dw2#)mTG1jeu-p=jkt3r{WK@E)USwB8
zT7&50F|;*`%(OeZEqeGdWZw}jB3E*o=*%*Zc2VIudJskNYe4Rb9O;mGPgGCo6`i8@
zuhI7>x<ng(g_u6k%enX|ABa9}hqQjtD!R@vAbLodwS%HLJm`HWI=l~7JQ5wDO~jBW
zv>IYYMJ+UEkBN*MK*mK!$-6NjQjlA3Qsg6olqpdo9Ul*fUk!o=SFtc2a5wRvh!{9#
zx{J5EL7|8E<$J(;isR@?vzM505PA=awJl&hB))MPnhuMz8&UEW^Clt9NBl7*N&1R^
zPJn4g#M8+i?<byl8d3tpOK7DH6lWfRlpyi$J>WblcK#jkW8!go;zPu3)4}36E*5P<
zpF+ivZ-Vut_@!cq2@|)_IERaw<i3p%|4m1qNU>ufNQ}671%R>QOEd9YoDvt&vL7d2
zV29At;%9;ZI3u1$JGZmqlS2@8PW-?bxOnk>n!zuK7toIJqF6*%KocC|>g50?idT{6
zBT2meLy%<g>IwAXlK4-`bxsu*I)G0TCkH@wx;RM(*_Xu!$*+(hj^BcDz9Oz{hE18`
zo?B?k63b{Gmo0Ac!QkhJlPH%wR~(rMc%Hb39_M_qKh0VNVn;Hq8CS)Rlc%*%{A3dF
z*Tk*lr7sen?*`9xF_SXKip4WOh5037SK95|5c`ssy;R&!i+Q;?oq|;r;x>x<REmG4
z1feSN8cH^<7XLwUsTy(MVszq`c)?Ay)rm#j=x4py$1x2&4dS@vP}nH`^%IcWVkzyE
zo5e~xPqm2uTLIQq@e`dWwTY9DLt49d7DeSc#LaOq=B_xL(tPiUhf>kjDHc&mU6;6=
zK8@Hd?xHuYM?BPqzVwPaVxYcHte|P*f%sPky?+DZCfX?viUVE;c_<D$3!X>fpx2;q
zNL)$3{jm7rQVhbF_{KT_$HgW80yiOk@^O?V#d5mxIwf9z7;q=a{52>!OWyT^F?%G{
z$HC$vN$-RDy^{Q&AbOu9Fa~Y=B||Or{p$mg*A@cdD*1*6-%YZX{E6<8vP3+A9uhOH
zw4M^LpD{9Ck{^ZuJScg+8PX0(K4pL$mK2|aUT?{!4In;}auuZbN@lsk-Xjvn7}Wbo
zYRD7kFIh>~4+A8!wWth~d}5^YUy$VA$I-*15|<LFI3_vw6j*~LHgXY#NS^-!<hbNZ
zPXI$DuTk>t2?=*I04F7?FsKNV^m0)Omsn_3ijcU`vl=Pc$A+O%5+V7Zqa`Ql2I(ou
zw6_6|lL+X<c3NWMK(ynGB*zP~&q|&k@5VXF+&94*FL|DU&YYJF`a{eG$pG!{E=s(f
zf$RiHBo~~ClC7g?OOhO@LT8dCbKU_UMG{V1zDtt7T`+2?lAnhmEKRcb2PjOJ)OSM4
zWl4z%Z5fj7<hZ=zkkrtbDN}Ou5b#-&gI_~Mw&XsgaO6m2^TCrV`Hfr;d6Mcg;LMjS
zC67sgWCIVfuSz<W!iqu(lXiF4BodlQizF<X&#y}sZvacN<lx6pUn)u22vR0-`W)8Z
zl#DzDmU4-M@eF8%#8(K`O38N>AXSogDBM~tSvn3)HIiB6>a3M`&p_oZ33ma8v`$hQ
zjkbEpx0GhlAlXQBexu~rLzsPAGLv>mO_C&9cbg>zUjW`BdCn7nR>@2B``nQ<MZ@ei
z3I6{Rwe6B=)4|#y*<OUkPRTy{LxV0!5arL@mt6l6EZvfbeGu9sIZew^pG5c_@DC&@
z<T2@&xX@jl0m(OW03VdxdWg1%lE`(CG9=mg4Cb3*NeF_?Ge;yV#xMw@lKCTG8I#QV
z+kx6~$y@88Vp8Iupw*Nln;gte(g1&uJ<^pb2z8OJ+l<m)=|8l?-Y0!G3Y`0;){}s{
zO4r-~ag$1mVXwRNeKrQcLmEmcJ)Y8EJ^}HP?oI;ykaQ)5o)1gce+zxy(&y(>{J}@M
zmbM1IQVBg?N2Eq6dgw28C%;jE^vZk)4U`s$(3xQAjvt^YM7oWE%Hz`MDFB2@KcZv8
z38@cVxCoPOq+@Tmbf5zYBc%1k5Edy7q5V{p^lB|Cqot?!10Eyw#^U6dc}l9HMLAA-
z<T}KhmM*8A-x=w=xsY~NIxP(Nc<IiUfIlylJ`Y1LNH<VNFG^1<07#G~S}-Ju(vQP|
zOOig|gXNNRJP<NdrJcXR>@;b2C*bMQz)yj@EM0yZr7P0cenMXynbJJEX^|ym((jus
z)w~OZIZ`{Ne&kBOy^gkgDT`j!0;!E&<EzqWihC4FUtbM{*Q7NRM<|lcB@cSBw2Iz}
z66rUT!GA*<N|R8T^i7)eZc1OK?7MR5Hp*YAkd86{uXIS?p}(cAmM*%9{?<renF4FA
zG?vIM={ULI>ZEIE@av^di(yQo^jIBa-<D?lj<zQ0)8qqdmY$)5MT_*u&ERa6{{9>)
z+oV|(w`iA2zJRa}X%zY8x}@KH2i$$>gBj>xx6~1-ff+s0$oUw=Ua6HFJ`bc(S&-H*
zEuw^|0qL7YkU?pxAH+PA7VSgnku>)vScar;kaKcGI<yWQ9hLU2g=u5b!^=U&rF*?m
zIU!9>2VhDn{2Den$pRW+p|h-eBdpjXyX2ru5Eq%>8T5XyEM5c?_sRaGBc`j269E-&
zvLpUrahI*2eTIjub2W&kOxO>Am#laYEC*#p6kIqYTSGaThh-gkX!DkBqI<tSvN{Sl
z`pWKgLG%$>QxQ1*WWO9l$zR59pxGcm_W5HVfikZy7!@Q7pv<JBvTgU#-(#}Sg-{qQ
z<F=v{A`5aspN`AKA45f`%uaFe6SDpww4IcV9z<K1>>{nZ;j)TSkO<k+ly@2_yG(I_
zC|PYCIHP4(mq9~}tm`+5zsJgY-iD>8WVxTi{5aWmx-))SCZ*T^j4a;+rL(e^XfJV2
z=1xKGcv<2kG@X|n`xSr-vS4ory(pVONhS%hO}|1|vg{r{N;5M>wp9ksOR{=;wbNyF
z4*|a{Teu&k3|TrtDvp_1vfxS#Mz$=6vb1t!S+u9lmsQiIv_O_jr{AkGDW%aA$u2I0
zrt7lH^kJT2*;d-{mdbiRLa9u4*b4Yf*+el$rc(CY8Az#;4Y{IJEfcW;za{&_2P}26
zwQqye%iPw3#c^9UKv#>KWUIe|v}V~_@~E}QR?P;YRrW7k`?w?1(I&4=mOw|_cG;=-
z(X|d)YX!vIl?5Dvh4*B0a=_9hdy|48_hl*TQR<etk?*WWRz%+UURgLT84qNa{{XIE
zw)$l#8gR&F)000a6VZ|2p=|Gc81qOr?{72?$+m2Tv|(8{#qURCyOY5(DvNf9O=B`<
zGlY)Is_0ptki}C-XHurR0nRDeqyOkxm;ZJE>Ye4?KS0<X`4{)VvQJ)h68iSbSJGMd
zfZWkj4Hd5PP2-U5CO@S@t-D;k8>}AkiEOZX%1!$r?V#L`Hfe|C?~u3buslfsP2TcP
z=cCO>zKh;sU-=u0z;Z-BS_9%IzeX>7pnQ^!AVKntw4pgFKh+69h`foCSdYusIw<ux
zRQ_`|$O*Y728}1>ee{@w%cspjDMG%UyjPL(%tI(e$-TctTeSSbHdqlOKN5>lti17C
z^zf8?4tbX2<Yt<|Ps_t;W=fO?&@7!KkMKfUviwOiDpTa66dbrDciBSw&s6yd%2`g6
zk3A1f>GIPyR9=>U_5?~9@|rV{eMSD06(m#sdlbZE$>)<BCtL18d0;v6P8+Pql@H8^
z&^-A!?ogjEe@q9K0{Ii~0e4mIMCplza>Xc&xhCI}2wahTxc@P{f7j)|3;<Cq->pY&
ziTu_jn0P}zkp$LKdH#J=mdQN|V9ZVVGRgt0l#3}*u1Y>T5{6dG=RF4NZ^<u_bEHmQ
z8U;YT{Pi+$Hpt(gFkYklHsvSXmT!6tidy9Pl(N+-e+4<3`2My0sWIT&<j*_>e7k(}
zCEz>cbu<=t<&V?u{hoZBE|GM~edq|%B@d+6>Au`VNlV@G&$mHZk9?G(m%Z}K{ZQB^
zuVA6{K>jhEQ2XT(By&JM-wR_gD8G;gmWT4Sl<MVpB#$aW<B<F)g&&9IPPES-k-K(4
z=%~EqDYT8rKh{Fixcm;q4=3cRr_i-Y`3IkXOv%^M;5#X1n*n!LY^;RYdlX!9M7Suv
zAm{O3#ZJo5*{8Tmp^g0tuVUyuplBDO($%5(iQ;i?idae^c2`_$g9;DD*g;f!Dm>`2
zfS2Mi+TR>htoQ`Rcq`r@m$HxI4+B_y6~|wMp+^++=$P-PkWm=jU-7{|kR70Sei{@8
zDqi*lJV^09?X`|7rjCH~nBuo6*c+^HxV{J05XF@wG#*zBL_>Y3;wj4OIH7Q-9Hf(q
zLRzWA6jv$jAY3uK0V*OC>KKTLRJ5-GJX*1sydp7*E}HXW72n<g%PEEPZs6h+rv0$+
zjAHg|C_JmUSOvg2MHrpkFDTACJ_GAT#d9<TCn#3XFPf;>w-==(#j(9mn5=k(qH8IN
zQd*-fDfn6lO;zlstl2ch44N;}6`TGB=Vir8@|I;N(icL-6~+7HfzMRzq4gk3k#ioE
z*$NS5VC5((=-td!498OZAy1J~4%zvNXn&9b#YI~7uPSEHIjm5zkkU`DDcp8~vq(`L
z4P&k=)=-?ZSW#OF6(x#)1EKeZB8d)JrHU8nnpv4b)d#>$Mc;qmELW5^fwMx<M%T3}
z6+Z-{RHIm*OYw(VMa6co-cnT3HM2U!x^gJ2SInoUv;mfawNddFP3X53-JhbeN%02l
zPns1iqX4uhj?up8j>3BZy4I%HMwvG4idUo2)}x5X0_j!kqR>^JV%09dA1MCJMyX%1
z?`?Yj1{C4MI;c2I?y`pp<xNO?r0D(;WJr-p^W=ykYA?MGia!O=JEq9Xhl+7UxEYlb
zil45ba#FGRHOQV)?7M?XXXS%0V9Xw68qHHK%2o4GxnH@NuKXNOR;@>+tFp2YC5M}G
z;X)MMm9Hs4Jd~wPu+3AsVKqu#N)LKk4l23yQyfw@(Z>h8mEY4P5+CIs@nG>)E^oo$
z9Z@<{$jnc<CLenJmE1H)2~eI`1{Fa{Pl^T}RW3RQ_%Y=}%3%mr7MNjnh(oC-&sL~1
zfPADUlv#8D3sZhh8?kVuDHMYrp`3dgZPCgKF7PqRtX{OmD*qv0#RcW`aA>-yyc-K#
zg7T@iU`3)bmsZLoC2IlnCM&nmyqc=K7>Twt<vd!B(v^qi0C!pG=>7q$8Op~fuyjS~
zVu9>T<t7#sW+|sr_E5I+y?*pJN4cH$^0~@8z0jMd6wU*nKv}u~fUC+<@&y+vlj~8s
zro5JdE)^*gFM_i~Swhi-8_Jcm8kQ=jvS3A-GT{pdyQ$1^(7Ic$oYn$Fg;Gu7lS<{Y
z+X1Xn{zF@!YUSg>sH{=G&;ZU_<tvmOa!Z*&Vaqz@%oV7tS5Bw%MT7FM2H+Z%!C!*h
zR#uanyGfaL3T@5Gw)GI!qI`<}Wv5lSjBaG!QO@b64St*Qcp_Nam7mZFw?lb-C1l@K
z=2Py)J>^f-)~W1!3~gP?Z8UG(SGHH7Gu_Hq%H-%#zA=o-UZpV)q)*w!gUkoYILg!O
zS8kzz@PP6z`A-Iwzq|qU50y8kP<o_1mrv{8kaC6w(uS1}m!ft=dG~1mN0liyNE=he
z{s9%^O6zj~PAHEb1<Rx|u^DYs$^rWDl9Q^5Vhnp!4D#aaQ_b=Ne81`{Z7dF`E_;B*
zRW%?6&Q10AJecOL+WacoJXEu5DgNiFdbS3&UaF<^<R4VkyTF)3sz2kQ;;_oR3vJ%2
zMw)beRAO3Wd{rN=MCq97oomn=tQsW8XNb!0XS5wxb)QFNsA}b97;{3kNC9I`s^s)b
zhN+^TM_<BKyZcazP;FWVoFh_|(E`0uDgnLz(W;H_0Ux6p{~nF8swNo_r&O-w5RX%R
zME=CnDm`5>JfkxD!ostv_i5D5se+5Z8Lx7l24Uw_6*MnjP<3xc<weyO(ZD6Bo;d&u
z6II?cX(p*QOoJ844%JFJHKeGDzksw$s+@5kQdOT2YnrOg8M4z=2OJ=mRYNp|XQ(uD
zz;Z=3`!A48mHih~W~pB0L2tH-PtlVc)g3w?<f@X4V98T0@kf{PRnxx$=T%kYY>aQA
zs$>mVuBjYnK8M~SmB)K9@w&>H3@%nJ`U;2=)vDEyc0=V%NgJiAL(Nc8rt+gb@lDnH
z>rq**x=i=dDpb?RJ5jC5Ah&Og>S=OI)T)xnvwKVR6D3F2se;15Qm<P72v#(xiq`?x
zs1iB;2J3CryOb*0q~d)Ee6y<HDadY7jZ6oyRrNR><?pDPUPh@+Rp$kv?W$dL=IKyX
z9)y^?st;Yka!>We3oyG=b(J;<U8>|wXuGefAWvGi>NNRedsLiH0q<2!Ctq-%N@}P5
z=L3}!B^LIp8p%mHpbDl}W>7VQCdh{>;a3=_N2>B|AVaDRN^lOVvaofVIigxi{)|yo
z6$fNYl_G_van->|STUh$z7HvrDwQ3jDOF!H+MLv5i(#6Jdg~<s_NsSWp#PuVr=Cff
zE3WFoDJXPPKa&Ve?&=R72hd9$!3H^~j-w#=A@$C!U^%RQkJ1~x)uTw@oav)pIRx3h
zYNiUMBkBco<nmMJnV`a7eT=q)0qTN}Q3_O>z6WQJS~v~;JgTlm-~iwMRNoS!7_3gF
ztn3iAmbUcA)#K#)3srwkKEo60>93=7Qhkgfx?$=ha>InHU1;HpP=EgfNTixa5zZ*}
z3pX(`(P|%ZoW!W#Ie=1}`j0KJ;<Vb8{Mu*KLW+#Wt7p)iQO9|80Bs8|s7vYl6&KZ$
zH&9AYuV+DMqPp&FR3@o~FQLE5>Nj6UWr{j229=l86T2ZTRXz6`$WBvVtbovT^}#Pt
zx~x{JKr+<Y2v~7N9Y*J{O!f3Ouw<z>Izw-^`ll91$#JMVX;IEquQ~(s^VH(oXv|k<
zQJQaoI_5PPb5-r}27byyHJ2g|*VGc4rHj<My{Npd{+7m~SUoEg@DjBq4SLJe6_oyV
zQ(dfu!gBRA$`PwjFL?p*O10uGv{k7unW3Rp?HHq@$Sw7T*HBxhj;KWGp4uxCLOa#N
zBB<|Dr%-m+ef2I{&brlQsZigeK6e#Dd)29KsO(dxl>qlZ{f`VP`qhJE_JG=rl6VHy
z>Ey_JsCEv9hDT~s7C490M`~gHu)5OGg~k!Jjt)zs>eeqIdrX~Gg`pW&yV621p`M!v
zpp#~{H#nU&Sy!NUkLFoQJaf^M#G-Pq<|uvQX`g1pO91TGD0hS9fM%5Pnp`z&$j#=a
z5wAkYU8AajX&#zg6d3Z<h{wqP;-#6r4AKs2exq6Mkfw%C<cBr;DNgIHS@-~!`e>qP
zg7VeeQ9#TQjf9RjewwdpQ1aJ&Jq@J*O*vf&3Dmqw;fo;6LrUH|s<~!>hGUvI38VyT
zo(@MTMB|l*(s9i$ABz8lYOd2fc|!Az0%A^TKB7%tnC1{YP~n<obkL2^WLVL)NKG@n
zKv9|%w5mmG%DeEx#AsaTBonJiqhQD>&E#~*j?)O92K=-pl=kUoG_~ZZIjfP=>~T(0
zN(pxHn%y`zI%b~NU`K)%K%<=la#2%NhQ<WVeI_hT)O<om%p^_7R!B?M3{sdWMbo+!
zJ-nnjT?^T%niuI4%xRiPSLjXGWYGF`S+knp8JfEx09?^rpgZ50nwL+ZGE4L9XONk#
z;r|EX$k8a;L31^G=xCd#=?+H^^EHF7Lui49eFBwNHESr_w@~wLJ!D_goLvk+k>-a2
zR9@F?q~R{s6q2{QRHHwKQkf<y38kBwk7)~2uJL~ofC|koG!s{9URjU6RB0rXS6J=P
z1f4>EYc%sI<Fi(C!2uPwG&YL3*J<9rhRS-)2OA)*LGzjx<J_p}p=|qR%_DLUw`i^-
zh&r=XBbg6rcQiXFZrG;z?oF88u6gWxl<sLZP`t8J6SxiVE=`ahtmx5fqN8Q6#_<bz
zdipfQYBUaL>N_BGQ1kOLlpbm_Y%u1LrnV0T4{4M?plw+5Xc0;ynvO$|J*qiLiAiIc
z-)Y-Du8E_Z)Co=aa@aJfnMHocDNO@qXE|wyeu7?S?Ut=DZI9MU{sb2-%RzTh_G&+%
zYn}(RpLRjEtM;V|0Nu3HX%FM6UDXdOytI`R{XD2W#{>S5b|)no9M&#M0>E1vM_C#^
z+P^BG$yckQ)5Z~P*1IsqPdh0D++X`~3p501KP6Xmp!Ug+&=#cKFyesFquO0PC?3-e
zy$7R$wa$-2MTmBHEh<lF<E2n>Qd>oHXqfh;f6>uM?QC+BMQMMX2@<UxS%kJ2ZTWuS
zVzsfaqI62T><&tC+NbH;S*Nw<EKqbtYjH)F&T5~gdoky<-|eFJFJAkt8a(H<-+d2F
z7qnX*g7u<yE6qg-+7X)i6SW2R(BCBOOQ&JsC9RYa5>vJAeDpU>yEq0c+1j-dbS+2g
zPF{jsttu5(<Y}W8qcUIn2Sv9EwEA1XUDdAm2l@)N`#zxc@0!*~S+_;n!xX~0u8n;H
zh+^%d5b%^}&;AK=LmTV^O{Lltx_VQljVyrdo7%<XAu89Z=YXY3`!CHm)!KD*s;kjn
zDMeeY_Aadsx3p!H;8UkP@&Ke>8}T+O8?*`Jnsqd4T|=S1Sv$KGq(%EuI0m6r+lw0v
zGw*1R(iW;syLc&nigxV;W#M#aKc<+-UF{PYDBaU8Tnx_p+5oyO)~!vGprbw7LJCpz
zYX2h_cAs|hI{-Y;_D~*4zczUnOdHUaH$dN@L#w8f!H~8j1hvE3LAs1FqJ4cjgpO(t
zP<HZ|HkjV@ajo_;@Dtj5S3oAUGlIY}r4^c>Vvp`Bt#K|oJI(ofb=po0!U5f;J!o^)
z6_SN+x&ze^=BZ0~92R=%)OS&NQ0Hh?!)|X~d?<=Oy1P^8ldo=!Lb3k3;b+knpsV^B
zvIBJ$k-#6*4bdqlST~23*bv<*PbiGgZMFjtsaw<xDN(xT3sH*J748K~jP8X5*c+>B
z9fGh^I_^H$6sMb_47t;~GmZk(p3!ZigYH>fCOM(b=^lLoo_O7=?ch1Ddy_IMF6h1-
zgZhg)r&_2_(0P*cIZ=0Q6L3koG&-{+>w@Xivnjg48&H2q*Gf)~R9&1MfHYnGZpcj6
zrLIQlvhIx!0LaiCIOKr&S9IqNfn@5IeFQ|7?yWEwoTGdEEK0e$o3mk4o=(32R^;m%
zm%^q3-R*ElyQ+IL0F{NhQ{#YN(>YNXp-86*0^quC1^N7nb$&;outb;i9!$HTbD?aO
zQr+L45M8EoQ_%kNrf!68L6z(JQXr;6XWaw!)jDPuDr<C~lb@_schnmO*Xy>CC%i!?
zBQIT}ZYyy%>kiY_x<xng5N)kGemhEcbjCF(wdq_VA*Ee6{ZpvFr%R>~eW$LCj_F;x
zd+;DQX7=b5<nr&;U9kh$r>pxNjSqCMQ4UkTF7iXP4d^0Hqw<mN&>4*EknYo!Aj7(~
z`5<FD1-7v>$8}$R0?r8?huok}`peWMXZ=nV+V<%87Q)bd`s1&na=-qCtq^@czhoFC
zhpRq^{7r89#u)Ip>s^n4c<blSfiXV%m-mAB>UT7P<%s^b8L+}nZ>PuFU;hs6djs@~
z)?<JJ^+w8G4buNR6Q!g2`{W5YrWd^mV}kWBrJxj|Kja2uj_X%%04`LYxCCt{9C{ZO
ztU0NFBM2l+pIQUi;d;gyG)CypHo=%k{c1{~iqikghKgwYXfxVk^nL$ATCCps4%$xX
z-#iJuae5bWj-1xlJ%e#RqyKmgG@aEir?=^xew5Ov<Mq49Nq=6y{8`{G=p8ryMdL-i
zoW5$EpdX>fGf|(p7{(;&Z+D`Utj{Zgv=lu*0Mah$<H!M$s{bYg>eKWYS5TR*zkd_(
z%lh~d$j;F3Tn?5i`b*EDl&OD>{Nh=9A2TYm^&Zr-9Q|M3DCO!W9Dksgr~k4HJo$Qs
zH%bNiowNtJs!yXpDgK4F1eMqHJGP^;NdF-hzuI;EmS~t=tQSyly+nV7{H8bbQ<R8R
zs^1obQn_A0@s<kxYML)9^{>;5UZX#B9F?{D9uCMY{p`DR|F%ItO7ZYUeS!;sxAh{*
zAZgLRz6jD<^`HL@y?68vZbM;*{!cmt-_<`x(TIEc{>>2DsgDl<OPBt}Nx<*xCs#ps
zx1L7_>>j;<PLaL(CW^-Q>Ep>I{6PQWYWx)a`ezo?_m>9sE1yO$9_m>XvU{ZO6GQKi
zzL^F5u>KP|Qjh4JzXW1bpH4X+WBL(tfQ;)y>6Yk({wFV3KdI00ho&k0hhL(<P6nqE
zv^g8T8bakB!%kWjTnt-^LG~Ip-$7sY8O|Od|I2=Z@Owx*U^qtSB3DB-Ww^Q-qBSta
z-4OB{WP2Dwt0C0Wpf^Chm*MA^Kn@z-l)<z^2K<*JwjzcnjNtS(JQ0aXA49;;DES&L
zt^wx}gXbbt`WcR0gcN^+8#zS-3{Qul%@Jt$G#%Ci8LYFwbJXzP3Yd7zP?HVy!G?rn
zAVLiKYV_i`!S)PH3pF&++kC>X@eAlZX{c~VTbN;i07AnJew6hWVMx3K*^!2La^yuB
zt`&hq8-5|vVhmSko{BXTK7gWA4#PXN?8g~iaDwd9hJSW~oH4LkAp5N0Uz#b-84{lW
zYrNsB2^e$Uuu%oT1w-X8kap3KIv27N48PBUy@`gi!7wJt&@vY+$%edP3_^-wMJeEy
z481&vPBmPnEd4aYx&&0F8yu3)z;oH4TL^_2hS0BJ{uRS!+SFzm{&^7!vkc|F5Snf1
zdms25!y91$<{H+M`!&z7Z4OHLhAHxt78s^|3iwrnKOJNW4c~kYz%|2n|3O2M;kQ`y
z<+`Ci8MtD@0b0#U48J>$LiP>Ad`fV?Y4|V}wdIE8n^3AS1d*e+(lD1YfvXJ1o`$q)
z!z-(yu*Tp*-x;Vi{Pqf@-7;|b0Mr>Y6pF1kNKT^n4Tgmrlo}0L^8vVR`1uNKYBIQL
zA*I=nz7c9$3>y|vOs3T!wgP|0kVj7BHUo1#df#psq;#?l!`nMix@%bM1jIc<Ds84a
z4fT}m+htgA5V-pWrzmLZHhld(Sb7ZSm|*EO>?A*PpTQUf&IbmD5|#ai6B8JV0mF4#
zZwC#PtLgtY9~y?}NdCyM>Nt3Y3`^&taoDhzP81`CvL@h14extE)0n}VcG%;FGZbZ>
zFceetWYTb$?j}tcW|M3u<9l?i&e@pEM$h&dy(pxz&v>1_i?H9gfii;*7?*sCN>^h$
z^f_j_89V;~(A~InGYs}Ht|oVgr*UoyD!q)m>1{q}%=!+}4jIqUH)jtUCu`B>ZJfIt
zl|IJ#N?7P?yiFdWBgVAd7-v6YaTU7cZ@du;Lj#Ph<l_%CTHi;Pf{Yz>EIMlJoDNRM
zG2>av{S7wGBZp6jF^3J{apOEX`h*%^PJxOO#`Qe3oizTl5xoyHKDHV7aN`GCU|NJR
zuLGq>V=jG@Cd!yR6IMhU8`>Zx#%QL*vsmMe4sf0_x^03namKDaXgh5Tq-X7n!{}nc
zkABw3qBGAqW5JIwCf>-+0MA9Ekv4J(#uoBHCmMgC>qJS$#WP@cvN6jA7N!_QsStC?
z_{Tf|QjO)WqLgO*#2>=ajg>3_E*m{xMk&L1lFmw5##Va8vW=_ha!-!Y;W`}(^Nn@=
zC>9u>zYLzM#sqrgi;P20!|v<G9P$7b8y}}*RjILxoLFVXcRxhwrt$j6Ah(RYdr(<t
z9HWK4-dLXrVGTxo4{(jfx5)Ex+js%D&1N<km(i7wW}`QSJz9)g9keZMHQt~z_#NXP
zG~KlsohVtk-FS8fNQW`L3M_Yx`&MA|?in-5t=MVgm!Pf77-fgv`^K&oz`Kpptms;g
z(PtJadyVF&fa^0hP+;hR@jT_G^&1nLVbg$d<C~B&XtcCB!1K^JI)d6q#?OopGi3ag
zwzy-)t2E1x8)s9>%7k%=4hByef5}1RlyT=Z0Gv#B52C-$CP@+6_L%Zcz^47C)wCQP
zFu8pNoU5rU1T1c*9$IqTO$wT4JWRolL%pZT^gZRDd6_=tqV|yKr5`~Ko3_*Sdv6mX
z8^5oQ$({o-zNU5^@JCF!IcW1U9gcz~e^XpOSOQFqAEGVLw2J|9)YL`EQpZfIGhtz{
zX${>_3^8T4z^3D-<&@BS!sPNQ;3rM}h+{iuhM9h&BW8qYRtmZnY09OzWt6E>3NbMz
zUpfZHno2w{GN(+fl(G_MvIYTg+LX|T(m7M(5|rXiyT}WB-t;0(lNU^h6sEmsx~K<B
zf@$IhSdnNdkB7`8(-VW>Og04%qU1<5c@3k7X{LGiz?yCvdIzkRP5&@JGE6t)QF+C5
zbr*zYno_o)7g?s8IJeHsHZ@EDmt*p$&sgM|z8yr@@=P2)0Qn{!t@j0{=|7_Fs_CCL
z018d@6ji%snny11B2(#B2rF@z$|<mP!}Q--SW{{`NQq5lrtUw0ziIOS3;1%=e)95F
zm^S61veHy+0iep1@ii>0HoemYQe)aB24}75PzKuSOlRqKPQ7VmH7sl}ojL^4Xli;D
zQf`~PFMy@VG)^ybv&r%A4m7ry!aHGptLdvFF!7G5TnkNYrY|N?*=~v{151agFb=@G
zrg_Ui?wOnpqq5VKO~>UfQ`j1C-Zw3eKwGzoPeH*R6C(mP^_qAIApNGv`yd0RF#`aD
zXoLD8lhi?{_F+@hJ@jJ4)Ug(1)HIVa5ywnF({nX$n)n^SDN`>kKu+d?t!Q&Le>fdI
zbTKz<Mde<zB?5!D&)h`D>^J{33+fM;jUtp>&970E*v;HH1}X05s(%3RFk5J?@HBgv
z>HOzqu3P}2ht1t#Al_yUrI!1cjd}om&CFS-JYrr-F<d|M@x2h^Z~ltHmjUK`^vngC
zFVeO-$h@28lB4GJG)o^dr;&d;*c{XjV?xX)V<Gdnx!(wQs9F9bSWcM3-=h0RC(Zwj
zLPeOlmO>5T<{9fiqRq-1z{i-cQ+i^o`8WkpPnkvJJc~02l;dYQZ4M-t#ToOgGE|;5
zKfN5dbLNNuka%-q8d%Po4_89;1#?Clgk3bhLdVtw^Ra%AMDvSp(EW!bb0URglg++#
z`b{zaHXHa$=7|;{QqAL@P?2W-l(tvt=I_Zdec3$9Mq7q?b{ue5%u{cJWSXZ@vQ(D&
zGZVU&Z9cyUoH^ztZ=f>QY&Bt+^UUYzB$02<w8Gv3^9z*9;J9iISP6xN=AYie2wgL8
z8w4pbuUCTgy4kZEti|Rp$(vJR&ZRTj4fBd3kW%w6w6vF*ooP<FY4)I)O1Zg&=H&{r
z56w4~=56o7m@0Fi4W!x}PzF+CR#TQ@t=X{|rCSd3ZnCt_{0zM-^=2_mG!5qJ)!=C~
zFS`$Ex6P@CA-l=kLtegSb2WYIuf_cHEU>hi|Dsu--7KaQj1IHkJha_4pBA9<p7~n?
zaGmCF-$q-Pxq~7z_sw4Kpu64XGzw<)m>u(PqociM@1LNl&s^z(K0Pp3Tfx(B-b@K#
z17`nqs2ntJU5e6>nfV4dht1DCg0vB{pdHqanirA!F?0T3Xd5?|P}0SO*_9GkCe6F)
zHsF-`*LPu)lVveQqMR*hzhZ#)SWY`GfXBrmia>F%B{vno1C}DXN91a$N&&*n5>5Se
zw=AUNjfcf528*X9Rt8O8mYuX&I%p~X0i{D0=Vg#`*z%YiHhEhtWoYxUXz0oHwRkLm
zlp_`^IT!sb2gw8IZyA1_*1rHt{|*=xXgN+_(Fn49PqV;LOZNis9J8FGZ)yZvo_iZA
zLM+j==Q?i5nhR+sE&8))3$w_60xsO*`#OY0Sh{P$5^4Em0>c$$sXYNJqAjaw_Z?$-
z-vpVlmOD$qa?0|kjP{>#mP)$!blQ?jv&b3C?-Y$VYx$Sl1o4*ZbUHe3@u0Ki1<RXs
zQ}?2!knRX2SQ!2QBwBj*qb<oYs~#lT^3M*~lwuJ*2Pu~<E)B3L)e<3v!poLdp2f?Y
zVOe(%l~*hY7<9+XY)jovn4e?u*aX?RmL5AgnrB%$3KjX5c-rn4SZx2_7g+*Nf~C;H
zrmODPEcFG@RAiZ=NY-_W7x_AhE#7M(ti%#Z5BUwtF7g?aTB_0jD6_ok343o^%m%10
zxAgr8(T)mB$D3%Zw9KG0VwL4|7^GEOR@3F88cXB~wAET%*J6NfSst!}iaHB>J33Qu
z$$J&D8!RtVIIht$&VjwREk7K9-X_aubb+ARGEA<a7RwIWJ-1pudw{k(mO3AhHjBdz
z>N^~kMlFDMErW+4`<^9)R+mo8yR@2iS*}o0_kGJ0h5x%PkJq8H$MV`AFu&LG`oE~`
zvsf1a_rQ|92Hozr@F<UKz`~-0ib2coL>^j7O|asT<yQmxGGzHY9WsY4mS@qW5sRam
z995&1%}o$9W|=nvq2rde|4=z$nI8{Lla_h(SWa19H^NXSYv3tVI$QsxIQSlGE&U=c
zRtv4dd#wYs>)&S$e1xIgZ|zxujvlaf^TFb3-BARYZdP3kO77O-7r^3SwK!-y>1mDQ
z0qAADmXF4R)+qW~!XfMRI;c2o{g47R-qy{urT4MEO8#D7>l_Ne9kC{*L#Us1IeAt5
zt>ODo8DQO#1VEs*v<9MstULYC`=eG*@){qris)<Q!B&4-4MVKy`IOmk-1;Gfw?eI3
z_k;C>)rID(lhy)nm>*^>p=5$^>!=JY5!Sg5kVxwYJ>5~(ce}tDZDpN?X))H>QV5N;
zCQ!uvl(lsLxH#)JTJ}#{8N*;XW9|P5xU<%le?iV!KYfh+FY(q+A2gn~I-SKJUa(eE
z)b*mZei}3-Sk;s0Z?bhEE#@iKjg)bA$@<#`$WFCh&IKUNnnjnA(ybiIB)n`D(BNlS
zXN&-F#Tr7#noR4<Auu${T6zS=WLsB!j#7?wvX|n2xz?X)H=Ae8$_8t`)h!hG0_*;b
zkbTuUm!f)w*7qn@aLpRo56&X%??1w(>sH4FkYejJI+K=ICls*ahIQv6NGY{?u0dOw
zHOUBa)B0Qy6qZ{zg`=&)`sFApE3Kn+W6x1#{eZH&s;xV3Lt%|Ir~r+%)*5<oZ&?lJ
z(9t?;+Y12JTmJ}0slht@09G_wbMJ!OwuUHSVUzW(Mzl3s6*?H&Vts{fvb0(gRgihd
z+Du>FX|wjxQLWwjJ{=4?tb2pecGqE5|9`Er{&xX9omOr(c)F|&J`i)?s?0~J+j{pn
zH1$~7TQK;&)>HMcx6eB3DGcxf>uh?;`mOK2g3^Gsj&`ww*45J>`=OOjcPbuPs~$nh
zkae8|T^hD#z6_QTYkf0VMy-xFr-5h8`pX#9k6V9j1evftwE-$7ts5x!e#+X>31ggW
zUtfR~&bD<DNZVt3@;|h>*d(+i*lP=-UF-qd<Jn+wwQczb#LX6_hrRB$&!eEh!?r{W
z3q5V!^H6!nHrp5Q!?s!nO_$!b4ZooAh|O6Fqx@{+pF*g=ZB;!g18i@Ti!{)-{VFPh
zY-v1@qqcR6(3xYlvCm*ku<iESAR)Frli)mVd&>hXp|;0pkqEObq=0|8?OQ*vMA%%*
zp&`<iM-On6O`1&M)@a)u^4*=Xy|5aHINQtE+|E30dvZP6&e<YqWa4e@bcQ%@>vD$d
z1Y5-@@QJpb&mb+ymT?&@$+p69j8lrOqYjmqZ0yIunQF6903glw(gncNZClB!aoP3}
z-T%w5-4{~+*%h1XW+1X{Zsf$uvHe+r(aW`UzXe2r?c{clt2Sv3NTKZ!Ilqc*>2$Kb
zZgUTS-eMd3A>bvpJ#`q;8@9*E{Znd-r)j6mHhBo8o3=G{QY^QH{)SPju%%j1S!tUC
z_l;v_wauWwk5^;sUjd$4+f7>BZrR`m#FKApAiq()O+^uw23tL)P&L|8<N(~ZX*OXH
znrw5)2i9uK{TAx)*mhCAc$@9VOR%ur_6a?K9kwUt0dUurtN=@=jYnaKE}J6@aL0Yy
z<Ft9{w%vIK3VUpcln~Wxdy%#ceYRY>_VK`GCRb^{Z3aD81GbkNV9cPclTw}^+7A8;
zmPfWgauf~O4!wcWu<bR<Um3OK(5ZRMmPrSSaa&&}a1*v?!%;bDt6PD}DTghV3xt#1
zO8JS-cD)~J_t<ApaKXjS@CVsz*HA9sKKtL46R_VN<^}u#d-YqWbhY0;jXrtUs~Vx+
z)4qh#y1eXb{_m%<FZvlJZ~Gf3px4Jfb_H->`_pGodBnbfqL+Slhh!Iuf%ea4f+xtH
z`zK0A?dQpLam@bX1WXIIUpR}l5WAXEVvpPP9$*Qz_gSF#g#FMJ=sjs)Ou2kv_ILgt
zJ+Xhu0zAU*xe$GcwELe1Jj$N<9E3&N8!4SK#{PZ=+G6de9CWGTwEe|pkaouYT{_13
ztUcHT<ec5_PY8{-^U39S-o9ZHB*DI%+)jyh<t>OwvUkz7f=l+NE~7K4_N9|BCe2>6
z01DIXJ><E+Y|m0dLx$aXH)LM1htucRGVQ$-b;+_XFQ)i=wtZbR8guNE@hIimSG^2;
zp8Y&U*YfQ=n)3_nK{L>H)vkUQDhllZall`*GbngkWdD<V4%h9K+aSBx?oNq;CH8q5
z0B+a^D1uySAL|8YnSCFfhi=-BQ3$Ere$<KL?^Skh+KgA*S5KicHFgU*=4$O$UsT?*
zcN_t0o!vJID(dZ)b&%FzPauC&qx~_O3~t-sq~UI|KUt2-W_#WqRJPb>w*uE{FS!Ss
z?$~?i>P?&dHq9mN_V>O5XNO(fLH^IX_Vybn-m~|#qHCS@jh-M~_Q%K3?fdqRp9H?!
z{sOs{dhBb`z}ah`yBNmw+5e-7vETmj3uqg#yHRq=pnbg<@P~E|C8$5L57I$($UZU+
zWZ2IA5`YoA7rkO*c9S!RW87Xs8^H;C)GI(t+6&*ss887y6gqR-k@X8Iop+=z2he3l
z3r!|_cRZVmwtYLk`vSQAJN}G@F$Z>VKY%p%9lSV{Ja+i+2dC!_8*TZ#c5I^1;=vuy
z&_4Unj;k}ld3Z<T6xzHUJ7!QmrO%Gh`H<$j<1Bf!kL+N+2NixhDl@?9zvBlF2o2cr
zJZ1X^?od+hVbG4JUIXsvj{mXr9bi#i&)eR+EU-&i*n9657S?n%MorP!H5y|QTTEi_
zEox$-`E5~2acN2iMJ#j_P(Y+fM-T;+X2U`e1VKPhQB<&?_`Q?=_dGt1bI!~=bI#s!
z&di+a&TANUm~J*jrowgXO*k5%YyT0yNTlvzHAs|BI0^M=UHSp|bVO(Q2QZK7Vn2j>
zjL!52MO<QaM=78lr)!|6*D;-E5nzt%eCabK@w%UFp_rgM_!&$j>gHXBhbMJo$DuJ<
zH}xQ}Q*;wJaH+bLr@*D@&JKr2x~?u9L(0_sMOSW?ZsAjK*}9Vz=*!Us8eu+HS8Ad<
z!8~1xFU;rbZqm~2v~KZSG#2QlKLT2zF5>{m8J+o`Xe`q0ECbp(-BpTb6zd!)>|3G>
zKMO}ob*>R;Jg@T$g5(9=gG`VzUEFt=gmN8Eo3l!tindc#x^1<Pyr?UlMEk!>I{mNE
zzpNWYOU5g@emP{W>Qv=utk%t%0Fi6DT#DFS*ZFS+cSAQh4x_lKEAPfAYIJHkFj%YG
zd=pbyr|YMfP`$3y3hK9XN~*GI&^@gNW}~ivZll{eH>zoC(zW#u!u{8*ODclm9Vo(l
zi*Dp@SZdW3QH^N3t}_!;(xH>m5$t=q+%JIErL*}G+<hHRo8TVN^_gJ)q3%7}Np$Pv
zlxTURQ?7-<$GS&%0NtZoR0+%{x}KjQ@>G{O9_r6@4hsk2{_EA9bpcGDZW5Kxz0euO
zP<*M=(p&hI&fg58{kj%f-@MkHn-Bc~-5eU|Tir#f>~qn7ORHd4ecTGT=B5wKf~1Gu
z;Stn#>*LZOvPVCX-gut+(Fz#y(*Hx-U2pwp`hbebN6*rt*jImpf=Pb*q$F_u`VyL<
z0R3<DND9>V(FSg>e!)WY?bD~w4I89iJOv{A^^t9W3D)1ExX%H71HIf1>fLD#5~^QL
zpFRoGm&AaC>qF@A8lj&R3Xw?t{O_S2WzsLIgMPH0r2xngeN7@dkLp+GU@%5Myc}bS
z({H8g;+Vc+KO~Rq*VVy`c>TMy;Y`ry)6O_izn}ztC-k~Y7-5or(@21w)UUUKda}NN
zj!CELuTrI1nm#!TBwa6}&Dklv$()`d8TyZB11(dZN439M`XhAMCR=~)0=OLgO;5n&
z>W@);El)qw6V4Rqf1^*z73yU*AZPSnG{Jn4UfvIpv-)nj;m_&2sTQwTU%3<NC3*{b
zo|o$D7DC~?e)w{jy`UGF=u}{te)@E<<$A~Mz^>5GUI>j!{gjRHsY=h#+UcTR)C2C4
z-eC~Nds%;vPP|{yGqk0?s;{J7PPKkTGt{r?vvxxAx_<dwK;O_Wa0j`mA4~;YHTpJM
zAk^x0dm&P%U-z8ipY{6pXTsB4`tXqeZP5QF1x%y9m@eIBedhu6-O*>d0;WY@N&E9w
z{pa2A;;vpSgWWd$4_h$ac757D%yWmnY#Jo*>Eq8py;DE+BS?1X2hk$@zW!&rJRazu
zd=K(aKi-z^zixeCBkVrX>*!eCV}0d^K<m-x(x<<k=uMO^daC~-6ll-%@hMR3)mPpF
zXrKOo76zZ|XV73?=$#lezSJkJg!xzcskC11*Q;sk@><_s50N+e1WGCl=tGjx_*S27
zOZf*E!y|g9yBZEDq2Xp|{1hW}H!R<TMh}B=EJSx3w6q=DV`!vIvbRCC6p}uM<@8qa
zHAHVfqo2X*1vr0023@iN24xLMpy7-ShP2lZQUdSy8II8lGsrMA3fz8!NrnNMf(^@S
z(R#oTOR2MihFvnac*vlbg84dZ_;U#wLku5zgM=FDKY^t%gU{ap4L6L~0}^3)M2oyg
z!_8)JQ3iKU=tUb|)9&?%;Wfpgjv6*qgNre|q~LL^;Y|(ZBF?bP7ThtDVK%vO-0&^c
zb;KL2vtTK~ure4hCk>f@flD@I?*dGUp_M-WlxmnrcSV|E+E|P*-B5B3{+=@2poL9_
z;Q$LunFd2UxNO5^6HMe7EIXi=Yxrpc^zsam6VaG&_?|X}rwt~rG0-nC)P4nng@)B+
z@QmR#ErE&*^Qk7_tYH&Xd7LveheM>;Fr5PGC5GN*=(}LJ_YjR`1`n#tD>w8mhTST|
z-NzW=MS~BmR4*BRpo{yeVW1R-sts8)p>WMm7YLM_1~U@{`)UjyPD5+0;b|;1>I{RL
zLFx_sO^ooCA-5kQO$IB<LN*(AQI*sk!_F%pEryTAqOa93^dE3{4J+S)qiu!*!=cx1
zNWBMx9fryOfZQ{LYvEI;A(j%WU54fn5V>!#IZgY&2ZooAAoI{*Lvz_}NcDrIM~00*
z0rauKd<IPP7{aN(>4{<Zb#PA&LqCJ1X9mZGK<hOm`arMGP(<f`pBsW`5B<V0gbcnk
zY>?v@d1YwH1nD<)(>ndN;g64C;f=wgmg1iS23Ksv#BU9zC6IA3MpKf&)p(%|GvsDm
z`ym?LjccfQ$-@|u0ew%S^&uGaGA>#P^WH|AHL&Yrd`4LiUt{k?fcY7ZS%LT)$I)B_
z7@c2$3p9?mgx$TyehND8GcKG>@4q191WEz#H@4DSG1xeKKR^!{Z_ujapfPMY`VJX8
zY2SL-c!E~_A;xpG;S4pp<bn$`{$zwmxN-Fl@HfI(PPwB<WBN}ZQO4xGup4b`y9<#c
z#`-%zIciKPgM}F5pNl|DvBuTrfQd7{qK(Bd<Ayqn;<(Xw6!a5~H~xSZCyZI|0w&4m
zWd)6sMu`u&WaB~+L{f~dl$A>}PNyT|>Bej=P)-@$uV5@0#-&-9u1w>ER@luk4u1zE
z*XThh_B><eeJJFcj6-;^r;U?00kpvQ0lkF_jqN<RGsbKNT#-@a15#pq`d^&N_zA_g
z&l^{?0quhEG#z{>GnO_%q1-sa4`3C>{A`F+8o$!OnJQyL2?lY|7-WRPW#gm`AXkiw
zN$;xBbdwG)RU4~lS$EA?@Hrg5VH`#^^f!$z_rTQ{6WoASYjmY6q0T5i2(I4v+8heE
zjQcl1ve9^qHaoYCX0&f?GKPExuG#p4?&&+mFQ>v%i}BkCc+qNfzY3q)j7f2r=62&j
z6D5{9jKR%ly=PoN*G{J~fC1NKY^QRg`^KXeVeq9fg=X)Kaef{|-WoX_h}-tw4}iUU
zd+sABcx`|62R!uM-n|hdV0$eU_C;?`YsQqE*#1Qaz*4urq5xIK_Vnuz$=Uw$M_RMx
zZ=bjW11;P>^E%u=yWNrA2c_G$d7`m$`;-HKxwXBOqRyS$oBs<iZ~yue^!0B~xeK4%
zcWk3e$8*Q0r{QSej;1OY4B7E%CCHH-U&x`Juwxh<Y);#;Obqk+I|eBMR<gr=7=3@D
zY)9-g$Xwa6Zv>pVv19J9kO|z$zYh~(JF}xOK`}eO{T|q9J9&!NX6-z?8)$_)&mvbR
zF5B5caq%lVn`lQ-zw?kEMDFffPK6-%cFt14wVs{tQ^57b&K_Fqyx!>|gSwk@WQ!&4
zKObi%7_I)!3%fCxAm_XHp?JXgKGju)Id9ty{aEMCv=57SPEf#7l5;D4!Yjo&obJ?g
z=hXd>%yc%R=S`OL)($9SJNHqFKganQg$D|pXPp68=)89T11xghLDd~+oo9xi&vedt
zIQ?&g#m-58V4x+=BWY-*&ZFM}Iq&T73L0h3YiN&F?%YjvdX>(TXq{2zob?SFFFL>3
z1)nZCyVL&dvhyGcT3>Yzc?mD7ohN>dzH82hD2#I5nbX6=o6aMx&{*SqgA$~*Cg*8%
z*sac4`wGKuasKc+K--*eqxuyIMfk;F@dpfMX9C>2!Hms@Lp97ey3*>H+53Qai?O17
zStGMg3y~&f77y+YvkIr1#cfQ^U^I3!uX8b;=S&a16I|H7ry$<!JYRbL2C?PIl+DH;
zMb`}Y_P!(y|Nh|C9+>*@WBL}$NA0xYAF_hB_T%r+UTs3#bo5TFnGEzvNA>u7G8=&2
zDUIL4rK$Tj<G1{3_fJ5ZCZ*2>OxH;<cVD-4L3c(u6{LRiU_FpcGpih-{B1}Zl)q!?
zYhB-?%zTh|*82~jHd{=Kg*m^Uz~sy=qnfpO5x4R0AJ{o)pMT;*jOxcy+6eq)pqcwQ
zwgNH>u24K?q0bk<Ty)j|%*B<IU0QP40=i58RHJ2?HPuZlH|;+Kg%!4R2yEqYDpX&!
zEgYb$*Lk63&9I9wvu-<;Qm=oIi#gxW@*d=W@eV-m#)(u|v`IS{|K8k7vEqNmP=&{C
z<{AAz7JHa4D6j6xOrcBCi}@dwvwAZwS76tNnVbn^U&ge3I$ZK&dRV~vGm`T_+{e61
zf?_lC8x_|+VqX7>#>Y%5JwIPDZd4fE&rGIu+HTft6v!U-*%vV3$!1nyF1=WV8%%h!
zyG_9KVNGv<;>#-DCqwKoDn#{XHI113aMs5}yO;>}=R%O<tTjD{;#ux{SW001=_QcJ
za_fP1g3YHx4@vB&N+_OW*X9B{nVnPwgDLFsqYz1Dr?db&jdiCbPCA=JiRM$Rz8`io
zSbsW~l*LxNz?p0|ipqa;*rV^6fR-uxheBmpqRmuLlP$VIXMS@;e_Oy{uIOnG8uLUk
zRLq|*`kE5Ar$z5lR;NI;fT~jqMKh{k;*9A0cAylA4BOz^Sy3~UXP*;&Ms;b$BBzZ|
zC=nf608%Onjs*01(b`cI|GFR=n+fbP(faMsC>IT%4YUf;5vmHR6rKGVq)K#XC_pcY
zo;-)aOQQMHVd=8ylTtW(MZ{6D%~eq|?YOH&(<py)O%zER;Oim<<&<uSTv}lFrfBdY
zSf~-@(jm55(NkPFCUKo;IOS;TMJvCB#w}5L2t*r1g&Z0iMU_9n#BEUt-G5D@^;(#3
z7FkEa(j8F^U4$(nUpficDvHp6+!d{D2TGgh3rd=|i+bZA(jnS!3xoGW8)-w=DOyA~
zZI`Is4}GTlqDTJ&_5;y)13Djy?#_f_w`k=vXgm@nI)gkGg;O}VM-=xZCgF)_GnKwQ
z6;*CU<1^8sBk;FZR7=%NeWGoX(f3?*BpqJ75dD4v&@V+LgTTEK&7nH-eo^9wKyfh}
z^AE=2YBDRRhGMGOP)aeSnRyujnr?ReG+<7dZJPp(472y10w&Y!1cel{%tQld%r-lI
z4t8_QCeht`*{qIk(JN-XkDzzejID-bwOKkv!y3%CQWZv{*(-`qwwbwI0$97*d!wMx
zX=b`iKWvxT>M2n46xULa%1fLS2cNvf-Bd^9CmyjCGwUxd4n$*sc;s&A2Z}4`j*Ajo
zu7*Oc_=kBQdE#~VLGs08PeS3e*oF?g6o}2K7Nk(TYa1+_5ucR6iz2aO6<j+j{-22)
zE*5`20WOw^i+#~rDjrRXg!A~KDfBOhPdz|infS~A?3RnaTn4)pVkL#^Z<{a319p>n
z;(Cx~^Dpv2?wDT~4)qpuPkQ;Zn!iKSeb@ZS3n;XipO`_vmihZqkUsNXJ9<RCHJ?En
zEEfx#o6vW)2)PX}+$_Q<wdHG3Ph;}4$UKZje+wghfFr<S<WiW}YjO3z)Ud@$7Gnys
zm{0~1Y;o)@P!3ouruXqdi=wCC4q0STWn`Ge?=B$W7K;YZ7-10{N#B2ru~<&Qu?&lR
zde&!J{OSslWicRuOt!^WB{abnJyg7zZxQq(`c7Lod<)kKEUtb9w+k&c)48TI7O9Tl
zE?DfNwOE<OUvxW^TRcAug$j$WC!(>^qT&fqE?Q*JPk6~9WD)JZYb^d!!S7m&<+QG?
zvuNmq-Fl00*YLwMSakdh{YHx=v@E`DVZ914O%{J21NI$@EB$b-#X^*d#=92YRMOmL
zv4Ng29Txv9fWkeCdp97`WwDM{{0}T%Q3CU!#ncZ$x-Hs1f)^$?%fz*C|FGp|I&l(W
z8P<%}P|FiZ;KD3tQD{8eQbLc*2un!<U?MFWmZ2}o^3*d(MqBp(1Cba@uNr{HTC!Ay
z5ohU4UuQdJIe-X*INs931th^Td^%7PEyXXuov?gG8T=%ZrRP$>WLlPwh8J0uKWzeb
zj%6dgq;f6miU68t*>M;m`Ic?zP%N-4p%-wW<;g_!ov|E28~!58wI5@i&RP!s3ysB=
z&nXpGV)+NHkV-A(UI069`7w>Y%+i~lVda(=twAa*O$&cOXO*Ql)s<efjHbx%B}<6`
zT&HC#ZS%S;H&YP*f#t8qG5Uv=jTAucwlt^w?IX)nSE%<`=F_eA#Im9ulFuv+^bG5@
z+)DwZ0n1bhh`zNvLjg?}NfHl9S4nRnoN<%%n~DMBE*bp+U_2zF55cM3l3;r1?vZ>W
zL8GT+#WE;*N$!ur2=_`>?t;iZi6z~Q`z1ZS5DAvl{|<6c66XcILy|7q$EHZ;)2=C1
zvYp;|=@R~3^qrD;Q{7UAq$dDero_}?0?m?~9|?!EB~$1p$&q~X3=^CyNxKZuJc&mi
z^z$Xt>Fs}7QrZAgAhD%0p@ot^C~R;>lD!S;MUua*VeqV^dnlYaCpld}KZWF1+DMj2
zmN5V;mF)fj(B~zE5$L-h*^))|e`OLQ1p~_^vh5J9kgTKYu~L#b52Q-sq=WfOlIm87
zT$WT@V-l`NPNu@qs}egZ3$K>+QVj8$WC&HzT$e0<7m_z5A2p!yret#mNUdb54w7{e
zH`*iDOH3TNTauIks{d<{Op1rYjgpyP!2E4Y0(@(dn9-HcED62_(L0j6^xu}WNGAKD
zu~lNOh8K4wd8<I$Bul6qp<UuaW9pF9(*p3GB%J|fr)1|AjCY^3-vS~*(uWhF5Gp;|
z0n9Mz=K~m-DO@^*_UI8(J4<v%NsDGcG+Mf=2+kap-Y|f~NK-ZFi<R0?sa~A)AAd9+
zmuh|iOuW>87>1o7J@O|=qV(k^fF?<u=mb=<bfN)ZDbi><UYjSqNJT~YQjZz%sX*%c
zDKHC7(vAND^t?2UDtInS_s~k}id0QI_N&r&&tvwgrLpgz@0#>2or}0G)fE8khP3e%
z#(Pt`yb>Zc(%b~tt(7jm0m&9=48^@$rSH+x{jM}_5x6$#!GB?}UFt#agAVC^3UA(%
zni8Afcc(Nh8rb)x?{7lu1L+J}`#h93Qgo?Xni2x+N7927e0(gO6byqs(gk#);fXZj
zXJ9{-E<F$IXVUkgf!!<JMX&Vd(t65uzL1Wi+LxEoUuZe_N*Z+)DE(5$-#}hV$C)Tx
z@<v)hTfhP7h+W{`O2u@{$i*s+hik4@#?c^dR_3%^akrYb4V;Hnp9BVXTP-TaJngai
zmlklIR&Qx@<YV<4{jk1P4=1D1&nk&_T>)0J-N6M~Mccu(y;ftA(YVhlHJ2h!K~~9h
zJMFjPmxBwo8twu82rG9AJ49OTrI2rw)zegvXscv;+8(vaehx0i>KFR$W395+fxBbn
z*az>QTXj-Bsf)GmFOYP#u00BaZq_SKlK0kUUqHme`iFWry4$*Q1%3a@+xk3h$9$~+
zq^f6M>p7bM>SxVwfkuFJ28CV&t+!B$cAvG6H5!Ag@6fkY4q8v3GhT<RXD&eBVe56y
z@IJ)aik@0w*2P=kQ@HguTD(VC=X{O6Nb4K(pb%}%(IV}Lb^Uu(|98~dWePxJtbaC#
zr8w&s3xRgby80kwj$04@0S?Dor+f{PZXHPv>r>XPmta1_x`qP$nbsrd<(6eV_)F+z
zTYp0(KRMP@#E{Iho=JClzV%{C78Y7dzK33s^?usVoVC7112kQ=mQs~>wRISM4&<8k
zl0VRS-Mak_xEt0AFQDDDUbqO2HP&Wn&~LW(c>(T@wU!d7E!IC#R;JauLj{yJ>+{<%
z&`xV@2S}H7740YQTYqs5<{wx;I0}(R))lm(cx=tiL0^x_`oKr{ot{_^r|3nW^^=Vt
z&#hS{L|<5cHU=;+t;;Lm=_~8U6|mHA9iV_0udVw<7~vc16ST4Lw^370E5N3q2<m}0
z58i_8wHdt#jr(juo`VG0OuqoV{We<~U_RJp1>F?~Y)p0>un*dlPsU&l*?e6B#ltqM
z=rReh8DjyNP@9|CAYnGbTu6r79P@%}kv6yPLo&)HmjQ{knM^O-BR0R$9`C5lxKc>Q
z*z9b?2xD!I^no0+8Ac~Cj@uN{JrZvd766n4o3W;0Xgy(5yaoeJviTe<BJoL^NtA?6
zwy9nKl43K%6KJV6Ur-frnvEOP@21=Ieh0l%HqLKgH^U~r7wTCy>MRg1TmLH{-nQ1O
zA?ahg_$&AnWIH<mc0+CB$J1DBcT*K%xa|vnia$r#X485u$~O84JdL(>rYzPG+twDC
zIBGkMk`^(xepxUdYrFnEkdwClEpRl`_Ve8!S+-mZ6tZpQ0wi;69VqNqX}g%hoK?2Z
z=L6-U?fbO0ykToM3|`!{?W}{_HMZM_QT<V^Z8<Hy>THL82$_1@k{rm~vaL9U#s=H5
z&j8wJJAW8V+_sHu!H?Hun>im|G}|uQ4aqyU_B44dwx|9Cxof+hHk@s?iIn<px3#|k
zlnz@lMZxdc)+9sWiLE6C;h);7`sn@l%$CJDOmVO6Lwj`g*~b0|?zwG06|cOooq7oR
zFKu()LE|girhF*&+uojo#@DugQOMzq?I0JpHefrRt~nRkuNvsN$_88^;wH=f9CqDh
zA5-<Chpd?1*Slq2bSh+ztlSTr$y1i>1yL{AYZdgpWpf`u!$+3tj7DGCj^&tOKbheY
z%=^m*KgI|HWMe4J9w@V>lH|RzsWhegWWkg+4w4;+L*sr~NIGWifGqsKb&<@;9U_Nh
zv#9Fpu<SE>8-~cNDF+a0k`1NpO_+?ehrw`Jv<3zvWZ%947b$aJ4WFWAnN+WQMAo<!
z8b@U(DKZlyn^lg!SXt3}^u@_Oq`=iN*}W!^<FYZ?Fp(fjUWl<I%BFt?krT4MA2A6@
zGAZRsPRhEE10`8zs`~F0EqnJTc#$eAj{#_!>^2qNrpuaXhkHu4nD$c{GE*1ElqD-Q
z18BDFXF3;=BQtpd6bGHDR6S4jc0A1I%YLG&g3~g4T5J`_4ApSvye#P%z%Ix_*FvF8
zmV6cSR4(f=QHe#htS<~Q*JOLBuI;+4{5Le-kgY8P+D+L^N?X^+rcs$^t?UXtSnFi+
z3s9(+MHd0>mP}5i&<(OV+hDL!mQ34(+p>>n4c{a?;0>^5S@Llx+>xDH0FhRi=MFU9
zm0A32!qD1e6;$ETF6#@0Mu*IDC}i%*$}WO*%03Q-XqRmCZ}8&2Y@8Yj4`gBUfc8+<
zJr<4KvetLd_(=9n6cirI9^8R5Pi22k2iP;&mzU7jE0bJ>LZ9s5Es*E3VZIP~A^Tx3
zo&S0%`#Tr|eI;Y^py6sa!UG1~>?|o0?{2pz7Sruvm+?2ow8!q%exP~UEu-)4dD)eJ
z4TIixS^v@{Yxh4&H2c~;qHhHF*$t-BM1Q+=RA?1ock&$U2HKtTgQ2~4vob*T*{K%M
z_y6PVzZ;5CB-;OD56~ogugg$Owm<k8oJqCc84MHY_F+_PnqjYf4UsJS1)srEp8eJ#
zki2PMQ3LfB`{h*5-fACI0`9JT@n&#s_N`Pd(r(X>hQSW|$&{?<u`i|V)D!zZXF<}`
zXD_8}#S42QrGH=AFSP=BW&fuVGt_TCkM<X@?QJMG`^KKlMB{*cIF&fPwZD}HG#7aS
zWn*3CdwzvMH+cw^Sh&l7TnYt0`PFnl`^&xN0VPZxL;JUIxqBqW5-I<da^O)Wc{^3w
zN6WvR2lj~k$Rvoy$UElHB*=|-ppha!kqEoF^0X|FJo#2S(3CGPnE{bf`6SvHoR?Pz
z)733s`5NkF@;Zu%m&^UW1F4YDNP}Lb{9Q^}R>{Zuqw%7Aiw9i0BsT?a2fZxcB*L6r
zkuRbJ?^Ss}MRae;-KcWCL7qp;l}5S4zp!*${&O@Gn&dM>!8OZQbi#`}^6y+gTI60l
zNUQww0qEV8hswaU$$#kq*DjBt;_?o8!RJuFC%+&;W2bzwiGgoj@)r*wdSC7^3w9sK
zt$%>bL;0{-n38V!*NfoVBl+ARXnZUWiGX5{yovIHPvqyH!?maKrxdt+Ccm`~D82G;
z*FvFB{@r$X_*~xi5F#(+f89mjOL-dAZoZPsqQLdbhg_z7%4_)v4y|wG=c%UHg&XOK
zNp$7DkOIby`<Pa`?wr{dARb)D4Tv1z=G6lGAQ!v=*oQegI$jvU&Co+HoLl$~COCqd
zLoduoPQD8MMsana@IIPrChiFL4K41Da!>RB`~SbWbP9mPa*0$n634~Oz(gJ69*%?l
zac<=a*p27n?xQh*`)C7161heym^i_GPvM0m?!pIf<|MZv3MP`dgH*Db!UbJ~WGeR?
zg}c(YA9<jpbMrWOe~Jrm2baMmxemhpm&w^Jz(BLOUuoN$%^je1WDd6~2co&$<f&-P
z<JM(@%jXPK*LIo<qSB}WZr%6ru#o%wFci*k^C;<F#Qm`WeP_9j!LWOdt4e}MF&9t_
z^%8Cu3hu?F+$#$Ioadx;#LIMndr8smGVVY<WXicGl*p{$;^|W#mE6u4a8+C@t+Fn1
zciW(GiSwYG|79*b2*bX@J#xc9uX0PBAX&{x&q4AUH<Rwv>s;d#n7_d#k=>izRwrQA
zaB((3spVK-sMndeK@<Y7=c=hd`W6?Tf)O@wF_cqi<PIE%=xy$YJdh?1!6{twoD~IX
z?{Ei(0knnNNyk@OxsNEab(fnq9<H@<zfj<$o$H?ugB{!m+CbgoPTqz>C-)<r8SLV=
zWkcjXXZn|-NDnyQLU{U+8~+1ZySa^bF{Ve{(kF1{F?W&PV?Eqn`VF3NB0CK2DR*80
z?iu%%&f@fPd9-Tp<Lceu%yW(<OE0(~HL&!OOFabgirYnDn11f53nX82Cl*5e4R^?N
z5uyX!;v|gsEti!JeHXre28b*Fya9II_}{5c%$<Kk>t+u=oemG}=BGEo-#xrp7&uS9
z_)GZY#S65o^X50z!zUm9c@X-1`O|cu!H-|i1w;P4g(XH7z+a<k_&|PA1ih*E^3!j?
z{65}V089|?7yuXd^9StVa4>)R8Mp)dmEX~KkbhhZg+siy79JkvXGVd9@av-h8p=<j
zmv|Wer5Xz1{52}ziQq3~KrfQ7r@GK6{`g`Tisqf0FqR|yjwN*d<S75GJG_bEf2S2#
zEbku<nK=GoJYbITiN8YeI3G$ya`C((251TVPgEV3$Qx*@c7l&82T9_mx`LeKKNt!x
zlKIeaz)aywL?EerHKnW5_`CGElytt59_y$0o!`*=FN6O9_n|nG&!JaN7Jr=r<Jo)(
z9aziZ{f2<#^7p7DB#)n(3of6}I}h$Oztam`0l#4x6bkvDw}LyvKcdiG5&xwDB4>G@
zU*PCDzTs=kQ!yX47KTdry<&{Mlppj0oasFOR{%6F@Wyaxl<{jvft2$)FOUkpXgNqF
zzd8eRS;dD?Uh*OzM<wT%_&`6vT;|VZ;%B<TkH`jhm3N{0zM9{)8kpDkq8V`QI=|Bj
z>Nog!IlQ>Zn|6cL@W~edR%_x{xq;U4k+rZ?&&Pd*&RaZh0ni5CmqKZcd?`JPZu5K)
z8k_iv8z9YmqXvC<_z&lUYvGSA0ZJ=BAs*^?c_+$SwDF(Ns=u9o{T=!`_*;>1?H<3o
z0)3r)^jPS1@ut$(XuZ$(JO$bVKAra95BW$sztYXW(*yE||7INe9`i|iaq0E&E}Jm4
zCww{uFrV_Z&(Qab?@j?qFCW?l(#L;6iLmGVnopqcg8!DbQ!n|&bXmRP%jucW&qq#&
z<ZJ#f(`K~3;Rla|-vhj77|2`xY84b+gdH}3aTW9m7<3a(R-@5fSX>UjJp{1=lDmcR
zdm*w%_$wQIp2A#OM0*MG4}tA1xYAYaBXn|5_Z5O{Fl;|zAH@^=g_3W95+JOW)BZ0|
z*wGA)y}~#jwC)pPYylc1cz+I!{lal7fDIPHD6DZnSV)t9Q1Dy^&_hC^ISd{af{wvb
zi13g?j-f&{eZC+}SWCO^aA8L%`XYo>3XYr<R?^v{WMSG0=%ol}=F<BwRai!W;xwU&
zf;#E&6gSB!VKr^HGlT~VVK7th7!S}aq5W?-nk@uY!L=O0g}l!d)>C<Ro=`wFDEUHc
zBkZ0QKB|OXfe`Tu3WY+M1)$FeT_3<uk+5Mm6wV53P$rG@mx4J}wHFJw5@4c47^nkR
zD!fN|lk>u*NH}~!*hbr%GGPuq?8}9-v%yseZ$`jGrEqcpXjQ_f#n8Jb+};M1OM;Sa
zfXjlFKODUx3=u=&s!(Z!Yt_Q~L^NI#!rnr`bY1w-2bOLKi@yWfO`-HWL~Dctw2iD4
zCj0@7I$;+TOw|iJ&!O>_u%raTZV>7?NHz-5lVIt#P^^Sxlkna`kY+&{0dhz9G886S
zgei1+v<e^T;o4ncsS#jp!n4^BX*UUmHDEggmpd5RJt2BM&^iV09FQ(y6U8j<3uCPz
z`at;WT^M{QyrP1MZee6T`W^`_l^~CWi^DOd9>Jd~<(~*v6gqz@{Co^{p9#_v;Ch9X
zm%;T3O{?Mkb3xq)uor^K^f}DG6uRF7=qrJvqV0Ymn9lON7HmF+%p0Mv5@bLaP0{1G
zLcvjt!bNd>J%;A07;_1nn<9`_mF|k4_rQ{eV&V%}+N}sl0k=o-dLy7c6=AgZ_flj~
z<*K)0T?-U^6eT8lMEEM+DFe2j;tXBE{)(=(kO@#2=p_@VD5BipUd3NoK-;G<NT3j;
z_?>>3{fd8S@e!=}zy^&66oV;Hdr;v(JD5X?7$<Ot6}1%74N)Y0g+YWWnrCD5VT#=j
z@GxAF{n!N22u1d37>rbmc7{xpqLw1?(Te6?$Q)5rQGNAM#nh8<I7Sg02rpt4$+QoP
zQyil*!effxDaLtR@u?g7;uS+SK|Mh+|8v+)RQwVNazb&p0Fp@xOS)A~D*jFeSh7N-
zp!iFQq7Q)(ajIek<x<lW1vB7Gx<Wi38mAO9216r5@%RZeG8Jn-MPrttfv&l1#hPX`
z<|sDSLoZj65Cq9Q#T<&<=PMRd?a65cLyz?Wg##UbDO9Y!1cft-nKI01k)i@|5d8l)
ziuqL5dQLHK6+nv>LM*rvMd%2KmMY?vXgsetIUArC6d`*tv@%5uVV5gHvH??}IQkGG
zm5N>M=&MrvL@%I=ieZ%UzNFYkl{uFc*P0=DMPWzJ`m2fo`U$HQUf;nr(>2AOwV>A(
zU;huSHxx<J;OR}pHi}o(C<^TWQ>$>NAEr)mGaU0&kCFoP-BLJCfMkPWun*K56>-O5
z>9*p<S1{3}NV0}rvqC%sKHX82Q2x9{Q9KBwRpGlIBfG2E@&qVtCPfDA1KSmoj-azc
zAt``~dy3`snC?`hQHfNS!p8y{_Z7>i*!zJ(76$I2BK``@cPsv;CBY-b#h2h7D-xr@
z^(am(2j&ySN?L<FRVZnH{Y>FV$Lx9)D-$8or`THxx1TFa!5v^<C}ti8`%-b*3huvB
zSge9#zrycxz`R!2PJzf9#i*GO8BqM2fq}kNoLvJE7iEtC4_%dC(W1po+4l)Jcjd!Z
z=<`rcm<6ALm3g#ZJ)rEWM&Ci@@agC~q#X7&6b>sxO{>ruq71eN8>Wm7gGRX0olcHK
zDD5e78L9k!6wF5{%{yT}TA8~G+!5u%(NH+5JVzBiG0G?t+>TZDPDf*$QvLz-jw$67
zVm+=*m<STD91#POpxm7Ug+%4TZy<R>*{q?(f0ELhVs|H%lg7b(veMB5jj770&Cp0w
zzV|msx^nz$fSytw)xuJS@|!mxnaUq2UYn&{@e)2|E9-}1x^k3Oqam5AoJR4NJY~vQ
zH0CR9+W~!AIbka77APN6VRNA}ZaU>3&L|Nr!~LL)qg=sRWts)vf9I44q~mr_#z(?L
ziSp@Sm?%|Ro`(D9l~OvPeL?v?Jt4}JTl`?6TzSI-k`+qv6O5%&={5<ZO1X9~FfS^V
zb7B6HvYX6bR$iv9=@q3@JiY&}D&G{MwOT2q3f61NVRs;UU0In3azptKon^hLOneFx
zHOe}wbEs81QjDceX+azFdZo=PkXy?0Du^^FlNQ3KMrAwgu5K%xDCFOytQtwTgR(Un
zn0J&`-@>OBW#VEGQ>$_#?e^~~gM#5yn{p%V!`hX<K7dAtayk_~-BbQf!LLrG<{Z$v
zlud(S>ArIN?`V9Wyt)eHp)%_+(7Khm^gw>3d`AuS$4dP>AU#S`AUu4c)X?7Usq*v!
zOx`o)7H>>YuSq#67ifLT>iH0TuAKKFTzsLl9}K%MmHAX?@JjisKS2AH)*nISwbEiV
z(B3H5{|m_h<#9`hyjA{t4<arqT{1j$Ro$Bc&P_Ff7Nzd0aUX*7P<=$DiMv&nw_$#d
zDwL|yJyoU?<eQhOmP$ChRT~2V>Z6)RpuVbio<iSGHR3KB{Z$%Ddj_b?>17_MT9E^{
z_p0t)g2+DA&lHCYQmxz$k^QQ*6uA#pHDv<&fa?91Fn>^Wk~}=5l0O1DteQvvSy_l`
zgJ}%(LshG;ViLntvBLlpuJRoN5}_*o6ljsEe<(5>rTV=W8qum%bSV0W>eu%Hb5u3)
z2J~W7Qyaj=ssi6aAx^c|2j-8dCQ%&YxN6C2^u?<}K0{-IO85sNiK>|=0CqyPruD!3
zPvu9O*^{akS|lc`ip`;sqEdbb>{ONipKvBkHBF0|O;_bmLFg&f0y@f<q57AedYLLq
zI`WaF`iN3c*{VcWH0G%GQU)tmrJ#^wp6aL%<~Lu}c^`VGRo}J4nF7@s5BmOUq3SCt
z<T|4&p)^&IY7tG_S=H8bSURVgmjtv@l|u!%^D3TR-({-quVAoTwSFC3t55}9fnKHR
z4Sl1rN;Q~j2`;Keu7;&cDmPmBT~;Mg*!GI*G!>#=Rjs2-y;`-$hR$DJQ&k^={&iIm
z1xaqGKKmIOH&qoBB&kv9sCu$iRWAltr?R|?G1aRk9K>L5sru)lu~9YgS2W&Mt+9b#
zlj@u$d}>yWS`2bW)m{bY7S;E0KxtL|aR-CAt1?hoc$=zn0u)T`s<Bjz*P-&Y1A9-^
z(hJc})oV&Db*ZYRK>xn#>;Hj!pfY5EJXEd!4U*leZ|ODoNOeF7@>rEboBk)Nh~MDT
zQ`J&h06tUAX3^NIs;7&sPc?+%wa-;AyWsB&)gG!Pcxh6pd1$;+2|-}{Re$8b{A*QL
zGq^XZ!Ua$qP&rZ>@vZ7QEgM|aqp94;RUJU<S2y*@Hz4ln{y)*@q3&r1_HOmF68va;
z)VF?wK~Ht^4TyNDm-@jcZ*?D?r|?l*#i7wxZ8}H?Wc}1C%INy5i|M`(P^WdFGf+LX
z8S}hX?NJWJed=*kyc(qbgw`4R)kTxxVX(Tj7vzBY4(0d`s?#+PIixl&fQiHEU#L(g
zMEzADL_*d7P&HYYdO;7=!_{Mo;ctX`ndv*2h*W>{2S}9qGujeFtL>?j;)r_A9B@a~
z8Pi}sMqNG+T&&uY>I>u4&Q8ESrgo*O;p6J*B1}oVdJTOkIYAvZ4qT%8=W8G*)Cp1y
zDM=j^1aeY6)Bz+}oo<f46m^CT#XnQke}n=iO`T8Gis|Y<>3GvAb;MGb$WZ_JCAds=
z7wtQ<)B+_CvelO}KyuXS*6=A;EullGdFp4e7-7EJArIK6)gRK?hXS?iOQ000?`xob
zM$HAFu}JMrYxuM3qh)md>zw-3Y0O@+x{88HC2C11NU7R83wF<|#~MH`s7o(Gq)c6W
z0HZHg*CfGih5D07cu}c-d=2KS)SFj=yQrS&1(8eYvn8-}Ssim0dRNpl--E(c^@?b?
zR;}Jh<&@XdW+_yEc3qu9b9qC}>Y;yA?dS#38ujeO7)-5NPG!?|>S_yc_3D`o5V@sZ
z_Z>_$s5k!v$wswQiJ{$AkD;Yvle%{VB%9Um(eHXkJ!}FRThx~*#onrxeho+Os&n6i
z`8M^ciI@aak9t%goO+^u?*ufSs{gkD&OB3Ja|h{FN3DWJpSoZf$aD4W@v!tl-B}F%
zm+F=laIe%KzC~ZZ`U+KizE+Q+dYw0FJG$=&)MbT0Iq5J%4#{MPXJrscb!eXn^>l}C
z-a+3flf$7zxRK#7rxHWUbg+y^YnDR<ZTxZ^F4ICR&tZKLxO@i}7l;%%?Dqg#p@S=B
zIL|oz=zzW=2NS(y&N>`(1=u-<U#PgH*dc`yN+k{(=yEP~5Pt{t3l0Tm=$CXDQ~+nn
z9ZcziAyet_%{(YpIb5UDAr~Dce2K<O4iBhm;<Cewl`we4;XMkOTy>av6@AqXg%oMM
z=CFxYy4M}NDdBj-;bS`HchlkBVQ{;~;djcH)H>K@ps~(DMmx582Z6#)w;Z<9#5Oo&
zo4hfKMu$B{h~9Si@EKs593K9O#%728!{Ae!!`={hde0%E2QZxuHx-cVa;UF^`TGt^
z3i&^9$odB4p~Da*e#vf!=V4HI<j}YZl06O=Cj#t=LvJY5pE_)v1M<w_FCOZ>4jXc5
z;o9fWV+Fg<9qzmf(H9Q0+~ML&ht@Y}eC1$H-%sv$$Qy~q*A7`#F!9D=J=I4HI1HkA
z##@IWGl1fvS=k5Ts<Hh9eQp{vGU%>JqA-ewrj*{IyEU_4LS&Do!VQ?7nt#5g`_D@g
zPboWZ&BBi{3Lnk6n=s+48FUPdewtB~UGvxQwAc#Jgis7EP@}E|=w6N11)xEiEGm-R
zuX%q16oNH>Q>x*B#?1f|2Q`_U`0Wm9GWSB{ux2EMN<uUx4`3)%)ATRZzl3QfsnHp(
zF>Zrmgr?pc8j+geqhTUS^L8{uqcs8aPCuggjxLs?n!g_bJ64l(2GbR%G2ejk9@D&}
z%-eBI+B!^0yyhr{BNH{*PobBjaiyonNzDjK^Q34>H-e;UQYfEgO4DRiz;3$6fzVEA
z+Gs1Dq50w-Ok`;sDSVWz`R_BGIhs(q({nZDQSc&9Gm0YV`I<BPFs9R*8{Yt>Kodv5
zNTH^T?(H+0e>>4wq<Ki63OK9jqUgjq&DxDHRIC{i2gwqXrsNn}OEo*_lVs;LQFLKk
z&<vubNSVgtZ@`pmj#1#HQuEdp8daJHlzF?Tak7MKmo%{y>b$J6qS*BnjXjS^xT+a-
z7mcqp+s?s~r{n9}K=F2*PN7O4$4>*$cgS%Qm2QMOn%pQZAK~al!Ru(pH&hxM<LL1d
zMB^RbR-rM$arRw^CORh4_U44+7Z$LT<XAw@{F9D9%!L=pj&bzfO>z8v1I?`C@gkt4
zIdZg^O?TAIhvX^83A<o7!_kW>%`zQFOa*4P<9L%EiaCx$zenpiM<s22iXA%yC|-6<
zraG`IjzTv?uR6|I2fNjdZM3es=9r*^GuIs_uEEf5I2PE0+;qG_@5UO(fm2Ygb)3Hy
zdUcMK=ip4eWBEgHw;U(yf!W}AaS9X~9lv=+@4wrQOXJbn<al#96q_AG*1)Gbj(KJ1
zYjF&w1@m3UqYl7sbDUTJG<T<s3`9Jfey2siZl?!3p|{7W-v^-KPRT2w7vYp$2rkm;
z16s;QImOV|0;8QyeTTjyPAmV*@;ZgT665}hb-GF~l4DNqUIa{vQ-&HQQk{zXFy1sL
zR~~)oPECH$KjjooFPRLd)*Ik5odPz)i!7%AI$nRq$zm_mi=2+{N8eeeStCFyowlC^
zSe29aB9Mzt{<k1<$?0f6P_8%?*E6{Ps-4!*-twB$_d_w5+fHG0-#0m}q7M}{J8h-}
z!W}2mPFQMndP~Lccb!H`K%O~?wxO}l>4PPZeC{;t3FhgA(-v?1J};eo=<(d|lt9<|
zYp3fJU3la4%Mfq_PIkMX?xN)>0Ah00&ZTltH*Mz<c;T*X@kXbIR<aRfxAxz5jDC;y
z93|Jiw6U}>@z$QI1M$)B-;KfeY7fz8Y5cVPFM;B(JxU4E0BzS&aDm!+w5r>uZH<F^
zkapo^^zGM<raH`E?K^GIJ7Ch@V1RZ|>+~f=4{7Tt+;v!6_CIunYQ+@K2-7C4fkuS3
zG7f!_+K{<`Ii`KP2Ytu27DiY~(0)J{M50zR27O7|w^Z?xtc|3&K#DfvCPY%T8d^N0
zX?-X>m#!V4^88a;(+YYFWN3F?fQy;h&!`kIOZ#0uNVZn8186zg{B4+oT&=x58uPVY
z^exO1Z78ilO0{d6p?+R_ole<b(0bCNyG;9Q4I0a}qv^V+&@Q62UX}LY8lYU%jz~t|
zCG9Ua(RWk(kBLfjYP2a*=r?Jts5G`&dwLXnyQ6iXopp<L@MFwHt9IrbICEFK{0a2i
zw1rej+^%)n4fPJ~FLcM<)2<r<^-gUU-IQJ0B&uP!uNB{i<OA)2zv0E+!55yh7zO?e
z8Se!nLrn{*JoID7FgWMV9H-mEgPB<fvYXlc-%goHu7sv1v&|hMUQB-ol)ag1dgu5s
zUwXoZFZ11Uvq9!zOdBojGZ|4XJk4TwiUDLZXMcciIZP~FG`UP<47fbzf4;!XXV!Yt
z{_`}mfsP3jFi#XvEMzh_!s9bcjS0gqVouY-_bl`6ScsfswjKai%$zAhUkQ^>um4J>
z<d;E%%sZHBdRlw1D|?{6n_cn&4DMkiRuJ)Iy(6LE#crvDh&LPaJ0{A9WjiVU<I8>%
zh*m%L-)YeBXNO#dXaHOEClmu&r50n_%U+;&<UV$BJiG{EUwk1QWFE!3R$<uJSugCq
z&G(2#&jpH?XwwL0koi85;}Xo_LD4kIQG|)2hQna0Xa^GL|IPmRh)VopqN>{jBa;sw
zh3u43w5a}STrn&x45!+d<+}#q?@bRV-LQQUU5m~M<No^*;%YHOU*<A>2QQl$T7$_v
z#|$6(|9@IOb|kt7M1h~e_FIug3%^{<{ys?qF<bO8F!z~#?E~(Jh1`@3-J=#Bl(vYm
zFr!kqSc^J}yfw@2wLqprrg#kd-LmD2(AO(l)(Xkjvd4?Tx!b)v3f}tIU8Rz=eRic3
z)jMqWYzMd~yP&@ydCYDQRf8P2^BM~;;_V(#`Z~cbk)q;>b|1u3{`rJm;uZ`m$<Cev
z*(dGZdO|<hZY>o&r`Vl}#pGnzP22^^e7mhjK+f4sUjejoyEPOWykb|r1nPBmzwzj+
zw|kunlv{R>TER8gz4IB&H`>X52kEx+qM-UCyHRvb;<4QV56VCH*zF4i`@~M00)tQO
zc72OcJhO|R0lU3+njz5Wv&)YI+H<=_G_;p?@1?^0D?6uM5b3wO^$d-#?VeK{`;FZt
z`nc18U6cqYZ|y=q2ega*^$HMI``47_ce6KA0hFhG@+^w~dD)lKZ{ck}${UJ4_A6wt
z<ZHiQ3~rzO3_AT6WZ&^82D;z=4?HZz!S)Bw!0rM2w@pBcwV!;BX4d{Add(-=d)GiA
z&HlL(<}>V5cVaH`?He9IvcZ1d1oSo9hZ1I!eK6(HP0jY}e+6x|x7iDgyY_0@KfSbH
z(uZruMXnKG&`++QRldJ`OgBh~{3vBMqUE<{!|mg8Z_0!w%fF-}pPBNB?Lav#AN&h^
zDwda1qOU^!`#3aSmA^X;lC|<JN#L5~rzq^$Zjv9Tc=khi_ZHZFCNJ6tXZqzAV`-we
zBlY0Cxdcj1`EX_wMe*f+KMWW@&J*{N*q{3#8zKSROR^it`TvE<+spBkE!oFCrh4fh
zuI@RU+0QwA54VH4;@9Xqz&-c`dIvdE|5BhG;(G2u@i6Cj6|J${c`9a!<370sjbogl
zi3ZA9&^e2EZWhHD61ey2zp+T<KHd!PPjC^#A(_Nkp8+|^N!CInnalnV3Mt%Rib<w&
zk14#A#+~zry>xCZozFPMHJTW>n91p*A)3WKro>q`7rP8HIou`MaOHB}2Y}>p3G{-^
z=jNATW=?ZmG|&R>$3+-gA@?aoNX~FS8DOc1yGybCv)t`?pq%5@HKMVY%cTO|63&du
zx2|xPQ!u0&?n5`)|J>%<qM^~o?SBt0KH%<9Rn=2&!#`;3=jJW|_G>Pq0g`VxZVL1V
zxQVyX_ZEdrkaXeap9Z!c-)RF8e||E>CIa}0KSLyte?ljM_woW&neXFIJ;bp0^A<+<
z6wLo{nCc%7@HG^vJjgdMh2kOpcMEWbd1DL65x&L-29NTAN5IAKmqdVx<$LF$F^*5@
z1k5pBpzlx|=L24Yi{~c|g26=oDS`{A4cU_lg(N=Ud(6{Ge&%VIPv%!r1yKrr2#2vv
zC=S_5|JOqr-+CFKdHg0N#+%Qtrl)ZsuN)8TGkoSakP3dnM!=vPqY;u9`9~9>cZvUs
zDj90{53B%M%YT*w$$DO(f`nWA6S`CH@@qbZGj05BTH3YqPiW!Q!O!f4i0K|*d=L(I
z@<Co;yZGT$YJ8t>r)b0jek;AaAM(L;B(R(BkipU;ek)a9KjzmZgX`hfQtkN@{ykTq
zJmozoWZlar{0fCWUNaKE!E-*8YQSIcS2u#Z<a_Cv{fd7prJvWtkD&_Q*ZgfaSbD=t
zX=OXWOKI`^mY2~w8HEs=q39|sO@oM=Fp|pZ-G${W%zFru8|d>Fd?%nWKycxq5GbTn
zLUOP0g*(84gqKG8(S?c*kYJ(VT{wC`_?z~wM+MU~ii^bvUvEcetZ<?pT%0hk8>2WT
z9L@yjalvLPxOgF&e$fPBPa6~yg+Wx-bV7*PhrT2sFahMG@a{c0lPoA6VDeIgCzNkb
z6*A}vo+i{rL*$fDHy4;0LVgFhOhIIt4K_<yLY>)ylN-jABP=1sTp{cvJk1l<QG_#J
zXrRvoofbN^Xe<z-C_+*wR2#va5hhZ4rbw8x5FVZt)_sb`b3)EAC|njMMZx?PA>9Ri
z)k0VfyuT)J^z^wY+|<(fw;G{<=JKK7ord}97Cgp*^b5o2KPh`H<n_VQ8-ZC569Yon
zGBmywHhDtdMX_`!9CcNkTn_Ku6uY`$*Il8dSFDHP7dkkzTk$;w4EHGZEJB~BqI)vH
zycAbH2a301OgMf2z(>&#57tkSMziOysB#2ofMW4xC<ZEG=L37MqI@#?_9>n>13O4D
z<sSO>E28KeTCn2UZj9-GLPtyYgNh|bz#UTj<qyomik-Ck3sIPsp)pjkk`7jcDLN=m
zAFsH5+zj_$g5vL`XiZckZ-mSVMIohElN874-Fi|Xd<y*(#p;`|o2rO5hut*Aa@v@t
zE5<c~JEa()M_PuWuO1|Ng#B+AVfu*O|H7G5BNkEO*=yuKzr#Z9sB=6l+!^IvjhT5f
zdKx9eO#`F<&OmF>m`T5Z93GQR&#RCzbLf>5HfDbb&@#r19f0|gF`KE-vviCn6$w_2
zaicrEW6Y5GK#L!n_}B`b;?Hl7_Tuj?wp3R9`(w(X{L!d^7h5%S;ct(i#oCTdQGnn1
za|`W1U6}P#f$Pe=d;lajW=jkte3;000OQLPQz@c9vyc|02be2#{`Vkr@ehnOk};>J
zcog%Hg?cnoB%m*znN6|31je!#B#{|Lv6d4|*;rtnVrrvlI7~fV8mE~*oGJfbz?__j
z)<R~-15DBxCX?cH<&1`M*A>i!hXAc)rr(3XD#ob}eK#2$72MS@ZWO_+Wz_V3s$)w1
zVd4&Ro-#Zw%<mgOTA3qMvU!*JgT8yx#?(-qdpi>_8g6$mGhU+4bdSl91GJNQl7r43
z#@QO6Pnb1y>px}uDPH!B`Ha$Qz04COxHrrSN-GR7+23P=-ZFodLcxXofL_b4Z1r_C
zy0JO5QgLTbQVpU9n?fkN*}=5u+QSae7S)rTmj)3p6Wc{eByaX16}S1YPV`XqWi6LO
z)Q@$gjHN$&hcc`I?2l7H0$Eus$X>RZo_PD%P)g1Ru~D>Q*w2<|0T#^u_yw>Ju)E%c
z$U*i6#a0io?@~SVVfOtsun@u~eg#KESyTF_kO^ZaCBUh0)^jc<F@k+SQK(3E0i8NK
z#xA2w^l`Sg9?qn&Of&|Q%9a&FA&rf;1W9KP(DBDS_8IMh^VzwS|3A%|)&iw~y`qEN
zLe`&(C(g5rwxRC=D~^R;8GGJDVXty_-e1tKU?(ntZ<VZ=&I(qspOnD-E%rC6erRCJ
zX!X^|-u@pHZ?i)wJb#B>_XK)(*(<Z4(8dlq2=#WBp^~Bwwu$1A_t?`D;C&~%j@~a_
zY>y0m_gRZ}^tp&eyVLW}Q#76qfdz=XM#JC%(Fb$T7%n=ihQSz-&t{l7A!`2ujY*=0
z6p)jm*Aw7HvS{&qa4Di}4@`clsJ#^mr$sMXVWL1Znqs<zqL>kI?Tjd*6I_vK?thU$
z(O>Vve6eW8TsnV`uVPTNqEu8&Ki7HD+k<fCg6N~|z%CQ%??L~%XvIx<aZ6<RDPUSe
zZK3Gv6m{-I<73gU<xqGo3Z%f?fT(i=6!w@|C1Scg%^nRxqnFv*)!@9%Or5acWA+Yh
z*L}@uhtd7#XZG<=U=N!;wg7gB*$?#K2sP^;08E(K*3BT{X2FzMiZJ_r8748(tYQb;
zk2cGrC&Ur6t@kk(N6ju!t#pi8!yAxTvymqB#hEeh(-mYkhDsCC&Ah3;H`nYR9Y~Q`
zGi`TG7t9(np?}Hj7G1M9%y!a6-e5M%9vZD?4Yts~Z?^s&h&(W>dx}v!G)onMbenn5
zuIrImn*k$yY-UasH$7(iJ%IAWZ2D@b514&NU*vsjHjNg!F5=a(Ag*E=y;j}C-+KYt
z-6Z}v4;mg~zkgw3w>XPR8$89qF6i_Uv-ctDEq0`D)cA<=M}hc?SJBhdPh91KK7Vmv
z9!vy?f1=8<L*iNcA#zw;coAHP*d-Gvq2f*CZ<ts@d4zCr3`Kz>#3iYaj1rq_sMs=E
zyk!euj)>nzK=i0MlOh-~;(#DH6DvOb4q)QMiz&yLEDrC6NQ$_AJh)VG*H7q66LUP!
z(ouB+a!S0JBHJ0_XH+JfDSn&|f3wBCwE4;rucB>bu6PqAo$|#0nC`%CzBu?tOwDPr
zM+DFc#J=m$SSa@W3osY(Muw#_aZx5T%EhY35UCK)3I(YY4>y8Ti6_(I;-a{$5h9oH
zX>9z2m&NZ;-tww=3zcV8i<garg=^waDjB;j_Mt534e^Kuim}`jXO=;~MtpZA9Ih45
zqV!9hcrw+-wTq`y7N!I41MQwzON;DI@$*6qrb~Q@66yEFJ2+rJ6b~i!Zt<6qkbERw
zoeYu3;!SjQ^@uy#Ao)Z*CKYzyitijkql>v;5as_}&Hr~1`fldq!-4H?&QYzkhq+`5
z^mm)jOM!=;<}XHK6kg`L-T>R%eAaw$KIZpn9qwy>@iTz>nddu$^EaQMf<mZy0F@_)
znK#q<!*KKdhY*P{ze=}Zr1_G0;G)b=B0y~tN1Oi}hSnqITchD(jQO%EV8@#0@!;aj
ze+UHHG4pdPVfVPXXd?RJ&A;l#JSUi&(N~!g&6m_c<eWLb8b55Yxt3BpRptlJ!~5Ij
zzcJvN%qP=o<c;|eDzlHb_%0P-B^FkcPB4{Pd>4q;28&1vel%GeI|7X^iw}omE_y6(
zQ!e*~MH*GezO=}Rr_ozxU50{>Wsf<`2V1g~B#5$Xc7sTo<zfj$PFsFNB@rc-3#kOM
z!Eyr~!RfIyKLJcn$v8^Y2TL~70^z7hVx@)~sgey8TF#Wr{tz<dl3!>ES|NEb7mB{p
z<&J0!kX8qR3zYs#b+3D+ev}>ylAier{_dA9qUz`a(tZC!<3Z`dez+YfedGhlFlp3h
z5DAyQFoUC!(nD0@9VMOY2zxP7)8F(cjg`iJ0>wD#Man40OGVbuKOz0(PxK{A$DRV0
zCLIz3hfhiGF9w$(-S;p0vZSTQftD?OCWZMNX&A-1bEWQdi&sid3<0?)U0;hyxFQ|(
zF8Z!X(~Du@hE$+6XN~k1lMCFalRl<LaD#MQJ6i8ZKYj}tH!FrpsXVMs)q>k&rJ+c?
zmsOGvMiF4edqZ-s)f6hN4YvA_62k|rqRr75VkM{JV&PVg8G3KykMNH({$4mm2AoBm
zE8+0sFnX{pY5$7We@pLD_-WZ_4$8~Ne}#XqNXdZE%H5?vUDce7_SM0E!|a*{IuyHh
z@Fe)PZqHc!z20>Ke#{NMg>d7SI@-BznnamGV^aV|yFGpm{=Gwd90)s?9mBt!%jW{~
zZ*?y4|9v!p&Ohwxas-gchUU|iY2m=QF&|K^y*u;Kr_l6gmeaYC0Oq}CXbfcHsK90~
zGd>a|gz=mSkx=H>KY<>`JVGQ^oWi*K!mDhiaS#;FFtKz1^a3-;5sjCbfaA2kr)h~9
zLi_J1)~^|+quF7l06fCVDB*dOjZTMd47<Gpp2oAQ)}b+h9Y&XYGP{&ctEI5JuVaj<
z?8_nO%Vfh<;Ih~#O4Vnxh6s=x_7oM47O)dzp-{+<9}Wv=*a8Z)m9R^<!3k3-n?to%
z=UKm75Upg{D43{XA5+luDqBIX(Q0<fO}KuIO`t3AI$QQJMC#afs-LT89Z!P0#h#$*
z%x3ny8r&Ur6s<a1*k3+|dMmr+zf~~1sS0*G+1C^a?P4!ct>q&V>vsXI&)A44X!NpM
z%b?%Kj-)H5pS?Q<c3ni)e?j!AWN0|%u~*uO#MFNiIKVLUjD5>Yq}g#{f1qQIuB>q%
z2I9s>e+gZ8_Tvgz^I&7CaB(*~QG>oc>~X3G^ko0Ho$8Oh*iKq(d$aS?(dok)DL>=O
ze*6?@e(akCFzU}vr}tw38~FkT1KETT5D8(!?4TFQj-e9@VeHUz=sV8-IRHxu?9Y#-
z|L3Lf1MPzst<Yg$i!15oT~bTi<)vHfV9vB`3+>>S?~MY~3QZRvR&J%p#HybuW4=0(
zs#ezw4TQqlRa4>7x^<MjT7SF_pc}pn!Qa2s(1T^8o<c2~2F3#6*RVs-+8XjTjOl-(
zwDt}Iy&8AgOhLN`bCu3C>}CQ`#Et*|m#JMygJP!7fx*2@Q7h#4F_FUo8pLcI1C21|
zI+a0(Gg;5zas-oo7A{0FznRc@l=+#=#4*e4LE@P^bPoIkV@+%CWM)29TwZ2gkPlaw
zN~*`W%FMbAL)FawewZ~~W1M$@tz~Xcg?=N`K%1%-MoE`{7ZYKNzFsDsYA#+eFPb6p
zhM7GTXm6PlGlA{O&iNQHQS75=G-k1%AkXoCch_YN{*lWhj)qPiGxKlwn$P@Xg#nyq
zzEq>HfO&5W)gKfx1_7;Sm}PW!y@=UKo9uE%NxRAlroICDmCToPZB#KwsYKx-bA%c%
zG5M75z07QJ_-}L{P*9+inM={ByG-OtaBWQAkHG9^rce^-5z{ss3NM(2^ss-)eDIvs
zzi#Z3TzKQoM$%&5gZ26w8vbl2MJ5B-b(>%}kp1K~>>g&lQb9u4o)wtfP}b@NNDP}4
z2lKJ46KzG}*rBwtImW6SFn=lR8hSjYvL#fjmdn~u4RId3xfq7>*^Nz5H=Sl*)9#^^
zEu;$J^K48iG%m1#6rn6*qsZV@_8Eo9tJ%n@(7479`xYa-&IZ!Prjgx9pH;if#+Rb6
zi8Z4uwV4$UpzjXbKs%u>wskA|?z0o=_3(hrr0~!~_UnZp-6qzHwqB1||7nnU%vMk)
ztcU%cDx{vU-%_^hDO*l4wr8vz75?<H8KcnG$8OpO*PgS_|2xOQhV8-7Ub1iBN8>9t
zwF_K7`~Q0T?x?7eZSSr+p}Xl|qXK3H3>ZjaoZ!fS5lomB1w<4KNK({M8v}x25EU&0
zDq;q+j>jx!9TPg{j5%V&9KK(5pSkzGKi+rWx@*1X5_Z?lReesKs=ap|!g<N*7uq=j
z0$*u1F9@41WV}Jo76|?LDr>1=ojwsxtro($H=Bg-^8gMD4U>VqB1G_z$aA4@GLYj%
zhiOo{Nc_n6y&FWw060@1y5EP=Gvb(mK;9G+BDue!jwj+ji@A6`i|tx0lxp)V+EppH
z24|Cue0hEwFD~bQfBUY~ZUv+sNFlSJ|B3X+Z5S<<0(m9VYbiYwtna0ML*eu%$<YI?
z?^0*JtC=M4XsWU6FZ-VFAA3CJS3s|fr!W;d%L!WgCh}!<_yYyhn3j{!;Xx)({7!ny
ziyenIeZ{Z85e=Q8G<nwv{7xYacrnU&a*9t!Q%Esi0Zb)>ctmFwxz3A}W|RIr2DXsA
ze1ujuDd`K^auUh2AS+1caxl9N8B931p5*g%?gsMW8E6Xm_8HD>C#Cq4atC?80OC7|
z)%`o<cagU|O}U%IX26R*q|aff*-QQ$2cCUogacXyr0+S%?<e7WRd9f8$%ouQ(rhqv
zA0lPC!{A|ZfiLZjkh;9=<tUk$1kPi`pF!tw(!d|!Pm)XlPLNML>U)w%R(=(oBE|*K
zcA9wdNZuLp!)XW>l51CiJWINjL+c!waSP5|CDnP6;Wg5MpHsR{cGiZa8^pv{$v4US
zl@Pc^k`%B!Bo2HD@`xmk1j}RcWgf(zkcK=u_>{yA1?Mxe-h)q}&xwhrMT^NDK1*z*
z#0qWO=v#gUV>>Ouw}hMar32LLreU+dSwO4AV`LA~=e#E62yJ_h_mDPw3AvMW77w_d
zp$jCm{-S;RL*Ob+n+%q_w831smLkNW{@*@JTHo-!M>Y*k0a!#e`ysoSR^ghK(DFP`
zm_tu@hLcO_=qxyrOJ}7)bQxWI8{RFa?p46Kg8JcUhgm0}HLR?nO-4d)HJ!-ItkzJ<
zC*nN1p0CsMsYeZPuBBsnkYXKmvF-!wditHO2RG2EuCTO`PT(a?n`rW6&^FTn1`L@(
zyTqVXK=<y2n*G$fH<TWyWmDnypY+#aICFw7=b7)5)Y1_G7wGI%n7>FxzWTmI4ad>C
zOm`fH+-=&U75Z63yBy*}eTQ0kH0LfYP6xP0EAo*1eVW@9v<Eb4G6Wyeqi5jLBYG<a
z9zLd&e}7MChsxl5N_{QR_Kf!7lk{_X&KsP?^x`SdUeHau0N&FNr2#(B>_6b|N1Dek
zqEEEYoA3WV)3V=z{X(x?2hUe(?E>(PZq9|J$->+pFkWdwX<sOvAsG1Nl_|vVQ1Lv0
z)&a|W;m`}TmI_`xwv#Iy;VI=j;cG5@$`>l}B-R$;AkVyP#alhWxmyUD3$RB>Kv>X<
z+0LI=(;X3pHiPb?!hp44EfhY~1vo2w;~9Z-!sdtY=`W!q9GvHc%1BY+rKax#LAxld
z&w|}cg8zItb6N1-2ZL9H6SKf_Rk#-kXRZm^rJ(w{(2>7C`G(-U8Z0-3_q>k9dP|7n
zPxafv)I-o#BsAwY`#m9sr#0^jANoSg1Htn$%s&*Cb%2Q{LIz(SJrzC~L3<|jKM&65
zLN}i4EEWPv0A2|@A^=_s%fq4ijZkYd<h}}}`GNfu(a`|{n9je0Ho+=-M*vO~P2)kF
zB<}YEYpQr`Jvy2$9`S(tQ^erjaDTe^@EZ*NF8UmR`3$iOzXE57kNAy~DY~SAwnjAZ
zaL5+X{}cpvi-Xf3en{-K6)Y!3kApxy6}#|ai*HiT7w{rowzmHX+NR4Hyf7m}jy(gO
zx$=vf(7iwoKMJJ_<<*nW%9i&`fQO6ZHah_p%k&MD=E#?8z~5ZisShkIm)n<y(v|X%
zGTa$CA{WR!xmi`{%$K8ih;*&I^BLsU$zPA5*Bj)PR=(-jC<ojD*d!-f)unaW3IoC2
zV=3RF_Z(9O7JFT(gwMU(#KF(doIp6;#}ovfzCs859&ob+3I;~y;B)kWczljY=e2YR
zm-xZC#L2uMBPo!t6ozMEmXSsrx{p33cb~-f7r$-hS<Ojg7r&fSN#~0&_dBVOfKFr(
z-`X%WgDmHRo=IYg;r&c9&lx?NPdf7F=mJuQ-{A{Mb3P+wlRf+uu8YXjN6@^HBprfk
zg>2$E^F74MSI`H^%5;F^<hpJDb%qRS1#K6|?xS$>8p)1A>kjGg4$eF!F&}_@M~;++
z(iA$>4+dvauR+kZl-8Q@cfpCTHxQX5V?OlGBnN+n=zKD!7@`YEE<ftLko@s8KsGtm
z7;Y^m(QU!Gf;`CN^)Ks4&8bkoo~+yni4A1LcAM)5ke<NvvY<6uJ4h}+h_RE%-+??x
zI`N8vLuB(?^zJ0NGY+j&<Yhg0agki$fwoIzc@UJ{BAqs)b(^f?g;GT%j29c+A-_jK
zOFnJZgV+D8r3w5USL^80zUcXS+NKDs8)#X+x!Fj=gMr*cgR28<rrE!vYbWUOZ4kIc
zOPavo5+S`KK#ov29JHl^KQH^w6@2utyG$tJWlPJ2$L&B{A++*^+)AM@zmiu8(~|l8
zvs!4_1U+0MIA+4(JmDnI#>^0>dO|)^4B~snnc_J9oSh{av*6QgF@#4lv&1S`UrBRB
zFFqyD6|eF&0~2L8Am@o;#X!y%OZcna7l<oEVRxZe-U!vH@|#HBd--!b%v#sWPrT9G
zB1iLw?>4y_Kliy^o~MD`-Lhs2c=pN@_ztN+Ui3RS56J$N!1+#ov<;lowT0VYX{|QW
z709F7ZpYF3Q(GkqUR==rh$9TP=j>y;jBk&g(-r&S<trM-ljSA!$SNLV{7AR*I8&P7
zdPgmfDqD`1wFZ>kjS&g*tAx+N9iG5;yOF#`vi+dZFw)_00d#bXod$fTA^dz#h!-za
z=xyo`ouRjk_}!;6&++x0^%b096?Os>Zsc#lipb-Kf(JEk%IkjyC-dZf;?aKSKvG2o
zOk)E18g%UJV2GuX-%;#^U1C4}bV?&(JRz1&hVt#!6tX%TLTick1o*d-IXuC%lej;F
z(E`$mhgy!1!yAD-Npf5P&XMPQd@d8h_l!4*^qjAM?vqM-G@p^*0@2eF@~RMmUrEbq
zpiQKYe}Ui>dJ6SlwxKK=$&c8z80e0XXt|K@FNg2t5taAk_BeR)fsFKmme1rNKY;j!
z=nq2tJ6XCNKBdr=ZGoIfXIBO1BwDJ7pZ`yzxzk}OowoiCp4rq=0L@u+P))Sf(Kd-_
z?V(BcG<Nf6sE&u+F4JQRpyLV+xetw3>4d5nk88ATGK8+vy+4BXfX1~4=R-QY5n4}Z
z^ac3!l)kmqGSCgY=P#)BOF4}0M_Miz>Oav+Iq-I>kZC~|GlaZd&^=42JO-W25?0KI
zi8(^p&*~iQRF|)|-jMfc(Das=_@cLjjLm?}cVtQ)G`uI%c#P%)@m_B0_R&~dx690d
z$?0@hbEvicPS^8g?i@P#FUZfOr}@^2Q8Py_q1$=FG>0~gMQbS?$j2#{zSF?TJX)tI
zl;+b_9U!ol&fWy%R{GEgmOp6DXSDXvCOj*+mp&9=7Xjh-&~lW1n}abrLpN$5UTCGO
z-N1U4M)C*mHM*k&+OE^h<AA(DtMM)VO&Y!(v|IFa0t9bUk!Qb)X#Qo$-=V8{;rU&<
zAQ2{B(*r!a_l92L3)i<acs3srx_KAm-cj#bKz^X-$AI$_Et!FyeWq4N{<xSZH24X=
zO%lHPfG0;d#8bifLLjeU+b5(p0PT|CW&rY*;QJ9Q&xHaW04)(pI)V08So;uer;4u2
z;0zPDw1>`o@njHMd&S{5z<EZ*k`RuHgA2g<UbI$+Yty86Rz7RZk-mOLbD@;K3Qpxp
z)p#M$YH7$6AhYF$JZiF7p2x$^OXN5FJVlQDS%Taec>zy|<;!<?ea%{Vyeo9Cmp%4F
zZj)SrXREf!QN7`XA`ghgQ0|bw<C!Jxl7nhPV7ENWpU*#gW%>aI3*;UAIPreDay7^w
zly}yL{2{q!MF<|2>qP;1Tz<^UvQNqDy21QuIWQE?oRRNjK>RQH)Gl?lYZb>A>8<O&
zhq^ZL9*}R_il5R8Iu!v-@Kb&mqumUC1Gl%n%Y$qO{N)zRW%^=>b@JH^heO))C1dBH
z((s{+%denzeOL#^y1iZwO!rAV&E4Z*8aR8dy$cP!`ttRC?{`C?I<)u!sD0m5hL2%A
zoS`SY*;8O5E{gcvuhndDM*gw@diw9QK8A`Yo8tq{w*+e7<)vVac4!ZL%y>7j4tmoF
zp9jmEKppalUrR$B)&d{fdn+)*R(6J&xGpcy%XrTha3x{NSA0%9+W`1vhu--7TT6cQ
zXgrDRg?^-ykKLf7fZRb47|%agtGd4-Fm69yh1MFik3g%}4mY@3f7K@FX!JD(V;A7Y
zA8aj0Jj3T6w@M%tx{gO|`vmX9=P3WGP(9$6LU<ZChHsnW^W*S&WVxBpFiKMgzsFUb
z054KW0MFRZAkBG!L#CBXYKrE3qV<9LW#lD4Vv<k7HlnqK^vH%^JIM)8Aa{|r;Q+hI
z<27($4_W31D@REnUpJp7^Ll~vA}JgK+9h(4pS-_E95G>I_Nc^n-m7VKzVqHnjg5i)
zgWllLzirgIYB3}fnwy1Q6wsyoZ)Du0`nTxKE&6K>=$<d+bb#&!!V<oZUnuMd!ze8m
zdh+{zh0u;K>{bf-TTp_WFN{Se<c&f+PZpdO=JJ=xoe?5xL7-3wnuOMQ!RZ-#c0sW6
zhv!A%v^5W`&xDaTU}=`PcQ?FPEB;&&$PHrZBS>r!Kl3g7Rxu+U$Zg`IiRyExYV{k?
z>;7r98gM)(?wE>RUlBvr179RwNrj<easEei<%Rgb1Kk}j&0G#$=~8M{K|`lWLt|pu
z$B)EdExHKZbEFrK@m0)|uJX4LFO)*VfLtv7v=3e!mlpGVbD{LpM<}=~&D{!?8&V42
zJr_wq*T8vSk|zN?meN|IYtN;+ShL74r4v)&)GXQA1mt2l5V3RY6C4kswMt&Y>j2lu
z53PK~uto0vCmi1`AFlzP1M*-VW;-nBSA|c<WT&5?=C*unERYZ6_j`eSCg0^1v@hfj
zJmmXX9y<!=zsUnmL(3$sGoLRqwR0ZA!@1h^4dMNKtt&4d&epc&5yutUkb2O$TI+U)
zhdT4M(IyZ#X?qR;*s5*CpC`w)6;r@^Qu`|p!JW~*eGP4wwQEN~_ciT)TjWu@zalt`
zv|h(SyQlqhAC?|!6L~J+jrL&?l)cl|>H>i;+DhMHXo9XRuX9M%O`Qsz>AJOdc@e}k
z-N8eU$j~``0m#xd<m-hUx;z{a!yD`y@WtIF-9ldBepR=gr_S%{0vf>5V_jYn9|T=@
zzFdB-v)UGRy7|09;e+mHzA62tOMe1^@%nteaG0c*`MZ|V^f!5-@oatkVtxp1jXuye
zh3f;7U}Bg4{yqrq*QdM$>mhv>ucA7oPrM0-3-yUUX#J%>+Y?v9b$!}usJX8n&abwo
z`je$Wd!?VZ8**>;XFVbCUVomK_I%P0N(1ey-oG+vDGnp+pq~>R4rarib+W^6ThWW_
zhLSK0_Z`DjKC<@>PBTG#WC(fziKhl5-<=d27B4~Tm7%Z~%uh59K8pdKYV_cn6lN58
zgm<Aai$AfJ7<=*<<TB%*d}>&0tlbZ^jmG3eIJ(t1i^r6<8^^W=a+lTkEgljFj5>ZA
z@|bb!H3$|O$E-!`im?^n;@&c5@e0X1M(s`@?;DT*1P>n>{a&G!ZraKh_R~!@AHc&*
zQ>D^yCd;%qAHAPvGV^6hw&}OVVA*5};j`jaQ=e?K6w{;n=*vNqwKtF0JvNQw!Rr!J
zb?(e(Q+72VQ_byb!o_s+FHHevnor@fv@JuUMw{_ra31D14bB2+1Wj%HrsT8Pq#^i+
zxg9^m%gft8F3!7iLZl|(htSSl@V}j3{ea>9qS^$u2=n#w_3`ozb^2FiXxxzD17l(n
zLs`am(xOIkOsrph&gkXiRo|z+pHIX3e!dNT8ighe8#W{{v|miDx0e@NEYK<j*!ufF
zvwkC0z5jcQ|0@Pv{1Qhc{(rjpzhcyRj-H16pZAoNBGm97S+)L~FEk=ysAuf3*eK7a
zh<-7lF|m<DhWC#OjjUTY)YsR`4;RaSWk`x1KD1xxh{jQ#L+cKR3yqFQ=#Oh6iGK~=
zT@#}c61^iM5{4vu2Sz0hP8t^Hom6F*XHqn{hYgGMP9BypI593FG73zwo=H)ONr|jE
zrS6UXJK=vXTaoRhG~hoPng98vzJo2PWtLc?NIl9$M@95UH@%|c;xu?Nqa(JD4oneg
zeda4ul(~!4m0gypS?C`%K#?Tchq8Drtz6DICsZmkP^vIoGQ>y~HB=;7IMqN1D+(5z
zltL}tDM*P)5eZ4kQUiTZiM=kRb5=HZQ1^Q5=suH)-CU-3Ql507@7(l>QL+77CPWO4
zQWlM*jmjx6GwHf2Y_(``S9WipEq-7xmpD{beniOFjjf8-m12=M4b@qLvec1<_(~Pn
zbAw5z+%*cT^z4#sEXCqRP#s&<Kq#ebbQUU?Vd2&FPVBSjU}mps3(o9qf>?!lJ~8MO
zhdRPC$+>gKHemrFzF{FfI<yb&8P;)FVl@w6A667<sH7b67EX(7)*8`U+0;PzIF1dN
z<WQE4d@7sf-V(K}ud~sa-6nd8t+u0d%Em3id@Z~G#-W+gc9$^F#HxG{e3VVc1a~cK
zcFW+Vd^#gEGW`6XT_v~_`wbtcVR6?47iHKrp<D%dz_5g&5lPDO5@9rDzig8$>KfXH
zy~PNn-3MV<V|M<GP*XYVEq3xS1VqGk8QI$Qr7J-_#6uzr-=k}+H0vYYG?B(^MpxN|
zG+}!uIXEkRgT*Vpit{3|g}{<q7)r4tk+O%9kRw*ov&2J^qjGMI*x5z#+b@>aGWWr9
zY39*GtgZwf6Z<=}F1PiLO8Hyjgc|JOF2T%xch;In7&|LUE_0_*1N-d@6c&h*R(T{!
zJzd$*QHEN|=$ewF%nFMINjX?g`qq>=pEr3Z?*>S5-b@^gOEG_#u`H`MnmQ^8bESxe
z?Cqb_!aCKIsw-blAi>J$Tfv33Um?3G=TA$W+*z4EVqK-}Yf0;<L<{mcC&j<K98;A|
zHDWySn#kiRn^sTqQ|kUG4>z!oAYDx*r=|R%EK^<^Oe}8$EzR8O3T4>Keg-Y;(^7I{
zH=RVCa=o{FO{)|~%0cc*beeoj%l<kc)lqzA$o(W`bC#THQ3kJ&qg<5Y-STxwxo|+v
z>&(Iz2ojrKB2-}8cIrzj>zuWxI<fBSjTUzHp1!iOI$E1|hn?IlS5Za==^n*v!@>gF
z`PUC*ulkDR6=jdk*HbBeqFe6F_Ea<BsuN@f3}?zqT-I|h!OvfQmK_vah67z#JFTE)
z`|g<}*6frZD^tts7gcBHy3le;t!DZ$T9($zScZ*AHP%#ix6u37bigHHyY<@iSH29^
zx2dLdn697T0_~2=^<~&zqt>95UaoIuDciAo2=0=wfbLye+HaBiU2C(Y>*O-*$SGYJ
zR_ZR5S;ujDgED!m{zo6?`dX^ZntzuhrTCsc(Zr?`y&IdHY;saYyw=B+W+k%D!Zy|r
zMAme@g8_fd*&)G$MI6H%k>}~Ky|*%Yio*!!GOate2<zq_+_gou`VD<-|GFy19Eb8|
z_E#o#Qv%mJ-1B6u%j<n~UHwD4g#8*4!kYhRtgHlIcR1_Jy1j9j!5aID7FP9^Y+%{*
zaXq09X|lzLUbpGr(st))*pROJa>`xN&_G~6I2${#kUtDgN<Ez+ql_soV$_gf5&eUs
zVh1KgD?2J0JnA!_Yl4ST)Xp%oF6%eNp`4O6$}qhGTicYDS5mSJE%Z(S{_Vp;0=xKz
zgtctf#y(a}x+(`38D=(TP19s=mUh#iDB-sZyCuc-zQI&k=N}jl);2K2mlf^RR%PuR
zjV9J|v4e#bCy27rof^-Xi61MvDOFTPIU4ti%q1HW=!>zEgXJGzg@#*g*@XEUX+`GK
zOV%ozoQ=T-w&|?ViRGL%)>TTo89PO?v|NW$N`9)*Vo*+J8kaW4ZSPtjlvTDIGhWuQ
z#5x8?<@#CUei!EbOen{?R+Al-&5w=U9oeibxtdbvv$3uVOPhil@9Y2xcXtdNIb6Yn
zyM$=9%-j~gxaZ33(xxwdEO(t;T2We>{tRIU>*MBidO~Y5?Q6M`a(lihs}5W9gTc&P
zJ{!wn)^T;gO#bqtR;w&LWcsa?Z0nB?JKI&P$WpFDZ$oF<k$vlJFeshRn{Hs%Po|sL
z#+#yp;`zcftg>zHb8Y&MXGx2Yp!S`^e0~3A&TG*zC|X%)G~dzd8u~W%^ljR}m!&$J
zz0E0DaQd5dX*7fUYQD`5IGazCG0IFA^BWyWVX4*3wMbdqdgiQZO&c_A*vKc!uTfLq
z29X0Inlxz=<=fcL$Je)C|Ne~|L^V?4UClxI|2hw|X4~XS&Hk-t@Im8-ABXuGO+5~g
zRv*FPLXBpOVybIyOswOuET$HX2D>jCoU6iI6{6VDhR3$o22qz_gO^l@#IddYLWQ4I
zs6{e{>n)?gsw%9jLKH@Ex>XaPB9OPT3G`MWGG4ZJq6)DqwY8_Ikf{)xUK@Uc3Qw!>
zo(gfg)JFfNLL-9u+%d$_0Fm%Q62ykUQ9>IGQejUOMyqhT3KyvmnR*-lRTUyHZfloU
zVNDhKsj!0zLsf{E7-(o9JQ<-PaLmD`AX9~lRG6niMTIDjvhgALV1vHwhQGzd8mu-u
zsW4Q9Q7Rm)!gv)Xt8lCeC#n!tvNpAN)1VDvn{0z90=2>YDm<-1guOW4s(GX$N>oTu
zaLPv-g{C%$jHM0MR$*fm2B;8K)HXUwwQO*Z3X@eh^=~@z3taCQ6(TN+Hoi$5p|KHA
zG-HD|RCq^)k5!1$RvW#73cXZ_;yN3?vkK!?i0HQspQger6)xluI`cSmf=5W{*cgwi
z@UkxLfwvhyrIZKWmX%Ft69*+D+Om_+0j}|uGAuOSVv#=7F>9)^_;`!EjP#o3t&S~-
zx422=>Y6n<Y(LOa0fJi5Y*PXxzCeO_FjIo17TL}ka?qOf;oulc<sg);13)nYyO?09
zNw%@CXqq(j&6<v-G#cFbnx9xvf~6v9#M&i-($U|n@c@=nn%OBm*dk6D35pIEH>WhW
zQKUCjG#W3~DbeC?N(nS;kSVlLf3;Ixt7<gfcIx(jp$6Ki9YL*Rr@jQWnkw7UMx{fl
zvi6CVnkGw&f4bA!E|>wq47*?xP;*qlwye_#OC=F{I@yVrK@3-k!8TDcl${!mo-}D`
z*7#sz;yr0^R~qN4(G0T7MYl3*(p9;RcIs77Z?Ut((a)ElB3fvZ4Y5;qxc{Rk<=XzU
zCtYk*dcob^lO`bjJ+R&Eg6|=C#cnhlRGsQl59T=BQi)V&>yt48(LrX-NW@IIv%Oe^
z6@5g;qpIDT+kMO$#7u0&P}=~ob|d+>7-rUFW)d5|uie;U6oL%38@v6YlxC#b!*CWc
z+ER%<=TbdhmeTM)H^xo%vrA3E1pk}e)@3h?W}|AWznv-~#SgRm`%m|=XyR0z18h_h
z&Tfo?)(@Z{tzy#}&0I&J0~d+r8!H+GvF$%X43{%EImoW`_-&$bvYYg1WzqCdO%AbB
zZx#_;m$t7WrL{#9tx{v{-##8cEA0L}YGctLQ*TooXBXWMYLZ<vr!9O^MHATBMEHbE
zVH#V?yAmF3(cD(Q;v~E1?uSGZW>?(21FWiwN7$(q5sGePmt74i5-2vaBW+aDiLD#M
zFS-zmCI?eC@9Ai}TzE0j)Kdqy+dum<#!j7%XJ{3>*5*AxRke<@Q}bStzi++Oy(}6Z
z)uR+U^)jdxRL!9NJ%$tP)Yo_k>^OUGd_v)`Dm%$ejeA2hQ|#0NQ0J-C$#&{TQ0Lga
z>e0udd8vApZl`7-g6(Oy+dAB$Nmqw>s-3#)J<)8oQwt+7KdQ3R?bM+ki3Zy({tXmH
zS~Q^B#wx=`C1Y9T6pZ3+P;ltXM#;3x4f^`G9HzcGV3I}y)0>eAm><ulV1Deu?sN17
zEJ6k_$MF_-@*`_F9+P7V>%&1fOXXlATL*xbFPk+5><ZYV<<-oXO`ynKii@^r9x>u#
HF7y8Y>QqRe

diff --git a/Debug/App/Src/test.su b/Debug/App/Src/test.su
index eeb73c8..978d7ac 100644
--- a/Debug/App/Src/test.su
+++ b/Debug/App/Src/test.su
@@ -1 +1 @@
-../App/Src/test.cpp:14:18:void testCan(CAN_HandleTypeDef*)	608	static
+../App/Src/test.cpp:14:18:void testCan(CAN_HandleTypeDef*)	624	static
diff --git a/Debug/Core/Src/main.cyclo b/Debug/Core/Src/main.cyclo
index c596d88..c9e806a 100644
--- a/Debug/Core/Src/main.cyclo
+++ b/Debug/Core/Src/main.cyclo
@@ -1,6 +1,7 @@
-../Core/Src/main.c:69:5:main	1
-../Core/Src/main.c:116:6:SystemClock_Config	3
-../Core/Src/main.c:158:13:MX_CAN1_Init	2
-../Core/Src/main.c:195:13:MX_UART4_Init	2
-../Core/Src/main.c:228:13:MX_GPIO_Init	1
-../Core/Src/main.c:269:6:Error_Handler	1
+../Core/Src/main.c:74:5:main	2
+../Core/Src/main.c:152:6:SystemClock_Config	3
+../Core/Src/main.c:198:13:MX_CAN1_Init	2
+../Core/Src/main.c:235:13:MX_UART4_Init	2
+../Core/Src/main.c:268:13:MX_GPIO_Init	1
+../Core/Src/main.c:315:6:HAL_CAN_RxFifo0MsgPendingCallback	1
+../Core/Src/main.c:332:6:Error_Handler	1
diff --git a/Debug/Core/Src/main.o b/Debug/Core/Src/main.o
index afa63ab84dc4a844ffc1503698f0b74f964aac18..384a82798e8f03a2b28a247d743d375c37f85fb9 100644
GIT binary patch
delta 289809
zcmZs@2Ye0L8#g{PcjivLJ&3Z1uzK&k*XXQnu{vw9%VOER5u!yBNsxr-M1mxU5(%Q$
zAZmyfC5aM=MARt%?=zR*|9wB7*RDD9wD0qrGiT16^PF=XJJt5}y|ydLJC6NgW$;I6
zKv$*;vz}SEXLLB*f(5l4fBo^7?gQ{Q@caD=ltJI`gHeXiJ!jwrqbPar_t_otl`ZZp
z>m^kvHL8pkQ(?`>(zvFNEa_FJLaCANUR;GCBa4GmYG(1S#k+ia|Mgoj{p#jbtQ+HD
z*Y9m!rDrqMrPN-9-qWo*r&r-W(@59ct$C;5X9i{g{x<8RdhuO_|4V*18__UK=&f#6
ztEzErh@d|qb+{^nDtndw{pW7&Uwij+jH!rw1MZSWCQV>G=Z^I7Dm|fmxAukJ?Hwb_
z;@*I}xg+OJU_G1vhA`^S{f+ZX8jU+c(P-YY`It7IbH{))hW9KQ6B5C>3!G>3Q7b|Y
zagAG+@N(}~3U!oFQ#ZW@9C{1bykK6h)F=zeW89EYCTfMhHC%`Mt&rZ|vKJdt)iB?=
zY&R1p=DQgnA30>?nvv-vOO0ZH-`1=2<Tg|RgJX0n+@k`9=A)WVWIT&THUr%hG8VGN
zx{NgxjVwatl1A1CT@Nx2vO2nqGyJG{4basglOU_A%Ot0PY7U1ZD}hlFLLR~jx{x<C
zAK82YQ=wO3n?7arrl))F>1Dn@hBp1?j$%EN5N;8L{2NuHWGA=pQt!Y1UsBU|X$EZ3
zrlXu>Y=E)RbMAKlqsvutmBvRpc^_e#aBUbKf9VNJTpQ|kOx)~|6o~X4%++6vUPkn)
z*%PSmFv*h3I$5_vub@BP`<S>t4=~AJvz>Ol2@K0KPOwY&6jbIXuLy++nI$utuKNF9
zRMxnnp2`?j{%c?i)!kb{qOy`tS(#Bep~fsQQ{rXD(6r=0l5irwUt&~VXu*J)uu^0U
zy-H3e2`{R3I7XF(Zi!Hk#JjgerVL+KnE1yG68<Ggj3KO?%JA-vy3qe=B`${Q<rRjn
zh@QnTmTkmn{UW5XP|GP>g|v!zTc!S8`!d2E+X=`Rw##XO5z=*nXFmsmxT_NqJ9!3(
zdpe;phMr|bM!0XF_Xj{vrVvnH0?Paj)M^mR2wC5OOjSW-e+Qaq0rAZF11V}X#|Y02
zb$}pCLS6(Rb?RG}5%OI~AnGwffeVQ-xObBo;f-Mq)XJ7O2p{F^91ME2hwGxUdL5)5
z{Xl%y30~??#21~A*a|5IM);}|PK~{I71TGKvKqT~?2GE_gqyJ=j93@pZfw`TFT=Tr
zGMu$Jo+De9oR(KU_uv_xeS&*$RtZ~!da!Rm>}HixP&2Xy1H+`U<vR612%-yt;grfZ
z5imQ3V&yrdA~a?800@awqIW5b!jeSelv<Fey2Q#U%ngyzbcq|MG=apVOWZl7wM}5m
zx}*%Jw1dRLrU9Tlr*tR`=_C$y+F!0$7#kaf7ISkS%q~PwMl{z@*44h;^(8zr%ti3V
z-fjCb!(D{LO?|^Nzq$yG3t3}iMz{#8u@eABx(GMMzVnj8jACm6*sY40Gw}?=eLXBP
zR*pRU3aU?inX%~<syueE!q{De#LawSWE?I+Gj{FJmvM6uR%0&^#ax6NHza{$in|DR
zF0QV^lyDJcj3NI?6`b~Nfhtpy3#167Zd@-!KvnGSQo=o+XAc*_Gxp7^B&H`<6H0DN
z`g6|&m-2w`%G{aW5;O3-GWV{T$P983lCeEH_+S^IahZS1%n%phv~nj0v&>Kz<;F?5
z24<LxaMydxaLz_gxD0ozKg;~;l9cDRR~48ME}|kwJ!T|lI}5cc+`K}D8Re4H;g-}f
zFu%Eo23-3A0yEl0G~uZ4i~%%_KrOiIH;v3#m#7WLO=g*KE}{cRJ!!lPy9?K6ugpwv
zNqTd)_HoQa7tx<<ElbQK7cq#VJ~r7E_AqYnXPNokB^k+8G#QvFE@BKv9qtdO3wr{W
z9m6tHU7~4vqfc`YGq|gzMP|B7Z8kTepON{~CGqCM-W!;|T*N}g-pWT{W^hC3*_3(9
z{bIzk!Lxhsk~2p1i4U%O-q@~hU*@AuI2k+}3>lwXA`L`6rpQHDLDXkHy9hUK(m(_A
z#YMO?_G?#E<}3FGJ-|wXvN3r!9P(ArKN#LKlEq}k&^aA%@(II82vmu$na#RX#maG{
zT2DlzyjzJsMSKYkmg5+X?}!%+|E&qBtrm0g^HT_GdbUbfQ&f==8yb>eDZ5KG8;KZk
z&VCRXskTPlgJJi#k{GF;PVnr%cVtFts1p+FLqrpu(AW(`w9pAFo4XGHt#!hUF-&U=
zsw?-9T-1@BbtB2g{#`O7*Vk1THq|0AawDDK*@U?wBRACvi7nGpU}P7p#u}O_jO>E7
zvfuEs$n9J{q~6`TGjhk`6umoRunaabawo1GDA`T+`b_>#>@YBL52#beWM9>VkKW%M
z7F<Ut{k}WAg|C`CKqoYI|6lMvSSPHEAs#QGJdE3`!z#7<q7|jy6aQe8I=TkK4w%O>
zimOgMYp7^s6jz-j_QO{Yt~z0m{~NH%_qJjT_MS4MwBqogbUj9;!{79LqJ21APfG@R
zO7r7YM(ND`3V~clty5V>9Twci2iNsr7*_m)XH?gN;aUIF=omj*P|0K&^+yYKe<e5>
z^+ywyJE<`0_a@YXS3Bx8ac5g!#yH<iC(5u<o&uv%(_sW><5bKL`szeQc6lyB_(dnG
zur-PygrPc7gE5?IW?<BjoX?M1spCf@X#UtSYJc9ZC#uE!H<r*jI~>I4i$7qL8J_=V
z2agGiq5mo)qyE8Rgk~&c<{nm7VMeOU8Y`&x79Yg6yd2##?9@td6Ht~Kgl9AAL$adm
zb#$}_><NDa8eDcNBn{cLevqsz*8(=qCT!3>P^&$9f@;BzZ4JFJooK_RFe0O_(TNUh
z<HM+Tgidr}?MKjz>vf_#JEjZ(HtIxgw%%3{oAs}Be>SWSY_^uAwi?7neFJo)P7Gs2
z`pA{%J)B+PR-g+b&OmTtE8H6Fw_z8>5kr6Nwc3GT^XKr1Wq9w;s41VR7|~kZ=M=Qo
zjAdZ+G47amFoqZ1I7Vx17y$zdS;=Lz7EM%`e8^=Pt(E>nT%A*EtLXzX&(;fvsDmz&
z*#4~qM(d&z8atc_FP*TmmA~M#-_t=ukQ=+#C^1?eohZh3IiWIIf1N1Kj(-GVpiY!v
z&wVm5+7O*^XOrH;X1Gq2WDI2{$&6DQY1l|nR?)^{sKcD*UxYvYdz3jfFjbwb6FhtU
zPe`Wfgv9Qw4IeXfLSxHy12IP@tn7eo@G(y(+}K)oct-Ql33t|518TlHQHJ%BQRO9?
z)76i+^nl1u7gb~ojjMqQHgrHdvbz>q53^-<+cxNj>lzGu_nMK>B6Nb6x_0QuXd84w
zlKNsQrft><P3q9SJ)>>Y2`l^Y3F;E1*BztaTuj5XSi@Z>`6#2sZ~mW;{kr~l9|=0~
z-A9s6eD`rwC%*eQt`k-^;Wh$4r4w!}KMN6`(+P}%=R3gtMMEq2aqoLxV5(@TdAN7#
zFOYVvJQ1!JNV`#v`U|hWGuo|kYw>u>>-}20T@KSFrXnMHqW2mumH=d~Ar_W$8B?t>
zCIAFKRv6Qd5wOE2o-zFx$VX*C@?#isdO<?N5Z-@HA8btRzt^GiD3&pG`d$amPcmcb
z`lAkp-wce&3xB`A7N(iIaLc#HYs&D+7X`df^Zga3B7fe4VLbTcVhmG(_dm!np8UWI
z0<)2y6d*Dgm>pyEH!U_ygR#>>5Qd0Hh-ZbJI)mj181Cb;j7$g9s`X~niG~<cXa%}=
zwU8;?gDT6jRrd&tX>Elqkd$X@3Lw^b&<ds^8+i`I29G@;er5|z0N7L^3Tjo@XRjdH
zqN~+lH#@6|jA@&$SBtHWm4j(}x%0rT!)^(KQFMhE7&Ty5`hnP~6HWAi%@pH716vFB
za2g_y^GJYAOE!A|!<gcAqLu!{Ob0yZiM3%wny82yaWB%EOYDb-YS_}2b26rLhRZOv
zt#jiU&tlXM1w33ZN@6Keu^4rJ7egb%*9gbtPY8@{@G+LDBxiv0-J-C##Qf}_*Z4bQ
zVJy#7R;X3KGnDl_Q^!&GKTMmm?L;F}&u#DjKuR?HMP!r=ahL^0`ehXE7_kDTF(Q3r
zOK6ojMtN!U`JV!{xIkY?#%x<CF{XnY&3wX0P8UWbbh9r;M9o_l#gm9GjOe6T%nj;b
zD)Epfv+E?&FBCQ-(saSRtscJh4|I7h$?3v~G;=Xe#t5uM>agy}J?XH5en*d6_=)mS
zA~m8&cqJzIbBy`9u>q+P!^xD`z1_elIYuvH=@q8>FlP6Q7-M$oz|;N*tT&}j5;`N&
z<1!E1jj?2tuIcwf6He-2J+?~cM*iRmbjOJFgetVDsxs!gP6t)mGo?Ke1>ITPG7NeK
z!$xF4v*H|N5YX=WU$!@Ez~e55d1P~!VhdeSvZ0I9a|OFOH7XZ0gQ<+xVpxqu$D+PW
zfQO;y__sWZrJx%<M=oegvEuapmw}2G35UDk!WyW<azP`RV)bxC!U;cwZa;*>m|{J@
z3w?hGi~SG|Vv0@rF5LV>Sp0{uKT~qiccJdjS>lJJH^Y?bfR*Y?h?)NQ%SM#SA1^Rx
zi2hxtt88l|F>ILLN~t=h6B?*^{1%Q`Q=EDO7u2P=$%kjw7N>4w2-@c?RuOtsi5jFy
zHQb<A&=9oS$&_rv^l(Xa$;R)JU1*f5^^lNYy9pF5{n>}VYy>@zlHGCJ34e>%9b{k@
zY4rYaLDLwfTKmutcem=!;*7!EOl__<Rl7Ry=&FFk1ckxqM6}Vw7^G$%LUV!SG|-C{
zM)lxHCh4;8rX-Rbtg7l*9x@9B1qx=Du}4{03z%6}WK^}4YCsek%XW3J6`*JGfG>QZ
z8FMYRbxA!Op{a+Xa>=fa7A09n$OE_XV;ksDtSipeB{_G7vFoAhv3VFMAjc0SJy=q4
z(<5@J=phwTSsQCNQgp?CXzNuc?Ghp7i@7y)N2fCXsE3s_OS+8k#B2R83J+7|l7!U8
zeO^hV%R)95a~o9Vd*#qwfBIQ(zOwKyxLTKh%6)G!S7V|%%A+w+Z;xVZWmFWeSuN&!
z10X0@{qeemXvIqntoRdC*Fhc!se^@qFsk%_G!}G!1Vb=CV`4`S^?&V9xfbf=V*KBl
zRYLj{FJ-7&iw*gscyTA$R@3XKKh?@5%fk;tJ&40!*Nd&+=pBsis9)0`>hbi4-URwX
zFERb0m!AI6DDmS@Biso3Ac5XQ%zdn0q?U4(zw1<g{kogeixweTiPDvJo<hCKnuX#!
zFi|%AWYtB65Kb1{+=m(&LupYcUM!@0iBjbX-hr%OH^>e_i7tuNt7Z_4f5}KcN^U~&
zq!8Z{^*YTSWng$i>k>K&@50*5x(lT?Zh&4Lmt+3BAj(qGr6>4W7p*}?(y*N^C6s&5
zg?uS7g)I>>*}XA$y)a~}du?a0;Vk2_;(1z-;QwA20R`qwF`99|zEAfZv9J=DA;(Bz
z@E|1GnAu+xTn~IC{W&?L<MoZC)*DDuGJkrL)N2g!H*S}3y>&*#_0eg%4w_2W6`M%k
zd3p*JhhGybHkj@&w<CiucaR-KGLQHtmJ?h-H*%K1lY@rMN!p|dapFHyK&eS|t=p0G
zm1sh+C6bj1?TJ7OiQ_kc?)S&h{j;`Y8|HK)voGVwY~%`Z@0UhV`+OufW$%${0agZZ
z_6KqP`HwWaHK+C%ah6(W?;=9z_<%HvUnZS*O^7oBUmaB7GPxXp1TF4!2)}z3l7?@j
z`^UANR78v=rGaZnklTdZ-{?kg*9ysTD{tg_nFCAcx<7|F2g;J>=sBd*C5?h;dYPn0
z5(wvb9pW^4L(;un=)Ue8YKivo<g083;s1wMQeZZZm7P>nCe=Z1bltg$R6{ON>^WGu
z;#t<C`?fu(1_`MI_xl#&zj#KW)W1#o*Rj|UnBZj;)|HdQubfRfAyvptliqZVeo35S
zf6;v>%0V+{&vA?sMQMsCCYRhCp)4*ogh;7yEh$y<qOjaBITo0}#l-QNLUrx8ggE_=
zkY=?gLa_CxAevzrE-<URQCJ6F6KB5O!+LC_`%5(mVbEa;QP>IuCv$5DIlfwz;4*3w
zP%9HbFe{0F|1Y}VH;Ar&g~ZvSH~Tg{&;i8>ZnYaZ+jojWzi^fAzob%#ae6hjejuFz
z!^yp1Auscj38zg6X*zR|vlEzwcgaE6YKp7;Wx7TqO(ihC`ipe>Bi$ePi8R06qx+q~
zq%$If+>Eo3V@`i?9+OGBu0ElCjVEa!W~u0CZOCP3?8D*3(;weCE9nF~dlAsW5F)tI
zbRAlbl*DklE<&ym{8-ZYdX%JECAyE9NTAR4ZrjF8I-aA+F@rU^z|0*<&Wy8&lj%uT
z6YRtpXD8|Dxnw&4Yf`jRf!_a16%a8B`z->q`~|^Xtx0BMjAXELECF@9Mf|rfNpny>
zT^Hz%tK^YRJzwJV$sjk~8&bXP*b&0Ck9Hgw<vz8XxSXVERS7vFo2<H;Fhzp{nN<7x
zQO%4g<jnqr#0eLuVFL^4K3O0L-&w?o4kiaJ)98MmKD@L`(OWT`G{+2~`<{6u&D~Be
zhm|6JO{{VRrq&GNSFB840^T7-ATT?65i8S5*Q&o#yx)B2dODm8ikpcamPqa|>Cdta
za*SBw7EnEg`%s(h$7qjna42yuEFt%|*AT~oYylo<00m*iiV7nNa%=*Vmq5~X3ZzaZ
z?*utG--E6zJCo8TJqWL(<Z@gVK|BtiYuN_`UByf~9_z{RA6B|==|+JX&Jky92Hm&X
zLAG^8x*jef_r6!?x_1#t&rPHDsG3Um&SIyjI~?>P)pr9Zt}aUm^nL|W3dU?6k<KTb
zNAHP$p*7WD^K_Da*h<&YmngU;9O-1=B7_CmbU)}MxlFD^R$()#daW-JzehFFA8sO#
zE1ZkT!S)KIv<zuX)TslBt9PWjR_{k<Z^sdTXALseXd8~P_8`v8U+H=fnJ0lM8BX_4
zFjEzn$pcCATQb?!Z%rZ2{6P1AHzQwl{-X*=Nc*8<j&xF^4J}VDkIbQa?O%d>wu69<
zwjiK1ol{PKVG7QYG&horE6gIR?Ue|0#}0BZt^r+bD(OtvM%SU8=*sRP&B=`ktz-td
zZ(t`)wXc!-fA<0s%$`TrF#VJITYsu$!Y2wMb0jtC{X8=BtVNF9pOUf9dIFVp6DMak
z>Gw*ax~@ndX{m$cc(^`>jxHjczq1H`5lfXkj%^*Z^dyD)|AJ{`(4ICdnZkAiWRD{Q
zhcDfK+DmTc2n6jjhJt8zk$?^jB&*DE1hkVU(0fD4>hd(b2hi3jlZRbjv|nf9w>?DH
zc0Un6P5-jY^9GKS;gFO>yeH_oXE{0063M~&9(3R1PpV%pELxBr*9R-*H-hl@rfUI~
zRCwbt-83>!N|Cenjp_cbmB;n^bP3mRJThd&cTrfUgAKSZ*sI{W&?e&Q{JSUB`&<~+
z(z%ih{%%O1>TPmt*-4J$vpDci-ltkdA|)a)>Dcnaobe5TZu^@wx8%^hhFK=Y1A#PO
zIS9F-MsB)JqRM=7C(X`Z2>;_vBlxWI2^k!EK@M`8kZRO0iZQnvMLnh#xhZHts#`*-
zg+AqAjAY(7BAv7ibe;JtJ%~d|<iKB_@jb;7Ltx4*ASsK4I+mSH$#!-bx-P_|#>h;_
zq)@~jND&$t&l?2Vx+}T-Ydx8{A0w9=u2ER^8c>bh^9bnVW`eGa-9CZw*8BW{P-^yX
zv6%Yf`y-V6Iv#cZc{mpKLbaTxaMFJKY~1&su>}?VCF}#F12Puke&DA-SULy&+86N;
z-i55YFk}LC#nFFG#r^nl^pTl%jh^tVx?jL|_V)m10V}kD_vP&DlPFfR1xV=&q3o$V
z1R2J5zX&Rv9rX{2HSCORn5|_?41v>iY)&4$u4j)mL{J;pxJ@wM$U5CR!`UV_^9EEm
zv$wHbD{Nt>(YInN8)F1>8@qV~n33%7SbGcG*+cZ%i(=z@0xg<NZ2;^Y?CUNt*vTH4
zi*B@wef$L2G3*-}wPRV2M3~31!XYqsvk!g(wTEqq1{U_RbDYazAJ1YBoDuf1HC6z7
zKYQyD{2pMB(=6>E+mlA<1omJM&<?SKY1<-^y>J@tli2IqVSbohw-d}G>`)qCkFxtW
zAedyf`zN3rV>{76beuhfO)%jE>$?{2PqH_uUteYalARD<V-Gim-|H+l9F2X09Tf)b
zo9vzAu(-wkaTJl>Vdo73b~-y42^8TjJBh}%d+Z|Q5rjwVp*L{&giWK_RVF)c84R-7
zB>I><V{4WMGl%_i6YO5G1xQ^8d29sD#9y<!zepJW^4WhUf?L2ki%`5_=V!uiAzPm2
zJ8#)H9l?CZ#`c57d)AT<>H}-9f<Qm9=L&#b#GXgGTlmaI9f9l{JCC04d@i1*Q9j(?
zD-fX{H;?<?KYxDmAAlO{?g*1VxOqJMPknFzo~G^Y4!6@MO~w76&syn=PDZFOu^QBC
zr_4kJ>(t+bYu#WhNQHVW%fngyEb6-(*-wYCV5Q#AU#*PZWb91SZn07Y07~Am;K);W
ztZ+%gBY!x;tK!oIFW~~V&u1q97P5sH<Bdz$N=H$xrEFKs*^JBB0_3*@KlW@zyqxRV
z2Q-1*z)Fvy@}4bhhp@h|ua5)FmrENC&1KxfE{J^<_w^#EaIVR6KyTn$EJp*xab=Ng
z5|X)_zOcK<WxU7ol)|w%Ur&Xg)NNXTc{J${xZ1z?LeTQH0h;}A5{wb1yqJRPa@JQu
z2$Af|-+*|S-RKRI%WPyKMvy{Q!r31kQ7JhTfYwseQKRZ#ub`SWHskYPteO8029sK)
z{=+_8Z91`ItP|Y=L$0yz-iH`>>Mb^*o$6P8j4Cu3vL21wFrzOJ8<jnYI2!ldg{Rph
z?-;I4^J!+%>@ZDV+FxG?X}1b%5m?_b^pP0uf!zaPLV73QOrKQ+(%E^)(+Tt0iT<eE
z687m|zz$(EivSYJR&Xj%+00%rqKIKLRDd2}rwl;Y39KIdAyyARk=5f*V)Y6fX7w5z
zVJT|k36^SNJjqf`T#ay##`t2b?%-Oo$s=4#Z{7ii9_fjQv{K|;v}a|h4BF9IlkJD1
z?uiw!tS?|h7n+V=2Tsdk^cY)v(^|blS?V-h57Qc{XBPog>o?OId31V$C7N9W<WKq4
zaqn4{#`&ss{>8Q7$=Yz+`ma;qcdbTC&wdN&t@CEr(^PssJ09Eof{&A}I22?UyXXVJ
z!`W5~5!xEI#(1>SW_IyhU~FMu;2;c!!#(s#jAa*)VI14#E&T3g&zPZ-z*f$J`5|`g
zE@&pQy=ZZNicOjWgVXGbgU~#~j*mfAZm=EuL**uW<qF*1Vx2|`Gm8!PgGDwgQDrb_
z*rEE4jXVwe_w2%-;qU|7Zz-6IxW7t6b1^saGaN4AI=X|on%jtDUqUE1XBEK0xciHt
z63Lz20<i7eH(K&WaSD=6!U68<Y^WUM#{G>b61eux!*FqiORtFfp5=VMLU@I%O9_}X
zF5eT(`&=wNvj<!qvVY7;2hg}#+}1asUUJ1WG}k*Wb}B04ZKymIcD{z078ooyMEgP0
z-|+e>RKg5C_W>Pl7+oHkTMgC!f#x>DXfG$qJ%&Hd!_!{F>2Ux(Zukeg^uh_lMoirG
zM_m5rb};f>`vPRe<26w4N>Q_sCnj;bU`%O*_BU3-SBII0ao@SYQ(VUve)~RzmHK@c
z>R)x-7=YI3bQjm!AF%T&)LZNUduPMtl+0){0H1xKd5Z~Pwc7L??cKI@4+Pwy2%FkM
zcQ5Ri3;q9F0RFI!v^E=4_XDKA|I-22sRQ$Y@TV~ybx1Pi_C<{j8z%<9=@H|^t`MCv
zMpDHt82>XucFow(7ryQo{VV`-rie|(K=q9n*&I6a<*d)BYmhv=9aQ(3H`BK>$=v4?
zJO^1#eL$_W<{bFm_hZ>r`3USTYq<_L_u0=sfqKCD(D&;R``R7&kJ(-8@T8xxE4QOq
z$!)p>XREj&F#rtZB1+Mi5yo9VfMN}I?<W|p<)VH9+B(kfEsFJ=<1}D4a-I8w+Qh{q
zKywS%p$jU$l^YR&DED)B_n<hy?V|PdRn8KMD6VnkFT%wQ?h-9TZ*sM7z%Gs3M@#nG
z+@+>qrgNSlBECO&xdAf})O{|o9=H#<8aN;)WN@KV&=8NfC6sY`!nOJxpijBIln%_|
zs(nOdvbpSbU_R$!C&2CnSNsJ~a=6&KFnGna#FhcNWa>P~<{NU;Q7ka5z?n;7p`q9y
zM8C-3nQy@Sf3cw?4jl?nhSKyVM;m(6v$|$zdI;2YEGhwW(@;DE4sRKz#({a;5KRln
zJBH?zbGU05L5t~ohWaB=JTPn?1M`Q5eiu+YHYg*}2u}=`wt>ntT*gkAkY$*41Ypk$
z^KXH2J~yP%hxesn|1@Cd7^af@T*JgrP<e*6MNrK*tS$kV0z>1v&@41er<LGa!!IjA
zy*HdMMAbeR*3(zvlVSQp*cBOu-UaiE;iws!Uk!mc4JORzPbQ-AefZ;lfa%Nc{|tjg
zPQKF?I9$Sazm1A6<vUJ6E&TY9op89E|A5y_2;k2a0WFYM@4_&M{}chuVE*zvxL?Wd
zwn1|hzp)i$p?q9D6k+^vN-3=6tI=0Ff{$DVYCSLBL=+qNQB;>rd~OEJH}lR>2NBdZ
zeqR8hh~%G9t4Hy3<{-9ce%C@+?BpA@fyFNVb$w8=d~z9}#qrfC39^U3+!A(sd5@N0
z?&I&=MHkr5&q{+q0zYju+#lkz>jNx_ud);7hxyc>p>mWjZHG!SAK;|*<8giv=KjJ7
ze&sn>oZ^Qnh~hLqn`T*O`2p9#JjX9M1<ecm$x?{>B0pV0af#p28Y-9h^ZS67%15;T
z%2j?#FoL<xN8f_V4SvE6RPYub+zcpbd_Zv++~F&)Mv=}}*hEXZdwicKDDLx#O91nb
zU;7PJ%iuQ!Lgxt|dIc~~`NqB|viN0np_0uT@4&@#{!TS8U-13zp?JlQtp-oI{JcNV
zB(M3N7NF$wHEF*0hTr}f(HHW0cOiSndk4YbJ^yM3%|Ac#3p+sd6JI3-pr3i4DQK@R
z{L-z^@fHGTVKHC$H4BCdgepS-vrrgO0ii7tf`36<E*3f#gWsjXL>YF=1P>7?%Y~9E
zH2sAZ!x3+wV7vzpD}+pX@q&eW-N6hI_9bHdDXbPQb%Bde;h!ux3>Qk#e0z;hr8BT2
zgjJQGx=y&W8ulB65y#NL8-;d_p|V-9{0qA+LYbS?gM?=m_>C00uAr_Xyz2^2JA`f}
zp}9*4h=gX0(Cav4aYFT-sLO7l9ladRc;WC1VDA&=(%15UFfbi{4+@tv;P;T=HU(6o
zAkiZEuyFh)RE`MsXTm;NSRDrYV}eMNuQZ`rD5%@QZ?qt}D;V3r?>*tmTZHyN*wY=d
zhe8|d1`CgbQCngDSa^sNFv3&hAHD%QQ+Q7~qin&KzPZnYR~HefxA84bjS2IO0j<DX
zU_3t=F)cK5y<o7&_^2ri78`x(>#@|BbOD~08GXEf?QiTrnXdrjBg#Dm84JdP8Ejm6
z91XO}ctL}~YNH=z?!t`D_;fT>xba*vbk-Viupg~%3_J$EsmA|WfVygYI~1xnjMFkf
z-89}E1X-F<X$FJa#(B#?r5j(<%>AyhJdTkG_l-Mif_h*~ZHag@jJ-rqkBkn=={zw$
zazji{je$E+r7YtpXB&WK8-Joa%5&q_T?p}o@!~WX<`~lkLiLp~^ejBRHol{8aK6zq
z9x#PQ_7d#g8e`(2`N7zGGNSlseEJ%)&&IGnP{S|AAuVD4&Df3dMBd`%LU`~ITi=9i
zf%xA?P_g3vLMO^NF`)o1_K5d8z{Os1@fx7*69*qa1Me4^8UQ^gR=y1?L2N3*Z=%?7
zE?|<xTjjt!BDOpO>ZrJ}FJ#BWqnChrT#Tie>q#;17pR;PPg64djHo;W^Q`Djxytim
z$_C2+UJ$+3L6{=Wq;%0Gu^i=Ju88$N;u)rj<LT3JO)S?2)OE2rb;O$@OGDu;@gJJ~
z-xg!DLERCP7&P8pvBO71e@}cv`TGZAZTwU~cqo<~iqIa3jXJ~cV=*un{xZeqODX@G
zB?iU-=DBz}l^S0hOZ#iD#NTj;NXQizIbfeJrqhl^f%vozinro`2Y`7eF761GkK(`c
zVem=ZKt1q_$kXfpRlLy=QFu#@TcJwxrRD*k7D%155a>cFX9qMFNmY)ba4wbxRD{J+
zsn1n-S|+_%0MO;q@;NZ{m(tIo2$XDoP+cLV%!Yliw1Rp`h;;QRidE9r`G{$?^v7Yu
zbVBlKjcT8i+O<V-MyiBE+QM0>+@ElNL0UtZ#Ea7UGjMcCDoO9=Wv3*`aF{BE4+QtB
z6w?7{*QG;K@eFQA)?O&mq+CB3-j-(2G9X<#HVW8xrN0B<{()3tE9@RhX|${MSlYJ^
zpiiXwgq<lZd<I#TG;}e{pGg<6s1}|}(`gKRDUE%My5vaCf}IF4SNhr=7I{(&YT$fn
zAx<s`1=7H0kQGXoX^Y{lG^rDqAEffMN%>Lwc_JJZNvkMV_*wF+476|3yh$j$<w3on
z=_8jt4Qhd0vLB#*<;+Y_i{y^yQ7n;rZbBuN%B7t+A1nCDjo!h<aycRkkp{>w0%0F0
z7gCxlNH+R{3YLdP0A`iEhUSQ?<<4i|H%z`44V7@&gH|CCa%3XF*2%wwfw@s0k`9$k
za*b3_Tjaq9(H2|fD>PG$lpnVQ%69qm3d+Ak%MAJ5A#2qU#V&a~&C+7zHYOBt@}w7F
z?v~SO)Qp!~)CSBxIerMR56F&}C=SYNC!jL7<c>6^+>tA%AkcKV<7t@RlaIxrxG&f0
z1HTXDu~7iakbSWt7oNyF>QMgqseB;;ac9XB=fE&q{;4-WpUZw1Vevw)*9y#6@`}1p
z$(1v9gUXkqrXz|1`Q};pEtG$yU5mGJ{z}N+%RaO(`9Utx0W~X<Cy@Kk@`B;;`&G`^
z2h4AB?L9D`uVe+#{L@ECxeDxs$~Rg|`6^{-&|a*xJpr91N}KI4T&8&52ezLwr~oSd
zioqKy0m>5E<6NQarP*DOvg$v`LX?S^)Cwz=<YBN|tsJp}3RUK=gTY?q>@Q%(D}!jb
z+OOnYKyx_{D77i)m!LHJ9Z?)o3T7hUBxSz=!o$iXBrt@dN-clDBr9EL{(4-wvJ#$7
zC>MSQbxOHQ`}C)ker=$6R_Q?5_jAgGmx$?tvV*cN7nM_eKwVZ|oCD?+WkwemTvI|O
zLw4P%RHra*D%)s3<d!m|7ChZn7P;dY+))y6tW3D8ETHYXdrD*mR30jC%7MyIvMHne
zSQ%Ie#S`UM+FHz1l4vHAr3`tA;+ayLc5R<4WtRZurP3<_%pBzclG#G85=~nud5Uv+
zU!dhHH=-ddQ2gj)UZ`X~ho`s786=^F4@&AH6d#p7IJ6@aDIIbF`dKOQ2+!xM^58KH
zzA3NmV9r+qC}-!RzH=b@HR?H9o~%`8P)}H=T7QSidi7`ug4w9PZHy>3sau_U;C_o5
zPIJty>S)?%ic~Xr6x-GA2cZ+K{^<#7hidKtv|VZrEuCUiLn=JQsehgV+HN(7mbH7;
zh7vr*t37E^xL=j&^Ls$O?E$|D>iGkx?;-WKbUdacwI~(EVRiR<T7M_2i|Rr3m>NOr
zxDzTn48oIYHf<4|Q44SgUpT9_+5qajT8_HV1+^TVf=E%*$AP+}8rOrmqNdQKB~|UZ
z4DPR~{b+;my84lx{Y~|k6)?Z0)}=j!+v*e_P<PY?WwHMu+*RMxEbE>s(^Bz)8cQkV
zhw7HyFnpx$e1PyDtA|Gc`>8rF454MJZLUHkTb)GR>zP`Uc0OLHxjc%OYTI}eU(~2=
z0Q1#4|Ar!1E8P`s7@|$`M@%a<3+3fkX+s|C^G_}HJ-DG-jbIdE+LW`f2-o_TfWx(#
zKkdLpXvsE2u}*tVBini{g%-gZw4)TvMy+{6*lp78R0OqIo01Gq+q7t$%oZXwQwc;E
ztu3d`@f})C8st;7m_n#r(gJCCbzatn&<k)yJH8P1soJf2D6VR6KcKj#m79a&y5>uU
zH?(WTQQXvuWBo7O(jNVTB29bU50%N#YS7H>k+$I#YX4N*wj0GWt&tI-J=gqlK)ujb
z&qwi6drT?a9Bn^sW4&@}Wo8)R1OJy#r-LjN@}I!Q)0mDHu6REYoJuvXqY^)t9f@!&
z*R2eGl~2@Ps*Vl<UbXGCu~mKQ3Fy@5Tp662w>P4;wNlW!LhX)CQMo#$Iq26N-xdh<
z_TB_${eLKk1{d36{wp*rXb*!%mJ_H!<Dyq^&}7#taGDOD1h{5zkzo~@@1&emi-WXt
z(lVajz1CeW<Ju;WdSct5JD}6<7fR!|&#4a04h5?ame;!W;18;H9{1yq(f;G?MHhhY
z!+!BX;m>N$GAP%u!NsAsfgRBgkXzX^e}EayuApZa%VuBso-AG_`mcnVpE!5`qFXM0
zxeV9-Vj9gS0z`lM_yvlsgCJWW?xb`{khr`bJO_)FX*v=jZeNWER*KP-Xjmn-ng^zH
zwK&fWs-dEmgCa~Uw-!#<irsAhjSxT81apHpon~<x#Ue^TZW2FGBWxBw(K>#cc#g)E
zNO8jggtlD_jD;*p9N81HXz>tjUF{I(jzAPU#o=S&cb7Q0Brs#d7+QD4I>kyd$~f^c
zZ5!+scTR<HkN6k%y)YAgKMX~@Sla*>`@|v{#eOjyzxEIgh_5HY?x1+;9heDXBl<uc
z5-qewNEEaFMleZYd?>;`EZ*@)Oh-g>GGs@^fR8AW#TtoVo)Deosi97apY4eBlo&wM
z`qSdvR$!hHkF|u0vtr{2#C=Z8FM!|kV(U#XyeR(L0xnWSTYVIl#O-I%>X*fJ)nR@`
z?3D()R53>Z%2m<54OFg)g>*9JrWi(;x5Nv#fte<HJN;1J7WXuR>K(Bae!?ZBi<v(|
z^{%K=M(3XRp8(MNqWc@Te;_s`n1^DuxoFZ1u~q{F^GLK{j{@`Rqx9^bi0dB$<*8_-
zwMC}*YyfJOCB~J5-)wO@t%9D3gUIc3v2haZzrPUM(vt3_Xrt}F9C21t2w#Z{ih;@%
zpFW2BJh5Xair3=IlK{;Zb192oAg18JAX103+!1J@*q;uVycM6Hgu{2@06G=-UgRo3
z<&&832t|=t{}^On#ZlqV{3gE2GhqDnmK1%BFMXnKnXlBETr8G)tU|Fwy1_zqnY3sO
z?ER$4bfRgwbZjeR{!)c4C<3Gr)FgqD5kH{8Bz@g@1R5mGqB(Q0^ecTWL!|l{FkdO{
zp&qnKikl27R7yY=!YPDF3n;d5>FFtW+9VAfgJQEZdL<&=BF$(Ci>=a&hiIT}QfC?t
zBc;(6Jkjk^h4)a2l1z5Q6fJe6ROt?>DkaBuO2zgdrd<+C>xUR=CY_Utm6}Y4N}P1Z
z2<C3-c?=5Y9w~b&T<n#4B*8FV`k9(^pVV^-K=(_rwA45tJ-COqJScUc3`c_0hH`?3
zq`F%XXri=+_5qTlF*NfyEX`~P^CQwQni(FIj5{DpmPSy5@t7p<0d-vJM&r;4$(#x3
zlTPW24}_<ru{9CR8R;S|{?1Ch+XC&JREs+Dd8t30B)lM<rt$Nl^bkKr6H=sSbj<FO
zwC6S)UX~Im!Yfk#NH9~S^RJ<DRl3;;o~}u^XruYMG%E&}H>7Hv;rFIAusn)elJh_h
z=%h(I&I9|lWX^)&9cjZ%6zS40bms4_)a@65-jm$v2*!Qs6HZNF-7}3w?uSyFVsM`!
zeG7&AM^efGpgfj3P}1g!luh}Lr_zI&(9D!JYS7G*8qkC%TMD6U+%xH{vkX+9OD~Th
znimp7J0&kAn+JqB(%UO2UP-$szmqEspq9;(CKbT`we&AdNAjhidtp!@l^zD>8>zz?
zgjOg`90kp{QfnF^eB^XWv4zSv{)6TkdCNOgX{|hycF!W@T`#czj}=Qj+Fx2P@3X;v
zgS;>t_8aA)ogmvJyH7-fo8{ZIL$*a8n1n#L${%RCw@rRA97UwejYF|r4jTjWDEWB_
zfJMvIXn5Zto9Ip7DL<g2Lb0+$BSf71iZ(NM%Oe&mc>nguS4Kl;uUyU(e&c0r9jJYB
ztspquFVE=-m;>^4YMFy_#ZzD=$ayEhJS0D80?kDE#VbUZB&+pdeps$dlba)Q@_58_
zR2JxvLbCkjHq4L7e>O#NTu!7J{|Wi0oizVBDPQUUi&HW~NuSfQfxgve<inqUeO7+n
z2CC=eVTWLNUOuUyNiN96kQEUw%4cY_O_8T`fZZjz;|^$Ema$evN0diVCN)(qhylt~
z`D!CP$!l`JU_f7&SN#jH8*;V7aO=D&Z}o-hEqUyAkZJP2H2`{B-cTN@cVy3r@RTlR
zOaRPX`3#-KyeFRtM4j%-r<=gwfgDaVkB9QEv(U_t*L4T=NRIVIOi$&!J^;&<3uYsx
zEO{&?A+zPaRNZItjy*tm?v#tsIhz-98XX~eDc7c4NRFKO7}P5{gmyx5<-Rpwm?yuX
zLv63+Jlc87m*WqkP6e_$3(Pn22Ra~BD7!s?-CH?>CgShpEBGN0R)le7f%!r9YX<70
z{FL_gKFM#3BZ?x~xqmc-pXJ7_&?aBx$cwQ5D)+Mi^qahV0Ni^kL3FNQzG7ViP#@*i
zb}$zxe>{T9LZwYO3ST8J1fYwQp>zawvEsE6noE>g?a*9HmH%kXyG&{N0*?HY1nLmW
zm1W~0^H++T{%{zetV@7Jpz<XG_A8W!v<DHS{6SlN!HUugsv*h?nvbtm7EXYtP$ldi
z$ikE-lmQM`HXK5+Mp@Mv!K_uP1pqTbnPY>)bxQ9*6zi2t`tWT~GO4vUD$VP`e3Ozl
z#R+n=@?jHPY*8{x17@odMeB%diXY|gB9*MB@Vi|JrGw8=N@yog(aLN(f4W1dPt*FH
z%J5nUdzTW~5LAp(hSt2X$~bz*;*|8Ju-mOf#e>?Tq~UlJ7Q$Y%rioY9F|_{Qr!>6}
za=#MT2_d4+ZDD^<nL-Kd1jV`-4i725bbvci888XVB&A+IfF4%bMS^)m865-WQDw#<
zXeKMu=-kdRC7l*;$CZI2fO$fRpyl34W&0XLaY}hh>FCqSxc_MVe@6K|8bO^^*1tn>
zPDx&iV9qNQwu8E$1eAu0i^?NR(y@X*Mm_L~vWk-NsY;pAXs4@6Vgf*~DduL-ysrG@
zfTtVEKeR7$Q<*^LlW!?~{NXT7!6X^)mNMrX4DKi=T7&6KSBh?-ysNBofO}6VMpOIy
z%0S8;Jy5R3!TzDL=q+lIp$r}ml}AdarI0;V+7v+cL<yXQ=6b4_rh%EMWF3TNmU8qB
zP_mWWu26ZV{JIY+&z0UDkiAg$?g8~usWAj#IZoy49MtKR@>E6Kxys_vpz@UBRJ>Mx
z#i<G`&fUWRQ=pvw4Es0Ap{md<R08QedaHD@0Op-?pf23MSGv*0(Fdg!MgLLxI2Wz<
zN%0vBgCb@2dB{F1dE>$Sq7*NND84FAPs+`IQ)bdJC~vhAom-f%KBYsfKI(j0Q7%vu
zX+pJ7O+E+}Up0}^=!?|Xk?^}%b)((wC908*1ua$6=Ky=T8Zj0I{_3h;paRs1lpG6E
zV`z32tahWNT!>nUwjx%mYn=Fno)D_`^FqL3YAbr8Yt@c)5;;PhydK3mwdY(E8`Vsj
z#BWj;FM`9(YQ+g?plzzh1yGUd{x`7Ou6kJDcZWKdhLoM^)O}#?Qe~P4#;BVp@fNF=
zqLgHun%EcqcB{h@=>6NH{!EW#uWA^LNaNMe^-$fXdT#^Fel?oTWgbv{Dcf^UO{#}r
z5>&S+7#vc|3`TP$ss$GyOH%t6!qZ`OI~`*>qAuSL>ZtncDZ)-xC*?rpn0kQ{s>jvG
z?oc_Qe%MI)?~`g;clbS}HYy3#)9N1DGD6-V5>cF0&(}hv=hS0CusE;&)fMh9sQ=ah
z_C>W?bAYC(3us)wr23=*`?A_57GPJ@cJwx-swp!N=yi2&2T(WEnD!`cs#Sjn^ewg4
zatZHWn(Bw&w<9Uhmo}B}s55?teY(1z7BqL&JEaiJJ+)sWIJ~d+Sp<~_YH|AU$wRdS
z4Z#_zxf;+Osa<nm@L09`BHkzJK1zN*RZaC_m#Ow|3Ct|@w~h2xs4Hnh<eADPfa!d$
z4yV(gFVu>w0s2z?ONB5;t-KbXuT;YkFmu(UH89Lmt+cRsttyo8%U6Tx#~}sk8Ty*O
zQHSB51P}_<$&?Cxt1hHj);slTZ<xPV+b)LegZlbsMEFr{F#`sl)Nq;}6*<*I525;5
zZNCb_FKWxZu>Y!-DTRjmrp}>Ldfr+hWvAwAr|QDOM;rDLGGA@z7cduT!}8%`v9^;Q
z(-Q6UWEd>fX4CfMGHpP8K>KO0X)ABJ7T*Q&`fH16NgkkSJX8WTXID!0uF$Ro!hMj|
zWCpN<wYTd56QV5~0*jSeQ#zHhN(-bsz-p~Z4*Z5{BWU+6OuJtbe#13xK2X+ZpE`iK
zR%>j7d4%>CZ85LYIGTO0*UJA2unihVUyhC1UJ33uY2}=a@C-L=b4EdDi}smv`dhVG
zZK1PGOD_U5Qfo|;kL}u|x6q8zE>A`gtwmCjc!w5hKukNe8#D>urQNy-hcQ|RE#qRf
zbJ0+V)9!TxbGH_40m>e2?Hpk4)r!-!H(sm$jMjhqw1zxD4{BXJKqY7=Xb0zz7L^as
zM6DWay(DQIrBe=Ton`~(h{n(^<xwqa7toTmQICOkO#5{b+VHqme>2QaXuD}!=A_m?
z2(nXJ$@=hcT6?(}24}Rq+9=LyV{6j-@0@lu3BvPQK25JKXbY<#?u%N)RluZZ^$Giu
zR($}lFKabvXZ(uxH!T=bHJ)Z2SG5Dw+}E_TbWHua)*}e<-q6zV%XZ|d{J%l-mR2<x
zvNWwJegAH2-p%3fj&^Dmoxe`kD$u0ouIBJU@jx?dLfj9vBedGj&?@|f;)%9>0^C2<
zvdcr3scoQ<?U~jg2F&ML;&#}*&_2?~?UnXv1{~&U8;`&)PdnNJ6)n(O^oGMXT7<rL
zsEwe(;H?%xqn7iXw%QKzy|!crLj0s{pnbw3%{d$}pS5drhUSYFh+pRlU$v-;Q2D0K
z<Pe3oDUPzk^G%V5LHU@f(!0IDWRHR0g{IBrVeV@hG#>_wOocRgSZvxw!_^W~?me{H
zQd7Uzz+C1umHG^!pXtp4z$`b_q8}6Zo5Cr99bht*gMFaMy&uq4m|`~}&>#~-$=+bo
zkPH}vn0)I(Wu>YAZzxuoq@}Q1ZF>ACP(n>LDXAT1Qs@U8;ikwuw9^{XYd@H;H8tD?
zl?an_>Q5-wnWjX6yWX^-CPLg`dQV@Tji$Zy=4>)OrlsCy(^DTXx0r5H!hEag0BuTb
zGcBkM>`2pR%GYl<ZJ|SSQKr`nsA!XMG|YFH`tPK7#MGZoi0m>M=~2X(p4EXY)-=mG
z1ZAA*>^*?)H6e$B*TS@(2Hkz8r9I&Apy>)7uSzgQQcQ<TyJ^%+G~K4vWRmG{5;PB+
zI-Ldf5mQ1%$c~z}(H=sw>Ae+p$4sHKfqC5Y^fL@jm^M~}qm!mYN_w3#-F`$ln$xB+
z-C%#lbd5UHSyM&>6z5F!cA+?L>X!_Q3#M6=oW5v!`U!?9rekH{>5}OSZ3kU8HKX+D
z6;sJU082IX*^QRDY6|)pnAc2`=}^;klSgwDH%#Sm^j^4W%AXI-Tc#chX#SaIdKC$n
z+oloJmUm4PY2)~w=@s>>`=(FPaQMKqLjv=msmd^DW|(46p?G5II}4#bHLcP!xu$Jr
z&;@c$2KpICo~au#Uz@z?GnQ|<aSJE~CVMh4-<X11fGRY#dxL+yPIznb!@^s5XL?r=
zwRmsRD7Ey#w8{a)kER}!hWTWw^Eap>(<xeHeKswdj^c}HWiu3CO(Pyc_RXYzfO~Iq
zKN|JsoBf^e<YWH1BZ66Ac2Hh*p?MljW_`_X=`7bGb4p(n&c$X^Fsio1T#^pQEj16K
z6DrHhU1x*2++4RTVEoO;>H{>uyyy;EFVMVVEL2vQOH&sJGHZ0mDA+vccho7w{FM%v
ztu%M(i_lh?=TZh@wK<-SwT7B~8o^<hc@FJjg`1~N2Xl?nTsZ?4Yt3`Z04BoR_%x_>
z<}dgMV1)JNF9JX}m>-Tn+#AiF^n;L1=2JYV&F1%3*l#iC(+{w=n$OehZksu{3k)L7
zp{)^iwD~Q)w>!*H5ukROi)A3DUFL12pb}$#UjhcPW~WT!Yn-_Yt-N-dgJ_zw$Lybg
zs_iv%6%a+d`6&)d<1AnhkGS`npX4Bl1Ll4-Q$1+DNc*7)=Az1=4w<{qhF79FhZ3eq
z=9?`19yX7Rg832iP5P!DHAhe?EZO{zAHa^8bDWg3IBw3RH2n#)PbP#X&FznaI%U4S
z4KbZI-&qd(Gv<!8j67@3evE3LGjB0KcHSHjg&JNkH>(GOi{>ud;XcJYtPhx%%$3fA
zdD*-s7?@YgKjELR5K_$}1jKaJti?g|ntA*j8d|QK8?*uUhWWu#aBrHA(UF#0<`3s!
zm}b6DnS|Tsw{$Ea-JIY=6nD+d_XF*oIfl+N+&53y0J{g~uA$I;Xl_y)%nWnsbI^Qb
zZsdh(KQ<T968?$#EPXzon&094w~%Sh-hqFjL&!EC(RWMC*(Je!Ztl|_7B9?uJ_6>Y
zc{k1MbIeC5JMqd~Nr9(aa|usi=b3j`Moh2G%PWJ*H`jQAunWxNIZ$uS>GUyvXFf!O
z$b0ibYPApM*S-k*qxk`yHTYys!I?LwP-JdM+aI6JNzLK#i@ED^fPOW<8;06{Ggpg5
z;cY2R&9=bujeb11(8ACJ($~VL!fuh}PXmg@mK;CSeu-t`TA(bo3~mXPWtQ|2sFI&0
z+zOTDmbx#2;&1sk7AgT2D@|CPK^9M1R0dntCBQz!GGr?1yVBxChqhN)R+mAwS6kZA
zHgKrruNzPavyA@*QG{E1(+{iHSoYDty4Di-1!xhL)|8}JXQ}D~hwCk|&*5-`We}ZH
z*=YH54E%1gRH3%mZ1JL*>K3Qv`6_tYYH3NmWt+u^vh0zT+SQ@6-O_&}45KXOWk8Fz
zm|8<~hb5WL&h50Ahr`n@i*HBxjj@#20F_wFENZ7X%aJ0W?6%Acgo{0vao-T=Udv<J
zONqBs4n@5CEEQgYx!>YsWN;5yp3z~-gO&%>KN2hh*TDTD%ebKcO|)F}LTE{@n2uUJ
zHOP`J_RqjRW;sb+{<tNEj)I=B+@<N@Nz1s}KsjaU<_qZ4mMv}J>5OGaNq9JC`F#|?
z&Rd#QMHCk-?VU7uUbNJtv&|`%HoIVW$&yE_oGX^Kv@}h%bfgD+)$)cmy02Mk(61)1
zTS`#k@`j}py#Q&J-3bWvw#Ba=qPSyOQyt87OZ9RvxNDg{7@GGiw_BmP?psRGZ>=9#
zX4FUV&|+9k=YKOSD~BS|N0!Yz+&{K_ISz{_mbqC#dur+Z3fP$z4?2C4W%(3>V6rXu
zR{;B&Wist3KDU@@%zk01`UrJ-X?gexMULe@{jB<xrCta$b1kWVfy%S=eGP-xmJO6-
z&$rCYW%2&Kv-C6|n)j9i_u>A7CF&U>{b)(40-aBm?4N*EWbved;<F{4&Q^V~T%k$)
zS4$%8zI?L;k%6~$#(IP{-&%<_JbbLlryyHkJ(2;tg;u}EU@o?fqP6T2>&HYGEVXXM
z{KP3Nv#y|7sh>6b6GB{WeL+(Se`}3bU<O#%P?jRlTJ8uMDA+op8-fY3HlQr~N^2)N
zZMw>Of&+84^$hKFgj&DSNt`h2W!fhVw~k&8hik0jHDIo_u1<n1!g@Fh#X4)$Q(!tb
zS{u-I#3t((Be<Kb)}64}VoiMtYO7VjPosow*7puPgGlRuzfq^{*3XpBh_YHX!(p`b
zY97pYSj)TvbEh@p9V!uP{qGJm<E*=`f!b{qdqQQ8wfrA2*lX=ZqgK2%o<qy*b6QKC
zM!DbW-3I|5u(sF=)q~b`b)l1By+_0BA?sCN$P%p&H55tK>ra4v*qYfLF(q4zC4xF;
zjXQz{K5jkdjp$EUUrYjZ(uzGWya(2h>F|5nnoav~XRIS*AUkWlOmoBwR%a1yhF-M3
z#$J$+V(mw-+9j(s8_dhrB{Z47V(oAo7O7VE-e`-fR;4feUbEJw75R1R<SWp;VLkXB
z%$wFD+u`E2_5BbS+_Cn&0hM&?eA@54Yt5?$^Ly5+l&`&Sef%Ga2i6)+`t9{Yt71Y$
zGps4Jw0&fKV}swv)~Y<HC)TQe0w&9P+#SqpYXSZ6?3wlANf<o026{sF!nz;^*e|WC
zX`eL5nnmYhURjq?jwIL0d7`3u*11JszP6Sd2F!eGJu^@WtTi&|bN0qMWFoK&t&eGX
z_1?Oc(x4x#xpZjYqqR{_c=}{Lv=?Ya)@dS`pRE^Yn)1c^gg)k9ts!mU;+ys6c2GXH
zku-5!V2h#S0Sj&QD?sLJn?qmdMYg}_jM8G;YFYy<vE6(|zyDfln_34t%WRiuD&uGK
zro`!TTcxXD`rAZ0cDceftqDMbY%6vl{9v00O~gWMe@ZY|X}j7LeplIi>7?Uo+h*E?
z54A<?hf0`j?g^NO+f?egYiu)UCbZVJB@HU;ZIi!H{$+#hB<<sEwEai<mrb_LPaxcE
zYmtQqyT#UUCmMLGtud{<w%JzEI}&Njx&zSdwlN%9Cdw9Fh~|p6c}BzGF593(V8+;P
zJOwk>)`7kiakjBEYVEcSqz~pETXWiC-)sAI2*8~2wtD{}sC~8_8&I`_wzkV4Ot3Yh
zq|PCmO#e<rqD_7T`y^Z6^I#sf@suz<Vq2FF?4!2o<6w|%TSMo1j@gEcM{(SiAwcDX
z?Jc$XY1{p7KsjTpaTUc`TXkC0owMDp34iCEw$AfVUa)lxfbgO%fHntHYz1Wy+a=rD
z&Tx3yCeUWc72DAUV5Zut(Z4Kk-ByNvAAiFp#lgi*+sl_|l3TX%6+org;;JEv+cx(y
z(7a<)C@GU}tG^UrcWwXBDad=a_+Bu$Z*zJt1Iz=P>JAr=Y?Cbr=CLhq66~MY#?m_M
zsqNqj7-ri3O+k@m``H46Y+DT)`k&eE(I@t~t?vggb8PQ>qDfxaI@2;P*H(f?k38F{
zYEXG?yW#^X-`2e&Pzr4GG_=|qTQ6rIEDCKWqG0jX)~q;$?`$Eb5!-v)M5^H@+i}XI
z7um**L(6=&B`t*E7hB-pkbSiUbOZJ`TjN|{d)v321Im2+o|j<y*v<4@7uYxVL6sKT
zpQ(`f+OzvZbE(}t0Orf=nF@VY{On_Cfxg_nmHL&xU6}^^0Q(g)bb{>HC=(EDA4zHB
z5c`;#P+4j3n~x|~*~iexw%Tsq31+DMNMnG7+2@UgX1M)*RhX}_=hC8Zt=-lSDiL;;
zUYvFIS+o(h-o9%X<v%yrw<8fLY_vP+tl%cQmHsJ&&Gvt3;=09-V+eQw?Cr0D+GbCo
z?@6RRl2$<5?c4qW6=m;EXOyDti_asN9rmghA=_#Hln=XI_G7en6k}gW8zr&!wj1Cf
z&fc1iB<!~L?<C^=+hZS3$@abW0QzFa+arg=exJQ0O&RywYnfnwz`m~yEDqYAKR}%l
z>{n|*cF3Nx8eu2eTP#Gilk6V9qd07zLQAG2_K~#KI%>C716Z>C3}q~j+22u4_PG7r
z5I8zvPi_kp=Sh3^E?}RscU^~CoVJ&+f_uikqz|yq+Uqq0b<RF;I<U{%v&zB#f<1E<
z3@+OLIuBWjeH;xYm+WsNQQyn<lU;yv#s10%E>i7JB4KdV?yD!L>^`(ex^8d(3uHI!
zsUJ|>blSgC8ugZaX&4OC>{UvDd)w}efZ-i`^+TZ2?K^1@x@%9Tt@3;J%TJ(r-#(E(
z+YjvFAEENlesmM4412Rxi0P4iTnDH;wvV_6yC?Slx<KWreMBxWGws)YhAhkOPX^g`
zr-@FUys(GRS@)Or2>Pu`j(t6C!@sh>pM)aUezYuPdG_k9QM|TqOM;7hdkQ6?3hX87
zpiXb>bBY12(B60*T)ed(ISPmG?493(dT;k#hX(p!@4OAvM|-Csu=`}+8U(N+dw`R^
z;-Bp;w?gNOz1&=2f3@RZr^j1m7hj>i-i|mG4{yHX+68F(I4aOD8x}ZbD3C35y!3{h
zuS2F~>mo-D9<s%b&XiqT;+XmnC`%n%Xk=REIP(DJevS$45XExG^{UYHcck>B`DcLR
zBIO(c9bex<b%mn?wR(_aMgv3|?1-m-IwQnUtS*=<9WgXbS>@Pp9QLanTM0DOv5JQG
zFozEvLI`&(*#Uz!j^~tfU+Ylm$Vr4_BMmU?91CbiXuSjfgdW~I$4%_N;>B~+qk(3V
zqY0fQ+U(dG2x^OC0o8Y_;}@D`ZF7W9MLS12E^Gv~-QiEaE{Srip?qz$V?rwwI~>|2
znD2DFNQH}Cj@ZMXVjLL_5L&Eb!XkjhIqH6aY_}twLCfrM9Oy&;{?J~>5!!r>cX<7Y
zw%F%LDg^d^$HR&!4mdnhVSmsuWgT23II>HFI^@{B4)%$T)~`^}BuCOIU>|m@QGjy9
zQAlTHk2=iXP$WBo@5Anx!}l}{PC8ms&pqX+6@<`EJG#+~-g(AR>NX6|I>PCU+BwH8
z`k0@0RHl<F7aW=y*cTmb=E84^<1yt{FF8)k1NLP{YY%{4alD}UW2$4x9hhHrw4on3
zTyqR7h33BQh}#468;;V{yKXviXw<vqct{`kG)K*TP`T}N6l(;XJC2z%L8dz%F|fbu
z_=kQgcF)n<3)Fo_Dt&h!I7;Rq;D-+1ZlE$8*)!qrkz)^ymX948C1svC?w11CQ^#b=
zkz_hv4uPjEM}xtD&UWnb1m-ix9oi#*?hxn%><fp}ts4wqI`+}2v>Zp7jsSh-$P5RS
z>(C0Jn&%j^A5pw^tff8cd<R1()e0OFYQe=D$G`OBltPDrw!_~#%4|pR&XKzZ%=eBn
zHK6&yaf~K_9~~-vcRx9PtqPSQM>x&sKRXUPw<7#6j%OXA^VKnX6a0R2WPSzZ?RKBe
zUCwtqCn5?TH#b`BEO46=3YCR!bN9o}*X`64s4Q}m0->_l?bvYyy2LG>X4p&Jy3ud(
zmbvw#(`0^bF=;Sg?$)L*{QA39p$vL}+m3aVrVDiI-3i4CH!qq82Dz;|1hinc`@NtO
z;&zpO&biWU-)G2HxjmVPVzrxFf3#Dm+gO@!hq*2N1DfG(=}Xa+5pGwmA;NWTpFJR3
z@3x3~&<3}MbaL|l<LJ8MvaG(iX_jfbckjKIT9#TiY?!0WhNYRAX=Z6QoTV>I*@z%R
zmP{D}f}l(RSqdUsWC$WtmI|^J{C&^wuk$(gp7TBDUf$<E_nvd^LnwnM!QUW^QGXVV
z;S8q-^!|%rNazO@$ym4_UPLi;F97=tBl9!Zjb{8q5r`PZ9U<(-GTaV8F^(~UYL(e%
z8PmT&FP`xRoiq~|B@}2%WcW}X?Hps2Zj&W3c2bE<GDAbdKF<i*4ht!a_uhbqsf=aV
z=vrrAU~HnC*G0ynL`+*6<1$T6I^!=lkPOCa28d=d)>Doki!oJ(5oR-l&w*TGjL@MW
zhmp|&lFP86BzGRegCew-8B<fRl+SpX2QLa3ef0PjGWL%{vWW3LEl|ab8p@7YuP`oi
zpmCLv9f3bk3FAu&p_ei)P(0!qW7jE+sf?jq0`u1yF6rniXRx;drh-wp12B~gOEM&@
z80RR)Qq4%S0awE~NHtTnjCbgGa)Z%FD^nfga2fh;GOByP)iaPQ#&c(7yh7*JM#h03
z;7t=_i0*aYVyNh_)68h6Us(%d$7#5Bn^8hL`&LHdt1y3uk=Kd7HpY<xkaouMNI2TT
zaG_XKC*uHRi@F%*SD@F;_~kNOyURG643QqjDrZ>eWwg@%q>o`eKLXKy#uR;}X@Jpg
zgvLF_?RzkPpK)g=WF9c~_CRrv;Y#=Qh8WZIlOJWoEk)lLW7)e<A7{k*gPUN4W}$DA
zk<|yuM+}KCz#cOSmcrl^qeu&Gni2L26rM0vzYa%jn2FW~491q(`UhA$=0bPC*fS4$
zgL7bJ(82F0^KK9Hk1<VD#p=j>X#mbRG5=kKVLLMmUIlSs?x3P#SEgS9`rMd4R9NB8
ze40MM=fQNk4emHoO(hhb%$MJV$O&dDWo^8eT``n@@MfZz5ziP?<PS?e%)XZ(>dVx|
z!wWy=PD*S0GuM6%OQ)DGe*?(?rY{8v1DUn7;|yX>&@&RuJWX%45N5qUMtGW;)dUjC
zl)IoWjCu47z`~hJykS0qIYMuMNalY<RDU1ET($)48KzA+M5CG8&jK`t=`#RJvCIV=
zSc+rv=@#8t=9_U4iD$ls|6?&bfhnMKXCgC$t}dQqcG6!miP=I=OfvI%XE<}7`P&@W
zO<_vbqA``ZU=}1VFn3dk<|5M`8yf5EH0J!vKuc%Zm?4wF{FCY$GnvbNgil#afd%^6
zOx|K>Tw>b&2K^jnn;9ax%oUfQkjEU=!L`fGcWE=6&vZ_NhXqV;4{(Ldt6ZQIG0Q2s
zUd(KyTH`Cs@NXe<m6=R&acc=P`V9UCrOY|>)ro7&a>{;|F(X2uah<uI!t3SCKsr`c
zF#r7u1}m9A(N?pHdHVx2Rx@`|yr_m5y9<rA%rB^n>;}^~3w`y>&EBxozzm{LbR$zd
z59&?K2My@E#a!S7^UYS~=}l;DVY298ahrL9epju`{+&>~!z`yVwl-$uLHN|pR8w@m
zgSq1uD0VU(7Qs>%v*kVLbu(-8(RY`b)(Gq#=2vf{ua{X%l~8@m-`ye7&wMTwdIQY1
z^#HraY^Dmx`%G&y{b3(4-RUcYgUkh#@f%`(OegDy%(SO~Hq89tGr){6qo_P%lzHg_
z^v9SF!{FgKvzqb%6U>Dhfi}tf-2>bs=2!^ae$4!XGW}D`Mf9tlX1+>;c*69iBZLiW
zk_*n3wb4qI-gc}<dtuO?7084^2i9DQ1RP~O&V$`!tgUll$&vLmjlzlbuou|QEYCTB
zabamF&*REU4Tkq_tWTbSo;z#NUPyYdRyM-!aaOqvL_AqDsVe0J>xCkKd9gmE_lP%Z
zbRX?MPqMy5Bx1G?tM3$AeObqvf$hf%%Yu1-Rx_<^r&z-_7)$_bx*Z~ctQNY27sR@{
z5SD^jg_NfWVdc5N#A#Ob2)Izzu8U9)W38t1TR1B(4hj)0n<<DyvdZb9ielY=Nco2|
ztWiBoM6+se4P$l;%Y)Lqv8)ZWB*n3A(2@8o%X0;|cvg=LA_=Uq{Qym5^%B}SR`eDq
zB(b*B`97JoD-R;)S=*?>Cxvx3292q#VF@HJu%5TUI4`mmjX@-h<%dwTb#^A}ZAubk
zu|yP*&t}y$q4N@J4=qVKEagiexvahPSIcAFr49OJ))hLR=d*e!30lBP`5dH>mBoe^
zMXYb%fO;|O5Cw{^u+~&V?<(sc#gI!_D@5Q*Ss&YDX0EaJ((BV&#`<GD*z2t7b$}^n
z{Yn)t6)by-{8zF}f55dW)|~&)SIzp0YJY23xA`z%%Q{Gj-5ab{oMLC!v21Ihcav2}
z-(jg|rN0C02G*`XC^WJT&^fG$^_Cm@Zn5-PaIKm3wl6HSSXr+sp?I4mxdxb4R?_#F
zuRAQ(HYm2SQn$fwI}2d}Jb0|VbeimBjUIwX7waDFkh@tzI!)eXd3_Is9+uB8aJ{TQ
z=`h*H%B0X;KWp7QkO7uw3KZ_K%BghYK1)map$9B$&<NZZWHGy;F~n+RV}>5G_R`^S
zn6;}8pd+kRw0w-R^csv}j5SW@gK<_9Rr^k``pNA{Rt1%HJz~wIPYyh0?PLIZiWSre
zlxbF-A4Hz8)=<{RhHco3K3leVB~a|xo2`Q|Z_ln`gLPn^dJ&yR*-L4Iag6=Zx6p88
z2V}#N6T7kw=AGG`&EQ<v{3Q76%KldZ;>P~#2k5!8uTg;6gKbOaq2p}P4JdfB>!~F6
z1Ur|iX1&<)v~%-jZ=*BmN%q}7E6n?_d7WtWWp5k;=f`f)!-PLOo9aJLu?-ad31Vx*
zFp6Ndn3DP-?A=s`cA7nMAC88yE9glLV{f3^-EcO8$}A$-Q&dzP$$pVm`6#xGFwd~d
zqJR?3zVr<AV%QExDE|=4cB3Of9J`sy=gzWI>R=+CeVFn*3GBV}ZIVQ`C#8qavCm!y
zOcMJC24Ireb7=p0p505!YzlkjN%)(}{>2I80{g{WC|qPe+XD48b`u>>(%GB#p)Z52
zSP7EJ{tHKO>+CFc-^VbY&35v@-~JMNPz3B8_MsWza@l>4;Y=P|_6x{m_VO=aDW82c
z4qg<ne?0=dLUwT>(2Cf9P+Yv2{o>oOdxhPaioUDtq7&ds*yX$E!DHip;o-q!x0b@~
zGPXDtde-agC<^(Pv-chYb_M$*ii}mVT^7TODs~uMG_PiBDQ{WB7Aat&mVF=qeK*+u
zRzjhUeT5dUo9v|&460{;lmmke>^CX?*~pHhY+e(aw-pv{vFl2q(9HhtJk(p*k|>zJ
zZDnUI2iwY?cnGKNuorg&t&M$wYSG)-UdhntU^iHS-N|k%L0=d9*Ucc^Z0~F6yUUi-
zF`<W@PucihcK8tV`q)Vn6zyj}PsiQ?wwDE#?y>c8=)2F>I)Hn?)>1}jkZr{Wc<|t{
zJr={^hwM*jXFtroL&5qH_UDv9A7xiQ4HIMRr$2&+<80S&VRwS<N@WL=?C0Nr!XtLf
zv+!w}eRK=BC+zDKMYZ7^5Q5lp)?I|U9jD+EcxcaYr?bBUCyqYhbCmO*mBMAmIGU#c
z>d49d9j#8B1uMZhb1JD4(S@_&3PfBvFAl??8^??4z}z{nvLWKZIYN=C<D8Xm!-Oa2
zc`E!o!TD_+On7n9-^F;nIpMS;Im!7T7@QAh`a>xAa(<tKQTuVcHqiUepR<HEuBSLN
zXfqtZ`AC3a2Xcy%AQQyd{X9T}Iipn95yII(IfB!iC#{eS<&1v-y)aH`F;K!eKMufB
z1jk5~Uy+=&KS826+m#SG!)b_ydNgN;86<||LzQN+oHtpt|BU0j^e3D;%dyb170=o6
zEIJc79(2}9<Wx{Z>>TGes@F^6?4SbMWX_&{VCg((2NkNOaC)6EPpO;~x;uY?^Yc;k
zUF1x^gDFYlJVWW$bdK>5z%n@N(m^sg;~#=#aefJ;{6jWp-D<FxIIZ2#$l+Y2qeL!e
zoMMJ~oLovXUFP`4!csnGLlrzM;56=ri9(LO5Pd})l`}?I%xS0N;}y;;F978#=Ti$%
zN;n1eFki~4_C(_~&dLrLD&xeQ2H16uKMmJf&XI)!rh+q&37JaH0Z(vMoOREjvzl{n
z3iDONS$qh6wH$o}6mM`0$6=|C<K+Nylhe5dq@L4C>s$lpV|qt5a<2FQrHPYK1M{~y
z&zu2RGspNXd}`%<m;f*CaKu^+qRq<5K8((G&eq2;(ZShy2a27XnYS_PU7W#YXmoQ%
zJfU%y^FF;sdpN?U;ZrZ?_f~Lyobn&xQ$J_O7i54llZyZDao$=C_4}NaZGe8jY5E3z
zgPi$vr*nw2j4lv7<fK!KW0+$#XJht8IE(1FGs;<;2r|YgWx$zn&SR<xnBc5#2btuE
zD6;hk|1A}Lk2!r5X`SLMa)rTZP8)rb=m}?nUeq?+CsYe$%hghX)s8#&S$JX3-9SeH
z2kzH1;Kfny1v-u$<7Qat5~(A%(;ux)+`gRvb>_+`so}!?or-8(xj*d(s2leR9d_Kg
z>-DhY!F`GfqK<Rho`VTb?kE3%oZy;11M%VpQ&hy8TQ~<`C%MaQ0PVy5=zDO!+*uTe
z_v2pd1g1aND5Ue>DK7UQGy=FkcK|ey`wCUq1#xW-LME8|8=aX#xDl!F=`?q@3JRgz
z9h9pM<G!;8ec{|AyJ0titEP}gB)4H9xG3&STGr2SV-903qPfnc0E^-NO{-Qccj8Zw
zIBuaG#Xrw-&3{8Qp1W)ZuoJk&bc-XA8%?!S=eU9ma6gHAF&d!B+~2mK@jQ2A1fVJ0
zuc+86m0Rk8IlRENv;y=ZcWpV;)3}-S=u79atH5P&ecRBN$@MG-$>PR7Kw~yH61POH
zvoCRj@ExGpIo!AI!%{Byz8<5<=Q{GBU%)k7h2MqTTDk>Q#0@QnNHKS*JDj<~jifyI
zRqk$j?n}5V1H35Zo-2jqHSX_6;b9rKk`l?+xofCYvz+^VGZZSg&rw>dl6y^pMr##U
zNEy;<?$rv|t>Fq@1gYi9=n=oc-RpvxspH;rhR99s!F*uXb6;Hn#Rl#XiVHMy%i5vP
z#I64S=8|hm>qRs7Y1+`VaIe!D?KamX4U(<g2NwZ$hkIcoM&HJ@qr6nRmAjMb<~q3I
zPcgJkt{)w_y0}B<VWOM+4VACn<?<+v*uxDj0O{pkp^$JNccKfVpPR!18Q@-^zI)u6
zPT=ly3v&VXfSX5`3<kMr>tSh#8#DoD9&*D<fjP|GJOvL&xYl?o#2n?`LJi~WF|Or0
zoEhiFll}zPhNg6qdv6c=9&y<+{6!vfW%DtLDemUi!A*0uufX6F?#i`jwBf1g)NRXC
zAB2J(?<C#5x95FBr)~#c1npao^4N6A<{0nPLnt`%=2&U>;KaMu1NWVI1&7h<!b_lX
zL08_vJaBG2&Clp_=M_c3pa)M|3AE!pHVZJGyo$Hs=m}oN7qIKav;7ew-n^p2=sU^V
zLZwJPJUdF``SNyTViNp#V-yVX=dHGb!YQ8Lv$V4a;61Yxih;Zjc7Y4xb*}*l=8aM$
zFNF6kr7BMI+(W>H@)GD>5yoqBgHMsX<CKeu;<?j4{|xW9NN~}-{{rE546lMR^|3rp
zA)JZhjlK?%v%J>|&==2pz=cl<Jj(_;|0VJ&UBRB?xg3E^5>LJnz9sWk6vN<oo(FlF
z!W--dN#%(s4RL|Ds~<2Ic`ZB8n8tfk2WQfG^(`P7yoXeplgaaF1Xvbt|4%^4=6y%G
zm`l81HuQ3M%GDsbyl4&8U+3}e*I`aB^VZUbxAJ*mG>HYgG)h$z^1gG!n2LB>cMPVO
z_X9-<uJBfU0TWkw5yjw2c=LjQUCO&N3*0r{4qCO!crVaHd7amI6@RUA9y<;S6};Va
zVX%_-<6iVt@#aunueF+YfYMtvyeuwE)bie;c<~M10KG=*c(-byc$2q)UYzy3Ih5XN
z;0;r}w~@DC2}l!f5gjFN@j4qpnt64!Z*Af2rS#Tq-Wm!CxAN4Kskp;CN%yqcc+7{e
z+s^xxis3q}y!rrG>f}Y!hb_8z4tGJid0*1)tGhg>5a{>t4t#>4_44XfnC?E_I(pai
z^YUm1H^5^^!QJDX%Z12&o*f10AMn0?0VspKx9Qb7#9Q|-EIs6X&IH&n&r=67!rMl9
z&QYGVfR3SKyzP`29_QJ94sL=s!viprym)u`{fNh~#h>dj@4h2Mrg(E!V-(Z8xi&EW
zg!c<&9BlZ<X@YI}_j6&;j$c5lhduv?jqvFhzm%exj{Jpm0CVF1<pDis{tl{-aN(C)
z_XEw9-%RlrH-7sPD7y3C3`eI2e{dWc$N6Vzo;~@4v@o9FPtu{%i~mYD`n>riboM{V
zPdWv+efUL281&`Oc>ySX{7m}E`tz?lLj4rqpPt(QK9^ROK>pmduouMt@(`W>g85F_
zAR+wxD400Se=!9bq5Q>5p%KP!qsuno{GT^MBZBWl;h#wUzf?~W#Sf-M><s@btsc>Q
zZZ;HR_?u}j9?Rbr183s+3%-WPS^fZ3*u?Yweudi!{Cza(iF}ilzCU@6ucuRY62GJf
zgGuJU{TED}=a*jrN#S#jz?oEjz!8XC;P0lW=0*Nc9=J6A>AwJz&UbthA{l%h{YW$U
z<y~+li~q|gEM@c4M$veQU*7?+9R7a#!{qY4DAk?EpEXAHXP5bTU%_rZe+w;l1^iDa
zb63beM5pc|zU>U474v_10!vr;eZK<cDnE(p$V&LbZ$qS%pFyv)Yy9`=5ijGn>;=ko
z{%cgOP|oLypjW})=mdk6{A@bJR`Gvb1CeU}UJ9gJYxw)<l6ft^_9<xG;J4E}*YQ82
zaMw-#skhKq&-b8|K?8pVg}WO0H|dnq#P8C8yT#X1xT~2Tsl|9(__}t0-sZ>9X`z+x
zR1NM9f6+{cwDA|xGt$my(xt!-{>wBoomPJK6)4{2du~8$55M{tNH5=J2#tOGHmbYn
z=P#yX#sI(QYxLdY3#p##K7a9Sh&<p2e}f4c<gfb~+z|h8G87*23#%bA%s;pu9**!G
zs2*gLUr+b<#`rVnw>Hji@rU^dzO|I{*^~V5DU9=ozv*+xJmzQ77HWzg6#$uO{#}Y}
zJ>icX1DcIsPcMkApsgA{*$ITlFeZD!M<2sA2f=^O0sE+6@e~w}3G%77%u#S{14Ntz
zlO-U|0?{Y1=OTEA-Z8F%8`h)n+fA_kJ)pS@zG;AlhhPDnx{nL)OCaMZXrx5T34xL#
zk6wbg*=Y0@T&e}yNkO9s&iDv?Y5VFc_>m&vegY}&)BOeS(W-Sy@FgV$0|Yrfa4k?U
z_ZVCY5=g#=*<eB4M#}$%2<$Il^rr<o=x`V+Kw1nBo?t(vu)+n_*I^<;&=m_3DfmnU
z#VA20JymA}4le;aS}^M*%*P12H$g8}u)Gjn#0kbKVg9V(?M+aK7dYDkIze!ip3OwT
zooaCB1oz*f`m-d#zZ6eQ7PNIi^t>Q&2JEH?%wr&_f_jR$ToCYrVd<h^0~40g1Xb4|
znJ##|7J3<inKc+%reG<3x+F``OtG14!I@W}cS-O&C2eyAf6{n!1sn?5=L!C$W$v<|
z47DxR+4%xBRaF-VmVSrULP41Xz7+|q^r@|4!6JINt_V_Yqp?&l(uBrqg0FFLX?B@F
z<AuiSf*J|TmkZvrLcKy@dmUV*pyxM?zDn@MJCLjv%=d;~jX-`G3blg3Zg_D+Ab$rQ
zTI&RglQ3~pprMDlUho!OBxn${(XO&lV9Z5dli=-eXxtKn(m}UbkU~#Ii$MD|OxzZ1
zqwspGz%(D^j-Y~%fwl=gn*dn5Am<w>bO>(J=D$<0{X_J130D3JXSxN?(x~rR1z*v2
zvPW>X2pYYD-BjM#Cs_U>H2MYIJUBccaG~()J;B~(=({htNeBA}g2-IJ3<|oZp*JLG
z2nWhT!9^)d3=8-#qj5x#wi_l!1zA)|G$u&+79!&U+!VosC-A%tkx7B|d)i??66~G?
z+GD}XZ(!I{g3|Y4cUllm5yU3~@tbJ05x!>+4O`)b7%12Y$H(BIy|ACIU^@sO(e=Tj
zLVVyK51ufcQr3>b7bvaeB%D40yUxOG>p)zD<5_5Q6&6rZ!A&?|bpY!wTt=^U525R;
zXgw~B&I9oj9-su=3E?RHVZDU!{0HJK?4@A)N#O$eHmr~E(@>cA75<(Fbw6QDGdO>t
z=`Nf(B^>F)bOi{zsFWyBnBW1hAmQyvaKXZ5^nIQX;fWF}U``8Dz61#sK0gVKFk$Qr
zSPB>F5-^Gg;ht1@7%BYi8B9==aA_F&&InI!L|?RUnH(fWXrirktZ<lzzIfp+s#r-7
zzDRMkMB!-)-<%U}rIcurFp4g+B@6doh2(i*>@vE4lp=hZDj8FSC|bg!CcH|UkBh<x
zdYz>S<!dk(=|U4Fxif^hRNj#({Bt`*vV@5$j44}~{s%xW34=I5$q{DJZY5Xv!_Uym
z6AsfB=CaVg1<?7zVyfOL5Psnfu29(5MDdp*;jWEfi-mtvj{b`9mlxpaRpBSC04)&)
z^}<rAa0SJ;uL(ce3ln9+)yYt}F03wurE=l6>j13~ez+ZamBIiDm{tk*tOltT-n)s$
z8sU-W;Y_V?69eRi@U0T))d{=b$0S&93a{^i-Fo3i?l9OO47v-0jlym!m1z=&({~DQ
z39l_cU$d}w6(n1PEBZlh3$@>Zv<e^10oonmw-=$%CTx2V9<~c}4nUzp=(`yPJB5PP
z@V85NEf$057Cxqf!Cj#T?Lm61!dg0~_X>^au+%3^Z-QvQ(BumJ0pZq3xOh)^*a+^v
z@Yg1YJP@YL2RA63aSp>C63$-%g@;0aTJwj6w>Lp#MEEByNu$D6FIXBAK3fivabYrD
z3Y-w)uY?CrIFGU?kA&9uDGvHrxM&z&ObLI>!6>GM0{Rxt6JZ&pIBZ0AjUcw7!?a_y
z6M64}Pxhk2bpO^tbjJbQQPIa@4Eva<h1PsWQRHVJPNMU)S~`n_R3hUd;?NC4SJ5x@
zBJdC$?ZhCCi(a!*Nua0b6vfa^h;AC7=p}lK_D<fSUnz!mQj~NI8a^UcH;AvOc{^bI
zMEmH-<uA(EiV>a??WNp)fG8;feSsp*&j1S&&A$x~gGC?HcdkQ3IX{6rE!syRv`|s*
z2AB;KJ^ek!U&2M|&%j2AtQVjdDGH;bc$BD+g4bt6XK0@hEn3uuz8Fyu1+Qa8*H;5A
zPBcnu=UI`N@&NH7iyKf9L>uqHwM0=33;v!HZO?#0k|>C7&?JjK$OYzk5&gH<*(oAb
zG`;^)MSOQ)Ul5(9W$U8ovoByiO%%8Qpy{GdnqeYC)JtWvnWD&UU}uT$-a=!x=nE=%
zyCgbJp}!o_b8BEJS7dnr^*mAWDl}det$iMP`J!dFK?+2UAEU8Q6hJ$-BGFou)ZzOR
zqGxh3&sRkAcLMaP=oMO!OGI-W;9{vra1<KXL|^;^u1s{9g1Og4XXv9p<sy5^yj6&L
zo1j-I5>VKvN_2@{)YYOdj=|9y(E!yc)QZl{gUAh0rZYt9L|0@me^Ye$8;DrzMME>u
z*&zC-2jguNJ@p~5n?$!Mf`3b7q`QI5qRn9tX%Pv21b17sbOnapDw;P5{W};8Tx%0e
z(HXj3w5S>C9irvSVWLy?!8wR@iRMulrd!nSjG4JBT1Nr39?{x)5b3pw;#8376S2NW
zYrm+3_W1*%iU#=oKy-jIN`s=0o}h6^^fJxtLs9<}(1t}^s(Kg^IYdBxR1`ziY-6HC
zsy`bSrBT3iLX=E<%t_H1+S)!6z4s*yJ{JAd12QFAyayJhMb-m5K%a<sA3?@Oyoo}8
zw&I@|7=@kK`!tBX_+~9&9K^jBpm<dL5p9o-iC2_E!BK2S*BP9|A_`19i~nmupNn`m
zg?3%VS13l}CSFC?tKG$2blmn3Z;OH3$HkuXZ&5tOg;x4f+X?Ye+IV`2oj9=ME%tc_
zXeY&K|3Sk?%%z3KSFE7|GC%S2wD0v7TMg(tCB}zc@ZgE(jX*C@ETCsQNc;^ADOkLo
z2NEJaOpE4ev6hzLP;u&e;KIbSmZL9ReD(s}e~%DvrxSgocqWxgM2SW8qCX?{qMcu~
zcwQegV#KRyOtIp^N;n!PKDQAbo)!1gTPa?AkUn>nAWoyuY@+yU`azr%J5j13Nt{hD
z_+;@Fs`oiB4ypr55ig=dWvck#Jc_?u5a&{X-$n8E5a_3g?Gj)qT|7-O!wj+21TQkh
zD=1i>CC=XmOWERcl-{}|wxKHh9P#HAJ<1i^(U~?+%&SJ<WwG)nSjrbS=R>_foVpF;
zEEInl0_Y;~4}lOV7JvM~3_O2V#4Emr%vJFbD$FPmcT*)|sW|;ZU|$oD+(ciQI3xz#
zb@A~(VWM2T(*l?ZamE^uYVr4n;C798_gomP6<=`0%-#@NBA{0%4x%INP4R-?&{r>B
zBZOpwc#IFyD8549II=d0Xa5G7TjESAA8!`VqRUAw;_oQ#dRwfc!s}M?11i<NBYsB<
z>^AY?|KFt)FMS7n9pa0$G<1r0(4D9*@uCaR>lSy=`|GaQNHO;w@jTik^@_{=@#pOm
zFR(#hznDiG-2tmOsukYc6Tcn+?EB(X_Rx4BZvPQp42nw&ATuPsz8-xK#e3cd85W!9
zbv7anAooYbrmuiDCN9_t>~V266;Muym;Z<HPKp_y0{W5oC`C~pi=A{(m=eE338iUq
zK7|#Yh^+^H1DcKG7IHzeZ6#y0L$H(lyB@?|a+{Kw4w59gyLMFa+-8_RCdqjj3XYN~
zsuOaO{JS3>I!nA0f#xF7_P~;>#BvFJZj$qv;M^t8zK=c+$qPv^e_WD7r)^Kk7xdmd
zA-QDT1~f0p+!APbOZMe}J1P0+5GKJ#!hZ`s`AQB_uFX$UO3${xWZk>yJ0*GF5&8j=
z8B`M&C~5s1eL<3SYrzFe2JB%eL^5+TBu`7GsMaJ@5_}h2nB>cNOi8$;l0wlD64?UE
z|3yl28zB=VSwcaQGm-<eHIJ6e|9?0|@+Li1v64gdiHbPMi_yS7E7?p(ka)=)y2zR!
z@umkhQL>nh(&r>U{0)&LiF+3Mk|n1p?360W%7Xd@$!m1M@uDR57D$>zG>`HR>5>|X
z@McKZs{oTJnMWbGEJ>?3oXM6vw-n@(q_Q6*M`ENRkz9#uD$M6e3PYiASrSeW-h9b7
z=P;H6Ns9oaP|`*rfFjACFT#sr$xD>py&|chFv?X)1QVo0qQH$5>+Dj=B&AlaNe1bZ
zQzq$b0(V`K`#luPC2t*sYZa33<lrhL3>I9glDtAk(`v~QDpRVF_*12Jtwc?6n;R1A
zn=oG|$)=zDP00^`Vf6Kq^DV$^ka*C$u~Fhpv6&``lAb2(ElEW@XtM<W=N%88B<>>&
z^tR-lFVI>g->nCCN0LQh{Wi%_XMna#@;UISLy}km(kV&%7<yfji86?EOTOL%?7NZ{
z%AWK{mJUIrSHhvNQ=jB@I`i~PtQ0mHknlbP*gdPnmTI5wOD6BY(gR5}J?VpzBr35P
zl9W@Z=Ak6s4%ovIxdw_Ol7*x&Dp4n+Z%o2QCVTd{WGD^T6Ov^+K_(?Lf<Ych#8i^^
zSTaQSmZl^g6g!)inBK&2pGc<5fnp=I9`FXJt+b#HXm-*kltr<Z7BiseAa$cK>QQM?
zI><3;^Gg_vqx83{AWqU$suysU?w$mwi<D&x&Q<!*0zEhB=qwm?mwJ2*Fb`=SokWgH
z|DwEyr*vg7L{3QUcf-7w^cyR^TfL==e}+@O(#;Ow{G?U1_WDa}sEX&5^p9GY2$1ff
zG-9B1dm{9Mq%&!68Z6!QI_!o>pH*NGr=`0n85t^ldjJN*q|eL&Sh)0+PJl&7eQAM-
zl#bC+JWBfN>i|0=wSHm6(4wXG6ts(xI#4t;R=PbHGI7$fUcj7{hJ6PTFKyTYXA-0x
zKLI9D`bG>U;heOU_EkyJ<tu@bEd7<%&hyfXR0NwM<<R}1ROyFwm+^wM-42)+r6&4r
zdYaTB9*ybJ19NEqnIVmn0y|UcF$tI~>9!|O%$BxNIP#KIN5Rb;=^|>(mCpDRih0tE
zUZ7o;7ErNpzBKC%I8z{Hy$06`r9%|DE0VhPz*4caYBRViQsHihT$M&7z)*?wB!z!U
zrP)7H{^6SRG{wToq_e10`?_@g7R*<<G~@)FsgPbe027tcQp$-`Nw3q2SS_{gf=G>Y
z{W5r1EB!POKHZRRcpiOq(j1Bm-^5=Mef84sXrIs^bvh5bjneb4z(SLB3sqI#lKRa?
zqqSMerDIBq)Q_T*x22y^1hG}BqU8D=>9)T?+NAcBT4|Sxv{3Aj9;C;=Q>r$?V3#zd
z9ev$W+g>!@l}7FZ>5(p^16Z%Lg|;_+(ht4`biZ`ZRyZ>t-BX0Vd(x~=p?=>g&81k$
z18HRjWCo?JyU;o$-DC@xhth!|m>-sQ(HnY1`aW$%#-$S4XG}=HsRx;qZWN*Mk+g@3
zTOLc5bmE(mzH<~lO-u3i#G@u%bpymkW<#MyTUk^%^z3A5zW~!-W|h)v>md6v6$X#W
zzKnuz$7F_f{DB;0e@;WgNmlm%M@=?|0-r9jgOtE?mBlCk<0jigFE@8tKnN5(WXvrP
zIWFr-2l14Zb;64ivY&ln$xD_{fN^@u4lY68Ntu*hrarRh|9^kkS9XWC4SurCIRN#S
zWfr0Hlq`#O1_81Y6dn(hefK9sf@B}XqAytHNd-|Mva?hKbXvBDs>(uT`Bc;vCfiX7
zy>Qv*&wz`N@fHI!QueMpxF}go62Q*LA__sGWiNbTg?@}IuOIHm$_D8t5GU)p2JWnk
zMGIBDEI%KO39`Bb3^Y-8i#GA+WQ$V(nk1WC4w5X3cp0;HUiJ%pc`QXXK>4gxnQtrn
zy&&6KfyRrn%m2csG}#_D)YD~u&~Yq7_OglUUovH(d(fFBbNK>_*|LBUbY7APEg(6v
z$79gQm7P;#_VQ%iX)t(M_SQ;Z=gS6ez^4LP_EYe%P<D6~#!@8v_-T-0*$))_x+06t
z1?E-R1Vx=oWb6YVrLs*)z`Q1t+0yr4%4BzFpK@JRnE}vp*|+p}s*w3mqO($_&jebP
zY~4>ltCr1N0mT~G=tj6!E89dHu^Y0eTM(&}jZuNaO_}du_|zyXrMGvJ%<peV-jdnT
zvA0>a{~r2UWKP}~?rquq+u*FNvR`O0cVxNW!C;$AM$28htUU@|bjS){g-oX`kQTo#
z*;ab+x@A!`rFUh|rU0}@mc12?y|VEDDD=sg>6nXt*(+S249Kch!?k;|uQlkqFRT9*
zb|1*T_zxn3veQhc4_Rf=biQ~ftE5B!ux#igI!9#rv%rnY(mLVOn5>P~^>JC|D*Txz
zWY#4Bos{YJ1N4z>HSHQ6%leXFa7yNc7~1S<*{kW`p2#{*!-S1|V?XTL%0;u#XD44p
zm9h5n^LapVkXu(t0CQCCO|Q{o@{mCgNBO>15GQ#!MPr=huO>jmMcz(<CRe%Y6}aXm
zPg)DkUH&WmWIg1elu$k{KQtQ#J>@@8Z1jZuAKK=4$ydi?5Z>|uF~~{zC5p%U$ld-$
zpRe4<N*6u+<WqF-!e3s~0JKx`H|Z}LApex&pMmmmx^WaFFPH^`!Scs+2_!_WUJiq&
z<!@9#Bvc+s%SM<yY8YI&Jd{?g2zd(SNh9SS#K3NpT=fCQaz;KvML^N=74+G|7<tfk
zdj4YNGxX?;liP{`b5_2E5|;6Dds?j%<Y!x8DN*kAF1T~@XGhVOB;RBQXOiWQj=<7+
z`JAW0rO5Zvy`@z7m4i^YAm5=v<3;(6&)`Lx{80$JNSA;91`K7$)9S!w%iq~S-`~9?
ze~|^49Qm@fa4J_`nE}N-`CuhrF3Z2W4w5fVq*Qx>e7i0DEtGGk_h*qjcR$dI<-zou
zyCT;sL9WW5T@O+sZ=_i-mAgryeobCn4a_omI~RJ_<qIh|QZBbabkI7xLLOLyF;&W+
zb%lv4`IZDYTrKzHK(U5$1bEcs`yNB%hWsxoV5yV0(ZYID-cPUndinmN&})#VQEIbM
zer+Qpo8<TkEFL`hr&P+`EMIvReJ%1*KGbi^)4U+kD&O=8M67q@KmPx#AM!q0ecI*g
zCqO#n_eNl%Q=UV?*e<z0onpJ?%krUdSN;m^q<Z8((yG-fx2I3F^vS=XV#R*>HM%i0
zApiO=Ou{|6APRQx%VpIV_5=AR6qg&6&!o-pkUZZL&=0Nhr)g;!mY4W}9g%;X18!7)
zXB;qNa{C`Z#^v(Y&^I9u^Z_?1XQTr3kvxVf>L1G|o&nmF+>^f5H!XjO0<}-%Hjgku
z8^up6;I^&8R0i{Qia(zQXRlbg3Y>$Y=>>RrRAFVtf*w;``v2xq@is-xoD^vk5O-Fb
zE`$je#k({mu8N9Zpy;M(r7eZKBD^2OL$O2$k>iTm*P-XBP$6|T`-I||Khfu<IC&GC
zw<3oPk&}vNwgJUQAvuLv^Hn_a94z=L-nVvOO#X_Hhj93mqC5?)0gA8oKrv8pm#(se
zD4rx?)=w*1BcK?nxFJPfm?DizOv4o+kI)yPSS^BHq~huIn1m?Bv3Z!oGm29_5Q$bC
zN{59Q#g5O>7pus!!cd$dz7X75#VghH{KYG-J^@KkRMECBQISZ;*K>;80l*|F!sz^$
ztXTaXV9qN-DE^Y7xI}@7R7EajUoI#%Pz3OzB9%_-X^P}>V5cio#c(Y{!4g6tQ!yk1
zbe3ZB9t>qGZ0J05N%317z5j9)yz_v`RcxkUd!Aw^<u)!WBy{S|R|MF@Zh^w@5%dcc
zoO4htQgDJGQmk;>0<<fNXK2rLRdMeB@e>7i9rQ{SIkcO+rda9>^JNO#D^R$u*gzhZ
zD}JF$rV53iY6hOaN=4;mXjCb-*}(5=MQAlTYZM2L!I@gc;V8IvLy<=rp*qFy)39_?
zk<$l}dWHTijIcqWe+Hn9ip><0ZBo2a1@4w&C7rsP6~(kAZ&5t?0noP<o^<MNRjj9X
z@*Tw*%7<Co6bE)dqg@d=4;mec-u1BCsj#D(o-V}+TDH0syF#IVSCP;PjUGij<w<)L
zXFr8PpQ44PyI=9~E5II5ETv=MJ;hsVF<ti+9#=654;1x(pm9)9v>#+hvE>Q+9x8gX
z;Qg>w@$r0^7*Ra00U1@?EC$+`qJzpK#}yCh$2Ot(q8p8qit=ya(<23o4rh-QpVfg(
zDLTT?XrpYTkcF-CxliGmo${UsOxP>;Q1Hq@$$SXOqe>wiMvp0{m%y&0GQArLPD*PL
z9ZZ~+n{A-zqP%qnUbrfc*TB4+vYiIwuKb<~ianHDD7SH3=^)1Jc`E<@7J4U?VL_1e
zQl`^d<gGkTA;*(S4=OV8QK~5d;j8@i6QKAhkHmoZEA<p6JEeT(cZ@7R8EkzU8iC6G
zAK*=p(mx3>!OB1nbcQJNC@FYa`NCq1K2-THow~!6ho}f4T)BdtkqG5Z@-R~Ayc9k~
zDUU6K<QZlB31CJmxs+duQNBeR$5>?<T?dL&>S%v|R#}&hzIdhT4jm8@ls71)lc+3H
zV=(8G&NQV-%FJ(|n5?v`1@?L62VbEtMOozolByi%!HWyZ7x>V-s7yTr$uy-0y+zZN
zWvhXmq0}7)N~Usa02H#6qm%{7Rvz5}^Ouxc=A$u3`P~k>f19h^b{;T!N>LIzFDtLp
zFDYNSyAc`%%DM623YBj3X__Ks2Ys%iSeZs^$`$3P4Y;dH*E0MmN|f(Lfh$$!eFU&;
z%Jo8kl_}dL7~pl~Uz^cbuDn4Zr3&Rd0~9KiIgxb!t5P~PK&D#xof<MV%5Oe{Vy!ZY
z3$z=`YaEQePH9KK;G4>xVmMQ;^mq;m4a&VWP-s*xEdpATGERraTS|L+3pXndK7hY1
zN=q90ZY$^91WKE-l#aCR$~m-Y=}?wDgu1m;$>L+ax|Elws=8b0^bKV0Dy>K0X^(P}
zY8QKzCrY8;rwqLcjeg}B?3-r~C_k@7-#uk4MQZLV7rg<I2g-ePn`ltEa1A7fl>fHD
zi-*cMIvEcuo#`^+h%zY>_C}TKV?oBON)LPZJ+9n9k*x{k(;d*5RJz{+%p>L12*^BE
z&Y{w}DdoFM;Ni6L+Bd*{qTHMYNgLJQ=^(bM^Nzr_Qzh0w!CrOo18@#1RP5lvQx($1
z%44b@gurxE9ij?;C)K`I^f{}n&(pHyqB6~a`>rZ6ox0sr4m@<at3IJ!hleVv79z)0
zUoHaiRH0}P51wk<G<@<>m3v|myj4EO0D4k&H5<f7<wzG%eO0CZ0@F{`R0#!t)xuw)
zeoDon)h<9ahq4KQs$wf04ue!2+OY<!j#a^6h{{0ci_@x_6KD)o31M+|n5vILVd1K!
zv=@j_&81U!q^g&q-BGHEkI{HW^?De5idMx%K{7_QdK@HHWw-_lajJL60DV^V?o*hc
zc-1mmG!s;AC#>j9R6T1C{d20y72uLoGt1$3vWiV{_4BIl>EGw2s9tk{Mye`%H=Mbk
zT1(-si>iYO08LXJp`$>$%1Y&68LFp7ppdER7zCH4@>>KCvsJs>!Cg`{C!#M$mADzM
z<*H73&BODTr#d?WFqc&YO8`@-I_rmF7pcsD!bGuZTLH)w)o>UzuB!Bupea#Rl>)R>
z6}KE{*Hpfg054P3is9OIRSMPMma8^W^+1IxN(J>w6|)sHQ>D6C4-3_*dGrgcQSC+W
z*gCsbwZ|1OH&i#D0J~20?*WjTs<+lbre5Xy7-$WuPfCE+s0yRVR+FlfzEp8b_4{j>
zpk~#u0(~ti3#IdJs}c{RuT^!Ae!zEBQ!RjQQ@vl0iEUSH-h##sRn6yU>{Latp>FL`
zo&F89TQ#3{m3LL!XxrVR`lk-0SM>`mo_(tM!@%xWo!gAY0o8hnI^R>hz7Ve6SA7=`
zv<Ipqv{M~aS?JX~q*_IFqYqW?^oku;*_?uhBPz#AfQ_nh>2Nlt@}UjUxK))&TjU8<
z^MBBoRHf6t_mRrY1sac4Z!UnPDOJzA0G(DnyA0eDRRGm^+NhmOz_wL?*$mE3JxR}>
zz52!m4AenApF;0P)&J0``<OcZH4sO&X)pe0PU?kpeZpBidnL@esI51{AnK~_rOFjI
zb?`=@xvRTA2AYSuV+;C@s{`_2-c!A$2HXj?6NM1G)O`q^&GuHm+z!x_>NQj;<D+(_
zx1q24y($ntb;xm8@>gpb@E19yR^$OQK>hnSPzY2jDMA#aHd*QVVXzu2I37Ipc_)z5
zYP%L#3RNrVDp;7hkwO6B>R%{l7NP#*IQq`0PyPj%X!Qv>)ML~g$-s_Pr_{r4oLVdb
z_F1*u1|sq5AuYHBbv3<r6V*9EP&lVf-2;Ur^}Z;otw~k~(HZ`{dUZaAmZIKV36iRw
zq%H0RwVDru7u73V0h6Y#rO-vX+J?e{8R{+vfM%-y{TqE*>X&Ho%T`~e)aE611ic7y
z)ETtb%T<q4j3iGzV>ZlRR=>F$BwzjZFx7t+sGIzOR;bn$z>6aF0V?<|R{uh`Wv-|_
zsW|$o+Lz8#C2BVb&`Q;x+QQ&9btCP-%G7ZsP`Iv6yaKLVy@Ym?73yUa*{xJ3(^OWe
zPu5_()#`cl>5>|CP8iJBs@KQS`R|5$@qPGKr_P^+&YSADQ{jHSdcYS0ZBX~pClngh
z8+W0vNxkP=^xaaIlz=p=gQS3IQ9Dw}$!+y}bQiK!J$4TYcht8ilGdhvu>~mY>TxfK
zbg2FQf@_`Xopf60Qm=g->eg=cH8woGt7iRxf%d4UDaX*OZlx_>pL+T8K<ig`{)xT;
zbw0iQ@2SVu!I}H&7Yoq$Kz-<4m>5)N?gSZ9?^1z0RKH7m%whGb?LZk(cRvR*s@_gd
z%$V9p-&7k{hiw7agjKC<0L-Mi+84e(QV(ZA|FPPQ2cM?YMQ34YTK!-N$P@Lylzp+$
zJiQv6t>z{bmD*|cI|JKZ<H!JU(9C=j<fvwCJo=n8-?hV%v!;de;4Yf?C1`ZjBy9(A
z(<mr9@2;`FIUlTt=G8Vhd|VSvziv;>7CB6u(1d&s*Ss`WLcn=zH2LT|srhOSyztT7
zI|@)=&F#P7ub;+l6Z-r$#|{DXl*VZx8Ur-pS-=d`9Qp$!Nb|54qYu`c4+mI?=Egky
zkWOp<vbMo|sAd73Cc`x4j{q93nX?HR5gNON;373E9{@B;lQjc&&uD%(06SXKatkCz
z(?og0Sj|zYQjF7#&>`up=5;FciPww=z^4RFKYnGi6E#Pu?(Li=f_6elnh+a+C2Mj9
zt+0DubKD=(mZEuP2)?CiiYO0$LGxESU@mHYrn-(a%|{8)PuJ|5f<lHSlLIbOlf(j-
zrCE=S-0W<P*b&?%%_tpjax{JWfSIfLk6!e7n)~ArxvY7Ig~oi%it|t}(8Q$D{o6uK
zGQ}l|G<+cjQ>>X=h0ZIQ9TZ}{s#)Iy{Sr-zFR)8ByQn1nnnw5?23n^1<0JH4*UVBv
zp<JW62=xlh4-a9fQe$bv<W*^M&tRUaHSa8jg&NIQ6l<^5a0a1%LsNBoHlDvaP5L5O
zx~bWJ4T|-e1CG#W(0nu#mKrrr)2)OijSVGlZ)sN2E4Ep)Wi7ZCjg~%?aa;4!CXiOm
zfD(FlG$&|F(5AV&5tGoaaZE#FhbCkTxK7RS(=gwq>3IXrbZcIE4q(<^&F4QurcdJ@
z2$_COdnoJ<X!7oYyQkr`K<2(?St}GDXw)WP4{C1H)@w*(rL*Nj&6F+FhcyMB&>PVh
z-U2tOiKOcUW14^$F+t;+;b$;26Pn)_W7w0LWZD-!(x{8k_}HqcKLPA1O`!-H)0$26
zl6s=~q6@@E+w}yXwpxJ{igsEPJ-_zazi40Npgm2C^-*o-AvkkP+eiB%N3EX&`kb_e
zFM;W-%}WDu(LOIjpR2aY2Hv}Az2;(M?%LyH==0E8pBcm`j%#z~!-S`{?G(^XXn&`A
z1uyMy>*0mBwt%9}C$;_b{Q77wodNOH-k%G7KkeK%K>W4EPoQv08=MCZ1GHujcoC@0
z>xX)fR!3XKVC~L2a3R{i-UoMDyWuIIgle~2Y1s<XetZgEgllI_!F+_)fuanN+Dsda
zK1#ciwmE0C7yrMx)IO{R7o(lO7?QDCZ#QspT6=mp&T7MH369r3Hyb2DTSsx9MD2Xq
zqMp-!OZOj=w7i|@OV(=I0DWGo@1yfyigx-BxSy(BL4IG*4pO1QMeR&_DW+-v_yE}H
zT2muPhW7P2P{`C)Q8F@1`!^Q~+1mB}n7m8c6%>Qc(JrOjZ?1OXM?lHbzC(Mi%i1xj
z(8<@{rk7fQw%7#dLTz#v<=>06cj=2~#o8D;9$nG?O5wq)+H0NAFVRYlfGg9ww1B&=
zWzkbnuJxe{Ko#0)3rM9l*A*tJwBZtnRBMarDoKrYo;NUSwUZQyyP@r;_)DF3+p`e4
zsoi@Kj@D~uOX>b!gH|*Fm`3eTI9i*uZ&0P%Ev*xM(Y0Co{O1^2i`H>F8gFYa%>`-I
zescqk-qFT>jR|hkez*^y?b-%9M|Eh|ltHgk+d~K4E^XYWfbQ15uoBRBwMVx>uSZ+`
z2ztHR`hE~=pH}xX^!v37!!fi0?H_bDy{A2r1GM|v;kD3zpj|<she2%?1q+6>#%Y*%
zsP(5+Ygl`hE{l$6jr8*x)qb}adSlvkn;<f-b?*W6gf^an?UUN>8xVP<Ek6N~$J)iQ
zaAwM?_0|A;T02OO%oFX>pMYkg+g$<9R+mdrLOY!w?bq#f;}qd_(EX8tp&ixzM4O&t
zIu|OeaMZ2+7j8T0y6LXDv+e}F7F=|Lls$3P{ks>On=a!&sJrWqQX!*<jyV(LxX#*C
z27OQ6B3D>Cq3fa8te5T|I%#_A?$cmS>hO<I@!;wF{Q%>uo45?~e!6+Io%Gjb{0MSN
zw<HOD0lMw9y$aNAt%Z7!Zs%9%3)WfB!ix~y8LI6(t!t&VBve<{1ujhYmvt6QgzHjh
z)r`=!3t=fzXZ`~uN|!==)HAv$dKpLS7CS*CM)w&#9I?7@Gr`5_jQ&tRt1G$<E=70r
zT_~jLPC8+r7j)-ZU@1d4NJ)uIU1=92vvjZi0g+tY4;16b(=Gdnc4?P&-|R)_HJvgH
zcCYJFe}YW8?oG-nROs%}ue(xriT*xSy7We1SL@0)!KWIXhR)Kpx)eH)+|ZR%MD3=|
zNdNJ;UKiklscg^{(#g0{S5LvOCSAxqVBXRt)<UvH7wSX%&)d4?nV7a#onHusc1Jhs
zCiL5M3n{D6p?i&%mQLM_e4usd++Bdyt?Q-q@?D*u9YA|@szjLY)y=1}pMKp|T9*fO
zss9fI>dXP?yRY-1dX5LW7mDHbpe{NQ>O;C=?4_-<AL<s<FKJj8orca4opU(2QC*=e
z(8hG3Z@|-W-P02IG@*M$8|6ve()YkU)-`B=J*69X3uIdNO%EiW=v@1NVxwO!1&XcS
zl>!m=dcPvL?VvwIN7|$M<G;a~WBToXgIFE)#a#e(*8fBmkS_Xs+Hbq+gXv1Ln?AS<
z#9hDWJ?MMrZ|#EL$Mu^jsB=QUVFH%C^o_Z&<gLH?J+M#eBdL<fM=!nu;;T<w1)omo
zSG){M0s4b<=m^v=H)3Q#`scTyFW9PIPi2N7`cG+35T-vwxzKREgBdar`eSEd_l(|V
zF1(1=@3NpTMxW~ra#o*J41@7{$6sJR0V9NZlKw5KqfFLsqEpp*{X0~uazS7C4#-7)
z`UphQ^mZ(8nR@PZKxgT#fpnQFTi<a6Xu0}NDFKkD|8_atzpS4z37C96m!d!g`hRFg
zQ>b5~fZtd2A5lf%RsGTwa3%W0Nc5HJUx)<uHGMVRgelW^Jr8Fp^lo%#rcz%)*}N+K
zYo}qaTK|m{=4<p4D;0Fq>VKxV?M?j*s&lB<AEqB`gT5sNCT{5iSU_vmr&Bp~i~hw#
zaCh`GI560zUrE7&cD+4i>O1tk*)Y+mZ~GAg?b0jgoqA7yAQp}H^>61u<bght#xkg1
zM(fm&e(B5f{5{mqlYt%9_a#GPM4v}TpHY4Pmw*}53&SBYuK(v9*qzW1ErH0Serp)~
zeWd@02eilfWmiC^^uniMVp=bwI_M|*$s=gAF_iAc#M&Be&^-b>!&|i5us6K)E5IBK
zqlan#dDO6`4ud&naC#rDj)uz=26ZxQnt)wrgWq@Pb1}Rci_yCpexL)kn?c_W^X>*a
z4`6#3WMtyFp<^E!y$nCaK;7H0gBI(PhReAai;rQhD~PY*jRy4j8GcPcpTA+#2KxTX
zDZ_9VoC+`;p>1KX!6hG_h8PaL4RYErNL#2-!?tnEMVMhR<*dUE@20?u2*a^xphX%6
zsr)U<kW0_V8G{#nY$)3B`Ik_SF=V|6=vc!bJ(O{V!;wHaYp9@?X@cQ71{AD`hC4x^
z=L~Z)ppj$<tp;|o;dl~c&Ku?rqVa;^^?iW3XxJ(Qmu5(&+R}7`4+EAm3~L*pkZJIt
zL`jxGv<x0*8`jar^OC_i3UioasG#3Pu3;k!D0v2k0Mm8Zu>37p$hR6i>7gz#G=zW@
z8AN@+zH0EB3D6RQG#fCbhTnVudd<KOgGQO*U?#ZhhRg9#C^yW$4(tkpExx5XyV78M
z7o^HiLNDWLLt+KgYYcgGhORXnp&a)O!zLGyIzz<wn6(Cj^+F1~X*7IFd*dd<UlgRg
zWq9>IOf(zzcf#RTgJU1KJBBalP1|P3^@c*bVRs1hI}BT>CcM+oOiB4JLlf1ZbQ_lP
zF&B3Y&z^=tkD-<VwY`Qj1DNJML*Y}f&~M0Ugvfv)$4cw#J;TRupmorYECu$kVd(#R
zd4uyoD2^J=<)d%RP<Ra*<A(hI;OK<G@qJjDG`znReUA+9YSH)DV5E=MO&Pw}087(`
z|E{C)iNTJxWp>6Vw9BzKP8^3l2V=$-Owdtd&jQ+i9y5kg^48IKw+`l=jKe+vbvAbT
zVT3NmDO$Z;jq9`kbu$*N1m|wtcp3Vh#+SZ@i4(@0Q0RFX-=oqEZ{veMKu#K$P_d(r
z@x@Yb{>C#e!tN>K_w-H<FqVD?lt82Z6utj~j5{3B8f^S!KTL!gXWoU~Fyp*`;6=Dm
zUkwux#^PKUj5NMWlMrRRdjg<mjMJ}zi#B%B|9*@yHhu_&SmUBlfW;Zv6!JK0{PlV0
zr5K~uKqS@JLeb_6#;X*Mzi9jmpOL`#2aWNzKub3&PGc@IjNcbRG1GXb2r^m59dh`c
zZCthv<dQLTEl7@W32g#$jcl6BJmY9LBrh9%>6egilpO|Gf$>jT(F%>fxxsvqG1(D~
z#l}0d^j|SPr1<AmWBsQvWGyj1O^<k~@l#sfuNl{V2ADGA@HU8EH%9bAvD`T4XAG^v
z=)Mb}mBwYh=&LdwzXVckoVg4pYK-}<(5p4Z24eI#jJxTgf1PnZ6))U0dddJ@Z<H^D
zqYXwK1?d}&d6YP4vf__`&RfQyS3#PM+kS>(i?QMX$ZccuW0-F>{zrkPJH|c7V5!ac
zTnYNxjcX|k(_#FWPJ^Asw<v|wWgL!&!ER$RT|c~Q+)ITZJ;vKt!Sx!s9nkADE;$L(
zZ#=UL3Ij&#`UP<6o^h1|?0w?`3dTM#e&P?ALE~R*VRy**ay`gHqm&NV!^VCY6h@4H
zkD+nY_$mc5#*BYZjo7%cDg|W1_*4xfCyiPv-<~o$&~|^?m_T>?o*3Vzqn4fN6s=SC
zCY7}p)WM{D0CLn6*a4Yirbb%)98LT^KyxxB^Dzo%(<{$npf09$^t~xpQyv2%Zl<R`
zgMz!sP>4PcQ|>u%$4wtmuG`aefwrh8Oc&c=-pe%Dg!%P0`O#W*(v(G+Yd_P;LW+O-
zo4#~{Q>RSPOlSm{zB>oeK-11Bm<Tehr0W;Kre9~HF~s!LMu?m?eNAVGP*Vm4zrsu-
zi-8ty`rvo;MVMk2!iz}LkCe=aG6n0<cg7S-8{TNsVHGgrOa+0EJZlQcruvt7la-eK
z1XJ=Ac$#S1ISiR|rge)jiX@ZYT!<!{-d+Xs=S`0PK_tbrg-#TyCIto5FPL841n#1#
zj4slonI6r8`E*n8FkH(peL+_hGED_Ev00`T3esnr4p2ejC6gHiP1e~trsZE?FuA5c
zdYk5%x*wqPvMHt*B;WLjKU^y?b(cc1(6r-g7%Vbvp%;CzX(L6+ub7^bpz*57Yb#Jn
zOmFzY`%=^WZ=in7biotm%S;RC%MaI0A>rW4P5<>nvclAA4|Qv$$v}0<Ri-(9P^>nM
z(k<~ClMmhQsWqj(42>J6xpW$=Gp(5gyEjcsm>~70Fb*UeOgHJc+-R!%2L_u=dv8MT
zmg(iE0M=~!j}j#<rm+iXyluKiNtjmC=d`Q4WBP)E3~g4EgbFd+P3zype07+9*b13W
z)8}+w`L3y#9{(QGw~;W>YYN;0uFtga6>$Bg9LmEDn7&Gf`aM$?#l`QNnyBRYfoXv9
z$%CdU+D{FcLLA}mL(>j1podKj{{dyh)Hw!`QIj>^7cgTc16}tTH_f;KrzT8W>6|cW
zDx+(jk4$4!t@zmV(=@m#6R!p$)255>0sDz5cPEIA*@KF4Y|SA@F$g=e>I@p~&34OS
z(7`;HN-&O^Pu+yu$IQveKyftBq5!^=`HXcEljv;Dz60|v=9)mjxSE%I0pey}ZN!+|
z&3`TesE7I6H=uvq{3o5fJk1w&0p^5x+3OgLmwD$yNP3&!PeJ2J^M^ly^D%dff%uy1
zC>rBu-na@D{LL%LwNvJez2E}OH{PQCXP}uEiPj+V+H=4THa~v?=0nUEFN2&myHf2&
zsM$9M4u_d7yFkLtPbi-qVSa5M6wa7qY0DRF&Zeg##w>}47qRAl*MN&NHwqwf)|_?~
z&cvI4eIJqu=KU+dC7S&g(*NH)XHE)*Xp*^)GAzmFg|wibH<!}Wm}35i5?ZO|<6pyz
z3+AvTn9_^pMeEU*X0}kJX}Y;^EBZ3bYi2<&)7-ot9%h->OW;Med0!k1UNXm(KrhE^
zI0C!5=5v=Y>OAuq3+3N0o9B2#G~et)>GT5ga|ysMG;bb;XpuQC2aUz%`4nNgVtyO|
zn5$-&&tR~`987_xQu7*$DP1%F@H8xyndf~Ca@~A_*7I`neL5yom_2rat2AdX07{j)
zy98XddH*Vywbq!Gl$otHtHfx%VRn5Eq|Q7}QHq=9%Sq6vH_xPszy|YHD&TB1tNKBj
z%y;RhbIW|p4JMk+S#M)5TFhH6f!sFli^p8FnoE5^?wFtd8e{1&KcJ0Rr}<?MSm-hz
z=z`g9t9e&9*t_O6^vQ=F^WR<=Os{!-6GZ#W9`zvo<~Q$SN(Rgu=x=b(>`o`+`{qb0
z)_7q4l1>|g=3htQ=#cq%Ff2VZyHLh_*u0#MJ|pJCRIE5^&Y~4!%zT5c+>D!-Q|@TO
zY>oI9bkgkp9$+4s7de7^Y*tdG_muenmG@7Z4^iOsiTN?@vTQ6W3H-IS<lcpOJIiLO
z__Vh~eGNSa%V%$b9JRRYgXA$w5{1beEqhl3#mO>@j!e#$3A&o$VlkhDo~y-dr4z23
z<uOH0+%1bJLgisOMca+zmdeW*uczh0A(%g5sZEAYUX}$3X!N#diXd{*^3w}I^Rb+K
z9hQ781=|4TX9<~yMt@6*J;*6b({ktqST<Arb)e<R8h`~^o}vUmu;ukyD`Y|}j;{gq
zwB>;St>Ko1O@N88_=bW+S`N_<G1}roJM$QeG7yrnmPk4Ljkl!E#{?%>{(TmDiI%_Z
zp^#?z=Kw6FTfU-HYKCR&uP~Tti7$hpEX#|}0xa9oM~9?KmY0}w@ciXi7SgLS*CMY6
z$+PU-4AIM$%Gt1#Z%OzZFa?(93Sg<wBBdN(ktK93EEQW;(Ru2Mr3{sYv#(lao`*<@
zWj0+aD7APgfpX0<ErCdx#rOpju3P-q!EU)lY=lUKW%VQa{zRqa<>#STWr?K3Qnf|i
z2ls0%u2<kpttHF`+zpFt9$@M$kqO{#TAuqFq~7u+Ws(~#ziBY0M$3YK0or6aPjy1K
zEc%5|Xtu=Dm7NyL#7U6bmfzlm7p<05y0?4B@)sR6t!<VWc2I1$SSat&VTqwn#dKO~
zyx@M9Wo{YJx-C`V=(}qvp{;d~#g_6sy_Ui*nD4VZM}MY%%K^INGhkUy3AB5b!&IVn
z-||K$hV;NPg9_>gEk9BuZpad~1(FXfn`rwwY_+@{0_+isKmD0UE!$^9am?~-94w7n
z_A$XtSS(cTH)(m_3TGZ!0_e+f)0Q0CK0mSe+5p>T{=puI*v^0R7ADwkKF1H1?B_cd
z!WoD85z_!WI{!;L8y=g_*#ULO`E~C>(rLc6@Ekgw=f6pbC71cD5`pGA|E0S?bDRGa
z-AZtuzkzaI9`l9E;PCPJU9@}foWE={^iRy6tA`g}^OOI_(RIgVS$%OUN0ypqTDG*(
zEH(Ard+$l5X{k*!%b%mnGAn(Rp@NFCw=CJpo+<(&qJSWX$dHX9G6b2T!0&tFpYyr*
zp6@y5-uHR#IOp64$`0{hyeY+ycrx55JnY3tnG2jZ<5$Wp^I^>T4V?ar4q7<^7_%u<
z7s$A2qkMxP#_bR^o@VT${HS2YBl>zk2;;;O@Psnfk)Jw@v7E$&Gd?7b^cluq;V?9U
zF_lhik&JjR7!$?#N)Hmvcqtr!7{-jd5EjeWMh=WP#yd<5$yvrz1*Du~yiECl@eIFs
z8qx$t+9H^r$S}_ZB8jntuE8fWhUvLTVeH6-F{zAO^!cYW#=oT~r881~1}=jkpd{K%
z#!vKgW-(OcusP2tpy1pE##12-y~wylN7`&g^Elv_7(YEhWe($|YpBd+FfP#fFOP9)
zJ{m7GCTD`=GoJ2-&?}6OzCbSu7;d?cc9qf1f!;z!%yTgR8soJ*l&&+Dkms<7@dpJ@
ziy5owpjyJ<<)EWC7(!ZWN*Ok~RaeG{q&%OS49)@!P&s4kDs-@d@%|Kwzu#iarD>~@
z@$x57c$@JF#ptUTo$o-}9fq3`mDP++`h98`6^9_EmcgNrXdUC$1K{p547B9bGh%3l
zXkg5W1fZEQU;|4FV_ysuwleNjp=WK3WnO^aV|+{rQTG`|KcLOl&REWem<NmxmjU0w
zXr!ExhYXn&_)f;GC?L8R$H!q)H)DT1tmt7ZrZCeZhJZ5jdKrJe0C*oGCmn5%83xLf
z>1Q-oL*W2pI10iB8NW?}!Xd^7v?m^Bc+jLd%6NSh;7@Ig$8<b;#yCk4sWHY$7x0WT
znrVrhU__IX;~+Du4df8hDF`a;nF1An4$N;@05~!;$I<4*OdW*Y!_3DAAnXX!ksgnu
z%r}#u-kI4#E+rS{3UU@4W0w67EXSEnQP6OLX?vA2W?Y#KYd}si7n7J%%zw#&>Bdx*
zq0*h{poGC5Ojp`IdorV^qU6QgMbT|<=F&<4e3+3mm-#ZcQlP|-8S)7#{h7mZlmeKa
zQFu3yIXe_R3t~Q?MdCCwjP|?1%!f8wTSJ)Y11N?v?<Ycb7<2PYRE9IJ{{qArX5J>~
zjbOe=+t5hn-M3+W6w^v?Tr_hX<zB=vU$_qSvCLPCK;oFcZNcE5Wo9c;I>)^8Dn!RK
z)eV3rFlXpcN@NC}1xpfB9YgP5GIQD>1}cU5HSIG}nenfpF^y?Q&a-spFBB=sV4fKQ
zK9hNqHjr7&APSV6XCBZ3cY*olY#55oRRI)cGpA5A?-DbeKC+U>oJQyR%gm$eQOak2
zF%$4B%uSS#QNaA;F2(<@GFNqAEDM=mlYihEGxP?8UT3~RUf3e$2S-7QnX-!@CCoNj
zRBtfd$;na5+(NH-8FM|&0ymi{Qm80rzNJMcDwyuHmAJ)pruDj#*+Eg)+sshf&Q&oN
zw1V7WuKtAfpViE9^0Cw~_cH;kW#+MfsAKM>z|vjj6B?j;=F&{GH8Ar(gx*Hx^R!QI
zVtzqBrDo>kNdUAkj}*hgR;Ke>$ZliarX$xqrn3vkeI~0GxOQga2FQHCOwB-dJD7WD
zy|z7M8kPak$vi&-o-XFbMficbnZu1BJxsyxKs;hDp-Y9mOh3v&>SO-91eK4Ol_rSk
zXRelk3@}%`4o!nhP8M)OOrOah!^|Qlw2d%5Xlwk0xs?`|QRaK2=+aYWK6!ng*_f*-
zR5-?bsRxbY%*S-cXo9)nIUo+Q66p6m#In$|WzU+G4TJ-02PH{5vWn?Vbz-RxLDNyz
zrq!r)X6>U}K`yLwm1sN0+UtlRInMfwJohJ9V?Uwf%9{Ea)SqNEUjyzG%XWp5)7)6U
zihyuueYP649<1l{F~FXzXi5w5V(}@V*qaqgz5^dtV+V*YtNkGWeyo3JqVQ+MQ0_$l
z>*N=x3}jXKq7=lMOF5;dS*jJVDVX&YA5ubC?UYj!%9^l3Q5Y-VM!AdOtN}XVo?$s}
zM=65UOOID1%lRsRQLHL*l}5ADTwr$$>lg(}Vp*O!Xp3WgNx67uS?vd5(>Yda0){f4
zHJ`Qw39Q3yz$LOyyaJg?EU$mjmdu(){`eHuxl!O!S&1uYGoHrc7o#zqRU?O(3>LE*
zmS(d2wW!QuT`fmv&a+G-XuH5#DMQ;u)*n}4el}~87uqhdp0z<*4$Gd75V<Uw0P6Et
zn<?w|GD|%NfP7XvrNLZbwY&>J0qZEm=C86sd+7TUg{({qI&+OxlmWzb)>3+Ai&$OH
zK}<1gN*siiu-aFmRK{{y4tsC1c*$TXXAM(Cse<J(3oN%-+wGyEl9e$ZoVQtXzk;wT
zRwrHZxx*6D>Rrt`8wOkr>oRfHvbu4dz&53hwO|0&+-0qP361rv?i5ICV5ul_-pIP~
z1H?434(Fq-nYEgxv=-LR=g_BC)(Ucwwz1xAgzS5)FaC3ZvnrebZ)dqsoaO<mG7ZLb
zuqKno@*!(GZ9_X*1Ahb1#oBNIC0jRZ5e1EVSWI$KK4N`Ox6^xBj~T%Cv3@Q_+hf*p
zx_;l!N~5W8fHlJ&LI+vz#K5#6RtZgo!>m|xfse3UPXYIY#Z;p-%9_~(O;1_LFGKw^
zR@zJe##o=z&S0D+ehH-s8*3kCp(zL1Te>0U5PSS*l<e7@r$9KcYwv<MvKMWGLMQgi
zH28<vxjI;JguRaz#iMK{-9C0^Up9ipg`IO5rDN>ZWKe&cUAGB<6YLI(7`U=uKLLd&
z*&W|Q<|%g0zaVaG+wfB$+}Z!k1o2?69L4Abu%}H0K9Idz3{64ou!qoen$3TJu?S}W
z_CHjHupcf3ODKEWKJ+(?EvN%7oLxhQtTSwv+h~hmd-|X)n!RK);4$nIY_P<#Q%*o{
z9D8>wIM1?wvh4yr$KEgk+41cB4X`wU&ASPnMD|SDStPNGq#()c^+E_uVXvdgRQ6ih
z8Kkj4p)GDYdmEjTGuY0NP?5<lA{S2<`@ADc=h+gP{4THqE`#$T+nd6VIqX#rL2}s}
zmQws7kNqnH<TCrSQy}^5m&uoWg<bR*HWjc-7eUNb_Dke_Dr5^NdUK8a+DuelXMgz$
zeyt+*uRXvOv;FAkQ^I!4L+J+F>oQc7vag)QZ&1b#k44)}HjBJ$<?I?tD6C-5-%Ix&
zZn47^;HhGNO&jJrY|DD^RI{g&tEGm03Qm$Kwe0v3=&fUaMNX`{>?suTu4nht?W+d%
ziX9l|MmCdP(I$2z1Gr}P;%bl<_S5emtd(6S0%sfB#Q{?8v01A??z6|5==|5tzTgYJ
z57<{|Ti3x(e+{e;*+(f4rIXF3s~uhJxnF^$o1OO|My7|2ATwSSwuci`^s+aNLvJ5D
zoF<CLY%OJZ^t1onjLHG_;YP?DWP8%-cZmJVt1xDm{e<%DM%g>g!wTC|_I^*$XYAY6
z&@{$Qh(&3f{q1`g#0mD76sS4G@qYmbdrk(8tOMtI5A-^6=FpGs#97_|y@xqLw@^C5
z@%a#Aag^glUQ}mJQ3Le4aQ>uo{V|TAA1uc?qjcCm!C}xr$koO<OHt;NoNZ}9oZ<v*
zg$g&$bn+>=b2iaV*@H8aHp8BrT@*L*;soWR(wk#=3cWs@FUXzg%W1s=3;j6ZM?m~J
z_g14afb&8jWCn6N=o=A1oVj&Sbei+V+mI5>xtEVp2*+ln6MZNrC<c8B<6NWXIh-@)
zSCr0hw$L^<g7YfndPQ<xnGT^*oNY%jq|qEt+C;>0KBrgwEN3P83eR!&+=rp@oFsB0
zC2*!V0+-17>J4a0;{5tP;K`it$$Oi^nM}`9Do0_Xb6grnL~~g>XLbvW$>40E_--a=
z4?Q$l9PV#m&EvdE8I+efW}2DuIcsQ%yux`*7c~kvuO5KHtDHDbz^`#On$X|tobM<t
zxrnns4^qrI>I#+;PTRL&Ddj{_z@m)v<KN_exyh-g=vq1Fb3UY1a9*LGqLQ=nDB5mw
z_S589#kuT>(j86_y<^p!<@7w(a3<9NP|I1G4wgC&V;@-Va(0zLeLW|M3(f{k@yF2H
z$SH_K2b(w>=?u`!xi|+bEgbJV6n}5!EGA!N8z;CNLho_DqXWWyP61^gw{za2z1{=P
z*H(}Y&heEH`j8V%DPNtOH>U&F#fha^pqsOT5;A%?>o=hC5r-dvQZMH*?X3Ga|K5ho
z$D9B$)c14p%3;$0M+viSQwBNvXumMTnV`?l40F`<uVqF#x9D>1Q;s7YMxSxI=!Y5O
z?4~T?an9`-;GE!e)6wM+ck|n*wCD1Y0C3>?HG(*D#}}Z@i5u`5gdO4jObH}Mxw?0u
z-kIA)Ka30aMT#5Rj&bAT!E=I}OVJEh?)!Hk?IhPm4!u*{Kf6%r#*H^as5^HCMNvGs
z9<&4V<Sv^7;>Gp+16}jxCeMWmA8tN<%f^?xo{qhK+=c0=^yh}qCOm+fL-|;N+_V$`
zg1B#SFixj!+;mFz2<Dn-Aqe4)Zv{^%chwMV3gbpzK`ES@KMOXU;U>|pFoHWA416S4
zT?P`xU9AC2H22<0D2(9_)3^R&x!=+~f;jHXc_3%Gcggd3jvJ*0AfD^;4J=IH#!N>k
zk!zbOhWZq4XdqZqxhZr)PU9{l=V&_j;D@j~gZsukATqg$<i0)6^`afg1+MoeAQ!m}
zFM>0h8#52;FL9U5gE6_><+Z@&aeoMg%*)(A=^kA^H#7?!yuw|U0hX)WJs#*_A@{B=
z4zjOt6~BS!I`<Z3kr#2xo55Plt)S>y3HQuD&~$^lh?1O3xn&e^EaTb@!Tg)t16!e@
zocs5GXC7{!FL1ZG&(DDDO78o#6S~cP`ync;xDx^B*&Xhjg#c7@=aI9mhP(Jn8+dBD
zE#!-?<L-Eb#=G2q=xf^bT+w}KYT&*`fwV?$5<P)U+)N5;G;>FHqSV4|^M&=T-0LZT
zw{a7zVCX&Wzq>I`_qkhxp|_peNnh`Nz|CZWbZ`gRsO;hfH$zc3w;_w(zaH-12_PPE
zGbcl6FLz`yc>1`1(}AX+TmCwL1KdR)qH>U1H3y|3?!tFq#V|J_2Dm5O5(<)ya#hno
zo^mDR|9r;HOb5#t_c*;x6WmrhxE<tW9faOPyvfT@vgfHI=>2oxE!=?~I`WRu&cuo5
z>JD<4xBC@HJHlH-0feKx^JN$dXP&taB^RFl4ob&(y8m*-c)9dEp5Qf-C)|~HdI)22
zlDBR?Do^o#O~R14@fIzI26x`hJrM1|vz|tqCvO(5-Zn4Z{LfJ9&C3XaQ9eA|7{vJU
zR(=bFA8%9!gZ+8+1JE15Tk>BfKX1-X;DdM<=rnkmm-H%r*kE4USHOkv-gpaALU~hL
zVMQ44`EFE3@O<e;SR`)`9g?DWUgX}6=D9NgkFoLUGhs$7FNhoial8f%5a)O!6yS;H
zZBIaD0&i;$tVrZ#9EGMNo_Gl=lX(xwjhe!1ArEgFZvhX0blyBVVrKBBQYv32ud*8?
zi<fd1n$GhE$$xo)_X@q!7kN|mqD$F4+lU*Amw3UH#goIEeg}v=-nHwn=`!zof0Xih
zE);UR!qZVGsDQWQHdI{YY3T7N<XxKzE3WejxR71M`;bzJig^i3059Ri&V|eyJf$x*
zl=9j-fGgwWQz*8a=TE;@1#gax12MOFURQvq<oPtC@iy;9EgGwMoe2Qm;qi8X)bO@B
zgVged=zv|v`;MmYyS%zm=&k3~=cBTT2j2%?4&FW|2y5Z}Fb5;k%A5TgINNyrNcNa=
zkGG4?viEuW=~VWBR~Aa{g$`aWojV`${!9f=CohxoXS#SF)xel;-s_9N(!(2~y+ALo
zaVjeNc;8V_|1poX0Dykp50u?Cz#G|%(jafiQOF+R&2)j3VcrG`EspRuY(nV?Z;?A}
z8s&XJw?>}vl0TyFFOBiyePQr8&#eJHoZ!v)1u72mna`v05dSOM``Gj2MNsI-Z?Qs}
z6F+zp@Q3+x$vbg`Ur7#uqx^k8L$)*jTr_Yl{NA5|JI+_prOy+5;}ZZ}`HT)!p5%WO
zipo=biGuQ9-1wpY0O-z7mxFln(>I{ei|_d-5Z-)mIxP9{IZHu&`Ay5wiva#H%4-bd
zPsD;Vh`%!xrPKUh+EEJTYbjARg#X}W3|A=MgAUK(d@=0>&hSUp0Up6GBNu5TKlU}?
zY*G9ga@I%lXVF$QhJS-D5XJE;j)CVaKR*wZ=lCUYsEp?)lY1_KKbIEOME*aaXiMS?
z=rowjf1SSamBO!nhPG7xpLX~u()d|iNXg*ueh$`W@<lWWW%0cy!HV<zt#sJ9VB<%t
z@N-?{e@BtvZ2lU0N^|&wlv|q1e@+h8JpOa!eY(sy(;Ah}?_7e?75>`?z*4}kEdVLx
zFQ;hjHGXUp0N45V=&)17zx5~DiutCE_|Z!E@$?P48+^4BNEv@B?bUAbZFj!`YdQZ5
za>rEg_vNDY7C+(_3{4e(g9<&o!{1C-GphM=irCli_ud7*mani!WgY)ZIw{`epE(TD
zz@MPSt&y*z0czrZ+5~%>`N5w<eGA`2OGYdI3o+nr{68q&^*-OuM%fGPd?oFvAMoe*
z;&<xcU!w%~hy2A2P}s@uqu^~9e|ax}-Tb-qrI{Z7Y)VRd#4jP&Lofdp#d#j{9cU8i
z=UeDsIt}oL=xjI0zw;SH5ApXS*fnLC{{!V}jqtyxL(VAwwK?P_f6CwRJXoLc7yl2e
zWBhgNAbXtOR*SX?e$)#5A_oOWX>(~WXs4&dL2#U0hK_<owApeJ?4}>~uz*Qhpd*5h
z9sze$5Wohfi=h7<v>g*fybBG-1&ingzzM<2r@`VXnE#agFK&X_YtRdKfo&>yJOn}i
z1Hx0Vdnyd}5;RSN!QO(u=+2vuV0#5D^b>rWiITrSOp|qhpuP~@4ipHdqcTYFGDRv*
z3(OBu3KncFfWlBgK84D|1Z{gz3KzUG3#OeBShv&q7a_P#N#T)#w>;6AC;{UOG)4=)
zjsuAiWYe@2D_H#<@NojuT(F!Im_Nn<#S4}^04_n$o(_8x1*_=BQIa5Y3)+$e`Q!pf
z5%}ezqiF)WVvuyfSQhNf5X>!uuuQ=_>tVJnOAs~z){BCbuK}1XFwir5N#N@bM2_H<
z0FYe4UvwnS6Z}dRUKVVmy!<NyN6Kg_5cnKK>8c<p8R`oKSrHI+O~C#h<8)nc`7jg~
z2|CH+St2N;MeT;5j;>Ud3Yhy)DzgdNC6IknFncO$%LU75^Isw0>S4t#!Gsq`r9e#n
z?c0J^=}cNBSpEd&R}223YfLqQ@nuk7D`1m9u}-jkCxqP<y!AhfOufL<1;#W8CVoO&
zlb|dZoXvvjUXT{StRX0B71(CK1KDkY9}2+JF6g4j>I1=o091Ae-Y*3Hp&*rZx}Ac&
z7f|XF_;`bK3xwnse<a{hVnwgu!ABr{g6ew6ek}0b31R($FJFh00l_K?Aq@(CrC{Q)
zAb_qBjR*`Skn%+Ew=D|AQNhkojNVhhm*l;ACTO6$LSur|F-RL1d_YmX3BeQ^?t{W8
zdMpnKH_9+v4#K&V9pWhb{uuyHLJeINIxIX%3+55w-;{KCROomPEY8A0a%>$F{=o&y
zapB%G5OzZN%Q8CuxeAxliR7ek&JOUn3#U=k$V2!G2PIEo8|Bt`2@_{Sg}2bM2A%N{
z{xuVw@fD_ZLzBO-h!Ua#gg*Cy3lxsb1|UfIHci&2g%{~Qcd+m)O4bMw+S6_$Ot^+N
zV&TGFPw4yeXM|a_(nbigC|5I5xc&p+ql9}dKvT3ZiT2_#!stpMVudk&;EWSGy@Iy0
z!rkN~j2GTW10X@@JO&ksLcSTCNkaU?V7v#y9h7gLBAiTV@~Oi9e<3Vg_|}gYk__SP
zX7aye3cvgYh%90E39z0Qj?pxoE&QCkBbS74P_9aju=q9fH&^%-dCl^KhbSt3S@`ib
z2+bGHUyeRq5q?0&-U8u4S`-U~xzoUMP57-27G4+XDVkm+M6Mdv1K|J<qHhQ{d<2}W
zRA@7!u}m0AIWFbGH)+|g5N2sG7Po}k$bVWXbfg*ew(#GTAXUN?$`H6C^rj<qjc|=K
zNUhMGavtl1zdu9UU7?`?QtE|U`vGVWI;hdsD0HGzS+j8C^AO!4-0TRJR-4c-8HhIF
zmgk}Ap74AfjJhv;upB0K2vcfd{zGB38l+Rmt_QG7xcFmmb_+H1;`9g~d=Ab>!opri
z>lMmrtJo(TrwO%RXqG|PfN=j6SU4!$Os=dU;W`S=4GaId1SwC1w&tfOjtaM1K%NTk
zb)t4mICKv9apCbulqQ5ho6vSp^eKH_;gD!F4r1&@W!)$_h)z+!!bvoE1)PUPKICFO
zB3knz07pf#B$(|i8oB~uE~3RJFbKy)w`c}GAu_AM=_;zSok8PC(VMjTpAx-AleU}a
zr^#q^7uCKFF<zn&8%o}y@NdykAJMGcDEW%`v`6$4Jt3FBzi3S&N&%wz<fI4`Ey;p0
zL83NKz=K8KABPnoBH2QeLPcw7V-hCXM)PvG$WlQ2&j``<eApH#()|c4qD0&19$$>;
z#9Z_+R^&n{{Bfc`j>GP=qUq$SJSPfU0nT{QTYSJ1MD-#FO%nP11u4lQA9{aMM9UU}
zB~>()-qbYF<QcFqUDUM&l^LQx6Y*SRiRQla-}eVaUnB#6LG*q#^j;MGP0N0^=qD~J
zFNyv~VZc0*NenTUMe}X}pD$u_QMw{JORrObh;<3%s^~Rx5*CU+p{@KiQAh+>u8Y>K
z0=!6+`U^<0Xj%{2N<?m#(WM)rk#@R&R4O_Vj=?As+4+O#rf3?46Us$vYhgu&=#&BE
zmMC%^5S5~N(IB@)ldnQdwdmS*^rA-e)_JI}6+PMx&N`7B<>1~G)rCTRy{L{3D-EKJ
zlTd0DZKI{CN%Y=ZC^d@?k+;j%B5Iuhe5<HI0=;dbaCgYQC)!WW-20-hFQHHEqIc-#
z&jZoI|6xcvMCUI8_)x^B6Md&>#18N-kvF{#k3@FMU`4O!eh^B1qQ9O2{#f)%4fOVl
z#>nMAAWB;f4TGYzk0Eo&Ci->{gbs^lljna#G<X2`C!#P4OOJ}Ga$v<%(Ns!6c_!MP
z0cm5Rk4@kl7me>lX+kvoKZrRfmVOMOhs5D~px0hpHHeafxPcC_hs9Fb?Hm!my#)3i
z6~91fFwWwu#~|88Y%7(49uvPsgK%8Dixi#^_mzUUii_Tdij(5^>FGQr_8CQ`yV(92
zjPVc;kW1N9-2NCiFY$c3P2nwWqstgR;;XJ8zT#N&HTsEpwA=9)r<3nHKzzv`ZGmD1
z-Q_<mUT5=x!NFqBE~p3*Z=oGrs5p?$VPRq^<-dfBPu)W088JTudLzUaHi9!!97VCG
zDDfxFXp0tK{{bXcyyi<-5hwnU_ETrYyUJnOIkE9mXo?pnO$JF22c*G@MDfR;qAf}M
znTriQOcoclqc%l+k**V^ic1Q>njyYVb7-b`5(WIT#FEW0=DgURqQn=(8I(bCQ9M2s
zmD%Dz$}zhnK1!MCIpP6w_T`E<2!YEJFMA5ke6jN%F#C%5iVl?p;^P#!yDI+Y*njaq
z@%=6!u8Ef~1i3C||Bj9piO+ljM6vja7lf9G1Cr5pL;U(-;LF5YhGG6qaoJ8(mWu<(
z=TIRoECKG8co%)Hs#5%5H&omf&*Y-AO1zPxpLfJ(?m}j@`1IFcsS#IWmxK79ct3r|
z^RBp&&b0O7VtN7_#E%M4Y82o37o<sS<^$L)-fskFi@5q%=xr7MFo?=Fu^lau_r$Bo
zHTyu^NjF0}#JRMie<)r>$FWZFijC+*m-srl=eotebi>{r@xfid*&d0_Q9$&H^R}S2
zPrRA}2#>`a+P@BnB@4haC{8GW!9(H^8B`35eUc$`MEr~b;7`O74alhYefp%_Q}HM{
zMW2a3pmgXl@!o2*jf<ar3vy5rLK#$tB>q2v(_RwxHe@>3B<Cri%2Co+gQAnf%@5?T
zgi!%aM<fw+SK+ASRXX@NOIELhY!^vG5?GE){N$)SA-QoCnp`CxXQ1+=#5*2<Q<B~E
zJi1AS=}mW+yhu}$hotYnbA_Z)1%Q`i9Yx2yCAJBQ^Y}^razoKya_mL)H$aj{@!>$p
zHxxh!l9W>X;j~0C2X+Tb<~joqB6%$lDncc%(|i*qxxvG5g-bj}z!@QlrbAMsWE$mT
zMM++vo1oE>%jB|;k!+y2MXY2q`Oe}bb8L@c%~?tPI1uL~CEtL=OTM2EV1ncctz1cx
zf6GxymaL{6q!h`MOmrqy66y!NX_AAKNRlpDQvj9>$-JphpDDQ^N4K*i?y(SkUedT0
zEEgp4O<>8EtfgqgB@77^<wz>pY@oT4c-jr;NgSwjS<*}%{Cvq<)lhLo;&T$DK=N=0
zfLA4RDq&NhL?MLiBFS5{`!1I3YXzW0BANuw8<KY)fu&RuNo!P@BzhN&xha|d2UyA_
zKSV=Hg=Anq;I|~XD$2jEl-%k9Yn5b`J$iUY62e7ewPZ;mWY<V|J0P@HQb-q<>Lg5m
zkh_vepJ7PrCE0WwYmjUtX^r?P(9tHzffTT`NXqL#S|!>B7}F-1Mpt0&NmkIs+xwCg
zY$$4%_;k|$|9c=g?gvdBl5f5P>qAKdIp#VgzGFaiNgDTo^hjJkLFFTfi33f&k}clo
zMV~}Xxp<Eyi|s-BB?B8EbU@;L0X7Xv4EMk}B>8Xy;KPz3M*v17hv<thPbJgn=<-bR
zaWgEmjY+uVWgnLmk?(Cna*;kmaZp<EJro|2mczs;_R=`|8n1(Na6j;lQZFyyous;T
z7}6usSrpYfDizQv)LHrp9duo!w+?~xm{jr+j5#iip=j?3sd*b@x=IK6=;ukPEgWs9
zY|@)WknJX|CpV0T^v^5c@s#R5hYBxgVj6(n(#RrI`bf7Lpu$($KN%%I=>%<!{iT1z
z02d(L{SZO}r7zIe4uYh@K#WDO^dm}y43X}WqZBF~m7)|T^^Qj=T)OEFG@OyzJSami
zLVAe8Op($Bt>B50hUK77(b8)2$Hz$RXvsP&H7tSNbJAUO%#WAmP*fm6s%eK6iP9k2
zY9>iPrbBzOH17^@DbnxAg_bH^5sgxs^zBNN(xqlvS~I0zYz90_y46+$dS1GbcIX$R
zKT}fbMQPJU^eJ2VV+r(LlD;TMTaNTRIT>@M-@Fae@}x5I2VRyc>CAIQT1pXv0x2f|
z7G9P9G#{i;`j|qC*QCGEvVUE=J{RyJX}2HX#nPJ1ASKe{Khgg4hII0L^r=+($2F+G
zDV<NB4KJ5AQT9QF^diM3Zb@?}3{ffVq?Eqf(k%**D(ONK#N3evIYD-{^z|T=YNX%Q
z!<bsBmlA+_>0Y`<+aTRcyU|AJdz4bwBK?jo__s=J@6-F&CjEiNvP(MM4GO!ZMmk;f
zNKc%H-bd2J7LZ=)d!K>yN&9Gqcr4A0gNlA>?Iv&zNY@(C!$E2CL3CnB`t3g`4NC{f
zoiQSfn}^CLQqwwcj!H-92KZCy{9~wmCT+lsW}7l5{fR=9<I-+=|0bk96dyh)`+PeP
zhh)Xu!D=u2u@GHzkRALTm5#C*7@;XnvfUJwJ1l!5L}!l3*8dKLM`gcJrm3@Rl>o#=
z7ED35V=~7N(Cy>0Clr4_Axoity2@fG>A`kV_76>Pr)0<X1K}oH7l~STS-l@h9y0A(
zw0X)pY1q7EXBVK&TNb(ogYP4AJPR?tvfnA%>nEE{E406?IR_*_HcC@rpsYF#Qi5c^
z(HwSKrlqvTU|Bk?>>)Bao$Etwvf1>bhsm~7L1?(Fk>WgOWELh65whu_z(>l2TfiD6
zGYo<yT6X<)3`vY^?^2LhSr|Fg<7A(cv+t~|kFJuOla=4a$i&MoAAs2jvOrol6J<g4
z2qekoFN3~hS(X5tDKcB@w@{HPTN4PQ(qwNHfhS#-Nr{vhvPG$=%#_`yw1X_!X4>bU
zm)-aUfD5wWov6GdE1~^Ojx5XpxLjG@D2&OI^-vDOW!dH=u;k0O=+SmXHi<Go3S|Cy
zXuB#)TmhR3WmX&Q{I1Ee$+>x5cDoV=7s;F{C81chhBo0PvWT~VzajgTJ|<NvYu^b#
znXH#~vo~cmbW$vrec}&zg>0_`mA7Q3aLBHd6;OcYwrtC{u%b%V{ygA!Wb5ytvRc-D
z7L_%!T`KZ_*2?x%wqc#DayLx8D?2p|z4fxOwGi4M+eF#ejj~}rtZ0(;G(t?XY@i7$
zT4bSrpwucmMGm<(Sr-l0J=t}7JnqYUG-zv=6^5boKsLA;QaWTS-a+L<+3_prXQ%Am
zeLDYj$#zrXOSjBT12H|ah4eN)l6_9`sb1Mj7hzMM>~Gp=KbHM6gi^n3DMhCTWTvZN
z8I%cXpm#{t@Fy%Bmep5*Wke<+U&Rxdy9z9$vae}N{ZuyXMRfa_tUC!TV>0`wNqGOp
zWph@+#0gpNs}Oonz9|fdL-M7kz+*2zN%2w#`OD-rbClm%2%%2$Sn?elmYXRP>WKU$
zN0@e0Ui>Ob&hjtLqU0iXrw#rw`EN#$<MN#&P=7)`egcM`l3#6s1~<9$Byif?<*9T9
z#zU^6ToX@u+iW1b<mFm4ddr(m0_Y=8ehVdEdCq@HCi1298~DrRl>87NzeSt8KzTR^
zrUl7=r1$=`{4_<Wg5_b9*%KnyY9TXJ-m(zA50l5WqAgrLL2mgoHaU-c9T9TZkHHfu
zf8kq@D0#+oJOa`3w`ai87<mf0Gh^jX$?Fv-KW9SQS^3=;F$m}6izx~jFVDSzQi6Q*
zXMiWldxyc9BwsfTqLby%=(La`pSKI8RQc@1up&(!Mp=gGa@)#G$j*>oA)_+oHRQ$3
zl1B%E=e%4n18o=N1C#`GQQk8fBwPLgt-_b&8RTWpk=tn2yDS%m1CTG54PY#;$h~wJ
znF4tyC5&E`=ll%Og>p8{+1KPTl(=$T{u-^YMe+`t3xLIP4SlbwMDAq+xgp;c1lCe{
z@@))hnSA+YsJtm(J{8i+<*&~JzEVC<336LLMlqx+`G5$9-jUztL0Gl?K6&SB<fG(z
zsFkPDnWawtQZc05l~*C=HKktuCI$K%<a@X_G&ag7;crTleCk)=X_kNJhf<5&`9+Xc
z`8RZzvP~{0C)7Q8B0c2y<tylb-7a_B1oA+xeh<cU$lq^<*$?H1UWVRI`MNrgF1f)1
zc(>f{HCWgq*Q|lwNAeFS_S7riAf@|9ee&HY=*46C4EhcF<>BN^8j#yjaD7njNc-&}
z`CUq98I~7uVAF^^Uxd;V`B^E%jLK(s;P-thuO^q{Gx=+-Fmz15@)9~aE`PEPEEDo2
zr(oJa#cH}(a!4`O4o-Uo>s`8k>!5g!wr7rtc@sc5DROp#99HZkgO4a?QrPCGV$Tmy
z=&Z=2u#1bL`43oeOtEnnEIh7|UI+Yy!s`^e=Bjv}KGAei(U%K_rxX<?5I4p83utp!
zyhaf_4~3Hk!aNo4Pl0JRFU70m2=P|DL=Fib#rPU1^i@RAF3V5xUKKR?E7-q+H9+y)
z%TOPv*s~QRNbzD1SWYVz(LY@cR^(AqTZm%pI!LHuF)guSilLRTFkF%T1K^PgZ<-9E
z6u;89TcZ_s=mm(eDUu@5(OAVP4r=2Rdq!Z)S%owWD$XemQnqirBJwI&5)|*}qB2o2
zjeJo_il+A=G+A-P3Na~)IdmXNRrsHPlr%+5DN5;zuW9bhP^8c?E>p3V&bwK-#00>3
zMb#!qxuCH1P^j;sVh^SFXDepY`SFrs{VcHNDCBaKaur+2tC^>8aY9EgE95>P`HENn
zfb1)Z)d7%Jpm=Zqrd?G${0l=;sEApQwrh%f3SwSYq-}zRB85L?Bo!-+l!#oSNV|m6
z4MmQv7qUwg-_SUhDN@cu+D*l?7^o;$94GH$g(58oow=p>{s=6rRG8m~rrV0zpP`~!
z5mpFzjUqi7q*jrNS7u6`;^(c9a#x|CWVm|8Zz<qxP^9L8rBU$*t+!2z&Q;)SRy19v
z-BOEUZU|JgD!$(cV4EV3me_lWnsC^3UlByta@rN15|9Uq563_{6q`PU(1!}Aag;h0
z-Pw@VrQnc5yj$@DeMYHA@hlSXM~Z=4XzNu>+lEq~ViB$7j}^nTmFQQf^XUG=fI>_z
zlR?GERY)6BoSP2y!-}eJpkhQ}sKp>YQFQwNF{+rp7;R4#ydR<Inc`D8P^OG27Tf@C
zT%q|HotRJz(?<KC@|Xy1hm`ig0N5*2<dEW^e7OmV9F<bqUpOg0eu?~_hm}83r1FUJ
z`}cr2s`R8Q&CbeI|3IOO(lQkTbWC}G7MbJ9j-`-xLODp;3$DswBXB2`TN_Y$O8F<U
zxu>`(6NKP&SMn}`cqrfA2fd!k)pS1aQhuff@m9V_cbI*YHVSLme3iSmL5!dBohj&(
zzw%$2?gEs?7to79Wlbf-1SuELCpk_lwRFiYSeZ8uz!2phF|aUHxxNFXFy$SJK!+=r
zd7*Sh`R88%L?}P}2I?b~OZy-tO6lf}zQigIkS8rpX&`URS(|bZt;Xk+1LTB?SAL|2
z`UK?=<+vm&6JLVRB;_-D;ggkaGLRHySqy-w$}tN1rYSd021!@GW)IUcl)K5<kf}8N
z0xPnVHz)_<ymI^>NV%XC(j#zDdDb5AY-Mr|G+a{JT7p4yl-cA*$yH8nhKf9;eLl!#
z<p*lu^OdO!pyG<sbu)w(C{;8hSCud2K~tgf{zo9!lymrCxvrc^C;1}fyLK?9Sjk!h
zg(b?@1Q>)H%E6n^P^z3vJE$_{f#b00rgEljDWsJv&wYW$3gumT?{6t1DM6xAxs6h{
zZY%RCDo~|dON;RxrI?<QYGq>wIBS$Er-S9LGDeHadZi!bgET0QQsPUaa*#q_O-eRJ
zF`AW5L+DG3^8NsfX;mhcz`{1A{BMeF+*A6}Y4X1E2ik14E5D;H`2%I{F<9E6?7jmr
z50xL$heJD+Tk1i&lyNS=bt`u_L0XS;axzprQZA<CvR>sv7VPa)HcmjrW95EYn){VM
zQkZr?S+^dgLFF&B2N_b@e@fq<7*=Xhp?5_2-CY2mC}Z8xII6t#8!DeFQz&HcO!>bG
zSU9HqnUXBWm74~kcS2e14uuC*X<Z<PRPWGs&|Y<qwyzGVh7Vx2qbhL&Omk9s(He7D
z^*5a>j;Jy=!iu9R*J`?d<gD6HNxv?t`rjb*m}(aNGOnsw<VZZJdYc^Tr&L?%*0Y;x
zTQe%%Rf_2_#zVC+7L}f=7dkN{UaE;Xz<H}KYhb;P>hJw9)K|54Dcby0<F}!~U$vC_
z8KAmE-?<4?Eu_7cEl8E~6A&RP?=T1rRsFgOD#BFHC^!+Wx=mSdXH;*Ivm!#ZCJaI&
zRTGC{ew0e<4ic^MJ_Bhns%Uc0#j4D7D<Mv$rAY2s)zj@D=TvX_fF)klKNY=CP_5Vo
zVTr1xQix8nsaDU18ObV_1pua~?ma~*RrNPLb7`t0|3YZG>VqhBEkjlP0xC0A4=Gfh
zrJ7FpKIc`%bg%7#s(|i*T~sw=OFt!BwNwNZmsDw0V98NMP})GQ>dX$X<f)?RvAV3f
z6AWCw$~L|l(ypi`XeKXE&7zR^Rn=y4O%<x9JVxo7YWZ_ee_gfUZwM_?{VW2YST*Yf
z^u9!uBtY8@mH0N=N>!)l!rn4f>I77jt9H}>vZzoQ=}U*VRP9Q%RjOuegfX{OJjyGq
zQU%#e=<gksaz8XxtHL88twuG8Ts5_-8aJq@Qw37Y?5=7ZMfK`c3kcYtVpABtQ8oD`
znBAo6BtJ;2s+S_VZ7Tn>;Jl|2zlqBGD%%mj+f}}PkoiFMGEKT2syQ@?JXEd!*aq7=
zRTn&9TbJrDHoD!dy0`>9J*usApYD-r$}zC?s=^mSTA#|j6=EK%p3sBXuWF_Z(SWL5
zjLJckdMR*2s*RBV46CM*%VR|K{y4}J)jJ=fZB+HbJ23mH%4IEtJyV@MPWNxeR1L+@
zG_HEr59Uv(Tn<C%LG|_tkVEQobON$hm(s?>K|OU6SRB<3v^{cCzr6rL534s_K-&@Z
ziyuJtQT2j*knODANHdFz+V~zgkEvh(0ve91ndC$|p<Yx97FTs!65T&KsjjXE&nfl5
z8$h_JbIHNwt}ci{4?Wa{p&*{>Z?i$X)b4a5@K#r5qrX1t<Y;uwSN-HKsP|J}n1C_<
z>gEs77NA~1(UU;+j##t>scY$b3a8bt)8|xz)vF7D3sFD#82W6X>doZW3sdjA3)XOT
z76moVsQbF0FhU*W0Ys$wH}YCXsZaYtOte~F2`ggMW?EEZ)$d7ReVn?74((^v8v`Kp
zoLV%DPQ<In(@;uKOTs}C)pt@LI!WD@2Sv&1cj)_NDK>R6g+^1=(e%Qnsh3PfDP4Vo
ze90N=d)XkFYPWW@WvNH#d~sf#)&xx#)P*vbeNpYZ4(hYje|`bZOX`EZfaj<kKL;RJ
z{f8qs^VF;Ug7ufxEi`KtsO?X|n5*h*T2vOQZO-Jlxu)(l194p~^hINldT#|9i`7w%
zXe&{_Qj4}5>IbLMR;qsY3N)3e2k4EtsUExpQm%gUC^S{5O%))w)N$mIu2lcl0QhZn
zP!0f9>N$f@e@8u+E(cYs75y-~M*XAhGmLYs`aXRVr%s*01pco2Gdix<s{_}gtwHTg
z+vi60TDr2(q~1&6o@VvVS0J=SeVWcwt?E<;INQ|UKZf3W>WdK=;QQ(sA3<ij+OPsv
zJWwmgz|x^!<OP<8YTX^k>{S19mi(Vx>XZMyc<P$N;OS9YD68d>x|_0pdez-?Agxbb
zM^DmYb@Da<`qiGPFlIo#=XppQR44w3(vW)DmryvY-bshE5%slS(1|DN$z!m0RQ+i`
zggsT?BA@v)^`4WkX-xf7C9Qws>UZ9R&<S;?1i*uu{%H_;Nb^0NLhUt6=|ObRWTc?d
zQBy+s;!c|FUqbd_jg^kXM>NrYVi1mM-k@dQS<_D8VHeG*8>l>{$)o+ram|i7fS=I3
zxee-FHR~I|a#EAGp7LK#Y1BVKubXBK1(e-2;}q}o&`8F?>Zwst`kc2Wj9v~O%`v*S
z;j6Kym&;G{CJVCtHHPyb0h-$%qcTwQlQ(1sX=WcpmriRcXrT|*I3m+#N{A*c2BlC<
z-Xf4N&8thnVhh)tpzN+Q8ZiedA~fIA?mJRrO+XK$G@sG_HCpqs9-|kd`BaO_SdITe
z*c7K(M(2{Vn%{H4a!!+2h*G>JV+bq>n#B2#lBg-BXkL<LVl6ZzYoglFmZGr<p*K~t
zoBXY5Hcj0Y6w@_#bI_QfX{6(Jrlxc^8nZOKcL6-F38$>G3mT(6I4^3-NJX~hLpq0D
z(o}u`mK=@8DU@<G+o+>?8aGOCzpS}a4U(^^oep7FG}+T(VS#2Y`FpNvYREfZsImP_
zGx9Y}KOKaMG!A`GQLHJV7pO!d?Lp-YO>!j=rJ9%N%u}Z6%7nt3nt5&bnaVY@DHowa
z6S@$kTbc&?VJbC#bWFId2|ouzt2F<kNAHfNi`L|7O+I4QQ))Da@&KsSFl_IF)@j!5
z1LCgcbw6mT*KD@}*r565U39xq6G<MmCXIFjOl#J>KLyfSG*fDUYt_6q6{JlQMX}#|
znrDB5+}9LQz`kAMP8YNuX!NxZ)}e8se5!|<Q<M<Zsqv@#4_%ry6*T*FYh1|{-lMUj
zANG;vZw^%SYO3i1d!MH86O6@UO*uX5{hCgieFikUzXD)TlaUR;kml`3=pEL~n*?J<
zG+URW?TN;(9F?P*I@-KH)%;AGhi97RA7I6pW-9H##x;GH$^SW_i6ZCbL2c<GSb9i%
z?^h5<t*aH4PTE`_C_Jpaunpvh)<FewRI6A5;;hX+4;3!jyNR&(n08|-$Z>5RWi*`7
z8q_GcYHyI!?4;J8j@hTQoN^F1?Fw(OxNCntPVb+G){VAxp4#LYu+&S-*ayAd+DcFG
z_-O6ulDe-}L038bwBnm!@z-X*0rdge&nc)FsQuLgRs?B{-=pocb{}nlg0<^<&=#Uy
zTnrMb-Ag;wFfI3Q2n*LbEyGxx(FT(<))t}tw*!_&YK=7AMQQha1bnpi(H4wljJ90?
z601Ezi6C*>9j?$6uU)nTViL4FmI9Edwf_K>N!rgzXtH(#9Sl;mFFXf(Q?(9ekTmV8
zzW`6yZb}5n&>HC>%hWy&flXO9?Y%dFKd;UB6~GJH<t&hkT0M<ywl?KYATDVQ<EYHh
z79K_qbG7B~Kz*Lpo?gSt+LtI<IA5C=50)$1ok<wA0&PniM*XVx*EgY}P<u`YmTTHP
z+G}0ce)=tNMcP)nEK{ttO`=!4M7z`uJU6s9dRj`guhSvAOuPI)C%?Au544qQAJBfg
zLR%67^KWSn#-OrNyPf91+gc$-@vF2um!a*B_Aq&4s<rmCIMrz96k%j)wSQ2MtWKNI
z0=;*&^(|nj*KV+pr48CmZjjcfwRZxdNt;4p-e&EQZ1A*bTkTNUs_l6h>f5w$X`$kt
z_Dz4ZJ<y6Mqqjrb|2c;1p|+X^xKkTM&b}_~(p@0k+Le^-(W7;vx9O2~gi@?~wdV~W
zeOlfp<o|rEjW31Je(nDj!?pn}=OTcE+JtVHHl&?J`Le^>sb2WCN3@OqK;aYZ{@Gv|
z)qY4<bf0Qn=xXpYZJaBljA?VnAZ1+poHuNm&~D=ceo!|`v8O}2%$G5~_Bwa^4IFeM
zv*`Y<qwabbfKECW`biG!ROKig(S1|}*++F}_5$IoYnleUi>`{YI*;kb$(Z9h9~p+^
zgzioiO0K#Cw23~c8zw)quWqL=^!n*?CWH9vJa>UJK-WTt$w1xZtuQS}mxbVsZOUog
z-qpYd>w;<43(*Drj8dp>J4JNEbT84DM#FV%3NfD1Rkp#x2;D~7-9_p`eneZ8&Mh8e
z7_IxB(vo9zJUT$d>g=juOq^~Ct=DIDfBg!;Ib8>NZ{u~WS7Bj-uJ9`mTcYmXJ}6Am
z<!(bUS+|Aqu~Ky3(9R-NmqS?(X}WH5Ii~A2(ZL`?_uT=IOx@Zfuw?1-SEDoMb+cTc
z;)2dL4dkM3CcTZ>x|^Gz{*vwh`RsCZy{@Rt)$OMlJWuCF8?h@kT{sug3UqG;p!TY+
zi?-H<y2m>q^qTHhihf?#MIS(0k?uVc#1!lP`2lSux(eEOmg)v5m!VAO(E;2|U3Wfu
zSguPd1gX%arbERo-3&SlSL$w!pf9&|YbisZO1C=%<c`i3&4c=CUF>2YYILJ?6sXlL
zr=WhF?mm6+;;yb|584`aJ7`{R(s3;yExNt=z_;pF((2u&n=t^Ed%8Rd*x%P#*TLR)
z-A7rF@<4ZneAgX1=Px1bq3(IwJ$LH*;$d2sF3?6j?AEOc0#A?b^$9dS(%q|v&|cjb
z%?W+Fr5#{-tShD`xL+6l21)}uSGv|Ss2eK+8PX-DgAD7k$Dw{i=SK&jCpr~*c1Lw3
zZ2&yg-Mk8!&vfzR2N~1pS3vZ*E>K46--PZ4`R)$s=h3dxUY{EVRtJ3{IRX#s>nMrg
zi2mVK$UdrfJpwD7_3sRU(?$O;Im?gfRjWW;^@~aXIH`Y`91*AVC$@maLw|^J2|V@N
zioxQg-z7)MTOUO~p^tt>HN_u%^(`w<>!+W(6e|4n$LR42(5pAX?m+#92Vf1-mrMu#
zwEo93umtNR6x9pS|Ko;Is9yC86o%=yKLKaBe&#a3&**E~K_c|eZlZ&cdT}t?qV#37
zdPnPbsvs;z|H>Znf5z(h6!MPKi)k#*>K%7O+ByAp%Cw2sZ;QjPouFU&CX7kc^XOSm
z(oeQSWwPGA7b;Tp4U~qRs{fQ$tTg@kF33*TzZwN$8TwgeFf>y?lRQgV`Y)^)p!517
za?)SW?;_8x?V|qQmmoApf0HiY<?5BRtIX36ybbl2_2uh8^7Ww%$iAYFOhBnXf9xWJ
zUe!CFfuV)^=joGU*Ys2J!E#+cM0>6xy^8iA#rhU<1eWN9O&~Y)5kkOA^=awQTc+Pe
ze(jq!{Z}8snsWUP6RfDv4{n9*Tl$<F2(8r5+l%qKtq%$Tuu8uu2&EeRUz8SEs}JFU
zrB1(__C9y@o|HFJuXm^Eu0en56R<SuJ1e20N$*P+7n=2gQFO3P-!T~$-qV-TrRV#4
z+lrImd8B`~2(o+i?azVq>0Ms{en5Ygl3)k*3u&?+($8a}ZCL-sU1%E7-=QV)iT;gw
zC_U4=Q_}sI{!`lRjO+WDz#TG_A4Iq94V*VnaxiGgFXw2OH4Nfp_-HeP9X5PtyA9c=
z3=WGS#?A0uA>Jc*Lpwc)9)?9(u-nt{C=Z&v3|lGI?QQs)oKQZ7@;89<HJopR3O~c{
z8Q}Cc%nX700K-K(_68d2=qwy$P&K3Sw82P28Dcm<&swO#=_-DMFvHc8Hb@IMlu|Ck
z8H4H}N)d(`6yAz9WP1Y`V;H-DwphcH|Bm?v&O;b_*07R%O6LsE&4;FV!)eNZOfYnn
z0-k6%kpe)HVF5+clMRQ%(3WE0%ta~H5VZ;{X@-rv!IExpOrZb&mthEPgHf4=P!{xF
zFl<qR^^(C_iBgV1umL33uyhhC^9;>@qIB8tCV7AJ4gc=JAY3tgWX1p&7@k`Jp;rwt
zBj7AFWRRcvnql8b7<%2Xi&6uM45fbpS8N!jEoO<q=}XFgxnY>&1)-&e%C#V6hC}p;
zr<;aYJCw=|Nfp3X7*=fu{<eV=0a9-$rQLUf;rr?6eWPKJ5)GORr8JbyhUvM0w-`Ff
zJJ@E}zZGrw3`G>9yKiV*4h!22FOsX{fq}mq#MWWhL$}->8Z5Nk=rmk(0ixTmbu$`!
z3_-_W@FT--w0Y?@^wU`O8C=q#{;^>z#liax%Znj&z~FxnrVScS(tW8R!=n_m4I6g+
zijjF@ctmg9s9|qEq&zj${f)L~hC`IRH)b=0(RaPZ4YMijb;7V|KgdDjJleq>GAhY+
zVQ+k52HwH=CoR;D#-4vs>15P*!HUDi3mp)8#Mu2OtUqe}iJmfN<EB7xx)^uA4B~3s
zORvKz<HZq(b~7HIi4M9O=h7t|52J0l18O~uU%?kW#mo2t<zM?6PdB17enuO`Cj5<a
zMUWj}oJIkUKx6bJ0E3JzN|4jW7s>G%Yz(H$K_N!@GDrzC29et~-00p5mNUkWPD5CP
zar;+*M;f1B2K7<K51+y8XrsN2w%swtW6=;3Yn<~J#Kalry$8fu<LpTgbI!Pst}G-N
z9cZFRG)|=fPBJR!+Xu<Ur*y|C#h5^6r8MJ0dhybYGpk@lhVe)?gk>84IS-aB<7D#Z
zoi~==N9lqwm-J;DN1vxT|B_Kvi($(#a?~j08XqxWTb@xzsXdpCuC#5>H@-`EP_7vt
ze}u8PZcM+1wj!f~LZZdSOXTt>F_yf5wo>C|TK3C~+uG1})3}yyG~Y6QMIWuJG%mah
z4Y!R8deBy7wC<$)w|9&=bf2}x7+wOswZ>XH*w-01vLU9ySicBujmEY$=uDHb=Q#{Q
zvr(1`F)hZ$xd5~p-+UK<Hsj*Iz<J+z*&m$k#!^aUe_)(ngSHN19C=(G8t>DNzSB5`
zX0$Hjd^`}gDc#0%bpO4_SWjW9K4T1pVjmk{q2p`6kxie58Zb_w6pTURn{8+tGERLL
z_z~l23Vl5>rc+A8sFAk>EKiN0DpWo*zP%X(G+|_31Lr~0n*UC=rrEEe(%$5!g!K-l
z=`?5C98DWMp#HGw_t(LC#I*D@$WhaQKCn8Q0?D7@Vj7A8>j~2zbd%fF<VC5TCrv+U
zVBsm#P&QcHOch^%xSQs80q$XHqHvn0=}<LTd`!<h54f*s5@r4QnOf<$_cy&vD`kMq
zv|~1EgG`^h1995)az03~>G?pAP}6R54TYITZ$odm>7C;k{4=H>zJ~e;)2dpCi8LjD
zfVOCpgf1n;m;$FlVXUc~i^@0?-y1AvO^axUd(IR|vwMOm_C4rJG=(2SWs=F}OuNct
z(}F^nm}2TFL@C|WKwtF9FdbhDF`1@AA7Fs9Op}P^yy<=Ns9i9PlirJ_gQsC(wrOK3
z$R*PcluDFia_d4{u4%_p7?WpulibvoO`p=PBi}SkDdks8o#{|iU|MJ6qVcNf99=Ih
zG@YfCqU)xwufy&llP~?E#irS-U}=eI9vz}@n0_mOm{QZb5ojwjZ9fk9O;ZRT(#lP}
zqmWWzx=G2^w@f+Yp{+Ds{1Gy5n~G>lUS+b-srin{=P#71O(_O)JJp!%UqP|fBwdNd
zI#ZAw>hGFPt_P_%X&-{6(R7|xhbB`Hg*}^14sWBa#q=dbSXxbfv^ceyMk>+!d!`RI
zqV2w^l-vsKrgQ<|4@|}Mv4sxPX)Q_*P1op}Wv9syO8K8%rq!M3TDM78hT0xeJ$*Ld
zktvD%3caSu6u^6IO6&r#-*k@_nE}%(JG2d(?CGpEViH^fd1A_p2N^Z3q-F4_X*x~M
z&rCDCA$rW@MlQ~A6Nj>nCQN_PTyoGH{M{tHe}~M!t_6?1xi=gL2XoF%$aXY;=?GRQ
zbHWT%9yYgAy2KIl?}<=<)a>huHfM9&_vo*S`J;Xe!ZCC42yn;EMW3Q{!u&=qaIWS@
z^v$l5=I80;bjn;w2TeEgDIGZ7%{RzxYx6L_YX{pr&5P(7gqL~u1C+eY{Wak6F&C`_
z-q*Z@A_sov^-(DKo3EWfDZqT95P(2)z7bXgng4wrvQL|<_JbwZT=WPmA?Dg4kZ|)p
zTA|OFCoPBQ2=k=*us+iK3HghnZ03f=5EE_w>Jm(hG537}5^H9^4E1s5(pHqtnO~>8
z;&^ja97uxs+bzJSn5)T?o@!3pisvHD{5GB4)6LT;3X);gE{DQQb4(H1vdk}&W9z*6
z(jf@DU|yL9eHYE&(BqM9wq2*i?UH%RCRmzd*8h&iT=VZiXv{PJdkI1>n^WZ&sC@JM
zJ>a}zZdnCVV3yo~imT=}+DR3fmpu>oHFH!cEWB?1n?8e9WG?IhXR+Cbp1>0G&*_kP
z!(3AWK&jdD984=SyV@xC_olhxQw&?Vx$r3v73Ni&P`YK_HVmPa<{Pw}-8P5OPPNL+
zbpW|z_8?C{wK=c~nrh5*c#u|W{*gYAT4!Fl3%I-Htk2Nxdh;8vp|Zh@9SmM0vz<Sz
zXfg+L(bjCvSxr&07IWA-@U)umK0!y@%<qr`<(}D@oSXN}>t6z}-TVoh^-~_0qcc$I
zFsD(T?L%`u`I|b;-+utkE^{DlMY_%I0q9bXnL~@jBlDt#P}pn!_%TX-=J{nPJvRTi
zABy_TCvwRDGGI={MZ774=InVOLuNgl+=k7*bf_FPM^jSFQ?m>044#=Q=o~j@{xt|H
z#?2zirkOC$d<#MkS~6TwdC2mh30Bx!W-ow+4wlweV49=lTbiz%EZTm+4_j=TVfGQr
zfrIq^9knEmq1M^5i5?6WOBe+#k6E@?0dd^2Ndws@EaMMATrD%`VLNFV-3XRbmYe^1
zQ!P6WLa)2!C{5iSmayIEgr}uE6g~8^@czp!v&^N%#m8cI02+KPxs%Z)Kg%4-1GD*C
zCXqKa$nqCu(}Y;c1gH(Qw7iH?nB`;&WQSY6rOD)sWiw?`MOZw^)e>nD(c~9pnL|60
zXp6oRDq<`?6EH2-vSufw#91yWVeeUsnqJ>?mW+6`#amimgrNx*iwY#sW;t9A6-gGC
zCtyvs4D!K~VlmNaGSzZKipn&LirlE_mYFk9nPHhrPj{x}eK9JtEYIqo_q;{>1MIzE
z=@9^M(Nb0io3br|A+Ye0WeEibaxBansLZvrlJ7dtvW;$+Ubfg?^@o^z%hl^>ykc>X
zqPD<t@g{^`wG7fMUufC26qa7IELZ`S>z3D-0$*gg-VG~?EkerOEwLn0j`a=8E`I<@
zElcSHRAvd4fZVhctbu9emW%sfT7~7n?*QDgG}2+R68B%<f|%PDT)@H0Wf`UI{vFGD
zy3bl|`Iz$SYb@WL2ENvk%!i?M7VEcYYqBIgkG2-eAL+2E)#Brfwl>RWv^d?fn2R9g
zz9oACGTSYKv@3jIiP4~E9hR1-XnSbcri9vFi+2L;KOb8h=*jQ5jCKP*U}2|%XV|jt
zI8=;SJjg-(#1carj8RMXH&Fl7l6?p)&n&UsD2-WWc%yCHa{fz@2}=mg*$1sJ7yv(H
zO(#!)z4gUDR61B^(q!vs{e<pRI9cn`DgJQS8d?c!j#$6_7ebF(Uzh@eovm6rZMaz5
zSEFmktSkydAGbD8qR$EIR{C6(tMxpk!JM>qz6jZ;tm_1*bhE0PK-{g5z6adHdSD~q
zo>o%@D!r_?c0r1_wU;7MKGq#FI{*1vzvP0)&$_G=#NX;cT??>|Zh%dJ)-7>R7-X%R
z1pH~M2Z;%`-hBkUA=a<gq7-V){tG0`+Pf8%;nwc|4jopj4y6dICJG}OX%*an!YC{A
zIaEel`{fWFW6fuvpSD=5iav-LXMIX%>9f{PegipYy}ua7#9J@WyPaUQv0+o9^{_ke
zN!E>QR3=+5)<9^AwK^Z_Q?1fCw53^B(pRn1tqJ58&#*3|fN-X@$pR~~tY2M3>AZF4
zcNl~V);#j_Ub0yqD?oFs{d>@uYhA#Hm^^D2WpiJ){^Eq*=UeShfaQuch7QpM)`Bfy
zxoS<YM=uJkuf~AonpO51Dz95(N5E2K_5BW36k8YDp=TvlQ4>lxtP3b7ywtk#E!bOT
zo%Jr@H?6j<R4liye-R2RtoP`^dds@o7o|$;p0|LwZGG_}NR@TL6^OZG4XFdEwoVwK
zu*S-EMq90QRv@I*S&tS#{ax#C9bl=qHf}{*gY_M{OVwztyaJXcYrX+2%~k_V8!grr
z8^uOitvgbou+91@EgkLFk9e@{fpzWM;OVeln2ENB)=lI#?zFm6UT~K+g2I>GR!cL4
z_E>YQV0mPnorkgLwSHEFQlItx-%)yO{bemU`>p@H0ht5VRwuv*tucGiHe}uKz=jbT
zwl+mW%!oB{8d#rLACsk{R?#Kc{nXk=zN}}~i8u%yvpTfGigD`>I^|4Q&rrzvpq+%W
zh7Q@K2cy#7Zitp62Rn5DDjn@QUV$(tJ837R9Jb>ffE7pV7CNBvsNK|5ioZMCb#8_x
z7rV0*GB{?p_XBkMxSgFn#GJ4bk;~H6Zr8^sowWO^8wyX^U2=pbH@kFlY`fcCpheun
zZtWmsd)giB!w=(Sw?hP+x82eqaQfPL(6<2m>@F+^i@zO1fwlm<Zk#u5Qv&T=(qUVW
z-9^fhJZ-n_D>Me%t&RaA#BMTuG9uK@@j5EQ?1t%R8gBRK94gP)Ws<in!p=Da3M1`a
zq-=>OyA83B5^Xm}3zir=Sug-+?QT<M-Z{H3$<Y&UH#rFQCfNP^8dz+Jb_tYHn`HOP
zMOd0__v$YwrP$r}22ZM849&e6c0nfr%(UAbhylv7yLkhg7w!Jf(RIglS$%&Srlo0`
zmYSKBR{mPH%u3BPZO3Qtz4ynaSzr6GTnuF?L)joIf`FicATk7GD#(y6OArMCWh1}$
z>96y;=brOE=RTk3xzD}locny-X;Ycy)JL`5mz*{}gT8F1#dIHEcG^y1%p9jd7pUht
zt)<Xxo|EG|`tqF$W<u|Z)3(ncQs8j<mWn3|ohIqiCq+)3G_PNEvb_S)VyCcR*e!8V
zb%T^Tt*U|DGN+$tfnV<AN?$sxaQfnHNM3V#Y8LdaJLS^5wbJPw3SLz?St)FL!^x!&
zt!k&&l(10aG>fK&S||1wkgRiZ+%W>}rqf{qn)Ocq7YCUJr@nVU8l8T$!L=r*ok<|g
zPJh!brN!wbst##&y7wUzZaJO$3Z%`+YcD|Co&KQgWrtHMop|VUnzaK8T~6E7P`~Z8
zkCK?(PP$F_DSDjpXq<PPesjDEZm-jpDm3pp4QkN3=d>mkKJ__mpkPD4lZiI7_nq!<
z1{rXwqZww<>B##S_K*|*B}hJS`r8H9;-OOzy+DSYeilJw#OW6~?2bD1{0zM@r%e<j
z9C!McYC9*KboAAZNvFp)P;h0+X)$FXA33Qh3OkK^2hKP%r0qa+W0YQnqC4Yc49Ffv
zHN_+LGD?4h<UYoUjcDy>ywwUX4ltgktc?fb8tsKW8SXT(c`*{{5SBONsZ{_w$hhzT
ztwW6Osj}6FQQc4PKVL>VRh;=Tw3LwcXXHc!G=S0h0$>g^7SrLCBMc@T^$TP?H4i3&
z7=KX~GMJIGAFU9^cNG3P%J}wQFpn`Jo`hZ~V|gl2!Wg^h*$ijIY=TGxV}Nq7k&Jvf
zM4}jmajHLyX0WMBGKTSXB06IkF6{t4&X7<_Cyp_bmNF+8X(P}$$(XYXeWw|3`9mRr
zF`r(siHy%F*ms5zc>vciiDCAJNHXKIMHpcULvsXfpJjZQhgK@%i~0Cr&M{8?4d!`9
z@*i-`ae>i5X9Uw3KYjs&8I0%}=w~vzrl66<IC>r$mlz#1v1T(`ndrOB_~Hx{a~LDE
zs?2AM3LtWY5q=(^1&m%g7GB5*^+2nLkw#TvR~f!k$WhD~d<AZoFa{}GTgsSCE15C}
zLqa>`a)xpx3|27Spc(2K;|F>Ut~1`5f{99oYb*4t7}ranaf8uc0R3u4+5bVZhB34V
zuGKO|H$lCQ5%LRKHyJ8gWz{np-i1g5L-Y~)8W|VP1FVS=x&?jBjE)(=Y+*P8hXLBk
zn9#wuTa3eBK&G9s@-e`4FrNMg<Tm5IFz9zPUM+)052Ggs`ga&hS3|FtafzamcNy<s
zmo)Pp!?X;oK1O6c^!gc2l#aX4xJ3cE0fws|+#Y01Gyv=&BPR`g!;D4;9bgz?w9<n+
z%J`gWpT-#9(?u9()ck@UW`gk^2iIbfv1b_+rx>O0L-7$q@(UcDW{l9Y>CF7~7Kkfz
z*E8_YjVUOBf;-bO29Z6?mn~4(%Y1ehEbL=ud&7bc^C_yU@MZcm)B4koSxTkp{>-BZ
zFc`pWzX<b(nYjxA8pQk`<!OVNtS;z>FpGW%_EBc|L-ZYE4*UekQ087rTZS>Gk^mac
z%wmEW!StfMV<a<+)&fyXUOQUR%tWf)jbXkU4$N4lp^Lshah%yjiJBy4H)ZpanNE*z
zEzdH;8Zekt=21PEY0M93FMW=AaVadFXL>#ba)Bv-3)tz*+j9Y$!JN^BL0n{>q(gz3
z%!xlClEpOT!I?`;!>16*W`<C#?=o}a0!ZdCcOW$Dn3>Bo{FlvO`qQQ(pZR}u+Vcu?
z0WC!en5-RuDP$&6c)W=D8ri+deD)0bikZ%C7*h#zM-2K(nLBAIQO2|{1a>*|0%dzE
zn6J@>{u=WqO0ZmK&V3dZDw)4dK%|QKC(XHz8_c~0=&WY;;HH~d!yM{{Of55DAv)`r
zgKvO&lbJaKX!T6fAS4@@)7j8(W(L#hu7z1r1!gNVNd<*l%!D9Zt~Tbp18}XK$(aMv
z!Q7DnW+!vYzwo|`nMa3oZZrRI!IkNDFwL~V?qM2eqPfF7zYe6AY3>B`F4NB)*!P%S
zU&CM@^LdKG_A`4&VCg=SUxC&DbNofPHpqPAMckc3%x$h<K45NXfcit`Q?%|KW)@Py
zVubnNSM-fC|6U0%#+b*Rg~B+~@kIs3JHh;b_7IcIK6jX(Vjg)MosXDvX;V4PJoqyd
zomo<<*K=XL>xGsp>*+rs;>KD?wK482=}s{Bu$EAid@n0x3q0J%IuHn^2kUGF2I0x-
zX@VDCtVR*^yjiu8&^yTb_`mAtL#$VRgNzTWHv$HIS?gDU__6+vHgNu|L<uwkSexDh
z^Ds+6b#F&lYsq{dD{c%Vh&4@h4#BLQEQ}?Dm5~PKQC8dvkYlXh>9-GMt)-HYFxC?k
z%MEAwQ5rCU^}eqICL&oSR2UV-DtH|ZN3&i?fMN`5+Z|}cvIgrgrsJ$TDX<&Ix-7)y
zKEYZ@%ioi%Ac_#3Vr^GLB%YN;@wL;e1QonUVBMlAG?B$y3JYggv!el>#8O{|`DE4x
zN?oO}=DSh-^;y<QS|Oye7M}-6W5s^~a*kC*8-(+$nXiFdV4Y|KGo7`bm>H~H{m{S2
zl2T1UCM(1M*RoirC>wu?b(aogXS159F!wSmoC#-gSPOoHLM}_W0Os>pY+C;2vp&PS
z(J}K1t9%mr1*~))NFmE-4`hm1ola<7Wo1P|w3u}@4rnE;t6P9w%1X|~(8^d%yJ7ws
zYq%7xDpm>YS8uR>-3ewj%S0KW8rH`j0j!qQ6NT$k$GSTVXKu0-N}$xU&fG@J(ZE_}
zhlxhkC~cdYSlnJ*#Aa6U9muq>{An_2Wpz>!!Y!8Ve}HLY)$NC5J1dT|`5mn4C(+l*
zS}g@y7i*ZJIJa5fFT=IyW(AmGzK6w-Lg5Z8n!=~OtdFK4d6)HP5Inr+V6o|BWgjaz
z9bWXaR4y=hpSAomSQ=opJqMXVR_ZibL#%Z)?L1(~s-XXnRbPbGFzZ+(S|hB#nt?sa
z;!;F<jMcgnedDY)s-c}=wNMyyl689?EKISC6jFM`nyQ1sG|MrYwy4f*U#hZlVJmLK
zZ&!Bp&luAlHj}EQ_OdrD2ieE|j84bxXBSqY?*O}$VvQc`4?hRfoBetpL=Lh8De`!T
zeW(w8e(aG&xEB6w)&jHw*vkdDqKDbfpMc~M_7hX+3uG^Jq@Xi|{W>jwkFp=lK<6>G
zPdz|G*>@=_8OC=10VJF)TmtL}_VcvAh-BaV0g_Sdk7+`WW{<xMv>0~se<i%^nY1)M
z&Yt}RMB>=iT(nNGzoU@<N%r1vA$f|OxE-U8XYaW|@4wURY&t5Dzz*xjrAcHTqi5_4
zyZ$n;lh`GlXeG0ky#TZnw&E|4v+U4#=%upbXm^yx{&hKi=5uTd{e<V)iS!n|z#gIi
zRXRJJ1Cb2&m$Y)b$R47Yc_#Z!TCQiYeUm8vcZt1g9=O?T*Dh#WX4`u~a@aQlL2}tg
zw}Rxcc{G{ivqdzeU15g>fLXv^Q~}ot*-!R@S;WqyNb6O0JiShe*&~$8EMY&SxwDk*
zcMs;v*ypLBshoX*9)}9{14RDt|9|X&+u&Yj%c%&clHC@A&MJ1Z6((-5?eyiNYBu`<
zhE~JQJ_cqjdq*!s>e#!e!u%$C(+9Yg_3Xwbs5h{iuft#?`&WAIo7l2{;dU$Ajf&ZB
zv0r)u9=5Ub*8;Phy?znE935<LAKY`D?8Zvycd<Wz64&B3n@2xIH+uzP_ppP?0dt34
zK-r>Rb|tN7?y`fH1MME$ZU$N(yD<i6{p`mnzI~q^OC@dt>;>P#nL+j+Ss+8~*rkAe
zz^<ZCa6M$-pp)an4)%3Q*^RJgy$Z!qww4y*W9+m;Ami+r6!@HA``?A)BztQ!B&XQB
z>0W)rUg(9sY4-9NkaXr;m<gX;I8Agc$CWexJVe|$XJ|v>&Y4NCg*}|{9@yQ>`IZN;
zeH`^IfbHkt|0ke-fHV0PG(0%zXVB@%QND~$FV1obcX@NFC_Z+O^Hn5F9OCp%1Js9e
zr3(J~a*B>Z!H<*r0+{}strWQk;QU4rvBR8OBVZok^yWb_kfWs9-5^f70?q_;Txhot
z!f|)d6mgW3L0^YB#>t>Vy`h|?Z=e;%NoYqaoRj%EoQdGLWP%yVSrZGiD2_b@Fwvar
zlnp%2QBZUvj`P$bT+$PqIrMACbC_}HJI$$h0wjU6j^@B5P8Pk{lR3-?xShh8Uf}@u
zEaz3)X{K^wX-Z4uJXZ?$FK`0-aAndtF>JIlIHG4@@FM3A+5=>AmQlJUi?fp!fR{J|
z%Kv3^m{bgKne!dZuQ{CD?QlDn6Z|#&&EpJF-Z7tZm~uc@IB#nqQov!fQvF#Wr;NhB
zMVyQOqVp<e?;T(lb7p5lzl78E4X{f&xo)_YWt@vIL!_LeruTgXXZzRayT;Mp!|1Pb
z@@g@NN{$;HiLBy`=pb@~!>>eNHRt~*pjN~2p$Jbc=ZFn`b(~%#?i@33a-3;@QqP&Z
zfzAewl$KYGoFOW#Z{i%LWOFlTxfP^^vw`lbR!&(I`r0|xXbi1`bBx}Not%}g0JMwq
zfWBONo3oBif_8HvXm`}Z$>)H1hohwsX)ouM9yofJvzBHp$34!E^x3IC&d-l9?0$|f
zRp#F3>?nl81DxOh*d64=nP6#%^U7vOKHyYP`r{$zJ?b0gyia%M2*=}3fR1tkB~TyZ
zH26buoU<kYeG?o{BcLZaB@ciy#X0x`pdWGGq*^T(2bV)f$y~W^H6U)>vG;+!mz&mw
zf$rnJu>qj_xsQiI;{dm0EwDYfFP}l5C)fEQ%zJUKMFGZ}dq4$|gWQ#KKn`(t4T0&y
zt*7^wFZYG5u<OVD<QM$P{@nK6@F{@n^#%+b<~pudLG%b$xewexuJ$jGAnu1Wg$Hvl
z@<BqlZ}z}oD7WHAm=ELb@dRi%_a5C45nLPX(IUAVinv5^SIoyiqq)EHp%B9j=0GHt
zn@<Uv<J`|yVt{en6}52Y1ot*orJUp*bF2aP6nFm{(2wU927sLAejN#!1n!P^Ad|?Q
zMc<M;!>yy5xFqiKui#-aS4y#+6z<|D(07&_NsISXpg|;!`;cC-=eV~h5OJQ{Itq~s
z+!rIkOy_R0Lp_7LhJM0}+)6do2WN5{9*5m5?lXaqxy1FZhr`+20@@f{=DtWbat_z*
z17<FFJIxz;+*KyP<a3{*&rn?9o=S#f0e9KAuvEw`%SNk+n?PCdtK8fcKo@fZenwvz
zx1S=)*SKHNak}f=ob{CdtK`<u8=#8&ng)tDxG!yoiE8d;JD4@xi*&texzjI#S;zg1
z-i<f8JGP>)k*lILOcVEasyb@sCQxRzh5O1&V779<rvSz+u7HZ8+qfQ15NYRrPYJXR
z?t+K-VLG`YoV3OF&$!d{KI-B2)3WXk_Y?Y=?{P;z1nJ}6^n=6w+;*B;2Dws-&JS^)
zTmtfdd-O|)jBp#MYIc+xHy0>l+zt2P;UqWj3i_tF-Y<eY;)Yl-2p3*I4=Ap@pFQA=
z8;{)vNylDZY#pxUKHdU1T%rBELx<4v<ULP&VK3gSPKbK*LT1CD4{uH|V0?N1TLgoC
zyt(7(JIwou4nZE_ouz<JAn!cQwjsQ9EBcP|{vHI_G2RxcX$$AQPSrmVJU_a1B6*SD
zK{Cd{^JAbH%Nu_T=8y9Z&cY~8@@Cedb&8jx0Ey?l^d?4;$lEvxFV65dzVJJV_tk#1
z&hprQz^7E+f9H78c-?P8;R3H<Ci>EODer=0@YWB|-Njq=-&UL#bP8bEyh{;qCKvT5
zXVJ{#`BPa~KChCNe1*J?Tj5&~&nE=VT;=Ve3|J}eG==c0d5d>Jv4%HJ;mlf|!j0|=
zUN#-~y2*<O1hbJhp8>l~yjTi%HS?}`L!pH?N}oY%<%Ljc@)j?k0dBYP#{T>Md^>MF
zEh0L2A76leC-3mzFyF-s+k@6^ULNJOdU)}rXx-u2ERgKwm2CpdUET}70`wm5s27Ia
z&s$72SNC~ysh(qim!1m~gFGYcJBN7QRKfUwr&$5L5nhoBWRzzc!WL-e7;hf!vnP2z
z^kv5>p1T4DAMxhDj8QoAr>{fNg@5cV_~gp}gK{cv{L7!B&z=7Xr4je?H8UWxkAH+-
z^!xcY=n&%pz9a=;9(>j&=y~%0p;(j`zx)V@H-G1=P(R4;&{O^AA^xw2;kOTe%g6A-
zm;cr$kn!W!eg;ea{F6Mu1n~cz1Lk4=l{UC`gg>4HyMcTcB}fqeAIg3P^G!?87s4-a
zgJdY*jqaH+e)0{N59cqSL}e8JOA5b6^I6Y9FNVM54SN3K`0soTODFhKLC`<RKfVKK
zr}?#XYAk{O{#zJYB470}V3PSgUjrtE{{yXG&+<zsl75bVp$U5D`GH>n<pTdG%{~|T
z>nYfm$zK%)g)Dwe1w=0M-=Vl%4xh=u#n0u>r?7<M3g0CR*aiG!^xPNnx0ge-h~HTa
zFRt<r&I7ZU|D+Ypl<?<SfL6*+phvun|3)}0mGiUThDZhfhcAJ4jenE_FDm(~XiHqh
zuX+Z0H~1A4ORDBCdKRRHzncZgT7I<_dUX!|tUVB|=QoAIiw6EyDkE*=ZxO(YCjLK^
zK56C$Q$VkU-%8I>E5DG^m$&$LH^7-Tenu(=+Ro?FMA5;|4+XQ6&-MiA=I@}Y^&b9a
zE->%#BRLrMJ$@vup8NP=-C*|f9p{I^z0cRtvT%T(y&7bYZ=`aiA->xx$UNXLn}8P&
z`Rl#`bC}<`7z!i&AJ&14@|je0IL6PS6N=;fKTK#%@Led+I?0z#flTp_pMv*~_}g4S
zrulLz@NpKjOECx+!P|~jP**_|%}{Ov&2#8<7o4N5#2x|SYPh=v*>u_V32x2>+J1qr
zJ1iX#jL9JBAsF})lAeNp=tB%%f?ZVL=PmG~^!-7>A$qAD5*U2Y=OYl8!ZlyP)p;O(
zf+uKG=P!^o(eoD|*mMyZhXwDy4RS=VDi$z-f>$Zi7$oSTYM5X_%8R%NA%cAguzOUH
zMZvyff_SR_2^IWG@2@a{mGbZ5f=}tWjS!4e*<GaI%(v)^5>)>J%xJ+Mw6l#7B%DDj
zR`APLRDX6{kYIs{IKlkYFmXa4r)le?Am%6hu%`q)LKut}sAxlTTJTpBm<fWhwZKjk
z+`S0wGlJi!A}~qtBE@@?1-cJ_k|HRgg#TGV;^Szg3Rs>%IWO2iNv;cm`+tL^3kG9n
z;`z%Eyh)SpMZt4fa6eNpL7rv_@K9haAaI|Lfo2O%(1Ukb@F*XWIf6MZ@Hbbmh4#C7
zg8ADZnJ@5v93oc)JA;8;AYk=_Sty7*2lGXOr4$IfDrkBH3&nyVsthU-)KRsrqg0T|
zglL&yI0>X&F#J9AD+CTH>|PVxqom?>!5nvJR0@8ipR!7@;YSSZhJa1`uxdenHJCMm
z-{`v+wF1cm`sxIK(|vJM@XiP5s~2>?0k8%^$}qqh1*a)5+$3n)2cKFUf=WANZV6PB
z1!)ru(7vW!uwooC9RhnOOmqq+FM`=6c$Yqnaa*uq6(qX_HFMF|BWQJj<Q+kID44y1
z=ct15u0Zk&26|7xrV|f+g3WmtQoo>s@-6oT8|kGuAo$?`BnJhK2W<E~Bsfp0(FXz-
zsvCbOSn31ch6Q?eXp9JI+u`A;V2CPw#sncBqctw*rRvuSfzb?0lY*V}zjjjs%|?Je
z61?{s$h2UP>V2GrpVM#WBFyo_C2<vc;YXk8CKNEB;4XA^Pz~=M;YliR*ekrzfl=%e
z?z;}3_6xUB!1jR9mA;4KA$&~@eNW-CV(5DbMHx`=7G?y((m~<II4}<hJ2rvoBOG?Z
zczuN{C|B(#?C6Jxzwqac7*c?6NfJa33+K>*+atooUs63~pfHj4yFtR8@$fWQ=tf0E
zA;O<!aPg?{ER_}<6F%huM?;0FRM`+F%=sLxaA7r-kwyrmRNEaXtf8-TMG4)0Mk`v_
zxg8=g!pxZ<vBC#bsCrzOF$l0YVdp%coD#nGJ?;PEg`)M~o)#9+cdpI|<7Z>oNy2~M
zfy2qdZ)mM}LD(J(k&D7+ihpJbf22f9mhe#)$R*(<Z6&gWUax>$7QXj3+|CicMls}E
z;buCdnkU?U4VYJivE^tL2-jSNhlRrJ@wERd5^kRX?p5L9E?lo-VcU-oEfsDU2eVB0
zXg5Y!E<9HZ^A*CWR`gvHrqZ_Ry0FgzQYrMN+(wn~ksAhjL-^}XFsp?r^tF*1;ZJ*^
zP%Er)0a%^zjo0DtP2rlw0IL_a97La^K{&#IiAJH0zGd7bEN@4vSr|f<axFqFtruE_
zT_*r~OIVo#58H$h^ux9b7f`C9LpV)8TBq;{S~_(Jn_bYlEqo~gdfmc6s+jH(%6>xY
zuCR0%nD>OY;vm^4e4!qs-y!rk4&UwzcT@0rK=?H+LkEQ%DoGd;K26br2f{|0XdVhv
z%E25KUg1JvL};1=pGJi%sHSyHm`@e_<H9Rzp)er~q9bUN!qILpr-Z^ou=Gf{VL!;U
z@Cd0piylyD$W7#U?7x+iD98Z2dqfX5L1VAz<Xm*_6Fo(_tNo&UdYK;(t$PAP^ALr9
zhEaHms^5eqFA<M&D&C@*bUgH+Xvb&JJ0ud*lkOwBc^?YCqOcdC?kD<Z9D4que?%Yw
zqU}@?dssB>utMgDXf-_@fg*zjib0~kKZQoH==TR;hKSZj0Q9IxMnCK^(F>li6e`N5
zkbQ*c4Jvqx6g_K&UX<uWC%|GwyZ-<=F7n+1g*Z|3SzNqRqT44S5--}KfZl1*t6hLT
zBPy(=_g|7|K?a)1qEC)uOsOIrEtu0pd#SSMoM^@v3|<g@JO`H2MMcj-KSNaUBTQTr
zeMH-YOwqRWK)EFPbtU?;MILk%`m)GEMXb4^;8v*TiMG8B%zRNUMa!;;vZ+L-Ks4h6
z`u~+8k+mAlt0H$394;1R9E06bQLq%PGSNCJ{wo(9rG;mOXcm3#?wV+EBmAutNroU<
zCGw}7<PA}F1H7*m{e2v*8d2#7P^cAsv<1w1Q3C~^8$>(*glml=2kp3;M5kfaF|%2;
z>JON25s7I>(kg1szz=jw^z}lFuuT+4%auE#Q*)uwE81BOa#y4q0n9y7J0)oPL{79Z
zzc1p=hHC?&qs!466g@*{gdT`y9)|jesNaFUQBfVen#V-L6m1?CEzLxqV?v}#L+7N(
zdJ>*aiGG>^^N&RPC{-~ndXnZjXYpKG{JV%lUx0?I_yaatd&L{*9kov!uo=w#Viw&c
z2gH330p=l2_XdimxQ>b|y~KYHz^=DAonqz(#igeJ?JxfJWsm@eIPC=t^sqQ!5@<)n
z!*t6BiZ?d`G)O!^2LXb`Pt(RCMBG3r)uZAq-vcH>yo)0Dk>c79L88PBS+E-|Ub-11
zMr<nscC2_SJvhh3ehsh?Cw@u=azgxR3x0|OaVuq362%T7rIOBw*UyK+B=O!&FrO^`
z)(U4*#Gi*i=Bzm63KUbtUv~gBP5kELFnB?{Xcn;3#l0oy%MdrFqVJ-(=VPE`itFD4
zN|t!tcVJ!;hwp`Cw)j>Iz%Gm1nxT**w!aIMT(P_3Wpw6=k3ImmNL)t|;;Z6|eCQX8
zpN@xXCF0E47;mXKRR^>(@y9eXm5b+6WkQ9xd=@~ji9aa^TD5q^8vv^jZ=;Y>tvH<G
zYjxtn$1vWT;@S6sSugHrg@+B|hm@0S6hC#<0TWH)&`Z#06Ca?xTDy1yt+G1AtLcPD
zr+8TjNS9dr6Uc4xA5=HjEzXpI^oaetVB(IrgZ60s;stUr?~A9Y0(n6EOB5^(isw^!
zZb-c8A>4i-j;4a`hvFxHfaI{a>vdXxj)*^|m*cp2-fVCu#Iq9M)1>$aE$gPlgS07p
zByL{~k!f*JDbSoHUr@x-MWXo~BCe9P3nAhrQ3-+VF8OU2$R5dCRIlS9iHk(bQ!>^L
zJugZ3N09WEbW`N;poGy+`M*Pw{0(s5N7C&BhkYe4HRD?NNxr8-<Uq-2B8D9#*-rOt
zu;l4jpoK^l21DVfMCJ_h$0P|xV24W9%Ap=65iwvQTyl651`#8<LAPG4<PEy@j!XD-
z>%~cyQdP<c$qy}1cbt^Ot3gjmRyPACUXn)B&S}XD9Y9N#ykLMADUz>`z~Qr!b$wu_
zN|<!wHcc{b5|++MzWYBYoR`#yfO0|7zZcl)k}r~AFjG>M0QD?M{vEU~Np{i7I$KhB
z7Ydgp%5bRXI3ynXftD-LUVw=_$;?+l@+BKDW4u=+3QGSMNCGL$Rw((2PH~h<LQG(m
zN#->Hrd*;b#s#X7tdqmiHOXFDSzMRoQPQ_k!j-{9mE`wyVAe@~qxauU$zyvUQZH$y
zI7WlS@w^hEjgoUe0<B5%=^#3rB@t_(*di&XRDFjeItbXEk{BwL?vnfwO*f(>cnwIm
zBq#--J(7=U4RS~FdJfckB_mXPdtb6J1;6BgWU2-zgAyy91sReQt%jiok^(NwK9qdz
zaE2Shl4e>&j7VND2h6x+fF|t;N$k5IlaeTkZcIs@pt#;6$;V&gB1}t`$l%OA>Gpjv
zv0pk62lWF|4rL5Hq{Y93cuK`Lq3$KM8X)2=W&HuW2c<DLA$dspYBUV_NSD-5{L@$Z
zPe0K7q^17w)L$B#4BrBzD=8j-Si15UU;?G)V1NcmoBjbzu=J=6k|EM>C?IfDnnJgH
zsB|e!vtiOis=N%Be*X+4Bc;6=K#7uO(`Am9&Y<XRjC95xNXAMJK27V-6Vi{D0sEwM
z9^DwHq(k)DkCz4+0D4-w!VSy>>1<lMB}%`g1^OB3d@`RTU9<wDNRgJ&it((}|4)!q
zsq1UdOOsAeB;cI%;hP}mrGa-bh;*q7l{#lgZ=0chQCftcj$>w~v_%c<EUB2{3YVno
zs02S-sw;(0m!*y>^yNsm(n2m51I5M9lYU5h%Y3PWDh#ejSKb3DkfzbBRVe+IzBW=M
z{fHv1SEbIh(JhwVp&)&U^sN?%luDInAyOtCe;3|6%B3ICYNtY)Oi}i0(%CD)t&-lL
zY}F0vDa!g(OA}s1UybzX18CJszi&rhopj$^jG|upWd`~hr0pFTXruI-5s)US7oGlS
zmcB_FzZU8DR(N<z%B1a7n{>@8h_p*vTG8rsNK+32txH<Z1^2czih?@b(t>ti_ek0C
z=({7m?}btHO0#JHcTYO-B>MWK?X?(8zjO`FTKA<jG;It>pV|qLA!*oIpgfR%w+Q5+
zw3ZeD!%~k0FgPNW(r-U1eTho`C!~&3E1)<jJ^ecrr=+XzK=hGxmJ?dj(l_0q?<~uD
z8!Z>vdwbxFt1NgA6x?J>DSGTKoAn74_Q*nm(6?8%vlxB*WM$7oVZW@6F8%@83lvWD
zkj<b#tEX%hy=c8;f(^Jb-m)2v+fY0x^P{-WAz3{on|)->hhf)O_VR}yezF+~!1&9K
z{{e>sWc)UmI4twq1`|hQhA@Bz%GfW186@K=ff6he_X9gbCdvdkD(jm8$zw7$MTkOW
z_D?~=WYY(r7cQHxp*Tu}Z1KmqCXupXI#?DZbEcGCw5-Mx&cw*#=w^+TZQce)kISB;
z7<8QMpDmC)C3|8a)Z=BYv|~Fh6ElIGAanBscB1SGZFJAbc=I5cB-3oiSdwLvdx4T7
zi>1ZgSy|vX)xV_56yHHKO;*r@&U3QoFJUm}Wn~mszaSf?C11L1j~SOOL+0EDw2QLW
zK83+d**9%~$&!7^Mc*aaRtj8Z%b2ufx-83~b6Pnv`}^=dSN4!9IPzo)Ds9V`&7!)|
zE3$u&(Dy$JWFu4wQYd?oGWJC>#S(aNRpv>nyJFcAO6QfxUZDxSRJNKvt5PQ0{Tj?)
zlLfyEa$VN<4!p0FP15JWt7IQN3vxro_y&^IvQ^n2HL`(lpw!By>9?zsJ^BG6H)Yo*
z;f14K_VRrEY7Md{De=%Kb5NN@lPsU+{ASrp6kBbP9jCg)R@r8H@7|K#q)!XC$sYR+
z3hlBF>G$c7byDuAQ^wl`W*163A$eQ2^aA?s$bLDCR<CR$mCxLjg}(`rd$Q}hfZ6Ae
z^+dwbeVO_b=nu&1DP%Gz3)%$}L$aU7Fv172-JR%rD0`pI?2O3zhM+$x<504BO!jy;
zM8;*l-4L0OtuX>@Qa1GpL>|d}DQ7h;+x;~#o#ozMAg=OqihQ`qk8D88UG6Z_d8<A0
zp93JeSKdvzjs0@=Wsn1M?gcpPAzwgI6;HWo8GQ1RH?ITnmUo|q{vo+o1Q8$k!gpZM
zSAKR5n11qu6JYww4dcKJkZ+(E))DzG3L6E=2PtD0Bv0UDEXU-p{r54rQ2E*~!3~pt
z7z5wJ<<HYTAws^64qQaZLulI@EiY{bc8vT+KG0(2$s6F|aruu_vlu6@rfSd=@<e($
zos#dScXGVkHytRa<-7+_PmnJd!yppnoxxB~l8foPp~><K;|?gM$UmZio|Utlpphz%
zli`x2$!!r(JSYE$D$LX6U(qHyLtakF+l%r5iqK}t!`^^imV84cTG{gMjqvHRJaY+1
zj@+4k-(2~U6)>15*FFL0e7QOceFgHZ^rRNbzu!XNzb=w*Pe${q+<h$!7Rx_b3WFu`
z&#3UTOrAtfMY-HaCHxig4S%9_U9O^aex-aKRo_*~U%8E8-;ftk9HUzP998es%0Ed5
zsgtj}4auAGLL&8YDeeCn<jd&dH_Dw+<%Ip8{Ot;0x5%|K(Ag?ap;zoJc@%9d+T=Q_
zIBS=`OOeY?dB}5czf0b-3TU_GPjsNwD^L6!dUxg52B3FOuAt-2eR9z(DD=x0Q^03H
z9)1B}gYp6@h#Hdb<bynrXa5f<j)(G@^ud{7`5-ObM&!FGIyol)c@+jaE}#82T$_+T
zyAotl{?=|Vr{uLKpfD}}^aB`lR*Y7|Ll?y*svve%Oj03;n?e?V(Yq^FV}vvJD4wSs
z=6=QN$6(=rVv8?CJQN&SW_UUjN8SbXQapVV8s3WQy^uMmkZc4wq^PBnvp$NP)9CY6
zxL3e6KgBVc82uHBCSV6B>T)4@SaI%Ow2mnHuEMoI#j-xQ7Nk(L!KYxw4k}CvQH)W&
z>rqA964*PY;Fh2js&KT}Fs3lYrk7wMT%n^pc!Xla8J&@eu)on4r3j_>ZnR=$5lD>U
zEvh?>Rs2GEfa8iq`H+lL<h=kBClp?CD4bMWd>xLSQapMa-p4Ec$${i)1%n>{1cite
z=!uFRS`432v^okfm?TAFHx!c<r#3?)MKSpoK+h_E{RE<^ikUwH?Y!by%FSO;l>7k6
zbVV0E+nEXxWl^#eJo*VQDZZe>iX6qo0$ht+g(UzaPjQ8o)CG#)>GfHtm_u8TB84&*
z3MC5Przrkes;KxJCdw3hXu*3;;h@y>bw#lP`jv{}R9u;AMQjXUY7{+`zpquy+XDT1
zMUyK;8WdkH25D6MwiY5Sin0W#w<`D_0PL2+KmoNj#rzTY+pgI2IP7&O`ZmJRP6hvI
ziobLz5?5kqw-t|*-`$G0J>X)GqWCE&_9~oX(7LO*_AWH;DehD7tWWX03~2p|+JkUr
zKyhCOy+H-<Nhk~{vY&$82a42nz<j89)B|UR6~C&{H==lVJHSR2A5uN>n4&v@_J8Aw
z*}uZ63B`_bfKDpdbgxe-*7yVTk>YYGM5h&17W6qQ3x0!n7v-H#faa<!uZPGUWfgrQ
zZLjia+6(Vf?x1zxer4Do%pXvm(V*p_OtL}JQ|WmYl3vQ_-vM?|$)-h`<B;-k3YYmP
z`2tw-RVwN9qn~meJ;wgZ%7u^#P<oVt99F(b4}6ev{a5G<R=!Frnh<4SEfhkPfm09(
zQ)X|$Si+UQCqW{V2aljHQfa5VBwAT94)ZZeD;2iKDxd!sea9Wj)t{j=PHCY%(+Oop
zC|W0#3qHgMPbn`_WI0|LNmKY~<@cS?NK<a4S^AuEE<JJQmFvY|UQl}9#dy<|3%>$N
zhSHBpmM<!Oo`t1M<=eEA$Wr2?h`33WD`+E=t=uRExvX@&Ol5{SN_Pt5<SIQM$1j?v
ze2!+@eC3h30KKAoVn56mD8Cm%q)=(2g=>*=B`pxHDs{KvOtF%640<KXFM463RB5^o
zg)-$M2AJi_UaC*3P`(ol$!p3ttH8XjOt=imO69oYdB9XFw@{^Ajk1<zs9NRvK``r;
zyJ<3MP(Dd_S)+1eE|^WqFG_*dtUN>YNiE9FkHJ!#GKNaF+LZ~5G3*Yd+Z~Wj<<tX6
zb}2uNfckCa4!RcI%3*pB^(ZeFg4|K=dynFuy-F!PPIr||s#?0Iw0?>ouTOb~(wF_p
zZ(9I!U-{SfkQ`8+r^wczGJrsbluduZ?gM4QS%^GT{%{@63@dk~pl?KZlG2Z(%I-xF
z8B_j58R&84d^%${q0GbrY38Kz*$mqMO)1|S$K`&cy!aMIIIR>@8H}@PqZ;}ys<blr
z?W*$7qt8uMO_#)7C8>wOJ*rT8)b^@=D~8>Ds*vx&+^_PbhwFeU{4?0~P|a$BB~R5w
zFEG7S$yH!_t5(wT=Add8R!NSTzN!)rfcmMPH9*E+RZ5Yq096is4*sx;M|t!ks%P}T
z4pe<K0L37c!wn=@<+}qUL{&<W!=tLCWAOKw>Mbc+p{gj#2!*LG)50@c<xCmI2vuwZ
z{Ebuv(u+Du<x5ouj%Zb7Axy-mJdeR(tm?wcuoS1dwGTd>P<={s{z+AJIYdsWex>s`
z@v4nBT*L&`tMtB3R4I@}nR!O_MF131ROhJx<*e#Gn#xjD3+M+;Qx*Jy);X1{83xa*
z3JyWxg6a&tqtYF!MU;onP;H~K*^8<yF*Gt&NpwstOLb=rT9;JU=0G%CwQ?;CURHJ9
zg!vrR`EW3ERfisjUY_a{J)8NesbGxoiYj0lq(CKcgHMI3M0)KPsX8e@byYQ#3dv&C
zArnMORE`g#;7zG&J|#-aRKo=@QLftS1G^Qf9kj{1ri!EO!gbYWt<b1c&7<{pm1=)2
zByXrjrvO^5vQU{)o$4csxZG5=e+9{U)oukw)}VSm2h2v*0=h|?R67uKo7t@ToaXZu
z)n*4xv#qK{v_QF~S~d!eHr4WC$aJW#ZNShvRbrZgyHsz-fb^;6UIOV?B^E&8zG|i!
z>I14GI)gc=dY)>KhE%B}`9S4O(Xxjs*F1;}t5PVeH=_E5rpYnYSvvAIuKI>W@s|nJ
zI~m|ksuuCUol<>GQKUyIJDup9R;{CIP#5*c8aU&sUh@&q+|-}W0CTT8suPy>sfz|c
z_NzD2!LkGDp=TlDq4s2hc&caKglk^v(^2?Az12_V1M{GIJ#C2(sgpve{>4|V{vGE1
z)V^2YzQ0;VA0H1;zuX9o!|H$=z&@hhng*CawRR0!!RlWq8yKSQqC5Dg+R_S3$JE=k
za644}58Vmj>WLU!!w7W*ZNQ?`4L?C7TJ1yMEQwLCsepwzwab_E{GCvLLJ^yjY6b->
zQq;eB!<n<{4_|{~s(NG|#+0UhpK>ba)X`^P_q_TVO{^K}dwbx_MfG|5kVB?=C*AT{
z>Yp}2@{&54@=Dq2ED8%=R)6$04CbiUQSnf&I<5m2^3<QuQr?lT4sC?pE9!Tjg+`&;
za}G3$)VpQCzN$V|hE}n9EDfy^^~p#`ma88hgijS}k9PE3Q!^9Mx~_hHJ<uxEuMWXP
zmD)nF)f?&(%AQoK&wL5J8uci}<!aSqu3*-wi|H7{O^15$BnDHjzE0__2KCdgg4?J*
z)d&}x)PBWKY*wFq52QuCb{zVx>gh1_-BPchy+@n+spGKJt}dgcVu#u&f_kUAg>uGS
z>OX0Rdt05m7|`A75~{uEQF~M09rcoN^!2J8-4ye?tDaee!Q4{^h2TQ<ske55*{{w@
z2Dz^e{~4eIYIZJQ2GzejgyN9;ECo;=sE@b<?V&pPE?UFt@oe;ss9Ah~jjBgq0CP;;
zIs}n%^<4?TCe&Wv0cBFXVm{oSQWrb+L*|iMO#6gsbqwWOoHc`#V{p|xNoV@^Xx{iA
zH1=vt^fT|%Y}^Tv{hGKRp?5&Dkv5zjn$=ID&r|cuH7Iy#{3wd*t&!BhnS+{_Y4SUy
zX*mW9KALhWg7wuLDguh1#z#%>KYxweGBl5Bd<$Urm}WsWutPPBt>_EWOeBICuK6ex
z*b$m{$^A%8EB%yFn*Tk9%N4Cr)uR=od2u!LVl_jQiaoC3)8ikfdEzaopU_NGdBsUh
zI0Fi&G{F=QkJtF^qVw;kHJW5}CTLbU!^K3+dvw{(Xc{g;G)Z%ezF(iL@sU6yMbq>t
zm}fQr9t3u(=J(z3Fin$4ljb>%;U3h_Yp(BtGZ!@eYtTy9tf9bXh9-<8FKX`D0iCJQ
zSV6Khy_mrrGcRder*MU`H6Q6AdRen@BRX?5i`W=NuBQ1Dj5klyMEiq$%?U9?u4v-?
z;ZuR;xwVii(nuz8UtQHODR@<^`Ry&(Ezvx&5FVClej$I$G;eH%Lb+!CQh-%x_EF8o
zHBCOvOpfcCU9>2!)NG|3UzNs4@7)_31%)SSH3hGuuTJAmVTqd>6-^ZN8WR;qH)sl4
z&}!7Qw84ueO(*RXn>GKV07#4G5Pd1FRdecdsNd40j)B>xsl5je+cl%!fbP)rJO-3b
zhbD>g0bQB~+VkAj<huf<TNC&%WO_8C3*h%1&2OGS>($skLEl}?Ti<}((>%Qd3VoWF
zK7e|^rirqy_chJ5)Ev+p)}uA3`GR7ULz;YgVjgI`X)XRxbMQTQF{}xtm&=I8ao~H1
zj%q%q<27TN^a|J=*ChW4GNEZ^!_uUtfX+)!X%v)ZdZal?b-~k`5314Uti3})U^i{#
z87R1Gy`zA#NBb%juI$(TOZ7enw8jYNd1zNY4n1$}uWXQm+Iy7aKBWEFu@y2t+NbA$
z>#My-1)P4`)3lHC*9QH7R)BU6ZMhC>M^!L!MEeFU2LrX4Z=n^Wo$&=EgSGz*f`n*i
zrvT-s_HUZ(k7={0C_7Z^O)L5^?IeZ%!nMb5ff=C<c?y`3+UH-S{a=)JJ_U@Twg1qI
zFGjoP5w2IP_A|<G9@oB`i!sG%lPPj?LYwj@TJc)udU$bK`x^ze6SU7!W;99rKf33V
zwLj9TFhzTYK3{QGtGJ9-s`h0{*r#b%E&%hK_QgeT^t`reF`d7?pnWy~+;r_D4bU>Q
z;}lo8s9jS6&`hoUZM3qqbJ-x5w9g%e7uni}v=6(iZJ=aij&`{bc5}5&lrhNDZlhzk
z`P%*ncz;E!DMVj^_C5ul3$;H`JfTQiz8nL*s$I32;xEP8P@1Mow96eJrP@%M<;%41
z`9r^4yPM9OUf1rWeORUTt`r8Vw8yW*{0;46Pr{jM?W`r}tI>XMhKZZn$3iiPdTsx6
zU^ZyiW}(%ijrM{UceGVM!hEmx{um_hYVGtkbKKL`CgaldX+6>a+ONI86WsgS{b^7f
z(C)p8)}S_!{2tOCrz)NYT7Qb<J=D7Tz{Ie2JJrUFXjfOl`%&##nqSAX$+TA**Zxk$
zB@<dx4u&+Tb*2}=ls5AO^qh542T)ubx?AzE>#F-91d49D;XrWRb^RV7dvq%&p|Mxz
zVuZ*(T?7?2?bkiF3D^g8v)@3=L-$t^T=UeuMo}v-ow6H}-ntK00PLWyo@Tv6I&X?a
z`RH2c`SH~q>Vczvx)pS@`0E^LBESUb9;fZiVcm%ew2tUT=*bDxJvI%EAe|HCFM@S*
zX23*<ZY4#pj_OK<fH|fMI)qlJZr~DHVLFBf^ul$QXqt@BHS>WPse6J2W|VFw-A~cF
z_U&lJ=(baeJy!RJgC3ycx~mk|i_^VF(Sj4YPiZG}Qg@S*A*XcDPy#((XM7C$r*(Q-
zrzhyTDN>WDOQ6}~jBes_fF|i8Xy2Hu%cn?qitgLFAZK-b7a)?V3)>7w({xY%mlo4?
zZU)$S-Q4RAz+BL+qIhDuZht<oGj#G}AQyE)H`vY8xzP(OOV|D-^e^c;y`hk;3ygun
zW!<)efXUHS(Hxkod*e@#JY6_#x$<@FMR4Ydt|t%!EYN*67np^*a;jh~(m7GF?^WGz
zH|hLCu}<+KG)i<e=fN%2{YIC&Ovk2Z_cdJtk_0oa>$WAKRjFG~YnUos^)y;HbWxPl
zsMbA8iL@HsOe!p_)y4Q?ymh*FJfU|}_b1hl)$0tDac|JICWG0ibD_0blP;4>@4sf<
zt*z+1r5mIOahvW`A3SZ>t)(-G9lAPte|G9#ply1W?&)=C_2?p~BI1tjvrYJ!dUc`$
z@S;zrqrGLnE}kMi_jL*m`i6A>qo??R?!6^wJ=8rxQ}?irLkDk1bW7I4QOBt6_VZ|t
z>3Zm=7}q6t!nX;XM>1e0b$2qsoYK9t2(CTSwZ}taTGu)kXwLc{=o<zu`WH6BHCMgw
zW$3x-7bb)0uD|sSeyx4_xov>nuaCG0y#xBEX$j+{KhX~_y!Bnke$G7T&^vt({X_co
zXQ1e#-+vk!zWTRs!Jwc1<6Kzs*IQ|~5upG4ML2U<A1;Lc5&cbCvIXk@rduaS|J`fo
z3)U}g1!#z#(Tvtn{q!pMbWH!t13-uBpZoxN5qe)PEJW(p{0{Xfz2g@>1{$l^(w%=?
zk39>X1O37|=scnSY$sehsXsFdtyB6rHE6}_g-=7_wEj~bEG6i-I%7<UdgdMUozcJk
z8(K;F<xGeq>tnxwr4;>010>Jt8`q&PRqswyf0|xFLELltF$dK;r|aWspPixK^ex7F
zQU7u*WODT`+cC5}y_S+G`Fb7I>0Qx(@HChOdJUzw3ia2nL$64GKm&tU^-sSKy<+{%
zwQ#0HUql(KQvJUB=quCzd;p|eKSu>pp`UVwp=<grAJCkCUGJO<>`ML5Q6N?NdsJ~&
zqkoAu(Y1QF2Ef$m3$wtyssD=Jl=b>eJ+RxL7g8Ztqkhw~@Tp1v&yVP9);~ti*e(6t
z8z60ZW-u;7yMBHe`a1MWXa&`&529bPOMmbh<sWYAmxO@Zt^e#KWP0>xX94uC{>~04
z-qYV=VW53_1EnbX^>5vPrThA^m!L49@8W_vsIS(;wIO{06#+fauceK_h<+CZRYvtG
zAAyYNH}pbpT)&B`lPC25N3|Z4diHs$|D4jtrUT}Yez7y`PU}lK5Op<}Dxv6R5R_o_
z?uJ}Cm%Y#MlL>wM4T{;2JYYznJ&Tv2W)zNk8!k|y@}Oac1T9~~uY1w*GZge-NdAUO
zO2r;A%$SM3KtmGklY<Pqk3ijV)bM!<n#T;67QnYq!$EfpEylo-LnGE;?nLXj;r2PS
z;ta!oLF9xXDFObTG&uTzcFLf!!l!rx^H~@?ZP=LwW`f~2+UO=4&QTERj3H(vM3M}C
z>mibC*gyppDTY0FVg9Vc@O1&qryAm~pqXaK`UHyS43od3b>0y9J`7$kT+f2}bi*uv
z^ko=Yq)@nM$j|~b)8M}Xtt>;wN+?`1NcO?sY=b+I%Z3$iLLtYn_Za-mGjM1}o^N<+
z6be@ibDx111qMgVd^lBTc<2GNBEy<};9fO+I0I<KhMy>pP-4h;$0$k-%PHnpX5dp~
zs@%X|0oN)FJSu0oW?1zDu&*1wWkJ2tz%xUk%FulVUfeKj-VO7$22M4Yb%wtvOm@@o
z0!8i{4FQg=FwtZPZG>pEp;iU%EyF!3cW5)L9ztKcVMRGw9fpaI(CRcS^#x3qVK#lO
zpvMsKA;=v=9c|Nl4VNi`&}TSIA^(0uq7Zub4f7~EKVW!^N|*)>Pp?4Vkm2)CFoz9p
zM`;l<Vpz2tWYn;hLQ@lljAU4vG#pt4(J8|m3WGWum(iG9jNh`*=W0yM#hCUO@6G~q
zukq6_fW6NsXhUni(V5~+2aM~ZA>v_NN6|K4BbTaw{EVw8?&ELtE`dmZaosSTe?M&e
zmu~ALMm4Q_1C7J0aDju2C0lT1gN@=rh=v$vk;YNuPtW1%9W%ak9Ia5J(>^#8X3YH<
z9)=qeUP51l@mmg@i8Q`-03^!TaT(Cj#u%#ii7~d*mN?cZq6(_x#=;F0e~B|z)}ix+
z@z&o!J8AS@iOy5TQg3(>Z`{xbOQ(%9pTu=eFtVP6r9|Un^f;X{{<;|0Nyh)9?~)`N
zOQ<G1#dz9;zO%+&KeSSfm2`Ke8Gn8b&YUwoptFqUjbCH~?1E8!2w;wM<DOF(XofK}
z1m-Uq%g=$EY5c1M`dP+`Y+zq9S{Fhj+h~0Zt;@!iBEaMrmvO<&H8#=E@{9q0p_Om^
z$b!}t<2RQeQeb54L#xpEC#^w>jQ^uN=~d(Ed@zfR1>3+ZaTuT3ieIMG_{(AVU1lt&
z<a)U=h61M*#(A_dxMuv!7p*GeUCOuIFuGAxq}te>379(L>_cGQG@kqxq~0iNh1*TW
z8<Y-jHk$r{UW@U79LzRj&a(h(H!>}-+hLqr279-Sj(FMycN+&q@S?}a+6d4)#!g?z
z^cqtsS$)@-OV9Q_W9F+6=`-G>ZDhYOei<&;eIu9dgaPC8%kWbS8jn-K%>!fP0L(u$
z{zdb}u(9MP*c~xm+zj<m<CnCf9y8vivf^>$rw+;$Oc;NB37wP1=NRBl88=Zu@grl|
zL0FnL4!@1@I-B;NL!XOjTOXLNrU-g1xS6sqgSeYC*Wtw;Q=%98_L>A#<+#sug0@Bb
zO>^!;{eY=}=4B7l0x_UHO=_%BXL^~$B3kr#n~EstcF?p%4Brl!)<i<l$Fz?HQD2iH
z985pcatcKFo5oi`A;46z6wJe>Vmcpo#56+5n?TcSKlBBe7^mP&uu1zAL_$mxufoHl
zrWz{GKW1vDBuuF3S~(mIGc}A;{vq7-OddodOxdeoH_~*$6`fJ0^dA5kZStb3zZg^h
z4PeKbn45up+!UD(5@$L=uAMN=q<QM3>01gbo-#@3wI6S?(|mE-RHFq+FtLgOooI@r
ziQ<f@b`s7cnIx#6cFasRy`+LhiYfg&pq(|f&^9C0<T(v5(oFsVAm>b%C=hYp6xxD|
zaKRLn2TSRuxxb<>!{pQh=0#Ip9GID=4_-qn%e4I|7`$Y9_G5UTZCXuh+RG;E42(X<
zROJc1T+`c2!F1%A4pI&&-!z{l&nqVW<A5nJeQ1D-g{B?!k+CAvrvkLDn!bAr8pWpV
zT9_y?{YA0<Qqx#0^vX<S^g1gy3H^XwVd`H7OO>XAU@)sp_uoP5hUq!_<U_S-Pe0Ua
zOcnGVs&$y`R5V;?%A%?Nrs*gZ6xW-&x1qDaG=2b=q|p>iRaQ-=IaD>#Y}z{)3N0pG
z8hmOsDcJDomgy&2-L;t(%?C=m$yW^Z4%3T=(bs8u>{VQgE>pWZ^lqCTQ=!#us-{Y{
z9+M-B7Snf3kG8=?uW9UWDBd;IN5IlOQ`JVu^qID8fk?k;`PWdqZ*q=?<bdfZ7MO#k
ze>*UkAyXv1a37cwX}Wu8Iz~J4VUx-WA|s|HPor<t#G3~)X8Nod>f@$=cS3T)^s|Fj
z*psHYv<#gxMbY<RADPxsiO#gCjf#ey&G-0Vx|jvuU})~<EtFH)W4<H>bFcY92gpA2
zqt#&UH&2kk17;c3;(3_8--o}R<}Nw_<Yj&_987QXR{ALpn!o!LV28|4_Bz1zF(1zX
z@iot04z8d1k^(OJn_s0MV}N=2@3_u~%^RrB_K0~6rNaZw|KmX<$h?fc<`itMrEO7&
zIh;O!f7F~xwZF&A&rz5<)coi>kTA2z28D3*trM^iVeb4A_9D%qcd7m?$~-{&(dNoe
z;9HE@JrFXn=GbKz%yIMKe*A`U=Gr>IoG`zJn|0<%bJPt;o-#L3rD?o*$xig0Hoq4F
zy#({`G?ONpTWQa8#_X~M&Lo)^r$FSadCPfVrkdyIU@y&F)k^!nbLJc5_j&Uk7r1!A
z{8&6-(#@aGfkuY;)LgVKn!nu*v`jN+EA+F>UemZTm&|jKzn__7X3{g3YhFXAd-BXl
z6Y#0PoYV#rh2}M9AyQ<1>ps*=%#TqySE+fJB7kK`#sS4~&74C)tm|eCmHkwjOP7Px
zo1Zj+*<hYax#LE&DH&)@W>Xy$o6Tjb;ctt1;g|FPn2%6l{4MhUy*b*<YiL#2Zk|h3
z{vGBRn(jKy#x)S>GS}!pZkuZ^L8RO4O{XS%9Oj-5&^zXe9CY@YzohD+yXLp*p?}Z(
zxdLPAGkZ|hw%`22Ak5!4`?&&iz<iMgGicsUQLiDh>}8-lFuzg;$%p2-9bgWd^He|?
zF)yMO?u2<a-H4OsZFvxxGJh?DzmLq0Myg4eHt(SQiL*tv8=x+he{#_2YN-i;PkSw|
z)9YxTrGE_+_giNEcavM@R6^3j(oLakPfOS|emgHqDed^YEyY`5@Q}rG9f*(R-hD8A
zEg6)!^RuL#0*b$7A0K)FmRtvY6!@?uFa(y4SmxzHCeTv(3Oa)<%fA8%v0SHWsiPK6
zJUl#RnSU0bp_a|X@F~m^*^CPmVfmJ#ZIPCf;~-I%_i2k6W7&EFBa5{JQ`+*lWmp81
z6PDinKsjkial@54WjV2y@_+G`ZmO9)ZSlE{))`CmYP6Cp;}nHWwtPeLWQt{n7R<Aj
z4N8clS|aFCNwZuy1<-SrJzbDIZ)v%UR)*!-R*dkXC9M^bnU;zLkj%2Y{a^UTVmJY2
zwq-SKx-VOpA5i`;$FiRGt+|$26j#r)u)jrTzQv;xL%U*`WI&_9@-Myb3oVW7&{t&X
zY=gp8OCY7yiY@hPAyQ&7euPU>ZkZT^7Zn!u36N_R`%7S6x4dA2dZlHEcE44YL<;iV
zu#{e)?|)WXe$+v~#u84YqP3RK>Okr&>%W8OO-pzh`Wh?&tKnLsg`W-5WSO%Qq}ek2
z8Njqy-aG}7R!j6Pv~F3<BJ{OcmNmlrcFT9}@UX)&CWiS=3#SjvE=y86L~dJ-L_^Qf
zZSh|T+GA-Y&^wlC+AsH7m{fUk*D`VxefKPjXnoRW>7cJ7^;=TIK?W_;H6TNlWlAVK
zuxR{Xe#G*K3gt#EyQt=W%yRiPka5f7REaoY`HF6<Ny}jc^rkJbe*xOrVf9&$P8Tck
zeppah11TQwZY>JK)!SoznS!EwtxwRld7t$a7FzqQUR*eOz<R$EFdo*lU!dS={gK{7
zUe;$Q2kUKZcnX+4*1st@>1+MH2MT`HMka{A_2Xf95n!E5Dcr+WN1+`sN30Q_!eF4)
za0ixxtdX>C4z`MEG6}IRr8?WARy)Nij#;<V;aY@RPy5gVU@hiDJ=`iB#;_x-8|OkH
z(&~B}cB8CuYz!&d8t@57ob{t3sGqRPx}kT{S~&obQ`VOq6g-Q!rsP5YwDs?5U?*4|
z`CukmuTir3jP;GfAW7B*ry-JT<>W#!#k#N=XlJeO(Y7_!I;$Qe%^F6rnRC`^I>2+@
zx}SEx7p#BMDf)ElhYe83uxfV0!bK~CR#%zU1`m4vvaCG}bY8OV2!vv`we~rX%hrP_
zFqmU?6JhkZ*6wF8&^+r|+R5ZwN7c}~VlAhwM1i$S4Sx%*mPnu!Stakn;8knbGZ<*G
zb*dhu#CnrfP^H#^7D$#^zoB4GxwZ5F)t^;Z%@+ZB&H4nr+OJzjX-=uM#t%ZY%KCLK
z$PMd4ns2JDti^Dq#`?uo47Aqzdp25i*4ebNxM_7=hgQ8cl^kubx>6y3qxCDAXqv1`
zDLmI~ZE6Oy#k$S~7Fw<I+o=BfmUS6bEwx!c9|yPH8rcc#F00-Linp!*w-9~Z)^%IJ
z?6Lk!pUt^r9bSgMUhCuZqusTNR$;vNtot{kug_Xuje+)CJ2%79ee3)k7}9{%K<C*8
ztuIVKVaRHK9n1&TpDEAj7_p8nhUlm@iHe-Zti{*h{<!r`GCyJMH=}RTx{l`VDeF2q
z7XHY3_)SPoTZ^cY-`Tc^GEpwJS17pRYTI`jB5t<39%#ASYUtlO_Svf50CT_XdN>pg
z*zVjx%ft2t?QT3Bw&%o<@v>ELV9DF|J|&M1+Jqa?I%NBO0bqP=Hze@M*Y^E<Sn{)l
z(5>rl%cnz-0k(Djl}XroDFS%J<~AE90&S~}=nJx`YoH!%dxd6!5Zf0NEI4YD%!9pS
zwp3aphT0siwB`!4@#ev)NZZzUbVk`aX)2Ajtst}*+l&&3#M<7ygX?wNR^tN?<813_
z^?kzjgaDu?Z4FBya>_O@3F`5-Kk3}lY1<0go+Q|GVn`<1p8W*lO|q5J?kL%|gSM6_
zHdhC&?#|jg4dABQW>9Htnl0~Nbe^-xt3b}%hIat;g6)GDfJwJ`T!Bv+wpW=jm}T>N
z07oy`Ca!^*ZTs32tz6qjDv&(ezZA;Kw=JSo#}(UD7c3OmX1$44q3ytb>mpliAm!h$
z+78HYg^F!o=EG8n&4)5srM7=5)=_42e;H`ywk>p%SJ?JY(BPV_E)ELUZHar~Z>6o7
z1@l$5ufGKL4O<PBj8xmcp)F#K?RGf8YHfRafl_DtcPaXA+MatI7pUG=^xyfv2HR^}
zF_=c%&V|5kvhgS#*KAAO28Ua0HGjfxt8G>U`fl0Yqzq@9ZG0UR+HLc1p|8W%<O<Sh
z`*}Ca-?lk;(CfCf?S=O}wwGRo-W{8TUZ%aa+j@xHwLL*a#`kRhS4#Q6K3l&8?)Td!
zDR_O~rg$ET1Gco~aCp#GSP15jEs82C9@uh;JhUlI@M74O$irYpY-1F;AGMvKuau10
zKBj%=xNW)yC=<4&_n|&%+hPK9$|eegp+~kqs{uW2a~Hx<hqJxQ7hD%RYGd&L*_Q-C
z(anC4%2C|yZnWy(W3TPQCE06Fc^L!UXODD($bP%w96%4)W5dw$uzSykh^IY}R+C=#
zCA28@w);{X<Dfkz10sj)uhISFW3PP&#Mk~6t?2z6c2A1;`rDJ}uxfyPBo3g5?S2O_
z&?EL|c7qvc7bid?$iDSDu!HTBei(g-{o8c3j@s8n!_i~*6ZAF=wV$U5UYPx_&Cm<C
z_qjnb!u|<Gt0V1KUEqC`{Tn|(N896h5Q(une*FV9)?Q9`_i?*#8${#miz#_~!hZUD
zfS$CEQQGE|eGUDF@pcBi_D|cd)0;BE{^CaHCEB|!AZP5+G$$n4v-YAd+1?X^UnIqz
z@+11r+I>d=ooaWZMb>%yH6|o4*#C6Uht1RNA4UT^!#<xvOBe0CZbKu}E_@M#$+8F2
z#lK{a=!ZtOeN86Dd)Yooae*BB@6K>0*FNJTwDRm#Ezrxib7(Pp#eVc8Bn#~Kf}vh$
z|B<3NMfNMMXkE3R_yKyw_Ent@h?dyXK7>=H_Jm-NGJ6&UFw5<k6wIx#FQ8QYHT$10
zqwl)?P5QMe?Xz-Wu*!bz0Qzp&6?l=%thVnmf>~q#hN`=2?a!COV4XcT5q&r9ZS>sM
z+h;^zoDKG(aWEV0|IgBOKt*{qZFiRi7J-F*%kHv(C7NhrG>MvgYShG7qDeHxL=#IA
z)1!v1DjHpSuPQ163W9(NNLOhhf`ZbeDhNmsP_Q9b@qZ@gKPShVnLG2$+`DhNcV_O3
z<9_=7e5=!Tik#eZD!YNE&8c7`Tx@sZsvz3oG<P*Tz2)>K9cAfs`tB=$b~(wNL3KNY
z(N?X;DRe5(ZaXdYMPIMey^lflIccLI((m*%9U^y}T=xLwu9Nr-r~xM{%E}EotzI?;
z_uoCIqH;KV->F~}E<SMDT@CXOo$gv;x*s_e(lU0)$z}j(kDWAhsAAa3z85efPG;Xh
z;fd3?EJU6<xlumsnbX2vn1AjxiH_yGaN0~^+m}v@-iC!yry5U4zH;iVgEKDbs^jp&
z=&C-v3TSTX<Q?dASN~3NTMxAlEn~gaN3$T~qmHJhrmuSLAGlcj)R_VB!e8A?%fSHk
z4i3y<^^riRhp02@X&I`1LbXf#)iXbbPhsje-vs6Xbx$pr2i21|qdBDZTn5Z=qk7E}
zbRJgsvKUN+`mbqlCQ{wUp@~wr4?*;ZdeJV3993VWBG_Z<;RKk7RVR5uBu>4%5GIbR
zJ?H|CR|jRnnFRH3-$3M~+H^b=PN`o^0!otl;0NeCt=>g5ldAr@6I7bom_VP3$yD1>
z_$W)A`3BIk)di;@b4I<6*4t;*rzqZgPQBw1L~_&uN&w`lC!U6Wo_ZdIHS*OT(D}at
z_2adeg!Ag9v!GC<&iey)FRHsQW1z+AoQY7ltae(3rc~WnkETrh(0BlySJnBnvo2TH
zd%|voddDs3SE`@U+0QC<ENug;)$i?tMveL_DqF8rmr!!<ntJ7C%vzmVxB<+1b;mzo
zHmXmrz;D;2J~Isp&1%yh0d`%Dqbs=b)m{`fYEjRA1ie=EN9FYXyQzM;92#xvx_2?c
zc6>wwGM(!7g)rZxZmGoxyVdb=@UTa{imt%h>RD8o(5r6R0Fi!mJgqG5sNbV&{jS>Q
zLkwv^olFPe2GwSNgLzMFL#u}S>To(i`au0RMM@v4*S$gcheztIb?|0LeIOQ!kJb0I
zkQr8Qq)5?-dMgj=iF!o_(4MJ(rET+b_02x``$D~ro|Z4w<3qt5RoAd^?UmZ&3n;i~
z5+}naS54BtV7h6Plv{Au)X^MzXztT$(o>T^mj3><mu5S?jlDG*+C2DZisLaRe~r^s
zm=Dm*r?Rd<&82?8glIIB@($IA55ewU&2-w4@6(ji!+O6)P1(yZ&F4;_4r!cU0wr8C
zK>N<anqZ1tL}(Hp!L>-ur}0pa(u{o#Gh;lWaiC}5QH_$4BGH=Dr(icmGfXuu$22Sd
zOP^>ae+bv&G(VZZi{qMUanO&~<Wn{=K{GB2eTf?JarB+g{Fwo;B#mk^z>+m(v}Z}t
ze56BjTI2gGFjF<_DdL!>vA=^R)2JDA!JK4i0*e5Xt<li2f^(YXiEubav*-?-$<_GT
z!eE|em_qmYn%m#QM1jV8D?ra{{(KASg_`oefp$UDlL0S^G+MHIQFHkqsAA0+Db!0e
zZj^_+q-msw?PblGyRcWPG5*BBM42W!9Qs!@nspe{Rn19?Ih1Sgx7lzzXfpl)TBXMI
z3!qhLj!XnvwdNVUWNI{wE&6IT-!wt*n&wN|(>7>Cv=(pFtiF%2G-*sIF4wFHppR}{
z*EIP-@`h&8UJS5B!x^VTqgC^u8O=>iz8Yw48Z(;icFpW7V0LK!(t>$QbE_GOotmkX
z3GUKN3<g@aCW{^>J(_d>gXC?^&N@)N8dF*`^=bB3V-WqCjg}bp9nHo;_<L7_JrZsX
z&1)1{8q~~9r~ThO&39Cta$l24PsWED)*PLWG!4xV9n$nK2h3y5yHub)tdSPOnGucs
zLyYN(X38umJk=yq(cyE=87-O@nkZTazSJa%p)jhcnF#Z*G_I66bJ0f31JhMoGY)$0
z+Sz+3{^_AL%SETB_DgSg;iWC5sqxmTCIHP(8+ibfzqUe;p#^9wX~`F;JxoROLE7Jb
z#v}x5{YPLhMEmqE`a-q6OVGDhd!C}?`?Nv3z}&Cx9R~|x+W6DJJfJ=6fRP>4awzu2
z-yhSq(6Nzl?Pqc*9@Yj`qccJ~n}Rx#TCZ|=8l|<igUAsrlZzkbsCMHa_!O;WJm6D|
zcF{(F9@7?0fO@RfKoOTXZ862uk89^&gNN~2&upM1XyY=`Bx)^RLga+@8#-KIJgNOI
z4=yHat=|AziuRl<uup5(3PGi68;*cV)1Fg6Bwc%*D$cUBhv?GH*4A}{I-@n5LEl-e
zRt@v#v|Ustn4@*_h520VH?(!h(@t6lX1?~5W`GrFr;~;A+K+w)v(Tvh`ZQcD(zZ}M
z<D&Mt1wf0nhtI&%60Ok#%uCuKN>*Rio{C3Ps_lCR=F7B4&Cp!c&Y=BNxwhgwBrCLw
zCxcn3-TNcdtF#6>FIBBo(pYM=v(JNBt9>#NBG<GBDPU8lHI9A<vR>O9icvIZ@AqI7
zjoOElM`+RpQAoL2n?*69>)JXh0K1{>qT^aE+Ui1pwrW?>#d1?yLPc$DS_i7^YuC=D
zaB+vWlq!R6X}K-1)T!+~4fP(af*$0zwMXddZ@t=|jBf$0UwiOfkax7Gzr;<VWw*fm
zfYwO6hC%IHSx~&Ey}Akp?`vPH1@;5&R66AIP<wSDL>_5hn+^3LZ7(IqA8S4Lpc&Tw
zJ&L|3T8|+pJk{#yE&NOyPQ`4`wKcT7d7+J+Z-mUK_K!=Dd8Iu}m3=O{@Kl(0)ooi1
z*W7f~^nCTu89Siwsr&U9M7(tW(i_iP*Fb9@ADsj3cYSqk^eF;AT|8m>>&{RtDM0u5
zAgDl{8EyK5bb<6p3fArU08NN)`o~oN5~|xnckEu>i8+wjr&~oa?EN|=9V`pe4bsc)
zfNmMBK@RJ*EodTiUxlEF)NP{YYm{!A4@8dWW-W&LQJu>Ls7LF*qX0;ZuARPkeM}ep
z3k=5UUMs|qj_We%x`@|x?4<Zhf^I=ETujt8FNWv|T^((WPwEbx0?aAh5vqSl(sjKC
zv}B!|2>L0yOgbi=s+&$RhcunVF*NDA%l4SV4BgmwA(^Q&oeQum9Up_fY+V8!wmGA#
zNe6XScZwc*=X9Ij1hg?n*R~zr<m-axLZ(3X+GRB7b#tk1wNST$4#Zs0%?gKNk?uX(
zKVH<GR71a5H;EqTCAuP7KVH(US_Qk8bv;`#38lJ$_d%8ER?(@gD>}__h+NgxtcFkJ
zy4^*<tkA`@f~qv?s)m79rF-cNZnds~qUANZHMGmA)oreY{xx0b?+~riE&LSN^}5M>
z&@|{K(GiJ8-Ah^^H0ercS=OxkeGp*Rb-vT#=ndV^(}CHdn?MEXt-6sKK)34#|3zPi
zZr#5?xur8Mrww{1eiF=jm(G3!o!z=OD5}|``+E=O`L?d>Lx}e3_*Cfk={~TBWWUat
z7U6evztQD!S64~($OAed#dZdDE!WZ9(|y?wl>53#44MbJyJOHi)D6tUkRIvg`2lQ5
z7io-w;$vN08$gG3DPv)9M0bz|^F&umJI1HFy|k!(raMJ3_vg9=dodV<3Q8gJQg?;2
z3ZuFuR5brew|NY(UG)9*N_W-Ip>Hp{=?_l<io3q&8!$cefzu%Ash>jIF)#f$#kBVE
z)u&N9&rh$V*OI^f(poSB^a)ho6sS+4Yc@!47=gpV`nR576e0RIvOtCETj+(kSN};c
zsD1jv7cjA3-$utT!t~!z=Inre9KC)I>ieip=#buqiVef{=bh0U)~}gJ>(2=NpTA(%
zBlV+HNfo94WD(3C(U+BiI;#KnA1Frai{1iujNVxTM~~^(p9dAI&!OOPoL*Uixj3%h
zYyv7?A3$Ct=qFHFN22~JJ+n{fckTj8vVP1KP$~Ld{{rQ-z7+csqc~MRlOq3V`d(U!
zr0eIE!{H45FSM}9)a&V69$EUx22f}8cXcpvR^QQz5uVe(`6W!`=wsgjGglvc8`ybz
z89hn!^{1x5V1fSRW-!m|_tFxmP@lXR3K#U3KZJUb{w96d#&}WRPf5jMefm;#Ue+(K
z1GiMqQ5dvLe`*=*mh0W<Ua8P8pkJ#}pG8-9jegU4SgO^BOozfX{l_ja(V!px0Sb-!
zCuF`!|LhPHn)NfUp}DS?RA7KN^yBV8q)oqovXJdY{Z=ZI>d?EKMRQBP;0<(k>P>$I
z)uo?Di~nx@N3TJ#N8j8IgSYkdwA$&_AGLx{efmw5S?$;RQ%>@Ze%v|C>|OoJUPun;
z!>Nd8P``Z#EZx(8J{Oqx_13ds;eq}Il{Y=q8<*08>XF`o4!#fR*DMFxWBmf!C=cuV
z{{?eIpG=$RC;B(Z;8XqDS7@H;ZI9t+ey%T>4C;lxrWGhJ^`Dl2IjaAT(&(@BHdI95
zV#uZ(fvdqe5tN%@jtq^vp@{|4!w_ve27PZs4h24a4F7%w^S*{18!!q#!!62!_#0+S
z16qJ#-wO;o(9lWC-yp-gy<i3#wmt@0h@pX^&Y_0Y%b~Z|u!&N@`wU;vOL4zpl!8HF
zhE=rcIAGZF4b%@BnrYj5$WUKI=O4li-L&C6Y}geID#9S#3Ykd5w2xsh%5aI2M@J05
zQUdR&A=L$TqYV?OUM|M)Lm6O>8TdSyh&2?hKoe(}e;<~P8wx0$9dGEZ!XOe1zuH6n
zq#^lx^qn#+mH{Qn5F()aFWDg32{Oen>pte<w882eVA2eMbY?u=Q0@qr41=@`gUK}f
z6bF$kLk?vl&KioS4)dI0!6G=5W0=+og<Qi7OHg?RAyqBp8%*gfTwsV0gF0_Wcm(J|
z!?vAZ78?RlrH{XVWH>~R;!B3z<v_b^sMrUYQbQ|6k;)9V9zeTd@T9tdtA?>EI8$zD
zI*n0O7)+_op~~R;8JcRt{1Gr~4A<z~QmrALR(015M<>AFdc#{|z-%x?)q`p@^y>iD
zWY|Yng0b1K)eGcx!_z@b{tZLkCWy8g-dG9!n}%Bt0NQ5QNe7qO4Oi)|>M#t<gon2b
zM=6!tX}DYopSlfw5t!#5L-H&5d)x4$70g~k5PgB6&oCr`UccchiqPIMTquCOr-r4(
zd}%Z!orKIQ!;7EMxNXa}1GeY3nFG-G**5(LX!vh)re}B1wkWFXi{56|1QVyW#n!-l
z>b5otP-Sl0b^#)1w_RTVX708bzhR&S+qUFkNEfzEr}sh0ws-@WSGO(o1j>zVXEva(
zZ=3PeC3y2_+awh_pKq(a3a8w+&!lU|dwYEn`hvGNUWCE$?Nf@-#B4VgLI1?|;Ul2Z
zw*M}K`P}Ui0nm!KH}EiDy8X(#5UJkYWe2K$`?g;p61+n$gN2A4!(o`G*d1f%0Xl8R
z1LGEOvv>Ty8)yYP!qx$%bVq$TI;(fwrX9ug9Thtv(zRpGJ)rgO;1qD}!H%h0VB*P+
zN?Pr_*r73lx|{RjDh$-mx!xPhK<8|FlJ0dbrO$4JIok-xyt9l#!g0=vXdjm7{HwVU
zmXe(RHvrMo&Q7G5?riG@(JW^(dfsF^mvuqojB_rf_|H1CNl?spHqQW6;OyHAp9-Dt
zP({-PXLB#~6*;f$Ky%T#?H3HR*tzRpxK`raLq{AgIZx}N336V%6eBBh-t>_2?^m54
z?}kRXbL~gqRycpEhEJ8wpV9`d%2`NJ>l){pVR%vN+)pu!YtG93pz53*e};z*&fT=W
zX>@*<HvLV`pFf32v-3iV$=-5~q_<hO^PL0qIcxlPQGhKvAOu-Q;a<JKxQ|wkjRJRC
zfj0||7=d_0z`PEvR)HG}nKnV24X6&mT?QiEf&(0wg92e11~ekD>p-82aL!#czCv6b
zm~!EV$0?bO|9CAWN?z+s#{W+;(ZbT?%b9TY^=D-6jWJrvf6j@a&DvbWJLsO5_#V(d
ztf&0h{CD<1XhA!+?Ba#&mzd&@USABjkL#WSVo}e1a6b8{7rKk1sUUTUjMgnn^JUOo
z*7`kkKfT@ondK=|;I`s0J)S-rT#5hxJZCQ^=L_or%D=3Py98oYH7%IG+~9yweI=)3
zgJ0jFsrzPHF4R_wD7f@(`D+0EZuWYBuCca5@7iQ~K76khfb&DyGW`F#uj3%U{;zJB
z+3=7m={K&XQ2mb+y}<ctOfIZ!`kgANe;GWE$uj<WmxaP_%jp9Jzt5w>qCaMi!~g&3
z>jeY<+EImvr{K>=(C`v`K#6s4K{#EKK7x;_p4C_IV=nCa2^Pl!+F#J}CLjU?9YdIl
zKtX2`L_!6>ghQ`gu#;+Q?+JE)1?GLhBzk-rp9z9-ZHS)>ZjL2O!qhj>cnLjb!i2Z5
zwh)u)Bh+n$3149~U73Eu<wJn+7p79YE<iY>gk+#Fycz~0g^QNJizuO65}E|z7<vvR
z3X|S}r4zzM^b$BJyt5Kur-TRS%tMk<_?WKqWZ_#Uft@0pOOb-p!Z|^ZNfn-?W7KKF
z4Yb5b7dlg-IYSuL3A>rXujyP;w$O({PG^L9RQ`KbxJ&`CERhFA%Cbd^Z&RP>eF|uv
z6>T1ZGv`EAy<p~us&_y#S7eN)O;ny}B4u^*MHOcNQy}_06DH1!PG|sAC`$PWu3Zp~
zdj+aUB(np|MbYE0pinH*P*rV-XrVs_b4ld*2Cy%SZqW(1QW5hHs4~%(nE<;YGNF~m
zRgvi;xLqy^vIAy?=!)?s3|5M^%m;Rr=*?VsS}mGG#Wppf{a-?(R<w3JG_Hy4Zh=`R
zGE!2hUSwMVyA7h2FJPik<o5%bCXqQwHjCb)6zz3U=R7Ff5ZQP_vPE>4K5Nk`^7<4O
zZi<@d{%aFGGd03|yXYgTsp=3Nq>J#D==Us`=oH18qv;a;-VB&-(KgyZ_lQdBK;0I3
zn8IMM=qc^!`b2NgP1`Su_k;Q!Q4_t%?ur&~Lf?RB%p&Lwihib)=RJ`xRjb?=rBOKe
zfoSy<%KtnR#Z&3qBhmUT;0}qZ1K{an(c1%192V76L}f%YJsx(Sh}J~_`>E(P%CkKa
z6%~N_T$CxtT)LQi_6x@1YO<Ubov9|1o<T3oq+18fbdz(jpfXH8r#E+|$p{taWtq5N
zr}am+$&dHJJ!6uW47+DdCeZC#Wl~1>XtjyD5sEb?<4R$$*5v&PG%Y3?s={bBxkvHI
zZj<jr(e#)o<WT4{xkNu~ze&mK(DN3r=>fEl*fbhG`HD|a8Bu`vXL_p#ir4soX$-=i
z0p0|Qf1o?=sCfD}&^RZKrA<(dn5Tk`TyZqrzj@+mrO?k8d(o<|KwPp0CeDj@W}qn)
z&nbdy7sPiPKwT7@O@)WW;$c@XOT<cABU}=%UJ3Qf;;?4)m5M6|V7APNzr+E%SHxdZ
zy#A)?;uv7JnYyF_rrp%^7^n`@syCp2%k=$8(C;*Tlcu}NbaE#Yx=nAsOTU)snh|(7
zY+55k-z!sd+F-euh37-v)$FT!c;RLiOPMWyvmhE$fY~!TIv8kX{Co<$2{L<YHB5w<
z?RXn=8EWSF4Afq;_s)abZ?>%mFkxmt(EIp+**{cJbI|NE6~0H9?fC~yq}i-)Fr&=A
z^F$MC_CJb^Wtue>qscPcMTg$A&4wRfNN3E-&(QputxtyeT(g<RkI<QCX7K@h%Qw5e
z5Plb!&82fq=goH6gSu=smeyjWW-fF)l$pKe4TURa-_8Z|s@al0z*LwmGC;l3Z1txY
zeWTguHgLPi?4K*3n$6}{!>8+J8!2?!Vzzq`)LYHw(z5ubS>!q+VA{;seZcN8n?^C}
zTV}0EV0M|=QAu;R*#dgP+&1G=pwVl#rVJweW@Wi(?wUPC22(s>mhB1kL9>l=c;RM#
zbv?X4WS%e#y>Ro4YA_F*x9@}b2=hgkfEj82Iz26;%x6T=`u~Xe?~BlR)co%*h(?<?
z>mh@}QOc0TnLm<ZgvZSj%D{}r0dIJbXkMj3bHe=ZHvx0f{Ifn#r_7Jg5!xj41<Qew
zW&X`O@FLs%;wnI&HP54W)H(By^MRRTe$NLYx#n@m85+g;=2z(jTws1G0iEZ~6|~_m
zG+(5|L|rhSwFAtH=4<PKR&4J35t<V7c{-q7GM`GLFEt-eZ`m^Qk|Cg6F&{_g>dVdL
znJ`gdzLg@smF5qB0o7-|l@6u!o4fy4w`3k1fjKk|m>;JA@}PNA1)6*2R`jZSVBSNw
z+C%e-D^MIV5BV61kIjoIf;4JgMgh@R=F>}|?;`ob6q2rzbGdNFP4WfBF5M;TZGqw;
zSwd$lJteE?q3b1a9!8(HBx5D?d?fjf7+{D|vhg>_gi7ReJMNP-v_WydBz-NK0}@Lk
z6c0*v(MI;P<RWdGQYF*qjh8NYNPF`P$?4TV%apWvfXb4ry@@7UqNSJk8ObfGsW>Z1
zyMdWGCwYTT4dh6C2B4lR$);6Ip2YZ9G1`2I&po(bAh}90uJe-izoB0!d2bXN7bG9k
zs=i3#l0!d*WD)HoizVYJn^Yn>^8v6gNuC}?-(^V>#cE3>;S>ujlT6wK$tx0fx*o4e
z!s&QJxg?T`1S%y=BSfksF-9s0tCoyUfTuN*{Dp9)R?_qjM6XFWDxs;9yx<{PFY%^J
zph1$?hNel<M0Lu|l2x=vzAoAH9CmL=DyX)iMG~|R{<ccSjfeT05=#n7w@GR!w%jfm
zPi5g95^py!Z%I;j(fYqrGTj`%MVI8CFVJ*L8arXIN76_YgSRD{XaU$O=@|rCpQP^_
zm<Y9S7=>$lEh^uH!eI+>B|sxAUeLNI(&8i9qDNVnQ^4$~#p*c#i?%pI`-Wo{{Xe0J
zwP><{UYx~Z3yMD<w^+Xu+yslCJ_k&qMI5%p;u98izoR*6;r1gylPqlL1XPN}FMk5<
zw1t7r*XCF-J#a18qJJ8E%C|65d1-;g#Xm9nOBSV6Mq6c}poLVmML2EPYb-qf3mIAL
zvqIlBi)5UOFpBFehLeF-Z}B!Aduy<8D#oxIExcl2x5+|P1kqa-y)9@uEw<7Eu*>3o
zs;}<0&~1jn9*ZD)AKbQZ6u?ri#ij<h-Dh#x8$R8!c>Xn*NY_wB^nk@<3N8&=?57vz
zJqt^!@-*JJ=nsOy2Np{=p!1={s*iyE$YOOSu!k%nLV*3)!h+uEBNj&~*ZIW4Aq@IY
zE#9N$;4_PL_aO4zV$nvRy|9=~(UO-IhkQVdT7335s8<#vv>9+2yUhZwxsLsNDjK)3
zmuT1FZXB!s4W!4|fhUmh9Q)2mOqAEyDJP)sJ$79z-1i$h>oE-akG=99m;qzY(5@?J
z><&705IlCa6<iA$J2eu_(6N@Zncq9s=033ZjlH)5)c&y@yPzI5wwS^WN5*<k#P{gf
z+egquk2MC+)Arcdja?vP$L<$ECT{HJuRwK-UDyftN5-bS4Kx=^b^|0`EkBHcK{rc>
zljOc-S2sjFEafF|)YCHRGwAtRN@zFcXL(>9JoLBRya59Yunh8mWRT@S3!nsBwtj$d
zhFWemS^{RTr6W~6AFy1MjbH7cW#K$@9<u!NFSs9WxsV=P5tdVb0CuG1vQ@AYWmz~A
zeMc<K==P7cJQoRt7|Us6(HyhfJ0F;_mi!Z#KW?d=4`#e&<8DYMSU&x4<82x84lvU#
z|NM}0H5ry;N?<<IGM57US(f|h<(6&v%mIpLEPK9$=vhncLo_*-Q|V66wVY1L!UD^`
z7C^7ilBEsJ1<NIW!ETM^#6iqqttG=i@|tD)YV_4vc9nsuxBN>Flm<)T0x%mbw<pl|
z|JyA$wSnxgoI?rJTb65(mJxSa9<u;Ux8>O%G0;BCrHyF%E#q!M@{Z-KRG7bO8MY51
z_bk6V3xDrhM$AOt1IuNOnBa$&%PDv<Y^kDf(uifgIV7K0E}smPr<U(uhNI6ckEhf9
z_uTSbON`=$<qWDTeQD`Vw@jc_&IU9=R;3h44Yp#Rpb4?EUIb>S)t(MCd#x<<p|{Vf
zuL|b(TYXG-MVM8&4A=*(g5Lz#L92v(=pC|hrK=>|N>4kO!&a3kkc_ah_zaT9NUMbu
zj6Y&!LX~?*t?EX>jkc<!+LstB6D!QcF{{iAV8&X_F2M-ntejiX#9J+`!6YPD+0i|c
zXeFX2=?N<Zed*womD`sXXp+?comon@vZo|;ij~L5Xii(*_5fI_l_gaHrx~rbPr)eC
zt!h4iVun@BW7y5K`m7uJ*;bq5(fC;3D@5aKJ+K;*e%AR@;L~2~d(N<X*m~=`G#Kk)
zs!NNsKI;$cDC-1T&K<Sh<O4^et<xxp6=OZ78WxUOe?mEnSnFJhAIDi6zm}p+wsxw6
zr&-pzZD_KsS4KnQjCCVDFwR;JyaAZ2*0vPpEVn+i5HJ<iI$B)TTmM4u#s=%1wQ#%9
zdJmO-G+CQdD6-l5Efylzt;ffKx?%m~Fg$FrPVWb1t2H+j7H(R%8R;`VZPvl_;YGW(
zyBeY$*43-v{w?d{KcVTe*3*Ww+q#!_DLvL7<OAlm_0v%>d#y!>q43c9QX2XmSs!Xe
z-;lMCj$uBwp8g7$!`42_L5)~fQSHhT>&1H@^3?io1(?sQqfS#s;kos=+2Fpgwx*E7
zOY7p@@NLxk=MhjY()l7Nx=P3X4G}kK$T)zyOHWYsqlZ-e5&Ar(KYsu(yrj80P~OrR
zYDoG>_i#}6mHyfc1wU!f&tUpX<@9Nw0O^(zm=BZ=wNd;hNIH|!?7`9phrkVy?xiUW
zmBtQX^n0b7qQKlIy_1M(3zO>qTNg=p{sWPN(p6OTbx1mq-iG1Q-zd*^Sh|e1Hxbfx
z^r3`E>2@m^jFM`)Vg86T?g#i3E!|lIDn?p~lVV2kG3izc&BRLeMd*x^ia$r^ap}I<
zP>h$3)SyX_dMCid38`)o26Ixn$POZ>q$`$U5|X67l)XxpzKR1%igf6|H?*{f_7$np
ziFA%5O=@`vBI!~MZE!QBKhkz8Q~GrWhGfi^#yx=O8EH2~bIwXP?E>gI>2gZw=ScnE
zg85wOJAXhwPx=WxZS$qUMR4Yl^x*@bU6vMp3x!hYGx~x>nbd;TrnS;he~4U@dN*Mb
z>ZH9tfmtsVodZ~dR7zRvM(OAUm~ApjO&(!P&C=*I(6}z0PvN;6(qdbnwMh4^fx%X3
zT@;u%rC2rMT9v+_MQOV<;~*3|q~TPn(<#m03TBryc{|+hmbz1gM~`&17Zh$wU2GxJ
zE3M8#(<faS0?B@97Cp1?NR2skncS5YE`Y{>v}_!>gVNU>z`Q4Y-wPV|rHiOI=#eyK
z2GEA2rkBz8Si1QF6o#cKSJ8|}t=u8<L^_{Vj8CPV9vJ8|>4xJ_aJAXB6HGT7Tgt?{
z+f1ZF3lE!PR3_$SlW3&HhqsNO6{L^N3|dL~+SJkahWu<6QKH%3rZWPH0XE&QgBfVE
zkP5AWZ06CiwP2e!cf(SMjpR6*P@6}e!BV2FwG9Sw(sqLxFq3RU@}QSu`^*u}q}uM@
z1q<o6C3#TDwB0#K_g}W{n73gm$M!E4q7AlF&O`r}ZN~!ib=qz@1**%oZ#}4P+tu`o
z^w?gU4E@`-zth|0fo%otrykl$-h<?@?HvW0C$@4*|30;yI~L6|+eK6Z_S|+RZ7*Kf
zPNNSBzO?;3iN1d|YP)g;?7p(SdJ1SRGH<$`U1dodV9-rAkB7dy>;WZi17tDbzz&rC
zH4iWmvQ5~)i6dnR`!VbzvezgFepEK^E<~bbxwHp}ktIxpWUS0%4o!k=%{3^TmhCtO
zXU@qkCJS-@<;dFTKvS;l_`8rPk?n4P;w9N?s`9=p`>qH2rLsx1@GO&kI2X+o*>yU_
zc2zc&QkLbiqx2h8$iChTyOlE0Ml@BjABVuKmgUfbw?_5_1$1x7-d_brTV&%YHq$CI
z*T9hRri}B3Mw@I|5Xg4fj0SkoA^V+5U~b9&6`<*qg$zNlOBVM6BkY#7-v-qqTT1V-
z+p;5eQ16x9q{L63?6;?|)Gw3XfZiS1D3yfVm4(vZAR3T~=Rkc>Hf<?>t$Q*?3g&&I
zEPo%+9>`KDG5Aonv<<#Jl2uXUa!BU73NVjlre8s0Sf-(3#t~U`Jw%?!#@C?lsm!b%
zlFwv06o7m#Gs%aE7qX18V7`=XafW#pW(@`2U77LEF(q!y1X}32Gmj=f(t|N>tb|M$
zbMq>&4=~~{fPILmqypM-rkm<&BAE|mP>f=B(Hrv!bLkuSdz9&Sh5OOW1$rmPFe_+v
zcZ`{pK)*KQK>?6B=Kdj2$C-YLc*ZlACPO`e`8^zV6PYo6V4h$`jkKIR$-H?3<S7RK
z;Fe*0C<&I#yiVV6Nntko!o+FD=PV>snG*tFr!h_<z@#&sbm}03iPnJ1WYiQ*$znu{
zF~V%7p0>Sb7_}o%&NA<$L-HIG`v#af%#9RKxlHIB%D?6@IaC{!&-By6wSf7=2#xcM
z8718dnYXEC?gA4|37jHkHbvqtGVOWLFJ``>g8LH2hr&OXm{WAd>oT+VU8t8buhR;u
zjIp5j%N1txFotxMG3*0X&WzF`tAfdIq4j4a(|rvZRg4p5imRE=>E%|#ys(03Ewl4|
zfL>#?R83LGOl*hwdd8LPHZV)1U^X(DB8W6G*?XYg%nWMLTxZ&;KKcf8_W%ai!kirk
zs+FmYg5*tRdn%eXX2K;p|J=^-6shfCzNZ?$Ta1#<uXHjoy^!f*>?gprZib=ANe@%H
z2nKI66KMz4%al|?p^vHVgTa2rIt?Osm{}A=y33q82}cJQhZSHBG9#53(mf`(8P42i
zUeRmp0V6q$KI21X$P6?4h*`&g9Adtwtn6cE5q;can7ONlGb4;0S$e{pxdKa18I3=h
zXUsu*)jem-|AgcV=J1zLf63g<hvX>p&Iye76>~Bg>Mm^8Of;_SGRpn9u{l&G=FV=V
zgoTHZeT{bXp6rdQu<OM>cLn9m{!O(YKCDj-Kz-SrS21iqw#*rQ{%kj$Xb50`y$(x(
z>^!Of2x8|^5;>Ti>4ClwHl`MqLfH>aKx8j#Z-9sU*eEmjyPy602B<Lh`(I(<0Bf8@
zbzTSAxg~J%5W6lAO*otDhxt0pE~mG61p7Xvmm=A@t6?dMRU|?22<vzdB1hSuzlEh}
z*1r~miDA1wM{|tz(ZiWoc90Gx#IdFnn>o(PLVyy_x_t}11a<)(97$xK8xI5R1Z(XA
zyC>Pf4<U1kbxuW-#IB~9O=hDM@FInky$R6MZ02K_NM&<3ftkjx9fC+Yn@rF347O=5
zMwrPm|J{bHAH8z2*(($mKf{*Md9|~wn841lr+2`74jXa82r`$gP6L_8?$`k;pS7jZ
zkOFqeMo{P3reDz%vXwtV<N|x*Cyc3xEqM?AUSya3h@lm;>Ca)egx&ZU)Fn1?4-_u5
z72Z%NWlQYQl(C@{GQ7g>UWVo>8x)PHEN2r^==*aOtY17pE7?CD<EN-%M^6E*nr%Oc
zf!46^(S2XbeossCYwY1^aIKDYeggCLY=r<#0~?`3)5zKu!+aAv(FIL2yYnI}U1!s0
zpzj7-_7W&9tjlc}YGn`7v*;!(^r8Gi8{0rH$9DED2{by`_9ZZXi(N=1S)J^r1JLhc
zpHb+cn;lQJFFow@rRclO79Id-FZ(<neSK`$H0brS!F00V4%^TQu)FNPv<DwxcMm{s
zkp1l@4Bcb*P^kYtYq<l%H9laMtijM8vfC(t`H0QGiOwO`BLOgv*+!}}8D@D(gpIIG
z95kM=M%qt3Wvj!{JYx^gGvPTqV=g3Lu(IF5e91nrhrv;{#TU&hwwcmtE}X&wD6ZTT
zGuU(EuH}H~Zshdm;kO6(wiu$GT!kNGytv#W==A0WX%+3m&FBWUFIPmDwI5et0)2lj
zPlTZbaGO8Gm;$*;^MMk?sc82b%vCf(A%ydD0W*|aOqtEST>BeP*vB=bLu5Z!MNy3~
z&Up1IWDanfC{%NhJN6jOA#UD5SPJJ>)<f|y_bYwBAc9*;yY5J?%@2K1Ts8$qlDUg?
z_9%sWyaJA%=CbBOB$d-roH&j1qL@xPXG-@-2Dh5F+nL;DS|et0D`+*D%@rGU@bnBP
zE`)Dqxy7{eI>+T7gWVi%0o9=7a^IE$G>`k_0u=MPm<LcO;0lLf;yh>M&=hhC7bsld
z)>4^t5oehWk&E2A1E7kz-)caWaMjHKyTo;Q!r#kWEA4Jdxq)vf-(SWB%?EjftDXoG
zSGoFOpp|p=E1_7y$<_m=l6$xkma4d37dTqY_0#LDhFkPAT&v|0j)1zxeMyy^b=)T!
zSgPmF&@a-!{c#4+joe?fi)`X#RDaaWeV+si*SW7xQ2oOVuC5TnZsGQeA==7ar+TZK
zT(1d4+qf5${%Gf%e9&}oD*C+4EzU@nM<@5gk8rJv`;bb%ySe`VL8ONZTL<bk7gdRo
z^>V*`1F$~sB7KXYpYx!Q#T{<*Q|R60K4U2VFu>iWiitr^MaAOxxO3+qbDvv5-wk@e
zS#1aCL(a7b)FUn|5O#;Sl}AB6=6*W^YM5KG0eU0ck5vEngp*8%`KR2!3=BTwCJHbK
z&$-lvV7}mLCP3sR7e<T!QBFd^W8*7s1)b7&;eT3(p}F$&b3wWBYFbsg^DaAK$%D_O
zRiP)pBo>qxf8je|d-Ip6DA$L7zZ)ie`CF6}^yAOc6T+V#$wCvrkEaVbkoQ~zksv;V
z-Z8;^807{-_{sEq3pMiJ4ujmwFQ#8+AAg<FAN%>~&%g}hC86-?06&qoFbDZ>IZ%iA
z)NddX&fC3*Q5@#mmSgl0{4XZ(Fp_`K3dtzGIvoa&@LqpI<R~BiHAJHMpC~#J!|$#@
zbBs6N4}W8M<34w|5y!8meb{mSD=H(5=c^+@CGf9rLti3)>sRQX;4{a;?nyr17tJYt
zC=-%N{3g0plKI79Kuh5d$v~avx7~z^RNjqJscHNadMl;#=a)etgZEZJB$Gcvw?h{1
zXq*CWHqXC}DLunGl!AMfAFhDnIeva1M05Bp6uQslpL~MB<ngUVFrUvy(ySNo)3Ts&
zo_|IA-9kQ=;vg6J3c7TP_^EWqT;$(91ge-1;UHPUZ!ib*62Ibqz`V@Q4Wd_NDZiNN
zTFUt7<Cyg;d=8~ZuJZkKLav-Qp%+jEZ+-^)m3%l==2Y?bD<E0TcRWO24c|sTVJ+`D
z8|JU^Uwnb4j^DlkChB>U58!A6ze5RTBY(&g&NT7$^usjs74G!?@$3BY5jb^&x19me
z7Cz4a(N_Ld3@qK`eg6j&ZG5H>itYTB*WptKzpE1pxA>k1fa&BDcfz$Ue)uN5=;lLc
z8`#6o35CdQevlIHz5Hx?O84<Ps*vjEz3+i}ho8|w=TGkP<K3V?z?WQt`9Z#s7ESl~
zzv!zi_xXenP!ISY>G}GQub&EokN8&FIt}qZuK>(re$!!y4D$i0aC?N$YXtR#k8=n0
zl)oW@_s{svtDyIs|A+QGFZfTVL*yktM70FQQ9g~fDX;i<zlMy9yjuttUFGl7s>MxS
zr3B?JpLrL39`eHr;nRNkTXbY2Ox|`LeFx;>GtqZYK0>+BL-L-b=nI#JJVg^BFAjx5
zq<m34M55%|DR6m2ZZ#fukIJWAgV|`KJm?>gG4l8Ap?^$%i7I?z<=<|H-*NJb1bSSa
zL{Zpy`OZCnNs!CmMw2LS*oWqX{LfmLI4Pg;HY88U_uArTN|L8h=q_3Q?%U`~kuTo?
zW~#jRdnlyIw{Ag`F8`$qm>F{8Y95v{<x<LBWyvimgPkpJ?1fKf<hgVJ`K)}b14Pfs
z^%Q@}k$b%kX0H5p3$XL#Rumh}mw&MZeFbvYchPrVo@0uuq)@(__I4NKrh^bElH(K?
zZU^~<U|1-YyV}4)iQK|SRk@esdGtkz%ktP3SSppr>;z1ioTp&y75S(A7|d09#|LQ2
z<>G$<S|P7p1oM^h3uL}ZK1y5DYI*j4G&S<Z<6zdxzx@a5*W?|IkgStC#Gt8{N77N&
z2KnrESZI_xenwlpCiyUBeVXO>m!R{y+@}xC4f!A)!)%f7oe!T{<%cO!b5nj`FF@Pm
z%O}z8AYYjR&<?rzEckRw?(qqlPWc_$?RUvPbA>bAay{+CdgL!}LgBXDArs7A`2YpK
z`sDfPRR7X1zhw<ecjTkrfO}WYEJZUQkGKxBK{-#m!F%#<Yv|vXD|j>y<c$UJ@S*%m
z+T1;o$9#^-8<LOnzyv*(e~|#NVfpLydBYL;QWZRWB7f5ocAv^uQ=P#x`8&?Qd@fH`
z(f4;=$X8AR+Dmz{4x*!SpU2RDC6BFzjElnjD8}omkWK^TrnpVJ4R?i$43vjr3Y8{$
zDmGFC!b>rRJ~!sANTwCNk75kfK>I3Idjiu>v4AlB6(3SsEI@&xB)pXr&z<3nF-WnD
zUgp7ytyItvqF~D*6RNnM0r&SRw3{HaPqC*8eft&fQaT_^@m(j(A5dH)4-YDsW;BNs
zd9z_KTro5Y>W3BE&SDND6idbdB~lUlCYmTkqyxZ?D6R!zNJkYHsJ<xLsNk=`n;1ok
z4PcHbF6TipR$+D-RGi`@WrU6^F71H%c!etkG7=Qe=&JyUioo$;o>0vE6Cx)SmX(-<
zQ;L`dSV~e%puKFeqL<c)DT)z_u%1?w&j56)BI8$xq$%ud;6=K^c!erLGZaZbqcc;X
zq^Dk%VsH)gvlSf@$ed9;*$(De#fe5x=M;PXMU$i0?goRoiWPJ^I8X80H8_*67}UXF
zfnrPm96hh-q%2jTBJntw7ZkUnV5mqDeGFhFikVrUE-4rzy}nBoAAJaeWeVT#;M*02
zQvnpODlX7R8p{<|r=qVyp{C2SQn6$NB2@}2`a65oiUm}NTBA_WwO*@O_yU%$DIC0@
zUZ<Euxu<$XExp?s6l*C)(x~WJ2b3m7_b`~v3Y&8jf4Qz$9E8E#P>iP_aH}HeD==>=
z<gZ|<O>u=%?d=M$&p>r3@^gTFOVRERm`=s$Rg9ubu}}psx)pP#0klVP%MZ@nR{TMw
zNWF@j7D)CfCefO<Uy=Ma)bA)>-va8cf=LzN{u@w4t%K;GVj;Z-?<w+4A#-0*N1OhK
zir^o>e59zN1>lfk9+g!-R?K-H`ooHeEG&&ET5I9&6UE>zC_GgR()Q$;Vz(Qp=ZXzS
zVg7~UX)UOiisV($8&wQ-fcZ)hI7;t77iGXwz_=<sX#MJ@eB(A6cctl%@WMlxT?uSY
z<-;6If|qiLzHH>J3@n6*kJ5_P;=an!Sup6Qj0^$OU-_U1a}l6iL!a>oRHoB?AEZpD
zFAfAN!~WYADWB1Cflwv?08Hav<sn*U>{Cvk0T=fxr_wSuOnHuSd<T>vVwgXuOxp<)
zhm>0`feKe9QmXH;vRVQvLRmQo^+@GAY4A5n*|!kC<PoLIW|%*!?0F0-TIoj-h!~~m
zVo=AFo8O1|Sf%??P;o|O0M!>BS6-ko#VZlH$33Q8JO&e$sN6-LN<N{SJPXuGWgAri
zoKl_~fu$tnXGRPySvlPdO^UKWguc_tt#k#ZDtitBB~3Ye3{ASymMYvbly7_te>0V1
z-UpSXG%JLM*-GQvlt4J6?2kipR#{^Lr_L$eUExfQGAaxM%~hIa0y|GREe>|`mDv;%
zDp0oALjSzd_g^pzl{~HCFDS(&z%Eh-#$xg=DlfXhV6oDgLP{mdvl-~Sq};DXb6L4J
z6C$NbkN>`ZRi@k;2fJ64Q-k2eRb^EH%$F-a`2tjha_YaBph{(4IxJNwcPB!zTKPl?
zg&JkyVK`H(+_e*+*OZ6pVO^)3YX*b$$~zRIX;3~eLb6e5x*UB?O0WA+Z&pT93H5d5
z#&UXE-%$2`2(m@_#R`bFDw8Q6eN%atBCT!8bK{`cu1upJwgXoQByTBuD97HZoc|6S
z?NWM8g!yjeq$!w$2TIjh`1DYDkAnP<lxrwIG^A|bjOMZOV|sQDD|gaarxE3~=@kEb
zqWr25`cIWPbi(_Y(y<Sn&y^eEVd;hPLJk~$sk}|QvQcI7alj<oeQplP6uWhFA*b54
zzKKDk+nHFPFT?I7ZF@8A{Byy~vRe@hX0}}pZT!yK1<^t*$1XbsRIc5JYP$dO?Zmr)
zR$%wzUl2WS=PW^Ip<Oz?WG>hhZv|SBUHlkO7wzs-Myc4Ym9FO!yT>2E#AUmK@$^&L
z6{NzMGP@B=h+MTBM|BS6cJeAnR@hy74a`crp_x#qvP+@}dbM4~988e0#%^*RI&1C1
zDbjk)PDLx-I=dT`aICjmdKpxMok9h_8}0TWVIpp_yP-i}v)%2r(7SH8<04Glu)9KQ
z+ZH>827_p|dw(k=Z`!rcI=#(q*7snx+XeCPsoO4;{=inR-8@>Z_ZjUHts&ZP=XL?+
z@7SHCkpEpfhHBpj?DFV6HfZ-G7#jENQoe)a1G`<5fcDUC0>yS7+0B`UX2@>C3osws
z{hbPtVY{1jR%*m9dMubv?5ycD$y2+Bcj3%4yR~WX;<=qJ5Y!7hqgM$`ytH$qSKX*x
z5DV@ryR-8E<D&YRO4VFdeGcezQ@umSY~58c6i4w;-J#d0r)t%Gh<K@b{{g7C>cYq9
z^HD`o#?DujD92d*RCB6e!Cy6HKbQfkzygdjP!&dNtsvDNBgN2yRiRYu7^0e|2k2f^
z164`xQ<c-VI`*r=Db*0BI!L8k2UJ1r`0);^{CpsCNcA1PR>D;!4X|`r)&46$BUE3k
z16ZUge*^TQRKXPbJEF?{ue?{~JrR=8sup^s$EX4=jUbPy3R{33rz(%fd>vP9`xfJk
zS4B|fEkULJ8dH*}`t}rDJE?k)$_J8EE9vo(teQ=Ep3|z88_}eyq9~!2rt&`vyXmS|
zbgN{jMrkXasWPpHg>2P$iXNR&U8H>SS=BOBZQyaIn&1yFa#V}|0BEl2n*fX{Pt`OF
zF!`#v6k#e*1<}2IUUj$u%tF;W3W!`#$thP|q^eyBw2P{7VUR3VT|EqDiRvFE260K{
zM%Tq<m4KEarK)3p0HsW|9f23|RaM<9iocYr1}O7Zp;|u%zE!GRXM(CyMN{y)T2(<g
zp&Hf4R4({Tm2m=S-u7V>tM|2kgF=;l_T${pchG*y_ZaA5`@PrUMU;IM#jd06izY)o
z);_ih1{3XbGr&Ay|8@hYllK0!yD^@!UuXhLN%kMO0WH~HvIJhF*#AxM-P87y*VD|}
zOY;GfW-p-CY`Xn7^C6jGKZO!4nfB|c)GW(B;vImVv7fRIdS~rZ=7U*ezlF{fU9|Tb
z3%x4)U+E}NwS7PvBx~%qZh+ZZqy1xAS6#Eu{0ZLF+1q@9q1D@`QF%v${dIabHroGw
z68cT{em_F7*?#7EICI_pBZ9eMfA?>Iw%G4`3wo{gs@u@JY5#gOm~Hmg$3w5({^qCf
zslz@r8-2Izo4!I{m;E0$fbO<8zM>PG?hcFZU`!qk*QW#2(_x|$6ulf)(s7<hhfSYD
zG0LHlQaVQ*SX#>;bqIL|$!LdQD%**1_~pMeufwf7V8%IQ(|aV|VZlY9oOUqM0g+S(
z;XRBu&B2$B2c|nb{1-n{hQl@^1tc;ZMoU0uIlTH3o@P6!LSX5<!(*E6LWdLX=)2%x
z?TF^8!%g}r${p6MMpNOifOfx?4x<A=sdiXRDYse&5$!FnIebKw_%|Ic(tY3N@J%5w
z+a0`rf=GwMPd~v>r$h8wiobL@poSd}F^7&cpba}@Er#fbgLMn0<cY%uHGZF`4!_ak
z`MHA~)ib|vc+UfUFCAKKK#e-o?Si_C<9Lc{x;my-K+?@I`crt}?s&`_eIAZIzo7AS
z%xT5wy&QWfx9;P(WDVsXd>!9vM5mvln2x*pJI;R%eg`;SYX?lA<IXQ(Dai5Q$Do28
z18G?o>ewF+{k@K}a?rQW(U$5k_d5z{e-P$)iB3BmaFo3T$%Bse_VDSD<MU1EJM8$9
z0>lxH8&*Lf%5icu{r!z2j=>bQj(7Z8ht34YUF%`#grkryh?9=7^t?)Pd_@&6DUM3o
z8J~8XO3%<#$C>4z(j1rk27~F20@}o8IQ~UXflSBl9C(=J_{n_qWjp?G7R?#Q-!}p5
ztmE82FbU@z2W-GJ<~oMt!)~$Tc)Ddu9CuVh|B_?5J>0+SI7->+Qpeqw!7OvUK&z}P
zj+<z$SMFG_7BCf#pB_P9rQ_6#=xcB+py*<wW5F1xw>fI4o}=9{$Pun}I2J8|+qWG5
z?Z8}gI(|3@&U6_a-=V`G-H!fLN!;VOMgy4Jj%Q9lzt{0P5B)yJ^K?`8J1(a@%^k;o
zTOfJYas4)U5i;)Tpb*2re{ZO_!OE1Me#XCV3iiP_cY!<I9Ug+EbQ;Q2aO1y?vY@CK
zir#|BR2AxD6zFNK>MM9i?;JmYFZ~Gqf-R_?FpUrl(9%9j@FP`_Web`q25?63?-KZS
zR$xyT%{jphs@%*G;BXk8-GartA(AJ!R*EKHFy9R#1p?7pIDB4k_je4xP|!^ImJ5O(
z=|ccT0^^VVATJ8SPouL~u%5DPR|PS+T1{^Y?$hJiLzr_5`kunclYr(Woc{z&Z{cU2
zQ1B6cdKQ$gkfjn1KjAofJ@^YJ{|jb-(CZ^81PZOPAsHmxw;s^J!W?T1DMaXOi{XX}
zcN-(&#$MqQdy6rqM};HjG3+|wm)L!qdWmXizWqh}5ot0F71b>T_5slh%27m!<VZ#R
zH|=w}shDz}vI*$(PliBdK}jsIKPt`!^0%|8CT3k^FWmd%PpV?v7ETwT^T!m)_YqVZ
z%P=;7fz3>iX9P!SsZb;+9QXgfDf{PmbdQSklVS9gXx3Ob<YICliiTjaoJz7oO+KN$
zQH<G00#uKgZTuMMv1Xo5z>71R_yg42r4z3~<hC?~4w4K?KVE>o$I?3$kbGg3HY^0`
zZgYepN`5w>UXTg3IZENYLpF}vKpnNY_ZvjxZO(rQm;{@jC&7zEn+=q=K4BxIRPjlh
z-)WtD%4X&-7<!UT3<a>0ZH{?DJ;i1Moy$6HQ?eJ6lWC*;9g?{=9zJM_Y>Y#n0<FyE
z6h#HAZJfS@ezVP?QGi~zIh_oc8#b4yu&%{s(*&4rwGpgGGibBrQ%K&kdG89S`!=o=
zVtil|?g#3j&686w_{e501w4jqLMi+H*rtN&Vux*N0$_K<#>D`Ur#Ak^NSJ?S^Nb#0
z&uu0=1owqa0Y$K1+Wbfh<WZaaJJ5J#(=rj*F18G<>s@X0DZ%e%yW0npx9$Hv0E&-o
zAN>@*wkEF7^Rq2|3KW0a+L!oYLT$(Qg1Ogr0zC-#*>+Wcx!<-gnety@wtut&EzUML
zg=W^)jNb1jZSPY^C(U-`70hSaUfO~Y=GuPO56Ko=<~{Va+HNDzHe2TiH0`!`e?rq~
zYqcH2?y?<ngr%ppckbfSagn9k!eD^x%5vBXl*w<P3746Ur~3bB*_aREcY-X9QlKfa
zlMkVvC5zk&OL?-BU%{t~vfVDwzam>U9(^^k>F+?YNj7UAs5aT;576|;#-~7JKsIFq
z><-DoeBsP<nfWoAC&sB1jW6>7Wu^R>2#TKgGlvkTF^U72RTRn%WZqAKMi8@}USGk?
z=1mxO2vgJqDwJ77<(GSz7hP~>A0vMs6SSX+=tN%_b8r&$4lt)bg--{W>}u#8V*V@z
zGmiO-?)Kx%Pze;`nE*P|pTKx^Vk#4vDHK~Uo?x<i0dtc1<`=ksifK|nG>KVw5=}C*
zayevDn6-#hq68@G2!@u*tfs(H8uLHedZ#mCbTA`>+4}?rvlx&4kj!S(^bPbg%vzf6
zv&@f_n?A=ldZEc-T<OJ{%VbcxKF`RM(m?Z>@TY(&VB%>@d7kn74VDU-^tT{-fiXP@
zm?GxeN-!@nd!|CMn3=K<Q&P?JAH|p&nH$c)zR4s|Em=2{;Rp}!GGBiI=ts=XU%-6M
z_<RcJ7mP(6BwsRJ??HW(F+QQ1>Q_tz?T=m9O|%*dV6TfI6UeTmphOURbS^}K*~XIq
z4Ph@kpf8loY{UfZW9R-3pZ2r+=`>v!YySz<53sq*p?8qQxi|b2Y)2cK7`Bb7gpRRS
zj)00~tzG~uj!iW#2KP8S?*?GvSsVHQMFKnNV=xohH7_B0lJ$*7-znBU5q6VU@%xyk
zWY#+Y=2O@|sdVTx`|vg-Q`wAv(4?_rD3O!HPP4*zbJ@rAG%jFECII?8`wKN!*pjb-
za+Q_W86jH13g$tvlATQ@42`VSGq~TxE<Fm->+Gp`=-*(M(4M`Eoo5ecx>?gOP(AGK
zHZ-@{6?Y-h%W6U~ratx$7f}7|Yb9vzu)Q^azRPygOM8Hg$DE)L;+`0W?y;ZFr@#Ml
zpUsQ|`GB4EImYymE!_o}M{G0&s~@u~)<R>LwdL^}jIi?-f_lPgzeV$u)lS9;pRpqk
z;plVrS9)H&V8>CF!b^5Ct!PKtH)+xQisfj1j0%V~&~xP!#~|Xy-6^KOzvRx@JcXhM
zcc}=Sf!xN4uoT2)2%r(nt;~aH2-k@02}&5$lyBe14GqDy{oD%&I2y(sqD|{D?iqco
zD3;41kvPujGN|KR=^aSMbALtxGlAn5fJ)@vryukL=h6f{<4JBR)ia&q76+p<i3^NJ
zlgurshchXhYbRVg&Am>0-&F2*ycbc|z|bX>!EKxk&`gf+29?D{(u+2m+ZP4u47Yg)
zX7nr<KnePDoD01hbGUUB+05mBszP5LH;odp`9^La25uB^S(L;-&t0Nlw2&KE3KuVM
z*3-Z&;;I~>QN>L-2=mq4OFDd5%dJd;-Zie^H82~v%Pd41IW0})02dd7=^Es&O+oXV
zTknRx7u?Zyn19J-eFY1n+^R3Ze8m|*r0|#vznX)muKddH;l3N6a0_<b`QWcHGame?
zGYoq2KU1X8i#L3QK5u^LO`!SkC2s)6mml$gx*xAR3MzoFq{$29Z%Dul;_cT$FPPs&
z)n_66$!X{d<@-wky_f&V*o4k~{AD_Twx1tE>HaW2i>BrP|5q5OgM64fKo9Zl1<()Y
z8&-mOn4eEaDkAuDO3)|rCbWt=!CO)w`6OTW1E^Dc6{S^^c#kcBPUd&bfck0PvjBEe
z`BNhpQW|gjFO5E(|FQyJWbhNIkT;XxS%W6}?LMj$OMm;V9dIV&Z4G6deWus0g^8va
zu@*4VF(dIJU|!C$rY!jAEb~M#_s-t55zV35k@UC<pM9M^H4`yA@if3PXV0YNV)5*$
zb`U9<y?F)2-^*w3raS%i>>*l$Cw}16I2NwrzrRC*@bBhd?f`v@?>qQ+t9UHD_{XOY
z|88TeVPN~O!NA`!yAG-@0=rqjbrq;@f^riSM?t_(uxC6_`~|D4;6b2Z9<4^h1e%Wk
zaRB?DUoqArf(i5#KPr$urI8DIP0*Pr2%w<f3Bdq`8BPk)H(;tx3BI05(;;{#fW{;E
zVka!+39kGKDqoN>1x<k<s2PJiF9`e|RGA=kDnzab?5_j!szB8S3*~~R7tz-s_&k;J
zkBx$lDRkK+81#gRX2JJ9Fwr4+qZWO)1Zkh4=@jH&f_|4^#k&|`w_u?sKzjuBl)1Yt
zu<Jozui)`3*zFVKoj~6M!P#M$cqn*>Zv97sP>Pcc2`VYA_E=C%rFky}?=PU|->4va
z8D{8}ASDT2xCn*xUUn6}TMMR}@YjE#?=EDi_|QX`K`@@e&LU7=!Uo!#dJ7jFg?S&L
z%^G0)3X4$HhOK}TJyZRKIm;j!AS|IwWuS0<Kl}|6Zl8fBSZKDN;;$jX<MhM}6&6kh
zcdu{}EgAL+x3NImFZ^gCu)~C}SwQ4~u$H2#2ZbyCM&BW!$#*ajF3ea6M-L14QQ3Qh
zFlaw~iWF|9qhwLSDhfXx5zeOLX7R!el!8tWzH<@G)50EloETGuttrq*6V_27XS#3`
zoqNm?*3$MjSGbP?8hOItPl25;eDXW&76?7up?^sj@)P<l3l9cEvQ(H)@vbuAd@a<k
z2>F$8?W*v-?NBHe?nwpo4dEa6pw}Y&H~?U+!owS&che~Bq?CJyP}c{=F5#qw(C8K_
z0-)a`Or~=Iw}n36(C;g(oCEj!gt=7f*)R06MBg3ZB+C4`h}@i^;4OMAgGi9*=Ls+v
zCTgSic%<lp00v`43@uMjiEc~*GfA{69!;{yD5PsPMI>7a^0a7)9+RIc8XN*MPxN^U
zOyr9uynu%VqVcc6?s-v1GeinSA#(Ix5bd^s`HP~mSujy7T1-)j5|MQwnoA;AN)BGe
zXB_}tD%x=a>UE;8D&WNp(eglu+!9HQR3XtPDpiAfU(`?njS-P2MdU_B((j?+h3_k1
z+PqCHM$zYE62A<TuSt6q^!-e<v`_apd5a>w0VdtcKpir9{sjJpo5ay`<FLv02SAB1
z*}oo5q{-<>cpqib_ZdWvm>mDj2=}8+lIRf;W8zc~m}4d;M*tIRGM9?}<4hjXw+xP(
zG)w6cGTCN;V!FvXEBJfP<Sh!m6`DjZhEJDG=EOj~(&P$Vvh^lM=pt`1d0hmBPLrPJ
zVBRrFw1UW8lO<G|K420wK<ocOlQ(JCb<d>K3B$f`Vojws4@^#Lq4Ch<{Fl%lHL>~v
zUc53H9)YBbIPx%Da}^I!-KrbDoCnw3#h)cY!2^F36DB;xA*V2UZ~WmP^!bS2>V%}P
z_(m+i{KQ78L-QAVS^T&D7i($36DT&PAWe`sqYl(Tak@KX4vB*hP7;TUPsae}uz1M;
zup`8G186SA)%3QC60eSd<Wcbss<Mn0*Z&EW7%}IG5grrUQo<xwe99Tl#Nk{ZP>zdd
zP;N0rytDx##?#^~imauIBNw7GO<YMufazjA<pVOr-%&_AQ*4nAm@IKuG)8zvTt=I(
zv*Km6uRJIIhSE(rVgapkbH%IZ637$Jpd4_%c;-)F7Koky0m@}@;3y21iszh$LYa62
zm8xAaiY>j-UKM}zGn#UIe;Rfx#8Vp}Qz`DD6L?kP#@W!X5$|dRRV#k`HJG?2UQ-IU
z>%=DaV4_}Ja}iX7c+EMeH;QAH!`~)x=vo+T7O&e3=pONWO26C|Kcfs<uXqPOJ|ylF
z8_lvYn0~Q0Wzg@4Ka>D_K-~Q)^asW3_CoZY`0;Uw+!tSr2J?Z~w-%BQ#nNQheI;J#
z4yKD~kQ-ccH4UPOtD9*|0I=OnuWv`6hw0(jQ1>*IAApD6rg`Ha>0^5R9-w_qzc+pa
z($6%u4vPM!8{P$IfT^__RG{hHG0-?{+F}lv2vbv9IYgQoXhj)i%2Q1Fi0K!fgF0$@
zn<CTErg}<v#+WJt;bE+4cpjkROj87)j+?I92C#V3-mhRc!F2vx=u0&HqsNGOK4JRx
zUMQY49diLPMW&@+;D^0v`XS|X%1wjv;r>n2<%3|hnRaf60;=t<!EU125EVogo6Y_W
zXeDOmfnc_nO|JyA&1_~6)ceiGQ1a-3*%iv+J~2C!4zQ<YH)*}(Yc8vx_^Y3J)qRX`
zzj=K+%pWyBuoE(A=0Co|B;=Wks1~Bw+>8UW#oW3cjy^Dti~y*&#APG;_DjBKgZeQ^
ziUeMyO2lj7#sBek7jRM>>*Dvjdt`TK1$TF67nk7fvOsW_1r~z4g}~tM*0{S90)qq(
z4#9&52<`zw2qA?3Q#HTI$;tn{pZA{ozLz~Ge7mZvx_hdpX1brQ?%5jBAej_77BWyB
zf*udaQ&{Sa^W=|^%!!^JHDuE!d5X$gUB3T3w+F~#rg}!?k=$vXuhh8c8J=OWQgNnd
z`fJ(lIi6N(Y{6VlKlNPTd7d{<rN{!$?isR$3q8T=F(peq3nxozndgf%Qg6BE_(Wlq
zXK%1nU+al!EAuvZ#$A@`n>{-w%Jy#YJdBok-fujw)VQB*p6cq!<33M;H!^d(=bd_A
z?eJ_;UHpWnMjGLi=lE%9gfpIA5i;+*r_499ii@5V>fscZJUIr*R$TF{ts)D%?zyVo
zq_;iAo=cITp$|&P_6`p{a#T_yL#wou^^Oi*poR%g^oF+UEk!4XHvC$c9-1<*)SnqT
z`L#63?9iL)%XnUBqSxwhQ2w7}N?-Z6K_WvI^m$D+sITF7>XWTeeKi=h@lzFkYLeZM
zB{hwSlIdn$mP>x~VY_6ZEvn9y{FpVZWVJ0fIpyEjMVZz3$5sW?%jUKIJcq2Z&6cm_
zmBz{4&=N1)t*#OF9`>cY+CF*I7hK;3(_|6-&Z{r*{=>`5LI>PY2U`R0s*#g}j=E(z
z-Y%*+hnVqI2yLi2yszX9Ge4%5iWAJIYV5#7bE5kApJdj}sp9XG&4aTfceYuvfRveI
zzHBH<pKG2}7YsI<JNnC3`OIC9WodiOy$9q)9Wk@3qu|r#HaQ9QH_I2<WMZLJK@D|V
zWKGy3%Uf)9R#EyT*7vhzWlODeS7bw1SzW41=4vZQz2i4n-L9%Z6dSEJdnLKa+8a-1
zZngHiB(=?IrY_R^tdpaK?bb&%if^}dNnM)RW0lP&tJrHzRgt#utjFrU)<f1AHR$TF
z_036H(+Mm2NLlYmD@2VzIcrTEC`Ha$cMr;zpSM0!$4nQjGKp3DU$OR;m*iEe?sTbf
z&01AJQn##S4oTg%)@77k@spJ^r_{e=_0mVdR?I<J?<4D?iiAG4Ua4b<7uN7SlKG3Z
zVVYEUV|h19^<S;>>J9VW+Lc+>JJ=DUKG<G|M2(kbeB;S3SEOY9Qs7V1R-dsS&FZRo
z23r-?{f$GcmqX;047K`Zk;=m?mwHajaO=BO!U!v&y0Lhqm05*tM_Ki|OM8sAUZ{iZ
zF;+bNHETtypyoI$-VIsUcx!tFS?L68o%(*9Xf1gm>ziav_o^EuW?S}evbA%pHebuk
zxmJc9GIOOh?uo2vwe|faLfuLFs`KE_t2dFd4L5d?RW)jTOR6`nY{|AX2~#KVO`}Ij
zezTFcWeLsOs=!2x{_0A3%)-60u$Bu3O8M9kYBXP~tm?qV+d9`7S!kP<V`N6$%41TY
z?cwz@-R@zeETVmh;Zm*3)>88Fdd^W7wEJFEW6JxT&nfxC&2`nK@(8np8ofQzoKaJ~
zD08NI^z~%(#u+I-#hj8zHfX9@I-^vWYmNz)R+wl0aZk2*zL{>1SGHlHS-Pv_E-|~R
z)hst(gbS<8pMR0ewPtE{?7hL<r5@OH+AO0!a?hAyE94cNH5;FmHJvl<SF+yo=8}$*
zx@<;$Ce?44bJaQ3Pi95+_J3?{aLT+l<`gy7;&(I86)Ez;Y?N0$fB&NyT0)jR#5$fq
z7PHVYC&?<dS#G(&;qP5@)bO$$X2B?_w9~B7Q8sIr8S+6E_^oNGi<`U6uL}x$%*Y^l
zS$oZF^JPK%%wg&z`<OW`nQXyv)2S}|oG{<0*w0DxhB{(BWuEXJl-%#leOF{@r_E_0
z`qfoZL4iAFwvy6hcg_B47|=cQ=FhU2=jJ;VuzO(^Q*Hd4nL>TqzcWK_%hHBg9k$6<
z46_=mWBK7$TXk#61Z!bmVWPE3T?CqB-8d>GXIU5K3bU=c71a6X9P7@H!cyzPG+F&J
z>z#^fFSnMcfn6)CUsXTcXcbZ)kDIKWMWx~ntB4vsywhsCL)Ns*%5+4ke`}3ZCl7}#
z`-Ws5w(JE`;fQrW1t^bNPt*#}S_5Nc(dVr0YS`|1>p=l^{&~S#tWIohSksTo%pc|1
zfim-^^`&~N-m*%*mwC6Xwt1zU9$Othmw8XDT<YuLsTHfjL(i=Ib%f_uUv=vB!m64>
ziu`O9QxD2|X|+%zqh49V)m5_BRwMQC^NVCk>W%eGhKhUTGa_`LY};F_<U`rg->gnu
z<fXl{lB=WX->u%~B=z1Jsm7ZAVZCo5OZ#9gRU^U1J1*Rn3UeGe`pLY-j>BDLZ>@6F
zRvWX~F=m=@$WgDgWL|NMQX!FNjx0SSbBMEJ4_W4X=Sg+i>)q)5s;F$uK4+P8ve47c
z59+3$ADvVBNyXRBrhSC>&NbWk2sk4TppZts>Iy!m+RAlZjh?wBzkw^MJFc;FWl8s4
zN&8BX$F7IxWu?zutvbshUb#|_lag;;^IFI@|L#hWSyCTex#FwO|KaW~w^@GTEo!_)
zqu<rZXp;rkWI4?mhRR}E<W<MjEt71Ox$V1ll^5KhWlH(CS2J~*&^zrlneKC3-F?w_
zTrsIN*bG&pP==V3)W^{n^MV>gJ=P3W0iCJl_|CHUY39Sa>iB1_Ir)|(=b2ra$;@Tu
zICT|dxtUyD>|Ae_sV5t_!Ay`x>Tfj9UXgh|bA=ieyxp|bH{}lV`c$dD(`@>ORNrN0
zS8@DrO>2y7%Wm`0c3H|Eb8sIivez7BNNS%s;HbQo{bmbwRNy^eW=bO-G?z7&Wq)Tb
zD=+mAnYYyE%we;Nx}bT)+}1&g95r940P``kiyAC@-0c5RR(Qg^p$5U6G*^EmO>oK_
zp|0kBZ#L;KnWxQ$-$}hQX1&XjdDcuFA*plby&q&_u9~N&OUqsJni2J+y{?;clgpZJ
znBnR$`A74!N3s<+%~GqR%mXu5W?A+_vsPOv^2oeDS?WJFE2-$<6VvP{%YJHROCd{n
zX8x%zTs}AFt4qY2EK6PS-DZ7XLN%9lRqdpm)|Gcs@>|Q8EG73@-VVJa_n;NgLSEBh
zYk@lBKV~^31Sj9!eN}|yv}He&#+NVcR#M}t_1O?9a>trCQZ{X{<3vX_bVB~0B))pB
z^Q`rKg!$GlKB>CEy7Pl9XrWc~pcGzY?JqB@UTmcuEUR2%6&fMcyi2VLr)2Y%Sv%cQ
zbh))bzU|~wC#JltWu?`qy;NLf4Oio<R$Hf1N{uyEb@k1();bU&CD&PBUz3vSt%n<>
z<OVDIT}f@UlB=lWCM)T9No}@ns2d5swz`<oVm@nyx+uHPnzdZkx8G}>QOE1YtdVLE
z;Bl+*HQAUGmU&0YoV40hkQx`QZ@bCrf3R+-@#B}Q6yHedvQ_AS)VpOpDkU3p+sdm>
zw|}yVSCx8qtWhdreAl|5Lh|>l)Fox!eQSPqsrSILkIFVZw0w<a3m;kDX&q!SkF6FS
zDf-097%WSBYDFBAqR*^BxuocG>&Klk?}fExrSR5z`cd8mzgd^p%J#mq>Zu{BzgyGO
z%hKLkJ>E#>AJ+V1Qu2e9udMK=wQ;J<8|kQ!Nt$bvV~_gGoaCshKD#D6CV5q?c$VXE
zN+~njQRXK}Ep~KQv7IH3Wonez8pls_RC7D>tE*UB98c76nr|G}?@P&V9bsdI-Htvg
zEO^MVLye+4?6{^z5+89inIk37IIg4=&N^zS0M$9ihzqh!=N&E82k8aJtII0>a?#OB
z-J<n_quC@`?<GgoF|sk29U&`Zg;yN8he(mDjs`VkW3D;sn6m8aj_+Q|yc>>H>PE{S
z9naJNmYa?_m!<kG$7nTH`nIEr>g;zN1JqT`dyaMLobtZo<#)3B2ac~xOTEXAk+0P8
z=M%@V_mX_-XnaD7K6CUPD5>X;AD+l!UOJ8hOO02KLrrDbuN~!<$h;4Zdn07ogPoZz
zsW8Nu|E<g$>a5dD80O5`TjmXS2CLBQ2<MWu@<K;DOC^-8ALD#lL$-dr^Y9bdm<dkL
zYIXf*qVtV<2TpPpR$~GuJ8SipnX8?9OUZh-I9u+K8s9p*sPMvf&W{&`lg{H?B=d>0
zpc-cJr>oF?*^1Hb44Gx#c=tFJVV~%puuqE2bT_;%i=N{yvQ?Hj*Ij+6q~^IF_mM4}
z@BTww-S;kV4}2u+UF5EtR5o~tJGP>1=`wd|k1TYBd#t54#@%;}dMCJ(C6I-#br)JJ
z^VYd1+>v_g-PsPv%iic-qfR<Dx%*ueHoH@NsYW5m{}V55A%z?D`6x9THxH3DHu)-C
zR@8K0Guh5&UwYLI)y<ETlR_<aSCW6*7I-d8Xjg5POn<SwlT5e2@l49}=v7oI^sJU%
z7SyYUI#TG}e}??qC+d!@rf(|s(gwVIFXe}u-c+jX%>(KXV1k*YrM!lTX66L4lu70w
zX>>U_eR5Yeeu}x+Ysf2`ZKhXYt~sVdonOy2@1GRrnI+VFe7<?_o-BHk*?E_&&1c>i
zDNEaJu26^22hBr0g=6Mob^dkQJQpboyJ)u9F57s`46h}rpUhYHWMiI~8y`vLuja~N
zS>|BttvZ~UVoh(P-v5iOKjg}^zquS~C1bMrRE;m2Vt&XYb!VHe)lk1VrlszvookL%
zSB~eI&5KBtWoFqTQgXRDR(<`fH`C9QE#F{PUn><hn#<MK^(Hf&8a}e!+*?UfJItib
zqycuCA0JBQLDQRCjVSoe-1bCX-AVIKoTN^f*HXz={9w+>FPWFj?&|K~o92VnlDcI+
zP$Q&no7M(-1wWZ_b!9PYtzRoig>}|5H9B>@RYb*TH&`#!2m3}VmpZrEWGyZzY_{%)
z3twBuRVO=P74)jZ`kU6tY*K%rBS&drk>j0;=PY)dQse!XIJ%m$-ldLrYQWMmM})dZ
zWVxe6R;jnbQD424S2{X$l_IMghg6fScJv=C+q=ebF1u{nBxj*4GH<f8ygFr^;*3#W
zvs0Zp2FUB2<}5V9EA^*4v&!+6Ylic+x>7gOS$2nH+Rj62^ztm{5_NrYwzIt&I6ueP
zBwE%x*I82?WsGp2sI6YTyI(h1?*@0RG?Lol&ZNG4x4Dz58$P$Y_x&a>;#+r}O;Ti!
zyR<q(+UIW5UrHWu=TE4{-~Q@;K3|HC56Y;<e6I`2o=oZ=37WA(QpbZb4Unz47&JDq
z>P_<hM^@1YS>iLR+*aAHmsS;ZvHXn{GhH_5o%N=Wlpf`HciG`Do%o!(=c4?Mb<!f$
z?<JDy8g(wnx@&e-gClEo>)@5zwa=+*>vf*@kr{QLCy}K`hb@!(O~<~K{AQ2d$-m7X
zs}aX7x=TRK6_a{}tgK~Ab%$B((0Wp<L&dx@-7$;0xZm@OMza0Asx6f=U-ebTpaWZc
zCbdSG6J(H=oF!&e-%g{<vg(4EjDPb^6vvp2)y153=D<Bt;TyB@K`FD-9Ih^b?K8tv
zsO7MkcfMqvG$%y}=gizYWz#R4Y1BF6k7kk^lDcOmbW7@~8CF7G=^HcRh}8RFUWhOA
zhFKePOT95x&ej~UB;MCqJ^!m>_axF3mE0SoZ14RlqVm@KUJdR2&CHZl7W3XLR#X=H
zhuL(a)c<HsQFrtVw#HVJ%wbm1BvNv?wdjPj!YFI&SF)zjR`UB&WSX^olPq|;6%`?=
z_10HyB(>YRb=&aon$y-QTOI#iwvJ7dWn8gV+>j++wMIlpdt9^jw2)fYt%FfA@4i*C
zj8uMLO~@sw$5!)`vRzLscQ+~d+#0S<o?lolb)NRlN>)u4|GRZ$ylm`P$Jr0UM90jn
zvgoOfK|SO(PIsIgCG}=FHp|PB^-J+2mDSPKYxAu-arni|sSbMInD++BI)61!&5)P&
z){Ijzn%~Tp#U*o?^{kbC*~!0>b&j`M6_Vvnu(GPd+!<DDX+*hJ_q956vaOMqBy*t^
zUtKR<WF1#WtBb8ss-2ct7oVx~?={w}g0lLx)|DbsW1V$d?dESR$DgvMt=6)KlG<%u
zQ(qc;tdQSjO^2=AzsO>aSn&o*8=baJsBtQ1EL&ZnxoR!XBqgs|#nj#A*R3-hB=d$f
z_%o^Zqcvxh%)4o|Ya;b-SvzF}ru_c7l~zUNB*diN`FE@X?c}Asvi@i(tAB0%s*YTL
zvDT}DkT+JFB~tNME33NJ_nUQ~o0R<Bnms^X+IwsAJxL97R8m7(hCB9Wlp>29*VLup
zwT@P52-{vq5)~!5<jC}!EbOME?_(+Aedb7{&hg$j4%U{L9~|9JOVJU|FV(ec+Zj||
z7P{8Csgk7jI3tcr$<xmJJ7g>FIA^Yul5d?u6UoxXxtgmFtr@QK4<$9%^<k=P(-POE
zD)M?)xt8>m%z5r9>SD|ScRh85Wug0Fby?pcuRF~j(lo2x#nqw7TK8@>zGj`fjQZ@`
z;4ZXLDsFa<yeg?}?&hD%R`}er+en2S?hB*jO}NWlPTiXFt-DcP*|a_GoeyM%``o?M
zHO>9*^zo$nLHEv7QvEwQdXRdD+<WUu<}vqrH6Htv+xwxKZ1?x>dyQplPP^l)&!hA1
zua|H>TDh7!O0UvgotjsjtxnXcb#+Vq>Lu$*PK|w|WgBYFRvoz3y*W~~cKw$!w@!x(
zQmgJd6%~oL)DdI7{(s1H{Tpg48?4JI>-s!c4Mc3{oukGFHR?N5URvY(YMf@1PU`r+
zY412$bhD~=Wp0b*iDVmN5(UeGTF!nbIkB^Um7G>j21&`*6^6)y+T6J<ONd*#TQ;$6
zadjNfF400M`NeZ}A-etHcv7;%!2B}ZvEVG3+v$ROD|N0_$Cepg#>|zhu7(;Q*6oLT
zvWV{1P1%$l4_?c3&z(6Wzwe$pGCiPhQOO@-CQ+BwN1H23$wKy-5==9ULcxaNFs9mP
z{*(`_$g<tKb!y)_wpaVEU3x~=t6#G~{_?$B#Z|3PF>h?QZjt4?cIg$@rB~0$imf}f
z@76OevRkL#?b=Jp87Zua={v`^?%K0(!I*q`)&KHG<u4FbEMI|qh4UAV?A5hvr=IqS
zk7m06-Brw3XZ8EvU4y;bw6gy1uEMw6vI;r8#|_ivs8Fa-WTY#8zLF(f3FW_ZC0&kE
z)m=_U!V<3VcCMhjE?1;0sIe=orpwu`gUjLQQZ3jpO_#i1<j7EV>?}znE!o@U7<tK+
z`I;+jq$^`dSEfi;+LDp7+@MI8yRFL=<w{q;l`%@?XI8mUE_W}N9p$zXCqFFp6FNfj
zx{{Z4B`WDkUDB1TWOY~i>UJ}?mEC+|k8oQ>QjeFul32EE)Ft`5(%zM<y%djhrHFJn
zBJHDYD?^2_f7_^CQr@cJax_-|n(eL7f17*KGM)0R<k&wbuglEfH07#-<un}!eDQ*;
z5$Sz*vst}zCX0zFSG98GiuLNpl&w*<a;=&bYt@g5Nnh00KiWEC+SA54lK4i{x7Nk_
zN^i4{r?FqU-BG@f3s#AQ_PNDYVmrg2@T|U8_pSH|?7Pvy34Qb4TKnVMZ}Ymd`X&cE
zatHaY$8#hx<5z0msaIT&vaNfy@1whfFLeUPs7!Xv3}I>QEZ=$J`?eHxtjS{kFg_%&
zo#BR+#5c8xBPcV~YR2|z{YBL-ZQ}a*jt_E-46>u-VHmczba1ep{pXNOzAhsj*R#6n
z^=ebKjc@UK$2OO};Y3IQ+q=av&8~Dmq<}jnre1W}n)dB7p~>xj-#F&_>TGr7cH1kv
zg~YRK#0F*d&DiC580Kmn+a<b@Z{1PH)=>LM@zCtHH7G2ZZ|eoe^B_BY>!1|A^Vc00
zEqm9O&J6aAn~nv(X}27g6WDLYh9~r`f8{9F+OD!PJj`zN$d$>L=5yzQ%=Yy!osst9
z8lm~@&;ibwf4!WZ9jmsf(!Sjn_K)YnlliU;a0Yq8{4M0q_k9@QY#KkLO4%AQ72-O@
z_V+cM>8#|iA0%~z+Y3jBdVJO#=frg3YJT~$wPNb^itW+MH))6SZK$0vE;xm6<RNDv
zkKJ&KBfGupwDYB%dx<O9KKaoZY!~`ID7A0h8D}Q99hyDFW4BoEsNg&FgY#-iyK>?1
zLcWDBoxz?&YN7S}Rf&sj6W61D|88*=;@bN5zjrQe<7(YAu1gzV>z1zJ4W(7fR;pUt
zzP&+OwR1%)*!S6XmucBeTZHBG_1@`9kldbeR2n#{VNe#|*mH7{mbDklG@>g-MH@Bi
zG>EC+xK72Gs?ilISFK$urcT$M>GKtCV4t01C9%`h4RhO<uQ_F^cu+Fi&Jdj1cj$sV
z{mo8xHYAI0z#}<e@J)W|su8j6z3XMDo$t?}q`nM6?)?eumAym4?Ppd{u>GvI+vCfT
z!d=)I+=F%dTBLE$PT)%u>E4yztzKxQqIUNwo>X@HOqScqpWl8`%$eJlrj9$Q!%l98
z<?&Uo=k{1hRmqC=qGRe;EU&jSyKHC<!_MFfPVVd6!2QayuT%)h=^NF^y)To!;Am(8
zU-hrt#WLGF%Y~%(4PWHG>9S8d!;|}3uW&c<*v@W2DSbOOxgWYb@}{d9+rCq)uKj$A
zwz*rm?14ueQTD1kVF`SRzIFGL<z8{ew_}=HF1t$ykK5<l<E|Uw%YMq8BC*H+o~hZj
zO`NaHZTCBu{bw47+t=lR`+fQp73)`tsZ+mB{d(nPqwCeH-@w1w1sd2d?>LkDyum@W
zO4!97xFhY?6@vOFQ?D<&QoiVzO0_?a&gU;%ut5&r+=@ZzJ@)>ho+Nht`c^96+1f#M
zg6shcgVXuyHVoQf*?CWg<?!Wi5)>L_Kk&Ko`ntsiZ8GiKL19UJHCqR53A1l+36Auo
z?H2URwA1BwhT9tlIa1rL=LDy)Q}qbCm#ksK3YBBjHm3h;DyC-7j=r=#gED8g>qLb_
z`O3`=I+e(7`Ezg*d)e2{ly;||gCp!MKLsW5726o}G_CzIz9YA<?)O34v)jR^-06L3
z-v%WLvd7hMrVCPUsqFcS`YQYxR3)uFeWxdtZ&B*ti=lSBjX^2wEnirPeHC&94-2vr
zUUet5cf^Eeu`9oEC9>-bcDa4GqJr}mG-K?S`CN&7x#EKB6t~~5a)sMdzi}n8TPBb`
zwP9RXko|UAaD3mIg~1!b?fVU!MS@~tD%32Szk(fG!b;)mw?4SN+s-^FESoR+H^I45
z+Ua6F8GW6;5ANwq9O%E5<9bE+s~Oj`XKcGT-;d{lHwL*X_Uk1dX5+60Z%*R-^5<Yz
zGP}Z2Pn6wup*xXXrkB(0vx7o<M%cer42^G>@8eEpkJ;`C^A$@Pk|dseezPM<aDKfD
zqZ;^XW(kQlGXz!@-LF#nwq2uY_H0*2I&%9i?aIe?>eMQ>bw}TVtRd}PzI3@m@;U9d
zp;m+))6C(v+xtS&`i4h^ybk(nYvs_TZToiqx1R6Yq9K2V*xlb+$$eMLg?u!9j*21U
z)7k6ydt{5(1Sjz=YZH<+%x?bFRlxUCw~!}E9WgPLY%^g{YJ2P}M*`oAQ6UeUcJ5kX
zX?!6QLi#!FM$uMA-;gOGeKXpNc6cIvzikO=?y%)if*F0od?C3K+cAyY*?qT9gyeVG
zo+d$gd}Ysud`xVgst}ab*Z+RV(hz%5|KMc4RzHWd${Qqot8M#EhW&j%Pg392w4Os5
z?d}&`MSTm)dIqQSm5ucz53%<@k^Rx5gQshl-8MWlfqis>JF#8+n-G^>D{p9sy}W*C
zN?*dh@>FL#<vw?qJ$jcT+;`+l&#Cx!?9iY@A^ta5e(5PI$9Ym^pi7pE?b6Y=f1PJ>
zXoP(C)QzcHuB!T0jWX<NFM?Cr8@GFYwfDtyq_PL6l(pU2;aQhBCPsY<)~jDJI;Ku^
z#Y$BhNqPJB>F`9p{X0ER-S*-E&Wv{F)~;l}Yx_N4xP!_@*N-U|9c?ep7?#GKy;{24
z`lFs@$?Qa19i@CTZh6eS_P9On+`jb@p?%Z&8s-i4x<dosF*UmO^<69&`pRYB?jt*D
z$D{C2-|xjk4}~OYP){wla{W5d@{j*hplAc%?h2uIgY>sT^gq58&ejP1GRnR+!kN}r
zePC!ht5Rfxo^d^TMz)Ua(Wz_C$O>Is_wKBZbE6y9uM*j_TWssNm|k(Qog?M*CQtd;
z9&KXe)2nx<xR`of+xF@k+aoTrLR_of?R@RMp*cc)t4D{vDQ(xj>Tubuf*pB%r;dhx
z8Q)$o+u6of=}PFbcy_}4atM<C8%J^9<A<Ri&4l%P#CGY~xqYw7ow~M)?Nq;g=Qw*&
zM`to$fhVDEhp*=I&{?7O)5oFtd_TPl?U>E(R52*Z*D*ubyrlM#458sGQx^?OXcwsG
zPHr!I?TYWqT`kPz^i{1DmN33ux0xfkZ+?rgX9>ch>z9{frRbVvqhspXXTJ$gY>&Mn
z-*fNZdQ$k7b_?6=N?4^{#hA~_)@V>MebFfW*T7e=PuSU@ApL!lFUl^PFDRwm?M85r
zuj8Pw6ydh-_pqe)nQT@(dq*}a*I&gl^tDpilkx?-eK*F1eHLn$*y$=}k2>v+=c{jr
zT`lrgmn_?+P5r+<Kt4Ym*1wRw>ZYTR?}7Y!K<)&3rTX}b?{d5DP-&B(eBmoi-V*g%
z$99VIt<N7m#}SV&l~{F<qTVP23Wvv~Ozh9CRJBs=vORmYZ`VcbRo~4z;oTgG>UE0k
z6Q_?s{DtJrZ*Q&{l*rezet6|jyYRE{NIPh(CxN}_ne528C`ST&;WI~&FRW#Fxg>V;
zCXV!W!m^IU_R><JN$gTj+#$Zfy~8I2+Z7kNlH2WXd2;zG4+`&>#7=X@^4O_<bBEZY
zvj?xT%b)cm^ZhU_d|5WTo#hU<r>721;PdVZzn(Ez_IuA>v7Niwx0Ac8_?r9}em%lo
zSs*CBulKWXPteSsLFw$*)#WpN>M!BvUEX5(^5@A{I4UYf`h5BF7RZ|~y_|66k1CQc
zzdG&@lm9--pJ`ZMMTCVLsZ}O_--u-+f=5{s&9V{k%Z5wn%1F;V#TohUulbE+zSSZk
zxNLZM^1qdlPp2P$4=-FohBo}GY?LZHPM1ypx3VSvzC5+QXkEmxbH5LN>XNfh!?2tG
z5uPGj9vOi3_rE-UPsllHUjKZ1f+`&OkHT`B!r%TJMihm2OW_3h{!uueedLeu422@3
zhP(hny$Z`HZpe5IovtrhMo~j<*wSekrX=aYdLh&8XMco8nn&$4AHs9#t#4zO{1BeP
zTU16p{{640E-vF7`70Wj&^lyw|6abhE}vd)kNztjn9w?m68|V)LYI#Ulqx3${{H7M
zO8uikslU&b<}Ce>bXohzhw#z~rvD>*rtj^C@JP#E@gY3DIoY<Yh;-(xt=S^FS_$Nu
z_22#+#vI>DE26#SRqwV0MowcZ`%}Gh5*WFRJ){*0jNFD?RMUUibvlo6g0xeo^BO<=
z+x$r5I_U~}ew1-X(yG1GJ366}-;j`>`jfFi@)uwJdr1NHmQH9CG@KH`4g9J3DgKep
z_K$Rlf21XB|JR?YFL!GE^{3ME%r*J*uU~IK?|&2+C26(A5~h+3DrHEF^shg)fYtv<
zZ~I63yMLtR`u1Ocs{UO`n`+_e%^>%O+HYME=@K@OZ^wc$RlBtBWz=k>&b{*4+1(LU
z)8}j5Dz<QJo5HbCQALX8%O4w6Fn^Jvt@F1o)H+|Q{Dlh_@lA0@Bnr+EI0rHQIuX*R
zoCe1!|2h@0mqtWHwhtV%{r!l`2xRIH+`m$PKZMkomFrZk9aFz+yLO%8>a_2ov-GLt
zUp4;zonb$Xi0JDLEcw4YMwFJ2`!@{FCV#VgHXDZO_?~2{g+zIG$`exzkBrDFr<AdD
zRg_x{Lwyi<<lWU)DHp}MC}ptJNTts(WLSz^2$T%fX{^<TF-y7DFy<*`r1c`@8pDvw
zB8IifFxDw$sElljVM#*mGtYJwxWiC`D-6$0|9sCb!;ndxj#hqa7|lqx5!LdGsyCZw
zH(M^H)#r`1!7yZ<hG&mq$hK)ODEAu1E0m|C=(KJLd1bl<q;N(xUtV!RQEhlprEIu#
zB*T&q<Zxwvf6FP8syDluNU4+$VYL8DhJ$BSMj3|G(etH<whUHAy}>fG3F%l=O|F*P
z3kTp(R4t|EduK4Q0%f=884}#rdgPU=f-*Kin*}8_uG96fC3Zmxr0e-|VOskDQ(69W
zcE4UjhRN#!axGdb7p}E3wo2O%N1zNl()kN<9m?QMoqrfJ%e6SQ;c^j6+Z<&~kxq}$
zO8d_uV>y0}d+|O>P*_)#`*E~&uq%FrGf@V~>vEfLHy%fMwvJ(WWee|;A$QE^3V&j#
z#Fy18NRC-h23_m?(kPb@bh<Ih&_A8-iGy(h&cT(USFK<_8FHhwt|)gUYvtOxRxW2~
z<pIdrPAGTB>U4h`g*MK|rMMb5p*&v1s~2#Jj0^Y>-=GYK(B<U9hE_)JYGrVwwg^_o
zMi_^3PmeAqm;JTlaiv@c(;2(SIEr#7sm}iiU*HFn0SkJ5E|ftMIxU0pwK9B8E0@8v
z-B6zFqtoMXmJ9^c8Ou?I<Lk5x8`jE@2(4Vu(%#3{DECV0e7V6%E29IoauHrz8Y^OT
zl<@<4zPBM0a$B6vXoKpjSG_lepxnHm(=wn`y9&4B0X&V@@e%%ta=BF3mq++0y@ovH
zR%hhI`q&ZW$!dCjUmS?TP{zpU`IB)qs<E5u1sudPC>JPo{$s7||F>kwy$O1T3|P^o
z#avhnYoc7u)aBY?FC2msaW1YxxocO~JD^nk{|p&-Q3hG*0$IZR7Qo6_A4lU1T#6fU
z7aqln_!GVnb^i~MuO-z~Nih>fVM(lp4KWVC!l5`CC*pLRgNtxQIQ@S;8GG<FUc-m@
z1}*vCRT~@+Q)3P+jODQoHpdRwH-i2@oQx^B1^40!<to`#q^~Pi%Mmi^56U(2Up)Cw
zHY`H9)-V#0PN!UF7@0{&Dc8%@LoXR+l^YDB66tn03>V-Iyn?@ACOH&RD=vgJun&&M
zb+{e9`_x2E!#Iz(nej-O%`ko=9g@Jmf&|LUhLN6hB<T{QYmjbCx;^PWq(_pT=1+T#
zrDUw5z-~OC%wQO&NS{-tHH;gi?<(b#^EGKRp`@h+;wvRT4e30j3zM#l(aI#U|6}!p
zVRT@|mnh#ohLziYkZC26uVIyz1*ccahGbXD21Y5RMf9<rv{)IHmKK%ws;t0JKf<c(
zNmX4>s_1%BRQkVE%&R6Or4JgVq8w-FV?g<cH>?6IAiumKl@_xorEnx^y<*8Pqtb;8
zqpGs7Vbo)O41R&#vA^iGipW1ILzXf^Sxg_78&+|NE2#8mhB03$r$oz?vLboo8dgce
zkVAaKlJnx-<R4O&HjI<XGKTsoYr`rlyG$wd9^!LlIm7rxt=cLt2~+;7U>I^Qt6^1?
zvs+~)IVx6GmL^wLF$}qL%dq6-6;M_)jAF{_a*U^}VHh=)H4USoQdZbpS<5imDQg>s
z+%9BTbqr&GvaVssm_?b0HVhd7t1HY<O1mvo);Ek*$_9oZqwWmrbHmuKY-kw!l(GUD
zzi3#EWWWKhOg_1FzPu;3$uJFO!W<Z>n_d<qyG>V+*4CCqdGR_eFG?HOr;SO+U>tVD
zz&`FvdLRzNG3cGd#0;E^i*Y6DeJ&fS_qix%TY7``qTctCe}eQ`yo7=Gz#Y<${CbTS
zWW2%mXwt+%D0e666(+(Im<|IcCNg+im&=Dmuq5jDifpL-F1D1D_OH#11}H<0^#Wp1
zzj>rWXVN{fKgzwdy8H+nhf~nTz!}j}(yNu~`+p-DGFnV8Xcz9sBX|nW;}yJ#_wWh6
z#JBhX9h@PBi2D0K9vO18t=@pZIa&tN*)R_lz+zY$D`It&M_%gXHAH!ohfcS~_A(Gm
zXUI5GZEutjVmdtpWz3UKPrzw78w2Np%So@r%_w(8==yR`vsMPBYLCeeG3traWL(5+
zcpD$!GklHj@FTh${^f<DjJ?v!m$9W<8A_$iggLxS$epZuh79S`%D_3TJW4_<_W@~Z
zVm)k(F&Kv(u{+8jcU^xV4nyx4CMKcW+^h@EMfv>(onDDDa9F3epxlb4(}A<)L!?jO
zS-gZd@Qz=vA;aMH0$!lpOQF;6QSKhmY57@Ct=uE5mBC@!6qpXPpp4nn^YdX5EQ#f{
zvj3}+A<ur)6&heuj71rssONXao+$Sm>3kW}tQ~>la0=QuA9Z{{_5ammY(yDhtQWKk
z_u~;fg)+!jm%D;D@g6?GKwRN1X}N_`*K^3XmjC!)Ce*iCJd}ZbIxS-iwHYuQ$}gel
z`~p}E0|AMOq~&QJx}4l_rfrDws63r+Edz1&gxqeV?TWooZok+0LvR!ZA{o<2&&Gwg
z9A!MduD=<5xEl}34}s_c$H+L17cmeCxlQ^3KEv1e4nLxcz(pt~z+{*PGs(b9y#YB;
zo?fEUh43>hi<Pk^%3W-_yxi8LjX@d8uhVkZtX7^~u9cz2+JWdD#)RDbqi0M)d7i9J
z&qaB(mrk$5^|%FP*u0*<7Z2eHlv{@M{7ZPluh+Ok#v^=zf!L4SB%~{vL4Jc!U3gP(
zS{a9{O@Zl9?jG0qxiB9FVnro&TK0c=W>m%6*Z`YiEVjeW*c1C>AjmX=^f;V?HqKY7
z{=bxr)wmJm?jijO0>P>Mq>tb!JdaoKCf-B2?MW|3#^`F_q6%i|{_l`84b_zL;54m_
z=+-8|RG0y?p*%T5my;(bXp3QK3`E1Kla^;{>T(USc`*IIH5u(u?&;M9<rx*)0XPIl
z;RKw9vvDB?qH1eNZ$^2ffL`uyxe;1V$bAo5xko~K8ZV;Uo~ZM0;{$w#fpFYA(jQR<
zU+Q|Hm;mKAbe*5Z%S0y3fst4UKf|(E8Ec~44x$&RE~%+q8G~`C?iW@0ax<j1FM8!B
zY@IO-$KWJXm)KOrK-_OJ>6N%1x8M$xM_cH6hfwa+(CM>y$*<SALB<^n1Pou0euM8(
zU7u4M6ohhPlTIhX6qpXPU@pvua@T{@ll@<kjPh6&Yhwd!im})ZJ7Z7mk6x5VGU*K*
zhw@x4owk*#|Ia65Dav<<F7O|pOj7SZIhWM^|DPw5ZCOxf?1ckxD2~C&XyXE0juQCN
zFDP*CC>PpvdcQvZmlilm#%cTk11F7lNk73?_zn%uYy#(sa;uhJf!tc6O^umQ#}Q<`
z`Skg}OsIQu)SId_2Ci=DfP&=LCqHm**ot&}?1p`D5C+Z(<%Vdz{AoA`7Y9xrb)Z33
z6gU^$MuFWZPqEMoIDzLda1MBj^aFg3Z}1Ncocqarrh0i^c_6r+NRH`H?!nUefpfls
zq(8&J<+`e*<ymUFeBfL!a2YR-{7%>t<!Mi<yw?bv<H<cGdI6JAej!As|EIm-zgJKC
ze<t2UIq|<&@&AtbB&2={Opn=6hxud|2fC*O)cpOwJO!$u1g7*Wm$;HP2LID;`QLdV
zy8j1SAO|bb5lz|BBBUk6r#GY`N~G<7v}+=%7ia+qcKMJ0%QB-f{%=LQ{u%6=C+pX*
zWGO3NgPU<X?#07+3NPR_{0V=?xA-UiU%N!suQwnW{+EG5=KrnfbiMy+%LO(>9z^5c
zfCT^HhDdx_Z$L?`fYmV?1K%wzNw>o;e!WI-GQPrLI2NbiEL?~yFc6shhV(8xfXDC*
zUcw)>(*F0zc#5y_cMJp~gZT)Jhe<IF%ClW`iv$9Ya@Uzo7sE1G8EYxk_kSSpC=W8w
z6<T8l)KP0G*N=4IJ7Xm22{;|+;u6$>MybDvv=8Oc0siCvLu8!9K!7nYb|dg+`LEt9
z|8MgHZ|eVta{m7Rso(t_*|j|a{l7mMgK-p2#2Gjb|G$1-xLHnkp#LW(BNb-E|MVj{
zaDCvP<AJ_ld0nv&dIvHw9LM2QoQ;ccC2qj2_$?m9<9HS?<4wHp*K0f@;}?97`kIiu
zYeRTb#>Zrs7PFu{U`6+y0$3c&qTCRw=Lf?5a#yXSrTv>TqYZY%9vF!84<<bdC*lm8
zhk^M18q%9lUptZ)w3oELcBJ}$Ag+Ib8Q1V9e1tz^AfEpxX%|OIVVDS0VjzsqkSimS
z{KBIC{x3;}JhVVJQ6PRFO}a6*#CF&P17Umlp)Fm17>-4GTDs1chl^+f;rbPU`2Tul
z$d8Nb0=w`49>X(u34g?U_!I--`QJ&K4*zn4F&-wB2SMl+2IBI8L1VcnAkX~J^NV2_
z420w5dDD7+18jz^F)-LH5QgtZejw~WGB7cL8S*H2y}&^DU4AxJr&r@9^x+;1gxyb)
zK95)NHa^5awB7qF86Qv{*r!(*iU~0gW=~H#8_E+XbooM90{!82!;t&T_58Zn2xI(u
zjkaV2!s_y~3c7+k-%C3b$KYfPgwq$0UXJqn1iIc9+=+oG`ccxSwX*+zAmauGhT{do
z=dZ|rhw5Ul4nUwhTvn$8QFFPKU#Bx+PRxfzQAf*F|Cb+K&=qQ8eQb)YFc2m0M!GM`
z10!_(5jY+L(ec1|zs2Os)6I1GjiT=V+sFun#lItc0_9h9b%iT<3j@*c=cM1DJh)t!
zcgWYAYAFu}qTtC%rwfe#%SuKbEQo>VcRA8ku?{xG78r<n2L>qiB>zhsf}?SgoBltO
zjKGM+Wu({Q*BFR$?;|ZE81*as9xvi`3<S630sOk$OZ*K#2IBwnbOl`?5Y<jhIu**p
z&Gr1ih)4M)BApIIvrCb#h&522`k>1-!9WoE3)0@MOvtaO>4F1sI0mBEQ%TRpMYs~>
zSvI<UAZYz9>4SJ2&*EjjULz2#zR!$j_zS*Ai;!v{NFASaG7JpK%tBfoJEJ!!5S%Vf
zx-3@F%KooS#^)$eX<e}mcEldo9|vO~7%dOJ*7auKJY0%vFc5^6Cx-ct{{v$^4^u#%
z-=r5L&ur5Mg3mvZeuO{cTl^CPLFcd#fBi%l7#o^_v>GF-`+p$VT$mXpu>uALjYg9W
z1esfsZinjr4b|U!qdXi-rvtHN`OP$)o`SRFK|nfVAsO;`S)C39mF1BjI=u@6gG`T+
zK7$044f)9sUH%?E#n<>d24cv;@*p~0A)d!?QcQ#Lo4a~`Ab6agbTKT0l~JBOrppIn
z#?45##ts-5)Y>l)Bn~J~Z`KQ#fbwi+ot7t+Xw?&1R1*hAxo#ruLwQ=fo_`2W;(3%u
z%INvG(JMdEr!!vQulNB2qhdql<WH?QA*R6em<{t{AuNIAu^QI(>oppY5rb{9GX{p$
z%A>>d1`Ne9I2mnRfbs+zU0xn*tCb(2)yfZBYvrN$qU?Y9K>?j1KW(9vXJ=~V=MuDm
zVYyF8zruH@?iN%n6NC|%1XE)s%!&Dw>ifSa8Ktoj*2KVg-=?HnVSDU`eQ^+u!0|W@
z=ip*d_y1L71O^UoBfT5H!xMN8ui!0wfX`74Fjg(|2Rg$2X%8j{jQ>qeMmo%jd9WaU
zhUKs-*1^EQ<QAj@1C%?F?ulRG5Ow~owlFYac@i^b;(T0&Yw>H`f&1_XevcRNI^My@
z_|nV7Z}<`25&jJe$HbTlGh$%Ga}?<!SPCm*4XlSv&>PFd7uXg1;6MzFkRC^RD$d45
zxDq$uR{RzZ;&H!T<187M@h0BKXZQ=g$G}kQka+%<ijT=KEoQ;oSOAM_W&i7;*YX~y
z!i?JZIX1^O*b#eRe;kaXa3apYdAJnUC{_R8OvZNHi-++PUchVk6F$P9@h$#|uK4~I
z3d2O0Qq=uF0~y&-4&QaJkPkTRe;OP94}#SG@BcuMIEEF*VMpwaeK8QU8b*2yPQpOA
zZZ7G?xDwanmO%V(2N`?u5T3w56e|!szCr#Se1t#aTl_2TPpBpg6Jg3gELYA4bW=<B
z*M6#aptmb43<LxNO*@?YaX1zKe~t&r@jnZ`kI(Sa!~>=O|9e326UPHp|Npmuprk)#
zJkWpqPnb*v1l70UCyWPj{LhLdAgDLs)5Qa2|EpL0uYjOG{mJ5if%sp*k%ZwsRXou9
z&w$`3jt9!|KVdZjf}c1ZDEt541A?D89;lE136}+i&wk2yp#S)v4Nw6=)f+xxJka0&
z{}vF`8}RAkf%N}>1qA&q@X6wVf%xBF0YL(TpDG^c{bxY%6UPJP_@DS50l`lk50w4?
z?*YM291qmT|HSQdKv25hr;G>skN*ja1#TMugz-Rs|NmP+Q1|~&7Z0TW|0^KK@c_}U
z|MhraAnx~9K#&y&^8dHvf!==x1V3>+&};l7Aoz*nfwKSqJs|jr<AJLG|64#%(w{OO
zsQdrl1A^-N{}aXo{r&%M0YTmWKV3YK{{OFlpuhirvUp%1{`Xfvkoe!HiU)fC84&!$
z@j$QfkAUDOjt9#A|M!64CyocI{{L?QK}mngc%bh8e-8+%{{PQ-U?g$D!dMb3V0Dbf
z#@G_uVHfO;U&ZJ8-!L-9;uM^P3vmUm$8T^K9>8OG1~1`{cn_b(r~khu<99SA<f&RB
z7~^45OoN#*7v{%eSOzO&Eo^|zyiByl4%i+0VW6CTe1>e;1oEfjTwH>yaTEG*4<17A
zNhZ$YRlJQ4@df^hAJCc5-%_EN5K~}!%!YZfkYBG+f{gN54eMefjKQ|p8GGRX9ExLb
zGTOKRmuqGJuOnj%?!^6g6i?$1cmwa^6MTj5&`9KOp&*RFBudr)Q<ISib7DR$ilwm<
z*2MbQ6kB0??1p`D5RMRa{~u4rG@OHraTRXFZMYl1!xMN8ui!0wfY0$wBKrRyWH==3
zt-75D6JT;ohgmTX7R1l699G3T*brM_Tw?lvCo+2CmpBAR<0PDk^Kluj#jkM(?!zPa
zJzn%OaUJjAV|<Cf;YV~Q@wZesCdO2l5p!S^7Qs^Jt;j?TtcOi77Qeu**arvVa2$tI
zaW*c(mAJvL*VszNw|Eeb<5|3nH}O6`!(Z?{T1ova6oT<F8K%|B{?9^2ZY+Ssu`E`>
z+W0v($2QmzdtiSYjH7U(QuY5CWX!{*xCS@lcHE1H@f2RbYxomB!k_Ui{weDI?~?KN
zs@sKOB20-HFgr$KVJwLiusTL#V{D1-uuC%fe{V9r!eKZTr{FAHh%0bCeuKO403O3L
zcnN<@M*qJ@##4NazoVJl-$KC{50hdV%#67(KNiC>SQ%@1nP`B`ur+qT?${3l^+uAO
zfYWg<F2U8f34Q3@!^9yxiRbYu-o}Uc0)NF1=uF{nsZdOaDKI@|^XoP8l2HgtV0o;D
zb+Hk~U|Z~ry>I{y#W6S;ZLRG81!OG8b+`q0;(k1er|}28fp_r<zQT8?p7pAFTaZ%q
z{|GXYU~0^SIWZp=#nM;_YhrzDimk9ccEi4+?*D_x7=hz)8qUGRxC%GoHr$Qh;R!s4
zSMU}-NJ;;HPR1Mj108ZZj6NQ~1ehGtVOGq81@SX1hgGo-HcUnTZ$U;JcEX<cB@V&S
zI0<Lsd|ZZW@oU_H`|yaDiSO|uUdKE57+>OV_z~Ty{Vf%ai7^#s#2grf-Xctt!irb}
z>tPd&#V@cc_Q8QT9LM2QoQ;e8dX1H2Y{0GfEgr<<cor|?O}vlK@E3fKRvLc`g<yQG
z?EhqBq{S?l8w+4@EQ?jJHhzxHu?=>_9@rlTD^>p=MaD#&f%9-FuEEW?9rxm4JcSqV
z8vcZj@Mlr?|F>lPiLSK%rV7JEm=ZH!c8tWrSQ0B>b&STw*fK5sza1G}us42%!*DE4
z!CANvSKxa526y2BJceh|(*G}!@gv^Dr}!FwM>Czjg@Q32CdD+E8FOKNEQV#gOjO2N
z*Z`YhYwUpCu^$GOGm`WKoQ`vG39d%(CMJBi2M^&%JdaoLHa^4`_$z)uXL^52g<?WX
z;n!=VCnFo?#X?vD%VRaHi;XY_+hS+zg#&OXj?sGMq48wcxB!>qI^2RgaX%i#)A$44
zz`OVaU*S8Y>i<Rte-i~^1SY}Mm<e-YJ}io*u@ctA`q&g(VS7>c|88XT#X&d%$Ky1d
zgNtz$Zp3Z48^6O7cn+^*p#R?@;{iU$H~0rSGWuJ}g9$J>ro*h52Mgk7SPrXZl>M&`
zFzS%e5L;jzcEX<cB@V&SI0<Lsd|ZZW@oU`SWnv#5!SC@RUdKE57+>OV_z~Ti{4XpV
z6JsjOh~6AbL}3vug%z;|*25+ki(g<@?1KYwIF7@qe!a$QG8W-V+<;s0TRe!z@ho1(
zn|L3e;V<|e)gycL`2P?+A<y~6WSADSU~Vjc#jz|_!P@vaHpe#D5ql_A|L;%6U>t=L
zaR$!ArMLz+<96JOhw&6%z-#!EsQdpTGJeLl_$Ruu_}@%nm<Us12F#9;SQtxU1+0$I
zS?K?b$!Lk~unYFauW%TS#VI%o7vc(BkKf=fJdlO{e~gSXcnN>Rd-xPz<L_u@^|w$k
z#>1qT1~X$W%<pBQ7?#1xSPL6qGi;3=usim{z;Z{Do`BPFZlK%}CRXDn^x+;ngeUPl
zUd7w^5MSW0_yL{S{4Evg*J~ssBL$|%Y?v1dVF@gc)vzu$!We9eov{}V(8~TFO2!zR
zj5aR7<+u*F;7;6+NAWcNfH&|iK2fUv|B8%vXk_;{Q4mI85=@PmFem22qF5R$VNI-$
zO-0@RTanQoyJ24(gd=b~PQy947+2v&+=jdHJ3Nt{{(p{)D|ibZ;B$O~f1o3Wzok5w
z0Fz@n%!+xiAbysE{$Gxas#pgbVhfDJPS_K_#348uC*e$-kIQhamx-@&2kyfo_&r|4
z>v#tr<4gPvKcYLQzoo)4F?v%mkr8uX6c)i!SP^SrJ#2!p_yu;wJ~$AE`}G>*$e4<=
zaS^V>4Y(D*#e;Yp&*EjgiTCjt{-Txr|DFshm%oWZFg_;3w3r2RV*xCVWw8p@#?P@i
zwo$77-;s<S*dGVuD4d8ha2_tjHMkkK<6b<Br|^QP`~NjEe!@riGrq+?(UsfZQel_~
zQ(^|pj*(axOJarG^#AH)L}O!YiS4ip_QtPp7>>m$I13lz3S5uh<fi}cBI5ua!!vjZ
zf5dzE6kp@-Xy);^P%y^Bq?iUXdzr|E`LP(5!OB<*8(=eRjUBK%_QSw>Mv|To$e+%{
zTwH>yaTEG*4<5pkcpk6fZG4C?@K^lc*K0WQ`kN{g6JiQXkJ&IU7Qzx(9;;zpY=kk`
z7CUQY|Mwze01m}5I2mnRfXi_mZo!?nACKZ``~hz$RsX+B#uI#n?@;~FhrVEd5tsy1
zV<yar`LHOK#!6UI)cwCc8BMVjw#RPR7YE@89FNm*4lc%3xDmJE?nwIocVwKvb9e=B
z;RAe*Z}1OvMEP6Fg9$J>ro*h5CyM@Gkc`i;99G3T*brM_9CpH<_$3a((Krcb;(RX?
z%Wy4zjXQ839>MSNB3{Qk_!wW}Z}<`2`TQ;A4QC=TroxPv1Ea7Amcoiy1M6WEjKwdo
zEB5j0H3pI~9LM2QoQ;ccC2qj2_$?m9<9HS?<4wG;mHq#Wj9>6QsxGJg3&Hr94AWv3
z%#8)GIF`jKSQ|fAs{Y@cj5gR2dtiSYjH7TO&cJ!N6xZNp+>U$ku&De0DKakLHT(%5
z;m`OM|3p^-e@lg7B20-HFgr$K;R5vkl4MlC>KKiUu_d;{F4!Bt!eKZTr{FAHh${-v
z|JRf84er7Ncnr_rCHxWZ;ZuB#zoS{u-$KC{50iSCNQ0R%7v{%eSOzO&Eo^|zur+qT
z?${3l>-CN#V**acxwr&Z<0kas9z296@jPC|+xQS)`1KmUlJNnZh5StwiU~0VrpIiU
z7YkttERWT&E;hm#t?d7{WOT+}H~@#@7@UkYF2Lou4!7V=+>b}`v{Lo|AIP|Yckv0n
z!gnY?rR_f+zz9r&sWB7g#C%v3ON+YyS0bY(*2kvU3fp5h?2ChN1dhjPI0qNwD%@C@
z{=bck-S{1zz;k#7Z{Y)cj&JY}bQJNolm`=Fa!gl*{-2eMJXjDv!*W;^>tI7{fpORg
zd*YWk1V`f}FB3CyJ}$$x_%-gpeRu@F$BTF!@8Dy6iNB%uBNOhT{-z4Y#Fz>*Vh)VL
zB3KG5VhyZ^O)wU}@ar|YlF<hT;&2>?Q*kyf!j-rIx8k>W5Rc<oysVY|f0K;+_zZu+
z_o#juPah9pd`yOEF$?C#0$3c&Vil$8|Fy~Z9Ghbs?1(+EKMuxGI1y*yJY0%va5HWf
zb^qT>#$h~#7w{VXgpcrNe2aggtGK_V!Y~o0#0;3dIQ>78jKWwFD`0hu#>UtZ+hG^%
zjbGs~9E($MR&o0OLNZq1di(}=;Q>5`XYdmKi1+X*zQ*6t{LJ4%!CoffVNy(knK2jU
z$6{CpD`PEefX%QqcEIlF?H8E9kvIXT<6K;Vt8o+ha1S2BlXxDl;%&cP;~^O@@K^kR
z&JzBn3dMw&0@GtQ%!`Gv1eV8YSXV3izY!TR*cLluFC2hFaSTpI8yDbmT!&k5C+=6O
z{(qE=)A$44z`OVaU*S76O8Q$U2qQ2Frp8Q|6Z46>{}&~rG*-fzSRb2WD{PP5urCh6
z5jY;F;T&9ClK#JnjE%SrcjI?>0?*+UyoC?&IljR^&{4|YQXWiDivFLRjC7b4^I$>z
z49j6vtb+})1;$|~?1^9E5HAy>aT3nN`M3<%;@7wX_u&!z9xvi`yn~O?`;v*@@FTiQ
z`<p5p6JsjOh&eC{i(o0Nh&8YtHu38<V#)XdyJ8<4h{JIlPQ}@{2v_0;+=}1gK|HSY
z8pc^NF5^wSkI(QIe2-Qce+z|Rd`yOEF$?C#0$5zB`hQt6s$gyW9Ghbs?1(+EKMuxG
zI1y*yJY0%vMBV>4ld&E5;$b|67w{VXgpcrNe2aggtE|7J!Y~o0EKC2-Kt^_q#KKq-
zD`0hu#>UtZ+hG^%jbGs~99!1w-?AxW%)*7Z0@vd=xC;;9F+78p@JGCdPw_SW?q$L(
z=iiWEjE6}v4Q9q%m>-K_8LW)8umLv1*68iPM0e~Ln1Lg40#3)dxCB?@CiLMRJcK9l
zykD<zm5kf?5MSW0_yL{e{Vf%W2{8qx$84Av3t<T?ua*5@jf}e32xG7<cE(;f0Eglj
zoQyUuz~#6Ow<uNr-$}-PJc_6B2fTrI@d>`dcW6}bw@?s9U=mD?nMB?HbCQt{i(+Z4
zgf+1~HpN!h9=l;*9E2lqJWi`X|DQv~VqAqAaU1T&@9+ek!z*|TAK-I*gMXl-BK_Y}
z(cfeVFgd2fte6K2;%8V6t708&h%GP<J7G^R6JO#G9F3E3CeFuYxE8<09k>sV;P-eD
zucP-46OZvF{)QjXUCG}<;g}dxVMfe>QCI{^VMVOr*K5=xqY1|17uXg1;6NOX<8Ug@
z#znXiH{e$MRxA7eAQ{K;EMCT&cpsnPFZdqS57q1V0LI5;m=?2OZl&t~1;{9lWw8p@
z#?P@iw!x0r1N-A(9EB5c2F??8|6fYR8r+QAaW5XmQ+NTd;ZOJof5x}?C%UTmTPmyy
z{XY>IDKP_P$4D%UC9wil$7pPfEwLST!QS{)75e`$GREQ*oP`T<1+K?$a2FoHV|WHH
z;g5I^pL&^ijlZK=)!#(H7!Q+T8qAEjFh3T<GFTaFVFUCwW1=;7!0y-&y*Lsl;B=ge
zOK>%ALLctILw>!+NixpkRlJQ4@df^hAJAFN-%_EN5K~}!%!YZfkXH782{OuKHLQz`
zFb3OVXY7Roa43$!$!OyOT&`68e;pZHa3}7^qj(yBz#DiMpWrKehemaO3k6{WCJ}Z2
zPfbQ9%!&E1D3-=bSQG1GQ*4Fpu^aZqK{%p1{eL_e({K(h##Oixx8ZL54o~1Yyn?sz
z0Y1k!)#?9#km0D|Zz>Naz~q<?vtk}Bh@W9OtcrE8A-2FcFB6@xCw_@Ta5PTBnK&Pp
z;adC}ci=ueg5RU}A`{o~4nD@0_#1vicTImwg=1n&g&8piMqv>w<=1OeB%=n_!zLJu
zUtm}4g9C9mj>D-q8yDe9+@O{Hzm<${@gN?@vv?VA;(dIEzu<ecYWZ6z1mj~eOsiD=
zKMNVTu>cmwvRDOc<LB5M+h9lRf&FnXj>3te?*B8$n1@So4Q|HmxEBxODZGH!@F#qP
zKjT~cvlji|RomZGVVDS0Vg}5Pkysc@Vg;;@(byPUVms_ooBrRMjIVGQj>RcB3m4)F
zT#w)2E<Aw8@C;tUAH7W6!>9Nfe@C;9zlDM^9wx;!m>F|nek_J%urhjUG0^~<VQcJw
z-LW5faU@Q_={Ogc;A-52KEGaL4;hE>B%a5scpD$$3;Y#7ptG*Or9v?wroi-=O)L99
zFByff1eV8YSQi^%47SD2*b4{XP#lAk(N?PdzkrP8xDL1APTY@2@ihK`H}Eb#!B_YW
zjc9)h1&O-<N05;OQ)4E~iTSW7mc~k06YFDBY=!Ny8}^N+{|_Q#1dhjPI0qNwD%^<M
za5sL3C-59z!CUwsn*RTsj5qiPI_mkG%7Y0oIi|y`m<J2uXIKuaVjXPgWugVfVJGZ~
zU*ZrPjgxRD&c|iA7Qe<FxDUNYnD`zq;&r@(kMSk`h9A*g-``T<m>5%GM$Caxe!WH!
zGD=}Ztbz5g3C7|V*cJQWKpc+aa4OEmMOxYaE6Lb^Tk%^wh{y3PUdI1J!(E11S*}q4
z9=bugyFo!wQ4|#w#l)mT8tIT0*mNmKgLF%Gr*wyONJ@8ioZ0)k&#(KrmY2w^cNSyd
zoaA|4<6S;s%rZek3HVaj@cz>ZvM@Ja=IeZiAM!JP!?LWxT5Q1PY|Bp3M)u!R(2qkn
ziW51V^SG32xQRQtpT~HHmw2;`{XY;qXPmM@Rf(CB8JL~<SeQlm9!v5|e$NW5R@VOO
z3L3K|+p{bCZ~%vMET?c57jgyHaVz(P9EW&<=XjNO_?R)u1r5b#GNxf>=3+q>VKIhE
zI7+cJ%dj$QvOb%!4MXg~z8uVvoWN;;p{TinC0xyo+`)Z3%G12a8@$hFj9orxDiKpK
zeZ=VZ&nC#rLVT0O`7yuXcP!7JSci?+g1@p0dxs70zrSD@$8a)dasiifEw^wt5ArzA
z@(OSBQM8f$M^y+aipQi(%}mV60(^~c^8<d$ulXY@u?Fi^u>Yol*6hgc{GEe1g5x=r
zbGVqRxPjZbmq#kt|0%%*UgteNWvq%pQwf=z>6n#y_zK_PyZnfshaBIs9ILW68}b*n
zV`ui_9~{cjoWvQN&(Jc*-`vbyJiveXA20J3AMyp`RtlO*!c@%29D$*z{DN2c7T@P5
z{E9!YBCGRfHeoAvU^o88ff1wM|4+d<{>9l`#FbpnZTyFad6MUOjd%HkF)Q1Dg76Xj
z>%dD)%Ph>zm-#y1;fMT;->@vJuofGzd9;!Jw-t0^Pxj*wj^ad4=R7Xu8gAlF?&mR{
zsciq31ULDB&l#sm&`@HgWCmtuJ{D$CzQ>aMlHXUc{|bU?tjor1$@c8ZJ{-W|9Lp)3
z#f4nKbs@)A?%^Sx;5lC99X@7^szF2XnT%<enYmbyp(2iAEWuJN%`&Xanyk-eY{L+H
zurCL5WMC+2f?yiwatT*+BX@8gkMcAx@&@no8DswxG?ge~^!uj}q-QqfWg))F;{2Fj
z@H>|0Pprd6Y{6f{hQI!I5%gw%4&xY3=1eZ&a<1hT?&d)r=UHBfHnRWQf=7(17E~0E
zNtv3Nn3Dzg8sFvz{FGnwM^>t4|1|{l*p#i=k=^+_2XO?)b1LU>F;{T|w^s`VAL(Af
z5uV}&UgteNWvuGKpP!J)nT}bRhp+Grz8i9U#LxLH%dskJvmt+BJ9cI-{=uOf%}ET+
zaLng2{>{zY#RL48|M4<!@gZL@ZjGR+Buo_;ipnU+!TfxcZ}EM8!ms!PE3!I&W)rqz
z2X>1X{r<lR2J%mi<6oT3MO?}C+{S-+m?wFj*LXK<c>hlXF>3}DCE!a;%Ph>zm-#y1
z;fMT;->@vJuvWB@{WlOaXIpk+Pxj*wj^ad4=R7Xu8gAlF?yqV8#{_41i8uLx&l#sy
z&{SfkWCmtuJ{D$CzQ>Za?Eg!__pHEbtjor1$@c8ZJ{-W|9Lp)3#f2fq3a;Z;?%^Sx
z;5lC99X@7^+Cf9{nT%<enW0>cf-J&fEWuJN%`&Xanyk-eY{L+Huy0@}YOr7=CvY0)
zatT*+BX@8gkMcAx@&@noS;Xk~k6kCIDiKpKJ+m<{3-L`B=g0hl-?2P@VjVUL8{U5l
z!LRJX-t5m|9K*?+$pu`_wcNtpJjmnGM)rSJaD}(|h*5QehT<_PQ!^8DvH)M>+x&o^
z^6R?x|D&K1Yp@=hvNb!hJAdaOj^KDs<s2^Ns=D^SL9m^Bd4#8Uf!BGDPZ{gyps9pR
z&UDPmJbWeOc!TfqBYw_rS&mg%n+^F3+p#ly@edAVXtZMzXK+53@o#SCE*{{&{EwG;
zix2sNaqC5z3PmLej;K`3$Q;biSNRs-=O_G%Kd>UJ^Jg|;tBBF>-$Brgzi}Y{<T(Dt
z*<8exT+eO%hlhER=fj5ge@$?gPZ+a)@X3^bFEK5%FgIW3>wJeF@-u$Jve8ENUqw)h
z4cMG**@->bk3%?$6FHspxRh(SslNU16zu0Qp5Z0l<O4ouoCZNtiJ6ian4S4pm_-}d
z|9gUx{F2|Z0;{nu8?z<bvn%^>0Ecrdr-U4{xR5Kjj$65hhj@bLc$Ihfm@yg#4aH|N
zhSE4PGZzc82#c`<OR+S|urh11KAW)(LxG{F9)i9c%#obHX`IU?T+NN#!F@c+)4a$V
z5u@M#zTg>SHwvms#1u@=Y|P6-e3QlbF~8t<EYF|9hWB4b(1<PgE4#2a`*Rq_a586d
z0he<vw{Ul~k^LVO9OqeH;cY%*RO6tbcudOF%*325z}NUTKWJ?Kp9;R_kF3NRtjDHo
z&5rEO-#LgQIG$5Er?LGn7Odh1Zs%Se;VE9=b>8Ds#%dBYm5|Aqj#)#FJbZ<3@Lhhy
z&-pFOu_|k`A%9^zc4jYz{%{QCXink`&gU}z&CT4!1N@i&@iK4mVPGigg&=OzpsFNH
z#f;3s{Ct&f@qK>6ulNHivO0f`82$cD1g+SC-S`^^@=uQAU!2WFT*>v^#(#J?Y<T}C
z1?PE<clm@dn*|Le;7d%)EX>W9`8wa>hx{zs$o{_(lw}pxVgoj3TXtek_Tvza;zUm8
zJT7f!|7!%BxRd*NjAwX>H~E0i8K-&BRAQ!N24-iz=JsD$P?YbnB){bMtiWol%f@WU
z_Uy_&9Khir$5>9`EH2~<uH#nj;US*jIbP)*K4y$xf`&rz9m$x6nVE|PS%k${f~8oR
zWmuUtS)a`ULs4x6A@*Qj4(3Qs;55$V60YV(?%+Ni<>`pg?|)HngZKH2v0DUHC1MJu
zXEx?#A->7t{Fq<xyRhN?mlyoRI&8!i{FPnUoBcVAV>p>Jxq!>LHrmMkw+MFgAdmAb
zukbb>F{)+IP&_7OYGz_i7T{|w?f-4T2mF*@^G8-<4c22*wq{3m=kFZE5ggyr{-+A&
za4}bL1GjT8kMI;P@H+4DDPy$?no7vzAxAo9Wgfo5H~20;;^+L9<ye)q*^s}m9YdWR
zz4!-*ax^D#2Iq4b|K?`y;sO54|9Ckt6m?7RkS`dwbx>6jrea3sV1B;JxA;Ck;aB{D
z6(dH!e|5pnY{FLTz;67F1NkS%@h{HiBCh0mZVMaU|38AmJjwIC#=CsNm~DcF67VIa
zWftb<%Y2>hL>t-vhl0=e4a>3$Yq0^Fvn@NZC;M>-M{y#jx3T|uf~8!;P29=-JjOG;
z#G8D;=Zw=fXeu#NGDBPY&o0Qv!Ys=7Sdw4zdsbjI)@5V1WP5gHpO9k!hjT2aa26MG
z1=n#a_wW!;@Eou54nvO}G1>(c#b+|6VP@uHK^9>#mS8ECW*Jsy&A?DpeL*v}VTe80
zmxDQy6F7}?xrD2^kvq6AV)XkT6`bZp-r#*cW9(mprV=p)(=!|MvJl^7aef>&y#Fr*
z-?2P@VjVVO3;xP3?9Kih#xb1CnOqQUWdF+rYq^EHd636>mRES2j~LZHXeb_&GBq<X
zXM6iEAb5>$^8<d$ulXY@u?Fk0DO<B6yYqJrYH$A|1miiCbGVqRxPjZbmq&Pt7kHib
z_>{3i9fGP7GC9*REA#LbzQK3-5kKd*EXS&>&4vv9;%LXt?8QGgl%qL`GdQ2i_%}Cm
z7Z32?z);kGg3G+chkU`f9fPKlFcmX02lMk)zQy<X3BQUM{r*1)DzZ9%W)rqz2X^Cc
z9LPU8j(>4B7jb3S@c!2ew(%bx=1HFCHQwbD#`MXYfG;sEvoJTq-~2wZ|Nnm%-2Z<!
zy#Ie!od5sd@&Et7<o^G=<^TV?=KlX*&;S2#(f|KX)Bpdf+R0z2C;M>-M}_QvqF_4b
zaVghu6L)eykMRsI@g^VeIpcH+K9>^z|7Vy|kb&8mkA+#3@3ADm<oB$=YOKq~Y{~W^
zM_2aY01oF^PT?#r<O;6iR_@^;p5Qr#t~&1UF=KQNDvHl!OvB8~#eyutVl2T@EX^{3
zp{UA&nyk-eY{L+HurCL5Bqwkh=W+>Gb7RElPlz3YeLTw3yvQ58&u5I?C1@%UQ!qWV
zF)s`8&9LG97Z-fYFZdnH^C#9}BevkL?84sc&tV+H$<apkKU1)P%ej_YxSI!goM(B3
zxA}-sU4w?=F)34bwf{_loGifC_%=V_r~H~fvJz{s9-Fc?JF<IMzaacB7{n1A&#9cl
z#azV=+|Io`!c)A!>%13oJY}qIK~)KvoavaAdH4$7;Jf^YpYvOmV^xM~I~wvAwqs}Z
z;vXE!(VWB?oX=(ao13{SFcft_@Gt-4W!~aLzF^$$K~qVXiW!-M`S~i};`<S!-~SWA
zSNwq$S)D(#30tuPyYV*;<ewbJzc@Q=c>jw8E4iNA_zw^BB+v62@A3&__6QnEz?Ybo
zS)z^XKeymzzRq{}AwT0cEXyja#RhE7w(P{7?AOEohX_V-BByg6mvRj^aVPil7|-w$
zZ}I`3_ptvsJ%g$eGbJ-HJM*zHi}F2|<d^)O6<CdR**N5A$@c8ZJ{-W|9Lp)3#f4nK
zb==B5JjBom$2nf*9X@7^UO_|gnT%<enYmbyMOcg_SSm0SRa#Jnm06SZ*^F%%Vh{G^
zV2<PjPUBoIi5UI<s|6dmgZp@tr+JY#c%RQ0yLZr3BBo$^W@Fy4;r$m9yvgGHm|yTa
zmgi5b!$xeuU)hDd*`LFrjqHDnU@~WN0he<vw{SNP@;J}(3UBifqxu95#p`4LNd>8y
zi8)z-ukmeuz)$%#e`F=rU_CZv>pu41QP7>ga}Y;xJg0IF7jqRia69+%2v6}s$Z?(b
z_>{4J3#v-U<V?q`%)?js2H)jJ{G8u1RL)VAwb_urupK+I7ysZ;j^-rJ;CwFQ-+`g1
z&4OJ#z<>E4FY^{3@&)7m9yFDNshE*Dn4hmkjDG*O1n=_`e#IYHk=6M#o3Ir-up58l
zK>o>bVZ;0XOE8;@xRUF+jsNg4Px3sk@h+b*X5XNp1bivl$o|s`vM@Ja=IeZiAM!JP
z!?LWxT5Q1PY|Bo4?Z2m>ABS)hCvrOHaVghu6L)eykMRsI@n&E9e;|0yIQ@dE5;G+;
zFgx?HFpKg%mgJZGo)uUv<fzNWY{~ZQ%03*x;T+2;oW+G)!FAlq&>qJjp5QrN<sCj|
zj6Z^g;xif3Ff((pAd9eAU?{4DpcG593@fuH>$4f#FvK40%fTGU37i%&`u*n$mT)yU
zatHVEC{ObuZ}2{!F?Ro;sYFb{^kKvM&nC#rLVT0O`7yuXcP!7JSci?+g1@p0dq*4D
ze}BO+j^Sj^<N_||T5jQP9^`SJ<rUuMqyF|EH6W-c9+NUPGchL%@HM{85BMp+=8vqz
z8mu?K{+kL~vm?9ncMjqRj^|X);bN}h25#qG9tk;4@dB^&9-lJSz@VvwOwM%7$~=69
zZ}44y#L(xCZ&{92S(^>{3)`_Xd+`qr<!Dag49*V>MJ*Hj&CT4!1N@i&@iK4mAzv`=
zprENFOvQ}M5i$Dx^9x?(TYR6N@GJhnimc9`*@Ugwf!+8U2Zjyr|4+d<{>9l`#Fbpn
zZTyFad6MUOjd%HkF$dd!g6Jdi4G5T)S(uwI^L4(%5BV9tVOdsTEjD2D!S>%)(1|_S
zk3%?$6FHspxRh(Si95NU$9QJ2{a+H?<O4ouoFPF&iJ6ian4S4pm__*>OY%#8A97S+
zHP&Tgwq$#DWgiaUaE|2^&f-F@U}&9VEBEjaPw*VC@(v#}#?YXl_)Nw$%*<RY7#NBw
zA}GcZEXC3+!^*75`fSEF46z6Maxh0mjDG(Kf@z$~C0xyo+`)Z3%G12a8@$hFj6E!9
zDpA<*{!<9jGaK`=5Z`2Re#|fU9n144)?p*I;IGj}zW#R+^k#n!;}}lnOfKMZuH_c)
z=0P6kSzZ}t|F;E?7&SboC?1nCH8U|M3-C3*%@6n~zvhpuG~E7c2<ovZTeBm(^LGy7
z2#)7e&f#LN;s$OHIrj1hPw@h;^B$iv)}KLB37MSfn3Z|>3g2MpUB^fKoZqq>tFks5
z@)x#aXZGSB9Lmw06c~z{A(+o){F|G(iwF2G|Knxe;zPb*+z~-jNth~P^!sNN<Y0cj
z%D4DFKjByWffZSuKeGv2u>-q>4e$Rq!9f1War}$3xri&dp4<2j5A!6?^BV6)8`=L8
zLCldsMG5#4(=rQl^JTuyclaSc<2NkJDy%iq{u>CIvn@NZC;M>-M{y#ja~_v+4L5No
z_m8yyV}dih#G8D;=ZrHdXeu#NG6S<S9}BZ6-($&;<4b<e3arMuY|NHy&#vsl0UXY;
zoWfZQEp)8lI&S429^wg}<5k|_W5yUAG!&o7n1-1HLs7W|1zCi}Sc0Wknq^p-HCdm{
z*oGnYVBd(*?>|^Dk`p+MbGd}8xsf}#k4Jf$7kPvC`7CUB|FOpeRV88yre`+hWg))F
z;{2Fj@H>|0Pprd6(MI;)LhviQus8d27{_ojXL13Tb1k=UHxKgo82djfxWe0f#Hg`B
zL-ClDshNp6S%9zcZGON{`SsXP@B{xSsKgqq$EIw}j_l6gIfx@To>Mu8i@7S~*ud@F
z%OgC+3%t&Ie9Bnkf)6MmlQSK&G7m$qINsp9{D`0PTb5&0)@DQg!glP;Ui^bY14B`x
z1(P^~^SO+Fb2E4G0RQEGyv$pC$QO(|KHO9&Dk@3jh>A+ZjLgCOe3ftUeSX5P_ya4l
zI)7#pwh9~Ge+NM~{>Fj)ljHaoXLAu(ay_^4A0FmOo{u)N|7(J~e8QL$f={Lde2Hn9
zg}M1MU*|jgke~4zmYrb#RRp!zfX&&Ko!FE8IE14(k<&SkOSy)dCPcq~_}_f&6zu0Q
zp5Z0l<O4ouoQc7Ylb9))f!Udlg;_M@c#kFdCBJ6{R%2Z@W=pnbSN7om4(C{grZ{GC
zAy;r6w{i~;@dVHDD(~<yV@wJfiqB+$p{O*1%*@4tEW%<e!BQ;EGOWy+tj}g_!%)QN
z_wOO-%fTGU37p2cT*B4d$Q|6rqdd)vyb(6M|NDYxj6FH1DiKpKJ+m<{3-L`B=g0hl
z-?2P@iZ-(UI)X-Q!C%>hz1g3`IEIrslMA?<Yq^EHC)@u)!Ev7D72f6}MokGCipQi(
z%}mV60(^~c^Mfh&|Eb_>{>VzK!Fp`U*6hgc{GEe1g5x=rb3%^AT*VFC&b>UsQ@p_I
zyvL`E^;ghTLMCTAhO#>H@D;wncli-N=eI1!s;te1{Dtk<nY{u-QGW=Aax^D#2Iq4b
z|K?`y;sO54|9F|V_%LGh`@ayxof=e?gsGU3IhdcX@-4p4PxuvoU`1Bv&tb#+Zz5>L
z4(!I?IFNsG9RK2MF5*hA=QjSs!_h|ee^PLs*Last7;{?CPy)Whw9LZXe3`HF9e&8q
zrrG~Dg0if_T5Q1PY|BpU$$lKdQJl!>oX4fp?0=156L)eykMRsI@g^VeIpa(Zno7)+
z%)so-7jhJ4QNG8L{F2|Z0;{nu8?z<bvn%^>07JtaV>yMhxR5Kjj$65hhj@bLc$Ihf
zm@#HV8VW_l500p0OvB8~#eyutVl2T@EX^{k%$lsvW)Y*`zl|Wo9_-7(9LWis#<^U=
z)!fJ(+{dFl9X7oGi-H@x&u5H1Gx%gm#1u@=Y|P6-e3QlbF~8t<(MI-PUhos^un}AE
zS9W1<_UAB;;bhL_0xsv;nfAX$u$u>YoM(B3xA}-svx0`=F)33s6LYcvUz=tBZwo%)
zr~H~fvJz{s9-Fc?JF+`}=OB*Y_>f~N=WsDsaRaw=FOTpPFYr3=@hM}?4w_2HP;y5)
zW@R3}!Z-LXKjP>7mgQKLwb_uruw7s%s<WUM|KL!L<|NMGd@keP+{|4(z<>E4FGq}i
z|678Ge8ISLf~t}*6*Dpi^Yc}{#rOFMzv2(97&g5B>Vluygss?t-S`^^@=uQAU!2WF
zT*>v^7Hwqz{|FBAB+v62@A3&_&J7w$z?YboS(uwI^L4&6*Zw~ge8z8BmQ`4b4cMG*
z*@->bk3%?$6FGgZ{m&CD<r;3{PVVP1p5Z0l<O4ouoOwZ0iJ6iaLXPar$HFYi_gIo&
z@_SZbHP&Tgwq$#DWvGv10Ecrdr*IY*as}6MEBEjaPw*VC@=jnV>aifk{Gg)vOvW_K
z%v>zUA}q!dEXC3+!^*4~G5Y=M3!1SFL+ru69L$lNz-gSzC0xyo+`)Ze!}~ufIL(W^
z!TWs1*b9QD5-|nSGaK`=5Z`2RejIIN|6d5cV|o6>I&8!i{FPnUoBcVAV>p>JxnP0)
zFBh!k7VhRj9_LwJ;cY%*)WV>lcudOF%*31v?Z1HFHNMRc_$j~UkF3NRtjDHo&5rEO
z-#IAc7{T$J$~j!jRouYs+{+_8#S6U7dwj}JtVKap37MSfn3Z|>3g6(n{D`0PTb5&0
z)@H-NP}DDicI?bv{DVU|nv*z#^SO+Fb2E4G0RN2`{r>+6F7p;2@&)5A4w_2BRLsa6
z%+FW(7T@P5{3>jC|33&SvO0fe6SiUpcH?gx$Uixbe{nV!ab>iT{jV2n<3BvilRVFB
zyvrwyxg=;P0bgQTW?^o=yu|)r7res{`5C`qSyo{!HehqMWheGzKMvujCH6m2FrD+b
zlxw(&JGr07c!rmFlMncuah3*6B@Q`KG6S<S9}BZ6-(yLB$?sW#)mWE}*^;65j;`#(
z0UXY;oWfaL$Q4}2t=z*yJi&8;p{T2ZJABL-%YusHGa1t`Gjp*Zi?A3=uoO$POvLE-
zuPms^`fSEF46z6Maxh170;h2<mvA*Vh7Iq3hhQI%@-#2<2JiD3V=oVyO2iaQ&uq-g
zLVPpY$o`89KIRwvj^+6i>#z}9@K<(WZ}#Ufj^X6x_CHgwfXlg-TezDCd7Ni?g}3>L
zQ7eLm;xQ>xudx42f}AYC*Z4L+;HUhWKe7^QupXPTH9N9<$niS|aRkS6D(7%9S8)Tk
zb1#qZ6ff{PL-!m{8Ea)wRYE3bI%Z`azQQ;7E<fVu{FdcdH82!aThNfdupK+I7ysZ;
zj^-rJ;CwFQ-`vby5u@M#fZ$*L$IHCMhkU`ftAeJIFcmX02lMk)zQy;$hWG!8;4A*X
zimc9`*@Ugwf!+8U2l7vj<6oQ|ZDjw81S`3o+xQO;^CZvn8t?K6W3CPwO2C(xmRVNY
ze{R9ce4X#`Lw?3@Se8{-iw)SEZP|%E*>AP|4-t&wL{8^CF6A0-;!f`8F`nTi-sA&5
z4>{tj393rWl+3{F%*Vnk%J*23U-ElaU^UidsIj9Z+p{bCZ~%vMET?c57jgyHaVz)m
zP+%zPgy0;n@(v#}#@|6h@tKTin3=g)kVROGC0HtAC@QM7pbRUsChM~q+c3l)?90I%
z$qAgsxm*%9y#LjLjoiU~Jj&C&$Q!)RXN<izXetp?Fg>#|Z?uv97ZSY5;{2Fj@H>|0
zPprd6Y{6gIg}vFI!`9mW7{O%D<N_||T5jQP9^`SJ<rUuMBSx(Y8j80r`u)Sd|0k&+
zH8U|M3-C3*%@6n~zvhpu#2T!}rfeN@bYyq_&Osc(@tn#zT+CJ6!0p`2BRs{>1;=&X
z<5R|3A2gJZ$(fE>nTN0N4Zh2d_&L7~3`La_RAp^8<S%T;&g{iMIFzF~i8DB#%lLQ1
z==a|&*u?|<m;doHZ}A~tFz$w+sU%FrjLgCOd^K!%|8EK2=O_G%Kd>UJ^Jg|;D|TQv
z{>Fj)ljEX|?Ef#pY%bzTuID!X!^1qu^Ss8pe8QL;gN73DrH%HVR*;3c`7&SUJN%HJ
z@f((971m+{HfLLQ+Gzhh1^qaLqd1Y%Igd-ZhMTyP`+1CKc!@Vdjt6|sIGcj15;G+;
zFgx?HFpKg%mgJZGo)s9X=BUfYY{~ZQ%03*x;T+2;oW+G)!FAjk7>e2>IK&e?$E&=<
z$BeN#Xed6DF%2^_7Ynioi$#on{}O^yEX^{k%$lsvW^BU{d$2DDb0jBlTG;UZ=L(i^
zH8*kx_wguC^CEBXKA$o6mY}IbOu_WgM)sdgke7w{CX4f9e!=fpo<Fe;8?gm{Wf%6|
zV*mXG!#IYMIg<;xoNKv-yLphud6rjrn~%2Gf7I5XqIgWo)Xc=3EWp?JHb3B}{F*<q
z5^Jzt$kCLo*^%A(I|p$D$8##@a4}bL1GjT8Lq{B^c!Ae>k53tEThLTOCTBWkWgfo5
zH~20;3JgVkF8G$^Se3QekiW1UJF^%6;82d{B+lUch|%xAOz<~1a~BWrU;f9-yv2un
z!MNLlrjjrfGcrfm@c#1)UgcYSpP%q6{=kZ?&Y#(Yt=NIx_!|dC8`=M#f^qzdv$=>X
zxt`nj4-fMs&+{7Z@(E+^u>S-*f~sC(T4rHxzRcJ84nO2){Dx&&g|*m#&3D*;TR|uG
zWIqn!C{E;b&f`+9;U@0nejekQkmC|>@&TVS&d#8r#7xNy%+7o)%%XgcCHW;o-#aR>
z8tbw#Te3a7vJVGvILC4dXK^7{1csv43AS<%5Ag)g@hb1|F=Ols8j8<kOvB8~#exx|
z-@k~U7)!7eOS23svnK1a8QU<#9_-7(92qve{|SO=oXaI#&5hi_eLTw3yvQ58&u5Ii
zJ7_9Vw2}R%5Ts`|=4Bzi$>RK&U+_DY=TEG|Mr^@fciVp#L2vfwFplA5&g23v=UQ&z
zZXV=up5>L@_J3ROh*5ijisCUTQ!^8DvH)M>+x&o^@@xLcN+CxL)?-t)W=D4C?;OMt
z9M7qo!^K?14Ge8}?Bx-j;ssvkJw9cue}bkGGC9*REA#Lbz7ZITdROofKj*hB$EvK&
zhWv%?*qOcf2ZwSrCq;~Y{~3b$T*kk-nY(y^|MEXx<}E(t3&!0WG?j#@!iM*sQILcA
z`6}Py`}~Ao@ds99b^gpIY{d@j7HwqzzX=BNPmbeXoXtgC$@SdEe|VTDd7jsJcdz|F
z5yadVRFr@(F)gz&H(%!Ke1{+MGk(LetioFR?7xAaIoq-md$J#ga1<wUI_GgI*KiYe
za(~EijAwX>H~E0i8E1dcRAQ!N24-hI7G_bt$52Vfm;9a;SdDerm@V0!UD<~NIGkfS
zg|h-fQ40ktxQ<)7hlhBA=XjNO_?R&c1P#S!GNxhXh|%w#OHhzSSd1lDilteGm06SZ
z*^F%%Vh{EW8{Yq5!AMTvG|uG`uI5JW;65JZX<p<F-siJuBm0kiFsLdKQ!qWVF)s`8
zO%~_J{DR-HJbz*xHackkEd;-^3wyIahj9!ib0!yXIoEOvck>{RAGH6of-AhuM~pfY
zG!&0XnVOlHlLh!1-{uGWlwXG&Ke7^QupXPTH9N99f9D{M;CN2u94=;Pm16_9b1#qZ
z6ff{P@9`;P9S)jG$mC4NtjrS_ih4!x2H)jJ{G8vi9ILW68}b*nV`ui_9~>Gn`u#@>
zCUFMma~c2UX71tv{>%S(nYZ|mFBtcT{U-?@(Z3F)Vn*g*e!j}L_&z`3SNwq$S)D(#
z30p-Q*?$K?H~z+f{FCGO7iV)3S8_eK@gE-MNuEDq|JMX}`Ghf#2F)bkOH9iw%*~hi
zI^W@k{EXkQ>{0u#BB;d%Y|ggq#GdTOAsoetoX&Y%$~D{+a_r=O9^)Ba;!Qr_bH+Iq
zG?kbsnSt4vkA)d3>UfVO`6a(+1y*BSHfBq<XIJ*&01oHaz);i_!7MK13a;Z;?%^Sx
z;5lC99X@7^e}jhNGg-vw_fI3p%v>zUA}q!dEXC3+!^*75`fSEF422DU{qG^@%fTGU
z37p2cT*B4d$Q|6rqdd)vyb*0=|MvyY82floRU)QfdS+u@7UG*M&X4&8zhim+blm>y
z2pX{ke`Oc;W`7Rj7*6I)F5q&m<reNfZvO`b$9a}lc$<$Hbs}ge9+NUPGchL%@HM{8
z4?>Pl`89uJCDvd)Hf3veWOx3~K^(#HoXXG~$6~JH25#qG9^olo;C0^PQ^q<OG?kFa
znJzFCl~s_3uka1N%a8auzhyaAWo<U(FKoxo>=iK-74?T;C`WS=XK+53@o#SCE*{{&
z{EwG;ix0zw_y0l=_f$|-5~gBC=3sul%D4DFKjByWffZSuKSvwce-l9~c3?OD#)15k
z<M<b6a}if^J-6{69zJFNCk5wujd%HkF;52#CE!a;%Ph>zm-#y1;fMU}bSU@%zY&yW
z71m+{HfLLQVo&zt5RT$RPUk!>4LR0u6L)eykMRsI@g^VeIpdrOKCr}0$qdZSP(DXt
z7Ug>^$uIdmE3g{tvN2n-J-f0G2Ly(qh6~1W3TJU4S8yG-at{yj1kdp*@9;5W{1<L0
z`u*caj;N?)OvB8~#eyutVl2T@EX^{k%$lsvW?{qoZzBk?2m5j`M{)wEaW0o|H8*kx
z_wguCM;qDyMZpc;=QGAW8+<Y)VhW~bHs)m^zRBYJm|yU_v-V$J@DuB>5nJ$Ac42S!
z=P-`pWX|LQF6Y{__P<52n+JKEXL*IU`G`^Hf`;NTDN{2ObFu(m3pw8A2mF*@^G8-<
z4c22*wq{3m=kFZE5e$uYOywLd<|=OBcJAd7p5g^w=RH1Utn)!r2?Ik>$pz_{m3jCI
z-{8Cah@bOYmSa`cW<&nMb`hiBzq6nh|KL!L<|NMGd@keP+{|4(z<>E4FNY29|CZn(
zUoh^4psFNH#f;3s{Ct&f@qK>6ulNHiMjP3Gb-~YU!dC3SZv2e{`6tKmFV5y7uH<@d
zyI}wS2oCck&+{7Z@(E*J3>r$nmzb7Wn42&2b-r`a{y!9a#&1}bRalD+*qm+Ii9Okm
zLpX{PIX&c<$E94uP29=-JjOG;#G8D;=ZteHXeu#NGL*rQo%vXpMfn~}@=Jct3arMu
zY|NHy&#r-?s6K)L9L}+v!dYC%6<o)y+`~gW!E?OII}xMb|FIy(<)EVYOvW_K%v>zU
zA}q!dEXC3+!^*4~HoX7(f@W;P5PPsM2XiDRa2n@w30HF?cW_^{k^LVPoaRN|;C()0
z>?=W2iI{@vnT>f_h;OnuKfYrBUkJWqdH%#YY{VA)m0j4I{W*+dIGHoK;EMe(7p&zL
z?&d)r=UHCiZ9Zbu)u5qxOv=>E#GD~V0lvn!`2j!W*Zh%{ScCQ0l&#s3-T6C1gB&9`
zo>Mu8i@Ay$xSe}>gr|6c*Ljam14B`<t_4*kWOAlsR_5U=e1q@uBYw_rS&mg%n++pI
zzyB|ScI?bv{DVU|nv*z#^SO+Fb2E4G0RIge-v57s%e=*he8ITagQk)&6*Dpi^Yc}{
z#rOFMzlt`p{~rVuS)D(#30tuPyYV*;<ewbJzc`zVxbnLFuNQ3NKRnEnJkM*q%O{L^
zBWNfAUt(HjVQ#*B!~S0vyu%Oq8NXp!R$(nRU~{%*C-!7N4&kVfV<M+>9+z?rH*qKT
z^BB+Y5^wSWpEJ(Qps7$|M@nX3cIIPY7Ug>^$uIdmE3g{tvN2l*hN9XFy0Q-ka5%?u
z3TJU4S8yG-at{yj1kXi`e*de2JABL-w}Oh|Ga1t`Gjp*Zi?A3=uoO$POxW=LD+_9}
zKAW)(L+ru69L$lNz-gSzC0xyo(MI;aL$HrWd72k_gZKH2v2O=WC1MJuXEx?#A-;Lr
z{)-Df<`?{q<@poqun}AES9W1<_UAB;;pE%)KU1)P%ej_YxSI!goM(B3xA}-scY=oE
zF)34r9GRGt1^61@<_G+gU-L&+Vhz?~Q?_PDhPpd`=OB*YcuwUUF6Jt3;CAli5uV}&
zUJndK-4i@zth+%~37MSfn3Z|>3g6(n{D`0PTb5(hh|%v~ThNfdupK+I7ysZ;j^-rJ
z;CwFQ-`vbyVZ-}BAo!R6@iK4mAzv`=y`ZTiOvQ}M!TfxcZ}I(TBm4hE@D+bxMONp}
zY{FLTz;67F1NkS%@h{H4Xa9=?E4iNA_zw^BB+v62@A3&_-VYi|z?YboS?=3^Zo$iZ
zo$v5Ne#UQDmQ`4b4cMG**@->bFXR})QJl!>oX4eH!%f`D{XE7qyu_P)z|eC?oCiTw
ziJ6ian4S4pm__*>OY%#8&kC%@x`Cmn#)6h?&#vsl0UXY;oWfaL$Q4}2t=z*y5u@M#
zgy0;n@(v#}#>1eY_)Nw$%*<RY$RaGp5-b%qy#LaIGOWy+tj}g_!w`G0F9&lZCvY0)
za!It2{jU~m<PPrRQJ&^S-r#*cW9&ykQ;C>@>6wjrAK8B)!J913kNE|^V|o6>I&8!i
z{FPnUoBcWLk^PSmOy*23;Bv0z7VhRj9_LwJ;cY%*)Z?I`cp*npre-GQWC6a$xA_4-
z<=6a?l~{xI*p#8xj*jfk-#LgQIG$5Ehl{z28@Qc&d4#6|Ls1t5*Ljam8S6<<RYE3b
zI%Z`azQQ;7E<fVu{5E3r`<D|`Wo<U(FKoxo?8QGgl%qL`GdQ2i_;=Xw{x=JD@c{qj
zf4t0Fe8?A!`!r}O2~#m6b1*+&jW)9Xw*>F=6Mn@XSdrEFGn=p#JFpvn<3Rq&aZm04
zFTrds;!3XPHvYrIJjwIC#=CsNn9qWS67Z#G_McXeg}M1MU*|jgke~4zmSq*zVgoj3
zTXqULda@sfa1<wUI_GgI*KiYeazBsp3@<Ts)A4}M8RvOWRbr-O24-hI7G_bt$CCV#
z-?KtsD5{#EE*rBY+p{bCZ~%vMET?c57jgyHacjir_unHp#1lNntGvU<jPW99C_a-h
z4Kp(r3$h4{g$?h&grF2lvkWV<ChM~q+c3l)?90I%$qAemZDjv*1xvV^8@Yq~c$BAk
zkvDjs&lo!@M&vg*Ct?bwkBSkB{DEwOyez~wS)3p93x3D){E2ngh%NXlyRdguDEOK6
z7YySVPUcK5;Bv0z7VhRj9_LwJ;cZ6${YUT<h>8&yk4c%DnV6FW_!{5l2mF*@^G8-<
z4TkDDnzA)JvO9n0AdcX8PURdf<|=OBcJ2)fMI8~G;ssvkJw9cum_btsnVjjEm3jCI
z-{8CaC}Joo>T|)jEXS&>&4&Di?bw;U_y>n_G$(Ne=Z6jNf0^KKZssl?;J^HjmwAg1
z`GRp{1x+PkDrRJkXe0a2FL;%2@qK>6ulNHivO0fe6SiUpcH?gx7|Z_u6pZ6voXtgC
z$@SdEe|VTDd7jsJmrocow*4oF9aQxa(=rQl^JTuyclaSc<2NkJDy+o@Y#ws7WheGz
zKMvt2PULjX<5I5SChp{Z9%JZ?;}UQ30iQEYoS>n^Ovwz)&U`G)qI{1f`DI`z>U%*2
zR%2Z@W=pnbSN7om4(C`-;VdrXiipwsUnkhgJv_t{JjbiN!^eyfH)tq6lQ9i5GZzbn
z4e!5*pcqTA6ic%VE3+o+vl-hk#2)O+!5kTFWd9Qc(>Rw)xSAWegZp@tr+JY#c%RQ0
zJ6_OKqImY7LXe)>n3sk4CX4f9e!=fpo<Fe;8?gm{jc5N|1ijgx!#IYMIg<;xoNKv-
zyLphud6ri~j@x|1sQ5ue@tBmUnTa`BfUogwe!x%pHGgENlA{Leu_;@#BfIl=4&n%o
z=Ty$&Vy@zbz);k7!CoHWDPG`p-s4loN)R-akja^jS(%5g@QsMk`+ryP5kKd*EXS&>
z&4&Di?bw;U_y>n_G$(}(?|+71K9})tZssl?;J^HjmwAg1`GRp122CYls%Rto&nU>j
z{Ct&f@qK>6ulNHivO0fe6SiUpc1vjgzX=BNPmbeXoXtgC$@SdEe|VTDd7jsJH=+GM
z5yVUsRFr@(F)gz&H(%!Ke1{+MGk(LetioC$M*}uzTXtek_Tvza;zUm8JTB!LZsJac
z_B)R83@`B}AMiQjBo3NN%#_T)?99i)EXwx+Ls2CKU-ElaU^UidW42^_c4Z$9;Bb!R
z6wZnmz5j)R6<o)y+`~gW!E?OIJABL-NrHyrGa1t`bJ+0ya|sHv2#c`<OR+S|urh11
zKAW)(L+ru6(MI+^STK?kIE{0;gsZucJGhTWd72k_gZKF?iT%e;8dQ~tDVUzwn3sk4
zCX4f9e!=fpo<Fe;8zr^>7J^^dg}vFI!#IYMIg<;xoNKv-yLphuLyoh&!rOersANGy
z@tBmUnTa`BfUogwe!x!|`r7d$E3pRau_;@#BfIl=4&n%o=Ty$&;=oYUD!~SB=UyJ+
zDPG`p-s4lodMRisA(Jy5vocS_=>5MUc!TfqBYw_rS&mg%n+^F3+p#ly@ed9S8{YqD
z!6eS$d@keP+{|4(z<>E4FY^{3@&)52xBn#3N8}q2Fe7s?KVRire4n52EB?TWtj?d=
zgsqa>e+NM~{>Fj)ljHaoXLAu(ay_^4A0FmOo=<N7*93R@gfUYD%_QJUOv^0H&6oK)
z-{FV+jNh<q$Wev0*nrL1mYvv>{Wyf9IFZvik4w3Rp-qmR+|Oe?!%Mu$2Yk*rDTAgG
zGbJ-HJM*z{U?{4n;60Y)m;9a;SdDerm@V0!UD<~NIGkf6M(=-$U=|m01=n#a_wW!;
z@Eou54j(f{s-U6xOcpl0|1^Tk%*BE%!eT7JQY_6ftjwCM&t`1HP_&V+|2+hKIhZ3k
zfzvpbOSqaFxr6(7l&5)-H&WUEeZe!vP90R0h$)z!*_fAw_$G_<V}8N!Se`$nw*NYU
zMr^@f*@eB?pTjtYlR1+MxSVUbg}XzJgFMc&yu#aj#HchuL-ClDshNp6S%9zcZH7K@
ze9Eu+BP+26>#-?Yvm?9ncMjqRj_1_CP}Cg3Vy@x_Zs%Se;VE9=b>8Ds#!4GBm5|Aq
zE@JflvkLO?6~4iD`4K<ow=Bo1tj&h}h3(jxy~2j~|A$~GM{^Qqa6XsuZ*Jx;9^k+H
zkC%Ci52KCj|AioKx}d5gOvQ}M!TfxcZ}EM8!ms!PE3!I&PG|p31g+SC-S`^^@=uQA
zU!2WFT*>v^#(#J?o&BE_oaZ&(<rBtCA2gJJFEK5%FgIW3>wJeF^0ScR8<u4i)?x!T
zXIpk+Pxj*wj^ad4=RAg%I@WL#cXB_E@eD8VCLi!Q<75b$O3akZ!0dscsC<ILEXwy-
zl3((BR$w*OWn;Evdv;|X4u}}N|KWnMoWfaL$Q4}2t=z*yJi&9k$~%0_7#Zz9e)x#~
zbs!njFf((pAd9dVORyA6vkWV<ChN0Vw2}R{5ro)-eL0vTIf2tSmrJ;s8@Yq~c$B9z
z+W$qt4c_N7#?BNpl!z&qp4pg}h4?0m^J9L&?=sncdBIPt!$xeuU)hDd*`LEWhLbsy
z3%HzXLyj%n&4WD7v%JFFe8i~CK|}GFl&P7CIaz?A*Bo#21AfY{`6DZ_2J5jYTeBm(
z^LGy7h`><Pc)?W8;bN}h25#qG9^olo;C0^PQ^v{?G?g%7^!}3z(lIOZ@D;wncli-N
z=eI1!s;te1{DtkphQI!I7WCpD9Lmw0#2K8=W&E3)xr+z*FaP7^Xe0Z-C3wgejGHy6
zDhX3DBXcl6U*%hTpP%q6{=kY^?Z3L<XEtFgc3?OD#)15k<M<b6a}if^J-1~I1s~x*
zg2Oz?^Ss8pe8QO7f<He2Ut(HjVQ#+6*ZEG!@gYCsH!RC4ti=Xw&bI8tp6tgV9L0$Y
zO?S-WQm)}9?&N+R;~8G!O+Mgr#>pNum6$05Ls1z7*_n@pS(NXwB){bMtiWol%f@WU
z_UsxldjEX{12~*xIfb*hkSn;3Te*jac!KA6m3P91_y1TBBS%nCd?sTWW@auHWDyo)
z36^4MmSJVqj5f0W`hsR`!w`G0F9&lZCvY0)atT*+BX@9L4*NeUIL(W^!TWs1*g1oy
z5-|nSGaK`=5Z`2Rew;HD{6Jp_zGHd*#5!!m7W|c6*qi-1jAJ;NGr1t-SkATF!reT`
z<2=hNyv;|9$`yQI@tBmUnTesCjskp*Z}S6w%CGq&E3pRau_;@#BfInWz);j6!3d7$
zRL<dIuHpu6=UyJ+DPG`p-s97V(ff~;JE$rllQSK&G7n$j8+?}^@pFF5a;(bQY#27Y
z|6c^{*qOcf2ZwSrCvgVna~c2UX71tv{u^y%|NjXt^A;cS1>@!kno7b{%*Y(f&sX^t
z-{&X%Dv$mDAgIXd{FzPIiXGUEzi}Y{<T(Dt*<8exdF+3^U>pD8VV>l9UgKRpVa&Wi
zLkaj2(=rQl^W~7^b-u$7`5C`qSyo{!HehqMWheGzKMrANlw%^Na~_v+4L5No_wyLf
z@DgwG0iQEYzDQG{sKmh$m692lo%vXpMfn~}@=Jct3arMuY|NGsqxaul(3O2SfWtYK
zQ#gwYxq|Dsm3w%ICwMMwc>h-gclekw@&}(x@tKTin3=g)kVROGC0L53Sti=Z{woV=
zvOb%!4MXg~z8uVvoWN<E%OzaRjrr|=hhQI%@-#2<2JiD3V;2aTO2iaQ&uq-gLVUA;
z{TKgVad!eYQ`tTaeC$i;5hBViyNHl|57`OX2@%;VDNUiG6cs&{7K&D_w2+k2s?xra
ziuOfm-~acS^Bp~@NAJHk@9%t!?>*O?bIqCioa@XzXXcp^Xv@y*$^IP5(L9mUcp7JM
z9v3o`S93*DV<lH{EjRE9Zssf8${qZKyZ8eWHRB%2$0AIY&^VZtScCQ0m@V0XUD<~N
zIf7$3iKp<4*ks~tf%&|IS8y3`<n6qN4{#$l@ddulxA_4-PZ{d}8-bsht5)1q1zD7(
zSdNFXHXE=h+prURupfs+M)f~RU_7UC2G8PLF5soSipzNm@8TLh#K-w;FjfCA3vA(b
ze#|fVJ%3}~+Hp@6W^tBbMOJ5BHe!p~>c71}7xv}=4(Aw7<jI`LIXs^i^Kvfb4ZN+k
z`oCLX9UtLSe4ejy8{g+={F*;8XPvl*3NV8uSvILrg|%3pP1u?p*`0kkm?JrkQ+O)R
z<he{<sIiz=@;ctkJ9!@;<YRn>FY!&j%a8a4zl%*Keig`bSlm^GSd67vfz@~z8?rgu
z@o4tqu^h(ZQ-=DVAaD{-=WL$Gi+CBY;q|<gt9d^k=97GmuSQ1o|CYde{FGnuN9L#-
z_fUTB&jWb~E3+mK=aFp1qk^gW?<Q~z2k|(bz{#A>B+uamT*M{3mN)SZ-dk7wuNQcf
zPxD2-!FTu}ck)~Q!rb-Zp4yKG@F13F)q3i`j=&LY#<uLtp6t(|9L*Csji+%I=W!u3
zlNwiZ1y^zv*Kz}&;AXzUt=z#+xQjn9ad_NA$$T0`Sb_($5^Jy?8?z-luq*p;AV+X4
zC&eZcrwE+EvpJua@Cq*Djl7-r@Bwb*CcePe`F6@s{~ri^&TsfLbJdT#svwK96wC2Y
z)@B1XWgB*4kI1P0`w0x;D30e;&fr;`%LTlYS8+LS;ayzAhk~j4e_Y^MzRWG$&X4&e
zzvpkv+aT_#!Ys}*tjOxD+d%y{5@^Bp?84q0z~LOji9DGzIfv)-VqVUr4b=Y)0=MyQ
zuHz$oiqG>kZsYs>j9>F7<~$<qp#scEYLsMIR$(pHXA`z&M|Njl4(3RX;}o9C<e3`h
z@<J}=mAsBO^G@E!2l*JE;Y)mz@A9MAWa0~f@Axb8G>p5d5R0)iE3g_5V?#D)J08tm
zJT_&h|6u~ha{^D|>732;co8q-HN2j;ay9Sg!+bI_s{iK%UgcYSkDu}@{>U7S;vUM+
z{dph{VP)3j;XE>!s{d93N3k1^;UFHz6F8aEndCXVfQz_<*Yc)D>i-Ubd%2#E@@c-v
zH~0=e<W7FeUzodb+*AAU03Os>{g)T0$~ruP&DfTm*^~V_l%shfr|~q-;=H8BLT2)6
zuHZ_p;#zLt6Wq*KxRpEj33oC1gGS=WxQp_!2utu_R$>j-V`H{t2X<v24&;c~WMZtq
zB%Z=EcsA$r5?;Y&ypgx_9zMX0+{71BhWdY9;B9`u&-o31X09f2PZeZQmSQ;`%Gzwe
zrfd@#)qf{}9_+^<9L4dR${9S1bGd+*@+vOpExaq3s{b_t5Akt6%a^%@+xaoS<oEoI
zd7H*PRhY$Dh83Ht|LOvD*@!LJo?Y0R12~*xIFToFCg<>cUffjuUoNneH}E#z&2@Z)
zPw{!a#%+9`pYdz{#GJ`yaTgU}21~LmtFRX9vk6<XBfGON2XiFHF*!x!RG!Imc_A0`
zN?ymCc_;7VgM5t7@Fl((n@qeb@Dab@cl?!kn#Vm=h{af%6<Cdju_2qY9gj{K>c5x3
zu^h(ZIe{nfbk62^yoi_a8eY#^xtjM!M)m)&z>|EAuktOv$4~hce`JmpaS!F^{ydO}
zurg}~Q}utiz>#dlqu7nda1f8<37pL7O!6FFz(rirLj7MWa1-y~y<E>n`7~eT8+?Z!
zawos#FU;LC?y3D+s{aE74q|y$WgQ;DW^BvO?8*Kd%F#TL(|B4^V;1LeAv1Y3S8yd)
zaV<CS32x>q+{ztHexk99KQPfM?xK7w!V)}~l~{xI*qANZfnC`rHklYGFoI(_iKp-k
zp3V8ZgjaAGZ{+Q~hYxUL%25BC1YY3le48KebAH30nX7f&Qw3R+rC5%KvNjt;M)luR
zpba~*2m5gdM{zu-at6=hTrS|Hyo$?%srtV~;4ZG=Lwuai@?~z}c7Dt+`8|JQ-ZpVh
z6=v}^>c5OYMOJ5BHew65XBYP701oFEPUOj)$vJJ3@fw{ka4|3EQr^JZcsJMa5kAG|
z`5L$JeSXHTlNvuUXWMv%3NV8uS(a5;i}l%rt=W;?*_VTv9H}vmQ+O)R<hi_%i+Lrl
z<ITL2_whkK#%E%aiI)W4<h%TcU+_Er$~^7jo+`v*EX@k6#>3c<%~OW@Zzpgxd+}Hf
z<MEuplXyC3^E_U}%Xkg1=dF=Z{jV0dpAYj%KF3%27T@Ei{E9y^NBg*k@^gP4$U}mu
z`mZcdlZW$2w&GFj#$z~$$MFPC=5!``4lii0{uc=>;kCSpcko`W=c9a@FY*n(!w<QW
z-}0CC>OXgfxU2T#0X&H1S(SBo1e>ufJF_SIb0|mi#H7YFp2k_6$A!$~)m*`qT*bBA
zz$dtwuQ0h)V+TLsF8;v8QE?CDV-c3%!K}m@tjES|$quo}L|1`69LNzI%Sk+iXYg#!
z=Ow&?%XlMi=RGMy{XZbEk(>AeU+3HWfS>al{>)q*<DM$WqAbO7JTx+@|Jni#*pzM9
zi9OhlLpX}#Ih8Yb7UyySFAb*Z|0;pyyoGmh4Ikp;e3mbB3%B!Qe#!6o8}oKj|Ajln
zT~?fBSdrCPmyOth?b(IBIe^1Ch7);mC-py5U=Gjc#k`zLc>{0b-CV~<_!OV#Yuv{7
zlNz7#YyQNXo#UP<zzmjTSyo{!)@Kv8W=D2svaiNqj^sE_;i){6=kh`>=9RpTH}g*3
z#|LARiN^$<;Y)mz@A4yl!SDDh^Bf)bR3R2)X;xr09+ooHe?x)hY{#S7i^p;pkLLuQ
z#M3#O=kX$5#%m&@`oCV_R<7p#e3(!2Iljub_#QvySNxGVy2L${pZf<>^?#tiA*{@r
zJe)_e6^~*!9>YOAjwf(3r!(0_{huRn0T*!zujNg=gZFYhALY}0k#F!Fe#o6&)c>~v
zzc6>#xU2T#0X&H1S(SBo1e>ufJF_SIb7)dyG*9F-p2k_6$A!$~)m*`qT*bBAz$cj8
ztnmuBatA-*F8;tox44J$u?S1>U{+!c)??$?WTK@&2X<v24&(@q<s_cMGk7-V^AcXc
zWxO$EsQ=pq?%@O6$W45Kuk&qwz|Z*&e`c=kaZeRwQI?8~>c5=8p{&gYY|1w5#2)O&
zAsof=oXQzIi*tji`d=V$DX-#k-om@Mh7a*^KFgQ6h1>ZtzvTDb)&Fk-d3(fNRhY$D
zh80<zb=in5*q&Y3n*%tUV|u9ni2^5cCg<>cUd+q6lsE7;-pzG<girB#zLwP3#`pOd
zzvfTO*)#5;0?c4ZmSq*zVtqDYYbHBtbZ1`<=17j?6rRd6c`h&HVqVGXcr)*eO(yOW
zc#x0r8NS3f`7S@=7yORDGEc9#rwXwcOS3}CQ2*5g4r4<$XFDFvUObk=cswWYB%aRM
zJdYPeM)iN0z%{&{w{kV_=fixG&+%2h#rOCrzv7R~(OdoJ4~^6p5b!`A!pf}4!+9iI
z@hEoVF&xC>cmgN)R{zrll01hOa1odATHeGvcrVxUQ9jKV`3B$Vt^Pk0*vW7C3v>60
zduTr%z=K$xRau8euo>I3GkYdA`g15p^F&VLX`ID*T*ypb%@th9Rb0#D28}1UnXhmw
zckmPL;txz56ZcR)7GVh<%u1{gn@rRbXv~)Ez^?4WfgHiHoWxUj2G8bvUcxI<hWcM7
za3gQ$J$!&0xrs0Eb-v9H_&LAf&&<^~?x}*2QT-PcD8+I-l(pG_P1%N>*n|Bzgrhi~
zQ#m7;dj3C4U@jN%QeMU7yoGmh4Ikp;e3mbB3%B#*zUu!=f$#Yn^Y)9osxXVQ3@fra
z>#`ABusyr5HwW}n|HB2wa3W9UOwQr?yqK4BDR1CyyqoLz2%k!7JkQs-jqmd_e$Ahl
zvwz$}1(?B-EXyja#rjM((P+(%?9RR%%#j?&DLj>D@?2iX#k`W&#U>Ls3*5>3_#hwS
zGkl3}@?Cz!FZdmQWu9Z>o+`v*DMS627O22#Jd6$5ob7ltd+}Hf<MEuplXyC3M@IF3
zp1?)CjMwmb-pbXypAYj%KF3%27T@Ei{3@8L{~rZ%42ZiZKlkT>JcN~5lZW$2w&GFj
z#$z~$#|=>bCkRaDbS8NYFW@3B;kCSpcko`W=c9a@FAh-uZwS1@54n@y@)zbF828kE
zJb(wWJgc$}k6<&lO=@&zPxj|fj^>G+#?v^9^SF?iyqYVxlF3yXYq^0>a5G=wR_@>@
z+{GW57!>zVJ{DmK9vquYR1&DcdTh*=?7*(<!+{*Zv7E$Hcm~hr{FI^oFA=zc%XlMi
z=RJIY8@Y)u@O8e;5BNF1;m?s#{pT7ScU3_aWhs{9p{&gYY|1w5#2)O&Asof=!BqWE
z6_~-ZIF}1}DX-#k-om@Mh7a*^KFgQ6Ww83+F7PqG<oEoId56S3RhY$Dh80<zb=in5
z*q&X6sQ=yq12~*xIFToFCi5oZ-+(L3;w;08tj@Y@#1>)yOTF}J&o1oE0UXXT%)|Xy
zlqGoxD>1zShq-<PlT9^R^C)&@dPR<PeJDq994GS>&g5*);{q;@O(vEIEaMHlm8-ah
z5AsoN;`4l!Te+PdaVNu1M2DUa{U3fkGqnkF<cQ73!YsyvSdLX#ll9n$%^5zgkjfw4
zr$`yjPoxavlDPhd3XJB7oW|2Qi}SdUnY@}SxRR^5mK*p)FjfDX1zzD+?%*ff#UGf+
z89$PIEW#2zn3Y(A_1HM4-~VhW(1BgqhXXl+V>yYZ@C=^K`MiWza2apR8Mc3P=HqsO
zd-wo1auZ+R>wKFZ@N<5{pP4IHd_M(Ql%<jy<#;G-vjLm34Lh+1`*8?IaXhDT2G3%0
zuEqjh%B#4Xx9~2m;X{0!&+=t%;dXw^FJqI5?*)Ei-rR9l6=rdkVMSJFT{dD1wr3ai
z<^T>)8Mglzfr&hsGdYLn^I~4krM!W+@oui;BYcX_M@G;8uL*49`}~Yw^C#vE2mffN
zEx-(xWLZ{WE!JlfwhpH1zoS5R_T^xX<Ty^@sXUYC@<J}=mAsBO^Ugf#|2}~S`52$!
zOMH{>@*{r1@Axb8gy-j|rwXwcOS3{=^<PckFg9d!w&T(4#bY^)$8!Qt;^~~t^LSBG
z<1${u>v=0z^L{?eC;1#-<y(A@pYkjI$YhRuaTn$1{ydO}urh1%a30B4Jc`|T3<vQz
zo)DW%Oct2VB+uamT*M{3mN)SZ-ploTluz?TzL7F)|91pF<W7FeUzj_8+*AAU03O8h
ztjan(g3Z{Log<_A?<vrqLpho!avD$LEY9OXX7XyT;7YFI+F+{wHwZkz&3uJhxr3i@
z7k^-)K-@$5ScD~bFe|Y}0rg)`pfOvr1G};h2XX|*auQGB89bZwc?qv5p#GN$+{oK`
z4<F!0ZsH4kop194e$H?BGjkP;d#YekqbN(U91mq}Hege>VJG%rKMvt2j^|V+XK0+o
zxm>_Yc@>xQ7T(1*e29<pS-#9I+#Z`ud@S%Kzvpkv8(!i>$MC`|&N8gX>a5E~Y{B;I
z!rm#v_8%ZHoMSkVCvzs}@O)m(%ej;{@HXDfb$lc;s{f}1p66@a#`pOdzvfTOSt#zI
z0?c4ZmSq*zV*OyM{+kH2W=D2sUk>I-j^h-b$}@Q`FXUog$?FQK|C<Hw<b8aQkMSA4
z#5egaKjIhsj=wTbc%7aa53pEa^<P?`0;};bHe_?Q<I(KJV>yh+a{^D|>71R^IFA?c
zGG4>$c`H}*em=}6`5a&6TYQh7GWnIpkIYdd?xOtMp9k^~R%T5e&Li21N3k1^;h@-L
z;y8g5IGNL#<T<>6i@1c>@+RKFd%2#E^68Xe`@bmg2H)X_+{thG3v=%u_tbtofCsTW
ztFjJ{V6(`m{@V(4W>5C#P>$w_oW|2Qi}SdUnY@}SxH6ck|5XBOxq(k`Ghg9W?%*ff
z#UGf+h<hj>i?9R_&QSlA1ZuDz8?z-luq*p;AV+X4C-D@X!LvC(L;YVOa0Qp~M&8bQ
z_y9L@6JOx#e48KebAH30lN!0g3B2gYRFFkkisg7HYqJ5HvJE@22m5gdM=?2GV=8Cx
zEY9TuUdpSuoVV~UuHi#`oX_&**kodhz;=GjFZn%xW8MSeo+`}ZEW?Vd&bn;G7Hpp~
zZ2v9-y*YrxIffH?GG}rQ&*#OwoJ)BFZ{yvOQT?wIc!W>!dA`PNe4n53YyQNX#o`_+
zzzmjTSyl<A>c5sieKuihc4T+<<zSBFI8NcIJd@}0LM|?*{;w3cjyLm8-p2>|7@y%w
ze3S3;BYwf}_$%`iSO0~=iTkMhim@~+uo@3zLpEnS9?f1nmcw{FC-9`C#_62R^LP<2
z<2AgVw{kV_=fixG&+%2h#pHV$pYkjI$Q&i&p2^Ssc_0sAW!B{3Jd&+=6uZSH6UPV)
z;&D8IlR2G9p2G{ch)Z}aZ{i)im+Mo8?f<C2(|nO{@Ev~0o&1)+F!zCRPwmG8co568
zD(gf>^?!swGqz=C_GEt!<!GMBX*`XyIFAdN$*Y5@`d=ZilB>9u8~6k_^A&F84t~O2
z{DFz^?o?D|`B<c+`Y$1HFe|YJ>#;FgvID!a4+nAt$8r)+;Ta{>|Jefbc?qxJGTzAB
zc@H1pMsDH@e4TIe1Ad;=_=Z0-SE;zG3bH6mu^bO&Z8l(2wqYmsU_T~@XpG``PUQ@q
z#kpL-OL-NS^A_I4HGGJV$0ifc3cSoM+|G~rCBNry%zIGWQ-xWaWmu8bS(lAchV9=%
zpgp^=HwSPy$8aJ~=1k7v`Mj8yb183#jOzb3fxEemkMJoz&)2w(@AET$&7YXFblgJ)
zn8A|4RQ;C~sKQ#T&n9fmj_l699L$j%$0<COXY$<A>i<H4#k`W&@n+u1`}iOq<1>7T
zZ}MG!#4q?=Y4!iBK%Vf%eRPB>#9}PX3arM%*pSWHjz_Z>kL55PpVXMZlXyC3^E_U}
z%Xkg1=dE1L`}r`R<a12Es__=z<EQ+JKQhO`aS!F^{ydO}urh1%a30B4vB|_y0^N8F
z2k|(bz{#A>B+uamT*M{3mN)T^lwtedE3lrA@@c-vH~0=e<W7FeUzj_51|!;+_TvFO
zh~*=r`mZWbhexm(+p;rzvOkA%G*9F-p2k_6$A!UE{bveX%@th9Rb0yre1e<#3b%3x
zKjAL^z(iT~pRa7(RYh2W2eT4uupS$;B|ESy`*0vfa4aX4RsW|5oWZj>pO^3oF5`{7
zo%iqoZsaDuz}NY9QsV=D&TsfLbCrvGs34276wC2Y)@B1XWgB*4vWG@L4&f+{=Ty$%
zS)9uSyp&gQId9=zToap2JS6ZqpXJNk!tMN+U-EnY#=Pa@o+`}ZEW?Vdo-&z8)D>vN
z7HrQh?9Blj&M}<GlR1-fcs?)Y<&jbSFBQ0fxAAVS<0E{E&+|2I<NN%KU-KvCtPuB5
zfncisGXzSqEUT~<>$3@4vm?8+F9&lZ$8iczt)TwT6gZa`axt&ub-bB(@;*Mu$M_6i
z;+uSzA5{q3KRQN#A@Ci4WuA)h?S)v3rCEX1co-Y9Iot7Q_TsTgjbS{V6L=C&=WL$G
zi+CBY;q|<gt9d^kX7Wjm=lCk$;(Pp*U-3ugs1)~5e(ui$c?c`BCJ&EICXN(n#iQ7b
z$8Zpj;|ZM1=}ht*Ucg0M!fR88?SGTN9lV$8`6!>}i+qFc@I&t8xBP{<E5|*x9}kF(
z>i-~t@~p}_Jc7;GmYvy?{W+AQc_OFrG|md9>VKZVLT2)6uHZ_p;#zLt6Wq*KxRpEj
z33pXi|33&Ms>EHCk40F52eT4uupS$;B|ESy`*0vfR8jw91t#$np24#@pO^3oF5`{7
zo%iqoZsaDukkojcZ}S6w&TsfLa~&G@R6!PHDVF1*tjz{&%48djPVB*c9Kul?&#9cj
zvpAOvcqy;qa^4b~Oxz`~h7a*^KFgQ6h1>ZtzvTD)jd`oaJyn>+Ste!J{uKqPvo0I4
z1>3U=dvgGXa||c)WX|Lqo*x<2|HT5Ab184&ZM>W7_z0ik^L&ll_&z`5*Ze7%s{fqT
z;w~z{43=bBR$(pHXA`z&M|Njl4(3RXtET>^2%O3@c`h&HVqVGXcr)+heSDCQ@fp6v
zH>;`tcLhG;7yORDGEeomrwXwcOS1y2@h~=IbGGBrNsV4Smcw{FC-5Ym&e=SV7x6M)
z!|Qn~S2KCP#>0G)&+%2h#rOCrzv7R~Q6ui5{M?@h@(@;zO(tpz9L^)zibt^<kKrI5
z#}hc2)0yNsynu^RhV8#Z;9B0qJ9sbG^HDy{7x@O?;fLJGZ}|&z*Hr)eMU8MAIDiMS
zJgc$}k6<&lWoPzee-7nnp2%szRQ;bOFpKlJkeR%iE4Y%YxRx9E1UK^)Zsm@e>i-jg
zUHpNGT5-?hV-c3%!K}m@tjES|$qwwwKDE^UK!Fh)%Sk+iXYg#!=Ow&?%XlMi=RJIY
z8<QHF_yS+&+x&o^^BexmT(#q#D#)TN#d189wV7<7(Ufi2i9OhlLpX}#Ih8Yb7UyyS
zFXdIS$;5JjTX+}O@F70VXZbR>a63Qdm;9c;F>jr?rwXSG+rPL#8CGO<)@38MV0(69
zZw}yaj^RX}%$bqV^Zy)y^La5Z=ThFl+juwE@ew}7=lL49@qK<4Ox6F_0zWb5VR07~
zU<OOFEUT~<>$3@4vm?8+F9#o{{znRo;}o9CGkGpA<YHdQ>v%Ko<b8aQkMWtq)c;EY
zZ}MG!#4q?Ae`TJ!aZeRuF_vZpR^wr8$mU6nc08KBcr1tUcuwF+Je{+79xvi$yoT2^
zd8@{1-p_~mB%kA}e2ee#Q+~xCnWJ9ZL;1Ns4~$JF4iTu#nmn9GvK5bFHy*=5JdP)D
zGN&`ib5e%we}TXvF5$JjiFfc`uIHnCnlJJVzQYf>lix;0_5X`N?$A!XVZZ};5X-YF
z>+lFRV_SA+Pxj|fjt-{k|3ralJdLwBj|-W}tGR+Jxr%GKflqKVUpZX;Zxz_VPq>Re
zFi}75p?oaD5<HldScCQ0m@V0%zWVPf(1!y#f@3*}r|=A(&H229S8y3`<n6pCsqp|e
zauZ+R>wKFZ@N<5{pP8#c+*1Wvl%-gX$wM`2vjLm34Lh+1`*8?IaXhDT2G8PLE{IJg
zE)}?n%Xtg$;u=20$N4N@<`!<}$NZAt^S6{?`{z9(?yABp&N8gX>a5E~Y{B;I!rmOf
z;T*$>kx~7hEHIOEcs?)Y<y^`ecpLBLIzGau_&i_ZwqUCM-xv6dU-KvCY#8@Y0cNly
z%d!e<u|AuyH9N9<L-pTRU@%8=9H;P9=1IgWv>%Hyd?X}w1TDvK3Mh3w4E<7uO`ftT
z+l2d11v&}zU_TDwD30e;&fr;`%LTlYS8+LS;a%bWQ!B8B5Akt6%a^%@+xaoS<oEoI
zd2_`1(|^of-1Ra{R@A7@x=jBSdkfdwGkig6YK6lWqooXAh>~(R$8aLE+f?CmPSJAV
z`QMs`v*f8n;XFdhFv3b1_Q90DZ?pJ%cAG4HhlMOxjNua=sXP@J&gg{eq5so&6!xvu
z49(e&N3$1?<uD%42|S6Xb2iW8MZ7FBs{d;QuIH^>&HMQ<pX76Vm2dGqe#)=-Bhz1W
zkUwmqRQ>O7TOG(lSefZ>I5^z(BN=`GCDmi$i_cSrFFZ{dzUVAv_=1y^$MFPC=JfFW
zBdHmZ0_X4oF5(hi%bR!y@8x<v%BT4v-{3p^Fns?=Y6W%*e9K>$J7;|RemsB&u{^7?
z4v%0nwq<AbWdEebP>$w_oW|2Qi}SdUnY@}SxRR^5mK&ISLSr*u;a2Y8C)~v!n8+3P
zP(Bu62_DQ!tigJ*$wXs;mh8Z;?8AW^!LgjgQ+Ni?=6qhlE4VCW*#0*P+|GOW05@_I
zU*PL}n;-CVe#4)cD|g&e1z9vQs{c{~<#;G-vjLm34Lh+1`*8?IaXhDT2G0tn>VK}l
z0$$3ixSY4}F0SE2e4NknWp3eie#|d(tN-r>eq-Kn5RYC76=rdkVMSJFT{dD1wr3ai
z<^T@QqyEPTOytR&$vHfq7xQv1<qf=zcXJ&d;ZuA*sqq@O@qK>AulW;m=8b!(05e#U
zWm$!_Sf5RpY^~9e-PxCeIg;Zzg{SgNp34ilm{;;T-W;1u+$nG$ALL_vhA;6=zRQpJ
z1;693%#$zfsX{Eq(ka9CuOLv3hp{1>vmK9SFCNQbJf0JH5>MxBo);O_|3w0q@fu#w
zTe+I|^I<;8=lCk$;(Pp*U-8Fas{V82kGm*8_ve8;gq2y7hx16b;!*6zV>pP%@r3;9
zf3m=ICV37o;36*JwY-UU@LsOxqkNh#@{RoJ{~du3xs%`W7v?Sy_tbtofCsTWtFjJ{
zU^BL5=cGnY_UBNJW+?mA5pmB~JciMKJBrS3aGTtxquak9+$IzIa&#L#hwOcD8@B&G
z9Nqr?;5MrNeK)#|_nEy7Zd3KY&qlY#h<h2_#^e8eHM;%#!L9n=N2A-nAKWGl4)@LI
z_U{L`$$dJy4LkSW3~rN&eL1>~>VNNp+pzuj;pjG1|9c(WM)kk%Mz?YO?`?3Ks{eg9
zx;0qc%iuPy|9v&O{rkbK`rk*R+rJ;&CXG_}&FJ>;2e-+6I=T%z_umX|lZkyfx{d08
z?}OX0{rBPMHdX(79o$Cszwbu3asBUYaGR?CeKxu^c-_n3Hm?5@%{YyxaTe!sAv1Y3
zS8yd)aV<CS32x>q>F@vADzJl}a2J2ze>)7{^JI4Gu>YlYlB3v_y_r7QJk<439LLE#
zg)=#u^O$}^VzKK>m|UiD18?KqT*pWF6rbm7+{X9$8NcRF%<0T(f!JgsLm=I?|Jix_
zf9te;=>LCo-aeG=H6GFR{70wlqx%0R=k5Rgl}+|9Y{FAcYM(0{Ox1sJfikSf>I@&{
zNG;HaE!du2nBHjzxIUa?IFTna?5uJ9&k;DE7xQv1WqKd^r>}zlRDR+9|EJ~mr}qQH
z{ijyo7T(4G)%$_TJ>L-gU%elw%#(?|zd!eH)p>Sh9{N9hsQk<K=l-oa&#ug)`rq68
zbN@}9|0i$HrRsk#@6V-n&VBgyTwMRzzdsjO$KK9hL_PG+PhhD3Y~P>z`!g7+9@_H+
zM%F`Yw1U|lVbk^hPY<#G?GZ8g=R@KjkBHqIkdEOX9>)`y9*9hLJ^jGWas2`=q5()U
zajn2jyo2|0Js;)Me35VP9e&82{Fc8kxADe)DZ^?WAdvok|MIR^WgQ;DW^Bv9{9gaC
z&4;>uuV3pQ)&DFr&f`M<H{a_Y?R1;vd4+%Vwf?F4|F^%_KfP1_2Sd5I{{Qbjf}#Ge
zv2*-aW4X}f|KCHo^r3a{XQ{Iv%l#+E_-J3q?hv00pTXGI$M{tKY!30s#D`X3-yP%Q
z2l&^A_^|!^|HEVazw!}`sQ&-{EOq<{_Qgr+RQ>-Segq?~|NpCxU_`$^klH){y%!X5
zzW?~;e7OJA3XJ1Fd>Z}7&!WkH=V|ospGC8IPDm#H`g3{vdfcBL_J{ueKN<IjvQG{B
zqx%1=&*eqO?El4cLaP4%;&XZbtLKEc{{Q^Bytpd<>2tz=Jp4}Ae|qoypC1R(^*<_`
z<G|mY*IQ`0OkT|uT**~j%MDCEp|P2-a4UE46Yk;<OnCZE|7und*GuqkdNvup11jFu
zRalGl*@Ugxk=@ysgE^AvBkB~_Pvsx?jnMzuzBaSKKYeL7-12)l`xSrwCw=xS-Btg=
zusKzp|Hh~}Rsa8oXF%in|NkB~+qwSxBV^eA(V_Mqd~*5UIYOq#|NsA=T>kHlkm(OD
zC;#y$m;aqnb25?M>;LD6-c)&p?LSJLrVkkDA=uv?dKXx3G1G6UEOR~mj!OD{f%G9b
zeQNi?XujzA|4|EUV*0I>S6xpZinqJ|5qI(%rr%;of4)C`NKXIlM=@1XniYbn`mZLi
zEF2qimPjPtj|^`HG{_eW$LDF06%vV+k(CpP?;@)v5+(8nYdC@)8$Rn1tw>nDL1ehz
zI5Onv?|SOoQIya1aIUC+Dsk#rEG&>ZITY?-wHfY<40rUJ>sumgWRB>RQNQ_==^aN6
zA317DqRxn^Q|nCo!?ojvPw3S@z9BS6j~&0e-F5ib@gpWq&s@+cqja8$BZp5Lo_T$z
zjA=Edj2d5O+NkN%>U3<~WoX;h-G=s>-eK(MiFLb9J-)}N2_wf&IKJ)h@#9AfKW<!R
zsm>X1*GRk>`mAVJo%9qv=IFp3?F9qECAZ6)nH7%CD0yTQ9+)+}$KqYWZRy3MZu))k
z$?3(TC%E0=Jr*CCW$__d=gZuXUVLcQ@E(hwo@Mc2S?9|v+QrHb&l=ui@o2N9SAIm+
z`7(#67mrRCX1DSyvn(DxklpiT-kDxJs?puyJ??#Dmc>VBoi8&-S1W&f*6<#SNBdNI
z<)f$S-FK7OGrjoOtl>Qt|2oU!(Yesy7hjfMJUX!K4)3vep>REY@8h%1m-%IS@e{L#
z_gFmo3!U`h(X;sOyUA?b&10XKHN3~-(W%Vz;*+w@mw8co@#tu{JL?{c_sOz&G|bvP
zU*<dM#iwQs@3Hv!EQ?ReI$vhJ?pFS!tl>QtpOa<rle5m3c~*My=n%eprS@3-$}EeA
z1JUpEWj>!?{M4-BJr-Y`W$_tV=gX|n!^)qQHN3~-(O)K|dp@eZ-D{aSIlcJItl>Qt
z-;rhUGqTQ?xgji`Cpy|BGq?80$SiSiXr`y=PNJzv=J1{w#Y&WluciJ^-_$X_DIC~$
zPwAU_M>kc?F*Ked9gSv7w<pGP%t+0Vd1cRx;>mNu&0$>=VYHB%ehyduD*46X)@Z))
z%#)g;KfGG49g)6^3q!j=xU>qFXnMM2k;G-e=n;pf($suW{$=43@+EgCye}ktE(Ft4
zI^k6zkTv1RQbiKgLM%$yAY7vPqJ-<iCF=@CzndBrY<f!Pi(X*;p08#iF+U`XdOAwj
zFkI3JUk>f83BS&~vsXsRWc1|!`|{z_iCGqJoMrLP_E@}Q$Q%9bW_n7m&qpDUHQ%}{
zk1u*@m0q3bZISTr_YRvL24>CD+02-_8s^HHa7UJe(fsLzwc>=kH^AzUuV9vZ={=&I
z`Qn?xcx-)`arObf&lzq{O|AC0<3a}&Nh}R(5_N3La7o{Bk3S?#BwB~wUz5JKFkd>~
zh&|@}v2-HQBi#S)DLvzm(8&6TS5_>N+W(?EZWAu)J3eWTgq_QTQrn&F_dAaM{4s03
zPeZ<F(?<D{?Xo0{-Vh4^c29Fc!e_Gt(#^9&BWuFSm5L<p2(c((hj2-+;O=~Sqt_wf
z1HxIhNmwL){JRsH@ul!<Uv-Pb2|Mm3;g4agw!|{gTK{PU-Ilw4kwpGbK+y_z{zJZS
z|EYz{xVT0lQ76h|$}VA{hQD`VmoRU3kNA<0FM8RWp8k}tt~+j*C1JNPcXkPPW%leJ
zs&>x~J3TC(K8p0%%i_hu0U|o2rKdlwkJVWo@+}QBMIF{FT=rO<&}(MAHYDsBW=K!j
zC2ZHINMcx+DN5KUT=qz~JKt9!U#@hLFkia)#|Iqle|bn49e<*P(J7hi5`J4NkvJjT
zo}T_XVIuKT<06T<VWucw|8U7J->}+=#J1>Fbb3lR|G0*U#GvrYbk#yHMF|IlOLhrc
zhW#V!lV*1L<}@vmC?E1f`I3Y7l5k*1STWq5p0Z20JS0r-GwCsW{;<%VRXa1}dp(^j
z81nsf)jk~(Mt|cSt>Lh6$?g&Nt(!>H&ImJ@vRlEIniWY*4+rKb--vMeJ>MQxJG)gP
zQ7)Y&%$RQOxk<WoFOrxPZj2I+{6oS&9tEy#9o{65j>4vNYj?iruc)JGU5_G(g$r|}
z5~g1Y{8blLUYa8j4Xe}BpAyQ~<(>T#)5A>B3XTbv-yiWGS1@@|NO(r{>~6{~;l_~g
z%ocINs0y-6xc{p;64TO2!hGrG?ni6|+m+8q+!*~8eYA$ra3s5gvtP@Rh<4KSlwHD4
zD`X@lg_)v!6T&6CeA`04anW;5YD#baaAnUm98@tQ5&b4?lrT!1UBb@q=1BayJ7M;Z
z_~5XoPTDWdHzl1f+W+?~la8O}NJJ;0(^I;+=L*gbKQh=q+!(E3`c=qZ?K6Wv%aLf2
zP7>x#H=}&fU-2bc*(N)V%t(xpF#WpZuM#f#JV#<hdhPZ|m^ELQrWuL*!tK!tMmytQ
z^k7{7t-{+S|H)31yII&IR&d5&Ck)Xr{{A9I;#?0Zx}NnBXI;UK&BL!4z8z+a*6{Rj
z`HMA-mQOVODo0{ysulm2UBcz9LJx*nqI~IBH-FWGSA={GqZN!FfA(uwsC7mn`lf^^
z;hEu*-3mVUO^(F=(T%3;R`ANU8HuG~z9`?Ua7kvDaN7?#645|7J*As_?u5-c{=U!5
z2{UJxZ@-^%B+5pQ*d$-_Pi42fQ%L9$N3X%MOISU8)5U)@!0M8b2u~BKM?CjW`J(=}
zR{cW4=mcYWN;m)Xh(p43*_{_=&Ta)K{~C_0>14sb%opANqOM^Z2cvB=KU}g)xHBZ2
z7j92af0;1cSh-uq?pK!45G}iW(|-%c-^G94CV$!_>q5dWY?5e2vrAYwXU;_J^jd}a
z(#<`4aAnVo#N2RWc)-cT#aR+w5rXN3LO9VRSI$KAC)(*LecPp>k*Z@iH0YhN`*p~o
z5KFJ%_3}mAKboe7k6XSG{Rp)wdj3h>;hlTT*fmik(Jnn#FuLRDvfg~@n-+!nK22W<
zMt2-dYr}k5S8#k-!AT(=ZQ{$qCB1^1qL1)}mlM%#sp-rdMKV_n&!|#ob&ev5=;yGn
q4B;EYC0ZgQT%xRDf!))_!bK8!3ufjWkx{YKmT)iO$!PbKZvH=WH!-jP

delta 286971
zcmZ5|2UrwIv~G9L^mLp&m~&oTa}I0HdCfVmIjyVfx`qL>2nJ9=Oo)I9K`{Y>C@Ka}
zQ9%I}Q4~Z4K|xed-+u=8zWbiv($y#Z=Tvodb=9ew&3n@2($y~8s&z}~Yhv(^Z$Ve4
z9<z(t$*{QVjK41Uqx-J->-O`$JIWqE?|Y)`#W1Iu?`B&#pJhUR6n+2k|Nm)w6K7C?
z^Y0qR-S;de8fFZm<vM$YarGwG=vQ%W^}gNmoQGPcRmHsqcNZpIn90;!KB-c_iZd(r
z?N;F2%{r+(?lrhuK56+(u4elwY|Y{+rkd@iGBqzu74oZT%Jn2inx0GpHi7PpHH#-P
zHQP^SJcnyqw=L7JY~Ko#ocft+jG1KZ$JFqdWWhCck_p!ela08JnXIS#zg4>bTgKJr
zZ>b;Sc~j$J-*}P<5%N_H<deos@|l!6slsIVo%Bn;igW5Ac2;AZS_k(U-2E3j>NSVz
z#X*L8LB?q)cEmKPBIpW`X(21;kZCpTC$*o+)S!m4{nuneizl&E1AEQolQlIjOr{XZ
z_tgIsr$dZ}Kp>@3UCrX38oWb;iLTZ<s;6@l+Pe+cncABXxz5gKn2<&1nCS0W`;2((
z46CJwQQ?DDVJd&#BQyPOvy4it|Mkx<vAXun6h?b|m4?wYDEAv=5-ZlMDlrnrcl$@f
zXvd$C7){&qBT2#uTh5A%q~$*_5~J<4Q(!cM%Ku3ctq|9gV<eHk836@R7@8t56}9}V
z`HM-`P!bt!hpO;X&e{~}m3H8wEvPD+7;P<EKM=+M;{15)xm4H4E}QsAwa`74VSR=$
ze2O^+GKNjR#xs1XgV3_Cw}E)<AVhZL5)e-ugvw~|R1p~dsU{0H0Lqw0Ktl-V)lZ<P
zQ7pq}{sap91w__QAe#xqYx{plvECfRXKR`OK^FP<dkLxMkfscuUy1~x8N+`lMPjr?
zeI<tfs96TJ%GEUd7wG{9g8|*(y10s?4$6R`AW9sBRvAXbHwPiIzund_{C5XoSJ~wI
zpnf<g6W^!D5LDkm*!UhWVoQl~eAi(^7_OA4#9e5oFdDWBIjttT4$?AOHUsz0taxrO
z>cM^lagr6UK~2YMGz^o#R_QqaAqb@i3@2_)Vi=K~MzLx+@h&ta_8bV26GsHejLecm
z<-`<76o<sbiT@-DjOvisI57hfy+cxt6MI;A#^8`t;=~+CjO-%-RO7_5g`Vrhv39ff
zewi_|N6=!Ha--R`2#QB@jb%&QmuupxWyX~fT7GbsA<XzvLgcm;XqgG6gvw3ZqhltP
z5+=SU049|ZHpV>nw#-as8v)o-&%o*NN^rBI1jfXXhY6tSw~!dKgF=-jjg}cpDIs#o
zOC4h^B~-po_aTg}lrZswKsc2WHg0wV$CN20%5lz3Wu|N?QHl4wDAll=-@7YJd2TC3
zAok_(SR7UCU#f(AJkJ58gqAUX-YGHzxrR`(Y#heD=1Y}F{8Z+;{4O#he=2ha+6&C6
zQbOdrp@WYuB~&hOsl<#aCF~}y>ll_9TT0ouf$ufUxKg5=qsNTr%=CmSal?nR%!E=&
zHSR=xo|#xm)Z(beOybPfp;nK3R=_ZmOC?RXfTkK|N-5ET8#t0@rj`<IIO;po0Bwg+
z2X59w9rH)2s59p>hh?Uh65ToKNi#~Zdvh;BC1z%+WH6U`j$>w(62rJJ7(iy15~Dck
zV{=Nw9>=vPk(jxql1W?_gNB(`N=)OZ!_BvsV$bA^AuO|?RJ731=nG4U#oU5Q0`q67
z+CSWH!*tA|Qi(IiebF#~l@e<ibNw|uvzQx0&!$o#H(ZBjgJ)M%Drb1~iO;3?TE6R$
zA<P#CVQ27cFl2l!6{#SaF~y~X2}E<Iq?E968%AlEZ>2;z#ysJU!hGjGq6e60P}W8N
z1BaSb=pT$mdzi)7Te~_LZ*q)g5(JW{je5<NstR>ONcEhENHw-giv)(%EUnHloMzlQ
z4DyWjjpqW@$*yU7o3MgjDTHNI1x9G8xd2PKoY=6HfDy;#i@=DDRq7rL+oY4oh|L^?
zmJLXe7_p^;5ZPlyv~dtBd!2|54#LEaISYVJ4#LK0%eMj5hkHgYnn?Dhf#jp-34Cdq
zJ5(6f)r4<HD+i%vC$A6~sjY($*|LLpMk<9>*~GRoBbCCM*c*+tjMTN%hcdW-e@5z2
zhN3UWXmdvE7^x@M6_jj~`jwEsl;avk8US_bnCz}*@G<zO!wQKAW#~_blNO;-M>q(T
zJ-8U&M>`07uo~edl*VzP4p_O-5VWE)c-DMW%AvuqpH{GpTv{hBTduZ_kxT0&vT;8^
zl-3D@{1m{-Kii7Y<`0w@xg#e6&hf<M?tjzsS+kbI^@XINr&K3YVdP%i1PJ6NN|U-0
z>d-tzWR%he!?2zUw2V^vV6<%QSVZ<;3;JZTjPhR#zRcn6jPhR-#>dEv^0NsY!7Du+
zH7Uo&#bccB>mVwz!L@jN%^XBEcCaeptLh+Xv0dLIgy9aN9(%V8LKy2Her2?;+G`kP
z61V!lS}8N8B52L1%hdjwBZE*aP3JZuI%mRJe7-bu1xze7F2}W)z-U|V(lN?>t~o4>
zWac!vip)$>TwBYiw`MhBbE``C4C_`0ZnjjR2GO#cn?tg#$^&$?7VOY12-Ks>0!Ui2
zqlQAVqiP4(*xRu2si1aM9|)=gTemaxyd6Ymc0MaGijRZn&fbkgz4tnZ-fXptXvX~x
zqCYEE0)VfB7|cHM1L5cRN)KcGhrq_a3cWg`*fl=@9q1s&F*^FlRn=Cr_kml1E{tw5
zg41=xt@c<l?2d56aC8E-@m8=kos-bnG#MpS?TLyGt<~j*jMn<@3LDM9@|btPwm-+H
ztu+&2U?eNKlG>q-0+X;jO#C`Jo=9ouRJ*8-fmzF5-VITAhe%{+b>bPdw}VjGMMU&-
z5GL038$SC3tuzGL*tvqpsJ}Z1CpPht!l=U>L>boa8HkY%qAc62M8l|K97H+x&(E+K
z?;y%E+Tz&~V^=3>d=aJ7o0~jSPfb`yk<v3&?^mPy(r2nBR;4Ov9gk6cSQXP)rkbOv
z)#R!)8L7qSYNA24bIVDLnycv!Wx0~R(N{tn`a)*(|Gkud6l)p%e`8CHOxe!p|9drR
z4uI&tSA$+&eYc<W4x9|4r-QJu-@izVzK?^z;8J0#hSB%a?1Cf5lhQBgipjO+6+=&I
zWIWGQ)3kG!nOd6iH5jJ4CfbQ%YH0R_b4*Rm`&&HYYu9|)A~5Ng5o1KsZ_wyqZ6pY7
z)C+{O%|d<0I1~)0l1v@bUB9!1{$~s6y=u^XX$$FhSEtJ2QJ&%%{hk_aA*seT*MZnq
zohH?_*p6sn{ekMIK-6Kq^_ZX?tkKa9y?U&3E<}eMdcU$28VHO&z@gWOwe&-64_BRt
z0GhD9y<l{-MmN~BU<+J99Cr|H9PgU`M0I-CI<Vo%h&-hFK-m1o{)rWX{<MSW=y+oK
zbJgjIb!K$*?X>HBLFi~9pc{&(s-4=6WAryP(_mb-*8wflzzRPMkB19Jt=T%Jp{+Ok
zmoluT5dtHp3+~{QUOaHe=xX4br=t<s8eflN<hQ!h|D!-{A<&S@*cPr88N2>GN8ibt
zq(B!&NANahyg#b5L-dkFbYXN9itSrte0QE{$x3U0$Z>Ie9d-0=v5jhu4?~(mUX|o@
zVRZDFvtB=<VdQtZ_QZC?96;kAW6f_OGi-VN0OC75RexDeVGNJ0<fO*)?pVd?S=^#m
z<B#3D8j3Z&u)IS(9e=Eu)iAY+)3glhuxH{OdPUGP)T_=inKo(-Zu_({Wgw`8zZepY
zx558g4LuKT`y{4Jv!BAWQX#{<`zag8lpFX{1|x>a`N<!}Fy;GVdVd8%W*Gk1z2(JO
zJhPwZnGU-4sMaFGE_Os8>EO5^aKpU-j`_Px;2&rfZhLRT>@`|uX&Gui&Gs|)GPR&c
zQO+P$a=6^#P_zA{ohjG(r_do-@lz0ln$&rURUF%cUk?TP*8+d+-nw<XJ=>LQV6Vq$
z3>c{yZ5iCOQ`#$Sl|EMVBt4@M+g0b=^F-4yqcbu}buGyRo}og7ilJ1cdKKtkHYU|#
z6s4o0K|{$_R#6;y)g>0%iUaT`KH;e>+sDdQf=FK-c#Xj_v~VD@r9p7zJay%(wRXhi
z2&B4(+*%yKr3?qMwGrE?{C~06E#IL$xwCoZmn&;`va%Y(e_@!2Uq(Tvu;}Qv?EmAf
zQ+ci&CPt-VJikW&6H0Y`-STA9x!j8KNEw*f+6F7CSkW-NteG{HT~?N1D*miDdQ+u3
zj>f5sDETg>?Mcq6{H%UybE2uLqB&9JYEEojN5It^G5@<3eXJeetcGXj3KbgEtjsjE
zQUs%v(fmjl)oO%lm16(j(8x<|&r=mDXzDa#JnvK}gGXQ2Q42?-*DYTSmP~j2ari5J
zK^!-Z4ncR+59uHEQ2Iwbm;TXPL;vV4`|n?4+~Bk7AkjV1s~p!z%nk5wCS4_Fn1hIC
zJy%w&Si2iC6q+gqzRWp%{xy|N4w=T2lX%;wu{uUmQQ*t?dq!2PQ1x07$Ql-nWaZ`9
z3Ye9v8eV6Uk!cZae3|K<pDH%%xpfNW>Y7ev9VpsTEI+m!U!kcl^qO#`{GWm&#`2{!
zzs}TPHxezH!)yh<s!i)TztTMRl;@L5t+~KLPp8U_?RUmwCi&Btrdjy!CdL?^*-?h(
z5$n_FJ_*xBo@srV6snIw`haQsO~$qSSJLmFLppQu$1_I~>Dt$sq>cU{{@cSMu2Zfl
zxX!yu*UR(ide)E7?7w4<$}_@yVktZ5zE3wYkRK!G!2|>of4LjM<<~+chq=g;gCQMA
zy0HzpPxwXwrAN{A2|oEeGyEtaTns0x`e;uCS4bScS#-~wr295q$##^z44JK;PG(Wt
z9ra75s7t<(o5UxiI{Z7S)>=TE)Rm<9s6DmEyX(|KZW{@qIE^%e?~u;9cEnkX;ToUQ
zyW}znX(zN?4&kfyNqX@h-5+mir{eT<Qd+W)1o3Uj{h)pX*Rqftr#Mr+XKbP?lS7=p
ztC42RGSXT2h=MqEhot5R!r9c6IPX4^bbBAVmzGgWbUH)6&ZHCmj}cT2m+6un#qfHh
zYH_0LsDq^1z)=rrFv0!Poa%9B0M($!J%U@~PyCkI6iUG((hr?O{JCxv){LvfpZA({
zTI2J@GvR~i`u-hpRxP6Yd?TUFzQr+io@rN!BI@y;+&re-6jL*al-3}_hN+RGB^qFU
z#WPhl5~pAu)phnJ;-p_7&8tTUA#WH3u^WpE1ksnmx|T;Ay`zVv;WgozF^vcz4=+B?
zR0;rsotb}}9Ou?2xQmSl=(C<6B6kqK!(zH`JescM3W>x0OZQhCfwE-@?oS&zJ044+
zZ@x$OOYTvK?H$#a_LX#6P9XO+Oys5fCBn(^AWgdsnFzFjqodXEqPRBRq3h5{3T3?G
zMe_bi_miuT=FX>d-_nzGay`jS9Wyx&@g+FzT#^oMK_SjQL(<J5^wf*GkW2S$a(~$I
z_*R=qr;>dz0i}8pv1=+_|EWewReb1r2pJUg@L<we8BNl0wdua?90Fx#kaWC}uDWUD
zID88QacD9*%U((x?^<Lv-%6Y=7LwLjNw)9$(}Sy0;OPH<<PlMpr6#)nmf+SlBC}39
zGT1VmfJQzd{=_$=dB`zZ_&OYC=aP=cTH<G?lbgbpRPS?I;?$-*D&vzzE%(ulq^|V|
zd3+XG_0ePDkC#m%)wIo2GrxFp_5f=Io*5fY4Li7i?i=d}V&F33v~e{1#$>v`=NMj6
z@x|born^ZqcMRQ6%OmOfBjj>KN4mOW)`$nOg!paik(XJYu<+rTMZXg(z(Uu~6Di&@
zSQX;=d6U6IBk=<-ko%jCXPMoa>X-I`>XEye+H7bA;tU=~oMD^D{fs@t`6GZhy|$A3
zKupT<5+ZYeiiMN3M26JPWL_l)+XvBgQEyTTa|AIunp{@OB8WCy>AF76(Lx5&3EfYQ
zUz_Ouxs?Llc7r&+X>?!pIN2T)=-R4;+*eMZt7Sb&T^3S1okdCu{ofKx-JyGbQoT2l
z;%cyoKm%)#QWb~Nfz_mQ<}>lLIy-9cCrJbR>1w@0!Kqr(nfQnh{9n_3-W770Scj}8
zFQw{rxI=uV0qKhd@|b6LL=;(*lnx*{gHF_)#LIh7T|W*Zv*a1XU)+d{KO;+nW*<PD
zQ4{I96zgf8d9$1D=VA8)&v+DRe!5Jy+D;Ur#}~S<-i~VA%T5(|yOZ>@C)ugd4AseH
z>woD!XeGfdI!-_vIug**Rm3^#cwy?_r2CDB$=GEnS@o+;pf`fZL7i4~jZ{ddD1ff7
zd(yRH2%)uTOK5eTlluZIX=V@6QU9O!kpxMO_wu#llR9rW)v{tSnH`->O<FUb%-F`{
zc<L)MPTo)MLr)TCEmoW8P!UvDUu3|sh7Tjh<#!T4)`8=dMP52^RLR*$R%6hcEmQyR
zw}=d4Xd8x+93RbNj(C5pBjb;b@4_&ipm+a4L9~u1AeYf(b#w*+P38%7`Zx-A>7T?|
zKpR4g5B9QnrfzTIr-akBcNOAKcYIk=T!3R|9{fho*DurchC4aPjvxn_1L?lWUsS&o
zOf6yNO#Eh331XQGT|Z;ZgLfVCOC7VJ0y*<+?YOsS!Rfb1#P!|{7T4WD6xI_@4ek$w
z%DC3B2)NocgQ(tBc2i>}?I42{tqAm>V;ZvC(GR|7ap1pwO0_(MRW;A-!A6FTiTX&O
z8yy4f_#C=FhFK=h%+Zmiw~de=A(g9RCe5MB%qvfox%`drw;~CzW8CZ+WN`N_Iq+&r
zs?p;q#^wDe>V}QTO~P-aI@pU^$Rh`1J!5M_I=Q}d{cRFG2z?YeSm>DXy~ISGXPRRW
z(=kFVau$gkEyn*!bj>QD7W)2*LfO~fj-)kn0h2}@6W@nix*j02m`mjH4R)_|OmR!9
z@kvKN7;uQ714mQM_B;CgSma#r#-G4kAFnoF{^?BAz0P<{)cN|i+QCV;{C{viOyiG=
z4*%;jq$8HE!~MtuTVQD)Rfpd3(Mym^<i|9jt~hlS5(4~;+4PZFm`qQ2>A>&c+dpGL
z!LMOGI>Wmgd-5uZUF@oJV0y8y@(`pqn|u@0Zuasr6h3V9Ynbg}KaGLYeQaPJyzXcB
zw?a?{*p7ZM_hs$3d&2QSw#h@N`ms|cBGyA}0(~p|*?A(E0qn1nzzk$>Vr|SHW*^dL
z?+CkP5YUdYM_U5>7`vx8434u-D-d}QyXY0LPq2Mx)DC9DBVZoFS|h+b$);5Xb&AbG
z1M{J*Y<GwKX?B|g;Tg8uc3_`nt7E5-KgZ6c{m=7kKN_LKSiJ|(!r4ibjE!Ks#KQdr
zcG?k`N3#AwU`DZ{XneiMj@gf3qS;x+K)J*w(Li*W9gfsKAHy2=!u=I?Vi1aZY!%rK
z;e9p*{fU3T)}MgJPGs}Eft|!okAcNQwp=tKO<_fBweYEIK9UstW44IKwI^)T`Y4{W
z+7ED;!4}Z$>J>Y2GYqoWUGy<|&GxMX<~z3JAnbD3pl@KlXQOB)p2trAE@J%4XY0%c
z_XFD&c?bR@yW$o67O)2{qP~Ufot|KRV%rUeMG<>5AJk{I+%E|9E8DC9*u`vS0V-O;
z+Ac!&gB?T9*M&=<Y1C?t-;M}3bJe(?{j*MI8bn$w>;;qg6IW{Cf5FW2@U(F20J#10
z#RA+fYSRhJN$Soun*9p(#x0kif=!YS;M(*>EAX4`sRn1wgQ@TOvWKzKaj0v3>Y_L4
z-qwYp5L*L)V#8o?q^DYJsuE!J#0dzm-hGUTx;5<lZ*~BzWy3JW>o&4c7g4QEY)MTF
zL$2%x<huCH?CsikIrp<sG=V+9`o4fl5gXMVVSQtLVgR;|n~bef-jy5E2eI$ucF|;L
zH)q)b=mT7w8yX;l>p2s4(Ok0)u#4k-K4Zm6;TY{t7D7;AGA+QWmq99!Z~SZ>1ivlj
zp*eJDGl0wsU4W|_TSr0&f$Z$5K#XJ=XPDe!n}uTpDPYf1E|?JIF5>`bx`NMuuEF#K
zRP)zS_&n$uMy$YK(rDQ#>@GB>g9y4NA-`e%p=;XpImVr4Q}k%3=FeWB3N5ntqj6i#
z9tyZt#a9qV>pxE5X}0MWgKOIenwhlgeHZS#HCYd7-_v^#*pOWMNR01T3pz80_X5tJ
zo$EvT&wDfYE^PlTsN6=@eKD{-*}!6ec(H+Y1uA~*Ky1(9ja`cj30}OS5ePesbwnS|
zI>L`&9r0ga9TkXV9W{tzDQaB|OEuA5VW}pijWFUn8o}vd3a;f7p5t0^&@niyKIZ}=
zt-W9++OzKIN@z!WL+7C=n)crg%jT6ZqVsJ(?E~kx6LH{l%ASviy4T2pS)UYIBMszq
zsM=6B7o=jTy~|Fy4_W0dzv8~;`!;a$i?|ZkmN%QgZ71a#_<ico(sQUky>-s4fu_<f
zY!o&x`PFvz&{&Y(Y#w%3F>;n$kI;PBJo>Ktv45=q#vxWIgrPs%D+MhW%%+fG2wSrd
zeowOTMyQ0b^Ri$b&ib8zW(0en3%p)s_x}rnYwYqcXvVT?5UP^M-lI1;iLG=GZXdFC
zmBP$qYr4TAi)})cdClH4L-i9oI2QIrZ0ovk_?bPu5zO`6UlpObfxGn$4mWbyWx?FV
zb;oHI-ivFw3t-;djEztU<VN`e>@YX;FUXE?JCI%C&v9>-LFGJmWhtTv<8th@%!}m)
z*G7G>b3f>@-Q|u`0_G7nh!P%8xlZ)V(zpn+f5DwSi^k351bjvLw_K7Q&Gm_ExDb_b
z*2oKCw@y>W1OqqCl+Dm|*R;n+l=s$DNCWh4jR9F;-d|%_4$S~fm;QE?r!=o_!c(Yb
z&<ucH){Gtm`xs3HOxzuhxZ3HiFshmP24t<YhNyS#&C8I;C2`lIn9}gwTz0@$_nR~c
z==JX_TxX1Ae)h!*g=10wUwZrj&|l|2#<lUKhPXC+R2}yAmi;N2(Pkb#`+WOYWa9Xa
zBj2FCyR;jKfV-zIglc~l`+)qgr)$6;r^|q=X~#c9I(KUiTo=sy0E9)WQc;Hsy7-}}
zQKZg*a~6D*?w5WLUDY+AirvzE)<Je(*MB{HrRb&`0c4LCE>DH(N8wX@=(tFM-%;1?
zQu}UDJ!5Eh0n7^qp%|XGo4kGpwZqgo>}TH(X8rRK*kg7~BHTP>_f-Lv#+r8{lILt(
zIpDuwv-jgkXRzT%Q0(9uVh<H#WWWgkdU1Oz(3s)P%{h<4hZ{#{mG*Ems{(BwcjOa_
z{oJLifbr#wBS0PGdeAiX5Z9>>D(=s9-HIsBa_d4-oZ~jo`uZN{>xC%pa|v;9k;rAx
zLNtl<N`&1bE{-xy$((z8FjKiuPXXVb$6Pe^(5KwLEx=9VcHr0#pU#z;kA`^8J$MHy
zgR49bpf9=Jln%_~`h7)Zvbdw&z|7|Uo(;P<obzj-yyLz%g+UG%kDU&5$=$0UbJ4VY
zf?|!PDNd5{Yc<tIBl`84Ssyf*|8LM7q3QS$O?7&ck7`n<!~VYJUO1=+n%Od7k~FQK
z!{I}Xa1zX9%@kTdrf8~A&f&3UF)gN_Xv$1Nk*4|e512pGyuF3uh34=iG(v`EWFV+l
z8ZYdx@R^!n7XkKK)Ab=Jd$#5reR$t$4*m)3cbYHcK37xQ8`OJEWC>LBHGRqf=7Z)3
zW!4Hb?Pw)fsL9*`sz{Srh^l?o%%HErSB;boyJAfs)%TmGs|lLlHHNvUpo_L_BpQFU
zcECa~*J=MQfx&vaHi4$J8?{%HQPEA>dh=0>&Dyl%aOkFejMt3cqJ3Ecw5{52k72l7
zyJ;UZJ+!@7!u<~IYzs7ZYG-wZ%uD-E3l!ekO_WmDqy5+o)LyMK<>mHk=R8Cd2edY-
z%Rz0K=P>uv+Rvgh^8wn9TM<Q|);R*<AJP6!3B#k>_UmAATzjfBEP}KvTYw7I+N%I9
zL>u9OC{Agsbc9`~_IXDz&uDF_=mKZ8b(3KbrY)HU_u<;G<^a2(m4aX%sa;$LDi^g$
z6n3<>jr|mAcv<@jbALWYyZt6Cu4*SMh~k=d70t4)YlkL+c|+Uq8Z>Wdr&UDUaaxOl
z;<h%rGgR(qhn@vmg0|&vK)I*AyaT~J(B69pl|=25BvkOBc5DZrJkstc3xgDG1`X7y
z+FpK?e|n-_^b*BWt!Wcro@s|ODAKj=+n|%7t(5?nm)aZaP-JR<YX(`C_V-k{$kv`{
z0OlL*@+T;Aw5uDyQ?6FG08NsoeP=`i<!fEZ!$<AE-w=I)cH|StK55M!FeuXYUqbWG
zFWQMcp!!uCcN?H3+JW=XUf;A80-)o}htR^pg+H1J!!^7P8wdPa{*RgnZ9Q)tj<(#u
zPbmYxoA~Y$>|FWhv}kbSJ#jFAcjr^aBi^n2sweQUjnAVO&x0R108CGQ0?zl?`Ca__
zzHs5iFUf?%-Tc*yF!bRc^aS=^zIPp{?&D{A!Ttd6br}up%U5dy6+eFND%c(3e|bnf
zh(AJU$Uwf%X;4S`{J!vXjE^c0%^?2tVQ8M<OD-Y85dJJJYESa9MlkKC`M=)+`wXwr
z*YX_ikqp1*`L)mCH=N%$7gPklb0GXi^4UpHiQ=P{z&@IPup9Q5c<()6KH@icgG%N<
z9tQQ8f7uy+pYSt^5KJ21X&_|J_&3-_<)8C!{bBxsccra@mv;UVgScPu<+7oZ#b?w+
zFt7RGI7I5K^Sgq=MK`Mxm}_+7=OU)Hx~;TgU#~mX9tIn9hG~G=q<a<zPp-Nr{ebPR
zJ42bTExJ#Xd)lsBL0>fw-R3KBv{N@<g~2Xer8NlDTW9b07!9>sH|Y{|_UQC7VD{=d
zP(vl?_WTCwo-T15R1<aQGC?Kj9*%<Sk#0;o7$oajx`Im8ZHxxWW8D`Vj^Ur`PBj9R
zrt8-c@uusBi=dwCs!&cRLpRn5F}>7Pp?pN9Zk4?YK(lnur-RJaRSH3fZ*<-MgyB2g
z*-=o<(KWsSPkA~o`UdCgE}RBTfzEITc7?juXQ266S7{ES_@etWAF>i%b(%AN)3xac
z^B+22$`d&Y8w=rKwGj6JvNb}Rub_g31%-B$AwtEEaB)hA>;V^{LJJ?Doe^rEM+2V~
zbPWM|UZ|A<Dohw5!f%8S@GoF42+OL28717j3hJT|H59T-LMz$}xh#}j0Ol28`ADc-
z6`E2qJXYxO6wK>F0Ocxg3L|_e|9eYFr4cn=s7C3c+d^&1zuXl*Qr<p6$PYkh_l2O&
zpdJV}s3Rr`TbiSIC_GvR>|~*1HmDR~Ifur3Ebw0t{S#pyP3+QyU>tzvp9w9;A++a$
zQ*ZcvA@q3<f3JjpT`B*YDeMXcOtxUUPmM1$9D^c9&<y}HSLkemeZH_L3Q>FzTF|$(
zP*{})m`}psUQqcWj9deQufi4Tf!~Cy^!k4n+<PDjXYs{vsFI6V;0|hy_$Uj3t`#*w
z&|ELBh(=-GAeN~Ei%lYXAD&#rUQ{PH@!dZ#bQh<`qSz|dbA#$OaV`!s^B!VwFbq7!
z8<$Y*6gRF$OuNJ%k%%cq{Doe;D`K^-C}PFTzrnmNCR4WdmN<bjiE-k<>u_{iT=NN-
zckH5@42KD#Z4|io#Bbe!_CO3+h-Z)}{^1RnN8(C17$%E53!s@Q9-0E?W3lHpxK9)3
z`NQs+=ta9~FT}Y00L>8h5%w#wT{dKyqPh|0uf+;jRP)*53K|37iiH`d%RAA&CI}(s
ziWMo__g-{s0-b!(fKv|q2XXpq$O^=*?-72X7||2V&*Dl?YIQM}COyUCq6?r(#8&ly
z_CqY5jlx-aL7OV8r4g~9)<~^}0eYRZgc^UnwDJ~;jZ#%VRAQ4P*eRd9St=@o3pc55
z79!muE#3zEt<qmOs*9=UwsoL9q(%Dxvr}qE8IxU7_v`TMEkzvzwOhJItB}1?#|r@4
zC%yCr(^u+G(}jc5GFs>yk}@dC;4f83LfC;)R7W^EEDhUEXh)^ZnIMlzN%av$kR;M9
z?S%APk0L~B@CMA2(lmMxPD}3_1Llm>X&kW6NiE)?I4`Z5g~~jX5|0BVMe0g>E~(P}
zYcPKz{eBX~Q|Z$X_<bf>jsPrOYR`k2A#H3*`RA9?6q@U0O3wenFiSf6J3zCgM)Wm&
zBMs^VW{$M08B}tm+M%HGrD}^1#RqBq4frjPI?%2~p(O5ttVp{38i9V6{JW!O#nP7$
zcq)-rjfdawQr<aW{*Vrwg1L+QZ7a<`SIg7x1ADC;ZGdo{+>{3G4RU@AbT-O4fiQHH
zo1_7IvpgTC=6QEH(-|sT<U6#-xlL|Lv%Br`0%yoP<q%A2`5kh^IN0ryQ_Y~f<o^3%
z5Gs2Q2lKT2l7_3Z@{Bk%m;Ia^PT7+%xz0R95iXymSLT8|5_|G|q}&n-4F00rV+&xS
zWi!oRFUvW*;3-DlH5b%Xc|{o*T$2xVhURs77-ipY$n|m%(=GWvWnJRr--m#@BTuGP
z-d%Yp?FrwP?Q<b}V3!Zw0yjw>O#2}Z<)w|`DOvud0-iyNd>Y4}_{Z`l+P-@tw|W7U
zXY!Y7pwi`DCt&wNzD+CF4B4Ny7GKG`XeN^>+uosgE%&5d+idyK2B5r^FNA^lPIjWC
zXs*0rAe!X8Z1)-pw0wE$F$h1%mG&aG0y*F<JQd1Ak%Z<y%M&-C_#&6IMza;muI~X_
zBHyM7!go3B1q^=3dK;K7ik|i;S1W!_h~7tWrRB*Uh3x_JeM;SVP}#58;}MLna<(m^
zIH+{6hr<0KWf#pc{gq3!(G;jm)1f%5j0=a(QN^h?sAEbFEfa#2AX++|P);YnQ;1TP
z7H21wa9Y-eD%V7KI<1VSMd4Xx?Qc*yrxezJ-!SE`^QdpQaw`>&>4Gx#9*RiC<p8a}
zqm{NeE5=_^deS;BM%hdo8CR5BIPc2GDicnlWv(kmUr;xdykT&7OR3Ex?06+<I;h)9
z%zjXJ6?dAnBq*u)tnl|0i4FifP}bA4Pg2@!hxtQgH0>cID}&d7N>Mgd#r_BXSaF_*
zmVKgBrKMt;vVl^{&y=`RFnq3rJwx~}l=G8;{Zi5GMrf~;+jI^fOYxxY^;)@C9_DWp
z4=swfO6DmP-;~(H09&UTu{pwfsEIVi^i(goBc>f{PFuL&sph?K%s<ujpTYG~S9_rF
zRy*8;#cs86SvcII4j&F`ulmG-DE6uU;D9Q>U!6va-~(!J3dUE>Z3(-B>MylH`Kf&`
z!Bc>0ErCIxYAuHdkE(6yRKqc~?*K64)jO0<x~&>$c(vbA@6!u#SM5i`Y=T;+If{Gg
zs4pn)t4Eiic%b@`VWRrJEQ%y`_IVT!)z8aOJW}uAHv)XR+J|;lpR3Y4)c&Q~Hw49N
zHIH&-*=ix}TE9_0QO5GEdYn?a@6^zE6ghVF2c3!I@n5wfI>=Jv@Jra#Y?O)?u9XuB
zPVH+CP>DMGCL!Fqd_C~%ouK~mi?|JV^*d2|zkxuToxi@N#Z|*~bQGY`lnlhxI2U_5
ze3K*&`b`VE0HN8phrn#!je=;A-WB_Ae9PnAV9;vn71W@$oC^nSM(+ft?TcA}Yv+Ot
zE8o602e=MH)&cIfS(GL1^qKZuJMW~P*o8R?ovw>0jo<Couh8tiVi&^d*Sj0|qhfC2
ze#R!+fBeT92mICSll~~&*%S6kD1F#gWuSL}O&tnIe>MQ;v$41FwHR>0?8Jnh$zoTb
znJ3gX3-w1JIyYhGUAT4^Hqd-xi%^?Bep`ii+aTK}{6*=K?Lrw!nt2F(SA^s#XlaeG
zLkOWn!%m_4N-*uagbrn(>Lt|3LE$a5+6$+91f2z-dxeO`U>*?iXcp%yY)^s3LBW$6
z!B1FE>-YfS8I3D}!Ver)<_`<+gCRR2<PL)DsIa;fiemyl2~ivu)=h`sAfbFkV4e`>
zu_%J=!dcpS2@x*Qw!ul^uRp;(CFC%mLWQL9C{7FgwQzApD5sz}E7ZpscK)2OfaV(K
zg+`yj3=_K12P#|`PHTh+VbI?Q=7J!3BkV|FCXN<kmOSMWWEX|cUr|I0-VtEN2=>?X
zf?W}g*bwPeVGm8~uL<otgBdFf=m;0rg^zm?_YEQb1N`0;?i_?+oKUX=T*M2JrE}(C
z*U{>Cgos~Zepk4j47&s&NCnD0;YufH-WSf&$(SUeHeo&#rlbJ#kucXzhcc3dKRZA*
zMfhF~MXC^72da;ST-slMBJ9xt^r`TX+@}d&6CisgoLP=0O&1=uKronBV~+y!>N(pX
z%Mh~Df$~xap|!;;VKME-X9{Dg!EctZf>uGVh3@1wTexw7_TS$KcW6oXR!E`7e<!SL
z2VsuTtt_Zqp(q3H-wWfsQRE5FuK+Y(@S-gK2cZ&vjDytSn{o)WK<MlayFwxMDja?i
zexXxwMZ%C8Q28ooUZ5xzOqU`1E>!k`<`1EHz6Rs3v)I6~#upRmTeeO-PA)cxPj;f%
zD5i2ybrns2z<#s%Zyr?K#6ba&xr?U`q1Yl;qn6z&u1W;8O*}Ibfo>OdG-vh@{poAz
zDXvO~`3~_8EiZS9ZRdjW68j(vVduTYJI_Jx7FS$@r-R~}KT!CImv$o3L*n+1u<#fE
z#m)jBAl{?lFi;eX)YrvspP_O@47MPqqvBH<hmMIK8iILTj5&#zf<$*Z_IE<8M(3o0
z#h5>#5+bhDfq7Eg5`@BjO8mYME<(lnkuW?h{@npOXT*l{0eV)9r=`X@aq&~M<$19t
zWjMmb7ZR!#F6Q_n&<Jq}?E_p8JJHM|QoPm@=24=aW`-9<uVau!i@B6wyd?UZ0(Dum
z(l`_&j?M)16|6tjKzLPr`zxY}74OmF@4DCkKNI3_hyi~==cdTg!G>Gn5K4o`i97KV
z8$Mn<Ny)(5V)+y}ydw^#2=9sslfg_7?fFo-C+_bJPxr;;w9))Pd_)tbMDa~;U?z!W
zYoK^2+Pl+8@ko3@%YtO_Y9<U*#P3T`q>4H^^Y>W%WduN<h!gVAPEW<y*$5_09OsNc
zpNXBF;67bUpoP+NG4(u9UWi4tVV)swr?VL^#an+v^OfkULNim0r=uEK;w;L>y%ztq
zSB7e~_#y_;yb-sbho`q<ByAGB6T8yNAx8|S{7$YING<zbEcyWZJaHgRNAksYp)mL$
zb{h}oM=}2zLMsqIPKIWo_@+Ioy;^GRf(m*`1L;lkk;WIHN_!-hcF*=oWwNpVj}?p4
z1fcDgwwhsoKr;Bi-dEC52I`;`Gz$^>N#kgT?2t5rj(Pe^VYJ)}kU}S-2$XKkKyg^|
zoCfnF(l~k>k4kzP-j7LNHY2p-(q=j;6fB*kuS19wPn(%1rE(ka!w>$HR5T4bq0)ky
z@OxUiu@BT4X|o3$o|Q%p0?avS8toySm)L7yhDp1xf*CHoYzxf@$u}1fUXaGp%pp?Z
z>Ci!xv|$!vx+vA8LkiJSZTt|9za;f*hvKr-eIhhtr1QsV{&Ph--UAj_r4!MJ?V1!t
z-|ASYRWY!yOKrPA^@fxa4#S($3>i&wOL94jMvRj(Xta%&>U4+QZRzeYXx@>qRz*jY
zCQv3dL2?ZS$~|d9Ydp#OQiCyoejpiF0W48Uqzr{UNn&YF_M!BH4i!C;d>R5YSsFq|
zl2WAjS@4u972zyD|5)nMAIvAxuI;GPQ|S=R;?kt1H1l{S)w}`Cbjf=FsOQp*b%^Pu
zq*6xam9&C}jZEn&B_Xq<CRE+mQp9PXWZR`?wDNu<Euen+R%%7LkayC`3{W}JP}&K}
zm2UkC!}ro^I@FdYjs6aUeCcu&>hwW6vlPsa(gQjmR3HV>E?1$nkiMy(BwzfL1S`TJ
z)qwd~8rKfg7ipsfZTMB1Sr$<gOZF~*Kv*Ju>4-M@CUuO5{dXzf4A39auu*XDEC<uM
z0vGv!4?tJT1xLYLBY$}gm9_F++Ur>-@9+TVdb!<jplpy+eWAHgKH3${wMlM3YhG7*
z%v(6xEI*_U;U-s^37NZ`W#0maTjb;6u-GbZ*$4Y=@+{h}+Adc-2SX2e-5{uX%9c>5
z?2`2};mJ#0_%CGM@-)f-@0J^cq41Fx_C_#!<T6`<xmT`jg~NUFiESwM%X#$SJ0Np|
zP#0fWZ3gp$vTlJLq@O&{4=xVLn<@gvU!FzlhyZyO<?jOJzuLj?VY!G7J|B^5^#XNN
z<~$MMG5H-$>yOK|8zbx>c|mJXC*-!Y<_(s6&^s0)uWJjtlXBZLpiaqk>3CVFd>%iS
z#6q|%OY8qL@~NjF&&vM25aKzxa#z@&m$N8=9VQ>3#b3DGz7P>c$Zh9<c|krs1fY?!
zdmxxmvOXBhi}LCSXhzEy-a~dtenX45%d&kEFk|F#wA{NQx1n6|Rk;G~#a)wEqVje=
zR{nGpL0y;GA`~~|fqN0mO*!Z=s9SQEN^lV;UtIzhcjQ6T1MkY|nUE#OWv8N@?#cb=
z-MlYvY6r~+@>3f;CCayGW{@No(D~$ta_|;7d?X*ELm<iWupcl;kvDe%)1E4SeuVO|
z+{y;-6Zu9nz&w?=Qtl{C{yP}<&t&T-)FNGOGZQM$<)lrJy^uH4so4xU@E<hSOWBRK
zfM3b0!l0QcFD?K|mb|+UR9?%WXQ7fUkEj9J8@Y&bC~swDEWqB`<-`A?PC2r_9&zW&
z{icC>FQ-mLktZvAQNw&Wiq2SlkUM>Y{YQCO185e=&FMWVl(US0`6PF12KPmB4ca*R
zEdNc>f03W8K&yR~`;LV{vE241WF^Q+fcZ^sUItNom+jXn&-p{{*$YBv<p8;GQRdSj
z*40XFT2Zc1yl6tTR+)PqD(jR}lty2#xKN^hgEEnlrW=+0bS!9-5=9&SZc4owFmPA?
z8VqWSqAv%O?aBt4U3n-oXesBZ+@}otE@h=1KPBV6lyu58cq?t`iSAK~@ly_duTruf
z#XjZ6aumMGf=O_3P?@|D4*itZ_{9ewpj?du6{!6E5q5`_02BNkQ(jF&aa^f%2FxJk
z$vb#Bp}eCl;$S7=H6Bcea*37@CzX@o^!}Yv=FlSvRotc^($mUWU#Ol@0s;YZR?*Qe
z%Q@wD%J!UB)=-8&Olfcw2I0!RlPDsT)3+eIpwumdr$}Wo9b<}8TAc%RQEC1PVMi+s
z-a+M(@^CQP_p;(#9x5@)>VuU3zM{<Q55HHHR^_33O&K@=A;u~u8t1MnBO0S+ZYYCj
zyYHqlq%YjxQpPp~cAQd7BWk=-Oyl}(r9v{W?<lWmT6b3o_yn*7C1VL9e4xZpS~pSo
z)(u6Hl0Og750$lU_~9M@NEz1}Fv-eaw5gn;e47LNR3(NMG>;XxiU{V3(zG=kK2?J0
zQ<bJXqOH?siXRQZ>B=4IkI$8@IWTyk9Hc$V3?-0~pD&fS&0+US`9X`7OeM^h-U`Ks
zHbh=4Tj=DTJzIIV2NrLXd$i<zt1MF?e5drFA7kVwCnLekRm^)}_+A;C4rZRRX$}nX
zmEKRm{GfEEujxnS2Y%?x7bpWM6<VlNqO{T{#cwdoi<JEvA^WW8>mkA~O2s8G_^NcL
zn2PPn@99u2QN~dA@|%)HDWLC4r3z@MA4<*3pq$n7l$~->7c_;%YBl-`Wb4!w-@#n3
zR?dfu4Qd;DOdHiBb78Pay+YfQuIjiJfZnX`=><DCwNW3$>#jDVCHWRLo`=d-)&8am
zqS>ZqZiD;nYRqC_d#JGo0OP4v9}9~e>S;QavQw={d4OGNpB(u0QuosCo3}c<5&Z5}
zJzap}qh9F=<{tHw8RmP{J?UWXQ@7LXd%qe*-Rgkq<^d1B>LMBL52`op_;o(-r+%Ic
zokMCo<@Ej4>on;JP<_6E8K@4V$;V-})+cBlQJ2m|aa3(K1fGtm?KOz$xY~gx;X&&6
zBse^wj$H(lVD;`XsD!8&`hj^;4KV@bl-mAZV1}wUX;?q4wtG#p(lhEK%C??Yv#Wy&
zQ`gWAPPnRk0BD376N%!2>WyR-AE`E52AC+dJ?&CnR6S1sEm|#`0kli%k~wI@%W66$
zn_^T~+LpPZ9@`GtRW+tLJX}-%Jp_YTbwv{t*VWaHX#ICX{Vfv0o9bMeUfog$)JNQL
z>Udh!#jDwrYq_oV9trF_YIE8dzpHxDf-ylox*bv6Q=3>2+I{ud3=|L4N81r^qPhVG
z;*hHfMrsMUst3`KJyLJ^pn}P2(+=>LqV8Qv=dV-Mh&bpxRt^18q^Z>pA?|1DgAAyq
ztL#)18S2GZaQ{+0OpBIRYJVEpUaMn+!OT{N9D&^%^$UI6a@3K3BeYz#=|$MRSNqX^
z*$1`k?{N50ZE*&g1!@Ql28HT)8nx`7)Lj;kMQRPqhWW4RXxb+%R+Wi>DN#?*8Jcfu
z5C>1+)u`G~`JuMdA_`}H2O6_o^!qM?TCKO!yS+w#=mh+()%U0Y^L6_6t6{KSe~cy%
z8}uvN18k%Im&a(eP5Rw*qTSW5Pbh(Kv;Ouvz_{ttZi8~y52Xb57QJ&-*l*SQ4+GjZ
zeH%Xnx?Nw7lD!`Kfafsq)K6^&l^y!lQ&H^HhtrB}mwwD&K=IN?9tGvCKiwL|ZhiAS
z)ZRz$;s*0Qdgmah?A6<AR6)5<|NRKK`}Lz6BE$pwjR!#a>bvYi4G-$?&{EG&zhn)V
zhxF-`F!$FlrA?^-eQ{%82kH+{zW%UYPr02V`o$cmqxyApQ1Y1m3+3jH>nnE#Gf4k@
zFbq!Umo$YeSpUgB24#qT;!}Wz>bJds@U;GS8g$R-XAXqJ^ZHjGP|+}bYl<mc-{Cya
zBJ|0$n!KQI9|_G!eYYFHj?#~-1=&S?4DBIA>(5(YcS+xQ889#FdwqjJj6Sdd99_}>
zA;axe{nQtfqq(N%XjvAk&!!G_UH`2miW~YqCs5qfzoo71TY7g&PRHr}OJEqUpH>B)
zZtJ_!ck_-O`5L?x`hrmaOVEE00oXnLn0komzP<q+YI>l5P6?(&{q0kbCF$K(L-V1&
z$y%C!KGJKC047=gh}!b8{yuGAKheLWe)UxUn0DCG^aDjOpXob|hi1B-i$#&4@AwZw
zd#U$uWODT*uA>X&>Q^p9JH6NUB4(c6ojzmv`Zkmi`=FQTHz6PORq32cfqrU%7Vlr7
zzRO!Q;wOF2+Ned5{_J0f;<G-Kb~L`|k5L-ttG?G#P{sQ8w8$#aH(!L}oBlWY6~%Y`
z+;qr(=+i#Ky|ZBqje0JI87}a&+Q9cjFl!83D6hKKP?JWzb%w-wV6HbDABw`h!4OJm
z<c$VTIvlsjaOp9ka5WrV3Z|POpB7;5hD|L2y2a2d1+BN$P+>Y$wizl?7uaq{qC-X=
zhDWpu=4o)E--PWj)EtV?b{c9^24a_CBpqw@GK_5vhu(&+O@Ol7kh~B~AG@Ii{UBwJ
zp-L6N>@{qrmfdGqN|XQnhIw>U^nhW-B*g7&Fs?^)A2h7uLHQZ>m|%a%V5kTKf5Rb~
z-31t`_JKj5VPqGCebnGG9GJ%pvHL+CH~6L_rXa)MicmRW@W%flf)6&>qiK8%F{IGO
z(@8@$$EhYm?Qm2r)KIo2qBw16(FfES!(1)mK5JN>gDB1!ZqrQlykS)nn1>lyI;s?I
zm`EF55r!lCKwU8G)WC0~;mr}4M;QX?n|jgEi&A0HhUS|AcFB-sr<}!QgI7Dm7Gtnv
zL3qUwav9WB!>mBWbj>i;9rm$?4~L<7-B9B>s(r&SS_|1t!=a<7;VnZ(GZ@4fCQ?6+
zH@v2A<88y<n_%8C{Nf4ByM{+)5NLv-s(_g88EVqR@xEc`zm)%fU?`yWN;DL@f}3RM
zGYu{t8k$f_>X9LpG6~6sC_0vqYS?B+6pszp&I0X;!L2u<cxtfw!Y<7aNa^)w2Bry^
z>4qDW5`J#5^+&Z|82)OAU@{D+>GS#0a1!Ug`Bw)11c&!8%P_^UTVhyO0o-gu<L<C{
zV{rQdn74-BS5W(RhLK0W%rSJO6nL&7oetZ*H!S=GG36PC*9Dbtm_aS`!O)chRcOek
zkMSo%0u3TXhUj$2J{x+jN7!Esqv@={SHlRLd9(AyhRXdBcZp#~2RQs@s7dG6zZ;f}
zN9}(Yl*1^TjgNI;t}%wvj|bNpbu@uoXS{Y7p4J-&Xi#i0_HhTwM&s8#K-pycBL#M@
z#{H8}rOn30CaAa>d%XjSyU{><(p!upXu@jWZVdH-j)(EzaM*hqU()HZ9mWhgw7t_P
zRYtXU8IRos)62Lp2`b*k7sC<7ZsVTAD13}%X<*%B{6blgy~aB}@Vn2*u7<<?#;b4O
z@PP3wo$2s3{{9F29yCs+w(v7HqM7O;yD?xFJoy{XP;Ut^j{gXqK;z~5&^c^eb`XX~
zjMp~-?WnOvXJ{TXF84xl+~`gX6lC=43BM<dSMk4Y<AaT@se6SOy^Dcz(l~J&T%0mi
zqUBVm(U100P8(0rk6h0flWEX9YqVdYiQqZovYpU5Z@fkQBg|Oh4fo;3$zuT;VGQh#
z&@Pn5bkTU729s#xs}f*eGNw|Oziiw_M?qtZcA5@eG0trQl&i*C8vuRHScTFsvBu)^
z@NmP}WD3A;8eM-u6t|3n?KF7C8ULZP&GE+MAQ;{@-l0{_U1LCRPzgpqH#EXM<E%O`
zyl>2;UrjzRE?osriN-Izp!vu+J`8~-8)wmKBgHuXS1?nJo2tU#vGMCDXg)Fi(Fx7<
z)Od@|lBXH#wm|XB=)Q~2|E3$qjYp)<jYnuN?S*mEC0Jw_%~?QuX*A~m`<3y}p3uxR
zj->BFmT~TOV81rT(T-xa@oyTl-x$BqBYbPDO)39(#=(_fo@2c131+VGG<F&J_r`s>
zFvv5$rzCs6v3(wk_wSQY)FPT9<3LKDeKxjvgGj#^D^Ux5HEOE@t=MR!IY^0d2%W9^
zW*klFpYO)0EkXS-Rwn~z)9wQZ&Be5YHau3FT3v%|jcGXb<F%%TwEeNcbdi2zxX~m;
z!eEoB<}?=XpR1`ly)v6k5yc46%`}Uq6z-<>Ibd!vEgOqstEo&h8py-6q920sG+8Oj
zzQg2_g39bPJ=1`>%cSO^@G>2xlQ`ZcKiVhVZMsA+rH|?SePHe}`IFzhrv9%{>@$6&
zpE25fP02i94w~i(;QE=$2EpQxX;LOAe^awFC<09Pt#}53rXPQ!PKQlbDW7q~ROb*J
z9yL{>COu|qTLk8D(}E&YBG~jP1)3qI-VZ>XG;JIJl~bnH3t$jxl4;aBZ3@?*WzN`5
zp|tIC)--Vl0zPMY?g!QLrt!_86K0xz4snN@rmTl7!sM(+altg<C9oq+=lUb2Xp>6>
zs7t0^7tz3%O||I&LyT$h98gzG6GXVbYC5(Eey^E4Is-b^^yUO)*G)rcj(E#tXK7s&
zXL9iXcD$((y=u2jN3y`YV=5mE=3Ud1%dki=1q?=8+%rA?9e(ed^t2*>VA3Q&Gtu-<
z5tvD)DS>d2Y;qY3gA~)tM5v^iy3l^-W0Ow<m_ISyr+n>G(`K6ZrI`}!j(L^osvZ?h
zH#PnW!{??Q7WjQ(`b7&W!=(NNm`u|YdVjM_vtnWR+O+&C46;rBwIF+AIvxz{x2Dsy
zPx{WJ^@773lP~2+a!moXP|^1$Z#qMrXF5t}EAmZ=2B3T}<vgR$*+)~`*}yI^ji%{U
zk*O1<K|h=J&^qpm>C`}Y`fAdj0a~%Cp8#fwsmgUw-%MNRWB%PVj;26AOy`b(T5T>F
zkC@h&uhQ{=wdRL4AzNpzLF>QuX4joyZZOxSHNZymr)>KD*CunDX3%jpzoFlfZ#GYy
z0HK??#(gl|%~3i~+ssYcA^h#;3iR+i%rBA=g{OHdojKTHp3oP5cbd&~(s7qLnl|CR
z%ze&6#oH`if%$Ip8S1${W)GSP?J=KBhRS|(_3xB_IbeQC`*^<Q1C)O`Xdd$tLO*k2
zCLZh|^Ick%`J4OG$}7N(|2Zh$1G9k+Cmc3c(V%6Hm<v9jxsI9>D9s&Yei07l39~T+
z%wRJ^---}(%nm@GG?z<&$|>^@+F}niKc%II{j^!NBd9ax7QU$3dGn~v5Qdq*Qc@?}
z>^cH45$5_YV1L0}cni!(GfN56D06+<iMnX+N;A%A^H@69bICk>28zq(X#!MY%=@X;
zubKbq3zS%M7;QRTH}9uK-3@cSM(}sjZoany<t_6YHwfd*BWZIm-n_3eV!Le~+XoKs
zn8T`}PIt}yT7sEizC&5b2j=?Gpc2h9L*OFG{PiuG<e~Xm4N#BF|I|km$>vDvNGawV
zN?NCy^_v0q*xYe4RGyeU2E*W~*>2nnm^Aana&Yn7JjaM&UYM89hJA*)9IeA%npaSA
z<(0YG9oT1@?-^l`Wp<;X|Ft=qKC#(m%U3YpnLi9dljNB1(=smCe2^w-@6CP<pps{9
zM8BTNH><sX^1-}Yk5>C=Zg1ZPivsiSv{EfJf2A$&Pv&Z|a9CtsN;UjyzDJq#V)F+|
zs+O4VuY=(?vtcP@-_3LT0sDtJhjzf6EtTj4<YHM%8PC<0*Q;Q+#`5bBRB5fnRfTMw
zWeUw*Hd)+9z}(gHR-yUlW=q9FaNR8NDe&uV$yo^dEtY?&qT4MKC==je=|*W|Ps^{3
zpt8f_{Q*(zv@EBQZI|W1aWK6sSK0u~+cI%FG<RG4>ciZ}a&t8N?y=<2VrQ=<hF+X~
zmJjs*^Vn}`HJ<XH2Q1%^h~#}OCOWEk(9-G!K>aLZY2tdwVi(ZP{+4I=Km}NSp+tV5
zr3tNo4qG-}hQSewjgC+pwLHEByJMEiagZIi^q}l~kmacf%oCOY{a_btxle285KA1r
zsV6OsdkJ{|PFWgI&OOwEa~Jq7Senprz%!NtBO*O(>1TlbIm^nfusCm7mX11wS$uwl
zEZkDV3t>lC>a9byFIe<+elXJVl!r=`r7f+sE?Oqn2UxVF2QAJnSw_<i$7Rc*v2YY)
zap?*b`xQ&>31DBf%s7BrT(g9kz>T$Nh5-AzMQH`<hNasgVBfT4R)zg7OV?#Eh_f)a
zAd9#BMT5z0i%$URd&jb-FHr7UHm-q-1j{_yM7d}ALHWS@mW}m*^1xDM1Z0U8*DolN
z?3Oc>Mtx{G>;uC`me{i3CR?O^Fif#{g@a19^az6eW6Mn1Dt}@rPv7mQ7CoIJNV5$6
z3YBM;slK4nEparBd~T`J6Dlt(g->9YVHw>ADlaX^a)J5E;!zK>OiME|$g<dPw+H#g
z^5-b1zO~G2j+T9A8J2~Zax9zYpvbi}r2*r;Me2+q&(bOqF7hpIl!W?VsoWHG`e>=_
z1hfLnWeU5{@=G)vezF{+<}R}A-H!(PY`GTz>WjrN4t8HH8$1A3Y?)}MuXu@N82!I!
zzFBrJ2ljW%H5Pt<SnB1XzRuP$DjuGT)sxa?tF25I7_PB?rr(XOwQ{Rrx6bNK)4}!D
zKrLh&tci|Xu(ftNP&QdZX=HM>Zb*aqW@}hiMB!#VRUew}))9kf{<+1vn2xh-wWbt8
zb({4hwfc5zi&lu#!@6QA3Qz0BreN-{y3sUcr?pQE>~~rJAW$#s2O8eJt@GD{+HDP_
z9ZnzX4mx_i$6C+viw0|B8esNWr_+wmersY~pd7HC#QrN@JZonfXbxI4n!&=)+I$<R
zL)Pw8Uw`Xdnq>u8*DORk2U?#W1a;WDk$zor#M-_FV2)brcS3Q@>KzC3<JR@`rUqHt
z(azfm>rpy^6>P1(9$+C>?RUsdT6a+Up0chQO8@_%P-`4*zMi%wEkawIvGy(m_F3zz
z+9=LhtKEbBdFyxDm<_YKRt6Pr)$NCUgmri>Dtf^>^D3|-tvwW=L|MODVRzBG@dt`%
zYXqIQyku<|3xg|G*OxH3YJIR3p<T23(2U+5YduCw#p~9kbVlulRZAc9o7S*nFuY~W
z(gQorx^D&i##=j4ZuPb`cqOp!SU=Df{ax$oSWpSpDycBPXI)M|aJX;%N=xYn)^U{X
zO0+hk-j!tCMBD!ltsm$E|Hvv1gG#d9n%NRMDb^}9LrAr*V_^T-nnu4Bdt%L`59d?s
zU$o1WW}Ws90Y9_$=npF0dh2gEd~RJf2-FK}EG;22tbr8(_R^}M9LXyyN56W=v>L|%
zI?Fn;7BF91!-k_~+17b<viXhGzO^q5-&(8CS-*GIuXHvb$6De8D%YAti_!O1=?tRC
zv(BYG>wIevZEJt9&TkACAFWRG<CFsHW7>BtwBDrC+MlfJL%}SvZfyk3&(^7Qe)o&@
zE-l5sTI>D-m165+n$ee7Q|*BW|C{wxFX()?ZuNuTA6CSG7tgjN5rvCwmWU`;+oD>)
zevNIdH&oWzHlK&xI@`(lP+4!=y%j1OZ2d1G(2cg=g5iFX&DsK(uC~#1nrySJHvPWO
z&1P;2zwWlA(<rvsZXBSw&sLj>&IE0<*=QcP-Bu?8XdbrULD2EEP4Nb`!<O_7vYoaC
zb5QKEeV{|9UN)KL+upX}^P#!h*2EP}x!3mO0V3RI^Q{iqe%oXNWCv_(>ExuZ?OHWF
zgM+qp$HDZoz0ITV-yxey9m?NU@(-d2u=(qO9cbG<2!0RSvS=B3#J097{2sMU`v-={
zY^&*P|8biW?aTz(j#Pxo3EL=2GzHtb?t)5)Ek6?~Cv6Mqh|DS57s~mC+NRHhhtsz4
ztq|cETV+gi?fhAra2odKY?r9n&fDhG=0cdQfg6f&Ta$)Rjj)ZRJ%S6i6O^5gv^|ng
zMA<?NC@$I-JVOy}OQcQiOSS;Y&|bDx_yJEbwo?@l#TA=Bz5Z8i4ZlG1n(bd2pki$)
zv^!?MZc8f<iyO9n{&+w)ZBg_)^jo%`^dX6}mFz~H;%!UX!ToJpS~z5PY{#bp=B~|c
zHeeELm+4g5J)6274Rqhul;&y=Z0qUFRHAJNEl-kcOXJb_4{h>o$R61`(C=iEZTR&Y
z-aET(BrVrdZN3u`&12he`d#-E+jYuLKDB+MUY2GnI)Kog*)nNnpKjY>h5P3=B@40_
zwk6k4WZ3TeBhZ(&KPVUV%C?hsi!yDu&9KX|b&o-4uWb+L07<qjiT2jt*c#CM<gLwK
zsR*j?Y)kQDZ$8I1wh=6HZMnH{|K2uxHgxiA{9732+l;ik{lWHzy8I{G@b-`u*~WH;
z`Dfc8FHm1>Z6YE2YJ2hyn#Hz|T>vYwSt;4@&GuV;P~UAAEim|DtK0&CIy+6Xr=l`0
zPP-R?T<zpZlkhc8bv!|>b=pe{zjaQ{DL1p;Dasx88=UUuBAAU%?FXRRo1E6rX$x1U
zLYj(fcDj2NGB>9Qbg;tRsXYC^gtj;xO$W8r=?o3)+nn}M8fLqb2kqK;{2z|4J1)!W
zi&uuJnO48vz4u<)&}?YaQJH3Gsg-5rs<g~3%NJ#XfU-dl0cFV&WyoHlY!MXMBA_e<
z*|Pk7Pk)`yz4x5&Irs8D_qk`>2gV;U<c4}PKBZ8a4<kANntT}#$tCt<+@y!ZpYar>
zwF4OJjnEXxaQgzBL5#f=Bs|Gzpc7{>V-H2?LKweO%;6NHKM*qvWn66nIn9{uhOscl
zBHEe4871_LL@<JmW1eRiFBMb${aHpg)yPCL_*GzyV$7TaXf$IDovC9OgB)mzW$dF@
z&N)VPELh?gUK;=t&*-F6VFII}3nY=Tmj04Sj7fT8&ND(>U`#UOgE`Q9f$`=#bY5hn
zJ`K(kMh=B&QW@KDpt0JdF?JRJEu9f!2G1qNQmSjrU|jhIHf1t8O_0xG>{<$mY{r70
zA)mvDr3h~>BRB^Fd5jnxOv`7K?Z;RFV=-N_EMyFLqE*D$!vV@=#y9l(EM|mLQT7#v
z?U!J=%2*ZyOlt|_)hPT8N*Vqku%e9NPub6M#>-)ls9?;a@OmZV5xG@WjDXLf@EYS8
zI%-xkGTue!bw*z%SZWxH=ng|IqdN(UcY{$i3uCt!@AyDdJ!9)tOrnAD#(ao3GIlgz
ztcj834E4=cM(Wq-ZDF(+ps<y(j(%6S8CB%6wK1HijO`BN$wRQIosmW{p$^6%RcCcF
zTwjBxyNuH-Aa{>3pMH8>3{xYpyBS}-iLoBWL#l-8WlXz+rH>JI5pwq#zkCU>2aKKM
zjP^6Ei$h`l07F54^oNXm%9Rf?o*>V9i1Fo9KpSQpS__yF##s*JM;R`ukRM|dg~P&e
zhBM^>9x<}M0@?&)+5@dg#u*C6PBFNY>7Qog(XV=j@$27^d(4pCh6Y<^2oJ3zOrCW)
z=6jU+6+VS*W5-;|ghG3!jv@gL%ufrT*OA#g51O2qzBCJG=EWXhyD-I6Vdu)6MR^`K
z=3csha*SC<Ubj1waR8hi%;W~>^<?fm0+!><tVxg)%(Tk@^J4PpJ>t!@{gck0_|hmM
z5jMWefI#&6F`2Ev_GgY{L45#o&snqrnHy{|nIL9vJ6KLKm(htcm>KpmG=(thDNl2X
zxz-ITLYZer(K^k{PlI?EbAa50aORbB5Qt#DJ_D9BOb;$*eU>?Ygz^uO%rHGvL^121
z#4Mtj>~Po=!&K6i6wCBwgY_J9+e)<JnEf)a#4|Tib}WH;hR_n3mhT{t#9U7P{duNM
zK3I~OgLLoa0<$C*ofnzwCE!e9?zY7|Q<+I)U`b<c{*L^=4CWJbGRb5<NdfsR=I$m8
zW-~KsOUhxkE(FPC+R$Guk6B0u^nB(9^3MyH?vw;AWWKx>q==cxf)$sUUsC~dG4tvF
zqI}Gt8pvH`zD_aZ66TN)ty1Pzd#p?u(?qXNYdQ1SCNwLUpRET>C6k#A)+%N+MgFfb
z>wbl4)yy4-Fm|2UMiG}9rY+sssAWq3!q^RFCcIdio6L7=Ay>zo*9EX!%*Ag3yPm0`
zn*$BZ1<jaQBXg}g#+sOgnJ~1O8R!oUEmmfu9D=RP0J;r#n|bhStXCWJExIakhxz6Y
z(A&;LSO5<m^Km3dCo}gSu-s)@$?3nx9RD10UCfNF5a?#U^$S`(Oiywqdzr6L<zydo
z{(O-8ObL}BK48wJsBu4YIpv22nAYr3nDLPLZ5Jd4nQm;X&=8YL&fzc<*UItWF~=#B
zHOgGB!7Rp@4)h`!XX;*tF^`zr%b{?B>Cg=olT7VRsF-3pF@QbItfLs%4D*KousmkA
zP%zb&_3i<T9bswL0Ocsl);b9FcC0!!n)a;Jg&1^TRnY;%ktP2U5>Bi|+0f+7`mqk`
zU0C7YpykS1nhbm0Sj(s&;~2~38_2n{?ofc)gY_=?L!PXQHz07FwYL?}Cs-QF4|%bc
z(#g%6^$+=^KCHR-tx)gFVsxU{kM$3I2+*IU(L+T5D~Rep16glS_$Qc^9)?+juv%Y0
z>lEwN#SjQ(og09mr&+RWpoOuvB|to!)k#%h5iG?I(0hgzK-tf;tlxAXk*v*;K#5}g
z`3&TuS#m4oA7WU$$t8$oZF>Ro=U6j!P!Y$H%*X1*vs!)!NnkCe^l&2Uf0ckqVokjS
znDZ?24yZ_GJwr!|3oL^#?7hfZ?E;d*>dl2fD(jslh^Mi9DQBF{TK*@-F0r1Xs8t5*
zb-3bIn@m<IC2_J?EKmIHvswE@z|LVcKY>;*Yt9Ue$z%1<!8M=t?Rsb`V68s~D+*cd
zhap$Q+Dlv7W!Ccbn07I%?oH^u!rGUDv8ya8T^253ef$eOcq}#r>C0FL%V2gn>rxEl
ztQD-)5iqfmb<7FaRjeY4j9p_bejQd+vyAl3jq5C{1I({s-IGB@E$f++7`wr8u7<!(
z)^D_V)v-?af#nuUO4F`qWzr4C29}i^s76)<)fG0eCdwet%<4*pcnj;{S*UNdvi#md
z^ES(I7)G_RN+>sShxHwmN4B%-k|EK-T0+}aCyQH#vAe9UZ$R#`(#kQ`#d?a|gl^W4
zl#TCUeLo1fUe@zT!0cmXU54C!)?N!VJz(96!B{_Qz5`kVto?Ve77tn0F?xUoSsRzZ
z;33v5%B~HwW++%c!dgfP^ih_h4OEP=I3K{maaQ=3(EEtB;XMdUuyS94z$A-32R6;H
zq~D?Sm{mbhR9p5z0mu<{dn&|_vVWl}I6L--<onyRV`pK^ft_TfaG4|feH(x}u|N13
zz0T~llxA{af4K(|u57QXU~yxcMxgK*TTR#M+}S2JSUlKlicER3Wp6^oadrR|ex6|8
zrP!Gl+vRP{*PH!16}J1Z`>B-Hm)-O}1pL?w=3>_VZ2o3?{{^srqtinmJC$yh1hH*|
znD$Aw<ve(T*@MpkG=x1(bseYJe^QPhl%3KB&eLp%cOe(X{_YA;!r9~Gbw{upf}rUP
zd+$Dwv+Ng?V2NbUL_<7^ZLxqvv!AC*vl#Z9EINP2vIqCUsB`R(Y1@ipOYu)<Y~tB(
zk*}4&K1~s^M7C}oY)WFUp#t0U>@9ylQ!?A}G&(P^S36^!F0yA?U_}c1Q%8)Yvh&`;
zlBBUqDcYURKK3`jF0q@^K{D9CzYmhh&OS-`hb(plS(DA~zXypN_Rr)><g$OGqP9GC
z2&I|w*%!}2Qvv&@>#(qpUHmIl6tPF?*nOFuLgmoK>_drAe}$d=98j*ZhfP2!VK1wP
z`cn4yC(v2OexehK%Gt$X0IOi9&~&Yp>>)ZyRk06eg6A50^9i)7*}p!6!RzdWkFj1g
z><fQmtd_m%ECg?`Q$3;SCY$d7Qpf)F6Odc%U38kQXJ4atR0BKK4=9anOD)tlu?0~8
zYi1{GgiW{Ep7F4vjjg~x)v~!`W!D_WU_1M*DX8dRKXC_wo$NvitleenY4^IvUPCp6
zUF<pvXLhs0Y+zFl`>8gxdf9&8!KOa;^MN4u*~h5(?*V)6Qi%7nx3&X%fE_{C7#^})
ze9$?_zVZ_=huHNrvthRN&1|gR2)mMgJEQC_x-T-u-pzn9<Lv!(Gxia?t{r58EvLxV
zB)gYf>M8a=ejwBAJU1wuVeg|aXgp>=q8GI-=P-Tl{0L`11!|9SRC8d39cPBhu<beK
zCt!sG=N+nOcjWA}R$*#R9IpWMI&(^Q1Js2xo01x?oTsUX){WEmCqR#Jj#HA&ol~WQ
zCJzq#Pk?%I!k>kT<DBOYfSllrQY^}g^A1Htyg5J6=K_5=JX=8fa^zdl^5bN!28uuD
z$-BS|;FJl-{|n^&br2FkoY+o)p5*YU!Y-II?{DygaQew-I>q@o1vZ6pI;aZZG-ny*
zs>3)X`!E*H`Cu>fMsTDQ@;Ji@d<CtuoG8lVMsijj##%&iB$O41=Db0>Rt(4CcaT`l
z=XMnTJjV(64XkmTr*;B6o)fkbB!ROo2`Umftgm2x5~r4`vCnfp`3{}QoRl$uUf}Hh
z5%yl>h&{1}DV%j}08Qmwr4)S{=Sn@s(m9^hXkFr@wPP%U<9-Dslk@#UbY^j$!!1!O
zKGE|5z5`^F!+G=onsPaXRJ~BZIYV_-g`6UauN85U=@!&w&bCUh6muA!Fy;zp59PtH
za&pXIDdCjpVMQtD+cI#LaV8yLVL4|<7nZVu(?CJZN={S@1gbb$TyS3F9H3if)@n{3
zWk|1cKEDRNHJt1PAhnzY^oZZ!+;G9l+~llr14|u8RtW4{oY0jJtml+;LvI5ok_uHD
zIo<yqE;--Oe$mW%+=0#(P7V2JtsH4OIB#?QNdZ_J=lB-P{tjn8<)zxKoHrjqqJuL)
z2mDUXQgXTOa=4WDzsG5(uikfY3aPxRn=`ivq=!>PA>m#Qm%Q#i&Nep4eU6029&o;K
zL93s$FBf0~oS*YS9&%P}f~G+Za{|T;aq8(UI?Q=}8WxUltV^j7bCh#u83xBV<rOey
zobx5gKjJJlV4)^B4f`-Q$$43ZzsMA)!i-r=bN+b+tr^aZ7oqSmr;L06TdqBM-AB0p
z`x^pBxm&hlx$U?@^1AK0W;(YzaP@S_#*y3c5CTrz3sxP}J98a+V7?1iMwfhCx#|tj
z>&C^k0X%rzzU>%u=Qf>zLJ#i#YM^;?1uVcE=bnB8hMwTQ{~7dpaRau2#hZKnFvfhi
z15}FS%Qa9M&yV{Ao%;Q`A5t(VfE!~6fk5uMIaX*2;>zBD;7RVypV12De)kDT2=_U1
z%ujJ&rBp>I_e>~Sr@88nF&4(%MZusmTruTh&T{9_IX{v+bq1{{t|SO%M{{E-Qy;_i
z6T+BSZVa6h&T&KYF&4)?$%Rev-0{ui|0Qt0IfiB;xBD=7lDLWVZIkod;44s=%<Uyh
zFK}O^T+Bu8JW4~PaO-*ilgiz-3!Q1)M2c*sbH8r|xx_ts0wja`UL(LVxgOsGC5yX|
zaxvN56)ec*a5L9{<Z}0_ss1{TyRi;ylFyyU!9)wV>9mN2Tvtj}6mff~Qs6T84n;$Y
zxudaAe}$`D4;5Fr%dVhR!rc}O>{9N%r_n0o4*mtOa_&}oC@Z-Cmg28f$&HMKKo!@G
zE(~7d_R#mUs=2~Jj9IU9dxg+c!}a4pMJ<<2@!}g?4|)u5ayQ(7U>&!MzDaP4>-Aq&
zj{6gZgd4ceF9T`heoU@J6L+u?q?v1_b88EC6Q#FWxlLYJ*xTF&%2c#*-=ce3ceuJ?
z=xyhIL&b0%R_;!!{^{f%{2Y4ka^LR)xyNm$#9<eg6$<%ot~(WC^>D+eqPLgZ77P`A
z+&ntL-RJ&Bp7jInhk0P>=jx~;X@I+!(k2hNpV6yzkjwiQnufR&41f)Dm(eeNggg5M
zs2$~6#Z<I7##PlrVw}5h9a@jLo*sai;6CL6yC=E(DfBSKjdlXdH1{s$g=e@vwow0=
z`%)A-ZF$0T5IDknHy;X*@_H{og&ogv3v6=a{YlYGCtk=j#+-Rm9*}e4Mce_VD=*%9
z5NK|^Hz@vcjJJ0g1l@T}<bHbaHd8gXC(nh}`8dyOAq+mjd!++oUc8OuXM6Kj({t~`
zyB`FzeR*X@DD>l9cn&E3yvF<J4B#a>Lp+ezPS0%+uQ&(Boa8xt3Vp%6q(fHlgz$dI
z206w1ED|b0dFd37Kh1me1|-6G5z~+e=RLUv5)r&r6#hBGlT#JXS>8d~#3Fe=(C!h%
z)8s%PnpZ_dA~C$_Xc!aAd*KVPoa2>Kg-skUVHeDf=hcw!pTMiL()TA5c{izyCW-fX
z5hin<H$n&3WZoh2x-al155t&?yxHAQk-~dSQO#7ImLisEJROA`(|JEE0m~)cHTsce
z@V=yPC}r}hDH@u^`*{qV*}T9GfaUN)=?|03OQKYF9<Okm>d*3dD>guH0q=eeNFgtu
zGIvG17s>0s%#%F{v|=92#Dm96+X<Mfyd0_{E8)HOCRj>&d#FmIj5kJUh;rVCe*mR|
zH%gZ=DtTEVSXjk-#T5##@xCD^wwm|&Bd}cOZKFWCwTAbAYQt-J_^>V>Jf1DB^G#j?
zU5u{dDVJjG7H|9>TJ^ko^12&%`^n2`<Yj2kYT`|eK(3jWuf=>@cm;HEww0Gi-okC3
zxCX5@UJ^my;g#j0)y~UX39t@c@hDI_t-R+;AlSv@Pz14?x5yEshu1TN&R*UuIyUt2
zis|C}eclIj+4KRgnSy8iyf0>hWq@~ZBNpf(Z|4ta4f6g<hQJVSVJ%pOd7C!D!V%ua
zKByn%Ine#RF<vv>^B?EE90>J~c-CmjXHW26qoROGo{@51Q@lfTgqr3}27zaW*F}-7
z$2?~zpxN@RJs?N;rdrr^lt0%AbF$+Pybsgt`A<+*+<_lF4FN~~k8{!K#BbaT7H7U!
zDToVy>O<&r<)_no#Esu)b%fo=_#MlE=FUG+2MG^;?qak&`Qfx}9p@`3(Q<-+_YO?+
z;=53JqBsBZ8$k2n9}>YBU;evveD&l1k0Rmz{4_eJ2k<|qT`Q2^N^j91K97F#C;2{(
zFfEw><`+;K!auc@@_(oJ{VAAzDE|X;4o~xOQpJPE_o2{3IDgYCP!YlZlM=#b_`6jQ
zJj)NHrz(=KUI^?ceiH34(foZ>ITFJkqSClnzGpSmpW}Z<Z_zmZ9(zE?^OumHoWTFH
z2CYPX`s-AGmc*Y!@x=3dHSH<M{LN26?*;xx;~*FL%PHcL!p}VkO{x4>7|@i)Z>a=l
zI=^up<Sy|a*I;TH{8{@TkjX#9z+AHUkuN|loBt*yZFBe@G~ZnQ&^s8*<IkaOE}!3x
z+7_!#0lz^5gA4f?U!u2&|F#6SUFQ1^0j-$dO=ra`{8hKnS;}ADjLtH?0T-8S%K6WF
zqqBm4KnnGh{3<KNtN4d2(YnUJu?MrS=Fff;oY(nleIZxFugHf$EnnFMD{k<Ar^nZN
zlmE95RMhcbrHA?!|3$h;P|wezQ)L4`E*E2s{IYOJH1VGxN4J?@dj~37_%D9}6|MY!
z3a{VhA13d&jo-(|MDOqyOaiQ(|2CDcb?|?s!+$5=?tP5i<-fQa#@yp)(5$<x{B?Ak
z?B=%@L!yV@Nku@t{C5{XqL2R-4+h`o_fYut0sqstG1kvNPW$5k|71R39`d7}02$=Z
zL;z)oUn7NzVSe%R02|@2`4uWg`F>P=KE_}A6<Egk5zhha5noJS^qAmVv*?69$#<Is
z%oM+yer(hH=y#xZhQH({$YcIE)e_kXs^~)*M+9F*LExxh^EfQD6TC)YYJ0(pC!p6s
z@Ma-c90jW=W$h$Lr?i%{U^B(QTm%p4jOZ$`&p@Y};LT?NeN6DN)gDcE!87z~_Ym0p
z551m(b@X>SE>Oh5?h^tBTY!2An*Rau7VM{ByN_TAUAXWSgr0_aKf$Vei2Dn^Zb2(R
zu)iC|1PT)Suv|fcy&(`dDfrO?V8McSCeaEJlv63uDS@Wc3Ybtq&IXXvg5n8CgbDDE
z`taZhGUG9e2m#{)EIcF7&A|el6_kcyEK+cA3&x@Ztul~kK_<n{Vg#Xdvm{P1L=`LX
zf^JGrB?x2-pea#cPbtwPLBUfPJ1<Bq0cWzn>211ybU|?9A>=O#-g^qRr3f~9LNHbE
zB?T+e1W(d;($WPTG_^~D2`cZ%5WMmeSTY5FDlw-lLDgP>W(&eOK*<sCj({asu;K^E
z<q1~P5hh>oL@S^R1ZSywr%=%7j#iN%tcl_;mjz=~u3Id4k4h7+2ztrjtAY(}04))G
z(F;wbf*HEDTqdv_fQoWK$9V`;2)-_arb@wJ1wg9=*Qh@5njmc&>r^c;e*$t{(0dD=
zHG=W^Fs4>e_Y%krLD3b+-4yJnw~Dn+5co6n-V$u_fWmsg7xbcU5G<nDL8IVb`c7e!
zpldP4ngwUqfU`v~w-2OMAm0RXTM#-2Xl;TW=@7Uh=voL1+XXlNf<TAhuWzBSQ*huT
z*n3yNjKw7G3F^o(=o0kOhTLrx{6*o{9zkF_H1!I^O<?U4ynhVx_XV;knD{^tWJIf9
z&_>C<0l~FJXgw61NW`=U1xHpwU`Sx36vwb2;%l&s2wtKsX;k3u1x;guUug>+7ij2G
z;3EMd{dn*M7Y~ASQeZtsanLEjkwI87E%+`EvzQS)%7px5!B$Ff*a~ACK#mB7bYeX!
zd~qLavJ++mg2i6Am;7u8;YVUj+fjIc_IxK{=vokG;dB$gT!bkU9ds4OL_^$7xSC!B
z9>TJ_n1rYBfR(Ok9~Y`!0dqpwY=EGbFr3a#-ols2)ASK~J3+!%7)RF;{DfIQ0mfhW
zkbJZN;l=MU!$9GE4JH#LTtN=lNumFCfCUTJQ{p{D_zYdvJ|$dDvC&YW4~5W93s=!k
zE=<_Eh2k&a!t<Y?86k8}h2R<CZ>u12Rv1db>qucCoin0@#qAi27S6c<ff(WDPk<IH
z9HPDRoN(g~m>nm~I0lq>;S2pREkXDJ3-%@ouTwEwlJIFNH##q@$pvPz@Mn4qF9_E}
z)BEqDFxDN|DMB-CTd6|PI;c+*hAjqYx^QU=R9q6qQrT>V@GE)_GKCGz=*$wn8~_#B
zLJo!ga)ccpLsPEsVL!z4gkt*5<qMx*0J#F8%WaTCVciGlEE4`gC%4POM;6Ne6$`zx
zvCdb7*;LwdRk)8f<PxF80Vb9TBPqyOCfxA{TIIq$6wIv<M$$)rDurKD=B-ND)C9R}
z!ZB)93%?77_;q0v-E^uEUZFaLTH#`fA>R<bvj%cEg*#~1suPZX0T$~m;Q<P8)eGnM
zV7?8)b#ytmQJ7{6v?k$oDpY6|+J}RsMR=BK0$PQfRhaf|Vg3Z<+k|Nvn07~ajC|;J
z;i+bbcL?z@YCL#C_e8MV6}~`Wn0vyrE?Ai^;Z4%lEqwSaSbD6&tt#;J3d6Uew@<i<
z-s1O#+(y_vAhaf+^P$k@Nwfxq)wHrh!XIaVHY|Ld;x8k@h6sp{3hk(xZA|zl)t`+E
zpQC{3BjGc2#+(qE=x94B6m5XQDdE0ukZIwQzX5YbXkESw^s(^rd*HDZ?V!-#5z+RS
zFpHxi!D$dXk<$&p*ozKP9>GCmL&qaWQEfQ{oJ2Z$jGaX~3QW6*uC!vzRkWW%yKbTi
zijf=>wNtvsT{K1Rwui`-ZtQuAMD&w8E;3jVgR?my%A<p)muMLWn!H8HZvo9mWP2DA
zzM@##X#7N{>!8VB^d)6<14M5dF%~FF4#9kbMEO)deNyz;4u6<nk&vboB4Y7DPKiFD
zO*2#!L0j-?k;8Jd!bF95*Vu%M-bl3qJ3>@X=ZrI=PC8JX6~)twK2kJMf!Rli%E{x4
z7Okf_#fUzwf}ydZ;w`Z7oG6@po;Z<-K6e!_GU;Jqg6KE;K_rUSSuoKg5uaZ0=S2Zj
z?~^RrdK2V==wnJ$UKA~Tj^ZyVqJ0eLO%;utf_$2YOEKtlk=q(raY<BVgcTX0A1GL#
zDU$pNO<AJFRA`Vb(ovOuj%W`>k8(xR<kRMfSacfA7m2@vrUKC)bbYW;<ozS&StP<I
z%<<rfP6mUeSmgK46L|ivh^~JQo~xpHRG3jBT1S<LrK0!W2X>ig>n)6xi>xtdRfwMX
z4Js-{do6&e5?%ZR<hsb_5X`O-t(pggwIWY<tn3X@Mg-(;iqz!N)`@0zVeFQuR{+j>
zkuM*lLG%r|YSu=P2US@$i5C2qofCQAgQgbILyEh$ikMV*eOr`FrP^(xX)Unth(>6g
z+eJ&>!dQo>g0_ZE(TCf>a#vKD0=avlNqT>EiK;2)-Ywcjr=%WHXdsrkSG4K~#`;9V
zZ4kI`6`9+B_CT~g7}))yb4MXDAo^|_tavEeSOlIyk?)rn8xon{1sN9k(d%qPw1~_f
z6|MOkXk((t?Z6%v)r6z<NW}XG^PLd&uLAU>=tcSnz?8^C2Z3qP0!k>&i0mk=@K|Jh
zY7fwC#fySr;t}y*7eJ1RzuW{gJ8@Pn{v!5b@BL^wh^xPadPi~2^AK<n7i%%*EPmr4
zEOZesPXL;$_)-rvxrv|4!PqfzUM5=Z;#>5S_Yj|@${<hitM%wSF1~FKazgx}^+%w2
ziJvKjgtvG>E?Pd~+P|;}zT(OyFvd@8qFkH5m_b{3fOz^Xj0K9XIYB;1Y>z5Fo0H<`
zbr=g4w@~ybL|ktVO{c_eUxPDLoK5cXY4J1U!iR}nlK~bk-a?`12=Q-=DF1gxJdfVg
zXT=-}l0=H<v;jLxyyCxbia3!H9x-CR4M?oGGz!?~#J1#u#EI=T0xe!FrO70SSu3zk
ziQ?7!!IC7NPmbz&@!T2wMJ|d}SrAVVpQ8(osp1vQAZg;<XDR=XF82QcgO|i-=!we^
zm*2yBWs3Ltz?dxYon;`|;?_Qp9C5-r*qtlhm;&{A;?L+XoG<>EBD@9S2b6#-6u0m}
zio^yA0bCaA7Q%{R@vYY(a78>!VU(-l4_IiGi0zKj`Lk4fhEgkK;&uN3yIg#Tyypt>
zmaP!16t_{4NtJlM9Ib2OesVvn#YS>XuZuTRnNp4T6jf^1io+;wb3<J98r0tuzZeFA
zI`JRBWA?YiD_enCFJ4UV#s={Lx=PY0?xd&5+9bZ80NN}rQ2@I|?D7F7+A5Cq2ik4%
z5{h87iP^5ubVuCi0?>Bxw;b5iAy$@xbc*+W0J*#3(F(BK6EC4uYL|GDvM1f*kwLKZ
zh?i5?saKppg;agwDhh$$7yG^kum@K0Ycrtz;#ztf2gEz+Nq;C_#|Ie{|FsGR4~gg6
z1AAEfyBdNc;_hh(jEc(>F*YVPo`a@wad0}YABiPYw>BZJ4gr}IpQHHLl-Nr5mZrrb
zS76SFA1uLiABz*JfMP4LKIH?@Ba*c@fOb^Eq(iu!WG54X_L83{jOrlyEgi&Ba_D(X
z#z}IAF3CAdR*=u*B3U&7P*=%QN6~VVWG#Z+G0BflL!rCm+=l@3kVKFt;wgzOL+5dc
z(<!i=kg$G*dN0XrE4^F2B~Shcqx>W(_GtM_zNWo5K=P2PcmgH<wNMcxai=umNy*QN
zkPnu`n_zE<<o8#g_mpI#9Fqu@j8QW3v}EA}C=8S2Q64*75=K>f5t2S6n{CcWJjoS5
zD>1zSut>?L>*)Spl%#Jz(4r-6w!n^&43NhdD+%od%sGkmE08!z*!M6dUUHC1a}p#)
z(O85;$#yzdB}rad4V3ee652bHC7)0c>;=i_8pvIgbkeCkMe?&9FjFNNn<0=UVUTN?
zE}5E3=g&)$T{2*2NY+jOCR4KH31DYQ_E6j?TQY}&n>muX)R`-3-3P%u$<w_+%a<sJ
zK?)?>U&UCV<Qmll7fH4ZV``Tr@jcK~Eb00dtt*mZs*AcR$xno$5{a3@Kc$kiZz=y!
zCgIXqzFabwO0_E_NwoD>O4gi!F;$WeDV=al@&%pFswK8d!FgRW^D|g#Bu~*+SSx9u
z0R9chOV45KrsOAz4A)6=?J#yrvX{;Y^^$;#(AywMe-RoQC0weiY?5qz2A$Ss$#&ZO
zS|p}C47N&EQv~t0B*`9n+a&$JgWQo!wg9wUat{d;n+}N|J^r1N1_Kn{mAut~v3nB#
zUUYUzem)4&Ex9QHN{?idEllf`eEcP#`y@`=Va$EW&&3#fAbFK89`su!yI#O#1|&N&
z!1GYD{}=QQN?x-A%#h^MA*dgg{JI;H8IhczqsX}AB%L!JNoLoBOh`5h(K#vci-l=Z
zlIyf;(~<`cuxUn8NP)b^k_$ILY^DAbYCIyH42RrN>GGd|X(zSbq21PAx;GUH9i#^%
zVVk40fQn3<q`WcM<ShO2zei2VqQIxC)PoXuZqm&Pz#NkrS3uldx|=>O;UOK~1{P20
z-<Lp+OE=zy6(^)~eWA%q+F68odP~>Se(odf{ucUtr7NuhH2tK1rNTsiX-f`31ElA#
zU@%bn0i6tjq%Tr<{G_yfA6SB=-=D)+h;-9VkW<nsDgp|XPSZKzv^1NF+QOu_@xf-B
zaOvmIpcNslpx?|Hsm=qfv(kgKYeh;;g&<K<?RqQZqov;Tt=t%?3;hIQrAN!rIw!qJ
z8&#b2t3q_fOYPz@(FAEG9pV$Eg>+6xlKw$^=y~Z{N`fX!=f?x|g7jOuu60q`b{qDl
zNc$_$nJV4&4{S=4zQBffx-{c9pf5?8CaQnQkgnQ?!A$9n^$^UGrj24STiR>^$&uEL
zK_XZBl^Uy;C*4N{EcsIB)xa*0CftBch0=njU}2Fo=p)SKvh;f!5d81O*P-`{bX^`W
zuS)Ayf|N)n4uX_QAJ9d^GO6__egCCg+E3?{3h9mvfL2P6)8DB|`aA`wuSu<$K&zHE
zZUfqNY1>K&)<|=<!n9iHWjcu6kR~^S<)-u|!p1gr(qI0CO%2k`^!9F)e)|VFo238C
zL#tW3<N?N7q%0pyw^f?dik9`ZG>s<HCf)KC6yA|OLEBxsv?vl*bVx&A1W%{*d)oZ&
zN^R-EyC=0&!k8{;zy*MIOYMI^XOGnBBm{b;@#$ELKB+wiDEFlgK89%zq)%ut)-OG>
z3wj5nZ_;g(htlOth!0w&J9?pFNE${?|FAT{7lR|xkXdMrN`Jl!o5rMj$gv-ne*H22
z%#WnO%K$ndEu|Z%lhQbfjZR5@&qLv~bR}K<n~`SG+wigUkJC_LD`VV;-XpS>r!jU^
zb|Vg8cCy(8K(UuuN5z0~kj2t#)KS(k2;wBOqu`gbEHDoeF0$9@cDbv}i2_Y-vL|1F
zX~$%iPtkIhJxM=V57`<@D0|Axv!U>~EPo6tPRLkv%<+=>$6*rQveRM^A6YHM<9%h_
z|6t5d_NtWw34hriMwl2N+uZ=PK-qir7Y&k)(glQ*vW0Y?AXxU(EGP_-ah9TWN_O#G
zC=8X2R)XcU>@sZ|VX_~G(F&K%qFpOO_72tLoRPUlL+@GH-FGpUNLjcqSfXUQU09%K
z*@d6z`HPX|=`k29lhdwwPPTy332`zP+O6Yd%Wgwcf-Gt|T8Xl&BN$7PWmAyxyv%`)
zugS7FGVOwFb_V8hQTEf{5J-{DSE4gjmb4aDq{-HW!isd+!q=ealI*8Cw6bJNcF^~C
zvt<jIfXR{Z*TJY<*_Lz&=E>f=4w!sdWF<&}?DbtRtx)#wQP^7~8;gUc%QEM`fL1Jf
z<q}N0BC{w#uF78A1X3bX#6v}?>@_LG%Vg`TfmtrIr`n|onF|F+DrMgzI%u`2l5MHM
zoUX~X|M#5_S$;eWzAjtFfnbdcIRZRtGCiHSZpgA*pzx;bXWCfnWZCrEza^`6glYA%
zN=j`u$aZW2XQM2KZX7kq>RW))EZY``u@;%D0OGB(=e)skTW0(aEY>#Jk2Wy)j;w@s
zpLUsc0;EG0Jqi__vUkY8xGOUk!isycUaBYQlC7eXRJUv{?OHuDh7MEfl{M2ls!!IK
z1{L>ZD}D#&1KHw8=<S!SzK&@R$cnc^?x8H81sVorA}>G>S!M3DwG7LY6i*zHwPm3-
zDw}x(m@(NJdP|JUs$Rm_BiSW?v?gRbQUE$BOQeeWDcSGO0Bu_K=`^rsWO@qJK9;>Y
zg&Eq)lPNZOM4nj=^+)CV=)#koocj@4_VTs`u+TwnjgJ9!lyCm;a4Gkr2$i$^y+L%k
z$p5(v6|V9ZX-VAV2|FNoOg=_O3U_(eeGm`%EIn8}<?>e`cU*3R8)Y^p<bvNY<|WUn
zL(5yfjRO`Rc{d$HedURPST#TS{CUveFF$6bICFq}1AQ+wQ2rzBUP1E3bjms@_oAyT
zr{r--SoKi(uV)~5T7E!^u`qcWm6(RhzoCEQ8X;dVg4`Lo-9{|JS-JLEtYM^F<_DH2
zxoZYAM9W9kVk}0^wS}TsdB<h6&dG%}^!&xiKY9`-#>@G1tV@u)k^7n`*Yp7<NzNf}
z|Ga$uJAg@+YbpM6LH-H_A}-43QT8Q8{t-n0Q{^k@Eu1EwsRDMoyyh}YyCl!xLm)%`
zjttP5^5yiAlq`8Ol__P*XSLJ&FGqfsvVytt*D2VZCtpRmjePkm^12J;`yHUSP(DF<
zlOp*`Nf5j&j|m1#u{`2Cpk0wy{Rx(<@@4<UPvm3tJ1&(M(P^?wev(pV<?;nrAy6T|
zhZB)arQBWyxhlDR^%HphuF3x{fJC)?*cMh?m&ey&utu(Nf-$x7t7kF88}eP05xOaN
zc??Z;@~7!<e@i~~8fI88Z=+4OLB5V+vW@an)o3-z=aJXlELYMov_*cHN|syYeDb<)
z%b%ooa+|!K?6uyJZ`=uqcKPP#AkiVeya{?c<r7+vyYhRdp#GkG>NMoL<dtoZ=#~%O
zgZdu%?llnTmFuoytWVzaJh1P}myjFyKwj`EmaAW`EWsiS$hYICZ}U(t{R?DJUi27a
zLvsI2SU+r)Ke9l@h&)#fGAdtq6=-AfeN-MfF884y+aq~f7dj{8F<-)_NqGSSFjMk1
zbs*F7-zha|t9boys6V1mu7+tx6$hz8)lPAX3XAL&uMUILK~YD}sH39lb?9|c40S@l
zSz%pEj){xn00o6y6<&8>g_}ZE3-!kow`nr&in%8t;h|7aZo^YCM#rn;is?;|JE7Pb
z0!}Z*Hrk846>BNv=%ZLh<!io*$V`CwDPC9w6n{kz1?dA6v*%$fP%*FvGYe8|wY~+3
zlZrnmRuZgu`aEDl6nak#o>I6_QZQ5zv=p;Ht>BQ?9j2J1(`dLtLC;8p;wQ53jN+#^
zVAEN}|K0{?q@vUtm{E$z6=+2(Iw^}7qY$TKg0YI6pJCHEMaLzK#VI~%qxfgMVvtfg
z35x4#n3$+w(~>4B+`fR|c?J6hu#*)Ze~z&W3U@z{i;7?_tVmI4`H)LhY@^G4X^Kw_
z(3`IK@?&6MQq=qllnjOFBm^=QX_N)YQgC)ceYWDKMd-{?wC|w%x4DW-7XXu|*qMaE
ze8s*OfL)+4H9(?Jkr<0skzy8k-Io>Djzh3mafSAjD~dZu(7LJ^D#xFqL@{|5tx`qv
z2LLNm%o75vTwxE-(WXM-@+~?m73CCCs#0v$L*SZX_Zjm4suhX#;JL0ipaxHkqME$H
zTE#go&~7N+qJ!K`#RB>T*D3zE3}bF7O!FX6uQ*x@fd)m*WuP@G4(rg_q;R3PaI<3Z
zL)hD*xSEEsR>i40pxjY>K`w2(qJ$1D9g4*x5Vv+J@+ob4SMlL-u-;S5rIdM>;!9gt
z+N~&{+QlBlJ7tjXRScIvqE9i4O7iY2f^J~!f#L^>)buM}dKD}Kinl3>^HA~WC*T}Z
z%%;laA;tEWFr{I|8)lFZ#oK40Z&a})7G%t-5ZS}-aYZ9VwjL=w$(x)|e9{D%NyWx9
z;F(e^pwhZ&g(uwto>6pd1omS^SsFNPm93OFJffWA4D6%INvcY*Q(E3d%U)T}gMfpw
zjV@L?DpdktIw}3Bg5O!0e;Z>iO6v^m-LA^$IWXT%S$-Tm$CUP547w|)={4%148H*u
zPbGf|$Z;inU_5xrR?32SDf_&z2;Ry#CxH4W`8goI%FSv_$xj*o4>0|e?_!&^2~g(J
z2`W%ILT}L^r7dL>PAYd>$vF&G9-<R#i1O9zP<To?yak}4%B^1LJgvN|f=yw{QVNBI
zEAP=+AVTR&D|<#+MA7cE%HaiQMJflvU{jQGStK~4m8x-&7-f11G{h=L#sGaznfN3Y
zC{F1{@2GgC<+v4t3Cish;7U{;T8UPY@>C`4KCjIC8=%R`zcye_7nI?Yp}eSc{sqRQ
zC@0dulBz7CLtdIvco1Xh%4hcj<&tvuC<HQ;_@}FQ@RS?Li_B7bcA%B598Sboj?(>G
zn3k)2>%_Bo{_>PRJPDY5<)_O4Q>1()0Mov#eDOD^C{`{k0=c4e2#3T~WeXdeCCdHf
z04-Hsc@Jo1N?9ew%9SA^m{y^D{x~#MD*GtJQ>DyMLHwFB{x(*oTKPc(G+b8((a)+z
z`3Q$Qt4*!aiGuYvl<rSJ;-<3UAXL;TFVp?OTgtR)pw%mDOEA`;+)t6MM&$;IiZm(b
z(JiQErLO{GEy{D0&TCaJIgGK}%0&7Bw<+h{2J{_e#Z4@1yYj1T=<HAqe2UIa<q9^$
zt#_3x_kiA0?xa&?mom8;q+5Bb4x~r<5_#Rd%6oJ?>QfrOMdy9xb&5JaP)@%L)B2Tr
z<AFAye2Px050wY{&>B=0(#3}%C5K8*hLtY_!NL*c%4+}{RqnimNsK9_^f|F{t8#TK
z=p&^gZI=_u-{{;ssT8<DVoKSw2%4sqvsVCgMtSrtv>q$pr5aCL)jBh<kEqI;(K@R7
zl%793)z_5jvsY!%>%>8|p1f{Hm6FO1oK#~6@JDl2rP1{X7nRp)sC89Y|Djq-H<gsU
z?qjNhTY%=S+V&yPJXAl^(b!Y<ARp?FtL~EzaYCh`5Q3NLE`nz^-m1+V0QFI|(@Vlv
z^*+4~{ZzLo4ezg-q+ddS>Ucf=B7v%iJYWW?Ufu+OlPV@1{)1I(t#th`M1>t351#4`
z7m!d@b`vz6R-K`%U|}j_7SxBU4pYu7LiLgd#v)Z8?FUSh>Sg-2MYL)|GO%M*YwDpl
zRuwA5B+jX(kANjkwTn(N@v3-w?<S}wLm-f-((i*nlFBBM(yixJ+sTJdR@E0^Y8O;}
zREd94H9<$*6jd3$>QYs8Zh%Qs{cs**>8g1Y7QCbiwFhX1O1>XsnW`<c`DLj-rPOA&
zDu!MJIjWm<*2`7RP>du`Wj`D0^Hqhvf)uDmhpGOvQ1wF~(27)&%dq0I>I*9PE>?BX
zZJ8^o@tYXCs#@y=O(m)r3D8Pa9Y>(BOcg{YuyWPrQV3M2{w+bPQq@66#VQq(BD>dA
zeYBL-s`qL!-|MO}5~xwNQ#!j=^)QzFzZ<IRe%N+Xb<_rfb*j}VF#ne7us<eRuX277
zni^EHUoqCG>feO1Ce@Sls5GnImI0<k<xV9ht*X&}sJN{<-w%N{)n+OjyQ6xw1t{&R
z4sWn@sQ&&Prgf_JlDBYI#d#It)_bZ*7A);jou=x&Zq)|*h)0iVZ#Pu*sygQbtxxsq
zZy39;N}#v@16A$@7}Kx%yAWdosyCKH#Y0u#ZjeFM3KhtZDxA)k!>aHOpp2-z=7Ef=
zO!UNzsS@Z7JFY7E4q%V0s*rlXOsG=)VcVq2Aq(<Ts?RBpKCNnxho%`-(i<R;RbMdC
zX{#>!7_B4fb+aIFR6U#aWjpmEDz3Iyd%gzZpq_}sn6uia4Vqlk9h3)mRbLdN(@pLD
z6UZ@j%N)$pU2SD7LeoRNmC9f|)gRHX`?y-7fQl1p{|xYWsXI@j<*mM$hcO?uX%4LL
zRW~>S)K8uBJM8sWKf4uU0qV}bArPqE_A)wy)URg&^Q8Ley&%Erm#6|OM1AcHz)q<L
z=i`SIs-9z|Nb70!LGmcV)GMa|8m{)*3W*4{^UG+RQ9nW1?XzmXC!jY{z1#roDD~`S
zkZAR-Qh>&&mrx0Cta{TF<j$$%$T^EshXlf=c(vm>Xh=}c%Rnnpz4R7ZN$LZ(06VXK
zdWihLWVJ95%XUG{r<%u$>J6dzi=?QhDAt&&etRWaY3iPHkWW|NrgYvV_1Bcx%}`gc
z(8^Rljf0#`mikp^w6fKw$-T)@@1povu6meW^m*!}aj@j8yO`)KP~T62c%eEqh3?-L
zsrOM_;<7qNh{+VI{m8|<q8_9W>s9p&J&-R^m-+*{R9*K7q)Z+4B_>*~Ui|^aD%4SO
z2vn+vQz2fZ77anuHT6{rWmT&`jlw!zS5LnV4K?b=RF_z*KJ*acH`F`vQncFKRPTNb
zn(EX`${=`4J=Yl$_3H0tK~saem5t6uHTyi!n$-WJS8TKT=XGecsPoT(w5nhG8sxUx
zLkYPybrT&4?x>5mU=iBY>~wT?sE>SyR;OBc8tU(=V<-r9Pu)X5Bx{e__yc%))n5mL
zr%yc*2EF&y-rZ<DP&YP%r(a#!2EhS!gAv#d)n8JkaZue#>7F6A$5Dt6s~e~Sazt&j
z6s=M94|JViOub|w7HC|3a1K`HkveNBrahrPM(3hQwVdu^O<C1H(H)6twYv}!GioLI
z(vQ`_RC8>r*+p@IBbq%D2p-jpnb5M+@TlIvUZW>p+Cfu&2*x;S(&${|q*+9X2WQQ>
z&w%NosZ0lP)!dL^%uQoH0_%@y=0A&>xog%w!kCA~x~?Cy@YF0=1Qo|Mr-FcXLbGHy
zB)l|>Dev#C310<GKAK0AdiK?9jDozMCg@qn`)m9uw-}(=^%w$yn!od5VUQ+=u1}oQ
z+`JF*U`+}g6+<*Bb!eT^eEbetp_<w!fpS{&zLmDEFio#NtO(cqI}H^P8rvkmoY7Pt
z!IGZUbo~z!k(%GaF&3rSU4vG%=C#++iqS~v9#E`C9S8AqnoR?kVVtJW1|(kd7sY)N
zG|$ozHBl2m_aBlp3A-?MUbCzn(8-$Dd&&R1ph=@|JzUh(k=-epF)CC@)s$|BM4E>C
z4zSZTJ8ywp(%hH>feg(9N=9aCUf@C?OB3FQ#mm+V(v7_w%_hqI=4w`c0F*q<5;}9`
zYvQTezCiQsCZH5*9L<0((!|}R{QG6ipU1I?#hRDNJ-VXF^#bcv&G&a9U!t)dMyp&S
zZAGg>vzVTWO3hxn092)kvVdIE9CU+<YE85REY~%P0}!au1bG9qR+B_7#0||~S7G)|
z&F(p1sndw)^n6PbBc}U*^_p9c0Mno;j6iRrW`siMO`26>0BzRzt;N(@G;8Vpd#mQ(
z`5?D7cWPj0o92~`Sl~Mv^Pd21*X$xcszbA&9CDqSf639kt8rKj=zE&p)qw8OETGRh
zbZdsDAlIXLbRWdpt65JU3h2|Uj=<FJYjVjqeV|!Lg?jy(s&$Yb(9EaM!$Zv>3Kk4%
zs;P8jNVAD{tznG^T^1eD9HgJusAkdYkQ>u{ycI0t8U@v~J<`nm7n&wCi-=`X^Nkl+
zrZg>7$2@J-%%$4J8O`1eSg*$#;rBqZ)n-yq=ZN+)MG22;mE<wnX&3H>h4$J<moPO4
z?Xz^~anz1xf;ed#4#8|^?ZGr)yJ$V=wcx5Pr|gNF_SONkj%ly`3vqWXgWky=T8F1V
zJhj%(Dj<JcD?J8HC$v^7RPfRkk*Ddcy-Jhu(fWjf)mJ-0H<kRfF$GZXuXUy4WPtXI
zZ6JZ#SI=WCNZUiltCQNYT8Ia0J2zk~M60JX!YOSW)pmwz%~Fh=)^5LtR+v_8eHtpl
zwKKG9Mrb|g10iR$3BQ7z)oyo$X_49==w%$G^`sMav~~kM95LEDdNs#ta{?fKPJ8G!
zS{Jn6E{DKH?Ku}rG)2p5g{Di|WJ*e8XfNLdXQnpuSFq%2pQ0E?o_6VXbV|$DmL7(R
zGVR4M=&jHm{2n}&+D6JMRB5B=*L_X<2K{}iwU--#eO>GG4Fqbm?~^ZGt2J(d`WxCq
z6j7_wW~>9}E$zQ_1-o9`NS<+n)@ulujoLZ)f!U<}wHBN$T9Y50KU=k8D!09@{VWty
zYt#Nj_i^rM%P1Dyp-rdvZl^YuVw88aXWW2xPwOs)K$mur9YDLa`x2nOM=PMRpFZsX
z9is1R&;J())H(!VtY7;o)pHDJpS}vSA8I2KAwH;ez**XAGo-!qJ79*jX_qiKqGd;*
zHL6WI3bZlpzE@!BxHeG?n;vN$=%75Iy}BH&DeW=3K`^a7O$pW+Evp-xkF{ZRt<F{#
zCIQM3-E0a(*y(zUVYa<)E4j1|x?d>v=BRsrKZw;y_rg7Zy6B#xD>SY;EyWDobhGKR
z8^?5-G7xv&XDcA@q1!>nc2C_H1$9p7{+xg&FWm=u(B!R4*$QkQT|X6W`s#Mw0rAsW
z*TAMgUH9|Q6r_8&7si~_tukU}!MbODz*vY?mrG@ar*v_2CJ56xQ!X@I=V}H|gf4{g
zCXqV%JXjH>n=oT6TK9<u$T{7fD^M7xTeAb|<8`KDh$rcOr#i~>y2IpECF?Fy&@4q4
zN^$K}9d8sYX*w|rtqh&A6404C>yqzaRF>|F6==D-wlwI?)3M)&`T07@Bwz}3(GgHs
zsGHx2u_7H)4!f`DlvELTRo9h_R*7!cf3Y`RFy#o!bV2(dUaoVU4`ZryKQX{^P4^GQ
zA**#eDG_#E_q!D8YjlsTlxnEe9ig~wo$g=@<ZtO-qaSO%uJ0mLH0i!#1FczCPvz7t
zI(-saZMxYU7;{G#L&1V}-2%$gcj)}HprTW^XB#GZS64#s)CW363_AOD(K%ol&@HCW
z!$Vya)v^xin9tMmH>8V`qB*QPPRGI#-8yo8Ms)`^0A@^A8U~he-OF!7?;~Bv>tLDC
z{T&W_Cv^jq_MFlkprG}%F867un9)st4Dwj#LawE)KK@rM>=C^u-6J@vx1-aBoxYAL
zRPFVChw1$3pzpki$vEm)Qi{?^KmR=D<g6Dyf?gMW)K?gD)pKGodpA9o9PDHIw>qHS
zUH^k8us!rPq{34_`6oKP^zqRU_tsk}9p|H8pNF~l>Q7QU!B5{yH5>l=Z2FdWfL?(x
zm(?avZ=z6mkp8XLpgu%DS^!H=>2+^{gz6vD5$d%5>NwUSOy5A?MF`i|U4Ru4`fAF)
zoY4m_1j|`{6Fno5`j6(LGfJ=B0P$%3HwyqAqko1@Lb3X1&I09}-k)Bk@p>f#0@eim
zcnD~se*Yy%B<Yvb0Q<Z?G#Na}`d$j7rszZd08Fa>Ng-Nk`ekPTldfOOfTm0OE^_)a
z^tUNdlBvH<pWVpPe?)7Tt$+0_)-Xr^5B)B3^^X}q$<sUWv0VB3S#%^Xu<H5rP#5ZF
zLP0L;cTx)Ksy<{EKuh%QR5e(tpYjE0nSN;mB+B*kGSRBgUyX-ArM{Tn_f`5;pJD8p
z{{C{1YW+*MK(6bRR0vX||C)U0TK%X2<c7Y_738K~x)rNdueW}45!N*51L<tssGp%A
zWs_dg4;9V&<aQW*TkqG4R+~PX-n4i0;XV*(*H52<e1~2-0QH^vbV|zK)$h0r&U^X?
z<c@Xe{m75%)-R_BZI8b10hYN}zj78d^y&9Cg5|#6(@Oj61O39+(ECtdECu$key$f-
zNA!y*06D5ZR*11N{r+-DjO#!87luC4uX+cXCiE5CF*d0mq@8$5pK}_W)A}8oAwHwm
zSEBQ=-kFYNM-8eULF^34p3rA+I6?&#4u-N{t>AGqX!c;DPKLu2CU-Wh^9QJlVSfN-
z=xVq{yO*2cS1mw~8BVW3%iXZP5c0<juJqzNVekxtoR>jJr5oOcn!O-ChSrn7^flyC
za3sKRWC8RB8j4zAeURboS3o&wSU*GWzhJ|l6M91ohYv!<X@eJq9>NSe{(u$XhQ{kq
z5n;%t+h%7B{bgvKHI#V)G}4ex6=zX~-xfh2+7R&p1Y!(%rvVmgm_;Fva|R9Ff4E>+
zL?yr%4R#c5PB9#%czmki9ehRt-ybx19tB#uAte;6cgZkZ1i=i$3HoGirokeE-C2f(
z>p`*&`#uH9F?>jefLy~h547?Oab4idH*BO|LV>}C?h6+hUX%f>$nZYhf4FS$aYkpc
z!Ae{I6~puEAb!<Qvl@!5C59L25id2gk;7VMkbDA|azpx$V68A5=!IaV!RH4|t;(?H
z7l2+fRQO@6+Ax_7a@|ls8)J>Z?l$CV4U2;@`x}NAS(xZeLlG4()EWF_fWBq8xfq7l
z8xChfeS<+y&wHcQ@FE5Bn+)Oq18Fuq_#T2S1}^QBt%js&sK0FxQJ|^Ku-X}#?ihUO
z`c%8&`A^X5F!a-pw9{~mQb>0Vt?^KJ&#-S2q|0z?5XN*HSfyz77&hF2T(6<k3#8AG
z{R;%{8?5uls0W4}3N-r-1yrvvVCeG$&qKq^I_MoVJXa4gWGJ9G^ROXQ27wWS&p0|q
z4L$S%88Zxg27z(Ifn<<J22Bk(Ck(Txe0$n(mX7-~1{K}ydu*6PuGUfG=C{FOXME+q
z+r0M1mj}>vFj_jn<7n)m&Ckhb|0~d(jpr$g;$pn;3?}Mow5$cEo6(jDmSe_Nx*g|k
zTt$X@7<ZBb=4te$BkpnI%andRVXSM%n3vI|3G3@^e1-NRALDh(T>Bf#FVjmZz&PI-
zMg<zTF(DCTe3%H<lSbz#s0cPT()EiF<FB*PdCGWdGgv~6cTb@6v~eW`zru_!E(2P)
z@#Y?kMHro4h81Uw&r&kutT97}u}I^4bl{CLzNrRgtdSE8&U3~!SycZLXY8e)LcB5I
zDlAPfI*ouQ(HQ<JW|3rE_bgb?8(;ef>XVHf<jGtx=8#8m(b!o9vr~+xzD6t6Xr+rZ
zX~sXEhWd2l)=`*t$+(fODr6YHq=n5iezy>uS;pH`keF?(d4~MI9HW$O1?CzL)7v!9
zxS9@P`NrjRYplR{GXSO)8av7$SY%xKITT(t&Z1iMV&lyZpzw<Ex(J<Djr+C(rNsDI
z0IV-H{<RU}WyY`*P+x9riU)Ls@v8{5DvfS^;H)yfO~t;}YsPFBG^>ruKnPwpMx+6)
z#+cd#g|)_v7a(!NcrphpH;w(XptsI=i*6X-GX6uMp?agi8!!#VZ~uV8M&oaE;jqbg
zjV|dl8)s9Zq{UcBk*QXrV;jJ38~4(wuFd!{1sU#GjWIvsFVk-9pvYy1(Q!L?I*ohi
zzH*l_n;!peW5OAz=rJCq+U{QC{TI;cGvY%Ecz}$zQz8Dq_z}g$`;FsN@;qRiM`bV%
zjR)vFHE3Mx410%+zlZ@nY|Q!>C?m$T6iFL3T3_`C%$V_Ay6!b@oTgOYBjZ=(CrlWR
z{{+EF<2!9=O&R%*(V8~0YQZvN+_oIpkBuwo@`$a;mx^(Ym<*1X#8Fe(8Fbp2{NIB@
zd($o|!Ei9Gx&^ZxO@d^gIGNlJLanpuCo9z)yO^r(K)tK!dCCsBnTpqg95cOS#GKqs
zGp_>F!}RQ{koPn#CC}@)>FZwrbHc=b1(WeIy-!#5yiM^J(CK56eUFx}DR&IS&vbk?
z<orzsKZ1q;Q$Lv&XbS5^E65bNgtm{9rrdD!2Ah6459|=rPO3~gW%4cn2{q082I^0n
zjJYs4%#=Z2XbU$nw?RI_R73HINYgMK`JzmmKOqopN{oXQF{Zg|(TX(%3BhvC^d2S9
z;!GVYz!`7)Vhvgerj(cI|8FLmZiIm~$@CQ6qdjjLq76OSbcLSA3#JT8Xk9cdpj=Ff
zDQX#(G}TnF31exd2>NnLy6N5R7`tS8j`9Z?rk`kKGfgRCSdnGQr#q+Frgusqmt%@N
z486IgE!miLp6ORJ<=^v7{@!3MFojb(z0mYL-FYiAy*>=q%chxJbQYWbp$O9zQ#utB
zTs5)QLScz1gNLzFQ{_f1UYUtaQLl27<L4k1rUcs0D@`NhCRCZuQsm;AY5roMRGXHS
zp>^G~{v)Wh)|eV8Gh1tVSB%~prs#PfH%-nIrKmG~c^(qCOo?9fsF~*Pf<%Mqb{|Ni
zDTaPJO{U-6p`zIo_$Jn(#q?|rNUO<*?o`}1b@_v|nR-9RTsll!=pfc<Qh7qdU6b)1
z)ZVk2E_9*UWqR%vuy&i+Coq{FQ`XmD?KRD=2kA3y8o-j=H`RX*n;w|{BG0(r6idY#
z1194qV0maNC+BX^Bt8XALnbGBjD}4E(XepD)J(;Sqo((1hZr+`V+%5FnnkIgM<(m;
zuRteEJ5~T@()7FwT2rP!sM34dG&LVEGp2f5So+vhL8mNR^Sct*d&Io48|sgm8B}~^
zXa0F3<m}B0mV!8#fBqAkj^;ONq1VaGp}VTiW-hr*F6Pox7;`n}QGKqP`2#C?xW~+O
z6ghD>AGry653}M&NO+p(6k@)|%`Y8-`V;0o$*{@G{8a)vz0HbZu=tppo&%b%`R$jX
z$<N&IBf$L4Y`W?fV2-1kzJX@ldyoq<uc7+uljgsvx+B;eNjp=BxwMwt-c#m9F99^v
z>_fF;;pXK{fQc~2hk=|ie@;KdD6@oar$(DEo&;x%`6)T<jWat~u)y(V5nd!V31(M&
z2&9?6{R^7X%_d5vUNVnSATYzcvI2@S&56$dEX#bBoTO}X31bePzZ`SRhmg-TCsLL=
z&;0SXV9hr#pAAg~X6H`<Q)o^tfTkkz0Bwwy&DnH<D>mOCN9c-q)9*0tsyXpISW3*7
zXM?5G9Hj(GnfVh6otK+euZKW|`G225Z>71_2$m{y>J)u{;+nblSqN5}t&|VAZqDq5
z`88%%F^s7-yB|U8hFSV7U~Zb<NI<L3{L&X7x6E~vNv=1)t-+ic%#;5Bw9%YRbwW+%
zL-eRMo2Tf?PK(*j7o^qfyc|~CHha=d-8ORzIhxix<_0?mwwv>v0MlVU>WWsUIhC$r
z-Zh7p1MQyqy9kVRnLi5yOt(3J@;p7}&U;YbYZlX=sn2Xff%yC8DR-Ftz+6ZrYW?QX
z4oqple7+1|56u#a#0{F|-+^<;Ttdg!VXL`<9+?sI@APLLHQUXG;Fx(R7MjM*-b}O}
zne(aKZ^CS_g)x)nsCsnHm@m=s`LX%0Bfz$`ICq2Ph~<707Wk;;vL7_rSr~;d#@;fU
zl93LU|E<8x94)4u5O=byqn+5<V%?I2K^IFHy$)S1BMCrrvk1F@cFfY3f-!eX5#_u*
zEaT(|d0Iy3^l;qL_zmPwSf1Cz3NOoYH_XY~(*8D<#K)pP3Qk|kwU;30XL&@qL4V7{
zK5zzEo}f3!Nz3n(fDX2}TB+V3#Bw4GgQqNesXi*yGW&1voVGM8z!PTqlj79jmWu=v
zVR@1w(q}BI&cM*KmSFlqMx^CwKNu5bsa**YZ84pJK#XN$Gr(dke^UVCoaF&MDsh&`
z6+nr%_<joL1dAoniorz7w-T72WSP%^#Cgl&RJ4*U)%Ivzu;k~%n2VPE3o-2!i%S(+
zsg}~6kV~_?O+~cn7Mx)4s97pL1Ie(g{R$-0vUva`%hE+IZMG$A2I4su@dT{TwPapJ
zXPzY_ll;GY%Qq|x7Fc{KSypJd_d7s~EEm7PEG}C#`G6_5%zF)buUI~Q66RmE>?lC1
z#IpA;#!4-jlsql7JWGF{a!Ut&VXDI7N(rS(%S!r0MU`bX)%jerbaAji)s|rsCV1Tv
zY(x3?8jF^;ty)X15ejcu?$gG6)3RF#v^vWxAEEP>C5rw&^_E4nlQ&qNr<7=;h0_DM
zCd*JZCev*Bq7a%|EQ_Nc&}Ip-1<M^vQ4AEeTb`@K%sMPp-VpD!oVW(l?pnU4t6bK5
zmX%8Z(`D(`K)&0OO*JDu7A}>o_gXHTg+!kv<}qx#Z()#Q@W9eQnf`uD3svR~Sp1)c
z_(RJ^iX0AF9#f^vkYz5F)D2rsL<4NZvhN8f9JR!M0WxOUPQQc+ONbHTlUB?BreW}u
zC7d!+(-w{!cxEgo??e4#%WD+*w_UXAF36EZD^5Yh(M27Ukg{8J=w%4lFFN=HOmkSY
zYZQ7N7p<imY)*?#($B+rQ4w8=a9Q*>g_K+uMNzQ8ZPDhR!Sa8Ot~)O4s*78>%Sy|J
zqpUP%X3ySxPa0a5W|ozinUz_#9zYO5rXm}Zy@xUt2UBE;BA^Tb5o8Jq3bN$=o|k{l
z=iGa~=bU?=-?;ajbAPxqUXFtW4~8vxGqia!w$TR8i_t&_$-NmW3Sjy$s_5*@QN||<
zIDCxpE-jyZ83$*AJI;8SvfF-)8&p`~&sb0hZ2^p7iY^8+KBhcr5W`6hE|@W$(z_vy
zAbNO(GN$My5ym(}>)jI!y^WHRCmCN*9z2|JEDgFN7%yEzV<h9_T|h)Jy0^k^G~+le
zLt_{=N>ax%qK-o(j<JPmFX9=0mBM@i!>tS?kzw~8CO?T0pahr9c=!@jr!Z<-08eGC
z)`3f7yhqhprx;D~bpM^kurX2TjQ?nzk-@OOgw9OH1ZCB;7*A2AB%870G4MGIqXKr%
zFm#kCIm_6h1umDd=tVesj`2q^44!BBdZF(EL*|Lbe8xQ5*B3Ard<L$N@xt?f7cpj0
zK}Innw2AV6ml%Pan9CBzi!5|rW{9c$t&|b(2QSJP8I%q$XI!Paj0(m@dZ|`2ey1SE
z6~^;Ia8-=0^c28XNu)4wjnS^fAgUR+Xen`>@mdHh)i8=E>srg;({iqkvEvTN4aVp?
zT7TYTlu(SNo}r<7t_FsM1w<p`WlAhHF*@j(e~U5w4EmZGH&?=L3u76r(_0xED5i9q
zvEnHJ+88faz{5L?mo`FoJ0qO7Tpf(NM?mf}N*jRdWc)*$=PrhfwoKiOw<vUO>tO`0
z0iu`TF$$SJ#-DHD2fD|YejB8p@g0T02N+lO!~Oe=Rqh}U81KIeHG_;@MyMHLG}0-=
zhm5M%VCfOV^(=71jEor|BaAi9=zGjC)6#g9F+UX+#u&k47}7Z7Njv%`Y>c&(Dx758
zqSCr23_ml}Ofg=58VGx)2mQVd%xR0jIWmKCfjG!qN)a(9=0>_xota-a!qQ>p3m>4-
zl{sdGh#PZZE&7fyXFFp`+?l^p<lckX^gTFF=7Nu4-iygD1J0XilTdM*4>L~)#8Kv+
z572syIa-7X_GNOZEaW(|*aYIo+(oeif99hekN_s57l1$}n;sNFOeH<bf|;+=6DEZD
zLJ$mwGCgKPbr`dBEqpq`yvu`@lgz}e0E9D_Pz_)N)6Pb<i;+wNMUSJHJAVQf&Ad*R
zR}6DuF@Uj5_eS)^F~g6*?|9}OS}`Utmt8<#BJ(M##Y<x5JHn@Argti)GKD#650O-+
zr~|k(=6Xv0oMQg;5Bg3s11PVX&isBHxD4jB_ib=ElQ~+3&MamiopH!!7SzMj9OlOw
zG@fA=R%0+{nL9_(m&?qRqVF8Dv;^*-XKwXF-vy>i2ee&eDrgIl$6P9a`Fy55Roxaa
z2k3ZbA#>YJh!ioMmjO`B45i%sC1&;jeSe~a$v0y#mzi&z0iu-YMAvK?^Sh^^rkwds
zGL%*@i{A%V#cWs$f3Gr`=@7Zb{G2u&)y$7ygvfQ~tb;I7!(8(!Bx{*#K8Lb8<~geK
zyTNRH9>c!LycP*uJ##BbHZY%Wqx#QAW(=M0Y+`0Si_Tlj$xLW#X1+n0^A=|NH&D~c
z{H6$fx0%n<Bdv|uOn2NJW>YaHxSgqKf$k3GhWW5`mzm@Ocqfxhd73Wfe_3#*n|X{P
zmOad2I_urb-19d8eayjJaJGBQC`ualGkFxG9AKWJ)9Lq_p&tPMfcb3&`UaWJ6!RNm
zn(0yakU2o{+DA-Q0$dwr{y~qz5$4u45P8gGdI2}eOs0dGV@!4{ER8cic@E|$nAOh%
zFv*OdmBAC{=4Zi8*_ev=;I}<%#Q@Yeuts-+b7T$B^>L8((Jc@s)-ylCpfl?Wn*2ko
zTphe{Va=hJ;$c=Hoj!JDoiswkjb);um?JDNDa^aGzNI=Y4^{<b3_MxuJz>y`mHahy
zdb4)^3*y7FRgVL4l(mF@pkpi}eFiO<l}|B?5Z0e!SPEr*-3Loytj*n+ixaG^yU}=(
z6}k!{;jFShG2RH4QxkBJtYX?^MX>~R=!<6YDT*4$IzAonc$S$1kpz~4YD^MYbK4=A
z#QMm#7c`mm_b7Cyu)@E9r>U$|%A2II*3io06suDTa+*~wfYNl<Z`7E<x<l!YOqPL`
zxLK?=y1KJjv2iew!{Shg=M2mD5V*6fk?FwYvIYtvd5+ab>Boz#jvkOa*7{X83_G92
zV}KN}+PpyuS=%U<T*T_70_tLx=i5+oiB<FjN=sOmDSLC7Rr5R=OIgep@N1Q^Z2iEM
zv!ZD0Q^A@~3Ghmmx)3I=uq?^=4XRkeMD$%{<x!OF8Y_?r3aeQs|Df{^*I7ey$kego
zXu*7gRq-igZnB=EP)j{)GlC>D8d&dE!fqpL4h6BASUEh9TdWK^ebvm$r0hux>qWXn
zTUkkTw&FJH+)a=+)?eG9><%kQ2+4NV3MXjkU?si}a+ft1K`+~kPF8&o>~^vKqUxb;
zme0!&?P1-dI+R}4ZOWkau^K5#aF5lz5;N1!s(%)J11#Gin7Ge+e+qUVu=43aG056V
zRUSjEZ9CBTkR_tRh)1jqwEG=qz5EiK8DWLIiHRL!)t`kIwsF>T$3Z7pem7xhk|jw5
z_k=Z#GO|-FCM9Yd*l*BI(~+&BnLWtfJ^;H;Y*+fxo!R?aVD}JvAyr(vu!VH$@-SOL
zQB+s<S1qvX#$H7G`XlUT9zw*O9Zj2k54P?rIO=I*pQTr<7yH#rAiUXs?Su&*wj0Hi
zj<SnrrF@LtMKKm%wmZEuj<eZCX!K)$Hvzl;Y#xO(1K4@R@Gy`)%@rhwUHAbSgV|}9
zpfiMBGzOia?8qh<3S+aELdyyEQaS;5l5JZ`RlDJAb^^u}!S0~zIg<T=?usb(KeUXE
zX1^u?iDA3WfznuZ-eF8>9D5lpA`;n6Ti{F*`&o(=CbOsR!qF7=CJG{@vL84Bm&Ts{
zIxL-HJHG??Y4+j;fTy$nseoh#dx4GiahdFo=vkJ<{^Aat$!1Tc1DL~B(?xTJ-SP`W
z^V!#_AgX{pa{^o;n?tY2BK9C1)F@{E`Y#M#Vwd^>ewi&WVZ5d6`ILDpV~@~=qMZF6
zZOkj!N!uZEh5ZIC6|30Vzv*pym0d&GwQKAM9<)`n&t<?;4ST*T`fAy4(!;Zk9eo_!
z4R$TvV>j7DbUoIych&>Yz&@4*kw*5*e?g>)Jy8Yox7gWSNH(*7UJbh~?50=@u$5g$
zdw|>QtqUO1#(ut@^6z)pjufkGXZKV?X$QM+H|Fv#dn2U*JK20%>vgeL*nxDjkG>D3
zJ#1ep`RZk#n*&@Q+nJsM_t<rpV7{Nt_yUas>^U*u?z4-BK_0LV)IsMU`xP<F53$Wx
z;nPEQ3f#8Mc*Nd9A%tPJJ1uiY*v~QH+Za2_0Hx#Xy|fvfU~}7Hev*Bjs)V1g?dL&q
zioO4HsBz$YvjmNfoOaqf9OQi70^-DpcpZJt91$h#T{zEC0m)&`7@di7<%H4?<Hor_
z0Z7{sj+7ES9vq<-tS85<3EI3kS_<fSbJpEMqYvl*|E2XPC!!s|W1M(ef%$TJ7JwY*
zJlKz+`EfSA1QY(8pE4m5z*$Dy-at-b1{#An@6#eYm?NOjYzXI61^}U)B3e3y**JTt
z*y99;OPBmf&e5Ha3FpimhEEZkP4tG3<P<&+pQ1Q%#V{DnSwhk37>@iZNGvB&4Usrb
z%6b@#=XlX)qY^mXhd~lK^A>_6afT@Jn9SKr`PmfCPut*OD(5{~ZKQE**&>)v=d2Bd
zXa?sqUpSn}X)(Z37H92B_?^v3q2y5xX9<OG&vKGzMUu-&Uk`GQ6E+u;=Q&PP<8p!1
zvJlSXadI1h%jfi+fX)Jrb`$yvIsCI2U=b%H8zPrDGbsL9!r5=5O7Y8_vAvKf<@~o0
zz%tGcZ4fQzY^Us61t<3(SgPbyMndEYCzdLwt2lc{;Qm$4?42-ijic0otL7vJ0(YGg
z`5biDa3<*eSIf!hL1P^!DhMOH!I}Ri05>@?6l|;K^li35rhyYcmqH^aX8@f|oE%y{
z-{MSkz)~}(<`KMT;Y`q@p_Oxtk{Y);1$)7@aWVtp{T<H78GyHQ&fkEe9h?=vVV>@C
z-Z=@oot#o3M7lVBOptEQI2(<9oSxe-bdS?_mhQiP&Ii+gAK?5+k<0s>Co3THfU}g!
zSBE&N*8qITd3PlmA93s!fE(uI(N{Z0IIIL%8s$_|l5C8lp9?b1nItU}9DO!KCOMzb
z-898{OdB_QuF?T^9k^|4z&UcSN7MaxkQ??BM(D&{L@N_#?o!G|9OC}@BDA@1H&X)P
zF!yiDG`e!@AAob?&ba~Z2se%XZG}6x<0KsQ;2x()xF`1$$|iVmM_)ywH#hS%ro@L^
zz7`gaa$o%&s*iDhqf!%JZWZMZY{$6|D5B=aJxqadf9~g#P!qsS-UdV<*C2z#LEK%B
zU^keX`ZKr?ZYWi(gmMkE8w}%aTmUala0@>N?j-jJeaSAId+rXrh~Un@hsJ2`(<AUA
zhAYbkE|wcX;q5rCkO_Fajq8>JHxjsKDKL=8J+A>Gnd`I}qAA>iX=qI4PF;lEH14aE
zNIS*d{4N?#bHArBYC4y(8hx4EHXZ<3+=~>y%;vsArF=Quo_>%s+?SGJ=`8oE6eO2>
zu?Vi6<36BA=y|TqLe;((xZDP?7rCEM;Y>c)wG=)TaBU&r3b`L`11aJLQ!1#K`wWE~
zFLAqQzgxoP&4L%D+&x_AF5`-+l&GBh=L*0pxM?p#XC*fv02Z!rvwMK6;{HS)UgO%)
zuT{-$uyLT~I#*EyL=E@7Hgwi<A2pz}j>|~{@CNt!mEh{Rd9L6ZxQ1MqXyo=)VJ@1u
zA6LQdE$#=!Xl&&cGGXvGm*EU$ZQQTtV`lDf5A20xJGT(U9y2<)6ZDY3%U!hqq>Fnb
zg5odT+!M6#?BO2Df=n;B>I-P=<6fwTGxxYl--1X#cit|L``pd5(D;DsKuP^U?$9Ct
zhPXpi-Sv>0e*oMgZpLBg9_B7T0xculDM~Fq=Kiu3+$cBUD0~{@KK&a26WqVo(D#=n
zxnBgp;U`>e3r0A_9rytz?0NH^Mxz6dMS(y^-XCHZbmDzufi`E}e_Me+#5?jE04_Wy
z3J4tLJ@W%}yYfD#q>~#@+W~{_yyupJ^Wd!*1;CTn+YM!2yqQ!|=gphMcGot;hqv}0
z0FUx!(kj@Ocj|L=9_MZR0|-CfUD_=9^PE?L1n?%;L1{4WX$p6R@RAZB8Om$O02jtv
z(+Tbb?|uQiKgsKV4$~FR^QO&nBu_zWfhgWW`cHq+yoVGbjp6AQ0%wcm9r6b-j#osZ
zkLQKcubs$y-vcs9yx*wUIGMLK35_YdZS;yw<z>7KE{%6B9DS#FOAf-|Y2Fwuc++|5
z6X?s}Nj}6+k;!wUyCR$S>r?PPhi69*p)<Vnr{Kj|-ecNq<l1;_6@IRBy#Hr{&-31;
ztMnpo0qw)`cyGudn$K&_ftmtdT?o_^@;q09E8-2)qq~@QjlNY>!dpez+RMCb3LBO3
z_(dRPypTW9SI(=UbwUO24<SS<dEtjZs(8z3t#*}X8`=iZYrJ?mT3pTBTY%Q<Jj*Uj
zO&zaRi4or5t)rtEH+cz<AyUu#;TG@>yw@Gk*vMNj3nERtu|puuJl7nM7G4)kP%AIE
z75?7lE&B-O+juY0E8`CD4GG}wyqgcucb6A!quale*FYcm=;B4*$M4k5+x-N(dw3tT
zz+f+L_HK|qp6LOA_jng*HQUd-M+@Eoo;!se?(=-<RW-<4Ob?ME-WT*QogVV`+QW-S
zyzL)B^)Rm!$*vhAynzqU_n0T5P0kqa^n4ozI?j9X8Hi5sQhtQ!B(LpL=zhZ6(ulq(
zp7VS7MeO-M(&EyQA4(gVgZzyYGIZkKZU%AYyU-7Nh+jufVi$hf0C0!-7B(c^_}{&O
zz9W3io3P-{kKX|i4}MS>L_GP-35vh?@Nd$AwxfLZEXW+=+wTU#m+v(T4j<>+&4$B%
zd>M)O^J}W%VIcqKv*3dGi|Jt<%>Vr|h8@BmqoqhFe-#I~F#gxQ;7;&|C<PVHZ>3au
z1mC<5TqM7gqOei?k=^wEi{>-$p*4nonLc|H%TJ<JS{y$v5hR}PL65BjzIHqCiTrn8
zf=Dud;aW^k3g7E4aH)KsZ1|hTpGPN-PVrUWqwh5THwpoy^JnB^pqc!Va*!;(=UMoh
z&0lsE%5wOt=tDKOGyKn{q4gZUVIhF$`3vZpy}(}?48%o#7?C{w2yKb;`AdCazJUK6
z)#VrQmrzAhF`wZ8?h^ltbeJ#UPmh7!%lr%5F;AuZk7=1x#{YI4k`?@q>7`c5&!T_y
za)s~p7q}`Lf1d=pukw3mp!FI*ix&UY{9!%3xXxcn#XL295yiJ_`RVj6fja*2F}Qz|
zzln}9)${kSh4}{lhgLK;@_Y9{Srb2ss#0$8d)(kmGyj#H=xgPFc@mPh`A4awwT=Hi
zE#U6(Z7(i`?sk6GCCGI0M<}z}#g7a|V>iFL1o$5QDO&0F^8cnlMj!tk<=XD?%PB5C
zz^^I=;6A^9HOK?LT{CnK@{{SP>=6I6SE1!0zsm^tBmV3xa3lOrBOv*hKT6e{qx=Q7
zIIv@UX#{3(oImLazbE*sX(Ker-$NmfC;TwV>P_)O8zE^gD5A^KL9kAW={hLbOw}Py
zg8wD~a2DLB<lZ5{EUI&N5o|pSoreX%DG+fL6i{I6h+r89BJKhv)r)%wv}<Yq=P76^
z1@RKx+6|ebg78>y#{>c@P4yLA9Kt}43-;1(!%tBE2?paY_;Vfx6Cn7pAC`gyJ70mL
z!GiZXfeR4?&Ice=P)fnrFu|N^{30g=i)gWRQgG7;fC$0FJ^&&GiZS~Be3ZaS;rVF6
z0SfBG2p+!!e5~NZbFdUA(9>ExUa+hdhy=l3L6A%o%$bkAB*9V&5~c{gq+;?^fngFR
z(gZJ=A$dx$hSn#i1rt;|pDs8>vHlD}%fC>TC18AuDajUe{XhPaBUrKxh%<tJJRy2k
zaETt%=LHuiI&wj<o5JK51?4Yeym^8LcYx0qyj}@XAb9ixlokp~*J4aXf;8Ip77N~^
zmtu+F(rk!a7R;r}f>Oa+%BGhIyxxaMxgeAW)s=#ItAVp!5o|T1vr6zW-Tv1EkDdal
z797xGF0Kn+rub=%;3z#&YXx&CZ&@cW_CfazK{9Qr>jk^qKpF%I*P**naF0%qHVNj^
zgYlMNCG8!W1!^_=S_Ci9>F(Qt#nYj>O(1lF$Q_&D0}3{@3tFCrr4GSfN}%5re6<cP
zb_@FH&{>b*V--lRz}5_4pWta)z26h4>Bi|76n+fJ0m0$>&~{%io0f_X1eZ2~3<*jo
z4Ej)TjaFxm1TV%wWLPkVl5-=16&ImpRABR`17c%>PBX~3Ag2$llY*DifPW%*moCI9
zfnY28?1fEKX5k==rQ<}7!u$Q;4hoYgVc{%1Q4GmL!W0Uzx(MgZ0pPH(Jr!=d3h!Nl
zGB;tS2PWZ&P<S0~dkB9}L()_D&=!MEFX7;SQ0guGfF9aD!h<u=c~t1}8q^#YX4`}F
z6Mp{{2I?<d@f)}Rp_SH%fx<Hs@(&UQoB|gtY_@_65mwO$2112`<A9$K<{yC<CxwG=
zf(sWep@m6=ur3eEB845rwEm11`cc?8MyS{UFJgr+Q`$6M$fpN#f^hxwz$Xf)+~IeU
za5F8^l7&Aabv7eK_!b}VRAHzXN>2&rAApwALf&$abm7n&5XlhEq&qcJ_|`mlm?iA|
z7LD1$uv54$&In(B_W$1>6n>ile6BEu&IX?oy3lL?yzpHf8ZQVZC=Hk|3>HC6fv~O`
z_(Gu*2V9XbfNrN^Vfh7+OTvKZ@V7+RKzZ=X!Zk4vDHXo40q`>6G5WG_x$yEm^i>F#
z=3_{e!da-Yu+6w4ToQ%Js1mjYLFTIPeM%=>6K-#W7uCXK1ITsZ%1uDj2+ziV)Cx}(
zL(NU0miCSH!gSi$Hwb6$fn=jlNHw@k!fzvB{+93;+N?ASznBKDML2_ARjtCe7K6Jj
zyhhP3Tbr<Z9`JXBCnd1kF0`Xkvku`G6wJLV6i^9qr!av|{&WdDcVkMrg&&;<ut#`{
zGSI!k=^p~#C-kG+VL-ThExfod+#3e&fiRGA>w`iUDkB>b#!$%rq42-8u<%Iu)f(s=
zwh345htd(@d$i(wEPReGwo&0zl$IV7+S5_$ap7JnK$#HgX&E{x>^4F2iSUa9;HHH8
zcSDW6XckouIEdc+9d;c>{*S;N6m9(qeTPJqwAyhI<t>N5hed@lz+FZ0?ojO}vL(qt
zkBHu)NpKgvP6j<h9#tToqMw$-gqJ9lu1;^!u5mOT74=QRnPVbv3Mu=F_6-4dTy%U3
zEcuC|D`D4PWTV3P0MV}$YYY@Upw&*0=tGKq2aA3TLSKkz$txgXqE;J~pPmp!_QAwS
z(Hsh5g^QAC9~L3<r23ag(UNL3Mv1K9up2E3+5*WK(WjT7G*+~;1$}X%kG=*;5LJH$
zFA_yp`oJZLW>v$rWYJ<fSV|GOPX|dA&7x3cnutw5+9^@W5gSH$TC}kXt?8og7XzOm
zIzX3KwkVdKp*f<+r4TtID)|P^oE2@PEOD+#MHj?5(UX~IJTKa?3(i~+2`Ni;Q4~PI
zzC6)8BH;2xJrj^D6dCrz?IO{?dNdY`1|9)-Nwm@9|M@?WT`v%qMOANrl!}b|Fwip5
z?)5;Fix$yxqe3J*g}zGBJ{RDtL@gt5|Eh?$2aVT6&(ndLYEexkaMwi>d>E_|{rVeB
z)QZ+n-AtW`N!iaEqKYQyyeV4xB}D2)Ut>Rm{GX_UzT?>>n$`~8w?u6=Aeu#eRN&Vl
zV*LlwDq2Cu%5RG*4UlXT$!SY{M<jlP#&%I8y&^kA916{LiQ4F7NVjM|t>}A1b7?!)
zD=MYLd!OjwD<JnoB1(1li~RQjXB!ahiU;DpDC#@3J`mNcfbKz2M=eAjiauWinMb0D
zN;o_$nkR>e5z(r2D19tCbOg?fiagXHV<H<x{>MdUUxKm;QAQd>CPghb(f34j@GB5|
z@#-(3+Clv8PDnb6%}b&4piO+7!aq)82Z|Xwi<bp~91@q(wc{c-P{Gb&aR_bvT*dd_
zhi*6VO!}I(ySQ71Mi24lC9vcv=F%Y!FR?Hg0B`a5b`T$N9^L6j#ivs-vSZ?!|L-fr
z;VJ-*i#HsCGC#4+`X1B-iv8%DVL{@!IT&xSxQ_C}A!36wNT|3*01_s?w*Y>h5QoxR
z{G|9y3QUBHS@gV#5Zm)GU6JB>qmYaie@UC97_kr4W5tS}s{}4i?DhpL#Eb7{0+%4J
z_!T5kyv#NTZ<55vrhrHm|F8`tMZEnL08_=A-63;I+<pz*X|Z_<_;hh3z1%XyIYF?S
zDPBv3Bw6C#Vu)mm7tezE9C4To!#*Q^ClRX8ioe_lkzDa;D@4wV8G67kh(At+p^M_f
z9X8NB@t2h#`QkR>3dH9qf?p_JMRk5f;uLR?VsYgj056F{>0wYJUL=I>GI2VszRSha
z+X1K$fA$n4E5$$1cIt|FnBGxU;_W}fnXBT96#Ba+o}hxLYVn@`0KYE2rK0-l8u1(V
zAX+D$Lj`X)#0R+OyeU4P2Ho{y3%ynv#3TEmv{8I62$D@=_m428x5NRo9cvcX{tG~h
zxPTt$t>RZQAkrr0H-X#{JJ9!E+QrgR^mT}tsleS8_tC1MQ~c>Y`u~4jVqFj{b&ET<
zL9|Eg^C!4o@n=&&^oebMf%J=g*Q0Sjyqp6|_r*GYjN*a#L#o9a6blc642jQefzpR!
zB^^S3Bvy4ma#$SwIp8DWdS?J0iwzWP8y5%A)@4Gx?>0QNO^R>73z;Y4uPF95CHA1t
zP}obxzJ@^ui4R<y;V5yB0XZo7h@O^Cl6PrI;4FFjQ%tFg<nj>6VaXj@sk%zm(MH!z
zvf&^kk4R>&f-~-tZN2ziJtQCe2%VmilRS*mOR|pQ>E1TU><Z}ik?f){%rVLH#gOrp
zy!$as9G3{P0Q8ec%F*aAQ5#?)Kr%W5T%aVL3<gOyB>)#JY3hQ~5XqCTpfptSSs3Qx
zgv1;LFHTDMRMrtLDU^YWkYv!>GE(An0~Vqrw&r-4h?bn7G*gU3K+nKf$@8>4i<7)_
zA2Sp$nFxf^B#HH1*iDwa|12a^Bz2S(NR>3wo+nMBNQ3!Pl6|ykKP_2JkDYYMTNFae
zkYvSy%ao{Uz-39gt^klD*}VhsGm;~=a?rDqrL;oNmE4g5e@?QE-lpdzE9hwB1xc9<
zeHSH0caS{E#1gocFPTm8zyirLwC5?3JR1zISn`0%^DjwuzY0<!DWufmWywN%pq5Iy
z@&GTB{1XItxg>N4NQEThds=^1N{U{^n65}xl*0T~$t!c<@HNRTsy?We{7Sir>k`{A
ze5#QgKMkd|5~Tv9PBKQP0dGjwAA;_il9*6%^^%X8;Y@?%ZTdp+EeVf~(Kbug(IK4{
zNg~B4+axVNqwkI+<Q=;I+9d~QF8d^pd|>dNq^$y^U-Dco><&o2qe%LFNyvvF4<vT>
zAcK;UB$ybIJWXF-c_`_j|5ETs;_iq+3`;Kl1#UzV@Crm8OMax0jY>9s3du3a-d_M8
zm)v(p<Ah`!Pc++%Ny%JFQ9hCE{|aPEl0o@ld#U6nARMH}_CVB8+E{|29hC0gheju9
zGG=Iovs7uqm<~w~2{9NK>79KrcvyPvKWK54Hqb@xCe?9(J0h)l2g7!kMp6FVLwe#U
zw0KH?p`r(ym-Hw-;Jl@M{{Z15?TkU|QK@49xMR|9Hloj0`a4x39+#RIq0dih`vjBk
zFI|!hH38C(OlS<0cJn}jq`%V794vkHY2ZSnJ1GAbDm_fkurTTHRgC_GG@ah;C#8#N
zUmtFh=3Pc>gmj!%%8}9z%JW1?cQJv8mZqElK1TZbcMy%0E*XYMoYeJoOi8?yyBZ`x
z`o0-sN|aVmAxDzb-WTIdmL6@w%%n(7R9%%S-Le6aY0~fL5;!F-r9z$4(ys-OOqber
z(^D@)>KzKFGNnzFc*v4&pm<fbw2v~CInv*#?BI-aoYwhgrJH^LAXi%VGa4^QyJ>xM
zQTo?G;PRvnwAjj*{+kGRf%GAri7J$Gbm%LR22h5-SUQuc-Y-e_u7^)0(t2Ab*vryp
z3T~E4#Z)&}CiSP1gmUR=y4WhDdzJuSDNVc$yH}*%KLb!DJwmJ5tI}cGDPEKAqWiB}
z`jG^U*QGy1LwAi-MG2Z(sp>0uQ71j}G~hR+om4e+Q~GBz8tbJ76~#Xrq;9QH(<sfO
zWOI{L^B8t-NnJNVX|r?}Rb#hEFZ19<t8{fU)ZCUz+hC$iI`?;QccgL($hAvzG6Cq2
z#?s|+SE^8>uTvU8UsdUn?%M$^-O{U6iP0lnPVehp>A#({|Lc>Ur^1(e(%l-U>6dco
zZXA$~Gr--KMx29B52Ts2&>oZy4}%+$4r~J8p|s!<L>@`kHo)$%)PFxb9FhKh10s*5
zW$R&ZRQi(&B4g6Iw4@%F#?8jCC#24&Au=g_4i84#j3?3o+G|Zo(_V&Bds%M;5Dv1J
z=waX}^P+s|L0JjaUpvVhmqDqs>=TL|9Fp;<63Ruk>mXb^EW7p+I9J&iRYkkW!f1hi
zM7G-q;x2ptG0c0&zVL#h-m(wxz=DtLy=joN9hH^S5tw7LM5;CMmG#UA;<)S|4Lbc~
zfnEUm%Qh_r7a$Ayf02po>s#Q0WN}pd5G)I!MP7((1C<Ad%3k23FHAOg7CKMJ@`5m=
zld><g&>1c}xD2C@kX>j;U!=_bBS=QsWE)c<6D{*y1DP1v+OI%jWxveDB@idOK(!a~
zGSQC^O_13r>Xj&4WkO$)Y||V}Lb5FV2t-n3yUu}2mHqq?;Ayh?qmVp>FWf`*Y1#hA
zXiS&g+6yj2c8bCSnX;)P5Xq9+&Qcvqw(JHul_NVyQQR{!ekf$l%5FW2zFb)q6#<=-
zxz7hVFMEpK!WU$}+y{42_U!LaQy?pk1fWnh?IGr(NY<gn%oNKKsbKVytd0&`l*oki
z%)Tshr^1y|nf*n;%VdAqD0NmYn^_NFh3qFANTn<`45C+LuiU_tR>>x419w%{I}6&b
z$=ntKUn3i$7f`J%m~u#UvJ*l$dP9~%&%m3qVT#Vz%L*v;&>)*(gfoq@aw_p`lKCmo
zcS}}GHAu~}A`U&FT4dAkH=|Yd)Mm)smZi~GPTFLyvqA32{-$s9w##m9!K`=4exQr|
zuIwHSv{Po=0@5Yh{5G8FmMKwBIipAR_H(e?EBmhzq)+yp1@L>aA==sY%ZfgR-2qt!
z<(}@#Y9)03=z**`9iteOy-B~pkgSV>Ne^Ys@o0P`TTkolVcC8vXBm+#qDAdvS-1$?
zsBDiEYQ|)7-S~aSWz7_FoRIDEgrk$P6?quw6WPsAAu=U%^nq*ka_s@Ac90+Mf~2GT
z#!@<edr+R;1B8>DF%6y0au>Qx4#^k142NChe^A=yu>8|+V9-_W_72ADCjW6iyf`AC
zz84<4%lm27;2~e`gQ0oK3ut-dCBKpngWmG}RL<-p|MndEj>>mY#_pK>8x55C%5Tnq
zYqsO^^Q+P6C%<<Dt^V@G^u`O2e@kit<*s$G6eNG?7l;PSo94oNi2Ud8K|<wk3_v7I
zUUv&hPsn$?2}>vCWAx>taQTb$ij9!(c^@7|%8!2oc#PbK9tN@UMfA@Z;^ZuMNXFab
zo1!t$1o<8gS`+20F*uVX@6CXTWcfT9xD+{~7$T|is*7k$lONs)?v&i&9Vk65UuXw4
z>GB={xD5Hfp3ssh=TIy-OTM0-z1i{;w2jM=|494YGxBF<0dQ8nZ40#I%5DCX>N_WA
zJ%*+8^2{W(UXbs50iqY>y;5*_^8Y-+<;z>0G0+0JpFc>U{L$~wT_pc01lo$_c@)3A
zBv1bfQ&J*#`3!xR<*j4jO63Q(!a|u`LKR8n@`4-SD&+F>;40-aY=h8!MSh9qxk~Px
z3vE~B+60)mCO=Bi#cH{R4rpDM->3gLRwG~dHZ0Z3&r_26rhND^;Pvv#c#sD9TsPnv
z<qv6t-6XHL3rn};i!&hEET2vFpDprf6lrOdhi!o5ZTaqe8{BA<N1cR;JMw#50Bo1<
zqE~E({2Mx5cUS)1`)KTxZ<T^{$+b^Fy5)iop|nRHGX<_!zWV~S^~p^X5WgpX;{@F9
zmmi7+d_W#W2So16eP{*sK;FF=-Ve&Xav?G#zm`wuA0Em}DP;0U{-^}nhUM0|Fh3$c
zvkfL5%Y7R$iKFuP03gQX-!DhsxZLtBEKSH8C`~jef8`2rPvpygz#yjNS}KmVS2POI
z=b)H>5&%cVZ?pwDs0hA|J}1S>&!Nm&QHIZ0+h!b6yiS=)7saW!fH<u9l?}VDipBpx
z#!c~H1}5l;LQ5|hcg40<(B`2yN!1IUibY1?yc8{zbn;gC--Z`H3VQ)0k1E<}8+c67
zK^KIt;wP#oI<A;&0P#~C{RxKr75`9L%NC%R`6JW>Dg<=$E=UnbkGo*SwCNa3h$5&4
zYC;w9RErm;*hq)$PAGOzZOuu=JX%nNEB@>O7om911zI8%E`H#m6t5frAX?E+>3|qT
z7bOQ`6`bQ3OM+td4wz3=RBr{BWK$%z!Tn^#mMXNSDAanGPgT6M5+qHr>scs0r5K?b
z{<Pw2DM-3vUmSoLiUq4MPnn9^=^$B(Xh*n~t$6SW?B*zL&}UrED13f^>a&Wi|3FKw
zqKGbmbBgC20Y9&pnGXvW6t>ZmpcfSl6i3NZ6t}`ezT*8tkOIXMTD%l0RxW~xBE_O_
zp|n^rou=fHLQw!qB?=#UcwJTu@E}sEC=JAvlqn{yaHd?rTn2*`iW&hXp;Ga5H7s0F
z_|OWfN>SqupROwEY*eUsO;JYY{i_wDbl+cBl*htSjY3DITeXS{lohB`Jf@fN4TU>h
zB{vl-dLdb_h@(Y7lVVhZ##@TVR1eauI822vEefY7xYnxZd=-ti719xmrA_h7Fr2xg
z5Ld#(cEzWEQ?Rc?v7L64cNJgLVyjcpO>wd=MUp!_?N<C-4>diC3pZe?S22DIq)$<B
z1h{*O^S7a`U$O5rObjU2P;uFP#eD|+eV{ly1rvjcRrG2eQZ%iB`G<-vRM-1RF?R*}
zh7}*%(f21t6t^g3@>uZ}?HWcE!ei(hQ|Nw0<G5m9KN=?#JFmmTNyS1sWBWvLfJQN;
zC^`m%_Db_T5C`QPS`IoYCusS4Q0clHZaXQ>6nS)3$|yE-NI6&rFI<$eFW|*trS&GA
zKXO$DQPHoP^3rcmdPKQ{ei={Y70P#dDP#7*3vZ<toqG0BX410zsIqu2oH?cxC8E(+
zS=WmxIj%gj060HoIMoFBD?j=djs_^*=^_nOK1-E(LCT9X&R}INedi`bSxQ@JTc|SZ
zdmv6KbLnhGxN^e>FcG0N(f5cVm5o#d7o}8Eup(MHEdokol-mx${a9tMH%Oc^IU3sH
zmBkdEOHej-z^6pzf}bFnq%5I?ZnE<I0Enb0kI%yBQ<cyD2xVzXkrb*=*^~({!j02P
z_96h&l{pjOGL*m5HJ7Qh`wvR9lzU<^v}|SiGic0FN=l&ZjI!)5xU<SHT7k<|meU!q
zbIKnn)^T1rO#~Acl>6%-a#8t_FG!x!dk;kNmA-UY6)3+u30$GlwwRtbMapH<&|0j#
zJP8*sDN}AkO^Nd2Ah^rQj;CP0RC(+#C@oVuivTEBo~Hd&g>na-N~l!ss72ou<(CWL
zZ<TWWGz{XJGNA+}s+DJ-2Dz?`RiUp&IqM5JQ>zre4tsUVzilRn-ca`b3rjbZ{ZzeB
zuUti;ng->6G{KEZf6AFPDW{!<<Spf!1Z-A*I1661C=Wl2AFWk+$prWvW#nqW+m)(h
zNOmY27NPO3lIH?=r*buAx4M+G>7m=LtiF!M9_7<(Z1AmDS$`b9^(im2FzkEEZ7U(u
zugsQ!8&LYv(c=5cr<Ot61Lf{JP&24hQ8nn0^4zmf^H3QtM&l#pyw$)BD@CyYj3^gS
z$m6jxgg);xs=T`fePhaHZ@}$w<+mH5Y(gpYp!2tr%Ka6v^hCKY5bjSYm4~3zUiIP>
zh=b}o+5tJLextzlK~>%~h&ZV>P_e$V>f$0OJ*4V7gFYA4isjIKSQSNwp<GqJ+Jkdb
zz4R6&kEp^o!h*YMkn+(Us(>pH@l>^*rt?Q$s=!;2@m9^JSig_z%cbZ%s=AYi5gt=@
zM1uILHeCcct{Scb-cR-I1&r5UWr)Yn0#uv-g!w>K6J0?;Do5Jh1gjpt2NI%M5Rbl4
z)tdKVK1|iqgCFLE>N3R`PpW3nBi|OT`hntl5vq&^h(@Y>DX9^qnnk6P(JD7Ox)Y<a
zQq($DwTd<dajLmn0Ekz)(n~c#H7JJniK-~tv?r;44S~{R)gyY^rl>y32A8V(Bnl)=
zwKD^%PpS6i!O&^d@?^l%ZK?!Hjb^AGQ#LYF)kyE%EY+V>u$rwJx&V@+YU)Ja8P)4l
zba+<v<84^VRW-@r#W~dvn_&LD>JdfRFR11R0)A2TJVpNVROL>P%vUWq0PhP_-_f;N
ztP1pjGnZ5`S~QlZY|q#Oaar}38HiHVhk@uUQ@wN@o#iT?Gx{o2e>9-4QZ;n~eOFYQ
z=-@<^D)c{$@TzJ%?c=Vg_R^t<YSlPZB3@S&P(->$71#`Tttv4OfI1ap80K%NY^MOY
zsd{<{Zr7{U+334%4XRla=xkK&Vglc!T0q<NTdEzK(bueUq~&vqs=NrmR#ge5dv2><
ze-TRCR7>f7e@C^C3CVU<>=5jBsJ2I8g72zo>2~N;Eu|}=OSSC@M7mX6KZx|GS|~`-
zt9mM#;-7u0mjB;)s`SH<=~q3|4=)B(p%fUqukx7>Z4XrTbR`X{{3(V#q?(oqXCA72
zo`JSUs(s&r8&+jeebb1_M4Pk6DqpG&8C88h34g~_Gao|PxGIHW<`b$JwEvq_t*oK<
z-xJk4i=lK%RVo3{Ui~8FfE?7lbg?<A#q{aEgX(89(deX(aRBG6{{A!QKBRtrHaHjc
z%0Dm(ht;pqYu{BJYeu7+`qmXR9#QY6^@+RMZ2{mO>O$IVc&Z~>AmXKNMmeT!hPQg<
z_ps}uPWuz?A619H0dh<|@&uy3>a3;c^HblVo5Nqdj?Qfas11~w3{=N5p*u+ZX)Z{x
zI(`irL)1=GvK6YHu*Z<X)W6Y-{)E~el{Pa@sx=AV!qs0>9an_<wN((YMXEihx+_ZE
z$%2V!^)s~kj!}=NV1%*iMSnwEoca)zK*g))XwaCTp0^A>C8~2NNRg!8l@F0*wfHi)
z6!o9O5J^>AUWJx4_2)rw?UdS;o<675JKNEhu67o}Zic#=;;orB^)ugt%~HG4<}O?9
zO55!mHJ8$3XVly`06eRHo5Iz(YR*AOo>P01iSz1zXdiY#y?i-DE~>k|!R4v{rGe(F
ze_jhM1?r#bK?>FX&4IEa^_N)g&nQ-ZK=GbS>I90;m#A&d^hCa_{+KpGW$G6PVWM1p
zn{J>AbsQzKE7g;=KwMFG+W}Ffb~*!tSJj*j{7l!>ap%BQt5t7-yRMF*AErkA0&Np&
z)pp5nv`+mNU3xdv#q>_TsrH+KmU{J<RKMAvuCdX!xluiJ0Ei|vI~bO3sl^rmo7HpP
z#IRe`#zc70s^0VkT)VAqngMNX>Jf_h-BAb7X0~0OOu63<b=Th@ch#FHN7t!Nr2|@B
z>NyQi)~y~s3kyAJAr(aRs@GBqs!#oQHHD4usW(w5ykA}LCVU%EzsG@z`|7Xh0Q&=V
z`+Cg9pxTG7^&#~;m*CSw^@pDW@JPM=0szD6n=!CEq7Hlt&OBBN*P(Az{XsPv$J7>D
zypOBfXz?(ij{XK-OsbdC3has6wUFYUQ|dMfZrW@7m%&p9P1s%#C(R2MG&*an0Wf$-
zBlr=-Mf0Kx<gli11&FI=V=hd%X;z+szehA3bPB^=V+?@X9-1N*I8V)w6g2bFv_61A
zZ;gWX06v;5KZqRF*gWX|JEoD)vd&ktZXP^6uJNJQnV;s%<B;*!OwfWiKy#P2PJx=6
zS0NIl+4(xm2W#9)K|(a^eBni?=Dn}c7pCFU66l2HmHX&Bso6rwwQ$X6v{H@GJpUJz
zMQS#$#au*bWOG1l(HaJYe_}LaRO}e5;jaNcPV@Kon9F!gni3>IvxW*m5;dE>U@1j2
zv>a+uHOp23kfu4j9F3<m?~>BfnqO#RkgkcP*lLF6brVRY#+^!4vNWHa0?F3wq>C&^
z;}8y?&e$})i-A9@x$+Buxf&e{<ea9JV*TeeFVZ9Ff+l?mjTbcuE*N2+CTJ<l=WCR7
z8y0B%s93mAb2AkpMVgtXF>A$|Uy?BEmo$s1o})ywpDHmfYwYa7m1>OJfGgA7rzLs0
z#x{*^@d`~Qg>fo1gRjHH6-^f(GF6&O2chPw#_|XHu4z2zRA05GCj#zY*SI90u|_jW
z&%j!Z8=cmy)2v^Iz8jh^DH?NA^Ax?D>NR0yn3)F6OiGe9Y6|YaZj&ag4I;NR-8M>9
zG;7Wrg|-&W{6j#rYTPN!dt1Xg51BU2UOP12(Hy1yU%RG}3IjVdC4uPc(o~#*WVhzY
z$C$1jO$|+OuV##beSMnry&(5A$y)*M*DR*HX+Yz+8|1!bE){Y-(73!u@y|icXcd$W
zX%4S|Zx1yK&I9;J^Fu#e8`fN=K<|iV3sti{)@=R<21hlksTN^OqopId<C+;l^i62~
z_J)>8%^Lc(o@mbd!KW$BOMJlXwF%cC;-F<bhxv8XdeCohQ2Y3KI)Ce=?TiA@S?f<f
z$sw&LRlmAuSKNT^!&;X=fpFCZ%?930d*C%R9?^b6MKSJL1;xiav@SQmd1^yw5$&aY
zLUHB*?PLJ#25Ps@0147gQl(6=Hj*}zA=>gJ=nU1?A$en)5vE=90q`fZd+DinQv1OV
z;KH@@DWe;qz2^hbNNt%OT$FavU3eI+UHBMEW3&gqMPICTbt>jCPFp^PzIg3i+CU{}
zgKof?L~V;bNRsxgUjRtf@;Q)9(YCw<4^y=te*t1k)2jZ0!Bbk(Zm_4dN~*_7*Zxf_
ziwtc9RXt>C_fYv;mUil0h-7Qe+dy)(fu|vIMqBy;-9Oq;H<-xPzBL=<oc1=ojL&NW
zzJ&P;S}n!wE@~aT(3q#?&V;>u?IbP4ifr25JZLM{{t}GVOWJ>FX<edi{uxRyYk8FY
zEY;4Ux{NaIpaE*iwUOVTuR<G13(qUs3=Tx9v=I~<x~g@iv$@x_`pY2I+GW`=ab4T~
z4<u`}F{2nut@anH5UA6-hJ)PD+J51~{7vl`y+-S`xwI8%&^|{={YLGt=P>Lh?VrD+
zuSNSVJ(pXxv&<lE+VUdc?`SuD2WQ%~KR<*>hxR#2*x%KbZi2s^TFzN$>C(DT?7CY!
z_cJK#(dM+GuUGqFDqQQ+?y%7a?`fxnL8f0@Ifc#v?Z3@XdSC1MAzXW){j~=ogWA98
z3Let#Sp@E(mKh0ckF>6(Aj4WwCdi0(*%Zt_)@IR0XjI!r(Wf!(t9Jny*X}HV&I#?i
zYtcBVoloBydZPVOM(@8VZ9m2C9CQwJlEzW@Pb5SS>Y^zSct|%b8htK0#}ep1tZSz*
zo2%}|FeKe{fuF$A5#3iCKs<HlDgf}(70-u=x9-F5AaYDMjcN&eb)FRvIj)<Kf%DT<
z(NE~FJ9m@v4*@#vB1~zZZqrJb2-0=Y<rS=ZZY%r_(G60rAXL{q7x*w;1x4vj=w741
z*h$@tqu|1IH|UOu(A^z{WTdWcE#OhQu`ZBko$ECWFh=*7VzRNiS@iaf(;ZPkS-h@)
zAH_ctbfuK?PSj=5TqNlxeucJV-7r<!r08Bvglnm~{>5-6O(&*n{gkej?$pz|^an7J
zu1nYjE<@M!9k@*0w0`K$(nZEXS+?#_6&%gcU1@~K86DG#2|BAwrXYQ;?rbA;+Ro`5
zpM}zkx_fj0FHd)!R+ag>hf83-K=%cGMzm13iwWIDI!PM1V%^9&D7~a>iGrggx*V#Q
zzN~92gh;6_lGa>hx>sopQm)Il1F6t`-3n5vdn5q-imo^ZcB^zuifdoB>GrIKH`jDK
zP4J>xcV;JaU)M?UptMGpNh|wW-O6wP>vXB1;OcdkSAc8KeM}`^jk@)*z%}XC(Vq5}
zjzy2VW?d^4m9^-)YGI;P_tA7n-quBqV}R|tqUrFkLwAY}J>S*YT)iPPpo@JAy6@{g
zrC7-W9TE<>$aQX%n0=&+oDY#<T?7MtBf5J{u=H3LM{(v+-5alfo6!A4Mfa1s{ue=>
z=&G2&Ip~cJ7`CH6?lo`+^;;<}=cNDhF^IE1_8TZWq~B_*gKlrV>k6px(f3iJ<*1&!
z3g(aL6VAYIUwueEEFIThrL!}BdL9L#{Pp`N^bnwLYk`SC{knOO4AO^CusvA6fD$Dk
z`rWh_4%J_|jm9v24^8Ds{R?zmgzNvgjNc$aZ}YN2TcqBTY8j&R(|f>0>;33?6Q?)%
z0~oKLcL99~`Z5Xn67`ima5PCDM)Q=c&wT}!QuKpV0hy{#z5<aneP|{Cr}PiifS=Zf
zMxrlWfBhwJ8T!5NLnKrG(mse}=~t)F|NqO@hqS|~9Q^|(?B?oaN{C+2XVrkas4x5+
zBu`&D4UPHwAO8SXp#Q1|N(=S%lzc7H&!htc#rpjBp!Aadn^8!X=sy^NqnGuwz2Ru7
zUPz?@W%`akfGgL3dH_>dp*Md{^)HqBU|MQk(SNxSq)NYK3-DL<EIV-5^iQq>U#-vm
z3HVz5=P@9+^vSgPZq_fJi_y2}PpYA<RUboBd0YQ`9^h^Iq)u?{`kCLOuS0L&49UCt
z6Xap1{xb@7bm<ST1+jJO2k4YrkA4;{H+uC;+<>^JfA9@D`}G;_aCksJ?g8$;elEpP
z9_SZm!~CGWjnW@O`YRPs`cOaO0M{Prw|RjZ)*qm?_=w)_7tGA4ev0n6F@3`jw2bQo
zf1__gzlDnTCT;rnxftOS{Yo2jPw9XA55(SZ?_YE}80_-U=V&-%0sf$&_5grR2G4)d
z=xq434_+KH%<O?u7lYp)@cyu2=AY<uHJlECq?=*gb0D6EjdVMB8{VY_f{$UtJPh!t
zA@*nV9W&SzPH6QtEJ7@L#&JV3RW<||F1BJYfd;>m=nFCw386dKuw*6rLJTV}0vKx8
zO0yPb*g%2L69z8blqU^y)<8>y;X4Z3MjCVvAQELTpMbJxgW+?)V+=8?VLsO2Isv!i
z41qRUcE=l*#6wMjVUlVO6Ad|U1CeC7`V`b88#?VkQVp&2phz>cdV)J;DBBD*rwz??
z#wgvef%Zz7hWA^bG|O<M7G7i<-lSszIffOv5IJLbo8ozA4Ldr)<r+RDd*=;l&(Jgf
zg5f$9-(EC~sKDhJqztIZH|*fTwF1LZd-N3=N|i8i*|2Lh=AzUvm+rVSgFoHr<%a(#
z<WXVRGaY?b3|Hy3Uu9U<fxfGT6F1R!-7uZtHHIWAC8{-4QG}<?(C{;zzrA7Llmb|9
zc(xLD8w?u)(Aj9{VnI!_LHHK>S_}i9U@)zQU!TDw+%{aLNM4)aTpj>-43+d*hjv5d
zpOCz3_%9feorYg2;ooJbs7GJ7VVEK=J%(enqVF}F&I9Q)*pJfs^PXYd9$4x(h$v0<
zz%c&?lnxqVuR+a_p^SD=4-KuGq5F~H+jjH~8>*H9|Jd-_49w-IVLz2Lj2V(wKxEut
zQ=xIfz}$fenliMMK+@j0<o`Qc<9jcm(b4#Y65by)wo}mB=49+X2J?rEmRBL_Vyp=T
zIczK%gs7`AmEsw0M&|^GdKk-TW;~5jI&kP^JfMMx-bTYki1-)>D1&v>c%v8aW5!8}
zt@;{YuZM`gG4g4^1B^BbqXZiF(QhAQ%t?Y|u+8||e6)rde>et2m~mSX$O+@?bdWsU
z_$!5mB8&-jup4Ro%L9`iWmJC&^U=mn8=xk}`0aA^#Tgf`L1VlzVipW07@fFiOf;5K
zp=y$`n+sgB@q2o@ry4iD4SQ+EX{79w(WanP<!PgL30zD!2Ge|H8NdGtvz~37wGnD^
zjPezj;4{WQNaU=saux8o##3bXoN?|6czE78lmT+Vcz{ZYE*iD>(3fZI9EUUc#?x^i
z1x6;VItq;;R8n4K49J3^V&fJY7oC@kzti#3664DaP*ZB`DTUu<#^>LK!E$5$26$Rw
z{FOG*mBz)FpyrA(IU0Rc#?L$eziRx22W{7k^C;p{ZCsoN^Vf|#DMDLg)O-t_wZ^Y$
zNnU4so_5VQjBgzPchmT#p2AM`M#mSxHW+8EM`xpPn;hnwjC(!<xn)eF%GwsAirx;b
z#@Ygm{<d-XQuMW9*1+8{3ZH_dcH@jXjK0J8^cM8pH9ApPq0_jX4|tc+eH^O0je07p
z>M>s51h;#QUqw*;XP@!IJ`C-iv84*F{l+`=*?<9KHpLb08^b?`nnB~DUI2%T=jkQ$
z&?vM+--vM|?X?~odoF{F8o#D8`!Qoby=2CXuhHXq!uW$fR8JcBQHb-2F`S~+Q^t4b
zJe$2~_4aAF{~Syc8zJLpa)<)rpy^Y(@tjOUP7rlA+08@aA=7VEF5zNYmIm{OO)I_7
z=V}`N8sl{{bv?u+95JbB`Ri`_^h0nSruaPIJWVh5K(&|Yx&b(ElgkGfi;rnF#oCXW
zOtd1g9WzbPs?^scp<@uoO|!ef`I(M1K%2km82$DErYt(~5NP@*4qT9FvnRM<)0R>I
zLQJhjcoAyiJOkZfCMGT3PnhZlAac@_ISdkMT2621C{r^<C8JGYbXqgU^diNJVr{0d
zccCWEH1h&nj5nQq4<x}Pcn;<hO<s4vC7Z6(BQ3?WCkZ6g^bTz-(oF*tNzX7zcVaM^
zrq#4}&oZ4Kffw1Pn`>Y&$0RRD-x-rLZTioe{2ZVx*Cfe?y>q6Q>GC*lvi(Khf4N{%
zZH1>7P4j<8XP&7v6rK5|tMq6oFv;bZs6x|4Iy72j`g{XOv8l8iCN7zhX(d%+YJD2;
z%O)vZL8Yee=rd?#CWiq?mYWoG1y+~_v!Jum^v@Llu9)6PfooMJhK*i_S5041LH{+A
z!vql3rrfRIuA9^&P+DX1tb^aRrW3SMtuq~S0=Z$T?|^GJO)SbI)SI?*p{>EREDT(u
zY2IGonoRy5Vc54!Z!AP(vk5C0+(xG8Ab8Pg`j?Bo+oq-uXw}hXO8yiwcT6GU7-+l6
z<p~-)OiT)H-ZgzX7r;)F0m1qiT_#x$xNeh*>TG*V2PxjvYudjYl6|JmZuH$Vaf2|V
ze$x|rNeq~-zX^l)O+635JuqFW0yk)y{vQktnO5Xc{N<skuoDhHGJQ#9&BLZ2Xy-O!
z%A`%@m?^ph+_-7~0eCoJ@;nJLX<8Tp6HiRjsWNuTl(!g4?af;}(CA=hQtsB#oboz6
zJZRoZ*<~klKRvFT&DVzjKV;T^3%6a&vmNOEJ8WJ<DN0xKZn`ks%uA-g9Wl4p0pV`G
zp@wb`b4E9ar`hj&==L(dy%i$f=3D=drkbzNGwi6DO^@zlW{2M}2w(G85g6fda~q{U
z{LE|U<>GH%Z4V0pX4Om#DbSotuQ6MYIq@~fgqnv8FmckHEI@0xIb;sF2s7(6bVr)^
z(8DCkETKxOX!AQ%av5X(jUIlnW)}*!$C*9*U?Sc;pHj~WX3ozbiRR~(@Hfd^OSf;b
z*_sNsQ_L4;!_idpOeIK~&Ai|$Oq?>`8-?g;^Ee+e>E=~Ma52MtgHphm=6WMUvdlj7
z(3owWqGx`NxsnPi&Y0)ig59&`J72@!T(g9>nCHyeCiryTyp}?&7tEKJ0e8`yP>IGo
zv*){L%s0QX5RC<9TQ(J%7n&ty=qxgu=!`_Mx%3*8UNZa9Q@+H^TM17un|;<nq|{un
z68JLn_I`L#Zhmb823lcupc?B+^ECPx;uSNOc0g6;?NX4dX4xlj?V4Hh7hJ10Z{G*N
zb@OhDo7R}iZA+l0*4#&TN1b^-BH}Y{m|vyytT)YLMkuW}XN3XZVBX4uqmAZQwxh4r
z?EW<R+RV4J;L{!R$YJ!gn_cPU)M4IR4lQ@h%cg<rH2c%4u*>|b79;C6o9OgnkJ+Y#
z+56^|X|(<vG%u$sf5?1x0Ema?!<1_qF~8sr6OYZuC_p@FcA*8vm^t$+m>)OSI6`E?
zoYxO-(mddYz9;5@%^*|eALyBFZ>gavaj>{iB*4+KdJv5VEtRyCaI)OFiy=8%e#@r(
z!yya57T&m6_Wui|hb_@F;IOMDnsys*mZKXmv?G>RC=u;$S+9jN9+qXlK)0vm29?2h
zS$?K+6mQE)3R?SEX0(DFwYbv-am+G{N?m*{&(XQv<Cd(w(BfzDp-hy&<vls={{k$}
za3B+C@$Ci)vLw*Zf-P@Tk~_pQkO+gJmaJ*Ohgm)$H76{C_hI*>W&J1M!Y#-D1c|WZ
z{D8(tOXUAI9hT?y;G!+>#$iTdESIR<DAqFgG#cY9vlUPsZ`n-+=C%aOtgk^6Eh(?U
z;Ur7+FCfVlH#)4EVp(htl4=QI!>2S$lrQk7EHf!nc-qol52fiA=R%mzuxv?2U#2Bv
zJ^HdNva{&Rw(O;ZaE|3C3%odENj?wmtmVV)n1o!*Mv7WpuvvamfL^rB-H*;ZOFbWI
z@+}9bn!CU<<c!f5T5ftkq{#9+ZK8`U9^XUck|p>cMp0r3iHFE#%hW<NmRib3AyQ^}
z>nnIsZke)TWEGbERI^`c`H5=6uUJMX*j8nE`AxvDT5KB@gS}?yq|c00TQ1Xv^}6M$
zKyWn{pCv%lS}eUFb(ZJ?sJUTjtOvPixoCpHdW+EweGQh}U}$NyIA4PKCQD-{L~dDz
z>AM%rmWhur7cCZtB8aqF{xL%2wq;Wj`r0gsHp-3MvHYD0gYA|_fdF<|*7M+7m*tnG
zkm<I3_dNP~EU!@5xYxp<y5K&`eo9~7vpjzrO8YG)D?|n?aru~w`xe)7a1Sg=zkwUH
zXg5M~$l~xibUw5wodJJjVg8A}VM|As4Kp-i@rZ+($Cfp-Av$U~L7t9TDku~^ZjrBt
z=!B&<2}&m|{C0Tp#A2jf&XnaTS`*t_N2qGZ!Rm4njgHp%B@j7iy-uGlak3V@0A<cr
z*IsBjWPOM7{VvuKM>HO`rl(W>-PKyQ1D4#Z!ayL7Sbdjc*zVR8N2u|z{zl~vp4PY5
zfb+8cMPD88wuaMrIv=a&zfg13T5S)&G3#ymNSLqHZxBDsaqE~6I6vzcotX)+cKZSz
zXw6>-ks#{@TF?YrH)6kOn-OAtI~%@*TK}b2beOe!GdfRL|BeUZq_u)Fy5ZJyWoV4B
znrQ<TX|+#5W0X~O33C~3jirQCjP>egAhFh23D6Q}y-#Im@z&!f07$YnQe|GUwT%Kj
zDb~ed@Hf@EbRk4+Y1XS$QhUn!(s_7#+8VYCT)MT-A2J!%DSGy1TUUAmm}7k^6ccpD
zy88+w&soj1sXT9;pxW*W))va!U$i>Yb)09NOJU4>>xVRl1=e#Enk}??<e;y}8a@NK
zVrxGg0J>zeKKCtXi8Y))+<V!YN6+<A>+8!PT4r4p1iR(d<Svj3>)ATkt+dWtkAYsX
zuFC{hWxY$4GFPp)X99Q48cOfhYHOAifa_Kcg>7rB75(69t%-C~)>#86Wp=~5TnNdV
zR@><xp{?HPy%TJMwJI7ijn;kZK$@(N_Q17U);nn+&DLPrrL<VD(dMqzdV#7OZ(IMC
zgS1(fx<Kh2>ru*Hwp&N&#6ySm*e?Lwwa(cAc&GK*Y2do7e@pRGbX&t{oIO@=+uIQB
zwLU}jV13p(-+{Yl)yBf7e#`|B1J<RqnZ0lQQ4aFJI!aHNLF+pkFzg}gt4ksI(7M$T
zbMeTUN-vOMYXc>gMy%|wVE3_ghZVR{>k<kQj#+1I!^p<1a{6k=gw<0-^=FgTD9S=U
zvHn0&*ePq78qV0;?QMs)gLeOx0qA7+S2T#T-6k{ehwMtskaV&8SPbs4-EX(yg{xgp
zJe0ZF?aah<AF(sjgU#JedKxq1VfPND7Cr5bJp|`vw~8uTz3slfPwzh;yI-l|>?l47
zht6Ym-$g*FuU*G0P;=bQYXp}3><-Y9&)@D8J&OYD2LFa+pq-s7xFEYZ6#faeEBFtM
zA$BLH0~czSPb;@DJ72mtPuT5{LFA;JBjsSj?JQqGB*M;hoa)aa?cSs+$tb&XbXP^&
z&F_HH7`v_v;A8C;{*R;Uj?23G{x;0Y(yXksGE+<amX>ANGP7Zsjc4z@_ruq|?ealX
z1O!<kOO!3c!Bm#AH^>qN0TGlvMHE@`d!OH5=XLKn=Y7t-d_MPc?>Xl_&{ign@zQ;0
z#4{5A1n(51(GLoz8K;z(*)t3u3ih34uqXkS#F+AeNHQb!d5kcHu`&>Dr!ra#(Mn_F
zK7&8ZImXey(RrRxMqeC924nw+P|RdZd;)`6j0H{5&tYUffW`&J9~scN$oQuK=5rZV
z7I=9KRuUBR8EzDWDq`#xL8O?mB?F)(3?KT<lTwEJA+*XEn|V+uXM9G592Jc0*Wh*~
z!%ErODn_jwBdc~WGU<eTiE){VYHAp7(+X9~7^U~1j<H}CCh8f_c0#{_@xN+lTxOi0
zLV-p`!&{KN!npH1T)WD+vJL7@j5SoW+svq%frr-^9UCFi!uV)2c&&_`831czWPJtR
zbw<Zpm~Ce`(k1|UgK<v>-#QpJDpI-0z}t`ah~fV?NDpI<l5@Qb+a-9>$Jkm3{eDI>
z9a{$&FZ%*!kTFZi$RWnlub?%|c%lV*BaD;>Aft>hI=$XzH2J~pF@|p|!0s}H=fJzi
zc-K)5v<b#6y}0)oZLdOqlEI)!m|{3~;}0{<ILpRd%rNd#A;~P`m3N`|fbr>WI6B8j
zpm)=mxvmq$g}G)SJlw~;RSt#yOwlAn4lqwr#@&^<<}X+{$b9Ahub?q&zJwuPX2x~e
zfBG?bX2|$6r%%J+5$4}HFdxAD=Q)4|F?%Ub8_W#qfqn>c6J<d{ncREe9b*pu1j#Vw
zXY+t^oH>~c&=bsZx&s!@yxN5cieRp#@J%E$;ucy_%!jFVH=3Dq0+=z()E@f%iCCtB
z5;aN8C&r<l%)B#;xlCnlY{OvEm}`ybOlJ;Ibp9OEwj6fPGrw5?lEHjr9k4T*k1hge
z7IPQ<H<oPXN(z(ZFh##Z<O1{IA~<uAdEg_6<TAgZSYIA<D^;rHGqVwzb<8hdp85Z5
z1~Z%v9YxIZ`EaI~d5*RsCCmyZz?3rW6do^Qw$dJ?oSAYOyb7l10LE0wd^H-pD&|UO
z*sW&Tp9S_M=Es!ntzouKqqCOz9VJ-mnCr>WdS>G^L>ib|Xw7w8W<FO6W+U?mWx%d5
zKPG3c0tU<`W*8lInwbhJXSv4wa}1I#%)mV8UuXW00ql0>od$H?U?!@d(825v#&mTu
zdp+RVP3H4YgWO{Nn2pXZX2c$N-_7*=3!Obor3+@J*TFQ<0lSa+2Q4)H%-=r(8DM&L
zqjQkCnhG$7m>*Kj<1jNa9tKC4rzT)&lvzWm&D+f5FT%AkX7G!6I`1%VxS(^Kxw#eU
zcbWclH}@V>PYH_&X4o&_-Dhri9bQZ_Uswc%DW>DQT8wv^nf?ScW|(EJFh9$D<`FO-
zFymDaonsnl8|%zcQ@!3^R*olHF08@dAhM5T{|$QkS&vcd`v7Y-Maf-R<}cylLDoxD
zg5kmXq85WV#QL)xUU;&y#L)9%%|t@)Fl)#`OTRbk0iD`?Slc6D(3dqpu~k2o7p2qv
zS)Nj89AVwwh|U1kUaEUL%6jg1bOy5ingR)8l~SEUFzW~#V+mnt&Y?4uwVbNSj<M|Y
zw+~~vQvJ$tR^b{*o?xw}G+;O@)7JqL5v(XGjEZEfSp$coSb0>x9nG5Vheiy`qZwn0
zWp$^*?n%~8A*MTybu$Vg@vL7cLX^O=X&{ow3Vj=$r&vX5cyXHL8VkuYEZ#C$ILiu*
z0(25fQ~>kItn-w*N?|4Jqx$PqmX&r0X{^0eE|JcXP(<t;>k=Ih&a)P-2FYN(e-oXV
ztk0=4i}lVZ^s`xaOVG+;y-8cP3#`q4uym32C;icLSvx7zna9du!I^xPC*2t>V7>kv
z%onoW+K1s5u^9L^I_4L%MrNU3!um!4Qpz$NgiIOhzf82sS*8exR<HzdK&xc&=uUqX
zYimA+R?RBk1M{^k7mCC+u>M13ESFg_N+C6}256sfg*CnzU{_gxMPZ(rSUk%8HnZB5
zK)J@c+l!W?h1G3?iB?uV9h=)&>jp82*I6EekZET<NsGx1*1vSav4ho1#Ydg24?G}w
zlXZaNrnguv^TF$4eI^51H|xJNvpuZumt!t^SrRME_pw@KQ0QlsQTTL#b)Gh2gRGYW
z;o*>jwT5n14zqS-!iy2s>|PigW!?Q4mTt3LpMlI6%X<#3JFFI3cE(xe%dm8pr7K12
z9xF8xtqGQ?9iaDF>nI{U$=bgRyeZbPIe<;G-p_-`469%fEX=YN(Z=KfYpNLvb1cVC
zbVPM#@45}qz3jvu`0c{3{TX9Az^+^fG*|Z7S3nN3izU!-W6K-Bb7#9ztkHu#{V6)V
z*!PAZa+v)aMIOD`Ye&HIV<#`gT==sE&!TmN9V)<#2Cz@ZLGma&a~8Znc7h`X%n<ep
z+Wv;J|9A+@V{DfefQGRrC@OiJ?f3!Y1bgZwV288w;vpHqKK}zGBiZfG05pnyn%>Q5
zw&Vj0Erxw%6GUR!-L%O&$zEQ7Rveo{A^&*xLpvdvz^?ojqfTU>zD(c0Q*7zW82xE>
z-w^cAu-~9}>@53PismG-AG?KCGTZ9~prx?C`V%CTz3~+E(%ANQK+@Uot-zo89D5o4
z3D2_^odH+|`w#`FGTA{~h-9(bY3G*BK1wn39Ciln123?>k}3apk^S*A=*?v>?}0`h
zd%++`KHDb<q=23DHAo@5d<E<lvHPedpqMQRKxYX%yc({RvM&yxvy5$DiJ_IVKcde`
z1^dc3AeHz_f>*_6QDmu_jSCz2II(xq>rlgXM&u9w|BqeMh2A>0GZg{Vvww*Jvw>Y<
zgNe)RoN6dGvgc)BXjj;OhoSQ-+c5x<Cbm~2c+G6_dzi~>>`T|7-oob9!(c1ho8J32
z_I3x{zQJCX1PdMPM#>R%vYDHpca#13Qh+&bv0wDXGuOp#Zh(F_dul%BqK6$pe~MoA
zr-a?d-dqEie)gLbX&qootWX$a?|KzzL+oKQ(1zJTF+dw(3n;!l%4R+fu-ojx@8HZB
zyW;}L9k!N=c*fb=C}ww;z3Eqo+;gz6Qp#?EokgFe`|NwP37=%|@Bx`(hf?5knjJp`
z#Tj<Xbx6*#|Db2}0ekl$@aEX{wD)o5VE2pnhciXja$Gn$lwI4$@u4!Z{hU?wSvbH+
z>xW%e&NFmQKFFEw0GJ!cQ9@6WJEwRZG(0$0>1SXLar7&|^yIYFq0@`AhvH+0Ih7GG
z;mtWiS#clEub1JkFQ+>UEkBO@MOgCZj8ZJ>2xk{X!~!@GljuCk2`z$TAZNA~a~Q;_
zRl=EI&U<uP2;qG0pd})dBct0)$2ej1Q4Ql<cmu8DoUd-7b%ImyDVz!CJe`fs2#zBL
zXptP(P{2fS{-$hTEGLno8z(ty=P;#loFqB}Byt8$f_I9u^HGq~oB~<{lQ>)G%bv`!
zQ_LWR6S<PoMX8(^I%%eHHqnxn&Z(<}`x%_5Va!Y>=T|mbS)AV&!eBP%B{~D-a3(3o
zcY*UVZ2&KFrl>e2m$R9Q0rEK2w7%wZu6_%*3pmeH0KbrvMtR2~j+Jsi#hfqcoLj<q
ztb^*$N;$Wv%A<_qPi3>^oPd5{S8&2}p<l_#r$?xY!`zR#tmf>eq{b!ATlBrJ;k^D0
zc(t6QA&kC`lh*{h^_*F{64}7XH9+JtC$}EFMowlB)UR+}qX^Gcj?4+XCQc%5BRS?b
zb7XWrxyJclBbY6m6|}u-<s70P`D^3+Ap`F^XU+=J&grA)>IR1&1>Q|gVHAdTi}MzJ
z8@o6+Rsyt}llDDG4`(bG-uH6C>2%b`@#LYipR<8NqywBU`r+sxXOzzFjv>yQ`$2~}
z>mOj)Bb<(%&=}>!mBHcLoPPpfcZ~C?8J6yF+7YmwKhBw;(Cl5#65`$CT%$#Ig46Rm
zK<{&2mqLA#GZ_HMDbA%t@TNH?6QE}}d+!2emh<utfPTO!rdqAN4(^Fgh`MkuQNijy
z?%cb;cIE!oje#EIj%)>}8`t+ZG~Br_ZvwUlx8e+Vhq&x}Fz?Bg)5gY&`#9Be9p+Zj
z3CNrK{x~{)xSXdT;>-1=QWZb$54-VK_UC@}FMK+}^;-)=0bIw<%Md-v&8It!f!yNX
zL4vq`bPx*W9u<IuaC>`UFpMkw5$2C`4W0l!!TpCGh;Z(UbViHdnknKE$<1Aifktud
z$eGQL=DtLCqGGt)D0~ykoqQbwJc)6_nK-U5Ri(spC62eyo4}1(3;jgy^#G7l+z{G^
zp633v0WxQ}K}i5T%WZlD=99RkU%<m;ZXd;VQn;0mfS1Zmrp<dA_f2Prq;tLFp?8jp
z<s6?QZuWhMWN>>U(3#0SNrlK+TqgYqv$-K!2NZL-_aA}X3*4bV$Xw*kZ-K+P+(J4S
z<Z;_6+?>yy@<C?-cfuW{kbBw)m?CcJI0jnGjZJ}M33u{4SSsZv<e^o@m6ZdmoLh4P
z&=uTYeg?0a`xJ$AYq=lg0<(_0<YUVJ)pHf}1!&-&(L(Vu_udYeXyktHgw88ma}(y`
zDmUyUbT)D82H<xyH;?jKtz0?nVcNJ`sp{xDmqD4;c5VTk!EbP1r2s|;x0CX$om}zH
z5V^^HgA!=BxOMmNhw0)b;ifHq|BUNN-=jY6545f8=X(DDjUn!LR17!F9rcI9Bis^N
zTE@7qegYGBxJC2}MC06nZ4jB@eoJ?;?sHjB17(t1J_-+KxZ)D<X1QK3f;`}Ev|<o@
zdDVQNxbPNuz?pr#flf#|TzQ+WVlEHzBKKj2+<2Q0qjiY4`3{`%<dxlms25N4Bn<lS
zl)-@U<t<+dgMPf~N$>)Aqg07_l(%6iumgFUXtfRD9k7BI$}1iP*fCzDJID!MZ4Nra
zc`J59A%f@l9+J@x-U>=R$MBLUgB{CzumGco=WS?0D}fiT1WDwXsWA5pPc#cJ&hozS
zgWpNKm+6R^%1ikbKBe(itprLsFJ~PTGI*{Fz{}+Aeg`Crw`Yu=E?!O{^e*yNQAQ`1
zXAXxm1w6;4R5S~DZ&1d*h}TA2zEa-H6kadmy%q{*%6WhO{}l;dIfd{Vc|-JZyTaQ;
ztNc~o^gennc!_(V*UUQ~1d&$WRr-<JHs1Or5V_9V;{}Cwo(m;PZt$L^)MN+m`&PK!
z$@|&i4|<b#o;DG;cy5`{@8bROH_UhQ(p}N&;T@s8Rv#~ee%`X5H)Mh2055JEU<P^N
zy8$}Hd)o`c9^qv^i$RR?f~cP3HqTfH=rP{pbtv57EwiC>oOf#l^d@+oYLNT9rg6%@
zPx4OehyDyNBL$+fJcj}XAMk2uSLw{3sfXfTzApt7T=<@pQ`yINrZmxh{`ZtdbmjLx
z1d)UM9rU4h;~%6;jPCsXsQ~lfze|C!L;UL$i}K_P0ztg^TUJB;FyE@D`cH5Ei${R%
z!+-e$c;U<c;{(X}@y9=bC4c@pK46aU_bfzb0N=F}t{vt3CBtqYKVAhA#BZVOXE6Vp
zm%t0*GxkF=jNd@d%yIs=jWB<Lzm^h}k^JQpevRS_mOw9>U->4ze<%4nzk#JVenJrR
z<N1r7fOd-SHI7l7=HI7FlxO%~d;pkae*6x=r0`oK0h7v?P?GH&|Iaq)o#&^036u=}
zAGG>p^UJA5Gl&0WI211M18X3X$3JonKIQY@W@7RS_-FsY$Q;Fd)(K#j@bA%kU&>!_
z38H2E|6Ya{<^02o&{@F`qW8Cwe}#^7Rs2tG!~JUhu5eho#9#b2L~8g=+kjTf&)~v~
zdVUf`ts3}V3!!(J|39jTXyj)+1#*S|BpZ@f`EnifnjCzMD@3pH&rp!Dg&$63q^<m|
z0(jBJucP$Ib^aR_P;BSFNk_FC{MPL--@!liIh^U_?@Gr&Z}MO0g2F9+=LvLn@i%yZ
z^zz?*1*DH(#RFzP{~s=fJ;Z;DcF)87+&*-U@E!l1K<_C3U)mPl=C{5HGRFUb%9ZZ$
z-+U7?<NVrbcyX8i{CDWQ$KUq?6ejrN6g9rjpQ6CaB>yuit()SnFrzii-~I^f&hY<w
z05Z$p6%X$p@MD}o=J@NVz{gpzP>w<D6%;ydfVv1C_5gFAVB0fb?ia+-QR09AaWy>M
z0`=429TWsF0-Bp(<pEf77mUjw=^@D44#`6Ty+2Sq1^3AdF9B;SBo7Nt(MQc&!0`po
zN6=6O*L(%~#UOry&u;?LUtqpY@81!@PZyvOAQ+)?mZO5y7{CMyim8G!NWhqbNU%Wr
z5+)%;u=zCXh6;2P>^mk<Q}s`nV209D#|676|9(O+LGNw2z>jW+M+oM=120m**$vDn
zfu2sb(SpV#v|<E@zoh!JSV55$CQb?p-hhcX!A*+N#|!rTgg<P8;Fb^u69tRtKyykE
z-iFT8g1Jq=J|oyqmoLu>R#1^il3<KJ^vQx{?*S!6&^HE!RDpqxTxo)Zhk$Zk&_N%U
z3<2XWkW9fDTw8R^&l0>xi*B|cixO}-g1^Yq3j#cjSgi%CXqT2NFwl#aCpcOR$$Y^o
z7x-Hs7|8%=p+HX2!6E_sQHT@^UZHx95<%DqI!gtc&cl3}AeLf6<$|O+Sf~)>tbksn
zVB-Ps994oHEQnSM4kv?L5_o<O{TjhnGT5yZq|+7bI>Ai}7}X0tqCaJW;Kq*_+GW8{
zbPj729K3?gD*_fJ9Ip!godK^&@D)85&4Tyd1MiwZwiaM5f*K0-w+cS|9}Kk#EN<}W
zhC^`C2{Ijmh4egk3LZa(q1_bhor26Q!7E`f(IsF|;=Wrj^e*&!1R)fq>lGwF1zw-P
z<O0clf%G^!2L#RZbPo!)?Z!Zd1Q+PW!?2)=!c`-JY09^Z3T8I~<+k8acSw#291R@!
zeMhjJu4Il27N%iN?h4|lYW|*J&jDym2<*4u;eEl!LugG3!YP+JC74IYn`yxh7Fe1Q
zj0vDOEBIh5KpzMuUI&>Icu>8MvvBGg7~CsdaRgK1BK!`2^!fXQ4Gbvk7tT0nzi>cU
zLIn=4LU|WPaZvbtJ$!N#4%6P&UHF_oS{}kP8t5Mqrc^-RQ+OsD3SL5eAS@jguBD<u
zZ{b5<pwmbAJ93TleTCa7SM4W^8G(quuw^TTbVMjkhDd<0VG}Tq3cEk2ddfgy8l888
zgaN1FX|S;2W6VW}a6kqZLxqZC5IH97^MHvk;Z{nb9v7aV*v<)|oXSYUg@03RcZ4vV
zex)l?xQl^Sl(6tyh(rrNd<-N;c!P?TVugQ?0qmsEeGyO+gz?|g`7crU)<@_)C2YgB
zllf<bKR$tBCkfYYfWyhc1rs0{LZ29jWD9Rm{4+;5@gzDg2%pLYxhQ;?0@Jxdzm*_)
z!j8A#cD}HYV#o!;J8MA-h4bowSuEsI`CEywssbLC3fH2fz%jo}IPW3!mJ2`Z!F*K+
zFVIz%D&g1^I;(|ldoaRF!rv=kzDDRqcS&l6!c%a+PWZb8q+Xanxs3*4$9@d-vasbh
zbT$fie+?5?gb!Sya8>vL<-wbTb*tfTv+&WS0J|o%d4uO@5$<KeM62*YIoxj(E~66f
z>%z6;XtfJR=&`&ZJaiJE9l}c#gYFdO(;xPxF#1#I-x9uh29~;neA+s73p4hi)gz1v
zhhDF6oQj<LguQff8WirB0OpYJejFr+g{xaYMjXP%Sok(7?4#iGZQ;~I_#2K12Pr*v
zN4W1{jA>lxPJy+%!sT@N>z?on9uy{oix$GC`@*_+(V7%;S~0XKVbmrlObc1hqH{**
z){o9vp_30RJrJ_pLFR-@NZnafvlI6Ai5&Tq@YpZ<-3Yq}M0@Eg?kd{#G?)iPPCYQ;
zCSp*0+g)^z7B~-4%qJMdAyNN2Sn?F5Q%=Q8luHSz!=hzWQ{XMyO>er7Xyi5&d_~)r
zLETSucM5v`qC;YkBcj_>0vsSJb=V<uRFpz*N1(`|g<_ECtB;`(EZR)Rln_yAI6y;1
zrSykACbArYr7+Px3fYH?&WFJ52+<lF^dd!fx&am=+VML`tmv~Zp>R@kC>4{JAbOAh
zkwnpBO6Z*uCHDaOtmtwRegBd~uVtf|EPCu1#*`*{jW*2bqGu8?-RDH-CSfo`)VL6q
zGDW6E(9aTi{{$1+A~78kazv_+fpSq)yAr%yQ3PFu&J*3IBGv-Y&mB-N6fJrSm_?#L
z=+9d$+D#=gC8Fz_=>M;jiC(>eX1VBT6CAD(eH{k7Riah&`&`wcxi_JBNhG0-XN@S}
zXMom<VkkFQFUqA0H4UPfUm$r|#BGK5jiT2mb$mq>MnT}Kq9tFU^O{IRMJ+9&!@t9|
zR?$K_akYsgFzc9qU9^vmFzuqp=|plv^jkLmKpmn-pT`J0MNYJ!_ltg_t=oX;5em2t
zifSp3FeC~dfZnj^XF8aVimp)x>$WJAF7AzqLeF8K<DwM$>7fbH545YhFFHh@=1I{J
ziZ)M)O0vOoOp7+219L{SAOW7vir5dq`~%VL37D7@by78`v-tJ(AbZ7syZ{Xs@nQ~I
zuHqB)jXEgSet}LmaR)sm?&8H00P_&X90tlE@xPSB^c2542D@J3K#G|k7T-(+w7*!p
z0_2E8{Od~?Xn=TvF60~)D=1wXD1N9Fph4n26&OXZIFn8?A>vOcr5Y+;xeGAi;w7mt
z5g~4SA0$$oaS?W-#GUlrjTZlX3D_~>8rlWNirZRY;iUMI8YE6!dINuo(_%hlR?dhW
ziz$_KR{R{5NhOIleGc=<;(FSnrijZ!Ad@QgErnv5*rN-e>EaEKz+i?r=y70YiVssf
zFiZUIIq<T@S(|~9BUWq#$^|j|dvsnD&m4qguGlFCV0q#VH=vL&{&gcz3dC#w|Mw>f
z#Tj?eTP6;o2ywaiGd}by#GFL9Rw@4Q35>T&T&V|IwYZ8_rc2_U8O%(L*y(YA){3hy
z0j*J-zZRCRh%Ypt^Qu@*`@kmgmWMIkW-)shnAgNHH{fB5*oAVEt>Sa#4wz^YKS9Z|
zPO+ZOYB$A~DQA64?BWTuF7b<1Al>4=pFn!VE>t(yD{hd3^og(cz(l`TO=q+b@j3-M
zN5$7Emw8*fA`+Iy#90)cyCaUc3%AF`YTDu66~F!iB=3nId4u+!6XKQhahwvr^#ppS
z#jMltX-3>l+qzkCB^?SMi2L4z$efr{2{dQPGKyI4l?>BP%0*K5EJXH6{v!tVe#vKl
zgB*}dMnl9yQXGZWA<5=W=y^)=H$&1(Qc01+!;+(;l>hUVFlq7gkp%d_VPA>=b<BmI
zgh7SKfs*mF7<Q0EO3!StWbH|yg-9ZTp%5zRb%yz4k`E~s6()I04)x=bkC`xWLh{Tu
z3?f?cS{oE%B*XOR#Y%eU(K{&#qPSd~<Y+t89r2P6G@uC*MJr$uC7;u>b4qgcCeV^4
z8;tNGMY5IxW2usfA#|om7PJ97UD7uVOXnml>!EO7q7VZmL$c=}urnpX6d25rn9o4{
zg5=r&S{Ehv{|jEOWYYi?@+4y?pq}rL+;9V0fn;$eOcY9%uL3EO_|mTf7E2aV`oBaX
zxC^_bk`+{sTqRjXv5IQR&KAI2lE^DDK{XPY0+wne>nmZYPEtro-+IYrIZQN2R%8LQ
zN#a4@zh+4brP!}Yq*kD`NE~5Gh_*_8_yK5bk{|DYd0k?l?OD5IFXcpTN#qnu?vf<D
z0@5uBiKYipqM~coy^_IHfc8n4v<K;zEH8xmfaE+C-;PT5q~I@kTXLEro@0{l=q|_|
ziG^|t;}QlBX75TG9L{j#o@9o0eiM>+YXCDPsi8%CTC#5=$c*GoN)F6QVkxfoKr-|d
zCSgwU1)U!cN+%A&gqw760@U55YRVXRNaKG6IV8Q^40TWGCL=_=q}f!sa#%WY4U*o{
zkD_77N2<O`@lRjr;}o>>ldhsFNq_0q6!>;T8bp!d0O@V|C<aPrf&m&N-TF6Rf~D`!
z?a2`7VjI*$rGL{SA11A#(&OXOPd~$uPDqEJfMkS}pAD2q=}r|eqoj!xy^WUg=;#w8
z{q9NHf5u50mjgRq`bR&Q3DQ*h>?cYUCV-xj?r}lqX=y5L-OflGZUODAG|C43B<ZHt
zFp3mu9PJoWrJwx{k|zCf4fN8b%fdm<Nz>PZoR^x0Fo;a)H&p7JCH>n1^=#=n1a%zq
zbEGm2urElRD6Vi(I=2n;oGZOk1)uVyRhPlbmxj|uu0ZPXCnmp8%BHhrk#r4J7!*rA
z=y@)Y{zzxTQfVW7GRmZjDAHOkjiZBZh4fDf(pO6J+96UU9ZQ8swe-bz;JxFLbcTKa
zqDH#A57@QRH(p0?gVd=G4quj*Qr4$Y>h>adSEMUF(7GzUaTB~I>Gr2FifhtA+8nk>
zH`3mxRjRoU(kA`Sau~cW4Wk=u?a~I?D0fH=be!sx_Pqg-o6^A!w7MM9KyRRROC$N{
z?U9yJP^VY=&n;m0Nrw`_>z6vbFp2@`zx30HL(;_g;0;UvZo*(jq@CU{KPr{evT<8l
z^9MxkNJG+qGA_MKcO33Y_Xj}ap7i9iFgPJirN8}sY0gqi!nD-!(+VigNPqneinG#g
znuG_^8al$vN%tRszO(G#4QTC^Epdf2F0#q}P}nC+rs(m0SrdKn4#;f5;JL~kDF^SM
z%xftW++<HC!)<rj5(+1J$bu-)dPvquRREr{C$?f{yktimJy1L>J4<mNZ`lYXn|)-T
zQc0e#towZsKbb=T7=M}mH#mGm=63@o0%WXjVdAK4>^MLJWfQNUGe~At0VP<rbQIVj
zvXUH-P}!M>A$d$zZv#r0Y-S6{ahbaZ^iIecG!Dpw%gQ!mP9kIn55q*HZ2D`oqGSc0
za3)&zDLt$)vK2evXsm1l#h_2hwtfZ41X;whP*0Stp%dFFSuYdVr)5uj0{e_?FCBEx
z$|e>;GD)`KJB%e+)_xEuDKaf>?owsUX{vuolZn5FXu2%8AIx*I6O<%BFLQbs8W}Pd
z+VW+}m}X2{mQ2(Mv}{@B78uNt`P~G}1=%xP@Gi<u*&&%LYoQ}ko@@pE?eb--=y*~f
ztECE#LfNAaAXy|kN}-2h*;_~H_diQy#{!{PDr^24GG(#``niH~*)Z+yDr8Nxlvc`K
zqXoT6Hu)cjRLfdc!F;W3$wrVm+4u%{UoV?^93l;}_n!v2EPID?F^#hHT#zfW#guNn
zD*L1ZhMHsoigY&1d>+6H$2Hj}&)~1tB8&F|vsJco88q5t&a~!Vm$lM9uwAxu1qO3N
zRzu(24%zz8px-Go?S{flS&11Vyd^sq1h>0n=l(!vw@f<^l0CAh4DkA8jx@9eWap`T
zW>EIkT8IqEHvSFFVTUXx5|&0~+dqW<ZQ0jUxj80V^%qRsku8|Q2*+j5b%S?Tmh&E9
zCS)IvLI1w&S4uWd%Dj3ZG9}Yc1Y%nDg$ZCYvWV9p@<6uI7rZ%H$Tz@rmPga&9vAse
zCVbi_Pu+^ve!1gY+F>7%x6y?*SNUbiZMew?@<80>-5GG$L*DrrCgG6Wv>ZNp$~V$o
zJ1_a%Y3O^)KM_O3M;`PR4EoAzpF*df+(<hEfBC9uU>=b_N-?aX@~ad!3Y5n^3SN->
zZK{SjCST{E<a(HVY#Vxy%iW^k+X;EeCXjG>K><J`<qy-bH%i{z4(w=oWeLz?<g0IB
z^s#aw)hwQrr%^R%oO}^|oD$@9^i58bznle>Q}WDlsGpYC-^U=%$R9Zd^(1-wLZ~Op
z{ihsIOpzDSKvU(_RH~gO_mE>s(&hKVp?FUI167!3$^~?Y&XS8Md7CYFy$<~x`R=vQ
zyCDCVN;h)lv!7!udGdl~Ao=pPztCAAZ+Z;|3+1mp3g{yF^ab!r<hAssmdc;{ihlpP
zOm0g-vs`|eN?R-B&n$z%N_nvX`qlE?RL62jewRx4Yvi-E2-V5or&X_B-Z2SB8{{IY
zU%4!2Q5>UDzOoywtMdHwAWiZKN+dVS-FiT-$^S>^zZQ8g?U!5Sf1}C?=Rf(nT41-!
zT^<7ShI}i<z&hmL(7~cpe&<Vw-jvUy$Yqy2d<op|mdC9DT8})G;&KD>%1@y;DEAnH
z-jKYXc9X;M%L|||A}_v#Vc(XY%>vk%+?fiZ?#RdZAmj4De}Lk+EB|*ln)l=Zv~`=1
zFQ7g3q<mxz20A6LdmFAz%adLQnUP2Si_Tg3D!Q66C%>@?2Avg>tMG8IqJ=7mT@)u@
zL~Ebo5xV8QU$OH4>$nu{baBW{vHdtKxGU;>A>yHUp0*i>9E#N&K|K{;)0x;y(K85{
z!-`k7fp{yJPh%853SA<2zKTJ55d9R}XkqkM+;79^k0@%2AQ_<e|9@nDRB^llt_3PC
zQ?+i8;+LE7DOj<Z3X?(<Syb;Ds_<F{d&d+nRH7B8a9p%wOve?S%VFY#Vjtzf!xc5o
zU`8ljqB8qPg_OR#QHsKHkZ47C4X|Sr^C%AxtH`H{my?QrUxbM`g;@cGc*Vjsa5O>D
z`Zl~zRHRZJ*C~abUjNgIKKhBXGm3e%l{l+tb5N2yNpYbUipdJM?a)Y3T>b-~sfxJ|
zAeyG|{t0O36>BIrpP@+j0g{=DaC*0M6n|3|<$~f8{RuBBBve?DuV9yAW(pMRs7R|&
z(L!7562%Af<d!NzZveAQaViE1l?uya6#uMJy!I(fR4df9;jLBFyoXkuVoVABdWAg|
zGt;Ojj0MaU1&cm1R~7DGLjRhgd>=$w6yMN~;It~<e-9$<3O=R0Zzw)^4`3aN6_nTQ
zRFqSi=cYpOFznq@oToirm!j?oiobL#DrwKvqX;PhOs^u#11|O{emxJF0mWiUh72l#
z>DPjW6lMyZ4J)ovbbdtf4}CIjD_$}{Z%pyjd|0}p_?VvjaYfx0VBS^i?1wY=6if|x
z6N;=I0K2bn`5K**in%j%{+m+d{})b8D|#;hbVhNHp7mM9(jx$UpjcN8(K*FGR`8sa
zZ~PDD_bLlN1e%Ld*8-6P%5#1&=&Iz<S@@tby9>lk`S>`@yDNX!q2-}GW{2b<<p*hy
z^i=-vE5Hsbf2K{E!&_NNTQ47FhX9s*m5)3Irk^s8USogd9!k3$Q68)Y2~g(J3m>F(
z+YVl^GMsiaA<At{PzY0IJb=h?rO%fb%L(P@RHYcMd^Hff2&E4_B~i-AX_${z&Qho{
zMwzn*yjX{F_!BTsD&M9LeVlUQI9l<_=Jznd1Z6%IsU#{NrNjFvWh1Rj>B<aRrOzqv
z?*Z?;@;M1QGn5UK9LQAGe+iT<r4yAbXDdHl1WP%}J4SR~P@a1Pt&7UDbdbqazCsmL
zc}hofAYk&99u&qYP`>jp{-TA-W3<{9DN~;YXtC1E4dzRfA`wJNm5X11Vwtj)$`i|#
zuk^y13grZ4I4hOYgD_F0tR96zwbH>r=OyJ|RG(C%bcupwtunO^ops8td`Q+S=Q*ed
zuu-`>0nIDQyR<@GRTht-^O|x4Eha6>cu#1wDjN&X*``dTJl=I>57j5NE5CRMmO7QG
z{qX6gawXMh-cs@gK)RIY??SR$*?Ju6J<6A9E_#(o^d0I`I+cO+E2H0`_~(GKiC(8c
zrJbslhLoRg!5?o}S@i&|5oJR=U`CYzyC8X6SwxYoG3Cc60D4Es{}Xn{mCMo~au-8`
zGxwA$=wD?{C`%~)cwgyG`}|4eBFaEdDQibTrj`2@fSyqv`XAkYm{tBfjp=@%%wLZY
z&MAAS48~c-(LjH%>fsvr?V?JdcWj^P08Pn$)#Yn2ctG_cy=tzig_W>-Q1$CBbh@cJ
z=;d-({qYIxdZ<{}Vd;?S8!vQvs+t?n>7~k`?ag6TB90!8`M#>xDWvSD3N%2*Uv-l1
z+#FGLN5P8#RS)ISkE$-|fgPyIyA8!4m3co%u<GCcf`q8vnT1}csx%D#9#f@A(F#+2
z5(nOK)%6INKcPBA8OCtcZ&ZU6p?aM@)RC$Wsp`NHrIMGyM6{|b3<hIVAFY6;ld3Hg
z6^T<_qcuNXrK*8Qf@<b(C?=|&uwfEUt3Idi^%+%A5fsj<eCh0-qB=wcD5<IvTFTN?
z@6aDKU6t}1TIW;?%`kXg#iit0hRQesy-bJdxE7#Us`?TrW~&ZJp^>Bdn69Z^P$j&D
z)<xCsry!cE+PVn_^Hj0TFrTm5K>^nS)i+duRjB%)8?7SMr4Wp;SoL;3oGDRd?*l1S
z8R)ZLrn*4^s&bV)9g-EQ-DXHusvLQd@TN)?d=4_zs_)BS;*yHz2fH<@cj=H-tNM_x
znboOkZa|}66-oQ;230^4BrmJ{=(<*;Y9Ey;HK|Te#HCr4|0N`^sTNRZr$yz+M`x?*
z-&Bw`)j0&+=3iGmLhE_E>J!I$^xjadp$$rh>R-BM)~Q;^z<k|OIWNG_x>PN5(CAjB
zM}s%4ioOUkqS}t!)%;Oa8U<HwtFGjrHKy`<9(M1jK97OOxay~2jQ6f;c@e<wsm^Z&
znNa!BGC8So(3Q6-)nX3CU#3-0WTSUR)kO!XS=FZ$MS7rGvJlvFstMXC>{VCN(Z@yo
z&St>uQ$IToov!MkE?7FKerpWGO`Y)xX2xATxd<X2>Z5cQ<d8bx8eH>KGb8W^^-??0
z!*W>tJ{^g@)!bmJfALl4Q7N#W`pXKq@2{S!2RWh^T!Th{dgd~)kE)sH028QAUyoL>
zdIe<zL)3@p2@X|1+5t<))Qj|RJ52o;Jqah&&&Fcb!quDd;C7_?%1;o9QlC7E&S-Tp
zl{24IzrBs#zc}^X)liIAmr$@GMO}Ls&ZMdvRzWdMoxB)hN>}fooXR;h<1Fl+S2Jm0
z%~JpF3TLv_P81Q#QMWt+4=<=q+aP&S{U_y>a@AcF7R*yG`345_)jv}4P=UIv3l<91
z1-qc&C{izNgWY2F&?0D*s(qh=Mwxnn9N6XRFDbBHq4uSqccuEHNJw5%XHYt!M!kx@
zhPCQrXV9ushkpdLdi5dt?l!2;Q*8CJ`UquD8r2?OK<|qBD#hils_R_P*`&To*BF`|
z>cBV*=9+rb?;tJeH&>yzReh`tF1D$ktc2oq_3Q6|w5u0RLH~w&4TWer)VXh>)v5N0
zg{7P7Z)vM|OYJO%dY9Vs7)*4lKco|Gk6O1B(7oylEzs*ze?q)|brb#8$$;ANIjtLm
z>aa2lW=L%e#Y7FOC%e!&qTY}KGOEr&hG+h5b$cFQ#?+f8pm;~Ep#aLbde2IjzpFM6
zp><FFIDOS7)KUS!?yHZ!h|WoM#2px%QoBn5Hm%;W6DTw46^o%atNz>J4w(n)g*9N#
zsW(yZ%vs|>7qVS6MHI$4pmC*BovUUw{h1GH9{dgwH;oI${M<DnI&gYu<~<7DAx%yl
z6g)L2D2nQ(8El3#hc!>o;^(dTAPg3KG+k5#>#KQ%e&NYab5cX!KYz`dm(dK>tS^P#
zV;c8HV25d}UxRmC<9`;NCp2H319rHk={q<Rp~<B`Wu)dF-PefHcw9p(TI2Nw^kOvo
zXnzx{d5K>ClN$CqsK;sIsJtRx^Dh$$37WGM5Kq*Y{-pcwr!=+6V4l|ObB2p&G*wh!
zbXId92ck)uIr_RJYXmZAq-e4~LT9RG%VA)rX%6jyhv}M!Y0*5VSuqUt^O{|M!I=!r
zj{l&QshJssLY5|-B(pU~odBJqdD;eYLGu?@aL4?MnweS5P_E_$14Q#QL-dEu*Z5PF
zR)NNy(kF$QK{_84X<Q``Db{Q{0-s7WZtp^}O!Mz7o~v?AC)EH}Xx>~8yOo;jOW<LZ
z=4bM^TJzf%P`IQ?eF<PS8WYuQ)M_{_u;8fEJoYVUy+%Mez6Q-<`tDxV{7d19tD66=
z0k28pL}7_$%_<7*UemlqXWACck`A<5HKv>JqD^yV1N5$I{3!s^uIUPb7dJFpK81RR
zW+SDZJ2l-y@bIQ)u{WS^X^I{KN|!_9aS$-wnp8UT^k`nEpBL)YoT2BUPji0>{O;G3
z(*|Kcvt<i-gPINsr44CrQA~DN(?W-i5seFFT}L&s6tuprS)oU3Ow&Ly$~&6<^u~;9
zxU?6)tKq!^FYal6+X^zFalA(LKKC`JY3nwrDXE3sDb1xHL8dh(Dx{pztf$oEtmdKT
zpz%QSKGg-!X*ON~&siHyLEwGbj3g-R*UF-RazI<L8&l$@4W)V?ckNU-^gOgHABLWn
zc7_ddSR3mF@4dC-j;|r(qeZM9uZ7l^O1}KG)pU;Y*KXW}))DRhY#;&J#k3zgs!gWt
zV4${nJz7E9^3Na{tUX56x*^(dN*si0f2GC#n6^3{&|%sN+R-1^hEwS8g!XnPI>WV}
zKL*SQ?eGh9{)^Q1)5;d5-Ay09Xze%iKw`8PD8m`6y;^`Voz(8U2+%lf0Np!G)J}Z_
zFHUJ^D6oB6yP7hiNm@SL8BNxfP{m7%_6rLArD~tdM=MR+_9HOUwfRfXc~1M{^KkUM
z*8fG?e`aWpA3<-X_Mir6S=y-gfSs-Vu?nC$+Mc)2x}fc$3;P$fRdlA!)pF<@mZ$Bd
zWMsbfMI-DMXifAZD}`F0ZeSN_pQj6!#o8tGt4JkUw={H?YKxzOGiBO8U&RAauKgGZ
z2gm#ht(2DON^PP8q)Ph-%|*5L&=Kfg(ms^{yLH<4=p0tBeMAm}4O(73%wN_npqqD%
z+61bvxT3vmhKXivY$yhCO&j_wI$N|k*=Y4?CG=A|{o3RoVSYf%rqJr3_CW-o9Yfll
zR7}mV_IcWYjc9|Zpm9{YAq|SRwc{+97}GAHILICCiaPMdwNKDGcURl)3lsOW1C#}s
z(C%)4_xJJW!NW;yKAn}Ow413+cUn7<k0H%yx6_AUR$CYkJ!jox&Oq7g(7k;Mc3pI;
zP$=%x9SB12e%+o!AP00E)6j6$Ej2;ppw2*90XN+X+kow^D_e_}hi-j2Tsx#YO^G2-
z-HUyY^wRzO8o&<gZqusgty}OoM0|A4^#1tjUK@a;e!59op!{`?e<gr9qI->wHvzgk
zwP+pHJx^JbKwT?c2?^58P!U70?({sE2+@U7^eR-hO9Yr>x?yj$!gO;~33XieA5Z9=
z&>f>?GF&$;0A_@)l8w$t-FkYSqI6N;p%tww<zd!hbe}u6VlrZN9`sc^sr$1Jf0;Pl
zv%6p^UKi32y9v6#9s+iv&h=sFpVE!fKK-<=gd#O(bYIcxaaNc8C_s~R8}49cl66HC
z2~W{|_Y_E~?k@@irs<Y#hokAbRVN^MPWSMa06VXXt8)M*LwEOmSjyBbEe3X$ZuA&P
zwyt*{?B?hi=mT~^C;I~W7j<Qap^&Tl8nvnO^K=qgO7nI8?*p_zH$rtcg}Qz^auw->
zbh0hh?FhyIOLW(s0%oZ$iz*n)bStUYw_MlKO!prubSsxZqf+Obf!-?JN=g@1>uylA
zyH+Pcl3;$F&YFx?z3xA>hiT9SJOqWyIy0@rjk^DAgcnzI#T(IiRkzaz<89J)(Itas
z-8`xvyQbSk8TS^QS28+Vb&Ea*Seq`8N8i8ey4<h9?9io7g4wCdq$KK1-RNSV-O?pe
z;;>8i%JcBMTh~KD`aa!qs)*><J--cqrUBh~4|p-GJ4|QG5uFD`dPa4ha>2W!Yo@n&
zTvzoHT6c9`b~tlS7t#xVCv=7Hz){D2-J?s<oYYl019VEay$8Nc>t0R)%#7{`)uhhq
z?mY+B9_ZW>pfRU&c^YWW`scp__FnyS6m@pdm($j3pMFsaI```(-{G%yQ2!bQAl>wD
zXF<<hzl^ppp87i@@WM;K1KH2{haLLwcR}A<zc~qtKKc`<q2a3^ya9uL`tSl+^4EVy
zr;Q`}(=WoA0R4Iq^pEP@Y0DO<-$kM5AiZogc)@zcb%2KGyRV}as!w<WJ{{Bh-34@*
zp0f#h;rcT?ScuTO(GnV|cQ6bXXpBCIp8Qxndp^iXebquR<MeO*0oUU7#>df0&__|B
zYodONex>A;K7$KOr}eM8U`%K9ef{8_)ellVa*}?UY9NyJ1)srEivB%1$fW9zeFR>b
zem^b!>H0@rhEM18*Br5MF;o9j1(;d-Wjit6Z2d_(z!m5}*@2-I>Yt!wN|8R9>hy~B
zPd$Oo5`8}H6H4_jH$bmUZ_vVExnB4V^eXi2o8U~P{;g@Ws`N)k!K>D{yMtWP_p3l^
z^g(-Js8(OIiPro&{gdgyuGdFLf;8x(sPyrQewbqJSM>uefN9e2xQNbX{VSAOxu)Ml
z&rXZJ>k3G#e%aITsZB5X5xndAAs?9U(C=>q>C_uSFbOyH;pyPr(l^mjt4qJ|B|vxU
zU#_G4Ly!JLN{aOAE8-#3r{^yK=%D@~TFHm>Rt^R_toNZ5#fZMI0hUJfnXf|OwqDCa
z=a}ATfNOX3vKkm1*LTqM`3ZfE2RiTTwVOdE^|Q2;P3h%Sojk3-OfUM3UYSAlpR@W@
z`oZ7_`d=NeJEsrhK-9&sya9^)45Jj=*>8Bd7v!K}nF%~M!=sNw(%tYqRcv}1zL<ie
zUWTtJQF++#q7*G(L;V4?{0xnK7?Qu?^9%6lsNvPezza0IML)n2WcZjOe~wT?CY^GQ
z8BEW?w=jdj6+??Qyr6(ajNx22TCoQ9d9+R%*p$+VGc=unzww6R5uha)-nGJ~M8n;u
zVDOZo@*+A<8$9Tsd&c1X3Cy20SXV+M$*}b!h$I`H4#VhE46hEse5%7RUIO!JhOa1M
zlWw^7Ar#LUdVfXhyuq{y1~Uv>FT#ALVZ{;fvJC%FU2wJ`T?^10!;aU`x?t#k9SRo>
zAG*WeT!V~Ap5fDVP{=nd4THah26GHrMTVUFP$)LIJ_#>M436&>!>Llk8CovO3{SbC
zx7^@64*d#4*lNsrrGa|@qo^|EQy{V0aQYzhFBzs@gKIU0sWs@VHEjO@*mZ_C*-)=H
zd|-h>gW)kM0=jIt@h{9@HT=_v&L)F5g~^%?4^!m6)o{x}H`&?@y;P@k-7u#{Z-=3b
zw$_~nH!5$uX=txT>y}~HX0*Bt3BG{oHq=r4rq3YV4AO6KqGS4i;ls6<r(we`3i*#1
z;)T!~HGHTC@3vtfl`xGN5>|kB$8awUo%amS9;5vGgrVRSko$&X6vv!4uxJ}QW7zTr
zL}v}_C=BXsoHV1g*I3U2&&AkXh%p^7dOeO#SL4#pfPK*TUME^^#zBfVxf@HPAmU*x
z_6G4azIzWmKjSE+(fy6{DTsT-$e*D5?*Yc|>9Ia)TuuAlKx6zHnBXAeZ(m|&gN;k?
zKs3bYs00Z$nwDVpju{hT(F!v*AA~c<jV>QT?}V}974X81Z*t*GgmIw<NTks>571G@
zY^wK(HvU4vpcrGb2_)9I`!kBaoHVvKgBfQuQ*<%j_|fZNCKy*8h8Ky(v{qO;Wptm9
zc|L7?_AyvGW3=X=^Q`g5rNB-yzPk={nQZ)RA@ov=Tr+s7#=rd0N;4jyr!(DHM!!OO
z&KTW<)_LPgc>v2WzV8b#N2c*V@fc{9aYrc3XB)3)pf|^uR0aJDMm<GpFB+H7#j;%E
zFAt-YXY?)yOujLcgU$luI1R1PI8O1CBIEZ~w2F--v|5%J^=@dD8XJOOu*`U#@}%X)
zKa0^>Vf6kMos|w_6_rv{8Rs2^-_^!tlw7}LETF(?jd73)v1*Ncf3zBm`zhaY*?1=z
z*p0@|=uK}jj(elC*%-YO<eG7~18%n&MQ;P;y7B#gq1SGFT!GF`<EM)NcGK8qh22}m
z{nfD7V|08<r{G>=ofuy98SS3~wBPupKV$}s^`X!oG?vl3J!F(pL~Pg?p+o10F_E(I
zqsCkGB-}O*Q_gtIxbp?*jT;9?VE(Sro7Rha#`vFLcf$DZcBtPs_OFJ$Nn;ZIrs$OM
zNeAT$rj0`s0GTm%{EXgN<4Gzgeqapqfu%WP{M#6>v*`o6d%f2r9zmyz>23Nf>@yw9
z2ib3GrGvo%liOkNTuqy(%JHD-e{?KzGv!l(tGlU<)@2V<hzQV!OwSdg)6?{^nD(Du
zrb`rbJ8a4q!#8i!m2fEfm>y?A)Ymj}0-b)Q(#>f3n-;$bg(IfFmZLMkv@#qpM@_So
zya_Z7P$DeI)J{jHU{m8`5D76IUkwjKP5;S)`D3P!qoELHdYQKQ$4$P|RDX8D^kor5
z!%c3K){Zdw?FTc`l=cHaqfCBO^%reA&<N}p)7#sD9cy|z3*@9}OE~o6Oa@w~;!Q>h
zD<+t7>2#H7`ia)SQ>Jts$Z6Aa6@Wfta?nC?*0lWroJlf0J3#f<$)*^pjY~1@_#SAf
zro9gVJIxd~4>IYd<fCxroarJ3BF>wd+As+jCPxu0Wtt9s1MDnQCROQYn|kBWnPX~v
z9jyzd*B^tyi>Bv3fcLqk&9tY@Gp&6Hqt7>;_5x;ssfsFH9EGOCltU^q9iZ@Qv8m+|
zz?7JF8ezWF^xIp|FEjllM62BN>UwBYm}=;pTxr@#vHmKP8$E&5CM|u=E}4Em0_+-7
zB>g0Dy~!m6oeid_4QO39#ZjEN(NsGG^(&?WR9Ao1Vfttt3^tj%Xz6b@ZKZ<ZYbNy$
zFk4LS9+;9=)9MrOu+0=iRTI}uPcDK&yD94&e7a%U#(_^Arl)Cl*J)b*3{Y;GHcFs=
z%M=#?UYDtYKEK_jFX*CSk7-7UR<G&!pHS#CIpnmN?l=9k111Jcg1@0SXfj5?(vZoY
zssM&fE5Cxsh^dhRkfWw2DGzYl)WJgMm?^UpgSlh+n?AVXCM7L*cTL-t!_qy|ZBK|y
zn3|ph@4o4UXFw)R5!azUWor8!lGCOv2ko$DOrexzo;4ky--mr*N@jpLXL^;eoz0a3
zbnZ1<zr)b>n<FTva=;uRL#M0RqYLDqIr&X=x|uz^0OoG)kwDMG%zFp^9x^K^9O7xt
z2}7rs`5wK@hs{5K1Tb&2t&jFxKIZo*wCihL^eTG&%->Po#NT|4LPST*@BfN<4lsXA
zb+$*%8PRYw(EJ!5B0=VB6p#xxr*DCY5OdBnTA}75`s^PwXU;-B%zS<q^p2Zv*`RR3
z{AWBYgqwX3`JW$QuHQiQXOZR_(vLD9_z=EDo4=sUYK-|Sx+M^6jvm3^@TB>2GhpJ(
z$#_`j$D3J=kW4TesM0ji{Ocd!oig{+!*<%trj_)J*+OTYv*zs--%2tsNrgzN`3&vj
z(#*p;*h@FdI_Ug&&U~BvK5t&^0v9vP!HIy$G+%rQ8d>I~r_stb$NdAe9P>M0L;r&L
z-8l^HqIos)_w)13e0s+U%;)Zb6q=o8;Zuou2i0hnn*U9MNSXN;Dt@mtXHP=C%6yR`
zfYs*iIS@y!`Fksvb>?lfgx8w`UIDpg_A;Wg#T<GP8m;E%Q-IcH_M_`2*UerO`Di!4
z^98*C<~2XV(GK&XZD@6x*U+x;rkURkkz3{|$~kwL-=kXPZnMe&(qrCt5hA_jkLcE9
zpTqoTH)y~4Q~{U+<}v~74w`>yf&P$LrNo$q&AV<xW5g^PgZWYOZ5M#vHvdYsX=CPw
zDs<j4Kd}NR<K`Pxki2VNa0{LH%!f2UnJ^d84tLr-F&~4NF^?5MWY#REP}T#p!<A|h
z=FAVBgNCzZ0Tl)8wbT@V>0){RD136Yc+%(Spe18H6x}RG=&f?M?5hXyu=r9a`;g_K
zc`)y3>7x^$m*tzUVbI(1`4$i#%ll*K^tG^Z@#poks1ktUZ&3-Lcf|67BOA;B%jHm5
zI%<h6giN62-IZVlSte+)53w+)R4vqUHxV8lvjnFCG|W;}2A_^wKBkJ^a7zINA|fmm
z(;$(Scj$;2ZE1_c$YLz-bb!QKex+|)oaG-n2F6=F4`5~zEQa?e|CealP1n*-Sz3D0
zI%~P}23kp$mj{5BY?-C~dWvOAi_TQbqiTqxS=jWdq+5a$0ea37+XKn-mJ`EhWmzt@
zV}#k3c@$~QvA91A$qSZPx({&C;+lZYT+5?$=+3juyi57Ne2W{MTMH~@T~I8vytfm~
zBFn0746WEw#DYeN<w^S9ms--dfLCUD_a+p|Ex%G)t-=yQA@EAe^Y3FyE?Kgt;YE$*
z>v)h_%X2TIv(6G}hI+lFUJdmI%T@~VUADw$((ivZTArt$in(H8QK{%vOCN0#n=CJW
z57B1J+4JDFSfp>jwN}fcxgc$pqTfKSTN0iGOuOZqQxLgf+1QCzheam>uhWv!3h!@P
z-aY^iZ&?mVVZO^UIE>D2i!>7=J(jc>=s9{V>{XzBmW<!g+i!V+;*bLtK2@F!T9zIM
zZ^*Ko_9w%ZU+GtoMl9b@Kz+=z_A1C7%O({R#w~aJV1B|<M~C+Nmi1RLh)K&Yt3jqL
zo|z!imJ_c*WXAG8CG_Sjw!Z-F?67|IF_?R;C_%!8%F6!+z5A_v+VmW-ZYF13t!wDm
ze9-zC8!b1hl(NL`)`2d-cv%1a1qz3(2kBekX|1Qtp_es)uH*SwYbiMCYyF@P3Vznp
zOb~zT@I82O#F|MFya1~s)(J32ts5wP8EAE<XD-N^LHp)lD~}eF5UcM7XoOlHP^{vZ
z^;#3=BFxJ4rWe2(FM#?9>)R6;cDVH=x)U5>{iqjqBdwb_7*dq=7X6;WNvpXW>T%XG
zDo>2Jx{X03!TOhjf@g_VNfGo<S)Zj4&uOcq7@cRVEB^z<v(}^lkR)s3DTpLnA1#Dp
ziZ!wwXsOm7cNk2wmNkQ<TmO6l<eYUSWn|A=W9amoVa2n8_1s!OS-C7LgQ|wIt=4(q
z<yg}_>HWK4{f%}O7p*0MP|UUZE&<82ev}G>`Bs@2qc5<!)BV3f>xL!hEVAZlp;v5O
zRRWk2>uxRlEwxV5uA$6&Y6A?GTfck~1Ff)r)C^K-9i<&qmG#*UNLE`*F2KSi>sb$~
zKdZ4W%>ihwRYjlnI;#(@DfQMW%BeJ1UoQl?Y&}lvO`~;mDV(`tohidWuUc>9qSa(|
zq3C?G^{p*vU9)n@(H84T$`ZF)U#5ko&AO4obJwjk?dWW`u5y8e8`jzms=w~AUZbj|
zPHP%v$!=Ozv<h@vxA;M^$J+QTc)ivIRMypJjisN>>9?MH1-t?4sX~AbS`*e_yhGNo
z?cfbtTdrWBBi1ut!qTYqpc964+d5{2$e6W{3c&7ISFJ(kxOI^7oQ?@==!+1&Z{5)i
z=A@Nh2luC}6LdJ7w*F0rr5WobD!Q1p7E|TQ18c%MNX}WK7Q-iJ+a}6H?X^{G!34S3
zcAtjGKHCo-XzjPzGN5<Rwui0}x!LxdfP%X%frjg0yXOrHha9#LF=RY#Vje7c+2U!p
zblA3v3Ix4vFVX)V_pzl);ghdT{|qeo*%<Wb`r9^6qIJafUy3dU*ebLTIck$V4ika4
z&rIM2*+wpd7i_Cv1%(h>E0vRk+9Zo$@0g8Gd&DrC!;SV_$88TShEox?>O?RjZ9cS=
zM%gA804>@UR0)w7TTegcE7q3j3lC4)7SQfH&eloqU%ahjIYbg{u}M%*v~lI=JY_pg
zi^yr)*OZMoW2>epL6S|J2$W>oVLDo-*n%CjyGynGOm!@2Hg8{Oq}#%r!8~V6xD0aM
z=KNoPX4n$v0VdP7r5HYC*)~vO=z{Gk9hWcKa%$0;Ym25?FR<k(K?-f56v`^Hh3hfU
zVw+nJER@)4X}4c$Yy1Cwk!?800hw~!n{v!hh3#q)ELGZ;TR^I8p%m+=wyk>=XqRj`
z^pMxsxb$4q+E&Lwq0YATApEVjon^s%gYD_<z`ktrSqxsIZH(${uh{+@4zR1X(LSIw
z*)}Z)ui2Ko8WVKQ*0qN2|Fzh*e2u}h+O|9o>^9pAl#aV@^WFi6+ijV@!|n~+8<F63
z*m5Z})M=YX+vl6M82Yr|vgPdq>9Qs6f%zVrh!4G9+vGub-)C!~k4wMpQTmt;*nTlW
zWYD&Zij0SB1yz*)8@BaJ;QolM_*e9f+WvhWinndTSK#oNZE-0S@7PWYK*nv=MDE%K
zOz`5KZ9N}@nXuiZ$o+kr78fAqPuiZNbLW)pDJqYew!L#3m@~H5DR?z&TM!6C4{Q(9
zV>xG&i{Plk+3xR)-o5ruC=c#pe<v7<`|O`K18u+Exf0k1?17`05?A{hD=^T5_KOUN
zxY;LZ%jRy+If0gk{iA0fa>%}xc9Wj=Sh}t0WgqqfIc&dAn=Eg;m7XUbdm!a$eC?mp
zj^58<mr%Ud-(F3ZRgc)+;s6?8-$PNAqxRSLpfk|^=UHe3*?sDP9c*{?$LK@sJc=5J
z+FPiw>6kr=zJ_7;)l^(|+#awUdME6E?1yBy{Vpw65%yCq@IKQ1zCWO&>}7n2MB5$i
zzk$Zszk3MGSbOVDh@P~65&_@h?1y#%G~T|CGVTfX{4OXa+W)wM&Qta=`cj^@-`xtm
zGxka=$XWZ-v?e6km%D+NY~L1&IZUzp{0LsE{S4(4)9hbU@xpog5DStS_GZTfuruw$
zQNYf!J1Df2ZC~6AjU4;Lix|uWyO1XTqP=?*8oBm#I@jdcmj?nZ-#+XNXA10jo6#z?
z8>vFB$nHy<*<$+_agZ#r{}TfBQv2LnfG)FhD5+O&KllUmD(v5MJ0MzVcYO~|RoO+s
zAl3HubSAxI520XgjXixnU~28#UInktexD6eZ+}3U`Ud;E?%-Xvzut+?M*DU%I<MGo
zQgzo=dtns}HrefGz-zXr(0hB$o)eC7w%FaL(AjFgc7%R^zRey)k(2B8>{gI=`&Kzz
zykS30>4XmZGA=yrv}gLjr<?XVCO~i5^ZrDu%f8_hM7r%FIvDiWkGX@_YtP$`R-gT$
z2#ECCeN!PaV4vOtltFvgd9;S?rXw&kY>)nS9^StZyQ~@xkJ?-2;Noq2MIFqK*`HX9
z>Aqu+pl$59y<!MxckQ#3OTA}L>jlh&y@n5k`}TQDAu?%ykMdzt_IbT9KW#rt*K%g;
zHz{m8YhOu)?GNk<S4hs;pP@*&v(tDiym0Jwilu5p7pEWp1aqI$PKw*^ciKnW*n>{y
zbC7X!GOh=4cPi53VexQ!-V<INa=J&`K~JYYmZH<!X#<^%eVhceTKYOIr7J&2oX-3J
zp8}j7e+!sLo$fTCGtlWX3rLXD=R1KJ>~Q*E2bdvFaW7ynp-y(XOm)m@<OPs0r|<7U
z^tjU-|3Kt~(?J6U6X_I63I8akAXkV)JI&<5M2yoH(P+gwy_pVYPC9i{=q|xYL+7YO
zr)6}x?vzu{7VyqGeb9%_B&RSsLL@smJaz*+%_(IN`sq&kbwE4k^y4YWoOc@Z#zbW}
zi7DQj=`?>FB3Vv;lmN(f$~p`E9H$!;*0|vGINkrd==47!CLz~pl9EmZP7MawEp+NE
z!$6Cio?H!uQm4tELCT!AT>&X~`q@FD;Yz12I$2jaxw^t`wbRC%(7)vLZ6nZXoc4T)
z&RVA&T6XH3rs#xP@1&<<fd6CZJD{Sxp10jy7T9HBVc)X5ETG0{G-^zu#;A!=Q!R<H
zB+;1IQcTgvHU*<uKm_U1R0JtfMUbi@O%xCiL{I?*X@Uhrv7v~f|7U*RcaFz#?wxsN
z?%lWCJ2Ut7vNOLKvv$S#+|S?|oXfVriza8ch4}5RI$O{>@S1Zxz1y0dadZV&zVmvj
zBf0Lp=n3>%o!7rd`G+>=+6B;PcW!<kBkXW)u|Q*&^X9oQ-|hSd6^!3>o{<O-Z#lQn
z6?ofOPO*bK&OfYyNU!skl!mzLd_EiMea=hgU`Y3z)2(6fzH=WHMD;sA-V4_rIA_wa
zkB81*hk|?L{N@D8KRkBMYk)UToD1k=^MJFt0WwdW?I>vX%-L57ZqWHg4$y|2KcQ{&
z3+I>~`1{g1iJq3j&KbdIeC2Fp;o58GxNo4~rd>egiSAk%1x`G)@!O%kOS>iv#8Z2Q
zR+GE6Yh?8QPkU)qbk@gPyO=f)d$ftk7?YoNBt1U-wdPdT6`*~WUf+AQvnb^qtQ~U@
zc0;tMk3uh0`;Z>iVOl{dxNz-NXK)9!GhYKGLhHH-+(B(LMJ^(>iUGJ5rTskx>W8#;
zZ(?Rl(c0~9kcrVAprlBwcIYVV#%VWEjmu%}3)*nTYoF48R+6AKGlLh2+J#BbPtrD1
zHZfUSL-mv?+SGXT9nt=p3$QfpIm&#eYxU`v=VRJ229ONx*S`TXQ~OE=lBI3D3zBQn
zy0~Lbj%#O8SmcCuGMzg-rER9yV7_(`5n^$Hb|C|Uh1xhOhAYzQSHncH_OE{cdRm(|
z5$YvcBc)x=X#KL`#aXQb*)7#>+6S&oTSAe?a_t-cLH(R|kRG-bT9-c9tJIq8S(vEO
zPB{qu^V&T>VNBK9brhSe(Z2Z&urFx${Q<OEt@3N2UDU3jm|vZCMigM`wE?srx};rq
z4SJWgYTDB_YLC%cyh+>n0AsnTEupyFHEo|O8k@EKevoX@9uL6)uWK7jQ=rkR{fOdC
zZQ58Z(Au?EX}UYKSF6$3sa>o`;|*<pGZeeDhTHI|TU!wTw42&3^f0-lb)5yt+uBET
zV*QS`p%Pq=_Op5nqE{=i#<1^dP5tn<Py2xd)bDBC!ol6wF3hF<U%&Plu0-(zZ8bd^
zA88Lr(D_(9rx~J8w7)F`%z(Cl%A=lYPtiv8nfAydjA>B&`E)2e*Ot*e_Cg!42YIO-
zqIKY~_IGnAywdKVe9LR?JaZUw)A1jn(Oq|c6!doK+Ww>Xr>9O?gwEZ%PH%YOrCSvW
z;;kF~2GD$UllO!3(`_|kX#TndwB!rWO`zOjpzi)UOhS+@Z4d_c>N4)3FIZ>%0(~L6
zPbo?ss=G%4?J!-+Xjll>&B+AjK3$$8Mz&vf3tI^M|6{r(RC^eqdrC*=4(guPp)*o9
z@E$axbfFjE=^>rFJw&2)CHeSaVs!ln;8U#bm?wOS)BUv;poevv-++3&ZY4!r5_BxZ
z(-U=7^zcg3T{{VsWZmF#kQ80}Fhq{%n2E4pO4T(K!o_r*=UYHKrd#L%><rzI5L~8i
zV+^<~-6l0evUM|PIeA>SiZ0y~x`A8ZPU>EtL|>lnp)<^%((Rx!!F=6wADA!DwbIJ1
zP&acf8jEy)UjtaN?zB6|Y26<i&{$&9Jxhm+XLarr&nVTIDC}FNyPpS7%XRI$(0ESQ
zLCNY0-Ns~)N?rE5FkhwHPMfo8T`^^wYILiLA$dV(O>wGP-H~-rzo@gO6=R*QfW}g<
z^C>~&CEb}fAaYrEi2^oPbf$~ngKf}F3Bf2Db#8YsiY8qm<q@vxCRbphuIY>v6Kd8y
zqyn%OT{=}+UDthd2B59FcDj$+bi1jjtzGB#9OLcKb!S1ZQ`btBK{s^KbnK%`H#rOH
zw{)5GAiu4fOh>Tq=th|)1Fcv0CKX%V)t#Xl(LP<uCYZmcTSL2s`#RGJDE8};zJ<XD
zy3?0{{ZLn%3D8HnfVmKPtjna6f=_h1<xn5c$xR?nb)Qr9+@S7<0Vq7zY3VIIq>~6C
z`9fDi%bS<F-{zPg^Gat&1AVQ_pvpcseRn3zyX)tC57#{OJLwyAp8D7u(BG{eMGIvw
zy(7Kxy!DN=_SvI<xdxn%ehPg+#aBOy*2I4LB@|2Y*L%^m8lbPB2@2HP(*d3!y(jJ8
z_Ua$ZqxzR%eGA>OA^HzyK_*mhOZ5g}`X?0k3D@tWxZXbfvr71MP(PkNeG;ip-U||?
zx1i_iA^lrE5Q)~G`3&kY`pIXY9;+Wo0gyQT7W(4#Vg1QpVK82Ae-=YZ)Gwy%B1wO0
zJH=m;_0?r?F-4#IIYf`>$J0%cs{i~bV2<iPsKE%+^xk8Emad;KhW;_VG!f=A_0|+~
z$kIn12FcdXa>N|w=&!sF$y|NLEPx%?C&!`hgx;49+nm&I$N`t9-|Y^RQ~Cl5ubJ}o
z)h_U+NWYmrDOaq&LO;c6{q1uwU!qT^12Jdx<#cB5tiF988cX#$9rVlep7cO3*T>TO
z@tnT(TiC78|Mm|ip;CY1LvU64ZGQmzyuR)mC{*jys3xvP&y@o6f?nMQuGXaQdxp-7
zdT&}G)af_TmbzZwMZ26!deLR*U)F!O5u#W0HD3X{L0?Yqu|_>lM<kl`=V*a&RsRny
zq^{|AP<Famzw8}2+M>^T2bkCO^Ql0+RUb-MZioKd4)k^EU+e(N4ZTS+1{z)ZAu1v6
z*0(-I=S{siMOAL;tLWoqxAoeOA$mt&k_r7D{R&4&_Uf<s!Na@yC$#qI({Gyza!)U$
z*v@_ZXH>G)uV32>ln459syltCKP&)wq<>5YcpmGW`~dbuKhYEo#Q}X*2SA_d|B%7p
zGyPl|%%HxXc8t&UcC@G+(m%Zc&=>khDh+t4cddlTuzmq$6<+E8ibvyXy;cBhH$wuw
z(%lU+l~C|7{P;Fdb{W>MK%=MO`*$F@+b~F}eJ{hi<+T6vG0gq}qP~WpQSidgu<S=P
z`Wx<1eN%uTp03$I!&ifFILKf=h*9h{)E@^IY<NsB%n-vkT3m)2whqHYn4#|?8p92%
zD08;Ya9#!v_ZtGnV!93(tQMg$!f<pu$U(!<7+QZu8h-f&vmRwQPnA@M46@H)KHA`0
z2`<LaM%l4ggK-kD;|wAl96fAkISnq}p!9=ef?;nt<|5J1F9w%nm``3L8@i~hBgNoN
z&+H?H=Iua9H}q`+cg!H(36u=O&9QX;Hq+3D5V1JRkn%1Dnr+x~0S@OFT4`aEYk21Y
zu#X$wZvuDHuz(Iq<r(g`VT7j)5-KyyH*BIiuE6jXZ3+twG4DaW$gpHQ3>F*qk-^i3
zZz4fT4E_|GIb-Pl80u#YbLiz_Dm9c-QnAbs{3SXo3=NmiT4^{;AIPdQ_<RMsHHM*9
zh+Hs4(n__~@E={>^#<n>Sh{53>0@7)4U^qrqS0_=H58f*QDpwAVa7oyTr<3T1*F-K
zR*M0)7#>l{N4vqCvXC7n!yl`F)@hiW2Xe!(oMNk82Eni3x(zF7@qg1WVk{JI8UDNh
zgSQR4wt?I+%(H<{J%%-uS?x6}qMYPi!^u;a**-&C4@B-6>T5vm8y>pAQoq4*7BC+e
z`li9cLqqa>c=*U*dO!=R$A(#S@coIwb`j793>S7o@u@*T;h$%Qu{E$XXsDq~{d0q2
z1b*Kk!$zu=d|{Y94vjAj8>!%Q*f2<CC9e!KDUJTx;P*K=H{%vx*mXCSQOMB4_?Yrx
zyNo$38a<6uO!Q?QZ{vax7~EsDTn_U-M&TNa!q@nmvLJp&>&Za#H(JvvnE+!vEq?=z
z6%?WgGLCr)w7teN6m<?ZCM<wni17_d0f!pf=%pBDTus5CaAOCpI`$c-eFydZ#{a06
z?tszbtO;&J7$a%JdC)kX3ST0P=l_9BlyTmC7(8VBmOf(<ZEXJpB*qx(4!g0&%~UTJ
zXS`Jbn8U`$g)k9s{B<!%f^jhwoF*E-qI7nWai9)^NH!`Rp`L2={}Fvhjl~L}q#0Qe
z-GAxEzU^R-8Sm4zo?+}oT27p0bln2;*~S_tz~mUeJdeTT8v7F<a@_bu73}62f42lV
zWqkE1oXIzqwL+o5*l!K4(Ae<<FpG@QRE1h><S49u+F1Dn&?UwV|Dv(Xm^zZ~zjEV;
zR3LcHD5(Zoh4F1#npYZK>!49(yi56u^F~Li8>lu~Y2Zwa@y|?*;({@V>KrZ_m5V^?
zjH+j7tT!%O0kBKPMaR&1**H8J{x%o`N1(CM$Tfm%GBz3jcGdVbgDEjxGp_Om+ic9g
zkI8Q_&i)0Wt;Q7E?6eslJ_KmH(Mb)i!?=a+s!rpH>G1G|@m)&gb{VH!gikk(BMxDn
zZyC>z0J&}am8v}M7&lGAAbN}kB+%<MT2O@cu5s0A*n4j5rO6vM8NWCRnb*el4Imy{
zS2+NC_tyXJL4VKI>K~!uxAn<#kif0~Qe|K4)@9c)B}cb<Q-UUQYY7FYa<`5<3z597
zQJ=u4f~}8fr&+vJU5Fu_*?NZtTE2D3Ry0;`o!|wOmaW-8qpxSHY5)HM%v;Y=wZ)6A
zKb?nDyS5e4p45BW=5%-(w5_%rmLj%|ECY$#<{^Uqk!@@oxU6lBw4N*2);$7fW!ttX
zVZL%(%KH$h+qRpE${Mx}{0fmEm*Waph;*^uj|qx*vHJ+nSuO`no6&m0WiIW*ie2`u
z227>P<_qYoa|xjxMYGG+e<9NC@)Z?=+;QPlaP6UsY%@#@y6m5d>3Zq%o&@S1u1_cg
z=j-~u4;lkp=U>KHLR@{QWI5b5TR`Srqjo_(!L?{MBvV}fl9*sA&GqnIh-SFf(5;&7
zn&tt~<E}^Od2_;*y$Owzt{WBT%X3|u2E`&*Guq}CyB@d$pGsUmpz@A0u4}x|ch=SH
z21u#vQ#vnI=9>N=Tq}1?q9YFHT;HO?h)UOb+M`vuraz$kd$sEdT4&U_uAPV03$D}X
zSb42$jWtYMbiGM8e7);5iW6UQeLyjb%dYVhN4es9V?8`<bTxkk$tG7DN?>1gJ@*_U
z*IY+XO!kIr553K9y4LPDhX($X3S4N7e_2oy3-=lXrZ?l^QIkMISK2kfmu^685fqPu
zR;wU}gG{@?*A85#;CDLRd{dCaqw&5#k%Iv}6Qt5R!A<!59tdinT!0cHT%IKQf7W=H
z8E|II=3`*r?9#!~*wEu}cHB`~Wxmy=qx|R0iN5Hb)$uO6XO~X}`bT|~Kl_-W;=nmR
zl-B$td<mv_?(EM2H*a7F5cA)oBF9hts4)C98P#`x9=!_fUo<n&{j%Uk=zhg@KxV-)
zDsWr)ej9Wbxls6T@x~BL&euuzDF5=!Qd;URah(l_ZyiTsR7(?RBe3klTKv7dtN>~&
z!j8bX?>gTE==a5|0s6x!d-Sd>r02sbR)CftQ@+B#SKA~){-<2JXnx*jf%Y{zD&bq3
z=7pAZn+jlMgH;ULf0>zt$uj-=h=am!m;KTGdpjMH+c<S3{{4rFa$7rIq~h=0f}DrY
z@Dkj+4Ha)ecQ*v~2zF3CtB>G80qpt;F4LRLPmuUFAp8Zwr<jWX!JeZK2^O4+fL@2d
zHxHil3trLj=?8*zdVHFO1Ug(B;uiuRTBz+7uAT_uCA=~fCcK5?s1Rq5aM?dF;Ug@h
zE7Mo_`v744gnksS^A|p$Pjdwb_tnE-l+cl~W`~3~D1e(RETiX8itvYbVd;plkP3iO
zh3A(5?5J=Qoq0$z30)~rkuEGv1@<vvAVmr?gy#bxlPMf%2X>aQYclk+g;kVj&JnKZ
zg56x<VLF#|Lb#MdPA7#9^xdsIVXqos$3;^pQg%WVbcgyxU+aOHCmK5dXHJRid(oIL
zn!Fv71tOD)Hc^G5g_PAP60JG`m}1fM9GEyQ8m|LPiKvmPpw5WeM?mqcDAOJ=rJ^g#
zpim~7IuE2=6z+$?oD;Q;he(B}=LoPXMJ-#vRf#^H3b6B{(8JKH7JWY-Zr6yyG{C$d
z5}R6KuvYY(wip*h{}sa1I#D?-L+V9amO|r_XyqtqTo%plLgN)t!$DYT5Jl5r!$wiU
z5}0TbEu%whS4Ea2c}>(_27}F_G&)+=B8uA$$?KwuVUSi)`~p~L6Zz2n*Di`Sr~1DR
z(M5k)>J*I*fc_291NvpUL_bSFx<xCS0drII0cFi^iOx2FyDj?65(e*xuF#IINAwxp
zw7sHt{h)qVR6uXCK9S`w=({Hhm=C@CqHUD&>=!MiYLy3~+5bZFq3Fj6l>d1oa#zFQ
z$D&)5_kAK-9{^7WMECAP@u?`9A}Y^B%adVuP&6qD*v~})gD^NGiaCwO7ovO>=F-jV
z$_9+Z-OQa9otb7gpF=OpY>NSy*=E1TgUd1F=*^vL7SIKh<7RtXX#H`*%<UmsPnvyw
z40iL(KB3$7qS-%mkJg#J*966SGkp~dUNZZXzJ7AuOiq;xt!5!Lki2QOEfnOISs@RF
z9<v(yVSCL2$3f3q>_U}Ud&J?f@X1G<Aw!=(zHW?(4G`a=;#N~27Ip9@NSsP{TnzrF
zFKC<+Z=y|5zSy!Iq(J<X?%zUjStay~#EME-D#rik0TZXiZ_%|{A`U2pYiGpijo?bf
z|NE>(nb>+48q38)DX?@-ykrT~E5z2#@V-(UcOPb}Oycz`VfVcF;aH5m&Af+(-EKaa
z4$5_yAB_dqX}*0t^lzAdG#2_@=I_#UcbmVa(+)SylisIa%iNl()Sj9*iO~1jJY)wj
z-7LlyLfzeBO(VSUu<)YHmY;<i4awiaZZ8@GEKFy|!<#^hR9d#}wfK<2!NC@vzXTUz
zF#+)?ahOF`H(<goUefz`pT&`@;PzX5pA0V2;;k(pQ5IXe(0It=geOS6MM4Q0b1lB1
zec^G7H=RLFSe&FH#*-FD@@Rf7^i;c9U}0mLht5KaJ2T*0k;U6{;dimcsqbL^w8g&;
z;3_P>r?pt6#VooVsw}Q}L*cwd;w&^)Tln<?=7Po8tx&JESVD&Ynk-}rxP8^aoXR$?
zSya`+r)CSQ0+_#Uv65<uTP-fpvbfD++)orLYq$6-6xf{>UsH_whQ-EoG<I7w&j8F#
zixKpMxovUm7&Pu!tT+#mUW+7J@%LFQ_zIHuEM&CsxNlLfgclx`3x9_92P{3FLNCH{
zNj(}5S_Xu|e5B<}3XMludTpcWvfLC+>;GuW8I+HSu^e#|qOq2Tw?Zb~@{a~!Cs^82
z6-J`vLW;#FS>{oMA;q#l2Xe&n<pjW_T6Xn-J8D_52$E@*4hw;D+_K|ccyYoqj7}8f
zS$<szXHHpOD*|S|<s~186j-i9&d?+-vUH&raIxj|6m*`pjH3;IiDicx6LrS2*aeNH
zmW7mxE3@Qjg;Z{7ZvfgkOIPG?#g&$2be6oz((4IO&RY(CguWWfGgMZ3!P0{wzqOVP
zzk=(rd`Y{!Udzd}<?OSpp$vxUp5>H0nmx;(YC-xf`!+-Wq2+&7P<&+hUo}LZSUS=}
zY`}6IMUY-uI?_ApwdKSr=(|ZaTR_rXva}G+ct{RV>~fc6*bXS3lEj^GZMS3-J#@V!
zQ=XyETQZL#WqTwakHi4?nk2WWnm$<4dk@&5l2`3e43h+}0@)`S;|9h3lBcwh&5&f!
zwkcCGK$Yv+61fU}Ig;5_x0EY+x*Oba$#3l-CnS#a5<e+<O*IvH5?u>s=9I*YP7UNs
zqVGe!K=KK_{R<_gfwQ1RlFR*YzgS|V$nj~(+P|S+B3b?#8fPRocsO%bqAGw$sbs(b
z&Xh??Xwz0M*)s#!=Onu#(N`f^MX}mS$y-aIS0y>K0g~q>Lb@KSCF2%?)JT4%B7s_o
z?Nx|elo(7eVX#gzBL$w;OaAx-&RmlGK>v@;WyvHep}8W7Q9-mpa+fZFM#<t%kgJmQ
zs~~wz@+<9;n<Zmjz;25q@D|8*$w)fR-zvE@3g+7+`{=}0yW|$dmOCVAr=Zs<v7>Fk
z4N24vTK{)R>MZeFbW0X|19DR`*bRfXBpX{{>9%Bu7JzpoQT;&ck>oFjiD0SsYq%C7
z{bC{%4oZV-02(P(KgH0Zq+@8sen{H#3?xSCI2&NG(jMA39F}^o2Z@(%w}M`R^rn>J
z&xz84?PyJwKBbLpiu4S&#o{B<yBk4Lr3=>sG)<aIm1xJL{eJ>2Lu%Cy?0o4_swygw
z=1hW5MbcKfpo*o3|HSCeN&mYB%!|?^w2-Qkj-?HIy)?80L%JmW+6H}>rCUc+{P~JB
z_88C_q~%$dlSXNBIb@oo3GuLdRa#B^${W&XihFlSSJ48nTblJLxSLXkO)z*%8b<Gf
z+tMo(-@GH;(ge4Aq;B5u>8`YSIU13!VF7(lDy2_++?Qt43$tI^L)W9}fz*{w$UT%!
zpc4&`r03@X`?0iyj^aI$dItl0Ksuk^>CdG7l<ORn&fX9G=TZ+^4h~5ll>_F5w014X
zOX=xTP#=~K&=&BOw4FX2@LJkHn*legP%F6RZsq+ph=<j;wCmVqvhw>Ktfy58eM@t<
zRYM9U%FAj>D)har`e<|HYqgYqSU;=KX=wDf`ga3d3$$u*0T*P|VGY;zTIEHdG1w|8
z6(}KA`Uk)cwYsnfT$oiV9RoXLl}TZTXe)*yzA;u?V?bi9OyAMd_OMk?H`sWqgF?t8
zSbeb!T&L9lg@vA3y_yU(H`(<ykaU+-AA&&-S#m15FFSY(BA&8@ayYtM=CT-iKC&v>
zjrq#npsHs-na3Io&|lW=3CTd&4>F(x$@Wl+HdywzNd}k@+4O^u*(d8ij$duR?C;s=
zJRn>27u=7K4N#0LQf9Uq*io`^-@?)%Su{oQqGeY<fI_TnO(YcJWOY>XdRTVjV_?S1
zW;}=aM498qXiSo2?1W^p%s>gy6xpZmfn>|(eN6eE9NCI<FrO>?Y61K{F4NM>?Sw4a
z5sD{e>#5`?Pd5HBNWQFh2rvb*1WFbb%e+2;UWqK6HZ*5s7ypFadRabId0&#<r>}ur
zmaSibzALiCDsT<5N&`?DW$ENolPoZW>i;@qhg!jQ%KH1zc|$e@X&G^sEX4{iH)WCQ
zFwh>^^(K&BSvzeg@5*8`VZKkcGz=pBvZ)j>dm#IQiZ&n0EJk61AIYAK##o-p4sHN>
zCM%Uda!|Hr98jLiYAfLAkZf5t-G47+-&kW5FJ(6$!u+so1KlzK))AD`3bbC?3;iJL
zE6+jpTG!1-W3Y8nCrF6(x?<>sTHmUJ`7rCXbXSC1*C>F!&wBnufbF+FUJShh)-&iT
ziLjm~fXG4XzD$rv>t7c^(iCMqk%IBj)?qgx8e=`<HCkh>HT1NNvu>w7-eK#-XVDmM
zeWny6Ot8*v0ZFnhrbB<p)<@|cNwMyyC+QLE6ZEBnqt@$|VxVc(cfLYny7j-5gg$2d
znm$31VXfT_uuSXIW58vZtiz~&H`{vqhfvJ1UQgf3$+hmJrN{|uaWcprn}{<YJ~q<t
zA?a)5H6A{N*!;O2b`RQ2o=StUsh}#tD4Y4TjXq?v`$H(i*qrr-qp>zDWkus`T<T!q
zu+5K@vxv8`i--9H8<WfyG~LF67G%e5)@}niVRJPW8YgX@&;ujSCipGDRNK^3n6t)4
zKNm0;Y<kN;8f?rc;?-zVL0>;<vY9|}ldCpewDh`WQ^i80*(NIiT#HTOL3nuGX7DaB
zTWx-u01It4*G-N1@!D;qbKpgX%?2$*J8h1A3-@o>>{$=eZKKct=BAD05hQQfbW=?4
zwoT4!G~TfZI|zkGHfOWZ_t<7tEBc<;T&MGW12)~Sf%(+tt3}|R+32ZuWzfdqKZrcH
zdD|Y1LpBkaCMdqJc`yyFFKrHa!Tn*IZ~lXCuWUxsHRmSp6hhHm-t;F#JmjC!OLdq0
zJXJq>$~AM*w_85zLwMmOe^U?6TYhH?B=^WC@KE=W+c!hOSMIYOjec^)H<(|4`7aeP
zA0YSbp!iRqJd`paL2^0OB=40^r6~=TZ>79(h}<m(jiGX3DyA)5zWjgdBKfK<5ZNyu
zMO9x1<areQkC2<QXgnxCeGM}cDgWRFxG4Ef8yGw!f1irlqvc~LT^1{!T@Nl!o{p1Z
zCh=kUGYZYb%hO8HnILamgw8~H#0OAJk_TM^NtTaJfr%sX`|~lFRJo%)M2^atuP_N|
z@-E6=rOSO1fpSdl_7@s6<cDZqktxrL24<H0)P9I$%U{q2H%Bg|?NqM(w;LFe>4bdE
zBZ!`qFQJ1GdGgacpnpn!jqdw=dGI8dFOW~%2>n7iON*@{`An+2KPUh05zs2+i+_MZ
zrTox&%u|(o4JGR@$vgcaa#@~n6_ap9{(3zc8|0Cv0M;na4Tqs7`Cn&Y_NqyqPY>2>
z@`dzGhGw~h!gDQhPX=h$<$<)tY?a%^ps`K9j{;5Ya>gBK9dgeDQ0SEZ^$|q6<X8Sd
zW4HWk7r1>>{{1WT-ICw*g2HY2YCDMBk?*9JOOO1wU`Y1LKUfMc?#fNS(Ph#nkNyN2
z_vD*LqV>MK-Vu%c^8Ve>cpwjGhBJ@lTPZ;JL_VhyeFJiiJ`43!zOV-5nf$gVL<Z$6
zXvO$kesMPjIwZfJ2nBcBkblwWVH-<_j&|9)1Y@|Kw(n>$Brn?;CR%)W+digb@*dm4
zi7@D6`v)x>d~I(~qS?<@N3V8&+XHW*F~IiDU*H05Z|1;mkS$NgN%q>7Q_wHi*7j>y
zO0mn9V-Tr!otD5%vy&G=@0eZWNH~*e_uap+kZt#K5fpOmBKs-QbHXlQGA!lWjo~2L
zXqQ_A{Tp_vbJ5pjXO{}D+s?QK+)cZ&^o!iGs~QLW+jckU?efqrllD`O>~i0O<Wsw#
z{T;^ztVw8xDS2VHnl=<K?GoOB+rxH$9Yf<QyDF+_dTke%26Z=u2VKDKiVtZ8<)N6(
z<FeYN=%Y-nzv7Dnzzk5#r(IQ~!U;Pzag?Gs9OH~u)X*b4Mv>SHkyu6P$Kc`=|Go{$
zc*P9UEE=|=pECFvihT*NdrHxn0g|uCq!Ua9ik0s}q+GGR33ksZ+Cu1ZRxG^*{Yr%`
ztu(6?^JjycR}7{?uUgS~5_&ZXKbrIlik81%w^rf*Gss0n-xD;}DJn}aq<Tg3EE8yp
zVmXznUsv={5UEuWrh}z6h0zNd?TUmTa2<;FMtISw7}^AKL-BzSq)Rb00KIO-nqiFT
zrea(VxLb-kDks0Km~RjDJBk-0(Ac9GOUK=M73D3^yQ}c~99*B`qYo&se@}6Y$^x(u
z`4YcRzv83~6dx$AghBD4!i6${j}#W|aP6_ez6abB#mgmt8Blc7>+`8%_-}alOtHQJ
zB7=&$dh|V4ENg`1kiym<+zW*>MZRAu^ptcPR>-!)yc_d@o*r!O%)u9!6A$JIrS5kz
zOW%N~Cv)^7WWt%28es2Z8W#im0OLL#Xc0`=T1<WvGoOLpA*TK?8l#!674SEPS?CV$
zW0|(^z{N3d&~olDQ=Uw}HuD)pJQ5gpDicX$W_^lzG9@vt<Dj3+3`D?g3bUvOtw)$v
zT0f>TAuZsJGNUP;kj6}OfHUcg*KU|N#(4O`L<XZi1<6e2PZ6-Q7&|kdWHW(u%piwZ
zpaYl73{m*xIMewV26%$mNBi894C@4xJQK4r2coB#O>dz!pAlt(D_}Ov1Xsws&V-2~
zX4V|&7c=qyLE|)IY6WNsQ=S2z&M>PeV{?}AqtII^bH51cWlRrkyvmusDc*CAIlBrd
z70kzU-&Hbt`mbWDm?TPEo@Y${&oHKHW@Q-I8fHB$t1d9-TcJ_QXer5mk*V>9NF6hg
z-e&d8RvSoOV)oB~$YsWb$|tTcS36+7fl*Rre<QPqj<+{4^=1&c$}m(8aE;k+0BL4i
zGGU>GiP(n$UT5-5Bf+*ZJ<$+tV+yJGtDQM;4kPSf@M&CJ@=OgC_1$2ed=IXRxlI>&
zH&ZeSuH9q~Q>f$?)A}h4-ex|bEz=!lJyrJiFb{iSu$TED8zOg^^WA9dW1gnM(R)lP
z?egz4o)>9h-_Pv025%lPb@bwT$h=3t!6PP@vUQIca~9kahN0}_08>iq^ruX?7S23l
zPSgT)kjbrvrRPkoKgbYsm)>nJnBa|&e964E6zapwzG6teV)Bn*xUZR+aZq<-1Ex`7
zr8`?s1*{(IMk);3#r{Pp3QzXQGH|<DzZ%%}VlTUc^Jd?s;*ULS!zF<Fu!<TC+n0@V
zMV}uVLPr?<*`a1w3Sb`&KrfJei?YT+td%GF_Og=8Fci$zAAv{+yW2n?RtaVEE#Yt&
zn|KWlhqI&UZ00_;lMW#7XR|0cd4TN=0Eu81`(e5cvXkhw9mzJ2fI<{|oJw{Mu^-Sg
zJDSbd50M!5?su>h%kH_1vBa@DI%jj3H5lPcJR8Bm`vi9HL5P?V*^_~QNn+Q355;6Q
zkILdwSoI;G9bvztdbm_J;v<M0Wt}oW(%4p-*>u)c4KI$ds)+#2U>hitl*vZ_g2pU1
z{t-m7+0U<_FNYnNjREGehyHgPvJ2^rbAtUx36YZ~_TWKi<gqR)kW=ggSD4Rdr_%<x
zfL)&ru8>{r3a*GPoCl3!cKlj!r`dwvKuXy3br3njj$aQ)&$9na#XOa=^=mP-GS*=j
zcFWl_1K`fFekLeXuxs`}p_2XG5u}PWIa84EJo^)6<*M24Sj=S&`$+~gF0g-7jd?9Q
zegHqkMV3nkS{-})C<a>3K2l*6m)IG!2EWXXqA$5zVW&Qa`38225Tud)%mC8F9w`IZ
zRW{8H<Qi*1Rea63kkHq{-ZIf=gRZl-R0-3{o~CC}8>{w#rFM2T71egIH4<oavcq41
zyTMj{5120Y;Xdehv!xVkxXCutGXEC4h$5Z0*|r0~yu)5CMqdw`JsEnvY#JRUxXZq3
z1y~<@h&J8#*ctatP`uA-+A-{Yb|e+!KVZAJVZ0C7F)J~&N30D+EFZHs+tBxfJ$wW(
z1MC}ZAWzwFE&P4P=5SCLWN%Ov;B)pzx~_)Uqx4L8!S>IF<V!Z{cQg*OL5{HZiv8Oc
z<TdM+OCPp%<4UD~apw+Oz@P``mJhUDTxALT_T(;#A-bFU$qyo4+#k{C^X95(*}R9_
zehb(>+%dYWeYp=QZ|KL(rTQ*^?iNK50=Ri|fD*`QXuBK4si-DmFBeBk(_pUOiasnB
z!X23ajZp5N9LR)myD9t{&h^(oW*;|~Vl(?W<5Q3W+%x(XSOk~d2xks*Yy~7ExqoPz
z9mQ4qq3;kELD7(O&VK?NJ;v27f}<H+;B1IwayAqg&f@G4trur=OX(gl<#5MngPqHD
zFNVS6+%UZjPjCT7czTk%Q3BWUxLT@2JH;)gdhUGgG!>l`a5pLeTFC9E+-nhc@(~n@
zxljrxp5`8LASGO~8x+oPR%&3L<s5P$Qp#oR16RgnUIJHc;;bl9a*jJhi|7iji}o{>
zTqQm1tGIY74L;A^8v_&7T=*c+YPdt+Lh%BZ@e^Qbxw<8=bdmeq1CG{lR)Zk*+~^H(
z?Gjf*8-mN+W-8sh!lgOGPy=^`evwA*HJ!0);!M^ev|i;N(vIyK_gOkjG;`0A(b&Rm
zI)h<f=MI`fw3W-F0;@JIS`5i{u9)&29oz`2uIc1vhQY)QZW3J{UEH&^aIKpwa0b{-
zu5>0uZgK2S;BIr=MU3nY_vs3N^>9C%=uzCuy`&(;U2gOc6#KZPEDYY`)(?T)=Mt$p
zyq_DJ50MAly*DtXhg|J8fIi~Zl!ANAeM8?sdBW*q!3}T<T7N#}uKWzWXWX;fKpEur
zy#w>lxu*>54RN1Pk@gGj<GHl{e91Mv0hwWLGA;LCaqe%!(rYd@2+p|i<A27`-1))+
za2`BMtIAz`>%Xw%$?u?5;cot~1aMw_%n!i!=2y~Ye-FRo7EJi?|4<gtm)DJex*z|`
z2|)Yvo^$~R@P}7YU@MTfp!a<cZ%uah@{{NR7tG6_feYcsP$^g_e~ME3Vf>vTG=}qU
zQD}A_A6E#_{XC}xcYqIC0g(uP)Km=OAU|axMjy$~F@uLue0Cco5Akp2!l!8d@4q1u
z!@s+H1n$3Bel*1+;`ljKP<@zB4}rt+`~y#Tk-*;#gr|wT9n}pc@oOolnauCnhQ1Vj
z({C_wg#T_7?56VH_<|he%}zoxjemF;lIeU;D8P>KpEBSw_!(`mkjdM82lXueb9yV8
zvU$@2XyowkJ3uCvzt#ke<9yo$G@js}&^33GKXML@dHmyAD4ybL0w9^spG?D;3V7?!
zF_=RBuTq#V;&0Hb7xVQwP&mzBq77~dzk>oFXL#o^P(RCC&>d6C{}TbO%*0RQAX?5h
zS)%nEKl~v;EBLZN46Tx1Mc7sRlqAghdESF^BGvr#ZuHggW%L5Nz=s`&dM*FiTkz>3
z|3@t(>-cAn(O1t$&`)@YU-JRXU*;!$19F9D*T6ypKl(#B+Q^&K_GoS59cUMNmCvVN
z<{F>43lr7MyU>oHg@5N=h+gM+ZiQqkA4oIX#xJ0=H0}I{X3*>4?cah=oxB|_@^0{Y
zI`-1VTT(S`H}BpKFK+TPX_Iq{cL;&VZ9bAR?RWT06FsJT_$n`uUjD0owBF^*J0a7@
zyU|wS9<Q#1`TM+<mIVEL#zSxqc;8@f5BXX2e0{{XybXhod3V}TKjGh}gLMP^RQgE$
zQ{FKPZa?FfT?IGDPxl1(oR6dm`5}JWw-k<i!Pkri%u9aU6vzzo<y1ZJik}|=(bxP(
z%OT>Xj1j>@cV#oB?>&?r_TY9YtNYOBsXRFsK7}b?(tb5uxuyht`;;-$(6?Xd^EMO?
zC}X}rUxacgl^aAVTSA}^rF@k{g$;+4b176At#lg&yD`cYmti+nsoerDPT8!1{$b^g
zI{=MWI#E(DLHQklCMvzHp_iomod%JtbbJRSMHvzXaztso3=^r!<Fqh2s+_~%XG&9Q
zDOQ)R{N^3>9aAQ`(uY+tm4iP*BTKnzGf1}b&2E6^C|SC^a+Q;)i08P{f>PEel&L-N
z>7;TMMQ`(zR~#UDO8F55T=JDK$Dy%6`GmGEh03gPuv?^@L}}7u<=gM0@3b<Xs>@20
zKhfUqjMBLeBBrxS9krG!t@px2nev4#Oq46XqcYrc${lnjyF&Tvby%uYF8miTRZ1a6
zU(YKosnn!e`44@Pq(*7l0niJ|{!d}PR{0ynVlOIJQ1rG=DGLXwSMEqa<0a)hs#v|O
zynhvvS4_%jhd~>l54(-Zk`9<?Qsyp%=v8Ip5s+)jS~|PXtX$m-(xTi;S-|VcUp|IU
zt;%P#yJ}N<gaWi(*+&O3I+VX<0JBrsISoGDP=4_lNSAWo2LS6<rn<wKn@Sn&!)_@}
z{q4}WtxV2E>mB7k6z=L#ewPEZUZtBHmhLJ|%hA}UEdCtip0czVX!n%^^g!-c{%H&K
z2g(8^$U~+3X?XZZIUEkx9xK;>gUNfMJm!fB8c<%RN{FY*{x2Z;O!*6a1#(c?ZIZ$6
zb7d-377Qs<Y4!a=`K=>lUMhbX3$$Tn3mx=)rJVm1`mdGMmmuP%DvN=K?y9ay;5<}X
zT9ocmjb^}ks;uY){chC}ia>a&s;CUzTea5>jeArjRI=ft`r8YbzN*0iT7UYfVki;j
zuToq`Yk=y<?QkYg_2du~gH$i+;kQ?nRs)e>)y6Z>4^hc~fk>$8DZR|YRMknq4p+U~
z1@rq<FUZ6Fs@c~-4yYD<0EGzEXVam6P$fKxIgC`@8HE8xsWwfb!iGbtB~Cz#R-F#Q
zm||4!{m_V2jkyA6;#5m0MSobeya0;vs;~-h395B;hAvUH#TDk0RP|J=m8`n92z@E4
zyQ9!}L{;$zL{e4Lk^pv86-~jbG*u0~htgHmv_?FpN`FEh_RCOhn*!`i)hEA0CQCKS
z4qjxd%DaJ<qnf@ReYvW&^wc}9+Po6_Csenk5IL!myP`2qHSa38Q>wpqg5;}~Qi!ua
z)mR6;LRIT!I8&smH^5-A%9qj}r&UX`&{(3HPqSt^qjHIcrL(G&@jxqAl^q9nPW8(I
zh*qjDd<274DsClQJFjXfhGMl!OXc%5s;zIM?}AG61uWI7ey5e+MO7ZfY3o##RC!vj
z+D_N{C6$6s@?BQddO`h)>U~N!HK=aWyRFfrnoU8HCe@bJfVrw#`wXquR7G^mpjpN4
z#b8=gujW9cRkd>|8rxJKqC!>NuKH#K40fpA{u-oHHK735H&k=|fYPP%tHB_;Ri9|!
z#ZA>Glc8`+^&u7C-BxX;+M_$Ffo4eds7&3IN$ORNrNHN1RpKUaeX7}6Aoo<|^c|b~
zDh0g;`&DZ#Ao4)9i8lR@RGaAp#bZ?(EdZaWei{H7P@SWT?WyWI3ro*b(U;)wpsINX
z6rSUMe}lr1>d#%^UZ{jr+5b`%Y`P3~ST*ZgD85onp}gU1)w<UZbyHh>2^e?v&$NE^
zP=9b6WS9E<T6p29-c}3j-Rdu>63|Qi34O}QTkUiPB74+-xx*PB_4VmM@l{U_Mx&ql
zquZDZfAv2RPzX?OvW7ySy7>ylUxL&fS253f)lEfE3|5bQh{h0gR~Ixw)zjXEhhge7
zw2Tc`KcS@FKK0*XnBT7s`xhn-sMS=N6QK@sgUCVkQ3<$6wVFyrqSR4zu^mz$nFkBe
z>iv{ei&2YcM-Z!KBk9BLaq4rQgFURC_94v2t3Uk;T!Q*PDkw};FQYLfsXfI&OI9b3
zz&xd>7axM%BkJsF;8NAf3m`|;zYfAunmW~lp{1+uSb!W;zhj2J4E0>P0yEXl2Y`~L
zc8dqeR!8DElS!PT9-Iq@bJgE|fY#&c)o0-133U~f^qf=|B!c9rgXvuEDK+Z>XY$pn
z_F<p}YW6s=3)Ka5*r7-*x(u#Z{agX{)9UwkqOnB1iPrFE)Q8FeeOCScVN71BI?@C7
z%G9^qKuqQ8Z*$RkPVJ-zsZh_Lm1Cv4(-)(!Qu`&r?s>H=2wqgH*PVv>8ujRJz+F&#
z?Sx3JdVCHnT~xn8Tc$d7o(2l_>LrnI=8{_cFEB5wzmJ8#SJWIGMQu>mQi!HeUF{CZ
zCX-sQ5S>@m_4lEFO<hDq)6ME3%9pgLv*v)iuC`tb(N^_&YYeSToko$?cJ=8|(CbiZ
z>4)u9KYJIFH`M?2qp?dZeh-dzs~g{d`J3vd@tA~%>ItXd(<8NYA`~90$5TS+iQ1G#
zpE@2;kD`a?Q}wDZL7u4}Oo63Abx#TOpQ|hANcWI>au51ms6D8}^QHQ0s?Zr$FQ;AE
zEA@|wKuNd%Qv%6j_8-!9oM~S$5rfFKZ>Q@q$A0;Kc#&&Ay%3GZ?L|RoJYoO7=@Rtw
z>=!1(?|gec16+aqNG)WF>>YLht=RrYN@<?9*GSP<V((8cnKSk){{h-r`=12hO6}c~
zK+5blQh8Ik{pAm#USa=HBK?x~`B`wL%Km^gM5^r%(usl^d(%ZoUa;TzCf$Fv_Lrzk
z;-Y;Oh0yEl^%OFxw?9F}aF^^q9u1hw_D>hW{1tm6Wf&Xmiz>i1+B-SG?I!yu%9mWV
zFUCqre9ivcD(E%a+fvx6#eO`6^RL_2J7W;7_V}s~enNX4t<&4>r>vs*ONaeeN;q}X
z{(c}ly<?w4CoX&J|FDH<uf0tP%-^-&zZRf<_E}Rw?%8jonCyM~?}DMwZ@+aVBp=#;
z_9jd`vcE*fTp!!_&IWm6@AMLl1NPgqA@bCI<uLqxX8*4h8VBtU;P{A1{M^2rYTAbE
zE3@Fm3;XW_!M(IEJ_i%S_HWXw?v=eI#WP;pyL=27H_f*DAnuxeC-iw}I`_cRF3k%H
zqj+kz(OY!4=C_9s@zU(r0!(j>9lfFVXeLsM&PTIAg+cggyy{@V<fl0qhE{)#n$l?j
z8lDzgftsiT&=1l)r|QPNngd3FhG-J0EHYG+yc`N)n%R_U2-i%bTCIJW$WHur`!&D%
zLgavkr%*|R=3XN#9n}0uwR@48rquw8(zvgI-XTpIMgF2q8mnn&jnRxB1JPK`V;8{0
zY2Kl$<*;Te)l(&CT$3<gi5mCsG2SFiBxT-`HQy}9l%!~WN`q^u8W*Y;NYgydhNX1P
z09Ef~X!vy?nVJcDh-7J=<-u;YCXH^D9L+M?isx!fCmLYlgysVZADz?`QwBLt^Q#Ry
zPie9#+?=nu@H;>YG&lS)rb3PTbifp8(&-l|*36p#_0t+f6B<i2Eh>nd(HJN>eO43y
z4Zun@!hMh|(^y8Kv0P)Y#~{vWKBeoTLbKUKB{G$o4`{VirP)b=muk&7BcM^ES-2M(
z7c>q+xK^uKI33(Y%_0h3*J&;=n1p)GoU3RY(yTiIG;fE`DOT^}u!KUDz79Kfp>My#
zCqH5=2OY+@0P~Q;xIZwKSO>*8sK-0ZuA{9}io-gZwj&PZjo?xpCeZfgs6z(5I?@~}
z>6xGIQ1u18IOZ^s-n$tN_b4cn>5yCmm@Eest!A?wxH*u_amc0V&UH9NwPnX0;@$)1
zNry43p_k{d?GrSfb!eo6M5PYNGK#-kbeQ}f(CQrC?0{&!L*LJ^d&wb|)>W4sT-L*x
zD-M2NV`vQyf4>IT=ukuN#wLfIM`8D>L-so8U2~{D4QHAiuC{|~amd{S%<B$cOoCpk
zL(*;NwK;rt7>(@?&qhP9!y)4<DlF=B7^a}m4Tsp}=<If26u`deus<JYyBwF_#h5%D
zJEj11x8qD_D0(@jZv$wQ<Huh^?~vmgN5Mrq*3!9&7)L236Js4e{19B6<Bb2Mc^$XY
zJ~_d0E4@dO97D>0lHq8g6CtKd$FmPG-YmxjHt5WDY}kq4DaUch0$$`grkn$J+_COk
z%-#t{EuE)7?I@%4eTk#LC;HAfx;ueXJ8mroT8(4p3Xltqi)i;->o}4srRyByDCKs^
zaVKppFFSsrfirE6%fjJdyUFnqZPz;-%_)J<>9~3wEOj})y$Uehj(CmXA?En`4`_Vq
z_%7AgK6CuwI;LdM@!S^tKF=K`^mu;Zc$cpAmyV?rUKn=Fvjz9can1kg+nwH~0EoNO
zM>UZ2aQbfnyx8S5X%C=1olMTZg6?(_w`25PP6kS@?{T_F2d#aaLYqK*og8*zFn&&-
z(xEPYC!2P_1URi)3QK`b^XGvJa!R0OU9i(z^hvJ}r}BLCg*xT`4ZC4Z2b-W5?u6$l
zo>NX!CP8w)Qw2r44mgc5{ff?mPMH)Tj&%C)TWB0|%8f;5w9_9HwN7%%(xWfg$&4z2
zk2u-U1(E9X89lDjoGPir<(N|+#RW2)j#D9jrqe}QJY+dtr0`s}Q@jl@bDS2_Qy|yr
zYymtx?iBhl`c61K%A=IfNvF?$0a~7u@J~#_DW`k3Xe@A&7sGCuQxB~{%AMGH=$~`y
zafJI7PK)T-UFq~rB^s-ouqDST$?1{^jWteQKLX`~lR5@{wNBSc(bwo?qTphaQ;PuV
z?M}0(6t=_3W+dhRI-NGt&iaNEdjoUP<;2Z`Gu=+-Zb1L0Q!JGZ-*URB1<Y-yTB<L)
z<8+*devi|vZ_wE5^l~Q1T_?5`l6_7sTj9mtk)8cQi~@h&Qg6cqjDM4osc(-Ahi|(C
zlj!d76f~rf{oR6bP4wdnhNz_0TX25|xIKbb`=RV3I79CoU%?&v5&Q&0-<pjuj}%nX
z(*C&MK>|EIA^4eM04D_zU%<CKfhS!wrv#6vR5M=?MzvZ6g1G-6QYfga0x1$yctE6B
zV6%z}>rV@e^n5Q7Os0kJ8Nv8>Aaho*)gN4`V9qi0l?i53maSSa5f`iZZGk5}tv!Xy
zx-j6~LgSl2^AbL$qaEJDqn=RMBfLb_@;<_wRBz`i+~0`t`UyREpwVC0I2Q^5!iZc*
zngWHopMf1DoF>PZ_6lb*7;msJ{}8+g5uS07jxdiAUMaz_uLxVQ`!@FydCmfipC}HI
zCi7rX#+Sg}Ct6H7ib&BTRtj+ZnYptPf6tyrrA;5t42H~{E?RlcjXMeC?>Z<MzxwAp
zbg+8kh_evg>OvQx>ySTM_6YtskFog)I^PF(QqV`2+gX9z=>Pwlvj2=m_bXBGI2e5`
zx^D%C+{`vc(+JG&*#SD(Y#i;4;w-Mxp_;=Mqo^b^-eL|Fy(L(@zZ&Wt^1RDb*mhgq
zLPtmL%N29bIUskbh3HFp@+aVS+0GjWcYSR&-Vh149ZN^t4%nt_1s7vm`#U6)Y!6Wx
zNU|+E7G9*-zC)$wM{GkW9G+@BlGeFLZD0I~p{LnKQvf^Nc9Iv=kJ%nYX*1#vwktw0
zJGr*(?+`7p{df<^S=%iOfL3L@pMrvQwlkJN|C+7-6+oM9PaFeGi|t0Lq`Pjr?G2c3
zwQc_i<i72sg^=vG?K%(cfo&T?jN*s3JN&>svh_%V-N&|V?_dy5Y-de_S<`@Rz$j=u
zwe_Wme`YJCp*^?ljDq<g+jy!Se_`uMHEb_!4^aer*mfkXk6+pTcNYq;Z6A&Swwqm1
z0f@WZmsIcUVYki)oVVTG89>=%S3^IAk6oJw^nC5&p996uE`&b)6>PHmy9ccyb_;&N
zKtt``qq3JUy9LK!H{9-GE6@_`nrVBTVpsJs6jSYH*Fho6F7h?Z=h`j%2O})7i|d8t
zb-T+`(bsBshA`Xh_EQqQ!!CCNNSEE#tr&K<-OxxFdT#gLeOx+j3e#!@4Eie)X?Y)@
z2x<X|P$W}IBUaJ&5&TY8EH_8vF~z_G=pR>%`v;Z^6=Rpdr&5K?9qQ*5cc~z*UXesu
z<*SNo!Qk2zbrf*CrT8iXBKH*Eu7TYriY<O{=7l2UFwGNVVX6Z4VX`PK<;%SAg@zxq
zz#B0B%ul$%!~x8TOlSl$cdF4B#QeSi!`{o(*kRbg%&H?031PBt!kJL!0VNv3n8r>>
zhBH5mgWf*IcLBimGu!H*cYv{?`ojdKi;7qh8TWIv|4CxTQ!z|3liUr^6h=hBg(J+!
z+ki=BF40N*ql~K>l4(p`Do8prasfn+F)yefD1*^bFfx<bK!K$!rgH}jW;2WW;ZqKi
z@f-$G`x6ey6U=)Z&^yUYrP<D7Mt(&9vEwObkiKb}&lI-7U;(p;HtU5<DGjuUSuzBe
zVrCa@DNi%$zr#`q^Vvj5o?*iG1LiDquNIA^Ozi~dl`)@$VM^+lf>;cxiAneu&~1!`
zHxzC%YevGuK4#3<fPTz~exdr07tFkcz<$Ym*8tIBMlcQfuNcoVXuM`N()QSm9XbVU
zfA*jSL;~0e6qE>L7tVr65Sw=tpnF+wI+GmCUT?w#g|Ztq!ly9yXb`}{*-cbxwU3Qh
z2)+I677K6(*hw8Ara1N`l?feYSHysgXD<u`ErGr8IT{n$%PoLOVvAznMKU{YJ{nWl
z{9#C@vY*GH?<hNqitf_bybmx>>8vUR=8v(H=u~G0`|%w}X0jh|0m))lR6sqS&9uRA
z3s{Ci8^tCz5XVbU&M}F|d3Nq{z*MtuHbC?OyL2`bYuRN~!qCKa48i@Y>|;vuHnUYJ
z&~ITA=}zrt=Q+Zen`}5O>Ta=?6ve;IuDb`3JM0K5QtDyn(e2;M+EY>SUH02cfbL^W
zJL#=`k6q#njr*+30+#yO(vRWA1GYL5+(VZ68e@9I{;>lvk6F<}C=Re=S3%(^dz`X&
z&scsgxIy;o??Ilk+*=so5S#Z1j=o?sF2dkT){3eWhS`hd7{n{qNOe%J*&fpbV7qaT
ze}JMpcjYi-Jh*LCK);KdJOo8g?)_5q1#rSQ&=|=5DTG20cdHPRd%1i)&_cK+8_*ca
z{Xm5-VO+8k91Z6NXw!O_TSf7(crJoO61b6-;1W5e50Xiob)*TP$=vT$;FiKYiUsHq
zZs#>9rgDwxaQ`S*8-%_zPMHjn&Yft0Gsn1^Zn&1gm97I?CN~c6MbtGMiiSuICz%e+
zTyFhMaL2hX-v@VsbELkLoX7t{*4zZrJH@R}5#avI=l-J5W&yXk4%1!8HEG~}5vPcU
z7scE(Dls|DEu~+ygcH(9fiv8xNoYLF_0bWii`*v>Fki>@&}qX<+;{2FyUhJJ7LAQu
zHwTd>E{LY`9%np^>AKHlO#pep>37k=-j`fO2h0z1dzZn)D{j+LXuRfl3Xi$*Hat9a
z=daR!z=NOB4ZFMebyOPW$@kKUh~4}!MGC!m;WG4j^OX|;wuiql9w<Ki*FI49<=>43
z=g)sZ%b);0T#Cj(erP51OhLSO39$F_Z%jsKFn_cX*dhE=N>_&Re@f68#{W#|{&0RB
zE!y|-=k|fy&!>3;^Z@Td+r9|?SF8+?c8~fO*pYm1D7;VM=g}(a2=Dy`8dLdoKY=^S
zPw~JnlEzQo4Cr(dUp)o-8T|Xju$#$`9mJTj_~xC^&*u9sz>6GyW;iV6^4^y~VkcLA
zj}c~1u6BVlIg@)X0A|lSU$26Rt5e>R!9?ejxn)2Zo|Z$g%vaMUA3<Zt^!v28IWT=E
zJ+30Aub?+h<aE=_OrYgXFQWBg+4LF>WXh)xQh8v_^tb7;b9=hvQ=p~Hc+p@5Px0q3
zd%7h5zR&~oP1D}R-<y-^q})IAd-3<y_4QER_T^sSyIi;eRX0Hw#SYvBmb5kY5G;>|
zfUlr-6i`f9<6VRY0fGuzj)n^sQ)$sYf$}$uHCph9HW4ub*C86Yz?W)~QUvoU=yycG
zwS%Mzwy(uh9Tl`s1!#`oj6V%WF!NtnDij>~4P24Hn{M)A!Dr1F<7vUBAHh`#PP`3~
z^Cm$UowKeMjPHPn8i7|CIvWKKY1!Q*aFAjGt_mvY{d7%mXAewt3UVm5b3^duB9Jb@
zG>Qav3z(@G;Z4CrFM!?>^p1tww*`r}(0500bObPa1S?X}_fQb}6x<_0!$GJ&7MPML
zQ1(P{J{S4}0#B;V8x~~Efv2wo=3ilkUJF*I!3#HGE0uD%3nS>k=^-rp7y7$|K~#L`
zDXb!t-NI1XY<UTf)85ouSRVuPdxTMxJn|7<qoOunp%*<<{e;uMf~3DtXQDdP0O6Fo
za5zx--Mb(`!d@zd-78!`PrP7ZG-c&OgoU(Z2o=7;11(G#O<~P&VTA-D`-ERp6~TUC
zBNaj)5RU!<CL)BQxp4HLaE1yZk;0MmpFBkg2fxA`9un@Q@Kdz#&b#z*OcMS~Dd=Qj
z>shpB2+a;+Fqy)CGN6$q^nD7EY@u5`8uNvnwEZm*PNaZFp>Wn$z%CMc{sFti!k?&W
z;+!yVJ^Cty<M%?cQdmmyt}5Yx9_r_XQ<uQCYGIHI6l#Q3ne-ovwFt-eL-D#W&JSp<
zLf17=Y!kLo%Dq$Q(+kCJ;k~)gxG9_x0R3CSSyW7PTlmWg`hA5?bjZ9%n0FZ>y~6jb
z(RWuEMVUW0QN(sAc#8(8{w+|%zJalXi(b-uJWBMNfYu-JqL%eAaa1%o0j+7G-;+Vo
zMUCU(#WB&8FTrJq#v3vDnWCyEXe<<6Z-t2>QRGW_SS%`i6LwFFwo%<{iD>r!LVzNT
z9n6=C4AU^AGEx6rkaE$%Vvutpt8h3|A<}OKw5d|`*LCP$5k0Ae7cHW-qXBb6G>R%D
zdPIA5XnY|0=NvSii3TVl_evD`BNV*M%!4s&-e#L$p>L1bwlBf?m~E<s312fG+Nb-O
z)zBFse>33%a0kqc^vRnDGn-zB95g%d2q=*zvr%h6qs-hWrF6)wdog69&Hnry?#G(F
zq(?-Y*?#&G_hB<l3}E8T5(YpL%y#TVU!qwk9Sln{+praS*=8C!{5@s%m@0Kj%vOB{
zpDN7G$3eZ;Z2TBtHkj?8Yy7&|Br_;<nVDi=qV=xX0vpKmnVC~<`aQEl_rTpZd$bfV
z{bpY}W7rSOLPT)%q1j436dsvXFNOXqv;AMgi`Qlht#aMOIgxP9UEDx*s~-658C=^X
zZcc%MC;nqYVD1)APsQlH#b0bj-yU&+iQZ^F;{6Fg^A+!Y1H?}}o}Q-uVg)UD0>rU-
zFcBzLHiFwPj`oDe0r9yCa1mlL)&3t8uONRT#R~#yD#ep`fE*Ir(qbk?JVpk|Sn=9F
zff6UK^~3-Vix1P8n|QI6E3H2g#J|}9CQ<wsB^Qs0EgB({Aznq1wM?;cF8Z>>SEvXu
zTfCj}0Xg_wDNN*wBdI?4xL6+te@}{irePBD#1E!|J0)IE>85<~;&#|A5O4YlGgBzu
z?F+CXanU+77K_Esl>e^~zxN6TE5++Gp;0Af+8}dYyull!THH$E{Ti`>78e)90ZkC8
z6<5)byNlx38StWBY}W?vl6c{pFmYMjbq;P{5ijY7i3ah{XTdd!`{_(olh|z`{Jkpn
zUkQ8H@Ly$7{{I$=lVIYuxb!`s-4WZ~hiH#jnTNsjif>T{{jPYG6xjE~WecExUz`^T
z$$l|IE8qv>6?Az$6wka2$w%Udbl80@uG@u1H*@VSxaMwtgCedT<^chK-etbR1%008
zKhA)<X}5V{7+mx=pF-6~d(2-v0Je|$jCtUE%`<5o?q{C<9zgxg$7;a^n77f+_n`Ss
z31A}4bBe%4nU~y!$RYFFbQ?ySCocvUV=kvhVXXOL4>ZP^ZwY{h@#dcv0Xo6_4?04V
zXfn?;!hDjsVL9w3n`<VaGsXPbZOro#^Vf8Xr<(hphR9j-_;2vTmYUa5>aE6n_i4D_
zW-jVSW4rk-T8#{w|8W_1Q!Lbp04uXl{SL5li;w^`UbmQd5smE@K7mm0wJ@jT(L)Q<
zRZ8LxT2xSN>~jlEG>zVJ`vqwDTDCpF2*WJ5XTf}o<ywl%Wm$Gn-9e${7OI6Pv#j9J
zc-`{i6*&6Pa%B`iy(OQmMPHc2NDG9+lJQb_ktqpU3C!b?)pQKLN)kd#(DRa4rs+`h
zlYS^iYoPSrV)zy$okQ39Ua2o_WJ9DMzJtb4=>#f^4wwGE0gC&iD+b{9LFqR;AQ>s0
zI1(aJ(i43UiI!g3ho31%YUu!j@zN8);1Z-Qj?hb#rc)+4MY==+^`p|Q8%^juCLN}-
z+brqAAUK>O-MAcFu2f<~-wCNj1WcTi+6<sCPwGnn?o(20y2Y!d{Z1ekq+C5Fp-#%l
z(RW$en+p>S($Tc&Y?9{u2QRKkE9nt@UFu60X{S`y4-pTmypJgV=xOCr1=h=|Vjb-6
zv9i!&x&y7w86mpYsxccR%xVT@g!fr3e1a*7uo|Y9ag<f;V_FX452ta#-`@pL-st;P
z-@@S^R?s=+l|N3!zgJzP@Y9bsMgVE`$M50aKfRrV_Me*yDgUx2CK4TMr*44Rbt}y9
z_xe96mAPSfB>w)Tb^=WPnvsK%{`Q6(e{Y;aDMI7$c8qrG)v5URwkM%LaGC0lf4jzg
z22cO}mlj()1@GbC|HYdF$F$pkf4d9r4nxgD@DtV8?-FF29HAK?m`TM0fr2IU_zx1i
zq{^DTf@KjP5rV;~5IHE&{Q&ex!S|Fe$PjGU4zErM&i4ZCwBXND45~tKo}Swm1)uMu
z4L(gv-dp%PM!1wp-C~82r-2tId`?mN!@_?fU@P7vJb4YCrU=yw(0WA3(<OgQIIaaY
zGlT=D!DR}6p}NZB|Hs>1K*x<_3m<Q(+iiB3$zgWvFf)0=%yF36Vd^k5Da<fom?Rx$
zm`suhGcz;ucdPo}yEF67p7-84-%HN!{8U%ir7pE}Rg%pfPAP3R3#fbaZnMEiL0+Y$
zdW`Ngvrd#5c9~CAH`Lu`yTP)54wzlr%jyrB^;M^<LuUEoGUZY8)KFRPF>}A_cy`Kk
zB~;&!(`IG$ob(y<nED2uHIqmd*XNQssHBuGo8Q$-X|9+9Rd2eRrpqp+TV^G7)^XeH
zok?cDV?H?~v)?sq9+dSyGDoOP=ws7=vV80pW}iJ0d}{`(4A46>%UYTJy?MNc%=g8N
zaHW+Q2iUu-BikGQIAf(A-vvB;sqU4?|GpcWmdVUNjQ8q9Z-AM+plrfG^V%T!B!kRn
zYF;@7cFWp^m@$?ML(PQhN#bGVVbu|ExOqlhy^b)a%#zthnnxGOxKZX8bzf$*nMXZ}
z;TmI3D<vx(YvxuzkmJlPFJ*<}&Ftzyi5X_?kFvEh&956|+$=L<yNp|A7JDjdT5gWN
z5a8L$cvIAMaLv+nW!hS0RO7AvTwN~LsbH7&)t#oUmg;R#56#s-bz7FuAiYXVH1tt-
z%3V>(_sG&3mFX`tG_I3XHmS)vb=#_G-cz#BX0b*|ym_l5GDC}WD%H~R*9cie>q+W0
z5gm#bk(EU^R5!GH<WoP5J%?qM_z>fWdYECTaa8r*9%eMCq&|}orQUTt!KiUcCZA~J
ziX$5|$z{A&=cKa?yT8=JY-7rO+2lEfdzWm&JR?;n2`)6g7M8^<F=mDczZ(1BNpPic
zxQxud#yGu3)^x&fs6*~aV~*;GamuK9TGn*hSp7!Ud&UTBFQtpd&H^&~HKV(_rn+ss
zo-RB#T-lv6@|}@tr_A`-*m+r|`DUC9lcoJIG8B?!4>U)mmc`67CybZiX0wId;PAAr
znMq_|tFbp+=GkUsYbTqv-N^J^mbb$&)XmMEhN-$8?lN-u$*0<Fl$s|C+GBiEecX;1
z9TLbExc)E-s@pzCjrHowam?tiIwu@A>?-)Du|eJFJz?Yu(4X$AN($UD7OL#jU89!j
z26WGu|56t7+=#F4{=6_uRmUHVG3sdl$%wcm3masbZrO^#W_NWiKg7(Y9xWMbwo+Y*
z$GObyb!5Hc%{E75(&=XN*}@F-YYC~`nPzhJ#*0N}Q`JLau~|}GiYzgoJ(r~|HBYH_
zxYk^)4v*{1$@yfyt>(u&65M8P+a_z;ZmvBjv+pq5tBZ$&=HlxTJY=R*SA~bo$0|Yj
zyXoqyR(Q%R)l`;!+KiW8<~U={%qgGntobURtm&GW=a`JUZl+%;<8GL#)i?E~Isc1{
zyJfynS3-}?r!{2U6Z7618TZr-$|}KU=I+YEb2D34nf-<NEQ3t)(#-vbRM0E)VQ-oJ
zwK>bBZj-$+52zg5TeF*b2K=2lSk?1;b7()=v=8RFhq9#~&Ac7tqkS@$sk7<NX71Bc
z`eLq8eNDfbL!)GA-^}bwWZW2gyL&RjO#32rnzg`QxRZRAU+q`b#;ms|oFW{wKT!Qw
zFWKWXa>>>_voG!<(SeRMU1Xti9G%p4?^?%<e6lfn99vWmr4x?+6(xAx@v^7P_{OoV
zyYR(PYcq#{lRl-@?X$~1)y}B8@`<ZX&u{ufx0li#p9QmJN%ws|^^i#(``kM#>wNC>
zUR?pacKNJSPgZ^KIS?fq{n_V08Y%toxu>pbhB&j`V)=1@Q~fP!$9y8otDEzxET{ez
zmFj6&PMudbTD?iewyxMoK5!c&iTt-~S#_Dvt@ITc?%pkqEVD=J{4&=7qlfB+GSGOT
z4o4%6B`(#AdXzC$J?}8dsNPYQKiNpAa$vKJE4QRH+xS>t#w|9os=FXdjM?fZc(t*;
znrz@2<8l_6a;*`mawu-&&>Pv9Ek;81OS#qftey$lX6*VZvu`)9f07w?7!yazw(K+x
zZIz|$G9r7rWSZTEX-aXAapH)~zt`BHI#up7iY6EK8?L&t>;p!Mk~056W3f8U95VK(
zOx|JRcw3p|ccZ^bFds3#6cqk2uKth}9yRj!lVu(=QmZe~aU+K6dHAQ{?k&L+#>#^-
z-$`TpMb-cDl#wrn6i*xBsu$*EW8_q+x+})hYEoZUjeLn@O>)#yXUW%%SC3>XZW!l(
zl}R2L$I{5M9~!Y+$|R2rhsyaqHWsPu;1gqXTUp^#W2SmY^O+%ijnqM6n>t9WGe<X<
zg>5z?<v8M!pK$Z4EM}XzN~PC#n4>1hq<hTBZW7#Yj%_HP>5v(AU424xyrkgdw|lBe
zxSlX;Ka<KoV;*cGGh8<RP<Nv4m?MVErVX&KXy-3c`Cq(d>a)%^5A+b`n2v2S>s+&=
zTF^Z6<bIb-J>Q&HQdYgdoIXI-xzOA_ROVY`zCA9Vb+OsdDU&WSJIb$}9Ce<SkhLr`
zJGPPeel=IA{#DD(<B4U46=tCNWm;*@36UvRnZ;F-VzoJ7olLpL+@ekg*P4@J%Zk>S
zOH@~;_2!Wt>iLTe=4-Y4-R5R>S9XtCXtAttuUS{6e2<uOR42ec%otZ?V~(0L?#Lv^
z%&etlhI8hu&a(RR<^<J!{DQe+qm(Y1$M?y6H_hcmWn*rcXVen}x6NF?$b5IqXq7R(
zYvxc{r+emMd8$^f|IEH!WX1>Pi6gR656!7{WfLEn$<+RPY$jB<mY<ln{bgxS%~|Ro
z{mjg$(%;X`2HR!a3-kLj;e)wUo!)*lU#ybt{ba^aT~y_-qo{1k7xU_S34S#z{2`Nk
zGglQ8zMGRK%Q)9CdvI#0ui^IA>YzE^{^+jEIKiGo<%*}<^CgjKX4o6wk<tQtQkC0T
zXrHG#iAjP*-Q8R%@9~sR_?x}Ay7RKp{_TNGxx?Oiw6N1Y=9Nrx(4O+Ve3nD@TdF6q
zy!LdaOnK7YBZ+XzWpAo7RHyB^R6n#c_Qwrn(zEt9mt^EQyGuQyb>9ADysY<vJ<BNB
zn2Yu`YX4laA08-^T(+kxFB@~kUelCiU$w_j_eihVOP-b~uiFo)4lFn9nbeQ^P5agD
zvannBV}@+nUHc4mSM#3THC$a(-nTC}D64;9pHNh0d~7eHPLQ71XMdH_Q~Ou-`}53R
zx4)F0+mk+%#k{f)^p_c4+e_A$Wxuh<StR4W*^3XCWe;%NwaW|x9j`yixIvB+YLdZ@
z;oW825JxhVnjPxMqHcwca3pfYmNkuZJg6X>KgKcOscg(x$J%A`DaJWm>Ki!TQ9*SH
zoZ$G-O~x&E<S!!Y{mt=lm&~xk@p-RIdB8FHtZ>ZHWTOP1I3}xZ7T<jaJdmvz;XIgH
z#*J~t+bY3v&a``Fl4;J}S7p&Nor^ZPWTCU1=LSh}wzG^%OU`lH*9vo;`yb1C=Q|I?
zmknO%Ok7Gfbg}bCpe%H$GmBkqj5B<s1Xnnd#g>JxbXHp=<5oH6-<A1RJEQi?$6o8)
zqAohtIsL8*>z!NW%@g{t5Vvh3nYi{#*AJPs&aD7hW8L?`vZi{88_0&%x2flr8VoNf
z6E*BtR{q=Kje0DjWh<4NZI!0I47V<$9w6$HUiH3-uAEYq(>0#jQ{5~}{@cBe>b~A%
ziTY%H)~lPELyXtz+dS0Rtxf^P8jl*uXK;-(evc`O8E>TiRhVEz+?TDNX!NzoC!1l^
zR==Y&jm@fs&oZW|BhqZ6f%=ZmF~aZ5qSqPycFNk^#yEA)e5cV{ok8z67Izhn7_Zdz
z*9l`*Hd)v?<NX%d#w*5kb@%tSG2*^#%oCSU=CMTI8<|xV3^0delNC-hJF2^j3(WH)
zOj&^ZFYe&v5}0808!F44Xj}=Cd1n}-Z_2DQjTGvM+F8b;9Kvj4bsm|1v5`2hOu58x
zsGpzJM)zs5<!g*PD`keYMxo6z$vWe^+?|l)zY(L16t^1l>PZD`GeRE89Q%!vsz<>A
z<JeRAbjOT#>KEg<(JQHJ#d)KyO0-=th832j-7w@>E6vM@>LRPSWn@yl4Q?AHtIASV
zny1Rh46Do>Pt{k#d|6sP`5JTHpEBiI^XUgExz?Foa*FHCy}`l;bG2$^N6m8TwEl)!
zJcG<X&+aHH%(q`v`J4rI*${OY%BEV`BKy8Dskp`Vr-fzQ5__HWGT&1B`W_NoX3ySP
zCi&GKFRy&S<@V+SWqViHmu8er8}E3hx+hF<Ir6J(#)*z^s?+Br$4K?e;$+7pmC2mq
zII~H%X{zH?9a;7?NAhhFv>fwQ@8#)^!waP}!?E$X%rMi@qnfODmcy=k3k-FxsH{G{
z(^P*Fca8H!GAaG$EUJEdH#@h*l^M1;2Yi+fvBT+lsGbAc<@8mTNPC>ud&#8xoR#9p
zr0<=RXUn8xe0QkVo2~LKl~96*eT!_9(jUHGddpUv^PLb+eLduVkIXyj^5~fvvRSt4
zm6_y=O!m&)G(|S(lX*y`nTFe)m+hXZ<4!6q>nl-Zwfg-nw<Mkv%J)1g>#oo(i9{+^
zYb$eC%C5S@S6-_gb*?f)J=jxq+G3f%UdfLVufOQC{I|h)b&s!M<|i^7)pDt<tWm}?
zvH^`7SC_fkgoMj*+vlOO_Gnif+5WEc7s)hzyQ*{0elZGq`oGnbUS4vUc>ait8g6V=
zCvzi=5OujV(&(;k=BzU6?v@!g8vX}ll5IxJQ?k-MMn;utIb;l(Bf(=vWDMc7abDHW
zMPr4!X1s2!ye6f4#vrGZo*Ksr$p?LBG*M5Kelse@Qh(TNu-PQ5%sA5YZ^kK0+<EHR
zx>7yjOHGtcwpOO?wpV3TJ{Wbo%2s?d?xdH+d@&B?m4$vamadiAe;B#d6FmdW1f?Z7
z*u0`{Qw=e*st1vVo74NrR*W#K-IYluo0Zqgf~S~ggQetJZ7yyu#hqs6+cwX>Ibk-N
zE|H67x(Tw3OJ?pHvc$_~>KIZVSIjaEWv;8{nCvp{zFD=HO!>g9nN>=1b*65iJTcem
zz6@qdb@BYdylG11ellDBB1`{lCL1doJIX%%yD-kac(Y5EJ;^>bT0Z0y`ykbmeyY82
zJ`U3H&Z@JmH^$|jvZS}hLUq#n&N!vMGw+Rt)8wOlFw(0W%}1j}0SOK^do|M^`(+<l
z=NQwKTNXRk9CuMxJ=HuRl_>Y>qScj?Wj<Hk6z7?)1?q<Be6xBxDK0SEsES%>j(;wb
zt}xT)lGU#?SLBg7R+)L`$~JE_`+b)+Z8GbsGvS?P4Ru#=ml^#<)^x}m|5lcA*zDL>
z>ga?S_FYOR%_{0z=CZjhjZAsP{CrgwcGYYqxp%p=oZ~7eGhR1yE|-xv%$Id!#+&Bg
zeo~LO%(kax^|#G)s>k^qvtn!cXs^vQO=R_N%y9>Vw`SQvs!B}%1v1}zGmE;{_tC7V
zZccnQ<MfqJ_QhO(UrK}R(^OZMA@;+mWs>>!iRxDHN_*-jF4>yh_U7stfD86(s$Jc%
z$9N*sJhOLE*Ld&j6)MZPZ}#jbWXhoq|GBa;mg8heS?Eefp)yk1<=Cap>rObjY>}<F
z<0!FAru^UtjVlWq?UP>}w5IxueI%t>KI10KHZAno6e%C~SNSsss{PG&rczmxxz0K&
z?L5y}T;=ZPJBNRhnpy75rOr%NI`^yoHLILS)Uj`kbE-Nptap~VETzrPt2JdS+|G6C
zmiboanvqg@+nr^T$_zW4f!So!b~!6QlojrAc2xH?_d0i}ukwE9;3TU5`2lB6^~lsg
z=S+1s^N6#-UYX;#b3u98?mwL!>&nKQaK3TL{AZj|3%MRG^J0;F*0TPOWO<RB)rHzG
zv3zCra%HPar2NcLvJDmHsRmqe^DLRQQpjr=TlxKInXAhCRkFQR{nQy_HCOeo^4Y6T
zP@7rfYbIG)&Ap@LQ`IunZSLC6!7^!`zGr0-b-$_e`+9|1%A)H}xhrEER*5Iu7?sFh
z7S!mj>gv>Z+Xsm>Y3`CKn<iDS3~CmAN0!k1!!Fsx7It+W&~nZ^nX*-%NQt*@*(#<?
z+9n`}6x!ahWOTb;>bunbh9&V1xo1hF<JL%7Xs4tPWD%XG-;hn|QbpZ@j2@g>;ytcZ
zk>NgZ^GST5F+n{tIKrq>SeCKJkUWIV7U^fR*=^sfVs<lMwi5a4SF0}ntB@mmiEd4r
zN0uxV6%iH@9v1PpSp81zy0vWGA-cZR!C{t4+oN@d9NE=$Vc}uf!?WiI&y_t#M6U4M
z^}BZL*e<$$lhz%wg@suUeaz&6VPP`p`Ja`*VW#-0D?H;cd;TA<Fx~(0^8Z$YZaIU<
zWzT!iX8721=gO5WTX-QKf1Bwr8kkO-Vfe^*Motf9@4l5O;uq@XV;^?GC(RX~<k@^O
zX7fp96$>!4C!8x2#<u&1`6Mjl6Q__*(n3B73KjAREo6-jFf$nYt&IU@o}jxjQQSg4
z_Td*UT(W!v&6Mc^|F(j$rr|Js?Dhe!FdrkO!|-f|eXzS-pgA<uie1+yu2s0OJ(d+V
zAt<x^Rc5nmCM)Yy|5WaNHO)hYRlB`UOzY)+Ux$^jnr{+!@!ICT#=%ih)v82A7LTkR
z6%`upwr?|!CUbwkU>1yRO&TAN%*wXHnbbYuvH3Qp)v>gH0{7rA=GmB5n`41FtSvKq
zLfoT+?8$wtaXSN2SbM()Cb9O%v4621pYqM(J`vYGEVVm2uYFruD^>5{P<OqC_M~a7
z3bUPl)|k}+epbhBzD}!QH{Yc05rgbQeXUBH?D71vM^)|^9U5N4U0{^`S~_cKbU<7y
z!)<4<HUE+$k30E#`z9YN<!MI-%jvdHwjRIn4Y7Juw<oaX2l*zjk}vi1x7Jp-`&fUv
z?QZM)oq)pbVO#8(oz|-U0g2pqciA5X`9?+6C|0$49?Q5Uvvo299M;Drej)DDN9`K}
z3zo>Atwwb7F45VVHty1{N4Ap9quX}v*eP4rj#<05YM!-y$BrGc_2}58ZFHx`O`FR!
z9kO<99^ExsrfbrzrF-=SyL`5%U4yc@kKVAKH?5a*WQVx?gHu}jZrkTt$IAL9bT_(V
zzZlCJINCpa>dioZ>v<o$uQlIcce*RSv*&7R?d#$j+gkp>5#QQ<+RtgPSgf3TRc*)O
zG}eOK_LNrTevWL`x_*vn)_{WnsjLel?7>#p6MsK<yZ#Qp0PDzrz~t_MBOG;OTGood
z81A>z9l7n!$ZAoM*-Kah??|ncycU?pU2L{vTnhKK?T+_>*251zLGF)-9T@|x$kUEj
z?iObpsh#dymmDV(`&BJbBC2%xVr8tDvjXF~&3BHc{?`5ZJ~6BpVW!h3G((OW8QsPY
z$D(HL6-|8x*RsYp^9^%n-R_g#w06u2%IEIC(<fF!t8$<{p8M=Mxxh(NwRCt@TZPIs
zqN>-aTq-KEYN;}jl`85T9+A6-ElO=>gw=VlPf{!98@s>NXmDVV^`n<>uvIvrGr%3=
zqV%h^hSzpvb{~8yCj|bbt5qlwRlIuD>{gMjeo3u%*8)P^%U<}D53v$;2uS08^Udc~
zp!MekGu#>x#~xz+h?FJes}PiU+AqHT?z{oc!Lh6!%jBz7{BCf5_vIwc+zxl5Q0Mem
zR;?g=I`{er=k`!*VG1*@bs~u~&|055D3kkORcCCwRXNn(kz9S4sM3{cRt?vmAVba?
z8EvI%SC5P;RiSEB1*=mnXM$<Re4OsgHJx`1cbeMH0J}BsgntHi?Rw5VsoiB<&O&M2
zix)X>__${+ch(JX$Jyw-E9tLo&c;4gRJY*x?&Z6k(WX@>c3>8Fo_)?LA=aOteM8+N
zPC66CwLXNIG2GklIv@F1Y0CO$vpPNY@o_JI?ED&P-Q4IG#|oD{<h~f_TfU%`_OX9D
zt4B&lu+^xnZ#(Nm+Msav-Lk$Z0<4hQ&iMX%n=4n1s%*uI86XYmNubkRr<!jjUu*n1
zpPcTcb$vIPR{ZHfF)jad{>j`U8~8eXt(KR~7}lO$_B8ID&3xAx)^9iLiQFAp_#O_j
zUj61w?rs+C`^>P`?DUOkP44D<&+76yIE8ycci+?*tR0nPH@%wcyE~5cVVl%`yDWY|
z?q?f(za_V7Op*iCFJ~M{-SJQRZpjcgDoTAts#Px~TUWJI>B!o0jB-Ew>>JlNPKja_
zqe|zfnmwv?@m!wz&*e^U`jt&?<=GpY$UQ#P?_{85jFXx;F+KQK%eQ<`uoYS`(APaC
zi{D^hD|Iq^9Cw|ZetC0RXAV0OxtFx^tDN5&T-P^+JKZ9`UBT`o>-|PLtz6Mkwdwl?
z1iMeV{n912n!c8UYraa35G&O53veeq?HBEE&p+?C#@DGgD4&&bq&<msvXzgoyYF?s
z5%H{b8+;479dG@75?GOiq-o!rYdYOk1O1~ztaeqM+1wu!`Nxal&YaP|is7D{$-k9P
zf~ctCk!8x1s#ZO!Soz2@6)Tjgs1D6}-9F*|*&WudtEST$Bk!WK_RaN8>299W|AVj9
zvA)CKYS7y+(ApE*-)SAc;FHB_S>Hd{-M^s!OMh#~B4?<3SZV(sh80%NnaMr0tpAu4
z*3bcd@!W-4`KJp?P^(tSGEpU}MpX~}*HBc2=(g^uUHzZNx2kTJUy${q{U122tPSm9
z?sXIV`#Ic|ruz3t<$mY(Z(z6b<n+((?z!DReca$0)#TtR%gP>AKC+@^^axI5ecEgf
zb{{_BpWVlr{nRI;JLNflM?5RuWcdayblWpoyT{5`wen;Cx&Bu0D0?>d^Edvz!rUEF
z1zbtx9#|@1Knm;qDZf;1qj^9=f6Hua#<s%tIsM&*Is~*2idV8k1!-~BYE+FXU#*7c
zi;%a5m9lnVQul}60h{dB@%?5(_qF~3n_|W(Tdh=7&0^(ilnTwBD_sAp;a)R7AW2I1
z*>wT)1FeIJ{Bu~=OJ~ewlXe6cR-<@!IS}QQ3Vr7G_p>6BIpbP;cLuDo+JyRrS|yv>
zW4ov93V7<YVzrVV#)St1Tu#d`&_BXDJv1P;6&d9(|5+0h&zch@qdOl97@NQ{1_zgL
z7q}Z>hQ;$#RGI41^2${AZn(Q;?7&_rtRY36v8?UA15&x=`6!pu-8OIFD<5mv1$zc}
zbm730{_eVE18@6Uu6~XPcjd}~y~5oO1_Y)sts)zO0<5;B0^(VrCw$UcC)PRq+%pCT
zUiFKwzMWM|R*#S)meiN}iOrB#j^16z1imj~oh%>ZV<mGr!`usw1$K|=?t3k8Q4Dwc
zXMysC3I86L(;9v%Af9{5i$GtyHK~<f9A{Ki$qL1?Ta6c)iQU^?2lfgya#$0}1t)P2
z{vKF9eKI+WM^&pD5ml^Y$*Q4$E$A=R_q0KC;`^%K%@U0}xMvm&3W;s`PV<lHK3Ory
z$6@5NIvarr+~=wW#g1vOQLVUjJxg$WtG)b`SlJrc6S{vi33?XGs?^FSzB{5@&_*Bk
z$KF9FeXYfAzx3{tgM#t}TM1^#ucEogFO9EmlM&(8`UdvI*2|s_U-!TXK?MS>3pJcs
ztp}%_G2D*XL6`Gb^&0qQbiX+h)H7H7Qq{|<4;LwioT`zfJT;ZOhI_7ma8MTOg3FBS
zKA9_cx#1p~CwPY4TL0FO%N<rAxLIQNvKql1?N-D6vR%dM1Q!pqx?FR{wo>NwORK6c
zrh8wr;70M>#d`<u_Oqhv%U7x5V>6wV;9Q^_s~^hOxzXU@`thta^8%dK`?CSD+~Z~h
zFHWxx^D*7^_6DDlbGW;~S3<18&4RO87w*a-w8fj?AUP0^42<Jm{5klHPu^S+`Lagj
z%Nda|G$JA_M_5FtTqI-<&l8c|W($(j(;xEBu$g^Bf`V-c)%hy_a$2#BkR)k$NU>Om
z-*9uBQ7oi(v0z`bdWc`K;NZVb+G^^%kUR;G{dLL=YRbBLN~@I-@>Dt!{`FrLTZj}T
zk6}}DnYNrZxmmBvt#moumVvT7Ff8M<%iR;3EsOl$^Y7n7s%*D~$-7qn`Y%jRzwuw8
zu<(BkssXz#{2w!f>lqsTYpQU|ZVyT6qt;s9s$&nyX6&&>+CwsD{nr#SV7Ey!_b>nK
zHn}7Imw$FEr6VMcRoxL1({lKRgc(Jx$&QdB?$?fxP}7*;uI3xk(TpYiKmPL1Zkyyj
z;~&!6bg3GMWy@rf9#;BaNnOrtlRE{vrX(q0i!F7si}7lrnDYO_j8}Uuw$zN|GXC{X
zjlcbm^1FYOzk13pJ(HS2`o8KF%Ei4bFt;tKl)eAd`0#&}3;m;9?jPj_|0vtqH*Vb_
ztf?(cGh3RjwhFbQ%2bZ56qPu#Lu*}<)*2DzEvR$!oYvdmkjT({IrHVp9o{@g?tBqB
zo3?12H*enN5qWZiM?^Gf)+|rX=DFPsLPFyBSu^8@geB&%Vk=v$yl3gvJGN}uu6gCw
z9ju51Aw68uY0zd1m~GSFf`B=mmJuM|DfRgRf^6zf-`E0zZ8o`;X$zQZv!zi=ra*lW
z%^6HL-)8Hg;tOoHzRHC*n=H~6An&tTO1YwPvCUSSawE~4A$6Ts1(w)s#TijvjhM*-
zW$p<ozRYHmu0~q5lg#8cn{1QKOs#f|$M~o=)C{%RQYqy>>69sLHuVKo(@X2u7FD_=
zAa@ybK(AQJlG)Ma#@GV8VjmoYY6I1RrT4g2ePUIX&MjJbDoq<8tzN|wU|P|o0+N~4
zBcz9vwh?x~IViUa_4o&v#PpOiU@k0<4N*FM>-l=(P@H7SZGN=@()~v(H%zo!@ero5
zd*UUq0k*-RI31VZ2HcHu3rjEm4XVGNt^@LnkhUXAFHT*SE(2P5<Vw2^<)KGimK$c;
z3wRe_q4asu;{zq(q&}$han+{9?2<Cpfg&iq>~&fC9%)-(G!8)Nu&l?=M0rh*F3Vj^
ztvq?Dy@HYt)a9~Hk2TRHowM`^c}0#^-YBgdjuy^Axu2`YOI}#J4iBR|7^UNq8PrOC
zQ!9Pbw5HrJP&FZ$PNmBxcg}P`x=U&EU^%Rf&9Mv04O%_@7+i+i@pqKx^7M4K@dbX<
z%KlF-4O(rHbkNi0#Zo98YIM8}O1C9lmUn$<N8@x{g6h{pEq6B_!%KKysoMV=0`fGH
zo*@_$qdah;<3+F(s-wGFfjm^Ct%d3+uj1;qjZ!+SXb0jroF(e^FOR0`2{z$AJb}^;
zMvs>ppjvrQN-G`RwDM99Z8FS+)lnYR)#E#359}vtZarc!0l90g%M)-ps@`1clk7)%
zWLlT6;bW8=r#kMC-w!o?EKH8_bh3`;!&35RCUl?*0l9~y%WbhI$^%F`J`Y!+ylYFx
z<<SQ18N7+l@C(M4A2hXL2{F0)`(Y}O1~Xwe=Ej0p0;^+l?2P?!G)~7QxB+*g>lg!<
z@IJml^)sh7Fc=eKdW^&x*jOn)%PlB(QOd7r56aVVqeqwR1cApGAm^uQg=w)MR>Zp4
zL@DR4-Ec7RQA#;So<VsT<&Bj0Q$DH7vj1-oc*q1F@tZQ9oS4M$Y*4ULe(V!cPN9_l
zhfyww<%rj&+=_B%%7bvMQf`RYrW24Oq|Hp`Iirz>ne{b+T0y9a%Zf87WrM<%@(I<6
zi>d*sIGdVYdLrr#(kCD?eW)tS^y!o`eO9GRZ&#-BoN>9#G@er|Rpqj7Pt_~a+HBb<
z>lMlPqN*%Qi&Un!*{U%<3R|Jv-Pg<MrIf9fO17C9ZMLDxOg7s%WoDbrQlrc)Hk+LG
z*-Y8I#Y$PxYGs(s_M1|+Vkhx~O8NN5l=A4!Ii;LWU1R)1e6Gx4v%OWy*}ADtSaR8H
z@?LwJnOlwvO1XkaERR{+O!;`BDj=5-@_d2K%x|;FZ6}*qz-Ci7e9eM3o80cTnT2e&
z3d+JZTP>w*Xai*to2{j?sLdw5+HGbro2`$sxXm_1S;A%;uaxPhDoe@<kFu1__N&}x
zwwa}Ewl&H!Hrp0uS(|N-Qf4@$l=}8jpG3-X9MQ(Y1egqE5<OmOTkGA0^5Jz^K9jZ>
zx@4U?PyxOBv<_wOzHLsqEqeEH56b;;Fpk9WI2C8%0*@}+G6H&^%jWBSE^Z~h8}+`I
z_)*HI@B(_j19vDt!WZ}szo4OOSoXiK9*|~)aWE04Ky|vTc0p#0z&uz8^>;<4llz!@
z`bt;>>!G|?%k%rMzdSO7^xe`kL}M@1-w_!<l(O_o*3(Ty3%#f5izqKg>3F24--O$7
zuc&|j4-=5?Lwdq9cnNRdJ$!<%@B@BB>3^h`BYiWqF;IHb=(6{^A*J{HU%HLx5m_+@
z=EEXb3d>;?tc4A*DYi!GJ*}579sITO?h)-kdCiF)7*1d;N{?Y3m;St3?*+;d$}4d_
zx>35k>FM|55j=tC@Cx3NZq|B+2PiM*(B(Jy34frE-7`KAV_^bJhN)2=UDnH!r^K|m
zQ2LMRva1*a@(6?uR6yyrrOVPcNgIXImqC}MgSS?m57J66W^F$lj3aS8PQ_UsUA6@T
zmf>pr4Y#8A8tx$FqbN_~=oMeUYj_7A;R}==0(yGs7$eI5mu{~*;ETZ+2NPimln0pf
z^wP;dD^I6t^I#z?fznAqkFSI^u%1$#|2HPk66L8JJwr6gtD<yS9*NKnMd?bc%M;PU
zIq1D;mA6dj>7@6nb`#1Q=RECyFM-2&9M7P<_C(Kk1MlGz^j__Lp!^N(@~fqen9>hK
zE6;LjRo6TfmmYPV^MC21ssrgUE6PKPI-U=`SIMO)mqU5vTTfRD8(>pxjU7?mIHRZU
zBi-EffOLS=N*{f#_wsr&<rz2+m!NbT)zeGIHLV+W;(k1WC-59z@m~MmBJcp8;T!yf
zKhQ@`7F87nqV(9)<ph`vQ)5PyS4QaRa-pjL1M*n29#IA>pge4$<I>Yp8->kL`a|k?
zXOu^2bXoeVX$Rv-l*ep!e5yy6O?n~ezyg#$ow~dlf5WY~8xP`9JcSqV8s5Q2C{Nhx
z<$Dqmvj3$&s16vu9;LgKE(c>Al;=%!JO#=_j=G!~BhZ_`C`7pgMq(wbp;Ya^9)ZT#
z66HNKdIj=c18pz#W<G{e9*y!YKRunid`mkA7vXYTi<?CK`|nMesLq_~OLZ9K4K})b
z2IbiUUA}?$Q2My)_$&N?o)n8*aQJz~%aZ|mI_Zz9jVF)U=z$~zQet|P{-=7pJm{;H
z9_?D`>aX>tXv$Hpg0)b3%<JizVr%S(-Q+bRdV)R#2I6p(PN91IWSoKX(3|U7Nm<_1
ztf!YJU$r}NKOVsoc+SOuJXWk{xP=e!8G3U>pD6!8>2Rdy3&dC`@AuGg>0zx+jnc(i
zm$RWO7X$J{h#pZ4<ymH3u7K6B4n|>fY>V>bkDgEZMr-?_ymmpCN1{B>tjaFiR01j+
zrM`Uf(gy7^T#disR@{vT@hG0c3wRChpf`#2LYHO#zhlG~G)N-(qIAF48x#i<p*#ey
z<7qK7Mxb=g)#D3c35>)_O4a^r5U7WZQJyB!3uuqgD1TK^$EAy`R-PNzO7~2yyc<F*
zy(YDDa1qK+h>ojkN!|Yce_c$LVZs01wPXvXYcK29Tk@aoY>Z?=?;Q?{vfKvJ^DV(u
z=)HE_MtLv(jwetayVCPtllAL?y9A!#Yy5;Zu57&5it<E(o=<u}Ym;JX)OiHiwccw)
z=@74{D}vrTE)~4jcGVf-y*O+_xixme9@rnf*M#!io?gLZoQVriUbd>od#?pIQ+DlS
z-~b*)>Ef+t@LmJnr2GJ%<2(F{-fO=AE?8n=LQH}3kcnEp%jUi2lSgOt3Jak3CQ>Bj
z%ILk;^WI!)PP`pPV{aUY>WLwBd>N0^w6g#I+8opb|I^m+znw1=-=)9Jr`rF2TH)U&
zl<6d;r$0d=48`;)2{S$3o9mIhl`faSU$6?+7IpiNBJh`Xsb~D}n&m$?@IQSJ*>=6W
zjHnZs63pXm|B_MD6O_X8_`hAjf0yn0uLmgF|Nm9COWlN4->F5o0@tH@&9|OlHy*;{
zcowhVZG4Fz@H_r*Ys}@{C;$7Z^KAHks=5E+hPZ71{Bn3VMAEdnW+dyXEs5o@Dtb4d
z5#^TH0lQ&e9E_v1QvVYPOvib+6upVbjg+_JK0Jaa(VLLGPWc`_#W(m_soK9M6Dj$4
z4xuqn9xT(JJQ>Ox2z1$-fXq%g9~Q+jSP{L6M|s><&)*c=h`RlECeRbTKT5+Wk41S!
zgI>Tals|Z=%icueI?8U`g$MB%dh?6YpTP6`|KELC{=4zs?Dzk4x_^J?WdE!7>HX4q
z51j?rN5$~J9ymPndB1#7OxGOSVi)X%18_KwllAKjn2P`H0fXsw<9|9{I2j*|aWM&|
z!hf~@zZ{eG2K}c)viJT#T^7(7TVY4+j^6tMLnx2NNgiFc83g9zGF*e3a0l+kKkyV@
z#2a`YpW$2lg8H72%K!QEt&E8YFgd10dAESBnH-oOi=n(gQ;+xN`{m&;U2cHQuq}2`
zs`l^A^ABLea2$tIaW;DM`zt7~M}6-|mbaU-zIP;LZ(3je*oWSrD|lPf?f(&hm*~ys
zf2ZuDPnD!=7RJHED0zInU~fO5Y?O1OJY1^B%R}p0Z~9)|o$qP?br{hI<xw&{VF&c)
z?d3&tIzAZXX*OM+h||%Vu3t)dHEzW1xX+va_vYzOGU5VW$9wn`z3KVSlnuLQL;NrX
z#z${j-rJEWGx6*$2IQ4C`jZqzZ#upr<r-KYo1(V|ls648uSC$x@h*25<*_L5VAtbG
zzuR2$M?Q66Ij%!D?m}<c{TSsls2-eFN6=gN5WVSkdBKJr{|z1Fh66piY_SP=)9j&?
z)1y4at{0FC3!*o@{tM+QC@<C3(??+o^k&uNNo74=-W)AT`yWJLB+A3ZdIE1cUEX}C
z%S%xHu9PnShVmS#E_<`+zf(Se=kXeP`-ti6xoZEf8Sx3#6^W`+Uz8W8>9RL%E)S6E
za%#+k5ttXf+49nqE1*0Hs^_mK>h>>B?&^RyP2P!e5A2UaaSVF1<K9ka3y8~0c=Ynt
z;%4+_#pMxUJ^rXS|9_gmCA^8=Y`DDnQ_t`YzoK1!=2T6|izKz)EO<i7DKH&o#hh3`
z{>+G;u{eQ9tc<m=A$qgk-d=Oj#CzjF9D&|!xBQJCy&i8by2X@Nx)|7i-YoYX%HD2u
ze^Ne&@}?=hKyP;YG38hI5r3e(BT7&2O=`<C(7NoBm(A#bROs!7Cx0+Q$GzF?!jwy4
zd8~%=GAKR0H;LVfa!2fr{cwm!m(82Kp2Ub5I3K<J`s5vZdIc(Lt@im2+>d{tyhKlr
zzlh#s^?l0E@U2$%{}%%C+EqQHH%l!~$Ln$e^!5`>OF0XAlhgSr7ejfGx1PTe)<kbo
zx|u4g_TQEf@}3YqLoXbF-ek1ApH+{ainDPMu0U@RTHYM5r{9f-@Hn0ob^G@wpH=^K
zRke@sC4Ru~=uJ8Y`Fp01gWe8{DJgq9E_##AxrrA-c|(Hd_ut!-QQnQBH^7@@ZbZ2y
z%Ihce_--gK63}IDa#{Ygk1kKd={OJNaeh7Cn^WHCPy64_2yf5FBa}~~H<^5$@;!Wt
zZ}2mEbI5)Ho)yNx_?QgScyqYk<Z*UJ<iny^2Ia4*=}+Lz8P})W6x*P;t7T8h-t`Ql
zJk}eZ!hk$buNSOdB%r<n-maJHD7#Vq8iF2w5Rc&*ls6yf@wf0HzQFhR&7<`H5A@6s
zh_NvdhN8RxQ7<?QbD_K|OvmNLjM`t&+oiKM<tS`{?X|N1yAtSwgK#8HKnv&M67=>3
zmG`~q4cLbA1}a_t9Z%qSlvhZ4+P}Q~L{InxU*jiK4-2VX;)@{|50heQ^!6c*pqv+r
zU}>x%>h|yLOj?f-O|Ug~!XD`DWIB}c7@UkVaRL5{YjHE~45IxXAaE2<qqkG)P0A1O
zIljZMXqU@fRa5GD5oIh)h$%1~W(}tO=Oj=7i=(%9Yh}u{upu_bb{LJlaUhPs@i-0V
zxENTBD{%vE#XWc!|HN~674M+8H|;CRAMpn|Lp(L)3T7ZKCc#vg5yLSL7RFLo9;>0Z
zn{H#ut*|3@_vo_qBQOL<<0SO<<DE}g_ve*;yN2>6+=04(uZ;hL@+rKCy1TE8zpu-(
z|DQ49Eq+1O^;Ug}{4pjbz~q<~vtSO)kHxSoR>GP}_50s|Kr?KMU9cApz~ML!r{Zi}
zge!18Zo%DnNYw5BIDxZx1#jace2E|MJNm@*)Kn10!NiynGoYNk>zbA0o9Flce|qB}
z8#Dg@OViQ*JG0;(=*?OUraThIqc>eQi}C_ohO5zgLvkzS-FOg>%KCLxc(YjE<ncA)
zckmIu#Q&1_Csh-KaWFB;Wq@9fG=Hr(AL#mLLNFr}gkv83KgtKn`9CWlA^4N?fl~i}
zPYC|xe4sx6XCLW=pd1f=W<Jn!{?7)egrGX&{lt7A=l`V9Bq69b;OFH7Y5)ID2zoZ)
zr{x2^dAffk1nr&;_*wZt*FO`2KRF*L=l^8ANC^Jqe4y<Azb6ELaz0SC|Gy;!rTjDV
zfu8e!(rGFosM`Ne%m;ef|6dY<dINr5K9KhR?}VVI27X#T(3}7JS3;0{-OtJgy8f9E
z{K@%1IsYg9Mndo>=L2Q`|2-l2lk<W4{GYU%P6$f#`<eMb&-p(apb~<r{r|*#pr`%+
zB_XIc;OFH7Y5)ID2zqMZr{x2^dAWZj1WAwmtbCyBp9#UAoDX!_{*e&;$@xIp|9?*i
z{^We1YX5&r2uk^9<^y&6|7$`}wf~=(5A?MEza#{8`~P|QK-&Mm6M~-h|I_k;-u&Oc
z5`yICepWuv_0NRhPtFIrZ2w3I{^We1?Ek+f1b=cqP__TRB?P7XGxLGE{r@!~sM`Ne
z%m;efe>M_>xv>zI#Bx{_>tG{ni5;*T_Qk<C3Mb<9n6&?S1eW4z+=$z8A0EMzcmc2D
zJ$#C9@G}~c@l-YK=VBlR#>Zrs1~X%J%!fs>3|7P%SRb2W8|;j(p56f*hGTIG&ccPb
z9M_>6ci}-ihG+0H-ty?OJtXh~-{UuQ#P(EGAjZZ-7>emJ40B;YEP=mZ6|L<5+61Do
z1-8eo*arvUNSuHc&c!9T3V*|GxL2v#|L+7&;CZ};ckv0n#!skT{Gq-~z8He>Fe#?S
zOc){R_MewP5iE@rusYVmCfFJ~VGrz&LvajF#+kSv4*CCI39QA<xDyZHQ9O;8@FqUM
z=lBl4qFvJ7s-^-kR$SVDLINo;9cIOxSOAM-Bv!^+*btjzJB-HOIMBtw2po^oa1JiU
zmAC=7;vPJVf8sg3ig)lax?VBx5r3dFo~NpUF)k*-RG1ONF%K5TQdl0VVO@_dTVn#P
zup@TIemDe2<0PDc^Kluj!A-aW_v0U0+5e{qT*MoAAD`h{{DNkDPYwBFOiX~uF)e1n
z9GG9J+J7+uWw8?0#0J<5+hP~&g#&Onj>D-q8yDdUQMdo~1h(LAJcP&bEMCFe_y}L(
z2mFpc2|P6wgmEx&0@{B{0vRwH=Eg!;63by#tb>iPC3e7W*cS)ms06hCi3FzOJY0&a
zaU*WWeRu><;sv~p_wXsc!Ot!RjD(&l^1~PyACqAk%#7JF9~Q+jSP^SreQb)ZHVkye
zp575S49DUWoP`T<Ij%!D?!tq349|FU*)9{fg%9xszQ=FqNaU%hK#YxvFci~c80Nx)
zSVAlN{}%#Pur@|v3v7>Fu@4TykvIV@oQq3v75=7F?SC7Az4$wx!1H(w@8T1Djh|4x
zDpj8kU<k&;q?lUN?LQNN2+WH`uryY{>R1n(U~BAzJ+MCx#W6TJG3|dQfd%+0uEou`
z6A$1~JdKy|CO*LD_zu6KJqhhUKyHJpDvN~)F$Jc>te6uEU~!DZ%2*2<VsmVV(dz!Y
zT5)e2h$C=3PQy947+2y3+=_efF#d_>@G83QFz^^(;Ya*|&ZM3V4aT^b1XE!~497fJ
z7)xP!k1ks^0(G%5w!)6s9sA)B9F3E32F}N2xCS@j4z29}{RIBNQ+N??;C+0CZ}AJN
zSNEx1>5nln0Vc<^m_@1De+~lqu^5)cN>~#cU^8rsU9cApz~ML!r{Zi;xBo>1R^WQv
zg1hk$9>=qI1#jace2E|MJNhK|)KpM%+J77Zi7_Q+z-*Ws3t>qthgGo-Ho}(J0lQ(}
z<h1|61V-URoR0HwDXzwixE=T55j=?(@H*bZr!EHG;Ab>ac&f+`V_<wthG{S}X2*P3
z6w6>mtbwlj3^c_y*cp4G3y0xYoPx7(Auh*t=*C@m(4)(CjKCSZjJNP1zQFhR4IQDL
znhM0&m<U5LJ%(W}t;=RBNT3A%f>p3KMqvwVk6p134#JT*0WF-1OO&epuOjdpZo|F!
zJD$Mvcn$C36MT)I(3a9uL%tY-@kHJJlM+acnJ@zLVi7Ej6|g$i!zS1oJ7Ev(k3&<^
z{>KoQj5Bco{)%gHGw#F#coa|LCA^6b@HxIqDf?d?v%eCsr}C5oFcv1n6qpXPVoof8
z#W4~qV=Zim&0P$%!)WY{191e7$7whR7voCYfLn179>zb>b&i3ncn2TjEBuH*&?&X1
zYAzV#ViHV+88IC5U}29gTPXtNu^QIJ#@GrwVt4F^LvS=s!WlRpm*E<%?Eg&!cHn;e
z15e>ayn*-e8NS6YsNSrr&j&CjCcxxM)&A2G$bvaAKNiEXSP5%l18jzEu?zOX0XQ7T
ziMstyB`_No;R;-jTW~iX!sB=rui$NbgfH;}eosUD_etxisvwMmi7_Q+z-*Ws3t>qt
zhgGo-Ho}(JAua8{8-cz!7)RkmoR0HwDXzwixE=T55j=?(@VbkEd-xRJ;Ab?_d1}ZH
zV_<wthG{S}X2*P36w9EiA_FzBJ~qWR*cp4G3y0xYoPx7(Auh*t==SKc?ILgxkKq}-
zjJNP1zQFhR4ISw{H5G`lF%gDhdadmLFao)-AeO*iunN}3C~Sf4u`Bk$K{yg8prusp
ze=dO~xC(#6ZMYYI#}jxSui;&Mg0Jxt+A?@*$XC?uKZHO$Op2*76GmWOEP|!60#?U*
z*aTZ+C+v}d_TQhtP#lAkaV9RnUvVvN#+`TokK$>(gg5a)2HO8~0`KrE+NC?ZI)(>e
zEKG<gFdb&aoLB&hV<c9_TI&59Y6T6kIkv-S?2Q9)1dhjPI0qNwO5A{3aSyr<Gw>&#
z!>f1)ALA?hh(FMo$@4*iF)k*-RG1ONJ-Tdp2o%OrSRSikU2Kf4up@TIemDe2<0PDc
z^R=@7ml0Tln{Ws2$3O5CUc?)CAD`h{{DSI@_xgMQV=7hqPe33!ro}9n1M_1sEQ^(}
zCN{uk*cQ8BFB~B1_CK7!IGl>JaS^V-^|%Fh;~_kbXYmT&#z*)vGwuHaf$!*(#Zy&5
z7zYz$O3Z-SFgF&$l2{I_VjXOhh4$Z)KnLuGeQ_|3!ihK?=iyRZjT>=0?!zN^(#609
zypH$qDZataXk_)&kRQgt_?QgSU}nsY`OsCAfihSTYhZnBifynn_CyyB!?8F8XW>Fz
z?$KpiN5GA{@E{(;Gk6(q;X{0Z@9`Tt!aOw<h_Nw|R`!1=f%F)Lxv(IXz+bQm*2XAo
zf$gy?_Q63oQmNYi1OgV$#U;23f5UCK7k|eScpk6eU3`MC@sp_Azk2<ZIx_iU2*$&t
zm>M%-1m?veSQ;x}b*zU?uyr=te<uPxus;sPF*q4#;sX2?*WzZ}i3ji~p2kbrX#Y0}
zJizDp4!@#3+*4Bl7z-0(3QUJtF(($l;uz^-pfc9NhS(h2VKnx}fj9!k<20Oui*Y4x
zK-X3V_TXXs6VKsQyn~PN6@J7Y=#22xR4~THB$&#h%a)NqIOf5^SPIKyHLQz`u@!d2
z?${59;AotrmHj`1z<gYWYj6|p!2S3Kp2CZG1MlNAe2ZUD{oxwj{{7W}G{2ab0Fz@{
z%z`;EKNiEXSP5%l18jzEv5TnNe=h<9a5#>`sW=-K;R;-jTW~iX!sB=rui)+MwEss0
zUg8J*jy^d&H57z#FfpdY444gbV<9Yw<*;fF+J7Aajj$zlz;4(V2jeK5h|_T%F2&Wj
z5x3($7XwG|BwoPlcn_cA8~lt$PEQT_VGN9q$uJFOMpt$Q@?lXdgB7s`*2kvU20LR<
zbm1@@i&JoxN0)6Of#tXk-M9-6;xRmfm+=-p#25G;zo8?Sr=|k6vj1ZfNQ9x79>Xvf
z7Q_<x3s%9}7=<mcJ$A)DO7;6ch`>mkfELchCAbQI!)>@1f5#Je9<SkDd?M=h|C+!j
zl)p6VIUm3fjE6}vHD<yH%!@^^G*-asST8s2zX^fX*a>@Je;kTqa5B!s1^6qj#m%@A
z58%<<wExotF5yjlfY0$Aenop8PfZ12EKG<gFdb&aoLIocKyi%3%2*2<VsmVV(byXY
z;s_j%({K(hM%PLPHsDs=gNN}?Jcn2D4nD?L_z{1gGq0znf-$Z~mn{i_RG1ONF%K5T
zQdl0VVO?yDt*|3@$9_0OEBk*mfk`+6=i@S5gPU*%?#Dmy6kfy|cpsnPTcv9MUkIo_
zK&KM~7!wm<a!iX^FbC$xVptX{VNGm+%|zY)+Y;!4y>I{y$8k6nXX7GVf$MP#?#4rS
z9M9&X{a+z)8z13I{D9xlC%>nrf-nvy#*~-=vte#5geCLS{>u@ligmCNw!{wD4g2C?
z9EB5cI?ltTxEeRQ7}$>c@Ccs73wRyx;ZuBrpV27bsUbg%f$=dJy3#O^8M9+PEQ)2Y
zBG$nA*c97fXY7eC9EM{(x@=Pj%)*7Z9M_>6ci}-ihG+0H-ol6Y0^j2|t?YkCK~Gf$
zVr)!=p_m@SFc%iY68H;N!P*#wEwH^(wg0XJ`rsfOi4)Mmxwr&Z;cvJN_u}t(0?*?$
zQMdoQ1fJk){Dihbo*MGS5R8XOF*Rnw2+WH`uryXEMEkE!pdL2C*4PPqV1FEnV{kIg
z#0B^(uEou`vk>k70D+@;8ZY5Ze1OmK9ezc7VNXp3U@T0CDKH&obuo|=3t(}K#L8F;
z8)9>8htb#@2jU1EkJHdKhk?bo5;x#h+=GYlPdtZL@eV%5SNIWsptFdsDVHtSGhmC0
zNiY>=#Bj`mg|QTt$7)y?8)GZ%h~2d=o2?&#AvhW*;S8LQ%Ww^D!X3CD|G-mt5pUpq
zrE34r2)xBFXcqN+nfx&(CcxyF7PDXu%#X#eELOsrqHg~U2sFdC*adsx0343va4OEm
zMYsaj;}+bFhl<kvj}thHSMWAI!k72~zoSnvPfZ13988QUF#~49+{Ij;84D38iRG{=
z*1<;D5<6fw?2ChO6i&qHI1iV)7+8%PaXaqABX|-o;B~x*Pw@?YMx(grgZg0%bj4>N
z8K%L^m>u(BQ7nTMu?E)1rq~8MV^4H>blHXx7>iSI7B0l)xDMU83lHKkJcF0<7Cyum
zTG{{a34B9G2~Sl8Vr)!=p_m@SFc%iY68H;N!P*$5RPDb7f%e!H``{oPi4)Mmxwr&Z
z;cvJN_u}t(Le%a5Jb`O?7oXs3{DiiWo*MGS5R8XOF*Rnw2+WH`O49yI6R3dIu^u+T
z*4PPqV1FEnV{kIg#0B^(t}RLX-%Ma99>Ak`8ZY5Ze1OmK9ezc7DNjuWU@T0CDO?Ps
z!>pJS3t(}K#L8F;8)9>8htb#@2jU2Hjb~sQ&cVgF5;x#h+=GYlPdtZL@eV%5SNPGR
z%l3nSv$UtGf-x>8!Bm(L!!ZvQ#!^@wt6^PijIFe?|2q=sj{R^5j>bti1Lxy1T!Wi%
z2kyr|@DyHDs`h__z<qp%Z}AJNzYnkT0~iw%U~){0Suh9Y$6{Dk)a}0#ftuI=n_*k*
zg1vA64##mg6=&ljT!HIxOBve#ZUTq!IG)8TcpD$#OZ<S}(Wk7Zrh+gICdQPQp)Bn`
z8-d(d2uor)tcrE85w^q**bV#QU>t=Lak`6vdAJl;<3`+$`|t>!#0z*G@8MH?gP+le
z^wf~ckAWB%ACqAk%#7JF9~Q+jSP^SreQb(tu(L;(ttSB&4#TlH1!v(xT#oC|jl1w5
z9>X(u8E<K2|34(~0^j2|bo}C}sz8j5i7*t?V;JVbf>;87!757C{%aG6!WP&byJ8<4
zgd=eRS~wS%;41tLx8Yt<xBuS>oWS#V4e#O;e2t&bR?bsHz8He>Fe#?SOc+s)_MewP
z5iE@rusYVmCfFJ~VGrz&LvajF#+kUF9PR&C0&8(I?!*Il6i?$NyonF+IljZMXfN-n
zsQ`@SVjv-=z;u`ub7BE3j*(ayYhgodj_oiSd!uV010!%ePQy947+2y3+=_efF#d_>
z@G9QH#~xj_R|G!d4|G=WR8=s>#Uz*tGh#UA!NOPy%VRaHtCjuVm_RG+h~2Rt4#Ckl
z31{GZT!w3K6YjwM_=i%p|5F4m;tjly&+sjNL9?Q#hWs%mCcxyF7PDXu%rENpUyMLm
ztb{eO0XD<7*adsx0343va4OEmMYy6O?SDOiEw~#G;c+~RSMWAI!k72~zoSnjPfZ13
z986q^_MehK2F!-Ju@IKTa#$7XU?Xga9k3hr#lbkr#lS?Ij`MISuEveH9rxi8Jc$?Z
zI^M&l_y%2{889k)s>lyxV0=u5X)rTp$9z~6%V0&Uf%UPeN0+S)fzH?yT{sNK;uM^P
z3voHFLpScigLn+jXl4IjCU6TM;tPC_-_TLTQ&WK$8xvtDrpGYMg$1#MQnmkI2vot^
z7=<mcJ$A)DI0#4L1hjB2F2Pm!o2c9WHUfL`cRYdT@fzO6C-@pap{=T?hI}yu<6%-v
zU6uBqi9iJA#UfZ5D`0i3hfT0GcETRmABW-?oLrUmKa;=${1w;YX55Jf@F<?fOL!9>
z;B$P3U(xQW=BcUxjD-m?1*XHSm=g<Nag4;uSPL6sb8LsMXa;)YKpcVNaT?CS#kdkT
z;8xs&hw)E5hgUtiY<CDe##i_ef1tCvr>252E+)ZLm=VJ<4;IE!SY9jpzZ!wM*ce-3
zN9>OMa0rgZNjL-N<1$=>n{bCxwg3GD{=ids5pUpqe1>oF3z{`NHRO*mF##sWw3tQI
z?LP;B{8$XjVkNAJ4X_!u#V*(j2jFlVhf{HO4ch-A0xNJmZo%Dn2#@1gyn?s!5x&F^
z_#J&}dTJ`DChb2Cfy9^+GhjB%jfJozmcy!82OD8a?10^{uZw}fI0`4?bexAvaW!tl
z?YIw*;7PoI*YO^@o-*(TKci90Q$>Cl1LI>dOoN#*JLbcpSOzO%4UaBceF9Cf4R*$!
z=)z$*7N_7WT!_nY9lCKB9@NVIKStmTUdCJa5MSVX{DzL&o|+28*q8`IF+GN1E~RS!
z1qqbEU$6?+#wcuo?XfHN!9h3@C!mFMafztg|0)8%;WpfhzvBr!kJs=nKEc=c32k*e
zHROvS7_ScPKPiFKm<b~=FBZYlSOKeJJ#2!lu@m;d{y4M_?SBk`$v6`i;IFtAH{(t`
zfJgB(Uc#IB0H5PK7Xx3>Ue{Aq0T>GtVhT)$SurOTz~UH*m9Z8!L|1bL+F>;I#(_8j
z$Ky1dgNtz`ZosX$2M^<)9$mI`1g_#8e2lN~BmO{VJx@&qV_ZyvsW2mkV;(H5mHl6e
zKzXc&b+IwF!j9M-`{58AjgxQ&&c|iAMycBWCIUNfKmLKI@FL#8`}hps;ukdQduqrZ
zV`2hKF6#E5mOvKFf%&l*mc>d~6B}SNY>Qp67Y@MTIIceJe=335xCmF^dfbA$@em%z
zvv>t><0E{DAMks9+P_Z&PgMnB988QUF#~49+*k-pVmYjeb+8e(#11Y7x?x`&jH7TO
zPRDt;6j$R$+>ZP32%f|X=(^6pJ$#C9@G}|>JvHQqF)%(R!!(!~vtvFiie)^yY!wOA
z!1~w}+hAwxi7p(5V{r=3!iBgT*P&Z0`+paKgLn+j;AOmp5Ag-Q$8YF}^3+ry#>PY#
zis_ZA{f80Ag$1z${(@DoHb!9!Y>!>B4-UeSH~}qDxBs~Wmf$M<4Y%Q5{2fo=dAx>q
z@d>`hPiSl8sUhD+wEqwS@h~Z-#!MK2d9etV#tK*+>tPdYjh(PZBbR4O`V$z6V{kIg
z#0B^(uEou`6A$1~JdKy|CO&X6@EqUaSF|_wY+wM!!i1Ot(_vQ3i3PAYMq*`j)ncF_
zHpg}tjlFRoj==Fa4d>wE|3}kZMq62~Q2;%FbO-`UcM3=f7B&_pCbo2Uhnr66?(XjH
z?(UTCZV>L?`<wUId{|?MxZblkV;~$jg|oScD+5C@8wA_Ak4Jf$mw1y8_>A$&1x+Po
zDyC;P=4GL%;rA~gc$=m8Iltx4{EJmsn~m6#?bwyQIfx@8M)p5JFrD+blxw(|yLgZ%
zc#c<jhmRS%e9%xrCJ!6k|4V{Q%*p&L$~X8PKjByWfxoc=tFs=PvQ>He?<nZbejLg%
zoXlBV$Q4}AZQRQvJjIK=QQrRV3!XA=g`lb=Ov!Z2$~-K{;w;GzS(;^7mVbsEm061o
z*@A7^g}peCBRHPZIG0PfnwuEf={UgSJj*M*%}0z?F=!|OpXZCr$Q;baB78kC6!Wg&
zV}8l+`76t_8tbwNL+rqA?8_k>%}G(i?>|$pfXlg#Te*ja`7bZ<I`8p6K36GdDluPR
z+K7?;XA$J)D}0r2@dJLwZ}=1cU?tXM12$(Hb`Bfee^0>x4(B*d<s2^NDsJQs?&mR{
z;bq?9!%FraQ#q(8K9eyuGcY?}W?{a@clZ&%;CK9m<yf_{{nrsR=HG13f7pkEIf@fG
zgY&tJYq^EHc_`#K$@9F%yL`epRf47xF$L2wGjp*3i}6jq&(NoiulXZ?XGPXveKuoj
zc480q=P-`t6wVF|#Viu6<OXi%J|5+1UgAwY;4{Xn8Z?!ZshFPGqK4l;ub>c1@NJgj
z=lqsG^DkCmZ8l;{wqsZJju_ehAi+pZ;B?O8Qm)}<?&3k7;5lC99X@94YWANnd_;a@
zVRF92Ow7srEXp_d9zWq%{DHr*0;{uLHT!QWXvL1~&VC%qF`Ud<T*wt%&u!exBRo~j
z{x1q{@IIe1ZuOv{BuvS4%*s40$l@%?4_TUJLXNWhla*PE4cUTi*@eA0kRv#r(>Rw)
z7+USv#GO3A<2=hNyv;|9RU>F90iWlK%*Y(f7Z{2uB6ywe@?(C<@A)gsvl{EN2}A6_
zZtTk;QN!;)S}=(-xq!>Lj$65hhxsor@H+4DKR#D8Xex2U$o^jtq-7T7<|}-aZ}9_u
z#&7r&|6nE7WCJ!28~yy>M$nl(Ie^1Cj#D{@i@Ay$xr6(8jAwYcrv2X%JY-C*prZIp
z#?;Kf?0lJp`5NEhNBn}{@t0cmUrtb!b=a7HvpxS|9}eayPUH;E=Q6J4mXKpN5Ah_=
z^BV8+3FFibno7hJOvB8~#R4qG(3_6;`6<8VkNlk#S%dZ2jIG&;J=mYaI5sd8Get0)
zi@1^-xSjiWl&5)#H~E0i7_UyyR8ppj8h-!uf^5voLM*|zS&E<YTmH<yScSFOh%MPJ
zVr2ha1-&_lBRPT7Igd-ZhMT#I2YG_$c$Ig;M)&_%5W8+rQ9>r?OU%Ta%+I2HgYWSZ
ze#Ia78!Obc|LTHzY|2*b$nNaNp&Y}>oW+G)!S&q6y>;#Xh~N}2@&@noDdW})no7cy
zOvkLu!-6c%lKe2_D9th~%RgC}wb+m?*p^+`ivu}=<2j9?xsD}V%}w0N13b>Nyu#aj
z#8~x%h7$03zQ~M$p_m+kd@RD(`7S@^m;9c;vOKG?E}JmK4(t{+{Qi9fLpYj~IFk#w
zoa?xidw7`t@&d2(9{-CN+5dA5f~pep1*T;d=H@GWm2dF_e#US36aQc()(jine*-~t
zwqa-X<NyxmI8NmpF6Jt3<PPrVu?F^kMsS(8_>eITgNEWW8B;R@v-4#Z=4*V1AMuNZ
z_WzyW7nWmH)?s7*&G!6<eK?q-IFU0rpUXmywcNtpJj9bc&uhHPCydi5Xetp?Fby*^
z7efUc#rP)Q=coLdKk|20WDVA5Gqz?Y_F(_OP|PsFSWe+=F5*gV;CAlgQJ&@{-sA&5
zW4y+Zro!)^G<w9uq+)tzV_p_w3BJuz{G8wNXa2=1tj$IdBl~YDXvePX%|RT=37pP(
zT*@`v%w0Ul6Fe6-y8o+!JABO8O@a@mgiOwtn29-=pGElw-{U9zia#{5|K9`^Se^CQ
zl&#p2-Pw;rIfj!tiwn7e>zmmBHo;yV;VE9^4c_Nd#%&rjm4qpoj#-(91z9}gD9I05
znq^p)f3h-bu_0TqExWK62XX{M;~mpDmrJ;so4At)c${Z>g}3>Lv6=-9CE)Xcp_ms1
z8JUCmScI?hU4G0j`8|JSc~)axHeo1g`29Nwy0I^Za5N`zCKqry*KsTN@G$@71zwLB
z+5bJke|)ZaP*q~Sz_iT5+<b+v@-2SA&-e|0;vZq7`>!OZ$p&oBHtfuv9Khim$Elpd
z#azXW+|k_r_Y02k3@`H*A2Oyz&`^9PV`^q#cD~HQe2wq4u>X$)U+_Er!g8$2I&93p
z*`EKf4+nD;Cvrx}F`vu0mRq=+hj^0bd5w4ZgmGF1O(kLqreP?vBNq#>7~kak{FGnw
zNB+)=tik$h#@6f<7>em3=+9vs%PE}AMO?`Z+|GSG%G12Wn|u&8{Ql1b@%|2~O3GAB
z&uq-gLM*|zS&E<YTmH<ySS4a)|Fs2;*pltomAyHLBRPT7Igd-ZhMT#I2g649e?oAM
zS9ynz8QWSCGCBYMx9Dc_?f?I+I{*Lb`v3nbyZ`@cd;kBcJK;ZlABz5uhyVXEy#N1p
z{NH>>6<D41*p#i<k=@ykLpg?%Ig1NJjul+bZQRQvJjIK=!TWs5xUGVZr6f$rbj->;
zAxA+LXGwm@(k#QW{F9Ygiw)U=ZP|sr7#ipp!SS5Nxm?24+{B$cz~em2E4<A|jMX~Y
zP$(uraKt>%7nzYcn2$yHI^X5T{F2}ESC(fr){Po|uO@;JJFpx3atKFr5@&J&mvbGr
zat{yl--wa@Ul3g9J^sh%+5{g=iTMK4G7EF_6~4;1_yIrTH({gu|4Hx%E3qaUusPeX
zGkbCXhjSdKat;@BRU7-?DA>XMJjOG;%v*fOn6^Pf@tKUNnSt5)G7Go0*VhE^@FRY~
z@AwPLu`27ZG5=<J{=+^T%uyl7M9$!RF5_Bm;cgz{NuK95-sKa<X%{q=h@ljYG|bFg
zEWl!Xlkf9We$5~GJ1epV>$6#4D5kZb6ML{fhjA>Ya5filB{y(8_wguC^HS9C``;8i
z;4{W+A5@i;shFPGn3siEf^V}FKj*jnIbvl0e+jCvHXE@e+p#Nqa}Y;z0;h8xmvRj^
zhmG!km*5~z@Eou54j(gihoGT^OwN~>i8+~{MfpYt`+raH3BTeG{EZb@o%Pt1t=N&>
z*^fgxhLbzk|17~muHbrZ<6a)&DPH6a-se-s?HDwbgejRW<jBfAEXd+4$q!kYWmuMf
zvNCJ2AzQF5LtPxbIFKVap3^v&OSqbwxRVEXoM(B3w*x~lj|8zg1r;UW^L&vRnS=RQ
zgs<~me#|fVJ%45SsNwgoCaB9M46y^du`h>kG$(N;7jQY(aVz&kjO_og;9p+gb>8ED
ze6DlQRARosw9LZXe1)&_Eq)L-y8q7v-|#2?!Ah*j25inY?984Vz~LOnshrc<{uc{Y
zaU*wdKacSYFY^{3GNwz=P<$q1YGz>eF82SjpfF$KJN$@W@H_s(a;(ZaY|Ovep8v2<
z$T66sIFU0rpUb$GTezEtc#`LNjd%Hkp*UTGsuD2;(=ao0u>gzlO}@`h`89v!@2tog
zfuWfCf@W;ZPVB+{9LBMn!r5HJmE6GX+{dF)!|#7uaEUkhfX^83pP;FvOvUuf#=I=V
z5`3Gb_<6+0{=XIc%)eNLwb_U**^XV=n}ax#6F8moxHN2Z|7!%Bxr+yRg6DXZclemG
zy9Es;WOBa5Ow7sr-R!@p;0?aVPxuvo;BTzJ>a546Y{ic3&VC%)&Hl#-CUX`Sas}6O
z8~5@EPw^se@IIe1Zug+6Bq2virejv-VL=vWNq)%EEW@(=la*PE4H;_TXv;3_#ep2b
z@tnrFT*B4d#GO3A<2)M}in$`V%}0#YBd90=pXZCr$Q;baB7B|i@?(C<@1us_|5rhI
zR%2Z@VTc{rjeR+UqdAE)xq!>LE@EW=TLpV~nE&zuuk#-N<8wWOrV{f7rezl9<|}+P
zY;^x`2|nOw{DwdA4_0DLHehqMVQ2Q_01oH4p7uXgFo%n|iW|9u`+1CKc$v5OkTJc2
zhT=0BQ}?p}41(-@nT7cp-{D96g5U8MmSa`cVPpQy_94eV?8Ctv#fhB3`CP`e+``>F
z#FISFYYg3WJYk&PK~;&Ef@zqUxmbY3_$J@yr~H~f^7p_{OhrKr)@L)eW+(Pwe-7hV
zPT_1W;!1Ad_Nd|a-zPZA)4ar+e86Xn*C%KyDN`{$voS9Vu>{|a7}<X*!RP#zKl3kE
zVQn^IOSWTI_U0gt<OEI+8{Pjr!BVc_X71uap5QrN<sCj|?7l%m37MQPF;idr&nd{y
zqI`qz@e_W<ANU(9usZ9pDO<54yZ5#KeuAMK!^xb*g<Qe)+{V2;!c)A+8@$h_AxGSP
zK~+hZlIfV0d03FeS&|>JG|R9o|72x`YB?IR1>3R<dvPE~a6G4RE|+jMH*qHq1cqXc
z3(oQiZ}Smj^$!|Kz~}iQGcpJBu?S!1yZkt6`2D{We9vE5p4C{FO&DSac4J=-;b>0c
zOfHBR+5d9EI&S429_GKi!0Wun|M=X1psB=sfoYkAxx+^H|BB#MzQqst8NcCA{DYNP
zlMUFMZP=MTIbeYO4;PH%RL<dIuHr`S;C>$C8D8csK4i?mprQB!?LV0yH8U_fUuI#x
z#&`G;zu<TLh2>b4b=WxM_?zwd5BqR1M{y!&a6XrDEw^wt5Ah^J=N;F0mrodHP*7DO
zreGRoW-b<BF}}(7`6<5+48{B?_?;D5gZ0^rt=Wk^*q_5VmQy&Ji?}js`29BswsRkk
z@-#2;CLiz_;|&g)O3GAB&uq-gLJ=eTFCloFrT96&<<I<!Ral#i*pltomAyHLBg01b
zKS3~^^SG32xS6|nkSBPKS9ynz8GA_3P(mgjV*f7*GBGFfvnb!-d;El7@dy6K3ark0
zY|2(c?7yR+JNt1c$8a)daUoZ5J-2Z$kMI;P@<zyUpHCTgXi!xWrer#1WgZq}ahBwV
zEX^`3%g~>W%B;nPY{9nd!d@K65ggBHoXaI#%}s%!n4N+HJkGPc!rOerSi^#b67YGx
z$c)Uvd@RD(qlVxAUBSovlHc=JmS;8AWfO+jf!)}bLpYj~B1ZN<Q?P)`xsF@8hllwu
zFYr3=@jpH{JZLI0Utrp>(fwx;<mM}Um2dF_e#US36aQc()?@=VXB&1NZvQ<612~-H
zIF)m_n5(#vJGh_6c!rmGiw}p}f6R!WqWDb4)Xc!_e3^y$8sFhZ{DR-{7nWnykfRP8
z^KZ82KkUQ79L0&8!TDUqwcNtp3>|Wu<au7>T|Qx)kwH_5n1X4TnYmbi#rP)Q4-Cb8
zD)^c|@^@Bb4c2Efwq_^xV1EwdSWe;WsG*pcMS_*w!0p_}qdd(^yvYZA#(1NGrjjxh
z(=%Jd$o}&R3b6#=W+{HoZ}~I-VineABerBac4hCd(ftn+jN}AP=R7Xu8gAw;9^?t0
z<5k|_W5ynB{|QG2RVC+3%*33`&!T*T@9`6U#UJ<^E3i82jSjzm<SQRE6|`bUc4t2h
z<rq%pEH2~<uID!H<q@6=IWF=B@AE0+jtPFCNtlx9n3Z{0ki}V&AF?z<WgKPsCo8iS
z8?pu4vI~20AV+XKr*STq1cqW(3pQ~l5AZn8@(OSB5o3)F8cM+D`64qi2lGV@zkd<I
z>wK3V^GkluUs;~jSeH#0Vh46(Uk-^F+5c$4B+ldlF6TOK<sKg9zr4WfyvP6e+_<2r
z#9^cRe?gFzS(uxz@KwIW5BM3s;ZOX7l~|Jv*nFJ*w-Iz^PY&R4j^k9$;bN}hM(*H#
z9^)Ba9%uiz1P>WAKBy=@lQA_jFgssnVZO$9_z}P0cl;&fD95U-!^ZrZ?fDP;a4<)4
zB4=<umvJpaTO7N2h$nfT*Last7-vGzR3fHe8fIoL7GSZ!P|TZx_xUNm=8ycH6<LGz
z*^I5(i9Oh#!#Fl-`2D8{W^)l&as#(>ACK}hFYzWH@EPMx44O*HR1qWlPcO*Eyez~L
ze4C~CIltx4{EJmsn~m6#?ZQU)-&N3?gE*2CIGyvjlxw(|yLgZ%c#c<jXQKT-7Q~(u
zRFsg(`4TfRC-bu?-{5=vgkSLo{>BQE?7zC89-FciJF+|baVW=dGG}oiS8zSIac{_R
zgr|6sH+Y{<8FzBfR1&6SI%Z`a7G!ajWavXjX_jGG{>jR$#fEIbw(P=Q9LNzI&uM|7
zn7M)_T+L0~$pbvjv%JFFe8gB&f`$_CdA`VuQN!<_Ly(U}_&VR^$NZAt^H-K<HP&Sl
zhS-7KB1ZP#S1^R5If*m5fXlg#Te*ja`7bZ<I`8qnu+jZLH#Mj#F<)R>W?^o=!dLkg
zKj3HlhClHSR$|Sm_TNCzoNd^dJvo5GIgV2~hl{z28@Yq~d2FivpAlT<Ek0z-w4kB*
zOvcpA!0ddPh4~ua;Ya);<oJ%iupFzh4jc1tw&y?W!@(TIiJZat3@vl4<rePdA)e%U
zUgKRpVVvnfQ;C>@X_%S00z)wc1jYC!-{+_Nnm_V)R%8v<XEU~DC-z|fsNwe?CK$^p
zoXtgC$qn4jeLTw3yu_P)z-Np%!~T;-j_}U|shFPGn3siEf^V}FKj*jnnSZegYqL?<
z=>A&@+OaEpa}Y;z0;h8xmvRj^a~BWt1kcT||Eq#Ke9YK0gJu#kIbUKX=45^r<r{pD
zpYSXGFw_2j6I5Vz)?-t)Vn=poKMv&>PUb8w<O;42Iks^xkMI;P@&@noDdWxxno7cy
zOvkLu!-5PIca-FZEX^`3%RgC}wb+m?*p^+`ivu|#FcdRhFpYD$gsZuUJ9&V|d6rjr
zn~xZ4cF<4)J|8vw{x1qLG6(aq2w&&B{Fq<zd;ZGutj4-*!cfG>=l>3ZZtTk;9L-6b
z$pu`_b==B5Jj{Q2f!D)E_kU0DAD^2ORF#-7FfFq%H(%kae2X9OGk(LL_{SXkuOz6+
z25inY?984Vz~LOnshq>bT*ZytF~|P*3y$#&FY^{3GG=bjP<$q1YGz<|zRbdWjqijU
zAMp!*$6r{ERau9P`8V71ANJv3j^adyW;o_^8P{?Pck>WW@;tBcE}t;Yyr8K>Ou;mP
zp_t5qTr9w1e3S3<Q+~}K`8zAJ2J5pKTeDNt@cZ`=^ye^+<rL25BCg~HZs$H8<!N5x
zO+JVi+5a;^y!k;@Ntuf2nT>f_h$Z+oOYw7l%b)odtAvg2zqX(eTe2OyvNs2DBqwk>
z=W!|5a5H!D;C%Z(AvnjYyu-(gy&z~PA(QhZW@1j}XHmYv_xQ;I`~OPt1Ak)$R%bmn
zWh-`MclP5@j^Sj^;=+()1=n*M_woo&@gi^VKA$q~!l0=nOv!Z2%1|ChK^A98e#p`+
z!?OI7m061o*@A7^g}nkpF#`o7IG)oumrJ;so4At)c${Z>g}3>Lu@*%d3cr7X=n)h1
zJYQr+=3qV+;p=>tAM;Co&tF-d)mS%TWdBVBA$DLl_T><c<|NMK0xst|Zsi^x=D%U1
z`@bN#&U^fi&n*r<m=f~^rezl9<|}-aZ}9_u#%~te|4)KHScx^+fX&&4o!OHEIGp1+
zm2<e5s}|e;M!^p5=P{n)W!~aL#w-aMiqB+B%?!-WmsvREc#ZGyBYwf}_zTOiD(kQ@
z|7Lss!#*6$&?v`5&ft75<63UvZXV)Ep64~*<rBtP8Z?zCFcgzQkcOF=iv?JWZ}NS9
z%CGq&e`iJ3V0|`=8h-!Qf==wg{v5`!oWj{$#FgB@?cB$sJk3iHBm2K8c)(|jw=AeC
zDN`{$voS9Vu>{{{DSpmx`E%Il{{IqGVQn^IOSWTI_U0gt<OELVJTB!LZeC{py95V$
zg6DXZclemGmj?|cWOBa5Ow7srEXp^Q+y8rlPxuvo;BTzJ>a546Y{ic3&VC%qF`OK7
z%;G|>;CgQ3ULN5oUgQnl=TpXA5j2&ADH%%V$jUq{$l@%?4_TUJSeAdXGHbCRTd-|l
zD5i^`7YA|#$8#FzatT*+6L<0ekMk_A@OIQtOw1!etd&7U3HUr;WJcy-J{IBYe3u{d
zOMcH^Sw3Q9|J4L_*@Pi>U^n*V5RT>~&g23v=Q?iXp0LsV9~S(}3%t&I{EyGA3YtpH
z7nqh=n47QgRlda!R@wh&f^YZ}|6nE7WCJ#58+K+-4&ZQ(<5bRB6@LH7FTE}ntl~!Q
z;C>$C8D8csK4i@5;QNiwWK7Kr%pP*Q%))$)@9-mj!SDDB%dsl!urdE;d;Y^vAID&h
z;zZ8id@kc!ZsBeo;z^$8HQwcuz)(z_H9=L0n1X4TnYmbi#rP)Q=coLdKk|20WR0ld
z_pdK##@6h_9_-Iy9Lp)3%|%?v4cyLsJQ^{w|I>m?yvYZA#&~Okrjjxh(=!|MvJgw~
zZI<HaVWa#1R`4_bVineABerBac4co4;z&;5bk5__wf4V8u$jAfkSBPKS9ynz8GBvO
zP(mi>OU%Ta%)ie5iwfT0d;El7@dy6K3ark0Y|2*b$nNaNp&`c@PUb8w<O;6mHtyvS
zp5jH`;C()2-1R|Ip(Ku!OvkLu!-6c%lKhaRS%zi#Co8iS8wQ4AS_s;*3wv=OM{qo+
zaW0o|H8*i55AZn8Mh(CJ6~S#jVyq28MG5#kUt~t+U_KV%>wK3V^GkjoF|z+(1?5?d
zb=ia=c3?O5<q(eMB+ldlF6X+i(fw}~?BQYl%L}~Dd;E{jZ48=9%omuJS(uxz@YRj>
z|CZnbe#US36aQc()?@=VXB&2APY&R4j@xMeQw4Lln5(#vJGh_6c!rmGiw_yIDQGA@
zlQDJ3k%8IyG7IxHzQd3B1;67jEXS&>!^ZrZq4th{*oT8TiW515^SO*`xrMuVh$nfT
z*8)Q^cLh%vXLC?hBBo#(W@auHU@^YQ_xUNm=8yb6YWV#t3Tm)Eo3S-Ju?PEe7{_u7
zXLAu(as#(VjO>4(;3!Y?5^wSWpE2H+psA!x#q`X^yez~Ld^>D(|D^<<^IQJRzgUH}
z*@!LKj$PTCgE*2CIDL!#&l4==8gAw;9^?t0<5k|_W5(VZG?b9Z`4Tg2wf~%g{4B~h
z_#QvuSNws$u>z~J9-FciJF<Jo(T_tphLbsq3%P>pxs7{ygr|6sH+Y|+r;fPWf~t}*
zCDSo0^ROU`vm`%cX_jGG{>jRLp_p2NhHSyM?806g$PpaRX`IU?T+L0~$pcZt?|)oy
zmRES2j~Huv&`<(C&lj1IIhc<{_&VR^#}Om@|5EThe`R@AV_i03h#lCCeK~}qIf*m5
zAZ&F1%LVJWm3w%Y|MCK_^B(`>b31~j67vP7Wftb%VgIiPUgcZ-fS>Uj{=`36i8a}P
z&Dn;X*^>iy*#B_BI8NmpF6Jt3<PPrVF`nUN-r_^X><k);A95sPYGz<|zRbdWjqmUy
ze!=hf3(K)8>oC;V@i*J^ANJv3j^ael;CwFQT5jQP9^%QsP|SJ3HQwbD#@Q8Am53>r
zhMAd*1z3!4@_l~FucL<F|3|^^tjHRy&t`1RPVB+{9LBMn!r5HJl@TNR-yqn|eLTw3
zyu_P)z-NrNJ7_8?Q!zcWF)s^+jqbmM;BA)T=lqsG^DkCmZ8l;{wqsZJ<{*yTZT}Ml
z(>aezxrUp$iwAjv=XjNO_?WTx1Pvu*@;&zdk{}avGCzy*4Zg=u_!WQPZ>+%TtjDHo
z6>@ZBclP5@j^Sj^;zF+AdT!%h9^oloWax(DKA$q~-k_=^Ov!Z2$~-K{;w;GzS(;^7
zHZT<Pr=T)xu_0TqExWK62XX|*a~kJz30HGd)bRW76dd4jp5+zZ<|D@17c`WB&+|oQ
zWDe$I5xyQVvj2AlAM;Co&tF-d)mWEJ7-9!@V_y#8Xif?n-TzF%0xst|Zsi^x=D)na
z>%7PR_}u=Wsl<GNY4_WI7C~;l!dLkgKj3HlhClHSR$@&yU~{%%=l%BIQ!s$TIgV2~
zhl{z28@Yq~d5mXxnYZ{b<cK*CR1}}dn3@@woiDR6U*kLch+ptK{=#w$Rdv*1WB$$d
z{D*xwn4>t6GdQ2ixRzVEJ1`V;NN|$pd5w4ZgmDfAO(kLqreS90VgVN8n|wcN`29Z>
ze9a&EJ1epV>$4eKvlDx;KZkKFr*L+}$o>}zR&oQkb03fLG%xWcAMhFD9SWLC%2Z6x
zY+<AO&nqaz5`3Gb_&LAj&-{y3SeuR5lI_@)y${*{Ai+pZ;B?O8Qm)}<?&3k7;5lC9
z9X@94!}g!>a8OlpzQjz-$^0zJH~1bu;aB{Dzp(<VvtG#2l&#p2-Pw;rIfj!tiwn7e
z>$#14d4!=;j*Gm(`+Ul{M}mfuFeTG5EAy}*i?bv@Wa+?AOc_C0{>jR$#fEIbw(P=Q
z9LNzI&uN^?B~iogzgn<~J9&V|d6rjrn~xalXwXmsKF=4KkvW(zVr2hC1h4a5e#|fV
zJ%43+R%2Z@VTc{rjeR*JY;^yl1(P_F3%H!?xRrZ&nE&zuuk#-N<8#M?rV<~s{}%*l
znT5Ie3SZ@0{D7bF8~(&UScx^+fX$EDe;Yw(_T&H#=QvK~94_W6ZsZQ`=P{n)<&fhR
zA2Q~6P*Hp)V`^q#cD~HQe2wq$BYwf}82ZIgj#XKQjrlj*^B?x%V2<KM&ft75<J!Pb
z%of3J9^y%!=QZBt6UI3aG?j=cn1-2|iv?ILYA7b=O~L#8lwb2l{?3Z5!TM~**6hR{
z?9X8w8!@u~DT3Kt#FgB@?cB$sJk3kI$p?JKcqfCVk}_4;=>F3SvN10Uu>{{{DSpmx
z`7{4w71m}Wwq(1L_TN>|n}ax#6F8moxRh(SnY(z9CwPumdFNy(sN}IA_P@cm6EZnp
zVkYKfeir2$e2<^-EB?UWSRv%7&U$RhR_w^`?8l)T!^xb*g<Qe)+{Vye#}S_5Mc&|j
zK4sifK~qVXlIfV0d03FeSu!vb^P!+L%djl}WM$T3L$+XBc403L<Oq)Ew5Z|tpDS3x
z)!f9LJiy~T%PYLiM~rnkXea@n=Znl3F|z+0f_yB(*ZD3#=9m1Qzp^~5u`Zi1#18Bh
zHoE`5f*~BuNu0?AT+Vge$~`>He|dq|d5`~{w*TkO1XU&G3rx!_%*|K$D&OJ<{EXl5
zC;q`ota--%8wi@S4Lh?Z2XHvYaVqC<F;{UTcW^(Cg&b#inYZ|mF=vB@;xidjGXt~p
zWftaZe1{(~^o8R){=#ys$~tV!zuBJuunz}w6en^9=Ld#jmI>B!3wQGnPx3sk@h+b*
z&bgqeL`=an%*<R-!|z`}P>gT#eSXTX`6GX4Mb=<_He+jcVh{F@7}@_Y!B|e=Y%bzT
zZs2zA<58aGCEnx%K4ZM|_MbF-M85z5(=!|MvJgw~ZI<Ha{FXoSFIHh~Hac(rEd}k^
zmAyHLBRPT7Igd-ZhMT#I2YG_$&fEW0!5uzk><d9N37MQPF%xq#Ka27WzQ<4a6@Lgh
zeq#kzXFWD$D|Tde_Tx~F;bhL@LatzFy<;2q@(54yB5&|MpEB;nps6HG$#l%hJS-R(
ziYYEA$q!kYWmuMfvNCJ2AzQF5yRa7razxbd`;Qk)<6JJ`YHs3A9^i4F<rUuMBgVQE
zG?akPM~v+MML|a9U_KV%>wK3V^GkluUs;~jSeH#03LE|W-$BrgeK~}qIf*m5fXlg#
zTe*ja`7bZ<`X&3nC-{%gT@I>B%omuJS(uxz@KwIW5BM3s;ZOYIvi(;Q)MNuTXB&2A
zPY&R4j^k9$;bN}hM(zkX_VXCe@G@`lA!Dut4aH|Nre+3a=gTb2*BE-o@e#k^cl?Fr
zSe13yn18c9|6v~v<|s}K48_b4%;z$$<rePdA)e%UUgKRpVVtW$Q;C>@X`+VTKeHeg
z3$Pg9<oo=TU-L))&WfzT`fSG5>=ZGw{~m(=9LBMn!r5HJmE6GX+{dFl%}cz=2VtZ8
ze<p}`EvPCfQ!zcWF)s_T1m9*Ue$H?CGyh_hYxZAT(1<PBj$PTCgE*2CIGyvjlxw(|
zyLj-L{htt=<5k|_W5&K7G?b9Z`4TfRC-bu?-{5=vB;@#tKkzqJV0G4GQ?_D9c4t2h
z<rq%pEQS_3R&YJHaW9YX6fg1y@AE0+-UymX!jw$Mtbw7JJc5EO&XW9)rCEk$`6ny0
z78|k!+p-ILMGe3IK*0!(=QPgc60YVZ?&JX;=UHCiZ9ZbGoA#d|a)f^#c%CmZBXckx
zi|}>6%a8dbzvr(k&uXk2HoE^Nf)G2f8~btyM{^Qqasiif9k+515A)xf_J2Weo%i@3
zpSu+_l$b9tEweB;U*W5Kiy!baesjzIe-iw`O03BSY|b|9%$^*;;T*@QoWsRj6>@Ck
z4({hMp5bNQ;zP#V4jPKjWK7Kr%+8k?D(rZT@9-mj!SDDB%dsl!urdE;d;Y^d92^*m
z86}v=8Jy2$T+1!o%|krN^Ss8pe8M<)f~FEh4ZnX1K^kUeE*4-hzRCCbDZl2A{GAn9
zgZ0@gV&wCGYe6UWV1EwdSWe+=F5*gV;CAlgQJ&_du+jbB6g=QF#=9F-m6WNNp4pg}
zg;;`bvlKt)xBU68{r@GX!rE-amTbqa?9D+O$qAg!d0fgh+<e#mcL@&i1kdp*@9;5W
z-wPT_$mD#9nV6ILS(I;t9PjZHe#Ia78!NCn>#-?Yu_L>)ABS=bLz5k|xR5Kjp4+&W
zM|g@Cd4u=)lyUC|O(kK<z)(y&L00BrK^A98e#p`+!?OI7m061o*@A7OhTp%7pce;n
z1jln4=W+>Ga}#&+0FU!5ukd!n$o?M*Vm$~dO2Fs&A~P}v^RWnD=ezuvU-EnY%JN~O
z`>!Ub%O(u51G}*=hj26}aV8gVIoEM3_dKxw!-9W#f!BGD|M9tpK~stO0@E@JbMqCx
z%D4EzL;L?s@C|?BAFRZhY{2Gh!_Mr<0UXY8oXR;N$6~JHM(*H#9^)Ba<}E&C%%h;8
z_)Nys%)n4~$IC3t*Z2-U;urjmzpxyuvJM;bZ?@+@fuWc_g25cciJZatT*kHB!reT?
zlRVFByvrw1!|xyGaZptvreGRoW-b<BF}}(7`6<8VkNlk#StDX(|MdmU*qWW#gZ(*-
zV>yMhxri&df!n!{N5e+<e_C*fH~E0i81G5YR8pp5dS+u@7Gep$%~JgQiT!^o_?dsP
z3Tv|wTe2OyvNs2DBqwk>=W*#1`(Gp2%w0Ul6FkSOyu-(g{a?^fLMG=+%*33`A957s
z8+?zS@GJhn-&ldwS&vQGiXGXV{TLeR7{ke&#f4nK_1wn2Ji=4F$Q!)Rr;PhF+Egee
zNpQrZWIASL9u{PAmgI*l%`z;@KUtZz*f47N{aXmyvI~20AV+XKr*STqa5Xn^ClByA
z&qj>w|BB!?A2HUm;DadvpXZCr$Q;baB7B|i@?(C<@54s-|Er)ptFbPdFvJe*#=acF
z(VWDYT)^dA_sssc3ij|Y|K$Z<=RN+%=VD?-e+4BmUtn5hVQ#*{S7SoKKlqm51AfMD
z_!IwNCDvpEHfI}lW={^_aE=Q(rg9D!a}_so2lw+B&+syD@gZYk1^=P(nT(;-jttDs
zmsyyv@g07|FZdmQVL4W19X96QfuWf8f`8bDgE@*5IfL`LjBB}tyLpHwd7jszhGJsw
z3Z5`d?4YVdOu;nF%v>zMVtkYD^HYA!ANhO4$o?w|YOp?=u{Arf2m5mv$8rj1a}if^
z1Gk5b?th=)C{ObeZ}I`3F<zXYsiaKB^vuS*EW{FgJ5H=nbho7hpYvP(%)eNLwb_U*
z*^XV=n}ax#6F5DN{m&CD<r;40E*|6wp5s;C;bX>rE@&trlk+8J3ORBzKa27WzQ<4a
z6@TDwtibB5$EIw>jtq5o^y5&D;bhL@LayL?ZsT4a;VE9^4c-q7#XJ?njT=;zgejSh
zS(%3gS)3*LAxpCi%kocFjvC&7EkQ%JU|V)!FAn4gj^{Ma<r1#uChp{ch>`st7o6o4
z-sU65iWfALfY0+qW@HZLV-dd2clmMH=>ESHe9vE5p4C{FO&DSac4J=-;b>0cOfHCL
z|H}pIxRrZ&nE&zuuk#-N<8$$YrV{f7rezl9j&J|32wvq|{D7bF8~(&UScx^+fX&&4
zo!OHELXP1a$Elpd#azXW+`;`k#xuOkTYSiv1VKZg_>N>u%?!-Wmsyyv@g07|FZdmQ
zVL4W1oxo5`W5M5S&wtp5gE@*5IfL`LjBB}tyLpHwqlWi?UT}?f`Gj#222~|u3Z`LZ
z=3)UB<C}b+pYrR7k^TQD_?;D5gZ0^rt=Wk^*q_5VmQy&Ji?}jubpIO!+qsWNd777a
zlMnce@e&11C1on6XEx?#p+xpyLhv?A@pFF5pZOQ7ur?d9CEKwpdvg#+CbIttg6W*c
zrCh_!+{J@D!E?OIJABO8iGzj`GI_}H5;HL;^Rp=5;CuXpU-1Y2#tN*?dTh#2D@R9m
zXFm?*7*6IaF60WX=Qi%;5uW13z);K$!F@hu+$2F&Ntlx9n3Z{0ki}V&AF?#dux!-u
z{{IwIW-T^k3$|q!_ToT};CN2sTrS~iZi*P$|4zXH9_LwJ;cY%*tfWCh3HUr;WJcy-
zJ{IBYVWazhSMV{v<oEoQ<ynn&*@Pi>U^n*V5RT@gr1n2kuz<_Cj$65hhxsor@H+4D
zKR%Z%Xeu#ZVA^E%pGA<HukcmA#Si!yzu`~(gOym54cMG**g53r$pIYBah%FIT+CJ6
z$Q|6zV?4vlyv5K%N6hm<Me&)8shNS<`7#UhHNL}-_yxb?FDw@rim587!^ZrZ?fDP;
za4<)4B4=<umvJq(aCg-3{tpRG@;tBcE}t+?@}Q|iOu;nF%v>zMVtkYDM~v+MQ^D8#
zk-xJdYp_0>u{Arf2m5mv$8rj1hmG!kkzge^a69+$C{ObeZ}I`3F<y$GsiaKB^vssR
z{__e7u>{{{DSpmx`7{4w71m}Wwq!eYW$zUBKS(f=6F8moxRh(SnY(z9CwPumd54b~
zJM=<OQ9>r?OU%Ta%+I2HgYWSZe#Ia78!NCnL-ia@*@_+6o&7kJV>p?!xR5Kjp4+&W
zM*>4Jrvw*ygZKHAaZ?6OC1FaYV^-#2K^A98e#p{M!}~8ID9b-tnYGxEE!dV_*oy->
zg5x=jbGam9WdExLo4At)c${Z>g}3>Lu~G#MCE)XXkr|nT`NBr`UqtXa-{r^rlHc=J
zmS;8AWfO+jf!)}bLsHrQXu%}T<N_||I&S429_GKi!0Wun|M*<$psB>E?f(TqT4rHx
zzQR}e7C+!;{DwdA4_0DLHemDcufIos1+)!2vnK~|ILC1+=WsDsaU*wdKacSYLzf-5
z_>eI#20yU)OvcpA!0ddPh4~ua;Ya*}-vx$Zei4*oRn}o+{>}FMhkZDhqd1W>IG@Y7
zHfnhPTLim#h$nfT*Last80V#+sYFb{G|bFgEWlzBBl~|-@IF7~*Zh&cvm$G-KAW*M
zJFy4*a~Q{ljqZPnU^W+VB{y(8_wguC^Ad0J0iQ8mnxLtqOqIs|(+jdOFAK2*-)1R(
z&TsiM|6&!^W+S#_yEOLSRnVJ*IFb`Mo%6VqYq*)ac#tP}j#qgn<ao^3X@iOqGC5yj
zCgx;*7Udg!kDu@>{=nZDs^F;3dTh#8?8xry$Dtg<$(+T7T*39+78r`zD>%YayvQ58
z&!>!=E@&zVQ!*X1G7k%~I7>zi@Bc$VX_jGG{>jR$#fEIbw(P=Q9LNzI&uI}O`=2XV
z!qwcwojkzfJj*M*%}0!tK4>TbpXZCr7&f~99D;l-!q@pOKjxSGp1-m@tFbPdFvJe*
zmfrsR3WjhrCvheha5>j;EBEj)|K$Z<=RN+H-u|D<5LA_zFEA~$FgIV}t9*+e@H2kH
zpZEtWv1Z88fX&&4o!OHEIGp1+m2<e5tGJOnxSye8jx)T>TYSivj6p;3nT)BKf!X;o
z3-dL;!;b<(F<%J2<1Z}7s;tAt{G09h5BqR1M{y!&aDLSA{+9{Xatn9!5Kr<vukkLQ
zFixhRsYFb{G|bFg5hMFAASlK+`9448*Zh&cvm$G-KAW*MJFy4*hmG!km|!fYa5fil
zB{y(8_wguC^Ad0J0iQ8mX8TW?IjAfZ(=!|MvJgw~ZI<Ha{FXoSFIHh~Hp(0d{>3c?
z?bwyQIfx@UfzvsUOSy)dxr+yRg6BextGvU<jGZO;0VZT}zQjz-$^0zJH~1bu;a3d(
z;P{OdSe^CQl&#p2-Pw;rIfj!tiwn6TFch<1u#J0pgr|6sH+Y{<88>UtR1&6SI%Z`a
z7K|F+e{n%ce#p`+!?OI7m061o*@A7^g}peCBO*rjKVC46bGd}8xrsY@fX8{3S9qI`
z7%N-QPy#+5HoE^81sR!x`B;Rn^Id+-FZn%xWqDR(T{dAToBekXbYou*;b>0cOfKMZ
zuH#nj;bH#E3%s5!6jX9g@E@Pc9^{Gn0@E@JbMqCx%D4CdKjSz2iGPF~l~|Jv*qm+H
znLRmx!#R#qIfsk6iW?c);n>e(Jj2Vp#fOZ^5i}H^$(WiMn4K@PFkcG{#k?c<h+ptK
z{=#ys$~tV!zuBJuunz}w6emUv?|+71K9_MVw{SNP@g&dl8t?K6<KzsQO2iaQ6EU*?
z%z|7jz+!xp@AFfB%^&$YE3yXbvl&~nQ`qSKdkFe-7{_u7XLAu(as#(>ACK}hFYzWH
z<h1{1f_S-ts**Al(=!|MvJgw~ZI<Ha{FXoSFILHA|Fs2;*pltomAyHLBRPT7Igd-Z
zhMT#I2Sbh%JjbiN!^e!BJ7_2&lk+8JVov5~QNF?V82ZHV6@TDwtibB5$EIw>j_l5U
z9Lh1A%vph<n1zBBT+eOX%OgC+i@d@6e9E|af~Jx%CDSo$)bRfE2nw<|OY%dOW*L^{
zpRCMUY{(XD%P#B{F|z-Gf)O0gX`IU?T+L0~$pbvjv%JFFe8gCJ?LR^Ih<*VAzQ~Ns
z!F(*j*ZD3#=9m1Qzp^~5v2I@bZz2e>1G}*=hj26}aV8gVIoEM3_wX?P&1?S`1lM_w
z|M9t(gN73G1*T;d=H@GWm2dF_e#UP?j-U7kE3qaUusPeXGkbCXhjSdKat;?Ww92uO
zJGh_6c!rmGiw_x-FK8$}lQA_jFgsrk48;@{yvBF<5x?Mf{DtLMm37#df3rRRVIK~T
z8s7gX!9>pBd@kc!ZsBeo;z^$8HQwbD#>pQvl_+9l|0x7%n3=g)fW`PG-{+_Nnm_V)
zR%8v<XS1-;&;P9jo!Eo@IgDdDg|oScE4hK&xsOMAnwRq1|4qRIK4ZKBK~+hais_k+
zd0B`h_%=)NbAHR83)uf(f-0=dMr_G;?8@F8#F3o9>72)<T*J*F$1Wb^37+Fs-r-}$
zekEuqA(QhZW@1j}XHkaUaJ<J)_!WQPZ>+%TtjDHo#g6RGejLg%fuWemf>~V16<p74
z+{+_8#f!Yb`+Ul{1%sxNFlE&6{?iGvG7k%~I7{+FmS!22<)5s~T5QM`Y#TAM|1N@F
z9LNzI&uN^?C0xx-+{ptx&a=G2+hL>oe<X-iD5xj_pXZCr$Q;baB7B|i@?(C<@A)gs
z7qb6qg1T(N5Ie9N`*H|Ja}sBA0he<fw{lM*`#&uBmlt@Q_xK;5D;zYHm@hCbvoJSb
z;j4U$AA}sA@f-fcKUj%1*?`U2hMn1y12~-HIF+F}j>TNXjoiWgJjOG;%v*fOm?A+#
z@tKUNnISL~lU?vK3-dL;!;km{zvC|~$EvKu#{8S@`A^jF{`&|9a}+0X2Iq4b*K!MY
z^AJz+Jg@OCpG1u8KTgr0szgk|G|bFgEWl!Xlkf9We$5~GJ1eqA*y#T23!1StJFy4*
za~Q{R3TJZ>S8@Zlb03cuwg1zCOT5Vke8zaif~Jx(71J{t^Rf_2@NJgj=f&**Tfxu#
zi&a>gjo6ay*p<CGh$A_H(>aezLyk4v%w0Ul6FkSOyu-(g{c6xqLMG=+%*31w<#!b2
z8+?zS@GJhn-&ldwS&vQGiXGXV{Q^TVLj_|vnX|Z%E4ZH9xR*zGiWhl<_xY4@i$|IY
z?>|ZOh>1zbbj->;EXd+4$q!kYWmuMfvNCJ2VZ_M(TL{{+3wv=OM{qo+aW0o|H8*i5
z5AZn8hK=t3is1JDin|kdo2vZ*;Kvjat|3Hahzyy>%8+@A5Hb@{GAoq^P9#x^O5NsC
zG-}j5QZ#BFG*F2~N}7x6zxLkW)4O?H4expX{rQ~xUFUc9T4$ZL_ivwd_8BgJVxDHn
z&QyrSS%&+tDi2^o9>mt{#KYLPnfxCta1_UIGN&@l**upEc{#7;O}vBm@lmd7CjVCp
zyvnz^o}X|FzvIu$e_%3FMOc!1u@bAZE}NtkTCg3vvKRYv7?0+7PT{GX$+=v>Y+l9m
z5{0E)#s|5APxD2-!FAloP5g>KGIdZgLIqhYF`e2|U~lfnT5P}rc?dhQJNs}DNAOrq
z;z^ty8}k25fqA@;mvIqq<n6qdk8mZQ<12iN@AG4R5gFzGw*uRl@8D#pc4rBeV@2-I
zI&945Y|Ad}$$lIfjPrk#z&IYyQ#gZjIG-2uN-pLtyo(QTIiKPS2h0E01=ex{KjT*Z
zz+bsr^JJuovNS8O3Tv`Ho3T}M`QJgH8+&sghjTP1@<dMKES|#)cqy;p4ZJO_a1S5m
z6MU90^G&|TkN7#i;Wp-Nk&IAbX0a^O`zlmpZ8qY;Y{Sm%!6P_?BRQ7G@noLPvl7#(
z^8_y96}*l&^G@E+$M__l=WBe2AMjIt$?s!B{{JFSpk*>td$1JCvodS29-Fcy+w)K!
z&H+4<$3#Z?KSAIGp2jnHHqYlJyqeeZR^H8r_&A^8OI#C-^Z#9e54o9N^C#wMm5fj!
z7H1jm!>T-h4S5h-vr{Yif0#gD4(3rD!^xb=G-vZ%F68CBmN)SZ-q%Y0KPs?_tNAM5
z=6Zg@E&Pr@GyfsUNEKm8?!`*1o>r*KCTziW?8;v3&tW{8<2i+=awg|;0n^zES8)lK
zav2}w3O>yj`3Bc<BRBCY{>W78c!biaf=MA&jC*o#?#Ehezyo;*JF+|ba1clESWb!!
z`G1nYbe_q1ypWf15pU$}yqAw~C7<Ife2ec#M*07-z!&_M+nKLTvNP?@5-i7x+@E#W
zn9bRiUDz`i=YKzep&Z3=Jf5d;2Ip`-FXok8%v*RDAK>yf^8YD;7x+5Yasxl(R{p?W
zxm(+0q>8dME3gV{vVPliQlXhZD|TQv_U1qi=V(skiJZn+Jck$XQeKl*xPiCv9zM(`
z_$*)Mn|zNS@pFE|ZOq#)dBBC4&Qd7LeOZmQ*@y?T4Lh?3kKhoF<X9fZlM~aa(*@4r
zdAx{M@H*biJ9$4J<CA=zukjszz)xdC{(mX(J%3?=_Q_D~!BQ;G%B;b9Y|55w&qH}Q
z2Si5sf26=MoWK)!8qeU_JfD~FYF^J<c{d;8<9sF<=l@FrYxpid<Ys=&pO~jZGD3w|
zoMpHVtMULg<Ut+ee`|qGJdAxgm`8C8Cvz&(oXvB&keBmX-qb<<-yv`xALS~p=Bs?0
z>-h<{@H_s@{2h~#D#DW7E3Ht8)mfKK*n;iYmA%-X!+12ua|%!8Os3~5EMPXT;u0?9
zGCs%^e3~!v4X)!xZsJ#o>C}$`sZPld6=X5)$-TKBYq0?j<RR?H?(D-s91$Dx|5$-Z
zJc-kJCg<@&UdBbdk+<_+KEjoJj;};U`Tv%{`}~++@LO(YzRt-=?amS`$BNvab=a8A
z*)|yGe;0wC?8l)T#c@2Ir*H=6a6T{Qm0ZkQcvoln|A4@9KE)UKI@fXoKjT*Zz+bsr
zmt>@hvNS8ON*DQGQ=mSZu@yV88+&sghjTP1@<dMKES|#)(h8UI8s5O$cn=@u6MU90
z^G&|TkN7#i;Wno8c1?z;Ftb>e`?4Bqvk?zw8+K+79>F0T$+3y))NukQ^K_oY^LP=j
z;B~y2ck+Hd#wYnaU*kKmA^$%R_>^Drd;Y=#hbAMn2TQR$E3*dcu_;@!Jr9kH^8avw
z0X&k&Z~{-@X*`2x^L$>yt9d<d<=uQJ80Y`v0?+UzuHn1<kem56e`20)$p{r<ahBme
ztjYtr$^V7|2eCCf@i6w~U>?OWoXn|Ab2iWALSEiY{$DF_6Yt=Ce3YxWny>P0uIDG*
z!teMq^LI~1sz_R)B==$^R%cx{VGFinSN39m4&%`r&nZlwsxXstxq#Wcic7eZ%lIHy
z@M*rtH@J=)6Vs_p0$=e*rVdMns341RPwvhASc?sKAP-?jc4wd1kpF`OM(|ip;z^v&
zGdYhJ@-i;sjl7-r@)53#jPn0Efmiqz-{;5tg5PpG^YutZYIl}kIacKUti#5^IRBdq
zv}G6eWIqn&D30UtJcTnjhx2(cujJw$^8XfryZ8W?^C`Z-*SVG(_!+nI2mZ?4dL|=P
zl%;#h{|W+CSd;bHjIG##-PoH0Ih><8ktcE*XQdU+;RU>u*YF13#(VfMpWw56nQ!tv
ze#Fn2{zhRN^Y%)Hs4%lwmiw|AYqJp#W*c^94<5lGiRsixfw4S}C-Zck#q)R(ui$mO
znRoJjKE@~cd~C@7*96|-2mF*@@_YWm0*5CfwFgVFJS(#X>#-?YMn?JHUf@t3&H+4<
z$8Z8q;AuRAXY+hs!mD{bZw<!zf49Ixe4NklC9dJS{E(aZHGg8B-pL3RVsVz?KE36C
zRe=N8kO#3fJMl2~<zODgF`Ue)OmjBR?JfTo3S7=>c@yv8eSDOwxSFr>ZLa4h+`{kp
zbEZf6`y@kEgeAEbE3rE3vI$$T9lNp@`*RqNW_rBB6rReNoXZ8w=2cw6rCi1bxq?sg
zMZS@kPOTHz$W8o;KQh%f8KHtK#yz<=_hT(K;DJ1Z9b-fOcNgfxK^(zjIf*B6I?v=h
zUdYS1h&S?f-WwU^|04n``5a&2TYR4%^9z2<?aX&XGE%#<1k14^_YcPTUq_%Zo3kyu
zuqXR*C`WM|kLM|z!8x4Ii;s~1R|+iVExd~la5<mi3w)hxxq+W?D}Ugx+^wJdFWN5|
zveK-;Dy+%+Y{pjXz;5i#fgH}!oX8W?3ez}?=kNkv%4>K7Z{t0Dm{0IozRWlI9@8Hw
ze9mvUjd}YgBU6}JEX#dajkVc`2eS=3vqxe&b%ekWj^tP#$CG(F&*FK!h*$7B-po6B
zKOc(?`TwNA^L&l(@B@CzFZn%xVSxe3NbSK=EYHfU!FrKV{x=n9$@V;yhjRdr<T0GU
z6L=cW;MqK%m+<Ofod4Gg+{(N85Fh6=e2HuLE<faEe$AhlXJ9fyg;;!`{4XQ053BM3
zHsnEU%}zXweL0v%aSSJOD$@hy|7?MCxsaFhTHeGvcpo3-Dz4_Me4Fd}3AdybzT?l#
zKPVZhA}q<hSc%nHmrdA$?bwyQ*q`ZP3P*E1r|?wH<XkRbHm~9mF6A;l$Q67#F`ar*
z;0><hMsDI){E?}_$p{r>G49E|xgTq>0S}A~`G1H&M|Ni)4&n$N%Sk+m(|IQ6@j_n4
zMZ7UG%KzI1?&Tv~$>;bA-{SlHm|yT)ZfCwB$w=+a5-b;t^S`3N{;b2sY|ggq!k+BM
zp&Z3=Jf5d;2ImZs|MLYd=9OH`TX+{A;Br327x+5Yasxl(R{k(V{{Jel+t6gFin25-
zunKFkKAW)>JFpvjb0CLvbXs8|PvkW2mP-ByTv3*01y*5A)@L)eVh46(Z>9$-4CiPT
zU=fyJS?<HI|Hj`P&vc-k>rL34ZP<z36Vs_oPX@SQ7)Nm|C-Wpu;~AXG`Mijia}jUg
zt+65hmkB(;$GD2m@nx>zI&R>n+`{lLqT`VX|2#7`PoBhrEE*Z*e<^{zSdrCu02{Cw
zTQYoJA-;p~K1FOeKM@<|C9%VJG{<vFFwXx|1!i(C7ciSwaS4}l86V^dKFt^T2G?<8
zIR3;v+$8W7e`G3e@(2pD829Af+>f=`fCusrc4T+<$s4wR^vef>1V->!PU1<N&NDfW
z7xFSL;*GqW_wo_0Oe;LcSNIm+=g0hl-*P+i<x3vO?kvG_tjPUYhv~)&&DoY+*pvM@
zl%qI~$MY1<;2h59#k?{xomwn#3-96sT+XNX0$=A^Zs2F!${+YEcgvrQRMFV5{Ywi}
zU=`M6eKun&c3?O5=0FbTXinsboE917|15!XcmXfvHN1hh@g6?RC-^L1=9_$vAMx{G
zod4elY-8SV@Q<>hFtb>e`?4Bqvk?zw8+K+79>F06<o`&4u{@3^^K_oY^LP=j;B~y2
zck+Hd#wYoF0r~%$z&reapYlt7&tF&|JU>SxwFgVFJS(#X>#-?YrWM-rP#(?!Jd($7
z0#D#+JcDQRd|tw<c|Fs&D%{P7_&A^8OI*Wu`5`y+YyQMM1(Ojf#NsTIm`?2@P?ZO;
zArE3}cH&{|%fUQ~V>p>pnda=+u>H>!SjfwHEpOr-ypNA^6<70BzRmUggj@JsWR(9u
z3*;}93{?@9<X)`A>a5EqY{7Qy%3kcxVLUn*=l^(tDLj=kIhPBV&8xVCOSy~>as{8}
zi+rPy{9h-qk(>Axe`Km~GC~DejC*o#?#Ehezyo;*I~JDz-39t^5J&J>PU1<N&NDfW
z7xFSL;*GqW_ofvd;YvQoSNIm+=g0hl-*P+i?VgO(?kvG_tjP5K3U%0+&DoY+*pvM@
zl%qI~$MY1<;2h3ROs6guxRQ%`3-96sT+XNX0$=A^Zs2F!${+Y^Y}o$0g_k(dF}x^C
zvjVHIChM~qTd@PXu{Q^DI7f40WR(9W3QXfHp2G`xDX-xTyp8wpVLriU`7+<+d%-yW
zKN9$y-*6lA?vad8VP>%`_hmKKW+NWVHtftEd&vJI1cq=V$MQIy%+q-m&*MeBg4gk8
z-pTv<*dFr#NrC728sFgu{FGnvd;Y=#;dOdEA7Ck#XJyu4y|hA8wq$!A%ELK;NAeg>
z;0Zj9XYg#E&r6uTTH$)$%DedxALlcCiEH>SKjdb9&7YX3STaI|64R;T0%f=ltMULg
z<UwrBPCSf#IhaRr3@3AHY}o#3f!REl3wb%O<xRYU_wiA#;%dIix4E95L`M0)Mc_OB
z%>2cZp(?_X+>4c1opsrSE!d7-*^B*yasCezIGW=*g{N{R=W+qFc@>v%DVOm<uHe(f
z<^PKUZ*UzqaudJek4$AHBUF&ZxF`4Keyqg?JTOcCA0p6^-PwnOID*G=5>MiEp2>N<
zke6{0Z%ixP&U^U?SMoW&!ngQ7Kjs(wmfM*xoWF|>OuMrL)8!N@a(~ugV>V}7c41HU
z<4}&`I3CYaI3qEgnj<iu7xPLk<}JL74{$l3;tPD8Yq^1+acgYY{yzx(%H2vPLsgWe
zS%Fnpll9q*t=NIx*qZ}6JTl7v(E<~BBByZ{&*25Ul-KYE-o|_QFrVPFd^s5B|C<8u
z@gsiDZ@7(lOC=*zm{}~#eOZmQ*@y?TO)2@`S)d1x;1G`FSRTidc{<PHdAx{M@H*bi
zJ4?y``vo53lYE}9@g07^Px&Rk=PxV}&ezBD0hVHUR!%F_U_CZvOSb2sJe&h~B#+?)
zp1{+12G3^te1%JRHLvHbyqgd4aX!PBxQ6fYLvH5R{3$V=%Cl!OM1@$KWw;Nk@&GpE
zL2S)VJdAxgm`8C;Y}o#j1*S61**upEc{#7;O}vBm@lmegYQD<1BcuFZFYpPs@H_s@
z{AH4nD#DW7i<MZNb=ib1*p6L;asKxb=+9w1n&UZzr*bCeasjh>6_;=+m+`?e@_&WE
z(|nO{a2+>t6Tjk*Ooex+qI4_BV%(E^b3fK9EB_k^9LPi1k=@ycgE)f6auQGCbe_q1
zypWfr6&CSE-p+gZ2v_nszQVWoK0oFc{Fd99uUs-x>D?7dupBFLf7W4RHfLLQVNdqs
zP>$j_9-o*_ogy%Ub2y(D^GYt}Exd~la5<mi3w)hxxgj=e|IY-r@(2FP-S$d`swhjd
z0;{kl>$4eKu>-rYcVv|R0|kb2G$-;zPU9?|!wYyRui*{6jrZ_jJ`s%b|5<^T`6l1v
zNBo@Ma2xZMPe!OPvsjk<vKni%QF-})us|DjW)B|0AsorEJdP*xbe_fYcoDDQb>-#%
z%>sAwem=%0`8;3aJN$s3@=JctUsxc#Zy(PGSSqbho|RdH_1Kgx*`9~;a1P*+Jcbi^
z0#9T54283KJ}=?byq>r6Za&1v`3zs;8otX9xj8YN`dZ*8=Gi+LqCzarGTet%c>o*o
zAhu>F9>%^L92>U(Q37K)nNykOY@W-7yqwqaCf>pO_$XI#b!3$PuL``)_56fe_#J;{
z{_q)$XlE+IlH7}xSe<p*ge`(`{<jn8%3kcxVLY1SIfbWkCg*Yivw0PlaOpnsf0@98
zT*0ULBH!RTZsaC@#UGj4HyNRVEXF;#_rCIfKY?0ozyo;*JF+|ba1clESWe<eoX#^j
zFRgGPFXJNK$lG}@AK^+q$5;3k-{;5tg5NT|T_In^WT<v$36^6;?$0`G%;s#%F6_yE
z9LiCN>C`xZ<9P~aa1Q75VqVF`yoGo10WRlLe1WgWrc<f40vq@lxAF)6%H1j@BUO~8
zS%Fnpll9q*t=J(l%KvTxy*ZG>IhqrBBByZ{&*25Ul-KYE-o|@^asEFn@C2Xb%Y2jX
z@gsiDZ@7(lD<>mVm{}~#eOaxt{I4z0hzGL`JF^Fm;1G`FSRTidc{<PHdAz7{I_c>Z
z0@v|o-pTv<7@y?xe2wq$1AfXc`8|JOfpnFm1ADL(%d;|TupXPTCEN2*9?k(glE-iY
z(<dmL#xr;}&*vq)n%DDI-pz;jIG^E5T*G%0)2R;yHuG!##5^HGqG!26EY33AhgEq1
z8}cBwW+xsN8@7L6fx$eAV>p>p8KrF0q1il_3wb%O<xRYU_wmulsIgT7tNAM5=6Zg@
zE&Pr@Gk?{jV?|h!d$AI$vu-fX|0V)0*p6M<i~Tu_M{_)<@Kny^TrOZXuc|8lmk2E7
zGCs%^e3~!v4X)!xZsJ$`k*R9Q2o+?pYVv<ifxWpOYq0?j<RR?H?(D-s9KmBbi6?P-
zTH#F2<AuD8i+Ce%=e>M{EBPE>;ahy4A2a=h!nfSceETOuwL43&94m5v)?s5dXIpk*
zPxebpr-llQ;y519Q#gZjIG-2uN-pLtyo(QTIiHFR+y4cD*SVG(_!+nI2mZ?4swX2=
zl%-jLRalet*(@^3|5gGW*p0n8ki$8e6L})1aTd?v1-z8k@P=TV|F;R;!-x3<pXJMZ
zlkf2(e$H>Wjd^P%BUG4KEL%hV?<-J^wb_UVvkg152an(oj^tP#$CG(F&#EE+&l9+a
zSMWOC%sY8MALEmJp0Dv8e!x%pCBIKA{K5h?lcCy!rC6SoS%dZ1lr7nwhw^X^;E_xp
zqcDLd@HC#mvw1!*;nlpJxAJa2#K-vzUrJ1;)(E`I54o9N^C#x1m5fj!7H1jm!>T-h
z4S5h-$A<0SN#HQ{<zODgF`Ue)OmjBR<w9Q0Yk3pzh>Y_8K7mKMimUl5-{yLL!Y%xc
zKQsRU$w(DpN$$l;!8re`3)E#3wqQGUWiR&UFdohEoWfH%lXJP?0QsLSa21zuDVOm<
zuHe&rk#BGvH*yod;*U(#mj4B7Cqq??dvb5?$69Q_19=ELvOD{55J&J>PD(4B#OXYf
z^LQaI<09V3+j%b^;YvQoSNImw?<;)FFZeCDGhdx#gmz~MmSaWk&pK?(=4{I@iRn~N
zfqopyQ5?tPc?xH64(Ib?UdhG0g?I6R*s%SV3p~Xa_&V2e13%+d{=i?kTis-&in25-
zunKENM)_Y~pcz}S1G}*|2XZ(^b0SaVG|u8VynvSm<NUuy;0E5td-yP);In+0Z}L5U
z#LxK+w=r+MWP}RWlmA%)Ww|e_u{Im=V76gr_TUj5!jT-y<9KpC`G2~=Sv-#y@d{qY
zn|UYi=VN@5&+|3D!w>jrTH#B6&tF)eelk>huoTO)GHb9No3bU_^H3hn^Z<n;c?>7;
z1fIq-cs9@HCA^x~^H$!?hxmA6I`xdeOI*Wu`5`y+YyQMM4U!Qm#NsT&eOQ$TuwiW2
z{s#%PW+xuTz8uV>IEIrsm1)lAxm?K0d2M8r|2GNT!Tb0qS8+98<=b4(Pq>BO@n`05
zn2b~rmJG)Ezn4HIR%cx{VGFinSN39m4&%`r&nY~WGaJhPxdIEA&8xVCOSy~>as{8}
zi+qFYxRIOqRYUpzqd=-rGDHPgjC*o#?#Ehezyo;*JF+|ba1ckN6^`X3p2X=qlk<2X
zFXJNK$lG}@AK^+q$Mh=-Z}EM8%rE#Yw=-YkWTbXy36^6;?$0`G%;t&dR9k^A?8$x{
z%26E0<9P~aa1Q75VqVF`yd^el|GNYp;Br327x+5Yasxl(R{p?Wxm%NDq>8dMD?~>5
zUqzrM>$4eKu>-rYHwSV!M{^=i<TTFWIl(ypFA%tt*YF13#(VfMpWw56nQ!tve#FoD
z4YxIs|9P7xLsXbqEX#dajkVc`2eS=3vj>mh5RT;7rt<$dfs<Jvm2{{GOE7#SBtG|B
zk>M0jd_7G4V#6knZO*pr!k+BMq2d1H3ZpoV$MY1<;2h59#k`V>c?<9216<Chn0`Uw
zb*|+Ge#Wi*fxmLMJjnxyzs(+Y=F+ZLU=`M6efko6I@L-b{8D;665$t8W5X|`#fBe5
zi5<?-oXFfZRrsJ&Tra#892@!;8%`s{h6z?MjDOe}<G^3tW|=$OL%mWAAMuFWsmyRj
zC&wLypZRgUCEG_v`G2Uu;T*stc?>7;1fIq-cs9@HCA^x~^H$y+jPw5?fyem_U*a0R
z%MZDkU-Ktse(9i)O;ns^xDTslzW<;3g@cA}IEdjNpu|HMe)v2#{NQP9_@T4d@B=5Y
zM{x`%b1KuE&2zah{QgMXz~uth@+RKF`}inVaW!A%+g#62xP{;GXXej*|G!Ayq$4G{
z7b~$k>#_-3upPUy7yEM<kLGx$rzo7tnVic7%;r^G!lhis2f2bz^F_YFb&2WJMuAQI
zia#=yFBzGFEXF;#H}_*LHsFCggdN#EHf;Ys0)se$$8r)+;&h(LdAyL9aS?Ci?Yx(d
zL`M0)Qs6nh!ngQ7Kjs(wmfM*xe=<_LvjoerBKK#VV4VMr1)8%hyRawwaVSS|9FONI
zoWVJq&x?6we$W4l1#aP8e1OaO6kp)$T+0poj9d8wf8}oB7#_WaTQu|i|Iz{#ScNrN
zpUv2c9oUV%IgrCSniF{<r==BU@f=>jOL+}%;BCBz5Az8=%a{2k-{VJ2f3ENiw=wT-
z$q*H07Rz#9R%2~8;=ydg&g{V>64R+60wXz=$MIyI&a-$PFX9!vjyLm8-p|MQWNgU)
z=LKHlJN$s3@=JctUs#}EGE#f66w9+RYp@=hMn?JHQlLE#<>4H_BY6xb@C2U5Gk7-7
z=Ow(F*9YVLzg6IFKE%iQ3}50JzRM4}nP2lK<|&knP$3p)naub9_YtVd1K5xUu{AsK
zF!tqO9>p=7%&AOsb|KII=L#(3<-C?R@eba{N4bit`6}P$dVaz!{4Udzp9S(4PKK%o
zOL8w(Vs+MK6SiPGc4aU2=P;&^RtRYy9};(b#q-yu(YefS!_NIDliPIa7<arYX1CEX
ze&>_hu>E)8>^2_Jolb6}{NHu6+hmjOY;qgt|1O)|n!@d5a-01A*RGn~{`urq{_mpM
z?VnF>)A^EZv}<O!e?GZQ@6y?A*t!2?a+^-=%Gqs{|2v=DhV8!#XSZ?w?{sn-<^Qgm
z-6s3i&L+2U{_nEct-0h*Cbvoc@2c7DpHFV(|1O%{{`urK^ZQ@BW_J7MliTzzo!y3=
z`%fmf>C~>A-A4Jp^T}=4{=0B?8|VK{C$~}l@4DG-lK(rK+{XF8%VxJGwL6*ICi%as
zX1AHi?Rb;iDLj=kGr#{eS6~6Nc@>v%DVOm<uHe&rk#BGvH*yod%KZM<j{^VcG<?UC
z*=@|OJFz=^Go3lvJWOB|$8s`H;xwMYxy-yFagpnna}jUgZM-KjoqAZ{2|ml0`6l1v
zNBo@Ma2xYFwOW{2%#7^sPuqw5|3~NTL)!kyE1SRe!Y0c9e{$ab&tKX6wHG#V{{MsX
z_B(xL6Hbi8w-;q;R$vv@4Cf!>6~jk4Vw<rQJFpuwd+k8ihjTP1@<e8K)>*Ef!wYz6
zxc~T$uMx=XBt={=!N2+{`0u9QfN=kD2Zr%KO~1eUeqegJJAR7)<M#v8sU6-B{I9(q
z`1?H1EzQIDCvOD)<1-k4EzfgH^C<tXHuTps=lgU2tvrv~`J*(C^M5Dr&&50EPS0S3
zhW~>T7)k!;{{CE&9XmUN5k0bhegY$G|EPgn-=F*QGZ=CGe|!QX^Zs9M@6Y9S2IFrW
zV&e|xc7#p;*&%ip9}&~3!|e5aIhaRr3^Nmvsji1D7eBJuJeLcZnSfmD`c1rp_r-=*
z9u-){)qIt2b3H%d7JkQ{ncsw?2um{a^Zu1wuO1oYe_eqlY{CEJcm1QC`c&=A<XkRb
zb}-KWUGTg9@uu12j&}01{z?A--QV@k?391)7{9Yay!`*K%;mz6|Lv(<W-oro&ht2*
z;jaD&Mml^3Bi>fK@E9MrpUWXWom!{^yY3jjvqO9s|NOi97_a?5Jj6%&pW8A1fAJBF
zIRF12KZ23u|Nq}dFy#NAoTdK9C#f?Bs$5@BWb!}k2638%mqf9dN$KByL81OIj^bGU
z+p}n<1OM66=s$iIO{e}VPorV@GDH3Mo)f~u|HIGag$Dm8&k0ff|9{N;qxnHJ?T_>S
z4?dUozj{tc^8epImzQM0u76Gl+dmqLfBRhCpFAi0-RXB`=lr+hKqme6k)NS2|I_0@
z`p?emEzqHCUd1I`%4K|zEBG{D<QrU<7(V|eu!&#sN2bgV3bGjYWUfQ2{=Tfn+H4dX
z#{Xb}HtftEJc2_wl9@y5aju`tzqM~f`JdZsvkn^U#{cx}S7xMg9wFoWFYgX2vj#Iy
zLc8z?ndJZ9o;K^?e?DuL|37K)Z+vq3zjK7lOpE{iCzt;_N67R){^atX93lVW2ba^S
zfBMPgzdCEq?DhY4=#4jd*#7@thu-+e8|D8rJKq_c%lW*BnKK%TT+h6vk~v?PIRro8
z_Q$x2&oT4P%9?OJ&VR?^)CMbj$}Rks+nC9c%pp1R-H%cZ$>mv@H5h+FvT!)zQ84Vh
z#lt^7DHxsqFPTc+8wK`ErM`$PmrB(v6s!=wOcLE;*HkKmQh7tg_(&P9H;%4{2Ku<Y
ze`IK9lIv3<LwoaFkDtUsBX_udcVuWkRX6+H-dXjsd-lmHojtBk*5vHMeY4)JIWqJ&
zI`f}dqPvR@niq!4q2UrfMI2v7W|uf3tL#BhI66lE7T%$HbX%r+_nhlx56@JOPJ-oD
zJ$k;$RPT{<z3e+P)qCa)?{M$Yw?s14d*xg&J5N8IKRjo6hw2M+RF9s3e(Pm+uT1qm
zIm0_tUz($O-<<1ZFUnMpo?m}!b%*LJb5!q_bG_`Xnd;HD&#n5}9MuQpTray#e~*1&
z&hQTR{!NbRgL1ByeSW5Tbha|Ld*358ml^qJ^6=Yw+3Pdahvp3LaPQHXnN0OzIoHc>
zFhJ*z%o*OHdUO^sQ+;^O^|EJVs*lJS-l2M*9MzA?xnB0mnd&2RhIgnwE=ToIIoHds
zJW%J4&KcgJ`m7w)kIA`S_T)_U(K*9ARKFre^<#6cm%SoWeN4{q4%P3@Q9YXF{cFRO
z7^L&#a)x)P9(^e&GxFneu9rPLQ+-0t@D9~C=BPd~=X%+9hUx{Pqs^r3=LcnFXRjTc
zRXR_z>^4KPs;4`JaHyDyW}nfrJzR;7TbU(#4AIgqT*8qw)jC|FWn}pOJFSCJv$ew|
zS}z=ZQ&CptY_EQJzJEBxGE1ht=-3h3OaIp3;?Q6;fs7ig8!nj!j}PUX4Q>t%M%ys6
zWEzYfa?TE}4(&z9|ERtC;gV@Dnlt{Zy?o)xAp88GS!L6+Lp*2wjXCN!%u)Z^-_=j0
zqOa+!4zbLV=}+{6Cue)xbF>!?aHc=^gmUOl`nN4GCET)mrnO*ryz%mU_#1URvrG@`
zEecO&nI&`EGa-=kj!S11OLY#LCK`xl;gY%Iw?a8nC%XSs#nP$N$(ei0apR^O<xosr
zQYMw^92G2?Mm`SLbKddba>Y^yhFEmR(Tk<b9sd%_nL44EdOx(+DBS;VOXkLCcAc}q
zg`vS{Q$`K82$xKQ(K{uXIw71YRW|%OTaG}c7`+6{+1|>~Ui3}9sJ(QnKWflutPeZV
zjXAc-zcpyRDdj^4izN-V-bs6N_e-TN|NTfOkN>wGx^Z!hVyQx52a9^xb|(#1-9Jg1
zuu8n-*1@IWzhY%JN&B$ozeX_Je_Y8OA08U4r?H6K8r+zp!H&Oc@b~S_2<=tbS$okN
zn$fa%?SCBxqMhttJ^X!x*M$bpi)$o*a_eCG(B3s+m1qRJhD&bkr5jXFrJ{LGX34F=
zjiJFK!%9(u-NGfe24{x$@?{zc>t%{NZsPWJ!afsyp*3pou$?q`W{p&8Ot?L><ksMn
zy2Vm+!b(wlnF(H@Q2s4TjP#b!-g}uwqWsU4ckJQz&|r;FDQYk?<@=)sU#Jx}Usxxz
z<knu*2E|g9!b(wleZnOk!Eo&Pw;q0$-D^ZRGVj=*_Mv|0dt5&=3H+n}>~TOU6&>U<
zOK$xc7ut)yavb%if4J<hMZ?G#u@6Iob+R(e<vw6j!vCC`S~6)cGf(`Z4weiDv5J{q
zg=RCw-#_4R|C`$vOHI<l!T;XF-#XZ!WhymuXr`Im8cd}IcPy4#5Z=y>9&u(W`9~dG
z7EYv&5BLAul4<()Jq#TT|AB34SSxDq$Z*+V2!HEfr7**q-ZZRW$*sMSYl^2%4@cyv
zz4VCiC$|Q#dL>V4N~V>tUZ%KX2RDX)?RI0hF=}w+PTDK^TAoxi!kHyhNgn@>4bCf@
z6~AnZ8az5&a_iuP(BRnUNym~~2e*gzmWQX9sJ+qQ@~`&7{l}H;gm10OlltW^H283p
z(7_@}gVAB*Uk(1gy)_@_Nk!*GGfSrU+XK!VnQPb0O7#!7Mm-!CF1a<hIed9N`f-NL
zk}3Yypa(LmURG+f_9pD4y>zY5@}!nzS_|gZ;O6>Ssr$q2Q3of5OKu%}F|_wr_L;@u
z-~BDm9GQ>XNrUY+=SiLAQH9lV?cm5pS*iEKdQk_b?4-SCzsQps7Bv(vne890>^Ow&
zn}#6_@u<NQ!zH&zTr+%5sp((n;L^}u^u_(Cy(pdI_M-iN$LEe=Tl1ufN4HvX+axUx
z%1T`m){7cEC0ugr;Dm4Uq-tjx3F~Ew(F2Y?>YQq=_iJ1JYo|GFCk<W}-kI6=FFfM*
z;XgQz_K2tdaeL9@Po?hvAy53WB)$^<<m_S24lZqz_1hfv^sruTkNBg|UUa@Ivt)`p
zZsN6V!oPaVq}|M&G?@A+99lE21#@e#al5dM!|l-~nH4U%b#QuUZ*I8V@h|rVSB3^J
z3F}1-&JLH{8Z5XiPwJw-ut^5D&q{r1lgx?kKeq<22)~9=C-X4Fikae$L)fiTR%%YT
zG3wyiIXbvsh-K=8aO#;~@}#;)PlFb>rQ_%5cpJOnwa)+A#`8if)4_TgtZ%(C1@oq=
zeI1U$mZ-t#a_|o8H4p#fwtZ$L>qP5yir0%y0a;EDE3V932}XAuEzu{wa&|C(m#p9B
zsL{60bg)lYFT9$F4vz8Cep}J(4db(_)t$PnXzKLv?6WY0FAbNdLRPp$jfM)pEk6_}
Y7M{(rn@-58Qf_3pld(}ZEt%r~0kL85tN;K2

diff --git a/Debug/Core/Src/main.su b/Debug/Core/Src/main.su
index cd84630..de7dda4 100644
--- a/Debug/Core/Src/main.su
+++ b/Debug/Core/Src/main.su
@@ -1,6 +1,7 @@
-../Core/Src/main.c:69:5:main	8	static
-../Core/Src/main.c:116:6:SystemClock_Config	88	static
-../Core/Src/main.c:158:13:MX_CAN1_Init	8	static
-../Core/Src/main.c:195:13:MX_UART4_Init	8	static
-../Core/Src/main.c:228:13:MX_GPIO_Init	40	static
-../Core/Src/main.c:269:6:Error_Handler	4	static,ignoring_inline_asm
+../Core/Src/main.c:74:5:main	16	static
+../Core/Src/main.c:152:6:SystemClock_Config	88	static
+../Core/Src/main.c:198:13:MX_CAN1_Init	8	static
+../Core/Src/main.c:235:13:MX_UART4_Init	8	static
+../Core/Src/main.c:268:13:MX_GPIO_Init	48	static
+../Core/Src/main.c:315:6:HAL_CAN_RxFifo0MsgPendingCallback	16	static
+../Core/Src/main.c:332:6:Error_Handler	4	static,ignoring_inline_asm
diff --git a/Debug/Core/Src/stm32f4xx_hal_msp.cyclo b/Debug/Core/Src/stm32f4xx_hal_msp.cyclo
index 04630e9..82a9ef0 100644
--- a/Debug/Core/Src/stm32f4xx_hal_msp.cyclo
+++ b/Debug/Core/Src/stm32f4xx_hal_msp.cyclo
@@ -1,5 +1,5 @@
 ../Core/Src/stm32f4xx_hal_msp.c:64:6:HAL_MspInit	1
 ../Core/Src/stm32f4xx_hal_msp.c:86:6:HAL_CAN_MspInit	2
-../Core/Src/stm32f4xx_hal_msp.c:122:6:HAL_CAN_MspDeInit	2
-../Core/Src/stm32f4xx_hal_msp.c:151:6:HAL_UART_MspInit	2
-../Core/Src/stm32f4xx_hal_msp.c:187:6:HAL_UART_MspDeInit	2
+../Core/Src/stm32f4xx_hal_msp.c:125:6:HAL_CAN_MspDeInit	2
+../Core/Src/stm32f4xx_hal_msp.c:156:6:HAL_UART_MspInit	2
+../Core/Src/stm32f4xx_hal_msp.c:192:6:HAL_UART_MspDeInit	2
diff --git a/Debug/Core/Src/stm32f4xx_hal_msp.o b/Debug/Core/Src/stm32f4xx_hal_msp.o
index 67ba9d1a96d67470460214d3a449b131ab0c3037..1016e7e638e88f071dc098d2d7004353f7996f4b 100644
GIT binary patch
delta 142002
zcmZ_02UrzJ6E-^G%$a!dU=Co;S=XF%&bsEXYtC-aUDtzxm;<7qf{J3mh!I5rb4JAk
z0)mK&5kVAD6!_md?EcSp?|rV%?(|f3)mzm)9jp7W;Yhn5SK6&}=W6vlTA?%7uxxj~
z_Kof_6<drg)1&mX(%m~`F>@Wil*Buaw-#etOlB&6ALG`e^i&;rEbka^_Y35z+U2f=
zxdnwx1;#^nr#Ic*?=n}ZmI64_Jq7A=_lhp4KA+F`6J5eZg3LMTr>M@JQOr3%jeqPs
zWMLSAVGRual`bZ$OxY5w!jzgXGa9k}=bugJ#W4)mo}S82H(6$mvf-t`{HAy}l$qa^
zg||fJ4`p3BhWT5G0e^vVeUXt_sQkWAW}NJIU1At^!*!Nn*#*C<49DhKMTTdc>=uqO
zu=i`qjKGde7Z@Y^OCOaH*)>-TjKuB<k{OxJ+Rriyn?8qSR8}7-FdCa*OkhlGlcfq{
zX1mSj84J5VQDUrYiLo4GW4&?(#?Gc*R2T;vw}fMK_DizJxUn(uB2$d5d0t|Qv!Q7Q
zrUbj%8E<4tvd-oLQ;O}oNMK5{Ylg5)8P<8t$dqLlf8&{QtdDA7%Cr8%M8=&>9KbRj
ztg^?zRA8NhSf(Po{IZd$#71?Lnab?0n;cVxz2`15RoR#fnW@HR7!;;D>%Ey{YOqI8
zsWsWWUnHg$`&g5h+U(NjPKl|*4s0$mb=e(9jZ8hZlWb(_vq5DArUAQXugWxJuL7<S
zJHU-)8naJdsZ0|#)M#XWVo$yinWk*yG?r<`{@laJG-qdyQkWL(v&B5qlFixAGp*S2
zZ469nRI-t2!>(z_F>P6=pUAXh|7fc+?b%j0jZUTmyKaKWbY%N1<C#uu%eNBKnLU5a
zz;t0#cPLC(cB_$Ny0O7|Jky;`d#*A)SoWNe>B(MsZeV(`WooHRZ}!7Tmg&m|rSeQa
zd^F>R#wuedJ4Io*ZF~*1AVYm8&+s)%Ohe0&SZSoY%t)MYVII#IoC{CN4BxDz4`p#;
z#3_l93_@{EW(<h|Xdrz`22+kfd|97kBuRJ~2?0sWND`Sc24V7y-zZO3CB`taB8--B
zjDdLBOL!OpDkzMhlKvOoEf0yY{5{JU>ggMZ@e&Ue4<}>f8Agi)iPlBjV*k-1W3_Ve
z13;PvcI(e@3AT^OX1Foe1%^v>5eBZWABZFuA#t{OAfC7gjWM+F5E(9+Cp-W>4<exc
z1oZM>pnzd4<K)u+MPh5R4EO3^q`OuSum3};yNP4CH~eTqlDN!Ugw(lzeTMs3gao1i
z!(|r%F^1wjWrq92heE8JJI{TSIROg2I>7Yza;`F%dJO>a1B4UxVj4(PzAH=Otao^Z
zD{v7Sci;htLKk5bx^?Q0T5=J(&<Q$h5m7>DKM(*#L>XRht)gR>BctxdjJ^hRZ#&*S
zS>u2p4!yhrh$F1A9K?*QvjM1BwtVMaKoE-{7|z)K5w#TZ)xa66K~iSv+en=8NtlAM
zfO0g>*Z?`IE62(i4d~sPD@W&yEs<k#<&@xz({%yk1nHFFjGd8VVd<;8b4Fiht`WmV
zdpOaSEBgNAtE)W>VO09~<gSZGK7B)S_<!3A>AGmRLSLr;e{^Za{t!LL#>Ru|DDg9U
z9618M!f>|ev+<)=8l23CBFZ52ZP%X}Swu*D!50HFs)*3|8QYA^=pw=@bOyqhB0^{E
z`|c^sSau|k9o5WSOC!VZw)1GY+`lG-#xi3oA`JY&5ej23A|(D^x{+~kPM4e}bnDok
z(TlRILLU%rMTE}RJHs)>iii@t*hpcD7ZGKIcAfh(B{*A87<Fe<s$P2iw{9%ti{0w0
zG9|faa&Or{?yXo<0fUPW7=FqCjDJIlC<FhgmB<V&A|#;$ddkm5gvL*sCo{u}2rFM^
z1j`IBB6PlU7SD_*B1*Vg-bl_yEu{?K1LOFpq8xX=SZ#qBT|`vkspXB~Y+oQ&&B@Qq
zVVJQ+S@rnu^?7Do5z&YjhY8I1BBCizjqsNu?3R4x1S9inQBGU_kLfHkp@`_nQ;VEf
zgx!_rPsq%qqMW|GS2)K^E+Pi<k1%3QAp-qxC{K-bY7zDb{zkscOe>Nb!*?|E%=9AS
z7oJ+~j3Vqwe8(d!GqWgXme2v6aaIxW8y{UxWM&tM&EqExF*0+Cay)q!gZSJc!ke*2
zFTv#P<VN5-Im+a4Loh)Lz{xEVU<5RRuSM?$p?&}U%(o%}p9VuuUJ;>zXuy0gBCH@9
zGCzt4o&PYDXYz}P5{!NEJ(Vfoa?k>7BFzKBxxZ;e;JhC|$&pYj3@}hUQ5oSPKMpKO
zGW_|5{a4u7U@u9PxJ%F1uT_$rU=|r;V}1=-R$Z)<kJQw6@(f0-r%?l7xGM`;Mr`OJ
z3|zx%Mn-JnA|$R8Co*C)7va=6<xhbTTe>JKV>sMLX2jOqae}QU)jKQ$DH3Z7sewy^
z;jYcX!lbc_FmNTW!qXxoi5vKeWuzh?jf=|?7^zJWD);EB!bt61gzoZ7>f|CyaL&xT
zDkF7wQDwN|RiV_&MYwY-OqeG7yNF8M`7F3F$VF7+elHFehP#Mbm}pz_j5LOm;b~FT
zN)zAVoo#plwZN9^%VV4_XeMERet()qW?u=DE4%5S0qZ`4(`~bnk!EmbpkX1kVg?U|
z86&MYr%=JY;oPe7^v-Z;RbXdLIjRu@_o4}M)|I2r(uixg7M`vzmy4Xn+_1sO*--v6
zbeeKKQb727#DQqZwP**iO)jD>7tM=|w8g_oSsl4P=TPt<S5{Z9^EuSxHW$&8tL_ej
zU>DJs%iRrPr)vfp$c-EXon7VVV-Mw;V$mw?aS<aJkw#i~g9pY&My3ZN{(x^Hz5-(y
zlLWO;ju@yeC$#0dB~;W@BIXZ<9i5K{yVPt%eJzYpP+yN$K#N^g3M*8`Ft;bi$UpI~
zfMg*pYZ<xa1*Ba2k1Qj%c72ngrYE;^5e9C0AaXjo2#LGYPGID&E<)pC+6hiZ?%|>^
zffc}&-VW*(I@eW}7`dN|aO1KrVFDcJB8qVyScAz!TtsoMQ$Ekg!(2oOF7q37M!JZS
zjN!smES<;j)!|&RDKP?5O^!8VN$>im@_l!D$2WE2qskA<QxVWf@Ezs2@|8fiyXsng
zT%LyYN{mRenqf~#<bU9ABi~v^spCa(C(<z=|JUUn<Qo{JsFxWyueZqguW!uijhz4b
z2K7v(gR9t1E4O?+sLn1*=ls6QjMB|Tlwb^_#`BEQgD($5MNM1zJqGV=V>BLyjlUyc
zMLuDjg7x<U4+iV<C^yX4?Dz-{>++em1tyqX=qoa*j3Mm+fR^%Wp===pLys5mXPx~e
zeSb?bIK|@L7@3aB#%R;Ob)*DTp!cG7uWa_9(i*sSCj>?btZ)fA?%aF{#8wYlTvp<u
zZ-LnEkqV*;7im)&Wk-eU5Ua+``G}klmsl-sTy2q2cDuyta1%Z_QQW=d-vGNFH+c(`
z_EoqIrAD0F8W0CuL{nF9Qx17hZ)?eQPK4`W9*?2Zikm+Ko3Z0AqP6RjDd8UU$=Wg^
z4d~)syo<CP7L%y)PwT)j%60w&bc?UUh%7qUOqi1gLV_u!4pW$C1~X{a!!?YG{V+ci
z-!q@ZVyzTqxkQU^PoNE3<Np{k$+{j)sVYNJ<=y`;3cWER4bS=*tgX(2Vp`&VHfRoV
zoNi^OO3eA%^v?PI#)$Xfjvm;VV}eL<olEcuGF@^(HH+j1nmsG9%r>1+Ip1GORDf6+
z{C^38=HWWS>=vjJINvc$$=3hox%hkk<&S`o_wNPfAI!fPfABvWR7h4XEK!($YSOFA
z8wV;%FF8kK29sQ{OKviD%r3dX)r;hcyczoc@un{XT~<f`|9CT2_(<)K^MyMVE_M<b
zwk;}~Vfwo4l%RJiRlt8Zo%y0t{l=91uf#6=F8}gpkzO^1H<v*V<xF^KuC`E{sofk+
z!QfpC53YsqAIDIP@f%=sIR1xa{8z|tzRklaFx?zzUM@s@7L{eYIaqKs4`kE@qzTf}
z|JpD&BBLH`kyWk)I#**Ch}FTWs!P&CCJ38>ZLO*v04!p%#IzT4X_Gr1d^ZQajl-qp
z^0`P)ufw(}`JV|7W7U#2)^2QDVnIpLcN6~K){8k<-u$0oE6Ei94?ra=0BGq_Eupf6
zL=q*7UKyrDssCg}l*dE-Pqwt5uU+p@rV^v7tyLaPuxu4q8Oy<0p{O<pr~JQ_Q&inF
zBUzw<VakoI>atnE@3p<L9E^`f|2q0raWs&ES&VE%jB%8AYC`c#*HET%CZX6&%yxWP
zta<Q{_v0*rZXRu9_|it9Sl=xyvV@{6Zx)LilG(#r1@|_2kf~tfWxJr<D1}Y9#tX*Y
zDz@B`LnwBx0oDU$beFv0f1kX`4J7RidGr4xLohuUhh010rr7_8^E=t%LMiJGpw=r<
z#4l3fLoFqXXkm%9XAt)1{9d+{Q2rGUjQ<7L&Y27bzFg@d9$&tU>&0)CF7+v2_J0Ho
zd;ll9X#Nq4WiI~xi^B(U<%?*3J0}&16dK$Gx3l|<|5ql2Q~e(5)j9XCeua8n=h4wv
zMiwa<XfcHUG7UyN?-ZxGzUMP~UyDVZz}&n@0&zcM|B4t27OBj}Jd(efNivC?faf3a
z^gQRK;Mr~x@#pQA@LYJE<d<Kg=lt39H0&ZY=Mt<W1!i0}v6^k9_qv@(AwP-7^Y&5V
z?_Eo9jjM`y8Zg}m%nB^`1ZHkiG9RB$4(*AeXI>YQPdh*eXQD`}Ha@t(y!}F)^vU!-
z{20BrYfrlSoW)43^<+|ex1P)=Cz980`DA8D3W?ssnnYk?W)sKHlO+FWMfLIVI@QpV
zrG&6Bl_VG3bCte1ab9(%_td*&^5#sE?~+OQJ!(*{DTLk+HgHmsJAs7kTPfoKwu}NZ
zu@}Kz!LAJcdQrLGucYU?4C45>ljIRBlJJ=xlM}7(QEu!R!kO5BI8$;c_h@%|U$}s3
zV(3Y-_1AO4fBZ8Qqsv6uiKJ-_5|xV6bI~pm{T55UJF#jOm}iaYeN`VSLHGLv*K{}W
zFTWvI>OUd*dDDm=xsu!(ewq0HydjxWHOb7`{`7p6L7XPP)B8b0b_8ZN0)-e}2bCv}
ze##~@^C&pN41Y{Qb+?hwX;)3m#2QFoUN0w3lUY>O@+*k*Bbp@d93X^4gUE@c-c*b^
zy~wR$*~Dq*YGG06nJ8FYLbw%4F5aVJIGIw1$#BP-1eZ{sfMP8Ku_S=_HU6OYp~LA}
z?kjP!T-83t<><BI1b4j{8C!9cT)+N^-r0xb;#^lTKID;1_9!x6*-BP6UnHE8{v_$_
zhAphXL?x2}_W<&1@Ev;ALwr$S?z=jYJ)hpEmM6)6sr0V-k<220GV`a63_lJbxZ*P@
z*P{ucWrS1it|Ro-r*tHfTi=rT5w6b{>L8gxPE4}`Q^%i($-mO`wmS(u*h0@e*m+}r
ze3)crUZC7!mFa!XGy?57k#fga=vi_i8Gh+YPPF-jjJ^JgIDc0mt!0>$1ZI;?xl<OB
z?gzxT(W<_<+W+}aM6^V_6MgqR!8NT%Y8NC@*fE)aYCI->U<OGRxJHW*m*MW8NM`0z
z;>SEEGxeHMxf3Pge7#Lt1D{gOEnQ2w(`ylO^gGh(X2S4}?_?s;lPjrYJ?@gRM%da2
z%#0YS*hOFI{jHH82F)kVt&L<L@G-qVbPX@dVo29Bh$L$ar}wE@l-uY4nY><x_=i`M
zm5kqsKd>fQDZpM4?Z1CNVtujG(;MMUREsw~R|b+oRV(phBFTK3>swYrpd4TEGnM0x
z7uDHHOcfZcMiHmxax$N{l{nd0D+^4RFFDaCj!b6Dgv>=!Zu}WYI+-h%$-uBa^qh(a
zIy#lh3Fmn-x$HGTtn#JjtQ3O2X(Jim?PS=h)BEG%<mkp5#3`Rf?|}zNcZ5XGK80ld
z-F<qp%PIHET&j-@th~|wmm<mzk9w1+fYSwx@T&;4TV)bz?-EM!BAGhhiC?}Ql_2&v
z%DuCfo_Pp}0Ms>meM=yO<8MiR)>Sf@S)H^d{Yk~!b(i?hT`k~}nJhkax;%=nLPBQ{
z9>Mye3&EZ5L}d-dIv-7G3h~F)CFNs?lc2R@KY-dAM^6@eUV-@>MDK%Vlh)i}B>Ct9
z>DFpbE^hut?|-$T65qx#fWX|?MDk%{vGu`3Qh`h=f7AQlPJ$bDfPnmQa3L_AJ&AM5
z)nR(z#7SV*?<eJ%^GWMgH3I$hAQ`CJgr0wDBonfio^f62xfg*P%%9B(tz#OQ@1&EY
zJ{U(I0+W<O8D(8v@queftumBK8StH)2p>;XS~{E5$}}Lue_)@3@4ACPw;d;r0UJVe
zwrDEr1cXXqCV~v7xyI1;KL}^f8?rK%r$R;}$SE*E(-ms}qvw!95Y7QGfx0G5?=VvE
zTSlN^C&^5lNYKf@k`vo+6HpV^GUV`N0`f5u=uT`PP_c7~6ThBxKj8>QV5W5?{-y|e
zhPo5q?wVOjP^)q>x7reP>=k<cvxW>Th$I8$`q2BrCiFalRUmrsBI4iql^{&sE+E&q
z_6xQzMkcfz8LRmdz1Maa@O1x8!ZYOtc8yG}FmlUx1CRGs;R>F^u;er{&I^61+#3U_
zl+_UiG&0|t67<L<s@O%Yc3^wWfj{Ocm9ic-zUXoY=op!uh$LcMa}Bi9GwD6ePS15B
zNshu{8G4O{%<P&<#duJLFcU#zphNW5$Xs&1bg8`~1MgapC_jpPY}Sjsj;%*#;@gtw
z_AOLH-iYYo;HxRggzTVan=$nHVxq`^mutnBR+4IK9|kcaGph;}=AV|N`=T5@|HPuk
z$UJ^cPHgYv#Q6uaJf1+$^dOUMf=TVzB{G@+fZY1ggi5^AwLWMZLeQSWsbno&ZGORK
zs`i*8*i+ErwPeU-l)cJG9OVi%?zMuE4%g@5eW3py6m*c3hup!;GQ1Bt?+Z=m(4+zI
z|K}12_zA;0Qd1lsJO}R+uh1kjD;uXK!k>c*z<16=Oi1uz>$ZpWRqTl?Nc`C?5nu+e
z13tmYP3(^tP@CD{1xU8A_wn6?K=$}>7~RT-XT$0?c6T#4wViz%0`*|l`M4X5?O;2^
zL3AhEXf%8cVL#Gbv5Sq9z}(Fi5OWXv#TzE}vI#Wpg|fT)0c{`a-2~YC*@zxcIKc7?
z(TonVwbFroh}}w~_F;A&jq_n_-LqgGVUx;&I?BeQf`w!3Tjy%%A7^_g$UMP*^#%4x
zw$XFg4QH#`z&ypq&<K5+9lHT&5$vB7GCjj4Ux)d#?8JRgk7Umt0yBy|PvdJe`}Ynw
zbB>+$9Vq8<ehZWf>>mi33K!YjK$yS8b~%XT9-E-hXm_8rHG|y;?A0--?1!vZAg~{?
zQ!hayjvY%&fdtljIIt7hn2S(MVqem@_Jlo#<3iyXJ30pjpR>8Nx_ZerU4x>%VsHKo
zl-KN<GGM-EU+jQh2D_{f%uMz<t;Dm~m4y<<zmM#sY2aqFZUsm_v29+#?q}BbJnZJM
zhHhYfVZ#SQBbQD11nMihs3siEW2@x=`#YQQ83p~pp2d-qP{{hy_g%zQ_CVfZ?&x}W
zxRUE={I`8pSw@3Mqq$w6GGp&T9DNBh{UTs#R?prrJ3D4J-siMygH0VZ=L+t%AzoLV
zhXU67wiD0#e>DNWfm9L38jh#=DVPnxPRAu~XjKEP$vBmk-6B&7fYR}!;K-W<wn)O`
z)mXS!t#~(dLNE6Be1u*EZ}tktc;hm*)ddu5Is3FShM^T~HliKEO14Qgbk1$;U!#Gx
zo%O<{2Gm1LC%Bc*j=2J`CETo0kX*t2)&st8<T}z~Xfro%HK4b18`q!$!nm|4&^yPC
zUIx8eoHGwQPAZ?p={*-2rApEU%%j~<z|{?3f{a!zjgTBLy#YX`U!95PDt3$l7xu8d
zeg$GA8?hKFci7&M7(qU>hVB1Wfs#B5fL6EPP@<aSVo}Um|6qDB*1oU+gGrr<o;U-j
zOGoC$dL`Oo{b8*C;~B=C21hKYr-nUVpa_i?>_Fu<4jBMHnpmvh|J465zGhSI5}wUQ
z(#oW{=Y5#(Fmfrp?Cy^X8bbdoG)auyQwcJYW_AP4?2$E*J1@fq{vx)rFABGeee?&g
z{n$f=0104!b7~OT$rh859AZN)01amg5oj}>W?kM#urBw{urB}6<EQ|Utg8f3EO~9b
z$Wlp+msl!^t6G(rxa=Uft$Kp0D0%z^o~7>|f<cc(k?^$gAOD~}tIjWrdUV#VS_ZDx
zujmWShW9Y|3e9$IM@Fk1x4>z$V>UeMs8gfqR+sijy;DTU53u8Yh09d&i4Oo-_Ipi`
z6_2!lk?Q|=;@P-CLzrz-NV~yqZD{K`;3oAtPxb~ar5CYnHvwm{ll=$RCNOgH-vPdv
z9kv9nZDET~K`rfM^A-Xlgq@!Y#a%4_1YR6wN04F|d-@CP9%1cvh@58scn$RkHsUZO
z&#<BGVD&QV^A8lRu)YzHyvjBTLs1^Gy@o*K5!>@V%*L_K-y1+boy}VbjaO`AD$Hy4
zx*J5luy3wIKbI|49R|O$4_AWe!_6uU$)#L!0SqqVl1qc>&;5#f7eWA6unAzBxYo-c
zvWFYK8(@1m_dk#q%H19aW;i!{0Ypx5o#w-f)7(ubZS$^j8z{DMjjPOoy35_808BjR
zR|U*uZV-L56z&u0r*Q)!P`T+`z-LhJxGH8;*B7n=ZUqUReA&6sTf+CXL17iYW(_1)
z^Sv>N3Y+-+RM_3jmq5r^*u{ULn%T`y>*GXvl%E{~OUHPRi2%L87wZfCi+n>Y++Cm8
zeMm<rRs7=}$V!dspxl*LEI?eAvfGcsl1AuoC;+xPE{n!{7q4_YCw^l7ZHuM0jzamX
zs}lfP>-iHr>z=8DX9Hgk=sO#apkPMR3e@sigiQjg^`m#F?{=wu;c&;`*%0kn1*dhw
zz*|eeA2E^kX1`qij@)T=y5c$Ww`?HHDUpmaoHgbSMu{Sgb=SdYl<`w{WL-9LRIr=I
z1`6`-8#8@iE5R6L1CTRDoIe4gpTuV^AhSs33Q<;HxqWAdo-n(e1@o-A{tsC8wZ`@X
zwZU3=`ro#Hm~Hk6jwP|vAHqyB8($t&3cHKuuV?It(!ft+s|4dqKWAh2A=$w7y9;9*
zxdul77{F~VMPtS$uEr@OTeutUPz>bel?U2ZF6;}EZQPCPfC=U<4+6D=Gte?NgnQWo
z1>eP$UJox%a{W#s3FlI1e|?Yh+5|7|bEj^@#6#{aZA2e&-5)|Pp0m)F{W0g?0?b6N
zlfQ`hCyD!$T4*xo)d<`auFE5crgG{mRKzoGJVl(IbI+#(^aW?8a9}zY@dJf<#ofSt
zFX0WhVhZ%$a*^+V@}Bdr4}}bF^gfiulMh~qyhVJ^CrG^bskrncc=HLv;k^$(_7jiw
z|5AP+EyqLoi8gTe@dqbB|32R@64V3!f(DpJeDd$`JC0v^49v%TJZ&Ho`1%xcNaEMh
zX8H+VeLRvBzTg+AKjoj^M3Tm@$0@q-oNu!S)JwifL+GXRug<~y*Ss?kl=BTgmnPnK
ze7E0#{hq%?=0ETswt&jyYZOBCBj2VJV6ypSimZL+tI<v{hrh8AR4$*9gQ9)q6`B?D
z`1fhh`_4yDdGmRz4Uz>sKLZ6^WQdDIAr>2s%m#Cb;U5Oo<>NG*rX}q%!>A+_bh)9$
zY?NZ9Vd`NRTxCc^Hxt$v-u(dDTEmKDDEb=81VeJYp){@(3L6aTaHmk%XqeXyc>#v`
zjgf3JOs0@Rpy5I|M1l;l6qnm(@Q#NU+YJhpWrty98uE4;oWDiDsoe&*weSKL`l8@|
zsNw1Y6lR}6SPG2;hJg0aIA|!-1k_=}+Hyb(GxVY$$WcR8oGb~)3~yV5dBWhAj53`x
z#3w-Ew4w0?I1^!L(*$5=4NDF|J<{;GIz*xkf*VB687etXpoA9;53u$ZE*iewgvMpV
zUK6~yVt7TXtZRlXkHEZcxOxqeHx1j$!0%gzo*I(dh6WuVa>uan6wqP~4_gD}o}tDD
zIP<_zmm;GN4PE1?=@>?|0!qB$d`T!I7!Gbml4$S`p-t}-!|HS-$%gVP0rS*QpF@&r
z$XO4W=Z5O{0Q15S>VqWRaIYcqUKxH#go!tXy|uu6YsgAQl3{pE^Wz6Y<_uIxmZ1`D
z#XcJDdjk5C;d3Fp|7>XY1bJT!pVvbn*U<b=T7P~sZ0rKjJVVNDfc`KXnT7hwH<aB2
z8Bd`sZ7dcEO<zILODH!AFy6wQ%5cp`csK-gxm5TSx9f!E!c`S|D}?ScP*!2kg5+u;
zbu|24E4)a7g>}Nd5zt#N%<KcEpHL$j`%l4Nc+dkT0)(coVQ{ms;{p`72p_uvJ4mQm
z4We6x@0+2&U5L7f3Jw;kwt&b^;RID)i133dc(?G4!jOA}m&ZZv69Rg{(te?0Sx6of
zZiYhgkRZ?|J51Pm0A)FXffP*Valt18*e3)F&6eSU?FsCj62#}Q8zEGi3F?e6fHujI
zf+HRxQNo4ap?^;36$t(F!rwt)#tSDmgL*7{2?doTyz2nFPlS<Q;Y^CKvk&r~3USB4
zd?q~D1@$x`l#U8sIE6AS{C+7^eFvFWLRFe`UkmT<!c$M<fon(>8U5OU>1C`r13q~h
zd-a1eKE?wrp|I3=m1d9S#$z$Cw8H4o6WFVbGb!@5#%QYngTBVzG^?#QPQeMZu+g~Q
z3I%`T4~pDvGCJ85RMci;i}R2PG+GtF1Q|Qw;)oDye9#KiJ)`ePh(0u)dj;x|vBC)C
z#Tz>{hr(my*wvsCjS_{FlZ+1=K{DA`sy?U`qudt$rWykkP|u9<Ly$Z-p23N#@WOcX
zFp89J40lpE?UgZo6392kh{JI4t+Do8D84tQ4u@!lvEp@D$}--gIryWoML1wS8=u{Q
zUXF2GI3&Ls7tVke-;6UpBkzYXVHQf5Z*0>J>V?MQ6esc&r{}`LVv&zWo|mZq0CiX#
znCnCuCLZ_%6Gz1-onhjb=(QDSC&VqMQNbt0nRNkrN<2z&kJDmx33ktj-v0pRtT?Lz
zm{H=(YoMaVh69mzUc49!%nRaOTDe{lbB99YvUq}m;aA1WsbF3c_fxF$hS)lo;=eb=
z=`^BZAwc1x+u|;YzuXo7`HpWGD<<rQYxl)&wCR5!`cOlBB-U<>Bu+HY>i@C$6<4%`
z1TmgN<t2$)KD>V-{zVJB6!9jm>IzTA`6J-kGqG_u*i93E{s?<7#bGNc{+lkUflz!S
zR=iJ@FQ!poD?=QByCT8|u}LxLe-wK~!HaA$rXG?U@e@UYzKE;4Lgbqmx)=(1;#-Qs
z=8Ltd`xl5OyTS`k$<YqXMUp$k<-H`|*KpKZ$~p*Ve54lVkvNx19jZWMx%B!0EUl1!
z^8x58>DJ#+TrDlWfn=?eyb7Z0q!xcef4$U$T8W>u_dJq~(&)wT$zO7dhEErzdereQ
zNmV-`xhfs}6U=K;uis(*rZklziMOQ2H(=<tG(Q)Zcbrl$Tr3x2rB=hhy(hKr1hfZI
zFWMD8l%DiQ5-)LUq4-$hX&aCzh5ridBq?ky%%@0sd!YAJimL%CP4e6h(C3mLVZW44
z;~uw=F8Qv2`fI5oHr2u#sWFX#@1(F7D9d}v>2nA!evk(AhDN4Ti7NP`^mA_{*;3iJ
z$onj1(Gf$ARM;8JuhM}HRO=Eq6$ZacLKLVUlCwI{3Z<-RNId1zv`$<s54#4+OFl@=
za*14*D&I%mb_>Zex%zGtV!0gV`~%*slncJW#433pZnFz(<R0swzgF&rJDymIPFw<N
zy<Bx0U^dE2X^rSFU%3vuo8)E`Xx}VH&@LoMj;7grtGo_J;X<&S@B|_|<bAZ!36Tpa
z$goSU{RnRFkzch1%3hiAqxj1{`Sfd$`{jAH;l)9@J+0CX$)znw!sJySz&s-Nq<(N*
z_Not<6Y~0zzz&y(eL!+b_MC>o#K{wBOi7U4XlO{3<F7*fi9F{hl4LoqKkPo0TO0sb
zsyxOB=5slu5yhWh$Z2Qcce-r+8;Y-F^8kRpk=xO1_*P!p2Fwh(un|N)$S;n8`Y3<e
z0V-SmeiL>-%N6O=B1ew$M_#Txg3cws%IiC$WZ&gdWd4V|Z4B%d$g9JFStviEc=#ga
z*g9H&E>;>m0-CpCwIFke(vuDhmMYILLuQ#$Y(ErND9xV&d!_RGCy1<8&Ury(jgmrV
zoa>Y-w7T<E&QmDGPuYt_t*}8!91T5xCD{flKpDIP3dfX(L%}?*Fmx7vQu%Zn)#VIV
zu2b~nv~p)AyogZdQ<pib95x~|QsEK65Tcd5HGny%1UG>G1!b^5EL~K-&IEN?2`>(X
zE6TyPki4dpqUif|<yZ!Mx~a^V3d~zd-+`d+C>i*1if~t%OJ~COm8xX#fm5kVZah*{
z3uNMy+jU{-v2wQ*zCnU=bsS72DIpZ*exhWhLFB12t|F*ZC6OZ9X^O2HlIO|^I$C_G
z#L!A6U8(c|$!lc=o!Y)p_?19;r;Ixb=6j_Y1w}t7$LI(pQ*rhk4788RmxIX6RzA^W
z{#mK}9+q+x8-mcnSEV`~`+idfwLrCfR~Bah^oP=y76=8(-!Gt0s91F{7pa95vs<io
zEe7wmsM~0J5~yZUOW3LgO^3)fH8K{?1gp`_;KdF#(s=^rL)2tiWA0K5=}2IYT1!N-
zSFI2MnSE+pUDWJ;bw6zr4yq?<>vTxnavzq$)M~UjJEGR11>iB&Q--DEYBn7^pH$no
zfk?PIvLfuBR@<CGc_Y*li2ysRj=qN^QeC-|_TT5!+l?T4UbWLc?xK2)4l*vOp}3Ta
zMcuQLsF`bO$q-OC)LPVpZmLs7xE-Tb#m`HG+v+&#4tLd?v}lP{&tO^+?yE~b1M`8p
zgueYF)wTiZaq68E<ULla`+!PNvpsPBAtb3yX~KS@R-vt8iaL%$%1>41I250$aj9@W
zO)dNd*e_JWX1MlJy?-Afuhcr!yk4u>Wug974W|>=cdGd$l6-Z`UVtspD&lZNSg(2X
zM2-4s`a1ZuLHpbi<~M5LFJ0?T&5#FffEGsq=1p3M8_?LS`ILmgKuw`-Z;<xX4llN9
zl>*_@HmxFUg12j($(dm7+)vQkp*^nzYNwWb0hV@aRd6R%*rT;61rPUW<LFkyer<6t
zFk`fqUm<c^dp#Ur&O6#D>Hv4O3N*~dYS9gl+|wR@Lvmm9oR8#zmPm>Zwd~?Z9%<FF
z{}<x4g$t0xYu|9WTu9Z*(8=mEty3mS|3aH{49ROPMuKZ^wE7=Fz170Jki642Q%Lu{
zR_YFt45wD`rx7;rpL;<*%38sZ4xNf2NvPpU$0Nb1>=%bZRPh`KcdKgE!LPQkF=VP&
z_XA#y0;-IfORqqt*3=r{)ILmC0qRsshhKHuw?yIU9W_9{{-zE<Xkd*8X2bgAM56(n
zaQ-GVe$W{TO)6YQ34Yq12?I@+Yyzj*^l5-=z7-Kxp+ye?a4qAP0<P5~>U(XT#^TvF
ziCSX2Y6l_Hem{<dgbpw3LbBsu{&1_ugwEg(4Znf+i7V**abAfS;4fz1cY-gg*;mf8
zAh)nJN<nTr%MS+RE_UiHF!!-0`i6(uclZAd7OxNo_(N=^IN@h_w@Ms;AEsA}GiW`r
zM%+!4-&(Q62IQ?1s|`jeeZ@W$G+Qrfo#2w6*nsv38^jz6G;9=QPcWVS;_6}$4G<e=
zAlW3o3xd%=u@-HsgT!xj!Q3utQJ{jwUKD`bA(mK%O4upBp?&;rao`Ln>=92dfoprk
zg-4MWD)#G#ynUkAPe}HQ@uT6z0nuYJ>>d=Wmj>n`@doWX4m-tJbo3G?UZZ1!BjVE8
z;2sqn6ahRYW{g2{Tr6*Zi4$UJ70F3a!3AX@T<lM4jZ<Pp{5lWo;$AdCMTnzlk8nn;
zJRi=S6+O4W?MN|W9ej!sJuV<GT2y}^IVZM>0`sEi+)5qnlGxh~o?aGb+(qUUv13~>
zuZr*6z{EAtZ#(?HE{^>SyEnwKyP$YWT+{|8VnnwlNN$V1w@~YML~CuR-xY5sKrdFz
z*MM?Q{M;TQ_r+|w8S_ZIOqg+Ei6_9sU2`X0%6KgP)e@o!qS*sUqS&uGM3Y2zJWBsW
zoM8lLvbc=Qr-(lh%u{jY->A}5(f$*hc_uEb3Y0W4fWG~6@kc69UWgSJBk!e{^)pJA
zF8<;HyRXE?bh7<ge7pw98!;u)3DCFVD%#S$6Empt-;3!jk%<*}aZn#bx0f)VDcUw8
z$r6`c1?WfdDMj(K#mcSV#V4_E894e`d`M-<5r<!e!7pM+CYZURRskY;V(By_-^CER
zLRTP01wpb<teMSY{PmPJXM?*)3ZS`ciPWD=ER|+%Lb6P97a+PqN~5sWO36Y~%PJ{t
zFY;DP9rqwvBaNggSt}{1PAt;DPJ*Mp(#kcU)=NP&Tlz^$QlY*<x<}i~jZ%eapaP^?
zezgDCB$;Te+bsRK21`4n@{^G4ls@>wrx58zYiR6}8qw6hTMDJ&aF0~efiJpOI+_QO
zQ0cV;KJAl&=$LW8lv)SO1Jali@adqmkCr-zq;$F`byzwu8zN!S4h763QaHuqokyj)
zvti<x6h$lP<C3!_WKKw*W&rf0G?}&<;ZnU+)a5B@H$^y3<EJJlT7(q17ml8hlw3%j
zm42s{N2D~eG1Q}^#k4YvmbM%~-Z^Ot1sKmuXODrpAn7y?U6iJ!1NxFvnzjU)m!*#N
z;LTO3Z!>^ilLmDJ+I8t5HRKyoKHVg|DSe^w^OjU13B4*tTGIe%w<SIS2Jc83d3aay
z9|vZvl%EZeds0$2Sh_C-(LwVA>031zd?;mfMe<1MSOH0#<lNgAGVu~01MJ6AJ-Tj_
zAie(+Nusop?))W5>4O3KL>l}N^^`1CqrG;Dl(iU+K9yR#!F;Ne7zp#vq%Ws|k|rfq
zh5B>pAG(|ILh_yu$(K^F2FY}(CoOnhNm&$)do6W#mWSvY>B2>L^H$n>8kXKkLPcc0
zm*&vUAwyb)pYCCY)S7BGQ~I0({VZuHEk`~|Cj7Vy8>OeC!TcoExe3=kOIOB1GDqq_
zBgA6axflfukn4Cta*N#l8;TStH>1<DAi4j0od09TQf(~Iw#n%Z=x>+5Y=(ZYT!|u3
zJLJEn!o!_%B|0Gsk!wf6(Oq&bZTEJ|TSg<<Bd1J6vR6);2=!3;VrhWwlXGZkwO?LM
zJ^g@uVlVOz%g_9fgvrb4F!PAqafO2ZcU1P92$^GY^@^~2T%HsR>VzEO2ZJZ&#r**j
zF8@VmNT+0f>f5K~(G-h}kbBWUaYine1rN{4pJ?R}DQm5e7bOQyhELJ*`2$GK$qN&q
zeqQd{0?7rr7|jP4<qL;t{c}lP-xV5{<?u`J?TWma=IX0*p8{ZCliSlt)^(Xb3&k7q
zN;9hDrd;hbD)E-wj7HlSxpx=n-Ih=7hvXeOlg>f!%2z3p8Y?$B3Y2?tep7tO`*MR3
zfPNrnQsnrde3T*-&PQ?`I+Kl)<pUt&<tzeyEH|zQ(FEB%4VDt+J<|Y_B>&tS%qMc;
zI+Q6{-cPHz6!|EvJf6zuZbC9uZcV2)&t$)4@acuT7{47AUdjV#*hrT<JcY<Bxi}T~
zwLIiFP~JG@DYWx`D`(>8O2Rw2R~VdmFZ-l}%8<v?NyrD;UKfg)vfDN!S@N_(D14M(
zMWamFa{a%+{3H*OVDPiN_8IhY<eD_6evv(BnUpJc^8n^od0;Due3PBUP=|T)ol@}P
zyX^dH0y2Ndrnab)d^!3K^b6$bxSNB0qC6DlJ(Z($uV9hVBM6|272kbedMP(($L_6+
z3xebl<>W?y`Y5?{1$C+7vlEibl(ijUez`J`_Pi^U&<q$_sm!HYE31@`laaSt>ErZ;
z!8OXYGtgM8_-%v!I;902SNSRt5l~#OZ0!e8Kcx$;$NiN}Q(!4TdHE0WHYt^dg4(Qf
zIg4bA;?o_@1S$&&Gf27RfWfUwk}r~N%08O-wkyr)R#ULz*9hu6l)q;>LGDz}?t+OB
zWq*0V>{9m7K4P~ri{f{C6njh9-K!j-i_f8oy&I@~O2T@0xL;{T%lZRK`Fe2spfal|
zs6$Fi+VdV(IO=0zN=i%U9Z`mz1a(xg)Ah1rN^{!N99LQyX#amgDV_@Qq|%`~TntwR
zwTJ#G#bSZ^)5>Jp{6#1cU*O>xW&8{<&nhPe0W?x6wGYfFCG!ZF(Msr9NS;%Q(Ph%}
z$`RVUT~JDo2j)fPSK97fQcBbI^0HE&&f=~pyeIAduPQ0~;M6t6Hy6ou<r%fI8_I^g
zpl&LraxigAxik+Z?kH(nk#|>_Nx}G7W%LBp(>-M@em02xbeEQpe4x~EgQbVc16mn8
zQmp6TOq}v$Eeysh`&BR>D{mO+B`90kgNZ|^!3ju{lv!?od7_M<tzfd^N3o+6W!q8c
zKUGS8Ln%^~f=Lj0rfgq{yfh`93i@1Gn+bz2ltpv|{8A}61IctHI|nGQlyyBJ@>-c4
zjv9TVoU4Sqw@Nrg=-(;VhXd@rQ>pY1%9Nqxm;m!Z89D(}rt<1nBw0!q+^WFlJcaI9
zWh+A&RKh3abWKQpR%%c`%27OQfcc`NHH7(GC4df&zAAr__urJuGz8}<g~OomUHRiS
z@_r}}r-GTUG@(O_0>!CQY`#$G*BzOj>S;2uNbR&76}4FHMmtI`wH6J!-l}pIB1_bD
z6h`+^y(!SYRGmXX(`D-Xi%?ju?xthyRqEJDP*|;Q8vtsJTBi(9eAVu>x>~Ppr>&fy
znnV$He|4{OI%ERWZ4_zPq%NW_8mPL{P2?aoX*-gwYTyDS!D_oPFtI~DO4t2&s+Os!
zpxtWxEl_*Zy}8iatIoB-?tZl#4JilIGpE2js1Bxe;32h;j))Jdy(uIargow&#1VDo
z8R~yW)f)6kj;W3CH$f0T=pPKx6KdpMz?@Wj(<w{1dYqy?r_`Ag;XkdG+Yf~ZHFX5O
z=ovNZ4)V^bJMc4p1QlA*HKr()ivSg^UVI6+&#9}jAaY*y9{`05>gm!Dxu{OrLGkZP
z>dZc{ds%H%5~5esL1W<JRrOFPytt<3)I-f&SJO5?<Ayq?2h878|7Zm4Tk0noQDfAx
zG_K!PV-taWM>QP**j=?T^`=<0-5+rDfokmp>Y>`cBa%m|FaywW>Zvsn`d_?SwmD!P
ztIz0AIYC`E1Nw<-3~gwV)S+eJ%oDX~a~MoklW3|+QB&yX^r@Qj9ClMxQ!Su9Q<r{#
zLYg|2&Mcp+4U-}HLap!<^j@k%+d?5-tsFwVLQSOuk=N>ey1D0kqi)&?jkl`%W_a;V
zJ!eMddo?Wxpc(4H^I(2Zmu-b&raB`P%q(@`bSQjOZ_$rKvQ>B5LVQwp7l*;mYF`S4
z=BPom%KD-{9su=R_11FaeO1R-gNNVLXTL)sPu)t(qwh|&(Q}CYP%Qz-%vX<72&h0U
zRSFeVs5&l#^3)0_I<-i<-Uu3twHA5ETcW*1&_M9fdgs8zQZ1f7(=zSsOeieZ;^=sC
zg?6P0L{@4M-J!Qi>q^(NR%?A}OTI>{W`xLE%~^?pz3a3<UzqpRuKot>^;+ys!1!s^
zMnYqQmcWAAsQpB70Do;}CY%Y-iqYxYCQT;0o3*)%fwDzox`G*~CD66-Ak9ig%v-fq
zwEEtrU8ZKWT^mm`N3eEDf%zR8?`(!|xKm3S51A0HF|90iX|c5E*{yxa2Xl{>Pf@15
zn*0@#p<2WYB>S|(6eQlSjTYh40j&xx!VhZI;$iTRHggV84r}QLAQGm1=?Uf$E#3~4
zqnfe+n8&n@G^`)jK4SfWuBO!y0eVWSSP|4|ZACt+G(ro^2Iv`WYb27h+9(98gh(yo
zZ@@%pXOdtyTEjIYbS};71<=lG5mQlz7c_Y{)GumDbS!g8EAT_!Wi7ukEL_p5?1sWs
zt#kt<*R;oVX#aOzdl8My8=5yQuWo8nYQpbZ+7{Z?#b|>F`?eN61lV`9`E)XVSHpoa
zI+u2H1H8DW4RwQS_qBslkUY>1`@-LcTHH3MKhnzZP>9nmT|{2Ib|?@9e5@^L4SNZi
z?Qgn&ov1aZMNg7;qBoKhEqW*XeyaJuglMXEZ9J0a8aD;zUuX|$)ACY#OC#HBt!o&V
z_|@(K=)Kjx(d3q)CHx83K4@LeK`&F2>AWmkt33b)KWQhzA^BPROrt=KwuMG5=ND~*
z9b~Rn3#(xvPisx*gx|G}V*v9*YfX1(@--(1O9k5FY7i;Zd=2oz)0Ec}*o#aHqCqV-
zz2Av?@-kgM47=W@mKCAC#H25Qf{&?MF7lR|es2x1Wv0*+)Y@{BFWqQg;WXvsBXgz6
zLKn|gnXb@}309lNQviF7DX;?c*P7f118tqjeJ33CHEn$Y6YEW<pFzRTw6HNmHki6k
zK(f))dKL8iO?7_<N`R>k1+_PsK2RIqY^wJOrQc#2OE+!<O{Or21eu&4Xaly@#O?=o
zo9RbgxVYUkF&I>^DT8{>4%0X<DDE^3@&+@+w3!0tyG)NiL2|dLLjz#%F?A{p5BHkf
z=@MP2>F=^&?lVoIi<0|I9*3xpm}=1tk%Ok({>VFI(rLavY>IW#8B>_)msEfrGhKUu
z%;ToAH0Yi%Rqg|Wr%dm&QP9(-V&qeVY3LcCoiWi5uZ6RwA<>YGG+n*{>?qTds>q8r
zm8b_V&Y2_!^v;{2{s!g+)1`bUTr^qgz|bX=y9%?HO<P{j`R^4|9om*%HN{bbx@H>C
z1j%(%lfy`En5NRv_D$0U3QpfL)uAyV#<ZjYEZsJ-G;iK9HK*|DT@yPTV6mp4;{dy7
zYET_M-8VI&OHB_<Zz;g^&@}ZV@*bJYOCT9%l9$r@Gv1UL3Yf>H@>G{erWJH>{KRyL
z+Eub?$UzuPG0oAyd}{I<3CUE`g{w%Oo4)=9*It<NZo^WB>GcgXfe)s>f1#c-O<}~$
zG6m2y_R-Xz0twls*XM!x$rRlh)MwMZF9!6#9Mie?sKhTOrZP&AYs&u}UVJs3q!W#A
zrpFY9$unK~6V!K8JZ-Xmn3mvjtB`N<ZH1)3wBi}^3Qa@5!@Q??HjR3V%%?qJX|cI-
z7dYc(J~apyyv>>PU6+`*P;AA=JZT^j=Th?n3L`Hw-<F}j+`K;tUaT-L`wPrfX4V}r
ztIaE#0CbJnI~ldN*8Kigh^#Z0rY7KPe$f$m>&-EA3g&12nJ$=ZFgF_n*EX7M6oK$J
z|7`(SfVoLi7~EvON2geu&FkiZxy5Pjp9YOUvs-z<1ev>E1GUw>oo=seGglJ<y4^gH
zZgB;hL+A$~JIurA0_sk4H|psjW?N|}>@rWF)!lBhiS7~YF^_2nxA&Rzso(B5kKYFB
zfcaAzd^%_@Rt6%6%=htU9E8JWXH6Pk!^|mLK^`$5r)ADj^NZ6c+A(v3D)8dCd44xg
zC(QMX@cX2BI(`8mgqzc8rFzP2Zvgev<|#G7j4+4Lf!7&xSBfB<HGkw`H`07R6zWmt
zBQ&Q*n@uHP{+xOA8i1WQ*L6-pdcpjT!t@u-F|Uw$$vpTnsLSSQIG`1-n47PL{#A2n
z+D2Y8pLl_4yKY`6An%6x%zl*crnwx=F1O6x_rZLO`ImuU-Zoc@0rQUe(FS1NHQz1)
zM`O*)MEG>iY&{Ce`{u+26#su<&Zqi%Xx_gP+(%}1B22`Y`_V~tyt(}?pglIvp+$V6
z89QI}5p&ilpgl1kr27oX=0-c9mtuC`0?DW5JlYMWng#sb5aF4*O&=6H&3u-&@XyW7
z7r@>N^G4kN7G9cn9>kyi5nh>BxK2yVQDwk=V{Xy~8gI=W-vRT^972~B-kZl#bRxst
zi9+BX%wBZaF4G)V9X@55zf!pPqxl=vOtv|f2bE)PJPndx%uzIm<eK|Y-dFRmWpMkO
zc`@BJ$TQc*oj0fO-8`ii{QhC~Z3Tn*=DDi@T3{YJ8l^8Zp9)3dY3WGS=4IJPKOOV7
z^rQvk5)1bbmV7KW0m)L!pKE}!%yN&mn9D8K+d^c8<-j-;X{F_s9U`kN!`=gBwWaP6
zh^(>nrUk3h*V2hLmFq30v(Wdm+@6WAy}@#oE^TkLRB}hL{VntEf*D{r6$g<`7Ii4R
z*lejrKdjzj@uPt?(1O3UhW=yuD+vB>wfwOJ2De$_-@@Q_OPUYzf-S`-!0rx94*qtE
zu+vhHR;nRR%M7{-x69I&TFY)rHbvR@SW4A_%wEg&olp$5d|CyxeU=67A-UhuaSM_I
zmRVFm2Q7)6QHn#B4E&KV;jkr`>M6`pJ0B=VEKU7j;;5w^3+kBV8J(pZw}b`2-xHR>
z8Swt3#c5N)4Y!Q&hs-HUKWZPREoFmXKEkqS6hO~dB74KNvqe5dTi(%Na?Uck5ZLD}
zx2efru!PW6(2JH3S`J>aJZb=x%a-4K0DZ+`=m<+!EsaaV!gWilUjTN)(y=<cxM`W;
zq`~u+MWVaSF&6JIDBiYwpk2;g%PQKM##&-mBe`ceL<imXEf+PQJ+RbU1WOMsC8-0%
zTfWoQ^s&Xe3A{+KOsWlLqUDPR6p}1EhePs-#n2Abm25dw9qK8TuN0YjYFX(|_kU9@
zwvq7kndO5B^J$jdm!R?7^6m}LURdUQ1olfyINd%;w=ALg;FYBif51?9ZSkfP#W$8Q
zG-kiGET>QS&Qg{_{_ibQ%R@cGGSDB)50+y%WfU?kUq3=2%kq_i>>n*xvRL%LFP0Yq
zyveoHr{LLFOZHoM`ppto4KjI_uH}LD-4a6K<{y?6x?7cRsYgFQF0gE))0aX^5-E6E
zUkAgrMb^3%khj=+{~GeVtWBvMds{!Gfw|Obq`mAiYwai~EVmjb;7|VvE35|UGApf(
z3gF@@>k?X0thUB}0CSDC$p|ECtvNIqueYA)0cZTI31h+BU}fmG=|<}@9!!6$fx_bf
z*6ixQ-elcJ=cJphAE;Aqv2J?^%s}f+vKwSIzCp6pYNP`IXR!5$4456(YIJ9Br?t)@
zXoOfx(MY_@+UO*b-PY>#3-3MF1@lp+z1I1|p%`jS3W33W)<3CA_gmZMf_cFD<{Jue
z*t+fsB*Uy9AAvezUC|dJN392ELgART8;x4Wt%Y>3bHZtDa2@GMYncIXINZwaf#@mg
zpA8{%+Uk26en(i_FGb!N>lrhWv(}C2z>c(@?E|0AS*t~XI&ZBIjS9YC{e><tT(pjy
z3hI(|lM3^ft>x#!?iK5$4uHODy?+RK*Q`BwNZzzMyU@Pqmh~5$1qm_Mj?~p|TaUg4
z^NzK77?^jhr!GJv);hjF>f)Z&HVAg_TXouzKd|1r56OpC=XWq4S-0<liO1Hc;ZR7h
z2FF7r(b|vBJCm%XYeW5swGYK>ldXk|kfc~YJ6-E4Ymfy6O|>4Nt?e`G9Xe4;vtj{<
zeqa^<08F|ys1%s5tT=&0%ePLy3WYb;b5)V|)|yKDuy<A;IwyT^olf^-GOT_SBl%zr
zs*HkWTDSiIGt2st?pA!XN;aTmTYJB7!tYPk!YRQ1Y|WwNRjzdmg+aesFVm%gZ`K=q
zVJXiVa{_4Jt+!<`e^`@gnUZfENRxSibt)}^3a#VzgIa8BLT%N{)}5{gc-wAQLf#VF
zNSdL2Y;F9(Txt_(53tN8yr<uPEw?pm2$>bO4EinkN?V!H$XsPx@c_)#wlopcI$N{m
z0QI$T^zqi)%F{y3&o++k9Bi=lq>a!<+iJS$=x@uVL-+vOtJ4tKWHVic`es{wYPnl%
zb!jCOX!A;d$TnN&LW;j^xAp%H#bBE$AIT2eJUZ{(X-j^C4;x}jpk3K6+eF%V?ZzKf
zgrz+;uOxu(wdEO5GoiLVUr=59Y~N^oa?n<A7R*Doz;rMV+iuY05@yTV2<RiWK{R0=
zwTW9{;h60dZ9SaFZ4SCPb;4FA7)3i}GtpJU)3#<5)QPZ-{~0i6Y(u61^sG&yXj`PM
z>tmor*{ae>RJ6^9R-ET-o9JH8dD~vP5p%&-OM=KnTLRVk72A|vK)GtmqC=-^wg}qP
zUALvxhP@k3Tj&C$H*M-VWZtq3rNhA(+um~U?Y3=HHyFHQ3#<V1cWrO!0(`73o1&5r
zY<<szdT7g~1OG?1y4@ieXOk;~ino=fi*%1|$<&Y%Yzzfu5^W<_KqSf5gKj}SvGwVP
zI!v}X6IKBx#de|;OgyvEpH&jlY{}E1|J?SX445x$BPh7?($??}^wVvttWbDm>qJBU
zYuhH8V&B+;=#Naiw_WOwD#@_PFJa<?Eru3pnYO4p5XrKYp<mB@v{||UCEFHcLalwW
zg*ewk<FoC>0chmdloH7NVyk=&26Js&sf2m90E(o4x7D1Cn)zY-oqjx%Z@W1Uc?GtB
z-oP%jO{EhsPkSg`Fk56V_yFc&d*(vudD(yMk0N>7pP7-j#J+L}B$wMK4u$#(dwnyl
zKUdl}Q*?ioy&biy)%MqOp})r7m<sA^51>fEdV41d8~fR-)P=|f`?^o?Vxv844ibO+
z&VyhE*lV=_*e3g&$&lP^uUHG}TkLVPDGan9qRmc_z3>StcB{QK9fWPO&lySa&+Yad
z6r>Ec*QdLJJM06WgW75Lp@nORJw!!4@3Jp@2x_-|2nF)@*g5)<$X@%li%<x)-x!F3
z?z3;X1-<?Dleds}z#dG|`GfXUIy*XK-$Dl^hwVpc4;^OjLRS)w*nh=OOP#_|dsB+J
zAG7bE8S}Wk4P6I3Vedgp#*_BmX6T38S9O5KDSJcwz)v`BZ$(jp2>a&ED8(6j<Wdy-
zto`InB$4(_Mu<e&b=qr1+e_B~*g1Q1+MJ!YzoD4y1^bbaFm%zru>(Y$m+bg42WAPo
zVLM83#hy*^{Hyj_1A%?bo=$hcuG`=J2J9R5%<|B`X<z*p6mHpZ0*S6-?@WWqZF_tu
z%6rG&i~7M`yW#^AvGzf9h;q+f)fJ$!f2;wN2lhrok@wI(;X9H?PWw+!VJXgDX$utN
z?FA*leQf_21jPh<>qt<E_C8^#{3QD=Ix2r+uSI`;AlY7@ZV{x|>;8bqQ@eKvs8su5
zT1Gyz*X<0EH2cw~(0gv5*#jak?9DTQ`O<!lj^Weo14!YO-5E#s`QF-t=&t)a`{%}}
z+4uJIbPS(i|9Lu+5B8okU}V~@9gt+%dq%;;NBe6ELS@^18lp^}?6#6X`)uF06((}*
zu@_+Qi@o_*P`UPg+fhMZ?Gd{{eY0Pp#Y3Kb%tnBHxBud#S^S4x-UFF@`?LkXF0k+5
zVYkrUI}7FYbhw%D@fJB^DO|SLA$EkKm*Xn^Zq(bc3_rsZmN;tCw$;ZGCn9gDV{UyY
zEOUfD1IluTcLp$5IL@R&eWl|<dw8+R5mOtIs~v0m(E4+YBa*JOtaZ$ws}$=TL#Wn$
z9j%(c)AbIoKau!3jE%tD;OIunl#LF{73ljrHW6rm!<`nTn;awQ62fLj2Rh;0;<!RF
z_drKYx^fcaxJU!cR!46-5!&WRss@zpj!yaX_lJTV6KJ5>;b=*BiFP`2CPOsDv53mM
z%i*yL`nw%9=c1nXIQ(~l+Uux8zb*-N{7&)OeU8>`k?eOw-hui7M_uZv2OWc>K^=1J
zryE#@9le$VEX=Wx0rU~aEUMq5j!^^X?++bwyrRR`<BpU$sEZSh-d}-z($Tvbl5oee
z`_Mn-;J3rXX-CI$pduXq1VjIfW6}o{^sHm{bznz2@Mo9N@f><F=tVmYbMWGvqwZ7a
zop)5d4uwmOtuLT(+3|TjT)X0UN-KKjRmY}8C|+|c>;#SLj%<ox+;E(wn=3aRt*yYm
z<#_oI?8Z1QP;B+Kqp>GU+;KdjBl^1z?gpq>M<U%#yXVMD1@?VMgR&^-14ka+!g=U;
zwHvke$gz$_y*S5T9-!hK<px9KvC}cVDP$5Hf%8BnI`$c$pXB&TzZHApNT!K1+2KR;
zZi?gcdpP{mVeSbk)p27!3_f$T?*l5$vC|0b=Z<b=0rtX?lL?<*Iy#SlrF2J`5rBT>
z2(Apw*N)%mHp?5wWV+e>*5TaO6N>K~_32jHd&e`n8<62R8VKrxV?ho?GaX$|!HX=%
zCpxqK=;*Jb60#lf^<m<ZL#7|6e0KEx2YES;?0rbSI655zGuQD?T}Xa)w5WpQo8t*>
z#q%6DYeM9^<CYteACAM$J#atY@qrF53LG72NnhyrjRUr)-T{A>LRh4S$navZ{<R78
zz4T^u56oMyb_#k+^r5pM;-fEE2a%=vq)TvgnO^xY%rDpV#=u;mUu+4HmHN3vsISsD
zHH6*O`do^juhD<qPHUgFx`XZnt<&9T9q6mKJPWk-`iuUM@zXnP2DL%&zyM~W9y$#o
z{(4#ZrF?+ih1T1f^i#7Txmj<s3RM}ThdqRcTXpx!$lIo$rWUka-|Y`7SieiR;CARZ
zmq$<2|NcnxUx@BUv+ypRpARo~>oHbf@6iYMh26b6M-hln{cm^J-KQtu$UxYyFQvQv
z2lUHyGILPBR1PACbi+nqAJ%>894$;g@fspW^aPrdkLsRO>|^?0lVIVvewPBgC-lTo
zbpPz6{@^6^!}U<Awo|%B3)j>7khMr6bRW8oaz-CSX9Q>U4HTV^)Q_u3qV%O!B++_y
zDw1=$UpOSs>u)GRdqMXogr$r6JKFSL(qpOnU)B%MMdK@aaT=hm>O+5mYtC!>vy#xb
zuBYt52fCrh=7GAYSEq^OmL5tMj$`yO&0+qwzV!_9?&u4D1<YMNcnV-*^)$Lwc293c
zzXiIl+i0!!K>wNUOg+@6)Ar<%9(Wg(AE#UHATM5@N57MOtXpVzlYsMY+O8++Eyux|
zB>g4*uKS73(q<=FUq`JhMPIQKu07SuHG^cTzQPUWpXudZAumlIcm>IGec>KB`a-Wx
zv8b22Iuw%Wx}Zbvl^%ZyuD#aFKLX|({UDvKztw$ceezCs+P^~dy}qsx<}>t=deHcw
zdu2g1Q_q<OnJoR>J79m*lj-+*+4_2F@?Z4Bt&x|j`?ZDoSAEtNP~Y^^(a6iwxlBlY
z*V}If*blv+1q|lvEFHra=ojcFccH$EeiZ8I_R2|@=@z+}=Ym}9c494LyxjWxgYtF@
zq>bMaw@YuK@8i~<Zm}+P`#BTNEORsTLa~>-J=Bq`aLc2m$V#^dSCF^LZ8}}7Snalo
z{+7@hw^C`K*1DacVSSyOPLU5^w?mBqz1~ea_<uOM?zk+gFP;`Q)vVsV_g-pc%glCa
zsi~QkX=YiP*|5yYmklxm0c9u~McG@FAw!l-1r(GiA{#}vApE}P_t*K{d(Zivb1(06
zpL@oAp!|a`qnQdx{1|5fFnFB7c@eB97@O!J@n>XGT04MINd?7$j5Lb91u?p*?&c)p
zUHWyOVz|&V63jS6F^3RFR1jtu%E)R431hT+Vl14om3F2G#sPXpA{kk}5RYQ`l~Vov
zX~xR8&^*H^x(e24Moa=g&oavHLDM<LTrTv+FuLiL6U(?250*HF>n6a&Ge+oCn84_v
z&s`-l-lxB05@VeaB$@G_8;nU|ls*H!sf^Th=uBgT*?=>hagahZ8I0XH&{%EGGrS6c
zmdO~Vw9N$ui|QILGJg3MHf1qfDOjJ)*!UVGau^@(gM2Q-)dH4FjIEa-kjMDi0Mqgr
zYyQMo0YgNWEDISzsye#N@T98&MU3yLuBn*u1+8HTBlat>lrm)JfN3pbl%2!h;0oj2
zP*_pUNTcj$1>?mCNK`UH=(<rA<1KQlsu>G5L17KULPyQ3jQj7S^BUtRiWk)~_I9IH
z$M`W7i&xK3&O@t#!SjcvMn({YqHi+Zeh%Wd7;~F3*2M62h5BYI<KZ^+wlEruP}s`g
z((kH`aeE&G+Zm};#&(;r`d`@8!T6P8LU$OKsXD8Z@iekdHg_3mD<Rj#c%FWG-HbBA
z?qL+Zjj>+F$Ra@ZF`AEprJu1q4RQmF-YozdWQ3D5dXHg^q3e<N8CT;WF~s<pGJX#j
zP2^b*GtNB$v=PP-)ohJ2BB?xMj4^W_^5cxE)39)Y5l?x5Nyc|y1MMNBjY`9(7^C?Z
zn`SJdO#dTBF8!)!7#IJ6+$^KH4H|5j@AA>IW6G^7FkgG-M+c$Mf%z*N3LTk&REgol
zTv!Ob&P<yHKyzUppjo&w8TYUxN0_&s28<h%vk?OB%;)I>iU-q|ylzkCtv|telzHkV
z^m;M-9Khnu40r@`jJdWHU_Q)a^d9kLI{roHPd}y+kqDdP%&t@DJ;AJL1-3skEeGlY
znCxh@0-5v4-wk4lyTNjj`6C4sPBH&|8JdEbBb28JVb*y<MJQ85A-FK6Z6?ISnJ<z5
z7Qt+ZgFqyc`4|*MF+=E~I?a4>l=2T}m{KEDL^D5p0<$>Fd@KSsonyNG22C-{)8rDz
zGWV`RD~`FDK4%rre1)=O2~1l;OJqL&Ed-L7-sImWGo1>-lENIKdpD`f?_<!J#=Inh
zY3a-_?IDoCEPDu+^UU1{MO$qyGUwCDB#Zet1?01tl2#1nFh8Q`elGL;B9KeWOY~RE
zV{WDcdOq_@^3MyH36umaWWKT<<TCRD3sw{{o0mbnnAsnPRtfV;9pp-xCn<(p#(X3~
z>k6~h5i3*9e3D+D)(Yk@y(}u38>yzQiupo5SgV=i6#1`VYJP)hSD7Ck#@IDx3q@RN
znHL36U&jok#BM$FD!f>m>r86{<ZdvzJpgN94!sTRMrK(E1a2~~kRNu7`NUC-H8Df7
zU|KV?Bmf#(tjxnI2(~iiRe)(@Zr_IWYG>Z0BJ|tLQOZPhFdLtS#2seW8IVq9@xNfX
z%d{t_zl*tmyvc6nrtJ{uVcPCTtC#s4Ig@?NHB>p-&%84qWPrIc9Rh<)*Ct@zV><4E
zG548P-6YHyV*cI@i3iMe9IVhV^9^ziN0?cS03Bt%Oxwp8bE_V+7-zcEi)4aXxCF*b
zGVhbw51EhmLB$kv0~Mf5Gu;@#e#G3_1(X@)L=aeJnX?p3wPof1i7`7?4S6v3tU>Dt
z)H|@IxoA4FE-b{L6Dxua7|yKrFCpQ=nx6wrt}N+Is6WE`;~TWxSl5$buRCiu6=Zm@
zD!+l8C+my-AV*nWkU!+b+TQ>HZ`S9x0ey`1<}Aj1Sj*|;=F75>PwK}q-J^i~aaO}!
z^qye#j-uty>d-+&04tp8KLc5fnNV?xwJHj;2xggIKr4hLr82ZomWJxw!&tZJNeyQm
zq(DLhtNAS~S0pQ+imIbnwv_!m&C(O*8P?!gphUAie;RUUS;MxJe>lfdlS>f8GQ9x#
zSk|HjsEA{||2$SNo^|3+kOY>N(!+_Y_DaAcv6iv`lgz642`W-p&(M(~mGx`@>`i0I
zJV4S}hv^<z1}nc6;^$evQqDM&_4Xl*U0@j~YITuy53ab?CX3bk5!7e1O1$y6&tbJt
z+9sFv_Z+k?u@=t2m^{`D9bEHS*VjW+0qgZxSW(C-v_kGO>uK83idcVAT)ddoupD|z
zSUwpTD`l;v%fe->mHX+zV-3?^vYa(h39~C$g>jIxR<eGgkbf1+<O=L+RtQDLYFI9B
z!iuY`O1fx%jpgeC^J`gdN~ow~1qEZQp0)KF1g^7&DXxBl^%Mnz8d&LhP}s<Fpc{-g
zSuc?Tb&Iu%>I$1!l@$<ZX6;FbcnfRlEY!DJSrs3k*~ao1hf(b;2g;4yX6>Q!$PU&C
zs;{`iQqs27$$Fy#V|Q8QJ3zWvZj~78W?lLWDtcIMFF{2w%Wn*FeXP(FVD_^TN+37D
za$gEfgRD967`w;nbV2Jr%i}iIVu)pRs0Ql;*5)^1@Gz^DPWB@#8@dTM%GyH-^f6ZK
zJg69FWqt$;Cs<E!f!;~hPWl4bLzefe5SU`sQu1boHUB%bW?AJFMYUxg5P;aRC(lFN
zp6x+Za1Lx4`TmY<<OcAhvG-UhT;|MX+W^#sZTcC#u51@dGaX^yp-MzIc4!$`+}Xk7
zQ0T!P?1cHA?8R)b9A!%>GUde<FNX?m_SIcrImTW{)fPVNWcu`{FZ&{$Nc`BkFtm=d
z3(3Jf!QS;OX6?`3yp`U60qj5N^bp8?jSj;>Y=#iiKFLl?1<xsV-U5IIvtObYSP1(N
z7kWe4%R0ar#@4(Kxp4NT5}-t|d#N%ZlC7c2uPAosA0VgMTU1~<!)8#SKs0;tVvw_J
zHC39OWB<sZ^Jffu;13uT%U(;{RvdeV9?p2Sf_$w6wu%nwiMUk<o08Z|sK7Rv%{&NA
zDQsC7I#bzu+_6q+?2~3#k<Py3im?oK-P>4_^XwZG?apK$`WIjq*b^5)F0ws81j%AA
z4Wax)HoKFo$zgB$8n)%KkCH2Ki5)~S!#s8rrJ3^C>tdm)fc<(cEG%U2`wc2CvlmG)
zR>ZctV}`}-jfqfS!tP%Hy`}6mOMp_wuD=EKSJ)r;ptGF4m#$V;uy=+7tdgBc)3sKy
zAJIvwn(dbjo*MR2KeVp0S3ZfsYwZ8#KvON-`5%ncvF}Dfu%7Md1x?r4!;T;~*cU$q
zX<)CX(`+L<lipD`*{*>=xy8=84)sm!r>MTDneDO#Hnp+&NwA`weN+$V+gA3MRt$Eq
zYbj-Zhh2OJf}QL!3as5_$I|ZA#SWz!!fv)Ny+(W3KhDEC^|DJl(CTByd<&cU*{dmL
zKEU2d#eakBD{nyj9{Zm=fWFV(ycsM*>}LYd`GCFtCtwb<KcpDP2-~_d7pphQ&ZFPX
z7~3xyWSo7P31cSMkI~K8N%n%fAP?Eg=@$4DTfxWJH2WKWkVkBPcPN};KM@9&S@tBo
zsBJmF{{l=qjtd29?Kux=DIGW>as?bYo%kO$Hcp(6sG{AOv(|bQQ*+_8pG2=K$9pe8
zk8oP)vsP{#M=GLq=M?@0P!CQhCD}YVEF&}><(!~`C@;?Nvrys9nfE8iF^-aoxqUcR
zii-GhLZ1PcAIF<2R*rMpzeei>=jqiz@#lEo1!e$;D<=OhkhA$8NCa_G?*jBBr+y>!
zp5nCs4W3|5Bl%1r98M;%Lpf><1j0D!kI)L|=zqsp1ZT^BsE_1yc0olHC*ozaPIF35
z1M>`rWs9|l<}k_uc9ye>cCB-q?ms|cI4?U={4<ub_5fJpIGR1cj^~{J1SEm;Rw`5^
za&~?V^OHEgo&#tyXU8sdrf}Y#0B9;F@q5^t#`)tI)-auuMUHL;XTw#9pXXe>iLp!$
zuMVvXocB91c9FAy>h!WWztdMNvpF63s-)E>hw}oy17wrS*)j}GmpD08y->i3rn;&^
zPA0|IE_0gc7E}=@<QiCtIfswJm=cbJLfNI9P4wKCasD&HiYuJ@N^q8Qid<k}1?Sg3
zEM+ApU^QA*oQo|GsOGp*TC0Y0Ns3PERnB?JkY3|#xeC3tobiPqb({=}GSqX%Jg_p?
zIe&YA<p!sx2-poA&rcxO$T>)Hft#EksZjM6C*=Q!OV0PSUo>+H=s?rLSx-J%E2sTD
zINLaNnE-3&1aHIaZ*%DX_}O$=Ip?Wv?ha>)4)~p%Bjj@3<?t!*-^B_445XVgL$U83
zPEs*QFGo*_**=bjyzYL^lN^u%PAQEIa&#23xW_p}SGn$U{wx9+;{3N6njUaW^e+X5
zIS=VAI>M=*frX<SYXg-6k8xHl$KW{UKn>(4INy@|B&Um(^dZNdvM*DdQ!@NTra4Ng
z0)NE0_A**CoPS<~`dLmT`2e=u6mPWbxIt7!W6$0H9hTdHTT3^59l5X2xz&kV{xOI%
z_w7*#xNw(R>Ga^rJ>C!Vk8qo;=yl_+qifjiTuA|19^9etG3LoVMnUAGT$igr^WuKY
z0gN{{;B6RsjGMm!dVRP}JHX=0U1o<dKkg|iMLN#yUI=o6d+8z;!JoU9;x7T*>y8iz
z<Qkr_LQ@cT>zfcf$&LC2tyA1XYe9m!>&P(=;jS}aNkX|_hM^V4UGW*l!nyanU{e(L
z70Sh&=8EZ@e}+4I8m(yV%3zp%maC`8$2snp7{<hK579XxmYa1MV{zOaJlGV^jo(WC
zUjkQi6wO5L4O{Reap!J>ZOPoNrBIl{Wjmpj%3Vgem^5w*y?N5PFAf4GgB!UAo#(mZ
zdKi<*&1eU?z-9P>T;!HC0W6DqZ6{E&xjvMO$>F}tgIq2*<x`MLT;xXZ{N-`qxq&sw
z=iVT%y?{GSi&)5gVh&&~bFWaPKoNI=Hzrfeji4w&3HQwn7%SywQRKgj+kn@o%@wYJ
ziigU%WwdKma7Rrbm0ZUw_-j>hUyFx8HMd<4=o;=IeLw3eS3z~X)@$5(l-{c4s`yY*
z$Nh!k#r51$dJL~~2kB1n4ekbdaW-%dQF^P9YcGPpO)hIW$Sv+%awVF$olPLk+*&%f
zws0+!-fHE#Qte?IH-|D6?Obs(I&X6qk3eq+_qTqKJ67)MQ_$4OP1_8;ce!W!LAtm_
zlsN3>7KTB-hs#-osr7RIri$J^?jNC0(a+7J6Wjo|l|1V~Zb<=H?s31TilqBoyM;g*
z;x-<JO%J%z|Db7@o5uv$2sc{~GRj@?0@RLit)B)0be#KLGbARszpY1WlKavzz&zw`
z@`l}0Tmyw3rnz-)V0pw{v=+0N;qI}8`dRK<G3d1ACDQ`i@#Yplp*?RP4JsUX(r;js
zGcS^&nJ&Df8H~B|YL7zh2+u_I5pKLV>pwtq=V>Ya;=x<^76d(c)8u|0<?W+tZZDoU
zt+O|;;&~W+jF(SNr4R21^0R$;tLeG-<8>T^+;QGg3lyH<?OTABKW`5GWCM6d+#w#w
z8>8noh*wYmV@~pd*F)ba-o(G;{{{0VazR3Po1&p2l;@ZMi7?*Ww;&PDi=qGY62W_F
z8zdrmF@ung;)PQ^$!XsFSqPlr9iZJKns+Y;0%v({bQV9yi;aabF}y1B?P7U8dqCoN
z59l62JZ}yydIE2iJ$-*Nk#~v>i6q{yCD4@2`{@8wr0_D!K~i~jb}%N5_p}{Y(s`{E
z)y&|nrHJKu-q8bq$>i;Q11uMKZ_<zSBG0)8#$@qIC>om0>zhDl4(}m_jdFS6^oO~`
zTSKYtJl>i~sz1x;&85%i74V*>?XHm5MVY(Hyn$@|or-wBKMu5F-T<AJN_ZTq%P8gD
zp*pfM-kP_-a)q~ys;bL*hv*Tn;0f?jwW;Jy&}ED&UMi(cs(DUFps<FwiJaK0yg5`3
zc8&Kmz2dC3yb-DmujBn;1BrT`3$62Y-VgTRxxp)X9b*l=rIa#g<fW0<eUtYMc{#Uu
z`C7D^cz;enu9?TuVZJTAa=JL%$}6TS@HXCHJzDL&>jZt9w~C&T4qnSDfZgG}M=R55
z<yDtKu$!0v6?%Jkk|Q9!ytWZ^_VJG00Zc#dC;I;D0Pjf(dJpmjD0p^{r<n(q`@Fa>
zu|Pw-_+4l{;Q6FNV3;SZ1Iq}HK>>_W-c_mx8RN;auz2IV{q$R#;KiPV`bnNOk@DFO
zd21+)GsXLka$eIsM>;}1;{6s3o*CX<ifqmDcDn-2mcOna#E$<>J#4b)2Oq(l9QX@9
zhG~xcs%L@i#AnYyz?tthADu3IuWev)<-b5)_Yr=_C(!4{uc7ydJKxLd0=qr<b}NDA
z$$y@%^&I7IBd^<w??l^{H-8x=T8{BQ?1E`N{L{JU^ySMMfab?f7sHt2d>=Z#p5T8>
zX<mQ+?{rQN;J1GQmO%a#{j7rcA5*yNB!7=HOgqI-rAT%#|MRaY{};kPk%`%d@(tu1
zhVgMy#e>H`Nuh@b{*qUqB9ecI62ejZd=&&w^EZ8g)*1fl7l9qkZ=xOMEZ>$YN6zs(
zi(y3!|LZ!akLCN*TQrXUK6%~o{9$@F6ZqomXeIJ5yg~J6N&NW~PfX@7qdg^se||3X
zrt&|Z07>I7r~+s@zbyosGWZ@WXgbeNt_Ei&KVUuNF7Q97$J8$JS@iXcEPg7*X0rKF
ziy)W7zf4KnT>cYued!WkKq31)e)OBLBA?%n+7_!#0Y66vgA4h7^gW)-{4H|WR>VIw
z476f?I-M0u_zTI|xx)Xv8J*?)h(iFa;NPK_OeOzk8Pr$t6KRL2=HIPGtA_s{Rl{86
z&(Qhg8b8wya<zQl%MhsJ@9KpW_56S7@wHy(SDk>08~m^6p>E*UcVJG9d@G$QZ}LO(
zF?Nf;?KC8s_!4q-oB7|;Q_;d7*bEh|`~eEDxAB=4kaoUVfQjDb2TTF1gU_b&wLAQs
zbolS&XT6WHyL{yy7}LcMrdfAe`4_0dpoia80*PL}T`4s6@!wqliGKb8%B&9XBPskk
z$UpQB#_sWLXn(xVKa>xcA^ziYKpybdoCeA;{|!1Lj_~ak0c@1d`4uY0_yaFMV4R=6
z6)Y3{l0^WU<lk%u%R|1knNHYKe4i=6O!F_(kL?jZ@qOr>;g3)Rah6|8wM4dpL?=kt
z3H)OqU@z#KfQ1f%%al2D6qFo;UME33MF5=z`alS{2o}8sPFKMZih&&w{JaswO%RrY
zPItjBN-B5=v{n~1Jq4|53?3C2nCSHqyhDE{Z^3I`fH@}EWe>eRg1EyVzJd=Z*zP9?
z*J1IG3!aOF`V)et0*Lzy+NqQ%K;YO5V*&-22C-a0g3WYjIVtd=PavKW<W8X#EHKgc
zc|ru|Dy)DB75qit#taigOhY1EaCQzfMF^S_pgvNtAp;gh3H+YI0-YB88Huqof|tpg
zj23VdAZG>n6gxX7*u}?KoZu`~ti%gM9{?;tFht>-L_y3TNRr_AT#O|PYOa7YMR0T_
z-9Jhd936ptn&7>;uq|ECM2C+IK@q*q&I|PPowQ8B4{c~&5d7T^V=f9_{}C)%0<H#g
z$`-u$D?oDu6Fi{g3hL;za!IgZH{|jJA#{Yv7xcCOx<K$PRqqrEQasVREReTQ{G~{+
z<SR6b1?7~ZFA-c=2un)^zug9Cnc({YXu2Z!m#!_B3;HPTQz3{<hCrp@P%$)B3C61c
zS}k~*>H}*8xsR|;R|S)lN4q9CcoUtq0x^{o)Cpc;gVYP!u0Za(fK6`|>kYxwe&}rw
zEb@ZFM#1-eP<T`DKE)1h38Gh^)g)NH6l2YTm`}mkBKYY(NULD~R**J9Ayp8!3-B>@
zJa_`*3$U<5u=NlG?g%_~LSd&MYc=e>D~OE4B)SA&l4H;<;LsVQ$0`V<@N2JNMHV#m
z37%;JYro(jRiO?D;-_Kapx{2GRPPBkwSeWmK)D31AwfzKru{%r{1F6(1--QAj|h^s
zgJo3kENw|+f(yr?X<YCYZJ`r_nLnU@QoyFmY7Ye#%AQOKtWgvPofb5aKlVuQP9A14
zBk;(9{H$O*r8sPbq9zbK;buCq+6yOsgG~;?r6<ASD14p#Y$sv56w`JVzDIk$i*WyX
z5Le;zv|An#o}=iXn=tMi#NCB5dJ!BI)^%YLUc!0SaSVD3A5aYKnD7HL1bu`7bawI;
z{!B46KjB_CNE{bB_kx@d+V2L8zwl{txdMdKbYVVFXd(|NNcbK(U?+u#P}gsBN?6zq
z3xkCV=(2W*&|w!^p+d`P*c2voq6+bFVgELYzeEV9KSeWAc<wv|qlEvh2Iy(wQVL$5
z5uTuPMzqkDzSntH=uW}wbHd!ufEFX%O0IaUaG3G{al&IBK#3Q6-G^xj!Z<GMO%(o}
z4S^)#wQ7td3w!c_nIc?4k726t+jI2(OB4R#1?+U;i?nTJ2sdtk`t!nP=<;-?u(%Z}
zE(qhPZ1$qCxChu-!XKzJTd1dkw;bUd3jO5@AASZ+mxSv_Af6}OMZdXx;f@86D-fP)
z11S{pKSbwc;Q>0i6$#%#SOMRk5GLedg-V2DdjVQ1^q~#8Oz7_f6R!yWbAm*<Q1v@V
zg)p6hxs}2w`sh!U(2p{2)xsZJAXg)tPhq30LWfX@UlV50O{ZF+nIbiH!a1}F)eBu#
zLGHRRLJsvegpx18Vr>v^x4~eea0dSg*5;=01YOR(C9I+dev@$67ii7G+DNdp2-kdz
zR;%!Z)tGjhux|?T?ZWw57<yZ{iG1h|p=&e5?+6v|Lq(^sI~go@h2F0Lx=VP~11r-l
z%p-k0Lfw3@^jd{0G~nqIj*{2iFI+}%@d2UX7VN$+JVEc1A>oeyzvG09X=R6n9&@06
zMEEhqUq*#LoPqe5Fp#R*#)Vt~SSEx!C}27%JWOZIhr%0lw4D+*Q3>$0@asO1M?wZ&
z5}y%TH~a)TEA03XJhmbUU9Pngeftt-VK1@?191@Ty8#$S(J{&+IEi-9@yJ;;K{Y)t
zqO)|J!BsRvxtJrOo2?jg6E#z4*IhJ8F%l2a&MFX3(c^TWIVuXLK)jczhnCA*^tknJ
zz#J33O$SdOk%b3MzM|gcK=Tv19EQYkQ8{fiCq%DP0hzz(2xW8wM2C$S3lt4fRv}3A
z_BiBDiW;1;GN(j~X-dH&6(1x-bblRKLPg~ZF%~9@e;2KAQ3c*LHW8xr=P891DH@@3
zMwBS`1juQTC%x#;h)OBf7A-PR!vCx&i{^Ar<Vs}=F`{R_hJ~>r1^GO2qIgOJ#*6-<
z&}@RJRD-cZ(RxZXB#G*sA&@K*y$X~RQ4oD|KUGxl3s}-bZu2Srk}is*0>2EAYdGZ3
zi;9z=DO2?E8dz~bbi@cNE{b+jus%z)@Na0!7EMulD@QaW086eYilRrCM6Z30u{@Er
z4rBSE-MgTvK=flF#0y1V{(yO27M-R#g(6WyFj$I3p(`K5^H(Cexe+|2B4;YhC=-20
zm55hFOFjg4x#+_Nj8%xH=xRr$Xy|vSs1h|U0Zg@M%Q}#2BK!YfcCE<&IVh|XwR&J>
z>qQZfkh?B=k6hXtqV4-I)*yOa49-T;9U;g~(Qb0pthYp*pTW~4s-*JqX3?5%XlfC4
zQrxvwluMz%Hc>H^YPXBt)B*dp=q(fEJ47)nFm^|zql9v&X#TfgxhwKahg_E^$rGL3
zq6buS)g!8kfZ4sGbEoj<?GshoVXR+to({SLR*^#o&;~{KP6GR$=sPD!+!wu1-(wgO
zeN_aW2cl2D#MrRtwRb^AMBmZtY*h3XnLj4V-w3pE(S;v?Jt1<9L~ByyP1kB3ifmQ`
zdP-D7QPgSCxB&u>M8{vo*o?@H!V0q@Yu_HA*^1AFz(hN74V@6|#g1D+9K@ed4%boa
zLwDDl#I@U@-dUXeJOo_C9aJaeDxUi{EIcAEP6nu(_;;#Qa~FqQ!kCBnZZ=w;V*EpM
zJa}RS<>9=<Z&J0bw>ZWb<d~Ra{T^sO;$O-k;VbURMaxf|`Y&udF7|jGHk}Zs+y?O%
zt7!`l5F1xwEKnSD1oA=R^;8pgQtY}8W2eOLevVeK_-87}4-qff0nSiyCArIC;&*$|
z3K!?40W3nCMxp3P@iU7l{}&||G=b-|xb-JY=8U+2j^@$gCv(wxRy=ONBAyffPM@fV
z5g&{JcC2^-xgc@kINHMF#dB#g31T6+(uv{+e}W}RtR_b_S<IisUnEUjl?(B7@fUQ#
zF+==88_0R_<a3mN$P}OY0fQIB-_jFzQEZ?PT$XslaTt>=ZhaFZNBqYiNUk_(1MI#e
zuE>D;Jn?J<1oFjC(M62{acLsvQYgN~2e~X>K_P%5@#BkNMX|W?4G5HozooBHl#2UV
zXqAb7b)@s>74iN|*j+AuhJw!(;#cV;RVm*24Fs#i+x~@V)#7^!v}(j3uwmL&@yq0z
zUK5v5nNqFzNvhPY6PHljre6HRt5APkY$eCwhPd~4%)UXq;5Nn@#T)3|cvF0ku9Dmm
z%js#dHi_L5K%2#T)xd5MpZgFKZ596>1kg6|=w`Iq#UHps(`|9DJ3u?c0X*1rN1Rdt
z(kcGuW60eVZ>t7Nmv{-KQoF@(^P#s#jITlB!4t2fuv4G-`h1M_iyPjAg#+Tm4*)i3
z6@N7gdQa?6kK=vufApjeiQNSt55)Ud!{A}@D^9>35gXJH92GAhfidw&3dY986S2@V
zA>N$@>`C#eeIO6Tx57ZC#0DzKn-&XSh5AS0S&E&_h{u;<y0hZrSAk+Hu{P3GPCJQ9
z1JLXx<&;HnkSwG>kfS7>!l+J?=d(eaC8;l9GA<I)0LEM;%gN_CB59cdsGH=3BU<i~
zoFy3ZkVtHx&{NX!A;6AGGRPD0l9W^4!&`DW6fDOio%^BQM>1f&4(cmmd=H~eNXnei
z@|Ucpy*EIzkE(bACHeJG5hU6E6wppeoRc7bN-~emrooa2uR?E#WRV<`2$fX1gM>+r
z+=s$&$*E@m79rW%1+YlTPTF9iBo5??pO!dL_T-Gjc>`@!(UO9{fOb}*u?O}!NdtL|
zF%k}itzsqqUxUO+(s#m`c*!a%%}J1aLDv})C5!1?l_U|Z0ZOvOp7zcZNfi~rrb;BA
zK`u=qqPvXglJ^{dnIU<Fa@^-7Y;r9#B{|Q~`SXIrUk2=pl1(#!$&#eZ1$MT?mEuM@
zl7$r9%#}D$=OxMM-yoPL@#_Oxz9fT+g$pF1%P>|bDW<yM%aZk@m|Br!wjY{`C3?yx
zlt`ZX6)dHaZHZ7+CTXk(<`v28PRc)&OBSz%V1?v2DrT*e_|n#2CHcz_##Bp$luoFT
zoTJm(Rmt)<z<EtF{0mrWB}?9cg>{l-3gFjE`WImAy5tT;hHpp?(rdp#lJ*tUH%eYk
zgWj8xYcD~=Ey)K|RoNuTdlH@2X31Z)`L#$ADLUCI*+~(^Hi-)**V`q-bnd+^+0hQr
z4v8BQCN_5@!SwidN{*VK@UG;*U5s@}V*1e8E&1ahNROma3Y1>SGCP>oCz<yZp!+4|
z-@%vx$zTb_1|@6h;=w(uMDYS9b6?V(4W1#%O8Q+skht0dW?0fT4D}<DhxCRXm8_zp
z$b=-7V&{{R|89ajlx!BFb4tQYfN9f`8CtbRlHXln(~P8$0(rBN@9RNqrLVg{y`9wc
zH0121e+NK=gVg#i?Y556`59<BNxh<Bo3qsQF8)9+(!s~ja+PlS|Dz`Dp@XZN)IecH
zcj<B!U_7Lo=;h`qJrDtbqtc6X2=J16(--NyrH)h*drYbgfb~Aoo+8ZCSNa+4=YG<@
z?a+5zYHt;yc|y7@119=QYw`dZAoVW6V4yURP6k2J+D(u@DXsVwET^Q8#bPX2y7xzr
z5NQMz0fkEEQdL=)bmylqEnK>{7IG2NlTV`+DRrmcOqA5u8?DpQFxs`wNLNwlAX*x>
zo{AsNO6SuPdrtZ^l}^S;b=7FaN?U28ij&@??@Pu@pQbl_g7n}<XiAh0rUNud>P35K
zvUKzXtW%0~X%awFrT<7Fo+j;XgT3j}7q6l-L)vl}Hl3HQ;y^r8TG<BZ3sS3v>R&EO
zPyUX<EUE8C2xd!j$1s>99k+nwO7~7e;*vB{gVoEEdQt&PzO?caU>8XH8evnR^eMW@
zeOY>KHRe(zeZ>Z(So$pmze=R<6auqUTC)nIOgi}w$Q9|r6kwK1a~<gWFBMV-MII}q
zD$0;nN&V>WR4r9gfVxJyJR4|Nr4HW#?V5DXClIWa{{A&gtCRZDL9AYy-2#^DQr~SD
zyCLncg-ti5%jxZXOS<U*IGd!Je6*USfe$d&B8@qL>9$H2-9gLRCY`3qv`cq>1%<bz
zY})QRr2EgpiaXM=m%!60{fjogyHXc=@VcZMX-T`K7t#RQBMsPv&R*$~U<mX{4Ov)=
zerYcsC<9XEr!Z|$`mq*c_oRh;q4&P@GR546q=#4#e_)lCk$*8Pjav;eBK<1>gQL<N
zbdO<7+Smn~#-;C)V?QB{{S<%ZNon010DUNR{u`iEQg@1tPD^*BLE$6mI=c8bBXy;>
z;jDB+I8@lm6!)OlPWHMD#_VM|aR76W6%_!*QD%Ki3K%EZA8}|p%bJEkTx8)C{Bo5Y
z%!9-c*)NG;ag)VTpvhgf`9+xKAzSh}TAngH+O>|#7EwakOSbVzDD;-CquA&%Sq{BL
zePr@POu|>@AO-Q0vA+TIahc^X#!krgTj`>QzbuFDT?EJ^%|Hv3y-I)4AlaXZ&~#FE
znQk1NlDR(#g~76QbO|Ixw)uT143#aZ1xuK$iMEY!ng0Y@5i(!ewIXHplqZdnabuzP
zwCvuyn9CX25ETJM%QjM_%vss^5A^(<lg;We7$f7+t{E$Poze+$vPjyk<7K05(3Bt>
zYXV7>ooWP2lI%}M7?UjfijJ=-vKlfiRmP`#OKGxK{sm{c%tM3D3|a9ySaDuf8V)Nm
zW$ag>=z@&Zh*q|2&mQ{zZjS6ZCSY=9A8vqAmt+UCAeblHR|}YY+4X9W0@?3-ptn#q
zY!7=c%O1u<Q<2PzE-V$x(&;x>A`7B(V5zKp3rLwPg;xEF%vJ{Ra+zBlFe_xabRDQt
z7EHmBD%qci4q9!hWq~&^-x`_E|G)Dg+mHl<ugT_cAy_LzjsTCEY~2hb>SZ-lz;ay{
zL>uc3St-5t8)S1_VOpc?g*`CsrtFt(;JhX4r5i_0GG8iXZ<c);kFge6kO1PXvK`04
z(k6TD6R=p@WpR|azbzY~-KRqqH4Sn{<~acsowDc2zql)Vmb}<5*$CB>bjyCClT?pv
zEA3jnvVBHOtxvX_iWU212kFMpfUM^LFb8GbXQ20<?6X=-`@ZZP#pQ-%+uEVwfozR0
zpogupmuYJmk%a}JIVyW}39T`i%|pP9%hu3aVnTL+fw4)M)E}*fGF1jZr)0%(=$w|t
zKLfN!vbaaUo{`y8Y;;z(^$})hD<7xWsGU5o66)>czdnJMgM8x}v>fHCMX=CGZv8S2
z)LHKP|HGyH)++G0%HJ79=MniLdQ-c}J!nbX<$wGLK@a&G6ngNKw+(_Em4Eyj1ia+g
zOF_Kl1+)hqll%OJF&{a%5iMW&lU$(q$*1WUdR)Hp6jtqoeEoCK;4crgc4AHe@@u0o
zI8c7~B6@@5lfOdnr2H^lWeJggl7>|emCucaV3<5fhOuyY`a&p-kbggmu}FEA1aeXG
zufN11oR)vO5NmiwE}{Q`5G`MO5gN|QQ`ceaoct+!D2kDH7o!y`AF8G2FHZjcT$mUy
zkE3H<f?P;7yovH%_W+Y5-$7B8WI1CcU{d7YQv4-V{tU&E)8zh?eMy%$HbWpo{sDRG
z=jFz$z|NFEe+8ypklzwR;G%q53g|5PvLWcpmOo4WOpbiPU3&lJ%C|oaiA(bDDA=AS
zpGUckeED4Rx(nnPj?h~u|8pAhm*s|J2o}i`g27TO@A?*KCGzWkfu&S_{{Qh4xpWic
zuE-5^?Xg^*O)0Yq`HN)`sFe59*C?vw{gkDumfK!^49{PUd<B(tU6t3_!-{KiTe`kj
zD^EBAW9sA^&tiu4@-37Rx-R#oTYWd=(*s~>kmt~MLmTDuo&xAic?*R>Z^<LCq17bk
zlGoiVZ>1x7i+slpK)1^OAg{YkK2!j(cKJrihgomS1>|*i$m8Zi;*R{<7U=DiuOzSg
zu6!G9TV3+A<mh(Gf9!xnk9;oWNqglluYy3Id@C(?zr39apa<k(RbUyEPp!pr-IJdw
z$0FR9m;8p#A^FdTKpx1qKL&wex$h-dKVp@8E`f?sd4v{ZOwOlb<8k?4lMtMcSJ97c
zQhu@roe$+1TVd0bd^Zy?({dmB3dSS(JW5U4Dmec^y`5s)Cos)k@tGIYJ17dMu*gvn
zH3m*6Mb`*8ofRcip6{YC^+3Q?VO5f2azrsrK_NHAOb4uRSBzeVdJn}%<kNa8Hd8_I
zQN?1)ZFnhOkYV+_6|a2>xnqh)q2TmUq|#pGtN4aOj(&>wsC@0Xq96xgCtwp${1wi7
zz!{*}Kw+{#MaIvVS&-s;>vBk(R0t?ma!TQn3YcKULT?O)D0Wc2PpIOxH!%A!#X9o3
z!xh<7tP!Eeq!3S}qMDXFO0n;4*mPQvvI3lE6ia-88Ljx_U9`?B_9Q{!IYnzGCK#je
z_ysn_Djv(iSe&BpHpM^V6(7;Im7sWol8T9nSi0(vq$v3kg2{@y8^BIc%-f8yRK=!1
zkTgY(5LTos_K};Pp>U(iediUP2I$RHuqfPhLGht2P%bJi1w$Z9kxN;SY=zApsLxT<
zEJbIoqGC7QzrCb5m<E_U#pM(X<|}qHz*?aAwgsStiW~80T~>tBr)i25%X}eNtnj2g
zr9|;3dEKRos}=ZDlqt@gMeB-!L0)&c;<^Z66^dLbCRnMc+>XvFMJ$Dssuc`91Zot1
z_$I#9=Bi@mCU~wXD%9YqRrHWISf`jH09w5wiVkwu6~EFi_=e(GDU4}Q{P-*c8WkJs
zA#hVsQUtVHii3J|HYpy^Tew;A?lA0aQMjDPSgT^oO`zOX{6;QqhhiQbTJ9(`V-UA?
zDqQ$jue%DNH(0wAS2lyETM<Kr5j~2(=*D2L;ye|V_9;@YK%!r<l8Ofh6!G;K8&nu6
zQgctS>NT+3SKOxCL_-Q!I(R-%ywwRSh80_wn9_)%#sV^`=sN>_V~Vs`ka4SG))973
zD4Hp<HK`~jZ}OqSt_?6#ipPm{TCrgsR6J4~qFcZ-ifx;LJ*)WbA~<c8&RHOKO1>Mg
z?UlOg5O7ek-bc$(d7TFVC*`Xa2skURh=A#$45A8tS7m7%#*Qeh?zC;WDR25i!d*Gx
z3my-p9T$V1N-3Q>jw*YugT+fJcn!o`i7*u&Jf+QC%-2V`(Fcp*tK8uVP(S6ZT#)0+
zZ|NfH3FUDsSp1c5W1F=JP)^VZDo~k4Z_ywnm$C^bl^#}d4o@kcr4wtgQcwqlA<A=K
z0W?&()CZkm$|G9X6s~mn5`qy*PdW=kDl2GZqm(asg7dU;_G5IOQHDfeouZY?qrrJr
znN6P4IptI2b;l@wp9FNQ@~632pg3h#4M@Cly)VW55|qa%z?G;Bq{^fu<%e_+Hd*-=
z#nn@k_clO2Rk_y#5^2ibUtvtTviKrcGL-9*0D4|IK(0Wha^C@<Tu|;9hrmVU@1tmC
zDYugsnXQbui&l=ZJqcsE$`}8G_$B2xe$V3h%TvDdIAHRX_ud4|W#y6pOuI-q{{VQ3
zmG#9SB}&&wOr}&>#|3AZ(xn2RSCq5w0j*rAuEtn}a)lJ8RVtU$&DSdB{6utCE9<oo
zuTgq;U}df<m)?SgYswGkXH}~#!QswoQ>T2>6EOA4lsS;Nt}HzS6*rWZH-M)>sdx;6
zjmpL=7`v$)BtQ9<ax+Cmnv^S<SfFNQwGv}3%DT;vYgH~hjIlQ5ZTbPXE7k3QzOBUf
zwDI66BfdlD9p(4y(AlZ{n+tL4U8UPT&@QDLohrMPx37WpC?7O{^eTgB^XyaZ8UuE}
za?!Ww98gYC)Ok=j^D-uSPx*BM(C#a17NRwz?4UZz2g=W=Zgg0AoL;db%8?*gII482
z!`PVe<!nr1T-inkq6w?=i8jzl<wME@KU97}=iVvhBX>wlD-SP)rbo)<??A<ja>WX?
zW|fDj#?w}{-U4hpm8A_Wd)0UJ{5h!ReT|7as=lSyiIeIz^17W>PAm`?)c{=*a8+69
z`os~H?P{oXQ(1$l*3w<2B(K{;<+KfGo~nO72HH^-gO0{ts`vt^_f{$D(K@Eu$$@D;
zDkH6>uWH{NfcmLIsZ!>+s*~P^Csb$ZK>Sr2A7~0t9csj1Bv5s{0GL6lo-ZJ9QYE3o
z|0z|DbpkxWD(v8R@Ki4z0SQ&T*#=Evs>7RMQ@Cn?LI4q}Val0Bs$M>Zu`{Z-{{T$1
z>N)zh#aWdbWfjh;<}^WXjOsZFCK0Rp)DA3hsuar2$E&93y_=v~M&Z{)6_XNKNvh;%
zD^w(_4w4U_qH00F$|hAcM3wkystG#crmOntRhOaq>L_5&tDGrxk*R7wh_MT*au<MJ
zRPFr}V_7N>D#^=MalJrtR4-^?Os;CV9A;lqy+<*UJk{zap*~-wgfC!Ipt?0i^`C{R
zoq<5Rta_{nRurjzrGoEbRX*L8DN)5<$5^TAA2(<!Q!SDL?TYGqM<^^;@#)}Mp{l8X
zK&8sD46Q0v3>_7#Rqpl>s8Q{qrM#-rQJDFf%8!n0wW`HYP+zB-iYNcCURC%2wp~}X
zP<-Hq>iZ0s-=NwNfQdG$@?L_bo2plT!PqTT*%pj7sigF%G^<{b1Exh)OP)-t>W?9)
zXjA16L7-i=CLgWas@PVbbg2G20hT+ezyE}3ovKFi7VfIJuR`3~rFxYMOS@Hx+c41{
z)lT||N3TlT3l)8;Hx~k}Uv-eYoB<V+-u{ECKQ_Radn!pW#_p@uz5^9Qs&DA(%mdX&
zYLH?4S8j-psJ`k18C9)$7Gz9irYB}x<w8Yi6RKUi05)k=z1jqrhbrG7*fym)nFIN0
z)dUrTKT_GoL(`1v!kZwos(8x2*s49(pk=52YaRsb)iqQ(;-H>jfH<m+uYowJpGd-(
zt6JF!O-IzvbD_yiT}=l^clGg~Ks?kJDLU_|wwhl?^Qig&mBDzaf2LozxB62BR2);M
zW`oB^Z6Ah~uezoXV}9!7XJEx~^*$>6JfU{{1NQo>Q@_DjfV%cy2n4F%d>NfVYDP9N
zPpSug0Xe09eGsz`R{tCYun_g=bNC^Js;jJ>P#>n=Pu^s>ddDn4Bh=wvLn2Z=5P?>d
z`Y>g;PpenWh2Asj*NwoAR{zria#p>f0-)#APf!VPjJl4Tq*%2bIcIU|+*7bAUhSO#
z4GC%`)x9OEN9iP#r0#P7Sh9M0nEbyK^_3tjTdG<{B?4*cF3N+atJztA$xv^kx{mYe
z7ZM?#sUDt%zy-CH61x}GH7vBU)CL^nY_ipTbO^{%dsE0USFNO%;wAM_deP^p&rgFT
zU!6ezh^s)&NP~Ex`dS9vzrC!sqqszoI$eax6sxPq#Vk<^GN8UxE$N4Rnc5lv>?`Wt
zhalzZ4m$i-sBJ&OSfyH}hCr42$4rP<tJjW0Q;qsCg|e=yKR=6gx~87@1~k;FFD`=m
zI`y*;AYQLtjhCX;=DJ$*8Z_NdAE<_4gSy8R5{>GYABU!!>is-)-ckop^0rBxAwjEI
zt=xcCi~48!P)4h|b~{L$x>N<ZcJ+^RB)F|^`38&7p*CJX=N+}*F0?w;SHhwGt~%va
z7}KTR`z*k$z3P!&;OSHE4h2uYIxzxz2h{WX(Hc}QxDB3rYS-HkyszG82KJEJN=L5;
z>HzXBht>NWAU>k@@`2o_y6rWz#?%q?8XQ;eUxWpkP_K9zD>JE%eht%psFpkg%ar<b
zDLSXE>KFZh{YY)5sm-W&Q+8lhok%suwwj$37qHVPB@ndNOqkJf&;-!A$Wdb<U)o8t
z`7mbhtl|6yaTm>b7mT@T!Z!l*h^F@fh@0l19AoYpp#z{jG)t-S(o@qoiLs*^Yup3O
z!b@|;0u|nx<>aj#(*#kyf{&(qGpz8{6j0RJPZLe4=i{0kF_1r@+4vmf{WY&pZZSY}
z^l_jBYUUTh!XVAN$6&=tP0s+tPigw;s2Hp%y@6JU=CAkA3e`M(0w`gcXRWktg=?NW
z3Hb=kiO0|zsR>L5OqAvedo1Z`jhK!(XEfr|P#>)suSe^wCXB)h=QPn?XvJvO(!&v}
zxlUVfoF?>1ka&%V;ywwQtyGYasL7!F4@sJT_hKwr^W_~tr)ZuVApb8_qyHWAP1Afu
zcBgB$8-bmnY55Kk=QYdT2X>~Wn<{iJXcj&Lfs2~_ry!rD`IrxZY|Y{UEMAVLg>LNS
zYPQnNxl5X^kARY=v88iDzD7sY_5~V)8*D1n6qx~iS@TOb<==}mG9N5rv1To~M<tpU
zDLh!J+1ms8GR@DnXjN$N59{%$q2?agRT^iy0938Hw*;g{6Ll0Su4)#^!E#OW;z0=1
zYCbp)%sNdyMdIo;hbjJYU6cF_SZ-+gF2K+RjYdxQ{~9%EQ-HatsXT+;Tbc<9p*LyP
zP64!8Q~epH)}q--_upGJRnLL6X}C9FXuBqPGbVFe)B86-J2am-LB$=-sv5|3YF3e>
zdslOEHK4mR%ufN`tttKiay^<Ivyki6i0*?}`!s_;K)zoy8;Pk6X#OVObWo$9LcM#M
z&d(u#U&Eo$!;r?2f&~vWqjLZ=tl3Sw)`;c@Uto`F-09~vrZK$%xpB?U+hN6ohBW}_
zNzFP6wm;OoPb^cKmA+t^*363q$|I|0jSko|n(sGZy=FC*?}28k?W3TMo%Y%Jkhj-f
zqw~6h_H&BxI%*m8R&vsQPKO?6Z7>y9xM-9Af!VIwqnW@yq8%%TLN~390V~|KTMnY-
zq1|*C;-1=SDr7vWUGX@Gm)6=^4S8>E#!+ZGrhWf5)ca@?$<y@J7SUw<v@2-aI<EaC
z2rwtKCoe<2zxH1`P6lY-*$EP;{VWAzLE02LUY*n)u7mg~?Sd~b7Oah<)MSX3LA9Ns
z+FsgA!n8m4q7|-PW3_>b2(3HqnvvQ7`anpOHu6`H)7l=&VxH0Z(91YlJLg?UoYm$~
z70)^CFfBriHarmGvD%q-v{JQhD<P1k-R_2orfcW4Lem9p2PGvgYF)d*nWcU7D_AaR
zCn;K%r?uNf`S*P7)x%IxuH7C9y_H(0UErzG&QeyPT3buM?i%f4`ukkfW;Ox)n)css
zAW*CQh<xcf?H601zFzwmMbvI+<30yxgLW%j!EV%g(@XKDb{ka|+|s^xADB(rxCU^x
zXbS@9{Mo8a&Bn5|X<wnw8ntWf8X<pMyNa?3ceHH@km%Izrx@j3?Ux=v>(V;PAkeK%
zbAq8g+6r2{UTv~71p2k3bci0%awv8-sGUBAv3uJ6RL^l=+d+xdA#HXN#vW+T;4E#m
z8P;m)mo%dN?*ax#wXvts8q>b#1hjGO1l7$=XfH@$)1=mc4$2R;yH=t#t^Gv@>_^&d
zlwh6F9vlGYtTwG5D7Lx<a-i7h`rpHtgD$27W;^OOlS}KQTS~DvXWg?0K&&phur7ce
z(dj<IMBQ{RQOwX?mwNy$58aw75Ko;uIbcV1r}o2cFI@%&b&lx{Q;xt#H&6ggzPifo
z!1mM4rDXnb-G8@1PUsvzg-wAv*$dDVq`UPSj5(=Gp&#NY-DkTo7HrjdQkh|h?oB!q
zgzFNrF|`QY@M7>p>f9)Aaz^*j0$35P3tWt`vpP0?rz2K3QwD``y5D|+`gonJ7~)B~
z2ju7`>-x#7O3|$?$5^_qYz0V$E_Mto=XIMoXkFAzRslLoXO(>iqq22j_CUL&+d&C{
zJe}lyn4hondIXpP-G<XpSg0$Y6U}Aa1^Ng_iS8Oz1eWTYGtes2vHu@?)0rqoP_9d$
zn=lo+1p0zWwJw(hmKxn$a;2~8+9;xYO?QhNnOa?u^*1a{o$dm~ZExsW$eC@>eMn_P
zjk>4E6KT@@#0FZk?vvXvrbSmqB^>QK9S_Fb*7;MgphLHVGWB<KzIjm5saw7S6TPeJ
z4TAbX-KTNryr=stA1wEEtu&V*T_@GDKG6OA0zH4jy1OzoM|7E~kQmi1CD&(6m$(5i
z<GSG}uuSOQdK-Etbz_v)eyB6iW<90LptR?-&Vho~k95o@p<+h&;#!bd-H&$YwAJVR
zhK04$htfR)dwmO?HXQVQRH5pq-(^eZPbdA!Moh+8zm8IrF8Uu*F(+5O;t}*7(Qo}4
zV{UqLEN1Vnzeo<YhyJThsQ1(__W|}%J)2Z`>Hj{6P9Od2l<)M_7yg8npME!GzK`qw
z@c=oY-**dR{`!B@F&3b|xs|^E5~$zP4WokeAJVZfSRY&jOGEV5w?RVnyo;DcnEt&<
ztVOu~CCXVx=)cH-6_NUFF+hvbe?jGMr}Zzb1n3#PoXTLL^(!_({H)&L1wfzEbLk`$
zqrVpglvsT%y-efv8U_Tc3HtaD&_q2i8xl$Sc@%n2*1wqoo)rBQg;CS>zaIolhJLLW
zt@C;r!DQ;+XF<~ieF!=I7xh0=q9jW{@-{5Y)~o5@nWO*aEY>hre~^9`m-NFNpycTz
zL|CqT{d2EFLxEMlmLBRt{hDx)BK;(#pi1=}<gS<LmtF$Q6@BXofR^j8M?j)NFV04*
zQs0^YfhzsuSAkuv*L;q#8vWP`kgIxC1IRUf$~B1B>Q9glU8i48IqrJ>ubv>+^)}yN
z)f)9y-FaAZQ}0M;<6HVysRq7DpK%{5n)S=OU~rp$_W)Y$`tRsXds}az6HSNyTo~l<
z=p9C&zEi*OC6K%NpQ#R|OMj8vv2ML40s=kyE(+B4>hIjcGWY2hKLHK>`jIBE4CtBG
zWe^<HKfesUL;7|Fj2Y4A{{JkmPy82xV|q~$#>Vwqs~|C<m;DDrC-q;y3r!F8^S;N}
zl)j#J;%R*_)f+t0S8s);8U2ej=$zFL$*`36hQi$-4u%#V=yNn2r-BM6L-0~Me>xk|
zD0%B*c%7U>SA#VGphpa1athrHbKij#?uH^QKs^i@YtZsESPCKUZAhgT-!VgA6y$si
zuTbfRuc3-Q1>$FTjEWtP8<tY&JiyTKJoE+{5?Ww=kRjzOpqw-qAA1VV-zh_x3wnbM
z)ARs^8CFy1A>7bQ#e)%s0tyL78cyXyVU*!|C0eHqQO5y##*n~3E84JVDFn_M+CGH9
zIm6j7fW;X09LIcP4TtFdL#p9E<wVj9Q50=XHyosRe1;(wmlN>)LBnn*pk*5T!mt(>
z41bhB@S@>hDR{CBbqd&>ZFqkpNRA=;bC6ua>vRaXWSBmNR-S>~3(kB)CjAl$3<I_R
zD>SU8I}Vo($33CG$nZ1Wfi5<jr>(!l;7sw)Qp4YCpvYQgFp`&a#o$ldd$~cm4losl
zoZVopG~6G6V3nbg{>;^e#lHZw#;`pQV^<9kc_7ye<+L%@8t&YIT%Cb;3bU^_%;RCA
z*9{}pfWBdvRRFrd5dAU?Z8W?^LHe79T1p(;vKn-BouSE)%>Ylc;mr3CY%v_5eX`Y{
zeGEKp1||iX+6_T2&~)37OxLG642=|qxntN%-e9L;6{V2w8rCI3VV7ZQ3Z&bxn+idC
z49m*V>NT`cG^Wq+7<~!0A9I1gfWaC<A=W`dt^&<_hJUGE;l5!$y*h>rJE@-efg$K7
z$gp9W;>;rkdj$kW4Rfc^IcE5V0vY3mWU3LHFr=r0Od5=J;CyHZq&)T`!;5s>pD{So
z-M(4FPvofD8-G~=76;>#)_zb&W7!ahlX1KYJkCZJ+WcIMZ~g`}S7QQYQH~g&c?J`8
zGY)<RPIu!~CRjX-&#Z@lr}6C)j2$&@BnQmP_!;H8y^U*gVCXU9Cp#eEV|=?6>+5U$
znf4+-BXcLF>u;<nrub)oahW@e3N(JfhD4C@*A%dxG=3Eg6{n2Tbp0aOnEn(xLyV`t
z21}^1%m<xe#uq#w9&Y@EDv~0MQTs3!Y0P~URzw*!l*~A7d|r>SGsZV4sTXbhNe#>x
zqc;_!#u`7&qxzRPqYrKU@y5CDW1$j^M@PYvXng$@%p%FCp^w)k8=I-LF2$&~f+f|s
zf;@^eqqGiYryGa9K`X=fEnTEJZ#?}Z)MpyI#$eh7W8M<TT{Mci(V1m5KM&4qqc0UC
z<`~DHCI2ti*t#B*xn%r;-lloRn?o4PH!dv!DKP$c5~dXzS64#tvhl!XC@eB=p%;Cz
z@%~3pSYkXtd5==#s}x2lGiLk4`YXotFCboSeA*A{D~!1m53Dpkbq1{}<EK<hUTrkc
zk=$Bi40c2Fs_{$!1g{z2$pTufv8Wdc>x{QwghahD`4U*J8$Xx_y*G@{vq2h+^C>jc
zXtX1D`KIx^15kL&I7{_OO-B9W0Bbfbq(n)JaakrhTa7>70a%-{g-&(t#_uV}aNBC!
z@gx2+9Y%-OuwHkJQgTK+jkoE3cDM0WDgo{>z7Y)-y~e+(w!6>x;!9}t8*?cSH(;E;
z0P#WN&nd9*p3(df<n9}{Q$Bgf7((Z%2gW)#*gI^zAqDh^F^V>*QRAl+NgFd-m-+){
z+<1YmdrcVMy8)vnjjxr${D;Qlbj@?hxUn6rY2(CW(EG@^tsX2hMxS?qJ!`Dp3u0@E
zqhcI8)3^&JVQ(6ZMyG@6nGd1R(d6!qmXm3cYOb73VQIj0F?~k?d{@&x>kJn0h-sh$
z>fKChLIC4#T1lUC@h~kgVNRZ=;AH?kYHE5F@?Ithd0yV8u>F8JX8L>?CgWqeIRZ{!
zlQ{#Oex{zCXdO3gm;^at+WQpb{7p%#p&`J;ISXR~P09Ue1(|+$gU+8PO|7TVd&=}|
zGO&Y9{#2P1Vp3iP2{jFDhx#zn)0bdyxGC~ykO<S39gvSS$>&4hjLD9Ue9@+p^i-TR
ztxSX!=S+Loq7`F`5rQSw^zjuK6KA^eE;!>&$5x}2V0!jt`v04WCV3=SlT3fn=M$4n
z)3l+dm`qpDnQBU*T9Y)Biv*qNrswH1JsGCuTQGLslq<pPGfm3xVc`YSkCZ>SXj)Dy
zn`M&9U`4j+(|9P%F%?umF4yEtulq};&H0#ho@r(=<=^v7+7n<cFdd+DdZ9^`2<*$I
z>QS&3nR4>bS!{ZaB1|Qw%^`p(HPx?$!ZK411)8pyqA5{QZW@^fO%<j@a{4PxPbe`~
zWm?6DK((odA{RBLsKr3JYI<0X)-}`aPodUYYx<HhvvsBbF?#DwvCn{9H?5@1!41>f
z2f@=|x<waR8%>|?MeC;N{vgOLQxg4jnoRSku(#P1wgPL>V(QKVX*F5sPDPt(9c>2f
zrnB@7kUOTw>5bQEYVv}HyQZLSsO_?v3aOf=+r*?#KJ=Jg^TT9%O=a7`+Gh&81=4RS
zet;zzFg1Pwn+8qu$uquZdXb7X?wj5tZ)3>x)i|d1z~oN3`C(HPWz0uR9CCd|O(&>W
zam@5F?GWRpS8PEhOqHKN-=xVZ-U9m2<nu0IrcB#i(V8}ysM7n9>B@Y-%$Q23W^2}T
zgHBnt=2!_-*qOKYL%qHEb*lJuFiXFHoTHib8i<p5?;&tHoByCNnTz@R&w%1;uBO29
z5p!KQ#@x)2$06r#UScH=*TX!A)O(u!u0#H)dD{<=@G=`OW4_+zx&J}^F|#fOHu;#n
z=nd~{4k`hQpZSSJKs#;@comvXn1w$8%-_6%uKER-om@Zy&HLYjT#z}H{!Ay$K5GGX
z%3MV|Q?U8>8&o0?Vjg%2prPh;suhbcFKGr$r1@JiILh2hKg4MB7CM=qHE*Xf-*e^<
zl(09>{M=G3aJ>0lyhv;k%#YC?cHZ3e4>V<(-=tLP1#{6JD7<JMqMGh3bI(%%%QpW<
zPEwBf5{u5Cx#sClAb-i+)d-Sj-j1?Nn|$-sJZLH~hpY!oq4`oVG+j22)5ch2Ua}sV
zip@FX2$h(#{(xzv<~8YHDKi_N1j`k3fd(k$=BFs!RbkE}flBk68=<$#EHr_o+FbUC
zzCTf8er*8+ubSsjKH!=;eh}u@nwONpm^!nBN^I)Q(q{p4-Q1mo)(vwd)dDq`L+3$n
zqxl0Z=5!N(CV<{D|4Cy_<`<VhpxK;3S9V&=TaJUYn)6n`iZ=80O;FTsb|Od9dfTjX
zfMAC?obn!b%-85sF`Z^Fx{7(%EUgAwmw8td#=6aKgaf9>yyggCdd(v}P~T^+4@axt
z9Q6v8Yrrg^1lpkaAAgA7Gk?(oP4~^pDzt{o>nRfV!2INQ;2bvZr{n90)f^WJ>{0Vm
zV<2PZO?2CO+<YqrnkLLAm}pI!i>ci2p*i0k#!Q)`sE}*M{0$wSXU*#!fo*Fkro*M3
zWq%76*xvF|5HvYhEL7$1XtAFKn3IM74rb<T`Ta*=x>#PNo!Hf4eI*HlM=WXdI&`zN
zCj-shQr`oG9+ud2jCopaP|oY9MM{p4m&J`v58jqH-@z=7S^lP2y^rM?Pqch34_07F
z{45ES9zJfVeF<_WEaBT>g})`@4{!!q-lI3iNz1({K%cVwVx@Y6V9VQ7xe{XejOwF8
zEgpx!6K3&OfG6A%d=H=zmahmV(!!#Mbd=@uXc&6hvbhoDjOCvIOeWeg_zB2a%i+@y
zIA{5(8DKFMBLy&GEeGgPiL=~z4=C}LDyk1murw!IF_>sMCx!V*maiF*NVa@-9<3D1
zi;ifeT5JnoOqwO(c}zRq@>LC58J55ILhii9>3NV$3w#DVYL<Bvu(@b)-vW|l>AMe-
zZFyV?3v(>%9)tQ^%k&hizhp6&qchL)UM|Hy^DTjFU>8_oDOpx%@%j^>mo4Vam_?E0
ziG08mTmF3&dP^+7+Q9r$i>eT<GRrJ|Me&Lym6E6BmX}umyTUS108Nz^DZOi|EPW_f
zvZ=OQvV&ZWrG<wDx@z&YV1m~y6;DzAz1Fhtd&t*W3QSN~Z^@t>{dG%&7-%;v_G{4D
zVA)82pGHfc17L1il#~*^WzqCOuE|nEubgJfHzm;2V)^7O1llc&9KdqhvMvq^J1lz|
zFta<B`{ep`T0CoD+Fgrf7sjkz7F(*Q@3#2pA>RY_K<l-b*FnC|a-WVX{g$Lz*fe0t
zPlgqPmd%uAx@Vb3k>UH6pPqpDkmbe&j6JaYN0l<emT#$~Zp3mj7GR^6Umt_QF-!U;
zka0`j5-56T8M8oq%4)GA_h{OZM;WO{miuntnX$y)gZf!ZM;I2$cJbqMh0Shpdl*#M
zFP{4W1RWM%T?zrm#dVLtG^fSg<IwB8*xwFdE{i{*pNH#WZ@Lt5WbsE7QgT~dL%{;~
z#eVz1;_*L@t~xNws*7WQ5{iN-*qBHtyxrY7Ma2XJ1Ld<pP|<f|V+D)_Fj%l+W8Dob
zS&t>#U|rNUmJF8c`yKh`aPG-_-{-k;&biMR=b~ZZD8r`w0@^$nU(o^X7~>OC<H`7h
z0+?Qmu^KdbGY+WXun%J)ZJ&=b<}U<xg2ATj_DMz#6;}8%vS=<l#R#QD$!W%88`0>;
zSVIMv{)`45umHwEn!ExTdufq4!}!7(Ac(=WQBpFP(M5Ui5XPod=niE})uAzrA^HIl
zXBmemzZ=eA(Ka-K@y9E0{~Y6OdgCG)p;UVj#aK`Y^U;iFF9XCdp8XDkAIqpx1B+wa
zUk=sr43AETCosOE4SFJDBVE8tVz|cA`<Kl4Z~_CB!Wf`^Mk>SY84%MLZ&L6qow0~A
zB^ivt3CL$MHc>!5i}3*^O0pSB1LV##Rz3wsFEEyu!r(=Q$_um{#&aHM%xAn!=lTMM
z<r83qjGId#eu+`A2rNa6W$l#zD`qs%-QW^N7sUrk88>R6w2X1Y7haSzj=KR=Fm6y?
zMkS+?7S+oPg#%cs7(2wksu^K43)C={NMWLuv6^b}>KMbcm8fT2qV@U;W01104UFYU
zU}<C==mBVA1iVN4&#R0dD58Chp{07RX2u;hBw84AJK#(!<4;HEZe#4q2CbbjM%8Q`
zjEjlT-N|sFm{J!b{~-u;Gge)Ohdqouin#PLo~0w#b;dJC0d6o3wL$JC!;ucpw-{g0
zk?A%gm)2`rA7k@cc+<~#jH>(x7@f4ey2E&_8(@&(ycZHf3?p4C9A?B(4bli>*%~yC
zGQP4v%@|{e0^lxV?<!atXXwsD?jFNsKEQp3C(Wx9jCUv@Jjs})#bt_-I*Tq%GXxa%
zov|^Dlq#HMY#9OZ0i(wPHFJ#NM<8L(+(W;w1M?nDTL+oxIgoH<K1vZWC+7OYaQhJR
z$44OG$_!(m(TzFt0a)CbrIdg>%)CV@(Id>BF0dSBhVBC9!K|R-g=5US<?zsxX$z#{
zG%se15E9<ZOH?ZA!@PP4gLs_TLlM9eOh*gANv1Ew4t$x9_XC__7W6~lG*e9zg&(tz
zhTEUHnr4^)rkg*oKxWBes6NAd?LGJu#5^Q`mSAS)HVA|;z3pHql=+dZ8cu~Vo9Kjl
zmig{az`~iq^ms)uH<d#09CK+KXpu}dWhkSVT1u2eGe!BJ#V|!wix<mWM%N|dnD3@w
zDC3!Rj$lb(M&5v2B6HW%(3!;SrjuSWGoJFgDNN-o<Wia0@7myS8k0k%AL-0cy5o?+
zOl*dynapl-Ka07JzUPq5{CN_z^UP0Z*}uSaErt6RnTLHr%VFl+gtlC!k&X~~%s0f4
z%V#!j1WN%knyz;iGAF4F<`VP3Y6uiDMSAq5n3*#~-=8R93hmIDQf6BgB+8h{N5E6g
zJTf0@Dwuh(P+H0CWB{vX9$yE4YnY}~u+%d9D5F%zJo^+_>X~kbVB!kX^LcPKFugv5
zvPNbJ)%i6sSJ3KxmH8^|46ZRdh_jg))kF24EzDTD-`UDMxCF#Dre7MgwKG|iIqzVu
z`5J0EnG+O)?qafOO6z8xei(h~VOEu3fP0zeJE8kJ(`7j<-C)i*L;NPwgYq=Dm<G!9
z-)6o=5z9X2<>T<TpD8~8fdS^_^T2F(nE#`s@gOsVf|NtdY!O<AnfF+bA7NgmxX&mv
zpJIMv%#Ud*yvr=5c<ngzK{Q;u$8?~n@IF(v9xM~g54|Bb$t=+Tn_@<H!O}D{=1G{J
zVKzJofmx=2b_NfaUn~YTXJcN+EHvMql`sS~4y^V619p&ALC=RHE3*T@iM8P;7(B#U
zL4)ti`pO6|Tv&xSAmGYc+Yg!>tAZ*F+*$8aQOsf1UOCJkVNJw<^C&BtHp3pQ9uF8i
z#>)O0Iz3sfHUKY{?Ymh>c(XoU3gE-~U>c+6&kCfNMF6Wy3i&|RzyK_rVeRV2SOl@=
z)0gFfS@vte62gl58~qJs`BK_5jJ3fFw6m<$S3wJBeRdkONS57vh)1zL=71%dRpJS|
zF|6e`!5Pb%vi$}a$GT0?)Oc3bR(P7g64rw!kv01W98O}rLZ^mgmZu0xQ&<|>Zltn~
z1w&~X%S>C`bk+enCugu!kuZ_T%AycY7OVFVuxwU6#Rbl@;xB>o0&8a|uw2&80f0Of
z`yC2M<g=b-0u-={yZ{PWFH<b}66;gCHd4eo{~FX3vw|u5RKhY-_NJ8e=2A44vD}}=
zuT{=^hSD_^tS{;4Q_0$}6|~DNZV?2kSe!WgXw|HnaiG<(wo#O=mK90`g>|eE4&6Vh
zXU)jL)5tnc8|Eff#HZl7%GxW2#5L9}1WD#Mvy!PyqJ@=3L9ABR9|C|j*7-Tm+F7!n
zG0q*Vb@YmMvR1Gm*Twp+1)!Vt<xVK;VV#wLvzPVf0d(m)Yitvg-C(Uj(91UeChKEA
z*uBM?pl#i4)~#p3+Q;&yI+T9aq9|YkEKiCO++nfSU}OeaIH%%OVJ)W;#9>y{L(n$D
z+8PIzQC81CU>Rfm_8pwL%gUv~h;i06I{n^bRWFA#_gOx#!iy=E{YA*xrddJ0fHSQ6
zR#=*4)y4sPz!FeKc8(>ZM2!Rc?LuG&*?Izw?9EiK>coDXe)L0Zw+`5KW`{Hab77yS
zTbHiv&TJ@iW4}e^B<^e>o$C*?Z&6zL2zxh`Y93`D*$ziNZ0yD~pvTy0nUL^g%jkN5
z7kekgl)Tw_v{UwBKcE=ParVQMH#xz6=MoxEvVWX`U0?RA6wW-w{)plcr`bd9kn>}=
zv(V_zzEcjJ0qjp_pfiyDWg85gVgLCOv;?tN7Xu4s+uoq6-4J$HEcz76zD3V-82j|^
zz|OMQ(Ka@m?Lf6&5$vQTP<oDC?T#UhWQ%AM5yM_drJAwqGlei8$6kLMj>fb1Q4lGC
zeaHoJiR|)Ku$06Orh`y2TTap26!zovJf*T<w9z>(js0Q_?54AS>VY#E?0?cBn8_B?
zLzBhcv<IyD>}D#6Dqwfh%v8vJnU=^)>>;|SQN&(n4}-;Q#z}~mviF+N-!ir{l_i(6
zhm8OgY>OvYD%p8ofu)L_O$m!?_Iv+Q{H2DSl8@F}_E8?R)v-ULpW+I;?=WZ$>_2Go
zY-Bs00@lR#_%HOpj-==D8vBE55NKu#vcS^9_N8~bmHkjH%(t;Q0(7FCUAi82JJ=<W
z=wK&%j?MsGY+w2)MK}AIX3D?!u!mlQd@p;p4oa`H-=qV=4faw>1Kwme(q8Wtd%hjO
zZT9pgDD7ig{sQP{FJA(=0d_0R0(aOyQ$fZcTlys$huF)bfDN;ylK>;^Jc?_Nvad*B
zevEyn9zNY=e+0K}^T*k23L)HM8)%zzpFKfy(G)v@F4s=8SJGj0hHdDD`B`=YRS7>}
z3!en%9Q$P|_IKcHe-VubIS1+N;K(`O1K`9dd<nEeoIjq0G8fK9Dj;#?w7m-RZk%P5
z5_RXSy$#HEn6sS{JV!Yn{a5qP+0zPb$2c<|!=NW8dJsHb949N3dUJN&grE=SLLX?y
zIl|=tCpf?FN7qhr%+JAuFNdEAmQ$QUI`*FCJd%k<KTZp6!u>frDKs0vG4*1A0y%TE
zbvk3?*wb4X#Oa`gAei&-58w&m1l@;Ep&T8p@L`-a^yP=M9G4;(4Cm|)g~13;R4u?c
zPLUQYk(~E8!C(}}kv<z0&B=2Gh~X?=0T9cH48w09$BENIAf98t10E)DrWXTC<k%KV
zVLpYkJP@p@oIicxa2h9yf}`o2J!{~12Iugbkk8~4QXV~<GrSYndCtQ304{Kb7J>63
zr-f=<aySjo!I?ZxR4e52Iah+9vw-7B_vi{aSr^d3OPs(a(26;?j-yK@9D7>=yeZ}U
zyazmG9M!WRmUB$k!CJvtN7=PXj+|!H%ba@=V5#D~=mb#BX`h7qHJs+}V4{{||KFL1
z^G5*W>N#ysK=&1niFQH_oQOMUY~&OLqGwH<=U;)qRgN<S+pcj!KDB|Tne!+;3N0KR
zg-lvGi~#6v<9yi%OYNMklt}B~ETt!~le31B8eN>mUx0OUas%Lf59i->i1%_lufoym
zoFDgMoNjQkse1e-r-r`XeT$RC0l3Zii-*Pm&cpN^-{CB~K=0om=ZS|QKg8);0Hwp6
z@7924gi}ZdnlVoF3lO}^Ira`3$2t2~0K3PTqOW$`=aj_4(j;e!l4MhyV@m+0Ip0$J
zbB42xDiLQnG8VubXZbqF*>j(FfL#af>;_;5x!*?8`{&5@`58TQ;s(*q<PbOU1b{O)
zcp0?0a1*G`$d#K}kFjv$Hr@s1&egO4JIvknUyT@-MbG0=ZZ<{2J-Brf=*ux~&`LCV
za`&WQNW8cv`YQw8+->`y+J{>Z4BBySBjpclC%BJ&h}M%_Zwie2a)%y3%_*+uSCBZ(
z-7JH{e%xOsVAr2}>c2{UZY@=;1ahnCG<b$<dKN!y5ZC^5$OUsF=u37X+%?zXMJP9d
zVuj({3Azy$!A+w>(mC#lHeiw5KiCkDvT@g3fE&@=Q3?#iaND$yh~v(qi%ap`Uy{(6
zz-`Wj7l~XRCDM|(36xq%<{BuBn!+8R2yYs<hYx{tZVVkUGq@?4_zg0-vx5Lx+=v8N
z%H~c{{PH|EsTi(Z;KtAtdXZ}jJq|R7d#4p>F84bsoXO`FUxrTw+!q6Y6><gJ04{Mq
z%Y)q_Zthi>DCT<5<59vLdkkKbaijRqUCtd11WN_?1)6;-x#iD7=Vk6ve^{vEZlY3#
zYOa+$tmW>dU#pJWVxvna^;}~qB(8ABdO>X9{?H0yBiAb#f=%4hzXDw2Rv!jv<}Re$
zNG;qqXbNxTcGSXd8+W(}jh)=}92o54ZgqvSZtnJ{F)}^eO}~S)m%IKLI&qzwO_Tf$
zZV#QxZgKhH6o0wR{f5q+ecad6!PC!O{spuRaQ|wBGk3VoR6jGwy+C_`VXn_2G>&kW
zUWePG+(%x3z!<lls=MxTOX+hE<J^DUq5B^9+F@w9&wV8V<|nvmUjm!tI(WmUDQ@ZS
z5SZbfT1Vesn&n3O!{G<q@=o+{jyv){n6T#+Jc33Co`C{^2YLG?FzCel=6z^8#1qnY
z2Ap}@DLUc8+f4xhSKh!b=yu~d#z4-U*RmUOM|cUZ06WUdrkZ~b-gG}2kMZ84k~&Y`
z0wvYIc<~-S06}lwQrZO{=gocz;tAdh`yp|X_b(lme0kEh0Z#EYZ$K~nc^*{P7{FUk
zg}s5iFEfCh;T`S=7Q{<0g7?8Z)=~^t2ydbuZin&m`M}Qd-q;D2aNgo5G)D03pM#w3
z9It_b^^rU+ZB?Uqk!xT#hWDihcw%|qTtZ_UZ+jdX<9V}mzE9u{t^k(Elbi)Di8oHC
z!DQYO^m&C8o{nDMRNl+)<EKdDInrB^!TaqYc%RAJP0^z)Ucp1?L^iL54jbofyw^4O
zxi0YH4np@uUNGIe$mOk~b66hlV>wv!c?ya?74UKbpr(-b?HXX0cv_mei+G78042Pr
zGBlR*8Ypa3#+#tSPB|}ZKWG)a1GG=5<n0%M<ub3z1)!RD^aN-%JR6s`!L__y6ppFm
zSqsow&-45rhNh7>q(%>$c-61MwX3|SNw8ew-J=V;%{-4oXl&sP(n+zE_oN#@J1;yN
zpo8}s?K(Pnp`Gxzi}%_`FyGC4o0g0o-UcbedwIJ?LA$}5w9)H-lUGF___)Oj9>ec+
zo9Fp3B>H%}I$^M%_s{<T26)+H5WK^4dLF|y$g`*9_z<t{DJUK0jZ>aylvhiW$QaKd
z2P}7ab`J1joagreRNv!G%|gq4o(B`O37!ufa;A9r``hT~G>`o#SZ8>?yTLlk+xjVV
zKj7KcgEq$t-iTksp1+x{%pT;w+6{jl`4d!@<-~u6Hd}}Iq4dK#^Dom(?7|-%ft)M<
z6)rg4`3|c=JIuF#6&8;0zoHueNBJ8<z~aFd%uxKri+_|Zw0ZMCdmKDIe4n2oah$*7
zF*tmJzjz@WKFJ@a`a)m6OC3Bs&1Yu=^WzI?vi9eXm!sPOeB)v?2J-zlkUPWQOJTAg
z{?ZZ{4B_`ssyvkc`aWP`{E(;M+F3sTXIlTl`9BY%HG+TlBsz1B-$1*xNIp9rAc}tv
zHEQ#t`G+ZM6vO{#1z6(vjP)3xczy+aLLq_wWj6dx<iEKMAc_CaF3^(s0dsIPg&$jp
zj;8T9R{^B+&z^_B8T>KI;bii=K7-q~EdD<aq4fga{#giK<gcP<Hiw@b2#H+&rZWI}
z{8~B^=kxWxFkis;qPqM`{JM6?7x7am(^1TSJ00dr_+F84yOi(w70j3MnY7I*=l}Zv
zoR$1)s#>_r*S-iXRs80^fmPf1%Vp4A!~gMdwAS*6ene{>e^L)G>iN!;zrVs4P<*?A
ze}}#$(8!ORhWl6f{j?Lh#?RRR^UZuWD;it)oxea?EB`(EU|Ji0@(7%1=YO^fv`+pA
zm1B1CL#d>-n;$p{Lp^-k6E8t`FMlspsNdu#ehN=-@eli>@isrJ4Dx;aRdrzP=Wn4v
z#sL58(*Sq)F%%ac;#(^rFwEbw9$<u@-U;2K{MUYgvN8V0&q2#wKATcV<NOjzCf?`I
z4+rN2zq1NjCi!``XrNPkeK<yMn*TCIuV(lnItb134HWWtz|W+t-W-234Y$3(mmW(8
z!G{VAm!sf&st$1y9GZo|A;FVsh&u~LXu)(5aOnKzDsW8zi<@A4Hv|p~{^Wz@h@k5n
zlpPi9c$dz99)kDjsCY~u{RKSUf|zJvK7xEI{XZ`Fkn-;*1o_Kg;-uiCkI@-l!Tu-E
znNxz>L$Ks02&RH4f5BsYkP8shFM~j!;5(YE&j|SS_(g&Qt7)?pELcy|O{hRc8?i9K
zg&F$({8_<b3eSfN%AbUZ2m#|w$e$DRUWBDc!Ft+@M+st^AQ3Ha3Iu12py_GQVg-Lt
zkT71bhl<G)1n<+eoJ7GpR&XW>YG?zPEQq9f^Av$K9p+O7-`Yc2y5Ns*FeDj*1-%r1
z$rQZv6(q6*8mjBh7L?F5eNpfYMMrW3>ngySD=2#g{mm0h(Kl!F1*a)1ULe@=Ba{{j
z{@H*&T@s|#z>6Zm$8l&Z5iD5@mQukQsw^lIJbDstmkZoBf~7(*B7o}4f?<l_*{TGt
zb|6*@Z1noq3ZiM*uM-^5Vl3(fophYLBFLl}wLuWM5ui~Z9)j*B!6`aYUlY7S`;2Bm
z!WHOl5iFPofmVUI8(P`~N#hV`7kr}utwV5wPGwz!eUCzQw?IdCr+aLIq%>&j70h1%
z!RvxC3bx-6M7|3bZwr2Gh5LPiU$p@J0`GPR4hUYN-TNJZf?k|K!L^UTIV8A!7utpe
z!xVcP5&ZoTz?dM8!k~8rp2hHRT)?ML);+<+_t1D>u%ZB3CIz+&vp}Z=b5?+90b>ZQ
zvw|eLWbi<+ksic3ft)_YYA=-T#Sh~kd^-VZ4hpx90CN;R!hr5WLS892orOE8w8uqw
zdl3X&g-fW&#7$UP3}x=Z6CN0Z!@@zD!H)_<)Zp|Gmf9jfJSO~(R)0^SiY9F@;m7kq
z^cFfk4>c!*Vh3O+g?o0OqrO7F-+`SHrhg7_T3A3Ke?Q@tWMKZnb5>vhLVx<eK%mgW
z7ve#}ZVz}7ENoZ}EJQd%ag0#mKQu3g3BM_&{b#t)pTfowLig|B#W~?TN}EOrJ652F
z(ZUawK|V&<cm#gO3U|;ZEl&6(1+C+S?m~zs2qVN$nk4M~6IzmmztQ`XB0NbKI#Y!U
z=uJ%%zVQS+Oc%cQJsLBF^~rcHvV_~7`0x9J!iQ5Ke_pt!1$Hk8!)e*SD148H#vEY>
zr2+GWXGKs`AY9%A`9k4~R2zCp_zJyFMM7gfK(X-PeE3@;?4dk(sc=~YSjvPeH$l8y
z_~~wd3gJ7Wpj8U_m(Zol!W>jt*ydLW6CyAe)xtu5@YD#;QaYhl_~CySt%TPNaHd{3
z?^8%z5#EmiXb=vTLCsa6h|Z1Igv^UD-z@z5Cvdh1-=-SeR-ri*=G%lDs6L`y`1w3w
z9YPmcsyc-)zW}UDc!8o_wr=5jl)mf{rb=PAS9pL*&8`dopkVF|;bkfzzA4l*VCj}{
z`hOUb+rkYOA=oE;KpE(M;ib(G9}xP`>o6oNSO+hLg`b=OHX?*MtOvr?t@zKF@OgWH
zyTaA)!os+)YaMjnvk71R14{1;S+wJv5PI7~eo{De5KqgL@E5vDJuP&k0+bnHTo#;}
z6(*a&`9K))7qB_u?w_E>UKG6!N*zR-_QLK#(Wyybjw0C((40lvX}9AdlC6QiuA)jA
z#N9*(k3qG&$d;l6JS_T-_UlJP3(4S75vLBoL-h5VFmX(jN>8V!sCO2P-lDk&aK=Z(
zr!4Vt(XaO)cS5v(D=eK9b=ShKuPDX~;FQRjVvVOoWwhJz6E!-+3x82|AZP)i-&X>h
z5w+W>{4_{(M+p!tnnyvb5RsnFVWA=&)xU&^K5RhaS<$0Z4i+xj@+F*!5QVRT{5jFh
zZqOn{Q(pr_i()^67crtmw4aI<HC%yfaiaG(gEL-aw*VkP6rTw%5=E(Ma3+abkJ!+|
zWYO_Hw5EtQ(3gNxMd|c-Wr&(-4$TyO`7&6tM5lMcnQT$@G`f9W)I${{7eo&hpz)&U
z0o9o0h+cjZAXjvOf_-_SH^h+37wwq^XQAk+eQ^7dsN8_YB9V;}cg3RcBmd?9L`Mc8
zQ7RfnmDl_-QQjVOv|RKpRlin<yr|HiQnV`-w9BFpSIAe3CZ^D}8qx4CXsi{z^9p>b
z6P>GqT)oI&2!mHde^BXhgJ^y_1R6z=l>KZH$=jh5-+$f?mTMvd&NImWiBjl0o~@!6
zZh*B-w2Pj=cF~Wez&b?#{eiYl(L4bJyF|;3;OrJn{sy}}qB<(s>J{yvCGxr`h(fcs
zMEQmI?QV<wX-D5D3Zm>*zo>>1?*pPgR|4D-r4Pg3LD7<5A!i#BJr)ItVNoANs76E|
zQUYOARM`a9yP_|j2hX@@eKj1uC$gt2p!Y@kR4APgeR&wpOp5B%08^qkclbLkTKo)@
z&4?P3z%nZ;y9(L^(MQ_>?8UWILFFLc_B}WcikH6(osKqf3>8#4iGQY;;URIQKY+8?
zw*i)1#Jj0r$5re^2R}FQdmEwKUHo_|SdNHCWoSGq-c|}r9^%beXgns~nFs+-aTq<1
zUgDkfrhALeB%^0O;+y}SE5!L~2%HfAM%l5GV%x$EP;**5=MB_P{P#li*I&Gs^1}h*
zc1j=wip7+PIwSU34!?uMd*~Z2!Q!qYm<SQO(|i*umQX?}O#IdiIK#zVbd-(|mv08=
zIq{w<$VG~!pTk0w_+iRhM2np$b`~Q}vyH)<SaIe&fH?6lUqLWlyzN;CCW!w!2A(8w
zXDzT~@rQGePZ9r2i(9JrM}OE&6W^dhl5}xL5m++BUoC|BOmVRi-Oduf6$_o&;t#26
z_Plsr7g#Qe*O?%mBaTmkp<MCZ8#cf^vAP-{UtHq=P#`X&2!5e>`Wj4J67Tc^C=z%6
z3c+G=15E}c;^#!rT`p$Q?z=)Pya9nq@iscxUlw1Y*S|{aL2FdCxbZhQQzL$i3W;mQ
z3u2+APHdsHW4(BVn(D8wh~w{owNd;T6+$+NKjeXURV+?{?rY*gT2`9Ht2)5aB0lQ}
z&?<iXLkww~c!-W;?c%h5A<!XKu17~Z#SJN7=@!4<3eY2-*9m8O#oNn4yDl~*Lhgom
zoOTU2#a(yk@BiHr-=eVbZSk=kVC@sHr1I5%aq1i-2E>*F0E6P$jc6Pa&v9UBSp1eB
zdNCq?gU)fI;v`3aG4ZcoK<QnvG#5UNiyylQ&U<3p7ZATMPIiUBgxE;IwrTNxI=ak=
z|E6EWHY;9BQT7Mox2}U{PV5^5U@tlO4GcO+UKj-JpoB+X<8_qy*+bq*vXHg}ha?|=
ziXnB8#Ek>EN)jm3?<RSV4!Z7=pPj&YSQ51s&K!}nQMUJ}r1MAU^pH#n(a&R&k0_q*
zX_LHj8M?hBpHLXaN8(Wep5v09%`kC7@=YcLPfBtwqtRC)F~h_uiIi@_oR;h*gMN~_
z7|8icRt`XEfJE~(lm<%112Gmsl7Mh{5iC(qSx1PZP7W+o@_r()FiAI+<ein+cE`d*
zxI{#y{}GapXbwClNh?5~A|)vlkB^cVX~~L}WKvu_PGV2T{CLS1|DdA@k~BK=Buaju
zt!9$sAv&}tOP15LlOnlEbAGDiOeC;0$xjWy(j{KC5Xh7yehu*~$zQfgz-)<_cIf9N
zWeUh&kSJ(1y(rmH1G_nrb~$Ldl66M`@+8Jr;99<9A;kj=B#Y?Gb4l_YWekcWUR0i6
zEIG9bphR++Qj4XM6SVA?Ngm`wyj-%B&h-_N&~E`MC3Zj1{`0cr%5&&bm1Ic;%-2W|
zJ;J*pvC2TJleFJLW4&bIefV@m@>Lp?Hb@L=fJVtv7N}{GJm~`6S0(&lVAmua9dM>u
zQmleNn?y?2Xxk;#v>WY^9RD7wyCqlXf`5<X(KqP*>y^wMz#t4rzB~?tcO*OLbTueh
za}jojBz3(2!;+%S03#9!?Tbbw?Qt+MCONYmoOdN%CiHMz(&m6p+>@O72iSdy<T<cR
zNdBgtO-hzhtYb>@8GUwYS|U4w#u>@O^XU9HE7?gY$_J8{cLK~wCSHOw_R<?aL&8CN
z?kBJwl<q4>*BqtK>_elI^yYKu?;)v<vU1MSH^u0Ti}ag6V9-_SPL-x^Ql<#NUFyh#
z++nH5>*)3o={72JKPr9f1hjZat(0iA9g}Klg7cJy)2HaXq<!bm>MafP2j(Na_7P~u
zrCX^I@r2an1<+1Pqqku2eWj%dP;*Lpl(N02rI+{seo|NZnf;}GG!+I&FJwSVpmdhz
zurty&Dr*dqvS?)wmL}c>XNXODt{knQ(hS-uhe<7Kq4caYk1h~}ORGa6A0h4d7Odx_
zCnvxXDLuUkLlPzZ;~ju#=^YBF$4F!C!4fN7?u-7$NsBr$GVxM;-5T$R)SuSPMCroU
z(3m8RT@QQ7(sU6xQ>3<MXx2-WUOoe-(xj`Zz>_Y$K!ubU(ywUqk}2I!Wd~W(ziFSJ
zE$!M3f%DRUU(lE%UCo1|xzccF$mK~F(`GAQ`cyo`3#2Pjz)~oc8$r7yRZ#^<ku>fS
zXvNZmci~fsbft}Uex*{=U05oU4pZG+xip1J5-Oy@^srS*pQaG{WvQ4d%&Vkzze1o|
z`jiVmjkJtTinY>WdjIOA2V`ihmo5m0?km!_DM8a9edsHA(I`z=0P!Yi2$j-am7b1A
z<29+hhT@;i(#S5TX_4-tWOJ+Z5?zRClg|GHO53H*RE^ysbrZsiPH;j^m-K^fnCO;v
zQarIoT1)}CUg?Gm2wa!e(c^JLx?Km_O=)NZuv^kC-$Ki6=?GO~^hsCJdfhK|?xXYH
zfV74RU+zdlbx<=Xy+Ci{kd#CDsbT4Bx$tR3%IbmOsB~r$*qHPzWvA~-x0ZorT$<Se
zyZ59^{(^`1rR$o(G9mq*Vil9pFb!Cyq*~fiPfNQOqT4gl`4n=PmEJu!5APrTL?#n1
z&Pg9y0j2h`f5Rc+Ap6?~JO^c`UV*2Mvb|J)?Ib(08cGkzR1`aKmUaGwMi<%Z&T!3D
z*1rOno9wlCVD7RlRONVBw#))>M8=tc`J*y7PdMr+bG;4=Ub6Qe1*gqhmPuD&d}QZp
zVClGQ*)xzhA@kFNcv4p64MAVozE^;ql5P60$VApfYr3Dzn~ER&Wm4MY1<0zoa4k@_
zi{AS)vZV9S86*=^WlykdinenhvWu(H`%qcyb<o0O2PrIn)+QT`2T!<cmLiA|vXUJD
z=Vaz3cmyJ4E0)63C|L=GGoxkZWpF=6CbNJREBki|1|d$y^8ib{Oq&ZVLAK^2h$qTy
zRL+$ovn_<`WZAK4G^WT#egT#$>!<KQnry>Su%ydujkF)kkd2d5nKCOyakFHSGvLXV
zJ@gc4=Vh%_1av`mX*s|}+0=hKIGMvJuw2<un)M1~Rc9ekDBDCgJTA%B>M$}zva3`u
zS}c412dFNQeL!<|sq9lKTq%>iO)G4<>@yps&MIWeHV9VAx+x5ES=Ji_)+*V?s~FO1
z8RJ7V*2q459NKDS!z&?wMK(nXP=l<Va!8G`2?-o+lDW|wcvW_RqVv~e!4!IEmKo^G
z(jt4j8d_RqLCAT{Z<8IS8l-mF7aW?QI%M<kZ+@rD`~`TrWT{ku(k(+u1uvJZmLg2O
zvfiy2_3N_sKf!WC_A(u?Z_0wU0o;=9c@xgumer!3a(<ue3rhd@%f={)IUqY@f%qNS
z*rRZCP?r4>><-C%Dfcui^O4d0qY>FxbZ>D~CZ^wDOm>cfNq1$xQgVG<Hbs9*;GWE$
z%31EqlG*TSLKZ0nHYqzOgPJK>(g1$nY1tbTa-5Onc*4<H*`s;r=mXh_Prx!KOZ0|o
z_VUYrLbZeZOg}ge$|qLS{aZ&lo3>|8az2*B`G@5G^q4ry7p%mPy2#xrZR0Bc;aeDV
zlW%wn{dJfB{0F=^EdTg7cz8tKK)Z&c@)~b+%|pI?3B-@dzoLRDPkEsQz)ODkB52<7
zrZ8~&$PIcZJ1(DH0M~3M<O?Vea#CLGfmUC+7p-`w<mt4_IxQD9!jhl-+OJ^sm#=*S
z<^$yUKL7;EHw}U1jQrCMC=HT-{wgd5%Xd@)gvj^PRw7iMz6l<N$v^)Z;t_H#O$O)W
zHz;2cDc?aaK$K1H6N!#S%S|r<jgjX}!I@aO8<jxC$)l;-H(qWj1xtebY9SgE<@!&6
zCCSgf0j0_E{qI9AMSfEVELHxo7j&n|g%k@;m-A@u&5$!)VK-CWNm+p`dBtN8$d*4w
zUkp4iw_T%D-vxONmG@tix6y~ha^(A#f;CtEq7qo1oJmp5eED4$bhJSJgdaem{O*3}
zz9f$hgtj6%n_iq^dG=ozk`j6H=b)9!Z%zR#lRIyNg>w0}m!Pad{sk2xSIWQ419n+H
zYa4~`D*2x@&eihQDdt`yze0QBTKP0Z7whD2(gm%0dA1uoyduwh1C|=(x&MQStMarm
zh+mWEQ7LY-eAN-iwa7R804=TZ$y>10CcjBjO1r$I5G);XDXq7iat4*FcgbBZ(Wa+c
z?id0SJ#yJr2=>ZjX^FiqH`4988}bh~qVcBue=>ku@-&L5-IjmzA(ZyXpLrNqzkF*R
zv<=9)6cE27&j~@}p!_GSF7t=vhv|aIu>3FDL5;|dybSM0<x6wGGA6%SK=&W+%6C!7
zWL*9S<#6xGBbLDYeR(C-DNV@FwO|k@<-hquVoDzK7HHFQ?{8pfMqWT^qFMRB)sTB2
z@B1E|n3F$D#nJYPVj*Y_inE~*IH)*4M-WHFN8O+~DR$BR;*jFeB^3X3R`hY;qKjhp
zYDl;$qIj_DrU?BP2Hh1a7GZ!6EBZFT?<0z^wa|7{@j2CTdMFrX$Q@ItyU^&VV9@O2
zrPwb9r?;Y$j)6Xk0eT>gD{lIOc0#em2yjyI_m42-tLUWyF54-^mH$D_X~h!@&?i5|
z5KVXfiZ|z@GXaXGt56fD*x3hzXB11Q4lGEqh*B%TimX_87@`On02Zo{QwBOrk>(5R
ztm67#5C~TcQ{_m6V%0dboKtL}uWv*vnkkYNqxfq(uvnX-o66DR6l<%|8n5_A5Az9%
z@81SUR4AT+(j>)N%3UQZ+!X*RihvjhrYbg2Nl}_&J}z<1Pgfjrglid!n;*k&rsApp
z!HX<KCe=V>D~$g_%Xvi{JpvaLMNSaEs3^*Zg&c(~J_ImVv2i^>p5m?RFp;m|Q4G64
z!O}v$P;vAnn7E|aOdsJWQpjmYiWR#GVW~vXycVETaZd=AGDTYk1j-fJc5tRbA$k=C
zD-~@548mnaLmezsDST-MRjqjJ7<{Tx{Aqg!+G-WDEg;q@X6U`IS9C|h(iMf3O1Bym
z3wD8}QSl-z#!U(hJtbEaY`VaHO;JOefL4V>i^ev^4XOueS2$DQONU}(1YGM>w5>v8
zm*R~{xYn&$bPvw-C=^xjuvgLcH{E->uGm4R$s3B@wAs3;@cIgtZYgBP;OT9}?q;az
zQ~cEoOZ|$BPJjW$z9W#kqp0bEwn0U7DohM1qUevI4J-Ds;qQpz=Z64B6%MpCk15`u
zH0@mlo9cSU6{@#j{+_~ZGkt&Jz9JwMb|(}c(y3um@$zvHrxcrhL*ulffl>xDikd6%
za8{8*MV1c~_SB0x#g`{x&|WDW25?X&(RT2l@*o||9hG%&!fhwzhZK1{q|B!^###9<
zohw|Fx2Pb)Re7Y9?jN}+1F7iOU77Velpa?4dO*TM`3hB69#cl|fft_2O9_zoQkK%T
z+gs^FwTnK=%vdxYSK19?NKPm_o`Kv+Wj@se_$o{6;pi#lIeJJ>E8Cl3!B6=w_0wPZ
zIjzD0$`f>ywgoD`-UW$Z<su4JgeVQ0U?Nn>rSB1iDIZymKAlyDP_QCg`A#^LMkp<A
zaQ~cg2~`<KDtAOcTa>br!gJBelQ-Z~jB*cUa$}Y65QtOuo&rm}a$q5PpP;OzTuh?!
zq#UY~Y|6Uja3fhc{X7Iyl#DrGsmhC#iAqy$`4>vlmD5q^T847pd^Bb%XDL;lrCiq!
zEL*vv3v%a`Pt!%X3(CzD>$s?#rSM#iGNl<Txypa3Y#>j``xPwt$~E*@6)2a5LatD0
z`<3RKOG*!#$%~X{=ip+oGL1r0CCci%z)F?*bQ!8l`R(6OTCTh(f<T3`k<L?<%Gc;t
z!eymLBWP911Uf=gD?fY$ov2l2l)^-va_=Jm^~yvQXjhb*x5AkQ<&GC%uTdFcvx2or
zxs6gYSCxNLN3SVApioV-GROxeT9h61{<SJADe&2*RFPo2@(oJEcPKwzf*-9@*-CMc
z9;Nd-i1#YrN(AS1<+7L1ctiQMJH&4)mr!==mhu;xbZ;w{(j?NSbX-T@f9Y2$PQbST
z<#rajeMiY%1D-);o&?yCa_dpB3@d+n4cbPO?_GzQQRS8%2#hHgJqa~;l@}#w99Ld{
z2Xgn6w<uV5Us>@f9Gy@WJOpPZm5;0kZA$s|%W!*I`S%tmn^EQ+qx-kB$~W-&@A(gu
z{Zyzor~KIsO6^swN6>o*l{cM$4yybqu<fV{co-~Bsw&zZ9a4Ss0+c$d9=!;fi|Xhb
z(Cw;fq03NistJ2w?yB_H!FgB}^${!_Q5~RK)}yL7YQf^6noOblN5@o^UEuLlJwvg6
zFI5}`xV%;NG3cR>>R=eaaTPlk;DqWaIuV>y{hf>c`l{|z9p)(&kFLO+Rv8{afBjS!
z=y>C=8hjTZKqZI;El|}<-%~iF`kG1*gH*awa0aVBr_i}AL{&#|y-*di9jsxhckV;*
ztm^qe7z|hKq^mm-Djl79&Z*uy4K<Ofi;eIiO7#dG`lD5SGI$@OdTk0L6RUbV5K7}z
z%{1G_tDepTmY`Y~4v?sFOM~hp)saFNN>&NuA)aDW{X(x}s;Y;wk!h-Vv?)$kO;Rj5
zL$xXoAXByb7HC<jbG?wrRt<K;(s`AYk|7sV;h)0%Mb$V(*>hBPPeVLcrKQM!o~pwc
zocXG!55W5Z6^owLB9+A(&J?ST8qipxvh`5lrc_mAhD4cafggzFstXMuR;X4wgI1~f
zsu{G)s?=c6s#Kp9!&0^CX$SPMM)f$I<7!n-?yyv+>b?R{ui`m@^NQ-pPKY<CYV#q`
zs0yBd`6kuFbUEm%ig_PyUsElyQC(HDYVQLOTU0{2f!eBCMaT6v)v8ZHYgau>+vg6|
zcXVZ;Q?*0`XS!5Zo`TYD)pA<zdsICS0raZ!@51hN)nWSl%neoCTIjr~dXAoiTdHp#
zK-q28z)7(5sZLOkqF)u4K=IE3)xQ5;Jk=wv;2Bgo48e;bl@kTVhE=XBplw7INl((K
zN<)jxn97kB`n#&HAAz=U)t}!1yQgA&4ukhqo9S>ip}I#m$tG1jv+#FH<undu)2eQY
zna`+hdBUez)z?>P{d=JL^Cc*qQ`N{JXs_;h97-M3_4KeERNLKwPmb#HG&DM?@7n`A
zq)z!9x}DYg=t%6M?%9vtyQ-h1W#3Kxiy4jX>L+T@cvy|kpyI_-A6*9Vqw4uT!n}t%
ztphB_)ap+u{^_ZH=LgvJQcwR0_r2ApUIFk?*HiJ)adqvhpq*5IK`)1|`rGC3`;=Nm
zsmar74I8@s)c;%n@K-0ULt}vY4wY;Lsy!Xir8DX{TIhq+X+1C>tk%Z>3sDD99apH@
zfkKV8F!kZ5;P+Xzj0Y3p>d$ER9ieteMi0-aSN{!dk?LRroQYCz(xWk2z2<fJ6r;|g
zAVsWNpAVKewW17IyxKMemISr)DriYmF9?8ZNop^eeUjB>w?Io#4^lcURehL_9%(jp
z(Dy*o)!uZt%TRwrvwWs{Xb*^4YSzmT%vL`~;p+41@<ZUfp!Ovb7u91_2bQC5r_gS$
zTI>TXPwh_~%~!j>3oQlecUl1o)uB&7*(LR<#qh95T}APpVs$D-=S$SKGMbS~)k_Y7
zr(FHSI80Qix6lhzsqP&@<7M?zjgY8PKSO7pYPB*825Z#s-^9;Ut9HBqtWGU_4OqPz
zpDDtNr`}A*ga&nEA{=d02hpR~q%IJHc2)h<!=PPLkI?zNSzTeHV{?o8zyY+js+0X-
zsZFhTAA;@b<*%aK9qQjHqSmQiv=y#(sWTsgwr;gkE983A+aCw$RX@uB?YjDBI<wqR
zdr*$<raGN2Xx&na+M(>WI`ASa^r=6kf~bD=VoE^`sO{@15qC$;qEPsty6rXea7g`t
zDmRDKe7e9sq87Y|u^3fP(X&3Le!B!d-BmyNIRwVll6(l<Q#(h&?tQiQ!*FIo&E5do
zq<ZcO8mH8$w0WOar_ttNMxFc(yqHz{?}yF@>V?G=|D02Q)dQ#OH3C|z95l=6E{K!n
z>HkWtHPfeI&{^}|j{q*3czP*aHSD*6xoH|GBJHj@NFNM6ta&N};D|<l3M@x8?HXVn
znlK8Q9n)MLg+Wivih2MqP3lRocxzZ5^#1v1zN2m3am|NM!P66(UuZcysbQZ0kFUlr
z4YX65$4;a1w8o(xEPk4IX|Lw5i75vN(2UbAI8Y<|2DCF8ciI94X@ZAA3)cKY$+Zy8
z722tWY8?N8vM|l&^%#q@n!gqS*upi5{qQtG(^Up=PP2b4<RdkyyD*kfnp_n?v}QFG
zg2ZU@y<jO`bMkGdNzgp976OTyk+;y8q<NK;CTrfJgF%X>f?}(wny0J)X__V~RY}+U
znhcPkxlRvRre;GJe9E$Ej4wkzTci99g6B17SO6C^+i7GkYQm}3D@Rj24}!TGM|bov
zPa}R6jrke_y@myvWmGI&s3}T>+$Bv>5=N~^^C;bTDAshn023veeN>52s@ZrDSea(`
z4#<^j3a>(-LSvhyx}8eR$`8PES@Q`!EmfLM5qPRKI%lY<(bVh*tyU9H`|Uc7ODNp0
z*PMw#;}y**ngbg&D!Q%NsQGa{Xib`W2Z&$Q+^1mQHBDFrMy6SFgBH^kO=mCcwrb{X
zfTc}yz(%QxcFj#6XzS3lxIm&)^BotgU7C&g;OW-9`vDqzH0euWzE{&ug@M;K&jx~a
zOVgbV&fA)dk1<?*nmaVW{hBqTY(VquZvb~Rp4%Wks2M#94~I0n{|7Lvu^IqIH1Z7;
z{~XmUse#flP5Ybh?XD&~2ZH08KZoJkJv_Pq_ce)B%{HM~{|^jKYO0rkWlEDa4lu1L
zq)qsYrkAc*%xc8+Ydz37pN3C!n(wFx%3kYL4;BaQXG<}@2erZU8#rq3JxPCm%t`BX
z7J`SgKhRI&tPP>+R~PO7u0oBg*7<KpxM}}b1bKJuE343WSX)6wF-Nq&D=;KSwcKmK
zJhby^6Mam(g7#IXw4VO3ds>_M7=WKP?N@O6Yabnh-2iPv0(1syqvq55cSf5-!KfhZ
zUYhlSwWU=UuMjPtGP<GK;^SZq)8<o(@vQdsoA5APJ4L&@2<=I_a&S)jNCL(%QrkWa
zT9noaH9_;EwQ)^wCPurF*6Ud9@4rJJPFqXS+j#AvXW(Iiw)zVITcVb60OpglhkgW_
ztTiYhpQ5$U&LS0l1549tKZW^pZPVLe$<WSs0LavSLU)_8v<w!#Kib!h!o+#){zU*6
zv@Nt4U)0)fh4~z9AI0o)wO`Y&BTu`Wt_<XB?P()+$)^304{b%-TY+dT*80%ax<u<t
zw*gDFrk@~RrX9Bjtz0{6hMEek^jpv>wH>tatkPcOfTdcyryp`P+CS-TZmm{a3Q(sl
z$%2V`?Wc4WzM_3~27PJJ?x6~SMy-U(xtg@L-vls!Rh#+-B(7-(=_t^wb)}?!i`F9-
z-EP$$*b7>R*8g|VI<-se0J^pAMUd~&j_!gpz1q3EV7aahpoIMm?dT`)_onuTM3}#&
z^`qGJZEX*Q9{RLG+CBGcJCi^g(C)WU5ASFfg@9*JJ30@&7}9R<g3@8_Ak7IQ+Cy~R
za#Xv6p5QU<zt01^tKCf3dd9Wkl>qm&$1?%$Ypw0@X+rxly+)JTcPX+vrCoai0@K=C
zWzadJ{fXirv)Z|Lq56ULH#x0;b6Piw-8twUrCsGg-CFugrK7Hu0)fuD=ORFJ(fv_^
zuDR+aD9q-jyD$MxcimD7mLJxoZv^nreNzpAW4iw3VDZ#_ybCNoy5=u2l*e^nT?Weu
z-Dw4|le*pX6Z-0y&6IyQrF-%{w4T;I^)^iS={C~i<*&=9dXfO$H025cbpwkae@5p=
zQMw?Vg|d3Vx>he>A-eG0Fc_+vqvE45-58xT&*~QT1BB~5>d?Um-LX*6&gmA@>K&;o
zR6$vkE_E-(KcjV(l=6<zourdUtgdzsw8iP#snRB1=Npe-J3;s01vrzai(o=clCGKF
z)MVXiO4_FAmiz=PRkwmxtTf%kAatkeA|jzIL$|CBj%Ml}>I6%cZtDjaplqEp1?kW0
zE>mRJc0pJA1eE6L-lWK5p6)8`D)V(CFT#9*Zs!(&Lfvi_bYIe~OaxY>JCh5g#k&8U
zgQF!nA$@YJRJXSXEM+?Ui3_|cx~FLmQlb0zeSk_`Qy0KxU8exzRk|ISuv@KLO>ylS
zo6c=Lys6baX@wVcy3QY<yI!}k07|due*F{U)u3A%0>MVz=Rv@(=?+p^WV7yRD*0;B
zwbI_FRToQjGi|!VG~Ko9{5F84L-$@2OmynrrHcz)y7U=zuvh2003Ke~xznZR8#-Ht
z7kGwr!>>X2ux=T}N=9_pnBXDTg;Npixb9b)?C<I1EYR-jMmu0>LKjSN=1HAlC9oNt
zBNg4x>fWN=&I3G;5OC11JBV%{)Ia$mv^eT}D6Q<I|8WxFkly_pD09}IwULXS`q8(c
z#!LTr8Qvpr{RlmXKKkPG@cXzvya<*~=p!iCeNsR3C@^3B^AvhGrQbp$ds_eKQgHg|
z-wT6zfBjpOC<)M8{Xh%Uucr9&8GRNFWw3r3Jr^PR&r9(egz96wZO|5`zf83ZXZ7C<
z0t?ss(R>rB?>G&?D1H4!(4zIDa?oP*xp&}bto~CPr#O8Q6*R`{lc)kRLEl#gmPEZE
z4FXB}wUkXy)_-sov=sf~XMv^amovbUreClJEb039lj!gNW$3rvfK!=zHzw?!*Z)8t
zS;^6Ve+5{se(p1XJpHOi(3r3Pc^|L>{V)AcTB!eg9|qx)ev=&rxJW<mT_`Qq>!!h3
zqBl^9XsJGvJ_c2$PozqUa{W%)_g3gR2QZYC`iDQG`+t}9o1DQ@rT_LL=&sg(PoH?I
z(f?=%tXBVS188;np`Re%p#Sw8K%4#t+I_d{?=MF0JM=kJXwa#D!4X~S(!W>;@oxPS
z1HgLqIp2eJUH?cYIB)3NH^9T2dL@NAZs`^40BpDQ3u&j^r+<#N8~u9mQApg;7gCa7
zQ2+f=I6S1Uqs_~(K9|OFM87E$=128Yl>QjgcU3~^T|LJUu8r$UJ%HWQpQRho_w~j-
z7@0|Z0KIWj`X6YKnAWfP2ecV|3Kj3o+VoXC^zeZ`jw0c6`pJI*><v3;2j^h;gF+Vv
z4F@fdcQh3K4M8WvmlU%*WO#lMUN{?0_CcwOVfkP1-qp}RPnnzHogi?!8y<ZUz{Bth
zRknH>__RUrGJN<nI_PcKOP6$f47N-sv>rEXK`eUy2}2-NHk>kS>_%r!8;q2j@H4EG
zK)1hvyB4$n!>W7;1{#!fH}H(%GYWhL8Sb>>*A6zs(l_Kn4L?%YHq1~w3YN2mfM6&K
zH|+Ql;t__q^)P?VFrUH_k%lL2wC#>Eyb=vH(FUi#p(e(V@H!-74eK9<nm9v=9YBKN
zNpCbJ8uT>4NrvCPfSP1O2Hi1AF)-+?lxA?FcvHGzF@=3I3_*ENmT4Hd2$n2EZZzbw
z4U#@!=M5i{y^Ds1M```bG32*m*m4ceX@KP!nl{0=d_w?z@~^-!>i}Az;id*AN)55=
zFcxKovU1SM4KehlR~WPu@~AWvEdZ^`aPK?>streOfL3Ejz6x5s;WZM!Vo0J=q6UL`
z7_>%%_*c4r+hi!9`>fXtw<!$TY&b^=))s>c2Wr|4k*|Z+VTjy<&U6~Scoc)sWf-AI
zUbn$F4+1@g)2~9H*I@V?oHq<Fp8@Ah!}nCme#>BO0qwS7VJE!kGaREGeZS%SC4d2g
zZHo4vcMPk4fu%viT1r!m7^W!|J8IZV$Ja4KC7qz|8t!}!-Q$LTdO^Eq_>E3L69yfn
zz9tPeDruN9jJyq&X+uXAw9FXxeT@N{GrU*{PJ3hSYXA<$jmyz^(D<_o-a8tnC}?eS
zGM+dA^UlVORp4<kJ{1DsYP>K8RyX5iif6bRSH^+$s8Qh$-5$oplt4dbT&ahLp2mfF
zVDU13Lm4b@BX1buKE}<IPCIU_ZUKw0F`0rnr;K|jjB?tzkA8bUqlBUp{x)O%(`XGe
zzI+@KXN)h?wl2t6MPbws<1Z8%3N?Oq6?VgnkscWQv&K)pg86V`Wee0q7<F%f7HQ<r
zrKBk1t%WccZB+2l7-Nj}1xu{4j|aIpV=2w<3C1(8!(O8CT~d~0v}Mq)GTFGk96d}i
zUabI@ZhYkzjCzJ~;})pNH2(A^1~|*OoLI7r&r(F~yzw~My<i-riyjw^$*BN2#&4;V
zDA!mt2wI+T-W;6CH*SvsC@?OeT}PquB9)Y1GIFwEsL0r2<AYdiTuV1lON<Y$K~0%)
zs2qNm8$VbBgB8Z+P4KkRc##g#myM~VP*Y`;MS@ms9H3-MjgdjcVYS9*DB@CQ{399W
z>y53H)3{<>`3-b77(b>hd82U!otm4B6Z?T(HGX8GAlNmd{ZgRK#^{Y8witg`z<jH5
z-KPL;#({pYbQn#vI&>PR3(@;7<JOl!>ox{bhNZ`Nm=>pA<JCs={<<;u3(#&DA0B`g
zH;vg;5OvGwGY8eTjo(pORiE()<tF-#E5fM$bHKQ75M8@tjH^TIpmFJQ07J%CX-hC{
zjQj#>MvWiS6^St;gBF>)#_110yKk(fv(|)hTLr+R(L!bRQ^pOn3{D$c?!b!~qwguG
zo;ChKA<hRz9Yw3>jB>iqW^bC_J`eAogK7U3@EkNbg+s#8^d`M{PNw}XU_E4Ve-e$(
zrejnt;bO{3fq7R`tQTl*Ch1P}*WL8nI0oUcX)A4ikC;|$26ohxn-4h;6Mq1zkD1!(
z<m733fr-9&nKl{0>1}$P)(V@C>Fv$%?YOBW5`LdB9qb2o(j;#KkFV)C{r0C!O?2bo
zw8<w5n4gJNgP+3Rw6hEX0j8BEcoAq?HXpjrnEtj0OOWZO5eNjE3=;rhCIzj~XHAn7
zl?*pEu7vjyrq?N6bk1g~cnfMGO%E5q#VFI4^aw<o?4N}B7}M}gU~#73X-bPXJ)Z!O
zU|K^5ixksYU)W7GJ-rLgq?u+Y!<lXpPQr@})24S}Fw?}Y04>WDM~D7w)8a!=cHY#I
z4tp0&-V}AZXtGt&;+A82Xe&I;H9fW$#5|KM7{q*xI+PZe3QfQYO^@vZ=Ot4p1E9!s
zrwS&DO~JI2DlyG}6yl|(C+G<(GgWy4l$*Rpz*%APrzfz|^b$>smrcj2AW&sm5D(X?
zO^0o?9M+hcH)GgpO<z8MM4jo$ZNTbH%`|#fOck`8HJEPDPPNgLcL<=#)O`c4T{ZPx
zgQaVxNe;9%oAQEzwV3LEfn2Mp;3IUq&19g*x!r^v3|=GCi*(HHG&u=C>oPGIwCm_L
zeM{xZJ*Ky2@I>^Q{N~Vj-SiX%H*c7>EP~)oQ_?4Byk(lp0CwBdM4xQ$GZj$0so&)F
zHaG`N<C~%7j_H#?bZO8OLW{(ZDSb5z4x3)M2W-R?R|{;^R8L!&G1I&}ioe`7{dOA;
zkDE?WS@S*9{yy~ZzG?9$7@RV_MMW{wrdiq<%$P)B0JA1e5KKHUoug`+In$Aspw!;{
zk0%-(%mT{Y9yH&00UkP<4^ej6$?QPW)gg1uJ%~G-KmP`9yO=xd>HTvxD<1-nn|Wad
zTHVcxhk+e7|9cG*N6aHy=ss#@(9_~!-t`@HA2a7{gBnkB;(yUpvkQgJz0JST)a_%|
z?m;Jxo0ptL4^NnP{#RRO?(jihe9eE^VBwT`2~}X7HoMR=X7e-ux(cj;=Eby~3^u2V
z(HdgjPkY-?^Y3ZU9cJD{d%d$}BUMs`n<FXI5@Fs)lixXW#advIX6HLF5oP95>N(o1
z{|z9<{G1a0#+vWZ>l<gDPJ-L<X4zsmnqYoc1CVGl8|q;q$^88kSd-0Pi@=j&zDTFZ
zRC6b#fYZ!17O<q7w>^o*40D(}T+1}SB}HSFd8Q3^v&~gsqw&1?9XeuOFvqpSr;Fw$
z%CYB|b5}zy*UYIwW1hK*V%PcR3v|1*z-+rph319k@=6ddnLn4Kwa6S$2c^a48k*%x
z%q>)-Qfj{TE?COUi{F8Kxq0&l9IY@jndoSx`G^rLm(4x?5U4U=NyRu<n}3i3)R@2j
z7_QZtU-}EK)tR^NgFwA`F&kR0nAh1}ftm*M0KFZJ=3?6JH<@3h`>a>Za~3GQX5J72
z`DSyv5RSH(*M0?Br&&(Nz;3fEMVNZbE02KIYfhlW>AHDaCA8cyUzi8%rg@Ndg}2NJ
zI`r(edD{cf`plzhm>o9jl4$=qYTimu{+L-sLG!z2Z8~`Fn}x?<V!|9iIiN{%C~YvN
z%o*EZe%fqs1j~%Meh}EK`SNMd9+(Ti0GKoXKy$XerGtjV!Qw=bfP)raid8sTrf4hS
zWU<nnibIyMEXqGPTOPX#Z(J-h|3Im$Wroi1ZWbRpZMa+dndsVK%g{;aK4SS@3ulg6
zPEd-%!_rP=Fvlz#sT{@Aa*H+rUY2ir0lY2y=z;LDBv7f#af`kYjVCNgzeCGOO9f@3
zd@UR~o&Qc*zTkuBw54VMz|Zn3b<N+BvlTuCSejyBFwnC5VaT7cc#)bQ%j7WZ23vl>
z)HFZDvgiOnsHO6IG=^DLkHPL)%hP&b;g-56jA(?Vq6!AjSuBsBG1Bt43aX<lsVwx<
z7HxUvYrq)G*;NpXwH*5$AkMOA4V;O$T%mV6!7|E*Pl=W%jzd1lvW<(zWXq?t0Zg%Y
zP_0&~Wil4DG|LkV(9$g*p9d|&vWpVJnU-~S@FL6dzZ_uMmao6YAe^_nz8i*eY?jR`
zz+B6&KS0d0bn~Gm-?EYpg$0)KL+E{>Wj&SDUb6JjA-c#C@*P-;E$=y_7bO;_D6o`T
z?4CtqnT0<CmU2tk4tP;vS@8jSR%schn*Ga`^;8pHW$}9n{#IN5Sq<?Ti>;o}T1zN>
zW~9ziNC(z>OPn9DE0%^AA<<yjIsnjU$uEMMCd+4S09P%pCK$YCnRghpX3L@=Xlb!5
zD24e}%X744YqJQx2d&+bwHag4VR0`7OQ)sG1ePv~o~Dg%ORSA@BRv-1bQtWlJWET*
zO^dGpzTL8<y#$`ymeor^>$8kLhC%4JytNW60~UKqU*56&d>u*$EsNd<%aFw}A7e3W
ziLL}TVoCfR*r?^VPrx~5X?g)V?^+nH5FfWJqW$MR%NzYRjL>~cdJNP|SiW8i)=5hw
zc{*k3rcm^>Wtw7HGnOynp>);~ejQ#suza8e=bXhvdt!TQ{T#G7SiQo~c+k4{Ww1C}
zzdeISC+iE#pzM%!6=s<E&ejYEc;RAw%^8iZ*7q|g|L$h>{05fXtyTVzIBcDH1KmDi
z4RC^*qt<;??%-jazaH2zYw$1(dRqT-g(WZRBNQd@wtnIO0Uzs4`bgMuYv3q;m=o61
zV#uAe?wJJVDXW;WC#S7z-vf)Eb%zo(f9va)Y5fbZcBR9&Kx;fzNuIG5ehy-g_3>Cp
z1Y3(KqZ?vvt3YF@^%5OT!>l0*Xgq7(PSLV(tBMj*5!OSW0GzXKjDwa)>r*<gL|K=F
zLLk=q84q^jteq!dDBfCg2L2{kx8R-^@()(YLm(zuhv^1EvbAY9dYEDjIR&0n>mM}t
zW>_B_gJ7ohcn}6C%etZ#oENOabf~;&eT}|Nkz?gN0a~tAM$d7cbrXd#^Q}@E!vgF0
zchFgAjmiS;lJ)h+Ay;Hoh`~~9vp)SDV2QQB8=Wb&?xlIX%=-Fju$Eh&@`K$9tLQdB
zrS%WGqIB76q78nPbs_^;we`CV;H<IkTnM>Z>npUj)>((F5U96uDQtVi`o$2i2J7aX
zu+V6Yr<7Tf^+gFduUc)zyP@rxwQx7kX6uqD@U&PjzX#B2<^BrS+N|HE0JK~4>6Fr8
zwNiCRr&Uc=j$PI;6+pLj)&)v?thXq8*=rTjjfd;jd%r>8hV|KRA%4^P=tID6SsUaS
z?c3JP)XzTagzYu3_FH95KnJYmZ-L#hzHkmc4O*igfy9t?kOzaq*7ubFBi8R|h8eXM
zY(lrktZ%;r&bwC5A&kYil}*8`d)5b(VYzQr?10?~>w)(nH)+*UkZ{VHK((FI)-Cka
zjv4C)32g*ttz61NKCsr&k!#L6s)IB3b{^NE#?fxH5`s>4PLTkI>^`xBytCbpcHnfe
zbCLmbwR5I2P&d18DQn|y_jVeF`>@?GO>9T(w$ml7qjoFT!EFz_HTQrWvwM#!TRrWz
zjnVq&Wp{=u&b;kpi$L_Ta}I~n<90pILd^-gNQz^gv|F(qz}N17G#8z+D>?wq({|4v
z2Igm1M^mA{T_~;P0d|OX;cc>;mkupw?4GB0Gsx~o8CZhtcF@lhV)yEHu!P#(pQZY<
zFgu5zVg9UL8@*NGb`{s5G{R0sDV=k6$+VS;w2Pd8M3miMe}fil_s~fQ#M$}o#K^|m
zJx0O41iPjq7{f%nOUJ;HWVdW3dYEi?o06a@cA>?<QtgiZpQG!J%ewmhnPFwA4NEio
zHZ9G{G_$hIG#geH&)$3QM=KjvkD`KrC>vxrSRx>bfNYQ<2nZq|O9dG+MWze^{k_lc
zuk*U+p7TEE-sdy!J?Grd^DHLeyz?vnftlv~?H_Q>k?x#FX9P2xovBbZ)A{vA=w~~B
zGz-ie=NlQ&$aUrwz<i#wnT@^+&Kr}UnD2awf>1@yk5C%%qH|g%K#QHz&jF>x`ISRx
zU2>k!heE0Ix37VeIZNq=Eq7kI0sdZgu9jhB6%OYv+96ju4^UCf73Y8tpjhSnKHUdb
zox>i$M78tfHt5$lyH!A=*4dQ`1+F=NL6UXOLkr<rz4Oh@P;YRaM@74h&Mh<Wu*vy{
z)eyPvZ2JU#H=Jb|0K4ft{5ATToimohY>TraYaF1roWG|t9j(qLDpF~8hQGLvoQ=Cc
zx}2YkfPT00(JSzx$9cLC`n}F`-hp19^Hz#V-f`Y4gnGYo@=~<!I*&9#Z@~G3haiK_
z8))}B<osR$+#Yt`)&j75&Wq`pJLWv#C<WTMGm91&6V5^ZgZ`v*1`X}L^VQ$*8%#N$
z4F>kK^Yj0M;*9f$hXM1zdDgFR^r5q!0!_Oa{_P+xjFzY1;a<iQ6_~tzjDh<Q+0XE%
zjJqo%?r&IdWBlL^3*L<8uR(km@86<p)|au-1Q|bu$5|NkXH4b7d;nv|3jhsfm?%$s
zgmI!9`XP*-oxl!d)QqDqjN!|GWH>`H3n)h!&!L{u=@`R>&VU_f^xnn<onWYFEfB#-
zq0fg#GV-Z*H;VB~1Tdo+#a;CMi5SLLl&Cq&_+t$ENsL90LL-^ceG`L8VaVw)M=E2A
zqVwk&>zBfA8sqgRLDCs}S3)v_@%VgzW-^*OF^DWiHXRDgW_<q_L~<A|#c(E<k@G1;
z@)(ai2h0nM&!2^4KBE$$S%*^rBlrKa8H`_P(^15zD1b8;8TDbnE@q_c089xZfx_dL
z80nO{E@d=PF=`njY#+u{&iM8u`Ytp4U0}C@VR;VNm5k>^5V^ugp8>Oq@f0Okt}@;u
zN2?i(X^7M?exqluqn5Gw5<0IjZc+xUj<J=Tsb>@~L}vq|b2*rejD1wj(!`iQ3d!q?
z9T%YA%<!PqT?=EP7R+0W5e*bt8EQId(Z=}H1Fp3*H1j|@7`L*)yv;aFY4lEp-``+%
zG4Acd%yc^#J+x-)VZ1<Dqh7}DPeJ+^C%eJC!<bDqBmInB-@xEq#>WXTIKW7rf~7%*
zs2Z&yhVRR8ZJ6<J39il&hH^icqm2BUP`}4u`~vUC80+XEKhC)QJNhOV&%6mQCK+Eo
z3x)d($IDkS-YLe;xzLzqEOv$Y8OFLf=zPHNr#-|&hJyjc-OS5WueXP}=`dO@%)Y-M
zvX?nTDX4wSy_Ejg&%8l(D6UMuZ{VRDGd=`N59T*lF$hoQN4Ma`L1wiSdS1*Qqo8+)
z`I3XGqYpESXxHw|OpJs<A7&-RR(+W(9)X4*GfEB(f9C!V!3<!AbwM$Z`P|=N1~Ese
zrXZMkhUy%SFz2!{mJsHL8DNGoKYjxwjJbw>`*7xy!B9WS9DECs$Cz)&f_a?j?L+l1
zCzy->gBKA@{o8Ojk{Lnu+fmHFD1aHw{OShA6vKR&0=p-fLv&rmGW+Rd*D2-`lYoh1
z&ecIAo_T&1m<h~RC?<58SxAr2L?-(sSUAIcHwMsWnV%KFd=m2t#Tw2r-*ct<>tyEN
zv_eQ>F3$u>WuB#o*m>qBZvZBZ`P(v(bf%HctY$Dz(yk$sd3p%?S<K(5rXZUsqa|Ao
z^C@3g%4L2+KYAW>FdqsRm}^*=l6+<qof$1)?w~^rg-k9je~XxPyD9&0ktv}wRmIGF
zs-!AmX3`~aiCM=)tCZ;%1<^8QUmVcNnfK{T|7E722t%u2N@y`%#f+gyTn%$Em9f+^
z3+Ka&Ys`LHC)6=#)&i`a`EL~Fse$<;<$fEP1uCF4F`atRa$IMAzXK+2Fbinge3KbL
zrzx753;Q9{!i=GZ$t|WUop5YrW>N7`8&l;8$#&*h%I0@4Uw;C9x0$=8K<i|>)68};
zk5WXdn`yVed=K*lITU)CEfhZOW1gjj*d68<A@H!@!Tf+uR^DZ9&Vd&LOvgSL9Apl!
zhyD;VZXslbnOkO|Z-hBJ39V7)m)BtF9@C`^tudxP60LD&?=65%Fe4};J;{uI1%3CK
zf6jt4Q_SHD5SeDa^ej+jnCmE{^nmGh9SRSbj&Es;x|<~$f!#f<^;GHY!a70m?ftBg
z`9O1JmAwk$##$_e#sSv*b?9?vEk6O`!J7U8OfQyw2qK4AU(h+p!>pHv(dWxLxd`U{
zSUVP?<<I(Eh#3uFrNu)skk$MEeL<{u9jWLHVKHd=8_GKR7&^mP3+V9?&N@p`$)l`g
zRGDy$wRQ=xkF$CbAbEn-_6sB<SRs_WiDXT*U=UHP)c-HxWl7dTB!<;bi@cMpH;d7V
zWz7=+<rM4XA7M9+HT!!g#Ix$J(fcofl|V-&PP4WQVQLat6?BiCVSP%`oU<(7F0_(Z
zBQF8%9BcDGAjz!Nr=gd^GJFV<%G&%t{LJTBFVIhz#tNsmXgcd(3Q%RRI9!NivJz?K
zmc<IEn0YoUnAU+gteA6@|I1~0JOgeX>&;$hTwqP!1<7X#LO}{xZ+-_-$m)0<c8gg5
z&?D_4>&;*=i&;fgaIJ(@*$?I=7V`}Zt(3KaUMFR&G0J6@vpVV7d6{)%0Ol)LGAd}Q
zWc@_9!xdIKB7gY*Kh{${;9h0D+>TkVX6=kYXANt|c9^JT-Jxo<YpkPL7+M|cWePCY
zvlx`yXkeW*gW1SRT7$W4Vu|Pqyv}N?g~1yvC%W%%vX;2O?OQD8WLRirB~gx`jWxIi
znC&bh1*RPxth?U0=5DiIy9WJE7IzNjqKh>>2#s!*4`KJPZqkmgm({Wd%s$pP7AV|d
zEqWDb{j7GXjJ?bHHWp|DtSez)4zk7<0&Ix&=#Ow_n04R+$O!9qD&iSsb*7_rkCjX(
z$HyG3SLQ--oE1*5r3u!evl!YWYlRQUeU>i;KBrjO{ZO1{<+eg{h80iO>I0VFA@n_D
zjnmp^H#^-4KJ8&w(6JmBwve)Gd)ZG@+3P-bFwMn&cF`T!b!A`V0nClvO#dc!fbA%y
zE6JU$UkMEl_HXnV7*BS|Yv?@4UP9q6FLph}#}2WRsS4*XdoE?gz1iYA`0K;o8;+JQ
zd)Z=G@?%d@EXtpKVHZdMd*yvF1KD21kPKqS)L;&S*$b6$<_J5Db_*fwB@TK-gtA@e
zG*cKmj9#kY><uf>I?8^s3$0`9m0!Y{<Lni=V4h$<9SemB_UB=MiDWM<g-8thbBb=9
zWCzTGWGuUZ_5kthdvWMXVE^?v$Z7URNf0^9me89$iTyOi49>BSyzan{kjy?zJIxgK
zHhQF`vgcR9{dD%HgP55Nc03oYO!nVT!C)49CG7#S+2<wb%VCGo0x*~T1Lgnn*z-Jr
zeSuv}&)0nR;}q#BV1GaX{6cmX<sFOIZTmnjvR!GPTg-NEqx!QF_7MvEUSdDtg3eO5
z?hdfa*sm2}Fy-v}AAo(CEudI%1^XRJYE-gsN#Mm5Ht#$1Rk6Rii=ka*Z)<|xYWA{u
z@S=uYqlZW>dq*|;uCX-~P^)8~qX<tudxsr;4eXD{==)2J>;T%IG_mJ5pz}I=87;4F
zu(df*yvg>YWOFn7x$Ph=Y&W{DZm~B;qOYCp9D|{Cuyg6%c$+==8bCYQ|NQ{c#r6$@
z_ucHHv^(lyZ{mX4%icsG(mu9<l7e^GkI+-g(a-*4FX&x%?n4ZFfc-XA<_@w`OX2Vk
zTNn(x!|W$5ur$K%M!?o-l<i09k9+KaAoPu~KccI1oNf3Epc8C~1nQG)CDp>-XOAVK
zZ;Jh)3DDE*hhspQVK;6A^aJ+Hb8vf)gLAG8qAr|PDp=ji(Nl$;E2q8}19jsJehJV6
zoDIjJ;m%3^5ZE3ZXUgV#aw;ZZ{vc;K8Zcg*KKj_nA&%?QAcr}N$H4UF{6mR9AI_2I
zVAq$EzXQLrA7`3U&i<UK6)+UQaa^l|XdvgTJGeodsJ}siIm_q~euNV#1PS46?T5i|
zPSiG-Kg!v37@)^E-%`=iagKrZXeT&lDAXCjnS2HVjpSs}ZZL{7pUy-@bN-`}kr>X~
zZ(x8YIsY}nnOKe_7bvGVp^lZ{#&M?Jfqp#4k4^_Aa2}6>%xR9{L&zj@GLis#hSM+`
z=Ff5_zJ`ZMoS%Nh%$(y4Qr<C{^D`~pQ#doUnoQ*!Nr2vYPAdf>(m2kv4NT_@M}e8a
zk!^>1CZ}JD(PwcIHI$Lc=9JHd-5gGN2xM|O$8N&mJkA!%yj|doP`Ejt<K+it0p}lj
zZWMApH3O!IGckdIUgYG_#;=(3(hsmy!r4%O)+J6&IlxLe{jGp5<9z6hz6y>rg><Vp
zi}HYZl{5V*<^QTVpZLJj8cr7-aIWRNw-qL?aXzwxS;wi~4~=@xwIyISa0=<&*vKiR
zyw(lQ9lGOga&A%8Q8PzHnbj7~Kd*p!ixcz+6k0iDlxJ<@_%I>T&RIhVv<{AF96!u$
zPCHK8;`?Wul^>zm!}*(*b-kS0pP<ptxwQu5E+^U_<_9>(=+QFFd3!xfjBsk{3q+%w
z(Txxp=af;^>;z}te4tEnibvq#H0PIM^v!TQ7lAzBOk44T?%_@df#Smb$P3Qw<&NEk
zq{EeKXu@2&ab5Odh7NE!K4^JzBdD_dAa_L%M7_8>e}Jerw}I+ke7MX-FzCyzok3p!
zH;^h31Gxt&;1k4E(9<@A+hs>zDEGBdfQ4}jDLr+Jd-(#G$GLmx(mBEXa~mY19NZ8V
zn$g^Avtd4loACrjaf<8Nh*lg|s|1PXE~9$LM6O~6!#=}}^@lTOxh8kClDWtKfKMsh
zmtF@-Dz|V26w<i^kE1Vxo3sifle=>SbC|>Z;{Uhe+_{v|$>aJ*!kGfD!z&rhLhgU>
z!^I+QAT9YyxNlH+{SvpFj!%_xcTxuIGWXTD0dtM3q;yXm_YZo?*K_}M#auLSH_~Rd
zk!wBzksI7J2JGJCj#Id+nH%Q~g%+-n5+%2|ch<t+R&K>jkT!0lgQ7C++yq)gba21R
zg#K-={6CoQ<nrCn>f&;~fPN3xvl6XdZkrX7ecb9zuzQDlY6n33xlbR$um`wjU&J5=
zxeKYDV~8ud2<TyMatjnjxZ7-Cj&d2VLvNgWL<2Ixt-MG1_eri}KlG=${mBrW;g+ai
z@Bz1lp3l2^>RKr7;eAGnQWsv89twMT?vy6l$IGEKqARbJ4j#GjKBX7^0UrNj5O<zy
z3cx&gpHN`TlP9ED)IlCM2*iu0eiQ14coPPy|2)k5Gzi$<ys?krg%9tUk0ImBd+&2t
z^5Z=!0E|EHzo)<q;B|GvwLso;DX<&F`$hv2%$xRv`Vn5;67+@e-q{DqaGn=kGe>!|
z8({tzZ#^X{BY0=-!9pZ&_w&$;;w3Jp`|l)g&o{6X%bN^^{wZF`4xlCQo}!n<X<ii_
zqD<ud@hM=EcnRME<{Ymj5-`cU9h77{&r4{9UK;PtW}u|=o}#Bu7O#bBG_!dv$DokI
ztF3{^1>S!Ym&@mEW?}LRc>n!}kvT5%#1!5u=543PdkJq#HAFA*PSwMUQr;ojO_uSr
zHaJtx>!t17W!@*FaKC~Vasrkrd8I2Ma)tN%CZJXEKH$QOYF-aTt!j9hdC;rn1yEY+
z8t=w4Aa%SaIgqU9t=2-X!NK!!gJ=^k{RF(Y&U2py{Tn=Y5xls``<~J#&AhD?&}-rS
zkG5*Jc)w8kvXz(mC7fyFna^XO?YuweLD9i;(0Fh2{yhlN&HHL8NDuFOJ}mU|e0dml
zKW`zep6~K1`@kIFIk=PH4)XF9z#ihQq4&@*?`JAk8sR;78#1H3`_u5^9&hRgFvoaV
zRK7FLTlE>p1n-YsAd|e++cBp5Jh=s}DPB0`S*Lk>9)Qg7eocV)4|vkOAP;%vtKjHv
z{z(M}v4<byXa{xSze!cMd-;LSp>rSqW7<mW=VR-StDEokEc)E|z4L)~fZt2+U3dOM
zB_uugrJEt?$$umeC<pod<b@Ysv;mTb_zrrh9p-2Iq0gHyy8_pI_{W|F@#U9w0@IKG
zdkfuv{``eG&<Nmv@IFW&Uv?5OLHum0pbX}#9)XD?e9;n2LI^+eEbNBzn<&^9#^?S9
zg>Zfi?O=}bcT)cS82|BC!933Y^8Y_i!r!tLeG&ZizX3CnKY9aTQT(~*(2C|4Z>IXQ
z82)EgcyW>+{SHjT@{{PXb&CJhFZf~O_#aAOFrJ@68=3_E3oT%t=IhsDOo@CM9lkun
z*HJ~_S-u;+=#%)TsmSXbpGPl{Wd0V~a;5M;IRun6{-c!SO6RZo7bJr(KIMe_FO%O#
zTjMN#&;_`k&1X{iY7YPC9AM}2g|te`<8P-M?*jkDOOVXx$GX7Z0)AgMKnwX%6df$$
zpLq--7x^1PfnCghe-O+PzBmKsFY(nB6DsAu`zXN5__EibSI*z;hCat-zJm$T3jQ|Q
zAXM`AZiD_6zOx*nReU2I!M@6$?*@%({&D&#YxwW~f}z#&_s~A<8h-<YyXyEmzQgG2
z`F#)2*T84eb<xNVrFm-NN2~zYb$%U%`fuQ;fT5fGbsq5PmV>YT6*8^-Zz&7X#?PUB
zO*?<)K4d!h{Npfjo4<e(_nrLr=+hWo{AP;Mb@Lz2M_&(rlM5t!`Gd#7?BoCQA((gg
z>wm{o_VcTzp?8<xP2s8m{$G@D8RUOKFU2ALhX)}!%y)Qm;P(iBV<2Eg`RmSOPVVv9
zzVK~~|GFzQ#`%AC!NUpu>bq!7@?WJ~>V5vPtsql;nGKev`7ev0H^YDbD}X-Whr9*y
zkiYI6M0N{i({Hy&@KXS$#6>Vh`{ccXJ|-0Q3Ep#14ex%z(sjUg6$Ex+6mEi-YT(lW
z!8!`qx(mkq(DD#;X`t^ZSVP}JJt(kbL%~aMJ_MEy2~P9@<*?whufX&c{Kdq0eFPfH
zRr?C&j6%du@b^Xx$zQPa97F;HNo#-^D44&Q&OZbR7QPP9V8NQx@briv_cP2zh+tR_
z7efVMR9X-wDDZ-baKUY=Y&a^2q1etb!MeX7d0eoVzSVF-uxkfEBLpj{UOZ9|M~|y0
zf&EF4Xu)q(k{2UL7z5Zz!RhCK5+`_~m)4*0f;;QMO%V9fcdpI|qMpLA&kEu`fWt`w
zA6hG>3o>FMk|o$iLD6i%IZCwT2-aKx$rYF=Fr6ouqP`1)fcN2cz95}q$OVGB6(EIz
zgEhdsDENZP---n-W$>^>5P6#Rf0qO|9tF2l@J$cqt4vTsM_DclmeNDFLLmDOBdipp
zRKolf!S#0ZRSEW-f%{hlkJ>=01#Ohus1ankVW72wq`$ztCfKzFCh7!x-Jwt~c$4zr
z4T2@~O`1l5Xc54g1S3A^b6gi>GGO9{;J?do|E6Fym3TJ`-Wo@%MbJ-|<t@RbIDoba
zx+n(SCRjBD(k_^w1bT-clYX?@f){D&)G2t9Hj`ZfujA0`7QAs7l0AZten#t#Kt`$5
zenH<UNZu8^cmrg>AyA%zZ-WAF3O)}BUZrK|uppk&V<Uo7P8iduU_S-c?g_dp!5kA9
z_)r)ZtXTk`CIp%_XiW;{Q?}^7Aa^YkrUZY|w{WHfoBP0=5iIk8r3Zp1JU|`_)|2{f
z;cW^H?G-x8DB-bBxWNd!`-QL3TijI`u>hTJ!h~L!I3RSV__n){=>$m+;e0y2?<sVm
zV^ar(k(5*M5{6Pj>X6Vv9~C_;9Hd$vZ{gSw6nunTFG1Z`IR63k{Dd26=jAV4@I9ad
zgx4K5$OH-*baw;^3pG#-7H(M&jU&Qb#0Q*0gu+OGh6=;!hYb@R^Ma*t;T`%#jtfIV
z;r0pP5qg0{2<LPGELynj50Dt4kp7M3q;N$VCNEBSDIOy6!sk^0OAwm60ewbzvXS0@
zXNBKnqnRXp<`~A5BK(mS%&Ec&S}>m%uAPFxbm4+|u#_Rpe+K%QLjKP%ktIx_Z9=v%
z<TIe;3OBrozC7U}ItqP3_#+ju76_}`pk63UdLNiY!th6-a8dXrmB<teC)d*duUry7
z)_`WIFqk%#Wy1HuVfV7IOomp4Fk%H1D}_0<@Vp|Na0Y0VP}U58tA)ReLb67fLOID=
z;j@%ky(XMf0cM@>EeZnH3m1P2W|MF&6}4O!KK&<LyCM9Vc3d}wU&E}!sad$4wlFQi
z)wCnIB^;xp->pK<LX5CY_&hz(dxbk_>DDKFhXSs5gjXn!&@Wun552p>Uua`KC=8_x
z){rom4(<&LlhQEIQDJis)W?PXF6f&OzDj$KNntxho9_z?^3dm)5=N$>b6WW9X?Qv#
z%%2VO4}@>8gu@SoJyZ?4Tl588Y<omk7DK~Dw4R5StLWt^SaK72eGTRT(QkB>xQqUs
z1ek|to)1twMMo)#c~F!{HE~{|0*aX*5>+L@dq2^s|AF{BMEe(GpaG&^=|E1PD2&pz
zL87&{02(aXTaHm25yjI^CPcKHQmUb%AAbhSagh&2?oWumT?Y~&`tbtnMv8{$y&EO^
z`3kV3MNiO;6C)bD0ShNZZ7Psh(VkX}?6hcvGAoH9hZm)i&WMbZoH#2|Zi4wFQ5LOH
z&xyq0kVzKVOQ4t{^6La>s_0iI7)%$*p9FS>=tKqjGDQRD(U&FK^a)V1MH#Dsk|Xl`
z0nA*{3U^56iDpv?@CDIVx1f+OYW@%?1)~4`|Mw>fMS1tYy(EgI2yv<C1tIjyM6IXc
zTDeI2G{$>bw19SA6(Uc1GF6KHp~{3SqLR4)trCS^1==;y5vnPu6K$oCQoYDV`?m(s
z@S_-SqbP9*m`$QNRIqkk<VHEk8=~-X2Ta@)ouy=1o5)IgwRRD^1ZW+iv-E+;+agB=
zNT=v0y7Ie3zf;{@w`h?Zq(?MFH+-*X1MSfUL}p?RilQi&IVAcn8kUAd&r^7AM6`Mg
zZjXv0-h;wDk$`IU$3&)OwEi3yrO+vk`=SR=fIB5>IRl@jMJvCB#*8Rt9nc<#m=rF1
zDEgCfZM((J6tUbR9;TI)i}<O95ZNnk!ErvPed4cof$SI0rg|L@u`&`ZPq7WbD5rzs
zFxp{yiBAQi?~wS=5as_4iwD1i``+SwKRE0op1g&*@D*o#4ue7Bc}Y+V7QaK+>=E%)
z4A4Tv+d`obD$d&t^I_tA6MPC6|42K6qvA0JOdJzeeuY6qiPzkOLbUi%HAsy31YLS3
z#laMpixr2rK;3al{J0u4PTbN0n0Rp~J$4erpLPQ+NqoZuFV2abC@_{R<`09JBKBwo
zcB=Tl8CW_mUQ3aSG;x>+DCy$w-GQAU9-}yZws=tz)N{oBeQ4#1n}0=Lp4f613Kzsz
zk3&7*As(P|>H_g~`p#;h_~T_DMPlayjQ66LP3iw)v0xH*OT;TE27OsPpJEji;!E^N
zoJw)YWlYc&@qHyMRf)eSho!6Hd`kLOi-%+|Q6uin24;hJBfb9`#VcJQ(j;cufO1{z
zuqhyVL;UqGK)WeskD#+z{4FidTEuF~iFAmUQ!M$mcrKMncZz$W=|U7c-UI0t$EN_a
zN9;~(kY4d*0o41%nN)l`D4vyyUvfw+p@`?O_~tk;N5prQ!_cUh&xP50;$(*l+!zxd
zp+&^Fcy<+F?u+Z_p*<x&x*B9!{3;~}X2e}5A@V@{!grX2hvFNwe{_@l;{g)~BnhX`
z=PsETfC&$YZ6}DQ<n#@wAC&M-5b=`u`~ka%B#+Xe>%)?MI?3rR*;(&E(?{Yo0yJOA
z&OmtTCz+<5h`;2mdME}+rs$;@Bxwl&Xs~1{0wGREBr|qMhDhGDLOoRCLYI8FWE(wZ
zk4l=T^75GEx%rShA$gDklnBYoN?=AxZcy|#N@Ap~PqgH%rz!ssD_O7<*ry~Z{pgI7
zY@iiqyyQ0{KocaN><9C-Wcn>I6D4zLfqq7^oy?z={QfFNaZZv;E5>9=#$O;Q5*t+*
zq)N_HB;dScbOlJ7q+<Ys$dE9p)HzeKmBNu(lGfdn|I3za(gHh2(*89jAy+bg6Q(;)
zGEo7aE=Z=Yp)X%jNvG8cBo8U}Rw&6IMXN}npbCSFl481^izOBG)GCoQ(JSMU<YkJq
zmP&3WLA^}!G*uszOCsAKa#`|xDnu$I7W%M`qf#>S8PKjsYADKHC2^wPsYdcrEgY_u
zlu_2_n&c%4E!9b`(G^@TiRnaNgXE<J7)6t$n-+)HC7U`i&>Ird1jtQ^aw!ZpOInwM
zv`D11P;QkxMcb)1$%}78q+K$%9j)6AiQN}yof00U<+>y<M!=bFN%w7F_ejPQ(bp^4
zdKjbVlLXQJuV3Q!IQs5NR$s?p1|;+8sWm8hoW3SHB&quoA|sOIRG^GXLSF>ACu!!x
zi!n*ub1*nADWTtfLNfLuCSgkAu)P7rX^Ckk6lWyg-38hM$r;+hJd`B4LVve3`+c<b
zNPDU1*F{?A28F%SIEo(clgj9gw_o~a82VhLuU<x<o3!}_C>)S(q$q>CR6yZG4=IlV
zt)9})=tX-_D%l91yrgzVFBA_+oha^eSc;FB;I@z&s3gxv+O-zMSE^J3#!veGA8^=T
z`c?-_1V}mG!9<|6=_o*hq>En%GgzAR|G7o!vSDC{NG*9Fq0+e&3<{H$&>_=sY3OGl
zN2PKP=pB<bXdRF_E<Lgib8<pzJPZ>N(igr%D^kj(w^Ee!NxE30rA}MnXpD3%#h_10
z8CxJ3Cv98^^?2zn+OZ`_yXffKX=#TiuoI=L5Z!P(BVA1?nX^*kR*WS{n(hIVbJFv)
zxJ#D4KST8|DbiWnAet(Dz8{_ErCE6xOq%pXs^v?U#?X>4Lz-;Gv}H<P=>S@mbk2Gh
z%$7#C113lM6CZuKQZ)rG^Q4V|Fn>Y%BmH*y((|j~eSvg8Rd5tams4q55k?P3FG~MD
zLf`)^mga<jTOytO2H2ORpDl$KrBWlU?#iUs=}}rPeT5$Am!%^sAyOfIbs5Z8Nd+H*
zT$M^_DN`-Qei1j0^rLwowbEa<Lh_ol`~pawG~onL>ZO<Iw`-7wQ--5adglSWa5PCb
zJcHl<y0pw2oj0UHDzmsL-Ad2=X6XWot+q(NdKH7YCEZ2u-B#(EFQDHhedBj1v`hUh
z7-5I>LMYt6Ee+TOW~X%4EJ$`q^D@!bD-BIWt551d<uiArh3`V7U+VT6Q0_XUtY}yo
zl>Ye{^oOK8s@xowPSVDHMA|-u5spgxyU}+~D*FEqKuG=XL4QKpPRZs;>E&LC+?O^}
z1Y$}$U<PwqTJR=B9!QfZXZ288P4VU3GQlAb7ugOLeA+AP+kn<Snd4_#VegmOgCOcE
z`yv4P2V|x~5O>)$Rg8Mbnl@q*JY~8i@adqecpZqB>`o%|56i|y5b>4`eE@?#vYMyC
z^p!oB2Gb7&nEtX1J|;g<_VPPu1<5L$&=)M5L)9>0G9L%+Cc|ZOHi3Io_QFZ{c1$Lu
z5Z-ZFGaa~ykX6yPH&Ql!3)oSzxMHA1%U=5mdNH#1s=+)d`<tpkV`cpm*Nc;R(>pm{
z_DMES5@cKNLH)F>aT<e2lpPO+`dQiOr|EW(EuW_Pmvgcv8fdcYHUk<dvT!A)Bvp3n
zI26yze%k`Y4B0%|L}$ug`Wb#_$)2YOZMN*M<<QHKov1}CPsZB>pDxH2F9pe$E&m71
z0$DdjLkne76o)L5?Ye-zVp##*sU@=4w$S&lFUcY)?@=l<Q+~HhcH(6iESEhnK)*uf
zOLZ)jvJdoVU6B>iL+Gk3a~(vgWuj>~S|bbW#;|K;o)pKpCKFRNOTFx7CP;&f-v`M?
zSr3sW*)WCRuFHO<_3{nbPpERj{!iw871%AZpUmjICHswDv8^&bZ7kYkK~!<pF8g~H
zn73t@o`?ILvLD|8T9+(};&Oem*<V2Kjx1ypBK@*#T20=S&3_864agFzFzg}O@0kD_
zmhGg1s1e!ALXc6})4PG<xF=)M2WQ4)v9xp>mpw&m>Pgv(w=vNBvb^`<+LY|%8z9p%
zm;b<=k)4T$!b92ewJ^9_zOw-y?vbyi3St+zg$hCT%HIma==aHo81QhvoJ~8-1M=o@
zSa6sB>jx1J`B924csk?-t3VIR3u#a6CBJ_MGKb{LHi8_M|Md(;;VnOuh&~^A<`uZ+
zE5A(%M?blz2Z+Bsu?Ug@@^vn-6e!<+8LkD%I|kueu-vBuJ{^(Ip~9pP`FK6X8!Bfl
zfxR#}>k3-oa>qV9#&lFZ`&F1YCU2zo&~f>eeds(P@7smG2>BoM-i?%(m4Zac-=n(I
zXn7gs0b=B3RPl0B{_9IH5i4J=fWj&H#W&$-oP2y0ypNYRQXN-<d@0@jr{&29&`Ol2
z(o*7#T<R#rD9*}%>xE*H{O}fNoRe>*WlpmE=qC_OkvCEFDox%P0F89{?QM|EkpD9S
zFS6wxltsyrN77H2E8kCr75Va-Qp`nxd?*N{P~JvM>SFm6ElNw|9NL0hl7B{3H0AQU
zPf+~xvV896Fi|1@j~2XDavi0fugVXpp<gXeJdc^VCJ%}MOr3l#y=3a;wk^<al1u0e
z*me2##UMB2+txs&MZPf+>bK<19|Npa{xt>E+T@9p=4qF|@EGiM$cw*%qqpUgPgDG*
zQ~uE#7+RNn3HjYE-**r$_Q<23fMTCKD+aAQa<>nm(J%L>;MrYy2Sw)x<l*$n7?P(L
zp*JjFJqHRS@?Yn|?x_4p+7aB7H}=ArG5I1o;WRFf{T^Tw@{%oJPRj3`q5a=|`MTfX
z)Rg?Us{oyr_tUjLBTuB1&I9?iR){{7=i1P>Tk-r(nBSu~`U%in6ib^SvR`pH00vzZ
zI@$}nDJrS#{D9&C<;vU@o?5g#6kB#c(o-=j4Uz{H{(k`MkU~$3G{<2@J}tex6|V?j
z$wwi40-e4JU%HL`6mPu%8Gpq<B}jnc65a5@3ZG5rJE91n6-|huu?Y&{inr-?bX1W}
zrN_q<I;v7Ut~h%HeJ2#h=qia+EPVj;QHnGQRYog5+=IRthhpG!be>eKq8ELvV(oFX
zPAM*agb~Im-lfQLyuzOz;R%YTyP=V)sG_IzdBwp!=u1<)CIvHHQGOTW%}`w543td8
z0V-L}QjAeaLbl>@+DYUnwm*heuELi#GI@$d`bxqDg(D&aF!_p+k3k9)EUE)5R9vG2
zQ$>pN^8k8Lp*{ff#fte7h?FR{E`s7EMKqNsmMRYPz?m||;-k<jSM2YHiOUMf5ELpD
zdstvrD(1z*!z+pfRIOB{=&J?us^TfSDXSIlIj9Kmn&MbInso}_qwus|QE(5;CdEQ}
zm|Rzs9frmY1?M7|Hx(PN0IgXuO7%%CimztDQk!Bwm29;uT&YI0Ls3QRxZ8@baY%M5
zW==r8OHoI2(XBW*2betyUKvQQ;{Ga%fA%SI>2|uKXz+*me#OPl@Z;T8)KL0zK=F1P
zU<MTxKSFXy5k!%#VTCXPpd*TR|AyUBMc8?W+*6#n3TMU?-=?5%Tyccbj}wYQTIWwH
zexwZaeZ?#~V>hL6l>>TO@!xNB{$WOuGlS`Vpm_H^jPRl2HJbe0%3wA0_bAs?!EYDk
z&lHH*t2EP;>{D8A!r*=-gKjlf<-;=AbyIq71M`6LZA!<vD}VnSc0H7uW?1r6F7*QQ
zpt70H3V10$rRB{b<z;L=98NyU4=JSVt2F2#<EQ+B>cIS!AJaBJKsiHs^gv~e0oXyx
z9LjtLD<9Hh=ZJFIZy+Jcc#0f`D*rhOf5VjdQ~(yP?2bd<QROaLcpg)3p|XzS%H33h
zbV4bl7j=Y^7le6oL@L##FcGD6ItGK$%IMc%>7?>Uii*T4Tj`m9N~x=YNSv}}7Zl@_
zrtO%-)5>osRi3EKK^Dd7jPf?^-Onj~sQ@Ke`7J%lQk22;gQhCYf1!0=8EApQH03Nx
zuB9vg8iJt=htjSAXr{8h1d3V8^%7`gD_a#1%~AHOL@QTWIv=8WO25@GctN?84)^6N
z8zaChP#UQMt59iO4^pIT2*(I7D*smqXNr}l_JfotrS#grq#U6DRjG1LI`qnvVOB_%
zD;?%2cyn1<ln$8+<&$(As8X5d1G`t0AJHbOO8JN<M6N0W+M!Xcw9|UKMyYRvWUcbT
zEI4{i`Kdoz4azqt;?k(R^bI7Nl#OyYdR_T;5tuiWkI+SWQ<;dMn^UuLXccC=MS0Od
zkJ($w-V9i3RbGw+TAOm!Wyo|WW4^?gZYxh*227_iJPPEl(vb@?pxj3vFdI}Ju|j=F
zIh_L!hn060!S0Ci?P!RMD$h`~?4B}&%6`U_-mNe{u6*SGSMADHI`Vd3S;TSxW=a{B
z4R5BEuM5DPQ7$P2^MO)NCpsT0*H(eKN7cCmFfOWK3ODanmC%05RrOCNEV-$&hCvRf
zc7B1GaaV1879t+1Uw9y%s=e3Y+CkO!D2&WYwWtJ`hg7?0OMF<hGmPqAd{mqNfO%h4
z+GV)!r;5A=;;*W|35@{NnOa~6sw`=M2~ycspmjv`9c2SUR0(tihpM{TVJS@Yh7N9r
zt2WS6`k1OD26K2^^<6&ZFhcbYEyN;K;vg`iRMu)(IH{6sru#2e^#(<3PO0WnminCP
z0p-k+RrB70Vv5TBS&S)F^%3P%&a3X8gWWV0iyo|*s-IoqOqMG6TQIX#fpg(ujw)g!
zBy&|>lvm1A?NPz*1=R%AQ{}6CD1=?0YVU%DLe=hVP;eBfcD2CnMb(!Jpi!c#pAU^o
zs?;YTTB>^HDq3YK=ku^st}2g$WTk4|D15r2T1juiD%JQ|w63Z)t_NDRYR^6B)u?hQ
zwpy$Dgt8~sR4JRGSEmZ6B~ZO;dOw&AsyI5v(CAR*#bYo{s%QQNxvn}yOOYF@6)kY_
zrYf)kip?s+YLFJy@hRxvQvFJGH?6A4chG86{TTyG?W!eoBC|vF4CM%Jt1eN_xKrgz
zJKQdn@FhTZtA3zU1wE>r)Yq$0(zj0fR1RNyZroA5QjWp&tA0h<gVSA=rVGpgl_~{f
zP_@PxphK#uLck2GvM4+^qDrR#%BX4=RVLh1?HWL9O!Ywl`o>i+iU2mDs(cB|NmcbY
zMDDA+WdNH}r5RvhTD5cm+@4WA;-GrU2dZJ(Cp=WGqu|+Y^;Y`Gii`RMI@7;jt)Y;k
ztNKU!ncdVye?sJdI+$X9?rI5bI6c%wPU!PgU%3i}gX$d=MfFlQHNlxf>cT(a%wcuH
zF<9_c3x7qQkNWj8p!ll$)b#%IQ%flT8LEDz1a`yJZ#DosTphgyeMi-nGhiN5-=Y%J
z<La>=;mis3e)=gR)JrKp8>xPH9jz$!RodZ3t2fa4CPw`i-To)l^Oi$BR^3kJ6{pm(
zY$(L33n(BSuWtE=&c7$9St;l|t={ee7ZcTw(X^dWEAt?FR=w*1^pn){q|i90F8CbG
zWVOl%*eU8~$@^4w{w0v}>aYQ*r>Xx(n}&4tiucgUQ17I`XQujdlFU+f?*MeR`WHJ$
zj(Q$aW)7!Z^$W8glc!#60=b}G^c6bu)$UZKRiJL8BPE6ENZKD1sgKGaa#8(+KYS`y
zSFM5MC3W9JTvw&)0;&NlQ$M*9cFWZt)A_y2YA*R(p>}))g-UhpQh;4i|7!!YO1=38
zEI6*JM`=-9t^SpAd^PHubTF+}ol4<}dUYmc>>Jb#{`d_W)xXe#qDg&_ileWq-)cqc
zhWZ4Z%(|%#`v7{)>dh8Nwy4EaDSAs?_XX5j)!)s4*{0q_;qi8L(P2P$sQ;P`l-mw<
zlPh34)yrwm)204-KVZ7mYj;DYM?Ll|{O(mx(*mJS{pqLZyQBW#2ataC?-Y~0tG-8@
zjsbOEEQU6y&ZMR0kh;!**08#nVw5B5`4jMBRBfQO_&v4rhwx%d{VTm(#?_7&sorNo
z{rnP)eo}qpD(v1@&-oc-O5MqYrD=8aG`yHme@<zp2kNC%7yMBDdp-JgYyP1i@Lo-H
z5)}4n^f5r$uX&CNR}N?*sNTn2(|7`U9-7x4g`St@V>ZYkO*Q4X4{K%|TOfn)FHm`-
zkLJK4IOD7NC;}ROnq@zu<*#{fJ4k?rMeDIZ&11A24AQK67p-7T*#>xVL^F2`Bt#=S
z2b56F%k;1h(-`TF3D-PMEBd3FqDO&pO!F9p43BG+bJ04X`Q|0s|3zpV6fla^FzCe>
zr8)5kNVMj^C!rXl3BQOjoz#?4<Rn((|2JCknx8+17YQ0S3T&U&$mpqeR+C8AT$1Jy
zS{0tta4Gbcthrx^R*EKO8!%HfQ_q2UUh~32IGU!3Ttw^7bj_Xsa5FR;bwJD1G*et5
zOY>R<K(jTg=&L(9ni&pAt|lNDUgT*u(?0Bi<~k)K^EE%vIiLcKjXttcsCl&u*hLyu
zB)q?<`MDf@#hUL@z%0@9FMu<bG#mei3!+q$@HNF>$}}1Dm@e0N?g6>1nMZR`p~;|f
zrAp1Q1lYZ*X;_F>wdOk+4Ay8i)WUqNX4~U%=9<QN3Hs_ZIVPBB)RfRpq)D^sc`&bQ
z8gkL<(HuAoFM2gM=o<umnk!V?bw}evZ!<@~W?wR<=B{QVt-uB}FH%9{pvIgA#UagU
z4onPdKBG9uh$fDzct$nb=s9;!GtUnu#x%>R5@TEwQ48-UG#lypI;r`c_Dc6P8>mco
zN;9tzLz>p?pclc6rYR13yS0D20A-Iun~?~+F4{$5P~59s9189}?d(G!`?cK<q2a1+
zr%%PWX}_nezyYnD!ffu^d+(s-p*>m-*F3cyolrQa4d{iWm)7r9fF08QK~KHI+D#OT
z^44b3{o|u;q@oyKtutLLep<&G`pmMwmPgy00PP%lg9K_{rYuU3cKaic3Dz#B1L#Mz
zt&hS)h_*-o6QSB=V!(uHH~XR$u3eUo)=}->p3pm{O`*r+ajjAS%oEz(EHERq)3m6J
z)W&>|R+RR*0J9dY-RPhb9x+;HdaIq(E~jWgtadr=WKL<PC>au`{rFK}$7=<TLO($}
zN$d2}+6s!)Bx={w)8mYG5tZhg)xJB1nMu+XQ6&7F_WP$nlC^;p2u#sF+zdxkwRyC|
zJg;598DMEzMy&%d>DqrNo|vIsQVi@&?Y(f2EbXQJu$!&*q8C_>b_?m}YESq;Ax~>L
z355&VXT1TFuMPVMpat47s=F!F&d`>tNV}hQwimS*LNLH$?ZWxMEYZF}5AsXecd6L7
zRC}?J>d(rwAHD>Qa_vu9;9l1LMAKcNbx^dsN_z@P0;j9m2+HMDYtyKHv_?BL3ktQ`
z*sW+?)9(HNUeswHqr$>^t<ewTZO}e@2zrg$`hVellXeAV+^=g_rh<7xdz#j2H?^nv
z^!{ts#?b1pRhvoY3EH$j55m)S?WSjd)}dWCh`!s}buYs2PVHR^()VaLQ$<9t_RCH9
znfkQ1J>kV&tsm_z2ei%<=^4~Ac<39^J|2j^QSD<dqjgWa(*|e8v~fM~cU-&lBRJ}q
z&_4bGnv>e-y#T$ho$7*bQ`#?*0W+=LPBp1B+HEhwwFla>r=jss+qeK|yLE4F0rno<
zeu{*<=mu!%wO98}GMM{xJAc5h<)+)v0q6s|?{lE%t~*Z;<b%4sRGR9gdx-3((;<g$
zkdi-#b=#=Wz*~1P5gI<aZMR|2SNGjTSn|`&&~C$D_x#InCP1eVLO)PvzX}sUx@x*~
zf^~nrjlLtgE3E(x(IvE^6{;I~8$N~U9+?1ixb6;xw~y=I;=#fR-A;OhM(7+b8Zgjk
zos6#h7#+(A<fJZY9y()nEq}wcQ@U^Fq7|nTP@!wQZtYW0NYMSoho#dx>mH0LQFpx`
zeP?vdn_=**E}aRHB;9=qOrO&w(MBd&7yT(DQ*<u$=ug$1q9E>hovR}j8W}ncRU~HW
zR#8!0mhLcZ;0kogtr%LN?p;cz6zRUCI=zd!Lr;NOth-C=gc98cHPE}H`#=kWrMl-=
zL9a~r{aQFvt~*H?tjoHU!|1Ef<#~Wq>dvY_uIQHRgP|&&^&|Q;z*XJHX~3@5JsS;D
zqpP5bvpSugo;UTnYu5qOp!@U!n2ow5dOI}fJl4Rc>$+DcXnjMcTL7PK>K6TszGfZA
z59V8S%m$D)-7BG(gm&E=%9?iQoM;7gTeqEl$xhvC)s%ne($!E>q+3@J2mK!1uBRY+
zN4JxXi}mYzI2h<%-9<`K4Cvl&fTclQ=_^ne(rx5}IjsA_2-ik*?^VO#sP1Fh7>w(h
z4}v+NTel8mQYRgN-hEvKRVPpBj?;}kt@}5F>OW_6jah(sp!>iDb|2~*c@TBc&$<T1
zz52XgU}>K|tQ(Wyrr%{j-vRydry=RCFQYxnK|N~<j(X|!l&CzU7fI0a(dQpP%U6H0
z4@2_P-_C<if%-uw^abgAXrCOcf0QDBj!^vo?Q+8O&(JG2Tpza|2BY+EDxndrFYQDt
zMt?s8t&{qryC4#)pLZ7ip3>(G0xeGOYllzq`j@CmKSA%22j*%0M%w5m>JL&7>Wu!G
zHz9IXANV;$lJtv?WAx|r3kG36*`dFF3FcGug;ZLes{iQ|D4y3x(559#Z(0L`>H3Zf
zFrT5Xp&&=5ey<z~S^610K(qBLUPmiO&w2|Axq8<F@HbDNNaTXvXE_w|_4!BPZ=wD*
z+L0IO*WZW2MSbEtcu}l(n4gDJCHf{hlXXdd+XLKEeefvs%k(_TBb4hucEu<z>)R-h
zSfS5%hkm7g=ry=@MgKRIvsCH-`U%)q^$af5tMyZ6DAed9lYmmIKSS4ey*{Q6%m)1y
z3X?VJ1NXz<8~POv3WeX)Pu+xQvp!S{ZmV8EOY1iM;!*Uq>z7ue)uC^vue0CQd-(#U
zQ(sN-_#VCVV~}3`m$Xgq)BjBogu8k>h5QHf_r%Z})K?qOH>B@50@sH19j~HqL?3t@
z%rSlRQ3o`}_0PTvGNFGp4P;9HEG=WF_1oWu=!|~V1Gu)^kVj+MV|a>%J{Lo85yrIN
zQ1T?0u7;%>f$e6v*N)Z!gCE74+zr1*L&U@IyAOzu;o>;@d<{$+eDX8+R6@kxaB-5(
zzXuo+=&}wpIB4A)WH|T^COFvOPvxse49o68G{o=}X@nXq&tmq%3>!|N6>d1|24{{M
zJl8?*m|^}a=sRv;@Zrn}L&rgo2t!B_pd$_TX!J!H6ch}KHdLBHVhrUQDgJWOP~C*i
zSi@$DE}k;9{06i*!%lB_5pP)10!s-7#vIJ^X@hkR`VtKb>2^9}h*|{fvxXxSq)#%e
zrlY6l3_%w3B^%xjKr6+dr>is7Fi2k^J#Toq39U3kd_KU^4Po8@b7UBpbUr52@Iffd
zXBl>-gPU!*S^@nWLstQ?a}7_>!LmF<>tkqLFzhS`Ouj+P1GB(ziiTEbsG;~tks;55
z)<r`)JuQn3OWn~bF>IqX$R)!F<w;8opB95zX1M%4nB@+`9V(@`Z14+)-xY@6D7ju~
zSQ!8>t{6tB5Ua{?!56I>!+OfM)EZXM^WvIeDi<&f2C*-gjfNk70%<bDw!!V2hU8U1
zX*R6?7kVv*J_VR<2Gz3wYd1V=gWV3pGgYwHWpJ#ZU2wPIkQiR{7*2i(&|ZVxA2NLg
z8$Flr7*^B0-ERnb6C!sFskDt8FvL<ee$em-T?s=5$5Q+h!-fGWxEVEkHv;qb3|lB;
zH)g11!0x!gXEW3%3?I>sdeXpp7Yg?c`y7-jm@>Tc3Oc6^i&)^!7-UpX{J=1WexQd2
z$p;wkZevXb`t}&D17NxsW9hZ9*SM+>WS>!A3orH?hrH0|YJ8fi9Nmm{v@JSd+&Bz%
zcjN0)IOAd5ECIBq(WwN?gGPpw)}LO+g$ppkL&i`Ed^>D>7zssh<6I6zeT<<e!1Oh~
zMu7-F<GU-M;BWluWiSJb6}Qj|G-@d*8e}Y@L|CwK$7wio#OVDvL_&-KZ^6S*V-J<*
zhZ&102@`JopbCy2HD*my{n;_&w-+IL+_;j`+9!;)d(jzT6w+rmB8|iU1Bo(jY5;b$
zk^42UV~i=;ASaFO<XWt8VuWrS<30*2#u-1S*M7Wlp#_tWVBDnxIc;>V1azX&l^zsl
zjO>SS=B&~C4%J^L8ULW#xO2v}KLIV-cy%_gQ;cUGflR7#Ng$j#Z_K7ZM4FLD%d2$b
z!eUs;Fvfoi>`ddmUNEza4^M%aZR9LNE5{i51PtaHeLsQsdB#$Td|WWjo{iDx8)xWr
zT!C@U%V0VRjfW_QRAelrTCt19i;n@O*yv?|`4VHx`_R8+Or@Pnsqw9Mp;2aZqkVF@
zkwvlo%f^@K3al{l=yg_UyyXY%D@N-puvBe)BOJ^cBX1R2wMNelw5}OfQYCPmaW<`T
z>K(>sR={9`aSuKE8;$-{P~2qv_j`0+H?k-dd&BtDF?e{>=)pp(+1M~23N6OJ(%{oA
z<1`ySwHjZf)m@vhw+(&m#*d{??=X4>qVKlRLa*OWqs0w<UB)dMw7QMae?g(g=r~V{
z>0YDXw=mIX{Ptfc-Z8!q2}}LPFscH$Yy9CGhzuBKC;&NV9FBzKka3(1=CJV_I!HHS
zET<RlsBsHD?(P|H(~f-1xbrYX#*HhULf?c@M;nSsqh~YJ?;FdhmVC;naL@{S+V~wE
zxtlTWrtiZ(FqYEcq=&{cw}HLeG$sObk7@D;Owc~lValoOH>D`RbTv6sWssZ6A16tj
z4wx2r1I*oYm`Zp(Op~kOucs;GNr)UY-8>Gamnn{J=0m3R^#D6;io4?g*W2_ng?4>R
zR;qCIH7!xVML*LV3NreeVt>ax2bfM!oo%2=P3iC;(|jI8f=!Pv!<dekve&~zh^cT2
ztx%KV97vdHAH{vbO^<B@Icln~LgAQcSpqB^H{~Pp?{vbn<U^`Ii!jxZex!-}DSV4E
zJxQ6>Xj8fjFfpdjhVUDnG%2nFCf1~-!n0GR&*~u=XL|fgI1_KWK%ZVnFnQ3$cG~m|
zJxLQy2WZc8#`FWlx6Yd0O@T<Vi9?5MQcQysgHAOiwbTCZylH~`PBV4xfs5&;ZxR8M
zVLCVu8kwdsdNO616f{rSCe63d&oQxQqm^rV2KjrZd{Z6WV+E${NsvO*<r(-?Y<ik%
zG)qihq(bD9sgf@Fa#PS0)GwRTDFRqw3Z-3@qssKC9i3NARaEv<ZTj?8kS5b&Ity~$
z^g$dnZkTSR0PUu!kB*x(n=&c#(PGklMK^%SjSAyiP2X-rtIcGlRbjiy*aDFblN&wm
zZkv9gTIEhtr~#zQ<S2khw`mWZn(T3yKB5h0uW4fuI{Qp^I%a*x<a!<Y{iX+$KDlf9
zhqAT<rhyTdA2hYlVX7e$gQ~lRO$}5hJ7RkNRiKQTUbza%d#1A6V2+uNsev+Xil-Is
zl<6J15T{L3#Sob>9h1S|2POxTY7!or7NtRBw|UoYfbKCLDnzG?SrG)ET+LhPb>wCi
zy$8hu=9lQMayKuy2I66^p-{G`Is6frKWKiPqQ+ik*|#uw*u3B~5O4EJI)3kCem@UC
zudli7G*JA^Q}wXtZ@%WpLT7;a!*Ey%G=~&ICdeHA20(+&uWtbfF~2JWcBpwG0UBZE
zqEvu}o4d>5(^2zMs^~p#4tWmhC(NJH_9nvoK5a3h%w6#qS+w~cr7dI3ztFoa)-0xN
z;3;$EKFmy<*<}so|KiPdI+mVbzT1t~8T097Xq`11`hk{Y-bL&6bLPt$Fq6%TRS-!r
zzeTr7s`&-V{hl|c_CPYtykY>YO!KM^j4;dmd>bUQ&1V)uGRJ&y6G*Q4%{Vag%w>9b
zaly=4OZmTi^Jdz&7MNF1T)oiD`~jUs=9N7d+C_5|6B@;4S9;%<n7uzm-zD?+?NBH+
zi@(Rv%FHPg0xvgP)?rF2&EHJJi!0``R47!L*S-qoRr7T-TGi%YHPma&RUw$zTJslK
z^!?9k=H+_m*O@z4!^L{DoEC`<=1+cvXruY3H1u6JKe8OI-7wE91i5Mc>~D}}^Q?J*
zX)(9OL*$lO(}7m2`5c`WZZoH~!25Qy6V(iNm>Z-pf7{$V1ZJmMKo!$nW=1sh9Np&K
zZ-Dlg-`@ppueqG|%YEhxD<FEud@dY){bo5O1@D^qKJaP4{1ye&ht2yNKt{~JE1@uI
zb`5~}ar2L~X`e7RHee8wX6`bO`{vjzkSX)ibXiTC*V9KO9-4or&k*i*SY~~W&OMgb
zXJbnDTIAn=yU#M4Ru=m$J>-n5#h0!tH_JH|S_dpg_;A$SlGp_p4~x&QQ1G-oPw%0F
zmQGq6dRey9aXfF!TNIr1u>|%*!PnBx2Jy4hOu!3&OB+S-0xS;mcEAK$E>m4{kfolk
zxnPTh*3CyON9kb_Vrg6jjZjPT9*Bflys7Rx+_J-$ZUBo`0QF;*m`Tj@af^076i!&8
zs3<1FVq{}Tk(PhxdkQBl2g{%yYk7=TE2k`TMj;YsiFHu$EZ*`)3G@>zw<u<D+A>7z
zn?y?!C7aJ!5(7ZaT2jwIB*`*{=%&*-i})7Mk}c2Ewl&2vbrU4jGDWeO^On<;kxjEq
z(e5|hvU4ufGc5m5RxZ<0zZ({^EWgp}D%;|8knX=6%UW7l<XSd_Krzpf_B_Z1%VXzZ
zFyCU5VDtr+!lyCNLJMahm_?Ra4fHNrT4^g$Y>C&x-xAA7S~Xm<Xy1pyQp^PgT4qVR
z0a9+^2_bpevX|B;6_&O<Sg5od@S^&&E0)$=fL2+Y>D7MK@+&=4sx9j&r&41{q33d~
zC6k^v*DT8y!<jnEXB8M|y~V8ntp-aRMduqW+RxBxvK%HyuUp0_OMJs3p$E-P%T@}{
zHCujZ1+&F+ejhB{vaIf;`s-GUx*vYGSt=+?)@~`JFDZ0dj#CLnm&N;e^mSWSeFJ8X
zWix&GsMk_V-&N?d>?j849gF%cjJMzN%og<BwItSKpaYhiuVHD>vV8}JG-SC>=h=oW
zDk=aQu{gaA=BVW@%5yr#Et?iYbi(pl4>~6;;%c~m-y$dTQ<lGJYdUQ?MMW1gmhDuz
z^1yO&B_tnO?mr8kc3a(6KxB{gO$x5KSUVCSve#<yLTjJ({dDNLSxc6KdBA!y0t)Wd
zwKQB0tL!i=csi_gBFG%H*7M+nm$jW<QirUoze4M<b-@dO@wVEf@X5z&d<K?$t(A1l
z#n1ZweYE_ogA`p1uzFJjFwlByE=&YjcN@_cY<;HzeMhXRZ$Tl%`XU7jLapNYuoq^X
zp*3Q-)zM9BuA|oM1#s$wH8mcc5!N1hltx;25n7aWaV12et>bqvUolo+e|UJ(`Yf%!
zW39*N{ySy;<Q0g-S$Cg>dc5^HIhYAn0X;-cTg5U+CR*z#N^sVCmv%=<)|IriJZBwu
z(CRMPx|0qGrC2}rgGQ?LF5MO9tvR(IX;#B_fTmlo&IU||^|w;^lxgi`!(fhe%@`cb
zwNBQ8nP<I7vtD3Tt3e8_^C*;6WNoC%<%`ym9#|;0#?orP#2WVh>mqC95eH;St?w%^
zLuJ<TB3LT7&NhQwwjQNeM}>9k>p-itcF;wB#hOcd(kkoOI4E4TK2E32s;##<FkfR`
zx*6EDRy~!BT(hPxL0_F!a2#Ou*7y2>(qL`)A4D3heN<f1WZm}v=l`x-<G#gUZdea2
z1olnq4ob&0TQ7bOhg+=alyJOdEuccKR_lKh8fvq8wZmY$)zpE$4(kzDklWS~2e7-W
zhXl~;wk95c_dV7p-h^JSbsoJ;`>Y8@h}^NhM@7c{*3DNa|996qR}QoRYu4}J4qA6F
zgyN9(@7Lh)u=Q{$6i2LDs;C&Xx)Ql(tu?}nF)NcYQRCM6=Kwlk^_W3x(%MLIs{7WK
z2B1t?*9`%4+S+9TbH>UIfuRT1_4R;$Xf=!BsAIP+&mY`9HV;>by4X67Kyk0Ff=*lS
zvvt#|f4}YZAxw#@?W@-@P&eCJ21E|n7Ni5z-M0NWS{}BMXCUHfYwZL%XnT?trCzqB
z6vsGZOUs7HVcTxHp1f^!AAtDS%A3&V>#zk=yw}g>L<u;5o98Kj2G}}%Fwj8T$^XC%
zvb}f)8o{;;HNZY%llWouA+~=gY8+~tqQa&yo0i^&;kFox;2pJ9Y=Yh~+b{bddEDki
z(drYn{rlm4ge{bgI7HgM<U=IN=6L)M&}f_WF?7b*2HGKd(&iok-(qdWKLPZV%}g2h
zI9pja6yt3Xv~o<aExrqp)3)iapqFTCwu79pJx$Mqv$pTt(U)X9AC6z-oGr^4eaW`e
z2|%aVqG^$pW>e9-Jl$q+(1*=4Y+*6L&a|Z_LnF)9(+iDk+o~lPOpdL65ChG%H4i}}
z&vupeH5Y7qDK3z2tK0);3T&lo(JHj9qNQe$tv?LrFWU6+kSw+>4}*G%E%|*wU$U*G
zq+Y45fU3C5Z1QfpX3K5!K8915ZKuLODr{90z^t@gq+sq9TO(=%oT_YXv@f}8TT8!I
zwe4mh4A$5f2hmq+bHR(m>6(pW0<+F`kgB`tZE=+_*kHStguX`G%k(^NvKb>W&g(Ys
z2VmZ?MF!FL=Wp7QDRR<m`@R{Z#rB#4F5a^3qI5#5t&Rgv+iYLbQI>YweHK7FY#aVT
z>$a_twrZWWnUz56vc-F%uiMtW1+5;Ne<VbDZO@*ENT2OGo%6V3dnFUCep_$=4BfT$
zeD?_MzX99hRd9IF*7guC4%zNk!~C%A=>?eX5!)+Nm^*4~8UWfo+e=v(@0cy84>04l
zeRO1Q!dCnOL?&%7Q9kUxO>qb2r)+oWSkAP~Mq%3-+vlrc;eqYl1CV@ZTThYj-S($q
z;e}(5U5liblZ$=nE_Cj-zu^VZefBG~jCHf$N`uS+`=)n6-0gunTr3{;kEtNo({5(N
z!-MvnFMxU2K7JVL-uA!fY3XC%Mn``9?ZrRCrvUq#9{@AZUR(=ikUhx^5^VRRGL|C_
z`_irG46#qXh{1%~8&<)YF#F3dfrQ(?8i(jn`#g%$9kVAIF_;K@!zq}Ew7=&LktqA!
z0+@)l-=zyU#(p~m&YZM&Q|K<vew7xy@pjwWKuNGye}cX<_HX*YJZn#-Eku&tvHy2q
zr`V$gpr300;a#Aex8F*HOq%_QHzq3GzM0~^8TLoVA(CnToe}_9c7H0%%C^s<q(qMW
zIXeHBYyVk<NyxL8QPQcvzKCL2h4vrHFwi1<(Hl@Gv9ECkxnv){22yJO*Kq`$<@PU|
z0D9T}lsoKJ*h4y?UuplN4ro{Gv9t}Wvis3v=c?UGW$V@UH)*F>V}I9zS*x|z$iTd2
zuipVL>g}G}@Y^-m^WTF=qdkt^ZB2HZ{lb-R|APa`8+PU>^lsWuedIv1+1~gQG+OLm
zQxW<t`x=UYwcF=XGPA>eoC?No+t<gy!%q7+W%Il2QB;}GZC@{kNbmo#^d(?TUC-N1
zLV$!oAa_YZ0BzM)YprdqwOXsTcF}6JYHh9BTC26%Ma`yCt6|?a5d=X5*#uc+M|MF_
z5ENWc5m7-9P(;B67sT(K-~W3aABQ<-=AAhwx%ZwkGv{WjE3GW<Zv7@7>U~>(osA*g
z+nPZK;rh2mQ$f`ItqptO+JmjX`(sK5w!TTfW;D2Ucmm}g9&W8~hBuG4&ZNBm<E=Xl
zka@DTh9X5nTLYEgo^Cyq3$*83^(*1pi><FwWy0{*BD!0?-1>PK8b`KnQo*%XTU)4h
z$wlk_7QkG!HB`Lkrv3L{sJm;YhJko!ducW4sg1Oz-=Fr<E*%F^Z*3H99(=S*QZXif
ztvTI30<@1NVK9N(zxx0aqMiQ*xINnN{jeLVtxAX9UhN#Jv<cIirGX3Aexd^xsSSSx
zl>OSAf51g)r#wPmwAS(oTsxo@r9eGK`|q2W8Ph>+l`CXowL2*(5~uafgxy2hEUIyd
z*P8t=eWLBBA1g`Jj<<vtNm{35=qGD4%z<`TYZ-^W6z%C`^rdQd(Y7~TD}M`M8QSGp
znCDFG8{0vSYM1^2%q;D4IY_ql_C1h1lXfwMo$|GFDJ)W;eL}&nB5fNz28*@Z?!lQ7
zZ8QUerP@0bx-Zk-UkwxG+Fe?JR%mq-p?+Lj_z%!3wWsspMU~bp8ht0Uf&0N#Ywhfy
zUZWkLJlshw(*yNW+Li~fSF1JI@-R`StvUex)7pmB7*oCWI>j6sv|H%p&lzpxUqCyn
zReuMxMy>x?pfzb5dLVgDn@{_p^V%u2PQRcXO?%o)S_@i>U)ElKh_PJJ{z`GV7H$21
zXuPUT41i>-HgYcpcumWi-h)P)b}_}9u4|(WK)a!BqUpY=y<3mQcI|>~Xzb8-v_kQg
zRz#WLPHj&J(7LoHx|!V8y3K%Ow|4hsa6Q^<wcvWS6E9#8ceK^k81`N5y#WlnPy3Mt
z)bD9CsV<{m+nq}*-TT`2sXFC>b`B+v2DLv)(fLq2{whQtX-x|O^H_VE%A=lWe^Y=A
zX_FsgOi#7ZQ=#xotEX%11snw#)_(2+^_SYuEg?Cgtr-jRue3+ZVaP>y@l!Oq>gHm%
zFLu{0b*1>Hhpw#@ou0Z%A9&%Vn;8b;t@ER-kDtyq5}d!Td^?5~pwrQkFHqM^Me{+r
zed{m@!8-dFFc_knMD?G0bnB>`GE`?LN8?^yD+RQ}bj`2BLb$Fx2blYG`HmP_gzf>h
z5cvHuT|ONf*{>_5qjOQZ!6tM@>*N&FIiTBc7M{lF!e`<WIjAcw2Z`04-w&VSbW^<H
z(;=PtZvc(g6^wy;g6@5axFqU+qIi0ePS6YwlXa2DfO1$@NN*`g(f#xq^ip+8C&Gg1
zh;E=9E@tRzC!jS`_qIE*kLs3)!DZ>biUXIe`%MFp9Nq6!ah9(urmt>+&g_3tFP)|s
zeaCe7zJR47-7u927VDaPVZKCnl2&e|y1k#Hu}oJ@H~Dg1tQ$y$&g^$I9yjSmWkaz_
z7f<nw6S{A$VWL`>Q3OwGbdg?YJgGByLG+Z4qca_~y3eM-e4TDs0#dJALi?!(ov{*<
zXLMPVLOQFv_bb#Jbv&&Yn{)~q%Q@Y=N;IC=tse)G3%Xw@U~^Gt(yRpAtaA^;C@$${
z^kNb(>wGAWa7Fj}bLh9|c2i8~s;-&}z*=>ARAqHdck2W|+jLcQ9bMPS`=ED2H~b9a
zy{XH}!)MU0n?{9l9l8mdVd<8xFB|H&bzA60-mM#=ol}o)jcF3l?&wZT0ee?hNj0K<
zx^0_b{+@0uZ6*43vkIYjUst*m1|R4)(&>N!-IH8^4(bkl29bxl#dK2ekuGf+)F10^
z?*@6IyGjRXp6bpGLE)KhunrUZ9D{)53!Um0jCxq-Je$^KBf2AXka?w((C6f$pG~V^
zSN+4~aLr9$ME6$@{kxse_tc+Ff{2&?M|$FU>o3yU$46hZ2Ar>c)m}*Y>0hHYvA@27
z?sEb9P4rz2)Gwh43eqbdK|NT1kJ29@db7Dy|FTCvhOXF9ee)-f*{lDSV%TAN0Uaz0
z*V|HDZ=e49Y4{YSPor0#MC)HrVC{f@Jl$Vo^y&T(IjBGS71U$(AJsrTPX8_iKo04J
zbYG3vFZ%-q6ZFq8!Qv$Sa{68*>)+i?@t4E;rW&}IqQCPsL{s(Mv^74WugL^Vn!d9h
zBTUz?c@t<E_#Ig2XX+#9m~@u@0+pI&>klS?<mi`=#vJDAo2NiBPcQluVEOtZRLNVQ
zFQYoyLcMz)xMTWDE<h>L8{Y=BsaU^sC%h@s8)iYjTtELbNQHhZ)vX@aPoOVUr9LGJ
zidFh|Y5#aa@1=u&wSFDl&};PGw0=CPpR*KpPw7`~#U#|~3+bH}b$W(QZJpNdr?+L*
z>#Kf*PYwD9Rlq!>H{Aqx)}((pgw96&FSJ5v(tki(>T~*6w97fKKi3TX3;LCtAbL?>
z{0*?1^<gd`m-Gp=Tez&xqq^@a`VLx_wdgCafV--H{2m-_)&KP_Ft6#es6f3<Ka;+>
zH}#*mps!tjdN)uy^rnw!gMLdd>c*^h>N}sKvrB(s1;%?@U+98)?$+DRhG>sIJs0}D
z`ba9XxTAj_1P|}(y=m>!r?3A6<epwgv7LVXyR9Ji_3!rq<$?Yc3o@WTB?KAN>nL0F
zP(MV={73q7Qydf@>l@nv`b0m+1_p=pc{G@(`X{twe5Suk`G@Cv8(J{G(AUwHdRWiZ
zL*%7?3}qEY^hJqie5Jo30=A1GiXQ2%hG|MDxEc1p4HS2S-w$Z?FnmGho;(d}DU9M}
zs5wddKVQRKO6U0*I!D6`f5X{TXbdoPQGHXO!L16SL58a5a5&fy{S2cBF~l4Lx5u!N
z9+;tqSM&;zy@u!!m<TgeG@&uv5G#i>`wX7+_>C}FPr!6V8nVAd<9@>jyFj8017m6Z
z8Er`0fLT9act;BoW6*pF^9K#58o<RG_EB~$&M@I!U>`E{Q7kInaHbMmg5k>mNG2NI
zsl{9*84At8B^&-AFAf_-U&7H8!&JIwry7cO0VTr_wgp_K;o5&dIcoR>`x28l%dqxe
zSjskZ(^4eI5Ox+0=NiNu#*}B6H3;l{Lw^gnLPPyFm^fw_cM~HlGMuDWEfpL7p)0P$
z@E&anOAWK=PFiMYoCt&EhFN5=!q87kpyP(6R1;8XaG)ZOD#MT`L`)|PFDR*4ZOER7
z&Qk{KOK7b%96krG&fvBHb{h=8(zSBNaEn%|XAQ5v4}Z@Y_Eo~tdBc|Xp>V-a=?)W@
z41K>q;j*Fo0VJ;&vZFy-4BMMQt{N)NVt}oNzxyF_!|)nqA#a)tc~mCVZm2H-=`d`j
z*y=6A{6D~T8dlNbzsoRb929RG#@vFzZo_P6kRC&%Eqv-VY^TiX9m5XFN!~SVE5gk7
z86xjM<ep*h3`oDB+8LJa8@Nw_`M@ydV^|n4)KGcTpuyxzk^hH=5IXq&$nf(*pglH3
zcti1t!JEQALxybHL_al*A%o8h{Q`Wx&kYw7L0%Y4RJAZ{m_!AqFAaC7tYpMs`Wh&&
z3`t*ub1_C!j=<HpBn_OKaSR9IZj@5(l83R%lmvZm<6{bZ`WQXFhoZ01?iY;0&zMPB
z5P#$N_kbN>eDgJsKw}dve}jyl-31qHJTwHf5aX1iP~T(hoe#ZGV;&uC+-uxL55+K}
z4+Vq5jmK%#vCr81J=7zNv9xWCH2R;U^AG!t7F~deGA^OQmuTa4daKd_V;%+6V~l^(
zYb*{LYd!;sHU8}Z>^P$f)yo|+3MnfPZ}cjMi3DTzw;+ke_5oN*GLCYCGs(u<a~Q;7
z<1HtsA2H5fg}yZ7ZTfPj8%IQR{bd+0?gE=>9HH;}QR6P8<;2;>*L5(TV{CQ;Os;Wb
zJqD9!bUO@@eB*BouzSqtCj%)mT6_U#ij8$Qp-^I+V*{?#Xhl^EWyZfLqf>5NOkwp3
z<3~e)K5p!#%fH&V7fDzA{*lq*e;X6yq_aRfWn4i^^IGE@7obsRoa70#)5iKVXw(}m
zHE^cE=$DOAoH0(LI)_H1%_5K{W5!c7o-@w-0gj$G>S<MX!T9G`_}grJTY$z(#-mrj
zT{ebn2iO(kT>2)MT8#H7ka5+hd5FnxH9Gwc(Kh1|+U#66dQr;zhH<tdxSPiNbWyh(
z3qOK~9Y$M9<=!&BJPV(?jQKH`=iA0}uYq(M7hOkVkI{QF2GMIQwT9ju<6$qDziVu%
zguQ1*8)|%MGJcl{nODZa-$C5Ay>bAy=Qf*u==*FtzZx$3Z*!!3chI(Es_cu~_InGa
zByHORil}96n@Itxyltv#h#cFNH3vSGY<o&O&GK#BaSW+)+jSaf&9;UeXsq8R^aV=m
zw)4NDuXmeCc^ck4+-B#5&KKKU&cG@6?P0Vh_1><|LSOLqj2c+lzkP&aeuuW_m_t8x
zdv+YS?CpC*FkiBLzYu8E+p|?LU%UOpRERWfuW$g@y#2}shy?Gr$HGGNj;aVuP{NLX
zX8}5U$2HRyv=;36y$i!G-;qVj!rC35G@-L;M=R|puI_la3nHC6+NdtSX9uH#YXdt*
zZH0-aJ0d@X-tdkn37m0rZlw^MpYtz%Xbg1zm+qvY&L=MeGu&BdM&_OM?ody3-bwqg
z6z41}6D*}WU+;(LQRioLspdGp>j}|(=hx_dQ{eng7c>f;tr_$kbMB+?K$){6ZS%{W
z7vF(T$DQ|3c}JzQ&If%}&R^4Mu@lZSe#bzoo%43XwHoIFI^uBB`A!#2kaGp?(dwKn
zA5s3j-uZJ{XEZpA=A!kC^EEwuI_n%oWloLG<#fTHbFLnO7w4USdJBCQod2ab%0=h<
z>)_!fXTxh~yzJ~wkFhJxH-^ErIIpFcY=^VD5tv=h=~3p;z`qlM9kj;3AaFed_nHN!
zw-VveWx+{Wfwu@s+<@3Bu%Luln;@Qp%niYp3UKX$8amzFB`Dz0*e^Jmg8>Z**3&b=
zMd;oS;w$W@s-{q(<zdnPS>uPM!<jM5Gr^8c)x**_ONwZ|`Ro|9-@0z3{O5F`AG&9h
zzmM)uG#>(e=6iqP|4;i|VQ^M8r8Q?qEX5Shx%xHWK3n$^5T6GOqGhgqFLb}irGnHi
z?P=ZeRT~4{uP^)z-FacRATu8+!Pms!aP81tki8gxFWeiB$@w-CC2J<}qM*}Y7N4O7
z^LLX*!LKEAXJRx<H`3HC`=T6b-$xvQbIXU{0_YDLegWu@CJlO5ETQ|uPaliXva)tQ
z{$5pj81k#<-iDc<i>=W9OKUhV*SLG3<yWR0R(^XY9_{N+reLy6>z!0k`29!#x;KcZ
zu;`DOqwx2}4hk0kw>=&IdkSnGqr*$^6D8KY1;d>X@DUuNdRAY7c^T~b2{t4H+Fvkl
z5=Ijs*h*(E0tH!_5ZNPm?*Q~}3f`hwzb|<0do(@}ET`M2>AB!Ld^f}|1YgiX%~N>o
z9S|?!-&0`1Ti8{F$@CGbw!nn1aJ>Pp`U(Ge3>bf53&raKgoA2G1`0>c!{7noGRm68
z2#rTU4h!q(K9nNNngUCy!ahqFIwJJ`4q$1*1$5>i-6Z^)0u>p;Eg8Vh6n;yQf}_F=
zdJ|ffaF~u!XA5W25+_IKPKoARVMRCW<_TBRxugQ&3JN(D3SUt9?=fKrWmWS<J1A0C
zAd07YnnF>P9+<~O(jhogB${*wjm4rJJ0V#jGJQ#j+ftE%vN~lVV-aA=MG=KCQ6aLS
zm)0K_>DI%wO3^0*C{~Gj8~}4dv}YL<szqOa4pJkkrEC7A$Z-NhPKjPi19q+G{uXd`
zqH0R6oEE)FD~)>5n$O{OgXobXFwclQOgCZhtSFMU7>%M&%iw8~=(FX}KPU2B295Kg
zwWFbNK~zT@;ESS#F|gDuN;nI<mqh<8hKb7}3p&JhMPx^kEg}a>(Owm0%z{Fz$khvy
z*F>vnH{K>{oevAwMH<@W-4Intsjls&==)$;Y8O4FFJXsBL!qu)qUly3ouaN*z;ua@
z(+2vsNOBomw<yCB275$zXh+v8ikbq@J0c5zsNWTxr6*aRi2EIV_eAf10lj{aAEi9+
zi+-nSl?NilPDl=jPE4fy&!9*_)yoe>jg<F&B>F4}o<0_B#}`%nMD!U|{tSu!q-4oc
z(MPesekKZd27}K<A5^08g-A9QgK#km_#MR6ES?sfS!R7Np_gr@HvluoEI1ilt{G2H
z?mV+)w}Fyx=6;RV{{?3K57Am^w)rUR9y3d!%eB!gn6A+#v(2qgJZJX7X&5|j#y5go
zGy9sVFxt$L8X(zab~6;@wpo@v6nf3xp?cvvX75jcp10VWVpKlj&*I^eulO;Q5e10F
zKVxD8#aRJpGzEzd?tnMJ;?L=dixq$L12l@nJ82VCEcUqxQX>9`uHRDe7xmCD6TeHV
zzH+f_6--o!YYIS)ix*bIwMy}wtKd$ED<{IkYO%XJ8f(PKM_}osc=S@JpAsLwhQ3;{
zW&mdEO!)Z**gY+tNb&mX=F$XU-!QMw1I$hH#&Bq~o1d5f{SNaadidNjUu_T4X<pR{
zg)Z~ZDfDTX`#*z+Ps|<7(f7)H6K$|uEIz9Mn5)J6m*It*#Twf3B2+>(C;=8HL(mv#
zVKOIAgDm1`*%o54eKO{9k3}QZkcC=UQn)0{;$Amk!Y!83^LU@dcq*ugu;@(%7j3ag
z3v$5X1x3?hEcVhVrv!@y6dTL4xN{05-(s5%q`;!*F@{uVVO>n~Yw;`9ZkAYlY?_PC
zQj7aD;9Hr+lsWLb+@k15n6I$d;Q;QG#qE0_wH7>G4s{kk`9a~dMaT>^)>}m11<V<X
zvCdFGYw>siMt|AjX9e88V&QcLT#JR^Jbb!pVNn6|*DTz=gnFAr94(8lTl}`#1ehBZ
z<>A0?w<w_)b%({`3^aCH+?ocME(@0KFx?g_v!T&rQCbg?I~LPv#ouQUG!K&ZEJoA9
zqu*kh241*XPFe%+BQ2G*9^P;Hl-AKvmPPwuKH5@6q45Kjzti0^#xgaQ*8c}B*HAtt
z*79UGMB^+Yw?QVsQbQTCL`%jFBTTaVnPTzDmT#KDixkUsMvzp?<&yw&#PU)foJq5M
zNE!TeOYU2s<Xf6PfENXpr<VfynB_WpMip7+l>xKZGL6orlvvu}QE3vFS?1FNxZKh)
z1)UX^KhcK&xTT72vz3<NJJ5K-vYAqG)t0%G605PiX#m<u%W~vz#kH0_be6o%vhXQT
zPFp_y6nzbrfmBv{#_}3P6wg}r`~j}lG9?V^cPt<NuWrdwau9Bt?pZFN0CK<OTzUn?
zeaoE9&>yfIp-XMh^5GdMKC-N&mDyuU2}O`bEUy(}psy_VQeM$Tk}H9vtK^+hIO8UH
zm;)4d$utHi9+F?^jHRa}k#4$Pl8mS5^Ohtofu4`#$m<wjh)EJl)%1HL>mLAnuSDMt
z#W2aDl_2{hsV-2Akl4<H;!(**yJ0CyGE9~0ITD2meYujtAAy!9+3y7|UlRKWq(E|z
z9^!?PY4nL4lO)~1%oIuX*FdsZlHCvW5=l3$VoD_@yOW@0l64Q@e!1k$cfeIhzW)dM
z$0d~l7_5{y(5k*l^01gb3P~mHB&#LCv}vo6%%1`5lajxp(RWG`PO;iri66xR>m=#x
zA$eNT^$R5HCG0|w2FVU85;!Z_+yaqCNxz9o!kQ#+q{7p4lKoT{eqOSWe#hp5q|qCV
z7bRb+A=)f4yNt$567vp_D-y|SNVZ5W(;oS%<n33m+bX$FwH4PSLORahCdq#T=C4Z{
zm%_Chk~#EExGAYEg<iX)hc?F@k})P)|KF0lWrfe8Q?lkekS+;B<p{SWuV06yZppv2
z0PK<24*;!K^5h4Y*dvX44I-h^ph-}OlIAx8G+H|P35Iq+I!p(7W2DO|U=}NNnhD7`
z>9(U#kC*D!fh0)JSwk;TI!Z?I=Ok(Be`q}{y+<3_6e&L%!%me>-UxC;`pa5?rc2W}
z^kquN{{^(8(sLB<D3<2+!nG3V50l|jne-dVwwFsc{)y3_lnPpb*(eR5g;bODGup79
zlNS9iWF#GDi@pm|^;n8OUzECK1Fc!=k&QXIBuzVsVPBShmH@j~q-C_P?2x{G1LT%e
zKnuW5Y5kYrx}?8shQZs?<Mce}mOi8SW{>pqD{#A4n(ham?n)!RM`NFKgaPzD={S1D
zN551<XGHExcb~*qOb?_J=!D#Wbmm%g4ob7=ocTlP+(KYKlHT77?8nk|^h_U;rc$o+
zsWfpP^q)y*(sJ;*v}+I|FQgW0fi^5{rBd6M(lP$vMx+^kgL@^tN1Fi`t9@2*&DE-n
zUR~j4^%m_q+)Y-E8^C&4&7gN_dRo0q!$f&meMKucZ>#&XIr6hwK_9HYRoGNC23Yy5
zhigGrqyGgLY!z(-*Fvlo#G-MJRaOR2Lajstz}{>1bP>2PtL$A+kFolb!VU+mk}2XF
zYbA*XiL){-pu26n)#z@p30D21;7p>`YC2rfZnc)eLPJ)^CIQVwR{aYkU1i&2VbDz$
ze1zPWnfE}%Lza3Hj(W<17D3Nfwv2XTelp`P@X%j&l1^R)$ewyZGDwyp14^*0eFnz4
zNA{OV2AELUohZoclLgWluLxQ7EObW7jQ_y>{W3k>wxVTrR0n%Nc8gZ;F|y`q=sPG|
zGaU+XGSfjQ9Fje<0g0F0{S=r9vZNO<pCs#B2rgMR))kV6WgpA}Sc>fO2Ov4JS+gkr
zlPhDeW)|nkK3V|3^JQlAa4V2iP$^5H%#TWbj>(d#V7OQ|FanqoSq~)(%Vp(s=;635
zVi_bWWydzb(m7c=Re7J6eaS)cg6s`CC3sQRK^3#jvVv_uxg@(j2aT6y&Z+eN|C=(0
zcChWTfBMncAxqo^(Oa^9Yru5LGS^|Cy|T!wAa`WiPDtLBjmd@iKAC+4MDEK@(vsqV
zES8Ek2V~08nBYO#rxd(+BHOhdWJo5FLGr20c>++L$*NAl(dV)U`E>ogkS(#sD28S0
z9>V-f*(kbX0<C|boK}#v;x6=qt$%qA5@Ovs7ma(YHMc-Qtw&WrZ?E+t+IfXp*V0uH
zZhcw-?0wcx-T_#Ib!!FmBCQj;!R@yWp&d+=wQm+kv~}tNNSY2<=lloX4q7jw%Dq_Y
z3$M@`XT5+PxQDDK$uSr4)^AmzF~Pcxo)wAKQ*MAHTYqyAlW^ENldh2zYj-!Gq+0h=
z&03nZ|MwVZx^)mOh%&4<?SlDC>#n&VN3G|10xZiqejK=Lll7em7)6ft*%?sGwZ1z9
zyLr|nJ<u<(mLCD}v2msJgs+Xu50Lb;nLy=Up*Ayj!fuq!*HdUPHX<sDKVYM#9ZZZ(
zz$eg)waNB_qj5GNl*Bq@V@7W;iMMH_@}~rwgGn%-Xk+T6YS9dv=F9Lj-$wl}NP*4q
zIA|2w4ABkan2p^;z|`AZoeN71HZh+A=8TOOEiRjFX3?|plFbmk{p7NZj><l+*zBOC
zSBs5636ZNdc}d_}Z63wI!)rE{_kh`EGim}XT(=oxqJ-5Ao7&m%;-<}b9You0T9(26
z4x8xpAe}bfI0B~2X8R*Z-nO|(F}-e^V2XnG*ldr6!k|rSF8UtY1hk{?k<B}F4D+##
zM1a00Hi`w{hHN6JcIBzf9=Z&l+03v<<8zywY|8(<u-QHht;05dP{`q>%{a>6j@YC<
z1Lq<aTR_oOKK&nvxXIt7hpM~$B0Wz$<O}D5c*?oyu;eAbW(4Og|5*=7ANhSA>b~+A
zdJg%?&#gzJzx>#DnBM^T=ciykQ2yO5ivI-37kWW4SRN3C))4tWG^Kmw4=8UODtC-U
z<6e0utt!Liw*Olf$wzI4NQC@ts``qQ@202We)${@jZyNSXnPYaucsF!9FU)|g~1s4
z-d>nLD1W&cKE=s*G=n=N{}U(0OyYR?SqjZ0$g`@^nJ8~vgw7<niXvCZ@}DUKd00L%
z4JK0M7r($@j>t1<znUihZayY2T|SX=B^h#U5>PVbMgMz3%TLk1B1`^r95A!xmeCN&
zk$2JtH&?!lwo`d>cX|Oo&L3`m1kpmde=jECnA~DFK#Syi>AEkLKYthIOXR!$gnp?!
zn(nq`@>ex*=A^u95NN05wJV@dE6<`gSk%cKX>EF5UK|XO3vx@Uc(^E^OGi|i<(g7}
zU6MCP!q8>8T@B1$G08uEj4`#y`4VVcmG3S9TC2R7Dvqwnudal_Hu<7BG+vjdmjdmE
ze7`HuZpwqAq0lb>Z8k)1$>(oDW2fBVU%1^RZ+Z>bx8*h7Q0SKDFc9gHYv|$9E4L4Y
z<Q@6P6ok4fH%(MRqfeehKmBq~9yA86{qj~PG~SnMe4+6`9(NVaJd}S=0m4V}1$F3q
zEN`ub!V~$!vmitA33SZiseFi5jL+ojd@#`G@_}S1xZ0}zL!+DR6ne9eyKTc>4A;YU
zj}Alfvh6m70L|Oh<px+E+vs;;(AV}OS~mFEX1k!z-&RbI_5j<R6VMoF`!*F?1=(iP
z;gDe47#COyvDK%5?6IBqEi9$jU1BhZBX;o;V5Zwmq_ZBGcFm*VOqShg<ov}sc5M|<
z$g`6S()Cwh_s(QkDz;NAA$rNK={WQ|?20}^-z~f88Q?nYYS)14veVKha@+2M3DEDh
ztEH#QfSoVxrv~k;r$X|HU6upLQ#+2*zt8OOoX1?)Eu$K+7j{iI;l;3B-+LIuOFN59
zdjHjkUHd}VePuTufl{%H;xuJrT@~72VbD!6ork`=B6JZ91}OfB26mugHf^$^6%ADM
zc|f7xhhZO7jHVoTtfKuMMB)_bv<En(aGMCp1jXY|Xc81<m!NP|F(nbs6e)J2tQ)_-
zsOY16cZs5J3S?>&96j$(D)K|=+pS=GpkJ#vMlta^McStzrxoFJimhH@pp<2ULg9+W
zGl~uW!0uVahrfa}Dh7wp*re#E1@Ae9GX->86?Nai(QAqT3MsWIhV<~zbX~FD7aBJd
z=R?5WR0Lmv`F2I^W{?hr!VKh=;=vOrb}DAP!U($*AKd|WTXC4G%exipoS@#L5DL)P
zt2p`smhLF#wL$N$!ue}(eTwku5V@xi&V+iuVqiW#t^0~r1sWfi6u#k598gSJjxh}?
zX3)ukhl)wP;2tU1rGR;?kS~YE6U9eV%s8Yt*aDHKioy%%d#3pP5+t81<_3X#p->)&
ziD5;xH5y+kT6e;{3p1?89J(^OBbX95X7dYxxijIE8S`LFtxb>#XXc&-_CBU{F|Z?<
zrPF}6pK<*aiU*k0928@iS@gs_$o#Y%{>CyQ54a!4d{58hLrjDV^x~P?6#BH8a0-AV
zGV7^oB#D_j7xR?NtR4^b!;H@X*iB)sQrte3i83vL%n{~4s+dS)f~kNZojFHIunflN
z0~49dG=G>l%1kbXWEN8+0(LgD(Ht;2%zQg|pUXrWz~wRLD4LSb)P9W-7BF?R?JZ=c
zz5$eD%*s4S7BTX-(OArUoDHso88g!awv;KS+Nd&S?kwn+Gpk*pQNeWG0O)b1dlmXB
znN5_ysbYi_i95ltw63aVj&{IO4f7|3e@-$JRzmU=v+qNw*D?vs5UFDpQ~c#L^ZXfx
zRL{I00j`00NsFvA%*E@p{yfX1HbbM4dFBI|CT4(w?dO<-b`U+!G)@EP1*V*;DK0Xr
zI$*w;X(PLr7`+0GmzhK}h+JV-xk9~#X)}UcWtL{aL@U#?9|OF`RE`4I#vF`=<aK6e
z4#*AW!#X<ue3R*>4NW`K?Fi5gW;~r=xy208m%NjiL$TE^W)VeBZZqF~1%us8IPIW%
z7%3I{_cF8Z!QdU{uUv@SWkM*3)W^7Iz|nim{1mA7Grmn2(tW0=4bD7Z_E5}VfZ0Hw
zfoYI&lwxKdGL<aYN6hz>;(5$?(6apr)2)XyL(H0U0Da0hoPnih%y1ycbLI#=>RvDo
ze?oGY=~@c)myEs=k|RufD#rVYX-I&&3tNk-Pq8c8QwzIp>|QDpb7#-fvf0DLzD+xN
zPgZvp4tuflJi&Rho2VAVhZWPZ&X)~63!nU0o;C*ltcqSj8^9K{!BQZ*g(?7o*b+)2
z2eVb5p)Z6jJrDDH*w%E2gtDu)!^6F7pe6hbW5>3E3umX&NzHw%X>BGnBG_-Kh9#2S
z5(2WHeJ23(6~&6_DIU#^m_g$Jd!4etG3<p5C>~@(BOwyYK3on<aqNSO7|bEIc`-;l
z`|b`nlfbT_6<8v>BMKr(?3F!0NoJjXgx+B`l8WR~*aFi5prx`C-C_3#J2)FMY3x@y
zAnEKzn%N9?n*+SaWL+l#^e8)*zQ|c@_69U&vm=iolEX5zdd_7h&BO@vSi}D=LpGWo
zIR)%*8i*9Ki7`+(#$MNe6tTlp5>m|0&Y+V8C9GR6*iv@of8fg4S@cXVXFvH3q=G%W
z5#%_lUki~+)@mKbRK=!Fg}*1*gf$piH9L6(c5B!rPr#jI*SkUC6g$fo3bkyU6G$EV
zkrCuH`yb`#>e(d;n92rLeU#omcZOA_0`x4~<A$L%vO;<VS`#~x4(=Q)r0f1X`x`CE
zFR;$^Vwa1oiVpHOvlV6_m)L-9AeY&gYM8&my1Rh1u(BFhy2|Q4Kwm3+k6t2ljXm89
zLv3s&-HWcXXMHLEaD#o9YHV+^=2p;XXQzG*u7f@I17L2k9{Zu+$yQV7p^Gh`RsU@^
zgaV)4?AMV1?P32qj=o;j@?GfNVRPwZ!Ch8=17Llu)iC<*v0py`N<Vw>Ce-h<KT)Xv
z0sGTVeDh2L?4nf|+92Co0?>!-N?IX2VrQoU<}o|<I>-}trydRuu~HQ@p0dBte(D+f
zIeo95vrcqRc)>pX1d_w-<_&0k$zC4?gCpz%db{r{cI+|exp2F!fa1zslfs@G_g^_0
z-A$Z#CH(f_-n4|MC--I`WW2b<L+JG89?~k>hYP$7Y+r68eXaetjg&_8=Paq*D}YO+
zfI=YWOf^+OoSJsO!Q8|aD1>ltxuJ0ncSHuvP|o#jDD34X<w7Kk6H&q<oHJFOfy_Sc
zFACK}aQB~rL~_TYU}-<sKq1E{?nNy`qq$ohn3)6InjrMWa3?4@lEF=;ml9-hx4(s>
zM>+qQ5Xs^SFQPA-n@2I794?)%kzDQ}ZMX9{2U;WMb2sT}SirfPjPSIOGgiU3V_Xuw
zt+0rDnh3kaTqV_@lyKd304?Qypm!paapi+hDCevxx>&)jpwjK*oVObkDmj4$pjBK^
zE<{dn<M)HB=1!akSHt<W0_-GL=L3IFalg^-rj{FCVS<Zw+{-y&Pjk!1!bCkciZ*@?
z+^+ASc!n$Z1u$p17fWHOk@IkeqfMOibC7df_iu3RJf}GX?gD3^O3sVidOa*Pb25s}
zT;fc{fWFMVPrJw~Tqf<`TDSsQX<p?<rBVGuEBAFJhJB5@X$jFb?gG_YUFS}iL-YoB
zp3)yTxtnw~w{!6nI_%&!(%0h_*Rd9^b#hrcpmlM_XF%jOH$)|o-P|GiHH{u_^N#@Q
z<^G^M@g2^GLKb(q*cZ_2<No3)|8S4{_a*H1b3s%rexGY7h0Fu4a}35bz=iDq=pZ*x
z4elZLZwTx@;;Lx8kGZU3a8I~fKSOVbd+jbzo^n&)gZXFNawQBt=M+@4{ervt85)PV
zIpZMmlFOjQ{|Hz24h)%IagX-E8yCKfa=5Pil`?Q{{8U<1y7S|9!IB5xMyo<kz9<Qt
z7k_#su)X<DXz%aCdv?QwFYiZ5K|g+x5bFNCv<TP%{NmSPDUg@Y>wALu1bW5<^NY!D
z2tSwZZ+lGqqo-g)`J42~?Bz|g_z2^xhtU|$hlIkXeSBFtKqL5ZN^p_<LOPMRpZA>#
z>?q#w4Mrc$3(eu-0e&joVPg1Oc`$g8x8DqrSbozoh{W;Vw?pI*zmv+V<N34U@Hc@s
zIeNj3L_V7KVM+WfDkDthttiHMm=`;vFNL4=JM>fe;MZaI2>-4>NE&~r0Fvo^3|%T2
zyfgx6nfwR??kN9f2TWw~ew0eh=68JpXL5MA`B2E^pE^J!k6%HTLq6|ldK;|;y!?Gk
zX(3-zht^~KswOBF@%w@yTFiezq5Bd(ofamg{FZ8%FXQjhte5k)g;1#A7YZ<4$N3*A
z4pPbgF&64o{0DT!oZx$+z*Y0()sU>=Us<8?BwsQEn5X#YAbM2R@=po7j;~4q%xQif
zrAX@eZ#&V~z+Y5>JHvNBg~79YAXVlx@{gJz*~E`LMBh1n_cL(k`RUVO{sP~-2;?HK
z`4uLb`JX<9-X(sS291~bPD?m*h2KOUObg%SMeiTK$`8`bq?Px052Dxjx!WPy#?PRc
zz0NP40TVa)H^fl9$zOaEKDG0gDS_U>Z+#4yTYUF_7+NQPu^nD?@qx4ryv;ujgGe`D
zO^Np&ely*rd-*mWkUM-TmD=6q{X6OWNgqF*wi5UFE447+&+p8D;(h+`Ah-woI)WMC
zzoYx>ApZreK_2o+w84JFfBG$89`m0bgvb+qRu0@A;%!>NJ>@x1aL@Q5Dwu!HPg@4P
z7yNYE^9=K!eE^Y{d?VEom`3<<Q4oE_KVA+Q7v)YdTy#~QrEI>Na*+c#cV*dq^m!=n
z&w)>2%8!47-Eif1Rp{HNbee{~2xZ44C`2lc%tzmT<%*Xe(aMm$P&lAWPlZT~@)qqq
z4l1L^z;3Mar;9KfXHt6Tz#dY*7zO=!We-*OBq+yGjxSM}NuWu}W{SclE1%Ow_ps9I
zJ&+XTstAx&<-Ch9aYSkJ9wgJ0om8cku6#jv@C;=lEeSG}1C*)AQl|e5g>0o@D@cyg
zvj>>DO4C^SdgUpnP)$$1GJ^uP1<J8~@TpL_hl07sl-ox^v`BetI!Li{4u#%Jlq1)H
zU8;QlZP+bS4pL=vxl;Eb`YM#g=J=KzSE^}mSE)?D50NS*hKb8TX$*yhYULOf7HX6o
zCOXJ}QW@X?^QV*%H({byd5S9j>XfC<5IwC7?ZaT|mDV#r8k9?S0rZUWtuJ8ytg?&D
zH!9m{YucpzH3H<EGWjqX&ntViP`{w8Y=PuOWp6x4v+@sGa9&a}w_xG2GVNOvM6W1M
zq=U35^J!;(RoP6VZ&h~FG0bbqRde7|n{qZS4zDXU`v7`FS^Xwm4$7rj0Bu*6PK8e$
z$_-zF+*01B-F~Ms(jCrpDR0v`)!WM8b|`c!&ljMvN4b@PU%krae5!xBqdaB@OLvv7
zKcKZwd2JrZJ>|#OfYz@pp&Rmj<up6!KTxh!fea|MRq$|7xsWz@50!5(!sI<t?(o6{
zJyvcx0<b5_cjiHINO{-+9zIo;+Q9BJ<p|XoJXh}e7nm=UQYWgv9aioh544xc?~D)~
zQNBgbgICI?3y^V9t%}EZT~%$9z`3cMX;JE~TE&9%P<47h&r?-O5eP5U-&B?Et=dG{
zPaoAcFX4=@%7y}ReyTPqz4BL0rnFdq3S~%mDyimC*3%TEdXFCF!Kz>?=m=4*Y=F!j
zRbUnLLsdU41KF!`JCD9FRdXt^!&MKd@?@XtHM)QzRAE;^B2_)pAh}<4?L(+Xsho;2
zhtaAVuVWGps8&t_iBV}r!{9;HTl5W#RarfNLYztUgf5^%DqjU);#FJ9p_riBUkff#
zb-f=NNvgh`FrTctN~K$eRqVIuOHr*DgT_=<?w=4jqPlq)Xlbfp3g@S*ylF3+p?XYf
z#7x!1ClEQRYWe`sS*jg>KqOl=kAW9CDwEG`pyjIC)}b>`^&{Q&@>O5ck&gn^BuYUQ
zs=}SocuX~P6<m>OfKt}Qs(5$IdWp*BBJ@gCn=ZkbGF8)d7%W$<r7TE=>O5tsj;j{Z
ztW~OhjD?{p)!&H#t5IDo0C!TAVww-pTGijPV6aZL=O_4fTIE&=#d_5`s-|yH4NXMf
z8P)Xpuyj^+kyd_<s@)W}ZBoTjA?i8RM*6OwR|UL+r3<QMzEHoYT0t?AW|h}G_<Kn;
zgJL9?Rmxw0az(Y{IT~A3MWqyfxvJU~jKQ?3#GgZ^O_lpS8n3I8g^;<S`dR>kH&xpg
zfwZfd%7ERWS{nqITdI&V7)7UQrUqVgsZu6G;kN28s>SP8<%+@es0`O3*{j-2zrk=v
z_0M}yzpIMc46aYLHAjH!@1APy8i@9*0_ZV#UsWK1%mY;)ZTbgQo^+t%p=vf2Pdrkc
zrULfIs^33`{u9-C9+rkwt(V~MQ`K7fV4kTWX?yZq_0kjE3)L7Z^dDBOp}^-$)zc-=
z8&PH6LgOpdRje9JVi)!6^8w?k{&)rk<EHMSh^M>y@>+P|q0Xb1-+HQ1nuu#m-9HDC
z-s%slAmXFWp<9x#nwbuRerj7f7w@mG@5WpNsK-!3H&FeB911~dGkW7du=?Q@Omm3(
z&kE@6Q5O%Q(G;qFK?jTWs$)KYi(%^1cR<3`ddl(bQ{S_I`3UuYyI~?y{ljT+`_<#=
zs7aK%YzauTI`ux(52#1w!QU8l&Sx-jP%Zlh=3~`T+7ZO5hiRvHNZt4)xOnx{=`f$5
z{%Rh$M3dU;8rUTDMjBJH+CvP{!|J&LOjL^chd9_xRWJDn+!6K1XF<}`^Pj^~x;oMo
zL(5QCOF%N!y=Le;sxGE)V3vAwBv7)|8xufs)R!rJn5!O5FNVld_e=$suePs(hXrbr
zj)Dz^>Y5agW9sL0Ot(n=$PLaEtKZm<5tgXmD*$$>deLFnEmKdSm{7TTSONVCbuw+B
zj;oK;8opA!rv}(n>ZM7Tyc6n^6icdBukrw?QOontcT#=+F!WBTw-rF7RxLLLVDxqB
zHOa7hTHUn=Uev3%9f$b_^};3K&Zy5)M(C_MEgzN|)oYGGu}NL4fx<cUivw`xy!zU|
zz`me1OMt%@)e#aHY*x2Zh~|>o!4;C1)rS|N?~3}JL8!N=CsGOZRdqrmJq}yd$7h4R
zroKd}!Z!68Yq)q_ZD|JXhI;%MDBe{6OCM~z`sw?S>`-qVMB^>>ElSCBszcs@`7U)a
zy}V&S{bezH8dM*lApb-4=-F`Qk=kYp$Yb@Yg;02+cAf_^r2gtXihn*;S09J|Gj%bY
z@P4lDq@wy4>itylIjr791v@X*&uLdSqIORKOoshT2_!S^>#0y6%l^{47(|Z!BpLd0
z?N8ITH_u*CfyR9M$)RX0urH^L-!c2Av=A${Ps#>YVsCGt^=FxVJSB+A?F0XYXobB_
zhR);mi@V@OrTv>*fmUVjDg<}J-s3Pxwf$nMcB-+z`Uy;&vUjE!XRZB(95_>Ff8GWn
z_4X@1g<gaGw~dfIV}EEI8qeBG=;%|U{cMV$H`)J35fjrn`-U=fp0_WfNb3cA8Lf0L
z+M6ih*lhpPX>gb9cT-X6W&7z!n24{~7a7slV(-2ZdROhuDD2c~{{hYHHT$m&7(|=B
zVhbd%+kZ^K*c<jc>4?`&`&nxE)Mf8LiH;t7H7(bBP4-2$5WQpn_6eB3YyUlk{QK<x
zrc3Rf{TuXZlYV>mP-xt@pSS{&1NPl-0&UR##{lR*w4XH#<dOZj*P#B`UYP@tC-z!8
zD>Y<aXAQ}x_FL#Q$us-eRN?mAek2!Oys)24U-e;oQ`IS$cxnG96-bQO|Di(bD|^>Z
z0pp_aqf#|j%~*Q=xoI|_c2w-HnX?dR9-1tAjCyMR9)O6K<{K?Qy*2jqg!a*tAB3c@
z#$AoE_-P8x!Ggc$n+P-pXr@wfEl{JPwN{WuY>I?_uqK^~9YZws+W{J?NvA5wy_zz5
zS4Ws8lu`}hno;XuVxOj{1I|Qf@_Zo@sfnY<%6`p)E3g!$d7Vo6qBYEFfE~~T{R+Jp
zO)iE04r&tqSKh1nZ7d|?G|n`nLz;~?RR0pMd3GJxiJJIS%vX|T#!r}wWX*ocydBm!
z(`$HAH2Ms<c0}XT2gP*F2Xy<$(0oOCo}(JouOL~P00Ts_H3v&zH%HS<mrAb2E*}bc
znwZP5P@wsgqDO_A0m>&I)BIsW*I$t)l)}x$8qZAtEzzV0VN9i((rJJx(=ZfaD%Xsi
z2>l98dJ7tlYYwR)QmHAW=tPw!WeLzuXl_PAvRbn~28}hE)ATFICpF*D_u`c1K@Rk4
zH4<7Z)oCIScoElY3?jPz8Z<lhK;w*NhY-G<)hwVI?M96q1+SYl^;9`_PE+54#^)N}
zbXf9sc!y&3z7EwC<MeY#^*~>QLo#Jwq8vIYEFa^LO|k1ZhlX)bPjHZ2fWZ`p*nBjm
zI_zu#cf?^W?QTqI4u6VaDcvE3UObTD(C`(!$aL69&)uUA@juhdI=E5YYPLfO6<Ovu
zOqdPHTn8m3TJjva>9kS4gY-jy7CPiEhR87ouQ_O}a!}CL=Y+!%85$cMKHLqkCI^dK
zkUZzmxCUm=n;gn%U3J01a~-_7=#a1&Lu+>UngYF-9Dbr_<7J1h)1iOGVbMA$wm2kL
zz?rKKB^}^e9cupu=rxDulc3P%(A5i+>kjRQ(0IdP%^T3W=}^1?V`+Ctq?k~L1K$eo
zI~|G?fbMcI{ZI@vcgJz}(CXnhpB4e0j+tAb=;avg4A29P%N9d1#_=enbPhV^(po;&
zaSUY>;~WF1Z0C^UtpBBX9sj0%a-!qxg)pD&xTFRsM;&+30g)`ng##FGwqukH`f?o0
zT<|gFI#!t|Ad%<zSsmDXM{`>F6*$(=@%jqKqqKQA?)bYm`YIg{ybe<DxTG9t4UYDd
z_c-I|M2q*cj)4O}X>vSADYx^ENem<}I3_#7nd^>Sblu-@tft-iO~>BfAkyxbunvZ9
zId1rg;xC<!c#PpD=D3HF>rWiNp>v}{j%jU}lBbTlb@+UqIr`G=`Gw=_OCd7sm_Xr$
zmyU9(Y#4Ez`oD5_r(K!Ac6IudszKeHwl9Pi?oJ{fKzlfSz8=KWNp%CG_j1ah+`5mG
z)e6c#_&V*nj7~qN_+1!`zf<~~@H@aMumdoGPW)0>3Ubna0WR3-CtB9+adJNZ{ZOaY
z67=nL8m5wjFsJWme-Q43@=e^QoIKxwWQ0?oBYcW<s@Q<OD5qo!5Jx*LS_*|2r(fgg
z_csnY{Z3KqWT#joIuARg(+WM+=~f>ak2vk7`&GKrUyc}Prqc%686R~zR{@bMryY&p
zvYif5crM3jw+1G1o!;J$#yqFxW$-ZH=>U}i7C2=e11WT}S`V;ePW&cJLXp#5TQr(V
zoEG!YsCIfvYmgeJGRl{pbeiM@_fI+Pq<eR*Qvw}VsdM^^z89yR0%@(+;PlB#z?^X!
z6OX>LPW3hDyW~_#(Z$P7x^Q6MaB8D^j+;(9U&naco&0HI-QhIU2}f@^DL#QSohGM%
zF6ehTF<+wfwo{QFFx^g(X)xd8BvV7b*J<f@XuRW8OhpWLozyoW+2<6o173uT>bWn3
zDg1kDpEInCf1i@6Z~KJ7H+O*xT^$~RjdU8yQ!xE9efWYADzNnyJpK=yk4Z2b0cBr7
zEj@Gm1efST@E82N)a*6$Xn~NH_W6Q`NpQ75Fp**ag@SWm!M9_A&Ge-y5*&^OS1kC2
zO1DY`y(Wm13O=p}DH9xYgGjmH)G9b!A(%wB_v3;-%C}SsczO{)mB2JH5bO!ThHP|J
z3!c*Bzh3Zi-D|IzcMG=C?b<`AqPVZ8aPnB7c?q@jZXj==k2e&2g#A=J?<;(rN;v$4
z@6+SKU#Q!S#sJ}sIZy}`4p59VNI02Zq8Th)t-z2%gnm?Dv`08(ItVvHh3gSwGLIGh
zfi#HuMPUba-{xMT&u0S0UzCPOlldM|&3s_*6XlJ8ztN)kIKTbBX`imG#UG!HqB97e
zHtdDWtimK<&k+})W%=}}Futn15AOZZN@<2|v*=6c{3b>6eFQzG2F#7WVB=J<g#w53
zn8hkV#_Rw8Gi5K+;&(*U{U(gQ5}mY$LoR08Lo@`lP7cs}%xq|HbjZSk&e+6Td`K0V
z2^P6J;3ZnzrjXlB`Pxem>6ZURhkE<v($CQMSiY+flEWr><L6-AZPjnVT|e7FFUah%
z-A&=VNZa&n;9_mV{(xw*ZSD7fIcz&buTM>}T~B%IR9iiT!;jc5pmlDVt^9WkJ>Axv
z0@xY0A_B{_b)!n>qqg1jCX+nd)tew$V!O#7q{`Ohy8vi)wzDZJ*kr3*3jG$8hokeV
zZR1hEwAvn`!n$j=q2pk_&30%FNWbll42ayfU2z871KSC7nr^^$c@Vfk+dtD`@S*KA
z3V1xSHB$Edv2Dy~KtHi92!`H}tqqOrne7TwEX+T*?V?ih7q;v}v<};@TnvLRZO79B
zdBpa{eQ3P0mAwUQ7dzi_5Ldg&RQ~K{H$4EHw_WOVp!nG3(MREHH`xt(es&+f0E)j|
z|0{ejd+c`iqA}F2>vxQEuiaXzdI__;l11CMaJ!;5pe5Q(&8C^PYnw$=YPYBf8rgOg
zB8(!>&T9)sSYr47T}WQDyEX-VZFUz4^oHGsF(5bXYJUT{Ww+273Y~WA-hicNb`$R7
ztK*{JDKinEC|L-5feN$hAo~^VuT%YhoT6(s{64HWLMhNp#dnXOpRbT_hNV))qVM6;
z2}K`e_)aTMQJUqPqW=R(UQs*`gX9gx1ghn}t=N?Xk$Z~1Ut#x=qQVc(yioibPxHjQ
zpo_$pv8Ak(ALBsL6MyC`;xs040JDKYxq-|8?Jj~C89ly&natl|DTMj&D!4t&!Xpp~
zWt^yvcrQ~=iH0y{V;B0u8IL!iw~vWi0G}e5yo=C_WE7{-n8;Ys)t<z7oq|F#bM8Ei
zlc~CmsZ3!!DYjrrWmeq*%n>G^4&J9Rx%LoEXD+0HWH4_pgiI!r?+A^fjAcBAmc{r`
zU@4nfPM=*4Q}+Nq<uV1&U@)JNM?kWG3GIYlAv2$*`xrBRCi;q)dEOw!%qR3<En#NU
zUcJ=BSZ#o48MFOMz?3sQ#YQTa`I}(rI1}?OL@Sx`QGlspO3tD21miOSiq*`cFic4k
zQ<H!(U1rjD0{c4i#1{%(%*N61u#Xx49iSgFC3G<H1rxLY(8J8eW=Otde*6&XBaA8T
z6gpoqb(<mT!WI<)JAf5gLMD)%LP3cjHsMo<1hXGz05pV+7=^w)?2Hyn&|Y?g91UZC
z4FOs>Yot=EeQfBr(2HQVSb&RUr`!ZN#5PiuP&_*`7F+^5VFX}_tk^^klO)#nI$)C7
z+wt(?Fzfs|8dKPhMj(2GeVBm0H1={T?54B6A7h>}SWPO-XR_1jkmpghp$C##?3-Ia
zvRQ@_ImPU5ImTPUcGKOsoPB>RpexwMF(9YeP0N8&&ki-4AbN(K`3V%yvMH0mU1nFl
zg!@-m2Xf{ryCDVot?Y-iXYXVWje;{>?D$A<x7k%4Al<C~9z=TB^t~8UFB?h$k2~zM
zlOT85&1Alhb)$#&J@$|e3jOR2a~QhMy3VHGe|f;VB!eAb4Lz_s$WGf0n1}3M3RXX6
zKUf8gCu}OE?}pepRQ&yvUAF?{8GDcJ+0WVDCvfxyTh$0l!)(oVSbE8BtOeKzE2Ks9
zEB3+Lm@XIYt(DMo<=m1W;>PVoIlW2j&VBeCiXL1G732nTZsTAnhzk-yBbeJz0nrey
zXdBQ%Ic^<&=v?<>xE97`kAkD&+;-Zu#&cg&JS>4*Ln4Ws`Dt)TTtXitleu>f0`oAp
zh3eZ<xH$SiQ#mOe>@^+XR%gTgG%hI^o$1`GWRMK*yDM-ele^Ig*N$?TzX2_a`v}iP
z)HQe>gh(#;8~q|r9`~RNTs{{^5847wOnrr%<-eHGV;oC*MVvJ~8;d!0FI+3(=Fl5S
zO1T(H#Fm-3wTW<}oU_-1t>6;r6FtraeFGOOxf$=Gv5Na_G&CBy3fikTaeIvDJJ0={
z3B3zk+Bh^`;<`DAT;}%CRNmuENtmvFuHhY!7hEr$f*s~&cEJ2gF8O;{7~wjWpz#%F
z`ojepF1(ovp1ShvO1SUF4|Kw=JHKx^X2yfp?t(#2KA9qgUcBIY^m+4D?*Pq*|CmlM
z`0}g$q3*|b#eoapZ_?xi@>&@hgZOc)p%={0S`6qA{?Ezi+r#%X06LV<F;Tj5FMpg4
zpoQ^C|6xqw{F}6B-^V|qdszhkh9^KH`DL{2+s~g`g2pJ`Zx^tm`DIiOk;3n$Ra7c}
zXdW7m@VP&OOXGVet(wkn!EFE;a?i<7Kgz#b1-n`NtQQzkHs8L>1pOR7ya`_9^8Mkk
zl*g~U01`LJlPbk>CPh(6ckU!3Wt@H9-L?uQu1tO`gNgRZ$4>(0<%fe5jTrgxiz8?Z
zo%+^VkjSae(xJD1YA&trqo=OS23X$I7FsS=Pt`d<q-JWtLW;jPOkGA-diT`-XbGM&
zZAuH3EaTsw13~!zF9{VC{~b65|Nk>$4KFq??Zf}u_RwN&`{=#E-w}NosxE>~iXFHL
z?zV$-6TFIrfS=%{5YqmF+f;)XC>V7NIN^eAR9Uo7u*yVl={P7DrcFewAm9a!T+nWT
z&J@8P6!c3K_}v6KBKU0$rYcRadn!$b;7}lqM{u0J8l{3Q8^Dzbg6Jy8db<^atPo6C
z1+GpoigMPc1@E>2vtIC3J1jH^{A<v6NubW5{NrW8pE69q6@iK#P%VNSKbUA2+`WLl
z4#BKNAh!ffb<pn=u=K){E<puVxZf6tC&2A)!TBEa^$42izy~VKGSD|582=R9px{Xi
z)E^2mDNgoCFq_Kz9}AkPH1DNg%N)A@jR+RZ!#uwdv>$~RF2X~!#&8ubq#8yyp*Jm6
z+=a)e_|QYxL@=I0PugsG33aqL^%ky=hX`I0u@cz6!XQ74&`<aY-BbOAi@$+nfUuG>
zm4U+4d+;|%xOEChu&_3Q;y)q6I=bWS5f*)b)=*)m9mrl`Ef2IXVF#t`!-aRPA+k?s
zMP&pLLis=Fixfuu2ow8-vN>=xO1Of`-lK&=`pu^U!rR|q4r7E76n;7={Ev>CB@2J1
z6!c-??UQiksL*B`P)u3E;4Ell3oYrGTaM6?&OH_jb15EDB6OsHMyYVc0>G3B%Qiuy
zT<Glu{gcA)*Q4*0&}t7PYlUixHq;4w^iV%7{ENas^}?&pP-qa2rI2T<(3i>{t_iDX
z_0=Z)XbtqPn}i+|m~R&zxC6yb;qYhB=n{6)uI#q3h0X<Z3!Q(U&sQj!0rz`_^XUO|
zN7!eLzPrNll=*WJjoJwXZ_z`le+v=~je)^%(T8)<ctGSUhQS2U{k5==CR#+ryXm4O
zDIgglQ`-c%ktzD)Yp_Q}Z|%V3XNi7!g2qzOzUweiCdzvSgXN;)ad53dG=&0e$3=qw
zg#bm%7??jHIx`I>szswIN>L*!s02AF>Y(J{DN)ZqfUXq{wL$%&$bz1dt)hR&0;NOL
zYzjqZuP9N6)(4{BPC{cyltmG_5s`8=G`!3{2*b2_oAuIa#K+9-8*sj6iRWO#&ukg(
z)BVlNDbgEYHe)`xNV6b%1I~W4Z|J@eWoG^uDA8v6H6RDf{3xRoW9GLQA_vVjZ=^M3
zoLRwWU>`E8q%>K)Srb)BCzwT1(SM@ZvR&v)GAmNhSIEr48Hzb(f6L)-k(mVr-;SHP
zehr^anVpG;`dPET#{sk1EP}q|*UWV0P`G9G-v}D-nz_p%(q}gP1{Cg@eQ=-F|NUm?
zmjLFz*-WZqdtmmT89W^@i!(xF(9Gj|=#Q9nd<!pLnc34S*G0VX09<nwyHee%8{Xms
z*WAVbq(Q+0Kcfc|p5mV~FnVt>y9IqdVq+I1eZ^nm#J$*0+&>n?Uu?q76zhL+`z~|_
ziq}w(CP@4q6+K3XKk$Z3r1(NDxcy>XB4DD#z5T$B7H<!xxfC0Bfy9W*6CoKZzD`w^
zapHNKfO1Iu+#4f|7bnpXoCNWmop2^m{3$k;;v{h|rDQY3UtEQV>8QAcB5PUVm!F|C
zTWl`@S`H3%g5-+7q>y%=xRmOH^Tp<g7-69}^g~R-G4Vv&R~CtPQM##EyzB<-mWUJQ
zVP;CjVF3Uu69@l_#&YpSEl^I0mkVL2R=h783U%Urbfo#TNxaP$v|e0G;r#}&11&Dj
zh!0<Z%vtfZ_4o`M#fLtI{yA~=C7_)b=TMd81@Wsopj{N-xR1tWv2zW$OX4kb#Oks*
zZUOwgBECXz=xD+3%K-W|^2{LJ;_43o)*}|uDb-%FDX$QNxg)+v8T7m2)ly*J6L)?C
z{eJQ7Fo@n4o2J3U1M!da^%@Y5ZieKb*p*%q@k*TKfkqeeZ@l2BtN9^{xVo9Y9s+E4
z^R>?C^DtjG4Hi7j+o(j&+x#1<KJqc&MDINDHJ@er0<538`z0v)n}7K}Km*L9wBQ2G
zg=Wx*GB1<@CffXHB?fcA{5x7v#+VP%Wq8p14f<Nfny0OU!8r4cH$V=Vp9qGB3Ff1Z
z13J<C3pzrRWFE8wV9DkWzK7kz<{#0E(NfH_drX+;RP%}9Ks#cdQU#eR^P=zY!JaTb
zxD|>G=Iblq{&jO^0F5`ym(ptFrMcz;?50?}mkhLOi;0_nR%5X#5RKO?_EPZUhDBQl
z)bChq7!98WEFMt~_o>DDJb*p3SP@I3x14u|;;(*|ddh@{S;ptVe5~aL3e06&UZc8$
zQcJ!PcB?J#H3H_ErK|;x4p=@t2+muwgmUy@k~_3Oh?jh44KK1J^(){-zQo%eB6X4s
zT7sUIczz5$f9Y;JGzLk<6yy(<dZ6AF&p+wNZoq^}`zE7xuXG&MMTbkBe~02e>Gj9(
zJ4)KT8;a3Vo7W+7K&l*o$U&)Z1U{x%shD0<k|6zy?xcy*C!?X4B=rgfNs&sWP*0N<
z|AD?tY4ug8XG<rAz~5ZyhUMrp<w<uN(ODpEiiU|oX#(B)k4gWe0C$meIbGuQ(%Yjz
z&Pd0f!^|{E7u%xmg0!FzCYq(6(4zCQ)NePu!0dbjuxnB+eM#G;UIP$uv&y0zu!q&X
zdT?G=M<@jEV^u+A!a*jhyzLMTv6AJ3gjoenhW<XQ$xkpP`>mqrVSK<U<_Rqa@sAta
zj{leEB5@@CK}|({Kibf-<rOEU;_shQDEzdtTnMC9D?Y^EtFNS>{pWpDJ@E^F5bbMP
z*Td|uJ1p`4TG?Av|M*+n8*p!(?K?2JzBUgd{rv%LUH_OvIYML8PK<Wj`}Ba@K5ri&
zc6=X<znxpC0&VA8wAkA9<NNq~_c+SCo1Po+x2wSA71Z1W=l(^TyI}VyC<Y2PQSCsG
zz>RMI!Gc}yQ2aeaFcO8<{errwkckp3SPArK!FWm-92MO74_*}t4p20{LNNIx26amC
zx(yl|1y`^M{=aF_y@fwwg=4AIElyZ@9C(L>9A!G=g{Kd|Sc34MYj8A0IBg*sQ-x^*
zz{?b-UNgbwQK3~O*eszp)m7%>mBru+gsUh?Unu<459F9I=>hu6gsyv`P%fN00VXPh
zWfW<v7XJJX%-0BaP|?*%VFO(%^}?4_Y2F}=rpmK(!u#|TJue(O3C}MGkJ2~rqEN@v
z{I>|>zXW?#_;v&|T7|2rn(n4>t{7aq@GDw%bO=9u8~V3||F5?14v6x2{=VI(U4=tB
zB4RI5;Q+D3Mi&)Cir7y?qDBQ3RBXXsV%O-{Th!QFj2pYg-c5|L_uftH{hfVo&DXsD
z|A^spJ3BKwySHU_pV@~|x))5V@56HM(XJIx_kFs9M_E3ht#%>tIjuDv1zym@8&Lcu
zUCcYoJKDPfmOEH_z$dn6ric7q%?oocd?JPABg02B<|h>XM7((O45r2Fq6tH2&k<OY
zq0~_kg@@5Co3XUvbk0hI5wx8h^G4G7JP>dc-OP8dqv<bvpFM{5TZ(z#)4Kdnb1YqT
z8I_HrgBoI?<7r90K2D%JpJI6v>5!t5$TO2V-=np&=++IGIh(%Pf|)<josY1j<@D$U
zan$X7wj`S0d`es7&5Y-xw?)(q6mL0I!SY&l=NtIe3rC{~ZEjvi4Q*TSgNb(a_>*#{
zoj?C-zjZM3XQfp`i#m+rPpyiwEq|cWj?>3sM$VFBDDcfM>+o}@-yEo-%ToT<h}>%p
zu(15D{DF4gG`=(z)~<^5;e;fi@CY)1M{kcL<(u+KkzD@j>q+F=DP*5as`#QoQ^@JE
zC@`CRWyMyQL+0K?i|3LlJNWar`J{S2QWufgyqF~<!yRE6srwp<E6J@!D8Gj6T#F^0
zARc_mJxLbuK#bqXj#F6DA7tY*EcX=Yl#8jeq)lBEzeM)(J=Jv*#k>D~@>a#X7o_G6
zlzU57UO<))#LvOszyFD}uZy~eP*w)j%%|Q{u!v1G1|M*^Mi=n#vdyG@7z%A6(Rpar
zRx$(gaOd~Q5A(K@SrG_3$N)1EcarP#P|+^p!#CN7$S3{~=`d-)ANw33PTn_;l3%&U
zdW>jAoO+zpzli3YAmglh?Pl;pfg7ZKeQdIuWGD{<x<xwj;GD-KnIG6aAs)PqUz4Bs
zZ2yKV<wqMs>F!Nv#W1>t`|`tSIexWdJk8^w#1m*i8!UGs%{z>oGw6)Y$T^b+B=G&`
zEIRip!jJUjbS!=`&E#8=C3Fz?Y?jh#d>pQ&Prkyub#xLBQrk>h^623$wBJ@NX)8T)
z5XHCAZhZ5wkFL3b#Qk*hLKHYaM}CXt9;8F&qTKJaWj3n*gHEfA0;g!#NWTC4lU}Ta
zC0(M8j$-Cz+H?(OUZKFd>Qx%}9`mlzDWTX-_vz{unD>Alet~%p>3DuT^oR~hMR-h0
z7ohkP8eaujp3-^z5!l~!Cy$K!ho<nSWY1_<KK(qW@Aziv1+9<GT!eE(i|^33SM;)e
zfrHNKiB)?;Yjbb<EzRe#eedYcJR0^r&2*x+4|E@o1RE#yzKd0xC54s7;ulI4d*QdW
zOq#`wSugFKhOkfCl7qx^QWJh8@<?i5fW#s4%-*PTuKbj5dyCe}zt=)*cFD1)QRxYJ
za5JP{mM`~5!DsTaLWFnni_KyRIH~0F6ZP}TH>Y@8DSq5Nzlwhw5>q#n=5tZgZRK@;
zWVx?Y`3nnujDHUbRs5s$<`=78DeXI;&2JT3c}#s$ES`M+AFfWiCG>l(=kXRT$~-`Q
zt)5;+J#CiTP))mG+^=rm?HA1L;?)xy<J+$T@pr++k*KftRvxR|C)5j-_U%y@r3RBA
z9)&W5T;|i!7&4a!QGZXm@dKSHq;npspGq?D46F#}gvZw~Ifq2F#mvQIIDZPVgnVnq
zVpo%!8ED`dGAIP)*OD6-F^>@&Z`EJP-z`!1W|GaHwQeD`KcM(l(&ioJZ6mG6qAlA=
z%dMzo2T3VJmYw7s#ndh`;V{-^H|fc}f}-EZaQ>)y4;j}6b?+s$;!%DdS<mO0{iGFt
zpm~6JbVHVdr1B4_^bncFgJlnsLIc7PGL(ns9VIUZVG|r9wi#%}aYFe)-U;&Uev~^&
zmYhZ6@1%}9rv4x?XVIARBy|S1+=U|In~Cjpk@PH%C0!y-xSM>L<UK$uu8`p?k>?Ik
z%cJhQ#J3Bw+#}tmp!|LEJ3k$KKnl8|Zj6vGfm$9Bj5Xqu#6NtJSVv<zqq0p@<MYU`
zv@efm*h0&HK+bJ6YZ7wqqDAg~kh+KVXpfcIPw(;_{~>zdED9c_-ZQbJ6Ld3oH&0RM
zfD-5Fiebodg9d(&rVW;QbmyTH_|Llxuj?EdU5GH39^Q<i^XN}p(R`Y+ADI`>kqKDz
zLRvTki(Evfk3g}aAL)e?Xx?Hv)Qqf4=qg<8aMqa=ho$^PgSw;OGWypUlvqv=2cX0X
zn#{v^R?_Eo<XlDHUqVj26Z<oAuA#lSJGho^@y3$Y(L5f?w4M&@k9iyDMG0Gs(Qn&f
zY8P$$6KdIAM5nhzrH5#lL1_13I^_}?bA&FsjXXzbodlFPO|yDo@qf`aJbwHPJ@N~t
z&eCPSq1;uvp#fI(8hyua5L~Ah_+ics`gS0~O<IZ{$={;E4KVLEjm}58JM`&cwCOHg
z-4-ppM~hVc{oSWe`C0J;+SrWR9?}JTmVQK6R7KXuwBL5jdqT&qKzK!ma`*N%y|^0f
zeM8UkUi6lhE{odU(LY`x@jZ<=iYy=Klo*7MwCi-t8!4?Ths`xgy3gm#iPArJP;Qcx
zTg1<bXGrNm$TL%VauZVvrR#pkvq);FH@7r*4%)O*%Fe-B{4Ckf=~OmK*89l0O#&Xi
zx?P&ej|KNhf1bv=?3WsaqwWLJz`4kIQrcev;dkjCe<JXQ6v*SyPDyXtA?Kfxe375O
zoR-+vnE979doq@LM#8NpHn4P-e?jM@#No(tUizvjntwssE2Hj<(znkr?~?TBPvpET
z?co6|S0q2as$Z36Z$o9*q<ws_-;^TPp=r0IxqMG~Tbg<Ri@zg549eY?3SV;n^MT~^
z36l>c_hZQVNZPO*<sVC4j}iWs+FDTJAE`n+)cs5<u@pH!NO_}C_h7jJkB}WA59GIP
zhRPc_%P`qgh<U^1niY|AgzUv1g^!kdc%k)U<nbwJ{Wy8jV>D*G3|sj9iwW{p-UBDf
zNBGE@Bo`E7=5jfhABX%b7w$%hZL$wPUf3(|IfHOizP<^G59A>{%;KXm^$uDwT8*oK
zdE->aRwPbPm+V27>FV-}sCt&#=vUM^TU|92Q*+cQ{8VzT8n_OjXr6lN0hYT!tsH;`
zFH)l$qNR(~6e}uSst!}QF>0G}NL-=Dd7;vk>eEG-w@Te{3*}a;*?Y0tYt_rU5Z0-G
z&P1i_)zJfa6cYaP>fRoiTlnxDTg$Z;%xo3J4|rRba-yAWS{8+%)omxmB2&A;4e|Fk
zgPx+IPUrd5)7d`{KX)1S1bKShs*M8qo6DdH1r@oc(Axm`yU$b}zTS5rui60HN8}$)
zY$bWylL|+%xbfs=2du*cveOH-OeBq0B1|H+@1XIMiKB>O&1RA|d>x%dhVl_Un+)PJ
z(j3x_zr1xW*?AjPuOl(ru{1_J`TIY&lLGES?;+pzMmR)P^8MEdQZEdZohE&@qKy~G
z4gU1^I_Yo^jd?(7JwoD3^3aSr2h%bREN?O$*qZnMg|z%=iVE<b*VAAmOd@SZqTb2m
zr2}PWlH408JBwu2Lz`!lH~ek8b4VON6<SPQ)I`oD<P2YaR+C3F(DF58;u;iKOWyP4
zdL7xzpHBQr(i1SXnI!P|t}SHWeI)K7MSqvU<X&>+A=d6FDa%)kW8`2ETJaajjzHoW
za<u_!yFwPN#MD(1QGi8UBTgP|aGj7eRI`%aNkoBFH0BZS67*dn)_e^ec@jC-(r525
zwT`}tL|9M#_^iEw_8)>ZJ3?y~aku^o9a$OW=S$V15f(_7`FYMlsr+#)Vv#gf!g7C<
z)`eipEtZ}|VcrsHZ3UEDDuwf|{F4;l6It*;yC&9fx%6fj+PgwpT^UWAD3`8)d6Q&+
zzGa*&SLe&@6uI*ttmjmD*Tf=}|3U7F{*^LKe$SuOO_$emrvc>0JbHPC?8Bc=&XnDG
z;QTE4Q5u#zTOPu_j1g+5X1w<51AcROjasQBrhZln`Qp1tUE_xWzp7^bLYQspZ|jg{
zhkBA<)!L=5?~k0nsi~ek{`RH1aXzx*D{=YT&Q@s+{ZRgZX4#IZ!&(pi!l2XIHecR7
z@ZUW;k8h72(P0ej`kPMU%lQjx0yO9iP2%TFqog<IB^S5Xur%a~`LGsSr148{EWF90
z(^z)WY5uq(c~EW<N;lojpRK3#=2xAYIr+t&)bAFfeCtYYk=~~0J^pTcoIm4h_w^(E
z?0miq3v2%kzhRaYlz~#;x;yZ5*U9|he*W#2Xn#S~rN}dI>uID9%C3h}BgmT|%pOU$
zAHkeaB#l21!}zzUlM%;|hx}pAD)NZG%wQvV#~(0lAr1e;LU)lYe$=v`yqk~2qokAv
z!XIQ2Z=bUyu>sn9nRL2}savG3hN*|-G>;#DK}sD$xeug|7v>G4KKy)b3_XGIU#_v1
zgIDW{l(--Luqoor{3>7X-TXx571_>1dtVcKMO5>S<kUu`?+Mv}@}Ed1ztJ<8Dh-i1
zj1KWd&fzrd7`DPFI(RUaG@7>Fh83MkPjZ*!2m0Cr1y<7roiVkY##}eJia$ZC;)z=k
zdJ^fAQO7y@^a^S`Pg{Fndt9JT+N0D(IzAlpZqt1+D13*;R>RbN>UkXPdO%4&az3UV
z_~!WuohD<UZ|JH<sQxYOIT4NhURw1DVS==aq3S7;nIBF4fbZ!>xoOfRtQMA!?B0dk
z+j>UM4M0uLNgeL=z92b6vCNkw3b1OgNCH2jc}-5#MdC2JAxE!vP7#(lj{Y5qddJg3
z?&eOTefFaGbh?i3oPeG^gT(oC2!CF>fY$AXsf9F^x6>jz|0&;pub_MR{hpPyYi*QR
zMb|7qn>W%Q3G)0x&)&z>b~=bJ8awF7_gK<?T9OAq9H15X?)3y+!JiDBq?Py+n)CED
zj}yB<tMc3C7ikzjd%r|a*Fm|<wB9PryFzEQLAk5+`$7EuQ`hM1Q&{|UI-5tF;}O%h
zShauXF8*}y8Ff2=@SGmzPRI*dX)y}Eq(cLd_?oWIN6xqO_CT!KJDMGY;=`mNJd|a)
z6j~lx7D!$fvG|qJa2~?8Q~D5&d1s{G_^`Snk;lkVgu6n%$9o}-Ou<ZaElwfp2>BQO
z>>A`NaahDk`Kv@s?Z6j~Bj*Wu!dA56hTLrha=wyV_@K72$}v7^O;hGRz|?G|=MQMp
zB4teztnV`AV1FdeQOof|lX>cVJa)!2`%z7>yah$-tdH0<%he0~iP%cDOfbSKwF{s7
z)~IDSpx}D7|7A>VQa80gE13E`2L(2(A92l6wyMj5P+*%nKNL;dp*FsSN_VN=+zsBX
zzT{nbk6NCO`@L$7VkoyyUDq6mht#HfP~eza^f(FaKCZ58g@Py4qeIc)Q|jm?Vn3ST
z&Yi%9#U7%*#J7B-)~K@y<r|Ysq%^rd25m?>!Uu5ju6ZchH0U|zrd0b2rJ5z)!1|{4
z;T~h!y$|>~y{rQZ&Dc~K%WD2;0$P<>^znC0w75MStJbpI8C20KXcMxwZq^A^w^?-)
zbKAZ0MjM?@3o2@#e-9~H75Od54snB#GkY?>-_@}y4;jhXv=dGIW~l=yokq+@&dyyL
zBfZN)59IuIc?5p$8af+uyUpZXsrzruW?)9{h<QlLQyZhw9_8+$ik|JRqba=-_#?>t
z1yzvVw^=HF9#Fgv(ua^0{L0{HGBgU6>>{^t5F0Q~$sif#t5D?~DG8<zq-xEOs2)AK
zb;-^u=#rP4ACi`y6do4SyF*T5Y+SXh9z8;0@^TAuatrc9;<CGS>5-ok(xY4NPF;`_
z)_fpw!QHd6^YSAjoQ`Vzzp&7-@X%V0a7ScVWJp0?Ubp<|pNLOX2y%7qlAB}rzb^~q
z55x|oKM_A@`GJ)GKdv44ef&Q!16#0F{e1ibVqxDzgw`l5tk&6pexS2s&No@TyA?PK
z`t``kM;fl>&isOoU2+RBAsY-r!o?3WKasvLozQ@3b~=d2(<abT_<J2~MJQMZoe4V#
z-5TDdr9z_7*Cm8MTgOtcvwScR#oSm?szrBe&2ugP$(;ksDGedJ*f~mD1;F3mT1&FD
z610+RNoyXH)vcQ|F|}DP8&HZqBrv~7t;4RCp%{J{#<XIvGsU7n*Gj65)PUU%xj5_`
zNmXbaPEW$A<Hj%+9znk`!iyDZ8CJV4jq?Oj-xdi)DRdabjF!AvLNnTdz`Tpr(r_u2
z=0m_CQxNN$Mh7XZTua)8Kr5#u5Vp6X>!9*}V+8Bonm$yZ;#G^4P06D8+UcbE7GE}~
z8!a@$jY7r2zUoVx$ZYWd`qpf7MyJI((-K?7In$lN?C40^q6!Q9nTArx%T@yz{6fDs
z!8SK@AS<<#`q*G$KP`aOI7+{h;SWg-g<nq6>aZZf>Z1i$bT~398Q||rDChW{_R{<^
zGh-8+G4ZL+%!uIseRf8$MQ7=14GwL#RcBqU(jF8V{7SuGVxg@(cq~=}VNyq0c3QGo
zV|8!PuPNL=NvpCSZqY;u?2n9n*`>QQUWT4uTLYBfilG^mSm{Uf2P340YL(fh7qp@Z
zg|}!Rb9+zoRVcm9SPaIbnLMG@K2tF^gG$~MPDIK9Y?&-I^E78frKVSReSfcgrBamD
z4v=oCu<d~w%Sx6)hZ{x@uq3-Dq$D<VCgyf2NGs^oJG%f@j<f}^>t&@JD}<D=2C)Q(
zw80Y`Pc?67a>{IHzH!nt6Rg`{QP{O)X|pOhof!}`%Hn`o8B&ThF)Sv`8Q0uZ?!63Y
zCNZU@BsyH_A2KDCn$i=K!t^vW>m>WJ^)03PsxdV=!Nv2$DeZUjh)s$LbD~8#S>1)~
z#$3r?<#dOjhr0M56-ZqO8{9{VSBf=^YT`_8o*3hd%gyT0EeHE9+c!XJror2XrV#MG
zEW5#hAhQ=V_)FDT+hNiuJ0#3k{TcZ|dg5n}YmuH9;Zj<8wX}!A!Gor7@LnfPg}fX1
z>FGLYGrPTBdZR#v{Z@DA@6^h&*GysxH18u-2IZ(`XIHjMXN>IZe#s#lQ<}%R)ESRR
zvx#SNUT#uWeplVH+yYn5qN7r28UBp4RKzPEQY9lKXKDVB+L(Gm_jA%l=&;os!kV6!
zt`acyl}pLoM#u_P0^zczXfXDo)RzTZlEzXfS)D4dAx`u9>7Of-J5--+E5;(8NMk*I
zc_jaB<ljrUGcHvx6&93Lyg)i+^a8h9iVADXDhjik<vS8{cat-%=DyjTvwArToH%mU
z2go0-;C)A{%GOqpSI7$QFY$0CP4$IO>rF=1vWnc(Y>SCX4s)iq5Z}q&NO>KBGY;y(
z{-`OR@+yJZ&eTLlsxvh`HTcVfGbz6-dzU0%^Mrr)TEf}IEV%{ok4tap#BVwg?M-i#
zo*3s$$;%I}7>)xXJX=m6U-p7XSB)Cfw)wHi9p%Deta4wuGR__KY#wl;tmMgh7s@B>
z+(5^_213*(lOJn6M&75v^A^;>YEG7?TI@~J6P)pB&dkOcDK4!G6Vw2x9&Ypj|G9Eq
zkN750X$|!p1Fu7T7<fFg`a=F(`8sUbpa#P;#puVn&y%~TR_x@?xP(+^OiWk;ye(!7
zV7C{`2Q2XHrR>F?ualctpw3ZaC4DAksoUffcX+f`s>l`{kzW%_Mj8%Y*C1gtkI9*V
zZ03D=j1eLRDj~dG?X3GVIkXDSC#C@CKU}dx=r+j&^E#SL61EkaT~ev5K*A--1_$pd
zWnu49qX*N<;XC!9RiQDE9jc}H`@{Nn)@XJ+Rhe!C<3dY$z}s_n$lXSb>`-eZNRpk-
zsD=>bZ}WpQ8#TKrJ}oK68J(UQ2Kbuo00{17(^z{a{(Tgfeb^Sv8h26}+aM*4R$vPX
zlo;7REhgF-lai4b>uesCni!Rwu78bTp&78SwZ$7M_EToV*-1D9@9c+X`7k-qS^`!M
zP{zQCGFrJWzhf~dI}F5V4Dg+!*kpZGGLKZ+Dt=$g6t2GD`fh5%u5-rX;QWDVY~om@
zUJxv(Wh@29mgAwi6Lzmg1J?N{Zt!WN%?u}2TQqzUB`eVM2mG`z$m|25PO7rYD{voT
z<lRv(@$_o+cU5eb_{63V6(IStYa5mH0O*{dMX*{Yl!qQLgi5|pX1v*x)x4$@5%@05
zTou@LrLQqQCBvnq=?$fu0;h=V3m@AlHQ^zCLoDW=B55%0xXB8(swR!~e5$yqUP&mE
z8kLsnTFLk*aAd&hm&#43c0(x*lV2$%*`Kd4nvGAYu4aPX@0CUHV|T?Hss%_^i2tCZ
zdh(v#FwGg4;&3+2NOze5AC#|EPrW0Dr-nJ>qpQ1yS#@Yo9)+EqO)3kJ)n*j#jZjLn
zIjY)^YEEa<l&GW>Sf4EU!#uN5g|;TOr#GLLoQX-P&ZJa_!==XIfSwIiFPvA@9WtMO
z9RDs0$J|t-2BnDR2R)K-CJyvbBV|?)px)Equf?)`dIgINK0)S6tZixawW{*5<_Lu$
z%doRQHKD-lO6mhYU;efHJ5~*!duIfA+%N}1vY*9`ZH`vwn^nDvH6g1%x+vHmRG8yw
zGJ+#gF3;vBsWlb74dSqo)8k@<?UC^JGU|n6Lw!T3(+M8YxXjw4P2Nmvt`0WChx-;k
zcCfv=lCtsH>Sa4LSfhoot_A8{8IH`6(TD1%Hc`Pb+EfJ+ZkpWK#Uk~r4eH*|O0z%5
zs}<Z~$rY&ydpAc-pm4oBPSw5Us}@<Wl9>2XKTms+IPDGmQO#4t+UlCaS;%sAKXKJ9
z0@iQGx(#k;)}a0eToyJxS3FpymFi>-n(neGFsUl${I*}hUfsbM3?(sm22M<%e(*3_
zHnXxntLqhbx=Q*QDtyqq*u7uX->E*!z}KD37Iu59I)!_Gk~gF*w*|m=7mZ~g`GwiY
ze%!9kHS6o9n5!BdRG$#YJgk0g!U@bZ9@)gh>PtKHp_&_nK9j3L@52^%c(Pn727@k`
zJlUlS>Qp1lzp36ThMm~qj81Lr#1FMxy>#v^)j}+y|MEcyQT_3o`SZ4VPllRPt;L|l
z1+5$`9&WKS`$N?t1#l-IDXN7tHm*rj%iz$$c=3~A0LK&68$zF`zeDITQ!tc!s-A=L
zK{h+sV~j>t?{Ae+*zgpm`=ZLWF!th^di+20kf`Ku{@Ph7$mRE;3mBUa<?1yx&`Wf!
z3#kr>T4C{r&~%#$mrH1^p{%FL!D<C*j|d;B!YwNotgVos)Oo2IgzZp@F}19AO*T25
z@v$lB!#J5+B`sEi2Hv=^X9lPh*vL@LXo9{2XjPnpc=@n<3M~N>tJvJ(;S_3PH*0C7
zC11T2(^JtyZJNYe5=W%oaO8yK35`oBCf2mBma9OIn`#K$h}QZ6y(IauaWPtXN*&>_
zz-SDFkL|50Oc-Z20@-Z#X6NIya1GwsWG`6R(HsEDN!l2gG+CBGX-2ECM@iZM4cg2#
zmSi(BH2?ps(87Pi6M?NpSQ=?@gT)(_U^dUGp^tE9fYk<W**K>AXK4rAeLuHqy6~%U
zQ0gv%v!|9|gv>fdPqww67H{V3s{<ETy=I$+Yc<?i_EfEo0?tJ?2h5+L?Sm;*O`-6Y
zpX|nZ&D8E&U_vd;pS4?}<q?Q%t-8ZcHPKbRy;N(ZLCY-k!}Hc?O;mPgqc*SvbPSM_
zS@s{=bt8P$35^|eLEEJ<=M8O>RLq%?n4De{?TU?yX%dwh7aI&wceE4UNjcr~di6`n
z%FXJO(;au*u10sitCjJH&FRp)Q&Ju}*?GNOWXD}?us(2v$F%*f_MH`K99Dx_$_xDK
z0LG|TSKZjLH`;Uxr4r@RaP^2$WBuN1H8oS1GrfhbiLI85B^2JNYPiyejK&|RDJ_<J
z^?dKv#)4_6Sl{Sjj{H2kWv~)%##A$G-)*kJ^8AcVDO6$R;_QzA<MALLoPeBZh4C?|
z&Ul<*b=QmUMRwIP0%du1jKytmPgULE*F@t?=vM>R7<P|(LxU_$W9u6kW$8=rU5uHH
zNyh#Zdo3TFuxmB0FFRK&zN}h`acS_h1M*kQr>7D7`o{6-MeY9{r|#i}#xh1|*2q{B
z&i_NraQGUv!vsk-!=(9&5l$w_K5(+LW@BzcjQgl1B`3FIn%H&xG0gbAKlB-8b-*_{
zik*#}Yc%?}T!!&K8<_;{easQ86*G1-=`J5GjQ=hpY~L>9O$sv?T7%i9J;nlT$&^G<
zhqn8TkM!M3xT|FcA2QaXU~6YC4R?+hGkk>m$XnfzkrwULC#@LRovD_D9;vcA{jgPG
zGmjc;Q#iI%3u5$yu`7W^F*wz9J!vd%a!r5ed-A?5`o)NI#<89zeR)kub*8}MPnr+Z
ztSGy)d5?@sd;?N(2sBJfbT*BT53X3TH=Z8UbQV+!Ees81QHtq?&6b)T^S|0bx~HiW
zyxnLHXNx^e!B*(1s@2)`lBP2hruf^u;j3YiiES=zI%kG6)o{0zyV0bAbE7E;_E$BX
zfE8Cv;q13+rg$^_w%Zz@xg6qD+)v>0b4kPRMcRpLS!^wns&|6VTQ$)&6YH2Z;NCvk
zw8q4qH8%OX!?+o^!?d<G%_71>NOd*sxi+T9mM^=JYsQ3Y<!zqevj*p}kMZa(eL8A3
zGv6+z5)xdQDwSc?yP5V7u-{X{nLXFEPllZ(&9&IMUM8Ho#tyMqp!+YhGPCwKF*E%0
zSPIqmuJsnkfnX1iZOmhYDOiG6AI&%|64eXnRg2H`9NErbv?<T}d5<IJGi93Tav-eT
zE(J4fgDI9m-^sEKP7X&Oq2ESRQ!luZp;m-<2Tj4O)*;g?$vq<<Cx&?a%ts%XO^=!C
z>q@beV&Yu&9)HeMLjAl~5d~emVj3^O_Gqm<TXe%T3TNe3Gz2!~;)bX3eUn3<Yd`Om
zUA+bt{;GJhNe@il66kS<7Kd9ste!0MktwGXUmS4m`eJbq&h;5LbG`x#ZK@}<J!C8k
z2YM?umg!|S;oNge_J-v?<{Bn_cGiu*;$tqO!O%?HU)2vX4<^uOfKr`3FKIqQefYtH
zODhfo{49pc;nL;+tHvjQl+0A98)Ei{O0#4Os~2K!AX$^5Vw_R2v8mOALo?WlF!M$k
zf-<cEtX&QB*XYGur2%YaJ@XW+!Z(HvXr|!~<Un!k2%)vmPmgYF?jk|&XC^zC;v_ft
z^Bb$3;oo=}Be^`JNLXJLUGgcZ=AjfuTu{rp$POsA(S)ZmC9JsmXP8eISx7tcK_efC
zHJxH0x~zw_uat5uzLUAU0v^X@Pbs)!P1dEGxrzo!l`Y}mv(+5H_UD@yNRYT)wZa1?
z+1NLI&3D~k7sG)yex%ut6^%5XCh)2}E<Sg!Q#aOmwE2SsHKuA+*z|GcLJASzn|;A~
z%Z#(yMDsoZ9kx(kFo)BxH1tm6GBZ-Zu^l&@Z`^HxtlDIAH6uK=8ADi`ndW)LZBA!e
zGiPFSVmfZyL*e*C+=|BjV!lDVoX*s^gv7LT+)byX#>FSL;QRV`W)76$Kro(T%uK}1
z;pDC6Dyo%FG_{<<J$bg<T+HZds9In@q7~Ptcv79!I&9u-gX1RE!Tvd8{z%~JWOVeu
zK5wo={rR^e4rp9z3^ARva&vRK!Ls#IeYWSKd4!QK-Zeij-jKD0`mtfR%#+n16#m?k
zT~mgEFN0~#Qc-0y2W0(e^@OV{Wh2<n${PH1&}L&zADWjHW92{bFHbUBmQdKTRjtBy
znk{cB+^J!6pYDd6iGmI`A4s`xme~iJB_)szu59^UGV;k&@69EvSypJa=-&BX49|nr
zEmq<a8<Ujij7!T%bv8-MaIJ+kaV>loY1yhkrTeDRY*QVJkL;~?bZ0_3PSOdkeQw2?
z8SHQa3sqg4c`=xe#9JofcKQ)|Y`Zqg3j5w^SzA0IBqKkkSAIx#R<CY(`601+*}b^~
zksp$pncgrYzeiSfj<Wzy!a~rytQwQmtD`e1uVe3SInK1aZwmTm^~wp+9Sj3J8mIWf
zrLwXePU4?_#p6qA@zmQ|_|y*9N(Q)c`Lc%tEVE^6TEG1CF4<jO?J#n%rBaY8di?Hr
zmT}O01}?iNnPvicIW}v@`If~5HjR~hSnNW}YYOD4S{|eW7C(4jQu2VEwP`R6PBbcP
z++xeuc38bm4u@Agak+Z3(Sn1s-*ucLE1GZs9DQZ7GRHp4QZHEA#uNed&nbTF$vI0K
zV%Jab(sBw?dUeU`)uo^xYk$Eq-2{u)Ny+TxO^c?M<cnG&4vDBHsnPMl|4HfIqSph9
zyX?k0v!lB6^HSR2iDe`nbo`{*;P7EvBxwjeMp?X=?X{)4n;X{=)h(-6cUMD1sn)*;
zjNOBd$I()@6%cd|ce?xEV#C($f%~gTO{}F@W23c+(U{*kuUA3vR}MDaZk=EPsiVyc
z{12PU^Py#fd24VJT_eDnL7|){Ee5*+t$ENUMhj(0C9KoDi-ls(j*kutclE3=e!}%O
z%v#3X=yc-l7Ux80mZJDTgC|Cd8kZau-6W0$Mq9tv*q%gdYa5(ujJud-Hj@`?l4;G+
zzFaWHr2Dv?b+HTsTPxLJ(?-dSEy%WhO`zx{9wUK6b7S{9TI(q$J_wxY_#gsK{-^~&
zgKw?tVM8sG7sLnPF6~k+lZ8cfwT>WA`J5EO_II-$#<SM6I6T*Bk`WhNGgSY{U=w>;
zhkJc_a3gwB^eAft{B;eNmIY<75yq9FUwxi`9UU#jU3>ZyqpaKQ@GJ~xykQx(%5239
z>yyvNmcp_7b)mJH5$27gA*|F2tD6KVyNtfDBT25us;;(<bAvXwZ0*p=OpA?*h4l|5
ze|C1O^@#%4!>s;R96OGGo#qR>t?v~)2U<T#DhtO`sXIG!z<R*z^JKR(j|RY4tJMwG
zS*<cVf6-c~fLd3p#!|0aaSESVhc1MI-FO;a<EFK!ID}l3s<Y#ttkwXRhETZrlDDIu
ztdcM|(N*<h5B+UNHJDWb4*&*~wmsHN`plxwKI<ymnt8dri_eY#<lU5gSyFvlnhY0i
z;0E<lf#kvdjIlL$ZMVg2QYqOMqrt%ssvFyyVXH(TcrqTS-^{cH$#8PIRb^G%*jgCf
z)A7W{nWq2N3mo3j7G{PTrH$?|Z?VOU?t!ricn4a&*!5i76BW*uRf1q>Nu?NUK56!Y
zb!*LT%+$x$i|R+*F!7=}oPV8x5L{l7+37;t85@|Aw6A~>b1`;iq-}I@xcrWW!lXsE
z-f*X)RuPtZ;-i|tA8o(u4z=hP50}_>;vr*9DqQ<n3V_4OQZaULsV$%Sqtorg@g1KU
z7yQ4E`q1vO+&0e&aDduie}K^gW>&XYnC~XrassrCtsFbeY|jbQ!#A))g%!A5nC{Dy
z*vHMbxpuw7gY|DUkkKQyDYDnUPYYtZ<cr4z257oe3S{d}*tQv=@e>^WSG?7_tlL?e
zmjuZp&Hilg1=~MLu`kZk5|dq1M$c=u2a*kE+el|D`ZBzsA#0_{hn=`(`_TwdJ++eX
zY&Gs*M?AKjQv7Q<!m2tVLqjVCI~>)*t2u)4(Q8;}4M!OCdTxu4T!4@6qTGz5=mZkw
z78+&KXq=ld%4Q2j`sbfm{O~W29eJ9w$Imh5oBROYFKr>DCX0J%i!qV~Fy^DJI7Xnl
ze(VSsv-R%}Pv5{a#)%lX%3_A9h8O=|zJk#-pMN+%-fPhLC*kK}h7bb=Vd?2QdKynZ
z@ToDp_-IQEc4T+Rip=U5nH3sZqoyM)D>NdkM$PQ7?CRN$4q=gzHCVe(wkRV+Z&keA
z{`=?#qMm4;uv&BTa@RBd_btIT%`LRrP%O(l)nFLS5icQ^<v877z~}x3GZ+l`?jeJD
ziosA?rvo**)#i6B4HN@j>k7m-sp#oMflUQw2y87dOJFB~coj;Q%NN*BAYOFQ=_3S=
z6*$?2MFzA>XP7JSM}f-)t`&$eeLCM(fx87B5O_@BDS_t%UJ-~98oK-gfq(0W=DiXG
zjHA~XB>dWWi<ksr*qNU87Fb+hDS;IPV$ibA7cQ`t!1@9))=1CCzz7|iaV)}uG6kWn
zK>SlbIztzM7!0bXdkY*OaEQQB0`aDU&No%yOo13uqtllNTq$rpViB(?MoH-m+Xe0s
zcu3$0fu{vt5O_`C9f6MoJ`;%X!Mfg00{QcIUY<pu2gV`k1boq&jwJ+^5m-rJh`{Os
z@da5rf0V!kfhhtr1mewqoe%F_=-5XfzO+bBkD)Nq!|qlzO{9MmxI*B1fp`^H=ie*v
zw7}Z}@tuQuKHg~25hEdWOc#hZP4)CpffEJdy%kO`G8`2I{L_g#BfbPe$3_A(1$GpO
z7rXWR@d9TF{7E3*=G60d3p_6Hg21~1@f`ukhl2p`l<ES#1dbCpQ{YB{7#61U{V5RN
zIHIR9rb|b>f1qP&fvEy}3dA>+>G?AR;tOjG6igO3&!VG(bWY%HfzJdQFwlqh9=yG;
zV}L-s;;5%11V#x=7RUpHxLjv}_<jLBJyhUC7uGh+5rpLe_Xxx{z~}-PxTzzCn(2tI
z_|UNhBn7(p7U66C_2l;gXA4{?5Q9hc{6hl&63AB?Zr@XZ9|ab}6@=3<x>iSg@s5tQ
z1jY-*NMufLWoR!5{Avmp#9&(;M+wB(I6b{k;97wP1Y#_wo{x9FbUY{U3bc*D`e7uQ
zPR855I{FC2;8#5zDzL6VyeY5KGX-`Oi1*BN`ga2Hg?xH?hCm(z$IZu!tU6wFVQIs2
zL3k_BU~w_10<ADN5$(jc@9A>&1>)6KJ&m`fbo@pj-ow_@g9VNkI7=W#;OY5zJ6=b;
zq_5*~f%t|vJ$*;ua~BpFh}D(hC9tBv>H?z$HWk=LU>AXX1P&KCN8loX%LJ|wxKZF1
z9dR)45`_H%j|sdi@QJ{80*yA8!QKK(3k(rhM_{7B<^r<?_7FITBVW<J7X%QvSm1hr
zrvzRR_*9_T&1Fb&fsq1J1ZHsbFc><DbfLgO9P$5g_`klQ%@P^QM8+>7y;r1<iS#9b
z*E!<%_qRwZ?k+>j9C1AQi*yBn)df9Tq??I!D|dALc<23AWc1{SbK^jPV+4JMNH26B
z<>u~&|GP6ccYAJVsWp7ILxBSvvE(-#(K25?>7aE9Y;JvfK6ha~8rsV!N8Q~Feo%{l
z#G4F;SjgfZZz9zWWAGyhh1Cu16^T3i)zDs^?1B%jRQW`Ec@=|-4eQ+@H4#PZZid$;
z=$~jWjjtax7~aD|PF?P8Ff@SO33gAom}s}t_x|u0CGjtd84Oij^eT;zUL^qPHA1?N
zkHK)9i+aL9PRB@q2}sv&`Wg)QUT)~x)Lxokqz=;5aitB0*%Vf!pp})OT4NNiP|jee
z=2Cl<i`S_N-*I{d(nG$W7gUAgoIV`srN5xBstQ3(kiHb@6I}FF&FmheD&%r<M0tau
z*%#~u)nEswk3hQQvRY@a25w169$f*yM;H6Rrl=(p+HvwfNWS9Y-qu(rui@n1D;W%d
zUnt)g1|K>75z>W?y7DkcPDZkOWrN||7wqrDU>?%7yGXBU7cCV5k2$Y5##Wbfm8dt%
zz<8+F6nP_Xb1}3XfyPa+RTE$W(v(g3Qibkc=pA?#E+btnGn*K`i-bnav9-@awG?Ds
z_&YHae4)0$7rx_kZ;T6X^REgI;t$7>toB55R}-vgj2iqQs2P$jUL=N(CNOhSS;$3_
zavm=tdVisGTL|pn^e5;f)^pLvC1a~Oz%3QYRqqkQl7Gvx;~T4>9jE_+bYa`J6l4#F
zHAq(D9}vSR>Z(NqeB_+R(CftT72ZYl_N@WQX~<dSF)>8q(PtxjX<DZy%;U5Uc*V+H
zhVw~iZf$ssB&FwbVyNOWYg-1EQy=Q3Bj?-~#1KSbRx{*m027d;Y<)%k+c#t2GN<1|
zdcYSNVxU?Ek|lJ0zjK*oZGwtp;X6(qg5)tSayQ<2;@~)vRr6b7n1=Ogg5||QP;=y*
z|DNCw(}z+wZdpUf<>aFucy(vu*GM}yf*nXwze2xy@JqPg9ILwW9k^v8+tYV8!$Cep
zctVp*97*FEK|4<W^}Wpy;VOR)(v^ppUI6PeajcJ1-3)c%9RGN+k=>B2m;L_$)ioU3

delta 139706
zcmZU*2Urx>7dAdKyR%cb@7f#2-h1p_V~?@-SW?v3V=O7IVi!><f`SDUv4e^t(o_Ug
zY>1*DASxC_6jTrtmG3=E^8f#y@AJ{QbJ}~(y)$#mxp)1X(98QouWfa>zP(P??a$S!
zI>@Vcv)jx!U8YqTTzyXEL469D->pB{aj(Ih*KAE4uVAhQ#}Dwj%hjtVLR-EqLMjaU
z#;N&z(S;xQ0p%rM%bD}yw=w-!#(34!q&d3k8HQ(AErUN*wOWO#=~^x^={HzLCD#A^
z5m{Zk)(WE?=Fl))(<<E{5?OI+ZHW;%{`oQuqn&bEVz^FK$C88-eh3#CQOmoq5~H2z
zBQV_eRTq*(D|BeXF`~$CjuIJ%C<@^Z1g4snpEYkW2{~D0w6$s}jHZgUHT0`{<DzBj
z$c(0*Z7}Zj2Z(VppJg<yY(Ent92bc$_wi45$Azt+U;IZ4jKQS6Uyo%NWz@hCj5ggI
z2NA=*a$M#a?E@#JW!rm!$Z!%Odw(g2Oedi-+MntOj5bR{fI!NbOGqOK>Dj+XA>&y_
z`}|*^@0);l@h{LO6NudZfZTR)jP|9b6#xvPw!pEAkou2k&1m0NAc1JZXx~*JG1``c
z(R}YU%b`}Ijz;@Yy2HU>Xdk#PtL3bOGIS(}&rU+Cj3VNTlMvam8+a;TorKEz+yPPU
zBuxCkej`x*T5%3k$j0}B5eo`L6~6bV5e!#B)Zk8c!h>LIk<&W5_CILxByw=SlGS<c
z;uxNN58?!?i-nqw)o2(dnXTD>C_)e_5ExF^<{rH$gstUtSD+}d^sGcq_x&;1!N^XL
z%IQ)dQk)_ar^`qc7}Y7Uak@-M^iD|?PB*~DGX|%m2B&)tiIJtpUWe1=f6y@|)`}o{
zauv^?LUq0mV;PAaK1J)KA*V;E(V+hS`@)d1lSY*EWWM>2uFe?u?U5NXdk9=hmGSHv
zNO(MjiEPDV<NVyT%%loJ%Mb50f|*=Fh+O&yEi<KpP`L%Wb<B?ygo*Fp$1#GLT0z+u
z<MJCaGmUKlWJ@Chr^h$Rg~keuiTl^Z^mY<st{}9WW`fLEDhQFg{!GVMD+rYz*mneD
zs~}AL_aN*QgpHdK$uX5Gh$`ID)-qGsQ9;$<d-Wf|RN>4u;j|7T(bJ;af7?b+u^1yZ
zD@;{xD}}dV6c@!;G{Be&1csY1LS)8P5Lzz3tH6w_AVj_oK9unlgvtdhm6!<?go$hG
zn8-2{D<~V+wot=NsvxR3-@M73nO>C|+?+8iGo?aOhr7^>XMU_8>T&euP36p&q1K2S
zUCc1kDkQDAiET8@^a`RKcW^w<%%~tba`Y1ZQ~~Yi%GF8JF+W#`dUA{Au*@$NL|=~H
z$X_e42XHy3BxYuXWH^@{&M~tph*8{4^jNbih;baftG`uXPvY8smY6velBry&LBq_g
zAb#TL#hnLe`u=8e$)PMWze2Qt?}LwVK?Sjx<7)}b!io@<aofk}m_-$ml^pX)!~9-B
ztYM5x*YeC_t~nl)rA9H=NQY+wn34)P!{a3=t+?0ny+@2-K2{JS@92ZB=Tilx;(czz
zlvNNW5N(;y6@-n`jMp$<Du^nK(f_)_eB~1H2AF6V;Li_+L(ME75!Zx+EV^Iq`Fje(
z$7$L^Ad1@gFWCxJU7IDOT6BX{lX4UX=^oGvjIO<A3M2-b(Be8uW%#UljL=G@$Iq}Y
z{$UxRt&`BQO&aPLp@WkU*#K5xgicOEWs{fijL_9dm>6y1Fo_YmbFPHiN^JFy0HDq3
z7?avKH5hjILM_Ih_D)L6PQoiBRv?M&kQXc?Rv@WtuR@*?dsM)(>2We6_I46BXIx@G
zCsBnJuPKZ;$Vt>-FE)V9P$yA`4N@^ij&Kt7SpNcqFxp8pVvUX}T1K4cq?$3>X<app
zIF-W-S<zbJujdf8W(j?cntH=E46EtTNn|+9kkjavHHQU^4VuVfT8!Y@#yfP3IFH*1
z13g*U=hc##sp2Mgv^2Y9C1TrLo9-F5cSCsDQi~cy>tNTkfoNMTdMxeOp<58CXRQQ?
z+OthYK;m876Gk1`!ZZ**E<qr=vOo5O+72htll{U8jOgbi`mzsVQSV(&VgMTwi&os@
zB!;kg)c_FSB!;ug0zvG<fP?pc6#HcqjDl*>vmVFp!}LQ8b`p~qfx6jR+S+^J)=U>h
zNJ4CaH*U3O9>DAnM-1m{D7AbBwr2l5Ff`-8pr)E=y$-E4><T6i8f7zVH2bPb)LP#T
z#SrkV=8OXtdNMQAkh-Gs3_JTRCJ)`6Po(0-lX^J`E$iwBNna-+vTJ(rj5NSWsH{5?
zgPjBh`>&Xd471WFVPkuVA|w6aB<$?<SPUzpoJ1uyF$=_4hm)$zcK@PbqzO)<3Y%04
zqsdO9Dx)o)Eiuwm%?AW&FTTbzjilrZ3Y4Cylv0Q8E1s!zw>H&4>wJpRz1nYKQODWT
zQd(_#h3YW^4QSd6Re<<L;|FDjp@!UIxD15zk7Y*w?}H2ZqGjZYZ%oT>c?QXUU&hU0
zko@;$(03{K`M2J_(?Rri5;peBM~RUKI*BTb)@O!>kq2w?;n4Y{<Ue-6rDicF;Q4E&
z-{hG(nz8OOQ%}R!Wf&JtjGbZXYJARd7=S-r=a~RawQU0Ph|%6U3ZV6xNwC%vgm(B-
zgtN^;ua5pO81~z_I;O9@eUtKU3(3B9>As?c<ee^5S1o%zjAvy3x?9ozpovC_pmw{^
zys{oU5KS!abvX&50eeJM7&)-6HxL@JS?CAk{Z6%J?D}Q`BOh?8wO}8kX7a(>XMo*`
zHT%HkaNV7-X~)KF1aZ_!baZ}d@^KgX)Vi|b14JI`a0!A@H}=nQ7;M9wM0e*Slfzx;
zk@aK*>db`z+zT`l77pX7YD@ZXjC@5C3EL{u$I8s(^YCVNUYtFqP!}UXm04raXzBl-
zgzgxDdRJ=~3(rJ>VjNv@VRx~Z?Auz*7MZB#bjx`xW`sRZw>J2WV|+<*n^W(%|MYyD
zR_KjV&%3b9P8*?e9zRvW<6~;z-v}tG6KxC=z*99ikEu-M?*Gc1{CyRChsPv%8Jo{D
ze?rPsM6-pwgt^MhpH1o38O<ZSJJzxV0yBp6DxxX<Pj5`)3cZSG#{EChWd9e<kN<Zx
zc>d0Cru{2GG<BZ!6&SWBD#S3u@sHhAiSDUZ4X{{ps`uAa)M_zP`M(-F`QQD^UqE(x
zMq}u#bWu7f1Fap=n4FX0qV2-}$I&!$K&J*|+DiYUj1d*8V(0%=)&2j*F13J%u~#rM
zii>uj72{StMp3#e8UuPBmK|ti!INE>f!3CQR-9P>6NlQ4e7Ud`nPZ@ptAcN*J(ST2
zT3JPLhU_8{hS3?7GYl6EDVVfucNal%fsYC`mekC=)7s*+uF!UxTU)R_s{ZH7Mc1&Z
znYHM8R{6Us8DSa^k)tAviYV+>R%7@t0L<hWrjo*v4c%6*xW#MzAF6-~xCjlac6H(b
zyuQJTHmGhGUD?c<Dlf0hFxCET7<@C;8#sfkfgt&cr$VT8YyR6h70(2%S_`d;R;z7i
z8#;08cx|({_e!;!@UN-34f75B>FOm`s_jtt%EPdJ)YMY>O2*N+sfmdU{%E{718?hs
z`HZHzj<59dPApYx@)e>rthVANm^Jcs{60dbu1O=AdHJ8}8b+gXyzU2C!qd0#m40l2
zQND)Nsb69B?^UC>fr)olt1)Q)SIp}bbhTPd5BvXcHT&2~e6<z<Ky6jIg8y#}hm2J!
zXnw7!$QNsS%|W&*U)x^`jQ<7L%c)werdG8Io~Cwn=Z*YdG_`AZwX9sFea-(d(Q5oT
zOkMFutJ%wm&O1%Hwl;5%Ii&j!T(h66<Mnst#@t^eUI#0;bex}p$zX+%mgY40+d!+s
zHMbHC+TT5*`}LTb@r*|tDfmsm8k8CQS;lqiC(?H*Ae}QDk89XHx}ID~(s{oU|Ir~4
z*9n&}HD!K|qw9pZbp5oS&>RL#2zjRdYhwMeo$iPBC4<}y4X*u<6Mx5Mf}7Gnz%^SS
z2RAWk<C)zZ$-UcG3Mf5>uBm-Uf6x&^xOI-K9#<pHgks{<noakYPSE|!-efB~DwEle
zpUJGD7r9SMr>Mt&CO6HqNc9>f7d*3VA#sNOO`5@7sXd-trWX2P10jscCe3rnq%)`s
zakloS`)jwzW#T;2pIt!syPA+x<E(w7whm&o{FRh`*iC}`F691~Aq006ODi<gDysK}
zO>_--O`Jw9q`CP|(s8>_LD-T>`YMueF1994zao-e9Z2^JmQzbCJ43$yctZHMM^iQa
z`bBb}=+c-}OYL->9!RPkob_0X$uG}%wWoSK8%8zga+}~r9w2_vOA3WeBmHB)5x@0j
z3TsaS@khKQovIDVjoUD~-hEA+$_wfKSIpRW=I<nqaiH;QQAGRRlAE)X;9#cSA*H^%
zN$IS!B@W^X<C%{eh%<CP)wS~`;-sA;&EzA5kT8mZNX0B2&wdbvm0C!gqy<#(419__
z)3_xe7-A{Je5!_nS$>=x2Q?+Q<W>Z9!$2(|`4V6E2i*^tK-WJ?h;!Z9?0cPo?x;*~
zlWgQHCXqtlahvYbQYge_&T3RDBb^3Q$bGtrywr;$9NCLB9jRD`qLDMn!I&Ks*N?a8
z`Z0z=iFbZTb3fC4X)V$ml1=x$F)iU4<92eBW+uny0tjy6Jd%!YPiSsuNE&~FYH#UF
zE*IsI`=!puH_t*k7RL_+lz_QCg7}H9JzYrYjUQbn80mT>lyrJtAnAbmbYC`yK>v2W
zwl-&-`u{?X?`@$VKF=U$js7Igiuz<V!%m!L7Lp!XLAJ4jo$tX1=lj3<4H5m3w8Zny
zCzrEZlGzj;8Qh#nK=w4^|C39a7oEMuSf}IBZ%C){YU20FAvayVrFvh{5GM!8IBGL$
zxt?1|x}Yf`Uwuwi1NG?7d1jhOs;@Rv&Bos(XFZ;fc<yy-*v;?h{(z1k(v}lvyf-=U
zOQZV@7(me9-5}dxJ4v%-BHh=1OHz*`<Z@w8x{krD6z-Q0e{d7>GV_B(?|-Ec#2Ra*
zYxIu<cMdBso@tB00S-*WZx>DOxs%j%Ejy9>Z{Jfra$Tv-USe$EnOT#GGi?*O->{1~
z6M~83?LqD*r;^KHnUDh_NqSp>)WMX-lY?5r>6$c%l-f-tr5ESP<sUBy;+t)B?Uzl^
z<tEYz-9wK1S?NB}LV>QkLY(+ax_@+(Y%7a&_4-Qg8>P_o@EVflE}(XLhkOR!|2dbb
zP7{ZcYLoF4R~0t`4XaB^6P-#m){xG|PsE?mi-L<=NYYTu<MGnnq~NOXq!X7$2=RGz
zUzR{FpJOVIhr5)j_s=cjKX<+XD-7guy<;s!akD-tokWrYqgj7~o7tc0I%hPQ3A2g+
zuq7EULxvi!>Tu%hm`2yeSiADf2Y<Tnw1}+EO(0D%j%?@jpb&?CqWfx{$X6ax`8<>5
zOZque9n@$=F66THpLD-_1;K4QMnKx01T@p(jMVwTL|mnN@55v~co|tWuScL;j*)}N
z4s>m!l1@Z0UCY0tYo`;0cCs^}X`hh$U>j-n8m*)EKfIU(6P=&p7w3?gIF@SZQATFm
z3~EyG9hq5MljA?0k?~oi26)Ej6mhm<X~#4AD5~pD<U4^GL5_cM_Mu%r6VBO}<mESx
zDtQ)}N}dUvEz|oSzlaRNkjqEc=o~b!IO83%fk219qwDWHLEC?!AeP-Apikq;ikn41
zdw2q!KbhPdT|}H{PqOmD)(OVOfy6I~q-(c2#Bb;vS;njej)UpaouKbtr0b3?<e*P9
zIhg)E-OvAn>X)#RjPq9!-|c6DNL)?V*O*ZANNX~Tj+s@JoQ?jL?hjbCxY~agas3gG
zOvgkXr?8HBYjA(!l#FWx=9oIhQEfQY`^!#h%nRGez!&Qbo*DOm9G`W*2j_A*@asOL
zTE0uCAPymGtz-O)2=wxD(){HO-S@Q6^^lG<4R%7FYaln7zfon9s*`3d(0GNB@X|5y
zj;Ca>DW4oX?M$j&rcjKYLn!LbEyzt_4^o}$OD$ATfH9HT){%5#1L+z*l^(>47;<pJ
zIpcd$m0If_Ix!t{bRqFycOu(iHRw7SlNud!=LH2Zf3O347)&B2jXEZ05V@QXKxQ-J
z$mM5jf#{fJ-%^eB&iCNAAcFRtKsEcx`OeqdPR-u$7?uw-d98YXChFc`GM3_elf15Q
z(kE*<?nl)-fQpV@R0`>sUF&c^cBVTl9pm<nLj2=hk+|b09Hv)s#;mn?7{6|yL1w`X
zdcsSka_}7wYJ;<y{jnFkZ)UqEpzvYyXujdgws?;qcd+&=pmwqomZ9)t|9lBEfA-o0
zINi;LzJ=F4Y;Z>ewU;g52lD{d(f&I)4rF`ZgX%uE#Z<()pWR7gMG#wC0`mY{O3Yxk
z-CDRf$hy<8cZhv49B7Bx$L)cAg!TRo21nWKzY+N{w%&7KA7|T9uN}hPN78{0WdkF@
zJi%tx1a*>iM+5VxSgpey_F=3}hVV3N^#t}AwrvjlhO<v-mUfmsKs|H>TZ)_{e~#Tr
zna@Zz=rY_#vC|I0Jetiq4rUCylls?K_M6=Z<~&>PGf*zDKGYFiWEUKVW*pmmH{4%h
z|2dB0HtQ`@-<HCT?gYPg*ws_f*mqg8AFxx|NpY~a$Hrbjr0HzZL|{K)jqxzdU=0Ic
zm&r0sQ9Ner7Q$f;d(;e+XY3Gn7`$K$#sMXlWov?&&sN(HyVvZhuV5Cix<Y^zvfICk
z=>Oibj^Dt2#~Qw%c+ZACgWn={`gzp1m~A)!%n$76F|a6MQ{I6pWt%odpr6>*#lS9O
z1B+47&+Pc~kd?EZ^n6!wJ7^l^$|ZUrLN~4r`|tbNAdxzec3+X=;paVDp@skXO(WoG
z!B0cscHzYZxL@?L2ZM0&x9%=%FYqmI{*DT^3Pg5@ZynSD{5GxY!dcsfG(H8e5m@Os
z)wKs3;%(C1XaGf_+BX0c8-#!(jpVU~Mu09h8nhanN1v!$%{Kn(0Kgj7j6PnsfxU78
z)!N8DsfTW86Z=jNeK+<|LwuZj*bth)?qzMypi;ti?vJp(us!1eww9ayBQ!U03kM<g
z?c7|N4DICZy90VJ7wnD(2<7(9hTVB?_XgNq<CcBIij%@IItKg>LA8do0CSl)7H}=|
z*Fn&2r4E`SW3g+^&uzK@*Ujt<2_Xct6Mq6?H2eDsnA~KWoJ9{(#HRTF+XS-T6abn^
zFbwFL{&pMHY_=W4gRXhsf6$q<=!4`l*OIoqb*++mVE&<NUGy0JPMe{6v{T!TIjBNA
zIRK5@e(EU1(P4A~;`p{l2%cugnwN0xbeU!*o!8!g`#%2bAsuwWAAyZ{uoC){b@ib$
zbIt(ZEKF|->9W^m@K>>&wxMzx*t35C+l!6(1Q1^~-l0NeAN#w6;yCLg12mjv#v$wo
z)*1ad)){^z>x@5&bygsnb=Dw;rKojrEY(DJiKUu2n^g`&zscJlXP_yn_Mlj*_dWuL
zF4LkAY5k9A3clf>nrKHybKg-YT95aHW!rpozI>;%d%)?IbRC=?u5%Gl-(FJzH*hPh
zk%ryZ0d8bVS0uIR305AL0?3-po8kVOI@HfMp8pT7?Vq-R^B%nu!5{b|Ej>rRruFYi
zc8w13tJp)>x#C?NtoJ04JJ`?IT0_s7wHBfIu>)yb-^X590gV0Zs1g_kv0rIO3}NHR
zFqExZ48JGX*GPn+cN&}v^K)!Q2s9(v;k3AqXA}R1K?1ul0-A~J@gu0pUDj(XR8rZS
zx8e34>u5+}K4)9G!{P<ofGU&AhMS=Jf&Fk9_9bl1MsQfl{=FW|b=<=0&|J^m`wE8}
zxNDWb^x+!RLgCA~?f}>hZt+H_1aqT<0CtdL7eRK2+cX-?aPHf`p>md6xg1eMa9)mB
zxJcw;D7SH$o5X^;#fg-Fxz9z{2Q!OnPtWWjcY^GnaEVBG^Ut||ia@>M)*H}VAGlfz
zQJIyRX^UXDRx{fKgUuR;8#LWDLotZ*J2Z<Q!S7DZ0c4K(AWesVpm{*EbC?6=NzH(3
z@N`O3eI`IJYFc~``#8-~Ox&H1xX#KxF#2ZQE0FcPu~p93Px?z&A?v*yQyRX{9&h;S
zyFV89-;H~Y>#sMMf8WJwQ4>)A#yx%pXtM*@IpJH{THxB|k_#Xl?Z4JRd>y;do7cs2
z7FgX+<e|NLts0Ji``%pu)gj%n>Bf&bx(577i)d~3lUN4noO|ElI=>N)81Rc8XP^#I
zx_V<!qiEfIH#m*aogEBOyzcX_z)jMPmLN;f)mRT->AD|`0CHRx)=!7(dtoE;;QT6S
zTsi9MAx-QD)zgM?(O^ay)G~PXFuCLW2JdaEcJAMIKZHH~7J+53bMC@T7W=jqsE2GD
z8owU1;Z=bDgl!jqC!NE-JB-4co1Fw_+d01w0Qz!%)sRob3$rl-g&+5>HVpl_YSbdT
zxfvxW_HZ}i0TaM&7y~L0rwO3BpIbK=6%XQCdLYU(+`!W)!nsAXzP`=v_C*vaoY!@@
zxXbOKg=i`_G8K0Bx$kJnp2oR!1@i%S#~XV=d<Hj;-q0-WSvznaa^K#A>LX5=kA`^6
z{r(zM4p(_DK%a8bBY1kwd4EP_UT}~5fccUum<_u;ZqIX|<Z~BV!{9ad`XK7EQu7TB
zFsn3!Gf}M8ti{14evM}NL`1(%Gwi(v^Z)glSu`C#r0Gpx@?lLdJ*yN=CeAwWI6b2R
zCRMZZ2^`+jSWbbNrnyQB$aKvV$~k0c*3n`*Q!{2diieugpJAS@5vlijq6wOYM#$0p
zaS+rqjZZ7sJ=cVs2UxD=`+J}qFEws7@V?UM7Xv$AlR)m@XcqZ_D$wxdP<^XuSrstv
zG~c#?W|1a{R)WQv9B)u1n!pdJTB&9+jS8PMGoHY%OcO!%{i2y_hUQmIISx4RtF&*U
z(fF=fc@davwHwM{u+E`<LsQxf+J+BM(T!Ti0@T7yd*>J&Zq`<#4s45d?-!tL)egym
zp@;U!9%y=Md;bIX-r6x%Xl~a&?**B!wzxft9opt2VBoI}JOh<o+J2is?a|h}k0|zP
zKUIN2pmykE$o6R+Tk$gU2egB?A&OwFTQtHyq>WgP*bZwet%Jo;?U`P%IHn!a9#n|7
zb#0)9YBRhL#YycgY%uYsw14yf^R)H{Y*_PWwCB=b5TT9z1;L!thPDM*ls4%Y%%inq
z>O&<~TTEe}*Vb@^p@tW=pE396<FqMBu!z^X>JdeP)`MnQm$kpAf_X)IClQ)S+KB3i
z`<nI_1;q{RgWgcNsjU<av}CQeJ5X+G*LfqDJKFqvP`RsZdk+=7r%meyl>6F^Rbh~>
zZM74{1MTMhwCK&$dOk;yr7hbCm~3qm7R4j&15fDWXsaay=BYMrEsE#bZ`wlkLObID
zT)fn>&A`mlp2|e=THCQ1JiXDT%tw<HYF*7}pto8R&G+7Gzb{AhMcUR`kbTe^JYi6x
zt+a&ZpC7dm{h|6vn{@-ApS5S^qP@OoD<6Q)O1|_R>{szKU%+rRKX@`=*6<VRBeZq=
zvyo`a^?cRJ@Vk+pA;E4F??sD-&3qwt;dyud-4w*Tl~2inhi&}8NwD+e=M4kXi`OE>
z=-_?$)<fXJmp}F#4tMgiX};~pU+)L(U3`m%P~FXM+yVQ&eEm2yZ~))4GgS8R@2K(i
z^Dn4@5AYK#@EgoCr$HU&I}U}XBYd?Q&^*THAA;s_UZO>ID1V0*wI}$eCNLdgydxjj
zr+JA+%W(b{onbl4XFZ1Bb9{&2Kt=M$zK7pvUQ16jhCjRn_UHL-{;<EmZ}$iDKL2(n
zs5HLtAgByp+XsF#`Cm#A%tJo!d&si+n<v41%uB&Af5NY(t%9cxei4hfpYa`ELFWZO
zoW|T-KI$4GU8xJbgkqI0yeF8ebzSEorZu`?TCuOwHKZ46z3wiJ9vgMLufx+O-PIw$
zcGoqb%-0s3*cc8ybOUHq^VIFW1V`I-D-{^{=qjy7pgVMqF<EG+ow^klq2sTMr~KS5
z-M|a*o2;wc9n@`I!X&8P)p@@Fm8x4l9<uwo*PUUIrW>&d)B~N@MWAHpTH~-9pQXFr
z3e-bg!ybtDk#30$>alJq<#cj%5tR|sQ(X_rM?BYka!@+$g|72VkS}%iP=uJLtGft>
z`8xeXsJ_+>xe8B(y1O(6zttt40ZftZ`c2ps>pq=^W~pxVZ;0Zf?&f>QKI<aqpoU*`
z<9fopT<4%X(MsW$5AfhBh$)b*7W8GHLWH3o94JEtkN0qKQYh*N7pH_D{D5{^a73Vi
z&j>Cp0eV*W9b5N&gpeh|Z=}$DIbfoM8`yH^V}y&etrRPC8U@(}VdpJiUKCEy%=MDc
zZ9G)sg%OktPZVZlfO%Q)r(ES#VR0bkf0KkV>QS!?RViI`L+DBQms`RC%G)OkMjAR&
zgypp8zawPRi<l}*ZinKY(3@ueX+j|mTJh;Za}63VL#SMe=re^rG_iXqEW~+RK3h0B
z386g}h7N$=C&GwA_<JTS-bDG|=fbT}z`PXdrcmPx!L+~jS~!U_AN(7k0qx4X6}Hii
z#XF%6jjhGP8Oj8G5XuHX<)hGaH4HupX_STiA}pcL|Eo~k4^gZXGrEGgN;FemezmwU
z7lE!3vyLH{b>f%{C>-m>hz79OD8{G2(<brMI)H8#*Di&jyEr8t#a6L&GgP;UlmCRh
zr+6>~243QW3n;dWi&rBiAF((ZF~x}kd!yQy#GZXoB#MugfO%Q$u?X&y#Iw^;?Q5d>
z3LM=KT}yy@(;*&F;4oQiJ|5iLVqQO>-4V^SD!eN$^aIR&agRF;)5M23)5$*&bAAFd
zLsYiG{X=p30oY}W4V!{`BKq$IXpXpxu%C%uFClv_HplraK3BYkMK%9YOr^=kEAik{
z)FoeZtUQJg--y1$U{N40YXzORV%abh@6cY56^UiE#ZW9B{0_`g@r5_Fy7=pFa9Ac@
zr(EG@@kS${m5cemp;#%U{Qyl@>1iUU)zT??E!Rp7sqxoI$~6=lq^3cr#760N2aeD2
zZjw|C7n`M4xrlU&w8{haTcw|HP7_nn-LxL|lzQ(0%yy~iN-%w-Jy+m&hqQtc?K`D|
zv<lfJ4U7TUZs`E_zWD&jKNBi}QqvSr`=ww?G6YG@QW18rBvX%eP_lbc{^hXb{Q~3>
z=}8kraZH*-v$W$<djpD4$@e9gCnQ(uHN&LTR)9Gzu~UE@F8%Wc#aZe2Z>Y>YsrVRB
z(j|tvh6mD>1ej+^b55YhlKe)(Z??oA0@x#I84qTT<kyz+&rhYfG}n7Bee)L#Ur3`y
z0`#TSlSacl=~@pkUrQ(3LFJ89ehSoEX=xy+cT%$?_$`vW2camI(tIE*kv6|Xpruk&
zKh&&DvXT4GlFJnM{VKf-2WGi6{S+#(O1`m;=AW+e{JTI~BQG>UxK{2%8wTs;)0d#L
zK`se~;U?LT4Qw~LaS>G9<vXrW*&>J09_Kc>E>1P`9&(?Rka@|=zlWW-Jb5zgd}I#`
zRD9)e0WdfvHys0Jn4C%7)fqYII-1K7F2_;!BtrI_k0{Q`$LW)al3()>M$77L$YNzX
z4gmA#WfRR`FUqHU;3-c2G6z(=oLmV83G%33(7Y@UrR@6^`N3<%lq5I(4Vc&DnIl2n
zl;d$~kH00m(VlRM{AwO#cO0^g!bp`9X+Pwi+`JV$rOC6Z;~AvO1E<18hP;Bd?=t1w
zCs4_j-_!;5NS+x2yC-tzhA496jkLA+OfI0A%yYTsYZSS19PQe^l#A8_<(14tf|)NT
zBbm*=k+W$Fr9gHRjt1IWdCgG>-^o>XA+{oUY(6{{%d?S$=1b+y8&G_di#wp%%H;Wl
z0R1dCc!GBRDi=I~LAe}n19O#<OgTGO<w7My@2AAk^2A@M(jVr#mAiAHvPao`9l-=B
z13M#%K;=8fX}I67gwq@|Na;o!O~J}W0mVUOG|s~Dhm~0kKpj!yXqj+K=}Akc<I0lT
z@D!>vqs7??rI41jr<5)dJcTK9X;FAanc5vH;Y!Rm@Ef62J%{?9Q-U(^n4*-KDJY^9
z_dr^IpI2(PgX#rErgdDL;yoF{OG-2jm-2~<<1||4vQm8?sH@8A(Qufg^rur0*Ojin
zg1VtR4*+#b@uNvgvT_&03ZJ4(e-F$%%5Hl0sY-n>nBP;jWkHsvbXyB5U0LCR{SQ7v
zsY(NOrt+W=RePwMr<8KGviTGYA1gkO5dIUT)^uP$RXY12v}ejCItTDVc|}RRTqUdu
z%=45W+HrlQtUrO`i*o58z}Bi8usOnest%fBdZ|aZASQ2BPkH(6>dB|h`KOv)3a+m@
z*9*lCb=Xx{>{P2&hC_e#CS^Exsb2Vz0KZ%9gwvq>9@Ui=!F$!eDVPAYqyy{%ReOC<
z`_!O|@N__}jkBG6uqswVgoo8WbgJQqnm829>uTjvsN7J?X&1q9Q*BQlz%6wgb+gH8
zZW|Q0)tettq^R5fL~%#0MWe%AHMk0jRJCseihHX6-ze^@4Jc{(NKKYNJysj$q4rPJ
zSI1H0stE!@d#PGqg3428VY7pOrP^D-eZKmhwy|D2)b2}l@PWT|PSHV@x(rUn^56XY
z04-eac{DinlT%TN23w{f+=k;Df!`>c-j~L=w*arnWJ>Qhwa{i~vm3OyYQB|@0<`$%
z8RBZ$r3)(8>WBvVtuOWlLL1|KV75I@dF6IxeX;+>x3~6%L5FVfsKK|@-oQb}CELO2
z^w&(lbzY7PE8oRc3%IVouLE4SIQsT_MBT!*XE?oyy#fzHr}rCd3-Nt2TR^k#37lZ$
z2lwg?{<!QU-2bZU0+-9AYruD9?bJQHv#g^gNI$lU9eR7&_oDzA#O|FB=3!Px&oG3I
zyDh*Re>Vwb9#C@=VyGY8ECk$!Yj<G~%_p`9t!VJuDo7rXZ4>e-UE(3Alr-}c>i0!R
zUcx+DBX|qRlxWy4G^TIQ;Um1M1XW)l>otlUf^IjQ`U~$Y0No`FY6a$AA&h2m0m6U`
zSOf~EsS)-GeP|tjK-fGF2EoFjRS4~%U^)TWAz|kakR2AvY3u5UaC<7EI4V4x3BSjL
zYt?~yT&T^V2yqBaY3n6axI)_oCxrZk;GPr)X+WJ4s!c@^Cfvc<FiePVDJaee^>E;r
z4;QA=T;r_J>?4>Ff(s2$=Y+PjMu-%07bBP`A$JGDjutj<MNBb5*Nc$F3fj*o&I?&l
zV8#iKY1B}cghV?cjTgq#ais*|R!=Y!g&IBJ;<8YAFXFx;WWIynt3ts(7+w=xy1>PC
z;Y`JxdD>;P`b}X$bC}-}mZ!rmS(u^+%55RKJ2X>-I64`VDiqNg{hly41DN-PbB--2
z(*(X7RMUkMbg=1x5Y+&x8A1!n=wu3Y1%PG=n)h)3P!I?vTL}0YP5MZv*#W^k78+rX
z0`uw(^z3tlvPVF9DkQIj?3vJkcH^H5Z|lJC3n7(OLAinlxqT_bM$!Izp74y8bgzUF
zi(r^9?C1*NYoVBqhP@F|pTd2C&}=7)LZLwdK;H@%DU1J3xX}$!ycfQsebpktoer23
z3w09V@PqL64VWcD_qtH|B*Z;IQ6|i$BXnPdUb~=KE>wAk-$G%QzSz0O7nK|YvsNsO
z2ljgL3x2-GZxGA0P~9YE{tSCJaZ@2wHj4{_A#)c~f>3M`n^Ti)6(6U9+9tM|g+M*T
zhBRmP6gSdn=_Pi140CUBExke8MSd<QU$H;35DtEa=uWZi6xUydr$90DR}}liCccPt
zzo@6_SCH6@hW-O$40VUWVpRjZ>*D55P&p)WR>X8zETewth&YLoV@Jh1ClJ#yaqT5&
z9v9EjIjInF%Oa?Rid%UwPlzp#qHvrPe;y9*DRE5<48z2R)TF1yhVuY=MogfkM!48C
z8*O=3>`fVt2yvN$s+|){k!;{2#l^G_5GC%QnMbs^zCFxi#IUO{h!wq$Kz3dXr3B*z
z@ytn37sYLK4kAwc?Kz+?ImCa~Ko~DRZHj0T#e7=)T^5)10ooO@)?(;f6)iaPjrB`y
zN`qe$-=yQKx-RCn2HFkreL5W86a|X#mY6gR%w#bQKLfyGX5b)rN)h|I1Nx3wN)x8L
z;<ACjOckHkMR8Ab6by&XeQ^OT3(~}zblfIgys`wv1F<2U`O6T$js|F^*yk-CMV8o{
z*4hun!>$N4TkLL!`$u9XEtDRMGwIaD6EUj+%yYy)=xoMQanN#TJ`)2}Xg(M3(@~8V
zVw2<0%oV3PYC-j-SVV_a^2GIL;pvq)vMz-AVi9eTycU<<hu=5iOlsKzaa1wv3&jaE
z9eFFhJ_Un!;;tXTd@p`YKxjqc`RULs7IQkI+OATJD=O$K4WKX0PwG;ND)~#@Z$P$7
zYWISM#NE<p>gV=If0|*xS8C=D`v9rDFJys|8&1gc`=nL0L$+U<8iPQCqye<tJ0LZk
ziXvF*GZV!@>C;azKO~*22C&1Dox1lUQh)l=k4oEvAPbRFwxI}>VrVn-gw%dLehbN;
zl!ntQe@dG84g7{l`PAK=mWt^#=ou;W2f&0&6KD_VtTd6n?Fgv{<s#2X<z1i|DSdo{
z2&1H$ZDAfQ)u+i#jD%mO;SH2t9z}6p>WO6$e?eN^8O24(MB_o6bm=(Fe=bRy0kDXd
zBF`hX1j&=e>O{%w3$QOsc{HuRBITTe;Z<q5geFOn62sAm*QA})+g_Kp(CB?bdVLg{
zH>CpF2fZcjrA%tFwEYB7ZcEKO;z_1ReJ29?jwG!B*j?#Q%1}5`r8%@Gdrwl1fV?ja
zZvoIWsbgKJrc3o{XZ(RQV-8?4q;W&R%#<d2piWuRr7kddD0QWoN4B)?Dl{KS+24bD
zEUj6Kn4U@-Mgr`aG?TiG=Ths3P<bH@{|<J!Qdk&JUOJ=@np@>bf6{yTN}5l(kbLPa
zZ8N`?_&U&eBYoQfh6U1oI@DGu{ag-%x6=2qsM9;?;W9AaOYi7_P?4m247+0KIZebr
zNNq=fSt13y0JBtz?+ogrG}nwa{3In*MHFR{L-Q+ypQYA4&?aA`fj43QRa%d;Ianv&
z7zg(&<)7(X!76#GKR{jO$irZ+mhTn;ZH-(=dp&FA$uu!pCmZQYT`&6wLUV(Bybqdd
zqg;#Dyqo0xui?l|-bJTYHp|s#LFO*Eb9lhv7P(U-EVjySyJ5dgZcqDg9&)pA7<$Sl
zheOp%zC-hIA369Jc=DC+{|VU+xx*+>J7wQ+6n^s6fe6N5o<W$q<UTey+$~r3M6pL6
zI1bFc@(McD6d-Hbz&ub6o9_U*PyS{<T<n*B!_UR|AbAO`BM!(LDSsC%_wE9}2j$sx
z@cEG3WdNwdvXRc89+7=%T7Oht-V$LSlk+=*IxZJdbA`wq=o<@_SKwC|{0X`9X;3HS
zu5`TYl$;iZK*Qw48e0FKmNA~=Q<Gl}M2O+?&fc&;EB7_PeT4icE&k5Q-o=P8Qr<Qf
z%qV&74*-ppT@Qj8Bfkv=GgdZ5LG!$v{u;6iat<xtF3M@sff*+kb^>)tZcn-5czGo4
z#U;pfR?_-EQMS>Sb6H+mg5ruie>Z};DkmKRl_WQ;2^ZI7%`&*SDKDTm@Rq!nlJUv%
ziWz99+j1}ZHdACr7iiv*x7y+9uKXA6i=@i=bUyi>TxA;^-j}ffjc-dHSq_7AS?mL*
z<AGcy9c6~R$p&tw96}omS#r(GsLVsTGOZ)B<prgv#Ur`ROsG7TPi%thiF}w&&F07h
zm!r9!%Ky+7@H2U1Bs8DPH;RDrLjG+4RC49b;ZS)g53UDUo_sqD)GPTBol44g$hZGO
zonFghXearN9P~4&0=X>}g|dAYYWP-OM`x_w$-By7|6Z1wL9<A%Lf=ub+{FZ#53;2#
z+?U83Y2&C=)>8Bz<)<sqYM<mw6Jby$_rD6+XPKpB(HA+d5~BDjI~GxHzFZFZ4#Jhn
zXL7Mh`D+sz%2oN6R+Ouiw{!$!jq=Y~sH{~kQ5t=nvVs!*>y?F+G~J*?UxL9#<=NlB
z-mK)!gn_$qZ3L(-N&zLuJd{|<6nH8*v<CE2vMIyvquh1OfsU_ILYamgN&r1kf29eX
zMBb%*+=F7b689I10Hw<`xCm4l&~g8LO0U^ypaaUiYoLOaQ}1ARP`O0geMgjozo0m(
zG(QdIG36x91CJ|T??N*~X-p}}P~|Z#Ax<cpBI)}(sq~{qa!MI74UvW^9sy82t>hg9
z%o$}f?XrX`5tQvYt3<U$FcHd=!!S6f96gC5Qn`=>S(Nhm13X159q1TSjFNd4RIKvu
z8NxoV_#*#;48wqtXy1!UrRq?LQv&u;{`->BV=(;2EA8mqUV`%Lj|eeQxpxRrTvqD0
zLd#rH7SMLzRb|s4xKC2%;wQ%ZHDyK@fL>R=r+)p0QXfAJ<!>tMXj*qmsZL*0vhw>9
zM0iJu=m+YqlGhhSsxo^XpzkU3@zYobe_wI`7BFc_G;J!UD?YPf|3C@IhGB-Xs0M<`
zR62En!z`uhMyNbgUeeZSw({W#{612q(EIpUS^NeDPn5rD&oW0TrsU^SrD_M*JyS|)
zvGN@07WyibDB2LoRX)+lJ;zJs_%2xFDQ{@W`%3XMK$x$%>;~v-<zh6LZ<IoR7#1jV
zAAwn@{5b~(Z<Rp$amYKRGmWP2l^*y}F<+$oLvMGn(vZ?hAC&e#z`R6}HbGXZTxx^}
zKPvV=VDL%lMlqE+l%r3e`dMk>3*i^Vol-zwm1@<{Q02<iI8ZCq`;?tprOs>x3s<%M
zC&<>S30M>J>(uduaIsz$=rL_j%jdyhqnb+Flbh6~9iZZ-diRIjX0;z3&vI9r(vp0O
zx<Ut)t*WDYZA7z84flY14>jZuV0)@5fq?N+J5Pdzw`!tODce;m<pF$D&jJMFtLkX?
zZHL;aCH(GG-B$s{Pn|aaOn=p2gTXE}1-~Ce(q;tBzW1p2=(XCb?(~9(0JWY1_kpUx
z(GkyZpZan-boQ$rl+zDVm-U9u0d>e%FoV@dN@5;Vxe{m|Qj_PRIII>?lK6-^ltWBM
z)k+Uwa7?XA`-8{TyR?i8QN?3W2~`b4z&xRzvH<0z+Uzf2o>D`pTMttw=hCe7v^rM@
z(6ef{x}YM|?X-h)PCfb#ppojM7!*<JcqFU%Xw~r-U}Dr|_uw~H9Tft!^Xh^epj}Yk
z(jnW6Y91w<;?ya$EptiT?g?4ETDLtsB&c12V34Q|ZjIuy+OZ|A|E{R6F%Vu=SJU(=
zNqycFabHts)2i;e+MBR%sPSWgeN!DpJL9+1N3>u}Ru^qU6t`7(YVH&@eHMy4>Qhg|
zdshv@fjH!<N;nwYQ<q<a?7n*04;4&PS9F8FbXBvA&R;)J6K+5!LmfQ~#Y6SQKE$1^
z%1@#CNG+R=B1i2!8}6T~OTK~ZnL3$zwp_J+D3~wR$wy$9r+%ct?X_xKhS1)q4P#+f
zpiZa#vUlo&5peik?GX;mB6Sya2F2=Z>a`pnRBsE&614?p!~7@pTiPcqQ*TTK%x856
zouT=nw$;GXSM^pysFbTOw1{G*ekAqTtMs9<pj`E%=-Xbck39~*YxFz6f%#f}qct#C
zr>Ea>^Xv7`sJq&rADWI<+o)ebC)zhT^yQx+bklp%!L!Z!z?-1l^^+)py+!Zo0{gA{
zU+D1XHvO3W2-HLWBPDx1^=BW$z)Sx}JE(Z;m;Q`myZ!;K*nIT$76ZjspLGP(4*f@Z
z$9L+ty+iH&^nY!JxxfC8<51b9cZju7?$(zb0(X!8m*xm@uYT=bPyu>w4{8{wuTE#p
z_vz=;j`4ndr!k;{^f|OCbwEF}HL!#A*_5w8sIOXvIvvul)POpyUqS~ZkLdjl(Kn*^
zqZ1;>^quKZ9M|`416hdv1^r(je5n3hHb775ujD`&rvH{Y-P8JR!{G3&K7fu_Md;g6
zOy~56&Hyb^pGK?6DE-%HXh!RIUj=rIzWX<j#p;*Q9>RJ3EGz6T=x6^4%!~S%FEEJH
zUu+IXm-HEw^orN}=g|Idg1$B_%M$gM=!Lqh59@&9ivF7r6j${hXlpx3KY-3LUDJ>G
z0>kV2{x#w0hQ0=kn>Y2Hd0^kt51jz8WWAA654ZIpjS*9d-lrYx?&$xZ1k+vp!;_Gu
z>W{C6<~@DQbu|CHuMax}m^6J~YRe4$Z*zg2ssBLlRhE7i?XW%6PZhw-)<;c-<|BP(
zB8nV+?4Jnjss4^LldJ!H1+Tyx{nF)Vrvm*3VixLuqhai=J}(U@@ATC#0`tB8O*c?Q
z`eWG7bnwM`zgK9)5BfIsQHv6N_F_a)s-I<t;YYoV(lDR&_m_ey)9;~0)@S{%zoYn~
z-$cKn_^KcD7_xGG*eAGOY4AD<gH?tutKiAi(5*j$S#3B-dDS%riF&=YhMRPjYn@@`
zNED9shQGF=Y8woNBJ4LB{4x>6CPVKfU~V?-uLBr&gO2i;TMVPp(Ry1A&wqi+HbZrK
z1w0HR`a$MtxI(*NUIq_3VCHT3dlW+3ZjdMg;bWL31I*Xp^(`FkF!X8#l%0l!^TG6U
z7%cRI6o12_+JM<*`1vxZ-G;k#dS#CxM+eZohUL=`cYt9M{U9XJFp>_S?lbhEFMYou
zfqsA$WOzWcy90&}bdD(4@TwQWK5XbS7MMp2`}Tl3YAAY)n2s4<RENrOLq7gL20p~#
zs6zc~sNo)MJe@G~qG`@aL!U@g?UbQ$eMAvva2W*Zw82e_xX&2U3J^uOp$P-oS;J4Q
zVIE<y(NU#yh78*9iZooO3__IQJL;#R4dM})#~4o0m>O$%NU5;%hT(1iyI>gR_!;Fz
z!&6Gr#~I@3cea-dMRB0w4Zj2<rUb)+EwE2CJUa-@%ZC2hXtpbc4O+;q8ZwWdhDnA#
z?O<@tV4zvyb;FTSVBRp4CxLm>kmm)=TZWj*2sGJnTR=>=4PQ<`GsO__w*!&hF>L4!
z?p;HI8@Q<k;|#dCXNXOL;eA8(Yd}jgbf8K614D@eQDhi4gaa+p5I+D>WEs8>gxy1f
z$q$;@hEc7+d}K(al<;H2oMEW;6T>4~!si&6zv1txVGGWG^Un;|j&b<@UKlhXaF}bT
zUIW~hhVT2sBG2IV5iqX|+vu=DzF`JsCte#qQUddh;WZt$D=;uk5L2OHdP7ie4Q|vj
z?+nv8P{oG1bD;UbaD+OM5<|{I$Vv^Z*CXtYhDCJN;FDnn&b&GJGQ*Xji2JkQdRI97
zV#sv|=vTupQ&9VI!}WtGRvO)@*;X5O&`-zK7#q?Aa;-7t7Cfyp&e5P)Zw%W4lnurb
zT4HWAR(=4xO~#UGsFIuUM-x;w8#&rya5pv%g~}FV7n-m-JdAhzq2p=18wq<a<B0`$
z+TO;oPvK&_v3hM(+sC*n8BAZ}wtG<7VJsViD0UjR9YWz}bf=Eh--us!;rlUe^@rcx
z#+j~gxX0*t1&4c$b?BT*fN}88@Ed4cPi?W!IGJXu`yIx2JK!nESecFhA280PEPJpq
zvN3cH8e{jt@R0H8MxY%wcIyqzBgQLqcJ8Qg1vStyW3BH{i{r+dd!Q0xd`ayTYV<7w
z$_e8TPq;W~9L#_^Wo$!xDPhKEI}q<_W9xiGf5zxoL=(Yq<C5*rIcuy;??;3&!58k&
z8MTuD8fh#aiqN7eVv04UQ)hDC82J_07mObC%3m}l(^1ekqX$g~FB#Xj0ZP2_<vKto
z80+?dr$poT)!^ZZaU*`}z+W{kX^be6j4d40d0sPCc?I&iF((9uH;lT$P`zc$9|S7d
zsM3SIZM;Vt-6_T>`qkteV;-eL?iyRu2XNmwF9Lz48UJdJDAJ8_&A@zMtnC7W45R;8
zXl5GQ^+a=J8Ba8V`9ou?_9(KA7k%mc?;~UCWJLPdcvXPIC&pE=u*fk!&js33<3IVp
zerB9Pr%#?6FZv*u7e;qaVCNdUJD~Z}IGp<IJmXY)gs+S;rTp`a(`&)}weg8Jm~V{l
zmVhcSM&-kx&=^2T_P55@g)F|m55_DlqA4*RdIa~S#=Ja4`q3y-3w<(1)dpIbagr-!
zpN(heY}FUzFO>fIYCKH4FXhHNWU$iokPbSpGEJ)snX74MB4n#gq4bm7HKy%3V6Hdy
zrM2t^({}nb>qe99XBOYzCQ~i?WZX<!zaYfTre-k+#@#gdHJDpW!zQBGYHD;I4diJm
z9gJYSOnS<)dz)hKqcYn~ztHZOkLfK{+t<{yF|c=-J~V>LPE(VuaOh|H^A0fmO>JTz
z+hzKii(<D4=a}*R1(@=*fC)6^2;lBB4L=Tx{U!_b#6hMDr%@a*#aQtSf=!Jn*Lcv>
zZ4wL*nLg}?!^5V|)TBpDMRZ#GsHyKqR3gMQJ_DMert-U>PM9VPfyznK)A=wsW%6qb
z%`npg9xZd)VTz$`mouhzBM@-7$u$tFXH8eyLMOu1_$=Z+XPUGQvPjciJ&Guk&of|0
zo2m>&Oy^CBQJ^lEem;)|zG&J<ziEs!^_&Chk||1t`*>65-{CjG<kkbwi6)VL&3)N4
zh31G!CP!Ub7hN;0z+Mo4-L#%QwHu}yd0^f&wF?3Bmg!R*ERs#pKcFpco92yx-xQOb
zR^)d~h7@StHEsF;W~xbZ04~x@n<l{^-Q<4{Di2KWX}>eWG^-iRGfkhV4YN$gXmjqN
z>50QRuQKg4prVgV2WV;g*pzF5-zO$a;P4%o2GdV4pPRy~g89O9{W1)5P2Ce<@X{3C
z0J1#OoKRrDGIi!r(R|ZYIv?}eH1-InH>QvEQPBd^$S+_Pnodmy=3CQj6HwlnK4sHz
z_TJQXHn59K(KNj(F}YA0wA6Hf)^Q(AS#+T1lj#MWYb`U)7Qp;$Dy3=47gPNz@cY%2
z-WM*)O-m1hay8GQiQ{VXuXH?MjkyWAUu$-y5qh0@f)AMM%`UVC*kG=dPrv`#Xg<>x
zI-AUaG?j5P52wWGX7h|YV7i+>=|F8W$J2Qg4|B&5gzsrCNJA7}=1O#0)Z6^WVEEl`
zzB3L6KISf+!1OgwI0Ka(=C5%u-)Vlh6z=`Z^JpgIZ=RP9l|AO+Un&2x*WA1eh5_bW
z%D)7fJ3fPOpLxJbJlOr_3|f^1nWxao>wx($`bL7y{T=}Hp!vN9Epy0hd5h*cY`#Qk
z?qlWykzgJ-H-8Lfh<PZD6`|&4)N7qE*H4DZNpoG=Vn1cRNlOn$nAyjHpiY}d1fptZ
z&5h`&VT5@TC3Vi3CyfS7q&X%B_EBcx8ko^$mo!i@=JiFujy1>9jPtyCCY|fKV2=J3
z#YOW*5h`)!uhi-Z=6(Z#l4vfzf#S0H1TE^Wm~AcK@2bNb^AE}-bC?^1*UWcmbMU&k
zT`k0R!~Bx=>Ta6%xS&qA%+)%8nQVSUS;;%*i1VQCnm5vhf2z4-KAPm7xlKJ#_swhR
zAYGby54}j~=Dw7ad0<Z21h5RVFP(zSH2*pr23clDo*Q5unuF*U29M3Nj0on5`N?e9
z=a|1%2lJ_U2_;vancLii{d4noCK$Xhm#+YJuK5@Zu`kW>pTNvF|1<(k^4cuZk9yyj
zf1*iRf%$ZEs1%w%uLkwj?Dri|-kFCR&}#3^8yudnC^9dim1?p1SQQ9Am@6g1VTl<(
z-o%@4PNGbDnfdfAw9IGozI8DCVlH0_*;jM?P+*sv`xgLvrNu!r&Q+H2l<{=6ETZSS
z+ERBUs<g&Z#{k({%U?8i*=SiY7Ur8Q$p65-n`JR&_cvQK^j^7Jn*9#@EtWzfbUZ9|
zropeLWzlRfy(}wRK*ihg&wE6%-J(#>=407)6ii>sL#zY&9hSW_p}Ettuqn*_EOjTs
zufHXM7CXBvx9G#!ZBb|=Y>%bK6v}_@wd5iZ$p=`Po`6oE#g+rmeU>nqxbC-j=+MqV
z7N0wy4p_WsJPEdZrWMdZ%ZiIIIAn3BGfIaoXRg8Sh~?pR$c|cOP<H;9#hW%mj$2A;
zqa?&~i`LMg7I!+6e8RE;KP`3eCoO9z*?!70lSa%iOD8%Gc-oRpzfL-1;f$~kw|wdY
zi?f!dk5Q)x%fV)lowKlXyd%=`$9hyd%CdYuifGG7S~A607SdWP)-tpSz|LDb(BkZZ
z<rd{+FIqlNf}=Rgx!zE5T(UF_1$Mlp&tB9b!J?YMO|;Y)3GB<3J{>?^v4k!L_EpQ%
z+OSWuT=^3Q*DN2dLU!HKnmUskmM%f4?@fz&Fi>t;4zGcWWQ!YZqTIGjawe!O{!M^#
z$Fg)RWOpq;enOGzu;?Gc(>=>-KN#M(OsWcQnx)|$7^Yh?BSAf|{1Af1&#+kOP)(+#
z=`(0%S!&ZMf`^tyWl+hsG}{a6k>v_aBOhBL`$Of4<=8{m<ycM)g343NpaNh%v$Uh(
z_qnBP4-8&d9Migj%(Gmb0M%EPpXj$L`Ih6f4gcCQdk%^>mOj*B6j&PfMp0;KMhBhW
zTDtSFduQp`7Ik`WDYpWx$dXNA7hC3CfWr@#I;EgWEOYjvfl4g}!Js}`*3;zSlV!0t
zz{)Ha9Yf&ov!z}zbiP=;{sQ(_iysHS<(7r?E9I5eWEBr@l{J9UWv<pb^vj0T)=GNF
z)>seVXPEq2>p7YZuCr<c$kto;J9EL-6_0?j(OUQln47HL4`J?Roz(|XY_?u%22FQs
zpW!tB++y8B$62;o(~6<G&00*Y?qR*s0g-xIb<0qAS(~;6)7v_YrYYO41(#s&V_ig`
zzSc?9z3;HPtpT;uI)`>R{jBbE^xWT?O=Hw9>u~B|c3bDsj?f-!BbuG<wT5E<6(64U
zCUvEO*38zh*k>);25P_c2dZz7wQCUU4_FHpp`C-RC-;FmXuUNA)FJEEx_~)so!$e*
z5o_vIm>;!vqc8QCwGHjO9k({<h|of;-PZvu)S6xn*$L|`YTuLAx})g-A39|nPn)k{
z){DQRElyhxlmPpTwX`9MaO<=b*q^nQ(Z+0q^<gbg=d926z&_GyDnLb}tbfD<JK7qh
z042s+V253-^%)CK=dEwEV0Xb<nh1kS)?H6w5O3YJ1)(Ka*VByNk!YPnOU27pUpk|9
z#af*P^Q+b~baExhnxY5xHS0I@f971beqM^=hP8}3&70OV+M>T@b-w~C*_ujc({5Y$
z(hnR`tlMZQeaAYN(p`709KBts)_v6L-Lods0Ds>)Z8TKU9M-J%&`Gxrpc%pgt8Y1|
z4C}W0h$7P(K?7%&buEp%53O4IDPXoWWeBK8R%tmLKDO$HgL-21=YgGL4XXz8r`D;I
zBY9?BLBD!<Zk<V8@C)mkdce%Jx{pT9URoE?$>uz(BX}?jUs;>bskD6Shyeh7ZN2Uf
z>W#I87NZ5$i>DApp>+oBS--U=(YE$G>&Dh_@!lFv=jV&8y=gnV*m{RfYk#l?g#o+7
z`mrT6ORZ<={O(6<BN}%<S=%*+N}2UXn$dr@-gg8e{4dr?1EKTP`Xf#0%dOv2(tM?D
z<vkRuY{4R;aJAi!g~e*ysGU$*V_S0;c57`l7D8p6&1WlA*4z5h!fk_XBF(Tj+P1X^
z<|f->I!)$g+mH_Tn{8ript#$fhoRVF3))L#<W}3B0VuZFJZK*1VXF}dG*4Tv;n4B2
z{kQ{^x2+a!_iVSdo(mNp+aNl0>T5eno$d}>^gL+pv{iRQQ|_|)-9?1EZLW17+hZGI
zfNZaAs3)iZ+awn}gFxG|qhRi{xxJ<FZ@+Cky--26b;}XO0UK)qcCc;U_wakr_K}v6
zhiqwe;P<fY+A<g(u`Q#s{YP!9XlLe_EwUz5j@znw13Sd_qYqR<ZH-<)<%G?Rj>w#}
z6}AHNlr5VM>V(;>-y*`(HUlQQ4*rbo_-WXO+a6N0owYe=b0NYuU^9wyw&!%lCDJyU
z_6VYE3n)7uZ968Th_S6PqKLI!$wqPB77`B43pST2C@$Jk%i$@`##cuamuwg5^N+W!
z`v}bhTTkks5^Y5t5Srt%ZF@CXT(QkLfCqHdc9njIo@DDo1Iaa8j34TB-6nQ{`x~~1
zNXTy54$=RUb<4*82AE`9+;J4QZA&S~l45I0bG19RzW1Sd*Y*=FPf~5ClhFA0Y|IVF
z?%O8N?_|?#Mq1sZJ8WHP-TJ`xaT=n@uwA3yb!XbD(_$yfmQQclLtB+VgqCfaPBZ&Q
zwm)rf|JauJ0<tHz^$93)Y+eTt=u_Jo%0)f1na4r%xow6Ob}wvuE+MpBo9QkvU)r9~
z-g=&GAk9x+*&NkNp_*^IiywRQuWeUa!s3nX>l>&R*fg`CQ)oN;3fOOL&1rZ0oox)g
z@*ix&Izv`syWbP$rM4<Qpg!9A#6tGTR=)t6WwvBrfPJ<FcZI_*wj)hJeYO2zg+aN^
z)((NLw8uCepfaoM%mR?E_DM7eUv2N>1!|2wgBE^k?RWBEzs~+}3+&h1R}~<b4fZQT
zQSFWP_H^1}ll@f^;&ro6PJnE)J)<|=yW88*|0T4=t~>#?)o!LE6x;046pV*Gs2!j^
z?LJ3n|G~@Nk5Xyg_RO6SZnqa%pz344N*{@@UH<^o4!g%#c-m<X8VgN7d;2Y*{O!dw
z<J@ImL0P)p_RBP??XjQtLk;)ZgR@Ws*xzr4EYRMSdZvB$P4tcIx6h!Idyu{M6*_-^
z!2X2J$OPN(Bt!L}U7{q^A$!mpcsgtkss>L-?8EnhI%>~429;y>!=nLn+&-Pwogwy5
zc_>2d!{|w#u%B#!;-uYoBZ4_)|5=3JF#EY5z&ve_<Dq%ReuPpq;r3OS&^Y+B_L4ZD
zMc7BShR!+rLORzNX?LH3n4;{_|G;6i-O&jaG4|wnu#dGrp$zYN`;zl8xM1Jf453}L
zZ&(6ZoV_yr$nuhXf(NL0`!M=xK!SY|4WEhj>ePmp?P(LCa>YKL^5TxG_OXZX43g~Q
zXtV2@y;U<9UbnXngvAYeA^qIwru`RMR^77O#=v2+{m_1Z-nLu&ftg|tr7fsC_G`a^
zdDmWa3XPX)|Cxs@&EC=np3?2Jub>eg*x#!#&#+(1fGpE~btBwoIqYqI1oxr64J|CP
z?GNd_dSq`vOSZ@MAUekO#J>J-#FS&7MLD6T_E<Wd^~`>t6Ffb)r}cu}3%g%DWVv?F
zOklsX|Iq`oJo_Q~_0KDNi91yC?dQ+H?zO$uM1Z}q2h(D-!0xaFApAmmtK+bEYj>r+
z@^|)BT3Nrh=W2jfWH0$1Fva%$bUfpOJ?AX!OYF%(h_KXtmi7TY+Fi#3?UVh}7EopO
z5K6{=wp(eZ|BJnd-s-RR;{U_Zb;o5{eQ~q2v`ibmd+)u{)Y7uO)Err^%7)rDORa3Y
z4B1nZ4YEN*lp#w%5RjovWec(q5EKR3%I|xAf1S^{_nhxJ_wqjXx%ZrNAO42k?9#e+
zSg>KV^1#_L&RN%Dymk!PA24XosA9t4QN}@v1UN7>g|O?$c!hE?P7E&^g)>7m0BjeA
zA63}7GIo6e1vkctaCq;|7^YLV2V*f^Ve(|S-+)~&hN~S!ycx%4K#nm!F9Dbj!=BzF
z#~DBUN&C+ejFpH)%=2ZW1)|lDQQ8J<e@0a<%m*;^vETw3C3M~mVraV{63mG4g{2Ti
z6Ww<WW!$Db%}K_u?l2L?I5Gh)oDrM}^$5mXI=@9S=KMdb$5=cIk!Z$R3Q5H<N*+-D
zA(rv09wy=#5-PPm#dw+0yzvZ={jhYJ@g5tZ35>G$!JT1r%OR4;7(N8hvy8t8?HuFb
z*HB1e;4?pX@EA)9A(Fya@Ch(e8D6K+c%IQGfn*wExh=+-&R8@BkqpLpgrcqUE-<!J
zk|3L5qJVr3<M2&%<}#9KNxH~5zXT+YkwJg8d`1Cn&@VAQr1N<JV?QN93mNk_fD|#Z
znDF8<<FA!aFJ?$6P*lQLR|~yTM(iNGFJrh0!Chg@alp)6WjsNzPir~jsqJ7Z81hYk
zsbnZ~AzH;4qR4+W<LLu%t%mW~5%gVSyhgRZ*BP}un6G85JA%GC#*0*RSkL&l7J3bg
zyYwBFM#kdTf!)Mde-aAKjLUQmyTK58qOXO~kptIS8IRLtjGI<QpA3p^jA^=s)6Tf}
z1?H=R;ZIj3IvJ0D3%gy6rUlUGX7K4W*~9qYUx@TF{-HzvEygA~P4+Qf*bRk#hW~zW
z1B@T(FnOEt6;)0SGCH0C8DdDN1n~~zU5XmtW#s$_XNDQp`IB(t9)sHtjr$A<8#6S*
z=%T~nC}T+zKp!wr6o?0pu~~~zj59jvd@#WndI`=<GD<37aEfu0%DSc*?@$5C4C6Hh
zupcrWPz>x5!!Zydvy92J=(Ay7Ka4(G=7IG<v1685M`7NcS<V4_l=<@#bUHB0X@lX&
zoZJQtC+0@F`|Hf)H^ICM^OxP=T$z>>`0K`8NCg@0%z3+^=fU*)6~vSIH=T#Pm_If^
z!JB!7N@9;Om(QZlhiRmp+i~VPI+LDYZoW$ad0*zb9<=%~FFye1&s?g5i2&vWs{agR
zE~oHM2(u{?qX=aldmh|L<}WWnA&mJ1)wzc=AJUT=!3?56LL_rNm03hF|Jw(<(aiLC
zfW<Js(1OG=|A_-i9CO`M&^yIkYD4*lc;;F<5}amQpND<|a|wM|^9=K)r!jkp%s+ku
zIm>jS^zb?6KqX+3m_7`^Br{!pfQc05MOtQ4nL>Z~d!D(%4J3{E4&4JwXYOr=dIs|c
z${A-et#oF|V(y@*)dglMj^fsN+041`!+Z|2(F=e3T;`LMwz<gM@))>0X5k|^lh6F-
zdyq@amd&tK!2I<LyeMS0Qsq|>lR-<`W#)B?ix)FLc^!63n7^f=uaxP20$dsMwf*$q
zF<;Ju-c_bO)!URaFDF3HTEV<cA^%F|E@xm@G1DkAR?W0|6<*XZA1(uTjroHk+`rBo
zmBK_VQx$@~I_A6Apis|zgBGs_=CA$`X=MJB4}(q2_9sD_nO<~&y21SZD_Ce@W|l*t
zmAT+N)Ne8$#=(4>m3fz5qwUPDF*w!1{JS4$oy`4I9@)iAPK8D{b1p4gJ<L;A(bvmt
z+6{7xd8h(?eawapFwxKab1_T|FvIRa?>5t%49r2Mm5#kbOgpL;yu-X2kG{LiNk?$Q
z%$F!5bdPD>Q3=ue%-Yp(c!b$VJNr>)76t1cFfTn0GR7>N2NUDW-S5N038r8N>`pRk
zsO(^hS^6>*rkS2k!KX(|;WyxBnO7-_YQs9r2eD-}r9<70wU4Uc>{&cI`yXW?H-ION
zrLa=C%#l@2nFA-*^S_|gnRS)YOfIbZREg-y5|u&3jrHd^47#)WsSeD8)ysm2Crd_=
zDKFN}H8A1L+Chb%$5^uzJM&@PdmZCF&U%Lm+fT42sg%~2wTuq9eyr$)7_~o3zKh;}
z0jxQ+aSdcGrp<5=D?@-`2eUS(KqiE>1P6tAp{$pwn(ZXZKskai*0Y_E3}<bA8+s9}
zz*3+@vbGMxQWR@E2$rH*4F^DCSf>;aiDj*zLV-BeSqsQ1mXa#X;#n3p?LSYm%m?9A
z0_zD{w$8A|>ETRdJw|7(vn+p#h@E4#E`(1>tlz1?HksA(2P~zqz79uYD(eOMFxGk2
zT@$=WV}(+cMmlTaHB3ncOG@e1OxCA=11yUbmIZQwmGCY|HY+5A@(($zZt^CV^?V;R
zF0x*xqeLF7>P1+}XXR3w=@RQm0xT7<<k#V0A<II+pd!{&BJ^EmdAnkS#jL<2m@i??
ze-<dEtRVwX%2+3xVg3qh_c1hHWo@UcmF29+2!K_vexl)8D_OI&ld57J%!W)g>;2>4
zYFJ}WqVpPS+heeFot1b5eYLE`F;J{y6?(%`JxlEf(!kpFF-RlJnRc^HtUGZa&8!f*
zyL*Fmg05t>u*%~A*2=Q^6h5`Hj-G`V9jui)KzCYMhpp)BVy&5hiEh@VE-3b}swuG6
z%i2h**Dcn|R72Ru@}$>jKPz!Q{)Pjr!cK6vS&P4cPlGJ)-@pyA0;%}#4(pXwP`}H1
zm9DN0vv}Jfa*s8A0*&`syY~Wfge9RE$0*Bsm2#pFSX%n+jIl=OzQ{N$Zz-IaU^P%e
zd6Kob2V{!HrpVSb>vcL(&#?aT19`}*aEHN1EFb!U#w-gZ8+h>8`+otZE!&X-wRY^Y
zPr(a&b~_VxkFr0W11}udVRRgGWb3Te7@8CNTmV{~*+oAB)P+4lpS5yjFQy_|H+JKn
z0Ci_Cq6glCy;=`Tp6pXp5aq@G<QbUoX1g2)ImX^X#oRvZE{cjAXGbmo*a^0s4WND5
zOFswa$KFSQcz<?&FE9hxUkT~_7s!784`>9joqGWq%s#Xgc0<@>M<5f*o~AR?N%lxO
zu*2A!R8R<KFQHs@1l#d<^hL7seueoc_V!+wh-T|4ZW_aWpO*Dl_9`ppB98qUWd%;L
zvuF_U>^BdAoMwM)Pw~$Lw)p@=&#-s?0PIBe6m6)^vX@is)H(Kr9dJL19TX4HWVYwG
zXiQ=6n*eAk`_^9gd!GHYH|8*nok|DYbhfq{>KW{qX7pvU?_UF##s07deHYlbN<p&O
zKix-T4m%dNM6L63*@HO%y~y4}6@__hrXHgxVDIEXzmVNg2EU8g3pYdLGW(ZGh!nG%
z>GWH|?xB*PQub+j?#tNc^zh;en^^(LtL%D5cv#MEp+s^8`yK@~E7@5$p-{z+q_kEw
zdlB6-v(~U*l*6fO?2oEp_d5Hz#UQopBNSz*W1n=!%+#~f+#%AyE-M0dBRl;AC^oU3
zDK5~=Zlzn3H`rPK-(0e-v|hBbU#1PsP4*o+qqVWuW<j!@y^IRJJJ|i7WAvTuxs;dc
zva+9_hDJAg+Xon054)6(T)pg5=V9U&dujtnA6rUk#D4aM%OC@6d|C<*9{UwKbq}&5
z*dRmfz0`MyUFHhzF8jYcfDN;c(D#n+u|M1nOZVBo&%l`x_P%mpj<Q!hgoh8<)~Bct
zbBz6P4LZl!_Em6Zg1wjYC)sQRCTfcPE@fY)*)vl7MP}H=MvUSi+wwBFN9>UoU~rZl
zN@oBY&K<gEV$0c0RWx>-x^FSv_8k9DL5^}fXy59<`JFD=ICAC=L&1q-XQiyXGsp8b
z+;`#l{f$;v&Kp}{*NyWq2b??SoxSMu;GBtpK~Iij4bZ$e&$9vJ&3S4K96iQ)ax3im
za9;cxBF8z8Y|wXtlT4*ZzMLpZ<N0v}wCnfhOi=tKfb*gQ6aqPl1y)!J;)Jb+VlXG|
z7jPjQPs+H5a$G2qcarlyr7FTW2gAXIb6($oz6g#R1%skF49dmCaF)?NKbA8|UyzF9
z3<SXKQ=Br&)W>t&L~!ObCx!M22^{}C^qt{Y{$B&gIk1b)e`h(bc)-PToK$iqiF1Iy
zZIaA6Tnd9JoKMNqRL)My#hm9HrZ-O-=RqG}(mA@H(3rvD>EKKzC!-xCixWk;m<ycH
z8vx7ZEc_NIIh^k(7n948GN5;n<MAO#9_L>b)nDgx%#E0nOPuh0477l=j3%*=^W_}C
z6mhz#Qs6RYmZG7>oX03iP{OfpL0>87-7;`xoVB6AzQTFxNpM#=H)+)>=X^j9Wd+CU
z3jSJ^oRS16RB_&*U}`m|p1z+|!)dyYKI=8kLwb!~=h(7gqL%YG#f$4Wo%9;5=Va7F
zv4Qgjy*L{=N&nBvasHx^a5KlW2IK~ZPe+LsPIU`NE2o_Htv5OEoIqb2CzNUr+d27^
zsp#NHlF-=6=^cgLE)Iu^;kvDyy}_{5!+DzS^!IX-Z-Lz6Ow&=XkJA_i{eDjEhZx!b
z=K)pp-sa4ucg-LtpLTFVoTsGV?r=62K;$mx097Ona|Dz&xyKp%4?f-J#L$6pg!3x{
zV56Lc^oxJM*+F^EF^<)hj-lh6WmMWa!MU&*+$1N7Zp=?{hCJc-H0KtD9%eX~ogng%
z^V-K4#UqZ5EzHkyQtd%(xUZjqf-RR{0E2eizi9Qa=eB(TpB%X-D4OZSjemqbXYK;p
zJh*T#wFA?YJ7_%uG&k;iiodvXUtbMH4{i)4Gd;QcrlH}*ji-6`=JwLUc#ONH6Ma71
z)&1x@&gIc_e}em22;BDN_L^YOkE^Cnx%hKs^pg$XhPpyMko$n1+aT_JBb*85CU1hh
z5bn$W()llxn|Bf9BzI#hOoVa2NP|W=*JBMdBDiTY(1_%6K8HpWH?1FBG<O44@x*Zd
zphYZ}`wOieaa_qoD4gQHLwoUf?o$bH<}|mL&UOjhVydt?!`0BKJCVDFCjBgT!iK&-
zd5-%tmC+<|*B4+g$=qGP!9)tzxdbGY+h+r3&T|(Jz(g8%lA@aF+)RpCW^nuHHJZtF
zcm*O^Ts8ejFL1x^gJd?hnxdgO+~RRG=5ldC4i6qzPk)#^t~;f=^SOs6ss8K|_XYZl
zUIDj<mb*f(U@p*#xF$MvU*@LF1zIt;ly*xcTmjW(lycY6o~excfU4-Oa5q!6{8jEo
zdc@1Q?ewYU3a*^W6)L$)=;~<|cgh6@tGTIkh^^t)d<2ne+=^d;X}!)3r>`Z{auc3_
zMjbbh=DD6Lrr%rx_rWUkHF6o0GHBvHN8zq!?g2XG+~7W|0oTH<8HZjg_YW<`dz1Te
zFF@P4eN+YB&ehg|>)<Y$2a!&0Jyp_oakJh7ST|QlGt*<`4wON$k9%PoTKl<WM?nU-
z{iA5S&GqXB%pmtTU3?$nvgoqu9j+Gz&+c+t=R;(eTeA%lbdTG!2i$#bN-7jaxMI5O
zHp<mg0OJ8ycL(OjxPEkhZ=Ab=erprl7lL4Zl4~uceD)OAo5DEL+)E!rW`?_%wonhb
z&B2g)#O<ZX)-2b~31~LF+yM|<UPmo_vg3W~f-%|i`rn3YM|py0fbGD0{t*-$d4E2I
zMkn4fdJLU;q2(YhyiY!aJy%{8y+_=5IaVk5?aoVn185$+$~tIx@;sM;^Wr(vvgOTd
zr$oy!-sVoY=EGZ;i^k);-3>rH!K)I&8DHLR+P?bnCaFBwpZ5#x(*t-Rv}y(N8ghXd
z#B&IMYr(t-C%6{E%lZ^%LwU?EDF1how=4sr596JD4~pSD>{RjK@jj*$RwU1RIZQ<H
z4xR>y=808MjN$$ADY#hPE6)Nuj#oh|%qiZHFQFIDOTP>+PV<7U!+Zj-ir%7Uc-!gJ
zoya>&&*oX4p$^<R-tyH{f0o31L_wis-XdC4Qh1B#)Sb$EauVb`k68uKG@f%1ET!{A
zOJOO47g7buOkUC^=w<PQbr{+O-aiMRkj;CJV#qnX=;xr9%UecC+l#z~pFtsyxAtxH
z<?|X|g%_82;izq~&MV;MYv6DpFJT8-i+G!)@a-~hBfTYxc~!JmEa5Gr!_F1n=2kRb
z<(>Egpyj*?ddXDqu1I0Nl9z7-^(tOo6}W2N8&nNb!~2EyC)ao{`a<tI?{}(NsO1^^
z;YA%!_8L62*7NrG!bAhFh>B7hc^`CQOijEI+Eq65_UEJT25&G58ZEpsM@&L1Zy!As
zH+df0V4{sD4FXI%Z><@mgBQieKs$N)(*Wz@JxAqh-8^^N{P*x?-$7q5&yDhiw|L<+
z>OL#ahbj#Ec?U|MF~EDD${TO<-g*`qgS?;kaCnIKIfY;E@Iu$3?=Ekg4)(*mM7m3I
zkGK6Xko&y1Vt_Kj3#L8dC~x(10DHjG{0b9eJliEu80Sq>;$ec9_6)!#dDp0vXo_cb
zpdI!!@7)=|%<#l7W7rRQrEkOTBi>z#AkOkkE754f&p!$cTmCfFc-rx6sJO+RucI*a
zQGVw!*mdAvErf_8|J?v6IPsGyt>w(WOffJQek$z|UHSiHqS1{XL`emAez(;QtOtK5
zz1ltbUoS<g7k|6}#GAjx6EMg4hiw7s!>{}o<T!urH?Vtx{}Eld@Z}$jfO$WDQ~}ie
z`59D76u{p;0A~XEnM0VaAigJUT7voZo|uFXe&#f|Q2rlON_3LHtei66VSMIiAmRMr
zX=p_7?I`pY$*)g@`6zxxGCYjtw?2glis8FOqA!-eei!=U_%F#oPVrf^wT|b%%tPN9
zej!z?B=X;U2ViIUZ&3K=9KYfYND}{p$I+L}Uqe?bQuuLi(EX!S{+$u%pXa|l7rv$O
z|MZ4pIzNS8XBqtM^qsU!{+c#$S$shYoVmdF{0<`7{G$qtDTn{h0f6T6{kcH7$oI5D
zB#&>q4|@6h<zCRc#LsI3bOHYeRqqt?`#ixF@uylS{&JZ=hiYPr`L9xGLJ5Dt5_nq5
zw{!xujQ`~zEM4J$M)B>d{Nz7jqMSdM>MJVvpI(BcN`7AjK&$vZR3BK)|BV8sHT>KS
zAlLY>G^6o4f9qm6Q_Ek*1gYcaT!vmf{|$PpSR43reu3RazRn8<oA_VSi@urvHpLEZ
z@UOfMu7!Vc8TwlJPg1eeP5vRe%iP8<*#^?iPo@gu4*pk}Q0U|@pxkX2|IZ^(=;mjA
z4TC-WZ`Q-#UjEYw7{o397#$4y_*-cY(r@K+BB4LPznKL~w=pLW9po?dfc_A_ZU!#i
z;cqm8yUTyO6(YlY$Ctp}<DWT)Vc+Nf@&Ob^_&v1dkMd`}gvbN_ceEsp@lX4}(m4NJ
zT0$rIBfrD^B%ei>)u#A2|AOQ+-}+G(*cpBpoyQ*X59VVOkN8{YTR5})9hBm*5p+;l
zq^;mL+OgUR9{&wK*$ZUB5IHLNh|bv#f;S`>wxht7)_f<ybDKe&1&e95bP)_vbkJ20
zdkX4qf)(^4@D#+~!XUf^gVr&0dJ7(R1I#hOgb|89f(Y6>9TzO3ljaG5jSDn<1-AVl
zeuDIUfbkdb>Btoz;C_n{1`2j)F_<91Yjgk$7C57>e_n{-d<Q%X6|m{D_DR7r6dMf_
z?4S@@xM1@xn2ivu{DR^yk%E&HLyHn{GoTnPXr`lhjNlvvuVV!tQY0=;@MkyrP6^Z$
zyp9*l-w3qRf@O3RPY@(g9^j0i!~-aaf*<a}wX=dKHvBy&U}i%hNpPbYeaV8dJYc2>
zM&|-ERd6((-hbx>4xYeH6X<E#N*APTg82+V&T@ce3Y^<uB1^E6Ds(OgQu~0NEl^Wq
zj$myNOymkyQ0VWXV9m#{lqdN7F4Xe{i|99ZNl@@C^a=#Q?I4AMA}aYR5)`Om=(1oh
zO6u_a34v=i=D9>*rP7{K!7H>NmkEj-;NlfQDg_y@3MLMLD;GSjgrgOLX!__+r6A*d
z7_1U#Z$htHu#v(>H3Drg)UOGA=%&+kfjdQNY6Y8~g-D&ixDI;tf*dK#Hwd2F1`%tc
zz-}Hon*`qvV!X|Q*XVNY4MC$V&{_n+RH)D@D2sx~O~H>}fNK*R_z1&p7ZguHzeDh|
z2Cj7q_R$%-OYr$ksCNt2ybTjQf{jTK=@sZG40B6R;DVXy6LgZje!)A>KxDuwcuNJD
z+k$VuMC+j71A2=O33NB$_pl(7GD`OZ8UKIB3D(fejtC0p!2GCS2gP3=2&$r?J|<|P
zYPNB~QK~<i5KJ6H<D{TB5M)YFO<UV(!RQtkoDr1ugFF-*p-bYA1lFt{KxYLP--3*d
z@DhdoY=vLHh*8)HU!{_Cdm+0XFh_+4D39PE%$N%WN8xi<q2MIkN{_L#u%B`<F2bfZ
z^tlS1D75P)ET9;PyYLRBdpv|0bdA<iSV)0*FX0qTm$$IkiWuCyW5S2D@$?ajIk0qG
zXm}lHCxi=WbLcC)Obd;l@bM;C@)tf$``!Ryl>vQ$!kkcyH%Q1CgI=(3&;c_OBJ`&r
zg$m1fASZ?EX-gd@oI^`+xNvAKxCr5A@1QSIXi2vMJ4$$)_8HN_YrY^c!jtr(j}_KX
zt}RZuk`n%>gnMXA@j?$OTR1Iz^K*EZAe^SR(ix#Mr2!L#ArzWDD^$@B;+(LOQVmH$
zFM7cz3%#h`Cq?)}JxHo>YClBI3vVx?_)D6wlHLpHLPj|BGlX)AL1zjh*TIV{VYUHY
zToCdoSf4GtP3Pns;WjEX$Q2gwA#zdJN717^p?Wj=@`c-K(RWGc^ffFM2+tHjy-?_}
z7vn4vsv`h>S=bv2kz(O{Z_UB;S0XI^6f&j4@*QX`6MjAev@610?*jX(a77dP%7trB
zgR2ns{st43LbsOyQze|<2y#tm{0DAd7cN@}gSEm>JTS9$!p3Om)eA**q-_xH`4N4M
zLR%pun}k{cNVD)dedEY_L#U)Gs}^D3RoHD6zC)LjZVI2h0{u3j9fkhdg#%Qo-68bQ
z0=rZAwE_BF!Yymj*Dd_~F!XwaZ+r!jUg2Om^lk~S()+7Vm`XACe&NfsOBxU+1Y??S
z3kPk{Hz?H7Mt8_6JlYAgJ3>PUu<r^5w$K<BZuuHs+!L-Zg3Nv4vpdi?A}o3fWK{Sw
zz0Mv8W6Aw7VaZmYjSGAC0((Lj6$NfmX!j4sJ0*PoBS23J)gJ?FMi{S$!b9OaN+>-N
z`chb7R%osK31~K==O~C}D_VUX#7>k<)!6nT2IX*%imuV!H3!j$U%|YiC}#;2oJ3#h
z(B~|A`A>N0B3gA8Xs)6ksZz~Nv@Z{R?xGE}qxTT4eFJ@-qNEg<_Y(EdY1><r?ErF2
z^n!IC(0oMi(<RsAB3(YX6QZC0#3cBNidMlHKaq0>h`&flOL%~2Yz_JXMG4N(4-!Sv
zW+_;-ZZrBqL@ryvg^CnZkbhFN>2pYiiT2ZRIb0;~0T&@!p9-)@(Tfy{juI`iQ2sAk
z#A|^}jOYallEjKG(AGRo^veIkDIy*{Rq>*f`5>o7b@9MX5WPT0kTaqXTEY`WFVJAl
zidN83`kZJVg}{?URa6(1ELu8?zsPyfPxOh2G*LR$mZgh=+dwizFFZr}hfL8hMR>DB
z+4RI+5Ur#TT(;<!6L2O+#90lJE4oYfTP})hHp1^bQF1!W=ZjvX&G02rAw_r#M9(B+
zEQO*L9!QbsbqWDo7R^}#FN#H5DZN`FTJt#UmWmu%;L1en?P>pcMf70?9KI?lqEk+}
z$U-}*3ell2pjat-`fs>aCAu#IS1oF$<7bVie*)OoMA1~HbX}B8mD;tUM^tfLCpxwQ
z=Iceb=qKMGns*SRZxk))Kwpz+h7PgKq8N(J+z=h2r^(tP>OBkEDyo+Q`=;p9yBKJj
zXgm<0?V?57z;%f1++e9wRO|}SF3}hVK6Q&+u7dQ48sCLpuV@9GJ8y~p_#N1Nq7)wN
z_KO~kKx9BvnTiRzEqa>HJcA+|3L6cHD&7Iu9jj<B)jr)7Jx!0}uqc9_^n0Qh9>{&s
zNAJVo5z#@4L63^QR6+59h(!uxqMy&AZ(P)q08101H!lEtQuOD~AXB2&Fpz1{cT|!$
zBicasmL7`OuE2aGvRj4W&Wa9H1I0#cUF-``Te16fpxKFgDT`t+j%PygsCYAlQ60qg
znIMkh=bp!4oW$>30dW?eq<R4t@%vK%brpYn6r7uQ)iUV0i(8(6K@YL=eSmq2yXYk1
zC0<#MMsM-8Fo+xzkL`zfA8~-S4)nPA$X+<*Ck}T2=Py1)Yj1$Kf~t4|#VNHg5hQ+b
z0nmcQu}RPm5yu+fZ>ZRF1?-*_za_&U!o*L|1~6RQeHR8J#J&pv7Af9BReMq5t4KD_
zix!`uqj-$CXF0%P#a)}M7+Rdzfr56Y#QW@k9WQ=13^J$12ZsQYATHVkaz@OdWJ;p=
z5S8Yf75Btr63&V3XkV2i{^vuWB#T$m+L<EWei1&UiZ^V4-g)sVy33d*K5`V8>EeGr
zheC$<c{*BV;+`SxKeNQEWWc^4{%R61+2TbMa?BBbOL3!Iv5JD57sWRpLt~z}=>Qb-
z#nE(K`I0z<iiHcrr&pk_P@GP6!A0Vo4=}XL;;}(kDi(kH6}S@d0M$j6iZ9UrcPJCz
zss-j1@%pbQ|8P}orhH4eSVpDV72*h5`YXlX9fLDf;+H6$P%UQB?yN?9_!UTA6W^u$
z?sf4r-SDUtH&6h-PTao;ef8pF6d7(1Tj;glC?4De^G)Jo=V7;5ocJOv+z_vzs>&Ae
z0y<G!Tg8WI@w+L0g(CQEVta}pwu^HeV7Ehj;~+?<_~Ukfc8N!kFqzja-b9h99&x?_
z27ASad(d}Fym=6fed2Mtt<o>n&;e{fyx9h>-4@601oWWzaf(q6iAze*cSpRQE*{*q
zirXnxGA#Z*2Qv4>Tj+OrU;MN^U`E8nBQTHu&Ps(K55)h{R%Ak4Lb3Bn@s~{?Q{wFc
zG){|MPQ$es@m-p=hvLOf@ad7bkOFzL;!o>AY$W?A)MzUij)I<@q%Hs!>?PI>wAvn(
ze4h^1L6RE>-y9|OJ@^ATN&cLKPtKC`|37MytrYllmDEuJ&rR}%0x<3pKYF=&NdAa`
zf~VvTZ34U`zh;4WOLpIa7sn*mj>CH&$?sHSa$Ms2D*8@HzNVL{uO#IE-(U8V_-DXH
ze@R3hKm#O&CFl&41kuhQNYcF-`oWTOzd<BKqNYlWP)Q9HM4gm)P!Uj=WQ6t!;gTol
z3qlc+w<zZvDLK3VT$H4celyXMKfS@lNZ7P$#Y&VEI*60RZni@Il;k^lV&f$z=qGSm
zvZ@kXg5(EUsLn|CTt;J}<ex+g^sL1D6IePYaio1hk|dGV&}7NaFJRVEB#8+CO_ls6
zhWdF)cnADVljzFPm@aYq7d~Z3_OPIyDJiFSd6vX%ruvr)l7D|gXSO8&6Da0Lej7(;
zuH=0S$VEy0I5hGk_f(j@e91B@V7VkY^bxQNB-wTFsZi2Ib)!WR#(Iq9vSeT$NU>z@
zD%dTNj9&s~sl-S}rZUN@zd^1@79<1ns$|BVzW-7#`Iq)76%xm6fL2Nb^mnR~C@DZ)
zE!my}v>HjoZlGP0us?v}b;*h^;99LDgf?Pz67QQ3sh5;cfkT6&?qB%SEZIhH?;Db)
zLy&BdEXW7fDv2IK-%ZI%UktZRlG_H(+AfKv!E{It?S#Qj$vd>%bx9oJ;6=B@^?Atj
zNLs!DOt0isdhl*ZexWJtlLV#$v|sXY4;lv~?}tF)wj}cc=3-FN!3D~Y<cAG#?T*A>
zjlR2*<{x2qSmH`Cw|kNk45;6?N^0qRF(O$&Yv`zC+8><{Bsp}CVN6oo3!la%f6=-=
zAzAP-{>+mS)@p!GNwWV0=(OY=+BM8bwx`12LrDu={Cgz%n%;)9lHbB%!bU2%1G~0T
z?|JC6la3?;%wF0~sk)<5tA`jc4$`mAfOV91jes~wzoOumvos+e8ZOf5vk-BW22!BO
zO*%-?RCnp)AA|FdK0`lQPiZFyB3{y;=fj}4bOpsmk4ZnHZH|xBJrRRAE_D=xoRDt(
z641WV{r{oQPwHx=iyr>cP9t0lkREOUTA)-yf6*XmKV3iwmbTH2qY&v|b73%4>PweE
zPD*XxhQToD<5ds|m+Gd_7$J=u0T(I#i&m{D={J-ojh5QQ!)}c92%?MgVx@V$5Q&r8
zQKif&sqs5{{^F$@_2@h;{Zj&`5~Ny6C!CS~N2_(Bbf_Jc&Pog31b0sQMH57lq$V3U
zlPo=814}8=i{x6WbcU9l^U`g9Lm^FiM~239>4Hu0B138lhZmXBs1-1jC7o;lmm>}P
zj=sN}D}9Cmn2XYbTi{flv@{)x`O@KQfVm{yRs~WZo%s=V3#B4^_**0$Jp)UZrOzJ$
zTCsF(He4%_zO4c&mHxN`q)f^=3lmqQl@h35m3mbHvs~K9fnJ65AO%M%rBR3uTIW?s
zzrT+0R!b{AV4_Cac@_>|lU`#(@wyayH9Tt4oe!Z=C#|{(gZ0wGw6Hcv<sU(>QTn<w
z^qQm}QfjkVYD@XM8`2w&=xdR>Q7L<?^wmW4-IT5tK)p>maU3G;Qor{gV(pMRQR2Q+
zD&C6GcS&deUydSm9EXV>>25k-^h!4r!HZkciA&JvlQvKtX1{a|ty%-pXEhkwZRufp
zM-57AGhkv!ns^A9cch(k@$as5?KKR0Semg1diSK;+hORw)a5v!N37B<w6u&$y@S9$
zkTzWaHzv)R0?fFyXgA1&bZ9C1CZ+%RgPW4RnGVotY2O(%&Pb~l0PUf4?jvA7l6F#T
zbXK}&1|zhQg;8wOR+d~2^LDZWPk^(R{k#s`QQ6$*;Gu)enn`J5N7=pSFc>G9Jw>RT
zWf7xjbdl8;!-T8s7EOtp?9_KqbeH{3p$89H#T^h&neKNec*%N~fq2WtXbn6jOZ*Le
zKC*@eaK~j49H5+#sp(p{udF%<hWupuXJEl!cGB8|F$KsHN8xaw>;SD^K{7q<vVvuY
z=_<=fS#A<$Jxt~u1I2I|R&P9Nvb4o87%4k2g}x}+dt&HC%MNbCB*e&8FT@<i%0Bal
zNSw_60xX=8Jwsp5h?jNSz|d*gZ^hseWG&a}`8y-qHWw}?%5rF1cUIOz$JcYR_XYry
zBy*(mU$QKmKGBpS+eh)2RM{*ABF@WZ<3Q46!L3k8m#v_;aE2_Y8rYe#_RDZBOBTX~
z!UdT@3g~Q^{2uJ($ljy#Os?#Y9(w;>lyMh8BTwc;!S;NafN~p`WN*@`yFj+e0d@;z
zzs^9vNVYy1ikD@vArL8+3BLhaiEKOVxk_aZ{~te*eN4aOE3!7)O<t9KOSPfpvL{NR
zP$6r@j%Z$`Y@G~xRWg@rbMX9C%S2SxRU_-Mg%{UkKh~o2y6i(|I8!Ujjl~G-WJ@S>
zS1)^e4*D8o{X-y)GW|-7ut_F(5}?hpa0-Loke#Rj*CNZ|z^7JOAZ^KS%J%ODbepU;
z6<oV4j^4=~vS7-GSvzH$zK2GaY!O9jyJdnMu-hZsM>RdYvf?n9za`6!fPSCst1f8t
z%NqJ%en2+)5fpCAT4}lmWmSuTJtX_95+ZkGnVT?OcV*_Qn1o@O_;)nklbt#Oa$ok!
z94L&)PG!UUQLC)Y0uv8pF=~)8S!gLb$7PjN9yuZFqaWL(?07#Kr(|<?!l!9jI|DE?
zvL72k9?DKoYSKo2okAA2^2iV2nw{K%icIX~DO6Z=RBj!Eq=USj4x^6p6;z(@B!8|O
z3eIxtE;^XF$k}#Kbd}$xx?(rEr5@(p<zhP1ddL;Q(D0Q1N4X6z`2q=M&s#o!2lS4~
zZNnhxBlo4X=(zkbKBnY^{Cz54^Ob*35ePqd&WAwpm%sHRBm?C47N9RsKJXJp79_uC
zeGMAH@>eNV5+awU047wf_Cn`Lc`GFa!{pz;g3*V|&(WznLSC^2l96&NJtI-_Q#9St
za;MkeQ;fXxbx6j_y^aGjPX7Cw;7-YJo`J!5`BWwbcv>F%3w%nD|8@a=XXFkY6#q<=
zpQ2^!th`497thI8(Ud011)o7NSzc8S>=bz{r3h2y%>f|i<^QqaMVh>Wj``{GAL(*m
zhWsYIMKk5UZUA<ceDpt{T#&yN3WaQW8D&9o<cuF+K38tH42>7%=f0==w|Vm8=K+&1
z*CnI#lKj&pz%G!lZiYsod}BPgBKh7jpk0>pk3+Foo=<B^iQGu1?o#=c3j8U`<nvE~
zyCUEI9>A{3hXnvDmp6(rzzX?1ItEtCZ(f96mHa&&6sqNiqUrosBhPPw%r&`A4Vmlm
zhjbdOm51|yRwoapja<F_>Tj6m2Kmp0aHdiI(?TdT$=B9Fp;^AL1ZX$p*R*JCk%!P*
zxK+OTKK#8Y@6AMCn|x~%P&(xs=t$coudl?&y5*KJs9SsF+jy9-Uil}-AbLxFgNjW0
z<a!%;+An|gGmruKWI6P2%PX%yV^D5$6wVCE&(xvsjy#1THFxFf=>Mk-%hyp9=bpTr
zHlFw8uXV$V5&4HpF{Dws#0>I4J|`CT#^jR}(jB+T*+=2`gglWVTa)q<I!#W=ceVg#
zTF#1r%#7SPA0{5kC3Fk;k^I|jz@C*ap@gB0LUsYfRx#oXY&%6_9Te;p%ijifRMEhN
zf`h`JE>=1!mhpk<q}V_e{LTs+I-a;Ftm|pna#hTG8t%I(`n@6JuCU{v(?g-7U5BTl
zpdKP#iojJM-U^(7@!%;|KL!OKMY0bj;ke=-XMmnij9morRh&~{NPdd6{~+S8cpuB`
zya0vmPf!n3+@-f@kfN&*ZU-xtSx;ctA&PtBkO@^xUW37til09RXqe)M<7f<5j40t#
zgd&VWVUdb?wE9FTDrjb-6)qI*j#0SM=aga<(@~hGIK@gTBRi!~On}5Il1gCVv|_^q
zpc54GxtO3ciZ!%oCMu@>pR7KssG<PZImN;EAeyAuO7~!s6$2FdOHn-d1Y=57{7V_i
z^NPEaEKXB|XF()gkwu%l48`KV(3hzwrE;(=#Si09xS-hZ09>}>_DXn|qd3<KE>}^R
zguaW4Ep&|`Pw}Mp(|G>!6|c+%%q4|zHDHPq-_w1`%Zg10AyceKy9`pIu#3cCN)<(H
zNR}xa%K>^t@zy&)yQ*MUqOV+WS_s!F6i4XhYo+4JvuLbRl&hg$t$4BvGgG6OXoiJr
zik<Ycx~^b8N9Vs<#b+LXsZ-?8XY%S5(SN~2gQ8^%WEvH41&^BIN*Vf^6(0-(?S^74
zMMYW^;Y%?=t%`m*`fe(UK7(GHLPingc0~^TfIAd@?SSr7ETr^Om*NDSZn_meZ35|0
zG_av=?Nvnl40=m3PP@uJ#kaKW?pL@rf($4Y(W(2kV(kN94=RLTp>arYo1)Hl6h~gh
zK<_F(JPWj8g@|^l_Y^zn)qG!}pt{i!#SMDJjw+rFf`<?AcLms(VsSPGF|Jre8=?uT
zVurTJlZrT6E~gY5Y2Q1oV7ftLMp69|EIm}%y#dfiiZ5OVH>+@=8c!Q#r5V_^N?{u~
zJLRh`=(AVOQmXH$(uQ6q4$9M1>*c7lXMi{<fBgf0G-qYueCW9-<3EB~SEcnGs<m`e
zCKZ8oSJqH%xQFu3_krfAe2KQkUdmEBDtaq5)!>dP|D_OukMbV`&*mLh{@e}F6Uv|l
znDAA8Pj5p%Wf!I4{gr!sU@1WPLo@y&fy%v?fElDr+y;eU<$tvK4^akKCm<85L{t(F
zp7H}%kT7LOGc1KGed#J#gz~9en2%Iy>2hC`veg}ZvC7K_0TZWmRzUrfl1W*Gc;%-z
zVE43gxd?+uP}bN&<czX`a`TDGfQ2x4R{1W4U(YF@ru}1*vN+ZX6UoX}I>V<Zs|ql*
zRAnbs;-6Pe&=xmMnMkj?bmfFQU^0|86uQV%j{SwcEM?A7fL>5;IE21z<+HT-<tVkD
zAi2sMdJ$Yyo}|5Ao>DjuT)r}%?xkH)+8h8WP}V-6`p-gTU=YxXlrLR|7nhaaQNeey
z@&etKDNzPDps!T<lM^hJDGx}1c14N*Ad3f28AgB6a^>^%cBoK#m4T~Ny3$s$O8GBE
zcB_?3ZUCi5*+qZ!YsziwAaY%)iUwD!e0YY=e|1X3efU<dTs9w_4a&wexZkM!+aCjM
zQVL##rDkQwe)Qc?wr@vYi_(i8l~(0(8DMTI&(cYzP5JRKrnFsoVHgS>N&yv)bt-?p
z36w6S*$*P!%B(|htw*_sP7A$CzZFoo-clZ8!qYxw{FfMLzw&kZh{u3ZG5`~|m481A
zv_a)gI^_&0r+uJ!N4at<oVlyaD?;C}^59ySxTic$S7+`keU%_1N*3)gN0p!SfILt>
z^)$$s@(evO<4PMUN}Eth_5f_ss+@BJFjLC7K=?MT{5uEwGs>?ikN!{@p9o8jly9#A
znN_~QK%<Rn(*|(1s<Tv7YNzUO1-8BF)KZY6sxMZ8IH=~IL!YxMvkjJ9R84GHa#a=6
z#?ehx@I8pTDwU%19x5xQ9gmud*M$*!sg`;`!&_A-hlyjV9odlaQC$iLcU*PmBKl6K
zHarC{d{s&+{Pa_0{tkcrRW&=&7oa-#HxvR@fy>Ysq}rAX%wSdZuOK0+&+lOLp(?*<
zfSpvuFTxKgOjTy>hWT)Gf{jqcJOXH>D)<X%M5&@)1{bZ`PTB1kRT^DfidCJU>oIYv
zHLW10RP1tq#;XK8h@4hc(jh59b@+F1XH<Iw;8UW?ClMCTs^(^bJEt0^olughl`bVE
zs~#Vv^IwXpEfCX|s%oGTf%B?Elm|~!<x#9LT@^re9T_UO)6maU4bDO#OSP5~yBAbP
zS>Uo&&tfAtFGn@s1zfJ`-2#}nsM<;Ku{_mhR5p;WDj0{zC6$$l#sZb+Ij9$^-cG0c
zw?!%`#U(DQo~LiT6sxY&5wk><Mj_Tx73Vhe%Tz%Dz`mmDqCnGCRniU&v|JVS9{MU&
zE>b8|sy1Xoy-Kz7J}gzMu2U$hMzuZ;^K?yh>{VE}t~x}q_F5J9KGf?}g`M;8{MD<z
zS_w-Hs&}qJu~GH7Gc=l1{g1;^v+4>9jW<-%RG_t}MD&VnRTXamcT-hPw;|e8-n&8C
zRh<gxb*O4+OVFu$`b$hgm+IL}G<K^leG9Hf)fNu(y{a{|CAg(pKqnFFfJ(IoGPhMf
zoP^Av>PjT+4ynGo4epMruN5+PRW_Ya99HEUfqhSvPFt`0s?Bt^98o#jL48zp+6Q_M
zRBKj&8&my8*9pc|m9#IKP=zkQ%uK32eg(sxQn}H-Xj=6j-Nl-*s#J7G;-M-?0F6hg
zYRV4Gsy^$3i#F=R6c?~nZxch&PJNJ`UwidCRBv!pEupitgIe$(M(?N=?1#FOdW$3a
zoYe)N0MkXiD+|O`-6=+&n|jI?(C+H*DGTYLeryVTo@(p<A&kOHT}|by-s*x7pdC|(
zQN4nX`pkBCaa`R@QRfrtCr+c!SN%;q^!?OJo`Jr<dN1V`1JwUKf<mCWwg4UmsoUuK
zM6mkU9jJ$>hiI!9sxD~&cTyen7Pv6A`3azet6#U$vK65|?*}g;)y=ao5v9&b228a2
zAe~8L)c?^oCszG$H2UJym9^kbsW-0%7q5QH6WnQa89f{c>SS7i&!_|DgCwf6DDHDs
zUF{CL=hSI*{~<~3@gw?@)$DFSr>OtDP3ON<wcuB{e_lO7ey6FQHvl_b{T96xGt@7<
z0qjh5Y&}Sp`uPP=xS&2n$;fPV92W{X>NkfldAaI(y0Ldry_gP#d1|lsfs(JTq<z9A
z^?a(fFHryJ3ZDwq3^SmM)Lp%lf4{6=c?^?Stk%)-s6>65!h@yihCb+*sXwrSD_8&1
z0j@%Qfu4#=bs1d%s#3p*0<wA4YF{^)s8NSXA#zQ9_b?Q$t9PCNX05u7B5`%<{S<$x
zSGzBSNQ3%vCLC>4y9w$3Uz0j<3NX#;su;B1P}{!;-&)i=#{k-@cHfAh-Bg!;hsHLw
zaS=$nT6hhPcBsd<VKANQq`v^#rT&)AQQc~8IrMteyXc_XtG@XWpl_+)S`X+xb?rCM
z>sPOyh2DVr&0!GhZFRyv=ntwnR5m-LPN1{t9X0-E8Xi2giUvBY-b0~>d+Non!~A`9
z7nP2Ts29?zHLCvG2iOnPuJrR7Q~&S^^v2c0pF?CqZAUe2lWH#twoj?wCXs3NE+2@@
zsI9SZ=Al)6SOe@wYNxH3uUYjMdw^!6`MCz1t)`cvgm#)+v|qQ^xKV`ns3zwEhUTDI
zPMaP_&8t*c;iM`42W~rSe#ro~i>8XoNnAA<ls$3N`2GpbUGw{YQ1{T3bOX#&Gff8}
zFO4<568hen{hqLNOtZEF=6y7u(Mj{TX3qa}b(*cTZ24-w3<8Xw=BGlK_t&ha?PP#v
z%hw=*n*Ay03(_p6x~O1{QytVpG>^8TFH|E;fEOn<B~;rPrs2`If5J75{oo=rpIM)P
z!;zX1S~a6Iav>~5Yr=j7iP1Pv7Bg1!qyp0xr#V79>{FV3R2mSk38Gi?X-#$j)Dtwd
z?ch>1iElvRyykCL3^Yws-v&!rnmd$~xS*Nog=Ds-?N^B8X>L)pEMF7;HSN+aX+EJ!
zx2u{%k+55#sreQ%m6{>SDpYBT=+|AX*+PGx8ckFSu&-$r?S{g2%?t-zt>(S$Fkh!}
zr-)jEre-rF8#Vjs3U-qwflkKFn%AhZ;D$zV8<;Jcf9PW+H#HmmY5&=#Ig*1hwQIcT
zvql{nb`$hFHT4t=?$&IlrKLx+kz$m+nuG2@yQS%%^m3nO%TYMmuUU2u*aMm$9HB6%
z>7`BdkmmmX1A&@vgVA?a<4W}$!x}~@+`gx2p&Ew!nsDr;t@B1S&(JSvRFjm2&Ig)R
z(cs234=J`YuK8{`Je|<IOIfN(O%`pGr!>BAfSb|$rUCXtjUOdgA8G9SAUUhqH3SqJ
z?FuPSY_$t15Mi&qTmrX`YD4Hq>!AIPVsDPx*AIeNowU`r0P3QhPgiJMwNFsY&`ldg
zSCZYed&@vPv{iHf^VG^|+wP@Zngx+#TFW#n`DooP!P0T<6uodyXdk0wzOVM5P7ptB
z$4BrfP`l<iSPIfsAAmE#+HXx5S%~(RJ?IOyYW=9p@T7Jf?Fk~Z49bN@YGW*riPHX&
z2)nV`mlwc`IBl63eW$c)FOUT7^JOr2MjQP-%qMF1QV=Rhn?wiQWNitZs#3H}Dpg6-
z4pLk@U3+W{A{p9r7Pt%A?n*#sYpu(_fm1o!^R__C(++0AZoc-+J8=J!_J@anDbRi&
z4TFVRW-I!Nv{D)TF45kKM`NjWG6h_j_D~%9u4r>9M{rg90@aq5YeSxfGgaEnRJ2sB
zJw$QH8twa(2)m|zRSNUhwUgEZn3`JcLyFrrXv^s^+o)YT3eu!KLMM?H?K5nkwQ67O
zgflm_@+5E_+G!39c4~j8U_qDmYs%DjYft6CM2~hQeUGSD>qGC<J6cve8t-a{@*py-
z9i_3{(_W@p*8AGWmeBJzqMaiJJE}F)w(x;=108+Fv_EYH%(%8T0wNRIQd)Z_wSJV=
zp3;681%IctPF$ePXrCwpd8pk=C2EhfpMDH7t36_aMjPD|zhPo+bpdpbz)lxIyA6BY
z#vcK8ROe)+{ilO&xDkVK)U{B3p_8tP!l2GN(**3g=;nNmK3Co51dQHI_Zl6r-F3Vk
znD@|artbuJ>UJFf@zO=m1y&zjWIWW5>!yEz$O+y1l==46`BFT=Pxp2+`uuhNY3K{k
zo!mv=e+ksB?}Af7x@#+7K2-N=5j;Jq`|~xBFr5c&p~7{qO=2!0bOy><N9sD$;6;?K
z_!Q8hb<Zz>NQ`dVn*fc~iKz@GPG`Rr>Zf!E76Ce5S3nQtX`MV4C<(eHR6CKVYh4Nj
z>sejtNzik;ED9th>E5aXcCs!Y1u`kRQ3|7`>0YKP;dGt95L||CdkkPQb;}vBl%*S?
zL;nR`9VJS#b*$InVUBKb3b<U|+89j9MV$xzF7k98F9IcB7bw7VUDEl#0t*FJUDL0a
z*+Si05g?a!3kHE*s=G+X^)lTxdbwTEP5J`#s%|zC8s)k<+2AU4k5O%QrS3Yt@2hk}
zThLdnvwZ`kMyF^5xu$cef%<jb=nEjVx^F1QU8h?_frNV93twQ?nsnBA>F}mmx9}9u
zZs_tUNZFz@--U@*U3CW>Zr9b`2G^mROU`uaUZovPm+oR1^t*MQR1@B#i+T>ESN8>7
zWV@wv`x7(Tr^}#oRKL!F0<{CWn!9Mct^4E&SQyk@xdD_Rouif3*E>4*m1w=EYm~v6
zQC-vj_wu@36o4Gl^%kLTT(_bE8WXye|6zhAb+&K9(v;3?FZ!l+jkFTa=(4Ha;GwR2
zCoDbE-K|99tnOdhmf7iTz5}t>S9!tSQT-GZR5<8Q|4O?%M}5H$7^steIUNq2_1OUc
zb<r;m#0XvW^0n~7O)u91)LlQh4xESn+d}Aj>!aw!cT67~1w9}AH&nWDT>m_kAfC{l
zqGCs1{b34@1n7Ty7Ip*m_Vi8;(m&b>lwiGbmfn9M`dMeRhU&$C!9=+JZ3;a^=;eRF
zi%9*+>o5_euet<-(fX8fa54JK69A3XpQMVjIQ<(hLE)5s!~0N(*WZi)*lGPnUyL_F
ze}l4WsrnD71o*su9Yved^xsiDK3)H$7d?L&`hSiBEmNNohS|%~&lW@Rg8q{d$YkqZ
zqfZ{?=p#3S<m#WGs~H#da@qvs>4!YQ<?He9i}8Eb7t$}GK)=WaV1@d<w4xR17ka|{
zWxcH{8jJNyDdJh8cc=Jgsh+bQhOA}!@J#r2ML$Rf)~kB^4S*@vKSwvLD)b*w4Pd4I
z(|s6Pm45Fp0Ik;F@kd{cel4x2*YuyRg^BBW?{?_b>NkaA^mY2tr5I?v{xB6UH0a&r
zfNs>cErX*?`fU`XZ`L26=lzCNzkd!)wCMepLZ(%J{%a`S)UTv<vQ6(Wi@tXK?-Xe2
z&@Xm|rB1yEU7zaGhf)}(ThFG`V2^$;rI32{;Z&+}OD~-P>C<nZLXdua%oT70`rq22
zcUynz7|5Xh2P(lI(p!gLf>U?&0tMK+`hygV9oDD$Lgt=6ehcj0*Y9cu8PPN7fIX^r
zpi<li`qn8lj_Eg1AY)u#Ks90$dIQ~+o74-hLvl*Lo4!T$P=DtU$RqvHr5MYsem@;l
z?F`3how7IlZl$8OqlUMKK^zSCdm-a!=%U5X$-w^wXwHUnltpnde6Rombv4ZY7?N%V
z3lk#lh83Hj;9(fu3=^J)^>hI9GT71<*V`~oThwEQ|8_&c$8h2%=J&YaDy>B)3>&_|
zaQzKCiYfjXU{E{5sX)VfOlSldW|AQqY;cH!i4emWUB3u5ct3^4lZK345D7DM9YbTd
zLFxwe2!rRVK#Me_{fxdSLnUR$q76?_G9$+Ds}6m!1~n!1;tXvnV4gNigg`REuq%h^
zU(Ogz*>Eb+@asDm#aY9fV~{y#`1WOtBFUhjkJlv|{-e^m6vGczh@=|+rW3_^!~H6_
zoo3j*8(g|!j|!3*hHLXN37Lk)<8Up@@Y_q!yI|nlLSweUhJy4t274+<%r*4Pr}N)M
z!}umRoM-rv-lqA6fqUq@WcY(_jTIQi1L0bsL0$pHB18FB7`$u<q!)d$;aQ53ml)b8
zC{t?q@mrvj8CU`E{))kF8`Q5F?i`2tazj4F11k)BV!%}z$_61>WmrU8a%;6A!v$=O
zVQwH4uNlr~0PVV=egFn*4Y@Bsqt0;bB1Gy94)b8Q!SD+cq|vaCLPJdk)(OBg8`d3$
z!5fB4RG-vhuzMU}t%my)H@#`#XQHvq&`wF1c0(5J>N*UL6lCbM8ustOU#82DN|DQM
zL)%`+^cea+#b2$@;6smpzac6HCI$?-w6NYbG(8V)&~TCRa6^W5X;8mo*q00s?-~wL
z$@8!wpYqA~3{2Wj-8cN|0)Iyg-$(#GYACV-<$+-*MbgF$)*k`@Gj8a006SseH^8Y$
z!%uWhm@@R!A~bFIqyyZH;odB`hlUk(5P4+S@j9?)4ISTs*cdCR7{}K5loJMFXZ$G&
zjrPWrcVY0T@g*w3a4_CzgxikB*HVGvWc-T)_|C?^tW<OCVodCUc~|4klYntEI)4J<
zZv4)GF?kp(Rsht~_~Huadl^%{gfrg8jQxN)X8dFY2IFJgIs(b##!9-Jcf!d32Ar?)
z;y8$(anF;`^EZyJgM|R2H@OyQbQ}a1WNcVT`_EwG?g+Go822RuJJficDw9qchYCT$
zjMHDje7JF4J{*oPI{pF@Y4o9dc9hY9;t{dNe%kWI8SCk(IAyF(gctF~^BcjPHm(yw
zB*FL!CD6_o``(0PqA~s>aA%D_E~o#$dCtg*f@qTQ9A#LNjZU<nrx>5Qg2q&17$vmM
z8`TmtrWp(9Gd=0XqdU--VN4TY^qIzGd*ES~F>fA3E*Q7a%w`)ulE8}`V>;bA%{8ts
zhu%eF_<yjQXZ$%Aqs}+}Vxs)}C1d6Zh!z-kQ#!rS_yO&!ii{tQLiDn+F&~Y^Mjl0&
zN{lU3Oi*exY=prw;{ggZT``7JqU5S^XdWz;8^b;YsW5&^>v^SdfD45xqxdIq)y7H-
zP-=`z%fVeUCai~9>viKY%FNappBAIF&iLiiAoa#qD09$Y{38V#jmB~xden@2sDQKC
z*gphv!<bD!ofc!B7fiGovtGws+%zWVfwUPt&SEawjfwss9mah621vItf;M73#&IuL
z=ruasg4tVEV?aOHKI5OuA=+>3@WNmQj7xVz^tSQ)W{^Q+#C=T3ka74^_;kluOef>J
z##}1a7&bc5Y2%*pO-f+jH}X%y(ugsRGUlVku2b;vfpH@hD~=h>v_gy<Ke7dxFdn1o
zok^p$dk5&0G3`yjOdIRy6+2`6iYmPy8adAb=8-Xq0;jXaCfa4$n4YE-l&$INZJ4(+
zZJrN<_NLy?pm)?1xeCO=bmlKeI-35XFqxC7h{{%-O#>8Ib}`k5qtDfpOZB;KCXtm+
zxb7wynfEXquZO;;=@xA_yi9&{o8H@W^KY0xW^zr1Pd+B@IW!(OSxX>t!nA4$(0olR
zUxFn+)2I6Y=5IRmEE)q$fppV1(8Qt(ok6Ams=p34#Zq-gi0M6AnL<sr^|TnBG@W`8
zpkb!NR4W!~60`y)%JeTe9BtY|Kg2jw7wybXnGS_OGTyXb4u8*>{xM^M6HR8kName2
z>1hqiFeUyCOPMBTN~LC*>M0O-!8A)X-Pxu=s@2Ld9ic-~uIU`(DLj7{O%3ltKhHE+
z3zBd0Kw0LzOQ!VsuvB2`p!(55Q(*xt6`AHzj_<N*)n-^KHjU6hsKm6C^8Tf!{A7rf
znf`bZB3DdVDxh37y+Wb$a#JxWRG4(1z;2~!zY!u;rh<p`{fTN*{nJpaF`cBu(lrz7
z4&1+PT3iHYYE8}d;Ob10rvX!MdM^oFgX!mOAdMzL92A;N$JH29v&rFKfZi}MsISGe
z<|Qb!n)>L<&P|iIA4r?&2@0dMoBHV9Zih)q2Tg0I>8w2zyG+?mfax~9=L)XJ6y*!|
zdrgUzK)Yr7G75ctrUQ|H={J2xd7c5&JbFdmHVsFB8#L7}$8-&uE>n8=j>*dp>UT|F
zcf-SB({~l%?wLNPNZftX(r+L+VtSUgucKDe6?$YInC$7#JZ4(>B+$l9&z*s#3Dbv6
zaFeEsRPHxrI${TBrcGZ_A=e|*9NIq5n)ccQ+s3?&HkY>McUv*RcIHk$Sh6=Sx`f7~
z=6_}Z=3tJav!SCo;d@{@nYYqP>}<9kNk*rOIgwt6uI8pBpt+gf=z~Fb^TG`Dd6=sy
z=jCaBhYmts=6OTt^EUsq7Na<3)*9f2kD2QZ?znmP8}w9|*He1f*X%?GY(I0}E_mT@
z-g^*|LFRwx%@J(wp9XY@`8zAs8-$wAM4|Jf*^cU?!p!kUAQNsblS3xLoPQUfk>(==
z6J_4984A(nt+8-4#=NBwB-Y&Jhrz^|Z+`%C%6u>e3i0OeTLE_3e0>+76U;sIsGKo}
ztp!S=*=-Y`&ze^!ThV#WJWk=gB=g0k&`364N(Yx>_B#qL)f`*^XU>~T7h~9I=J%?>
zrJG;=33?gk-Ah0+&3ozBnPo2g1muEw+fI;d^Yk!Cj(LiXw7KT&M^L|Len6rAJo8sq
z(3o%T%%St&C37khodsq$N|qIxw;Tp&k@@g8jN-ESy#l}#oAXz|Zi)HJIdH$!{AMAz
zGP98)hgZzulsvs^-u61M%gy(&F`8FlUPtemO7m9wL`9YPuYaLeZLZ{Cf@;i#CJgYJ
zdGblhzh5`U?uCA>`85*^)|rn`j=tXfm<VVM=JxeyY%~|p->1nOV+BmJ`Fl!<-Y`EJ
zfL@C^kX|{h=5GpN>8AN73M6!xFWN$+)0}l02D{9v28^uR9N+`>9<yH!T<bOOq^n%k
zTjnCFsP8k+sG;9)UP?DL2F$;2g#K;wC(+OtG=Dn>B12{o9SrW6U!pYAU9*)c^M=iW
zdFZ=m{+c3(_s!d=Qf9;~qmsH&bLeS+Jun}b1A}Ac{kzaOZr(}1gekM19_rIp^DfGU
z%$RK`BlXa%aEIt4bMzgUpEXZVki*6@-3wxC*%J;Ec9vF3NZDJ=%b{@8qInF{<zOis
zgIz~Uoh`teEKkzU!`b3Ymm*v&4ir*ywd7N<z|F$n4-t3E@_1PAuvk}9#f+!LOb0kG
z%S!~~ZONri`5d!6Ll-@KEIDt&;o}w?+CHDKM9v52YiadIpP%LXIw<&CKBKiPz>-0U
zl0eHU%993JHoXZh*s_SyyCIfLTD(Fnk@S){X>oA`3A4OlwL@pP<q_q<BP`KLz>c)k
z*Pt=VBK#2=(UvzUzZ+xumbRg>mg_>eA7}BRC+?KxU#h)`x3p5A_q1i`DoBFm!@Zd2
zGnRXAgG;m|ya?#C7RPp|pR>f!20h85p$mA)mRkw*{H0jVjboxxEhV(iIB$u10i9`<
z`4l`$w;ZBONrr_n3H?mV$8W)ImZePq?t<m~2hhv5u$I8l97}UC4CY$4dZX{6WxW>~
zFInc&xxT={-43qM()}#di!A>xgvez}Z42f9iY*y*H@L*YUXIRE%V-rq%Pg^e@ZyT)
zETzM*T8gPIquj#!0wyXfUsI5y(z0_kxGKwkv<g&P&c6;5H5RWAFo<iGyR?<KZfT<T
zb*<$&nu|KiXSAKGw@AA|8Z7hmwEt|h)KZM4$x^r+ip>^2y-03Yo}<K4i^W3kzgEi^
z7tnXpGN6XtHVd2f>FpLS#gsZM!H+?q)3UG}9(Gw4d<yJt%X9`5dMq31PDQW9rUiPp
zEWUJj?z7~a$8h^C77CqP2P_U6Xxz4ZO;!GbmbJ9K8nSeDfZVZ+o(J|_%fugWf7tSY
z2gp6kQYB#STULJvm=R0u8jw-TVh$`luzZsZy)nzH^FhWfm+a9uVUbWmc+&EKUM^FX
zi5U!O+QOr#?~K(_`9F@XJ1*<0i)&@Wk(p+eS!SAMn&q?i-jlLrd)S+)Y1^`T*ti%1
zviDL%KtQI-kiBGxGGxk75D}H7toM83pYu8Qp6@y5-sd;&J?GpXlq#Iwno6a0Gh1b}
zSexD2{|FHFj9&VE9T<J|*m7ieX9MBH=%gY^XU5lbr@Am^9AW7oWAq&~9%59PA##|J
zMG3egj7MBBB}W+zUC`;yxcWbE9*kYvVBV9lxDq%ohAo(i(~dFT69VDQSi2RiK8yv$
zm|$PV1VsRkGg?g`evE~0pwXXk<`zf*qn^$R1Tw_*pa^0}=~))cSo|RxLl}S3w_!pV
z1M{IejB#-zd<tiz^PnYy@z@stL^1-bFcig5+o*OinjxX+aSY?@J>X&)`E+^3F%}g9
zc!JSOq0*C#A$Ry4&-jEAC8roG&Z94Zp`lv5(~RSe@F|fInT)ASV)QveB$;u%7q~MF
z$7i53h0*Xg`cfGll-EsT2&aHM%NTsi28Yubk5{5IgRxlwHJOZGsY)`7aZZiKY{p~s
zJ%=2|YY)+Pj&YD)`{x<aWpMujqtqXLxs1F%Xv<?<r7c80LnMUx0tTC^ZZ9%+JPSY}
z<6<*JiWtqW0#MB8(PAtmjGu?;`xB*%1x5^}j4_c7L^)&VC}b)ag^xi^C8Pf|lvXhs
z-vL*{D0vh9)-raVg-9Kvb_`rSW8M;oTxM)=hKUA-+Y6Aq!id`rWmg$%wHQPrV+*~#
zn;6S!Wzfv{mn2&lkvL9Zn|F=zD1APvl~KPCoo$S<bZBd5{6U%X4#t<?LQN;*LNWTf
z7$4DXe4Vk4a>w0_@DfaL596N>=<a2#TmnmdjGx>9zrlEm@-#OYYbn#;&p1mF%K^rt
zv<$t)`2GL@gN$dWJj!;PQBE~^LyXN7q`brU8YiCS4Kw`S2L3K1j^aM|7)2EGyU!?~
zN8t#gmEyIdj9aJR+8E>MSK!PzL-8g=CKyxhz&&8}s=z&D?Cyl6Nyfk;n4e-CS`5H6
z<6Bx8%rKr=2yWKKu;3{)&z{+M2WlLcU+x6w$Sk7k!-*N!4&uz*z6S<fm>QaVSLP!I
zc;Uu8M=!;L%=}=OIK-SVLF6z~UI^|8(?<&PN0~oT9hW;Zmlnew%oz_D^khE%Ep&P@
z5B&>rjA^Tz1j3uS?`aSp=HpYCy<nyv#VkUYJ`z|8WiGo7OJU4EZ(%ONndLvCF@ovz
z21Fv6-~55`Mlt;;?HSE{_89tNm{nKN7t4HvqNpdC3+4eH&+KAD<P`H8PuNXh{@Vx1
z)687k&!CCSqDkmZV)lIoPm`I?)<fnDGvzTjoWlG@3X;l95<qDh^C2~!Wya9TAe}jv
zmbe*A744HVnR`ycL>BWy3h`t!KXwI|!>ppXz&U1l5hTwuD=Gb$#}wZJ$!9uluwmE*
z%zaxyE;2j3Knj^WiX|5@nPc#&nEBajP*cJTr07#Av;PQ48Pjz!8q1k4FUGG`!Soyg
zu97)TM<lA4Pf!B9n)zfAOk85_PQq_c!&FnPRxQ($qHJ}{%_6|-nMe22`G?EQ7&&CF
zGIMCb+{nD}5oDT}>nYUI%=`#Jl6fu6LsTYljTuZqtX5_c52TG*@(_LPO!F?xa|d$`
z-J+e$QaW4F#Vl<Bxz616HI#KTmkA-+!&JLKOD}W9J0N|`o7ZXocY~Q81iLqxmuXqo
z&-{BCL<g8fo8Z$e<}F$T3^KQU0+HKH-wl|VA!hRe^xa`r9fXNt=3{g;|1Q%l5hC}P
zbEwMWJ~R9~I5WaLPK6Pp%p0`(9b+C|3TMWd!&GPYkood?;B1r3&3>R$%;+Xqnr41+
z8r%$X+Zs&bEb}NOY8+S_seILu#iyBdV&&e2U1!!HJ<?oQ2RmTbm9_s0I5*a+b(o8T
ztoJC2dWiKZm6IH1O}&W5Bdjh;D<5U8d=6f?vx>fiqaHSvma@#AtPSZvc(H!{9wv^l
zKBbtFH>;dh%04U^ErxwrPg36GIBRz?8vR(WPQ$K0OG*)h0M?5Xj|gP>y8;))y23zX
zFzZ4IbcV1B=^GKDtoPesD2z3@3R=Qh3B}+dShg*+qmN`sPh(6`tPr}MqgkK*0xpJi
zlXjZ1EQSyyj@3s;Bu=mr4q-}9vO;JPk-+Nx49=Wp?Vwm;BJ0VUa5RbaiWmBlSz<Tf
z&ai@CfTa|c|2n`^Sx+nlJdM>+4au{tmu<9<OJ_Zm0J|BiJ>767ll5c<fLW|WIw_US
zTKWq_3s}8W5OtAtjh;+}EHS+zi&(=i!hA8S_W%r*usr+#FJrkIG2U`kW+g-_SQgq)
zRI<j7K%|Pb?rVr#VmZ)Kv4*wxADX>dR$l>H>sXmwXsc&cpM|9c)(j=BuCUVS;dzzi
z?+>n#_11r(2i9)79-CS6764jUO_>n6#+s#jyOnjX2IkvX^*juso%Q_&*zI5)If(&w
zvhL6xpo^74AEmg?%5SFpdpBzZ#VUJPQ}s~V%S!qYbJ@pwg3^FDSX*hWcav34|K_ou
zmG};n4zQN}1#*k^?gHQjS^MZIaGUja89W?f9r+ZEcUaGz1UJkIngF@W3Z%I9J=Q%D
z%-?4nz675}Soh(!ZQdwLM<IkURx~Yh##u@Re0#`RNTnl_tk&OPX^N$zGW%)P-&7?$
z!x~!z$yt{0W2kXpfAta?9oeI_cW`3=uLH!H?YshgE^M#opv;Z^G8K><WOu#-^M}~m
zC?$HB{rpXEwj=EAl;Ck^zf0K+4|aP7L_OL06wvcxyWB?OF?N>`O1;_N^a1F@{+3o?
zzU+{tAjjEB6m|Av3!VkepS?5_A_45pwCxRKe?tcjgV@8g2oGkz_W_iJuua{VpiuUF
z4oH}d{U_a(;p}L75k#;(cS0tT{nQwIiekS&Z}@1oZ$G#gb`GryW7%It!C)NQu@2+}
zyIT#Blk9VE!C*Z5bUEhY6npFtNCJDob0DYLg;cDO$X-eL*(7%2SMV^IZJ^c08Mf^)
zs&hzV>%t&<mi?*^98PENq2Oo+`{H`|oyoqn4)`qgR}{X@VQ-)n$vO7UEg<LF)&-Ef
zz}`zWF1hUD<!~mSy{8qp0``2$1Ycyge1N_}w(>j%Sj7G#3nC@#M=1VT%67CR!J9Jn
zS3g0foIOI1rV4gj4@4{3LdvdHu|NL@ma5r}(Ga=Be%b+~hMoNY?$@##zK4lA_RxQO
z9`?gv;4ZVr7eaRfyMW$*SJ+E#qwy+xPasCt$X@&k08Q)&3br+~cWk#oriFc%V$s*w
zA5qApmA!_(rrpN=z899-*{);oqJ#Z3U4fl!Z%S%(u?4h2zRoTPhWFj<<>`R;un#oB
z(O$OYSIko%TO0+uH`x93_3oSOlPr*a_Hr&72ifu0VdysduXA+&4Y41e3;Z4SMv7bx
zvzKgu%w6_pw4u4rj(ico5jO7)G>)<pmw_8&FMAnYjI-ZQfTaiQE0iRA$o^p=$Rs<N
zv`n!jnGl&~AEmo#mOXzXaQ2)nj<D;%8QBERkuwrU_n#BT^GA%(nIoW;i3>+e*$7w8
zfoGx3jbo++!a>eK$}}G0ut&fh<}7ancZ8$+uSSfsk*-H~PCZ4!JvfO}=<3Pgy?{n9
zj%OOC<QOMt6D)XhWWPhT4<{=EeZHJ7${*N{bM)__)sN##fpLG%$J0;~zzO>jh(OMy
z6b=V*N@;~0%sH?RTnJ}7m7#@lcF}GyjKg1oA2ys5upPJvPAGlJE|T+H54?!tyh^dc
zSkBxDcoD}5qBP(Mjy;99PjZ5pfXCZ7!C7$Q6o;)tYXWCf4MZYGO$V2fIG?4UF`2Wf
z0CvxCI_c$>!dbi?jj5cED2$rMdHD_WrE|XE1CYUqrY&YBXEBxXWpQHffMj!+NwAc|
zSw+>6=QxhVaP2(jCwhcl;MjOn?VHPyw}Q>%d`E>d1suO}_;iu;NeH+?P9>$>ia5XJ
z!)`Grrx7MfI2-8lDCHzQ0WZoqXSvW_!C6G5M3o$ub%0lKVwXc_HRq2&Sh&PFItW}1
z$BsO#<G9nWRnPg*#)X>897_=p4V<BFbY9_Xx`xiHoCjwBY~*~s9$Ygg;V`%s&f4=Z
zagFl^J;GZ#8MUz6##vB;#!gN<3kJJ578fYH&iQf)W~Q6->|RLra1Nr_V_q+3DIJdO
z<Al+!>?X%AhT<>%oIu)l4sdK4kh#S%d<t!YoZqg&ncJLaUxUaH=T8c04RbP{LgQV|
zvR=4-j}yBRfcu==RNXbgG5iH?l;e2_y2m&pN1$b#6G5rP3C``$z&+q(`oO1$oT;Ay
znBpwkMBiVU=IjrE!!w+S4vcV?^YU((u;*@i1dR?{cUt>6a!154=*(rApv{H5m%cOL
z%6<P=0Nl75Dv>$Jt=S3Phqxw6IvwV&>x03g+!t1XbLXyo0DuQ~WB|%MxzA8Zofr2Q
zw!5}@$GFe`1E4oIQwHM8-S!DOk8>@50O7|yNt-2q?oaDM0=Q|Lp){DggTh@Q+;IBl
zP$+jY9b6dKuMb=}*RKfPM{pM}#&kt;>n_9XXzpjU7Kq^<`v~w@?&f$j#&O%117|zI
zjrIrdBzF}pRpYs%^lK+@13e&fn#-nQ<3#TE(`ZcM?xR<1GWSV(sh;7+MWHW+`;-d|
zrgHi8m9I2z>J<9Ua<ALrr%30{(vj6n?$2}KeHQm?iXLTie}4pC<Zwr6vvJPGHLCD)
zo#%#ACint(@)l(BxYd)u=W~N7VN$^5=0MFw?no%q6mqX`09VAVphtHxx4RUil<QcI
z#xm}4Ea~T!bC(u_RB&Ja6MdE3AX+C>aYyJIbk*F22SIAM{m0Q)%eC#LWpEwWsRE>)
z>v$2Zm$@f)VQQ{&7tt=Zk;|i_8BN@i4<ORa&1wg}g=_DK#%tUgv{P*5_PT+zbB);`
z9b6$zP$zeL7yRww-m}8|b?#C6CqdoZU<u$o-2L~^*T?m;(d~bOyM)%%H@S1}<9F)k
z{yPob1Kh=(FnEibPRZLr?(zEo-sZmlBBpDItD&N_J6th^9)`Jd=v8%(`#L>D?sNMu
zKxBmbgFU<$<$m}cRF84*PeaQ%H+L)gCb;Wqlk<?PU24NXC%KYGAv(qVYd1uvxiKF@
z_Y60$6@9Z@|1J1M?0G(PWY&>4Mpuaw?`sMfI`f9wL0ou&^uxOH&e4<DjdyDpxP!b8
z*^oTU+rJupM|eT6z`{}9-ftk{&N~+l5f9$b6vbbT@$BBmD7<+;KLHsZUgM8I`0|!N
z35SpKN}hzne!T2$5b@`EU51B&yzg_s1@YdahjlQ|z5>Gz;hm<XNGPwJ4O|#+)gZWV
z-YrT&Me_V9RUXCb`x#s`FKjVfi{V*+r1xJe&yI@1<9NOF*_#u*Vp^r0<b|FFiRZmb
zkF8U@LdqH?@RlrvNFpz36DBB$mq?#bNak^};qMvVyPt!k@E+fZzEs}4M!?f}`imH7
zI&UNGHZpk5Iq)}=*G@T{ES|%5xNXbkxy?cAdENvatiHet*$;!cJZ%UNdAvL#`MjI7
zB`)CcePRA0Z!^{97xC6pMN={FJx6dQyt(NxU&?zxfxI%_;jb}I<vbHDb1HZjry*Iz
zdyZae)x1KglfA@y?r(54Hl9KP-L<^=kE6AYx1SdO^*m=iytvG}PWk%=9-rddS9nj*
zp7bg&auV)0@!qFnOwGLRO)%fWtG1x=8n1OPl(q6iJ25kDyemiGOgqo}d-QekY>|-c
z;ssMl>vi6KTEKPlY)`L(?jD{ORjA+KSwDuSH+cmiXzb@5F9UvncaK)Ow|G_xWDN4E
z{6TK>iYYFBhu2aGz%Xy_CXl<lm=5T^$J<VY9QS!2JP$1+JReFSjq+ZnWa2pQYdS_W
z!8>0KEf09BY^T6J<QZZxdy~8pie63e1hf&F<|!!TF~duztlli|WE&*y`3AZy9r(Ty
zOqUa1Ow}RIeBKNIF8qE<?z!^&_5t9=*VF#(Apf^yh#ca-L4mC!{1;ddIm#DPy|_F7
z<IS}H^WZzuR?(BM+yfbJequa0AO1U3n(E81q1u|`{57=O@Z$%6fWi3l_b<X=0{BHk
zuoT3fc^-}i^B?I4E`)!32>_w|77E6O@z2%c7YXNYqQzDOzt9_iDE{lT5R2wNKSkf4
zkKsQ~;rUqpn-tWE;~Uoke}bQI0hUhkFVI>%p6_%Oh*Nym5J)EQ*FTHC)BNQWBuwIO
zqhj)8{-;wgafZL!49OJ!53~SG<zJwB^ECcNiuIr6Z?cE741UrMOi3oc1Vu--d0G75
zsMsT$|Dh*DbNC7ofEW0Wo=0OYUrk~1Jbw8yj5nXZgQ8{y{IxY87x|z50HuZe<V_e;
z5kHQ$y~X_1^inM4-<S`PGXA4#cv#L~LD}>Qe)krLRPqOSP+iTxPZ2!ZC4RaEoi+S@
zbo<xwm(gp#p8tdvb8(rUL)*Cq{_0$~c7@-x1>`FKBvlAB@;{|5bu*t&>x>qD#AWEd
z#@ElHua*BiJs8{g&7%Oc^Z!wyuY>;*o$l`9S3d^T*ZChgL!{fr7p4Qz!xzqjrCxq{
zE1c@%S8s-k{roo@;r;;Mr~tXeKh_T5Ab%OH-f#02bmI*1U!p?uJN%J5&^F9>prztn
zzT^Xt`}|5Nl#TEcXmvKqe=!asWBfaBp>dpFnGY=w__mTMun+k&W{^p~`w&{E`HSd~
z!3=*ZU5K;%_dZ9Ty&#avEF1(u2~guG;N1o1B>09B7A^u+DI{G5|9XOR6I_1^fP(^;
zB)EM@Fk1p;hXu**n1myOae9Kg3wl+M^bp*&#i7$v@G-spy##}|z#S9Jr|gZl;FlMm
z=D1+H12{iH{#O{Nzaae=Z~=nKPe1|%CJL$s34Trm7cAICL5dK;Z}fqIP{BGsz{3TH
z55tQHLDOn*k%D|$m_!Ly(sMalFkDLO&sf1x3LD1>;=hF#Cj=8zMj9{pkRHgV1ky#o
zCkPgL!0*$7`4p;56ztyw$s~bL0C=+C9Wj)q2p0SaEvbT|bpNCY=DY%tvx3LzPE8jy
zErN#`0`qrh%oKc)it8d<z+d#=_Xh=^)8{eI3HG+Y?s>rudhK5j<Z#iLD|kR@zyg6$
z1T_~0-Sxm13e;?HMS@=PzF2TIAEZPOGY|fj3T{vyyiA}y0g-aS&u;@>A#nczq*B1V
zjlL?ub9oq2wO}KvENt^G2}E>irAE*e1esdFca%=36G&R&MZMq+1IT5;gKa=G2tJ7g
zxgy9dhMFb;m-da#f?V3zw+PaHgyc2BD>Qkn0;g!0Zxd{w`iOP`DiUx52wtaGRj1$;
zD(LMJ^ij0Sc3m)^(wE(WCNb>x2=-8^S+8IZ1#|lZzEnbdL+~e^{JAOkau24YU$8G1
zzyU!Vov*$n`29V=2L--#JKPbh*#s|!1s>tx?h39`ZvCEMfWqVV1*H`79}ygR6Bb4V
zTi%4uF`FRrcPJef+@uxfgdo`-_y>YYD*1XSc%6<?PYV8~0+cC1bT+h23w}32az@bg
z7r0r$|MozQy>J;-4>$;4_#Ji~h0!D6oP_4D(B~=~qScO@FzPk<dr<fxmBAbm`guV0
zVWF)`4thi=r}g?#VO{|^ccHQl#6wuH4kkQ>v2=BM2_@5L^cGIcz!@K*hO)%I!n#r5
zjtgBsgC##<YBlWo3qz<dK0tWuD_9B?me6V^Ncc0wzJrAagU}Zud}29Bm~fdb5Dte6
zk1IhUghRA~ixkGvJ}gT37uCN+3qP(!V~p^XDA<h^9-$(JIN^(>P<ldmv<-bHg)6=S
zIVCLo7+xd@2M55N7Czem*Aj(ER#-|BCOig`EHqN6@{F)e3CR@U3U?bum@53dAFXM^
z89GjMR_IEXSEleRJwvmE<1a%bTj=vGoXHVxq%83{;ZnLF&I@NAN8<(I;$3hiSNJMr
zsq%!UDA<=TjG*^OfiPqml7&L$?{K?FxWRzNV&M)-+?5DlbpJ2^C;YJ=h%#ZyDv)yF
zwO=vN3SmA~zg7w#&{L#J*hK|%)xwVdHV;DKLkz7}ShpLEb;8wjpr&5vO()7O3oH3B
z*dY9zzR_|;IFJs5SA{{8{cIFIN?#3V5<dL}M4E;6p>uHmT@#+C?|8NfSNB1*P3S^b
zV7pLV2ChSxLle{~{EP=+moUcw$?L+FA7Qs!C>%v&kMJLQMfM8qC^UOhI8un;u3s2S
zEBXQ9Q?wnsCA?0F_d(&#=Rs}@mr$yENT~b?INKfJ+wnjQ3%e*nbyt|N7P{{V|F{a#
z5#f@RkQo&wU4p}7!VL<T7#F^g2Bi~1A4-5f5dNhGc_{3slg*RD-OHeCN?3CSBGba`
zX7tSnEnk7yi|$Ybm4oOet&kl>J*%M8$tD`2f+}YbgJOm*qOKqiS5X69J8q(-RIqbU
zl!J+ycSvOaHgq2r`KCeSs3?fG%kCm;DJ*%2inGw@DQZmsz)Mu{CCD*RHQnjnBEJ-j
z%t!R*UJzeVvl4*gqEQzp^Ap(wo1rF9^obAHAkmij7;ms>l@8`ZME;aO2o>ECf`o|{
zEQ8<SqEqx1j}UE7go#Mez?%R>iGJr{x}rrtOhPhNlu4VUIFTFGW1SG0E&+E^^e9f7
z&5IX(O?it`q8$`FOAx(ny9aMhi!ROrktlNf5+q6V#c}|XMQbQ!kRs}@2bYS-IV`1#
zbo6pND>@hqE?pE!g(MlGHFWwhQzU!}=CeeP%P{P0(dq=K&Jq1aRkP<rS+p6wAUaIh
zh+NTf3hm^Hx_asSQNHNaOCSZJ)Ak@2MbA;?W}&FB877KE{~iM=7OnjWz!FglJq$`k
z?+T#1LX=CZ?@E!d7l10!Qrg&8i`-~CbxD*(@2DD4*<LtPE9$2eXPxND1Zb%jeg7}u
zmqj0|sQ$V^luOmkS4C}3n4v~d3J0A{qOw%zZWc|_Yo$fx^&6C46SV|GvQ=cJ0`)eL
z6K%)ZMK%8b&>=cT5A;qEGaVw=MN8X2x<#?{DV-isHJwoG741F)T%X9ERt+~qPYu!k
z|GO#L9Rf@JqD1=dCIh1O|8g6m`EwvMDB5=bz#&oc+Yq@U`jibz!y<klMsZiPnD%k^
zMD0!>_eHGF02mQ%qeIA}q658<925C{0{FP7#0`K6Q7H%JCq>@0b(s<|C<ttu7VW1f
z`;6$-9>~m!0>eP;#qaHaK?kt{F3xiln@)f@iJR<!cNV`!O9B`1fsZhyZsIt~9~=}P
zqD=oGaW~zthsBA`kUSz@x&h7{6=zYl*IgXC2Rc2(fgFs}Q_QA#x|dDtR|Vb2#10gO
z@e#jJ3K?JV<hw9&Ts)ltpr2S*jYfZQs1YUt#4kPxE>LVCgF)iw6MzdAKkS3j5V7x9
zP#P*`hG8zk#on>-B0^j(2Nx-p%E3j66KQQ3Ee>ylg&48zGF9lsiUU&68YkXP&%hJn
z_X;qklj1^($H$9bpjXyu@z)d=PZW32Ha|)HCuIea#b;>Gb4J`vOU)GVPTI7miXWxN
zPMUZnh0xB58{)yGi@#_9mmv<X1t3d&ld>4u;vF`sh0hVcPb>6u;u|vH&x@_}HoYL;
zN=F-W#gE9)mnT*o1<4nCzYNz3#4Z#MyeNK-_B=)6-zZ~HEPgHw9+rr|dI6+VTtlhF
zGVwUQ_RGcX`G8l5LxTaY6p!rysS+>xfmU$U;@?+bOqawr%VEA&y!<IRTqmB8ps!wB
zNx6y3;&<pgPlNb3N?%?Pf1`x%tK#=eP}3;h;0oPM;?gj1&Em)oIMX7&qX3{yte=2~
z?P4CSMmxlR`~cP0#kKp;*Dd~bE!}@T;+JSH2gPz<7`!dMO*O|u;+k`?bVr=m4KgfF
ze;4Gg_(fV5-4oAAf{FX$PpC3)M0}q9OTno4ODX~y6Myt4xN&jQ^AMR3ucDDX5GT{V
z{-N0NGvJfrbowO6lsE%VG~2vs@uQTYoDmDZ0GSo<dKu2xOHS<t!a=fdFGL+B;&Kel
zNzy{4sm_wQ&ttqUl32>hxk}y_VlZx!h~HuGphWo(v>cLLri=Wr#DkJ-M<n_5_0yx0
z7pctMT{1}H^pM1Fg%+Eq<ZF7sc}c#Y9PTkmPaImkB?f<RK9Y|2(dR3X?E?O|B=SY{
z`AHf-z~uW&)+a+v0K7nBpyXA0LkCH|r=K}k5=M{05XnoF{|l9{_JRwOWK&sVxMUH%
z*&`%x(!M^@CUK%4JxY>FE9Gd(1m$^RB&(S~#7h1M13pf&^gD>2klY=I$VrLdMNCP&
zq?F3RPD#{ej444<LWLZsC6UK5-b6`wD`qB1!nKFn$&x{OZ=R9-LYF{_B>7F)OO+%G
zAeknyZKbE)S;@69IF&Bxr^G{s#HR|KnG$sd8nYxjsq6sfJ1)Sr9Lb&k0dP)IyBCeQ
zk{w()nkVsh0xn;|pv6{!B#depE=oq}OjMyHj7p%2B+-=NFP0bz(N`jwvjsktO0L@|
zV_zm&KLShTl1{3dtB|atl7vdh-*mB6Ne;XOe6^&e19mS-&h7)CMsk`~v$c|cXs1{w
zX`uVBUJ@=r<7LT~Sm<t$uqZ)uMZ)?LUR;%g&IP<t5_kiRO%k6(G&W13RW=}6B;R*I
z%{9p;y1ZH?;S;diCNWR}bh~7Ns<AsH54iB6Q(|g`nl6dmb(pv=iT(v#x8!RI$n{8`
z%><xVGE0|7pG2TU-wjDjEV!GJ9Xp_<Uy@2EECwW>lwh2<BzOC1|2HV9p~9Ejl4AOt
z(vYP2Z#Z*D@(Jaqh9!x)@ae9knHJjjB=0={cVF^7Wv53Z>&hT9D*5Xg?2buheuszS
z68mO|Oh^JLR`EbmqJqdn$@8?No|N=HiD6Gkyv{;oTCx!jM%%m@$=t1QaaQv6b5Lq8
zT^Iv|gY-)u$T&*fDPQU&O=O|ZS^5Iisk=xYQtZH08bg&(ZqhafxOPxl@*KEB(%^V-
zho$4RD?1`hGl3kH%En>dU0Un~N4=zndSKz0R5FW3o3}KUj==ax&rq$2uk`j(AdX9a
zQ$dZNG{X}z{!%U#umniQN`McPx?TepBz2_XhhS+uE%HL7vuwB)Dt(fRzA$OkIp_?R
zhEQcsgfxnlbCJ@<)fj!0G^7`O(b9MAAQ@wmnv)?DD?LFG#5k$**B~dP>IJw2PD-~u
z4Nv2xS16o$N*YR0uLP;Yguc_#v;~-iL}|lOh$Km$$px1zE!zh88R>Q^=Sq>5Jq6XN
z(#y14NRxi>6S%X|dF$Xsx^yR1#%4%uuct$IrZk<L%96f8QQT}PI}|cG(mV6fcTT$D
zQ<yj}U9%MAg7jm03+GDzx(hB(T1HR3i_)@a01BnT`<RO&X}uORQ!F*n6QV@=?hjC1
zD*ZJPl4a6A?Ex>B7Uu(AA^p`xsk2Jy(q;gwqzyKZYU#ajh+dMGHDXF@q@H$Yti^vB
zhqgNDjpu=HkS<k$T#>#*k;kjj06rXTl=g9<tVw!@qVvtthZK5fk=~;{%Qb0J1+=tE
zH!9KBCKXVkzg_Ceruxqg=^Xsc>y*ZP44E#eh$_^tOAkGX#%}35be6J5I`$c6y;oXG
z7kQub4ccJekglQH-J8-~YvD}4^eXBp=M6}IUkJOmr0JBz9F$%+1Abe&^)Wa)B)zr`
zcJD}2DEBlhO_9*~qr1}Cv*^4ho$i6?ed$FCCXGmEPoZ&C+CcwGU`*;r<t*dURu+7k
zkQRu+J&?vppyr|Ur9u3@lhRoVIZjF6_k^R<QcgYwIwMW|5F)eEL2tNbFB|w1svTrc
z-GZc}Ec+!of9oWBhL&f}vfFqa&U2B?q07WoHbV6zZZaoI+Z>en?|{KWGXK{w-ovsF
z|9}@qWZa+N;Za#i1>o+o-eVY=hwRsdfP2a|P(hTJ>{TjfJ|??=9(~?231#ejWaqR{
z<|}*dakyqXF59*doqn<wceMJ;{OOGsAbXzF1j;rw!cvfI(N7Q!mX*$j`4HLF|AB<c
zn(sg)Otz&RO2cJYt6?cZCa405lzm38*eKbxx8Y&5%<~(-<77?rFgPL0r+mptSs2{_
z@iy6bGzNM~*0&05f~@Z$oH;F<ItvqtvKA@0B-zG7h$PEe^U!!kww+>8DY7fCL20Ti
z-wwDm*&5oAoR$6H1>NbgO%w~xkn!o+n<*QlZCsXY1?_jUWgDIZAV;?D6KFXnvkg<K
z@4T#U0+uewKA`<$uI$ZcAetxZ5rfN@nJKDSAggr6KrhOE3jisUG514vkt{0|+KOfC
z>BcFMi4I^&N@X3}(N`u5rjSy(tp0OYsF1Cuilj=}I;z^MlJU-gtCkJe?m_n@*-o10
z8ri^kXseY86JVlFmPpaXdYK{&gSjlLr2jb9AX~ErmafPKcfmxHthOBRW|=dU;<m^}
zDMf!xmhl6$w92mBfTcEB0X<UMW!DQK(jj|_A}yUVXDV0kl6{*;2Wqa%A|qg;TbBGe
zfITt~dd2q29Ae>9pRAUS<=nte0diC3H3vTR%e>!%(gE3>x!`Wew&X$EpltF4Ox%{q
zBhfe{i#ZAS9T}Srhz!d<qZQO$+1N^We@_-fONslk(gHgFFd_?}kjbdbLOI+qSua(U
zjmsWTozjFX?iwcXfov=Yh=;O<b?BRvRZs$9N;W}hqG{QOHNeftUfzj8%*rm%aRht$
zk3#f0$hT6`$x;3UQtk7c<fiNBbC%nG3S}<xmlsg{(^bBP4Hw<yp|1jQP=1O7yNBf8
z{|lMJ@<-=kf{w_y(M#s2yy^{TbC)ltI!+JyJ4WC<<%~`=ddWA^)90A{CLfaC@=@9b
z`pEav1>q}i3`XB^c{)X({N$h08D@X^1xjn#0_45Bpe9gWKueh*xrH8g!SXGSVK5=`
z6Ae%kD*uFP@xtW$sSYe$9<u_#2>A+HP({iE2Ej$iR~&?vX!%`#a53^H{sJIY{=Y9_
zK2E-N7+OxqXQ{aBl)Ql=X$kTGipHF_$-Ai>Em6*>MQf70fXZN!<>gf4az-v$2&F0V
z&%XygRbC+hNs~W!0>HEKwNz4+F5iknT=O#I;f`=EQ~o3c8?xkqyWvH)eBcMD&XKSG
z2U^a_z337+FSpqPenH+@01LTtTX`gCp4^M#w)ygU`ie$@Tv!NlQU0MC_(Hk!OE6I+
zZ~YERi{(pbN=oFl7h$PXzJVTIW%9)Wh?L6@WB^bhueZRNO8GmhVX#X6y#SL?Ezhrq
zg-i0G3CvoJJkK3I)ylhVuR~j%TuuL<yk35W?)%H~$KqkBLH<3JZe5YD+X0cQ^7#wk
zccXkiT_sKO`Gb&bmd{%Vkyd%1290g<i&PKNE_bEEmkzlq7Or*5t5=}0OTKCXu3eYs
zj=`C3IingL_Q)R|pmR^X@^;!y_Q}7b#nugZ@@KGgQ~tmMp7zVPv_Q>({I_OUx+PET
z02!2f9|i8Vyrv7<hUA<yn7AWXaR3;W-`EO&@5-BJVd9?rReCkwm+L4^J0gFJ>Uu}z
zpVJy-Ox|au?@x@&Cn;nyA%BZ@4G-j8A9OyHFZ%_Jlk!eV8BEFJ8{pxz{Ph%YGjirQ
z?9R%U_`#sP;?x}w2gPr+9CTEK(`M31v3eccc2;~xkw+KBVv5bUD&D7kg`48>?eOBD
z;?pKNe{@J;M@7Gf6_Q_}^oYVjzl?{%p7NcZ3h&?Gg_pvb4E!-gDJ{Fb72ONqjE`cP
zLJz)*gxi>s<BDe58T%=k)$rb5k^K)G4N!#9MH;9mZ-j*)MH`JXSh1hp!Xb*iXVGU1
zRRsJGhzP|T3RXlag5QCOD8*Mih(;^gsR}Me@i_%6ViohFpfpY~<_z~wD9+MR^^=N!
z;-D>FVNY-GQwk3{m5`wLlQOxd6>kwqRLlmTFG=y{Qy6`+V%{z&JEQne2GuDx#S=^6
zMyjIfMF7(j?la)dDq1NMm9A*{7tUlTzB!4ZWh&|)MPrs?MH#eZE7*PDaukcYfIFuc
zq$J9D#UYAyTu^X@Fp;Zpx(bmz#a>^Ke8tp0h!iNg=(4(~SRV;op~6<T721jvJ0C%7
zu_AN^E|w_vP-v=DQFb3(nIeY{LzOGs|ANvA#as~pm5L(TPgN<l)2W1Nh3yLZE-9W_
z4u5MDM;^f->J(i1Ul#R>w;u($tPrTs*Pu8><xN)<TUWx~RmEkS8KRAfg|rWAQgoky
zwq}KbLNzT44NdSh#SGnlt%^7be6}f;5wKm+^aQ-<P{b|7kJhPpg>uf_ibER#?@??>
zhGef|-%DuhQ@l@Kj=rIIow8du6*_w8_A5Frqj5k{x6uaQZYjd37-&#&n2BNER-|o!
z%#h-H3Aj6oy>zsASmFOFwB1!icSFrR#RuI0+*h1f05v0uE)g0>6<=)xZcH&v!Mbt9
zE(&=}C?3p#GY=HDP3U{5Xr$oAq$2kND4SAz>Otpkrxm7ZSejA17X<fb6<@kSsl9T|
z42Xl$iFQDa%4Mf97f#CKb0Olalu@z1i*j})l)5TAGtuX!yuB8>4=P*fFw`OCa}MAR
zD_6e?$s<bt4`AV_GG+{}xhp4YAmX8X;Vhj$@>IsPLB>m2_976+lp_@2@>a$tV1z!(
zglG_7<@b3Y$CW2(N8qRYBp2iLSH7Qs5e6vl{SNbi%5{%|3sPRC>}Rl2OWBhUWg5LJ
zLY2$6z<ii8ZxC}4uDnb!#t7v(3Z2^`m48!QFG|_e1kq@v4<$8Xloy9!Fjn~o9o>mj
zo}j4p3FW8s`NNaSZ$1YgUU{Ehs;89O#qd5sIZd1P(@J?LlqM=K)6+IdxhV@=vT|)K
z$Qk9%vrwI){5}_kQk9=k3@gp1jG@%%S>+<S;nS5X=7GylYN%i}Q|XWglBEp3iN0**
z=^h|*lto>zbWS-ghZpCSQy;+m1?9pIA(^XuIuP(Y<zp22&sS!+K(at-cL3gBR65hO
zTCCjZ4QEP}GdeVuDs9sgxG7Wq&kRJl^3@=8RwyeP&{?V6>Vm#1rQJ33RV!;E(057M
zQw&Qr%3Qi*YL#)ckE>IDg3Z#rdS&iqkju&)&X8<S*0uwFMae4w;HvV#1k5)oBT@lq
zQi|`v?Pg`I?LEwMi_$uS&TGnFn83Fx*V1;qP1*J_`r4H>w0!PRK0`+qI+bTB-P5J?
zd<IIdE1B<ubSpa;knB;$jlgcN@)26m_bK0a6FP4wf7%Q$ZYp1#g-E~h34e$TC<iD=
zaZ9-{nc|;=%E<q2Jmvm_kQq{bN>wd)lwVR{Y*_jGGthQd`RYlKd&)=YC39c-D!u4O
zlq(*CwozsEci_g9`#*ufapi8>oJ}Yvso>^;vTYjvK2&}&0%eoRCq9Pcl=2bU|4l2I
z4fOt-QLb18rL)R@DS-AW|EHkTLG=`+8XQ#<x8akMsy7{t&Z@s0z`3aA(?-=*l}}q@
zH`R*$n1q9><@DM=q+-%{xelv5YtVQ^^(d`Rj;dr!0e4ruv>WC<RA)ON;;GvHF~vW<
zR3Gew-D4^?C6v8YqpyJYsH$cm>Z>Yy1$}<1xy=~8zsmku_#L1Mqnj&G^*a-~gH*le
zK!R1%8_^h|(gi?ws7mLAA%&?*=|vx|`VEyf^CDD=Q{W<18T3D4qEv5ggorI#b%d(B
zVpN?Bn21#c(&{@-HIjr8o>0Zm`t_tLREOD%SN)_$<0;iEYv5CYDvN>?r&WI!KqOJc
zC<B+IIy?%IWL3`!XgQ-=84TA_R5p70q^cUa(U+!*5W((QmFfWOrQ1}W?gX2m@}tdN
zrfLg4<+D_^`_P%KV!aGtj%q1|tIw&NTp)Q~6-6d4s6L^6Sgz`swGhcuH5>z%ulj@r
zTA*^+3@sN`Yp;P6s=S_rvLaRRe0W%_+DP%95>*C8=Sx*K;VVFtsY)npT%p=C0uz-g
zXS#u^R3((iu2wC+3dALqjP^V=s;C?otW|w*13y!ps^kK=dR4$0aF<mN>4#}h{Y~41
zD=J+g9KEXgi!QxJ)ik}6n^e2zqOVz%Mf>v>)dm|KNWG?d;{aM)RZD_lsZAAb2C!Wf
z@d}3Bp&F!!TBj=cGq~2JN_iaGuB+6oz;&xG&}OzrRYtkrUKNY>EPW~;%F*3W{Xhq_
zZmO2IKv};^K=o7uDkc>~-BPWi6x5*Vr+Rw&+*Wx|D11oO@G3@lN5$sA#IR~F9bmt!
z3fh9XxTjK3EbG21r35~Ws9xU=z^Lj83IvX+x=+IHxGMG$I5VO0+=RXdDq#Z}AF2{)
z@jj_)rNzUPYUW#bF|Eqq51lhA-(re?&Z-`7hg0_InAPyqK|PPof;g+Y=uobU`k6o&
zbXC8(8^lfBLvMhCYNyx19a4Wu+sMP}ffV?AM17J@VH{QeSJB|Eo}$`a5A|FMnt7^=
zX`Ah(o^u)Gn0mk;TD;X354!(+)LL5B`Kk{shNs8X8~=b^KlLs@$oQ)lrJ^rDo$QOo
zK(%K*M1s__FTi}TdPN0Di26@j1&6Ble2cy?^(~5`hO5hl(HEf}pyXPl`i0XVQR?6R
zg0g6J;+vR@81+9-f!JczM+V?&ocaP4JDyONZv_6NT0}|mc=cu#$SL)|R0xuwjyncR
zN$NT4pe9-U_!|J6Q3t<{#uW8mq%>76qm4nDI(rr(XVtg#a64W7>;b?t)W=dmGSy1D
z$g<S(DEO3ZQ+LwCFGv0P&j6lN&rsswy!sZ^^juJ{I1M$q>byAs=BfP;VTAeW6RXfz
zpnjij!;9*Vs93mAoq7hiBK6ud%v!P9I}x*9qE1~26Q%0=REbfhmN|ecR}XywT!lKR
z34ltqZDth^Rq8L_g-o^DLRZTrwUsu}HR>DAP*ba3@F)7})E{_ZF!ky)QE>mVIzIu8
z4eBy_23}GBPNy}ms&hA?uTfq6FW^n;74&jyR{K_9W?Iy9TtTj>BYI%BRXzVYMB3Ez
zZRBaY`ZZr@>rfB60@0~1qBL)pT6F<3*VS%zXzW(UP%ySfy;BPlz3QGo^xafn%!XvY
z`oj+}T?6VxY0z>@{VjdJY*4-LXOP?KF#6Exka`2%O?TAhJs`vCaXrXg^)H(#{&`Qm
zpcYE+tHrOww-NR3TmVPaKi`3CW9m8z^p2}FREIL5e(!G>e4y4Wg~&s-*C@!Ox{DU!
zQ);Ofv`nKm42?7D`GN3hR{bR(aC^-j`e=cJ#`9^+ucPL*FX6qDX6$J?f9tGCi~-O^
z^FI9~u9^s{es$BRnxN*OrsOXm4r%s21^i)6HdS>V(J-h6_ozld@iBMJ3r*lWG+)so
z+Ec@!bya}o<sjG%)Qmq45~T6l1Ib{`;vv`#(KIGOXQ<{gL_BQs!Zgop1wLF;PfxuF
zjh<>vA~mU$(T&oy_&_vT6GAD*7|lc<JdD-cr`27YrjU*toX}{_U=B}e8Yj^guj!yF
zsZ*NMjc_JGlV%TcTJ!$T03>QADSDfvnO+7DlQqwM24Xv-dHMj%r)Zx35p1gF8>+`j
z(>y{ei?f;s`@p4Zr0>IghUPum7-VV`4j@^YU(z6wt?6OV{iDe}0u$#nnY70{uVK;M
zctNv-$}w{_+ty%Yd76Jc(U`AU_yp_~XkJc(WRXqN&x5vNjWq<VC7NGoX<e$((`mpm
zP0EkJmuu>%N~1!v-2gR}nkgy`sM4@M1b0cJ<v^rH(@CMBTFrSnM^LBvt{kLZvm*;8
zE^7?57jDoTn8aAFXf{wO{8i1zQ6P;P+Yle-n>2m&8g15;(N>^EQ+*1*!8OefIT&`U
z=G))V*P(IWhrUkDP7}y=O>8mn-J0a@;Y^RFcLXB6n$yD|eVXeZ!rvR3q8w<ssVSw{
zb-$*SLJtF)CA50JrTO^`TpQH1*=U5fH47skGo+cKGMGD>#!e_5)-d0LYj-u9sVMZG
zMod@mea-5X;6^kJk<d1(aVP~D(~P8njBEU6VSYmM?>e~lK%?3P6Av|S^Z_ub`K25>
zr!+nk2btC!*aFov8b2w$|7JA~6uWcKM$t(cN3B~dM4hy46bN+Hs^ZY+rp+#c?t|JI
z3bP&3rjJANu=Y6$mLJhBe+R@v`^zN&Jhds$Lc~jZ>VFXN(cb+Oli;g0Rzu{twp<3z
zPrKneSn$_A*G&0`0Il*xOlhE2z8)rmv_I126|8lkdXf<Bca$p#)kZ7;K1>^33z2Z`
zPn6Y*&_3$}E>fHE0}MuK6;qIm*6!U5c#QVNTOhGoTO9@%r(GI_z7yKx^!7ffeL@9g
z@!FfeQvCCjwj>TR3EDF>7pJu)zd&1}b{WN1leF^_;99aa;w3n9M*9(6>nU1}1&yiN
zsrxXIrd_fN+*xhd_u$gCy+hEQp^Z2JWtrOkS~!}ey><;E+1ev^n4lbO5C!SaX{)Y5
zr|rBpdJ&Z7X?IfOF<)CttI7iHy_aDAqV`+*jA)_u1{1oAw4bJcE7l5gp|nKX5DQ03
zwM*JS%Cy2_h?HwXXw6lj-9>AVO0Az2q)Hpu2~w>+C;<GDHa81)YqX&h*RHi`?canq
zb=qVzyr|bcOCih4+PMW#+Mtc2mHid1Dhj}>+I?Z*nzd)CEV4zbqmr*{T3$SGty&K4
zY1_0F^tfx+R&9nzhxW-vnCR55r-KV!+T<w=ut(cXg^<14Fgo<yr?uTb2AMlr@fzqJ
z)>c0Pa#xFm2`+MN$UBf3)fPMpkumL0^qJ*xt)>H(CbZ88pyq*g=?ZXD+7b$YOlzH=
z1)0%qeFp#soyq~jcGS&V2`x^#ITV+3*8Tnf#6=hIEtI+H{;`pZUb>L=P;*SzLx~n|
z-D?|Q-bc452Y&nN;tOEuxNhe!==0NkNI@un-B}7f1n6F%nGMv<eHxNMx(gI+57tf7
zwl_q#llH=)x-}GE4%1zusf^Gqr0XJ5=TU~=AW9eFX@j<C-OIG-iP7!r2N$bzr02~^
z-JSpd<8_bcqVJS$s|0-sx{bHt=xN<DiYX=PBB`J;NmoS`kjc87OAtAu^GgRHMQ5UH
zda7<u4EoY^JD&r0R`<^qh@|U|Qm8RQS8<yD|6iu=au1x!(xowA_ngjM3DI2L&sV_Z
z>8d^f$=7}K2pS7?AMOWtQKz~ErG+}bKQIYJy3Z|`;9{NKTToh}lRboFsm|j894*t8
zd%@9i-Epd<sL=gJ>)uM;FfB2wbS2yA{9m<B?gE)hx^1*es?nuW^<AxQqaC<9-I)gT
z)$8`}1^$XI`~*mw&XHE%?YiOl7=4E>kO~btb&KpVv@Tsv0pQnlD{g@6(N*n0U$3s2
za&&#VE#%=1-5x5uzN!25O%PkZZauA(2XxQSa^se+_aG3rbr&c}Fr;&Khr@StPtxLL
zSl2>xc~`e26Xx&f9#Hz@zOJ(hN=J0RI>EJ3-C9p@V>%(N#m9A?zhGt_=qBind#JP0
zOJY*@*x%@z(rKu8Z`!7t;b4R_x(bSf&+3*FvDa^-6`X^<Js*9JdbI_3Cw=%|06Ob!
z|Dw@Fe|!*Lxa#8upwvyDzaQQo)Q{6uc1V9L6q1Maa~FYl=>JERtzP=Av_LqfmoLNs
zz4fkiNXJKS>vcw}uYNsZ(esY$-=q5L0R5}iF_=L8ca)n5(k~G~cd-7gH_#WNAE0Dc
zsQxP@NSNM0fzNQgydA%Ggns!(Xo=DfQ`k0IA9)udF?#O^D2vs5ehPS;K70erpU}@v
z!R?d!H*B=*j@Q2s4>hOs`U6mtpkKHah|_w<N1!HAf5Z+XS+Dm-;~9Od2e=gdu8*K5
zRbNSGjMDUvn82m$hdQ7%Lx1fGyvWpV%!jfpedT$GWb1F90xn0->j!sEZzg*e^c|1V
zGe1}F(u!%z({E9M%h%7PGp7amPWt5EMg7yXY%kPbl*2@szHuYwqFmoY$0aNDj+7Fu
z)GshYca{DzdiY(^e@^j;8vUQW=&RMIG@<XZep&{2gFcE%iLU53+(F+}z5h>i{<cvc
zSOH+O{yK$0Tl9+q(Rodu$%2}8ecc-Lb?CJpVlbWhe;>mnbm{9Tl6PI-QUE}=KJ66%
zdi3LeLb6XE6$;54`VT38epA1$1%3VcCp+QAfIfy+^tbeR`5=S(qYr8Qd0W3~FDwn|
zAEz|cUHvUe#op7WUWS_c`Va%ujOcmv9hOo3+FtaH>04I;KcWAPQeO}B^Qolaq5j47
z5Si46tI;^6PyQAYG^-yhg`~aVjsJGGh8~InIU0Nv@ZQNFqGz_v*>K7i=3NcE=OOB5
zXb%NBXehi7(L)Azif0@)#3ew~-EfL##>3D{m6x7|d@VfmGOW#q$T7n%%3ygL6t@8P
zF{DvC&DXH@8btgJ>yptJVAw}tlt9Bz^xFp+QfO}%Y%_Q)L2Iai=L<xbfk(@_a6><Z
zQ6mleC^Qsh5H`YYw4uiXlOJPn`4Z-14IV8}6K622L*Gfm=1pjfHxxbvgQpCCanYDy
zD4{~t(}wS8g_~%&Oi%Y@!yvus&KQ0mWhn+*Jgq8I4fm;(Da~+_<}1T6hYIU64XZzZ
znk+;2I!ti3p@l?p4Bx&1{5gX^**$OA5CIP_7?xy!<Qm?iQldOV#BKED8<aC}roeE4
zj`&?Ptfo~*p<xG=louJ|GhnFL@Q00u&Jx4WHkc?i3{go@xuLThepeU{&@WnP_+TqM
ztujndc&^$|Pzp7d442~2S7V6v1iaP|Ma5xthO#MWsW-G!arI@xA&Ss87@qwOI<FXP
zv?RZ3SWUa;M#G}Nz%?1()>8hx*<imIY>Q#pTj;!I@Rz}St3mM*NSomjRn~SG`1E$@
zG<;Kt(RUg4uR`B-!^@Om={8i*%c;jucon1XH8g&LzCJ@6g%xfXwo^gWO+(m2sO~q&
zsjO<iu<2vCearB6G}V6&8iIx}wA+S(I<yWMnwEpyF;q}oVc3xK3Dn#(aOsG|eZyLM
z$&45h-$mcJVIw80CJbH`AP)@c6p)98f9WMNY50I1&r^oW0Z=_{h^7$djG>RB)w70|
z6i{Yw9Q|qz?mq`(?uU?ZH2xa{gp=`Wy78Qi%UmJqVvJdYMpxr5Dwl9GzH<iV4;r;z
z=sRTm;~R|kurX*9lW@csH3{5N<B#uxb2o<P1Lt9Udl0HUjRM*^c^UW6M)R0)ImOz&
zjUswi*nEuJ-i2?z#>e8}_i<y}060IRUn{iv8=s-yKERksCmsTg>68}^GK%Ve4>tZ-
z4nT<UQzN_xH7<Azy2Fgw_7Dj-_TK>@!gzKJB-*%&-q10|VTww|8ksBLeVoxs@uCwp
zqjWvgoHRb43m4;!rJF%c89#X%<`ayQ6s1Tsj?*J8$@pgyNV4&7+E}C+^C*&j*0^9N
zoJlv{XatvGTuxb#Ok>>}Fqmchyb68U#_P1{&oNFrK-oDXClmJ08~4!ValvRSrI%Z-
zk@Xoo%`+bU4W0SMlVRvAFrK1E%SGeUa!gdAvHv$n78y(F<5|VV$17l>#P~V^N{x#j
z1-#6trz@!3nC1miVLUtx$x5SuuD~i|dM0#M8$B)oaLFi4hHEv(H*NGftTnFQhH0xa
zelQJ0z44zfz+E;f$Dy>r7))8rE5<xpsa`eCxPUYoGbs|#WRx_+QnT?j4z#rxl@Z{s
z8K2k(T&wZUHVnJXxb%56wj15&K%~Ry91JfyjiEgBbs4?4(sJXv@$v1D={B0DFwh>O
z&ny~yjm>$G=`&)Rjr+)0@(~(u8b8kl*KgcGb+!Y>rJFIBTgHR0Lvqk~;yq}&ZJa}2
zni(=Kco}ZrF=nrZ!C~X;cfs8?9;yX*&p1j;nEOUW0mWZNjD0uY@Tf5rh2QhWjECsE
z&f~^iw5fb(oGk-4X)L6b!IUwc_Hon3_8^#;F)pFX*jZ!TOHgWWT6YwU4yJou@X*nu
zTnP`IOgYcOHD}Y}6X0A-Z;t`)YRcaMx7|!54s`z=G`Y=z%pubbx-br#{+tW$h)L4~
z#8J~?4RpJk7SYw>Vfy-e==L-n_yTIYOu_#}Q%$meVb|Lvr$@Js>A)`-gs<t<XpHc<
zDTUG>ex`>$7>mDY+6D^&rkzh<NP(uWs1D2)WRg=fHPkepmXi^tY9U%9O+U>C7iAhe
z1KrW4)ATTjG5J#^Rjf&Q6eP|xmmYp6Od}L*KWX~qHcZ5uex%g%DU<t8APJ^C1^hj2
zx=OciqG@{y+)gsJJqbsXO+P9?&e%+rOE8gQ`sN`-Q%%c-kV!K+(r)ss=^&+m(@hB!
zM$IrKKaIvrlaa3OEK>;;R%DxQw83tUsq-87d(KqH2jILZxD7sCFbzh+!(7u#lpM%2
zEuySzzG>ZhG!~ec%h7nzWV5G2^FmW(B|3{t<ubGuo80Q5w8S((Px(@lYCSwHGtF#<
zNV)0b4Zv5Ja);qXrD@|<47AGBPc_!nrs*I6E}7n@9Z-#FR02|K`uKggR%hCJ0It=W
zB7O(pvPnR3(*{$%?PaLBVj85o<Ep8PmivvS1QCEurcbH9zS(p<9QYQ~2OKzh&E)wN
z`Z`SskD%|m>Gdr5)NRUlLtl^Sd3rhZn)FrB(r5CU1MY@tGp!15npWvBvVPM?bb4{X
z6r_ULVUzs7n8Q8Oe!BASn|4#se8lv124u!fn~uW7gy|UNfF76vX@T+3^cI<)H2vWO
zktx#wDnXn!bp@br#x(p1$gHW4cE9#!p$>2db2~)>9L+zEpwY>^_jLfA%|bd;;bQ(b
zoAM8?W@RJ1aWlX0FO(iM3!Z?(hs=9vw{h5fWDACN#QZ2FqK}$aYT=B#*^N>Z9%k=x
zX!A6?Q#p#4`6C`0kC~tC1o1W>q6@;uTut8|@io6tkH+KX(VwBk&)iFyD1UQ-jP`#4
z<|!s*0?ny6K!VIB8d|XVz~}HO#JngG21CtP<^UgN{)*Iun-lNCZiKmD8@NdG)P9gC
z^E*GFG1@%!-=@PHq5~IezHt&W8fQLF<whsWF^{70r1>=^RL7f}85pPSl=;hVKoiWq
zE8y^Hv-8g&iRRs}!I>np2i@Dr=6C6v8fVNqeSuFg&u&Fys(B?X0MpFgg)o2Cye1KS
z>E^`E=*uv(bI_M*-b)GLEVHu(USylya>3=8k9~tlIA>=507JPp^G^!UJaf?R=*&0o
z;X_S<SxcM3i{?3Q7=59+&;uex<{H{W7n>jd9wH^?o0JVKHRqgyNSQf>Do@JI%cdYw
zVZQM>yr?vPWQUPenS-cizuK&!n(#~J$5z7M8uL@H0$yvjiHNN;fA$m%)|;RB6~0|I
zU!<f{gIT)@h%08sAjnm7Xg<_5npaSrLX+7@r+}NyE03VB#oQDOE!WH)r7+)We$We%
zHuKLr(bsOSqq9^UW{)C>beh+jAkt-K(qrSgd4o+1w%hzv1`PI?a{~apVb<~C+fDNZ
zDi-NCw?2)&0rM?N{M|AyTMCguvm>Q1Z<|+kLFthB8!JTam`g5VE{4s|Q_|_KIp9}t
z_sroRLh`=(_m$8&Vs3E)eAN8PpXeJi5B1X;b=+)!5^5&QZu24fz<ioKeQ3T&q3B8T
z=C>d^W%f&i(rL3deOPP8yo+`@vt~D16Wd#=sA|Z;;uD2NM~mkwh&WkBLeS`JNnQ+P
zE|xd&gqi1R+2;T++$_tS(0I^Nlt%gYLzbd%Vd=2tQ%V^ev3yG5+oP7houJ0uGM7S@
z9+oHH1m|ff9EL$Ji-#L59kY!712x{3->B5Z$0DZ6K3|L7ef%)TE#*Ss{46ySkPNUi
z90xqm()t!ef-Fa9K@)7*bcx=7Ar@&Cd<(T?Q<Y?xrDZ!h!!7$x0TE$Yy#=mCTJ)7@
zjIwN^4Op}#I0=n07GV+QGS;$(5>jy%9aT%5usn>1mXnqZ8i>SOevJU&v}KF~yNQ<N
zly^+B+zNxg$(Em<gNW^n<%PNEOtEC=!qZgCm%A~-G|Tw_$egvb)3Z0z!aN3GmSs&C
zCMetTS}i2cTeh!;r3;qB7vNg1<+p|C%d<>A2`=CA%}#IymX$Pz7cKu%XtvO@G8=tG
zmi&3Z6<Y*Ch?LkYJH7)gwfx|L!IW7#=(%2QIkOs~6&5wsKvY_G_k&bferkf<YD*|B
z@Gn{FGr-kY(l<e})-vY_;OZ>r>D^jyIc){tvL%hewhflucfeh-{6y!wu39`OW!7jp
zO7Y7ki|x(b(AI1j{~m0MWnT<ru37fH3DRnLVIN#;vphy6EA5sZ+NE?@Hd1v+rzL$W
z09}@D8OU|Z^KMYuZPBtYYdw}<=)^;>#rg{XeU`6x0Di;r{9JH1Eq+vX*KfH%;~cPj
zWP1&ww=B<4J=mbd<vVb<Ey@${X~<IbC=honuhV9B*s@m+a@QiKC(J#|y|*#!`<C)m
zkQ}k-oiP`qmUrm|GG+;(#L~FM<15&muy|R4dtmvMf`kt()l}O#X$jhfzA4LRBC0=|
zwiKTRJ7f8qqOh};tyE@VZ#DNqo0FAU1)#Il^#q8EbpvI^U9C@BA?ao{3c($;x^%&d
zL)HY!+8nmJ(q8z8bvr%Sj#{Oum>GAgFBRi>SffY4d0Mqp+3ID@yGQT8V^&Y9IP<nD
zo<gUO^$AL?_*%P{L(OsPAjL8Lto5|y^S7>F3=;v?!2^&Cw7z*5T#(g|9)-cy^Z%kT
z#ENJa?k4M>DbNyT<<PwuZk>=qB*OYP<zOSNFJj|2FUnd!P4#EdR@dDyA7gE#yDHXN
z*bAj`)(A@JoUlGkOPP~aj|m{+ts#G*@3i%vHvoy&_^&auN!Gm->`S)(LJ7Dt)+-(m
zNwGdd$5c|SdjjEhn$@uw+*xbe5==sdwfi45W?Db`1FqS!tQB-dFxxuJgTWkYb`$XD
ztsZmGc)?nq4MeUrs1WA!tj_PDFW<T;1;7I9AqqkjS=FCHq}VFYfzlG|JCwF8wO(}x
zS7u#DRbl1U%T&lwVJ&+FZdY1$Lik%{)qRPPRokqu1p<G`+DAn-HC7Ehp=zzi=su{k
zK0XZ-_12>6z+bkyRs+#s{hA5|u2_dQL-MNi?lQR6XdROQ-eevA8C<iqX&N53Sf}2G
z$TjPCZ1lBSCG_t-+N^9P`r56mH(<8IYTG*jrJdH#{s-T>tZ`JN(rv}vkNe1K`y1qj
zbwMQXH?6CwqN(5dd=c;i)&sO{y=8TwsN|qEf|8N9t)^ArhOFJ!fV*SeK<T()YXR+E
z?^+9e;PySMwjIhwt$$>qZw&Rv6i6JmrqPW%VSR^cpB`9u(Ih;yru~B7VAAUFF6Ls&
zI)4>_)7B^725`p8`WcSSS|jM*w6}A(4&rDRv;ZDD*}Yl@fV17l4<O=V_sbptT<uE#
zf(17_*Z+>7*%_5Ebj<EfJH<b}?bhsujE~(*$uQ_^=b8)i$L+pe2BiUZPf?yW(C+t}
zzz5k?{0!Z}c1dIC3$bI^K{C{C*BodGv)h^mrQvpK-bZ7EU4JhoDAG<v;hQMCv>tHL
zcCGZ8s~Ees2<VKp`|&1ye<IFqJ0)t)*u6Uje2U$?Y0PDsU1u8xbJnh(4s)d2jZkzx
z!*1J3*v+(i@kx*@yWanEblq`TR$p98t;{kt&8%!`nVC%+R;HF&ni}ukd+)bQ8`kSU
z*(%5o0Y$b5C<q8DLqMi15fKCdL1ZXf0a?HA`Tcc1_ug~9=iK`~&mHHS`@HV}JKgEx
z^8mfzH1i%hanWfXxydd$E%_5H8BWjT!<bB`sb7I5%jqKd`m&wAo&(OyPNi_oI;Q71
z9r=GW!%0Gijy$LM%P{7OlY_P*`A(<ofGKd=MegxJr$h=}7dbKG&{pj9`hN7O#Od7#
zv|V*tw+DJloy>EAUFP&G7cAvYiDRg&aB@(9rP8U1487*GnS9?>PCw9`>$vXpOaU6J
zo!%$E;0>q6WK4~dU@jVOI(<fmom!{gCQ+($a_a}@EvJ;rkiYFzO1ry8r;aLAHaX2z
zf~DDsMM<G|oZ{VKT8mTub0Dow(U(wp*U9LB^=(cI{z2tErvzt=OuNG=hYr{sPIj7T
zI-Q>V3Z%;^t{s*4onE5^%m+?yQ_f?zQ*JC2_Bdref~H=lPbyLBbK1QC9qo5|^fI2#
z0jH^yu`=kiuL0r@onp7b`bSPYI_(cR6>LY_u+zM^V8w{j?=L{$v6Ev)CHgz+R5cS4
zV@_TNpnlxRJROY_PEmA*m~_hd6@t4NJ1Ado52L{grM-;z{{qWC#)>~7=gjzseBb*S
zyC@Ik0HbO>EOcRf6^KfA#^)92ga_mOCRpLgm=r_Ki?J>Oat9eR9WG!!#2BVi`(eg{
zFevn9RFZGihw<bTNE~5QN+IFPsQD0;evFg%An4Cvkoo||wlR>SjJ1^K5Xg9eg}xkP
z%q0JG5M#xgAi<0%`t3s)cFJEl&QOyt_XOjOXjFzW@_if_*^`W!|G<hchBw{r31>u{
zfnWrKMc3jY8Ghu$j$*t{A5w{CbkcJb!|0)#U8fkok%uUjQ9$AJ(~S6)sElK*CD(gA
z<K0MbCNNkpL&F(HS_GiaGE6y8pU5a9Uqce3#F_H1&oT08hmg$3r^9Rt;}m(sQW?2)
zKse8svJ@nZVQfWZI^$ESyufhnh5SXv6v`>M#Ar9dv<${NipFO$4%3gG#W+Z=&TPh)
zOc-;S5xxZiIgBd0)R4>giMGFajDg)0f4IW<lI~RHGoBIvrhxIG3wR0{uTt_u5o7yF
zuog4^It8>6#@qDSoU4pgS?F3RW5FKCRWP!OP^w}K(s}hdBlme&QO(GpeZmcfbQQpA
z7(2r;PB$4Wiv89yDilDeW7Kt^<haGyVugx&#u{>UHZaENHpOkmHxIzm$S~7n(!}Va
zB!p(h9ZEjB!#Lpq&K5?46F6HLV^5*&E+b6>v^It-jqE+fPm5qhJEPhR^&O1kG6-}s
zrpAJFF>+}mcAwGe2MZrK7$4Ei%5DZX9ai)(7Vm??Ud9Kjp{b8?bT)YU83~gp4KQ}m
zv@^(fuNs;jG9*_}dc@clj?xe#t_h&SjB(2T8DVG^qU|xmJ_W{%GM>8(mN7>B^UyHP
zI72R_3C7R2ATY^rY@s9SZYHZAdiO95?XY_<b3OUD_cND~<MaUY@?sDdri%m;u1rHU
z+T56N<ZE<i{`oB`y_hAvU^&RNk>~Lc)430AKFojxP=AEE<wcZynVx)%s2?*u7M%Xf
z_HncYFjE}KXgtQ;Put%hX7!V33}#l=12lyBD|sc4GxN8CoM3K!8Q7uBb9BBq$(&8w
z$uK6HCiHOT5qdWxm~3(+L^4Z121^uk#u~6hGvCcYDTW!(1Ij7p!cE|eWp4Zly*|w>
zy#D{359YwD=zTo%sr!&mVCK_1c7_?61MIWRC3jFtWOgnDS`u^bKOpCr@5jNIWM(d%
zj#8Mdi}5q3GMCd&c%Jzot)gknc5+aqGtF$UTwqqv&g~*IhJ5Cim`St`%wXmxQT#8H
z+4TZyvzP}vAd$^fb%R`HHXH-VVV3*|lFPjH2K44JXVR2*g&7@y%6w)+2}~<s7TiZ=
zA(Q<kx>m$oNy|ww^Z6e^N|^8c-vz*&MxLco=GT<aRL1;~UWamK20VZG|3Bt~7SvWU
z=TQ>SHKr{RjaAIg?ND)@X(@wXHFHiHx^{zk;sh#dm>FGQxyk(Q2HI+wb3Vmb)-hkB
zC-4?Cy$Z(EGoPjRzJa-N56o_27SXP-nHftlf;-GN=o_pp%umTN?Pz5#@xe29mpO7B
z@@>qx85oOu%&aa*v@`oY0Za$8i%xu<%s@&~?qV*pK;S;}<HbOGz-%-Dt(zGh4YVHS
z7v$gWWm@M0tdF^26O8F+zLNzqz<i04cm|oy=TUmd?A`&EM-JvNh3tlyp|mUwGv}N^
z*G8D%9|n2MG?U|V6u$@r$C#^{!8y)sq-S-4`L#RRCYe*Gf^#=3Z8~h)!`kyS?A^;M
zrRdr|mJ?mja%LT;vDnYb=z`t@EH@s&Tv%56uB0o=kxNgK8|&IKNVu~q64B_v61{;&
zPgZ9oD!o`cS3%Q3RtII_9Ae2RDt?&tR5k4NX61yS<imRO5;PrQjgv3Rmz6{wF+Udb
zF)IC8k}Kd0U?pF}7#?N)qJS}hEGC^6j<M!BXo?78*``88FsuGg@Px2VEJ5iwYg!vh
zCs+;N!kAFj^mJ67WNnXvKp2Y?4481%n}uMBVr?exMl?{s8N+g-U;8v`=oH%GSWz=T
z;#tl#2cBj5(#oF5T17sCB-W!h9jHCWN~Du!GV48>(o$HrOJIH)>s&WRCY|*(dHF7|
zR?dRLi>&2z2DrrP6rnAHHBKAAOqLtP|FT$bx&u3#RZH{hW!B<NFeZof%a5=(mz7U(
z$2`_`iUD0=Wzsn}pCxUk{Idd9GP!*VS&u2{qKH-13G8Cl>C2EWVJ)IZ=qf9fB50*7
zZ;E`Eu_7d}qMY^jk7%o4{o0M*SF&c;LGLw|U>2;XVtuIx%XQX2RcNbb{Y?(F8?3eD
z;i+NO*wA*9CB|(e$Mjm3C!J5~ST#4$c#HKBZLjKCr|2Vp4XiW@Hs5A(Y#@!S$Mjq^
zvHplaTMH{K0$pom{X%QwU6#+A0BvKf-wbk(wICSQx3iAZ>8OJ>or}s&RutLP#gb7_
z@IEVyW-Z49*5iGk-K=F3=yngQY!f7US)bDfqxx8u0O;*!EiysV0PFYl;2dQAN@wAR
ztS71M5vz(O-62-QUjQ9uEtf!igq7(B&c`fkEZRm{Dg&U$SalD9GS2#B3!o=hLdw<J
z<6tM=0qb6NQw_*I_9Du#JHWnk7aetBo4y06E1Piw5^n6LJ_fcsJ2wGs9_(eqQ18j!
zO&c38_J|TJ2ifapfgEDbd5Frx>_l3>yxGz@(Cfpl{|&$L5q2uwyYOX4z6V8qY)4!*
zSpC_&{iqFKOXx1wQTDk6R0gtp_#nsFtad02VgI-l>W{P82LXD5&84KJQ1)gzqn%{m
zBUfh_d)^D^XgGT=4+0VF4>@3oWXlr462&fj3muGR%WlG$81@$#Ksm*}?|2`zv25Wo
z$e(5>_=Ci;t+Wk|XUjeWPXhbgS%99Q<Yc@+?CkGgVIn(<d^<_(#}s!w$Bw1Vdop`2
z0$S5k*g>Zum&$G?N5pyd1^P~L8hbDtmFeuYl!$zR9ZTNzi|lzCib!2zJElQz2D>p3
zJeh1=Jq*rbzg7el*=!!Un=i9p@j+z{dm+smx$GZxfXQP&If#y4VK>sjFQ5JK&(KuB
zo|c1BA$wX0z>3)M&44au|FjKlrR-etC|9sIWdXC2{mxeu|GUOE(+W_<wrL@FoxSZR
zsHkQyu%q$@dvZS{YS^DHLgh{NN?IFh+4djMR?kkLH?D!biL#DvvlSFsZDcQ4jLIf<
z|0L8mv!|Q|=N)$UHn6m?|Dym}D|_D%ewe%LAg`zK{<X7(v>tV^Q)ye*$=<aE5)arj
zDH*PtolR*WJ?wKdwe+(S$vZ#5-mwT|kR7}hEJJJ^-NhPa7d{7+5%xO+uyBm+Q-HQ{
zw#Q2#6YS?K_(At@meO|-_HvfE!<c;>>0NL-4sa~h7)uvU@IH)?D`(sjB@fQOl-cgd
z`K%SJUYuFaLg8V~+GBw6=A2ysg+83dVYK;iK6(|L{v3C5_ylkc(rkN-bKi`%AWlm+
zz=AnOSCA8&=1Zsy<=mo2=Om}*7jQ;6I896xBRP#vKz$TvJNZvfaelgqQY`0~9ON{I
zONqG&ocR;5;ta>j7j~cJG`XR4j<ahAY)a<rcoQfooEP4MKpN-Er_q+qdEz6G3moMD
z#xR3Za0POioV9TP%i{bI3S)9Oj{C_d=5iKO#6FMnIc@n0IA4={y^zyH*Qbg&J1GKo
zmE(8^Fx4E^Ul6>(ai>|nhV$xvdM-G_blt0#;}Qs#dd@!#=xyL^oC}uQoFFd<G;%^I
zP}0O%Ls$HoIpOsncQ~sZzMw6f7}`X%augRJf0q;bFVwej_Pd~Tk8_3MS{<AnWhixW
zZkxf`#d)|Edhc^Qe+TFT&O2V{b`R$`eLl38BcObaKF*3fK=*S_H$q^5bAvJ%2RVPg
z0l6X0T@}bMr{*EW-$yus&X6DD{B;hj<DB_&D4gKzc^$pj&Ha}4MSHlP(57@R_i37F
z_HkdN2ho|U-hgf&;11HoBNy&7w9vb94^t1_xO0;M=Fa_f9s1(IWsxt+lk0gD#EUy)
z3B(U_XJ{z@^ANYm2iS+X%vG?$o4cBB3HWerUqjOo?#n#D_;L{k!^6hyZ-#09+>mq7
z8^C=+4RVwlLDA1Z?nevJc8n|D56%#77Cke^xf3^_{si|9?V!TA%gOy3&K1ssTm(1q
zU3&kbxmPwoQw+D@DCAFZV=O?6<F*Z=7xCO*$Zwm#{qqaJByzvl2$&>pZ5UwAaTye3
zOXVJDfZTcRN8bY_jeG4f1TJ#3C`a=WcX22LGPn`tV9DlM$S-%9yPtu<&*6sti=H{I
za3v>!ozHEd_r8GpA|=rlaucq>iX!eoI!zXHchdV?!rf*8+Es1<z2c?Z!zZDsj5|tc
zq~+YmwLq)je#U_n*SNpYk+_Phm<74(+;1r(qMBR$EXWP+n=EkFaNpNL?xurV?gG|2
z?uAfTaf|!y6OgaxHqi>wz&%UhliOScIrJL2OX;ZA#2xw`>YKT1zk@M%xWA;Jqb=OM
zG*Ps2Gf$xMF1Ozkq@8<*HoP6&gFI;H<W_Ug?FZZ;@&|Tv8@o{1!*y&MMr|*5L=Nme
zt`B|pqM!Q@r7I0^|9%%dgWT#-Sn-f++JwqS+?N+ZV2Hc=OORpilD|PlxF6Wir^no#
zCX`0G0~BW+<F1+n8Ry=QhV>KNg_P<w$z4SWKD&7;IXbb2_nM;xbT6-jW~hC<<u9Po
znK#r3z599atKsS9{V@w|F1*dNf#%8^rFGYh7a#?vJMW9{!Rf(E_5+G1uY;`c;<Zuu
z{vhvDTGS5lP98zqVczFuFwL7c{sM>(Pt**|BfOs*>HYKNZOnj#AJ6dth(B+86kq~)
zv2($5lqZ@36@k3XFJlmn@ji%$-XNX}Is1Zn^^`{)!h43+uj9OMioc)Wouc<Plovv`
z!%y<=|BSXU-iF_S8O}?klWhdgKM|!!-pubQ|164Ux4?>MUd%gC5yP8G)7B{-Z!3P-
zSe}aj3QzM^(19k7SJQyXc;2GVfSte#qsy0Pcqx<-c$U{k3w<JQl9IfVc%RS$a*p>c
z9l4Tu%RGQ`o)_zdE~W80{sc+qrQ_P7WBLW22Onq`c{0lPxx_P)r5U{AGk~4ROPhm^
zX7R>;M4z&GCkw!NnRjI`?9Jg#q4RDo?-%k8=JBRa2g?=SU4LNb^S<pxWdU!HlAa2A
z8RQcx;_aUbuwq^jWd@b-UOs>}$5q}pOt6;n;*vnhc#@wXU(O4bg0+ITQUK6O-V|p@
zT;uJhpR$VQu?=0j&P$<lST)b*CMs|6-08eq!^@vQ+f82fdXQS)78<8IUdb|m-Qu~E
ztG}N2)*n#Rz}x5so0=TF<-dccndd}NkUPAabgpUP4N*2sEAO2UsJP2po{7pf-oNx|
zjC;JN-T`MjFL)N(I(VFY;Oyl6cLJ4Nyf%8e@ALknF!}>t5#4y`=H-#Qs)y%6@s?hm
z*M~sq<Gtwy&VHUFh6TF^cz;l6bdXn;j4^r0(|g0VN4%{EATh*iX@iBsyv5xpjqol~
zEcG#O<If<Yyl@LNjq#opKyI8D@-09oc+=hjndJFVzRzy{LHh0X@Ll~dBzyTxx~sa6
zKj{PkXFlISIlTM%yC}io06(A&y>Q{ryat<G`3uQm>&AcK2ukjJ8-0GpgP(B~@}7Lx
zOAzqlI|o41LH<}LP!93`U5m=Y{GYd?zutUTidFmY=k$Q(2tRfWy5!6MA_**h{AWJ_
zrayn{cMdcL@K4cs_b6W&4@(328cHHM#-ApGi9virFj#{5H$0&tg#V-z*vI)<-=cJa
zzxi))hVs{)hTKX18Tv|B7{BLNl*0M1&~z2SKk_t4B>#iM&=AExPibh;{GjK663frt
zOy|GTe9@PvjpN7DcdpLxTV|r$XZgb)z~DrFI_(wH_{So_a*<#ACSWe{%@k<K;2+BZ
z$>h%`$8;9o<t>nGe!&WueVKoee8@Tc+GQZQeC0J@Ug0mK^tXKe?P6G1z;BPE^Isvq
zdMav*_?!-mS22IVHn3jh4?RX@DStaTh|BoS#ZX_)ufKz~3jSj{R#oy}FoIm;zeBN&
zDt_4kbo4rZ`yZ&R=Fivw6*u^=yF#FbKe-oRH~G3Hu(y`q^CH0N_=gUo&2fvrlK~a=
z{AcKgZQ$Q*Md>!*nKI=X`ES#Hp^3jD3ZTvWr&3_y9sbNdkQRO)1<+gh3lgB|F8^cN
zI<@gV=`eYZpL-H=?R?20aCY#k>Ev{uA5Njv2mCXqz}d~8S`X6W;1@^3wqE|qbfER|
z-=l44KYu2rBn<GIrlC)R{9`oHJmmM4qw*1-&xODc|BacjX_$ZhW0XetGbmd0n2*0w
z##_N(L*K#~<FD>Q<v4$>H#AM~-*yL?<S!@j-GXJCp>LnS!KQ$Rv%s#0-u;4KX%#;p
zXnr1zE`o!1p~6)#mr@ek1Ti$hxeKx>L(W4mwj7!~1rCa-cnN$dAazinp^u6l5<Ed~
z`e8wAKLor5dlo_5N5B||+z~;m7{pi5Nh!d7g0&8E1^5g0(AyCp7*#{?s33baBmxC(
z@DEHsCTKqi&>(?~e%N3E*AtpT1oh;y4;3UIgV`qqm9&6_2@>uBEK*Rh6C_HoY8?ck
z1;OVqc(H<%(_lF*kSZV-Cs4Kn`i#J*me#+sf_S>JkSLgoNq>5>;2YX7rwCS_#&D+!
zX48Y1CU|caG^Gos(E52n@G9L%xhU8{$An9Q+w=rx3N&w_ElcnZU4_mTT#%v@If9sG
zi02Akc^{a0f@t!VT@mmoMJ8X+`zihZN}=G)4HSz6QFN#*7ATHG?^Qv&5T#PVEK2?>
z6BN?Mvs|#&37{1M?rqq6O|WVZoK*t9-@tiYFzYs~uNGv7qjW>yOHSY#!N(g=Str;`
zNiDYoi|PJRz2GN0aWx3Kq1G||wqOe#VHyQ<=|s{b*pq=Ds9BKuB6@g7@Gnj1odOwc
z-MR#8OF-@m$|#QTK+sPCnr^{1I+*tghAD#8CkUjAd;J3MRCIJuQ0@!yA;Go1Xd4#T
zKZU@EVEJnpr^kYti)eF<3S7^laZE5T4wjA!f}e!?3Bh(s9Gw(ALG#>h;iq&*Z;w#9
z01|tJS`JDFg!4zC$wgSY7L~5TC&B>gCghC(%w5<|)18O#M+#zk3f=ml*Gt&56><lK
z8F8@wi15|dL3|y;cV9+F{e))vPKdwoKML0d2%o1<VI382r>o<E!d-NdIVPM&A=Mz^
zpIZPEDtt8sDozTASAm2H=Vn81xKK*_u?XQ;<-m><debgAO4w5m4bj4lDv%iAU(M)Q
zyzoLH>`f3lbQDTDBb=b%#986;Z=pU>c-#VGl7yW>;5jD@FMwdOP}c^~6yetCP?#pn
zcm~+%!cg)DUJ%YakG6}##Ls|oNyw)pybNLaCRAn$wQk_d5_(4gEL-?p69g^`4^wJD
zj_@DH8)(cG{!X7ID->>`4Rew3c@E@@g+Ir^v=ZTwXVKrQ!i_qhl?pp4a9<{D8^g$y
z3un+;Q6aop0kmr2{PzHML-+={lxl=?XdieJYa04nE3{K=p-!081PgBo|Ez#`z3{JM
znm!tYTPav}N9aOlwH9F`#jIO}_vr(XcZIxCkT#+3uORn?GRm847jBb*bO;06p`ugB
zqBB~LFoG(3g*Pdd*(Y2U22K6KbL5^I5We&XW)BJnRzTpPFyt3-J`$EJrTyoS&`h^D
z9t)G6LG7q;V*+d%6IRi-Zd~}}=Rlhfjx7Vrq|lpUZM#Jq$z!=kR7X3hy`rV_z_L#i
zE(Er-D4)X1`$f|!U&meK5ss3F=;LNs?<pGj44ht~4DuWv6#dgj@xMc&H)!%ZEJ`{I
zgS|!f8Zj0=BIDOk7$Eu}5rRiWFVZs`C|VK?v|}R0F$e^Su9LefSX8csO(CK(IuRTf
zJ?{h+Cq(zZLnk6cA2&cCQlzCvFG>_hk6yIs4Eg0^MC>MrJ5GtFszGB#&UJt}Et>ZK
z&jO0RZvk4OD9{Kil0+|)W9*zr`2dy4B3T2lQ$+2f(3C2=z6^5bMS2lX(nNe$V5f^1
zNl<u6wBszqGemy(QOXo`{D!tH(Y6i<WQ%%EK>V^pRN@A-98n5=XEj%}VhKo|$e4rv
zUJ->+u5`XgMQ*kN(E;*7Ulq+HUqz|NTnm^oQRr0+P`T*50-7pBUzb2rrRXvReXog@
zN}-}kly?!BH$?(k|7t~{6k@LvZM6X9mdK%3fVEz<cr(x%L{AT*@wO=RV+b~iv=kF*
z6~zSs`>yB&rAoJn8YAgJ6pgL`X&2=u1GGa_`XxxGXhkl>yF?o{f%J+_Q07RV=sWUw
z_KP+?0_K2dE5#NDML%+(_Ms@xLAUE3i5}9<Z%EWl^TuOQ4^7&mBEOG7#zdb`a9~{Y
zLJU|YMC>0h2$P~fIzPII7rH@(tGN0U+T6syQ^des9R3H0hdAaI#689C2C#UES#*8(
zpm-`>x;`X+IueQwi~p!`py(}D_XEvG{2XOT9uW)A!8Tv<D80sh;&ECO1H>bN06i+c
z@fTnM#n0Qoc}(m|4uK%?^j#n!;$<|=9v9F27F{|ap7IPhPl|&t0VPa4UkS``aRhm9
zBgE_I=o2Y^?OED?#)#j01=y#={_SXt6{~5-d0Jd+0BD@Jk3JU}FWy93w*>LCv_U^3
z-fM;YS#di};Ys4Dv|~Ic*8B;QEN&&=PKx;936NCrhUFmV#ozUy6Y1jPl<IszEHFd-
zqBv+5#s4mex2b`hA@(4@LZ*1vIt+J~xZ^5p$`=1ujke3;nY5A15%-brEms^&$>e$B
zE0m;lMI1xVbH12IXTt(<2`w3gVl8=Ei^O_5=oX8Qk(0heyyy;Cu8IfFfu&Sj`XQ`$
zl!^bM-A=jqHhI}A#1Gy?ZI$@lDj0lS{2xVqs>Q$4-M|~-UV4IS#3%2f?WTCa^XNsL
zc$_wex5R7P(9wGF>mwiy;%vJ8aa%l-4t|YdlMxm+i@&7f)E%+MJ78%M7vDkYu0!nX
z4YW4#D-@QyC!Q4sW7@^lt-$UOkHn*`Q!F@$UUZ4u>HPOVyn6=Py2S_T(3u|b<RPf<
z6)&Y}qfgBL3oHZTD%vOyis!uq@=$!z4=j(wl6g=#BtA~R{jm6j1sH@;vE!rHAUG!O
z-T}dJF{1;l6XM^UP?{9?9Dw|8$#W}F+9R2uq~E=g!<50iPqOqb)H_ScX~o+w`8x=0
z2PC8UXmgQ#N6Fx>k`fwxH%YV%Ebfw2a<qC#N@=0>lyKHyWV|Fs2i=D~C{dH&=aA&{
zjQ~9?iKI(w-V)_15Fd$64wxen`3@NDD@nZ#6@HQ?^2GT|UI+zffTZ>nR34RdD1Z_u
zS=<NgW0GexL4qVQas~xUa_N$3h@|98kmC}656GR6tk5{X6Dp}(g)uoPaXttYVUkaO
zL@8V{n^vU=$s&4KBPBcNqs>v0_Hm#^OaAyCoUxKGUWE8*$pu=4<0O-G^(|hq$P3sB
z5>Gnlo{?;x4bHQYn?Iv3iIS^sKuMCkG#@DEB=3w-{!6kX>=&@6NG$i!m?{aNAo+R8
zS@Nr=NwR3mmo7;&V%RQ7yzc<*qGZljP<Tla(E^wZNjMvAnUW3UxXhBwrXy3f#EpKt
z%aW(*c#<ROp$v{($%1ik=1J`2dblF_$$#dQ@2BTW)Z{WLkj$am$AyxQUV#-w5*6+4
ziX|GFN=qcK(S&|gvV}gYQY!gr3Dj3e{`(N5QZhT>4aU?L9onDJRxLT51#&~ePX<bj
zMA8W8o01LW+pLwWpM>5zNgsXX^_Ju}iZs+qwo_h3gQS!u`P-5X+W0j}LSBdUO_Ia3
z&^AlzzJd51$&>V-JuQ+*6S~wY$vFlMcO~0)qOwhL%P|G4_avHhG<Hg!OF^kil1K?N
z_a#dyO#48RybGY+lCu%e)GPVxOUU<0ex+2+e#!IyK*fNh{xP~VC~3ckwucgrPk}Nd
z;r2p&Sduvvaw8J|4zN6yeANY(QAwN$m1B~9iyh#ZkgTI9)ud#>j{w~*-F^^cuT;T+
zP5Y!Du0hFJs-+87`=t|p;5;CGlRSs6(nmQUZqoWR*y}FcL~axhsg9C(Jf*##gLp}6
z6Ci#_I-72n9+rA9hdytq%X6sok?Kb2L(WH}L!$uomHx}ekLEA^fgD8v(wb?II4XUO
z@?V0b-%~U_M7n$}DvwM5jf80@q;cf43zc4=8x~>GS~};3OV2j}J3`u!53oq-e%e7r
zNng5#%4lf<rGLgqqiHpYm7c~T?3jL9diw%k;-nuwgnYcTbqKvkkTwQE{;YI-7UUD9
zK93=oB)vc#JtrOc6#~i9VmXE+MY@0z3{s`Z>mZjdT}G$o3)0^xT6<AiO)l9>()@QJ
zmm&R|ViH->h3n9lZ0Y$|KpdB)O8R|sr0#D(VXkzLJdb(O8QEyem)@gyvq1U-y|;zZ
z4=K=5B+aH=)?(=>1rAE2E|lq6DvhPrpiFw6a`wxmLp1ADN|)0#cTJi)3PY=;e^SEA
zb?Hy!xTuz{X+^2VA^ji~^rlqV2G&~XAdx!hG&=F!lDg9lxnBB!@>Oq3^_9SGlscQx
z)+GId*3@PxmrfFQq}kttvqf4x1(kQD;qxHSCQVrauzS+k_fYDRZu|yv_oYV$!16$v
zO54Y7spI3Bu&qbxT8?h_Nn<VmtzW8HfYN~USw6_1bYd4^9!fXT7iJzwqiL@;Bpuie
z`4Q>&OVQEC(yv#-v{C7_w?W3F!T+LiT>28-#h8?C`4kFw%bvdp3-`#pDP?%CY|TQH
z_Q|d~ywQ7SnGf}Fzw9eIQ@YAtI}R0YG9MrCxXbd%pWq?uUkTzV+e3$7FIm_FupE?~
z{SM@iEMYb}aai^gIhed<xfL+YN9LfJ@Q94j1ZZDba~?STWIcOO@|Vd=U|N8zp@$~&
zqcW#f7!@dchEkD^$qFdLHAuE(5flc?-Y!8YM3!bnpN`A&UWSSjvacxc9V+{L586)3
z=2BjLn5>W%+HhHQ5eN=7m4J?v-6F?-l&p+WT%u*lh0qWq6UiWON;dR11(IWB-78`K
zY1uluhZiUNf?of4S)L0@39<^>Je-kzQH0K%l{K|PFi{rsJp__uU(>$koUH6~a3;%k
zZ9})u%Le@*kR}`d1)S-!KgM9iC0P)KO)_Lh=_kyT?YfWBWtpUi9O*f-KPW9LSLRQf
z=zQ6S^yn7Iw$P!YP<Ap35+yQ^8PIf9mh?4Ll*;~~9d3op`xBHZWt&wHzb1P(2_sW2
z%Z>ud4Otfj>}zCR-$T4kw%`C*Zpl_J1gV!D{{$?JvOms1+|eZ4_!-ceWn0LFc1IRX
zft?na;|VBim3>CLy1TNKv%u0OJMtE~c25>r2$*)6p9d`Lkd>!_rAt;3iPC-9lOLn>
zK;}%|vToT&GJy5SHqesMC$k$M*Dw2dIus4a{GS2lphLEW&HxW(9i6b|5jum$Az9@{
zpbg8c8&EkSt33mj$FgO=!KP8!<_dt0$u`lmJ}y)E19U<*SqjccS+xaiyX8IGp?;5i
z^mBmimD?M@vR@wV3xx;dv+3~bA}_rQ;wpDM^$^%@@?H&!?((PU17aTXTlDdNPx+1=
zKszXRrES?E`48kDJ1p<yLzA~WkghxW$UW&bJ|YjE4;Ei}VHt>@{8M`2kIKJVkG4R$
zH*H~#$-`<P5F(#S%h7T9@Ot#+g#2R%<t2v7*BnLTN%>iNOv2?m$Duw#eukWrk@5z5
zN227$Z_pMkzwk4xh>@=kMd_4$&Zp>Mto%A<rJR=kO*43${JDD&NRhYFES)OfKyTc6
zxk-%5G<jM#x|=T7d=Hch@)W59nl8!{pNFPPaub~$GUO|!p_D0)qoYffypL9{Z23Es
zS9n<-Nq(Cg`8rDc%9TrKw#}0po(Jd^`7t-B&zGMQfu%sMTmZR3`FpfMD3brt4r7Yt
z*@2KNk;gxPhO2UOAH9F2a;I&mEt3aPMpC(aX9QR)<h|vntd##w>6F*x4;KKYTHZ=`
zb#BNjX@aVezx5E6b@JX~2;7qY<^h3vc~c%L8{`WpaCck&2PGsm%GXYXX?Ns(l%v%m
z|Cf?7TjlQ~XV)?PuH5etSli^0A&|c(_olIEm+zkr&<^>hMIfDW!AIy}m%N@{r~C5H
zC{5{seAO5D?YiYIlPLAb-)#m;uY3;qNc!Y^=}6iyf8sbW2jotFLGPe^bqZJ>%G0jF
zm`C!gGiY-R$+u9zaai6kA3P)SS19KESU!tx)s4!>WxyVjPx}L8Tz(Wcf2L2!ufLBT
zPRdVF-pg)9g$m+(6v=eWWUt~`@;vNQ{6zDsv*HU%$=R>iPOsVl#j>l=>!K+81(mLf
zGJ3b%9E!7)GwiNV-G&Me1>+!UJr(6usPt0g(*EY4!ix?Y-ile|L-tW9>C*{E6j5}^
z##iw^o$LJ+4HP){SG=nSc7WowLC76dq|vk!sOX?j*)c^Vxe9|60mor)u;L<Re1#|+
z8)DITTyfzf)SpnaQcN*av6r%rPAXoal{!o@=>zrQ3U(n>L@4H+fWk;c+3V00t$2&v
zATf&jH0PgE@XEmwt7zW^xzh@p1!EYm7?}!%35td*5ICdQMThkyMdLDXo>NphXf8`u
z4EjPoMe)gBD5WYQ^iX(Sv4Fy9X^P)^A(*Z(XaIUaQJ4?Gi;4*`1THBi#o)|PtS0|h
zrs8Sx|7R%%K8C_<#kpFjzpT)bA3jI1ol>rH6>I3-%v00_qk~rzJ(tOmm#=Vh1}RW%
zrDeZRv4c)tMT&@2uof$d%wR21><Nc4R}~_PjFu{v6hTFq;uRn0EmvgHsj5OThwhbC
zDh}U)z%|7l+HY4Wn6==%uK1xAZPf}U<t5!zWRr`fR?++eInwJCRdRIgmLe|)we^bQ
z$si4iAh_A4-&UAE!f-b#qL-txN%0!(Pns12!w|Tm_?Pm%TNN2kp=);)_ojfeO;Htz
zwr)jE7D$iciFoMkRXk^ec%MR*fl|Msa{(+IP>7<Y;Qbp^Tp<70L&Z|^Up`V?`wnDC
zacc_5h@y=yxjk06vY>ZVp}YhYV~RgHs2o>p$wlRaB6=3ECl%AKqH>S&bvo<pRc`tm
z;`@{zPeJ7YWn3GKaZzgN?w6}l)qs+la?u==9PY{<4ycE6<1N_csT^C1l9w`to|c2k
zBKj!~DHoGN+*|qYPN?@$-U$cG5oO|a^ukxE+=p@YQ`RR!ufMV}6(|A9lkY)ApmG_7
z|BfkHM<5=gl(axDSm~mL*&)hsa%G)xC{xHO8mfFZ8}ebw*JvXauG|@b!H-bxszh6~
za_Jh#$0(Om?(Zq(r{tYTQm#G>W6mkxeH(Jg$^$RJiWKD=6hui?%FjUWdF9(QuU=3(
zyFk-L<<0L=c}eLs6BcGD+r9&5rqa=Gg*92qHA-M-D?i={g_o5@<h0IFw%>z_TxIPq
zkjPW&Z$s}D<q1ltC{QLn4}n6ZekM4Jlv~J?U93DqUhWblKOCH8$~gnDsa)ybhPDc&
z^bAUsO6ykuyQXxfWw%PX!_fqZ>&lZ9FR516tb^bUWhHsyYLwl3QF&A8R}I!$<(HHX
zQl~7Yc-AdtH*H1gm0h=CVT00q6>_(g2R{O7RL-QsN|RE55^c@Od35%;qfCf~q88;k
z+A6jx$Al2StMm`1KysV1eF8?^Q~vZKu-lch=o(Uo@&}3_cPicK>n2^w_h{a@uZ$^1
zXC5g32*EgYD;aI5>{0e6f%GcB{1u>m%9>1|^ebD)A2*;(B#+6Ua@QMB|4_NT8>L4|
z|I26_Ql<*%BI&Sl#mlH2Q8x5L;bUc(1ZbnmRvlD~DPNrp!Et4<J6I-^WpqrKRK82z
zvfZi}3U}^R?I6F+e%0%LL+=5V2mQ=0s^OhraaG;g3OP5`96E5it6ramHV;)<B?LTG
z;tD$dd8v-q!J30Aw?EOfL#h|)BQ}RsfBX&!Z`Ir)!1$=%rU>H^)t|4R6r_?BLT|9@
z{taM<s5*W?+i_JQrA(eseUl38P*vqd7;{pUPQPTBib(<4aMk5Hlp<7*>3|!lT1DF%
zN0iE$UjJy-cgr9jqw1!Fic_j;CM05226BO)R#nnQJ5JS?gtmCqmOZdAL8VxT(izqJ
znczID`eOp(iK<Eo1d>#@R-^Kqiggfj$*PqUu1rzY7lNd!c6LMjylTVWFec5RTJb)L
z>8i?ZNL*0yi1nhX*beMVDvcE+Lls0*c&3U!1uR*r4F-^G)#~q1d07=pX<0d{y%aCW
zRn6`IXr8J>0+uVPHGZ%uU-j@~a2BfaC-GPnsp=`|uUIu}In<V@97S_r;#HNE3@%l@
zyABd%D!-S2R<62CSsE3p8TC+6se0`vkZURf1@)>_Rdf^Wx@zQG*juA|dMVm&sxm0Y
zvR0KxzT7%hz+FJ!QoT*roa<F#t+1j&weUm8-BwMK1Ef)v=Lm!uO{y7m?Y~*&F^1YZ
zsz(oCVvDNr5U^WSEmHw=SGCOrFm0+u^i$kZdD8cU+Eq@w!P236L^mTlRmrqL=u#zr
ziMIPH&rKi?RORG^?N<Fr|8>x#dYhcTy{gxZDD|mY)#QKaS8XJ(<bdk)VOTM!Dx<yl
zLsjgDu;P&_;aiX)Ro_qG99GSI8NDA-IafmOW7VduAfu`kTxc3oofv}^<0>}Al_pe^
zHk2k+TWip^Tm2V#efOz-5+UHMHbeqtzk2X@a^$(HIh5h!rXC7~pu75wCm`sh?q`7<
zROfoZ{6lJ2N{l$HhI1Zog?h(a7~`W}@Br9H)KfO0<g0#;j$D3f5899UtEba;FhG51
zIZ8*>Kdu31p!)7ZkYnmhiWCH?Fa1jAzhHGfrD2Dt=hK${xH^fPeJ9jUl9Mo0{p)mq
zo>bRT2scdKK{H#p+L;!<2=&kukVy5dXCN1){x=VOidM78aT24x{ufH8)f-pCia50&
zd9vfxQz;aBR=u7si6*Mwrd^>UN&Pvw{?4h-=Af9YHf#lGihBNBRHmxuzX(gut2Zn}
zWtuw37nSMiElQwWP(S$@urI2gEd}T$HH$v8lc8SA2FX;vd=yq>sTco&QO{QAQ}pq&
z`aeDN=BQ=#Rh3-zwtIlibEx^@F#n2raRD0h)ln&^El|Hj4uwMX3ybkU6scL?1Fcv+
zoBWU^>fqfVSJgXdEK1c6{UBbZ{@^t9R;qucbJ#VtLkfje>X)ma{<?bEQxLCKcTz&d
z4Rt78TCP=FkD(KFYDfA!)ZS7jr=!@R{>u|qbgG~E73#axMU>8UU;R2QXAjg(=P(G}
z>Y7x5_Na6JLS?V|E}gpj)LYn4(XY0U*#qi5l(sXd-a+%+L-o%`py83)GZLIb>Lu4<
z{jgd<)9Z+Ok%RI&9;*w#0`{o-!DaMmO#Lq{1mo&4y7;$S^X?wN?9sd#550Rep9Dj2
zpC&30mCl+Io*?@*1N51?1DZhtSX?x-C=B4L`Iy{nZW_Zfl-xDt#W2l7bN4O;JT<ls
zaC&KGyg}35L5(kwLmCzNq7G}W(+lLSsiZU*A5AMwP)9V6M1b+t1Z@VVpJqC(ApV+i
zdT|0Yx9ASYQO(N~un5$A^8{2J(<JktB1rR%5GcW#+QTS?XuPsfI<D#QfZPd9vxN4a
zp_-k1fS%O+K%2ZU&AqEAg=;>hgKmT-kd0xB)Lf(&C`#i@t6H??OL7*(XpD4{Ii;D=
z3B9qJ-l@Pot$FTAh{tI<X`ddiX(LZff@c2DKslo^Q!dU~jXRwi6E%5H)BZC_^V2M#
zozt|XfG1h=+Im=;qM4v0W~%1D^*}qXky2bKO>_TKXiC>Sdj;4RG!KG7E^2C>q4$y|
zi`K6Ujba_dGc_rPA&{ln8UcZ9&5FZ7xvZI>IWR}_*PkG{nlU<YIr21H=|bBT&Dmq<
zVZLVNa{w*SJVi5kp=Jf8_ZDeV>VRFWx%M(7N;L0K%=fD1TN>_C%^C7`S7>%3DlolL
zvoZ;#Yns360am5i_yh#5YZlN<T&-zZ2`g@B*px|FqnUdM-M#71JmCSsTFw3cprTIm
zEydVxX^tnNvR>0bo3#c_FBju{ThmDC_05_q!)UvsDWa%pize&^ptWjtQ>5^&W)2<G
z+cZ7or0>w|q!frwjeIS{yEJcl!isK<GaW5^G|uGc>D4%VIcOZveD9COL5+g$YdqBO
zY3_ccadg1oA<d<guyj~+aXv~Tn)JN@eXJR{2h&D1uO<OzOtYGjP{%dR^I+P9=Dkx8
znA9ws4Y1u>Z~AD#9_`AtFm11vOa6p?+KuN>>8$<T@iTrd7wvcpuwAuF(je%jolAQd
zPwkOjSmC8jN4#_TL9O=|$RE<0DYM|P_OAp8cxy+RpwLHqHy4_YXti|O@YT*-1Y`WP
zp9mrDul=P08UnQI$rXK6Yg>x8K<)N=U>?&(H<AA(NW1PG7!|C&H3aMsZF>nSL$%Af
zP;pYrpgA;5yGe(RMry6}<VR_l(?O!OCugB8MjQDzOgp7r^9)L{+62mMJ+1v>CIsTN
z?ks4E*Y@o}mlCu;K0w<Ut(yD^XSEeh6n{w6uAxmtlGb_?tmm{J(Oi_Q-Ahw{iuQZ*
z;-+eYqG4gWR#uF*3)<f{p}!ZkS8#xvo}&%>5napGc9EALPa8#vc~`XWKZDAA?Fx!#
z6=*-Gf?T0ip@vOG+6^B<u2}o{Q(FH@v?nQMbyXYHi^fuIts6+0wp9UAu1((yO%>YX
zpFn-3wloFU*R+3ygH&l_D8=lCHg_smYP47CfpSy(Ocp9@wXcjqyiU8E9-Uj-x5#N-
zubuWBY--ScxCL#uwX2U{EF8_+Lp7jxv|k2c5L&d^d%@bOjixQsU9FCO$~NtsN=V$(
z&J9LoySCsIN*!AL3~=7pdei-|2igxg=xDdri9!@T+DGKV?$sI>L!eK~;i9r%tI@->
z0j<6g`UbTt>0mJA&|dIB?XcFe3S>m9r@8F0Hiq(%N40;`n?9!PNrU{jb{(bLO=#Qy
zh2BZ+M-)EXt81V&Zl7)+Wv@ExuC`+kTy(n)XmiyqcnX|uI(7*Zdg^`|g`r-$JrtQd
zs5>G?$y?{pJEQ2Mn@66pBf5Q=Fv?#SF$0YOx~J%qD@Sz)0wEuy+jS15V4drWFfBy)
z!2u|Y&{^dWh}0Ffp%kS%nub!euJ#|W#OMOgz}{23*j|9e>H^HL>9p=CO3RPaMP{Kg
zUMFzSK{r8Huo~*m=>C2KJZE*Ee*vCE-ODG?`y}1pJy3s6cfJ7XlXY9kVUwae`~~Dv
zbvin;oY&o>OZaKJy;)G7uInZz#|53A6ap7@uWEpKNw?w+lrnUUZ$ltcH|h#|vvhB}
zQ6fjSu8+bAmvuKnU~sPP>nN1+bn{0baYffczVCdU;Ca|opeu0)TA^;l4V6W@Umild
zSm*XOM!iJ0Z9h73Rp%Z8&Qje`SBRJCw!R6|%60W`qq0JmLEgbi-G6L|U(<bPqW7;#
zH<<{S>$=MSpuR>IPz{)yIw|?dY5@v^>vffMb*(}7m=cq2>v$SeHtWvO*7}ZaVgPL|
zy8ERlwd$Vx45hoeXm6mj>9&$TzC%~H3Zzr_4;|CHbm8Pd=+^xWkH2GjkM0+`E6}Su
zq(@_)Zu}^0>(@;zhWvnTQ79@O={^mC#E_1+7-U$NL4M3posG7!V>*we;2hVrOu)3=
z`T-+Kd-R1&wC&Yz&qJ5?>x-X8<pKSwHGp=}>nR%Us{fcKO^2J_H3B^D`U8hSy!9VG
zLZgqKOMagtdR-}aeD$G}p6I7fq{rG{Urqbo0R5qNFu+IkR?1fm)Gr<c=P~^q@&p9w
z-<*rV3)YuJqZFcVbA>U-^$Wg$+zI`j*U%QK|Bnk}PCE3%9-v|R<JrIt*LzTgPlSFc
zIfEkg#YT`Qz42?Ph}LJ+p)E$wCGX-XefgVci`74O2v(fdKYbgT;`DwqU}(HPZw53a
z=#w%~c}D-`d_bSoe^2?|iTeA`LM}<4U_#qDz2j?N6qEHvdOTC~OXtCuRQ)*RKAqS9
zb{S}C`r*SsOGjs5#Ra`880s(TYtm48Nx!BP;u-qi$WfcAfAj)avh<gxp_Hv>kYD_=
z-poX0jy{iimaF&Lfl{7+$c)kzy_<uk%Y6M8ZYUP$zok7$p}v{|rA2yXJ}Qg#t0@Pf
zL_h5Z{4iJbZwA2bQvDYcTrbnR_`!;D{VduUROnwlf>M?K5XD=r>r=@qQmtP=Z~9IB
zIv-Tl>bo|B)agU-!0ZM+^L;x1-PULP3&BSHhzzxN^haL+T8sXe6?$9s_sEfdPyc{^
zk#>C)MI$=&T@;k>)W`XPrAwbcvFiK!40^X8=o8-pOSgUzx!HR3rzjfVtDhbNls^6F
z%lIk!^=>agZcsn7n=Z0F)Jy$<_DDaKzRWSCPgw`~Vf~&ZP&lH`phV)w`bJ9f7}c+P
z6>Ves?Z2XOT)*}=SU;gx(C;&;KlB0myW8+%D%$oK7WATWuc4a_P5TUwazLC7-&Mhi
z{e~?E(RRR~M_Qv}x{Ki!or_!zi~1n%X5dR;jJrX`2eyad23^kcH2f!qdM`r{Io%E#
zl0-1=kfA9Qa)%9dzk<`-a5fZ`K8Ea1Q95FHa~TAD4Rc;WrJtd&5hZ`aLUM`*7;aJ^
z?5JT%9E@=U8a6)#o@0joB``6_Fzq7L2OCyWhCztog9=!B+~7}FxlR}==xq))_)%E<
zq=D;<wlKr!R)B^ZTqw;i!thNEup<qBtp|3LfpHNe+AvI}#TahWJax+8Mqb5O!zx<!
zPdf}hnJ}brhBF$Fc*7gTz)monpqb)~Vap_pIcqR>L4BgZPRVdd2JvQ~oin`fB(ReW
zO7iZf7<Tx>m{h|hazvarjNQT@q#0`IbF}G(+zo)fV5p(A{ELP+=~Q*eaQ+RHG7OHj
z6j{wQtfcEPS%x2IQ=4rVn+k=O4ZnE-G{^A9B2?xYkj;fR$I$;S^j<OCn+BMC!xcT$
z7Z|+Bvs`E>rh`n8!TufuiVc2rPA)O9$=83?aEj)lQbP`{W@UzNDBw_TaCN*2P1g)j
zbnm{(;I<N_>xL)D(OYfk?t=Uc!);oJY7Cz5LE%lq8k+iR4OPzot<Dg%5pA~&Dh~`v
zy<uG_ENn2Gp`?l1hGnxM&}i^I51X0{FVcmfX2Z!Zq4$pA&K<P17&eM2{?KZO^h4ua
zLk%szZHCh>XuM}oDo|=SEc+W09fpS#+vqfWy%8$93~%j%+<n9HFlc&Ucy}#Wx(((Z
zz|v#*_6NxI8kSKUpwF<Hh01<IO%wVuU|8!0&OyUQn(ZDM9Iw!aOdc8L9t6*j!Tnh@
z4jT$z02wjJ8X^DK5d9}uM-7v-Sd1A&bjNPokVhYcoiH@eZKO%VI>O#<d|QahJ;vls
z7$9e(l|m}}jm<Jt9x!gE%pezIz`Lk)HJ&DYZpL^aB{I4jl^?=j4`asD;PEu>4+ff-
zv7X-MgGR$@pdB)L-b3YK<8pHCdK;g79hE-D7ZtGZh;fKKM83w{KQPXI#=oy(@cfN`
zQ8+xnIGYESqsCoJ(WO9R^;ghv%(!z5r66MlCHp#pjU{7{4>2m}3#Z48XRVMpVRSwX
z6`@8q^8BAPen%-=Va6Vk4>unC0;WY6y(l6ZX{>z}ZBfSL9{hyS#<%JFJTXS;SExK?
zY^?@otnrI)Va#dcD1B=o&iH%?<l>FXXeLc?7*%xUIb*E;0oI%~Zb}BvIpY9r<dTiA
z>7g*im~;oFRAU_3ecm{_7Z#=&BjN#*ZmfR}0vC*xvr)QeeB~d2T{60EfIx<E{RDcJ
zX&k4s(q-ds^or#e=h1bZT;p5ha?dw9o}#SG0wXsCJcUMYN_Q_Y9;SS*tH!w>!NgMI
z^eKR;Ft(5rtJ1ifrtoXVuvbCqjPKCpk6Xq|G`-gwZ=M5KgE5}&m)tgfNS=>I<LR~Z
z0vO9F6TaE#{vAqpj2>!;w;1(~M)0&6dno37*I2RwJZ;7$29SG3-%Rkd8_VgQWQXy6
zI&gLxXXK%+%c!S&)%T72DKGee@ghY}x{WRrwCyn(`k}tpm_>o1KI0}z?&>!dQDW?X
zF_b)7gT@CGta@l%)9OI&BjYqRV1|q?w8b4Yvgkn^Gfw7!XWUpLg~1cX6{)D4G!CUe
zV7F-*<pk_8oytYqUQ<W_Y&u|CO3RUp>B@VMb2X*V2hZG0ZM5XLo37J5<6+u41?oLb
zYC7<Fnf~2CiNuFY8^1*3VbemoaPMuhW#jktF|lI-bHsF!4|!ixFD(mxrZpkZ<Zo)o
z151D@|4p<VHU02C$T8D8%2W$7^`C}?!6p%1NenUNQEKUN(~)KjP^igFj);?{d33r7
zGkt&)rek`9sUsF$i!}98+%n3fp~Wr6w1bX;r%X=!F*32HDoR;7ZHhVyy>TZ04wTNA
z8keGU)}$gYY@&%n(`1q<pTe}~O#dpul57&utCC_8;L6<eR8xKjIM17$dQiGxy48pd
zIxd>#(w9UonNH0EYlbOyEl8&6msnJ0nI^QbBHQ%vL-gXZX*-=;b4;I+Up?1k_!(_^
zCjWMH?TSgqgh0OODy{bgrUzf3t<cod0)Zk^DMi(aP1DK!Q(}7V6M&VO%ww>k++mtd
zDGe2-hm_b<X;PUXf6a7N3Hd6MguHy$O;27#Wwpsm2l*SOFDW;)#<ac`<fducCUDl8
zV$P%OmdUUbrq!F~WPvo8-rosw+q8BTP#R6o#(|~Dq-jB^+4PJMZFfwLS&cBi#q_cZ
zOl&o6ltR;8)6adVY%^KX!E?{_cO(ScO>eyo(qVf2PgHiA+UU64Win9a$$e8_2-+T)
zzNY<2x9PXTu&Kwip8V<kru8)-1EzS&@*On2=nM5jrYJhJ51TGJYS4=j6MqTFW79Uu
zL>x7(qUUPNWRXK~(lks9&~EcrtI@W{j682_sLWj(Q0Z)57>dE$Z=Oa@(F0~PJy$N~
zG$u-}=3Y7=yP4l=1B$!((eDuOFh|l_;c4DXn?o<N;b~g`4x2BMchcK@l5)v?%xf7S
zN6c4;V1=(amt1&$=1?18{LN!uLScaU8a;DI&91a<4m4-bWOB?ru@VA7=APYP2{zxY
z!&rov7afGc<L3W(5I<p_I)Y&iH9t8E0w>Mh?ezYIncrojPvPdMRUpyk5lUH!F}G2E
z;wf`;KTL}?w|YR~Y4a2LkdHIJMlPOsb80>+6U?)gL+*^Z)gR=n`FsLc63qp<kV`VN
zngDjrJk1>nlg-t&ASvdf<eNz~&qqYoG5x$*_#S$ZX5KLq^6BR76qdVS4%rPA7tPCP
zdv(eDw<pFc!|X*ni%fImQDA48|D6kxZN8lhg_q6eMd*Ewx#3xKG}r7-2bnzcR}{**
zVjiQDM85em%2+8dU!q+@q50?s(B~*Jvk+97UTprO2BgGn5`gupc{^=TO3iMWP*G+M
z_5@nF`C<l0h4~{|+AGbSG^boM&!^9SR+;~ydHK58pXQrt^MRLO%nkE1Md)aadFf@8
zZkij(J6~(Ie~D6^`4ky?%VEAxVd8po6YXXj%xlR%ciTLt8I_G@t20zInZIcUOtaaO
zvX<_c=ZvGW#az~k$~N<uH{|Y_H_t;`yV*)<T^;60`c6)#S@#;+y3C9#z`SqvUxNNV
zFsD&4quU%<gMRjy9q<1DO}%D~9ewIEXVML}esd-zfDM?RUW&>=^Ii&c4w-K)1n02%
zm3Fj^n75Ei>aqC}sUJ0~>1aA;zE4RP<K_dDxH4hBv>cq1=7Y0g({9T>`jz)sazDoa
z?X`TG0G550`3^S}oh_c}5OlH3Uxr#&i|YwUxLHKhUw6yJLr~#i2^WFI)AAY*R(M%v
zQ1IxW<-}T)4q3)$1Ld$KLJXU{EsN(slaJ*TJ-J6LD_;VNuf>m?i++|o@&Ni<{(Tx6
z0xW3;2Uw3<R#c%e(318xB#v2LCT~HIMf5xr23rDNfr=2zzqIE%ZrM2-XeTXQ^fj0;
ziyKX);g*Gj7GVi51xuu*w+q7+Wr;ch3!^RbX!jjsIZyB3Da(yl!4hl9ON97o%a2m>
zzr<NAG>gPr+$d_BV3CuX;H+gA9gh+%20B|NS>D?LL(f@a45&=D{OSXN6pMW~+EOi-
zu7jMn{PG(>(=1Ov36ylp4_9E*1<L^z6lPc+(s4P{QdEJ;EQ^^2J;$<FM*GiPixc^>
z@+=BHI(o(8-3}G`mL<zkDzKdY|GvnQ83>jl%XcyiP_gCtd}u1Mv{5AMs)a$mj#A6a
zR{>gPd6^E+<(5VCTvS*Vo`OK7Wg%TJyJlI>g!(Fr`+7iMx2Ru0o1@y|MtQb3EQd}4
zt;X^^-6pzed5ON5TWguV1jANmiC+p8w=9ew(V2Qn$BV#juoTh`?zW|UBkXOo3{$|d
z$<jr6T+NmSat+<Fyh6L@7K^3@ZLOC0{UCQOAMb|xdzN!N$hA8xMXtc^u*A~p(rNjV
zR?{xaD!KxC-*TP8{|_vsWvJ}7c!^<tk7dmcRQ6gvn-94@%h#{K-hRs><kC(bu*?vG
z3|ihH^3ZbL2rC|0*7MMpA<N1nU=CY+$50xvJV(dQ#}-HNO~8y=I{N@RW_g9YSL2o?
z0njvI`R*F9CoO40Si0MK)*F?3tdr#U+-serUu2)vmsVkC>t)*Y@3;Qkhaov&{o)OD
z)Wy2m2`sMGo>XAESv^Bha<?YD02U8xZ5xQE)yYA-QZFly92p0#*DitQkkvsC)M4wp
z6sYmGdex!L$J)b!`Xkn#DFEkd-5&!`KWm9MI_huD`wx`?*5A%R;HY(d6|e)XM|{!y
zW7gISC<R$}g`zLP*1Efp3$gw{xn;+#bJo-Qcfz`VKUhPp(KKJ3v<5oE{4ncoKVXMj
zf8c>7!us+~kVtDJJ>5~(?iO%HTODCAEyj9#GeA#Sx6!A!Vy&y_Cp>LEas!od*01UF
z^YPaCYay3leai-N#`^4IfStAOccb%PqIGdF1~JLnz737%tojjPCtJ_bF6+EiPm6h)
zb=xqo)2$<sz`kHzPp+kl*47RPT(Ww-jLu|OpQXXiw3hTiAj=w0$C_+wBl!g`TibWT
zm>lc-t5C|dE~lMlo^>>sKBRud+8hPeeCxMCkT0;_T><Pu>jr0(imY{%#$9Yx(}#^q
ztp9!jo32`S27;7YEp#R=v-XoSx7=DV4JZ}XUtU97rPYIet!vg7@}RKFI^u%1>sBvX
zN2;wCDEZ-r^%y00Icls2N}=$kRhNLqTI)`FaqFx#Vd&^BYtRTP>#gqwpwwVZBhSfg
z>&)9Ajn<ViSlDDuqi{mAwVTfOcdT{Zu&Kq`$pB`nwexS3?pnW0085)yO9z8{Ru^})
zwOg0{f2nd<-wFdyr!_bQJYCj@{{iN{H6|UU2iEI;(9~`9{t1KMW1U|PgL|$1Q!v1N
z)?L@2zTcWX8>IoOf_AZk)~arRJ+$iSPQ@eZvM!(uS%2c8OT*S3^T9G=eMl)xkFBPA
zFlN;1Nb7*anDs|;^p0CU`3Nc|tY5o;b<+AidBS(wK8S%8du$64^qRicw&riN?X!JO
zTLNd>JG6~;v0XV27FSyaO`2}D!#ddOZfkId6&|+VSg_F3wqrgj580kR1o6YR)ihgr
z+q@kc(CBNsvIR!@*%o~OP=8zEbyNn}I_RRuQCkNcS^{leKcVfIP4E&r6J&G$5XJ=C
zS{H(Z*nS=Y=W*Ky|AFO%t%;Ig!))JBz(3q}*A*-gwyew05NX>Sg;JF5hg297ZA)_^
z|7Wc2F>QEH+sfYoOq^}(3pAdwt?5MNS(~U8r9@lNc3>ylW|R9U#kS==przU@@nAV`
z>o|mQO0z8{e{Z@?@dzvzY=<ZSaM5;?(y}huPLWq5!}cOw_{+4Z1sH@Z+Y_JD{xiq6
zjhtAywzrGX(LCFuw;)kq>-iO=(01nrNRcf)5N##4DYXE-YKwM(-cp-O3lx^wM(DC<
zxvhkbffcqQnszE}uk1$YnoUC|#VXq&Ge+&Y?R6<Ct8K54`=-X$zG)`jzniv!72v70
zU82RU&W5`yc=Bx*$Zu3{n?Vtl23y%DDBZSw4vFcFwuhgghfOv+`M_FitJgt&t1Yq|
zJ-loCED{#B**4M>c+d7cU7%~X{UilTr_Gr*7G1XLWQgClm3@aUIUd;JpM%0~8_$f|
z9$S+SZ0oh{_P~(z*;f0Z)NlKfo~r>{aW#w?v`vXZ>7mVkJ6ImshR9JgWLviorD5BY
z6o5Up9i>zAsO{Mf*gIxRquFxYRzbJSCT!e!Fm2NI+BOL6cGyGSfl+(x4$9u!Yd`c4
z<oDT)ejv{F_b8WdzddOdSPs}tv>3bCzo5f|t6dX=K6%*hT!ng1yNxaYdD*xA-%n*f
zPn$|_`(z;W`q(d>hTIYR=agvUYo9oUlAqo0H<XUr9bJ@E6KMb1g5oiI0=X`N>~kK$
zwqW~;7|4g%m%M|KIc}e_7c3|2ZWI#<wfDq9?@4<t<+y~|pZ<UJ#4h;;rbXBnJc+(U
z+BZf)JjyPA3SiOp8<b8NW8WNxwo~?y6oAFq#SV&m$J@DQFwO~f#SV}&_9zWN&)R*T
z2T8Oy-UmsxtH|w?V&6z!kyQKNbgdxWUPH^^1-sLI7<17+HV+Cf*}tS@xD5L$F;ryQ
zFVm8fWsi6t;@S2x6TmLpzo)<1$gwXxM)CJt`zk*a^X$LPf&3NwJO||S?F(tnFR-_E
zL1CeN%6zCOvi}+c`C|Jtik_C()5+&>)jnq%uuJV%3;-*$cWee&xqZq~fK}K}wu7_M
z-bv@7Yxc#oPp`6v(~<UuJ^FKsKh)UQ44^YN?XBbluC?#~6Y_QTEKjiBvM2eVhxK;#
zN04Z+ZzX@zZF}SIKx?$GrQvR}cb5E*r7wYx@%r93?_`q9WSL~%Wo9zT&{k1Jt0>h{
zEv?$CEiJXR6xEhy7NjkcecvP!kwr*?gphrg6<I7vBqSjsVo!pIAPDh)&iD8Ke0&`D
z-t#=?+&k}b@44r`P}$)eU_|8&=ku+=-E^KnJHfY{L+R+vZRhRuEV<)s^C>j%IxnHb
z&3n#wtLZ;7=ybMdKrgzSO*ZIuw{vwbx_#gIV+-IPICoKA#zW_s*#P!9&!gm&N6y=6
z^XRd2t_*E`&Z<^uK5_nU9$20_@1z9vXU?l>q1x|kPMJ2(od+fX@WS~+y2S>Z<y#?M
zIlIz4(Dd5*Qwtylomtv%dE?wiTW7Ai$Dg6nO_z)1zQjZKhQeK*I=f=DdFfhx;Dxtt
zX*h(BP8be0f8FRkC<W;DZ-r){?pK=f1?jpdX+Bt&y&8iMqI>!h219k0l>fO)7dRVj
zVJ6)#6ebVX<^6}+-MVe`xzz~WoJ^2L>T;dXwLQAWw1$Y%rP8sHy}BSeIv1@QxPZ18
z-5QEa#p)K<!qGULWGa4<eYy*U5b?VEQSfQMuFeZS9nhWp1)K>wvv&Yb)O|$(mn5A@
zL;>}KI`ewCcu1F(51PZehFpkbUG^L3r05dghlwM)sA70{OxH`Bx5ss}+`*lu3pGP2
zUAHbCr3~G74p7O|9iWV}9NlTUa&vY3|Ds;HihQ)?>uxy1e1Xn~(gX{2<|aB(U8GB)
zsoM$N4_~6TSm#Yo`4U}$8$_wDd>tywbWy4ButGPN;u$A(aTNAFrK>K0qo;M>QPM=E
zZmc&nt8}^)h-zKNhcI8G+iL-FR@Y7mdgpYDPeAj$&Vk}owYqnIq4{T>&W#RC)$0~h
zXD;a0mZP#kSNk?}8g-8-VslZa`w^u}I)`xdqDl8rCwkGW3!r_37F}aC#_6(7`ZdPs
zif%h4fVJu-Q<l|Lom&Ms+jLjyHoB&pd>^=W-Ln_y?sZ*q7UiFH=$=z*&<)+>O|W!R
zXORi~9bIiUbnfab{eZZqOCJliE?wV8D0S<~8MNKk`TPa*4|G4#qT!)#Ssrjbx;Kkq
z@R4pSoet>LZAk;?W8LW)Q0dc|=%nBi-NqjPf2tcW4Z;2QOgD?t=br1v^aJriceVy2
z`%-6OpgN%2Li3wfy14038Pw%bN8jkqd;x!5^@lTH-c6sk6t21Jed3_$sh@BQa4-G)
zG*R}}FQ+%2kNzUfeSGx~R-xplpC1ZMf4u|EiA@3e<rGW`)O*my8l-oj5en9CqeoJR
zKAskEq54r@qHUM{7rJA^^pa1Z60Ucme1qNk1$3}1LccE@B2r&i1D~SxZuG5_7=73-
zh**97ZVW=4{u_U&?9;b=1$exEYB}KhP5RiGAU&WDjYeaF-fja7ChEsjpic+&WprH}
z(hvI=s)zOEr{G1h-i8*ODSC$Pkt6ykN6~gvZ$sz*QuVDPKz2<3L<0D6{TtfEOxIgb
z%ppS`l>m{cpFb31n5ADl5t`Y0)2mOxmZMKPfW};X2OYM_)341!DPO;glBNpuhbg{R
zs8{_9XNvVf)1XqK|EC6`RR5$B=F9Z&&;?blub?Ay75Z0{i+57rtpog&-ie;)r}fWi
z{#dE^{SJ1k^h>v35UTYPOjA*;(bsPR_Zj`lML?X@ODNy&oPGk$ozCn3YDcM7fA~4t
z>hyY=Ak^!}(vtduzLi!v4SL&4fH&%oZ-nMW{mnVxzNF8k*I1MOH(D(;>p!Ht?-qRs
zP0KFpC)4iq75(aQCV1Maj~fTltNH-SP;b-ErAzm^e(Vmkb?EQ!0L=}33$4#@>Raw$
z)Nko~o}%rxzV%1+_l`cCqNsQEGp0lHo<1oP@J_vz7Mfl91e%0*>v_67?(0uYg?ON6
zD75oXuf0m=|9bRslzj9^ujU|n^%q1CkM*{+UDT(y3If{`{rq?UpXx(8K>AES%?1Yh
zaXq5)x&8<(7+>fan$*73=TOXjKrf-C%PalW8mPS1Po+(TL48^hD&Ob}#h`XI_~Vt1
z|47*|SqX%@p=&f~JPiLV0k@~2jK<5$P#lU%Z-YNYTKx>OXgkl}@FTsI0u0;=R0bLv
zD8DJlkVBVju)*mi{0%Wko}&|?hHZH$?J^+ZiyOzl(%drKaPT!O>^2<1@e7G5!tf7m
zokbdE(Cc@PVasrgSCrwq1*qI>c>W(mv|-`9uoPoBvlgQsYZy=G+Tsj;U!iiJVNW$m
z@rG@G0=M7rGtEX180sh%m0;LchEk%zjWREj41JXti-QKv0;NL+XY%5($)KUUj$}g^
zJ+xB{dKb_fGyJp#rQ?R)9iT}w#L&7V-S9naCuA6=j7LW^4MHva%`!~o(5Gy}<X&*+
z7&==}$}^a6gNb~@xpv?R4A;Jeg+fE;1XLCoV!A+m!myd1q{Rl)_>nMJVqnN%sX<43
zlVt{P3eJ=p)=-v5g(1TYDklxvuVLbpp=LJPstk$?sH`?b)uU8n=$H$;=L`$!Ryl8Y
zi)N~|hJbPK_kv-t43-)Ua{9Vgqv0P9SZFe+Dc09)*l8m3ErtUzKwLI_dkNx-p`;c)
zY&BFpfKIz%Ih{keZm^;(sSd;Re25!{-zc_v)39+JO1BJhn*853B+!)ajzM!12JadS
z+ac~5nkfsl)3Ap&R=W%jMna|AaH$Xjd*2Y+Mfd0f!|L-84-MVhVX4R9MU#j}hT)T8
zqSvsW@|zwTB56X^XLv+kTzO(Bnh&<8hGcKxo*9xT{L^pnr8V?(!>?rUh2icH{Jt*@
zpCv*J7?MY#@|9uKb+EiP6jh>f(C}b3#b4eSPJWG|t1*x^3EYeY6f<-;vK)kmaUX|D
zPvf^q!21|w;V|fHJo5w0`x&iPqZj_h8rlU3Fb@3y+=0eTZ!o|?#;<5Bf{n3Vs0=aw
z_Y7pAMt6!j?=tS13tX7-;%oYlWw`Mey%l#GEB!zkVZ1`Kj!5INCBW}7&ZcC#C}RlC
z`u7^2(1J7C_z@+(#29C8fl91##Vi<%GqOc!+h@Ev10vq&>H)j^jixrJ957xx4VDDs
zf)ZFrG|Cr3BpFvcf+5pE<3ta5bI6!=0lheEeC-7M5#uk*(RkFT;X#vX9A*Z@F(bDF
zrQ^nay4KT-vuIZ?!+6^n<};0Fv|!0HUOI!mWE<@cK_$mHy$W{ojoU3C3XEa2#a?LC
zUI(Dac)%8=6DH%7<sdCKrZl6r#Hh1GsnlrS5AHH!+748nG9I8^*VD%Lc7nUo_;n4~
zs*Jm7W?pUlumOM?W4agE&KO5g+Q3<(R0C(u89md{iSx!K$a9d?89V1d)EkxksJvkO
zeF?}KjHdfEt!p%fzXOLa8O<n%zR9?~8Kq|9(rsXCF;1W>;j;0NA4*q@BOYS#Ta9DZ
zL9@;H&wRkI8AY^iY&Q;3p>*B2m~N^L<AllZ@P=_T?d0Axn%Bdp+s67h4D%hMmk8pn
z@f{OodE7JZq%SaZ8jn~4*k!b)5N)?{T{#TCz!wxy`P%s1F{r#T4*d<ned}H)aC>dl
zJ_Ou%>#d&w2-s>vkM7{DjXy$V|JHSvF(gN~&JTk~-|9vIs_d<u6;R3Fdhv7kRJ3*e
z23lB@Y#n_9eJbBtOC3GE)nywh&u$fbLDRZ*$ttvUZcX@KfO+drPG}q0y0;oWd2CCe
zHL1_G?P+i{WZU)Au(WsEc#8QQ*w!uqJZ0OX{U~K@n=gj>qHSV2OLc17StZO@Z!4Tg
z^UwNim+4sDrEPb9gHFiyc^pi{Y;W6x5lY-XW;(btw)bsDW$yM(x6$pA?Gsjjrh5DK
zI<(bqe~(raSGMo}4=T5||3rx(_qMYtxYoOU?G||Pd^<M@xL4b6O5u#VOCF`9`@6*Y
zQ~Wc?#YB(NFqcTmS&ne|LQLjeQapiAa@kAkuw<72D_BZ(DeHu0n#*JWC7CYgJ)oK6
z@;N<ka$Op41CZz9#iA|W<%eUy6}wE!A%9(p?!l)rmmlr}UhXo-2W=HDD{nxUPP*uR
zLq|`!Or})a(=I<bKvcS{x<w=8a*q~iH7;i#0(jO%OY@9#E@Qq#<$0I=diYf9(q#)1
zbuJBb!(VVY(hn~hT*M>M*65N>VU&w5pRR?6O)iUupt9M;NUyOLmv>&FblK$cCk171
zxWv%w?6ynUUUNY3=cEYh2XKgD55T=kqPG&^P_yW5y3#I-HoAeaRkUOzKy9L>0#w>X
zLlh`=h)&Y!=G&r8N>n}+S!JO={h}50PH<(8K7{aN&TI!u7{eUKhZO&3O$h%4-n<i#
zhT`xx9ZbFZAQ$}_v6!ZrBj2W_{U=jstu|FP9<87LI}z-kZTtg&PaEQf*6DS$t@-(e
zg&3(B?z6%6#q`%;_;S$$)XbdQ3GA%Jl-~W-nx9es^)3$B*`^^Y0siKbYfzelr}GfW
z+(3Fh&HI2R3-dk0FgOduk5IF46-{*)Repy0Z|jDlSBv$u5csZ(M(+E%V(9#^i-Jo_
z`bL0rspoQV{`f6rApUf&7xl|V3_;EE>)+ttKdTQze}&$32PRi0Q!4$c$rP(!UEqV7
zH5n&h=GTk#^j|yfFh*<LT_pg&T@OO*`rg-YWyAQP`1i&>iWUEN;wb+15?$y4z+3b+
zeQm-=lt`DPuPB<*S^Y$JieT4Y^n~7I0iw*&pa>M1<~_$?1c}}|0-ar=sAvGMi#+n-
zNsp+05h@>v^z{6EDO!h1Loy(GV@;Nr(PJRInaBw+;lm7}L>ymc{$`l)V@4U^sz3AA
zGq40OTPa=_$UIg<Gl*$!fW25|D=lK;7_sR%<YC5X14J_O?FX=w!l>ybaD<6p1h%8h
z%^diY%Iu*y#WAKf72L;}jT9(IW2%ColFnpb2X_W@bqwH{OwMqWvY0bBU^kly9)(ga
z(@G(yJSK<IfAg8q8j$6PD~HqkBUe0^5^D0qZFDFtUo3tGX9~oZx=>jt&iWUsMPe6P
zM4b@-M!P!2VkKp#mWXB9Fi|R2>%mec{(u4n<>Fl;;3~vlJA&n;IORJ4PKp2c0^+pT
zH4uHN6mNbHDplgQkJ9|3TKvP`DAtH4P5|2(adskrXT=sX;rBVQpA$&Wi{ER7!CG-O
zEivlEKNZ8#da=(ExOPEY{T%=e;-$j?XcX7d0{EghI|i06iFcoe-6rw)Z(*TXe3lNe
zwTR70^RoE<DT+T|5x+-);8t;r7gVo`E9tuyZQ`MGVd9$j1G@j(#px25zb<}6IaM9v
zalydf5NFXzz?<TaWDvK+hg-pNTYQh!&v(Q(nozncer5@S_rzmqLDwmMIRTtq;%R|^
zcZ&zsf!cIm{L4BtJ`gXT3E)HVM-PDL5uc%Sl}F-{lxyBA{_A}V!ejBDY79`HIP))5
zJ`w*M1V^8W<0+fznfNG0RQkn%v{&+6JY^raUx))<z~D>qi!xLWh|?Uv;%XNC3;N<_
zCZ{=Py2-4cj&o(0{cHqjrrF<#C}o+2eGEjl*}~hP$uZk}6*ReKHGQbeGuwC^cJs~5
z=x(huo4gNf^=8wXfxBR~;0!by%tZ9{ldEP2mFQWUS<*RZ-ZuLz9O91IJ|2KhvvT@f
zyUa{6BLMV~L{X5+SF-c~obr>@Qyx*EM7aVZ8zd>G?ABn(wQX=FMDi!yaq*J>mI6>9
z>7+$ap=9oLh$6`)x_wVb>dpXOERj(zNQq?aPq0ubnUV!jCfRTbu9Zs)n@~C_xo;W`
z7f(sjJy3gEQj`KqmH0nifv=MM-HNtq$<{}(TO--D40g{*zM^pbHS<jBcDwm>IwyDC
z+z^jahq?WGfZs4*L@%G4=I_#Q-!lLBCIGk1uYE+nmihYU@bH=Wa|znsnD5*{&wp17
zr$XS}EF7ERg}a5GwzdK+DyUC^79F9e46^uu91XT8r)gWLMfLx-hAsLjhb+wEQ^cbr
zyDjQ&fF;5rjNZqQ7I&IZ+GDYeG9zOw=KT#3YZ26e$~cP!9uSEZo#p@gkfB8eJ?nEU
zesYG$wdkWP#yksgAq}v_f;5;fviO-2x=&bGPK9g57OgYjc8Nv(QkXBbaB)Pb%Hr7r
zh-wQt-3~PtPkjM6V=?7ZRGzi?yBjR$E!J%Zyw)Oe9(vzwQKF#ubBl#N<!xNHFh38c
zu2?u0!TeQ=gR_8dvuLAf@imJNR)VJ8V##iBcUVMHi28<w*Kt(dve-O@E-#BI^n|%<
zQIHP6J&TC5P(jd}X8iXpKAr>32NwO_fIqYt=KwF<Ek9ia?@dvbZgk>gucdh-YNIWW
zgu{G{<vhg3C9#%6>2VonnHLY5eU|ZGqAlLC{0=ntTWYpJCDGD~Hpr4Jt0?K^pydjR
z#UHX1nZb)>%aKNi6w9Zhz;eX${C%(-wVX_6fKn|D^TCp1vP>HfH*zgUehcn=%b6$O
zOo3&82}lbqOX+M%k>ww>X;^IOMK9nI%kNXrR%$u*Pmq>bZq;C%$}Nw$pz@^U<|dGx
zvb;%KVy7)R1IQ{Z*VFcGwPh1M!)h!m`oMC=@<TdSf6mghf$~bvTgFl3x7L#1fKsPr
zF)j1DEE`Xwbl+0B4}L$ed`to4hn7QW|F*~S&R@XyTKb&@?y=>h^U!=^*+nz6r<O_z
zAPrjfQ$X~M<)3E&ca;W9q3I^wQVeI@r9V^b(nGq~qyUYlRP`Tx^OD}11BAEKw;zo@
z())`6^p!RaLk~lx$0(bAm$bA8+~Lwm*MZwDUB3(>Qd;Q>+#cz;*}$bqU(u>5U238?
zUZ%8?*5+B#*FS<RTUzOjQjT=yb%<Q){rBnpmnZ#~k}C40rdAA1fppbrs1{0>^#ETa
zmC)P&g!DlfM6py)XF^M)m9)Ysm45pt;APTS5e$|~Kc-oIh4kYS^ixP%X(4$^nn8=U
z)6#;;psti2h(%kKbS=edtECO!(fhAPTCx_ZXQX{Ap?X$2Z63rqX&Yq;)Ji|R3}@=3
za|Y4vdg+~HIC??)3#ElONWb|TnvK#|KB&AXZC69{k~EGkfhOr-2SkgM`3ahrr6yV<
zUy)9F3A?S*my}v@RqD8#&Y!eN^WTE`Ytq2);aj^@L|4LfX;L159a1eV18zt=ccSv9
zbiE8e#Vu*VB8b~k6{REGk*cr3(p@Q@w7Bu4PkTVtDP2JM54&XHL!c5S%Nhefw5;|F
zIAdfNX<ig7v!fZiDNdG7Ig#<Q=+B_KUv`Za4hb^PUm+4@b~XSe$v&~d$R3n={fo-O
zvg)~@NtXEyL$_088#Y25k)8Ynq^YvKc4#{;%b@(BG}$={cNEHocEYtHS=ku)R4mie
zW_yV&_IGernq<wC!BZzYL^G*+nNt<;7i4dhqfZU8x8-PSlzF@b;6<5dI@m7BZf0Ug
znq-qIq0%hdlnA>mvfz`@ydmpvgSaU>O-qwovd&p3-If{ug26j7KYAbBm5CV`x+fdk
z0=GM5rZ^vPcgxbgN9}#tAPepXGROB}>7i^Jy)k=aGb#A^NH&!Y$o0y8UxT*CvRXQ4
z-Y4szqj*nb7sJ8*R91fuD*dun+Uvw?eGlL-WSeO^_)<2%3M>P%&|e^4$=nM8e=S>W
z3P5pCR`LgmZ)6U%7;v?kYYpGrtfsvW;cm5(mK`2e78_9Vw2Gi_X?j_0J&bYkw%T|U
za38BqS{(UXS@*+WfR!Ch9s;c{(yA-i>gRt@3b9&h3)e!eF2|vAmsMseSi-E>UV8t9
zTfMsw#obmDcLE=0^&y2F_E}A&kZ-)zp8XK}t!lTTEy3!oJ18Yu{X)Nel2!coD0NsZ
zyan(3t-8j7%+-3yYG}Gy2kwJGck9zf$$RU*J5ceojy?@Xy{s=R0M5_)--jaHfBx3D
zR>8#p>%mnZ4YaQFf@-j})CM#m)@~o8qr0sCum(+-wS=;sBdv$z;z!$Ky>2SnqO24C
zg!g-`7t&KJ#(L!naK~B?(BwVNy6I!I?X#}?7=ZoOBclO0V0}XhkzgG@eF*NqL~GXp
zm_KMOe1_UX*1}Gx9=85=8rYJp-}?w6)7pie)>+o$s$f3bdi7j%Eywz7F>txou8zRv
zS^q;RKl#>feGrA#uPAY-$lCrrI8$QH%mA*;dIPOz%B^EIp)VJ#mAx2dQ-k$o1ymcY
zC(tp$i`JQxGJDB7%m|t$>qF#Iv-PwT;ICVk(<HpZ`kM!6yI~#q4>WID*VusOwsq^T
z=xC>P_+^MLYjHa?yRFMJVE(@KzDTI_SO?LJ;*s^|l(gAvT`&ye``Bb1@HRU0%sOB#
zM8EYd3N$>o{(BT?URX<N;OR^2wVALqU@ftQ7q6_RKZg0&)|2Uu39|90J*{9HSvTMz
zHr_8GLTxN(qH>o_TL(m#&D2uh!fi&<%4@gHaJnlZY|bb^9cg14H3n>ZY-W}M7-bVm
zm&sn6JG6v}wz-`S5o5D>K2&3Ewo@#ApUu~lxfgG9><udS+nlG|mjgCuXpNU(v*{!%
z6Kx90(ZeL0mdg-_Y~E_bARM+yrh6pW<}-J&q}a@NK;==JeAD;nXsXQzG$T4@^A&AE
zAGZ<Dgh;d5=?%7Yn}fqq%CMPBUy{kRsrm%KEF1PY>}K2K-UU3@#y$nY*Y@+15Pr7a
zOQGp+8$Jp?h1stC2X>=vqb5*aY?o6~e5~yvT1Lm&9-K<~5An9kyy5A7TmKiRJz(2<
z0VWb`Eojps(bhZ(=96qYC|mTHt%BxbIkxRC5V^L`C}%X!_9#6s@@@4az;f31Hwtr}
zvn~4qEaz<((A@Hp?N9V>Y_fHsub(vAmQmJ6i|vhPlz)5KcC`SVE4Igzpwntw5e*lw
z+P2*XX`Aih_h90h?W<<|c<r`#ro)Ttwkw>W*<ou=gLlKWdM(5)+hkgB-nRYj2{iB6
zKBbV}U0Yv@g5R^<6%D{++kq^!_1Ug(L)#PE13@(Zd}_-MLE|&qrg`wY-`0zgSDxE?
z&~5m__9}&=UfMQf061WKcOoiZ*>0zh!)x2A^za(AZG3@}tGrJHoSS_5CaAc}-=lY`
zhn#%~oTr@o9Bp25-4qz|mKQst<Rf47H#AMY@^}GwKe_%25dQK<zo0fizU*5JaG=~+
z1@l4jd6cjiEH|fZ_7Hh@G%7>oJ~X7e<n#K`7A9X2kIHa)!4ZsFgnZQh=0)=Fw?Ji&
zd<<oMMaf<0ZMavyoVMAb<!{sKCdMS6G=O5Pe4iZ*#>w|lR{K6VNBd>_<=<RD>44mw
zj*2D7&3w_{MEO)Y1)3zEG9PUR<=In!J0y?32ys|G_6SU*$RE=Md_+Fl0V+r3C37$c
zsq(qBS8_~#_z+l*%fI{+m1%NQ7cDH(<+^x~X2_fNKqpgPMJwDa`2k8t&z8@;i9Y4Z
zH}pX>PyQF3i^!LMwG;RPc>vw_h4R#KFkd7O+W`0pxfM;eiskL}MWjmk*~cKOlG`o=
zpjw_rU$Cf=PocSKgS^%h44p>#nHKc$qWoVvqjE`ps0eIL@*T8o-7HT#3A-(F_6hoQ
zS^lU1fGhH~xnOIRe@v;+SLNeriP<J!u^*M!<bf1uYM1A_f$X|GG#Y>oc?0F@+?2a*
zLFFy^bQidNTmJqKia+0xw|fI|SN^p<bneN6b09k9lft0dCAXyGz1{Lwx=QZLOTGZx
z1NkB?Dj&)>YEjuExAq3$kv#qioavJv{}5zP<mal<_EcU(&xB`kQ7uHjJk=8_&*j4@
z=lX@*(U-nI_fp<{5C}KBN&lhN-L9Mt9eLQT4MTrD?Yb#X%-ilcrA_+Sec6tZubqTu
zQhs)`Y1ZIx*GQA-0K0H{wFlbm9EHjtyDuowD%dU{2X;g3*1BRuL+$D*=(o!*Z~+V@
z+n=(f{P!dFZ=@hiwQnc}@VI@?P&kure}eY>GwnB)0+DThi&lKO_AAE0QlY(6fM%0@
zY7qwEhW$uNXTNEmnT*mc`^jrix@}+mBj9)JuZ{xzu6+}|Tzc)}XgT%R{@91md}i;g
zgfKm~=V|-*g+1Qo7z_Js$^jd&4{L`Puk7vVi-NE1*B(dZp#619ae8C_>oKsoDmrO5
z)=lw}47w{m5dim4OjrnmfeQH^a0e;=`3x*EiuY*!7OM!3M7Q@T)U*d4uQ+)RD*H_e
zyU$TPpr{)S)kMYEPiYVoFKI(RO|c>gb_*0&(jW>IGnc|(kz)D;sGL?rx4>?tqC1?f
zZiO$Ma;jGRM-$H)#mZ?AXA~uLi0!Q6ZXR&w6fN`{oL3lrhuvDmcPk+36s9@-sI6Bl
zr3vo^MG8f9TNQQR!qcmYXB1OvQ!F;X(lv#(7ZB|V+g&JKS2#Driw?!*zaVZXti%vE
z6)&CvcS|v05M8>hu<AnTj-ri{%kL_Ns{y~K$fb>+PDS$o40S2ArmFyUD-ym&@xEfx
zB<MU)4A2NYRQx&zKUa^U#s-y-6iE>P_9}X5U+}SlYlmxnic1u@e4-e&7%Wc}pZx&9
zGes$#q3c&{z66!$itq-sy-=)cg62!b00kfi6gd<Kf2DZWmNp$;D_&Dhu`Bzb9)sw{
z_P@rExU)4c!REo1yaQEFc4a+OB3Q>-a7VIJ7Jxg7_5T=bd)b`Tz{RqYdEnyMLy4%|
z$F5!if8*I=6TIKgE~j_$0oIRlDiYX=!}Mdb&lC*qza(}irHve9yD8#%h+RDr_`|Fa
z1G~wrtP7PXZ05I6Il}&V6{Vx>CQ4vPW&fZ}uw$%~Crlh?zYBngG*(^!&2&~{hMr}x
zhb3UiWX<g1eHObzk5V>!#}zC&tY|iU|2UUTq-Ad&`;6w1`Rtu6s1~p;BT-q%o=Qil
zhz<V)r4#Js445cpyD@Q<l&}JQh^CZnq)%UzvGp17shqW<7iI;!i6U_)+5buaKgAyD
zz)+rMk5KrhlATURysFrb={7V~v+vRrs)k)j8<}U=OE1u;v+P%qD4k=QX_j@KO}++1
zEqlBkh&pyMZ4}qD@6yZd0^4W@%?6g80+mK~uN+=nWXE^F{3W)9>^89r6{u`xf096@
zh2850_+@tTR){MmHj>T)wX(U9=;2j1cPL72Y(YF!ud$Jo3f9gJRH290*$EV=?O?At
zg7gNvfX=VnWY5t>ev3^Q3fFG4YbkJYhkgDP4Blm*(v<BUtD;2zPIfAt8SG;FGojMW
z22c>`K5Obe3Qr%f<+SL3$o^A@KJ~DEm*LDKRx|~omwimX!DDv43?tje{>P#8gnjij
zOgv>HXx9FWt<k}me)g|=kUnRho`a<q?37@Lm+WbJ)eW$t*F*CaJN-MrU$dW;L35C8
zF&#mF->}Q+5P&Q9U=oBIS3>!$?wlv(iFt5GY2NI~`FxL(7q{>{{PpIhx})U76@Cbx
zd^w*+kos{>weZQGv!sPV02e?98UneDtFRQr&3y)3FlV4m<PdI@C)z@}(~UHR+QqdU
zg-#f!)x*Vb?h7d#-p$=;Mk#`eUJnzI+{Gh6?BO{2DWW*55Qx3p*8v!=XiiNp@fhy@
z8>qx`wX_Qy$9+K0?0sD79;n1~9ZO+oKUZ@ReL286(W#pR?#VWK|0QyAdbcKV$77&#
zkaG=!-9y~RO94F0Wm1-0GWV1|{glF4P;~zY7xpPsj&h~PAX2%lG_uFIzcldTIQRZo
z^e~On(si89U8C*l46ghUR5H15o6wfUIe&%@W^;bH4Na09?iIaqa=C8>=;U#SDA_ch
zyF@|C0`46bm@nkMp!ISQ_iH9fC%EW;Q7YzgW&lvaZTtnLQf`1kcV*n+HBc$%)W5>f
z3a)k{#_1#%w+1~s#f=(--P7FUXDC&2+uZ;#RdGN00#VHsIziNMn<!>@hTBb>bZ5DO
z0~pJ5+)6q`aGo1ODd)A^2oH3vj_WxFwt8;ZF_bQFNosVWfeZN#q>Y^VeYkd!vwsQm
zm$*SOL=(5!2+_=4KMk@LF3Jt!vWa_r5|*xTd&Z-&l{@eTG*`KbPFQN=7Gy(Q<2wCd
zshv|(j_q|$Dg&T{bD53O4X)uw(A?w{QGnm#W>DziHkU@T{yW?h3Vhz>5~IL*kNc<$
zZJpf4almzP8|Yv`H)oo34Q%(hJG2IWz|H6Z%|p)64tx)%r&#|ZZr*lWSH0Z7%h9#R
z+!zXA_Hm9hL3qM#OaaYPZX$il?-}Q<gTMXUJ|2MQ+)uQedckd{%jzXpNza4<&f_y^
zzT!4+K;>)hUDHq)9OME6Al`6$Xg|%B|HKM3Zu}c547&5X3Q_67CzQi)PyROxXnOIJ
z1EJ#0>-M3|hZkm|(w7gs18zTl+;&*<=OZit58&sUqi2D91;rDB_~Pkc3Fg(b`VHYn
zU#9n8C_l>`wY&J=tU(&aza9-lI3Gv}u)Fzd6xN8~kDZ4~Bp<Z^q<i?e&mp4tS<$ex
zmtWTmTr}TY1<e@#Ag#J%c~vml;`m1t9684CrL#xJ`S&RBlEznl3YB#JbR*?IWbkt+
zsFTTWp_?R&kD=vuHot}@i8=gDdK>2Q<`n+P<3Fo_Yx#WPPN)>{Hc7Bs$nTmDToK<=
z4bl_5Gi}8d^SV9&O8AWwTrA}msUXVuC^rDg`Cc_RD|jAB?KpqQhwee~6kpK*#A*H;
z+Bd1>3%%fQ6+cMJn`-_odf3<SB{NVu!{-c#iL?A{TKJvgzgP_1dA@ojSZeuEbOY4!
z6?Bi(^FO?VxWH?Eg=-DGJsmY}<VQUR;3EIk78o*J;=lbIY)!nZ5ZulDPzJRvd?hX5
zF7py>$xE*AQHN03%KKNK+gJG_OK7(7XDHw58s92`W;_3kwm+`(FX?9P;0Gykc!U3#
zE{~i1lQnSd7N1I~-?#aJPoQ##mr%6%u8H4XkFMS0W0r!glmDHb#9jPqidl5?|GWh7
zKL51<gAe!;%9wb_J5#QB55K7hDv$UthNDlteDyYvKIZdJq14C!5d^zW_<ZW`Q~n*A
ze?H^eRsq+~|3UeG&-vdzfcY1^>3abNU-Fd<24R4geSz9n{JG)KdCgCu$^Rh#@O@Z%
z!w1kIeOKYYN_5RlFr7fjU3f+rM;^l39kApn_|dG;OGrD2lDE*m4Aeft5?cHF3d`@p
zf}gOy5&(Z;wg~V5A=#7%?m*#Vx`KlQ?K0>D3!CUA6C(UWc0+~VQo*)Mc+ihhnDCr_
zm~bJBcKUY<#RI5}5bjfsQKYbrRxo>nDkVx$!nz-zvRC+Y5;_qrIL<@wV}zAv@Gw@e
zq6bWzFqmzE!F@vWU(kscMo?b(eqkJiCk_bnD8D*E*t!c2Ckj7%!;2&#mDXVgg)B-V
zJR}UG80TSOh6~z~g(>R+PZ3gv!R`^^8-IwS!s}dUrV5#f&^#t&hJoz3P{5*;Cd|4f
z!~K^o)Gq}-Ln!|g&SVNUbAiYbY8;`HEeLcw<OrKbqcT@8{}4l(CmcA1%6wsBJ#YoW
z;b3SM3aJ#iFA{#B+>;Z+8hWf33uQFwC4yfj0Hwm=AsDVQA)DeL<-#dkI{5!@gw^!j
zt&>7aG}ulF0teO8!bB@nRtkNefV4`u5Q45%3;T(?M)>wHXwC=&v_o=McybGE=Y*~F
z0y-}|dJcoNLMvtF)Cp(npjj_uK0(_BVcT<*8idG?VZKoiErc*#6vnQGiAzEpO(2_u
zzZ_88EPO$0(iUOFW*EFIRCwU0xFRf|6+x?T>qBT>6}D}KW}C2xM)sP}HWen?g;^5d
zt_$WP;ZujuK>O!6g!(67xhWjjj-K5TE?tKgw*_xn<lHd{(%sOxD;%Va_j^JhJ*GQ_
zY#)d&A)9jTx&`l>P`NMk(Nf}p&{qxf4}~2xCFl`$KSt@1uq_;=ULkxwNFNIi$G~8p
z5RL`5<cSbH7c5VO&*Px-Oqh}ZxBCU@6_lO}rVl((d?73_hx;#uPWm4m283T}&GSl_
zG9Egwg$tBSFerS!7n*N`h$T>QRT|9Tp_}pq?dH2HH)>GwP>$+Bo2PQZ7w~DfGKAKv
z5z4p9(H5yJ{1|O}l<w~V5T&%3jkdkYwWjBgG0LOiK*TDgDbR^iE}+QeK4sY3up6(O
z+X%b+mDSED9Z;Td06sx^i86c=mB}t}J4v~aNDnG?HozTHX1RgouyV?W5Xs7R3O=VO
zC(xPBBg*46F*&MS!Qp30Rlf6*LKnxBW*?yOxN;1ox}+-?uLL4Pd3p;(rZV&<NVAlc
zDp<-^-lb_nj&dQzYjc&RZupd^?4bk5`N|GQXcj2Hr|46m@^?C?Q>1L5rOOFr_`9%M
ztQ<kRrX|Wf6VO(wEX4W?_k(ggE$+&d!Cla)Q0mNa?VMCDrw`_xQvSrk#A)SRO3JNN
zj-wOWRZ8cpFj1{E{0EvEr8@;<&nOFNZhBTZ?GuP|N|*n@d0zPkeVo5mIeP@C>y&dS
zmRqmvkAS$KbV{W7OM~(lWw16XQ!hjHqS7o8;*!#5C+s#Uxf?Litn{7(e2elkim_Z)
zj-ZA473GKbAzGCqXjAa2^6WJD)TZ1)x!2c}brIlfSI!tow}bNYbZ~Yk)sx`U4dqVC
zIKQb3p~b%GmeSx3Z*D6`(>m;qa&ZR`ca@tc>FJ(w#<$SvRIbSZTbEL>hox@i;_py-
zUzs-x;(_wz6|g;2_Rs^lN9kh^_#@>2eJi6^IkFrcK2|!=+OALea3KcoiPFyt1N2n+
zni3<PnUvArK($}#-~<<+D+_F3_k}Wo5)ED|lUzVLpiI(2<(1Mn5^S%Pe;A=Ts2oP`
zgEz|Z2B^5I+7G}(H`U~^D7mXP(4^EuWn@wER6X|q&P!E95eRQp6J@3QsCKxc(pP2D
zAqiUIr~1?fr2eWVO1%nDeclUvpz0Cj-2|zI)3#@@YA_DK5S0`89jfv;50zc2rxdpd
zQ(3QrO1NqnMecX2nv=mDq1td0<|9?T<l!FG(#sH0D%E5F_NvS$0UoW|Y|6nP#;87f
z8$FCwHI0RcQ%xEQwtXsVx&q@>6CMGvU)4c3&;eDVJ!leC^9q1VRQXq-l%y(n0Kh@j
z-hW{JkjkCn7>8A3=;(a1%I$4brl?N+4wWOSr-wjxR8>O3t5nsO-2d)B)!To;;o~av
zr_f1L{XGuc=_=7i=wztgVc|ul>J=q~W~l~Nqb*xCi=KKps#VLtmaDR)EvP(IrVA?b
zRr9Z)RG`W;K@_UqrHE&dime0gglfhmI8&^$qg0|2)t(@_|4LPVXQH-DwUCCbTxHw`
zOBE`gB(R-U719T{DplW7%6hdbb{Y)UsG2F3d`2~_47jtZiIs5soa(Fh(RN<NeFaOk
zsx+GU)u|TI*H7wImnaeSf@&6B>J6&9w3*+i>hZC_{dZASMnRHGs&U`I;U?8T6eMX@
zO<E3`7S)LtsJyJI&Bt$lMRhp@ooQ8Rzko`c%I-T<UQ@X-P-#~!7s23l)un|H9jeVI
z;Mxt9)E_K2Rc`0diCd~^loozlwfqAB?x^0OP?+g1=IJQjQ>kgUs#6t78%tfPun&Om
zRz?1W(tXvd42TCR?P_Q~RNbXHb&u+)B~%`%w$Y;hu_}|cj{8*RlsoZ6b&&GcpQ<A0
zVtb~l;9;p>b+iHgK39#TALfPXG%ZhFnpC-7C=RI3#=`t7RqQ2{UaJ-_25?aI{WVm+
zQB4xTlB@di6ZFDO9q|c-yL#DO2oLo;zo5-i?O6+MFZD1=4D?o8&wxQ6HCGN5U-ct;
zB>AbiDKO}-9=!{d0qTLf7>hu)X?ipeLFzB)|Az=xKfQ>?5cT60jB}`Zd?|pt)RTHq
z8KzF4c}BQ;(MRxbw|WvyV<Xh6EATK<?Jt4(J?izdVIoRBf)aK1syk?_FIv5dvdLo9
z1wDYrs*CAbi&Ibg5*GHUXPN$j`FM2+?VRsde?;ja2h_{IMkzs^@d?Z)sxN$lQj+>S
z<rf}Qe?xsbr1qp7<-=+x5ymN5{Zl;brl{Q}p>#xjkTUy@s=s^zOQ~vuD|&WJU2F+)
zT%BZwwlp<QCri`SNqZ^&lA+$01d*vuqT@|j>NQ`${cN@3W0Z2#lPch0uG*C{eDc&)
zhavLSGcDj#f!fv`&J?N-MWKg9>VzC{pHN>t2)o7V9Eu5*sMA@%OV!`+L}i)!N1DTz
zt1ni9x<cK!pUyv@ROeGL>6Chb8^me#<{UIus$~X<Ds@i=2Dn;1FA%-2QTrZ(-81SJ
zq446YdTA-lpHsVhi_&?uwFxS<>N(l4RHr_95V(5vCPx4+sO@6mOoO`jUvM_6ofF{i
zMfF4r%KyBiwp|Z=lRDlFs?F+e=A*Gi-E$xK%W8AVp}wNdpzV`Z^|%=*T~$ZVhi04F
zjrOCjsaH{?wOyV4HgMO~68d2~)P|3sc|+Ywd+ayW)5gQmTk49pVg9zd_&p3luR5;)
zKA9e?8!5=&rw*kJq9<zhPl%^#{X8I^sdv#~r+)PznsGi?ThRLNh58_!@P4WOwi9gw
z>LSYce5L-1@^xOTqi9t&s9tvvEXN!kQ6%lSLs$t^(jCr^MJF;H&PdUg<?vAyyvQ~=
zv=*Z_$6;6qYI7YTXyKRdu!JUJg$|R`Q7Up+rH4wfLn-YKl{l3D4$V@B3@fyiIh>@I
zOu574Enur~2oRxk(qZQzh*J(;bUB}P=$i_7l|vh*8<J{=zDzh%<8a>wDrX%`TR#Kv
zoWoK&9dh2GXgF$X9b}V%sB`#=Lg@7l78EkM;E+nGaSaYbhk>TiVG+%AFFLr<hT|oN
zVRX!|$${0v?PiAv+AnEwcx^!2Wrvt$z+G{eO<|{2hq*McR~@D}qZ4fo+e}-add*=1
zMPu6?8kV8<y2CgXe7f!MQz$&W=U_qe^-c!|iqdsCn3uqOw}UT*{O>z-PJnpe&_*%Y
zhYqD-0Q5NY`~=NjhsDD|_Sm7%AMieh$<rX7ID9yO%BK$cOsG6_$azE0!hVPKR;YdM
z;OS1kuR}DYxV>};$b=UI4m0Umf8{X03MO7Vd}R&5pu=xURK9Vro(>vU%||^DZkk)e
z(B`gT$e@Sj9)(dnHJ{L1)Jrq$F;u)YKmQF*A5F!VX!F&~kE8rgKTVtpz3|sexd0OZ
znwALQ12y)vyB4Imw-_Q=^Gg))A)44G07ErPwt+NElSfIC;hG^!0NAa$KwAwFn(>sm
z6{&H#f!}VA<~@I?L}{w&t+H2R*$hL`nhz+IFGh2H#Sq+ov6?HZ0gTgZpwQnw&H4Z3
z_iFxo2deuuk@QYKpmC?GB|%fy2JR${#~}>YLCuw)(BDIvy#jnXtU0s<Lz1kCpm5|7
z%}UB1NYxyrr^hkPVanx6(}b*nNY~t<{j3blXN53p%GBi2y^^IFlLJJy=9?y%$kp`H
zc;#u{-H5h)jYf{P0!=D~n+rAJzk#$!QyhdoozPT$44Pt%j3P`WnvtUcFVz@ZP+6wY
zsi9J?c}dZU3XNnD$WCgW?1APfjV=zAr%jsQ9np(Q%@VpWsx-kF09I=z&}^wjqocsf
zS<O)fh;y23+Ic&#sb%0=E$pIHrzz)QqF!^B62~rRf-a--rRMt-koh=TQmo$3(VIe?
z{*HG&(YD92h<0D19os1^ALnQ)rQr2`$H8}jPjvjc0S1#DRWxiVj`b}l9dRtB<;_vY
zcO|ft>R3U~{9}$k&W0Dq9jDNHH_dVVDjHeG(<NZZaJ)xJmYI$Vrb9E!(b)*Q*^ci}
zrdf{Ti3#A$bFBOsxO~SaCVHY)I6mow!IO@wYyhlt%%eQ8ddHnNpnAcvZ58Y`IPRr+
zRiopDU*XI}$ApFG+9k&s6zFYo)LaEiv*W~6z*`)x)&h6gv9k=$Tygw}SXv#&{sqpf
zj$_6G(B_zS4=mRlWeF7jY<Dbu8^G(1$~kbV!|}^}G~RG*p$YRX$MJNa>9%7|5!gJO
zc6FoD(`jHlNWGly{0*G9)3)s(jdhA#2wa?#G8LtLPN_7Nk9XQYn~D3KygotcfK$N#
zc6pteAEGkJNxXpe{|-6*c^WinPCL{vk?v&ZMSnA#2IzcXrc)bb=wvw!rFcZP)52<$
za-8s=_~9aTT0zI_OP#LL+M&$J#T#wqPT|8K&N}Tb1=%^L<|Pp4ouo8*uXWnk3zmAP
z?`g-a!Rd;E_Wv54K6QdO*PQf`aIxJff|l#oo%(-)PKQ(P8d$pNG+{YtZaLvKhKHEb
zJ=$D<=Ctu^X!bk(brnPM+-db@{5~(7x@jY9z-cF4>#v-ODZ235DbWt4L8rNNoY+;n
zlOCvUS{KR&HMwh>=D}eP?I(U{^wfU#8-$lu*^b_OYd`)44*P0bXky~0{i_ASUt78Z
zoe9t`9RarkwI8*CCP+JOF)RgZKczj95Uqh`b-T2?@P#i)n6{`8ZQ)v$@-TO64_*c?
zLR(3Pogz)z+hd@*N4v@i{f*N8w;qkr+DHd<Ek?U*F%WTD;{mko)9$CJ^&#!Q2DBa4
zo}mePigpoQ5J$98^tejZUZRYb<JxkH3#4g}6+$Il>rIn~3~daB=Q6dQ*nu-kJ3R`O
z*;<ohF<i{i&YF(KT&*3Q3(nJiz7}lx+JAq?AQWi3?NC{yZJ=*qp3<(TJLa_ZYy<F>
z+WlI1U!{FbyVKR$i#4dM(K2*hoY8(mbG>ugH_O3tUi<C=wAE^3Pob?z8%V*$W^J-5
z65Q?D*_6<6U7IuvzIABV)5`jW*7p|1;-+@NR5)`>>vIeE+u9<^B)+3Pt^>_ot=CbQ
zzo*?V0N$xxya<(D+Q(BNy0x3zp?P0>ZX3J^9UA+HfhGJIIdeOVjM}jle~-Rp+70JC
zL@soDc#57KgYXhfX{H}v<cpsOr?|H7K*?A1(O!W4M2+;$@fT&%j}Ra__?_7h^B9qs
zruI3a2TAZWSM)E%0P;lqZ1|QhT16L4fvAEqHw#5uD0QnyG}09+Cq(vVY0g+Il2Hu3
zM6}^&cw8#_l%DTpA`6=MmW#sZLjV<`uY*uJDQZte+bPi)+GRT{>R&fxi1}TS8$GQ(
znabOMdojNZhe2;<K7AX=hxyV20AD7e03|<WJEh<GGcTLb&j4oO4*LF9Amj4|5JAl1
zET{%EYgd9hgxO_}K7}&fEc&~Pk;KD`Fs2qECi8e^9JWEsFEWi-eVcoW|Dl|b0I>;?
zCi7il%Q@hV6mzsk5hHHnWZ=f1PogQ8^3xTR=rnD47<8szKS=u@GY0ZOz2x$TF#dDR
zUHG>_OKFT-b#xKBC@GZhE7G4s-vUG}AEA^d+D9{m3elps|Nn2wt$hd0gW}mEVf2mo
zq%|CJHPi2>9+)-Qfq9qN!W}3bu-HpSY!WPf`V!=c76(mRK$v6^Kq0s5@-3I3b65T^
zo$7rk|7SYdp2|1ZLiLqgJ_98Wy9kOX`P+@6T(n(w+A-jcvfI54rFgsQ_0T+I_mt8C
z58J(@ucs#4mD9d;id_(e!;jc~M$_D*c81?Ds;PGEb@clmv-`vc_~Ul@l<AyiXWWg^
z$+r7<JyeVAmit0f*m=(dTaBIgZ#Y_S*ZLjsm+f?eAiZMOlLnSnyCM#yt9E|FVZP07
z_-crUc7+s8@3D(MhteavbrfOjwfj8?rN?&rk5T-g&#rkadhx_AdJ^nDwfp=nAfDMB
z4usu)yJuVB(+j(@IGBHF_lh2219mSdrR|lSjw0Bv?Xu{rPJ?z`T>!kX6ORD5tNmJ<
z*1OsNM(NM)_6q_~^0Duj0v2EUi}X|Y*=M@b@9%G)@B%ae_Oph7W|#elE{HJugx}E7
zaQmBe__=o5Z%TvR2>ak`U`w)(OQVss7t#Cui2Z_k05a^44Z?i3z5H+Vu*m+4ZfIV$
zpFR<7ZT9~WXS=;V4&u7~*tHNh?d3-F+H}jl=Pg)zVK4OH+HqA}phL8Qiotm>7^HZ7
z6=JVqfVMRDD+Z^-@572t3sfFgusy)%C?0Qyr4x$j-@~Vqiq~#{pHZBr{J0AW_9JMv
zC=x<ZYFE@y!10bkO6e326e(+9_K8U`F#z5SDAE&YpxEJOApBTc+LiKWPx%26z;5yd
zO&~j!Lb*Zg0?G;wX5XdPR|tFlS9Cj+?NXrIyI4C)zYJroD2+Ir9W@zl?`B`NLo<SX
zF#@<q_U2rW?O{FZfs0~IPG?Y?#Ll3*{UE!o5{N@=`vvMKTXhGd$?V${Tu5Q3-3HAO
z_T)Oaf0RA1hGr^z{s_b|)`w;;$Js>`s7zx6DHxf~KBBl%2FuXWJCjZ7flpcNrkAjn
z!_M0S&0Kc6={kUUY#<GHKAS}=tpc{#2cnR@eia6bSa({ipI}E*x?3?DF$**$Y#S{p
zOIh>ZVX2IrHX54cY;F`-D%j`ss65FQQs(X{Rvv*Nsb{Ma(4}T}+<&0H#_sb1;5Peo
zD8>KovtA3p-N)9@$;1Kn{ycEMVmDlZ>T5P{BJhLke-&tZ!`A)*O;=7uv#~&Kz9m$G
zxJeY02<B#f0+kTXB^8{Z+$Y1(wu|ehB}X_{M2_y}{tX3L1m`ph@JOzAKJ7p6;kH<y
z7{zs8hd97_P?}Hzr`wNGB4-)|TM{?tYg8WOuC;;Y5LXosFAj6XU!pRZ`*0ANN4PbK
zXgkUcIRd+>T=`^-(=m=uhWX>17o`rRaj)({Go6$E4Uxf(!$yt?$sM(HvbTt{qu53X
z7ej|lO1V!+oZ*)J0GhMhjZ3g}p1buafcQ!Qr7$#eIj_*|7Vb4|@?POWk^yh!D(OzW
z#eF;!&fMm5X-;>CThRe=m(x6i$~~?;3|;Evc-;OHQx`X;3bLEqgSP<^A)4u}{ebgu
z2I3(XZUIX@Ts);+KjLBzq14N5xeL3Gxn(;*)5j%JtokXpb2$LdxIMIc*Uzn`<nQO)
zp&ub$aKDd22VZhedg15*S6&B0uebm@<?-6Y8LPlH$ZeuLs5jg+njpLK^OphW#<wRy
z$DQ9o`Sc$AJ-T!~`E94r7R2A8I6yET#Q+e(_tNR3Q2qrSln>+Q{7OGMfBq?4+s#iO
z3P&UOOj@)i@b6GOERhc<l_cJDqZ-A7eAa!a9^#w!g7h%2{2ZlZ-iChB6#m>50FUr>
z$Kd`^zBLqWsr;m5h-18(-sH#mYq#K98ejGc$kO>1dV**0Me$I{;+cuy%;tyPK`Doy
zF&?E{{!?np<KH#?gCWi5M-Z@pf16&8g?tc&HjDW8>5C*M_|3EtTg?BM1TRYXcPYiB
z6iF7aTgK0s3lGbA-?6By;IoGTP{(Wb!hAiy#E7;AKKM9rjr=fr`ZVz|0#us$xdSLY
z;N6mFb@7lt`98z|FL<Ky6+d_#=3n!j-^0Wpe{V4=-|$_oK)4D|DD~D&=%Dq0yU=+H
zc0GhX3PgJflXt+Nmyk`7LT^F+J=%N($1x!D6{6k)i=QyXA8>zR$N`iBg_LHBKLiPz
ztWX;)eD^beA;M$IJ_{8>#=-n9A-@{jVZt%mt_&C6&|cGS;pTtnQ-sh@BNHin7=_Xv
zVUZU|qlCyZ!1oGr%nY&ZzMf80#0Y7W50NYc?n7mYP&ylxM})Um(f;#MA;A?tNvhyY
zpV&Ai<b42qnlQ5jcGCs-m*`W5u#Q%wnL=V6yvP!yl*pSceANiCe{38jie-*H;R0u}
z#?G$;i|@Gg%VDDBgRg90u;YVym0)>2@ekSsADp=U2r9!SrPJER6g6o&J+Jmo%HY8r
zGwFwPuw_qjrTOBiN!Cu#IXy`}A1dc2O{B-p-ATj00$cLrDHpBaDgJC4Ntfgw-FLzM
z=hzSM_g~X&;Kk;7-S~Se+W_#kiD97M-qHl9t7y$+(7K6!?V$WOcM%s44S&(OVW0^R
zHB$~^kjO-{(FoDrFToKh3jYm#-6tBPMMS*FYk+z#8b&YTWRWuk{Zd5pDI@BLsBblf
z>Zs`WL~v$_iUO%SB5%4hPKXkJL#bHQ`W{4yDDDb<f2&mV#c~vDL^ZT&eMZ#Z3evM8
z^A4CeC;IOc+L}aRlxf#2vXEf_T0}wge!46==?4=XqDQr8yCG7~g}5o&Qw{hnQRqbU
z@V00>eSG(h=+#KLeOGk+F52#it_%TZr)YI5+DyHouxBVf7VV>3zfbfl1%950hUWtR
zRP?a|rPrdM&+%&viux#@?2YJ$RCwXayrNVNH)csAD%}}l8@N4~<R#GbWITz*i&;vG
zEpNu3)}}tp<NZ+aWmYW*wI7q>j}H2qn5Fbk4PfTafodQVLR*zVjM)P?9L#L^2qJ{J
zO3ARH%=>S_!(B}Jc$C5zHO&~pnHfs3?PjcogFAw`YzdV}<~_<H*uzBqg|;Xr?nhYI
z%Vf`hqtT3-(%xej#|Zco%b4VJmMo4*pzzZ^rgl7lhnSV-P(93aRiHABxlYfMbjB|Y
zhz#Z?C30pmU(>nALT2cFR2DJ56wo-qOqdPsV&>~juv@~oP}W2xW4{h<Rm{7g(5z<i
zDcn`VY&HOXhDkFmf^TOT{vRODF@YK2Ze?~;+QU@_{~;76kIbf30A6F>oey9KGpifG
zTg;{}0l3Y)p;g%(MoP&<cbO9uh`h&SOojKIjGSIDUCdz{v~@FYE~3p<{Mo+%_=x)`
z|1DVj@@*3gMu@l1L~X2i+YlH`6#wumOdJ&-r|jKSF`o=^Ogx&d+2i7)w5UuIZ=emt
zba6eM7Cj*jz6KM;;^%`fSRz)AfNQ1VaTH)H6E~>PRxZv^!2C(^UlRa0CBFAL#A$KZ
z3EKat6su?vUL_v38Qj(4f;QkUip}XY*(!E^2Q)XtkLWN+r&y{-<s<RIDggS$e^5kj
zP`q*l0N!Tr?82z|nBAn=h_6{YC0O{GrJRE$f3q31P7g2}MuFZyvz>ELiZW{$p#Oh$
zuh|$ni4bkp@dPw6W;a$t#F_=h!)~0}`-{-0eP$IK;QoHId&9tez$}x#%bj4>O-a&;
zW{H&apJcXiC)y60ne6EbGP|)IxJ<M2a`;<d_UE4vWoG5G;8T@Z)d9e3%_8WMHC-|b
zri=Wl*#dJQZkiciqqf^D&K5fN&Dd5T9+(|_fYL*=NLqFEm`!m;w;!49GlQeOX6^<6
z9-9sS0q{XH&xP>fjalsrXu3)~V&R&bB$D!0-SGu2xaJ`lNCChT|05zey-boO%4zVC
zyt^5VzLLLgL)A}`a0qPvl7EIn1mFNA5P=dgO?ZMNB?T}MEUBS$)_Ww~-cX5>{6ME|
z_DZfKfF)Y8j{J?0WQEXBO0sr9#7Q(XnTf|iQE2X$yuS%72PCF$PxLTB5>H2P5+zC7
z;7pQasvI;2CBd{MdtAabK_yM{DNT6NC7LhLmVs0DV9UgLQ-~~l{|_dzC9#wroFmzt
z0Dto&PiXO#FZq_1l?9R>+HNY8SY3zRBFVjPFfu13f13ipRxI)R1+^vkA~I;IBr{*b
zV727!3?OPGe_n&i8OZ`)h_jL_6y86F@8QAjdCBK3P^pzj*Wo9ulQ_|a<poK0Gsqew
zig#h6QPN7eVizSnwEcNWvZM^9Cdo@WVbv_jpKF4{Es_st-{ms?QzUTTK@thXUCE3I
zV7n*z>k(8tC3gAfOqV2`cF?;ec2?kiAbB+h@Q0GOBcRzMNtp~2k0guf^6HhmYJ}!v
zNgjP9;*I2t2P$37S9!rvH}eyx0e3gQ5<>4k5A%iF(dcRZa57AInR|u9MIZAoDEr9Q
zd{!U0{mg%yiITth<|Y6G%(sjOX`p$IGfF|`k7(r^ZC)q^ON{xcVw7Ud*U*GA&V11~
zDD5-fy#S?n^Nkdl-fv!f4dQ_L@?d)ZC7O4ZfIG>28l9mzXujA0^M}korf=IEHXl0<
zZOP^-_b|>W=8j=tJ7Vrx43!G=SBvn&o-|L}0^B+CJ*Dvenz{8ORJNNNXg2cNeE3D!
zO}1Ed2xO-$e%c7K(-!f;sJv?NCuQ%M+ARzrz;{^;(2AkgVtp=v&n?Qb!S=#pJ%ye8
zEEm@T;cxly5qh}WQj-qz@s^#ml*_Q}p}d0=mf5ASd&<&<av!f+UcCrMdoBOl2TmVp
z+#0m)mZs7KAwlY84KLEAQOm%YW0HRB0G%3X5=}wRNS{suFhI7<9+kl|Gm7$u$X3&}
z9x6M!12kbW?FXm~mrbR#=m^;%y7VGt=Fi}Ev@B*PG-G7;!=Mr?d;30A_Q{g=;Ae`L
znLEN@qRg9~q)D;|LxDReGez%$OqQLN0)JHYcmo=b%StHiHbXW$1P*7(cK(1;wrsBv
zZMm`^VqhXqX7dzn`7%!ma2LqJ=@vgLn>h^PylmtJ3_`u^cRAV`WudvSa7ng|CY{Z)
zcoV$1ESohKWLISiOcznxA?tVq9e1l?ltbldr9F$1w^crc;C-$3Q=V|JRp?e|hFa~-
zg4k{KfHKx1twue?knFWONiXAAtJhCyI*32Kg$w>((nb45OV54>hkrD`1G1ltlko3l
zCn)^1JWm8B)6a`0ps-?6G8$H9Q2NBGov~<G{bCKwu30a}-@k07t;}C#!|?aoPv3{h
zb@#H-)8A&;;qMK0l#gZX{|CL@df_Addt3W%Fl>KC?{62UufX}QH%+#7<c-I_cUG8#
z$Hdccx|u{>uYq$Ho!o{>4^fmB$RJTSB@YCPR?y==M0A!iYeGeAG{jz!XcAPSMYEQI
zJx28QZ|G^7DDYo+g&t8fzEmWq50_Ml*3c}tPPBdxt?y}Al1Ae1ct%c{Zu^<{%IN!(
z2bf+8(<d-ddtoe*sc40#$&BI~RHiT^=#oFqm|9^ojp;5$DV;G=US$rGZH`hdqo+Ok
zJmyC~h<s)#WsDXxDmpz`!g!2=%caZ=5Bxr-m>HX4{xnlfIaig;k9E*Aon;<+!R|RG
ziZahGF!&+}9-d6ZX}I3V)X)`pkugUUS8|ytoQ2XAMzb5GR;FMgO4pfvVw5_V#CP#i
z++fy^2K*+o@PD&lW+Q!(u#?$50@Pj1WlFN_VS>s~`Ghe>0`SztOiKg)8B?$wzyW68
z2-tNMo9m$3Cmj-kaeOL^#*Wng25?Z6c^Kd~q8^&)xiU*Xg9~oVXiDL6XO@oy)`R&j
zAJ#k>vm+2*%qMne^JX*@w)J67(dyNgSs4wuAJcS@p1=Og4;0l5U^cgbEs%LQ8%Bc|
zhF*}tjJ_8JLzrqURQ58P`r&Le<3L9fVwllIXgkbA--o3XCbn7je_rzQXdS$?b2)T>
zTtzqUPhZ{ueA#9Rd|94ItEHdkc*2DhH%&J{v2ra%CRSB#fRC#?%D}c}qX~dtj*W#!
zzsAzG)!JvY8ejKO0P24;)<A##Yznn(U_S!G?>p$D5u5F2z?eRd_OrKjH{;*i{~UvQ
zPtjKk0QM3EQuemDsB01RNpuxozBb{y&ToMJE|G%*9)*co-T@*;w8jdf5G%6mgv)WF
zOQmojUgV-fWrFDJ=b$+#vXet3i=z5bc~n&PHQ>iZscEoOCt695+<H+oC1P9<?P)~M
z8blkPz;2`H(PordM1h|HZfX<#LW`;!A~{|DU7{Z?(D+oODhBYSXiF<}UW=xE2(~w(
zq-o%GW0nmEO+1qkippH(H4df!-`y3Z!9NN_q2qxm6nSrkTSX#0+OYC_qe5G;=+s1r
z646o_DoaIg#nb+0nP@pJvTH=kl<?q;=*(&0&x%eQMCCbA15H`ai+26L-o83Ms@&^)
zlB*+kIyFjZfws6-aV<3p1xf`i3>1oci%W~c0*jWjcyTShWbv~2;;^_Bx8kyRc}`~T
z{+{=F{(oLRL%)+8$w_W*?n!cThi9H8gm3hoBd5%c+Rf#Q0uRU-zB=`gY~f)*k4SkQ
zob!sz;R|-JNhW{0_-C?|kM>_kk9(+W9QFGHtr$<=p)a3_J$2n+l$b%^@mS(tsYeQy
zJCk-giLAfT)Wrx3=*LFbxC?0`{sN4ZbV4>3zl#3ktJ<sS4DQ*ip>OzoxP=zu!{b(Z
zsus%ard=Ok<{mn4FB-F#u04$6`{*V<c{obP<zr^%F&e|Cg~w?`FD&;29nK59Ko9UW
z@{9CS8I-t0SMnk6Z#scbY;M!o(@48RPpn5;K8@r(^)4;)9clOIpL{0toE}I*S^+)$
z0ckJjO};$zl3r<v@QSYEQ?J+baXDmplSzl3!WMc<{~n3*?`UtnP4=D|`SA0B7UdB?
zA8Bpg&i~NN(P-Ky8e4#dex}R%Vb#8%70CIOM)26aZ*&!pHT_Ooc0y%8XyO{AO&9Jy
zL4k$B67FR!7m5$Wx~vo4b7Qs%nb+qb9u*$)0M_fmWxgizQpirn%(3FML8x?zn84?~
zTSU*=XiT2y!zXg*#Q0{Ic}Ltc9Od4N6NVyu6MO8^hk*0aN<KZlA*Eg7Z6&SX(KC1P
zNBA)HKpMCNH9eMUj^O*>&n4*!7WzuM%x3`aq)F3}^^;UQ6^;HXwJ(FIpV9?BtC=8g
zu4TZA;m2bekGE)Zicdz{72L+6Qoit|o{q=4U)|}{E~NHsJOC@)E7=GCW@Phe!r;+2
z@%xYhchos_YF(7d$|U=CV|~VwNqjt-O0@b|<zL8(nW$h6Iny8Y&n0E}8rUN8@*buZ
z6VefBtH@ym<yMnD{1Kc>{^sk%o5>TtkGq9z;%g|39Q}aC{6U^4qw3w{;5-!HL&AQb
z_+C=uD+=r*nSFjiWA+ojy{P5@xik!U4ic+?sXVg&FO)w-rgN|0Px6UxH6JF|+N16x
zq;(X^A0<EdICG4Yx`uF^#P&g!6Qsdh)OnKp#e-%4A_)eBQzUN;>O4(~^G<YzL@Yon
z&XRhWd?oK3nRpBZ&y(!yn0tY|alzC@(&!o*bAwy~Y`UBHyvO#sMa~t&l5P_h?j_$L
zO`f9_`Q+XPWO+jT%AoG2q<0Twc}7moLGkBA<Ew)Oq;(%u{epbrhcsW3LcVeNid2u`
z=Wn*smR(WXE?R~UB!AFaw@}R<I+ic5@1rmqS@USbV9Y#B$Jntl$LL)?<3CAHUqZRl
zbRb_KIY*Chck>dR-30}1(7of3<pI4s6-~<$R`oGrE`B`g^QtbUNy8A9(99pZQFbZa
z#5FCWH;*EB4m}u+MK7mwvark*^z<Z@TS?hjv~Cq0AR*^!Itrh5IO^<<#8TGMn|)Aj
z9X);p1=iD3#ZX`aJ<k2~jdY3?IXBS{w~;fKPTP*0n`tlZ4sM~ZGd-}Rtu%|rGHs)=
zBapbA7V^u_s7pso<<UDUP|YFQg)jM@qzy---G9*@x6qhVRC|mpr|E_m6u3;Y2V(J8
z=nx)0ewA+AiK%O}fNv(>rS-zGp7&@5pKaf#qxfRZ1DZD~6Y(Ma!Ixnk(L8>v_AwnY
z2nC<e4u7FdPw9;mwD1{y)*ID4r!V<ZaRHrYLTxYTY(7Z8q@ODz=PT;B4{5LI`*jGP
z=t%C~ex@gL(cUjKg@>qqrQUos<r}^E2{XS_+bO>P{)299gsg=$GaHGMgkq(zy(SAa
z`MV}&3LW_1HA}eN0c-f1(6l(RED%0C#ME+O2VdJ+A;>*YV1saLG1|0I7|S=Yb_k33
z&dW}r_;cjkCtTv;tNVo*zASiDIC2H+a!mLh!q;Dp3#P@$dS1|qBU}(<zCv|TIDQ#z
zx+J`}BkSM7nHxyEEPShjv@61<Sy=8>!FxIyb4_Tm5(~U8JROHDH-ss1Xv|GvnTTfJ
z5~{pH+HK+6CFHy#6!HL;eBss&6u&F%+K0+A?+Mo^+V)VG!?!gb33vIV^0CmB$Fx5Y
zwl+e+=fZgI9~B4#dEEL7!FmQcUkXFkqx>s@yh3;@v@)T<JE2+!)csy4xf(ft2)R>G
zb(T1vN63y9SA9X+I5Cg2j29z^A#FmY7|7RVCyGsSv7%E%(G5$QDprk0^QVhbU!pNH
z#P~H>i(kblya&z{-|#zUmgqkeY3s%M4YAxEqHqWW_KEKfBIgnD#6^VDV&7euSs->8
zjVy&you_EU6nSj`(x%JT_yYT{a%RwB<e4vzxsAFP%1?Kp(na$9@t9gHpBauOE|KeQ
zMOZ4YE5LGdWPfk8cZEDI3JqN)Z?mA%HS(V#H%4wY6*D);ejccEqwLLRWt-$Nk5DdG
zet8(Hy+w}BL)a?sxrMMz-jF#`cdb1hc0%qp&G?k9?N2k7*e=nA-`j_FL_<@)R79&g
z_(UO3M{_Lx?Y5d9%jh1t5Wn~E?1$fbraecVLB)CWO?p%*G$ErL_Y?-F0RA0P`ytk8
z=xkoIkzM$v<^&>^;QOBwiQzOBH-j`v#Y+52a$Qi(Omc)b`Yht|1g)P<78$T+3&>;s
z99>8j^E-SIY0F2X#bop|-b~~*-{9IxhU~}E7}>)2%=eSC+=D($mS!NFB)9qe>l|4Z
zh{`S#f{Q?zII=fvj>-F^!&9to0a^6|E&qqa@+Qcli9uN4Y<hz4E-t5wru-Xl;_ZhS
zv&hhisCPDb8HAz>$Ri%=w~#EVk0zsaeB*dA>Cab%R*{67$hn#njzY*K$^6LgX7VbR
zk3U;Td*(3xGvA*0gM5#{)NYc-1HAT-;Afb5m~7_}1xLu_msq>gB!oXO&JY(qE4f0B
zhGFJavb-TG%O|HcV(Kobkd8&%BL!Qq0=PSofLb=viaa=H6D|4@P0OWiV)*&X%{28K
zvTmV;|6n_8r9HzCw$V)*!gjha3#)dDmf>!FKHX9Q<(CO9`Sxm#VD5>u<-*)ESi}n9
zo`B`96e<T{!>tl5{EWzI!KFOPtr7b1p1fArI1pLZ2^DK%1=kDP$Mg2zAbhQWw#^iw
z91>@VaeU4=Tb#?Evvb6N;aJhR;&;B1IZu4}JKB^jR^UVOd~q1}89<!IgO`63Eqs4+
zfq0R}%`X(+Ct|sa#1!sjOq4U@dF|!11F_uAazqJC?U46z4?T02yx1Kj{*XiX8)5dz
z@^<7oAkX7dq&)fBaAf^cmOYU5A30?aa!yxHtjFRvDc_4?=5giGUQGR^q>e-@E-Mqg
z_(K*y&uCjdJ$gxdFtqC}eZ!yTA8AfD8uW$k=gUl!g@-rr`R{b-P9`E-M9LPtgiTu)
z!NTL_{*7ff>s1_cns4Zf(k&9VVw=RT=SQ7ey6}TN2|HJ#c>91an4dE28~*JOvmI^h
z81@3c+f&wJVV(YNjG8-FPeQ3)(}MAP?{9n|CH-4lUjK~jRme1I-en|=PN|1t6G<0-
zkZ=-N@E1}h6JH(!Glc~5>DE;8j&J5{B0KYte<wN3H<<R2X6LZbJhD0xX~#&HrI>k|
zl&~ROB%}7B>DS0`K4-i`Qu8tOh<uhY^@4P&&*NV|lDa2R@CVuGj>Pe_aa9zYN`<bv
z%i^(spRJ4PQxsbw`V;SngAXZK?@z>Q2wL%(Oe~LDzLD%&sPsGOxfR8KlAruQPZq5j
zgPG&0Pf_HYKueuQO_OO(CKfb>4!qCzKjzZ*J5cjH`q+XJx%5YOOzo%7@9VzyIl65j
z=3Jw*W}}Yl^l3h7yg_%{usv>4tpf_(qDH>o_n7vLK+Y#LuPUaVQ@68dR{?$Ch-IK_
z_~iLD{YkNLztE(nSc9)LQ~edK{YBVSi14cr!cg}dp-cu=a-OhqDi)C~Xtnh*+H*Pg
zw%!x(k*Mhd!B-da#w#%n%lwD5pO01hMC^Qx<}(>v4>QNpI^7)AZaoUioKCCNK(#Yy
z5ANk=Q;)+ao;jap@u?Hg6W1_z8C}FTOmnDTUra5hgLp&X($s5Y-9SI^^F15s%^E1M
zi56LgChw#-49N03-SG@l`{{Q6%s4<Zzhg<qsKf&xj??=iu#L{qReWdYJT1%TGB@aH
z9w&A)lPb4S+btTw*WPbaZ$8DpLmO^HVm_VC-yVCHYJB(m9xcun<?hp_{B0=@sI50v
z?HwJ>clX}Y1;-FR(4OOYlhBLHQ0^b<&-eO1Q#0S3_)0ZC^nRlko?>deP@ygwGeOAQ
zR|a`<gy*;yjLy?c9>aD}D94uxt_pkkeU&ftd5J79g}Qu>_fd#wiL@U=gLB9^QT%Hu
z8UtdpXjHmUOlpj&1LD|I$azl0j(~=W)z>2DCvlf2Dw`(F<AYYVH2*oK7D>}G=b}+7
zBrOi>yG|NB9CH`TCHbn!Qh5Ylc3vh2^0oUMd2S)L%zAkg-w@j<|G`(wH_0*|`!>tF
z_`tADPP&1qUGkaMXa$oicSC{Qa{5%XVy|4U1Pbhv-}1%l19BPuvp9M3uBQC?b4X5d
zMft<>EFY9VA{V%!;8FQ~GG?BX{r*IWGjbe1*LPMP)*g*HC*K{5@|WbEEA;tp%q;Gt
zHy+KW=COTCqI{FJDvCE<-U@T#?7yH5&F1kNxcQ$;P_%{Dd!)vPUdTkTmMj+yPH4$p
z#>B+$SofqML0D+=(~4MFt2@)ss@4kM=5F(8JaV=Ty@D#*6>|T+{jTn)IwkQDQako9
zf;QS~n^8}vmCrDzv%pV5rrP-~PnYrhcvsglJY*#8!a+2#n=Oz(|GMwZLDn8~_(pWk
zy*6a+bv+cn_bvn!=u<2QP3(IMFuz~oBFyREwJ9nc@Rd6z1KZw1QwGKJEy#4=DwsdC
zbpn1L8CD1L$C9;;u^v-MlX|Elk37N$g8}b4gJ8fo5(6dQtc^7T!GD;K|4G%Vff4-&
zr3EGq>SBnfosyV@pJt&U5rb3HVk4vM!BvBUss{g$yp#cb26yk-FFgg?6q2YiLwoiM
z4dHxMgQ|uEg@guG3keOb7F0bYqksQC=_#o_`vq35nmvM+Fk?~weqetgDH-_xw>&SH
z^^>?j;SUl3NraXH_LG$TzqR52SpENO(t3opYhdr1)~)m4J{k6m;RDjrtM)LU_h?Vg
z=-RVi1}5;ypPtb-G^ATtP>o^3Fhl%LhBFCQ2ptODDIHA&ctoi`f+A2nXbY(VT>$MV
zwSYpY6@o;H{t(?2B$2-Ocp*f>{)>fSPy1>hlBuaARc+KqBKH491b8OWK(d#4OSD}v
zIQh!#2jvc$HMXoI^%Y_86v+i%ho}m>U5Z{NaKE4G4*An9Zg6V4r4p1^jlS$&8S3W(
zf0mNHV9-2MCCDnJicqE+eaFJ9(|#&!A0)cLndg?7>|%Wy<qqM|iZ@jLMXL-yjZ}dJ
z3A6^RN|9~QH(n_Tv*)SB*s}!Mkq|rFohy`vnrAI8kkgo&V9^7~2&0l{Cs;Z}D#yMi
z(a{nV%n^gx&~~&ZfgUf7f$+UO-OBE!&=(Sv+NM-tr&H-C6T8uu4l}`zO;Q~;Wf+YS
z!M85b&W)m9O>#tdb9;0R@Na7Lfq2;{!^|xfm0g`oTUXZX_QaO<*haBQcDr8?tFn^@
zQ;-)~Y%pT9u?*xTXr64wE;`r<zqgiMSd~1gXsr1eI!1(Z-()i=7iq=$PiPf*8)o(Z
zzkO6;JulLM3Y2T3xiawvU8KPBa8oh%_dPm*LiK!$yBgm=-LHH|NHQDskWQdbvyl3-
zDo<#vz+OJ5(ITArE-I|uYdT$Jw$HS@44>9%LC|`LMT5J`%o6KXNIT1(u^|!m7U2oO
z_VCEa8g_@y8p-UtD0opAxt^L>T}5c*&ZZU<{3s;c);yu_PsyU#?MboCf@?x&LH5e_
zRZQ^sv211ezQPunT`VO`6I^2AV_Vo``}NF7%osGdO9td*n~Ffm5u&>s)g~#{9tCe(
zOP=g?IiZOK!am71);&yE;SM3AjGoS_RZFhGsx%hn8zCbX4bMtIn@_Y9cFXX48zG*#
zwH1CNkl=4}XFJ;o5{2&PMGXeLwBSWd5gN!Wpo?(S3bg_xD^msuCK<B4RTYwsDQ>b~
z`CzU+V3>ftp@>~^gPD0kQ8sP35G}EXV}y7GwwE!MfOWs%eRDNhEdqY)Wra<jBuuse
zzRj-$s{+ESqVRE#TnChPcpHRn6@I6%<&0P!e0B(Pp_pK?!ho@o2-BaMtHZq=!fx2=
zhKi)Srt)mjPT{iz+eVnYVa(qanVsGvY?C1SccUMq-O_A~<q20+xVBRcV85Oef<<=X
zjIfZfA?E~tv2H}|z~uC_LFs{AIuGhIG%zwPy>~|c0f8C)t7P;@tJ1fB|9*i(`w!}!
zKA>}#H00@5B_l08BOUot2X_b8>S9rL<&xm0!o`7>!1=d?6ELEzQdPFwTPDWG!i5F2
z2n0Pf8=3EIVK0FKS*s@U3kKmKk}q_sYgC|QzAzN7bT_&vj_wkc%;x0_GbsFAD#t0P
z#2%3l0{0eEPZ&_kBC@vkg?m=XZjWvj0dI{)Z^)QpbaP&eUeVZdI{d`mp7>Un;0kca
zWP{h~YAJS$iZ4_cGE#A8PtBq%!txeMQTED3Y;A#Jmz6jc?<@YWun`r+4I*n?RUC+S
z{Qxu46u}*4bd)U6I9qaM4{M5Z2$cJ&*kJ2=#hVSOEk5*sCF@Nl$lY#f20=eXiH&X{
z-gIZvx`=HE`_Wa5CUCEz=EeGS6NkBpSf5}x?}GjQ%^g8CJ9~9xf;~18&fCmIASczN
zFw1a}63`k8{w!pKc+SRLrir%{)iGcMB?QCrNVOO=nJZdY$Xs!>8ETD`OF~Ah><!nK
ziiysFB?MgNXkL)COuP?kTrBP|D+g`smm~I+Vg57Kl@+cLkC|b>6io!zKg@x=zk9H2
z+r>CDJlU<dG5Y~A-i2K~BYr0A<~gyIFTfUyH(boqX0hNG;#3u0+{W&@wyf;NzI_m@
zR)+cu@vhi*UGjmPRhq))_)G2*1dY;4uq$Qp)p$yDVzUT)qt<Y@l2ja~$C+KB|7lHP
zKkML29GGu1{sswLs)D(ldRR)sI2XL&o<qz&%+gVk1z5R}dcl|iNrAQnQZTfhCu*!|
zXZ*nvXnaTUV~IVbrkV+RMPz(zgxzj{LrabB;8RD|U{-Znfmw&*&jCTgFd7Wg9vO`=
ztE*~;>LaB^?CnTg`GDsErXcA40Ehg`qoonB=Ytr?CXK<L<N&tVtiftk_GBfdNGTGV
zK11qO0^B!A&z%h&28ZgJeBiE&D6@9CIQIaTL^Xs}*otm0m{T41LU?p+3&+^TWF{pQ
zW4~OG-nhc_^|FcK!(|GAm<Y*bervM~<$Y8i$a*Bjz+Yda0CxV7)LVkpWwFM;6iB6E
z{&kZpcnvfLu+0UMpg?|*j7KUS;N@L$MsR0G-bq#&)^`xhaIGgc;*-zP1E|pyAJkvJ
zNUl(`m#H)}f0b5<zzU`1|Jr}A0rdgDa7l)$xv~nwe@Y1~|EE-2hSL{l5Ug!wvO<gA
zMiYyX<(3rI1Q@Ha1FAe22k;Z-035qp#D_PFcixPNW_hUM=%~R#5S%CYz$}xZ0RF&;
z%AXakuvajf*blS3Q)CBhGLo+TCRicAEk6JD=4+wsp_g1;gr^}&Wmei(&R1B&((-2+
zXf;}jqRN>qq+$-0%w9<@D9YMI$`?)0MNmB9hL>yte=k~u^=~0JmVo@Bdb0aT@<$52
zP8-WZk*!86b7><FGC`;Dk{2}emjc<+RCx`B)LkgmFipO1V=afsPetd`p~FZyMuua1
z1Q*y*1)rlg#^H#Ny8*|TSx<~2yE9h4ra`NbsvmsH!8&Y7qcVFjQ+9V@O_#|r6s#bW
zU~`ts#YJ{}wcJmFmWxzx$Xa2p%o=T!j}q8YAN|kSZ4^(|G*_OXK=mBa55~3@y`bZL
zO@Z7vDF6y9sxoW%yZpP9T}t(Uaw`;fXfY65^ZYRC!usu%*HSpIp~|2G@*Kk69+Xd*
z)bt+x2W9wG3TB7@l3x?BeOCNn`)Roj`*K=-Z-a(yOr^n`EBJ$btWjn0cjToiG>uXM
z;nidL5o~9Qo0X5nAwkIo$F-~mW5cnJY)Q2!V0|jzhjIP!SySea>dsuA$<IWXSxSgt
zfv;pAyirqRR~Y<Oz6>4Ln#&3i2@%exz^xbfxSa7$-UYi}X;#oKYQ9ivh+2fTe=jr2
z+WjM+EdyR}(LZVGs~i)cMg=W^gn+FAx<`3k(PL}jr?g`?{FIl3T?kOt3(#VWR0eW}
zm_)Xztnylf#p|{55c*9j!uD2DswnXI6RpThp^BTasIx}~CxqCe8`W~UCAE?(80@g*
zGy0Et!|;a5>S!^-+Rr#(WTlv8Hl?l-AUH-!IQi6494=oF+}Pg@l%W#reQYcXBchby
z*!831lB$Qn0e@pzT0M-JqLp$K%H9_|SjWan3|`S0S~&=APd(sF3uUG!HzO)B!JZTq
z;WQ$+I{FRM;+0Vfw7VdMv5MFkuwR@NWf=WbQCP>eO0EiPV?-OQ+#{4?wNjO>c)pYS
zLX8p=66}o<bSEn$6n<`{MOk4N<(Lbc|EQH@x6+kp72-M@jh@x?($GsWg!jov8`Q6J
zMjBj57u_NBK90D4&rN1%Slp~Ie6yBfVpAq5)m<PZUQyx7OdK-~WGi(gsI*8q3dT5-
zl~rA=JU6qzb;>~W%`d1W*xB_;vI1+4m~l!lMD~ZMYDO1k-=@@)!L74Y8T+#&vlUDk
zQXFn}u@qxjmz5JLe0nL@WIgUEc?#^BiOxy+$I31NnpF_daebzoh0D*C05BFPnHIZ!
zXqO(H2iY^wA7*n3lra_$yFDQ)CN?oCD#0F~5EUKUhLZw6E14o=-<53Y?zrZmj!UlB
zzZx6#Q>mk{J+kU8vD;>KF8aQmR2$SCuc&N}RUJv4580aNao`I!@MZ-nL**qV6&;SG
z#0cjY9_^}znb<ZTwFQMs`!sLnS3*5m0<JFBtn)WX?z`%#^C<+3!W(tVOQXc*H&A^v
zSkY5*1K)!<lx~Yt*J97%7qKyf@5cM8;T;kE>+!1F{F;hLqieyT0?fVJNsw7)GgT7U
z{CIUZg}dbxnZ+ckIey?ZSaXHBv$Y~ne=j}~OAOXrn3jPjU}1e7$(IcosRpaCqlTp@
zymrIBG`ThUvh^RJWAtUb`jxVulhmo+ptMm+vfVjq(IR4_By=m@5@T`peU~~*@IY_e
z9u<>dkBA6~arPaY7#!H6_A|12_$yn~(kwiJyZ8y!{DP8MgX1bb3^t|EFm~Xi`hvo-
z;i?r%9xzFe<Ap=bu{jnucI>oTiGtZ?vA{P4+oIP`#SHG})MO}qK&)U&PHbdvkrZQZ
z906p4P!enwe6saFkKXLMb82l0Ue##`6E3Pf2wQeZ^)|9ox71(UVaRiwsm^|*da?0u
z)YbTEG}U-dgY|w&a9Mu+lVU>>>``rEBmMqI%HAx!w{v8x2`x*?_{0UOkPwzt#8}o+
zG%BgFJ+fJNEcUFVCP}eT&ISlgW|squw<$Yc#(3StXFo3RbCKc?SA&d~pt8SK1+Eph
zXzY2gv6cxsj*(>+QP)^kV6z(-x8V#J;u{)+SZtJWtr19y#gDydZuE8$ai$j!t~1Tv
z5EqS|Fs`F<FuKW;%|-~kZLS1m0~IT~WjE%Vy}2ulV@GsCl;3}U<u!rX%Vl?#-`f~2
zutxojM~GMJ){!yjHrtc@{_~A9vYG>p$3$q|O|ru7D-?agDcB|24?))(atiQ~wsN#_
zhY7wgV}M|{Cqsi3qA$GmK~HP@6r-O2tH#Qe;n50<2lJe6%(lR>AkoT>{boGpEAieO
z4aJ+|v#ViMQDwjXZj8i!fDFKbjHOx0Ka5R1;OTZD)aj4poJObpb`mYlww*S97NE&H
z*$*0Cmp#~-^Tvu6hQH3`E5n9hV<-!JV4N<%x*b9-cJHxqvJ49vm;)HzTEPT{Rg`Ru
zzBcwF5H?8&WCPw9=lTQ9!?~-En`w~5j(C}hP?)|)4TH(eRNMSw*e73mn`*$o-KsZ>
zEoQ<A2)e^Ia4#)aVQK!RECPjtjkQ>bQl?9ksbx*x7N?(73j$rZpNDs)66_dIDloqg
zQy;;Ykc9U_Ttc&OaJ{N}o5B<9kx9JIRA9eVGwl?4g*BF5+f-G7u|~<Aoeei-T3nN3
zn<v$@C)p#TBI3dmq9XlRW^+@20m2(vaB^Heh#3=1iv_s&8K<?YlTC}L?pB4u+xJFa
zunm?J_G=r{IThZXRRdUu&L$jD$F>ow73K5c#MZp~I{sF7_TTEstX(ftd5JCRZ>pep
zMn*KlS#x4?f;}!V*~w8e8P1QFeVOY}Q;q<)FqV_uA7MIg1^Phqh83p-FLr0D=?Zag
zoET+q6&{xy<rh*d$nh_kou6hZ6rgfrB^bIN(A=11mZ=-n=k>LmzF}51L1cU8n3fYb
zJyP;#OXit+s4Q%WX{iq+7BPmxl;3cE?Ds}Bvrm7R@I=$M;^<o?+ws9m_L__$oVbOT
zxZ*)mWf?~Js5MxZqb64ss(sX4=9jcckhab24rBZUBc@Dj<r&isjZMC3DkT4zc^oVu
zmw+>UWj9E#WO8NmZ<`umv-arRuU}dpur8Cl!Ir62VwLZjCaExJ4h~%rd#M+@^3*h2
zX2V~b9=O59X}H)k_np~|^`qwfs)o<uNPA*zyC}SreypO|jPB%x2(uUau9<P^AIA}U
z;;?AE7o(FJL)98u5k_6j1AU>&SgL}xo@|86LrekinwcavtcrP}0Iq&Y5he$l*DGv)
zO|zK*ToTH&{95Kc65HFrTtr;^Gy)xz53%N7i^ARZ*wx3Snh*QHnavgxjJzayLVR&k
z88|=2Y=#cygyzt&k);TeGR=!bmOI{DzJwb-F!2+tJ3_(e3Bk?f=IL;_FIINb3iB!g
zyE;f^p=>x#l6$N&|3lfhwdQHIqR!DII>FvLOdnbJcY7FX@Q2yk1|7TLlN;v*9&E}9
z^HL8;zlnXf|829KK=Ze95te_)oNZ)(J~b;cj7^n`LdnGziM@Jd#%tTIg;)a0cB8J$
z>%BQch33soA?)loa}z5oXR=%-Y>&l~rLqW5%M2qkm9+Gruxd2=$7!C_4VpfeJz>9Q
z@qwNGmIhEO3?1)M0hVk}cz4|5%}&*@1h}x`F_x(c>^OrHp%SjD1zx#oI9>HeH#Bb<
zK3LB-w}fhtQ5IJOQ)=UcKCH9m!K$TL(iGShB^QAYNm6CDwToq$$R_l##1i(srzK8;
z`4+_ky7jm0D(UbyV&k|&5*-`eA{g)CVa~fFC>Z@N*mg|yU_k>cD+nWlEPqMt&QQyE
z4|o}E34-+LmQZN%00*ZTIcnv9Cs6a<L?1X9f)jueGc5aUVC;xXMZQZduT}6nuKKZ}
z_-kpZ*|Gi=+bqG}ECIHi(%fOH4?16)wphMU_I<nM7c1U{iIL%v5wOiB6opP*aL%p%
zX?ZSj-%z!L1Uc`1boMJSuM?K<5{o%&Iqm^5Ni+cFry6b0e2zt7^&VJ8O6>7dycUpA
z2^SFh7FfpMoM5$Fl=&$dI(2RRwL1#DGg}V8viaDZ+g8wCDWHs_8kGD8Cm$_?wRjJp
zHBG*7Y^7#{%t`2RZ+$F!v7=F1qNw{sj#ZuFaA%|0h1G1LwKlPZNm?VtxzhV?iKQaD
z)n2PXS*4Cz2@!G*Xk}Pzs@73utd|yS0(faG3f8rP!omh?-(}W(l(vCF<U?8;)=am!
zv*wxFLk;$p6TIQl8FWkf&(Nm$z}JOJuydHN33*?XVvzL)Ct%IjYt3O0pHSRbuU(|D
zYm;^WBATjhCTEic<8@^#bF~Z#e;$+rS@2eEi3Ns!!6n&$_GudkY@cfKWJeEZ9|$bF
zN2{^aL)sD>g!YvDVCpw>6f1X8n<v8T2BIg-T#wUvYX*8p176_D=AEv%HsEzto29Z>
z`I-kVUEo?N3wog4mYCl&?YW@fkP;Uk*9sa|5$nULL%1}v+|%gEs=U-zs?e<fS3e%k
zM*n{4?>MFJG#Y2`<^It&OU0@M*Qyd+D=fHzUvO~M(5k^W$qNYysu3JwfLGtNXc+Zf
zb0wqU*Y8>>lE`{}*UAzy0cQWu0!a`%^h1kKn_w8Z!Oc*~kgM{Ae&;_M!d^`C4JF**
zM0yp&ng2z{cbGZoPWeE?D;37b);@l<!fI8k9+VbZy;g8omu{VF)~uNpTq86nI5@Ry
z*BW7I)tO1LhO3b7Vhw=xF4js#N@D@0c?QD}j&lr#07n|A&05>P3Vx>;1{k7aLme@+
z#gQKe9m1?$q#Nw7Xf2t^P2t?xI<C<X!(try7&7WW6V{9KVeEqgF*w$N(K;sT*hxnW
zOLEYc=!k)5j`R~9eQ=Ki^<^3`fWSehreh-=JL=e5M+{GO@J-YaLp&YnWjb!s5rZln
z`Nwp`m*F_lc+S&-9dzvFKs<6WQP22I$JIJ+*Ae$C9fFT_e6M3E+%)1Xg2z!E*h0si
zI%0r?BY(V(vvgddBOV1e&`eZ-Q7R6`BRXEt@s5rKI)2ts!o5shu$zv!AMHq2*0Gk3
z(K;sT*hxox<Gh0(BR&mjT+uu|1K%CuAZ*rgpN<$f>&UO5V*?$dbi^HW2fdw+y>uL)
z<50-;u$IfjmjgK1aNpK}uXOyTBko!|@^QD`fdM)O>R4At45V_<Tj|(E#{oLxOHUm1
zY#kRlG1IVI&seKtu8uo&+@s?u9q|PZ4n+@je5+%jju?>YpyN9u9f)roa$ty#4Rnli
zAa=F3dPX-LF;2`OfbXSnAfB6X;2|B4>&V9uexWYucwNVQ9r2wr4*E|WEf~JT`SC?D
z4lK)&cQt%xr6Z%Ej?Hw$WB88z?mA}ZI95kIi{zj$(s8YhJ9RvyBfhW6!H0(}9Ed07
z9Eh8rhD>ge3x45<VNMRLpks9%BXn%3BgWS{`0&Jm12c3Sp<|YglXRS};~X9FWQ#*?
z1HSLo@nx@`aa_m0b-btJD;>Y-sNxY9Zm_407((hu<GU6dSXW1UOS&VCN7EeGMaKa;
zj>dQ=2La<_9Jo=(qdMm6_>iNk!SG&BD;6ieg`?GA@X^y1bgZH0N9yTBJ)NSb`{+0@
zlYc>_S$f7i9T#xKj<Zfr@6z#zo_|44-__I4^z;`U4I0YhNMY8oC`W9ua(X&QPfz~t
zZN>jC?7O$EN07fazll&Rgd-M@5vUIH@Jx%No?F<&Cbo2y%z_IEHg~Wj+HClX?^c5f
z{)x6y7`B9uStlullU_JT133wU0}Z;=rbL@7QQ$zLtt<vV{zu}wGuxVED=R<5?1mcD
zPC`l5YOpDgnq&)*O5-KC4K0(g=*3Ak8zt_r8QH0a3tZtC?hb_<BVC|uGGae>XwI>Z
z3k=~{*Atc^YQC;kLl9mzJk^2rj!m}tl9KR>Q{qZuWw3Bgsn01sQf7d`P!(o(vX!<3
zSPdAe=^!?A5_6Fl2;r@4rL^h)5491vrr3N%BnCjZE?HiejC4vCBJo$J<O`I{(W%jJ
z0nHIh84N9TwWX|vPCBu%LzLbw1!r5Mu`iH>@wg6qnmD!IEp0ILg4ylS*fLhb6kRUP
zNo-QaV919Ht<l(3NaYWCUeD%EYK3w*0yxV&UCwIo(`DnG)F`B4U3f)bAobtMBsi(v
zk$T-p^(c=ms2i2!pwforVRKvF>=mqrVQ$VsTR8>$VtbZ!nl!JD)i6L8Y~yGJQVW{5
zLpiaY)i7%oaTwdqDQEqS82UO3oOi~>FibZ##aZCU-{2J&w48M@WYu>T*wHEY<t#B|
zz`!=xKo*-}onBri-J0{nkmA%DX0;gx=vq^qT2G#bJMB^HDkSCMNW|N&D|Bv+mkS-K
zLb%r+8>g!`%Ha*oiQSx9Lome3lh?7drL@h^MlZ65lNj@eU`KOYlgednh8{Y#7i{Bt
z@l?oay_V%{hCg(B`Zz@^qT80?6pbs7Ch4O6oYbXHiD5FlO-7q66>WyQ`o$jLq?Rcl
zxXs|aoRzUyUGpF~)C!A5Vs)ozQWcwFmM)s%5T$!w!sd?H3=acsh8*;Mcuj{mwVuR-
zsg<1;O$ht%$_#T-KfWV|5^#^-4%LvTYaQVvx_>19-eomyh9KRZQBGnw5{v12k@{~F
zj&V}k<5}}D&br*Hh34wASx)M8q)v5G`_#4>e$%PrV0K5W=_g{ycGgs^V>7(bZJOW|
z{e%Z3syK?JAL>D?&NyC`#;EAyFt)R;6dlz7)?k)gK&c_(EnMtu3!qg$z(1HrGd@6x
rRK!&cAev*{kI)ZM8t_pw41fixIIP_*#85Xl#J_%MV8fe`4{QGgl99pj

diff --git a/Debug/Core/Src/stm32f4xx_hal_msp.su b/Debug/Core/Src/stm32f4xx_hal_msp.su
index 472bf1b..5f2442a 100644
--- a/Debug/Core/Src/stm32f4xx_hal_msp.su
+++ b/Debug/Core/Src/stm32f4xx_hal_msp.su
@@ -1,5 +1,5 @@
 ../Core/Src/stm32f4xx_hal_msp.c:64:6:HAL_MspInit	16	static
 ../Core/Src/stm32f4xx_hal_msp.c:86:6:HAL_CAN_MspInit	48	static
-../Core/Src/stm32f4xx_hal_msp.c:122:6:HAL_CAN_MspDeInit	16	static
-../Core/Src/stm32f4xx_hal_msp.c:151:6:HAL_UART_MspInit	48	static
-../Core/Src/stm32f4xx_hal_msp.c:187:6:HAL_UART_MspDeInit	16	static
+../Core/Src/stm32f4xx_hal_msp.c:125:6:HAL_CAN_MspDeInit	16	static
+../Core/Src/stm32f4xx_hal_msp.c:156:6:HAL_UART_MspInit	48	static
+../Core/Src/stm32f4xx_hal_msp.c:192:6:HAL_UART_MspDeInit	16	static
diff --git a/Debug/Core/Src/stm32f4xx_it.cyclo b/Debug/Core/Src/stm32f4xx_it.cyclo
index 1c5d501..ba9f3c5 100644
--- a/Debug/Core/Src/stm32f4xx_it.cyclo
+++ b/Debug/Core/Src/stm32f4xx_it.cyclo
@@ -7,3 +7,4 @@
 ../Core/Src/stm32f4xx_it.c:157:6:DebugMon_Handler	1
 ../Core/Src/stm32f4xx_it.c:170:6:PendSV_Handler	1
 ../Core/Src/stm32f4xx_it.c:183:6:SysTick_Handler	1
+../Core/Src/stm32f4xx_it.c:204:6:CAN1_RX0_IRQHandler	1
diff --git a/Debug/Core/Src/stm32f4xx_it.o b/Debug/Core/Src/stm32f4xx_it.o
index ef38dd38a9e62f35e31c9758f7664cd2fdc08301..df2c03701ca11a5d9bbcf0ae6413ce21c96c6e0f 100644
GIT binary patch
delta 285100
zcmYhj2V7Lg_ddLLckkZ1y{U;^V>HIzqQ>5h8hdPs8e@qjQKK<2#sw@0iUkC*AVowe
zqF|va2v|`-Iu=wE1w{}973=#PlHdRR=40;MbLKqHIWxD-oSEg?n?bod2k&fQmb)4h
z_>b*DN5$s~Z^iDYfoB<kf#in&-M#9W=?<sUisQ;rA76d=s7P`;t4JbSfdx##sOj9`
zqL36#hd?!Mm7tJG^*{fq7|orIl0wDszcmpQDkXb=r3wYNCz@BN)a;6Pyh7b(7pG88
zXgmWjm6{vXMX6Bn>{l@`;JJg2JWgR$vrB$mMU_b`>=!&`6sj(kaj=)y;lR_u5C03R
zao`l9L0wQpXH!N`QWP1t;8ei`pJx^7n+<}Rne74LR)fGZ!&gAK-5|&c^~+B<h5C+)
z=)m)!r31aeO#)Hre?)g?Fbegf|A_i_fbjS~qMr>A%KndNgpX38E?1Qj5wETqPdp<g
zbyZaV%Y*Z7ikg3E6zaJn1%>*B>Pr}zTBy|Zf|C;F<AzRBINmmEXaF~E@+8H(hI2JH
z1?TS@&Ut41C6z+`p+S(D@@o)2HV6i3^zcb&IH4`la3Gk5^G4E;DU%e+hVxI&D|$)_
zwTfv*{#q!Pj!`Sr%ubv;G0I;1lnRz{1VB2$DF23`hB*Nti?NItH%X!9m<B%zrLsH^
z7omYrtyFG;p};g;7o{@fsHhMdYGkEy2Wq5-8iP`qn#C#Ph8l}fxfeCshMGo7Wr>zm
z=>82)sXXLBm7eiHBU&hxb=4Y$fk{RXgOvYXc8ay(vQJm=bj>N+1{w7&(VG--gUtME
zPuK=oQt)(1vi?v0L}7ijPgJOljA|zI+O8mDlj@WX6ds;Dj(;3s6u7{Xvn2(aqPhd1
zidVNPWB#?(bnc^q(bgLrj&0tf<Jl~YMxkU&QbmP|U9e4|P_yn90nd%P?O3Hk(_6&@
zAQMXbRMY=HN~Y;^Mxhzda8oOoYyUtP>}ZhG%=h~s4g2?gXFU3{3eBhnL1uhN7~3Ei
zm@;_Qj5pUIIt%kb#Va%u8w4wp5|0Zwr9rSUql+L+ZxHNE=u4GCGqXWx#5Ab|W=@09
zSfSQ0atI2|T-9hqXA8Q(Dn8d_89L*+XU47rLv{-~S1>JFgCVy$wL#5{a|a~9`7j7A
zm>zyGD{M|TVH<^xdRu+ejQUE|Gt}Eh>{Bb4zD;_7rO_=J`Z%TL2MCSnpwL0@P&64Q
zs1;n9M!))jQgIDxg$4gJ2lV$=3yK($>7~OQ(0I=j6k#Om{*^Un)D5qN|C3uC)hKrU
zPkqldDupx2nt$zg=W~jc|0DnTm8kd;*Z=<+FoQV7l>d=SIw%#x|9@G*Xca15U#Xw;
zl{DJiM^Y%14T_fPe(YB*n?Z%wrmBrXk_JdB#HhCYk2&s|&mn#al%|tnU}F%qWWeOL
zR;6=r;Nkm%=l?PD3^Urym~k_=RE#!v21+zDlGNb5r9c(Z|6%^~4HLO1Y;kX^nE@?1
zsU;ZxwP(m)r&mZV)l{$lU;iyN?HYTnS7{vU8slAWWZLS?2>uh@RJ)Ne*#ELC6vqEr
zglEKr7}$S1fGExX^#}WZ{b6Z{NkVr}2cb8t|8+rw0=Jl%QR)6`g+vVY9{<-xeSsL*
zxIcnu)QM^6o(7tBP?2F{wxMZF{tLa~8c-ds&H}G|)hsRDGynJBaIaqK!45pAbStq6
z+?06P(m|zQR92p~bNE=OnsKac=6IYm75=UCQi`l)#&;Tp>Jy2z4c?2dP*e8bs*Q~L
z-;)qVW?LMpg-t81O3<;Qj~(ATS;=ZVSbYC@J!|7T;CuL~!Rxu&;xIO#)GD3o-;;lj
ztoHJ3yvJ1oP5+}+1u<r}$-o0(>0<d;|DVsJdh36<O@>Ea^gchr*x2Ts7;yYAfxnVd
zt5wbH|LRoD8*x8TqyMu}HE;Ys#%k3bWs?S3mB-+d_&;|0m7o5{;IC}@ugOPsGuE0B
zr1^hbhm_6#vk6yfyvo?-%tkL>)5Q_=J>H=I)~Hps&sf{=yZGFyaS`y3f6wBWYovGN
zhnpH4`#xfD9G^%ATfW2RNO9%0h~vyRWZ&!w+1TDu?Z`~Rrmv&gZSzR~*<l{XZ<Fx0
zR?Ip_$N5VfR9x^Qz~Z0j*sF{*cem5|v4I45o2$ZcQYh&^aU;6tEjb)pGvpu@uWMEj
z-KW9*TMB4J0v*>4B>SBq#Nd3IP;YExX{{#B)gS3xIL13r+#5pR`BsAUoJX)-+sM6h
zE=Aq1j@-l-671v$vV8k9X<GeBmWlnTKYUZEhvdz~aPlTuF1boJv%exu)Id6Kc7<Gq
z|4R0rWyD|mxl-X^6=x5SFt{TfZ_Op6I{MBl#`hxk*&~T=K^-{`Uq|i!Y7-qtJ|m4&
zbF$3(gKYZdP!OM_Q|;MP#1q+(G~QKI`(`+u&s$ABvEn%ST5<>c4n_V%YKQmy2GcfV
zI>|`KY(Fx6bcJHyK9=YnbfR;40=3}EHL~yKPx}4k6bhe9_7@kCzQT>dntg%v8%oF~
zr4@NuF@}!aACso}FLdr0i6I)Ruv{iUPdl}E;}dc-tDz5SGsvigAKA1XMPW^zL*VOM
zNONlmwRP!6(qx<_%lcqqDF2p%NIyZE?IS3xe=11Rrr{2&!2=7Aor&R|<1EFP-p~%G
zBjnhn9ntB&Afj0!x$Lrw^kY`gdF50(PJd1s!x}mt+7RfUcA|T&CudXBs4;V|)A`-&
z6r!9-p<Jmao38jK;@ZpP<xT>wKd5(*>9FHe-J;<}+u=)L*)r+q6-%KMH#|sxyrT1@
zW@K4cMCX6+ZfL*`a?`~?j@vg}xK)d(Hlz!Ms6WwgPlVA`@9{NxJoJFvPxDvN{r^r&
zMxRe4qVk<|K6Ne~rKV(beK#FfOLUAmPBzaHsCGtMI`6TNNI#!PwVfN<v|uhdwr!;*
zEtx~kX09SlVGBaN*OBJ3mTH^+iNOS`2p&nD^IH`W?JlQtAIw2O@rX#XJJ7kPBtXS{
zBKrIW>9;>1%j|}?#mWZ9<DQVshxMdCev90AccXTXz-$Qb6%5L8JKv$6TjfTzS3d)@
zLvb~cNcU)|HF0V(9fq+juGtmRe_c$Z>{aU6Q&n_+NJA7G*O2CmhHl@VN9Td~tl%Yf
zov@zXWI1j&ohLt|THj!Dx%MkMe!7Xge7TDBj!A9EjiH8a3iY?7I&P%nUo(iVU_Bk%
z;uC^<RY&?m3FQ85!?kqlLG4>nNj>y<JuxiBrv%q~25I8m$^DEyqzMQjO~O`kUz<rD
zn{vcF(Q%rpmvB_QGld+;<LTIOI2lzp1Tid$T;`UL&B$$ZtScsJvq(0{`^fR{GM)de
zr$GCsk!EBeo$m@Ktd*zZ>R05xFrALSIZ^GaWe)17CznZRf1d6D?{Q@6Ihn!=+eD;`
zn~}}D2Af^~kd0>@>HB|8Ex7Ru)iw{L;~!TkxZxj2AC^N5_J?GDDv4Y^YelF%tEqW?
zuaJIFyN37wIvu$j=S)F_Hzy;vmUMI;OmwYBP+MnCCRp1Aq<{4}fgdd=(v4$Cb7mGD
zZ&wk|&pvd%55rcpbuw87BoVf}FNIk7lFkcykgw-|sp$S+=t+S0v#Ha@Hzk*&|Df~9
z>xs@Uf{2EGMMSMI^<@>mG(0cbD|CMN5Mg($B2<2JA{`Y*4zBf}V;7lhmW0sJK8lVb
zP7vGk?!;!lg?@4<KA6bVF@cEARZ>M3o=a9?`ie}A6RDN6-_p7B9O}~VpEle$4e!Ub
zC4?>APwsOfh~ejBWS?|~+S)aiYTL$=V~>V+DEE$d#0SKm@Sac(V;>^*TSx%s<pe0f
zbRLloB%-{Ac%5A6yxUVcHfPB4{0|gF&r3v9Hl0w;KN3%+f_m=49CGu;FQj>}jZpo+
zq`v7en)FxV>9`EzQ;Z}X4WE|ubwm`4*##cFvvf?`LJm%eM6qiOok#pe?Q4eV32w%}
z$^P~CL@{I$QM)$0*M7&qRikKWBhA^~bY3j0ah&lRrf`Z=moZ^f{CSi(-L_+Xrf`bH
z{jX7U&~rEr{+8PPg%5Sh!(9Z3?@A7sJaU}Ya38EK#XMDUqlj90Jcoi<euWsWRS{|Z
z?_{~BoX(@QbbQT_Wu=9flQ3x3D7O4WjX7x{OGQ1dKdY$9)}Z19#(i*KP7Vh2BGcE?
zDaLExP}C3GlbcC>$ui1|ddRH|lU&8x9%SRUpN=u#(}jqOAqN=^Bfhy!sJCkI64NNA
zFD3nVJqi27PDdLCH4crUw1i@rio05)n2AB7M$vREx%_G$!RqjO)+pX%o(czDsKr$c
z<Aa}qiTVUG1Gp#+_k7b`)a?_GVp>Im*T&Tg(Du)kVcN=e_@*~}44u3d=Tl1j(a@>S
zUZ8f`IEOQY>GRwG{mx?&;-4WlL2NT8)2;Yp;8L6~+Djjq<%{SFuQ@<NOh*DHh3p1q
z&0u)n#(1Tn@L}%Jcw-MUtpY*%GEy3(z0B%WDE2Y^9s#zWshS3-e$2fJI6cV7-8Fdr
z{h5nFzy~n3L*Ois8JYvrAjWepVm-wCK;MdBW(^1BVP^I`C_|Xg^>A^7IZB_sqs*MK
zU<+kRx_~>3={FRBaHjQNxQ!y1a}Pm%jQNh<+L26X0^r9PLp+oxm>$g_Iii>*XVEv&
zOmjEjPcmu|m8Y2JTfu#r>2nW$&oC)8NQ+_S(;GUL`E&=^;uxn8NbyW~3fw0!1A_ri
zWb%(dd6t<*@7Ht8U0(!~#9Vj{mSkomy@<{;<3nMY!nE^)`&0+xehlRe#*_SJGXs0V
zZw~W(20A;JxxO3Rd5q~C5c$lI1O!^dlurToP3C$kaJQJx=)HEEd5W|jd!On46b>IS
zX<D$9GR3X{JZ7fT$E1vD(iqAL#&QU_XUx-jD61Gpr*g18XG-hQrfTNHPtevdf4)ZX
zf|-9Gerp*$jd$vpq#;ngWIp*8fLDyF64GmCVjBedhH<R~_giL24I286vBjhABXhYM
z+&e3Oq+yhca?dVAxK(-Ly$JvK_gO!Bi8y*Z9S+Q|GwGfC+lo{0wA_0%+^%@O4CgEF
z4a7W;%v+uQ3>KYhe?tSi%-M%yR~c^@wp%J@d~A0seV+oDpE1*EFjuc>jk`(n2MxQq
zADe-Y|0fI@p&yG}8WFbaMjtK5=XrQ3YBn%e-+*8vvlH)l%@)Qv9?f!N`eV$dac2f0
zHNtLXG%fLP9%L@l0M?&zx&xC}O!z>A^`3cg4rH5@89%_%U3q6XV)s_Ip~28zrRP>q
z`zzOapaYI8>wg3;NojHcE?wy;sm0`z;?bX6hKeR*m%*xK$VAX}9_|YL*T+7h|0ZX3
z0m(1wUvb>V_^S~@2-9N$Y!jJLYthIIro~CTL24PB?|)q&a^Hc_um+z2%@?h1pp_j<
z@p;gE`Ft&2CY@aW<`v4$4oYKdy5u1Bq3OE)9^O0M>Us22_dUgELXTVf(78STK#Ga&
zWlBQCy^Ti^O`ijaIDWN`Mkam#xdQh?4bG??^LP&eo79~?5_2B5fX(8<q2O6j(+0JF
zPBcO9%%r=caa)+)%fapNV&1$2%O0khg-H+-phR(uNz#Dy4AbE|gdNK?L?6dAgdfi|
z#Gk-4G$4^_Xuw&9qSmA^4Gl?Us3i@(DtgzW6RZbvact~Qv3#;O1pZon6N5<G9(MeV
z4sB;_ijMqp%M={DdU*obJsmG!_N)7g5zN=lNb#`)-IpMuVL!}7?4y67InwyuO3+R2
zxejSVx`1{r1C&jdb;Nn=tv%qRz1v?n_UzFS&Ic+kLO=RDntD#Q(nIIOxM&!Bf1H_X
z$mX&x%$nKo@5?Nz1^HgaZ380P$6TiGdJtpz3mk`-ZO;J=W{%J&F_I}G+;QgWbND^M
zER|pq%dA7r6K|*7qp*x;M$+6qjj8zqfD6p*Q?R_q#D$<KxlA;kWCva^XR_copIP$-
z@Q)Zb8vQ?J@~*?Qj9IFM=}RUw1^8FYn$~dmni;YI%FW8EPhjb)9Q+y%w<tH5q4ZHI
zKS8la8R`i#U*&bI+OQ$Yu>l}Eq7;5b-BD%0R4C6VxBdYWM~t#=B_fSgei;WB7nKuQ
zp}m)s1KyxAQ~Bf_iUQ?$N_gB+wxDZPth`A05~WWRI`@%sKrN)F%DXbU>!nh)0&Q_p
zg)alyCRLCGz&4d~3oJcUrTB=lzN&kL;M}WPhGaY&>`={L1JlE*f>9`<R1+@3Q?zQ`
zVvwF!jUNkqifRT1?hTi?h3`;+T7UTzVw;s6(C)VHRwGwS)kCIXNW%^--U(mBR>$Ie
zq}yE_7oAr8cP}=Hord<epD_=l9j6rF*tyj4If`!SEkV$88YMIOd`fp-zZXlO8PM(#
z`g`!X(Fk~0<uX`)vt5bflqx6aXD_F@*@7o8P`m8)ARK?YQU!*U3CJ3=37YxeqD6_C
z^R94uRueoLRcV?z)Ud0X=}OdPYx+7n;H*gVUIf!MZsYebeZd{<4;yD8^gY_TOE^0a
zrl)ir5}{1c&3*~by9|dWLE3Goi2m>1k7Q;)LtwX<Uv9w79j3f7q++I$zF+s5NfywT
zFlBpjp&u|shfwTR&b<g{-VWuxFfi^>Hlmx!S2-&d#Xe=`JH)kLxw0A9{FLfi6bF^_
zl0g%o{9_8FKxI!F#vW209fpPnE6;C5l&6)OBT<}D>U6NYp)B%36xqr_m*F8-Ij|DA
zJf)ZiT!HchWts|=j_!S-y{SA*Gud0pxpar#QNHR1WwEl7Oz$ZxC}(wF+2k3d2g<HX
zK>AP_P3gc#%4>CK%wy%-fl!t!?=A-JiSqb;uv92NV#S7irVI}PwUa7y9qOD_-xQ(P
zp!%l?02@`098(bfW>s(nqH$FXr_uOPRk8?WsEVU&m92_64Jk)8fCEjQs>f|O%vU`N
zhq6#rxC{*~QmvbdU~Z{AXfAzQwQ4qsVpXq&fZtUmrK2cOEu4c+c%X7Q0;yCrs3UNX
zRP*B;U@KF#%Z6C4N~90(Q`MipfV)EV8M&`i?cEKjO11DcEUQ&+7SPnF+I$JiTGd&a
z3D&8)>_YKMHRJ`F_FC1Rz6x(tnKyxZtBRxczE|xPVe&!skiKrt>eMr6u8Z2SRE_uF
zCiT@<Kx|f*(U5kFT95Tr)=lmEGg`4#-8d8ux2eCO7ua_7Ao@!0P?zR|ZI}A*y|DCD
z&-@F)>{dV2!O~mZwjb*DsC8HeVtv)0d<(#S^|mOOAkXLy>7e>)9-{D9PeEH8Y@qtx
zZBz!S=bc1Qht<JYkYPjAv(6y=qv}vf7>25!Yyu)&ZT%W9BGkirLW)$oH3i#o^|9@U
zB1(O60C3T2*RP>Gr7q3EEpS>rB^Q8L^&Ko8v2p4tok5nM{yPHjMD@oOFmaqyPte0A
zNj>8jT6kXF3uAvaMZF^ph&1(M4WhW9j-gT3C3TlfC@-rwpNHjD^?4h@PFDwMP+V8P
z>j#qz^=zzSvsvmU1Hf`aJ=hb$<f!*&!z5QdA`=bFSKE7or9d5P0-(sDp6-S6rg}Q%
zpl_>7@1nS)9=aJcch$S!p=tNj3>K%^2kN8gpn0gi<BZ~wdU+?9JXS9#fQxeVi_f5Z
zqMlcX;+fj^IXqRWyDvwVJXhDsV5wGbS_|qI>hInl`dan<+o*e~cIdVP@k%{&CD`iK
z-wuZ98};gRkiJt#EkS?1S8D@d;>5O~iG?$(e+=LTcFA<mY-HV<A+*hG+645aE8EQs
zzizCa1<sv)N|T0dteS(R2kSc%9(J%1h48SGJu?+JPd3Ie8d@**U<_=0*k6ak#U6H6
z2^{WaE90Tu$NoMT+y~e#tzhZL4)+4ypLIEp4h~?q_kc+dyXY_A4zX{jgAcRO2KWtO
zvyVXvWmk`Yr!ZD!g=GYr69mg+Y-A!LJkH*WpvBx1Y*TtVPO>K+gZmWw(I4*5us_nW
zZVcQ14*bTkk(AkuXLBg~oXDQM0h6<A^EH4cvDLc)PiC*t;H!Y0;RUIX%{T<<7Q66k
z;BK>t)d;4TZ7~{kcUg&Y757<H2o^Kh61D@a6+C29KZ3iI-AXy5$81Rp1XIQyxP(ZZ
zG((e6IBO#MLAgQm=@P`WQFEPU?3*<Udja68xj|nKH_h`4@Z_$!`wc?#(0opruk9Lr
zYdGAc38k-^r>5t5bda|ul#}rM`Dm<I(Pe!##(Z?tUd^}XVY6S;kMeT|G}mZymZg#V
zLb{>J`VN-4nhW<J<!RncK}-c2Wj_E4HF=vM-PC-O0G3-CZD&~C(R|tgQnALhFXFwY
zxut@1Uz74JiU*oU22eX5YTh3~n;vO$D4q6L6E`1Hxh69LAwJPe{1w0o&G4x(eWp=e
zfv4vhg9_Z$8lU5!sns;U3|yUNP!ud*YaELZMZM-k1?t{uQWm32-fQCf0{&5RjPgWI
z-1BO9aN!h`+TY;d*1Uum$rX_HI5+79TtsoYA#f4RdHaCv6gMOq9ekP_@Ht3hxKX)~
zV!0_S{Kj)LR)Z#id-MsEXSo<!RyxNGnSi=vF5oIS&vUUfa!uuCPl8Drmwz0}i(ExM
zl$SWiL`qg(;eHK-->cj;dZS+BQm{dWz0Une`Ik)YyEnLoS=^`e>B#1G(WF0z)6lig
z<EHjNk<Z0AfxD2qbQn?*w~0aL-Qs4{BKq6h9m?MqbIq`QhP})EIt`)S=hhE{+Y)Yr
z<0%}LayvFde8gQ21x+~@pGlq1?WXm$XI$k-C@VQ91Mt<{{Bww+hWmlOt##ajo4~!~
z1`L5oJy+laz#A@??!fn420i{CxKo1>g%j_B)o<3BcXEfcf$#qqfo|mQgwXhBGoKfS
z!j(6)1;UMAkO5Ebd^>8>Ha_5Y06q9A$tZU4?OkEHlOM7ccu#&F-6dZ9%5x~Z`Rf}H
zlMjC{7BQvp;r-F<R6b|`ii>>8N+>V!<9~(wt9&oYB&PG{QYrs>oiBV2(hR;p4To9$
zhbeG>gFieRY&rZonib~qrMp2>z&mXLu#mUWG~g!B`~c-G{-Oum7xT*lse^e(dq^ex
z+P&a>z}FCUDKD0y?h#+S0q`<D1(RyFoF9UBpo4wN4}O5gRPf&)MTnLBMeM9#tN55M
zu&L&a6HwIfeIBB&mVZG@40Zh3kx;(oC(<HiJwJU39KPk9u(yGI$H#sSvXA_Qr6`<)
z%89Ua5x%+zX@ihJx8)|`<|9a(g}GNzIJOA=526)r!n5Dd(5*t(YPi@YeEI;9ZWr=*
z0l!07H4CP@gqNEkc?vCkLE|lyQa0E}n3V#*zC!14NPC4JXclrnXdDAFKfxI*;%tDh
ziiQh;g82rdL&6n$-2@9?W+UtnoYO1qi13Kg6QP1r38XL~`ZGikAxxoB+A-l50mX4)
zM=6vigmoc^;-oN^7G6&YEvAF}jBxldiWnjNC$uGBI7zRRB4P3+nA{ZBp9lQ5FeU=U
z9bwBv_`NH9*$IK(6C9T*WBWiT{1U*2!q+s`dn7bl4d7$J{Tq;$3x%}$@<d4P2jw$?
zp;gFA;YI|cYM~P{t89&MHx2Mw;pH$Cb;9YLsCy-JFGrxSg`DAN*;}C|9FE=zWi!x-
z55neC;QS~YbwmR1EQYxQ;UcQ8gL|WRMT^Q!;uu;ma24kz!DNfL=n#PJV#`8UZWXUS
zhlz*S;~$u87a!6Z=T4FP1)g?^RsW#QOH3I9+-|WCIrI_3bTHW?F4+e_w0LeJlqbdP
zbF}__TD)-y{dGqCY%T(h72hvL6mjAXdSnvBH`oZlCW@(9s5>VPb^}e482<(E=fz)k
z!&8b_zZg=Qm`LmN7sRoHVR=b>5`((SqDKW{x+-p30M2xA#$-qtV)_MeW{Qc!1w4P*
z;xuxYBWfv%JTZ-yL-IwbBRmy~J{DYqBGE7#E^dj9^su}wy4;7!U9st>knV}?H=_|H
z;<Z+QKM><-X|YsvrIE}daeNtyGV#|rP?n2pHiG4;7<CHD3UL>b*$%c+Y&sTwQYH4A
z0JdszK?o{q#BY7km|9VM3Qu)n@HZ%4i@Gf+>c!}8aQIfdP!7^};wBm(d=L*71MpG2
zV}R0G`iF9ME>gW7(eIOP4@BL5smln!{UoPFFgYmwav8xm0;E}e&{2VsJreE@Nx#z=
zGgykIg{Bbci~_|GNv6IGm0X%b3X@*YG$BHoL^G#jlI=P?9hZ`6fN(<cr)h1p^cA*j
zvL_`gO$tv-$zQ?bjI_Tw{KiVFPNKPS(v(}cObHIDc{a*K>EM27lcZ&xVVW$Bq<LJ5
z^n?~NQl&0lkS<Cp`f^>8Iv#*@MY7Q?bX9W4<eR-F_4yIfb;-UTQl`|21}#}q6@68*
zr301V%#pU!wa=4cJOIy^2GSZrq2$O!2A(aFjx_=Bmei6y*tey>Y0a`&N~V<ZUFmHU
zfcK@)B7|QeHTfRg52YUa5L&6UlF}rPrQvjYl}SsjfIpF1(TeL+$twcIduhaBkZqFx
zoR7j&PNX5Gmz?R2n0Cv*IeNjpw|w|63Lm+1Ewp>&U6f$<l^<OMVy}G01c&?OM9Od;
zkR$Yn!cVsDLre$dDKrW8m;az(0_0)cfD4pAYYQnzo|gbmhh=x{rDH?n-eyD?Dxajq
z@i4h=6qMKG3Dq?JyDm4P_iKjSpB{irIf`DhS#rDXC~nAm>rrIO(%&d@<Z<+M$d!{U
zDDq?*=KpNI{D23pK>nVRmiOe58Yu6}eM-^#hw`gX6lJmtHvX~Ya+`;cp2!3KM)6ec
z)Q;wV74ivM$9g9Jy+Q*Y_}5}MtunOw;T|xpE&1r-HtXY|X}cf;jreTEJVe`WY-{L0
zSJ480`>XEY>(Ds?*e}x0!KULMEus1H;{mj`ll>mz>g<g*9k$C)A93tjGz1LY47v3D
zb-zf7<sMB30M;{mAOO7*&!PprQ_A6>&zW7&e6?!<==%P4632cEXj4%CHqIdWx+P^v
z2hK{zanKvO69*qV1e+m+SQcW3HfayX!^-y{tg&TZL;s!6Rh%yx-UA;0+;b894j1N2
zdOv$G^>&E+m@Fgg{F%SL1!XW3w-m}yW(8ftNao5l4siT)=W0D*ww3#K5~AD2eVY!~
z9^9)`fG``SkKYb%v<K>TayKbmvWsg)Ni$E*m4+i;T)rnF*v*ZXu>Q(=b5s9<)`uHG
zTY&a(>z|<T<w||vbU){$1L*;7Z6_%Gxw$lo3*f5r00`uMqD~0nVwZyLFxO`>03qDS
ze-PRcE;<Z#N4d-~s0-x=bVU)y^_+(&!nr>4;WmP6-2|Ii*<;+C6=-E7*PfO@j&q%`
zEX1DRe13z&D6S)A0He7+God`mEyNBo42VbYC{A;2u&<Ln!+k|#jTp|Q2Fh5j2YsO8
zxCJyvi05=G5KIF1nK!~t<d(Z5rn6i^JnGJIztz$Da}pPD2HF&E0(Dd>_fdyP)3^v4
z)?eW64}kI_*KHtNT;fLUMKG7Sjg|0wg-iAWE}gsF3ofp4-_sK7b*?T2y`I61Zx47T
zH?k18Ebfd1mK)rUePNQ#xzo;=JWeD|M?UvC<)#a`XIoGda`t{OE#mkVC~k6FTfy`e
z_YGxqZgYE8Aicwdllx*W^BU^za`o%brT4fsT@lQEZhQ-{lyH~n+CSjlVNWpokaPYU
zb*0=?T8)3i#kPRo$6O0q*)DT%7szip7a9Z7C!9PHl~1{M)cF-$U{BON<Hp$_RdQu_
z;J%6zyih#n9wdRZnj1`6{2DIpYeeya>q6_QwcL5yU{c53NrJ<d+}m;}UvU#!!Q>4$
zu>{3iu3aMPK5&keJ}~{r{YtCqPW*wV&^q(+^ex-OA0rp8eB3S+Tlj$=Q0LA!SqS`A
zz8mdm+QxSZM4bn}(;vllzK*(N2Y)3C(oX*Nd~ojK1sXGZ@^|TL>BV2W2l#IO9ZfI2
z`Gt;OAnxHuP!__M|CD0e%MZe4OE!@2H4jA)@3j+t5AjMGeg*Rv@1cVZ^WEun7{X_W
zxS~h+v==Zr%8%25C6vET@1Zb$H6_Qw`RoY96v6+U1j}Rm9@-}r$ycp}$#Gt*r18%Q
zzTXiPQT*TELL1HZi2?8=-;BES6hHW9ke=opG}So6=N6$aWB5unNMrdk8Z<4AR|O)_
zc>dFBSSIjYXylQ|SM>z^EWeOOhUfT|A*f5@w^D*JnfE#d={%p=o!-AG{1j|s##CkE
zMpUNp9_<j!MPA<xq?h=W1Hg8fzqJA;SNJrnuVMbuo6_Lv{NH(as;=>Q9l>^;e@)+u
z4E_W~n8`n!17#L(dIpml{I;QJQa1m!8>n;mWO^az@;{BF_ir9Qpe4BT`L^_?DBv&9
zw4jh*N84?Rc=>k}H~GSih~gICY7$6q^LwA*QrzL&(_Filf4>fa-sN+waDR{g)*IaS
z`GOd*l<>VNY4d=OrhLake&<S9mhzP{EFbYlXsd?fF@KBFab<jbW0;on+maE?6Mp4M
zczVi<tx#9N-=-CkXS{nB{8sW=)U#E5uS(#b^Gj(sQq4bz1fYf&XyNt+?|B}f)$*->
zgk>G?PHzYop&RY8*dvVm8<zWo3op>5{SKkm6;vJ&hL@o56Mm=n+(E&n1>RryY(MY;
zLdYQ01qw?SBEldcl2*tL39spk7%T+Pbnmdxk@g;h2;CQ=I3m293;0nX$PBVjVKBYj
z!-Tc;poa@AZ54_XO!S60E;tHkHS>fJy8&X95H=S!(ZaIU@Ox5dx)0JR;Rg>mJS{w<
zVd@!SIISVY2#u1Vj1_8<p^OuFdQrp+%by^^1i?XfLZaYGW1F+W^F@g1oNy=<MUqgJ
z3wW}ys3(f^!YapHn5GC7M_`&N{4@kbny@SZ!CVl=(YN}du=*vqFA4W)Sbtf_I1S(x
zA&5nnTouMd!6aQ+LvPz_!ni@eT^HVj!!kp_2NyS@Fq<-|S;B!Zu-p*Z_Q93R7M@H)
zpg97+mga)Ff+Y@q^Mw1fhM6yXN~yL2p%bm|6bhbAVOk^v)5`cwA>${|+!E4gFXnB*
zwgYXtBebQ477KMW^0+H_q`~r@@F}g@+!r_(#Pm?uH6CQ8Lh)L}^hl73VDeaq9<0Ih
zS0=bdfu>xzLu0Ea!c@91p9+g97g8b2DTee+m_sWemBQKf09FaBXj9vBA?q~&)xx>6
zXj6?a^miy<2nT6{P_3}C2)H`oAq~V|3Ku6p`ASG?0?yY$=U$NNg;qMszr7J6O$h(3
z&}uF!-wDI|qD$Tjy34?S5bAXx{U{_%gL^0O6Pgh^i~aY5)J0r%1j-HKyXRorC`Ne0
za+5fX1}2-u?i0b{D$Wmt<rYy(8=2k2)xofI7t<fX(N=L<7~qa=;++Mk^blulg~RRQ
z(KsM>h$(x4-zoag8pJN~T@-+xV)Jic=_L+{hKY}uI3J$&h?oCBov&#97SdkPBO1j%
zvEMKRvtM*4&I95)EgbrZ&RbC&6nE2y&tE(?2Avn+5RZNde4zNl5{N<KM1QzAB(}DL
zCRh|{9&uQFO8L7Gv2Q>4Jt7XIjn7BL$)g~Jilb=%X_%Nx!}@S>Ob3J=A%4*f(lJq>
zId7ymm>#j?Vn5pSc0%lO0#cMXk#=lHi;mfmi1eg5jfOd=#JhB3oEEi1A)OId4gfwz
z{EiaXvEq1|{Kbh6pCiI}F?11>3F6XmAWal6AA<6%*eMLkbE1PbxFm^BXx~n<=tPsZ
z^WyN?;7k#fG}}uRmr<@bP3-HS#kdRNXKUf<qS%t2oJ(StS12xvgM1Op6|vwbq^qKH
zBe+Nx2d#vQ3~?~sftlh6O2%i2YkxpL-4Hv{vzaa4?FGvm@v#}6a?uEw<cTG;KRI6v
zaD%@B@ijf0g<`=Qdj5*UzxqRaQ_RaoaZ3!=LwQ?#+X*yx#FdmgDi&MQJmRi6sT!@g
zCw{X4CilgS?x-sf<I7R^Kpgfv8u3t^zXHlqamFcFJ`$T!cRdzO!(dV-et!Zc<>K0=
zsCyzFI!60{pNi_~V5<;&{ed<;6C-IQxl(LB7gCiN{R4{U;tcGnz~tOPd#q~2^{;_{
zA<pXn%Ubce7RoyDcL^*n#rNId{*}0v7LHzvGbs9c(Lk@@H)7Nb0N#o>(@^(LY>s4+
zgMBZmXw~9_cytt6|55y9C@P(#Vshau<+`JzT%^+<q1+%v(tv8CH0~s%P0}n%qi>dG
zQ=;Eh5@>aMi?lWs05{1<tJ>QnVLkvJk}wX^cIgNu$974-(CErjGSTbC;U#UPwFn>S
z*+SUtk-F0UQ(x%-UD5s0TH1+xKoa)@;V0c(gCaokr$Kz6bbk{Z21&^a&_Rc#U#~z4
zk#1H3cSL$e3mRe4#UD_FOYe_E86ic|IPjSCk(P)fr7aIZecT~=(j4N1H2V~yiIVKJ
zXc8?=n1e`9N<9z4^ptcX5HzPHhE`e5NT(><6C)k%gkWN&^M?S4ll}=u5id=-h`I!c
zt%0XRDS);yot1h=LpmqzEk)Q#(vHV4NtQN!gZ@1)IecxfNs;yip)yr!I}(1=q-gv~
zhrJ+aXCcIk(#{Y>aY-_CLC;*4hG2q)^h3f3xW6ieQ{FCJ%AhyuHK{#4zSpI=Y;b2t
zo;0e<lyYB!EKB-zIU>xFejg4gS2{clMV>U&u?*b#l9wAi6-ckUfu>LrU!tK!Qp7^w
zZ%QX=LUT*HW{1gb$)9FNcckquFe#Q6(T`8=N?CW{_nvfy?#KI5&SL;dq;EGP-Um_!
zB|jfZ)4KpyD*5*Y=OZb>4`h#}7HXRRl}XQO>t4C!b^wScQYTN4K9xRlsH>1J>;vgD
z>GxPDE2U<>09HxA(!}Dq^usa$swF8I?rWs4)}l*ZNXv|HSS#(PRA`;_ioRwqrOV#{
z{z_WE0d=pXz&41mUh2Gp@^5dXhcrHVE7@t&`a6l+h06C*8Kr<eNWM+bQ6Hsgv<~DX
z@22dOvuvdG2^U%M26da{&)z_}S$3{~3s<>@e%P=@ZnOjdH#wh{C*9?Jok6`-?l%Ou
zZE_TC&+?G7F+y;#+vR*UY<9@Knjrk0vKQ_A+a>G&0Jo?7fYMT4^1bOm?3QclLE|k8
zln3yU<ICW8j~q{{Z@zLH^1D~w_77P0$x(x$+%Nan0)9YtrWIyCxf6}P56bK4w(^&=
zz2LzSAg>ePK2ToV9i12?r_6`VAsHJz@Bxy48v>id@+sP#5F)pw!N(DKTMeY6^7o5T
zgv#b|@DwJee?aTQ<%>lCM97zKz~M1@*K)8#%2kJ9a$Fub3d$4mco{5Fvhi;?igw5X
zjeAeZGG+Kr$!i&q#>jJ<LW-3OXay%uURDFrcscqkiUfHa<*E|poYkN?E6cP>c}_-l
z0uPs*N%@du*^f5ao|k7H1Uy9+oe@Q<9Jd{HY4W-*@Nhv^1_N+WcJ%6s@{(-(0*K4<
z@K{t{k*jEUbyfb@263m$-L8Y?njA>n*X3iAV3{Gu(aLzH%+sQ9mb`QuqPQU^P<Lm`
zuYN?4BR8WC&Xvpd0G=m*_YRi%@_X7uSs;J#K?4ir97i8GERt(~hs{md{SruT$(|!o
z6w84Di2JS_cNeDjWa|$o9>|Y=g!_kb2F+PY<u6YFS0;0zP?pOJf`NM?kEHp<Gudqg
z99GJvc;KpJH(I!@kso~ne=lVH30T(3(}&agZ=L+%0%%^!uT79%$<t{t{6;=cD}rz3
ziW#7JC-<N|H1Fk$AK~|de1taWf0PHRAUSD0C_C(|9hnHpMe9P(_6F^NQ25=bjs6ty
zO<K400BqJyu11}!_S@bd+oH|NmGJzzX>)1v?XI2h8kJkM18C#fHtpc6kUX>=l)&Du
z-SG+VJG7f7fNiJt+d~L+msVE*7oJ+zVgS6fCp*Dpx7M2$rM$IUHv#9PUA!DDd$eZ{
zL-N&5?tx;jcI8vFexKH7i-6~EzczukcpT8qZ-T;4TNDh^gW6u$aLxK_edx;*pe?2+
zCs6y_KL7@4f2C2wA?-#=m<MZb(W2C0ZAwRQhiGLhB0QqqNSo-6YNZDVG*ml*HcEzR
zLxORaglmiX!X!d_f-Z&Qn6@*0up_lEU&Hjcwk_=ri`E7eqw=J77rk^(X@4C9hcVj0
zwCEA59ZoUDX%9w$EnfSX7Ptg$cq}XvwKG$}eOCLp89f!+X|#rrq&;s0E?Jwo3Y_P)
zhu;H`qAmUmj#3@kBFcKDX;+iO3)&yHp)nV=-gHA<()x8naamh;1jQBYaa!8Gsx7DF
zbh`H3Ti~u~<tFfSU0X@ZK^a=iIq+0yPfr0^mR1)5vK!h<tq@bT_9$&?%F((~f+<%U
zc?@-VTF3Y6VVbW!?u4sWp!Ey_O`-N6_2n(??@PdaTf3d^t2^3pw8B=bja5N;SNkV6
z$FujevyxFf(B55z&>m`cHY9Sj$5TO8sXe(G{ZyqLPRi%n_4FC5*2WfqrAB-595`QS
z)ehRIQmZ{x1)Dmp@i98_rFLjrwBnWahu;vzYpshBz<TXJl!keu&0YcNt@bcYvfgPQ
z({CK!YajMT@j*N1Ch9(F6YJpKNw=2Xdd|AX>*2{oH=S10H|V~kyy`~Xk2ILwq$^uO
zchY8EzyuVox>Z}zv@N<C26#8!7}}xYuA8$G%5A#0%|PR!Yu*K<+jX<@(0e;{Z5F{~
zr)~*7@Vj)W15oFwJ4UNuUb?U8H(|SVHRBPQw{8SwAbfP58j$VL?d}GDzPhJhh<N_?
z>i${^?LJ-GTR`mBZEXaa1G<OQvwpfV{A8a!sJpKLslTq@9K;=<+etqN3DoIm18R`2
zB|Yhfbj9=otYDoRjqVQXmX84-ME8Cm!VcBV{}!BKx)BE;h3hhIBc=#l<R=WCzhk;w
zGZ2xwHS~TxuG7-Y>x9ls!<;CcH6Bfi)@hm}ij%tDV<4T<^;V$ur*$jK5XBjtOdrJ<
zT~tTFV|9ILt5TfKl@`3>b?^5=O3?W$;Wtrd4FmkFE|tEi=XB>N73N6N<+y?^SvO`L
ziu1YwbSYDGYaXF8RTp&@Qkrg95MsKZyRseli@K>ajl870audCFSy%WGey`|KgVDmP
zI={{Ur0bs1eSA%Kg}#l~bsE~#nW4Mr1<p*J-3&mMuDu2^-EinK!(f`NtNjC!=IHhf
zf;Lz8aubw!I{62<$k&-EB~_p+q)bAgt_=<1Z|aQe5XCKB25q>yt*aY`2=C}R?FX({
zmquG~?&{ip0p&g2l2lmU*M-pz(-Pgn4hZIfZVLH(sB^rog;=WFM3dpiI(--%mg)TL
zP?qbW1_ALzr>O(YQ{7JbZdd45QFh{)ZaJmED|JD%*{(|W9ezs7KG$_?4XIkEy9JgS
z-IMpg)#(~9gyl=!x}zvw=@wG2z1FSYfUxUzjU4oQ&NsTmo#@%OI(8)Dey6+J8^HIv
zL$q)GgKqTqX#GdsKlo!4tdqW!g>r+whJHM_QNN9L)NIo4ONZah`W7F7bJh3T0+ucM
zPPBsQrZ1%wxV!$3*=W*M{aXo^+w_OZ!Q!Fk!s+?juHQ!^)?NBwAJ};6_nZRWOK)6(
zn0D(^Z^MPRUfl@I_R;sDW#B#faal0&)gPXODE8{}gHi0$ucR02e*N-#kR8x3-4DNh
zdYAQZcu+s63=aME-cG;;=zpRuxPf}{CVl^c^ncS(^^m?X?Su=~H>11du-;k)n-Kkv
zZP8yx^nV@z@Th(fZ88egkLU->FntvP!u9j0gCg`BhrsVKy=gy8BK3pm_ByU_`wA>4
z^u^oYAxgjhEdq_!&!@GNllr^93Os+O^hfEfcUpgy#(`(_!MlKn(J!U@BUT^d1^03K
zyVF4$uU|b1p(Xqq(>cA8LtT<SwI1Bb`sFkcI<K#s3n@jfrwL=KzTgY6r0Kmkg8G8q
zWdIyq)c3Z+!(~1HJ;)qa^rzdS+pg*d)5|kmpY#OMHT{#L0AAPk#$SP9GxfS*kh1i<
zUC{|Q^ov^qn5~~oKbp+ZCs8^iS3jQ~fCBx1Q}A1;kL!#miu9-2L3vXj^(g?i^uCi}
zd0Rhb5W4G*UTgz+u|xk)7nFDPZ)lb5o<4OJBE7HIGH_U;UlR|+1O0;sV0)-vT?Xz_
zePh~v@<`u-z6X!>KX`z<OmC(Y#d5uZ-q}y|i|7(Q)h{VWlPdIM?SMbi-?)jQQr{V?
zjBJ(u+G7Bo>m7S2%U-Pys6tRL^}Y%O^Ga`_<k@Te@p35Z^&_c+-sm@f0=BpM6O?X#
zr%$B4Rqyrwl>YgkSJ5wRKk9u6;AHUKhtQl2D_fz?#Sm~FbsG$y(0#no(4R&mu7)`J
zy~`GZ+K~u^o8cJ^P}~hu_n^PF8hl?P#BGKm8d7)|UX($(-7sT1iXDbz`WSl}z8{HT
zybSFq%f8z%DF==5Hq<Mi^f8R2^!Ogb7wy66Ybc|2(!GXgdMNi9I!y%UenTL+Jz$7>
zOnYej43+dd#sI@&1~h?&`y7-(hS5iWIAn+@g%oV)d<w;3!wfyHL5N}dO0?;S;ftBT
z9W~_n!C|OjEOlv^!Mhg9aKpG-G$PV4I3JeB4L<av+Y^RCqhJzc*trCNXhTgqTK_v~
zX!a4FP8t57WtY>2DdQ3F8N&cSn8p}xb_H9k;kT2BJI=7i1$FTTSwN9saJdKWL__!}
z#FS)kI|C`%&^rkoeBNNE4GbxUz-5q94QEwwpJw>541O;dy7dF~MS~T;=60}`4994*
z`Bg)J1o!EN_1nRH&G3FC*sdG=OQ6g!n8KjUG{mNWEz59>7RhcHnDOwNZTOpJ<T-|O
z>9EW-MASf;XV3@2MWNx|YygT3-EP3-reSOowB?pzN=LwN8|G2I)^W!$hgRo`4Sm%>
z+%>cl(a?K_<utXuZ|JUr-x5O~`Vrp)!xs7p<|D&F3zUxyIVr%E8J;EsP;T&Qfx0J#
zdo&MwYPe48q!osZyW#Mep;s`ZN`t96x}?fbTMy-P1OGiZs~v{h5@>1+%x%Q|!Z2<j
zxN8lmG`xCcD6%1@*9I%i<LV8cjfJN-hPX(uy*1cWP`)#)IS=W*fo%l89}Ht?2=vkL
zc_<_oBSZJ<2IKrcV6xFTv>EC)8E?}Udb6?jPAFZCj{cYguv?6aN>S-%%;<>1-55_p
znXSfIlsMgHY;he*591gmq@BimN?`6X4v$3mp2nBCh{DV0L3<8%8;_5LUvFd0L;!q@
zZRxjkdyE|@dF*REbq?^o#-ViQ?lYQbB(&e??8t`AL1REYn&xl(sTRNhV=v0T1RBQ{
zqb|spejgY1kWr1l)x!oGd(q76u<<W?Mna6Wc_2MvjHH!{qsG=1=&n#>lf!TrVVraZ
zoX3nCZbKPqTt(lC<3{Hlpgv)IMjy;5BeRG0A4VICXMydcaR_akI%WJO5KW6Q&e)8)
zSmW0-AjKKyO$1H6vE3cu6O8`!_aYLF#Wx_GH7<Du?sLYUX~dai98LRrl8v!HqBw6n
z!@wlP_+7)S+gL$q(2K@rwB~flc<d8ef4FR%+zBqO7;WoOTs8W+qB7lRrcDahjBlGF
zwCl!vtktm@#@C;sO_@ehFDSE&-_t&q9HTV}Qm*lfaCAbRG5RsOB;T0U98!UCDs7}I
zG)|*@dXaGs{ZWRSMvpBZyJfUt7o>x|ZFKzxh&#q}TR~H7{9u8L`^Gpuf+;Z;F9iO9
z@jIG_Jv6SS<VvaWDs2ycWNc>u;IT1xEx5~!13bW8Zd^luWTL_tI2K*<%=nOIRh7mt
z8l+VjYudr&xp5HvdZyawIvgyH8slma-S)zGd>at8#z{0&tuw0asC;R>MqBq@8Rt_A
z-xwEBCjG7P1|?PB8IzrWdvAQW26Z2dN*djLG@hjuFelUI3t(|JO{0vbi>Vo1*A1pV
zlhLG&rj_^|GP}vtmc}k_4%7bWz`L7PP_}KWDUH(A+f31PUwN3e{{sAWQ<fekyG#RT
z!mp=k=K?6bOcUF~WVb1&0#SIIV(880V_JIz$~~sX-9hGSIy)bhdrh;y0DPaxeJcF!
zH%-Yvj~+1P(}Uw@azxQe*g=ywy$$?LvOA;zlMn%#KvTQhAPq8AQ_~Ka%9ZHnVAJRf
zNQX_IP$ECX6huSCBc>&1Q5-e>O?#9=O%-Xtg_*psfiv8+in8+&repM*)MKWeBY=xE
z-J?15aZ`kYHYJ}hwHS)nqD(5vxksD&(HHZi$?pf?PnovTknyyssRaBP)6%a2h%sHb
zi#ElY)_jh-IMcx02s_>s>WpS5m>w=hk!YGoQ>L?~l{D8nXWG^QWJ#t^XmXZpa-|iH
z^QOP2JK!nBlrsP}siqdR<d$Z7Oz(yZreQLa7fnIq!F|aztSh9;ruM&r`--W53*fJs
zzFq}Dx@qGD)Lk<Tqj$-5(<^_pH^cN{6j(A%Gs#1i$(I&UZkXH~5>%%1t-+FGx;v4>
z^OtM7QU{wn)3PFX$~U$11+c)BXo0fO)bb#JMJA8akZzhb(@W@<X*4aB-!^rj&-NXY
zAAPoqO`b1da@SP057Ir;jOz&IzA11ROiD~si-3Dz`g}M{9-68v!C7kB){fTSADLnZ
z@!0fxUzk2IF;ijs)FgC9&sLbQw+qjaY0P32m8L<I1*$S_rLE1+O?KMoTy659Bvg%Q
zOGmWng(=1WvRYFSg<WU*A^{FxnhL4AUzx_zp5)i2ceH`F-n5zq4~{n`%?_}=HBF(f
z_&bv-05<PU;cLMC!KD5G{72K?a<tdUoFU`lIh%V>lHbMbLceU-U>>SL-9~fxI^Z^$
zx6*KMv$^ymf^ju(r<DB`^PO9W-p%|oy_ww2`)>li)jW47qS)pzGxSpMFwda97u(Iv
zXgkXevr{!pcbY?}*LRt3_CTbb=4krU8D8d1ouJ%pcBWy9w>jt>;6CQRh;)zn0=?dS
z&Eb@7+iU)eCUyJFJ!tFse)BXA5gssip%;vwdEcKfIcRn?q2Zao`Ri9G0?c2~izd*#
ziS`l&nJ?^wbjVyv*}-7*CkKH)Y@WFcO$#yaJOJs4xq3LHqvq(QfQOn__eBwAPQL(n
zxcT{YxQH-+PAhN6%s+KSXp!dgv>tujT=E8WC(JpH_lPFSY?y>dqs^CT@%5y+)hhJG
zDYGm6m7mk*W-U>iF*myge2lr<KDdZAzp_J$Gn@CLXXDLLPXSLb3-klMM01=3ma}Fj
z+ADj`e2IR^nPd*2{g%n*!zloyngj0xkY@IFr~NM%%ziYazi94I1mGoeJ?&AuY@SLV
z^DAaA+PQMoyj}ozy4iOP{9ZG!pxo+p^MtkF&M<dt2GUIPh!jX!=Jol2-!Qi-0Cl$6
z)CdjCF@H_zu3YndfAm_Oc@(Ad^UbkMY5lLjTrdGPg=UwouqiShTLI~&+4>IBE%W#J
zh~l<+;c&3sF*m(}xQor<6^Qq)Ie84Ed*%_p!{L2%?Kns!=4lMLADAcD0DowH^B6Ie
zn)^+I-$&*wdIdi=A8rHAGIP{K%72!d+us1&6SHX~fKScd*p<dsm`~AGh-c<-Z%CD9
zf0~R|nXgA8isxp&6S%9*D%z=5V=kiKxV$izUj|F9xjQX~*O`YNLh;fZbrQ-~W>b4u
zzBXsk0I=SCgr?$e%<8r<alAFZ)uDW6o*9hr-<$o1z~+N_01fFsnoqoi<YcjA!iBS?
zM1?3^EN<}tY_N2tePA0cEl&ft$>RDmOg3A5w!*~K(w8P~TP%y|?<KieLOX%Q-SQ7@
z64`25o(uQeEYTgo;^DBIp~b=NmQjA7*<sl_0>w^C7>xsWS-3M`^R(oSg^8DC+d8oA
zwm9lh=WY3UAqpRh3vD{xV_6gchrX8BpJBPz@}n!d@_;3d-hqCWADg1?pyf5)LH?Ez
z+aU#5TDQbC2(&mdk3bt_`KB7&hb+hbLWseZZfg+5VT)A&cZg;CSVVEeQbN<nqn7H%
z@EdALTm@X1r4tPh!YviF|2M*N$Oe;RmO4r_MOuE3hjiRhPy&+^mfbyI5@p#(&5pKY
zE`*1ZmiG?I@Sd_XrjhPx3x6DlGnS{+Z84S!w73v!N#BAZ&XU$1mhqN2S|doX7$`fR
zXc@0Tan@pzP@J>0qxW2r#fcWVlP$%Rp*?R|{0^Q{EIRtNV5()<29Tv$@@b>-1<RXI
z2P!XG>|GGsB}=3Yh|87^0k}X{EIlZNe$}#q@)7Bly|m%@nx$z!xW8_3r`6gF%g=K`
zlWD1243;d*x^NUXEESYv$+mQ$v09F0dKN5mErV%#l4l9Kh|bTqY`=`U0?X3-lz%C-
zU}As=&*Dkb^_!N3vk=TJ%QpI5_ic-cCOda5ZgiIwTgvw%w7ZsXXk>rSlB<XN`xe)S
zs4KBFPet*-GLwFT^w83Wa#5w0H<Mub$dac6?y+UoS%g+*Ny<cBxuxG$1)jermYFm_
zd1_ffKas1joT0zc^vp8;3m_^jAx~ghWoi5qOrBeQegf`l%R*Y+uCbh_TmGfx;|MhE
zmE}Z#z+YQLPgvGl%(19@V;M(Fgl{d|JVEx(lF%PbdT;694$=q9cG}79_-KivFRhbx
zOg<XpY}GG=<YFB`gYXU34Lcxhv^H7}7n`hWDL1p(dch5NS8I<-1hd6@W-OZRX7!-m
z7Vg%+E+XEo*61|UZL@wu`zk!F(*`1#?beW6kak#K&})6C)nyP&b~&siv~1&P{ewPB
zUe>LYO51JC-wRLP*59+?-pAVFD2hGSKw8%JwK}H4(_ZWN$*|mKeZCdae(MJsaUQTP
zqAZ=CHI6=N2dx#SVB&9$%SS^4tead>7if(L0$GrC;cmD;WOdA@oO`gfkmmk}t^Tw}
zCd9fq9i~UD21-I5wSGcl>QL*uM(`A7T~D8!aI1zE$s(-#rh?{}HHSupk=Ah!Q5?4h
z)0I47-O&L>lr?%2f{C^oY0KnEYsxoJp0ZYbKylid;Gi7M8S4WY(ZpD%q<}5f+Vx9R
z##z7b2w=R`eI{Z`u$Iw|ibU(~uK+k}wJ(OJbJk4C@FrPD#Q~6PEpLa=&RgIAhPo8%
zlyCr2t!eI%(ySW#X}|@m7iHHkS_SIEOIE`)2W&1|7gA#Uiq(1u*WjwP$3aAqZXMkg
zz-!h~en4Eeeog814C`x}R%KfIjz`aASr^by^M-Y~0&LmV*_1EJvF0p-GS`|J0h2uI
zN(BIg*4UkJRAl{-icYv`{YgN)x2%WrY5aNH+R7d7?^vt8gSObJqKU;_>ovNs?pX)Y
zl<mH?9Ss{wtnXGMrU%wfDLenr+I$IcrPfH=Df-A-^EGgftyQV0E3+;ufZuZK`aY<8
zVm(hgp`Kb_xxu8udhIlD&#V)s(BGe^v>v3{Xq9!)0fhhD+WQC))z<H6#jnP?^CM_p
zSl@j>6t&jR#)78K+LHDJytIZyA(&Uz`v+0?+RD)nsp@feg6xg;jXR{b)|!0?`<*o&
zEB)+yYbD*)AFMx9BR*PxqbY>L$tKz$I@`_<Kzm(mi+@KH8*GEk@Vn6#QHQ!sw$McQ
z-E13AYca02FlxmXTcbzdcC+mkK;v%9rgfgJwhOdna+|HG5;zZA^$J*SxAngTzdLOG
z{(;F(+uK(tcG(OmAoFzCR?&yV%U1FyY<AnWP$I(HR__g^k8OT2xcArsW8mJ`R!ncU
zy|x2u(U^U<_IF{j-=?P#=K<Tz&hX@CyG-je2W>4~;lkgx;RU1s+b_|82ij)R{4K~<
z9|FK3+h1>B5^Qt$Hb%1#+ZNZL2(iuj5-yI|HoS+;QCk;U<_)#EErq8rn?Fs7!);rJ
zL5i@Mo1>w}Y!a=GMcN(^+i}~x9|1UFOQ!jKl<i6)OrmXX=yx|KZKIDudCIo787xoR
z{`v>)JY%bJ)W9aj)}3<E@wUQQC=zVrDIcF`>so-iv$mJ?N;+p7BBMyMO{A-qZ2Or8
z=;v*U6cj18o=p%%s;y!)iZomAMu_5q?Lb$+FWNd&qUe&XNe*zAZ3oK`{T189=8&%1
znmH){l5X=9!F|p4dNQQzHi`DsW!Q>n$4jQ|2xb1W&<P0bhV9coP?v3ML3@95Y}f2?
zpKFU+g}OXj1WjV|ZSAsvE3maF0a>B#H~Q&uk!`&%05@&F(md>z?b|J=yKOs}NWZ_n
zV_QnU#wfP=wE*z0O?eqK_iQz@(O>s%)$;%>u_@-l?*khvqA?F`9cVULYO7ldlSj6h
zH0ghAyEGBFGMm#30LpD`e}?qLrl-l|Q(G9N?ka4*@hG0z8qpTSO506r-Ego~w#Bqt
z<GF1>4Wg*F-7W>9#-?nH9(rN(-v__7w%{8et+VZ=*T+lSjJ9aSD_a_UNM75f_CPT8
zwhRjUjcqFZ()6vZ_6A(MvrRXF`n_%J9k6_`4cQHokG29zraIX(XhW34*&azhkaw})
zcn0?y>~GDGHrltysN7`VP6Le1_NG&TaJ9EO2Txn<7jxj=&7M6MlDl1V0`YFO&!-I;
z+w3Vbfb+2T`x(V{`*xZS?XWAe0oZBpbraOP>;bfE*3({^j5;re{R^6u?zXR`FSWP*
z?LBCH?AI$H?Xgek2p7KgPx}GC*Isc3E)Lkk{Ll(Nd$|G9LHn#u0QlPnR3Oj*dnP@p
zfp#xSBm~)GX;;`Gdm(MA4z{O;g6y!}?+X+m_P#-2IbwGRY5<SgGacyeQ2T<3U<<Ry
zO2CKPjd^epVV}*R_m0^ezoLk=2hj5HaeH6}XinJGCeTFLAN&Xx(e?s*&7QO$-Gz8h
z*{^IuaoVn=-+`U6m*)W<W1q~zQLH_R<}7h`U&lz4@%BKPiznE-(;`lyJ#+_b&f53V
zvduYrKL%2gecD@?B-<y`ZtnB;(sA&VV*e)sQKZ^$uLUm6eue%p#RdC9%8OsLdm(Gh
zUb4@LLfvKiOAkm_?5%$T*;PAFN&0mAs7ti}?3%suFo4(XM=0f=VfSzWccwj?5@T8R
zo4pXl4SOB^&^+57<AUzWv4=K?i(GrX59;#ld(#2Pw|AtMSAl)E7fcH6U&X^=kzGsq
z&ztt%G=aKhUpNOIZri1c0Nk;AMAG-K*scqL`@8n!L14RQzfgsk?%O++fvv=Dq1}-W
z>>G{&@z6ekUR$O1_p~7V$euVC#bf(rVk@)18Uq*Q_Ah0)cw)cw47jKE97>8-*gMj+
z_nAHUOE{{uw+caBm3^x-?f-mkPbooXRNLoWfoYB1+zSD}urH^PeXV`w8+3P_y)iAI
zzqFefxOioE8H@;D+jUdnx86QvAOLUd)@}g2wQu7Q(+B(g?;(A(i?pfJsZniHcyMl%
z77e&dBOUF6+t6q;P5m7k8)58%N3BsCN|$YJ^n((lu8n^G70NA*y3#U}TO*!^6z+}w
zKaQ?DF3akRS8Cg)+PnAOi_Fw4EiE(6%F>ou+OX30(t6o@gEAD^AY0i>5fs^=fNT&1
z1Vv?uZ25i9@2~T@_nz}T=U(3DKIfiu?!)ipVDVs_8i7JjM(0&vdodQ4fyJA#iy~7#
zi~}!0g)igp-C*%!IBkO!{)_{wG2Z}&fJy-a8EZq(I>I<g2i&7p#<e9dBZzT`G9|%`
z9pt!%FpksBl2FFeTul2IBbBz<<BYYB0yK=lr5D%<#wN-Ugfo8Z1ZM<e|Lc&8WV}d+
z;3!5rRVG9;R#W9y4CDHbAhC?yGO)xkcvL75&nQ!aoMc!7sMIWhvFABRBr*aHz^Eh!
zm$t2BMkYO*DU8SpkW|JR^3&58Hk774#R&fcoTnL^e}-H-<KYwN%wV+IW1TV?IwP#e
zVqB&wjcmpfv<c-fqCUesa~Yw30xXY_FbDB`#uL`{XcjOkgFy-z@4f|chEd!LiL(p^
z9VLnw^As~Y$9RH1HB!v5BtTOM<F9I1c%BjVJycv^jFQ`3%Gm3U8D3<>or3x@#w(8j
zrJQk81(XVg^A)JCWPIU;&MHQ3HxyMfHipyruZH17^Q~n(6AqX<#_k;OTw=6&p>>(@
z<6?}}GxBDzUJZ=WKQPwFsEC5x6$Zl(nwl8)bYZla@yj-l7RC{BW?LDv@gQxCX99rI
z&Nxh0vN{+^kpSytIK2m(x*3&;^!<Y##^+MZ;u_=d-x%y=6i-4$A0w*^g8htU3anjc
zG|=uf!1$PI2nQJ}={0(T(Y64An~a=Jw1yZ9U%;kY4Bw+5w;2uoP=ALJYk~MMV=G-<
z8(}>D5ynOttNqY9#`xn)djE|x94N?fm+|r$tlk8plzuz+7&CNVWRj8e42+p#bWuWi
znlXD7WQLLP6vk#5Z_<%^j*;aLGS86Fchl}Oz6t@$0t2xXJb26x4gk}R=|O>7d!}>=
ztZ-lkFT-3MnJu%BvpO;DMuFzctggb;T$tm5u+5d(^$iBym`+qT;Lf~CPmTw3>)!zN
zWd27<HZNw00-C&;(NqxS!%Ti0Dtwt6e*^Jj{y@*YKXaI(A_2^<#Q+Or9;b?xBTT_A
zw2m@k-T+FFmHEwefCe*LSwIV6YJY`9C^PRWK#wuc(J|vV^M^xV31cc~xlb^+o(6U}
zvzMv>BA86dRYx*se*jt(Gxz}1M>8L#kVg!29mP#!nTu&#k7JJihqZ`jPE-NxBvVDZ
zRsz$Sa{x4vxs?h*l9;Q01Zy(0jcUqMm_NJ@lFIyrYNyheM?Qr4r<fnmt&`Kt<j>KW
z&SXsjG=mxN1x(9i>OHZBS<I~+z|3Zvsvw@j%x%C}E_1pDtvqH}7sm3LF(n`c%rNV1
z^cFI!e}djKOy?Yco@IVU6@^92K{;$HVgAN|{CQ?@1?;}Sd~*v}N|`TKg5@Ifh$oCG
zV>VDpP&xC40W1~FpD3DH$*e2`XB9Ki85UMEclTl`YnW;()vRUaw?m+gIk&<JgD){J
zP%!E;Q%f1rdS+`C^foZxdK{#Y*-uf1E6lx)u&{}_))_3#%)>>%ZeiBG1-VwH{w5T*
zF+HzBpq<(Of9H}}V+Knnv!5KAF6Jbi(XKL|%L8XO^Hr+%?qPnrliq*Vm<&ox^)lJ_
zAkoKs;SEf!pV>i2uItPfDDOYO6mA0<Wd2LZ+Z)W@2AF-5SwbP<A*NR^$Sr2=b0D{w
ztImPt4)Ya9w1$}my2>@e<kLrmN0|}3plFP_V*<vEGYhMz{_HOE%oI$VV2)EI@IB_k
zD=|2U1%~=5CWGXsnRZGjoMEP&0Ou^TjgP;`9P^+WvzTXcOlaL_YL-Ib0@GnLI&E1y
z>C|n<%A_h9dsgX}SZ)WF(+41qtb^pYI<bzd2eCS{o*#mQ3+qS9%Db|PuETscR{C*h
za%YuMxu6GYJQpmUtP5XY%!}m_4u#$<9(|?8hxHo0Ieb~az63-4ShB6q>(9FU30MMH
z?;XNeAj^wNk&dt&D2;cNHBx{@2x1LWFeuo{a{CVwA*^0{*MzbHUxMH<*2(>79cMLf
z1_@(rq=Wehma_~?63%)*6s-uBE4?csS-(&)D2DYQ<zix4|B{~{#~O}6E1uO62(wSJ
zeqRLB5?J|67?a3aFoGqC<yC;OWR~?g6ag+tVeKXdFqQR`7g}ko$wS~d#q#|Krk!S`
zP>MgDRYitoupB5Clga9#H%}Jp;Xc4*v-a&nXAUcsB3rpEzjly3*6);y$!DpW0an1u
zri#EqRvE=8&#>B`gWOrxuhxyAMXYxuF!3B~uo-Jo%#svfq9v?RTEz3LZ)efEz*?X}
zfl`*e8#phr9;GNj8EfJls3>PGP~^XYbsz-Tm8>neBfq4I^#Sc#)ht(fC~H{qa!jz6
z6(0wIIu@UTsh3z={-pZr%dCHfF<8%<VL?*^i@O{u8d+%+FTTQJ(PP-e3cn1&W>y5f
zI9phW|If;?zNC<F8_RzsNIPpT7@!@j-YX!TEEyFtcCnhhF?N;pH-&_|SuDy_^ssi*
zJ*{gjmr<&J>17q%fcidGSP(SzvrcS>-s`M{UXTISqjYK*WJOT|{RZpa22AZH>nSmo
zdx+H#3>CLnb>zU^W`)wp`VQ*}I&}}Ts*Grjuqqz~$|$S*FW5B3+I|R%##!&KfH8Mj
z6UYl&mrStyDbab4HAbh<N!DsAZJlC`yp7g0D~N8)&#<2LfZemKLJB?1vEFn9%RKAw
zTbRXtR;wM<FR-3;1hHlF;~`+jK3)KY_Uyq7XmVh0*$JDR*^Ly<bYU->!k8=jOJ4|B
z-PkWsfrLAo_dC!$*qbT-;>q5z27+GfJ;yNS&90|Vv=94<m%!r7<~;#>{n!a~sPt$5
zNayST_CxgC2eO|y3bT)}UsOTiQMUXkpaikE&`&m)t*7%)2-}OE+fep#HH<lCW%J*G
z!sG0uKfn{l{xuim1X~vc72)hWipNK=!&gHhl5L)bL=^knP6$M^Q~J@0VP{Z1Ni2Jo
z_OLj1IPD(s?EC@<oMdkxUp#^RbS#WXWIz5MSd!S?RAH0MZrTg8Q`pv6TJ=<R!XXHz
zvEQLGnp5lz^ck<y?C%diMLL^9r|t}PMFNb;WWU-E&MfvaXTW5$ms7+thy59a9CO(X
z<Rj*>UFk=f&)(V#&H}b<44MkrE5^}zhP|j8U}xFK=?_!HHdra`a*nN-LbI4XwiS9y
z*zL64oo7EV3%f6{AEHxtDZ6zZ*caK#IcO?lv%UsQIlF-B$ST;ksEDqTolI34RqQl+
z#H-m4(>t|>y@ARVYS~H_<m%X2F3@+0T}_AB%j}#@l>e(|zeMl22KE6e6>VgD(FZoJ
zu-EMZOcVRw-(YEG-(H2W7Ph<xtycDJI(4_P&AY+U&VE3ORtLL{ZhdvKcgQi{E_M`M
zoW07fi-o3cc2NylJ?vqEzQ*<`0O@6av4Qdree8o{fazxo&qHvKo$~=y++h3Ig4|@U
zyMxXl_Ki-!++ruu#rNCnN&4L29rggl&W70^ECS02d)50`?oqbiZnVbONhuH*XN%~v
z+g<kd4`AU0TS@gG_t;<4{k=){P!7dEr`WF@h5Bi>>J<#mu%{@DGt2&fa$a+6A-PcV
z>__Q*aG$-GB3ldWFbAO7a#mgkvE!ssWXqo8?tnQtaC~2dX^xz?mq5J}XJ#G(&YVkB
zTjs)v{0J<roXr<O+&I~<L!Z^1!=RUp2j{jO?DphTyaqHc&X<=V;mvWTQ@0Q28W$|S
zoJdNv_;KFtf@%JoX$m(7aPCrWFpx9Gf-y%pG334;<-AXk@F30$<fjL7&eE<G!l}sv
zW+-Rg52hXC%(%d`<5o`8cIXY`ETM4M2~O^5%s!m+038k^I0&@j!Q)(;#aI-_k3Po}
z&3P{lB!;sfhFmPipPs5X&hX>Fj^`}(h5D16E~*?!;CxjKD-t=nYN$`*c+y)mnKNVy
z=oC&eJ)5Z<YiS*tX`J6|VALs2CZ+REb6%l6C7rYHLFmokoSXp3<kV8cC5!X=QE1BM
z6g~q@Ih^5gaOQF@y#u*CPDd?J@;RR5w-#_5C^l2bd6Y7CXE?1|2%P1N({zhCFR#Pc
zIZmB*HOwgH6i{(X35P{h)#o`EK1SyS&S|PMD&>sQt&@u!B|ThaockTHx03UI8#=2v
zPIPann&VC-6g8Y)4g_jBfwmB@;~cI)>k=oKs$nj3TFF1D=hXQ_u7M*v3xP(?7kyTk
zafQQv1tvCe-29-TnPaAhx`i{<i8-}$qR6Xk<8TTw*3L;h0f7#V4;^$nIr;Qdba7g?
zL&a4NHxww{94noEdpLzmOz9fu*BOBIa#m3JS|4Wvl?3&3_PvI&>zqU1(fe<JGb07|
zAZHu7lQ%dQFGAubXB(9_4sraRg2XM(4$7?F=DbJY*E^hm)fgM*JWTuJ2<MF=%xRR9
zxB$5^&Qsw)8Rz^>KH^;t=UH@4aMu0+4fi<QCm}G&VeJ6R6lecqbpD&>{Ll@a8P40}
zVb5{~rhqob5g9S<d5&rw^xo$<Qv`8=V>F}FmK*2@0Xyy^Q4p}_x=q1C2ktKvrgr2O
zc|fldS3p@1XRdu91YEcWD6Qqn)q6v)8@HZ(M0f5lndr27a8n-!wkJ35KQz6#zlkvD
z&Gmf>ojzPgy7uVHecv50e%#G=0QKi){0kDmjiF$BAopjwaB+ki6$bT3xnC4QJczrZ
z4Xt3VdoPR$;oca;a)okT$!R&pJ@1Z1IL>vLMJvq8O`%$%6WpFsz=U(Zd>15wi_f*-
z!Q<|y&|efcGXd(OxveR%FotXM2o@-o`(6~r;<!6^Vl1A!lMix|J43Ov1nxXJmC4*F
zs#r<kK2LGARPF%^-=uLT20%`6I~IU)nrrp104vH@C;^wjy>tumnOu~S;Zfsm_JCkE
z_t_pyCWjle87#Tn<21EAZX}g=<a3vP1(pKt2O`X=kgNC}3eRvaE(6M0?pIV3Uc?RG
z1G#hDUF5<Pa}QnxbO|?<s&~$FU$gq4d4cQFg27Vmho7N!k=su>`ZDf|kHOM%?i=j@
zt>F3&KvN|*yAPaI+)0Z2RCAxE`idIvmNU>)%l)GQpmkiw7RX)VE}>oPGB;@pNIm!I
zMszlCzk3wMG;+VBZ;xK#rWe!uuZg>hUMtPqx$mI2g}c)Y3R}6p^rCO$zD2QvcJ8^C
z(dyv38Zg$$y|@XSUECiBK(2B(e*n_WeT;Vb9xj8z)YrH!Pr$-n?ytW=ppV=9DHQf|
z|9%JdUgvI)$0P>0QH$vQ(IEE>`5-sAO>|Db$@R&ErXg-(2Uu@$H@ZOnHh1kTEWE?j
zsnHtd@>;+$!u?5))+pCK3DX|qI=%&gajrM*`FFX8J_gGK*N(QNd)%AeuyB$)Ph02|
zcjZq|Kh2fnvKqcW!QDXVlUZ&Xg+b@Ir|38~&wcVNW^teU2;PxP7Pv1_io=%Y+XQ0A
zOC*QYo;Ub2Y;xeW1cJqp$ES0)6YnQBrtQpIPJ6x!Z!497y7Hc(-O`QcM$tico?{He
zJ$M!LBCvY%+PX0dA6_h7)Ar>xQw+_Iw_FK9f8Hczk^^|z6hjN-J?99CBfS6mK#uY*
zeFc~x-q&>G3g*4=1!fq+yCuV1LU|TCfF0xQ*$1%Wyls?t5956@36>K)HN{55dCQ_<
zQ-qawk^-NRyquj7jN)Zd3@w`Ho(;hmUI-n<V|gD@@H&oHOnyc@@3~%#o#dsYLLh;+
z<}IKl@<wUzOyWKM|2h<&z#Awjyq=pdEtTi_9PCZwl~Xa>DW3l&jGg9X763DyXLX_H
zFoXAfG~_dRyS#y&#rux7t!&;K??8PH?@2w@BA2(J6)br?DOKp?^PZ#Upn%s$zx6_1
zW*}6Y;k{0wzq7oIx1gzrw_^z6=XhfJ%@y-lOCeXnJKhO$p4Ub(k_)^{s|1=#dFQC6
z?jp}N2kTtM%catua^3^9Ay@FOSuyQO-jn1nRPn|SqE*eyr(kXkZ`BHP*7CMd=B<u*
zp&4?QcqP=j%p0H=bv^GY-E?Z;ZK6m`Bk#XQz;cE6#umsm@p^a^c53DoybqohUK$kz
zwDK19W4>*?X}Y4{&T~5qv<_Y%)hTrH0>dER#ryVSw65|R-oUiGc`NQgyodL;4C2>#
ztLY5g%Ujw7@jl*1uR=pV?`SeuuJg807-oR?hBH=XkoWWg)t}wqc{~E1o4hbFc!qcm
zJE7thZxOx4Z}YS*uzQ4eIsu)dI6a~@#<QW79p}YP1MMy^h2k$0yv_)S-{ZaaF6^D;
z38?;TipQaV=`?Q{xtKG&8ggxCd5m|VZ;rR2pX$%%d6J(1dY_j-RXhv4ee1wu%YSkk
zu<iJh%P<Rjz73V6JMhn328<*BQ_3Sa@t-F5$eI5_83bJT`E;GZmA{4p({B8>4ve|;
zQz)|Q!5^g<i6=j!48)7SlN=gvej)|ptv>u(S}$MzEjljv@%_m0^yeR14ov}k@oJz2
z^0N;^;s`&QHkzaSp$2FQ;<wgAE||Zd!B`0Y0m}4;^7oHI?il|+dbW@AU1&;Sd?6d;
z1iyPTSi<?sXbX<u?_Yyfq?P~51`I~=xiqI}ek1uAG5k-cTq2hL3%%&$_^z~V#q$l6
z@IT4-pgAS*ov3Odk-tEdeM$U}>CBVNFQGJG3SXpzg{l09=?9U<AD~pjDgIu1!Jp<^
z3_wZeucy+Q48Aq)JMd)kH#`X|viNiKUdZMTghD=tub~)pF293fhI#xM9jwUb+fb~&
zfUo}znhN<&l-@eScjJQPEWh(5j1}>N=tz5xznr|$V!p%Y&{V?Te*xm>`SD+3o)`EZ
z9|LqLKhzooo{Lxn43_c7J_IS}57CF>D){9SK&#~cwh`D>{5vfetLBd;pjE?Peh?~Z
z`Ry9O)bU^13{uYz`~zk;@Vl2lVI%)(stmfquaALT6MqFAX`A_bzQI@vf10Art^8;v
z`JZk4b#zv1=dYzIs}4TD6nZ=PQ`e!Xi(g7{*Q@-wAHmYiU%U?H_wf6bz`n*Gq;>A)
zf4T}|ef*u2Q10h{@)=mJ^QW^RH^85x_tzl*`(=Q>!QV?>(oH`9D3*DMKX!<ozgzq^
z@^o+WKko$E9e#ZXu!s5MhaoY-f04e&Fv?$a4lHB*IZ7am^Q8{~<}P1S2Ne_i=g9hd
z{7dgb(<FZ}xf@e_dn%xu=KuN^<~zeb`v#zA`R`H`b&h|Lu71z+6LpW{`Mb}5p5h7%
zeEp9=vlXnPAeNoL{uGG4;Km0)a}YF8GSgA;^v`HH30~d}E1U&_XCdGs_)Cg0SAorM
zu+UB5n+Py>fq^R3JOu1KjCl&q6rklLSW3lC-U5$gsP_?M(`no4EAVjw^%MN|4F>%M
z_-_Mv@C5fMK^rJ={SAw7L?E$&F-HXh9Uwsh1#RKMg0NK>3lUgdAs#AdCuixH;N^EQ
zc3e=j1+6f_$9B+kLa=ogIKu^HbX<-Qyx5Iaq#z&-U{O|qfMU_nf?rKg7$e}ef+tp>
z{Th>r6MWDO?07-_|HCPQC`x!F2#V+v6^VlGXkaG^{-q;GvfvWM>Qe**^uVSHLZ~!6
zO<?#5ET;sA>7aUAU`t`AOo2WZ;#q<-R9luUus+fPnj^3dgC|#Ta1RFa1QYbc<qHfH
zf-4Y&`vSXAuwo_189@+T$2%+ddJD`h68v@w>dy(<BOy>Mh^7c{iGX<;b2%^gn6j=H
z1g}yEpj6=f1T<U}1kypXOmKq2DCL3->$9L00zb+FR0?7#wNfR>qf<_`puGjH8Ug!b
zjMWN$`W>d#3APB(x+M7HS(tWN;7&)=dchc#DK!Y11(-{tpqnbLuL!1BLVc59`3VR#
z3m!Ot*|!MJwF9$NkW25zHo^J5Ry5lMHS{=j2qKa}It6h;V0Q`H*JGkr1-w9@bqkCX
z!RQf8Qds|*;3+Dw?G^mB0ygytd@q9Z3xd`|?z-S^Iame+tv>>KP*BBy-Wvk_Fj#I1
z)>7DMNWiBf&n>~9YpMR_wm|zD(C!GbsrG4DkWWwJh@gP(WQ+>l90ll@U~B^n9v9r8
z81!Ai2?eG$A^4UA?g{=*#Mq=DH5Qtt1Yw!Lo)-9h12QAH69O_T=%o1AoM0o}TbdVG
zoB@4b5V(@=KP(8Itp<#(@XaFtwG#^JfMzdzj+}4@;k9QV=qS8TVN@sK`<WolLWiZ8
zjEitfDTu4kmd-qG!lns;x(j{&L(4<>o)&VR!V8O`&`apG0bt(32fu_dK0+_#J(l<i
zokPH4^%FiuXH$RS8hW<|2>0*B-{7e5wjEkQLND5TgM~j+6;Ft8&n2h`6?#w_@t80?
z5%R}{+sHQ!6P`9e?+M`t5=<go_!%W5BZNISp)gYT-V%UC2_L2nHCi}Lv7{K`S9BDQ
zwF>KuK#LRpLB3wRFp2)Z+DT!@Az&v69}NdjqVVTIz$6LhJ_Jb?K2FJ$6yeG*0Fx?=
zj=>_N3Dd~0Iwf4a5h$mH&;ARPbfGdAHf0Ds--KMI&~YiO&k{B`0yA59>_Z6T2(2S0
z(VHvWv>44ip`QrY`NHT4z!V4#6ml#SeoS$rGr~V8xOrCiAaxcA$A5&}IpNzwKr0r0
zM#aJ<!o_A7b6)t&GcfIf@HB<)N`<`ZfW9acQZ}JX_!rehl?#7MfuaiGe^v_rR0`kv
z3<|4+|4=BbTBxN`?Hb`fwDs2tPkLdjPMGiyR9q6SB=799u!(lWdSN5wcN>IJbi<=j
z_*5`#x+47ZF^n|{?@?s9S@;OO_FIGr<R`QW_oYK`n{X3lklTg%c2;0_2=~xs@lN5N
zwE1-j$0<5_Rd|>ph~2^!lw9u-uK6A0novopm0sZm%9r#B$LR6z7b;XxcwP8qH^v5p
z&r>#GP#FCO$PM8JI)L32Za)muhJ?@W0Q4<k+UGFlw$QPdzW;egn70w~!@_eED;W`P
z$Og}-aO3yr924f)0%lz3G7j~3g}kpZnF(Pbxgt|S8}c)zg)@yHGs4q6bj}L9<6zpH
zP){emdEq%b*mPfr0}Nhq!lg|hwxXshu*ptzKb-#mj=gAj4?rD68)>(76g`s(g-)WF
zNbop|{_Muz$3^t<7;JJC1^@q16V<_SUE(g9qy(Oa=$H`dJw-d#LflK_dJF>IqDMam
zi;w7&ED&GOmTR!WPgLatMgF4l3z%ns=)j8@vj&RZqqpf1Q6K}&qoSA`m>4A5S^&^s
z(I=%C3laTBo<XSSJcY-PiJtitEXPH?RL~eEDyD*{6QXV^0ty!;ke?7CdTkR-ixh3H
zfn1cR{UNlXMdBBM86&cFM=Mq&rClq|D&kV?AYPP41yv_S`{;>H5WPc5oJ7&Ba<q~}
zhp|yDNfz;n(3v7?NWer>MVaKpr-`b`PdFu7N?Yh@QQVVQwRBNlJTNmv2iXwM6zO|l
zZ<feZj?Qe+$e*w&NAwPT^dnbft)Z8Bp2$uG?0nJu4;U;E-QNnqLecYgF?L4uu>s_)
zX!|%MibNd>tll}1R~8f&i#*;2c8Mt9GHg08lHZ5=3!*pP#9T^6|57Q@MNyFjddozI
z3V~TJ@}nbDh3I?A_Ed@ntjPea68-!y1gk~2$WN&e?W7E8t>{<!JJpGPqD1E<kvbb_
zmqjN&1zNpm^Ba(B5J@R&+$egV9I-2+=w`4qiR!7qp;<KiH*9JXxzXFZU3BzUaCV69
z(y_Nwbo>U!x<udZqUZ0b=t4V4w<w<`(<5Sk1clc`|I&8XD|(T>d(kJ7Jq4D2QS~0c
zTo-lFgEt`hjh1v!<dX)_8=~7^q4TClavTCfBG*i;=q*v@GN9ZRg}epR?uhJ_7#kMt
z`WnkTBI^2^{{QT#$o5&tkBO@3d@(L6r$hf;k;otN6QZ9MFm_KQy#|{mMfJ3=Pl?vO
ziRGFWJw)#Qj40wSfX<3uCa+;mbTkDD=SAmVhcWj>XXtIXAabB|wyk*E4d}HK4=%!(
zz4(FD2k`tkh<8(Uv!nO}Az+-usyMWq#j9?ExQKtF;Fqg-14U!p#0OKs;w~PgPXKv{
zT`8LCDZa58EiZ8??ONXA5*Ao|#Am2d%~w237ytakj^yR|i|Z3Gi2!joT_O$?FWm)b
z>k)C^pBOwU{$&{?g2dmdVPde@cm-%7VjKF4hKgT32~Eeug>>WSxOnnDT47?V4O%C}
zA+JMWxVVZ6G9tu5<LHbOR}P~UC4QN9t!S}@YI0)4<+0EkE8epnbBPl#_<<$fDn3S~
zGAG6Ddmxw~wpC*=QS8TtO-bVKDPfr`X3%b(B6gwD<5aP0J4l+C-2j$T;w5xUI4!QU
zg{E}zngs}ChzDrf$rP_W1kNmRkN_;%V(Z(mB1il=mAU7NvuvO!PizgNQi?+HvAqyH
zBX(Z_n6u*acVJVI_-r}^&xt!O1EyH~YAr~K*k&K}o)^phg}oQV_4N8I6`%bRXcxuL
zWWmrf@qQslxwz$hkP7h^iO^6fb`n9nO6*bv%xZDZa>&()i>(wLsTCJfc(6|VS{<yo
zB>vC^DlUr;Ccxl&aXM83H;9qq!=olnnu5R;@uhYsY!ZJ-8*8(;k6!yN;!HcpwTkai
zYO_r&r~F;J_;Ux0b%>=@%HAnn9gndtaUcicSH&D(@_W0*J2rr)M_fgT`)lIe+h9zu
z_|Zv_KJhc-P|+_Aq4ULc@so6l9T106J;|V0L!Q(P@fq5+Zi;iHnA(uolipFc#6M?2
z#ci?tATaNUizA?SSUg;VX^)6~DK0lEex{x7zmJK>J%K$gewVhEyW-a=o;V?{%SP*-
z_~S{yOo~fC2bmJfp2pa;c-0ZKX2i=*0d!W}Lj{R*;`)bR@4R^b9I)?;t0^|RAkLb^
z1Z^c*6dSdZtSg6ldkHQ`;e{tT@g~Jz93{4o!$c=ZQ7nkF<g5QXmy!^QP`OGRZllvp
z5^xSG+$AITpu$5^vKKI(62nJO;U&=wf_O{3=&j@<*-9U$_LV&NF<AU0yMDl!zr?u#
ztpG{w^FRrdY$7-Gh{W><R?T`;;=cqcf+W$`FsES2JRO8WB(Kr#6)M?8Ue+;523=)2
zAt_A8s)tLqMnEt^a+`~>NXf=$pfF03aSvnBl0R6Gi;+a{#3IB>_C1U>jFb2VfhAtT
z&V`1P67zP9B}f$iLQ$esQdWv)lEii?EKQc2p9M*gd_`_usw9MtuW6E<{eU?od6G{1
zrzPpH0w!Iuo8m7Sk_{Ay$dtT6*_SMdr5OU*lG{ZvEk_bu2k2bMZ^bYzPx2)L0{N14
zVn7#24$((a3MJM;I?$Yv^mfATvl8ZGkSLP;OTqSY5+&s}iY3;cF#8fozdiJxm#m(H
z`~}IzB*>LYI?3g`DCzhVXl0Tm<a3ovIJnrdq(b6FzvD{DAbFEj5|sngS4;BGL!d?y
zKo-_YR8|25>m;w%1N4%lfzoo9C3$wRqF&-&gRut5tUZirlq`zI46jJSC?nJ)X`X|o
zX33iaU}=#An=!*y$$^Ie+9p{=G1+#>2KudcNS4v5yHj$2T=Fi-dtU(hs-!y&t!|0B
zkj{TSl6*4wn&kU^km!}{qgYg*#Q6j0?UzhbP0w}7-D6NcAaSIF?x3Wq0|GZBk5ZoW
zrsVot5Ezn_(sJLDI8p)hZOMyt47?+$-Hw?JOKx7kB8*6m{(#O=3HLXUF^T8_`v14%
zl8<v>{#}Vi2Ne^N1qsMK$ygcCCMBn+I&w<#1P`W7OEwOob4Id%2W*;^FzIkMCsEXc
z%uDuBYSLDEhe8&1(nmMKG<#_m6`43lzoX!lqts;>oKDhb=`iXnjY4_8b%~2~`&CG|
zO0(!-;wI%EhM>E2a~G`ekY22XdQWK=O~y;Qp9+e-rSrQW?<0MfgT?cee)=)w{G{n2
z;PjU+{}E#W(p?mC43y5$RoNrb6%>IuDqYwBlptx00dm38Fbb1dL!^tp!_-2hi`GKo
znDixzl^mCrB?Bf*s`S9v3F$pb3WiJfyo}jLNR4#rj+7>E180=fOwUNPbRSt5BfUW-
zGO^OBb>NJXZuSFaywqboS|_D8<TxfstJ5*TM5*t7*py_I_T*tOS!$tEcZ$@Xwyjj@
z6O>d;lRi#MdP;iwJqVtbetj9(>C#b35oSmq3;@ZLzPJKbWJzb}n4c|ej{;|o^eGMW
z=1LQ{0y<B+>u;dsOMeT3K!J4A6j%zSE&HJUjMQ4MMekYZGyAcKMbdq#fH^1qB?W`U
z(kGSzyF|L72@>a}pT?qfLHgqbpp{Br_k!F-=}y{H%A^PB)LkyMs{u-d^w}u1Dy2p1
z0ahj5%mP@obe4k&)<{b}MrW<`k3z`RNu8}4NL-TkM?l48>A@@Dsh2)31y6%?BV~3P
zrFF}Jc17w)j$D)URr&=tOTQ|DF)h-QOCZoH-CYZTHfi}qfVE36$k5p#Eupt?r}W3$
zu(wN^n~Sll())CG<(l+$I@0z^PgIis*(Y@!hJ3%2&%t_KmnQgubwJwvE_eo|t^dN(
z8&c&CkekwEDk>e4E}<`M+>%a^+k9J^Qjf7a(pLJ53`^}zU>T7<NKu?o=`1;(V^YRd
zSTQb*p_B1l=|K(1gp}(?-`~9_O-zK|NvXvac27wID6%yz&7jldjP%PEz|2ao#(-r`
z`s)G|&P!LWhK2W~@6dgz1!-{xIBjKDC~s&dd({cp_Oe5b5O9zkS%;RRYzGGdPO{&%
z5O9`VVgS=c_6;idtxH^GPt*CtO?I93Zg<%ui($TpOi8D1PuT-(jCsiplh@%bvt9y=
zkF3Q6;wwYe6Azw@N8v7i*$=*0gaBEJJyZnB%5y=E$Rfp<(otE@U%(8KEnJ2`uq>ZE
zs1Vs>wA)!jWmS|;I40BjV%o=L3FNVc$wF$O@PzD>PXHP&iw;0%gzUT+Hbu(LQz$G-
z_6qp|(Xu>R*%;aD6zz_c;q%3K@MJb8U{kzoMHDzs$|C9Hlpu>c4-JX36I6(mBwP9r
z7AV;&lhUr4A{%$dV5;nOD?rm^YzlXsl08cIU{A}oQCvM;c7Ge@lp)*h0f9`}(0&+`
zC7aCvOSWu*oV*;_T{;Tn%GOf2D^GTA1OoZ85AUE=Ae(;?78c4L>PG8~EFuwOXJuAf
zsunJiJ>Ut2=VUQ-C!|<rvj#91WM9#J$x>Oy0jRhr`}Q12nJk2AaLZ*pO3+luc$EOH
zlqI|hlqy*~CBUm?-?Cv^jjWGqaBF4#R6S59YY;>HlI+)ZtjuNE#a3vjmx-*gpbfHj
z9|vor%$0)mS7cAl0lP^y_&Z3mtmb{Nw8-{MgQZorvlM7;vW-JPYnMg-1`9i6&pivX
zJ7rG^G1etJK-s*jvVW}@>z19TA8?OswiVFVWG60Rp1rc0x6ta7{l0~Ai~X`)%OQVV
zrvDaXK(>Xv%0XEq<(F>Ab~c0Dl<lR>b4cbp0_<C|hxVZJwk+%ewC>0P^e}B$#yJVF
z5!o*CR7Yj`*U=i2J#`tF<FXlg!`_v>aTFF#$hg%2yC>V9MgHfc><jXUresISMV^*D
zN!#U&tZfWrR%UX6#GH()ho*ViCu;$EUv~Cov=(H&MzGk*2UNhelTWvzWiNN7=g&bt
z_W>sADF2sUCr<Jw>D28kKm9a_i(LCV{%Ef9kp+7G+~mD)L$AC1L8`U%kmJ9_<H3`^
zOZjLodEW-0dCLvt8vDpM(Mi!)E~-Y$Pri>r2>$ZFD0UVg|D^|@fpQ~N${dl0(%bN;
z{7*{52g&O^U}3PF)rP-Fi2V68zzmfi`w#-wWAe4+{2!NJ8U;_798pO;c=9NBkZ}3l
zCTNO~r_)uiNO>ED0HWm0lroE!H@RXgPHz7TVB+PGe2AZvf0hR91o^X#(3>bPV`CCY
z@_(&hNtS;{o=l4T^@pJ^RX!68fi$c9<pYp7CI2%HDo)F5=nS7OcRGuyWypW32Fa9v
zN-l1ed>_5)vgK_qfXR`6o`SJl`41Ep%#*LP18Bay_8`Uz<Q-I!S14bg%;p*SHF^=8
zl^-TouSotC#YoP{n;rlumRm3F2Q86*J_^C}@_<mFU65Cmz=~3N92I<Dlo!!$nKJo%
z%@`|}57T+7LcWa$v`TsQzmThvFQ+e&RLe^*LZC)2FGH(VzLvbnI(g6`2wai}&{AHO
zKSO%!<r_($K|XG!e0HN;77x}d@@Ix%X_MS@F$SCEo3dbji##U)6K$3IJ`GK6^51{N
zSi8KOp1%%xUnN*N<;h&2bjdYTa&lGfHiQ-JmJba<phsRsk+f@aP8(2q<vV@B(kH)n
z5aRvvKo;HqyDq<Cfc$`5`#dZilrQ}P6TKmKp&Y|a`2e|mL-Lx(fObn>NT;0JauL1#
z@5p8Jy{TdO;UbKU$i3G<#i%^x8;~)%iwI;~{=fqezbn5(MH3V9ho1nsCoiQZW>W67
zo$5cQ<UXGRZCXBf1u!#mb|7q<m4BTJ`8oN0Dh8jIf0YDH_vIh123e4IQuf7Gv2F`m
zb_(D75Vu!kQRRq(!gV=_qvFGtK%5k6D%y2btZv8RyD1)}%dPH;^W->sD7wF*`+uH_
zpO#>vUW$D>^m;3js0_wO@st}Rd=+d7RQM?#$pMSMV&4h00u)jC7z<R)EP@qB6rWJx
z=TSxdLD(ClsQn0I!HV%eArPVn)uS_1p*jQ1V+!NXAjcI>RDl(ycsB}Q))R`_$M8!E
zSDd*D^%06fI#EO_TqXe;r5ODj648o_dbDB`0hHa2RlG6>&^X0D1xUQ&Rtv~UMHA%>
z6BK{F0G32W2py7=6!~;GOIGX*giR@m0{W4qDyA~fN>hY1qIJrun50`trxm*>-juE=
z2*I*tDE^`nflS55WB7|?DS9c^n5}r6$|`ddL2;1JReUrJfjq_3^JwKO!sr%af#N^%
z;|dik9nd<X*zE(G&MID|mtv7(T_eQLDHh)aOR-}23+OCSSVNN_e_oM6zx4}>Lll=N
zRj8Q|yr`(6BW9UmmO`xMinpn@yF&4&Kd>tmTd5?yO7ZX~m}s?P^?HoeC`^0^)GD4$
zhj^XB;SMxiQg~A+>#{-}jdiM5M6ZH|2E`7FwKpm{tfP>>qR`V@u}RTrhNfmk>qQ8*
zD0q&LXjL430GiqqUoS&vyW&12Z#xuSEVMcmi{3%2OVL2LA+9RscY$;(9-&`;kK%<S
zfL&84cVV4-71J5$>{DF*9IbvuTm;l#S8RKccE$lk)?%RDRIJ|vo*_kiFnDe$5{^Uf
zZN<LpXx&i^w}NF@!RmqFh(e(T_NXG5T(2>OoX(cx3YY&Neplh*3AqV{(1O-I#ou(D
zU{dkwlUSfBMdd?SnQ6t|moe)Z#lv^W|D08<E<x{{V%i_r^9m77?Y`nudPyxP82uo&
z${vaf*eSmdLeO66MbEE;GLifuM`a6b)=tV_{(>>iO4j!fcTp~;#Dl9c;{#y2DXVfp
z+?7FGjCm+u`4856D*t_$o<A>T<`f3Km9~SJg^%)SN<{lA$BzQdPkD^$75tT<AHj+M
z<r5pBDNy-z491Qqe~ZS-992H`B*cT1pHprzSUEETfe@u%AuJ44UZm?2$CRcah#yzB
zlB*b|EN?{Xgfj3Iw5;LE=cy(=Lb;2!tw?2@KdgvS7EYlvTA5B!h8X2PbS8~ejywa2
zIAzZNolE7FI<!tIKd}L4f>Py%R-*C>Jse5OA=-kIab^HXQC_FGPpZ<x9eUH0@6i2+
zQ_3H|!Psf5Qqu|SbmiD}sLxPpe}MU!%By5|mQs%ry(QU7GrbgZl=*9bovVDg9wbk>
zbuk3;mA5DvS)f$D0D(f~jayi}Gs@>F27OkkphIDi^7Ly!Ij5{7KcQIpAr;$~D7zhC
z(|M(JqaN57l>XO%R;ql=4~uwFDWc<1nX=XgtmVp&dmvw-^g4uAwQ{f(ts3P!^i<R;
z*U@J;>XZkle(aKx;R+R(mDL=u)GN)uLZCspG7y-JO8x%>mrCgcC~8uUE&@xlQeY+b
zxkdQ{2MSx2FWdu6o3c9`o$bn>-hgQx%75vLuAR!LcQLgtWiEZV>8jG@36O5(3$>8z
zQLcColewn6_X|LKl~y`O^(p7dAlI*4^EIrvuKZvlpa+z8n*cqiyu2H7H<V#h<nG^8
z?!N&tq+GHG^0$=JR6257d6SN&ca$UfKpR$`cn9($%03D`j4Fi`EErSnp~{hQ<(IT;
z-Bm920``Q`gMME3lv`~eH>u3o1(qo#rytPM%Ef;{(Tws9VwqKb>P^qzoYI2|ndg;{
z%7A@e`4@dsXF+**H_&WVJ1(JRr+WKg$lI$@$z69)t=tC-9aZ0DV`@&SEOL6BRrhm1
zTvYsjVYaJk7wtE0Do=VXxU1f$?1_i!@n6vLRDJdr#JyB|@J`16Us3haNytZarULT5
zs%Tee@>5Mxp@P5a2Rdm6sQPF!fhrDdTSrvS2Lk4(idh8pL8_TTkYLsF&p|>|-zH-$
zRJDfcqK>IvxdQRys*~F>7N+_m9#))C^(mksT&1OI7;A*;lWS;3s^S;G6Qx>3yJocN
z77v<YRE|G^#HwDT5L}#UH@%GGRaL7Ya8eaP(WeB}CVDj|s>T9gVUo(+fmVj<o9{p}
zRmqN+XqL*EYL4?%D@LF`UzJ2Z^#aw8-vhJAsya^LvU95ARHap{dVo&*RjM^n&|9N=
zcQ<%yRo_!qp-#1le%+T;uhZY>vMQUdnboVFqQG>6YB|o*OBz*e^tpg5s#hqW)~qUd
z51cKkUVkiQtEz)e#%(Hlsw`+%t-KDk9V+Vwm%!SkdeR@7uBvp|m{Ygv<T1>!M>Rl4
zpKGc(iUs$n_R-eTuUb?DwCk!^XP^zJW+=Tps9J1=_zl%Rw0JjFCu|{bOLd&~<=d*X
z{|5q9{y`WURt3C(&Jk5AC00jOSFDMUA5;BD&h)s-lYU8eRqy0ra6&an(WiT=wd5mC
zs+JmI=#*-y5H?M#GRRS$QKh_w)|{$Z3ha5+JsXhwszZI?Tu{wZ9^6)4!2^n&dOrms
z9MrED!)!<OeLB)QsqMeDLa(!W*H0iW>OThn>ZVRvhl#qY3&`L0P{-4iWKZ>{r66AF
zlXL*{R$Iwy_fZc}P{&W*Ksf?`^_zvz6rg5&4D3MlLzK)vqTX^9<fuAg6Ko1m|4x<5
zq3VSnVazeLos#l@$JP7yU@%PmPA$+*sF#j`M5>)A7aFCWP-FJd>UTdxXPkQX5?B$h
z&NO1|q<Y31BuQO*9txAy;=NFxqGpwW^OX8^s-rxuUZ7J|x|&C&Dp~4l6xYsHZ@veX
z9JOK@eSbG!y|Ns0Do{_-15~J9ei&#)>cR}@J*N)X0P~C0x%U85qBc+z=)Ag~JemvY
z7Cy`_QwLK;V7a;?6|D-jZ6wAj)rTlYP^CU|5aQM9Qu=~Po%#;lnYpB{rflA2^&gZ7
zv(~GbbW@{2{rmweO{4lNirY4;<JutKqW*apq*Z+*6Dm5?dtU%rr@D#Csk_uysf43P
zty%_!*VH)_Ea+9Qp-g?B`r}-v=vN>A5)-|ycBFUe9reLjbPlT%^T9HrE}*%LTGgkh
z@N-NZO~;IJ_4pvr?yA?4S2&?|r=!n3wfzpjOsZc$0r@F)8|}T*>i2EHGNV?~W<9I^
zh7IvK^{#S|dG(i6qIO?h{T9fA+G2}NTg}!Vu&{QT3c5#NuSq9w!$D(x^*f+BYF?x7
zzc^_eFGIbvrs*|wx@eZCVot7_U&v#1)BN}$#@sclVljIU%|SX~dusGuQ17Mb^8mKD
zChmI>AI(}iv-oQUV<8@(iKld2pvGK?xg61)qIkkl&E+c?3(|aNO~YWY#*?o9hG_ih
z5?83E&jzh9&D2>~dO}mP3M5=JM=n%^CM64Fks21ItfMsPX|N(%^CW4C(Tq{~Tdc<T
z3NYg|Y4ow7c+K=Sh@aHR9>;tWG+*6>c%p_MhZRlIJn#+qpDCJq&q5+q6CVtcrrDnb
ziBp>98epH+{BQ~^=^E)BbY^Kj{RuGHny2YtpQCv{7BIOQpJ$;dPm@ZA{(KFa5+wy1
z^~<oZP_u*9@QmhEB$ni?W*z-5iZmh50_B{>{soG^6l)S*f{GH2nI7u%n)y(WQq3t!
zL6vJBqKIdO<_J{{R%&eg0a~TWi-172W+)r28qLf}u+(ZY%Yj{|Y2S{qOPYXnAeS}r
zD<Jh6-)e|AXuf_Lq)~H21#(4m)|sBaCe6LiuxzcGFHYf)*QObz!k2c<GzBR;G_5zG
zqEjR5gu&gKtpjNFXiDi#drjjpiK+E!V#6Wcr*Wp5@P5s@r6AWe%ZkA{pmF{MD>|rg
zrE}B`&5IPFy{R$WK<ALgZXU#XOY>1PU~X&Fw7=fbR2iXnRFlPnF?TiD|M%rJ#lJ)F
zo+kP%#wIm=<q(+C`2B|kn${e91)63wsk<>Yt1;0HwmD7xadggWF6@Ac`x>80bS`L;
z$t|<jwvm_PpncjC`W&s=n^aNZq-~-bozB{puQ5><Z5M^fUA1O^fVyd)r9+{+mc1HQ
zcxV^N0qUtexCt#U?c6zt`)c3X0Tq7Q<S@wjYmZUsMu7IWA3*}OdyfM1h*n9V^I$FG
zap(=vn(3V!s<lS!13jkon*rK!?M^qe!nB-Up&~;2*bV57)Q0{9E26aP>!2c9`%MuP
z#%OobBE)Jp`v5dfJM}bL@mh@;0w=Y8uR$O|+Y$+|MD3qGm~WESO!pr$v_EYFOQ!Y>
ziZ*9yORN--&(@ZBVlYShloe>X+Vk{r>^yDmIr=?oA3P710_`{tb{A@Gwt}3|25kX3
zt9^-_fFiBd1Fdt~y>us|SX)59gc9wle*kt~>%jxq1#KzCr%ScZJE8NU)&*Ptk}~a)
z|HnVewI6MSrV8!T^oUn#<7s=Z(yrJHm};%>mtd{YzDYHJwc6jmz|`urw)+8kNt;Ms
z!)5J!9!S0R+gG5XK^xQoxkl~VVVM0DZSr%NXp{DHDqd*T=JNpEqSY8+XscG0OZC@n
zS`j_)?b_|r80^rV{t={8d-`(-c4^<Dee$Z-dj{&ewVo7c>d{s@LDMy@LovpBwH_3P
z>C^s4r@?;hOO!&ouHBvrg#+3qx_&sQeVPhEZfIvJ(7LJZ-v;Z4w2@wP|L>M|1;rC@
zYuD;w)E(`d5UpYDQxuFH(Wd%A#i;h`7U&(*8XG~zwW}%4d{=vw4}l5o^1JA~r~RJd
z7?avasu7#gzD#%JrnR-T;GEIA(lb4;-8KbsUyFaIgvUYqJsni7_PRLQs2p^+`#~Ia
zw}wERbc?Tn$61#{o1cqLx*uq+IxS^U+;kr<#zft9vbVwMp>tmj7Ej&pZ$rRKry@hW
zb?)@Z6d#>GxwyW%7;;hlbitoOz+bnm8S5LMTT6RUpjG$8XP9r0E{)Rg!MbEe7!{(6
zd=3(!y5=OX9@9M<3l+z8jdcAYOgHf$I#1|6+X<F%U9T59BXpA#{EF25wGv=ax|8Jo
zM(ZAb7-KQIr1h{qR<~7wu{d29`MdGDm2zMv>Z~#<cTdtiMH_Rnu7`dJDY~9lFpE@O
z?-+Q}bk#3n7N>M)9|7lST>+KWrR%QJNhU)#@-s-LF24%mSvu=3w6b+YVsPf@G8e#^
zt1Fp+X?eO5x~h<`)6l{e=<+B?U#NT8+63$~y0wd7)LGpNTVZgKZl2zz=X6OFn<>^U
zqg!Jox{N@Wc3yYwA_On!c5jEmQe7Oq=r8IHP?Wq(7e;xHa-Gu`K&j9*9D((fx|p31
zuhK2|hWcvVJjDZRbU%foRjb=DNd9M?Zaewpmvr?`XkFID9fe@M&M^aM4LW5X6gKKU
zS_+9Py2ErDY|{BZ0KLt+?&m;Sbc-l7)T&$K3zRlp$sbVIuKSPblR9*54+5-H_dX>`
zx^&&A(Ro$3r2}ByI@ToBfA;9C6lJ)k+evkpy}G2AuwH$-RbPOoUw4`AD-Y^?=<&ay
zI~@rXH+6h+pNDkcJcZUR-CFWGZtK>chWH)b8|2Cl>)NQ~c|?~;`Q%ZZnEa_RozM~X
zj_dr{fWE66`J3V|6S|93vvp4w9SjpEb&GA$n$opVs&87i_#(`o(S1wTJZE*1F0|%!
zpUk2)ue(e4Tkh)~Tn+36-Q->nTYVW7<JjptoG}S|y&@c)4*JG*Q0S<iwnxiJ{|D8p
zI_pbPfMRvg57SqbT=fN1bL^%+*8%nJ`ll&7;GvIy2gFmqN{Kmn=}T7v)LXyD1bH8Q
z#%D0bSN{eT6#MDjjaUSK{rnwp2I${QLua6V<!-c&=vR${9My{!K`uxyeiIsk^;^ia
z5Ubva(g~sZ^%kf<rsssA_qcv_8nDCkYrUZUgg)^MNVvXhH`GVydFNnnq<-K4NR)mX
zl{H7}J1HI!r`N|pMZErPI%l8Md!Gb!g8t@PXeH`nxL`@rms0>FS^wrM;7rk5+cu$@
zs^39X;A#3LUxD?M{uBCq;%R*dZRqLx((~xd(BG$oR;J!gfX*y^)r(ltY<=|m7|YS8
zvoQNy{nCA~Fi-yi<qz`p6|}Gg`c5vaDAdozL*W_yOey5f>cjtm+9EyQnulqh(=#+6
z#d>!iu$JhplukddU!MT%3;MBPu$JmS%17r#{dtNomFbrT1EyTR<6S7M(7RKhsZt;N
z9u}`kfAT?Ss@A{t9!QOTy$EBqdggKn)ah#|a&bw&)C`o%`YolD|Et#v--O-<y(492
z8}&^bbY9UnJp$6CZ=}pYv)(Zs5-s{CsUomd-?t9}ZF<%Xkaqn%{d79?<8DyVsb{~8
zwdm5noey$VzbP4O(XIcMHiI60-*(KUPyZe{V*PrtJH7v|>#tLB=YYQA8Waxd-OXUV
zp>OlRWNzvMKL+cNe)|=WTl$J2EXi&CQp$(j(LYQl<6(WT7-U30Pp6Gh{VW~s#`OPC
zZhl<9mmZ_L`j_eGGohCr2If6|JnayZ`WU+h@cd2b|D*DqX?^`pkQsg2TENWeeVx&o
z(?{sQI<MbE<^A{d15~rMpub68maX9i7b@%wTl=8i-VpU5rsiO1+yOa9L*_~lCqvh-
z;B+?pOkpw?!_1pNaWzy>VA;(u5Q;IYyP?Ayf*uAzJbFD1JW}sv2yB47x8dPEknk}K
zm0-TU2GL(o?`H_gfKC1eA9}+F7}gYnCD8EBV?aA%n9xDfQNu%2%^75Hdjy@q1~opk
zxFp2T@H*r|4G~m-eatYt8DPh)hWBY}3NtXMxaEYwbs0dz4Qr@YEXrVP0!*~wQ!+Tl
zuyh25#v3?aL*Yrob}I8tFgz%Py~zfl77LtWaC-=HsfM@dXO&}k@DFIpH9SJ8)I38r
z1p@O8=@n2^U{EXqSfRoC=ws+TV|a{SxMvOj(W|n^U`tu*bA}|U$}BcyJ`7DIhL5%Y
z=DgwCv(R+G5K0?ksbT#)&~(von+`%{2KNInt=!<70+tFx-4d`=8qSG;Qe{|Aq4R1(
z9SPJJ(ziihts&g11y7wpJBi*)2Kz@Kc-gR-(gF2`^y@Ic!GM33ji<uE`VXxu2Asd}
zR2a4<qSb83r7u6U7`&q)&}wj!U`}lY;~`+S8}`sxhasFEwN8Uv3DRY#I0|yr(76Ws
zx(&7)C~nka=%$nAHN(et5bQNHIRK{5@Q^E7{f0YKzkS{CSvk-K3_HTn8Z>+#1(+L#
z5X$r1H0<ofw1*6J$I!ZEsJ6j!-8P)1^za=6!w<6`Hhj?y3r7rWDySbdI8k}<nBmTs
z|F1tYRFVIB*U%mc><NRK{>=9bc8h>EY2YP8)0E+>=h2!rOi;PsjG^{0jF~l5?*+MU
z_$C#GE*Q%G1-7kGmH;q2V?zrT*xo1$fF=jyqBAhY(YSX3U{1z7IvYA0Kl+OD?=Hry
zwP1BMx}3(Kn~_0@C3oYBB%pa1M|z>q)A&LT#=MNHDd**FTulcdA7jcO#(a&TpF-Tv
z_$I~b{f)y^9TH#+f0>>N<NbfZdBhk&=j)@!!kw@p$k<H|cBpX`y*aGMjG42*K5iTv
z18bP^dKd;z7+F*w6>f~7uLndJ+oWKLG!6~|G|KoV!9*J`(eE+F_;myfjWy0u-apRx
zNC1q9H-7X6$Vub6a0nzA_tW+JMB}Rzz(_K>)1#7X+(_Ak6ss|EJFruY8_3m6Gp15_
z@04-HGDw^@8t58)x^X>KUS_~17?Wvy;0a7S%NSaLR<<#6ALMe38IOVF8Z+tFnP+VM
z03_d-O3AqbW8nx$p|P2cv}cU#W*~mnxSK-#MMmqgQuLlP#?q0x*ckpC21|^8WP+SG
z)==&61>=$Jm_@0PSpt}g#zZspmKi(eFpF|yG1*jMY@&}SRvH&5d0J)M`ZB<(jnP#6
zS7Y>`gi@_hN}s5xGj9DG)4pU>tiS?YHl|t)m|?wf_5oPYV0`Zj$Tu24QbOSs<F}Nf
zZ!!k3f!1u~ZbD~^agP2zt;T=o+ZJuccDm}`Zq)ZduES`iS5BvKl6HtL<NHw%=rJCo
z`|H<?3*;H}8k_4evp%DrH^lpm?_8!Dnd?R_-Q^lErcy=yps`vC`5VSRsb=J+@y2Gz
z4;k_A@$hgNC+A?(ZKIt2T6c^;QkrSl=s}fvBgWGYLVVO{qR8Qx@#F}`#*Gb)P<YpP
zF$Q20lz_&wW&CF+Iwy@wwDkRn8RI%7<Y$d%=y)_|4Cn;RywU0j*89dQ^om_D7EzGH
z)^wyF#Ljdy6e{dZj%y+3U}BT+;%GXwfH5c2^JCEKY}!mW*j!A%(9grwR7wdcHxrYp
zIo(ZPQ?S6pwD(*3{*tF@JQ^yzOslA3#@qA^9pHRS4s?;+*YphqF#Sx=m7~+&bm$eV
zOn~WDJ75A$TOUH}h^a0BV@FL(>Hc1jX;~4#f=&NXq9nu=sX}L{>AUr49W#AQ>D}X|
zblSYaOy}q&VLf4rw*?J1eMCvg2-D(!(26ugCj&dm^hXUkqfNHoLn6kMM)}=X)2HNy
z#+hz0FvECLhCf(Nnr5kpJi*jQf!;*Z-HRYeroCTcos&&h*P)eSy6_C3Q%!=a5Kl8b
z@j6<ktfoh)JnOXSPAufpO}S%Os0`CE`5Bp}hv^fgS*AZIc$RIN>H$lRsbUiHxu!I7
zAoEOdlqktJt#}=B1*XGPDN|_bDTcx`CYdkB&YI%r8!N@8<8+In#Pl<L1M<A-m&YM~
z!DK!3ICx4;4pc>O(Nx}zwJbAzP4R(pQ+y>rD@@lY=vHZ}a0IC`oz4ZRHU-g3wZ`QA
z4_InVSu4@1GkLQie#w-y4k|92>epiu^`;SWB^pdw^uBI1Jwa=6#k7~)xh7MkwHLJ6
z)TF=+TTE^g(QY+$=pfi;T23#Lc2mP=Fs8%g{4dP!Gzl{?)@2%{YPPGU+qCs}o5~)8
zT#w1&K?qzk1((6XUK9UAK=+x>(vhp*)Zz?s-K1=W+<<8{9i9hG>8GqP_=f2rik;sy
zT~I+{$n-r``QI|}sKV#AX`&6}j_E53fe)KL`vvBYnAENyqo#u*z>Jwh8-X%zI<yMp
zu4xTrdnZgbS&+MDs(lD#(llED4O6C0a*d}=CVIKdnA#>N|1fL%r3->{rX!RpoHwNn
zVer1`Pjc24OfmPN$=1Ay{=RnRS83a_H@jv*z`<-=i<YCgfSyz*^WuM@$<@4Gi%vIl
zI^7C#Hy@+~oQIifhb8eeAEd~=mwDtXw7ktH-&um^&&Ry+0t9`{6;zz&Xa05#B>c?}
z>ChQqj;2beKyxES0FRhgYy~-L-b=BAAoI_IAi?IphaeDQK1drysQDq<%8r>=eT2^A
zX6+Fu3^U(a1n3jy?`5zl+?=usC=q4{N~KyO&5>_IQ<S-pY8Ru;PEnALF(3X8tyuFd
z`gz5f7ZpJ;-uw$iN>7?auJ|P+m<tbKEYbW_F2<6~kyMM9Y<|raHl>&&lCYGi=1t@h
zq?zw_L++G0pI%(2&82@~EZzJ!-9*c<n&T!Rm}yq)VQ`i?luAFc&Fd%ukYiro3QKd%
z|Ex!6p1HUNlgT$<xQDR<bHu9{D>S!JLhFoqQ8rM{nv;4!ip+y_gg9poe-Y}7&C9f4
zDKWqC90bmr6C1&D!8}Ia<0~~=AErx`7tPP#hD4cpbQ301Zm!ILM1}be`ps6FW2r!)
z${d{tmTL2I4M6M6OEj?el6hY$ST390=+IGb{_JV6G?-iegNjD;PtSq#iuou7ft$>|
zROZ)g{)RrM*<$WF0l8MQ-bxN&oB4@OG~3Pn!_d@WURZ)wC#(Qkm-+S^V7Y33@^ip+
zoBt`oSdaNVdW^4`*HG%X*Sw_!3*2Ycv;(`}obx0!T{mkeNH|~~vS3PsW@|c(xncf^
zB9=GJYsd{9GTZ)1@t0fXYlUduHs7P#xI5-gDM&eN-h~@aOGeD=G>{)Pe^rLDF*8p9
zP2=X*DQA4we1PJ$6Xwbon0C*6g|@;;a~Ordr_2*nz%^}t<2AHq%<K**nl-O^4C?31
zF;75X-W+YB`|tP7E{~$QVCE}fx2?tf4q)sopYB7;-lCg=goDMl6~xi<>o-v7WN}u*
zG-r$Cby(qI*+DNwSIZ=QKGe<f;+tS`w@gv;)x$Er8tOeQ7pRWQ%d&}_VQ-7d4f=d6
zPM=f$!Pj!<FJSvwc27dW-*WOXkN`{k6jtw;<$a1-9Jd^Q37WzzWkb+(!jcyQfpClE
zTXaTPI_bVfq~*U~G2bXl5T!k%Evq~*7GwFT9%HeVS&DX_w2Uu?c!Fiz0+vL}W~wo<
zCRuKFfi>Bp`~f7zGDp$WRLkO>ur$rWtO3s{%j@J>oVKi?Q$xDtsg(fDuy|2trp1Fi
zgDeY+T-<Dnmd?pJ7I_?0<XYM(#FJ-P;)qth#f3J%0?V6c!C7dTru1Wx)sl4`^ql24
zF{WK?`AiE^V!7%Ga^CU;#gZ>r)(pd@QcIQ)Fc&S0DEd@p2}Sm1Nx7wq!ul1KO3Er!
zT2@lJrpodr9et`TMW14<#*#&K3bmHMQ}H*bv%EvKT9+&?6lJ??v96<v!g|X?6f0@4
z99s|4WGNtrx!H1SCwN*c1`4&bS{|YpNt?yD0(#pmFH#Vz!}633NT=md`m|J+<->2V
z&Q~p8sIhq6mKSu8>#^83fLya|{Ssik7VAoI_E{$Bx$C$5V%30Nx6HO<q63y)!O%Ns
zSxR+&H!KWF*WR=&(!!=8%O`ZT<CbOpF0kCT{33zC9gF-)j15~Jpc2Fp%hEaM9kslc
z1eP(&%|F31ZaMP>I`3NUwgYp*5=y7vdzSsr!<b3SV=OCHcE-{}yVtDchA+sRC9x5j
z<}K^u(YkN>ldhR9SnlpX%g*Mb1%TSy{6+x*2b+kS(CcW^NL!kdjavuwI@^442`v|!
zi*)PK)kaKFR5zOzDkpKbDR}{%9yZ^PfW^~hb{U=jylm{~PKdWn4!vT1Y^F{@!q>)o
zFZBA^?4g*Fzm4r>Of<kIhn(R+n`gH`;E0W?6rD$HN~WPV$mR!xGnWM0G@rwiLTo;x
zSYzn_IJ)k*tg9~GvTT@IS(#R9xmsrW?7jCc%hIgO(sGsBu<`*!LELQFvNr;P$dE0{
z5Cj<l%2ZL2t+IK)=jEUCIrpCPJ?Gx%H|{;>+#ifrsi@PRVJQG+0K@VKn1PI5Izbx5
znD!R!|AHA$6oU<6l+cd;G(#1MF@-YH=z0!gT%x-ooMEG7Yy^W(wO)~oQ92?K#TYz*
zDUD{hpMj+~29Iv>c*Y`%6(%r-+Tmy-<IN-JOJe-)2)#3mf9AqaGGq6<P)}iaQS{cH
z%D8<AqGuT^Xdjox=%Qy?I^*|NICGBCK>6Ja#+!7}oM(7!gJeGAxj}FR3<W)z3K_r9
zE3$~OeICpgGcx~#!HW!yC)6)7F5raYw9AZNs4TgZkxUzkGDfQlM9LX+zJtgWJL7X&
zD^@c6|3qgMV;^PLt}@EmK&xg1(ob=Xae|UowT$QJ;aSI6;0~^y@%R5j4~(zrdc4jU
zxDJIz#-S95G%-F7#L$`<4rMTZgVFRE262-y`+eALVf+$`0k$%{Xb;fFu#eAxOgrOP
z1E!{f5lgYkPKIX{KyNV~{*1Z2%_yhRfIEz5DJI*+IA;X8%b558p!XPU^k}%xIPom>
zx*79dguf3ME2to&hw;LfXzXPy2?f{32pa_HXRNsjg#m_@1M`CnCwnQJ8e)W#-wzqF
zv|f0`xM6_7$BdPqz_n3EnG&F5j5V|w9cLKZV19y;*@nhR#?TB%PBA!N0L78nLir&l
z<`C^2_A|FPfjBeybI^By`R^=%xiD2!K;p{e&V%_w%;!qz1?I;5qXX<=CYusGN13a8
z0dtIbEd`>-nTZt8JHZ_9g2+kcZZ$yNnS0ux=fPY|D=<&y&}<Md=6e)%_Gb3I3_Ty_
z_GF0oGA9;7;S_TR9XRx3meV5KpE*JGSOLtXH|hKHfy^I2!{~#UvArO{%$Mns4`Et1
zLFP0wxgS1-GB4(X3uDfn3D?4z)<PJJV9pDG!APd43?zyvlR_k#x#<HKjA3rP49Qrg
ziOvzkF+=8n#4|$!@!Kabzoq<aBD3rp%0DDA|Dxr_8Rl9J%%?JCK@dI5e2cynk;eR*
zVx#HIgr)HN9P{!*=w~orq3~@c^V)iFSxgmu6ET|^{X8Udm@iUk_yy*>6wk|J^5{;_
zXFfxj-~#40I!9N?d@UUVEMn%Ig^2wka}@=+N|@)OF<+OMJGVjRGV|ITD3&rcHy~QZ
zoJB#Ma;BP|s1-~V6**sFF8dFplG#51@2i-MEiiGFxl#tMnz@WBRBM<krUUvKa~r+?
zYMF7j&{)UZ;DwRZGk<;;3JrE<7Dd~xGi?<8ZDgA1N@!xvrI1N8vyPU}H<&-s#ded)
zp+s5>^HsV6TbVN`snN!KjW)>bOolhS?_jP=hI%LS*i|@si&?oH^K_f}R{-qZVe05;
zVi)uF3Xr=@&Pp_PGwtklSbD&`n+fb5=FV|w^fH|&a@ogZErd)z(~UMXgCI~GVs2Q3
z#)r(N8Q>l<Uz!Uq9y1w{&>Laypd{HSvvL~981uPjfilkgfGQCun19pVG{v0#KJ*+|
zu1+xP$okB_6s!{~<uvs7vvzNX7tX9jv@$usnnl@&gRD1R0-6i!KdLiwWtl0{c!>4p
z18{Dvw`;&1W?BAUBgX3VhoeVXi=Kj|W2^}ZL>y=R^a>hJu)a^gl$>N8p#L)9&Kjj$
zrU&bHKYIUpvfiV^(_XAR0}OhzBK+W!59`J-V0>AQ-$COPYd{Q#{a7)5u<Ori-U%*%
z6-yN>fh+^<27_3=Gw{O(v$EGfFNAgQb)cMP?QVgkP}XIN6-KbW?1vYTto13-i(+}y
zQT`#C^>79BV_3hQg%`1`06AphSW9HkNMLRH9HNP=6>(@xV)f?1?ip4jz1)&n4=A;g
z!dkfz9;UL^Q-n8-6|@Qp>8#dRm_Nt5n2z5dgQe^SInNr1hM`Q>t9+0w)(YIy_G#HH
z_uUv%4r~2!czS^~K~+4tte<P4k<a>|7(NxSrcQw?WR+9Ot%x;r9(IdamTH)|$ohgV
zj}lh=bMWFa>*dwJE@gH5K%|WI1wDPrS<G3$tYAfZ!NL{Rp*zs4WE~?9?N?bhC~;BE
z@?Hs;8dgUxG_JAQZ=$o7)l`SRI+lpeqt>%>=u1u4S%U{b8d;BMgWbehNKf!)R!$l0
z-e9@qqOq0r$qE>3V^uo>tesUf8#B|vdh1t6cCutgF^F3%1MOvR+gbZ)Th_&@3WCO6
zRx0f~@3EGgh0J}{boyveH|w1`IP-udq57E~Rwu0m`dArHp|PL!^G&!tz?zr~g+bPI
zSEvuM9{&mMA#39yKtEzFrc%wvtaX%H9A?FS32ubd=K-HaS@zfI*vL5R<HdlPU}by4
z;YrpMePefu#rg>*9N1|S5OHKbt-}bN*sIu(bY{=f0PO&KFMVs}Ap6u#D7diiP(Z+y
z{pl~jKEw_W2bddsO$!VjVW+(b?kGEW2nxs8i*Ez$INQM<h}IMAFxu~)WbdTfVRv?-
z1jLiQ;!E^-u~+VbhBx~Tg;9OjPB_ss&6j<0IY9l{TPfTXz<v}7$w0RK47ecn`F3!@
zY)vk_4`Dk@$8?=$AEV847(0I_M8etI*FhwL{aP5^f01nSD`<^k-|;|eH2Ys#s>ZPI
zEP~xQ_Ci;P#IrjtpfQ2Xjz(i5dk4K@lh{Ku!JT1W3qoHq+n-*hDeSN41AwV)Cf&Yg
z*;OWtER8LsyW$-C_b1_f273!dkIu87pQ7(yXR;sCZX=8RqXIuyHv2rC*UDiJ)47XW
z_IBEb<*|1OFy4IjSSnx&*gaHRQ^+1$2(F0z$A1thX8%(RQo<Hdw)PS`npX6e+3vL2
zDP>pxfxa@f53Li**{hfksbD)gQv9=$9qxh7D)vXT3ckwDECi`$zm<o^8upT(Ff(=R
zZDNeDo?SZ^t~IbH2Ox5tZD{~ZBinBu8k^YRv{P(mf94EwlO2%;(!yRwtBzLo-B$S9
z#%|EVd^>y7c0hNq8|gx_cd|JH=)BE7OSk_Wb|rn_ql?{spKb^C_z1A?u@}+d&HL={
ze*)=d=X68y0h>Wzn(1LbLq%!5Y;OuZ^sy%?&ojVoqld^K`>Py?46(QT3ojnBx7h&w
zi2dzjpgd;Be1^VZJG*cuG)CE(FJqu%?BkR0Vw~Ny6`~XDLMyN**{AB!H^r`9j$g!q
zllupV6Xy%6^xn^TgF=SRoQI7d2RI@0!ye@9q$Q9GXMQ*ITsh$@A?e21^A`FJb8_B-
zGe<aEH$dbl$9}{QGRHW_X%BIdBeH?Ga|-AU;=$?L3=L1t(P!YW7pG`C9QNi!Ss~)X
zQPsf1Q=BI<!1-~uNul7+;S^!m0i0)EKw}{1(r3^M;@qS~S}>=LQc$NkXDC%3%6VxA
zxG>H~_7~w>IOpbOcoD(*;Wk<$Ig3wVFj1TxR`f-4I-)^hI5X(670Yp;tWg{%feQK)
zI3@JhNaS2-fnE~FJr(|*;q0WndopM759mwb#83zzmGfK<ETnN((q<!_vm+h;p5v@6
zr5Jbyr^g1r&vWX>AezltNrm+}95r3D7dUf$ppnZtK_rj!##&55K4&j^SirgIh{hsL
zdmYq^InPkC>mp}e63mxyL}38C#Oe6~^K_ZBnN~TaobX4GEa$AIms$m9!yL*#T;aIw
z0b9vgD*|>EC;draU*+V|;=h{nn;Kr!Z~`fRe~lAF@$Fj92ec=x<Gl0`-ZyZnXeD%=
zvt=2~H*&_cXl&x-?*Ldc$F>PGbAvO<19y`n`~iKf9CH99+c@P9DE`vUIYTSB4$hIc
zf!)cONddh(9Dgf3?c!twpz$t8T7<#e<0R2a_de%E3S@M17E#sS15PW&#d|p}#o+ol
zOBaLmbM`gD!~o}6D&!dCTzdm3L!2rl)E{zIQ8Mu{CxG5K_F>MJ%Rn39d~_MZ9_6eH
z!t9N4aw&Q>&Z()yuqQYPqd=SFETpX76lWt%w*$9;E=x!5Y##LXa|5Y5#F_gWeOKrJ
z_XH*P4sz#Eox2OS*%_FwTvZH24sjP#VCyiq?o)^yv2!)2fp(PZLkqEETn23wk8{Oa
zAmh%x5C+ZzqToEae^Mcc7k4l1HoUo+CJe@hdvOK^<ICmUgC#%i&R5~6KX<AFdI4NE
z?d<}&*C`kq#ErU&-yoQ~or*O=xOa|0A(U&6q!&UMcL9BDD4d%_Z`ug%ehTVDa({al
z`cd2s=U^$CyPVeIG2CD2KzA&6)Ekm<-0xmQUpzPWLkuR7D@uVv61Q;}CeCo%)sRf)
z`p^O}h3ic9=BZqF3iY4mI_w2lI`?b)2F%Gh?)7Gn4DQg^&^XUsb{wLaTqk-==Ws9n
zKeWsJuLvT!+;3?olgGVEL9=}BHOh(?aKHKqpoQG$mtjmr+|{)0E$047FU1nB{uzi|
z;>Jqg;bm?t)vK0r&wc=rGOnCKVW0}GVKEf1a0fN$tmK}d8keiwKzi+0bB7d|iyH16
zil1KN9;YX2Ew^w5NF7&t2iWyo9&M?wbALSm(#SPcLa&MY5uIRb=DtG@#v9xtLr}QM
z^^u^jg}aA#Wo_KWPt*Iaoty0dnGWtt6m00^zB37Oi@Syr=(oAH<?!$>H@6z@-{TGn
zLGE+io8VJ7*SZ8gJ>cfkjnl(*H$k$O+kGEkeOxD6D)w_f{v2eG`yn4-L);JY;Ne5A
z8-=nSalb@z&OYri*OUdA5$@~5kQwEwv>;<#x4USZ;Fcsnf08Ss3vr4&LZ7s9;Jv&9
zKa3-<pN<nb@xH$YZa>dJ35x@~;e1FQ<i%2m)rA*44GONjld*975YMLwU~at9Lzsla
zyhM6}+mG^e5{Mq-?G8uhao#R^`=8(?&_nwqFYqb!x$`Ps1B@5%yMMrW^F-?~P#@lz
zZQy))aTH!Z#oMqN3Vu9!JUD;eS_)DG@MfmNnLwV#9qPfn-3Q@C2=BA`;7;=rX<-s-
z=QU&lEsPhFk6Dl4Nps;_BroDScoD^8P}($xcVZ?+7|VP3JoMvun~uTnc;1r~s!ZUi
zDRY*{Q>=!15>LhlXfn^T2Pi4LWV(M+c^BS-$XVX!bf>2ACZ30f={)TZXgtTWUrEM=
zah@0aEc7#ZpQS)Qi}z+N>}K=+qSt;7ubhd-3p|Dg(DHdQ0bmMvSy!N6$V+5`E8=nJ
zb}Hr_&jh*1yE+NI65c<wl)uFLA_^jxd9n|oUdoI538ako(OvYF^Io)PVN4ag>m6vl
z!W#?5TvYO2qeyxcZw{psuJWw4K&$2*SAx{=Ce2W|#{2m+NG;Er510nt+q7@I&O1gM
z`$pb|&5&&3t)m*;X5N2cFn@!0l{PCkd8kOh4Zy4a7lvASf%7Q;-o_iFa92BTJryx@
z@a}V9x09D}4A{4LaTLtG&9l%KpzrX0q?12gJoB%ZlDj<V1?b)5`O^97`@B>=)Vq1F
zyo1JG-V;=A+sAVa2G`G%(bqEuc-0ghALM=XH^>n0o2B&rd&qn1Lx4WweY+c=k9mh^
z#W~DN+Y9{>-pqZtT1I)X+3;eFcV`%l<Gi0}89KrHQ3uIM-kROurg-{oKyl!Az7Mw@
z`IS_Q?!+(a1Gk^Q@_Y0h<mb|2$AzzZ7yi2Px1bCL-=E+wI|OVu{wD&E!~9fQuOH#d
z$ly`_<1&zA{Kj`+;yC{sx;jtr)x&6X=WiruJouxR!Flpid!XmV-$I8ey!m_SZRW#o
zb_4O{H*J8Ur}&@KV#kmFo&&t_=a+k<&mO=Jqlirq|K(Gds9^p#v{4S>htUe|G+$5q
zuu%SCs(%UNTguTG&Y$#$-3Y$-SCEY4mr(90ia+x@`l9)B)`P_I2WXiR$Dg<bE}kD*
z4%ZU+5<Lth^1plnB#B>@3@^^u`48m~P3DJCt}TUsyc4ad{9-yzbe8`XU0&z-S@aCe
z;LoCj|9Sr7AK^?Uf7K%lJBvR_1ti)051vC~4!`#&ICFvj4^^h;@@pvAm&b3R_eehf
znQ=%K@|XM$w~P3j<Y+AB+uxzg-9>(_8wOg!w|7G0693P)KrZv^wqu~B{FBR}QO19p
zN_)!r52#+Qg8#V_^eg%A3}R?i{Og<1c$NSB8}O-`f2#y~HT**QT-7yxE|nhF@)MGv
zP{%(^+0S}@N&_$(`2F^8A#<I-mo_v_{9TnG&HP<05WT@aOjqDd{?i5ETKFse25IF>
zRztCkU!{X&JHP!G*zMqV_Mx$pf0ka6xA><iG~2~Ll8+(X<v*kq{XM=9Ww-A0T`BS2
z%`bcf<N^QX`?O{2;rG!psh59`vPOOUcj^0F{rnA-Kp5c9qxI_$|ARLm@{sRc0e>Iy
zwS1U(%zrltpu_xbN`Q~>8A^~*{<ri+xiNmxD*zkkC&WW!g1?jE)06zv??D^{-Bdy4
zC|J0W>aU#yac={3zu-p-|2PYtq?q9WL5?5DLBZw<SaK1(bPO7<g0nPFhXiLn0k)gq
z=~Rdu5uBv$@=?LFg|Ku?usQ>c#|2$cP&gsDuny#;AaE&W-Ca-<hmm;*<Xb>I1%qPx
z{-BrO^nRdu3-(f;=ak@e`evA)Ao5v^*Iyu_^l*Tnj1mZef?>)(1PSCbFv4KL(}$rD
zBKRo=CQb`3Ermj;pl&s$D@>ptf@Fl?b=o9F3IeGfD@yRfCFn&9`YB`|BlwE)7WP=d
zHVU4_2^t>2{dmDEv<FBKEL#VXD7f)D6q5umQOY1$5K;{;Mc_|0NU4I3G>qb`;Abz`
zO%nuD9Z9;Nl|I3BPH_4un9mUG=VRFC1(T70&J?(>fk>7>)drCqK{sV1F4zU@;$bOQ
zAZ`Q66XerkIA75BFGzvFlOp(qf{|*NC=z^g7^GOR{Z}Yn6jam0phUoA0=rc3E3LlE
z1k327S>=MrNqATx@TKk46~O`)3|0#2e}ywu0^@HGxhhy00hDTi{bwqKt`X#lfqhM|
z=>bIR1cw}<UoS}c41EoPuy|l!7evu(rBM*n0+A-cHGhz1!8QY?^oHPF+Qi-zT=^Rc
zErNgPdEP3Jq(P)zP}mI8Ay`J=f9Vt~q9ZW31e;=^cU$0Yr)9$(L3TG<y99yWuyj`t
zOaI;Ep5U`R;O+~)nM7Z=;ER7idIVF;(by|kzY>=E1c@FPMZe&O%W!Q#&`A{_gM#<I
z0p^h4*>mveq2PlyNInuoegpN#g0GyQFf4eMf^B1h1ZO)s#{~uSlS~L!P?UXAFsB7F
zQ-V5Q5C>u2w=n1^d_*2P2`A|@J^O`*z0h|SZlKDb1Huj~rqo4PPx%8^VJEFr4++QV
zhIJDz+6T$Q!jAXg%n{*=JNR9X3a9@J%wxhetLXbL$Ayu>=sY33Uk2=x!c!E6@eo$i
z=_^m+JQGZK31z8J^cKEcf<_-9_h<O)EBy9JaHoW^WYAA|DHeME!WY{yc>%%`^tFRP
zVS_*BB3QUS7+!=3Tg2c_3++5`p+d(*djEw9jWsY4E}TmR@)5$VNsx&YCeSl5N;r#F
zXVF4uipR$Y*V8L2Ug)|Ib`yjg+U6$;H~xu%CJ7Td;l&wYFD*5bg-Nt&PZ4G|KrdA|
zLC^fN!nPQ2X~LJQz@-bV^lG(d2tBE=;=C}R7$j4;gI4HSLKW4dW(!x*+cZb`DjjXS
zAe=8iU#{>w3Nq#iUw8|y<qL~gaI`?^L3^Ge;c{<q#X=>O=U)__cm<?H*h;CzOTrL(
z?OzsN&W3uaaJx6u%k08E-+`73f8Geu3gMO4F{Ud*uVR?55+bUBdqwyp2YuDT4=6WL
zBkZI!#5JLJB0y_}#X^ue;bl4vSTB@00lPuydkWlj;kxT^rcwADy<u+%j|{=Xo5IJm
z8f_6aP>ix&XiwXT&JLk;0Y={`9Q*^MTe#&I3_cJB((bB9_%9uw>J`32k@P+x&j`{l
z{PsVP0pUm#ObiMyQDxqcaHAX}d?<X$0fTrX+_eYXW8v)C5E&Nkp^=RU2WVeED%`gn
z>SMy4c6#rQ3pEoU6T<lSpfM@rd;>BibVh!7nuBQ07HBw%Zf%8#lSom7q3su`ccRf*
z^ni}x9uTo9D|b-zD<5NV5zV3Vimsx$RB3uhbYc~Vo2ZL&Y==cx>FcLQM5B~{KPr0l
zIGrFkCi14LhvOm<J>X7=KBpY+Nl`&48r?+#DsS`<b(zuUDGL1+`d*?~+U9$UW?C@$
zKB7-zfZ{8vQ={>eXd1nt{X{nUnf*m8r{H#gXc^`I0!3}~3=0yirLx9gQR)A`KOZ8h
zp+hsLMW51-9xD2#2B2Z0cj#0@xafsXp%Eck<p=#p(Z@ePGD<W$0Fh{s$D6>85xu(%
zBv#}=0rfah@jnoW7p*^m@g|5O8!$78qLU7AJ4rNu1tiaiR?b6XvgrAxwEs&HJ<oz@
zs%Qm0_0Ecp`(pOeME_CZAzkEGg1&R2=g*)qL-Z~c)tndA(K<g<G>uLiWr^<nipC2f
z(`q=HD;l#yFHht@250g`>!^mIKva_ekwVdWIr@r3v6SI27EPz3cl$-rrys+q649%)
z^1CE5J%FXlBA;3~Tq^RUl7uo*9$jqZqBq`zeuc=|1iM#6Qu=^IrD#2^W~)TAs9gQ3
z$d&HDYLOQgjWwdX^ogfyqL(Q_Q!6s9gBNw8d6Ph?7wK=KvB56-Ee5UEMZ3k&XcYa^
z2$&{OBqf`hMZJTtdqeb#1)w)YKT|b!i|EJI&~Fu0)x(Q6(ZUv(Xct|kcw&d>Rr*jy
zr>K^u>z0T`m&a{Uy9j-EL}|g`x<tZFK)EaW>rFJ?6WQm|3;VukHx*QMi>j#b<$-9u
z6fixaGjuohiqa@O)hGHd10wyRb+phP5HSY84T{!Kc6vzkQ6WSgicIv61s;iJ?1G1n
zMXyyuWLV@(v5FCq4-Ifs6qkp-G10<jFzRv9clJccOo&+YWSkU<sJ3lNl=&(^9mJ(U
z&~OyH9EFIJ_!i|$_lt8^q0d>|x&WXD#QP|8a8NvRGelg(DgVJWSMirK!5tDuMSyb?
zuQq@?EbgOV-4XHrL6|=(Uf~8uPl)%lQ2gbjIA;v4?&3e`2#kmLXR0;v6uZoThL?Cg
z1#Y~>j}Ak`N8Cr>pz{@{{=djX{5<^ze&Wv>q2Mq6n-+Ni;>YwMqCjym-S<J_pfq3x
zi^aZhJ49SW%em9y(Rmnss5t2+<^RIOYy(8Y#nUO)5h1Ri2x6qT{~M4f@y%y(2}Fw{
zsrDj9e4oOZvEn+4dc}$3)aZ*BmryxMf;im;B8lSI3~))}X-24@5xWmTGFiM}I-pa;
zX|!8N6|dL<?yUHO1+@N56Zg~BCtW<B&JUgwU%Cm0GsMmm#XT?Hb_$+mir;(=eOcnD
zH87Da_M}*SjyOvRkqhEDin8a51@zP_5MKy}LZSFaI^j_y?owlBip3FBFnUoui31nY
zO2pgfnSDtdL4_;!%VMW2=$DF*(}xkt#BbF?v0U6kVVDYW<SB?=5qsBRN-M>S3}~zp
zKcu|!Rq>qJ(7z_$BLb-vhfxZtPAp==(R#5>2TKiN7mChb7vG`KL!)@Q9?mq0w_XHF
zvv{@?eK+jld6enDDej>_MvM3f{7q{WFZ}{CZDMCss84GbBbS1kOFWOxQg(_1C<t{+
z-10j_Zi_9n!M-D&_zI*;tbPa1+!c$dobsMH`#IRXFaEI}q+2|j0@Dw~M`yyr9&!2S
zFxxA(CsXdJPdu9k(0=j$B#dG}Jd1vVL9r(VlZM1C5omlUUP0^aM`8~uXL&4^lfT2_
z_c-82#OJv{85IY2;`bdB|41Rnaq-`WfjJ?r%)vk>#aC?*nG&x#0@oZQw{`*AQF6rI
z0Z}K3eJ-5ZFL9w-JZFgmy$ugYu2Y`qpd_9gc9HZvf`+RkZ37G*lISVz;wGv16J8va
zq|>ADh~(RgP(Lb3KZ&6ola$l)=(yw-eTnOY<Vz}NJ}LPj8-4DQZ9$Oqki0Fk1I<&i
z=}GwJB@umqPH)LpS2X%aLg<a>E7?IXrz9P9u;eFMx($;4l3mZje1N2SBS@fRFJ-rb
zB*(4;G+1(VE-ZyehKoT?OPpyb5h`I&on4qDW&_kCC3940jFQYdOW&V}mMn3BXpAH^
z7z2%!G=B#3agtLba3)?-eg-BIBm-h_iIN4m5J{38%R=KB35Q})$&yhz;h!RTqy<W<
z<XPH~oRy5b0VPe6Sqd&)q6-FhPO`uWb~7YJwB0=~`Qk~+|7A)ReF>N>$qq{OWlK&`
zd4G=N2iiYgkSJe*Xs+Zi7hIlXFGV%;C2#J>Kno<Po*;#i-+l*nkz}h6%oj@}bmLr<
z-2DqvQX+Zd3-n!*@Q1-&mRQ!pLaC(THGq{#W>D3hy<D>59M}qpxEt74Bn#>>&y|v(
zbf8s9oM=saRgzB8#cIjtei%%RB-j-mUX#?n4NJ9>7+Op>NS>p#<#ox%aF9lczy*3u
zlHQHzYnJ3wG29KweEPt~P09B;5NVNc>3!R3mt6e_qHU6|DG=B$Iq(N$IwV)Vgkq;;
zK3!M0B>&Lqy4#YwbS&qNWG)@8>XP)2fZUZ-8K7`aVjcr`U(%cjux?4?X_$B*+2s$n
zdnC!xQ16vAR-vy?a)DM*{Sx;#;QfHa{>wSY3`$aRFtj1b2@07!l)OYa+((l4o`d<v
zk~ioW;IJgB0h2f)dD{yLqmrK%qHj#{2jvgOB?FWunvlG98G4fv_9lQ$Nh0Vtf`fEF
zAAOF}rvsqiB%Mo{_Wja3t>|->KCpiQv;)$w>7@Qa=?=<Nx=14yLc>+sx)OE|Nwfcg
zh?~^$NlegT>HGAOIU@abG0=`mA5rnbF=?O*ddH<Rn$UPc>e&o0PD*V|NV-d-XdCDu
zo%c8FdP)ydMUj_ufTB;{(%kJ7|MZdWrM#A}wD@PhoRYfF1E`;rLytRuseKBK0aAMv
zU;?EJ=#v~l(xvpVgkb4aT3Uxl-=ziBY3bct;6kOFC<7fP-EtCKxU~CkC`3p%e+%=G
zQhhg2qNKyeF_u^<dlS`P$4R{?91}0ixe50Zr1vNYl_*`RfcYe8)O#Rjr1j4MG+Fxf
zkI+w%s(2u&(uHBrJ1hN=N{Z5?uRQ^hE)CiT*Um{lp<qLXw0aY~I4|9@3DB9+U;hS5
zmb9NPfo$pLIE`zcmLuJe1rryf(G*t9m2RiFZJzXcGfd=5tLQ9OfwY$vFNM-=b6}!K
zI<^6z#nQW#=({NWm}+55q_5J$>yq?021G7Pr_Mm3R63x8GiB043t+HZx|f4VsF1!|
z4hvVLRsEPXd!@AF5S*%#rY-{7Rp|;VI;*8+bl=xV?}x(DHEAgeptaJ4-$SHMx{6-L
z^->4AN*biRTadgiojVO8&C+od8gEFS{SBBmrT3`trA7Ku1YB#CE~P9+n>1<=uC+@y
z48oZXyEOk2T<nxS+yj_f(zmH7;I=e_7F&0u@oQnJOZxF4czRblK{cB9r0>v&L+?w!
zX$0w(79ND&18FdQ8K6h{UlL68N;iKBg+A$#PvCFA^oKE67?9p%0Blg&v=rutq^qpp
z9!l-|u?U&=NcuO$W*<wZr^D{BltH_O5$TrW=o^*p*@eb2X#=GU#-%^eR|h7fi|LH*
zq_mbsF(qZ6fI$bDybHup)=J?8C)pv|nD3X>zYn*aWiL_W@qlcUex`%6btUk^MfS9P
z4cu^*ZM+7wL$Y6}=+{j){u@9K%XZNZb4=Di`Of3A!9DQegsdnL`X^=OwCr}5&6);h
zJY<P+X!MjtcVSArWUFRE&s(<SXF&VNYW@bauPlNt(o?eLDp>H7-Ae<Qziiho%D)H5
zN@*`0C`;Lh@rKCCf&hA2mOz`OP}v_Gh=$4bQWaddYzD<DB4m4m02(RFc7TZ}S;AqE
zXxX|DfW^pOrMGviY}qaN6ert5ncR5U2SgHN&F&CMl(C<|=#ymc{!HH=JR|##3+!YW
z<0W{JB8#WGj#QcV2)MJd2FgUG$qxPt&~#Z$IEHpkc5n(_WXOCdReoN!wjCmwvM4&&
zmL>b;1%PGCylF+BBU{aa<OSI`)ey;*C7l4tll}Y)MDk^Ga9P=>707x*pjar&q6A)%
ztdySQ#j@u{;o?QvI7OyPWFz$TsY|l=CqXXDBK`nqsq7IO3S}}W?Wf9RnM}A=A^YSi
z`mV?}zXpFRW!uJJ>8k8#2`p60-h3LQMz)B)sdi0vfXbWfwX*MDgG`-lwg%&^m;FYm
znFiT%8t8S|0Oe8}Wn!A(CfO+6f6X#6W%X{zWTbafW}-BFi>!vOgjSgs<(xZY9hA`R
zlo?_mc}q6%1{!b68uml|j%>X*FuP>W(lht2U3QM1BKKt3bY0$;t@VI!-Liqz81@5M
zITaZ7$To<;^~z*NAkrsWPBqf~GHVN924vr~LSay5dk!c=vLQAaAIkQ=2fatK#3(2{
zmZek3V_4QS0x}}=U5vg_Ssw*A#$@)@7NCvGWQRZ|WY1K<(xlAM8}3iZI-CINAP*S@
zag-O*4#-KqAR2SAUp_Ss1!wu}WHcU-e>4Z62jz9C=yQ>mEdaKw{8Af44$0?H*3?a2
zJ0FsV<@sx1;fVZ83L+hqKV>h2%rW^Zbd2e^JmETIPRQF{hsH_yRtj*r%QwbggdXxu
zr$IdBPta=COa2G#2)yOWOpMn@zAgeo^Oeuo1@oum2gd>CCm(wkeg5*flsyTM=hC|(
zQ2xaVm=BU?Qwd_Q{762<Uqa-kD0Y5Y9!hb&Q2Ewt5Dk;_sPZ{nzVSW`M#!Hy35`hk
z^R(xQlCPo9A4bcozJx-IJc?ebvGRHjypNL`hA?^Y@`XOYOpvc1!XOgmlgZ$c<WC2K
zoRNQi2GGg!Z!;<WnIc~k4gFO41xk&cl`o<jK25&)32^E1&pyIH&&h9I0LhR`yU=%D
zK1KVBO!<2^U@1#Jmy#jb^5az9oFiXO-=?@AS9n1^SN;}7{`2HdJ3%sEzJCwAFOVnG
zwOTA!9-;FO7v<l{(OM!Or@+l6`F}=eT$WFIz|&Is_m$`?lN%h-S1y0D34ImvL_hRh
zk#mY+sZzdUFGg4;-$>iItMcdruv9Jop%SD<?(Ye`YjS%dNUhvE4+?ei)P9(+m%pC?
z1$%@1rylryU4FrWd2W;^KSpPhJZ}Z`o8>>zcKwFD>`V0B#3(S(7I{Y=6kFvxDBaU0
z-!TiI?efK6fON?FS3<H=KK=k6-jZJk!Y_GSE`1-EcjVG#@S;neFb0vk^3D?wxo4N}
zqbS9F`KuH|>y|&y0O$kxs)LZ}k=NXX7rpWs6d3E1e@OMc{qm2)K?da8=_NBLkDwR*
zkUZ`Qpgol9zX$h7?nCuWkL6d`n7m>6V=A~Akrz(@dQ_g&3$QWy4jUxL<@Tp&|2H9j
ziI!KBa@Feqos#Q#P;^kdOgSJ&#nY5(a8jJQ2cPyU&LyGIS+T?p?ttRx=g>Q-c=I`M
zE{cgiF$u1Uz4Y2Yq*$a!qnqN-D`-5d=vfYOMDg`Zs2^3lM(ONhiZnZ&**UJzevZ}?
zirpJw_oO0j7dqV)FVjZKL&2o;R-TIFH__*<aHgBXM^QEdZu=^B(9Ly9v3)hL{S=>P
zf%q$W7o#yi@r*a10~LXEZZ}BLP4D?&g)0@>geVqLM(DKS`g}WRsKP?A#xO-MRd<Ce
z0$0F9grfdg*o{=^;xNJ}g_+i`(Te94n7tUqr&2V=D(26JPjQM~3R1)?Udx3@g5oaa
z;Sv?`{SZk~ta%M6XB3Yqo0qJJp{GxZqPhirsfrjToxeS+;Qk4NX^Qk8;6=JZO`E%O
zipy!h&QLULMc;YFQA+A(Du$`5EK6~Y9vj(;A~KPqI7R!g3yOvBLnK!*d=y-sVml2q
zUy(~?RRxNQT986T*E0YsQq)g_hsBD{c*;LqRFqJ7zC`iGJZM}}`2P)=QibUOOq3}?
z_o1;|QBR5N3dO7%jPQ!WPJ5n8#qLZPtWw0Z;%B<5@XY~Ntw^2+u0~NtKg>17%d}0X
zRfNRA(K<ybU3&G3S@e=<Q0yKDiv7A`51m+QR7l<eX;K{91C3@ynlCKfP<%$;pu4H~
z`CSaVMKMefwN}M^dg`?)wm${5cE!7O(Cbj#!)A6`r{c{I(RWL6i1sYE6^AKDcSrH!
zD8RZDZ`T3ru40nvsqQJ7D6V$jt`JlCT(@Gu6_5vte<%{(qqsT`zV#~he+CnMic7~a
zw0^~3A7U;B6#jIr4=SF$2%m-&+BHyks5qPng-42>P}qH}m^BW`VTI#T^o=O0DE&XG
z@SFpYF~txq9>x{_ZGaaO3VYV?5S>&Qav?LNICLFOIVjiCyUJ1d8l44kR+gyIctF|h
z3xfxh&uj&8QQo9CfUA<b1l%Fzr?iW7Q+}EVe-A5r=oH2g<=<4%a8$WY0`8b{7X{6Z
zE9cQR`-IX)dw`S5_w2rqaaZ2?1+(X&%%EkRr!sIlJoQp4=ym3;4EKhJkMagBczu=8
zC(w9GDXoBrpR#2x%=;_1QBpBL8A7YzK;_|Y(HEqY(Gn<F`A;wULX@I%kkiUiTB(LA
zfBFMpVanhobpM4b&r>uuLirShe<GE?6oEu37cPf>v~t}Ka4kj|Bm{|7`cNTAoU($B
zmnJIH762wm`Q7_aIHN3m7mdlvtxEuwqWqmU2B}KcI7H4WuPWhon$m?zRnnDi@gV1v
zUA|O*mZ5w;6i%I2&U^#<naUToLNQC(MTv)OWfsNybCf%x0dqn5!6+JYmCKzm!aSvH
zE*kTdf6{GOp!}1Hg$tF=u@EUzu1v+O6)VlrnDvXw5qdk6C_kfI*(K#1M{t*wY2VQQ
zA1hVn(`lJ9<r=!h%az_b$W$oVbhTVjW-)+Wsr02dah1~Hcl2FVnvP&F)yiK&FhMoS
zs0cJ(Q|8e#uvVG&5m4%sJs+U2UfHr2>J7^0$^3QYqKlZBM&&$8k~Jw)Z@{d*SvmbC
zWNs)gMZv^P<<X-+Yf<JMghs2fn9{s$%EuWHX;=PbL1Txq;#rvQRIX9N#4Y7A%1L%9
z6Vf1gR~c%;blp=vn*fyi$}1G?>sH?S736`^k!n49l#X;a^(vFLf%MsxGjyQ+$`q<T
z7*K{)0CZ3}e-V5eQZC4V;zMQFJ-GHr`4sA9r#)8wO4V$`%3uG2!4ajyOAr}V`u2c~
zDJ66?cw9Ml6ettQ)AYHVN##lp_%x-=WI)|PHRB3I993b@VSb%d_IvmdrtMcLXTrR*
z>Ss!r98hhhU*w>QO~(LTR8Lg{+f_BZ8ybgHA5DY4o9Z@IbskoINkuV7RP7v0$x&5K
z4Y*^f`Lu{WuKJXgRlcf5PuM-Bdgdt*KUL5cNcyXuy9cuYszCdX@GVf)M|FNds`Vd3
zKUlSio_ZmwzD?jxt1eJRH&nIt7|e&MWO8ufs^zUvh*14UtGh^58yz`_Qhj~~gNRm1
zAEGZt)isR9SXII`I1{JZun#0&Rl5}m395}uNG7V7FWcc_l4|uDkTWXlpD>uLQvD1r
zMODm)eyYlgRu*SfuTa%Pno41T`E=D*+8CTuWl$PEL#3dzP3KjsKgL)xRXYyCM3!p&
z1WaVBmeSprqk3gM%wJGF{|-i$tJ-%Mjd`lePff@Dm#+$?l~|E#8J&?RR_*hJ7Z+9E
z($cy_mG&z@FR9!p`*~S4hw3s)RdZE<DN}9PfWC6oWm<S%QGLyTNTup)3Jq1M_R`th
ztE#szgH)?tPlbgV)yBu*uBn`<bgEV*d6U+kbt-lM+^<)Cyc*^kRFCO3dR<jXTY*N^
zzF1tdO{(wGG3;hl;~(g2Q3Y&8U#n`Ivaao__j94%p?aR)-kqw*A&A^kZKH(!ZPgJQ
z{Jo=El?jwC)h&u$-&M6y=;5AfC)LK-@2g&mgKyocbQ<9U)!TlM=~3ya45n8lyAIGk
z)h~Lu*01Wh1CasMP0F4Qs{Wb_Zb)?^5NHooe-?r~QawRMHIG&MreJ<pwQeC?8&MTe
z^l4P}N(U6iR38-rb6ho-%GD?AD$ixWo>ZOTW7?)v_bGPgs9r*=N+-2@FhuvOU!{oj
zLG`Q<^tq_lTmrVMdj0`;aY!wqXpWou9SW8oRu6pya!kF1O7f1YMK43-gnIc85b;o7
zTZc*TR0m&#h?lxe0?u1)_oCm>M}6iRM19q*b1<c+)V8HC;ivAP%gbNA>l^qTpuS6~
zf<W~f)1e=v{<;bx!D=Z5#zNG34{)c|-ai2)RK55iB*WCMOQ0UE-qr~cq5h--1B_G~
z0?-$wzDIk9X!SO`7-%u-r+!0ctU8=h-f`+A+KI%gU!X%x3F?<AwwkE^J_@cSsfXW!
zGiTJ%9|0y=T}pRqiu!#@+NP>!{0#1_I_G<EX=-^Fpwrd+!T@$o-A5bE40U@wM9!-(
z>o7r?>W>an{vk_UL80Aj_4MZenyapqLorYN97VhH)jQvY`2zK^uRsdbPkaLGBK4MJ
zaK-AW41iu#x1WZiCF-CCkW1>33lO=i9;7u_sd_!FLCVzWdXRFpx*4QG9ms?F74@EU
zdjD0b(<!iBrFK~iXRfNdDLGNCKKUcCYt)I^0KKL@{1@h{RxJvJVx3wa1n#=Jn93p>
z)iJ9f(xjG$L9bceM|Cqd)b&q7{igcGPax8wF0O)wR(1OmkZe=GMX8)l_3<a@{dY?}
zMW>!`tJfcfOt1RkLSXl))1Ct9R|h@~{ULSZhY)$F9(@rakJRf{q3^LewH}s+)&EeO
zc|<Lp4Q^b`*TC+C`q2!KNww|+C^%~5|6$lpnjShqx?fXIX=P_k`2dLhfabR!fp$>C
zy$aD2nt}y@IjL!+M2ov-^)i_E(7crnzdbd^99Z(w9N&RHZ_QdNVDZtky#_sB&7~%o
zIHfuMJS6=z$0*qDuhG)BH$W3Yd*MLM_zg4$Y4T_)Lp1m3T03pmEV+o^K2+08(Ty<8
zA5_Z_uGxGGT!dzro;T5&<sMLs(FA3oFIJPpMPHnz=oTD}*NoFVC1}Q|pfOSNG!^kA
zX`D(Saz^t@Dio46w<J(c(ddKFm#S%+1@5e7>4y+W)7Uk?Lnd8QM^Tk?8mCq`m7$qO
z;h!vxiwL3@G|Owj<!TnK1Ig3;Gl5CW*Hruku0ZogCqN4|FaCx}DAEK_469h<_z^HK
zYT_P3y+pH<GWC}<ekb7QWzAPq8c?d)Nz2|c&5QQkuv@M<`xP`QG_N0k%oWYPHNdXa
zto{o6RT{Ac+*QrK8uV3bayLW2R`bhgkQ<svT7BQtxIT-~w`jy-fVFCt{)?ftY5t_r
zsdmk*4se~CwC~Y(OT(s<jkh%$$iq7tCpP6Dx-_XDg51@(&?&cj8VM~o?rY+lq47Yo
za1;7^G-)nyxL5N%EnfOG=V>ncHRCBTKcLw}dGJBaU!?#Y(%k(Qu07PW90B)8<3wxm
z$D00an3)kxQaTz(HM8j@F{V-fMeo0HO~=b{aYFNmg%M6_s{RJ{l;#N{4%+Rsf^*dJ
z^3dm`U2TB=er?Ae0Cm<f_M!2Bc4im6IH)z;1E`C3@h*7ps%@sL?2tD16eQiW$ESlF
z(?+a-7bmoV^ohZf+Fz$r{=r>)ijK8<XrHE7u&4GD3PpQq>#4HASDW30!JN`6C^zA!
z{fP~1e=XxZ^aW^rvY;2J%@=_LX-BE5ELb~HhhIBHdwVfZLbU-DwhhxZbweavtM>y~
zgtlZ2)FZX(_c6crC~fID{EpVv{t6Q@+Q;F5iPZ*C?O~jD@!Qad*ET)@m;~+LCXgiU
zS$a^M(SAo0oUGmaIbc$>>kj}lRog{-r8I4VBMhc%Q?J5{bJ~vc0L##BItP*S+R$j|
zWont7;Ii!6k0M|&N4tX3Oc%7aCQMtdRzp>Ad0H`@InCFW(kK54wCxV)E7WeGGbop|
zTb5uhE^Fr%p|4b1Nq2ggc7!V8%eAxV;dez_L9hKvZ9^;is<bI|qPa#JE`a(q?N?Mv
zRI9ZI)4`=W?Mt*ouGfYXL-D%y6oo+>wFWw`+@wun0OqE4<2&eU(R!FMm{x7v1njnH
zvni6-u8q%!LWg$7JScQ(*X@SnZEcMYB=2ZnnhAqlFps{w+UIY;i+kEN=P@()wLjXk
zLA$k&2Z8oL`xJ#2dbC<fQ}t^@DHS`QRnqo#Q0t@u%#il<7r=g~E$c+zBkf<b0~*$T
zNvW?9Z9nA}N44>bATp+XQi8^D?Kj^7dP?h12uTOs&3Pb>x(SK`Iq4EawEx?$OQoo_
zv+kfL%pcU%z5*E+-6B5_SKV9+r5)0RP&~s;cQ6u?M|I|VkUXXn(}Ba|x^@XXJfRCa
z50R6)&#fTtI^G?qd+1J5I?YqpQUehmopK5azPc}{=<k%y6hZk1KizbCRr>3;&qiyY
z?)78P2-0O-014JzqA==d-L+X5Z>X-7iowHlTV3&Mh3mq;23mwpP=`T8>LM1PFIx92
z9ZHJPEqfXUV|5Q!p)pSPlm|rObrGLIFF{vEPxmBU*dqG>M`v^cl>SfFWzecJMK?;N
zOsP6P%~!f^`ew}fIbEp*Fc~`D`<USKx;7HY)R`!vmZj?_yV<%$A@DFq_f9&<1)Ysb
ziE?#sPyjJcx8yOL$=4NygB0jes5GEZ_bru_+lzF6r@&IN&fzn3Ueq;PVWLDAL?uO+
zb=!;Kcd2g1doWn0+wmbBE!S<MO>~8BcL89o=#HF5U#0Fk<>;z(GpIQ1s&2~&P^xwB
zC%}A-j!O~RYdZ5!z^v6VX-QtE^Pvn@y<N9|FW3fMy$s%5*HzIztWkGiIbfP}$y9LK
zto!+MkQ=&|Hi)$7*c8WX)nyc5^liGGZ=$bVw~I0?9lCycId$slDlz(7y7n*8cU$*4
zg%$4T-dGLwE?w&*K;PBfrFX?Wo&8TrPTbec#6n|Qx31t0hW0?`SBAzO-IiG(y}CY%
zEA;8U`w}n%I!z}O2X#Vv$qec4>CpFBw~CTg!#Y_p$cS!#9LT6HkzO)mx~e<yVq7<S
z1Kgg_<x_}rQWr+i>M32JogO9*`n7aQ)lq-L4D(L<-67D}uYW{dIO~fYAbLRGJROY(
z_1{yqgp2;uc$jz9zjYXWhxDu0!+STqVF;6OSno`=_eb;_tl*C7-KY-pnBMUgppWZE
zmC!q(&!mm!N&QDgdjGlW7tzbYL+`GKZ=U)Kk?`9~-*^k0x870<G#~wP`t5!733TG&
zls+H~oS%M(7UBN-XG@?Epf6Cti$MLwDfkqm|AZFr!TOW;p%9{9Hvkf*FQQVwaQ!FC
z03D%^e3icc5~<%#0i!6r?_$72>o3!zDMtSrT>`QCJX#aS=|?C?k)U5jb;XH#hiH%_
z{n+=gl&TLn3A<<YTerZOH2o-LIMek%4Pu1n^m`Y>V1|B9Ir`4)AJL{iQ~$<3fMw~g
zou&9^w!ZTgM051>IY7Ih7q5k<xq8(uIFqNZ^Fv?0et9N93-n8*n5RPhmYt9+(l7iN
zq*y;*3=<di9kh@t(QlyRCYSW1rSR~wKFbZHRG)Ppl4bf~D#<I?kEKGSLcgRO3ic~{
zO%i;o)L(lKomF~~0n>I>pGO~8s@4a51+GS)OS5-PA6gB+YxV!qO0`bEi}vpI`mPqZ
z)}XJs3QO1Zhgkq?)bH^F*Q8&#6?)D3k4+f%4ShIW&NuZ(pMXe<KE(%KwA%IeSD~{_
z|1V`f+w~e7WIFUuj$xpk`bj!rbxZ&EGZ4A0NBR)=kv_zR#xDJ*=fU08FFXN9@9AY9
zVlemhn-)N_Ti>Y%$^-p?Cx+CckD`}Eum08fFxaOzJ^<IRUtSJwKyOc?HO!!X4!yvJ
z^j;ls_@O>%HpnA=a|cHFSg-jQ21oVTbPi}t|HdD{9@lr!K5jzq=M58+`UI+`nbJS;
zCO{nwGhNZ>XmF(5t&`#6>+o>DVSp-ZoDCK9xH@2Xr5EZ44QK2d;kS#y-~>@u!xl<W
z9x^<YhDJBTH>2PV8&=dn<A`C06xc@%&UCRHGZb!y!f`{_R}eX2==py%)$saW*mXD5
z6~Gw}gVzoi^fYvZVt`(TfDb^t4fRJc79T^*f3V<d@P2}R!&8QAdXM=T7Ev@c(C`OU
z(}WmSP|?L{!>hEm4K)nM13S#Hgw}fDhS#Z*D#GxPLM@SoHT3X{G908}d$ghYHcZ4A
z%#?bLHPlnwCeDy9gTL{Ha=LvJ4ByA0FVS%589M)$WcXMFhtC*Pr7)3f_+%8KDTa3$
zkV!R&a^c}wgI$EiG{Z>>qoy00pF`t0LkWcdG7Q_O=JC8?v<`MN4WS#*m}R)lg+jJr
zPXm0)F{GY`hZhVCN)F^2UModoo}n4BYx}f(!!|lzT44Cy12Bb#=!@tqGEC>8vDna9
z2GEO!c6!Q}80NeOM=u$i=}hotgM1l4OAX)Ng`;JL%~ZQvZiuED>k7kaA1GWgJVQI6
zO2czPkSarq8LnM5{Imw@)rK28p<u5uEY$+$nxU7XzqN*Lx;yF&ueic)y&;DO#Rh}#
zljyr{DD;PZqv2J$jhhVi4d`n%te%9Wc0+v%KsyWv_oJ`V;6b<1ErTO%$8H<;Jpl`M
z3|v|jb{W2tVq|v>g^$s9&u+*TLbT7YARaISh9Bw5A2hs6LGvNQ>NAjeY)Ep&n1&5^
zDL_18sHX+SsNo$lKW6yvKZuMQ=68deFnr;GzDdI}T47HarfB!;U>u_<aWsBJHCIl?
zy%ek1Z!DpugtO7^-;OaIFd9?g#X)03C5Vgh>AwK#YE)Cm@{lo=b{lTS)pW-Fu<^(V
zU>`BARKuC0MsG?{95b#O0@`t7<}<)PVJxIYz)9oWW)OFyjxGofV<~-m#M9VTfkrRm
zm$V=9HZHV3i}CsxYedlZHJ<+zGN+7%bcDvwXrrO|8@s-QPXWfa5@0aU`0Y3pf{evA
zuoP@G_CPPh__-ONr;QJGgM=CvZboC6k@*02!;Obj;3AB^(U{RlqxLe?qm1KEqA}X2
z`2YVFj4`gF3iDWF%X*MFW6!Hlj5nsz5sd`noOj_&qH!bL+et?LXYlEa@qKsbCmXXr
zL1T)sv=*SL#wEEhf7aL>i@r4Dn&s$AH!e&^-#KG3tzt8baVB_i-ncdcT&6K;J=K3^
z8DFEY)dk~KAxN&#YbQGMjCM9)@{MBJ6c!lQx?uE$#yf5hDKfg#Cc4=8XcI&(8s|G;
zf=Y}fu@Jdre0~lZFB|m_AyR7Wq(cp5#w$9Etlao^1Goy~T&fAbVhnkm;xCm(_FK@e
zGF}He?W*yc=V7qgxMe$jpc-S)DR9?}-_M0ct?@^y^{O*^WCNz&7+(X@VC2%C=ekjU
z0DX<d`MyADG6v+se6#TdTC&|RzC(rAH;w&9%tecFQ65BEjX%=YDC})U6+JiFjXzUv
zq{H}E8Vq(C&(N#mj?uabu5}qDR4j7W*!VK~?ir(>!X(@`meanb+vq{r%Lm3qHvrmW
zbTdPw*XUe;x#%-)r4wEK#*y9N28{J|9AVHHL3J}j#y~2beP}m&{f*8?#&>UFh8`R1
z!vQmFJoGd~M~q_fbkvwYq3AK=R*Gef8&wGaoiO&dz>7&^g&2}k#&JqnJD8YMHRNat
z4?v@n=`OvF_M3|7(<RQPZ(ao00aMj|pd2(6{R1ytO!mL*XmvGtCV?C>-TV%g+)QtJ
zLF2HAOX1riraU`fj+)j`$nu!!hb7>So9^F*!4swhbe`^{X(mMp+)e*bsf&kc0af;S
zng)9D!+4om=v0umsbLV3zNX=mP(NiFSqc$9Q<$ArH2$Uz+HeM#UdaFnG_`dDEyy(Z
zHTr^0>5<R~G4)eM_p~Xv6pf*#-IOB;GyNTl#&FYTd6>%x)6x(aj5M*RS|ZA1q3=&b
zo7T!85@QMt07|@R?n>BAFqwQ{DA82vOEHHe)B0JEIb+&83eaSe?L0h9F`e23F4c6(
z9U^B<FOmK^)1i}4%rFi5VuH?_>PjJ*ZJIeBmU2uZRNH;QluA{zxuy~NTuz>;eIvMh
z(*~Nu0#hJ`W(!Sj8R#oAZGDp7f5j#*IskOh)cGAqiD{!726M@@nV##HO@A(cXsJm|
zH4tT{SMP$9o8GE{-3n6$E%2|HK28Q#X$qlAnJQEKQ*h?0Y4bB6)usY76lzT6AH(i7
z)2qGUYE9eed{>?6Z=}rZ)9Ou+DS+8vn)eIPuA2sb1lMT#C<HQ1rq`E(G@GJ+fonHR
zk?|lmO)qr;t;KYjHg~P2uc^wh%@isCX*YegA8vP;K3j=d>omRlBgidN@m46@HnmaC
z`Hsnnl9*klV5+*a-!&;|p!ZD7chP#^)O7_g-KLe_fqP&op^sAZm_{g{-D}#l3I_X3
zm2@_+-?W#WFaxF=pJLd9riJq%Ib>?yhq-uY;?oP{ktvJvN{>x5*1_(uX;KHh5mO2U
z2}ez(RNFabH_bAkbKJB`0GJ8We#$~lnnEcGJ7wyZz!?Yg_cwvI-+bpH6rIgJr$G*w
zU#3XUL9<Q+Nf+}V3!JO@3n~LWWL_5wFgLRY?S&7UAJK#Di20pFjPs~Dfr@dCnRR{O
zj+^bVw8}bRK7AiBC(W;5jXTZVY^Qv*hq*8Spq}RM-vEr4`3l7`z0IPvAU@{BGhxEl
z{0wCwPno9<f%7vv)1%PeoV6E?0cIR{$K7N;kN}h*vw-f+VDk&~rVBCqP!9IAd7u4z
z$b_0#QPokH*=aM(hnv&ru8J_P?*wS1IX(&cQRem(C`Ox=!%&DZJMKkay!o@^P)IQU
z`YmQQ(Huy@z9jSev?@GfPFM~{lg+|e7+{Lo(*s<pnUM$Xtoij9VK3dx`pb^ib7tFb
z@GZmq{wgS*Hz!b`Y^K?z9wxHQK4Z|xF?*##<AV9CLYU7r@3EmT&pb)F?tJrZ3PKf`
zH+=z-V)H9!fqBs^ptNO)`2|;Sm(0>Hp>WykM}-`v=7SUkDl^BhDE?V))_#kjRhSRE
zL;s4ogNkY@%|Fr;s>*Dj`{1hCZ5Sr1&EK{`zsCGd85FLWXHua+t@%ZgtTP{+1J~-!
zUs2k!!EB+T-Rou<t+E=;`VSz|WY&KQ3(e*a&I0U)IY31Dznf;`BDA)cXFUXHt9k84
z_||4VPlcl$X59U_kIW7Kg4{9B_Xl>Dc{)`z-8FmX0Q;V~hPJKu&Ao?#(rtdv2K5K#
zy|07oF?&$KTCaK56iA<WfC6&;<~zsX_JFy+0burrX6JM0d}Nl;0fxusK)P{<&DuAi
zKVo*Jp^chXZO0EYX8z8IxfnMOQfa`1S@kLOCe5bpaCFN2DkWhYEUi?M=VbAH5gzWh
zyio)NXUnxAh#at7+XjV$mV(`|;9}`J1PdqZmK*`-NlQ>8WZW(Lw?f9lav%l<JuPc8
zVBX7;Jrkh5mZOxWJ!Oe%gT9}odONWFEtCD|3$X0eLNd^jMQO_*%ZCZT47O~eGhiW>
z>UK=fY0DZ~3xrxS+Q5ZbzM<OPaEm?BAD|JI6}QkDX<18&nlqNKd!e6f**}80OttK7
z#$e7`7X66EG|OVzOQ%~BUx%f0minhbGAzdy0sFkA^#y=tT9R*L5Lp&C3X^49Ht&W=
zj^$!5oVj4RzZxRB7JrKM<ynI5RH~M5xk9no0!z{Vvl*6T+H@3Id}+s6Z266rA{Q+U
z+W=Ey*-zo|OP1|q_p)U}H2O*{Wlm5pv-pIduiP^55A0T0uD$~3E0$R{h*VnU(T2Xt
z@(Cqau3DzO2n*Gg*T*UTQe&A<HMrL-xdrH~wX{<Ptj=O0XX-7FW}vUZ@-A(5u3P%X
zz%^P{_CT`9;zGOTn--ZK*ew>{N;I}wUfuwaHp_G>3T?M+c7<ylmUmtP>9l;4j>cP-
zq<`T3ZA-yll>fV9>Dh;=>9W{qgMHVcpgq$)%iAoF`<AITG<I9qRDk)wa#I0=J(jQt
z80@vQ4!}~Mg;Nf$-@<+s10Armyn?H9(2}wbjYF3C^-zCk$&G~GBg@OQ*?(+N?LgnK
zW!u|y{&vLT@;o#~Eo)0L-Z9G)w1*hCaGYU&!eW|)Ym=7Ew1=3ouxT0VU=4T=jgHps
zJ0ap^-MkCx`>m%b1?6n@qV&fBYYEk%9JIO%;h~H5p$8h>tVLxQ#9?dkO?Yv{`u11Q
zvmdp-MCI<stVik5f86@YPRN|F%ISdEN$ZCTLENqP>HhVw_O6A7r&aVJ8ojJTRQKj>
z-Ag$-AM00-(dTQGP@Tgm>s%AY;%D8If<}Mqa;hc^uzo?meW2CL9qK{WocACZY`0EQ
z9x%lE#Q!tc*0Dd}MX2??g>X2`+7<)FaBJCZXhc}e*D$6?>zjD5OpCJKq3bHz`UEY1
zW2_G-LKJIV_#H&ztoJFt7H{pQuwa69)oDm3TC3;6(Io31!GJzveI^g)ldX0x<*rh!
z|Ju=-YE{q@=&be6RFE|5BpW2%Izan_bJi8_fMi&|Y(e9B>krhJX)U-9^(^c80&v;Z
zg|uYLu`1_5<bt)-h<VPn>L}EiXO$S?Oulud1_}k%4_|@#LTkL8mcK>Tk-g|Fww|Ih
zRTr&GY#=4pD=%YAm#kJQez<Jy41{E<l@$)OGAmCG>~iaebZV=@`U@?ltE_1hiL0@)
zsf^{Cb!s;nYpr3lPN=i~wh9L8t=ocu*<g(wfW7P1m>=wbX|%rB0k+Ai`4uLbtzS~8
z^M-YlPE*{p_TGm`i*+|WOj@nGI|15e9i`WPyLIUSNOoA~QQWlCDyAsGE$g1I0Cw9t
zL{XeO){Adp*1N1tl*+kl%~=bDd)6)rpWe5AGDhcbyRA3qpUgh6O6X)|k9BDpyy&%7
z{s)77*4YeL>bDwRg2;fCH3n|b>PnBDA*=cdEIqV-o)7Mk^@l)kkF7s90(;o{EJdV8
ztnbW0->9`|3}9o{BNWCQx2}Bw7ACA&2r1d8O<Lcng~pUMjJBu_wgV3!>S&wY1;3qa
zc8YHwu<<Eyde9d828fF-@=GYV+9oT|cgS|b55&!Oj)}&jwq{xt9<#Yo<ng%er+esg
zxAo7)=sj$AW`OgwWv#`GdfD2;0cQ8Mu}9G9V>>`6vHfh0wEXqAof`)iV2iB-TA(e5
z!YM(vr_~_AHs))<4zayJ`-{^y11%>*Z47##huOwH09d%~6$&Io*na;QB9XSuY=}hJ
z$|-#xZ5y@#CC28gfMl%QmLS8h<7|Ic0W{vW=S_@0!S?1I=qK6==^jh6P2>anjBW1?
zaLKls*+5INo!tYHYI{B!dS`8(^g+Ee8~<%wW$Cujv#@l|=1XtU3|lD$sLtC?S|E~X
zOQV%rmQ74C^K6^Ff);`~w%m9O^ny(`6Ro+n+3nECvrXOx$+tb@1yW#pAOb10HM|A8
zMYfCdNGrBoIf=%LwvH0GR$?2zgT_m?B#N|Nwsq3$q|~-d3Q}eZ{(lI-cCH8JD{L#N
zpy`T@Z>RgA(w0V{zbf0uEg)BI|4|W8we6?>adhQzRaH;iOiDA`v^^`!HcK<jC6}@+
zv(l`1`@Zk{%QmwIDgv^}DyXO+2#U%oDvBUGf(U}j4zda&iy-^*`_AvL`J6K|-<fmo
zednGtGv~et@XDPdbTCoj%%U$J-EzL0jG^6jE)7HH9p_b)+o*J&a|^sG=P`;QS36f$
zLA}N~vjoo6I?toueVw!44!GUue2Z3vcb%2f;9-;V>}B-(Yj)0|$aIUdC;-n~t8;1z
z^xK?gIN@5fJD1W&bnZFV5O#<2ks`o!I-96S`M$HK2?|}#Uatb}fpZR3#&$cOjR07W
zvy$T5z0R@E0IbjX(zkHtp>y*^kbY+~74Zx>&rG8H!y{+81u}!qLQ2^UIgjGC<TUKu
zLyPbc=Z)SVqt4D0_#AU~x(~&1=ZGpuPB_=lvpVTK>IUAF^RMI3b7AB=!6#S7@C^97
zixE!AwcU*ARQ9@u5kuF)jnUl(FZMG2WKsUXol#Q@G!I4uJxQL7$c50@$B2rDB`=28
ztKfMvk|=8C!}$C&Sn_2wQx%RM<H9tE>}SN$xl(_I>JVB1jN326QXs>hVo^bi;}j7K
zW;`*1&Jf1ztB^dvP*d%0C}WlY&N#vtGibYTkg=1dh(nC-31}Q<yh<<CaK`4hVekm!
zrMqYyWwfn?GshTXDd>z~q(uTPlCdHLFvl4clnp$=cu3KW7)BZG<YO5^y4!J#ne<CP
z&G49l`WeP?ngbIUf6$vf(ZT3B3cr&W&r)bOnNd$W%@oF4G^L$mWaPt{3k-fIuFOTo
zp>1fTF`}se>=Gl3sx2-v9&x}+XPlq~;1xy!<^M7m$$LOD8Q+dU@+xD)Mp(*Xoc<dA
zW;5<lwQdfhdnZUP!=aNvCXaEY7R-D`D^+<EFy`$5vyid14cONhic8QhV#J9-iW%F#
z2k$y#F(oxh7y$x!af9)~*SL74jG+e@eHo*Lf|EBHCMS4N&iGIbkqXALa`0|3SQJpZ
z%^0Vm&^wF-2c2=RWIXo>y;Y2?rO>EmWY8x@YZ$-L@~W1x;|dh(7`G|eT+cA;KpGg=
z=(%cSn4`dJX5<}%_brU4=-t@L=zI&9ZH!NU0BL7@9|E`UF_zQrsDshZKxZc-gnYWs
zNNlD2Ll<L|Ht!D@CtN|g8K*}u>>ftTkI?94coo34KE@E8KYGX*Rl`z0!)*g32N>y;
z{&>XjCf*=pKTWzrcyxd{%y1DweT4CMAS6c_J5GQ%#`sSK=yAp(+B8fs3|r~{S0)+P
zsaVUE>DmC%UCg^wu)3S6qYAsdOs6Ic)SVee=R!T0UmS%qp3F_30ec_wwK(v+n4eK(
z%bWQnEo^+4H|b+1zRa(l2JvGa>P6>%W-h(I{Fx7)hTQ<B2UU0nGQDu@!r>IeEP4l)
zf|)_35Dj6z=?YH|F#ooJgfchK6duN8Ge8b9x3s`uI8#7Jl#VdlJpg)?`7sqO9b*<5
zAriq1q)=xh^QYMu=y7H+?FOTmOgao4&74l*n-k2p7hr%f%&~Gf<A`OJod?WG=C_N`
zdy4tRLg>daz4n8gW`@%;^bGUJM-Vy7^rsv_JhPo@;u4tZweT>J`MMETCW-mu6eN?G
z|Iy+-g{gOi$T?<CH1txLy%dNz&s;&<zza;LBj~)y+)RbYX%6PgbPq2vA6G!}GV_JU
zU^kuV90ZvwOdNa0&xu)08-q;dW)(!PG9P%OGmBa129nJbC;*eg{J0kb&1F{7#xIX4
z`wo`!nO85NRlqz?S@A+<W;LL%F*QGdcb!>F5#>^*qv<k0%b07wfQvVoG4uu~XZlH?
zSix-n1}1JX|Foj>HgmoUH106Zy@<|AW&yn$tC*T^!K-ENu7E-v^R@TkMLlzr!UGLV
z{0}vLBh0Z;n7_-MlK{ykrt41-X=YAvfYQQT=@`VFX=P@3;_BUFZlZ63cQC)CWnCvT
zU@J5pFz0)K*Ub#~h4~)lcWyv?$jqkbd_S|~6_5dD;08zzF}o4~I?T+Q1C$Zw%r1C1
z&fJs_-UM^jD<G51X*z(pvV;tv>|(|2rRDE#RuO$#crR;u8Lp)}>kt*ic(4XN(DGur
zb;B8N*0M%O`mhwUU~oUn6apB3);sjkkpR|$N8kmsgfBuegmr-eJ_lG9nr#oV?rFh0
z#2V-T*kRUZdq9q|0;!(=80!}!eSa{5_2T!?h+<9ALOYuE=_IgEuxu1RJ;@rP1HY$O
zDMFAqmWB#*&$3cS;YB<vg}!Z(z&hlPRx&Ho2E7!P-)lfQ$C|zn3Kv-Wp8)S7YuOTz
zG}gr~T*GvhO9u3=u(qC_hTmTXtMxFv$zqM906UwNzYs3wu>PhcUp_0G!s`XB%ZK1h
zA?wEfk4UhDbUNS`>$~mHyUlt;;mkX%>$HQZWUZ#XY!ypE#|LX!+FxL|j^#q(u6ou}
z`=HRkIzx$)MwZv7@YivdwUo+cn^>a#Ak8cvT12$4K2L#uE35cVm~UgHx}w$2TDk)I
z9jwB9v^rVYMo8Xg-Cqm4U91NbZ+gJ`+7rX>VL3m8LG-fz{sngXSXCK-e#rWc_MQE#
zrCM|ju%3PcdP5GDLJT_0THFKB5mt%|^v7BEk{~+4dR_>FldLLQRl2Z8uS3z5eeFH?
zw2Pf0gTik1`}830VY`2cVee&cq}QiAJ2evqJ=k?LLQl49GQjq+lh#7di@lEavfk|6
zP!J!sL-Y>xec5lw;IJRN$`@omo3RvL__HJFFk%3kw+f(v?3EnA1hI=}qcfP@TL;%d
z*ngdY-2-g12qcuPqwHrGyLc{m2id7^kPK&+(lc{}9b5+UN7=h+1r^D@*#is5*^eAg
zLotdy`(1b%!~XbdSc+xO4u<|oc7hIQr`aoe!8^lNQrz||`|M|cNn|hl4lqgV8%F?>
z%wA7Pwp6xH74*)tL%syc1-2i}K9|_1lEJ&o&I*S@I@?eLkxcfR6qmco9@|0>O%~g2
zCx({GHdA;nk3B-a`+Rn7Aw&z<CraQ&A-nb&bY5fY==WR1{?GulV)ozk6Ti;>@enMP
zu-AM7ksIvv4FD@;&;J!(++@d5)T*34-49+=us;n3*e!PdlOVU*FEHr+cZcn*hGHfA
zTUUryvx^SGiyC(6Buvz@<qUXH$F8UJM?ITE0lfzH4%(_UvR_>f^LN?5t%qb2dsQM#
zG_zf3qG(~uXuPfLGy6d9vDdr~(!oCSD=c)ff1)$j57->6o*hoz?4_;f?O|8-qqmox
z$_I8I+wv~RLv|RIEA_Jj--gHl`@JD}@rYgWEjkC;UUQ)^#12{xGR*d*qQepP3shP+
z%63wtHOBsFI_!?K3&ubu*u%%+{UrMVrBbKZPE_FIaN(5kFbY?WXAQ_Mjz7&%yE%EY
z!Q8`1qOF7*2ZvMfbaRf(1kaswd=Ah&I5+6M>&X%EA-RteyAG0GoEkr%cymg~3m?uf
zrSE+?dDAc!KTd%Uc>6i)3*nkS$NV%%fP<4%3(!E0pb|1coQ5=L1asm)1_|N3cLFd6
zIAY2)hH~;pAQHxjo`;KYkhA9`>>lE*{ueNZIbk*^gmYRB;L04~)G$GgavpmVoyRy)
zbUHkOGo98`k(@<#U>@iA(atuC<8VquGnx}|0?iYg`5Ksr;Y@!ACSo~jXxci-@%#}t
z_7q3Pg26bBk~TD_IeV+nd4{7~4D7R<-|6sWJm(ly1SW6{^rBDXY*_-7B+eRofh2Q=
zr{HJ`C(a!x=Q+ncF{BHe8IJ9s7dbhRfJx)rree5DoKZ@^UFQ5ko~Cn<W5aCCSwxGp
z3{La67*i&PcNLOXIYs}%-z-ik?RT>|Pi}%_4oCPnL~=QI0sx)InWUUoK4(n|oGIY6
zP)w+h<2w!u*EsI4(fhB6quK>#G3PgDh+gMhOadw4ymkYfH#o2JV7HX>1_z*J9EA%M
zZgNi3tt{tU-Hf4Ca1v=Bc8l|V89HxsqG-Q+hx5TOc$J*b=((ukgwu7Z<_H%8tcLS3
zh5BnbySLN#U+OroQ}(8j6KsIYT~6FG$TV@z)4ryelSS1qEgW4KOtf;w&!e-AGd>8=
zc1{>Y>F#kh&jhc76Tcghot$k4(RrV<pPue6P9vq!A8<Y&gkCo%jlxwuoV}E8>E)y^
zru|<ZC&~??4>`rZ!0&#}SxSu#aONdq^p7}e{NdUl$3SbJA<ni2csR`2i4~yJ2&aB2
zTB988Hy~r2%Nkf3=Oi+rH^G_t1u!Q$7w3aaaSl_xj|+D@-8)zALtl8miz}jg?%2&W
zZiU7k?%HY4cjKz4z+o?U_g##_oqLfE&3JG_DgWTf{hB7ReOx~=^u4&cJm`CKd8ttF
z;T8nKk}r3p6)1jO);e_V=YIMl#_P{bpj>qTch-G~1adRK#E^oxvra=K*ufqC1fU_@
zB0AM@fLlrX-B9j}aqu*ZyMu~|4suWN;o%|fSt>0!%+<KVL^yXEB~g!X7f@{HDEI0=
zkUYj6quTBWZlMvFk=(kU(K^oENz+vnH~2A-Xs&c0ES%srJOEe>*YV3!fH}qegraqE
z-2CO}J<YA6?_9-m7d(MsCvck=!{J1(ftHFFxKBkw<Pvx0>wvk;)l;G+ojY^|<O+8!
z1*S8&sl?0VF8C0bSGg}z3^|LtoDQjGb9L8&najOUgjOE+4@Uu9%;$!khJFF}s|hd*
zxhI=&y{>V+e?Y64`~4t9uXC?cs-T4XN*>JL;HK7rSIT`N2Hux(&r)LcCil4&aJ!r<
zam7F@xO=VO-Qqs@1{Q8}OLsxx4tFEv!7I6M(Kl(TxL(iE@2{FG^#Zeo>+>5-)N)gE
z;eH+0(SlYzS4EX_4O{`O7aF;%BLRAsJB?z{P26RjAkExO6en)smeNgY<vvbJr#9|t
z+Dx`{(<7jFkK0BS(;eLVv~%j>x=||i0oV69#Xq~b^KL<-hx=R<eCy>lBm=FF`}YJ|
z54p9J9qZ?2O+aIS+rAt(_7OMs20911k2^zTi2K76@M)MkgKAnwxW}l1f0Wz57#CrT
zTTDmL#<^1+=$zor_ky8GE@KbK6u06x%0Ia9j(i7$yLoC#c<kYMDPh8mr=qv`Uf%Mj
zz;ovvZG;IA-cJ<Y_T){Q0m*&5LaLDS;yq65F>hWr<y3rlzs>;h<z=pfo*!?5YI*ka
zexgbYf8N=-P!HgJJ_x-)-mg^G<Ot&VQ%!6z?^TKfgzyf~uj2qOMhwMJ-qdnvgz>^C
zJaCYA@i0IS@xGu?*kRrd+Lwg$_!P1~#=9Q^w<CBv=>-zWGq(UNn)mN^kQ2Pxb+8b_
zGf<7mDPB-CMB;e$l$1a1;Jwri?08=EP4p)4-nfKTB5zwL#+1U#@Px)W-r6`^?o^)m
z5e#17nV*EEi#*$G=%?|Xq7x~Xc<)u9^D?i1p1>=-;rZZY@U~KVIFnb!!634DPf}_!
zn|Gh~XgRzgik9W_97$9olgC@K1O^Lu&NtC2<Xu+4;cGm>5!fx}wX)H=&Z~U~iY2@}
zT6o^z{qZ9}OL={i8@$OI?1yAIFPw6c6})qm0K3Ke_b6Jod0$Wv_zo}dD|A-#La3;v
zhWDxsuGR8t9i@<|;{}l2dY(URVH$Y5XhYJ-`}I6-&|Tg$b1}ju-d38>J9(b8bi2>n
zL;=?>-opQ%o8W2Nq1Vk5(Z;-&_a0@i`gkwX!M%sPf0J-!26)f<Lw$(%Jsl1j=3Svz
z^9b+sE42O`<$2OK(#Ci{C4xE5TXzDUPVgqi(VFCmsc>|Pr&xtf7ycT0*j)Kj&qHAs
zKl&H6_VOF)9p%pdaUD86_~rDJc=Go@g!(@IB<0q<_^T<2>CMlknm8Z+Vv3pj^3zYy
z?=O(Q;&oh%Aim>ehz9e2qx$*~zTaJF9N@oL3D8jf^gN6rjQ<gBEDrKFQ%dy^Kb7{4
z$M{_oxsTv){uCsVpLY><kMm3Ey&J{%E&y~i{~E1=Pw;!IU?GOTN(K_kpW8_FpJ(`2
zDYbHzA4#dCc>XC$P9*TlR>OQEe+p|<rzHL*I%}8AUz-cX6n<C(K+o|5CINbZ-#H!R
zB7b!ecxn7vDw({*XDtQFW&U(3!b|6`*o4k2{MucR%;0Z}09Yn}Lmd<xSNV-pCy~Vu
zdKJuU{=9zl7Vsk}LR`q7`y2GH@%>`qS`j~H2F6>=@0SAYI{z}wOeK6BRVLivf9nL$
zQohGEfZgIRc?V#(`5#b7=?-5zA7GXI;OV%NRs3D;z^vw9tc8a)4*nCx(68mcp9d3l
z{MnQ&YvOm%UagrQnhCTP{_k`^q?P|-K1dt?+7BS@eEV&9agYBr52S<7qx^X%|F1^?
z>)}hOvzPzSj8-2%^aw0H<Xb2_*Uv9~1h)tH@6rnQ5#RCnW{3{*Pc8r%;zxMG;3)s2
zC(s(>`<#ML<9uIQ)=ltdd<L{h{yP*co8r4uuFXZ@MiEO_!CFd!?h;riW4Bx2&jt1#
zf$eV)H^EC(ud`3^T?ATQf|?rWc?(8Ag`|&QlOq63UqM+X4EhOH(&V>a@X#9$`wOmC
z<5~m=e*YW>4+!3m!>~gIbu@d031Xsvc2Mx;K`0y&ET;19!-7^hu)_txv?DkoSh5u+
zjtaJ{#UP>t%c`LeEnw55cS5inkDgPEpqNGZhgiWojnF?SP%1%A37)(Sm^i^>|NknW
z;OhpUB?@LJ;YE_bClLN73-}%AOc6Yw(7`#uA49N|D%eSpi}QjEIwyHSu-F687X|Mp
zz~E)U&QnlN7p&|+>x!Vn2403h(n8-~$`njH4E?KuxqE?@C3x-}Ok@jYy$O;d=)8pS
z<_dg1fJUCco5F1Qg6}8>T`XwUqw~6;w*q!c1j0OApc{gP0$3^)l+(hZOz_ofaOS4q
zD?Tig3q+~FtQ2_B`>#r{We=@Cs|CwVfT<B&mqD~vFynim)d^1aLcd<%L#wj}!BxtM
zv<S*66V)mxc^RZlaOx;Mh=O@^%=(@n^ejL-1m~%~qEnEQ3HAGeWt%~I1@E54o$M3T
z(4+oP(9;LfFBqc2TE~FE!iL>Pf>2j@F(`<qMZ}QcYx+llQNgbi{uvXLF9I1CxKeau
zLNJ%&dXs{A8*mY(1W)kcjJvRKH%xd4{bHc*DSVwW2K$6=RuC`YueYJ@Eu5u<h>!3e
zGwk{br&mJK&mn9-0?_@!KPc+#FZ`bBzygGy`D46+LQOJU3lcWd&p254Oc-De2$#~E
zHdNS0JEt(=0s|xu3Z)bfI3!G@M?PFAqiObt@NKGTJ1YFh36c>)@p+&`3jdY^^SJOQ
zirz*E9lo^ni58xF0wh+r>?L5I6vi}zc}n;StvKU^g&KgK7Uunn&NITtXz6xVIMfKV
zcww*}dI`d0n!%HVf6|IESy*HPNfEB23WIaPFp31E3d27HIWJt-i9uWx&KE%>O}NIP
zh5jX><u71g7JjG%cDnG)I$VS+!b@v#oil`g7Qm-W;g$;Ut_lNaA(tg=qS#xuFzNwX
zIYL(|(#jQHYyrs=K2LkYd?A-!83n>NinJCAD-)o8O~^TlR*`UTHAISq9q|<Eye^FU
z819z{FVJe|hVV8;*-M4p^fE6OR#UdBLih>Q*WVI8OQEIP!Ua@pd`B4E2wtTyY8D1j
zEsQ@0UXAdhW(>4em`QuQI^j1jL$6+V_+5|&;qPi--W9T3pxz{GUP$#X&BD4GG+Tu)
zc>}FYI16bxr*>f;1$FKTKW_wfhj2+Oc%8x}z8J-Q;pnFjc_3Ur9lUPgYvmYBkMJv+
zwR(l`(6rGfbovt_{lXAhC=Up?JO}bfc$XFdgTg=Q^y855K5o6kX;?V^94^9`aPU<q
zjtk>{hvJ0rM>-=oDU@zQYf7kafxe4qJr$g~iuO~{?=F$j0fpTne+nM&5&ceYJU3By
zFnD`KeOchSiw?|#f`@1g1sOa=#|04CC(5QktC#3+deJ((MR9cQ$w#DVfugTyBgK9E
zM4Sx(-7lI?C3*g$f0uv+h@7Q>2^4L#!QUX!7u7HkEV@pSxDe4(#{hajbo3Q;hKf!I
zfD$I!)&=N;qLK?BheQ`1gXCdRtQjcbqU_ZmM;xLaFDM=r#r=O7D|+)YT+#^9o_#P8
zDGH>N-Eq-IdMibVMm1<fiz>f?qbEe3qd<!h`F#b+Q=*g4!bF^CnBKytMZI+N?TpCo
z1L(7&1GLeN7wvuuk_n>MH)1S_BGDe8B#9hmTHPg!_76cZMU?X$M9+!z?O>*gd?-nN
zUQ|bM^$Vh0TJl{KrKoY)(nK5Tfp$rx{~UUkMJF49k}g{LD|lB#TPbjvA=*q^rcBW!
z<=C!@n4iG=EYV+7!I3Qr8i8bv=sO369&$w<0chrl*c39!7kx~pj|)Vv&Vv_)qEE*F
zb4}z-Q)!Xt5LNLMi@tgvBG*OLZ^3-2XvW7NWui}LC392s;Vg)hi(Kb`RER>qh2$+!
z$R&{5B0tKu-VxoUdsivqZ>3FTl_+omUQ~;oo`btqBN9;Jp;jcIGK)IV0L}UJqF!1D
zHi%MR!C)Fi272$_6_u@ndXs22{ew@l$c^q#i)bZ1fvqB)9i45W>}il}7iF9SuT%7I
z3R?F?g;YM%B`R4!@4pA4kNyB?x2Oj1Bd1<bJbi7XPjrbwCJ#k>cECixXwx7@I3OBr
z0`HONkL7?F5^3(k#IWeCF{qD-@>?J>Dq7hFkulNBD!4r^62A_SNzq&%@TNrnQheD(
ze9Qx6m-rq69}cJ8;)QF_+#@br2}L(?+J1=c6>p|MqK7#CGKi-*KLrl&6Q5g+i{K@0
zqnE0;n6nDRM;sRmbwBX|N<HrvuX!H^{l%wep))`{I0(H!v6P;!AhDi}0fvZgQ`qQ$
z_=9QSIYPx-s2t|7cnc-h!^P{@qW6f{D+1T+sCb0-w8z8=mjN0n-cQ@!<Kk;oz>X4c
z&jDJr`0W~u{)AXpgw7ao0ab&>inHkDbV|IF-pO%duT-F%7WdLu2hND!AHX2aig$-W
zJ;5Pf^aS)1#cz|RN#bZ4XtG$n1sW;hdwh)PocKAaH%JxR*F*85*oijLY2wpc;r1o*
z{wk<n7GHP=dg<a-C1_=c7p%cpGR1B4K(2}_x1%#l+(gmPY;pWFK<9`vE`paQc2v?&
zHD4^EpK*cs2<1Hr#Zy$;dQE&_9t;+VGv&~~F3zD}MTz(}mGIvXSJ5O?Ccg10L~e>R
z2H|MAIJ+Lht`LhTj&V!8imG?+h~G^DsTA*}L~@n5i%7M2ib8NT;)@PSYSfAsQJGV{
z`28YaH;9+2z-$ytDF${|+(U&1P2$RpkZcy$kHJ!_c>NqGw25_Z1Fc=WgW_`c#h<N)
zUY9th8+s4K1GJj#7B8oxBt7B}Dd5v5-f#h655<|!qt!32Wl%U~K-}{eU>=FR%xDdY
zzbb^xkeIO@`Xge^+ZgDmnDGHz8xzle17uv>PchC3vG4>Gro=HzV9-TUdmA3QN_J2M
z@h-`mub{PClIw%f?~&a25gxip#uK3KA-PJmBAya?0OcR{N&cqrf|sOj35d7kMan|@
zNH%st##fTH9>h<QH4~%QFPTeee1FM5rEo1ka+)T_K*^O#U<XP5&VppHWaGbRg-D*s
zhieBU&)kP=p%O(Md<v7u-$3U<$x$kIJtUd&8twlMOU_eBD_n9@k1-vQ{QDA29F@FG
zdGKSBUv`2QAzAb%c#)E7dhZ^W81q4*Bu^CsJ6aM?d4LlVSq3CyB<XWuB3AN;01781
zGZ(_qQ<6_8e;y|Z$%5o*iH3guXC$HSXgSVG9;3BHyksB?gGrG1wLmdZ^3<2mNRoU)
z%ba9M-b#q3NCLJ2?YyMS4+<9~OMZalMM(qwwl7P%TA-dTsij+ZMRJ`|Dpw^hXX9FA
zNe)wyR<>kSAKcE9JWo$<zNEbYm<0|=dn7c9B&(*wQn4g|ElgaOB-4VoR8qPOtuo04
zA@pxbmY>Cyxh2_1Tc6vKe#+n9kv#Yk>eZ4TT_92;(LN7SD@j-ikp{`Gc&Il@+$gqk
zR}xMEwI<1D1Ms(5GLueyv`8FwTI97#zHx#~o5cDihSn|-WdY`%MC%0?J0t-~5V<co
z5RF!s<c&pWJ&-J+*ju+Go}%+Tl27TC(I+XAL+_y^jApieN$7N74oFtfj^L4Ge<z$7
zlqe<O4M{q_2iUM=k>fk`j!5E8LS|I5%7lwBCi$%hpyPO2U}-|)xgVgDlGN*voRY}3
z;JHYbTVdW+I!=4iUD8i(L&QzG!Vd=bN=sWXdUxrTGMMm?3cCUADQ#4sbDz|%hoqNu
zWdbC<r8O3czxYaBX_e+DeT>3o`=uLru;ed2L8l)Bq}S+Y94Ni@3`ByYZUrF0(xdc)
z50x(c2D~uoAGD%5DBV{9g>b2iYM+is&r|8~QK?5X$T8_?0C*A7$LP5@E_E4(`6%fR
zwe<Uomiqn!<_YPk6=23lW4?zMvC_dXv`$JV7h{B{q@%R!j*~8@&HHKT2+d6Aq`%QD
zohl960p5A(eKtBTNMF8(@m`ev^)*n^q~%nyd`TMr3_QFn70^y1T{>?DT34ja!F2v8
zLpsieiA?F%Ai!LeK3W2jCC!+C-`UcgG~4D#{iv`$SK99h^Lf&@SrEyWZhIbj1=3$=
zflw%|XofS_q)C+FERssPV4_&Mqz?+$rK^5IXNi<c^+`9RZpR>5D!o^PPDh!vl&ULl
zO7~I?;4Nt|9o@Mt-F_IJ-jUAeMrXA&oPr}YQh_@(YNcUU&{-#)PkFq0={2fPYLISt
z43?Ut`ZoB~ELA;^VYf&>ya&=Med{44+oaMksJBb~=vv%^0x&xq(ndN&(kWg22}XEd
zy6!8qx}-e;F#kYWy$lzjTl(5KT0PRoY5~(L{quWB_DOFQfIO65A<%y5>c7z%kY0(0
z$RnxwCY%|R7R7-#ByF4q-mtWgmiZ&n=4-$lm3~fV?8c-HH&-ynrB^9`I3aDL#L}d6
zbRkAKB`u&b7#G>Uh$}j|$_|&n?_Dyb0=(U_M|4T{$ezCggKn}v=%=<<)=&hy?y_&c
zN2iC(lYU#CvLLD;-X~Mmz=D@7&KI5Dvj1+N(?|BNgVr~`GUwOeslRL~g_HwiIrJrk
zK-nUy0}GN3Qhj`|tbp?9A+i&4U>}f8QRX{T)<x4!n2ccrIVgM94U&gse}ux{!?L%i
zP$yhAxe|IuWFlI49+iDSWgW+4f#L8sLbmufT7O2$hJ9iFxNLR~M5AQ+p@4~&nO}!~
zjLb}j%wuJHXwE+=Yr6)KQ?jpjLN88c(BUGUk$F?9{H!b?6AJONW3+cql9jy+$z<6+
zn#xjS@pMDa$^NpTl`2b9!rpmV`+oZUU6388m()dBtO}rMvj4K6cuCg9hsI^uI2WSn
zvH+^ix+3Gvf@FrQY%xZdDNDNr^H*i7Dd3tV%b~iNY}ukFv~pxWQzkf9b~qiKd9v#+
zAo;RbdhHj;*3&+$Q1)RW{r~$lS(6%~MY7Guaes?tk;#y`F5_pxM2YOSAMD<c#nC3K
zRMtwng)-TmIw;(fNol=ZE>ltDzC!jwC3v@FOMTI*lzmGPmnzxD{|CKgt0=TnBXdnh
zXRYiVdPwVJeH3$Z)XVmMgv;F^`{I4{Hp<e@!_r+@+%PnnWNEZ6YLSgh$0cc%{Wc1X
zHre%P@VaF|86Z8fWJ+E2%DgGK(kCmYGnfx$uTTwAzl?PPA_KA{ik3Z+)l=EepsZ#!
z$dGIuO_L)ISreUk8<qX>8|;qBUQR{txNP=s=$w$XW}<Ua*7_u{r(~`9=ya7oPg|c|
z@`}Td+$~R|{nTE$a~mwV%lEtwY!CUoI<!3Hp--W;Prl|C5HI<Q)o{&Q{_$IA`N%!!
zVeyqaa_L_9$)BV6xWD|N1)u@)H;zCiP`;TyJ{}~Gp+#D-JnalDg~)$S1<V0?<3}(N
zCJ&8(`a$_tKd2v)U#o%MVfmj*xE(IPPJykX^7|AbJtlwQGSnmGJX(kymoxlvDWl|{
zI*P%Jkr#gf{aATOEtn_exfHBOk_R4vrDXY_KNM5s^PYwm=j0FRO_?fhq}TU(`7D}P
z)8uvTuyjd&;43(DS-$Nl=%vd~RiX2WyvPV=GURarKxfJWzlOc5^6gYSlqFw#m-eRF
z^0~B@&yjDeg56yC5Y<=Y%U_-ejRJWi#exgv6NPA9lh67HUKGg}9f4$t{HJcTZpf$8
z+pts~9fww#T>S;WZps_!y<0ASmWNh_d_f3AZpq8mLGQLanc{MH<i9!S{B5N?gaR2=
z@^7g;q*~redCMAkF)c-E<tHlPVV(T<d??n-@6krLK^{tB?ne2$6r#B+Url?DCi$fp
zjJH|NrKMtvyty9gt@7$nT#`2V7qr1`mrr{h(D&r;z6p^Ixd(U-r%rj<EckX`zLn;U
zF1a)Ztq1aTe?zfbo_H6XJ@S?DAieUO88F``zn%t|hw=~#&-KgCx5CnZyoV|i9?7FS
zATlWL&jfEs{w@Px!}629XpP97dLS|?-^>Hpn0z{w);PxHhG*gTgnX+T6er~-+9yoO
z&(VjMTonIY0B@I~gu*y(ilmL;?N$6px7l4WWQT}{;@2Ob=c$;t18DmcIyz_KrBK~~
zg0~`pqNqL!Llw;XDs}_{%un$RebQ#X!eRu^-=TOk6Er|^gI+R$3Ren19#R~q`*c`Q
zL50ZSiftRfJEFKk6_iI61Agc{rub_kE<%Lj5Z%g1#fk|G^ti%u8?7jX_d5`YRut2k
z_=MtL`uWEwwo%?NR<W7Ng-$Bw{tSOlDICXX%ND1|qJ{Qp#r88`o>BPkgo|et6;xmp
zugJXs(FBEX66O;X-$ubwk|M(cyky1upJQk#idX3MdrmQzCe2hucL&tZD};Z*;049r
z_tCnjDCq!7nnFa9mlS8HzUZ=Iz@Y_9y23zH_!Y(45nyL1<O+ypDweK6=T*fa225lr
zzM}L=w&Duy4{{V89Ejv9{tSjsd5Ud|Az7gKU<BhWR9NWox~5RQ2fIZI<s4WlR-}Ip
zh3kqpzlK7IV(UDB-B46(==-0giVB*V$`mU$gWObDDaTi?I708;3Ptx9aQKcQgTlU*
ziWVxltWvx|q1|dl#9d(5C=Lffq*meE059qkpM40udWDVxAPtI#^guK!zNZlOU4`)x
zI-3+nI^bcmV)j1D|FtL#6KJ+7o^k_dn_@QIigv|gG&S5)u>S#ehl2M4{O(j#(gNYW
zqW?4Sx)e7kl=eWOr<iQFf<u3O(4%OetZT30SuI+9itAFe9x9S4M%l0EpkK^@;tH+B
zA1QV$qV?yX;_7OcA5w&V3(;XkKP}xx6nCz{?x^DLA3(+wKT#p&xI#yt3Y<{1wE|{R
zA)&h9DaGtE@LZHnJ_XlyD;052*rVKW6ew=W-%S{{hjM5D20fL}gu~E2B{q@xRVZgN
zK^(ryW&7a1pVGV$GW(UtHRETY{Fq9<0+e620XtCH_8nS5$`@(N6|7uEKa~(=Lk+MG
zD2?x<6{>Vw1<5ewgKm(6$|6b}98!+_fMFk29;Bk|aAhH_=#MCuj>6ti<;+HO9&;#5
z9s_8Ea{CMDja2?Q2p5kl-?$29lydVF1{$rL`8X6$D3@knOfkwiX#kB?KJhzRamt7l
z@Zz*GoC4ctl*=eHnxL$wXD(6s9<2(KlnW^Im#kc$j#i42vjx!Sl#)5<OjSDmo(E6Q
zE5lzx?*(P?e)L{c{wM}ono{^FurDb^c>ukvtfmhJrz=ypfm~5;2!IzEN*V3LGL==7
zjJ&G+M+v)G%5KUSWGe^hot&dw7!L1ql}TCP<tdZTp)+5(lHv&k$~%tv7-6CEk99!1
zrj*b$U8J<QfD|j8=vrJ?zDW~RiE_>f*ez3f(mw2_avc|)<;sgCFkhiGOoRF@<;(Ob
z*4xU*j4)B9{5S-Is8&9F8l5%DQ|Hj?P>y@Ri%#YDKf?TdWzZ<CKf9E@;lO^NOi9E=
z=vL0B6<Ck*Ln>(ORrb-YyH6SVGfX^G?jpbYl^#^ZGoYMF^V}n4vNuc&Dnlb6Ii!4e
z6W$LindJ6}(w+87qsr=4fF4s;(vjkEWpp>Zm{2xHQT?@xs&WTlTvh6mu)9n3d<YbG
zt7Jjw+@t!%9mGwwVh9?0RTV0TxT{8~u*pNUhQe%~s;u|X+Nau;3)j3<WsOkqR<*Z4
z(nnQBi6LLrL7MgaR4R%^?N@bEn$};nr<39@0V)@IS^`xqJir909;59|uqwO+tq_%k
zvM2{s;!$XXs<@QD2vdnE)Ok>)V!*^9)fPU+dssE$jaIm-GXt$7s#BiOJF1$ZY4Vs#
z%>ZVEY8kEZB2{bXc{;9ollHleDAkc)aoM6(qx1thp;FOXEk@PQfg2O6y1NO3IjNeY
zWXLI1<zv8(QyrUv;%U_}TBn~;ZKg=gS=D8lJ>pflkAs(>GSI#;QH9E3`~XxTPlF_@
zY7-%nqT0D0j-FFR(hf7#p<;gtZ_cY;C;`j`l|RK3FRHF)0y|B$Fbw39>dYS4y{wx2
z5HRVgtaZ@8qWazo3K^;^$Doj@>J3EaRn>FL0Gg$G?+=h{)dX$1a#Rhpv&~g0f-t~5
zm1-t1^Hob|A}>%m)>E}_p-Nc|>}#q;uRx<n<(h)dV%1K%+}BkHDcW7CI!ZZ$GF3R`
za&D@AyA8B*)zN8Cs8DffCcdS*vIt|jt#U(Qq0=4JY%h$rQsqV!pH-^w=uxj$<@p1;
zMrAsK&RW$i2QAj>RGi;%o$FO!)9Uc9>d8l7HmR(g@U&Sq`V7!oR68kg*s6+r7Jj#>
zn9I@XP%&SGNT-Uu7V7s^Cu#rJty)fd%O2GciuClVo}yyoe$`|ioEcEH(5CQ_D$N3C
z22}}74mdodQZ52>SXJ>nS|h60b^?1;b)pTfjj2Xy**&hRpqkVP)y`+(+N5elG!&*(
zI;zfcQBVI8c3su0zJP1H)F~8C*sb0`M^W~u8@|PjaaTV_0Z0$^Ybnt4RJYND?5$?>
zQvIio+LyAQzUq=q(DzfTsL)`)`lncE_^YQ;xlw>R@(L^ks(Wd-5v1;?Gw#7^4?ac_
zqVA$4+W~buJvyQ4t#5%BrXIQj%!6uC4O)lP!|%bT!|J(xfDTt5q7RuIQ_ua4zCRJ6
z4xu?TQms$`J6in`#mP>nWlkV5>Q85a7pu<u9j={Jk5O^iDfKs0=o+WCJ3-;JTKfwu
zol%E7Fs8HW##Zp+)$iERN>KN1g-D`$Ijtd*)Q?l4K(hK9nu}7@FTV&2j&o`YMR8Nr
zTVmkiMfEW4v(wb~zQuSisc+H-E=w)_21CnMCsLFkN8NQCUgWCp%s^+JI)c^-`Rd$K
z=oP5{mBL`5de5iOyQcn;s&0$a2FhR+tAFkS@49-x4WvXpDFV6SQ0sQWQmNW=8O)cd
z=OzLBraI;*NV$5LD$Z`J+o)Rjj(U47U@FzAY3Qs{pQN`#wYr=td}`FGRL51TPM}iU
zI<<sCv-N7J56s_Hzgr5@q<%RV7ok}l{2wG+)Kl-k-&VEb*SWxMQy-<$gm!f*B}MM3
zqodL4P+y%6(Ju9RIxhA={qr^qv|F7?DT*F-$qiWQRcF5eg+8^NK5z0+{h<=B^{Zbk
zg24gxZc3~Usi)JLX;^(}DaeRg+6KK*^{ioljj3-r=$AgOMs5^Ow>lvWWKx~}H|$QS
zvwwl;E{!YILGRXBY0lrHvD3M1cg?>l@H{l8$06ydnNAg(-kS3RaMVZRPKioi%`a@U
z{57AtpcSC;X~mENHJdKNrx4Am$H6<GQLmz{ZK&o<AoLGuvS^ocSaWp_d<)l9?S{c9
zO*bDJ(HhTYv`%P#pyJFJ&ClB*604aL4}VW;rcor}lqOIMpW-x2sY?H}=Ff}hJfm4f
z8{M;-I0{0=Yd(DgA_<!QWe`c!EDEFVpCxJL-GljLjUpT7Q#4Of#O9plpXE?Y)!eqC
zbzU>=6BxXp`6><OFKUV?$dRU5OLf7QG_S}2dRepgb+pno&&-Fy6;0}1_?w}rCz7eT
zLD__>nxt^}o2_~67+N_R<pAaXay3H~`_9umI~z{rYksEbvOwcS`Qbv%1B%&S(;R#k
zSG`E1bHyl%HJid9d0o@G2L?+t>et}f4UOAd=q%Of{{wcJ<}!V9^QPtp4HU{X<?%qN
z(0Kg^^LI3x%FtP<`I5q9jw+3x0}j_}yy+xcoo0;cl<GBV61}V0Moa4^O$L=WHfvG}
z(Q46b{~WDWO^gp<+B9m4$9HJ@mw<F?KE4L9`<fLCah<v~*C^!QqxpbN4)kg|FsC^6
zX{=Pj^iVVSD%ATOnx77$cTh7U6dFUC(pN!-HD4!yjA?e#GIm^(@HRvzG=Gf2H5ct1
z8k4KG-Wj}I+QMu&>ZW~S20Hg@53B~ZyY`iOv^=!k=|J(+Zi|A*J}rAch`;tuA9w*;
zXA1iSY8~bR$OLICsai2udxjqC5bgW4?meLGSOE7!wJ*^Zv%|F8dLVgF+d+|lL)taZ
z;OZULdPbrZuKkJv(?_%)u7HO}wFh4X@0d3AS2z=)-M1GcQoHdoppR>HN5PBI_S2R)
zT6^3<B~&N0FRX%z7;R}en6cV~e}Q&VyLSP2r?j7W!HYO;Qza~&)@DsX<c#(WCs;bG
z-A<Ja@!E>#fSsV#Qu%kHwv%eYleFv9;3aEc4niwMn@dmUIj!^4a3)n7T7lMi?WdP$
z^1Pr;_66ES?Hvk$q-jNmVg8cVHx-?iwSmRZPuG4-f!ZtDIQkE`4DGZ@=w)iBashKy
zyJZ_Xv$V%)XxZ9W8(KNq<7%{WwJR?{Bu}f^jaI(4FA#bK+7}xjQmDO|LHoaJ+MVB^
zw@CZu2HcrqZJj^-zOLPTA2KD{Zvx@P4Xud^u}Zaf_M=s<{gLu5725H$z`muucLCUy
zT8%e4tF&{dgrZuz<}Tc>(~eU*yk4u_0lfxotpuG-+S9WD)~p@S(Em@jXuAtxuw8qJ
zHo^C_iIk1#&^A(1zEk^>FI>B?{f*}3E^XHvz<!{um=BR|?NbzH>(PGjIxbhQHk+P=
zKJ9@QaVs8bv#8)^K>K<J%s<kuqm134_N$*@cSw6<J=BM_t7%8=7}5IBM@2`qwN&#l
zrv33{Fvqn|Zb9dSb~Du=O={=U{h88se2DS7=w3<!&sBH63!S@kbLh3OTbFzpWRGrB
z3A}LA&GZIuuTDo*j_$fUv@P<`F}k4cse6e7XZGoYOh9`%bi1#j*IRd(4f8&_nrR@u
zx?ll(^V9tj4#oYt%q<Z0*Zp}6odLR?pQ0708(9F!AYI>U=nU3btI-P4X{ZMGfKEq=
zuuxqiZJEM!KRgMMgSy#o!ox$l+bJ-AShp?$X2W%k-0Sf4h^~ze864HUmjlsbx*sX6
z9ie-C7kH7n)%4ko<GNI;`is()mjOFkXI~HO6S_8fH^%5P$hBDAQJSYt>S`Nd>6C67
zz4qgDGMX<=>k4HcXLKpKfIh2x><gg8>n=Ekp`V~@YJ>Si-7Tt(OVS<q324c>g_Dp;
z(G5<(i*vfqf<RJrZ&M)Ryv{+(s|&i23|P9TtNR+*X}Wt<rGH5`GYXxTb)oaoO4oHg
z27_00zb=LM8M-ctd}QiW6Y&13Zm}0FnzD2=X&IZX`-!TZa&&tr{F<wqHwoABbXGY?
zzV0kVmJ4)gw38{+$rnQ5nl6C$$wj)t5I9<_Q_~Z8T_>QoS&44QAJ8{+O)q0)H+6R?
z{#mZ;qwr~k&Qy!mE!|Wb)xX@<Eum%39bGgP4Oi+?{swlH?s+O@s@9Et173}8HKk%}
zb!(4d^mV#pzoAvHW6p#^gHDwQpBi<m>HN@LUGhrUZPHzw4HM0}2OOxk=*s=UYt?zv
z>$gq!HXSr<*NH_G|GcNG_!Al(y6<T*-KiVg1QYjls=uJvrR$4;r3bn%zJy4(PW=@`
zdUWFyfb7-1LwSHcUBb`ke5hMoi)+!Z8>1KQfG&cjyGOdyv?CwXjZm;|NY^wAykXtj
z&w`BTo@;=*V^nwlcZiPZF4GEoTsMb~+)e1-r|-i~>V86rj?<Jbhl++>^n5y2=c>QG
z5kuRfPo|uTn|_Li&b@kJ6NtOM?;Uh{=mR_f=BYo0XpYl9{hW{Cua`dKF^G8UzYayG
zkN#V_6}}F=eL2wl^x;kD-LHR}Lc9L@Wv`$!K>ruzO#<~QiVy|qub6S2gY~PZ&Nf89
zfzsgz^j~lw5~{Cw7h?+3zxz2%9Mr!ug4Q9ue*(y1{SQ>@6|O(J33^BL&(qfDsNO3Y
z7LMs1OV_|)gg$o>9FEklC;j94nq}}UN}oa**=Rlg74S~z1^00eWAwunfQi*#{2ZMp
z^&VxAJf+{d9?rz+Eq3ru>%Texy)*jdG?Sjy^Jvc#ufO~aoJr7cJPVOzeH5+ZQuJ#b
z6ofvf_pU=TRlk+|KCfr&hKm>UaWR0osGs#DG}82cpMuCG{d0c;?XsS`0j+d>CdIO@
z=x@+o>8d`Meq&ksM|~jK`hDZ@DNjGv01Ns0kK!RxppR^adXawg5!8$I&5QnD|Ec$-
zZB?oMJ_WJL^m$bFb5sB2D<IYSbqaLW=>ItmjavPSXMt9y7tnE&dc8YEJ{t6U=(Jg*
z-ieNc+|@hQqSd5#mqNW+ud9Vfi++M~&aL{E_aM@y7s^4}^_$Wt|8P&A_7Obo(C1QE
zu~VN-|3`UWucGRqF8y9A6MmroP>3;g>*FbF+oOM>8|HiUkJA&_r%$2Uw1;|j0XqBj
z>NkNhpf4$a<Rkrq26PVU2V_7Q(tl1X+%Y|i9>j5d;1&A)P3VKTaClPhPBjTr`ldu^
zxEQMb2B@py!*uX=8J_TmPkRlE>2>682!0RP9)<(-tMW8FpjXa5!xB13<7E&}gL!WQ
zk9K@MhPn;t^fLr42ib2hb)nPW@J%LeZ-C+S37|Lv4ev6bA7scn2WGJ0VF)aR7!Kt?
z=751SAG}b*mtTS$G+4O6K4d73frp0;kqH0|H>6Re=@G+J6)w;*LjnaNA`HI|fkYbo
zDYzJAcp(}ii#D`S+VX_q2YR=~8vJP+c+z2*pqI=kLo1c6#2H5S0p_%U-G)}Yq4z!L
zCm6gb3Y%y+f%Upml3@m&mQFSpr4UImoTQ)1Im2wqLZ%vCZHDA|!;EgU(hN;C7~v&D
zQ#~Xv8y<falIe!0{vW<EJQ0h|41?np+I43dj(m(!Ts0)qzBS9RjN<CqhC|<hmt%PK
zE_}*0uzrO`p5gw_Fp+QQUIt!)A*2}!g@#YR!O*T5Uj7UsMTXSH04p)PJq9ms7*bDy
zlp4-ZT~nDMTm|);hBh(O%MGtND9Tr1$V)-*EyGR~^luy7K7prq40W_ftTec6f@qcD
zyK~^x81~WWoLWP68a%8stg(aC8~%F|C=G_(lMrb%Y^X=;uAzli{Y{3y?!fzIL!2u-
zY%!=fFw|=JxD%aihA+=KAk%L6{5TZv8U9%S(qVY+cXW0da%sPO-?0B3h;|u*4}tf<
zaO_F6x(zmO_|#)?J`D2E(03E0-=L$S-vL9LFU$`a3Te|mY!H`Y5F>`<w?IY><L5xe
z4Eb+BWZd8(r2k);GDQ6aY!_qL3NT%bOCQGwcN=eRMCTr3!%<v4H)At7v)5Qc&y~CJ
z>d$C-7<W^-t*5c<F3j&UCR?H4WgMe-g|~4nEe?H*A5g?(zp;UWlm5mqsw@vMmTv_K
zG_v|B{~lyq9)V`CG0gy&5aYmV7(8GcrDrbGc#+o4VaAIznH)6kp;`KnG1~<qhmFUm
z?mOH#cOMKMF-9_=e$@EX0ET_c82=;`B8<Jwup4PyPpO9E#%ET7#29}rgnF!Th!)|F
zlg8I6iF(Rtpx{}Y@mwbKPa6{{W^u-7&qU{0<4=pA7;l_^03^ZK6$_C><L?>JOEPxX
z11;I;z83~ljJ3Bw&KbXT0!cOUDI<H{_{Dn|#06vIQ&7KXe5Mu(X~w>PVBwO(c!`!*
zmyIjvLjmc=|7c}##n>DK#SG)@XFxKIU&O=URpUx3Fv>E%N_o6&;|1Eu<QPAqTu!cW
zM<z_<8J($OCEvI^5-0`6JBwkk(74kH1HERPRSr^Q6fhxKY<#vBlGlxnl@!e>F)ncj
z+6^O<QhlYy-)UkkGqS4T;!WfH9*CA3S6>0CFnZH`bIUmV0-U*R49~$p?--jdp;c+@
zr|5i@v1mD3)yCE*;AoBU1Z9b9joviR)EVbfc&^@9T#e2KW4z-(m}oR^q$uBA<5yI*
z)MV_ZELpR$xDlOg#`AtqY&U*97rcAMB~;ecVKmTJb2^QguY-5r=tMWI%NRq|h7XL@
zl+5Tho-V~edyI$a`>MUhU?YaqXMD>Hk%z|oVJP$)Wp7jbWxzNv7Y+{@XTAW@VdLUv
zFh`8z6p|V>{z>M?jDOMAbliA_iY_LMY&sS`Y0O>-$tmL+N@lv4a_Kg^np`Njvdh$R
z1|qvnHG9z7V-j72p1Wz<hv@V$4IhGnr|H=)s(;yM`ojk%yi6kk$atI9{R%I9OfxBY
z<ZG(`0xdsN5`BMgzbT#zpZrZ<%z>o<Q}Y9OA82}pJ~<X-`iP>7!KQkO0EU=8qUhiO
zlR^Q>P*Y|Jcwwd&XcjnVVm=O$L#9*DOvCT*uqlTYiQ%TxwB|ZuVm}MC2-7e=4&xMQ
z+O!0U$4xnp11-v=!N=8{qD>3hak);IR{O%k7?V4#zGF=_^!qz$a(W3Or%YvuP>(Z7
z_~<-sT5$}RXG}4ajW}zvQ<NaV<Y!0Ak!X5`_LfPeg%)_4Z2ExeSW-+20-$luH2**F
zQcdY)Am>eIYyiDr>KucKi>As<_>^YK-ilVb>4`2ldd1{ljLr<xayPWHOb!7^wrMSe
zvT{tWGK@3Vw6hr&@=WXBMJwN7^8Ek8$aE+WGKHpAKCaL;Q*kaV6`8)LOjfZ;PqB{c
zrcydvQDRz5yXPCGTeK%FHHo63P-g0)V%D3cTR+2mxoK=Iuq#acv%$M%($W_3w#k!D
zV&5^n)eMwMll3L=s!WbWZ{Z46o4n}!UybSauP~Te)7Nu>U1xfg(sA`Bmv7*3gK5$4
zu-j;grb4c}rcMeCHJKLD>bcp(s|T;e^py)ptLenwFyC%^-5GlKOryI1-C>&k4)i)r
zV~tR_Z!*z=&@R(<M+bTzn06MRx7+meTsYHX8l&KKuW2i#1Nuyl(Xbzy$|)?^Z?aQG
z#egZ0$RpD$26!=O>T<?lhD;xv2I#P<g}zcUV)}sgouj6@GN6o^yt;uoZd##6=Y&ZU
zi0d?IT2<lz_LS*u7Cdz^_xhmM)f~46qPxtsbVqiZBdHu^kNLkmV7r;edvHnino~-^
zb2o3?0^(t=P6DW>S$`0%eP-Y1AmU}V(`wS&>`tdOeau-tAin0PREYSQUFdn*Z)Pv1
z^GE(>87=7p%)2Pw8)%N-1eqYSJPM$}=7(MwXo&gjU+6qw{^Sf4L(NNW0z1rH9E8yy
zG&@t&_>g(^VK{o&>`8CKaB~4g@Q#=}*F*29x!w(u$IMeST}7BbcHlNenqzRp!Qph=
zyx18sQRaD8kZ7~}I1HXJ_cuZ`#{30US;d;4-3-u^<^;;PpE6&ddl+Z_hF<%p&GL4L
zoH75o2B2rnYjq&;W>!DI63nB!z)Li53B?^rGQUq**JSfkgMdykm(wE4ao%jBm-z+r
zlT>kb(LCcAu+z*Q6k57uzS{zg%jO63Fqm}n6}tFW%nR;AA;Wx}_BEO2gA^CIYHt4*
z&SaU_FGnle{3b0mbIkFyn9Vgmh=gRG`PD;E&o_TXQJezvtCZ9$beLyTuHc&a!d-|K
zncrCgr;5#&f<dmEKc+otiFxTSK)Yf7jxzP7=6kd+DKo!Gck8A(mNNC_=8WCoRhWb5
zJ#x!@N{i0h=B-rRb;rEC5C$vF8K=OjGB2a~yxRPHIL29HcGOX>t=9arKbm#s+2lpN
z`S=}>2J`b0xY%gcP&(nR`GsHMXp{N0H+*U~TYd&;i+S62v|7zy#X_Xbyoxpk?dBVM
z!MkT}UyoLYxu0rVI?aZ7h}<_1(6{Nk%zq`L^}zh4!w;6a%`uyC@q5e#g>bmn{1Gh)
z`pg<CpnhnsnT^ZcZ=OqqxdY}Ioj`kJ7So}ML33O)V1~>qSx^`@vtESAh&h<@VWVb6
zGt7^fJ6fPHZr)09-U+j15iCrapQY()%3NJa`#%@UyhwQAYGG~x+Ahnx|A4vMQb2Lr
zJ(kDVfN{5YBtpc)a+_vNPfMQ${_eBn?}Zm$mL1#Rp|@rBOX&2oR8g_je#^91!SlBa
zZ2&LG^4SmYDcHjK0GJ_`((C9vU<p=H{4><Dk51f%S$b#@f6$WjA_jBF67wOPIc%Bx
z0!X;!XfHI5Sh#;d<fuigz+fURn<?Rc-16#fh(uWoRO%URVbKG8!t!e>oQbg<*$R<U
z7H`@|#aYh01C-O2=U0OlZ!x#h`ZK}ucng||mXFQAPO+S9hyFQB%tD~0T0V(|;(1Gl
z7p~I<OA*C;FIv9sfk>Lgj}icvEUi?Qb=jh%utvJYgHB&vu~<2{2pN`bpFttZGDhWo
z*_Os^T)Z61lkY+y-{SNuh@-#~b{n+NvVcOvMV5HlSr=P4yI}XarL7+NC6@dOpxv<K
z(l)TvGCddyWtL*9TEA&oNIS)Hi$jmAR$)29MdvMx(f}{+SYkHe-c?$b(K@ioA`<|t
z+H!IhS~ZrXR7X<lu*CF1vCi`05;W^AkG_LOgXOy=7-6I3zZvLkw*2-r%(qy=i!j1g
z%c2N)*k)NzPhh(xfGQL2Sw0p+q|=f~D~tP<=(AAovdp2i%LB{U92o4jWK%&@kHzK#
z*Lp39Znz|U7Dq9KN*`MM>AC8+6y1a~1D2wrXg#v{n;<i25mTgS$ikb4*05y`6|jt2
zrqQl>%<_0E{2jNX(`-3miKJs@la^<ngKJZkEk8oR#hSGMKDk<d{{x-7tT{WNzS|l_
z*Km*Zo`aT?Zq`m(Q}4C<)63Z1+Dw}V59`aZ7?YRPuK?z~t)6rM$j2)Ff1Jwt;g@Ln
zTaO=r-2m%B+K~rZAEQc}AZsmUFN3X58PE!~uA2l(nDuHc#(B`nqR7P|tGWlS9k#Yb
zQ~WdB>P$7UN37d-K;x)YMmdpV))gmVH^Qoa2V;t~rd@(h$E}5{K%%TcQy|gSYqW1X
zVXdTWVvO~*Fm%RRpFDzrp0xh393wn!orgd9ayn!E_aw}pwH~#A#9QB!0yDwdHjBQ$
zn`nLR9-1lE^j*+6XYEP{OsX}4jul+Ao}<@bnzewwuyM)CcmW14TYD&UpKfKa;O`Y{
zHNA2&tj!-oJ<}?nw98fNwlnY|%jz8jUbc0KKUz7~YZQ6RwO*&>TAo#p$=2bNZ>?>I
z!2&DqIhZK4K24vRxMsb|!kCJzvnVuMZ2e#xu&-O2sW7m_dgFVb-LP^f=2vRHc^8sp
z)>r0$chmY=Ia=k`ZM3DmZB@`({Eqc)s+O;`zDRMoD(kV|(OGTn-3v)ajWx*^BdoOs
zFM&p#bsNQ->aAa!fYxA*qs!fB-BpOryVe4lA)2g>6;N!pR=2~a7VAHB^rqE%5|fEj
zoAs?PAlYtRPlcQJtd2aiI;=6*F^Ep<&N&$NeQR$gu3DE>_9WCFIIPb5(d@RqoCMJx
z>+YFwrq{ZVl1C4%&5wiEZ!MtWlmY9#O@Mi1%}E9sw7zf^&J0=aJ;0cTt*xIyVZ?ff
zeq&=+Pcz84^%1QDC#=KMp)hH^_Abm%S%0F;nTzeW)#!A!Ib7#MaknjjCX+q3*fcQR
zY=iVCHhXREejx6)?<k|Y&!!4Q%gg3ug`~IbX$JItY>8Af?`uos<0AOk77xJSew(8M
zJbzo%_uvKCd?`vEXd9z|c98AH+prL9TX-6nA+}u(DmOY{Q&F{ks4e(;kT9F^6(}CG
zC6!^=hio>AOdYmG<-^f%n`H&=$PwG_RFI>#cY~pR%;w?(pCW8a=~D!ewoC6o{kZK8
zMO>n6mnoheZJVUY>x9iM2`DkPs05H$Tly%i#7^4AK7xr;w(l;&#WS|ul)OD_+xQ=_
z<89$n5J|9YKZI7I?evQfNwUqR<>WbAIz73mHcb;+=WVZ3aOHw6-wN{=Z5z_yOqxwh
z$Ez>do}#VGWt(s<I@4_{ZUO9y?ZQrqzhu~!(AOI?ZBemsG0V1*;u+btYfk_)$96Co
zp61#<psI;Ho74r8`L><MK?-dAPhh^#_8o1`ifkE_Z7Q~Xe*u!$ah=gwVr$|-{f6zq
z|0~38A{tAXttkziH*LG$r1)pKZ4+e<Dr}Fa=Kq%MOFxX_wym`tqqt*hr948VZErRd
zt8Bd#6RNh&o(BCITl03bYHeSp!)~38`vDZ{ZJj7;b84_%9l>}TZLMdZch~mV8u;5}
z+p2=0W?L1Nh_=~kQXt}Jx7B(;<DRXNK8Vt3t6zrJeOoEjh<4fj(Zc)#n~io2-L{Vt
zq1a>Fz6Az*ZF6n_yU(^G4xkTh4eKD%Z~K!@3J%!*V?h0pjo|_^Xe$^2Z`iitArwYz
z9`qI-wW+5=a?D}-k=8fkwuCPrGilS&K&Ncw<gknV!5Nr$wMR4H+Aez$&98gx;dRh=
zv#&e~k-hd1dgHm<f1|aJhy6*~?|Rz3y&<{J{wl4Bz3kl-OY*j-1)=3*|KvXG`r5fP
zCHdJMv9y8PZ~x{?F#YYf=@%PdpI8H#K>H-cu!HQy6!!_XTPUs<Vpr1|<e>eTDv(3=
zR3DJT_QL(R2;ugTJrFr!@BI$yN9_%iaX)6CLjjNo`<7tvBJDZ}>>an~WMD|q_8X2G
zh@P-N|0hIa?0-_(U93I&Ylxn-SJ2M*l-(}|yf}MKF-CaWKJXUM&e*rifc{zgcabok
zU|&EnheW&6a}Y_guXqL5FxjqK49OHbYZbuG*)LJ;Z>oKi&f1)}bK}vvV0UuR`|qN?
zjpA!*cEfh~mTvD^1(_@M#W^4uc8@HW&$QRj_T;L4gnsZ@_6@Xu%(ll`pq^u2O%r;q
zowpGRdG;$m!EU~Ntr;ULu-oXH7KQdjbZYCG{im%^D6;RMnz&+nUpCdBUAKQ<jb@2`
z^CK{C*kfshP-<U5Tk0}<8SQdz+9R(+zudl94#^7p*bl(IWw$s$Zrdkmw{XY)1J!+3
z+BZ-!X_dW_veVV}S&QIkjlFgWFl+5yRCQEmze}}_jrKQj#KGZo*Iu?0FirNQv_WsS
z&uYX~Z?QlB5Q?q#DQAqg&3<PGu5-Jc^(7?l+3%i)eusVGYmn@;d($HPzP+8+K3(=V
zSAsmS|AN?#Q@6dO2BgRSGM&onwJ(1bq|d&9s!|@>Kcj4squ(A*p}zt9{DV+@WRI){
z=%Br5CS-=}FVJ9y?LX0uam2or2lJzL0ma<M>}Dzr7`Hd)KxD!`pRx**_J59`bIShu
z1c=M;E%Zuv{r%j_Q1~B9-vJiY@xAT6%L2PBEbP5|cb5e;CYB@`O`@i0Vu~7#8e`N%
zV@r(2Xf%o01+gtnKswmyT|`hoq<0h$1d*aN3mp*~Vi(l!J-_e&JU$%H%sKBlGq=pl
znKO4?bYIb1)>Sv^2Nb&LTB*DC8+1D<j^eJHN0HV8y6v=`=cOA<qmsAo!{sRS(M_cM
zCSTp65=i>##y^I?{yL|JXiR{v;WW5F-9j2LgLKDyz#Y^*eg+eVbT8@n#bMoTQ#AC5
z?sFP`kLuK8&|Sege@ZqC(HRyxfQIV+_}}Kdu3{Z}JzO_=3rK|S1x@lIb?;J)GfHRJ
z48>?&CM{oMbW{I>qp`a03c$tbB<_%m*S#o3UmVkYISO2Yu9UnuuA5G29f`UKdS{=|
z`RRdjN_TEExD?$2!#=>I>KtidlBO$7f#_-7<|$}sx-M)J(9Y;K)5Io2xA_jZOkGeT
zxNO~SIw+N+Yj1&GuI|-B=;i5HdgAhRcC;ug(5<95X`!xdEDRRuwvoYNT^vn;N_5c_
zn<>>T|CI7S&+6RwLgt)qJ_XdvbT7U}<$0a-A_^;Y<0%YUrTcmg?AGWe(xY-wcZ6oD
zwYuqach~EFDS@R1UCu-(H0o;i0;Ng!5e562brar1VT*40VJNif%rAko=~mRBfmd~9
z{gi*!u6q{;5yTz3zU4sc)LCSJbm{)0*lM@#_x0d<bQ5Xv->Z8;Q@%c3CMCDr)UDhJ
z(yyCu2A^)}0%&J-KsSf>Bya1E=b>Zo=$7At$X#6qCGp(Ty|0I%`?^7zLk#Lxy>E=?
z?}2U}<u?uK=F^1gp|18#SbC&;HV0^rb$i^Q_(bPN;h(2Ee_BL8(_NN=JlFj&0`fw)
zB?^~$SobMqEsW@{&@=W@xA`mzU+LOt9rjxH=2zgH^l}f_b=JS8kfDoy8|{Y~T=kz)
z@{*h0A`1E*`l}T9^wi&41oH><f3HI;y!0<<7sOk?=53()=odai2m9(Hs4x8VA-yQ{
z*VjA%T7dq;6sQO4k1v2;kbWj@0Uy*Kqe1bI{xer#9@e++g@;G<VLw9ss6j8HWV&Ge
zG;D^7L-aqk113}-8xAf^Z?g?D;re~EU@$^oLZ7jS)PGGIcv1RJ$`X#&J5jz|jQ(;d
zP-68=4ot-97tRBT*Bjk|rDJ+uS2&ZPH?Bq_j_ZG-9}7v+?_YtsWW8a&1z=9<7rjK~
zDgA5*a4GtUchMKAdXr4RoYpVd3iIjuv7-TVM*q$QG$un|8x4_6{j_tio1?E2f#m8P
zzk)M)dao8J<m;cyz!m8KSq98P{VW=Vi}X4MT(N%sAfQY1BEwFUmg$!t1zWB^UIDH`
zKeHTY=k+fsHdCqZu7O6CezhymF6gIF-axh9LknkW^uL`%D=zAnQl7&l{n0rfb^2h^
ztJkku4o4gG&uCWHs2?{P{$A1F8HK_o{rU!Q&HA!`3_xqq`_iq@s&At}Mw{Ml0G)qT
zFa8~(*Y)eah5ilwiMz1WuFv7Yb?9HvL*1$0F%_1&^mAw{w_9I$2|o4eQ;(u6`}Ar$
zlzUU(cmsv~`htmQ#4SBSGk8Yyt0_WzTW^~$#`E`Fzsv||FZH{RL*})9);bUu`w9Wr
z`|Zo`Lc`PE>nCV<+aFv4;%9HR6e7{~8=GJv+1?}oB+dQ<3Q%R(A1Q)Jj{VI~;ZweS
zHLWy@?5|~`Nu~A^X*?*mzd=igYWqYNdj783+pI$6E&E^2q4f{#+bG*&*xtVkKDj!u
zbnkdL7*3$h-(lxDSPF5dqL^QdL+L9No^Uu63GTGRG!e|_JNS&iZka>20;JO6*?Vxb
z&Y?>Hcg3N2BSidn7Rq5EY-e5|`pFQtbNWYsIla@FPNHS)EWCkc7wxq889r6+oJglG
z>vnd~ilS|&*a0FvJ4aC>NdL}2HC%hJbI+eJ@oeYh_n<ej^D|R8<Kp;J4I1j@Xyt}N
zUq=UelLk3%r<CQxj>{>nD$J3kkZ`=g@%cv(O>`VIf~Av=^*s<xbv#LrYP#dTeK45m
z7)bA%EXQ5F(8zWylA$igF_gjsg^n{)!4)}f>48rrjvFbxqtx+;E9%ZV7F-88=V-SM
z4J~u*-UHXl9n;hx6^`Z|)IpAhQFP|5%JCW{>Qy`bM)Qms$8Wwu;YCNYZSbkqQAG>5
zOO7AzgWvUzt=~bU!SU@esB3h*MRAnNj(Ka~VUuIpb4WHj$|%^-;wYwVyjI8mC??zG
z=z0;Dy^hlm5Ev!KzjKTS=J;5DFuTLx-xWp`1&^AU$`!zGWi)$$c$JaSs^U8Hw*n&V
zOotV?PUe9e_`QrPhr)YIdm0+_lzBp9f)l&;F317aLJyQ6wliAv|E&q(AHbP6gHyr2
z^>jNdjY~^|vxf0TG|il_j+XYH1kz&dQ}HBJf3|Td&}Z@+@psm*bhz{Lx2M6SFBUC8
zPtA^>4Y)6To&e&j_5CRM`T-?|f5TIL_Z-7Al+R7FgzmiT2IziU&<dIPh4lC>ct)?M
z?^v2EEHsq)p?4NV^rL9;P$~ZZ{g{tYv1EcBTJ^)$&(NBs4b*i%MrA{0+20ggT3$B>
zpevkL0Q9G+TGalmqxZwg_z@tivZB0+U*4kMVOnk72a{_?(fe`j&_Q6XQ+T3ey)GM8
zehV<r+kb;D4!!leU<HMZpU?*iHvLVBMSmQiSMKKX9x$+HTQdIcXSxQU;LaSQjdc%Z
z0o{_GOfMZGJ;2mw!>$*TP9vE&<1!u)K8!1!x$tGCCqN{SsW<|?4(8J=cygb~`i}O0
z2AO~8{rQ4vq0H!E=B11*vC2sx?yTZASz-+Z=uA&`(-xRGz#gPK(~CVj1Q>68t(`2f
z|5(ErU-nQ942H87v}+c@mQn!sI2%syp+xriJ1}&D)zTo4#1?-?>+fXtZ94RDk}aeA
z{1kg70oW<*rxYnjWzT!TU>f^%2e41G`)P`k&Q{Py^BK1C2JB|A7bk+tVm&D2l+D&*
zc`VLhf1*v*OwnG7lx2y`D4!-<)Iw*{azwrl;7qRQ$W8kGW1eUtCG+Qt4$>m3K*ZCo
zPN9gW^wc6zTPjQxi(c&jOo=Fb4O}Y~by0fuSy815Fy};7i=j{^+D}=v<)U~`w538+
zF#!h8izLSYT`8Kp9bA>Dl{Qx{h>9sIs9N;uD-c7CD2H}zFN#h!!C<ZE1}!lziQb_P
zt=EYXDA}f7^!XxKY7nK2fkva~4SGdh7Ihtkr7NPbRj}J68od}Mnnk&Eh^<AmmLyw6
zPP9eaCffWl6t0T0oFRElw18IQ*G2p1z`_lKsEbzI?V{-cARVG+Pgv>{dC*PRC3;R5
zrdxDh4ALXoa|JNHqA*%O_lctFz}*xrHi5x@Q5>!4Zi#xP0CYff#0ToPMH(8(?ua_p
zqVBF}$JfxiCu+O}h5I58%2pW^8CFxS`2*3xx6lbgB2y(CekkI$qwtZ){s26EELuw0
zOix6+-$30{(SNj8@=T-;2KIAN=MW6O5M|||a9DJM1B#Q;(KYBwXQSU~(wS!T$z$l9
zHY(5qGu@~o3fvi^<S9_dF#5{S0hml9=PQ88GJ0?arP)SvlVCT;sF)ttOGXdr5v?<t
z(+I_SBe!#qY%p3@33AOyMTra7jb_p(vU-i4(m>p2v_b)eTSkL)T?dS|j)k6w_%_9;
zJjJ$@PkKN+ot8vC_&pBFfAAF__C~3nSi1wx_={^PavX(UC5J|?c-0pmd15goY~+hY
zbkPgMo@LN46puO!OGWstIG89Fo6@~nBJL}MYo+4S25{%Z`^Lk=GI7>k6qbwsqFk&B
z@v8+;KQI2diQ><d;{R^LZWX@R4!ak`TPR+C!+3iru-lErG^gq?o*D+yX*@#t6J5r7
z8hpBqmr-~3828d?hhF3A$#k`hvmV03C&n{h!{67&&GexXClf9U>dq!p>fnWoiI`Tr
z-X?p|B!k$;q{s`Uz9yyP;HjTUI!)UGOrA|fUj~}28wM9-(pUuUkjXfD&mA@~q6Nnh
zlU)tqj+#uT%*Zg4)-536CfyWFi!d2WFSa<7gaQ<1nB>sAKGURWD@c}!_AYuR+oa+Q
zJT&B*j6MPL`6kO}p|Zea#WeU<XwonneixbCT><mOCQog^oi~Y~xmcx14LuH3CJC-k
zxL~sAGZa>v#Pk5=qDc&0!djD@Z_qQ%CV~~*ZZT=1X>F^?t4jFPW>QO`(`zPCluLZw
zVDc}`i*K0hUjvwS6UP8xcbXJYjJnGtC<TQ*CQdT|(`&Mn-Y_>!N|K<^Z?d!;A_FEF
z*&ugJ7S4y{U6XHU;&IPJ#lZ^~Q@geBKG^i_A?Sse=3Yc$sOf+|%!iqFmjg50)bJ_2
zE+b60h5#ngbS-ViM42{rLNwa6MF*KU)3aBA9dFt}NiWAtA623-!SpwZFeIABY=<)^
zOe5a{N|I??54dF0h<T7aY1%XwD4C|A@575M)4cBhon!i54xGs~tttX$p6L$;+T_eP
zwU35kp{a&qO+}{bPoT2c^sCJPEirv2prcAn$LvDkIn$X}fL3NYOj}~*rtkd&v<lNb
z-=eP4^gR{|Ri*>?fpWq0YdTh6V|td-N-vrwP~^AP^uu4l-7*b12=xI|_YwoxJEqmN
z{J3lS9R-l@nHFCFxo<j(hPnr)Gw5vDkZJ#UNIo)U=_U5qG=(BauS}~bAo|+$?J}r4
zNglG0be4Qs2xnX*F%-LWm4urE#Z7XT(uVg-7Sl`DUD7gyIuFU%@96xqr(~lIS{NWn
zS_hdxNx=ZH4@!EjLh+EqYdOdfNzE=O9+mjfLN-;hgjP*yl6PsuOP93M+Wd^fhVqs&
zBt1^xG9@coL9!&x@50|~Nhjr0<Vf6`(KERcZ80SCBrk5$_?ItXY4k6UbQgdWN~R6M
z{UXWV6gMcAy!{vSOC&E}K%-PLmS**5C8h;*DJ0WrC0QnMpj3x)$y*-+yFwBcj=J-b
z;}ol{l$b7rUX{dY9V9PEn$`fUTH^2>NR8y;pYYyLE4kYMnM;zT&(Z8UNqH>L>LsR>
z7TzG4Ouu8(D4Fbn!pjmF2gxgvt#k`CNrF2-S|qP2Pq|eRLu=$ViNh1vy(+Qo0=Xtx
zM92BBOBA*+e?t=cBV22jNa;@Kkc6IrUZ+9g;D*vJ$t*{dc1z;LxD-7S^#YJy$<_`S
z?30|KjKQ0dD>MP@mrS7v(Je{G_b?GCef1o!1xY`d2!&8-Sp`7Dr22<wTDbIITB1it
zb02|3Nn57_EL!>&eN;SFI(IEdoYb(`6pHauJ>}{hlU6yP^td!-E?^R+%WQysLdwzZ
zb&~YVI)I*(E;dJ9igbVyh*G7lbiOuE8cQj<`O<)i@TpKLwgqO9G;1R;E2O_)0p=xX
z0!^gqq#P~S>!tfj(4+=wnt{F=(J1}c7K)dprAa`$A{|Uemo!Pe$|2J%eJcibTcn>A
zL$XV{g5uuY(y257?2*o={OVq*Xfq7<NpomCxGDXS;+y@_+4XSymUN68pl?ereGl_@
zq`%SJ=dSe4aWHgG`avMYpYga-@NrOTMknMRNImF8!;tj7S%7&c-AIW%kEFxCz<w+p
zM`QX^sr4klJd@^A?#pwjfu@5mq>@sg3`<j2fs9C}WI_F<^fE00Ur8hX0QXw@F`Y7U
z!ta2>HD@#J1j>JKG0UQ5hpX9{^(b{Si==O9?l*IZLr1xreNQtu53_b!9C?|Yq6_P7
z_BPEPe9V5NiH)CG-GAWx&6ZifwE(lEU=#+LT}=Q=klAH=nhu(6_!itDvyR<Rk1&h;
z2W^Qo6C>hl5J#D94ueLtnK!*{W6jJv!Nr+PqH7;-rd$lJ)9e(5g`S$d{T|SqWGmJ{
z(pk1S5(Zsl4awxaY-txn++<5i;pl$Zyl<g*K=vN3#=K-A%6j&e<^K#!ADN8{B>iN+
zngPY&FZ=uhG&E3_D+5fBtmhD9j>zgx<EkB%nax05uq=NQ+z*jO(rYVBc8#*d!e!cp
zuoNMaA&MuCl<7WzLbPl&P10gyX2#Hqm3e&*%s5#NZA%`L6@G-m1liPG5IHVO`xsz}
z2ATb2&~%v(y{*s4PL;rXhAd<O{LYjaXmHDt&DB6LTQ-VPesW~__dxPwpVO0`FN>qi
z!XnvKI`mK?Tl5_yOJyTlV7FfO{1*DTL8iBWWTQ+$rvxv{=9YuIB5V2=C`~fMqK{G9
zEVGG&euwOvW^kRd;(k<i$vo^K+AVvJa=v?I&sU?Nw`4OfgAB;r+aP&cw&5hq-;tFE
zK;*t`Ne28Kl=V+W-2<7`Xms$9>?;ahJdypr0pzJ{z8I3vWDaA2@>~{csD!64WFMx$
z(y;6uDZChw?Ys-~FJ(W`BjalxzY4_9{1Qb{{mnml4iaEK_6rmSn)_S_2{M=ELhqn?
z4}HG%ka;^j6^G5=;{bic++_m5j+#doK`+?+K7G$A#QdXC5D7KUO`+#6%>0jq5Dho4
zv4?Mw<{do{jWR#{8imp3VU+t4V{T7tyjb&z=TI1Do?3_&#+(0g1th_IVl6u1xOpT!
zBZ=k#dw_Dnyq3OnkZk^B5gK~Z{0Ev4oiabL6XsLQH+&9~YToQl`#)*suSbJDZ9Z{4
zT9I!4#&js2F|T+6yBX${UC_@m9~%eaX)#m?a=_y6A0X*vvEeQF6lAg69(F@5lHRAb
zSlp$&v~Y_=UpN|J@sOr-Q5K_J;AphPa@rM*vFNISg;<L-o9O!kaTa_u%*R{&Edx1a
zk#Gr~W?GE<4<yTCkdj8TEo>z)m}6l>VZUmNg%swjvB;YVn2Q!;XmWYQ;u{(pn=Ixv
z!tG`Y2TJ>BvGAg)SF1(66-3%B;-kS`wJ<&k53gCw>;tCZx<$a-Fmb~ow;mU--D2*i
z@S?-Qej7wPExw`N>$2!u1JYyh4u$4=E#}hJf1kzi9KhVP7#c=lzeVK{C=6LVIt7%6
z7Ta1;_sC+kHynLzv0)erPb|*O2lv!MGzyJ)W)VS;;d6t<G!05$SX9$jABHV_rlNGj
zVj+bbURoS9z_nKv?$5wE$^U(YI%oN(n?PLTt~LO5m48Ork8bjO8n5@u|N9VLxXa78
zf%A~B{R@(wa)SW%1M*Q#Q1Fu9S%X4v`4RdwkdNG8PV-P-`4`vGLO=Oc+6eKN`v;>i
zK>i<fX`p=B5bA>DqasjvP#zqQZaXYr_`i9Pd>ef<_ozIYvc7`lQ)x5|k?Uv=AXF}G
zLeGTB&piPbF1L}wV1zup1Lh;;Pk(_=(Q-?}MX)h)UpgulD_=vQnK-%sIaJ2WpUy+w
zF?sX*P)v}&cM;^c{PTF2I3Zv91saniub}m6vYh!Eop4e<m-b3d$zu|Lk|N)|5rwJp
z9$HtV$yd@jj?;4MLl8-qPoxFz8M)6y+QH0_uegRbWyyo@K{Q*wuN|F`BhPbyey;pW
z%2m&kS51KVe7WBSa0T)-dfOJtgNoryh1_QdXy@gVmqMXZK945oRdOlKO&jFv4?v_*
z?nr5Em*pR?M&T8?eI~$~<n{q{{<2yAR}t*C$QNPGD{hs4mjR77`FIM?U6uP$#?du-
z1}!nK%Pm7ucth?$fu?qO!ET^+$c?D;JLR)JhDf)3@}DT|k-zDPmi5Y~4Wq74{=x+c
zH|1S2i1f?X(%^DSuJEDfZ$N&JUfQ?i`E;Ayk&l@Pjl1%9wJ5wNpJIo?`*MF5Xbj4u
zo8inudDy!^dnA9O5_ON|+l!#^M4nLz@>Kq_3q+pDm(z^#xqOKW8u~(B6$1rl%c=G#
zbg|q^XO3JgJ^avIgPZ00ztARk%PN1Md04(|0q1FXWdaNyu$(~C1}{rrx=h}dzthm}
zW7+a13Vkgv(e|L9WnU`n`deo2f~5e<s}%GLw9Nk&mJ+QT&CrM>t4ShYp0qOLLNCQi
zp@lPPR;L_bA>Cm0MlLimtYo(#lVvsUJy^=K+F%9ICac(N=yzFdqIC9dtD<;tJyt7L
zg6p;Vj;=_b6-&pHZd#?%=<>j73N5FGtX52d<P)p6X|v*))j`_+eQxDx2J*s6W{D0O
zw)&Em7b8}NWfX~cX=Qs7rLU|O&V$|8R@^C|IVpN+H`ZC9p$V0XBAZeyTowP!gMyEO
zIS6cDh5bi>2~$j?^;@`NYXF)ZsrZlH;8BXp-4KaZ7=H>bMo~Hrl5q;(8Po|1zgj4y
zDg;9;?B*&CQC@eRqKOVP<tx13gG{;NCt4U(DBe0mcemoBF6dV(ZvF+uD#fN5AQu!n
z=@eVFBKr*VY7~=pqwu1_Ya{H|D!%_2<dWjuK@`?0&Xk}@^@<n@=w4N{d<RFbDJtGD
zK=HbwVjC>oP&Ck|LfREOy})%Slyq{dQ&B@HFkOm@S7=4I;`>1;_9!BrgX>ky>;~7T
znBfi&Zz`@Sq28~UPa8kC6kac2X+V+O4E5WJyt&}+D2Ap&<gQ{lB?;V9lzmP6ulE)E
zq$nL!IQs+bfuj9K=npBhba?Nf;s`}9A1RJ31k7W_uElh(E1qqFhffuA>ml+?@nJ3M
zo+~ysLh^-T^Z{_giX9XPA5rY3J-C;OE=nnO;uidkK6K_<pP)-zxCU(G<NN>I651Mb
z<K|p~%weweJg|>&)!za;m}`C?Xd&Ds%Bu<I>Mfuc!Cj6*VI;SC3H*)Xf_B6EXzpto
zlVi9zBvpuGx#&2$+T3CafW&i|lr?gU>-rk~l)&YVh5B)>ff8a2iQMU1C_TY7&~!41
zv$+N?nX4Xw7bm%3+5|hrbyGAag>$8x)l}|91|-wC|5#w3<}yYBCY|e{QwL|bm)pQ)
za9=nBC6n9mCAuq%OQL0OHdjE?$Q*9@8A#@G^WQ{ao`L%?4QxL5Y8u!AE}3$p3b`(t
zxE67@cS56>JJkx%67CwE+$!ZZ&<4&~E|?<e=eXP0QxKPNzfyW>Id_x7KNZ}2Bzc}|
ze;4YN+(ViYRB@IRf4RV!KSYzNxmt?1)^LVmnq^(&@|&Si%O%u6;}Un$1u}Kq7c{ul
zb2lXrZQx#h2$4okD#10l%mrM7`74}1*=^zm=(Kw?cbkDo3ui&u0j=E0zd_o#I64Y+
zm3w<SB(HH6W58YKf<qvAgWGI43EIxF=g`6qE}a%Mo!ogPM7y|5`Y2X6_mXb%9?sPU
zuJv-YW~l4qtiOQ4n_MGJ+4{NaY82k$e(Qt50d7+|+IyRepdiv6?)^kKdY2ofMgKj{
zv>Hvi&jnmTZx3>ReMryW1MXM4218sCZQecPR`cK<adx!D^O)1owEYP;pDyfEZVXv^
z#-&%l(sQoF1LOsFl!m%tZuW1G9O0%ch5AdbBoC6WxZWhR_cix!1k|1QdGCWb^OwIz
zp$lK;L+77e`OP(eapSFNMZcdPu7tzx{IY%EJoo`hOZDXcYXIm0zUw@E^5UQCQRmHf
zC4u<xtD0fSmk*^306#vFHj({#A1BlW@Ov6zDUdh*-)fNm=5Kg-kk1jr-$T58qZyvR
z!@L(AAw0srdmI`^dF@%a7|ajR3H}iNR}b`8D4*;J6Jh)o+FlChcm4oN5&W%W=tc7V
z2O$#0o6*;Hqj~pQv?YfBk&fNO^1uBHXX5z#N_Zd7Cx$`f81HxhUL^3VmO{^PoIg!j
za*2FMD9}#ud6Ykx#D79-wPe2f1jtF=hkEuDzk-JsDg3wN0h-FM7=np3euRSjr}>84
z5J~5I=)Hc1-}EtBn89~B!C)r8jE0;n-jst#HgA0t3ORfc#VB(P{GXH)lE-hM9?Iuu
zQwB}}U!w<C$giFWjUwLt7jVVA<~NWMzH~K2O8Jpr;pka@;#Bn0IiC3ymdf~pPhq#5
zAAAh1f^Xdoh4cJ>ZcwP?)72nVyc>lKFYx8xfK>B_n-S>C8h%R}G%oVjj{~%p58H#L
zUE)iR1FeqN90ym=kEqa!2L9qgfHv}H$HTSD{O-pve}z}PMqv|w?{9F;d}KMmTKEU_
z5^Cko6vI**|6mg8uJY4HfO3u3_ruV2zQ8~)qZ_=n8!WZ+e^HKY2R}y)jZVJ(D{x)>
z2wm82zBUN@J^V@vJ@oRL5paF{VhViT<kubnXg}YVi@IC<+;^Ziz?;(M+-<(66<~LG
zyT_=z%Olesk0IaKhF0I_gWoWqa*&@%C!QbhXO^KAL;NcW?>*$J+fet2AA1}ykNN3W
zL7wniX(Q|@|EU!ep7C$edg?j9gYK&reE;XT_QU+)Pa!$NSJ5%`mwbdZ48G!Lxr4ms
z|44(Llky`opg1cT5siN?%C9LR?y7tvAAY+jcd!uMuQc<4jJq-`6m=d-%g<5hsqA?Q
z?tn6!Zfh^4!zlRct#qVM68R{{eu6gnD$_p&=cnAOfO&uAyObgkpj@yAg@MWqGGGQN
zg}2Zb2bCciqwxG4Qoct!7KfFisPm5~o8|%ZsPe~$Ai>J5^a+X(<p)hr3{|?FgJhU;
z8Lhg*l?y#l7on8=0m)O!KgYqf6lK&rIGU<VngNkC<xYwdpH@z%m`=LViJp-&%G0#k
z&QSW(9MO=eoJG^gEakcX;Ayt<c|Ls0QF65M%2i&DgWWu(!?#e(SNfF!v_Lsn0L4Nj
zHwc9y<-d<$qFDJcrEZrf|8j;xsq#A|FwZJ)orcIcWyV2pWy)1`;L4TP>H$`voJCXW
z^9JP`v@u_)JU}n|D&=|lhTsL|!7(sVt$gtmXf?_y-$U`Da{Efa)G9a818_<C(Ox)O
zr}UxWtX?^NEnI6*R@3^RQCal}3YV3Ow!+dC<s6F5G%4H80J>QjL956X<p8bUT9t+@
znrgNw<6|LuRr&2%H2a!z3`NqfD^1^lr5nn38Hl#y769o`D))nQDsuy2qD#4pZjWwd
z)@r!cqYR|f?_Op5G>G&m`za;zrqWQ2mh~$emjLXRGUyn{fN~RsEN&|=7#>6Mj<Q(}
zgLjqDlreEn*+9qq?kgu}L1s|7$`);UpgjK{K!=q2B5)6tZ3kfYk#a{ExW~$e>ENCy
zzg!2sr^<U>KzXKIG6m+JE1fA>;)QbMYxp~?983EaBg$c0h`dxj$f5kBS4yV|u=HA)
z>H}w-1pi+k>MTsk0p}v5(5%u`Xt9SSHz9y#h5LnFQQ+K#DfGa42tKs-_Y}N4(9Z{i
z)n}pLC7h-=gtxFV9mGd4q8r#(uvi8WKjB{*WBdi#1ls=#5Edo?El_ZHh|(azW(Cj=
z3Kwbn<B%}nDGCn@#{=Ng5y6U<Fh_;a0=Qtoa|uL31n>9Ih*05!@6h@%K{5&+h6`Kh
z4HF^MrNCgM@YNp>i4tZmgGjV6ouU&l!dLU?`HL0)_JzZ7LY)C##0z_A9d=AGqcp+<
zVI%_FaUpXD>JkO}P0&9f)X)klN!Z{Hk}QN~K=P#ENRP@XA=wXLDMAPbE>-xh4VKb`
z`?QsMT1fr~&ZG-3=0V|%5MTolLxzw<&qJnAF%hL%!Z&o!WeZ13P?#e;sDfgyup4<>
z;yhu9QhxFUdzzRO2m-y=3xx;N>qWxh6etu6X|&!g5i%(bQYu`hTj#70@f`}!2|kCw
zl?k<UI;vclVT8g8gYe^YfSwoL2|&{-g|mcRC0N9w*DnaSX^W&<2<t&zjZjMi&_!V`
zZF$!U6%*joC86O0B<qA9AE2&YU><>M5RSeN^Nqp>3qURljjLecir_H~dQHM#6s~F(
zwzF`iMKA=?m1z~m({!axSn(K6T@}twg6K72<qqgy7X<3r8^ZmMVWM65mp%*CA*d$6
zr%s`V_RqV7^t(Xm778d4yhljA3KP9T2Q35pgfKsd+!U12u+T5up|I~QfuU~)4hSa=
zlxufe*hR_ScZ5n>O57FRISUi_gan!r+!qFJgBuhi1oJ?U(ED`=w+9S96uvcs!XsfN
zowIu^oS~V;6G1oyx1S2>m%%*~7C3=>E*ztT`4__Yh0q%o9@zn9M6mzgN#K{l=Tji_
zO0cJ8%4?xxF=U)nQ%1o>XO&I?6E3Q=0ytOI*_)_yQ^{t*r$ef-OJVo0s<r@iM^x9R
zpzf&Z-EmL|R#kk3x)9Z|M<8J;PhTj6tN1vGM5t^ja2cucx1sSbO7*-JcB54aN>+_g
z=~U2<RZZ&wXq;-91N@FxJ*5rSV=6ld6cbb?6k<KDTK+ajqRKcB<b=vR779tKpC&*u
zS#{VP*Y~8Vi9&a$R9!SBNKwV;P?)AFS^<UAs;Pg{`R8<%Upqk0sO;$W%20XIv>{XV
z4+U(qRD1g1Q?}|~CHgBzwU>_m=Bj?B_)DH@m@;njRlT%yDNxOP19l5lv;Rb0k?O&F
zs4G@M8;^tP2U^>es-k)!a#j^dh38bxKCoaYQ@P7vqFfa~S-BM|cRHedUbV9YmMT@P
z_JFBURqlZ31=Y6OXiT+g`X?YYs=%E9y{M}H0_JN~gJk}a>L-fj)~U2XAoZ%&NE9}x
z)Re&5s48xN<YiTNILH;%89K_^WKi9^1{2MyX_V*CqWYF%EUhX}I?B+dntT)Fs_J*z
z6uhRI@d<pot{S4%)eY4Xe}J~DR*nJJp|VN>Xs610Dtziv1yjm-w`$@00P9iZ?1MAC
zs*h+L)~CAD28Eldw9_c;R~g1Hgv>3~)Ks7is61t`bXzrbF$(Xf*3JgGt2)sHw0kNE
ztp@L_N~F*qR83TXJWwU)!^0ufsvx-bP<3q~I`5Hc&3<&yV^uySMm$kn{}Pf<RUc~L
z;WO1d3G6;s<x-x(3)Nu*MaG6zg(}F5s205ew3n()e?#<@DrpG%uT}rh-RY#(gu_E;
zwdq7~F6uy<l)9>;Ex@^{S5j)?esuvwAl%hXl$GwGzOe^|p6WKr;5eXONx$>srCv{%
z-s({gpzfm<HBtV%uX;0Wd-|!rqQTr>eU)B*0qRdLLMBkXv=sV5>e_V>IjCMwq5DJX
z{#aliRtxPge?%Qk9v)R=YZwon+VUePgs8VqhkB^`_tWUZF!gdR8W^s=KOQ7P?QadR
zNcD$4lz$tg?xO^wX!WRCI1{73Cj(5Z`pZlx#;IqY0~fEJdJ7uI)UR|fpP+W6K*n+P
z8u}_gqMD<Z$qBXlMu;S-6A}QHtlmw*tCQ-nw3a=k{*2~`De4u25J^>QC<`u4J?2-+
ze>tr#l%Z$S)yb3*dPe>17gT1bL+P!TsrIE$PGzaL8ABvned<3H=BPUwz~!pVDCC%@
zu6IVS=c~=Cp;w?zq5HT{z35*UEK(2BE=aNZ(Mfn%qFzV6R;qRng`u<RO_2aIl&g=?
z2e&HJn<!<yQk^~v2CLLhmcsoD>g#z>tX6l@HyUfyQ{P41MRh*imbL1eH1oTpo<d(g
zsZ(1VfqK2#lkW8f^&oBLH>#supnh3xOM6dO)JwjEzfJ0Fijg#{KcM8v7K1u+2&Jv+
z$P8TjHuWK2H0G+>=`+Y&SI5zZif*X8hGD5)UH$?Ncc{(21=p#5pAsm$)Rp@I)2)_Q
zq7gmnd`b)NRXa=sW}kYVC!D#dZg>TSes%a|NZwM<r#bC_TKz86Z>tTvw}HK*-g+A3
zuG;%&DBe>K(wzFfnl*yVpn5_j3WwBnw0HbaeU2u8kJQ%(K_07p>1KPPwy}bxr)t+)
z`1?$~n{o-BtB=$2<b`^G=6J(uk6@S|QBS1>@=JB&Yxw(0-DGG*>1*}pBM^1cI1i%K
zS>s6aR~L<GH;Ahy_7`~JrdfCa*!wj@^aTxf&0n9vpoivl0Yp4C8)?0IK(pWjpm=HC
z@kODxCiW)!!bhW}4P9T&C3^1tH1Tz)^VdAQf^H7b^ybi<D^PR&4oZVG^J$)OP!sho
zTs)-7p=s=4O&IO*9ns8SVE(A4k|Jusnmo#s4be>B3z1Mw7^RbiX?ER*dbsAxQ}8!J
z^Zjg?h|~;XlT93@Sw|~^Xw4+b4vEox`3<;O&EN-={}QJunhQ2w6HEDp$21=n!kGlk
zK}u3St`Rfn;6%-zA+UQw<2W5$lI8_v0VHcq(ro9XCT9<tc1p90K6RC%@i9VOs>bdG
z6w)-2AwW5;362Lz*HqByrZbw+v*3M(X4edwe`abjXx*8m`H(gcvNbI+AUT>aI;NYe
zG2aJg@-!EN(87F;RVJ_tG@*3%p-}UKHDHP~RdT2oYjSp?utc+)=J2JOpbA(ztMLy<
z=bh8oP?)Ps^T%G0a?S2c)KzG<>Oc(VHN&SMQ>kg(kJeXd%;I79g2vk$UQ}zo%!m0J
zP4)tC7d6g1AyTWkm;y_eG?(b>3w4^a)=;R|+zEqg4Vv+L0NSWYrkC|)O$Q5uS2UB>
zL%m7!9c}hDYqrcmU5jQ^Kh#?dnq`zj-KP1y3NlwU+dctzP2;%$qSrMEv>$y#lSPr%
zc1^byiX9piUD!^I@4Jxf(i9G$uv_!aBskimX&ejly&BaxbixD8_+0ojr17N~|3l62
zM{wqmM!p&3u_k^V6rN}dXX&uhQ;i$VIG<@+OQHW<lXDr|3(advsvp+GQpV?q<}*sz
zd8zq@R%Nd=mtz2P%K8suNTyiN&4Eaowb?{8BHh|vjJh+{|IkOgGOYDED9p58?~TGN
z>u_55<yfz$iCCU>t04(&zIDkq$P`*1p$(!U>%xr?Ew;XIjJgu*9W=<4TEDXuXlJdj
zj)0uAULA|VGHV0f&*j$3r$ha`bx0IlN$Wc&;Y^kFTM~#=TQ_|Kg&J$~I!Io$?ih{2
zTI<=AG;zs#@e&&U>Z~;sGO4#dnuE#)>ru9VX|yh%3-gz)gJ{F?iuD9K=GSEXl?r}0
zTYpdcB`wzbBT?9DT}*4~Hfu43ovvE%rk=fKJ#QNtaou{!Hb~yEo<qUdcI)NKQP^Sa
z$-$>y>$3;w`RljtYy-?K>mBrUfC1}~T$sOY9ZMnqJJ#=A#5KHYT}b2DJ?po9(6sy3
z*H=LDfwl1%pbc5a?}z$BYoCun9$D|85Y1!jd1(-NVtw=({C#SzFhSun>+3Fbd99BQ
zz?m1;^(plI@nP#LUSLP8V=7?crF9Y|NW8K>Xo<qt)^;-i<D_jws+!nY%UPq&MSI2#
zmRz;3D30Q${Taikc)zyv9z@)=+y6q-JhZu#T<xi~r5(Ei+Wj2b;-wu^2MgZXLjfrC
z(VEcan!#6Fy9m@zYeO+Kf9;P=Pz=ys_y?dt+V3k+cu;Fk-|9G|y+K<IhqVvaz{C-)
z&sAKzquL%1hy-hQ)36ev&2E6DQ0*j2<qOl!prp=l?aEcqi_pFphGe96`ZN?qX=Cgl
z8Ew!8(wH8j%`*iXt9`E(*zwwjvFNX3+Hp(K-UO|RHt>#Xd%j1PBx?OA9GRr`>xJG)
zZ8p6<PHA6LGEb^DU@b_R_LuDtIjy~$0lVqi@dS28`-+z08QMGbu#lw<x(~^0t>KN|
zQJJHiVTQ_F?Rg3}=V|x+3ebFQpfB1~pnc;5z!Yky9RydTb*5*#Si7bXg(cdh8Wfgl
z|E9g_v)bSV06VAM8w5wowBwJWuv{CgL?bG+N9n#euboO$kxK33-+@x46&Wm1S*`UQ
z2C327c|+r(c02>$YPB5{>b#_lq2P6$b_$P9sMjuNMBxi<(lMZU*kn?y{(#MN3RQa9
ztlo#Zqc*E3btBZqlfv>5HdiQi9c?2Y5A`^k9iKrm(dI4cwG%eK*VEXXWb-90Z<1}y
z#jteJrj*|Kr)<8N120l+M$x#NYO`!L^{mZN%3D2cV@$Kzber{bX#I>$A9Z(zO)#aJ
zW!lIl12fwu<|pXo*nIdY3eVbzY3Xy$#+C9&F4=6@1F$-qfi{|d*4vb<h1~|5*<V7Y
z(PqgSICI(N_Ixz$icJ!wcQn~NqOq~r=H)Tyx7h4l4HK<4`6Y0s%_g!9+*KRftpL4d
z<3163*KNYOp?AZkEDD9~HW7Bv>#%A120nG#JfxUVmyHMJ%lQ7d%@!H3du=@Of#zy!
zb`x!Kv;B@H0sC!(wm{L{HeUzOa9i1YC`Q<>Ndy;ZJA>x(QMU7GH!<3_eHyqJ+r9tW
z=C%Eo*2(d<4`>`ou)SRblvLYc4J@SDP8dXUPuu=zjyglStz;Lj(;3@^6p+ZUW#~9U
zrtOo3@HETTiH_G7+nUpEeu=G_GwMoh1FS)+Z8sGIt;Y85a*&I*Q|OaMwYCA2I9+G^
z1|=;u*qYMPve9;n0B3I4P6>pE?Y3VP0<*)m?N^9&8f@>bhNW)X1FHbjW4lHI^2l~8
zZLUADt^5+APi<{l&?V1o|JZ`-^W3(EHo}H&ttg*)#I}XP3omWIpv;C>wsCu*?qv5f
z1wfqb{-$hD7rT$=!V6cspaZCLvx|yG;eI>yHMHK{&aj*|*FEiC(9Gn3-CHdnUUnxO
z&=_yK{iETxk6mU9G<@wAFM=gMyROf``P=<K)4D*rIY*!#WS5YIx`TEx^zD~JcAwDt
z;IQ2l24F|*&P{~mQM+-rXm7Ax(>m0J+6_{GILyw(un-y%b~9s88ENM>12748#s8r4
zxZQc0p`Wm;qQmP+c7^o5I%)T>fQF{n6;WIu)h>?m`qS(_p~=H(yVgxGm~NL$>G@~u
z(&;UbVON(04>RpPqaD>OyRKZ2Y`c}~0G4C7^$(ho<l232h0=UGLmupw*&U-fNV(lU
z+ApoJ%e994=k0oFce>KfqYQ;rcH`;3xL`Mx=6W@DcYg-TMY|bcsH?S`UxK<OyJhra
z5zTg;v@U74Q&DDYhusVtxYlWBPAix$yGPgP`RlfOe>%MBvD@7a{a(B4lu6uYcYQlx
zZrc4$Ph7v<Oa=6B*@Z4Z;eg#zN@BQe*VYWlJ9eiX;6=dbS$A2O!oLZLJ78tv2tCK|
zL<PY&SEiAk4mTzv5oAB}$z{6u%=L2m{-g)<)^4z#%p{tt9$>c8nB&Dfp^M<nT>Z{y
zlyMmI2~F)YneJ$Kn#E*L3?Q4?O&dfxjFN7eTqfo)xIE@-O5Mt5!W|(}z|@w36f&zu
zL9d9pOkWKwX5OOLdkN!?d9OiS$|Td50M0TF9?(C>+)hMg88er5*{YdeHjWx)e3SW_
z*0yf!2RER<pWQ+Ew(e~BBNTeDD%za)WLq=A9bnBUg~N;OYCuE1*&s(0`mp=Hgn}=-
zCKZx??Dmy__Ggbt(Ii6v`?Uh?4P<kJ;YAR;1tBKmDE4+fntho)fYrCLyQq!&+glWb
zNRx4(DEez)9}x|WhQDDVM@uQd@$Zu#s_^$SGs<+DHOUt;pNGZ)dUjDdke9nqPRuW*
z^ij4yuAPOXy$^0egV-^YLiwJ|7&@fk&FrN!TG@;{O%={E$H)BNHRXeBQ2k0Y?oAkd
zE&9O}4mlaQg`x=oMjqyX4m8^304~O40iCglHQDhw{D?Ej*b2OOlV=oi>yR7QLFA@<
z>^<1OCx7}0?LR-3kI)gW5xLK25OuXop@@=~r8DKC1zMh`a9*&bbSJnd%P#s6fdtDB
z7X#+F<+3;6MWW?0+P6MonMmRAB+ETC&rP=ceFK_)(lVR^*rzOmJfNOpY2^cwYB|pz
zos(hd@Ed*qBH!}58#K;Z4$T2tmF0Fs1;uriRZF1XYWai?i?vzyp8(8N%kR%a@|xu)
zJD9(2`PE90dzQz)h2(w9Md!f{TDDS%@qy*A2e={2Q>S3?p{3K?Xv8DSN3>V_*z)LT
zC_J%zhx*;{)bcL}$UL{a7XtGyEWId|eAqIdQrbo=<0yjt(z2Ys>h#L8s}CBlEjva7
z+sW!>Hi)y;4oZJ^v1;EB&ckZiG@y7|jiTV*0jsr6(DSmgeGC+DtHZBwVFImg_MtGy
zN=`4rg9fYWT9h8LYCHkEhpj%p0kn9l?qup&E1t&pB&*(w&^T@N?l8<}SpE4YT9|Lu
zKLE*VR!crW-F2&3H$mF1RAC?;R<^%_bX!gT7tQXmvZHm=b1Qv6ZXGAZX$9>0D0DQt
z_f;5bnn6Ppb~dmStyupF{64OD!lE!m@zwzJGZjDn4NC=zvc>S}oTA<t`WF-_TGZ7m
zwoQg)iz3ViT)V=Z0*-x(ov9GHs}NSf?jyy0PdGEINQ$F=;;zy|a)6sjyHZ}9tAWBN
z-kjDIFh1NO3g!B8CMnSH<Fqt<`Eylk(d+>3O`0VHa`!1wI*8jsdBg{~w?BZ}hq%30
zA$gelVI1_1a4Y8k>?pUe2719<=6MvxbIa&yKgLZy3xxzOsD|3fS$9zUA(5-4J);xc
z;ts$hapAwi{bVkahv-QzIRWGpH+K$1Qn<|&s7&Q5!qBudZV?5RPIG_I(mS2|@fFA!
z&g>}+W^x$;kj&!dT!UUV$5MCaaOJen%H?+M2g&0$v{3$IJ~x{d>jm8Sbr3D&9#d*(
z5f?~H%3^N)Z?IIt^^JpTrQD8#fH})0UO?eF?)lr$E936?p-bwxmT<JGnQL<d_6_cL
zXDIY?1*75N9Zo$T&=0u^I+!@jy*&reBi!Z&I)C$$i<t`jSKN*wRKDge`~guXet^E8
z;lsxp1I?G8OF;=ge$;e``19|a1ZV&sNJo?d`GiJv&_Q0g0X`k#fA#{{VV?g6>PPq~
z^PqQ>4>JK5%<t*|iQxqnBC-5m(clbmeBB7p;`!7sQF@FIX#z|F|4}%+IL`0A1ul_S
zzk+BI9~uEJna?{8yC->z57AGj_=j;YpTZlhL(io0as7}?<G1_+a+<$EVd*@6m=5;l
z^OHKDUc@h<vnIv-JsXe<2EP4!z*O^(DfoJkfBqR1Yx%yn!8P+mPvL$Gzby=+ZT$QM
z*uBb6p(T3{zfldeUVaBn>iYN@6ve;E7Ysn8pAQN`lWy^)G`kq!%gR7*^FPpFaEJf8
z1$uXR<}WDR;|)?HSh~-@{sdkO^1GtJJ>Z=w>3oR)d@o=g^1oBC`Z3?P3>r`P@2zkR
zp7JYaf_uhWECqSayS#xGzTj={!O>xUCA}|3_~&%Y<0U`wEWlpzX~$vVH9v*s$4<(O
zAED>0956&e#znc2^66cb2k6#yQ%);JrLVG_;sAci{+CenS0?2^GC(=wAD{&(H>{<L
zu5_nFmqSW1-DQWB6aIx4vC2Ov9u}uOMI!M^|1xmLl&kJQGC^5+7?{VE7GHo%RL+Z_
z_0I`q%w;GhDaR+l{bc3TKvbSoew7GvO3Bbjo}%pTglnlv7h3zKDW_swL|#K?6hzJ_
zi>ClILwUXzT&D6C4YXOx=~S1k9HT>z=3p-#db!HRL^ztKoJo<*eC56ibpED5Ih}T5
z3zcId;YE>BN+~AAN&{Wd66Myf;bE!rzsV>(t2EdE?UJ&X*6MZ2OWRS`p!7(DUZZm7
zTPSQ&W+))ith`NKc~=>P%_i*VGvh&ql{WiOH=;as4d!1e*Da>=H?Ncr7NYdE^2k1D
zI0=gt@YGrO=oh%}BDi+LuB+g_7(L@Acss!0e&G*_6uJx2A5rHaSWEz#r(i!0C<g>5
z`u41s&>jlTM+l_O^A%VV6#5BX%c18lm@WZyfS`N_b%sD;VHvQ4gcVm%c~F=|L8n8)
z&-Q53VWEh6=7^9O2=1t`jiN=t!sZg_hX`{pGsL!g5*?`s6Sh!3M4~X8W>F`E(O;u5
zN%-<7aLIzh9$b-=0#9GqI3+xp0`*kkaW2fJ8HC>-qD`j-OInhq3o9<bi!(wWrJ`mC
z!8IV!lS?U6EPZl}Bb+%i`A6Du_Iyva0w!9f>@bFj&M8JEKzTXMfp)=PO<NR?!l3Dw
zXl)Zb{eCj^LZ-J{06J{?2PXlRG2N#V=F6rVJ`o^OK7IZ|$ka@arzid9^tqHtl=xB2
zB}!Swzb#Gy_`7wa3+R6}(eBB%-KOwj`<_1hwI8O*nnQ&T@OS=o393#^)KtJaGqtVY
zT$tfV2zW7<#{k8f*+@BvzKl1`Mh%CVgR_8fg!y6}+8W8o=`9|`3_hZkGm~i`PGm|c
z=y!q{rZ7Vi^N5aLB{K=r0D6XL@}%}KZFFlCFonN@D`YOd1yaPk(*(U@X5$KQRZQPF
zh+JUmn}Au(Xxd<*#=v|~g32Z)k}~a@nKKl+Y+=5o0jiZbdH^Omnf?o?>tbHd0qJHU
z&q2S3IWZY6>}5{60JM*}{07{<$%J;HuAg~_{Jq6&N<iHM=F=fq7-9nG(SOK@DDd-$
zxtR*}$Be<x66{On?x)ar#YpC(hh8(uiSWXSO{8JjnUzrvqYL|e3$R_;rIdW=#*QPH
z{j7)<TkdQUtxY}Ha~No_6xjPCun(|pl+@<MPN#ROH=FYfBz@Ry8WMb2rXT+LvBwOP
zK>gW`fgk~_%nmLFviIHv7sO7cDZ@e5(GqBf*a*r}KFqRWh#X-LP#VEewtf@pf?4;a
zFcHEg&xWI+Y(3=}hOr9*;Zry}pN^76uw$OVZX~Ov(`E@Q4n^QK$nGnmz<es}b`*_C
zWB*8o#%cCLI_8$nj*3BH9vedOkbHJ51vCoSwy%I)$Qm}lZV`K()GOG1YfyKd9p?kd
zO7<qjyQ<iCcR>9Ddt(7yt7g6agF+44a0<{@S)T#uU1RlIP4WJ_&gxe|@di7O0`r}$
zxF3o=?A6bp(aTQtgnl3Uh|UGvWItF!*O#sM6z<<*_tF3}z#cP4-EG#m4s}kVkMvOR
z5dB1_zx+hY>|pRPzAAyjaM9xt*o_l?vmO?bMLtO0HHc4&9>t*Yl*oqe*%Xo0*Wgk`
z@w9=MCaR$0q6MOf*I}Yi)b<nxi$qgL!?j{ja}z{LMCtUk&{ENx7BGKK^bU;$Wg>ry
zQk084b3iIYKhPrlyr||6Kv#;EHbecgD6$4#7_N#I+XALbbkPTuw?q~Hpmb2Q@;o%2
zivFaC+$+(Z<<M|9+TaWKJ&dYpHsWa%`8Bu$MlqEz;bk<M*6H3xwG{U9G3xmST(D8b
zBlsI)G>Z-*gc{wt3zRS;W+h0tQ3UNMMHq}We+!vNqc4AhVzkj9y&__aeyvAe#2Q_o
zEa^C-=l4P4jY{{S?wFCeIo(1=6L&x_-DsQz{LM95y#=Ji$Z0lwI&X9%0_wF!6UG4Z
zict;S<JXJ=U&C&<QTsC#-Zr{Iy90NO4A#xixNEfh7T9}6ZnWyUZ)8h(Y=cJCFJbqA
z5ldO6Lq@+Yg27itp^M?gYoouPK+;M4+YyL3i|5g}>LQlxfNQSetMO296JOg1%>Cjn
zN@?&AtGA%eQ*1(q`woatMFY$WzdvLP>Mb5IfrgK`e-A2s#Q_wg@e?0K07-mQJlYu|
z!QvC=!G(xTDfd5AEF*uz#Gf6Yz7$V%0ErMUr^!qdj*UVx8o%iWlo;`LXEZPtUtxlU
zIDAhM&cur=>DcixvDKCTCH9N&&_RY&u?<al(!{%GqVlwO6$`X<@hIB*J|pJ;7h@Ig
zN`c)>@x}<CWs8kJL?`5klW1L;D_%?6O?l#$cG%4qFQ!|dK%C<NutM?OUr|^j{%9*4
zJufbO4ttg2z%+`#REeu8=zc*Q>IPCR4qppWBVI+5i;H6OW`Nd;C#=Oayd+-z0rcy|
zTbqH_ARZh86OH2f61aU?oJQN9SH#~HfNK(8pd(hz;#+g!Z;Lp684R}KcVGeCC;o`G
zUv7$5PNMz)ez7@CvTupcXQD9!;zzWDep~Ee0_?lu$)tZz?BfT!_r(W~L1a+8nQpHK
z;^<3|91@qM!0u~tuK|Tl#)Aep>TLX3G1Og*ExZ8jYJ5nCIyd7{GoZfTc%MH!^f3P1
z29gF(<G=0z`+#xoEU;e2&X=I*ZJhExKz)pV-3rdvcss3pLyeyp0Vd4Yo@Nf=#wIkQ
zj4-yKm~y0X(jstC##bmZ9c_G(lILTL_j$p?IAhmbK*t+DqxIP_V~2lWKEZhTVwgQ{
zFy2agc8SKTZ=#=17_at&Vv_ML+Jic4ykh}0&KaMjt+yKEDTQ$VhViW1C~P-gNwblc
z##d=@N;G*p8faxE_P+tF+~k=b3a^>GeF25-Cc)lNA24}G1J@pyT%kSOXC{a6f)_tG
zF<6IC>rG8-q2XnEgf_wtnNBzf^HHXUcR}W~>8fFLLV@YOlnYU2TCYUmHPehbIQqc!
zR4_n2BsRaG?vUh{t5A=Xgoxoqn&jR}U}j1T97L)l$>UIXK@$2t^t`3bQWW}0e>40C
z)?Zr2fDMpZ(n2;!>i!NKJ}AADiMqqmGP?DS;41>~J5+jqCnUq9TeT1gms<BjBvR@e
z2oIyAZZ<F&C*44A(s*f;8hXd1lW1C$C_N{Eda^X~SJb6QCtQL0Y3V#~x@pcx|6Yd5
z4C$f2QJE#(eHbRPrJ0nBkRy$v0C%p`lpgVF>1qwgMQL#@I-yP)BSl@K^mZCdT#@E}
z1<+>cGXuP6l_t#r*fr?`x=A~w1GgdKV&?rZ{B<*{F9+vt7WOMWf1YNElqc+GcA4H@
z0cP!~AcxGV--Z4Wv-Cl9Nr>5A8jQou+V9bH5dV~W9r1U04ecAPFr}ovpQ7o__H+4r
z`2Whqo-nZLjhE2<#dk9Pzj}5o%GbDN19a`lU|3l9WHqcB*7v-IOTWH527iAm*5dDm
zi{qj8duIw-y3tXBzkfWTEkeEA0j;(7dk_D25CsBaXP-O%@8~)kpu2r(vbFc{Wc+{M
zcG`D0SW<U7GutVI=E7vqm3C!@G*I+qavR{RAG5(guYZ3gi!y5hnEN3hA<W{bkO^hx
zF9muS<Gv9sO=TYF;Z-){(g(C+=4>$<b)Jc&S@0!hY!EH*sarB9;BOQ=mQvlKS@&Y#
z#jrOiN*~K!I}BTK?B2_8G?C5y8igkeZ0&6Trm!+Pr<Te#QNlqQ`wrz*X0k>sxGXlF
z_UN<O9h7;U!<JIUXdye(4+=%>_K7f2%-(Ur^(kXxw!?fmTSQ4$6|6}WB&*qfU0}C{
z9Zwl3_3RqDJsQ}}CGfnFHB@;6^fDVOhfFJbc{aE<_Ll%~SJ^yD%j{s6z6R-J3+!+y
zy4YjyK);(^{=Zo;JBq$Yc#Ey1Naz5YMOl{j*>OcEe8k@Hhr(laPcp!suv6%U8D^)B
zg<U66I=$E)N`efS3F5O7i?Aj2zYcuGOs9A3Yvu@bj}yC;&Nn)<TWFo^!rmceS2j2U
z*4)?y2_XAf9|`K**=ZEE^<YoX>eZ9g9D(`)wlfNKh=$X?j5llB3NRmb$yc!H%Wk0Y
z(cs7Ov~lgv&bEe32z&A&ybWb1WS}yPJ)48N<E&LbES+HE8m0f=OQk^T;1y*nAp6tz
z^zi;{a~<j{(_g`fRdWgB7r7H$Sl!<agf-rGQL?sgJ!;qa6##6#W*6jt-Dj8xmwtOp
z+g2OqR|E9-ZraV?C@F`+rZftQ{xNPUApX4I47KeOX2aNjGiXEGA(wK>cUDY5xf`RS
z(+vBWHI%*W&a^C|HZhB4!C(MWd=cV-%q0sr6vTWm8VX^|Z${{aa0BDri7tv@ju*p)
zDCXQ>D2-)0zW~fJ#zGE~$ixhxFq!#-=H4mHz7w!?iMd8T)G<3L5u=`2b`h2u7zw38
zH!>e>2G_#G&V>4P#@rZf>0*AQ+kb#@8-=>Zj3^g+FBrqDHpskWj#4_<YbN9qU^}y?
z#{wpbb@fJJ7Td7z|CXWXb~u^K?4~ao<uOs4;Z{C#`8fa!n7ta*6*7~igA_6OBDAWQ
zDGvuw2{V({*j3D9+C;j*jHd6ZR5R!4-Z0cKd6b-Rk?AW#X)UwD3FHzZp$S<XGn0Y>
z-OLS&PW3Q%7l7+!jP3yD9`lR>cK4aVnK1v1@u0W;b4GO?U@q)XHoS0Uf2O&-8@rK?
zmiV%f4j_K4^K#hrXYZ9kGT6X|1cQdK;h&>(L)r2skT`aB0L;g;B^1>@#xACrO#&NF
z&tWQil3tH#Y$_$G<+8uE!<jsGQzk6svk}EmFJN!c;-Q>9OkYQ?VAZrLJkLf@fU=TJ
zBYX913WdlUSVQz1&}d`_>6Lex4WWh2b+)q#l{eVS$57YKKBlQ-2irM}x=!}g6m-x4
zi~EEYJ&`=>?ywaU9=gk({{iG4yOEY&_gVipp+3k?D@O-CU?r3pHN-BUU9yL41%=oi
zv7CW2ejc;klq>#(J?aSGp0YLF@bnoQwgpXl&brfV`UPuN3vQVGk#bE(*v$1nd&yeG
zpw36Mp#ut`qHdaI#fTPeLt7F>J><-3QRX3#a#6y16t;>UQAp&jXxD!zbT$gzP7BBg
zqcIwoPc?cy9nO>(jlBfWOGY#1!~GjZuk=uSXjJ(h$gt7J>Hqf%sKW>ir8aS+DT#@n
zQua)TxSWyzy2VS50;x~DMF)`q@!3l-dJn(e42U7|Dj!Hb6?^>xpI;cnig93Hi`UVr
z#?AQLC!^3X{Nt6BZ}GDaEk;)zY5~sb@g{&-JDKLy>szu=`{!?ep}||$3izw5asr-y
zQZxQ<Urnbk9B$8mmJ_or1I=+}7SikJ0OLhT)LzW6KlFo`1j9DqA7paRp)`ysya6tp
z`DraG<C!`ZipQ9TGz6bwRxN>pDNHtP<fbx(%fMwb+Iw&&hq?a)uydJRK~T?QUXMUM
zpYeDMkpgD67knvXx-)=M#2D-$Qp~Iwp`K<s&QV0IlvzvDg0qaJ7UUc=dj;&4G1;@B
zU(W2Isa*wQM)@x1na3L;Qps3SE=(2EF$?4Z^XVv%YG(RQn5bc<(@k`dnH2&rYMFFB
z3NJB6CD5y57Pg|Wo-vbwYhb><Lcf33#=N8i{;Q1367<(K<_7_mt~1kVntX#P?S&WZ
zOn*E?ZZdPm0K1<VpvCGf#w`Gi8DREPbnrHl^B1u1FdaNl?lR^gaQB#S+9FP47q16c
z7Q3I`BROn8U8FqL3(<80p4K}Q?=4~7DL3pK`|CP1rh?r?EB-2WJwk98yOk6mxx^OG
zbhD9tya5VrtiKCHx><=ETyqi?ZI+-E|CEKa_6TRc-vJWAhGs)GlATRJQS6~&2uHJT
zd<iFG*uXtB|BPkFc|b3Y{pkYSi)ZgK5Ix4aVzk3sr~VsQInK`A1jR(wp7N_su=BN0
zNMajlo}SE3lS1+&>vs*3r`Sy=A(_G&^@2-fZ7J%Q#xA2&rqk>e9qQ8AcWGgr&F=Y$
z_Ww)R&`7|PvbmH3QpKtqP<erUOcSDN){(ZnYgjEM(O+Rxx50c9TSxih&Fqmha4qbK
zbI|KxzyAUa?PQ&3x!uJ^QZT2R<tZ%K!+yC33cc(fbgH(G4cHF7n{0X&L+d|Q@e^FU
z#V(-hH^A<vSn+N4jw#UYu%pW%dYA2<1o!W;7qd}!pZ(+*$Wyj=1a|>mQ^(=&bJjHo
zmR_&|MN@{^_aC5ege|Oq<V)7_bC6f8RRHSTMVIW*T^^!0DWqiZ7ge=GF+eo30xb*{
zO%os!BARytT#V=-#dcyv?C;P>5;=v!r)1GS+Qm8}`iXX4GDQD$L$W~hi#tf6sGlY?
z<)Yn9XiJ4?;Uqwx7hOF9$vTn08l+ytP=KmIw3YJE8V#bK=uLWAlz9b}S46!Zp|VM|
zHvo2<Mak}PrbT2H1%s`kki8IT6KTJNGgn0)QmpWr=<{13*F~|OAU8x^l)%z1N@|6A
zhsZMvV4b3)dKC7E7N)?pUeO9#Q}&6h&i+5%?gKuGs%`xKY)^Kxv=Blkbm>XxA|*h8
z&`ClsO9-JzhtLFFkR}~OI3gVcq=Nz@y{U+RfT%R-q97dv1V!F!W`B#|{XFmc{QvLg
zA@?ocIoFh(Ju_#@nK@_W<A1gJvlzF%zu8t97f9D_Z#|aO4coGBWYU|q=Ek$mTegnB
z3U_U1lZ1P=?CoXQ_ifP&WXh+u0!B;y5%ycg8?qzqEsfST@7k9blZ>)&F&@W^w!4g~
z*)jH(#-s4}><hi}LF4T`5+r9P*|++y%Gyk}w_7Z$KgE8|*aN59uNx(2ntg0P8Mned
z-+0ygGyC?fGRJoN)on867xvc6WRgSns_P|q-M(n3v3(tX{VZ$op0lZuGn1UZ-<H{@
zIInG&NoF}qpOr;_<m|aYf^(czMoVh0v*rNf`RhDq`IW+a=c%7%p$nbvEV9CjopEup
zrXM>)jW-LIIgdP(;0ou_F%n$q-0GEuu5un<DC1T;r=OGg);MeKldrwbxx~2XSnnJ%
zLzcP0IdvFU)>*G~kcnHBG49w}mvqR;HeExF_D^k3wU)JSx7cV<-QHSDChG7<9r?FQ
ztJ|`mu2+piPq!z%WVrjFD>6<0x68})1JaEbGSYV$R|*3oXUe~WE?$-|HTbtt^6#*X
zf64TtEjNw5d5mR;aS1TlvZtMqBbH8KvXrToqeh<lr&(%TkhPy~DfE}@C9^G6jB2ir
zEDwzmKF9L-fH2o`^pea!&ob*5S@e2KhHdg`x~1bNS=tWE0^<sLpXKwu!U4-I<NoW2
zC9#BL(+`$o8)Y5OSdJS{e=k}3T$Yu&ZmD)ff)6c&?6S-eervU8`M~Mc=;pGtMb;K$
zgD;${$|ZqmmiI@>a;IBL7**o4EzQozydPPny)LUf$5P99a6H#?qN04}$Cf0c&EZl@
zHskcO#xit<tod5YgXJ>AI!ia>dT_lZi}Cu%=aww>B(=rTsfE%1z*ftJpC!7_QqOoI
z`i12+;}Pm1OBv&gao930hXjALoQRd+3CqgLvb6J-F)Ji>!P2Xbe8fddn|1O9E?Fu!
zmZhw+#$=R9R$B-EV(b#uNTZH+t<`!^rd(%@GVV*(TQfup8?3ED1;2FW{FZ#RgVsl%
z$Q<XbafRgr7uf0=k5?Dkilxf9MYgMl<Rcc_DjTJ2i7mdE<lM)$-bNddrM8;|Wxi#$
z%l##|+}6C0O!A4XdL{XWD{RhpWMx*`ZWuM&Q|-44%eZOwpZ5yW?GeUl_I<y->OlFT
zGwh>{n#>RE8#l;G&9tYqkY&%ZSJ@;%Wv^(wz5Jp5#5_sOwqG{-c>l=$S7Z6yIri1Y
zRmK?Sf`-Pocb4fdpS#vsC5NOwa~3d8zMGxNMuX4KomU>qm)PzM|5PT~>3r9?L)z{1
z-!TqOd!6|*$)pdR*_BK>$#rUpeEe!xM1%zQyZoCa^^GfOu&l)ot{rc11$fQ+b55E1
zrnSTdS+Bd+$Hv3*2i7l)nu*8OPDVY`INPJ+Hu*UDe^zh2d|<8A6_O(j)@7C9hBc)v
zh~Lp@w()jk<9$X8r6vznN~SdZWPq$wv)e|0Oo?lk%FJ!QZX^qBcj=*wZJ%U3<Li+2
zs|@=VFOhi1$eOYODQ%j{TyK6{T!wqBHy-W}xSlNQpT1<FOf$ThaSi(RhDtKm7|XLr
z89mlg=PTp+$2iNwA0_&p#bVrUjklaJ9_FmJ^xG;kY_tsBEpu<R#2c-fc3V6(WZYMl
z=^sh(kY%+;_|B3|msLM$nQGiKp0jvPOX`Z{p;J;fEdAe*Z~DM8V6V*g)N(3J#*MPB
zFDCPix8~_6-#?H!pBasv<L6|SoTziaxW62D)2LB-WSP`Q*5VJ#*&?!-KP{6h%R>LM
ztXnPfKeKEzTJ(&t)~PGOQPz5yWy;ak4f|zD<E)2<$|t>N-G5dlnPIK4Mi%^mbxx?H
z)>vDnNNR_5=p{{){Fje8Vm<kRgiczYOps-qvc7vxmU!A)B24n*jMd#*=K9H6z<A#G
zi*@Q7GUcz<Q$;29n|0+uS+DEXRP$v9YlzW`;kNa?zhxC3Ti-O=V?VK$H0od{*ql#<
zDYiwMWzp~3qI%1B{J@qx+Akk5)8=@cgLK3e<7(@^rNKa1((jg=#^dV;mj1)#Gap*i
z`?B0emZ3%+%^#Kt6(l&y+Qw&o?RrCGi%zoUD=W*LY|Up}=FYSp+aa^hvKBM$oRrmX
zyr#Ioy4iSMy3jhZm!uY1{qv2CT5LV=n@qaWdZWC2{3>gmvNFeNYwbC*&Ks@UAIm3g
zvKBY4gm+lK3Y8glT7P>WpY)aWtKVfY`>iJiNgf@sPBNYh9kp%@lPOPIS47E_XRH}c
z$-;iJ7BuSK&ssAWclhV5-IvO^^VTW;WSQ}Tb&K%^=0$6$Q7d=JTEf`#FIy8j%U8Q+
z{mpo~ci)=0Tln3Y^Bp5gtW)O5d=ITnjc0v-SV#1dDW6yi50S6-r?rrAwisor_J*v?
zXxsI?GRZ>QVB=BnD%&{Y6}DZrspVwc30vU@M*g3-Ie(F9ZrVl|_jnI%t((cnr#9C?
znRJYOgYoQI*>_f#g|4#qtS70R_R{-h$|Lr#F3W0Pwl7;EQ$Di4mRS}y(b3X4Xw7u&
zzaptQj_p%rofbR#)RFJ|iTogz1m`-R8m&I(JI`Cp_K(hZqwap8^Y2HJH7lH3j0a+?
zoWEulRy#j6Do@rrTdk5AH#pn=D5=fP-&)FA=+2YIBl9iJ(&J<;wmEx7$_(3`txL$N
z?Q|BnA|JThdD3V`yvO;Ku`BO$mNd%!7fyRdneR(y_ol}C7YCe&jTf>HJIB|R_5RlR
zt?}Z;5og?Rng6)+)O?P1bsHKN>GiaqWqAorUz2I-Z?wrm8{B9jk%l>qm)sidGYW9y
zXG&&mQty_GZCc{6%+;*h8d=}OPoK&MB%OF9-#z)9v6jt?mM|(KTco@vtJQMncQV}S
z;3%22^*2Xl5pAv+*Y|CgrOBe(J^5M2cK9TtEW)?IE+5me{xylDRJkvaP928Hl&SNK
z_FbKKU6LiF$rE0=gxOkLB3(Bvl;LiNj0e%(?|Wp*H@_$=!#!$#;BITY&|vIKy|RBG
zBYG<(GxS+hTNc{4#6`)bewlufRq4O%whRv_Z!}*W+_8}i51Un9;v+5L#$)yOEO#r(
zGIm>jm&1wnp&Ytw+G?k&al?|YQkl5EeS3CKO-b+Gr}uy|Ny&}M#?~6xDJ`LPeCd?F
zeaqD9(>pz_clv-b@u@w#_Z^T{rf<)IUAxPa>h0TdyV)xxwa<VG<$N)vjsL|)$Ciz*
z98)%?LTrUH>3#b29H27Yu|(F8sk(LVou>Woe^wFo(G5!}_2vyr1$Fp_CFFnm>-D~A
zDe}Ml8IpzBREHauLaOl{ORnm^&S_mz2KG$%r4Q|!HlTDjO|A%i1JXNp@0~6QIh_wk
z?^QOoOS$NZLxxDe{yY#!swwv@*^JW)lMNZ->z2|}CX`UGl<vJ{NUF|W8tF^z)4R)m
z74M&#8kq6r$z=rt;nY6;(|oDD%1KK0x##OB&AR?cNUcDZw3PIL{mt(ptMBWbHn?Z^
zPQF2D{RhZCDf7xCKKXV72KJSNOp)4aK=%PJjF)8xLaBXv_3hp>t$*P20<o^<I?5!y
z`VRD^^zSvOqKvh;)Uvylik1*{?ye<=#i26Yvt+f)2y-ase`Jp@ZAf}|WAwjsrgN{9
z|0XQ6{8wWnOVa=AF<pA54Coe^MeV+4uGLQ2RO-$>i(A^Y{cDr-9c+9{39AuzyxB_r
z=b8;n>2K^0FU{E9h&WY?`<7$bjW;J`&yhpHA&bRfi*;CP$OCnYMcrLv4_6uMhB@@=
zzgw1CBAc{G^u@P`Z=4(zSG$()c}mU8>xk5gJ+#DI)TP<>((2t)?nr&*Bg<TmT5!Ts
zUY!_c&!CU9Sx1DZPH#A~sG)s41w#^(Yx!z6Xj)En9PP-fmkP7C2~oWtSqkf$vsw%0
z)*nS%eGV0K!kS%gS-~13mlUb)s`}cB)@D}q@RN`%E??6=1EO9lr$@YQ-5jbW9kRvF
zO7%F^`t~ln@+fPl{!=aM@laK1owd3CX(MY6my)Jq1=P7&wh&dnO;`rKY;$Y1Oje&y
zMcKk4)P)a2^DFN*cZfbT%{t$$m+xyW<q5A{vu>kW&3&~JeKO=rY8W5iRPFx59-;Rd
zW<6k0HNFTf>}j49mzeBJO7tbRQq870!c|8V>eAc1ZEa}HSud`kuU1@RUs7^ha(rNZ
zUtF!^gck9-{GfDSuhSS=Cq^}U&6P{_4YND-o|COH*}OhqQZrvd&4gs1FDhD}yTn?<
zsp{r*%Cc9<*2uO}`tsB#NR?GiTcemn{rmyzhEVlYK3i7xw3D}pYCF&CRv%84oc6!&
zD5T#!Zmn%od#>Aa>YYwl&p7pV=d8!GgulFQiSco@TdPiYts62Yckh*!+`oI*u4(<#
zIydUmIZe-U&l+h_S;L&+dYk*!x|!{Xwd*D7yY03;PM6P@oX{wyl1j0K<WdRULNll-
zF1J%3=dt~m#a6pvqMF`Zve!R6#Gx<FYn$&?847#K=mSgI+J~r9(bl}`RykXuDl*&|
zp&C2vx%3+4ZO3iOQY|c8)r)f#R(0H-jCz5}w!N8Dd`VlhTE5SkNxz+7TVRv5NKVvu
zHnLqWXg5|<ozEs)W=B8UZ!VQ_TUaiA-%y+1p)URyR#Nx*Z3i-VlZN(Atv|3=-<I7w
zr+3p+rr11QXME$hnhoRiadT`|TUbJDE!o(yzJ_s0$*SW;S2lLDXnos!+qeSCo!|4C
z?%!j3Xj55E+H<R=Cqgr+b@ybuE&0+`(4r>TLOfwHv4MRvCboGo{m-v#Qypsh!?2?I
z&O^4GwtVImFDIW-r)F%Wz=W}tnitcOnkE<@t&Sy!MCdh++KRi?{Ba@q^+l&`?HwTl
z<)~LS)|ak7J#X7!4{a*P$kY@$zUgazwoQss`gm`}z`j&gZOGxusr=g<PJODwzSpjg
zblV$v)oqI>N<S27FBqya_LXw5_77(%wS287vzj*DZP&Zxw=cD-4u$O5RpUbT)4^qp
z+#Z%yZ(rCR?p1q_I;!Y>W9_Nltk3tH^py0pWI6ZLPV1uQu3^7dM6cb|UM8bEzEyI9
zFQHMQuaVkN!WOAIj`FxvqbwmV6=@I2pl<i@gz8%d+3$sB^7$GiB-Qe@NJvVMtq>KX
zuNq-bv#Ue9JZXB-G4|7rNHf0@>NIJT(!FQRK0|zbo{FAmuavobVvOWtIgSOAiz;qu
zSh&7qqWx`K*nm3!%%<X}+N+t%N~kTRv3AsJ(L<v7Yp$=IYCmUDqo&$Rslrb!ne}g{
z+p~t~(uHxJ{Cc}>_WbtjK3|=N$+7_wl6(pAwR{z#%a^Y#WiwVEzRRA=qCU$fN6JoC
zXK{VgZhQMkRr;iTNw}<ej2slAeF=%p>ZSDVESpP3EenlM$3sKI)zO>|w<@zN)T!4#
zW#8vgrzV7!){9=WAITrc{0i!V&6ZO&O}07p*KLk;Prj!0TKifiCdh##xk*%D_3OxA
zbIs?g+ccqxiaQ+=sb9z-uY9R?<(vidB3b20kv*Yz_jLVPcIl;BbvkD^555sn<~$ix
z^>to{ntRn6qFahNmSoa*SC&rTRrS4&l6s4}js`Y0rI9U0-(6oi`&ONvN{z$#Kjg4^
zskI|9LZ#$#=2hkTIL@feeVmbM{0e6tRiv9Wqh6!0qm@Np(@%O@R6jqklu--DI_9Z8
znXD1c=pixD%{5iJy&TiWjC0h;q(-J&v#K?FT`uK4Zw*uH!`(U69hcSaDW=s)YE;YD
z)F==!g&aB6q0_D~z3_*Q60Qj2+*8XqBG*o$oRyVw)?|Uhoy9nsm+t4vr$(&t*wwt6
z))3XUpDR=?9`B0KdvB0#UuOR8&8^qk=I~i;b)pmX6WbkQY-(IqYZ+B{u`P?<d$&Au
zu_xAvNmR`mxw5M(^W-oz;s?p1d3zm&GpLf=?9uw)N2LdEbz-SEt2$aFq?o?)f}?>a
zb7ER*TK7R|b-H)y)38r!kF?IJ&<)3U{n!o1_6#a>n5%@o?oY>Khk8`hnL(|87~)jf
z{&I)Un&Xfj#E!e|%D>m^RQoN?_w-3t=MUM{s4v{%>dfXaw`%vm6{3&J<=hgkE;&4v
z^%`ZIxgBcb#?Z{FliQw8f2W+YoK<!zYi8AInk%dNBUH9S){4%&R(0{ZY_{DNr%O+%
z?40X#4@e$DInw{C?%ZGt?rIz6hvrhd-*Gstu@%&v%&rJ^<ULvZg}b3e)Zz575dBZ-
zfH=Z#oU>I*Tv!f!qOWNqJ-xNFW;Rt|Oh{S%aUW-bUG-lf`@-Qq&XRh~bmtShT9_IV
zrGB)#GpLTutxh$zj3-=0?{S5wJ9}&%{llTo3mMeOBesV6koTPLIvw3oQ+mhfkEb|`
zS}Z;l9WLjybp>r1Ro|_iOsdI6nQzBu-VnX<H0M>TTCH4eRq<(PLA}BZ=g^EQ-!o4E
zecfW`EUW4})=@_9wA7i&t|qPv%dPI%Lv!f6RyZpZ(eoU2{+(IPED=&l&vnT;BbzEz
z!x66E`oo!SSD#l5@#^EAI)Ag<>%_@vwXfB+(yo3nj**MfT#@S2lFqDpX_u>nU42sD
zkzFNvT)Whaf+3OannrPqi8l7`XLCa%)yCDb>UZYLe!V*()Tx?waLKPhhPhG-WHHXI
zNoieUGzMZdl`>GSo}$XQa$2l0W!3Ke-dt+o7dBT&*=S?;mP6Y7kKNhzv}o7SOsZue
zhgW^O)+<NTb5^;!+Ae3F0dcO}+107~?lNlsB5x*rVQbeRxB9ziNOqOHRZdS!I=gP#
zlZ_L$p61$YQ*~_Cvc_>Z<E#ZvhuV6;T0{+6<jJU>=C!)?QQckjE$YD$*@QRWbiEg@
zFM7xIlT~JKn5YjQ=^AZOx1;Q3l-|LSNzXLO<+ZAjVcu}%@9y@fcYh7brk5S#T9`pC
zpX17;Mh&t@spB(THPxc+j*5E32d+m^vLrcYx8LM?Vhi_~mqvjjWAH4}VvDP97WL5T
z$gAqq2$N0U*XdDzA9SUtH-^d~&3DLk+^*tld9&-W$6OJ4^v<_j%Pp!~9d{<>xZ#M>
zJ$GC=+>y^uQ08S<!-S;d_{Is1>*~9oxLStlarTgOx7z6nE23}85YpGCeyt;=T;A*Q
zsNK~(+4Y`TLW*YAKP?#Iwy9^8tvU3^MMB&bJ=bd?Z`su74ze-!mIyhRQC;X8mRGHR
z%kEXaNsg>)_(EH#a;)@b)ZecXl3ZAQTESV`)}l$0x>(8<u4hRJnPSc5^EFM3tJ^5f
zml$6=zD`2pc%Pgq8^<-0GoNZ!Os<pUSCTTSZ&O2@`nA-MCN5P?N|ZjLM@X_uO`2|x
zQAG>evgyC|582|%X`UDx#?|#D$0sJnJU^k8kFKe9)(eZ&^|wNLxYhXiw!F&P&Y4~B
zH6|p+YHax8>cY5?DE-{HkR18dhmAbpmU3#%F=rmV?23@+4C=h@bcGrRU*q~ZRy92?
zhm`dX>>2g9^pMt>l<T5BN<Y3o<V2o~1L}0|nV!}^F|BL&0iwR*N=QwwT7TJQ&s?ic
zT{-*LY7)a@<m(-m%aYMU>{*rHSmN%{_7L^$WKWph{(eY<Fcn+bSw=teEJRKo4J@HM
zU3!7g(76uP`@4`3{d|Vd%$5k_`#wK>1up~i+ZjW1+EmYBj!@O9f+xG$HrnZS_<XVl
zsOsUN5qiP!&@0{?@yYdkjpB^6M$Lv%FD6u6jj-%`uKc0zW>*th%fU9=CRaU`aiv$T
zRx5}8;!=z3wkY*W)38kHf}CO0aJ##NihdFjrk{!nZCXS%IOEPW>vd0vI$POOQdQU|
z2dbauxZHZbZlT$o>dp}FYk@;-B{gD(GnYDg!{*XA^bTzv@y`{VZFK05&g{lYHBD}s
zEH@KA`6rNV(Q;yQP7K}WRS%0>!_{ZXlS}>H$&p#lGCOpeJy&9_T0Xf&sFjq|FeyHY
zlnhEhKQu4&aEK~)UoNm)%yMVaS1b$tKDVQeabQ!!_l55JkIVn0_+-8F7onMLYT{XU
zVSU>E(3k@H!E2$9!`yKL)BDsMIG{<FF1q|gMh~azw?8zW-sWlOVXG?i#5HeIQTGE|
zHsj<_E3RQeO*u8!;?!KRxt`PRp6Jo{XLPR()#vAMzvWc<Yg!}p22t)Q#g(U!y@c*+
z;Lc)K-<7lFmYa#BmQ5Qas0|Te+11oE$*k&4-0>MB<rYIOj$?ea8YM-&FszO}^@Qsy
zJGigf^&_e71rB{uclQ~$+8p7{sP6P|$%V4H6B`%eZ>78cwyBiza)b8XJFXo1iXrYR
zRuxyoo=xp6>U62U!X3rcv0?6P`p#kQu`XqsD5v_`quh%vuG$Gn<~_pG(e5<4X1i-G
z7iwOf)Ra|Hcc+Kto7qS1JmvRZT`JG}VJ>~$RQHWcDrJToRkl5oGoTy|Gpj=<Lqhd^
z3*Bv8YGQq7s5+HNZj~1H^1AdqpSUMj)L*$g#q{MX+->rx4Mn_F_1gR0p&|O%BW_0q
zebZU@Cm~sr`=|6C(5rj8af#8ifA>E9yQdG;+x_BRll}P>`9D{hnr~JXxzx<}%>AKy
z_DsIj(`W8`7WJia#3)rXER&wk>e(kvIHXX$bOcs8ot|U=+BxL-(j-y;&FQhbRnIxL
z-1@Cdo(yuZ9ODjABOW<iN>#MxQ&Y}`g{e%l<=(G)ZqGrx9-H6ulPz#p`u=`z9^<Ot
zqYo|YIWApH<hPgA8<z0&%n&$=y>u9PUbN+x-4@xEwUC^_pY{j~RZ~yfGV3d<d3NT^
zXsotzVH-ScbZPBb5yq`(bl_HWLJ>JtE*fjiuIhI2RIgj6`2eX!DwCShzh|ETWoq|H
z9oWmP%uH;VT(8W4zA33`zVx(|US(v-rD~=0@9dL1%7H!8d`W$}qz_K%pH`-JTBm_s
zHFayKBZt1Ai|6YQm1&GUQlHz$Q{1ECzLvX=s9~Pbmart_rbshZQ10s&m9pkm>u<~T
z<F~^--{n+;K9{?&Z<Qy_sUrJY^XdunJx#6Zou6FURE;UN0;<WhP`AElq34H4eb(om
z?G{TVWf|eksZKs~XVgb*_55m6iz<gis-u-d?CMTmXHK=Ea!5vR;6fqrnbF35LoU_v
znN@B8cY3N>^w`~=UXg05&*RWfo$#E^rlt;a=g>FZ@|3oydLz6Q)St@X*6-c+oVKX1
z4!ZKHT_fZqbLp<<FN@01)m}k=bl)@19ym)jsOv4Mzw?JDn@v?6=ZIG7s@1FS{L|Cf
zrf%JnlTM9io_9i2{^8!D`ZZTrNxNLfSt8`6pre&tVe0Bvwyb(YSXhl5>I1(cn?Aa5
zSW}PsVW?cBjM(P2yUfB`zPVaBR!+M4W5Q~b%u+8Y-q#|oVe|N?N`bqz=6c8WVHL|L
ziz_s%zF<<=CtgRLq?kla9XlT)wG$tOO}45^JwjsiT=T-@N}}c<Yoxw&UD$a?u9q(g
z%(@(3)A+`<jSGXho5BV-LVZT9pxo8Ps5>_u5qh<4Vc~K@X)PPP+3~OsY--MKsY3Cd
z2pgV79Xn}%BXC+>bS*3)RBb(L%cRb}DOWvZVmu*w=KEnIY$|G+Gq3*n!>~GT^=Um@
z#H{-vZsqwrEUTJ!!{N}&TD%9O_M?b5c5{^XQ|IgPN%4s-;%i51i44U&ABufGRQCB$
zx#vUW^;|{0#dE83_dPlE_O-lcY^u=_cV&HWUGEK#!`v%W+#hoGxfAYoI?I|ni{2^8
zJ1(OdxY(Xa?HKO}Q91U@iEV#Fx#!rG)#24^rF!eQLlSxqNKfgVnx-%7<*n~gYi>ww
zQud+VP<c@%hr5_wYq-~8S3j+=7SM-|@b0h~6?4V)q|x5a4z)C+yMS!`3qwP)s!YGj
z&0EF^-bwb*`2PL-^si;qDSb4>JKK}BY0E^Tc1<pm0%yFKa?OjW1|NAhs<Judpn2qx
zCsYl}E7woYKJq@wWS)syru0Z_-dAOwBlnK}P<yEQ<+wXAq?cLk&6rIev)5bAlCjRf
z-l@iujFg^ciPX>S^DeTesHyfM%Cg%Vp}I^A$*C?_<*QHoQVzm9zVu$QXEDxniD~J9
z1ML8#(pjJXjkjQUuF5g7rD7^XM;D8Vi78#SbWD^y;E0W`7!#{$`suS?r^TDys6pi~
ztA6a9cb_FsreMIdoF*;pwC6E3{em~Y6!6b3c+2Fk`qGp(ZQ{SulXcrgug~fq|F8H|
zE!#^Gi}v!8tlC>IjkjrQUrO6Gd0O?tpF_(d4|xCib81arO#7wwURs*I@E4+Odnp~N
z-FzwS*7BNl%fVSZT8o#`VcPhY(q2v4?!54qL6aA?pa022xQtq1srdirFO$~prF3RZ
znz+31mqnAN$uIncYw}9p3x8R)%JN|3pT7uAUe0{sFPkP$NrQj#`C6oQ@1KCAvum+Z
zwf@gv4ow<czVMe*lV|!b{N>WFy_C+aNt5#z{_<#PFQxNpi=L;A&)4#4=bs0Rbd)Bo
z2VeNhulZg|7trLj>KFbBYNuaH7t$g_UKp(v*5sAh7ygR;Gi>Z^Hf_p30W&>azkJ1;
zV)aXhmYT8gjkU|771yNk%nRuf+RB&GB{gYY@WS{~+ToYdrL_yBGnmUOquqEZ9j!@s
z2j={N@i8^EFnK;?tU#DKL#!rUr9A&L%ALG`Wsa8@mSqLYX>a^%d=vG<Rc`@nq0Z{z
zRd4O6nAA=w6;e7^NQsWFSScnpCAwT}#Y(BMspV5+I>lC~P*HDl&ATqdFGtva*Yjz?
zlg$ekWM=J#u{y@y<6aQRCikMi5y84x)8yM|R(W03YZzs$VL&6(jdV`KJepR(FrTIw
z+r^q!o}iU72BI|iLIJB_O-#VX*bY<iO_ZL4%;mg|^8S&T-i3$oG(ItvebObFZmd97
zl;5#5(@oGgWEkUTp}aX~rj35bjJP}pH<j1;OyxyFQ~CWQ)50k4mYHdJf7VnwvDU19
zSwL$7T~L}am=hesYbZ_8&A2p)HMQFUW<}{i%#25&w0kzwB{3G|)eti-FCb}ttE_;$
z-(UuM;!qrmGjJiU!L7I-zsE}`Z>^ilm4=0;(m#r61Qw8np=O{w0eSn_OgF+bl=n`|
zxV-$PStB*=ZPM==Mrhh(((fC}c}m`3GpAo{m|4@-kp9##qo(a3z1QAQ0<y~<Ch(o1
zG=n)yT3&I{q;Z&blk`19IsQB)Esq*C<3Hn|Va=&tzwfQ@Y-J2bs&{4BU&|ae4m%Q)
zz1}P(`DI@-(ovcw1;VtjVF67mL%I^yFf6EPW+5n~X-UL=*bV#PP(xXm?ADsKh%m+&
zD5{x9J?m@onAJ!ZlN>TEu4x||MoA7Cme91%3`<H55&zOqil|w7N^9B=Mq1YLEaR`@
zEyHL{``s``{xb?gtgME|7$~c0nGL0k=QNbYLs5nmG_AOyyxA#lifC5(+Vbj|X05Dg
zwG3a^v_^(<OpsS`%oUY)jy0>ia@5tZs;2cbtfpzk`?uEWnl{?7hNew5G)mV@V<1k`
z78uslG-*PvS!-$9TEp6!_PJrartLPA>7{{*X04-X$4EQ0KwS0;bG+<Mrm`EF=0Vv?
zW?C}W)Yz0}>5?yN27(8+IMQ{o5eBzyYtq4OoJP6_2DkNK(r@D^9FJ3t-N5)pGYQPW
zMYtTzZ6C$97q<}Kh2}mW@q?s~;Ry`x3ztb>!`sGgXso~k0)L|Pb#2CjM_w;!X-;Ft
zb6`G{raNX_T92B>U`4Eo<~}2zmq5CSpMmDs7Nt*2b3x`#Bs26PJphMdaQ-o*C*pKe
zI1iWL3iPjIU=tdbn?{c8!Qi>%FzMrX3eTf7@-XMSj(719K1Ca+hR}e1Eh7PG&226q
z7v{&JSPG@50dqR(iOw{5vWh3&0GnY;l)hrj=~J=0sce6FQP~_Z5akU-Gd&XJr8+Y`
z8E4>ZT!2e)6>dOjc4N+OTzDHfyAKZ-8s+~8fgkV;Uc_JVCf>)#_zWGkzz29RGe%+_
zl=rmF6_KvJ0_DF9f$~@drCp;rVO^Bh-ORMKzc6i$!Lze8$ui^8q}Q|`N;@7i{Wgxm
z@zU*yIbte-nK%a*p){;9rwg9eKO?;bcj1>P?PtyDkKqYCi<j}5bbDn^C@=My%Db$l
z!RrAFXHjWzXU4r4j?xI<jOW9`SOR0PB38v(m>|tQ%mp;T=GYcfuq*aL>BYvJZzu+r
zGluj;oQ?|T;S%((U|<~@cVkxBDW%&_(>=H!gV!O)NuR>=cm=QHU3`SW>k?^}Yb@Wd
zNuzD^gQU5Fsl3Q*nhWz|Q7naJQCdQn(^p4n?q#MMU^8rq@)EH*UK+uQvi-Xg=z{}s
z7>>koI2mW)Y+Qg#aTRVr9e3b9L!<m3AaDeKKxtxPuIWYm6>p-nWj4plTiK@1&>`1)
z#wPS&W{gB>m}ZVID4OU0Vg$;dywGY+AniI#<52oAG}DbR30tENjT>xZ1$tmV9E@+{
zC~5X+PAF~vO{d~alzxQGxN(PWEO0rl!Ow6D?!qteARfaLcor{9vnO-G*9hFk2lyvi
z<ciu@0ci|w>cw!B#yMs@A4=O9GcAqTO=GYkR>fNK+POJ_^yh8b1f>y@nU*%MrYYDJ
zd!f8WZjP6h*`~qeN#6lxT3T|LPDh3F(7%KM>0rQ|a2;;KZMX;b<6)H6xaNGP@I1;(
z?`Hfu-o;1wG@xIz$sLE0wbChtX-14d>0iZ+OUDwXMX?l?MQKrMj+ahDP2;fvHp7-E
z{U^$Fvi(yDbVq4SWiDVK4nyg7!Hkc?$tdl+%=m1Sewoa)v<)>~g&R<sj+$|K**;MI
z_YsgLZsv$1_yeB7i})+v#QXRdpP?f(usnIu-CS;FjKn;mS^f(WD2CG8hdG1v#%)>!
z<FGDDUvuX8By5d7ly0xg@jb8~4#u~QW<SQZA4On1N>d3lJ`?Alw3aaA%W(~UhFfqK
zN}FAC`hzH)iJ56>c5Qk#l=6R>fOMv1j<}5v@K3ZzV*>LyfYOH4Oow9*%!h?hS|OU#
zNn0?}ida>;9WVpZJkL}bD4I%7(x%cB+_WvGp!7{^#(Uua9E!o^N-I%wx`{X)rFDZD
z_s?TMTCSJ@Ift13-`q?ZIrD#bFX`9*eKXmG73hWOI1Jy#@i+|?&c~&=8qIoxC{5c+
zdXK4W|E~!g!5=Yr)A%##>v#_zqsE<0@Ln+k=?Kh?1<|Zeh|)Ck9?>}eS7JnUtb=C7
zf{d4LWz0<yyf^Gbx;ys8!T1ga?+K-w33L7#_z^A=&GK(nILHSD?**l4nmNM`lnznM
z^g)!yS!OzT4|sv}uXqa|pfmwCrw`uyxw&D<EZr`fBZ3u?`4}OM{LFapp06C~Dp(T}
zP&(@~rw`uiNdspyorXOzSZ^uaiJ9X^O1BT@fHYb%or<&Y|F$&zkLQ!mH$S*I{!eH8
z_jJL^>>Mmdwx+q<q9_$(W;$3rrGCmx2kQT#G_5{?W@y$CO58{K|Fl^Cdj<cSN-4iq
zkPj$^QblL3Sw*ad@hJ77=J@~N2RvWCQQP&O2Pnz^I7ZaP|Haxaa|MExU2~1kGs^!G
zK6oW=z|V0Peuanedpv`e@D4u0zwy7yF|+(fGQs~_Md5#D-T!^gy|5yI^8erL9M891
zaNh`SL#dTDv$87I#s-*(!E;MT(p|AP4wU1MxuD?$M&SgUjvwLzT!z7l$&IA9;a)s|
zNAU!n!z=Rn<_g@v`xtokBahQKbcSF?l!me9e0i`C1}h+ANms@iSQi_kKUneDjzB8D
ziT!X01}hxLlAesxxstg;b8s;RD;n36)^TS*zxE{o=~=*BK(K;Qx&t%QFYGL4`rrG?
z|JV57PW@j`C;9)X_x>Ji;{Jw4`5#JP1dhWg_|gF*>i_@o!pU;IqFMg463B%GFj(yV
zr-$U=^MN+ZpMu@64-Ue&<@3#LI-0;ld>?1yLR^k(aT9LGefSL?!;^R(f5Dr<^8Y)5
zKhb<R6eTyM?1Y&x67ynVlwN_%FH#nbX8gtxGY+M(xS4K(EwFvCICUn_1EupqbB16&
z{|M6Ka0<@Exfrb9UrBlcn$M7Ag?5oPpCL)wAFS8^o)Ks85?;eQ7_86#o3w)~r7#S~
zoEWUee~ok*tPs$zRV7dxgZ1}`q=V0%JCg2-y)jsAFWu&wIW`I>;B@>DgVpuR%(RsM
zHH_GZ+faHZF&Ajo(@RzzC4B<V;T61r!Rq-Zq%F3<azZd8W-~O(f3RM@5F<+9zn_NJ
zAReramwr#o6>N^ii#k?WUMk8j#+m70HT)3Lel#AQo8^Bpfe$cP{l1vA^uu8;Xg%sE
zKPG3!gVpZFn?P1sf#WD0>znC|col=S?GJ<X|4$hqJ@J?`crXhFtJ$MS7sb*Td^#^Z
zFq-oRtJmw3ZicPUhh5}nH_aJ>)#~z_NoIN&nvd`08%duuW?X*C#xz)+E<coErkCPs
z{0yb*6mxvA7X53|NASmBz5Q7NKVz`^+<crbEAW`O(ahK?X%}X|V6D0I#bk~zh{Z7m
zD`Bv<++T-4BTUA&*a?HR<i^Wa#tIBZ>Db3ikHJY8tR4S|^dkHO*9G)zn+XJ~#lIkZ
z5WmAycmad8;YLTq#tJ>aztAS9IU_EeGnxi#!KHgnGo8;=w!iUum@%RBPHb8ZgSFq%
zNvs)9K<OONOt(bo71~S(YrTyQF^%O7K<QP<OpiqA5!p<emEA`9pG9CEevGT|Qw-K}
z?<Tz;zr`O=`l&EK;4=P(ckvH=CYt46e(A)VAy}&|U3r>m>G;Z2I@>iZhSJNsnGV)w
zS0f#d4KWF&gIII=U?sNvvY46fBi)Xe1A_>>jq<ayW;|GXZS<;aWa(^Nh|6&;1}m+%
zlir8l;4wUj=UtS4`SlX>18(B)_$OMaQVmv8XCiI9*=MYn{J4W@VJwNk%IVih$6-Be
z;%7j9!^K=cpjKMbI+N~!(j&JyekhK>U}d!Q0d0<-iF0uY8t(=gD;lhX{+zUb7X#8i
zp*ex^lAtl+_ZX~vzC`*O-oZ!sHwG)6jdul&<%DBS%#X&qf->H(1uL7S!$5O}s#qHv
zU?K)9nWfJtbNa3*T{)U*>Bh@+I0oyMCy<_w()+DUC)<Ak0r`0|bH-q$@<!6za4#M}
z>9ot7K3JK2j`S70f%owV2J4VR+%msW{-wulb3yWho~H7%T&9IESa}>vS~_ku$IDM#
znAS!4X(TfptTS#$Iu)fCU2}Xtl%Apj<v&<iJeCoY@dK3K0y1Y@j4N<G>bMi7%W89a
z`Q16w<9He`qI6;!DF3$!JjADH_XHLoouHcw%7QsC3gxF6&GFJBylHuS1EmXbGhQF1
zms&I3N`7|E9Pkn7g1s;uhvB<89;c!77H2L;x<)dU{*q0lTU1l|#dOoHxCg(MpWQG=
zNT;l(((ALSbXR8jGhWAg_!y0MagAc;!VDOJxv?M?#~AciVxT(K!A6*jZLt$}$G$ii
z-@!3B31{F(xG11s`-H$c+>AT$3p|M5;VHa;zv3-?fPbM)Zg-8Ga${yw+5XuH<ijFZ
z3d>;?tceNO6kB2kOv9cy0N=uqhDP~+kHA!%h4b)ZT!o+F7Tk^d@mu@>f5OZ78{QSo
z^Zy?No}n{CAgjEX6?0($EQZlo5vyT5HpC=sgDDv(|J?}m!9n;oj>d`jKF-F4xE$Bw
zCfttu@Ebgqf%1Qnz<K-yZ{qLxCmOHl8aq=cX2M9!i-oZymc`dG&d)$SY=SMYJ$A+(
z*dK@D2poq~a3;>hCAbp(8yNT;ci~rf7{A9ecnPoJ9ejj;qa#xwr@}BCa|ZNl`3by+
za`|p%tsLM?|6Sh~tj{aR_+nTFgHJfBkdDK;*a!oaRkHnqmBc<qq+t*2hl5dSt;`i0
zh2wE52CM7lkY0q#aSfUeB#rXFg}^TS5)Wdq7AshJe3tlSyoPu15&n%1s%pY89E}&9
z1K0mdD8=9WX0Nb5kn4XwIGDAgNl(Q8z4}1P|1W&dO?+kbfx-H}=M{o%n^#pI=>K<x
z;47{Vl<R-0$*2%~#r1)*{a>ySe8u&F=JmfVQ0&YK!KhbTA83|;KPwPyP4f!t1G)ZZ
z1*AgIJOI7A`asJ6KNW(36?kR!fx-H}=M{p~^S!G2K>xoh1YdD|pj`h`Uq^-DE3OZe
z?f-Ix;47{VG_U`uj|;y2`YP)K1K0mAR0vw-0Q3s$0|Vv%g$hBl{J*;TK+69=6@r2C
z|H|qEgY|#UD+H-VdsX#;{(n~pzT)~ox&EhGj0(Y5TpuXg|K$q7S6m-xl>e711SS0{
z>jTa5|6+xpQT|_HePE#czfd7)mj72*A4vKCr$R7L{$E*rV6gu0d4-_d_8ObuRn-Uj
z|6L*Yit7XY+P^9UUvYh)Z2y-l1YdD|pi%x`st}a)tE>++%m0fNg2vAG3hM&{<^P2W
zL38hab@hRi|9>h31I6!^)dvRa|DIO}Qf>CC>I41%t`L01^?`ovUloG?Q6E@_dcg`<
z6>DPyOvKjM5xZh<9EihBW&4jJFaf9IhqwTj;TqhC+i)))z@vBq&*2rkVQ7^9`vjh#
zMXEfFVi<xMF&pN=LRbQ0u`<@cy4V<-V>{6-|EUDt#C|vg{WumU;|Dkg7vl<Ck2>ze
zFY!=j>i>@uIE@$aD&EG2_!R9~0y*WuESLkMuqc+s^7uv;%6}~a^|2YYLLYX)UYL%<
z@Le2_(@^1jT#Bpx419)LaSwitNAO2Hi$CLayoZm`=o8D>mt2?uBha6lfr3~ZW3Uod
z$2!;uld&y!!tU4?2je?9CZJ!NL|_Jfgp2SKT!))+2Y!JE@jE<)7w}iSg%3<+`~OA2
zCe_|XR=F`VX2*P31WRE#tb#Q$0h?k=?0{*8M)~haU;w^_Bk?_)inDMYevGT|Q`~~P
zaX)^GKZs`e|B1k5{0;BoANUNN5rLfYVphzB1+W-KV@0fn@e!2&h6IwZ4W?i>?1O{w
zZ5)jg@qL_)3voHF#Z3{E|Lp|!;Wu~;PvUv}1#jZ-_$OMk1#&19Ghrm=#ln6DN@7`j
z9pkVbHo+Fy9y?<X?2kin1dhWg=%2~JTwH=HaRYviyYMSKjNjuKyoA^A4nD%a1Io|7
z$@}+4u?xd+%!&E&H7tV_uqxKZ2AGJgu_JcH-lnqs2ND>Lqi_OF#}9D<F2gmr5x3!9
zJb*{>1fDZA%KsGtH}F0_K}+^P4uxPw%!YZe5SGALtc*3VE;bg;^52|5J50qlu^$dW
zKaR!8_yNwr#kd03qmDbXQ~tjsa0rj%X}pM6@isohr)bX+$SDtI!5kQcMX_`a%71wR
zZ(uE~kIk?Z`mhW3!gL&l@8Wozh6?BV8CZ&|@iW|td+=*Kf<NL}{28y~J$#HtFL&nk
z0Qxg95P`X|AQs0Mtc2CE4mQGMY>S<+JNCuF0sY!L1jgVboPi(VBK!o`;bz={U*JLf
z4o~3){MA&p|1AO!@GrDUa~Sh_05fBD%!fs=6qds(SQCw($~KnQ6k8e^<-Y@gH0+53
z@GTsP@8MLOh4b)ZT!o+F7Tk^dMYH^WOW+6m2`}Ssco+Y`XXwlw_-0<rin*`=7Q<+)
zn49unjX*p$#3XEkDcBAB;2?Y(N8?0%A7|r2T%Mcqzm~uz+>ZP38$5<5@jU*5H}QA;
z6ODc)jcp%_nK07NKwd12C9y2Nj&WEIn_vrUkDajx_Q#<(0{!C{n1VBLE-t~9xB)-M
zUHBCq#_#bAUczg5C!k+@MBs09<PBt17=~j`%#W{O8LWU+u{JiqL~M;6O=bIcCD0oO
z;&2>=6L30yhzoETuECAC4fo;!JZk8do#F(6b9e=B;C+08mVAL63c-w+4f9|jEP=6D
z8Ec4U`L9c$F*e6`n2K*=KOBO79E+3j1Du14aRsi=NBP$Y?8Gne5FW?VcoDDSZG4DN
z(Jr}b6gv-Q!5kPB<qu3ylt5`Lk8fZttdGsG75cCX_QG@=hVSBdoaSdh;e1?*tMN13
zihJ;DJc2*sS^OEV<2`(g^878311`*f5tthbVsVVYN?0B1U?WV%w%7@~2lQ)w2@J+}
za12hu8Tb({!cTA=ZpIz>1s=rj@RX@+{|f|u#as9Q|3X`VKu)<aGiJwpSOiO9Ijn*;
zF~QK-{!IzA#15E-J#hfOg(LAjoQkt>9)66g@Kf9(n&p2tf&KU`{(wK>W&92A;ve`7
zodp9q<;AR+3kzVef|UPg0u`|u#$!WF!Zw(K-LMZ1!nbiWPQ>?dc0tPjLITTiEpEc?
zxDUU<V|WtJ<1cs<f5$)3S}2f1p?(H3VI=0o!dMc^;_DcP^{@%H!1mY~dtiU`4`pBk
zj>9Q96X)U*T!|a-bKHer;bHt9&)}tie(f58JNO9yMn~a5R)t|W=EVH?8kWHdSQTqy
z157lP?cbU}N9>BdaUc%IQ8)po<A=Bam*E=Rh}&?lp;7)15IBk_@El&j8+ad|pruG4
zhe9wTX2U#K2uonBXqNxV1ZrSiY>dsZ9j4-&*bj%GAIIWk`~c_RVx#|OtK`560_#!7
zo%kgl!sB=vFXC0ajSulD+KUEq%7a;oQvP!gh{B>+8q4DwSPSc8Gi-%E?1H^89f#q&
zeg?+lG*mbrm*Q&t47cJQ{2Gtok9Zb;#_Q<6$G~IMUJGQA3o~E@=Ej0p9AmH&R>wNn
z2$QjGK)=?BKzHnmgYg|4gOhLueuRtg6I_RzaR+{Z2Tf)Be@EaHUcg`R7Cykg&{iyv
zQ*O+R*)bm$!BSWbs~8&Pzb1hMY>F+h1Eyh5lpilNOV3+465qqAI1A_D$GA!~%m1eY
zw%~5ukKf`C_!C~n-|#N}fzQxcJg}l(%!;{+Q~nDOD2CBk5vyT5HpC=sgDKbz``{pa
z8%N{B;*|gQ3CzZYxE$BwCfttu@EbgaC-FS~f;aJZ{L{~X(X+jABn-t&7>RkYFqXu!
z_&Ua6J#2z4uswE0e-8%w<4_!d<8TVj#JRWxSK<cz9CzVYco@GA=-18=xP;g64nD%a
z(NQvxQ(+j6IWa%JhGnn<R>j(;vi%znNW|9I5xZh<9Eihl6i&eD_#rO9Ww-`68XDz)
z8-cxe0FUAcJcn2C2HwXfXekxQp%Bc7*)R_l63y~of<P=*#u```8)I{9hpG4`_QN6Q
z$FVpWKPW}{pF?0VuE6!E<4*h%58-h<jTiAM-o}Uc6z!!c|DMu;EX#s9Fba!eX)KR#
zU@feV&9D{vunYFWbUy>b@Le2_(@^1jT#BplGu(=M@M}DRKjK;R|IEO3yoZm`_`wh3
zz~sUV7=gL5AQs0Mtc2CE4mJwt*OCde#ZK5A`{H1H2gl$foPi(VBK!o`;bz=nD%<}H
z0tfLsJcSqVSG<J}@GrDQ2Xe}dnK3)&!y;J9&?x`q2votEn1D^OC3e6x?1=;LEgXsO
z;Z&T3^F*`!e@tK%eu`UgH}1!8@dx|~FXL}`7yrO#=!^;ElsAU*pOru^EP%x@8Y^No
zjK_wUgl#YdyI~(3gm1@C{zns-i0|WUT!_nYEpEc?xDUU<V|WtJ<1cvA&%p2aCt70z
zSrm$yFcR}(VJwMd@pX*Dde{V8puar>ov{b@$Dud^$Ke#5iF0uYuEY)aIqt%*0{XSX
z1ir^JcnPoJ9ejj;qoZsfr@}BCb7Fpc4a;B!Q`!Di3Dm|0n24>hBX-5!I1q>9D4c-P
z@k3mI%M6Y3zlOj@+=hGc03O8?cn+`N4ZM#}&{8gtLm`+Evx#Q;&qJUPmcUr7j5V+>
zHpb@I4pZ?>?1w|pk7LVG{wEXo0O#OhT!HIR$DQ~k9>U{z8ZY8iyp0dbQU0G2u$K>H
zl?St64vfO0SQ^XY8(0hLV>4`pKJ4OWpckg&Fnkxs<1|z_AD7~4{0z6^9{d`Qp#Mh(
z&f?E_9q-{|)G7pW$b}g&0&`<QERHc)39AS6Yjp@T!enfVov=Ih#liRvj=@Pd13$t=
z_zA8vmF>Tozz+NZ58`)t3NPTVcncrkUudfs$SF5w#_X8S&?x^!2$aHdSOsfh0yf2#
z*a6e9Cl0{3a3sEmQ$@4<&mu4nKgLz~DQ>~txF5g8AMhu<jKASs`~#m=r2IQ81+vPE
zSuqzDz+xDU6|ow|V?#{BHkg9luumn*{~!Wy<7k|S@8fJ-h|6&;Zo=)j55K`<coNV1
z8TbWn;_vt;8b3H^)(>DNjKsWH7)xSVd>!Mk9{QUw&;r|IXY7IfaVU<!aX1BM;#^#U
zD{%vU9?-AtBJdR+#_#bAUczg52Or_z=y*MlQ(+j6IWa%JW-8mi41o$*6>DPyOvKjM
z5xZh<9Eihl6i&eD_@SXu{udBfhHG#mZo|EJ0FUAcJcn2C2HwXfXsHs&p%Bq5{}~Bn
z!#r3BOJFQk#u```8)I{9hpG4`_QN4nDF1!}V{tNmfOBv$uE6!E<4*h%58-h<jTiB1
z70Ul@0uS*i+TRFdl?St64vfO0SQ^XY8(0hLV>4{!XTXPDuotG|Fnkxs<1|z_AD7~4
z{0z6^9`t|Bz!Cfr&*IN`9q-{|G=31<tRKJ(7=gL5AQs1%fPSqKf$CTX8(}iG#ZK5A
z`{H1H2gl$foPi(VB2(G^pAcAwn{fwzfd}zBJcSqVSG<J}@GrDg3*?j=GaDM^KRbbZ
zSOiO9Ijn*;F#(%mOYDGY*b@ifTR2iQ%l~@>rs6D|haclA{1ms~ZrqRG;t%)}UdG?>
zZZ*pP9|WGEvw9$_yqFbpVF4_L(O40yVLUd(By58z)%}4F>PDas4#Kx_G)~0#aW*c*
z<+v6%;db1I-{3Jn11Ir3{(?90cl;BrH3BOhikUDH^I~BviDmJ1^v5w!51U{MY>%C>
z2lmIII0DDv6r723aS5&r=+`z7_#AiPS9ln|$1`{dui+hhgny$WE|61U7>+qj{hF4a
zz-w3rD_~WujSVmnTVqG;ioJ0l4#!bA!O$Ni9S{)s5EtMwT!R~N8}7vecoa|IIlO{5
z@IF2f&GK)l8OWj#%!t`A4;I1_7>kv$2G+&K*c{toD!y5h^52iZ5cK0%oQxmf99)bm
za6Rg{6TiemcpOjHl<jYvy)F{CinsA0K1F-2!1Nx>f;lh>i(+Xkk8fZtG=G2FDl5>8
zKr8fN7wm=UI1Jy#@i+|?&c~&=8b3q-RtEOq*LVbf#IyJ_UdMa*7`57g9CBd>jKJJj
zFrZ&6P9O#=VRfv7jW8M8Vkhj5eQ_|pgJW<K&M=kj{}F*j_zAAV&A0=<z=QZ5p27?G
zE8fBf_!rvZC8vz??=}X+%$ObXVG%5a<**9Y!~|@LEwKZpVNV<&n&tm30weJ~oQkt>
z9)66g@KfA^yKz5$i$CB`csZW({~Lk3_y;~iXPrO}c`+;I!U9+fqp>1Z!+30nNp&dy
zZ3v`bH|&Fh@NFE86Y+hVjSF!(uEkBb9ryVe_y&*RNj#6g;7$A;|3quuKn{gsCXB?q
zSQty9zbpf<V;t7QCfEYoV`uDv{c$Lcz;QSQXX4y|er*YXmAC;v$6fdp9>(wS3|_)(
zcn2Th-{`0p$f+<>+5X`Ka$<gb4a;B!tcta<0VZN=?1){lHx9(%hDP}xMPLF>#}9D<
zF2gmr5x3!9Jb*{>1fIhyctbSH|9t{a(2@|yq7cl8*)R_l!V(yZm9Yla#m3ki+a*x`
zQwh9@{cs5SaV$>84{#1H#ud08b=-+x;-Lh}|8WAR@giQu+xQTlqP>0~r#zSib6^w}
z#nM<F-|#a~3+rPuY=u7Tg1s;uhvB<89;czg`M4DQs~PwVx8ffB8js+Qcou)g>v#_z
zqt+mhLoUpK5dr;LZUP0dIL2Tltd4cC5hi0>?1bI1FAm0caEz&J|49U9;77O!Kf!gl
z8F%0pco4tCQ+NS?#asBm&?x_Z5wJB3WR)8;V|L7kMX(f>!zx%46R;_^#15Dyn&rPI
zfdTjyj>PwHD$c@r_%W`+PjL(G#{Kv${?L%}{}X}B_#58EKkykk8wGO8i&-%j7QkW{
zjTNyP#y6t;HzbgRZ7>D9VILfXZ{uj3i0|WUT!_nYEpGBNupRf|H+T$B;(7c9Z{qLx
zCt4c^awrrtVI<~7e_;knVp)70<FFn!!4}vaJ7W**k3(?;j>9Pd{n|_db8!i-#0~g4
z?!vF|Fn*6`@Dg6bJNO9yHkIw~XcEY(Fbv0>m>*xmGFSntVr^`IiP#!DVpr^KXq5kf
z1cu`%oPg8uLtKE%a1Cz6ZMYW?;88q*=R~voUm<V<@8c7+G!5iX2xi1=m<J1C35><c
zSOe=~<EE7V<^<YdD!z&Ra0vQwEKbG`a1JiU6}TRC+}V`!|0RJ#cpOjTMZAi)@gY7%
zd$T}Jc`ys+z$h$=rTq+)$2YJR*2iYp3VqlGdto{b!*_8!PD6$M`3x+@)%Y21#Xa~n
z9>E{+EdGqw@g6=#EisTou7G|m1Az$4jRmnd#$Y9^j&-mRCSzOdgx#?(4mOqT{|<pM
zI0<LqN4N+-!F9M9ci<Oz5WmAycmaPkG|K-i0uS&nv?T?y%8i*ZJLbb8SPIKw6|9K~
z*c4leX8G?xAPsxs0DKEa;(It1XW=~j7+2w^xCM9P{v^u(w*-E`pYSsNhIjD~e1^{C
zKu&ovE9SxiSPY}FVlw5w8i9Chh)LK6Q?MKM!9n;oj>d`jKF-F4xZKacTHJ)&aUXtz
z$M7Vc$6xR!{*Hg5wRs?iLNOEiBN@nxg|Q@-#n&+o>tPdYf$gy~_Q3u)6h{Q~YvTw^
z!I?N0m*7g=fS=<o{0a}__jm>`;WfNtD%<}NfxpqwB9K*K7>+qHKfZ=#umV=a+SmXS
zu{CxyG|GQh0=;n{4#!bA0jJ}KxB!>o8r+E6a4#OfqoP^<PY^hVSMUbj$0ulM8OWg!
z%!t`A4;I1_7>kv$MoY?nT>_1<Ikv-8d=vZO5cK0%oQxmf99)bmaD7Y4zfNE$eu;<h
zIG)CfcolEsLwt(%R)L)IU>3}QQGN!BVreXoZ(uE~kIk?Z`mhW3!gL&l@8Wp$Ph&vg
zd|ZmF@iW|td+=*Kf<NL}{28y~J$xKc^1pQ;i(HriBQQ4>#Nrr(m9RS2!A6*jZLt$}
zH<i!tOJFd*gJW<K&cKgw5q^T}a5L_}FYq9Kho=mU@_&KAuXqa|;9qEK6UZqyX2$H8
z4~t+aEQeLFCMJkx`EN>~C3e6x?1=;LEgXsO;Z&T3^YCL_g`eV<HkAL}1oq>%_yhig
zm+?2ei+|uVbhZuTlozvNE-Zk>+EV_b2~@;t7>^Ax3EN-_cEdh62;auhI1%5+*?tBV
z;&NPzn{Yes!*B2yp2YL`3*N-v@lUk23*?YLlz~hbiFvUwmc+97I>uo=Y=SMYJ$A+(
z*gv3O8%kgVj>9Q96X)U*T!|a-bKHer;bHt9&)_9f+5XoE+`&iqH#*t}vMLP2F(>B7
z*RTv$z^Ygq8(^ZLQT|&K=!jjhHx9(%I0`4=bo>w(;4)l;8*v-%70vR0fWT2af#>iF
z-oX3#1T7r`ITV5!F&pN=LRbQ0J5c^B6R3f8u`xEsc9@E9Vm};$ejJOF@dKQLi#t&M
zR}ff_I_|_T@em%z(|8fD;%$70PtooR<dg@q_!-E7QCJj9V|jc7YhitChON+tU9cCX
z<1qBU%fNV?h6?B7Qe2In;a1#(U*i${5zpe!cs-zByGP(LY8?Yv<iZRXfw{3D7RMN@
zgw?SQHo|0VYwFkjADZqm&gwdk0`Sl+-Q67$1}F-OilU+@DvAn%(%p6GZlt?Ar9-*}
zLFtxmLAv+O{XhF=pYI%y!SmyM=Ed#~Q8fj1*@Ugxi9Oh#!#IYMIg1Oqoa?xSyQ2+d
z3x5Lw!BL*!CEnycK4q*LK~o8toavaAd03bwSte{`|K$Z0S(#t)d)8(HHfK9_VQ&uN
z2#)78&aGkpO9ZR9f!n#42YG_$c$K&LkS`dwX3$g;reemL;rEaJpI+n;<YzIy%CfA$
zO02?atid{L%vS8k?(7$G4CQD};!G~!GOp!j?&5wP;b~sv4c=wwi6iDuK@$m>jA@yL
zxmk!MSeoVd0Y7C`R%fliP*i<EGqz=C_ToSe=QvK~94_WcuID!H;em+Z_dhN;%PYLa
z2Yk*rwSuM+GbJ-HJM*z9U*Vg4H`?g^e<b*v-|$EN!bWV#4(!Ih9KunY$Qhi^rC}rc
zUnAJWo!rO6JjDyV&O3a}7`20j;xj4JFf()2w*P{H;(VQN^L>88FZmsRVm&rx8;01E
z1Ndug`yVTq!r5HJ75trB`3L{zG5*8L{FnFnjIl#M2UR6v3Z`c^=4BC<;v0O2AM!JP
z%^&zP8#2_w(Vkt|hl4qi6F8mo_#0PqBX{sm9^%QsP}F(BHU7s(jQS;LC>~#8YGz_i
z7U0W#jc@TiejG9U{$B{bWlh#)6Sih2_F#Vw;}}lnEH317u8TH$|62sR`4^A!3@`B}
z@9`;P)d`wP$mC4Ntjxp0VI%u5DJaA8tjNmzir=#~8?ZUsu?u^15Jzx)9s8dqn9C(x
z#SPrfy*$VhJjbiN&4+x!xOIc3lGL^TRDz7m!Tc=7S6P-7Scz3wjWt+@joFGFLyqq3
z$Dtg}Nu0?AT*kHB%w62iBRtKE4Bc?t<rBuN7gUsh$(WW|n45)If~8rGAMjIF4Gcw9
z7t~^XHe*|MW-kupaE{|t&f#LN<a%z47=Hgff&)Cxv%JDve8A_7Q$J`bF;g-Fvojxy
z@|9?#_y4BgU4F#R`3-;MFKon??7(j9%OM=aiJTEOvj6#lrCh^J+{t}B%u~F;>%7Cq
zjL{%yC_a-iO#}PSEXc)zEY8>YHs9wb{F2}CC)Q(Awqb}p8`%E<!LJ<4DV)tkT*2SD
zm4EPW9^*f}%zt_R|G$%Gg4hj%suD2;(=!|MvItA@4Zgz<`5C|F4-Eb6Xvh|9&#vsl
z!5qm6oX&atjjOqlJNRc{DC&^lB+v62|KlS@H3}Mv$CsFznV6FW_%dJPTM@(W|DNDu
ze!*{9lXcmIt=Wk^*q_5VhLbsq3!{zR|8l`PZsBhJ#iKmKOT5W@e9BmjgQgNPInyy~
z*vS6#2nw?#%dk8vvNFHo_pHqZY|eJ<!rmOz*#1Wd#&a6yatT*)1GjT85Ap=h@hWfg
zAzw7M|F}(ps**4jGcpJBvlw4xSyo^rR$(>PU>!CNIa;wJyR#pMax^D#CKqrS*K#v=
zaX*hRblP!|H+Yv%7_({6Py!}nT4rHx7GepOW;uQk7>fE-P?gnLi}l%zZP}T<IFQ3R
zj#D{@i@7pl`2E)lws8*+@Ho%%3UBcNpEFLgpsB=6$qdZSe9=blzo_69zR7p_5kKcQ
z{E@$~5nHkYyRk2aa8%gH{wE4%a6XrE4L5No_wg`K@dB^&4j(f{^Pr*l&Fw#_APqA!
z7YnjDU+3F=pP%qce#f6!k4@R8x&4O(Jvo5CaxABCHWzUPf9F>I!M}No|M2qvKk>hU
z`+UaOErO~NF$L2z8}qUVOYsf9!w>lxLti_7;LmKx7HrS1?8Ctv$qAg!dHjv5xiK&l
zwL|bH5Ah_=^BVu-BSy6h8j8o4n3|cGlLh#4#PIvSCU}eQ@ne3$Z&{Od*@Ugxi9Oh#
z!#IYMqmADGEWtu9=Q?iTZvMriJi|-8$$NatSgnGl5;A$%$o|s_vN8_~vn0!~JS(y?
zzvB0-%?51FcI?v1{(B1saRkS68s~BeS8)Tkb1x6_1kdp*Z@04lhk_T3+d8N!2~#m6
zb1*-P@l}>(1y*7eR%4BjqYfLh6+5y!`*A2oa}sBA0he(tH**(5`yEGkniqM4clm@d
z+XM|IU^1p<7UpIlmSE|?P*gd=2mF*(S)H|5pUv2oo!N^6Ih^A-m2)D7-+!@SCD(Hs
z_wWFZ^DM9M79a3A<FpN$O3akZ5N-7SvkUUEC|}{5e3u{bbAH1g`3oDdB|ESi`-Y9|
ze~4fdCvpbob1Bzw6L)eS5Azf+@H+4Caa;S3(JrVcK9e#HGcy+pvN&Jo+kBs&@JoKj
zpIEP*{Wle~VTe6BfWLAqr*JkGaRq<pR{p`idF=n6=pVsl{>%G(#@OwHrV=p)(=!|M
zvItA@4Zg$BhmOzqHGkmGY{(XD&#vsl!5qm6oX&atEie?dTCkBj_$LqXB+v62|KlS@
zbqE@Y$CsFznV2(T`27nAUgm3ji|_Gce!*{9lXcmIt=Wk^*q_6qjo$wl!DP<jLN4bz
zZsBhJ#iKmKOT5W@e9BlI?LT4oh#CHkBxgEiWgZr0NtR)GR%B&<#qU|04cNS+{kIcz
zVQ&uN2#)78&gBxW;s$Q#ULNELp6h7;R|U8EkS`dwQ_xTnrea3sV15?kt1Qb3ti&oI
zM>W=99X4hwc4T+<<4}&~B+ldlF5_B;Ham84KacP<FY*TO@(E*VG69n@EweB;3k8Ov
zN(f4`96#Wvtjg-F#rkZ<w(QJa9LV7u7cu-FQw4Llm@B!S+qj1Zc${Z>g}3;C&l#t4
z@MkG;w4w0qQVKFKJM*z9U*Vg4mml$Se#0O63mdT|JA{pV{qH8|%OM=aiJZatT*@`v
z#GTy7!#u?cyx!UV?+6|<Mwg(X_)N+)%*<RY$l`pRZ}WYA!Y}z<7jN>DpdOpD4MXh7
z0sNI?Ifb*ih%5LzxAKqw|H6L@j`1H}=D)npXN=u7Xetp?Fg>#|FN?4gLvJ|V;fMT;
zU-Jk4%!X{i_Uy_&9L$lN!0CaZsCk0lxSAWegMac6Px3sk@jpIdRJWj^czlVeBZl8U
zlOQJx@MXTnxA-1E<`?{yHCdNU*qWW#BiiWw_ZJM~7*6IaF645q;}-7bUp&e)yu_Ql
z7dEp0r-E4BgQ^lTInyyK^RO^WvJA_!A}jMNe$U$7?Z1JbIoq)ddvg#+a6G4RE|+i>
zH*h=m@?dxSKOs2BtGvyJe8IRqf~Jx%6*Dpi^RpOVWm#4TIV!OVtFZ>_urXV)BfGO7
zhjKJ0aV8fqw9K)Vo4Jeod4#8VkvDjkPZ+aj&`<&<V_Iej3`OM@6k-XMW;uSqPg#}K
zS&Q}AjBVMOy*Myp`2B|q#&Ig=a4}bMJ-2ZW5AZn8@(OS90iQ=3z5h79f~pcTB{MKP
z^RXyj;hTJyAMta3!yowz8-<PRzono9yRk2aa1<wU2Iq4r*KiYeavu-#R4@C#Ah^yu
ze9RcVgNEWWDbp}BbFm<c^L4(>_xVY0`~On#9e-jyHf0-z*pmbJE5~vQXLAu(@b~}!
zLR$rY@NXXDKfKI;d7sZ1yHC(mBBo$^W@BE4ia1K~4Zgz<`5C|F5B!-8*@Eram3=sv
zBLhQG69m&akH2v>H*yF6<RPBqd0yjxe8i}}K|}E(hTs1sL271VP8Q(He2s7MJ$}qD
z_$_O)E}O7*w9)(TB<R8Z9L6!6%voH><y^-t+|9pulxKJ;Y-Im81^4)rvHAs7C1i4@
zV^-#2VU}bWmS;s)=2!jf|9e4gHehqMV;A=3AdcX8PUBoI;VN$6_I~!iS8$Lgc#c<j
zn-BSdar*~NC1EONWDe$MF}@mdlw}20Vii_n4c1{}wqi$iXFm?*Xij2iregt@aV<A<
z7x(iBPxB&g@GhS)=76A~1WXnfib^ZU!rUyx5-iPf{D7abDyy>=>$4f#vU9}n`}YzI
z<ZzDTRL<dIuH<@d;~pO1ah~NB-ikJQ{|^Mu8E0TnRbr-O24-hI7Ue5^lkf5)e$H?B
zW7x?4e-SidOLky4_T><c;zZ8id@ki0ZsJbv8)*NB1*dp{*LjDJ8Dmh;P<$q38fIoL
z7G!b0&bJ5I|NDYZ_$9yNPprqLY{L+HasYqjSWe+=F8cpJxI*wdxAG7E&13wBm-#R6
z^BH3g4w_2D6im-hHb-6-VJW`BclaSc<JbIwKeHiQusyr7Phco&uwW!7a60GlH?HPJ
z?%<z1#FISFYy6LoB8J~TYDiE~Jif%#%*325z?b<N-{O1xm|yT))@0piqxauL(3+jt
zgZ(*-V>p?!xRA@aj$62!fAMJ8$o|g=F7YPs@hM{s4Vp^G<V?q`%)`Pg$uca@ibL(c
zvfwLz&)RIj=4{6<?9D+O!SS5Nxm?0kL+yWqU_1BnAW!fduktn@@&)4#3z|y8RLsa6
z%pY<T<Et#o3arE`ti~Fw!^UjIj_l5U9LmsW$0W|=0xsiPZssoT=MkRfMc&|DK4HvX
zBMpV35(Gz7GNxq~=4K(5U}=`)2mF*(S)H|5pUonM-@mP(Gkb9$hjSdKat;@BCD(Hs
z_wWFZ^K7)y`@bT%#Rq)OIKzWKOo^G28JL~<Sd_2uO}@*I_<7jK{=X6Y$Y0oqE!lzH
z*q1{%iW515^SP93xM{fk?-cCgVV>dzUgsS?W{eR*L-CoEX_%S0Sdhg>*#GN-xA{Il
z;g|f5Kd~O0vJFG*$pQS8V>#vjKXJBT5m)ecZsi~Ro5%PMFY{mC=QGA088nrMp%jkv
z%*MPd!cu&L@9;x@#;^GUe`Z6rVEe#OR98VC4(3Qs;B?O8Z(Pld+`&J2h$nfT*CK}B
z|3ASaMvV$8ipQ6jnwglB1^6;w<6C@>AM*=-8*TLdYYOVJ30t!hd$2!;aSSJO78i0k
z*KrGXhmGw2FTqis;U(VWJw9cu(LqxQnVjjEm3dg0C0S;){g)S1WMzKE?^&A-*qrUy
zg}ph5BRHPZICr%DFA=Qb25#qG9^?t0<5k|~L%v|#F+o#Fn2H%gjvUO-VtkclS%H;U
zh1FPtb=a7#*pb~C>gO2B(VWDYT)<^q%gx-y{XD|cyvQ588yJduB8WLQs3-xGF)gz&
zHw&=@OS2q5;HRw0>Z}zp{QmU?&DfTm*^2`?oZ~o^bGVo*xt`m&hX<mK-v4pISzh5S
zKHzi485cB_m?@co*_n?;`3m3UyI~{y|48sTzu}Mkg^k#f9oUV1IfSD)kux}-OUK#&
z8o?&+<USteDPG`p-r-}$7#}ngpGld9nVD<6{TCDz=j(i%@ADIW$?y0R>#-@@FvOl5
zz+eCW17ihKIGc;Og1>Vs|KQ&|#(#L3|MEVcF%)}3P*ozPV0va_UKU{~zQK3+AwT2S
z{DD8SVPGh#g`hpVvJVGyBqwk>=kYhL=0@(|pFG5q5yS6)UT}^7@e!jY1`WmIOH9p7
z%*g_LnXmCJzQ>QF4Tbmrh2UG(WL-94Yj$D}_UAB;;bhL@LN4dJu#x?55$xt)Jjye?
z#GAawr;IfzXeuF-Gaa)s4+~GS|B`|-EYFIp%&+)8YqJ5HvmLvzHwSS9$4?3czvF3w
zxm?0k+`#SJ%Y!_@bG*vie8?A!J308gNkWcP%*Y(f&tiO)Wm$ohScTPCgLT-Ltr+U)
z=+1r|%F&#}nOwkST+7Ye#r-_O)4UiMin<}V%O{LEC8#I?lQAu`FgFXa1WU6VKj5dV
z8ZrF-)djU!pUv2oo!N^6Ih^A-m2<e5E4iNAqK)4F9>D<~=UHCiEk59L#+e#4m6$1+
zf!UdlMfpnD$o}6HyvvXHIltkL{DqC!k{#HMeK~}qIFU1^+W&mPQm)}9?&Llm<|$s_
zb>87)#+Vi~6rV|%W}5wH7UW_<7U%1HoA2`ze#!6n6YH@l+c3nQ|33x@e&twB;cPDA
z3jWTm{DXh<82{mA{>#vP$1}#B9#oZxDVUzwn3qLZif`~8e#p=GHGc>UMg1&j$QEqR
zuI$6X9LWis&UyTetGSUo_-DlM`yUdV<au7>e|*HK89_tw_!3hy6LYcvU*>CkE86J&
zzbE*ZU+`PjWL-94Yj$D}_UAB;;bhL@!myG3FBh!i7VhR>Jjye?#GAawr;If-XeuF-
zGaa+ewEsMU!Ys)$EYFIp%&+)8YqJ5HvmLvzHwVqM{}F=moW{9a!d2YB?cB?QJi&9k
z%G-R%7a>R7SwU4vn2H&hgZWvEud*yFuoA1V8f&l)LyaA+*pc1Yk3%_{lQ@$LxQuJL
znY*~3M*>4prv(>zgLnCaF=q!2C15h9WftaUA(miimg5Hz!|(s8pen1g7VEPa+p;rz
zaUh3t9H(*)7jtE_(feO7*v36Pz~em2E4;-Ae9ky?f~FEPB{MKP^M#G<zo_69zR7p_
z5kKcQ{E@$~5nHkYyRk2aaMT?8pD38Y`CQ61+{B&S$HP3u3%t%de9RbggNEYIwg04o
zG|bFgEXd+~op1Afe!?&L9e-jyHf5WT<Nx;b@c{nHv7Ex$T*MXpom=?_|K>6N!_Z~N
zzr4?9j6E-?DiKpKJ+m<{i?9^m;5+<~p9O}Zz83tzpV^Qt*q&Y4hl4qi6F8mo_#0Pq
zW5n?L?-2aSLp;gzyvG0dh*9%{hT`!hre-GQWC6Y$ZS?+M6THRu_%XlWx2(y!Y{J&;
z#2)O=VI0HBVI%vWC0NMiT*ock&A)h*XLyM>d5=#SYeCRdLMC5e|LFu-nTLg0l4V$)
z6<L{I@q5;012$(nc3EKmy#<3fg5x=jbGd}8xPjZbmj`)*=XjO3Lym`h!MF>9s**4j
zGcpJBvlw4xSyo^rR$(=UYB=h!F<Y@CyR#pMax^D#CKqrS*K#v=1%{&b3y$zKFY*TO
z@(E)u3K~klWK7E}%*{e9!O{`K?_W;v0Y7C`R%b2NXEU~CXZGSi4(B*d<(z1v_rF-M
zlIyvRdw77yd6rjrix2pmaTW(nC1y%y2piddc0oQC<tu!X@A4yl&Tsf5e_<oGWCwO*
z-^KPnL@<gIIfL`Llxw(&JGqaCd5RZ!op<>7|Nmdl7)yeR;xj4JFf((pAdB;LzRmaf
z3BTlb{E78Kj;3tG|K~k@Jb=G)ET?cb7jXrD=T`o~zZp8__=lJIFYogiWB(R3m53>r
zp4pg}MOcb&@SVU=)Q5u4_%(mv&uqvRY|pOj!@(TM37pP({4HX5|EmQXxr2Z55Kr<v
zukk-VV${;0p?G|WshNp6qmABw0l~|Bjc@Tie#|fUEo-tao3J%Iu?PEeSlGz^#|S2K
z78i0k*KrGX^DiFd8D8Q|-s4loT4w(Vmj#t2XF6tO9u{UvmSK5TWMzKE?^&A-*nF9<
z|Lp`_*qehmg5x=jbGd}8xPjZbmj`)*=R%IFyv>Jv!MMwVhLSK9GcpJBvlw4xSyo^r
zhN?KKu?Fj~F<Y@CyR#pMax^D#CKqrS*9L~7HVbxfKacP<FY*TO@(E+E2pUSjWK7E}
z%*{d(!|z{0P@3iV0Y7C`R%b2NXEU~CXZGSi4(GUNqxU~mFo%n|lIyvRdw77yd6rjr
zix2pmaaIORB@P?ee@a0HW@kPY<tu!X@A4yl&Tsf5e_<oGWQUdZ-%Ze$LpX{PIfL`L
zlxw(&JGqaCd5RZ!{r}(N;f~-jW2_1)iqE7>!_3UZf-KJ0`8MC@C;XD%g&aSz9-Fca
z|NrxP`gj0;<ycPPY%byo{?4ro{o(kV$M_E~^IzWQGsa#WG?j=cn4Z~~mql1AFckHM
z;2nO*&-gWe;LmKx7HrS1?8Ctv$qAeuF}(kIg5S8B8@Ypj@(@q*Jg@OTK4R3GprLqt
ziK(NF-hU=RP8Q(He2s7MJ$}qD_$_O)E}O75JF!RD$o~5ahH(rha~2nJIoELuck?eE
z<r!Y$P2O8$|4#+6)&^B2WOAlsR_0-0mSh>0XGK=#SNxu}*ZTV3K+v4+*oD10h$A?j
z(>Rw)xQZLNoqKsO<T$}|yvo~r$QO*eE@&zVQ!yiRFh7g&RhDI_f};|vuo`Qy4jZ!-
zJF+|baVSS~5@&KjU?^&tU@bRu7x(iBPxB&g@GhS)=I=p637Cv&nI&TQ{c{Tnu>?!A
z96#Wvtjg-F#rkZ<w(QJa92jjVy#L{Xah%FIT+EeR&u!ep13b>Nyuw?2z~^Bj`;W6e
zs46j2G6S<SAB*x8zR7p_5kKcQ{E@$~(R%xDDd@m%?8_k>#fhB3`CQ61+{B&S$HP4J
z|L^T|L2#XS_?R&^1P#S!Ql?>M=3+q>=j(i%@AH$8<4b<WpIDDg*@plB=X&~h0Dt9J
zPT_1W;tGa-cWmV!{F}%44=?jy-sdyM-WW8Mh$)z!*_byl6jek}if`~8e#p=GHGkmG
zY{(XD&#vsl!5kSe6csf=FrD-G8&`89ckoXh;z^$8HU7s(jM@}56ffFPw(vI~5Ts@%
z=41iB%-8r9-{Z&pg5R<x>#_-3hmGvNlb{Fta~Q{PGG}oimvbGra5w+rQJ&$YP4<6N
zaF0(JYjaRlLMCTAW@R20W=WP|c~)d)eziIL{xQQ(@V%fm8?ZUsu?u^15Jzx4r*STq
za1}Rjd&seu2YG_$c$K&LkS`c_OYkp}gsGU3Ihdct7<$!FmK9iuRalKRSci?-iXGXV
z{Wz4PIVms{HB+#F%ea=Cxr_UGgr|9tH+Yv%7;|gTPy!~47=Hh>f-KC<LM*}3EXNP{
zDXX$NYq36?u`N4C8@>Ntf`J^)ah%FIT+EeR&u!ep13b>Nyuw>yBl~|Kc+NQ6f~pcT
zB{MKP^RXyj;hTJyAMta3!ymWV|1W|@Y{?Gn#=acFQJlyboX@3P!%f`DegFTSj)w)O
zc!Ae>hmRR!d(cpPCS@9CW-b<FalX#CLyq_P3BTlb{E7A0lx_I`U#F*!2k=*p<rL0l
zXpv(Df9F>I!M}No|L`*Z<$XS5>>WW<iI{@v14B{S1bJD6rT7Nl;fMT;U-Jk4%!X{i
z_Uy_&5ySf*EEvfNoX&atjjOqlJNPFL@g&dl8vo;?XruQZwKJ$F9$#W=W@1hj;LCiC
zZ}B~T%rE#YYqD<G$o`uMTC)>-us?@!3@39I7jik*aSM0zFCN`#|7Qf3c$4?|l(BXN
zO(kS<rejv-VPTeJ8J1_oUB3QT7JS9;S(^>mobA|!y*Y>@IG)oumrJ-R<k-ON+{=SJ
z!E?OI+kD6ujJrE%DhX3DBXcm6-%*UOvMejG605KpYp@O*vlTnCJNt2HU?^&|U=n9?
z0he(tH***F^9WD#B5&|6pD^Yh(G7*)KSAV(ib}?`%);C(#1bsca{PdwvMQ^y7VEQF
zw9)%-E9lH#9LV7u$Elpd#azkt+{QgTz~ej{HnRUKf?IsR=Zv!__`{T#DVc%UnU6*J
z3g6_r{D`0LvHx!bKk^qgVoP>lH}>Taj^ael;CwFS8gBak_j2AT*vG>>#S6U7JABL-
zdxM7JGbz(BGjp*Zi-#Pq^KHJ*PxvLj<4>%|rfkFi|GGVWJb=G)?Ein>6vu2X;tKxG
zt^9+3^BDi(W&X?ie8$*+22CXj3`M07q-QqfWf7L*8+?Z!@-u$TANVsHvIW~m4DY|I
zpbrOgBqwk>=kYhL=0@(|pFG5qJkM*<M(_VW!6QcP3o44omzbKFn3DzgGGF6ce2*XV
z3w|3mvj3Wbx@^MM?8F}I&tV+H$(+T7T+Vge!rlAq|1ZH&p5Z0l<UKxRto=b#37MSf
zn3Z{0m?c?ezpwx01r=GDU-5g^W&<{7J9c4j4&n%o=QPd@IhJr0H*h=m@*q#}9Ix^=
zAMyp`{uMNpgsB+H=*YqREXG$^mK9iuRalKRSci?-iXGWKFcj5KFqES?i8Hx?%ea=C
zxr_UGgr|9tH+VN<`2C*<V*VXelz_>YmRXpag;;{6S&kp@Q&wel)`~WI|MdmU*p{8y
zivu~F<2aRbxR@)sp4+&G2f{}7e_U{uS9psL_?&SL1WhGoN@ieo=3`O5!Z-Qu0sH?*
z@HxNXkNky=*peOCjeR+Uqd1W>IG;=Z|93d75p3d4?&D#e;ssvk9X@7^gF!>_nUram
znYluaf-KJ0`8MC@C;XD%@h8?}Q?}v%KTl5|5BPunt79yua5fil1%KyO{=vU_jQ{X5
z|K)u?3k*fYJ`_}yh$)z!*_f9_Sc-4(9e&8q_%(mv&ukbmy#E%0_Uy_&9L$lN!0DXF
z-?*9^xr2Z55Kl%Mz5nxqYy6Lo7<D*kC>~#8YGz_i7U0W#jc@TiejGNk|1SjJvL@@Y
z30t!hd$2!;aSSJO78i0k*B!S1ErQ+ri${5emw1!+_>{4Z1WhGma;9Te=3(I@zW$dK
zlwo;RWMzKE?^&A-*qrUyg}ph5BRD?fn8vwW!d2YB?cB?QJi&9k%G-R%7mRx}XeyM%
zk%}3agZWvEud*yFuoA1V8f&l)8?#klD5|5NJNt1cM{^QqasiidEjM!)_wxu(^J2vC
z``-}U<rBs{7F3jg$(WW|n45)If~8rGAMjIFjW&A!)djU!pUv2oo!N^6Ih^A-m2<e5
zE4iNA!bbMLM{t10d6rjrix2pmagGN~C1y%yV0PwXQND8A{@)b5%a8auzu}Mkg^k#f
z9oUV1IfSD)ku(1PcQ?%!Eae(*;!f`4VV>dzUgsS?W{eX-L-CoEX+n<7%*BE%&e!=i
z-{&X%lHc(s)?-t);r~BxsHb26f8|(C;cPDA3jWTm{DXh<82{mA{u>yIx-WRf*e8Rk
z5-|nSGaK`=2utw|zQYgs8NcQa5ySicS<sLz*q&Y4hl4qi6F8mo_#0PqBX{u6XruRk
zNN|$pd5!<^5u;884aMV2OwCNp$pU<tuko$0k^R3X_?TbtTh?S<HeqXaVh{G`FplA5
z&f>yT_P<=Pj$62!fAJ{K@DgwG9-lJS>7c2EOwM%7dO8&Rggk=6EXgt~&x)+fulPM{
zvjLm49lNkM2ZbCXIG)oumrJ;c8@Qc&d5|Y~j#qh`4;gylh<hezA_-G5BXcl6i}6*K
zWd&AZ6;@*n)(H$nH5RmDM|NjF4&`W0;!G~!GOp!j?&5wPi5QBCIxV=!8@$UWjQLN{
zPy!}nT4rHx7GepOW;uQkZ75s#8xRPpvN~(AKAW*EJF^!DayZ9vD(7%9SB8!3f4yKE
z_wWFZ^DM9M79a3A<D3neO3akZ!0gO-*8YnMUg4X3mml$Se#0O63mdT|JFpx3atKHL
z|L<&^D44<dT*@`v#GTy7!#u?cyv{p(%oyi_hT?}DNtuS3nTrKkoUik3zRyqiCBNfO
ztjDGdwfX<So*ckmIhIp6n~S)DzjG`9;NLvPe*!~Mmj(awKA$o6`Jk#qOu_Wb#=I=T
zQhbB&@I!tUF}(k;1wZg-He?I7XIJ*&V2<PjPUk%S#?{;yZS?+k2>#?Dp5%F6<9~d_
zs0%?u@%R!`GZS;N0ACIp+5c;TxA-1E<`?{yHCdNU*qWW#gZ(*-V>tPO{m&9C<Z`a#
z7VhR>Jjye?#GAawr;K$mXeuF-Ukty0%<vPW6J%u`7G_D7VR=?$Wq!r)S(^>mobA{p
z<mk;o9KrFN#<^U=RouYs+{=SJ!E?OI&~3*<zF^!-K{H91iW!-M`B{vwvMejG605LU
zU?{4Fpbi_e6+5y!`*A2oa}sBA0he(tH*;6S@cZu<9N}qR<PF~C6UMw8G?akJn3h?X
zn}t|{rK64Be>uSi{FGH$owZn>&DfTm*^2`?oZ~o^bHYaUzgV!6>$#14c!0-wmRER-
z5BQvMt^`dbW=dwbV*l9%`B;>%@J+tUkN7#i;g9@<jo6YM*o}R!*#8j0C{E-I&gW9D
z;U@0nJ|5;NUf^}!;p31a#?_#r_)N+)%*<RY$l`pRZ}WYA!Y}z9e`2Vfqbb|`{|DHU
z1NbY)atdd25m)ecZsi~RJ1`V=Oz;mc^IzWQGseCaG?j=cn4Z~~mql2LZ}6Rn;rIVg
z@EO165B!-8*@Eram3=svBRPT7Igh_Z8@>P4f{on4KY55Jd7jt!A0IL5deBfjzQokb
z#GGLx`!67PnXmCJzQ>RG1;1rY)@2j6W+(Pwe-68D|6>G`Ig1Oqoa?xSyZIN7@(eHW
zChzenW8JX-gg1i9k~1B%G7k&0B+IZoE3z`b;`gl025cU3v||_c<{*yXcuwP7F5xO}
z;CAliL7rgfoZ~8Q^C4d_?#-Z~BuvGO%)$ID##dRE6<8@S6jen~jWt+@joFGF*`573
zl%qL`Gr54vxHe+={WlACaX*jnG%xZ7@A3&_{u?xufXSGaS(uxJqK)2v2|;O=;|Khd
zRau?2Sf9<<mYvy)138@I!bbK#RWOH(xsvO-jeB^2$9a}lc#9ACoN;aiO(ni%|0x9-
zn4S4pl&|njzRQpJIltkL{DqC!k{xc@e>Xv24&f+H<P6T|Qm)}9?&Llm<|$s_^^oHZ
zA2Y`7prZIp$~4T(Tr9}qe4TIeeSX3(8T!ug6YH@l+c3nQ9Kc^WmQy&Ji@1Wnb8BEI
z>JP!+JjQ=`ng8-WpE34-K~ssCg6Wx!d0B*|B8K1p4Z%D7ke~5u{=lEvkS*ArUD=0&
zIg%4NJ=*B~&lCK{)!fJ({F8@xlIMAi|M3x{?gS0R<4a5(HnRUrf}AYCm-!ms;(Pp<
zU+`PjWL-94Yj$FfJNDmSFpOh3nX|Z%%ejtQxSN0RD9`W`Z}Q$9`+q8kbvLLgA(Jy5
zvoa40vn0!~JS(y?zvB0-9da~abGBm__U0gt;CN2sTrS}%Zs2zAW$2*e1kdp*Z}TBv
zFz&sesU%FrjLgCOEXG$^HZT-bK~RZRSdBGUhmF~a9oe1zIFzF~i8Hw%V)*@+3D$Bm
zcX2<D@H8*-2Ji9-W8M!MO2A}H%Pi4G??1Po5KFK$%kcw#%Brl+TCC4zY|GB<#ercX
z`yVbC$Elpd#azkt+{QgTz~em2E4;-Ae16~l<2(qeO3akZ!0gP&qI`vK@?Cz!&-o31
z<S%UW!2VkbI<Oo2atKFpB4=<umvRj^aVPijFi(XX7kHg__?R&s1`Wk$Ql?>M=3+q>
z=j(i%?=$p?<4b<WpIDDg*@hwZ<N*H4v7Ex$T*MWDp{U;lTlok7<}v=m%lw!3`HZn2
z1x+Pl3Z`c^=8YJB|004?e1q@sLw?4u`2&AuL$+Xhc4Z$9=E!KH_dh`}o%8q`S92qG
z@J}A%NuK95{>Mj*dK@$qFKlH0F9}jJ6LYcvU*>Cki|_Gce!*{9lXcmItsmQeCqWPP
z=P-`pWX|G3F6TOK;couLqddb)kL~}a;2xhc){~&BgiOwK%*s40%#tj_@~p_p{3_)5
zp0(M4&DoA!*qehmg5x=jbGd}8xPhVVj=em{6FkSOyv>Jv!MIO@rjjrfGcpJBvshp#
z>QzBmR$wJoVKvrZ9X4hwc4T+<<4}&~q=@17pD9?tWn9b6+{OJo!qdFS8@$UWjQK2R
zC;^j28@>Ouf-KC<LM*}3EXNP{DXX$NYq36?u`N4?jqJadU?7Kc9H(*)7jq@oa~t>Y
z0FU!5ukhA0`+p#K&N$D5suD9LGcY^zu_#~Rn|zla@pFE|AD`R*FM>vF$qwwsz8u0)
zoX8oR&!t?$P29<SA;)2!;ssvk9X@7^7ePbunUramnYmby#rZlzZ#&-SC;XD%@h8?}
zQ?_A<Jvo5CaxABCc3>!KkzfUX=T`o~zj=)R@G}49eLiFCs2Gv|iZ>BcFnz>OR8%%W
zUKU{~zQK3+AwT2S{DD8SAzQFLyRuKTq453(3r2DRr*j^E<7#f?4*tnQJjwIC#{c*z
zY-ImYF@lQX@g=5aCgx-TzRcJ77T@E?{DR-IChNwC5sJJ`6G3ZsVh{G`FplA5&f-EY
z=Q?iTZvMriF+#z=`5D0_-sC+#WvrON&ritYOvkLu!@?}dGAz%EAxC9?#qU|04cMIR
z*oD10h$A?j(>Rw)7+U4n!0p`2gFL}=yvo~r$QO(oD`+YSQ!yiR1csvW3ySeomSqK2
zVii_n4c1{}wqi$iXFm>&7~cPA!6eS)0xsiPZssoT=MkRfMc&|DK4Hw*;fA93pCI}O
zn~Z6hg}GUXC0Lr}_yIp<RaR#$)@QS@k^Q$7bY?FO<ZzDTRL<dIuH<@d;~pO1ah{EB
z|5pUJ_<+wDCr;2%Vy0vUW@kPY<tu!X@A4yl9>@N_5&Xzs*oZCJf!)}bLpX{PIfL`L
zlxw&t<k-o5Jj_$P!0Wuj$BYp-Xed6DG7U2`7Yi~}-0?c!=KK7FU-CQt#CmMXHVm;R
z2k=*p4Gcw15zOWyuHf(7%0KuwkMSQ~=D)npXN(;$Xev>}@cvT>(lZ<LvItA@4Zgz<
z`5C|F5B!-8*@Eq(joyD(K_3q0NKW8%&f{-f&5hi_KY55Jd7jt8M)v=o;1Q$Z2NlKR
zOH9p7%*g_LnXmCJzQ>RG1;34N|1|}5*@Ugxi9Oh#!#IYMIg1Oqoa?xSyW`vcUxK4N
z!%Mu$dwj}R34*2)GC9*REAy~0OR`MJQJxi9nP2gH)@B1XXFGObZw}%Jj^{Ln<~o*e
z6*q7@_wpc5@Eou5HXrf@<0cH6O2Slup{R_49L&#Re3fNcft6T=)mVdd*qE)@k=-MP
z_uo%2l%qL`Gr54vxR#r_i~D(mr+JY#csJVU{XY@JOcYd<fXSGaS(uxJSc0Wljvw$-
zR%Lb83LDvfeL*v}WoP!{Kn~|PPURdf=1Q*THtykpMD~ANaF$niix2pmaS{hjC1y%y
zV0PwXQNF@A`EFwS|48sTzu}Mkg^k#f9oUV1IfSD)kux}-OGAz|+{B&S$HP3u3%t%d
ze9Rb0f`;NVDbp}BL%AFUS)8x)ZNAS>_$9yNPprqLY{L+HazJ1x>Q}*7PT_1W;tKxG
zt^9+3^BDi(W&X?id=@dh|JW}DRV88yre`+hWf7L*8+?Z!@-u$TANVsHMjO5V7J~Nd
z%03*-k(|KkoX6j|nj5);fASDdhK=n1yx<!D<0D2T4H}BamzbKFn3DzgGGF6ce2*U|
zwf`>!-?Ap_vI$$W6ML{fhj9!ia~2nJIoBn%|1E;u{EJ6<hL?Dg_xO~tk_AmAWOAls
zR_0;hkfS8auskcWGQZ;Ytjz{&&UWm=-W<dc42^e8<6JJ`DsJF*?&U$A;5lC9Z9e1+
z#!Vh+DioC@IHFQ9BXcl6i}6*KWd&AZ6;@*n)?s6|iWuI1M?rV?<4}&~B+ldlF5_Bm
z<}U8%5uWD7XruRkLvWW*7&ArihbaM*F)gz&Hw&=@OS2q5;HRt_HnRWff?BN4W^BvO
z?8Si`&T*W|Ib6(@T+eMO?0=8o0FU!5ukaQh@Hyk844O*Jl+3{F%*Ud9C8hnpDR`G3
z@pFE|ANdO#u_ZgO8~btyM{y!&gdFp^lxw(&JGqaCd5RZ!op<<{F;WE$#b;86(l|0R
z7YnjDU+3F=pP%qce#f6!k4@Qzp}<g7Pr(5G%CVfn*<8dG{GD6*2mj_V{=>`sH)44I
z_XW=wJ9SW1BBo$^W@BC!VJW`BclaSc<JbHl+UWiNENI9UY|pOj!@(TM37pP({Ee%*
zkvsTj*vS452~P4nukk-VVpN)-p?G|WshNp6S%5F|HNKU`{@)XP%rE#YYqBnzur)ie
z2m5mv$8a)dabX(!UoKe3E!@q&c$8;&i8pzVPZ=w1&{RSuXF6sLIr6YDOR@~hvmz_=
zD}K+~Y{2Gh$1d#6&>+VMj^{Ma<r1#q25#qG9^?t0<5k|~!@y9~3qjm;K~+hZiW!-M
z`B{vwvMejG605KpYp_nl@ctVMTCpR$vmb|YG$(N;7jPNZax-^vKaWHkz5mmKi@d?R
ze8QONgN70?8PhTgbF&ajur$l@gRqhPe=4ZT>a4~3Y{s_i%w8PG;T*@QoWsRjncn`_
z3$}3&5AZn8@(OS90iQEYhM=j$Ovwz)&U_i{zo_69zR7p_5kKcQ{E@$~5nHkYyRk2a
za8$@Kkux}-OSy)dxRd*Mn5TGw*LjDJ86#uRP$<45Dbp}BbFm<c^L4(>_xTCG<ahju
z_1H8p6xBu$Vowg>uN=!MoXtgC!QZ)+fADV}<3AC@`@bysm-qRMu`>l#C1MJuXEx?#
z5tiZ`e1{+MvuLCD|Fz%;{>+AK!S?LRJ{-)EoWSXv$KSY`8^cESzeDgR5Ah_=^BVu-
zBSvKo8j8o4n3|cGlLh#4X8V6l@D|_W$NYldvL@@Y30t!hd$2!;aSSJCw*Ogzg<Q^c
z+``@bi${5emw1!+_>{4-1WhGm@{l7Pvoa40vn0!~JS(y?zvB0-%?51Fb_{iK^yVOr
z;CN2sTrS}%Zs2zA<w2g{IbID6Mco!W<O{~l8dQ~pshE*Dn4iV?D$BA0E3pczMGWu1
zhM*1`vlTnCJNt1cM{^QqasiidEjM#lw9)(DFF3-}yvQ58%O{MPEodkKlQAu`FgFXa
z1WSjF?7y7g1AfY?tj=1j&t`1P&g{j39L{l^$~oEWf3aXC*K-^9@BokVEU)kuAMiQj
zWDlB3%#_TKJrw*vc0oQC<tu!X@A4yl&Tsf5e_<oGWCwO*-;iSnM{y!&a6XrE4L5No
z_wg`K@dB^&4nvO}F>(Y=#Ai~bVP@uHK^Euhe4Fp{6Mo6>_)}mgs-B=J+c3nQ9Kc^W
zmQy&Ji@1Wnb1VPg-x0(6KPLExm-#R6^BH6344O*B6im--%*!Gy#W(m)w9)(jQ1BVQ
z<`4Xt4cUV2*_C}bm?JrX(>ag7g^lcgwO}K6@J}A%NuK95{>Mj*$`v#ek1sJbGcji_
z`!67PnXmCJzQ>RG1;1rY)@2j6W+(Pwe-6uK|6>G`Ig1Oqoa?xSyZIN7@(eHWChzen
zV})`DRV8F{rejv-VPTeJ8J1^7R_0gyp0(M4q2`Wu?84q0#1S0NX`IU?T*VFC&b>Uy
z6M><qbAqe9&4+x!xOsx6k}wrBG6(as7++;sR$!%w;r&+;RAUX+VPm#pM|NjF4&`W0
z;!G~!GOmp_djFdRySSf6c$yb^gLnCaG4louC15h9WftaUp|Fwtmk^X@Iex%TS(VjU
zi}l%zZP}T<IFQ3RF0cJh70lscuH<@d;~pO1ah~NB-r@s3XPkUNQ;GB0e@a0HW@kPY
z<tu!X@A4yl&Tsf5e_<oGWQUNW8~btyM{y!&a6XrE4L5No_wg`K@d88F9e4PcG4cl$
z#b;8cVP@uHK^Euhe4Fp{6Mh*Oiuz9Q6YH@l+c3nQ9Kc^WmQy&Ji@1Wnb8E!#{{ImC
z&13wBm-#R6^BH3o2%1X76im--%*!Gy6>aqX-w?dR5BV9t<`4Xt4cUV2*_C}bm?JrX
z)5AvgKTq%*S92qG@J}A%NuK95{>Mj*Di|~rk1sKGLHo}n$jJhHnXmCJzQ>RG1;1rY
z)@2j6W+(P2X#f2M!#IYMIg1Oqoa?xSyZIN7@(eHWChvtDPZ_IFP*p-EXF6tO9u{Uv
zmSK5TWMzKE?-{D?Xu#%d$1d#6K^(#HoW{9a!d2YB?c5s}iaIDb!E?OI+kD6uj9WNp
zDhX3DBXcl6i}6*KjTqj41wkcNVKvrZ9X4hwc4T+<<4}&~B+lf5XruSPOt6-lxr_UG
zgr|9tH+Yv%7_&&wPy!}nT4o6w*?(?9A(miimg5KflvP=swOF6c*p{8yivx?;|8T)L
zPURdf=1Q*THtyj89_LwJ;VnMk^CI>ir)W@BVy0vUW@kPY<tu!X@A4yl&Tsf5e_^AL
zqa{1A8~btyM{y!&a6XrE4L5No_wg`8ryLh}op<<{F^UBZ#b;8cVP@uHK^Euhe4FnF
zhN3<Ze97<l6YH@l+c3nQ9Kc^WmQy&Ji?||Uc>li(w(<}D&13wBm-#R6^BH5m95j`P
zDVUzwm^a$!{TC6G;v0O2AM!JP%^&zP8?pu4vn%^>Fh_=s?0<q_I_L2>uI5JW;GaCi
zlRVFB{Ev?qRXk`YUUB<>NsyYEn3DzgGGF6ce2*XV3x3O*tji{BUEKaV33{+Uhj9!i
za~2nJIoELuck?eE<r!WIId1YEpE6d7psIvS&UDPmJS@zTEW`4w$jS_T<@lbp*?`U2
zj$PQBgE)fYIgN9<gsZqAFch_2u$KpUg6DXZxA~AS7`J55R1&6QM&@9C7K<3(|Eq$s
ztiVdF!fLF+I&92V?8xry$Dtg}Nzq2{f2LpomvJpOa~JpX2v74OZ}2XkFlMQsp#)48
zHnRV;f-KC<LM*}3EXNP{DXX$NYq36?u`N57vj1L!fgH|poXR;|%#~cvZQR2HJkI|W
zcOPI<R9VA-o16rO43cw@sN{@*2m%r%Cj~_T0YyOtTg3p1f{8Ja6pUcPfLT<G7*NcB
z0Rsp~Fe0LVg|~O-V~1gXS9a%Np7-{l?yc%meX4F(hxw9QxvPo#|3%;r=4u+J>IfF&
zk*v&GY`~^$!%jSbeK?3ClNzV-OrFE(oXIPBEpOr?-pLhwgirAWzQ*J`8Xs~Kzvg!S
zz~7jyS)8G~EX<ND&uTo1N3%t2GSOb33wyFZhw>Dj!O5J)BroUHyn(m!cHR>i)c=D5
zkMmis;aa}OPxuA5a3_D}e&%c*XQ}{;vP@`L|CI!4vOb%zH9N8!dvhR1@KjFV6kfnf
zI6E+^|9JxGT*zfy&Xs(UtNAM5<_Fx!uegnSxVO3bPqc_rl!t{_g5_A1b=Zi_*^bAt
z2m5gdPv+?@)c+)bsl1SvaSpHNEnLF8`2Zi|Gkl3}@LhhK)cBm=@_YWo-<hLjoT>aQ
z!qTkB8m!00Y{g@l?5fd=12~*xIG$(od|u31oXh!Kz@@y85631GPY68ESNIm+=LT-(
zcihci`6qL?iZfM^#aWhBB7^#`Ezpq7*p{8yoqai&qd1lmc`j%0QeMUDLc{vMSzs~m
z;{AM-PxD2-&UO5VpYa>+;E&wL?5)**zMv6(0Rc;~0;{twk6}x8;PE_>Cvg}@a~#iV
zt^UswxQJKq8s5m;cn9z0LtMq@_%h$*dVb0;TdV)A0=xJN|6r~*afXgyF&@dvti=Xw
z$~Nr86WAxIF^D618qef8oX(lNlGpMkF5;bB!AJNMlP_qz#&`H3H}Pw3=MVgi+1kb#
z%FDtm$?~kmqhgbZqXk;9J-e_c`*SEy;TfFFX-x8RUd<bLYh+OWw+r0E2l+Uk<r=Q#
zd;El7a0_?xXYOatc5$W(gogEBRG<tiu_o)Y30t!xyRkP1as*H11Ww@vfzkQ@5`o#A
z$8;{_GA`#zKFQU5m2dL{Zsb?o)=vHJ5!lN_`#42;ScoN9j#XKQjo6&+cpQ7MABVJ0
z#w$8m;B-#nR9?u-IEUBs7B1o4e1MPf8NS3fk{a*wV}8zW`8|K)@66F5z61GLgr!-L
zHCT_0nQWzTEW5H72XHvYa6HfE`Mj93IG6LefJ<YOiTeZ|<`aCLukbCt&kfwn@3@=4
z@=xYIHqKN*7LN?-zpOwN)@DOCV_SA+clPCAj^bEO<hh)|OGCr@ze?ab-ps|ki}&+U
zKFt^TI@j?de#UROgFgmF^}kObd&f9M`IyF1tibB5%VXG*9e6xX<VhUH(H+(QIDxZx
z9xvh*yoNXOHr~N|`4Cs}Iljy{xxS<N|5V^hZsjii!ata+Q=F+ISd2%qGHbB`o3af%
zB{fc99}eP3p2jnI4ySV_ujIA7iHmqAS1|dA##4NOukjsz$W8p3+xY{3W46w5hVrs7
zOR{`yGEq(7C?3rgY|k$2$^IP5Q+Ng^a~hMpoL5H%^?!rFt-PK0@IgM#XSs%J`5r&v
z7u>>~{F(bh!}`y8T%4)`EXp#h#G0(nCTz`)?8e?4$Pql169S|9pCWJpFX3#?V>%ad
z8JBY<pX6%3%D4FeHy)?{zY^HSJ>1JgmpDUtScoN9j#XKQjo6&+cpQ6lQUCn}hVW#b
z&Pklg3wasm@Os|DCA^yt@G(A<)Od++@Lhh)&-pFC=TH2dIgXDrm7hgeniW}t$$A=%
z*^0-qD|>MOhjR?a^K72ai#dyPIX^a;SRk;J_wivq!RPr3-{Sk+z|H)QyZI~sWbUqE
zrh@t}7&Q`!;w;N5tj&gO#<uLt?(ECK9L2Gm$a6!(`kx_iDX-#nyqSx67w_kze3~!v
zb*|$_{EXiOM)ki#;79Ib_HOZmDIe2ViWOL$b$JY1vICFji9D&B`X44Rn&WsD&*MeB
zg4ggy-o`t4FCXG6KF624ssA?x*7H+-$*tVQU-$=eoe*d02o~d!tjt<$z@|x!HtfU`
z*oT8SlBe-Zp2O*!$t!s+Z{i{*@6=eqNB9(9;A?z`A954F=63$T-<Yj?oT0od9Ggs(
z6e!PXJc>uN1>3U=d$K==@)VxI$(+VyWKjQ?3tY_`cq?z`J$#Ul^I5LpTE53m_yxCc
zXJ}aeKMU+<&K_~93a}{4uo7#sKAW&LJF**lb09|qM)iNHzywa=1-yi_IgjaF$Yos4
zm3)$``6}P;q5eM**vPNAjeEG4iJozW@~{v~upFzh4jZvK+x1lc#|iXcKMvu^Je`v`
zl^60d&f)dEg-duhA4qCE#%K5v-{8Can4j}oe$SuyJ9C^EXDUC7ur!kuHEOUP8?zOU
zWmop%01oFEj_27tpBHmhY%(!dU_KXcDevRMe1gyO6~4vyxq+Mc9e4BB$e{lJ6v*8x
zPE|n`XIWNZZ8l^xwq<8_XI~EHD2@#c>wluaxtzgEc@?kY&0Ng8ct0QI(|nPya~(el
zjOzb0fp55jKXM<l_l`4^k7+E$3ark$JccdVfyeh&|0fEZ#9<uGaXgFX@giQqYj`7X
z;~l)04{=p*_5Yl}%Y2jT`6<8TR_@|2{DZmr#F;vR#dstuvsO~00h_W7JMjee;UJFW
zX*`qXa5`u5N?yz4O&W`MCs*(hKE)UK8sFiE+{CZBoj>q5X6qYeD4EC`Hxh+elI2;A
zNAYO3V0(69Pxj|fp29OYIWnmKX#z=J&Z~I?Z{_X0hY#{`KFc*+%lG&RzX%QMe~Z9Q
z{>=T%*)M)D6<|@8VI|gNeKuihc4Rm94vgx5puh;8$_bpp3wQ}<a~{*VkjuE7EBPc>
z_f!9`3cSq^xRGCR8~1Q86aC{1<zXR~U^!N09X9H({+kQ5<8kc4ejLJ+c{(R?Dlg<^
zoWtvR3zsA{?&br0jL+~TzQK3-F+b<G{GLDYcjh=L&QyLTi)fT)Mb=<FHfAdx%dYIj
z0UXXT9M7|Perz&vvA`_O<$NySQr^dh`2?TmD}0OZa|1W?yU3vacMJT=Kbd<#oT`E>
z&a$k++HA;XY|GB<&b}NR8rJ_Pfw7#(b2)>T@+w}(o4J^G@qRwar}-jZ4~*)6oxn%@
zjNfnvf8;)99~fsSAJbTh6<D2hc???)RR0|Wj^~LyiNiRW<9HU&<3+rJ*YHN(#yfcL
zK=uESz$!k+m-!~w^HYAwt=z?5_y=<hiZgWti}A>$MrGDw12$zFcH#-_!$BO$(|9J&
z;dIVq@=A?sc@r1$POji1e2OpdHNL|SxrtwMJAa5xCVmshHaJdEUKVCamS;5{#iQAR
z?b(Gr*`GssN@P&~X9!H@G$wgDujUQBmACUAKFG)UEZ1-?-wO@v{}X{PxP?3UGxsy+
zkT_EXSd?X0i8WcDP1u?p1Ec!yCeWJ$IfAEh0;li-Uc%X&$8;{_GA`%JA?p80fz^DK
zZ}S6g<X7CrJ>1L0&^SYRScoN9j#Y=M|2hJV*qrTn9DA@Ihwx;c&Pklg3wasm@cN|2
zEnLF8`2Zi|Gkl3}@Lhh)&-pFC=TH2d$sEJtROM$8mS#oPU_CZwD;~?P?8N~b&M_Px
zn@pT7a6T{QEY9V8F5pt$$A|d@pXV!li|=zoWKjQ`1-|2M{>nd@dw86wf-KImtisxC
z$YyNI&g>o<)_-4t!5qc0oXB%IgSiv&-+(K~;w;N5tj&gO#<qb`{dX4V&b}PXQ5?%$
zEWjcx#qzAm)CM$gy9rwb>yO@e*g>ERdoZ;jgWMj$F&xLqoXQ!T$=RIC8+mK6{%8Z1
z2;9XLT*)W+9M|v-uH%Q?$j#i!oecg&bhO@m!TO^{wrsI^Sdhh7h80<zN3ju`u?>Uw
zD@5Z5uTw+@*C!%_c}Zk)gvP0yz$v_dmvA=cF`Wy!jLW%_PjWS1jZG%r7WjZ0`4zWu
z5BD;WJ-!EdScoN9j#XKQjo3Ug$bUP5<Jg1!ID{wjbWY+_UdYQhhu8BKF5%swVf{ZK
z@ED)rOMHXx@?(C^Z}~lc;_u9nBhFNQ7GdeYsQxPo)L=a}W-A`cuI$AD9L_Nu&$D?x
zFXpTq>VK}ld@kTp-p7ae1fS<Ce2edM12^+K?&hyK)c>CXxpT&;D#+q2%POqRhHS>R
z?9A@$%fTGQu}O`IJeM<gDX-#nyqSx67w_kze3~!vb*^LbBaP4a4R`QI?ql}g;GaEs
z(B@+rOR)m0vo4QeOLmA&CXN?4ktcB&M{^v{;(5G?SMVC%$lG`a@8v_0!Tw(*@El*}
zn_SON`6ah<7k}X&%oUuU!%Q8)Vmy+SL&N&7CD4FP*@m5X0{d_fNAfhD$#XcJGkGPi
z4UFplCV@q~lPmZLpW+LAjqmV7ZsOP6&L8+2v*l6$dGo}nD$J5B&uTo1N3#XnvkQB&
zKZo)Zp25j^)c-VrBroUHyn(m!cHYAW`8c2D8m{Gg{DfbmR=7oACx7OC=FA&sr~r$y
z3@foF>$3@4vm?7P*;`{ENAOfm;1piKOE{bJn9hY<#^qeeCu5U|)dH{bZGOOw{EFMS
zhkKdG7iTCB3$X;tu`26C2K&E}Ky$X^aqPi<9Kw@%Iwx@|FXUyM!|QoVXjuPC1n%Yo
ze2mZVCBDIT`7uA|xBQ+z@ptCPA7?6mU{wD_1WL0aYp@<0vlWkJSN7rn4(Aw-=h-|z
zzxuyeU>4_cJ{NE)@8iRKg3t36zQy;sft&eVe)Ydw;8*_1+`&_v@EBf@#aWhBSep&m
zjBVMO-PxCelNzHqmJ@j{XYf*9#p`%87xOOO&qw(*Uu5!ijdlEppYa>+;E&wL>_@~I
z%EvU8Vg*)bT^<vgOtci}z~gx$PvS6+<~W|k^LP=j;5EFFxABh1VE^AM@DNw=Iljy{
zxt^c$OK#;Z{=z?)D|ntB%?DU4G_3z41uC-^8?Y(cuoF*U9}eP3p2jnI4ySWwU{wEC
z3S7&ZxQKUh1s~y4e1Wg=9e&77{F>YOLqYZbn?SZgaf<S?FiWyLtMMov%@%CWF6_zv
z9LiG)ssA$sCUY8-yqs6_2Hwisc@H1t<9wEDxR&pwR`7|y7u>>~{F(civv8cL0xZfh
zti+nE&n9fmWJir|?9G83!BaVbQ+NR{;cU)hIu~*om&Ya(D+Qk9YQD<1`2jcbD{kW+
z?qwn^&QKl}VhNUu4EBFjfjVr&=4{8~*n|BzgeUWKPU2Kv$jdk<G_3#Y1#aOI-pvR2
z7@y%we1q@uV}8zW`8|K)?}1VM=Ljy~g-53REW*;P$QrE2#%#r7*_FLGfWtY4<BO>O
zvjxuQ#hk^toX-VZ%KP{*pWyR+g>UhFZYZMuHw%2n-Tak*GI!B9Qw3R^Wm$!_*^tfH
zmYvx>snM5%If`RBk>_#-FXdIdjyH2L@8bP@l*y+xUgYas$B+0Kzu^x4$bHOSEY46q
zrm++&uzGAVQCHv?wqyq$&l7nPhjBE=@hqOli+BaE;f;~O{=ZG&4&KX$xQfs5WxmPv
z{FGmED|hi1{=r<q_4=s(j|dw<`4!`ltjt<$z@}`&PCS8qIEW*88qef8fl>WW7nsQ_
zc`a|^BHqare1uQ&1-{02_#rp(>*DHvyTA|pjoC`XnaRt-EXne$#-n&NTd+O5uqXSM
zQ2#>(PT?7x%xO&Wa$e0Fcq?z`J$#Ul^I5J*4Y*d|J$}M3xP?3UGxsxR$v9I5Sd?X0
zi8WcD$tD`D*^%AYn*%w5r*Z<P@B&`K*__98E{shkmI*B9N<PWee3ftW18(G3+{QiJ
z%S7<%R9IzsSST{s|0M*<u`27Z5u39ek7Ez^;}D+A(>aM#d0}XH{=ZCM4zK4eT*ABg
z03YKse2H)HU4G2Z`7OT>jOza<f!~><beyXEEW*;P$QrE2#%#r7*_FLGfWu3x|1kpN
zc{b1I#hk^toX-VZ%KP{*pWyR+g>RKs|L+TI;AVcu-Tak*GIyCcQw3R^Wm$!_*^tfH
zHmT8>-PxCeIf`RBk>_#-FXdIdjyH2L?_%<PjYs)3U*zjt$B+0Kzu^x4$bHOyWSpUV
zOk=6oWTJvVb=KuEY{?Eho+t7o4&!K!<5@h97x9Y7VE<nua3gQy9lVzhaTTBA%Y2jT
z`6<8TR_@|2p<(_1A&@J0;Xb-Rz+ya-m061o*pzM9i6^iR2XQ1%3ykXjOo4MaoilkQ
zujNf##5=iykMJqJz}NT=KP;>MHwk>r?fikiF<ZGfLwQ-4C0U-;codIj3$|yMa_YaQ
zKz|P9DLjLdIgLqP&Z~I?Z{_X0hY#}c)Bw*4tl?U|$4~eLw{Rza=6>c3-h&Z7mI|;a
z%dirYH8tw930t!xyRkP1as*H11Ww@vyo9qkFE*J-7g)$;T+WqzlB@YD-{uG0$gjAK
zd$^a03SowV{hudlBoc*Kg5_A1b=Zi_*^bAt2m5gdPv+^I6q*e7(Nuv8c^T*Mdfvh%
zyqgd3F+RhW_y*tQ$NW4ns{d~VzUNQ;ojEGT52pMq!qTkB8m!00Y{g^QmAxve{{aHS
zIfmnTHqYn9oW;4E&jnn{`}i=Q;PVxe@jZJ*;4Qw-4cyG{xSPN7Pv#DGXIORxS)65A
zg|*o*snLvW*_qwhmxDQqV>yxMat1HuRlJTjGr3sfF5b^a`7~eT>s-f=_!+<94*tk}
z%w9RpP`=n?B2AzaE3i82@))*c2OiH8c@l?lG{^BQo)?)+BrX!Tg4ggy-o`t4FCXG6
zKF62&CfD;*e#xz&;r`zx@C*N7t}1b=j$kn!$;zz725ibU?8Fn;hl2v6`X4E98qef8
zoX(lNlGpMkF5;bB!AJNMU*Kz1)c-pIA954F=63$T-<YjxoT0od%#tk6YCMWZvqjZl
z|7Q<&L3@EN?8*Kd%2Rj-CvzH;yqs6_2Hwisc~7dtg94B9S+3z)zQ<4a1-Eb~f98JX
ztQOzV0xZg88I4M;$@*-<*6he`?9G83!BaVbQ+NR{iA^SE3(R9W7jhYwb0weTYQD<1
z`2jcbD{kYS$YB5P6-ZQ%Q<R5=Sc2tPm37#N&DoB}u?PEc2u}_T>;H6tNu0_Hc^T*M
zdfvh%yqgd3F+RhW_y*q%jOzbmfzSCZzvoZ<ojGd6naa;1EX|6n!Fp`WRy?+b`tK^x
zivu{EV>q5?^L$>+S)9xHT)?Hgj}O;S|4#@!&sX>s-{%Hy=6Br9U->6<*Nih&ki}V+
zRgxOD*^tfHmYvz1eL0w;IF=K6E@$vkUd7~f8aHz>@8bP@luz?TzRq?0h@bHr?%<Ey
z7aP3)yH=c{d`x30R$z73<uPo@4m_SG@+1!9XpV~v_WxM|=kX$5!E1OUZ{r=jmk)6j
zpX1AXlk53uXjuPW3T)*r{=z?)t9G2JBUp?_vNCJ20h_W7JMo0TsQ&v14B|+h#xr>i
zr*kH+<h8tsi+Cqj@DV;$Tm8Qv@EYIYhup-kxt%}oH)g97XDBZVvn0#28jq@@{*M-D
z!S?LJp6t(|JcVa)GN&=g%Xu|#;H{|zZWp+R5Atz7%Qalf_xK6F;1=%W&)m<PN5z>+
z7SJflGOWa!tj{KF&5rEG-W<pgJe3nTB{rG3K;RP2<~*izA(wGESMo`&=Bs?0A8;eT
ziVXJuHi13d%S7EcMR{0=C0LGCS%;0-ob7lVd$3<<SpP!=PUh*H#HqZHmvIiS=Pg{q
zyZHbg<1>6IFslDI1m5Mx{G8wNd;Y}VnWJ8usr)R$(yYiDtjEUn)PF01W7(CxIDo@B
zhU0lQ&*#OQ#kri%1zcKB{og0>FrVP_e1&iEeQw}pe#hPXm47mK{WwzvSv;vxmQ`4r
z4cUxs*_qwhmxDQqV>yxMat4!^YFx$ZcrzFCF5b^a`7~eT>s-f=_!+<9j@V@4M}d9J
z-XKm<KBlo0E3i82@))*c2OiH8c@l?32K#@sz&M`8^LP=j;5EFFxA6|%%ZIp%&+%ox
z85-9AdVx>*CAV@Hf8ig@)iBP~5iG_dS(&xifKAyZFslDf0w=H!2XQ1%<C#2%(>aq@
z@><@+MZA+M8mj+C1fJpxe2wq$LvG^N+|D2P8?!ZvGnAKwS(4=&ssCyMNAYO3V0(69
zPxj|fp29OYnbVl$<-9r-xIy4n-p+gYARp(mT*I||kDu@hZsAV;%;bKJoJYs0D!`&F
z!%D2l`fS41?8t8H&4C=jQ)82f2?A4i0WaZf&SN?kav7I%C7<MKzRI`xL1eK1Hwt{k
zZQR4XOdJzuC=Uy<1k151>#z}<vmK8M4eP&$KtB%Q$vmBtIF%RjGS1=kyoF16Hy_|*
zfl>WGBk&U6;Jf^opYvOO&!6}^b2N@Km7hgeniW~2vHGtk(3q`wEW5H72XHvYa6HfE
z`Mj93IG6JqtN#T8OL-q3<`aCLukbCt&kfwn@3@=4@=xYYHi=VJki}V+Ral!1*^F)3
zncdl!gE@+0Ig!b8HD>TqUd8KpGZ*tN-p@z*G+*TFT*r_2S!^=#jld56$bHP-G|o^y
zrm++&usZAV7`9{w9?ugagZ+P!z%Y*HIG)Axm@5%)PyrTU@RpG1T5?4Omw=+%!PGA@
z*yWL}cx-4`|6K)oaR7&N49D|qp3jRpi*q@j3%Hc`@!`Oz{+|$dp0DsNzRwNZ%<s6H
zzw%G!&KBR})Q8!NyIq!5g6|)RQc_!>Ayc1XZ|ipOP3h5c!55@P249R88GIp1<S35i
zL>_Ec1@Ci;`jrpXA2ouj<dMO3gvelq6&XARBmd7nt90;PmRjKv`W0jF4v%P@$_%dP
z#On#xA2ou<R%9D?;tA}-K^)1`cqY%`bk5|Jyp}gHxk%$quHYkliZAdrzQYf>iC=R&
zf8cLSebGVQco!uTh3%`7EYE68eZ#@gZnt3Y2T-Dn1z&s~8GPYsWbj32k--<7M4rMk
zIGNKTgZw82F6Y&}fw%H@-opp^IG^PjuH}3DgkNw=XjuO{1%Bp!=FA@7g90qdGOWa!
ztj{KF&5rEG-W(Vh)&B^AQ#pZCcmXfrY|djk7jhYwb0weTYQCCX{l6{n0XOn1ZsQ*A
zWg<tMp*$?a5-i86tiwiZp8EWMJAvcagZ(&!C-Zbp;#6M9%Q%PE^A;}Q-ARoH_!ytz
zOMHXx@?(C^Z}~lc;_u9nGtN|g7GbiqMn%?OJvL@59?P!m#Q_}7F&xjcc|I?WO(tdu
z%;kJ8;8Nblhxr7b=PP`R?{fn;^E>X24C?<^fj^l$IEZHt%CaDfvn;EyHXE`T+p;se
zvo8m8RA^ZLV+AJiT+ZO7yo%THW-jJkyq}NqX}-wUxh^oO|BnPd<2T&FAGwd&bH^FV
z$268=1y*NW9>bRGkX!v9FK{AH;xLZpIG)AxcoDDQHN26x@ebb0hjIt|Kit==1fJu|
ze3R?>DZk`a?&2@}gSqm=;~&9dJd%}DpZ~8V(11<ZhMjl<`*09P@-&{wb2yzdc_owA
zYTU#{ypt>V2%q8$e2wq$LvG^N+|D2PTWm6sEpMEnye!O;EYE5@ibt~r+p`OMvOkCN
z6rK?o?ElFE)0pJtyqY)gR^HBg_#hwWvs}Zqe2<@mhV}o2z!vW0&)m<P`Ql6!U{RJ~
zCDvqpHeqXaWVgVm{(B1y<OrV1pzNb6Iq(_JKc~_0|5vqKZKh_?Sxj!@`TyaX-7c~r
zck*8+x9a}|3%tg^X?A<)$!%)#d3a{Gho0Of59{o<(jh0e$;9ED-G+zutS7g@{y&Vf
z+o)=?oZN=>fB0s%aam?HxsB@ou+46B#2b*s<TkGV!!^4-^yF6kAEw#up(nRVlg`64
zyFK*eHhEZQx50z^5R=<v;&9Gx!}`y9avSXb!#KN*>OafLZCL+@Z+07(UsjXbsQwSz
z?ABZ_i^*+V|A%XKd+5on`aevw+e1%oQ<KfZGrK+X<TiO&XSczF`w)}cWa4nnZo~S|
zdU6}={|RQfQ+NR{;cU)hIu~*omvbeb<Z8akxA{S6SpORZzT!6S;a>iy)9?c?W_L)K
z|91%*VXAttFH;wrN4PzP<2ad9IfFAfo2eHhZgl%rE(z8jt@tj1`}ruJ=8Jrt>-Z5r
z<2T&FAGwd&U0Kb?wBY;4qYX%<_TRp4Z@?^`*+k<W@`+8b{%FDf-|O~^^gH-7n|Rzq
zJ+Vn{GSJujH?P|t`k9RsANa&3xG)mk;exTrL~((#tisw1-pUbmXvVhe%<fD*Xa~DJ
zieovE=Q4h<2Km2K;3{6no4J^&$H-rO7Mxl6MfLyRD!=*eNXFL#qx1iL{^Mc(7heyI
z>p#N_g3-P{+^+}zv&_~1L0_Mfk^i{Pjq@*Mo~r+Yy*~GM)%n57Jb8%M=l*h?|C=w*
zB@<b{K6mIV82{M?j3ED6zCKs!kXJDNvkMsE`9G`I=fcx+)>kn8^#aBLhuAESuu=X0
z)kEyxa72vjzm@Xnz|;}3r`!EGl&A0vrY0iO+)h>1<!)ci8<?7a+@5;<{~rJGARp(m
zT*I||kDu@hZsAV;%>B&itXP0WQ`i4e-|t_^f7E1sHeqXa<iWnze}w-()YtkaFR|ck
z{!QQO|L=aSe=@PhivO<f^-n!0|9Om$=MR}5;)6%Zzj2j1Iw>7;E@vPA%Q0R&(?fh%
z|A+e+pVc8gs{jAtTQK7KPgTKx|1B87{tpka|FgGXB)ya2|MwXGcfAE88N3H0%0QM^
zse=q1ri;|cMDrZ+2DIaU_bnK~{=eIbv$#qfW$5p|NF5!h!utPPpHKwjrOuxJ&eQp*
z{>LTaUGUdWqjCSga2Ad0|35yBI)@zWEPC*Bg8Hv41GV^HJ0}F|j~-mtGWEW^MQ;D6
z&+j)G=WA|f>YR}LP2hm{<sI&Me`?yFOl1DPyu&^3Pfh!S{Ac>Uyh?xlobdlM{f?gh
zryiaEi{n64|6@D`4m=JV>bl-M{nELR%eb5?`6O5K)ztOBw*@}nMt;R@+{3+0sQc7k
z%_`(}2_7o56;kv6>ISUKW7v`%csx(!NgT$}Ol9&cx6k9hJT_AG|G&BV734p4^(&RC
ze{b6Sx6PW9iNE^J<-g|$8RY*^hseWvgbdIBf9;*if6oyzs{g<A&gEdk|Atv}eE$C{
z?_3V2?f>blIajLw{}+ee@D7Yg)qm=Mk(z=X>d-qk5ziZLWa^5>61P*YsH|{1bqG#f
z+I>zuxklp+uH%PH9f~)*y_Gxp6ZbJSk4PPoQ=k1P=8$|OE5{}iwFII+E)^Vwq8Fp{
zBoaG<V`cVyiA3(8ojuq;6+?qp4Vs4*P9&mtLKaCRhKIL{1+R35mPjOKhn7mjSG~F<
z5~afp3&xEO?ZNHnVpp(Cr!d|n$bWQ94^|XiTnZK#8U9DG!YR=Li9~c!DOm9wx1+OO
zumQ{6j;<L68?x5zcS3^=+V1wQ&|t%&Pdo(U9}(W+U;`8N&pvNL`s!+FKNp!YX4;hc
z9Xs@FG@{SIh9kQ6>79OW^|bJ<-VdbDsF7Bx#dX2b;b!La`#>;6u*QG<v=3TG1i#^O
zU4!3$ESLUfs(ZJL;RCu44E`_G{e+CmrI)X1?cFnm59mHAL-+7G$3NFTA=N#+koS-9
z0o`Y1=ze0x<<g%?b?=oid_ecb8M^n*xLkU{S~k8<#_$2%S7qqlH{){Y!&2S*WegwC
zJ>1!;)b-D}T>6Ss_i&DIu=~CxL-zq0mrLKD>K^W#gLMz*KdH43%D7y5kJ|40;Edq|
zHokO*?n5#zm%bp?JuHfYtv&p-R%-3x1n3{jrSC{}AD%IMz}k<`(0xS4<<i^KvGF4_
zh7agIGDG)K8JA1HI@SH;jNt>ihadk*ZTu-2mrLK6>OMMS_<-)=WztmlF&URjuXmJ<
zKQ&|cfbMr^=zdzp<<e)Qx{u8mKA`*a8M>dIak=z2Q{BT$<Nw$p2Xy}^L-%nRmrE~S
zH?35?@F+4qWB7pXyE1g2@c5{@Y5TGzZwUT`Pu`$U*!O6C!`tEHDOfxaPJF|kUcu$2
z@D<<GPq>NUPk5m`I0h%$2fyLZZNYeHf#G<KgWqtuaJ=v#8;+Oy86Auld{84jM}xG=
z^_B;nehmU)r>4Pgs#Ew;vW%U=Q^lh6B@NPwm1ugvf29Q*F*bc&-LztD!dI>{Zqm~I
z1ruR0hNHL0FnZSmhL{#~>KYBvGW^_P#vy(Wh6s;k;SjAd3^DA0Ay(&0U)Uh6WXnMZ
z^zZ&h!NjT{7WQwGS^wb9hd(zLNdNx-^cT;WD3oYeDDK}bST2>If2`kf9ZIIRZJ1WF
z%|F&J-ndYqMBd=E6t2HR7X8DoQLi6o@xUQk7b%oz9&`<d=$OS2`O5^)F)|-wN`@gi
zXE8*JV2CQ253xKLqL!@)PRR#N#E@W!Ycd~VeK5pgLv+nzh^@g8y)z$TO3^}zk%mZ}
zcf$wyfx9F83iKS&<Mm(m$ogQ2@HiZ%Gj;CGY>4o?!OzHiD{>Yul$d2JQs>{yhPW#j
z;<L=RVooqbt>7^dZbj-GoY@eUmro?hWxf@U1b^eJlC4Ochcg@E_F#yE?9}za5VZ`E
zIu~a)#7n^tA4gm9&jRxR|2-HYoTr6%By~Q{Y={LF(*HOnlLE<Ex=><T(YXJhV2pzm
zSokeD6{B4K%O*^(Qz$XXCZtZvnQg+>2I&hMXR-;~gFlKkFE~AgcVSo-n=tO0Y>5e(
zXJPu&g`-(-I7I5qoY^LPbWM8OCYfx)k3s*7+QwNJmBl8U6ns>6O6HHKDf<d1!jojU
z38~X_W}EQ(%h?h`Grt$*_7_e}3c80wq)yS94N>Ej^!iORxfgSS{^1{#4Ev|f(V6wX
z_ML2rKhhgD4Ne&c9_+g3O-oD)o=Sv6oF4oh?BOssxCU7w^F%ydEG;omB2wq-%(i0b
zr`Zy1GasUO@F&m48e&2gTk++FY>8!=SLgJSX^B-q*YJ)^%wmWuHXd}3HZGNx2<I)~
z5R<bQV&A50i7V1OG|VKOKbB5QeC{xFb{0ci5`4sZMCNy7ec2!vLDz6A&dFkkFM=VO
zMqBYO1=>3J%W>f+pTi-hW-&ymuhRc$p2_2CZH2VN;^2`G_CGI+{x!B_OVrJLkB$%i
zW?gEJUXaBQeYR#xRLDG+>#GGrxEC|B7-G`4YzIA+*G!9^O^0_RcpiPwNB6>Dh$9bj
zM}i?zkM4`J7-H4-Y>5jq-=i<p3U)`(HQb7sSq#y1N4CW5%!lY#J1udOAuh{ei06VK
zZp=KL+k+u?N#_+=4AE~_wnV+mbFrarT4I(0nVn&XGlN+0?;k%G@6MLEEqz_9v|`Ed
zwUdnV%hC1I{xQG2D#H-x8=|2>%J0pV=(jyMF!>3G4}UK^V7bY`U+nCZTF5fta@WPn
z1v5!MtAYh9rB801R;*=kTKPZQ^hmHxi-X0&{WCZCO&tRl1<U0~L`Uc#8hlRUoAhT}
vr`0HU#J2?#4THn(^+9ZY`tH_gWplOOT`<u<y-1t1s=4|#NJ~5x<?sIizr5X5

delta 282298
zcmY(r2V51$_dd+tw)OUkU1RUPCB`13F_zd(G`1urmZ-5sqZd0MihvYpQUpX%6f7Vp
zg4n=H7ZDItKu~PhmG?O$|IhpV<zsg4oH@^P&dlykIWtSno}t&?582bA`Q)}b2mGh(
zO;?BZ4qgtP4h((`!v9}8I2`YFmht+?OtxzvR5~yU(vqit5*(Ty;*}1KuQLu3iT>w5
zhEcWdC^|3<=WXL17@2a<N;wkN;}{3La_xIc*xK$g2ZmFcPa?;$y>eIwg+lrJ(v?&;
zNkKw|cO~PXJS-?2WR)tr>hND6JFOx^WRVG!U7F529HPAD-+b3o3WuQo$={DsIqdnL
z{DZY}hfS0x65u=JvJNZ$C;zsu;4uGx@~Z~34wL`O+X?VpCz->@|6jp@Y3(42UyE|s
zmvwa*>?qd^Y{`5n4rr-r=cs24sv)*@j%Y1C(?(;2R%6W+tDezW|F$|fDE@<TXx0Cq
zB9LM`$FBfU{a+Edc#!>r5{I9>^!$%Xa$>O8-~3QJZi<X@EM3sfa<g1%{r0@lLEcQJ
zv;>XAkEV)$3%z7YrRnSGDhGLEmD2LSk3kXpZ_!rVg9d^~hF7*|`3gF%1UWA%1-YZ#
zK`u#3)m}O8Am`Ld%lLMpgS?5RL0@72H~IG}S8M<Kq0#-XT&Z3?TkfEc57z&WR363{
zl#PD(2WxlZzw-b5Jg7DOn^$hr={-aMqZqTY`34y{{+D3COs23a<jpMq3gykM|5K`v
zH@E$ttgp<mAurEm8vUPw09oUI^YZ<&CjY9`E1D|JyTVle&z?M7*6cr>!?Nc8{kkb@
z!8&*i5{-<^YogfQK7BUx|MV4dOIxL-@E$$XxIy^W=c5wW3N4STTcHZqBaiTOJFHG7
zg%LAkxQed@T)%!#`Y~0cGvFhYrrsdz#C24<d@jjHhI6?7kSyXlD~Ya~f3;K6H<$n`
z7SZ*Gha^dGr{A)#2{18Fj;mWF$wRjj-R71ouHP_Zz-u6tdi5vsOFoiAUdeP#|BCcu
z4-mt<I70nqBh4PQBw70l{ceAlqbKpoFajr;3ATAQ!T#7q=CwKG_4-$2=C3@0MSLbr
z-6E0<SVfu-zoPcook}fKznvHs7m#N8RnloTkR*2p)9-&W$mHCmq+eD^{Ifd99PCPm
zu0fPJ*@dny^GNAo0Kt~^CG+jRA-Zqt$nb*oRPPsC=-TNCN%$6|Ie!)D{CS(4IC_;z
zzdS`eNgYXY{0WtI8bQA+R!~cL#geTzMc}tPoUW&WOLOQN-ilPGYUw&QfK=x+)MMTE
zM8|iddSs5H8tls;{h|<(&#59;JZ_VI#V;f;aV582q?7z%c>}fuwN~ONx_VcVWbhyK
z+dfT4biZ6BfZj?qPOl;}{TkZfbtWm*29nO&hL&J{Ca~R^B=;6lUF)}z<Zc{kCLAD!
zM&rqef+HkpH=@C<$0X_6@Psu9px^zv5yNWxS@LmJC{d(FlHtA`=yz^MBC6%6B}O(h
zZ_1zad-!C!`qq+Wc!RuogQI_0iOxe!#@1Y<%2Z|0?-kd`Ma?yGrNevDnTP%#JQ}jn
zED85t>2S-9RC~ly@ts^U;O<Lq#oVCltORmpLBosm>NWj7(~LB?+@as=y+~*4ZZfk+
zM~1`wiEYM0D*e!v*v=oNQsyw-_1S~SqVge`cL<f!^Y0*$QrZL}YV1zGJ!aE&WiwJ*
z<3rbUiLMn#Nhc(cN(Z)~-(UYmq<IaG?M5}}jGjY=1D(l<m|0}3(@K&&YDTCzT9V8a
zskGhS3VQx)Mo{B;))LXNNAx=ggDviN1<~;x==alxhxGP5BHEZm@<XMh`Lv<8NNq5j
zSwW;7{~<Yhm(1`zsou^Q_R;KD2sONzT5gyNl@_!Hv)y5DGLc58sW$H!0*`Q`-)F9n
z{L)<lOAVb*&nNUdUPTnE*HTkI*hL0T<k4>ph8(5C=WB$ud6A~~kMvtxOQm<h$z;d?
zx_-NvtTbOma=T+|GPCX(Jrw6BkcczTwcU?Ix5$aE6ZQ~bh?eAglF0nvhI{#`7n$Ex
zLoIacA7W^O!2~_sG?L`Hka^aJBq<>zIk}U}hutKLi#cL`V2`KbPf99|yFdo6jHB!P
zk)*W0!HFIzWb#re=|sEI^?Wf=U*t*Wv0sB>iGE*{$kCo@Bw3wHzc(HxY#WZQCts8K
zA2R70uz^Z9{9&hts<}v+iK+AiO#Yr!_x?a`t=~qZHye}A{05!F8%al3M{;Q})nM8p
zD%}@M*A7?6xtMyAkIrgni3g-#caBV+XhkTO)l|KCS4qC6O+)|hhFPN0;qQ&)#ERym
zG@&J3^9B>$^O00n%VdHH3rN1GBY}nGMEd&}k_7xn*KeK?PX{0RUAUZ3{1nnmJ5Si(
z`;&`<-qP=9J;>Ik^>TXtyLl3z>yOlE0~?b`(@OfS*hqBO4-?Vpfkc$uAUWCazP!Ie
zr3=CdtN4phO`8(wABV}n?ml!KB9Tu2NV?{YqU*{S(p=Do*p?Kbo$L<NjHJ3?JQ3Z0
zN(F^@FO?228-~=$6RDO%K9CbzexfGbQbWya>qPoq<%DhLPo$nPBsm;I`u$E&T_+_{
zsUd+3_wgWkbpy}La^g?>Kq&jReni@LK||v#CxG7!0xTO$fH$#Zc-&_Cz2Y%lTQu|p
zf6gT*W?d$t1Jen$WghX=eI`=%EJAfzOp<$UgxZ3sz0%?Bw<K4ep{u7O$+PSYL(9Vr
zMAW|@Ir01qU8lQ}fdK+hY#2+w|LNUubt3Tke@Oq!pNV4L0-}Dbq2CzxFil@*BuQ{T
z`fbuEaP?Ti;Tnotrg9h=MVw9d$npE_VLbmThfGXMF}t5Y^<J`<YGBzzfYKgB>fSI7
zdDZY7<Uf)@t}3ACBR`v*@UJ86+^0mE@fY2K&Xx3glA5md^~C0ACgu@5Y4-b#s^M-T
z%^`1b|IyuMfzn}QF#(((lYzKCq#8MceB3#fy#B5oIqEWyH2Zl_3tg>H;`f-oq%$gr
zu7CYZH=<u68HjI~@%3v&t>uhP47epEFX&0w9cH?|f92p{2ds>I3BpsYa>&7?QRPrH
zhD??R5G)1Vv&zAeMQ(NKNj2`)@EmxD6ZNk%sb)hOp7|-eso8f#h*aR9bZj*rt<-iM
z)_%&4v;IIk4EOpQzb8ioqoPx$y+G+ymE8%MX&&1Foj!UJ{GSnJg>N&p^eE0B;sn@l
zCuxvbmO*!TO*Kt1?XpIYY+;rTg>^T^DIJLq^MvLbzD#5dob+SVsmSeP+?FHpXZ$Jv
z3t(DIfzcplRW*zTGnQT|y#M<d?=av)m|a6)IF$J*2dZIA;m`0joY_fZ#Q`Rtg)oBo
zl?8VsbHR=zig`oB-a*Db25ixcwHvq(F<XWJaF{u@2A;<-jUR&g2y=#d?W4>Sdh%nL
zPl*s7W5j02*^e_1XaJ03#_s?=o-qk1Ji%<;1@4o~#QU&&ig`klw9||$_0S2-#$8}b
zWYQy%JHvdP3iC<K?_q!^GmQ>Hc$V2n{p&fVxeuI4VNCDAa-OkJN0iEJkAh|zGc6G2
zFW8wgF-UJSVPrRp(e{JgY^K*tG<FWN-V5Bh43`W<9wQ~e(K}3|so*YT=3fBrF7uH3
zwIW8-3CVqCd?gH)Gd;9mdB}L~0HA`IL4!#p)3pcMw}u%J2HX?I^(}<8jD2Gj*q$*p
zZ&0V_jKeRGzF@3xki2AkOJMgEla_$8I;Ph!2wyW}Cj#(>@vA}ZEwiRI9DUEk)WYBg
z#^WU_`jLrFKv_ML)f477$*$2fYO`#h2Rz&<d+}a?ef(=Xg*p*??-kzwvvdLVxqmK-
zgQaC3N5Sm!_KWa)Maf_+a7n#YhxX9uW?F&@b`SE!wa1gbkoR<I3S+%))3Y1GlwqaQ
zpspxxf!eChHishX(gcLuizrC=@01N85eH>UD-Bxq_Ti(^Pi<iw>A~L0c%qM2IWuXA
zsFn*e26Hx*D>DwE0_9Gob4$FO!OT0F!0u-XilFj_DHsB`J~3y{foz-1LQk!$tmg>$
z?kzh*lc9aGF9VR<FKfCB4G=5)Y5{O5vZ~F%Wy<VpUSeTN71Ul?jDkkYVraG8IT3W-
z!nZ>{$b|5Xa*}5c__yTzQe54bNEuv+WFF6lZZh-p8dUNI)8!a?kXKBg_kT?wjF}EX
z-QO4nRGkuTp_ZL%Fg&Qbl&wc+(zVe#&Oz4APQe>h_jmnKwI0=_=y!SstI$rpT#Ddy
z@8ErC+&((QQ<QxNrofMW5z)At{U4mgbwD}IOa|I7!Tj)wO(-3s_km+Sc+em*Yeg&Q
zEbKB2Jj;J+i_*2T43KYP?5?PsGc({%aNE6@wXeY9%S@+tJB(pz?R|vd6(Bvuq)&s}
z2~30ciA;n0XP5^6lbD7IBr^>aILnaNsx+pdA{Q8{Nkgj&xo^=3W=jsPj<1Hom&V2e
zu-9_fNqE}E*ZvP0w4Kxx4cTSXWL$fAc>vjKRUlQc`gb@p$V#_y@S$Jf(TEW<;rr;8
zv_=}&iviuFs~hD1nzDX%4U|p4?~LphBK7kfv}<tfGqW>{5B9kT`RH}D^qlkyy>w2D
zr;5S&vx(7ofM_$*<tNzpW8CUMzK{85D?IaOGH6^6W6IWoBb<qS2H*jvPcFPT%5)@L
zEYrIdc8@XHB2*HX;xfP!8Cx_o&oJF+ZJ*9uSPj5M=7%_FUSev)QI#B~9B;B6-AlqP
z*v(^tIsyNPad88pf)S`PmCQ*2s;`;9(tv-%Y-<UFZ<(b|5N?-UY7EUCvV-qn&{>wD
zgV0Ad+J?keHqjGgelpuFcpoWS6%4W{S%*a^J184C1-MhPUsglKep*)l7d%any`g2^
zCE0z7ZCsXZe22oDGAjjO@@1un*(mSHEOgI`WpfB$Cey^CaUaQAVH8zX%Lc2_T(4z`
z%TO05`JTlf+a{0Z0dSK$Z-eG8`RChE@ssy20OvmWZ!MvDz%E~~2C5PA<ZqE2mzSl(
zQk?wNZy-&TpBxQ*ntUH7?hQ{<3-{pweW9;LwsqUisCS#|t1xq+;$e^7ksrQbH*Ae~
zNt1w4)up)pcG2O#XR(oTGV0&K^=FWFcFD!HTdln<lAbXwLC~k9IsEH?3B$hf%SFFK
z^0ngwwD-`;(QtT#b`dnkdOP4cd9xkzpWe~hY(dADC|%rYD6W6no`Ye<1Vl)cNvcs3
zP@`nk^Q|y?R@G??iqciNRIv=zRt9BRsvDc_Fm^}f&VlI~d;3SIzGUrRL1z=se@0zB
z_*a9WdO~wP3Bn}J{8zB-p&RrAa(i`uocQnAKgwLHhGTb`?U<-2?=e~%a>Yy_jbHbf
zYCY)7m{tC`(dA6j14#DD=3Rg>Z@aAiAQ*jRwKP@olkGo^#9!9;GyDpWeP{-@Alalk
zB*C(}v!Dr)^_+rSsO;}VXokzOMxf#cWUF?<%agK^N0FS8MbY~DwoL8`FS2AWFTz5O
zY&R`Lb7dhpz~#$AX~|w7v)56Gs!%qY0tk0yPV|J{lO^_ouvnIu3)NCt7{#pa%Rbj2
zS1$YEH;_J%4WV%0BUx=7DpMir{56DCvVh-#do0T=21|{sv<CoBWJ^Oq?Icg#fU-^U
zUkZ_Ik%v<QZIyShPl5Z}<yW7;n;mjf5G);(x2HEbT5hL%l_h_20=aDY1r=y=<y(tj
zFi+m~FoXs2*?*v-cjR;Dz?r-9$+VU(lF#@FNwNIsFMyZGr(_~2lZX9?MktrZMI!f5
z9@PQ3M{?Ihnn_j4kKIJJO8&*SaH?9qYYDh(<iTYAseI^O<Z9(EZ=v~IzRCca7xEsR
zp!rJPgI0oda^4fk8@b0TRPC*N4~+`%<?RZA`ykJv`hJqX5ux%~?oXrJCdJSMRClw&
zWw8SN-!{d!bwF%a*bcy;v*JKDD(a%x@CRzKQ_(*P2Hg}*sRP@saQ^@{cZE71Y#xfQ
z{h;ZoXtM^+>{V1!7{^;N=PQ)?DmHgV;-|=`kV1fBb1YN>6)!0+7p!3O;KhE$5Y)x4
z3{~{Fi^4EP2_9x;gyMiZyogi;o`m}c72W=VYtf3pZ9p7W{P87B#3+92gWOStfu7D-
z#jg|uIj*>feHUe%B7jzvClmv3;}JNiV6y;7P-y1DnM6fWXOJZ+7RCUctoWuGRP5&z
zlhn{jQP_^4hN+4=%>9*Viqq*pq$~Qd@ZzH49?h~YE2iIs@QPwWDl{_`6(+cysfbn}
zxvpsY6;y60reeEBc}p?;Yp~o_<a)xxY{jixP{~mQ-hyj+ik<zzlCOAa0N{>YQBOT}
zq2dZfVT%-fN|D@CWNigaiK5pBRIOC;!3`?qinObsd7!vtNAgH<u`^UE6dMX)qDt|p
zHH429K6yx<C^Be#e5yG7Cz|A$VuJ*h=ZX(|;Py*J-a90(6fs38d#$kdcLU;$;^s22
zy;GzQf$Dq3?rR|Zs2KAb+Ut{|-+rh#DVNd0Vv{oG5rA8i<EDXTt1`A3T-&aczDHZ`
zQ0_Ouu8Z=e3^-TicN|#Ul&4hC+@*Xr9Twb`L-S!_kMbS8cb-bg{w<_l%7v$)<D<Ou
z4NUkd_mslmK4rog2>q2wUxPbP>C*z5LCTjN!0%W7nTiGuQ6B3Jl`!RUtg@8h$_ck&
zK0>+28-PgVgjnRFmHWSer9;XRT5-lGt>Mr-qHIfx>{z8P#*WGyQ?94CBVIZ35x7q%
zJJ4u(N||sIG^dqyg|M5bTtboEGfL0#u$!!`ya|=F%AZ#Qo}%374fuKGYi|hil|A<&
zSD<_wirigg&>-N7l=ol2nPTP6F(@lhW*mm_zOq+@1Kz(f<qFy>c%b~k0qylrd6!~F
z70Q(~=2j|A7vZUsDnA*?CRK|sA>5*x{u_MSs&b<h`*u}fKLB>9n*9V87gdwXu;i*b
zG8V4wQuU|E*KSoF#hyG=EooHqR832RA#c@7%<=3>AJu0H-TA3@=AxnYsUDq&PJqgl
z;&Xv2pR)koQWbrP+-(&z4VpQsb~MGwReApapYm1Z0|6*d{kRpmLe;J_V7aRr)&-jP
zRKq$VSF9@P4}VKlpXJEiS1Bo`Q?5$Wf!h8+l@W<LJyL~JIITjJG#9xl)$=28@v+Kf
zF@QCyj#HreM78e<EIm_M8E`*W<sSvjE7gXpz}2Y+#zOP0%JvJqc&B<+jk1rbvR}|7
zpH$BgHc-~9YWG3KiQV=L7B;go3hi&Pvr-+hN7=<Bjb;13go)$q;2|&($2Q&zwiE0R
zacJO^?1J_nJ<Tr5K`wy}SHbQXcG(KhB(XD^LU@)<q-~{hY}bh>JJ0r_y^vJ4fM%{2
z*j<yLlFsg+VE84raSnu+S^FpoR$gU;Ltr<9b*CQn8p~6-=sN2{@t2!y0>$lbv14iI
z$YPyo(Vxv;qz5sVUE3Q;9=n@n{{^g11af!ShYT9;E}Q=x-WRb^G_fmY-=9G3OV}pU
z;o5yRb{Nc-u{Qf-7<|aC-HPlZRyqWlDmMETH9k9m_Sc@UGe$%Bl-;TU{yF=WHY{GS
zLuhQRWA{-c=ry}<I8@%TS2qFhp3SEy>?gJ>z5bus?+3#RCoZE8gqt`O#pSnfu@!K1
zE4Tb0&40FYlai3^;Qnp{gbQcA21~BoXD5)lai^C7xQm;57KuA|))|_6xVL`;@5ybU
zr^Jifn}Wof>$C+v`EYrs;8Pk`_7$pqfxGiHl1p6qG6*koITWqU;QCV}F_T-KO7Yk0
z+^6Rty}^C0g27wdq)9M;n_E2+Y}uR#tqOCv1A9S}&kfiCU;#IPmH~y_quCJN<qqzK
z`C`s}KQ%B{iCr~i8P}Sok>#9~-us8#$1;>X;(Rv)Udg3mQLU`vwxJKSE33KSa#W^<
z^NECuPr117fT-pCx<ltVS27OC3vNjn%3g8HE8%_}w{sMPZ@G@{)asn^4;cKw9mGDq
z@*@}D9%S|0`b9{bc;|`G+|0MVgxnTBiXO{t{P)!O+xhP^kl3C14?(Df3ol!SitglN
zpTdM2fBZf?-OcCWB!JSL@AxBBJ^0Dnk@Ms;_kqTn_pw9h!*5B0T|d4F1={!Vk+cd4
z<Y%4&SrFfPAA})%U>;OLdGl@L!uhxjsLKKVn{2opY3ElCgrz9ng~AijyqWAC;vHMV
zix_?#&C-tWD_JD5yt*91V|+{myol!;)5hxwe&Td+pW^E(keud^{ersW@lMpG+~JSY
zo=YLWG6nD=e%&D?_xKS%z-|e@vJ)IF<?S~qVq4Dd?*iZhek0BG9`V;#16aX7{vM=N
zypBf0$NZi_5I*7Cb%n}Pe*977p7XyVvZ{Q+?@9;!72kz+E$aBQwBUHdzpX^_miHWq
zntk9~k@=7OrfI0eXa3+xaMtr-_88zd317Q`ZL_f98o0L#9W*H1Cg`ct-XWOILd99Q
z9|EAOu;valcM6U#pt4Koy8$Y@g>N1}xJNikvpWyr{zjB}3D(iT?G<iM1<psX>Y(B)
zwD$)fPM9_x!gwJkiT1xw3JWfwy-o>BDSDD17=DKriNY~@Ws(HD1Im(x83<q~&k4B{
zmrfB{()=}5V7y@|P4N5`xpd*C7J!Swn4!?TEJzf6zaqS;flnF26^goK3bske-4JHe
zD(|N7WH^uaFH2ao5QW)7$VEtVg&f)r$rDn#z*2$0TW}BV2+=cO;;yisw(p9BlKW68
z5r#KGu2h(^1(hfhX14;oTxddDiw}hlG?RHGl+%!2DKz;R!Ybj@Ca_csBjO>f5uPHL
zZC5@OWZ$7pYK4vC!S-C}5rM)N!a9niyb?B4!&03ve=L%>!ucIY-U*rAVDN*`t{S8t
zg*A84&Yy+sA^_@zF$M@XiQQ?Ba<jNt5AXd&H7!p9#9De1g2ZmWLnT;zNF%#FL~J?$
z4HYU*KLYdNVgSuC4~W-jqbX8sDnk+_c1?gvv{=^yxkKViS|-GZrY|8pB3{jarC4z?
zEzXXKIkc>e6G!u~6ffFoQFu}`)9`yr?9dW+6U1KesBWUz{4Q=2?*GZ#NR!1`0g$GM
zsa>FYUR2RKE=}x78yOeGceF!vNjz}`Epu6{Ce5p2>^K<A5RYK-t-L1Qo`c+VF~uLb
zn_^@-a<{|+8db8ygc@*Wi{I0|&lMN#0z6M#nUAsp(H?>byz-8i-3Y+D;!ql}i^Pnl
zs9LdD*A+S?V&!oF?~C<?aKB89{}J2|#0C4{+Cy<zCR8d!XL`IU#W(}tkHrPF<613-
zL?ib}To?(mZBp;~NIa!>qtJ$4QV$pSv{&-5_l0?HsaFXSAF1yPNPVT36kzs~`dtBH
zpEO<vwg71@?Z5>}j(T_zBqdPK7A*PEB6z<PNzQ~w`?>=cDzR;l3zJ-uU@1b1eFH$G
zw897vqopnZAUh=89|PevX~lC||6P}E&^E#i=_b7ZHzh4~v$rI!7n0l3hIdG^r0>=t
z$(9Dt=#V3Iwjjxs_QoU0lNRC_k}_W!PC?63$%lpTzBIWEwSOQfqL5TdEoE@6N*Z#X
z8c3S57D=@f)}GdXHB!N4c=1FUyIchu_}5}D1!G%HEC%L_(K%@0)*(rdv?;!hO0;b^
z7v8p;(h~Ca(`kdh!?-rMcKnON`<*1(?CgA&7FS*VrlSB|BdBq^@qOWBcg1I1d)yiZ
zhMpaA>HX_9kOIrSM|}-gpGAWJ=&MLU4f=Jign|BFxkEDG_*~Ep{09+M<(D25lltl&
z&QK`_87WFSSaTKEAx-H#&d~A@=nOlEZ6W3G`|V+PM3oQR`mXzzkWcTNf#1I+(*EPx
zBkAC`Z)R#nz?of4a|^Qmj8zN0{mhMVpgh17{tjU@<3soGDDzV$3poC{vQ2kFZ6{kr
z{iqw8kpa`Y*h8rR?PiD4;OEZXbVb=7)`!9+9&9qja6Q>`G#&9`W4++PUiOrT{a2+o
zJMC{sec1hGsQR*ZtC9F&E(oIm>{bb+f$Zz95bkHcI*D8eYo`EYDBH{ljS$ABEe2Zz
zTS5IwB>UGoxE96QqfvH{?KT!=(QF)TT^(XK%z+n&+4b{aHinI9B*Xnb!fyN%wLHoW
zpe>MCwm-Iol*iZ~mcih0*5w0K<JhJ%A&h5F%3$II>&+uM$xe0#?i5@52XLp^sFx5X
zu&y*fC9;?9BRRu%T?%KC*o9tjJDKg^0-w&Z1Cmj8j@|p3_McPOUMC?<V?}DH3+xIV
zJWXc>I<9n)T{sxROYDz>Vd66T%n#07VV~B(?p1b6AaI$it~X3vV<Y~XGoMGR-(Y2(
z0KdupAw$_M)*^xBHhZ`qa#^e~6DqlEFXFW4v0>RD&1aLGkrc3Zs8_widbB`N$i8R}
z)w^sDis%%vl?ssFW6e)szL=d(2W(2%Y5$-}OWEq~aOOU{vISVm*l{~iR?eDB!192-
zN+H09?Dom1*&{Z-1?*O^^Jx`SX=lC2ZWX(qVylnYOj^=avkBDrHSFa+D0{-@S&)0m
zjwylpS~h+!l4tDdb1?Xv9ZpgF7wm;W@Zu#a(JJ>9>rMwu>R9D@7<|pT(5bjLZ1+}B
zdC%70NAiIkpNz84ti6#BRO?wU+EsVrYN{dK#MRPRwv8J?CU$VY?Lp$q&HIcpSI+Yn
z;CFI?bfU?Pd%hoKySPcTr@5QkNKN9-O}&ZS9?o?EI6b(u?Z|m@Lus`1;?|V{zL)!s
zo*-|o*uEH9Uv3#iA^f-u@@*ft={$T2<^G<FB#c|^0lVQ`)>l9r;J%=tKZ5&<y2D7$
z#-U}SxQdrhImj)Sz!J^Pr%>r3uBroshq*C_;8P5@AsL!SI8Qn!b(HId6RgTuZd^T`
z|2W1iKY+sHoOuGIaon8K0LF7osYy?8^A>{iBo|6cjZ@q_I`nj!%c2NJ0{5i~RZHYX
zguu}=-1b^%CUFO7=8??Z>I3*$&O|fAbKIc=C`;jHQh@P1ci}K{sod~B)c>Y&E)T$c
zfs<`TVLF%78qQqe`t$_pW$w`+uwCJNS3u<|_f<UXW^i3844%pL&c<7HjVtR2w(Hy-
z8ZWSlArEhI=AR(E#dWQQ%5AP<1gez9E!ht0Y;IgBRC2hQQPltDa+h0zJCED*9dz=!
zI9e7Ia7*d9%^hyjawLVE2c7x5%T1a9(jx8y-O77h+5$LJ%w_%qM@zU8Gt8HAT5oXQ
z=h9DurHmU%L7Q@JIi1aTz~!%iCKf{yG#_!5G052~xGNNntK=fBP_5#Qrox%W+`{9q
zRLv<{p{#~0rX7+eT<LAteaaoDmaXMhKLP$3*D(;>&$&A>0KDMF&VcYG*ER*Nz2XAq
zL9>p_>V;}==Eu@03t!&wH#GhEnJ-YK06X8Gw$B3jxg|(~`03Qo1@i|5;P>-W{echR
zpAJG<C?B-|9)|H|1!%(gM#*sW0MB<s62Vu_MiR-_{)!}ucb^UTL4KnVWYPR^>fI0V
z-_nbIn77kWp`*N?E0S2=&dq=~$M~;lW_p}|G6y<w{P$nLZajZ+A95%7{<~rDB%ejo
z)KmPIw1;$>A42bT0-t;y!bH9+brfg#d6n=miJwDHLNXssbDOh#%tH8dj=y*aNebUO
z8}RddW-lbEe6pRU{Av7Q9QsyX-~)#tN#`FVz?qAD%_p?bCH`a`xG(diG_AkFr^f?$
zm9L?WHG}^U3zba16ZN*&_(wE)U*|j0QIQ+`cXSZqCcl*;skiuh(O|jFkL!;+nZ*yD
z0!Op?>@^h2%;AeEM3KuU(4K4_f0qsw<@04kTEK@ihUy(YasezA^5wsP<}U9z3c@1(
ztvl*;j~_)9E#~{u%%g;FaRHj8{5PYKyU*{UH~ay=VFJh=^3AB*c*KWL5VC@=8mhwk
zSII}mfu@ST`W<v0^FH)kR`W5mfmg!^-9zpP|A=DESoL)Pu$FH{huWU;{oVucoIi~9
z9@c;(S3vlZ-(Qa^z2Y-ym#dC{MHBJY{LkORi#L4FCg6O_$M!<*9luzl_}hEl)d2TD
z@RKM={gGeQANWta^JU;a^Zq!RgLUGXX)y03l+n4cO@bHz(#?X;K?t`9>uANkRhYRK
zn%e}sD{jnoVZnH?>=1f{Lep88Hwew;BGiUL(^Y6pYvrB7S~|62cM}}vqi~lnWhV^o
z7QE?jhPzPX3;Z5Ivk>j&A*_rA&{J4B2AW<%w>YTy2t_}`lCLmsCCdDSSrh@@C-}!A
z@fTu;!<hhKD{%%2wK#;N3=(F#Aqf`pY2e#0>>G>53$Y8@PQZr>nnlQl3Cn_DB3$^x
z1eycFW?Dx?2(7+EwIhZ3U&3ybFqIBI9~2DVA{Q-u>je)F34>``e^{8-9&X17`+FgG
zL|Cl_=TTwBbO>XG$#m%Ln9%kpa>s?9bi6E1u&ZfN6EDQmH0Ok{vH-c0Lcih2of3u(
z0sgcgurQBT!Wjk=1sux7t0wIJ4Z<WLehf&Hg^ExJ&k9eXAv`B6J_F4ZLG=h_=Y=p@
zyrl}xKY=q%Nbir_1;K}6#p%LEJH?|f3a8h@(j{TyAvkqeFug%?MUeZ#nX3YO5V;It
zi3KJy1^o(`xFOVfqwJ<2R-o*bV4Q_^x-GP#cQZ@q-3OZ4!VnWI<p|4ZUnEzkrSr*o
z!r!j2moKQO3oa0bzN7c=j&NcSq=mw#EF^b@;BYuoBut>C;634IiX9aTvm${n5j>xv
z7Nx?5dBEKl`nsa5Ovs~(mJ2Ue0{1|$Er;--;2#goN5X)oV5tyh4uwjkP;?wBRYFKp
zlsy(&#?txUYN5{*u+<3GRjAVwK|?#qPlYx=BUdY&n2qF_P=ZqxSe&1xGgdEzb8mou
zDP&OJ`%19lJ;EA&9c?zh7FzUz`8R?CZ5+K7z9H}52?pwd-wR7-0`NijAq{081qFgd
zcI78w8SPqp7K{{|uNPE9QRpN#dkYhr#9BJUx><bl5yCBE9v#8hDqcK>+%|Coh0(W*
z+bPh$Lu^I6+s>ly0st;z8SR(3i38^YuuFV87P;NxQwolGh+#Cl@)SSQ8qn?~e#A4S
z^bxaug^sWIj3NzwVjsGr0ph0jXuUwO_dXzk#E4Z$LPYCam<Sbfw!>hUm^L2`6d|T$
zAQvf4uK_MfoGHQXA@R)|B!|USM<9$5zoL2I5z$70x1-`Z3Q5M=#qVehaZD^c32%;z
z-W1k~69Z?$(|EDNeyE-h&0(N9DT=hqa!UN3qCKa@lbzvAf;c4tfJE^_43abAwF@Xq
z61O~urDSpN8&IDWUmr*AoH+X-+)feI5212ij2(;iO%?4wSfG<8W`v^fg1BS^?52w@
zj>ugUf0+RnFNtwc@Zz%At2<ieiul0|fU9E72$;_hS5Vw8QykYDq}RlA)URI`du4(9
zhIoZ$bvMO?*C4wkHeCS^v&9i3k;@TRk3f<u*4r0@J5Q|J0ZaMf&)q>&Aa;3;irx{g
z%?G|v<SFiOS4=QNrAUmX)zLlimn~2!7NcqBv_$-+2zE=w=AA%xU+hx_K$$4p4u8wV
z*A)DGAP(vd+(WT~7Aud$!T^v}h{F}M{;L!}(b2ssaXK9aeJq}!C2zGjo<muUcrpN_
zPsHkz5Iz;>_yAZd?kI-vnP^@Nz;iK}=IJj)#acAUOR>ZNgRev<3We5*{VA;UTAVuu
z@HgU=ttfjdPH77d--#3cr1;x=u`@aKLHv_;j6aG2o+$hzMo|dpv-oEtG*rFVg7$%&
zq-2UtZIY&U0ARE9fI<`7q|xso+%DBu!Nd;9Ot;Bd`b6jdU8LFqIO-~$?*{6f(w4!%
zxk)NIp0!JAgeAFMxm)V1gpRxP69s$sNbTt4pNBMl6}Ua6FbXz#NqwdQu~+Izr&7En
z3&jC^B%um+eWg*f`{pN&>IS>}q*d#|;x9?GBM~4yl>iTvP8C8JBz>ax4VH4~vDz<X
zdBTD{L@MH8K2$2|iAD^Q*3N@YxYU(q76+thbbKd5T0*B2BBeO;B1&rc9JzzioZpZ{
zOMi`nr9+aMdWgf4#~lD-q)#_t@QC#Na<CkgdeKS6SSj)w2#-mpBvj(Kba@>N#o47g
z>eu6?p%mdiA=Nv8^t80SF>(pgloudPlqS3Y=^5$Uvq+MpyTzzevUFq>XwFJgZlW#D
zNiU9oEk#PDc*uEaEFH2<m2xQ9lqP+oZJ7&FV~T2}OV7H&!bRzJH~^O<`-~n)FH0Gn
zfw&?SoI>GMX#`ELGNcuBYAjPq$^gwZ$&0wJOG_q0^M=IJ&iGAfdJR-=Nqb%3#cgSc
z8m?tYMe~tlOU<Z(bEKuzb>~X!KSDE4x}1cve5pN+e+AMgdw&?bBduEwokB@Llb*X$
z@+c(5l6NTlE|H$zgKDYt%`7D4(w98S9!S$#q3od)K|Ncg6mSSWRY?)_kprSzG`KyH
zyjH;AQ;ACeu2%Y%_RC&K+*sIqDNTrl<}0cFNZS9clU7r=^;%LGk$WRqXfpg>no2u@
zAEc%~g65-iozBpFlFSS&eU_HeM66!gFNYUS>ao;kZ&Lq$7P-ypP<pqwsB`F;=~i`{
zW`J)~@7xH$cJ-e$dDx-8MctLNy8gC^_s>QBt_Gy8>Zz|$xKrJO4xYKGUtLCSm%3F2
zyx6TC*%)|t^{EM9+oN_0gQFhm;khv3sScqigO_?;SE%e&ulpH^w|c}@;C$2}OTpr+
zb~=EZpZanyB>U8Hbb{GmZQsu0{R>bRMnNY~J<f(CNG%TsX|Ot|EnM8MK2IZ0i24Yv
zTSL`@HUJo=o<=)3;p)p2Fh8K4L7P$$>dBqK9jUfcygo`DO^4_XsuRoLXtY|n0PsWV
zqEI{~ht(!JArhm``VIj55%mu}QFv5c_!g?M>YMaoQk=TqJru^PH&Ca0LY@0944zi+
zq2pBv>OaY+MD^jLU^}DkO<&F=sb`;pX0m$o1#q8LcWpv%g<9wevJ`bA190cnxBmiX
zsyg};0BLGPJ9vM=uC5YbK3y%4!HepLE~v~UwM3gWm(>${1Aj&B5{=}l`WbC)XQ=zr
zIi^f?vyZ@CQ%|zO(slJ>8aHpKr%`n9ruy_Gklj*mj|SOo^}yEfDNFqa9cs!}kNyft
zj=Jq(l;x`J)(ue2Q#(1~uH~!S9so^&x;wSyUA5P*;4V@hqvz_LdLZqv6|3JlKv<$~
zI|G`f>hM$~<?6Q789Y!YGz4<hvo3(_se0pIs6?%L2??L6b0{wNT%D5-mKW;W6mY&&
zcd^q!l~?NgTIkfN<qy$_uhp&FpcZe`bC<%4x9VEj(RinxN@1Ay>P>$k_d(sC7Fi$F
zRf~~)Qcv%P<g+^dF3RfF1M6VkNpmg&fK8e^c39f1ai$&hEt<^~SKX=^Po3U24Zo1)
zpW8LJzeln|6XcAlIcu8J;W!tKnNFy<YF7RUp_^uFbI|P4c=Z73Zq0)%w4S>r@K>np
z(X62t-b3?wFv>hN^OvAXUYcq;V76ED>U+56tx-}0!beji2br(tYIoT4)BMl@yIabA
zntcl)_1CPYqeB6j&yJu8)O1cmE=c1~r&oeC&s8AZuUYdW{0`B~rVm0wHAftf3)9S?
zH$7bQog)ATH0Nk`7oq7k27pM-)*)~^TH`eloQE`hgOEF{nSU2P#b}}%GkE`wXfy^O
zj%t3V{xw$9k5*pCG}qjqb6hhc5mk%RTyF+1;x)=K$eqyi{|uFrnz#yhaY{3mW~!$(
zl^p?3(9EHuN{O02wBdC|6G0J#Bu%{xc9S(DqX9pw*-T^VIZYyk!t5!U8Qaj7=QZUN
zvq;s%QJ6kW^Y{@8FK9+2BbTmO8UlkCHCJ~5e@SzbmXVh=5A)G#S2QJ`VE3wqrMsP>
z(bMRXso6x&@ik3{@ep3u?4#|z8=Bv}z=`);55O&riwZv7wrjqpnPZkFZ8bd2*0dZ7
zX^zHq2ZXtr8FZv2Pvbx#seFyYMX(iUO6gcap~m-bcyU*Ag$`U5Y1$5lhxarEfxs1O
zCejg{5>3wz5SD5_QAqf{#+^=>mTBJ7624s1mFzvx*mu1|_Ms+<7Q+>qCJnnKnrT)D
zt2C8EfOxD~_7XJJnzuA=*JygtL7*p^6bfKI)$mQgU8_lL5BM|9z81(m*K{m^+b=Zy
zN8su-S7<PPt<ljK^+vOqTJ5cd+YGngX_naOu)%vxG97yRpjq}U{QjsJ-WR}6nr&_%
z{j8~<h1%C^=0+iL(vGBN+oHuMZFrBgv2>zloA!&Vu)AG5_!DqDv?dp@IBTcV4yKD%
za|bwA?b;tvrJdScJT%?34z$IvOFKB4-oM@2kCpJvL;C|QDm}GPCxG|Tx-5fFd$o;=
zV8UBlYDKkuv^Q=-=&N0I3o3rv_Y>g7K5bnX5`XP#>R1D``4kli)DEN|MUa;J2L^++
zK~*rgU%Qyjsf1{KeumjlZQFbr|H8C$XsQ~nP4$GO1KQ*Cv_xp_6lIUp9%_a5iqcjE
z0(emSWDD4$wJu*m^N`lp3&~-vbv7);XeW<=-6L8zKd2nlhEhAlYTfI=a!l*#1`Efv
zVejB*oVJ+uQsT8Gz7BZ*PH6q9*E^~0C_s8jd&3=w)7p{rd?aYg_P~6icI_09p3(Y_
zf@?|t`gBe^R)Mk<?a+7NKCe~KLMT<6JqNio?L?XmUeJE(1eSEI^EOal)aHK$LzlF(
zjIeM;E6f6!{i@cd1DY*E>r0(yrZ)UBa@Vw-4gz>xyKp2_Z)*FGK<<`yi8C7Ew)Q=3
zbZ2QRlwix&=218#N9#ogdh)fWj>B$&c7Hc`aYuWu4TOc-rA+|1t1X!T%_8kzL(p9J
zw6<1&7u&U2U6Gb(-_tHxsn-4zJiV{&PJ3x(+O4O7DAz782ipVfOIo=-)K+{0%|}`}
zjRzH48}(C_+K#lNSf$ORP36bh_jC)ZwV97mr5bHJdUT#>e=bDwRO^6UMrEzG@&N$P
zw00kgvOm`f&*0Q+ZNGW|-)I+8@a(O&)nf?XY1>l+z1P+@0ow=dMhZ87)Q-Oj%}?6>
z6#n_FUDE@(daXzRCtdRZxVA|*sTImL>w29>*%sYj^hxek-D8@O?9g4H?_HdA&+SP-
zxah)Zg5s*P)2wu-&hi#6y6N0#O0i2fs{+E^I@c*k+;wF%7<=l*jD|B_y6N=Q<X&CW
zEmX!^_bu&?`RJmnk@)J`b^xcJ?gj0W?$hn0m(pLiWjr_obi0#L7N~1oNoQz+bYIX0
zK#1<pXEboA?l}u#m~K}T5aBwWdg24RCMS?Y=w3)riPY^`jygr@Dkz?DP-ou{gVDO*
zs7Vj$9@Ig2SeN+{l{l))!`}!|#_C4UN4Ljx&Lg36TsN44ZE?CE+tdDEyl!YcES=Du
zrfrv#x@}|O@G0F&f2f|;1@;76g6{X@@H<gA#|dR;bVfRmlcckjfIC??;v4vsqH99i
zc;|K3&!K@+bv@_+Lz>QUF>)7lk7Y2Qt~;_6b}#DI^#}DO-AH`RZC75_ndq>2hK{5D
zHB)!c4cyms&FNLUt}D3@;SJrGgAm@-jY|XDE#2aYXp7rA|L<ToOSg?y<k`CZnb6G9
zb$kY4u5M&7Ocdza{{+AtUFj{T6zXysp)PlIYdQm7q?=FiTKhfS*XxiL>((<sl<1N;
zRJ2q#`8|O5b<-r+Ez{vxD&7O#ls`f9NS99Ib%pNNRNyLg!RG*|(#>pvvd6mXN5NgK
zYa&OLYIHVl7<{73pswMmZd(g9Nv&@92MC|(Cd>lobGvS?2$~l<*E{h0rEcQ_aKF+`
zrRmihT?-0>zSX(YI_{lrJss$Iuj_XVY#(&*9U%OuOQC7XC!K>0c0cR3(G;j&Cq*N-
zS^ot+t6TK?wNTlrKh+#%+w>D?gx;>t^nh@O-rfd_0Hw43^g|T7=!bPh;;L^)Q<<H5
zx9KQz(|>y%!d?1_4#@4%`_XX~5B;hmaNkpJr-_)CzK8{2uYT!wu<Nb=ViEv8`a0T#
z_tl3Tg^Hj4P%_~A^dsrX_1DX2CKRC0w`W5qSRX~7zwOsMzXC8sKZD{gq531V-x;PC
z=@AImU!Yal0sSXx=Lo$Ey(5wO4s<vnO8@<5kRH?zu0nG~>-UDiV2r*i9e6yV-+u?f
zqxvQ^R>bOO?g8~N{c0L8kLwTn*<m71zxPM5#p`=-gi|N<|Ae4wr}a;04w9hHpN?Fj
zK6)Hz&gj?N13pRr>?$;q^(qROp4CU!fcu=@HXnc#ed<MUpVv>EizHRwR1TFi{k4Ww
zx4!o<uw2sDUP5wNKff{UKU~rG?g|rE^(!|Z$<S|q3z|&*4mzZ8P5-(nT)VEH^(_qE
z&_8H|I^ERw=?md4eaI)6$kxkJkjv2*MWYdN^-Uh3N%Hhln<JO6PyPZb1^OU*knZS*
zQBbB(@8klqyL#JCEZ)B&eZm+Z?&;_51WmF2F;3+x@9QsW;Y^u+4ejxj>qpQ!?18>&
z4}cH#<#ZtKk-nb}fC_!}8gN(YU(gU+rO$r{VU0fXJ2c4?{ok~zda6G_leAiWVmqij
z(`Ro)?zvv`4Or|i^ywn%`%)k62E;49nO3TG`dwBOzSgIuz_mB}@l?b2dKZeMf6&Vo
zpk+SlCvOJsliq&~%0BBWMuEFtA4@x6P6kIBfHoN(R6@AfpriY`#gO#_s<hSchEB_D
zGpwVzi;LaRW*YFWhEx{jcN$8cLh5Fy$cEirh98#zzuQo%g^Gt^8ASp-4XYMF=w<k^
z9aQ!j-qM#N-iBYPXY(<{ML_6lQ1=FzpCN1>H1`?oodEYYxJ`!L0K>gZv}mB=XL@mh
z40hEN7z{StquyY@VW~56A%+38{0ud?+yiNtA&(}m;f9X1@H=35a~-(|!z&t3A`L2<
zDn=Q8PC|0f(2ve2MH_lw0`8EZ(=~7&HteD3e2k$HZH62%gwRIGQG<ZLAf${n+_TfG
zdd#qQ7<@Z!P*Ti2&Tu0INxb3VY~W8An$nc<q+ziH{3%1^*8rS0v?@iN5)8#{P?l)e
z<O#RW7}jh;wUZ3*79vSD%%vsMSwj@9wayuqbOc$7;WkAq&l?ue4o9kC!&Eygr5O~1
zpmV{nAR651hP%`^Tr_+qKzPaUW-Pcb8~*Nw+!e#uOTm5BU~B<=hGEny05T2hE}-n1
z!Jqn)>xM2tsP7HKw$Wg@X)tbtg<FOzQ2^XFeAN)3GE{s4mTbfQ2`t{f9K-Ba(8)El
z$%myp!(%@H^9{315Ed9F1_5}-(BcGgg@%y_(fD@_Cupm@$S|7z{J=d!F%8?rhIVyO
zDKWJ7gZWZJ><u_`-_U*}RLTtH1;CXX0!KjQfg$%PI3F77+R^^|Bf}eCASw)f=;X;`
z!=uSitu`#9Z&hjxpJ^NZiDCP%NS+#AH$qvhA&rhUKQpLLq1w+4uPF%i!f>=R>h#j^
zSq-vR20j=j>I~-+VeqvfnVS2Jq0S#Zy)|@>MDCrT$B)3--y6>C2HOY2laVm^(QqUb
zI-d-ySAqMpA^aoo^@ge{)Yr*aEaB#DGR9D}Y_l<O5O7<Jp)AU_8V7F#ZkurgO$WCd
z4fSwlhw*qrEZFFC2j06Fa~^`z)!4cK@SVnQhr<guyYWg}(Cjk49FOd7V~an5cQ-z+
zh3X#T0BUs)V_+Y6>S;Vce>%g<_^u0tdyR24P4PA^J_opuQAVV`#$f8+{fxiR6SU9x
zEiLN&jsMWm^8jN+!xs(4m*Id183We>7i_e*rs>&!V-&3uLX0-*XhMzG=qyo~ap4~1
z!i}@2z6XpKX_ggX{Btp?7HJ$9j9iqlF@0Tf&{#n6+Gt~Be<X*D*V6z$Yz(G1HOAP7
zcHWK{@AQOgM~$PLKo)D9^B!f#j4SNaz{ic(et@TO#*?)98gHEU7uw>4@p3J=PZ~$G
zL~_db%{Aap8-MbHi3H;x6r@NrPT7Z+J!5ou0(g=!=q$LCjaNmmoHdqffjehp-y=ye
z=H>%;-Z=d{02hpB$^b|=Uff}aZx@Y==s@`;<0M)tUN&|g4BxI8O*EKaHD=Pul?>w-
zEVwg`VQXRcnsGhFR<9eIt^@ZC<B%pGy=lxzMedeS$^-niabgarvy9hhDV=RRc?j?v
z<4$_Ia*aXM>E#()HmCi+eB+&Q&?zuhb%o9yW9%~I3XRj=A$Qlfj=mKuG9IOY^PX`j
z?Q#_x-D}`)iE-3-$dwwcf5G5=<FRqbl^N^m0WUY!7y*A^97r*ehsLUDu=~iEH5p|U
z#*o(FtTdL5r}$@;F@=scKQ{h05>8bc&)`&=vc_0VM<JdVr}!fG)W|<YBh(rT55tRR
z#y@Gx`nhqn7LD-2SWn-$yfoUcfaR4jk@g+yjAuiTyf$XXLHNeFy(2W=8i%(;^3E7d
zOY!%{MXjJ>|6trpQ~Hm_aS?F;lkq)mTzocG(&JTc%>IC!lWF%2nAl{hV&KJQ6N9~I
z<rdT3y-?X|8h#46ZKl9Kpt9X`-UTW<OrvPw=4|rA3|r}9YT6wvuBLE0B(l?_&4zh5
zlVeA)?6RA>QV4yw>8oJSxSI?(6QtZ@YDV)w57Vc3uz8x6jE0Jr>Dqd*?KOqHLz%Z}
z<!?xQOutP;JNcS|sMGZ`O<V}geWn-N(3F8D?M-+XWI9BDts>auN>9*!)1Nz$3o$io
ziF*)gvX72{G|bffIk>}3>;Hy}2TZNk!ixygWe(htrn=GaBFc1*mXQZd3mU_2v}xE1
z;0~Eu(*)tLsT&;&i80wNP&s1qqd?P9)1WiR#hRr1P&sBgLu2xB6GPRGGwu8h7UE6U
z?G)iXVH!g--IJ!vwC8oo)HoK-oHkvimPs&8+>RvCw6+s8&zLS6P?lu6K+*YRQ<(zE
zSyMcZ<eaIr07;7JGi`F8H@Q)SHq~_c6D*~fdehf}7fc!S`lp-j(Lv*jrY46eIC{x6
zs5^YSY-(%+;)>}>FmBLQ(+mosXP5#g9+7EU=#M&GGkqQi^Vdz>DU{tXMa~AzP1Et;
z!E(zK9E0Sx=>o-AvP^aBfXg-=xed)66GzkLTvH5v^qXfocnM|srX9r;e<?6^rsd5Y
z(<@r87n-7fgfn+d%jmoABGVvR?A$XQrl+jf6yp!qN=!}qL9^6UpoaPTrUwsER%RNS
zj-=ewfxba{V46m;sE4LAv|IGZw3?2wRG7A$g=>|jSJzQiWt!^hfcNjQX*Eqys!cvG
zpju;k{Tk+<m`XbW@zkWNf@-a4z&xltGu@;0{c}?~eXjSylt+*JYg1pE`MohYeGT|q
z(=c~vzB5fejk5Qqph{?dFb(to*+*00SE$k_(~Y*seKvidFCy&qrWRdrOPtK|98_kL
z+530oHk(&$1<e*SzYDpo<|<nFZ8OiN*vxkGMrYu6n1i3f8E5l~v8c9-`H>NctJysr
z{_ZsIPe+-Xc?X@V*kyJa3}<$mU*AQ}-Q0_gQ0y_skux54b2M$+c$x>$yw}Toh(c+5
z&3S$(^frII3G+T?e|krJ&5dbW+t2*vR9M<)4xb23e{&WE2?NZn>FEwM54V9V$b5kY
zwP5q3IH>G5YYR}(5c7Z?C<`^WrJgCw%<qMV;b!|bin$*!|4My#ggJrE$V8fZXF@f~
zJTVHwgJw0&siV!?9AW8@`8*9dhs_rwp%P=BF$FY7%o<vE9yJF&KoV=dN_X;@c{uGU
z9ybSUfirRDItF&*%}2*Uc)~o@0h%Yxfp&_~oH93}xx{Jn&@`|mm>+h9PNI2HM*z>5
z^QXb5B=h4nP)Rng8UVmqbIad>KW8rL0F@N;r85AWH@9dD*HX>wa+IZ+jfVlaU=G@e
zT)O#t`ZVC8`7A}(FPSe+L0vAJ>!#SDbH(gKf$^*6f>7Lp46{5KUSyh+Y4`J*c|`ya
z*Uc*_yne&%+8io3%^Sv{Wp0`M13`M*e9HlBS!ON8i?Yox7eJU}*2O?2*Zig)77EOZ
z_aM1rUY&|YC^VlC;O|}Yz+9St7MTaR!2CUP&`d~+&1za$l$f3AxhgfcUI^fQ^AS46
zR%TYMfluXTcZvx;F#FQ!tcT{Dp0M=D{KZ$mRhWw|psdo&<iXJ@^MU>-du;AX&w91F
zoikKw%ui1M_r&Zph5r7;Q*#KdMr+NR{o(#I^V&!to}0VSj^7J&H(FW0G_U&%FJ74q
z--D*k{MHfp*XC2l;mjLzNHEIYnl+yRe`mh*1IXT+Thlo7!MvD)u^-JcI(+}h+-x6k
zpUo>*16OapRssulC(8yavYRa54n}=9Tkg?;(=C=V1MF_K+^j>{Hp_GRb0^y^>y@yy
z!&0~d+|CxCa&Ws?4$uiZS4$4<^X#-N@rU<rmaVkv-eoZ?gXV4vOHoO8%d7QJ*<<m4
zjl{!JNMCV#+AZ&C>)FfFYAtm3THGlR;cc;dLFi*iDF(N%rFkOE`&o`q&$iDJPwQQO
zOI#6D0xXs8uoP&~(x)mx7Wd{L4Ym|+gNgkXhC*;5mg;!GLoEUI0EAfvHH7snws%lD
zV6nHPm{f%2^h+d>mW^FtBFYl^38V)tbHd<Lw51hwNrx=$ZBRLEX*mqJ7|Vd>sOS+(
zE7~19YS~O|v6egY061oer}h1Di;xVJI7=dZcN1?}6b<1COTT8&JZX{sK|N1dy4hbq
z=d`5{#iGwx3TGlovh<>Oe6r<m9?H&I%=Bkd&soX^Bq^4obl1*Xa%h5{YI#k=Z<^&F
zE4;X1=}muLGu@)G!HbKQH2Qk=lI3R#6kWFT%?9p@rO6|Bf7LR!IdU16I46p~WLkRB
z_<7BeFa^2mmPvG`?uKRJDX8AG*n-d&w=6sVfNQrcz5YU3mSql|{mr(#FvEO~C7w2R
zb1f}~BgwNIyAE8wWi$QV&jL$2efxCB($)`vLd!>5huyV2a6ws-Wppxqe|^s~!V4yf
zEsACUmRP(mfu_`QbQap{zNI&PDp6+neirPOTQI4_i)WchtI3C!iuF)=Wbvd$e}(1h
z1mG$y7iIuZWoh?2a*r)pw3w{6)KloL#v*5tJh5o#2;x&qH$;u?%36z+Hi({C=DvUz
z&n*KgfOui~L;<~*mJ(msePwBO8>DrXF4TRzwzO!2TD-9+XdroO>DwF5ytB-`41@12
zqsn38gQdeQnD}T(H-h?;<+nnxe6~FEgi5_d8;vq2>xLC5vv0B%&=O{|_0<!Y-(u}+
zLT;-yUyZ_T)(o0pY`2b^1jG(&!dX~ywyw;Ec^7M=Imo$M+aHI&JFV3%k+@lx{RrGH
z>thNq@3yAUddS^+>^1;<th?`k+QZ7y{*b5j?m3is*{!*>DBWw#ppn|!+Pwr)AM3NH
z$oX3PbcP8(>!dG%-)Ge%z(k;RNg!$wWF4kQF4(%TGXVRoGatjz5bO8!riNPcDUc9m
z?N7%n!mW+x!tMd<OFBmxVcpmXNu>2t2w0-5_8=L62dz$aG<USs8%qM^A*)3V{9$Xy
zJeY{FMk>&HN38o7AvtO_HbPmfwcicU9J5B~L37;NmcBoWvyPx{Hr~421OA?{`fo#W
z(%LZzfKygmHsGhN^OZ1^VBJh>mPG3YJ565BSZC2%JjuF%HgS@zW8I;1);hHbxX)R?
zV~|U+M$k7|=dId>NK&o0$HP*Z^#~oczF>`73tYO@i@LOn)_RJIU$U|TVfV6iQY^}@
zSa0q|?yB_;{VkOYYcK`rGp%Wt==|9=>yZcmuUqd?$p415<yLUtwEjeav0K)0v>|-k
zYNNlok!2ma3C)#l)is5Q9BUM980K29TmvA_I-WYOd~2QuR0^zf&%odv>q`29vCtYy
zyLor5@iSqe$lC8R0Qan4AEEKD*m^w_=1Z)-hk&irs-$J_eQRhX*vhPKiLg{|WnzJN
zV7;>*+z+jfX+!vtb;TSc71me8R%x9*8YZf&Yj~J=Y#mt*T(x!UA#m1MOHzP)V%^aN
zhMrmj!%<di{b>`O|9oa$R))rS4jQPwu<oG0rts3Lpxw1s*60st?mFw=w1NKG+Nd7F
zH`bV;@bIlQc`EF_v;H{*fcMrvx})raHIRc(pRG-2Ay;p$rJmHume~{*HrdV`gNK`K
zQ|T1k7F!!y`rEhK;5}Y7TW<=NZMPkzor4{=>Ln05+nUlglZ&lAO(|S$^R7T;r!D&#
z47%ACm4JJfZLtL^yKOd#Ou5^#C?2@Sc8Cssde{oThZml<r~Of1FWX$2k?gfy@IlVo
zcAXZuK6cx0O1R-`yYM3n`q_rj#C4x-3Vm7PZ}V%4Y6sYIsGAM61@IsZvdyK_Y{9k@
zv{>11`}r<3Lu_+L02gYzb{Q;Tw#JpP6mCo13rh!Vix(k@u+3}>l}OvX1As@_zU+eJ
zpv_)Me^oi!mTmyzkZsOVICa?OO5IkB?OQp@j@TyCTI;ASoFZbeHg6t29kVT?1GdL)
z9?OA?v%RO)YrGBTcJbobwDiXbPTKa<DUDOMuc#9`Z9DK2>X~5cvKnNGwss!@KVzF?
zAA)R>P4Y#OY>OC$<gD#Atr*YQ=Fn0i#TH93!}GQ-y^*BarXGT&G+WelczD4Uw+JTE
zZP#hqebHudMGY_6uF&%FvTY=7l3lUgYX_FAw#GRypJ8*|31Oz~P%#W$vkeTP_1|^d
z3##u8+fABD-Ly?P37uQE-Mf&xZA(_7EX!6zhb*&gdsd<>$96UxxLliU4=m-`O1B}&
zw+*2XT7m5%O=j=dI?)(aXuCt-?%uU&Z^C?$ZAv)E?%A%5hfk%ps)O|R5ANHxwm~h*
zY-&1$UT*938YUjth8F|)&^CtxYmaO)>b)v#$!_qw(sq%C(JI?e20lHujl73kwJm8b
ze5$dfEJp5$E!zX;pW52=1iaREtQgeKY?tUWhUd1_-4MR8`TR`d-%DF01vy^X+MPw~
z)!FbjPw=YQzC48FjqRKU&b+lPr!QmQ+4dA8d2h2&Wb1=%DJ`i#+Di5y`DAPB27{k%
zZRsy))Z2Q|K<(rxP<OY<@c;#CH#@GRKiRRxu|$u$Y;_#=9yt3p$5a|dw>#ReqG~%F
z|MrA$&W`oJpwPu}0BvfxI<}xgv^yPl(;U&wF_9KKyBsICho#+)Kl}w!cSlKti9L?}
zS0V9moJfbcJssQ7E~J;^Lm9~SI<{H|YH!Dh(~$FV)KVbc*Y4Q)5lH<UV;X^NpW}#S
zK=?a0z7Ns>NBMZz4Rnm5uU3K_-D%Af?5I8t?){Fdz5pP^(f18<p^nO>C<}9({3pzZ
zI}R#^i35%d#Z4m|M^LvO>3Cox+9JwvXC}xFI!>crE85YX`X|yuj{P<OaoBOjA5e{P
zESeAQBaWpsp*rf=BL*g79lK73`^Owt9|Y-fM~~SM#yPHg1JZcMq4VJH2}ciCwBbp|
z;39CIa=b`e^r!znj;=c{%j%1pqs+{PHhA~mdzI$QEGsQrwyn(4rv1vwOnqhVA&7$^
z2*{G9OaVoZA+k5JWDh|$iUat4Pk)`yz4v_2IrqNLbH_R7KCjKPI<#fjc$A`a(dKp=
z+A?iQ^FXp}4AvpkX4?$?0=<`PwxvVpWt-+cXv(n}7sIAJn+^&_UbWE_!|r?=^%k%c
z*yI#}rO@VYPZ(2V<4tk!Yc|()U@5j)OWw@uHv5afSz_~r6D%yX3F*X8mf74Qr)IfL
zO$z`OHvKECFu2kthn!JWHlY+Dt+tschTa;RZHqx_ZSIqoq0Yv~78cgqJnsya2AkJ&
zAiL4V^G)Dx*h~&UVUta6D*(+l|G2^47Ml?xSXyluw4rIUVH+Xkrp@*YaJJiQjfb!f
zn;$=>^{><B0tKeJY)(<$T(?aUZSZ?+KAT0U*JdHb{rha%-vQ~j8Pj0625gR3!R%W$
zx5y<tXw%vSGGw!11;}li(#v2Ow)ux#79%#%<SQJtIYHk$8napTDHM&{_)o%^37eP_
z%0HX5k=})gQ#Q|29_Aez)k|o+Ytvl}{Irb^;qTdGNTKk)&5a;%KCs!tM-Ly`q{+~W
z8JkKYO0za0%b<SFri9J_M;LlKb=xw$D2v99Vf!tH+n%w3PTdZSL|Wh-89A?lSe+Q!
zejuC~J`|OAVSLyF^IaJ&6rXZquqa)^oiQ&BEFO%)uh8bnFq0G6i}4bDrN)~PK`Vz3
zW5NtWk1~>1q2$Z3ehC&o2Jc^#jxoNVR3v|fABFLbGn}$82qzfB<bOG7WrSN{=_$tF
zwAKVLcC7+1kkP#dr67iiw(Y@;N%G{KW^AQMMF?Xi5T#H?E3Fl07)o*mMKJEtoPCy2
zO@K&-O$bU+jK_Rob~NKt@_fWF+HGJ=EaOAkC!Aw=XP_;PVSSPbqv9D%+5jdn&U>Jg
z$Z$IVo+L&tecR+bV~Rrj7Z^QcXfmUQVlgR<JGAnoG6WqElg8NlJu1@~>!mOzgCS`G
zxyaB^EGCoDMUJg3#;&g*C7W@CVlkH(f~SGI%*e8C1kGWj@L}Q=MsfqjB$qKvj?+9w
z2o2&@MlXdb@)=q>br&!eJA<>3@g{i*iWo1@srwqkGY_R=MiQ-}*BN`~p;W>+MzdBa
z;|F>v%NYBM(ZO=YzOw*SFlrPKUCHqHi}J6l7{#M#tY#!Jps9wD_AFG?GCm}KaUFwC
zuVFo7Z6$yW3}0F}8yQXiMdcW4$tB#xD1Hf~nGs1Ri5AAn29Q=p0PS1b8159^y2)UX
zOSqjOqew*ugA<F&PDcGW<-c?>UZiZeZbp$mH1#lEqC5S)44V#+KE}&*YUpPSPyl^^
z!J|a1TMS#u=pAGnKLHg(3`A-1;xRs^ll3rTOBPs080+*XjWYH=3Mpd@?*p)DoU!pB
z6iqPxeICY4GG4?JZ(TISI7NZZJB$)Kh2CZ4R|7H4*tQj=dyH+a5ObgLhb!!Uz^EbD
z!$U^7Em&q4-@J)l%raiGh59+hkM<x(m_szcwoC?jOzfC-$<Soa^!@}kIWa#YZ>BTz
z-+O3tVea$>!0O60Qi6mVb7UW+xifRf|Kh<syc$4H<{1iRdNJ>kE83g+>dRp9VTvDz
zy+@e^bg1-YR?s=ykNFn8_s5tgkHc(#<`)VmJkES+8Kj(G2GJvXk~xpgL#LRL^xg(A
z7sz2upq07rZ72+4rjlnXm>HM>a+>)`C{%<n_a_1o%KT<E5NDWw(m%a~F<<-`fN-Xg
z+&>Y_RLUng%lwY!ut=tfW{)UlOEv(}%nxWU9>d%g0b^pBuWSR$Ip#C8vd1wUzlYiJ
zOzUA9^#tb50{|v6H`A#*iMfeB<8_`nMjO`)%%m$I$xN3R7?Z-R>jGygbB4T{Y0UZL
zu}o*~{tZ$xm{YVzyvRI24{0W|i@s%)#e91LnzEUOF;re+dbC2=Wu`0rFgZ+-l{T(d
zm@d;O<}z1pf!;i3e=5jT=9d(?%V(aXQ+EOL;~B^<WNx8r6h+MBZz1LyGn(?qikX9J
zz;c~=lCm^Pn0x3IFJ($-O)X=}C|#kP8AM@|3TCtm^i?v~(IK{qIrkdH|Eif=X^pF4
zo@j)$T4v@$l<Jr#Xq@YrPtr5jz<hoc+8UV~+fcf}6sXbrCgxr`<uo&w2vKTbeliYC
zt<1;e=x-adlP=EQWG<)ELOXM18A=^Y)(l7|voaH;iy6J1;t$<S_fd%HVg8U0U_W#A
zJ*XI9W*q{##oRT5%0cEz+BOU^!|3AsZRWbIXd7n!M!vHVX81y|j51$&AHzMyT=xx1
z<IItG04A8PRD)%bY4<)XoMNW;!@@hvHoCuem$@9znsw1M)BYIL-(!BW7LE6r_sNa(
zfO&f}cpfslOu)}D-#QMKS>`L`*_vZI*+SY8)|qY)TUJR8Y_em0Vvj!Avl`dHGzZp&
zN1@)4H8cZ&6YH7zsB~s^<9fg%7gl}&h%4*%YtUzPWBsxjvfWv>_ORQ7b!7vjd9u!x
z1L4JrF`?wm8fAjThc!!qmZPj2%`nZE6-Vx7Ki01mkampqq797kXDMj=dYt7ZM%xM2
zS=y(cWc6<Z%PCe9t)c;}dS93p$a=*YrUhA9J3oNlU{>xIkbRo<LlSx)!g`4ghoLMu
z%kko|^c2DhV-=E*Go0l{0pSQ%vKY9ttgG}^MY2{dhU_SoAI&h)ED7Bzk6}Ger|wu*
zG-c+UW3BoOfH+q65r~dwWz)Nvz_R{Pfnp-7-vXnOSh3_!JkJWHIpqSY;1TFeX5GC5
zlET_W9+y<sUO#9`V|}y?n$lTYuY)s#^#~;cTx2b*fRs$uJW8|3Vu{FyoXuK65xYyQ
z^-2IPvy!R1Ijn@WXuHCiw!Q*0a#>5r-Id3ZiD2+m)`8DZna}F{7Sak>>&KzKko6qB
zTtzI87T9~8^>Z^SOIS~k^SG3?)*F>&tnC~C%2}I^0A9h0C`PH0l}p($Rjf}f;H+kS
z>jzv7YxEKTwXCU5E6k{4G1kJwdRCS<R5Y-7^insn)Gg@K4ORo~Dw|jp7tz+t`Xv~E
z7S?~??P_H$p|_%q#e5$sZnCzLd%d0YHJyGtSYjr+)XA#34`E%b9hAP-&ALIG{~nfk
zBieddFa1dCUmt5Rb-SPSH*F^eSjmMz++uZ7+Uy`JWEl`cEImb5Z?k?N_v<k0u~*PG
z!t$W`ag??D3i>pLM0k*K*83rlGQoO`_K1_LH=cp8Db}AqLc<+a;^P3^Wxc%}EYqx%
zN9p``k5$|bp8Kr7X@~uQWw{SA4_O~;(d`-5H|wBxmSw62nPd6uQF(;D$pHXc_L>j?
z?AX6d!$N!ZQHq>7us`sGUPtzm6a{f&$N2)_%yy=*mJ53^`RZNS3$}r{v90G(X?15e
zFM@0jcF(^kdb0b3X!K&gx(t=x?04vQ@?jsMxXDrW1Nvco**_ct@nf^Th2CTA6Cw=0
zKRY)N>W{NsvH?HAu4q8%BzveE#++gw?!#~eurp}W63Bkj1%nX8-u(cjU@QB{EkK-R
ze@>G^2>a|dkWh96<r1A?A0XFX7<(uR>ciQ+v9K_L?f)1C=q#HbhPFty>vpt7v3IgT
zqS>oxYaPR$rcGrWdrK(P$FrT+L0AI2l-xIo>`mloO=2q_LECw@)mjYJ3+(ljQk2Yo
zdI<Ow_K)*nTPk~j8-Qu-1vk-|boRlwz>>lKh=SY~*_D*uk;#5)Cs?xBSzPofo89m;
zgkECff9LS3u@CGAOAg!N8{n?6vuF#G%U*R8qVw1#^uk_cZ?Jlyn9p8ckH!M_X-d~E
zWN)DueG&WE5?FeTjjxeojbn>@q3Jq1x)Yow?6to`MJZcP`4wgCcQT==ob6Ktp%v`7
zM&K&hA3g-GioJU)NHzPVT2$7snUqpc%U=65NF6)nGOd60>}|BHG_d`5LvJH{hz@W!
z*y3&|Y+~;u-$66mv<jsb_G$y#TG?MwvQ!&;up8tiyX!rWcJ^D8LEOP!l@35Bd*lgN
z*u@t71wc1D`wJ-SVZX5z_V%)WJBv>Av7H{F`$zrk<Fp4EU@r{>{uW!13{8XVKU=^$
z#BQPwUfyO0KY)e9>`n@)j<Ay{xHrlc=}{VE=aD~uoc;cr08Fr1^!=Af_MuO~GR2-`
zL-ZZ?ZyvDlF58c$&}sHwx)gYijdT#afA`s&D17pO?LuzQhwM^1j?J(&Iq1bKTbmC2
z91MnvBb<U-5L?c9+OXPjPSZtyd(L<MU~%A7IilpqInG44ojBe!=R0%uzYXHTk<)DH
z%HdLqj2kB*3~+Z&04)SoFV5;t^un9tO4qb~IIiSFJIZ-Q4xlfGMSCYd&J6j`j&Zu|
zf$--n?FKo{d1NQVoZw{9k?SNU=}YwR6z4F-_5(OO=o7wyoEN@>uprLg&9E?-b7K-L
zr#WAcZ#0CnI080>S~;WS_&me8_%VQC96R!%g>(K+12BSP*a*Z~PVRqKQ8-VNCoYP!
zw+n62oE`B1#BieMs{yebn=+7doUOZHb{vQ22`TZM8VZ~zaP~Y4dlNaIQ!-l;M@HF3
z=Q*(#Vc`XiwSFFiCUX+QfluK)^n~nGjvq~1X`HsVpgx^r&_ZYi=cgNBxyXs5wAoC~
zLV6FfI7_KAoAbvpsJO)07X#UsIdz+%DF^BSzrq>Yg34UZfhU2><D|BMT;)WQk0hUS
z*(!jh0*;CN3WXfc6pV8bCy!Elu5nZ}As2K0vW11$IX^l9QNjuPA4;X1RC4B)aW*}V
z%5u(CN*}G@3^f2($+3{zsEYIKF~F-iKiI+08jhSiHMN|U#bBx9EGL`lIfE=K)HiUR
zejhxIoaf2Gb%V398~ttKT&FAg&74;$YTLrO<N|4}9DF?-FCHiLW0Y=kmb{K`w{zH&
zfOl}_q%f_M(?)0LE>2@B;N2V-`t)KCCp8u<y_`P{5Z%WqvB${tbN-q~-(MQw_$~s^
zEzUXmcZESt%BN5<#7Uuu&~47^H(>WDXDSAjW1Kzzt#O=W8rca>&orb>a%RZ?GR1j#
z8t^-u58s8ocR803DqJ+pIZO`Idz|gG#k|j1LBa6{oHyTrzK5LnF3LZf;k5q-6|<c0
zegK){#IFX=5$?P1Lbfe;0ew};j{99Gh&}hW3W#ywzMllVBX=)tkDRzR`2aX`vww$P
z7w%8wn0Dn(w4%+8TSJ~*cdlwVhzD0)1mek!qHDBX++lLWTfMpeqi4>CyYyFxIm&IK
zji)bn_i||R<4({=w~le64*}uNZKjFlIM=Njnoe-1s)0Mn{a1~)Q(UJL=x+emX#}`H
z?z{AE2XQx2mx8&mOpw#ue`re`!YzCZZK2#-D^WUQ<rZv2V;FZi^(ma2MEi^g?o*U5
zah5Bjg+7wYp=m3Mn?NVNXzqFHQw-OcvKC^w@t?rLbKK>0=85CBQ5Z0un?kPH1a2lh
z5Q*H+Db$d}^`Qm+JU37cDHpgUlv<O_wSGjA$`o$+Qdp77ZKQP}jT?Ik_;l_s^v$9S
zZr~PJagp1sffbqDu;l<`aU*_*rflvIg|{wo9VkoxGB=*QM>*UfI?`U@t|>=bE|>KM
zH05#U<pX||+xRv5na`ac2+;*xsr4jy3b~SvXe{D-YzMi<Wg#(RQ8D-S9Z0**HNFnn
zCESaRXe;H`(bbMJ?$%$RqMZAP8e%HAJKqAS=KlF7%&y_)FMz^Y?tID&s^iX&0Ir_<
zA{}WPxc4cazmZ!?-sT(JFKuZ5*~GQdS*@A-C1qK)aCcMscq{j(K4@y=eqIdxP3|+4
zc-_u5uYvg;+;<d^-N`*52fT}Gw-RmL+{Y-O+{5*tJ5jydHEF>0aeXM%-p{>2KKB8x
zJ?)Ziaogx4VS`+!LzMqH#C?i(y0^I#&5$<C^$&pT5ia)t5To3oZ(zk3_ueJ2jB_(S
zLE8j3pDx}`ax>|<nBu-q*5Bb~zYk4!xdUHA_B2;T*}C_*_x?nG?{f{CAo>CKDf$S&
zL++3SfEn&H2q;+>&2m2?zrq|h>Ssth!m}kOmM!mK0*D>2{6k2y=RKfcrUS42H<TQC
zcfNuZPCV5!066moC1`Wuz41FNbmig8M0oLd;gqT7&f9nqZ63VXER;NX!+Zd|c%|o{
z-kW!mPTN)=-g;U%kMf4TN24!KO_yB#c*k;3I>rn69|pmn_m2_A9Os2Lft=uNpeg($
zug8M6Q#`#3-~qgqloJ=oyR!{#K|Jm|C<XImw$OB%7q}gqA-rvLTn^>E--^;1o@YFS
zg;{xO@<oU9J~TjK1kch0p0m6iyU>|P-uZUOj^a)J=T707=&g$3z4i!5ERP=!+2?p=
zt<V(5Ya(BLJntmEunD}%H5jKvUIV$nlXzM>sGjHbk=rSSmzM^3DsPr@%hGsO+Xm2d
zUf^x;Wbpp?H5xDSQs|A#<b}3lEVFpUUXY#5J75O6#CxO<<T5YeO_-g-JDvpfS9q~!
z0LbMflZQ8t_ev7_a+RlNgXHr*B^N*ePrC#f3VDkuyj#S}B{#}7p2WHww3sJ4jK=G{
zT@+d=;Z@Qpr<C^tou12he|&<ra^8FUU|I$5GY(3Xyr-UmX;r)%bTqBzJ$DCEYIrj|
z^re=!hWs{lyr!3+zMf|a0-%AHxEH-|<h|1jnKyV{bck)@Menkr*vzxg>(s)_iw9}t
zJxQDCHr~<==;%#eAzfT*=j|j9MhCCb5t=%A!IWUz#WOq)o4R?z0+1e_Zar|lJQkfh
z`*@MRKy*LvWd`&P@bYhi<rYstZl^)s7CQ0_@%~yv`7gJ5cIzN*n0M(e$Ovzw8Jb3U
zLzGT7#w#3#&~e_X4KR3ux8Mk5Px7oXbZv^amjHKoPElyP%X>8nnx=VQq(JsP-e0>x
z?(^bLfjr>#k$>zV?+3cKG{a*%K=dqc`^$9yVUCwy3^7Oen~y=LEnh(YRcptOq)oUz
z|D$ICbl``R8`Y6tLbqF;_@XD#8E5{@s~|4?E5jHdSN{4*2zBFsc^D;kexU|94}R@J
zDD>oixe3C&_`P%z@#Y^u++&dse|Z2{tVj8q=xplCA1Md%<4eB7Z*ZLd_Yss%@VC(1
zdy;QDh00U><K<8hz;B{3Vj#aO7Wg3kaoU>(^BZ)~dzx<+p%WqeFDV!q%HMkn3eWI+
zDYg*C|ECwi!uhYz1QWr(M@R9qR=&Lv(jxg!y^XF#@k@S&v}pdFgODA=f0=G^#Pa9*
zAm$vuV>?J3zi=mviRb^Z17Z^R--lxm68TTk;Vy|^yAe{(^ViVad4d09I&4bj|8FyJ
zDg6CU!1`3a-T^Yx_@y5Mkj}Tt=xmw6PgsQFMLt6a*_nL)1jJ<V6DUZY&EHLaqf7jg
z<lMZ>w^C&ef5p$hUEym7AuX4`fs%#u`1=ho<|=>1GMJXnuP4`C0sq%th%V$;e1TFC
z|G*DmxyC=907b=om6hB-*ZG~FL178Mf?Q#x{0}IZwT!RZiSa7uYuwRR!5{bsDk}MV
zXm?h{SDL_C&3B{tZVmqy-SDX8zkD1v)$yNLjJA6IG<k*__(odx8~Gp8KH&!6IT?DJ
z__52Np_#wlN@<lX{9L*$-pco($*+xXA`kve{uS~dw)6K<aJ_?na34q~|MCq8?cysb
zcfXsz;Vu9@{I6tC*vr4$hPFQbZ?{m{&-ecuWPqPW2e4aw7G+}(^0$8k(L?+%zlJfl
z`Ej|l{~YEo+XVawe~^47qkM-{@Qm^8en90oKgJefCip*1K>Z|t?YHR66hD}@BGY^~
z+GpJ3$5(^g=euxF`GEgf1WbF#Po+_t;s0|4HqG*9$dNb4Z>$43BABg%O|}B|Y5M;i
zJHhG`P+>1fquJI$U`R#DQP6(|JWc}qYX@F6LBJSnauGEC_o@k2lH=1&z$dq&yC8-O
z^&Wz{Re*a6-k^_5cnMa10Tyq;dvt-oN6^s@D~<{lc*1&LL25qw=_jZ*q0M?su<UCn
z^cQ44kK%DbKW!UM2p%DK*Ga*lLbRO{Jl+C)fZz#oj|U32{SKBO!J=5S1q%*QLey!&
z(rXyf5J3oKm4ym^dIP4N5wzli&5ObWv-4337wo5JCPHw)4W+XJ1I=2IRsolM2T_8+
zcY%)<Obo#M7=af(0<nUCYbc!)ti?pNC{FMdeP1$OusI4HO%U|ZCO%P6Nc)5&!A_b&
z&kI_f#Hd{mj6^_YvOvrPJVnsj4trAtrUF!^399~rP3eNKp8-5WVC|*F{GuR=0w$S)
zxu4LOCFptwz-+<JDYRV@u=F681zBT2<OmvM7`-b3=VU0%6@2<OWakN3w41#ucxx8w
z^9B01(3b*1=>m{KK_fZ8iUgaoA@iEx+9r@<!RkLjt_xnUo`cX5f%{<qO9eM*pHe0W
z%7oBz!PoRVRR{_w&{-*nNr$v5!QiKmRxS8<BXBi>4)Pk;3I=E+RwuYeiRSf!1$3FB
zLGUO2`CgMCnO5&+fy+K{wg_&~vA0#g=tEnZ;E|8%{ktjHdIO|g;6k105d22BgE|E}
zX}aqY;EzV}stIzQ085X+g(kmVfs$UlKEYo!r2PWNcnBR3#Oy-lEx|+}0E2?!WQ^#L
zAaVty+!i>#4bz4NhvaA*5q$m~hIv#F_YeL5?3lpsDd5KiZ;>}=LhudEp_78^M}eOb
zc;nSsbVu+)J8ZfusHS;+S`hmthU=c7dL@M37i`}Tp$`P_(XQd4;G=jboDsaW3C7F{
z4$^8kCy1wT_7Pz>IRb5kn-`+ZPN+j>taXvSFp6Sz4#Ic&5aTGkOv|W~aK|u+v#`De
z#6|cWd1G9KUnGFVO=uuTle>_y1crJD^_x-h6h2Cite5Z-11#Rc{5ja`Bdno|e@BIP
zX%+Pqjzyu;PgqKqh>r=g$RBU@7Y^@7<8fi!voP_5@V){jo)n&|g|t&bclt#Ggqd^!
zAyD|eKT1KumGo_kVBx!T3FNfU=QSt{5q@|Lm7&7yNmQN@ZoZ9Dn2<xWR=Dsk#YrQC
zec{l1R@nb4`VuL0^ae|mRd|F_Wuk?y-vSsT98jV$R=AL6&2z#ra$Cg-|E1YFUf6vT
zni7P|R-=?C+*kvaBq8e`^!~h1b_AL(2oIBK$--8ec2a~B2LMPFwz0vICOq>NtVkDz
zQkr{)@NWwgT@+fkQ7T2Y(6kf4OTy#i&$ui+u@yGu2ul(HydrF>f|y+4tK}eh!gb$6
z?^R*uVc455TtdrdfiP)5q!kL^OMz)cLLWZJH6imukYb@V8XB$(j|c!S5xQQ3%u?ZF
zl)F?WeA`Oik#b=qxd$tR*GpkVrBLev6;;C3(J;7L7;gh$jd0C8m{u#ia0h@o;Xn%%
z)(h{_#M&S{^crxDLU%jhZV1m(XtPOZ{TQ6h!tNtzYZ2N}DtoK2A{uRNLN+D#-4q`7
zvVx~wI7~ao4&g8b?mLCAy$fTygid!rx`k)QprS{3mz=S^!mz8bqEGl-76AQ18`?<?
z2y<xGx+R<yplgG|I9j8IgnnsIaa*{0FJul2e+q-%5uvCQ-5wRbPJX#D;pry2|2{4(
z^@QvRVK7ZClftTFC`}1ll2N)NjG2a*yFyz!a!m_QJ&m?|!ZLr9?hAeCqSXVTI0}^y
zg>#R<-WlQbhmbuhJVL(FIbrq`I(S56PrgxG(Wi9p$xh_85G8xjqBqF@;vni@0uvoY
z^Ui`eiH4S<GtQ#jTfpNYx=IdlS5ej#sBjbgN<-o<njp`khp3IV6rLil0T3@y8Ldj*
zA}xKK+DBxdIq;}x@vms}6=hYS<R{wj9Hbl*sdhq&zi8DlD6$?GbuNO66QXSLGoKXM
z48!14B0HMB0z`X$0x(eYJ6&ZtEi%Po)I&tiga8;STFye-8PWSsLt&UmPtMJ7Q4j;T
z2$A{|48mDa;sT6eq{!zuSfWI0E<!`JXnY&mVnkX0LQ$+$lv04=InnK9uryAjm;s3w
zy+PZ$1W_&>UlT?9Iw2-Wbehh8=S3?wK+FZvH{^dw7X3?(h!oMTFpyNy7vup<6LryP
zJzW$~0nr(v#W^tTqA2D$05U~9Aw*}1S_h#hTV(a81I;Cokk0UzMe@gi$PtaLgr+N^
z&nUK$E80e<?mSVWJ@j4`aUTMoFLFBvT!H8@geVskirjWUT9N4PUtqZ=+WMdWMD#m7
z$Ja&6;OAacBHB*5p{1gvTmZ^Mu4G}kD8tGJutHQ{1)-Iq;LAW%iGH+&71g5la<tWm
zQfy&Ntw=zh_^lJ|rif6zNHPme4Wih7ur!M1=)0jeM1RhM&?eD06n|(IEiXZ-MHEce
zrdmY-v?Xs7E&dv!Z;Ecmq0}y#%A)gMhiH%t?i2-m3q+TwfP7KiB9{-Kw@2hoIX%51
z3r$;nq7Uex+b?3$se3^5V;9ul68-WP0E40;8tx%cIVC{f7VWqOmSNGJ_t3Ku(f)i4
z!l)?p7gUakq<?~piwyJV|8FNm)hRH4Qe>-wiYd{PLXbP6n?;azS2Rl5k<%hQJ#6<x
z7yD6pU-a{bu<3!w;~9u~DB4yHG9!{vX!3}7(eF@iE1rA<rrC+xD9OZLY$E5CgE)2s
zoQ~p1I*dAr1t#*pIE#O20m4PRoDL?g;^adBx`|h}zzTQq`f{lE5I;(1T2JxlF&OG4
zp8EuNZ*ewluYAN2l+<=q{MjjR`ifup8Et;zPI5UO6aP->YyRTmR0umR{&5qeoDjR|
zfIBI+B{!M%lvunQT?-HwtN|iW>`1<nAo2cl5ECr^z!hz$#XnHKPl(uU6?z{k9()dM
zXT+1V8x0eGPVY##*pr4kLd;tU*=NQ4_27&Yw;hGdD6!qEC`F57BcU)x{8kD&7%MK_
z1DnoS#pQJ8J5Kxqox0=2uhX=ZAl6e*F;QF=1Wifex3&RzUc7>?QCtw4-a}imIK~$w
zMSN&EtVk8_rel7Z_@hv8ri=epL2rimhj$?QqIlJQNXZnlP5_W4cAWxCws^%ZsJ|q(
zPLl`mve@MZ3}TMBD-mL@h>xB_W3Kq4C6JvbF0BFLs@OLSrF`)`I&~L_*Lnh1C_X@Q
zN|AUCow~1yUnql=V)6TDP`WPmehtD(#FiH!tW?ZrqJw4P-{=@vE<Sk)xC-%Zs|tup
z@mHszqDmZ51D<N}WeIp{#DNsqsTD7I9@6T>U(-geUi=n4!42Z?vSCc4IB@|0H^iwG
z05pkr6hc_DxLkzF7I8nV!mZ-@lwsN?ewdE7o8tB%=<O80M@QN&vGf}4KfA^8qrmrw
z87z!fuQ<jBtbJk`h0OcKC5M3+5cg2-;w|xKlvFw>-dX^_koYM|$-6BstU=qb*p@ss
zBjP;<u#AfL&~2hIaUX3w$HnpVA(RPmG@Xnm#gPh-De)WL^!?pC;uEpZdsoap47;br
z&E(m-C*FJ$i2LHfI*557PKW@@L-FxBD4Y?$_zEnX6+cP$rRK!*=TJH#*+X$dTgi2M
z$hMQ5s0F}Ya%&Ar4iXg$ERGVn762#7FV91!v!wP#`u`Od$)$EQx=NPOwB;r-Er9v%
zl0-M~ct{!;X!DfV)2_oy5>*KnZ^;%Dh>rwYCcJo(9rw^}U&%ar*8L<K9H8Qu<n>Gt
zf5|yMx^!I9wI4E1Nc?G*Jt@hj9n>kwDw^%A0g@jnoDeAajt+-G5>MK(21~Y-Lg8u2
z3v|8+k%arAGE}0VEX6aDNpgjSNzT(=AYAeeow_3=FOj$VtmFxL#UmxH!LTVxvYyh&
zq9sp^gTzRpuRuerB$E=c&PmwwF+g!viIir|cnOQ*O9>JtIk*xf->yd~Ns@LQcAuB%
z$gh4ua_c?xDOs|>9e@;x!yXuuD#=U+OPYie1EJ}XSUL)1NZufK*F{Os7yy})e}+-Y
zlH|Mu3$rEfx1)4P!ihuMWr=kK`MGi=a#tw4BH8#5nsOyORzpm_<lB?zc7f!`uTW7a
zF<b#Dl3Wc!XRb+>P=Kabvb_XCuS@=U6;ethxkYFzl~lY4)5;{5C<nJ(!j48|g(N@-
zc%`JI2_sV_8KF--R7=LJ^jy_Q63Ba8D`AndzD~0IK4jNRzT5}WAo2JBER7O}dtkXC
zdFLvmHA!m8v(+r=pf6RlNRpq1*{zZnxoB&XTzwC?o08_kXls{jsfRHglJ}Y+x>FKb
zhJJQQo}$xDx8$35=>A`iWI4^Ky%POykUq&u+Ew;T-l1*xfMj0-$SuhYnmh+3akM=e
zl4Q^_dRsD1al>KBV|ti2B1wvYuu(}m?NrAkELxh!C4qGDVM3y$l#@xx-ea(EN)lNN
zVRs~^RN8;um2lsKv}wr%ZISOuZvPF$eaT+h_dbv?9f5c#`CSc7GZN)G2%VKIUy0J3
z<YPTpjz~Yp{rN?<Qm;mo?4-{+pv_*okwSeA((AOGI7&CtsoP2V?NcDmQZ8*%T%;f4
z`h<0nt2FFw=yj8Bpj=CL={RMscu3!;c(kW<<*Sh9B|Su2V{fT9ofLhfqGFVeO81is
z!B_gs=je=|)V&izk4bORBH=H6l~%*!(lH9dpO8j-z`~Q#o*Vc@PDu+hAu~Yw@y7sI
z1Euw}`45s#jDaUuS~?Frr=^!%K|-W{HP93)T}@ZP&PYGWfch}06NSverH?wHEmFGg
z4~U79uHXY6E&Z6H3Ncdm8t9Fc1~AcybJD#>z!E2YK(YCFsca$iB}ko50gz~w{{Ax%
zNz&INq2j#MmCo=Nr2l54Ysu2}*FjRGduWTBDvhJ1E=}s^1TpDSFY;VuNaM&Ycu`t#
z7(z3pmA|4bOFB&{dD+r1ifmqzE*8L;%hDwRn4KeaA|J^W=^6^$<w~thKY`{+Cq@9g
zD!qCN((<LZufmD~=`WP<T_}BY8}t@Q*$rsBCjFC=Z;Peo^}t=1?mY-xi8P3IV5QPO
z3IQmS?!Sgox%4sGO;$+R{{T=a&7+~LlKzb!eNnZvi~u##T~>-`*GhXL!CEKXb_<r)
zONYom&>%IX!u&>Q$5C|jhE)F)G&M=}zoM;Kx_uCU7HQRWu(V3KTu5n?9(w}to6@rb
z7}0j=ky`+CNDq@ItyB75BcyamIX+<NmKN;=yhobJp!<Kl(l-sj_el$%hNb<|k0^U@
zK>EBBfVZTd4M4@9^!>*nZAki%PC2)wEL#1CrJWzZm=Wnym(eyV%~=H%W76{PK*ps<
zc_0(gr{@7aDSf*eWJ>z{6Cih_E9s57D=mA6@;|4g)jJ^Vp7c;H#N3xQ`N6ga(l640
ze<;20jA5IRI>tfMtn|gzAal~cDEe|l_FxN2wz5kzfZNG-Q|5@hEcrPQ2buL{5J%aq
zXb5wWecT8suCk5G!RaRZhlNUaS;4n-|Ib6Va3MPCDN|`s>m~b?(qO!0Yw79skvWK<
z;;5`E1uVX@PeV}hlO?93?U=0X5m@0bliNe+aoNN#u=j+F`4QSq%AEcJ;FPR_@?-;K
zSF#~9P!{tWNRX_q54{hTy%r8(*3&Zf6L>B|WN+Vu`cN5%PLpS3Mf4SnFxko-K!nSN
zC<7!ymPpa<vof#y5E?1lD*=g;@f$#*WwQkk8YA09S&Ff;Lv%<wCmW~3S)9!NC~S(C
z9f*R41R4J20WY3RT8mPWRd$GOC7qWYrWyHyY{w}KTe7TZ47R1n9uL4Tk}7K@Ut^l=
z@J5u<Wo6;OXUHz!2jHS?-7_d<%9hYA#4Oo#Fob2xN@x>sN%pc2Y`QGF^EYJX$l7R~
zzaq06152*#vlmdAC$mOH1AkQ(O3!+}Y$5q23S_4#J-JX;Mn}vd*%Y~0ugTgeAFEi#
zKL**?Wq(jgdWr0v&(P6QS>gt?mEng4pj^hk0C<J$ks)ZRlr65q;8n>!I)iblmVLJh
z8fs)mo`Jqv*%j*;@O3h0S{3VMasxCq$ll8buu=Ay9S}EUC67Q;lWgu8R5r`j(Iv_j
z*(O?ITV=0rMX61;f`XYhW$Ql!X_q}iPkx8YLR*4P*|JYD&Rw#R^Qi2W<?leLNA_nZ
z)c4AsdC3ZE`edi(L)tCbA76oIQ1<;v@C?a5I1RnGWfMIp4a@d7fMrDXcL#u@vajTj
zJtk|Ut=G8h13Fty$bLHr_@s>K1>BU((SXt&*?ii(-<1_VfdQJ9=@(*T?#VW-La*=3
zejBI#=L6Zdd8mCT3-X2R8ClK?K+MYCp+#y=_Gd515&35F3)spxPz2jf{s_Il_HuXH
z7dgnwX|i^duip=2oaD*0FLIV&qRavp`R^Y>rmH+71H?@}%RrmEyox?P;31D)MDL%c
ze8oL9ddY)&&<k(*s2(bO<blT_?Wo-J9T2|q?VrF3Kl$p{py`-=8-<?z<;HM~%yBtq
zDc~pMwiH`DDPKJez$y7f%EJthTU}vApxm2w{Xz0yX{#74@2ErRw0!Yel&m50^_1=&
zDnCHe)){#lUHS}@KfH^|aQPkbGDOIik+bit{3va6BIRG5Mq8A8PdQ4_a$9mQ#K^mx
zQHqs6L7x9}^2g{+jgwDOo<h9*Q}X*H$Pc?iZ=(Ery8n<QkNFO5=dE(DHpspp|Dp%#
zljX_ut%nr(NwPat{*e^2)8r%H0+BACzY4N5<n|RH7v&$#2Ov}a%42|M$-5{LoGmXK
z!r)z!SJREX%W{7kwB^W~H$ci2`M0!B$d&(2$@Y2jbO+dURc_7GLUz8qs2$P@<Z<-H
zvqHI+jz>juoflZI$phMfFP8HTpj0Yfe*>j5c@Vu7<?;hh15hFFR6~8G{InxfRLRF#
zV5ycz{||r~d6OSlYUP&y9G7xt9u(EfS1bfegZ!rT0xWHmC)+^b4SC!o#5Bo6LQvT(
zze_Ik7Wsn_2yK<G-iEHV$@kHRn{LYco&af=+mry;A%Eiobf#0j<_`$%lJB8&RJVLz
z0dPI?{dCanmH)K~qWk3EzX8$xa?Y2)4al!d(*f?5JaYhKP`>#a;D_Yllsa--UP4FH
zVR>%`q>ae0Yyo~$-b=2BF?km`3&!Q)lsPgXA7r64DbJ<LqEqq+dc5w)FBpNlE8q4p
zSf=G)bVKw#`LchY=)Qahu{@AFdC>d!P@YSP%ro);F=WrmU-}5+H7Eb(D@Z${__z`!
zTSefbz}qPfokhuB(Muj)2gN2@l^hl6wCQnD9HqnxXT_m|Fxy4(F3mTtiWFKF+!R9;
zJ#km8_yZ*m#nJ<Sdnzs?krDsDqL`qQkhfynHQ;>||8s$+qY6h#RPa@7rIV(gVl&0+
zjwuF1!0E3DB@gX!MQJwFpHRfpcJid+y)QscDdOVL7N7{H?Ny+nwifUp#SC5J3s#Iq
zz>3p~C6wD4qF5$Cn>ADs*n#31MZyet!W5s-tQoH8<3Lk{V%2XTXB8t9#f(&3qs2H%
z@gD84qZP|3s1c(Ol5Zzg!SaKJ=M+Pf2bQb|-wl$YSnq_6rYhc}oa2j%V-%FgRJ7Bh
zo~79PBV^`S6}{vxyP_~tmR7D}{18->D4qy|-ZI7eJHS(}h^MGRg`$j}?n=c1`hBVt
zOX-?fwc`2?0BRI=I7=_8RmdNrRHsNIhgyTe_I+?RD&l-Gls6Q=(W2O-c#bj)niU^(
zL2Zk|+FAzIHbtfnG~HBePeY&D725(aBpr$cjlg#*`jS!VRs_<z+oLF>U1hIgr3<9>
zDSqJq(66|32=D>LDH^<6il2`FFr@IMdHJ@Y;Xg;9qSha6BZ`a9p>kAFNrBZdg^iUa
zxN$`SZKfv_Ui2hQD)wfeaY~U%4!t{y|Nf))u3{g3oo`yPn4(no6kW7YzORVbfYL)n
z6S)j$6mL_2byhLh0nRzaXM>P(MCrtV6kBBuIU?+p9(gd^L0LjaT1RF0_muzXq&)B|
zh_iBaAB4Iprziu`P3c7YZFgl6T}k#(?#Ki2RPLt(n3vL(cJ1CuWd>M|Dh2nT$yeE&
z2~B>=8Cr0UDVY?^_g8+`4su+%auaMir94QP%K^%l=*$tQjFMCQFG#uID>McxyU2TW
zS~*5rf-}nBDHa;0WU4Th;mTVdp)yh#Gapt&DI4@?i&h4Eft*wRaTN;Vl;UrpK3<tb
zPN*cMC*@I|R|>{q=mq6@a+;+ow^I^%no@HIEa}SP<@EjCOr?J@`jn+KehH(pl`kBG
zv>fHk1?at^WV{CRbCu1MV3env3x~q1$}O~`$yctUk8l(z4^l?pHRXmll!}$Pp=i6V
zTuU*666HUXT3V`nY7va7P&(6{nM&mbI!ae5GXkK`TCI%YL4A$VL<t?W%6B)T)S!HY
z@*EnKj}C*}P}b8W<QC=a7a*-wDQST*ZOTUyQR+~Bw*m?~l`3);bSbMShp$^%oeC8_
z$`w1&(OzXXt*OJxfiP5#DA!yB%c#<gJP%`5Wh5njjw_$1W5$HiNVoqdm2c6ma7vj%
zN1r=N77hMg<>f%&r<LEVh2DG0pABHSudJb6(gWpACg2a1uU`Y1QTEM)idp6GW{^2$
z4`uQmQ5k>6z}l*I&^-b>RXOc8>{Zr>l%ndO8b1skN7Za4)H|uZq!6XE$`pq_xu`~I
z$Lgv|+Kx6i)uFTKy}RlKI$(RKj^2cNPt{3x$o5jX{{-T#s;3LAzN*I}0QXaEr^))5
zN}h?n_^VElKjFB_tp;r;RDISYG@ev#{u~NVsWM(fV}L5sf>N-`{Squat=d4rkPy`X
zZJ|O{6=`TYqf%4II!rZ@04u^(N{XyTsOHmRd{*_yddQ4aZF~%sQK|>;03NOS?J@K>
zMs<Z=%2?IAXECDZRN1>}{~53PmU3DXRPP0VB&ue}k(i`<uMD!!tGv#G<$@}c+^DIl
zgTFvbnyQoXN7GgI5fGE1@_P!JE~;b{GtN}4qCiQO>Wi0QVK#Ee!Ffrg2*HqCR;AN(
zk)vu~1}RrmJ6<6FORnmtl~9qVT0<}ORh2^^NP+4Yg`lpf#N_cTR>{&K=DO-D9|$c`
z#h(G7RMnA!QkiOP3|PulszS)FP@SMpsaC2O>p`ki>+3<PRl*X$YgCWX8M;>WuL7h_
z^|vFvfAy-kFEMO4RNN%|cugvE7^F3;7Elg+i)!NlRJ5vIZGyq=stnqsb*Mg}m9|sm
zJB5yRsrJ#L*sWSP0QEhpDhkT?s+Qz{vrlE-hY{^py-nw+0aft@kXtI>Tc{jV_0NJ>
zhg473LCkHHFU_yRs&z)_9aA0Tz?ezZTmS9lRbl%8yrU|)jJCU~6NLawt40oCfbOYE
zS3}c%)y=Qb_CU2>gtmvOhm>zHqx$`0sF+o~dJUCxs%qMn*{Rt(LG0E3uF&UTRYy`r
zg`@fjI;lFTr@uu<oz)&SQ17B%>Ib2&>Xeh{p_|&9W-oVjx(q@+)JI=O$y3eA1KdY_
z`U9vqs{Sb$IA8UV?I3>Y4U~d-OzrIlnf~eqa*mu-$I`X#Q|j3^SRbIazW5zzpjvki
z(t^~dTu=&Dm(Z|<st?kfa7G>RKUfi_o+6iUxZ3p!6h^3@r9n8Wp7nyzNcF=fQHoN(
zYXl%#J@hI7G3v!<AS_nB#vA=Tr}m@!56NonyI@ICAM%7vsp>*2IpovS5p+8tU48Q~
zq-CgYpTbyNRNu>?=UJU{1uR+W&seZKTV4J($R)MzEs)D<uX-4oqfT}~>56)LCpdG}
zE9ptdQ@?Tm!mg^%vmh*A9Yy}>0(G|oDht)J73gk}+V(&H=QXu0eS)i4{V*N2U03sI
zdM{BYz5y|%YTs|bTBfe29KdpQ<TvPAh5F1M2(46qaujV<YM%^{YV`<Bj5TUr6L7Wa
ze}mBbI`za;=xDwAYf4^dP`7g+x>0SbfuT3l(HANIx=Ec%FMPB5C|zf0Q5XIK(yE^Q
z9Kbg9cQjAlR4=8E0JN*;XuHv&zT^Z=oodI+XzNnHu@$9m^;dKn>`|vt2&q@SHUSFz
z)RqSz{pyKv7&D;mD@N&-`guy78dP6*qx*kD>VhAExUKdj7wfRvO^DKn`X_S6j;edT
zpkhqDj`Equ)t}aaOsF@JpLtS!n+?E}`sGPf-cgT{o9(W8;B5e=)o;Xt+*2<o1Lu8p
z=^3!hsDGaZnN{yvhQ7?H7t&G7YNu(SiOOE{F(tJ*Xtv)1an$&BfX7L5gC;*`&8FRu
z=Av21LN8o3%?r>`H;w0;;B?n?JqH#K&1Y`|;Hh!j3Kd?OH|YT8t@(qtxIUUXDL9X6
zia!JK)fCrbeEl?S%OK^LRdaC%`g=kXL}B=o8iO5-I;HV^8eI#}yhxeiff_|5R0L^8
z|An+*&5M-Hc3RU-2e%N-lO7Nns)-@z*BQ-b%18>+bkp`XT=UFAv_)tp*1`I-n)wQ}
zMQUUe)Qi%DN&%16Socsi>N$-QP0VqceJL<1Uc(~iW`f2r37$kvyajrbH19tO&hwfc
zO0Bz~8K9F)vgZEpASs%S#ek=3l0HKzO;bh}Y0@<vv*66o2=2hNi<*AgNM&j=X<)N7
zFFXOxY|SFvf5PjeIXn+WUDj;g0)ulj=V>*)qVcAUSgt0v2qaJQjUP<As##J5V7_Mh
z9Vjf&C@B}cP;+$y6c%X~+Mx29CT$0#6l-=LhxOMrYd-<JM6<*T>Pt1*bcw%A^I`}}
z<(l|j+J9DPx+x8&Qj=wmQkCY16986g9?~uG8qGi5P*|(Uc@l^^&F^#?tk=9i8;k~x
z?Xw__njmrw-O!w-<8qT`{$Ehotck1vu0^wIK7_Su{3uY;rWrkt%A1;qW(aH7thr11
zpB<X3v<dIjoZW#z=+e}_jPdH$9Q+zQJ({B*;8*L{u=`>6fTl78DsE|pXks1I{InFM
zA&r1`9k(^_CICLH`IENtBbq`=c^=j5pm_3_Mo0UpaZQsQ?48hLFd=$UGyV_xU#2vJ
zli<0d2|oc7?`lrkqBO0UUj>`)X+EOMm-jV4(lyTqnl(33dZ@Will6>-MYpYIHE+HQ
z*>jo~c7hzyK0(PiwpuSIbiz)%BM6oD+Szqb=%5u-3WlRrPWh@%+CSnT#p<lpk_X>K
zyOMH_U9|#ohq!5jPC|^k_OW+CJhU6>1@hGPzXYLP+BEutinn$zoxFUsZ%{(<QSEPf
z41%wA_ib?cX%{4*@|bqdmnivb!^c35YjYm~?u7QKx1iyq){aa&W!0{wa6*7KPY?Bh
z+Aji78>Ia*39^H=&m&W4(P?e<C6Ey9v9F*$RGUIqGtOwg`V}NhJ45m8aP69<07Pov
zp)FsO_9HrHM{7Tig6J6SM{lDPt5tKra!z}h93XMp;ML%a*IGBcj$(rLamoTu)LM3d
zHA%aK?$Mst^40-yL3{fuDwDNeQ$Q<4yM&L*RPC4rLz<?o{Sa;G+7ruReTMexE?9U`
z`!~f8GPRG>z-DO!*svm7%Z!A=OWJ(}z+Kk<xF2eBv?r`-0AA5r<siA*jb32Q)7DWq
z{i@c9_Eq`XFNVQdpsmY7WuZ2TJWNH}R7xherd_cO3X8RO$<cIOJM=CFuSEL>dA&-t
zr?-KWX)9?yFV}wf8~_#CgS%0x)D9aUrAm9O(28QUcH<k+TcZu7$ZV~49S4<lTJhr`
z^;$he4jQzP=YeR{`cg*V4Q=l(0GhOkeIU)+f9cU_(dN2BMXUDxRd^EGw9jRN+|>R+
zcPiSo5B)(pw9jorU%ItDv=Qskrn}Sn*Q;%8hu%J|vKtEfwOi<u4+Gi-6p_89J^m?J
z2erL5AVXT4Aq>fF?TPKMX;@o(7z#(Uk5jV7sFwRCSjMzB>2No$T}83^39Sc3%qO)e
zbo80huBK$gJKDZK!E#qS-*z6}ziI6viUr-%dVLCVUn^V#F%Pu%&L}<9+ES+XjP~qe
zh?&(MAjj#PHimXtM|AIVp~6<@)dlr-x){p%wAcA;2hKtF*UKP|y2L-g>7@IE++@zW
z@93_oi|&upz`5!o1JGtgGK?q2#9fyXjam<#?`o*`)Wz2V@1=WbClKDc#ys@bN0&-L
zjib7Y7hsdG?jWu3e!5+`U^%9nTMTLbx@9V8I<8CF31KI6uRMmzle&jTKu+l*UIQ*b
z7vKha19h*x31LB2-PbfV1?vhc!E;)dyaGZ)boP`h7N&D1A4|CIQ8G9}_cuL=Q923j
z%%gR@AaKU${CKc8PUoV)0LSaD&w(W9ZXN+3UDy04G-c=>r%>ue-S{pj%+!5d3`JQw
z?IRGDt+NKvDe01KijFXsb%nH4=IHFoK(6R~C@V8pm;Wd<<>~%;8)B~N9#ZOKzHX2v
z#sZz@U1%!QvFSWjq&v13rd`u5J_nX!o%T_%T-P}ZAf-enB-eSVE{gzVy2svuzH%MY
zN`FOHq5EwbwUs*QA^@v&8VUzg>&AOvevR(2OE9KZ*MA75I^E$XAf{gDO;-~ebPp&O
zs8P503;;KD-U9TgNhdrAna#QgYHQIQF#^!4TPz1@(-r%J+|<Rdg}!#(<g4VR@6i20
zC(TaXEE|?~>2ho#rdu~fpNi?xz37cnudbm8()x7PV3hiGfwZ+A(5W3E=9Vs+F2D}z
z{s~5DNH=1}aNX7oJHqT?U8xUbj_3yHvp1u<;v$sBbPLE6H?E7=`CtB-ZU^mOCv}Tx
z+dZZ8r=R(bu5uxy-POHw4w|NQl`BxXr{hw(-+f)sK^XHu_tbYFvpQFDM9k@m4?*@3
z{RB<AwtA0x46vO(&Ig+8_4sRYycPO=lqut=U%wszC;g)DDF4M-zl5e@7kx|;8eR2k
zD6r(FuZx8=cfGh13O)3nr=iVLA4V}RFMT2%guL}H^r6j1e{MbcdsP1``RaZ3zLXu}
zr*C?N-U@v>g@^t1Pty7Nxc+fU1~{Rgq78O{zK>Q8YoPw*1IP~2J5#<vu-=O@S5E6!
zQ+`y4{sa1YK&U=T43;zcm&r{Xrq8DkW4L~tp2rBiI24AS)yGzYMC#u>ioQhY<2Hgs
z>+M4Th|$~A_4`=8JvlJW>Bs0*iPL+ngp_!z{+0J2J3;Rdi^fEK47vA`^m|tTabC|(
zL+OIvOqrL-`kj=0kfML=adbOXKYbmgG<_QV2I+d{5|9i%oOF2A^nZK^lBvH#!MQAb
z=qO0G{xltFFX>~Z0l%!DBv*fq-kO(>+AI2(=}4Wczwk5~^YlMo0J*B~q}<_rec}7)
zMS(ss7h($a2h7l0r03p8FRtkyzl>6`KCl;U*Y)2}@U%pqM;?<>J(H6E%Je_eT2rp~
z;G$Ha|L!kzyHdYm1qP@}UuD&yht+!7JXleqpGVVHt-eG7g?0K7nwRVK-%}DpgWhE`
zDjW3?^!wb<AEj?wH0j@^kZ801Xb*5L`k9N6(yDjQhNd?C334QK=w<(crBlzLPd;?%
zmsX)?-TF*-z<cyvl~&l+tN)bla`ovCQ$~Hi-Y5iqK%YQ4Be(QVyaoKA{`FuWhV-w`
z!lv8$J@ji0>s<$c8`0;6p$&1f1%Qv~{~*udxITXvZ4>&%lu|dTcZ`6rDgFQELEjzy
zIZCX(tN&R+-=Dazcai}AK;KTsqlfybHi((gTiwArtN*bd>gV)c<m5PF81DhGHLMMQ
z3Ohq71*Gf^74%IE2Sf85+8hnqQRsCt?4lcN&IV_CJX{P8bSc8s;72YcH$xUV3)~IA
z{y_OJ9)`3qsPHr#c@NUO44=>e&f5?|7s-7LLULdpHLNH=rLW<^D;OC+!)vsCK4vh?
zL&@K8-v@2S4OhwmIAMsQsqCa-D+NkU85(7%3^08CDoTNdL_JDDhEAHif(;+iM%Q}U
z@QNL1h~XBkt)T}0e^EMPV8%jrm_c5G%5cN<k3d8i#y^GLvj!_|Ln94eQII;yFy#Z5
zXv4RZdl6&!J0I#}4bBB1=M4T|W1Qm*AFM+u-k^ULq7w{<ZUUZYxJw)KB&%V46nM@X
zv}b|8V6cp1ppp&iXrGZ{`0XCrQVpY&9hqi$nF1y02KhAb8HR=AP`_w6LxGY^!`9b;
z%QCn;4MVdH`>sIYB}1_{+AbR+y-=BJn4?=1d4?xGMd_;HP1?}p8?5e2z*AtzsE4LP
zLw762vdEC7f$VFBk0|}E*szqmu-6S2>_AEkQIwZaYB)uUYMH_309eWm@|RGmFx0&W
zc%>nB9aK~q)UTlv)rQ9@*i~b2p!K@eV5O*QoxzE=bM*#qYZqvPVT}YmY&49LkL8A8
zn-0Jx!^^agG#j4!0>-o$KBV=p)u2y7Tbm(+ve|ALo}ztvyWu%MjAe(x?-2kx4G9IX
zu*-0fyvE&zayoML7|uI`^cvFZf$KB)Y=_K#Lr%OE1`ikx(1Lx-a8?1tpkaW%!#QMd
zrtQ^j!`pNNXV|cfT;L;yul@(~M-AO{Xc#jb;z7)~;m3`TGGVxC0hu%;u7IW~Lvk8$
zcMR<RmNCO07olO=aFDjf_Y7mSxZF1|rYQdKz~I#k;6sCkLWMJiHG^oJHFUlSF>{8E
zGthLzc$j`)Tce7mEjy$C1pw@gM)HU`7_;b2bu^wl423Snf0U?nHQs*%EN;d{b!c-p
zK1%0Y590~?5Q?XfzY`@d<KWgsc>lbOUIhU982_c@w4=s1R|DZ|Ow*#$&sad2P{)ja
zQ(B0>v2H8Kabp?z4o(=$2S835zZ?YMlyM<V6amJyG?fJ!Yqp~@$e8I5g~3Lf1rUAO
zctHr8LX7n*Atlu4NTF2g8KdV`XbLk97s04-V?-$M5ys%%D4jJ9)8iFsT$Bx9lu=2Z
z(rDwTGoFMP<K=(R7HedtqV1gVIm*S0GaBi-WW4dk7z|~C@lDziBpQ3$fJ-vw(!zD#
z`1W6DyI|aV5v63Sanl_DQ;bWsFgVrtETw*=84Kx-L%Q*&8?ZFPxSTTNE*b~Q(3wo*
za=MX{Wh|m)Kiep{3hOT!kCWr%vT=PoNRBa<ju2OjxfZC;HD1$zCC~WVvjAK*enoS3
zzVSO2gcTUAx>wPeLgUV1Ac~ADH=#4vjGI$|C^o)J&+K($H6<vN7z@sUrPSD>gwP6O
zuM+lF8l4lsQf2&w4jt9TOHYBN#^`$pR@54|JPXb`<7?yut~VasfKD_Rf2Gf9HX6mW
zGq_>ww-RfU@pHOQ&}<ZsKvRqH)(ar5#-S8QYcqaBk@K6z%&#D(-58bw&JJTCy~dr!
zE%VW*F5_Gd`qXXw<_2W<7~fn1O}$1gISKoW3n@<1Z(Mr;#taxaM}fO#Tus~1LF3zh
z(sMav+@Fo&ZR3~oA$!<pM^4HS<0rWBv}n}mBnN)X=w5`jaifX@O%p~3nhGb4>*)H#
zlyOHSOuJ*Oq^a<(@f^9pr;TD~;O-d%)}eIYxUC6_9vE{ML;XYJ#8Loej1C66|2}K1
zr<3NK(TOIZBc{n=h_N+I?L^7WR7Q`7z3I6|5C_vIyP?q0w3`Os$@I=^u)^7Nffhv<
z6aP3=xSE)o!Qy5brr@i)Y4a+m_b@G`JT6bu&RB4InJ&9QpSQ{RONu}Em@58;?4zdQ
zDIk1JiI0K!neI?bGte|nK8qkz-pkMwY|;+_f7)~~9DoqhoAhP5P}86QEN4vq^yTO<
zQxb(e!%aqav_+VNm1sL_GLjcH+O%L1;4!9DGgx9x3n<6Ldd{S118baV?av_bChio*
zIl(mWF?x|`ilewmlF4sA3_fpKN~eYkrf<y<nrv#J$`sRQv@=LGIn&~nX3C>wCEfI9
z6jWrGJjlg!(KPLVQl?2llV6s}CkLF_ro}TDk{qiksvEUeOou5`JlFK25+u*`xI4&I
zlWQVa^G#pTwUGkTS^>lqn!?EYRAl-9(VIorOly~+ve@*+V*FayO=tRnD>1p#(Wlh(
z@0VyRGwrzq4dtd7T(?|QVe+Cc*H)U6$jeq`vOYo?h1I54_oK1KWdABiy{VQq%nhc$
zJ^@doX*;=EZkT=`A4!u*cnx}+O#@XB+G6_F2-0eDnnYWh>91WF=bI)ey`t@=H5%YL
zOb@F;I!z0ALRgn+4wqgQb(@k7LrRZnp;ZOiYx=Sk9qlu*PC;+KNlw{A1E%v&g7ucE
zoAOWwO?4DO8#2w3m*BQZA^~97WL}E45mUJxRE(P3A3*Pz>DxH4jGIpV1C|L>*w?6>
zG{sY5#FS|>oqq3_{FlR+yQYIoD@OLdX<sU=cwh?i26<>Q(idoFOiLqCnl%N}y^T53
zoexp6HD8_wfSvi9JmBrk?E}#3VE%!AbVqYoEA%><C(2QBHb2S1Sh$!2$&2c0{+`lF
z+{};Dx!&D8kFsq&%#!Em{O4)b(n-k696?L0xB0gOAbiX@v`8H_N0U#<*Zh1HI_hV>
zK|Ypa<{4Tt{LNSLQF+|_%me5>Vg42F%ta^7b5~&DDYGlB>;dK`H7WzmJvopWWX_s|
z%wY4D7AQJx{uN(Hv@QxU-_A!d)chi4?Vd5a&_*oGETAJ>xVe?yiU{)_+QyzW?=*u%
znxzXNG|Ft}fFX@Ghr~nEIkWwjFec9Y7WoR}&8{6VG{L-qoJfi0^|rtzng6nZqVwig
zxPV_UpCa$AHQD@65m-~q!<6)tYCcGFS(@3s1IDDAZ4v>@FrTD{=AzmEXK?149Y;~h
zGk4R>bk+PbEs^==O-!gSFjwt^!a{TFF~F~x#c!a$#pV|&@^;<aPX~$;^V4)NFEv+v
z4VH4Nxi1G|D$K!uqp{K)dIhyr=J=N(t=jw?{S>w4ZyeE9XZE1Uv)(*#6r~1p_J6Ji
z^YfnpaKn7*1^`XwRp-IdY~Dhj`Drl+6hnQh`4J;J(PsXH54|_dv*GAqyZIKK0Xoc9
z-cs;%n$sIGG+pN1Y~Z`i@l_DoW1icCvFtUkqcC8fSw?%ke)Avif()32N(jAWUN{Pt
zLGyEu0ykt%pjqIy`Cc9@95yfAj>-{p&l!|P&HM?FG4o;aYmb|wUV{1wvxBt=MopSO
zBD<%|akO8!V-BKi&Rz3b6->Kt-t`)UJ~018htY@T-JMWBV^-Wm<*a$(GH}kBk5IC|
zttE}(Lw1&*>Fi){x!VZhV6lG|ZH^Z2Wf10UIZ6p6E*6Om)Vo?z3uys!v+U_W(cSV}
z40t>(FOEQrm!%^StlpL%$)V?C8SVwkQOlFBL#VH10Yy>#EOxX5J7(GXEQr5FO<w2Y
zmQ_oEJ7H0u2g^yzE;{y}vK*ufhXIyA+JpyM-rojcL6+<m`u=>drBRRGpSG+U1_`kU
z>5&h$czz3>GZyA3YznjdLo0l^Wq%h+5te=VP<Ynj5d?*imfa;FQI?bI!4hpLl|o^R
z<sN<OFV^xS-6J?>iF*zt&ax#0zkR&rBE@GDEJ>eJ{2|eD^HCI&EM+f4eX`|`V6diG
z-uHmPsg{m6p()K0Ers3bmXFDooMAaj?%Pa@9qmZ6EDuy5*_Opiz<J3Mu?*@jTb_6t
z#$2)NY6dRXVhV-KJj<io(00}GQ7Sr^Z%MxZ7Hgs9OE2`P$nqCuieIzb`4K$DmbvEu
zyly$u0@e~s9!1wmEqC`rQ<)`~lAOye36wZpVOcQ&>nknsd!VAq;_=^^$MOSZsMc64
zk3w{<<!eWnR%aQc9Kd>un=g9SU|Gur;Qt(5cU;z07gx)swr!}Dm06}`neyzt_tdmu
z!_lzP%p7GsfC@N35Rp9uSt1}qmdcVPQ)CYT0TB=c6j1j2Jum;9&$;(}&pG!#zj5z5
z=l-a-*`1|mTZ7&6^jvSW6VsK@WH&{ZK(pQE)6jj>ZlDF0TI_sB;6<z5O1c8u?DkSp
z<Cfj^9pKvShUtr19d_&E0q?Zyya7jV+g1LCdFrxT5&*k*>>Qa8>9#9f1=3^p?PqB0
zv$J*Gf~9`D+6?HvXZQRB5CeAYbD?z5?wfZYGh{bK8=41p+g=86*zWMVXdJO~oeyr*
zZuM*M;-TG~aNx%5>L^JzZud47D^A$`Nb%1}yCn$_nX+@DyJ^O*o;Ggwj4lV5bzqFy
zmVtF-{1pQHLB>bF!;3?VCKqsr8P{AvoEWxw(B{lYqdFrOMne(i;s|3yAGo88i0j~v
zG5+{}jTmDcU5~De<+EVPjqwI$6HYK1UPhxkqcsjw;=zbo2@59~Zj{UPWQ_UI`|lLv
z3?&e}80}gZJk8ibfpKq!;vv-dFc{wf;ma5j!eKu~53P{>8P=WP0vO5L0S{z6;S5|5
zgY_(a*kDG#6}S+_53fSY8OFAouoTMp{0<t!83*peiwMSViNHlNdg>_u5XJa;74XrF
zjs$pdj^QGQObp`-5fHJA)9WA_$A~?T#(2izY}mcPxIr(s1jav0(U{1%Lo16U2A?9l
z7a1?D1t5hHOk2!UMt3THgEWR$KS(+wi(;c03}+6=B}RKDegEY$qhUA3bcK=S3Qsc`
zd#Q>ii(yZNGdYaVT=<mB$n^tvmEl4uw>-u!N(JRJX6UF<0i%d6k3z=fC*j34hU4eZ
zUCcP`3y~7W<+lJYW%#}Ton?$(Pgp2tyhf!A6$~ADXscv&&Y<-M<C)K)ri!um3J}$d
zoh|6BVZ2a-NvLIPqVuSAjFDeJ8W@iB@vBD0?o^m)V!TIB@Meaw7<O+mZe*jejbU8{
zgSQwPY*5zDxc(w$rh~!$36h<R_uVjv+l+a7_}gV;MANpco3Sqlh#p2Y?K^uJ%8QV>
z%SfTEQy=4e4V>v`{J0n*_ZVZe78qpQo{h#KMrsS(zRz%42*3lz5LI^#GkW%c8(}Os
z0@b68bZ2OJ$T&%<#Yc<{8^Mh+22aALafXfY8xWI>kY!La#SqiyyQdjx^o`va#^P--
zVb83dfQSS0eF_9RG9y`#JjC2AhqlAam@m-h#H{=s0B5Ej1q57}Q9ncX5$0QzbUMmR
zYlFe#O!KSYT$xWl0KkozL5C?$Fvo3vXmw|PB!<Ht%<=;Oo@B;~Ku$4>tmyM%n*RXe
zG_#1psNT%YAAtBUWh<c6pE*NyjRDM^RM;EH{4^e15OaAOxM1eXS@1rDdHpF&*BNFC
zZJxuJS9d_<Ec3}PArj8q@c)0l5y2dK5v`HT-#pM7#av5E)oA9>64;Glj=KPOo_YE*
z8e^F|BhVPfyhHo@c;=JzQoX=@5P-e}=CAZJO=R-E2T5XvjG`}@dEAJRU1TP%ftFO}
zuG#QDjrl1(gwmNCX3_nZ!F-!`8<&{x$?$VsW(uf~<O<WN3o=>EE3^;GW=aGYZw~X>
zWT?qyzD4h-tIXfu1DD7A=|70%GXo1i3YkArwzi1*46W#|F&k;KQ_RfUi@p+O3#}7M
znUVAjx-#YlM~Z(|FqyPiyUuL<3Zj+FITVe#!Q|$kv5NWOR?JK-GnbDM)-iX{(TsZL
zdz7$mVD6^_yN%2x2hiBWl+1xhGxM?|NDDJK38a<Dp$TeZdbh#fTg)YDm~UskL$8bu
zrk)MBt&{oYeROs)Uv&fG4s$E5sk@o)-lf}t$$tplz07@$FnE{w!cQQ5%=!HQ_A@`F
zFU{OzuB4*00p=)$9tN4t^s2hg{E8kT512CgmrldXHGjj45$2N?s2*kJQ?BbFvvf83
z9@&^*(=KP6`PFk6=mhihB)phpT7HG-6m!@D-P6oZYSA~t3|Nj|#Gd882gH%}Tq7h8
zvi_rx;UU(4wAeb#`jLKECsqbMiJe&qy}-G!##TY{D9f}EeaBcGufv(+tn{xT;>xla
zd?Dk;Y8i+79;^vE&~}n_jou)hteT&IIK^t73x~Z})lb3U)2z)T;?25w10MRa-c1MR
z#|jbx;Lj?&ieU$^w$M@}kma)mxF8m%7hEu_gHljuSZ^*wV<>Coui(O1Wwxi`+gVoI
zkMJU#^<M{CBUmx67)&H9k5*|>tT~Y&(X0U~Q9H-_<Qw2)Sn_!giDfMrhru{jV>58^
zEK?Hvy}(+x0VIL7elsR7k@Yo&0FqdKmtf%{E3W_~g|(F`CsSD`N^H=U#`??(HR-ID
zF^FDfoqZ9&D=ao$vze?yFCem5{L>)WtTVJF&SA}RgZW&Rw>=v3SYJ~`Q$FhoWjYF2
zi{fFvkhSRyloheIQ3>!hmWft5#jMT|NS3m;(o3z3_2?zaKa{gh?EzcCauh)Kb=I9-
zuv^KxMvMO&tVc?4Rjkjbn5UX`j^f)jEF<knYgwO-!uxs_n~rxkuqHl$`9@Z^7L84;
zy*r?+ne``CrQBqFzy;UB>f4OIHrC7jki5nEzK`NB?W`)Q(e7YveiOPoSzqKr<_@dH
z3{SgRcm2`W!y3uKV0u|~w9>uHIyVD+A4^MBd;P3y6c-<0EyxEq$kM$JGQ@hh0V4NV
z7wM?%1D5a~hzzqhltLO|?WJVmLza}@IJQTu#f8v4#yU&otK+OiL72S>)_@cIo@Di1
z$FQeZS_*kgv-VI{Z-#ZV20(lEi%&qe1KWcM+(Gut9dL)(-Y>(_VRk(w_ng?e?EpBl
zV-G>63%ltYM2@gCDX?{nJ@7F^j@#HrsbJidz3BtUxUoC(K~At6wn643``<8do^0MH
z;7+k`QEiPEyXr;wbeetFh{1TXtLI}dKJ1UXVabpE;>&Q<pY7TKTmXCJvj7CLP4uu1
zVux4aHwb3;-3J%KR?%uBlx>Tm7eW|2XcUOEY+fx$IJ;v$OhmB%c@y|ZwsR^hMX?=d
zEgsE&Q~|&_cKT^Z#;`Nzq3=BV2?`R%vDaPzAfCN=6ecdPA6G&$f&C1vPZHS{sy9z!
zKSO2m$!z`KP?o}e%Jx0xB$dsfoL3rqbR!Vy>=HMKX0S);F@1%-k%A+c?0kAIXR&{w
zolG|SMGBhbu=PbCx$L3MP<oXuT!t~_vGug=&1VmVp|Oy?<8g=-vG4QY;WhTA6L7nj
zo%10?O4w;@DF0r@{^~sd%h~lRbXKtK==QH<U#8do4fa2B%taNunznP*>;v>ftzmbq
z0;y#?c0qR?yMngV4eS{wkVf{QGT@rnztRb|W_Dy9l-*?a4Fk}^E)t-xmF-TuvRmxK
zkJ0~sXlIN6gG>ioN5$lwY|RwNZT9n&K<{GT{tzDauwS_j_j}nKF34SWOf!7yW4}R*
z_kOky-8lEyr}U5<VE@tsWrJ)!Eft5@JywthY<miW4zqXVz{3&t;~@|kWxF9cXPf(w
z{l+Dz8DqaW3Yl?sfD&Ya{dx}?r`SDlz)!R1(1kd|Hqob8?K!XS#1G@Z*&Yrxj+}&E
za0fZFKZWkYoZK8pI&t{Nz&Ue1e;fc8PEaJ=KEg@Qhq9xbac4}zF^;qfZrfZrizE<r
z<NOqk&J&!meNgJod4?X^9-O|%(07uP{u0!9aas?6JIxV&g@Jl=zTE-NhqIB^h`yY6
zD5&bk$&Cf)&sji0iU3Z-MK}}4`NtjbU{1(EcoD*RYazHZoL^{R5^CdYrw4NwhmnI>
z59cuHyF?Kj{w8=4$r+|H(rC_O^guqx5j+We3}>q={65c_MWM=APW=0jjN@!y19&`V
zE)Pl*IE(*;mPF1ax_^>5@4pU_WX=zCr(Wb}>9}zUr{h~RrgChT5^!Opa|US3mcg+m
z0e^`TL1%+6bIR$pe}&`5Kw~E7TS^1waKt>Q$>m5(fxpT*VFxac^CaC)`JC(NAO##I
z1qll|&(l)Ah;ujsBG)*^<$xD+>bHQDaL#q1uaq<2mWDBvah_{OYdI$~2y;=v;d_C*
z&QVi3p^_6tHP$yc|0qGKIC4Dz)ttZ}kQz=`Ce+k(s(!;D8aNfSv2Wx&_X{MOIE!fV
znmMtdFn^O{qxy&z&R4U*wQ}6)Rn^AXy@>Mfw>Zrd?rP`cKMi~bXE76YJ2{_Iso8DL
zE(+#$arS3mOm{fWbn>U0Gw)YSNe`#~3UIxgt8~8lF6X8e@IFot-3|ks<mK>Ukdqb!
zZiusO4DkD$AFE;a0cZX`kYP^lQhNW5aCj@Abd+QK3rZhy>S@LKh_i++wlPlV0bDKP
zoZXk<#RNxB1t^o8JxS0u#aW_-<TU5Izrf9K=FlYAb2ab6Z3k`+)uKCcRrkOh<lgxX
zeNJ3QTI@J;PcDYPF5E$s7vlR9+-4W(KFZz713AWhj3(hYcRm?(<%XAlxN&t$VB!SV
zL|3Ofx8NZfPjZXL;EX3XibBe#xDWb)^Wwfuhbc~TA1j1iZ|)CN81KXN{tk}%az|*f
z<Hv2L*tb8|d<uQG04|pf^9OOC^T9*~bMw1kB81ydE4VY<-)SEf%Keq<U&6SSYiK;n
zjS7U_aBksxNJen~&W6%RF25FiQQRNC1Ubiz+6XUVxNp#U>O6NzDO`)?HmYDKj=NzR
zxOlDu{imY~HtuuCg3e9g?x$Q^B6n#AT9dfhbet%e8%LK{DpyL2%QWu6Hz1PE-LVDE
zWN;HkFzid*cj$t+%th=9w+eR!9qP^G9-+$gEbg0+!F)E?!UQgdyJZrRSGkIvFrUZ0
zP9Lht=i25_=B|KSbPNM6<oe$NqKKRM8pt*7;hh+0G1vbCAWFF3QfW^qcbw|w%D5{I
z0$;)1bRXVd=Z<YfV<q?YtMKUtS8@%wDsCTruBw_l^Cv9Sa4X^gsO7#$+0Q!eom%Lu
z=SJE#L8gIwE&wu3+@~u*nz>h7A$pVh3|)aO+!eXtTDh#hLE5<CbgcXqH%J4?cJ3V7
zQg?9m18D5zPSPv#Hn;F2_|(mf%f*m-xRbP^@8!;>?buyz8ztWRxbYO8>*oga(w6NW
zH~3co2e|X1fEeV?{S=Ku+=w@!`#!h40;0oQ@7EzR!u2VGzoXpUT$p&sT@VYUkGOru
z;LI5JF*(RMmvI=5PH^9R8OkQPH_t(2ip!z+^fY(H_aOE>78PPS@XTAN{@Rfj@g|fW
z<T+9J=Me8BiWwf}9rpuq;<eMY<IG!o3<wuqC(Y9l-pW<beUvwt2$ADFciJwy@+Pxk
z$&L3;8X8aV-U<i6o%bwVj~=|o=_!4ZcQOVe^W-i68RQgiDPG35xn8_elpZ_H`|4w;
z@#UTK0O!XWp>y5-yq_sO9KiFX1VSM1Ey_d%@lv0|2!nZV9R(nS7ZL#zXLtwbc@xT8
zK?$ia-th;J4ChtQRyu;mpn9xG-s&RYqIj_svXAC%rM!jh9M6@4XE8i+AKX9BdxQ1>
zu{`@PLE?BluL2m)V;+J?0?&^2Jc+#CDd3ZMvGj6F=Dp|*yBB%!R7aA++e4=xQ+auF
zU_Ooa7#qV*=h=lrbp~%SRn1=FjkH1J3hzBR;F&hwKj&a6i?_NJB%8OJ7Q;EbgY<F2
zT;6Gl;9un#s$n9JH*g#zpJ&+)U;(e19tMRxzctWZ%p1#t!4lq;763|lBQx-@jF(Ke
ze>rb90|qO2-~0?`uJepLAyUa3JPR#1c(&D42wlZHA%^a1o~j?BwY&q4z}N9!{S1Be
zyv`WtZs4t_*GeNV_jf35;yq3qgJxbC9Zb2&OQY>r3(t2i0Ij@WdY-rOHYY=*o#)mJ
z(!u+JzW>t6d!CNK+~!4}1Fnl_wb8QS4sTgMTDy6&)3DUTdr1G?q?c!-+Ks!sOVjA<
z<30Ni$UWZsbaM^xPOgHbLEa$MYz*<Ti{aXR-agvRJ>a#{VZveFf64G^g!gSLBu9B)
ze+BqM-f~9(9`XKO4f7Mc(~dTDPV#o%f~6_mM-*kB=7mx0ZHDJXpP{hlKlUvQI`F?E
z4;}es^qHQ6{4f3i{t*9&JK%@;w@sK*Xa290KXBoPQKtV0|K~U0%uzm<BCN;w>UZGG
zasE5E@w>Y6-~16e-S|5`rSHF-;4h(ox;wwV1iC%=8z>Cp$$vQ;GN<@j9ZY!fc?kfX
z=DQT2(VL&R4gUJ@9cF{`<^N0u{rDFtx$e*ZpcRuBz+e6qbO!Q^0x%cB{4>GuB80z<
z$~w;QGq~VF`C;+&{tM$Dtb~cPd?r=sh4bAg%@o0(qGw<vKP&@disJt?2!ql54o@gO
z&yS<Hcr4$Sw)t`Vm-b_z@qA7vytu%hq@`v8znrS=6ZwbhflK1QMIp3g{)^GzF7hSi
z;8OUr=+$aV<BPuoKAqoL0FuEEp%wZiegFsf%lw|NF{Ug0WBIU~$=7kvm&I2(fn@XZ
z-hgX4d?v*MbNMwR5Xs}GP{tsie~-%Z3-~|(0aC~hrV`O2{vCSlU*l(G0A9>rO#Av0
z8-MS&pr!nCn;}}p|Kc@_shqF83iH?b#;4(MCI15!`fl(SQ*NS)FCB$X)%<mFP+G&E
z<b%}m@5-U2j=$0#y6gF0`G9NSA8LRzjr?f|05|#1(8jNYzlm0(t$ZVu)V1?%+v$XV
z2mksz7=0%{lrk)R{7rONr=R~C?XK?eH(Z3>0sadVNgw39Ye9ziL-d5W&*w$K!~_1b
zUqW)2A4C78V1z$yk3o#`kM08ZkbmeUh&<v?zlz2&{#pwp$N4G00zSdtY@_$?B;SY1
zDyR4lmH;u$ciI3l!|z9ac&@$Rqo09r5S;l9B94OkTnz1?;MbjKJS3R)0>*n-P$|Qh
zoCK#R%HS+``wtj&5qwIOrbh(PpMo3}e7zdDV}eBb`ss1O`&8!cDrj)CL5-UrYz5Su
z5LD3v&Rwvba=0FXz7RB?6#PWxjh=#PGx|;m7H$XLOK_dG`KJZLMohl9U`G_R_y~9k
zH2MmDrZ=>oKt(^ZzrcPLZ~=m~l>ZA9xYIK%NHCAe8iNJ*|Ns5@5CM-i_Gbhgxo8a)
zJY5B)VFKxUP<mF7Ne76+1%G-2A0gQE9V8<K`|d*|O0f71Oi8rB<wKBj0s#foV+8K|
zA#z^u>IsZDR<NoTGZQBmpmlb<z=z(O7X&_Z2_y(!d!P1yiGqLaAetmNKu^77!D3&`
z-bKL(B_2`)A5*+4Rj}d$8q)*|sHi4g@LCF7%MiT(Jph*k&;EkOOu^fBa5PKc@Go%L
zf{6(@lOtFj0eG(9vGWkQDj1~_s64^laKQ5g{+H2bD-fLj7)})mqT0b034$rOc}?&!
zJ$s7<4pfp*BCyaRyi}090QfS&@Aa@-E|C5LK!xB{+QMHKd`oqHm4XG{fZq^2O%>u*
zf}8Y-r)ohSC1`2{_Fuw_TERCH&{8MJ>Oy0^O%NT4)&@bh0Ek9GWfRmi2`*8xxmob+
zeb~Jz@Hazgi@-|N*sX$2I;qqqn5l*rw*>4qm}nRDP&~0iP)Y&0PQgQ(uG@meCj3lY
zf{%FUyCc{g46a)+OlO381X)yx(JQdU=VPFE1<AKyuusrKg)jYrO8T7AJ;AqhHx3Av
zuL3tH$V`REkYFDzwC@Z48Upt~@DgRGhXq+V5E&8dt%2Q9f#*(m_)y?h36V#FNQzaA
z37!=~WLzMiCG~{h!#NoBq~MG#7BW+UAEV&KwBU)AaB)WP@+(kkFLVtA!a;bz6(Wwp
z%akuYD0EnZzC*&MB~W@;sHD(=lW^%z5OEf^{0-M!gc;9+J0iSERnbR<due@tOt?@1
za$Goj2<BadPaT7!?!sqU=*ROA&OAcvN#V267_X;r>N+f)5)RA<!b`Y?0yn3H2aZ6*
zTgZ3?oR6^S|3xN3CjAC}!YNu@`U~5ZLL@-AkjjGtg)Ma72MHHbmMU2Im@nK85#FQa
z+!^7Lg&2LP@WnRDKZFVGDK39j_z}fA!i5hgf*2uO^EF7MaMxU10#U*hPs7n@;j^0|
zc}}=yKHQHH&QhT7ym0t2OhT-1hZ98NguBzg#S4{sz%K|d4ns0QX#W&cCkjVsw~!>f
zy8~RZaLrq^{=6tGrmatka5<eHOcj3A28Yvx5{lxc3%$MJX@>BJ$I*957`+ZAE(_OE
ztp1Ad{{L5SLg8I-SwaOp^>T&XfdE_;w)bH!@`Nc$%uK%UIeJ1A2xGTGb)hgJ5|Ty2
zNGe>hT@x;#S8TCxAEnMpgke;CR4Uv}NtiO>=Y9|^7bezXN-Kny)M&geT=yijRSJh*
z0KQsyUI0=fl+sbmTA}mjaI{V+paP+KVKhbO8-&9YdT12Z(w?PB*m)INnuR`;^15jg
z$|=*|BCMc5MyqfZ{^qs`v(1pXC3HiD`rLLQUWT~2gcTHF>J$#schzqTx6(!4C9LQN
zxg$Ki9;911M8&r~LU$^s>=j;}3%hrPzLdo56HaLW?-%Ax!{2+tV^)|Q5ZaoKqH|EV
zjRoM4a7`RWabLKr6`~J>FHz2VShzn7A|t}FWB^Bn=1`D_!uQGFN5U^z;Kqc#6tWl>
zwszq6oe(Bd$Z=BGbObu5ghQDa=(KQ-86q>nRjzQ&UUcd&sCE#Q+S(!NC@Odr({@m_
zpK9?Ai7M!Acv$2`mx+_;!94Uii$0^Yjf=?dTNpedN}{yOQPKRp@Zy*#jUI)^MK9(7
z?kd{ofuXsHRz3^(3DJBih;kR@QaQ7S$Z#2bCq>5tAn7TxN@)LgO7ttGfW1UNe1y)^
zq9qiM@D?4XH=d8Ef>v3+qPSXE@)IeyV-)_P7cKB9K(zgPco8VN)(?>&k)jS-f<@9r
zuoNO%QUG#Bw4as|p`yYS@Gwl&_zmC@A^|-NB1Mf!^!<q_(G1-H(W0IJC_N|YS`G6t
zqOmbJb6zBkgNaztOBD2u6TN#GBJrXpsG9qN$Uz4#LG(C<*%C$Twa}6z`h_+m$)XEK
zq2;2ex(Hl~=oxzUri$)4z;2r8PulLLi!RTh{9lG>hZSlriT<Ee-(}I*L)g6{@}Uoj
zWs1D!Lo`cN#Q>KrdXA!+IigSp3^Z3XauVdKNW2TW^F(9x=E)Zo?t^OuqNe@uw@@@`
zMPHHV*ciBLBFhF?C>Fg<6-gzc^EbfRN=4jcuw|mH{m@-5x=Zt1Au33Lw(FuZv?i_;
zHB)r)hUh;Z45mtCa)F1{BK{&+su6Y4V!B>r$OF7V^e`NxQB-;uxF*q(t>|kOt*2tR
zo1!Lqq_l{lGa=F{s-X96n@#i--7>dCUsE8kU9^4=WI9AM8vyJSy+zm6ZBfiw_|zr(
zW(6AWh^!otZqX~_AU&dsIske_e@=kAD>{(|WqqPU6cFzhE%Jxk_e8fM0Ur>#mZNV_
zWJfEgA<-&&m){rJVrVV#KooTeLmL*QQ^;gQwB{<bjf$e4fcb}_Nz^ILeI&|mz$A`|
z@=pOUE_$>CeG{Ukls}jhy-RU{DG~P?aMPlnH$&Ns=pr3QuorLPqR&BG;0J)CIE1z!
z2gTA`=sP6-)V3bl4vW91llo5LJjzr$i=Ey9!bM#08SEYrAEoc=9Ti9H0XZf<MlYG;
z;=!fR<|=-N>NwrR_hrDH5QjFP(Oulx3@<#yRi8uhr1)(*+3zWy|2OQO62DIS126G6
za*)$v#_zN)^A?9vUdu;3dmGgFid`2$sh_x?9(Vp?rztcBh@UElnn1B9)#3$-zot5{
zV6pUN;6lXT(SquXnAHU?R6O7aK$uv365LsF=zajg#Y?}1`3P|_B?ltKpSt45J}17g
zh3c<k#O>?Ao)?>M!u?pWJq4lS#4jsgK3@FQ`ydy@+o@nDLHvMj_(X9b6C_FeMF?=o
z;`{Gmo-T?-Gw>os?0f*OrHa$m!ETzkc^kY)7jNGJ)fwXHz0h(={4-qwm&Nw`>H8B`
z#5XU)M5fqGVZ|)*yB~pMi+^Z@i5&5k%OJVp&9r#ADpoCkr9AP<@1ZnbysHd-1>%Ld
zuv931jvih`V$Zb@xhB344?wYaqZ-bXh%pqr)WlpiCZS9$E`x<~@e8zqvQ>y>E^z9)
zc;OOgs}v7d(0N0=@Hvnw@v1Obsus_t(ybbC24w|m#sAXFxK8{%T_yG6z%EEOh~-q1
z+AJ<spz)@dzXLj3#G_RB(kgDE)K{DMWy)gQ5_9jvwRUmbFr4YIiJJ=GVyF1*UZ}Y(
z_MqKlm-qxNw(f|>C{ETbo^XMuJ>q2zP}3_uPy2(r;+_VOKJgbW!1asMTA}TpcyBCB
z42a!61z=G8U<Ldg5|@s_!hP{FdNn@~|3+!rVe#Ko*E=G%xndDAcU1fmz1km&Ke`CJ
zkHncZ;KszBuIL*VU)+Vp3Gw<nXq*(gmBYg+aUd00PK%e0!0wEA`UDKxOAg%uagdBq
zc)?M^q>cGO$&ICO`;g>&iaZ{c;2&S(PLmAe!wYAL(MB&47fD|wv>lPuy#&NjNg8FK
zk4b8rfpC+2M%9%kB%l8UFWe;walm^>ZnvTFq-5_CaK=;OAA`nI61#3piI;>iAGp&J
z`4*`5mTcS$)jpD6m!i*Cvib%r_(|r`IQ=E>{zVa+0Lc;BO9x6izQ=e&B+pZ@;*7-l
zDNKY)zF<K#Owv9NV>&AlQ>-FfGVBkf5t8nIVIope>jDxbc_I|bq9s4j+xwj4Fr7+>
zkv#V!B+pB(QbIRY;&cikagr;KVf675;a2+o;01{j8@dxDcb<h8iIT{L047OZ83UIr
z`Gc;xi;{i+LTQSmC=^3Wl?2xTkS1xRRC&7O8r8yPNFHwk?vmsNodmrsDWDbo6^YMU
z_?s!|tbj<CWUU)Ww&cJs5Xq5r;IgvK&6QjU0r0A12R(1{B>nUx&zD3zf{O)`a}=2>
zl(_YSE0SED1i2>Jxf@E0B?W8%N+gG9KUFGuo=zo{Nj6uYuUwKtTZjrt@i;71O8zc{
zg&UF&9|Nh9L`%?DEqQAlaJCvrz$=icm5eGe-a3hSA57Fslr+!=$p;jwX_Wj-6Wk>6
zq?}o^<e3ym-jw`DxE4v!TzJtcVLu7C+a#$9z&j*E?*ZN^nHLSo+miFIp|MM{$pP>?
z66aIU*)92mp1D0XiIAQmy^>aXeB71vd&0LqN!1z*yI&%B4>I>8n*`tnBwfcKGAQX<
z3~fUa=bKP-U$Xla01qUO9*34;$@>g6j!62K0yio-8418c$rzO~Jd!LL0~wP%`vLmK
zB^wvR?Fos^&IoOjl1XQfDT!YxEKN(Uo`U-`lArCN)Lz<7ML-Tx743i=rRyoMeNY-S
z0l*>Y5n3J{mIl8HrB2e03+Qu}ZhRNIU8LW%LF9<kkJ1Q7rQC&(JSP2WJuDoTrcy1d
ztJKSO4Ki-h^>M(TklInQ+Fh!rSigsK*+TT4lpa2Z5qe5DhJu`uzDuiFFX>6z5uBEC
z(=c9dY2aB5%}2U)C(QdwqbH%vPdb;LEdJ8>D0>nh9iewcpww;^%m+!;RDu{REz73(
zONdlQvGX(1B8uyUO8qM#8YT^=q{dlkb{`CeOOxG!h>!|t&l4$i@`aix>B}1ch?cIQ
zm+Cp`7YukGBel||{k*iq2RdV=_vvXHCq0k^E?ycN0&+pBj)Uq1>Go8Le<n)(D2SCL
z9iY@`vh*>!;V(*eOhZkIbR89}rb<gPLDHm8cB3y{YM`RS3~4i!KwXkbC>e5D`XN;}
zUy&xQhh(O7hbNR}Nt3DODqHGm56K*<^)GmzD}9}=)qH8AE1iERka|neS|}}~z)g`<
zqX*)eG|CH}7E7P6KwpW}j^f0n($Yrsl}R@Qps!rIEFYFCq{jUi;dSX~I!L8-H64n$
zAze@gQYFnl30$=_xgMlOdN3P+T50VN%-2b4VgRt!OFQqv?*{4LX3TS=wE7`Bo1_aq
z0lrz<If%ZSQs)imYmrvc^0`&ICkwzfDUZ@Ux1@gb(YtnOC+(*?q)DqG*(rTz03P0!
z4*TPm?2=x5A3E<ywaef|w{&t6B0bW5Cn3^nlRly-#a*eDVrYHR-v8ft(q+z&xhKuP
z11|=o*|{Kt(!ZX8wjt@}Ga&b+2k9mAK)Rk@^uyBe+0Zs3)qe+WR9Zy!O%J7WX>;~S
z>Q2=mW72C=@ONBV(hp@5(m%|QoRr#D(*AEs>P1h1X{qC@P&y-Z<N#<d`-XBr4zkbv
z0Cbd%-i1#GWor}Acu4lTJ-EZNWwcRslI^1{v9l~`FDAi7=0vakBeE7s4<D87FGu4s
zS<iBi<FdjR0C$yfDV^;mE4R^^ofEQW)}z&3wsAA;ddM#BM(0VH!$J^GS<M(cJtcE}
z9et-|Npy2~%Lb^l$49oGZZ2P$#~SGNlZh^Y_{+xLLt}u<hf1~rW!vf8Zjfx0?#5tQ
zFO@}x$Tpq@cSbg|kglsx*<Ok@hRG(Vy6dbgWhG36%f6=7cZBRkI+zkE6Vv)NO14RY
z*^8E46JXfqWH%O}FGltT?Mu$f?6M&eD{IXG7bp9OJ{ue_dq@>Y7i0yL%}bC;=;@Ov
z`|2k8l4KQjbpAG3X4(yd7iD8Vz>5@Fb{aZUWuBDYN|QbM8GY%pEpGvsA&aA`vP-hV
z^w_v86O)N6vL@PxWy<C(g-Dj{%j4j(W!Gt-IWi|ItICyqRReNWwtNnh<;hwegNOOD
zClK$!{U>vx@O+^xlb*;$vP23S7t2oc!9<D7&K`}WvIp&GER!v-#t6%0TWHTyAxle#
z!RxZIHvCMLvQMZM;f8GKo8YQs-%G$%%R*?IP$OFq2}f&XU3BTy$#&bpe7)@c1hm*1
zWP!9nZ<Hm|wz)~RV>b}ZvVFd=bW>KM0I)^&!`m2ktL&37c+n>N_6xXnOE!Ntw6)6=
zwZL`AOpk$d%J_6F=eFz%+Ou@YTq#F)NA@Kh(CU^&R6$vf%!BHwdS&kk(0A7+TTbP3
zeX@0>ApJ5IiiF>jInxh2Aj6kUaO25}=m7hWY~{z8i~F((y4D}a9?;WgSoV(<fDzfc
z3;;%Dt3qM-p=|FIBp=C+y^p>znVM3#<FcI#ATlA#qQ%3c%(e+$Ov!A&?1t#H%q<f#
zGqP|BZraPU-+-qMaz8o?a!CIC|4XgqCwySgNuIGC#996v-IOl!wadUAk^e!v$fI(@
zdH8!w-W?BeT)v+w8eHWG0&s5fS14$9LN26jw!7Ss_5dF8_iXght&{Sh?U+4J`RV`|
zJS8_g1y8-?U(@UCwEV0WM7-te=#09Lyp6U_zVg9Ri1^7H-++04`InSb43KYghZlkJ
zotw}XBoCk^P_X>=0Qy4YD@#Gn$Wv*h8Y=Jm6UxHm(M#$6J1ftoXl%HAxC5R>$ls*L
zU8MZza^R!nuAAXnw7fw8a!&pX6@tXb3y;B4oP6<HP!liz{apYq$Oqp>V}g9oQYcH5
zKS3LVB>Da^h$PG3kizYYat|t1Ns*VI2T7I3_)`5@n!NrDoJyCkcn$ardHQbvUXll_
z2DvPsq?(>9@}6+0$&`CcpfO86eh?$fmbbl%#vJ*`J&;^^lm$w!%IBPiNS@r1h*`^*
zzZr>HFOa{%goQ$R1XW@b$qVekU6boK(*GYTmcLd7M2Y-ky2VT7qZGy|lfOb&OSzmw
zo9GI;iAq+k%a8tvzDoJNBN)sL`KB|Npep&@a5PrSJLnl$BR@^2HEZQxtUzC#d@Ds`
z>g7fBa%zyjo`;!fls|3{(j;F%K|Wiv+@lFHH|1WGs%VjKbAz^4`7S3Q+T`Pu=Dj7~
zkphu+Im3j;4*6@e|Lc_Bq{6`4@;FcQb<4w&AlW0oZNPN(%GI&Za#tQn!M;BEz^@?v
zat76U+><-d-83No;5U##o4iR4Iwbd`>Vy08%jHn|Kz{B$_%<w8rU5u2XZFCgQMoq-
zdLPOIshaJP+-?sHj>%KzLu6cj=^n_0{4_1XC*?QYpk+$_6#ZJ$@`jV}X-59ZTEOiU
z*_3;7P^^0r^XsUv9mJ0?_n^Z3Jj@?bd_@V9!-`DWB{?ZfbPUj0@zD+Fc2Qj04a5;e
z_G7>wRcxfH&SMH+DvCL-_=w_Tu8N(N;M^1!Xc2uvv744vJ_;94*!5K$nGNEn$lL}=
zf5l<iOa>_0Y+K-4ph7^|n;^w0ibVx0rs=5{qFA{F+!;j)WpqOoOXy3ZVTxmvVmzxj
zb_;-T#Y+#MG(u58M-Cztd*U&OD8-LdmK?3v_6UvV6a_VKCPrbhft**=Z3iG$A+>{K
zoFe-F|3EBWvGoghdO>mfFBnWvn0^A6sF>sepQPxdl|{1R;V<AWDqN}jEk)7#E<{ol
zH~s-hQ(UDuak}Emk1>`E#fOJs;*w(W1Wa63d`5TU6-D_sFrTT|Nin-DMbr^AW-ET0
z{S@xM9EIgP5P6D#HPDu?$UY4(3KUjaS{Evcw?k=>LQdJwYl^79(O0ZUltN93;{3Ph
zD^>hJ3(s=JVmpXbDDo&YbY1ZR<&`QGNkt$x6oquYvPz+N2(DT&XB1<pQN*D_0N>wL
zv{T@vPH|=}%-1XG={4G**g#u>Muj~k^_vvGC1KdjiiLa7*Q$7zp37|tFF8oN;@51z
zI}}=adv_|14nyR&!bA!CF2yYq{Jo=Ck^wE<ieidg_b5IzLRqh3Ijx>;cNO{3@U2g=
zi$>V5X!eE7J%xqJU<MTa^-wyfDAvKXA%%vHTi#cA&=veZF?%7nVMT!-w2dhCXM>C?
z=2KD4LxtN6%s*1}(ne@ZQ9#kBafPB2fC)uLE_6;RVkizWWm7yw9~+uh++t(eW)vLC
z95^WJC=cMMWCug^pmK}?flf+m2>P6reTC5NqKr5QFODdyhah=W`HUHsjwz!)0dZ4S
z7XffWDVYZmcjb!jA>ye#O0@*1lqH1_@lw`{z@1jw>ghN1R&KrlQ6J_0mocTj$~7Or
zgr9PXE-!!Os;}X9fO0t{7Xp>ro(4WhIamRaU}XxWEkl&rli<!MZ_phRs@ysZ$uQ+4
z?KICSuXKWhE2oPwzzF3C#bhIub@cX*Qu1tKXp2_9w*#H$l;t5HG0MOHpF&oO=}=Rw
zl24U3amuE%a4lZxun5jvP?oQRngr!$B^nczyZd1xNg1&PT(a`s58y5;BYL1ZMHzJl
zI#ZPgi{WURayvzq(v@)<Oi+fh?I`6RE-AYxw0l{(;YldXQeKh+n63PbR+TwQ1(kE=
zDnHx+a#gu|6?Eq*k6i$luRNIwr3K2_A#k)%`9&>Ak@B4^h+I?tL~E{M<&U%mDN){`
zKwzoz-$sx!<$oN&%az`#^!}?*enf%o>q`CmaHdlEsuEt@P<n2L?keT?8BkiS6z#)&
z)hKtI0kBrNC<t7GGJ?t?8<o?mA=0EgOlzNJ<!4kkb5r>>J?>hRee_swRrX(pg*K(b
z3>t4K1rIU6PNn-a<^OIgXa5JgT}r#-kQq=8z60HZ%KSMXL&_M6Tn;PGtboXfasxf=
zN0m1E%<@C!#}oy6q@18v<d`!2MR1eKO;mJ0rSzT;GOf&_kvXWIr}Gbvs$x1pdQj!G
z59SZ4h8}>}4y!((gtU|Dhf0XLtGbs!jfbk45-lfH3qFK-Pt_=$W;&%R$bcm;RXpXo
zPph8vf(dVxl|m0bs;LH;@KwF{6eRsrCV%w#tEy?+8=xwty>Ot)qZy4ssy#H7A*xsC
zx;SG~?JdM_AFBF+q8nkVR?1YKRduz43s*7ec@w3o^8hefm3<j~=TxgG_#C5p{5Bjt
zubM|OrC8M+Drk&TX{d-NUiB;;QoW!$o(w>OYNH77MAc|8`jS)!UI3S@a{CY>7gaXS
zpO8sW{qZk4Q&p)ga4JnT`8n)fQcdt7nyJdF2A8G!<tvbE)z~B^F-J9jAGlmq{cYf`
zsut|RB;=_aROriBIaB_xKqVXoyij$4;><-Vo;w`9ruv&o1Bz8|)3Ucj^{(v?%w?%+
z=SFx@rYbxHnR3<Z>!G_sW%mW}*Hw*1aFr^*D)ik@U89s}jVkU8$W2upt-f1Siz!Ln
zs&b)1gEm#{ehlrF>KQ6*Z&%s3f$LPw`4)Y*RYR1c>r!?91M_!Oo0*h<=vJLt0n(#t
zrc-Xcs@iS<@2ct?faq8GQn~FtmFfr(1FG+7@iM5|90G1gb^ij)-&bYGfqS63P=Y}W
zs~-Cgu8pX2T)~a14$xZsp(^t?%*>doG8K*Es*wlKGNEePL+`&y)d8yBn^N8R6xya$
z-;-}Ms`$S_?A612(dVH4FdL(HR1fNaKd9bAFX}_;u7A;ZSiPT0mYvj}^+Kt$`h#8Y
z-bH<quCgQQ**=gws($ZD5I6O)Rq(=HojU^69_ov8DgSU%T}j7UJ=Na!Xg#G)rBJk&
z`phMW`l#noF2`3rKoJ)|bt411{neB2qAx(LP6sYf{VL5`ka`sbK7-YJYw>G`sCDl_
zOQ_n7!nR@Rhx9>_v+628C<|AgUk`YM`oue!Ut6R)ZW4Y+sSnYzJ6iot7}T6o@B0gC
zV$?ow0dZc<o((mz>a}!aAztlD4~h$FF->rSI^F~|iRw@28xcwBPie1oQT=l(bf&1e
z6!uM3FQsDvY3fy}5J^|(MFW?i&g%eo$);XU2Ct~?D9x0qKG1||%ToU>Kx4N0oz+m2
zqxM@1*K*aKv~0hsPT;^qk$U2N%*8eJ=6v)Ot2a_gv_yT8LLQ~+)3eZ5uFjy>eucWY
z1%21mCAH|QQuna|uU6}+l&D5+^XNurt@>43BG;)u&jYYQy{Zg$8`UT1ymFKJ##*Rp
zQ7?H5eXZ(RBL>r^erX1FZ>bY0lGm;l=K#>59(x^tPW7fgA=#z=#~YG&)axmK-mTtV
zg}xs3yDjjdS6xmk`n&38TRLc;dNExQ{pz&eVd<XwCZ(x{)W6k1>3wx}3Di7L7t;=E
zSRF>+VHr`occO1pz2G&#AE^(`Kx9n4k4hTG)%<rMGNERQFu{}Rr@w>h8TBhUkhIsx
z-T-mX{PH3i9W^aH+W#HY)KJv=kY@QQn0M0r{sLs2HBsImE*kzlh#t|*p%YR^HI{Hl
zx@xZWLefn$LzR~&H1otT@2+|05=1;SuUJ7&YSKFa_teNJopwsIu?iyIn&v1p`e>e|
zqCa1aA&>G8ewu$H(CV-8eG#pJnsX<B2-3{T1_{>e@&!4gX`|3ksK)a;W+qG{JAz;9
ztj6U_m=D+Ns>UE9G)ZrvFG{nT4kblvG>^gHIgOa!jWL>)9uPUNd4pECu^Lqe?8R$>
z-lhM4bU{<%g4P5LpH`KL8rNKmFiCSg8(fO!Ln^FK)x2$lnl#PXrI_G!&2AFO(5NY*
zc1bfsb}wtp!SL{kMo5{ROwFArxSgeWngWQ~nr)+SCPy=u!qmB%ZB!a?RpU%0<+eP{
zP&_Q<Ya&*ovq0lxfr&!R&lG9BrrB~8eiv(k=@%{0bgYD<rJB98i7wOdbD^eOV+cWC
zg(mU{;MX;-R2){RNgIcj8yZOr%vWg^QG~WyQ?wO2Yc!>_B(K$6XoE<dO>=cW*m}*|
zw6AH<G}At;QS<%>P}8Jor-IXFjSrQM+|*38K%`Z}r8s7rCOj9Tzoj|-D*D<r-%*C8
zL$hNFK6PqVR$}zGH7~D6UzbMS2`}zwKK%^vZq24)sP55xMrBpK8e0Y>C+=#}gMjGM
zywr`M^=n?COa7jw^aYRs&8xH|7}Q)`2Q~LKTW<mQK$Ax=nPJT<TJ$~CB+y>#k!C0l
zWK1KD0U6hP^f5*_p<&bGc~Y}+6WpHCL{NxxT4P5=M>CpdZCq%x*H(UyP6zFCRA}d@
z4GIF{pmryDaY*|g)rcL|c07SbC++W4E#a(<iiUX?ZPgL<9nrRLg7-(YvBQ{zW7<5b
zy+5vf%M8v{Yo7s}o3`>cRG-j#N`Z6NKED!U@z9Rz=>2z6TTgLYPwieUd^@FWi-g}^
z+MjNNJFP9LhBj|)ApQ0}+Auot;Hzy51LvnbdL3|o?H5G=1Zd+_@FGyVbs9beX_>Tm
z57tif01%=r7z7E^&Z9T<S?vf#CBwCfm+AX25n2lcj3TwOmqAUGR+I`CqqX(RK+b7j
zcnaoYw2sZ-Vzt-lkrt=Ti3Ew)PEoWwNh|k+-DGX&PjKd<)<}Ez6s_YBMwqJ2c^3xL
zv@s><OV>uxrawa)_z#p_(vISA557O4t);Nj6|FlH+A_6&&=(D|w5;85CR_WuFZyz{
zk@RTE)xIglJYCgp-vP-yZPH4ReC>2DOcZEqXdzXo-A2bvinP0n;o&vy#iJm_T4OIH
zOSCW26<DerNq|V1R!|0jtz5f54!%`r7t!nRx;9vkX{*$J`w)m5+Omz{s<g|8;8V4B
z#dY{yqdiM2)mp9E9;8mIrbs}&R!3=s2JNp5C~MTd=?AV!EB*zzX6;J`4Ev_`Nm?Pd
zXkBMPq*XiY1uxoc+WBkHc}x2#Wk1`s$EiHIL;F3IuXbv;(s8fb+K9&>(xvry2EaSo
z@7AHQTe~|AT#vTV4UYC|&r`hVu6E@TNcL%8qNPZ`_D%ZI%ss7?UJ?V^nKxi?P+Qsy
zZb;jF4cvXL?YsYA>47#T8;D_T@hvz!qD^=nWK_G7c5V-~Q?#iZ*LLQDo6ru?%3xA^
zEC6Imo9_t|(^~ZcD4o&vEr3#co!~GU9dxTGck8ILe-$1c)OAyZ%^{sTJ+2Px%=Z9y
z(*0`N0>7PgF%A%Q(M3N(>k-}36f_>y`BTF3n6A7Mh~v6EA#}Uy_Rz)RrsL4Xc0#ve
zBShSF(sFp{q5F6*?4H#9LXU1wUCM7TcuJQViUE4*vM9fLTDP5EF5Wu-|6svKH#OUa
zG5PBLp@Z{&x;H7B8mKFwYMKz8iGjv5y2!`Dh3e*>gYGb$J3UO!>RzWxs&HK#g<2wX
z5_<SW>RzW6NtA9)H%vt9Vkz}}PIq}bw8ZF~DIR}bmrJ*AtS<B%`r>rI&7t#u@w!En
z*u9`r6~aV<?xk^vChBBsA(N#0k#>{Gy8i@dyr^rCKqN)Sej1IbIz3(8X}XJ4Sdp$X
z*28XwuH_r}dr4Qw2H>*pnL7A%MdwHn)=XX0V&JlLkws|C*3}_)ZJV2;YkL8$xw=4i
zsJW`+<fAiBC*h(oU-vY{sS9*Zy#~JvbqAJUW{Y&ME{Di9o!~<#E!G8f!;2E#DyrQr
z)rrIqDbsDDBb?>BWwZmT(7EwJuIttq;98~br*(ke(8cWpz*eQ}QbA3%Zo%tNQ={vn
zyQ5YYLCgI*osA1%z3$R%^fl<_`T^glTlpy*ZPIbRLtmTDG6_rVIv0vCb?6f9(buV~
zrQ7JX?iy{!x^!-{VBwA~i&ll*x=Rv_tVj3J82Wl`x-LFM2X)4CP;+0mm#+K=x+4@c
zAJ!#OuI-_2trN!dNS93k;xSziEilG)ja1Pzp?i@kI3{)5`@v1=-tt7>v~E7FuxE6C
z(lgs$e~PBWLGLXC=cq5HSj9p8r|$!BNN;m(!<Y{1Pb9(%C%w4>#95z6l`Ag#GTOr*
z(SJz0jidU1KE%+D>4lVtKCYjkLLXQC;_cAwrgx+=m=pSUs2s&zFIkO74}E9@$Vt63
zT@ar7WlbQb^uLs#(M!LS_Cu%jAKD(rc)j&s3W4|0-}o3NeD$q#gvL*Q=RbJiuV1kN
zJ_YF2=V35VA2$v_kiNePmV)(x1Hgso`*l!yM*rt7kWl^2pU@blH{XT9v-%g5;KKC>
zqA;To`YnZkN9w<xgT^TR4xSCVqxF%WV4&ypx4s66(Ko&b;CcPsUqNE^UoVC;ar(dM
z-j3G~eh!~5=+jODpP;W<fyPArOcj(S=`*NSD_K7sgT9OUz-8!5(Z80AzEpiLtzy&k
zzZl>}y1p(QT!#MCH&p+5NpGaERi=I!4<t)3-G$C<y@&-hIr`01&7G@Hb;9Vc>Qz)y
zo2O5vO?19KaT`Pm^u08QLj6NJ-BYChVF4Pi>357kq*(tM9VIEz52`V;QoXhYT$$cG
z1s2NnyjLjyP@&(n5cuo*Jz(cn>bE})gE#bczvBn0(u;h-RqKlv0#Tzcpjxk5y;nNa
z)ahqeg4F9rH89wqZ*xLlqdwFNTAK8EIWXU>Uq(x|oBGl%=xfoxtHWHh>Qm@kcALIJ
z0TJ6RePA6r+x1P98|lz*y$FMy`X&zm@96h^4%fQ%=N3VvN8kG#`g-*WO8ni`zdRoz
zeR?xxFZ=Z|R4;c=uQEbpK))~-b1|sjSORWH&)N;{zWy>DM|hxbqq>=4{cRoKBQ|{v
z1u{nU$#n4cq23e<HIMWub09jVuO?5&^<fl>p3v()f#jrqO)Qj7={s)1i)sDiw9A>%
zKS66^dqWLX4LKM#2cXf>Q1dE84jTTXPnR4r^gjh<hYiVhp~cB?@*jBNY_LrqK&y*k
zUM$EF!}H(5(osVJr3{W4iYR=0++g_+YFrHx3R$`tb}j{X!oZ=g4!9eJ9AL@A;I$X<
zlZJ6Bb@4QOHwfLQ45A_YFkXhIc)*=DtbYJWAHzqKJ@GZX{UJpB41P9R(fAwo(}pv^
zus#(e(C{t2qJs?4U!pJAP;(ZD5W_U3+Rqq{7o#!M@E_#}!VC#fXgq6Ja|Lr5ZdgPK
zsR+Y^FF+y<C1KDKWjHE=NVK7oo}K3ng3n+#)?hddLve=Pe)RN;H|%^4G8YVi<4~Gl
zcrzWICK|%1bTY{xIR%kqgP!oIh9m9(rWsPaF+u5uL&cE1Y}iAa$}5I0s_o7+FrP$U
zmf>l-j<XG&KY+_I-2WHwTthj9X0ICdrlBv-@Y@XS|MCq_Q&^+G(Df}yp~2G`gDEmN
z({ufrVb>Cf78`a_y0yem-wje~D7pc=Wd;>3@XHN-7r<2*u2QAUb%XmXI8$lR&H=e$
z_?m)ORR$r2ZL19r?}4i^T%wz@*02L9Guzxc!`?LztvA&D0&NY3<3E6FH2e?<nI^+G
zOF^0q(Lckrn}#o_WTnOMHSJPb4W6{QYcu4m0N|G4T@FaQVUYve?l5$%#;kQ3%C~~t
zHdOouK$oFo6X16YJrii`Hng+xQ`mY8TWO%ZhP)+cy=(ZR6l(emt>1&|H}ud)Def7*
zn+7*vDEbTr2MtTPAVY>gdcxc{%%TJ64-DrPLvq*<OR?M$!(DoTj2ikVuk_IH{8zC1
z$Y4<eH)imrAmO;-wJ$KT37g?1Jvt{10d$p48H|*LoHi8EmTSgvl*%mZjaOTt?V!=C
z0Kh}W^=Cj18`sN#cQXE^f~2#Nvlg6-@pmc%Jz^A|gR-N>I@${#GkVg4?YL1-hp=3Y
zOP0YWH{->7;7%BAw`i5+ZoJhCH6BJEdx)MiI#E8_)A$&rR!$jzdkt#5jL+SN$Z4Y^
zE&05SYoCV+A7jN|kn}Ys90BKN6jJ!d-{`atjR8i~HQ;VCo}`sqknu9zo54m80YpNK
z_LPG?V;r@82boagda61KGcMW&^Jk6ybXSENGdiI(!kB&@_(<d9w3LZ5e)I@{Xd~lq
z^qn`R9S0!R82L43HqO}U4H9p>c?ffO!C18%jwTovzJLKH8o8d}l8iH1;F68I=fPfz
zaqd2Pb)*{S{0ZOEj6SOYOgE0KhQSPDSRG7UHZGttjVs3RBp@=4_vpczWn5!HU$*f8
z<+^i>zfce=&v<%0MDmT6B<L(Kswr(*XsmYzS7a=us<3NDFDm3HHuk>`w@ZxEYbpL&
zYJ7s0GG)dsp1_wIeHX)Eh4JVI0A4p9r2C-KI6MjyH;k8V0bgZYUkX6AF*gU}tucN^
zlC{Q@3*cIv@dTwU>x~{%wA)}j_Xr*~8h3pJktSpIXRy$0T#^W7H;uoFDF4@D%y|#3
zt;TOhp|s6-|2z10%lM`pWIBwv`*9x`?GAw4F*f-@cen8ws%Yvlwq!zguaQgJ*1N`{
z<IvJ)yiCc+eq;Y@;O-eWH32tZTrvYPX!N7q>yS}JUpl*QwADkIZNylVg3eLn5jw!|
z&}gCs#v|jEH-H~A#?jEmjcb3y4>Mtm(qJwojTKZHFlGGkQ{bkJJAZ|vGsd4N&}47A
zL8~lBQ`EEY@Sy398~_fP_zxg**rfdp04LKQdtkxYbnPfCxZ6yR_@Ex9s(Q$rG)+)x
zx~It;1%szd-l;I}Wy+?4VjmNq(zL#&r#pc6Gu__~-TtP9gXjw|`KcipXv(FuWsqq{
zEOZ8&F3=gU5Yv;CcRXX-MQedjQ)N52FjH7Aw462B{-9$C;iltVXpJx}r9{mI)4%k=
z?F3W)DCRQBRM(8bB%5SAq3xn6qX&Q#lOO#jf>hI<IUs4Knzx}l-Lz^RlxCRrbYT#e
zOm9+{?6T?RE{I$)J(&e~rs<L$M6yf;6zj`2#n`A+Eyr|+VzarXWwgGzYHBM5$uqgp
zjxpa9KueJV(+jj5EHur#0iTLY^U3ZtlUF$UicOgZ0WUGV7=*r3Q_SD6TV}fX5>%I)
zzMyPxg(+hcjn_?^DZx@{vXY}WOyd(2f2lHs(?hq~bTJ#9HKv=C0jo77P->;lbmCd`
z)teU5W~afldJJ5n$-fVhO{O<<0B<pE)j)TvsjLi*ZKlYtA#%&)<%KzHH+^*ku63CH
zn+MWqI+%jS+a~ef@V?8Gyr1%acTAW6!_;(}B58x&WBQREG`*%)`s&VIlc61reWrIP
zP}^^cm%-pY)3&oPIAGc|2up*eQc7(OnQSj$p!ZFeUc%M+z_k5eG!C1jb%2kU2Eu_G
zHDyu4;-N|PJNh1(HZG#`w__&O(?E=yQcE!23Db{rftWO{JPh+wrUUdbsA<z#+C$8k
zzNBTWy*Zc4^&HF}{Q(h2GwV;l51L~r1$D^mP3e!r=4U8M?qq(63lE*mVJFde)ZB6n
zgE(e>w-sI-H_zDsoXyqzZxDcP=9j5D`h@xO-y!2}-b@F?Jj|@OK~9<{=>GLIS8oL3
zlzGo`G<un(w}3ls&iD&`-sW1WDey5*QJsUYd9Dd#@iQ-___V*dbs<QA`6&JNf#y0|
zfd!eDQ7kvuX8w@!fFb5t|Ic8X9d^TuQ1itla5&5yLiO8c%~v{s2sam3VN4NbHhoAX
z()@`D(;a2b3Wi9u`3s5=oilIw4k9t;#1GMU-t6}+yofdb90bWYbMzZ<G~Ub#g6a$A
zWjQdPV78s0+*P7^?SE)ZGAn2alx+Sm5#*wI7e&NU%&#wk(p2-hw?NX&eRN7D-Rwe}
zh75B{58#)~3aTl%Y+gZ2wkzg07C|J_d_<3V&N8=9VQ#khV<Vi&F>g@-kZV3fhZ?S$
zSKH{gbe?%1y&Ut+m&brFFn?hMDKy`ohcOkI6LsLOnK$`Eve-Nx3T-9k)l%p#HGfQ}
zw#v**T1;Ozr&1)Y%3MPG)oSzG6iTi!-=%dzt@-mcFj!~yrsJXY=86Zf*I@qk2OHEh
znt$sA+hlJ42_~A&CA4k6X?E$xB(|70_Cci8{3Jb0+RVvRgmBB8zXxjC&9j^!*<qeV
zannxoW{MKrHox~Jly#X^G_iNgfeYb9xA{$~XzwxK`x1a&^UAXzcg<dtbpE!_yx;^}
z>^IM%la=?(!HMu<!0d7W1_#Z5eGW@QX78sVa^HN0j<P&3XVPP5*c?;=OC#p>nczmv
z^Mb)WG@odM?nmZB6p<b?Z>6(#<L1A|p=`qZ%w>p7n(sad3sdHzXv+Uho8>h?%$SR4
zi)wFK*auMuOYI%_?P!VCU`&TC_nv?@CyUc-AkLOLIvwX?*;j_XBbLK{AV)1LX#eJF
znW0son<a)Kk0&e<J?J}W$)Zc%)1rP3+$oD}BWBdga^@_Q*-l#o57FsuDTqa<pJgE}
zfBh|;6W{_YH>kKX&@#&kF39pRRVD;mcD@ANA(lh5zc^!AP0Ptp%XjoZ53{VMd-JSi
z1qBkqEe#(*B*GHRgh-@CdI?;Vg+melXiI|xlILs|Um1oSV>w?ArROcHUdQNTEo(Y~
zkFz{O_gK88HwU^eSWY*BOR&Vh2yKa$!+(J!Sws=QC0owW2lXym^54W&mSWjOKVhn6
zE4@Y2EYHv+q+4<g5XrD?r<L0!iwDKbFI#LWv=F>vd5qqenU=8U(VAs3-2x)p!l%#c
z<yg+20?D<!CIq=^aifPxo@F;Z(()~PJkVHRxt#~s3N5Z(Xe_e$FT~KUSsLkeQf%2M
z1SzrP{67R>d50oPWfndaG?iPn{r~^zRajCf^mpB&Y6hvalu^?6hQ&P?z$#11FECMU
z*-!>xjb&p3hE{9Y=ZnTV%bD8{skbbzL0^L<o?^(2mRWQKHd!oXaHiQZi|+fI7LR}6
zcAKT0R)x1Lk5eH?yXBMBbpLf&KA^~Sr)84|uDRQmmU7^`EL-McF78<R=p#DamJ_7A
z$D%EPnqJFcDpI~{nf*HeeU`niVZ8m8zkh|YdzOI^C>yXuQha;RvWS9<LzY!i7`$)U
zlLqp@^63AiQ<n4#lz$kp{PqWAMlJS~vU_NGYB7M1EFVN;Xk(V&j)II^{3-A`VfmpC
zK22K2s4Q#BvYW2eY0I*M=$o-@7zfVYS~C|uIan1>z+Xq}f(sBiXdR#p$ssGY6u6tL
z2XDg*C+p|fC*%MBSwC-vHWzCHT}el*PrnPqQELHx2IiPG;SKa1w{j?I=4#b_0!wbz
zmqTIVg!OgGio07k(YaC&>-qq2C#{vQ!IG!-eTrP1vM#5Hn3r|i7#dGoGczISZCy}?
zIrOonegkK0zSb+WUGTFmrbmRo_0tI;0<68eAQNak@g@ugS<kkC3%1T<z?l&1Q;BFi
zV{Hh5woq%UH`Ih#gD4vqVXdX;Mx=F^cJfiyU+CA4u@;7*@4WTmG~lt;YI+7<u!hl_
zJ;7$}2!Y>;R!0gACs}2*(@eI$LyxqJRt9}{Ce51PjhRWeuAwMjhIRO9h+MLcQ?<oq
z>oQ8$T(S1k0x;A13FZH?tcMPPWLsk<A(><SMFLB?*4Y%mziQn^Me}*q-T#2(TWzoZ
z0GR^o-bQp5TK7}fx5(;8WwY0;sh!YWYz@x<zQlU(TaZ%gbM&p1GHdaxAmvs)z3(fm
zPC`uHb!$^UMqg>2SB<gUu=+m^FRHAaKSHG1T66<_HP$g7{1mm;a}?pJv;JzMGw$`)
zopc<j!5Z}`5RKMN*U{Nzy-uDsTVKos@TT<=C7WBUR;t5nwTkJwYO@B1p|8VwI|$x)
zTFdC&c-#8t66ox*rl>&fSO>h|cDGePyQ3a!{5mxDTFn$9y=$G_Mfrz5>p^;K^;>-%
zLGD>!eS~2TSQDu*chI`82(ArTvprz<zSV9UEIqK!6G3v=I*azgBi41)H)@Thhwek`
zd%L0Yk+tX>z{jlfPeF3rnh=J*32XcosGhXS2cTujx<W_)e`VVGI~8j=tn+JwsN=fv
z8jyqQ+^NFOY29CRxX*dr+iWOxS@%@%|2VqtxGbwLZYF6%EzPW~)U-6SY}ho*G%K^L
z%y;j-_e;aZ%TPf!vSfn-q5=XA_D~QI5gCeX5K$Qp1QlfdzUTMX`J8jly7zsaJI*=x
zdEv}n#)|i$+l%2(*?e!tu|b&kVLV0~8()T}3@m<(pPvEnXS{b8!~n)0l=ur|_&p7~
z`xu`X@hb;04&d5_!zq|??{!!TVXU|a)=<U||H0ERMt})mKVvpc;o%I<ZvYXD{Hrh+
z%~-V!=3^L<o=_UgXr-d1IK~A%SmGI9Q^e%}WBZfn=t0K2zd|5^(ZK*qBIEcGup}`K
zFGU9rG16+`j3b#5No6UA8L6v4J;J#C2IP-27ViT{VdT>`G?k%v3oL1j)087P#z3tG
zULeM?PvKz(;|(K5CX?~&1UQc~;%M`Jf^p6TEGHT6iI6+Rn4~~N79(~L;@OPSXb^K4
zYAQs|buhRTUe99`Q6em#A(;-l1&n#Y;3;HWxeSMk7}HB&qL?v*9^})EBySMUFx+U`
zC}I2~ftpgr;oIowS;i}A;4EVVZGxq8MsFUl3Wnk=l$~R|&<fR+jEh^)c7d^(Lb^2!
z#|*kpSIc;XE}hje4$%rw&nTt~&X*XxjWBVUan}rD10%x~5?2_e1t2yuX3^T%#Q5wR
zw6!vh(i_*ta9sv3+8OgHv)aKp@FIwvjK4-<{wibrF>rP<Ufu$hYm6xtv~)8<9S`x#
zTxTq$JJ3B0%?H4G84GD!*T)e51c}>>ls#y>!+1Xc=I=6IpgN;L#%_wv4>4FT0o-To
z+W^jCMl{{U8eufdhL%T+@B885IHR=;Z4-=63L;H1zEDG%D{~`#7r~AB&MpVMac4f=
z2G%{y8Pym|59Y3aF+!fqH}?SZW+vZ(Gd|3`HgNhfOP_?n0A@OECj*%!&%xk6X6zu^
zLYOsFi5SWZrhrcvGn!`G2&StFZIR4pZ$eoVQ{V~^%Y2%uf8v;2BYl4`p84Z<kVs&P
zwn09T`SCb(Co$b-p%;gltLxy*5$1Isz)|KFD$Gq|I*r4NW6Z<!ZHsiKpC_>6%#SRP
zJHebz6ZuKzGp|D+n>p|V+H#m_?*im9+iznG3z(-1Ay>%!_vkdde??4D1iU%JTyz4u
zOPF&gV_(Y5{|!9l%u5^KS_RWP63(1sCQ$~girG)M11>Yq)8f{^<kKvFg}H}LFpbP7
z{)1c-b500|t;{!mh21u0JB7R2nE@UU=wP-{qNJ1A`40SbTxIrN2JB)MQ&i>}a}#YM
zx|x|LA%C4&{Rhn7VE*6^>?Sk)1IYI>SDXXZ$Nb9x&VHt79qis>zC&NRyv?+Dpxbwu
z(NCij1I#18!tOn$PXSa9G7q#vV2Js-7R39^b96`=b}*Gfz!B#50VsXMjQ$Vu<IKyM
zV4Ywd;lkh~Q~DZu;lg^o8iKB@z&GHN8%s(#6?aw-{n7R=R>qg;_8!&|x_IQl($GTh
z$@<`3fW0i^aVYa*^{#`QH|s|_%lfd+h5`7p95-KwydUceDv$JMP4@u^VC{VuUIen-
zKLXD_)~e5-G>BEqf|_6!Ho<t<Sbw#^wNO@03hailGKB#9S)r8u3}-2xLt6yv`Q6}*
zW@XSb6T{k63-ht8OiG3vV102177nrmj@b}QV7;^yo*rV2ZG@#{R^UF!A7<64pe=>9
z{SMkvS&eU?_i3!)_n{_(b#yb_&SX7`f|}#34=KrZiuJ-3$YrsV8=xhdl|{2p9xE;b
zZTYNIF%T$VJ*WUnF{`&3KAmR0`XklWoMEk_xWrl3yOGdc#ww@xzMQ2f2Wtf@`8>Qh
z$LgB{VkIky-rw`AZauVBv2y4Yzrd=Egr#cMBD#8Wk=4Bc%4%3o{su4VSSJ-|t7onD
zg%_7tT&jq;%v$dR(7>wwjn=;_tQjf@HnJAEfwh_C6#*|=Sc|7YzLhmjD@Yq_NhIvH
zv$zz{>tMyvQLU4;X+6weWj#;X?Jm|k$6(?b>&bQqbhDV$-|MV6Z-5?F301B4vf8P>
zsE_p%-MPNasxi>}cZcP29n`xl;~=O5EIDlp@3EHCIyA`okII#XSWmnTmiw&L58%ZE
zmeXbsAF@`@hrlpv)`tKiEN>gYBUXh8y&q-GR011g9i=?$IBVeqzy#~vcz8d_n(-&V
z6iZJ9J`NZ5^E~vzm3_4tz>Qr%Gn6}<{UjQ9v74J<cQ+ed!qd&}p<(l2KRyTAJlQ>E
zVA;zaW&?P!udN5CH#?p_#Nfl;MFoDo?A$NF>Bn9`i<&>Xz!z-+?3!}87RVlX8epG;
zUEKtwLF~*X@C36T%ZEe=`^D7&q3rvKP!q;JOcj*-+3!-`B%B>M4}%cFev|~ek?eaE
z?2BT1Q}s_Y`(PMGCWc+i0ElIK(R&-mzD{L#@$8x{=)?hbrxiL6va{%9o4|GqrUOl6
zUrz#>#IDl7#3A;xOJE|Iy`QG7!|Z|Y@xvZrkNpONN7;>YK}=!iT>&wb9q<lxr?H=+
z%a_O4k#9j+I=g`u`V4kF6?tW{1+;)1XNOI~(G%?VcSB1SyPg)8Z1y6D6)=bGM78_5
z?3ZZL&108R0xqBZgbmsX*a%Z&wq_rH2J%I0ExmZf?8stpo@R?EMSq6<eI}Hau>Yl_
zbSb;waj=|aUpxUVW$doI5HDx1&4e=*?1K~&I>&y7ipVS3cNWt6cb+}qg2pQLt?gjF
zz;4L^sAgZN0`VgIRSxXdup8+Lb}hS);zf1rc={>p*{gp**DkStpmW$|c3cgJ4eZNw
z-o3*9VFYcBY&|^}P3#gHr)KuuWl+|_-btbUR(6S<zW>t3zTgR`I@w3`;JM0P`~i5n
z*pmI|%r$n>D4gkL4}`+Rb@on5+}~g?rgY6s_S;Lr*~7l=gtlJxY<F<>vFC+@*v}rO
zr~4K=mD1?9*&Mp@aEF~w;i|jrk0{+T!2S%2qQmJPdzCv_2iX(b;P((ajZ&lc*>k9F
z`~kZy0Ioe`PjiFBFx$T!9*(d(sKVzFdj{oFN7+GC{W`{uSHsdc`-vTpn_zo>44sqg
zC5r&2*lkC^;=&pK2Hke$ocD+KZk*V75OM$Q%vMP3;;5&9?&iF_7P|LvUhG6KJUDyL
z!zWKp1mz$0a&$C_d2x!xkoV?vpM`)Ar!flxzMO4=u;j<_xDGG;Id6UmVgTol@6g{s
z&NRwZ@8fv%fF+32`z5**%<)JCONfKxL^p0jIa}#gLl|e0&b#|LpQOOka1Q@-j70=z
zIu{;Ba@Nvs5XE`L116$5Ke3@ZhQp@VPAuoKo#2e)yh`6{i0Aa_pz{DH{AXYXIVZjW
zO9JQ2G=N0T8ZTH#;t2Yo>=4HhF%xQza9pY8>L};C_d!kJ80b4!$2dt&=yp2iiFe^}
z2B(U)irJi9v0%yLyh}mRe9qsLXer=y7XlP=Bovq~;<Qp*F^Byobe`rcqZslT&ewEF
zwS+Tq9y-r*bmxGTampR%;9@yvPYUEKIPGI-JjZ!NG51PN+V{Y!INR=n^#bQ@N)=Rd
z0!m>1B4;bzC8^<jkpS;&IgeBFr;gJ}xs7_x`&1KfiIZeR+hvZOzBbap+3N~{E1U+(
zgEw+sUJiRroaJ-q{cGmD?1jb_&I)?}S~>6058KB1hDyBKIZ0G0*TLb_exZ|NjD^yx
zoYyG^-NkXEANCq2m-6S`oI(20u5(;z>vV&&iVl-EIk)2=*TX5Iis@cX4xOBCan9a@
z&fA>V6Dj_AhofzP#9hvs1MqEtW2NBpJ&wy5utCm}EJzG-?v6v^K4<F(_+cM#zPt$H
zLk{~_uncp89*0jOoON#ld&HTb3jR?}?mHNSF;2}hAdYjaeIQP7GJIfYlGC#rV2bk=
z#2rp9+<BW}(4G6%|94W{d>Ksa=K9krzK5IrB-%W<d2KM^$z@P{doNc!16}jt-lYmT
zZ*JvsSn}aAcfyh{_c|qp{J3jBhMYe)g=%>MxDf*o2;?qZ0P%fX`vb@Yaf4X^j$m#R
zl>mouFB`!V$}Oh1BaF+S{QG{c?ITEpb01N7AcFf(B$P&SZ?8dH6!$3)Sc>KfC}bbU
zT|fnI@!Zw)fz<=ts_Rge$Tj{Bki=d7IV>FFcBkOSKEhpj2rNgrojk~;IJkRnLiaK5
zSUsre+$ZyZWpL;0N1sk`H`9jsBv*F?!+naY9D>1Y?(g(f!5r@JQ;^T)mi+`1d0Z|X
z6Y{zHKY^A)?#WltR>VDz+gnb>+@~nubB0??A(j&E_T|u7%AFhqc9!dip&FSo?gRR{
zD!5P706WKRmB8Uju1_@VR&hU|&vRYiZldD9YVOap@w~`w*b1dJ+-+^}w~pIP7i#Lc
z1(cJ##NC7?%jq&VGYVJ(H;#h9SGbj5f!NIbk&0ScxD_-7w{qJZ7r@iT-As1dxlhm$
zrh_{k4v9|gKDtzYm8+VM9(Hk0(1hN{t)Bsbe(v`aaJ|Ldavy4Lb9vVxcZaK|gZTj0
zhca0AxOZLwHpsQo9ijW&5c>4cFjw*~+D5qZ>Fn`{t9+66pQGHzPNH#)%gaFHICm@&
zo=$L=OaPnYx~+o4Q{2c;Ky=|fMw@?E-u}4|aN~LX0&EYjl-4K@Ugc*Xdh$Z)DcQ?A
zJ_vCyUM}U<y?HW9V*2nps3y*rH;-cGe!O3k>HQ1h#k_)E1oLLS2-XlDlj`e3c}LqJ
z5yp$T45j;dBXkiUoYzVxnFwA1rBow%k#ug1<GquHaf;^|*8m*g-N}L7gS@9Ht(?H?
zqq9;X?-K2TlXy?k=Uor+hNJ+=JaZ@2f2Q(wP--QOS4gR(W4teB!C*S?rH^4ggZBqT
zcr$q#x@&iwCn$s93Eo&Il%C|BL|nruoA>JsfE?b+IRLplZYJ9Dcm?l3OFnN472y@|
zmVOUnA@8_5Sc-V_;-IXU$7zQ$$7$XZtKjz;-poa4EaA!SgId9Rn>NhncwG8QSS2ql
z39g;zU7|YZDqg${+Ai>>(acoMyF`@<7kTGqKxqwcdL@)y=EYM<K?5(h8pJESK?<)m
z@)D=xmu%w2bVFw|ZzC0~wK#Z7Dk0y>Ybt?>HeL)R%er_=sEFYjuZeQj-MpXZg2;8=
z`f`99ypQO~zsWmy1zz;<a(Mu~ye!I}_wl+Y(|?yYmk;6qZ@v-OJ>I-1SQ_N*rSRMk
z@5BSReV^y^HUu8<9Cx>X^&#&QI#LhwOnYH)l=mln_+^Zjk_?~5dHio7F~R$64YW=2
zzNcu}6mKu(+FbZLideex|E46U8$XybcJBP2xX`_eFW(8Un}3-K^t||=9RTLdA8v%4
z4}T4vFn#%R9sAJe$N%sa4Epm$H2DSa|MY^xfqZ5Y#$q2oVl51Y@wG?M?frZU&0gXB
z$V6z1;9sTk#7Mq3m2XG!ooL#K=D*8<cnn{(6((Z&@t>g+3H+_}=q2*!%K(!20eJMB
z4)K{x%0DFYYdRo*nBOJ`IKuz99%_#Ax6!nd!mn(FwhaDv3V4ypX9mIF<NT%@AfDhS
z(T&@a{LTlkbc$cP6arcNnS5x;=685Nbq@dg3>eJk7aoRq0Y9h@SRsEGodJsY|6HZ-
zFBS7wML_;E|G+M2JHyx0CA|`U(W?NZ{0|Dy-?Mzr6_6<7KSiIKDCf7+EsiRFxDLb%
z{Ka*!Tg~5Hh5@?BSMgz~hQGWLmTLJgybNdR_+}0))bm%Kg3d<%Vk*^a;(xW9_MgrC
zUJ7Ki@Hb1r+RFd&8)$3ek5KVoJ3nF-1UvW_k*as<=KoEx<m>z%3y3%PcVg*5glhmj
z{1?)pw3qKedyqc<4N5Qf^K-rj7~o%`%8`5gqx7f`@;P)DWQhMI<rW<G`A@N6_W^&4
zE4+Bfucb}IFh8~uYDW2<6#f~57Xah@9*S;E@b^$$Z<3$79)mE&-$KVn4}qH-On3@1
zk|DlVu$wXlUV<bOfVZIIGQ@oZPs_pLD~Qm;uAg906FB`Hg1|T^4G{QK)HzV#(Fbk&
z1Tug0H%Q=>3D<%JW{M1l2rkf~7$)EbL+O6OEF08>3tV=??FhlE28c%r4$>nZE%=Y7
z*%-kVs%eWAJfiSGykPJov>XuJqhUTM2>KM_2?EE9ba60Iu!U~0CJWflL-%1pNhcbQ
z2>zrU=TX6K4V0z`2JyK_r&PiCG7!@QJ{{0@Oi-(VT)N<uSJ8<~K{)Lgj|(nX08R)J
zmqG5Nz?UKcrvy*D1&}4E>_sPX1d9b=$rb$WP(eOV;NcA2`GR&ibQcJ&e1SnI6g*r9
zzl#KcW$>w3puU8*(*hlB<jx4xHVl4=z(}i7sUVArw9X1HUj--=Y^SqfxxiEkxe7rK
zMOx1Z&eA!zQm}}E^ydZbO<<`Kbfi*Q$pwMv9k^dDSWUZ~i-K>vpu0vehkmDefhT3F
zE(zMwA$VDk{4ClU1SjbUz9LxGiMB?;r?b$BX2FW%XloG&yV22B!Q5ehHo^D{kZTvb
zO9#IWL9iS;uL}Aol-wow@eQhfxhD9k4d``2r8l(Q5S(Q~@TTCCC^*w2c(Wb4dj+=-
zp{-9)>x*9W3*zb1h_?l;)6jND5L}1O+!dVN3-bd46HOcU1jB!TWk`@s8|C|gqUQh}
z2vq)Hc_`?97WRe(&iLsaP9uW3b1?{Gg7pg_I4+2GhTw$2Tm>*Gc$KcaP6^hzLf%D~
zv>KSJP~rw>+=PMuK)_wtOX<U1!WLTbb_-KO(6&c7RD?DU;lT3{@D#4dfZKb8Ur;#F
zOL+Y_o<MKm)3ne!e1wZX!_fE&A6|o?pKy3NeDfE&QL;He_;4TW1_}q(0PGV!DS?_G
zq1+6AgN2MMFcBi$@hwb*3O|p9(lFtT1t9Jh?hrytxUjnqsw0GwEPzPiixdos5(+6o
z6fL~<DL{-v_>?yUV}+^z-^L1UYcQno!Zc5qI3VnyPZu2&K1Zukg79N{RuhGDH^I>)
zVdEII9TFC=2j>yt4|8GSsPJDpv84!)ZHMkuq0I-X(}az5&^;#fngz~u;qTv|FB!r$
zlp@R&Ix1*)cU-uJ%Ck-g?`#I^N#Ua#Xgnp1pd@*g@E5A(%NCZ?mM=&6lLEt*D|Bv!
zwme}61;6rzXRbm^f$-usv=s^s6u2xBeosfHV&P@Fr*&HBvkKmy5q41pM~SfEAvjBg
z!ww2PoE6Rq09q#Wr$Uf&A^$7zR0to;hZpCB^T(j3QrJvW>3N}*s(7k|Tb6_6f>6I0
z=4*tZs{m?++uwrsbwX4w;>8jA&jz?8Jhu^?mxVq#01ZO-IB2;doS@&XQTW#X@BcLk
zhbG`fvye9jzgmmXXEz#Kg`x8x(I$+dIlo=_R|7ok5We*?I@2j!7Xg8*!kRB&qD%O;
z76R9VrztnsEqp+^qw7LfGl(~Y_0zz4Q<y_vQ0NnCP5|o{22=UWE#ZR2wEo=|e)tEJ
z-Vs(~J#rclHd2k*J>evUOa_Iebg&;1w$Qf(?h8G;p!<O^{6nZ27VheSi4oz(F^E4B
z@~MJ<R9H$8h%w=6CEOktCcOxjNnsV`tfquNZh}r1(ONG6H_`eZ>HTvT-CqZEm#F_^
z2<{fy{K2|MG=~C-o}z&~fW4xEOgQW%`iP<`-l76pRDDFBeFESs`sxV8{Y48X^&B8_
zT?T`JqOqqy+$R##&LBuMjh?Px(F%%Tg^JV^HVPBHJBcB2>=!k#(U~Zb^<!9y78yT-
zM2zT2EE;1)+bDz=C(5J?7Y9Ud(y{lTXh{onCy2t%LR+Hf`xf**NfcfM;vrElRf8sr
znkcMyL^O5`#G@kB31~?XU7}CZq>2*mp%ZDMZzCX{?htv-gnWj`>plcCMUm9e<Dz^j
z)jlD*z(b!-iZ;YU@RVria|q^$!s!s5E7JW0xAR2V6rs%*omm380+EPP6h)%%K1W}Q
zMN1a|oECNc4&oV+ZZQm&h_+3k_obp~IcO^rIl|~wEf@LIYg{4n&IEQ&)JdhSm7@3N
z!Qgq(Jvrnrh#t^eQ7xJ&19nj~N|R8n=wq7o>O||Q`mSEo(SmMY5{>){@ynwBsPgiP
z=)GeAjiQGg;A|4{I{}(SX>|T;5p8nN;J1o)P?=M^Xxn+{?htjT(AWtHczRW|f@b0_
z(Zx;Rye8t0!P0e6;%o@q5Y@g4Z8t@E6qoB4J@z@|ZizUzA$MD(SHO!qBJp$x+!eJ{
zU_|eUq&ZMFC@P%`Y)JI}Zw|owBIn<s=7Ffh0PLYCfVOVKqF}nU@<?QT4ILd7Rjh<-
zW1@gp0menk=~Bgn=pVY8F(q0=*Oy$xBMtD-RlMdyc;O~~=|y1f;yYgG{VwsNAK>9`
z@fJ!edx|rtR%EaEiG7rR@Devsc)?pdZ4H2rSV&n&UvXSNc>Kg$z69_W+h?H{0pcx`
z#t#%fTLahji5Jtv7$jb>8z5L5Spv=w@pJ#cQmFWJDO?K^AEavC{o=BA*bNu|{4$6U
z;*}TB-AM7&OLYE=60a!*8Z92upieR4lKC(ZD?U&8hd6P=PPD~~AK1}$K<rBE?m=;3
z1wev0x)Qn*#bVllC5a#AgY%I1@N+PcEI!1Az+rLkGB|ofJhT$t9~HZw0cVPMd@od|
zihrODx+6^-LVJm0;#W%0i*#{m7X&lJUw;XSOmU_aN{@?sKL+awvG`|b%MvRBA&@N&
z`3{^p;{WK~&KG|{Nt6Qd^G2926u)`{*lBU%8H~jl@i$bYRU+Oq2)E0`AJCIqF8-zy
zIx8IFC*mP-Uc6`;ELDk<>B~G9#5-xjTO-c+09dVfOaS>h@rI)qnako&=;+fRo==O+
z74gRP5N{U0=mM4&aTOI(wTi9pgQY{9nFjGr@sIC9*;R1@1=PC4Wt8T*CSF0eKDxz@
zG}`1{7n`V7<%W1_F}ikBeCssS^oVn5Bi1WEkO`K4v67M@x5NQ&1G_DDr`X#aaRvw4
z?utdUWZV<ap|6<@isNWz8xo&=3_9<NXVQt_f!I!Wf**=Qg|Is;PW}$cM#N(d%HKZ{
zzeSOvQE`C|2FJwL&q3+9xPhMa3GvSXP&z68@d7xf#0oXqTqMaRm~fT6{~oltNs=yu
zWw)f4K9ROZ@(!JaJtY0t06ZmbccFT(BuW9yOX8^mr?=$6F>v}w+Dr~;^OGE;U7EjS
zh_+q<5>E~+1xntYj<$W0jr1A^Nxr8#vS3MS1we?TgI@UklBcerEnKpib~F)^x9TAf
zE!jN^mKez=RC*jMnNC%TagyXfw8cw)rKjYeWO5kh6C_Ek^!_DEOn;#<N%Gn!Xgnl&
zmlpbDiF*XF!;+_0qlZT%ODM8@RI-o`?<o>Liq4;u9HLqJltlG6+Oj0KnIL9M{^~`4
zb0kw=LrbnCn@X1RBt>)JVZP)=I!P2rmd^lID4C6e4D#=icbG6yEO`(FHK!$uD2#JP
z^4J*sE|H{3;YF#W{b?vYE19zw=F229CRoZPQrfpxNJgkU@tmaWDx9g5v{8ohyrl9L
zOjJqc-GjgdiQ{_^t0k`-gohU;2{GWTk@Qu7=%|$xP<3UUr1x2<xh(OZn}!V%ek44-
zBKhVvh|Q8;XfkP$c<zEktE9OA#5PGf<?-4jSyZ3YA=&U4EOkjPQ_0pf$;Ri<?QY4b
zn*i4(CkDWILlPef@tcxZ8jBuD2dzWB4oT1%=<bu;q9aJZB#>UGTN3vmn7=Lg`aKN7
z9f^k0mv<$h&5#(7$S7iRPx2w1PzNQGq;yDfb0@I-5>pyj9!Q+(;LJlwV=~%?C2J`C
zI3j7C1J@o&^pt@fm1On;j7c0XQE9=r<T&LICnQe}W4I?JOWr^arzDT448}#eN(>fP
zX-qZzc9SO4JLWD;rXkrSO`-~&-O_{fs_l_FpNCx!sq$M8J*8aQNbQx5PzAA<^uJbE
z@RlC+1<^-(obC$vN(&sczwwhs(AgtUT12HT`=noJz!M}59tKaa^m97qhe!)4j~*&b
zmO^)!^s8Ht+b_+fX(wE&F#tqJduSnulrD*YzfscS=fN2*m3{=d80q#nn2(ieDZ>~i
z-A*+~@zU~NDXDQldh#T|LFr>>z?vZ45e_wp(v6ECe@Obs9X=&XFVmcVSUT+-SdK_z
z=|0X;sgoLmm?~|VLR*@2QxOD?N$cqBo+)iv3eMxw7ikJUA>Bkj=t*gj71$|hvlQLU
zl6nQu`<E^Kl#VGm(j`hL&6V1VA($sk=0hT1x`hSS0_oT)V1?3-S>P;^?xqNQv2;^C
z%%7HyMSyrldY<ZLN~A^fZk9@CQzrPV^yfSf%cNpj=gXxjwCq<%8z?|^PTGWWA$<Q+
zTCM`?dFjG~_<gISQ5oR5AU#+D6V=k}0NA}K{eTWxHPSG;W>zbm*9L()X*BJ(>!tY=
zxxXZRw-IfZrKSGB8l?{?;?gAD`TwA|^q2%aYmq*m4`QpdJ{6!%`WwaE9PQH4RT%CL
z>G?N6?Uc4=!_rl$KV38Hl6KR+s9QSiF$~FdX$~d8Z%8K+&~`_<stDk&G>%eN15!T<
zuH2Ir(;dt~Y2{paI3(SZ2$uWO_im!U52TAJn)y)r*k=I4QV~s)j~vp!m1rE5e()RY
zj!C~d1?spo;b#yhq%+TeI4RZAjm{~l;4Fx)vPE?Cag%M12B*7hIo$`}BYW`%EP2R|
zyb0Z&vW`|@du7v}2IeLE_ZI+f*_X|5%}4g@Vqm_qMf9-v$s9sD6Z^~7QG7g5Hcpkm
z`(&lj;0cmFtVS<_WuO0taSoC79fhS(*}79u6DB+T7EFZ8=212<LbjXgW+G*;w?HmR
z_MsAPN6S<c*ou|aQiwE8HY*q62V}cwBX&^MLmROKS(}6EnGeaH{{-^MvO6SySjM7Y
zMW##|153wcO9CKxLU!^gcyUr@rj_!PY>JleEZMI#vF6HNqr^d;>^+Kz<;z4*L9RgN
z+ywK5G7rit70K>USg=@D`8DjFmMx>=p))e?t5pA4BCGom5~Z@nE3kW3#-jR)a+!+0
zyiy@sGYhQeWPh9kRw>)C0$!Y#-HrlhwM=yj*hSe!S`BMtrH6sl$^t%vvO1X)6*Se$
z&T@cVlAWVd<Yn3BFCf<-yF_uhE3(Fa==&3mvNIIOXp-%W18A0wQ{J*g#$5vWR#|l;
zJZzKAEQ4UXZ0Fkm9kS_kSm~4<iA38~*+x2hbjkXY(BEsa<<7vmWt%%8eqAOG#gN>P
zh0_7|rtG^pP~9Wj@(NgbWpmKxaO#tN_7r^UmpN$OxFx$=0_?Wz3~kBp$PRXZcvtpb
zD!_nj3kCV_$u4F=&7kZdh3AH3FWrQt`!eVMAn-u;c@J0~$~ueDHY`)p#f1^skAA=&
z$=q*&WmFc&hO#l)O(}i~$GGgzx$t{J_QWm-PRf>2Vt7h+l=3Yu^1>{%xye^7z%Q~}
zK64}5_Q<c%&cZ|fq!lclavR0`_R3%Q8``|&DfG!OZ@Hre0zUFN=i!>KJfsQc{p5e|
zgED{lF8U-~fPAqDZGjH?H~&AW%KsGu4U!*v9!ewS3+Z=?lG|zkqUDP>qAf<=c?|Ng
z@>D+%<K)E~FbMJTeEKO5$fe`x=s|hnC145i*IoxpqWl%w?Ig)ZDOi3;&ZN9yvOJ&4
zD-O#?euBS8<c=abvK^IwPw~VQ`I|ItrOKE80~gce&hvpClly0bHC_JmB+O^XcOQhM
zO!=Q4Xge<7vKC!CAup%p_oSRhljbRT=S_%b$yeH8Fk2qH99WK=Pl3-|`R5d^&Xa#d
z^+oyehYs3K7Rc97&a6=W_Xu<s$-kF_wOF1&fw9wa?hcqZBWF|kq(nYM=YvvtH5)8v
z<$najr!u*ICbU(^e|QAl=j5UEcvZ^n%V77sykrt>Rq~Ft5V#<J^=k-J%Y&bTvWxN}
zwFA@|`2<Z(wetJ4DXx=$N;$rI`4dk<{*t_qq7zr-xs<VQlvhv$ut{Dq8z!3N!3wms
z$iEE*Xq7K(hrey|#JAu@yWBwmkPi7;sub;%H&Z6+syy{Rh+Xno6du1OkM*YfU$=ZI
z&0g2#6BK{BArGW8&rP}i-%!&d-+B_DSFW4~zx(9bbUx^pt3Cwrmi+V00Jr5co`b+0
z`O6<b{H}Zf#exUq=V_~XPyRC16%NW@qdeM>e9JI8abLcZ_TmrZo-1kp`A|MgeHxZ`
zehr=x`9<2gJ(7!;z~HD{u@wf#<p2B%OXKow;~-AR|DYtyq`Z;pf~Vvk)}qZt5lKN{
zcSTnU1a>Jtj|Iza#qU(O;;HzS>V5VqK8-}Ty%bnW@m44f>;Q21DY7Za?XP&a2|NJ`
z1(i1jDx9BzGy4>NbdC#Byt@flu;L>snGR807r{iR!cN=4FvZf9!1gO1eG1NS#j|$-
zA{4hXp(RqWj3)aiMLrc}M=O}LqmNNohhZ;Pv6MoFaSp}YDWLI+ITYAFptwpi+d;*b
zwD2V;lBY0Ui3$^CIFl5kh3L~E#WsqZBrC4ifE`sV_y}I4C<-XBovH|?Sub7j2i+OX
zP;94NVWwgsh5n8!W)=WDp?IDW_9qoPo(A!h!m;~#c$%enb0MhNiidun<|xAW(3Y#H
zrMN<#!mAug^A-A)zzP)E+W-m`J#?lmQe2^PSg~Raef#IMV!jM^&nRZmM^;J{d9)^%
zDne+XKCAe)7;R;W%O^lASM<z;GZl(D$E)b!IYrzT&{nA^rfK@TVyO#2mBK`0aY1o`
zs`aZC%?Yqus~DdPZFP!1E{OFCeHFbU3jb*kzpU_DfVKw3UwW8mQZR$iiDrd@^1>~O
ztW03N3b#G*qEE5<2bk|y{5eYd&s&P)w4B{mG-P5B?kE=04(zUC6%{lNC?@IDeNWM{
z4JHN^Ybg#gq*zpiw)=_*isU^|`1r!aLq&BAIENK;>f!x}Vg}8xj}(=3RvJ}AeG1iM
zifX!2Jg!(q3&Dh9MIzN-yC?&9LXE3(&mq`#Q|5(1&|Ud#5Qw{!PwoNOtvr4o5_^=-
zD!}5QJVk{~o=P!=+4d^mUIENY`QBN$=B-qAK)^@Y)CEpo<>!<b@>9P3H-Nt~h+<Iz
z%6T+<1S*G76oc=7Dqo_fB}f^^gPLIFZOWC0C{JAk7OE_wHz!Paj;@64S9VYlL%6by
zs`nz4dD~$kQaPQ6{zfT9-oT=jSBikeD5Jd~7pv^1X);c^f(f1R$~)UZJfKw4^K?*|
z_#H4ug7U^T3|peo_!$N<N$Ekk#Y4)3Ui>i0%E##>b6EM$HP}6(?0F2jk1Fp@gM5lI
zl=kVVN(V)1(v&kcLd!Ab8&sN;u1ukGV}=rO2)qEwgl7PbD|^$xaza_R4vwBwhDL+)
zltZ~<1GHr+iz&^NtsGemOF7D{Lg>y_ZVLm*Qwn#%ZoaZ(CDars7m|FTa?A??MaoZO
zAW*FQU>}I5m31@+o>4BO<WGt6g*Jdv<wgq1oK@ZnMhDB3h9{u2T)E5-#0sTjJREAy
zDc@^`?n>oxD#19f+(4z1Rm#UHU35WNK+*0R<r|bEs8xDVE~ieplj=w7l~dCoa7lTB
zk{Xwl*45}sgYq#H7CK!~uJuHJ8<kH}#b=Z9;D4~ttn?3r>K5gVBOtaaCmpm|Yg2N6
z#W=Ss|D@gFRpstMG<GRl{=Z5nxpSedTlsV!+O8{|=$L*(Df$ptuk!Et=uDsT{O1tw
zSGw(i7k89uI$PdVUZhCRfbtnCHXc$=qwL9jWy}I#50oF!)csI7uiF8Khm|QS&^V&}
zdOom6%2)n{?os7SH{sfta#ae{j4NZPCUrvj!fd!Usni{Sz?AYXRcE=V)_(=Nt||c?
zEZkJ_6i;wh?V=l%yHsm8;fL{1St$VNsalZ%xxK1cC($Jz)u#hg|LLnrr0l1kYUEqU
z`>T#np+SJE<1i!wRePIZaG&a<0$2)Cap|-XthzW4&V;CHxadWwDweivVXAEuir%k!
zelgm@Rc~H~&Ir}5W?+%3p*P@Dl<MPqP#vw>LLV}TQ`P@Q-=BzAJ#B{k0ab_;x)W6`
z^yDY0%uWD@R3%TKEm<|&8Lk~x`9BWqh$_DZ*iqHa$03lS%J>PEQdRyg=u?_%$#t|H
zQ$247maba*BUmz2kJBC^Q}u{K{>N1_Xf8UTTDAZd94A%RUVu}lRErM5#T?a^b7;&}
z@xMWT^HkGmPklx;`W3oXq8gznL8<EL1MuRkDsMW7WvV|Zy;ZJiuZ3KNDpdr7=TwR{
zkgHUg-+?pdRliUMt4fvKhqeo<Hg|w()fxf7MTctHKd@AzO8EfhYgMz;p}S6177b9Z
znxcxc29=!Vn=7gfbgFAqX|h3VQq8B-O0()^dURS;*;L2Xs$x6=pW0OA6q;>UF@0hF
zsw(;-K$q$??UJskPX7(gZk6XU_<LRDc!!c~H&iAnO}MH0i$<tN)pihAFRnX*^_J?E
z0fM(xj$hExJE~MlQQTFrD26?t`jJX|?x`l2AP%bJGPpLR3aW&``>J8OK0mAqq@c=(
z>e)2_k5nBrm5r)ak3iX&D%e49`nYOqHsmK%(YXMVs!MdcbxOsjY@(Zb?F9(BtKXqH
zf0z2x9t?tqdVw5mp6X-d;a+t>DGd6kTOYttU-e#k)%?_xY+!+E-oL>1sfVwjOF`-;
zO2vk%_sl?Bm^%L>ic9QQGbr>Ism`ZUPLz5rEwRz+s$DRcpdR2tB2j&Vvg%3d(F|aR
z)ND%WB&$c$;O}9zv>)1zs8_4t(^2(Ks?twUKgb0!Rehcgx@qdUYhnJFI`k#5q^qBK
z4=fq#-u?9bvrP4ln=pS|z3?>5pHPQT@cE?rhmRn5O8qKDY_in$cVIAET}StKbJU^$
zwB@RUI1tEFXNaIQUu~uDOBSftz6yat^<fYATcoZfP^@-;69T8zuF>$fL|qyWtW>QZ
zr2OAm^>Qct24!l_EI3uJzO)P4D%5<+51&(iF$DQa_1~07IIsTAfnHRp_fX95g4*N`
zgVpNhMR4t+y6P1WYt&OTqt&Y8>64pvYON9i_38)d&~i!r#eXn=Mg8|h5F6D!;ox*M
zsRa%=+^QB(B)m=iJca4n)h`n3Rdo;T3cJ(?sl4%;dVM*tZZ&f)u<PntZ>YJUZlQR5
zuUhpUK%Y91j_LjCa*80_QP)z)|E{|DH^>dBSIf|LPyIRVo(I*hya@3jhk7U+)Q9RW
ziq;LQy<P$sQ4gj8jHzR38#}Jfr4-bJ`s_GdbJ4s@eR9?O`5W5YG^a}7=x)vI=^*aW
zRDTNH9-5z8fq80N^Py$0=CuT{cxguc0RlB&51?(I<`$*VgEWrm6vYkJj8U~>h~`^*
ztV1<>Xx|&A8D0$c_iKbyz8bFSrnFjw<{yd#L~0Jr#pp$8evAhet#R>$GclUJkKkdf
z=J7>ni_=8@3TNUqygdL1G<i8teNgi}{q_l(SLno*sNp!MgepnHT?-S3G;dx;W3pxr
zMHdfiT$iHlh$d(+yf~`)gMuR|nztT<qp6yIoM0(UGmBoQV;aL8=uX%8FT+q~Xhx|f
zJX7<f5^cvdxk12AXfo*OJgISd2F{$)Y^?*9rD5e!{3Tlx;ty>(n%VL2B3I)V3G;cH
z^ehnbH7-?<FVN^IP+O>Z@Dx~zG|Q;;u~?H?0yU>K!9Rj{M)MPOtwd8~0#>Tot^syd
z(@V2unPz+!uyW0Rv<Iosyx$6zbDEb=)A_Gb)3^!L^O~Q(#4l5&@eY9B7c}x7@KkFW
zC~$gFlSqYFH5y$YuzF1?<y$Uk9;QI|WsQ>F^hS-;2gD}LCsabwtO>gcx7#$EmP1Rs
zhW8KTIyC#lAa-elPeR!>&7_9@f4W=aS^<MMHQn@+^k}*m@S<0f{solwY3};LwSLV4
znwM{B=Fz)-TQj-{EO#_zbd0>KnWSv|fMyRp3HLPb&BsqMsQG9f<nC)exdHPJG&M9|
zJk%`T3cJIaX<tBmMDrn?s2z_q_m@CoRHLO_!I;Lp0FC3CxGf+~Xw+0tJgJ%TgQY3W
z5(<8~X#I|%%~kuv9T45LU(&MRu5HN&*rjcvgTZcXpAXvhXk*`jG7qhpjzykYb05U_
zYD+nA#!H*99jd(@+K-Ds_0hVrVBS|dYZ`!`b}Ri?iodop0)heBSwDa^Q2T8hi2Jmm
ztAPb+i<g2kSbOVb5JR+6O~696ew4fk)4t{pY`-=&5zd5bIWxf$q5W?$JdD)tI0f@j
zT3#&7Mr$4I)$lY%dz&s9#A@f2f;CQ?L22!H?L#-T9nebYvl|DsbqfI!w63+#ov6J@
z5uzk*2p!H2Y5mBxWUV{RQ-`&yufoz1ZTBd!qgr>GFH*FlVt`cb>Jq3<(|-CHv>eke
zc8o$kU3;k;<}<WE$sm!bWp0JG<Jtog;5nh)Ows+5+Oxp`r?jgn5Rs)#yM#f=))p4Q
zQjT`c2I$V!&Y+UzJnfGOAm(d3UItd6t(ihwq4tmW;C+#nNqgF2t<yNXKdoKj<ABmL
z+IMLiTcTY~A0R8$zCe@bS?%9baIH+cm|`sD+DjB!uF$F|oOw=bcpU<j+73D=pVxYZ
z!qF=2DtZDhXrpK~tJZq&gX)Xg>ILXooz@WwV!d|dN?@0?WfbSVtX<Si^)C(Dk7%27
zMf>7%m~YfN{($Z#Z79VWo3+1ujkXqTpBL=5YIRg))ut6u(L}rU_>&Om&~{VFbEj6b
z4RTkt&Y!?;mv-qhFmX-0nFaA~?Swztu4{*A`MseXrfRaA+7TYbKYO%ge?p>HTSc4c
zK5gl@Fww7l^g9G^X^Z1w>9)3*ssQe2TfPL#U2O=(nFqAnDGzW@oB0!ngW4^0k8VhN
zhZfxXT3?#(9%vWS-twU~lY(`_+Ko@4ZA9xr2Z~49mUf6cMzvxaSjV(K(++!F+e%sH
z3GI*`LprIA+lsa+Z6_5CyXZF1wK`Ybv~SS0UAk{+@3LFh%>{9fuKy~4hi-~)&Uxy#
zdP3P=-S7^`dFkvc;jg#u7QI_OI(-O;zPi8ZW%hIE!asyIe_c)or~$fnD6|`>W4{RE
zKHUK2O@ef{C_)shGgvUrAvzJ&*@o)olA~d|dJ6LI*R5ZUK85QxQ<N`4ry2zosXLwl
z5T)~e2=Qp$Q{O`_Mz_}lfmmHt0xZPo9Dh>eKVHY83a$e>5y>Caz4tzROVIHtvzn+|
zK;NWE(v|h%H$0?Uav5rpb?>YN@vv^)MQ|R`{k|T~9M$c#qb)^ulODEIot$RUG@Xjh
zJjZmKD87}h8-5DT9M>`ElFbR-5{C>1PwJMo0zIXRBEPeAnQm|~TX!o7YI1a{Sx}m*
z`}Qzc@^mZk(FCV_-G#4!73ijqKwF_sb_64HT9-%f*cshN_W(+CedF+{Ot-fK7Rq&p
z(!o-pE9{2&d7VF%b5-dER?>#*f^OsyK#lHc1mB!$bs{SJsnfO4H@%y6d<lpxy7dPj
z(W<+Y3T<t=z&Z%D>jvJ0za6?Abla>`XWj}&uj+nY53EbKgm#73bnbKp@7BFS)7^C)
zo1(urbbfMxo4Ud*%0KkzPSUl>Uft_A0Qz+O1!(NorBe0KEnO^?3E$S~1nAQp-8+3y
zdRO<)EtntBg;HYZo^HznxHhP>lz}*;lfDKm_jTWvf%Adx^>z>+>e6M<GOW8<41qD7
zJ3WZwx)rEcaX3xrHuB)`r0&~vP^WZ_#~|UN&;1ihUG?Tdw7Ka!0^!ph{ZF(UdFaPq
zhi*^(FZ5RJ)w^5(@Y26b7iqlprfD$mqhCcQK41L@UxDba@1^G{Kp%7)#6W!`CGPg=
z-%NlON09!F-yk2X-;jmI5WOP|mO}OKmx3ouzkn|C?AK?m2Z+#*Qn6H|epV7ZjM7J?
zL20x;pDImb^sFWfP@LX%HpJugVU)){ppT~DVuHRl0X<99TPbasq@SXAQL=s~9Rm+L
z^aJh~nj`u{RI+kZf8PsgQuHTo0z0O!eFO68`c{g<X6RF~Uw6vX|Dy!)xc)6ESWf6C
z-vjZae&i^Wp3-Zsfip{QyaOy(uWLdN^YmjK;LO+0oDI$bz36j*LjB6aAQtHzTj<nX
ztiQezy*RB8rgQ5VeI70xJC*3GHleLl&*_9uXZ7<adR3->h1UCW{r30KR-xxn1;{zQ
zawED{sc)iAoYzmRg0gD8%NV@4sE;@dP@}(3bxpPULn?^Z=@(LPq+Va)*oTq5q;EI@
z>Sg_BD#$nJ^H;&eEBXN1BsS_Zz5#2KUUdp>EqXt?oztpcmkkfw^u=a?cKzcsp`}BA
z^9Wcv^_S^ozN-Is2im&ygAMThn*JYGc-XBE<G|2$y{;F;8~Rh34)EO6uS|eokN)x3
z0ebbJ77+XNCW=G$>rc^rk6ZfPQE0oZAD9X3jy}o@KHb&-8v!t=f3p@~NdKY`0{8W?
zzA!(m|BeprBl>x@=)@!a=~n?p^-`)~AJgx81uWzG93FjtcS;}n7j(NA?tBOyS3_PR
zFn0sz8-QJgv{;PZZi6p5v&V3co+}SS>My`N4X;p^c(37!PMG&Hn5+=+HY}ud$j2~D
zn?qki-gM{;FnmqH$w0%CRM51~px+7*Waz&~`S)N$DuwVu3@uuy2{pV*5wS4C4>w_H
zzu_mkDj06qPLoN5;RTwdBMo*JutXVNuE$tJ8#Z~sV2q)DJH%rRo<rz%oMDF(1mX={
zR1|Z-aAgO6w1bAb9|0UPtUCwsWW)S6$T<!hKA|M)5yNH*o*gwfiXoq3c$-2zsfNg6
z5Yr5+S3&TY;Z?dCoNhRp43-STiUP=G8n$*o+i}BeI<}rLD5xaiq+#Xb0H+K)4}&Gk
zaGOrQ*@pC|Af98;(dRUC4MjU)A<toWindqzhL!Z8fC9sM+F2AD-UxzVkzwvL0L6xp
zG#ET>_>>Ba&KQ<Z9<RiprISpl;kq1hXALE%VWP~iiz-&i4ciYuONAl(9T+@kD4&jw
zRvLsg0Ot))vA|hn5VeByg2B<71rybVE;^)LG%Ti6UyWfVE$y|2G@4WD3>zq?Qg09!
z0$eiq(R_2+5IzsiG#D0~K}W9`oO6LS8WJfw-(>jeLtxE@TQlHji(w%Z^0yisG|#jd
zx?clJyWxH_h#iK19sj{Zr=g0Xd{+&JZ^7>_!-o$*yk=m~EO5gRP9+#O4b1sy>oKIQ
z1F_d|jJ}%FXV~%z+WHL_i=gzD!E-tKd)qK$J=*RVrq`jPcMVs*grxz)1s%F{&k#oU
z*#-@pM<6g{Fuz6}y>AGa4~K^hf6oW&h#{{FjgJgf6p|V>aLD|aq52ZEjT?5*+&y6!
zrEB4n2CwDdoHA5VCBKXDuN7c%HHNRj0J#}!Q^DeHoaqK^m+=7oTZe~nYz2s(Mr$|(
z_8R}X_5b=$Bb$yl-o~%_;PEjUw!;fw<42D{x1aGPst@!xj??!C1B{(4_!MaLq(bq1
z#;JaIA7uQDJ~<X_WY>Zv#5kAs`Ju+y6depR&R2qSzwyj@w1pd&&@2#P<Wo6Gq%nKW
zG`xRN#!qOI7;UVhJy(oTH5c0AjVn{&%mJhC+YmfxOnwa75{zACU`aHdx{l#WGT!oq
zhlh;c((XIi_{?umdf2$(1+W}34y8l<s4<WOVv2D_9CW4{eJC4|X8h=5bT{27wgGcw
z7;D3UW*X~hcX!<QmK?fI7)t{oand-K&IhNA4Rrun#@iMs%{G2F1`|0(eIb0xH9kR!
zp#tOUy>PV9_;MwPMMe>g`Wa&t2cX3GG=;KCjhQm^^Q>`R7c7(+(`mO~?l8{GKx2h*
za|pmW<9aSesM07s3rpvXMU=^^GB#4I<AQPF3(!_=?4XDIqA`nN1~tZi4?>{U7~=td
z>x{-9VZPq@@p|aKWDI@^ZI_L5IwCe0bK;=vig8^hv@{w8&!er$=vezIMyT2N(lVH6
zF~)p_&a@gM=0kUz@h?ipwHxn$4Tn37V>Di!#_%|_T{S*Kmq@ydKhW;^nz4tL_HN^|
zE&$h!={sTmrt#J7kn1t}QRt!9=uL}DAIw9b-}t8jEVqnxjy_Ot8;8q5y<=Sb9Gtmp
zyiLLD0b}kw2;MV(PghC?jS?#48Zw@uii-Qj1_BR^0Xlf`(D?OsbY|G7OM%i6V?TYR
z<dG5o6pHu9_#u@?jTxKoLg%=VsQ_`pc!zQ+lg7`^JD_{Y_&Nigx|n|V2G!LRvm2~#
zraknFxSN`372ah^qFw)PlX3t<vd8pP4ca_RYqkM+nrhOabgyYa6fiGS&a+_gHq~4Q
z@G%Y2Cn|hRkrc=9GrgV-7JpMXJx>9q`giF5QJ~4|5*qiJ7E!!6$P`HlxL}j-0VoYI
z-SS39LrsF6AcmQ?r9p7NX>}cRhnuQ`(EA9}hFoBgra!~cmnc(V2jrqnf1$X{DaMrh
z735+~U+e~FoXL}>t9aA+fB2aWm<;|-c>fNXZtnn3f~mv`kZ7tN21qhJ(*@Q;rXw_Y
zCYyf$7D^ABR?-V_#5B?YpN^XTr~xs>bevYoR8!jLP?~01q6Ii+`kO9Br<-cs(UxKI
z3&j{_nx3Yt>v0oj7^+X0Hg%x8jx3Xq7V~UV|1fmtn0|CaW3I`KLQ8ojQ#T~?O@0)d
zEHJI4!7nt0d;nsRDV@$W#in;dAaL50xf9NuF-?64ti+Vk3YJpS7qpo@Yg!fu&N5R^
z1jNftzrP996{bpeVCNhrE9D9*O|$5m3+GLH--c6FrmuqlE|?1QVYk|};1_7SX!4i@
zvBtFf1%O&p)=vO+rphxgSa0fgfr(3|SLt&4Ws_11VuNXnio33uZj`}bqiJn2+L}zy
z(|q1+%89}lwwN5eAy8XQ4+DU<nRpaAX*Zp}0?=V97s16&Qx~NZu9`Oe3`e_63cAX2
z&2;uhDD5`AX9srO<Z=isH%u{fFt}+F?nYaWN%jAw%5;iqTl!3?X<+F$75xb<w@f*i
zz;2rsIs#znj>-9Z4E|ly@8{s~fa%XkxOmT`tcCeO)2i9{eTGcKw2i%Q3h#lo2PQpT
zs(5JX?}D0P(;yQ9BPQ1cV0mQvp7LR%rc0f0X3X^8H3*EGIw@>BVfthhEKHhC)8C6v
zndV-k^Ph{EeE?p#njJqvo13}mFEqNF|Di3xE^`EJV?E6KGr;0$-tq>(Ub99Gf4$5@
z?(o9ftojum`j{8K0HVM7A1byAFn>q0WuUp7YL|k|d%lBDA?C#^pfl9`=0y<0%-^Uf
z{<+`0<0Poz<~QkLS%mrN7tonV^9A~cj41Q(^8ljFrS~8aW9Iz{mRPeyhRz%?|3?Y`
zgXWuVU`a49rc%#Db9F4RB(sf5S`V3TQ0VT6c?+GRj+)mkhn5uc;3sH1W}eYa`_FW9
z1)U)>%p*qVK4I>?0r`{WldnVDDf6Qw2xgh*(|$YK{2#@8bIiN$fF;+QLkWO9^GsUm
z^3DG(LR*3PJG%c@Xda`FbrqQtDCu;@d{_><CFWVB7`#$*&+8B<H^=@0;HWUm8vxIl
zM=AJq-rP+m>niheuCRN-+}H~FYV$R^`+3p)8HImp%+rG*P-{-5s`WZ^ZV9k@^Ey37
z?UFf;4dP|<4-~$+V&3o#e!E8VeA)*#nR97vYc^*+39QBZ0o9STI?N9TA=qY)dIxB`
z*>4jhI?TFv(Zf#j;}iqCX5R8O%y*k(D=?PV%{yY@;SKW-^aS2Ck5gqrkNK()EPdv3
z+FA6QZ=^!}mf7`lbm_MFN$fM6?wA{uAl@~<NxOyt^JWhW$vv~fg+ir+<{9){4Vk;^
z;mm#W+&Ewl%p1($d1wx$NYSvld;zc#^O_UTHfo+ur{*!UjZPHf<_0R}nK1KwK%6u)
zXT!BA^QS*Tz{OIv7(TgLylo)5S!VnVad%4sjo~hf+CjB^yDj%<Prb(yNsF<E#gh&X
zo|ZAn$a-5g()8hDnOF&*d@X<fKTc(leFZGgqTCO=`z&>dkPEU{snRCc@_YiY5X<uh
zVEZjmlh6`w`I%<K2um?VE+Q>H18^<MGV2iSZ=x-KEymEqSp5HiM6BgS%8A5Tb{vA;
zc+136^yz@*ga4;bEL%Q;YYCQyaezciA)OnOEGwL#?T{r7^^{J@mi3Y7=wZvM57EOE
z%Ut})ms6@`-C>wdvzW~Q$1E$v(3x)0JxSl+&9Efi0D8i*h{8@MEiQRbbIP)XDn@fG
z9kdMQT5{<N8+n%0c`%r7>7&qnfn_%f{uWw_XvrzEl)eq|VvCT{E~hR0Bk<ykWot0n
zN-Ro0V5OE-&qDmH<v&WUm09vI**cucE!^ucSYZ*)fr)dL++fI8T1=EZJ#TrILbFwt
z2iu_gf~7(ZZPk{Ao1yKZ<@7RWtFf%T2F_YbC7p-rEFQE^ueW?nN7@F<zqA*>ViEVF
zFO8N0ipw=wvMeArTXuPZ)6rsS^+69?EzhliM4LrT@uqgm9GVO|EN|0rcUtNzLA+`S
zH-Xq?`M3ds*DSF&;ZwKe$Zlx6Zut_EiPH_s)z83r(^7d6SdXQq99XY~dmf$Wv-r+N
zxBD#{`Y~#^EasUIzwNNBrqI$I%V)>Ide`Fh1e_VL)T?1)(DH*5+J-DaRGf0(vVJqv
zJg^i}dDKHoD;-paEi0+gX2cTyAp{;-(&-%=v&5JH#w}B{51g=sJqCeE%h_cxKV>=U
z1Vb*?Lmz|aYIXFz20?dgAWbH_td)6a+->b}g%^9Q8NL7>Rvl%1ysQC%z`U(9;kc8J
zRYF@nU#klh&HGs=*%$<W>o50VFu-cLiMBwi>^rpWv)-a8d63ob4-kW`?4_^}VpSZ4
z&QR+?hXqQ*tZz`Y{(h^4Y7fJ$YPvcXVg0@q-Hx=brJzofb^19t8f_i;0KZ6#b?i7m
zto5fLh{st!bHJx~tBnVx2dt-FhxkEjGDTbxtX>pPPqa=u2M?31kDq{+L)O<RWS?wZ
zH|hY-VXJ%<OdPR}oPvv~)&<L<EzP?6ALu@2eSHcn>DJhAU>Vl^^TCp7?e;~VPFmN|
zlY7dVO?#It>w@EG%eMY&f%zP(YYv>rweIwS`8?|nv~$b1#;pUfz^bi>vO;V8-xPl-
zvRZ_o7F(MW;o=#qjp7+4)|C|YEw#RQ5}uy5{zg?3W!5!x-=o}GcmSZndgd*dKWBZ5
z4rk}BK9p^$vhFwu&I{I$Ujwn)8o-D6Me94XW2~`Wn?zq~t>SzT>#Ti?DE?V*l~Tm!
zlGX1QNL;qY`JxvMR(211am89od4xvm+7bvhS^uDzP_vc$801^5mwyM=YOT$K-8SnE
zI@-2d1^oaW*2G8XZ>KeZ!o^puE2vPe%W9Cp&^0S772-Fn6Lf-c+_d`973?1C7OFz+
zvpz<}R{d7QAMuh{PpM%3wl#=O4R@@E=~ugJ4ciKX1J=B1=)Pz5Ooq}y>$B^?GGvXQ
zn}YYPFH*qgfi;uL3m;lPpfzg5di)*)9$C{%FtDT6Kc<6o%wfGo`<rp=)la}PX^pxF
zZBy14=y!6lJwv--SDS<Z*W7HshJkaJ?RFdFciY-yz_P~{O)H*<O-OqmPur(--rZ}P
z=LJqLTlZhUylrZVCHdI8_W|>@#nJ%z*}`c`^0zsv=>QjCvr$eo(AG(B>^|F@>%bFa
z`<-Ig!M19O`-IruqPSkD?Pc17MA*t303vNK`T#`P9;5j++Lq}KmKfWy%@B{Zv2r0E
zXZxN4An~@*AhaE@rHWzipzTI6x|C>J?Vw;(k}b>*)<ZT!A-qVoy+jAj!?x{oGCpE^
zG7)V@ZQLsKFvX@?3T>&jlo^muv&rLNKHaum1i1{`bI*b$)Arnp80X`*_IJT~!dCe)
zl%2F)r`q3Bwhk5AvTQ%60?W1yJ81pOv6WMNE!XxfRaq6--ux6ig|-%Y=89~uP~B>=
zt%xqfoVG0shTs`n8J!<XY;p_4OKm^Xgnrf*Nc+b!+iO3;Zn^EA5k0H0-B=6koXsGI
z>Pp+pZ4fwb`<H6ss%#!5RDX8C*4hZP+7|W@jTdb_J7KBDc8reHwYGLT<<!|;xd8ck
z+Zwukb;*{y1-dWWmO20$Y;V#Pi7U2(w*VS#OR1Q&$+qGSlr`JTE8u90t>9hgY_-j$
z0`)eVKRvmfwgg;pa5!DHx%~?@UA7!LpkK4;u42@?ZT@#5c-{6MMKy2Ov^z1*H*JnD
z!P#SrOM!f^&6mn7`fS;>3GcVX(cb5lZ6DPm-?j<=zvr@rx4`aQn`<|;4A@w+0q)sW
zQdP>JjrAV7<QTI3>H%%{ZJqle_`o*O0;LaaqM6_swhhs;Fk*|K6XPS><6M{@wJoLn
z@|f*=e{^Qt_In9fCT#VTRhYE($ACCx`*H%n#oj|px~u*4LI}9okG=&h?smq{AnvmN
zMAx2nJM3JFqwKMpDAKyuK8p=jFS|FbO5S!k6GR`o7u7fU+D)gy>1R*44}bmbefQ9r
z0DE8tut575Etvc493Nmo_VI@>5p3tt^@|YuZ%?A5q4sUG{D#>@uVT3N+jG7JG2HHW
z`47Mdd-MO3^LCK{qaI~1qe`l1`zkt##Mlp>1{Q0NRX{M#ev6K;@piKnjvla2<^Vfr
z@1o#wg59?mW07c2ehgTWy@I?rWLHvIN3y-0=Iq1vMEWv7s=ZMSEX|(m_!nx9*=N$h
zB;B5s0@e)s-1lHN(;lsWw&V7fXQNLi>=SfJ?xcM~J+LhMZVOCg+dpcCT#kLsR><Yr
zf2TJt&n~1xVZQyJ576HN`_d&aSZH@6gGKhOVF1PU(-fOIZGYnns+Kxq&)f-~5_?G<
z8cXeOZ$x9c{h3M-E9@y-;mkSv&dsn}WiOyt<$^t(cB<9(D0;eU?cW!}Qk{M34G7fR
zqyB}K2Ky@%?7Lz&lKDn^R|o`}>>phOXttZ^1K}<9?LAa~)?xn?7ZIE~?T+7|?W%oG
z20)knLyE0lvro`3(rpi+&Hr_~Y&isP*ynY@;7$A7KLL8|)lb2vUVCO5bobfQC@0x(
z@6W-&-m+Kpg5|b7o{D(x*vG9fbk}bF5IP6!8{U5c@83PUKh-x4+UK8!!6Ccb8?bcW
zF8dDJ9@yWdgYrZBdJ6vx+h3<*sS!Je3_h|Ci~@|>_foCon7xYb+>G0M=pCD|FQQE2
zq}_WXv`pFm+yKnQIfQZquFkI|0CRJ;P(IAz?p!|`)LqWC(UA9W{%;=)dOC0U8G?JA
zvxMk{m$M&bLA;%pzXcC{oPCBdz`o8;&{+66uec7PzjM!BXbW&&k_PcWXXhUvx6e6>
zQoupZ6|^V@JI~t%ogvO={)UI4&a52}4|6zgqGG!J&K0!l4|m?&1~n1RuTbGjq;n&E
zRVm6jnF8w3&QbIkix}tql)#I1zV<Kd#yN+#fF<6!p%7XQIKPz*69=8MDAk_eZ0v)j
zMCX1wS0p)qRE16)a^AEM;zyiM?Lga6XU7;l-6_r|CefJcyzviUY0d@x7>i@h3+e7l
zhO<Hk^O??%UW1zB&I>EinG?=|v0ypr{BbetW;;Lk7(kBmv`ug(*Lg-G1oE6Yvw`J1
zGj>2{fpZpBp%yyFQ|`COSw8^P#m=?=qv<`sqPm{<aqqpm3%e{V>@B-XS&jL`n3&k2
zF=~n>_84P~vBX%@i%}ygDK13?1f<yLT|rceD7}cHf>c3@f;1^&K?Sjc|9A5J{h!Cj
z@ywZdXU^GM&Y78WHPP)~=-BpOpvv*Ji)dYR{P-NuE;-gxY^KQ3zZ4q9j*E5y?Xu%0
zsv9VATx|zuN*x0dFp4tA2&!|aaBQ9dQt7yv^sYD>=sz8(avXmY%xcF(y2EQ6Uk(AY
z*6~#(ysvY-waEmudPje{6s|eOyP<X6F|-Sl-{6?N0irh?<7Yv?$&sgxW3%Hc8?;&+
zr_){4>ex9Bmf9RgQ!4kS<B|&a)Zw^->KZ#8e|!ahyBx!*%Hx)!+ei$e+YzA|+#`+~
zC_;P3adnm)_un(egEV^sj#J_w^U87f8W7iQll8#fz3tdNXn1UEUJ4DbZMQxL*|+V%
zVu(a;+gS$_$G06Rf%)WZQUd)j+vep!Bx9R?GML%h%4nyVx9zJl7*fHucj$d^VOtAr
zAxgG6xzhdDu<gt;barp+K8MlwZ9AYx=ZkIr1@Osj`&zno+_#^NN1yNZ;6fM-+J1*(
zeo@<d2EaVF-6I06l<l8#FrU4>kt)Osw_mmfDcYVt8je<OH>aYqn(dC?L&SH-Y7H!e
z?D%d!=E)SZ<C{r<N!j7{6S!$RESoXxyd7~%;ZxC$=pyu0?r5ML#q}MXju2_z@e37#
z+}iPz9<DvyvF>M>c)BBM4D?>^2r-8<u1>1U80cQ7TXe_yI62XiG{EUeDKHN@RS!TR
z#A)p=sK=U|K7Svg@lMm^uyn%dUMobCoZLw9l+&btVepKTM9-Tvr%yVdk?!<}Qv4ZC
znG_z#by}W;R-RKt8+<zJ<U-{g1x~|U(Ra=%u>s_~Q|Vd^w9u*MU$}O`X|e(2qSFj2
zj3{z4<<lmu*y$-1>XkV4J3*t=Y3d9x%bbS&4xh@M9BBhr;WUw=)>oWH&xc5r)1qPM
zt9I(9ILcM0oK^6!)~TA-H+4=W@sO-{n)L`G*PLEbZm-R0cNs7{oci`Fpn*T<8GILw
z_8-g}VRUOS)5G9V9pgY(+BK$%mQf9i8SN@=FpWG!ni&f%TCGfs2KXJ!0|Cq)hB<`+
zJz<v6JHeSPx(DLPy8Q{10M;v-`#)>ax$$u3^`b;H|EK>QmfomJhO?#-r)Zh^<~y{t
zpL~KgYg4puqkF1hJkUQpPx-TtHqhbDkHaXf`N_dKn5k*y(*QR;=`kQ?{L=x>%rq(t
z|1^#YQfDPE1%I|q3*9;2S3!4feJy0>sV&hv{|kCNEjXBue}870?~U16c!O%zKHrm%
ze=j;P2_0V~8!@WI2WTVk<yD%xB`s-?`6@03&MiGW44_|^F9GPXQFiEE-gF226`jw3
zuyO{~O?>lxB;;2$(?#>`^dXR3y@yKp)+})cXRTQptgNpz(bIp!{wU1WcTRLp=KIO?
zfr1}Wo&e~_wL|gmpPbxb;GdOL;jx<;?1I7`<}fAJ-5Cv`doT>uvwAX@&cN<o#*w};
z=f!lt4hV1N=tInf5A$mbMEn`^gV1YXR;9y}`^?~6%KtoIa_RZ`oH>kZL;ixXq=njU
z_Jemo_OP;Uvcz7>#bkQ0?mxkVCmT;!=3dt35n#O7OBAp3X6H~Lst=n}3WK4nD{W%J
z*nM#zacnp}hvM03RAzFFol7r)1a`!H+J7HsU#CM4C)nXCD4t}cqrgsNGg4tNiGAn+
zgURf}W?-kVrL@F3#l}&hIh9@92)n1*#F1#Fu}&0nN@u(NfJg>=Sp?V_ZU;rm(zu_f
zo+h1h{{xsA-0%l*CX?&CMc;qS;>K@-Xf{_!o2VRa9%XfMxo@aEHIMu9BuwOUr?&v+
zEZ6)kTr1#a3<26X&Q%AP^W5{#pis!A(FXVe_nte(a*-P|5+awlg+~Bg#C2~(tC*Wc
zhpR4gB?9~{;W}r4m`b@m%Gj214b?DM&Y67zOBGx^CCVzfI$DNY;nsczOI4ijFlbbB
zo14JA%Kh&UEY)xy(qY3|u7P$|b(|v|VyovSlH@f`pcL(Ou91$GHE<CoNH%h(pMc!p
zHqU{DCKKmJ_g^#DO>y8B&W~!US~+*R2-~<m`eANzZZeQ|F17|R9h{ts1Uk7(m1uQw
ziDoc(i#tL)x^6CT96)b#hrFPEhZ|fC%)4CMx9Gda{X7$TJ=|FOuF`#O<`$3#oGFyz
z!4J92|6vk(xhN`q>*KtB2lEkk)E%Dob2&Xwe9W~`MCA#WPPvk&+=M`2KjRdXXM4^y
zWr6vEGYCL&mbI_MRJzC()1ot3mQJU+Qe-c;0`rt?Wf)qivZ3_mJ}s*>H3R01td2s8
zX|n0}z)hF!jECI}*%G>4D`f8-23n=8yb_96WTl0WtdgCgXjr2xgQ_rY$hMY1vP0(O
z57H?M(?FqH_Se@Cxh<<23O#rERI1GKkl&4jPoDDK=5W+ouKk+oAAIB=c!9eQK}k5{
zD^H@xaRmNfU}$8@-KT+M$=|&Wk}aP__iv6|DujNnoTXZjJh^ExOytX*Pk@}2kIskP
z0{MLM_q^PC1UxL1&!>&X1^E}0#JVUSxd7^y<oB*p{JBWZ+=1O<`AYik&t>^miq|(O
z5^31YiiNbMYEf(o1Zh<~843M1MF_ooZYq3vkamUb4JdRd>POM9rKoxc4<9Smyn?^4
z6ccHG<!m-A73wZ#yRX0tSF=pYY<Za-!H`UHZ?iAG!Syj)@&-KJXSSJ^ZGL83M`JGi
z&GKKM6=2q%kJbUR>2z5BpqVGVj}MtuP^{>%+0!VrLd+U|1_?ELMZvT%v(Ntli7}f@
zv9Z%;3us?>#;pDqkTkO(Dq>7Gt4)Q6rcAR`D&EXCEB+9jIc7Vk0yWp{$~5?$XSSWr
zHRYR?+oN^K%!SrsMP_U1b|^Mm;|hh#W}~NqSz^X@0;SAs%ND4Yo3(w4nW;1T!v=2G
zn|(pc+G}P*F2bklX0uPje4`mp6{I&zW_M^^++<cp#V5^X4f}xIYGy?->Nc};C&6qt
zn=uJ69cFIygy}M45}<I)?5_(Dxoy^%4szGbb{-_}nU%Xhy~nJN&gZ$BU;P%|2b%AH
z0KFjdAIrcDHs9m}^C9LFC^Q~wZdy!_%P{k&L4XN2Z=#fGg!#Hwh(?-Uc7#lf`SKcI
z$C@vsDvTrMvnUpS)O<HZ7~;*-Ho}=><{hsACBfXb9j)W$p7S7i!rXEWP|ld=j)NCz
z=1b^AL5BJN(%?*{`I<anW|<E+(WQ`W{#Ow+a?MZD3pmf*FCLxw=Ig%)=vnhq5+<s^
ze616h=iv;{3e9^dC3eAl(MF(MG@m~geMRPfyn=eM`A_#iE}O^UJCO2Ha~CQrEi><?
zh+?_9ejQrf<{#3bl-uTCoTd2lUGwFE7|cEMSrkC-G2cR;s=IIg8olZsnitZo)@y#~
z5+om)KckgdzxgVPAPt(&p?B0P^TmZwcUDRqBwdtsIdH~RdG<I^+>~c6fU-*|bHrG7
zE2q#ycaQSX1N6BoT|cAq&mPL*R1WB;d_vXq{>u5cfxTa8xDLew%4{m@Iiy_h4-^k8
zZ_-9KNom{xOUX(HdgGl^ekP$WRk@JrmQE{oxT1ANd4eJnY0BrL;BUIJY%W?EN=*%B
zCQ~^xACg(hdH3l3m#thxZ~q)+M<z(FQvU$%=PA=@hm)^t{uTOXmBU^@qd+;4R`utU
z;o0<4C|{$UWT7&Y9>EusUSolMQCSj#zDvq?DOOvg{E1?L#mby-A$eKpP1j?I^8E!M
zrAkjK5-^o3#cIe@C@Y_0*p<o^u|T_`{DR8DtCTnC%VO2a0yi+PDop|;Yn1ME3Dhe4
zTR`fSvlm11nzDrU$k&zqR8G*K^l1iZRBor^{5O<?wlLqM{BQ|eYgR6#E1^XhmkhmD
zld{GQ+%~0!6Sy~(Z^`jfv@55~1L;s^x4>Yh()tE0bt$EEh}=@XMhl{DrPD%~@K=5R
z0<Hz9O5TJ*u<GJ@fQG0FX<Zbm`jfWkVX8?KFpE$voCL5))y#OPN2^>{fyAgx)n-tP
zRsBP?dPh{Nwt*X`dOQ;_@v2-pynakoumL1N^~YL(o=^p<(3hxs^gYm$R5lI3&Qi6t
zz_o1ElQ-Z~uIe0JPkE}Y4Zyspa;OGog{qPkQk5!^Htbhazn;aAs#J?jN_1AMB5a{}
zRpp!jv>KI`j=j~YwqJluok|}KyY;Fb+E=!zG<6_1RkLUT*scoy7_APK{6`q<RQ1vO
zpi8xq;+wZrhpOOqx9X@1pzo-L(CLi3s*SYvxu?2K!KEJ6MSqGv-&c*K;Nt^TBAt+X
zsQQggH1w+6rUIr<B~c;IBh>>RVE3!E^iF@GdO^9)r>aF%`|?b+mX?FhRpSbP@<P?}
z4aiHC1w~5+R3~?%HK@8y9}ak>a-dU2&KB16%@-Goijh?R;A(M&wjFL3>(+z2%fg<%
zrMcT8BN7v}$6`ON;M^^g;c$Pi#moN|ycS_&!SuFRN(-BP7T33;<!kYs6<qVP`28@L
z{uaSUff8VmL3h)Bi@9^rI$%*n$H2lY&TYb2!Yzsr@ioaKEJg)GBhunudfG-?L^q=q
zV{wpv`&f%f3(;z|h@i006AKlEv7Oc0)sS>iPYQ=YS2cT_yjOqP0+C(n+4*pExBBNf
z(DPIW(r#?8dcq2L=%xO7B{03!N1Y+LPhDUE6qB!d*%%DeUww%_5)h!?cL*|v)N|>K
z*J1UN_s|!pj{E`c2dT5@u@$0jqH3{F^-MZ05T@=Oi@tDm!x$(;s`t<$ElRzVgI=`S
z^J8Gfs2eCPc|<Lr2<B0B+IEP<spXRZ7H?9Y90htx{eYg<sp@{Jqdl!&J|Ea;)N%B3
zOH=z$DNDL~DV6+WsO#>6WT|uLPR~|Pq-0^9`uIoCJF7l87m@|)t-rwT74>AQ@~%=_
zsUcadUP-3}ud4H?Vzx%TU=vVk)uw~wRGm7R9y=}SKd++Is!r)dXPerRvNAW-JE`Wo
zL*29r1MOB{rU3A5b#xsh@2G|2Fn?F=MdeHP)oV|~-v{b3RJ8d}9Xu2h+^hbGf)|g~
zwiHf!q7I@s!&CLg!-4Wl{eh_no<3I}KMqST)J_)g;-&fk)s+sYJr-h0d@O60gY2`M
zaU1%+mO;-z{4AGz1g5`bK?6vD<=!ml?YC6Z&g+2XpLACow4A~N`jBPj8vr|O>5~V&
zK+D!<w1O-T4}nOqWkV9(e<79=KZ9tfWqAYi!!19e%Do87Bd@@Wv`nYkmncg+I$0iV
znRgD%7|WC_j4;-6ZxzT<%WOLI7iU>S0fczV)&F3G$1FWWFppa{EW|)hSpH25qLY^P
z+hIP@GUG##B+H3=DF2geX=y|=#j=s=cTZU!oB+jC%MtXgoYR(HQ!#LwWotBuhgD84
zh^N(<C6L@}b@?^;6ks)bE9?ea{WhM)Vzq~=2t%#nz2Rt>l{gU!5mpOmpBrg4nX;l$
zR*ogG5N)*{ISbVPS-lqy^RZUe79c0BhS7TLjMZ;{f}~jui-JbF)o=8`$gtWl6fh-L
z)iYqJ)M_-X7|X0uDUeWOwT#}4wN@Ld;dY(X7ApIww|YcNuWMFYY#?&os+=Ao4OZR<
z;9;Xxco#5DH>@_l1rtqHtyeJl%~l~Fz>5~E!@okb)#@#py*8_oZ$a9v+G)etVHHBD
z|4yr+X@Kdn@~0^HEvsHi%=KD*KtcFEtH-tIdt|kUj$!s&{qhV7kFDm<N9&2ztO4{r
zwR(LA$TO2wF2$psTWP3v^o3R5yWqaG8l<rMfYrmDaBa}4^C?=+n$#EQbJ0|90CCm)
zK`&J|jTcov?$U4{U}kn}>c+u~J(`YR&~n$b{|reFO@ah<PfaGhhxTfAe*>nM=IlJo
zueZiD<|54dXv(NOXP?H5((JyPFN47J)9j%s_19EAL|=gBQ5cx}HSZk7v>nv^``@}q
zvyVQSdswrEs=fj>dGxi3AWb0U0D?6US1~gons@ur3f1gV!C;u?jV726*PNtuS)?Y&
zMD@y1nmjrx7Oe@V&`gZxpY!O9)%eXq-x1BgI4B;~#Fv7^X$E3o;+Q7xBMc@%vxbMr
zam}hvF$pI$&6F!Sskw3lD2bZgKY*E}S^g2cNY;#u0A`9N(jOwHG?BEyP1U%MG=Y0s
zlW_xMO4Gc152ERsV2b8sXbN{gKU0$(2#qYw{WoDgTl3~Rv~n~$T5RQNR^`K)i<(Wn
zK)a+_y#xwHn!sYrQ?bT_lJ!*@!4o3YnnWsVyQ=B@7R(w=`e}gGY7%|u{AHcyRSxXd
zYkt0mF<sNBPDA6mW-f*28Z=#0anz_;NL$Psny_Fnn>4>ups86i^<SX1XwDyiLaQcs
zB1CR#8h-(^U2~0cLmiq^&(YVZx#<jrF3naIL~dzn6G6H)M}6r2yRCVD9>#k|(@B@f
zUCpu&p>a>MMGt0==4~UG_cfw3G#+R&>)}kFCjKp;J<?dwmrwgOALK#dv1WY{$P>*1
zI_B_H(@iVJXBwj`2Krpn7Xbwq>*noXx>}E-OuU<QH>K`PyR3it9b?*K{TnSl+^yfZ
zhL(r*hqRLNwBA6=hP~Dw)6e8({U*KIy{$W61JlR)3Z)14SszJ)U0>_nbezP`+CB=z
z-#TtSEXCWLH^(3nZ1&55dBSFVI`k54J}|(UWSjRKVd0d?W_<=UPTQ=a9bcNwFQZ{8
z%jQQ7L~Cu5PD8)VCh9}<-L!cWg;u+b`%1JrY}&toey7dI;ZX0g`JUb`4{e6fcB<DV
z>@7$>w%J6<il;Ual>U8YgGeLh!sa)s0efMy?HaszX=93|NW_56Cnv!jw27h;r&l&Z
zP6EwYyOXYG7wvpnP`PT)Q;CI}Hh2ycytVK60ozA=eIj5&v?r+OGgSM^AHxpUcF_|&
zLi?ZvB9Yp^CZiRlEqNW1G1|5XGznVsawsHeRi+r&&D5qPf@Ep`paV_W+Lm`9b3tpW
zg58VS|Lv!%Tl*WGaw^ik{0)l5TJQHkE^C92L9awRCIxz>+UN8elxY*z!*01YbSX%M
z_SgGhR%#>9Vn|oCmnopzpe<YoM;o>84mCmXhPHAeEH!Bd=~E%i+QnXIwP=ef;YF*~
z{3nn$?e_y1#ZB$jhfr+Se)trv4sCclTAkVhyWwG%_H`cWx3qz;;8VBu_H$Uet^KYB
z>UXqGv(dV%wHOVNd)i_u66n#sm`VB9``RKia35$zn!ShGkguTMtBtLPYkk^2id;U@
z-l3>}zjn>%bggUIpWxvWZACdmo@zTw(DzKc^C~2tYh5S+`9dqtfQgsd8)`5Iw1I!Y
zyfgnR1>RkF!(&W|EB{45<$v7xHX}rL@pCF5bC73>fPIMnZZ@z3`FF+wEr=ho5{jYx
z1Pv6!_`WbO!}+higufB|u^sR}lGm4`6~(_rtGj6aauogAd>jQpV)<q&6Fb7E&cr+&
z<u46`dK~Xeg@&ehej9!8=NQi|fJ_44)qvJ<zUL*pIKf*`66_?ep&urZ*SW()693>7
zB$N4S7T78L<RO4L#cOQfeJcOzH?&UkVa`A~!v{~tbfxj{(Y808=X5~H;Af;lGLuiH
z&mLr%_+iOtX7f9#t}Taui)y2C`BqxE=JD({Xyo%V>H&I|-%BUA3i!Kv*geNzKY&r3
z=j(H!UdZ34eb@y)gTg--`9=!;UE)X3ZCJ!>Xa!Zw=TRQ>GC#HtLn`52{m?4qO%=4t
zD&uXgL8F|Hrz*J$-i?k8RPt--<#vS+QbM$fFPjLFYJLk<Q(WceU5EJ^-htkmwfvWK
z+P#jS!a<~-A4$~#*Z8zeAlLZ|$*|DCFQAoBBi}(Og&X{g5J)!hohBM@Gk>rEBW&SM
z(}t#%j}al-#;4Oqv2OBfIv~={UpBzC4&K=UeVzQLpTJ-j?>-WJw|FNi^zY_Rb;96n
ze#t3}_YOabf=GAyFOI^|dwdpc`g{1{#Te3k-cXI%e!y3crTgz8|2h2zy}VJ0neF4<
z1+*UVb1B8s&*#vx{V~6Qe%L2``DK7U<*#3arDuGQ2gq|?q%h12e(f4azT|rrLw$hX
zn+3^1UQEDvU-3P32*6p$9t+|kY^aBbt1y2roqu){{Ak_0OGy0;&g>Qvsor>xaQ$zz
z+=U;gEY(BUTm=nJVbvx0v{x|wi9Ro38J%eG7H-wTl8=x^6#)B$ZIndz6|_6i=O<{Z
zVcuW3a0DU&!gs&H!~KGp8T>sUl;A+1Nq$h6O-D5k2}kHW@?jy7VwHiyaXP^tB+TE9
z`3e@+ctAfyI6>*9P@!xQEQJXc^vn(yv;h!_5RQBeOOZliImQwt<k7L4XyMpqI1?k-
z(yKLAs1Jt75#iV#cyUzl`T}~UIN={UIT9~;h5+rD@a`RmCI~JQAah)(r{wtw;RMa>
zNnyMIFA{}~BLJEtIQ7Crvd~KD>J*{p7DP@7tLeF(D!e}hBRnlk`|masPSYzVO;}_N
zk#yl2oma~cf_acklQ7{=n9ma4qWyBVz|a|$93jjRtz02?GBompU%x>sUl^p=-C3cR
zo<#-1sdbP%Cxni{Je?Qjt;Ns^h38LU_kwV>AFYc*1Emcw39DS8P$bk#AjQHF3K?D&
z9#fG`iC|KMVlGPs?<8oH2?cQgEf>!Gi=kBrOOFAqQusCwtt-NAy6>xmQ=b8}T2Ru5
zU9Jk&k6^w=@T0=cTH(P)wCaQj7XVf-EOG(4CLGI!rR##*JLqc=+y;QsDBPm*&Ktrp
z6FrQYghVPZX%;S17_>$BjDtq2kn|~9ZNi~tfVnCB;}89Ip^QQg9YO}J`a1=C3Ve16
zs>1-iC0J#luUmLN3VOGNWqn}Y5e)SJyDLoZN8dd`(G9&G!Mh%#zAr=%rIgSE;oN3i
zR}Y22uP};U;Q$3N`-CC1LU<&68V{I$;qyk2$HHrr2zw$_TS4KeU`G3?XF@bxSI-44
zJriCC%cer|r7-<RFb9NXwlFv-Jl+NJN@zX_J!f%_1yEeX(Ja0HT*d5EaNWcRDvRAE
zK4BobTTJwV%pUPWTK>9=yJ!{dAttl~+f%$rm-SvT_7#Yi*fIn|^A@*LK*2|J{SYYo
zL{BZu`--1ZiG-inL@QN)@lQ1{14Pd^ps*iihv5D@AkL?Z#X<2Mn*2jzHbt!ui&uI<
z0!97+OazIa*FrH^oKyhG5Ydx%-Jznb2l~Rq9tw_}6f5cMQKDEd8;&N4R<tfk7DrH=
zI7PfnF`ZLlDBUBeqKS6fr^UZ%jc7U}E}-RPns{a_JWUs0%Yknh;%3@;Wr{H|u$v|3
zQw>VCxa%B1bHoqwpqMMJe+Y#<@qQmn<coq0$XU_B1qub?Bp#UOL<=fvKQBJ^N2^f$
z^9ouQ#5X8ya#1`_kKRiraSkQsi$pJa*cXfUCZly(d~G;Pl!z;7<5w!)Sp>y0@!~ST
zl#2`K2B;7h?}Ve3ViLX1u82RZf@@Xcmmz3Xi+ZZ$yej_w6D-w;;zt0h741?1T_-lv
zF0x*<qxz$3qA7-!n%Bka5fE(<n+h=OMsX$!(Hmj~)mt@*<6psUvpAhfbX&whx|>_Y
zg#j?pCJv#?<EGfV5+d#594h_p5NEyzkxnsu6<S@Q_A*9xOU(EJVBO+kdJ^9jpHax-
zj(Ek?2gSSM6l)l~C$>BS=@Fx2(Rp7ydm7|{SZ2hS9*RAIaIIGi%R{SAT<Z?IkHj}F
z!cxEZYcg7oMbFg`c_NN(1IknJ&oMCnOni@uC7z4%Lof+1L<8k5UW%_7Au=G2&oF@w
zidu>uzY=Y{;Ec1hU=@buA~l~u%T?;vVrJZ=w(YRHOEO%8rQK3q1X_C}fo@oLDUJ62
z9@0IkT=kSz=R;wy^u-HcdP%Aj5N~N1UBEt4`BI4NlVtR|_m#p&Q2x(P@;eGNe@Wd7
zZh*9qewqDJ52Zg2NEiFTJSa`|hfjy3!Zi4FSc<2@%s?rVV!A<63LRDomWC|A=tCsc
zAef=j>-2;PlRi&|!EkBWj}VEFYL`GHQp%&~M3iJbhwi^<DR3_wj*;S=;YF-8jP_wi
zq^(p&cvLD0Ln}_o{}X-jQqT9$KPL6k4k|(VY!}FJDd!9%Pe^m=RyiqM^#WL;RLG;1
zBwek8rDSQ?VyLG`e@})przDrTP)L=$>>*-0E%lW{<BT-sEpXE$i?=bQ=~7TGm>H7c
zG88i<<35OHNj4O^&z2%-VUi=M>A9XOEolR2o)mo?3i;CL7f?Sd8OEcpK>A`R)Xzz-
z3&1=t84jXVD2Y~(ydZ7hz`SUZ;@<=4CFyNn46R7IOW4KIl}OC`WhstQBqh??cJ!4>
z%jgAECjHt6gXK~IRpwMk-xou&Qi|?H-xcW){e)Fg=@^)=mV)MjT$M(xfQ1@q+56C|
zm0nS}s!pom;7q+_I!eFHHR;5^n5gU0)kkouLE1JNqK(pDo1lL~>WGG=CMjhyOf*aN
zuh7>bJskm`TBR*5P-v5S?*iqfRJ|EPYnMK~4ig>HSG3FNlosuSNSEXr1`D^O>GYKD
zmb|D!>bCT@=@z(mB=aW7+?ASXD{)WSavmmnr0;1-a9`5gL+gQ*>x0%qX%szQd!=!-
z2I-RmXoLMo>ZMb2{n8dX#qwC1eH?B-k)~Zm>#6kKPPCp$ayoYNT>9cO=)I6qXv_0b
z`e+p8{|2N#--XPe6iM5ZSJLZ?AmgknAB2pHE?WZ=uDV144!h~tF7)lvHGT}A4(PIJ
zzj{#Tl7+rQI&Lib4(qlIheDuk%{24{>0YPmgAkp)FBC#`OQRtYrrSk<%W&N+dwTyx
z=th^pZlvzXuW%+xmn}d)S~sE%pfS4HJK%S$?qdQyqB~Df*rU3dzX21c`}-}BcwH$4
zpO5L@iG)IeE}Rx7$93i!{Jtl2?^C$=r0x)X7&lRO+!4%V9kUDyDY{ud)A{F9I^7L`
zrt0E!uyk5iN6UsYx?l>}rs-6j@F`t4ih{WrI$H^nnYxV>f63DMybflzZYphEa&&G+
z*v-|g`w@M4y6;D$FJFht3AcmJbv~E{y6iTHoYS2k=6T)U-mqXQ)P10ai3_?UI>>)f
zr=cU-mvjt0B8qfbj({oFX($+bSyxAE(-Pfk`a(&mZq+t`mg%CV!+g1J(okSm=(bTT
zw^Fyz59EqY6AEUP?p-Qit=5TGA$e8j6An_NJF^33YfU=02AHVR{WAli^}3xDW4Wfw
zpNY=vx@;PKgRWZ!kw#tG`|#<8PECu$CS8s%K$~@?bRMHc=X)HWt-3{{;ZvKg_+yZp
zm;`{e>lXYAXF7B%Xdl+86DY{urAtTx^OnxEk%C{{y3L6|yREZP!_pnyjs;-e)gAo^
z<eskSD$sg#Z_{q@zRswI{sUbI5Asmwm<<nmbuGSdtxp%Y5R>;vXSEv>)UVqa4Y0?$
z4`xF0i7wO@9zNAI(7}Rdy6cA^`CON8qR7|_-B<%;Uh0I`fHt5LH$!w#_sK)(ztSBk
zg^07hAOs$|=(Quza@CKbMX8&<P>t3u{Wm+Iw_9IB5r{qdE~-j**SGuwriXqC)j)gd
z?@?NMufCs3ue|i_los>Wuc)K46d(NyM>w@lUvwCXzWQ(~=<w55mO{o~|49M#1N5rZ
z5ZSNqqnG&seH^6&4(b=&fcZoE8uIY4eo8e+p#Hr{Pzcg5nh5n^{pLi>VTiuS9s>;3
zZx{&@rvF<HuyFmm-c)}Zq5tAOG$Qq1SHPJleVYm}(fZF%K`}=EegRss`r%#BIHLET
zh1OC1uYaHwr!Sn1R=mE_0X`kmpW6Utg5L2cz>e!<D0p>3zmWE_C-uXAgujXUEj<uP
z(yx6J(8>D6>#6=FMgN8+X7-f6r3q-M`dKT`d0L-;7tWl~>sCNNO`ofPNV<NNBbXWb
zm2^%ZQ-6(8)>-;OSIm00-m(aKIr_(R9p~zeR7#Yme?VD~eEkv1Qk~TsY1Rt#$$>C*
zPH!CvFw+Hn2z_wtqJF}Bh!*J^K7zqw{hMFG{mc4InNTdzAIOK_rTQhK&{wACK8A^M
zy^6AW75X7tAyTQgItcYEdONz-tMnV6!BVw;g$w$w>Q$6`s?q;79sbtpJt#&}r#CGD
zO1(+n^bp)@dg&B?`|J8``!JXWefm_$+|Ylx0L&)6oPt5k`gdN!;THY2d1$rj3(o+%
zP5;OhFgNvn78pdkKEMuMbm+rI0<%+Jy9ds6>H7zva7$lu1(MzRW0Y6AtxtFx>UZ>}
zalfN^SHC<3<et8KITU;J8|gK8U+>OA=7BznHvPT&Gn6~-)8C;5;3NGIDy!_*C)36D
zSU*eyOHcIbQuzB+KaYNxXZowOJ$bJGZ;kgtf9W91ztks`fjOYRIsktM^}VKAa9`<j
zXxZRwxYGl!i{S>X9$XC{wSu@AVpqb8U51)Vz}{`xM1_HS3<Z;6(B06V1rZN}i5^Lw
zhOy&;ve)pH7noj#AG<IY-i8YYq2OcKU=D?ShHK^M^EIgd+ZGutGfhzRH_W*MZh*mx
z)*1T^7e>Lw1BR!qAO{VXDaUunFzFRU4jW!kL@m(pc|M#8GI0MwB-n6aK1hgR^?j&^
z8hYts3p3PC!!H?bh(MA}9$`rAM=R2>imF4R3`L)!6>a!#0@c677-r2uGuCjK>I;t;
z-pYohqXq=hagP~91``}_7#Re+#|)tp(Mm9MQ5C>(!}LB_I$>DwH->i7V8wwX8bW30
zOEQGg6_{)Yr&W83p(qCAlws|1kW@p&6nKBy@Xh<Q{ybwiNoUa046Rh*lWsU11(IQS
zLF<J~!{fi<OqRhh03*yc44wvdj^Wz~*v&OWP)sP#@V*U3m~RN$4(3_IjlJ-qz%cS6
zES)n{1Yz>d8>0V#g+jx<zd$Y+!cL>_qT%?TAf`(Ob6PnT8BXlM=!*@nVqy2P;S(=-
zQDT^s3G=0f(D`VU8N8ezQf}CJ5|%0qs2sqJXINkdg)4^a5I9q1_~CDWRvVVk*EOyh
z3Wva8jlpIu)N2hNIYY9}aDYBgTW_$Zs_APc!*;5nzHZPKL#DydIt8spgN6<r-7xf1
zKDx;uacDIgl=e_;F@)0(+iGCmg=Cvypc~AahDlVj-EKHN9OgR=Z@i94cxd1=;Zv`{
zg<|}DhQBF4^vDqZJxIU7f}Wj^4W_>7pic}R(2Db^;SbvXJu_I<qV?P`;U@ZC7&@uq
z^QB=f73>TcdT3WRX!tw=Feh!(D3q3HyD<YI$+lH*Vi2cnS90h}wLKL8FHYNjk^$x!
z+fENK(`?6-K|RAZiWXv7wr5Qg!ppYx`5iL3wzGBsEzkCA%5dh}ZdK4PY8yu{nF8A%
zeg@h(+qUN*=WX{yf>~&rMA!2L+wBxvy<}TK%Z(!2u_xh7vF#``h?LllqVol%wlQ=#
zq|ElV1DNHuBgR3Y!gk7+^!}@~ZJ2@?x?<~-hR!P6IkteQw(Xh)^H*&b$3nEmHtQT(
zwYIBu@Vm}-Gv!O_ZRdu8dCm6066jsG4Jm|)2HQ4zM>X1({enT<uvKq_WRq<*t<#%r
zd%gs-#dfO=eCn_b*-Q7|E!%CVO_X=rR%sx5+g6zl^LK2kR{-X&?ag;U?%Cd=_gIfD
z>w}@)w+&hb$%nSTI{>ZM_FIbW^w|#i0OXPFgGXTY+y0yak;k@mPvGwp+jJS2Pi?2V
z($8!A#%(zB+_vNdeSiFgt><1eU)t`w2onRg&#6FS(Dn~&FkjiWd<Yn4yWuERle^eW
zwnd+--EVZv*3GVz;wZc9Jn<Tp@3ymk0Fga*M}NW4-0h;MxZ1<6<q#x2?E-Buh`n~h
zD`COQZlN!j-gW{d*GxWk5-qm&*(KA8$k)zT3q?P>tD6BDU>8YMlKbs;(6>4c*lnOx
z!$G?-RJwJ@uBQ>d-C?^r4~PWXHPCA%$nI_>ECt&+Q7K=D-A*d%47K}a1@yw~=27S`
z+)kPRW`x}=3N=QW?55E>J<6^?0mW#$u3BKn+Wj7h`8s0v)0Y_UQM=bEffr|2ya-bg
zZ&yX($OO9wRB(F2t}p?XPTH-ZJWrC{XKO%`?eIV5;HhWloC>?A>>}w_Nwxcjw&JJl
zA}U}Z&90TEE8WhNMG55$yWMJZX4)lFxH-$Ncr`$??I!rZ#T>hX;{cOuR~LX*o}Dk<
z+xd1cuYh^hZlM9p0y`(lRiCpPHy2>%?PdqS(L%e_!(d*ps}?bci*{l^`YzeECP1&q
zZX7L^itT<dQQ)P-?)Gz#QoARVc`LKq!@#$4yRXKfRbf{u!bGLrRH_`iVz;Fl%;$Fh
zivgOu{ZACD_q6|oVw`*Jx6#||uzeKm7J}`iI(QLg-@gW9iL`(42GnEhV<tl~-hLd-
z+A;g4N{YWE*uN0q)Ny+UIV_#9PoNJEoU|{Q1uqiqJ?XuhWN-Z~&8+>qd4Nf=52n@Z
zDSLl9w4Q4JfTsJj{bnjPJ7YioU0|l$Pgx4R4Ev2!!8~XG8f|^f+gDK?NrnB=e*so$
zKjS*BKd;ztTMfHa_8zpZs<!`f6`Z+hKW#3CR%1Vp0=>2N_O*biv-gjKe!YG6Dww!t
zzxXVixo-dX8d?qZ*M0?PqkZlO=-sd%+XlTR`;161o9#ypgI<gMA2Z-nt9>lRgxc(L
zuwKUZ$L%96f!$$Wk_9w32geSKX_v!hS_JHNnEo3S_c)CG6QH3Eqvt{~%;BG-XoWkJ
z&{{si!IQog80oNN0$NcH?*FBE9a1{MjCI&S?~$Vp@0|rol0%gN7Lpy@A7HpC4yl&t
zGo5m<_zS;NszWLTBu+b&oI~r3gYSHJn&!|(5wU!SD9Yxab!c=(UxCAKwjd=AFX^W!
zb#Pw_Qs%Im(vRg1Ew_PE>G082no)-=3rJQw9HA2yO%6BczHfHur`>vsgWo!cw3;0D
ztc0bT4p&wHrrqIJ`Z&)c2N{(+Ja%xH2GJ)Di)%3@PaWKU#P9RWfv3mw3x@={)?Ydl
zP<Ua$;ffNiK?ml)a(ClBdZ4-(H&ZpJtMQN7@WRbl?E&ar#+ooNcN@pu!07iFO?xQ0
z?qNJYD-%!S{W_4n#^p{JjF<8FQ26a_Y_EZakI}RMmi8Inrksec@dYjG{EbzIpdMfh
zJ&nHo#+V;q_kc0=3iJ*d?=k>8WZeEXBo7;hIbghjM#Eb41sfYFKpbLx%d`L*VMdE6
zbcP#mO#sYM<CBf(j57*f!O}6~dvrl07%$m_oG@Am7-*vLGujy^8I!55KiSwtwHGPI
z#XrE{DdSiRV5S=Xrl-JZ<I^;Fc*Z#8WAvpNM`VJe8~1(-ungmyKT-WzrtupaaI=l$
zGhnySm`zXX3&wZKpnuUg+#c><GImjRy2v=O5X@qu2VEDJjninYS86=A0w`t1{$TW#
z8(-$4uhv+45suawTWMd?Y}`rp94*E^JGj<rTuK}3HsfcFbpPEn9()f5+l|U*=yw>+
zKE@1n8pYoM(`9^0<wm!RH5%x58}HLidD|FAMGSY0U)4eKuJOn1@WOAXcMl6w`15AM
zW>^_HNcZvE@9l?gZp<9IJ9aTHaUi>yFKg(>XD(l$?@zij(m!Z=Fz?V>)sxAgcg|jB
zH0?3Hn5he8Llhy*P+HobVJvC8p2lb?29VAypaf9{(?S<bCbQr$T3Jj#m2PD-NB@FI
z4)d5w({q`1g8<88bW7oIKC_t~?`IiVF4f-@Fhk#l%sIxw6Z+?wHz?&-$ZV%9TM1MB
z-H;)QF2+QU>s{=Y8_?g)F8Ln}?qOqk!E|S5{sRRMwmKCpPd1jy@Ak4T^m_1O-`D}B
zH~a5&DEP3yoPgv$Hewl|ec5Fy49VojhEj!*KRY`JUIega2r(%lSRQE*#Z}gX-M3;7
zH)bMWytrHS+z^F7C(H!)A<p?V_#47$k&60n+9!8WE#=f{RY3o!!wWJW@1w=^wDMCx
zURq4a_;1Fw!o452oP*@HTwH`ExzjKT<$Ex}7ce$2rky^3m(F<5QsEpk7GKNx4_wHg
z#qS_@?SC-(itA9oA!pf4y5js~S5$!Zm;JLHtthk6bjBvyEQZn*F=kV!1}@fYDuvuy
zG^Z;d(xp-K0JTT6eG=uL`!!M#L|<yulOgJ6{n~K2yVv?0)uQ=ZThWQPK<oM2(TcF<
z*Fo~AwVujA;;h#Xg%|PG_b6|D%-WyA;R)8PCtAm?hkb{kpRg`02G~jK2YaBNX#I{C
zNRsuCeVCln*4At3`xn{P8(g7r&U((LKr6O(LsU>+X}x<f^sia3eG1U)*6$<$rosAB
zAtW2E-!;Pg4eK{ofb>|8o(IYM)-Nui^}zZjg%}@NC%L25YklJc4E9-H8i7GPvi^y(
z@BP-phC$)6b@Cp7nVwjm*an$r)?))<{<*a`m6E@(j-ZmZm)5FzFh5}JPV3`A>$UCB
zcx4?o6xhx-m(oF8Y@#W_?`o608!dO6W8;D1VZ%~z&(r1$7wGM^aqk0)mreg5ei(n7
zPj7)4VDse~jB~%qrmP&?12&QIuzS!(*#xv$8#aMv)@ByH-xF*G%b}5C^ZQenKW+2p
zFBoCAP3dh&Hri<4L*EUXU;=HnF$)E0vAMPm<fhHijTm;j&8K#-^vtHN8<&o=wowav
z-r7U7y7$qV*42UrX+O1vrAY1J$?!W)`!@?_qIOyr^v`HZHo{Vl*02yho!7d$K>xC~
zpX%eTXj>_(T(2$kM5|dFK>^23?e|F#xu;#R5_TVH+dSdS3+?r2nkRm9F^DJMV+BKd
z`6LsCPrUf66sYm$V{n7XefYPMps|m4px2i#zkU^l?Z@lN(emfrjzA=UUqyAq`}x&l
z;r0POs2+U>`K&jfcZe_h6kvz>nque$@`_?GV|fML?ML|6&qCoSKdqF;$^X(qE4FyP
zVi4S8{4X~ElfZxZ9o#?8H)z2;!QYGpImtKE(j}2^pn{+zej^1VlldtWSW4mN($@PF
z-}@3Im0$T32G8(5{*X-L%PC=&&Uc)JLI&?nx#>*)*F7Lvd_WD=KW6i_7ifa{d>Uvj
zKmTJ4EsxKnEoD9*vmT0P`FCH3YX$tU0GK$(52r6up69Pq<!&MG?1w3-<PV2pOm%$e
zU%+nS{dPj3gHIm{5AX6RR87^#^WT8^f<G`D&@XwHYC3;2z%LyS{Xu?fHacJN8)$#*
zER3ern71G^1DcN@r=Y|>!7v^ozJl%qK>Y;Uq3H7$8m?f1_6y55z^4PkT`zzg6gsHX
z>W~n-7UZyS%nT$@7})|6C45g+LeWBK1X`vTVeA0VVg=JoaE}OlEntocDM9cePRPB5
zR=l7ZglK{=BMhzMLSsDao)9*S!#tf79HL=9QBbVL%p?gv-GXGY(DnyNitwEuP_l#-
zDvUQ<_^lc0c|tm!HOUv261j}}kIw;9A}pwc`7+`9R4A4U!BoOfCw%w>!>$*)D9L+W
z_%#l88-$m1r?v}TdZ2X(!~D?d6iO)N)Fl}1Lgbb(k+v$`LaH-bw}s9NAa{gW^fI_B
z<kCy~p1}PIg&x7QLJmv!g|9w<7Y~I0MWgjl(6qsBukh#}!1M`oAHt`8;nospJQfaF
z;Wv09lubqJsbIYr<eAV<&+O+y@Eth%LfAsji<g1}RVfSzy#)Xp6e^Cu!Yg4it&g3>
zv@fCOA_kb~D^{-Jk5o_ZCf3uXyGy*3i%uU=Z3pH)@je}=@fGi+L()$)+XS=#@xUtj
z(Zyf-;o1Rl2wi0d#c^BUMYQ<*FDS%_O(YU4&NzqG5%J@@kUT2(1pqTnwEP6Ec=3KH
z?SGDm#aE%2Acn-j{o~?TKXjfDx5R;*6eBC)OrrR*4X!1LdEWpnS<IwIc#7B&4v|!`
z{vCjx7QH*rIwOvK8?7|)d+JLUEB*^vi~l3NOffwkj%JCQDYBU@HkQ!&n;da0Wny#1
z{o(K;PdrOWd=xZLUgoTLa3(w~5D&cz<~i|}1Ad<h(e*IQSBmW$(N`sw#6z!IZ2cdY
zwc=|6T{_~FXK39M7l&iIdc>kPKwgN+6mEGbwq1w$0dXD9)|ilezwtS^uS5@8i#khF
ztl_DPWLgRLU8R<ru<IrbrC01OX~lLJ+%1W;+}$G;e~CVKN&g1WJfyeZ1d6Am*$wr*
zl4mGd-qKiF2Kh*b<Y4ZT{#Xh<UnzPKp#7w{x6o(umkJAj9U!$+x^lmCjt-z5kk(VW
z|DcpfGjm9C2|(+x#JB)7P#VmKevowJGcbdtkG2ClL>i<7eY{i_2<9<q>vS*^q%F(Q
zIxfXH;TJg}Nk0Mlq*ONs>Pgb?=`fpYl45%?rWA>#E$Jyqb{SrzN`Fx)>S^gx8A#;2
zy;Lc7>fL2da3=NL&LY5gj9&K@Ow^C5G=quOF|+c4GB9Bm#WDvc_{V}7FmcE#kidzJ
z$DtQA(Vt#9Arsdp0POTcu^HwICz?*^Aah}&`Dc(RooJ-TPS?auv;>czR9;FY%lPw)
zvoHSsRZj)Qzd4M=-@gwrhZh@dI`H?l0a~nW|H~WrJ36TV&6(lH1J;EZL0e;2=5ja$
z_A+ON0mX|kQ4OLG6G*F3(?Q0JN{bFL_ts*p;Y@i5P$C%dF^!x##h@>qDWag?F=p&F
zC?+t;bo}Z#Q#=8nsf>aSsh?)z>C(tyde)$o%hU}A$zyI-Loc5>L=_dqjGA)Rmzf`G
zfLX%)K_B`mH8CUe&{@k&d>d$W%wY;$)-zM-1$B*?=Lu#jbNdoJZDZ!l1i8tKqex&o
z<1hvz>|p+K1!yM|@*3RkV#c(h?-nzT{OxAqj-c-$6Z-%bdYNpx_4}AFDe&`%QBrw-
zKV#~l+Pnc~2IUh5nL4T`d&LYp3NM`5WAs{fVWX?SbY<IVrQ*iMErR4Ob}PZ`X47c1
zwTEq>y{S99Cm13gY$7F(JlTzVFv7iTa}<adYdI5=-t0&8O7LNQyWsCW_BYczpuX&A
ze-J-*2|e-r*)yZi3SgV5?sY$V*9K?@*fB$aeUP2WLgWzJL{ZhlY{QS}3uI@11rtGR
z!ZbJ<%<8G^J%rur3!g$+b2>^E#;&LEQ#kwODCiw!4^s*{j@9Ovz)fQ31Y$7BY{W5W
zq_B$~K;{(tC<@Fhmg@vFn_W)<jU0CPG+^hl$=|_l9=qXRs9$6YzD3_9cF|r)7O}%A
z+EC0o{0a5T?B&nkS_yk#D-=rEhsOckz^ZORuaQmp*&NTm8|=~LP;6p1Q((T8UEdAG
zc2@cb8XasQ?aDe?-589bi=D8DeqT0j3f%8zqc%a|HhabreRtTPa`ZWKo!g+`&TZf!
zvX5JD4}%A}#A#rLa+99JZVWesmZ!(LX(-+`$xm<*dtm+~H-fI&M6Q)Kl}Vf<B@mOj
zqO%xp4!8RTOyqL5Phc>Qix~#j^11J+?)5BpQjfj@uFw+Z&vP^BT~Nr?eE@QSJ9q}<
zBDa_};g`6-e+G0B_g5X%uX5>S@WRx<$s7RF#;x0j&Th_iGq?}9`;<R<!Z}eyZjd|q
zH8l3fy7$6;cUdm2Mm%JbrlaL4i@5+3du6G#Pxq2-ps<&>ta3J5fwD(^@Ha@df}R_}
zGIbA7LS*CV{6wg16=jsdOtOHvkO`N~TnEKS*%f+3M9B_SU@oF%Td7JqMrM2n5-S_J
z6MaWyi57GT$^O^^y;HK?R`54drl;WBS()Ku_;g8T9t!nxStebwHM0G5jW^0pzk=PH
zvYk)Byd!I*?7&@_Dds9P?#c4I(Cm>-qg~g1S@k9i`+;mcmD)U%$u>fxR~EYv1_xz7
zeGV^P$?~2+(pjz!goulL6unnn<vTaQH8**93>0?BEx!ZiZn-`hqj#5o^%MF$<lnVJ
z(o^0O0kFOJ|7RUQz3^!UXn4!RX~E+oznTFP`{b!~&ib(Yo-;%O<%cez6(oN%3^2j+
zZRBr=T-Zx<DIdQBBuqX)>%$0~?Sy2cT=ol4qU4XL5IS1EaR)5K$ZI#jnOOPHbnN(u
zd|H(W%|y9l1!R)s8z{1tEU%n`&J_8-EYMELzo682s@(Wrj8(qr1ni!Xj|>G`y1a-s
zUm0>E?JG0o3n<-`CEwEwyV>$7bP43h=j;JkuKfFTVCKoE{{}}d$+;)6S0vw=O!1du
z`K~(1T$caO4WvX~PvQMi`5&~nD3iZc2hei4dNqE-3VG#w(7z&opCT?*@}0wBqFP>^
z3%9Sz58MZ{M!ql;ty;Oo8K~FEZD+yXdies%yIjNn6b<N3`RkN^>5`YdOZop>@`bd>
z?v{6_VKBGl?vz2lBd;|F_C5LPPodu<|K1mN@5|2|g~$VWKnR!*<x9#S*(-lUABlJ+
zFaH-zXGH;3G`T3;&O+T)(dY?iH^rJQ=-Z_@_de8jE7H8-p}XRd9VAU2ik!Q^_EbFh
z2+h5UI$DQ&DSXEP)LUWwJ6b-9WZL-#D+XA=geZE_&<a)DxdV|fMI7CR;ffs#(TY&$
z=}{P|SV9TUC`F40Jd9B+%mj3-;_v`|rXz~Ozr*}d#hyhl8)s6CABoO*MMW3p`Iw^3
z3yKK}_cX|yQyiEFjq{2@O1+gT7U#kJCPh^@n9T|etwshEo2y|r-t6~CpcR^ZvmRg<
z%%1vy*=V--GMLR~&pn}j+w2PiTzhDC?hN#vnx&-z?3tM<j>1l!=HX?~K<btf;Rnno
z9E14?bN9a?lVV;#bq6`-GOC3rG+!x!*=YU|oxOQzzBCY^?n)!&=np9UXn_!|yeNYg
z$x54SV4hKC@enCiZlNXUWhFBPdS0qeEWq5Sx@Fpgrmw1tLDNt5a2sF(RJkMJ@P5^I
zR2F?ub&M{(Ln=c*{0>&-?to;7YMB8dp{l?Rh=i+{aquZZ^^H9Y#;Bh7z~5NaDLwR#
zs9GqK9IvWYLjAbvvkmA=RPCjWWQuCDrwI<Hsz!f>&eN)yRQHpndi@|wq^pMBM_-1@
zg96-{DlOgOC8`QrkTO+$1q@cI;?2=ltx8CSi5is^EjsH|Uz^~?HPxXx0Bcmm(nZ>;
z+HnUWt`-(lLbc1nbOEhB7K_)>{pVp(^b@?<XEARxMExwTodh{xVR{$(hb-pY$CLzF
zY>tM(P>Z2Gv>e1AF?R?4Ui#Jxxcc>YD(YJ{Ku@;icShsiD_A-&vGVK-=zjCnyZHAi
z7t|BTzhyE3y1M5OEUcNi5>`!XM-0HFbpe#hTtC8qzc;KI0k!YAB#iX?I@-Ga_%Wpj
z9j|Z2Xt!OWsoOr$7Z5wNyYO$PB{Kl}cR4M#{+%}l|K9l}<=svBoA7TJrv3@kT$w3U
zWADZ^>7eMt)KtOQeau}GJ^p=}YgAd|#{>j{1TitAArs8_EdqK7Gl&qZJc+5=3a`?c
zyX`>BXT0+<s7uW2v<j|ZDzORvziB!2CjJq@?x=?8NcPWs;6<^IC`upAuHO$^G3=9S
zI2z9~)4@DuVn4VIz(n@KRoF~oOEb|*X1AK7^9+_+Xr-|=l%r2)zi|V}U~8#jG?xvh
z<CA&p&m&<XpKYQ@TOn(pP}K#tBoXQtS(hS6matD~kyXlOQRUecHk;m}RqTsAcwWt#
z`aA)8m7Qt{nQN^46SS_gtv+Zqu=lAfvxVI}0Mg2ip;bp4yXS4_-(+tUK);<GUI@G0
zY%N7XZ?p5M%JM!tCm+m5Y`Py5`q@X6;(yHkK^M#m_S|dGbLQ63gRM_F+vJIP>{p#c
zO6tD}9AuW!GxinJL<>D<HjV1|UDyw3pX|!+91dkSHsBPj?P7n91=-C$Qlf7U8%KqJ
z?(CW^m=6#3)BRBQWIg|T&9d#3m+@l1tOJ-g>plZEeb|PdVbZjZ-EbcUec9&*$ON%(
zKZLiz?7UQThOq6K=!?S|6qb&$?_5#+pO>PE_Q79&`xRuDS<%hAJcYK)D{83JX=UL9
z@V}Y*FI-r~v;yH<B?Tr{>nKycW_lLD);_2A@j4IF2)ML<38k$z>?j53ccGNc|K8;s
z6n^+O9{>KabSxl#{))aDvGI#(Fow@;gTK9oYRY#EyaE0$W-Xm&K;5A)czc)wpVOEa
zkB?!{kNJ{{?fn^p8V&_8(;T1>!uV4CbEt_aX~Fb`F(1*UHiC)&4cur(MP`mLMh!?j
zGqe}X<4n>g&`)HvRBBnlG?5RLOf(f@Tw(qxgQY5FIh8?IGt+-YtDY(O5b8IWhqR|^
zW3B~&+-B}D=<8>mQLV*u#`ME=$P6%VjRM*$=I5!vc44Qy4wwk`!@Xdpv4emAzip^^
z&kjyzGU4N(lf~@%32tRGPo4oVhxv+<o4JhTM36kDiM|Dt&t!%H=q&RO?XioQeb(^c
zGNZl#b!-6X+Ax(ek0{+$##9%ATh5p{gH$m46#tFxG6e;0GVf7zs-3Btk5&ic+6|Z<
zricP|_nA>N$4{9J^t6A*eAWOkSN8pMc;Uv5oCT3x>@qr9;=}q;De*qGkdi>YZ2LJ#
z2AbIOhd_ha_NkcMVD?cpNDTXoG6b=#18qf)u;XcEbCf+o_hAzIF+CoWS)P(+ne3fL
zIFrS;r@>M-8<7L`95#zK4;R=wR2h7cZ3u$GCANhEltt`yvUi33Wj&y)SW}k~8rAHq
zF&N=h_AlDl++fF-ptFfp#h|a5t))w~g}v|seXVRI?SyW#NE*|o=M&1@-(|ZgJamuU
zvlyg@T}E54`)utns6Sv=UBCoAWas@2g<kg2A^6nCuAs-yBlet$j)eEKn`xdOv+K9R
zw<oOnCOm!0PWTB!d&bVA)%0`rKnYqeSP!Z-eaQ~20onk2l`6r!xtL}s1apbB%!=Z6
z{fe=~b1~#h3b*_K$OW#A>Q}FEZ%|0&9yj(+FkNKBexpZYnCvC}cuBH~NpR+@><pDC
zRmgVEhWkyjKes}$PxjFkkQcJ#r2qE_sFeRq5%ueG2L*}A+o^h{1^;6zhJI82oVEp>
z@~K-Pa$A180!Dk}GFnFU$_Kn4`9xm!4SarXl3Tuk<}3Mt9HP4vv6F{jVE7}vM)elU
zyXgv8IlLa7t9F?KX0?IV)obn3(EGF7FBtGIy9E5b^{_MW9M{$0-`gJ3>5J`_lc0sm
znW|7+m>u*u@?=z#Fyg(;i+#`!VAh*90)IcVkYZpVOl>n-p-jZL=!|8SQWoS0v)BS=
zPclgqCr)IHBOsZ?XqTXs&P=-xXEK=g=}no*SnY>;7IX6@)U%m=eGtiEdMSpI%k-TF
zN*=R$J4EuC!U39TX5<A52o^An86f8vCrUM+XJ#yg-9kqF3G^>8J85Zmkx8IP-X$jX
zM~D<LsT5!?W|SX;TxRAE0V!cVq4K;^W(ZwGWz0vE%`Ingwt-o}d{zLxN=A1L%qz@F
zOSGz(Rkig0pIv8;_+#oCm>=ncQX^v_!O{(8DJ_$mnADr_qM3Os79w5DA|tSGF?VUR
z+Rf-G=69P}P0_(S%-G+6eV54*fO3yPo{}CCztL_!nGN|CU}^02NdU`W9jKlmi#11d
z-GsaKF2#G#vO||(X3w*_H5klAwvKlE#q9c0D3-GI6mYFzr*uN3n*DtP6t1(=Tp@Ck
zt#gBG&Rp{kR62n_B7y<<71_Z*LBiOa45)^)GYBYxt;vIMB)fb%oQz^u{YC4~Xx5F=
zlQFES2=2wQV_w0^5mt@29iBQxpTbHU`^^tfjAxHiebq5`7(Iv+*cMu+A7?L`LGlD1
zMUXtn#vO-bBD<~wtt7U>5|)zLC*EkKuqj*7cZv-dglp++{xZt{pJgjU08_v+6!I-*
zFYZ9+Wj3(}&Xlm3H=t3<&Ygidu3;-tA0n@1bM)w|W4#m6s%Jkr54{$)_7e=Wl})1)
z1Z`{)1#@n)ZQDTF*{gp+p@U7LQ?;FJ%5Tu?Vk3$f+W)anzJ`n4?73e7bDK3#YWWWP
znG$GsS@AqX@39JczV)!qXV7<_T^<ASgxy8U+o$Z9WAOJGJ1PK{p0lO)0DHlH-3#VR
zc2glF2iWgF1Q}#6_@ZwQ_r5)*%blA|pPDfFa!Pu5`El=3tT>RfmLL<v9d1G^irYuA
zooFs(9W)ZS{kAZ8oGYP)b1H|AG-A`hoxKUk9BzU;NG>;t!h#pL*;GY$k=ybPpf7Qr
z2O(L>&C`Qi;gTspRmB-A;8V4Ui=ZdzRc`)Obk=ZZCZn^K8|DYQb)3czmg>3bR9AV8
z`|=-%T<1>Df-?==Ulc2B<W_cq+~BHqgEVooX}Q+SRbPX83#Xvlx|Li1Cz$QrM#^e-
za64#E*~t~=!+aNKnn&B-+uU2UK)S;{eTvpyu8H11_qgs@==X5vZh<`H!j^*ca^<Ul
z-N)Uh#KHjg%oW3SmVHhYvM#c8Ixp!eTk$Q3o9sNLV|K~Phe2|;%$-u<9<s?6Fytva
zI1e-9En8&jf;T?00IKEPCmTUmpsy@=D=hiRJT{^4n5>UNv#GLyOlaiDZf8KUP<Ag4
zBBipONnqZQP1r%dFFrpEFFX{7X=c0?o;^_Cr+7ODB8L>u8UY=wa7YF-L=ohMR;c2$
zt(1QaQ#d7nge#_Y0yI+5X#<C&71t@26|4B!0-#3~U%dkJnBr?UFcTERtpIvlafw2t
zClr0n&^xIZa~{J^QuxuPBUzEs0Ft7Z_4of<Sqo8XAiUh0D*aaMSHR#(gObiaeKT%3
zykFH#8P;z-XF_PTX%7DW;oN;7{CJ#Vvp*&Oj(`6g&<2?;RqsLm&tNLZ*lJC`l;iP(
z_<P&Yn;6vgxiqxD1xjk}Vv6Z%-pzE-62ON!{|(Iub3zFeUq%rLV)A36Tj9Mw^P@XZ
zgP4&N<_c!o=nfBIPFw;BWroo;9>#pr3Fu^IY!0lYGX__n<ub=;1$~~mwh^S5si6H=
z1(P`v(^SJ~Ps7Is=C?U$wJ`&fRlLLOYzOl(b3+bHXA`?_EDZXy<G%u06g$uT|1UV%
zX$OWM^EW*q{h8jkp&P^;yAIu8X6=V?IfQvK4kVPxm;{@#O!_!T9${Lyft+Nr{o#2c
z^L`u@l9&_px=v<hu0>x4(=rFGOeSdweSaW}5pRNfo|#V>(L!eT9gMD&`G?*ZWz2Ni
zmDDmp6lkksDklT2nTbn4tA#o8J501PbCNKCHs+VlfO4EYK%WRX!Cvd4OM*?FhLI<-
zXXwG6#D>$pB$;)jZ%n1I0}2q+DYghpIXq~+5}?t{R{swMBe?9TAd#Ha2J}U7HF&Gy
zF%-nYZVZ?CHfAoCJ3?nfj&M<LK<_Abk4}ijaW<PE63-3$03$rcUHuo%Byf)@vh6Ed
zJ_3DyG6iiJ{bdy*ECiTjUv0ra_shQB3;hGKcd)*aAC%3eNAe-rciCtimNioKa-eK(
zI7EVEujm`^!LnOlz;1{vl~x(M6_xX8^ol<=!)~Htoer&3MK7(;(-a}}-{EB_X3+;>
zaugF&Ad;u}n082K6{c)@IGs~?+d%ZOV&(yedYc8t!2Ag_R|(8ZX7keiKi=*FK8ovI
z{Qs<Hvk4@G5S-u+3GQyeNpK4m+=CZbv^W$!P~1v!?-VIopg^$#rMN>W#ftmync2_w
zTfX=AzxQ|V|8>c$^gZVp-7|A`XP%uoE2Sf@^L=D1&bmsM;0*AdHMemO$OCK1jj~-&
zto@BI%b#0c7@3LJ*2DQ^>M^!jXKk`N`7ikl<961H%f6KwsSyw^!!`TMvmjnatuw~=
z6}7+ZAamFGW~Ee0-NU_Po9d;GknN4VvP@=fmae8Ow0ZyMGPXr4<2$~VZ;Wr=;`c6=
zc&pyV6K1U^)RwtAr_3Y6T_TJx_Y>zdl<n`cZ-GoRc%X3(IwWf`nQOFVUbu|@((-!0
z@%_gb%Y?HM9c$S>P8esIYkZlr#xiHS%&^6hXP3;q-BR@@S?M0j#qu)lpyl*z3I1%U
z6)5~-xn|VQZ<g=N%JyEd%sDTm+ZLxwN`G1km6lif+_Gc8%=g|hAxOrJwBF4w^Nq9C
zZYi(dS2<^lhn*{b2$h<sQq{P=>?@zG@)>KH)l;_Om8D8{S<G9@cg1C)?<~iSyMsPj
z-WpHz46{0_N^qogM>3gml=aX7S<)Em@qx0YvDTXxWRmID{%d5xGpx6bQ}wmhuUkv$
z2W$2la;oh$_RR_Fuo)8i&3f9n|M|T2>J?ey1?v`%)W=0@qlPlqCF`twGVYFbTPd0H
zuC-Q9Dg9yH|Fdk@eQSbwGlTW4aq;}fy5gN|!fR`>8nWm&*2zW=cDyb4l`z>h`8!$k
zG~0<D@)~E@f=7B~6*F!5O7JEfzQH)#dTL2)^uO`UGSN8ceQqf?Sl0Q%viB=l?n}$6
zGQum%h9VLiX`Rr@eA&nQ${w9)eN;%6JIVUTZ?fu{)^<B(_F2|V#+8$@RyTqRt#^!X
zn-*DL8)vJFt=>gOMJ=(mG?KcjtVxT=>Q`IWM#&s&tY6NNZQf#i_e$2Z)tc5g6aK+E
z!1z{hmo@22S<^x5s%Ns8L)M3hQb#AOLyd2SPFfon-_TsJ_B1|tFIv^Fvan0mcq8|I
z*?Pt3ndFK!$8s5W)q2)jPiDMkU2WWfdEM$VvT`@94O0j=t#JwR(*CmMZ7HjNYMs7Y
zcxF9qoP<2L9-l4qy|7LQm*6Ywc%%QQH`d2}<)yu~_PHUYk+uw_WMf9zLNmxDi)>Lw
zer>f)`b?GU4_nVdGVYvh`%|O-uiC2ImT4Z?o*N0!=eDPHW#oI?S3k+5qwT|t@2-{o
zemPm_YJ2W#Qrcy|Zk*ShuxGw4n|;$Bxmc!rX+Iny3!5NaO30Km9nEh^X|ChWB-y4V
zj&F>6kiV5*i<96yXLciLvcPGzn$JHv!;IYhB4@&DshX9}o5mMntDV6{x_phZk@4QQ
z&gnL8+u!KCby`Z_Ir}t{t<arcww4*TIWvxxt=Qol8zD37bbggnHf@)4!!23i9;ekf
z4c_alV?5Wo-+4H>%>JXZSBT7az}ZE<%=9`AJBRI%IgUA>Rg>*L?o824Hs*x0qVe?T
zX=mI#-tDT6Fiz5|l`}5QW1@4&G}VjSWT7?k*Of@k;Bm4IwX!9X;o7_8+g(SU%YVw)
zx_OVtT=g2PmF<l^`(9QMSN?^(_WI$uWStEHavQnohIdEHW;LpBe9hf>@JN}o$$*ox
zh^AMK^ZRCP+RLJw@4h8tTc$C-i;jO}m({dNdQT#)TRxRYo16n>%C?z}E`!>oHEtP6
zkZ(-n6ego_9?;?TLK*Hj!T2J&(;K%;+4*ik8Se7a)WBwPLqiJVA+c^1rpbuz>1N6d
zJ%WrI#ClG;A=T7t!A04W-bWwHaN^4B67OHLjtqbCz46S^a7)Ju@<PU1iWiY(?6FuS
zE27<(w=SC&;ZozCSTd-Xr<U?6?^8?m(iLmP#l+>0>E5<$-*yRF#S+cq>dSw%3Kpo?
zw@pG!rONTq`J$upMSl`&-m`1p4xPFuHdoi4SSn}j->G}S0>*UtqVg4pDo`-0aDjr+
zg`<iz@6)44*Tm*+I(5&VFQ3Z)%#tnt|L*eBd-COzRr&r?mZz2!QUA-Y=s&D6LN))(
z67acSXEv4mxuu{tu}`;x1=<%HFd)8T>#q4aYI4@tt#zmFG9;h(pNx!e+oOB?|69Cw
z+qS+LKb^c?f-$u$@9(e_?SB`eiVhf%ucOz9wC&M5A--+5LNZ=H#S;6p>(srE49g+-
z_pls^@v^|yeY^IF?=!GxLZXZh(6sgmt^4%tZI&cy5Z^taf7ecJ;`=4^PVCgfcn!vE
zvarOyJ*8kw@%I9y(6(D*r?QFvm|9kD#1iF|cI(-xYeH|C>F-zv^HoZ*ThG4nt$TOt
zSJW7*=Dx5LRi~a?lDpy)<n?G)_27jiBJDq4wo$Y39eQ@^;h!S%r6nTef0&|Ox7OzT
zbzWLh75WcjrH=aeR`7QX`u16T+t$V_l^N9am%-t7|4^8l)%iw*sbeoKp8vSkp8bti
zX;qJ9t-1fhTKl%{ZS09p;+>3$O%-}&Ii(i2c82Q(UR%Dks9(l8@~fwfUCDI&TT6^Z
zeUr+XRh9qKkwTyP&NAPl(sp+hRIUa=A$nqfb!b39Z2gMy6>8Kiq)rWSM5rFw?Jm7$
zsI_T;dbZz@Uq714nmMhydeQ1o%Zl4l=?@EA;~ka;>d9hfm_DGSHN8dsp2?F>b=@Bv
zpx-QIEpJsn=MG4vmn&=C>{g*`T@iYj80#^&-XhML)}`tW2uiQ&mbPY5lgkB!s6m%)
zp=v|xAcwxOskKaq`lG)sNVPofNurnUVx1VMo-FgES07JFN9{NJS|dDq#Bl2wiyk`C
z+S97f8*S|o?23=CA5$wjN?m_tjZh(OmtB=j=XR=~Zk_<$Gu_%ah2CqWwX9Qxj}6YG
zo}_bzsj?wKZvE%=*7OdwXlQVt3Xika&>w8ErcSLA``E%%+wQJxy61#-gIl#P;Ym8{
zXpl=?8x-hL@25M{svhl}S=5L79+zI~ytTAV)hcOCsoq=*^33WRXjg;cY=QdpOV*1{
z<*4FHqj#2MS~8VyR$zq6J1a1qI=jObq7q(M7wHi%ttl+(${KfiRsNMVOfUD!S~XNP
zuj-D}C%SEWoGN61&7ltuvB~_WK6p~8vrB@*l=VAja=m9}+tOe)W{y2XWvgS$s<I|}
zLiE^ZTdjaJl^fTOiI1rjEB~U4MgCo?6&qbl?JRDK)615yown)K%h*nZs50%`fqK(A
zwna8|u9hQO{}^lgBeQzeCon|+(9ibJrOG4(rqx|uo7bVL7Yj<KZyIGgoWv5Zyem8r
zDoWWrYM2b^<EGmJgVnAGPg?!!MK+5~)p+6#%uyi9xBj}Z@pWShM8(%i?4rdKs2E={
zwm^K%@^SU!>-I>D%n@Bc|8c2pOs1HMCGs~&l(&ogZCm&5+CP7#gv2g=di2cSr$^pC
z9TW0)>(Qfo{{B6BcS)3As!xz<y65eakk}_trfbu;gJvAU<!i>)Djypkryfsqr_yI1
zw4Ji4T}N#xl_ObDh)VBpxb+1`Y>^h#JuIk*{_9cOWQTfE&00uZ3lDJUU!Agr+tkd7
z&YJoUXKYmh)zsWUX;rtxAh&8!*%RulSiW|Al>*AL&l#bYyJ{=%aK^{S)r~2vqElHT
z^cA;k)9retd$tLYs`nd5xXMz(mc}<vK{Y(RE4A8F!sXQS1lsr6RpXAfV3nnqGqe6M
ziM>X!-XyI(vs+oly7H^7rGt~I2hpA^YQ<Jhs5&_)$gW?@YF}<ugX#t5Rvr3VL)D`d
z9+#S*!+t?F+!`JfH6S{wfo5)ALG{GyPNOD%6%eYg%xQlcq+cy!ZyT(79`K}8%?@}9
z=#47bpJY>2Q+Sf8+iyHs^lDw~`ID+5GvuILSk>WBMdrBDs3$Y5$@T4n?9bi$o>BI8
zb~UY^v6IKyFF2&NRjnISC&ql$>e;x!<Z8$idtnvYEI5b0e~SGpn~FRZoK3ZwZZEB-
z&9vur#K%{uRnb>Tzf8C9v8etDu3&Yxe?S)X{EanKKRMH$JV5R3WlyeJzq6!Pv(|Z%
zsOC*%XT6<ocV<*=&&Yd_Ww$+}T`#%cp4y^1TnS3APy5l{B0_aKVoR$YU9>M%mM1}_
zRL|B@TdOYFU$|77V*!!+@muy28C8W-uJrnRr{imn+O*UbuGdZGNb6A9huV{<^tqiL
zm1IO<K7De8d{?6?q;%)jE2MQSO{xxe3`py$5?4#!85^mPw2pMTJC9>;NSe4xF?Hf&
zD#pgwZ``1ErOL6f6@7<sp$0ki!=<ECc70-XM-7__4sm7B18Ph6+iKT^pj3LA7LHco
zYEEy*MKw69J(K=zqN9T)dEG{_(j4L&)`_Dr7>h~LS9(2Esa84jE6aHKX#uklSE(N-
z>zq~Fc#kXPbg5ulP=Knk*%6|4wy_52r^Y+Vg{Zv&o@l-CTt`!v{?ihNJDF-zE-1O4
zW~=<Nh911z5pPi&=D1R+wR2qQ^qza<LPn+R9T=qN|IxThwN-UT9#tlr+og&gl*KyJ
z1&6B)V;oMs^g&0~Bx+d^dr5uj8R-jK|KgUThDSwrmcxA8b2(l%_OXVk`;Q!b)%Ib*
zS@c$q9Xpe#flaNM^r{~nuciB>QL@JuJaz^I_*#6S25Pj!IbLmgEAw^y(Vk0B>U5q>
zslMp#NUxS<u!rcO8Jru#RIC2-7H%u(Ozu!!BOIB0&8hILDz*r{T`^~bRs9v<Nv=HY
z15)c>lyJsceG?Q@rxrNUsFRh0ovNI}9q{+A4p0k%f<pDM($2n4b@SJtWcu=o&ILB*
zJ{siFhg5a$3)kDXaF$Bpn<38tXJP$pqBF*><{fr=^sWP(kL+saPeC4a=aef##g>&u
zGG&O<nN+_%(K*7Ycbe|ZW>Hl>$j4ii7V^&ADrJCEKR?5H!>a$ToCA~UBUd<QS=BI`
zExAfE-0Ie=t#XFgRgRI4q$=+KXMmcJC`VbJb<R53)V&_AJo=$C&Nrd@!#mFDDb#|j
z_Pk2nwuk96-aGr)Q<kq(F}`{wc_Xb}seJwNzJn*KK~7D1o$?W#(dxQl*X=IXO1ml)
zB_9~~Jg(e!RWQW$y-NGhky~XcYEP!84|Pq<q$*aG<1B^MmPD<6>Ts*Ai`+?#p<wl>
zpzA|uAz4M03I&S!)=;2W13jX!>yHpsbbC;k%34M~dm5h!4$|{faivJ9_iX999H`2+
zaAsGBl6XQ?-%hRvs_j%)sM_UmMfmnkA!Yd>ZyHNFyHfZ*K%$b$dr#iQHkZDwv#YI5
zWg1{lp)c(2sxC+52)9EW-XJx;?v0$Rg!gof4O5G!$U*aRXkaRR{z%s)t3LEg*GP-G
zKE2#nSFlx0$}Fc93&*>hYUF`{4Emz+uHi{ky*aK5>g_B~pvrgK>QY}#akx~@;(_7n
z+Hu((yQerjdWx@It0QMkl<g|D&K97Coej#O9v=vBx=WXijIA73xqeRlz;@Rgn@8UD
zrO`&mSE^D)T}>{hH_vyuY9&i$yf4PrsT3>!ibnpkpqia>4b$JBa-Fv8zyInAPp2w0
zbB4KmZJ~(%=BaCyMcw;O4#KO?T}cAfU}xa`t&V_(Zk4`(yoy>EJVEO6#DJ7~Gj~9r
zK>c}GKu??MKggb6&1e=BGHa>ZuB(WE+@WS`cNg;QD%n$eas&j~RI!@wAk|8Gm{KR#
z2HREaEk{oMcJ6>ci;C^!3R5+2T0Q#nJOO=dYVRFqUe&mVHCR2~<aFsXqXP7#`hs!+
zO|piYpDu;vHCL&?@{KpDEbRm2gQ?jNXQY0+W558H>bNW@T5r)apo`1*HlBV!fGlG`
zz&4jEmnd(&Z@dAW1J#m5XF>IHh$EFgcYHvURoSlEGU_iT1{BMvo=*tQsb-A|4AbM+
z1w<uLJs;Was^>=8?sTQ?N%eg@1Db^BC65K1OQ&bLA5cD6ZI~MnrZUvFIh=APAq_x%
zh;yXWr@aao6Qp{t2rQ^qbGRE@BI-1Zjj!CWa_#z&M#K5Lq%U;3ce_-^sdB#1GKqVh
zLoJ?e57%FWxzkxxn{&2gddYCN%cgfr>HZk3mR1c4)8}V%k4UNaD(k*4ugM`z>#M5n
zN!e8G5L-U=aFsPc1@)6Rt-;;hnVkN&qw@2eY1FlI^6~$mkGo;GUVFUzv{P+55|CVN
zxn)nSmze6_C(W(1wV0~=lblvYFLWQU>&ce6e-6;!t#RK<tL_|j?^Az_ux8VD9&v}*
z)C^l-8vV&JcXTFqym0{(A0HX5XMF5_6QpN*@9ykWJC!q!zTOsi%&Mny1wOaw**t;c
zJZi+$;7t1Z6oKp9>h8$koO+AMz(G#+i^UrDufs-#9+1PLXI1%7d7Le9d@fa?rJR?9
zoVLpQU^c5;MZOAj=-<~1{AiQ&z$Xm?!&Lf9E{{6VSz7Sx27#56x~i4087~Kn$`=+C
zp|?s1d~BDkG=i}eE2?^<U4`_zodXv-RGsmzwEBY{ftLfrs>M}~Z&<!&gUXQw3P+iL
z4fH#M0zcSX=8+d&P;K~8KI)_1OA0tjg?^Amm(d$|#;VFc_oP-Mezqr5CpSquh#e95
zrAws?aHZ5E#|MtLs3e}il=`L#f$aiA<Kt_^#8r%M7!wy$p=RaCXicsE(G#x6&k76+
zO(N%V_2OeH#MGCnjM7xbB<=`(=Ze4<F1_e_S&sh4hQOxj)Q@9bA@WLt3+ls<2g)bQ
z-P*y$)tJ(@B>L=M178NK4jwtNJAcfbQXhXSaBYBI^FiR6l*;4utW$aRdZN@RrzeGe
z!s+?TqKc=rN2<{~0>gEe+q282_7!jzSLcE}C)MMk9=pCf*z?h?Ux@G|@u<BU0&}Vr
zG4c+*u$5CT3l;@B^&FW!NA0T0Xs28;9F)()r`bK1Y=Kh2#_5FArdqJooyJ}{wo(&S
z{(^i+ew<--s#&F-;i~(I;DGP)c&<3~&;p*WNmQ*Ha#gbHXL&W{y1Vn}v&(rF+4b&~
zJ-brtrCNEu4Km+V)W;C{2v25}%fsB=JY`kLyr4jRM>o&80QDrqT3BD%&y&leLgzZF
z>ZgZ$ltu43((^90%2!AZkE9Fbl(bTWJ&nF%fv370_)FwMH0g3rUHL35FPBc;&$=_K
zwKl6uzqrCPH$rt?;EB}x?e^@nsF^dI`OLF(wWqwas!n@77i{{Z1D^I4M_jyIN+?Sg
zcMcUh&R$gi>!7E5gu1ysFjSQdu*ylu70-<ndh_R=ycT`?3(q}^zW0?UnbkOHk7-(2
zEe^4T>F&3lF?RjLM^6fy>Xyx&P7k*Q^|GmUE1VgWwZ6O&Y<3293{WS+0<!6)lLkfG
z^<`l}<x-`pTdhfaqu7}GmE-HziHsUx9IsX6uYsnL<dsAIZJwYy9(8JqqloG;ASh6!
zwK{_Jp~ZsA<<U>I3o4Rd51SFRA=r2a4Asvs4w_;uVC*+J^eV>1)r_kgNl6AJpqcx$
zO4Zo-S{3U=^D!LVKv&CxdM8tj*U1IxuF0+xdImk{nnUeL=62|jKLmAis6U6=(x?H~
z<z%|YK(|w0y)P&%rGD;0&<vXzKgyOvAAKcga57clcY8{`!IPjEw;JILN~3Ro6Ex9g
zH_kX!uS|}#&Wce{4Ql4p+kObDD%aw>9BI|*@$!Kg*~{wCZv+G%mTT7ua#HeV_TZ&X
zRrz>eDYZI#Z~^^zzTm8B)yZF7DOGH5kDO}M2tI66ol*uRSIa(na_f<Gg8%gB#hV3x
znbf@6P$zz~W>adTe6;WB<8iB~lnyyvxhkoFBIo3cx79Ft1$Dawrwmkgo(CjVIo1az
zRTtY?lj_6z2AA-t1%2E(^ee-H-8L05%^9q6Bn?WvB7Bs5Y+Onw*QhgIcyg=373_g}
zm9fF=Z0aX(Ksr7B#Nc)gb;4~gDwik~V=JnSQBq+}Z$OxSZffu#yWVV8@NAFDwBMde
z1uO~PY+T61)lwUe2SupJpIvf7y)^ij5ViS{Q5_%TbI!RXI8O>yGPx^IrF$0;sQQg{
zhpJW!94XZhhci$wa3r{lMeVC)Pv$m1`3uOWmF_(nyx5|Kw{V2(&5i|o9P$nzXTRfq
z2~HN4s&I7iywSxAMdyr+j?PywUv#7-XA49XmFwm2ZU;Lp`fqoFw^-Dg--FXj+Uw}=
z!THso`@tb9@Sgnd&F{e>dairHb*<h>nmjf1k3Wkh_v8KJ&#Fl`1poN6X{-NH(j+N(
z{gbjoOD$h4{p-)E)%v9D(xkJBfBktSH~9TO1CslbU%mRrU!W$vo&Dp_qs4tv4${8-
zq#Uem|D>Emd-zE?sV0wb{QW0i283u${t?i$P)#07`o~`~?eHh%FzwAJ<>Xos$&CK%
zFI<!U5dQI(LfiC7IYN8%ud=LPOR43TWaYp9Qfb{jDW}#}eNs-N$%ASC_)Dv0HogP+
z`!Ag)k3{_AFTEx=uKeRKgLdifaw8)isil+j>%aaoYRx|>XVPYWQqHWM`=p#jOD-AS
zfBj|E>Z!{Qg42ag{8vndY}ypv^Dwxz)hkbDXvR)9HY1sqOPl#gIk&drlX4zy+b89`
z+L2Gn`LxTFlbFlPuig8k9Hq&#k>>h*<D-*l@{Noc2r_3VprulIpGf*I_DOKX$l`^H
z7cLT&P_Rhx=t6DVw=Pz!SVDBsf>F`YZQ8XfS}382zV%7)difUHIQBIyaGqwQw>4`@
zO$#<mXS^hzDKNF6{4bMXT20GlD7UlaWxRYdXwFv>D_{)DmxJbbV`mx5Zz+0>0r^7J
z3?$+J9EM{I!!>OhWo0PseF^0ihM}6aiL!2(RMYlRK4d7bO1>sD*K^KL?u@>nX$8%|
zT_YfM`4<zsG<3;7*}KLD$~W?wJkw?FXnCVv^**?|diOrKn%sjaBcv+Ks!OkF$ytER
zW6qe>FoUM$r(6un8AfWFSv46oEsl6Rc0{=;!(7fl!%R|LhM6^Ov|$!0%FU>nRn}rw
ziR_U1Mmf8tEi;s@SZkO=(>5FC)U+RnA27_NX+In0*0i&Rc{J@Z<A2A8hO&d78RnCJ
zMoq}8@fb$Q=7bsp(VF>oX)Pd)&?pzwG<hgkv&s=6Ul(dtxwBmEKhUg2G_9gxQO$fi
zwMuo!_p#=N%8h55Rc_(!U?}h1y$t0@GH$}M%J<Qu3`=XqUHazqGY!3EG;N_VP*&6A
zIYP}^PSe&Ime<U;V`~LX+hdfaCgd(-&00~@PEmFkuSnu@9GJ@SV;X@n$}CH5n@Z)G
z`gf(gCg0KPKip-V<^)x-7W(&X6UzR5oItq?`uBBz%0qA@j>9Q9(>NTAS1^~rVqAgd
zzL)Xlz8AL<-;L%mAn~J=PvJSdj5qNfKEmh5;b?5YTLKoU)@&{k52h^lRGZVK!VD<)
zZ<}#>gvc}+i(+Xsj~Q8B4COl5z{@~0Y>nnYBs0jZcjkf<aUlBV8%<g6D>tW`iVElB
zQe260-<UbQSDwf-2X^3IJcP&aG@i$+D0ljr^WVoO_!8w_Ky$p@q-iR*)|w{u>DA<R
zC^KN3To}6|Bg$PrW;rj)U2tYudcrrAJAO^&)+*B)C{OX4<wn>7+hQl|VJiE-F9CVr
z(428Nj=@Pd9p~UeT#l=8BkK4A?#IJ;!q6+P_$+~ocpdNJ1AL0oyN0=;A5nTyG0Ps5
z+u6)=1j_SDW;rwF#QdW9=~bA3Jb+_PC^veU%2R}<wJ;8i(==mO#bW|?!Cu%Ohu}yY
zhg0MkcymEB3CJVgW_dBnjkacaEpEnbxEl}PQ9Om`@G{=Sd-zEDKrvVFoWNU@=akI2
zbg*G6y)>GJVJggkSur<8V^Ng;1kCy6W<ApwtRwdTn}G%>JrbJb)+l`}nB{ILcUqcd
zdECL&KmTaTaub^wpNb0S<5FCSUU|~eoI!3}GTniD@es;0Ugr4Icpk6fZM=_9@FmLq
zKj!>4`P4Fw9eHri(5uNkt7bs%<}#HIyG%1;c9fny&3HkS+hNUeS(KZd%yJE^hmBAk
zjyA`)#ZIQO|9cSVi(lYy9D|c^I?lm`xE$pX2y;anQO6%}KOQzT+W!dxXYnFl$Gi9d
zpW<u$i1HMXxnk*f(^PIHH;q8)>%lA=7b(Ur$SIobKR*GvtH~T8H}{&#gCeF?u@=T*
z6O6|M?1J(nnmK=e9D*ZJp8xc<e|a{-oNy-2#l^S+*WzZ}hVnqJIsXAXil^`#UdEev
zPws&?XM9B9Ile`UaSAO}C0#U_N<SN>VJLTKn`P;2!Za)9#%L^x(%p?YT}6zMdl1cl
z+>U430Of9Zvn&rAnM%)mrrj_R2cmyDqbX0osi<&1%5!z*^1O1>u{p3Fx8e@mi-%C2
zk29w~jpy+y%B{)fc;iMmqvoFAOMH(ux!^F{zuPyUCB<+|gBelo8#Wi17v(_&vn)?&
zn937lrj@Y<*26~F0^6F({_jMf2lmA;a5#>^NjM$lMp<*k3voHF#*L`s54hjZX#a-^
z$U`~ig3jVaypDJA0m|L)=Jc=eBRbr^xCiAKS93bKG2S#CW){u%pOZj-lm~gt2}`0p
zf^L?pVl9lrCK!(iC=YCz^T{pkrt)x}sq~g%I?}iY+&D<&IdoI$HOO=(N?#jhc`>fQ
zwYVAO!FhAK-6;2go8_Z;3eVwXyy>R>-y<O1E|@bu$G2#aJ4(&>0hA}^&2kt@-vwql
z17^kC7>)7(ra4_{tSHZ*nt>RsgAK45%0po0bRDo8CgMQ!FHi2OHK(6|Q&Hi3^e$yU
zK10kI{{LJ|8a4Fayq5H8@vOK#cEdjS1&+XRC=X7W8?0~vF2^<KzjoYCc`yECD*OKg
z0eNiBT;OHAh4;~)T6s-b<I2W=t(b&zIHtwSXyy~7hWyuv#f-So{>w5!6*Tg+Mpa7R
z0;c|J!#0#Vp>$Maj_;2{(SJ=Sk6oJMr{mYS7>#^`+5Y_(gYtZWIl~VqPsN+%qbPUi
zn`Qqs;5Ev3@gYiYDdu$V(0}b0$OTI%%B_{Y_Md@(JS1e!=)dMO?&&lSDy)DpSQq`*
zdeS+ZIeh}k1KDOd5v6-jv+Tdb8!OKMn}I2en1%n-*6`n*FPE&}+<^br8UKB{WXzum
zBQZNl!pmH~k?S#PQu0uy713LrfqK{&|EJCJ-#75TNJ@FNoUAYki=rgP%q^{qHSxc>
zg1-}&{u=o74NB_2DhvJ$*)H=1&0~E_4UP7{ioizv9(UtGJceiRBHqBq_!2+he^z5=
z`<HDnw=6UIcga5!h5v*1_P^iS6aK$9#Mk~KnBc$K5Xrup8(JDGVGWE$f1<J#<qp^#
z`{H1E|1lRhlE8SJinDPceuMtR<QB?1a33DVlXwoV;BEX<)^BdWQ+$K|L}UPOp-EAm
zjxwiDhgr~{fGj|{IF`ezSQ{IlSDvUg7uXg%V=o+l{)D6PrJ->wOhV~l!z|CmCFoBy
zZlJ8=E<E7VtI6Y~<^uc)#tW4Hv!mA7fd6W||5*CZr<3~kPx!xm^mk#`_QrvRM*AN|
zU<^)1NspT~^T`{AO#eT9zmRKMb9up-Tr}H%8UmTn-~Rt!-;({`4>V=|*4PnyU_Ts!
zqh$T&7EK^94d>t@T!HIwEAGVocmz-3Z+I2&-~)W-Z~t!z_`fc5a}b7L1g6KVm<J1@
z@hqotaF$1TV$dx6^ZgAex4?G(X4Qp2Z}jK+hfyAblW``_Lw|mM73Ga+e5G$}&~7xp
zLz1#Tt?xa<h>Lgw@8M(g=kq^Mc5tQ?gkhK({b~Fhl=Gu>gJ^D$JR5B2)hZG2=kH@F
zH^Ele0j1L#a{>Oey*xc?mPg`vl>S-FxO8D)>QC2yLwT*KwEryxcHlnr=jl&UK8IKE
zHvWnJ^!yvj7MpLy(wU^W0ZCCFEH}$$THa{?Mt3pBKFW>KCB0cLj^)swj+ZX8&G8Me
zIkv^l=ug8-pDO0`#&^BOdcMR-qS^ju5b&qpmr!1b8&Jnx=uf*#-(}{4rQ<u(3wRx+
z4-Yf`2w&iPfBxTY_f6nId7Rsv!JlT2q%4nMnsIp?+q5v2LVtR_I^}vO-K&_>$76f!
zCcnXEj*uRLO}{|tS;Q=lL+Q=VEc?^x(i?$UUXE*UGs^Sx=6HV={U^%uAif#@6)*eq
z_qPc6)8~ItevQV*ow4s+D1CsKWq;OOI^;0RnK2heV=?q+%d1fK)?%POO3zg0g4&=j
zO|EIu-LV<(k3(@Z$`1;g<New3uPHA^>HEMOzaGEy>DByc@gEs+6o0|<cn$s8aHBU$
zqeh<NJG9BioDr8Ex=j69aOvjDEN8%Mrn3K~i%N4uA@pazrKdnM9)r?Dlv!?s(lw}A
z_Gi7N0|2v}h(<4I#)b?>=@!#0`;*<XjIz=G=QBcnY|xxwHEu$GmU|E7LwFp|qH!~k
zu|j`#`wz-bQ2N&~$4hTArqa!wul@V8+R~q!IU)^a!kid|{%m#`%9XJu#-a4yWiHR3
z#O_GB2TG5tzR&+51f=^za|VC*T7L1vEYHD3xB}OqKWQy}9+=bb$0I0RDVXu!(4VZn
z<D&gPV8k;tdY~|>(n?CzpQH|<EFFoO<I|(`!)TWCpg%b+y(ydV@>mV)U_&nh{;YI6
z%F>OUIivJEXF3pvp+6ZtnX+-?ma)O}a4AY}8D`v{g#MoLZuA~x;226*3FZv`<g@$|
zx>>%5kMSjbK!4IX$nBdx4CS|V%=t574kXv?)rt@(jne6|IYSMMMSqf6y3sMmcR=a;
z$1F?#52k}rlFMdUI)*o$inDQ{sqFu62>6rATPW{9>8sIPz+seL(9E(wnS6!vZTu6T
z;v4kmkOKmJ^CvYl+Q0njmbpOb2G=wT`jf{6C>KZR*T<YrdNwkZU;Q%m=Zu?EZj16`
zq~`cuH~@`YvHAJ`B?0OA)tqn!&c!9T5;vfZyYK+YFEN|Tkq#?NFW`0j9UsYWV3`xV
zAn+dT9^Z@}OopjYI+rx(li%_-m7iWREsUj5ezd`iS4Zh^#4I<)c=-(?Gti!Z^!sO)
z``{Ni0_CTk%<<AUnyJDCxE$BuX55Z@QF_!d=RYBRu$u$&Q`DxHQTjPD%lGjwe2rR=
zZ@deWU^u45%$N(Ku^4*GGEfC;VSQ|dZLkye#Qr!GN8?1Cj$h+q{MM&eTTkFS`~iQ&
zqxcJ+$7^^OAL4U-hc>y~HQpHmF%(mp%KpzlARFezLRb<jU<}s9M%WS)uq!6wARLZk
z4UP6cg}^MFkIQg1Zo+N22M^(KJd2m`CjNm>@Rew`|BnQmNqkimjL9(#X2P5pg+;Lp
zR>qnbhfT3Hc1%M1??Ip+4#8140jJ>{T!brd9d5;)xF3(;Df}%7?f)u)JNN*f;afEB
z$u$lpH-=yYrpK(92Mb~eERWT^4AjAf*aF*O7wnA#aTt!l$v6||;Zj_M8`1kc1H17c
z9>X(u5pUo<e2g#g13E%{H5G(mm>M(s^lCW>$mzRTwekjM`d@r;@b~uy`I-Lzp5Onk
z()+Ui<5@rgcEMiQABW&b9EVfTpRSurc`>fQwdnssa+^^$+W&4w9KfUK&tmzL$CruU
z#C!M{U*g|+e^NC;7>34kA;v*0mjRsrGoz6ZG)8>Jd?4rltaubo!2kVxAnpGFD}08Z
zEg$I5|NWg1WZ!(Qe4zK=6M~;PA1LSlq{~PMe&&3j?Eg;_f}c4bXrBL*4l@&i()>PW
zKG1jm&juI?L8JYD#(W^>|EyRNg60N%zI-6<|6d6~-v)fPe4s!7_jf{&eBbBF2YUZK
zA^4f|fpY#&-j0OeXU+%8{{J)~_?h#8=J`MQI5QzA&F^#O1AXWJ|40ZL?f*081AXoP
z9|=LT{eQlEAnpHO2|-``|7`g{fBx_9gdpj(&y^4K{(D03Gv@>4{Garg|K`)rn-7%z
z|7k+-Gv@=1_WwyjP|BY(A85A!e<lQt_Wv34fxh<tkA$Gv{y$$nkoNztgrKkef3|#}
zKmYf4LQpP$ja~4$@`2uePY8bIe4tnRw}jwl&Iii=|1=@^ne%~0`~M^%DCN(Y4>a5V
zKNEt+!S@;Sfxh<tkA$Fk^nbp5AnpHO2|-`;`)v6@fBx_9gdpj&&y^4K{(D03Gv@=n
z+P@_P|IP>ICofn8OJgOhfw9;GTVV(6j(u@3jx?41Kc2u;oQ(_d8(fQ9a0l+g!*~+U
z;T61%f8tX^qy4`jV3Cxk(fk51DW<@5m<4lV0W6N?uqxKZ2G|_iie~%oOrRGIKreoY
zlW+#k#U;2BH=vHY@Bsddr$fpAUm$QDf5%7o0^g%OnXjfim<&^4Bxc8aSQtxT#bmVq
z>ICXxV~of4*bV#O7dQgP;a8||0WQZixY^6VcHE0U;R*Z|FXJt|kALB7G&&P9jwKf+
z!Ej8A-pmZ-!e}gpWw8p@!ur?@+h8Z`iT!aXj>d^Tz1nmFU*lr@7T4o<_yhikNAVXt
zkJs=nKE&tv&Q$ilP14>*RRv-wro;@G4fA3lEQu8`2J2!YY>5fj)zE1Fi3A4Wa2$(M
za2C$TWw;tQ;WpfZhwwO_#Y>{u{%;ca1E1h4{D{tQUrhyLa!iAnFegS~Q7nU%v1T~!
zKaN0CY>geU2lm4uI0`4=G@OHra0RZzt++Fs_P?LN5j=&z;Z?kY5AYejMQaLQ4Y@G{
zBQQN?#XMdH3StQ?kJYdaHpCX#4!dA)9Eihk3{J+G=$*&FQe1@_@q65j2k{u5!HakU
z@8M&7i677rVb+va3-S$UVVD{-Vh+rYMX)qh!WtNhO|TVq!0y=BRQCU10wZxePQ}@{
z5Wm5-xCM9MK0J&k@f=>k+lEH_|C7K|e1n#hzJn<MlVS=?hgmQ;7Qo_I4y$5qY#^HL
zzd3=n*cp4_0QBOQI0<LqTwH=HaRchO3lF5E{r^nhG+w~#_&Ywr7x*6SseCo%!DN^U
zBQZPX!@{X(|D_02#OhcN8)H1S$8OjMzrYbV4!=T$3vjuYfi<`px8q*?2~Xg!co}cu
zef$ewqn6rNLoQ5$-f#xeVrI;R(O3-2Vil}~^|2YY!A{r{`{PibUTrjii8vj<#>Mz8
zuE+222mBF_;xBj}ui;&MXe#^vIe~X*ldr$c^8pOSl$ZgtVO}hRC9wj=U|np4Ee(zK
zpFp51CgLC*j$?5O&cgY)3|HeO+=hGb5FQuJ_J5YZCA^7$;1hg>AJLiCS5v{59MfPX
z%!yH06w9Qg{Z}SX6XUQcw#JUw1N-3+9EB5b8qUE*xB}OurTuRuuoL&=5j=&z;Z?kY
z5AYejMdLU!{<$#(BQU+O|BVT<Vje7rC9phJ!#dayTVOlvg1vDd4#P3%oy@>YoQF$s
z6>h}uaW@{sV|WHH;tjlqkMX5Xul9j}BfYOCf-nqIV@Aw@`LPI=#!6TNW3dUg!Vadg
z|GN|Di-U0_j>oAu8yDg?xE8nI4%~-_@g$xzH1_`$0=Mx`e2Q<-lEGI)0hkn1U^>i#
zxv>Bi$8uOzG~0h|0u8V^w#Cla3kRSVzr;y61LxurT!|Y{&p`X%Mc@GbjHmGeUdP|@
z5x&6pXpi*Oln0YxDvZSJkzU_~`3MxoQdkkIV?At)@z@@_VITYgN8mX83YC|E1-Km7
z;AY&8d+{ecfxqHqyoLAiFMN$!M&Aqfx)?};;g}XPV=j!wVptZdU@feV&9Du2!k#|8
zT7LpVaWqcE>G(A+#&2;weuqEck9ZV+!Si^{RQCT}0uS*yzC&9kUsVNSD5k^=m<{t{
zAuNd%Fb3-y8tuOkftHwnT`>^{;cy&_Q*ai}$7Q%0H{mwiBbx315P{=(7BAsV`~#oh
zEBuJg%)Xim#^jg=Ght4Q%1rw&N}vo@#+n$1O|dn0#2(lWhu|ojfYWdeF3L>%UqN6U
zZpEFrACKTE{0*<-9ejY#@GVM@x4!cM4Dm7$f$1?T=D~tk0?T7Htb+})1-8R3*c%6;
zcNha>a5B!sdAJl;;YR!(cjG}khG+01-oSf4z1m{}FYyC9vihnj2*WTnX2cwrAB$jV
ztb{c%7MqyL{%=K~19r#0I2cFbc$|u}aUp(#YjF$iz<qew&}jcB37o?#cpLx3r}zdf
z*?ct=fJre0ro$|l8w+4@(QN<a2vo(|*Z`YjTkMRzZ~%JoOPqu=a4s&vmDy<j8wlvQ
z3lHGWcp5L@b^IM4;R}3^_Uyiz@?bJdm7Vq<NgzAs!@^h!D`Iu5hmA2F+haHEgJ0kX
z9Oq@=D^$1um*X1TjN5T9{)8v+SG<h3@IL;9-q#FhIeb;*!Xy}uX)!bALgVLvjSHA!
zSQe{bEv%2tu#Hcz)`>t*?2kinG)~0n_%$xZZ*e_-hd<ztcocszmHmI7z%{&!5Aiv^
zLt9SYD-Og^Oo<sV8|KAASQ0B38tp%ZKwWHvEinPRVj>R0;W!qj;4GYv%WySr63zC%
zjldo}gvaqLUc#IB2R^}9_z|7Cd^Ht}$uSLP%0>InNgxV~Vi~NAH8BpGVr%S(J+L1R
z!BIE?ry2ck8AtCN0*i13uEVXk6Zhj0JcYmERlI`_@EN{Et2eiA1Kb#b5ttscVje7r
zC9phJ!#dayTVOlvg5KT?48&nL1}Ec8oQF$s6>h}uaW@{sV|WHH`t)iy2;9TR_!2*$
zBag49f-nqIV@Aw@`LPI=#!6VjRQ7)?fhO1rJ79P0i-U0_j>oAu8yDg?xE8nI4nw2;
z?;~&+PvSYeg17Nce2Q<-lGj&50hkn1U^>i#xka=67a&j^%VAZljSa9lw#Cla3kRSV
zzr;y61Lx+Y{VyS~5;vfZyYK-1jHmGeUdP|@5x&6pXwT=XDNjDye=-88FcPz4J}iu-
zup(B+de|7_u|0OfKKO-~fe|<kze0rza5=8Q&A1)+;!k)2f5ppq3%&Ol_zPd7(Qlsd
z&gjA<7>;Q%Gv>l*EQV#V3f98<KD}Bq0&TDp_Qd`;6i4GkoQ_}PV*D1@<9GN2{%9)u
z|0sc9@H}3_yZ8{F<2$rP`D!W<Lop?0z-*Wo3mF>iza)VQ7=v}O5w^qx?23sv2#4cX
zoPx7(J}wi@_P?6ICftU5@DLuyvv>(_;ve_~U*Sh|M*C_i7?VfS{?ic1ggG$^i((n9
zj5RS1n__G1h&`|$4#82;wEqbNrr{i1ge!0zZpEFrACKTE{0*<-9ejY#ybQcW;|FMr
zX6MEbjKK7m74u+0EP>^*8rH#v*aE%n80dn%aUc%EF*q4#;yhf6t8gQJkGt_89`otd
z&JehWH}D=l#+Ud39R+<g6@+1!8Z%-J%#TH|w5ja>N(5?PEH=Sb*a5p^UmT1haXe1N
z*|-qD!L^1)``<!f2kyhecoNUy6}*jq;!}KsmO{Q73c#e80@I0R`_DokHx|I+SPrXV
zZES$eu`PDSUN``~_$5v%MEjpXU@k7fmAC<Q+=U15XFQD;@H+mEkMIS)FGTyd7xq<^
z2a{ncjKu7i4+~={tccaI9yZ2!Y>(Z%4D`V-a0HISuTbFvT#jpSGj7Md_!FMMU(tJ+
zfm?VV|H9X(74g-O3zJ|trp3&d3!||Zmc=SQy;>~-^|2YY!A{r{`{Pg?jT3P?evOOq
zTU?LdnackEfxwS=6o0|<cn$C3Lwt_!&{ot}Q-K(YDKP_PGc?+NUIK-%Bv!x}tc#7X
zB_?23OvFJr9LM4moF$s=e?Ea_xEeR%Hr#`U@Hn2uOL!Ciz$f?$Kccf3?LWAfuga2R
z8q9<_F$#-f8LW&oF%FwzYwU<UuwOCS{}2MBZ~{)lIk*T{;5yujJ8?fA!BhAfUd20J
z1|Hxue2c~p%9-Z_7=jU)9<yQ|EQlqrJXXUx=xxYA3v7p7us06GVK@dS<4l}~OK}x$
z#P4ypPp@{6z%e|77x4z(!^ij%KcJ(8ucm@93{zu9%z^n$W&al;P#P;?4UEMm*a|yf
zckGLUaU_n%sW=-K8XE2Y8v<)_3+}*uco<LOIlO|m@lSk;Z_rZGS3?1qR5aUv3Igdc
z3+BcGSRBh?RjiE-usOEH&e#hFptmIL|4Rasa0brBCAbndppLun0RD`p@d94Q-|<mN
z+W!jz@6le$S5+QNhN&<TvtvFijHR$5R>ykS7~{PRw8w7P2fx4(I1ax;g$r;wuEEW?
z9rxl-=sm%}uXq`6;eGrIU!zvqS3@pLg5j7JGh;4{#$rCbT3G^Buol+GX4nQhVNdLj
zLvb`t#Oe4oF2-+7W&f`y@E!huKjKmR1<&I(yo(R<Ile<%8DC8WVko9GG}?a#0@*Mx
z7Q&KP0b{T(Ho}&efL$>W2jOrWE1K<p3V~TTAD7{3+=Sb34<5qfcor|=P5c9&;HxsU
z|BnQmWqnl@jL9(#X2P5pg+;LpR>qnbhfT3Hb}Z}lt*{4yemDe2;RKw9b8r!^z;(D4
zcjA6Lf~W8|F9TQc4nDwV_!h0@d>ib>5RAa|m=*J2K`epg(OZpyI@l0fU_0!By>TE8
z!!bA+XW~3uimPy=Pp|epf!%lzkKq}-h&S*aKE{{$0UhOiH5G(mm>M&hdNnNvf&5qm
zOJgOhfw9;GTVV(6j(u@3j>Pde)zE1Fvk5H3Z*VPc!5z2{593KZhga}6{)tcV4O%MD
z{sUydILS<kDKH&o!Q5B?i(@&ginXx;HpjNu8GBWr{SP4E#V>IZ&cM021Xtn))NvOc
zz@PCnUcl=WWd9ql{C5J6@CCj{dqv-L9!!R*FcPz4J}iu-up(B+dR_(^V?4IUZrBIE
zz!5kOze0rza5=8Q&A1)Cdl~o%PvEb38E@fz{0m>BR>@aGE=+>qm=-f*E}vd4nm{ou
zi&d}|*2iYp20LL-?2kinG)~0n__e9*|HTBp#r60d{(wK?QTzqZ<2AgC5Aiv^LtABE
zO$8bn?LU-2O3Z-SFfSIul2`#_ur4;jmY9HDF%bue=I8%#0%LIs&cgY)3|HeO+=hGb
z5FW>~cnNRfAC+nUPYArikLax8tEym3j%hFx=ENv0ie<1e*2Fk$T7~xCnm|YFf&Fj@
zj=~8z4d>t@T!HIwEAGVoc*M)VDf|tu;vIZ|&+si;tNLoljUgC;=`kzj!Gh>5!9aPe
zhIOzZw!n7S1$*N_9EM|XGS0+#xYVatTSZ_aeviBHARfarcoA>lJ$#HW@dG-l`D!W%
z!%SuWrzVgQb6|cff~Bz%*1%Y7f~~LvcE`Rr7)Kf!?SDLhsW=-K;y1V!x8M%khllYb
zp2I768~?<oqS^l65U|Afswe=HVhT)$Sui&iz~WdAt72_zfX%UO4DG)&fnGQOz4#?g
z!WlRhm*7g=fI9BN1NbwZj-mZuAaEUj$4B@A-=n>{uckbh3{znwX2*P37)xPAF9X%F
z9yZ2!Y>(Zr4}O6oa2$Sx3K!sVT!Y@t3~a}}_!FMMU-2^D!u$9azDBKvuZCQh1j8|{
zPp_7lKrW2NVptZdU@feV&9Du2!k*Y4hvI0QXe#@EI)SfoF@B5d@jLthf5fBs3!cYo
zco!eyb9`rLw0~PoUsVNSD5k^=m<{t{AuNd%Fb3;lBW#HY*i|&!e<FcFI2^~~6r6?g
zaT%`0O}GvB;2}JYXYo=^+W$=gf8Y~*g&)yb%U4sum>kn!Cd`RZSQN`(Wvp3?_8&)}
zDYnLr*aQ3F5FCXQa2n3RMYsaj;a1$~Wne!Z!BhAfUd2230H5JowAS|3kQ+lV0@Gtw
z^yXopAeO-LSPko7Lu`TVunYFafjA7u;AEWX)2q!RuoPF}M*JRk<3T)zXYeB4z<c-@
zU*ZRJ)G=yG_J5E$plM;48Z%-J%#TH|G*-eI7>iA?6?VYx*w@f#|APsP#PK*4XX8Tr
z2G`;i+=2V>FrLJ7cm;2ZX8Zq>z*BsKmb$)!DFBmV3QUJtFgF&!;#dx=Vr^_tm-gSB
zKwIpLy>I|}@k^Y9GjJ|0!IiiHb=-vq>eBvyCU6=r;C1{RAK?ppkM?@Ln(|;WOofq{
z9rIyfF9W5pB38$G*cjunJ$A!B_yvx@arhM~T!7x?46MP;xE=T6Pj~`<#mjgL@8e(i
z8nswo4Y@FhPp=kEAT4IbTo{eTuq;-=T38>OVH@m(J+VIyHI@B8n!rSyj$h+q{1(^a
zclZPTh)3}kJdfA#E<Q9g+W&I`@6Z<KtExZ@#gv!<vteE=ge9>8#$a7+ge^t0{U;FU
ziitP~hvQhBg0pZwF2mKh3Af=MJcP&NX#ZykT*9092R^}9_z|7;eKi$~$uSLP!kid|
zMX^kM+J9vNH8BpGVr%S(J+L1R!BIE?r{Nr2ge!2Jmw~Og6Zhj0JcYmERlI`_@EN{E
zYXe^mxiJJI(3_rtte6K2VhJpd)vyjW#1_~NyI^k|h{JG<Pp>waz)YNnOK}x$#P4x8
z9>imK1~1|byoZnRrK#-y4+I<yeN`2NVVD{-Vh+rYMX)qh!WtNhO|TVqFf`hKcLIHJ
zFpk9WI2C8(Li`5T;uhS2`|vQH#B-wA{;v?Yjep`(e1n!oz8VU^q?iKJVHV7d1+X}l
z!>WyF|FsD;z~<N%J7X^#fL{C(C*cg7i%W1NZa}>e?SB`61NbwZ#tV2If5%7o0^g&(
zv9G2)m<&^4Bxd(AkPi!EDXfUqu^u+Ycx;c|un&HLBXAskg<i$L0$h%3a5HYlz4#NJ
zz+dq)-opF%7rsWViCIHl&E*@=l3+Nd#mtxsqp=v4#VS|}>ti!)gPpLasqFv$1cu^h
zoQTu$Yg~-q;(GiJf50E{DE@-y@tUF0{_hfah|lpI+M4<fra%nEl$ZgtVO}hRC9wj=
zU|rE{|BVQ=#02b$i8u&{<5--6vv58x!_~M6x8a_qwEsf{j^kOpgg5aIe1fm=BRZS;
zYAP6$V;anaIWejk?Y}62GFTaFVjMQb*4PnyU_Ts!qi_OF!#TLf%fJd;hg)$c?#Cl|
z3V*|^cn2TgGklBI=Dr$oqc?<s2uzPzF%K5R5?CIqVI6FUEwCMS!QME~r&k+BU<^*i
znK%!Z;ws#T-{WpPh{x~@Uc?)C&s6sRV*)Sn13FsxswxP>Fg0ex9GD-AU}>y`H82*N
z7#i)r6@d=e9sA;79Esy`D$d4*_zkYbEw}^s;bGBi|0fBY!z*|j|HP;G1}!apH57nJ
zF$Jc>ESMV$VDXl;|8fMXVr^`I&9N<Z#$Gr8z4#?g!WlRhm*C2lwEqnRblimp@Mk=Y
z7w|g%j*svKzDIk!uckbh3{!a-h{Wue4+~={tccaI9yZ2!Y>(Zr4}O6o&^wNSuTbFv
zT#jpSGj7Md_!FMMU-2^D!u$A_Pp|fxfY!=aMJ`N&;g}XPV=j!wVptZdU@feV&9IHB
zSJOHX=!yMtD2~R7I32&n#rQ3*$M5h5{1K1hFNQ|@KTqHq-o=Ob9N(d>wXdcEF%(l`
z2F!+eu@IKT3ZmKmV+hp6M%WS)uq!6wARLZkaSG1D`M3;M<EGZM|7`^J;2}JYXYmr=
z#6R!}zQT{_Y~!n`U`&o_FjE`Z|Hl14ISE8zQ7nU%u_nf0Q*4bLu?P0UAvg*r;507-
zb8r!^z;(D4cjA6Lf~W8|yoz`50Y1aG=(V=>)qopAFapzKR?LG1u>_XKYFGywVhe1C
zU3_}A-UJ5XFdT!EaVE~grML<=;`g{458^RAgBML@|KA{R4<F-8{D6*jzM2ZcFiedZ
zF$d<yB3K$LVGTp0{l^k$f~~LvcE`Rr7)RoGoQkt?A%25vaSQGc&Gx^Kz+pUz=kN;N
z#y{~XzClZZuZ99JDW<@5m<4ku(EbY$D30Z@D%QpZ*c{tpXY7Ro(2HN<B%FbB6KMZS
z2&}{nsN*g?fIs7Dynxs7cYK5|@IBhw`)bPLWgr=*!br@H`LHmS!ircO>tSPz$M)C_
z`=Iv=21ejG{0bE=z~#6GH{*8Pi$CEB{1q?bEuUWPK7qgRHEJDvRpi1X7>;Q%Gv>l*
zEQV#V3f98<rn3K=5om**uqXD%p*R{R;&l8P7vs0M9>2pM@JB<V{U0Up3!cYoco!ey
zb9{%kj=q`-#86C$8892>#X_Rl{!0?5fH7DX8(~XKz^<5xgK#*G#VI%o=i{=DwExuv
zHsLnhgNN`qp2bUe6aT;`_zFLwvy-o;f-!j~+J71XnJ_0tVNooDm9ZwqVN-049kB=Y
z!y!1z%fJMjhI4QcuE2G;6?fu(Jc6h2H@u2>@Bw<CG4K|xoqbj0#t@9a^q3X%U_mT_
z<*^#p!G_qvr&nu7pbPfKfjA7u;AEVM^KdDy!j1Sn?#6?7%vARO83Gsa2HwNR_!2*$
zql>Smf-nqIV@Aw@`LPI=HZ<CQB?2`t7Moxz?10^|FAm0$I3B0sY+Q)n;9Aja|62&`
zz<qcaPvSYeg17Nce2Q<-($!Z(0hkn1V7jif|11P@V*xCV<*+K&#s=6N+hS+zg#*xw
zU*e>$wEr0d=He1ui5pPIU3dV0#?yEKujB9d2w&iP{}$Q1`Kro;$uJd0Vs^}jg|QS?
z#OhcN8)H1SM{hR<`rsEh0>|N3sBi%;$2GVax8q*?2~Xg!KE2vy0=Mu!{)Mkm>+Y)|
z7bd}QOpBQ@7e-?-EQ?i4W&hVAP#>FN8|;KVu|E#Q(Kr#O<JY(tzs2?VouSeGe<1K9
z9>rhqJYK`Q_z<7tJGAxi)l?vcVoJ<_*+jGb=Os`GOJW6#!MfN8TVeus#Y7y0!*MK5
z!C5_M|MLkf!_~M6x8WW<gvaqLUc#IB2R^}9_z|5wY5&1JeN~nm(_kjdiBVV-%V1@!
ziE-EzTVqG;f&IJ;48c)20jJ>{T!brd9d5;)xF3(;Df|tuqW2C15AYejMQbl#&A2fH
zBQQN?#XMLLOJI4dhIM>;wT1**U_0!By>TE8!!bA+XW~3uimPxVevi9NW&a-}a177j
zMZAIc@G-u`59sLatEnIi!_=4&b6|c$qx}~lP#P;?4UEMm*a|yfckGLUaU_n%sW=-K
zie~%&hQM0ff;(^@9>)Je(_O|_S@2;19s<%JDJdWg0#ec;4GI<rDq<k0SRg5N=#cJ4
zQo6glJEXgj6a=K-bM{>C7q9<r#s>GZd;5UDZ6A;DG%xW6@9{BXGz%Jv%OuV0Kb0T@
zvoa40vN+4J3Tv`9>#+eFvng9M)Xe_73;J>hM{^>la~_v+4L5Ta5ArzA@hWeJ91r-6
zv6=@}C15h9VJ7BaJ{DmqR$z60z`6{5;b_F4*qm+InY}oG!#R#qIExFpg6p|0Fch^{
zaG0lfk=J>bj~LY=XebU7GbPhA3v;soi$xoL{$&M~S%bCs8NcTDY{FLTz;5ir!5qa2
zoE9;%|G9!CT+L0~$pbvbv%JDvyw9hM*)nJ<K9e$a*y#Od6l7;!7G_D7XEnahI;_uz
z{E^MrhMm~6rTzC84C7c%=1eZ&a<1c6?%`iN$qW3O|M0(-_Wwfga;u=KL`=bSe4V-Y
zCX2EREAd@^#83GZzY95jVN14WSN7&0j^ubw<s2^NDsJQs?q}$z;|wqJCjaFVzSKHs
zC>~$ot9*^w_y!BH1m6w}MO78N$B+3rzu^!3mA|ngd$1peattSN2Iof`e*Vh@Yq^EH
zd59-?p4WJX5BZ$2e+!yQ$mC4R%n>8|&nd{yw^*7L`3^tiC;XD%@@KYSJ9gpk92how
z|04u{@K4U>BCg~HZs$H8;b~st4c_Bp#%N>zaoYq{C1EONU{>Z~K^A8@R$)!nW<54w
zV>WGL|E&cfc4uD>;b>0ebk5^auHk0x;z1tgx&ObztAg8nz-NrrHfSgTlQ9i5F$eRp
z2ura7t26Y0qb|Q-BmTtZY|GB<#Q_}7ah$?gT*wuHp{VtOZQRSlJjIK=&bxfXsCGd^
zahRAXnVwmgJKFH`FCZw!vaHM+ti{jxHNR&Qwqgf%V;>IYsECpMPY_JwTrS~iZsJZJ
z;4z-%72e`~K4r}IK~wR=M(;nVAT={GJM*$IOR_wx@qN}|eKzEeY{oY2?Z1<tC;M|4
z$8s`fasiif9k+51|Kdqr;NR`-{~y7Be8HDH1XU$s3Z~=h%*8iZlx0|n@A4yl8ghKa
z@AwN_vOT-9HwSSf$8##@a4}bLBSSkJ`+1aSc$qi(FQ4!w4aVaue3h>;8{c4|z)(~P
z!P~6L_xLeC=QsR;zw$SBWDoY^P>$iGXv6=RA(+o)T+1!o%|krF^Ss78e8}gF-7)xB
zO3369Bl}M)$jqF~&$n2b75NT7<R|=+-|}a+U^{jR8@>PE1p_&PfACMv<|3}-25#p*
z9^q+T;tk&GX#bA|F**em#bpwvVg_bq9u{PAmSYvxWNp@CgHE1JV?k54W{BO{mqR$3
z6FHspxRh(SnY(!K|L@?q;2f{=HXraAV|5OiO2A}H!%WP<d@RCJ3{`Mc=Lf9IFW87b
zu{qnaGkb9WhjSdKa8_U_YN22S*K-^9@-R>FBCqo<A2F&+&`=yEW=f`yHvIgv2y(Lk
zi?J*#vj%JNGk(qQ*@Ugwf!)|AVr2h=1*15D(>Rw)xSE@|lLvT=XL*IUc%M(hM(;mn
z*PyESOv=>E$n4C^!Ys-1tj70QhxOTzKX$eMW`Z{C#GdTWVI0fJoXG`T&UM_%J^YI&
zyW0N+!QcFc|M3N1?iMtah$)zkuQM0lWKou3CB7SSe8f-r6~E&zY{~ZQ%HABrksQyd
zoWsQot#WMS4({hsp5bNQ<iC8vm%0ZH#p5e{m9H^dU?}PhK_Qml+pNm>_%T1{H~fLW
z@;7#55BB5GXv5Ecj9?OHa6XrDEw^wt5Ag)g^BV8)A)hmL5BpCTIl`X@k~1wcGbi)&
zEtY0QzQYgs3BTmG{FyDnM(@9!pbLNJK#t%a{FAe}h%32)+qsWNc$$}b*#8Z|Jw9fP
zo<TElnS`mBfmxY{1zDWsScNrNyQlrv6Et9BHf3vu*qwbjgrhl;(>aezxrUqn{|0vn
z4)Qq9@hWfg0iQ8eub`;}OvW_K#2n1WP!UHdR$z60z`Fc`jrbFrvn@Nb7YA@S#|4I>
zrU+(nAy;rcw{b5I^As=gI`8rkqkaz>io?XwhM#{*L3(CkZWdrMmSttuU@d;eulYTj
zuoXK*jC}p?Cg{V#9K{Ko#<^U=)!f9LJiuc-%PYJUHhTZ}1y32XcTiP)CS_`7WOn9d
zVU}chR^$7u!}`7LzoFnqHe(xhVo&zxFplM9&g23v=Q?iXp5FHVm*6BX@NfRZ|M-G0
z_X(Ox#1u@&*O`lNvM9@h9F_PkKjNqSir?`Uwq$#DWp57RNRH=JhUPdHa}_so2lw+R
z&+syD@?SpTOMQce;_(%}8W@UtO^}Umun<e|ZC2%b{FtBf8~(sw`5Qa3N3`MR-%l`<
zV>pR3IG@Y7mRq=+hj@bLd5w4YFk)o?&jqpj1yv<va;9Zw=45`p#nP<EclaSc;g|e2
zZ1nzr7PMeHcH!?F$PxU5e{wb#aV0l!JNNNOKl?u|xWpU0$H$D(KWHc}lQ0!CFe~%0
zAd9mctMs@3nu6M_#|CW7rfkg+yR$Eca5N`!I_Gie|KGqG!DjB_K_2HhUgd2*;4{V=
z5Hyv5$(V+j7|P+u$097n3ari#SeIY05r1NHwq<Ab;()+V)NsK#PT?#r<O;6mHtywN
zp5jGb=UqNx)WAqX;pZPG`iP23%#=*eEX>UUEXJ~|%o?o4&-gXJXOoDL{kIZyU^n*R
zV2<JhPUBoI;c9N;P9ESfo(&tl|0{x9yw9hMIVkvGiqE7>&5X>>ye!O;EYE6ue~|sx
z5!7cx{>Wx*!%pnU{v5`!oXnYAz~x*w$o{tq_V6#B<OTlCfA}9?@a4flQ;C>@>G(Qx
z@y(E<D9f-C-{nXAlwa{X{=$}Q&#vsvK^)1@c*j)E;bN}hM(*H#9_1Nc=1u;~Cwys0
z&``X<P}D1eSNR&V@eLMY3BJv$e2*XVbAH1g_$z;lHvIfM3VN^~hjI)jaR%pe8P{?P
zck>WW@I0?YjO_o8;31zg_RyfJgiOw~%*>q3&$n2b75NT7<R@XH_y48fTmH-zY{xGA
zodY?7fACMv<|3}-25ui}|N8_-c$$}ZgZKEDF@^;V#bpwvVg_bq9u{QrVfJ56P=z&F
zoAua$joFl~8De+#<q(eML{9(zZ<r@o$~D}~T|CI+JjbiN%?EtOSi^&+5-=G<X&jlD
zgZWs5rC5R0`2p+l3pV0UY|ggq92kn~B^bcr9LFh~#f4nK_1wn2Jj_$P$m_ftZTR^=
z5=4y%DvHCzOv&`j!rUytVl2zbtif9Rj9*8L?EiZ~6SiUpc4Hq7<|t0!G|uG`uI480
z<bkl!`#&Z)%PYLa`+UlnBZH>mGbvLuBeOFv3$rB4kF@`4g7;a6_1Ta=vKia36MM2h
zhjA<?b0!yzwEyLTb==B5{EH`ffq(NK{>K-5c~sC;BBo$Ez8-Sq;+rhWGOWaR`4K<m
zSNx8@uqE5GD|<6E$T5=RIhAv`n5(#vJGh@md4`vHlmGHbU?}RP(LqJ=_zGX;Ys|(s
zScoO~HmmYIe$3DL4S$F>{QQ3v{Kk&#!G0XdF`UF1oX=%k%Pri^Lp%{Nvj6jfYrMmU
ze9qWof~FEOIny#Tb22~QVrf?7J7J^u|DoU$e#vk7Gh477yYP1o<Ou%3KRKI=xN?mB
zZxC$fJ|5v|Ug8bj<737c8#EM`NtlWmn3Z|P+J8Yoah78h)?{tgV*@s3Q?_P^-PxBz
zIQsvuFi|j_^SG32xS6|nkjHtBS9zNc_>8f}1x<w#IFd09GcgDAu?S1C0;}@_*5wy$
z#GlwaFcj5R(3!nBfWtYCQ#gwYxq|DtjeB{Rr+6{i@bkYexXVY3`Xi_)4ihsa(=!Wm
zvjB^+EGx4HYekIg|1-hY{GLtNiXGUEeK?q-IDykRmrJ;so5Du#f2ZI8kMS(8@D}g$
zDPxWgnu^b)OwEkU&b%x<-u_Dp%Cj2ZXC2mOL;lESY{O3M$^IP1v79_U6#U6&3KnoV
z*KsTN@GqX^1^&%{_#a>J<q5(2OT-i*M>@XFTzr#7S%#JPE<fU@{EFZ47q(=3hPpa>
za}Y;zJg0IF7jqRiatHVGD9`XRZw7{<{uMmoOA~{N;_(%}%Ga2UZ?F(c@NHJ*d;FN6
zM;m_r-w1x-ul$W2*@OK!lw&xFGdQ2ixRzVEJ7Q%2hXf~hp4WJX5BZ$2Ck0I<WOAlu
zX69smzQxjEqxWA?@D4xZC;XD%@@KYSJ9gpk9LN#;gMV`NB>P_^Sji3C&V4+>)4aqR
zyvN6kF*#@`E|V}7GfcMstb#l&$l@%=Dy+%ctj7jy%%*J35WBPQ|AQfd(VWQXoX4eH
z!_C~qgFMc2yvo~rz|b>CtSLcN37Cv&n29-<k40FD6<D1gur9w~qrgzqPlD!b%g*e@
z0UXY8oWfaL$Q4}AZQRSl(T1P@DZxcv=UqNx)Sp2^ahRAXnVwmgn*~^mWm!35WdAh;
zwfGso=J#yER_wrT?8Ctv#R;6oxm*%9djG2ho4At)c#LOxg|~R0PZ@J+&{TXTWol+*
z_Nn%tS5TNGS)SGSKI^bP8}dgsV;gp2Pxj}qsrElsFqt#CfXlg#Te*jS@gy(sZ~nvo
z_<}EorUg|cVhX0?>&(SBS(Ig1iSP0we#)=-9e-h{rK3H&vNs2DB*$|q=WsDsaU*wd
zKacWEU?}Rc;3og&6TUP(Xeb_E;j4U&+4u$vu>{{{RlXN(`1yY<_?+MH2mZ?6*pWTh
zk3%_zlQ@I(xr}QgM)to&u$zZ?g6DaScleOc8GA<1R6-_aT4rWW<_{aa|F;CCS&{GX
zLw>?9`7M8D3$|ky{?36M!9Ql$|DS@{T*Q^!!0p_}BRtJZyuo{X%osC+hT<~GO#4qI
z$iS@3!-6c%a;(Cdtj&6Cz{YIK)(nLl-PxBzIGPhVo%6VqYq*)ac#y|=j#nAF?Rdav
zj5RB$Dgl!*4KpzZ^RWm^u>z~}1J(@;MSUS?#GlxlZP}T<IDo@Bj#D^`3%P>pxh>l8
z^WQ5t%u~F`>%7ZHjG7%Z6o-kKlIfX+xmke4B1ZOKR#2HWSc{+WYktorY{d@j#y%X(
zQJlbOVWamySFnVuxrsY@fX8^2S9pu}`IIr|1Wm<fQl_3`{}~0@nU{rGlI2;A@3Ri;
zvmt+EGqzzT_MBt?{RP7~mXkS?3%H!?xRrbO7f<p6|K>mZFXVW^m*)mmC1MJu<Lk`D
zH(8WrSc&iQBYw)S82Zlf3tO^1yRtV2aU{ocD(7%9S8*eEaDQMZ>ZsrhFY_k<<rBU%
zFK8$pU*W5KjoJ7H3$X;>jyC-Ks|w!Z$NZe%@CW|N-`J5o*pEXwhLbph^CL#~zf7=}
zTezEtc!KA7jd%Ev&l!7u&{RSuXIf?s8@>OWg8Y1orCE{h@I!vWFZnHhW(&4s7yizH
z^X-3x;1B-E*<8ex+`#SJ$0Iz=OT58*e9RaN>_6^;psFNH#SF~KJS@oKEXOLW$=a;P
z25iixAxCTe|K;vp?#m$@&54}Od0fgh+{|4($m0y1b6n+ZKHxLPS{O8xfXSGKnV5t5
zScIimfz<;;Q6C8E@(VWNPi)S%?95&qz~LOnDV)WHToG;f`L7pj<6a)-DPH7t-sK}k
zEeaZn!^BL<^vuHC5hMFAASlMNtjrp$#n1RPzh@J+Vh46(9}ecIu+jUUAehFvT*B4d
z#GO3AV?4_%yv6%`%9x9Trs6NQ|D=M{%*gD_%fc+l@~p=9S%>x6kUz2++bp*KPJ*87
z&tV+P$(+drT+Vge%02vxCwYN?haCU#Kfd70OM<ErF$L4{b>`xmEXp#h#CQ1-L!Uan
z;&=RoE!m!3*_(qnlH)m*bGVqRxG^vkwL`F<M|p;qd6WP0313<oG!&1o@KwIXY<z=-
zq76U)5`wo`mGALme$H?B1Apaj?8qMM$Dtg<Nf9IapCOpfWn9ZG+|5Hg!SlSvJABCJ
zjJ+&qDj}1HjoyD+L1yM;e!j)htjKrxAwS`l{FXnn1>3R9GW-8sFpwko2mj=3F5*gV
z;CAlg5uWBH-r&9ef3Jtff*8w#isCW}Q!xXxG7k%~ILomLYqB=$u|deum`&N5|Nr&w
zUhc~w9L<TG&UswQHQdZy3>|bF=Q&>GZ9d>L###|Hm4L~ZhMAay`B;Rd0z*+11l9Qg
z>+%aW;!kYOw(QJa9Khim$0?i@ZFv6+1uM9o+qjp9d5RZ#op<?&Q7eOn;xI8&GJV9z
z{<8>jvjB^+EGx4HYw<IF&F|TSt=NIx*e7iC{s#+2aRR4tE|+jMH*qHq@EFhX3UBc~
zpRTn3n5%-S;xj2zGb6JzFAK9I%d;BaXC2mOL;kqR*Z*dMHtfWn?9X8w%gLO{1zgT`
z+{!)tizh>l3;dh^@ISub%d3N?5-|nS@pb0nn=HyQti;f}j*s{$zv6fNg)P~hUD=z1
zIFjQzm2<c_Fch^)u#r2spGSFymwA)_@(EvB6EqZ$ukcmA#%$4spZ^<zLM*|zS(Wec
zV}8zW_yd3CZ|uk(?8l)IBl{mCn8X>J&t+W8E!@pRJi+t4#yfn-=ZwA9{u73e=x;#4
zw9L$$%+I%2nicsDKjbI;lHc-YwpeTb?F3!;I|p(E|KOjT%|%?v4cyLsJi^nw^#AYi
zbVG2Dj~QcK&`ew=VJc=|R_0+r7H2tDVNKQ!IqI<i8?z}}^Z&2k-OGJBgrhl;(>aez
zxrU+5j$J&+<2=W!yv+xE##rlvrV=n2(=ZcrFkfIOs)(QzE3i60U|oK}M*NA**_NHz
zivu{E<Dv~kMNJXR;zF+AdT!%h9_A@t<aOTVBSviq8j8cj5hMFgDM-&O%*_HU#<Hx;
z8mz_7_%*+06SiW9u+d-ty9xSmFh_9$r*STqa5Xn^ClBx#&+-ayZLt6Qf~SnRF{mm&
zlQK0kGCT9KFiWyLtMPr-Vf~Ha=O6jZ*HG{yo3RZ$u_ya;7{_ulXL13Ta~-#GPss5X
zPx1o)=0E(8FZlAN;4hGfDVUD0GZ)`vQHIJmD)C)@#83GZzvC}#$@c8Z-W<e{9M7qN
zp{O~6#azXW+`;`k$}_yooBWqg_|oQ}p?G|SuSOew{;vtL@eLMY3BJv$e2*XVbAH1g
z_$z;7NA`#q*?&L5P>$gw&ft75<63UvZXV(Zp64~*;lr@e`+qKoy(OqBA(JyLGczai
z^DUNUMZUui`3b+|w_EK0XF&_LV;BC;fgHg<_$Oy`5m#~pw{stl{QrA9o)%o<4c_Bp
z#@HG(6qiYuiW!)dd03FeS&mggj+(5^dThYPY|7UB|L^ba<-Q!k(VWQXoX5~o#~N<t
zE*|7@p5s;C<^w)stZhM437Cv&m?<z6l|zt^MOcazSe+lRF27(S{>0{N%g*e@0nvu{
zKU^@5Q#gwYxq|DtjeB{Rr+AUqd6$nEwcY;XM2_(1fy7M7^vuHCEWlzc%gU_5TKtS(
z^LsW48@>Nlf)4D)J{-(ZoWN<E%OzaRP29-?JjS!z?f;747Vq;ZW9|qViqE7>&5X>>
zye!O;EYE6ue}}LCbp-X<kUz2++prURvOkA$EGKg&7jQY(g&bSChkx-TFYs^v!~gh#
zFYgSRO2iaQ$Jd#Qp*I~xS%#JPE<fU@{EFZ47q(=3c4co4;>f^I)Of*E&f#LN;zsV^
zejeo+Ugk~y%O`wkSI|(rXv5F{6~U`~joJ7H3$X;>W>vn&kNG*j;Sc<kzeS9E{qHE~
z!G0XdF`UF1oX=%k%Pri^Lp;IrycRZk|91or`JAzL2UR6xa;9Zw=45`p#nP<EclaSc
z*=_${3clsfY{7Qy!rwWNBlrjZ<ZLeDN^aox|9?;CeS#xA%}cz&dwk3odxD1IG6_>L
z1G6#@3$l2~QI1tuleJlo4cM4X*_!`<d)>X<mqR$36B(NBn8&4D!_C~qgFMc2yvo~r
zz-NrLH)tvWlLdyN(g-p!2lKHAOR)m0^8?o97i`3z*qm+IIok04dkF?`ILC1cXK^7{
za6PwiFAwt+FY-F?MvUzLksxYcP*EHvW=f`K7UpIF7GqgfW)0TjXZ$*B^!~pWG+`@t
zU^n*RV2<JhPUBoI;c9N;P9E52|HlMpd4;!lpHCTcf6!EXCS_`7WOn9dVU}e1{l5NJ
z6THtltj~u0k<HkKo!FE8IgDdDnKQW{<XFyi+{!)tizj)3fAb&y#}|D0K+seoreHdT
zUU%f;n=HyQti*Tu5kKWu{Eok{CEK$rdk2Q11_?%TJg0IF7jqRiatHVGD9`XRZ}MM0
zi8k{54+a&*<12iXuQ40nU?G;^+pNm>_%T1{H~b-DWdFYkeq%@WU_TD!7*660&gU|&
z<rePdA)W{uz5nxqYrMmUe9qX1f~FEOIny#Tb22~QVrf?7JBRH5L%}EflHc-YwqQGU
z;qM&C5&VOHayA!n<^O+{!v?{2?&A@j<|W?XJw9fPzk-J1G6_>L1G6$u$Wf5RS&mg$
zleJlo4cM4X*_!`<``x|VmqY&l>!TeLIi2&klxw(|yLgbtd5%|kn-BPmu?|N!6^cp_
z98t-bhMAay`B;RdSb^2~0qgP$HsVig9&LF4Z3Ug#ivu{E<2Z%0xR5Kjp4+&Whk1$@
zBS!XrU2vC=7<DB0V2Z=UOv&`j!rUytVl2zbtif7gqxb)r;A?)*CTztH?8ZJE%u$@c
zX`IU?T+K~K?0=`=0FUu3ukaS{^C@E<4VsG2q)g3>%+9<leAL(fl7jNA#`jr=_1Ta=
zvKia36MM2hhjA<?ha5AxfXlg#Te*jS@gy(sZ~nvo_<}DV3z|yAPzpynzRp~HlSNsE
zmG~|{;-~zI-|-i=Wc$ESR98W74&q3T=Ty$&Vy@yw?%;kN<r!Y)&1l2V|6joqzH~gO
zC>~$ot9*^w_y!BH1m9*=zQ>RGdBn*6zY+YvU-=t5vIqNdD93OTXK+53aV@uSci8Ct
z9}=A4d0yikKIC)8J`psPkja^rnVFOM`4&r`u>XpJclaSc;g|fDKeGkfu?v6aK#t%a
z{FAf)|1+Ex3086gw{stl@H8*+2Ji7PW1I{cipwNS#S9@wR_0+r7H2tDVNKR%JvLxt
zHf3x6|NV9U|I2+HLpYifIi2&klxw(|yLgbtd5%|kn-2m*QO^XiP6bsZU^1p*Cgxy1
z7GWt?V0C`Ly8METq7Co=CqZ+zWoP!{01oFkPT?#r<O;6mHtyx&h>`uD5?thU-sK}k
zoemm`!^BL<^vuHCEWlzc%gSM+_g_O$i=Xjpe$OUs#SZMoJ{-(ZoWN<E%O$7nf3;u}
zck%#_@hq?K7Vq;ZW1b0`iqE7>&5X=`CKSA4UO{1&WO-KO`>ezIY{(zkjBVJ7J=veb
zLXNSV%$Z!k<y^<D+{3?kk{9?l|KWdp!O+WRg9Z{Y1=I0$=Hi<y$}+6Pcli-N<yZWU
zzXXP&S_;~;D|>SgM{+!;at;@B6*qDR_wy*vL>r2Vx-7WKfBA$joeLU@$5;3&Ut>1D
z!9py-w^^0%MU3qKW5MVAhClFE{>F~%!G0XdF`UF1oX=%k8#a3XTLim#h$ncS*La5y
z`JA!O2Tdhpa;9Zw=4Af!_WzckG%NBQe#lSwCBNm*Y{7Qy!rwWNBlySve|F=ag4tZe
zmE6GX+{Yt4%}cz&dwk3o7lMZ3GD*mhiW!)dd03FeS&mg$leJlo4cM4X*_xsM{{gxS
z`f><Ib0Vj69+z?rH**&c@;J}&YG5epw%`GuG1kSPssv2NG|a>t%*P@u#R{y>4_G(a
z@czFLG~!Qe&bI8#UL3&T9LFh~#f4nK_1qRQvj4q;!#u@{yw1CP#HdR_LvfgxDVd&G
zn41MyENt}t%L*#925a#%e$DUMgss?t-PnhNIf@fF?UMb^6)fRuZsJZJ;4z-%72e`~
zK4r|yK~wRWl&LR=pMT_ky~rrY&b%zlk}S_^e4lk#pAGpVo3RZ$v1iE9pTjtolR1+M
zxSZ>_m3#OXPx1o)=06Pm=Xk-FuLO-GVhX0?>&(SBS(Ig1iSP0we#)-`Ls8!eeql?t
zXIJ*-AdcjCPURdf<|=OF4(^XO{QQp!&hRpC@?SpTOIL%2;_(%}%Ga2UZ?F(c@a>3^
z{Z|#d$B+3rzu^!3mA|ngd$1peattSN2Iq&3-v2VeT5jQP9^wg}=QZBpLq2EhYe7>9
znVe~v`I`Ob6y)byEX|61had72e#vk7Gh477yYP1oyk`F+1b^^P&gLSn<OXi%J|5v|
zUg8bj<737M{T);kmr0n48JLxMSdhh8j#XHbwONl1*qEWFj@JJV*qwbjgrhl;(>aez
zxrUp$iwAi;Fcfu8aFw_DfX^7~deBq?CSw|AVh-kG5td>FR*yFP{67%X<ri$kpV*vj
z*_pjKfWtYCQ#gwYxgug@|LX<YxR-}{iWhmEcln4>H-d)ZFfmgyJ+m-(*y#Ni5ENrs
zR%Q*>;%EGt-?Ir@u>-rY4+nG94f~%Un8vwW!qwcwojkx}Jj*M*#ru59m^Xu_;@`CY
zq=MAU$n4C^!Ys-1tj70QhxOTzKe8FygdCmNll?i2V>y{Kxq!>Lj$65hfAJ(QF!Z<M
zAO6P|eEC*TRU)QfI=;?ae3M04hL!j(KMD**eJc2h-|-i=WP5gHZw}%}j^|X);bN}h
z#%ROOe}`Z{kMayJ^Cti06TWmiXeb_E;j4U&+4u$vMU3pfgy3yf<$L^?pYt33z+d?r
zJF*A+aVW=dQrPJI&k)S#GOpzo?&cw$;CWu-9X{l9#=a9Ym5|Br*ne6<X69smzQxk4
z$anZ5KjD}BmOrxv+p)_X`~O`qkR$j9|Kw~g;!1AdcJAX5p5`Uq;JuLJF=PA_R1}v<
zn2H&gm3df@#aWJ3Sd+C`kD&&R#%#*g|9=H`XI~ECXinsG&f`+9;b!g%3`HFj9OpS+
z<!wITGse0bG?jqKn1-2{gZWs5rJ@Z#{|bWY{D5`&1sm}vHfLLQW-kulaE{{?&Wae>
z|3bkEuID!H<zb%UMPBD!K4R3pprJTS%#=(YHhTYA1i4v&#aNb=S%bCs8NcTDY{FLT
zz;5hw&;ADsMsWhCaW0o|H8*i55AYbz@(OS9KA+yR|Cs*<RmEpgre;QFXI>U&NtS0d
zzRx<W&xZUl<Y>k=?8Khz&tV+P$(+drT+Vge%02vxp_7ga{G0#qKfd70_k*SqF$L4{
zb>`xmEXp#h6c~znSMU)(<yZWUzpy3SvnzXZ5Jz%6r*aM#M;m_rs{|XlgZp`uXLy-6
z`7fXFr3XPn@%Rc~<!j6qF|z+R1cg|FZ?h`j<H!7*-|z?i%HP<LJ=l*!!$$9aj9?OH
za6XrDEw^wt5Ag)g^BV8)A)hn$L;FwoFsLj!(=s!2GC$v9X;$Pr{E(mUOMc6r+2W!7
zw-a>X?;OYx{DXgTHWzUvH*h=m@d!`zQpj<G_xPAG{tKFk%Op(249v<rEXd+4$11GJ
zP;Ey&Heh2mWow4moqaikqdAe&Igd-ZCNLDWS+I)-d7S5XmACnT&lu}b&{P5@V;W{+
z4(5wC{QQduO0fc~^8?o97i`3z*qm+InY}oG!#OTuWdBnHv$&8exSrd%mxp<Z7kQm`
z`G`@EgNEWTaoFhnrxc`T7UpIF7GqgfW)0TjXZ)Jqvk6<V!(;pJCg{V#9K{Ko#<^U=
z)!f9LJiuc-%PYL~*#7Seo-*c>psM&x%GAur?99u;EXne$#`jr=^+S$^{E^MrhMm}x
z{W*+dIhixLfXlg#TN&Ep_=_ibfq(NK{>K-5`DxHpBBo$EzRp~HlSKnVQDp>`_%1)<
zr~HcF@fWsadv;}S4&q3T=hSG!&wq|!F;{UTcW^(C@(eHYCjaFVzVs|;C>~$os}Upn
ze@&2$Z?F(c@NHJ*d;FN6^BexaU-=t5vPanH{r3|L<rq%l49@2=uH_c)<{_Tod0yik
zK73~X&jqoc2UR6xa;9Zw=45`p#nP<EclaSc;g|gOx&8kvXu)>u!rwWNBlrjZ<ZLeD
zN^anG?&Fb=<1{bv2Ji7PW4s6&ipwNS#SF~KJS@oKEXPn4M@`mdJvLxtHf3vu*qwbj
zgrhl;(>X6N6tz^ahMT#I2YH<5c$K&LfX^5!Dn|4_?IvI{reUUNLs3yV1o>EmrC5R0
z`2p+l3pV0UY|ggq%w8N2F|z;Rf^nR}SzO2!T+eOX%fmdyi@eUee8i|2F@pWa2_KPv
z1y9VBOwTOL%>pdOvaHM+ti{jxHNR(*7%{>>|26!MTM0U_8~boDM{xqDaW0o|H8*i5
z5AYbz#s~#}^DBZ|yw9hM`BLzD@tKsVnUUF<mxWo9<ynpIha7cSpAGpVo3RZ$u_ya;
z7{_ulXL13TGqldJm3#OXPx1o)=0E(8FZgoIps7Sm!E}6`xdKB`ZwiXC3@h<ne#B4t
z6~E&zY{~ZQ%HABrk<o_tKVC4EbGVqRxRE=!pGSFymwA)_@(Evx6*LqtVr2iX2wvrD
z%*HoZh$Z+otMWa5%+L7^f8ekDEo}7H|Biwl?8l)T!%3XM`CP`e+``>F#1lNvYq9MA
zj^H7mGj{Bts)S6=w9L$$%+I%2nicsDKjbH|?f*-`xBQtc*p6NJI|p(E|KOjT%|%?v
z4cs1b?Bfxh<|W?XJw9fPmxG4lG6_>L1G6#@3o=yPQI1tuleJlo4cM4X*_t7CXI~EC
zXif|aMNJpX<5I5SX71ua9_Kk;<!wITGscP&G?jqKq7CmqjUW?qFdvJs6f3YgKVV&c
z!AAUv&DoZnBS!Y$OE7@LIgV2}iwn7e>$#14d6=hok=J=QZ1nyg38LZ#6~$p<reu0%
zVQv;+F_vXz)?h7u#;@br|M!9>Y{d@j#y%X(QJlbOoXaI#%}w0N199#DnBXk0@D}g$
zDPzV9nu^b)OwEkU&b%zlk}Mx`RO9=s!}@H<AK8p;*oi&apTjtolR1;21&-xh$F1DM
zzj%@t_&5LIe|*80;|EP8VhW}U3`M;z$i+8Vlx0|n@A4yl%CGnxe_>0uXIJ))HoX5q
zf{`50shq>bT*Zyt!TmhSGrY{3{FhH6M)v<wf}o;!e1)&_HD==*EW{Fgn^pN9Kj!EB
zhChUj-v6(H-`J5o*pEXwhLbph^SO*`xrMuVh$j-*|9QbR-r++&XY7PQQwf=zX_=Wh
znV)a5G%NC*g!ccT;1hnyZ}~G@upPVbcMjwT{=q*vn~S(I<k-ON+{Yt4%}cz&dwk3o
ziGqgWG6_>L1G6%e$5D{QS&mg$leJlo4cM4X*_t7CXI~Bp3`LC=OyqRV<5I5SX71ua
z9_Kk;<!wITGsa3BX)3(`1kp!SR5GSvCgxy17GWt?V0C`Ly8MET_!FB)jO@Rypfh`M
z0EcrNr*IY*as}6O8~5@sPw`^d=>1<8+~p%iB?&&5;xI8&GCi{}Hw&;B%d#?SuvQZL
z|4i^Tzh@J+Vh46(9}eayPT(}o<r1#urX=>iQ*eOCc$Qaqi}(4IF<%LqiqE7>&5X>>
zyeu4Ylw^5U<NK_``fSJ_*^F)2i9Ok$!#I|q$&Q&^z~x-Wt=z-Ec#;?RH~-;(e8HEK
z22CXj3`M07q~q(%#Wz`$Wmt*t@*{rAulOB*VN14;HoX6?g5Dg&ksQydoWsRj#f{v-
z{XEJuyv&;sBm4hX@PscV3o44oSNJMlV>Z6QLM*|zS(WecV}2esdjH=De&DbCjUCy8
z{Wz3kIEgbjpUb$GTev%!{T~vX;CWu-9X{l9#!enIm5|AqmYJE8`S})0C%6BKf_L~K
zKjD}BmOrxv+p!CO=Rl6&AN-TELykpU$qn4jeLTX`yu=&4$H$D3B4{WslQ0!S85~)e
zhXq-j<yeI^S)29PfQ{Ldtr=qXz))0Q!4Qt-L{8^CF6A0-<}M!Oah~H<-sXd7!~1_G
zh?O#^Dgl!*4KpzZ^RWm^u>z~}1J>miY!orF|DOcS*_NHzivu{E<2Z%0xR5Kjp4+&W
zhr>qi|CHb&uk$V+F)CHiP#h*^N~UKP=4JsFV_8;CW&bq<wfGso=J#yER_wrT?8Ctv
z#R;6oxm=RU{#Oe&aVHP(7|-$wZ}C2#GUls6Q}LOUshN@4Lyo*G%#tk6YJ8t{Sf35~
zBb%`eJFzGGGc?RGmXkS?3%H!?xRrbO7f<p6|K>mZk1qm4Q7@+ss!GHZOvl%mi*K?h
z%disP<wyLKU-3Ks5^Z?@Ed}k_mAyHLBRQT^Ifsk6iW|9u`+1aSB1ZOqS#Xp8@(Eu`
z6EqZ$ukcmA#%z3pg;;`bvnt;U8@>OJ1)uX9{=i@P8#}TG`*A48a1v*5K9_NA8vEZO
z*v&&c!SlSvJABCJjGZ=UDj}0IEi*GG^QX1{w*;kGk?-(Be!?&LEq`VUwqqCm&Vd}k
zKSGW_Ih%{Pk{h_4`*?(>d5Jf8kB=E6UC>ZmhLSi^F$1$Q4-2w5%drY;vNr3n0UNU^
zTL*@sLW1t>%OM=iiJZ=PT*@`v%w0Ul<2=W!(T4YbTkwF-7%P2HRRShs8fIb+=3^0-
zVg**`2do=0vi~mxjrbFrvn@Nb7YA@S$8id0aUoZ5J-3C8-v3^~VV>eeUguptVpN8p
zp*T#;luXYo%*_HUmcjnZ3M#V(Yw<IF&F|TSt=NIx*oT8TiW4|3gZ<AHEa7Ty;!Ymm
zF`nfW-r{{eWz5%trs6XxQ->TGnVorAm?c@B)%ZT^us$2|M>b;{c4DZfqd$jnEGKg&
z7jQY(aVz)mFP`KD{>^^^Ls9<;Uhw6NK~;&Eg6a4=bMZ|UWf@lDyZnfs@~ddW`~Obx
z3tO^1yRtV2aU{ocD(7%9S8*eEaDT+e{*MaI@G@`mUq0bWnSzGm@fE(x*O-lOun<e|
z?Xc1NuPS(tAM<m5!you7e`81XU_TD!7*660&d+53%LHq=g}Zr(CwQLMc!v-9oUt<p
zO(kS<re)^Lq2LvA3i9(UmS#o1!w>lhzvQ?4nJw6kUHCf(h8!dK2mj=3F5*gV;CAlg
z5uWBH-rzkxW+=w%K?8A_gsGT;S(%3gS)Aoqg*925_1J)o14B_w1+5ukclPBFj^;#8
z=R7Xu8gAw;9^~<8!}~ucxXRmnz-Nq=C1@%ElQ9i5F$eRp2ura7t4ECN{{ul?e!)ik
ziOt!To!N^6IGp1+g|oPjE5b(af4yKE_wq1L@glGDE*~)}YtT>}CT2>eXBOtpYX1cU
z#aNb=S%bCs8NcTDY{FLTz;5ir!5o#<{wD~gaW0o|H8*i55AYbz@(OS9KA$pXwxFr_
zAxBcCW=3XbUKVCamS;7-&pNEnhWwGu7;59_#GdTWVI0fJoXG`T&UM_%J^YI&c_A<q
z^|#<3{>K-5IeSo5BBo$EzRp~HlSNsEmG~|{iZ;CePX%A`JO09!Y|pOj%|RT=@tn#z
zT+CJ67%{T{9fJKl$}_yooBWqg_)?Cbp?G|Suktl!;~Oj#HhTXh1aGq{-{Z&poZs*V
z{>tCjkv-UtLpg?%a@hY2!F(>`T5jQP9^wg}=QZBpLq2EhoIz6wnLMZcrxj#oPUh!Z
zEX|61had72e#vk7Gh477yM!FSb0A0X5B|y7T*Q^!!0p_}BRtJZyur{t$79CG6;u?L
zNtlWmn3Z{0ki}V!Rald?SuZdY)j-ggP1%|uc4uD>;b>0ebk5^auHk0xiZ;CegM#Bc
z$E&=}2Ykj@xr3$>Fd5S@6LT;hi?CG0$o?w`s`CTZ<ri$kpV*vj*_pjKfWtYCQ#dPZ
z^!^tLR&YJHaW4<^6fg2R@A46&@&paVVPd9a`aJfZMUa~XSd3*^nKf98pYdyc&n9fe
z4(!H0dF+3%U=$~C8s~BeS9240@&J$VEU)ku@AGNM5%Z0ps`yOG)Xd22%*(<o$?~km
z_gRPa*^r?h9nIK=o!FE8IgDdDnKQY7%ejtQxrcuRhN4aiF7R*u!~gh#FXs)KO2iaQ
z$Jd#QZ?Y)Muu`<){l6>th@bK+e#c+flI_`*y*Y>@Ii6EFhl?Xd_P<K7kvq7bM|p;q
zd6WP0317+=G!&1o@KwIXY+<AK|AwFtOYm)0<$L^?pYt33z+d?rJF*A+acDmKA0wE=
z8Jy2$T+1!o%|krF^Ss78e8}gFo!|Zw<_{`M&a}+ToXpR+Seh024nO24{F2}DXSN7A
z+OZ3N=Rl6&AN-TExri&df!n!{M|hf{OO6}7$H$EEX3$JrCSfXOU{>Z~K^A8@R$<M+
zP*iO}JvLxtHf3vu*qwbjgrhl;(>aezxhC51{x=JD@gR@$9Ix^=AMhDt6$qM2z+_Cr
zOw7T25hMFAA}GZQtj-TumtU|Ee`0gCWoP!{01oH4u+jUUBACU6T*39+#=ShuQ@qIQ
zyvs+7Di|~rhlvZ?e@a1mW?^m?U@?|uW!7LVe#Wo)J)5u<I~274Zh}4>%u$@cX`IU?
zT+L0~$pbvbv%JDvA;*0_Wz0fBRq>gWshN@4nU{rGlI2;A@3Rg=^&JiQBb%`eJFzGG
za~Q{RGG}rDmvbGr28N>c2>#+pUf|#ShyU>fUoIRpm53>rj;}Kp-(=Bf!}~8IsKj^q
z5kKWu{Eok{CEK$rdvg#+ay+L-jO>4oU@=#5BX@8=kMayJ^Cti06TVa=Xeb_E;j3Yz
z_y3w88{c3dmf+j0%J=v&Kj%06fxq%Mc4Utt_TNu1lw&xFGdQ2ixRzVEn}>LU=Xs5H
z_^^omKNrM)E2t_VlQS(dGbi)&EtY0QzQYgs3BTmGA;-^b!FKGz-#L&Y_y_;wY%bzT
zZs2zAW9W$EG%xW6@9{BX6b%}R%Op(249v<rEXd+47Z{4FBB;sQtj7jy%%*J35WBN4
zhj26}aysWl8{Yp?!5VJnE*|7@p5s;C<^w)stYSe^37Cv&m?>gp|2YKtScIimfz|l|
z>+%aW;!kYOw(QJa91u2o|HB32IEAygkSn;J+qjp9d5RZ#op<?&QN`^)PVu0s#7xQb
z%);C(z+x=R%B;a!{ET1odp0R<|E&Za*o}QSn4>s>(>Rw)xSE@|lLvT=XG4xFyv6%`
z%9tgBhT=0RQ!^v8GcOCXB+IiJL+?B4us$2|M>b;{c4ANV=P-`tWX|LQE)NVvtrKkJ
z9{$CXyuiQt5C7u}zFabBDiKpK9badzXv6z|Q&5y;Sc&iQBYw)S_#J;?OSWfM_U0gt
zj2PMfc)?W8;bN}hM(*H#9_1Nc=1u;~Cw!??&``Xv(ffZz@G4(pHon0^EWx)~mGALm
ze$H?B1ApajrR=|>pa=VLD93OTXK+53aV@uSHxKay&+}R-`@bW2$mfh*I;biklQS(d
zGbi)&EtY0QzQYgsNyzafzva(t!FKGz-#L&Y_y_;wY%bzTZeVD;V;_(3G%xW6@9{BX
zlnEM&%Op(249v<rEEpJyDlRC;Dy+%ctj7jy%%*J35WBN4hj26}MjPJ$biq6><r;40
zE*|7@p5s;C<^w)stg=B<379NmWdCUdnV5t5ScIimfz|l|>+%aW;!kYOw(J}>djGuy
z12~-HIEAygkSn;J+qjp9d5RZ#op;OH|06+ExuBvrOw5!_&n(Q%0xZU|tjrp$#n1S4
zxlr&9zZW!ND|TQv_TgZT;sj3PTrS~iZsJZJ2sw`NEU)ku@AD~Rz8(C*<1;B!Gb6Jz
zFAK9IL**US_&)2fJ{$5!He(xhVo&zxFplM9&I}AiEf6f{I&S42{>78Lz`ywq|Kkh3
zTs~+j5mPW-wBh}~F380<S(Ig1iSP0we#)=-9e-g<wr5xNju_ehAi+qE=Ty$&Vy@yw
z?%;kN<r!Y)P5#R#VWao|QiY(RczlJg@-=4T8!W^Ue4ADI9zW*i{DwbNu>W5Lzp*2G
zupftV3@330=W`j?atn9!5KmOF|MP-tyu*il&e#=$rV=ta(=s!2GC$v9X;$PrA;*XO
zgkSPo{>&C^$1ePx137|!@K4U>B8FBvHgG%l@d!`z5^wMxA2UX!prN=-!c@$_tbw7Z
zJc5EO&T_26nyk%wY{15B%GM0AJNt4-wBh}a7EI)H&f`+9;b!jQK_2HhUgd2*;4{Xm
zZ2t)&NBHwVGNxfB=3qV+VJTK%b$-CQ{DO`66Pt&P-hW#`XZGR%4(B*d;VdrX3a;li
z?&V>g;>F7Le_e2wj~G=YXeJI5GbPhA3v;soi?J*#vj%HbvH#BmU-Nr5VJmiEH}>IR
zj^YGP<6JJ`YHkWScJcs^@hq?K7Vq;ZV^$5CiqE7>&5X>>ybKj~lw^5U<NK_``fT{W
z;_d|AhVp+L__6O?`&QO$MaY(fR3cG?l3h{?sR%7PiHbI~-S)I^v}jc-DrwQaP*I6?
zD$=4-|7T|2NB6Jms_!?y?|Hf2b3S*T&zX5<J~PjmbM84D&2c=PQ#hS7c_pt;Os8%Y
zxQFw(fQz`4ukszP<Qjg(4g8sZu<*f2PnC)d^<P1tI_t0zo3RZ$urs@}H~VuKM{+DD
zaB^gH{+}jrAur|CoWnbKFCXSYKFgQ*23PPSe#Z5|xc)Z@{L1{@k}fL7ELLU>)?;I~
z;6Cict~`uKa8Nh(e~iE=p2E|3HqYlJyn@&97T(PV_!yt&^L(Y7`hQ#C1Af9U`5k}a
z?<{mk(o-c_p4C{J4cU~f**<OJKpw)wc@&58IG)H;c_ydw0?y`DypgvvJ<r5Le1gyL
zMZV7E{E(k=9lz%<%-22Xp`t9qN{Q*zt^&Jp5AMab+>c#&DEo3Chw}uU%t=i1yx36x
z7Ykg@Yk4#8;{AM-PjLyC@h!g3)%=3r^2f-i{<jDe?2&X;36^73)?x$h$yVH#2e2D^
zu^)%<*kD}$V+6+Y44%UooW*S3z}q;N5Aty?<_mm{@Agpts|42aYi{IbrVdSds0d55
zB6ne3?#|}in;m)3q3XYfKpzg^(LA0faU##+xx9#%@fzO5J9!@;Nt<|*&+%ox$@lm%
zKj%06fxof9VM$LFXIWNZO{VLcXu_6k$NhOQd-6yQ<_M1FIG)ZaoX(kv>C}}1*Yj51
z!}(mmMO?~P`3_fd4Zq?B{>(pOL;V--nRHbtR$z73VIwwU8+Kr4c4u$)=P-`s*vP2<
zCkRaDG+xL{c{S(o4&KX$xscEDCBDHG{3saL|7Qa0xrx6rf3Kv6iZP3oS%dZ1m@T*u
zJFzPd>!tpW5E#T`IEtt6G@i}#c?qxJb-aal^8r4_r+caY=LKHj+x&o^@JoKjpZGfq
z9iH@5NtS0d)@DOCO`B-V_B@b>@Ngc*p*)T!@>HJ5sl0%*c@@()nz)_w_z<7qGklS+
zb2&fcr(DPH`3v*)PI{<lVmehupb~fGZrp==u`Tyw7aq#K9LV83fhTiPY^eXVz<Iow
zm-AZQ%)59$ALUbA!exAm?{hW3h>Yt0TY(?Bg$4U0T~&hRSe3QdfP1nP_vHcX#$N0f
zjO%}hz_A>|@jQd)a0X{Fn>X+_&gFxAoQwHFANBv5z`I<<wfveJxtXcHNe>laX;$Pe
ztjpcmoO}0G{~ZMmVh{G=03OZbc@ih`ES}4Ycp0zZO}sO0;yymYC;1#-=9_$vAM<m5
z!yot?3mlR3RB@JNx{8UKtj{KF$#&eI2eT)S<Y12AXpZCQoRXMMO&6HSD|tO{<vpCw
z1zg0Xe3kETCD-sPZio%_|Fgg!EPQ0rRi#*g)mev)*o<x1ft}f%z1g3`BBS~rDKM53
zIGNLUAur|CoWnbKFCXSYKFgQ*Mli1b6#^geGp^?*{>uFQk{&9?ELLU>)?;I~;6Cis
zPyKflIE+Vd5Rc&~p2E|3HqYlJyn@&97T(PV`l<iN1fJ&ee1&iG1Af9U`5k}a?<{mw
z(o-c_p4C`8ZK5HYvNhZDKpw)wc@&58IG)H;c_ydw0;Xr1xQaLOcFyBNe1gyLMZV7E
z{E(k=9lz%<iRo0n{z(@VWf@lDuH21#a4)vye(b_S*_Q)3oF~MF`afA<64N}77xQvn
z%bR%@@8_d@ic7eRZ}I)esQy<Ae8F$|Be$^NfTX8NupFzh78`I+w&K1#fZc*|{r3{+
z$00nHV>q5?@Ep$IEN1ft-p09nkdF^g|BD4);A?!BtGJe5b0ar1H8AO+A}q~{+=X?y
z`#|;ITwrf@<U#DgJ{-WKc|1?zM4rWSc@Zz;HE9z!@lM{yNBAV4<I8-L@9|@P&Tsew
ze`A3`Nl&GVn<&dFtjYRp!j^2u{dq8Z@<<Nm2#)5s#B}O(fhnBMnY@zM^H$!&`CPz7
zT*_DZ4p(wbY^eXQ1UB$z{=ve7lddYo3arjLY{X`4!w&4s?(7{I)qj71VI0Y^oWRK}
zoJzg}t`sY<I_t0zo3RZ$uyZi3|Ly|4*`LEWl7(1;Wm%bFUE&uq>oT(dP2F$BcI*@$
zKW@-Ppa(Mxa+Lc+ID(^iGAD8}r*Z~o@(Nzdo5JJA3vh?PJU++;e40!6GT-2GuHqVg
z$!{6HB07G&@a37Y(f5zV6Gd2x<yn<AS&w_LIoq&3!}}HDyy10<*l>L!HjGPRhcJDt
zi7_0{Gk6YXa2B(918?J8KFG(pm@n|P#B}OifmK|~uep(%naZE6K@pZ_Mef47+?~z2
zH#^3L?SGI!5BA{z9?j!<5-0L3p394P8L#0@yp#7uM)m)Qz>|EAFY`^l$B+3rzu^!3
zjRguMJyo1#S%o!&asAg9Xu_6k$NhOQd-6yQ<_M1FIG)ZaoX(jA)c=(N*Yj51!}(mm
zMO?~P`3_fd4Zq?B{>(oLsQ<zRlddYo3arjLY{X`4!w&4s?(EI}9LA9xn>I0llR1qS
z@={*SIlP1S@?kFIvwVqfa0SyJnfQ$Bxrx6re>nI@Z&E47ELLU>)?;I~;6Cicu8HZ?
zVFE{R5Rc&~p2E|3HqYlJyn@&97T(PV_*iV%{!a@$&sX?1Kj0_)lHc(s{?0<-{2cXE
zNtS0d)@H-VsQ#M@v}SuA$U}HIkK#}s#}j!f&*W5Iz}dVi7}x)e0=IJ>AL0{yhA;AU
zF6W2*l<W9Ce__5NNe>k*qW;SWRN}7OjeBq}w&i~8!b91Y138>0@MKOZqW;qY=ka1*
z&TDxy@8bP@luvO9m+>vW&(-`Q^T6K<{KzdVSTyOX5-i86ti=Z0ldZTf4`4U;V!EG+
zAv~62IG$(l9M0e@X7dK##<_fuk8^QiI`x9UYkZfhxRzgYBR4ZuEa{;lEX|7Cg>|_*
zo5zOjzqdd~9>gB(!vQ>+$MYmk<XJqI7x6M)!<!<b`oB})K0d-H`5a&7n|zNS^K*W~
zANU&!6i<4pILij(`mZ8Tll9qzE!mFy^I-PmksQns9L;e&ol}ad|LFoVc_pvst-Ocx
zxqyqfl&|s~uH+hi#SO*P|IY${uyA;a6CJ}#u>z~J4jZu<+pq&WvpajUKZm7FjO18O
z;ABqYg}jtka}Mv|y?mGp`7B>z`VA8+_z^$jdT!#c%wIC;p<>KpW!7LlHf9U%lbB9*
z66ngqcmxOW7>?p8JdJ1bd|tvUcpY!y-LYZ&KOpcJpXT#?g>Ul%e!?&L9e?8QEEJxn
z$KwH(XSK+v{%Z>~WK*_gdmhL`csP&ZP#(t<c`DE3R9+B_>wmVuRlJe6a~>b!6MTj*
z@^vofhy0Z5_&t9qrT+7kPP(Wl%dir6<!;=Ad$BF|V;3IEz8uKmJfXDuKUrWB(>#wC
z^KxFxn|T-S=c9azOSp`0@%_vLtrqx#-||OpVZky<PnBRfR%I<V;GS&7eR%-W-Awdi
zKMvus9K-QEgXeGtXEB>M@HWongNf<X;{uEM0$=01T*bBgnj5*9sjQ@jim)^*au?Q(
z4cmWrf#%$s9eEIYun!0DXdcg#IFV=ZTwcV>BBT1hM&Ksi$@};SpX76VnQ!tve$3DL
z4S(QoED)~W#r0o2OhiYhvaG_Itj{KF$#&eI2eT)S<Y12AXpSqZ{!bT}!s(pJD|tO{
z<vpCw1zg0Xe3kETCD)Wy|6d7g;LrSnh07&9REiZ?opsoV&De$=*qPngJ8hyrhjApw
zasnrF8ZYFfyqa@(2k+&>T*&mZCSKwjT)~g{8P{_Ye`WsiNe>lc7Avy`>#=cSI@Lm8
zA9i9_9>ya$h{tdgPvL1io9FWqUcu{P!}h;L;BG#^$M`g#=PP`hAMg`?$?y0Re`ld^
zy*?ffL`L;rUZ5Ilvmu+ZHQVz*9>T+U6o>LSp2$;qW-zY*sR9>pHm~B1yq)v-5TD>P
ze37qnIX~p5TvtK;e=qP0^Hof`s3^;@5_jcp+=F|uE%##=9?HHPSW*2C7dU|@a}v`$
zj~DZDUdx+#7w_kze2PoBER*;xf%mzZU+`Q0$So{bDe0*aEXS&>#RlAyt(e}|!~yKa
zUhKyqJeFfPo@ekJ&fqL&^9J6Qm`=?Vc#w~CF<;<oe3z@ZmS1xtH!~Gpor=n>2urhK
zY}o$02-M~7Y|g#ekq5B{`)~k{=J7m<6L}WTjg0F5B7w_z4R7L|ypNCYNj}Gy`6l1v
z$NZe%@P}Yr|Gx<osFHM5ah7Ej)?|G)VN15-{ydmHc_asOL>2WvT3{Sc=M+xoOkT<B
zc`NVXd@kT3F6FCyr;7StDX@lLaRYzmA1quo>8Vnz!0N2SMr_75?7+@x6W!UH{W**y
zIhGSRnbUY7FXh#o!#j8{(+`_i$Y=Qy-{1;<#Lu{%oA@j9S4(=R7_(TJH4@XQdIF8v
zg8Q%&yYes|!9hHRqj(BW<Jml)m&Atce}%wxyoGo30Y1j3`8;3Y+x&o^@JoKjpZI%Z
zRR4v-3-|GWfaO_@wb_tO*_!QnAP?c;Jc>hk98V0!^?$0snViZCIGb1TM&8bOe27o*
z8NSHZxtt$XSO1?1tmF6mh52?#dZ;MNuo8FWZrp==u`Tyw7aqEc`tK_+ki&TbPv#`1
zc^)t3<-C?R^Df@cNBLAH(Gr1We2edMHNW7u{E=H&Fzip!zEpzcSe3QdfayI=wBo)z
zfZf=O{Wyfjatz1w44%UooW<<Kbm|6y+c=jG@^LQa3w(|5auwI|Yi{IbrfMWTR3tWR
z|Iz{#xeM!ZcQ)tV?8t-IgMB!FNAq}|#EFqn{huXpE-&I`yoNXNPTt2y_#~g>%Y2jX
z@ne1-jO+g!fgkuA3)D=ysyNHC3Tv`Ho3JI@aep4no;<Rq`X4MXf}=T(r*jIYb0)9k
z^}Ln$a6T7s5tr6XCu{hsz&l*YHT;Sj_%r`t;aW+aQmnx0tiwiZ#x`ja9oU)O*_-`2
zj3YUg6F8aEcp)$4)ttlh9VYJO!(7N``4ZpY3Vy`TxSpH%EA!V*dZ-w)64R;50yS8V
zjoE_xuoJuTFdo4{Jcgrq3QyzNvFTLme1S`N1+U{Ryqgd3F+R=b`3m3W2mFLz^1H~W
z{(lnqorUToT~(6hS&g;XkWJZ|?Rg*%;o&@rLxXYsA181kPvx1M$_qG~SMf&P&Ut)@
zPw*MO$k*$r|K$Q7@>8zk_xy$V>Lxu@lx0|nyK*<~!M)g)`_&EGKRR7@5jd26IgrD7
z0#D{7rg<JO=H<MWH}fvupK180z*AhpWqgb8b2Y!<xBQV?Sa7#w1xv6Tt1?~7L<8>0
zR@|2dup4`^ABXT*j^TKo!E-nxF`b$vkj)!-8|U&tKF-B_fv@phuHssL&5hg~8@7L{
zUeZNHSeg~N3+r-sHs{{#$b;B}eK>$e^Z3Z9{!bE^$g_AZFXCmqhBxs}-p5DyB%kBU
ze3S15<NE(t;B$V%ANU&!)K7Y<ILopMYqCC@uqE4Ze;!<4{r40&l7l&dqdAVJa|)+(
zCa>i6yp{KGJ{Qzi|BD2c@>RaWm0ZKGxPd?O4;F5a^i(NUV0G4EqqK=;Y{L%h%<k;X
z{v5`U9Louu%xS!kmoj~|i8;K3_wr#b<g<K<Z*T=a;%8jXP5hPl8^%49P8CZgQdz9b
z8m!00Y{7lliCuXZkKiC4!%;jXHf;aX1kUF9yo6WqI^M#&`2Zi|(|n$<@NIs;Pa>oG
z|5D&P{>0x|s8O;rm1KEVV{JBMQ?_P%9>_y@crdR2qXdTXIG)H;c_ydw0?y`Dypgwa
z9v|Wpe5R55e^KCdF6W2*l<W9Ce__7elO8I{GOWa1xf}Q3Uc0ORwgUUH3lC*q4&-p2
zz>_(NX`aW6c{#7;&6yeR61bm_@+mIiGQP$4xtd?_TmHx`EVxI~Qze)#XQC==u>tpF
zEAGn!*p0o|k3)DY$8bE)NKB{B5tzYQ%;pWejdS@RALnAez}NULS8*-Bjt$#?qrhgS
z8Yf*;gr!-LyRa^IXLIh&jy#Ax*oOlmqxwHu;CP<Ii9Czv@*-ZwYj_jy<b8aEPx3jw
z9E|J#O@a6LF+b-w{DHr*K$E1WinA=MuqNxX30tyV6ZOBpz`^XvBRQBOIGW>lI;U_t
zXYxv3&s%v<6ZJn|U;!6#DPQF~T*)>3iW~Sd|6t)glb$NY3ap+sQHPD#jBVI~o!One
z*`LEWl4Ci6lR1s)3r$?gt2u{v@LoR5g?yGT@eQuvNBoTIxhXN7`c)u*)1-@vF^iR1
zgZ0>$Ew~Rmu`3Vb5gf#0V#D?yC2$H)<Jml)m+%T+$6I(eAK+trn$PnUz8x9W{|5q}
z@JoKjpZGfqHA{M`B+IiJYqKGnvNhZDz+hbehX@?bqd1hu@kE}=GdYzPa5k^vjl7-n
z_)s(T|AfFZe37qnIX~p5T*vSE3-dKkdZ;MNuo8FWZq3#I9s+x@E%##=9?HHP$l*MJ
zCvy_hJdYRi^2{%;6}Xvq@qRwar?`a6_!i&iYJS0Q`6IV5U2w0Yt4gpOtFjgwa8I`4
zzC3{4*o*x*gvWABVmdWm;0&I_8Jxvz-oV>9mk;uBF6Ik-jqh?*Y}o#51-|A+Zf2@Q
z(nCd9niaVV>vDHC=icndgV-Z7s{cL$19&u#=SiH%vv@8q;$^&sH}Ov1$4B^NFs}dS
z1YYKwe2*XVbAH1g_!|qfOnRy~%d!e<vOb%%RR1jn+Hrp#%$_`wgE@kuIgY1u3a4`>
zujKVD)&H#m_i#QJa1odCRldWOT*I%pfj{#P7H*aFRH?Ly3arjLY{X`4!w&4s?(EI}
z9LA9x%Lz<RHZhGC@={*SIlP1S@?kFIvwVqfa0Nf&XNl?5dVx*+mHAsIT~v%&tjrp$
z$Hr{Ieb|Xzc^Hp~4cmW^z%d-fQ+OH+g-eC;ORFr)@RpD`UX$SxP<%fO{bIu=k8Q{O
zd2nP@|2+kc<Y12AXpZCQoWkjx$t!t1Z{<Cl&jrD_{uc=><*R&$E4hYWaRYzmA1s_N
zS>wzfvsZAxI_t1e`23N$YnlmU{))YW`{9$)<KKr5NR162j20U{5G8gPM{+E;x2eMW
zoZ@z&(_`y~$B!q%b%fY3!io+1U~I12ESF7|dBBp|m1lU1N1UfN!xf$X?{Qj($BzT;
zc_0tr;XH~%c^psVsXUWYc>!nhD&ENS?Iz~&AwI!p_#$8Da(>89xsKoS7v{5Rin2^%
zI#o$vSMJ8lCmihMep`kwK#6-SeDHZ}_`uWH@Ihy>;R8-$hw}uU%t=hghW<ZK;9_3R
zYk4#8;{AM-PjLyC@h!g3)%=3rMn?7jqresx%%7}536^73)?x$h$yVH#2e2D^u^)#7
z<N7~VU<}9e44%UooW*S3z}q;N5Aty?<_ml+zxsbyU=`Q$Yi{IbrV1oIRD`8jk-M-i
zcV~0%&5oJB|365e2m5dUkLK|_i4%Di&*eqDjMwlc-pTvYCLZCFe2y>kO}@vE`8mJg
z5B!Y<3MM^OoMl;s>6#|$vk6<W9rx$K?8zfJm?Jov<9Ir!aC%}oHB;b9Ue8;359f0M
z7jY?H<vU!-HT;Sj_;YNi|33r@hl6-@elNuetj;=Y#Aa;64(!bC?9Kih#*vXx{f`xx
zz{#A(3wbH8<{aL^d-*UI@>#ybH@G4g*Z)TXpK(1m@mJ<Aob*sJX0bABupS$;1@~bm
zb}g*_4-+_ogLn)_@f4oMvw1!*;T61&xA1O0z{d)Q?H_IPrv;wpD}0+D@DqN?@Awmc
zXQ3iV-jXcOYOKwMnZN&UD$ttkc_0tr;XH~%c^psVsXUWYc>!lLeU*tDc{}IvAwI!p
z_#$8Da(>89xsKoS7v?J(_fR@jG?_@1VI}U$-M9z$Vq5OVE<BWdIgrD70#A+&+kcWk
zn&<IiUe0TIGw<U4e3Vad377FLzR%T>QT=}*@GXDj78Wd)>`WzCj#XKU4Y(&;abF(5
zZtN9|>%X7C5FX1=_HlKTVCEUmUx(4je2vVP8AXRDPI3G8JdimCx5@Z_XN_)e_ki0U
z+^YW<&G;{mZg)JmO-7-q@J+}`SN*%A+Z_*X(>rx^8+Ps;3~tk@ojJOV4()jlZo~H9
ziKE+i@6U5^8`b~L8{H=RR9=JIxc+zA=++=KkHKwH|2u1RyW_#F`rk>T+Z_*X(*~bA
zXLP&c!EJh{j&8%wy@SDRI<+%Lw^9A)J-7|qe<zM^<ND8Ya2wVC&Kun(^`F<^Hm?7j
zHo7&|%VThx)c?*J-R^jBtNwS==yu10+svSI=ZtQ5Jh)Bo)X{C&xpy$QO{aF|=r*eV
z?G0|n#Dm<h{l^>ap22fCgR_{;8+aS%@<Be%#e9LU@m;QpjOu@_z}MW!&HQhN;oDx!
z?qsmrB^cL#4}spy49ADKKZ2upGAD8}r*Z}}FGyVB{<XY`cZA1}50Uo@Jj{iBmM`%Q
zuHZ-fjO)3HzcRnkbunhKQ0DsoKfZ1+aeL<S%qCv3OivCq-*Mb}**@%l@r?iUy8Vuy
z*(7;ilz)3qY|@{a;U8YN-|;gWU7UGh6E2LzD_V*b64R;b0(IDk&De$=*qPm#*=hT`
zKa3+emJ^uSS*OMKL;qjs7nkyC&f(51zqtN)cKPM?dSG1tIbRTr4w;Lr`BLu0*8`LK
z&+&p_yp!y#*8~4r=3)CsYh2r!Hsn9Jf)TghVV%qSmom@P|Mp&=`?u<Rdu5*9!RvGX
zxX%CK1&nkm@7L#cd<EmbyMPh;KhM|a!oIPCD;WRX1&rwYpV#Yi(axFo6^uVGU~K0Q
zo97WWuK#~}i2WCjh)Ml-QXbKWBwFJ`*_Q)3oF_0d5SiqDrkc)k|6*Rw%mCzO_wUM_
z|L+%gluvO9m+>vW&(-{b-||OpVZnUKij`nFR?S@ht0mBYd$JYx<=_2W|G)dO{^=PK
z&*H!Ix&D9mWBt>q%^vu_{apXdPWjhkd|rq6u*dw3tJMG9G2T9q>mfd>|DAn|&+8B$
z*Z=?UEf`7t|L@*{5w?GHz}czC_>h0QhxoL2H2mFT{J;GcjC6PpM%)8=UZoCeu#+xQ
zr&AqWB+lz9b+n0g&PD35{qM5?d0eHAd+6V~NS!%Q#jmPG^<UNjqB27$e!#lSJR`~s
zO7nU?ANABfc|H->|9^iPO&0h+IEyCrzuKDq$EQ)}kZsSRnXcacIYIsZpO5>k@a*vT
z@wVRfeR=;^=Y;fj-j}zt$NiaMe>#=>`|@`7xIZ)O5B;C(`|?5={nK;8KOKI@J7-k?
z@qr-tzc>!W_5V+=>&>#$X7dK##<_fuk8?3!;A@%dfA0#c;#z*qjoi$Xde3}oR%!Pu
zGE?{4>)9Ie)XR+j8w<4HKJ3J<Jd8(h5RYM|Cr@$zG;Vj_$khM;=IU4I|4dhH{}7oR
zpmx#`GMzeA7yaeZh<L8U=1?vF&Ji;7|EC^k9lvK@!{+ET`>%|eqx%2P-nsnm93kWS
z|Bv3e92Wea9wBpi<8pHT|4-hz9BqRCbkv;L=}Tnl|9^4ljaFb(rv5WSu!(lQ$(+i6
z@RCYAo|vay<`BHV{inHv>6cBs!R1`VHT;s9D;z(#pLvNTGmgj{k~4q%QQjfB8f&v*
zVmej7NI1ZR4bm|({Pc?~7QU7@G919;cPy3)AJZM(FB85kFEVVe_zj5VQ>m5F{fenn
z{DMMw9i~dOU?E?8NDuep*Ac=zVKS9J{1+d}L;m=h(t-U_siDy?!UK&rLwqqQJm5v{
z$7j3nz;oS?N4a4Embw3WWLS`O?td3qG5heQSzEHlG|O7jXm(iDF#pzD%P>_k{6vX6
zho6FeW@is-o>jSR6h0_tc$?<k!|yW9yX2fNdtRn_w2oV|Zqxjj9L*2TIbZgcO!ICz
z!`n2E4%3-OKP2aT***5M@X-Qp@6n?xahc}P^OUXgWnZ6Z9$oy~8s6s7=jLc0or|~5
zm%TpIyl2kvHqD>Q(Y#mA`Lf%$u<(cH3~$qXWsc^(bIzB2ai)2noZ)SnZ_3fUZ_fF$
zS7n+<<BF~8v`zDp;eMv;j?6h<c9WJCKJ3lgZ65tyO{RJDa>dq%$)22P-alt}n@5i>
zKxUc`$T?s3E1Bj|MQzQxP4hlEnh(l3U-qu8Ed1b{;cc3a&e42G&iS&(WSS4n8Q!M(
zv>eTc<(x13$xQR3bB4EReqD~{!*kA;U8=Q(KPG2*o8}MYXg(t6eA$CC&5z9)-llo<
z_e7bVKQ8Bd+4C~ZN9GJ~(|m1?=EvupFMCU9UMM=+obYJXHd(*sD^_x2sZ`N$e^&Oc
zZL=zeLtt|287>i(%U<0!t9*8!wpm$CDumghXWCKI=vWqQ^Qc+$XMf?})?0MNW?XjJ
z&r6lBSY?}EMPJl8H2zigtx?LB;VXfn!i`e42|t;X(I0{3OxY^@;(+X7ZL%sv`(rqY
zr}hg!(QR7D5FPfS3~j?tCPT+<GE54;SP`#Gy4^M@mW33Lg;<oLU2Z8tKSZ~lVKjed
z@nkysKQxJNTl1N3+7G2t%}OWv+J`x|S){PPoAKwYRO(vOQKs!Be5gR_RMF6L(E@h-
zYr?JhE(>R)J>%YOzwI(DEL=LZcW4@==#)o_#UVx0+*54Ik>Y?nQbgZ>Q788ljf<2{
zHMA6&Ghnm_ZQWQpqg;hl>XO`3^a&~ENRc@U=9XekNYN|z6q`bdp;Bbdgt?{I5K<I~
zcbUI*XP@wmRnd#pQFms}hPkEK6b2|K<h~Tsij_`Hw-lK(Vs0r0R|@ZC%zY_J77yJS
zx-43X%vmwF6z!{oZ#&3+DO#2+ovLLiGH1rzQXCahY-gkP2`L&%kvTi&mg0<%;=On&
z{;WXT`^=Cc`UBBuMKWi|+*0(Zno2dv3NyKdCh=|Cy?t7#(y2-1l6;v{W{!NJHa+l^
zMyXWIZH@|l^;^x-sgo>I=De9B$JP{cb`P(_4$dse_KSFQ?b4}P;nlWi9Wy7=9QpoS
zraIxJxiPu-({B%yNlgmvqa2yDX^tFQmuY55aaQZNYvTVhOSf%5jh|m8b#{j&U*`0h
zBj2CPRBBPa)cD+Y!cE_mN!_WRhJ{Dl=4iKdnWikxml~M+YF!t;%j=}jG+M3Ud8Aks
zQjCfY{%+e_t&-oDNkv}`8Rg5Icyp}Qp9kQsFXv1B{x=dX+Y%NqJXMGiW=_R95^i0`
zgWk!Ps+fB>?OQA>)lWAaAJS~En+Cj_FV!LU6qgszN{y6aR30g=UY;*?TkhrlTZydH
zW1(rZB4hGM(P2eqd;g_YA1axZ3VTDGVr(8M=D(LOb-r2(vu*d}Ha>h&+s9$PXpv6-
zYra4C!L}>&rH16b1NA8zdM31ua*X?Hj;-70s*s}f-&m%FAz$>z&QZQo|C;a59q82$
z^QFo}o6>E2dt~<tS*bZ;z9`|u@Uy+Gzv`2Gsm8e<kJeTBbL*d$M~Y%$;8){stYe>Q
zA)j?T<FEPt?Dqzr<=gJ4B7CV{v(PqLt;v7Qv9;g(h7{Fu->KJy6q&k6=aFLU=i!i+
z`%Zmejj**W#gsf!tPd$><h}#F9a3B+#ne1fO!y*S>WaV7xua`lrM}a-=l(U{pPgIc
z>wKvuxo_}+b+S^^725eZa`X(b%zhTaslC_bOGRHJow;Rx*F8)`$F}|aVr}^5!>(aE
z>Z%#xC$kR@O!Bpew`4SLgH8ETCw&<XcWzO_=;yd(#;x;ZugX5OOID>3<Ha-cuUu6s
zRWNGcmZ^{EY?^a{8t?Y!cDp#tn^~YKVZH+4<B>D%KMvm~+A`j5*(<wbWtFP%QK{7H
kA<^tG!)4i<yJS@_wDyZqse0K}yJpobv@m47D(=z$2Pd<P=l}o!

diff --git a/Debug/Core/Src/stm32f4xx_it.su b/Debug/Core/Src/stm32f4xx_it.su
index 088e092..3b4c4e9 100644
--- a/Debug/Core/Src/stm32f4xx_it.su
+++ b/Debug/Core/Src/stm32f4xx_it.su
@@ -7,3 +7,4 @@
 ../Core/Src/stm32f4xx_it.c:157:6:DebugMon_Handler	4	static
 ../Core/Src/stm32f4xx_it.c:170:6:PendSV_Handler	4	static
 ../Core/Src/stm32f4xx_it.c:183:6:SysTick_Handler	8	static
+../Core/Src/stm32f4xx_it.c:204:6:CAN1_RX0_IRQHandler	8	static
diff --git a/Debug/Core/Src/subdir.mk b/Debug/Core/Src/subdir.mk
index f09dc2f..b5e275c 100644
--- a/Debug/Core/Src/subdir.mk
+++ b/Debug/Core/Src/subdir.mk
@@ -31,7 +31,7 @@ OBJS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Core-2f-Src
 
diff --git a/Debug/Core/Src/syscalls.o b/Debug/Core/Src/syscalls.o
index cefc3066cfd1b5e5025f6221849e7a1e31d02c27..3958a3599cda5f47878053cdf0bdd8e2891ca95d 100644
GIT binary patch
delta 11502
zcmcI~d3a7&+x^-5Is3^#B9oY9GGss!iAV?%5d@*cSgj-?A%-L*=JLc45+R0%oS;gz
zrmFdE(NaaL)v8X~qN=JjcF=08R9oL#8@+zNf4=Xp_kDG(`|Q2X-uJNXeID0kLxp;)
zTrCR}=ANMWX084c4Wr2)^9`fh5a(_)q~Pu>!%))2V=2f~<LeoQXp&+WvR{K?28Ue2
zyMkPm(U0WPWE>WR&BcOun`U8wm#Oj#O1Q2D>y@kdO)eJr_Av}wQ_t>LAaVj=2S2pG
zaVD#Jj@Sx}B-Zc3*>B2WcX?=ENQd3~p<Oo$_LF`XF+_Dd>^!e6w9h(Wf2P;C))qKX
zxZVuIcn5dGFvEQcu*U7FG4M-8cE_~*tQu>g+<ajh@}*KdL?^h=FIPh(_BRZBwjUyg
zAMnYZS9dM#=MkfQoG;@SJ(6Kp_<TWov(w8S;xTj;Mz;98&ykm%N%oNZ+oKJ`rHT7o
zea2Kc=+e}EEDx8hu&Yae`(`|ta$OD{0&DHXgR7hyh=(BeDm=K$rJeB*?7jvMwdIZw
zJcQ`oJmqB6!=;(~6wG+Z4Cg6(l34Hba0w5+6^mVb+(%%-kg+j%@YN5dOmoA7pMG$a
zKR7d8nmBe0H;k4ppGrh;!+N9k(O|;}b>+ju0aq97<I`#aLJFxp11kbC<x9ix_^~NQ
zo9R)HK)mPX>k*GxSI*jtTN#F>^g=vh))3Fm!K`h~Gnnw@wsN^yV!PSf`M{-7y{Ut+
zVEMo6{q=f#kTcq~UBj$O!zg>aQ=py^CU&|P>nwHcEo;woe&AY9tZ`m(ZRyo7#V|^|
z=!RTgVz`WSHg;<s-W!rBXv7^bSl4j5xXdu}A8*)DZ+QRFhU47Ao*Euu7^5CfKlCJ6
z>GLq|{b(D*<<d0681Z;npx$Nh<7Fef9xXGAON<dAbXP7fGF%2ae|D=U;kcW73sSUu
zXxL{suHWNb?T7OWBU$^39gPlp+W`B+Xy>|z#&UJa<JJCyAVtv;(}v-vmv-Y)CZXfM
zj@qX=FS@s@_euzsM*W*%FTK2e_`dL3e@XWv7G868SFUl+D9=Fgl(WBQ3(w=p7<6|x
zZMD2r#AauiXJ9}d=*8ygW7_K2TzIIhzK>?p*2quU3!HCxX0{uGd&6dL_;CEuY}-ak
z=8xdJja5r;C;&T{kLJ9ZsE`on&^pb;ht64b8jAbQnmPfE*W)6xxqCibWb=A_j9-Y7
z>CR8<#0#ghwpa6rD0aO)T$#1d>$W-(Hn&#F{S64l=F$59^+0)~IG^$garh6#*`|Ry
zDWlm!qKRZF<2wYVjK82$Wi+WxT!5QO88s-fGAaUz{ep<?ONqYCh^e@#l<{{D;;og$
zo~X1kw&S)@hNnKIMPu5#v^~{Ps3%YgWkfe2J`KN>(H|*MM)M5f6QhVn#}Z#anUrx4
zMODVLXc1*hLl%{Bu|9DC8c-Q8H6;2XT4lJS-<7dZ@3~Be(ReyXzG^@;3Y@dN8#|IF
z@!|IY#CiIKPrK4SQbCNxt*ne+^#N<DXz$G@)~O+`MnB+4+y}}ypmTGlJMF(}5fk+I
zaEMYF1^W1?ZnPIKCZ5#U{lF2<hsc@4K^ps`Kb5ghm*DU?+IOKxWlZ1~$k?4rEYykp
z4%fainrgR>FQI)$64#-lmGP-A<>E}*mJaVXUBtvEI5OKwtX$+EZSy7$(OYENXoqX;
zq7Ocyqkqtw<9l_zW8-KyEhDC*FO<<^9&wY7ucKZ$r!_~~>OAH2q`eLOtBh|u6OZQ+
z+gBM5P?3)Kr1mI1o)b!^-Qh($RV$+)mG)JwjAKc(hw8%p$BlN37UPE5v^(k9OVP9+
z=wf}Xi?U4%`~#iW##(uPzJ}pI?L)Y<3SU?#93K*8T+(qT_|Q(qRicb98WEj3b&K`L
zZEZL3<oG(h!!)g%;rf7QQ#f9#gZa5H?PQ&UT~E?}UzcMzd%<D&=$7cAx7evQY}a+Y
zrZvAHRBzOlSgG^WQEU549c5KE$8GJ2S0@v5wd=cQ(jGjTct#g1yanxxki9a7&DFNn
zjU#p_AI|HzGxeqcTCq(dIsVLYVh3EY%6L=fAXX<lL2KoxcBQEn<{@40VfdARSPf#N
zPI!rq{<9p8d|@MY??L>t7x7KU7}Cgg#4r01Kh~OWscUvwN06?QJVbA?LHBMw53byx
zk1yA;Zms6XSUqxF-wnO>4ks3JJXX8quTQb--3~=?{CDIZbX`ZYRCmFQIvn|~KQUDI
z=o{K=Z+DIiNh2of`o(Ge-_o(x=(-*eoV}>?m#)i~r9~b7G{;kQu|Ck<;iWUZv8&eq
zn>zVQ*YC<mE*+<j&(bfH>J|#q@=5gPtXq9zm9F|EJME`+nQChR_RvR$>E4Oy!P%Lu
zh*vd!s593$fg>q_TL0nN(^`6?c_Ez0)qQN!%CPb{a=I>Y)Ief0eY{Tw?T_{BavjaP
zI?DUn>ESwy>$Di%Cvs)^1mY20tUz6kuu6<LjA6c<sL>Mh*1kv9=15DOsCA2ItA@nh
z3y62LVg`+;ou@bT)0^JlcE*HQVxlg`m{GI`>A)K6{oQn?w`jp8>bt=amdr&D787IB
ziNo}wg}QCrbxeo#cJBmn_H!R%nU+<u*2Fo<k>UDE-ZqYQyw-et5$%Rch(Apw_Sbn`
zs@I2i;7E=GHBiR>mc&h3P<iFFUG$MR^mZT5=Sa#FV(c=a&nn_!UE}X{e2sKI{3daH
zLkr?2E!!hc(f(ZrR_IOJN9W9`->sOY_1{ca+My+uRlr4`mk@Izi07UlUeP0oT4IS&
z9J#EEwLv%4ex2$y2FKsixm=V*`&JmSTn7`R&swOjxK%pT;+b0iD|9N(>DQjqi;@Ii
zd#4uBFP!MAtMySS?Sgs4jau8=N7D|_>)(%|oi&}<P?x~2`>0B5;(lk2f3DSYK^J`i
zoWuR!IfD~FYH?lH^{%B;-M9<KNA$+;cVnGC-W^r98(F!;*ARi-_`ZTTRIl8YM|&AE
zWH%=EBZlkbuUo-=qOrzqT$@Jwwho}i4YtF$rzb8C;KUv+u@*U8+FJMY8Xd<mU7$KT
zL+QGCUeb#B8+V4?2+(magImg&t7kj=a{L`#xQTenZXD8XHAUg<#-DJ@Zv25f*$u}N
zxYg~(bMe}*0NRrq5Qn!W{xpc=-_|8g)>TZ`4Y^PsJXh=Ew|1NzID+`3&c`HOCY8w@
zR-xIjTMaQEj@peA5UkyJJCzvh(2D&|H^weq#kzC3(T{bAejSN}AWRVc_G~g6_CP+m
zq*6$($A$sj^2R<|(WoC+wA{*UMpVN|)ut|%t8eA#`k<>aycG0<{5TSHOBPl;z_;ZT
zf6(vp2`2cioG=Hp+_qyNXsxZ|<Gs^=$il#IdnIt>gD_yuF4pBATN6a8=9p1Pg!a?_
zawv?T8Fhi7V<?n);vW+a^F`h6cq$in*hdxOnZ-EYzDPv!qO25Uti^L8he};9@&<wa
z5T9g&{uX=ShANY(<3WpLIV7T1Nq^>GwY*4yua_}MtlA~F(TgK;DQ}JU<ppR>J9SBX
zIuhGo6}KP`byG~@7Iz)uJ`4Ak7|P)0$rjB(71E^%s9Fv!2W^x`P#(QUKz(eX0yCn4
zL4VP|=H517M6Xg{>Mvfvv?<JVuPHMgy<=}T3eR<BadpEEg}|U9mN@cmGSJa!C4{Cj
z=CWcFwzE4Iiw<;Yvq<JfheRD-52r;b%3=Ra<YI~TrKOw=BeX6rfbd)BQZ-LxQStMI
zTQ5+V*vIx;AQUgWg<?H-D;G^EtP1f~PtYRaaL~C*@c?~qUn_dju~)>)T>7f`vNmYH
z=*`ADAVyOo2gQmM&}-rkZu+_?;OU3N7OL*B2q*@<AvRHyM}#{|^`>~Y3UpL7Ms3wG
z@qIApxX4=sdP{sZjQV?D9D!5zYoe5OoG*{`1C_}SQ8~3h?&aV@`6}Nim#_1P3VELw
z+afuQPnGi7IM8C5x(c*J)-D27$$@lxsr;SsE|b5NfR@Wm%<Kwz9<6L&FB?_j{<WWx
zojvim!1l2ZCM#{@6Y#X$HiBudwrzo6(FNzGKT3P_(;*mW>opD-a}+gEaXTgh6WErj
z!)!*Ic$i7*^nP1l=MqNT<qu}I>q$D3vY{5R+gJ!h^>ysyq5XFy0Y|jX2WF0DGRKuH
z1dcCD0~XC?^G|f62gUcF0Z!iK2b|U?1~~nu2XIE63gE2S++nUbwG=d8EM;-aL`!<S
zP>dN0S|kp)167JVYIU*jx3dCOBAf>;6~)Z*a*^nC1_V3a8i|LkVlTsZN!)J;+Acy0
zKrf3mS)g;`jaHzm;vQviO*ndhu8UVPKsUtSoVzIkS(Wd_1-P$%5Hpz0TcUvJ`&s<b
z9CSzg!_<8!o3;jhBi~22scX`5FmcyqE4p+`URehEU49h-x-V<30R1H&@T7URgN$Lm
zEe~Zx{ThaWmfOZJ0By1bqnhf3?R*gE9ouBSaN1_2f<CmJZUg$nHZ&Y`!PdJg=quY2
z-hS6?&Pm+#Z(A4A1KU?D#~ibYiJfbfGzQH#e{q7U%-M{7g?YLRRBgWD4O(sXNC&Mm
zUt^Q5Hw^}Q%zQlubi%wi6ZD>WkN%!E%}CHE=8Qbh=Vn?c=)Adj9)B8KG;>$t@rt>*
z59q4-6dUuJIe`_qZob8I-!T1|uYb%Rb3qTx;mp%=<zEW2)JO?hqYklmpH&52KpWIZ
zHpoU*-5Io5y}_2)rV0Z<+f^m2wM%*9J%`$(TzS*&Q^ovQuwQj32ED6(V!NGGZ<5|q
zr+9atR$UqBhsuL=MxieZbykJZ?F(ukYkx_-)fDuNdY)llRy(t}27mk<<v{=Uqk#2(
zUi@$rmr;M-MvrcVM@_2ENq-2yeo5YL2KrxGmOI-W7sq1H72+u3wyzWiopXZy9P3Ij
zc2Z=ZYxMEn|HQ(m`~Bkvm!B{NA@%{l=9#>sTmFZ?Uc(2{*;YGPkT!~0j*{8HwzGLi
z>^>?oZe1ZTK86+T*rFb=Qy+}$bJAyI!N_uW#DkWL!)(emawU#cYh^MLrk<4}xn!MO
zVgo%VP0p>CcZP#D$o4$oWqGRwXotK|4caOH=E{Tex0ayS<Yso<>+<XQphNNxs_d{F
z%Rp*u7uj5UZBECKhyK`W6|fh){P=3aaGu}VLY&&y*KL<Z!Ft>Fp&#h9O{Ic9v9%Zp
z`oebJ1$5bVw-j{6HhMhhd)uen;V0Xq-k@J>%{zh?nw|LtT4Ww804*`!U}HL}%nzx*
zrREKOW0#rxd6h3W=ks=2Va{6ua+-asKr78m%5Rmqo_Aigc`6NLnV~758uK*o=hbE|
z=hm2UZ9!|zL<;p;^Ex+MXMV<1KWA3hLF>)eDaH*BGp82#c{7+VZZu=ZfnG3A)6-9t
z;1Ork4Jz_8HIaUQt~RsGU#NAg>RI($KhQaqO1ICeD+!=4)z<c)3o0DyRbMGjF8Nvo
zv!idSWz5sh>L!=`tsL7}h*JA@7HO{CBMbD6J;F4=_~WVDpw6F2IG-PVlmGuN_`h_o
z<cnw$<sxu%>P;IA91NpjTmwAg2S0u_Y_AP$^*Yk47r5WVd8+O=ctJH7RS0ZUItdsw
zlTJ4e_6D|;-GHrs<(lXu>MmwhJz&B--U^+HhXK39%ma4&b^<W1Ke6w<y1<OH*i)Yr
z;8?*j1WsHE46;!sE#^i(nsi&a0MG85C`|9=PN2`L@LBo(N$vZcq#EjPWr-Sm$J?Ue
zv01=`FGGMGUZJWw_MoeY2GpyM3yg||(c&h*wGkz`Ku4>!RBH59ysDRkJ(mfiO{wpr
zXWytCJlDJJ0}Q_G07mp}4s4ymq(%$g2=Tip(~kbUs}skK0e1c<ADHwfc2UWD`U1ON
z#yz4>i1}>}j96E8TD;>`dfuskKKJYw4D9nYwfn?bw!^@HDZs%;ndFfc<u`geui5d7
zSd<ATa4oAD?=z-SafY=i6Q458i^M|a|5*{~0oow8Hv_#Wk|u(-inmKZJH)`1Aje)2
z#~ke!FHZ*@5@~fnM@14}JR$rn&^yAd3Uo?zV=6und6l3~giEVO0r_v6hJg@QCZxrW
zy?`wfQ7s*8vns4o&7WpELVY1?6>*NAmNv`y`ysNa3(NGf*z5ETt?wwMq%H^t9r{YN
zXCb~3L3H{%k<HwEFTQIB`c?dh`1SsACn(_dJr)AvZ!>e9viW-F4_KHk&3RT*G`C1j
z2nTjO!Al^;&TYEc=K{MY5PLR^;}<q<Vrx9~@+<@P@$d(xFJ1=hJGl|CpF|DSfHu7F
zGEOoJ1B00SL3xzr;5dHJhTLW5ht_4Ph8^PUn4hVd{F!`r?9>Y2xTBD`8t*p(I3b_a
zDCmZkbg05i*1M=DBcHgIMVl1T16bU<F>p%%slcgzEcCQZ?2VacnZ;+4Y5`~Y(uvu3
zqJfT&mIF)0qT!%9;*{5;Y<cMG#Iq+e@$aRgTod7x-Q%c(x24x~_@h%B--b#~yqyH>
zG>x%!Nl62y1P%ah6$|l}UML&)gkdj3y7aT#J?`)GgjPj$f7s23vkomPDY2GgqJW`g
zY=W>b>MML7lNF&HEKREbIICKpVvucoc`rqV#{r|l(}B^|Er4y+VqjduQNZ@G?6LSw
zY?p+TWxx&vOkc;^x*NY>lXv>56xg|yj$y?h*h!7*0h2#^0@(FMj;9Rlz%q3^z~ZK!
z;xXNCu<3gg)0LiQM+4JhGl0F?c>)LJ(TTw!%yjlr9zSwFOP>?Nh)0Qqz_DAX$fBWC
z+r%@AfK!Guys7?F^IS2Oix!Axe0!mAyeh%vVzVEpLhNA{7l|KO+)8n(A84`I6a-o#
z&Qg3;Vth-`QZaxMS|$p6fL4l$5ujD#Pu8kh%t--RVoDgOMzpYlR*O%UfYyj~DrT*C
zg?WEg>~Qd;b)t|FJtqdEocL?^Zf0VG@Js-`D0ZT+)h5xLA#N5!nV&5pgIU}vBC<d`
zL=78qrw}tiyTlpRXulXX5OhGK@!W&rH1qeGQ1d{qi^DwOh?t(q{2vw3XaOywMhTN)
z1Vj;ov~Yv}{SF4tWTji4L1OjV$P^xzG86fDD9Kfnq{p^EVBIb_K#vaZ)E&lCea8Tw
z_NVhB{8^N&=}c#~<NQ$2$l8=!&Vl;CQLl~!=K6U9^N#b#(Vb&}V~(&k`TgOln(#t2
zuxKoQe@q<21D`=Y(T`72ytB7ZfTbdpXO@WtJg8DwRNQj0gEh582t8RVS~-}<^<tk5
zv{8J<mfs|X;if}!`#lMINo*(vZ5Ja}fnF9@SlgYVAw{-Jyuk+9EjpBg4hTPP_NzHi
zfPOctn}cdpS6(TvsJ$lWoU#uFomZv2|Grdb1@nJF<+DZ=_GsQLi|ic-ftJ~4vHUgm
z4RBaz(*0{{&1)xGz#ee|w~W2j!CAo8{AU&RHjVQPLq_tSc-W(cB4m5?M@X%`Z45tQ
zF?%C`v0goa?G8Q-jC-0@XzzH9yT`X?j0sho?(i$Mm~x{Fu-830HlU;i`1C6r8PgXx
zkec{0>oRR&DR7Q>el)0DEMV51;ugKML^@Y&6wwTDhv@AKdQ}9VBK8A9JAY8ndx!ls
zq5Xed=l~809l>Eix9!J-j^wytC^`xC_S3s2H>rq_X{>)(9!js;eN6AVOyuR8cBT$6
z<8x}fRQy^Enj;dkKy$@hwqK2y)ETr|9Is9H)`%2tx>0na>|YQ8%+-q`XBudy*vX4x
zmx$z^yG1Mq4~VX@po1ctvVBd&GsSO-mDJSR;(jFPgqV-IsWV~&J^f5nQoNswV>3Wk
zMJ0L$e_0>WkKe!RqDd<}-Vxb;pg+U}UN?8eDXv){FHw>UWeLSpE}e9=T2`|Nmi+Na
zP>u9v(3|C1R&R@(&v>`W4%0!e%4)j3Ury(pe?ZPa@2V5>YkK&OJQTq1--mKDU;IK2
zrn0}1uatu>%AX)7by?nKLtT|k{6XK#ut3lqIe~d9wT-9T%WUnK|HZbY-9Srhi<!I{
zn~N7{wQU&h@fU3a81^Px^a9WxTO5VG*VbSj$Z^zmgq|L=dE)24E^)xClupnBs6#b7
zSOx47lLSn<MqiRcX?MMn4NTd|@=cjI30NV%oda4dT)Kl+i1~ERDRwjP=fw$Li5tag
z*761MOFrm?m^hp9zavJmZtsd%7VM-rp8<ML9Aewv6$vcOCi$ilv{}Y5;ag<S63|wB
zI6&KE33q!*=F+?E(zyckvV3nKXotK_H+RbOQJ`J&a4pbod5x~^k=4Z@$6h&{lH4bI
z)`0#aKcI_W%RSMcOR{Mn&^PkihsAhMgr{$1JVo%GOkjep$U;{5stlR{x+X)|)z{@L
z=JbaAfSq|$=CuZWFWrJcKgi65pdaNY9Q?^4ck_r_@=somKg)e1K)=Y!A&d=wd@`60
z-#;1w{bo*mG#a{}8Hn#&2uwK4a60s|13T_uo)dQ?v8q!h*K|I|s>~NFDnVtU!UQc4
z<2*o>!i=T<7mM~3@DlNBD5y$2$s{ioWz4`balsRGPQJvs^D>A5eJS1MgD%O!DWDtD
zzZd9t89;yUNXZWUL%z-I-k16Ap!v3v!Jw74UDW?7+m~6OYFje$;c9ep#Xn9lyqt|<
z0^=i-i;BkQ=VX`U7ZwypW(-V^X`3>6WNuow)Hc~gMUg3m1tqx!CB>1cIpgz-igP22
z#!nudkCjdlml`-BJEyQXE;ci|4gcRZs%=bELUc@YT-&(FlET9A#m<Yd^^&k?OnyPG
z@!vkF(SJP_|AhZ~5cRqh<W3!*KeBZ}c0u8P_q2U2+s_W(cX`-OSJ&i}l+=vC=$L&q
zBdt37k|sHtIDL*c-*;r`SX=kVLB+X~iX(HfCyg&Gj_g*LGkJm*#DF0Kdqx%)W#{B(
zmgHtnh)hZD+d3tC(x}Yz!cmjQ=VoRU=9Ns%o|GHeEqCPP(fisuFGV&<?b|P7SVmxc
zypfsNqwk=UK54yEGm|sY17k4Y?AzIYU%%sByc;G&w{0CA7Znv27#-avrcHDpl+`w>
zeRNx6-<C6f_i^waqe(Zzh$iEL=}AU^<&tqXl#;y-<0#n||GD75x`x4j5GLyxMmsXD
zpmZ|YJeQ11Xcie?h_&P(!#GF|F^rGN_!|8{ZfUq1?r0zxW*DLSTL+6TYl$(ITN|-n
z6j|Hah<;+4b&phPrA30u_pgo=^@Lbv?TNx;jU}S7bc6MLwCE?d-m-2-i@tLAEvsu=
z@PS*_ind~kD7V~VusF~f29mpfvtEi3eTA2GkE2OeS}bUcwHhQpQr68_Od3`~JML(=
z7PZ4pKijSIU=d}7#pz?Glaj2H52-<WJPoz-NgJ$#AbHlqa*xNG*FCH!!I<3^kKwzX
z)}MT=Z>1&R@l7vlO#)VZ<YnCi3s)<l1NNwIRgglhbEJ4HtRvTYTQfRh?ImyPJ+SC$
zHAuv4k(Ey>wGM*hbsx*U6BqefPl6H0woaJsY270siJd{N)@o9qb%PXdC3FFeu_{Q@
ztaGF!D=Z0=Wlbj)Stm)QR)b_vjg?Odv<{M<u-v+Wrdh*CN!B*fQ0rb-5h0ST<|!fs
zr>CWemTFK(!`N$0=7@{68Y7~QbrdAe23a>#L<@QMbIYfjXdzlz3EeQ8Xk~-y-whUq
PoBmef<AMK)hh+Q@f?tix

delta 11484
zcmch7d3a9OyY^n|-RsRj=15FwA|Z*8IU+&GWQdsrMa)9YLt>_HL<}K@c(G&F8d^0~
zbwDXq)k*oa)f$RwDOHLNv|8HlzL)6roqx{x>zwOy-S=8+uf5hY+|RS$_R8@EYEzk7
z79s}jtygMROPgRAL03x+<7SZaRWoetwONLtq>F7S$W)^P4MU8|G7Q<JR&Rq#E>kl>
zuBvkvl8f6YY^YI!4Ie%;5F5NrHDYWL_myJ5ay36Kz=lB`4a4?~XB%t~n}RV8eKJ1l
z%us=js4}dysM(57&o02Y)st~lXN)^M8F!DvxQ~A)?zxtN@i6a~I6mdX_)ERVwYtEK
z!Zjia>&@H^!;JDBi#=}bo`YQ~whbQ3PgY@1oSPrUhFn#QNqnjc?Q%85!fu9PALI|u
zVFzro538}3<HhjNKFW{&i<KD|m-(LMc)8Qt9_G<`C01VY{e&x(&UAa&h|9wb!zIYQ
zMBgz62D&`sK9ZNqP@L)#?7j^XQ<e?EB&6DFn7GO#A(+&2UxJCdywnntQ1>;MRF^-7
zVG^cK^OTd2510Dxlkvn`<~UE<)5S%nhf7ps<0d%8*S$X;7;-`)CVqNi${aUL{Po0D
zo^uXx339CNYZwtOUr2aw!+xXs-=T&P>B`BI1y>iG<6CnKTnei`9Xmqs$d3cVBMSKw
z_4TSpKfLGW=aGV^u6$~LwXtDXN^iszPYtndHlEt%&BOyg9xE%%B3nvF=RYoW0yp)*
zhKhgp2k8Cw{?2&UCbfGmGK{%TPYTgbgo%@qn>dSIJIFt#J3n;|6!V<lyGD4g&oYc6
zZ<--1iVT;|&bn?5q830hW9#q)EY>hw&MY&G5l;`Stq=UG>cCNM4f87-8OG43kDpi)
zs`PzW_o+I@a5*{EF#12;_Qb57Pq+2=uG(f678(7+Xs)anZ@5%A@3{p^81CjCPKtMr
zZ0L(fb$NQKefu!O$k4XJE~A+?F4+FW+Y<N4B<{|7x;r2PQWVYc*f9L{)@*KN5SssM
zsC}sOvU`)jU&638?%xP|>+LlI_C-~DB;DVz@S3Z;avk7|^9&K~oZURbJ$*8<=<aUX
zs`;o!>zs2vLxNMF7n`TAY4ftV@KRe%U(Keij=!=Wavt{_&?F0e!)CAjWWDNXLLDW0
z^yj;ERm9^N5WUUIta|1hq{6(M&wAAtZ#!ps)fPWHE4_m2E<z)+xqCj@Wb=M{jenSu
z3!PthrHKDHt9v(S6wa!*M=7&iLkzqc+1wf{_tzm9n@9BjZ-MfNb>@4AIpnjr+cc0T
zWq8jgc1N(3@gF#*j8w!(89~*FXF3u~kz{3@2qBi&BZd_dyVfT<(W#Wtp&jx26~uPP
zv@$Go8)bOvTf*ydyho3RIL2|(L0=Oe#PJ%~t&B7jg)$0ri7kc_ca0=&Mw*oI5J^?W
z`zR4*3`G=`ak(aO=`+MvY7_n7tuor8-j(r<K69CN!*v>0F4ZF59^;(lQ`gaWA}3k;
zvZMNidO8MglyQ9ms#+Pp>I;@F;dsLcqN*gWMm;EF75afPw&>Vox8?XzHDUw3-WH-%
z##nv*^VuAiloRdRZFdLCOBr<_0%c@qT!Q*k#zvij?V~up13fCEH@`r}x&q=j9oPhX
z2$bQk%{s7{;|G%HL`5s3p1y4A0FJ-!PR#5?T-cRZ<Rs2s=pb$PA$HP746tz=rLl>=
z_=NVplUBe6o$r!l?s1<>T$@2moJ0IoUs=|H<9DKokvdL$wI+T?{VF3~t7OkGj-!_t
z4$v;`@eys&+7v#>)M0mcbKF`h<4|jkKiA6e)>mfh#J%pu_3>Ja<<E1xD4iITK)j`s
z6|Ix9aXwcL=(xIS<@x&=hC>+%_4%L_Usz>S;zOd0ue9H(z8q(ul_=wE9pbk-bme*_
z9bZLd)bb==(78N;4gt~W3x3Sv_>^|0C4UkaOLYv^_TjizF0n6b!D0C7k|@<j+|nA(
z(|P(rYyQ1RZau8M`B2BHxz=_=9fRqE__SM7;^&iyeYNT9W^kN2oEWN~4iD$}vM#*V
zB^;m8x^aX&%gKd6;w~M!YFe><W4SW1f*3xXcvQzANe4VuYvo;Sin|u(L!Iv~OSu!a
z0qf|1AJZazcL-O`+K4OK65DB&>~uWG$wqvpmC;a#_psLdq&8eRr9J4RgPf(0*raPW
z(1TAm>FbNMuNzizWu#uYt$V|2eZrynT#wRb<?37P`m~3QxPBk;2VK_QEY(#o-HR&;
z-H8RE#CNpSKKSLNjIBAurTS^8*8g4YYpKrb5y7V)>-eSW^!3!D4(P}Ac%7^|x{mtm
zNZ-rU`ai0J|8o&HeKweQK#QxReqpjMp($EEEp)?itI0hVbzUdhInLE->Z1jirmt+M
zYiD*_KHcA#7^V|+T1ReODp!g_wEhFMrPcI7N5lAFpRVJ(y*QpTjCiUBad958zP^5-
z*6?Bd^c(HX>)Oj3+UUMIicX9BAB-m!jUn#P$qLZv2wsF0htb=Q4@$MfT(s@6)wwcB
z3&gpQV^y2jbRO|Lt(c6_9Cz1;8v4+0c%1P{5;0PzBX20jJ+x!|9i|L79ciZ)Y^3fD
zjwu;@aKD^b(uvqxZ~9XAxCi-M*{+W>wHm(CU15fnRfg8YdC5I}P2$Q?#Cclt^|jyL
zi@9=P3UQ;3>r%acYBR2Eav%rF_$`81p#_z{fa71ah`!Xv9WLcc>||opGNS8B;$fZR
zTiQPt9S>t7*Dr+=w`$q$&<<p2gT`rr|E+gA^}Ca%YW;ib9`LD_SjVw^`Ir{trbZk`
zXfb}KR~BlCO^f6DIi0Lax~MkmP_Hq#epJVD@<5IoM-hv3{5<qs$90RFtz8{3L+k&F
z4#jEx+LI4by5MUcR3moNNBpL<eyEr$edZAFX>D7>IS$tQU3Km|PUFgR+T%QJ`X_ol
zrxn+a>2spA8}BvL`Y+c?KCi`fMr-)@N!&V8zp%3de!m-KS}YH+$8K~iAZ~*PcH`SJ
zJ=Qx{4&(STj<y>|x)1|&@SV$fnge_6#urmLzN{Unbi>$Tv`y!OIBmq8dVK6VgezgX
zrhm|W?A8fVIzm~xcy4IL+=QWaBR`RE&4gLXn5v()^y7LB?fr1PWjEZjh<%YbyKx<6
z*^R4+lihH1MOU{Qw^R6XYzW7bY7r}=iGe-2ezgX1kj`S3F33WC@e!?$cwH&!{kf;B
zjz@o;rk}B5H)f;Q>_)dr;x-s+H%{1zer<@J4z1XP)_i%7&Y~#c_$M#o;O4~55GDx!
z_1vA&u)|72xs*^yuDe+$Zrw*#?WnV!J0c!*2R15U8e_U+ySgfe*92Xc0mY!((vu3l
zD+^XRz`w}J0igS`4Fmj#>^&P)Vf!i%wAL2!^z2UO24bP_BL-k_izwibwam-kHn#zw
z+2)ugRaOK9H^f4{=?q(B-ds33NBqtHP%4Jd?FAwm=}={2Vma=&FBA>fC>M#j%*6(=
zw<Ts9#nK+2-^DwFK##?Gn4#v%_|c$+vIr7UD`hTYuv*r^#cHEWL}1k(xt&%Vku%se
zK9L{JsWR${I5HT=Ul(^F4)vqx&m;bDh#N?gdL**x+#ETiKB!E(1c6q`&I>><N)Mz*
zCm`6w5h`R^Jg{B^YNLUV4cI8T7})w}HkF*ojCA|K)2rUG*JE$++D30`hmQl+%V&yX
z+hhVAX`ex8D)&Fk*cgk|SuVn9(l(L7gAR#)Y!9czcBI4po9Kou+LnkrY~zuF4InD5
zBXEw`-4#?SdbJ156&qQ8^Tf{#*?h5)r!5fAP*`QcHwUy(jB?PpMdB9f-o92O(Xcnf
zPHufud|e&%mS|c4+AoGvBL~ElEYLx5bqwfj(TBGm68EXP!=hRt=p9i(O&$>sMuCos
zcb0(O6?KtYbxcHtf!-7O6wz_<Zg1-E6LADa*>8x$Y*eMvgI>&)Z_feElXtl|U+&}^
z3*<|@qD<y6Tnpt;&KAiZS%KxU`AX1Y`3GaXM5fd1rSd-gT_&#-fhuGLBfDIlKq=cd
zN}omOzxFe-r6;EIY@hk!;Ue3?RLm-DI~n#>w)+q)s^I-;Rbh``Lk|)jQI3f}A}1<&
z^(0_wRtT_J5xs3uEgP8Tnh0#UHx$_FDkGcu5sk^(#J-;069Q449s77`x5w$g{<TH`
z2fWc4IBEiY8vO;+G`>UuC%Dmq!W%PzllJ%nr<U=8X+L@Zr>ipHtdTsSL>yZRDit%B
z+__>XEuJs(o&_xwf3jE>iDA@gxd`~>dGHc3l@~1)BN*ihk>GR&hdN#zjLFO5ZUX2P
z@mFoo4&gNxv{TF*2s$tRY7DwAzNZXsh)>&seh@w9gKmmu6!woIfLXaEF2a0uTYSiH
z-W7eQje8;{9P~gmXWKt5`|^cvWv$kr8}f{Uf%`#*(xkic>t&$(vNkXLON!;7M>3M}
zpJUrf6_whCA&tmiuZExs+q3gPTW#Z!O?AQ+$iqIcy_X9*W&562oVHbq1$}N?83np%
zTb&8IWShqBcf;nG$U`678j=37eL<gQo23kFiCI(^RBGOEf|i&g>HTu^;9Sru^Bo`1
zYI9{L(0X$l!@JQ;YXCZCzBB}M!u)s!=wtIC?LB2?Xe-QN!!Y~GoEHhYU{0OGp9YuB
zzAG^O-u$g2=(?HD!n|R=!i@Z2`nChzG>1}bf1BqEK>wKC7^ey)i$RteEJ173A=d6X
zb*L3+lj=Mk^rE`f60}Xd!jjmob_RoXsM*Zc9_54g9BQv>%}%#Z4M2NPZ>jJ?(1)r;
zQ_x4slk~AV#@>BO#n92y>LHub8HKzU>YSQFvoESV=KhKjyy9E+0^R;jt$~7cBlDlM
z0D}NmUKMz~{K+bsQ8#v@s;*E~r0TrP#W&Y}MaCka|6R%QWV_>IR_Su#m5#{@vDG;{
z)ZbB7gtd=Eu1D4NKFwJWHO@XQaQPua5SG^+*kD%%Fk;gbU{oHCRE;+?Au)eZ2XS`>
z0ux5^lBDfaWOCU!V9I!Aw0U?SFf9}7+RaYGxO<?ZZwjbF{K=wRBa3mZS}R8)U}~N0
z%q{EXVjF0Kyf+oJQGVAKv`I$uf}OH)1ZbE1d=+T7e9WB(WIRQ4P+nzmye&T|1s#%C
zsj|azKOL#G)rkSUW^*`tJ+a4L?GS6hyBp7|oy+^9=fF>G>)W=IY#s00PWyvS*>YQh
zKDYS}2A#ECZ~=X1yH*VP-j+KWbj$XLC)}|e?Ew1OR@fXg-;ClHXrZ}#ENHR$7Yoy|
z#C)6jTWW?s16pP(+E-zYXLnj|PFoCen%PT0E6jD&#7c7!d)_Luc6*RzPR;^Vnss@_
zYO@=ktuYG|Kx@rN3U!@%hKH>;!&v(p%rZM@qv_TOw8>!(Vf%f-^yG^#nj!2&o6Uo?
z^b6G`2Xsb#Lq&e6`qA#M)N=j;Ijb%(tLIc^SI~Lo>;}4^68V+*T0LkAx~M{+UUf<3
zcL9B)JXz5{s+o+_J(ZFIdaNARqrt^?i%BZ6KO6x1*51f8!1(8>%fPE$n<w+CZ}NYw
zg8xbPN`8wXQ7*riRUKMuR!_`pC)dIp|HB8r8g^6%HvR+Q)wjB*;6BvALSU_~)Nq~A
z6M^+UqF)U{eSi^Nvw_h!xhFoIx=WlD2uvNvu8=mMH?URk9ANh8F~FQOV&{i7fVszU
zroJiIait?hA;Xsf>vdxe!;i#PJ#;Ichq?Q&6sFI7C(!pz*sT2SEeHDBnd6!dn4((s
zsEpdX*=<s5)(19wfvRfWmZrA2J*4WykTFS^hkwOyZKHt&Ku6=_RBHU^cvV}}a3NC=
zQ|wnY_p6JSRp2kaz|d0;V53D1fYHSaYJ3-Vgp{p|fz5MSb}f262W)w01Tg(ioT4)R
z=?u&~hd!cjNW8*NN>Xc9T8iV>I8fS-Fkrj#P+-TpiNLPsf`EC|CIfrE#UKx!L-`GV
zm<${}nMoOQ0&Q7McV)vW7NHc>Tycb9UMLC~|8*kP1GGu}z>sVajVFL!7JG|8yF~jH
zAjfMWnK61xR89jO5;<O=cSSm1JR#gI&<Ell`gc;qF%+MQ{6(P8MRwyVhXPhk#X?wX
z1|+<B2Vg`3vZbA^{|R=f2008zq#tCh8U=&^W0vvvL#(?C)3j4;aQZ~nbey83E(!+?
zx+KDMEeH=9eNAj&Y;K8qbpKaz9{%g|lTT2<O%vw>Q(_spv_X8mWt~i5tHHs*^dKIQ
zF*ypD>7NSB%3{p2e_<lpG$;YK>y^weY|idzOxpih3hd|+0PIw<4A^;69blI~7_#m$
zY<Rgx7=^t4Nx&Y%D9fIO>|njFG4js}hN|~NK7H;YRWo7&@~=jYK@qA^e?#JGw82m9
zm>xyIv159&7RPm%jLG;UdOqPClQwZeTVP>_y1>b4Q-D(jHw8|uU~SAe$0*KBuLhju
zM<bq3WK}p$Q~-;`<i4QU;-q&~v^;b>@tn&@{M%HNYXXe2d+c(sTY4A39v#}0+Ej9j
zbSgaU4f@uqA_tf?wma};F$-_$jdEl=4D53eE<JZkrV@NxXjNS6hH-;R<{^B_G+@M5
zDn4=oW8W~C`ik1fU^U8hP{ECZVXTU-&2fw$`%>)iWMJIXPQdsvy?_aSG4{#!p}?j|
ztg)1>ESJ<&=BimAhOc>!uEzIR<Y^a*fh|X9AKvbPaeAFVV8$~vF7sQiXT8{rY0BQu
z<hFK;0JgcwqHp^y<K6D~a9~bJF0g$QPhgMya$wI|jP#(TyngUzrhdq59y;_V=4a$J
zW@G$Hs%^r@tm4Ui>E4uFs<}jb5e}Ls>htaS!ttgAFA&@OL1p3&v$Rm$W^xya+Fe2A
z;=6jF#o`nLutaR9nM*}WN@$rl+!nM#>}K>=igxWmtHkLnkR|pt1XYS~J7~4|i1oZi
zbfRL`3R@~@o!I5zP3uJgJ=!38BAxip?w@GlCXvrQTf`RBwc08Q>Ebr=EaUT%c!8$9
zECL6Dc8N+B<Zkg3d+Z)@lsS4!l;nZ-i&nh%fH=kY9TY#a@ZJ`G@`fX#U;yL)t_VU2
zXc^UMFbRX;y2N@~xS{`k2SX<?(-A&UhTa<+I|GBP{fLL2%d3>6$Mq0kjhVPWul8Nk
z27~-&)OEiA8sEP<lQM7|!#T)t;#tt(9LjCT{+hs{FAfG4`1=5d9pIJ2XRyaS_lUU}
zkp@%Mm@DzX@%x(rCoJcMGofA7V?M?EypsYf7V*4uu9(S-7Kt-dT!r|n3&;{-v}CQA
z?qD1@ihVZFi{eX`{8rH#oesfm-UsxGC@%!<5P2&>J4IqPXt(G^k?j%H`I&iD#4P~r
z7lV1&uV$VA-8a8z0IF0Dwv;#2YbNNtitP!yphhzdU#oM1@xQ1BFh^zfcy^YB_MtsM
z%j};p{gw7RFjz;@J(}_L-hvXaH+l_S#@=}AEMPSMtim4SI?OO+EdRvA9@iNz+v5)*
zwDyExe!>#(HUcK~=Lt==_5&v8G7C)|2YGr*E&7;xk&m0*q!zQ9rUTpGrD5GiRs#Fk
zxbj>!I*^+10rN7ouoyU7EFKP8ASN>EPLak#ERn?>FNz>KxJz{K1HCD#JqL^S3vK)X
zLF*m%gF@T?w$Kh7654~qf@a%~3GK;yg0AQw1n#1BK@my7uoKLG!`G2|)g+kKwd%*_
zn{&nsnCk~&LIpQhfo6-yfuIsm!t$#WM_Ynci}$M2yfq?~hrTG{DErMKpRw8^x=aP_
z7Q2H$dqgbHd{u;Saldfz{sUqUWqVN6XNZrB71Y%GA|(!VLVS+AsWakIBIrx;A;tTZ
z*gYL|U3^H>Ziua2`2G7q^l6Og12M=S^t*V4?dA{R773asuTYZn<z9+ufh?n;t7JKo
zV9E1+K$Y?_X`2ks0lg%r)8Ch6_%zU)auv;fOOCTZ`{i3rKqq8fTKIu{7|ieAY55y7
zc2;g-*SaKkEC5}W7a%9~o&1FbbzKGpfNsfQA)p7cH{(=nJJ=O8*EWaoFSlJ{VJx<N
z#NbuhT)aW6Z7;EpZ?Uzc+goix^FVuTr4;sSHZ=$2c-OXrmL9YHiPY&72k%^lLA{Ak
zhpNA439!{{CO7>CZONF-apq@(fLUvpzRCS20?Wkd*`RXKgZ*Z?_?*T$#Wp(rf_QBx
z=tZ%bx!f!+jR2hx{hp`)ABdsM+lQir3HwOc@<1Pphb-Ga#AK#st9;W5+9rb;>6c_u
z5$I)nI6&LwK%VxBETDBeWZ81iPWdZO*(ER2%-u3D9<)aut_FHlHt7c1D@#~&j@M*g
zN^+lUSqXYweo7O+k$3pU6*;;i=v#UENiuGY$Ly+%p$M+Y1`N>mavU>!U3!cG-H^3d
z)j!A)jOk5zfR*{9+#C(MCEJ98Zp#kyK|e{a7|<Pu{F_(Yl}#ZAbx&^W5Bgb7=|$i0
z&-aB~px^Ixfd0d$RINsCW&~22jRU4uqdU#o+kwqjGtMp6A+Rc~1NXFipIIpt3l@Rq
ziZT;4PmJ;aEfN_?)PK1MW7RGeaScIBL>mTqsW`?6EE5+!LFeTSR>KA9L5IGU_bHt#
zvhQTjO*ynZ=)Mf5y$|Fa7^!}jdl}uo<Op|Ascn5v&<fja>VKu}gMpw`w&xKKS7VDS
z{y4>$;;fSx5}Va5KQ|BmIwdA#O&VN~lihkid`x^?O#FXY%O5{_((n;u3-g_^Nv#`9
z88J37f!ku@ViMvK662aAB*r(1OU^GEH*R!c{@@W~V`E~RN0Xna788TflYh&T1D$sh
zUH?xnOe~yMX#5{~7!dcrciZyhu>ZZ-?K_(Md}xcTX0bgA3nmuE4jD9Y^px1_g2GWn
z<HpApjf*aNt{{5MxN&1+r;M98s&M?EAqChoHoB;wu&5CG22UEkFRk|;SJ%#6a(m~7
zq@?WoZII>V*|u|!td2PyS`Wy`?G%!@Z^49;pnb7RN7~$4XJloy&JBrA-1p7$E3r=Z
zr49C7IM&OjR+ISD==jv6_=X|z@iB=p@gY!GLR{1Mgnb>(Jnrb2hk}!ChEYjIW7$JS
zU7aMOC)^<W7)GQE*bjeTN3LNQv&n&mv5t(^^Ew&jeUgmkbB&B<AW;{xo?(QL!we&Z
zjIU5GIl^!^CUAg~UHaB%^~BfJ#Bpm^wAd(4TAgA<7jec~Pr7LRM7s7?TC4~Z;<nWz
z4%6SPt#R1;$Z8!gx=8b$wJKh8meucB*UA3(tmFhSSzNPrC1CSR>oG`Hzi)L;6rIIr
zYkeYC*I7T2j$3I-c-Yu(ElI+|eCraYri&HR1SfTLv7QHua_iG3`r4pm{py$}beQzI
z<<S)M$m$1@NuJj3rg$^k)A}2Xr=3!;oabe2NWrwo`iaxJK32<A>}u>|Edh(6)}>UO
zQDj9o1C?5{NGq&QL9(u|^-Oc@ZQ*N;1&b}#;pTXH((-5lx@h$S$!tGscMERvxBdph
zk4|ZLy2V;gLJ&zqt+bY)nbu;`3hNT-xE0+BbjF%RT4#MqI%EZ<gHBpwNEfZcq~9!$
z4A4xgA8Dtxi*&|%Oj>7k$^^Y`t<MyV#LL!4nIa6g|CA{r)S>2v@v>Db3oEc7OGMy#
s0Z1l=T1&D-xXL?g7)j3fvwqgeEa5E{SeLk|(o)&jlow{jWQ&0R2b8&gDgXcg

diff --git a/Debug/Core/Src/sysmem.o b/Debug/Core/Src/sysmem.o
index fb4947e7468092d62b3afd2a527908edf3178f34..9942109c0c1aaf307036beb67ffc1c06e8dfca5f 100644
GIT binary patch
delta 6004
zcmcIoc~q5GlK<{~?|XtMLbD07qaq;hu_%Hff-C}2h$3zg5fCFS2nueA&eOO7ilWyj
zqH!CSv}=@zfMQ5A8atY$HJWJ9v}uVWInl&6I&pNmeii56>2qdIpXB`Nes$~Ks`^#c
zeH`C^EU*4u*80l7A3Ww?Crr-$HSN7<)h0Z8U-i~Bxy~b4(==i1^37lpHv0512;<e^
zB!sD#dLeuhTwa5P{!0(C5BJwJL#BJp?}xnl!Me-sWKFX*3SsleolLf;XqvI7(?l{c
z?IDnBRjwQ)a@1xyUfy?acql`J(@hV$$F7TRmlR8j?l!v3Ze=ze6mO^-MoZ?&KANU$
zinesk>;{}}18g$`%SHkFX90h60e&?aXxkGQLBZ(SNXk>!{x}6VSxwLb^5XfPb579Y
zP@KB9{#9UG6!1g>u$IrJ*kOIa2#k&f`osa}I09>(fvJB0{*`U2C}CaOt-jR*#MTWa
zH)}0ldCdpvokWqY#g7N>WrwTynhTSl`5+1CHx;;uoy;A9^)^m%VF=bQ9DqjF=MLaq
zCS!FF*6GBvu03-F9wkzB?VvRi;sZukZ>)=$$sCTeD?7VB8Tx;xGV5Bd0l35h+{|I+
zFy0W*yv3FWx?z2ZLyX|`0@%Jc2Xr+DyPtBBPwcGt@Zl?>CD!(gTXM0U#Mvh@ak*ol
ziS-A5F&5Yw2z2Ll5Ot=mJqZP7dje;0fyZ-mJns$77rb7Pi1mByG1ObL(ubJBssP|K
zXW-3Vz^}Rfuk+O%T#iz9*^rLi5nX`kOm6}A)cwBDJYW{vxmfvJlp*7wU&OpFO2zt9
zW~h_8%&2RZU6q@S*?N=Nxnhg`HA8{P+zwfM?iDWJ_Z;K6Fzhblu5BNJ^>k)AjB7T8
zqh7%s`~_zd$JsP;zdrJS{b+8tRF2d^ho;iXscq*GF|(V{k=XcvE8)TEA7k$Px#fe{
z{RsnXtUO*F%xQHDG&8vmyYZbv21D~-T$NO=;`t0{j2x&f(<mlQhiVhYvT+#JAMt_Y
z$yigugpad<j+}i8&)_o-tC?B;GZ){Jd5`sj<z0K=Y-Z&ySMi2f{mHhUwKwN9jGg83
z&_3hs30$aHdct(=nlG@8%aP9nUgBKmahBy=@a0`$(=rga-xc^KckeRJX&wjkE$`mr
zE?vZFoL8@Qb+fke7(5?=Q%iY*f8tYr;U+5O(vM~qTVH`qLOd{^Z#%*IEH3d(u7iIM
z?AEh>O#s&6JT-qCg!O+10{8sxkz?LxWzIg~#3GsLy_{-1kIEVs9N5bvbcfS!U}xJn
zh}XHqxrwm(f;kRnHw8T9hq)IO@5cS^n7jEWu4);(f08={hZm;-vzUV*E@eOFK5qi_
z!QFvznZOks`vM-em1?J*rOSS{S+1_xS*$zQ%>{nl(m9CR%!lrSvx!`XPWG6{RVwNR
zy&G5iID0=F2F)v+Y8p4pRlX;HBfP^m|H$)jC<vCB{M>C|vQnaWrhjC%in6i2n6J)a
zmrHrdc5(wO;46x_rx&Z1ZeG?(K2^ePGlqFu&yM%;kUi#58rdd~o8%4VzLksKgZ-}M
z_UPLSes81$-(ih~Tj+Z)XdI>h-{7fe=gFb+kjBr-84TyrJavaEj^ErG?(ar^J|=QX
z?U~r^VEbLn$3eEa%oo{lWxV)tnU)00{d|v^%l!*CTN^jkA-4DSg^gPVli$c0KNtYj
zX5P5h2kQvF=yNXaN)GPxDCiqFpmWUD7-rN~dD;h9^T*R)5!yl?pxKn5Ny{M)Oj<n^
z*QB+^;_NhTByX}YY3G>HnOqsCc<i2H{bKeK>I%&U(wns7T(LpiB(=fNU*`6Ezy#gq
z`XmKYDCCTLZq0BQ<?ykKq%mppIXw$8XVR+FJ$tXT{|talA-nvT*fMG9p1|s8=uP}b
zLj$+a5lT$go>N&(+5j$e0#nd64thtG(ZkItX)1Of5`89ZqY=1WE$9)D{WaZ5v{J*6
z&~({`v`jO5y!<xq1o<ZV()2FNkdBQ3K5fgAUt09)ghgN?ND1i%y3JG6!ye97D_ZM;
z>_l(<A}7<0`eSL2)_5wN@r$tDFaz(xRzvdt+%>8Yo%UKB$ji4uw-j8DA$(!jfmD_n
zyHbmCoUXl5aKA-(Uivvxwx(rbJ7`!gu22C?l_KLT8oWvj2Bp=aDwn=iiyw(L({`~M
z4YWi23ja^UO?Z7SI+4N(c|L_iwY0??ye$im^A>qZed&<a-xHOrlD81dCRsX;#BP~L
z{x~L|J{T<D-QI+Lbt=U%vVXmq*2}~Y6nD93#Y?k7q@XibihJ<0N*sVmrTD71+Uq#f
znt<n{MY!9MI3+Gpm+GfQ5*n*jTuLW#Ms(o!@&mCC$J@kR)ayfGM(!U8FE<ir#Tk5^
z6RxP#r($PU%J~Ojz%9$=pCMMr)UhO1N^fMjN)AK~D`hV$GN_VY4kS@6pTps5>4QdG
zBUhu4HPR7J-db6V4qhiOgM(Um2<O(zksxM+w238$J7gA>(R5WlwI#9AFs&Qytu{=d
z7s9mOaFK+*$q*buVyhuL<0XYw=S{fK)eT+j)<mTPv!<<L7B$Sv99~|je<SZxhnT*T
z(NvZH%>ft3RF6!11Vj^h)Ta{q9Y7OWI`MuCy@v#{yi~4}hs}J%_L&%^mO8nKt!j&t
zzsOXlo!qTgz(7Et3t^vmf-vwn`aSp=db@u=?3&v_eOL#|7!lEzaKH>qSk#Ab8SRLf
z7;*^qL#I;ZIJ8j_=)b9Zk@<RY86~WjLx~c7tK3V2sc(~a;8TrtcFW1c19eE=vLkU=
zjz(7>k!SGx&@2UJqD4Lcd8gzNRQR+^eU(J3)T2n$8M0p^aoq5PXkcdT{sz5+2b$2M
zhx)|1k9D0tt*;x767l*S!w&pKcGpnlN21fPXb_2?3`@|@KN~vGN~?@tQn~eN<If19
z#&`xntTm28o2)ZNIg_Y0)}W!*8+DMj!5BV?gfgzeA9x#$N4!bAZHz<(HW}?bVY=D)
z7}Hy4^v9rXF&0xN==DYqRq5g{@0-;j7Y}O}@Onk}z))S)Z-c$BbYIYXO+N}ouj^mp
zlCSl%VEr3C7B}C}HzLlP`Y%v^tKXw0)!X$7q;gyD98TiCZbs4%^=iDa&-J5lw8Yeg
zn!aV4jq&@d>8eV04b0x)Lmxo}2t7C+e1~M<qW+I)<n+)|G?F>qhS0JPLlhQ|ISc<c
zYFItuEIdcGW5fsTK@!m=;3Z~(`q0(Ox)8(-Yee1SccEVrsttt0V^R3Tajt|(9k5A0
z4@@aWbR&L1ccfmyooRunWBLPI!tCDQZ``|+3G@76pZ^qT6!gSB(=KEa{&4|vDT_d%
zXLqwAxOwiV<@`&&gl~!NV0fiCiK?v<VaTmgoJ8YPiCrEfszn%5T`jJIgEhhrm)D3}
zsP9^_4A-v{r*W=U+zBDEQA|cH-WErY{w5KI95#!2<aL5xCr*u~&n;p*=Bi%I1c6(H
z1I}*~FYHOYBOW57?IIQg?GSa~b*CupLSm12050~5ONelv=m{S7i{WZOPk*<*XyYc~
z2)>(zFN)P7o<*sWo?h0?$lRezG`%SyanwJi{>c=FDHQ)6VKU#P29cJcSrwWo?0X8#
z6#iQbVZ?W6oXCwB{sFm|*@4@J5=QwT_(27jw&;6!PGc@%cko~Ymv|5lMEWX(F(zj!
zVa_@$R5Ns3G<z$uThIs1xK#8<*($~Pu_Tm;!!4Udxi^X3;vFz`Sa^0P(I`5o{H7+s
z!8Z$zzD02Orv%4;T5tlb0#Tbj5}e3cflRbmjD6R$!GtdEpu)WX#p(4Q7y`eAC_<kN
z=)u4_AT~4vHsQTd$4F0g&OI{Q52<+_MY#hmy-FB#5vK-DiX$9$hMeeW2S9n&`JRMJ
z#Ee`LOGUR~B;FE#aU@YE>Ur?RHFQ+HXjLOUf<`O=D@|geFNtPR<WHhSG$NRDBBUFM
zkHw$7NSqf#VRBVGLJ(hxH_@Hf#EeW59b&3F?cr}7Nadv8zeA|cDw%>vD&=z!zDatc
zfi}xtu_Wr`uNfrv$)CaaeyJhYcja!pv5j(e0*RCI3Y1N9EN17ttU(MHWCCXQb9n{l
zuFH*SB--ULP;pDXX~p?F@;9W{AtxiiPB{lBewFD+Wr<<L01_(<6d4VZVJ>E)#xM@Q
zS#^e+;BSkeVgiXhhFgemuOVg#iDQOxFn8S03Cj-+!*TUThD7QK&7Nv&&@LLOh1Ivc
zJfkfMWo5-h1$h-krL)Q{Sz|{<MkLP7FHB2HHs_U<SrSWURTR#uD7PdR6c?417h1}S
z=e}M<mTIw2vTsRVL1}r^fZT91{)-5UhzyGfj|`8Bh_Y0amKK+*^`3qI#U2)V`TUDL
zO!Dsa|MFn{XDnIr=9GlaDxFmrT9}t#L=Q_r@!V;J+W)mO1*IkC@(TLDBr>9aN~vmm
z2L97ZHT>YS#igNjV4Be;Au%yI%Qrl-!G3U%Z;B<myl_srr66xkacQ|FskC5j3HQU8
z@ncgh<z;yVg}D`lc_o&_gpAO{ygAcyN0m;STU?l%RXV+5e%_oyOHyI}+}9i8C%Jjq
zCTC=3P0aF*j&2w?e{om$nDB_u@Tjn`Am8wCbEG-kml`M{Y*2Va!-J(0gXGu7hV+AP
z=ptHu{9Yzatjn?aVu7kTmMJP#J7KK~J&yI_<C(H)oBHf{hWuok@@~kG54WjV4H;sB
zYHff)_xCeJn93nspbo!J#@p44_cQ3mQ752!=R~G#+o^s!ks<o2p^b1=Ls+KT8#Cp1
zyOjB4hFGE&pUjjycdO6nBUO1dWeOWrLKv-Do9Otv%Dy>R{6WPu2grK|)RgAF`uFtw
z6sfA_05MV>ZVuFImulJowd*}6^<%Sxe0V^;Aft1v98JpD76<ussmf^SE1OoSc`beE
MA6_->k)pkS0AUA%X8-^I

delta 6075
zcmd5=X;4*Hwmy5Gdk!Ef+8~o4lL*LgFQcG1AcJBem>>>_A|f$3fQm+q+82xp;_NmK
zIJQw^B8dZnpkg!{6VsZcUo>hIP3#xj7fsr<NwiI2zxA#7x~l)Y>Po#IugY3$pMBO|
zd#&&L*5Q_yew0Ukl570s@VY~Rn}qp7gr+69sZ+wcduKmQldHXZYMLf24%d2<b2Q$t
z!C5X1Bqz*K>Z$NgaUO#R<8Lk$UmB=sdbZcfUk~MlBHH0rx~4f<gmAQZQ^@uVO|y8q
zj;0WEHyOED706zqR&A6cWr%nE0~sz{J-bpKX9vSMEtwV_91X`?D$257Ojlo8tl2*X
zYnq`cdSz%+JYZjPgl&t0ojw#cA_umYJM85bU^6^nW2hKITSk2v+W2v>o7E^IsBj_Y
zIqQm@S})kO!(iJIU>j0k*YMd4XRJT8z|KyD_3H;avoq{PH`u|ygZ-LgmQlloc1ztb
zg2dHzric9^r*!qlb}K<-XbB@>_wa>PoTeoYJMX2zdW?r%z?aM(g!NW#u`wL$r=4Ie
zzwXEJTL$B!Fsug<&W4uA&D|&X4Q;<Y8}2=}Io+@>VI;?Lof=<uF(3PH5Y2{Gpu@IU
zVOMflIc&ca*qO_bZ@0(#0+(3E?TzR7LN4gzv3Pr$n|$PK$3quRktnh5$aZxB)_L50
zDg#&WB6jAHqzvt|;jm9aV7++#5-HQr;+XPvK3MNzg4eS+db91&1N%!-VfXTlle=kl
zdU(VYeHVlmiCthlImK1xe>bPT!*tZ~mGwgqGsppU2*X>%nhN2!5i}}9C6l#-Nr@hT
zodwBk2gCl65elUeEr!<4LwPtx**)X&=5r_56@6hBu^e*vTs0Hu-yQqP278KC+u8@~
zHyC9bbJmBeexFJ1z}?KJ`7yLc)~k)ztGLD`%y%aPZ$Gee@z?pl6ow-5dAw*~CcL@*
zLyTP@Oa3LkzClNfoyY42V_K7hohhutOwQS-H+GVIVFxpd=d!T2aG_2N<D=0pVQT}|
zvc5mo|6mUK<YP?@ll>_dHjBH@;2Hdd%les7c3|>-825Pri2SA_><mUFkYhZo>Mf^G
zyEpgLpD)|WLz~F2vzVxuF*xSRDNZpRI~cSJ-0M{CvYZKD+zyeCn7IFR$9g`i_ciXR
zJ`y`#OwC<Z=>l%!oEp~7!(Pv#Ya4`^N}k~F`IJitcIue=7Z}Bs=dhD90Cor8)xi5}
znBslRL!b-Z*7E-OAgrT#Y67^sWX@Lm>y2FVpY7bR!5B|xyN6p{$O=2pGPunnber3L
zz?W_1A|^4#1*y2^Gsd{I7uGv@%D?4?6~CR&&Fp41f6uH==j*>K=z{|bGhuTWgD|GD
z8)H9m6!v>|fbEwJJD+Qx>xlIkwbR+^u#IC*t1q0b_8WXn3xD0JxQJVf$3Q>CS1=Fv
z_{IumsiZyjJB)xm%(s7Q!}>XHHIoI?nRkM?!mFJ5KF`B{g&{JVKX;!pSQ!a}u@&Y8
zTf!PG=hQiT<w>5hoh*R4oT7j=U9OI`_qBh(7*Au_yvR6x!VT<oMz){0l!qKs$Rc@_
zv46s(yYRiMSRO@P5&tEBnYQuHR3_b@Z#T!`?NOF=YYNsx57}{c?qDEO6Yq_!e*Dc{
z$@+fihMm#eQY-Ti6pWpXjK_YCxyXr}nVCG!Ffk1=Z*ra}rrXNpwy~({IDU*jVmz`K
z{D<6eL_D@G@r&RdSjTXp_T0xAMz=ldtey)x%V@pGh-N6CjzRWOBk5O!*2rgPP=lsc
zOJ_~(3Q=ilEy>84$3hxIF{XBw5uL)!xDLSE$Gm@x6+D@xvX1smZ67l>izRWfCnC?V
z{35s|AFeH}CzV2%vF26`L{JVNGpQw0I}(STU_#E+&Z)Z{eKQjn`(1qH2ZWZXRr$bv
zn21P|e>BvygmzP7^y7nQHMJQ`bP7Yzt{?UtRF;c}Ywz)R8%Y$K+IkD@bv4%|D7T9*
zVlEK_<TOLJp)GR?%?CeQS^>UEPnzLy3Vb{2xYKER`m>0xp=dj#0-%Jq2i#Fx)B_hc
z`w3+JtNa?;`kTzBjK)vWLJb;^r5pYttkw5`uPu7||Ku8445f{U19%hCp_Za6No1eu
zJJ3p{Wf0ZRb-5RM(IQ|0J};qe)UElNSPvK$i%#M6R4uYJOyV+OqZ`c{VK1Pk<>EfU
zW^NZBL8m)JETDWOuH)7=5sGS-$a5LwYNQk9;B~nZJ#Ute)t@?LMvV5Phh_36irFBG
zN08ekD~NEe$uAg#<$tRi*?`L`qjPM;75ve8P0R(ki^UUsX_kl#D08W}i+ifXUl39)
zeiy9vbna{aJ&Haiyqw7$7w7SnJRvH9aErKr={+g#^d|S7*o)(*M4$(`)1o_ie_!O`
z>5Mpnr?bKxO#M;pq#-l^A_gGKV(Ab~ZiyT`oZM2`4P92rnP9nEcD18}WwIm4tdVWF
zaJkG6BDX?Tg2<J!Gd_8%<WwklwLAk1*2p@XTPvRjFzcivjgq-TW)h9&CHdHi+){mF
zdwREA-$JT3*Xkw+*q~1eC$~k<&3Xo*-E9RDx(|nnJ>DhifULPil#*bc_3$jEaZQF$
zl=+pMO|1NH7ce<yEjo1>55~P~2a^qW8zQuZ;``C}E*i+mQw6Txjz=(fpNJY&>FOb_
zs?Dx}Vud>4>SaF<1cD}FsDob-WJ3-^?>&Ekwj;XXZPe$0-WEifFk;Gjkd50zQ)?ug
z#+8X#n2A1hi0`}2{aMpPW1zqBThRGh(GD7`m3;{kV~e~^gK2D)eiUn{;cgyd)5p@P
zPTq7T_l_I{Rlh4w;_pMV?1z~+CL?g+arrJ7J|PDWBiAAaCXm~tKR1TlVf_)oz{olW
z^rA(lkr1Kx^XenFVEctYT3^u*5b(xreFuJ#eWRZXAa_r1M)dc33-tVh9t0^>S^h+H
z8#R_6P{c~hFDPP_Whi8_+EVUDZjI&Rcyenk20&Y93CSa;ELHe{x88EE8@bmlv0z|>
z<vAaOZnVT;5H?u~pp(s(38Vz0)-qC6cL|gsR#n%<+n$CtKQ~5Vs4f|of!<}qA25Gm
z8~~zMjE+ch)zEOmHDew!e`%~oo!1R3Hg6a=N0Dna4q-TM8TST~`__m;(+`Xqd}G^;
z`?#pWY(ug|<_wJA*XAXa?jDl+sUJOr6`}N=1Auq<awLj)NF!%N)<H;7102a(|BNBB
zEySEfe+Lo9G~?!kR*ZPBuhB$e5pYQ=Rj1v3?TrAg|3hePz#pKOlp3Avz+@1gs-TCo
zAiPc2VKd%Bb%R==j=`TJXXZrkIOMNRWOKcN--zw`WD5h4dBS6~QIv~36F<x)JGlY9
zOfLh`Go&5Gy)pt^&T+!lB5~Z4+){BAtW}9==&f4(2;nRfH@(T#2pd{mF5IAt6=EEc
zuM}O8ca=B=w_5xi=hg^6=z6`#2N$o4duV@yn1&uUih8<rl(9)1e}Nu1i}jeRTCooR
zZV^Lqeye!ek=!<M2OVt}$pC1FxQq&SiZTasyTv!aVvleF<a>oDaClQBsyNR;k0Qvp
zNjL!SX5kOAj)}xxYMQ67eI+{Yl$J=}l<@hXWFyk44l@$}A7Ms)LjsZ3lG0h4X}d;+
znbA*@$i{pH;l$Qp_~W*sxA?7n$tH9`@x6*LZHagBIZbjxuf1(3F7+-x5JMKCj2Cmp
zlO21(j;)t}ftqKmMR#+9A;wA(0otm?IjBsD`M6`FI0zB%65D{(JHn>}xkhn^=r@}L
z7vC(n`eTC2KQ6fb6M`FP5vbaHUvML51Uk`@G4}1WaI#%o0EO316x_9kFWG=bkPy5M
z8VorA>LUXX6Wtv=#*S8Jy<&4c(3<ak&>eIEAD=K2oW<w$BisKZU1DUu4ajqJFR~S4
zTmiXC(Y`;qMdCj?liMV&@ZgItpr~3=ub%e~8&nE-o5Tixa?N6IAh~0r5yhMp;qA$N
zAnu^dbK+HmToN|8%c2SD{6f5(P414^rcQVV+GpbKrE(YesgkdGlB<>v0r&>l4FcLI
zyC##{B!A8#w^v31hBxKUIIvIN!XKzcIU|MKQF$I6G|9CXlymZ9)bOGFJ?8RL*$L;a
z$n}}zTIB)&cvCjnasIY^g7)sn%_#7mJb)8F%OPl`LSGz5Zi!Bn(J<+UF&iuO5%`<6
zNxu&KHtUlC{%-vyD%_(d^&xjiKM3Rw>-P|OTDK$h`+6#ALYqz8>Y9zLR5!Z%SW|oF
z=M1NRLt|r7XHO{3OiM3_j*7NLMgPlQ{`9G{CzX_z=PR2}dhnc*(%2Y;McJZaY%#I6
z_?Xz}cw0jLtg^DH<@pmzO07{*>UEzUza@Ltzm?rOwPb>IQc;n$aOSkg(z4Rx$l}5Y
zCD!QZsMx4zy8WO3RE3|1D)V*xe^N?p`Mh%NH(>sMkBYnPx76|PabI8Ix4BDlYHw?9
zdGXA0Yf<6MsdKDp#pP3Gl})$KDvO-;a&hFeva(X^oU)ly%BL3=6;n)U<gDWIS>+Tr
zVfLhY&-fu0$E@s}(K-H!iS?6{!u*}mQ&LmYbNr)Y>#vRW@U4IH%7S)2@zF_<(MfU9
zVgA2T?@xM+vGt0MA*t7|t{fdE`y2J&zWu5pHmTx++2WLHI5>xX&_y1~7I)P`vJccn
zUi%)-mY&;G>ESFHx=o!VH*A~gSf3@D)Yy6ize9G7Y9o794Lw4^JJj|gS(Nd+BiQQO
zkS+cHpjI_xiE7o_fU6=Kv&Cm>VPm!&uuFZ?m?geazDKjA_J%4wnkDwBmZRC?W!0f6
zn~EFTM91G!?>6-m^VGGbAUSxydfL>(7((BZ0u|OAB;Ha(n?sBTm6{f(QVzPR70sRG
qu>ER#a}T5YB5eL}z*XI#%~6Zg_su<|XSH%a*25UTU(+7q-G2kbM0}?J

diff --git a/Debug/Core/Src/system_stm32f4xx.o b/Debug/Core/Src/system_stm32f4xx.o
index 4dbfdd7464643c4ffefcc6acbe52178c624d0c42..c5140f03f77076eaefa64cfb795e75a84ce42d78 100644
GIT binary patch
delta 127230
zcmYg&30#iZ8}_?D+q>`YU@U{NuVb6BFJl`F#xlk>_I>P(8S|zj6jHR<QYuP|EvZx}
zi4v8xswlJ~WDVbS=l}h_&(H5U?|q;9y6*d&XFKOU=jrvfA@2C!LfrRkOM}!d(r*#b
zKeb#Wl8eN$#@~BC^P*;19i*b~)^j3dWBva-NW=<NM?u62|4K!Yj@ALFk%-wf-*6&{
zL>{mKN(obWmK8~4^3xw#5v%uLM3M=%g=8mVJbFk(5>`I@A`DpOLHis=q>;&&u3Ar(
zk#g8~wFx4r)zBUG%uXB>bYRDO7D>O=WIvILWU*p>Bvc}Cu_q^MBEIa|M%HJ_wciyY
z*;TPV6cw$-#WfO<?AlkUow%ht>XN=nox}q|Igu>+tJF=r`#LX@UH>ZmAbwCJ6UkD(
zN`1vQJ<rPebljQ(U7A?mP9hThD%M5FMY43Ueki25V*j3kNOoJS9|>u_*wND<-`4Er
zWmY7+Bffw@WXEt=hdTK-idV#6_dF|aE}r3;iDS5DoxFv{X&ft3Oq1v+Zkc$1XA4D>
zDI3;tBE^iaI;~hfQ!G;a@l`U4o7PB0ikV*}YomX~EQyZ%G!>ht!E*N3x)$O!ZRH}x
zoUc-A@o7(YMH736?m*A`s{28FbuujGf0g=*qtF(`g0Ect#U=L?BE`b5b%VvKm0(`<
zRT?f%B+JDT-F&ocl(=OiqFwT}?pLwnMTtnU^sDrnc&-AiTlQ6&F1~3e;PS67W{PF+
z09^64a<2Gy6+&D2Razj<Cd*Y{T`Uo=JOlTCeXUz99X5HANU{2>v|fC(2_sUh`D(dY
z95e}Gul-u*Aoi;V=en=bc9H65jRP9IUXp;gC9F(Y<#~yj&}aNfR%D_Ml<Z&6?N>-d
zEx!sYxIQ|WsN+{*2{#)xKYkS!i1bOz&JScg#LW-9QHZ3iSSiQJ`8=CcBvne}icd05
zBxQNIxtZs4uE#gYb8yj02dNnN5Xl;k(g3kq{*A=*C%*ZBhW)sPq$kC4dGlpbSpNTJ
zeiEJB+;)OoByFbu3iOm1<i?3J;I)ZSZhqtG&CeCPdA{TOh&On46S~<K%n|=z3YiRd
zH2(9S<v1qkI2>OWDR69EA;$6VcrsWpLxN-U8y?5MK9GI$8nUTqpxP~W3484ys$Dgo
z^x1(dj$`5l9H(5S<LJe7oa9IL_V+8OaDGCn5AO7P#2^B=<w|kfev<SbU5L)un!!;c
zAqO{pqS}vr$^DE^6ws!4I))7(`vJkku=xU^`lFL!^MW)1i|F^fF#4?@M%YDm3&H-J
zL$I*D<bKnAin_%ca<e>_Oe;T=Y0+}hG}}m)rv^}e_$5&fE!as69{FUMeT!_ue<Dri
z!Sp*ija+X1i|nse62G}4)&6meeh=zur{es4GMavrDs+9x{j!ln7gSG<eYaA(zu!Se
zhg#B<wIs{q8_8x)HU+UIjcS`k6Hj_4(%gDRweLpI@9FEQClbz(uQ?@+CreD4sCk?n
zg{C!`Ue?ml^$1n`+SrcN@kBSKE49OY0<|DCo#+z$NuOOwq4;Hy{r$zHAMQqBExAtm
z?;n#*ZVT$I)1&AZUr8Fpa{3*kCAML=BqF<9lx(Glj#QJI&?7`K`8FAekC9PaV^2(&
zOJK)cq?x^(+M2hcF^KbI868XvPk*H#?naQN<p>HZw}v!PjaOLIQTi?FMhsu#Da2_3
zV6cnMog~M<;pHV4MRX#fDLnOrV`KL=T|>XuPN8G}I<hQn)O$1r`p80b=QQN(j}!|1
zZ5sU^m_Z>fZ*0b{k7Uzz2D$%HLtYx<h^NC|vb3+oqe?EyyiX2h`%ql$9XiIvQYbl%
zH`0;!^m}D<vaBwo-(wDtO^iFaQRvC>qr*h^-!iHl*p1kV&QNWqFgojJ29V2<cpJj9
z@$@ZHk&V(mk%)G<laN1$jtiTU(eK`LjKeclE?SMZC+>n+stssEzk`+#sb~S!Zcx+l
z=XvD#%`OUJ;%su(WFu+TwIEcIhBS^Us_nCdu=hsLY4Ui{c>R|>CE+e!{<x|ui0+pT
z^t-u)02vF2C?=cqeh(YZZlnFBM#m>B$VR=D^fg7~=8qq!-IFjRk&BMrBvfn(^_*rm
z)edh<%<@Fy3{#2d`cIY+xXO)MW=^Audqo8PA)Pw5xR!puRS-qt-=wiMcKgL#`d#+*
z@p7B6YY&iR`XBVW;W^db3M7{=`_ZwJ6M0#;k@PRyke6jIIlBH!Cz9&CfsPwyQoO6T
z(eWod=jEb{TGD4;Cilx4&*g;P)V|<aY6oYh%PQPP8qevZ`DZt|AL&DyaRH=pbR+jo
zv&iM|95IV7Qtf;OwRVwLGC8Q2K*!HNlTmGB5NofH%e03?VRWNoO)*h#7RbiwFgeas
z(eHgK3UpX9Y4+cz-?3qYUCPpN#yfI9G@Xw2|ETu)a_T3|4f<{W?HXMUw((?YnnH2;
zx)AA!W@NM@g^c1FuM(%Xq#rz(T5xj()#mxp@mwkemn$M3(>-GN>oNV#P9&FmS`+Ho
zCTiZYTcnR|yaMj3$>S`$og9p9Nk;9zqoZvI(f#x@wYB#Yf-#FoU*D0yH`fs9)L%#w
zF^i5Vbwo7Vhkjeu5^CX8vJAdT*l&NN5IekY<iQw4F4~1*uw2yZ0NK~fY&?HAnv%<L
z8>s^YJJC%IBcdVwiRgZ#=4j&$v+5Sr&JQB+koAPBZbqcT!^lCiK6Ko!B%4Ji>3Db)
z9iJx=+q2%p7XE<TOH5=raiW5*|A)`1qN?$}{G%V4mQJKrZvRNXWpk)YFVqsOuJQSJ
zvz)*O50m>%5fsXiaI(J`MQ!a9OSO|@$Z>ZM(sykjo_XcurM`hs?2p8`bRkdIf6`h4
z9G*ddYl8^jaE1U)oapzM8ahsFd|&y_qaYTh5>fK+gpw^JqIM$cx#6=26|ssmp?e6m
z0@Ds$dZS726-&oz8|llBlCS#zz+)HH_NAy-T&81hS8^~UnjEB!qu(pnQ2U-c5ZHAq
z=}YGjMf-(B{dePYZ8wI83eglJX%rZeC`4`=8II3ZVK6H);gl&vhe9Z<FYXv$iXy^!
z9DC_74i(w2|4OkG9;9yBwx0mwdys>-jl+<wjn{#y0%K&+n|x|z!aWM2{tbbTJSWoF
z4HV+yO8OnIp<@p*S^i@p<}86M|6D?i8EPiW$M1<>o`Zp}=&-$n0It>KpjTfqeLaI>
z{B;~f-Ml?TI=nxb?)RV`@~=c2MRWR)P5WbX^qfm4!WK&o&NPnr27W`mwFeI|g{a#q
z();~D*xeR7PQ#!^Au24VP@G5L_EU)VV9=-#`Hv-+*N-&9@O)N?Y}pi6R8ML#(|8^9
z4<zcPe^AT5X}snK@1t&a3KpnBByYQrPSOu4m|)3Qt*1-+ucY(n+toKmqfgd2ufXrM
z?FVCEP1dc>+uOsWYvD?ebo2GWvHO%hsOX_@fqv;(_Zw)Ai~qz(ve904t`(Y~aHU}l
zv+!FmvR6W&;r7YJUoBd8poc=cT3mAqC$WNtrrX5^+(L?-;^VRC_FdxK<~Yl{#Z%Nk
zxZ1^&TB7mC#L+ZB@Ds-u!{)7c@KA*HN!;Zs$ebnP=D>8fWWxvqe^6qkmyNF^<On1`
zN!PvTi%3bq0^kxQ@11~4lVrWd;GY_(Ij|D?Z~D{tw&j15!Pa%O3-kj9Nnkj+S5G?v
zTxnU2qnlWRX^1>n{AK|dFN=q51|~z?<}A+8Yw;Ve|8)UhJROYM54g<~9gUf2W~b)3
z{S=)?ZpF#!GVLGC)4S62T+wYT-g}Df^B&=}_PENTn|ek*K+HcBA4cEy`sX*q(c3=Y
z3Igfl5{k>DZ$ko({i5l~|6>5X9)`VjMD3U@J_u}*40B@nEcfqVvt;!!5UqLsJ!&^E
z&_lmXeAErC+bND+19DGs>w1uQi%+w#2oU#>qX-vg%fNY2+;uvlz9eo8-X0@v3_n)f
z7=N6&u>qIGjV*{5Q`m}Y;>MOFiK!`#-O6wIfKD*w=iq4TL$Ng39|VUj7e^z~HVx<s
z`S<@cLqB#_PQkJJJP!bSPCH8No3tFk3|N;A&7d{*#RzHmw3&!~^dK68j^8H%-Q<k_
zq+eZGI%R;eSyU&8-(~fLllBgqaqM-t6PyoHra(VBh=%r)M^xeHAihsSm2Kj`J;38A
z?l%jPkNEH#aQliMIwP_};<5DD3=nVs8_z%a32|f{fPvzpxrib{e2{>V;?{NWdqzA@
z2{)I-Ey{t95f2N6Wvuw`q41h4j@b;rb@8SPuuKtG2cjwW#DgZoBuCsO3x4m5i#r1T
zMBH@`08hmqZo{%dY!_hpMtmn3&p%x3b*<p=op{nVXm?0%H-V{(B>Dp!?v!}zp!AaT
zL5@f6Eg9ztHXliOCc+Pv6dniLNy!VEQk;?mO#$wrr1d74L`x(a5XB|QlsH6~B3VaM
z#~YIGKBDf9<nkvJxstWtL1}*=`H9Y1u_TS~k0c>y(78_}n_fezmTXj`zuri4)}S#C
z((S9j<}B3<0JupX?SSPTsTdC_xsSA20Z4tN-?V~dpmfIHundxhj6rc$8j%7|=cFB$
zfb*)<aV+51qysT7qW6zT-r~360DZTp8oyi5?~Hc0iQlAvfd50&@yd`7OV|fr!*l2%
zJF@a2j*B_*|E|SvvVTMS+yDJ1SUdfli(^+&dmMWhTLIrIhUSWWPvNO5|LHzGM+WwI
zjP4$?W(?vT&e>PO^p{k6Vf>cpfQp&S1Grjn=QXNVtRI5oU-FlrSj*<35pjwikT8*7
zR^&LtX}rQd7FEd#fm(J;@v9VdS&D2YILlYqc@U*DM`ptE74x(|Otx`Lzo4o6xyT`~
zyr3R^nc5$x_Ns^H{aTkvkPc{niTdBQA0fV2i@*xSyQq&Jh^uXoip50-5y?aGO9S{H
zi31MfOqYrK1)(?~aZZM}gOYxsAoP~Jp*N9_q}?SHha`V~L0pF=IW0hTR5JJtieq+3
zi$u^ImrR-p(O)8=VZsT?kP&Ejpd@q;!i<u1ID_J%B$ehbnUWO;5Ji^c-xRpGC;8_E
za5<8Od%)#N(r6~1C)wT~$^wZeO%w_xBUd1%2a=h+pe&Y{?!&TFl0YeehZ6f_n$ed@
zhAahXx#Se3Tb@Xcy+LE1O5P8GvQkpG48SVMlM>L>NJjMlpjMJ}0^APLw)6nsCS6>J
z!bxgJQdPcP8b1Zm?~s0YhG1NzZD}5TN*XOd86u5Z40x6_EecY$bfTRDO^(#(0UX|!
zHV=a~PkNUI==svwG^Z<+c5aKJNV;M+iehQ`Lf}iJXVXwTl2*+`CzMHlKMCov^q-Ev
zJ(2E-1zCkO;Vz^~=?i-CR!e_h1?n2<J#zm{I^ZCr=hD9KX=Gm~Ei{1UrF3X#n7)?A
z(MY>q8n_?QTj_uGXxcmJ0(vWakSb}4_fg6gLHS8KQU%M;(nH8L%D2hBi$QxGWz{R8
zbe6rQH^2^AB8?b!%ElvaEZ-#ySb;{k%GREOKR20bGmU@u%KmKt+dkRrTmbjW{yPLy
z583R$;r@VZyc(tlWmN-E=PgtAK;a{MOH;PPvXf_Fazr+r@*c-zTXPYGpDdW#;xB9Y
z0CfSftGJfsK{C5Lq6n64xrpdb$&OP#CPe19LyYI&X<2xGAi`wbdIKLJt7#6lNZH|i
zh~lhFGYG(QvO*fQUy%Kpg-akxCeH@ol5E*L1QR3M*9B~GvcPb_FUyS0VUi$=p|BHW
zpJ;e~RThh(mHe74_BsH`vTO!XT$hb&gTj78Hv2BLsj{m{Fuf&9G9&IZnO=e7wrq2M
z*ks5`Pr~G`Ofd*FnX*v_5Mj3LN)}A+$#OFh+I^YnN0{WwrWydqmwluMb%Cs$vRp;7
z(GO8PkXd&irV`n{2DGeHmP$kPGP^804K(GlFWXQ&k+EH1^HgTfhl@&CeOoB2WIOUu
z)XJES@bpYp@fW(}h3u&sG<7nuC&GRu`>z4TYgt|q>fXrK>;>ShtkYVMy_fwk43-~c
zfw#fgAPZT7?)oG<>JJkKxqWmkV%sJk`4m7W`5#ynkZ+gge2dt2$Ul!mU%JTGo8Whs
z+$;xhx4fAFG;VT77M6SDO=rNxKKc7RxNw*6nF^eTeC=o`J>@AeF!7Ri9|aHIa)(E7
z=qoqJLwQJkVi2g0$R&1q_Z^k@JOI3({LD3U@NxOX-mnRfZ~F(p6LQxqxDS&5;{`;p
zyvG?xA#(LdcnXz!(1<=v-ZK!E;d1{tL>MXerAfmXd72W+^Kyr$puQmAM=#5Z@{GG+
ziIz7hg4-DRieNkNvGQp&3ArrK%Y;q5{K!V&6Xl6sz+aKip}|+KeBD7vdGfu1kP79~
z2LV?k$IXgog1l@j>PqC1;ZQ!57X$(RNIrv7vE_0nF}mxqyzDVdp2`*U&aIHQN<p9w
z3P}Qw`)`}#)BtFm6vvk!sO^f06A{b~#e#l7xF{;=^|4DaEft=2E8hMB?mdcsDYLLw
z5lM6V{fcQzq4ZGvlmt%)74dQaycB(CX6>UGpNoF-Rjj=Vlf#Nll>RuPV6FgnSD_ss
z#r>D5$e0e(dy1uHsLWC9n~d0U6=Qz_B2N+J45>h|oKkj$ijG}j`9R^+0aCG|`HzUV
zRB=NF>7gRi3ioA-4SH~wE1J`M?};LpvK3Di{TD#0RHQ|~q)PE*C2%#0X47D4uT|8i
z!qW@I7zw!R6j702d#$*13&47X?-`iBQ*2s<DBdelYf;yr2w8*{eo};CS|<OZm__q&
z2j)s0TsSgw(oyHcEXMp$9>JU>WhCSJ3Leff%AxRZj@fV!WEYsN=h44Wb|$DDNTZo)
zIS?-~?hO3KGQX_@O&pW-EtK)hSxVa{F#k?M-4*7`Es$Pi{AlEw#8mzUlVs)uB^y(i
z-Z@a-V5U<p=q5ADAAWB!cj$qd&b;h^y4%d#?(lbqu{Pio-ev5sf?<=zj2j9uo7qhl
zVh%H;7mEALF&h2nF?*^Y<ue1N=)FS5=_SH1VlWiJIbeoeMC(hKWxpe|hs?jj;r9_U
zxf%{1GiP@|dcyQM4VFr#GLt%=Sxw6qwanQuP(EX->>A+fm~9D&;w5tmi-_`iW>*1#
zZy50i*t}=DI05m2`H8N;Pt05n(r0GLU_{}-p6iV^ZDZ$B-qVR~TZurovy($$xr6O>
z8HEcw<9h&hvB%TlXg8~-Cb_YP*8sPN9iL!FxsUbQ1ygtS%NF20*jaR$c(R+Xpg72S
z$08Un_TwcK*Vv;2(d;Dlz+e<9Y}8sPZ?HeFg!@};%xp9}js0*Ho^G=(Ux71&UCO}W
zUDok8C^OkBBhbKXb{5SF@3Hw_^#03bSM35YkL^d(fCBdYTyPh%DtEXqW}Eo~Si<_#
zs>LH#LF33W_9x<g%!<oV_k>N~4tNDC3<h^4YoljiHEVi|w$!jsPa(o*tca2+&sh=m
zZynoy0*aUHta8eKzGlZ&BK&$bXC$=m*cG%0^q!r(91cISw<s6Wz|L+DwlA#93KR}p
z7A376xkEP~IdS!LSvqsc6_9ptm1!t;a@~%j5xcmI)d<Fw`{Ox0xN(mkA<(_t+5Ld;
z<9cJARBqqTeb@ofg9|?dnuDCL1GHY;jwJZ?;igj})0bOEvydZP-)OKM<$522@;K*2
z!v%lNl_okTxN3Ud1ahPAA?#qTp+7vG<PLkFE`%FRenYw1Hi#mOn@WSUaP9$%BGS%P
zmO*=ln@sn?d2RwNY+c~Oe+TzPE~f%TG#9=Yjk(X|oB~ZgS92341)TF$;ETBOFcc5C
z1(V^ogqzg~ftKPDg|dv>+!eTTZYGWOo^Z0wz&+)LP5@^m$I#obinAvVgtnGj(gilp
zxbBgV>bRs;II%Ce$`s&VbE%XSuIJ)u!ts_{UWwuzH|=LM?IY(#?i;v&rlS#`IX5ik
z%D-^p2*9`TP4|GzkzaWm)Z6*F8q_)SRg`3P;g80{WGCOk9suBOKDq#=uDs$EZ1(WK
z(OYRRzmwLG-1%SVD%;Qh?0`B?e(M-W2l%vUz<KdCT9|nAvyK38j-U7|l;`<$dR#^E
z-BQtA7x^HX^jzYLmm-Q7-jVK@IKGz@b(i_5yEOku;LlUuFOjeB0Q^;cy%#)P<Leef
zO6E`NfVj>d7y`>1{EHaWrShAeq4l@;MGHZi#y^-0DTD7o)4V%;EUmd^@qNf)HoxKq
zlsUXr1C#rFLl-#8<HuWY4)XaEGwA(S$QM%@v522q2AdLoX;Vn0e825z#UuVMO<l|Q
z*|c=?m|spqnJ4_W6(}nBWpkmd<fl0y&}x2e6qGf5Ya|Qh&-mw*qJGXZzk;le-*FOk
zFZnWhm%rv;*T7Ld-wruGyZjxWv=icc{!uqL{K!woh5>m4f0RZDpZTO>AinU;4Nz_q
z{-!k`N8zj<;U5wTXnJy3xIkCJQQ`MxFgYf?qF4KIA?!y);V<;Y?g#k^!JmehfkF|D
z_Jf5{QWPfzJ$0o$M6kDl7%F@}25e!%37R^E3zO2|DN?W}fbEQsOw-zP!X6Hu&I^Ch
zq%caD-VY`hg^{h`_mW_ZLVII`v4uEIae^)j#bv?cD3pnUtSc<92-T60t_e#iPn;xt
zp$vSAUAP;GuDKz!I0o^i5HbM{ZwVX4h&x@7&4YAXa6b&`j&R{Rq`QL71@5ziOj>}+
z7WBU%rX1n;KEUq_3n)jMCnRixlrQvZ0$icM()+qdh^8f>VxhPjOiG0I=Ye}D*asCM
z{6|9gOmLSA(nE;tvC!i-Y@P~j>GG-&{0zWX30-JKt6K00h4e`ndJ=5T%B2fXcqr{O
z#`IKf+KreFD0|Qv@<HX{hbX+1b6!E|t(?6Ng^#kyO#pnAQ}rM_tn{%@fp|puOou3r
zDsRz~?U=G9O@jTDBPf{T%A)Q7`YZox11Ui1b{U?6lnL(u2v+9Ma6d%3f>w<~m0f><
zGF`d$B}{HBGbu}(p*&1Cz#XL%J!S7ISNBAbsf>7!B1;*y#nZ2&-0niSdrGkdMUHag
z1r+y{Z+PHxmAxrxS*mnmp?s(uU53V&D;rLts8DW|BC<+luSe8B%6@;Ns8)9B0Pi)*
z(o__+%KqyV@Pz*@woxv&)zlI|zUy}%{o8u`WoX)DWMB<K-nQpFMEm`??@-b1FkLV0
zi+6&rLj(0i$EpO_baJJ+Rc9AkY3-tVgt)r8A!RP_HunpT-46}}LywO4LE1B!(#k*h
z4g{)K?m*c0Zh8d`=+m?c{C&OLq3O4I9@u_de^$UV;HO2OVcK8s2%-V~C`&rX`zDTq
zpU{Okq{JVlL*tQkmk*2W0LQ~Gc_XZ`*8b2>-+2qa7Z2+Lmzxt(;J{IQb_8PCBmQWC
zbVyvTftjDU>91f66yIA8Wr#S4&R~SN-ED@Rf%w0hVclTo%9PP#)QyQvgX=v^&uc*K
zWt!8wZy(d%4R!9!Maq`!XTGPLnFsSXjYd3~7Y7i*0cHec3=c9J{(;hq8ABT^ycwTw
zz~aNK@rBdFOcgCYA7PTaq0W!7JJTTUIP;Y9kN(VL>VyEM^(wFhF}meI1T)kAL1-tL
z!>3Vqig6i-x)7%S4=6&J;<<?8G-I0&zhTUdrXUSxx=Bz(Fk5+aL?n~{1E|k1d266N
z%XFax;5nw-OeoJY0d^@|Twok|6j98c-RPc+%*W*bMl)$N!@0!VqW4n_!_pKXmZ@Kb
zVB(nU0|@&vGust0#WPLfQJ27+c#9&D`8gWOYfMM#rz9pC8-p-N9+8H+>&)B1P^K{7
z4u*#t%vE2y{!*FZXYhNI$vg&N8uRW4xJYOA(hAmX=E7C<dImG76YzJKAEZ#;WyYyM
zlgW7Yg_Om#OovGh^M<DA_nCz`;LK%q?n05rEExdHd}eto6a`F5OIQ{%!zrIr#N^1a
zr%(QXkw1s~VrCKTUnpU&{);XxWd`&_Fb|nSEkN^#IYsBbj2T-BnsO$bGJubnM^n(W
zC(NRj@cWc`P78+>%v|zY$s|)|wTf}430*Zakk<KX7+Y`D)iT>?y7Y`$QA%^L=gh%_
zXxa;A`V}~=W0EO}|B_J+L=>->L=z%?&CI0r`+A1G3Wsl)hH5C^GCq{#{J@NQgyJJJ
zDIRs7nHYM;ePNPo!Rf$WuYqzKTS9L#XSNl2aA8kklc9VktNVgF`))RMA@HuO8*LbI
zV}A}n<sR1mIEuZj8+FM(wiP9v-PsEZLAsxPyAzTJyOv&-o@`Pn;0M^gbOjw`o2-Q7
z&4y4C!iP0bXuj<FtBBs8wah~iz(#n$?+I2xgRek4d*~5*D2RQq1*XC5BNjb-lJ$BG
zn^SCo3N#^XO&sb%*>#i~JI#v15K|btAs&|Dtk?>81iNA_Od?sU2+A|;${-YH**U*L
zd5(3w1l)Oc@c>8{*on))8O8oX6OD_k{TA&hiDv6%Aic!iWYM%3*5r>!W7&;$FpXo4
zH1N30_U#RPJiD3(h6(J)VALhDD=5Kuh3y;x=_-4hmYJ`yiI2gZ#LAsfm&^vVK`<$-
z3oUKlU|S9bSt{FXJxp%0ads@PVfyllo}X!Kr+c`o(%Dy?z;>G*@&g=Zu)!4J9X5Lw
zly}*YH89C!C;SXgS?oj?aA&g@>4AKY9XuMOIjsM8DDJZrzrZAy9iI;BJa*kf;PTmG
zN(&XRDb9$ZkZm!EM(#yyC%Rf5uq|n-UCgfBibzY?CnmTrWrur%`yq=35Sj#?Z3%oC
zJC$;4<*e5_SUzT@Dp)>Y^TQ!MWn~ettY90gu&iV~t|6EzcF%b@s%9^>LR}5}8_gSP
z*(TX^|2<=E)U(go@y~&O!Oo%4NFCb|TO~13D*YYGSM0<q2<<hSJ`a}lY%Dz?9J!ga
zitWvf{RftZxP!0Iro-GHH&Azk`?nOuQEoXs=Z<kVm4N$k^^I?J?*2g3`E$<~vbg^O
zxWRJJoZvpwD>0C}Mzg&jj-87lm}|WR#Yt}09N<rJ-RW)&;qHaPVJK&!JN-15Kszxa
zxR<UdBDs_qs5`^?I6^whx&8^0b6nJS2>U$ebqLZ0Zp%LSi{cW;fy{o9n@dYb(cCb)
zw=Z#>DHR#RIrM^QEcZ_(Ix&t*rIEvBZVZiW;<=ioh$(^dJB=cdGv)w(g>&wO;wq=5
z_rWzTGz6AOT%X}6lDRpt2<AFBieA+z+>E!NzQJ`E3d_`QxymR2Z*mvu!Fr3coP$jo
zw}hUy>D(mG?mrmqE|faG%VmTDm&xh+;oN0$tEM8dY)-ia=zCm$%1GpJsk8)ppDUm}
z8o6Ba&LGL-IyZx5KKK1%Fc)x<i@;LI%^U?~5x0Cl+VFs@=mS78XG}z030IR0%Tn&n
zXh;var*;QKU(TgX1lwb7Cp{;gaMSZ)^OV~@48RJ`={#sEIm<YhRB<kJ9aeL>v|d-k
zZ76|M%Ux*!lV_ZNN8p}w^JtII3-0HS0Mv0c324$wE@eHGueiIk-{LhFNsC(bTwk8H
zpuFLJ9}n$Y?npC`zT-Cbg7lv2twg7N;072G#YZlZa?%al&>ztypSaDbz<=gsI*@+h
zyr;vx10P2-z-@f9Bj9x8SBF69#J8mx`gZ=17c8CmWv<}d!FQhs78ib4fEc&PPCjTL
z`fC^8<pfN3^WV|j*p;6|y8ztyKNp~G58uiS4)^l+W5K<TpK=IzcYZjnPVMJ4XMywJ
z3&z6IlV45aZ!g|;E<Abji5pPo!w2pIz?b(p1LYy!_A`Px%ufWTU4De`poPPu{E<B<
zj`8y+!IK~Vl)C#kU)BkDf4=VuNCABDF}OIvPcwlgkawqPLlFOf(sjXn+y3x-lK+wR
zk)GmnM?nhVEe8-`DDO?9_|yE74u~R*Z{G`2I6s!Axb_Hs5ZzRf{PG?Ep5e!yfpnHX
zgzYAn__n7x%z1t~jcYFOoeCgD@xj9&UF0_o0X~{{=mX^?UP@aiWBB$j5MeCux)d?R
z@j+w3d70mE0?K$^5(Z@gA07wGM84ls)LpUjJ7~6cmG3+Yq}TY#G`&mWzjz~xWd0DP
zpRe<Y|H4xWUl59zZt!c~qDbY3`NHo_KH?OlTYRAfF4B1Mdbr5oyV4bShyRaq?{|6C
zZ1htmKa%dnEPhjOSZ4FpCOEps+v8{`ki$Pck7(}majtNf%d3=7=JCIM1R|dwI0(uD
z-gFN|A@2}~V2XIpE}(h9XH%-En4d!Ph7!KdOEjXCU$FqVhkQR*)IH+43e=VH9X0}2
z&i}9$%E$cX3$T2`PqHI-C4b5f9SWNYKH(f}D*2RVsI20pl##FICDXuG!~1MPn`-$H
zv~c{45B?L<bG{c9FZh1mXki^6KwDN`^7CmQ&MV%j6D(iz4+SXe`7$0XZ}`fdaQ~KH
zLkmUk_}CkC|Gnp1(~$ZDzvmAiKJr_WP}#tXDLM3sA3=*0pZVpKivPmD9D+IrA&FdU
z6Atc1KRF5~K0)au<kOCe?ZVu1ker1-DQmt%Xc`E=E<)cdNIQiiv|((QkVotLZi3eW
z8ScM5Lg9FbdxbbkhV2(TXguX1{PGL@dJ3Cp>A_35vjisILKHF!avz~9olztRXk+IQ
z;Wlj<JSr4#LUCLe^(S2T3;lM&VSq4f5jrSHIGP42Sdh_{%acN=3W0_SlkrHwGMS)_
zgf>iwq=8?!(1a3g5rVx8+>wF<%^A)JmoFliv%)6IVx1Ef|A9cy3rCK_@`BL)1lXd4
zCbXz>Q3#{tPPCBH1;Jbr`UC?IBRmL45i7h+MqQln<`o=W77o1wwLM-aJP$EJ$b5{r
z6NSphu(=}i9fuCSDil~@b4^$ufVw1M$_V&P7Tj%+t_%BVg(yXEJB2822o2rPGpRy1
zTHU)T#QY5Rw}i2jr%Mw|y}_9-Y^2BfZQ)Hes569Q8phq>1QXp(cZIH=SAR6xr>+9o
zec`8Fpw1O~_5dzVD56E<e8F=800qM6LbRn&XiGO-kuatgJUkFKY==p)Foibnmk75X
zz)`7?M;G8jVOA9Yj|9030xT0AP;#?eDDDp2W8qFOa6S=69R=A_L1~vGv<jh~wpv#T
z%V;-Um7v}a(rTfaMO}^1?kGrWg+<X&J`*y$0emjRmq7VKFs%fjPAH+x^)H11^!9uu
zv^K)wYhf#0&Gmwr@<wljKgI(7R#@nax_835?-Aj9VaysDuze7W6x2uIH(C*H5Vm@v
z@{{03OZA_Hjo+ZRz6krVjZE&KyhiD#ZOS3E0O6=KeL$VF^4$k0cPLL+!G(*mn9j>i
zWvk@?>{8a{BhcN-F5N)ws$4!8I5*{J+J3c1Dd|rW_Pxsa_`XBFPucey1mmuh?}hvQ
zO1BN*_E6?h-pNzBU>Xnyl)1E7=%7-47BpVUD*6h*Te*`~*L;*(^6RUN*b0_I%Jsvc
zJgoFr1AasqTm<D&rG|#r$CRQ!K<20P_Y~o7IIc7ZaPP0|(hKJ>K)HQBY)&X!_eB(e
zN`D&G1Stb(`$4c$L8Fb6%9$@Aol-triXudrMp@ucWlRHFe_9!z4?vi*me&8mmDw~=
zi%?FWMc+u}x=~P`QI1f7<*YK}A2_m~Q;wyP?RjN)r10ezlu?vUjaJTU2I-Pg{0gKo
z%Al7Zja6pGqli-uqh!=&<%*4<iB~SCWyl0&mq@TBDxXrq<BD=4ZBo3dG#mx|n(|Lt
zc1cq1*o(Sk<<K7Ra9vp$2tbNm*{TQ18%l=Ksj159OQ^i5bfNLoEoB4k3QJSoq-k5a
zGKRQsE90iXGD8_eOW${t-D_cTS83mkC^D5TGzcwAnZFQ4wzAd(@!nIWV#6DfQ5`<P
z^1iZf0_t*=`{{j`r?lUp{j2%P>b0;bP`<ta(n4j&Q7DR)><PqOqAV_fX{k~+2Su4O
zmqT5-vTtkDJys5;CmGULrx8=7(u+2US1D)G%dA!zu?`NODLcmk_gtx>^{|)9Rpa6B
zm9onjSiV-SwU2;lz0#kaQ*V@l0n%HgiH5r$l>2GP@1yeXnV@M<-lIJ-pOg{_JbhM<
zq><Mb<vSUoa8T*!A-zpC4qrFP9aS2-x1CgNXjs2p71<ncXH|#;06SDZG+J;`dDHW0
zr|O$*TD01w>hKJtyH&g1qS966MLWyfR9jOa?NQC51od9kx6Odxr&3P>o4cyV2?V-d
z)iW0^JXH5f0q|5!?go<ss!e~QIH>x22XJ1hPk({MTa^<G$wy`Djlx&8y9TX4q`I_|
zK3X}fGKRqBh$_&A;;70u2&BhUYuX`1Kh^I?ARSjF(w*b4D%lEPfXba78z)r1Qbs&b
z)r%ILf>gm>z#XhgriA=S)g{^`cS<EGL!col-9o@aRe1qu?rGJr0Wb+u^~I^M%fnSo
z=nWmA>O+alNY%W2ke*Zd6@%@(s@ja0E~o;=z+tp%D{Y^;q+%(i7}beLu*Ir=qUmCs
z>SQ!5FRPrB!5yz^Xo|W7)yS@hB2jgnHX2+}P1*>~tE$>h09;cYdJh(RlB%-+_sOcY
z<nX#`5Y4+%R2ykA=7!3#7x1a7<)J8UsxoNl`j)B<?Ndrq{r3sDbk#H~Jl$4}rx#_0
z>N`sR-BI<O3bMPZ{-;5fsY-5xn6gwV+O?Fe%A*w0Jyj9q9dhidU+gfwuR7+4vzDu3
zgFus~a-_a2RLxin?jqFzx~?7|CO9lsC5fRdQLUc=%Tm=A6PjJ7db|Olm8-5arfO9&
z*FpA7<+%Zkc&^$&$`>jly~gTPWAnlCQWbLroUc^&7Xu-_R^`5cO}(n=6R^EexwSzn
z-l`t0MilQ<$+TkeUgblHmJce=^^iWQWY<yGpj!49ichM-ekeYxUQq`AiwYx4+!gAA
zU;wtM2X2EWNA(n1GIvtnod6Hp)$tY-&gyq|+N`xheQW{>7xm6vXxdKo7YV}Or5-{%
zP<E@QuZGf1J)3sl?NK+QEzEn>FSF5m`_x&BVB)U+k8b$=>P16P=b^T*LX$kzCi<r4
zfO^KS2<@P{igr|Zse@%8^H!hh0e?Q~wjJ%D@m0@V3hg0v9BmCctX|RtG)L59lOP>c
zFQVNk$JD(Tkou_;X_wY<bw}Dz@2}=)gK2;|Gz4rX)O9o{3{*$ZXf8<odJF);YQs>3
z9io0t_id;;<QSyW>i0#6DNJo`O0%(Wb(H~#2=zXCzDBB#`$9US7Sp)qtol(5ns!bd
z+yYUYS5FuN>4JKx2%e(UyDJgJMRgqwO{3KvI{|)4y`wdx7`4+}L?5f(NI8Ny^>lhp
zT~^nG03NT7rgv(Bx*c*|c6p-u{0^{PQJd$YxT@|&r}CQmPg(;`QnyWjl&qGWKup)w
zfqQ{ZQLAa%ctb79N3W%-^<UukrusWN+qcy7y91D>o=?|tx_aBMP~KKAOo1{({m%h#
z-cc{r18`Rz#~>zqrn)N)6|>aaHX+h%^%?4~d+PZ+q0CXYo&^{8)ko3*%vDSAIj}rW
zEuuktftvjXQ533MoC8~t`qgkm_&^<d6u4rw2W_z_Q4i|~WvRN|HCR4W|4Um)AF0Q5
zLNI0OT6%q!+tn4=;4Ocw-bRz(r)uLVIIK{Y*r2RbpBM^6m3nSHXsXpN^xm#f_Xviv
zRvkte%4g~aw3+U?dP@huU#M5Mf>fs-K|S+Q-SjhX_3D@OGJd0eNe_{?>Z5t6d#4`n
zgs|VM?MG-g!3VWB?P~j|P92T78`Pir0QgB=wFji1)xsRK{)^gv3WbAa6Lp)DW(9qE
zvt6^9cFZ_yy5EA|9hymBfOFAI-3^wVnya)#xl7|*0NifP`&np`t0qE#rJF`t1C~9S
z5c_G^?A5fU5$k@9hc|3IG+9x=dumcvBc=lyQ88Q`)Ogy^Y%fiRyHI*-{>g-ik7m>)
zMB%G(3Pf>86H5=)!<r|Q205bng|ZSyHS@N@;W5qeDme7h{7aiQj%%F%gj;{jkUV<-
z1!!i`Q1yf+p0>ILYPQnV5~TU-Ic$P8o4<p}NsXEIzn#*IbOu|9rtl|NhH5+ypg67h
zjyfnzvvUOehHFxMVG^Oqrhbal*x!QXjONB(csQ%c`G7#rX~Jl=<h&-rhdx@npgB)Z
zy(rC}G!DF|>Ei)Jv_?kP<0Z}Q{cs<nSvwV^v6@e#5n9~Wm=ZK*IqDKMl^?-<Me~F%
z`Ky|{^B`T*e4^oCl4f8huq110cYyl3<{L`8q-gq?;2~Axif<Y0@|&8^?a^(wG`aNf
zOw+upf|Ral8Uo;LO|OwKy`wof9MWA)<SukVre;MOM3JQ#M_-*~Yho$?aZfXsZh&0P
z#Pjf*r`b%ijeO0;@1ZQvh?)aXs0p74%OXwhA?U6Ln(f~KZZFoDx}hx5+@xi&QjOm%
zMEX$ko)*g<Y5u(gM42Z4G1$sAcb<Uzv8FriE_tFELGOd7nsIx<U7=Cal3}IhEiD>X
zX;SDER%>2Wqe(TI0xRIPnj1wZo@rjJMe$tI<Ou*T?3z-_qt|J6)3;x5G@c>^^HwvF
zvSsfyF4a)J*SJ#$ebAIP1KUSU3mStoXqu$K#V5@w%J+QM+@$4|FPhZ^aM1p81fgxy
z#<fD7qxQ>H)H!LVKLBpKwkM59T(sF+V6szd?}5D-@?F|U8lddfR?w)_Rh#euA-ZXE
zXh^X~JFXJSz1nHhQ0&vD(976E``;J@<Eb@M8vTGaJ`;^OsO?3|UtZb*TFUU&X3|a@
zA8i#ag!*c4(@l9un@KB&hqZUe?Gf!^dnL-F+TSU~e_Xr%3p&_e+lz%VK$~<5h!a|e
zr;q}*v!YN0X$=~f1Z#DaTs)~|W&(Fg`{!{u4AD9~Miimi%r{V;)((7wMnq^G?!z)t
zdpr};8SUzyVRBZxl(K8*w8jp!=lQ($1+Cp&(1y~&N|biecm#Y=yZSIpqqT#6fXOB8
zReH?EXnh?~7pwi3cHG2iSC)eNvUcD|#FVJ@q%Gc8w8Ik7!B@3I?BKknow@>2lJ=qu
zb;;Vqzu@<}c3wYFr)V=G=>EH*9YnjyZ)v@iaG$1qNQ*t`T4%b|Zfm2<pv=%7r@{0c
zZNW9L-PLxVgucks9{2@*v$Sn#MxL#0mk!H&+WRk{%+U_<gNr=voS6XRYiDG`q(B=%
z3z~)6!JPpw(w3tS?eYiOb^pRsv37(6h!Sl}9t|zkI@8qlq4o+b89mZQ;g4#_%e14{
zfaZzzxDm>y+8#;3RcOCYL|vt}XDifIX}L4tuGVrgG^s}G>IH|j+AvCrJkx4ud&YBZ
zw+1L*XkBK(gS}3B2Y;PF{!;5xfVf|2S1tngYi%nUUcJ?-DDU}Bn?aib-fJJyhMf;u
z+gY%E)OM6Y*`O_^Vag}%U$k)bSz9|8F1~0-g+g-FF?6ju=|=qxlkK{}Em7yJ3!pdj
z4qdnhlrDDN?45A9Q<wMzmAiE5T~X}THP}$;s{5T1rEa=a8Bp%gZ5Kmw*M0vJNcZbL
zha-Fs-5wf<dFpP`rh)^yp1;8FL7n|K0K9ZO&7r+@1J1z2M;Dg>xUVi{9o!$%ZJ?3R
zVVzx{1Dj*If_G?|pRP|mfX8+0TNM7fJEf=#(3L&Hi9MmaMzgX&-F@okAl+>mj|J;&
zwEf_uE`-)1PU+TGp}RtK*)%>0(`||ZXSgo50LloRmEIMRx+D8ReMYyPUYKWfd+fA|
zeol9sHn5%7`O@uhLD!ZxTSn_rXbf^mC+iGljBe8e(8TIoi-C{RW!!@DvhLe#Nb$OD
z&%m9a8%iV2MBN?Qw{u0eop!uj)s2$D<eKi=##y(n=`gUQ==7;5Zs__qqwQI#x+7iS
z@TN}mABtPLgYQ9;rqj_bgmhiVw+QXF?kp|FW$4y4MVs#EKGO#GySinc;UZf%><XlN
zx_7712{}4t1-j(EuA(KRT%CIxnB?hxPXk%LZqPFLE6_dO4YER=?`&*XkQeEke*xlw
zZk-!wigmvl;o_k#U4vjA>FzHCzD#$H=3(W!nH~T>*1e}4Z%=f-S^%Ev?rcV5Ds<n|
zzMV>4pN~-1=zjYJT~e!iNVBSEx(2#`p6fi?!{midOJB#->E?~3KU(locUFn^zS3>n
z1H^0HGMcH@>lWMK;*Bnww&uOnxl;>2=vGqZ{G)F6LNum9_q!8tpL7>Dqwcfr-e_=t
z(WTN7mxKN>-9Ov((<sB~sNX>6)k)uUGMcnq?<}CsS)V!)miArxcGH31t)E5NHdj4I
z6LdFyZVvqJ(NFjb_`Uj})X@F<bjk#H=+`cS(o?^pJxmVh+doGX2lejsWb@KXPeJLe
zpYsFAeDr<`VCkzL)d}!Jdet=eJ*=-zM~@!SucRC2s9oQSR=$qujk6J(pZ)^nA&=`%
z(Dc(^f4Uf?0s15wxSr6zrq$>`{p7olg7m#9aUZO|LPN!q`ql9$PU)x79;6Wc<Qu?+
z>Rr;od0L-D>keW1R~jh8_3vn9Btn0J=FpLPd%r0V&*(o7M{H;HJ1Dz;PJf8rnCJCP
z=Ky~}KahruQTq8R;4kXC(Gw<G@B0vKx}-n%J?digHJ%7NRzKVk&5qMwUy9<gK1czR
zc)dH#wG#9>9YB_-uceIT6@4n@V6W;w+o!|RHGSql*d*!q(HdK_e!L%Aab15wfHFlt
zVm!ES=;w8Zl&a_d0{2b*xE8?Q(ofq6K$_n5I_lE(Irk9ZZGHP=Xm5r-e+*de=tnug
z!(IJfv}%&6e@^+pEWL^*N!j|5lWFpOPaji{B1b<q51#JpXB`4CSO3@yWuE@yQ2_Jx
z{Vzf)(Dw}mzEH0m2fsyndpRs0=ugpWyIAk|1|}u?*1m9Gs;|0(U>@o{e}>5;{a9Lc
zFVjm#!lYc^;W;=T>m%AraQ{8gzw!a%sXn<sOsn+yQ(;=IA5Pz*)aa#;5L2x_V=;<n
z`a4Zg_gueqAc`0I9<-6UPCr2o+)Mp)8fw1Mr>Q~qT7Ui+T-582$HCznz3m;OxBA?}
zi0Pd^n>NV4*H4^D_umKo6?d?G)Ia?h4jc6Q=x=#^(noFr_h<c=Pr!fCU#miU9Sp5h
zIC<L)xs)w)G_0pD7n}^ASk!Gd47UU4Z1|gogF6f_MW}NzZ0QcbPQ&E_M8C_B{1lwK
z4L$M!cQtqnLlky5gMT}i?lBCY-4%Nc{%e5WXDFzHsk>nc_4<B8NBSDy!@zAu;b|D#
z4ax%sI}K9~8XjB$+{>UPQg1^kJ>Go`dGvPiHMF8h-66vQ+FE|t;K3onBZg7*fH`W2
z*aF-!yP+u!&-@JDZ&4gK{7w%Ve?t^)778$I*$?T2VJEdW&~WlN@Ii*3R-&JS4Nd(Z
zoiyzJ8PX}k1<Kck7}ouWBGm9A3GmZ~4|m`q%+Q%u+QJR<e?Vvv2LEj!i!`vGP<O^)
z&!7%IYp9`3$L9=hXtnjc!EYV<;(}pC9k`<m%UYtiXjpL@_-MoRLvV4)aPJ#PF@~f=
z=-F69Z7tw&hSUUbUpA<eV2L;UtOYK?5cUy8qTxF2r@Uf#cm;qY!;3Nik_{pDorvwa
zA&Q3dDTZ4#RlH%S9*o#h4f$gs-83{k3E(Zm&m6eZ4Cnra-*kf)<yLPS61RXm!*IJ9
zNbeXTuR*$NSf2-YreQ@6sIv^eeS-#O8<tbL>z-jHU0pebbb9FBHw<b)7fr5V&_vke
z8REOaCg0GFMhFE4=?6%KhC2EdtjOR+FU|*sUuapY*ic@BcuNe2et}eKU^c+vL&Mz(
zkRBN(iosoGcy0o`+@Pl%$zwyG-{I(qVKO~}pBl!t0cV9Faw6qFD-BID!B%Am{TaY&
z!%f<DR%6&fn;mKmeS9E2GrXtC=yO9>7@~M#7}gowb%wLFjQ!Fum_E#XWzelb@!HUV
z*1ziw4gM(J7-pUa^;?6s6D;2uZqoqpy`jTwMDf8es5Sl3hL46QHB1`}?Sc{hC&RoE
zu=#AbMVHqXgJT0E2jj@Q;NE6zDn%5I#(!e~a5BapgvoZ}_tC&P8<#AH$qwUtSD3gM
z2hqfBr?F)u-0w1;><*UQ#(LTX;%bb!2lsBq+Kync?=jwtK)Kf#Ne|t9#zmu0xEoK=
zIB>tQ)kUy*7#EL$iKnqQZDl)PoJh+(2aSbGP<R<<Oh!L>8-3}a>tj5#6qdfmzAos>
zBgQdz5#dqe<|e2+W(=n*$j>-~wniQ|X3{n{f4i|N7}@}%a~-%(7@N@r6=>Y`H=+nK
zZsEZlY`iuWQJgfcp$x<+V@6Z>4Kbcy2VAJJ7Yz_j8*kJ8-Y{binrVg`Ln+Y|VLW^p
zQlzor5lqe)mDKvP#vE$)IpdWj@NnK}e?%GH3q}i#bfb)6wB~iu7)ad~ZJbAo3zv+i
zT~NdrqdLJd)|jqGU7Yb3%FbUl4pg9sH`)Xg2}T7y=Ms&jw5WZ>SU?%ttH!|3@N~_n
zrLO^#jIC)WPqI<*8kX0MZ|tX0nPNQM4YA!YzOVw3Y8>j16LizKgi`3Yj55kcq#3sy
zMw`-&i|Avj+r}zdp3N{mn**9V#=2!-xog}Ujv~{TO*xh<W0$SKWg9E9V0q8@uq9fS
zW4x1$&cAPrNkv_*F`$I<FL_2>ow)IgZD`(FU>rXa!4w*=zlO5NXrsx_1LHor%8HFO
zM-W<x@mCtzml_9Z;QpcUo2RIIWNdRCMVWC(Faj+%E~8x3V<S5imQReOTHu}<cO)RR
z3S;>l)KwZAcGLW?${0celxkxveF{@!JWPM(rq<Y_GZ4>=qH35vH;U%N<c0CK8gSPc
zjkKKo(ilLO{2OEDC^YS@@xma$-x)i*!}7hc$0gK#Fm9zK!jHx+o*-*5$|%?H$vC(@
zq|e5?*r{!oe=)wMH?4!|Bkh*kW@45@ax_hK291+x{$5DiP5CtOb2go)+{_Ns`Q5;~
zn7)01V0N0Wk3+L}nfBB6iruE;v}@SaRC*nCZYCXVq}XH18iZi>n)nBh_L=hNvF>hK
zMQIrOev>0D+jyAv(rd}n)R$6e2TVb}@O03`XTrUg>8Fz@yiLWlj_qUmV;Vg9n(8R`
zcF5FcFQmh!jWpssVtPaO$Wc=qz0{7Gx?X^ZpJ_}!dgi!k+Ah@jn-<cODZtd^Al#p@
zn^sfKJ<v3Sp4~yFJG3Vz*yMg2rYB89PeFOg)RxB7A*MM^;3?G9g}#zIZAv}`lQ7e_
zQ$Z7M@}W^-gemATibzu}oyjvMht4R@n(jFxm~$qp41Uj>8YVz_!L&^b%P5mw_8l5}
z(Ue0YnrM?_64)-8T6Kd>jOkz6xEN~+n2wm@Or?Lr<g)2OKLFxQJC^~UV5;p1lSI?0
zH~_Ag=6{dSu9{k{Mcp-1J4*Q{nM&LsC7ZsXt^e0eZRz!yVtP!wiEo%H?DXYes%bzd
zNN<`t2jU#uGMW4kMVjg7b^xZEGLHgr+Z5dq+!>~(tzdG;q?mx7xoh$|3erqd>JTWi
zOw%b}lx>P#2<1JKI2<N9rYW@3B+s<g14X{cpHk5UCVv6(7Mfn(r}1ZzscaYAKQLAQ
z0d2AATbfvum<s8-DmAsFDceI6L&JtgCi7;*RAy38cD~$no3>*;Hnr^uPftuQ1_1Ze
z)Qm2@3R6rjs4Gox`l7DNB&Dwss!elu!=%QvDGIn+Q_)n~jq=QtbOQlDH@%<}`@*#J
zBoK9`LA2uc(&S1r>sO{$Vid1UbH{_G-t@%={2SB5a|q_G$?rHKd}kU$>j3Xf2PT8;
zgJ~AMhd!E?#iOplRP_^-pG@&|Rev^Z-vrzj(=bdS>~aV5H7mqz=G?((ucP_Lb)a!F
zFEhd6cJqI<6T{ieCBp9x^GF74E@lI@VyAg+Il5$*xq?1r*=_!j)_Gjb0}ms5H*+M-
zy7!pN*T8bGxhG{M_nF)O2NQR5{aY0K&0~{6X7?~Jrx%H*dCq3o957#_M8rXJ{sAbx
z%)Lv&?QIsv!o82Vke+P5W^bDB9x`8f0F%S!4m9FCVt&^Zo{pNA&|~(PSwnl8{mkp@
zAssj0z5uwtc_Gc;0?g}90dT^+{sT+`?dFekR|S~^U!w>%kL&^$C(Tnn!{(G(e*!Uu
zn71v1r%<!x8<?CntA;@eGtX&`hK8FJv^o}HE+)1}Gd~}IGiIwREYF%NF2m%U`9J!u
z=Dc}CD3lk>H(S6m$~<~2+Ii7zzxN6@(dLVDpp7;EL5l=&=5CaazieKWhq`$433?<Y
zm`5v7B%0gM#P5nZnFi=r&CE3v*US!9M3H1}ItoRy*<?i&*UjB%i*ky&f)YhH%whL{
zOEtfv9P&-`m*$XenWOFW_u10SzLa!JH!G$=x@{goo9Hsk>9phJj(G%S{_mQVD-l|z
z*|HvWS?0d9xi{OKVS)R5<{vhqF2}rk1d99Sgbd(v&B^5;%QG`Sf;!*))(3zB^8%WO
z6`JFBqprxD)%Zs<9+;gEz(uh+uQ`Av=08(GQ)<qbjsALQ&YB0{BeQij{Fa$9LdA_|
z7Sn9<vH6#+FnMAwqY?5`bJxkhRhXyE0HD%*YB{7T^9Y(uR+|^nR>>OkQWiz6xhHKo
zd}bbzN&8=(n}^T>(F^mRuMkC@`L7BfUYb|f&_l1xg+B26+MJjL(t7iBdVIVwzi*3H
zyfuf=i{zd87;Wr+Z|-~(4nLUZmczwIvn>lQ8qB^%P=7Kz7J}uox!XaQd@=uh8g&kq
zee3A`x6Lw=K7e<$ynY7vP8MGyr0tdrHGs|*{amo^ur!$hgo|ZJ0zB=s6y?DEF3Uf2
zA?>zE&LLh`%k}S2xLFcr0=LIvT!~_@#f|1e`z#&q0pM;~R|x9;7Bj66d01+$pw8}T
ziKa>E0ZS;osSjFOJcQQE^5QupZ_Ck6aN%Q74*=fR^70Z~9I?b5Lo1G2F6kj1v;0l_
z&ipLvsuAdMOINy6{VkHyfCpH<(7xIemKfSL9cVd3tDixZCmm4)TPB?V%SpTCy%fMx
z7AFUEcZg-)M6iWg7O8<hZRwN?7h#sww9XT5S+oL0gk>u&4@X)&GeC33qA`NztR;B?
zT%5Dm=rMcVvdI(iUa(wpK@nx?d>Md?mY(+jkG7nY!_g(nTAH)OSnSIvZ53<Tin+Kv
z&eEM0aV}eCyTc~lQt>Ug6D<40kP<B(pI~yuGJ&>hU$r!!2v656y~7YilBIMDaM*c4
zkF@KS_mme;vF!f|es5SdpG94&MduFbrlp?#SjsI+s242LEa&XB;U?V@b`s)kOFpIi
zGb|srgZqwU4kgC!S~B}0icHHx`j9-!;^K(z%C?k$3m5k+PrXr>W07V6aNlC3hgYs;
z2qlB^EDPe`FyG=wpC}es_R|Ea(DL6O@K9t~n+m`K%Zx~R{}o%(Pr!YNC2%ODQcLIy
z#PrZ&rEk?ASs2<5S!OAV1ftwxrpMM}%Z_x^J+b`vCyJ+*uJjpig{9+IxTv%Y;o+jn
zQdbRJwdHsiIBP6RXxdwAncEePo>{&LLfv!A7AN{>`-LUu5jwHXa)oZ7mlhrUwS-re
zWi+yXZSkUHeZ3`1isFrB9DNP^*3x7sB7A4zr^D}iOD=6Y_+SaAkNZAaN@?-tvt{9I
zNM9^9^dxn#W;KI{ZPt==fIC_T(k?hB>o!dNJ!SKC_QSMT;9_mJ3PwAv6KQ2>m-RVq
zKHP1+e-m`B*6cd?aI<F9)~`L*Ar_eIwF;Ds+Glm^3s!flVjfKPTiekF3lHlF`fG`v
z)=4x7Ibdz(1L>f33C(G}tn~~U>TUh-2mJY1o$NGV@U@Pk@$Vt)+U98KVe1)svL3O%
z<w1JXx|KGt9kcGT!LOgynLcPeZf!dPIDhNVRL}%iU(rPSgtZB6_6oEXuRsxGm46SD
zVC#QDfS<Hp?}Fl#wIgjV3$cE003g)*+iJ>zpSI4SCsmj=P=?BI>w_C8BCMNeXdY=z
z=MmEx>mu4jd)E5vS^&>kS00D*ytUE+{dB>)sXL;GvaX<w85gY_J$It5ZRo9b$+~P4
z$YQK_J_8<WJuw7QoOO#2ip$oDQ7o>3c<YlgAQG%&Y4(t4ou`566>CN>6j!a?Xp(l#
z`iQRbB<p`G;3C=T@D1v&TWzjrVTyI)8Mwb;jbOo&YCYW!EH|y!bKw4#HE9o&Y1YUR
zI83*O`-AMZ^#(OJ!<vDy)A#Z_)-BPnxob_@2hvPyhys;aR@aZ{uWakhji|e4_4e$$
zu)V$H04xfvg?B++WbG3O!w1$wzrtUs^}A4bcxbI`g8&~{O|*x+%&L9|bh-6(DR7Ui
zt0+zO#M+FWMNh5Y(~iIjYiD{XR$5m`;I7IVUIMAw`eGj9tg)V71*z5=KwJ5qS!?V)
zfq!nzDgpNk>l6A6q0ZXG9m<#14Rb;I$~uKo7O$;K63{XA)(3Q1ys>sVjpD8KkQTwb
zvkssSS>Icql%V)v4bq_Qqjd~TkQ=O{JW+hIrn|x6XX~OvF!^Hrm0r6JwzhxSLAuRW
zKzUb3+n@9oHk@o>didRLo6-QFvuzRWNZ(;&Z=q=}wro#?w$t`(G3s{NR?#ki-L{VN
z0C2UX(TLB@){<`DJ+_n%@U+*qU_ChZ*@h|M!QJMz5ygJn_$9!3*joD0``XhsUIw-U
zHc#4sa?tke?~uG~i${UR+vfKKq&~KR&A{esYqtiT4%uvvKzi8bMw5mkHuFC)Ickfg
z8PGA?%X8rNvpuCX{o}SlwDRn4Tl^R50&J&O!~F?cXG&lM+T43nzBb4<n4Z$Xwv*Hs
zCv8vZ&qtlIB~mLwY(=Y4gxXfyfjDhzu^g6Rwpok79c~-*Gl~eCIRY*sZSAHY`ZKm)
z>7$Xew!pbip0gFa1Lt|$^7)AOf~~<7eHdjsN7L4ew*9o=zA)N0`aUWz*`{YejIoJJ
zQ5kEylY}D9wz3w=%eM3MRcE{{A_k-hw&)6YO0-pdkC?96vc3U4$+r6@!cMk*Gae?_
zZMRcll42{Ox$F&Fr00+&M*F>+s7kZVaY0DwwoT>eyW6(NUm#`JxMCRIu}!5_sk^qd
z^ch&DtwT%1kY$sl!%wy?hC^}BmO?p#9NT(FM0DRaeJ4zEZP8ajooAawTeR|R$D9yK
zf$eMw0EM<`u86P5=5D8Z|ACFC@kp`lFPdVN*h((JwA40&wrfAMRsW9GKC(4Tg0jpu
z<Q)Lzwj(q=e{7S`gz1TG1g+XXwFON;QDGZKORtqShbt(mY+71Yt+qWbM^R(jVM0-B
z^P#$Dwl+Ix`TV)<JNnk@g-w4MMV)QU@9^}}_Tw7_^UC(aZIHgU@wAVz-c~~Uc;DFm
z>w~(tw!!HL=ABI-`2XSPy5qX6zHr*lm1S0r{O-N?LMuzHw54TfX*SfR?b5RSmA$tp
zg2<93GL$JpKsJI52MDq^h)hvH<oBHZI-mRA^E~I=%lEzG+;d;1*38JzPt$AGhC*{@
zjgtT^e6S`|jz-L`nMVPzhie+2guS^nxwL{m!Z_$bJ40K>R!V}gW2AqM?zU&_qfN5|
zV+Soe9T}RJA)FZd`+;y~?4~ny7lwBa+;?UCN_%EE#y6Dg;Lf<84iyi^mi?&nWUQtT
zuoq)1eMH8av4~~?A4Zl99Q9=^pu8SGM%5>eKC*OyKjYG0C>~|};Q!G#Ol!&!czA+w
zl_rQFM&R>c31+CiLFpvJ?+u6$#wOZ8pJGVpL?M*XdJ?5D#>=mxE}XHKf;OiaEIKoZ
zVyvb0cr?Qrj#3O`%nuI6GTi7yJ&v)C0jp;i$7w!~XE<L#-C4%pRwf#lz<8b(YKe?O
zPn41vrGG&unZf=LuAO77D1yQBjJxD$3gaxDnWQo<(R7i<Slt1dbjFRZ@GygMo+410
zjFu*d3yja`%p{A^bRA^bjPrZJlEa9mSYj??csXzv8IiA0q%M!)B7}?ijE;Kz5DFM?
z(eC;ZV+h@~ppfA;i&7EeYge?Xn6cjlnk9_qXg6QV_~&hyC}VtGh*CL&a{}BIjJ1^H
zbD8mw?!Z+tYIP7*jQ1<hz$=XM7yzmn%PHtt!zllaB6YQl^ifpSF<j{w>MA351x#FH
z9HzMLb%q<ga5or_)d5(~I8L)&1H*xip>8rpDK6W{_+}kM6T^j8{I?i~8X%e(Y)Uw6
zVffN1R4YS6q1!e_8l5P#GmLbBs)JF8kC|8(bTXKfwbsSZ1;SD{LyuWuK@a264v1bx
zD{aa87(<jX(a-RvgsB0>QVF_yka6P#Ox$K5y%Vn(qn~!bcNhxV9S<{njVO&U{1$^{
zl#%imd>UiK(#CF_F|Z2GOfcG25Z1el`H#cyB;)Y_kltg|T?OJkBX%1~Qw&FU&`dL0
z+~D^NBZEQ&4;V6gsLV39y@^&lWSp^u`8h@l4L3)a8)E^mWj@G-K|AIu8Yk?T!rk!6
ziJ3}KM`xznH0oTK>wN%lwKBI+B7+;V^*6A&Gg%ZT@nCLT51=PAgbp3Om<#Fb!kgJi
z{p`c^dJO*hGTUhL=f`}i8+HCn1HIu#nZ?K9b^tSkzQ1*h`PVYA9B2MYKiNPghxRQe
zm^t)@1~Kaua3+{(ZF~y`Pcn-s0u{nMbphfO^G*azgfc%q2SgZiWIYh!O#VF}BABo2
z0w9vPh{80dnHFT*EQn%$OQTgZ^G6ydVwm~40K_tn)0#PsxiJdPoMA407b@}0M`+GI
z%S`$TZYMDFth7f@WFDtvog`+)vp^&>*VFfD&M`luuQr`$HWfgmFhk<uOe%AEH#F0j
z7AMf8Ghe32Vg}RhXRu^4k6EB{foY{5X%=&JCp5E}KTg0>4s*{K9_BKGT0nM@S&<4{
z9`kr8r4ZyZ`=(GVV5;bIc9)oKG_Vyi=RbhoMNB^Jj*FRdbKovv&d@Tbl-ct+Xv&!V
zl<!r}G`|Ry3g*JqFmajbMXz`zbBI2fT*VYqTEP|OLN;*K%qQGnuZ9^%o6TBg@2j-(
zsAI07+3YHF8J*KzV|vq<F0L~Rsh@8!M-PLho_X^*)HN_aX+`NKb18+T8krfi8);(B
z7o&8Gd3gesnwe4s+S|g+q8qKPOf4<(+nDkzD77;m5OoJLF&m<j>9cVu-oGwp>L_Ts
znJ&cu_Ax8pg^7M<=)VvHOqUTn9As{71<h^dSM(j$A*OyC>h3V#V4*R?OrHf%8DWO+
zKzENa59~*2jLAp>V4V5lRj5ob-`)Wa?=lsXw=v25gD%$HW3Hm#n)N<&GyvwOn5+$`
zoM!H&aLWv{_jTwzVE%%|(SliK=5eSzWNxAe)EqO<9&ATgzC94Otc};<lO0R!fHv8)
z@?V5&4y*->!R^S>Jp{ms)kHa9&aB^eLB)kNS_0w9a@h=fZdTS+nn>JPAJXpFgXOph
zY@V!wY9PE=ztHa3oAnP3TRtok9f<g{dT+rsKh|9e3;VOAwO~8Snqa`00G0zSOpmdu
zB&a*idV*HqfvgW`)H=bc%K&E(Yc>7igIVp)aP1_^n!E#cLs;z}gZmWA@jO}|%BrIq
z%VDh4CC~|Hap<Tif|W$y#ffA!MMIos)k=ViV)@Wp6^#=_aL2HQXoQJneM}i1ajeih
zcyWdmSPAp-EEk$Z&$1frK%KyPgu<(dtRX8U5GJvHSqrC<S=n^#c8=B21=aH`4(*Op
zSY7uZQd#*F8A)S(code>S-&lZr3{wKWoTxyu51PF0_(9Fuw=2m{uzL5mKViPa#&0{
zS<7Xupu^RRta&>D$Yb?yKwUm7`vqF<7O>_~Sn3k%s2C0xvi{kFhefOxDIchqrN%6=
zpoC>li^5XYL<{__U`5=*!^^C{>3&fq>lI%-tYWos0l30?%@*)#*4YY_YFM6>wNlIC
zt%YVC>&8*wuCn&!18|L{>!M7l>#Wb|{k_4G_`*azYahMT4J<Y#{NH4i()zKH^=vlk
znpoMP@cR}kly;}hEDpUDEv%S#VWO3Fo5J92tTNiNwzF2T(4-EQ@d3y>St?31>tdNJ
zQP<5n@CxdBScku*`LCCCh??EU3ZYDZewMThhyhmOC0H6{MK1&5Hmhqj93EnAr7-Co
zmiKzp4YMB7ZhVCGW&zqX%KBy=#2D*`FtCiX#IzcmV8uNJvb(IhZ((7QRkIX;d#sob
zpmLw}?;?;{r&t^4+ZxlXJ+zjdVF_nI^MJKMk7m!ZSQ}yYAuEw0eRHh0jd*y3{hA{H
zw(NCb0NAlB?!!ZSHup44II#6zu<OX)Rs<C%_R0VNoY|-7_{oL+2F0pe*?YD_xUmnP
z$3u53J7y8MJ=o=cqv*;0S&T|A_FdYkd$aTMAbi;AbTZ(}en@{<KlV@mLin?{Qc(OT
zdl7Am1K8RSm_NpL&jtKA`)&hDfox3=oH@b1KzFTz*!xcb5X_ErMJJqO$IqY?!nS@v
zIX|b^E;J~FvNhWw!q{_^^Apa#NFlli_NFs1AIWZshli)xrHj!)QS5b*sEcO5zYBFS
z><_sRvFuigamBH}VxjIVTN4iR3G91xjFiZhErp>ZwwMB<$?Rw6qwXA=X}t{9^XwT4
zg{H9khJa6He={GxrLos~0GQ5R+=j+vun*Ap$}-u1(f?7pz#gPDj4Za#=TOOJd-Ktz
z9QM2)K$^?`d?i>evOoC)DtT<%&w$HkOK8_u!2Yro)R)+Slx0)MW_eptEMl*%M`bbl
zI;GW?uz4!5m9j_3;WBoADcW1k-rEaH73>7MPJEd?OTn5-cGh_Ss@R*eVd)Axyd0#}
z?ChJs)v!0t0$0m+-Ud;}=3K|atL!UF;LJ7l=u;5a*=O@;{=30mNz+O_d*W-@ZD3c>
zR_!KxFHQ7~>_7?%G_iADK<O6ydn4+a*}EyJsfAtI4bjSOeix#Ry@E#hb~cB?$sO!}
zABTsX?A?a}=werY0)yRb->vYshkfcX0DAGypeR$Lk6lkAazA_VN#F<AFQ&oLAUm9{
zDcxqLxB@@Ko~76L4x6h%X_)<O15`%XI}Ip}vQ=l%>@oJq*8v!3JJ6Uv!G5?0DtFoc
z(vURCuJDAxd+cEvLhrLH>GIwb8_RUOf79%eU!gj~uBCA01NIzkyk^-?=c5%5+1oRL
zpJNx$QN$5W+6@R>4uck~cAPA_fp5==rhBpuoNG=fIdXECXtoo_N@Kn=XWm;7E}Tzk
zv~=YJP)N^>^9tPrbmwH!MBruR{M(6EcyoFtQR&0+pum?e=WjWHew+=ocJk+3roh)x
z&O9d|0yu|yAdYcHJ_F5h4xhGMft)j+poJ$mBQmrlh*L!0(hcSazXaJyj?*o87{YP9
z3zbux%zY?@aym}Kr!bCHO24^q&T}6E7{RH08>L82W(I(#Ih<F3h~k{1AagWlmev_D
zoSrV!#d7{k0w9hv_a@lRa9*NKcRXkCbGUt$Q{oAh1kP<b;7;T)SHRyS&S6SAOXfJ#
zpza(eI~$zmIfd4FAWh+1J`H>-XPGy+(>M=~qB5P+@FvV>a1Lrgn#uXI5h@ork5DE}
z7H0{)2iY7ZJ<Q?!L2>t74wKHCFLIuL6PEHgN&SH5bDpQ)Tmk3YGT<(823sKtIb)QW
zRm4dbSz)P|<D>(kgyWcoelF$64}i3cvz!Lxa?W3N@UVijoYo7MIjO&(RLR*(5!fou
zTdVN!3P=4a;MJVF4ZziK!l+csnWc%kj+0~$N3U|cC<b$lvz7wC*Et`*1>6lzCx<en
z>N%gh2b~7aMhacs<S={C-bT&}x<lK<Is6aUZgFB=!Pd;-heD-=b7U7vt(>SWXm%Ut
zox6aybJ%jY*1;K}J#;7Me=UG_advJ%1G_oH@lfgElo~+Y%Mm-GXZkqduxDM+&zV^W
zodM2jA#?^g%lE*<ZBE7!&<t^2YlPn;93GwgjB?8Uo8vg%)U)Fpw`s6Va28N@!d;GA
z7~qqfEJ`}N$H`v_mHV82PduFB6wwlMn$tl`+ZoQPcVO=UC!`y~I?MU;7npd+iNdJ6
zV2%?&Uu8bRZJ?l@E%!0{ypbLENlG2J=T23F#({g7;{A@?viSfwabG9~z?r+A-eMPS
z^c8f1D_2f`W;gCy30T~@-V_b-;IhjgJh?~5Q0K*cjBeI>Te<dLXs8eODh1bkxg)gj
z^y5~ofF*yfls<oTl=}qjQUbWI(m->JyQdGmew_O)oxBEeU)Q4U1h<Wj0)n_nl;<4G
z{hr?KlU#dhQV7?94RMNlke1Y;+&^dt4&#PCk5V|-y5m(;MsU|sn<BZN(T@H!cO|7Y
zL~$iF(MNOtq+u(D>qa}iSneunQyljUWfz>`&QJzkJa--KdCqe04MHSvB}()~BDX<?
zx+HEloev~)577jFj{Bn)Ea$m5Yamj%R_k}rN#!;^0WZ?H?oY#RI(LBn|49b-6Z)1=
zCU@^vcyWRIvKC%saSyKmAe%ey5G>_zS5rbjE_a*_m5bc==TVo(eRnJB^0}W?qppCv
z>SI{C#Qm)Z@Ir3sezdcQdo>u;#oQey{OkUH#`^pF&@AUZplx;q_x@&(UFLQ-08q(&
zDjuaO?wKFJd4;=44O}&M@C}GM?&M+kd6nC{02Z!szw$&Iu5;t)d-^xH%V`f=&)xkc
z>KeG8P~i9`cbEy$$o+u!W=&iXWk22GI$0^NyP4ZT*&i+33<{yPa+`mEP8)arOYpay
zyGRA@4sIoNY$x~HI@EP>*WjdgK{xk}kD=1TElCHimwSND!27t?r@`IN9X$!R2e{7!
zqF)EO?*F3hHg~QWfFbUlW{}<CE<Q=Wu3_$@e*rPVy}ut`jB+2NW85)r!*0}#b9r<l
zc7nUA8Yb>?ZOHve?qjrbxyS9<5AOTiWnm~yalbi?_D*vHw}5+wdyN9554ayn0hr}>
z(-z<%cOJzN=D1zof$RuxIFL?iY<W#dFk#0lcpq%`yoYqk=)kM_1tmwGav!{K;u)U;
z!kPE040SHNrHA05EAMI?*xY!FDTU0Pw>b-S9=yRElstLw3jpxq<(`FkZ{GW~z4qa~
zOcSLqPw*A${CGNCKD93J=RKB>;!&RcFX)5-UXBUQ9OIQVK^*5Drk6R8S7n2`6FieE
z@IgG+$6+a$x9VNgo#Y*U8>JB5U0YZ>#ryIDXom6>v_B5xecysoIPZ2M$Rc=R3NlCX
zatyF{nzyzID%L38)-TbRXr7Fg;xW92|KcaSXga%y<4x1IBhK)~BEcQcYp0tkXL)rL
zc2D31(;J$|bAJi_l*Id;g4@Zw-)U!hjyFkhrc~Z_`u0N_Z<vz4(s{4YJ^Tz_>K&+L
z^2R83d%?>4gI=*Lo?AQmGMgvy1$Pe5WCM}Q8>NdU7kOcC!0$X>!8w@E=Us{bpn$iM
zZctp}711$SA#W`mhZgZZqCI~xFJLK5l<@p$XIaYoX%?c4_w5RZa^5~G>MD4z(-&hd
z^Q@_~t*PYIHlkR?3*C*%E4(_&{;1~la#5<`t$GTs)$&ScFIvYdqWqz&JRu*AxyI|5
zfw<1wv=-)X@FHj@P|qv)39WD7r8k4~ChrPOhK;-^3dS_?hLvEs#XFe@(adYN^1$7~
zySWJsZRK5}8%1qAErl%Fc~3jTQU|Zo38bC8tY_g<7jL)(qMNst1A{$05p6Vkc|kvd
zyN@Sl!fror?haH2c;8Z-X^{6U?Qw4N@+nbqh*!J;WOsNY_aTOPt<AIs7~x%@%Mzo!
zUxwk#7*DVX4v+Jmu?6=8uU7`(U0wtsCVBtHqV66~6bnoDc^lKgJ;ghC0AiZg5ezZI
zn@_oN4|oO}n4jgn?*!_HyzX^q?;LL{ouM7!uMPmGE#F#2Yj8Wh1FgF4`9aSB=)f<b
zxTz!m%M=JFzSomzj59yJ7{Z1B1#NO%`MODvy7A}!MaiB2jt)2v{<8~U(39`G8Dw7k
zPTG2S^OHn)=)>O-3>9C#=eIEL$N!z?Qh)xQFKG{ajGt?Z;&J{{Tc8@qkD>IM6MUx{
zm<ZyR(t%(wf7w~!Px3#f#b^lsRXyyU;)jUPictQewBifncie`-aQ>zRAdBFS^nxss
z9~X$yY5q>ydq?q8O(2WrFQH_L7``6`>8!E*h5v#(j^9CB#54R~20#<fzqSkFEPv)R
zIFrE7{uDHc{Ol-nLK6P~Eu@n9S7?QLj?bsD^F05xO!$<-|KtteQu*z)Oi$xSIe;^r
zFWU`32LF#ZJj~?ZT!_*I{)`CJSyq14IB2r@?^BF1hyN)BigNkuD4KbZFQtch{AE7?
zn9p|@1X}_B7-jKZ;#Zj9Od<czC*fKVf0|--#r)rT!Ck^<)A2zmf96}Ll<|K`f~9i4
z3x#_s__y}J-eta-&Q~h=)+ov{t>VA%8T#uA-^Bx!)%^G9{Gf(k^dZ=4`9GMUTE~y3
zJd>;ZI=XssjUP@C`|JFlm!R$j|BpkkRL@^c^Lzt8iWUYp`TJ5~w~@b&4uhNcK}SG+
zi$A^y51aWVH2AgfpSDuSzLh_i2up4JK1bMX=U+Gk(ZT<X&Qd!0b96w`#n;>iqMIKf
zhru5H);84j@(&K;VIP0`cZhyIk9J%G{GETpwL$*CPEg<GJMV)tL;R#msJp}8z8Uag
z{?@0_mJ$B`blN11@+-c<(=q-sd(e#Y^T%O+g1>;$HSY59AEWT9@kc0DKE;o}3Ng*U
zM6dr0e}=M79`K)}E#53Y(Vy?Q!rFZUhHM4#p-{9FBn5)fUJyp3tApV2bd($g|D&&M
zISIb+z#qg}@X|PZa1s3T->W5%_rQ5Kfe#(UxeF|Ouy_dEUI5%v@OKCRUV?ix>3a))
zOM~zctn5Hf_zLcL!dpLq+**Q``3pQOs5~lonP$%b!LesiIwtrz1705&ypaXcK*2uR
z+@BEqOiO_v!R%YW2MauZfyzli>lxIA2y!Vi>6Bm#W#fbjl4)HKCTOJOvT#9M6>t%P
z(nnE>6lBwH<g{RmyA{PKfr5sqXu)a<4#Wuh-vK^W@Fl&Waf0vYPku%)S%Ff#po#{j
zvx4<`c$gqqMKgM$;5@C;lLX>qkR}VFXv{n(*g@x+=LLgN;7k!bqywu|futS&rU^bM
z!NYXHyMItnFGKJGeSRZTz-j~c1wkL3h-3+l`~Ziu1vT#gm?L<55_P$PJOji<LHsxX
zc>+5*Ixk;PlL~_cg2*?)eMz98<!Yf|iV`@B1lBjvmSVw$|3Q=ph7GV=DoDQw&N9Jg
z*c0LUzd&^u#R`FK0!S|lf~^2n3K$extP+T`L3%|HUW`(;KuH1U8i9Kz*lGpoAA+q;
z@Y<`uT@}ouY{hGWS83sOU9heZDmMf*l$ua4==mK!H42u~Y~3VS_8T;B31(<tYi$-x
z_M);yF!KRKt6)zfM4O<F8q+QarE5AJf}J$Hbqb8J@S;o5_5@VA1-UfX^$4D&7p+%t
zg1WR%a3%?){eqS+@Nht|AOwIxK};%o^tNF4DzFR*uD%7=?g(TG)D2q&x4uF@j|jHW
zy^m4Bk52(VCXi6LW?b+CjhPdI5<k@46-3OTZc@N%hfnteztcE=Uof9`^;3d{w4R?9
zeEbJUX9Q+iB|H#3mjr{ef;75;_fW8pX1_VXW;&TZBINeNtgX-*PIu?*gclOPW-rXU
z2pR|Bd;w@2g<&*pItjgpA)JM)S|D76ujd2cDhy15iktAkJXmrUKL0oz^$-eQN6Ayz
zMTaI{LKPhtdkgP90)sw69R)vqg)h*u#!sk>LnHi!yRCGc_o#3QB~1nhAO3;LV?vh|
zKpYpoMHe6fg+JT?+X-O_<?sgy_s~s%VBu@WP&z5>et=Sl(4KB%oD%MQ6$V3v`^)h#
zOnCV&9)=4ihER$S9;8t!QfNczG^d5XM!{^9@bD|NppO=|`amZ}_zz{d#0pbB2QW@p
zp+?;q;SU`66fb;}&I`^8AEVJZLAa+KmJ)?~UqC5IxaS&Fl7)}_iPoPJ1|NZ?^FqZe
z04c)x>1a!;aQZI*(u8L@P)Qdq+6pf+gv(CSf<9BYa4jrd5WZRmr*ec}eFk8zFoXgY
z7ljUQ!>2r9VKRXE!gsEMra+ik4RJ{rO=sza!aOVdEfVgb`LbBJ@=uVJ2(@W&tyGv!
z>%KB!(hi7n;RWjT3ZYR5_+?>F`BJ1_RSG*-0$3&VrSQiU;RTBSRSO%c;6;t_XIGf0
z75e(ux?!xo2aW4OF6Exw5GrXTtrs4C6^aeQV0$Ru6jsw=Wuq{D7c`rMFWRB*mT;;S
z_L_y~;!xKjyvG5&RoL$hl{R7HMyRw4Gv>j;4xxTKjCTq(QxILkwlP@f7H*;aLyz!T
zEA2~rg+7!D(kD!#49I@r1{$UYgq1?{&!F%iO+vSYhcjSeNVxbXklqn)jfCA{;fgD0
z=7{iJinNUi7t(5XOt{P&+~dNpX(*WxK1~6_yTWU!C`}5FO@ZZ}Fnlk>ePPQ}G%!sG
zHylTCT6l=AIL!$6#Ny!t;pIocHY-#-1ouPXIf{1935O@q!Xu(8igwzHzM&gOb|S11
z@S=(8UPH-2ba*K|bQF!!xv!Jx{r?t^qH`2-auEg7oqAW%#R6Dx6Rnz}R84nL$L9cg
zh*TfKgr_Kd0K!Z37+sh279BT3_=x6c(DM};eng$0DE=x+{vxMUpgAg%e-1|jM1LMb
zuN@QpyAURhi^eE$94Imj!`~C4y);?{iS~aFT(IZ^x<hhGG!Rb#;84+*;Q)q-hS{hL
z7wujSgAt<U3H(JOMGq-$<g`e)8=Vj(`s07-#Awl{^i`D@5kCtiVnrF-Q5Pq=|2Hh1
z5y?tXiWikU2}jS0);)ws5S^rDTcW6lwx>y=1D#+=7A>dUy!D)@j6RNZUgSU#l@w6}
zMH*5?W04SPqL(SAmoA#fgKHV0<+b3>6dCj3+67U<Dgd%XE<$i;i<S++QjVzJ34mPD
zV%no$6n#&}e0icjD0-eRlG0&CfoKEmsxOJwJHl+CRrJ{d;EP0Qw7f1B{d594C8CB;
z!B#5zh!$04qPX`_S1$ULe#jM~y=HJ<7CmPR^Od54LIA2nLFC~T(G5CxsumgQz*!?&
zMj2VPqVMhCMV*LQgSxAtetS4`O_Usg23{9g8|aMZhUl3&SgIG*^+TsYbk%?s-W0{o
z18Jk^8#+;F5<Oal(k;<px?0gJ`j^(+Eut0sz}+h9PC%(m^d(Kg?V>Go!qp*i{{nzc
z(E|!Db%~a|54+u>SxVCB5uFZ(`Cic%R@%w-iL|t>?iZb<lg|NB!J9w~iq=zi-xdW@
z>hX~1%W|mP5uM+TrVWeUD@G@bi01!@hod5!-yp_BzdZuLxM+Jiyq^#isbS)-=noOZ
zr0BhJ)ZG&Wi~)CF^aKa4O^I{^bO1Un8Y16jM72+Y=7H#I`u@bM=r=lSJR<I=n1roZ
z_Bvd%6JMaT5qt4x6rFMqpBaIsqqv=Rn@-|>N{n|FyEFsfB6g;YhpRaAU*O!t`<vl~
zyLhS^<~_vAXwT{?e&ZPZe;qIJ5jw5#76-7=dp_bO%184RD}$iwCk~{s$X}d8LBylt
zA-bd*Aby%c49CQmHiPE4SZM$*P<)!=U?;>Y4xnj4;vFvm5G;O&Vj(BRM-#vjBKDyB
zL#M>!bjlYh-ugUU6$%p{q-}M$xMwR=BgCK3OA;v#pzb~`zOfkGQR1!*=%;A$c7Kq@
zh_}3qQmpvRSQv~GtJ2WIGvXDrfR7hHnT@)$;@uSFN)R8WQ7cjWfe39$5;Lhslf|!W
z2kxBMi#{J?Jul9uL%$Spls`nO_?s2*B2B!D_VMZBqv24^5bx5!Zl+lCHn=Z{v;PE5
zmU!qm0NG;mBvf+5AAJGyx#D#iJiI6_K7c;V6Bj3gC0~5`Eb0ox+@+wtByPM0K%v+x
z5~U)mxRSnPUMybf1z-tU4@;%uR@zpVi4RtRrd%wHK&e7p_$t^gi#_Ozj+NqB7Ft*(
zzW6a7UJ?I&5x8n`wF-b5@u^Uls1+Z*4wX9bEh$v4is!uv+%@s{t3Y;L{0uGJZiuaC
ze?ULii$BhVHx1%v7XWcnJVLK(qxf10*qX#85<I*mUM2vrS-gG-{<er6Gf~$nt{Q^f
z4)N=>XYCZ5X_e9?t{nxuTkJ~bpgm#-UugD<Cn;;BPpmrv0Fs$MfEW;`TPYuOQ2bp9
z5Vyr#O0pXgmtRBW9q~U$VQ^Ty!~~TQ@e35D85NtiLUT;KvK3y8i<d1&n<m8lN{GAS
z#Aq0t6kny7?LG1PN8t8-aTP_bro^Xcw>T}Hx&f9MaY+<Z9*AGX?+>q<_{j5c@u7GR
zU2B~aZ=OTxh{S<T0&OMB9l>oUdEy2T_7e3=C^<-sET}k2zSIHWB>CxCkUC4^D3RVp
zvXJ&8u9DR>YPm`9@6hq$NtV#A+C$R9K%J)~ofaKll7w1H$n=)nFhkWxVx@d&U&*5s
z&+?NT^g}23OBjwIJt~o9Lj*`7g=o_;$zA%)!EwoGEdYTM<=23pkjQDc3zAr_!R=tl
zJ6>q^Nyz|xk|RWNy%GjbNo+m_XQ<>Ce>@D6JQUFU7cMEFSXYE(@+r_nN={SHo|c@X
zaCVer_z9GvC5fltQ;g&yC5FXHW@xJvC+XV@pUy}+DYYtIvTr^*=&U591|mVShz^Vr
zB}xilB}v}gh*GlTX}W-VPI8Xo=I14A-viv5B3bAGM5?6o0D34*5}F2`bjhwWAkC1R
zqqTpgWIrW%U63pp2O>-I$1qCSl5MnY%#nQAj#94Vkp$FTlx+ST@I1*1HyF&9gwDcJ
zfrP&vEJYFnWoQ&j4*dj`5=rDGh*GOW5Q@f>Nq(XumvYJ0N|07a5?%(|Wl0?!X;(@j
z8E~yiGUowHS0o21AD~)tPz-#HB>5J4rdIN06HL@eme4Qos^lT9?ygDhx`O4pWb+KD
zZ%BfEg{YTo-vN~diE$b#Hzn3ji^0|?*)jySCJBea9=9ayXW)0UWH}#oEt03`e6Cfp
zjSlPEBp=qpnRbcqEpT^8X0M>3ostc-o#~P!y$#VV30@6&kL3ITh+h2dVX#k9R0q*7
z8Ek+Uki^i~IVidQ--p|8ONwY39g=L=0ZVrzz6SU<Eb%)7wh_r9YRstQ6`GpIBwy8n
zbX?+0Q|yGK;TSx;D@m;Y+oa@Kif7%EbkTz7zT}%Wh$+brG+Ite&d|DdMzX^hfCrK^
z4GhgnKHWge{D+eFpF?p@5=U8^N2J|qaN9~ZH=<-G-9_)8z4R%%f$AU)p!vj6+Cte|
zPSRDBNZ>3zco=qFq;_=G!BzUzTd?aUT~EoA?ouP|vOT0%DXZI4`uEEq^OC+sOJi?o
z%tiX&B0f^v3KV^%J1At}Ctdmx8sjf5=mhCe>2At>36MTRv*9smdnLqi>3}CJ1xlZ4
z#9!ou^vN8M21yU^0w7p=i5CASrQ>5z36Ub|h!;=#nHxl?H1Qe?g-Ku91)svD&t0Ia
zdJ)oOIs}W94mhDQS~`6QG%?as0^nn%>2z!mC*5`(cF#yvbayOXdd(IpXQkiMQYJzA
z=0X@ul%@s&kR+}C9)M)&p%|DrC%s5}_VZGYi)dMjbbBR4s`N)%;igGX&`f7dmzKGJ
zCPR9kLKT_PRTTHTAmvi1E=#)oXVhg&f1o709BC?@Rpv@HG!a~s%7kz`Pimfn-F)fS
zk3tkk_k9m>NvatIu28x^2xLXl+9G&SEZs~Q+$GX$bg!jU`Uhn@mszFNw4W-MhHM0|
zLVB8R^In!l&|kDtT3rT2mGq->l&(mBr?jnVsn?$X)JU7DFKeX{^hd9g^4@~VRq2sX
zl&(p;Vxf6mD!UCwZ%AKVh`M^|uj%l<LHfo~wDYDk_$e4_lv-VWL}in-oZi1%((mbA
zX_m(EK+_@>J`Q}V^x^=zv`v~l2t>QIltO16(v6Lv>69{jq0%MI_!;nSDT|3xkMyb$
z@Lp-v({Qv;>hUQW+AsZxzMe54&7%u&gVMI8AiFJHXQf@vkhI?uz&q0U^rfd^>1ZA*
zN2DGvz{IFDmr`cOq^<&pap{gnfS-_F>V~*0{ctJ7q_mLUn0wM-N;A7JJ^U%irlisv
zV40S-1;Di#sck0U52UB)V0>2kX#xyAl*X*5Sizk1A39z+BHOkNC0kj@9PoCsZzvbU
zUM8S)X$RS+br6oSX1bl`BKzegEV;^}>15kY_AUnx-DQ`)fbfv*U4Vvq$`;TU5WHj&
zl-J@d6F39lBl|)E3%)W{I#m2*m0|R$B!5{<CMu80=KT*|1jr`sL3&I!^dlTTF6-Zk
zx<FasVIWS(GPQUZBzrv<q`|VDpCC@k()!T)5E<t*xKGI*dmKN@P+3Yl%!kP~(`GVU
z_T7DOM#z5p1b|4{hdPu_%gP4nfBQtq!s(7twCpPxM2zgIn-H-w{M%x@c(OXmJ3J#R
zpiNS|?Cl>>IxG9Z4?ZQx{)mH#MA_^)l#*oLH&9BJ-J$zK=VVDVAfK206og(&k)_g^
zf2!>DllY6I$s}oDNtg9eqJ}j?R(=}zOj*?o5Eo>RKaEnBtaTMi*)khi$mPgR(;^^O
z_NOm=x+r^^CdE9N3r+O-GR+uN3S{N0@$ix?G!F1WSv&pKi)1YnmME4jW&u|s8=)O$
zscZ*@RLf*cO4cs7${q~>cZJMu65_JV@k2DUQpTk(hgHe8uz|QDdn*O_YFWZ<SgMg-
zrr1@jY%mi2R41Ew9wx5JI-Y{TYqFJNfM1t=N0Z_W*>^@*s+T#whEjuUg989JWto)v
z)+k#@*9@9uRvq1Cyd_&hQ*5)WdMipTvITTn*(&S)5TZ@Cgns$$vY%*4&>`dRK|goO
zR;1!#m#ls-O5HN&aG39rg;CI{SC&IRqygFfeNY*c1qVUpw#*y~yF;=m`or9jIW<6K
zSa!$S0pN%%LILhk**~=O8k5=3-f~<P_b>1hvRN-6?#f;=p)@I5POJBOGUGCI(0$oQ
z3(zxDvV`Z*>}lEF38>7-zAVJU2eL$eP|wQz*8uQP=1zwJbFz3!B0eJjfZ_tS@;E-t
z>2`8=dVlTZkN*x*2YD-v){gS&-{Fjt{Av15fU|te7IiLio1Gwal}}xOaFf@uQ0FdR
z_Aj_S<iF7|qo@4PH0r$M)jep0w|p0!H2cWEqs@x1+@JCh{N%swh8O<wC7US$=%{?-
zX;cQt4N<@!lka~V_~Y_7=<qO5-gh5}6Y?C&tPGN;y2FcL`QNnaKPfMwrDBM@^9D+%
z<S$cFZ>W4FC7FlG574L;E-&|i7ZLJs`kHm5oSy)e)ADC%){m0UJWZeKjF#&{Q5hpQ
z(e1}r`Be%p#L1tfn>}abizw6|FX!P^U2s<Z4kaQa$WKw+CsE$%0lP`^zv)IpvV8PQ
z)SZ(jw}Sh;{H<P?Pmznih4-oQDsnqbevA?k(&ZwW6f@)l&w<*SDL+vIc|m^hQ6RG9
zvc<q>%fDR%M2=iAgx<@QXVC4si*hFh>hk1oYywTb{9{@t6v%@qeg2ZX)Db=v%6;_U
zE|O<-fUH=4(HDJKBA3$cs8k+I(ZMqLFCBoF%Rl}LrAn(@+=OD4+?8I7EAm@(q+TsI
zQASve{Js-R)XJY_L#0l>;2;oJ<+qPQ<(mA!e}PN6stA^D$eaHMm3nzmDjaQ)+cIGA
zrhL&PSQ_Q0!tt<4{@1@~%Po1#2soSNPVb=9BDcoTCzD#`oF^dK<iAw{*e;LUfyQ*m
z9~=Z}r#zfCQeASp5&*m9`LxmPk>8>ek6!tEuY<c!-v2Rh{qi5DfE$qe4?qmcd-ef-
zTkaT!mJP{`Y8bpDzn2BFVY!5^E{({)vQp?_RQ?M^3&!McQ*Ow(yqJcq3Hc;l?7S<F
zrk~fO{5vy%_vCNvg35iliL%tD<eWcYX<ELQRA%IPUQl@;&!x=dS^49XjQCLgfZmun
z`6v58c0^G{F&$fl%_6|<6amo`f3a6A{~9hjD7<K3c2umTMURu>bS8weqW5q3?V>o8
z0&Z7D4iZKdxGA1k1~1$ds}G^%q0s#WxTnHQbF!Dh=1~Z51*-yZAH|EVu;i;4qR_0L
zB8@hh{)+kk9nC3b!{}4-0g86Idvr{(GZ*HMD<-oc0u?7dhB%?9r&lIOafOyw!3y1V
z;7=;v+>W{sg>N*xIHh=#vNb~$zfrnNnBrh3O5uw3hfs-7_|c#lsR-i2r_+k}e};%s
zh$sXXt%$>9Y+VqeI8H0<Sj8?n`;Sw6M|1NTg<}BP8?Sh}38fUp;MWkTiZ#w?Xqw`m
zR#>{A*l-8tvlKP-ThCUEd<W7zMKVRp@)cT2yDCt8K<kUk3SlJdRw=ITg~}DhZaPJ%
zR!E&8tTl=<`UBM}w$R0~I>o@JKwMRPKzr$HidC~HU00YXqE@fi{2nwL6z7kkFK;Sd
zr%AC<@h+tfG%3F8g56t+!7I>gQB3>6Qmf+k3^b`t!9R&EX;=Jt6Yvg2F~x$r6vt`W
z?Y1gjq#$LF;%VBe^(yXhf#_3=S%L3YT&3O{P^_~B;<h4^#^oVJ>wkej#irw^8&(9+
zmHH7yDxIW`DqcAY_?Y6^L_8c<JV`&K3B`LCP<L0cI1HspMJ0tC?kQf=!O{B)Yc?NF
zO)2bXr97=TunDCHip^qh&nmp=MD?NKdIwbJ6d&IP%@O6Ze9+h`=TjiUUKw8qw;hyu
zw5N4c`h5+%PRc_+K{zXudco<cY+jFsx+$Z+1;AbDMYo4Nl(vNsp31Y<4ZwRTmwykx
zy_KmH)bUk5ISosG%G?}S@>eeZ2;4`NY&xzFPzJX{98(%M!>1F<?xnC4q&!NSj$maU
z{SZ$oEqhTHqI`++22UwB(~=-unL;^P5z3ELP>EFTd>;>^l?NZC3y?9&FuLX%t4#8S
zh*wq@!{AwE^cOInpp=wCHCY)+nUUv|f^j%{UilB@qNFKXD6pNbbf1JuhI0EVl(LjH
z6=+hn@-Mm_m7_HO3$i?AQwr?nD;-~j_XSF~dtkYwTpdO4U!n5JdQ=uEpP?_slqxgN
zz>6~FuTMg?T<I5%x(cN~oe^AC&e7eLO65)Zc1X3-YdHWl$__fdt5r%U*{)7m%!m1_
zO3e@GnQKaW3ftBz$7wIypxihNaZ|aPR%f@ArEBQ@YgRtj3~ySLO_Zb2t}I&tgB{8P
z6fNjfuA`&*F6Gt?nCMo%x*rYgQO3}udPn)yX*?WOa<ic_qKu%B)~NC_Wpa)w%{1JN
zE0+#{Y(lw-R)u$!Y})!vDxG(N<(_i(B;eNj$`KlSr<C?a=u9iqXqhyltYw1jfijDt
z*0ahG%0YXm-0>#FoU-o-9v)Fie}D;F)rnp_v{TLN1>9cs0xq>Ia8TW)an(^3S_kt^
zs@pH)p|k3T1T@J-b&?jWuBul)K%JXabs`$AcUSeDK+!{$(gyRMswz)#d#SA7LwKv2
zX|3p|3Wx&UUv-3z<BqDH%RyrTRCN?kIHt0@hPvab@^h#QRDJys44zOOrCV7+Dl@GL
zLsZ|>uIiMk{CS8_l_CoshN-M68K?|bEuk~&2vuzoyogj?pxZ2`RiD#j9HlaE1ZlJ?
zjz04fquRF}_*m6*i_zXVRUy5UXH=6>=+b!A%}3#Af@&=#sV1t7!4OHRHR%8(t2SN%
z^*Pno=K(mcx=T^iG}X)2A3&3?I>bgXL!}^^Ow|-cH7}?JY15yjDx;H<Y?b^uc$lL~
zq)yCL9SDP^iz){>;CZTqCn54xPpv_B6{x14gNaM3qVLeLg{pHWA&OP~bOcqVx<<S8
za@F$}V6Q?|=4S=zWfd<Hh)UH$`d&qq>cAQ3Tv0t&3KP|;jQ3Diql()IQLEZi4^gKY
zt_1$7>Sx+SUsF}7Ag-&<Iz!x0WqyKQyQ%u$c{tOk+8znACe=3-qr9au4#GmS>f<K(
z+op=`rS)gK>RXy=J5<GVw%Dn13Io1N)z%O5-KsG<h3`=@3jpj@ZTS^l+NW}-ja0v?
zI~8I;l{JWmgQ{m9fr;Cy#W%n*r23M^*E_0m6CRGLcJkoNgi7TN&ATcg1t2F?SMn(N
z^PY-FpC!4kYMe!PPpMA42ustd=l26RqdH3?@dH%=B^b=A@^=CMP<6Qs59d_(Spe9n
zv-d;TtB2iS&_Ufq85EA{2@L>F>b%d<P-peTb(nWiZ#@c5S9Qq=G|)}GdOf_bx~s3t
zLF%Et_Zo_x>iLDh`>3lZ66dQ93kA?meUNfB{MBa4F+8gN^C(CI)J6)O2db-<!0rjP
zg68BP_3K|i1gkx!L3UF8k}FCf>SpS-Fm*eH9>UdmlpGkL{<jJiBCYE03t;fHI=BSI
zDE0q*K^m>z|0GH=>Ss+r#Hx3^0z{npJf*>(QLpnsd*js=%YaK!Ptci2s`_gRH>asp
z^vg|GFY!iQhI;l0$THPVC(#!d)b;tmWvSN}KqXtPp>GZ4sI6shLFTFzblKvfy1X8q
z=Bb~czRXwe>4a*5dgTC0m(;ue23w)plLNLQ_2XVJQLLWtjE5!aWE%QQ)zuXLEK`qc
zhNW`#dfFsasJm#tdRZO!8dxgT&(M{rD)sA><99_p-})JvR;~8=2BbCWKz~%$s(;CX
zs8j#D0Vb}hHBA6sQ;S2;`s?ca<!I;)^^Iz9*Q*zD!QG%P(!$Z3YPT$yZ&cUP!9kPS
zGL5=hYQG;Kn$_hW0oS4qq+MC7I`sj}x2auuR+w*B3tV8SL;X)4Dm&F*Q5dF6-A2FC
zZgn7?A@!*LOoG8)^|1#Ked^aJ^P^vFe;K6#b?4jgeo&p}4)|^L@V5XAsjpLr^^Q7L
zgwn9OqZOJX>RNB8jH-{n4YOnF4cF=XVO+hQ;>;83Ke<5MRrgMya#FpY0vY$zO_UUN
zU;Pr@ew$K{UxDVdx-SAMvuZvq_aCZPFGpkM)SuBt)lPGo#wmNv7D{4s&}_a9;i#GJ
zgo=|Ug$6%o&EsE#%tf;lhbYzsu9_`j&~ejzNMCw#*Lbalj)!K;Rv<hz9ot~SOQWF;
zn75{hmbgBe9yv69HO?PF_-Q;E(82zi*Jvy{s#&xb?LDqpPRH<p8V`H;bV4)!6j~Of
zS#lPd!J7ZYz`{w*hqSP_hG^R7<LN0)`v=eo)ok_xX_)3L1;4^Ie?JGd2#x9h>LN9N
z(&^Y~P16RrAEkLoiMnWnUr>tC*vdhAMstI*P2)BAhq740XnbhsPtZ6}Y%@{Ay$h8j
z%}N{CP1a;Cg627^W(P$_&TFP<CzGO?JqVGi*<JyBn&$D3P)gUV6GAmZQ}75nAyZ>_
z53XI%$muRZmPXKphuNC1C`g~9*>?lnxtiA~gXyAX<u>@6r|F@|G+)y-in;;~kFJ4T
z(u4=VwL*>c=`sL|G-GeWV6mp1Ci)W1LJE_YY8oggQ>Ka93z~9G<8ioOp^4iC{AEo&
zomW<BYUx^jm8PGz@K-b;ebB7d@M%e2qnU6-saA6<5V$(c@$(?Ns<G{cy=$6n%K*5p
zdCmGMbZ%&>=EH8i=GYXt8#Iy6K=r0(i4SNRH81^!hfSL4y`Z_J@qZMeSyMxC(-sYr
zB2%pzSNbn7ZJOJ(tZUcYp+$Iy#^F<RLZ{~VI&@c;hC!RrZcQuQTIkdG(Cgo?`6S#5
z69bwy8dwK4wNIdQTa!wM>qD9?Nx<LHv{GDrSTjvI%_ACbI#3?f$Y?<|rg_p4ZjWnP
zDC|3-Sxy7gUCs1es7z{p2?WbMO^6*z_ce>_;M0_5T^YQe)(p}hG^07#M)A)Fn)hc=
zoYe?wpz~0pUkC0vP0N0WBifCzcxbEjbw(@fv>%4xp}qE<4KV1ST|y}sj#?=tq&jK6
z6T#xFJ@E(Zx@fy8r`T2d3WY=5wB;wj;;#Ml9S9HY4tjq)wddB-`MZ~PN)NoZ)|+--
zKH9QxLF21^%817JX+Ic-s=t<-jE6_H68dWeX#MH@@0gbTC~(KMA5%JHp!Q#K?S%Fq
zohAfnKaGSJ!P;HHcz9B4a}LxY+Fg{GbV_^uB1EV*Y%iK*4bv*}p&G6|`2$3R_RUYg
z7O6c%@rY>cEn4!$Xm`;*J64+<2ktm+!dobv(JtaaC0<)i0g$uWw)N0V&@Q7Kq(tp=
zl;)kJ{pA!ileH%LZs9p?(gpy|Ye$OkFh%P^=UJ&%ZI=K~)3h(!pi9%WI!blP&~9X*
z^_kl0FX&a%)+~TZmUc7sY_?X#gBLm4oiQ+&s|_y!?xHsGPuR`VKAnkP&)2@EgecJd
z?gPzB+U2#dRH!{i%c>&nTO-gc)@J13VTsoI;5JB0wN8PcDbwD32L{WveH3V_&}O}Z
z-n*=goCiyl+S|10uhQP30sV?LV<iC9+GvVg)M(!~f~8iQQi@WYHtu!Uy{avzgV}3Z
z9TyL;YoC4$;)XVsf)w>y?Rfwiw70F4w|rCk6(wvoY6totnzYghJiMj#a)XIx?GrDc
zFIuz*b0Au^FDIfe+O$8?V9>7Z*p9|@Y3I?5*R2ikfQcS$b35$zYQOJBsZTp{5|;Y4
zcU;ky0qyFKpgE}Zxejq#J9eAqzaeeV2XN|+Hh{Lq!&)t6Ym8_eX}2+|eSuD}$FweV
zHb1WQs|8>}J01xS?`nB}f^<@g#2dV7+FxxU?rV2b_Rf?x@k5Ad?I$mRWk%aaGwcIx
zzXmF^+If$G<)Jp?AIepn)3(qm>xk|r9!%KkzU+p1JKe2E&@_8p@&^Dq=oZkL+EEw!
zD>R*SH54Xu*5y*3s*7$XZJAtkO(#+3rhCa7ICtH#I6U;wRlNxFp1P##fP3luX|>_4
zTSM35eRN|u)37e^)on_FQ+~Qkn&JI*UtNOEQQi5+z!snrt6}MwuJJRl9oOBVY?weD
z!ye*<?#?T~1?j$WhrhwPGjE{RPwIBj$P}X6K*=qqbSqbaGgRkHsbUejOB7;>)b*W$
zIIa7Neu&l>ohL2LV|50~>y6Wig>d++?jsdCI6-&x5daf)UA91E=z@NOrA(b0ouyvT
zJx2l8EM3lJSjyJzpAWVi-TWnZn5)}E6YfP_BF&U}x>h=*&eug!7G{BN@gf+yq-)&@
zmO`senhQ%sx@sC3i*<j$14|{kBH9R*>XLqfYh}8NXQ5KA+qVcR6}r75&|KDi%!f*)
zZpn54s&qTwhQTYkel1k0b=E07tkJ!(2)J6^b~+BI(^d4s`>VRSTsU)0=SCSe*L6w^
zP<SnLN6w&FuXBDEqCvMM0*ISBXA#=esB`%Tq)j@Ve@-gX+Wr!#+jO7M;Z3`4C+#Ua
zboE@g)Tz5~5B)CPhi=gC*8NJE**&__GEnyFS}4t+PxopB%=POQI)P<Cm)wQ+4eIvL
zALO<!(}Io}($&#9@Eu*9A2^3~_gdh}h)!IA(x@)UN}0c7y5!HGI<DJ53)KnTDf-Xh
zcXf{R2c6XAE&$s-U41+(-Pc8}L}^OrLV11Dx)=X}Gc&q`FCZT3K1+t9bGlwDxR2;x
zI|DLXy+b{E(oVn74~FdZvsrM)L7zDXGDm&&MvCV->9t>i)LFlk##|S@;T$Sm^>5J$
zlAC^jzV76%U)cqN9{R3y)OqU9(czYt-iEe3-ugxTsPoZtJ_6iVpF~l4KmBPBG|6B8
z`Fi^K>u=LJaDcw!8Q_lTue}d1j_V74Sb+C6NN=V&B3OTG2HYq0mngF!ME@zJsGQRC
zC=n`D??xB@!}LN4RKoSoQb0OF??*I|`d!-qIIR~&z|koE)3i5>)~EWxnHc@>D-f~z
zQ2LBUoc;pcoIj&qO`(c-eKFpN?F-K8f1`tg1ij;Sa3|`2jYnmY{v!e0Pu4S50dY?M
zNd`*i^+66OrRe{>2xn6DKRt$Kr|FHAD5dM|z635qf8Ae{A+R2%{b{Z~XBrw8^>0tY
z!8|>u6c6+DZ_@6#K=1W5>MrSh>D;SOpGaxIMS8&w_*txf{t{d%(R*9KT&ll3jXzzP
zo}Y(OxqcZ%0W0*bbP#%3{{}_OD)q-GkFQF9jSh#d==WOrC|2uVKa7Ue=(lZzPOUyj
zk2cil7te<mSM>@Sfv)Lys$lTCe$!iM*bV)C3R~3c+g``R2K}$}7r3eal|DStsJ}pO
zNRz(tTh!gs@1fbFS)WcXdy77Wf&%UOkN<&6hyH9dt-?C>59-jgE`5{-@ZI{CD7mRe
zAO0!odiCci8@^A!NDO?x{&n24STLaf`7PiF^_xxsa9eMjgHJ>H-SqdkqmLK>Zdjj7
zS#~4(p+^B9)o-UL;Fx}B7<J?N``2J^LhlewS;%+wKR*J4lltE&OZJ|A0}X)F`W;f>
zXY}5*(|Mp@-3FRjz1Rbq5A{*~Fh8dc3qwC0F&yZHur)jx3=?*S)aQY-H#|b?5C_Ba
z^Wd7JVb>_^IvEcA12SjBd-MZvF&s#u8zZg;dx{Ua83t(M?{2vM4RkyVOQT@I)3EJb
zuz4BYpuL#4p=<;yK884oMfw_SO7PInaAZCF^*6|AC4AKI*?g1&4Bft{J7##j8i3;l
zR~oDW4PQ`>(g_1ofrmi`G38QPgAHQ_6i*sFXnYDW?50)gDZ>VPh){!+&KJWBA%CM3
zZm31t^nwV(`OA11X)u2az-faM9o0q|Uc-`dLA0TqK5!Ld*h}wJtYM52!s84t)3wPn
zhWAP#;tdY_(amQK(eztOuo@Q9i=JqhXahdUpxlB|vcWeFI_C_$XyDHq;wJD%Pcb|@
z1nyLW{S4~T3|fkVr5l#hp+|<nbqerI!<H9e_kv*u9eQLL`d$St+u%)EFFA${mtZj0
z(By-<iw0Y7JS;F+z32+WCBvrOC>9#V>14ggQ2iKmiVd+1uvB80qkFuihKID(FEgC0
z1Zlb9SAW!17zQ06E*mN-$D-1}_z>_aL*n01xnelG4y9_t_+zk8W0-ge7HSOvuc8rk
zhNX0Fb=7dpN^|cuL)HeUUN<~RYqJ}MhE9lj!&5S}u)$D7@sgW{Mm>OyhIuqqG#Ngi
zGoo9DNgCCg4IibUuEpRhhTT>}KMn3}hI{_#%63EjJODZjd8P2M(;#{u)Ln+D^8j=k
z#$9L?)??t_1hChTM;qZjLq;On+i%b%!0v$I2_+DN2H*QoxowD|mC}&G9pBztaL3@A
z2JT@)+d+6gVp!t}F>2`NgJsO{?kiv!H^kdOOc*9s!q8nqKn8G=hR6P!s0??qC=2<%
zp@EjUQ-*~JFfnb&n?##t3~{#rd|;5#so$(2c?fk64bRcKYt9h*5SES@*HA8)tubgN
z;C4pO6aegvIh63|VBAM<s-rQ)3WF}j92FkA8gIV_6*uEPI!kjmzGS-u@1KV;`W8q%
zjmtkr4|y36ZG(AlV*=%+`WQ8oXXa}>_W}@p#&OE}^f$&)R?|_VE2Ve@7=yM!95a4O
z+{cZz1E>o$o*x9@gz+UBD1wYmG?WD!U;F?MPa0>A!Cr{5`+uOeo-!U00T^mL@f>Kv
zj0@>lG~C#<4VEH|bLH?U(rBPS@M)vR0hFSQkN*Q;v~iX`G!SDHQq(innCk+!<BYec
z?u_x7bkxNgzoN9dv&KL>_>^G0at2+QX#9#M{UqaHD{#qHqk;}{&KYwKqw>7*2wfvf
zF^1g(Fx7a7u0N(3*B7HM-MI5*&}0}p8sTWBQA62o7mQC<qcK^=N2XAhZS>fPx*X%i
zB6y!`eA6Fw7mbJ7L6&D+XMsw-asOJFFEB2kuDoQl*3o6mLgVi=Xcrl)*+3K<L+PBo
z#Q63w5T!=`W;CYEs7ME*-0159l?r1FB^z8ehMt8=r7=wn(rV*275uF+o=<{Gt+8Sf
zr8=YWDX3gEmRjM(HRIef(7bN+qj>HO<JZ<rXhprTehHf0VBAQP|4k$N2vi%5Kho8J
zCS%12EZs6*Sd3D$u_O&_EymI<P-!(Tru(IB#;APMwHxQrkk(=Jp?ug*qf0)T)Meb>
z1nO?%H;=<mkI}&y@LnU6j$HbT!c_WO^cz2+=;MHK=`lDwXmmIX#BJj|N_84Cx;zT*
zJH}WJycjk{&`t6Y<Btm9M~(hvs2ek0;KI_l@go`vCyXE4g7dC%LkwJ-G}_Zpc+a?6
z0+sv5B`&~C8Jp=+<+O3bEsDa=7~ftB^AC&zPXIA%yiH4khsHwMHO?77q(SJ2>Cgyh
zY)!JyQL;11?gL<Ns=5i`VA^>A1|3b+G*CF1a$kWL&L%lciY_L%K(xixwD=9ExS8hY
z9M#?A{yfZkm|jLsmUV%r=~O&ay-X+FVbI&OcrQqOOz->&;cNOg1qS_0&(hz=-_$vc
z-U~KuqwvE?(+c_;Mu_R$5a6dwwKQRdnpPgb!!XkaboV0M^ap*gIl|OKCzz3@M?6q>
z+H|%Cbx|e`MMSN!rY#GAk2Aeu1D!LbweFyaH_dN@>RHoc-$NvruG~dGCz>AYMk|s`
zzgIye*>r?f7UxVGXj^dJ6m0=%im99)rkcJB1817)BbwXNP2bU;H^U^1g@sI0EJbTB
zm_BwwDa&fIqrorR6q^s#9MfB~=)^ozem5TGn|`CD?*h|bYKTjwO`Z^irf(@MTx9x`
zZh#b<u25r2Ob@3)T558kgP1Z?>XYCuH|6a>slwzt0NiEMYTDscnu0$;U6pAx7q}}X
zt055vt4-DzRMwadQpl{<<g*?+btdcYsJm*a+5~aK^jI?<)|>v=4V4B{tObCZru7u>
zXfzF%!%~x}w+^JYOwlHYW|M)w`_y7u{{{NF)$|CxqHU&sHNdr-@~%O2n3h{<JJV?@
zu|T!U)J-p5x9NQiM32eZf`;~*yn|r3&$NjWf%;8#PeOCR^cLlm44PKZEsfhI&K{@?
znO>0saL4q*<ER@p1yeTRh{^a6c1KO?DerO2l=~-C#!aF7@o>U)wb2UFyQb5$lbtl(
zdj`(jGxbo?+_cF#176IS>U|*|m^NO8rCHOySd<=`{-7IUbEd-|pk!<Ap9g@QIie77
zdvoR>>^hjAp+CB#xuFGioy>WZ;^b^@q8pPgW(!3`UCmdTY5nPDeqt4#x|^RLfsTjS
zg?8?q=6~pVhnKmVrdV(D(qtff%!xEd`I>*D@Q|PR7g{L$n_r^E@KN)dbOaJ$wiM&x
zG4sP2*gbCc_zNuyG|#8d!U^;DM}P}5r)cpo*u1=eZULM$$4`PZ#9Y`6OQ+1AvOp7R
z-dBQBnE3&1&cn@r&_XQ2e2;$5k>)shD^8nDw2X~1r&8Khw0V31NMp=pj_A=?^Kn{3
z#GA7|hBIf)TPg0BV9upGmWgJS8|sqGPuKxxO*VJ0fu(ci6@1{&o98GJn__;Ieo(3A
zp>RA*Gk-#3S-QEP1I}ca@6l0hrukF)&0H|A`VpE1X8kBim&`BG$W&-{qZL?@`7I{Q
z7n{?5g~1Z@JI4SoGmlZAu-trzGK?#%W_#LETsBWQLZ{Naa6fdem{STsQ*HMD19dfK
z2RbOLHLqL;wmNfi5-eRaTj~7ix|u;^=MD3)KT7rH*Zzwlm@V{sylL*g2|%Oy{S>G)
znX@QM;FdZ5GR!xd-!q~SEoR(8fZbMe+iA40&AetOblT0XPe7-`tf85<(>%omzRR3k
z2hwiym$X0VF`uR*y<YQtim&#W{ojG;H-D}K>45ovqfi+%M=l2Lwz>K-_&a3YNx2nw
z%$~dOaM;`xiPDJqsP!)7sM&#n)MMs>wJ<+!jwypr6Xu`E@4My-nxiJo`)HYS&-^wW
zZ%&&(c@?BHW*gd!J}`%L!u+gxZ5tjwG{3eCnserDl(%nd$;DaE0y~R<B02V!1&t66
zmY<$MoulR3<#Y<|Y}xZDiY}HE2F$x!o}%MTH_P`OD7jl2<Dued`F<EQUY485(Db&r
zQEbk~vZxO#zLrH>K<a1tmX4bIEsnGTJ8HTA3`BrMM*-wxmj68g+;Pj(DNqTttfgJ=
z3Cp2`rC;HFuq4nTJlGOOVb+rtQ45+KVo{hNPFen>#EnqP@ONlvnC1HCPzkpz9fMC1
zmiaWpM_Rt_M(MO=S1}AmSuTXYV6?@v5+cUZv=J(?mN5TirA(_P41eSV3!e^E6D@@w
z!<QtBfz}ntmYtNGkYZt<LNik>>pkIan#D{3&2-CqGWeHa`IX|onU(@N`_8h|>_sWt
zvX;I~m}7ZqDKv8}@syWx(eg6|;qom_w}30Kw1k24lI0OA-F_>y7}L>|BFnLQRF+t>
zeBgYk<-i#@Q)c=4JE)XfeprRN3X4+<G%s6<=|rs3!la?I%JK*$CSS2||Awfxte_*q
z8cXNbFi~rn_-}J#`H-?ouUbMEf%=-Im?paGmcky2@!qif>W`+?TYl#P(O_w&z}ZcU
zmO{3TmM!!rZ?e2Qg1TE4pX1<ew#>G|Qj28`9e%Z1_R~+T&GHo;M6_F^v=i>I$OGYh
zrzI^J@GcAY8XWDmy!#XSsmC%(DPX-8;d3<B_F1CzQ0=!=(N|<{TeKapG-O##DN1)N
z-#!3h*s_A6jUyI&K2%06n<(XU+_GjRa1)kz0UqA9Y<Lo-Nz1Y|@Zz53gBakZEML;e
z*0d#iA;gU31hG7@yh_=FvzFs{ZSc<tE$3*9cEo149qiiL)X7k?v#E#x-ri>OkMP35
zW;v}u9Bm$YLpa$idjf3EHcSfoyV&&7H9J=u-5r$NY*K4ca<^IgUt*Vy9sTe;Z9bX@
zgI+e9#?TkuHXPb_`PdXBp-Zg3Hb1Lj!p~-cP9XhlB$Oa>)MhIM{R3=Xdm9Fi*_@zY
z_Hmo7Q=kd7d3hfICv2YI2!DfYyhdR+*v9w2?0cK%DRnHw=6Txoow9lKar|9FZL;16
zF3e`-vtS9g`L+dyB5Z{Hco=212^)tS(Kdl}b{AtKx`|S(O|~BRIGf30SUO{qLjizz
z8_~-^B-o7opQG!J%ev~~HY~Hu^tCK)*icK$vMipx_nuZZ9Ho|{(z0yWgP<TNLzc2d
zwhURy64_fs5Sc0<AVUNMks;vwJ@L=^+<VUXo^$W>8~2`b?hi`JB-(k<5wEj$3-aMb
zlHGZFizVCnFGpvJ-3YB9QthJN1Mi$&&}UFMZ<j`)$aK3)8Tbt{>>LI_GVN@OD9)K>
zH=iQ&*>*c~;oAkfllw5H9J^H>XkD~p)uWYb=g<I+e7mYb%uIpZr$J~H+Qm?stjNwn
z`I}<9Kk0Z-iQPQ9JWB0m&4Cx?c6FZuy25UM07NS7JeNWJlHJq`z^t;f+I(T+vYl%$
z6szsFkc%~Ti|Oa8wewjAn5%ZDFG8cvuCWcgYj(35z^k`ANry-q>`c2rn(WG)K$`8=
zXTU^@os1sU*X>@Vs+=2kefj8Yv-ABB2HWjY>;ZPmu3-UYro-;BAF1N5)6Ufcqv*1$
zp~v}cyJu<1(_^QkEN-t|A#E`G?A|&Lkvn!zehIXGyG4y~=B}L^)w~SY71K+9$S(N_
zbl$V8Y=zsycAMyfXCrp2jzImso$fERM(tj91@r?uuOmPivvUum&rOZnMQuQH!Y<bv
zPEFda{TUilcB|e6%(PvQHyoa^yGdWVePs8_4=`cR=$?kiLB>&9<Tx<avLShhp_XGT
zhZ+071kZ`F<`*b9Gv21UmLrTVI)UrL_=XZiu8i~Tuy>4MeVNueZj1>k)OTl$b^*<U
z!K6YsPevwfY>zWG9Dt%1V~nnKA4Y){JYU8;ze2%}@e!rjPB1E0f}CVHybsVoMrAQj
zf*1>^7&n-qNk%J#Vb_jUDC1B*yg$X*^$eyfjB))k+_r@?Bzqwf!FcQ|$V4)Ji$HG_
z<EusJjAoQl+&zZzRWn8r%jkUzcH<ZvSBS(j-k{Zb0wX^Lor#QKio=~{bj(L9iLp5Z
zykv$eZTnIftnWZl8II%Nr7_}-7}+@nhwh4W8)NTda6g0b3_XN08PdlviY&$#w5`Zy
z^hoh@U0@{r1?(KgL=QxA8E0t2mB;u)0LgsDXB1{CV3Y*|rI0cH4q8QwDoP9#GY*!5
zlrnY{p|gykqNRH|V>l0_g7My;;8ikg@w6hi#8}IOOcmn?N04epoG+MH81K?@w}$a1
zg<WbH%L>qWl@YrgGgHr)P21H5hK$ZrG&1CrWp82}X@Yt)<F5ngY+;1bmhd{`@k1at
z89iwrt&GJlU}SBKwl?_N&RA$u!~8AAe)=yw9gIf0k~$fChrztfI7qjDH=~6<%F)A^
z?5Ep-(MLt;eT<A27`($^{Rq;}m^T2uyNu8!n63fFhq-7CGImjnVTj>Nuc~3j>+}#A
zVK~vhOuEn5{SUktWf;viU_W5gQHE-a;rj`g<BS8eotb15zkq>0WRy?Ciz$ZZE=W!@
z3|3&zFm5-1_lU7?HGUC$rqg~92j)7e&UR#)C^mSAd8`TKFjGLks}u7OJ&B!}{db^u
zgvnV8Nmu5Rum1PN4QB2Vcyo+-=o`qmF+Bny<Ib$4&BAf!QY(lTbBZ2G-pt7zK=Wai
zKLvk%nJ?1^CH$C<7Kof+GOxlzf96wJXaz8Lil7k4JY9rg2QdR_DH6;~_!N2}Ox_)|
zLYXbu^e+d(n9nao?`h`9E|?Eze)24Qi(qcv0WTt%Cpys?#hmSd!9+6`n!t-;a$-PY
znHG9#onih%`JXuEb}GV8U>4J%okZs74d|U^es&K2CNY250Fum1`5u#(!u+5H>Z#0s
za$v!Bj_FwjdY<We9uB87D<~h6!7R1_CX>0~Aw(}Qdly16hZ(vb1}`$7J_&_f=D$Sp
zm=U!1&1Y^P4-1%=9MD<Be1ocxikZWd(kNlhN{0DTW<N#j%9tm%V4ljEuC&UjurXc6
zAbN?JPj9s<<|8U@z08dG1FdSNQ~>NN%-wVdw1)W+t@3M`8WmbsnGq*I>X^wC$iBvW
zpEjTMOaXnhw2`@ro@h<X-K$`}nfV#T4O^JrzX0qyll2{D<_5EmgVs%^?WL_?wlU4Y
z5N&4$Q6cIr=G75c>R|484cMK`-wPqq&D>#zqdiR5|1$W@e+w{}KISwnY40$fqJTv|
zGg}6cyUfR_)Mt<>DnV<AnX(+@9<#C;(8J8uT>u+l{&@f*_nF={N*0YWXQji^81qGX
z<%}~UsRVO^nL;I}lgvBxD16Ag>I}c9n2*zrXPOy9v5gsKCMD<|F;6u>&z?0ym*qj0
zj0HVM)=DbrIK=vuzWsBUl}BkhC)OEyVLG!ao$!ksVdcb8DA<K{?>lH5Wj*yFWR9`E
zq9SiMmfd@hacA*qPw2s7`~VRz)<2PGd9xN!J*f|?hU#H_S^v_u!jC03VJs(DE%Pvz
zlPp;;ECsOqUxcH9tkEv$1+jeTGl0RYr|DrG!diNjD$YY$Cr8jc#Y%IB#%b1j^gak@
z$tIu?!HT3eZ6s?6MQ@^5zrF$eXjUwJ2|R|ijn?9^tfCqyoM8=|gk&7+O<HKjvj(Xa
zIFYr13c$~@${xT%5^IMFlF2MREdWzkJ0q#$CzX{)LH#t=&|gqI&-!=^rX-#9O)E$S
z>kq2X$YkB{z}1q)vZtqX4r>=hK`yd7>A9TC+VdjDo5$*Hg?c`VR}NCZdS@#z3t5gU
zF{C2aM%v#Nvwn_5XDN#@8zN<_W<ET$m9xI5BGU?1?JCGrvgX<WyNXpxvAWBwVl{Zx
zEKheR*08GSwO`AsmSZlivNCDkR>#VrC+aoU*^fZ#SsQwQ-M~twt#cEr(HW$f^;<Rc
zT38F{*x7Z~xkiB9VC{N9H-L@hD+IHZ^%<SXZfD(m64<v`K{m*AuvSx4p_8@x5l9#7
zY08D)W_`XI9`>?U)xiBe*4tc=JFIpJg!QwASHh>etWdgf23V5@NDi`OeE=I`eM?Kl
zd#q>HgN(2WDc*UXWpgcni=!+t1+5;iYTiTd7|S&WFcU1p7+R>`rdp1NtfP0(In63O
z3;h|^V{{=tVjZCGquR4S*@GYEAp5y!pg6Ey@1W(#{&+2*53@fhf}|7s)njNmvpr@*
z;RxF=25!5sgKZ^1b7g<xib*)iK1GjkH@02^QFpc|3Oo<?4to20vggr5`#8JlN$|Yb
zZ!7|gFMHwuT7K+;Z!pjk>^;Arb&?%Taddxn62<ld*b#|n1+qV-Xhaa(E(6X4vu_`V
zdMNwQAzFW)V#h5-GmPy@E0fb~Ej^gS*$WFW>yd0_E?kRZGd9ADXm%5oe#WvD^guqt
zer68T<JbasxE;?{QA{#{?YI(>iR_$pP(RD|;Q=$5y>cH=QrM|<|D>`fXw{I${&61t
z%d2y2=5uiIJo}~1=uKx&rQpKIWFMtNVOi`oY0%GRKi>em7ue5Vhhz@>H6}VQvdbvn
zm(M=Nh1~+SsS4_a?6J?#Dq_dd-Bip@%mOK4e@D^4QZ|d0@@4Gzqajkx-n^Rje--S~
zZGfp{J9UG3i9I_LW2$1$bfEJx`+s4Wi)wcC3AC=TS(G=ZVRuknbS?X=667j-ksb<l
zZ2wS@YwQJiKxt$T{)9m^u@h)t-^^xE5pWB87ERuD_AaViyTR_J&5G?N`>R=Kwz7-q
zUDd|^o5Ex5Yzf7+Zn15Yr|e+&GGVuq?dAsTF1DJYwzt{;WMfR-Yy+Lv>0xVjV@i72
zn=eAIkDW+oqVKS`X`$ZF9-`Y}kbQ3zycl9{2}SE3`$hWX#juUNpdNNd*zOeDzt8qt
z0TZL_r``wX19rsk03Bl&(~5JPt)q)=g57!m7t18O>ms~($o__ENv7CgX+WE1|Eh)L
z4EvYg(R##wohHGa^Ts>CJjf~OfSv<ql+LL+az<zq>%_4Y&}zq-v*|TBe1v18a}6$>
zNmpRIa+dKyj&ee2y?%`IFBx>>Ja!qxozw6pOn7j%(ADY5`DqfJUYw>$IOENElG4FG
zoXSDy`Epj%2?#&Vf-=}W!MWf9a*}gtGYt82zOvD3CxElyAiN0V#QTC7#1Yd0{1DC!
zsu>OCoa=#!Q=D{K!G&=Yv=2MYsap<SI47wBoe><@5ZI06_<RA$D9#i4z>Ma6*#KS)
z=Yy|6&T!&3z>7G}$F!b`=e$q_*Ah5&DtgW(a$IJCoaF?kz>6f#3HsHNIoU@r!W7QN
zPIRVnK71AWX`H59NTzd4w7AUR++6~ZOwOtA;Y=3i%W(`lo6|>?A{RK;r_q_i`IYLz
zE^=O?bW|><n}T|IoE!8W$>$VJ|99ew^U7ZMUBr1;j^1L<MoQ6@a6WLuKubBEx1dqR
zDR>#AoO5Ci23o<1e-8?koC>NaxWpNzBDX3I`w-NtIZxb&_g6T1+t69VIr%bts^$D!
z0lll7v-rl;>^csIzN>PLGnqsuKI%CRl;&*UG&BOVk(0U+GEE#yFl1UdTdP5?a~j%!
zeS`B3U4b__YYNe7<tYCKY2$2M2fcPqj~bG<IORXUZU={V51pNyrKM2l;>@8KY!An)
z5JT$ad^iKQ`#8;G5V76iJV##=?B~3=5acdrJ|(pWIOSBNI>@<A>7gM`5hXV7aekvr
z!7%4@O7Gm~?0N+vqnzif;qL=Z2?ru$oMlVUInME-O!ovwD+8J2Na-_h4>@Iv05-*u
zC&2DBXFCO=XKb9WH-p-9pZpxy2f1EbA?m<=@pXVYa{H+^>JT@KVupvgA%P%H+*-PJ
zoVm-6LE#A3o#x4fJNXf?UAb%N6W7PM&9q&1<IXFDC3o(YOmup1mqbCqlUu(5<T$sH
zZgelM?T-YE*PE-`3F5=OCxC`8cj7S6{J4db(DCQKM&J1g;NF^pp#^dqDGwaP-A0*$
zVD2xUfrM~}=fmw#ZV|o2PjOF1!$cT2fSxy}xj#|nDV)1@6q1qLQQAsJaZg(y8O>$c
z==f#~w~B)EvD|McLve;{q2O5@_u~OL6VKI5LL-42{}o6gcjzT3p5?wusexp!S1np8
z+=dybr*faAms=Wl<OJ-V<Bm|l$a!u*eKsqd>-Gf9XK*vv7<MMtIU3Me+&4bAK_;8a
zYlln@_adboE^^Ps!BQ^Qt_>uQJ57t>d~V)9AO+mTRBc(vb-e}?McgVkkYcWUH}p!l
zYb)VXDcABDuq(JLX!Tvm{a+gtE^%+of@Br9if;eQ+#l)CK{dB}2i00!;nvWKvxYku
z1(;gyPAXo$$}JQ_qmCPL7ozptc1Mh`fqUg+@EW<-=;%Zf*PdQ0&0ODBh_rCS13|8H
zms3^w4Q>-{$8K_K|Aay-_Xm2Ow{iQ^AaaYFbseOGyBFVV!M~j2I#z($#jT5j;%#mR
zEgQPIQ3L4g;l6YNmU_7b^gl-WxGhwqafiEf7DW2F3;%)00C(FehzxT7UJFY@+;A$+
zxW|213D<_X2kb#cxR2-r;C=4&Irucn)we_P0r!Wmp>7-F$`3(fockn2+a7YOsd#6K
zn@PXOH22y{$joq`ZHLGsZUuci!k!ni5e5(P+Q>r(-ot1RN8a{-pnixq>;?71JhcTg
z>dcF#M8Of>ku>PJ@HWuB>B`gCL-Hu^^|#^7F&mF{8$YZYuXj5@-FZ%HF;EZQ#t<+)
zdEZq5`#A448HhLU9vzwT;k}}V316OX3iSMV`%BSzg4eSR{+{Hi9!JZcrz3*_ynB>H
z59Ep3fEmPl`)gnZ^VlJni%?z;l{K8=*+xZZhVdjkG*9ymB%u|~`}HbJMDR+YU?P(D
zLozy}cnjJg63sh&0b`2c<xo66mdB+xRy?nc;^GOsE40l|<bC!R26~nkej8pS@$S=7
zGnqGsHti|AaC#P{@`mV<pT^6u#RBFW?~^NNp67jC1&s{eE~=o&<ULUalEvFi3-oMW
zD+l@)c%$E7OgTLN64<@STfzk|m*+r1#ysBoSK(SduYd&;1-yf_=PBZKP{yE`mrEt}
zCA@d{f|T+?sM@oPckVS>f0pyE(CN_%-q$CfU&$Na404I5_#UEFytO!&JNq)PrV!?@
z@OD1~e`|PuQkg+5?@h{0T;)Yj8lsNJN&@ILUb+CJo@Z17rGdBA0nm-SzyP$Gc;3x$
zrkPhr|KsWg@BA>`e>Zs_FM+46JhvUdzQuE<WBDDtfwwUFPF~ZWApN}69x!;9_cZOU
z26$oTVRw-C8AZ~EcsI2m_jqe)T{O)5Ar>Y^c%f8+cc14?|2kll_niX<@qqW!uV{_&
z%KrzEabE1pbmDk|S56!IN#6f{g8oBZ*)fPt@eWh{<TNk;O=!&Uj9-F0;@zY?us#35
zk5D+sAO8s=4*ZBB49$_hdJj4e@vkqycn|X{Wf+nZ|8p+J;>>65g~22IMO0Dh!q1~?
z+?AiW4tlnu{3Y*T*vI(Jiy-R8zeWRf=cj!D7!Q6jJ>Wd~dP>$F=R1U>(~ECDj+Qt7
zEjqm8!~c9I)P4E!w9WV9cbhQzC-|FUfpU^RSBXx4{@e714&ZN~UpbJ!n?jsH{0|a<
z5^UpV(L*eR?^}t{hw?`$DSnFo0d4HV_`B#wKh57mMZw|x9d83Pf<H)yej@olpM-uC
zUrUvX(fm92ArixXumn>Q%NMQ!Im3Tak0HhJ%m0Q*JYP*k0||U?17;?Xzr`MIpXJ-O
zt%Yb3e-~W>$$ZBZFqp!hMOA{Sd^tV!()h{%_;ilHtOz3K`4gq!rSsP(qcelQf~sdS
z`J=SX&*Il@hC()f_AYc@<gc@Xqq+Q+f1#Jh|7se}<n#ZfVub?!?nH<b@^AfD>r}+Q
z9tHhk{(*~Nmhk`j5I&XivuSHu#t)_7W;x%5p1l?P0;)Zz<a^S^c8Q<97}!;OmnPV~
z%rD*r^=iJF7PD9Q8Y<|k;fqc}y_SERgU+k`bowk)9sdd?Xs+>jU)$hDJ^z_0z%=kb
z>p^cLe=-)GP5duJ&}il_xB-|JzB6T&uk+W9!0rwHm>Hlq`M&8;XywO!0`)fjl6rX2
z&i|zyCT{VQcB9q7e~i9v(aC=+1qxmK`DXk~xA_Zs;C1tV4f`+u$Dg$gFunXjD!J(6
zFQ*sw9sV(@oa*PlK^yzKe4zv|1AITa8wdG+Q+jHMACv)+dwg$NXb<z3jG#5b|CrLy
z_xVQ)Au`JUwjOpL@MrIZhhu!>Rfvr9f1y~#1pjXg&^CLLzk}A)5BbNRz_6$IwnWHG
z^Pi^&;|#y`133JMfAK|t+6!7j0eVoNbccw8-~pve9R)AY3-ge`{Y`)#7GzTBz)3Ll
z14Nt!1%Jb}BZAi`+vFl>qVi`~!7LqGM+Gi&5Zf_90#!-42~@}6si$C5D@+_0#7&^n
zOK_LYt#}K*q@ofZ!N1Q#!&ji8z>S}v-W4Jz1n<0v)=9z5e5m^i%-7Hg5WLq6g+M_X
zE%Jf{NHpPA6O7V*A0n7Z2WF_?_W-zk$|m?m4A3ya)KZN8wBVC=FvA6VDJ&l$c#>ir
zk%BK)KqN}g^fgGdpz$eO0x^P2Dzb<b)KWO}jNs7oFdrunE5M5v<juw;BnTpoKqOI6
zn}ya{K@AN%N$~wBB$EZ{&j30_U<;t_LaIQt2hB9W`^(_PIl*%-kU1}Slg|953pC_Y
zhTvU_;${kF1wbTA@cwM@vIVQCbmD>_lw$Qc0yhOjE(-qcM=Mvbg`Ro^g4_2n`a*&G
zUCc$1V3rayQ!FT@1EM8@2HQ4ZmkPRLAX+9UrV^EM!B{r*D+I~Tuv95XrYfULf-VZf
zR0%c(Lh`cUy+(jm3(l$0c}3tn2WT~dh=owE6KofPToWWx+_YZs^Ex=%AaJ7~aHGI2
z3zAKO+3y3oS+Gn)`G*$4d@AO=E?6l6^M)XXij8gx>}ZkLDwu`8*=>R>Gep`2qZEU_
zCBV`YH<w@*JqkMo%P0udC1}_Kk=ug5X@lJ@@cbO4N3iY#@OlLiR5#ftc%Rb$cLXk!
z#OxQSwe-csyMiz(#2645tgt&MSVXy}Awet)iuVMDB#dHM;L`?6BZB)BOu8?a9|e(7
z!A<(!{{w+B0%T0!MuC@c!HaCPCIsm$h)fF7>G;+|fq_DfQv%shU``9J<zk#Of@<@B
z`FFt{clc&6to$9=2Za%x5Ook%EQU{xLN6-1J0!e7Z^OgFeo7NL3G>KbXQ6<yHb;af
zHp8Hc(3#RMu0qux@ZzYDxf^aD69yDP-A%aD3nOzEe)k;IJ%le%<&&py3Dqszjtf0=
z!1NMM21C?aI4A*{k1&+ZoB0aotp?9e$fJ0~31PDt22To~A{c+++y+<*5Q?xQnH?x>
zr94`YFk}n72o|2F>~@H7cOx)Eg^5(Wc1rjzeZ($ID5E#*Y2hnWP#10!mT!c9lrWK=
z2GPP?N|?k5g>(bN3cG><dPeBH4xMqrFCW60cwsBmIwc5?EQE<f;gTGPoE09-LT8dt
zuR|+YI7O%OQ-q0Hpri`lp$$oz@bWRBoD+6cpmkpOOc+|}LR&WN<1&Q7wBOAXc0U1)
zEFsqlm~7!NrTQ)iznp;G9HCDnIxh;3JrBuTVKxJ;JYoM)wDN^L4j5>GaFY*6q44A1
zfL$b9;SaE4A%kw55~1L4_**I*Tn}EEaQ`G)<-$7K2AHT2_S1LvDuwIo(7GgCcMh#8
zq2B<oFAL=~&(*@7bf8@kE{leV8sVBx;dZUCn;r&Ng%%fhSSMWg8Z2EC{zPl(M&VDz
zP;U}8MS(O67dk_)MYw4jc-Mulw_xaoFfW<vsBQ}Lb0O0zoJ*mWHldmd)7ym>3IyH~
z=BU8y5Pr1*ik-qxdc}4LO>`pewy>Md-*gLaazJ{7g_9t?!qa+S_6gsbLhFvOF%w|@
z!fg}~zbovg^C$ztBQa1P6uwkVCmx4{ztR%wp73LOnGXwH(jhY<%*?^i?hF5+kjbdf
zj&isUgr7YF^JBvKbaroCSkR0~oDk;wLSa(qN@oQh3UymxX-atVakQp|k_za}2*210
zut&m)#{gz8x<r-p2SraI=VY7hAo`F}?T(`CTVNg%6|D!_VNu0wXgG<Urc9-?Xy8p~
z91(5*1a@6Sl0PBhD%$!7$WhToddVCUZCMF}ZX!o2UT_zEDu<qjXhRD+Jw@X;;KgxK
zz^9P(5`~-x@fPi+3&Q3j`jR#XzM^v!eex6iMhA~ih{`ChbyB3<4j6yY)KY*3h+e11
zU7#qF;x|E}m#P61EE=bxyAY9v3cf-`E{mXdN@S$<RG3KEjn-+=r<8#X7wz*#D?$|e
z7Zf5zl1(rlWfT2Q*@0-$Qg{5?XGHB3N{bV@P?jrRltpD{38L#1gh~|26)=BR^ydnY
zBvH-N08JLHpwv~0=pPnHs>mD$lr&N0a?H~?(VLHfoEPQ&3)j*`DeGZ3LnQtIUSx{;
zw*fj!WMlscm~2rLT>=+G-~R>u98qo#Ok5PLqp)JGXya;-Jkc-o<%@ig2OZif5M9OM
zWp<%xias1(Bs#JMpv5Bl%ixuWzM`VnQc>nAkTTIaJBXBvE>S5&g=mEa&Qyv}(Stip
zRB2;lpjDy+mto?v=-e=-ty*-{1wLKDj}EjN5!VV{t!Tk~kgFnf1T58wPBQ^|O>~#C
z0`(#}y^I?~<#d%aii*1-*(6%{6hy9z7AeqqLlj8$AU8$RRQS>=8bRu7cAMzW|52@P
zyXcP*_;yPaI0|PvMEzxOu~XEtA23~_rED0yEh?wQR=22#!el+7G8Z`7D+;D!%s$Z~
z`q<|kk?}f6zvv?u=-m|!v;k~DR8ODm9TZJ{1cf0{=?C!lo~ZR9EDVdDUq|&XBcj&#
zVE(>HK^45CqQkTXc_4a@UhQL|)N`;qF1l2Y)`V!t1H4Jm@LqI26n)%-&M8sWIMk;_
zW~!!~5iNKCyN^VZo-k-H{<;_Bpg5nFgAU@aX=CmvKCm2a9};`wXpe37VexHx$vBC#
zX=C9me%%5uj)*5~f#xEPr|Mo;F^@9PN5xC&hjABQr+lY}_?La~!c%<rEYy#Sm)=6B
zm-zJ4m@aQ|Lp(Zt#Ib#t5?^uf^U(7X&)W*<6XJ^ffIcaft^m*GFW!9>CIZC1G|)it
zm-H4668}Vd>0oi~cNp&}@oEZIgo(#!uXI|ROSy?~@t%1YQ-t_qid964KM4kCl=#xW
zFcB@zr}O18;-1q0ixunX?R`c(bsIj#iFZ>bH(vY}kp!Fg2Vck}ihq3yqdzPDa68bF
z#EmRqCyN8-!HX2}OLY6EiZ47wD^0wUuDNsK8~+0Iym);ChL$eQcm%x+@eHNPGsO*U
z5Xln%-44BM@n$;lc0s(GR`fYylN}^4iifX2Bv)+npt^xPv0^7=^2JGXT@{F{!=P9w
zK1B(<B5@Es$&1C0Q_8zUJkk!BQgQhJT4mxlW<bitvA+YfLOjWaLZ$d4+D=^(o9OsK
zmDpSZ-evKwm*8);_~$8Ds1Xm8!9uNgm+cAAt6~Oy39U~2@_Hy<6F*u6nR;=D3gc}M
zU!}}UqqsgCXieh96sc(zTWEq?#3h@ca9#WZ1wL<x+ez=H_~=vcqE+lR2X42CU!$CJ
zhxnW2Q12AK83)NO@wz4Gye-afutC3DJmd$^9<hZUy1il@Jw^J&u5?-65pSYepnfs?
zQw;mAxcnW642Wa+Xbp<T>6Gx0c>fzfyC?pm6)3~vGjt)2h?hPMl>6e5Q{at?|5yRN
z2jZj{D2#~@Q^aFjoHt1)h$qCp?}9lgR=ozlABuxa(3ldhbp@FgKez--Gvc*=aQ~6G
z@E}0#CGO)O2PNUO19Fg<D6s7)nVf>cA;~*bm48^$xfqyEl9pufoF#v}4d^41<LwY}
zk)%-?!Bz6Yt5kn>R8q1YCXPw$D2n7J*<1-3cgaCIujC<-P_o)n@;1f#k4rKrz~v>`
z7>5yhOD=_j_(-0j)vT}N8QKx}Nj7I;5>80mBQe60k~w=|-e2;?G{6ER({F$mC|O6@
zlOV}GdRN$jB_VX6D@2k*C5WLC1BH)HNp@1~JWMh`alO-$<XVV^OMEG*5g|#q3xko8
zEIN`NC266cb+lwTeX=k{68!}fVkP-hByvXb924HhNe<AaJzkRF56lF~2lp|EM9H^l
zXq~l5Ji<VeBtItsJ6ZBw1}vpWiph&q$xX_Prb%|v4S!B@`VnBxOJ1jX)pW^oc_0~*
zzk0ySlzc};hgp)xuR|nT;!DYp3zD~tFrOni|2ZTtN*d`KmbsD{GZgY9R}VrmUt*Kc
zzh*0t?4*meSaQJ~&Xh<#mZ7s$GK;FT$|SxzXp~D_{lKe`?5qK=Qu6ab@GeQlX`@>u
zVFiPCSrSkJOVyIYe`ADKB#pF<tC8%d(+{<h5UNDHDp^Bb)JY<mL9R)PZ28crm(&l#
ze1qg(0yG*Wp8fE<NfKbjJU2@m$H8lnd_hM|uS+~>w|+ws{UvxeB_XtWZk34gq1PsH
zmcf~J$<zzLyd{aH?No<k{W?f?N`4%Ihh37PAk6P=34bLpyCsr$ZE&MU(mM^AUdaY;
z$n;6FDN1oiBBdBwzr^(4jVC#J1R?{Hn^avtC{a>iY)Ha?7HIb*8&87_OZ4=T8IkOz
z7yW%n_u~K?l~iv*>w)B*&tY&(62-#gjY|sY$k>Er-VEj6CncQ&Kzk?|wm@`Bvh^5z
znwEsqQ(#8Y^%6iINw{1n+DlcG13D<JrHjo$+R+c69Hom>(0NFD;2>IurORle>Lfiw
zTViKv^?ppk5vd!!_FbfFb?9`J4pPeOsMH7R6P)#w1}%WTo0Ojo7u}^#wnD~3`o-ty
z^pvjO3cJUp8T-KVlHOSg;w@eK5RUpt1xvv5lU}Bq<An5!d2sur)Rk^7f9Zx#VIn~4
zZ~-JxdT%*8gQU;Ww~vCQ^Zvz<LZk!qp0|ZcpQB2fQ_?fErwx;~yb5w!8ceaqaOvaZ
zcZ9U+1DJ@E_RWFaDCyI50wr1+P3zYfX_y3)7c1=)VAyA*aj$_FCv~8GNxXDPK133v
zLxpH1O6vz9a#m`42`EX@#z451Y?CI^(<epx<4rJArEl87ZkqJdeK2@Vdg42@&P&;}
zxl5PcO9ys_G<OGhnbMHgp_e7CpsKQLsmUIa7o-DZB1bBteb`0m4vOsNN{ijl%99RL
z{b#;(Bb8MZNDHZ;qEKoZc^qg(QaLU6i=}OeaJWQzn8Nd=(zEnHE|dCE*tkNveE=pZ
zrR;;~yd-^&GFes9_pd?WveZa>o@%Ku3kI)9=iS23R3lB#L915k{yJJ$rEy}k>ZA*4
zn{Z9q5d%l-rH^cM=`~2#Fkrq>8bIg5nxv;_gWfEC{WXvl>Co@cxGudz@v0lrVg(d$
zN?%-tVYf<GMZk+T>B#4BtzG)#;{dxQUDE))4(UHnf^<r4l>6<HE}%WjZD}7R?7OA%
zDS-7z)9UE`*DH;nf~r30vjQ;hNViZ5s$VL-402cMPm%Be=_dMN2c=6thKV6*xCaJv
zPx|8;%*C+u1BzvhNVk{5r~6XHdMJ!aQ!hZ_fpk_l?2bvDW*|8(bzBMFgp@@o+)3%%
ziz)v3P&!Vlhbif-&G2Gc`p-Uy&PaFVLgtY)kAj=_GM}Yz^q}lHIty}0Hb$p!56i;*
zVbDodvJ1pnmOwY<5n0;`v|MC*+C{p`ToT~#QJFj$<d{t14-q%neX8Acm;H;NnQgX*
zY!B_TJ!Ltx2RJSpJ^>jo*<Dw(yk&c6S?42rd@cs#D-+P`%un{KA4E>bo=pJnq^y#5
zPX01YHADhrN~*yPly$#?$q$lkp?}B_EOXohUWiOiOQ2BMRtm_SlBH8}%@!sbp{43+
z**E)u7A^~0fw_o~z4s(Yq--9Af1+ej1t8Hf@oMPD$a=pAcC1V&1UVz~c@rc~=0oR5
z6J<kh0OhQ#`E4j9$zEE9&Scq7gqb31J%S;n%9c+;Bu)016mFlh$-<~s<-BYn0VG}a
zdLT?>$c9eCr%ajqV(4edI(~v;wyf$CkPEVAiuLEnT&dRUqU_WZI&)<&J7I)*vW}P0
znJ){Y+YtYci;9H{Wu5U5DUw}J!K@X__Qv8@E|DFe-C(KA_7Mv*WwP>vXqL+q8=zPr
zGtp_8O4)Y0#V^TpI*3%sN@=TiS@t+>qN`<2_JFw}bNdav8rgTQ7)-6K<}|#&DtkH_
zoprK!dInyT&AbnkdKu#b@ET<Ge?q-c=0-24CK>)aEvBYf#-%J-i_ESKcCX7quS4dB
ztdCL^H)Sy%Kx>ulbB0Entb@|L?Xtdfh}@D*8PVAxYkv~vJ7sGXFwrHOLpjMFS=l*A
z_R4-TV7mHb`x1e2N7hTRzJ8hUCy=``@kVdn)SI^2YUqu~%HDzX`!aPVc%!mk`(XWn
ztd?TAW3o9^YBDbSc|R~GWNWD0U{aPn2=Y+YMC<G+naC3;)3U|%gUraTdBf}@Su&L~
z+RK%fAaYPX=NU|)gZu!^vZMUV`IwkP@=tA)6FDrOpnZ^&d^>IZo#mpdz&;|+{2dxD
z@>gd=-&Gz$g_}p^PkN(uOumppU~clQwP?A^-==l4hdh*4PABDMzOd^r=RXM&AV0hv
zl7aHgJ+K=j|92}~3zol6`I!)T!~3)c4waA7gYA_3x2<S}$qOlIds@E26XwI^zfu-4
zLSA(X8j*4>E#RW$g><SQTK?!PMiC?beGI%<`SY|#IwLQuhcj{V^Y$R|@-KdZLV`S=
z0<?+p&KKa}S$X~!AW8DK{-79CvOMEQG*jg1Jm{y&YiRM1CV!O*8_vnUq6)Y3@*ipK
zpDw@k4@ibQl8!HB$^$>ZV6x=jIKxD?yulMDF38`b8!ksa@GZ<=luIZqmn&~Siq1TF
z5j~{y<v%Avp-8^sGpYe9mam~NHI~T#q}6k&+>cK7mC1uC!C5Zv`Ww6oc|09&tdtu!
zfp<y%HLWc#%j4`IQY}yGg5DLm6P>fIk<Tv&sg-xoS;?#Nh%vP4<Y%Zl>Y6;1iU8{6
zMHE_TkgvAGSZs}Q0hMz#$+yvJzgd2P^7bwAt!Wtcb@}JNgV!qe*$G~o+(Qm>OMWOH
z`W^DVEpVn&-g+M*UGgZ($={ZLXokPt^3B;m>5-RGc)C~qfPxEsa(xSUcjWDHaIIfn
zP6NDalP?H@%z)g9DqRNU_RRntlE0;gZ};RnIyyNlUqV;#h`ePfTKDAzfj}FT@5u*w
zAfHWTGh_1FM=(DwpF_9Ngj~KICMM+vx}fk-?pp}VDfw%w&^aylS`FwKc_Ih1_DF8i
z-$e7EVuV8d4vJ?_LDW$ZK(Rh2#V=vtIV-l50sDxepCV~4iun|;aaDX_hNYv5t`9-n
z6(3bX!9x){4<eq5`0pU%t?;9A0UyOv<q+{z1dGt}Qyie5@PuOXRY;yx*xO#jl=>@z
z=p0XgV%`B53{>d9f!{%j$GRXItT4}oeuzSI1tOt}6%_kArC92XR+wVRHo%-#%zXgK
zaD~%*P>)a)cY#DI1}<TQQHqiv@S+uJdO^o1_E2R_tm3sj;GI!?A5LrVI7RAzSz<-#
z&p=C1+@NBbM8!W*aP6$(tJmO6l43qx>&c35l;})R{5Aj+sfyX#&`MLN=%sW{ak&rJ
z=M}sNV5Tedm*8lI;!g@5Whw%-n4m1h48`HI6+INZy`Z@N^z7$wcPIuCk(-^T2sp9%
zvBwtKW<CO1kz!FYyeL-umI;^=g+~}%D^=*J47yD5P98+c6`#cdyF#&%78aF?G>YzB
zQtZACQl+@fhWcg2-*n=xT9HP<>MM$sR3crY__hzNTE!v?Lta&!$p&Vf!jBTU*A%bV
zPD8O?@j)o&t4Z<v3bdLPLaO6xQLLv0&2`26e2^Qc1BU)hg=GyyS`{NT0Buv;m<7pp
zg>D=}>Qv;<0%(`w4SU$Vt=R7dkwHcHTYw%?JVW7+dx|)UM&4KaMakAtMa=W`1)K*8
z1%2;$Off`fImQ(Q^xm6L%vp%ml%j~D8q<o$DDO9;P<{Y~gGvP*YH&~<pktwq${flS
zA5y+J3UXNa$yR_lDSxPiq^I(E+E*V})=~1rOL^d3nD<ul&%tdUrSJk(h4?Cerv$d2
zQcguFCzSq+p?Fexw*@Brl`hXfG(dSA5%k%C$|aQj2vUARQIufi#0_+YC=dJzgQt{d
z!qFL~{HhGU!D;0MidcjzPf~qCgtDLmtw`lQdcede7yCdjRvD2)RUv1To&W9KmDg{>
z(|DzUCMrRxT?k8w${keJcvkreojgraZaW9GWM#P+`YFoBQ{bg4Z!bhEO}S+iM9wMm
zDSmifIfn}K(v{I|@F_$2{W{pqR(>Xg<VEGuYiQ*v!@dHs<tf7+VG{F|D*D_+fpQjw
zbPJUq{fbE_QvRd{uUJ{R2B0O%z)|RzDy<`Mv`nc#4oAzCkyIX0p<GLA*-GV8dtvvI
z(sKh8s+1LnA#z#ixE|2e%5<uzyP|x@h*pjAg=^r|+LRydg#I;U#c7Zm$_QFg-&8tK
z=DAh*3sn!aDPR8^Lu*&|Ux5BC<&Ji=I+g7k!Rt~kZi3`(Wh{Bvt*m4KyGJ>-8l+eG
z2CaVklnZEmaYvc$0EN5C3X1y=DBq%0@1WAgq4oWcQcAIrd&<SBFh8uErkuuzGWrrg
z?<@aD7wM>Sg$G&>lr413c}$t|GiGK&d5-S5Nu`Qj3lEhq?+0&68T>pvoL1gqV1zTu
zAO8XLBjwe<LF`pqX;pSm^&>?i98@pZ^w4)yrTz}ZL#n&~qW7@sN2)`1QaSYj)L9kt
z8{9vl@~5lJMfI~kBwbZ5b3oix->-!io~oJ$z&@_BJ%tf^sn*cR8*fz*ZQp!U#S~ul
zRV}2N>XWKvl%Mfe)ld{AK(&Qs19qV5+B;wdsl2nG7_9n|4-%q!gQA(CDi+<8r&Mn)
z2h3^J2*qN<RWI~IBtkVS2xyV2&@Z4KrTXSAn2%NsPr>aNRU$2=V^!&qKslqb`yD88
zs<)OwAztPEI8YK)RwI3f_pGX#o)k%{Xm|7`s}7g|lcLf%12k3jvK*~*ssj{6I<Hbu
zEH_>CcoxtyRBo9N$y9}$fnJvC{o80|tNO`cj_OBB9bHt7P(f|3N=}t+c`BEW;aa}x
z>}PPTK;?&(xNUZ!%AW%hWvbopVlK*64kch#s6y#ZuT;&^0sE3l^8|R8RS)S!U#+Tc
z1@DTgijFB?Rn@VfUZ>hf^+DHEXL`Y_SMA@8AvLHT(HYey)zK>0ZB|XvX1zrf_!&@c
zs#2DLXKPh$G-5DqD()<3w5u8@I(JKTIUgDws+~)q(Wz?P2hrOq%}GdhtCmqxyhrt2
z9eBN}FDQ!Ar&4BMX6~py&j#sNt)>g&uBz^5SQ=0*q0G}gRXL?shgC_JfHI;=p<U5^
zo9dm<fjz2vq6^Fis(A(I9anu%`K$@m(^RG~sY-eWA`eyb(*QH2`eZY(AF22Suw<`(
z<-hH!n!ga84(d2QymwTy>6v{<&Gv<PC-uICkaSi*?hkTA{qrCsUDWSTEXGxBi;0G)
zoB9Zy&UROKQaPoE`fm|j^i)4_0W!zcTdW{nYTqvCd#fENN9Ln`^%_J@sCPXE^^@wA
zdtk|5y@~cX0qWN&<PfNSxB#8O>SLZz2vNUG>$p(0B>*H$-TeZFds_XyjZP?rtDRjj
z`4Q^CuVFq?y`>&7QEI_5@M6@@zKhOS^`a+X@QnKKC+Lh*`+7qpULF1^^b*v|J7Msw
z+W0mMCaLEUSh6~amXRsyFN@$|s`_C*TIbb+l$c3Z?=}J@Lw$IK4HKNH7LZJqdh|W$
zXRD8q-3#ieP`H?*E~jkGMRhsV2j!~YqNre=`q^<fldpad0aBnoMC*(~^<JtIFH#>%
zhNWWl_{ZRts530EP^$K&=xMonUoqUSP%l^xdzI?lYv?=lm(<R*F|Ja#x<Tf$I^r~#
z)#~3|p?^ianHCB)>d1$HsZ}3{hxw~&1BG4d)H7S5a83O#EyC;7x2YPeLH)sBXf>*z
zrj1OKx`TFJ&FYDFfzqNrOGTvD)mtqfH`FhoTGlqZRc${FnKt$9LX5s$z4v7>Z>j4j
zZPKA$JPVdO)!S<^`Yv_b=iuE|Z=_g3w_5%&O!TPdjsm+^{R-7e^{Hi)aJZum4243!
zdbkH8yQ_YZF8KlVhYLUk)tqG@L+Z};K(P(0H{62ai274{$=p{5Yrq^+e@VNmakaJ-
zWI~;@8_rCs$LS^WP`!#C&r@p8Z{hZ|I-KH`GwPS=<@88BLeCO=&Es3ZJE++~#d8jt
zC&QrNsM$nb9MYs7gydn3W)3=?Y?^IU0^zLrHV)>GXyzOP(?#>qCb;ja`G8K&9o76u
z1@*@?9VWEgG{-MM(OuJY8`vHiH`*(CYD^zsFvm3#3ZQ#w?o%w*Tl2jRuK8%PV&Jx~
z=1MnOej4|BfSu5+Tm$u!8e7>}p!sX2BG3%b+@@uBpoU!zjUdgG3SI<j@*lyc5RHO%
zgQ1!`cc5@ebAA{kTyvib?;|vqDbyILseTcXQJQTO1d7(&S_zaG%>{Zg#cJZ|5;&uY
zp9Ax88qXVOC1}EI^hit8q{M)n)%;6aiB!$IKCqjnS@I*CIj1>FyY=&$xM7SiUE}dK
z3}$Garesm3<}2FfXKBX%0a~`E`8*6>&<u7$GDq_=8(<eTJo-vOt|oUMczGJ90PylP
zF7#w6(A*NysenRF{~m}IX=Z;2QmlEi2qsE2Uy(+s#(x?bWt#6R;bFPP;V4Lj=I9+r
zR%+g*EAWy=n+lOCjrB4VE^8jAZF;q)_f7DwXvS!7SEG6EWr);j-unuztD09v;8UH3
zSwrj3Ynn5(RIS%+I0(|9IYxW`M$HS98)(wh*#WItGZ27Qi-xlciq|!d3>fwe%?`Sr
zZ)$McVzH#zasnpWG>M;r*RI)28O>XoWfq8ZX!55p&Q8s5bcCx*vv)Q`Zfg?f&cglI
ztw~&u-X6_#24H$M^N(X_eH#2n6x>Ie*>6F#U$dQ-B6l@&=<6{9nwMX}bPsBdErr1$
z&Hg)R-P3HXKx<g@9nI*7#*W@!_cd7^@OM<>wgBXTW*u$S#x$&tU~f{>O=o*-4>d`&
zG?>zS9Skz9N%Db-8I6`IWFBcYEC#5(_H8G09@Orqgsg*h&MWZHQ9D6pGl#TY^td{#
z9UFwYlQwKC+;-N!?f}UnTHPc%U9@x3(dnuc(1G=%+JLK2IHrAC1ZX##)`PAVckP}Z
zpy8p-{Sq>sT3a<-Jg!}^A9lU8zVz(&)+YT7gFf2oaE#DbyW_utF|C%~E+@3J>|x@h
z_Fbx~^4D&n+O7cYu~#4&tbLwVlc%)940MKRpP;4fY3=kGK!<B>_Vh4`(E3w#RHU|p
zf-6zlbb9zjYh72O6{G#S7bar0CdwzD(I!!(CQe&JLH2lUH{HGoTJJdU61ARB!qKzZ
zk9i<T+FfNZk*pO@LNY~rg6gPJwL54tnWinHwC*`=zD)v|^IE^T=uOuyrK>wb8%%|a
zncAaGu$!e_u@MeuYd@qd<^^p*BYeuy`cT;PqIMxg{ByOxR-iLa>#!1?`P$_R(OIB9
zavUgy+NVpwE7DeR(OImOQ0Tct+er`kQmx@FiprO1(>8*XYx~}Xeueh;K6p{7owEi5
zy`=p>3|^JC^aM06YiH38s9O7)0OX3+!2s84w7s;1snv$;g~C;BoC+v)+Miwq$~A32
z-5m8=8!h)6w9oUP*Qh=8ICxFkUjr#3)~pq;g{LjrUp9l;rrkCJOSiNU6jSQZ`W*zX
zQ@exiqb_X^ZO3kFYiGekw{{<`3VXC~OEI)wEprmQJ}rX}$sui4JWz(UX1el6w9njw
z!hNj|<<G{n9?lrjxONgjUz`fi{y__jN$tv9c=}NLl09Umv|kLsnQ84izTnMhXVD7#
zk#?GPzxFzNnv#RMK^a;Ox(bR;IO-PA)Ao?gs~uBvShqVBUO4HVtpRb?)l)Uf5uGD#
z;azlFX|v&~Q_{J0+fkj2vdhPGN(Icj>D(#r;I8}m0nj{j8mckz)XiOo&f~hIW)Lr3
z^|#RX)@djM?4#R%37x*WmuWxbr#n6y<2|A46+-=_u6GSg`0MKESWJMf-v%!Nb-7=_
zry$+cc-RZJ>GG$b5u&TBgQZZN>kt%A>AH0Q4byf03UXTa+75Jv>vsOP>Ck<zL@QDk
z5Q`~|((NmUdbIA`6X=Z5<#T}@tDE=;13jbLvJoUsC-@&6jn^rD0!h%VdJWDb>b|90
z`>f9P=BIEfNw?Yu`pLTf_tBf88@vY4R9#mN%%|xZ<H0+p+qn|F^E%FX@X~c3Q<gVF
z_n`q^Wa=`r(8|(9Z^R^I>rPT+_oD7c9!Rck{jcEV>8`MVlCOK8HiZScZ=5muLS358
z6*5J-R@y`t>$<l?rbL%+k5QEBN;iO%>E<m)XSwe62N0>yO??3`Ds}6%7}_P>b}GcL
z()~$=-j{WPm*8);E^i6+uIT=xR*mlLGcZ`ITlEWEyQ(t>pjD^KUJ8Y4x`A%`N$PcO
zS%7KKEv^M=)G4(v*rdyJ2CrE+<p-D+U1<T#U)Kp+A#y|aU@Lexb%Q$0MXRp;B1GDB
zE0qvw*EKeRcT2aG(j6VTsPiz`sVnh<Ubn8|6S&r+3w#wKy}C8?=~QZ;E}R0zcXVyE
zuj$trDJ6MVm)Qc)0p0UP=nv|m3NT+oy3tE$-P8U48(PD<vvkH_L??a`p!apDI;fB8
z7XAs|1KnUJCTL9O84i?jox_umoX|ZYM<;b@6nlQCJBLt~ZT6JzmqdV0>w0d&iy2+6
z2%?X4&(NCKUcZ(~fez|VhM?0yznb3Sj`~#k9?2p7^Unh9u>Ki5VrDz(*Zl)8ob_M)
zi_RnZXuMo!yXa>&!IG=~DL*J2)!(Mtlw*2NN&~p*)2W2P=B~fK98C}XqB}6?sh@uc
zmX7P6qA-D%e$l_s@Yc_!YCRwQnqmAfzWPc!>f@&`ABE&ez3*|T`|CHo3y}c*MlpDS
z`fIe|4AQrzg9PiJr8jhlKK?84LiOK8LE)5sK79ou%%*>rru4MFi?RaY`lWH`jnKb;
z5px--cc&~<l>UEI0uilOMgk^A|G5|<v3gSwVB+-&YhgD*|N047O4P3pguiF?nin9F
zq}MzIX0rb8Y&e>tpZfz^sru!<5J}Tt2!wjN-uC@*C}!v%_+y4L^=+3RdO@$EO=XUL
z<wdx5QC~u(u(^6IUC4R*ty|H`*MCTpSfF1;!Pr85MkaVg`jE$<SFAtAgh+{gI~7Ef
z>i;-`v6Sfp=&@d|U;ZW}EA;az>RYK-+j>DS=|8##yH)zdA7Y@F^))GIRqKyY`O6i3
z{^J0x(f>^E)>?g(0SZ_36%@9u(`yFNx~6xcLtFKFAIgI@=y{((vQfWy7r>hIx!<AH
ztp7FyA}#vW%R#Q|S5a~C4gIeP6o0v?=kx-tRUc2AyEeTql`gjH8#o}h^cF{ecIX$c
z!?bnk$G3rW>DT@Yh1>e?DUaN(AD=>JkA58+KSi&8KMk}`f9p+j-qG8tfYPsj<~y|R
z>I>;Z69f9AkI)*_Kl{mlRmuA8T-d#**U%GYSYN&t!yeHedL5$o^_3LN9o5gL=+y(g
z;!B8(={>)J-En=U8hR7@Llh*O)Ze0l&4>E^2Joiz8+kyP)<;riaYjEtTdqg?NGhGM
zH*~cD%+YWU-+QsmK4h?lL;tXWN2zWn!;BK5&W5)?L+gkkq77cS82+I=jjLhPc}(|F
zgC9NFju|rOWR;uY3{}{;8zP6$@-R41xvHljvmYqO4Z{Z^>17yv0z7ZSqX1y~7=Bv}
z6kkK?2t;gthL`9ud&2PNe3&?Cm_vC-e?yupS^)-cdK3m4a{oeSkiq3iC<Yr`;{X$4
zs6T*Fgc_F7tL~H`lk%!zhLxKka@sJPDv81ke{F~P2*c-eQ$-rqQdMM>Avpo+(T1C8
z(2KDdoX4RNYvBD2X1rmcJ2VmugWq6g6AfAl_MJ5>q*Y;(VG$j_O*T}~x!V*2!w0QY
z!!HGBr5TFm!QgpA?tXNp8y5Wr*D?%!>!6ouxbX=LW*L?=!NLVY&NLKq3|G>iaM57<
zs}SaM4HITC^9<i6Kr!FoK|!b@!|>;jDK@N4189jsM2X5$L*x;($_&+1>Q!z~ECZ=9
z<S&8Sl?I_5{JmsYu?a(~GDP}7{jy>2>o8bts9XuXD+U|g2Q`L<aagD|d~EB0{#Apv
z3L13=bpiCR8TOKBy}|!QxYl4$QKGWZaG5G`n+%x~@UYpCN^{X-P<;Xu*A3D%pxrQ>
z5`lNqpk9v7R)b~?m~DpTbWWq)&_KnY9R|3I+sJV0ACPXt3&C_MpvPcOWlFt<2f5Ji
zGraaL6z>@3x&x-)aGuhScMTs?nZtm=wFQcUhVLl>H)PmJyVrY$H2Qqmu%WvdV50^j
zJ#-%!V(3u9n8AVW+i}B6s%M%o4ARIZ4d;Kx5A)CvprNYdDTBjeC{7zZKZ4?nVaHGK
z^pPQs0!{YDaav_L82g`vhmJ-Lh35_#*Nj5su+e2V6r7APf53#Z@!4ZA;c0XbfE+g#
zHbcbA$k+uDZ)5Zs81ymj%Yb=b<BIvfJZap3#H?+$zfs)@{QzU;E?@^5#rMDrGQO>b
zXs~gV5|tswfJA_X8ku@@o-%SN(->xSqqV?k<I|mJg&PYBff8X%4uYjfV?j4Mqm18B
zo+in7U<m5T#yw-0%2cE7CdQIx^xlR}(K+L2A2iMz=ez_<>Bib8Kr)Qs%YdC}e03f`
zvy8pBF^X(sZy_Wv7?=D8ksM<emCal<UO92_Rpiln8(^@&sQWK{VO&bvj3Q$wZ4rx&
z&b0U_G49?Cy;9?ntMH=C_#+uAHy)1yufq8DVW?Lc4WZy&GPeB#LsiDkg)n>BxZDVl
zYU7Jk{C&k}rj$yJQAnQE8hI4#zG_VU?=f3vEGYo<n$eSTUiHSN+mLB6Cd~tAqp_HF
zH%-Qy6KFLXj}Abx#TZNb<eSDyTF$i^bE?tVW(@lVBJIX{KTOaqW1cHq>oA_12hwSb
zOh;#z(e^jIzioVlD$}}+2W&RXMUU|eZK->WLfRzt8GmAe+%bOFfzE#81}dYxYn+h6
z;D9kZ3I+#_bE(F0$as>nm-mdC1sLeC@ux+&97l|&=-qVRxVjPQqej0d=shr&P=;d6
zSn&&Z<Hp;s!ix!G|6HnWnluhy!gwDVy`F-`l<_!yd3M_P^&_}8W9+9*!y{v!28#Bk
zp109?(3G?nA`Yha_Q9Z|Y3>V9KV*8Dg58Hr-c(KEWIDlxht8%BN}0Ku1}ia$qbC10
zcyY}1;s)rsnfybkvcTQ6+X12;rVoCBjHjt47zU4<N+_7>W#Z3*hPSEvD`@zbGFPF~
z*YpKdulbqA_F-rzO#e=RchdCQM)>4!GMnH`faw_uNC%oSUIhs<{YAfhuu0?v^$^q3
zD<Bzax)_d5+bL7E7hu9n!~5XHX_NeII2>*|M^)Gnrh1B4Mw;9xXdPwRngqMirYX9v
zVoVpqAQEemQ%vZL>G91Fi8CEth0b`>o3&^qn6`#OGSQUu3M`y8Ia8r^l4))M%qN>_
zDY}qiGwq-<p;S{DEeX<0k~ENWrb!madDCA@0h4a}`*n~Elc*J)nWjG4CS;k$`k<d}
zdW*^iE||Qw!?he!+-nfIXwvC1Yq_R8DzD8m{cXgQ<eQ=uP$)2cxCrJ8O~+`xTV%3%
z(c7@tw3ALom6%eg9;(#z)$<rrnQ1P?z{*X*K@hDl=_7$wX&R%G`Ik(~>FiaNsrhf1
zzhY`GMC+<)&L1#QXIeqQ<7=j?v@obQ)qe_u4W<X7z-%;)+=sm;)6VaJ(rh|w>q4`|
zB-{ZL*G*OmZr(6Gq%#pWO-*+p(`vd(Pmea!F{(3YH_gy{{+3DP49O1DT}s$@n%<|l
zK$mIHR{*<hIz}_wZHia|FM3S*yJ5c9r1}~PeI`XD$Q@I}G$i{?vpj8Z@vi9+tz-sF
zucyI_K~v7ZFgRrT@Kad2XWBd$BEzOMI*>AA%A&{4eN)pF=#QFoxoABw4TPdKW(sKm
z_PFVN3PDepO#cIK(o|2Cun$fB6u6u+JwF!~rcHSiM4B;uP)~9EN2V8OPik+r-i7Ev
zv$6+%JD5MFfc9Z?)*PTYnVGMEIGaD&024>dKU@aS#k@Wc#MOL`iB30jA}s^m&5;yp
z^f3Q>2RtwHD!Syo%}sPJ*~hHdfEo2QpNayQpLy>%oo+c{jz|PEz^tVOZ=l&_8m%C6
zW&_ZI%{~-A2{E5nfP|Vgi-3K~{5WkW!pv{b`th{6U;#kG&HL!yj4+ERbP#DycpoBB
zW&u?*N1JmmpcP{-H322o{Hhd^XUtVHjM^4w4!Q!+cyl@(ct|j7yP%(FZlrtcta)`I
zu#?QmEodd1xBL%iDdv4tke+Jxih*95IfeE^=ggsR;AcK>zLyG1>E<kYZ)TWpQA8@!
z>|umRmU%BN)w0d|C`f+6JV*<_9GiI!y&^A~Us-_OT=RP!(8x2t)B}=lj`0O4F#jk3
zDKu}Vhe?q+jUH*m=Dl9%EHTe1forAavTk&inct-cYq|Ljy-q63D?}ib=9T~L`ORTN
zFkfZ<jB1uHn~Ujos5aZ0DcE<#{QV7(8go0Pd27uNDDiOB?64Ci>dcofL-CsVehP+G
zZ&n7Nv%!448zPP7(0cHi%xx4kZZ^-SE3n1<Mm3zdZr0I#f5UwC0NidfH`6k(-MncQ
zJiKKdqi>RRm|blYitaSKz6fTQxw9Jjx6OV}VJ^DOv+1YkG3OC>uQ{d)Fn#79snqz6
znfDVe(tdLlZLIH_|Drt0fH^M=V1wotDWE-M-n0N<_sqUBI5TYiA`4{1Tua|PzHh!p
z-_aU1AKCj~9f?^<Il3{k?`u#THy@{E_k=m>7|5jAks_TB&HB4goHE~RhUBz4ny%Fu
z^V~z=Ju)AC2t9iXtmFQ%ta}>%I#`k@o#tp+O|`3sEbTNGhb<Rx!>*IX`~|?AEid1s
z(=A6Vt72iv#d70qXt-KVC4+g?GM65+$1F+;let;Grw?DcTXLxE#>29Q^5CA9?#r-y
z+)^HlmX}5FGAwyp3>2&Iu>?>E%-2#fiB3O@JQtEDEPJQ|_oQX^MmXbd8Fr#|T!3Xi
zJt6`v*B?S7$kI$lbAv74ybgmQmghRq3blMoMdzn1vr^F+X4!rkXs0dtCjk>~nJj`x
zlw~!AGomfww0DoOY@uH}&QcNyUcAM37D$5SBYFlVSsdxjo@`l9K>}NfrT;bbrdocX
zy=9u^6?&wdvq($eOoruLA7&=gvWCKXS(f&>5XrXOqw<OimXR;O%duqBitnPOo~luD
zEvNshvbAK<^EKbnB!;B|i$n;23oQ$WfKp_UQ_`o{BBGsbiOmw+0%objM1kHi%d>xh
zS#F8G4eSbwV>a|FEj#EEx@4In1Fy<bMHRf4Ek9A|VzuP~RhnI~d^CX3*H}g<8d+=E
z{uG?KYI)~Jh}2o$p>H-`vph>7w0cXQFBBRqg>+E8(PA5-R9%xr`7tz_Evst5Y_a@9
zo?f>ET!i8c%Vo+g-?aR>3#8R@gRZMKi!1`X4$H5n;C-j%EqXV0S+s8f^tNTL8l>BD
z#}D53SY)&v>a|p_M`xeKi+s9cd8QkV_FKNO(PQhbWrjW;HDGyf62l&}OsSwTWa%%5
zYxgWA-mp7t`FA@kjaULjki2j4p?t@v<tySnu;kH0cg(V4A3(<~kG_HWgvH($l9QH%
z2=E?SLbd^V%JTCNP^K+IT0qZO8t2nm@u2leJ479<Q}rN@)|&T$?PPUq!$6&_v21`I
zu`W3U4Hv7&T41|czc~ZmQR`b2$~tD%)56Bh>hnEB+^ycvfp}PV4x!W2x{5M=$F29D
zgIzD{=AZE^dt068@Pv<b@!NF&`C3P=K-AB=hF-=etiSyNa?-km9^wAhW-Ca5HR=`&
z23volJZXqE(-okh)>bN0I%U<-t}M*DlR_+~t=V%i&~WR!CMZN$o7O`l(pnu4ktnO<
z+ZbT9HNF<k#8@X#hGLr?Yu)xfde2y&T?zd->to&^@zzx#kV&xeR>M-Fb#($j&ss;R
z3NFcdf(Z|kt<Dt8NwFT9fn=)nFIv2(SvdzGa?a`y4ZZW$3W_|WTRrYWJ;OQ?iq1^y
zhg55vWgVb+x-Hv!pHg2Jthy&)H^=(2A7n0CJsRL}u61@1OypUaKR_hk+Tw=J0&6;+
z8?y_o;w^wFvRVf)&|<6nEF?>;o20N*YVE&(R+%-Q(%|LR^)~=rVGUA)S7rT-g1A?#
zJr{vlW3wKjqhqz!-)R+m)%xmpP^_~SOJL%f_5D5Qthb(bfJTFLY%w|;t!>@#yUFS(
z0q?ri>lzepSgp(9#ZBvbluB*2KDPv&ZPqs_WYKOdp~UJf>mn6II;{2^fYNDwKxg^7
zthViRV7ABlF@4y(*ZL(b>-wx`w9vR~9d-t9!1}-AFh6MhKS$Rcmv#01)ub{_TWZ6y
z%=}uKW}22(W~G(cG@rfq-jCXRP(VQTRs`9Ih%z0h2r^_3K|v5uwu*>=3d;Ju&+o7E
zI`^LQKIh)&Gwwa-+|RSd9cY6)UfBQ>LpxUef0^x$=C2?*yd#@VRE_L-eKt@Y?|8cp
z9**t!y%>GtJ9;Q=G_k`~4X{0oPZ&Vi%W!vtGcJt#j#j$X8RBZpr8^^s3Qav2&$)y1
zVkGs$8E-~uD@1)5qtC&vKjW=XzyvTpd<6yr89xr8FN87oRY-<1zIzGSVT^z2X&cVC
zsY2f&#y7VB7QxuG7bJ?YkE-&c8RzNJiDC47PjQTR#_3<cCNR|Fz)oabdKRNN%2;p(
z&LlJ9_#np^=~R1rf-y+PVp179=?fKUj3G~OnT$XS^s*Q_dXS%FOkWIzGmJ&gqA#2A
z&qp9<8FQ$5Cx;RB|9fx7)0D%>W#|u49y^~Ap9Qvn(Yy#Q7BYUNC0{YakK*YijK~N$
zQ_8rBoR?DtW5#=cxytz5hEdcrwDgp3V4R~J%r!<59olMS+^0BkGh_4bu-n2|F&jR$
zGVXXl;ReGs87May@6tiNHbz@Ltv}lt%lyH1FutKhL?<Ko6!g0og@3|)H{)Gba6OD&
zl*qcxkd%SD!w4}zvX{~G1?=8sXsiJ3V<dZG*!>LUEDYj4<7ukk7+}o30O&!+Yd4`V
z#E7Ai#Rm-TThJS3^oT$lBaEE`0Da7;cZU8LV;+5<ahws)g~18N=Wk;a&dl$tp}2>s
z`5%1R%k-usiVJfWC5Bv?Pi>?th<TNc54kf3$)E?*P9yYWrV`kGX8ae>^J4l_@X4DQ
zd;r9US+W@Fz7FOaA~@{F?4u$ef2QRlcoD$t{RA?BOu>491~Cg*fC*-{%|v4e)4dt4
zg))<m!)_RpDFivd{EO0^2bsE;(HGA2aD!wd^EIlPJ<QChgZU`tAZ0&dnal6PLLBq%
z^U#ZDI@}h)(<984-@;N7vo{F(N10(NprtUi{pdT+l>85)Kf(NDHDJ=2^S*=M8B7+f
zUo)93%Br1WE~c{l)6DQqKsm!aOHZG3%pxkvJkNYT8VWhgr^+Cb$DB)nxQk4epW#eC
z^J@piC5o8RNMK)LzDSSvVy3kOq9shHN_bJq9GH#9GUh$Hf6JL03_z=32GA{D$()FQ
zr7EV&a)?wjk8T234U_o?yr^X^P@=DnDffdHSD2fr1mY_5nWsVOnW29`vVpl?>44%j
z<}w$EHZgM};Kg<3tf|m%W<H`fNDI@K@+Gaze<^}@gL#?mqnpeS%2&2A<2J&XcINNt
zFww!Be*+4g%+e?{b}^lNKyEQ3sWAOEbNwH%aEF;mC#U<E&l_O&9@C?n_J94%qg1Sa
zpP3;5_5kziB_M;$zo|ZHi0S_>6dy2!kKn~aX7m;`K4NB3z0NR`^9jfZa~2)Hd(7;l
zbB0ft9x8C7%<0o%cZ@lG0%V-|K`gwVVBVtS=_K<jD(P`%WpkZy|LtL2YQ|vpvSR27
z<-+=tvSY5S+fA_R#=@EuS2rtzrp=wTeh$z)SdWS!;>j9dgY0MNH$u{j6-l2{@McAu
z;e`+Dhc6-N%bG?nH9yvVU-bF2B1+*}0826(BoG#W=?G#CHbEws)pZ^kA*{zAf`qab
z9RW-j%Sx%m1FSD7QF4$qObOv|R&f&S9%3!|7cdd57wu4pWL-OmnK{hLWP(JoWOUy~
zv+C)LcMR)wT2IBY#;m}MV;!cQZ9Hpr2Dk(V>y0F^iL6H&m^i}v=N*_xV%?&!{83iU
zR{XHZtcQQV;4#+Aw4q619cx76an|JzfqjA%L`Nu7SzB;Y)+vp3iC*;StWK)x%3$&7
z1(L}cnuMcSEU$e)In6pvFPAf{Nef6e%TXT-n6s>e?I7n^i_XLS^Q=WSpyjZzy24t3
z_2wMt=d!MD!I<(`z84{RktK7$-+WeaCO`{V>9m(FWX*GeND(XR6i_a)*4>ACG0U5(
zoJv?KiV2mnvL?`1#>%HspmNq)$6j<+u-4L%?@E>|1Eh+@s6=Bm>o6B~Ygi+cMZC=V
zmP$TqSqAzk>sYQoVrW-b|I$9}Dr*ykyXsl7wBK!DJ*FheHP)jqK^j@pSD>$nC0+us
z>ntS&_nTQ$D0J7ts_~?%qnoUqddRe~%xfUi&iaN<!FRAeehQv;vbG+8i7pn8GWFf8
zs$qckuyQC$cZ>DHv*^3ca&`gQ9oFxM(Adi=r>pxeD~1y1eJm9nak$6IqHt9|>pM!Y
z+-E&QFU0|tt1G?#23cjl!tWv0zmyAoz|vEp_(N8I09<>-a&m#jFiUw89*(e{xdZMo
z%R<T1C#-3-y%}X)(!kOf>l6AHx^dPopThhE>%jt$NmkV{h&Z#A^xN%WKOX?^_p(j&
zo4c@={zUITSN8W*wCl$H@e^S0V{dE2DBRh9R>CI__8Szi^<<aOLu@~Lfdu+qY)2o6
zH~Z`vDEP3G0%6IQ-QNQgKQ?D08vWT<smdaN-FOF*fo$n*hy<}yHli_@tv&&f5cWJe
zHtPswPg#%7FgBC+y9d}W9*3s~*@f#d7vby`T#V@u+cyj%5$yGzFcHaqm9nOX*^fU1
z7sb|6-Dos>n2Nb$*qwTS#<H`21sBKug&tS&?AU1_3GA``u#m`}aTj1m*s^DVlI&m?
zZh?to>^D}UHHG~neS<%hz2;dAJB?kv0uHCMmydv)VHZS0<Q&`o4Zxgd=Tc@Rhy7k2
z$OX3hyJ*a1Pg?+z$3FBwU|wXWQ4BeseVmS(7O+bzfmy_UPzvr6JE0677PB4s$Dv=s
zUO$e`QufqN%vTxvl^?-Xu=hNKXeIkFy(FsG=L%uInw{B#z8dzY32^^1dkbZIYS|Ch
z!R<QsFD@A974{w@`mVB{+6)u*><cbXXkh>Uhjgy7J(huMWN&@}U`^~_9Nu8Bv(3N5
zL^GRz3GTPBPj`ZAW&d~|+zs|JS})vWYoY<##{P+7(Cut4RULG&zos~GC%b}vv@W)k
zmQLMlKiW+8u)|`YcZ)sM3zE0lPyGV!E?Yy%(?0g}L`dFaCp6Ggq@SG=hf&;T`(^=c
zfSox8ZjgPH@?k^l>kA?BfbFyfKkP$xcr_Xyu@irX$S|8f9X^e)|6303G27OHseHl?
zT8T**Wv`u$#xZt7FB-?$em+2%U|-w^GRfXW>du_q-#vr-&xLb_5+1IcV{({q<NQu<
z@qL^vv*3(7r@j>?JUHj+W$wwzrU%@9&Ze~(g%>Ao2`qVYf+(lr!`U<)#FumWQ|S3|
zE>QK3KgWFl3IQC&Jg5h9UK@s95N9dvyn;CwQ3LC63gIlLP(Uchh3<|pjza>)1Dx@-
z&^X9p(>5iXb3PKFhd6rrVIw%ddcaa7r<FqX(VYLN!Yziw&_XYkGmR2x37ooJAc>q=
zbjIKa$3ayk$(-ksAaaZ&7C<kBGvzj*9jTnPSJ9fr*-9TmNauVLjxl9%qCB8+lJkHT
z%%?bh4`A>N=f=~pl+BSp5B;;8?w?`e9A_(S6V7ugJ_X7J&UbI4FPC$i4m9U+6kH4<
zpVLhtmIBU_CBQ7?tfHT{h!alHy-N;G75!W#9KRa0mU7}GXf5NcJq)`QoGA=&m7MvD
zpjgG>)55cwv*IU!)^Lg_8(7O(NhfIPIIfh0yuvv~snn~S6OrKRIW`IcH*nlGp|Oec
z3ze~4=QPnHxS6woc3dqS$6DGDwQ{7ig}K3b?hv?}91|UlZ{xf)7b9%vc+dm=4kywH
z8oeBC5y)MR9(!@8K8~#$diOXw+L+(xoTd!c0O#QXaD$w%49v^}PCtD=XqaRE4}BvX
z#tJAr=G>!b^AnD<;}kkaIr}ouImUT%1fGs_s>i`ia6ViHhbK9o({s+5+e8=J9&Xf&
zP}s}e^*gwI+-FB&$(`%ifJP5)JzXW9+{_`U@8>p&;Jp|3XG&svb4REM&WAg>6?(qh
z)pRN#i0k(z-G9N{_SYa9!VRZ_`cUqr8_)>jrql!U0CxtRjX21a)5ap4yW})X9O8QX
z0GMd*%v8)%3^#QpNGx~YEbPW{Lufq~&wZ~P&<WfPbmJs)H#Wn<5$;kMND{ZF4I?|w
zeY=qEzZ2XBN+qRog_N8~<4#=%^Xc3yTBBxgkA}fuCU;XY6tlRG+W>l!E1Lx98SXz$
zAlY1HCHl^CKhH$pIc~s8pq%H<r>eUg?v5YOc!68s3dvlql4^eQxPCXFaFP2RY5^Qh
z`CRh?bQW-beTdc)t`jYoOSwzwG;SI9))BZ?&W)zZ=L&AQ3}}^HPkJ&{aZgh%LN%B9
z3_xqRgJqb6tK4N&L{QJ&M<JyKZUu$cu5oWq!+0CHm+6vk;{JLa9$x3Js(`wqnJX!T
zi59N&IcT(VuhU+wgL^s;Xq{X?l#V!caW|KMbaQ>Sf%I^vQ+@3%?z4Q5+uT07;qP#3
zDYf6v<x}H*?(-&a1Ki&tVQG*XP2ssA?u(D$_5-e-R=5wjU;GHkM-J|e#h}C7&*|m(
zge#}dw~TVTkHV)hZsHbbjB^*Q0@?)Eum~cP+!V^SIrC;w#BvYs46UU0^2VQshzn28
z1-2`%l+w#?yeqK~+0RRf1LwtiiPqcRyjN+5>BE~Fj6PqUL)Hg_e!NBW@bl-@dcolU
z-t6m`i$LDpH82>)3rWGS5Ae3r)9WD5o(QyX-VjAo5Ah}_+!evg5(7Jux0D0*!@T7`
z!9*0Vb3FzT&)Y+nUIOoXy7Urx&$L7D2#-x=C`r8695<nVlsB7Bq$Klxy8@VFyan{w
zN#R{<0a`k*iw@&w@OU9`IFom>2aQ?0!wtYb$;%#wrBl4XMNl}+`;rHgGrV>WU}y6d
zWx(KhUTQMbb9kY>;4bi@X%CRgGq*z_k5>>u0iTP!TW&zh=WV7_c?G-!3qcBbTQ6X|
zMZDFN{=dXKMPasL-nGpj6}$u;8Y_A0>i|>5^C`vzRr6-?VX1~UtsIsv^WLQNV=Zq5
z7Z&Px`_2IK8gGQ&e~rBOeGqBlIT@*r@;YxPojPget=SB;7G4)s3%2r(Er;R_9*=S&
zoxEKXOYY+R^eRX<?>Rd1-NSq7eUMwcku-qb=0(sN<PNVaAL_ll=eL5~=iR46`~y6%
zTA&Q_exSo2L%dm(TX?{;GpFGGd&t|i7lV1kJ4TC$VO|qGH=gjmq43Wr&$=9BjQ8>+
z8pnC%R7^9$du<~oVUl+b`$s2t{%Kd3@ZftLg}Nu-P8oy!{M}{{FaCGepzh80RzSpu
zFV@4ZFaOOZNc!=uF~D^A^8+aA9KaV+<yRoTih@Bw{FgH^CBgj9FGDeeKkX1;!uSQD
z06oCJYX!_fzRNzi9nQB=K;RJn*?&MH`C;^!J<Ol=CHkWHOCsTK4BzPtP-6Luq`-{h
z|4q@`c)oykJ_!zfD%JHT@z=})_EG*B1X-Mt`Pb;Re~e$G0cZ-p{x38h=U3BrtxoXU
zZvriq|C$zhY5eEk!YDHMlUvc4$^Y2~lEvTm9`sJ~r$mFC;^%$<a+?3eU8raCqlFMT
z%fFz4`Z>NsyA#;w`FH5>a}NJ~iYr{;<IhHLmGWat;8PyIl}_AV<R7QwY5Dv{ioF%^
z=g?cJke^9qSw;LZx}GobH`Cs*nD0!lj1s<@BCVzTr)i^G##cv!E9Vznhe!o~dKyG3
z`4Ns4aKDOwidH+-{Es?-UBkahFY`KnCuOUy@E=pI?kYd^CG^$veW|**f$!ChzH9u$
zGcbxKeqt8-uJePtFwkcH813;|_^x!^qm>^`XVz};xpH8(@%t&1+|K{-e-P>5&#R>U
zUl)JU2WZ{=E+$%g_%iy{Zt<7h0QPPE&7<hM!|(8gWH0~Qk0H{>|8yGq?(vydFqnS+
zLV9Z5=YK(ujR8LIPlychJ7}T&fIt0Zkca$>{t$V@&wdf+hxzB|w;$p6zAyv#-zb06
zt56){5A1~EI6s~yVS@j~Z{Q~RKkkLTv%q}?xIF>~Rr&4}*#Cusi=c{v$F71@dgHkX
z+QZPdPtco(K6k;Pc~I~WsA%#%1#7tw*)K3qpw&yTf?l-Vf+HI!|K}qRbVJcsFn0-j
z^AlX5WV63u9TnjP2>x0H5-6A}0Zfo!tp&eYu)uT;CPD;B-@!zvpfd`fVS+pJ(0D))
zD+J0x!NR+k^>9JM6Z9Ptn4f}Vgy1iV5Jd`7KLa@|Nb^FUBTBG>%59?sr#`}*#0Yx!
z!$hoL8Kvyv1g-S7#dyJgbg?D~lD~zciGrdrpdAtTY=mU8AnQe_9}~=^9b1aPM)iot
z1+U?3lhX;oQQGLH3WjDtGELCB8DmKo{Im}!83HRU?lK*M{lieq67aV`^rS#{8=a>F
zfs`aaEeN5w`We9;TJmKJQWTiBvjTZ5(9Q`~t%crs!ALt`as;KnpznfU4FxW91@mdk
zlqcw-gIN~^)yv?0zThEMa1;pk4nwj~@Wd0276}}x0I-(?fB8ePSnxibH!cw*&4m}G
z0w%5Q$^<LuQCcqeld5<s1e=yXq*5^P4$RjGZY>A7EC_lZ-q#AY&wxmsAoO{VD}vB(
zA$e60c@Csr@F)f-4T4u2Vd$E`N*Rtu!FI<a+-MT~J_o<rb%ALgI-3QSSD?`%I6%+*
zR)Kp1JiH+YdIN*GDfsCS6xsx@e*yh=!Jq~T9fBG3`*aFEpewLTAUC72TQGkrBzpwY
z=$i?51j#4C^$IGfeCDp8V<ANP1mEnY{QEt@YIpc{U$BUl8v}ypsZ?`Nu;OoULxQ!B
zFv16d`<=jkD3GiH%&_3}ZRn2(1}NG5SP(`v`%eVRZ$V^KFrt9lV}jt<ATlAC>WjWf
zfiuOIorN!Xf$SA}A@bqmB3$|fecjwu==~`a-GoVWf^DDhISM3t2&>M6cnaII;P8Io
z*g8ytm#~mts@}qwbs#>%ca8zgPna_ab${V6i(xQ8cxxsa1BJiR${<L{rK>Ag_#MTt
zLWNH#Y!oIGPs02GVI!N)kw*v%X*U@u+^_)}hlQWUpfgGsKq0(nVe(mk#tQe+wl_{F
zY6f<^@b61NOAs=fG5SQ|l}a=o5q41dXOb|7UQWrv7J4Ti6Q<GRrwHGF2=(K_Uk5RW
z6T<96P)`$fJ_~h6y6~?@P|OhK(LghWi?%@{OL&uyF`X3Np*{R5VbbSN%ogsVP4rpe
zM?d2?I43No2<>^{*+tOH5xP-|B3F2DJ;stJbfu#e7lnhn(3mgW{0<Bj2$QMwqfpqI
zjlN4l9^I+M4k3?j;}T&-CfHKp_mtl)6Rvv&2Fr!3sMNDkm``^_l~77G`_;k<dI((>
zK1WZzT4C1+9IX>RX~wXx2*0K{##P}qs@`c3E=>cuCY;^|$wuKls-0*O=F$G|x^N37
z->F&XXrX%5R-vr|*f)eT)abk^oS>r)ZNj%`W6>@Qri!x;;dF{zb_v(ahC;V6VIe?!
zgh3RS>lJ>o0eW|Z!T0d{_6cKYHF;0Cd^!~Rg)$2G3<$TJ1=yhQgBQUK2}OT^JP>v}
zb^+$0@NFa5M?wQF-G+si>6pr6q2_H2^oj8I58&FU@ChB68xsytjB{N09C<h?)PDqn
z&LZPAc(_L-S_3ckiacHg=OSwK!suN^duf1fqGgm;_7E*T3=5v3SA!t3Uo`vwzoX(M
zDqRWITV$g>v5zS3E@XT~*C@H*C;H!W7=^!RGo|qZM7kQd7ATU@gE2@n+6e4mk)sfj
zA)-t=$r38sS_Id^M6Fbwdq8yS2J9XbHNSzzaM9W-4EK=8@H*^8h*U)s|BMv%X)&h5
zqO@0FB1&|d-b2x%s#^e!5v|yTzF5&>dhf=GVoO2dMd}J*Cy1o90!tLVLlrMaL~|%Q
zpCpp=pm0?5+hRDHEUNeb-X9YcQXN-{=qeR?92fmW3-l8r1C|mFr&Q5GN^+-(vO1xd
zE*jeijSSJdw9LsAWvqi}mMEE`SEoha1w#LfNb&<Dvqg<`Z=V-^+YR*`k(qwN3!?XW
zz+DtM7ho>(MPE^oR)NSm1h+4Vrqh*MEILQK-x5)9EEF8&qHWV)sY3L^=P*$z+D;4J
z8qsU3!Ce+b3!q;s`ZNVIb5-;rZGGxRO_aZH5V?H`{U%YDGeoY7R=xz%ESkF-A~!@E
zQlWlR^xj7RYZEn4#HC#{^#T0t5Ur<k9-X33X^q$A5N&uGGTov#-@(v&M8)}lxg~nb
z8!p}!Rc1n_SM*;ZxVxg)KLpn&x=g{dd!mndK<gKML$8bhQHl(DgQ7ZmvJHs>D0Kcn
zw19R54@ISS;LIbDn+SG?Mf&dnHX_=*8I6xcj+qoGdLmk>$0Ur3(#rulCi-e2ERBnP
z3;^haD5(;nlcH`7`kcj1W|-I`e*I&h?G>vVAmS$O_lLoKVkzx~-No<FI?zL$NM((l
z;>!wf`^A6gAn7G;N{6JkSYQE|uei!Vt296HcN8x37w58JDL~vd9i4&V-E<oViG3*T
z5-dJh3KAkdO*i}j@%9e%9Tb00E1Ga|-4!TAir3KV=&<-al^#clo#R2G#kYdc7b9lV
zRT3vod;;_F;x{RHl^~A)o9bT@#Yvx{^N4uw5AY&MoOTG@QSpKm7-6z_3q_WXiEZ=<
zPZ8%+bpE9Hd3s8p63?JJ?zGszM&lWA3?&D$#lGJF<*c}zN|w)wpPB<p=fy1AN#uxC
z)4^R3@1%`PuJ{R))}MLefndN~6!R#IlP^9#3cm})&(YJiP+UF>phe;=Pnf?X9%ewK
zSp4OS&@T}`pz_30ad|tODHE4ahO=C}^&U)Ah?N6Ss1%!jKx38IO!Z0C;*Y6XsYd)=
z85%E(C-Uk2S1aB|HGo&eyWfDNdU16GJZ%s!=tpCdxRHV**Tp(FXf%t@TtH)s_#evS
zwThRO!O{)!S5slBU0l=+pE|@3sRp7`{Qez~E^+?=B)i3tVNmZ8cg%*uE%An_z`QM9
zPyph%BYuA+?DmSU(Cu_r{D=;8_KD|yj7hjBW>EUFU%b2-F!#k_TOm0hHqZ`rQ2c~I
zhs1h2>^=~Cr9tGOSX>Kd9*Jv?qHkEdfYOg6;xjKm<gxfK`WVv_vEUBKsCbYPJ7W&<
zXLgtv7oVZT(uDZ0By>)ScTgFOv*ZskWcEm2se#{nC0i&E;UZZ@&sSH8paBNmBu2W`
z_DL?6!>+re;(IiDNaE?{@|0vy1@V4KRtqe6N%r}o(OVKnX9avDhiG}@D{&mAy+?q=
zi9*VO5(|AgAxQG^%V-RiFrwi_h@^w^=%JGL<-iV;%)bZ40}}T=AO|I%7(l`$AGkyE
zkYw5+_!}Ylem*24B@5O;@35qZ7M@X(3Cb`=OWdR2Z;a$cdQrzpzI4#ZtT@R_g%FLG
z><I@<g5=7Z&_5#CNKug_Nk9-9k4j#o68>b#jDMkUOd?Zbo{mdOroi9{$()N&NR@m+
zM;bFEb?-tlQ!+%4vMk9d`aw@h{<DHRC5e$@WTzz&lw3O_vG&samn~r^0D4y9mJh{q
zk`g{N&P!flK{Q8_Mb%jsB>I_<%$4MS1cP~!->$&?Mac#VxaLbHsBWe}GDP=gq2z1I
z1Q$sToJZp&Nu)DKvE(Is?UzVuC_q&zd6*8#GD)GD&Oek(R>s4d3dw^E$W%)53t^&4
zvMdmGt0ntrlT{-Lr*mbOC4b!jcCDm~YVqnM!&e}AMUp@Vw601L{lQ(6yqF5?M#(4t
zAM}>o6k}x9C698@*evO%z7~lq#oSsYuFL8C!wtz7OVN5$l9vrjZIZhq&}f(Fw_(0I
zC99`lO1dN^lmPFR#3!Kdo+LUKq+ilZsjK^vIZCJxNTyx@Hz@g+PMHl!K1_tj1Iesg
z81F;LIF<c8l5GDBWLPr$|5xpjCOYKicp~}z57-@*h)?5Z9+MpY6|LivUWy`3NJi)g
z=cGh?35|QCFVog%uXO51fN_zoqXXdkq+Z>y<Su=cPDpu3XSRUzl={sCw_p17Zy;XM
zlh@&zw{+J+a6ZzWJYf1tS+phgb4Zs^d^|up-wN}A(vZWD36lO!p_X9jE(hj0MEb`G
zSPGT?a~d#V()T}riG$MLC>t0qHTgjOko1`r=tW3XO1K><twm(ZDN1Ug5NWjZHTv*M
ztn_(Wh{Z|EXdxCa{j3UoN2HE1igqVS>q!5ow3LDs8B$vmEM-bP1EH8DePb59I4S*|
z-jt`LFHNHHwDcQ#u%4CvK#7BM(ugnN%z0_tbI{9?#x%nG1!=1h&g4pi_<+un%D;iZ
zi_)K{cqm^Q)egM^X_$iwF$<;sjj&rJt)%*jV(C*epiv@SFax5cQY8hp%cL$#;YGQ0
zLlh*dq|SZds->^f+ptDDkqqv#bo+XM)k@!|f~GoY2?yL2X%X!ruS%=vVO=jxq_|vz
z^yB~F?=@-Szf^MBDBT$Y(j>h}>8<P1-Lw>GmbNs)#TIE@F$}g!D?S9dAswVJ_f2U7
z)!np7*VEpkT^e`<<L!|0X{p#LRklIBOL{g8Cc34MCt$Zn`pO(Y-;%!f7DR4KRn&J!
zdVHAfzh3Dbiuv7@mKDO&KI!V+=)5OQx{1bqsox2Z`_hJ|VSYebd<HOsQU)c2hoqZs
z!O{b1HB}}&l-h4Y<dO6pyw#kBrBA4eZA2>Y1NT_EvJWCpq!ny{jY>OZ_$kJujyY3s
z|BXvGP(9^@G@14ZlhX6_sU>IGcV{rBy|P*g<G9JTeuKV!vR~+Dc9&IJA>tuxq?n(l
zY|Xzw+b^3R0ue7+$Ym&a%YLYUYd*4BbmjZXwgv&rPc}%$Lj7f{Oy~=ct)h*pBT#mP
zUNS*47YaZgl0|(9&<NQ^DnyQyZT|*+hh^$C=ts%g{m~dLOWK4<h>`iyPZ=v)H-Ul1
z$wKPE#miC);Y@;TF|BqIW%U#+KO)P08huH!*;FocRMzziM3QAqv|~HwkY&?CJ4N<2
z1&WW$#Q(y@6S8qCFiMs6orP$cENBAe(`7s9t5q4Y<DTftl)dx`hL$Dk{Tm*hl>J2y
z%~P_+x1fGnCf*5yXJk{BfXkLu_X6dttZ*rOIwuoRebIT@E-g@UWDX-e!Y|0)egf=V
z*=7Yq^JL3EN8?4=!W}S?FEdj5q(Ig|`-4JR8wVmqvMnL->5|NE2GB}mj~@fORA!;e
zt4wxtG3=Jhd?wLXA#+{}g-V%n6BMds;+FtcE$h^vu|{Td(0Ar8%d%-vTq}E#3jFG1
zy62#OMK<_3#?&B_zlXkSvP3_4*eHvi0~1ZM3kvjImn{tgX_ozY1OB$iRxX1Vt+F4L
zkh~#_r3>PwERix%ZL;4Vp|M>yavSO$vVXmy*D0IjL-${oOhWOOZrL>YDSBj4{{ZHe
z?EXKHxh>Pb1i$ad>fZ*}D;rpYzPqx(Eg*fenN;p~PnJWQj(*vT6brsDo2dmiAbTtX
zHz>RN3&@b{DBUp+WT~_ke<(Zn0lau5yYVTlKZj){Uqfa@w)bU>{;@3lZ5Vta%iIQo
zqq1wi!_t^6kj_hv%l@S#%!F(%)df$=KC4BavwSK|my5jcI22svpT$7LO+HLT*&g!M
z6bts0|2qR@zkJIy==sQ>-vQz)f60^n-NR2FLyI1N`Cck-43KZ6lCMB{DDC5d<nz7-
z7c3uBfP~1?D8d^m_kRy_87ANOJ`5g^yR3)gLHP^!LBi!bDRFQ}p0X7p5%SQJup23N
zp%wjM`CB8Ht|&Q^LWa@uM!Gy4G4i<-*p8K7euO!RlP@YjXT1E`sUQjRaLRBd%C#3U
zrX%v@X91cdFSdg_CReV*2vg*)6xcp4A3hG0H2DEKGny{<r59g@d?|(gGUdB-p^zmX
zpepW@@|;;{JSF#j1&*F}$fr>5_l$gd09v!<5<bw*%HLfD>~r#>5{&S?y!8WcIr6uD
z1GymYq&;n}d=2fx^5hyyMqZR}k-=`h{Iyb`6v$Wf0J~70ei+^t$;}thcS$ZdiN<32
zp&4+dM84@QTo9#l$KdBcE0e!XamaG{;yoZ0av{w{rTm5w*j4hCM_~7|d=u@%YUQ8u
z&{!vbSV8xQoHZ5dSLM}IUr{eVMW>b<<(q;rh$eaT95h~+r)Gk?EpK**7kA{ZZG-t<
z`B4f?-<3~w(Ce&Eo|cJ8xF<K#3anp#%#OzU@<+7m9+1m^fr&wR5BWVL@2N!J1NrjB
zAP?nLzA*7fUKRz(VY%xSct0YaN6**Casd;1Pvpy}Om|d%gN_uB$*ZaOXk7kHBJ`XU
zm;Ryk=N?5~6723(L>_>mi{jT1G`cFj^Z;>F2<bC*`xGn%MBEkiRM_O9$e=Krr()Lo
z;PxxLi{YA=;yfjWycMk-kn~Y3qr{M}Vl~~xehMMQqWl&2=wM}l!f+Rk1}fG+Pw|%^
zMIH|@!HRcidlRClr~wzMNTE9?Owmk7LJlZCqx{7|h1(=x!WA<pdUZ%Kn+KQ(MVU9a
zNX4rc!5vmi^M+oOVwfJ2(F!{gm@$gkw8o27#L)E=r+EB5xOhbt9t{qs1jPv5K#2-A
zz15B==2NsFNuj2l%uxla6LynvLIT*w6wOnipQ1QI>-6J_^<Tln3B_G{dZa4;qtcu-
zg)8kF(-m(}Bs@cLY!*nSqAe97S&F$|z|oV68BvftrQmJ?nB%l!K@DKeC@NOKQnsQb
z57=iFrw@XhQ;6w=$9ctf?*k@B!TB8e7Zk5iwkTJzD+&sEipU@|UR2oE05o6m&u)+c
z#kN+ELPY}YY>N~hhhl)26!p&lvsiK87mX!~RaER->QL~SfL*5Wc^w+%iub5=vO>Y9
z>8@1lqiA=H!a+HL%ZhT!<<u&~4M3|?u%<!biedphiLWYBKg3|_71i`1k_N>>PmK4P
zLQWN*jf#0xKh~rOp|d*I6%i?DY*t*PwOWh9k+&W5+^Tq)R)=khRYT}(SCmr{wL?+!
z0?;}Y|54(wOQCuJes?RTd;;#af;kr=cNE*dfO@Z@koJG~6fD|X_A4$>r02fELdC{I
zigzh{@<6fVRd5d#MiZQQr1*o*-3}}Max6vXh+^I=U>_^iJAnN};eQLhjVgj^**&Hh
zJBP+`#kx6gZ9<`pgTkcZU#iY>Ru<Do3-%~eX=AZh*-lF@7iB7)sB~5C`W8QoyE2#p
zkRHl~8PM}ow$lUITj_HjUic_IchdXMSE>9C`hLo*RA}I@yqFA)0A(1JX#^_g=fYBu
zQct^$VC7yq;~t`Xh70{r<<c^k2vaViQ1k(1-`nUrsN7T!%y8u&E#M9*4=;gF5z4iL
zfR0oq;L{~e(aLvrz(R~tWv1__#4257z)n#9OjmxQ5)VY&2g>)K1$L6M!VcGtDto7c
zOIGr0!5vd}Oou{>((yAa9alcsgE5^@j&!3hRT)n4gf!(ns)0yXuA?<XhEhjCl}u&O
zXCPV159Y$cN##-maUD*lls_cF#cbvO%FuaMnZE_&J*PZM8@PPs+)Wr-fpUzZ1cl0j
zRHs*@Y@LqAOG*z)Zxt)sYN1!6j1a?Msj_k<^vaa!RGnO|45kcLg)-?b`YM(4_JLF>
z`vf4>N){b+cGM{Ct6~1KQkM?wTIHH3kUHhZ4?*gcv*>x#pwu-3=9)4i8;y<1rzo}3
zq`XBHKG&6Vt3jHTyPt(mEy`dD&9*AvrF*PR$+!&Cu8gBqQin3(A4qm8)s!6XQr@Ir
zvfH6_rZSu!<y}gO+)`Q-!QEC?Oo8ZK<ve-;^(h;E!$9vT?@@}PUn!>;_I>3ND(x9i
zPGO;OP?;iwYePzxau|G|bRe_pG^}i(^Ft%b?UdPktUO1LvM0*xBLEv!{z*6bn9|{$
z4gGOt>p74K<(XZuJE>$)HgT^irxJ=Ts-NhY@2WaR=d#^Z-^<bGq55+wBt2C*MKI{C
z>ZR}Y`lwRqR`XSD<A4iLZTt^hpsJ?}Lkd!z%Z5*(DytLv!c>!M0ewLAn}b4shg5H*
zf{joaU!bd0wQ3&>#;eSHXe6i>bc0J&&7<PXBPtc8bdpqS)8Ow>RnT3aC9Awt@adT9
zTdLAeQ8k=H<8jq-+UTB8l~NEYRi$|YB5A63S3x9Q^%fOWWT=+kcEEh5D*7VKXQ@mS
zu{o&{u7%<$RkH=$Y1PCE7(AoOIt%mJs!enj>#Qo51BG*{P7y%Qt0rFum!smm355%)
z*`Dw>SGAT%o+^e;)m>Bt9frRJs>E1ug{qJtC={vgKTZ3;OR9Hgz^P)@3VK|YsQ#k-
zaH;D32hcB5b-asNFIRc*!6+(J_Aoe8sXFNj{VLVBZ-T2<g}({)8rAeYz`m^V{SE51
zDz*v=b*gGQ%zH((k?IT@RNBjEyrwD(hh(GbEky1ePR*(#bds$_wUxqjt*RgqM$x9~
zr&VFQYGep~9jYHoz;&uFtO3`hdd?Rx-6}c7<8P}5C`Erq6++weUe#wyFi-bX(<vm?
zuR8k&^zN(5r05$^eMPJ1LDk4>P#;nihNIE(NTs1@-LPuG0+12aYzj?{s+Q6+c1)G=
zHblo&8RKxxS^XxBX^%R8JNovjhYK+#H}y{XM$$gDaXqlz)nBxN^H57K0L4?iHUT30
z)w3wt7NA}=h`vDej}-R_QdgBgB-o)I9fJEI>IAy1L)G0=U@1&3eFyFzP;a5~)r0DV
z{SXaTe@_~R)c?GI*^5xe#DR-cFY$ykht+?sgI<*S0mYD`)xO)|OpN+Z50F^(+H-)8
zQ$LD9U%Wbqw!{f)IaN?4svTc{0ux8n;(Bx@sdxVaw4>@Zi_n>@p4bmBj;U8ta3n?j
z$22&4Tz%qcSURD8gKno(wR8$5F-?7vg7oR?FK0n7L!GNaU#7Yu7+jY6OG<s6RG)bs
z&YV*JPzUa`nsXjtXVhs9s*}i8&xnN=XVo7@!2CINFnt{Uyn1F8^mEi(DN=huolF1Z
zmaDFvfMT9{Lm^-;s`veb#(eckx~vP-addLEQ2mbvT#@?Yvk<wYzUl_9Se+XJy%P1d
z7KoIpKh8&Enfj~Elz%T*FZc?-Ooh5U5YAMp!)`;SO8r9!yr@=-s1U10-AdueI<-6H
zTdt^gP*miq`g^+5uc=r1ps`V%xEZ8LJ-Y*Lx2Ruy4=Anbynms0Lw#6`#&-3KGXd72
zmTO_QQ~gsJ)qnP=xwHwsrA}qSi`(kXF93Q+y~-aly=o77F5gvuO80i3y8caw+*6M#
z(AckbdIQsSUwxgfgaP%sx%im})qlMVy$5Pd56nMQXVCNFk^04-V0Tzu`32NR)UAtQ
z@3FcBWyKDsC+Zfe`50Ain~%;hb@*1mjH_2t4bp^K<_}AgYAFT3oHg&Kqi>I9=pGvP
zYC`F?;G${G0ddtNRKW{3%`d*_+o$nZ2{3m}9Bqp{G@iXs_td<^g){p#mhFJ{(&Xl%
z(c!J}Wy8FW=GIgYUk#J~4#iJ1BLa&4nkQQ!8lYjtpfON${6la-nuG5`GFZcX1C1dX
zWiz-?P4!AlP?%<M0JsC1X-RPApeFJeh=gmNeFq*M(yToV^AVccl!S@YJgA1FhaH-?
z>10=wW_uAtqcv^|VK+v@bwy{ark6gu5vTcts{Z0NqjkVe&@9>r>_kn*DUc(YXmTw{
zbB&%;M>StjSTR|%lwSMCG!}YZq-btSK#pseg@8Vx8KMV8s%FI~oJrF-`nq5~UGpE+
z#${;U*aoyr&DJTv&eD851u`c!pN7JjQ<~Kjh&Zh&y^2XVqq&#|OWB(1R2pzrv+xEQ
z&uLT%Xgseu{sy=l%~VRPUeI(=xHwm{h1Rrr8u2)wFKXO;fSIp(&OyuA0*#!ioeDJ`
z6n-tzBu)W$N%I56Sc)}YQ)IbBqoHtSsYbpS3T2vP+9#K5at>fH6&eR!ft4EDZAeyW
zCW3%nt@(UDMpmo&H4Ke)8twbwu4s<6fV-+$(*^Z<jo<+Vm>V>)@4?_T&6z)e-Kbei
z1;tI8ps&$)UDM|UyUm)p(HMP;X7P4#t(rMAp>RWUiAtVtYS#V=y*ABsTHUp4(q_R#
zhsMl;dZ$J~G2|{yF};3~L3M#%k7keu?v`fRU-Ul;w>2DEOyAMW{thO3HEVZ6@vi1t
zEG+eDe)$TZ_cZf1L8M<Zbt4q-YaYi#azOLyuV@_9$f&S)NVA<@xDPb1)8p=;Mm8Uo
z9%*_gSU0Tsb0+#mG>>RQ@mTZB4X8iSMB;l~4yRGgDq3NWX`Z7acjKBK1EzFB^E8#{
zOln4{T*+CxnvT`&(Hg(S&|I}Hlv8oj4)f5sPrJPn#9gahghmgo^L~JNYKwM2Z@>2Y
z58$ttwqhDYytT|wH2P>S(9P_t?OhEpho4sBi%Im?zDJ?m0Bt&5>w(&LBycfEy9FU4
zr(mta0+A4{vKV6u)&7st;bGb@Sr9p(eQOEEbWqz(+oEvoAEV$7X?-$4BDCv<p&qG~
z`~bbf+Dk?#L}_ypU?Ey7`V{tJ9NMGH;c%>W3PlOywAPQ|TfCM<nbibsB%KmS)Sl|a
zZ+JxeOg&(dv<@mfJE|?LhGeq#voGPyG3~$f>4g;S8M@exYgf^e^n_MOd!AHn?YD3y
zP5UZ^hBCEgTE}H+-=yQ6C$$dG7O<zZp5*sw?Rze8@r<_R2w<|c1v3D8R=ednaObo$
z>7xnfwO`N&FLJaeD3*0WyO~O$E^6Oj1(AGh(;!HJb}Pl)FKGwbV4_&-nGTT>?Eqc!
z<=Q(Bp<bb#x(psxYG*oVTUDd2m80{rR`CizYqhQOL7KEPC1|{^4UC6Ivo<>wXf4`3
zbljv>dwD7Ry`lBk2<)5Ml5KFbP3!U{xOVM!S`~I^vuO|BsZFNGU6;0<qQBkRDmh4x
z_Oon=+|r6Zpmo`8?ZF<9JKB2}(Alf~o2rNIYGbHOxKH~6m0;Y{Hd5BMU#q(Z^Y^uN
zbl(nW<Eb`nP`j7vWQVkK7Xsyh_K#vnKGeQ+6OE6wT~u~HtToXJcT_8-3vo>Qdk#d#
zwf;P+Kbz1l%RuX-c03&#&bt1;0J=x#k&D6X)xAU6&waXA=yl|-t62<151kv`Ri3(S
z)gb$I9`vB`(q&G8d2gM7c6>fM`&Vf6(=A^O;;$>bhsFS%EDt|#psqLpC_%c!9aR4r
ztXo9q_(F6k2Vf~wccc(9VY(v=fqg*NM-TgO-8fZC9n!Ir;9-Prly(b|x-6<RJ*@kj
zDte=JRtiMK=(f=ICRP_u(ZzUOO(I5?pliATlBk<W@3tgerW;U>>UOwcW*o`7trR^z
zrn~3`m=s+XmHnjZK3f9)G+ie}VbgW>v|i89Whl^?sS`*clBL^3x5`P~8p=YR(wRFU
zd0Ka`AKY2ppG_FyIo+x@NS@c}=_pu^E_MUR1>Lk{H0J6)rA>F9Ls#`aMsZO$M*G%$
zUFi)d7U&LcMrWaJRXcnt(tW%g8kcl7dfyl8X01kFi7uWhKuUE}zs1nXbpOyG%5~k#
z09K{DIR-DPb@j<0HM%ycYr3qPt%iE7?r92+)ajn3Am0_8W9liiUey^WHe0Woq*Boa
zoi8mCuj&5V0?|g@kEhXhT~|w|bDDLh=+bS`eQW_~)dkD|%njYeV-UHi`=S+Gn{L+*
z^tJ0wUW4}?x^NeG*r^-hz)+X&n_e__>psbXNRMusBLRxHbS>|K+}1r~Me7~iZxn~@
z)ip1I=w01NB>MVv-p_)&r@QJ6pZaz4B0&aq^Xfo`bP6F99_X(4!ThkUp9<whbRCy5
zh{w907lJ&|ZJ`?WQQbVctj2V^_|TiwjsE2TwzGcKCy?2r4@m^)qA%PG;;PS!#_YN2
zjpWQeeKcKH?)uT+z<KEBQI^<K|ELWx`}Gg4Q1H@!Oz$CY{c_5|`sn9V#Kd2pLcz%Z
z{ZKm;0`-b*AVK;ibl^Q$e>aNapCS6II>3bLZ+-@YVfx>1!O{W!l6|mrQ13<$lW@I?
zp3;Z(yY@gNLf=Al-;w(NdBEUdee@qtkJ67m#IU3FyPknUjJ}78Vq*1QQ>r0O&s+;~
zM4w7Y&?NneR_Gno|B4(c{>Mx2PQkNd`uq9NPtkW$%;LEI@I^G9&<9hpIaPl*6eLZ5
zI2j`8`m`KiXXx{90xeUobc4Yxz4Z#nN&SybAgA<M$q+fMpScu+IHRw84(i$Zb~+$=
zRxkb=7S8F1CoxZs^Lif&*yiY`(aPe2-ai<MxqAEaAbI+hG#I?7&t_rt`FhW%G0+12
zo3qhasDGUn;YIp(+Dcr~-;}`LV!b8~C?)#0SHNJYKHw<~v`lZi3{tLVu^?HYx3)mC
zQvWdpbE+KrDV{*9*8h7Jq(=WOz1lD9gXo!3tN)5}Ds_5kF31)AK6>6<)xR?r&eZF_
zD!@P+^vv_%uIX9NLA_BQ@Cmpk{SI>Uy8hcp=r!v*X))WP&!O;KtNy8GG~UpENs)(}
zdPfsQ`P%gFQ`J(t{u*V;I`mR{3Uupd(VnMAf97TM-O{fRVNAF6->@NaNB{0y=<C&g
zML*hI{e7x7?9(&8K;J$67j+nDzg|qi$@}^b^cd2B{tBIE8`Sqbfx?h}obHMT`Zxdo
zubzkXd9OfpME`CVIv?xLQ%LHGz9Il7M)fmjYdWScqoRv(_ylJr^wK4eoYeO{2S=R^
zVe~WaF{FKj3EFFTJ{2M^hF&DJoLmjdvZ3d0NL-3W4})_!6g&-&`@rot<oMD3=VjQ<
zgN(PKbUVE8G0c4m*uI9i&%yZ_E<Fbrf5UM$d<rl)s8Br6@G34{ryxVpe82=747Csm
zF-%YdFx2qTbeIS;e4&Ko0mH&d^c^%De+vrX2ES<#Ib_J44SNxWf9BKoCn62YUc<B<
zHk4AST8tr`J`NLW*tr~vafYubyby1wErv*fVW1noZ=xaaI@~^D_?uSWNrpzc|Bf2s
z=0POc@J~9_j~Ra9qA|rVkG3br4N)9Oo-h<rlpxLUs~udr;ahAi9ZngBE?V7X8j=;j
z&N9@~1fMk6oFRJ3&{zj@+VFt|pl1ws$6zAc5SEJ(o;CRW3@*p8;|?6XU|3p?#$3ZU
zF5vPFVH}VG!`l?fDm2WdRY#FwO9w1mGOS+$uGny!)<upI!~a4-OATr+W~j_?tq7LN
z4P%tasxTa<SVyJdjrl;UG6d2^UTye*u8SJO%mgT0HpF<q-&%v}Cz!7@<b4V3D~2aC
z(RbBQ_d5FO4bm8ZH5fi>1Ijf+`CRlh8kR4_1T{Gf>*)O7b;JFQ7)-Na^ITxJ7#e8>
z*J_Y`3x{tQdTG9H8fL|!ugwrbp`ms|1TCLC48Pt)U#DTkUXU(B-rq3aV{rKcdbbQp
z3O(F5=oUloj^Sl`nf4lPC?ImzaJ3hWeFjHQ30m(NMqh$A{f3LQIlOQ1dl`xYhHZ4D
zWYF+=0YrujTX%pwFldN8G*oKg#Uq2?b_{0N5PBS-BZjwz!96ytqkZQSgMrGUMh(UH
zVQI{;S&7DR!}o!hrwK!71)wJlaSkRtbvD*`qjit*DawQIHLB<raWO_3A>(R1L92c@
zBj*no+-KZ;8GY`?e}4h-Fh0xxsHbr_0^EM%8!uwkyo}$`YSP=dl@_Hw#uh&iU*q&_
zi1-;J=z8)u#!#Lnz-Yco@s~j3T#EMw8LNMQOtA6Y1b~JZv%N9UP~)Dz(HLf2nhK2r
z#@ISwA2c2chBM*DJrp%QWVD6D(Fo%SdK*R>LnwlG*m&<N=tUXR+#nfkl+fcU#`yXk
z%x|nwO-CH!j2jrV{){(XwL&z(*fIi=X#BbZqDPDk^zckFe)By*j~eBaaZfhZv_bKh
zQCW+|6k`y*DUTb~p9A!SakCC2)tF2NqtlFSuINiQj)mbD$uN%4r#dr@TSfq#W&G_X
zhI`tWf_J&Y>5TDvsyNFwrn{i?tg-DlG|m|tx}kC2IFEvpImV;`4D^C=?HV-Z8k1;W
zlV^;fxWGkY?>}%R-x&J|xB}xVwA3s#s%bG>WLy{n$xFs3hoD|;%%;yWlo%^r!Ic^}
zQmVjFW?aw#(Q+gILpW7|nFXmdMpFQ@$~f(Jpj8`xn?z%c(c@K+%f|GdL28XB3Sh9#
zSiJ`(t{9im;q<G<L@Iu$H!`WZtHEe2hQVvbY02noG`iD$+hp7yi8;J(eC7cfn;pi%
z0I)4aBSlVHjTzTKZW!xCaPg+Gwj6zJ#ut8rr|rgYANbT^eEDa9b{f-ng6lGxlOWP<
zw9v+&#~8m4eYcDYr~>)6@lhm1?ijsNA<}Ccp^wquHHKw^>oc+gVCbIFkxPHy(ho~;
z_`Xq2Yk~n|b1lpd8sC|XpK{2!`WUze#w)jh_RuJ!LluvV1)YEyHonAy!iceBE<_$1
zFH;HA6XOLsa4~Ak?u5daF@?gm<Hi@3!@`8I&>fPK#>pBu<7~1y;^4*})3ZMTZLjI(
zU+8o(g;U(t)f7z2Sa(wamAHAB>gcKIX^K+8-~FZrS9sxNI!Rw!_BOpW4~>2%Un;ip
zH~mOY%K+0T)h-2_O23CsA*PX~zzj8sYtR^GGN?fgm@-aN!ttQ#A}!*>O{eB#Fo#UD
z=`dA<sqrO{NYkxBh#ofm_7_B=Ozl(z8*BQD68>?fEEkBxn^aWlnP7^F2A60WqdJEp
zrfWY!B-wPG7QDwy?Dv3@V&Z&?zEso3E;Oc@HgrzG{g-aKYXWwb>EbQupESL*7-*+V
zKOcq6Y11}ZZ=W$eL-F2h)BE=!a@I8HgT`|v|1_YTH_dz#eL1Fo==9YE(*z}?a!oyy
zbjml?$ziv^G_wekS7`c`k{QLO+rNU8nDXkU;QlK$ZJ^L_x#<e+tSd}gTwu4-G|>Y6
zDifQ&?^<oLeTBvv(`9<>TsF1;4X)Po5$zP~On>V!YgbI~aM5_x^d*IF8cgdq<F~tJ
z`ujtOG@82U-PUA+0bKc}0~9uDHgya^&(UJKw-Ritsiy`qH%uujFv6RrfTz*eVVeCl
z%y*i`N->vRrn52du-o)CU4cEOIiuiinfinfxnp`lD~n!J;R&eUHO-{8OP}clT4&rd
z#VgU+Z{qsFwfm;GJTN5#rhODC9dwv{>AD&+^<05B4@}Eqz&$kmZidVwQzJ!+hD{Ok
zz>S#BWC87o$pzbHr%@B1j%kjWX3^7f+~iNk%qC3l&W3A~rhPv_!P#8+4t&~UHrmj*
z*KGJ3>Mmw$2#Bk>k8V*nvx7rL0sG8B^fq=kAEV8Khxs-7dXAU5{1VK2o89REkdHa^
zCSd%{ar90OFgG5A-9YoZv?C8P`%<M%usL!u1{z}CX#jV?JT?iGgXYt%7-+aTjUpF^
z%xME~EyCP>1nQCIC<oQV9yUk)3ymoAVoHicn|+gDH^%I@7?xtq$Irs2IP(kZK;q4N
z$3YUz2Wa1zXny5spdB$kp?b<B^Jfw8@TfU(HAa|XK1-SJ<K|zF!Tbrc$O4jTPNKt}
zY39dNO`UGO+2a7sGW+g@#!2&y^ME;J-b@vv*=9Sv2G5%7y5Y<@GwT%?JZ}!6Vz?Z0
z8w>tkFn7``C)d1uIn?vaHz@6L(fr3Tc#&`ZEfjqP=HL9l6`G@8gnE&A55;>fnXBnx
zTWnt2P5ZwRbKxAAC^bI`g?^bihmA3nn?HMi#tQSsUw~a{E>Zxk$~?IlXw~M}_kdPo
z-q{Js%jSP+KU8bZr|+oLnG^p)U%fe)*5VE3Px~;IYi3`H%Qc!0S<u*I=6gc&x_PeO
z4BUUs<{KYDqs6SDcvGu+8a)hdm<Q?4U~Zbz%hA|o_B5lh-E3}vVu$%9$^>_sed*{;
zm-$b6m~@*>8z9+Z4!sQSmN}~g+--A5IR<gZeEE3{yVv~MT@3rK8LtuC9A-lxILAHn
z%UKZZHxJQ;c;7ruPsTyB{b_U#nRBT)<$>9G3t%3a=VgLCGXGQnXNJvFsM2P{T($-Z
zkInzkJvM6Am_WwNbN+$)xOr$A6ei5ODc>?_Zh0DpoGo|Op>dDp*|(wR;;>wzhl#7@
z#CdeOSzdL87yB%;{XyI<0hIOGZ+RR9&dcIqfuy%3m6m)ymILts^|h3;F$sQ_$p<j#
zZ`pqfeF2uG-=i<k@;yb#gDm9~&<?hI{4OknSQsh547I#OACwHUI5<?Tf55VsY7Y-u
z8eWBBxF!BFIuBVIK88kw<%=?S8fiJb2EWK*%U>r!qAaIE;8V24um?WHSYG7;G}fYi
z7wU1AOB8X5w_Mo*lmrW(PP-&py0U<B#4?>i_DPnGF^C+syy>9R1<968XW-&-i#sK6
zPgvyt0Xx-FFcn;y<<kgo>6VFCAd+EOLd(gMmigUut61`A?Q+^8$U@&4%RvjwXIq3+
zCV1BJHl43NXK|;M+j-021~leaI9CC7!P4|ENUmj`kaod&mik1vm~UZHJfpzkN@3qZ
z%afDvw8*lKswOU3#*nObDz^B=fs|N6m%)6gh4U0hxuuN?^eQadPC>HL^4!~Ktg^Jy
zmq@BDPPAgIvAEJ$E?d6NL1V4u!kZAOv;5mc|6_8+;_(~UtCpF57)8CMn!ZcaU=dIr
z;hM$22ou$4X{VS_ljXZ<(7$e3PgPdUmdqT0wpb?r2ZdJ4mAfD}EcK5u-kTOr3KzFo
z{-i>=cFP(WT<frWb^_|%mVNXf@392n2)4uNmgNIFTYtw=wi^1qmY!+oyla_I!F-=(
zFYOxcS-j|1>$i;m1cUc2^DhH?z~X!qpo5l{&ml5ok<v-Q2Nst<p#ISEo-@cJ%Vw&c
z8?h{T0ENevOgd=z#By#LBu6bRw7hYQSx$TgnF&iq4bUbnD*BzAty^dnyvMqS0oV3g
zj~#%ht99xP=(|}{qad=+T0?I<cdMM%J|5Ob9B`giofjncTi>KLv6t0@E)Q?(Pjs#N
zSm)8E-`8rUN0OiQ?KL3&4(nH6qBFpHpLTA6*4rB(6J&Lz7<RDr7dFNlViizaFVq@W
z0H4CGxeXwPtS&wv5!SoDa68i4;|7t#R@)Y+M_Fqr;~s6T-3ZJW>w0>w##(<A!(g1X
z>>`GgV2z_#RHD`K>`sUtvHq6_FOsaD-$3-Jbxj7QJK36?h`wXiQxzCtigjQS(2iT3
z=qYl-Iv4}<Y1T~?b4a(o`T|5Utc9;(o-?hgk06<4{pmA+owR;?7$T>v&1&?Ww%Ss`
zow4$$W-8md(y<JRXRS^<;aiTi_%p~{u&%oVl572r>Q?it3+RHnX!Q<-V!ril+CLUp
z?^vK;XkASY^djr>%}}^x-T5=@7F(aELxCk$(^_z))|qlZms$V!3lz$&9aIxnVI403
zW~DW_iQa!zR@Y&4R$G6k6+(@5K5eNlTkC0;Q)``71^qf}nhcUxtd6a~zG_|U3{r1h
zNk=3atlv@H_cbfyABZ$sU+D)}ll9y8;plbidlc7hwqBqD^%iR{)jHm^&fSf^Hmm1<
z^!=B1YdCGtJFLgsG3%Yy4foO6WgXv+@pfB}{Ed0;v3|V~25(v2PC);*^}hv>ykm`^
zMR>3EDy@C)TIYTW(r1<b|C-BMbRBm4t>$i^+_$ct12SOcjsa}YT0|MyA*&IQKZnx;
z>)VH*_|W=k3qT)Pi=KtduyrX7X2j}FJI2S>r@1iy#Hyi~`>1t4l?IGizb=Bvxb+5A
zp-xzziALk3wQn56+4l1bK-ps}nGc1%HrX<uxY*);MWd^&fu_sNRzRtJ$3B~dBCVb_
zE2Z=H+x}SyFT8AdOf-7i&QX1nk8OKCM15`ZhcS9TThkB*<8RxU2`<3)9#vZe+I)S%
z1=&`Pz(lYuv;vJGwthND6KV^j*Ke5Z!?!S92W(5fL*qeP<1UbJhfVelEFH431(@{+
z+k0w|NZVD~i5#|7<%5f|DX989+O~2juw!h;DHauL`|cdLINM?msK?vb`Iw6YTirBp
ziMCOSgB-D~rm~JCTPi)XkJ>z~Ksj!USA#oYTk{`KQf-d+Xk(IQ<4`&w-IlQmb~9{m
z{eJ<At&$ctS+-B_0{f&b=_<I>wrC4XoUz%jLoeGlwhboE+NRJQch0t!HihSHo9RiK
zW9xq#1~1rtCWE=Q1qVR#Y-tpmxoBg50rh-asN-+Q6xjArK)uj5@(ntRZR&C~me?k@
z!I@Iq-0xtw!e(!R7nQa=TB%mqOmuZ$ws~HJrCM9%5-8N!zWfg;^|qB1>}#-n{tg<i
z+1{m+tw!618jvQNTNN;`+luZ$<c95s4;(Of)Ar{dKx?zTlL^vpn?<qJ4%;yOBAqr3
zE&jV~-!6e-x6PA^TY7BE{sg&Y`}}$MblcXF3hX;JKgvn=+H7Yrvv+MD(uW88Y|E*L
z=br5uI}G*P)_nrZ`?fYZ7&c(rwSnG$gEm)MPz~9lm%!2k+qv(7_RzM9Hp-7|VhaBZ
z+wRdOdc;;d3*@nF+Zf0b+wfuh%%iq1-vc*hE2MjD+!mjQ#tGZdH$a)Ro!bP?+1^h%
zf<5*W3K{OTH&8yz#r^;lwfO$0ePJ~8-R=HCFz8{A`4x(u_Im=1V!vHUSr9M#_y_RN
z+rH{CCfLW`L(5-ZyI&6){p>Fe0L|adqo{L$J$Ebg0_|ht;DYP{^imAAFLDEBh<%h+
z9ijGJJD?tBUlE4i$8o?O|2sMl+J#rq8gBpK5Ij9(UugsvVShpa^+<cyNtifnzrFz^
z%0AT@cBAdp%@B#PSLFgG*1kL&C~@{VTS4OOg1fMkU>CT+nMAv(5`#EmKlm!tlkF}H
z^c}OGm;;m)hyBJRI*;2w{S)j7`v_g@srIiaE0=CxrGxnl`|5>&$+TydV=!6v?ih%i
zw6C}byJzgzr-EeL{l0}WXYIv}P&jAzpAGK3{d)#5bL=L{=v=Vxq1<n-T{i&eJiFI!
zG#1(&a}I(nvcE|2?MrrX0nm!=uhP=I#NJm0jZ%A-8_>$^VyYV`x69vvGZpr+6pW(M
zuBSSOYJ2fFAT{<(3hG?8x6-+#TKfk_&{$`$pga7k{i~^Hthblf!utmM5i`K9*@qo;
zDKy&cu3($&yKiCguiJ}d5N)yhZ-IWR{VCcw-mq7^1n#DN4&7C4cGGHDYPTyXmD^!Y
zt%grs_6=0m*lqt~3P_K=tQC#7>^!=3ZrgpQg1ci6rD~&I`{(Ci@3CDtjq0z*?VlZm
z%%pv3Jk0Oi`QK~6cH2482Mv#%vzgHF+PRjV-M%|JsIo75r}H&T$+4Xwl`x;S^LGkR
zW$mn`FwB{qUF*?!Zs*TZ4D`azI{Luk#hrn)#Vgt=wxY3oXP7HcuJ24`(f;rD&cgo>
zFz;OO20BM~X63^tmtA$VCw1SIeiWYi?fS0>1`qD4rkG#MuBu5i9^Ew>4K96`$5SwW
zZdd;p>=y1yq)2wjt^*&zM9r?wdEl<@+M|Go-|mtZVd2p3Ey0+exZTIsQT=E7?&)+C
z?bPmfZerLMcE>Q_aLMk#QkbaO?Mpj~rrpZj5b4~_p+b;byN$2HwSnFHv@kKUd)X@J
zjqR?T0cZC9A5Gr@7S;8{>%Dh(VVAP7d+*&{nwqAuCYBUUqQ=A$jY<5+5_>l>Cedg#
z#OTr#qzVW~N2vnRJJRe_K@?B{DFPy3!3v1J-{igbefcuXIWxbRbM}^VX69UNeW@hf
z)%GRbaUQmH^d$AMl~T#FpX~uEs|vQg?gaHHTW{Kj>Emo0rLdG}+tvorWLsZSOtald
z3zJOSD0<#x*`{?sBinW-9jM8%eG&)70$axvaD}#Bci~g9ZPQ+uFR|U`h`w{S*Be33
z+dkijfnKnkL0P7YwrWd|OSV&}Fye}>6YbGT^|s^h!EU+j6k2Cg*p8Ts)=Jyn-{4b~
zZH)pZuG;>OZulD8<BK42&GxTR=&QBOp*YHQ+t1g-!#Z1sK}goy7RE!e!S?<$h}^VQ
zP)xSXc8DIq9kv60GHBqx^Gq16@oO1_Fp7WQU?RfdQ9ZMGIq+{X1_yz7n@OWxMH7?C
zV+ePc-&EjQndRod?_e$pXnerjrYfHoOc}is?AQelL5{M;dx7G^{uasoUu!z^tw4Wo
zo&@Z;*Ew)=?yxQX{;_K;+V#ukKLuGn(*Z_T{N;?fScyv05z?Oy&=;~-`O!LabKnmA
zz5QM%dUyS##Mt&XP(`l3+5#<(%v6e!xickH!spL)B%v{YiLr#-31&|m8UvYKv``IV
zew~8GV5W~AfuYPN2Pys-#$;1iJ)Aic3DF3~mP-ClGH+-qPciRw!%!si2c@;57&%>J
z(TsE>1`xy4+F>-Y%mWG&$1xp?F$4szJ_L3=^XnWaBrs2C@14l_bOQPe^DZUhlbC(^
zP)}yQK=wi}O=0HEhQU;3SrH7TF)l};pU$jQKqG^xrFeKI<J<<jS<H8oV991Y&Y>}f
z>GlL#F7xeIP|sr&=V3mdc@qWov&^^wkOJmN86*oC1-)vD7-k44#mrZ+Kq+DBPeVk1
zj&W{B=XqxC88}tLbdud`j39#4GW%^YU)Py@D%QBc=nA1x$Bf$t(3{LYS|Z+JMqh&$
zx0!gloEw?k@gS{?1C`LWGd>hF?qE_V#ofi!or3y3hMfw3dl?lKt@r7f&H-RQWUi3n
zBWC0PS|2m^+tJw1{P_~(3FAzOou`Zu74$x1mhS-CbLM}+Xneuc_Ce$&vu-4u8Dy#-
z;inj44n4&{Uomb}GyjI!LqD%QTR<yY2X-;#H{IB<A*u<W-(Tb@llS%y$>85n{Q=Z>
zhf{&}o+)jE#*CuS)2B-*m@wn*3Fw{q%~Sw=)<^l>&+X~(@fQy%?LNzS0R}yL)EuDA
zS@!}6UnbKPJNNx==zevS3Z}m{rb(OEtAg%)v!7`Fzu-wdgcj~oqWhcax1hXeV+sCV
z9OZ#|`Zlv0ElX01@%ML{8EF6Bbrc5o!-~%^jHTaP#sB|Tm<^d9KaYWP%XYm5hn9!@
z2+S2hmgrqs)ra<<d<KEAO8GVZUj5NY$gf%23AglXjpzlwZom(q>j#|Cw80_=W;RvO
zHM4m%op{;OXby#~yeE3Mt);@Z?Lo98`1xNK82Hye5&u8Td`Q3f5hjERKb#o{dStpV
zR#b0&l<CceU03Ejt+d>jf_DMo&cyW7`5O;rdlY26nSK6HY++{Sz>|l}qlIXE#JJJ>
zeUJ&ovkSlL544du%rX-}j<DAE$r5{qz7y)g?%M$qN7=o<!&O)IHC+L2?0t$SyR%Cy
z;EV^`R*A_EVf$&59m=*-f<Yh4j-(f59BcYMES+Y@(kdmMeX<B>39JJh%1LAoQ6TLM
zYY+?UBsPd5S;_1;H;AOLGg^S1$_CLAJdIVp3oe~q-vqlEtoS~-EVh|KqS<WuE{No?
zN)5m=xwk2jo2BQ%sNgG`3)}_J9B%DnIFrjgr>9OH_vL<w=5y(^$v?||N?FGO?tLns
zF68=>V4{et-UFCo&WWn@O1M)D^v-b#3!t3mE-!(?1<vtvkc*tH3&wJZyZ1gsE_1)c
z0Qw4NIC~e^QjQNu^~S#jyIcd9O78h}n5g2)Xw!R@bEVX6H8=SOXw-0*mH_)2S2_wq
ztK|+;Nai}{69DWR+_$B$RL2d`Uca96qhpl~+#e))lbc0F1Gl(sGof&sYp{o8BX^k|
zQ%zj-0$6C~di50Sy2Cy625I3g9)+b=ZWCR0ZQLR{o7&FZk%HXi-0A?+!5yZMPA6Ac
z1Fnl}F@(W;oDm)A>*h+Q0Q5fhnLE^bIP;Cb?BzCZKwlp>=_}|x;HLIM;UQPL2jmea
z`&SRq$K3nxViNkfI35l^;ja9K#;4pJdMrQVK6?bk=Uf)W_+D_ek+A!c`y~k21Kc>u
z{0?%h`Dh&C{^fyUCrMt7skE0gRzfdDvYE~orb<5j3z%t=z%X#>lG9V5kRkb`jZWia
zN>mMi$&$=@fYxluy?EHokzAtt^QvU>37}O=8f&0fBk8#a$!n56iqAGmW(ycvlLW=S
zm>J1yACOMT4l^ipORmr{)ccZ{(a>|2&ZSyG7wK!N4LK?uEr+A-(m7aX;%=0F<BnEO
zgiJ6dFR5l4JPnt=Lwl55>BBi7dD72rgXBxo>4rTkeS87>1=2y<hZIU}m%>Dm)RL~w
zV(GkM*e#K+B!ACK9mc}L3)1iG(0Ebm9uGs8q^XObepwn&hd%uk>E1rrEyX{b0J~+<
zoue`OW?4K9`;Kfnt@2xBI|D&lWvAYUew(a>mP75bel^Hlnc@x<I%M4w>DQ7C^~1yG
zGE+S0rEg><^ywTs18oM>?G1{r!3zh2ddjuB8D!9q-1P<@c%aq8;Nlo~<7w~_{p)4N
z48EiUg}1>-+SB<M+$;un++a;3VEhbT&<fGtpo5~90S4bjfeSWRvlAr5z~VL<Lk*@J
z1c@}Tq-br1frcU#nFc@o29jm)bq{7H+knZW`8Ck{Q8{tGfn*js&l>2cCc41Dat{11
zH27x)%oiElumX44ppJG2R}9Y5?NDlP+zAS02L3bASZ*-B3n-NaoAyGz%HW5uG5UIg
z4i(&PFqlmnt(yjKUxrV&3@%bIztLdZ9H=)LMCoa#)@&eI3z$0w^Ns<#)u5{fzO@-F
zN<!mZgPKnO(_!#EJyW_2`s1N+&%oglMD81OT?6Sg*s>6keFi)&g&!Ei@bJRHuw@;*
zKVj(D54}Lc^H<RrWLV}2^TCE%O4fuJPTxhlp-{tjg8>s}xcPH*h8vc)Lo~wBW<O*i
z4Kr>4JIe4astbxXe4DaEF^1FVOi-Mm!yj<wv|;*NK#4c(?*NxzSpN+q6Aj}Q043A#
z$P{>yW%%tkfX*>om;+~W4eu2KGtY3g3*CSDhMA?%C@^fGS8k!<$EVR*WcdCzfEF9h
z&|#uV49jQ%d)}~$lEW7avuXKx(Qx4|pj|RNP6Y*53_l$Kg;GQQ0Z_^eH-3V?3d3zw
z=v-+y6GvR7RffW5aNUMW=$O=f!;*8f8t64VOdH}pLr+R+JTM%(0`kz%j9zY!4If{G
zV!vU3DHNX?7SdkfnPCpaG+!IOPj96+hCfoK+fIImgQUHDLjjy|kPjvT#Zmsg2~eEm
z_o$Hlu>5y==pK<<(>>xWzx6Hj^e*xY8;tOn{2ZO{@Rk?!0^3(EZ-nA;xyv#TfBDvf
zPz;d2_azjQ<qfovPmw#&J1$K=T7$lH`Dv=8%a9**1eYoArC3>({QLy?n=NPP7s-)Z
z*I{OI<@1UmnJ53~0o3#La%+0upOrV|ffUGpdj$6j<xaHcE|T}`gnqI7>JT(a<mR-`
zJSQJ>mVOHPeu`~ekdLJN=0*AXDZsuY-$BR8F3X)MdvHZwOws95xnw;g%j75MdMuX@
zEdr^Kmr~hEm0UmZI%KZO{~p4ytK~DJ;c1Qh6FRAIP5y?$+O_f^Cp2D{Ul1U9Lq1HG
zK%IPN8%TqkUkb^aa_cWJCAZ`!slw&9Jh%m<QGT6LdQEaSE0}MVAE7gZcjV!e?P!sQ
zr$Vn)zEDp)(>D1TT6MR}v*{enU3tVJkPi9PRv7G*J2%5pm;5O$`R>VQ&=ROyzGn$c
zcq{h4f@?mC&*^g&L5l7R01Z~8KEu#L6y8+n5vquP4ic`Y{{&zWii4-2eo9fc79>)!
zQ9+yDC`E@9o<=JI_oFpd(fk!);uJ~rIfc`To-H8pil~hMO;l_$LSK?%^>&~oD{Se+
zcb+1T>fG`b<zwJef#S!Jz${eM(I)VcLbwjhs|q<SovIZkB~Y(XB>oq~RAejYG<dCI
zj};WJEBq3Hc0&=IhAF92^jyNQ>lJR1u-l;6UjUdk#q<V{c7-`D`R*!OXMyWb9Qg$X
zI~B|6_1mTJposfDMNKW-?pBO&1ayz0@;jLCRs6*Rx=(SQ!krHkpZZcY<U_@H3Wq;Z
z6d!}Z#|k~2vFTS_`V25n6jP|Q?5U!_6WGrbq4Z9Fq1a5>_m_%uRE;&DxbhCTLB%xM
zq75lNTMP0^@gv3Wh7}KwfP1ZYi@sj=MllY{f2p0(umY~x8}+>pqIWRbPa6$KBe%_9
zos2Hf*If@AWt_xB9WhF#HJh{19}#fh)u@|(SU00Fw0dwis-rl7r%}^i;Jl3DOySxw
zqceeM^fn5N1B#E4$zwqK8cqKO+;O9i4?#WD$esdWVMd0Og9z6f{Tc!qVN|mZou`am
zwt$N?IzqpFlu_t+;98BMn&JKnqdzAB&CYnrdPv$EFARr42V=Jc^4@r1D@2@(SCqif
z!^T$^Lhq=tmf{1h#>c1*-_1CCH89<cd+j0VY5dX{C|<_;-#@@Wy^X7k0pnx5D*!V7
z#_cKi)dGxXPD9@b<ItbsexPwXMO}l9*RKS2h;d#QutSY~DXtu5octjaB8*qjBJHH{
zND1^#8P|RR%t&L`XD}aa+&3MKF~(zTArfo6;1htw89&lb08KNFr>AwgF@GNBGmNe2
z5s_(JN}-D^V{Z)<vyCIag=CKLqdt&4<DcnH&o_>x^mU=}9Xf_nZ0t-sm=fdE9k5$t
zY~F);zGghx6q2>Zi|O3zb>r^y;BFYl?FLGn@xhPi{a0`7Lyw&nW6vAlT8+!P(Aj2u
z=r4%28(YvRgbw4!>oCx6<0*9@_l*l0AlYO5!5NtEHFoxf$U|c{T2eeR)>0YqW8=M}
zF~R-DkKV#qo*TbM0nQi3(`Ar+X{>n%C<DexS7<jpXuR<ZEDafNGlmzhjL-DK{IKyd
zx@9~}d@0N7X%gE5eJ_)NL6Bo6qh_Je+a$FK#K&Z3KJ<J|rqEvNxJf776@Dgj)R+W+
zlUMHnEWo6y2zn<>I$OX6n!KPrOOQ!s3f+IfCi=w?4KZnJgnpPw1_e&SO}gKpF~Vdb
zJ#9~#d|?O=Pnmo}NyJE#)A<--lu2|gNQ{Xy9Yc*Z8AJC-oXLoT7~yFXGc6huOs;%~
zfhL;V{|b#~On#!!Op?ja=OD=@@0FlYpJEb3h3Tm#gH%zTX43T$6w^(P(AS$XObYKp
zKg*;g3dF^9Vll{3(}O=k($zHVZTRG4s^15@L8i)S7*nvR9o4mlm@e^vqoJl*w44h!
zoook3BTN@iw(+FtoJv?YW$I34Cy{#7l5m)hGTmnka>n##HJr*c9lsYO%e3qyV6shr
zqVJaFn0`pvrE=3v6nL*N&H4f`m8N=%9NaLSO7F%x)0^}?o_bSjisUtz-le72P18m-
zL~fZ*I|=T#X{R4NY&5-e5137+`kS<2Z8mLt2L|t$Hh&5)T1>rvgJ`R%NVC^w+Pog*
zuIWzNVs@BzQ!z@XX;3y`x=j0q(0I>ubpRClO*d0o=!vPM0ew$RGw8(WGt<yPC_Fa}
zTLkWfsq!`YUYZ`K+i<`%Ku;0ULDLyj%{*j!c`{mGnKBe)7&hHPo3q!Z^XQthQ?7r7
zK6|BXD~N;gl_fwOl@atlaZ>is`}(lbdn&v*qD=f1oU?NIuaI<6>ZoG>s4|t_L#|5w
z8Z^2o7t+V7+?DFf6sPr2PQQZ@dMbM;HRq+g7=*@S%1tz--pa3^qR&UUJsgd`O4C?O
zo1gNV|JFrHmtP?gpgc}>h$ocq(c3UkxtFq1LCS@+y$M!YzW^7aR2#uysB$VDvj|h>
zQUW(Z8Cy=#_>)Sv6_7cl{K^I6jZ_v~KxdTFbsj{cm4i>=cZ~8xCG=yJucBe%wDLZE
zxiwz7O@K&(^1|1cyhP<q%HEw({v899BxUb^Z)l}2?JH80Ga`VQsvPuzNSd;VHn{1^
zDcDZwr5Vaw%@|Xb^5+K-%~obo{3b_v-4>v^%CWsr%u{|a7UuJnt2ROZtg?rmwgt+{
z5;${7d9fd8mz8-xLg9*XAAM7$RJnu7N3JQSxIv^=8AgSc*Ok-g(9{j3Unaonlz~)7
zp|4lAQsHrf(%}KdbW`~-6B@Uadng`vTj|3Ctx-9jwwO)IGTJ6ID}Azoc1OAF5YSqb
zFa4p=s&t}ay>_K+CmQc6TPR!Ep<FeLzD}i;BNV!ne#Q{Fr`%01mu{ttCnWFdm1F6^
zd5>}#T_(Ls)fdp{Q*NM7=|505*`V>E@(+7xJW}T0gfmZ+x#NNMROwKPzGuqQ^h|iJ
zEGz?gp-gdt$V=rpS}_hNdmJ#(LFI0Wg4&yjwrF%P`;{WAj%GhnDA&nMUqO|NN6Ze<
z;=|c&+AVM{W@faKI%<}%4Kl7~bL`OPX11MP?e1nv-$tW{*-}badz!hX!mgLum;<nM
z%&d>XeBNfy7Qs@SxrZEsh&L~k0yEM4Ko0bh%z1n#N}6IGwGS53%xCL!p^;%eo$BPW
z%%@I<r9AUWDkZ2hkIjUBoB4P;V9{>==oGlS=IyJ&b(lB*0R2w$C3Ik}%X~MzT^^g;
z(9XKw{Kz;+J~#iI(q}KtW2hiuz}%MZ+d=a-s!AL(-*y{byfU9Hr)sQWb6pZzUz^{h
zqPsWdpCtj!PW3lk&-SXAH8AL)Dx;zwN0od56x>xBZ(w_<j(-f8VAa70G=`{JeK71W
z)u;58xNucRD?}nx>}TLks?NU)$w<|^AJHVJURFUNS#>v(PJ`#FjwQo<p6VAmVwbOa
zdlF<Wssd_Z_mb*~FJ0ZLHEqzpqPjv^no?EsM<8XYy>za!Tve6^y$V$b{RWk)-J4;z
zO0{D-$W@iuV>DK)T4}*sqw=5-?roKdj#4zL7{q4u(k9iEU9i-wYNL<W+)??ugKJR*
z*1(Ha)%U-Ew5dv7V-)SG6a7%Ut2!|Nu0z$*0j^VJcmy7Hsmyq&-%}kPfyQptH?Lsn
zzG_V!)O%E4%m>%2dTTO7`c#WQf%*fLKb7$4AF6x|(fUaB!W)W@Rr$*>rhZl0O^oS@
zY91w!o~nLW447xC#ot5Yx#|}>*7-u!bQK~mRew~VZ$M>t1A2q1%M@}PQg!9R#48m~
zS>a(-_yL%=Q*Wh6yS=*b1*XJ7{gO&c9QEqGqao^~E~ti#pITlDY=8B-`M^G*{^LWS
z1*!{ILor1Cn#xx~)f?%B8Kyq<KlmH2_OONb5$gY41$R;%L}fmw)Eg)z5~*IQhC-Bj
zfj_ut_3&JbB}P5<EvUz;i>X8_POb0mM(b&HHC1)QtJRI*64aqoQj@6up3<^s)K4gy
zlcav+3=_#}Arq1*>Io8Hr>Y;afJsyDrZi2u+U^f<8EP|opk%72&&3F{)N^Rto2@p`
z0wqW7m;uRLwbNT@%u{dFr-IE_e?1NCS+x;W>lLWS&w_rTx^o{iiqwNQ0a~nXptFP}
z>Pr@|dk$m5D9)>Ow640KUO@%V7u9hT{<)+cN0OJ-O1cfNs1M(ONU7R_;xA?D52$Li
zT<zimu0pLILA&Ql^$)k8QKgnr?)0kKmkzR2t5?y>twz1r2%^{2Z686TR&7cr<FBj#
zxDE3+)Q8D#ox0T+jrHm=5{NXYKcRY+o9dd~Ah*;@QZbg>>Rwt2HL6FB0@tK|hfWVQ
ztFI(cHu8>oBPFt0)YB<a+p1o!foPlBnod-;t50@9^sf2@<^4L;Q|Xg3oofGCFxaJz
zrXAEh^^Hn2cB}KcVDP^BcshpEqxPjBQm@)I7LN9*^^4K?Ks~h_Lwcwla~-q&NF6(c
z?!U)sFZvDo)you^*(d659^6xP&}^7^rcR<|`*U^0?{MaYdK_7LscyRrO9SfLM?nVF
zFX&Y_q@J|_lCRY1OQAljzIPUquhn7k81EbPq%f%4@g`G2?D<<aA>zPCQQ@NAk<X%a
zvlD-Yj<X%+Kc)jTNBC(6!8!BOs5;4o@2Z8yQGW3i_~gnz+KWCn{#`m_<IaD76P7&q
zJCC5}$<L*-1}}c69(~97-)mvso4*hX5g&g1Z}8BUe`)}KkMpf`MAc8vAD~06{`@?u
zJPhFfp;+Y!zJ<Oi5y(3_W4?m;gRamI=2uceDTKHD0hU7fjx*2;;}0B%NH}js-+zwa
zGp=GRCwY+$f}P@j{u9nb@<&B@AI0wvhDbE;K^fl|e&tf=#q#=0s@sg?U(x5<PV-T;
z+=%CYp}krHUmXjQ$otZLe}?Z6;6)PO_#Qx$dD|y2k-|4qkUy0leIJr(yoOfK>HLnF
z7-0sVZU=*z{5T4OX7N_$5Xt6E1EG+^e@kGw{470HDdq8FX}_G$tAk<wEbp-&TmkPs
z0~&?=p|#+O_#ukj74s=;pisgWZi3`F{=tWsr}KRL23Wel%LifiBLCrYaF_UjgHX84
z`%!)O6+S}?Qp$%@$gqq*{}o6%zc*Bmxvby?I@VIj-=WNP6@T#%hIW<zI38%#yl))1
z8h$<9_t*IFB>=7E>)(NE*ZE(c!Tb&W69%M?-@O~8o{zr>um=7dJ%n!Zc}1{vi@z}m
zeYg2tuYuCYufGpNP5k`~s)lUlovGyM4lgYOY2h;^&}ik`zXsRFGgKtl&Y$&#{#||r
zg&sP1o~p4r`E3;V?BWle0O&p5JRg1C{Kpfacc1@?(s4b!{1(7^`A4(|@8jp(hu#A|
z?IuS3kPkwrUoU;cPo*>Xk9oJ{7+ODXO##d&{3B9)%G;a<%roAp3FJBdIi<c{@VCsM
z@RHv`WvT=G9J;Os`7QKJ7~(rWgXAlI|8_JE^W9c3_?jQ@4DyEmCmDKnf}0Ug?1e!N
z_Vf<I42p<53iec}?IfI$K=iOs><*bDf`1_ToP{D<MY{+s9l$;+oTAIxRd8aU?<N>g
z0iwH*M*#&7A&aW~JcVN_nD-LqQPIvZp`BK$-a@u9Fnt6(Cvh7JUr|Z+alNpIqOpF$
zc8Wp!3vmkp8X$c24CI8M^n;~9;bJ`$gM{J|NCpeGwCfHLx?Io~D)dlr<cttSr{R)>
zF%)=77Os2*krcs!;>4-Ks8%$l30J#u&7=#ZwA;=QN@<OlDd@B5b(kg0r0`F+@J<1I
z%MtD#f=sTE9|gO4LhL*!<_mro0D4yVz6gp1!gu{pC=@n5hlwKLvI?YF807$k5+Rfa
z<~gAw9U|w2jlSS62s=uFa#5H`X_HHWH7%(x3xRqn&$uEyrUYK8FpFx}%Y<2P!$i4|
zHvqH>!RQCTR0{no0aGP>LN~xwVWS?7RtxLsbyg$1vktCZ6Z9eAY6U6P7GD>p{Q^rj
zgoPBFsS^h15MaIFM!U!c;U4YZZVGpj=>2y~sEdH;ZDGeb47*V<rbv2|5H}u{nuV<+
zAbLkIrK0f`;p4*~twJ$Ehtf7-6<r?f!i+U=?XIx-Pk?m@!_y$rDa5Y@*CjNUV`TS)
zgrxxM7QUw^@qOVUg)Dl61EVSa(kq0T!C;?o_&LY};YAEO9|~nzAdiF<qcEn&Lg*fV
z_6re3;GPJ1F0lJl_~;56p9wNre?AwA*TMT2g6u9(UJ9Rm0P_Pvrx^?m3VsYGVMu76
zgT`0Fd>e=i3uajR>!q&+r}ts$jqtBKMqwxZx)wvT7sqCUa}e9qm>Ea0|8LlJ635(v
zrNiQ_2yjP41G-_I#gPH<!bP0i4iiVk<;75N6%*+R;U>P94&pBQSiqo%Xhk_mPqCWb
zF<zn>nbjW?6JvqqEzW-e)<?9ULLFc69;H8yi=$tl(N9dG)TX~^LR**s@qb!yC&VM)
zLnKh_p9Jh6@tZ{$eXuxl1Uw887t#|ZRQw<n2E)X+e}+i7IEoG`M2Hpj5IHHXnh)-j
zUUYPW!;xaPJ-mn#r_equT3kkjtubO#7`RyR++Os>iSKNK#%ZyNc2M!+;UgdkVnh}s
z6U7a5tDF&w+yRy(zDH|_WU-CnASvSCluAt%lV`x0H1WnlD5Q&nRuIV$^>Vr&GR1r2
z(3&OQrE4x*^e#kWjySp;in-zkUJ%U_7g6XwU+kxa$yw2wp6dmoAI*B97?cQwBC(G4
zyTxKH#X(BMTXgB16aV-YjpxNx{@^Z%ZKjaCC{C85@sil1p9av&qVyPsc18SxDp^X!
z_aZUtWnvelNXo_9yXdPBKcp8>rRen(2CKxKW8u?P@k6@0t3|IT=&KQH=qJ1;W>P&=
zt+?$Qkn7@#Rj_bF-1#x|>cnyiSJjInXiwT8{`oWQ|89yhTCUs@=hK$pwwOK{qK)F>
zKcU|w4pWU*vpAa$d)*N^28u1>hB5G|RlL;(g*LJ50Z`h-Y^wOWE55o76CGkbZ38>S
zWyc`WC00@5{hsJVPw8&4h7y(cMOin+UwXt{Es*II&(l_-PxQV3^AE%=v?O>a&VB&y
zk=XAA?y=~-0HFP1IITgRh-+wr{Z#Cwa;#@!EUhe_iz#Q|_6sqt4%|y|ryaNfF_mh3
z2gRF<p*JMX9SxLMqBxQAf5YOM$&h(1%4wVOMojz;GIpAABjBRF#>EUK95hxUI7iK`
zd+2l0n9YVy$2FO>U-i?J<)hDEvzv|>1ZZZz4TTe$MRU*>sJYq?60CXc1%(jJdsG%5
zs#!^a%P@_N4LsC`YizE<ZiJ@iH?Su)MFR9sX~wq$G*Xjbi&>A-7!zo;rjw$uF`E7V
z0wz{-_I;2z%@qnhpVs7^ghIS#=ev+h(9AW%&y=X~r_kLQO)V`6k~H~LMV6xRTLFbs
zjrk6cG`;5CW`L$^>~*k|p}9cIhD?o|GT2#~gZJQ5wkDm9#OG+NwUEr!=qdh^r+Gs)
z;Q5*Zv~@YF`C%mN7HGcz1$~8@><`daq%k+ZRZ^_^j`nsXn(OTlIj2D;6}N+Cfd?#H
z(CB+iVB(_YbE*@+r0KSX`O6w5JtD4XX8sMBQccw!h?Z$qP~}OvX7mh@3XR|20Ik&A
z_!8!;G*Sx9Ue!n<fKsi=@dl~U7=@zonr7fvsMl(~r^AxhHGhPI+|XR6I=MPcqrM#`
z>NQ*DLbO5i55-t+YF5$C{FY`?H^^<xeo6{9Y7Tw^pPDpQv^Z?m<QxO&9nJE$>2}cU
zP6TMH=93TLQ=7(rHb}eXU)t^8)wmpjGaZ^XT4Hu;-liaXmqwn7#(SC#-%$RcTk~Bq
z(C%vvn8H$zX2)VQ_G&!80O`|I)dB5+<{jD%KGghf0{ust79QlWrn3MZ_G@N%!?h=x
zoF$mNryBDkn4o8xS}Kfqu8H^xk}otKmhkYUW{w<o2Q=T(ig8d={MUc~8muPB0y3{O
zeN@OctQqqsL|<$E>4*Lsjb9b)+G%}4;Gw-%K^3G9T7TMYIBF-Ff^*W^+ClHIww@vo
zN3{8LPQqFH`Vbmjv_VwCaa6mTO50qu9}uRS_ESoWxoeN3><0BO+D|C$>8X8-Uglof
zC-m?;rkzj;8E>uKIq3Unm#&A1uePWHeaE#iln(II&ZNo{f9*x`FhD!*2FMBRtB;`&
zsLh@Z^&ssp$*>!&onnIlhG_fV2MN{I=l~X`9dyT#^x@j-N6?7Sdeb@mliEebfH|d|
zmkz~9?fmoLqO>#bK_gnbZa%me?Uh~NVzu52z{P1dje<|7wTi81jMqlS0xUtBPr<81
zZ8E)w&S<TFfxk&ww}%i()=nA==oIal%@9e|YcovXMw+&|1!(D7vsLKK&_3#eGnrb8
zRnX7U{$v1=Y_0D;H0Efn>EueT_P{?NdD{0W;+e1gfL3>Bwas)L7idkXl&DbaPg#&6
zZ3$(minZ1>Yb9D;Fbtj3_D2BhqE=s=3igur5FMhpq7C~321~V$%ivp?c4<Bo%eB_U
z@Vi25H35B<+8(+rtF*ba^1G_F-v^OuZ4;G7*JxMLwSG-2(oxe|t*0aUu4@-jjO2#4
zg5GU)+P^7AQm_5?N1!xl9raJpdQ<C1=U{GWZ+l@dx3zzM4w)wHNA&5eW^KkRSh}N~
zIShwev{iK6qE%a;4eT~;gCk(twFC5{-PHzK!ix@V^H^YZYON>~)}@Vl1BH9q&TEkD
z*2-y3dtdu%0@Qo7-~LYP&t7d{8c3gZ(@#)*plzi!^+WCF^g)0}TJI}p?AKnQ-0>6b
z16lw+)sE-~d8W1f1bWZ4M<`zVLTgb8e_v{QsFq+rn?c)?LG58Xa6{TOf0%!z4Whv3
zuvSW|q}N)L20D%NM!V%TMD299A7K>sx&T_gI_M_0gE;EmT?;RqbnRE5aagyM3ImVm
zBr{>qStl!ih>OmP9!W=aHB*7&s`Kzbqnqwl7v{oU7wZoN5Bwt;Q1H~1R-?~LXZqi^
zNN1Ku)u7(GkNeQ-qqC=VhObUG0WKcbRkwrq={hLK=db&jf%yPk5Jl8Z=xmF@1?r+H
z)fc2&Lgi$^y7Y%o57C(>!QW8b)-Ul(hUrQv$ri2)ehw}|H$*$dle($%z@5@Pm=3pB
zMCt+;fQ{0nQhi~xZU&7hMu#{r?lIj@3??{Ex0XKMeOkBmBXIG$KdHJtK^O8AmJ)R?
z|6*uobUP#<NxBvZ`jT~D1(fA6miiw*gQFR`^B(~$Q^yy=nJnGslq$&9`A34}=q4J#
zdaiErA(+k6?e@i3@^!PafO1xsb`ll}bi#FTg*qb@)QfZ$|Dds0w}4jbCAzRnfIg=y
z55hE^*S(^s(FNVEe?czl-qUBI^OEk~9+1nr5wu3UqI=+sahB?CM#FBIZmkErDAz5>
zhxrQK(Z%2@b;18Yq)Hc*3`<va3~i38b??%vu|`)J0%xx2st*9OR`*UQ{JpMw#=_tY
zo#`g1*Xd5#L$Y4S&7;L#gYG*jiN2|O?*%|_>3%PV%x&GTpMh)CZCVV`CS4n4o||=l
zP)zlXZn72hT67cXCv4TZO@d^b?gnMk+jR>jz|p%ptG8jkL+AYtCgHK}$2|DduUj1j
zg(tc%DHHTmXRw_Xch7VU^w4~+E2e{XFLZy=+VZ7ts08{0x`p-N26gXrpl?XWM#0i6
z-E1n&8P>g|{nu-qM+DH$SVS5^GRb0hE<{o+65huk(ku>2(U)#veH>n7ScK-GG1FqU
zD;l#bhOouMr+zH{q%~Kbg(n5;@-6KDfJ}kKzmy6pv^cs2jYSr$oPJS@0D7I2SS0NL
z+Bpk>%2>`@SVf}og2fW5Yr1Hm{TS+(Ey`(Oam8YF5}YZuIBp1$a*N+ThC+qK8#<U&
zY0)+kjruB!%Tyn6)xw2><<%BDC^%AMk(PtbYZihfU}`PCr8Vt!i|=C~dBft!1#op1
zB~%t%Z?T9nBMlb*;b^>RQ9!%qTNdUNV7hIQOcUE^F>5CV(PXjt4@fp!%xnkB9gBPa
zLt~5H;+6_dbyzgH!P9#dlW1k$ZLxrIK=&<}9GLI1@TTB?uSE>qRDBlT&}VfXSbXIP
zg@+coD<S#VV$MjQ^;`HHf%+2*7pjSWY7z1bjn6FRra|Pn#lHja_l3nR85&<&B+*Hx
z0So;JDrOtB7?%VuhAd*;!M(CzufW8xg+G--yta6YA{TEg{`dkgc9u#iO0&0=(wok~
z@+2MccC-|~1)7s(2fZ*4TMj>h$Pr6!Cor8Yd%i@Ui{&WF%^kJetHxMdEl<?If}5p-
z-W#p%md2Dv^RP6eWtFGp+qCxavizqGipMM;{s~YYODC#_^tEiJ@5CIp)Nvqwmiwtl
z%inTRGn@&q{LB?1CoE^u3nb98@fs`zS$?$^n8B8rYXBBv*|-{dp_U&}kT1;g&@{@Q
zhg(M4Ks3T~KaJ_6<v6-pPFb2X06WSu@g(Le+VbgA%teglI7-#UT4w!#DT%W*JPp_4
zEwxlAkZ5@}0hZ2K`kMed*>dLwkQ7Th%3P&dhGfESn&ln3Rnjfj(WX1Ya%?pfcV$^t
zJ%(tuWgn%Eb1eTgL1(UIHwBjSEaTP#G~aTbC&qNvvTG_}3M{*Q!4+B#(Y;+{d8HPO
z#g=DvXe_ZjN?GZ1mg5%!?7ZdT<8btXWy=XPUbOs3#2_wNme6%^*>X71V8j^d6-(PK
zfGM>sr4UQGrPnKv3d>JDpiyaghlOiZmdye7#i)dLy^h8~%TrO%ceZ+b33^AZR#6zz
z)#`{H`U0#rP+3Nh)gcPGhgwB#fcFtrE8oMcMOy8e3CTFC_i3I^Tj{SsGTzFOb}k84
z8>R3*(W;#u@@K3*nh&!{Rsr-%O}6@A9ZjWGmc9@$saD~Rn4mPPb@YjZbSooDqGVX<
zsf;YsYR^P~W?M~L4#ga+m-GldXC>0M=DbxA)refR$~y$KYO67gkgTzCSP#3`tai<U
zNUc@vIyiIPDrO-@cEc)q2wa^NR}YkWt37dg=r>qxSPR9QR!zll=9bm%+u&|n>F9e$
zjaDPZLb1te3vF4Nt;U~1;~lGoqoLPgwR$dmYPBj(M_-#&BCUn*T50L@T!+<<`2cgY
z#=j?p+sHa?JTMPi|N0yBj#&S;7nmW|$G@TP;)hyiQMx9~T1M;iaO+8wDU7g={s`Pj
zYyE#IT<fE>2ad8Xr#DB8^`a8MBwOFq!9<F+K|jWuYJH#5j%n8K|BIg~-MU!<FEXsh
zTm+YCeRL5V&9eTMzU5G4{SPJTi>(J8XeVA`J<<v?<<@@|0j<Kie;G)nbupzDtE_XW
zD7xA@oziL7tbe0zW39CzJtmv2t$pC(9qTX70<^_CgmMF|)^@95somOe6;SS4yU0PF
zTEC{e`E%<Hb0GP`dQJnT<fZkJpYi*AKVaQTNv<L5D7v~|Sr1a^VA#6f2;6IHkN-;9
zZKCNBYHxF#Dm@)+6bs;mqmAuRU_05=grV`U&Gu%D{)kOmz=rd<s{j25-n-e<jD(}^
zHgD=6;$gG+TR?l-s3^hVWz$4!G;f<X0T`f<O-UB|d~M$O1%{5>?5l;IpAFJ7cof-W
zjE7`^jh8hBc)})o1Nwq&z7#N)U>mP*p%7|geF}YHHm5!UN{r2qOa9xd*tF4d`?Ss5
zbP2@U6wwnY(Z*cF$dYV|Xp^686PE#z6q~uUK1j83rdV5=O_&Kl({1eOM$fRZ$O)Kp
zfl=#i*F!(YX8SJ~Xs*pBbBN~K9LR+m7i<FP5q#0ch0>juY}D3p__EDfdLUo1@uuTl
zr8ZA!=~QOpL`$^_o6=Q4sk9jvioPnF!-eRpv$=H{uGQP5_yhWm%~C4IXt6nL17})o
zKG)L@q|N5TW(>dG=DX=Ic-LlkEA%^TexgF)PMbe}2TYgEEvgo}XVYj7{cf9O-=Oin
z&Hd>hJvN$~knFW_{2N{z8)^HH4rt=PG2{2b%2+)WcaDoW4&NM^K)L~(n7Y#-hnXMs
zb@T%>UtET!Gjre|I2UH<1eA|55%eN)W!z}m-5B2`k`c0CrkGadnamz40Lx-F(H1_N
z(NlgWhfy{_FPE8k0$d*R(ixcfOx6L2oMi^6vb=yf{sv%$Ou{laT*Q38o?-^YOlJW!
zN|@8*A#;wodlcMx#+ovA7ntdkBr9hmTSttLbupLe5$wcnPe$WmHlNC6kFXU_(CEyL
zq1?I)YenU<N7*o{o^xftrDwhyyU7-f?(F3`Q1D<koq?n$yYnZC8F;Y@V~pt-JD&=K
zyxBcL@WO{xAVMSyXGLT&WY^ha*gVUQaDP(GhZ{E*fg+hVcj#+i`*UG$!QWtRDl$p`
zP5Y;FOYz6d52#S-a|=(%eDO1_kY^9119@2*<<eJMw!yvaul1BB*q2Bbq3u5uiFaWx
zU&7qDF*y^#Wizkoay!Q;@cE_x!1-oc(Z1$hybGgmxJ8C=$WHQi2#r7zYy@a;$)C31
zP8#f>BQmE9c6|ZxNQ1;3z>6}tx&rDg%1PHC(xqIje*oAA$_byM^O<r?8AM+xOJ;y`
zG)tg>kgM6xR7&P;)=1H~6K2l)!G)W#n;{uvCZ#HlShI(t;6<ES7p0v~o0U;CJKk&!
zEnXAMmTkq*6U{2<Ea@3De`lyCnO&ng<z%zz$Ml$;470f#A)0Si;0SWg%=K%am70A=
zLA`3T=%vuVX|`t&ptsCcBmm~N*^P^kY&4UNg83%18LL4am^pj{$%keu5S5cYGJ8T1
z!pCNnN5S=*Z94;lPt5$rU=UBu@}|J-Gqb_bRI~HkOhFU>!mN8AWCqN_0%3m8%wz{-
zhRmK)McON~dI~@fn~AjOeQowx2Nd3z*^LIao%y@8ShqJHPu0r~=2gz%oXvZu0>#Dr
zCH)jf%`+XK=W4$H8BpBJmyH1DZ9c!7YF2&BU#!PKea+`m)yi@6XYsJ>XFk0dXi?^$
zCD6>8tLPOTZ_ZakG1Xi*0P`8<gTG>g`R1d0AlYc1ISqYH=Ai(U-ZB3t6r{!6bTdf1
zxz!&S_FeN|=>W)p`J4N=bnH}Ls9{g<u6i{e20c`|29QA2C@WZsP%WJazhhM&O3|34
z+H(*3nJU9SVCk%C`x5wcUUirfbY-gZRNhvjnmQSh4XR{UaCcN$6ff*l#iT%_PxX2g
z>^@b^cY`xSD*H&9Cv_#=BuDk?lay6*Rr^x(!%Z!xqe$-R_M33gL(Qc?!&5z*-cVlZ
zHES{KW9k}H4BK11H3lL+>WwXM##cRm3fw-f&bSFlKXvdJ==rOs(#QhT?PbtAp}t#+
z#wc~J5$r{)r=5dBj9MQ;Ux|oSAENUSaq1Bi8#s+x6u`u**KLLS3F>SfqKWEhu^?yE
z<+M6UQh#j$g=F=t5DYCveSqRZsp?W&7)(<yp$e;X_51-C%v4|Xfn=7tk@8*H>SC%C
z&QXh>qc2xot#<~^Q=g%CX})?f?ZD5fb7`OjYL8hMTA}(Z?GuaCb2dY<SUvPMBumsA
zj>E(`wW=JA=ha`1gWd)8CMvtCR#${!NcHLu{{?ijdM`a<JJdTy!NXp40u@6&Q8%wf
z<B+;{KBYcishzGvbXa|4D)e8gcb-M(8}+$u5Vhm8>4Plp{6~fm@!%yCY4GGfm<kau
z{(olxdW?TM3Vq&uc`YW$mw!%<9_P#40p`a~{tD{;JhKpb0sJM3qMzV*w}71FmrAH+
z=M+CL0&FCI>^0D$`1G%!7|qw!115$q3W680yx)Crar~0kkc{WmVc-(@tkbZY$j3~<
zJe}dwqhLOXcc#jpWd8O&NT%>3cY&nxg%nlJ<1>vg+<gA4R;U;9ZdO#YQ^dayiaH91
z?*LQIAE|-)O8(2wpjgG%PXJfX-yMMa4g50->)ztOj)UFX{0|ARbeF%25E$whHqg4Q
zli%0~(#6aAAaakNPy3H<UQ4(CeZK4xNDn`fUIx9q9lf;meZ13e(0IVllflwMKHyV$
z@raj2f_u#GzYDwl{Ln$bJmEtr*8GhBWjPd{^P83U4PNlez5w@<-}gU|0bc(OMmWgN
z>xH93yvtQsdc`-=DUD%%^96vt<{!2L<qiKKErIRy!pF;?XfJFIhm3=;p331Jg^P6Q
zItizX(B~oCqRqXh@YXO~^AbvPAbCu9K_}aNgr)1~M;9(X1L$!feIy+96Bh4*7pH`e
zDV!B4gpf#-P<{?vwBXwd$rz#87nreveg)O1#R<g}{5dV8+<;=d@XKkqpCA}{qc2g=
z#etj=c3y)sNy3!7a4lJo(S|lf@O=whs^Aq4k#ynVM1W=pZ#uwb3cB&&vIHgdWec+X
zn9&?z=Njnc3QzE<1(YLf)VIU8d_hx*&a*-|B~lB7<ZyUVC^S+IzDS6tU$j_|P~Crt
zuznI6&j~kepm0@qMjP;IA%)HkUK5_vF1J=VM;|+?6Q1)BsTal!g6k8$kHB<25KfK(
z84@z>(DzEX)~JX1Vc{~Jjd?AM{~oPxgg!fH*ohJ5@YG(+qBXyRxS|7g9Yr0zVx2_o
z-!OPs+)d%XBckX3(B~|gjRBa8xL_<$j*82UK;2dRH58n?_=+aa1Ho)GdWxG?K+j9;
z{f=q|j)?=~(djKdJO^waadAC5eZ}t$(Rf_^ld|=G;#gXy`-|s%!3Bsi2Y{XsU5nvb
zpg8<38iT}t{swlixSPru;>5u~G@cf->6l-<SoIUQ1kw2){33~B0KHnzh_gNzf%`96
zyq5#JDdNJX7*ndaopzmR;)V)%kuI*GI@}DArF~Px#G<7bVcNuX|G=5_iD_kkahY^%
z8B8=xo*;*b*2!-d17&#HzZ9T+J?%_18hxg(SqpMvx|SYSfz!XDH%{>MibR0vGp4`Y
z0`nK9Kh{F#;`GYJkg1qHfgU?u)6dZoJnrN1RYn*o{@bydlH0$UP(AR@9!h@v=Ba=e
zzc22@|M%^=2Ic+9p1}V*yc()@Oz2d=+A~J9`*mO%!y(|xJRAiSH|AJ5tv@}OW3(Lg
zW4@dP41Y$m31baoIC_eQGw-~hkuyJ2DN!6VG=#C9W=7qH>+wuAot{cye5M05otZ^v
z%rlrzeSm$IY1#;`fVuh(NFj6kI`oQ|&C9`+GXGG@xs0)?r?6r<liUas70jo_=&WN}
z#sRIK$)k8=0~0~-r<=@TS2VUVCX|_JV<vwE(#{N@hfjBz*bgwm4rab1Ks%YeZ^P{_
zW^)_*?lD`)-)`na4Ei23$NOQSpNXMc{|PgTf;sx9%rq*`f5vQ4fgNTJ&w$2jX7oag
z;tf+03oq>0TO&a1+1J<5=)i{1O2v_V_B|w>*o_2pn4LwNts`t4?M9v1OCb<(VHL{(
zeUzO~)wZr|$te&w_WQ3O>COhwE5Sq0viISzC;Rmz5HEI`FUT==v=v<RW<4i@^I?5x
z$>7U=s0P|`wuCb7eyj-x5r1|xRRILBU;cu=6YTM2FcHW;oef8W*bXWa3}&0W;Zq1(
z`3>eUlr?=0yJ4)~1n9-E`V1LFW7*FO(3;HV1!6EMteh^*RQB)3kV#{=)3L=o_6cox
z^Vt~`vpCBt<^a2ZeY6#J3)zB0P`|`(TZg{OtcyD&uds(Hh*io)?uB|8t6c)u%GrRw
zpise%KLhC7Y^VMn6dTzA3KTc7dsacQnQftrc`Lj1J{0e=5nn)~gAH|seka>PW&K@j
z&=2(cvdWq8zMI`ZFPQu6fC>6~*say*v*WD)hJrJ<gAQ+bau2Ox!H;X3gT@f9eGq0N
zx#^qe%uE8ej*4#+xdsF_q-QuAx@MC&VICTjxviA{OX052>729Nt7e!e;EG<tU?Dg0
zEx1<1RW?ARn6vsXuE$L>gZcB^DtZ@O;EFy4xyX5Bfn4H7(I)&d7rg_}SGbK0^e<>!
z=PIk<#ci(11~6^hTq<zr<_!0s@e#N6GBjRr1r&9A&B<57;1S7Ocew8?Vcww6Me_ES
z;EqZzU4jW$i68CL-6R1N*>aai7Jxe;38YUd1xl9Cb0bJ%{17O?5>Fg|&`U!k-jopv
zl~^u>Oqk@tW++BTj79_dq~u5q=HirOITblaO1`9;{V0jgA@oH{coR%%jARm(6r@Rp
zl<+rKvT`R#vE=Y9_;gvaJq+qql0|O;^M+(6UE__CgLsrl+a<SNqEX)?`C1N{UP<Z=
zX!J>vyTLt>Y@l7&L&?M481^Ha=!e6PC5LxGqhB&{3G`n}(w4xBH<E;xkhGINpiRHM
zbRoT09q@T(xaKH*5)B0>{KM_QJS^oSF?whG<D=+vk=~{k+EJ{(B7o*9eP#{fCRNhY
z)Lj})3my;Y+FY3Ml)g_jiviL+dx)HnD(J9Gpwur6FhSC7<ZrNaxf?tTk$y=r-B4*2
ztq;R-s1cG8(m6YTa#Fg)4g)+TeV0zqMB>xfa3)Hszp4OCv~)G)29u<Y)sRV+en<<R
z6sh_%^rcGYaX?Fx_R2ug@hJtE$dKMj0!*g#=P>x2E&X*mCLu?<i}sbdQg_NB<w>vJ
zf!%!R@AEM;XQdv_04tFCZ$x9EH1ao~T$U#5U%=oMX;CUPN~Q4>NiUP`Z~`fpj#>v&
zA)QH!i%Mxk14OE%BRAkTyeeHq3C9|#Pd(7CNkiU-iCSrSA>6($?WXMI4e8f;;OeB^
zbV90L+BFaUHb}pwWXetHl%E0JDLty9n&B?#ipfB`Cw-R|+1=90Yz*eU^ui(Z_26_o
zu=}LrN&kT~_824|O1)ws@<{qP6pfFijg^q>mmW-l-8WJLiZ$BF?%2aods#3ARUKrf
zT><SV+p!mYPO=|9f%;+DNe{{yJIgAqA?hMK+Xw8UvV>XSTxF_jP;`^M_z<A(vKhaF
z^N_8foo|qAn*=byvR`Q75F(pRE6PxrFWrV=vU8MS36~X6@Hs+uhO(F^W$(Gd!$?^|
zKA@vyPiTJ@EnD}y5$?YjS@ZX>8!Iy!ht4?Jyl%|%Y1wBUP>h%9voVS1WP^*Kab7m>
zSHM)rrWe8eW|>J38t=$NT8#|LDycp`&fw@tfL$<HxdmVs4Qf5n*l4i79F2Djwz@(6
zzQJi7TzhQ5WkXN@(%@JI&;|^yQ`qUK;b0{+Tn!)fVuZ&HC&a^ixM44C<x&l+hcO9f
z4LkE-_ky8Ri^fL7MRauLvEh4x0Ckp!uR-5&xg9MKPRV^_@FGPXL_zaRxit@wQu!iU
zf|ki|d;mQ+y`stpt)2=)isXAKQdn@u6o1l2)<-d792$KU?HLgDQ=Fws&tDPv9DWBW
zyl6^;6?ZK_LKJ&DArhvDngXA~6`QPJFj8^T6aGdiwpu_hS|QM~C{CeKKs`aRZwva8
z6#9l*=%*^;-QaM#;>nNb%up=*6P;O#k^XQdTcLc6z8pmfU01n^x9AoxSA1#(QmJ@A
z5s_+zxdMH)3a>PnxS{xg7M=BqQa!x5sVJjIaHC>k6&hO=J$(>yFuF#GT_>a4`paOC
z7_Fr+yNi(*mHB!a#rz4;V@97OgB&+HI|=&!Mh=fKC4ok|Y$${n1*1;yzZIb{_&5Go
zRz=C6<@r>Tw_-1yI$k+pGXDN)lq<wnSq(#X^~A~ed(F~QXkXh-#SiP&oS^$}y(#U+
zH(VQrOB=UQesa^G1^&OeW-QdUOiIB>w~jH!|F?fYdB4BZ`!U*mg%j}i{)l5h`1`pN
z{<d|V3(x~awAea$<OBSD$dLt(zGgT6wr6_ib4d<N!k=h!WTxq$=%Hs8QAL0!Gf0nr
zFXj{##vEg!f<OY9&dHDoV%B{R^k8N(La_Mo-2e8&t8AvR6KF-ua0v!=nMtMR_EpBr
zmp1tLPk22B{|{%=ufuc%n^6qBlWZ@=<xjC^kHc0Zn|Fh1hU3_7TFT(tS#-%Ku?06^
zGnsA52baQrL1mGd>=z8UEcVn~kZkt&VUQg5)Xx}b0W0@}LLtk)4--Y~Tt{3G7ue;$
z!~8||Jk?BHVt1E9vYh?F9(F6(QB*)u!%m{hLw}9ETnyK1*$K30y3VdqLgprWZ8o@D
z>`X6kx7h}&s%&AM-hi~Sxufw@w6PB;=+e$+{I?2bWfx($n|(+xg8S@*V;J^Bc6>3o
zr|f_?6rQp1l(&D*Cej5n#QyjW%-ZQWH+r%?k#BLsJU&xQMAqrQ34G0bNYB_e%q5x~
zJ9ZZxPqb$Ts1Cw`eMHKR?EQ3%#EE@D1&4>(BnA48upd&`)|ox92lL^=PCgFxqwK2x
z-m>gg%EY*_U)}_mJNwpG^vxO%R!c8PPxgDtMtiaDR*(r~>mI|~Aof~1`hwXjdFYE}
zt-4_8G&|$k|G)Zo(LQ+jie->pQA;=PN?jAwe{!NqrB%BKWA(^GaAD2IZ9rI?*@KpK
zdno<A-WA2Bdg+GA2cWRgZY*5dbcZrio6~7GzNLmz^jj0pLt)#sc>KNn4|=-%5=0+;
z_+3rq=X-KjqkaEkdNuw%dkjqmlSGFR4l^n$zCOZad`DwqRI_357-NG%3VbWB-53t}
zFqJlBKbTof^~)hlWE-Y0lu0jw3*k)2?`S;5RL%xWG_y$w636&FMPmXJFdO<w%+mx|
zy2`AlM{YIqNhAhP!<?#urEARBRK;A&#O(mrz<7QR^(Ka=ih?#~Dqa5f8IePu{uyJF
z3&laE={97BnFAAn_J#@l4A}Op<-33hXLq}!F^g@(KPK>h@2;no_#>CuJ_R~?%;_C)
zE1!uO1mIa_HRUf0n7^ij6f&_AjH-y4Ku6AtnbEYzE@k{w@Su#byF_Pp%9+`8aa1tX
zl<ulz=3fG66{D~Rxyo2kK}j_;g@OX@%sz@v-DQdvgX>@((J}l7%qt4mJ!CRx!Td``
zq^JD=^H~$X9N404c;U#dp|!jd+w>O{JlJQpAfD{X<#hjhvCl3*^aML05G0VT_zaU9
z#42xqM6#2p>>-LBMO%?*)|pl|F>D>(hskUTJswloN~$r-We1utrabmiHZ0|{0R>P$
z%f{2@;UYW!HX1Lnmb5Fp%pTf;;a*|ql0AJ58%{CuYi#C7Xw<SUA7F&n*|r(5)Wn)q
zps$&gMWOEwYeZLS3oCzxzE(Ey15D6;Hh?y8J?v!>eZ6cNg@^jsMN2^*u&=33@F5#D
z8tRYO^_MU~kJ<DCQ0Qmt0^rjVJv);gKX^vaZs{3&lS;jxv%$9T?FD=Hzw;NY?=KkI
z02@ZD=|T2X1-K#hZz>gi#je``v|;xBQ|NQ&4p3w>h|8sA)=93F>Pq6cpUIh2ZigSp
zMQ+>%G~VRwDJ0Uz=@;)stG&eMH-LsplIh1wmT;fKnPQ3kRe)ZVY?}}Fn<XiKLGg(s
zXb;GcWKrt>djwQVttfqVOWGwPG3iPwiD|(<Dv6nEmo^3hsZ%<BA4Kj;A63KX1L@)&
zfasShJ?NVOFQk92fzyN1oOhx42A?B?sFTbXKfr(2IzN^^w6n68u7Fjpx6rw!g+e{+
zzNK~bhUhHx{&H|92E1c~i2v{1LfeGDeyGRa`&RP6+@JIbwCorwDlM^R*3jeVC{si=
z(5`x>&I<rOOzt1R_htS*ht^=mxD{LoQ@0j<QH&8~L86(H^a?)13{#vqiRq_AZZcC_
zhrVoPI|bx&7zw>8a~b>NP|st=3`0Gi$$kojv&=J!p%gGSSwJad>i&jE5u<<jnx+~z
z9Y_gNNXvqA%nnL5pJ&dm0QLpuyV=mc$h@KF%q3<YB{VNHRX;=I3UiSH%%w~P)w-53
zo+CiYneYCA2?TWLBC2GJ1K~v#Q?Vb7SD7v6pjXYzy@|#e<_Eng*lWzXdU$h-Iq8E@
z+-81Uiur0}e6_ID#8_dOENx~g?!t>Zj72m=x|sQ+fPIhoZ3{%Y88;uO-)EwtF(p0B
zZ##kA%lsh%rH^@s1NVT5pcHWmA`}42Vy)>plEa!bQ2aBGO`-7mS@tr;dy84!kAOMP
zzP$m1xx_BHLnCC1Dxp}xE}{U*RaWeRNG%(-849=X&WA`l8|4Jo?6|6*<!Hr!f;Ejb
zgf;sMB$SQFg=!cZPC!_g6hSzG)j#<XrcbhdbaeC-`@S>uB3a)na4(7-cmpfZtOee7
zc<Ok34J)zinC(!EV}q|j;WRsj9>no%1Fh2&*lsx_6WL7^q&UN#NQ7h(+d#{~WY$3m
zLkR6qeNrmB>o4@Bu?6}!@GYDD-%7B>Y()rQO4v^*<Xg%P+oG?GjiGb*<*fG|h*YpC
zbMZ6YV9S1k`8swIt-kBo)D&<HZ25WUwXj>~V4$sR8XW*=V?Uk;y>|BGevrGYIfdjq
z*Z?{d+sP*UPV?Wz&Mb#h_t^U@;bJ%Y=2yVnXY~dU?O`1iK<j1Sy9miX_Uc4PK443;
z(D#t-i~@PVw!Fes@RBu;hra{t7^*uRWTPpXGQ|G#1dXrQfeVlvX5&5wdCiv7CpwRC
z3L7e`bmo*4Q}W_kTcCK1J4&(Q6Wn<XWCFQ_JK#=o!&-=(;;J@bg5$Y&tzj^M^QU!l
zI`=hYUNX2VcOiL}+eiPTLjm^=g#|Bir|K}4OI-Q{Kwsuc10Y$=)zH^xYPc?B1oZeA
zY3x-vRm(kD57Fz~(;Mi#!FAIKt2%CqH|*APgU4X0f%}|_C2w-hhahr`OPU8~ZgUH)
z(Ada%bb&N+Sw}!nWk<`kJKQ()Qg7kz<p8Xe%cXn$F1LWPnjKs-?J4!0+_%Lr-^EF2
z+k2n8K?|fFE@B8=FL#69KYd(zG!!3j_q#zJb3MyJ`ng+cf&GMg5CO?yPVR(Z+eu=n
z?A2bP8AP9hWa~N*N695h$2du1=}g37i5aEBT_meaVCbk`V)G5A#$Doi58il4JgGp}
zQ?iz>Krcxm-8si3@;&G~E%}HlwbLcH^Pq56(v}O!3zDmG5UG%?NkL<eWVbE-zEZC)
zc;O=3N;BgwyYLX|o-)G%i1^FiZ31+V?9((f2Fvs&PGCc1-%(gHR2G#05+>W+1<(jt
zpc)RJk{zI<8BwwbV}QoUo-yQ%EX9eg1X-#nKoev$C`6hl6I!8nMz-q$hMg>{DF#WA
zjco!+l`a1F|E;X~k_`}E`62Dte$tPm1@)>51uU&z`xCrhll>07UaS2YLhEW5;Q!mc
zd<=x`HbMCN=ZfF)_b&<Ukoi-X4*5OBRzTSMpd7t_*#zMK`yNoi-u|<W7}<fnuOaWm
z{Hvw8XZmOf;K6*gj%I|}r=a+U7sH+e+A-#C8@%^s&bR<IkO`spXb|%w-QmH^bb2C%
zFk|T&4`r%40iD9|1+bRQEO7!_0dta8(C3-jT_B~*$73OKmGKydX}ZBY%790=nQaTe
zwJ}>e;7kv*ypz^n&ly9CXxXvjK7>JUHl4DIC)p&I|6g!oW`l-fOolyhy_xa}&<$if
z8vz)^9RD0H2Qy<SaU8;o`UEzknB7w$8O>PG>*oyfo-aI4V#dTlA(@#@>%kOe$|m&X
zFyj``9xRtRNF`l)48BuHBPgeY=mo~57o)3S=F=OalBu;sV;%Du?XT*Yw`KtC4r8AH
zu7zR$fQeSdg{lqOn2(nLC4qgRgh(RG&^>d84Vi<HC$V3YLNb~ChV~^X?83?P{7J=z
z5NsOTNi}}u>~FNJzr%h#1_r~qxnF=pa7J6vcaqys1rw*Zehzjcxw#WCaZ%g`I^q${
z6}<<&81B(tG{$lPyCD+CxzLoH=Jp+eGx6L5ifnsHJ{^m`W0Lz9sQ$xSvVz{TK9W!N
zV4%K|aEfFemt0PPPkxe5>5=R&*++|p0LdHLK%9_lq5Nc^WJ)I#f+Qa;h23CDBdszH
z%R(2^=w*q!VK+(kxei>q>^*w<X32gwg+h)jdI*C!D=SQeh`vy^j<!g}vZsGR^qg#?
z3Zl<tll&m+ZV(U+^N9v4G-$kR5Ss(8%;1}S@ZyF+|IGil0_<iJXnWMhZcBq-kJ*uf
z5PQaM^oBzNY$(N<oH>^|4(9M5|AvlC%=J5s8CjIB|39@{i&s-e8fPZSB?_@wERWr_
z6f9do#XJZJSb3y?VhhMqVHIN%B4U9=5)Q`|O;MDhb$6@i99$n%*L8b%)Sl{QrG=$c
z>#=~i=vk?PEuwI&Qi~9!cD4H()_*}b$=vVv{pS0=ncUnvcjlY;K}ad&dpS~d{(#bs
z7oqmDFB{P(>09i;Giv=|J#+hUR9;!hH%hGPeT4V?T)xJ)I&uWZhGoa#Y|ZsV1Ypcf
zN3Hco!*Tr1z2CySePjjVcceFfQ|aVm(9O*}@q0Tt;`E1p2ieMRPc<X~D`LpNdaw&c
zExF4VbDGFO{#yj6$mw=aTFGDe5?BX$iBGkBMf3*%c9BoLQ1p`6GYGwpY>G#`Hwo#7
zbcej<3F$sL8;gdz$@O!n_msrWfNmR|8^-5<YH7@x=R=m4FRe%HNk$*^#Nx0faLWUv
zX!m3C3D4f0By+-G=4Y~TA&mZ)NSjdo7c#sbF}+K_UIGx)A1{MhP5UmuQVqSo37+1g
z&u)OSm#%Au;X3-UC!}T?Ws>0hZ=<$b&&S$5v~nK^ebje1Y<xqPe+P@#Y2Xa>#|=7r
z1#0!vASHCe)GG$e5qfPdr0?lB-H7WR9iGZ%pcnbW^8?!Y3?ckPx4w-QJfT->5$sM;
z{7)$UDC*&}pL;~kK^q!bCwg-`T<jB#p<VwUyOs0N);RI5fTanN%Llz~a;p+PACb9x
zVfQhq;Bz#Sgz5lpqa((tX2(_F1AU*0wJ^Jz`tf1zKDxLa)%Vj5{^Z2y#y)^Y=&O9a
z)Y(9_B@jQP?YyIo()#Z~#ej})&uOGpYSd_=6Z~U7ML&E3Pp4@x9|^b7d3;r{od!<A
z(^vGD30S#6dmZSb9{MHEQ@Kn(^9J)eUCM8~H|X(eFxF2`6apNeKKu#)rjyP&0p+*!
z82|Ct@2H%weh<>kSK$5@J@1ENh_<dp(;m`ZzPdL~H*}zwpi-VX=cZrRquwL>gD=2I
zdfy7>6B@=hl>SUDfvCPsRKrtQszth2L1_?$^7*w!(co<a^DmLJPXpyOk*^!pz7++I
zfHNw}<j;6+QA`GOPeq3>g1TM2hp$~Tan_q~(J1~g8B)7={dq8Z#CgLAdq`|J3g%;R
z#7r35CE3F-TKgpI4y3<G68?;sj!N`A&G_$<{BnQ?h2u`X8gp3a<kQYagnT}C-yk@i
zpld!7iur<Aqp+4wmp2K2;Mcwu;djWz$KCwlRY?C3DsmBpOE_slg)_pAT14@gaF1U{
zJ{PX=$?J9@U<3|3gbjR6^9$h&Kb6l4T|8a*oUr&;JX8I=@Nd4Fc~MaIfYU9c@NIdQ
zgw&M?rbjStLH#Sjo<q;Cc1yPKL3(n)9dMV{^SkU@5BT%p+y6`ll2W!4F{IY=FL2s;
zJ*qAX_yOAVot>za@j(mX&8&U~2U#JL{QS$#orf@UZ1Z4fxxNNrtvJb-xpSS>pyoZ~
zd78f$^No!wSs_fXQs04g^%@_TFzk}R&6=%uffzs9fp?Q>6PV_|@l9I=dvC*n#h1?+
zt#yY1Dg09dj@PC0pCm0Zdx5#$d{P79o!NV#F7`Qq7)u)KpeU`_55!uq1a53SL+GUq
z!cBxy_FxRh_J}ax6$f~}%BDOW@G8=nfOfn`f_1RbL9jQ_!vpyY9wLuAmOqA}fkJPy
z6&IO}jv{NRU6GZY8lg@oH(8b@CM_`9Y>EVHsl!t0uq%?x#YHx|MPVy0FDwF+og61g
zK_y1B)vnbTR15gOTB(juMyn!JTD4Z;uv&}lENGng$Ah)5sMO-|;(ZxkbbEd?L0*5+
zKG0`=H34qo3UJem*(|?bNR%Y#(+rtxFk2kRlwZiEyY~BwE`Q8AHhPL#c&Jy%w9M=T
zgFYoQRnLwTiG5kRL*&V3HF-;GE?*G2E?*Fje!z~k%7SVJ@+7W-JfUhUOCFWZV9}kP
zVN91Vle<3Y7tV^=BBw;k;{3%@))6W7a=8Wt`(4(SCkd)Cb$a3@b(uP+3B}B%k;z=O
zy6Fu+x-vq&6iJH}Id)5#U12ts6<h6!M60>HWa_lZT#=ouu-lAgi@{+rmMGAU@C0L7
zfg#meP+n{?WLeibDvV_oMWV%2Ug&a`cqt$GBxfZVmg`e;l7ga?Q-3)%EoN_5i&^Gg
z&W5|E%USiH5WuQV(3!6Pw8|ca{yJKv4p(WF%CI1nYC*&TRS-@^wNj^2yM~5j!LlHg
z*<{oj3$#Y1QWvFC8<iThF3PMnN19b8wN|UE2^o{&HNzD$_L4YiI<hG}D88U=f=eAH
z@0Aj7CQ-|mky$K9Ew3PTtQ!(-nq+|y@-+JSBr8Qp3RqhNNOer6fwoJ^R%?KYSu;d3
zpFN#Ir?Iq1p!3<GNT93OC<=Ppi^Xbzdb8cyDeeF-vRSxpinAF7y&B9e>A*>3uS9Y2
zQ&t)UF@?231XmW#Q8!y14YZOqbMgLT_6#CzqAYD8;92a@LXaJ76b0><v)DI)*0J4h
zOqm$qg@%PMg7Tmr+p-AC`K+6ZU9Ygf7>F8H62rB@tQ{il3T8860f(^sSiq-VV=Y`v
zVNW5FMJzQ=K93}@jdAkV=($jKI8Oe$q<)fk9Ag&&fiM~;pCfs9Nam5t^eXvGHa}i2
or&mK+Y&@8Kz%^`43A_?G@1A)19E5Zlg=8XB?xAN@YWd9n0poo6lK=n!

delta 127290
zcmYhj2Ut|c_dd=pyL;RAzLwZOvBlnEH`W-9U8B)x?7c^m7+nOFA}Z3ACMpVu0xF6$
zMHEm#r6Y<cO+ipm!Gh)g9{m2F=jY>dXV01QzUR#By>n;I%;L6t)Z5*o+}eu#quc3h
ztt0>5DYC&orPRhoY9o>~e?IVqw`qN%tF6uAJ0cr7ss5jTVv$VVO|W4f?y$8HcQX$|
zl~}|cZ^7A!#nLT*K`CZhoM&ys66wPx)`sor&e({jSeB8Ugjv!@Y$Il+hc3Z@Wj=Pv
zXKYjw>8kZxsWMXv`yLj-#@4Ls4SU837a3jHHXaXczf+y8vbB-KiL{YW*@z-NI7v&<
z-yWSL180@amDxy=McQywbQDF_ifts<ze$}%!`)Dq@=fY4ni9_0NN#+SdWoEG@-~v2
z-=uz`a}OmplGJa~Akj6CXvx5CzotT$A<}jh+t^GM8P7>=B$*=ZPmmUgj`bC6Bv~Tu
zct~4CGdy(C-K{?+ur`vrqKgPb5{Szd)Jb<!yf%EJN3^t!Xs$;#uD3nvrEOIgC$l!P
zIbsdPEfLN0Xe(<u>&_O=MmF!8PAy9QU1THs{hOp0)jhYhk<I@mnVbE~7Kk<Er<EvY
zHZ1@6R@YXv?SE1m*}`v9M^U(ko2;d^sTa_Tzv=pkQfI(o$v0_`=px!8Tl$S_sOVFk
z%tp5CTir;}t+ilY{!JPqN+Qb@V$Bk?Y=Wq7B%)pUt!}Dl#wD?hY}Geurf8=Oty}#~
z`c0H>CE%KGF6N7j?*Ux<t#Xm5s{)~|`z9?F<&fq2Z!T7fx<tYKhHrHnZAZ_TZX?_H
zP1-7|YRTBhHhr`FTXcOo!ruI?&Q7$k0i0XDNqcM*zo_ic;H}~$#4TneCDk6W%#?xF
z)2xkwI#7IgE4NrCwrTfGSj({*iA}d}!b+|uY6gE3mfC1rt+_Cqbr-dXZj{;Bwr6cQ
zPRfT_Y;A1iVyUc$l(VsAd8x6L$4jnH3$KN^X>CU+82GS}G+%9xi<Ht9dXFJ|n_*3d
zaSz#^7D=UThS<XL|1}E|Yox|*Q=~Swt+n5P9%7wTzkVLPw$w|F=RJJ*MWQf|_xwPS
zyGJjfm$mIe(f>~&k>H8O|L?y@aeb@daMhH^aBX-h!gXRI8T6kg#`RJokL!kyWIwc)
zZ0bHyt@R#ZlXp<<{w1WBgs`~&oG9QrGl8xXR?xLWP_zB*wN(69MXC%p`n+uf0TvY6
z;_7gk^dB9Gu6IWUSG|}V_zt1kra|Ps+h+=BLLyzy3?uvXr-)(uMM5di$q3~YX|^n<
z&mIx<Sv#7r1Fa^4Em}yhod?OiX8}b$tdZRK7m{i97czaahBU3Vk>%21)F06))I<H9
zh#}=ZSr*+Un_WXl(`O`ocFG`^KW-rVv})pi+Lda%2hwMCPb(FBmXJ}G0IKLQh}`>)
zC%TXZa(rngwR_Ayy4ux|=3+at%-%*en{p`#pA4#fafx_7cPCBL3#y$qjy})XN<DEX
zihTW7O8g&1q){&6tSGv7B-8t9y1MvN#jNIb9Ql>#ru3wCOqxP1NXR6*L&2oat)@@{
zbI88uO41u#DXf(@N&mirYzo>^Z-q~w>%nT$NY~KkD{5lX-xk|g(XnQV=*n|)v%{Y#
zCT5XQVgMP{Hupr^MFbx1Oqv~QsI6i9NRxAcEb~qg!^mkA#NBhG={uIfs;(u?zUDhD
zEr32J^dyF_i4<bz<6yAbTs}>XJK^Pp8?ZYOZRV*bE;M)V<W2PX#4NhbttU&(cKW=e
zInXi_(cMsyv+k)BdSeEC{{0SxxVX6)^P0%UX&$*3ROCgJKs;RzlBKl=hAOFzxcNr=
z!<XV>@6xp>jzY<6evqzwpwC^}kR|(&K2P){n*uj-Q>Y=wPyC3^Z#C8a-it!~5Jk10
z&(OCXGmKoC@is)mn!i2=1=+~0(}?J@8wva(x(;YVMqPdA>WVQ|YO@h<PpM6dc&a_#
zi9T;zNu=4$x9vD3*(_O1jvJgQh}nOTvq9TP<JOi?=_=BADyWwIm$12G>1*<N)qMXK
zKP5r*iA*;=Bf3>x>2q%}0iG`<B9~m!dp{vdbF;m3v*T0G$VRb~^jrzK`MV#rdm5%B
z7zu6>YJVy9oZf|M|NI{@x4%l95egf+|5L;Su5qQ7_06D)+=m2~W>UwN)Y0d6GNOq1
zhcpA4yWO#nK3{AeUgl*Hc9SPrX8ul}vtCl|-IL_<-H&wb=0IM?Y$Ltuf8^!A*Bssd
z(bGt^M@QFj^C{j@yXiU@<Gj?yQBC>-3FLlA1a;lo0nOif9krvSm2Rus7Si1KjWj!4
z$o*1Z((F1;8b?=h|6>lh?8*^y>q}H?$Dr0~v*HFhxH5&VEyt5lQgaYJu93@6Pl#fy
zD_v_J5w({<HeP<@xIsam4=O0oSvN@IR6w7%MG$rsOV{o1$^H0Dy6)OVwJ+9CKgrVQ
zv$fN8YE%AXGVL>q;=1HWq%p0@XlE)Jxi;S=$KH`%Gm=`6zLshWgXmhGPQiuR5Ko^x
zVwhA(pNp=N%kYkby1Jd3H{>?y3!CqNdrI;+-)bcXE8CILxDIrkIEv_ojH9+Pvk2C4
zIq6fo5%|s~BHc2HG#Lx%>QhfdJACQ0X)~b)%qGk2$%O4Sm_lrNPoHI&qeyM${YMR$
z?n(Az7c_r=6|KnS!fn)nX}gGSb_5Y=hZ2#yl{Eg%4@}qF^w}<iz?-)cs-`uO8Y0NS
zive`qBPW~or|CLp0$pFG5Zl!O#I~!1+~?}aa{V+J-TzfDsUp7lx%~Y{GOe6Ot=!W@
zpW7{@F5O#4Fy#;A_-F-zQ~k)j=Q+{@pC$X47-}mUN42Ue<amHP>3e=6o)Hz~<$s?E
z)oCzs?pVgt{qMP%0CVOMAZ-Kz?4k(J)`32+sHN+Y=J(a=#T3MVbRzPaOQ?3sh-j`2
z_1u^RgvwY?n#co$T7zYW)aIw3N$(v;*H;$OA8UTIr0xQb)#mFUih4}~U77vlKzo@S
z_)n(KE}N)*FYO3Ce<$fH7ZOG1WkkKJd0cbB^iXCqQ%@QhrX(_(1u6-yZ8l&sYm<Eo
zb5WbiVHDOqH_R_>&YtCQovy(=)W*7dDz#hgP2F<-Fac)tAqV<Ga=f$oK6vyLb7UK~
zm|A%#kAl#?Bk+}%L|XV4S?;N(&&4XbE)kLC4ny;IFOX%QmDHGpMzR!tB>wjKnE2Yn
zT1yEq|2a9BK8Q?j&Z8LRcpzmqy}MAPe-0&6H+Slxq-wO$rq@8S`4~XgrHkl`sJTK8
zvYKan!&^{q{eeMDW+Pfp`sjXy^*7OV4kk4+%nzD_9*f6MX5)@YBRcIDa_Q|)u*n#o
zWi~ZA6xP1J)Z&iK_rcJUMBNE19K09KkmC`DsN3yN2~=St{oerklKS~zfhAo(mTu_{
zZ!e&4H@2UMKG}3>Ek1AVG7=MOvTnb}+65*(i`Rjqm#;6by=M(XMW3E+(Jy_k&jige
z(IU(wo9!hx+M@|F7n;^E-rs?dy&47$cSwpwF)_9qPlH0|I^1(I2T|cC;P;4n;SrKK
zi9+Jg@y?>RZSXC-h-N8azTYaE(+-Uf6sdm)Tac*u5p3RxG(RD%&!S(FLAF;sc_B<)
z#HYq0crUS$UN%R>#r}|j#Lo|)FCxXIOM$y8zU=^9hWO=MO#Uex)sc13w-`e6+jf34
zz}E9;N9c#C#W0*9>uW`T>z-}E)m1c7f)GxL&MyUHg6OBefw?2<7>#e}t*F8K|GI!L
z{|$_4(*`uDn?4)O>^>EbpX>+oPJCHCoOWQH-jkN+vR+g1-jnt2TZXT-PcDmY>if6^
zG52foL*Mq_F%xkNuqv-1kb%F2<2D(Tm4xe$w`k-ae1u*PqtoqCJJHn_flZfSO)OpT
zX9w7<3?2=lP1n9h?cYna(C-$-xuSJWqQXre_Yiex0Ev(2KNc3pMYd8DXGJ*@a9$Gi
z{0&jZikgGBUJ*5iA17*#KVH<_fCN!<3lc>Xw(Pp7xg{wgYD#mr@;>wo85;9(wXCFA
zTDpb6VY`1WBhpS;=nCogJ6fY3e@LH+YwyMG0QT*S2S)m1hcyUh*p^IaMr^dMKuBY@
z&PVJ&t7#7UYlIkdGlF*6esg6Seg~ATW4c4^P|+7ox>*0lwg0j1a6Uqw3jNR9Xlg%W
zVhyf#q5_(#>=uQ)gU4RfFdveyXl*07kBH9iMPx@sD{0s~E^__{<Dc||=wdy9Cq;2I
z<eU?w5-?IUpdNmsL@VTQ6Dz7O2mXpk9}den(LX=I>kU!C-vHbcIbVcjs;K59nvy3{
z&wxq3=xa9o7KqBb0bV8Qc>sW?B006?nP`^)%SKV{4UB)d*_9pO@V#i-ZfN(3vs%K`
zQS9^)4xPl_8YsQR1CZm9`iQ4{fX!Dd%0c+2#C6BOc3S+BmK34lkXgW85_j1Slgr}V
zt%xF4yg42bri$HY>6j)S*@U{g;`^Ub6p9aZfYMqbo=o4_BXI`d%fz8k=-evt_P3Cp
zi^nU`Uyb6!o6s0L+u-$J+iN>o0KnDu$v#*fu+70BCH1u(Tny49wgv5AdD3?KKd=n3
zO`V7$+BPE<p3d8LT?x))+Xue@e%<zW%!}y#V<T;=9s^K^<<IfCW4|BJ?oP$qWf1WH
zrvSV%q@xoL!Pl5maritw?g_3dIMM&zi!E|yqWxWR{se3H{e`&p?A-;|KKk~+_jjSS
z;-G&ps!E3x&^R)DNhP{_)V7I;cg$kzI+#xSKrf7$uk27UUseKFOKabvdhI`>aNST)
z4~os53ekvo*)$|fqzSUTy>OZ+oB9i?ZpZ{`*=^Z6Th!&qPCCHZec53iM461=d|19=
zo(_e{Zf@{bH1#l-ISQ5+l|Ls?`{R{q4e)$e?KmBhr@D2_|K0oNMCo-1?15-rF5Hxe
zS|MjBeI)weg-D)=Bzo|diMIIRn=TjeAt*e>|J{H$FY)Sd5c-H4=}qJ-?i`EasJPEp
z#N{VG)fQv{Vof88K&!aTRnQz0cbE+^SS+S#!U^%Xv1s^7aoPcd86zGah2oO9nAR`Z
z;$5DIB1e2S6)y6`lU@OrFaDGVT%p*XmPAG3Swo>L7Dv%S;emMETEtW${-HmVkHm%o
zSUwj2ODTaTV(ScA(U*&lt^#R=_$ICHs>CN6(U_;==_8@67DucGutr=`3YuE+ggyY&
zi65T;x1H^~U8vh_JLmxl2iqv>pgp$NXCeB1wiz!FjH7KC&2~a<69g#3Y-3gco@0A2
z22!r=dMgK-eA`tea9Cj5F#_5m+q*PDzi+#P)^rbSC(>f&p{?^DC?45XECasOHaY`E
znQhAj=!A0Hxu+pj+8*czT$Sw~aUgqUn|KdWwe8RJ;(c!W$9hoL+UAk_7q&lnL3(LB
z>;uj0>uulbK=aym%MUPpYwJog?FQRRhatVQozj4&y|>*)Z-tMxT^<71WP6|5``Om4
zfaMq4+3V24-IBMlXs^8_VI7ovC2!~ruupQ8W(-b}HOL!Foh4V-q7nNgCqm)RRnqlu
zn*Sb@Os3cLA<4}`01r$2j>6Pkvhg3d_mr$r!qiI=KMZv~l9Jvid?o3$Wb>0;iH3>4
zqzmOe0wuo|B8nhM3biFz(zgV4$0hE#m!%;Rs~e&?C9z&Y^r4cVtq3hl^7}p!#=kR?
z+e3kfkks}E{+uMS4cH<jv4;>vv_v%m!1Iy_nzdh)jL*R>5F;6o3qY)7$YKO@MH1Wt
zZ1IvsX8});=-R*}Nm4*zUzN0oM0=AZ+c33~UYG2@3BV0W5rZghN~U*0VNH|tya#Q%
z<WUMtZ%f`95qE}Uv<yX-Wam)W+>u0|hRHq2_2Hn&mRLLyVXh=62PS!v&}@WOAgTHh
zCWVsUbpYI#*m$BSmc&q&>!GB@6BH$qpZ6iAQc1)owCu4Yi>B!1R!L<BXeuNcdlXfY
zPCa1rR5JBGTvSW`_dS#~65k>eb&?`_KfaJW+kh^4C6Ulnw_fs{2f}_M@%x10t)%E7
z>KY{u2LX5|S+E&oA0*R8!}6o#uPktWlEkk>cYT&b2E)WoYW=kivF(<Qe+r<3^l$76
zNcTvKze8;Mq@O3FFCC?04e;wM?JNb*MfySu8dqr$3(Eu2$@Adikkoh|F5IN<vw?G$
zp7<F`4{7-on0QOY6X3x|>RtwiN2Gldp*$)*J_6MK(l*xiFb$AS^#ndhy7oFc_?UG4
z0N5OtPTv9G3F-VCxDS#3>kY&yscjUbFsW`lJcUamX+|F*m7Ij-S?RHOL>MVOLW_nd
zslOb`3(|n6puQ*#rkCX<>CJm!xh$RZ5N@wXoljYTkCW<X5t1OS$%aj$)PEcBSEX*=
zz+aPYqRCgGbc`3IBI&V{kRC|?8UfrxX~7!=^GJH}7u1zXGtWZ#L|PmIc$suArD7|j
zGezjGO6j#qm^_tspm**wX}eSeY9|vV@p%4r%We*X)<KrN5<%^eDW)NqeX{;^LpjQx
z(d)xm);S%XTx9Pif%|~$Kgui|lx5P|{;+J$Dk$A$@)UUTk|jt1@Rt2dD{EibnnLu`
z5!vQsnE1&iQ2N7P*6|u}_he6o+T!`kmVG}Lrg^f#G{wo61<ycig|c6U08u2nxEE5f
zY-2oV9?16egk_1$sVk&MvY~?!?_*h}1kw}PaWmYP%iOi#u8<9-^<I@Ml(H31WpkH8
zs+RemgGr6dv>v!x+2A>_wARTQ(&6cqY=;=!^|H7~u)UQz-v+Qjb~_5D?`6)*5yb~t
zWgY51$wHT-g`Z`&uq=~)l^vvYxE)hc4;S{#>`c@-Fnbyyonvm0GLqT<1|FiBWk12g
zd1k8@$SyL!UO@lGSefw7Aid0V&W9Mw{K>#?95Z7JXyO^q@1RU%q9|>j#7v%!x@$};
z$~7l5fi!bXVd7@O<OXw%l8vd%5BX50F{>#Tbc>k~48OOTS{hI@nfk7%%VIwDhQGT^
zHKj%GG1fPyV3WgeKS9i8#?g(K&wTEOqJY^zv;QLIj~Yn#8I>)1?*U`~8sR@=+SAPL
z5wjKhg3?lE$XtZ>gvlQRzh%tE=Wtlbr0j!K#jt0<Qq9C=Q|B|IX#1j$v7ZR#3x=^$
z*1MkBorEY}Gojc-lr}Jaw9;;5a>l^s1M}4$h>wh%?!eDXZw}HI=HHQs!j6p|fHv)B
z7gFBSfqnN3f$m{DhQV?lD@#D($aec40B1Hk6OLTi(%s;6WshzG?f^SE$%^t2yTTc!
zZfyL&z`L_O=r-|Sf4+voiw%oIFy5@<3X1D&+;B8Ig^eDGB9&EQ<4>B#j$H@$x7mU}
z(CiGh+jV%#Vqd=o=N)!11Bdt63p1h2X0MG!19REMv?|PF8@=iMSIF*n2C#@7PRoE|
z*7zs5AFz)O!Tlrl*I)ok+0ES`m9d3>AT4L*^xRjneJW5_#a8bD{242Z1a~$29gTs{
z*{TY(rI!5=iU?n@*^>Zx$=Xo=*0Wuvpm@!0sG$7kTXs@4!f#;n$3y#`9Y&i#AJ~p-
z;IN7Hqg>1<wnZ1PePu^uTTyDq<xtYvo|~Np$$?9y+j1}GMV-Ho3&}v?#7#biMmTf1
z8xhQYZr)3HaOK412=pKqeHidV+-u4rSPyd__d#^$b{z$c7dOieT5oPn3jF$VdP-y-
z;WpDM#Ge~>8EgUE>myJe<7U!yA()$=1L*|!nZ}!wT#Gz}eTuWth<2Kr<Bqy8Zh0A`
zaPDg-L=nL`(j@IHr{qvXTDfQC&_;1H=sCE+wWW=%i`=fc;J(BaKSObuyS)O9Dd1j*
zg62M#cnc=QoKG_F54pw&6eV2$8Sq=m&F_vtA9H=NBA1qPUOj=U;Qpk!UKN+W9k{2Q
zZVEW7xgtt#*Kk&^;n3D`>w3WE1t*S#RL{Mo5$ZK3O9TEbS2+$v1D8k(j(6OeY83A|
z-8eL@i3=q6pST0Rp%GuW1(!hjmFsg3@ZEf!E6D8m%~_z{!}nI9ZZFT!nC-~lNrZ_L
z-^O|zKo{Pr7^eIA!q>1lz;B|r(m{T1C6sRbPP)qu^CmmgdGO~ZLh|HG<^bo-C#qrM
z!~g3Kz<GYjR46a-88lqQ@RQTgU6=R}TJ*&7<*N|I75>3y#2e2~w?$n7A9Ih^A4&Wk
z%KKgA8JfQ)^JBf?={j#q6NMZ6Lk$o&dCyU>OyiTUpe~)C@B*#B&97Mo(hUB{3`lqQ
z@wCjl%j;;*Er%aU4s&_uG$`|VvkE2!d{z%QD&pIi@EzReW9HHO?*U&<X~c*8_vNrD
z<=3}@^q3#C2dyaM>uBj(&iACPn@Zk^rZQFhkY^~K@k16tS<TOOK%me0oiR|>@(oB9
zN?-8u$>@@oynHIi>iH9=QTLi}pm+IO{$?#4HSiUaX#V-0w>m-mz(45)hfRE!T9AI?
z@6Zh43!nc8h_C!BEtI>3@Hi;#1$!;RKPvR4<%yrLk?w>5q3ddx1PZU|)qYIaIT%p{
z3qx@FL3%>iOjFF0!daT_pAsy#C{7FIu`scQ2~*oc3>WNZoe&{xrKQtZ!65^lB86Q^
zV2ct8Xjyw+IKaWv1z|TW3S)%7euT*-!Q38xV}<@PXzvx_mk0Qo;ss3(iUc7t0LrUE
zyPmMTCa|=OyDqGvJaLN9$_rAeRj7+Z*Q5!<0wLZK;-|pjZDEH9ac2s~#gMWDFF#0k
zg$p+!-4i-E!hMb)egV>4;SPQG`9k6$zzc+J_fc0QJlGBCzA(5Ya1R8A-q#NWr<Z8i
zBVk}~n3M{Y=Ye}7Sk(^^ewlD}KDa9c+oOoBQW%p3o2NoIy1kwWfjZ!8gdb=}>$%_)
z4(YR?I}NtI^1(|{xXY)~9MeM{>VlX&<x^-6*-IY#1ckTU?G2PZ@<WGE_{wY30XQOG
zsRfyze3g}UIQ->THHacWzV9f43Y52_MR1UOECq8+{-HO3!SW5AARU)4NPwph`Jwj!
zoRSyQbU#eKhIWm^<u)|RXUey~hDnzE0FAGA<gxSs+?6}fD0@%7u`h~j`MD1$a^x}p
zdIWWoT7M&4o;=5hB40lKB8mdJ4vA}Np?n4<Eg#EgvQR#ek1R*yE96b5Q9P3$wMAsr
z^6q8SKk`BUpm;9-Oc~u;d2~98I{Dl!GI+xOw$neOrR^O{0qO8d0s6P&tORH}<=(*_
zg!F$e|3tLk@9Kbx&argAbSZHHU)N967u{Ya!KS+lt*w68M?0-Ox|SiXo?%FtOMC77
zifiv_qruSUQ$9%hdQlMl0*3?Dzj`?A2h?3f0|xe}0skN`H)wv`z8GwSw?qpV1BN(!
zf$7km_8=OznzE!L(r@89@;TjzqaFpr^rwT!x=TkFc7@|Hu|5dv7t>Jae{;Hx&nxr;
z;qvc$sc>K~S~nK491wLkLpmxdSHUbuG<hl*Pl|q63uTyS8-0W4L}RlU8Uyj)g<)J_
zx1VXCVbqnmngQ1bn58tGILLIQci$nVvn%S{7)Q#M9A>_!oS8f0O|uaXCfO4acrp_y
zW9Y@W?|{;qX-Nkxe3+OPVDV*sIs&JD45NhP&v^AhT@YivM3cB<jHC#NU}htA!f~d7
zmhmA>84W9^nAtlJ+G!^C4C+Fe-zK9jj8XJM5zahXgecB1-z|aP2xd+zke+2kVif0?
zojf`sl4<M*>L?~`6O_@+FO&d0&rF^V<ppMo)fO%;GBbD-F-(vPy5|yec@2P<8UMFX
z#$rZ@;tF%W3`HFCc0GcLXCz(-JAv7;A2B5|wKUyJVz$0Rag|we8OrO-Cwjb67$+PI
z!X(*9he2*K=_8>`Wr|0@LmHEMgzmp|=G6=My~Vr;1Tcen*AFf-nFF+gmBn00Mz7yt
z)ZKx<%k;H{@*eY@0yNo-`yfa;OxsMD<TK}qw1BbC2WKI3z!^mm^W!jB-e-okM^Vfa
zwS(mY=1<D!JY=w<#Qj&om|nvDBW76!DodH<|Inq6nR$H?%o8T4EojP^)AZe!Gp!zj
zrh<u}3}7X5VHTQJ#k8lq=Tqh_Z5%#hmXY6Trhqc5HOwSh&^>2Vn}Mrkz8iqLI%Ya8
zmtHW#9@84^C9~WMO?$=sbqx;dnJ1LQf6XX{BZ@c7Ljxjx%lt|E_YKT_+AwHjEVWR+
zV|*#e`H`7WhN6k-kchf3jLR)>e`UOA&(e;)T?^%Iww~T(d)X1>!I8azLxxf(*7y~5
zRu?vX8Swkrz*^Y2vP+Jm@&KE348=iqKXu6=c0@KLH+JtbkRE3BG-Y;YN7KvFgH3r1
zxF^fe9puHfTnEXAji)4pFRP=_j<EkEBl=*r)nXLKS*ttzo?r`y0dUgFuEEBFG=wer
z7pAA!CoFpQH0$>kHleJb1Wg!Q8;`nhb`0gl&ahw4Af^a*Ya%SqvLZ9!=h(HIVG_xj
zY@m!{*M^{oW*1I{@;o~u7Pt%SieZp0vf-=28N*JZg~lb;`t$+%@-oX%f+Lo#V$rlK
zY>Qw-8pk@-!!(}lO%sm<cF+Le6WIf)03@-B)2O@3b`FI5YwU<~kdoOz+Gf7ax>bTZ
zg-zarx*Ke8Cj^tqy3*EW8asR>$kN#tIO!<8#l~5&y@usWB#oaL?1DTzRheu@$^~Yz
zqx!+&9X5p`yvug~1Il~s-?cEwX4{T~ryO>wBe-+fTpEz`Sk2EM&1W}vKvBS6nFNzU
zmd^xr5qpvjGu&rYTTm3U<$Dpu1NNWkG;@E*ex|RogzZa9?MLk9ortuQtuny<WA;xU
za6e&_V?k5K-f0JXIlG0nzAIS2EwHR)Z56PrVjrD_^pw3u$+%~%#RAJ}cFA=FQ^N*b
zfTQQ^*7m5YWjoQjp^mN1q37=fYoVTf$*y?`{44f9nvK-6!*Em*3#H1rP`+WOUPEYa
z+04bTY+$d@2w~6tK)cvJ+=3mjJj$JagEskb)6-Dr&uw{(B7k$EaW0U1AO}2%YiNF}
zbNRzj7tFO?&f@ty&S_|e>;!k0UWq3;4_fVoaQ7FYIK?%rKyjM$TL^q8_bWY(VO&)>
z9ENi(=t)1rCDKWZb6ov?6p>sT+RKdMeC#1bb8dga<UAMC0byU@{EkAp$o+B%{$jX?
zG)uK!;x^M3(q&Gc3~ekoky4RYxV`;h8plOcqZ8w~becINa4TqTlgK5mLQF~A#xp3c
za{tQ*{2KSDKZ;~dP49#2Tv`|`Q@EL9P~71Dh(j<pxn=aKPUW`019ckL^(R=Sf5$b&
z0C<awp@H=_*Y7-RGPoaUw9Vv}di3t6xBf<{(|cTQIB?lq)*yU$Ib6_eM3&2a_b<?S
z++4~?<a0-83$}oJM`tt&xmQF|#7%4s%lq7z6<{vrE-nYl1Ma{CC?9e|52FnwoRk{&
zh_hTpT`9-igymx{?`KF)xGJk1qOaimr-7}KbE0vgiu;R_j!(JZ(EvW<W?leIHTP^1
zOlmk+x(}aop|oFD%ej|As^bo~g~<ypsT*)FIV+tJdc~QV0I26elhCBsT=`Zg-*9Dg
z-r_BnNt;>?+#sHgpfqx8euefOx2`ov-*Zm=A${Qb%h72cxp{g-(ZtzNPWlt)HyB;=
zncJBT{1>jB2BcrPmA}Eg9beP|mb>};e&Dp{M}<M@z;~h*`X2tWH!Sz^tM-F)AMY{^
zEROuwU=bb>C%#}f`pcRB;RH-wcpF+9@8>(v$ro4NeJSb=@ZY<_;X&R#4%~<M6-R-0
z<HykM)L~v34V*hKOoF8c-~9qiym^;J@Z`fM{e?PT{?Z`;j_`-0pghVC7>8i|_}SpJ
zO8xmJ9O{q;@aqns2;^5zho>MumQINr;~TmIAIx)WAsy#cL2z+`pKSomN&XNm8$$Sx
zl&(9)mkoj6)BKNgjx?0_m;fn^H+dq$aDFAt;?M9$x+01Q{v*w9&ho8jiEBN_`_6+l
zl3(2iz$kt}6r^bWD2|(8;X97jFc<j0XkK%X|G5}a41Z=cq)YtxQNUm30|r7F%U`9n
z-W7h{D?}K_hps|Q@%+hOz?s0GIss)O-zEaeBz{#qEU)sto}%uWm7hZk-(<ee0+3$k
zJJRwlh1bw}@&><#($6<}xBuWNl`jrQOlkb4cPP^NMMvQG7Jn`j(rx~|2`)1D@3z9l
z9extsfp_^`lzYF&xA_D8l+DkjXEBHO901E)KEVJ-dAv2ArULnV)dfUTz`O2;!$Mvm
zhq8!Y-UP&bUNr*BV!kRD#RGoYNd)tdkLm%M68;dSiXQPZY28rD&wPzWJmzmM1?~yo
z;DWj`+)t=0=bQclu7ZC>JHD0t&Wo_D;vKBWT}hwvqke+TGyc$d*i`cwtx;LS=TXk&
zIsf|{u+{Q0+tH>v-bfqAFZh%{A-&|MQ}K!)<bxL0^TBjv<uz~j0q{5c%<iy!%Rd&N
zY~b~@x7^5w^o9F({6^X+de3i5qv!7fKZ>T*ANfCi2cn7pF9nsK`0pq=^qDu(CdC(i
zD5c`R@{*rWXD2)+7rO;77xa_8aQrir4njChp!Nt0&qLZP^r5WzKB31+_;nOG+RSzm
z{OQ1$v(WH2s9l8>OC@;z4hZjmg?Lbiqh#1&;Uvwc+=bRO-gpSxXzRgSs9gyYA7RsE
z#Oo`JqHokssBA*#`3t3f00aoHwxc*EO!yNnf(4#VPahW+Ek_512<tN-of2&6$mMBa
zhXR3y3mq|}V4F-(MM4`PWIl(BvqCLx37-?9%E28e1kjoxN;p6VpreHe^o^Vsmj8}G
zF9_?7!SbRYJ^{8Ep_a}BT@sR3fb6pHt_OmN71&b%ToKNlMG+@7-auWvpnD5P3Bu*~
zptdFo?=L`160$21_f_FpC2Xz<!zQDHlZAI?*jyL39!Fh@Fmo*Y-Vod@kZuasX@@9P
zSP+UR(uCMv=$Uk3GVSi&613yt{<g4^@^l%(_XEJ0DR|JZo+aq=Kz&C@p=sP*PB75p
zgv}d|<iUFD_v=AcAgpx;b)hh}4{$}o6WTPsFSsuSpjc?}0Bw07jHU<fp|GMqJd_CI
z_Q2$kFq01NmkKo{aP(LRqZ{yv(4z)`G9ek8lG1YF93?j^gr?rWRSI|dgR@HbCjewm
z1&vjT(4Glz>8N$J@ITsLt`QW6LHb;H#iFiO_}~xHI$_ymC|?L)eE@tZ94v+Mm5{v_
zfO<h)1m$aC3cWqw2n{+od@CHKySYJVNqM72Vcjo)zY_-RMcsR0%=d`!gK%OKP1rsP
zItr>u*hD+RpM+mMQ2AL1qa4o{VOtCI)>q*ij*&_2<Q|lM+ASYR8xZz#!$;KZm4E&S
z<vw|M4O}?NkJ9(zBp<N`0B8Ai+J1DA_w5Dh{qof#fpeArOUJJc$VEeG!G2KQ55Mn_
z9+IzWfneO^1qa~%u-x@8aJ$RjQr^i!?llJpPx)IqEaW9uM1#g#{*rzL;3J<)yKBDk
zOgfN$M1E~2SdPla(vE|lJV^<-zdZIKlmYS#>fb<l@83ZdBoFqm!P9U|UctkCu>6<)
z_zsWDM=pWQ33&r$2u{j_X<8E^ze>jsPRRwDZJd_>^BPj9{L3m7VRC=U0*A|EKcV$!
z<caqIh>(BHhQqV+leADfCvQuezLE0G2~bAKCn~@aEqB=gN7nQ5m1ab9K|UHOeCb7b
z4y98s%RO2{ij~{E0qGTa$ZL?s$+Htt#LE{^GAcp7X&Yz~<%?+>GD%)@4s2KD=0_mA
zCLd3S6qDuJ0Kl)y`#2zq6#3<YsJkIw*aseN%0o^9kZP4b>Wwl@Ui1SH>2mf8DsRbS
zX+CvZo<*m^GUVyBY|E6_P%<S;?m7#WcjV!;^?g@9pbjSY<hxuDMYepH3Zdo58<(NT
zmDjl=-aL644!j{5)$=nf3*@tsP**5F;e!Si$*r|?e)Yb*W;1Mx<sZ^O`as@m0*XiS
z`^OP?sr*$bOdrb^EJRT*f5@S(Le6zWU8Q^kjbzW{zn(!%)p9>NBwiz*PcO4NxpfO1
zzL1ZI1Ma2#))ch!wS51t@b^aEHwu<-<(sWzVcH-+M&neYT+l&!C+|bk-H-BfwB^?%
zpEw^hpX60Kn0%J!is0#sd@0SmzRGV&5QUv03+Z3!ZpC-_b(7RyF_NBb2gN{|*6&f+
zwE=vuBGnFneTrK&TX0l_(fH(~(B#slm9wI$4x}!MxOb@BuUJ7R%Ul)b(jgsC{7VVy
zgNh-ofj^`uodz~HMV}K0^sr)VAzZjCPCo{~L$R?JOgt5ywCUuf@ZJZUx1z^Ju=prm
zpMvD87%%|E5yk0RwEn2#wiEqm#ZNId3^x9XWLjbcD9(g{G*IEt86gHK*7!p@rr1FX
z(_lr#P5_T9j?=JlLNSXn;wKgTXwxY~k<tU)rxae4kUy<(rc-jE3UN6C4O3(-1w33)
zcpS|=qu4+vKq3^g@Kso)XBCBgP<c)<kP?}Z3hRB4o>wG10^0=zOM~u3Mbkt$ysY?@
zHZ@`uEhwfdisO-Bi&G4t<zl>|=rSx56ti!DJ5kZp3Ux^eb5BHZRpG4z?wVr5HgF~@
z>OKQ-T@mpCEY=jo4+7lZP#hwMHx<Ka-Ic0vqRp5z#f<*Irz?hrqqwEWrLF7Ribl#l
zXDFt81};-E+YC=xiZ=A3yrbwq>A$;*S+hZQPch^S$g&k)oe)!w;!!`~aus2eLdsJ-
zh(KMwRk6wn(*i}jJ-)R<#eJG<6)A$KFCQr8t^oH##WK3DN)&w};P8>+x(Lcr#n^eU
ze5~*>pxNb$n!gZQh2n5?s#Z~O6J#$GA%CF}FBRiR`AShqiMM)1tNUPit#G*p&Nm8c
z1RX?qt9bYdHVul&RbXpWxOPG--YLFrL=^88UOE6jC{|IT<)dQhR!B{XcC@Pcq;TAT
z;<MuYk0`z<ZcqmPs{%7iJQd0_rvTWkRPBZ*d*wOWGIvmlD08|;Sxn#SUgb3FYH0T<
z-%UZ`sC0Bj)0~v8Y!SY*aul6FaZ%3M2&JpCC!M}KpnTB>qz9Gtx#+z^%ADmeaZ~Q1
z2mY{f;3(9&D~GH{lRT7Fbb!oLxqT`^^HMUDV(?amNI>SJ6#BxSuX0c~D`<`=7p{W#
zsM3{=2Kgy}YzZ2FWvdiO0ZIotof4?*&ww;Y`D#AmKBnwN2kL{B{}V$xu1p96+X>|>
zniQT?UZdGuh%#y-0H>4{qY!qO^4fH8hAaOKgmgw}r0GJ0(%gzxV`r5u^+23cUZe3f
zQhELeq$uTgG_Q$PmR&*9&MQ;eB8m&jDH9=GRPL~Wrx@kwYD95Ksic?UW#xqKfX6EL
zcZ76BIdc)Bk5lfT96`LY3yo6=%Gxl%6P0=NPEAsFMy|^$y{bIF4{X<zofn}<R!*m{
z^18AQ?E$AKM<+qLp){UAOgEJ$4+5X6RM4_9P5G_}y_T*V{S|(1Dc^>mg}0S<y#dHj
z_6vdgOy%^cP-ZFZQ=z=09OwzoyUKl90PZPW8N_7GR@%^1F-N&?J0i_h?*0kdJY_#8
zDD#ya7QjV;@;BOvE>z}G=AcNKP3I1ZmCO!A@jyB4JlGy8CyhmfCCdGDF8Gmh2_3O1
zRc`GD<zwad*J1fYd4!ITmMK?sM=<5e*Yx_Vuqu%U#fwBaoff}OmAX(ke5U+lfwEe8
z?I$2=l$#qs^IYjl@9kRUlv7aFDR)wa@`dsx9j1G!{G}`4uawsIkm{8~?}O#Fvd0(T
z8k8yYGHz6+&>-?o=}EozUTJke*dLVEEILi_QRzdc+M1L{en#A%l(Po`_*of$0Hj}(
zX@8*gUzI~bQP`;_P`5d#oc{;h9@S1dF|$|I>o)xEQ!V`poTKV{7qB>~a%oBFteRa6
zoQul%2b#2BbxnY!t19m~SPrP-t!H3!P}NY4*bb{AePH9RIuQfBhbna=V)9hAegqd@
zswfMZ?XBv14@w`^q->b@s{WadD2}Kuo<wm}6-NWBpXxHDLHt#$Kl}!${@e+NfvQb4
za2TYTOy^LJsUFc0+hEn8B6|NFSN%&<)f1}gbSC+v>L}eUA*$V!Mn9$6-T@}3RZjx|
z3{{QW3$`%T;~}sNSNYP}xHGC!>YxbK+_CU`R(10TOwOrJQa?qi4!;9Sl&az&JVdKx
zw0=6T+DW@57gXnb=|^i9RTVVq#i;rS&|Xsg><+|b6-W1DtSa*`++R`cnGMo7Rf~xT
zE&f|fNh*UBbyrogPvE|$x=goxvZ`(|r0c3rG#yM)jqVPX8>*yzpuVXZNNJZ;)oKGg
zq^m;lTL!E2mg-9vblYuJC=H$&s`oXJGF9!u0L)Syq-D)rRm2!b_f&Sy=!9&Qb0<WR
zqgqYBI?GjEq5Mal>dF{c7OJLRfZrmO7p*q#tDb%jWwEMt8vq`tBBsIeq3ZQWbXSQg
zxC7wUN2)%(P?oB0(Kgs))y4&g^oi;VZI+d(cEkcvu4=3VTZQUQ6}T%^z3FsGmC8u(
zgQu$12f_VJrJyatYSla1G_FyV(^vRhb>lgjRI7St2E0yH@esuel>+;S(w8c26#%cS
zs>hT^uUGwEkDwY=Q8ozXooYR0%igPgdk*CXl^b=?M^$udur;YV(H!KHYETATd{(We
ze9sqE6>YD4RgEHmow~I@Lffs5Z;v{Ab*t;Bb5Q?P0^A;TUz(9Ps!!75)k$rAK|cp{
zR<Bux!bSa&W~KYp4?ZG9SG6n_!5mO8tcLQSI%*DzLuwy-8M~{eOhhmq>J1B^^i*HW
zMq|9xGTQ#~R-dUw;iEo4CvAMyEjz;Gh&qrS%A;!WG;sQ<_u~kN)L*^UT8%P5-IY@O
z$JATCqJx9g{aGlFt35-3IH8{Q6w*nxB?d)^x|0efr_?<txp-P#MEQ$Qb)RE!7^dD{
zi73L=#~YzMqyD`SjX0+cD1c?8Ix!nklzPKBm_(}wQ+DmVy0Q!XXyt;sf%a}Lsv~J*
zB}RSbR|I@Xy}=Krm(^;TwZy7l(=dBQea0Sjaq6=yig>llV{j*^r;bNVSJhE;#QU0h
z^i_0lvRZ2e=XLe$wUAQOxf0afP`hn_-<#?`e*|@^`p!9e{?gQHI!%6C?JtM>4E39X
z;LcPZ{~6p_>b!C&@2JnyWcseU_&V6`sq1JPEL(kQ68z?<N7ITtSN%gKEc4X)ub|9V
zj|_r~BK5-g0Nht^&xJ{`+DaRm57eK!1O8Ag`iq{w61CfZ@bpMMMhrx$dN_}UK34Cg
zrR@`Sy#jvA)K$??maCU<0!@`Vo8H$?)l*V{d#3*FD(b4$Q`@7iMtw69+|Sj;bSKoR
z=hOL@I`vLUio8%iZig;;sTO^L@|D_g0X$gi)wTHR1k%@PpJK%QMxDAG+;7z*XnOTd
zEvLNadvz8a3izPb{sK=Q)irc(wMjk97RpcRNSda6R&St<t1s%Lk#O-<EeVHYuPI7|
zCkKt?ADHaXXvqCu%~g6s@6+sZhtkoi+2{m^P8$CzR61({dZKXAWLZ$TUvr)krLLM0
zcc46=iJ_l1xM|)~!t$`@%UOi)u5qP_n1|*l9V+nDy!-`zy);v20^qHAKx=3p&Cn>A
z_-e9}06(HB-vakXHREU|<fpNg=fNgWBYZ&9f;2-L06eBqyh9PJIrbQJ$2B%|3!KoD
z(yHvF<_-08h$f5XW2ZFT==i~DO)Bk0glbmRpu55}IW#|s(1gZ-^Q<Pi7|L^+*7UB3
z)T}!U>L`r^y)dISe^_Z3{k&#A{j}$TW;Hzy7d8K*!<LsdJ~Ri3)#OuB=Za?A6wt(J
z=05^HUK4a1$^^~J97u_pz!%_7(&&}~a8+}M&h1>&crQkgtg%R7a$Pf|dDX3HIT|df
z8ZI40nr3cmI-ZrT@$UhLw=_1pP~6rm{{Wf{O&RU}WonjvhtRS#_OuyyM{}?h+H_YF
zHvr0enpJd;C0FzHDx^G(Ap)I{ulep7x}-oOZ4aqXbG#EwiZop_Kz3g<e>MCSYc9Ef
z?1AReA2_feeW-af35XI+Pgl@9(yY_N#S=}Y3c-|Vo-G5uTyxh5WrgMkcK|Cjx9R+M
zmF9>VfTx-}f1@$aG-K%8PPK+@g0faKcM`g!PV<FURWCF@(CG0}6WIkOuQa3R*D>{)
zzT@eS7QEKj%hBF9njHs#c&l-wm1=`#kOeLpHI;NU@117SHIRPP45!R_lcwh~H0G10
zs{?SKHJkrN-4{*$&*1*5`A`jRJFS>rK)bbDDZ^>69Y^1*gSOQSG-;3axPZF7+7C1m
zTb;EPbAWfzE~aeTe(hjdpu1|T^Wpb^cI^h>4{Cp+h91@iP$s}#duTb79@>B|F!9uW
zq@RX(Y5$~=&0A{-h0;g6v>(WPwFygMc|<Fr@#d(u>m2y?)7E67NBy;H>A?xGYM0Z_
zSD;q^2Vx7-RyspErj4QHXR!9aM<6|}eM}SA6WTYl8+}r{@gAfQEklX>Q(6m66;EsJ
z6H$a}JJTVFFm1;);KH?znczI5jiY^s2<;6OlxMZKXlLY{Hip*Fky<NHhYq5&Eyp6Z
zXzdBguAkRlPDXJ-+iD^37qwGq${3^VrvUzv7Qb!8!=YXM1Z|4d-uNDMSG27?5q6yR
zXL~d|UVD2LiUe(l3?_-%>OSz4q|NUNva8y#bx>Z@rc(|!S=-V&7oM(byN-ZOigpq0
zvE9(N2|_DwYAY#$pQ_#VE4b6N@x39XYgHS-eM>vJE%3Lsowosyp$)i+x=igU8cVXY
zodeO{JKFGxV7aSZW(N=Vv>RyGBwH(QPEcvJv`EU;E}cP(?>ub*tpW12|4|yXK-=Re
zfQ4GI3CbdEQviVXwR0~)D%Q>lN9RA#me6MSL+#WGSe9r{(`);YHmDIMrP>Zh;Qp~T
z{w{)fqFp);CS}@{wCi53Z8IJw722*Z!C9%bb`j(GtJ1#q1>&jJYbZ=>w2iZ2`dmAk
zev4A8?N^4F>a<^1pm?FJZH2m*+M~l!ywZ+|MYHR*ZKc4y*1n~w<{Ry8CCJ`tF9gCx
zgElc94jZ+W_mJLcL;Vobdu=Wqko}--KcAkzkJ=J9ur+BvjDy2Z+C}uYJU(law}bnO
zw$&HlziQKJ&|W)Tdj-C{-MRwGmf7nL(=Qhsbaz<P?a>*m!0pv}({ym3P9;K}qiz5t
z7oBu<#faWnSMU^^F1p_L0pG84AB`xiuDYboFg>6fMyD$d>XJ4Ae@Itb4^ubYX6p6B
zx=#bpLU&y;{pkS@-O652dg_X3n&PGVcnxrGor*|(bkQ`t`|85z?Q%r-<_wCXx+Qe9
z+)uZJLxldiWi-G9=raBVF3_r*Oy|^sbYZkkIHohuKohLHNQZ@v>joT#bVBDy?LDdc
z`xx*cx{>S9&!=>Cfsjt?4vm8ps;i`YZI~`|Fp6;9(-gqZ=uGsaM(DcJPTN^sKiY&m
zr#rSAWRbc~pHUa3vp)ZfXrgtAGZ5){-Fez=y`T%)g1)$@bFK$>jBZ0a6qj_vvVgy=
zD?ADpvAU2Jkgn+79!1Z_>5}RIkJqIofjdE`kb@;r_lp|1B;Bnh6jybHbe{5>PMZus
ziY~bvfE&6{s}o|osf(d0eX7onmWpXQb`)Yu*Ll&){FbiAX#j8Qe&fKMp>y~Lelv9|
zD7TuWyYVl$@91h;gY>TM;&n*(bcc%o&(<x;2X&5aQwuaOSGStdU3t3Uba&<JKGUFA
zpi{S{o2F1Ve;RCxba#8f=Duz+%@B%p;*XFX=&sXm!5-?o=*3y0Yn_3(AL%M;5pSt(
z%_K;VbshhL!za4nDUix^>qX!$*NKdPSLk|Dj-*n@&V{2Y-9{RMpX!)S;C!ZIr&Ip3
zTGuigY&E(E;{bfFJ4(mSYIP^*utS}W^@a38C%i%@ywqh!Ac|MISwDcgUT3dHC%o2;
zr61<L(HS?Pc&qC|``-<^reG9}y7?DC{Z99!8!X@J0_lA22i<sDihtBi>qvjJp-Gpf
zgy|>UhY*DSS=V<gY`*CHg5dY7&hZl@JN=}4;NGpDY>O!D^*gQr;GjR~1(QAc_m_a%
zt6#SUCj0b)D@+{q!)f8>q;D4q_s;sidxOPA|B+6C?AI6M!M&^gYd5f159rg+p**O!
zqe1tOe&7TYZu);{9(Y*a?-JPD_5VzSiHCjw9cA;>&!+7jFMY&H6yEynGtf^ydS4oJ
zef8H@!SaZHl_R>+U*GZ`A`H-PZ;84<{Z+byg7kCgXyh^d0XpUuY}Hqvg7&z6Z#}qA
z=-bl`by7d?A4CzN_u;{PO5c*^C#UrXDFYFz4{8O!Vfyo1fD6};rwPIteGZ-PjnGe_
zmF8Lfa!NFv)5j)2iqtF1VG^a+Q0t@hPpR4G^@mr&!v($d0%dqF>NnC%H%5Oe3W!Vk
zlhkdO^?%alLaaWV{$|z{{l4z7jMHaoQ5Ub@N!j@X{qHgqiTVKoiX{C&8t1O+qiIw7
zn*I!BXp{ASeSxRz`cd?2z!ZH4dyw7G4}1&DoBA{>jZmrjs9uOIO`mKAB3-{Q7+=sW
z{g0GFzpXb?J|aUuzz=Q8)GwzWQ)TJnX?ymLzRe=g+|^%S4VHWQpU<Mm)}N#tOOAfz
zPT+F&S8`yPr~lFpEz8%Z(vNxz^cm@>E7Tt;rTj~gzB~T*p!B}Jk(TSl`Wf>P%me++
zw@^ORPo%|8iGI;#a6i&>0SK*B-);~rAM1Zt!Tl5c^D5Mp=^JmLDA#`uL7)}-|0ow#
zslQLVMOFIGYT%yg=OiJtXZpswsH@h0a-sEKjs6%-P@e1e(@$Y)^|AC<ZtC<?egNWy
zUi%!TFZEyPgzqbTr&@5=>nr7;d96Q9w|t}i#RN3%oqq2Kz~Ae;yTS5<eqb!>KI-jh
zi?B)W;{mcydI{wkKI<2Bf%HWmjFZ|{=~un1C%zIpL-%|%X177M29mvD)?Uy!7#1Id
zw8zj$3%|XF3zVDLXSnAAyrbdeO9bO&@ScojI~x|$@d_8ic{(+`-{5}}b*_f8;c$Pz
zP&fj?95g(52<ecafrfQAL)TF-u^u)A^#ZrM;S9Z&JPfNSmF8&(IRZ~!1}+=!y$yp;
zqwp~_<pSty=spLYju_g{faOsGdk~VJVF%4P{SCSnAPX?m(n~GSu;?O8f($M1qi2p8
zwmPFO*szpFrsIY}dPYuI4I3!ue$p_G#_kZq9Xb<p%5XLdrl$?#L!k^c%%M4Tn4woo
zcnUWxq+iLMF+2%{Nra(z7HG~IR?)2RoWZ^lMWi8#zR4)VG}=>)HdO6JFy{?jCGdN}
zkTnI$i-zeUSjHHvk`8F-CBti)(OfnRPXSx3;Z0B2Trr&O4q%)i_&3B9Z}|KVOcD$w
zKLU_wn7bPIB*S-Pa@FupJOI}WcHbkkWW$?HsJm_$dlrBcLzF9|8wLv<{l94#M6b_O
z!=>41OPT=(=3$d=7#0rFTZV}z@g3YYWCtRO41=jNfSHE!03fmqdELN$$M7R9tL_?v
zDd?Gd2Co2+W*aI;L78K4rY)#k!<A)F<{4yXVUlmyOeal>42RrN+&3JfRCKXnvw(OX
z7*vHc|9ogDcZT~CL&ERSJ~B+9g+-|$g6^xwhT*hidt#8$w4u!KbUR`yHxyD%sKSs%
z$FV96-TJ~)mEq^%z&$nGzk#}EhJr#+R~woJp{~Y|M@OHY8#cSZq}H%K2Dm!I+1Yd&
z<%J<G4FSJ2wDU*!uMF!?15s~iqP_ChhEQ5rzcGvup?GWP{VQl13|}q4HyX~LM=<XU
z3C9rOd&6eh2l!y{m;thnh7J4Ssmb7&h`LXP>LE~mHYCzr{lzeg8u8Vj#}dLSwKIB{
zA?`MYjzoLyjce#gse{qc0Ec^w4s;S@udz4@e)k!dGGKEwcA{1|88=m+OPr0*=%*|$
z#yPalv)?${57E0C?P%3~z&MP4qjb>Nm$H(FjN^8}#LcLsV<?A>D{p|z>TX<3FA@*q
z!oOkTX?*h@?!Amfo=|!lnaAMvG3H!>dtal^DM&|*-n8C5YP?zk6F*~<8$9_Nr}cuT
z0OMX7W&@4go!}zKc(?)5F=OCGz=MrTY5jKGI3^T;6UM_IVRF)H%%rC(#Q4`+6sL@~
zJ>cTBao!i$gc`Lc5L1}ZV>LX58*^z%e8$*jG^7aQ(l%)5S)-J8$Icm>h%M5{F99IR
zSWWBuXk%RhOwJnz&jjZMqcI%Hi^i(9u#7SOyA$oaWVF`5fz4%O?m}qejDIgc5pSGK
z`S=9m{vy;R8uMsKN-{2&qqu5pq%OH;ET9Q`ve9xK#dV|Aj3`o!EhnJ3VKkT##Z6;>
zI-;Cvd`5|)G~>=Z;L?rnD2IH@7~clcZKIPFf7(czVZ201w@hQ<Y)DzgF?5LTjxmEy
zyxcV!1JM`vj9u0tv}~hsE9!ELv*>VduJNl0?(>Y(wxKTHc$yZm1;)fXz!e(3=<g;L
z89NRJ^?l<fUjT}YyJ;Qvz<AIFbq|d>&3`nb#5mg%E*=?c+5lK;+?5WR$Ht&P&|goC
zg>=lk%xL-pe#?!Rq2j?aifA=iX>7d{CRN4;njt?mPMQJSGvoYu08|@qu7OlzG}2=7
zxzU?aceTcSEQ&hgSUPg}!Z<XW&cD1gYH5S$m2vqSL{V=X`3#8H#<dpo&>Lg1FZ{kW
zKFk4WgK-WGAB{%i_h`jCV=BE!-WvnyVD|^(#9MIq(RjE5E}D$pa^T{VakU=QpN;=K
z0LvHSWG|R}HSVWPA3M{cE%g4|ZJI<sfVVe&cmekgra(QUJ*FTffO}1&X@arOv~?B`
zj;2vb@Z@CrkPr9HrX7nQxtMaJ5$}GJcLx-%rbF|AJ7B7$1oJ^tC9Q`Jna1Y<;AV1r
z0P4f0ryo)0Zu)W!byg3P6D>+TO_B7b_A>Q(0<E{H;Uy#=Q$TmP@HKTC2K*6I3jNH@
z-&7QcRs@)wwU7c$;dJgS$aL~K0zGE3i33@%DVGun$4weKW^uxlM8~F2nvT-$XNak)
z8;Vn=4JW{I+G;XN01P#autRr;nc}B`E!;Fv3H%w;=K{EhFm0fHp0lQ9Yf+pt{Yu-z
zktUBjpoubd*Mlb7bZaSGoHy0bFnht|>4A7Jn(`e{#F)Os18~XIH4pI1rqfb5iZvag
zHOm!~)sfOxai(9f7MI4GTxb&~!PLSHHi;%_8*nF?4v8RLH7)rJlWV57bX+^x^lB<R
zT{jJgKolva*Z%@{!_<z3w3{YjGMb%gT08`P(@ZYWs7p7M9fEYr6ukjtw@qo@u*@)B
zw$g!{Ow+B?5VK50l=8o0%Gd+$yQY@E!StT##UMnHZ3>{jsgYxfwMTd5ni{`@i#(IW
z7j^ljyet3;OnE=Rq|mh4113eL{?zRIrj7Iy#bVP5+Rb}l+W9*?JT#3?2cX2XJ(Avk
zk4)7k;J(z9{1c?drnFax>4~YDwnoZKGCB@fZn_u=M1^TQ4O^9_pE6NbWg7e^il-(U
z`Wf#t)1F`8qS`c)hl?81tLMNyHziV1wAOUw8gO-{oju{`g~<|vx|b#&2l~<WE7O%S
zbYi`!gdU*Rrm{f@_>IYtX7+DQD=1mtU^-!oqS3UAehvK2)b=Mt_}=tj4*Y&Fh0?Ku
zkEYx7<Gv=-W7@p=V)Fh25{9RhaA;@FX$=p%&GqL2w>J-?Q*aLEKrH<|Bug~bwG!|+
znmezDk(0SS?JPN)U(n%07qj~<(Cs%D)x(FY`PCE99WZN6Fga-MOv$K2=1NKdx|s|A
zgvnv^+$nJEZjPb9mgr%gLz56sb1Pp+Ugo{Dru8;!>1QcE=8wO_pRaj@mFB8P%)9ac
zJZc`@1}*h7KcSJ;-<-~aG{F2T9bgMI&$Ga9kogk*p!Jx!Yz%P0=AY6*bKI=1fu|GZ
z7T)l5(p<6@MTj~1e=s>^o)QB1X|s0^6rtw%bhs?c++7DixOvk?%7LFT_o9(1!kkQx
z<5{zkmRIM@&OJaAX%65KQ<T}^Z&*f~XKe=Xym|OBC@+|w*`c2<nz#2x6fx#abTH$R
zc`=PUm(4%XTP@b?w;g0x%(Y(tk2B|uf)sB)<BKA}Z26hRJ&<UAPm9DP^F&%bTs2!M
zO?b`xyg!O$vxpXH*UcC1Ai@;0!&<nwVGf{~_Dyp>9eGYQPm6;4G;=8nmUMG?XRzEd
zm*vC#ZFBwsC^O8DOW`onyek-FS!Q2q?j7@U%$>fM-Zi^khRr?m<3k|LHvcO_Wscdc
z3H_C8ey|O7dFGWKgO+u%e)5FH1M~ZPpnhm(Pr|Uod}J#8JvPq_hleNT7o8AbnYn5Q
z>dMV+-veD?PJawsrFk8t$*RnH8jGHqf1?wD&&(6)rC4nqCWgBj^X*bd&&|n;5ofLW
z-g-!N=Hqmf?}hn`wJ-25%_mC1{mOiqeuhwQZs7*yYxCAcAbn$=M=6W9=8j3|m<IDl
z%D*(4d!Iq^&YYn}Fz?Ot=!dKy%(k?B_|Y7$LS2)22Q834ndf<+_-xK}g~Kmqhodn0
zYMx53T{}zJdOE$m+j55TuJ)Eb^cOZ9EN8UvyT`KP6M%ay4s;@YpXJBfXquxX#{;1`
zS;ntKowH>>odR&Nbfv}QeoF?;_*^ZoY3XvnQr;Dw4qEze1?M4)UJeg#mId2T9JZ{X
zr`X-nHi+KW9u}(vY@QZ(I)LJ3**+JNw`I@-(D+z_szB;%`MovRj#$3m1W!jTHS~AJ
z{49rQ(co_}?tn>vWk0Qe0xhZw;104#{s+J@%Y52-4z>*1fV$(B|2D$?3CoBwcsObK
za{%RQLo6d`ls;uyLVa=C@|6C3RH(&`2B9#^*^MZ|E%sI*&RE*4fn|i{-{s&wYgsW4
z#W_n~ItdkN89WQoM_Jm@k4B;`$%~*oZ#nZGoEI!ZmmuDYmLFWvhcOn15^!F!oTCl*
zWtS~23Q!qq`RfkEE0&y6RK{73rJ#tnxYR+JU^!2}>P)m`&|mFIvRrxwPggB1J0qs+
zmJ=-iPqDb%LfAJf1Am3dO-p7vOj0dpX)T*(vGW+UQg5xlg{lloOGkv1Y4NN;-(^|W
zOoDXBQd|PVyOu4qD|OG(gMJ2<ZE0$Y7;-GeO!&#Q)Nm;BEE$v|$hT~<M??jdE>18h
zwB#j&y2zrWBU<+@fer|z*pgBTzynL?{fO_O<*b#S{Sr$nnvXoPY^5busiia)rjIRS
z=(zS13p)?3Ewg-@4rRIJkM{snSkBS(ywcK!7EDzZ5$)PPwfsqkPoG&9(bj9VCEyy0
z8p{((=svexuRu|2nPWgvXNjS@7na7ow0-{4(w=^6^~$12Kv8emG#8#;Tjn$(m^YSJ
z^b-94IJ)k*E~_q{rB-U1qu%`Oz4s!`mZh&&R<_hq8(O_qTG=woe(WK#mm;zh5CK7^
zBFIn>8M2f;WDl8&AWPow>96y-_nz-L=U#r#ea=1S+=sE%EUIICu=*rbQI4;6u))~G
z>RqKU=Hco^1fN{}f*k8Kwfe0va89q@M%VmjR)@+liP_avCbS-{j#~zObE~t+gSTb8
zd5lhmc8m|G2*#e_vKPzkz%bCE*^%)xxt&f7;~OB(j2(SIxG<ihcfTtmz8mJdF<j`(
ze3WsLiv8Rf6X{?%#@PE6#yl9k5m4yK;8a4G7h?&%1-u!hHZatOv54w=d>Ns;pLlHX
z0zby}ztHq&DExMQ$Fw@y!om}b5qd!cGxog%DJL1bzC$a7arG^bQ;d~#fDUE6A;aXu
z7)c>$g)@HLjIjvD5enLzVQ46462;g@{&+OQCjzY)#;7k0Jj)27jCw5N6$Z4PW2Dmi
zJdWXf31jh$zpYG6FoCgz9JTWds|Q+%jE8@LCy6mc-x#^T=%Q47GNX_TO<`Q1oJlI<
zI=wE^7)#qBCY=%UEjlw8<rIOs$e3;fxx}!goJl5QNezTuW;lESDOrqKiX~<<hMooP
z3M2AOiqz#Wf`u?Km(gB}A3`2uADyoA8CS4e3$8NaD5Y?Xao7!WDqwu+3eG~tt8|*b
z&Io=FDvB8UucCE>@!ko@E@r$;MLs2rM|20Slu@YzDPu^BF~OUR?ic{d8Es04u3+5w
zog#IW43|+1RxzR}4OPu3Uj-Gn7;Y5Tz0J5x4_pmHS_NP&qln&ibqq&JL)9~uQs}mU
z;j#v#k+Fk3{wBtTI*?|@S}HhfVVtKdR4b$34-0#TQAHVrHpcsOfvTP1f1h@~4#vP;
zsPAN~KMqY@j5qLBSkTRQyd9*6(Mm_MUd8}bO!P7QsbH#~(Im!l-(}oC0Tlxbly~A0
zV=UyOHN?=;>3EoN-iX!+<IGc#GRknIm*zdjpLDRh&**<1#*8sesX(j`7{(>gJI-jP
z)8Yi9vKokoj6dH+YmyP^4lz@VW$v(hnvqT+f*FR?0W7nO@88BO9x=|@LH!(~g|-`8
z=I*lq*fGnpq0pXLl?oLOOc`BIb!Mhe)X|0c*%ZcHnJ;?-;AUlRphAYD%$eUI&7HZ0
z;v~nIv+Dr#V1`iA(UVzAA!9G*V{5_U&CFQ@dwrO-boldSw$pjokEy38+@Bd31hWH}
zk@WqoK;~adAti`;n0~UynJ>|~<pk4%p3q=sp9035WLg*F-=!=FVFn%o&nf1Qmq0?9
zkDZ2!Fy`S4K!h{%UIrq9$(sNolKI<q08TR(Qkdop^Fyjwieet2-71=SjP{8brcX8i
zXPH6dGsiMFM!}eK%r8FxOB{2@w;=IM+iziZ0@K?{tA3uDO2s;f%nT}bNn);}@6%jh
zezhMel9>&8ASukuI2e=4RCj?hjk(DgV$zv&`2b`vKcvv$MP`ZxESH!`^drq=nmWLF
znfclnG-WZ5-9u+K^F#}TU12)YA0~(Szc4E-&1GJiL^F@6q|e#qGh1n6yUOIw!0u~I
zKAnyWn5@Sjt&sT`U3a+7e7F~4ikMMU?{$M|eg!PWOd(Z2moRha5iey9&?l42nCq#m
z;3l({(i`Q>7B}dtU>;_oRmtq$K%PexlS6N_YGy0daNlCa)0Zx8GskG1YnUT{Kuj$&
zU@gY#m>;*IRnOe3#q1lHy>uFBWE#b2H8FeXI#x6Dp&avVVb;=()>h_Y<l^69YHp&{
z##}uI(#}k|4AQ~$dVMjTzfNY?D8zIzcN75F%Pjc-D*BkA|A6!}cZ{I(E|Ww4zyMQ7
zXM;he?p=%xF_|n(W|;Zq0<erQuY80B8fC8i3axw0yXOJ8&s;{A(8ic&KZ1o1nE$1^
zjdA87x>z^C?70XQ>qDj>5b7tHYhJ_P6!Qp$Tc(+lo53@~d;`wWf>~x?5Lg~D*HZ*)
zj#=pdX|}A>-5_?X6}MrNJxk$;IXSR$UV&+jtePhw+li%n1b{QE;c;}ju#Rj8iz{oq
z5X6lYwGsM`T3PeyCF9Og(&_jZ>-F`J=E1sH4umI5L#JaeRxoW_-Yk4@6b~M&y9uWG
zvLqML>Bmx4LYhBI%!DxkEC+H-16lnNj0Le2<bfY&?WA4n1gkOwGJ{#YelYDMtIY+b
zg|Mu4A3^UaR`M>$4rN6qWA<UJ;Wq#bXQe(3o(R_PEXE>PPwAoJG;1&#<P0lP0$dcU
zkDjV%*5gk@b_{EPc9^rQT~y%_%c{tM73Wx|N})cEwS(TG@vI4Zh)!TVM&Z@-tVPx;
zG!t2G(CIjdRYqyI3#=5{Q<7Q3k3(+?D{TTKm6c18ku=s0e`rc)xjqX`8LS;8;JnC^
zQqukstFatXGFfYW2H-L)j$$ZTEGA{vvRM*Ju3lkP(R6cI3n{do%lcy-dAoV6Dk?(B
zXI&7(;H#`PpP};_YuVS3R=|2hw?hh9;p7xvXDz2=Ofl=1CUlmt{-XOurK~S~&{@X1
zzy;tYYrY-e<*XycXjQO$scNN?Wq1*sRje3);Hp{w<N|PuwWX6PrEatK((_xx+U5fl
zwJbJ0)O9Q^75vw;>dAj>U~RsPu|`&180>Chh0^J?nKj%36)mjz51^uzH9%qTJFFr)
zvbM2$n3z&KYyJ#`b+D9FX4c6vmtw4owf0Snb+a~oPw&4TmJdz4mvw*~$39labs+j#
zCHc^FmleGfhym8T7hv!p>m3S{4zc22#@H}xmQLd%ELI-oG|GBu9>_h`tKpDxpEb^h
ziZNE~atM3Cdg2FY7-zLF24I49Xd74_vW`3nVb)33@^<h{u|6eVdYUyh1u-+M6ZB)7
zWvzJ~dLOY$DAG5_I!pH}Y}xaj0I*}f7!H6vyZ9k2bYQ=K1}Yrck9$I|6MGS5E1cQV
z003Orrzrj8%4Skb-Hol<3UZYFdonuRt?X-0LiRCs(cfr#u-DV8-IKlIS#)}_n{q(B
z*+rBY@L^}tAJ&(x`Uk|1y@i6}{_G`mEDm6QaSG}K**miV4`NH|(K^na>w+;S*fqUa
zu3+|8p#Yp@N4jAVLfCQBXq{qPEn9#HWqZ)35XLrc1qo-fCV+@wU!f3PB>SUtP=A`;
z90v=}u#Z251&U%nh{RYlJ8?V4V%Y9nkhAO=igCrVzhz-8o;?>1^$F}%6#qKUo}`#d
zB3nTL(Ij@?Jd9mn*IJ9gn#_KI5@jju1ypgE%Kq+g*p|lr_!xlc>@{~VnGCk`J7BrU
zj;E<zVz*NnMkYIfzMFZO9l^((ve;GoAvBx4?>R`h!rt{KSaR5*dw|PjZzC5bkNr(6
zMCY?d>4Ck<W_elByvE*Fi@^f+Z7QoRWE)hFcAcHK7?u{XGp}R5H`qsdpsASMLf45)
z*pL4L6{YOVWB|(88!kiBO?Ju+2rXwHs|T)vy@GbFO7`}5L8{opx6oP5zWX$cxy4>e
z-vGVMj?1C<Uk$sGK5SCUUbqi>>)0phs8-KDLNEFT_C5*<G_vd0q1D8G#fY(H_V-lO
z)WR<80%>Ire*kiay^?nMHuf;3wA<MZOJHFKTk!_~o$P_#P}s%x*#djJ*-484=waW$
z!N9tpmwlFekUsX4A;9;uKTCtAyX*+MrZm8IbOU~neUl#JA@&HRK8M+^bzm7`OAKg@
zvR{eEwC}M)HUn^<9YK5k7@N5hEDzZ4(UvsMzTp9d6YOEyLLahcf5aM2vf-xV`I};Q
z{07!(b|r-?XV~L(@S0_J<X{$$*aCV-&ata06=BP{UISvsd7B(od(Q6%VUq*r54tDo
z$nmCY$xfU+CZ_Goail%pg|qM-5Lb?lc1t%-0EP69az2Ry+?{iqUId<2&U+o0g%_uL
z9E0ARP3{om!?BYC=*wA7zLOuPm;zt^9F8*(0UV!hkU-Any$}<``GAgG$2nQMF~bv_
zXXpeJ%&7^-*hx<7*AN!M*+vQSQyj+!U<u{8Q9v_{lX3<&g>$S@`prdfw$Y(Gl2iH~
zTBkX`W&n7Gqk9vGD9+V?uZ(bRlAjU7$>_w`Sx!(Q0I{5kw;}Bu=h>Seah#F8Fgu=8
z=m9AS9CklUJI{G>73@vq_*2nY634LuV;4AOmtkQt$KOiNVG1YY4DhL(Vo%6U<1D3Z
zE1lE-Hq>Wu4rw9uBIoS}uw3F)qP%rMCTA@@2bVbm^jpv31XA2Ro5Q4h^A*nax1lMA
zbG{GoT+U1Mo6F<aF9j~2lhq1xm2;0Ov#xP^L{?}j;GEV0QOI#j!#ZE*O#Kf+i#W?@
zL%zXz#~v0IbDkxCp@idf5Uo-UOA15FIPW}<&YPUKC_`4xDXasof|E_HO3n<usH-@4
z=tfdC=W~j|+~Pb<o6v2}u6KZ|;jH3PrBp4)>qGF=aaK_1s-E*=H|E>GSw(kf8#(?*
zAgzfL;|6KXoO_hDYvEY8qt(jE|1YL}hhz5u@HWnn45qbn;^_?C!I|FzcqivPeFCwI
z!;1$?H>cD9(LEfI6IP~|a}fHh3;H;!C&AOtG11MHyPUR9p<;mZi!H<qa#lCM?h(%D
zIdqP4PW=0h<9O1_-si+jLE0Fnogys{IG4i#ALrCk(b)v2>N&7H<S-}{I>~tu05ZjC
zBiDAC^W*!_H^WKn0<q3=Yz{)jBhK&Gbr;NW{OPOAw%le4>e+D@(dUiqxyz_@+<~j8
zfEY)v8^!ybxF^Uxa^@Nf0C3@cN>8yX_YaCDyK$#lFm{ytvIJ7xx&9OlImQ(ffp~Dg
zCWpq8+ep!KFDv&|`ptQBt0=hU!|fr*)0f-73Yz@54_}5fe{Rb^Km>5N(MA)<J=BX;
z58|$)%<FM3LyNH!+*V2j1at3Do%2cVQF^vRxF6A!PH{hGgM@OOHiIRM8%SGlIQPO!
zXhm?X;td##<i167I?c5uKjRG7KxGY4+;&H(h~^%qZ7YWBMkl_rTqeyamK#CU1?RY>
zRDl=A{f^E&@m$#eNCNi_CD!6RH<o@7iQII`4<vDap%?rGt{s)-By;O3KvKBxTPdTM
z%8h#lR-|#y(t9DD`(z048QeYeEuo8C))rWCiTj2YR%CKFtpeaO*YGPeWpR5c4VBHk
z&j!mCZt_bQ%i%iEkv5lWB5yR0E87K4`P|>H0e+Rs+k<&t<JO&o=mM_zgkRO)E3KP9
z0p|^F*#zLl+|-Q_R>JM71E7>!b`GsFZsP&SyvhBq8n|-q$Xg&)+?9u5XEk?n0W{p=
zzUYBD+~&s8_w;MH%jgVS%l-ZvjMZ`fqQG%IcL@umf%_|+%^JDFJz#0#ZnIKdcQZGo
z7n)kQ85BZo<+dLH&mHb(ufpCoZk-ac+qr$TupQj`H5lvU_S0U_#XY?XEZy9~bl`fp
zYbgib%l&5sWcP6e<QDaFb;q%;cey+N!Po$IIeE5&+(XR}HpHzzNoU|;?&E&}F~Uv#
z3RaAAS(L`T$Bo^AvHRSY=|=1r_xW<Dc)<OL%pd1Aeh6t3+$YGtc*t#~%En3VzCSSE
zDQ+57L{D?QDL^{I{agybEO&yA0FStjQ5<28+xY{8+46WNC{ts{TapA7_Pmx)AkBeS
zPFY4r-rzyBoOm-|zzS!caXAn!yp1x9x$^e@3JcwMRk4tElvhtz#N2uR$;8+(UQ8BR
z9=uNk0C@89<DuS*C#5o2Z{8evuRc7%w;1!~&BOnqwJz}EEy_jHpJ#s%ix9x8H^G=d
z-b5ov5N{Lh*~fXMHW)j>8*v3bnD;3atDWTaY{ggzZ_|5do#IW|K~pI2>uul+<4scy
zNH}kA3tAC8b|QpD@<bG5KF!NAK;IeO(~V%UM)9J*!DOO&lWmY4!;8&E?^)he%3Z|r
z{xcus9B<+@WXJK6>C6$&dxFC53A}AIne)7}uVS4Nc>xsMPU6L8K+^@@b&4~k^6p&(
zJdHO-MPKQ>FX<kB2Cr)fEEjpp_F(Lim1m|$ER*NfhPAxRd(j87vv?jhAlbYp`arJm
z!rp@2IXvGBP@l{DhrHiB-g9(=BA<7S(qvb8FH$=68c$7U{sLa|VyGzO?V*$9b>43j
zH!0$+TLp51=WE4SG4C5nl9ceQDRitU<qb8US;ni_fx(-+VXFQp=gsG#Rl$=jhiR3(
zAUcay@orH4P&H4+$7F8t=B7bz^VYuz^)<X|`pMVwe1F31>v+}8kXg?wqnBX=FQ0-j
zjl5iXnwog~&x17c?pt|~-NG}xfr+;AuG5X8J3LnkS+wywoS~_mw~8uXJ9xD(z@|>#
z5=wM+@m}OWVK?u=4Y2g^GJb^YUfvV~di!{+VX*Y`q!eem%QMp%XMmSWg^Gi`@z)@1
zh{vA<8Rm^PlMgV$TR~6yDDUTC7;}%uUk`)t^ExT$JjUyh0r-Gd{Sb(8-jTByo8Uc&
zfu@JN-RY1$$@AU^GR2!a2{O&ArhwQCZ-_1w&GP<7!LmoZ^fj389PgiENU`PrCjc_-
z_`jEt4{p!@n7nQW{`V^ZbmZ4j+|-Hxbqa_xKW-T&<H9d00CDBp(;>%=zkVD-kMieR
z(Q@bWb-*3tzpwxbJ@{X3gfLJ3V|!tY7yo+^I=%VJPlCmVf8~3q_vOcygZS}P-_RL2
zkUwOHW)Q!O_TJ<CLsVXKf`7aMDuVgPDIs{0-x>#e2!9Vbqo??9>7h52e@cW|gz=vs
zk1w1*HvokZ{LdFaSR_A>%IQw?8;+xOhW|00y`%U}CJ2k>GvC3?V)#B3q_dvo*B*iF
zSbjSl5zq0x`XMHcKe`<xo?p5L#w73uK8Kj|{JJPCLLz@HIZ{ddJLI8W;PYtjOy+O7
z2%A#)f4v1<Dt`rCGECz~IYMSSe{wqj8GQFxbYA42TZq;reyIqeGp+p6`w(-P|H~YJ
zS^V7;D9Yx4Leb1C{5PpHhyU#X0CV|{cOfm0A4pZa`TQOejJe7WS_adu@k=OHSHS<U
z2eJ$KL%Yzr&VS(tuoUrMPlTo${HRI@E9MV<27M*`Zz%Lt%D0}QD$_FlL)!Xp@?DN$
zu$=!P<qs<O0pyNV^4-l~t>S-0btcvPO1gS+i=RRf``diar!iK;5BwFHYWdI8d%lkU
zJ2?jRd_yYqHt=7eWN;(@ge^oj@vl9J&SriPZGJ8M|5zzx-^$OTkl`JEuM_mP@h|-f
z($4pzTuKLjxd^~c{v192UHlwMe0B4`yMwVF{+pCO=;fCj0_o$Aav-Ij|Lxx}?Jj@#
zV~8H$Z~qd;4DxOBF*d}v-w60Hf6EHYWrY82IvtWm`P1K__a4919%AnEbMHg_7=J#M
zYdqjDAm8I5pHGg(B)_Q|WQw0pkN-4(imFa#_)F=CH_I>a<2$Xgrq@7`ouDZUjP?TC
z;}Gc}2&3KAQP7-*mXqLiBv_mUN89lSaS`mi4;x$s!T&y5f|n?=c~lTUsW^ARhkQsm
zCJ0#vxQF1xDF8eL@9zeSm%ud*#9Lr!$4dAJ20dV{ub}JS(homDmj#3Vf>mEaVSwQJ
z3upxje$If^L4v<BA@sPwK!^Ji0#9-Uf(0}00Dn^8aS$vaf~0d8J0<X>%A`=i3sj90
zCdenhAY9N&#bptK!ZP3@1*K1*by`qIzmYS7cid@9h!V(Yn~D}ZPr-p0K_*o;ofSCH
z6B;Y{nf~PG1S?C>iW7v=#uP7DpM%Z>!E^LRKQCCk6`B$SpO9aWB&eZ1^MXK3`OIWN
ze-vb<2$*cZQw5SX*qbJJw-BA_f*=2+pk9Vx|4QI53I^%reMvA#8IerEsRJ<hvS9Fi
z0J8+Vag1dPybT~%1ljii$Pv6E$Il{HFfR=X^8}~ghU|QSoZQu`f=7>_{+i(Zw=tIj
z!O{63g@Pdi^j;TKUxCabfi2ENxc)ELjDJwJpjhCS0HGy<A1LozDySj9q)Z^b452p#
zy9&@M7wn`=W`$tqMM$d@q<so$Rf32Oz*P&XcEPk;f(_(&-4-lr085QP{wc<41zm?=
zQ-eT2Z|g=u>u=y}5<HWImbF>%pa+93f@ijav<g0L0J$TmqRF%gDn5b2cELf~-Z})s
zF|eXjaPJwgbO}6Zv+EZ0(Sz0_@TMj06=WqsXrCbQYjpMt@<IT(D~M0UiVg^Ve;!f>
z1!vxYX+wfeTD)PaVDek6^N8R>y7w_E2wx8TJ%O0QHTMO!v}cY9N_;W)K#)3zv2nqc
zHrO;FI7IvSLqYXhSguJy?OF((60H6cLZ<~L@)BkQ+Y+I0R^UuG@E!^Np|{_hU^``|
zZH4Rlpw>=kJxF)w?1h&SAk9JOO=ZT8!Yh1;aT5M~7A<Gt7sDVf!k%UjS0N)805{=B
ziC{S@oSp|w?!qlgVCXTSU^7}C!ahoxcnVdNF!mD4=0TyiP)ET}AK^3P*7yo{#$pnF
z!r!fQo!4L3KoR!<VfmjJ3>02k1w@c=A6<YrE_APfv=hRhdawiwKc$-hCxxp6(FzfE
z&Y*Ql_z~U42o)~h0EJ<~FK?hTTp02Ioe{$OgJ?wxf1zFKwD2P;r#T~xj)K}K;ifmq
zp^p}}c!MWK7)(_zXN8V?0gM%%RAcO%@KxF+<AiTfz93$>jCSV)p^CiE^TMy!p_M39
zQN%7uI7d;$3&NAO(3C8c&jOGlT$PTwqzcpj0w7Ho#{o;aP_zYBWC&jkA&35=u+|2e
zE(w3Hf>Bw*KlcEbEj&d5iz~v2_h3_wFh2>vTp_<2V)BG;<skXOKPZ=eRp@Pnz1M{M
z>3vxs?EVwN3WcULn08%wnf$&YVd_U9H-!DP>czrg0pKOV<{OJqdQ~c1^*n%O!h8yU
z+!WSO{I6VCTLvpCgzMd)qEdL?ukz?B>+|GP-4>2CLqm;l6YZq6LbnZItP}p=0LFS@
zI3+6^giYJQ*(iM39%D_y;#TNu7TU*RtVLMF0lZbn@CM5r;lS%)X%lA6gMsbBceg@$
zhw$x5kWS(3J!t3>zCh=PZs7}7I+ykcy{HtVSNJm(fAk4=(KgjDED>UT?g|gmOK3p2
zDFZ47h0pv1p+iE>Y3LmmN^WABBf_QM05>WWlDB(L*y;({_l4imRx&2+2tezBusRj3
zapAX<kTM}W_yx#AVd8Sym?nkGgV3B3Zb*jEX`$*YI%kBvPe9tNaC#Q99|`R#+BqlW
zO<;z$qB4qh+KK)yf_i%qd;~mbBIRbZ97TUGhJ{X|amxETi+=gnc@$lskdv$EB1O2}
zL|%E&a8zWRq*6_H(Mw+gcuX`)K7)tIr60sow1}=tdWnL}Al{<wwCVYXp7;@CzM|}E
zwERTdo`)EJ(MIw!14KcAShYZr!$PPC5?!Uh@o~|fVc2^@^fm2P!J^CifjcSsmF|#)
ziu&Rx030TAhyXBL#N%KvLbT&qD2x;}jo~kHTJ!`3RL_V8sA@J!bZ9;nF<SIFeN`n!
zbng;WoE81D6=Sg?`4MP3C+aLjD^3)&42H&w7Ciz<5QUK2c3u=f$J0d77afq2BvR99
z-g-fFVm-tpi~gdBN{Z;|A0Z}HB&2*wnrIcp^wLEO>9w07YO8?kiy}iVOuHnCe;$BL
zk*g50FN<0SpeajqmJTf0A~BuOuZZ?jnlDEbNYV3Lku4=F@<hAnRGlwc>IAh{t)e|M
zz+V$N#{*a(vOfWyLQ(AJkak_9Ca0=Mbok!@iRf?oAs36jrYm<PqBV9<Un;7;3P71C
zJ_qEcD2A$#%0-4M$gB`4sUoXVB)5kZRic4%j8%&kI>MM+qP9p(@V3bMfO0%FqRvOq
zR4Y2&2c9}nmjN@Z7uC})+aP+0qO6Ug=gQD(5^bVmb+hOQ`P?m{iZ39$Rn(b))*X=p
zy@cCDFHnZ7UDQcGs}4~a1(!NSl24$wOT?g4b+_m?-FNB{@vV`-_lh2)V|AbC2xUI|
zMZRwXaaXjo5@Q3RASyi`6xq-@Z%CB96;m4)Z7;wgjEJfapmS98)bAkoM87`<z<tsC
z>9BrG)TV}t2ckd`$hc_P4UA2QlBtmKq39L*txbyN^-}_LO0<Y>uuh92S3t~+XiYW9
ztjLd&jke-mib>dsCpW<~d+{Z2sCN+Wq3D#OIB^7=PU1&H;B*#Go1xc5Y;6X>RqR3s
z4>z$J1$~Z+{hDEgyZBK#)E^VK(p)^mn*-_p>v)P!eFnUjIGOw@Z*e2lqxpz+!C>_j
zr_o;IC-$HqqQ7{6E~y5H-=GjfpxAFC!~}^q8Gt)3PNz873Gx1Ym|Cz{{3-w^#qUup
zBt(260a8whL+SodsQ4OX`NG6czeHDs!o}Wntd0<OZ2@bfSW6GdY4JB?;u-P%ryx5@
z9R3>CDOxP>gU}f96O=GID}L)N6vm2YQ!&GH;tk}$$B9emvUR-p`(|iLfN2;zFWxD_
zToT1E(uyXDKiLZ01#w(8L|c=^1(ftl5uft|Nfqx~1uN3Ta?0PPi~S<Nnjw~Jp!cG<
z|6RzwB(6IQF`43fK>%D9o5sPCCHD9l>a)eKXwZ2@T(A#om?I8Mf|OkG428e*#GJ(t
zoiDDx1;ACY$7!^#S;c+VAgw_BtS5klm_0OI7kB=HR+0FZGKje$mPMjfEcV|3X(i&=
z)sR*y*03?dGO-t(^KOc_Tmi0JT&@D3LVPL=Dk{a%x4}{+PLP77T5O<H%`Nf4=OOI2
zSVxXqjo5mGe!;cko!PLaPP};m5cT4`3LqN9w+bPxQ9L0*XOnoP0KjJPr-QJ!MeKAD
zW3A%QLFjE4Z=y46huB13N~bt-6!0#w8w<<TEq3$)XOH*+RgLtD=h*_#C$6EY!+vqK
z^#;tiD}K2Uhyn2ky^aRO!M89tB)0d5!eOz*1eOu;yA-Aw6))TZ&U<1*E3CLLRz8b4
zjfoekKpu#{i-y8+u~!_(g!q59F#Dmnlp<G?;>&beoDx5*fs|>neH2(`#BbsEheu6p
z`w~oiBv#Q)r8)7&Ikapg5tIqElf3Q(+4hnasxxtr?0yw3M~RUI7AJ{~4ghC~{R<H4
zB00PoEmz4xI*+(XdTHxEDq$~x_3o0V=u~}7(!#))hopzzqMnj}DybmTOA=!StGC2T
z_0T>N9>ueKC2#s-5&R@~9U;_TGMNbyAh{*PoB|~){({gT$!H}2$0al5GM$jv({>ju
z`S2FZJ}G(66Vncn^wTFfPDvJ)L1C!mDLPMtNe=p<GhFhlklue062`{>MoO+PhnUln
zJX+Z^lKm9Uj*=`{idM8FB@{NrNGc-1c~<hw7)Y!nEDtKqNmkv5>^RAnk7I%2B?sso
zl^|J238V9p846$}O5S=Mtt5$-E}&kJ-24MFlO<160NI)%$)}uSs^q~wtWcUHD-As9
z61Q^@njzUwzW+suk>XjGBn|g~$dvpujMildmyV5D5}P)(vL%)A7`r0ba|rMp$;zWp
zm@CPeg{C}7^EybmCNWTjMuEiVC$JPsa`Qp1TP3D2Or}WUK`ECT5>6?E7EAtl1JX()
zoi{L6DoJC&v@%J>F=)CeaiV&Fa*4MX_zFo`6IP~DV$%o}RgwbwT~$lU$-BEHDRhIB
z+mb(~A-YCV@*7C4<e87aQYU$F3M};!>(2#{)*#tC2x*NH4uw6MBx_f~?q<pBe2le7
z)>D42Rq`$+>+eW*)WVoH$yfAYxpv9eO-!^yvYd`Hof6ykK)NIs{{wipq<kMpkHm+Z
z%3eu86-b{Xs}7`J5>0#OUCBc02xJdPY`;YBpycO|&>E6_Wq@tNl0D}jZA4N>g#e?H
z=jhdZPvTe!q4y=*=@mOB=?{d34<sqYkTx#q6JqfuB;n)`J(Rq32V_#>PP^rl<U0Ai
z(~@so0GN?fX`pCUqI-?p{6~^s)}lElDWs}RTWPu)vhAdM8ql(ry3zCJAbpl@pgKzZ
z>3!lPou=w7XQ^>Hh>P^iKcLrD`XOC)aFYt(f!?FibyPg*E*+*)lw;Bn`Xr5qG~o>h
z^OXLVTw^ckp)2&iMZBeliqZ6uI#I~LSIXXr$@ocqJ0R3w`a9LW1V~??w_%{PyA&iy
zdf5Y-j!Ty};4gAQ`dSu*21_^5y@`|3TjczQNFUw<%PA?Mj(G5-dyayHNuzE-QMh!P
zK28)NU3`hI>P1TJC<%62+UJbHXlco>5ECQ)Q2_i|Y0r7cj+K6Y8+y-4H*+wHIBAp}
zSmLEeDchbP-L()3&r6+x0Z5cSMwzN4sg92I7o=WvW>1!eUct;#q<cz1Ql&qVhnprn
zPH#GEy0ps`Vlt$Q&SUVR^m&T=U6OJrRF^3|@H56POJAkUFH8Cp<tnqKMtTukkxr7Y
zmm^&}2few{HI$0WlN$De<V)Wk1@5Z!t6&JbCXKuXD+;80sDistT21#_u1o)<YUd)W
z^d_CBZb%Qj4q&k~k8bmpNPnTfXsL9d2#7MN`UYAzr2$m7RW9{73_ykS7OiEa^cVW0
zS4l_7WviBM4MXdebY3htZ%a1}z|b1$^9wOnE7hmN`a0=Of6TL9dT}`vHAt;He#Bs-
zw40v4CaIjBm1gN-9>larWlMl>l@9k~N$*JO?gG&!eMq6RcIk%=5Yr*$`hcZVdh2Jv
zyQF+NEp$uI7y<8*wyuDoz0zZ!W1@Xh56U6*OTGJ{;jVOcF@z0B*I4P4GbkPM0B}fJ
z{Sk~AmM+c3;E1$q9aM};pQmds_oSHuko(e)9s_<%>emJGK>F!oka4L$Juwr~U@9|v
zDE<3$2%D6?Spz9k(%Ar*HZAqL2>6UNi4x<pQe6TRJ(3=JnPLTVQZGuc*vh!?qGcz`
zoCDroCZT=VK_;MbX-C<k7eSn4Q*=AcRkp7ln%rb@l-WKi`;miAcUkM#Ajf1!7GR<t
zGJy^)Pgx|@wRp++E&zDTED~t&k?l$ci?8fdIDIO~PZoU<gZ{FW^I=7RY}x@r17#b3
zg26$u-j6YMTsHOx5GQ2Ib?6M1ZO(?!ld|rgKtg1hy_o$e+3;z|4wW@7#?LZLR?!Ca
z;j;hGVKPGI_7E~7Wk2l(;I!;>9a?8(lXvNV`$Wl7=#Eje>^SArVr0U4kh8MdLI{nO
z4O89WIawYZlHz2xbU2Hb?e~RE39>-?m7SN(TtF*P7GHx_l5CLf4_%Pi(uSNYQw3wy
zQe;k)^G}t1Ly7G)**1zTrpp%4%^hootmq8z7iFQ-KwOe7UV&DoEa`c)F3T+B$YsfX
zb3!Xy_O=gfx+1%I2tspYQS_qEm8tK6B~NzaKj_Stg~kGYRd$Mg>(^w76qYEE)l<E3
zp{$2anAc@a6jCjcy-3B{H>|Q-{*YZP`*0kjMCSA<CR!?6_a+9*WE<H)+?26XfG?ND
z4?t6ete0X}m9p8>Sf?sk!Anq4Eo-Mr!&|cF?g4&V=0-2Y8kw6BnrdZ7H=$K0`@j)^
zdYRkfP}CrMfvy=e%B*I(%h)7S(kr%Ec54e-EwV+Ft!$O`e+qI(ww8YRZL$b*3EE|^
ze1>)IkV#U}*(n?Q0<A9D8xc_7E&KUJ7}F!WNk621+2t?6a#waS7%T&_g_NNlloit-
zW=Q5#2bN)3j<p@Y5m}A`vPWgX<a*tcS?FweUv~K);KyV)siyIP?6?W7aoIBR-X~=5
zlV9{ure1)RnUp20#k8kn2gxs*mf2iI=Zx$-y7VwBi&_o9BUu(D1LkCZ_rOA1xs2ih
zcJf$0z0>XGJL&m#kjtr{z)?O*yS0;i?huS|mW${+0WR`o_84=O-zV?EO`diM<fy!p
zg)w*etN%duF}WY589n41rZDCyFYLx7yyV*{)9fw(nGP#H@+hiD@Rk2}2dwauf3=Yc
zfc)hf&tNb>{$3RDf%31G03Re@XajOw-t!QM6LJr#tPGY{y2FZ-@-5``hsfK=RXin6
ztwAeP{>5u(g~<(6zaB2nr$YY-d674)h?HNMMCWPwJqj|Mk$2LWG)n#gyd3L-Xt_BI
zgE8{06~LdB*HL&OR&J)7J?G>LDbyb)--<_dLA-oF6(S_af26q2d3owF=uMPwp&JcJ
za>2J4yCAn~h3sVc?jER5k&C{E^{MiHGCNIvk_r*h<q!4(kRk6|3(?k#a_<VzOY-3-
zfXI|jQnvB3+;ue&S#rT3RxewAi*DClk#D2qZjSuD^$?RQ|B?KJJb5XV&*#gJJHe)_
z@-Ov}eNBF&9l{FahkdYyg>ng<j;_l~y}(%{_i6|HhTQWnv`Ve=^^Itj$v>sX;-(xQ
zFvX)L-%1r>74ivZsHl{)*<h)XTYdqeT7K3aEVtyrbcVPsf8`o9)yUiDgQZs9mI_1b
z<hBebte1<%A*DfnIRc%H^1uGUT$<$3BaqoFcYYtO7P<8>eKM(4K1^35@5uL;0@x=1
z^&?ECT|Vzu2<?!k&_SwGZdV9kmwc2Cy4~_gD)H!%|Fjvhd*!{mfa{b0Itg6A{CGde
zUHRQF0UwZm5{{V-%8hC$9Fjjxm3PDPH{Jt$MDA#%(8H+w4T=`rlfO%~A@}8hv~7*a
zSJJ)N2l7AY=QS=bFatOt-$^Nrhw`mdr8X%arr`RNTu&_1@=8yz%*eB-GI>@mmqGL+
z`Nfa1TyyfjzJxGaMJUB|>=f&s1l(S+HJait4vIF4@H#4TXk&I#d`wP{vm%cwCtMUg
zf5UE9g>wpIyD2>AwQy9yT?#AQ6}`WpbxbkuFTgz%3+bKgsjzth#7nWJ7;taJ8*b3#
zqgd1e^}dQUI%xVSKKnN{r??bOpNbDqBvXhsP~n^n^+5_Lxs%5g#k)XGD9$EeELagn
z?$t?!?l$ltiodsF?3BVg8diiV-luBKFvagw?h>x>?m#O-v0@G^k&3IdX`WVm!i7y|
z6f1rPiBi1o0Mnushw(DDE{IVSk%xU&Azuj<v5HglZa$|73c!5h6mL)sOp1cF4<uF5
z?~IA2DUP&4(<Q~LLr|ZoXs6%$WyLf5Av8ykNYS!f#p_gdm8X!Ae^H`nr6^mOV&n_3
z+*E9*EJC?L;sRo=P&m>bs8aC)T^y@YT>c!0YK4r>(zg^nGicpbm?)xFt9blFaMmfx
z{jrwy3I@Ft8x#&yI?$-t(+RyzivFA6Y*GBj51LvPn=>$_I|@k%mZVMbHeIl3R}@n$
zxKj~GuiY-I;xh_Tb}KquA+1MI#08>PvCJ0uKE?bv$nICXVh6;4B8~RtK}FKPfk4GC
zK^PlW6w;OY5rq?FQb!ff(FS)<p&(!SzCuMmq%nnv;=~UW;&8Oa6_pfnm{5GGgP{)<
z)<5_#YEofOp7NAJydJF?#U3$a&nn`~AdeKc=q}uxLNfp{wn{S}V(gSg3Pd<4|Go;d
z9hFUVrgc)@C0Ef|Sw^mti!!kXGToF-FJq!dl{Mc3;I8zb+r!6{hpvKnD34fQ1Kv~F
z_5<wpQl?T+$47Z*5}JIK4O!6Sr&RBRY=7ktm0|`ce`o^<RBqS^n@%X7r&{D-Wx;;P
zKB*j}A7Y4d(-#;!rF@m@21At_$t8$T{+NZCMJm5kf#tOF<4@2TtvvVyU4V>H?xbt3
zXO-W3fy5~X3ZO7vdG%|kPf$v(gEdJROqG!rl+yb!G+7x;wJ2%IX$owoE8WMzlA%2C
zJX)E`h+<6XvNE1-M`bBL_y@vrly_2~H&^+|23Vh`^qPQ_d}Z|+dj75|RkawrrWA8w
z_jTp3RPtA(+_(&^H<UpU7%NsLQI4QQSwVMON|kl=?T~V1__F|1DBCD~SE<|<0)<t|
zKt9x0D_ss?Wo{`y+Kg7M@>!~5s8jByvY>ipbs97@DUYwF=dW40xEa>8DC4O{qfJ@1
z3JTkm!4xg%P<}$G`A+3K8Bo!s-0&49+O3SHm+Fx6n=|MfR<64YmJ#J{3O$S}o2ioX
zp7I0Q?(QpP{SY>$e4V_)2TCm+ea4k8A4AH7awY_D>qBK8?Y)yqdn0(Jl+NTPO)D!Y
z&pD&~oubyW%FHLA;*s*_w?XEVXKc}Ft9tVQRM@G~d(dgGdPweugX)>@A<R*Af%a7=
zRaO<$JFBwaK&Oi;ECEw;Rh=Y<)lIc|8^(@WRo_Kp_U@{|6KEb&Io^SK4^_VhWP7SY
z_Jeq-hRIj-RTV}7@2A>Io3+2{9ZGcvs5&X25U5JIg|Q%2@CA$=SFPCzg(p-642%V<
z7Lr$ZN_8{`hK8!TUjhkJb(04buCh92U@$_pmU7gQs+vStaaz?+*_Sh_z4S7UQZ0NP
zLZelM^qHR+)jwN-KdV~v6y_VN@~4OLoN7D@OB$!Tiz@{S@PRWbQa!Jle-b27Wl0Ah
zNwx7NL|;&?Nd_QUwPFaJX{z<s0}zw0@?oQyp;C~Ti>l|BL(?VIQ{-r8swOE@a#>}+
z78YiyT4@opRsRczrYkB3Ip8^}_+=ouDh*x8%~O@Eg^GMt06o)JRrVnu1*$$uK^3X$
z>9l@Bwfz$G6{{M2tq@wG8jS>^RP_RVucAz~ma469s@7bGigK0fhZw6+9ey38Qnj)c
zq)N4<4ESo5Cmo`1srpqQw^cV>Kx$OK?#8OstN6(<ra>h*4PlL{m#C<{NwwiFG&HL|
zYJ|OaRGB^Gf3~Sy=}p_N8Xw2hI#lb!f$vnc_CbA@YCaVvbgR^P0QRU}_zg?it2#>u
zsXo=?6rt@`x!*<ST~+5C$bf214WtaJ4$=NPqzX1c@2Kh^55|nCX8(2NRj*M1a$FUb
zL&cvHs;$?7c&M6~#d1%o?!5v{Q>rCj0XVI?K|Aq`DuxOSW>r4hq2iHhhQ4Dmr<!E}
zV6V>o3dBJ@bQB65)$x0<Ku+o{bVbuyePu5u>Y`pwXG2#t#~(7?)b=MZ!J}%^%do=g
zu8x*N=rQ%G&1ib4tMh^PRzIRhoR2y?3_xGCH`QwRsXw3^Lx1(3{tz0VexE|;$JMP*
zL+=T-g5Jr&>djw+oK(k7L0E|TRX4Owsn64@g{zY(^bn!;J_su!)rk}mK5bRMk_Uxn
z)TM=JMydHe5E`wvE<-Cueai^MS+)30AY#?Y5s-FH{fal{8>c?G6u1<1(tBV@Reww2
z<}~$YipQs`8$2<Vp=Q`Y*hTg65Uj-|byF^Ind$?1V7aV*jlMOMrM5P_1DdT~N0%+G
zsDo=^X^wgct!1wISO-}1)T{c@%2)sXH>6!vU*SO7HFYz^rwi0v7jzb?%V_Jrt`4X8
zXOa5BMrgXBp1cUtiq-RIcP~+2-UKP7YTaINmZ`s?8o!(BYAgMj%hi3~L1=|KjogMx
zwO1xcmHNHcprTr>ZUpd_T6_w#zpc)B789*e$56FGt$HyRvg_1sS{Pcd{)~e34eBBK
zSvIOaoWfX>I_LmMv$|*}a4l*t+9q4ol`~L(NBt?!3iWO3`!3MbuKqg*gB|J@DGbx8
zo~2)DmwF%Nkh;~DL@4Z0e>(%xtKLMFAARaqOVH|9uX`WX-&Lo&13sY6{T_fp^*su)
z4ypeXp*5^dX$9wqy21-Aqw4=rz4ATv^4pYuxUW7yapo~~5EqCC>VYu~j;p_<K*of+
zfr`Q&s$ZeoZ<A{Lr$sy*>PwMenN>^3-G8JuJ&VcAsehw`s=a2G_9+L=4k}`E)NCIB
zank&!6D-aeN80>cG>iWSVXm6RNTOI5xM_BTgXgFwg}(IUuKD~w;5nw*y9EdjP0G7a
z;i-9>4q#rIMsjhzHUCk7(?@e>Cy1{mwhjyIr}>)pB7aTY=a_Ghrj*j~$2IN_u<3;6
z*%g>sux4pII8SPBM?*u1=2LR)t*12IkE1tKvx3Sy!Zh3I3=yvR9|gZ6G+U?yDN?hG
z+~3ohILeNl(KNgU^P@D+DlrzV86}4|M)QFjLeFWQJOR!)&3t-a$7>R3>rc>pOtH=L
znvpTEBx;_sf!-v|?I*!`!K&Fo(UD|L@nP_!Xl~MpB31K#G4N@c=FiYd*L)%bYlf!f
zF)YGG&4&{(?UF`AcM&o*uhPn1*1Wg`oLQPLYalyY^Ixi9x}rJoF6_<GJmCqJTutXF
z#_}{gx(1f7xe@@=u4=3u*8#kyng2c%7HA&Pi@s1}Lt*mkntlq(6lorP0Wmi;aX~P@
zSQEP)_!3PM<ts}yLv$^_Ofy7B_?w!<UT~IcJ|LI8LbK2rtx8S8ap0;nfyoe7t=ZiL
zeYZ3pE(PGWCc^qTcxp8Lk3(;*CU6q6>ojRA!CJ3b>kTmtnpb~EXQQU%3y5jb?0o{H
zSyMrA(-zG@GNiR?qUpcD+|i7ZTi2$^At$_D<M25ap+ocG8Z1|*hD(RhE=|%$_@nh|
z66o>o(|AQ#p`u?iOB?H5&CoMw4QNs+xjv}bm<arkW|T_!hBYNr(>$X2f)dK38Ywwc
z_cSUen0;T<L1Eu9jhZ&72bvP9(HhqrJPs)nngjM|J=D}!!lp^hq9Ry7rFn{6+iA_4
zcPRcjqxoeT%~{R;a_~IT=+;2?oTm9J5L@jED#o$XZgIgZ?6o^iq0>S8@oP}%sC|k`
zFr2j8t6{dYHvT-MxM)xO3B9h`PO2$((>_PxkfYk*6OiJr)x8gLOzR}alsvTi5z@6T
z@YFtU0NzXc1)aRSwO!vsjE`1h#AJN6`-Z{lr(KtXPJivcf2{y*6qQN_YS%siT##1t
zHdGwf9wF0CXuT<$5Ul<DG^{wO-F6b4A=;-dK=diC+zaYMwb55V!n8ZTz?7`vT175c
zBeWq0Kq9rQ-H>)#yWtriqP5RNLq&{M{wok?wPmr89jpE49kkAA>$qTv)3#9nBwjoF
zGB^{o-)=(dymqk(QWCXqgn~0kyMQjnUeMaoex9t&yN1pb?GDOkrCPOV0`#V7H`!oG
z)3x)c)Fnf^n}yk5)VhC7kD4}O0a!A%8);=PYd7;?MV8h%1`4ya(S^WW(WV`S-W=`n
zi&*ts?bk|>JZ*qCIP<k_luf^?wI{dgns)aHI199{S?Da(T4x3z^t#slIK&ib1Kx+i
z8`?`0Xe!oTdLOG-qRpKLO{H4)2OwqI9NN%tYO|gLpj`XM|In(?eqw}_O0DB{w5qg)
z<VsX)r|to8OFNH?&fD6Kr$K78e^QX5R;x`0piX<&>Oqg1){zP}8?;aMfi!9*W9V$s
z`W=OeX02i!)}lr0odwdWU3DI7aYy?aZ3b=Hm+1QgomvjP@w&9%9D|B(?b3GW?a{u{
zg;uY2Bm|oJw1aM#OTX5%6P$Oo3AaH8v=amL{u|VOvJFNJX@lu#JghZQwZ@1xl1>|=
z+I5t{zNg(mx%vCrJ@g!nY44qeg%7mc!w@>IMd1w|HSKS9AP=<)N(D`7t)GHSY5#f^
zQl_<+T+y1*_G!Q}tF3w(QXXl0k5H}RoOYVLEL+{{JgBhKIdnn2z3!QLn3{vmZX1A(
zx|%g0PP(k$!0D{JPGK?^ohRKsb=672fOFG548hn@-BvH)+;!i^qVt%p{}rhB(AnMw
z+*7xA4**`e+gCANZ=LWE<sW=>>r-HqukKfR!~5x8%m<IZu6z-s1?WU-XbRND?SZr)
z-QuUwd0c1X0CGY%^d@k@x*yzO?@3+bTUhlF-8R~pPU&`0aZ9M~x#u7=Oy^9cVv#yO
z3bCBlT?z#`qx+M7h}Ib0ZgS1f>V`tV8mn6`gu(H;11c<Vg3j+T0MF~v?10G7h5Zgq
z7j-d|OTDD~{u?OF)YVfF_hp^m<B*o6<35efY~3L`!CcWL(3>(xS3^naTwU&NaOUZr
zdJ>BAbu(Ka<*HRD$%dwDx^UVV3v^rFho(Z^H981g*V+CA(~5N2@nE^3Gdu~FV%-rD
z#FXfE@xfB6Yal?G&iOqkys697f~8#d{v<jpbUU8}u2Q#$(g9Vvo*r0Vt$UOWV{YlZ
zsKVy9PKgZ)kA=?Z9GbPdV;_Lj={80JQLnow!kij(JB~nTqt5J?mCCdxzY5WJbboDt
z^=-O?bf#?Ajd5X8hi(yNI68I8qu}q-xlm<xx307ZB71ZrRA$ht+YkwLeY#qTUG?ic
z=<e!Wor?Y-1G-=7y3U}klJdYqx?x|)9M+A~7i&gz>x<DE)t$Fe<?lV+4|~9RU$=`K
z)iGVtNyvVn3!*>hxXyC{q)q5*<DluG?)T@=n$!hTUEh@MjUzB-T9^Da$RnL835L$;
z=G#KHt^VtC5N4-OtHny%>lgS!k%N9F6UI2|FU~=jlRo@)D-h25$G(A37yWm%=ep_*
z7cl6iXHy30sQ$?WNORXqJE8EHzB3(T9(sF9Zh7iIq9c!&esv$ly!G$x1l&iTN>O=V
z{TIhDB|p9SW%~K+pSFTCK%cS_xIlgNC$J(&UwB{vp4VXgLV8D>)Hl&L976Q1R9SFJ
zzn4l>LiMBBurN&j8D0Dj*9#?JiO{ntARVdqAu*@*zr72<8U5>#Ff>Z9y$uqr@A8E)
zF?!wxkhA)q=rbCz`lEDn{+ymgp^7+tEuM+33*z;^QQ{y$@3a-N&+8AzVK7nuf&k_x
z>F?49<1gqL8E7Tzzjs6{MgR5{7?Y}xScGY(>F1ZCm9BUB2Dl7;gP$lvVD+c-X}136
z6gaNve;9{>Ir^8bqcd0kKRO-f>2p?KEMI?`@?KZ<DO3i0O@IGG*jb=|DIca3>c6l+
z@^yXj6#jHY`g^4HhJGnU0gLsYQX;fO|1Cw#O7#I$$5*DmMaiL?`h!+Jn&tXUe_&!2
z`tM%{Po@47J?2oQ7e5Xws`b-f0e?#`Q9<Et{mOSRu^RnzRF6=rzpxpdb^62f7pT|&
zN+shB`Wkvd8ufACW2{Mkh~6H}`ZRjjTl9_;6ll{QJ_43@eRDK<VIBIVRMp$5KXVND
zF8!-i+|;eF`W$0DdIze8@71ps1K+3r2DdC0^y@v}0sgN3^-ur?^z-Ln)1ZDg{XK^C
z)&0N?>$9lJZbX0O3BX77pHLL=o}NQRFZcC}s61{=9}!Je$Pe^CKL&;4`bw&jozQ<k
z8{m}wLn-jndVf0U%;<Z`o0`>&kAd@%KA+x}bNZd(SSMS<+8z))!>W@|VQ)xz2{;Es
zC4I2M(XeD5Omi~0QL4z<uz_xyxfr(755U#noJcoD+zhT1A3ADaeheOWL-cpxIcAVW
zL4}85%LkC=Y1m9>F)za;neS~lOtDBGgQgIjz6RfyVXvQIBYDF9hTk4XE5Oj{gRwxv
z;c@_i4AHb%9XIf)O74W=MM`-F8`>!1Y&~gMM!DJ$!!g>QP8k&BwT2p&JAi~4wo`sF
z+;HG;v?2@@D4SjoY3L|H=V^oadjQTD+$mKXWtdM@0?~$GN;t<DeCU}vYnY&d@L0na
zg;0Oa@Y8jWI79PSSmt=cRr;+ZSPiu+Ap5+b;12MKh8c3UlMJV0!E?bNjs`y2P&kG^
zdWwNP2-&HIfN6}S88j3JOE;(~>5*ahbQ183hC{DF?<K>tl=R3nETCGU%LXs1ddV{E
z%7?;iLy$Mdt{CjR(3xkj`q34Le8c)3XkIluOWw&fL-```6c{q=psCO>PWO1P8<;xC
zE;8IKh0q%Y7e9;@8)j+aFEO-GjYX-!=2O7S3?+Yq<)-1r8nns{4;Mj0g<<SfXs9%N
zvjLN+GBlA}P;L0YdJ39u8ERhx>utj_^37@tbsZqJ2B8cytTWV5yrkX`rw6dXkZlH_
z(cnrsq9(&M?dr`2bsEN64CkpZt<{i8oBJI@ksp?_%}_fJfObRWby(P85PbsCorYpM
zJ#`tbxsn&wZCF<iV2@#B8-(^6($8bQeFkj;^!6K`Q37$-aQ-1!1`NNGr!;8TNw;T)
z3|lCiJ#3i$1=f!kEN&p9hJ^x1xo6n=CZyaqoU;KLGZZ`rMGp+$WB@mAXq*o+VHnJ$
zD&&WT2ju2X8ie%zm@+htV@}hC@FoCf3~MRtH)|*x#MmRlV)DD@3|Wt$$<}D0zptG!
z<2k_XjmJ^|a4-&*qUC7(lAcs2;{hu)xf<)KOw`SIcN18S8o#7mn!9nU-P3sfjv4=;
z&y;u=_wB_Bc^dzG7wWx?{}ck~ZG4;R%zTU&)&b#byrx5^pYbqNHTfGiP>Dx?@e`^I
z4m9p2*+It0evBPACf^0%gmEWr6v4&}+R9EEU)hGv5MyZ|^qn$3z5t@Fp+>6+z%b*-
zYau4wDEthF2xI)a&=hH0UJRQ~8~0Ek_>8e@A6ijH`4Ir4jWhJ2ff(aQ6!ko7%y)&^
zvBpUnJ7-*xj<GnSqY=X5jr;6jQ-ZPV9G3FD(a{Q)L?i1Ca7k9<XNw{9g7NYn7)&<$
zQj#{sm^}ets_|F4{+MQ5SAel}qlAL_8OD?b7<$q88dbYpGTym~$z&QUA7bpXantJ<
z%QCLG2J5qpEI*80G5WMYSdMX#1uVHn>x)pIXROhJCEsYRqRW_9jj^<8Uo(cYfhaJZ
zp*(w`kv9y)bt7*hCR1dbP6OhG@hexb6dSKmu|bLPr+BcG8mrV0T5fz-1$!%u4vAo?
zG!~DeRb`yN94ytwPVy^m8Ck2qdE2;$;<+`(!`AhfMXm8EdO_D2SJ2D9-niBltPRH3
z=xRWtv1bIDnv6%ELaW&rlm=-n#?JqOrPWyf1;pGj{+^4mHY10&w05KS<Cs#1@lr0P
z)M?z)2+>`}zn4H!xA9|&_w^VVlyd1czLrXVi$3FD6n*SBE)Imjca4F605M>kN2N}K
z#vPRZ9Wo|xV8yU8l5UcZ7!N3bA2seR!q`1y4Hug38~>!OaLjm^Vy_R3%VS{Lxbaom
z3MY&v30NK)pK=9m(zx_>w5E(7G*J|O+W5m_sGl)jeg=qH;{dq^kBt6{(3&&;K%0=Q
zX~PJ_*qPSuMa$l_;UNGHrv7>mN7KQ5Q0QbTr;Wndl>a8Ia4}7F1K?^3IgYuwnZ$2_
z<)~?S4qEP}voAsYG1D8U$+9l+Fnt;aR!`G@cPR8SiNAnQZ`1z6AU>uebP?UxwE1ZO
z{Y<G-SiO^`?<xEcVp>gK!#HKK9|SzqG(<1VFcV`RI>SxB(%p*)(;@m`bEGMQE*zgW
zEjWg;Gp6PWj76E)6cM$aHT`!1@Uf=nY`}BQ^szg{#F@Bvz#4B_wjU(HRQ&+!eBQMB
zQ_LdK6hJAEB-2*%EH0Rq)3G4gbkzc(DW+iROf|{EAv4XSCMP!C<VJ6m4AWQ)G+Z<l
zP_*WfN#l%GrqvWio8M*ApSfVoGQBg4Ma(gccA+!Z6hlSdd8T+ZNWSSK50I;-bxGj7
zX4*?PKnhHAG?_vZlLATCO;MDHDKa_zo53_SeS}uA>2yDEB_<Y~a7s--?1tVlli&()
zH%(T<c_=J5ImTeH!lb2;S*7XAm%&qIvL3=%wW(}9NR6qHT;f`jc?VePObHeM>P_!a
zyraRigi0P7O)pS9s>yWK1k!BM(|4a*OzXbJI=7nG^oZUuIcR`uGd0};X*ZQxzk;+5
zQ=J8@ou<d_Ag0Uoiw30I^nME_+GF}67<zk6zfd7ipQ&>hIQvcSP)*5Q(@MIfF<=^|
z6aS#;IVk``rgcj&Hf#!~YQhoI`;VY^)U=f99`Bhv4};~tDeEhAj+y2+lK=U@lt(Ao
zanr;~7&BqYU}0saOlLA+#k6V62V}<dS~WDyn*KS9)+5t7x`Huh^52G*ojG$J0QTnH
zbhvjg-@XgIj%FSG(Vfh(Ezs+1ZlV$=7jpyMm~=IpDI)4-zS~Ux=TY;L=h5qK-aZ1J
zV`f)6xqF!3rRyD@<_LPldYKm`0pV?ak}Cau%)e21$k%+39A!WAPI89*%`8fR1eh%a
z=nOQMPeX5zIhO7V95+|z!NL>fA8dgOHdkoTdD6Trk8S~kn6t+r^px4Z8Ja@PIu^u)
znb{OZ4>y<5;XK0p4>@9y<|6t%pEjSTr{aux4Y{#V=1Wwz6>WZYA%w=5C!MgOXU&1+
zL&TXgcfpu=Gl$}S3FZd6V|m`JJc_YI^9p<5tV!ms)zEaotmgxtY-TM5KE?di4X~z~
z7tu*A&8(%pEZywe4r4ORGnA^mX#SagGndT9AHkVt){UZ-Z{A5e(^Yc}d0^Mf?=Ydh
zz?}LU6c(EKfq)m8-`<Sr-Z1-6g>kXf98M>S67zj0@RXWszXZ=sb44D+l$(?O#8`#-
zV@i}&nx9((X;tRLL}<EY4x#+hZL<ySoi*kqRGCt1-tuo0!TjWB0MwiN>H%ml|B?ch
zM)O^&5@<4Kmq2~9dAkvlXfa#G0_bfuUpRvq-Z8&LXMi?y<}=`FH_z2$Wjf5yQ`oW7
zY*z)LU1l3PA9S04qm*8cxte^vUi04fLHf-5ln~l)etHxvcg?v^0XJZ7TLgOt%?GKr
zV#s`MJ35EW^Uk0(V!mK~06J>^xC)4S<|o%c{e5$25o{VWdy?G`%supu8aK1a&6zOU
zYGB%w`6s$3J8fP^htV1HfexsjHQU@l=Ogo`rQn=1Z}|{X>@3;H^(?Tr@F|kxV42?l
z;%NDCCB~dAA<t44+Qste6KJ|xDi~1jX3<c3^Qa}1f{E^yfjF>uSoRM?jHjh837lS*
z&nPzMZF#X5EIyXi|AkOri)#mPewI(j1M|1sSP2qfnMVQSK+6-)02gG@(uZe`Ti&8m
z?+ME<35&nQ^I+LWPWVYnCDm4iSYB_zv`<<7YXS+i1X1Bem}Tq-Of=lG@N2L{SlIVq
zQ>4X6Z}`)e!(C{dvB(RcFv@cD6ck2Vc9(+0SeC2@%UMgZ-_q+$>s%QA$O)EvZ(!)W
z<<2hHl4yB?{E8&YK`Ks2v9Loi%~Z=e515-~Sx5oRbjvas?8~rhr1<YeOG_#^Gc6J1
zdR(?VtpUlhJi8d2*_LdoOSxk4q##_bCB6x`JWESBWae8|Sn2lLRm+R%n94QFx3w57
zw3K?o`0Ezub1<gJ^6d{`xnVg#mEXmd(=FgEvDi^Ytkg2_Cp48==0d@8)57^1q};Na
zQic_lj{iYLrKRBC!;R&0sw%CvR6GgMw=9A5qPuOm(@inn8q2SKm|Csn5EqC#%di7@
z>Mf7a2Hs#fM1S%|%LgMEYqES91li4&nO10OvGk9_idKt}erk6te^Mf%&GPUkwAw8j
zkHh*7OLr3BotBYm7}{m|@h7ZPw`H74z<MmNt);!T*OIRXYoDcxz9KVV(Y8a=pr!gU
zWDi+fXMh;CbS;F?5sNDyETfi{RC0RXVtEd@F-wvFoewO#mZ3Fnd380cn6UgB1KgzL
zd&+E0S#lSGOk2LAnB|ORTMAfaEk$^2@XrY?H|dCGYqP^1dhKk6>0X4rO;0574mOYf
z2rC?I)Z~FU*)S=E;B2$<8Ax-n;Ze}v)ux-S*}2(l8A9u*O-dzN?lw067IxWuNIyIe
z8xM+Jd)oX$DF82<;Z^ALw((8Gl30Cg)M}{kwOLLDEq*o=^kE)<n|CPaA7Jw}6=nw7
zq*E|E$ma7&h&gUE_XPkaY+iaD_6FO;jY9898=s%h3b9$TAMjH)+v(UBYV-IK{9VIr
zR&E0>+{W+%q(s<+v_Mg$jkyn<QC6Fu@578}oBwlk)p1!~U)-GQxt=<w3w4_={7v_E
zclTVmQkTwcI;U>a7ZgE2K?#+RmQX@ULg@}c8bKsg1jIn3;rBh`pYu8Q<h}3n+&Jgl
zho6!m7{wT-pma2&c`f8)7)eF2bcS(6fyT3py%I>oF$yRt6VLc24vh(nXY*k993z!h
zu|&qtE6|w4NT7gdG9&UG&{7${ehh*0jG9=OPh*@)$8V6%unYoZFzjn7&Y8(rLy`Fl
zjKCcDc9C&vC;F7d_`(xdHe*90upEY^2@-jX$^wi`KI4%<U<HgllqM@=tf2f&5#xA0
zOcXP&(ZRNaF^fKVUdFh$9;(Y3Du1w4Fv6BYypl2dS?IjPaJKuxL=_|I76hvqc5<<X
zp`@Ryma%0W)YLITvmsH>814YAf$>}uXpM|Ax<uN<IItDq3S-O}poOt29VS{CJesPn
zGFX+c+s3$%hsF+u{|7MG$w+j7vMxr`vly9f#;l*H;;siBMK7*1j?i>|gYg7yd3qUo
z%HrN)y!tZ?_A!R&jML9(pfl0{V{J2>xy|sRnwLRFIW78k8CCR&fP0L<cDQ|?vG!F6
z3^BNeApU@{>~CPhjCxn7e#qEF<&`6hBLVcesZqwR&w-9Ha=hWxIK%BXNK7&&Rzb}a
zBfuLDPcxorK@VpbAO8pw4$QGBusAZKX_K>`IfnyIC#G6~z8qxMd<L2`^XuOs;KH<0
zUCSZnb-ID;%KVZNMQ%)&PS`ul{NWYa>l|S|F$@V0=5urf!js9QLb#($H#*oJV}8CD
zf?muKde(iI^)}FanR|CY;5hR`O0%6{R;&Uz$+WD2(g0>}5wrv{7g90qDdta!z=D_`
zcLED$hUUTh5au6`VYot>adb+yhcmz34xR|+^Yj^}(@a?eS|gdeUqE9NvzX%U(agit
z`xxe8+WMbmKII0MSf()xjd9GnXf(z%11S!dz<gmLuyahWAkY$-QFQD}Vs6+3kj(TQ
z1uccS*My#>GM}QiBF)a+J{#_*Ggs0il)-#yHhPiC{F#mw7nl(;{9G5A34cR(7V{-~
zNOPF~j6*(`sT6`UkGX)tO!>^xQ_xbtEPD%BAv1^)14T@82|x*xLn+o$<`UYvmoW=+
z0m_-<yFsg9+RxICpprR<1)fVx)&YQO=D)rmUS^Jc3Dz3s{UU%`<~`bR)iH~Iz{oT*
zKNg~gP0UZ}K1DP070R+-VSaW6;w{WQd(qg+yhumFtIUs_0Io3?r2@1wl{7#d%#IHD
z+sS;^u7UY3ri#{#Ze|QUNj=Q%_d&eDOrqESCbP8=STFPC+w?jxZ&6WtAJerJ2K$*$
z`~)z-d~OhOx0%6<F<gVpSvkP&FnJVXxXbjRrRqMDLzBo5Q%wId=>gOJFT5CLnk;tc
ze#ksc8LAPci3+SnnVxi<8E1AaL`Nr><5Tcrl6iD1IH#De+n{@zIky?K8K&22{2~sl
z@ZA9WSzD+&`v7Y*#Ri>N?pFW~vNqE1>dZPoGqDTnu>r^(Vtuw2oNlbwU;Xck8?3vF
z;mu*zfsNof!io(5j|VG|4hzRv19S<^i}fBQ^t@Rw{{n43EdNK~uP^Hr`k=&dmX%me
zuvm5Q(2vzb_09gQLNNpaSW$)Ob|7mjZADJ8_N|9p5bK$KV8N`G3-m7sLRsyU-wtEl
z-wN~LEaMaKErPZ0XLxa%<<W!2NY*@0bS8==F@qM(`ZXFLhP8rbturj$R}eqT+CxS7
zajY)7v=h%7XoFk=%aRIz&#?~DAw7|GU^50UiS<<t#FJTmS+HPFWyO^Oo@WJ~hr?;C
z0LsUtv&yYdlfe>Cfb}9P^En7+v3{p#Hk<X<NeJYy0tn=?zM->k9_usmFrRg6KN<^J
zT&hAUVm-4DSTSp9BFvYtmWD%FDeJ^{7^gB;AnkI>?X1WVuvW6XXjQw!dX{eFRk3#N
z0#?nMErjmNEdHOcTf>@7yZl<#QZ=wT*3J_E^{hk+WH+!j(&4j_^(=k0w3)@Ft4CK@
zZtuc;3u^(z4O>};-=XX(i?s<O)5ePA0=vet-`osh2kZA!VC`gO+y>}kH4nj3H|yu6
z(A~pQ6oBO>>o*G=?Pa<Bm%(Qx<fAivtSZ{l_OsrkfW-hSR}PljtQQW#{2i8}7}#A_
z+6sVstlk!=zRx<h70QNK?t8)VfVJ69$)aJ_tTb2}VJ)U5XOz`QC75HZL@GHQXFd8N
z1SeRvbZ2mqRab*<PqB)|(KyZOlY(=Gl|@B;4(w`rEFIaOvLSbXJ=zP*i5>AGEFEO$
zP@2w}-AW6l3%l1DzsMoB$5{#myRzp}2+N&4{{!$GW`9FP-bdKhcfjMp{*umwo^17x
zVDV!6od)L3ev|4+ec0Vp597-=(6Qn;`vo)la)RCZ6#8<Kz3Ub%`LoZH_W|tZZa^-O
zT}&17r`V6sWF5pFsHKYYVD<^B&Iw^(_kctgTTbgiIC~R)At-{KPb=+dcK_2b5y_5N
z2KgxV-|4Uv%|1YT@fdbz4Ft}xpYQ|cS@ufWXveY#sTMe%y_E{U6WApWVc{IxMGekG
z_Hx>vB(YbWri!0rb`AygQ`p0QL-0I%E~WO;*zdOkq_cgfLL-Ci=ZU8!lWn3|I*aW}
zQIKqQDuu&y*nhl;{^qhDq3Bp1TT%v)&;ED|bQZ8fR-sFU>_6yyTg2XW8jU4v-h8l>
zvabl>p}malNJXaQ?76GKQ^8)vfbL7|9*WgfvAZ;&RkJ-kAXvlhq-DRB9iqTk)Ug}s
z+*Z%tLo;dv`<D*^8ri#gp}UE_pN`H~*fA~uEo|p%$hETHr)y_d*(uFX*2d=1+2NX<
zJtzXPo&7Q0$?jw)%!BSOc7Po`-Ruu3s?ft$&H!9zGbtB-gZ<}fczBEbdJWv~W52-z
z=w~OjL2iKk3~k<TvxDiy8Dzg~0_PpJtPjfWvOl1$;yreY4Pc1fLGjK9Z2K4aaB-L|
zrl8eB{Ay?&VMk>_%^2Hp1lTzHBdX<?U`O|(af<De0QqV5YxE$_u;V`i&4DxT5BxBW
zoF}57Wk1KWAJ_rT+_g}BkYg+ar!(g^g;HHOvGXBth~pa#w_Q2g?8VUL#*w*U5ZpN-
zG=(4GESG}SgY$eOXr7#(X!SqJxkg9mW1KVdK=a~oUw|54PWfJ7$2sjA(a{qe@$bM+
za(2@m(U0Ruv3-Be&Ujz}oJS}c5y-Ko!<kc@mnjz*%sJph`_B+g=@Ou!oG)l+62|$N
zCgyO?%lR1f)0{6TJ{-wWe+@69I1j1xGlsK>Cgd}mM<0dwS&q;HZpU)e6qAhO_^twH
zJSTr0#1lAM_|TciVeN#LBu)>#Kgh-|21^R(r>E#&UZrv#e-bX9=e+$bTGKe`Nq8_a
zI7jJHSSDvC8S)o6tD9i=BBz~}{VdKP6OGxN7RvYKaSrofH=kp=1n~mS$j876Iq~#1
z6>*X?0g5^6C>mJ8VbNB;l(QxZEM*)oJn{DV<(%a|Kurbb;7t%KIrB2mr%RlLR54M-
z`7jh?QO(IX0qinIOL>DDP72jU*K!<G0Ck+_4G^g3oD2qN;4I9AmS)b`ZRo@mP7<B#
zTR4yX0?t;>QX0IgoUK&3*2bCF0L*@k^TjNn?VPT?u++i%hr(l>94W=Mx;Rdhr|jm4
zsfxFUbNC2!U+4TtQQI3F-39dNCg(}It<%d{`YVRy7U$b+$n|mJ=uUJ$=NBEs2RL`>
zb-2UHe-~cd<$M<m>>g(^ee&YIo%4Pp><)3xQf&VLCwe7J40G~VL+L}#&cC2^gmavB
zoTHp&^stR_7Vg8tGR~Qk11}~x?^7+wBxidHv`ulOI&e;NM1KLB;k5h;Ee_nZZ$YOc
zccdF~`?(M3p4tI!!ndF~bM5W4+i~H3y%Y`~;u=Mecjdn94&82Co&dm|8$tW^!`y&u
zU`M#GRRMT#qhE&!Pwt=ebROlpkE79xduANYcynK;bg&P%_YUNIxi>e$(sAy>QrJDg
zz2FLPl6#6`ihkVPcG~UubKj>RcL4XSFNlF$8(qK;;<i!EXfU^g%4kEl=V=EQ%3X9G
zf??eH6`+N4qsq}3!Tll#c29F}e+te>?z%kajN%%bK#S(C`2ye!_lM8n#aZq<w4aLQ
zzIX|)#c^+_X`YMc2FwCT;ASSli*wvS`qdJ-hbgI+#QnDijmg{(UWI%Lw>bx#X<QR+
zF4MW$i@}n?4cQE5GP!?^qT3g^kyI&ik!xFk#w>0G)rDnqKcaM04)+EH^>VrKw2tI)
zeW(7ramC%f9ex*b$LIr6Mcl6`MOVz7K8%i*a9z3}QOeDG1)z-k;~(f~Ik)W{2vl$<
zXcnpD-lHP7OWY@&AYRQ~{s7)z=H`5l#u{$wEAXk7YoJ?Tb=+U@jj8$dTrPcArGZ;<
zj&6K3avdqn*~Goo45iK7-@XRV6|VIZcv`tz=wq8#xzQca-NqfJnulxL87j(a=Pv#S
zpo5#f4sxB`UJW?AxTQbBZa3F>4~;$C0a_xjbDyFZY%h0H0lIXH`^_}m?&A)OfW_X=
z<x#2m0QY~-0o>-Up``X8*Pn`1?{L$iA#s=6ISu)H+#QrDxX(RA>755$-XgFJbK9%n
z??Y|{7c3*(d(=3}^`cDo7*{6;80Ws^3`ZxpelI}TB=@s8*q!43K!NCKJNL_P0UdaA
zH$b-|Z_^gA?&rPu8k8R3Jx1XlC*F3786M<)9suCXYocezg}3Z51P<{$Xq;Sm6(2&k
z8}D{9SPt`A=(v1@x2yn`Jb15VpwW}JC=vokc@3Wf9OL!Ti|)m<`^2HY-n?J_J6Q14
zv>5yH$`3-@ab5u>bo_XOUcmf$$&aFI0lYTK0|)Ycp-jOk-p-E!f_Meb!0ljOAuZw|
zyc1C{5z708=9@5{J7u22dHP{+p60EjLsBF!%nHsZ-V=7Zz8TF6qTqZC?@P*1oZ(q0
zcy^X29fUKnyuIU)h~u?=0T9o-`w|2bcuOcXkjV3@1(w8%o`!fb?`>M#Qh0?YU^kUF
zL<J+~c?0y>tTdk2T$oSim2=ST44z*URA=&9Ke2=70*~Jbo-AG~r5&<)H_pOR4)4bf
zfLz}Dr2u)nd;bFD^VU(dWdZMt2AC-11swq>;%)vFa>cy2E8tTJFOIGgm-ANB?z@8b
zVFv^%dC9ZDd5Kp@uYVQqC%SY{&8zyEYAr7F25HAx!+SCcYHE3Vsd%}L=OckcJum1s
zSQ~js2hhVN-a8+G*34_6s}omvCR$cnc)smmY2}3n09@rgG+;#Ac>Q!7yT<F;1A%tl
zTWiqI4&FctSh{$bR{^?tKjE7#_?L4$K{<%md8f}p@CGl1whcFVy9UwN%Uf~+mTvL#
z=zom#@mi@!qn|f01KI$u>K}kX{LEmv!>eBlOLuv>RGe{-S6Knq?(_5x07JaXUqa^t
z-ef9#8s>f53C@SSx4wk9eT28!2@<2chL2!=g4apKJCnQ&`bDOA$5w%7n)h}mSY~)P
z>Dv(w{J5`S(2<`=9`5I-MFAY(GyjFS6Mr6U2@djqq%5lozmO6Ihxn&cAm_?oP3K%U
z{!#~Uy7NDL6V4pA^MAR4ANB};@CPXM;2&Izj(YOHqJa8Q{<2HZeT;vF!Z6<ahjeAi
zhritb6TbZ7B*-1-?=3;&34ZVQ@b@I&Fb9|){}(do&yS-ddH|o*0iA*T_4I{;Q~W1`
zFc!gl4=QU2;oFPFKtuU2@_~l&_2+<v^AFa+L<D~%5++XbS&3+j<af~=7{w2}h(1O0
zvnU=P!{^e970bUuaq&2QC>`_T`3wF=M-%wDbmlq7AEK>hBA-Qv_9XtFG#4fFRXboI
zg`aMZftpml>@v{v{5_W-k<RCR3;7IweF;D&znJEP3;ang<S+6QX*JE_pDc#mZ2k@&
zXgPcz3Nq&Mcf1PM^7!6tn8@cl(3z)@pF$afB7Py2)ED#L+YV5|zd$*}Qhv%(+JBbu
zyXf|4Ie*Uy$XD=R{0^X!uiFgPOZ+*wmpi|TKc^7pFY|wW4F1;e_feTaE#FMJi8}ty
z5%^Tk-*65}8~F7?fJXi{6|^+*ckPGjW`4Rquq*t{EpVoVZ<j)#jh}j--oI;nDQ!pF
z`A2?+?k>KBuH|?0bKXGjd-!Me01WUy^n}6N{3q#jHOQ|$54(5xKTst7F8>)lz&-xg
zdjanASurp%#E+m7ya#+Q`qu%&{B>0A^N|1R4qzjE|L4In%K!Tnx^X<lucCwfIA6LA
z@)LYNT6ZV;pHThe6hHTMNKEsMp8?G96DSYtAei_G0*->RZD83i$fHjd9uR!^2O6CO
zPf=m&K|z}wU2+yY&qH5a1W#;-!9#-QsiM?XkVDV7o1lV{X?AzP;<wQ4!vdEVz<NZ`
zLLK!GTz?O0JO%q{f;%eEQ?mA$z$YAyUIOzmVBUfu3ur!q4ZlF#SI|bs{NsXo77YFg
z!Il_kIVspgX<a|TzqCU83%1g)93bFRh%->ICJtIo*#+)2i3JIYE71F3K`|}uAp!v%
z>_Y{o3eXrP@SvS?xZt-pp)^8}OP7953$~qve54?fDi@;!j}C(+T2QhWLlPr+?p=U0
zf?PeibXL&%4_IOaKORGW;{@C$j7+@XI|sO(Ah0vmg7utWA3Xwzf{>Lkm?T(ARf5R^
zIn8=0g2n#uDOIqn5G>~fFHyKEO|U8vjp+g=eT5)HFi!jYOhMhZ5V#=tYAYJE1@jqj
zG)K^~4|2JJHB)dVPY@6d@qB?j9xMfd2mjSN6$&~dAzvi$&jztrp!onkl?V>g(X><$
zLBY*3fh*0u<$`@wdr%?Bqlc|hQ1&u(UlKT6f!!)W*H(yE3x1@{>}A1Hsywd|Jbx16
zwSssq8tVjyBA~inaF`M_4T2M2+Tli{;L%B_X%Z};e|pm_c=8MyuLyREA<-h}x(YR|
zg2R+mzAD%<1iNj5QVWz`6PT#5x?Pa<5yU$L&o;t~PJyTsCb|R(zXIzPyhdNQ=n)Lj
za9tOyp~vHf;8{LsHw8yS|I7agE^dLETY`Klx#$zDpar{M5JQzy1A@C$;c{E>6@3C}
zQ1Ao2jduhm*8;mM2u%meJ%Jl-wC@WTL%@avb14n|KoDI3mSMpMjj;PrFmF3N91(1*
z1Iwsj4aF+P1Sio!`}}diPqe3=5aiEAw<iTo@!**fJWUhhv|#c*I6Ncpd=W|=grmVw
z>L}EEfMvh%A*D+X2s_t<<|I_V4y6Z$jTAa?77qUi78haOKXC1k@QsDQT!qb4{_G~4
zuLtHX^iTlU4+~?dO5%uc$zgbURJgYtCXNZujG@s>m`(RqyoH}pQHhW6z|)ZM6>2DO
zb6nWq29^`TH(vyHQkd{xHHlE&0L)+bP74GAgvGSU3ls)3;MytS1A6a+gw<)#87x%z
z!|f2e@H+{Vh6>+%6}=A=&g%p*T=)lt<s*a*biL@baN|m_L<+Bc2@oY5eguy|w6Kwi
zEMkN;6wW*&v^@>)&kFxkf)*=mn~y<=6XqQPOT6$-Ca?ryBX#?n@TXyLCJGNd2GvPI
zdm0@Vl7-Lz0W?LpaXGw56}HjQ=e%$^-T6xsE+wDRg))lbW(c422TP`KHGTBqf>1%F
z6BmUSDOR5)Jfj3lw(ulH*>i*+(X5v*OuL8P7YL8s##j^zXQ?nUMZ%MGL9|#HZT}v+
zON8msU@aAPQHe^K@C908%Y_9luv8&DM^#3Z!X664ToSGg0B4nOya`IHg(Vs^UKW1(
zD74iG^PYovz0gSn&>*a!6jGyb+d4SfB>akkz|F$1GQoL8`0*O3ZV@imQvRV;_%s!B
zUKNf~&Z|urO~ppngbdmwwhL$BZ+?fc(gK!FVKK#^yM)-9;^h+7P=u*RXrdt0bz$Ql
zV7Vdun-17Fg<%^2dWEL<K)WT}Np+Kb!i@`Hw_g}QNz4J^t2+AP;%#9F6=DnupR~d5
z9pOsKJ>3-+vmtm-`0F|J;=XW82P_Q<izt}%K=^tjScZiY^u7Ow!fjNyG9o-eftOL?
z|2V+LgbO)f85h>m^{ok^jY5u-!d>prIVFtDK|iO3Z(IM%zYE14@XbLK_!o3Lit>8E
zx?fcGGJHB9Dxjh}C(#jF4G)U4C{5%n${~MUM9+>v;E*WgTNrc|`BB=%O{CrhFWg0+
z{0g@Ziz;Z>a747q3qA7?t$PyUo}$hy*gGofR|D9OiL_ZDdWlw3%FbK#qzu}8M3-m5
zeP2=8yPzExec^`26QZ-U;++&V(JsqR^mr32`HKRuC7B-}x<+}lK+(DH;KeDC3uU*1
zL_y8a87#v8HJ&v;L^M_m5GvBp3L7T+m<sB`?V>m6K5wKbnP!71(N#*AM2ntt1#66`
z=M<El5k;&+<5|(W6L2P0bd74A;zXZ42NUt4MOk1;5IJO`@tjDn2bL&$kHTz8BD)S+
zl0|#zK$0TrKMXCYqLFf7=S3?+fu)J;xpa<87j2{SZiXm*E+jHVTpQF}5IyrFT)ZfH
zcMNv3MBb;-m@V4)G&planM`20qAYh{d7?!J(9wL+F&}^ek>OA1E)<Q>%2Om_(2G+n
zdiEdqTOxXL18Aip6@`?_MEC5U!$i5LpT4tKA=*(7tWxw*DzHnU9|objN~EB1t`=pa
zLEB}Ki7tB9h(1~mw`)aXG#S*17E)TfUi8*dSZWXnXfNF?5>VRmis(!vK#NG?0=ZVv
z+V4TTDvIiYp*B%lBGpk{6M5x;r(Lv)LM<JlAE_|CQ)Hn)V3){44O+Ko&F2v85nZGu
z_PWSSH{x!H(&_%qO;G|DpjT8n4sc79V}Q;+(W*&c{i4S*p=?0Jpn&*o(LK74GAKF}
z4e>i7MK#@cyery4Tc~>?DJ|yrMILG384^`wp=%FBObVF{iyoyM?n9B~F_<3_t)aVn
zqayDX4C0um*cSrhqA0p6I3Zg09V|_XQs)4h61`XsxoJ@%)hN!0#%4pAgSe6^=N-jw
zBIjhEzh69yrkw-g!(AXciOW8Lwu9n{`H*lHzeSl!7xCchkT@iE`UrMi#i~7EaTEW%
z3&36c2Q4y(#r9P&ctm`FiWfY@-zy;JDc;qJ#-rl0Hh6JN9J?NzUgA^d0ldW$dLZmR
z;&<tQ;45}k02~+pNf(b#i2W$9byEEI4^ZPLo?HT@{^C0{-35sID1H+tez6*APKnE?
z=q^b76%~91i$AB@nh^0Pw4VwUzjhN?nD~1q2!xB}-oPTnTmFW?Y4MBSz<i`#ypys6
zQR2lO__fc7J1LZQR{S~D^~H*tsO&6Ge3gPw@#0sMFrOe+uLL+J9$WyWiDKp^h$o3X
z*Z|35b11Z=h<jIHoKnU7*#PIowfo>&nt0nMu$wM^;YWCpA%2X~=$T^s);&;jK^#es
zz(w(<zagI`KAHs++2Z*WR?HE9xEdf={2P7wB2Vl=m$vf7cd>byUm#xeGE5YTKl=_!
zi^TRS(2B(`Q_*XQcqdI>rD78UEM?+bi4Z6k+qH0}LX3(YylLV<I|m)TB-U5KM3uPq
zK8CGYe9;v?T^7%J1KMiDPuoDN6?f5lUnhPw0+#B<IV>n`5YK!KmPWCh7UL#y89gP<
z;^Q~Lc}4sI6`x)ezo0~8o4AtdL9U6XsPLs-oPgBV{0{N)=c(4WQ|vPY-@3$Ghv7`O
zc)AoW_K0J5L(O&Z02>Bxh|6fRbyHkGVX|KFC096lOT4WGYWl=$>4Pr);%!#}2E?;n
zA$MDx(*b3J;spt?a7R3wYRm45ue=9;?}_hCz`}j;Q|qYyWk@{v4$MCgE2x5ZSbU!L
zAP>c_(b7I5PELj0QE^2hurcu*s>~Y~-`|eL3Gv!qG){_}Mj<{WHd8g_w782pF(aNi
z3WE-kJ+}ZHCB?KI+%I{L4(10WtQBzENs@=FJ@)wrC1Dh7ca}7lK#hxJsTE!vl8n_t
zo2z8+^N?_pJVP01cZrsM7!OGt<vTqkzwd+>M<p?IQ~8)=fVSOUk{t^$T;3AzSTy=b
ziu*7mzLHET;5{yRatl<Skd*C)>XVZ1R)S{tlkn?c!e8P`9SxAYORI38#GTI4rzETC
z{!NHvG8jrjC8cy$3X|keZX#Ur*Hh?IghWcQiqn$+or2OxNyR>xh?3;e{qkr@Mi`XE
zNS4#;eMWMLt{<G0*eR16D_KV%&Msm3f+t>b^bzzvL2`(4G3O+0Z0Jsuq&)>Mk|ZzD
z>z^#SG65__vX`E@R7w0kC_OK6i9pxVB;_-ZOP5qrsysu|*a4PIiMA7R7bM@)jkk-E
zUuj35B{|CgXSU?tWw7K(>>gA%kSo#s0-iicDm_>E68BID7D)b}`KC}3N;7$pWErKr
zizP!8nJSUo7z9=-;Z6gTNiO^arR9<e4g@MBAJB2CQt}&JKe!~>QUh9*g!dBst(F{~
zgoPT(nNnD&m29=o1+0@iMqfg!m%RH41REstUIb60WR?c~ZIaxj%uKUn0d@3><Q<CC
zv`8#8z^#(zZy<10a*zU_ZIT-=K<=94%SYfvyX31!;dY0FO*!Xo$=@p=-Xr0k1?P2%
zX)zjaNYeJ(A%9achtgZUk`*-R-je8O7U`47>9OpWto4O!0}{@9bo;i%|1Gc#N}>h8
z?nqMTmhfGP?=on+Cvk0umiv-_s3Lqw^4<byc_3Lx3AAB}awX&*O14HrU_|0Z5sy(x
z+c@1I9+Q0kHi+YrB}?J=ge1cZiAjmx4PZ+0uo9N0CEp!~`!kY!M<{iW9vKC2l!nm>
zXus4%f$am*m!}}$Bz=>r@()T=UxrR+X-gt#E>h*2P<==m-w761=|M_lxk=x6mFmyj
zrNy7X#9`^96h%5B-B$q~52=~%D|t#Kl&n4~eeen-j!7FRz~v?V@GN@hEj<+u;3I9y
z2Jn@((23x<bVnuz;e^!tG<tYay5J9(_mgg%f--;U`!urzNVib-Bv5*n)(ZP6X%JoL
z3X--^byu+TbqXJaNVya{50ws4TrW%-T?^K5X%r<jBBc9n!{BLY6J1G<l#Wu+I!d~N
zK3Nzojr|k?G15FL5;-G%jRo(|O5^F!9xL7F2c2<J^#gPwUiv`_umrpGn^3@WQpa=9
zohbb-9hQ=$$H|LiDTCg|6zMPY!lz2>W}xQ0w1r~HY0}ahfOP5Ky`W`C*HO`7ru3t$
zV7Vamr)0=Q={gh4XGynj0B5$e&lk#aq|+7%<Vxr52WOtt{_QTfpD*Ro!&)Rg;sIxh
zr3N_~OQg?Hl~$?LR}YCY=@-XAE0-Rs0j)yn=m=V+bd(Odm!wae0<B8=30;t=mWKU<
z9$uCXUjV3)#vFvDT4^;^BGyTT<VC&od<#H>)WMzyiAHJbeVA{OK26tvnx&ot@cWAN
z7YoL@MS5ryv{vcP4<LV4>Pe^dHtFuqK)WUlr`>bA^y@sxbx2+0aHdl_xez+Lq+94X
z)h%7M4xBww_FZ^*U3w=F<9kE8kcumBN_W0Z@t0m{<`j5tNmqM=r%&2UQHp-4nqp`J
zQuBW=p7hH@U>TG?Lsczzq<>Rj?5>pm1hn0geia6AUuvaAW=QHu3;hFW`Wz@5mJWOe
z?4fj+%9}={1#Ar7sI-CVZN{WeO;i4TT>9c2Xq%8egOuU?N$IY`@M%gKMzg@QwC^P-
zosoXdgP?<K3FUwsWwrFM?U$ttz^4PU-b6Gy$@GrE4$A&V2UTa;KXfE^k-6{2ARLk%
zp=IAyHb;*}H(72q8r@|^>`!plQ}*k#kUt_@Ncn6JS;IB(c*@?{fX1V;9a~`cn9Ox2
zXkN05O8~rO`UyDdBipzbwBxcOdO1$WT%Us5CuJAt<?@rgv>qn>W&Dc(0kSt%qA^f*
zl}ffw$)4MXE(OV!y^cnEu&j;hB12>s=}a3cdvYm2m@JH9jp4F6<adOu@;#V1En7gl
z??~BObOR+ywwv~^(Xv`81}{eTP>61yk(Dk5?X1j)&Ly$3{#>xc$>tOSi<dRr0ZW1`
zkiL#~PUaH;*Anfrc$$5ZWItX5F<G{f0lO)(bvt1&RTj7j*m)V74tHs?r)ic?mu3G9
zT81p>HOOVkoT;kpf^35WI4{a>lZh<ZE;@&0%YLTFZjS8X5n#Ep0_ta;>|ZLY%9nLC
z0TjsW_vb)cp=>v8_lsnS6!0mQg;99EMCL#fa;eOh!p7w?r$LygkUi;$#!A^-%4A)V
zP1Qr7O16#8Jk>H$CJbJdUF*cpR3l5v0#+;g`ZZv6va=Fk^|BA>n9v~WiiV?&vJdU_
z=rze)m@wZgOQU;XS7d)=L!w1?hmOsyvZr=I;;QT-#jDz6O-cw}lhrIkx7%g!M8Jy<
z+2{ti)+uwI17%&Z8H)LJ%XISqdSp(N`@JrEiOwuHWSx|-zbSiV63TjI$@R4U-IC=|
zK~<mZaUqEPvOg&WH6Yti1#nwdPLc3I*<Si#@5q?{gNeJca8GpRo{arI#^Szgnx6F`
z*_$Qs>47Zt69^2;E?<PeL)rXr*d38=m<H#lEM*mFV=@7yaK~lBmnr@^A$xomS|?>o
zzl9f5GTlzFPRstt0ndyqje?sF^2jA{)KUHf-34)yKcw5Y2jv_6V9;5<e=C5CJdR$<
zL-N3tz+B~4Iz_t4GvnZ|yL@*dz+t)44=hLID@4FN<N*kp+2?!8#e*<-RPIp)a7=#x
z1bDpU*>1qR<-gOm&PTrNadgI4E}-S?xO~TPu$+)T9tYY<c{!b&{Nz7XgT-I2S`706
z^7KU*{6P5+$Kb^&dB``Q1<7BbEl{xhV+zQH$ahe3%^oUGpsi|{{L7ut7A~))S2aTZ
z`8<Hraz2HBBIQl_08#Q6Rzp5op1B#iW8}|?0M5v_ybf?y?nn1X<K=UfLra2u<V^^i
zlP_70#zc8A=}eNJJA^JJ%ikIYONxA!3~r~|<=d%N<-EL{zU-VPze7)1x;!=vK4r+g
zUxs|9JY^dMFUW&F0=Ot|r&xcM+?8s*vgLnFqA^Fl-Wfg2l@Gsy#yoily@vVn1}k(H
z$Wvp%QYgQggi$M!d&b~bE|#<CG*}|H&!*!|sr;ZL&@%bwpF^-*{$@QSD&#-VD_$vI
zrU%O<dCyBQQ6+zY4$;-}a0jTlEdT0H&}!u0xuG+)@~|*?Ung&lL}R`DN16j0<kM@Q
zrBVLad!RMR8}>lFS+1hR>580VFUHWc$PJVwYn4CR0lQb_L07@kCSO3FUX$<fgtm71
zS{F!k$hrRmXQ%vD8d$pI=_WLG%RA=5e2;vN5+<(87f?>JSKg8e&Rg;wMhsV<TpkZC
z{qjtT^$p11*amQ0KJ%3~fAV#Ecs1mP<bH3#`UCl^8K4czkM_a(L-`$w<&MZ%RBAFR
zciat~WAd4&!7?t-y#p{Ie@Of6N%`|fp=C<mO9e^O@)mEHosm~jIirK(?@F*ZDpov(
zA>6O<q)|Sg`0N=BjFaLKJLN<UD$3~`<g8%Q(ceY!d>wQjQZ)Vr30DPcKIGjLzfs|)
zyJEdJu)~UHDFk*zal96ohvI<`<UAF>)6VIn;<_*F`YFDg2jH)8`T?8)if?*hH&Ah4
z3tT&;n4(I)AjN|<bOsJqJgx#UL~(ixuuw%lC2hkLI2PfhP;93xVuT{73lgUlKhp*-
zQqe)T3ZfJ<3Ft+%LNNkbjAAvNk<KXm8sW@Yg^L3~tYYUj2*fF3DL@;qNL>gI6BJ&b
z0-RG=c2Nu}QQ`U%&?H4YAM(kHFxot%C|Fe3kgE8cD%{R1*tGXgQzZWjkgoWPt}kUM
zLf%7XG8KQjz{CYb(@~hXsQ8>-xGY7^S1_Ng_=Li8If@~7H0CNgX_C%U9Hy;Sp<-k`
z)c_SKzCMZ8Vud^Ho=X$~bhEEiv27dV%M>qB=|#CBo31xjC_ecHv`WP`+FMpB{$+rr
zT2V~VpUVnox@TLXc%}@XRxv9DCh8OsBf#nvC8Ov|gW`880%%nDQfQ?~G5In2VsBOm
zshsPIVhio|TNJw~Z{MoeoPus&Rc!bRw04E}FQ9cOLKOgA3R@oJyA^l7gEKvf_6K0O
zu85?Z{0+r77WjKpvGfA8^eTENJbg<sOu>adg#(qp^ed*%!nFZ~KXvf7UGaV(cm@?|
zROxa@ajFGM?<$7$@a>*r8P$E>S7_)79#X_E0ro(V7XWR;ir@199xCQh+02Ndb_V80
z6<6r2Gp5)~0j6<<{yGFE6#fO!IjLa3i^eI%rqxhAtyn<W`x%9OIVA@il?!R(xL>(2
z1gr;?X%y>oR*FJFb5VX*3f+g4OAo>eSLGUt*SIO)vA~kM@;rSu!b7R6fPkm6_$ja)
zRhDf6i?`BD<pMs+rc$u@DnAngJFeVMKj8_bR~<M{D!uG4Vo3dzfpm|@UwMrluK?xp
zjqp2A`Py}`o>IQ`IOKzr+RI=GR!S)L6{1|?4J=ft`5tP*l&c<sGhDgh9f(IL!|217
zr<JoVp@)&mia^k!lnZEqj#i2#P!^;7>krV*DE|tlJ@{E=(SKQD<>lX?El$}+#WeBC
ze<I;pf^yALICD<<0zK=A%HQZsO;YX|go$M3%ijY_Q7)lHDODNV2i@nD#t7(4Q*Nz<
zqv^`s6g<jMrt2_3naU+c04^vqD0q8OIksT_lXyFnxroTk&sD~r_;&W}7wpv^LR+Eo
zg+zE!q&$`ZHO0!@P`Fm2bf7ZmQspq+aw$`;kAd!T<x$#LR4AX)0aPmOR{<_5Z*U-9
zrPQXwQnm6R1*<PBrK@1RM!BgESgmsH_fTD@Y`p-T^~z{U<TfZ5*~1{%sJs<~@w%dX
zdL^(H<yTb4)vEl0HZ)h2FXREVDL<eI?wZp2K3Lk7g*8yxp&XwD&Q9gBQFN(CSvLzx
zuPeC@uzN$PIs%qE%CFym>buIvDEx6xd6uG)50od~1Iw^-&(n7BJXFqG2jYnGsVlHF
zs;sAVZ%p~rbHFB*ofOrWQocrcziH*-_aNY?`g||Cy<g@3BGepEc~Gv{Np<4^z(LiW
z%~0m7V%384sOot-S07W=QS!t~wfAk9_g4K*H<Wx-!i!WD;;Y(83GCyl%~X_fLiIDn
z6HcmTT4BOZ75Nxg{Z;XZpwACbY3M8)sFEEA?Ud>z3K|EgSbJbFM0JsBCPGzfO7R<n
zsV-2&B3$(o)h9%#^16YYR_&w-CR(-52XZm0omo^Baz^#=zq7k)>;^oIRT*iZ;#5CB
z2TSoP4prtPs9q_9{5cgP71|P2HzbfxQpJRTmaLllJg^kipYMVtRpmwT!}F>IRG62h
z%IJVk>8j1^VE2N`A_8Z&YDojI998HS0QOu}_6!CwPo<{MP2{U;Za`^)YW5BcLZQl?
z0#ik*!1tlFSd~5u`4ZLkAvjv9dg2%yEmQqP`Tla%9NNoPsOE2n-AdKBpF`l1%K0Ez
zs#FI)f$C~iJyq0QR=s5cR-@{y2d&nwn*9sp8&m;d0Bx!%+EQOr1ykm^UG*DP4|J%O
z{)4V{svgUNe3$B{PGCK%j;}$xu2NnB=MB~0<l#+K1rxe^Rg<d$ZmEny(E3#G)Bd7g
zmAM}Rw^ij7_a9UZQSA7R%Fd<z{aw{d6dSpxdM6p?@2lRY<o1wicO{fQQ1$GCYs0D$
z4`2^fPtpc^L{<G8MrKUqOmEz{N=?hcgi3`kOU|EEB|Hrer&K}oQLbqfn@U+{R1yCG
zIH)(%uFO%rf}#=o)tz=d<PWHO{(_*BI%XeQ532v6I%H?Hb03ttsEhuD`-jvvddghY
zA%5U=Q%61u;GuS03onkU!yZESG4;Mj&_gfv*L3s7Tm35?-+a`C6khgKe?T?WC)M|^
zqAz~xFp8r1tL<z%bO)&KzXf8Tx{xwhr_^o&fFSi+ie?6@H_!#E5cNkZpe9URNU_*(
zwP*k=5$YOBk)Kvy{1oDm>M!4b`6%`MNw^)Yw$oNRMqPFqTF$7se?iMx_0Td1#Hu&X
zftEP+N)vsDH$fdjGsQXeZW`c3^}lAQNmBph0;S37mleQL)$xuncwVidSZ<nnK_;}N
ztIuSBB}4t&8OUX-RX2cLP*0P=EVVzSj<VH-R8X6v4x!4nT(#@};98#A;bXX#uQp>R
zZl7PEKFNiNQnlOL7>hEsr5MC=^<{d~E7Vu0%)L_m(_GN1)M>QPSF2|sDL?<RI;aV>
zI&~cf;`Qo3s6MDc-AZAbMz!i!bg4=GDt&wHirW1W?6#;^(-q`a^@fk3<(j&BIcWBF
z^=1<~)1iKP79={=w<tQ-rLM|@M7R3TVo3C;CwGGNhT24xbvM<^C@J2n_NfQ$minD`
zc+sa;rekFK)t_7d7*J0RqZ7B)M}LE*LA8c5PxsVilwQ5BPOXHNA$201iXPb2q7BeJ
zte$%v#E0s6`Dh(gJ5oMtOx;ZR!g2Mbx4<%?7N$VWq<Y@B&^@E(=fjeNX7zu^Rn0>B
zj@*9DJR!V4p!t;MY$wf#56nAjT%H4`i)OYTz#)zB4me#k!xW=%)7Xomz<NZJK||xA
znN3M?PmO~ZE*{m?UjWZB%||u>FOAQ2$a`xnlq2)euo}Q}LgP9c;wLrT6dUo=Y^O7h
zzh)_g90D{G&!X{^X5&!^1Zi&N0t9PT_ydG$ZZ1T3!!*8jx}g}Z`P2=AAE8PA66Q~9
z{%nMrNX^FOphaumrkh4Fnnm+q@QfzxBQ&1XM0tZHR`Vw|we#aNZ}q@ng663=Vep*h
znkyO;H3_thOw#;S2oIAr<9Wc&YX&JXlcotWK})*kla+Q1aE4|h@nmWe-+}xEO$^z+
zsF@6gi&>g7%GP9S{HZ=DM`P&)Em!mQD4faDOhf?WYeFgCU!eJe>ck5*?uoEeq?!63
zXvG>=D=d^~d?|Wbrg15P+vS?~SHNC{hW|c&hrUwtDIJV2Y1)r~r%IC-24b~lj~nDK
zYj)5^p+@u91k}`O;$vaHPV*~;UF$W|TOiP&d7C!jjhZw{OEqcU`x{uZ<`Fu`T+wvX
z$*V>4#5>T^s(F+T^H(+5C<mF}rg;k0viAAy8iy(HbZEi~(ECnJ_$wfGX^v9bq+7FY
z7A*B>n6>Erbq(uN&~9jsQmo*nM*csT=+!(n4BfXhuTZU2pGHFohkni0U<eFoMtae+
z+nUGdkss8odlul1MzkE@uI5D~<>uS(YfN1b9MY_#MdpDfObg-&`imhQ)%;unFs9i<
z*IULlWwgjlXt*>zPil^S1-GX(xfHjY)~u&Wq8ZJ7noAtCbLi%&qn1O(bNjU~g+kzf
zb_;poq`mA2&V$;$kD}4puH8Z<5H8w{XJP)3cEw>3UA42nf%|US>0#J)*E$bF@US-6
z4D5(DoQf+wwC8U?x2HCk&PqqMzrBaf9MeiEfbOL|N3mFMt)m{U`Dopv;kK{#_Dx{N
zwPzcl?1XldHc}_G_Lc-_^V4360P3&3LEG*C?UQAY2-IFu!;4eeYcudENV|x(>%rQo
zeh7qUOYZ}OYlnF7K0@11p~lnNffvCUsXahJpeSwfDrkw;UZ9yNMw|UMz!`1gqcDF~
z>)8e@P8(^bDJ@=`77dV~4WOe$vUZH3<0;z3Kf#$)?U!^~Kd-%dA3aRddb|mP>DmR9
zEXvUCrel7l_Tj(Kc0qggJPcmcE~m#MOS_%}W!c&j^p%1f?a`f}<!aOXLCe#Aei1tJ
zwLxOK6;PmkjLPy0wQqa?P^5jO5GIPXYe=F*TTZvaOSL~$z{4`Fi#tHMHo70271~ww
z1XgPIC4=RXc4ZX=s<d<Hm|m^zeI2yR+EOaguhG8q3Rr5j<5XKxr(Hb+pX#;D8rpw0
zX#b(DYNK|wBS4dOBc1)5weL}G;EJ}M0c|bXA%9@4T3@O+y{diHgl@NKf1~I5nij7u
zHcMLX6EM-Ctym9Qr}lr8(d^Q$u!5yq>otjf_Go1kF}bewoDY^8+W5z3;r+X*wSR)v
zUhPym)ZEgpIfkzFX}_W%Qor_%H^4fe{eiY3x3vrC>oJ4ccNbx}?`UI|z~Ei&u6|(m
zw8zVV-PbOo5gpPpX#IMit?Y)s!`kd;0Um0frK8%2_K6Q+Z(N&R0L(t2O{J~Dr1slW
z08`ooADEcdeoYlJGumA*L#c!A4QDhu>UL8?cE4`LB6xT}_XI7tPP#eazz*tOxC?P-
z-S#bT+eP=<esCVr{W6Y5SKSqQF5Gk*>B73ZF0Bp%hjmObR3EYHa(e(hbbtH^2~S<&
zXW%)iGgiaJW4eXAVb@FNLvy#c?y=ut&`0MUjvo5zR#MXRxb8JtT~6p~Xd*wU8=HeZ
z`RVr3GUl&4ya+6(bONf73DG@6g%qK><+Qa8(@ma%>TsRiizbr@-Fd2xI<1>Ub(E31
z9W?nx>7pot9<6)t7EHwGexrQy8Qmp{)ST7TP>?-VH%6~-obKdV(BgGr^WbQLPRa*3
zr`uEt6Nx&>I5?AZf$PDNtmEXu!xUX9rFBzvxppad&g*`79Ia`(<@9u?>jJ5eF+=y|
z71+(xZTK1vU(kI(N6d@5_Gb8$r8834G+Wob6mmJbqvdGK)$v!MF;DmKSv2PBT#i9Y
zf$psm&<b@yJTw;RUZl`-vF^o1aJxkJ-5V5@FVz)OqQ6WR`8MRsb>4mOqC&UgeRQ-^
zCy;=4Nq2=3*HyZj6pVAVZcqSlS(j{tYc;w@s5G=zcVRmO>U2M-p`~88;}vLW&<)Vb
z(Wo<0kh@9O&VyXD&UFrGS9B2p6cKCDiPyr@R-Ncu5Ic0cr(vl}mzNBs-8x@K(0X*g
z(R*}VmqEv|8@k$AFmY4oMZ3aY-2*AQc1!p8IB0!3o&cP8b(OKua$n~}PyUdu<t_vs
z=(Z$*Wkl!Uf-a5f#u4<ztpJ@5Z7{}lt8(D!gzlytJd?V22I0(<PUH*Pv~DTwuxE5t
zG-*5Ny=X`r^|^9j`}Nfnoj9QHS_uIseL*LN<e+|gGQ4osFRTG@(MM4=${~FS9pPQ|
z$LX-)rdQIvb-TNM6J?hV>s3maKcYWEc?S=@@FBE$>X%ZD$x;2Q>(F>ipU?u}rJqF)
zgtvY#Wq^J3yDHJ>t6xv&q2v1e`RMNneWnQFC-uGW!-Su{g098*>$9k50s6vE;ZvZ#
zE*ADq+4XgkkO<PBu7{;y{TFv37@{B3LushKdj~+6e()zWhU)|WJ9OyRtAL%>e-eWs
zjnuo8K|D(DJQt18`eGh*$LL>Li;kYr+rI`ltKaxM9F5iQp<5Sm`gfMXnRxw1dbJbu
z_WSGL)H(g6H{=ub{cF&gq@PV2z+`<-7R;yUV`4!|)&IN-wDWrXdC=1Ib1BQ4uJ1R%
ziwwP6Ca_F>;nx_13;HsO>}Koz`2ackRXae-)rYd7B~RbWfIz-}qYHXppucW+15cs;
z937&I^yxo<r&xc{0lg^ESAGsqs=xLU8q4%=J_Jj-e&SPjQK8>KU-7The?^7(m-K2X
z^sdsIUxL5Y`l7{<yR3I7tVW+epAM<jD}IM-b^2%gfz|5|FM&XVKIgxOtx<nC6Kb0D
zPuBu8>lf3R=ZfCV1w1YKiQ`bysy~?z^H=rEcCfVROSXV^O|PU2QtkSVY_N3bN0ngd
z)W<Y~)}{ZL(jDFU@6N+ukG{wYayRwWAHlU={nl5(a!ddIGjuDpPoGPH;(mQQoofd4
z+bAV@Tc6$vrGxr%BjoSsBl9s{clC*t!0ze)`V-iFeI?y77}6`Lh~|MlNe}U1{d0Rj
zd#Hc%ItFM&?->p)qx#@^;2hIWlcVGMVv0Ra=u;8Ovd^E?uZf4!DgB~$crmTNDhBI}
zzJ>D84hB7y0y!E|gV4C&prlp&fZ_5<G&&iUKLKqA4Ub`pneS|1{R=N#3>)^L@sJ@B
zi|c$>!-j8R$<6TQaR|5@(kNbg*pO$3mLrB8RKj5QFpRAL>S<Wi4}(VyYv_*LF~fWc
z6L=Y}Q~ip!;SH+R^D)fa!w=(YaG|R{#|<}z!Fke9d<^1#hAnS{#ow?*0$PBffexI3
zhW0doQ-;TBg$^?O_yuUe2A@a>gcyYH!nIJlp{D|^VTSXR6$m%HcNVP?hSk{^%hQIh
zDa#aT==l^N%Ah<AHPME160pP=4g^9?tRZPF?8X^hI{{1ahE)OZH^H!XAz02COcT(V
zXgGNRjwTsee*l(jc<2L`6vOQRh^HCsn~y;--SE6WMkvEDMfbTc8os1MWtO3v>b0{C
z-IR>aG3e+)&Nb}c0xZw)4Gm(xVPX@M78w4_0Ikq)ZZ_nK3^6RQ6dRnVAfm+Z*CF(!
z)DTP4dYPefIXKG=&rsC2!l1F=0<1LX8esR5p_exJRffSNVATfYdtkk6sG9?&H3mmo
zTWbxGMhMgy0w`=-Z_wTW)?heDm$n)Wk(38(G8jJwXS1RA7bv@8sM!Rp#jr65EUkuj
zR{&f!D5$u&&2Ti1;xE?>qFd0`ZfK*!U56oxN*6l~x3~aZhVKtRX}6*GBMe)Qq3nBr
z>xMbMLEwhLk@Cnl4P}&>>@~1B_$h7~+^C~{hUC}L*l*Z(30ejWE#CpVjo%(V4H~|j
z0d~jm_DBC!B^#W0uzSy7q8aAC;ow?yd&ppW4Xh6gy%fwHHgwPm^3bs8Gq8*p;x@wW
zsG&~-xiLd11qsIuom8+nVemDAHfdPGhn6Wrel)OY!w?<0W(;XmI^keE-vMO@j8B)*
z7x<lw+ruG$(8!}yx3h7s8munHH$Db-$hfluUbq^Wl&5hsesdnf?QV>wneDK#oNiVf
zG5$jpHXg>byTCk+!L-XdYHS>UmSe_yj^Ok%E~gx`w{hAZI(>|Pz6>qC#>+!su^%@s
zp=tJnanCa_aniV$@{WGS-`#-u8#mKb7+|dV8;yZRoa^yA8C}mpO^`8)-pyd+Jt0^^
zj1`nu4K=R%7A#@L$ElJi+<5p0n2#|2L@(88;~c7rj5MB$gLsrNfp#*{cB9KEBw~!?
zRI40oeAWXJamM9eVPxZt`zY9#VEn)ZgLuxkh_2rz8vC9_50i{MA7IJGBl*BmjJ{97
z;CW-=ZZxJDuhWu~Zd|Y)av8>}AHiUzvA-D>E*e{=AdqDYO@TnR(f)S<%;y+WEg<F^
zKZt{1o-veyP=&^V4d5v<ew+fO#YPb&Doc!K4go7Qx>KoFnQ`8KuamKEG2E^&e#L;l
zmBx{;(X~s)zkDEGW%PUv2CI#iS3&NwaUZ=0HO5<`uuyB9Yww1dI^%1XAW?7pHy`p1
z#$CkPX!Ls#t~D8dphRV}v5G2juNd9vDoBeloyMZoxa1?4xN6*x0&Q)^Kg6J2Grqb4
zjqS#zBhcAlWY9g0PUDA6uyh;YE?y&J$iDzLjqjbJTLHaB6O}35GM3~(zRx&F=hl8>
z>k+6KFqTsK@wRa;l{pL=-C7}d$GDjiaCeQr)9Lk|@wzA6zHgk@3T4Aa6HU4gjeF=)
z!idpA`-@TI=wgVE86Qy3#*KBq;fI+p`e~^udD0k6rQK7;qaQ+W+E}m+p3WFcDbVC#
zdZ!IwziHqJczD3{5ryZROu}KX95lK93IS)+o?S5EV!G-M6Gu%JA;2+HLkn2EOw6rd
z@irBnfk7YB-{~;#Ymz(zohMDZkeId4_cOiP19^W_`c~);F#UNC#6Z*A8nB)+t(*WB
zWcno@N`p;&0~$k2PgABb)Z|2afiP2ZH?VM%cLB6Sn5qI{>9ooFCK@A6zfqp%oN51E
zh$otUAHh&2o0eTeUs6n)zel4u)$|;lrO%sIyaY>WraN;1(oJE@p*zELo4yy5X}Wa-
zy|`d{gu-MOO`1Q!l4a_nvYBjC=n2PHkw?p<U~Il=*-Z!(m<BEZ6q*vVV7|!YOq-8l
zQ_!!FD={sqgBPVHXEIb~IvNRDx#@uu#4AjOV9+W}Q~$!yB~#CHFk5AM%LJBc)Bi@%
zc-gdtQYtm3=bnOvS`(jw-F2oUJ596orsjMQ8%$ctc{Q5OP%fp(l>ZcH%_c`W-CQxX
zjR9*hof-sZt0{)g$=6K1w4G}=Rac|2!<4)cES;vP;~1bW(=j)=)@^cr3ZTdIR~j0x
zo6h|M?{Ap;{zl_X(|)@hW6^8+hmO>@OwUo8sLv#z|DDxuTGx%n0n=7T=)P?llfmGi
zsW}n`@0cE=8ppe)RLWl7GijbhNAH{5U%=xyWXhto>49mo3F5=1<B^biXxdL1iV@Sz
z-$5HS&0PvF#!QbrLDfy;rh-cJcfz#k5lBp$zH^58Dbt=AxHfHCN{5CSQ=1lo4(8i$
zqS4XpxE(C}&GMZvc);BH48)zx>nYfM(0r1rNu13wJb370p5=>1H}mXDbi&>Ia|gUQ
zZ2sTpkUL`jIhZO7Jj`47gVodQOvm)2<~czyc+A{Q!Bj7^U=}32&GRV0>tk+w7mdE=
zce>!{ar4MdbnS#WU<|aA=0PfD@H4+<hBN-=m2|&9z})aEK%n_B{r0EKJG>wsWNuyo
z&S3Lp%KO<v%++2{6KcM<6JCUwH@^vo!_Bp4AsAs^a03#j&1WcR9cljf9PCD!C+N9~
zHn-CKtQhlW6cajQUhpkg&YGj&MPsZv;~RJpXWkqP&Uo{=MX-=yjtGJ3bLQ4Om`^m%
zRYG-=-RweTLdoXqv?WL}e@hh+spgj{26o<TUjn6RW{1}R(#>DDqcOvLhmHxE=C}JH
zf5E(p$_6f)H_;|7%Urq?EZOGA>2#B0Zo2?1*Q_<cnLKkd8O%4&dI9DO%<i<`Ei~IV
z(P~&^{(T(s#bzfPK#BSA)96#Fxs~c0%FKa*U@bRqJq>LY=485=Uuk}e?p|FoxBmn4
zm(4W=!0ODbT`*B^UP-~@26HWK3>wW*>tV3T{AdVtHk%6{z}^+}s!h<+Vs@}!2ij`3
z{0tLU%`4xB!8Y?N{TRe+<}<g!({8?70J|OL7^*YqG%wr(HC^WCUBKCGew-quJ?6C(
z7r1T~e*tAT%vlt-xoM7A3@>`kUcbWpE%TBuA<$=DbQ+-FymJbi1Lhe|J6ybNewFS=
z4w{#yz>7QPmVGdI*L-L_EZsAI^Eg=Un~Ui}%8)sOrkw}oGnXMhY}VxfduYxH1~y{;
ztrfaQ%_<5(kC{!+gEnp+nt-wia~1_IC(X+rhlMF~4h4~>&C~z=KiL^`C#6;#EZgbR
zf{qqdFZ|wbVNgK(prz?iXmhrFvIxM%GLPbrhb+HVf#z!YA^^b6;><$h5lb>{13fI$
z6l(Oe1oVUEW%+_0d2h=#x|i$&ag3<1B`Xrjj$6V<>2}KrOH4e7{+6$4!y90UoB|eT
zaii(ul*NzYCqb4AN`PR?-WQ-d#4?)>6rmO_?H|J|`IN2+w|LRJ8DSAo=-{*^XAM{)
zEgPwtIm(iK5m>aP(hMyz7M%>7XDmT-^cr6`jlT?~v6gze@DOK_UWa_VrHS6L1k25Q
z=sstOZUvTTu|E%ONfs|ENKdvzL_;pc(oN@~RLk$n@H3yc+)ak1G)oh$o9UJrib!Qx
zdQD)-w7mZhlwGjMDM)_NGMo12S$4}z96Fk9>05}_9E-dg61kR-dI9n*alQcgmTf|S
z0*ez(CWV$7ssbpo?D9fmv1O(Ru9aA>-$Y}nMfNJXR%V%^<)qwV7XwsSr2n1yE!!!U
zbjh-wYL==jO~Ig5TkJIy?7M9Fq79(Nl0?_=YAuh3fmmm8`2{BGEx}a~Y_JR^p=*s6
zy+0b8Ea5l7(ro#?5wt6oM2Z@>SUOrD-fH1i!<nm=W%S;+St|F!?GDQo+6H!7_RfNb
zU6y3}CRw+|(@vr29*gUXAYQkmRzv=V<%dTw7B?-EJ!tH;93$PgEJc@~rqA*tl^XY3
z_}lQ14p{o=V13*2G38kXEk&VFcE=(=fyTR*wG>XgXGxO7nfsQVnE*qUaQf!)1IvB-
zj@Gc{v+e)Yky!MUqZ_d#(XupZ38!uMm?ix%z_?{UMLH)e%Wp$)(lXHk&M8X<J*(4}
z$DBZ$v0S9hj)N7}@%~unFMz-MtqGJ)J7B#@ClDuV5{<<{YwHczb+*1m2V)oO`fGH%
z<&c#d152*fJ8we5&H6_oi0;;BXqr82RZ^Jjh;<Wv_|n6gMP)ahRx#zlk6K@;hTUUU
z|5L!ctio4d$=hn6ScQ+(k3wL+))V7sJZ{~c1I`mx530aDX>I%p&iGlM!STR8-{0y>
zQ$&EZbpjHB))Bgzd&>IdYcLpOeWx2(uyqp^orhRwlF%4xJsAdVVOFn`P!n!_xd<$g
z*3}fwh_Xi0**)6&E&bYOt=*?Vi?t@r0*JHDraADOHH237MC&RF64;ZhSriLSwu<O%
znPPo~rnFS6v>48$TTA*dG8tAOh4nJ6NmS!?!J1Fy6&I~qO3-9kGik?{Z5^U&lpJf$
ze^s_tcbZ@Gtk)#4lyBWh)yxIfXYWEwp;b;vpCaq?o4`_Rw^p@+SYmyX0==cy$NvVg
z%$jiny34JHE<nD*>OzlDrFF3!v`f}@s^G1%3TVBrwmvTb?Xva5LG-@HT1e5zTC39|
zaHh^W{3BTEt#8pc8yl=8e)uUGtqUlo(`5Cbi|Wl*d)`B|Ua@}vKS;D#6}2F?TK^$W
zuUh@HA=qZ^r_IMT>+!7s?bfUGTy<FG5ukNjBSPSPk5xcx<8|w6Z$Rk{YpWXIruFV|
zc;9Q4({bpQHRKaC_E|SkOtjy6gR+1F*7xl+ZQZt39{?D%a>mi^JJv}xB<@<H%i!8Q
zYqvM--nS<F082yGtzvLKu=-KHW7xWzXb-J9H0h4u(Sg!Y>&!-ok6BH=;2gKcMu0Y9
z9r+%rC#@lOp=HV%tApxk>+mzQS9G+6c7k=k?NTGa0bAo5=yta4??6XgY=3j0^pLGF
z7!s~F&$ZC)X8ZCCXzn%vg|ZIYw$jGth|Nd^Tpl*>CjmTdhwh^Bs7*nczGJp$spinj
z_P^ioD|_1x(&Y&s+pBNV`{!$0SOeDMw)bc;K4IJOJHSbsou+U<+lURo-*&nS22a`k
zq&#Vmt&wi~2ipRuOew_n3!TbBZCnbmgxLljM@PeLY%>HRY`&j><+N=e7A%oA>zn9c
zl&!56&P3Z@%A`0(jE%7dt!HdkS3>@*t=0=5*7gN$L*r~;tcIm{8!rw@6Ktr?zzbwM
z&Vq-DwofUTlVnSs24}KOL!0*$8`lvmskY!K$ep+0Za0=ATj&Fbr`ui%L1TvPeX2Fi
zv<*=_-G0GVM5(Wfwq<i+H_NvEIC!#cu}yF|$JR&(gIwF=^dRTiMvtH|-&XGoP+${(
z2Q`H@>mWK>WP2q6oW-^b87!69vMvHEwOyk$c$sZg8&sFuhBcsFvMrz>?qyp>Hgwk5
zZBBG`tk(7y?SkuUx4(m6y{$_M6AiXCf1t6^=CU6WO|}<aL1VLR>L&cYVmlxO?W%24
z0|eS^KdgWk*KFey4`{cw(V@G;#;1@)r>&S0t6jF0YOr+MPJIq7J+_h&{4m#T_LFpB
zw%0aD>(MRSyR@zAvz^gF;<oM0L!b@XdMH(Q$7cFJN7o&n^VP*sS~_&1t<r^7t2&G-
zEgk4?wd&b>@BN_FdO{*YB0E6_*%Bd<AtDl)vV$y%Y)Obnkc0@b-tT$;I-hgzIp1^c
zeSYKKbI$!eZa^E_cAet!_qI*@f0^yJmaic>vh4~L#y;Hk`fQ*)+V<6LcsRE0&l2>F
zZ|kA3(ZsgXYJlxw{K){yUWV&FIOEKC&e2ZSI)ilybLqyoM1`jAj9G5rJQ*kN!Wl0{
zX&XcjFe;yhU0=rU!GQ5&{PYS8`ZIpIhrS@jjd_p^X2@Ow_CZDnJ#9l6Ln`!zGS=P%
zSQz8$y&y*!`=}~Ef^mQ@ok+&?A1RIz!*Kr{Y%C*W9N2M;;+Ysl0%Lg{oH@=I<AWqJ
zQmFPeiBU+$Vv-rV=nEC67)2i7(invn=%q8hq6hhD#;Qe7$Yk7m3Vml8zkULe#pt+$
zIm}_i<U;Q}<4MZl<T7-jl*cY$#H52QWHi467mFC%XvtT?I6?9BQU*H=&Xh4akn@^R
z$!MYj0QHP@HjLs5<4bzVH!vD$2h+$nNr$$sGV+7a*ut3mC+xN|CMmwv#^`m2LOa9d
zI8ZtmUw;gLuQ6U~p!H`bgXasji!rH#rEZ2i1Nzq)*Zzk28;twT;CdJyl*sC3tSAR}
zi}8m6l6{Qn>tVN_p|Jw=HY3{u!@kQ<Jc~gLFdF`Z-9g6Y^MD>=+-iryJ%)u!7Vk55
zE`;6)V><1)91j`a4+8WN<E9hz#~3yAea3M{1{Ve=7|*?hQ8+PQy9C8OOt<&o(_SW@
zk|@s1ALv4KVb0uuVY@Qp==hKu^Idw;yEFZ1gdR+7I>7cb^S^?gC)1aLPhQNxLm&s3
zhZjNJ+rfNY1c!Z?{Zs_x%dGeWUidNlRzb#}iNB1;<C5uM0Va@n?HM!%F<o2WS}-&D
zB<vn!@`NCVn155c^DuMw%jgSXy6=NzIP<mlL5?t+YGM8;^ZCOVZxnO=04zi^2cLsp
z4AT+y4m>@^oU##?;+eMspr61DRsrn<Gwd$<PBK?epf-v5=L*22Fncz`?^LFS)~{(y
z4Q16bnD0_q{u!qB8=zz|J?ZIlj@dv(nc2+8N1>3zoK_BzJmwq<#N{(1euFaw%n8ST
z7}^D<Q#i1TnJ?1gy@Y8gg=i^rtP)<7F$ZU(v7Gs)2F_G4pEUrjl9@!ecop+f7%W|6
zIxmCBC8qovfL&(3{};TdVcw=VRV{Oe54@;jZln^3dghZ)f?Q$#`4=P`m}`{|C^j<3
z_CmCY*%AgXnwhOrpx?rrxfNctGIJ?k(#Et=1h1VLMO(EFW(egguQ6>K;7lh|mI4!9
z%(?AQ=w^n{c&{_Bc!Atx8mKV6m-)<JuyBicnNCjMW<F<t**i@64XWe1%Pgj1{Q;&k
zEei*kFVlNyh<S+WlkPFa??UlD)As?q7-r^dM&ko!^&BXSFn6p1dB|M49pn)+f@<j=
zGh^wKFr&<RO014C>&HRHnM<SK{RFdzlBbi*KdGe0iFKYk1NYw^R#yuKvzHY?Pbg=W
zCuPT6SXs1{*vG<}6jwJZg{IAo_001?b7u{gK*WRf1Rc`Z&sx6$lAf$6U!ZugcxHHU
zfc5%%NP4qsr(rBUEFW+5`LfQI!8JdYV>XCCtD^~+jsR9+6J!Ee8QIVXVwHac63l9g
z1I$5|g;I-$ShFcna+vkXE0}~3R&hM+hO)l<4=`b@P8$@$S;L1hGe=mLnIK15tLVOs
zU^UYj??~3`w4RD$Wm<t5%`(!?HimUK1zfCy)qf0Z9IHeF6USJG--d~J)>(RNC9vkw
z8x#NiwG9RnS=}$7@dPX9DjH9+u6zXSBvt?&p-g5?qc3@!Vl~o>K7}=PIZ#qr5_*B8
zv0k7pS2}CID^Sj`GU(-!$(pc$oMkzhqX3h|I=&U;9BV^1+|OpUk*7H<tgi61X03f5
z1I=Z{(T$hK3do0KK5LZ&{uZ!`(*Rn?+Dm)sB393Ih+JS*X8@&`_4xqQOISHn<y6XA
zL@}W<R`mq>%2{<(3RJ;TI`*QolC_$Sd{?n#sUR0wZdGW!#5%`?-OH>pI!Im3`i@FI
zYFJkKDQj8Ve#X%1SU$85t7i#n(0GM4O8eag)&wO{8d)XlL9Vi9Ek|DyYxfd>HM7=G
zaKD8$g+h0&EH4kLI_hBU(nIDN%X=kcI$5vKDflkd?@z$fZq|>7VB$LKBg)j@VAYNQ
zw1?G1QM#L~cV?omm*wOPv|B7=C>r}%t#ozwv(8iE{5I<gI^uALl}6#JyR27j;09QY
z^!dI)ma_}J|AtuaQheYZ>p#kc-e(;-h0zbQ68+%X1J)H<`;4$$I^f|$RwI@4JYwyj
z<mqG9Q?$JqWp!y_X^f@V2EB2Xcn!=?u%281GRdk<goqP+4gGd|*loV>elOcjzqvD;
z{VToyT-b6d+TF)~V->Jn+3IT;g&W(G&c(R1*HFOLgWW_AvHk4ZV(5FaU2cPTu{|@P
zaDaWxAC|n?&)x)z5BtLnX!K?KQI&-syN%9}__HOw5D8$bHlQ((y*3FVLG1580;VIF
z{nA==9%S=qzk7(?NktQf*+pwH7a?pR7h?)#A2<k+FgDWzCc@eCC~JCzJ(prTN7-7c
z8;xL>QZaWV`zuO<M6vg80T<2I(c>zHojVOAmOa%I7UI}5`vG>0Eu9IJ;|})lW|&B1
zf3yOvC)jUz!M9}gA2TuRQ*6)Wa5#lMPHV+Xc0mM0&as2$116iDOPQ4%_O)D)^K7qo
z(U{AA>J5-QcIJD)%x70o47q?^PDf1(**B_yd4avS99%JbdpSHTVLNu8gnlWTIgZXU
zb{oaq%h{j)46c%$It<Y&_7QqXTx4ez!Tcrm<yQ1vW`7<F_p8}b%J$T-i$90kwQQX;
z23p5<GNP}ZUAGY?uCSY(q0qqINQv)8cI=1XuCkdg0IZ3vb9jMmW}E+ni59k`81A>S
z&vb)pW2>k%uATiMtrt4j>Ii^dV=tr_bSGOxRR>*c;aaG7v%^oq(slMqS~}fei)b_1
z!#)@Zy_@VBDv|DGKk+-bezqGWPj9p9V<CBmy}f~+B6rz$qT$;BJ24$-gY51xa6{|_
z%7@)!pLi1@_t}D#_+f|HA(znjfQ@i2?g}<<I(&M_4qXQB5qncBrt&fS)W?{FQTEo^
zXdGk5_n~o|Ejj>{3AVp0$Rs<S)SWm%-#>->&za*v2@e;}blRfs<IJYFxGP8cESz!U
zRJFl`JLiBBqwwJDp8?7JoXx8-3Qtbn5?J!$6j4s)07oz##G6yM26{dmA4;YAa#&P)
z;m7%WF4X-wt4E+0!1;)FUV)rE)WAAs1aZcVkO}5&pu6KBXNv@ihd38kL*p>#1G@A=
zI9I~~8p_ep4;#kWL;I3&&L}M)BRIZP;TFkxPYb;$PVEhV#d2bHfW&d0p)&@@IJ>E;
z<T$7K7(@~|y9LlY!KuCpXh$;Vsd}`Y;yg(oLP+6=LNKOu&JlNLoaWr81#<=`?>-D>
za$a}}md<kaJ_r3Q&Y9m};v9!Z+k|XR_!^*`=g8hdUoK}i9ca$ue9pxn3OMsxpkByX
zvjmt$90~or7dU<tXf1Yd`sn8><>XyPYZ)g>g4S}*>LajQ$(h^+u8Ont9VlMp@Mz(A
zi8J{NKreHGDH~YB`It`7)N-6D30cP}Z30+5=VUmzD;!q}0yl7?zCmLX=NT$vY33x-
zBe;e08SS`QIgVAdA!_3U(iWzjGb<Ea2ggoF<F9eLC{@wP384r2El$`BX!LO;6mae5
ztjAt_#%)e4C1~z&bhI%a;J8x;YmhVi2Dl+kLMmqFKIaa7KWK#WEu98>$g$F^`4Q)t
z`Ix829ET$VoueFPDmuqF^Wx#@IHztL+ytkW-szJZ_7`Y$;*QY8wuhVYA{6#=1OEi)
z%AGk1OKx1hb!c?w-lMC;gPVB|>ifBgB6#n~{gslKUfiX(VfO&{4T_n2bEng(fB>#&
z0o{Lr+_cvq8pI8ug8E=?PCGOXaucrr^bmJGosBrm4W^w;2=}`)FcHd){Shz`+!vBD
zPm$d8k3pii1zE5g%~jBPEQb4l_DZqbXX(a?<G#=W3&*&Rq#*I!%xf6gN$yugbpIuB
zXHqIDnQNxx#3}BS&tX1=n@(%gRBkaHu1n*-R073xZuvEUp60420h-DEbq2^;?i$+k
zXK|lPL*F@W^v6KS=FX+6yBzM4AJKT88|VVbT&@cpQOM(p+M$ro{ROoEju{2qZ{I*?
zA@}WJw3c$OP=vUQ`yQRfE$6-#57#QVIaK*v$qkbMt%~bGPo|69GO9(m#I-#I(97JB
za!f)!cWe>Bu5hC-qp^V-{wBa0xxLdc-mBbFy5yU<zc<6fX6|>ClXSFj1Bzgxl^cEz
z8lBvSv{&omX6FH|n=7ItA=kNcOF?dM1$5>2aO)f4#ZB&29!M|uJY~#pal0wCf0w(Q
zkH!J6f^wOI+%4g-G{ikh;kkR<7azdw``q=k!X4(${uz=F9NZ<er5@pavmXW@b63v<
zH_DxN96pV4<2FNMoV)8&piOYC??7ad8%?=3C*D$uSnlCv(n@MCZ#iY`oO$cHz;@w<
z>;l=x8;pX;e%^o4;5>P=Xua*lGt&<90PnLv^m+3ft8T-f53h~Netdb=o^aTY_hB>U
z!k;&|5(W?Q6elq3L%c=tkUY%W90#-zUNRLVhVmvT+!e-469YS(x0ZGUM|k__jO$U}
z)O8p{4DV06^kR9h$w1<GjdbZ9<IQ1$#PeQrbU;6WH=9nR9OwN|2be_Od<Mt~UPCL;
zQh2xMFn%iU?;tpw#!K%(V><5=Vh1x$^D0JQDTC+t4iwJt*7Jap$vff>?6bUk6vxlz
zr5}fS4o}$!?mUl2E9+dIsuK!%y!tQ-_~i3ma|K!fPeP~i3VEmB1S#UpKacTV;N7L-
z=wjY!3bU2)@Cg!Jh&(aHDyn#&)&k}tPf&shy2N{t4@;MMwY0LR<}IM~V-3%Z3k$Wp
zX!<ftBd?6!e^+^SSBNz6@(ol++05Hcr%qaUD>ebGm6tJu&Ng1lGAOq5{-&HrH}7AH
zC12<L`6|c_UULLph`g@%L2mNOP64!+r>8Z@Ena8=)cbgCRBb!JdoCHj<RCA*1}H;3
zE*<{3$9sly3-@_;<`mq2!@QY$F_;Iue`ygh!b_|G%wwL2!at)t-(?_Uyl#qajPt@M
zt~bH^a04b`l6MdL#~E(?Iv1F5=kpSv?!kAXjKO|>wHd^dFKdLl7e7G(kpp~@9(KL?
zcdkOxhrclrm=0gQgrd%V{C}zP%b!0<!Jq*C%W0UBKt7uy!$JHvLjiM;Umpz6L;OA~
zU=H&)xWera{w4|tgz~S_B_GZ&rCQ@7{8B2lJjx%T@IWO0olKxa@!ydGGn)SoMQ>yH
zKD6_Rb?_^n1dZp*=K?!{pNt^OjN|+SdhI9jgEas>!LR=ZjVJm2)$k&TKiL7aWd2WD
z=$+!XEx;&J`ESsQF^#Xafu!@9RAF$MUrmvK48HFNAZPfTeyE@2=LjK^#lNe9`Z>Ns
zvmMyk{5Uxb=J1zOT;V+bkFVf&E<e2#KIQR~>(Q6b-%Sg-0)8XK-U|84=&e-5Po=V~
z3;cY#o{RZE(cZ9x?@zCcQobuiTFdwaw9zf+yHb$8g5S{$kxKsDQxK`*>mAGC{zbkU
zt#&T)KkfqdWquvK%xn2mFT+F~e=Zf&*Yoq~G~gA!kgAIt`0<_SYviA!Q`SxVSW28X
z^X1nu&=!6b?eSXqk#yXnji0j^q@B-^1M?a`kG4~t{D~zH>EhQ^(*Ex{{|#@T-QZ_1
z(b~gb6%J=^@_FsR?&Xgspzjv{s5d10_;Wsk$Zh_%Y3RGdx7A@VclitHsWrg=k{%m_
z{Ez;I$US~KEtK!`>t6yH=I8lB<N<&Gi!eXJ@2B7XA^(jRXW{-E<$wJu6vy}l+o3ql
zkEThO;LrX8+$8@E3Jp04SX5!UM-WC;zIz3>|DfP3=xc*{7ePL~@%9NO52DXia4Qde
zZUWt0D7Xt2rNV6w!4F)B>=zg)(CR7pnqIVCf}(Yl|2rVqbpwjtf*XtBn~&fsC7XQ(
zGpPvAPw?}nApU}CF<=4&J{J6HfdXYCOaux3{vIZR1>HvhdQi|i7mbGmRv}Oh3%=~f
ztcM619-}W*@GS*{!UU@+LKH60egSesaLN;Xj-!H~soXX~Q2PnyBvSBbKTJdkc$Bh>
z7Ie|q7Gng-bg{+?N;bmLI6?3j(2faiY=Go(LG_DJPZYdQJGK*oPqqU4q~JB2ZJLoJ
zNTQ8yvS1OVWKIc^H(@L(0*xzBQUx35042>KI5q;sbb(|uL{AGmdeNC7@S`O88G+(e
zXk-em(UR}1;JgCUmL=HH2DEd6-&R8}TTs>sm>fa#@8~-(SV4iyT){lrGUW*}=wMd9
zp#MX7Um$pj4lEQ3_E0ffks!kZj$RNrlzw1~1%LZOu|%+!&Ks8sF3f=!WdbIx?#cy|
z^eC+m{7qFnl>*BWh*SyYzXS7^1v5SZsTLes3h!$KTW3L}RuKFgNS)yBMo88RlFxx$
z5tKv%r9trgRTyd%SSiDCRj|l02{)Pq?@|d>v%u(z&K5!RE6`{agwr#>P2k!958DN@
z`4~)xU{)v;t_fcM3i_RbK@AkT1Z(N{=@xuXSKxJl%#6kxf_YOR*&|qS8hy6}iqqiw
z1npEN+b`&R6C$?-uk57!`yIh_H~2Onc!!o7gMu~+nG6Y*?*eyEu=N2(cwg|`bzlz*
z7On)$h#;vK`VR#UDB1i-klqcE$ATXz0x>EWSHSHtLBMMenGh`WM&G314~j243A-rE
zyH}Wv$j1z4;iE6<>*g-Pgf&pyC%oVXQCH#f6i9Rz)@Flv2=AxE;r+td6jkvQ7ST)9
zOBne%$N}NdaiIAKn<(|{EBtK{4EhPrK7&Sop@dcj0m7Yhbp;AvWn+NB!g-6p9TfUc
z!u%m&5Sz}ChY8DQHyJJrTnCLKLUklMj|!7M0*MeNWC1ivxR<uQ(ZWw#fE^?Jr5I?j
z!uMM+`Z!@M)hr$perbeyyfB+yPRE5w^iEC`UZcrBAzV5P^^?NihcJjF;r>vlpAw#)
z33W$`(CYydQ-w7&&@|!JU!ajL9Oq+9r-ip@51%2-`Vxv~g+I_HI!oA3$=h?nLlmLS
z7WTaZy&NHfQWUwuBWp31JfR02t;iP^?m%OKaPHeMSST!^IAoEq>n!?;g|E_`TH+9%
zrrWqw=$;0)O!x!kcgux8z5;_4!f6yjuM*CuxZXwKN*TCI!o^l_)xtOEsaGSM_6UyF
z3I|&->^kAM6vwC+{!G<74Z`<Mfiw!AxCY6q!aGzu(IoVv{a>?i8YX{6i_p>eGrVaN
zZmI-!yRb=x&JN+n$KdHT;aw^;=oD_DinA`^+Z4IHF8pFP6mAI5ya~`A;VFvC^$DL`
z2fcn_${qZ^w}nx(n!F?YaXJ+43WLf3HYl8z1+XFE_b-CGC-nOZ<i7B_V+UY{g?|{q
zJ`irGfXs-nnvSVF5{ABofj$<#`vF`V6;><+8590QrzpmS>*Am=Dct`F3_6LvrV{Nv
zqEA=Ci@hRuDg<#BHF{$7E+RJ?;6Bk9rIp=9!&EEcA*%C-$bM1#b9DcCiuQdB)=Q+N
zJ@EmNtsgSpqJ#|~KBA5EVK-mVMoQ!RiF9<(*I%@X9*hB^SE(8%P_(58l0l+OI>{0&
z+I0c09Tbh;f@_CFXWL=-u;|fzG=_*)UBqxhMTXa5FHEGoK=IFT(Pk<cJ0ePc1tyM)
zvMB!$Av$^!ppl}lcc3pyH2f*JXpyxHBu3;~3G7(Wo3sLp6TL+hFULg7=(twA=sXV!
z38Ft1!O`QQUaE&o6gd?_@`NakZvT^_S+qb;5^caz!Z9ORG(bu2Q=;N-D5i*B`x+Xl
zqIYPSlO{5J4$*Ycaf)7@5xq*2m?=8<BP7p?9?-p=Eqa?uDRM+n^b?*JP3r-dFWOg#
zxhN2Aq9UzA(Z+jlyI91h*Jp{yi?$%8q6<+_a8!r{(_pDm^um`gQ6)0bg7>oMwH4s1
zMX>_t*N8qpftjfnb;bhbis&lk?;AuJ>!IHyy5$6sX3@%*Kw3mMXnoQyT9*v<4$-%t
z0PLD*CgpWIMGNo4-!9QFbk3t&G>g`F*Bv6(laRR~y7Lx>)+4Gc0L)EMlP6s46&*=~
zOrK~iB}4i}eapbz7ERj<v^%2Tc|f}>`j%c9gQ64}^oB&!rvUq&D2YPn_eHl?19MnZ
zb_>ot5VeWWHzHd41Hc}NHf=)VBax#e5i*ZO%k`LqQPIT;fR2e?d=r+&MO*v;Iw6X$
zg6O2^2`&1Z#H-CPzejBS3}}1Bt_={`Cw|rs23^G~X)o+19_j{h7w;GVw1+rK0dBvT
zt%Ibecq9dqUgBMJa@$*c)IqB>AMvXcF7p-VvSG<jJTV=e{^Ff<8wZF5R7Vylb}a)5
z64%iUe@MKw3w?*h(`iK$A|9xNLb&(~dL11RU!>CGqhd!4NQ8JsAo?Q3tLZ9<78gE-
z`55sX3RT96^LJ7GOPu)cHRwDh-byd}c=4W4a0%jHmt%y-#XnPIIZ<q*NB9YGJ4NSD
zi`UarIzv30?zl5zPc|Ae#g<zb?^&_%JD_BVZ*pPjocM|7VJTa@ly(w1V%2nT=f&={
zk;xTrWzqUGPy8SdF!^FJg>eeRCr06Sp}1KJFN(xr&jR#<INby0i^XFMh?IzpFG9am
z{D{gE%fw@yaHd>bLK)5q@%%e5Q7KjqLZM1*`Voy6#okn(bV)3YfaGQI`f@Z@i?dK%
z>6lR?{)1`&>%~9P*}^O0h%k8CApYVm8k@vV)5D}$tlbBV7IDsbG`5NlQy#BP+(Y$A
z?c%Se!cwQW;Rbx_62J5^hTSdRd<*2d_}L*y-Vlc!gnEy-Yc>>aidj>E*(?6F5X5my
z{Ft^Nec~A#!1jwv0%88P_`T0C33tTrO@O;A{;>rx17g)rkQ@|mpdIRv_z{8L6Fcm%
zdtV%X3L?W|aSfb#Aik7<z7g^5X^?y<?tK9wkHmk|$Cw_A`L{qu#f4N^Fy;_HZHI|*
zaSkPxCd7ZoqjOTcgeKofvRDk6J(BB};P+n1&lHGomPlwyTqL_1U~r$ri*7YnNp%J6
zx=DI}K%=`PhHfqo$up~AcfVv`D=c_QT)olgB{@xJ1rA6eXnEr;afH*}!%wo>9iaXa
z3w=5vK=SF!XbhCRN89`$$uQ;7gC(2gz&<Ehc?XJzBwl+!4olV=Ktd#=u8<6s)P}&{
zFo}E~B*P{4&!Klj5=;xvqmn16tRq4aa}@qYN?xQFb(CbigHC2eOBNMDG)D4g2w-9*
zgA1U4Ok&yxpW-Ew05m2@-mQShamlRzppYopuEso_lpLM{gGrKQ`A|rf80bi2s$@D9
zprlD2(xWV0;zmE{X^FEHT!th<ijkd>uqe5fDe>*2`|qrTp#W%><X{05&q)sRp^+_l
znFY}t$-ZUa&g1i$kj#|?d;)`ck}Y*GpD$riz_mc~@dWG^N?zy$S0oWqCisG+EE|o*
zl8a6tC6bTnwO=afqySZ!<fT+dmP@Xw>HI^5q%RuYR7w_8qO?j9Py`bfC1ZZDdr88i
zP1a=zgU*#zOAfXJyGAmX*4wp`(mF`iNw!}_U%h09FStg@a*DWImHhetptqz$jFB}<
zUOtb;7Rj@8k+w><QOvDPvJKC3d`CsXc^|DE62G&sbWPI#5E`8l%P*L(Zi#FfrsTTh
z@EA01NMd5qcSjPD3vyR-h*DPrl4VM$4@z=!zzs=4UWAADBp<~=<i6yYn;7q~WLh4;
z9!OYUfQ(39{{O07(ocun9FHaM{sp_ElF!cIXC9NB+Je?`Nj621CM0v72KJ;xQ;fzv
z(v7tB*(-hW6Tmo2f294CtJL!bEV)S+&<QDb=`*e1JfwlofZH#9<_{20scSP_^OFAi
zCb$FA>2$GpOEt75_HjrTQ+(V{deZ{){?d>mkO`0)Dbx}uji;PhkW`TbOTp4LX8?0h
zy7U8>I4s>l*}xE~@c`6ArHfjj7bg8e3Ae+gHHd7@I4bp_5NU+;!)&NWNnfIcShO@W
z08<$wWn4txF{xveqTTV*0n$&9-k@Mbs`Qhiu#_eZ^@n1*bj`Ey;<WT#%Bf^X7fqt^
zjPzT2ux3eLr^LZIY0`Q)lP!&Y8hSa>$g41aUYbmKrCjMD3Jc~*_kIV1`O<|{JX9bx
zbwaODy468z`6B7btFU`PdW7mLN~AMqL8DZ9n_|IbQXK`h%cT+T!;1<j>nJ2IN>eDE
za7p?(y$vr*KTZT!Eq#71z-pwA>AhPkb>V=kla|vivR=Bs9NZP@B*o<#q@V7Fzm3w^
z|ET2hs?;6{(j;xC^j5R<$G4&1B2Bsq7h9zRB{0|~?WK)wyL38jRyw5d6j-|^)zaRh
zQ|f;V<L#0fX{p#PU2_fU*QI9<!o&?}`2_6tNMC*)&^M)wg%IhLDyi?5w0wl_zdq@F
zdT#VfFBQSl+tSZ=qVtaQY6lwcO7oIH2Bi0&g!w^faVB7fr0+ch=soF6H(}|%^deOz
z3`_lcA@V@lnvcE_=_Ebw9!g*L0ryC{{5C`$OUKy&8<kF_(wZ@;<M}DL|Hh>(s;8Wg
zHq$;~QhJd-wd5rGJ`-cwD~qNu&OX_$@6hKe6VuP^CR<{Ih`a2;Ptfy_{qY~r_RD?<
zf{3R~Q4Iwz+3S^X?SQPc3Ff_JKLr5HNA@m##Ku=P&4fNb*)-ayI{alj=_L~&OP>qS
zP+2w=wS~!eH6Y=#Mc<+Ch)jJ7`bTAxzG#e)9s3585Gm`SpE64J*8~O{EjxAvT#T%;
z2+qXHrqXIBPF7FB@?)}rC(#!#`;f|o5@gf1K;*crns#i74p}BGv`@%{N$5N&^ZySn
zCdpo(3ocpq^f`#0k_Ak_e2Q!reYGl8R_=kmG}%Rp1f<KdcfrHcvY+XpnIZe27wTtZ
z*6lEuDO<1v+*w&a9p}lC1yQv6oXkS?McJ}IT21E29A5MYKQH_0F|c!G5(Px_WIuk1
z#(Y^bRcRH-43s`8lnvAVphz~sfyf2f<{<b~EQ_24v{Ko`BVd=wqUrJ~myIui-3po4
zB>F04;j5ugB~yL_g^M!LO8~nho2o_QW!WYNeP^y(W~W7Qjchp;_|?iho`!y%tnf>W
zsX_MkV)Ql25`Ey|RayP>FwrFQQJ}9`_9z&nMHbu+e_Lf!K7<!-vMowTw##big6NPH
zUPj+FnehP{J7rH(c)UyYn-}!DWzQU-`|rAJ1;t-($fnXy(IYec3z(a-{C^?SE7QLO
zzi-Koy#=mMR<II%{W9rhklV5aFGJyu%zFjY@5)}FSnz<Xg_fFwvWG%&L$bc#LGH=^
zp*!Zj%!$_G!?N-Z;Kc*knlEVmIU+0h7BUZIM``KyNEY%I3_g~*`~ricvV=cjX-wu%
z=OxEwA(Vufkj<gG;7QrjHRyAaFQn;mmIs}Lf{UCH36XvBS4<eTyL>vuf<5HF%>vmk
z-#iU^2jtIf1M!x>=t2MP;UkZvMUSt1FO@g?$=6fKm%rRf`?vu4oQ>cD<)aFaAbB!H
zc!T9Zi!ql6<u5FS!9()D)<W{Ie9iz!h<rOG4npNAKS3l+t~?F9;qt#|MSn!T;31~#
zsQi5j8Aiw(>GE(y%HN~Fc9gt}o@~+bd-URqkzbtx5-ZnIhBHp?o{updlYg28(0F;b
z9bBT^<#UYigxr||+b87@P6FkW{5YK%O_2xCi!W8amO_7N@}OKOq{|Daiu<(u&a-ID
zkbAuXN6$Fq)vuy8Q!e*I>sh&&540@#*PjCWoIJP`Bg~eMegG~<zU~i@^YUKW)8@+M
zv=7UZucMFs<jYwy*e#HMNMBVclrQfAc9DGV5qN(=Zpuerv0QK(jV1ETS#YLQ{>?&M
z5M^@5$d^DXmk-iox<cOJ1X3wC(_B=^Pf@l0MfoqsV7FTS679ok<g<8atd%dRqI*Qn
zp9=MQc?8v0T#;wcspYHkuLCiNCb{`}G&akV(!lk~o892WE&1wSV7^bDK!NFg`9cT1
z&Th;1q+t^7$Rkn#dRJa*N8^Ben0DQRa`o>pF(jW(agclR=@-#=U;ZOS@`mL{y<y^k
zyzD3>N95b;;Qd2+54rtFE@eXRv3%?cK#$4?=}7UI{2~<}jmuw&gPxP3>t9-b?okZJ
z!|q;%;Sdy^75X4Fx+u8rAo~;o`b?dx!b1TOH^nh3Y;sqep)i|=qV;`n`xOaPX78!E
zN{Jya#q;!GssoBKN(^}`rqf;QqxhF%QND^d>FMF8*w7D0{T07FNAZ^cg&z+vfr=r@
zl?N%pFM|tK{6}}rLB$<95^_kfhVmDO6;TxG3{kA5=vAnqoGL296r*0?!WDIS;EpJ2
zJ)w70@d|A}BNUsNz>HM1Z$)F2!a~<mw4(e6a50KBJQ^G`Vijd{1H~y)DXw=+F^{4J
z@d{Vk$s{P4-LQLHv5XSviHeg`p?^Ygme%Pf6-<iMBq{pn>5;7Xol0{~DI#g#n4*|Z
zk?>SS;<F%WijHK6q$@uA3XYyuG#!CthGN+_0CSvCd_ifZOhwyrSURg{$^&+mqU<op
zImLo~u$!&;ekovb6g$3z{&~e}`aE;4V*61j<S8x&pfO*uc_ly#6u<5SDO4<I11VA*
zr=9Hu#S_68V6oyU`f^{1V%QsvrHbFE*tg7~;57leTp@TJ8WoCfsdTbZ!K3M}QhZDA
zxXX&&lq0BCxKS>rM)6q#&}tP+r$M1kahsAF^$MqtFqkWf2r4XWP%QMocpDWms`$LB
zm`n9zO^Vb2KsPHwPoS|y@gJ?#S{07gt(fOF#V52nyr%f%9y&V}t^a>ZC?a0~TDKyU
z5{K6n`WN8$4aI_0;CdDAb1;}&3e#6m?^6W1!HYWz4ec%OD(2DGYX%fPf1>Z6;&sZN
z+*f=@r#FTbMiZQQpjdnz{*EaAcD#?yhl-w;!9G$j9l(C95Z{Dvql!3Mc8@7uqngxl
z#gEU!wF!kH8VZw&5US2{QXcvmcK0aLX=AZhc?1E48O};4`sjd*GJYd|7&oPy0+8;?
zg{jc<P^QrX*-LqVN>dLg-M7>G&s(Yc9{N7YI4U&oRr*s{-%lA#Wg7m<mASAKpmfk~
zBT#vi&bS9DpW;G4SjnbZzJtn@6pB8ieEMzl9agTn0?ZJlxfNWflCuOpg(=q!0Xke+
zP>RL~<<MWS5UD(DrthdkDO+X0j#d6fSALul4@BGt%FQ!@9j~mm!?gtE%o*U0EB~QF
z*F@zj^tG%L%H6-g(n;loJs4Axa!wEWl9gJDC!A7#{~JV7lrw1!k*fTPf+}fB89j^A
zl^@K3h11GM^JxE<p_~y97tbmmQfxI#*}fU$J*P~d4P1fpy>BqILggq$35t~ERHt`A
zIWQfK#Y#4%w@Q?$HP9<n4%3fbrmXrHdgaOts!py@22uvAQkm6{zAEMWt{@kcn}r~k
zl=j^)<hZQ-bOp>;E5lQOU89sA1*ug^he56=m(ug5L8)s2Orx^vEE=yW=TK^;N!ddc
zKF!K!FM+fu_s@h+t;*XJnr&0QPxsh0CAS)+Q)xShN$66>{0qr$<yuOPUssOPFL}eE
z^sj_Qk1~gnA~%)$;=uJPE2coSU)f`T;%#O89~kHz<#9?;+*QgbhCQGhSqOzeWi}O(
z4B;n)Yxk7y6)<>T8HUX2j1lEbcQig!nkcjRNSQ^Cvd78}s!kqN2Gfl`rgZ#p7W(7L
zkaHjt$}>A)cT%aMY~o(k9eT$(s}|BT-$j*3=d#^Y969>jRXe9b(nD2n0S3KP*$?38
z0aY~JYTl{^9B_WB^}E6Os~%m)kOEYVXW>(@YU2#_9aO#XIiL@z7!C^kg{po@1{<dO
z`USd5RnuHyFh=FgheoXGHf7c0R4dZK9aDX=10wONp=9`*ppx|i?YJsj1)maC-%*wR
z303?#G@exLrj2fr>YddvpRD?KK15Eb-uV<FDXMi;P?4(ovDX3fX{zdcm`_*PDPnV4
z^$CTIGgQ|s;LfNn(V6^ARdp83pH;o&hrTS;00#=^R1ZV|%~riZ$%P!1Z~+v~tJ>Y+
zZ?5Vo50E^S<vl3mtA0NMe+yMRqQDiYitj<;g6g@aX#ZENdS@1#Dp7qzkIPckLCO!8
zsUB0zzFgJyE@r(#bz~1lQK{N|5YAMoZn!}IqH4|paF<kv7eM{8s@@6M)vCllpkAX&
zRY9Rv6_EmzI@RcIm~T-1SB=I-RVanYuBzTe<lZr(MRkl$vbCz_Q<$zzbx4F!TvJV@
zrFEz3;XU+qseUR2*R49g65Msw8{UAqp<4YB%=fAaC`Eru6++weJ{4mL=IM@V6@~oo
zsw)42-hk?o6n%p#KCPaIR7+on`aM-y2pSy^RBjZl8&Q4n2FOFzhbbVVs`qIbJErP-
z3!>vH=W)2^q~1<r+M_PmioU(-v?7dYpZeGnXmnM3tp&E5`gcl>yQ`fj-sGVkih;;}
zb*V3ipZdEY^!cm#6!!^G_mx5<(4n4kAMOXK&(LKZtUg2Q-h*nVx8eRF^(HD`J*@un
zE<{7ra?%J@|M~)EFHC(t8eF(~i3glHqW<Y~=p9vGpcrz5I&mwUiBt!>gG8xUoda~V
zx+D^PF=`nFgJRWhQw3F=+VRaQm^h~X><T*L)jR(MT7r7uZFC-2f9we_64k#@aO8w~
z@iaJkQtfyWmXg$K=ypn0tEONQPpPvgNS~r!|19)U)h#OYrK#Nm!KJIYbakFq*FOhm
zGSvUnf;*%BFdJZ*>M94-Nt{*BjDi<g>W{);{+wE#2@~1sk}BxusDGzO?RoWi`X{$s
zb;AS{^VGT`z~rm<{ffo{^%T0S3)N9{a<xePs|MT!wKNMN#p<|y;7ZiKLC`Bzf7c3;
zGW8P$Xe?L1xQX(A6>9s}_+={9H~ryEmD;-(G8fga2f>R=>i?(^>#{o8A6%_EhVm_S
zYFCPi)T>{kJH1i8@&FpIsuMSXG^yJ=;dZO~g~dQ=Q~Uh~y>>N6jK)s&@@D|nrCv=3
z;kwnDa;pFAQ7@xS@J;nh7QE<HpZ*G<x75>oA=9U3({s6B{T1EYx7AP42K$b>lD3g|
z)idT}x(3t_=}H(>|2PLf^N{-Im!WrGE$)H&VYM?oFCM6u{|dV!>Lu%;{!ksV2=*SS
zn^0ElnDJQsm})*o)&I>y=a~A$Pk<R$FQ*!$3H2&pSejHjQSi%2^L`5Y_GpUkpmDE8
zNv{QGO>z#1i>81!2KzK`d85x&bM0e*xoJ+*w#Z$R)dzJCO&2|v_iM~s0qv<7$VH>W
zOOwck`2(66(?Gm6FZ1D>k7i~V6n!<1euAi<=9Ne^`fE;n1TH|6@h&6-HQf1V4AQu?
zfD6{teT)e@sQJbZ+#$`I@o?s_Cj2RgglMk51rI|tPo07JFwN_cup6$qa0!kcacKUa
zlU+wO&tHIOgy!Izup6ma=7P>B%>aFNBU-bTs{Ud$uhs!OR<mIPu;VnBGC+=Lc;s5V
zrjedg37Quvtax1WKE3u6H5K%{IHCDg3UX4zC<1hn=7n`YN!Cn0hBK!$j)ga1K1H*e
zYU5Hh4L<`dO{1Iw>~vhlkU6cH6%1!GG%F|&aYmC@k4ebX_~*gWS<T9Cft{t9+m6O_
znlEC}n5{W6A6$;+WlF4`*W99Taju3%YuY@`?r}ipYZwQBS)f_xpk-{KW;Ini6=`BA
z{CYvNV+y!p&Fd6nDbajSk>yg&5(;OQX@V)aP_9X!eR74S=@14}sR^Siuu9|C3(1R`
zO98;Xq+!p)$Z9m(4x+JE<GvJJou-uHy!Dz7uS5Nc#^*i-m>V?K#W2{YDW`ACT-AI-
z1;tI8qHodHtVy6$Y>Q@21V-Pg>G%^|o2KJwD70%1Qpt0N#%Bxku4(Gmz;37J^s_M0
zrHNuey<4-BV#wDuSLyY8L({kydOe!yd~i24V}H~CDD-M}&|><QX7=|m(Wg=FgkrxY
zFbbA#Yu@@Apm#JYzJbVH&C460IG}kH1Ia<nsx4?7(r~G;_nu}Ey>RbqKBvdsux1q&
zmopw{rtgQyh~}qf(DzVNLK})lny1>K{#bL-M(2-4HNVjcdrVVIS>|!gbowCdgy!>K
z0W+x?qH-lC?G`##w?}K+h@rV?(<!I2Px}hhsJLoP-5_pS_jl0ft_>%H9@-*0Ij~>L
z`2hZUYJ2J4^3pPb(Re`HOgFQ)c3=g-96s6=-k3yR?IH^8`e`%hTKCt!O(n4b+D!-%
z%?Q+Pu|On9yN2p)gSB0;aP**dJqsd-w0CJad06`dMfpOsi$}qQY6YnvVcOLrP!HFx
z_z`+Xw8cg!9Mu-Y!a{^rxCZtj9oph$a5zf4fb^razMsLj7%iVNtFhXw*U=ZJE$zc^
zcud<!N8RJKVN`gQpdG#h$>Z8#sx(d1{$@wt32hEtY$vt*nNUcA7ch~mjot`nPH8`&
z&`_Gzo7QpZ+O-seKCN}cwSvvia>(y9+QrUrF;m-l3@~T4fwKUbrTzJ7aObp7+kuv?
z<$Mc;9PLSpWu4c~rSyHicKN3eDbS7#ffQ=zQ!uAkJG&DmO0=95h?Ht?(j{M^eTvGt
zDz%?|2oI~Y3;w^Yx~#31qqADO^A&*BXb0wjG-;ofps`t-90QFO?UiJpwQ2+EpxCC3
zqR2<Pmc0Sk9ooacz|m{kzt)56)XHg9*rnZ1d+=^;Gv%DGYttzDdqaCv4$`Ata~2{u
zwQqbt^`E_3O%KQ|ZSHw=_G$m2>Y;wEr3w1CwR5Nh<BqnGvbJ}%yYImKfOa}vfrHw7
z8qAP3uoR8=wABlNa$mc(1d_wrMIC5-pv{m0WkefEE8J176J3a7+COq2GOiW#sQzq1
z`$H;PC$-O~Lc>Y->@I-r(Xn$en7z6ofB598dzoHGZo1AzP;}QtQ3%{ar@jQTUl&Uc
z8c$u?6qxtYeM~#P1G>1c(deW5aRrF4F6a&#{dBTC{Jj3U;#i;r=nA({{b!)=9=#WW
zbpIWKrC{B$BFG%n6}<`UL%OHG1_{xfrD~~Aoi-jGhUu1_0%*7{jVeu#=-5=z8=>1s
zA>l~f&$PXX(#248F-CVg4kL@zjkJTr=}LG&iPv4&2b2Wel6{yN$8p{K6`+Z_Vo$)F
z&}G~Nm#q6@3G`3t@+k_NqI-(YAEoM26=+P;eJq7Yx=uj1%4yxe34mtke(Q$h8C~vO
za9O&YO&H-h-Lz|v%+~FvqhL9@+;t%5b+rj-%+>kPraRA}t6GXt<m<+0-&&w6ZHHo^
zZfFxai*&zr!lw(mCn$PVtlLEI`x2de1^P;LF;oFkrdzlXLo3()N`t7-UH=eZ7j-FP
z@Zyrr|2W8HT?f@QRqNVSP_NMmMNqHREv6t}oz78n8m;xZ4Jzng(Y>(@E;i_LX_45d
zYuF6YtGYMNps!h1L#K0Ebf@XkZPk5h0cq1E%>qoj&OZ?%9Xd`MxNABOIxpO*t7(My
zUAi;Q@UUA~#DSsfI#C}QZ|GL0L!?Jn`~QD7ys1li7y7-rC#`6`rF)0skbSyq??AL)
zR~C-G+d99Q;O^*pyx`Ma-TUDnL%R2CLGI~37ee8_ZqNtjM|989rv0Jr6{`7vq|?3$
z@>sWtYS>40E9kNs(_N;IN=)i1|8W4@N&nj_$n4Q8;=noUgEoP<=>Ltt?CsNkP0qOL
zW9hnb(^vih&RzdLWr;oXGdlsZUtes6f~S5dy@$N?<Fq(DpkFy1n7;Z}3QqdzhdQC)
zuiyC#NPzx3I`AH-?>kEI&mjGBJz#?MVPC-DLH)-!Vd;>5gx1Z6^#|!;5~ANnPw7zo
ziaihs(?71mT!ibFxWnKP{iDC2epLVJ0}MMt@9`8ABK5C!!ETiPTS_%V>zS)Tj_I|O
z1dZ1(Zi8Neeh+e}_#ZDli-Ko~`sWIve?s3&F^iLWV?G*_^nsLYPS*DagPhWzI}VW)
z{k0rmr|JVbfR?6L?1RB{y`>K1w4Of$Btw7wI7H6qTWI&2sjqq(>Sy(7RCSc4SL}j?
zbNbRr%#$NqFYp4*(VwT4#d&>xAQW@;{?CEr=^vkh!F>G{7Div7&w3IAE!3}_jm9E<
zpB#D@^l7w}DAuP);BSe336(OG>fc%pgJpW(Cos@*y|x;pLcf#+$x8jkR!COqr4-D$
z=+H0l0NN#eNEXOty`3Jc)%sKPOsUatqMS;teq}C5oqiuZZ|e2y=fIgO`VEB`XoKFC
z4X#mdr|A4uebOp$O?p>yv{^qV9C|JK)3lgv)i=Ebkv4r@GaB3V-%;eDL+`jsQNC;X
z$G72kr+%2SWL<g*Jq2#)Td4%2N1ypJ`flo%i!i2M{SR!2+|u7)fWAIGzW|{9`T?po
zyshVcg}yub*|iwxUHxYioE*?|^%&BizK+hb4e6gAg~C1k>u;g)zJ9G^E*u`w`@I6u
zhx)In$oY}}B88+L>%+<XsJ@BLXO8L1spw){UrLoL6MCm5ket*{J`G2m4664bvd578
z2_|T-p)3g^&W2k^Xw7gje0UamZU)KwXmmF?LZIMbD5v4>H+cKd{pV@e$%BlSA!IAO
zIAHkf31E90Y+r)&F<f{WFusN-Iq=EPu!Rc6{S80j(wz}th@S_TK!dynB0&bG1R}wP
zZ>Ph=LBnh%Bo7(pR-x~(p?o0}LJWD+AQEcGoeg_ohF|B=_b0*)pS*@?J7Oq%9%zw<
z6#6(!l)=6XiqQr$g%@HB4J8nXHO%h8bj2B@&2ame;SjC9;|-r}gGhoQelA3g8~#m!
zdZHnoi^da%8hVJFG-OlKHpvh~QG!zjJtfdm40Euxbj(OKWYFp^%}}BMcDlizN@GtO
zHaS5w!*IM7<c#413qUgsv&LcKtRXlTBg`@c{su0`@XIYYdfxC}1sZb=-#UXUFa&cz
z3Jrs+09|Bgr^@9E25A>86dRsd0<Of6Me8C*so`M|Xqh2|iy106G+uzE3d0y>vMLR`
zDb`VCczqtwE*g^QBEMu9r9J6o!<Vs8s5bE3;ct!MpI>3V*5J1u*mZ_^&!Vs1Q2RRi
zt{9||0BbP3cMT|whMRNHch$gu6BE?rFwCU$f6a#B4H!&|VeTAYw;GPq3a-ttXCoYL
zH_Y4)yB&sBD&)Fm2%^wXry-J-&s_$62l~1VKko&(Zt&X$^F4-$zo2*1u!bI?y@szA
zLGPB~6MC8U8BQr6(r<|CL*s3OqrVibcMQv3hBtQ&Z4^ZsFo-A}FlhLhj+6`;zA1#r
zJ;U$YK<*oiM1~DjT6pomkhc|s88IkN0`#Hb_YrW948FAQd~Dc2<x!)CLj$lhW;mim
z<GA5_f6UW_;XoyzCk=THCOmaAUh+cg9%G#=ME4rMpsc#HG0X@V7o&q#{rilZzhKbS
zIJX*oZpPn!2XQw(l?G4`V`&(;{l@t(V%9v3uhMGL%Q&AFr3Z{jJ|N!4`b>!U81-~L
z`5G;hr|~m>TTk&9f8%=;?+q|UPy#N{xGEN)LB{i57-+EZPbzRYXnd3ejYCFjEwB$8
zLj&PVi190m8iyLKA#gOzn0F0&;l@;o;2kmMehs~&##8$s8DU&O(dtO!=X)@}QAPtD
zafmiP%b@jVj4{p%(O6^BLy$P*%UuvXW{jtYXS^}&2Y@CR<&<$hZoGXBiiyU*YtVSY
zc!=JVCylOO0yN1e(SalzcMSvOlrhx>eJRF|4&fI`HO`@|YnpN1LqMk+w{&2*XN>>h
zUGA8XY5ajI&dwV5I-@ho_!5Pd&Kd9DfJU})1qCN_jDHVepy!QSSE4c3c#QTnc}5Gx
z1@evK|H7F9qjeRyLgS~j)GRWtrN!(8<HATt78^4{p<ZIVLZ4+QHF~&!D>ELVRDq-1
zc$;Dt6-MJnaH`T65(rXd%%K40MdO=v%=(gX%On~v8$(_NsWuk=22x{m6vAMw@!}qs
zs55>*htungJG5xLVzg0pSA#L41O^+8Q;(zXs*y#{^CqKDIOed~_~d;wwm6I<eqdXT
zUy~PYM(0M5cB797E_N6jD4lT4sQv?<b{fwdfKOe<jlTi3+jwz1xa-F4@esLTbfJww
zkFnkreK(EEsRFsz`0^2m+%ozmL!{66^e&+E8^hAT-8O#U2Say^j@%zG`FD+XE8y^e
zaW$<828}0cV1CFr^c;T5d&ax8jJ<Ch>;>AeQA&p@9vC~i0W)IkVnX4ev1<-Q9vP=m
zKJ2kEhYnnf8n1LiVa!-YVcT)zN6TPg!sz4%$w}jj6bW}SZE{4zjXkF4eg)cIQ`kS~
zbT*x#xUGvRj+U`*rodE)xSL|=sp(-ls)E1!O;=ptg{R5&Pk88MS~wStKBk|j*vi-R
z6Fn{cOqEo-6li+<1AGcH%~=Y}VAE%p(Rk3bK@D=qbm@!(t%pr*w1^Kexy{31LQOBz
zVX81w+e;wfrn5s3Jz_Ha1CgVqNh*SkGW|^n|7g=$XNbg@4pXUTtSKe}T%2i)>Ku-l
z8h(bzannOu@Fto*SPYaCCe9l4C7XEH(Rj+Vu6qjZzZBCfGqBT5Z8xER+O&QV&@xQg
z1jw8*3242YX<9?^-m|970}#nFO{WCFIg>AyWo4V*Ux2<G(_uP&b>5W4!X)IHrhkgY
z0#l3}b_-1{MVP!I(-ul*l$d(AfRvi@u1vxGS7v&aLc<lN8?>{oG)bLdx61T!8}u)l
zKA`WrUNZU7Ht@2knjSmVrb*hN)|ft_ono!&7d>XJ&a|G3#(ERi052L$zih&9*J#@H
z5k#(<=J5d5WP$-)`KHqpHfk}Y--Di`)%46KVB1WuRzs%Ul(HNn>@X!giN-Ed`8P1%
zZMs*6xx8+wjD&|bOyAHI*kgKo6x>Zyf)FCNOdrxZq0dy71oeJX%Q_6{w&?|0XWTI*
zDA9P=w9^N!4VdoY*vE`PQ#3_Nha4s$U03%^nRW2yzG*B1+_33gGh`l^9#Euc#H61K
z?x86&9cYhD5!g1*7&Y<enC6(Nm5O=BO((t4IAMBcHe8!DF@J@ElX>`U__W7tu%U6U
z*{}=h&Sq;6h>LlWZqa>ahbMhg!_{0wZ(}!e4s9OX&GnR#^)!za!@QT7MF)Tmm=AOS
z#@C!j?_@vo@x!p|Z(c<^@&L1tDs2MIQHwCpAoKSIaEHuQbhhuXxvmWZ4KWu`<Ra9(
zXArK1nbVFzJ=`4QpqkhtX48MrIBM?DLL<VQ8xOmY<`auxDaw2z3qD1g-}xLQ#=K`7
zB-X5sg?^m*`V62QGe4qw%6RjdFnE|?_FsV!o-l8x%=byNJ`v`V%>P+HlFb(+z&vH1
zOA*Hu^LUQ~G~MjI7aFI{ZP|dyF#kjqqi4--^cu`EPw#;<=gdoAfx&F^A5;vNV@_qk
z-}C0FdVuDdmo0;Oo_UPYF8SuIiSVMpYzRhQp?QlBxFWOpMW|mee?{@0VsivNY)j0m
zZqWX()O_uEm?$&PI|%)9vo{-KsxWIP=1^(g@H?=p%$*9LT{KT@0@@|BburK`o4@ad
zWVJbj_Cq!109vQlns@wzzANScT8lTBx825A8qEO|m%C~Xv7oWZyxaql&F1%fX5s#8
zF`xPb8m;Da6mM!Xzi9$myLmcIcZYdz1sboJ<LC*|Y5ukWie2WHC==XmK0rrruA77D
zVRFO#%{oZ-nA57k-8Anj1=nkSr4oa<Wv+e>!|pRL?8mVC&3KLA<}h!d$dcoZxjPM_
zcg>4tV!8*+7wO43WZwKFI`5ftsW|1nIb}0ohRxrnfjls4Xrnq}UO<&L56z(~q43DO
zhwiaav(W@HX6~SM;JEpPC!jE4UP<|uNpsSZFyv%;Y7H9qSgyVaJ!gldiykH}7DqNZ
z_gOx0ffufpw|qg|EWrzaw%_thAUID;tOb%@mJV9-9kBdGxkYbFDI1gEW0^h-gT9t?
zH__*3>HZ#l{+8FCL1Tbri~`z$mM1925oF<>0A{e|CHkP`L5pJtRqG$Jd_%Q|hb;|s
zbS}gaQ;p70OFSK>3bV{Eho|9|vX%Hnj#&Oa4RX{{8U&vrES`JdQ>0}951>(&#qUBr
z+R{Z4ml#XkW}w7c{-V<^ah8m9pd7Q*r-H;=ri?=*!E(p(Axs>%STf<_NlOeRZ<8!L
zb^|-v(lHg>Da%h`;8HB}Y1y7?8KH`^)0Vk6=vJ|WcY!-&@kvKtre&K2=FeJWR3?~Z
zdCL>#&sp4P<(6$3S%=0Pi>@AE=PmvJf#h1|3uzaeXQ_{aiv<=2#WM;m+bHZ?WT`j}
zPcK+jQ`JPVWh$NbD6s@agOpn0KZN-*i|z@K3d;l)=v7*N&VXc<<&C${c+rx~hx#SU
zJG5fFY>A|?R9jxoL1T^O@&bs|T5L`9KPGjSkUzlITfX$cD6Uu{dNGOy%Pz_zG+Itx
zz(ifOq)|+$$@1zn=r>!Qp(?8u%jFz^wpz};2Zc6EY(Gf5<;o+Bx5E-g;o@tS-Bc*o
zX;~qIYh9M7lc0XX;z|$l9?P#dg6)`b(=tjQM7d>gr8<;8OApnE_FFzy!~AVaGwmAg
zSa_6Zxodg-Hy9kStgHt1pv92@&>_p}uOM>I@+O@Wyl-*-3+ls`#ZDj(EKI7NduaLY
zJ`^5VT<9(Q*m91F*+wmQX?f!qvplsHG82}B%Rrm7=;?QIvhFwu^Lwm+GT_=?>+wSn
zb+Oj8L4Th${U}6StyAfZ=Vq1D+Q;4cJMDKptXldM!G7z<v?lhnE}?QEFRPHQ)dSWZ
znjmkhH$9SktczEI_&ThIDJSY@&8Iuo-x|9PG67a+ieU#@b!?0`$hwQ-dcoGZLiiM7
z9cTavwWc2c3A6Tj!|ibEbXSNRv3{}{>PM~BlyQ%+MsEOSq?H+rz9{P!F$_jqL-R4D
zSgVa<QE^tsQ`;eW%<7v5FXF9n-$69NI)iSK<JN>Y^d(v|Dlx(n)`E9{cG7xf2K1Ax
z??%D=DQk!rdMVadUw}xe_1bHg=QQgVpFlF*s`&z7r>%@55XrDUQlsyT)ioJhru8GL
znL2Cz*zqA0v#d{Vhi^I7?k^y7-uhQDNUn7=)ve}P-=GUB-+Ck%iUrm;Y5!PgJ!gS_
zk@YirpkJ{5xCsiy*6)9V-4bh=5ko7rena21D6_sG2Xwjh;crl=uuh?JyGrYLAuy|~
zDNXeLyJ+1ug3e3UKWT+<*}9Up)YaB{+U3+(U%UwYT5FXIl6BT~KLNYm+ClHJE7mD=
zM54j^D%E{ATCM*=<f`>LWv830jHPh2*}9nG+AY>XDo}5=&ZH~1!}`ij^j))V+D+eo
z>9lHTgWhG`-HBQ6wyqsO=XEQCqMA3Xjk_?<J=Tf!FnH4%l?44>>+f$s@|HD}7U6x?
zAzJ(NTR)=@pWU{~|G(z4UTB8hyH@8LKpC*go(CDUdW`{W$XZSr*?U$mME)Ez?pwbK
zh2pSvRx3asSUYDzX2iOQ2J_I$q8;NSYXK!+A6qpPb04*GsWf2BD!c%Zacd}L6(+2W
zN6|QG9U2F5vT0uc${t(kJSgn7t)i!_v#o9m8eMGhG+p~_ffPn@xZ1v>NUMj<O6k1)
zwqNPB<Z1I`qS4FdMfFVwY>TKU+uOEs1f%z{_20u_d~E?~;QVY4=!NNTOY{a8U=uxr
zi9nmO5{*H&`*e^d*yc~K--EVg3o%`XY#)7(#>2L@9UvhN+p4!=Db%JFVAjKIpQ}N_
zZE>^{Iby3S0C&_TS3ohs_6w~>BW))s78PaNc@A8(ZJ2_`F}Cdmn2T6j%rtOuwq@kS
zF`E~ab;R4!>6x8ibGHKJq%A=WF3GlXH&Bvojt3O}Ib~y0Iw8g8{3-0F+SdKQfW>x;
z7B=a&ZT-MLZM#qp?u^ZBfr(7p=4R-fwQZwMEoIrNKStv@+g92XX4|IHlQhS6=PejK
zZ`(=+b8T-Q0?D(@QbQr%_Q6+BFR%qUc0s1l7EJ;5BHJGu(OF^>RiLrdcKH`LQ)c_@
zd)TeC`8UCfDw`jzR4>~0($!sU+msJWHMYtnP^h(iw;L!|Y`;*jufewNZ8SF8?o;vY
zRok<dL7Hrgi@<EQb>4zVyX~J395C2n^ZW~F*KBX4fpprIQf#%$HcJSu+qRAt|JQAE
zmO$}_jnf5#J+_{mAUAF7=ipPXEh!n;w`?NHN%q-nS(w>=+r%x1+_v4U0=Z**%??9%
zZ9lF8=74R24u%cdwy&f2-;gbm7F73aW;*zO-{$oL(1vZdU7`5E_8EnLMr_ZN!O}xp
zH?5l=+0<hok8ST$t>mbUyBOS<ZJ6${aa(;J8YgT;-vMRP*8dGSC;J`B5$v(IQpj+x
z{XXTxob6A(K=m&!_Aeu#?`Hoc00!OdmMu{9u-_426#MOKTw&hR{`!aT(98bYBTVoC
zdnPS^z3nG@(CB0Tb`WU3_E(dk?q|>a33~qas&Q}u_Fw6x7-+vo!Jr`fbF{7rw*RmV
z>Idx~9mMbBIApi~iO$3JPwLScVqY2xPebifjNroTlN3-7x6jRhi6i!h>p+g$7dpXi
zggv4KB9Zp0T);%x$1{NvZSSB|dyL)G4@<Fjfis+mvwu^CK^(JZybAT>_7(>E673bw
z1LcInergh(C+*w*2AgD`a~pG!Y=1ceFe&!cI+#zjuXqzMX?9};29s`oA_^j>?H}dC
zZl=9yD#%&8Xd|4-vUgvF!a2KmHn?oNoB_-nyPYyR=j}%*_nT`s4+1*R?z<C>MRrHW
z{{vO_xfI_nwzCR>R$}j^;7qCg=}XWkv+vsnv~s(G>IN$8^7(M4(mwknMp0$gQJupj
zd+~Q5m+da3S8Wg321je`OOK(k)*eowhkE<hQ_*<Eev=M%HP}y>0oG`L#X(!2tM-3f
zz&6=;+{ENJ+nr?)ZMFMshJKrU4s9IU?G-P9>#)zJyXu<#n-#FsY5$v2xn1_;OYrHs
z{aLDOykTEF1*FGb-iF4T_P;;CAbRcid=l;vdkIw=_1V8U2YZj~f@xHLJ#J?tKxWeZ
zUJT6d-TwP)z}~lg;x;tgw{KuV!*jcmp55Ntr~C!Ui0ywgVoDOXAFG1-Q`=`J(hsx!
z2}+A)ZePC+jpw#&r5Nb>?KSj)#r*BbG|mg#cU#d|u|3@dD9zjRS+xJ_-Cp+p0Q2@Q
z=A(0Tdtw26a^6u(ds4R@842*zXUFdsVDRvc2#Wbd?&zCDW5SNg2yiJo+@FB?b33Mv
z!*0=zhL=D}cbxtNCNA%oLq%ovJHApt#AoOA7hxfE=e$5nQ1s5!&#C@1W#`*;6fI-t
zP&<ZwerFm34wvpcSOyc9cm6~>il&_|J0a4&Q%8j$H+LFeg=>R5qqQ*caOW7UcE)!8
zkEZVci{kp?&CKjB?6R=1GqZ&SqKQ!xTVi4?F&d2;V@*tKu}5PpvBg9sf8zq8NL5fl
zdM^S}q<1W!fMNkb6cmuIVlRN=`<=Y^zR%CI_ug}U=iECpckVss+#ym9W1Q^IlMBwx
zzU%-hJ?$^kOzLAVp_Jw0_9rN<D$u^#8RAj)Nn^ojjI(c&LQ|rBT{Bpd?bnguX?s^%
zm}J<Wq4_4${&XuOvh2U612x(9gHA%Q!2ahHlnU*`TVPYMebQf0f5zT#KibaPOB+DW
z*<V<Lj-IzSqbO5}eG46ND7BwPi4hm=znO`il^N|n=z!h|`?a*rxMZI{6}6Y`pKO6m
zmG%*o=5)n=J3a8%>`P{Y<+}Yp1JG7wpG|(0YWrVS!NMAQmtJtz+TV@`=S_PP3ggw;
z%gHC(Y=5Z|n6362I0TTb3A>mOTH{wSH-pLleS<k23X5u)e-{D2jv4eX5N|VEX;;y}
zI0@*&U1p0Kr6y*l74TabUlEnvOd@6ZykY|Bo#4RgAAz{CPyPam4?8K6`@h=sn|=fO
z;29DWKe<A))VFW#@%v}p$EY_hT>2bj(Gn*pUHq2|#$w5Yp8>nnlfIDs%X(U8u3bl;
z`uP2B8(O!oRH1LXPf|v%@rpHS_A`&jOXk7+ODTN5OiL0f{g?y;_)ajR$d%;JY@>y0
z0JD8GDg&7rlphq#jQf}Tk0DGoxz$6NjgeptW85j_Kb)~4zfA=5g7PsUnXMGoiehe=
zq7=<Y*PsJ2Oq2t96U!7?U^L<wb}qVbl3Ds0u;ZCcQy`GQ46=viiOkwIK%Zh3Q7}G<
z*_8+JWTrQl_FpN?l5e0emHD#>3Qscuu8>b-mM9>R&P3gWiVS86dD$|V`4nKuVpg6-
zWj13?`^6k))ij9bGDFTmeI8>)UZZ?wVh>0Gv$!0bg^ZkDHAT$zUZ4~+@5KV;4AXfM
zEXK3UzI$jq$9#JVMqOjtNbhw<)PPhmd+jk^)yz#w*0{k8D}+Q1(?_{hb<B6PM7+f;
zpfrcu%zC<=>zTiYfiyApltO!tNhYUpD{~nOU1>Yh5drZIM)(}|K43;!L++uG;d+7n
zh;b&t$IK5ssC~kO{Eo_}%;DD{&lrCS>^x^CQbO+wX6GiLy<~n1MCB{yF}<)}Go#*z
zF}+OqV_b?pX8v<@^bHe7IrHzBBXoHkSua}II<ck{-*jh#`zR-XuD?c4k-QIoOh$Ro
z=50Xzs4^93gNM;JXvo*(dK$lgoCy<t9*)+p44(sNVj;zMzYd|p$CH#_Leb=dGtud9
zKAHlwDQjN=VQLKBvEP2&3E62elrTNLVG-(Q6sRHl-H4^M{-4=Z3#RXns?a=Z!7T{S
z-ggGS=R|s9oaSEdM9sXEV*H-}#RSy<uxtQ2_ai?M-B@6_g8zRymj#}m=f}Xfg`OY4
zphbZ{19NczWymgRe2Ds`-n~HhWy5s*UiMWu_?ItegIUHE3VMOBEI$s=RXr}KT0J%!
zYJRPtduHu|NR0WqCMyX1CU~KB{c=it`#pe`1RKU3f`YvZC<EyLGnB6RLFO`j4aJ3V
zqABwb!&APsE7P9^y>3h+t+d>kD<1*EgGqQw=Wjfj^-<vQW@3FI*vMFA!;(kLqwi7q
zm~o@`doPnqnfrarkF=3Ez!nS#ImpiIB28=xeJAt~du0<;xU%+JVX7N@h3)`%_6_-y
zJ=l5HFvgQjyNtmPVpZfpMp92ah%uI(NH5Ab*8F2=I>}C_RZ2WNXAaO3*fctnlgQ2|
zN7^Y?84K(rb~AahlG%ywU`b&oGy*%7^`|BHX;$?SN@?uM2Ix&^HFRz+lT9X<Xck+(
z9W2>wqXu9Z++A`CW*WI|G{IzXo3;ZqoBQVpjLG3HbfPks<9CBKk5f`&K|VK|qK*aJ
zP)eUJ<Q^nJMG@z*6EMY`D`n}O;dU~RJIf8R2Ff{Zz<dat=jzEpQ^Lg`LSIU`oR7hB
zftwHm=!=}G)piuixWRs@-uP><%d~*G%ss4zic0R_WME(6mgT@S#EpK0#5L|7`GBr-
zWdqQ)DsB<Iw5z#ue!#xLttx}28t&43VAgW$=~(4WZX0pdag!)%;1)NQA``c{E=O?I
zb9FRLHE_FTLc<+SZlovfE~oSXY2=z+p{a@cm2SIcZtrQRxW~PrgJ3P(@*2Rja*H0q
z!Zt4C8cOY4D$ULv7$C@Xasi_O+Qm)ufcSlG<QiZ;;2c(??IG9oE#$g634Q775f`u%
z<S{4PYXs{PZsbQ8gr{7t0E3@#7q_7DIroI7<rkd!V+g+FE|QP$6&FR(yVu;o0ATlU
zeb1q=mph$@%0A9f0E&YoX&HvnQF4N|K`D}7pFu8FGX8I1o|c>lK`Bl0&u9pwOBOcM
zX`BqnJ#unqN@jGUHcQeQ553tEKYBi|NJgFj+EvNzYY@C9$u9xtbx9%lXX_;^C@-i%
zGVu~PTP0U~K-wf5Eg{e;@m~y<E=l%4$hk-dv;g{$G&dYJxk?AiVW@}nPpmWXG)iS2
zsP%%+0ew0w)qVj>L-BWPA(103o&u69HNOp#CvBkzHedSkJmd?cJ+u!g#2=Z3iXy2s
z-JQi!Z87wokuD~C&q+gv!ou^?0S>4vk<N^VqEcz*Y=~cwrq`g&cv0&85PHk-rxT#J
zTpCOfq&u>c)a|>nFKCtDDBJ80(j;5?G31+NrL-KnCws+%w8(7kLZDS<J(8}LZ1^)+
z_)^AWqL;ptouN<XIGAYDA?|46eH~UfnLMXhtGmeo>XL`igz-eJr%Ce=SmR~#lr|Da
zOn3@Vc$++?tVSP`_+pffnfyfGZ#Zru&=%O&q@KK&ekPluPzp4${{tk*#OgLGgH1mB
z7bMbT9C>TgO}-#cMTW_)Eg+dD)9zzrvP`b0)A*Vg*Hb!ip2@(;Xv{bH@=MrOU}Bg8
zy9-Ueq?2|<CO2$Qx?oa6yMv1+b@VutnWQ>HpxngwD^ymPylDf<WfS9H5U(^@G#$OK
zHOW-N?3*UjX`@wVVtoNN-7+~(&is0l{Zk;`U~<w(JGDC|k`;itYqI+Yu$xRC+=p$=
zCbN@J*<ung4lu1ICuvS;H+dBgfew?OO2N`)l6@WIfyuh>!THc+IxU5}P0k6h!pSsf
zC9FSTdi*Km{7oBaXBS{v<^}bErkxjn8D#p!cG?XEo4yPHOo-{<U!yV9wCx^P!%QFT
z0#BrA`VC-5nLeX5tZ38c<*1A?9p4XuI8&ExFy^G`=?{PsZ>nlTDZw;u7B~}4OJ)Kk
z!*uFsSdnSEY8IfgO_ycEm>koNLSW{at~f-`U!Li~GDsAd*3v7t&~)rcG!~f-T@TP=
z)5UrW)EU!qTELz&4W;1ldDES=W-l>~*bcN((_@rSaM5(!dk`oy<-37WZkjs|ZI?{<
zpN18eO~0Wt|COer*P_&Es-R<1U8Z-=(rVy==^}r0=Amg3g*3WNhnImoGTlfow<o4A
zOCb2vR8<ba=cfPAB=*Ae2A$vTH|-@C{X5f-N+9kaZ{fh{C|_LwW1Qr}$eX@j{);(K
zoaOD5$bLXRnI_$X@_A3u<|0p+3pwK<`87NA@QC~jo$v6L-+BP-qjEz%1dqv^7J~T7
zzx)@1e)7e1J|kJ)KpXiK`A_tYJ1u`o-l8=5Ka@$AE}yp_r3`ri`N}foMtW^$$*+Hp
zQnuWNKCho6*A{~_S8hU1+dQM(hTix2^7>qm0{NE5Fuzc~pZ45E^4LEhUo5ZggTxv6
zRN7~rl@H0MOCdi-zK!$p+xx&$BHu9@*roDKbe!yh{2)aSF3P>hJ6$FpvkIK$@}KE`
ztdM8T2Du~;ptO}rxv{?rJXhq$DM|6FTp0~ZugS;KNrmh3Jo?sMm3*@^Dy!wkMR4Ab
zSJEv|BmcS?<ffco0M0u32a_-)x8z}z;c{CZ&<Ij5Z=;Z2gFMa#>hH)8(iy_L@+gXS
zG|EF#A=f1T-bg#sX8CDab>EX$o8VHk$O~qJw93Ppps-E8<PJ2o%X?_a*CF3bOQ25q
zfq78jt(g7>ruis-q0dzWC>qZLG*IF60$mGIBvGbEu;Ri?kWfY3IDmyIl4vIzq3Bxy
z5~<jypiOU-LPOc3(TeijsEt)LOan}u!e|HVlZyOxAn}U7*8nt8vBnH-Ns8gW11(wM
zODDc_6}6P-mZxYK0-FjHJKhIop<>i}V3sOoR0H#h!az%>s|w{Ah+k7|_|J){s8-Nv
z@G8Xt8wge_PA3BGh9dAZhNMOjTZ(SiDwan=?@dJ<c{-XE>u-YGQ)p<(*P>8U#(%3K
zaw8PBDVEXew_Q<49`_DKL>0{LRJ?Nn^nJx(IxqA<@wWizhl)mWcXlfjM=2Zfk>U;A
zkdGC6>CEO6MbL6IK2_YC2$*Mz`IK7rTyfS5*e?`I>7D*cv6iCmuN6lr8>>fgaS%$q
z3Mp;T`V{6XK;9@0WI+6_qWB<6{feJ{N9mp7J1qaD4rY}KnC56!_%Vpl$!s@mH1?Y<
zUyGu%S<`Fq9571@$3Pu4bD%Ywi<x5>%y%=(r3>qB_WCnadYC;UKY*86679_no5j(W
z{*IWH`=ip^EHe%$K4#`m0DaVK!7P-HnVIf`c(B<)a)gDLeMB*cP@~zQAkZ+g2%2pp
z%)};?BFz@lwU08(osUwJ*$v8!d1dzJNT4|=xmDnFRAT##iAL$3K-Me&X#$J0a^o2o
zdO-Q$d&s#eJG;T+rd&gL`0mO>%Yf;jv~>cfm$FO=l*3BnmQT@9Z)K$tFh0sDe&F#{
zHmBgK`6(xSfwmLM+zl|_Un$VE6{y_11lU1J_jX_hD^tj?9HKn)83e+Vf6yW=TxlnP
zT!gY}5-=l`hbd4Vt$Z*Bl`+b}_F#!s{x%L^aY}RJ2+-3?ZanNxQ?^oOce=7}7O*pv
z0pz;KR36bnFiTlI7o6G3f!!dv%HQcp&r_bK@O7awg^uAAD-Y5R=8Q6R6ZBqFj-+!3
z*OgN&z*(i7P3Kmtl^vABeM4Ed11L4hy<gJ%uU5I1rkzIRfg30_Df=k@qgnay-(bC`
ze4kDsv??uDp`)G3`86P2%JiGyysw;l3hEyyJ-os4NVz-%_C8i>DUJAva{53F@Ka^t
z2k6U7W%F8)SIP-8aK2W4F$gF<%A||58}3!EJ_SvE%CSmV@kV*)0o1=$Cec>H)BFKt
zL3^3+xexin=H<O0N6hUfqte^_Tmy)Y`PX@nJ8I6+Uh9~77CjZm&8P4f1YdLg5P<oa
zyA?t1gt?aP5`XiHv}Xx0KbS(#U!b{h4p@WC)9N7~Vt#-eC!yw@?@$?L-hTt7aPuGN
zTL%&5vnYrdX&#q{9!8l5Re{8qM^$1FV$H|XGZJSm{TDqvX+A=S$^`S)`RHh(`J-v5
zJZ0{-2kMi|b>v%0HXn8dmBtkFEIO`{YF<GZ<)_UhV<DJkzL>t=lx}{z1@f8ZZ=*mC
zS<EU1akZHDGdSHWQa*%DJ{I1)pf|vx@pJSk(87oET7xX+dBV_Oiz-^qg<6bsfT3X)
zdWtrNTdcec4G|VAD2f(ow0KG(jVOzwl)rq+;?7kVm0|JeUm%$l<>7$IviO9)Tb6C{
zDMgnmEIud4`z4F2Nr1U*5k#JY8y4&6-B@E0Pv7IIwWu2ma?|1^Exqb2dU&whvX~K$
z(rt^@<FK&a!mk6E4Hm{a+OXcSXdeWHcP;wH!-__Wt}S3~viO`vui2uHZoL)@SK4B>
zT3G)KmNpCjEWor|C@3z|VX?&z0#7Zzps>(03+^V`o?9HC6Q?gMDtjUD(qh|elwMg_
z^rP*y#Zh_;dn`5>4XEw4Fr#edK8w0hsC{Em-~#jCTCAhZS-*vr?l}k5$~S0pROx;L
zaZ>5&rMh3Wo$_&=RbBMHKA`IQ99A4uC2U5?MYV7<I1j1xl(FxsYNq#)o637RD&1A{
z=wnqLs+Lmn(|W2F+(i$)R9zIBJFM~zK;;qDQ5sTj)vwRd=A#-Hipry^yD=EH<EqI2
z)<vqO&0z6UrBWW^3DvjsHuP6TQ&cKIwVt*&fvQojPzqA%%%Ct>HTo{php7Ih0B)En
zrh>fj;i{I!;E7O8JB0p5s_f6BF-jFQ1FX@iVJ~2Jj4Jpt<YQI(7^pa@GE7EgylRgK
zmIT%D=@^7W)qRSmo>J|J0ZNjp;J-JtDuwnHDXNz=S*NOce86&A)j%8EG*$Od@<yhs
z67HZ+nW_WbV9in`lK&=K6>SgD990iJ_qnPuL!mxT^~bM}&sV*r*|tE{Mc?QuRh2vi
z+69&S&k(q%`i>UpWvZ`eZF*fb-yJMfsubiwN~=}URj9n73djIhjp_vDQ5b7g{gilo
zQ<X*&Yn@7&35i>(X{kWFty(JptzNa1wwMj7z(7>qQAK3|?XGI@KA<(KL>l}il`mzF
z-BZ<WMrDgC$R1|5s&>CcTbpX+eh9RyVwGU&P;IA|OQ&in9fIvLs)o>k^ZTlWbelX-
zjhY0BhpJWdDgADhza1(cskS;o;<3u34#qrFbqxdBbJZmJ7VisHDa{ElRkvw@{z~QO
z43^ibqqJh|Q9X7-M|)NK$qVXe*}eyrPL_wrv%25%fET*!Y-tSMias5*oIr~Y7fb0a
zlnz;bKr1O%%lh@;akG4DM4P*%Grih9EVq4#N>9se6tMQPj7^2!!<NJU2TeyTpOTx;
z+p=^vG{sqY$kB;-tHV-YCR!zCLoUf`x&g+dSVdA2%4vKJAqNuaRud>sF4OAKNNCEn
z>Y`MF8mpKL$TwTP`5JBatR6+6)MAys45e19$3H^8&FUvQFxPH1g2HD{tiGb1^;4?@
zpMdkF)kF%Py|#*>goGX|cY1Dnt<oqfvCnGHZCLTfYPy`VvEEvBokDHDmG~X>zO#CL
z3TO^$H@cr4)w`ENp_96tl79B9EoMT%L#^=!wx{~xSil6Tox)HVq(1F~ZilEB(F`7{
zu5SWMnEL&RD21z^e+14*_0%tE5Y%rgA&{)jh@{itIqEgZP@k**-w#ljr~YOncuLe8
zXk$>Ses+}ZZuQn?$X`@nrYKFB`rely<?8A2kgHIaorc^cbvRvv%j)fGp|?`KaS_NB
z^@t~^ys8eS1@ATW_vFI8t-d!8hSsZj_-2gK1~s=Gn(nBZ=;Jka)$2S^YE+j~a&VK{
zk&?2S)pz>Qi+k#gPa)W%&gem@Rh`<3Qk&ZJAS`TGs|1L5s29D5%1*U`JQrPR&l-r|
zSNG09>4AFSD6l+KZyX2lZgm=^@E9Mdy-iX3SbfnOf=|>Q3(=>i>eM>)>6v;41(2Sr
zo#p`Mg?i%;ka(${un`u%QrBMr%WHMmCA9UZf4l*?UiE8oIrga~<cEKwZZ${cTlKR4
zLA?WCNS<~_{`M;ji4!l<LU+HB_Z|pVXWr{7c#iY8E&|(^-~Ju2Pw*a}0nMM+E{9+c
ze}&Rlf_Wc$VTSNKe}cWCyoWuk590@2K`ET~r!=1k{?917+Wdz+1fuv~D32+cfBP-^
z62t%S0mNhZ24AR+<Bgr2s6EMlJQqCiJYSDe0v|ysHHrK{3d^42pOQBxi9bVG)XDsi
z3~;9KZ#iJ6@=6Xcr}-Terb*+2x1p5ITRH+IgJ1A1dYH+7L)+dgUZw*|Ha|HXoH@Mj
z2dK>DZH=iY=JAWaKrx@MKLr&9{IJQ8FXUTyL86G)-U4Vbf0E7;p5gthq4z9rPoB7Q
z{Eb40pXdLggy#~zgxo)+d>^^~F7Q}3;FjeV(F&@JA4~q1a(>Knbg6=mCV%TCo_~*~
zmdpGHw;)l;zoER%EBrdjUAW4p(aY@`ztIe=*ZH(B!BWNZbTYo054#QZH~0wBTf?`}
z_ZMpU*Bn@G@^Z>ospBJdfZXEerJ^sldHGmy*7NTVK&gR$5eUvZynhl!Bk%J2D3I02
zFCb5C6Tedn)@FVJov6CU|4E*$7IYh?wemmECuQ3Bz{yb9&hMffR0sd`GAcWHzji3>
z;(tg(m+tc^<V1SF=f%R%hx}J_P}$8-uRxa`@q?=|+K>61(e(U1;b+q|c*+k}U}T^1
zodQbF`Ot5m;st+-mhCV3&aE)!75^P+dd;U@fTkWk(G{eZzeumTK7P__aK7QUEr9r2
zURnUoem*1~{e8#J4uQCX@X6;OjzU5mSe%4NN?bJV7hGuF>?{<`Me%^J;Q|akD181e
zN-lzwvXc%8*;SBm6@I)3o7{v)f1%A?7({1mJcKQE(BvstK7pK<Fq6_64hx%&XgeZo
zt%7=Qp(z$DKEfwkVBt}r#02&p6K>KG)#FBC4jmr$6{b_>p`YMKzRDBATl%Jizi`|I
z;}swTxIsQpSWE$>AYsmr&=f3W(wrS4cv7Zvs9;Ioe-0B4TtQ#Lh4$GX5yF-~VN9gp
zN|D7VVRs-{q6H6%_{IpS3m_LO7%x!XW}I-DKG$|q`1=7^<An{hS4$ACP&!AVu#TSl
zQv$1j6-h$VV1OnI`<_8XiqJ<+{!~HN1<uog4XvKjgs;9r57UJ-2Pn)C`skIDDHyE4
zk|hlDhd{QlNd(Cee*EuS_PN4z+Arq`R|23uUx?q0Qi0$;0TP8m;0lzA1l>B2VnMzF
z_MQ>``4yaJ1+&o@r*lI5YG^ty-0Fee65+F#D3uDDeGs@H#8Q6uMWIy(QYO46mtnbJ
zLs7X3Av)NIvAiURbgbpF5J-{hO2Ky@x^_h{jR)FQVO<<b*Mv{$xxX&t&jV<cP%{Xo
zRSSn+K>ZD2Ap=q)c<lhG72-<(c2hV@lTe*-sR){G2~S6&?Y1zbA1L+0r(ICgAjG6o
zHsl>)38g&U6>7>r8ih6qB$|Zu=_oY|3?&KP6Y7pazC{>Hfs0n*Gg|ex3G2!6*)GgG
z0niSiITvl6g6RmzbqOMc<L(QFTL60?yr4b!Lt$kX<hq4>b?EgYp#rXcqx7*bn$F-q
z5#ko1YflARa$r6aSXv=G7aqj{=7q4Z0pz97^C#?nB|JbHm-Mx;j?z?ngei1i^$Htl
zPUsV|CW7;gu={sZ;)8d#P}ncbbOCuM*e65IL3B3*ileBNK%db`98Vtc{o(>j)OHrj
zC15=u?)3oALGidh+FZnXT16icQ(J-UD#p@n?IwmZkarjB8FbA<tR;tnr|3dieqQ1c
zHPjy#wUo4TL`<iZs<)V>1g4MJG8h6!#c7n1eat9Ekz3=qIF1J2S1kD+pnl?-7a%7@
z;W#w;i@voG3=p5t7c~M!ciMFai4P8;Em$<&2+mVtCY^>$5~q>lC0QIu>!K7fl>Ef0
z;@9NUIW3lU;+{zp%V@WqE(XvVF+(&~)9Wx(RFeBAOMH<J+p@)$ec;IvcSk{Qt{5`|
zf_Y->d4T4N1B)P7AP#s6fkM&v5-N(s7Bxt*SnmjdGh(g)%(G%<8d%PWK1WeHFRm#A
zN{Kj{!X~An4K1lJh#^Kw&$uXB&}3gGPNUrQa?$cbsHhO#dw_OHtp5Qpm&Fg40;W=2
zNDsgjakLSJUKQ8U>+G8N?@E|<UHl;kr7E%JB?PL)&o@HT4bhr>Gc{sA9RjQs-Dnqi
zQ=CE>adl!~621R!i8sQ)dRyFd7TvBFt;mz!AeIb+raPkVdtkjQ{yqt$QT+Y@NR#Ld
z*P*moTuQgcJ#q7LnARe`Pj_dlxM&Pm+QjuMP-++ZD$uhI@!|r2b&6YPChiiO$z^e0
z{NF(GzdR5lETQnB7(qEa-J%eS#z$g%CdgxP=m7NTiTH9SK%a^`icoqc<{X0F=i<zZ
zsC*$xY5n<9EM5ugUx^>K0Ohs#dKA?6h#aNw^or{l3__n6Fa?!w#5s0gc`J%o`x~YG
zV))0<^iDkGfnGRhCayr&95qX`P;$~V@fex?nsa-g*I6_87Bn5uB!r=KP&0@gSQpJ_
zez4+@=DmAR;i_3!3;{Py8O;#xns3uUJT!jRQ0S?7xCks>nuqj`Ijk8$YK=!U|HcB%
zTeI#Niawg1bY+ferqJT!m}b%|R36tDDYWUUnM7L{Kg}Q=N+&dT$*1eDc{LK)0h(E}
z(fdHn-1lH%kmetnVS+VGDinrjhHd~$sAd2iR0z{l)Pf~k^9z0ZDZ;36a)-f@nnRAT
zB1+SJ7$X#|89Wp!Vl@6CD8*`y{)M(U&7k#=IH`F@JE(Y#-$9TB&5lfPCTeWxQ8}e4
z^Z;0rW-zTGk~K}_2T9R<zX0N?8ixrm=Cmf}dkCaydTqdxjt|w+^N^v*`2@9@8itOH
zW@(NTqB2|alyZ4;G!MMMnycAMuKPUAD_WT3Yevz$UZ7b|qh6@-PlP~`<{9mGi#5Z)
zK-(Ej0^K@iH6C+Oc}_FT7p3!>CJS(uXy!;!S*kHLjsfTejr0h*c2V;!WwMlMzKz7F
zmus>qL{g!tYC+p24NEVe%bL{`@~+ejh3`OmMKh1??yH*B&(L;F(@mG~y2fHO)K_VW
zW`R^|4*dcRH#A?5g<OrMgWOfMnrjjmb5pZ>1MUCnG*Viw+|sOj1*2|joJWDRUK9N%
z<Qp_Ol%sV=V?~F(?rN&vgJ7d(^$^(9q<Pg0fo4s6H&E_rGAZM$MWe5WidM~Y+6K01
z{yYMfcFko9ymx5AX_oHPu+AV|8pH?i{N2}hHiGAY<}7U`9%_C)5B1#|M_Lj*(pYt)
z^jM=Jm?xT~nE-vNiJ~>gGtDyEU_aONQ##fQ&3Rf`ywsdM1+!miN@`Ggt=Z>*QjaEu
za(sI=cjiE@PqTU;P~K=hA3^cIx0;Mm;OW;GXq)m*lR6(f4%+YDgNcq>7fYyc(vH`l
zv|szG18vUQrpd7BnDzqgSC4D^C@tPsyNiw(_-QA92!RvY6;sgWudRFv5~#g$7y?1s
zVU!jhtldP8%Mk5XcCgSGs{Ql|^oD6ox1t!XEfgUip<R9tppn|W_89djtr>wvYhRNW
zHb%R5FJNM|XFdjr(_SX$^GWUfa0tX}H-7}q1g&6+%ao}7om_XPv{AGqNYZ-jLS>3J
zU@-(zwVF*Jr;XY{cL18EU7&}ibnS6kHe_fmD1x1-4d{SPS=y^wj90dHln$IZ+7$A?
z<Z5lm^`57lLtB@8?GNumZ-MsYMzj@btLcDkkruh9cpS8Gl-YAeTX7F8XSHRtr9G#e
z>j@3#wMJ9Q_%G3Jr9AOcZLTfUU(j066me0zWDj7<v{gI7TCN>RnI{$6hVdYmw6S{t
zdRZGY73wRs5^~L6(T)iN%2jQrH^?=uA{dp|wf&nRUZovKhb61E--LqP(6&&XT#dHJ
zcn>OSwQIix>rJga`B>_-yJ=^BOFO$0<hJ%01qJK1hsVLD2JJ)IUER?Z90BNE?T`=Y
zanMdp1Zb1i`%~D|tbOzi$UW`<Xt&>@&DjTITD8rz#B9?(zYT$Q?SxcRc4$}4qWD9n
z_UB}vb!ksnK+}Eg#yO~bp!J*t@=)7Y1GH}Kzce8~(oQyq{9|pZ0P;l36~e-&+VS2n
z?U~kf9tQ8Z_VNJ?&<pKjN{o1^-7yWEue2)-u<*5Zr5t*Dw05*&?A2cX`@g>itKDo3
zo;O;>hd_I)eN88k`?Y>gA^%PrTM4}mI=>)T=&1W@C`wK`U)pW#*R8Zb$yw*?0J#IY
zIPyRo)Lo`?5-vIeML!SeHd9u<t8P1`wz=u%5~jOuJcY$PbiduCuQ7P)Hd5HrOE-{S
z=7)8bWcLx>@XO%w)=fMMc^}>WRbV-)tG|S{W4dz`4mhrxOPMFWx>~Z(PdD)f$O&Ec
zSP1y*vc^C>K(`?odINQw9Xc4KEBqKFSl6uwScvYO2fAbo)rCKXM40YZI;S75+p7dj
zgl>8o1S54z&!H5h`=bLA(YmbfP>Rv@Y)2_p*EJKRIGu3-Y&xm?>Nixz>sC>wXM)ay
zoL7muWO@&s(oLW>Vv;WZ5m=ISBZdMxMYnG)SW=C;9CMg)TG!kNv^1US7c{2p&OC%M
z8M>OKkk8buGyzMNZrv_aX6q(Yqm-j__y;6c*SjC1o~Ii^tGj$%1Kr03x?z+`RH*Z%
zC`gg+4n?VobrWdR&gg~(LeW{>xiEm0=#1A>Q7qN%qeB!Ib-zr4!ZO{@3t?NiZd)D%
zD|GXUVfQ87&0%P}tm~rNvQk$_E59qckX>N8s%xOs=xaJxy4SDkK7RvERl0=zXsgzl
z6hZEW?i#(@YIMiRM^dYs^D|Ix>cWiAP+O-vmWFG8OP6>Uow=<${55zQbTjGGS$A|f
zZ=mU}PWcuFH|j!Xq12>%o(1e?UG09r+|zwRX%;Oye*>&&)!iEk%r@Oza)q_)PQHUc
zhpyo|I6HN>D6Z6{(~p4oeVu$Otv?^=7M=!qsQY~>1iN+pw5EQf`$Yzx$2#AOsC=qx
zrP%Q^T@ft+pX;PgL0;&_jDy@uT_pKyU+MIhVef0*W6CAy(OskMNw3b$0i`}&sxQ>P
z(S?%Z^Q}%xtE7IN<R+cQd8c#i2djhr;bZi|QU91$4^H~Y_dxdRr>=k%&idwykT{_K
zkP-tA>Ic%X6c@d&04#^}t7*ULs_*_BC~o>tPgJ_=Z?$7AJoI~fA>gTRqvzgBfBP!h
z4(spMVwjKUn{p@{)LZ}kL)7}{9ci6`zhOHZCLYs2ya#ezUr#YUU;RG})cfhP$fI^b
zzo!@_e|<cK`U3PnQ94<mKJ5|2gY?6aU~jPg%c)Qiq7R@TTd4jI+7X25`)H>au9wU}
zDMDW~24*jg)Nh)JVwB#A@(ZK&bEr=-diZ(qjOmv$7~nYlKlJhLllp;Qq7<(mSqYM$
z&v_0_iTa$q=-Mg0iv%P|-zY&_vVM(Uc`joxuAc}))Ai@R1XzZ?m3Ek!`d=tikfl$H
z1j*L-(-H9;{S-PVl&jx$6n)9l_hkSjUw<VW8VdAn<ozks*IPlnNI&);R2J*)X|;Yv
zA5seFv-<J?4AVJ%A9;<=>$mL%DbWu$W}vZD-?0<qg8p3scrNOTT+q)leS9?Zmh1oV
zgcTL~U-F>-l0Ie*N|*J2`~#LseO59wUD3Zso1?4xmo^Z%rgsg3G1v81{|C$}{l~$u
zw_0yPr=oA@hy4oi8vRa3aMtQgXVBvArhW#cMAzwuQGWC-y?X_CZtEvbM5$i?`5dq|
z=+h|jd`JI{1f{$BFKi&!sPCVGQj>o9NN_gmpHejap5C7Fv0L;uA3}YrK4}mJ;fdZd
z7dAcB508StGyTsL33{&A|4xg$7y8d=ntZ9(PXl?SpFwNO*ZRIQknho3*P_&`|FRWr
zeflcO?R=x3OsP3<^&&mt{d$iupq;Y*%M_eR)>CoIN>i*aevD3>wmvLHTblK}W3VFK
zIyV=U8P=2CP?>41yF#Cu%(mW5Ypz^tPjc4fS%+)`Pl5GZd!Q9s2d+b9k@fp>x}w%6
z>2-3(`tBy6owc6v2IQRe$VgP4x1L9NO(oW2$cuWxx||jk7p;dU!I(1Z5>v2LSi6sf
zz$NQ<bTH|%H9r8A#!BlJ%8$5Wy_B5gSFOJy=g2kd^Vw*;ZY>x9Q)Ru0*0j~uTPU=6
z!#eUjN;TG{T9{pHZ9|cfo7QQesI0Tr(BABpwG}y-Zd;quz}8z&`U9P4u>N8jIPX|5
zA-C&Y>)xMG*=V$WrG`<h)=BQLw8MJ#ZNPL|>&YS4W&K_@)Ze%6S_YU0)*sO#_@VVI
z5tp*tTJ(azBWt%M;Cy2J)B8YsYMo3cuAf;)PXKvt9ryy3FRX>rV0mfn-vfJJSwE1W
z^0jpmon-2<HfB74HNDo$l3+!j^?47J-dGo2fQq-)fs_i-Z#|hj7w@dUnFJUIL*qjb
zM?=lu7%nG6;Q?scZ@{J!Q=lP}UYG|Am5;%4(D20{z;rR(pNh6ahOa3$=W2-N(Fr%h
z#%s{vZU{Acqt?S<MsYMxg9$CGybRC%Ab;5KPYnc*7>fS{sE=XcMN}R&^wD=>jv2n>
zK#m*YC`rrL@U8*I_!-RIz;eQ%B&UeKq5C>C1sJ|v0n9){#&UoK8G4pMF4$l~PQDPs
zzAq?#9%`tz18bOJCcVAG4a?|mi7-sM3G66CLO8}N+R(EAV-aKcghF+(hN>SiByom1
zay-TxI@=+aXvm}4<CNidis&R8zFrNIV)&6FSE+`a4Cp;=xI>Rhnqd@ey3-9yuTpYX
zrXlnRShEc8D0G}{m}`#4977*DmU9iUs{op3U}=M!Z;*Tem;yueQIrY|x{qLCk)gE;
zmBog9Ju1%_exa!JS;N=g1MHk(<1rX|-jI3%l_iF+H0VUBp_uNA3kGW}I)+Fu8sgUh
zrp!=DE|v;I;v0}l28AaiE*nx<m{w^>_H!(zO!#V4_8P*YAn#)H0r}xwZT=wtrJK!S
z2ekRw{6=XR0XBi;au2qNTn+2PY?chhs72b8eFe@qo1rvLCvAeRgEQVHjCL*wHfyA?
zKGEg{P4cH~OumEKBpY9Pr6$`jD`_ZgGL40RNwwL&9|LsSChNb1B%68~;B=cGD2*(`
zX3q$KX4%Z3^K#iXWi*AJwK1n{%{iMRlp}J*#(f{quG&ni2j?}LNvojuy3Mx9V5zcs
zyb{J#+thxKp53rH+lNw(O*OstYHg;)86khu=C>6Ptg~q-hB3EnUf)LPwoTU`0Ij#N
z9SXq)8%Nr*+_8BRj>@|>)&n8eXtU*8*wkdxkcPHqn?hO(x7c)A0K3)Z=RAPzx82>2
zN@v@wVZc0KJ8=u-4%&wN1<WAZ)LHah{9xO53fF|#en{)|P}|wBz#3+I_Dht)ZBzaW
z;o8Q~9yrQ2h~6AAwl-$~lWbe3hl&*2n@`Z+RNFi{jC$I3#$H^eG}~nIHKf~4D?us4
zHgGl!&9vP|-*PCjolSxIVq5Kg+KHdBooEA|3fn)6fOg6D=|Ygpw%!z4th6npr0A=*
z&J<3&ZtG?a&MI4TnkMhqPVj++cWt-j1GLe03B?AQY<-qN(>+_$Ux3nLdq@uQ+}3gd
zDqq@qPXXsE+n;V?NM75{-GJ-!Lyv7E1-bfcGwJSrW2<yT<6Bz^Wi9mEdj6NnZg-ZZ
zP)9p=%Jg)y8!{7C?6<Rb1-7%@)eux3up4&=y+3G|=C}GB?&`V!z<PJPn)hL-huzB>
zuz1=<&jqxXofQQ*4%;Qs8qM48svkP&V^@`lwxf1aHbT)cyQ5W*J8p-t45lKx1H-`S
zXLr~Z9Xw%|zZz`;cB|+!ErE84b0H9HR~L@95WBuFff8ePVBUXw6}u){ZlAOpL$^S@
z-D8@O674?Jpl3;T^|Z-Pwu?;%ON!lUS|6m^xsb2zv|XM#K-26(=s{1nyPxGZ<vhb1
zudjl9w%xdm=xC1JuU25qvrEi@8RzXT(iB``7fs>LQo9!VY{Lb+ku)J+v`Z>QWtrU|
zy7uLE&a_m!WEb!YP%hhj7mT(_yUaqg)!5ZtfN8aMDZYTdYqyTlF&gb6>|jij-9#hp
zK$`95-9h*7*~O8&x5dt@3G%IWD=87U%`S2)VA|~xVxhjnuG<RoopuLjp|Z=)gmMt>
z+kH_7&Ifjr>0JGh_h&t#1Dg0ZWaeMcGBk*iJ3rZd47TlOGU)+uW}ck{Ilz2mtf33c
z^p-->g_-j&N{5)f6A*S~cF>E&jmf8BcW2hkle{MjWEyB?p1~ZT1h7ozbK1gZF+Wgz
zC!0~-gj^2OPl=bgOgd#=<uNY*14}+rPMPHeOvyWd6*4LG8OkDN{wner6f;@0nmxn(
zGYmXunG9Ey&M`I=u{+OrQNX@}k^J`Fd$M-sHBG_JtbH;n53qTZE_;xDO9wSv*ufNA
zKg7<ZbXiw6Wj+SVjon0ZzB_x=9+e*Kg((p5WY?Smrx#nYlzaw<*&#~w=?JT%1R-yB
zS^%u@VQt_cl7+JE`RH~v8-dNU>>ziT#@n6ispH<0d2@l&f$hs}`vCR^a?=q>`fu3B
ze_MthUrnusjbD%T0?(xJv_k%-JPpVTQz@3d%(@xo{oZe+Fu^YAYOvbdlPCTVbEy<#
z<Ia?iKq-s4Lbuyl=Jp5w@0tqtXhqx4UHk}2-*FpEVUUC5co6kK5?}^sZ^>bMl)_C0
z(-D~nld?$wk2Fcx1iUDd>ctRmRL#B)mUh)LV>k47t0s*{;|taJa<INpRZT!?zvW(X
z2)S8qpj0w%%iH9QJ7MXv8>LXoWoyA1WBCDPal~3G2f~Ut%N`0lpR}weZ+5)pGFrSQ
zSPuRTT~D+OCjav(OJ5g=Cs|&nJmqA|1xJh+opj5EYrvXknZF<8tYzMGpp{wvOisP4
zmb(@}zRvPMFF<cu4ov{eZOiHsaMoLXH~{J!EEg{W>9+i77C0YS{spg`^s(i6@(@0;
z>~clvspa}pQ25O9*bsE$xn=EWsC{8sF_3b0URug&;9psG?gCGb<rROZ@3s776L|V8
zpHoKK8_Q2;L;YLJcJdteTYl9Ffp?a{1A*;eHI)|Yj#k4cd)dkAz6(k&R`M@^a>z;~
z-<+$}K_|$$S-HLdio4a|_fYb-(sfeKs*ly1Rp{tZD}l0Bj#;S_p!c}dm^(m=vf4s_
z8#vBtGrhv&ty-@@Fx5)e1NG@v6`Rq+Jgb5C!C7y0@C&pxSZxKU^sd$HV30<uyT5|m
zvodT$w_B{X(*ckktE*kObsW@_c<3{FsP(jF_f&s*6U1NrqYX5LskeOvyJOY!q^L|%
zZ|Z=2hT3!+H07&L%!5tm)Ki=wU#>n&>2254Ka2wBO?8qRN_W*6<S%Sf|C$1phiYya
z^gdVX++j?g+A)&GiN8z_iK~$>w1g%%-iN#&?)+e9z<BWKc)+Bdd^K$uy!f&7hC0k|
zU4d>N;Uj1z;LU$Y*^@rJPa}*u%7;;$;257!2hQXCA44GL%m45l!2I~;a>$+FGs;jI
z#n(^{N;E&?ECgbBV@@S?l%G%MBjR{9`36q%d+z`yp11xD<|ptS0$3CI8L=Rz_y$^?
zB=H*ZGbZ!Xg3z@Tek}QgQu#J}C_K$?rVOhzUe^PK8GM)zI5YX%6z|I7ODIz~n{TJx
zQw|?)bOFufqv&0l$Iqc1cs^f29WCGsC!=eHyeI7wi})F9Ay~}!ehAJp{J+Pb;w-PN
zK;=1p>L-vp&wuWXA-T$ThM-HeJi8arclez&#kTT;2f)Gyd;ujxJ>wgep|TGp3Vpue
z7gmGyEx-74$oKP`^U?T@uU-#U2O*0-$l@WGn1aPq7)YK5FJaW@U^y(PD7)^6P%;2*
z-a<na2I#2JM}{5~0zCkBTo^SC;=Y32_mJ}wO390ULfFv=5-xlwp`4uvVMZ8=k;0mO
zphXGJ(;yfvJgWsvj8GT=D`JJyT`0u~^ZLOVFX%#0N)TL5LT{pQZZyW}lu!}{^+`e$
zW&R`!w>!X@BD}vHBvmLNuX3(%&<x$p6V^0Ayif?Xp`4u};VV$&QKZcWOog!c8q{AF
zrcQ)lr4Tn9rCNdMh50vy=j7JCC1~QH_qMQ=p41khQwOwG;a^&}wF&zuV$?3wJ^)LH
zz|sDrQ|KfwMwbv+3UXg~OumH&LNL9wjSq$JEs*FIv@&RVB&3gr6_1752$Y@($6BEG
zsgU(AV4exV<ZFH*99#r}m%^_qT!UA_pOa8}Egby`q(}H+5PH}vOn(4F`-G)5U%U~T
z=#<7=!Qni>`h`dLfbvfGm6pH`M)Bu`5Ofqbgo4LOTuJHh`$b>6b)Ci1BD8smb+ozn
z5`TIN(+-Q3+2A}P3V#C4M@(2r7hSyY0-(plZSTX-<D%_OSP>y^Aa_=z_<~rX#5ZSA
ziWZMP0B4NYa1@xaqH!_hr^SgS<or1)I^KX_ytv^c%uf)_ywR2@>f=C8iLTdSOp?g8
zz_es>ENy60#C3QtA}!%?C|J_O?hyb@7vHs_lp*Sdp_D1As4YvZr9Er57`z;EIb!lj
z7@8~YG?HgBPwcpa#(Xi90;vU}Lny2$6i-kLzDT@4SF~7^Q{Mj>(LiafXT^9s2wV|M
zDfn<z%%HP_*ToAbAy*|H9gNBv@qz%BTJbdv<wJ2x7>27`EF1#TCmwV_+Z(Z^-U#(?
z#g_R{(J#K4kJ@))p#vlwGzC_$)KQa3Yknuq&{pW(uNg+KSZ9qb9h*C#@gn!%LCvh6
z(B`6<G6Z0UG<rIG;Ho)DA2W8-ObkZJL!+l<kf%m(f=VxqaWUi$YaYy}oPi@6&2Th&
zYr4+@+efpp7L7+WTTD@TO!F;8>yK-O(lXswbMz=mewtcGfS%B}6~i=tP32rv251uY
z06S1KmC_mFG!_1+JgMoJipqFR=u(stGzb5|6-m^j)2sEAX7Z=+;rUC}v}Z$aie~+D
z^eI&{j&_}=HUD0M6=|9gl!u$Hsj37C8=?CNJv=?a`X3mRHsVS-U=EEuvk)q7j(Tef
z6-}dt76aw&7yqLmcK;XqqEYEHX2c4R6Jx3qA?H744ZU#!$J|K-m@$3K2aQmFe#}`N
zcuK~&&H>M*F~exuX&-Zemf&$?Kd3ZAPw{WlG74^QmQX(MA6*pu*pi@t6<as9;s0IJ
zu0weDB`@IbiMk3=2WIQ%fOTYs((c!ZIS~p5H|Eg*ptv&;6}0~JWDe7E^f<F>GBA9Z
zjy33O2s40Y@lfW)OX@juK!Ub7X80TQ^&~U;HcXFa!s+x>0yA$6K+~8X>5O?gGu{W-
z`OKGe>c4<_kDl^EMtK8rMNB?9-O3mvg`CTouWHGySiv~dL&YU#b}<@jn4nL9R?A!>
zf8<SO2fd%_7*jV?HZc;4%rrA2r-9sKtjWFC!tD7JJ#1y>><4HY<NYDbZf6{t(bmBn
z?}Oe>CO8IdPneje(D0Orrbqu7V@b{&<8uZl+A*s!W7H_VWg;d(qMsS~J$mtuDUO8|
z4(x;XKpffr>!@^Mb7-ZqpB+rOgU;+|f;qr$r_I(umYD|?F6_M^upDA<Q|!l;)ls&s
z8|y=JsypjA4V)gVFTD~xjqLkfFxZRzbtK4P_Q#_jN7w;2FwvV$KvW%Dfn-`T9A#M^
zXvf$)6mdV!Dmk$DvXdwaz>noAkNE`q+d`=DXP<uqLj%|rN)rrZA9=&3Al7vj#xR&Q
ze+j)I?CIf<i(!rFGO*$^5(TJDX5IbKnH1JQw`MAP@(FlOv*YO4VlImVo0zKD#pJWd
zXXR6XUBI6C4SEaN{CyBFWjC)x+XXhj1DqFGH*#W?v48yq@p86vE=;RnH~bBOOYHJf
zfWFPP8ap6Z&wjEQ#Rm4$FA%)Lwo=5riT$z*f-UThNswq|x4J>TjSZq)pmsLvN4mbO
z>MK~^$^J$!m@c-*9Bubmr>kgl;JSB1z=hjHhqt^qr5!XJ=hCL2GKg#Lh1y6?_A8y4
zN#I6(jM_x53yuxxDQ^BCkR+~+HkHYo6UF~hxS})YZ$5YV4pbCy^{=6@kn0}^(~7vR
zn_wyCZ2t4>akDL<{v5ZI-Ua8m!to#_oJS@|DK~&N;TO1Fn*e>08-0`hf<`qLQVA<=
zbG>$eY32k<aOmXf{zT<t?zan&c*PZv*R7wswHOKyN~U_id>0Ax4sC}dW2U0yDk&(1
z3OC7m+NZlq(#f;sA-VA#N+%?lFJP~~WID|o0TQc6Knawr!tn>AG)R&}5usqofbYQ*
zB57I+!7z#0KwyVUPF%xSL`a4N0VYzyQ_g;r#AhGcq9vc1V@P8ppHoV~X~`uO?9GvU
zO#ZcEiQi<{bU|Vt0`W@8h7W*wL*h#Jc)i34Q<?Oh<kf3b8t+SX$-(nLl5ztQ4<%<h
zQR<d_M!T*@l7t=T_G8IN%9ME`iP#Q_r;^e0Am1-JJr7pAlk9yBP6uhx37F<6#pHxX
zRI2<FrtOzn#z4SXx{!|V9+2{p=)DX6L?+q}NfYUX=4zCl4+EN;wAU8IT{@g*QxEAH
zTJU&ESL8s2m$a9TN&88Q9KmuzT6z&Be`#q5U;?Cj$lgHd5O-J@B<0Dc8!WA&^<gLu
zHG(rtI%N}3!liQ^(7_1lSUN!yi7#Zsm?)|7fdVkm(ghS7Op-cX1y8c{Q(Ew(NI#v3
zwp8hC4rr&PPsquiCOvEd73tCkNr1_a9teTGS<;DPFbLUFPuf@JNM}+EDOY;sF7)O}
zC(|vEFD-NdSb@}c4Jr$ze{BKE1!<D;6%<~S{x200WzyT^NiUZMI)hY5e_RQ2N%{>f
zE-p)V+yqOdbmD4U!z<EZ6mYyI^{EBgb?FvLa;%b;7sBjnX(vT5Z%C)*qEsX8rV~=N
z(r><ly*H(cDVS0xUAqC$ZPFMu<qWq=hmHbThjc0}vOA?AS?Elc^u<23-N(UwU_X>P
z&wzZlbk7lRK9a7E1<PY8N4M7#sd*(hpGyBtg5Gyhy#p#8WN#c{sH5x;a;iGXlH35j
zU$*xzv^mQ@7zgnKvM^7I8N0~3Y{7a+cIF|lU1b+1qvR&LN9%BR*{jb0>LD}Rijt>n
z8SQ)nWPTFB1j;th!XZfZ4Xr4HWzqB)hRDuRge6pVmYmOFvP6nvhRYVa!NN${#XLYq
z$t>UDGDXW)Y&FC47b8pl0eWL)Lq9=doJ`w^aXu;g$`gX|vVB<?#IrK(97vp#?WSq+
zl1x?v^Y6$$xsS@bvg`H`cq_Y1`SEckzk~zqyvg6|09ImB<%P<6lbIE$yldj?4)HFN
zBt1-fVp5a|Ipb@SHR(X>F^ML(ldEa(Wk|T0vJ}TYW;!e$>O)NnXe*a$8vYi8kZ;Q6
zLGO9f8Z9d8O=r>3nJ1>h`~m7B&tHzVV{#u_AVkQMWw0Ve9zag>4EYBFSjyxZXbD;_
zZ~qi>?nXtG8EU;0<H?hMSdqb^bVPBOHnKhn+fPt=RMDIc*5isgy7hb&n_j~107Wqk
zX`q5JfCMRawt*!?@%L!h6sq{u1_~n;@m{buO5tP;xoE{`S{B7Av<iqPD85^Vwj_m7
zUJdzFMZP->PE#cRjK*}u;6KrrsTkx7W3m(jpP(&UQAPJvj^Y_DNGlWy8<5M2qN`AN
zRWVh8wkk#9X{flNaH2(Lt)k2bE9w-1GXYkwSV=c&lftwcEKX)E6xek(du_ac;z2V#
zx!Dhyc~P3Lmsu^%UPsI}CW9O^^Bf6zU$fB17!rT8FS8&JWOfR9djG8m#oj&mvG6_x
zgBBH2PTu0_Z2(*H*(m&8`n4O_e;NN4vdd<T!tdpaBT&C0osu6`dY+)?Z<RUi##di^
z3zOFDq4?ylN(261+dULw>)z2p*xz2$*7f&M6!-i4quuE3u7ctCz5Ch`AnbYJjNkT4
zz6I$2&eLM+-^HKe_rBvSaEuW<@Y|7jOP@<}V&eZq-G1grJp?_Cj7>GH^<sKx`ajI9
z9FEcvW_19FKf`?ro&aXW4?quOM!^M(56^Ai4Xd)4?lzzmG1mC-i1Y$eN%Qs<X2en2
z;NzdzKLr1Wvd+~|9mZ}i23|OOpZxL>Y~C^GiezhVP|k21+d)g2lk9{C08C=LX{nmb
zKFUKWh5ee+A~V=+3`&`7-?t!HY|H_WY&LcSI$FR^@Pa@gdzG?Ci&%kjh|aT%wnBXg
zdzNyhO4(gy;H+SOaD?7Vz=Xgxb|l>%#_McLF-)&wC()v*n%$}bPaQjK3QD)w35QX-
z&3;D7aE+|*JCG*UjaD7aY&SVw?y=X-LA-^nJrBK|Y%#qEy4bh0hIqujp^4%-TkZ{k
z7wk!j+rMNJ>4xcJcMO7@gOOWKGutz{qdUg&g`)onMMv<jpJ8c^eaDp0=s2)tl!lKb
zFy%owvF7yA+Wo8{9X)YohsJ;$VAB+6JIJ!+wsm30?!<T;Vn-f>xGTHrzqc&wM3ESG
z_UAf)d9ahG(Kl;6SslF~z1V>ijXuntv;mJld*cbL4PdXQp)HX0&qZ4-JGUL0PO{^#
z|Npyx3hjdzZCnW6#fRzPUGilE#Fx5KrqVCl2xFPuKA5oFv>6C1(&>vuE2mNTdsQBi
zO^wpkbN&Z`HK{{k(yw<ZGPTzEGC<dLQ;7bzgmVyB|0o{6fB%MNmyH#Uuwm<!Z=h^v
z%`(*Qwxw6&o)trAFc>2pMmWG!Qu6gd=D>XF6LW7e6dqx|qFi}zrdbJte3&jQN%749
zW)I~r2QkIX7`|X8tq3NBGC5mO8Ns-cnrP-%6-XSD{2Y}DjPEy)Phv_Epy>*;m!{mS
z%&bUs;2N{D5}K|v8p>j>V(d4ebd#C&HN+d3!IV+Z%#5bnzl&+7uT2|YFrVf?u$M`?
z4W75mi4j11$84PlY)AINAi#vOULL5-WSj8E1pe>S_1u6TIn0NnA(P9LZh~2POhPXJ
z^O<E7zbs(>9s^RyBudb$BIa!ffQp$(w8t)EV%4yqoS9fkXLc%>>2z~kVi@vsUS>Fo
z1ywSo4j@;U@sv<<m6=aYfqTqR@=mod^>a{aWzNts{BGtlIqV)W2WgC7GoRCJ-^0vn
z0GJb7lm#pHvm<7J#hFd|8v>qesXd4nyJ8VN|A$$V60n|NC;5Z;vlSCDxB;x}21q13
zo6;Vl*eB%Gj%HnGWfQ}8&~uo~UZ&|Wg&j;mvmEwy1NxN9`ei{=9_w2G@qG3IZ5~S4
zH<Z|0%8m<yzy)^yI&}9UyO8u5ud&<L0{c3f{yrqC*l3#as@diV(A2;-RiNz-i_e$f
z{ml-gJGGIOzd>6QyYN#CP#5b*8@T&yiw12E*sbIqddQkA0O@AAsnGO@jT{K^$Ly!2
z7@#L?+W#Q%l#Qh**)t=%gr*<N5p<&a1^bdxy<f7Y>|xt0mT86jYc_f#y4J(yMT4`K
z4Znm^AL~Y`qHoxhtAX~Goe_aH5AFncHUqc{T4sfF>MiI?95;xJN#zC~2Pxr}twv=X
zw}4zC4>_ahU#NAIcy9q{u;db5yktrBI2cnb2|?ZwJ{$MjcQF5sr0H)6K9f}J1nHB^
zO8tLRz*XsZ3ZLDQw#kT1D$w%05r3c)BX>`F${$E=(wV!!(j`4}6-v9M|84@rQ)z_<
zeKX*dboX)?-7Ed;BM82ewwZv{S*FAV`0rj9hSG<2mK4xt^q1IMXk4Bu2h2)4T34@*
z&P40Rnm^FtP2L*(|JO#^Cj7m&7Qc5b5rDb7VjQF#nDLZa;>awc>ByD2Mmf-KMyBR4
z0DKs?ZNNXu>^_THL^&H#3Sw$jpe>3SN>Pw#=1(Qmo?=G+0PB+&$xv`6GmmS~mc{%*
z4!LZGqc>#^v)~xS@ln;c5YJ;eo<ks?NhKdj0rMyWD1}Vy9<UTK#^Qb&YDQNIa)vof
z%Yw7aSGFMMn8wAxKF>IO1NjohhO#G1nWN;%yTF8Q0Lw+jksQor%puBkEoZ#m1F2vJ
z`~wwm=+I4cnNj+~ib^J!z6N=P8FLnLSDA0?P<f5{z-WQub!HT0QQl%=e9(*A%#H;Z
zuX-j$2Tcu(0n23R9p-Hdthmd(9}SjvX3qd%cQ9`2z|zSq_knm96B&&mxzB9*1K1B3
z4-HTrGJ`mjx|tocn@?eXTM4jCb^^^K+3fo_$^V(lUhV-ao>ubr7PG^C2FyA3E+w3l
zvhUxe9<rI2A$W<kAqUA7R%{1L6&tb^0=L+A6p6aWo^*z34&0E9a@69V*iCznAhzi*
zkYIL44n#v(Ujhncvx~qS#u_cZh3arNmX3}_uphfXE|NWe5#~j)uirsSG^@wk4ztep
z)1f7n9sWB6<JeP_G<A|4LKAU3TTAQo1h!8O&P4Wea#EaPgA>7-#Ga((U@{x3f}#|*
z#1o}d_V2&ZcAE7vzJqO9?2;uY7PA#WfH}jCBbRR(TWOEBa<;Yx##FFLcfoRrb^I2W
z@do?hR;aIGXIrDKmOYn((oMGF9ON3=FaJw+WK-z?Kr=gW2ITIsF}p!p*r|IV(8~JK
zq1ZN7vW>>SoqbgfqdHiVr7*FReYY7fU2G8fitn>OD==&i*l{#TKV;oUfU}$J%|zQH
zR!b)xUa@cA;4XO0HlKvOJ?wDGJMCr9k~gJ~o&5}zZ`e;t!1<Of`5L63?eIq1LC(gG
z(kflJ3Ys(zbN!7FJi`4#zTy*HqZT~=+}^t=g>!FpV2R)wf5iaDb5m`hFo8Qx>*h4>
zSBku(bI~o}%;&y41X94gpv6oH7g2-0lycdW2z-HS^8@EquG<>q8kY?Rl@T8!y?F&j
zRdLT&fwh{mq6hj0mrEzCYPjwr&|Ay(9D$~r+(b&2tmC5gf#nugJOjqu=DxE*Wj*KI
z4${D790a+;Ev4n!UCux+^+qly8(>YG8$IhSoIVAnwQ_y4fnsdq_EAcDJ2#NFy<J>2
zEs*YW1$`(z;9@R;^&uA&4Z&_MuM^}6m%j+)Dd)Qa*v~k#aB#lmZtX|69VB}s5O9=q
zP-dT#WZ+7W{SrS4$2d#Qe*n${5=#n&ACmlG4n?j;$%nHrG#--J4p`$U@uUP@FUbnJ
z0}o67rQF3MlEFLCc2e>aWooBM8gn6#FKNmF=Xpt399S+%)})~Fz9hn)uCH`;JFGY)
zTSp_~A!~XBaW9#90a$!xA2k3vK(^>KDg$Lkb7vHTWCO@887%ud0VG8BMLR&lWSKk+
zj*ul<U@W6#JCp#8k*QfSMwaYMcY-X_0-y;pGjfq8%Gw$scS<(=Ji47M^DG8Qk@eJr
zq{>Y9{=b#A;IkUcOXkszZK-h(EvSF#R6x@*ucfeldFCKky`pm(m{vy3#Q*DgEXt+7
zKccB;!=bJCy)oh*c>Wwc2K+lqY=H1r5v>&de&mb)cbQS5)9(EJ=-L0K_k-V=@z>GV
zGljGS@MPAkq!D5MR*?VWFvElc?Ff_64C}p_JBNVk&n%($XaKW=p720sJ<Ui#jFj&2
zV5YJS&?!u7KD1>qo1KAHz+9&l^f_ku4v;ct>`<^=VM0H_Fx_BYq{E`y%$}JjHRJ2b
zFy=n9vyIkYFPS<SKpogNTF-d1S1Gy}&KeK>|AdnfcBnYQlu`<rH`6g3vi?j$Jpcok
z-@b;)flSY6kRWEjIOvRG%0CBZG&7uDKc|?*bYwS)86F3LWM&Ml2U8e#icVxRpUk8^
zSPrw7Qo3>(Z7XWeF&z{TJ<lwq5b7mn2E8#ZGmj0ZtYOS)e^tv2nE<rA%z^}z8kx_x
zK}8cYjj|1znIrRnlEA)EfhCc>-a)qnn=}PIPhz)~fis!?p7tdv?6Ofb|D>{`Y1%%`
za{r=h73?Hh*574+9Rh`+-0DdnVcgK)&=$_wR6<1rcaDSJNKP1zfs5k)r6V5E+>ybM
zi{Z}vh00iN!w#^-affI~PICX-2V>&7_dkMZhb4-kXgeaw!<G?e79@Ysd)7xXb|*S|
zRI;5sna3ohDX{6dWYH2}`%1pcM5Uj^$^?}sBx6ER@|S$v27v&H$pYvNl$gIj*AB>D
z&Y|AR5_dpvl5DFUr8L<qTA^pkez$-?wrp1)I*~6cOa+UvP&SITNX0VQF0h`JjaGy8
zrEJ7;uzHxJM?-z0$xtmSFPNOqMycH7`(3c&hKU3R68?M7cCrbyJ$lHFJq^2_uoHX1
z_JZ~ChCw}SGWnTYxTQ6;4!}R*>I~@nHsJp>ckMw@URRuZzugZ|h^t04$uvO|qpJhE
z-@*b5h*Y5BgQr0xpt!6HB9BFu$5@jfqOR0DXhd(oCZf|!MUY5qvq}mf)`V)4U}735
zQq+Jr(pE)9kkr`Up{6tauaoH?-PzsqopXNY+;i{V{r0}M9woA3N0}Fxm0M^pM@%R!
zfQ&tz4ePi|G`Ak#WrsYWl8#eK-1#nyQ)_6WMB2@Jcwd`LbA0O(ui-j<8=W-1z9A9;
zn49BawaM;->zoHPkYYcXjQESn>wtMFp4y-<pQDA}J6UttOz3y9-<*NU!Pa*{x|?}W
zcdL@M&}2>{%liNZC)i*cAT8_wO@Xzu%S)j9gca68_$fO-8RScrdJ3U;v%qk~+sB^n
z1$UJ#cLn!1Rvm_nj<AL^uzSE#AA_!fFV)icPbJ^K{!x?V@p-g0E-G^xO5!KuR1u43
zxgp=9Y&#u+GRDTJ>U_(L!EpKyW@?1_Lw0pPV%o-cErqaxe?ik!JNQrsJUO^KEnMBr
zM=k=gm**XW<7(dI3ho$Rl%YobZ{-EwJZfuq^74HEbn`(vIOxxO-eq{~;UTn_?;@X_
z469x~OoPRPT(bzsYy8Lpa6|m)XNc>sT*?RX1|Ou(^G*KgcL?D=-@XDl80Q$(M1xz}
zd>`a>X^#`G-;~OJU4TqhOX)jdxKBEUd`;An849(w?l5gBJl$o*)aV^y*Iq)J_gLs&
z_#I{E!$HQFYaoOb{G@pz+hL{nKwss5GQ#a^+>4sI`?#eI=KJ}F)N>MiOE-iExl#%9
zvN|4+2lf!ZxD_cK=I;*ydX!hw_M8U3*8qz~KKB4(KEd0@k<xE@BDI8Dc{I%mw(*;z
zNa+*)@GiV`@Gpu`MxFdLty4MAyFGyH;hFTqdy)UL3(k6ZcNT<y;r(>5NM9L`{1ud!
z_+dKy^)kOgD=@F{*b7Mh8~(8uNI&0`iLBk`T{OFQhnKX2+~sr2s7UzP8ra?AcV<91
z##?Pbj`I-OQ2H%T=?7OKIcO=%4k`2*K<cCv8eeOWE)O7>52dnhe<-^o!w9@xl0vQl
z^LMF&`gkMKq6Fw3NN=A7bf+qo=B|b6xg~JgplXZ;*QPo^?Yd6Yf<c7cuUdB)$Wc}N
zbU53iw$M#$pZdgAa0k>$Rfy@ZdL1n@KBE3<F@(R6on<r|^NxI;hMf<}YiaDhPL3K!
z(bUVEX+o?)&Y|J*M)_45JZX}bG{Uf19{vj4`?B8}MB$XnGhlE^POd~0AIP`pKJq*H
z77bpv$;N9)uw5>pIn9scuc<2kUhbpi!e``}Q)#98$MOxD%{(g`JAwI3{t<1<`&^Dm
zMKGQ6E3d%*g8cKhAKmSizD$kuXd`vam(|d(>~aqo<||s`Az2ymGsF<{I(>m-HMKB}
zGv0tUzWk4{N{DGfyor_HA%Rr^V^sfMC|-y#lL{8X(duvq!b(0))7)!9b^w|(<pNy1
z=+z8p>c%X%PBUDEcAYW}F4C*iNM`-^>yVi1ci}ywXe*GGcWKksh7AMoV4X1;@=RB1
z2V}ibhwF_VD<IFVo($wBORhhdoY{M!&YfC|81q`Ip~x@U4~fmV6v-6S(ZK+lpY1~^
zh3&(*wyU&|m*&LddTU7_<mIe40{Pg@yaVB*onddF3;jici{$c9tQ}_Fx`^PkRWINf
z<7bE{&af_vj7nF06}_+WAF{N9+~Tb4e0!SMe49nZmS*Ss83^aA_ciDZetM(9PciBP
z(u!=hTzgtZcD~NnSC^Zeq06#Zbmqc5pL|=s)yHbi$kr)}ub;0%`tP6O$=mFi|BFDr
zzRk=(D3H1TRf&kN?y%>7kpKU2i95ty<`j2%)*R=OnbL#zLL-88Np@?YU1u>D=9cOr
zt@fNETY;{~=2NuM>XT=)<?Bjqg*o;Dv&9NbzE6?WUStO@qd3cv*&#VIJ5*1-DO%3C
zdOHrKsGWyW<nry}p_ddPj`w+ZIc>dit4f$!Jm(8;berXjydsxe7o!gMDMH^XYaKo3
zT=8;q_MCH<bEikIib`Mo<CRHK-Ug$7;*sRM6fmjjmgx7Crip|O$;<iLyve#KQMG_S
zA>KQ!mW8HInk(KosB&}0<xTD%aZ8MdNRNq#Gl-8m-5+<DEgnv@#j|_0C{Iy)JIyVg
zYVA`-#pI)y{1vVDzv`qns<J^Js2E&aoMru<vpu~{{w8C9-s%@%Qv5BM=AfV;s}ks^
zSCotm8v^~U0gm=to_IaxY`--{6*LJqF&B>S^?X<7=kqmRy0HRrNYTWxZDLr_l(I3A
zZP3JV&3(~g(8O|Y{K2%JCYJp{r1$|eCh9@B-d&87bfZ}24{4RC0pa>dV#puTDq%80
z+Ab<Vc(jM;F+y4(v;h;?EksU=vqaj(6M?`4%@LadfjJ^hO|U1#q#&@zMM}^FwjP8B
z-4o*^y)2fQz{Zb>S`#AFNMZ;S@tcAH?iQ6GJbbF?35Ik`XhSAkY$5WNI19pEW{M|6
zp{x?wp<wk-ixy(v67GvgJ4d{@2#)o0#8FVTTihq{tmnk?FtEo(O&DC&iR)pSg{(=;
zSgd)L&)16J#hT~UD)gOeg%u+9j;LI$na2i1GYAjTiXH-l4tTowi>U*i)5WZCjfP4k
W9H=Uh05WThR^x)BasK`I{_>w7eCiMY

diff --git a/Debug/Core/Src/test.cyclo b/Debug/Core/Src/test.cyclo
deleted file mode 100644
index e69de29..0000000
diff --git a/Debug/Core/Src/test.d b/Debug/Core/Src/test.d
deleted file mode 100644
index d1676ac..0000000
--- a/Debug/Core/Src/test.d
+++ /dev/null
@@ -1,74 +0,0 @@
-Core/Src/test.o: ../Core/Src/test.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/can.hpp \
- ../Core/Inc/sta/config.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
- ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
- ../Core/Inc/stm32f4xx_hal_conf.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \
- ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \
- ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h \
- ../Drivers/CMSIS/Include/core_cm4.h \
- ../Drivers/CMSIS/Include/cmsis_version.h \
- ../Drivers/CMSIS/Include/cmsis_compiler.h \
- ../Drivers/CMSIS/Include/cmsis_gcc.h \
- ../Drivers/CMSIS/Include/mpu_armv7.h \
- ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
- ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/controller.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/filter.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/id.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/headers.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/iter.hpp \
- ../Core/Inc/test.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/can.hpp:
-../Core/Inc/sta/config.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
-../Core/Inc/main.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
-../Core/Inc/stm32f4xx_hal_conf.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h:
-../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h:
-../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h:
-../Drivers/CMSIS/Include/core_cm4.h:
-../Drivers/CMSIS/Include/cmsis_version.h:
-../Drivers/CMSIS/Include/cmsis_compiler.h:
-../Drivers/CMSIS/Include/cmsis_gcc.h:
-../Drivers/CMSIS/Include/mpu_armv7.h:
-../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
-../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/controller.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/filter.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/id.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/headers.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/iter.hpp:
-../Core/Inc/test.hpp:
diff --git a/Debug/Core/Src/test.su b/Debug/Core/Src/test.su
deleted file mode 100644
index e69de29..0000000
diff --git a/Debug/Core/Startup/startup_stm32f407zgtx.o b/Debug/Core/Startup/startup_stm32f407zgtx.o
index af9b2192dc035bbc96d7e397653377d923d9d939..52f31e800ac08d1e1dadac3fe3b84525c85d34a4 100644
GIT binary patch
delta 313
zcmX?O@xWq&0%OHSMRg_tcLoLqCPsNCex`6Bi!pz41e1${erR!OQL%n<Vo^?hvA#=w
za%paAUP-ZjP<V)kesMu!a%y}@YGSUwv!kD`b7E0Syl;L=X-;Z<aDG}zd16uO<V#E`
zqWK{68W;r`1jIwdnfavoRQZHiC;Ku7Q*Qh<=B&+jENvo;8zvu>n9q1)a;juGqr&97
zlKxB#;*<5Hv>4kbM@lI(Do?JJQfD-nyc9^fO+E`GBPM?Zk_nS#rPWy*m>C$VCwodO
qGya~OE3M90F?lMG6q&piNLoyO3M3^a^UA2Rc8D`Dyqo+{LKpx-3}2Q2

delta 292
zcmaE0amHeT0%OWXMRg_tTLuOOCPsNCekNZai!pU_1e1%Ivz2~macWVqesW?_PPx8I
zYH@Z+et~{TzHUiIs%~z6ex81Leo=ODL1J<$P)(k0NosLP@#H&9DL?}pnZ+lEF$a-r
z$P4DI%^@r;B8+n;-;|iocw};=WH}?x<d2g6OmD;{J4tCV)=tiqQf8E#JW)!WQD*W^
zAZauCA&?B1%qgwT=rh?+TAj6mnSr5ja;&s6<IBm7K+%-RD}f}_<cmO3W%5rT$ue0{
TMqQ#roPpsT(Bm+`2xR~O5~x;G

diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
index 34d8f7ae49f887bc3a61995e7da3f1fd6a3929cf..2c9b96705ecf9972f27ed18b4544be03a8c5b98c 100644
GIT binary patch
delta 127918
zcmZU*2V51$7eBgt@7=rg_GT}!#TI+-y+>n-B{8;GVr)?pH72>BVgn1HfCW+P1!;;1
zDA-UeG!+X?L{O}ND2NE}d+_%@@BQENlkD6%bH3kmW_EUV=FBX&U-o-l&~JMKc0p*v
z`yB5*m1Ru-h~8hgdd}|>S!SvBY(B><*Y@r#GJk3hC-Tf++K74#vs(KG@_)41Zd&F)
z?MzpZakAGP0>iNGw^@c|<L1bWip{q1jGA@sQ!yIW^E;8@*#Dk$jF#OtMrL?+<P8lY
zuxSAzBeMRdSw>>bD_BNmTO5`dh286{$uT-Mc9X>D*>?Y^83S98DKJKM@N5-hVzbIP
z#?0!jN{ofA*rZ~tET6+OHulY9p0TsDt_X~SP0G_SHCX=)EmM=7)RSXsvA*j#rZyY)
z6U)?LH{8}Tb=hteYNj6BSg&E~voXK$Oar!ZBFi*ne?R8bFyF8TC$mf=)-yrNG-gK)
z6`3aNz9bdXl=W{UFwIy;p~!s8s(6WM&Z<z$7VOb~M5ZPC(>#G`#f~rvOl!6@Utqpt
zD|_=y8+LSrmTAk5lC?}bHncv+v}b1?lbH^z7uY(oQ);qICpP@K%yeeA3tA`Bg+23{
zXS%Y?A1u?2tvy=HbZ1kiOH2>;lAD_8$@UFWGricF{WVN))>o}%`mh=KDyA=6=)*Jp
z*xmhPra#*@Ny`jiBj)qWKvr;9GlSSGZv<vAyYHrk8NzlrBr!wTI<krx#?JntW`?sN
zxiT|?ZGKhDI7hP4`5I;vJFK<Le9!ir$ueWupPs6jA8<FdCpycF@WTR$QSDQ=U>Jym
zzKujiqv8@*tC8^EL<@{Y!})L`BMjMtelWV`Miullyl*G;2Z5^_2L*wz%))KcaK9~D
zUR|aa7@@F`Wi)M@TmON+{Uk1qbGXPxu2iK~GmPqwJci*usmvs0RN<GrV})9#M;Z;o
zRjAA{5GsuF?2h+Kp|(Bulfa1GOhh6ZRo&TzgrDMFTdY;@(QAQG^=3`PBB&Ckp`g##
z9N=2-abi36s<)fitUg--#iXxAR+VQudUo>HTn$FKALo5bY-sHGBXlOJs>w7e|Nh<;
zVyz*wR*Nw9RcKVrpUyI>pT6d-s@276M)mX8Tn*LteLy-@RqbaT)nfEd)h}Pm8mMY`
zPnBv9xmX7OW_*>kRkiK{^vtihj;annbBt=%*IZZCOyc_WD_2idrz|a_n*Ft`uPVwr
z7F^j8@N3>z*%;NnXceRS?Q3qlYN!Dfng2C6N%a?T{r;8fXVs%B;1+x>o35Jg-B7Nr
z`W)`vTdw8IZp7ohs7yw*?@E>SCm3D&RnbKiiAPMe>}zfvqZDm~x64)PBB)CIbhN%U
z_9};w<L(|BKc=3-_<@e0IsFDhLUlRctdPoWiU!w*D|w7B+NN-ty}41%s2O2dL+=N&
zy?uHUE%Pgz|Az)6N$3s^TKmRmz$HwWgFe_rT>%o^yc889+_uwA*Ts3)S9-Hey?;?^
zvBBP}lxD39o-j;%l|<cz{?)+$>|Sm~T@BOx|0kXAeMf2LT-jN}C@Ss$qpiM+Zq9y{
zG^oa_n-s`Q8C$LMKS^3!HS_NOkbM6{X7c|J$=J>ullgy0CbZ<4d;f0<H^6(DuBEDc
zxA%UXwdc7w4HL}j$d&(@>C;ie1pL1xwV!*zIk&H(p-^P^c15F`26-3iT08#;Q!{_E
zwuaT7{@=B)^ZvQOuoGAd-2?hJ2LH2reF-LrYGwl4g#aqg#rnzy8fGGEBSn?x3jG*K
zWG1nWucd!6T%D&ZGm`!PHg4TlG6pE>`Sq*mzqYx0ky(S0uevhdRvWB4&O2IPlU?h5
zUtizkGn{AANnKxEW-)|whBxXudnR&>x~|MqiP~GGaMn{ZwT!wp&)M_6^_E)pepSeR
zqf?7|PI^-xokvk~T7U1}mL7v%%*L>#?qjY7YrawhvKFpZ-$Np!ZfpH2|6jo|1Kw=-
zr{Ua;Vg53JM_G}puk*fWS;WrpZf)(te&apc+SXY$3w`;2s$FKU!?@M8VP7r7b#t|1
zxavL+FH5e+r9}e6^^N~aX1D=~V<8_r|1VsJEL#N0&_<rnADQ(VUZ117)`$N0fA&%_
z+}J-cvUB5nc5@6j{`d(k0|e-q2U>`k>$RZH40q;JCjJ#r%*Jb^QSTREnRFJ+%(O}Z
zJS-udP8@ic!w>0N=_cWt{X5B5orZ7B@*AY@yiV8XrF5NrgxGp7rK?y>l4id2n;S~{
z1(|AGPlq|Fpt%>(*;?_qPLs&M^?p>G(Ur`Xspxm$Wpb<DFw)NrCW_}53H1YR63478
zCrSJQ`u%eR{gwt0_S@QoS~H(ek9LsxJK5xP>ngIcHAiqFiC0nWCoU&Zp)0AD_9MyV
zThv4*5284mOQhHDl8(@aB(I0k@0zJ(Qoo$^zZ8*yVc${dqQmriZYR1v_>FXqA0YW)
zy0=W7F~ny5#4t{d$yrbJUb>C0Vi9@GH6hi5PEwkXPEP!Kk4kkHh^S#FlDsIR(th95
z?+gD?OFTG7##X){0~J%K8hw7JQcY{pyjQdOdW19wR#)Toc(6H{mtCkHA>*h9Dfb9)
z=qQ<~_l8_qnMr`8#UwA<Ms6wBNxuIT={##iX7b0;^_xPHtfW55_*seVcT9v(ipQH{
z{NIxmLv<SreMmY*2S~@cu(~Oh%^~oATS(MzIo0){2TAT+Bvp?PqS!T=oVa<OBo9WD
zTc=7$QjYPQW8UB)<e0xZ62quia<SJjVu%bO!;>(aa?Hh!#M8|}E#X$(x~-jmQ|9|$
z=(_3?speJ}l<p_rV`~##LJcw&aEm0_Y4rQs2jt@P>U#WGMLIb%$@~Z#nK^`)6~}Dw
zBTeQEm6kjq{yTo;R(LX9Ct?1CzO~*-N)K70+tP?s`{hx=`5mN`v5Vv%ZDhD*^_{!E
zluC;+By&u}c`9ubPPJb=m`ujKCi6F{Z{Kn|>9qcVc-riy-<L4w#Eou3I(_`<dfTF=
z{=XrFl!C8PaYYmQ9kqx^8_y@D^;Wu`n@@(v?I3r<=8&<F|41^VIiZ@>AjvK}m3DF=
zY|S6&Hhn0g-*ey7?`X{Pp!JT}G#v=V$`bYeJ`0KH$H!DK;|-}Et{yHDstvz-Poy~;
zNq+YknR(ok>ODy$NmUY|8s<{VMR`$aw>Ct*?FMmr;_ZNrrX$UNx6tnu_eh@poH!Tb
zMUVdf%_qu~NJO#pUux=})y>Xj((khB;l-9j;Ou>*ne-F=_V_@hsX=7YuRmQIY$G$$
z-y~OkM`rqzQ;l~|AjzK&y6&1u?ylQF*P^|o?>u6qf|YS(en$1ZOvFk6wJfE2M6V}`
zD-B7qcm_#gHk0{(4v^&iNs@fPOa|j-I+?6tAnL0ZsdVxM(tMmi{DI@>+8PT4bh=rj
zQ}ZfW6r7mjVgT7m*Tg3Tm}w=YOMztgn4Ny-)F4mi+$IV0lztBlA@Cf9u5($^>3pA@
zShkr;$Nxp`)H{`a&&DbOH)Skow)}<M8nB)8mo+1uvnkc%{{uHtD#5E4qxWF)?z<IK
z-0%clTi+$;mh+_3Dw8O@-q7#WH^`)aD?+)gruwZ(C3$dl54d9{lRvnV6F)U4oo+4Z
z`e+!jjT%f<Eu5sH{=ae&73kU%xYOT6dTu;P#5r`G_koB;9H8GbmJ;mL&!m|WPbS+B
zBp0J9>Gzr5WGrY6RbYre>F=9OZFZpvnJoR6eotRZYzu>kXFJwq=>IL(k?1K_yd2XX
zD{7AE8cg7U{}QaMImtVOl7ZUY>FR1EoiQirsvAYuW9LY-W-oF}{j9nN)F92U$<;j7
z58;dI$FgTPGCXz)RdPlZemj|rxzwa%N(jbwB0!Co1nzN|NJmDJBrt*iP2#AoGh?ar
zRP}pOvxnpgrqH+rugUxqE!A>ff8vZ=O!`~?BK<nkNXNDMo#`7&PQ<$t);Xet61zmI
z7v_-@|0WaBe^Uu|Zy^y`Fi%92P9@m36(p(aLnyHewaq6?Q!(mA({<lBB)?bvYB5#!
zs+9i3{3V{Qojr-a{37v(j-%fp^?OjFxDxp2S}N!_k0|ymA?i?vcf)#iXN66}XqlcX
z1zhjnVR79NMqYgOQRDZaa}ur-Yx20}jjyg|05x3;tX8zl+wMd+>IpUDj_TXq_l*kj
z=Q&g-eI}Xg#*k*WPsBO8dRX04Ouw@obS-pNSARAZ|7Z$KGqudRMdbCb^@+3?D+zRQ
ztl~iWf&iu>GO)8RY1WuQE-v|joVIl!M^_Cb&C0#hATdP<wlM$oA|1max-R^cn*GN(
z;%~TsnE6^xYMcWYw6x5)<y5e?H-SGiplf^?mS;@K8&bWAKCERTF-6oeMWe~&$v{Fy
zVKmk<b03mhPr6Z!h3dQh{b6EGtnM0Obr1izo0>f+RHg!kt0^r+D><9u#xPt9;ZHQ{
z0OoJ}9$$4FHJwnW0>wYBcgOFE-Ms;w)Myg?pKNOc*QP9`o;Ry<IeyPwK(CY~o(|lM
z6@MW{z&Q^$fn+TkG8oP3!A?j(;=^Xs?8287Kf*~rcG?}}cCpU4|03PZvTwn+hYgqp
zqyFr(53stAP49`C2e7_Jf#1*e8VO?u*r3PI3}oL<gR2MGS@dQ&#7@vbc$kfx4&f2@
z-Flcf%2v@!?il-K0?3ZDBfEk61e-Y$fRpS;SJd|uJKXsa+(B$24brFCV==%7v*{Nh
z3}IP>+PF|Qo8EU}?ECG&hqDv(C_BT>+yU;hY}#|!jbOjCL3oZmK?8Cm>*WWs^X#+J
z$VIW5+b|!^`kn$jhV32#;RSXdjiwjblYulw$FiPSNON)QcQo!?VvmGE^)g%L5A#>p
zDW{R7u(@P6l^xI<ns?c5v(VW0*us6_zR&iI2Oy2*ufx$t?1ib|e$39j23$H@heojs
z_H`R1Ijr^r?B%kx?O@4cBfJpj;-0gGQ$h2B{i7kIui3nV0KQ?Ht5J)0?5<+46|#~V
zCW_c)OQ2cIMzAP*&#o+hu!K#xg4_o-U=+$evhOAVP|EV9$d$2cTf@<EHmnrXpILo5
znyZ3!yMnSR))%+e$+@b8rYKya8sY;N-Bp*h|LdSlU1`kd=sN<KMN4UjU0e|ZOG}20
zh1oyuQjcBQurC8|@!vPM+CZaC#2=8hZGH&VY}dI9<n2E+gRu@LsqgM*ld-O;R@ba)
zh2Es~bJ8rE&ut1uAtf9l(L-dvsx)+)jrRQZ&@eoNYgr#!DXn8)VMNz%WQSfswKlOQ
zzs2CPneC2+Fz3#8ZGne#AN$)ZkOi=Z5TZpp#14g9U)Xs!!R4lEM7?&is`>Zua;GXK
zkwN?KQjI=>Y=Ekz7aAZ~HDMuuv8qX%0lcNMS7HH66*L(Bg1pvLT5mPXMvRARvv~vL
zy`lstj;r4p6<k=d3|9{}SO*u5u%5qxFow0S10<2HAA=F3gq?NZe@!5bnSpl%XH3Va
zuWcEdifXo!FdS-IXSrZB`Oa${f>CWKG^lM`)DKl_mym~Xr+ugi&D0?pfeEgo<uDqz
z)9Uf?qqETrd6(@WXs52-uHo8k15HG_r_f|&z>k~Y<?wjKo4K(K>6I{bQ*-Dz=QSP)
zqCe_=hvJoj83nHF!JVkxM)vUEAopg6GQj(?W&<<=*&rE75ZlBEVFbd(@H&#McK$qD
z?R^wm?S3>{?SBkgU4aWMd9A(7R#)T-OEsx(Rj0H8v0KjeG!u<mvvdS}sa+flw;PU)
zg{w`xUD2S;_B2F8wtim^rR|cvfb7ugAXV@eS|0WKE)kMGxl7^Ez_4GzHf#VbiN0SU
zLw{WHI)vKj20Gr}2V>owR`}g0q8Ds5k6A-&lukW6!FZn#TKo;WNGr{8F7(v7uy<+Z
z?8=(=f@lqUYX)+D?2RuV-^IEh?v8=8*CI4hAlq*ZC=Rmba^McJ@1MYn)9iPI3uZr+
z!EOk<+X|IPcGpY5&$C@ap&7+G|L6~^SJ?%wKwM*I#y~ZmwS}NA_t^E5p>v<Dp9Z^W
ztg|EV`Rrwy>_2B?s4_3u6gxCOvPE|QFJ<#v!eALYcngH<RX(+$xj_}jf@PyBzYc^x
zDzC;!d{qthg3M3#*@+zk?ug3$7}$=gTvnj)nCkEZ03%e9n80!8RL0f7N2-cxRTr;X
zPLYi3s$Lr8l2qp@-ts`T46!+^DVowP%TnDU_)}F>6xudlm0yb7E7f5$n(L$L`@c{Z
z7j@-dz`3c9S)D+5sEwXb-J%|iw<zbQ);xvXUFz;lp?XNITLaa@YH1vjP_<tYEQP5n
z=YsT-S~VW<%jyxBrdQwM1`me<)9Bq>WE;=vfQD|e#N~fw{cm7K!wsmt8>R-DFX8u)
zBQI!;I9JR4uQS$qHVyS}uAUFpR`auQZ8NDIuI;CP1Hw+}jp1I`t$6KoJv@Gcr1#J7
z(BA#>$HL!%rOTl?a=nb}`0`DV|EzxjQ@>_>LFs}H!*N}_vlI+Vn?FGvqP07xphnIZ
z?QTyPy`a^OM%h(uHr4E=w!4DDRBhBI7<;6>XaUo0{=!^nzUOcBgo>-^ss_MQd^QZ4
zXY{_bB8t|BRKc>R@z_}8b{Km`|F7?#X5Bx)v2^wUHE|{z^$l`atSP_=S8~{?b;19X
ztrLhloy#^kg=B~7OcJc^RCPE5MqgEIEin42rkqEzTXnk$aC=mxjlkxwO8$&wpDHf_
zEc;c;6yy%5I?|-|pelJ3Dt<_{%LiVbRn?C|5~0eb)pUv~a*v4iPgRvB!^Az6{1L$W
zs-tNDK2W`*$kIbqHU*>}t0HLKnyz|49W+xlxGRKNs<;Qxe4-k?95+2jl~IUXuB!VV
zsM<4CCB+)@RcsaN@?13;yH{L+DsmBUFI8(0b>&{G#<r&z)f?4~Q{Z+{Us!`eS9Qb_
zBx}{*V?T#mr*88L++VNu`2c4&sO^EUbWHuu0^xD>Cc0Ir>a!P-yQ}sxf#tsX!AfYR
zshgaI@S(aBEf*iDlPJQFuI@!k=M43AT6<-wBWDBd%vLYBgY>ET{cJQsuKM?5$mOYj
z?*w4JdiiCz|3bYo9k~Ma5_<8zQs1K&(QEZFGXGX>+=tvdwHu41NG;a|OR?IQ;%Fu6
zyX^q~pf2=7u2ik3+f=6RNN<I5_4`}^K0DQoav=Spj<P_tQaxlTYUrvN5{p`_(M($g
zp_`@#1x(j#QVzr5M$O_ZRCJT()pFFrU9%tz20b)!c+9x18in4{+cYjufb-OZAB3it
zM!*Isw?p$Yc1XFMnr;J8=Bw$_6^Wn58A>69JsPj`(Alfuwj;MsGd>+&1ZdLg0C7NL
z&O=$CCKR2SJFLmv4lj;qevO6u$21%b;Kw!3Hv@1|(_;_-r!@ZEkvpx?Q|}DcT=at%
zp&GsqaABGb10X!33Ccv3&T2B989+p8eCNTN^BQMYutjUyhXNm?Y1k4v7d0v5cdRCr
zR*RQ3(ioIo);zcaz*S8nBfPk#DWF-_b<N6$5Z=%vVsDkZsqv~0w{K~}3`p*1x(tF!
zqUL!N$dWY^27o0+v)#`LZ|-U$9z*AzX8A+vJDMN+g64tder+HgX%cCqeyk~_plgO^
zK>?CX&6sVV$=0NDNS<hV(26lvQ+^jL&orT%kmPFuJEQEmCNT>Z3N&-tK=@L#;t7&B
z8mS!&z15U2ruk2yMx?b^k>=JKaKG0?A!N^$Xri*vULQ3XJAo+G7*>Prlcw!Rl$C3;
zQ$bpxxwjO}^+hx4I8<D?yB`2|<-A@3x0Z{Ufks%zMK^<M>$$Q?Xvz)TrrNN(iPP$V
z+sq|k(ct7fxCJJtZsE#i!o)W219q~x?OYW-cwSuNu@HK5{jWg9hl~3jCVaU+Uc%rm
zE<7H>-JER%xc73UEuiVo&GQF5fSVbQ2Hwy8*&8Z>oYNJ!gWR`|s0VQ??eP8x*FOR|
z=W)(|G%TIq&d`eU6j%QwRD-zow5Sf|LTFVR!u6(yBb+-^2<|gnA9`6va4j=n_Z-(7
zTio1vt{=s5qqr5cNRHulKZ42y?)G1R$8rPw0gvNO20-|LJGlqBhg?%ykfb}gEkgjz
z;H;nFO%|sai^6Pf-8l$zxYtL3f6Cn+3QNzpJskYb<Fs#~@|-JZ0cT!tniM$dqP>0t
ziK}+*U<lW0J1>P#>$HDNfHUj0hx-7qK`YGz%O>slL>StvJv|cCTeQwq6zJNjjipeN
zr?w@%*1WWHZotw`t-%C@kG5bvJoVE~%tkxy(!RV5l|9<d6ph=fU3v|6leNYH$famq
zW<c|v_Gtlf_qDBmLD>Uss~!M6)aGtO?y=TF0pxV;iZ0O1)HZf@KsHMo)E^E%(K>X<
z<!IFu!^zc-tqq@^X=_qEB47KSf@jaQ3Pnu{v{B*k@TIon3gBLA|C<KQH`<V!uvDmR
zpn$tb8xRSW5^b#%;67+?orh+bHgE~N_@qtvfU*j0?WMH-`=ZT3+<>dnswphw!fQUm
z#2SA51C*`hPgWs!ntxS}B$zM%2os_Fg5fX`#y<@J+ZmpZMgyPaSG5D_IsPccJtFzh
zI@pckQ~v`?G~ccXgcta9+C;j@@1KOSIKJR6kLT|aZ(0WF6~66H(7DS0dmfhJc`xjV
za@YCQ6q-!n`vk)7O<r>dWw-flIDf$1;e9FolEmjxls=i~=*^MJ-=szVUH$}h#QXf|
zZb;JjFB?JqkZ<!AxkvnuJQ^>ZKl+7Y)ERsr&Fr#x6^<lu+5FaN@GXbGHWGH9@*7HE
zFpr<L6}fzVQviSkeB%ey_<Rf6O?$(qVxO6N%d2P;rif39g%`zqSUV&i_`jb5_mOuQ
z0hLeuwe<j$^Y1C<`h`D5F#~5M|7AED(M9OeA5vFgt2c6Mg&VKo={n)(U^ug0Sb7=B
z24Qv!AT|lLAHdRPVIkGYL#Rmsj4i^-1SH!8pKZ|GE{t~q?j?+*Ug9kryoO|_5WN;Y
z`3U)O@aeLUIvBOS;uI2wB8?Xg{tfAM;UooTZwj6iIJ_nNc^j7Q2<mc>CJL`~FqkZK
zm<nNvkTeKvcZG+4;vU=+;se0)K-lO7+(TjSCulwv#{ULky70jp=Cgz=CxFWq?$I9F
zQ{nXiaOMimy2PC)^m&WIe8I65_!ok@FSrW?cNzm<3A<mQGOvY*5P0}j$R7*9J3*ob
zE)wjckrWHxzeZV!;8_CiKL{Q}AS@Gh`B1A1Z5PAfXJKtDautGSYmik59dW9La}nP=
zX%l6Q_}wjJ*NQbKgWFA<Lyf;)+?j-Aqd5OKYOzV|z6#E`ivi^@;USKD4M(?%7FvvL
z6ZcGqrl;6r19D!X_kOVK6yH+p*GD{f3wHg){9xpEiI-^=vRC{j4rKmf(|vTG_KQi`
z&^aLfLkpdQqW=a|=8)+72!0<CqX)s#QPGE@6UW7KuaG+-UT6a^PKixuk`^Q`Gb0HW
zTfc)aM4WvTUWALI`@xGdV#zd6M~KEEB<I9>OHh|IF)0)*kHqhjY5xCMJeB}_h8TDT
zNv2qDBJ5_1<rIK@BEAtJ%oR6w0q~hPnC5!<;@f}0{aoBK0i*?De|j6f6t511@Qo<Y
zp5t4w-&y2}L=yt5T(M|R2E0Vf`yR;$@dB+kO2vrR44%I-F=05W_E{WG<|{;Y7HUx`
z9*YKPm6&!8cvq>8H`vxlGt$7lPTFQcnVVEjLH`X>qZ?4!DE)Q{xXn`29B8^rK4nnZ
zBBgDB%2tV`&9m*&e45;ON||d><}I}u2b^<<)N3YyJ`(GIj<4i<7>F?G-4qDJrH?dT
zot0{(puHlb)f7F6lqN5Q7w4rV^u$C<P8nq}()3i6U6jHp3>_=wbp-s96tf$aE=zT2
zo^VwPt_8p~$)g`MuS>Nl)_%h&)hvcnH>I3~AiX6mpM+eZWTj<ZlBA|B;8ZE>50u@N
zeoTh&zGSmNB~7a82uly8b#-wM9!bq-!$i8&pEm0<r1X5KWJ{x)AooP-9}e78sfbpt
zxzYn_i#%yA&1CW==hz~oFQl!sNn0SfZ2`?IsqsY!UrQ4a&F0=pV<w<U-bw#V0$Y*v
zO9;w}rAGVVT8ZR?(^}jIX()owT$vQ>f#j34ttVRTvvdxpoVW@pjwT3|(wTe!s-%uJ
zA#|1d(2nF9S#j2c`@7}uXnnFrZaM;ZfBBy!(Ag*7r&s%anePoR4#*A8!Tdovn&y~?
z<TBa-I3iyWksOtKU4+VUIi@XI_Jn+tmI<fiN?JJu$#?F<Qm{Ob7H1*ySz6VG$(waB
z6fO_^;6(PUoZk;R5pv&eVK-9N#iG9F<<^;Ci<V>VB8ic2AAvAd-q!`1aq^S%$X%8f
z(6+@D*|ZP2c=<#mTIRYu<tTCq@(}7lH|2N{Zr_%F!eKe?j=b&=a!ImJGIGiCm95q5
zKN({c?yr2D?)`mvn;-CL@&wvMcqsSXjNBtRyAgot^51`;Wi#X<v_qLCx1f-6wtOxE
zxEy)sQ+WSW?l2eJ&*aeEa4k=sOktAe@&W2yFXYel0DmcWr2W-b^5wHKp1&`0yHj9u
zQ+}9-#7ohSMw5CggLc5D9m?FkFuzkd^Ad@Vvi1vvz6!q!iJ#Id5rAFFhT1T=M;SXA
zxxI?I2E6cBqV~b3eabjm1P3VZ$(jAi_U^zPP!gIT7pUyH3PY_AE3c}6IHHWN0~e1g
zXK63|gkqyn{<d<T;z@Uu&NRLzDsJAPU98T1UjR>4B5AMSuCkC6?<w}WNbW1^qmZO2
zT`ag04-{XDQa(}o>mkfh<aem`Go@)bk{8Ns1-=w0rL-yiQc>KfMU;VUVeYk3M!QsR
zl=#*EcUYx9?J9iZT>wZUXNxQ}Y2)BasBV+X58!mu#5r)U*{zn4e>=J>l$syh0lpUB
zQ8>S)*LCQ$@}tF6YnE#FUDH?atIca{;&5$;3eay?lj1h*|4s*IhYSiNcbqf?s7|$q
zLBI3lc$n`}qZs^M-#aOQ(=Bu%=(;b8!L>&R9&|mYx`VFQAPS52G2g?rZ)ZAg(@zY7
zPX7$-191axwuk1xW^`6z#O5K8Pa1F=zvr&&1(Pca5@BEsoB0EhE$qz(NOrRwYC|o6
zy)y}nhuF)@sK*{>Q|X?aX3c3l;P`Jdf5#Vk?!4<y@XmujeGjI$@TY11u$33-ZMThI
z?}M`K{1S?fc=F9CO6J9%rs;<_|1B*FcJTjFjBqF4U>$@$yiyyQzWlGnNc{MT0kFA;
zcb3uVhrN742S@|>fi!E|&-cm!;sC#o8X=JPqjmdXzT+Q29N}ARfNMwj{4*#!#;1-$
z*>QeucO)lx&*|{uB){W#*geG`s}If~eyA47Y5s58@(AX?&@NC2fA&uZL;03YEwW*}
z`>#mC`9UH~oZ<T!k(}krJke$myw4H<&+(6GNfXI;qc_rd-jx;wQT(#M;Y>8YU?1F$
z;g{`zPZ#(}S5S75Pp(7~%d>G1Ugq=Yfx5!itpP``@<(YJe~sTVunwg0{KA1Sah*RK
z2)}Re;U8f)fzLeZo!-6H&;8p&HHi<&gi131j|qSjzQ#b<P36T0xCi(7K?G0Z7g5yt
z0pEd6S3Kme^o8alehZyYdd&N@gl0M)FbDO_;CIO2%;X<?|IowgjOhUfb9k5LfIa2$
z(!_g(_s9e68Gp_VWqEva+DFgl*EfNk=ll#>(7fPfvQxkZ$HLo}d<d=1Uh%bQC+{^M
z+Z$z=Ow%oY%iqg~xp(~PJxB`qu?gTT;)5w3U(9pP-neJ)`J8(2tc2&i0sO$%On||U
z{Mix+OZjIMuq@}-KST1FpK%Rkm3(#pG^_aOB_MSXMprM_g=Bgyxe0a1#0DV)XO+2)
z!fGCxn}xlz0e2T>lt9Hp7;zG1TZEwF6f@i^EKftVw+SsNfV^FJ_&Z2F1ryDGy@V8c
z^LYz}Pl4Ydl+sdhr_g#Ka=wDq2W)=Ag9_w!33YD5(gDG1K9WEo-4Bi)6tpyxIwY|4
z7C$UJp@Hs*(9uf0Sol<-!4r5)=<5K@aiJcCJx>Vk6zDoBd^`)EP6+{YU@u6>q7zQ1
zg@~n42^Q+h5QYf86j~1zT*g2cCiI8{E?k(_3%N7G@TK59E6k@=Lxj+PB8caNJRLYA
z1&P9Y=Y?)3XwN1}81V_J(Sng?5ivr|&cI&~{OM5QMd9XYl*I}^Q?M{jcy$)JOF~&s
zSh_3})A@rd!l+FsyDCg+2WR4i0X<Or>q7HkAiE(vUjdZ_p+zk0-V|2Q$aqT_orUM+
zwlI|9dd@q-Kj|=-C{#Ry!6f0gIglm`t3N^~MMxY8OR0jL_KfceNi^2p6HKE(dSCFy
z$zd){=s;t@1EHKI_z#7USHL|IE>Vc*v0$RZdg(&y6mVt;?(cCcGKG<}Y|aw8tcRo7
zPT_AG%s&y@?FV;`;2i^+r@|2mz~l-oDNgoGXz>qJ^Mn@)H1ma!2;`m%UKCh+A(+2`
zW`S_wI-Geatc-@GSAwG%%3ceDXbtd2h@?=>TcNxY;O~UdrGOU-yJ%)nBsdEqfG8Hm
z&V=;6V7~?5N(ARjsD2RU_C>YVh%48jhQ4C$wb0xxKB_>S_K2HlCv2}+<24e0F`h=S
zed2Q)-~r<KJ%H~QhYm;C0denQco--~(`MH}u{oX3JS2XgmD^$QY2#T)kBG_wBu7QV
zeBh6X<LGHTE-Ex~pAh3by<PiQoGWQ7GDM8`fJ&&SrA{6uvW;OWT-<yRxijL?oiK4$
zZ15v+5#k8i|2Zd)r-wOGoJ)bk^I}sP8luF*@8MIl7~BEy7|}@+lM7<PLO5|z+!}%;
zR>bNBT~18th2)Z$Jc{P)mqlkdRIiBRM<Tf@=Hjan?wZ(^-n;SQTn57H;y3-Fc|*K+
z0l)<Du^x?ZQ!I)?tKAZRr{VOr=;J-Tuhn^o;-1Oky>PgcBL3G4H!D>fJ`G%V#SDt`
z-V+~P1?7FQ8SS5@iNSQ<=YjYQZN@wl*{0BZB-UI4=Eq`-#b8Mn^*=zEAr9J!I%JAv
zeE`T3V`$cpE#}{W<`Z!sZL#EtHm5tBe<r@02(~=YokoUyar{&0JQp900PuylG!irg
z;uo41y%e`l$9pB-rroyJ;?d{Gy%C>MVEC>0q62X6L|-~@Rw#~EL8VCazKkjri~0XT
z_+H#eXLm|OAKH=nAa>Hza`mHFOq1YJQECiCnK-2nbUuk29cZ+2aavt?@mb8EfO3WC
z(;rRpMXZ+se5KeF=V-8|`{8Gpcad(jgr=*c+Yin)(zMeMu9fD~@_L<=6aY;(sSQmk
z)=RmQ!LmW>aD>Isw^5os1m-tMD}tc9S^A|AmfWR&bjHL(8nzH+TckBRU~sFnj1E$4
zldc>9e!Em-9-7NjY7h;amo#@gG`*!tnmqeR8Nb7luhiHDWq#7I$;j=JJfe~8mKu(R
zGkc_~;B<0(rQLQI^p_I6k?fQ1)2l5&x-$;Vy<fW98TbRzPfL*tl-3=CiGxyj1JE3j
zmeQpEuw)*DY9Eoj`@-%~Nw)@N$E0C&O5(V*o{ol|kebpI{G@cDJ={Jejqib6kTl&6
zPUmT<XeOk=QVlwg79w?yL@rcXO{b~DBsHx-!lel`ML8pVn~U68Y3N9J7$JEL0sfrS
zBo0ZWR7ESb^U{!Vco-#B`~g6;^yEiy#z?h;AiN;?pM~(EG(HxZvC;)PWE1C<LTRaW
zN!mIaq?e^1=rH;fX#_=fuS)AFc6?3BT>}&Gl5`3_U6+3PjO2#2G7!!rNO8xJyD2?t
z028+)_kUm_QTmm7V3L$Tk@IB9dmh>;MQTsaVyeXTf#zK)s3r{Elbqr7?!PbPT!c4i
z(hE-*d?3L!JY3Qz6@ZVVErTF@EOpF4k}mny08NI}n!0SJG?(H$S&}mh@N8+|XH?>e
zG<yM5a->e%Q1(>X@*ZWmQb-95K9hp}f-p~-c>$XF(h}z<&^(vUjDpS!DKQciEs#z%
zMd3@yLh<xh(wS*sdo4w}piXb3<+SblR{C!~a_=M^C56%v9D%?}deR=S6iZ9!kk@-@
zV;g9eNFC@g`XH^cg5{$$3*UcnrBd2|0F+7J-=gR5la#&|h;nJjG$1}p{S#4GAuU}D
z;TLHNZ820z9zUS=RZ_%Al)1>sWWrTW+l+QvBVQL_Vy*o022|F`f5bq=P4=LW_j>uv
zN!Z;WFQW+OM%j7|fK9SHZO(hhSLV~yV~gB#BC=cME_FfUDX*mol$YF|#v5;0pnU@$
zxi57nU->?T1^nc*bVv8d0dz`uuPh%#;xBKcrT2dMGflt`$ocLt7$|pIj0QR^rz9hH
zL>^iO+)=qMeJyc9cEOP1<W9;B&qI1jo<}piAo(|nlAV_C<GVJj@^8`nKSVwi17||z
z4HSb4lUL$%L@f3T4ngybT=xXn&dN1uOC&;m@CV4w$;~MoA1VKK3V`$Sn{Xsia!eA+
zqUD1XFcc$a(U~LX1v&WwvKQqUFW`5q+`0%ladOZEbb(89VFQ@IEdPEGWmn|gI5Njw
zl_%Fk?wY)C7Vz=%>L7S=UH+>RTIPm4j`rpfWYuVxzbXGjLAG1+CmK+1%S&lkzav+r
zgE~=uOY^oQQLZWnTe954yKu18*<mTj(&QIjpnf1X>IvLKxp@_8_DKG`7=XueB&|Nu
z<;L{DWyp(q!9u2dkKRpL@+#Wb%$93DhoL8OCUw9Z`EnruPvueWa4=VHPCJ>;<fh$$
z%ai}<2SC33_6W$H%Rf75yW)lXjt<rp$W!QK=1Y0&9(eIe?qNdNYkAcHkiL;0U4rnf
zy!-%w@8rs75EjapDF$04tDZtwEbG>w4c^PnS}<55zop)c!(tTl`6$1i0C=f<)g5JJ
z@`~2*@RQti74@KU`4Y`|KFdAm0C|PHY8MK>$gZ@}UMcsfh1RN)YbPM*qGV9)$W_Ve
z1i%`Ft3;WbGDr>Fdga{*nAo69qWiK@`F$Axo0PuUaCEbh*cB@7N+xZzc_?2-!QU;)
z@*y&whONp`2|C*po<gzP6^_p3c`7M?g4;_m(S*%g={p^W9ZC_M^x3Hhv}pHHn$Qs&
zUqzw4F+XK<N7&t^Om_pzZsq-O2=^#|H~`qI_&$TsU#X(@-KS(wKMGKccvU#L{YrlW
z%pXvKdf^@hD)r|<=b*BB2ZV=|T{NpXtX!kB14k6sMX1G5Wk2oi98<0?MRHuR{|HMb
zluRBzom2v7T760hrro<B#h+GYr<HMZjxbn>83SR6@~;gnp-Lkc7;=UwGaAC1aOE3{
zzn@X6WRRXyv`vwVRGL(xNzW@*+A@k#>eI$ZwDL1Wl42D2j(3c51K(3}7nPVWu*E9s
z7a)sMb}d31UQ&KO3ixHEj5bZKC~f>uc2zmr9Tu)BcaH%O?^O17MtWV5C>DA{Idchx
z2}(DbPu)~n(vhxPN+_+<ZY$R)Fmgx9{t23i$_E3?Cn?di22554`oN16rI4CCRT)l4
z#_uXWdBfj(N+%kt?<*@f0MeAp*HQLB$=rtuK2)4-2EgDWWz4_Od93VChEBQ?H3mtR
zGT|uv&Q_A1L-mQWdoGe(<>>;Lf2K5QhO#{62O7y<DC<KZEKv3Z0ryhrM=ORm%Ar+o
z?X6PdGH~yd*0h^dthi2uz4uCu^Uy3&T%CiU`azjP<J3nb*o<7M@-hrAmLqZo)z8Y2
znV_jq`p^NFFUo!%mMWErH1n!bj3T^n(Y2#N+Eusm3UX_7XX)8qt1AhG-F3Pzv~B06
zYq<%4^|}a}Eo{)O?hCSwx}{mPdALazPwVN;y5%eo?z&ENEX+e!mI~D^I!}r&Z`HMG
z0{k}J<Vj%LuIqLPj(X}EX9M7+bL0cyt((;qDm!#9Xv=7)?kX+9d~_pLfyGyME*LpK
zonLPxyL9d)sQqr;{OuHq+N0BlLuaopiq=&Ax^_Vz-KXo<9xevxeCbuQUl&X((F3~U
zw0aBF^{4HXgSu-J&OW4DMO#LPb#FR@`-rZbqUlF<d340>n67Ug96hc(MaLLV=v1fa
z8PUBN0F_g^5x5mjE=aet3kpx`>e1P_VBPOIAPv*Kq7gM*S5O~5ozZ<W4hGNZbhITA
zsT)i_o!9wCfh|hcKnD}ix^0)B8KVol4ekp%k-iJKs2ko1Uc~A)IDm`OEv2x-CEZOH
zhA!)BwuK?*6<rGhvR8E%$>25J-kqpSyv`a1;B}o_4<t8q%R`VP=>DRO=bO5-6gs}8
z^I?(P*6nQsOLug?(2FurH=TnsNxEj!K$fg)e->mZy7w*NQ>w1C3jlX@9r_`;r%R1M
z*?p&O$4028=^D7>u07CoKM9(Lx&&&=blvTx;Lgy+QoqX7X+q#=mab5NFk9z09hy&c
zWjB!I>Q?;+*PiJfR)<}6>4_kFtLybI+UcEc3keH#Yw0ysq-#hqtzzA?Yv6pZbM~QQ
zBqh4;wB7hYH@Fau_)(YN1hpvD-B|@M%5;xtzu}Ya8bwyhb+LaV_gPm-tEvj!h?Pjb
z=z7o>4VAiKxhSjB)nkxz(Psq#;HtmB4wlyF&(ePPTD>bpLD%V{>1FDsFLKgRtM&Tv
zlaOrCkJ^c<ZPeeF;r=FlBRW2^S)aBVLJz$Q9i7{vAKDG1TlKfH(0beSN9I6fyM7iu
z@SgeyLr~_WH!ee!y!GAa`>Y-Mg_GgTPJQe-aQf(P8bIc&uj~$cetLT+Cunx*Q<p=!
zTW@*>#2$TGL(uHiyCxv#uOCB4OZMs8%ODNV-=HH_`}Jw`b;bdGk%U~Jeic3G2lbsA
z0B}ejK(o2S`hlYXIHEs32yP$Ocb*K+6Z-N%<WA}x`S9tKzH0+ojRon8>i}_DzlX-x
zV7;D}S|R$zG_MKOTcc66Fnz?g@FHBV9gf@?{SpCgpVc2Of)^3`N}8IU)8}>sJW{`)
zHH7E&M`<@IN<W`M1knJ%Zj8S21mG9+MYIufQP0(3@%+W=bGCymPCtvH5SR2j`@!yI
zy_z;~ujm_GNA9YA?+N&HO|RMpe7t@lEgP@v*E~b3-Ozs#P?n%?MtA$B{zf+dZs~VY
zKfbNMP4C7#`q4=cChC9p180(cS8X_&tmhT@<V?}`p{Zi3zM%^|y{jKQ7}9(CSz95z
zuOCDQPSW&4Da!Of-yjie5A{)WXyCDaAbn+<uAdwYwhVpGQSc&DzyBa`S$g|kXlCpE
zIzaeD|K>I{bM%>GQSGOC&yH{=SMN%%&u313E1b^e^7Kn+@%vogyLxLw|Dhp-1^S1>
zfq1F!^aV7p^s)5bey!)}n9dvh?-Z|os}G{1aPRa%tpP98_iBY)k^VZhOtD_kBKJXW
zTMW&Q`p-0ol<MnKS()D518#rPJ6F<CfO7o@I+FHTKXDBFuF$vZ3xi+uzMdeh)E}9J
z+E?j+J%z-@a7Bi2tziaz#<k9HLxE3jhMM<bX}#eG9?1s7+U;Q3Xkcl7ag*WuEZ{a9
zQs$sa?uOe|sCXDQ6@g`oVVW}>I$I5!XvXSkxV|4cUIzCIz<V1WE`d)w4A1jmVyEHk
zH>kFc;eHB)zJ{HTpyFrvGzDJlGBl@;oOc_1X<*%Bct>H7y@sCqk@Gj4-2j984BA2%
z3^1f`MA?3WVLr?rFkH!{_g|nPk*2B#4cqCQ+9AVS>Me&2152TE#L%`4RE`>&9|rK4
z;m>VgJ8p0t2+b3QIsQma8ZJ@;oiZF6fl34!`r>bLaHkFRse1(*##ezQ#1P>N3!#QM
z4RT?IP}=wiH~hSd4zHatWYVa2*07!Cff0tayP$K<;79!<(y-Pa=Fc0RO$TX|fg1<c
zqQCld(J;@5vRFeCI_(x`s6i{AONM^G!_s9#Ls}tTF=TfH%T>ef&7i(!csv+};tl=k
z!NLv0ta<eQOE9!(fhN6aXibCXErTnaJicxCCJewkhW}_;lVs>T3b|xM#x^uUieXD@
z7)&*EGJ@@{VGG4S?ir5LX`2UznHS*bL&L^y@Zyo7Sz8Dn8*-ZhkZ!p6Gc+>{ZiCQV
znTA!Z0B@FMNTBVuY(rPt(t2W;JOiHQ7=}qO_|)*%6(DjA#c#b$<1Nmm^agltSmFz|
z7lxd5C@U~L$^`DEA%t$)E5q1gRN}Rvq9M$`G1SdR^49P-b^*C}hJYdf3Jnh_QeI?e
z^#NXdG^`e3z0}Z^!eeEI=I<c<WQb`Fm2yMN#vuD_c<F|+3Ipf72NPcmnH1rvGz_Kh
zT&oObLbw>?1L2yhk#B^uHO5ajQMT6DhkEWh<6krf*<eg@fyzeXqc{LI8HdkDvf0=%
z01f1BELQ>GVZ1<dh%LrpMG$T^iqny7GZxX?*UR|d7$>~(Hr|*G=?-J9OjKs4@vZ=&
zkFnc(B)&$?cOdmM&T9pgUB+^H40jvXOa|#5<6oChw%6F}4HAE&2L<u>8~>KTa=_SL
zfiTb*6b!&YW7k*69WuU(L~_{Jq6Tj05o5c5>7dt9<0Xn%95W6%0)xkm^{7ct7-v*K
zc+&W)67782cpw{<2{y9n$b}fs{s5IwqX)&)!i+;`oC-Hi5zsPcjAL&iIcpRq!rutv
z(<9J4XKYT>lt^PajjQL4BQ~Qf%4jy@FBEan#`6W>jxm<}0H<P&FJqC5GaiaV179*u
zb%Xntjq?^Dcg4702lH2rPydA7YsTjT!5weR3r5*>V*&@wo5mz7%-=GOr0tyB#w}w(
zcE_0d3c^I={4fZUjAO3?kZj!WBih25Vr(@Lc2kYRX$^kYSm!=e?-^@VKzQHiasnnE
z8fX3t#3N%!22>s!lW99L-5Avl_za`wKbXigdea75mT{>LfNUdYK}DY!|D?5Sj<G3i
z3OzL<e29*3Oj-q&eB-gY5I%PrTipimg)t}rhyvq)7ASma^bH61E8{8J#(ZtOOXpSI
z7_(?Fcx#;cEh_rX7{?-4Xxuy%q(#Oz_}dp;u`wVIZofCqSp@D9W1U0@OO3x#ptH>A
zpoQBfqxU!%DmOMi2l!{BQ>Q>$VYJ>v_KR^OUf*1$@fVu(R2dDYky~SGPn~tGsXg`8
zb*8P&Q08XhX~nnRbleZZ4JIRf1-H@kjLv{=GL>{fve{&!xr@6=o`o_G)4VhYx0w3V
zmk8TUYv}Zdr^)7|o9AVkLsKtr(?&fIJ4|coF!N4R{1hO3OwH-rHeb{CQBd(SWyJ%(
z%as2Q%<neE)7)o|DL5S}`%KqVC<`#{{sP>7(*z2*958ixj<P^g<xAYxgC<|vbU0+n
zr)EBEx+zoS?ubdEvjay>p0xRJ%=8ff4(_<A&S@AtW$GLYVUTHYK7^-Dujq9WY)YWN
zs}W*aK(EM9(=yru4>NJJ*a$bZT??PinCb?iX6H=tH0g*miESY~Z`weABqGWbOyTfo
zlPZ}$hK?~cO$XZr)0&UqzG#|5bIe#%C>^tjGo>#;a>;Z>g34vn+Uj+-Y3ui(i8uAT
zi{!d#I4$FDm~MOrg9#?he@Jec{_;fGEz{Uuz}+?_d;{0+nAVJf7m231O<+FB^m`AQ
zt0kM3(7BVlrk7WsbI&y3EL!%yX}J@mX{KAvk$Yg8-UePgH04uIdSnWrKZ)?z<h2!S
z>83yCLM6l0V*=VR)3kUySh7qmbl^Y76l#DoPfaZC)8(2%XyNtDG>oDtd8Uqc0e9w`
zR$760ZVIHK|Aom;$7~8rnkooin-a#ON#2-R(?_;%O`T}?cxMW12bDt82>P0($kc&8
z1S~dPHlx+vn+kRUP+}TMOVbagO|&cj(e#lH(v_OJTm@&j$&W(ipH1$+qh%_broNj1
z{9^j}4+<+yooGH+Wh#CTZWnVBJwUEzBgHh=m=(IQYt6mJp-$_}@pPEQ&Af_cE1S&j
zKLftm97G52-ObHtMebp~kqNt7%xNnC-)e41_4G7<qNTr=IhVp2-e%|3cF@^jzV-oL
z>@<hd$mU~C4TjLy%=H4BpV>%%tznmWYFprUn=5D;xW~MURyTXigXzKXH=Cxx;6AhC
z7q}K+-m?lU`^_`x<lX_ZB@ekkb7T5a>7cnGt@I9=&pblzuz8k~LiI<?C4HcJ)V%l_
zl4E8Q9dS5rPPqf%33Gq?j_ss*2nFCznKiWE5oF$g!Hhd?&Y@Lvu-S!<2#1)N@8Mdg
z`4<YOhnaWK3p3nYOg^14kEA)`S@UuW;1Oo$U;xgUnLK*_BF$^sq42!f%^$UhGQZo5
zYDb&<E=3Y!4y2FWE|@cDb#>9qwgg+O`9C@`7-tTrO^i$Cv>C8;+1z9ZRIZrU(Wcr}
z^PYpK#5MD98-(%Zk3WL?y7_cB<ZhV%S^??=v#kNm)oz+6{R6};bJ`sg-Zn3#!Q_rP
z@;K_7XrBH(Xp+p^H^D@**_HN5Qp~Z{Au03wR-n0Sp7Jxw?wP;Pr2oEo5yef@%z^uW
zdtm-t55kA$;(fq9GBfmUdu-O7LF1>JCt|xB2c6A{1yId22h)2y%N$<?oosX1A>^Kz
zSEs?59P_B*P<d)TKpX41W@!vmo|(goL7HdIX@#<UbN?%-#B+1~zR0~acb^8$SLTlN
z<;ZJu-`DWzjd?YF1^d>V*%)Q-%wdC(I19~n<52A)^IQr$6`QwrLY>~5Yt@4J67z`w
znD}7ceH8{jnl*GdqSSoh0DLMl=h1=IPiA>KaOLK#U10lc_NSM4h5658Q2An>>;!eC
zxhoI5Rc6h5c<5rOZ^FHEwd|$v*czwh_z(csT7EU4aGhnI8-Q+>y)+$MZ@DO<Y=fnw
zI{ItLeg>LNmZWze-E5Jc0q<_vJOEyJSVG%EbBpB{IzO@1;_)}&+bqGKpt;>rlUm)=
z(!4ty^|I_=jl|m$(iOrT7H21#r|h&iZUXOPDaZw>uSG|bQa_7kGjh8uCR)brwiHm5
zeUIe_IySP`(t<`9f6Hvz^Vw(FO^3_^EDLC1u;0SaKy$z{whI7(mfDM;dC)S7>U+qt
zg(g{tEfIgBnU7dh&cnzawbUGq>@mwEiqIanT<?$Mgr$BG@Fy)l(W83G(v0@jf-GC<
zfYfPA674t#TLyCA4zcuq0hUn9k%@3L%;HVktKpV{WoU~tmgDp%cFtPHv_KMJnR6fT
zbCwQ)un=kC8ak0ZZ~5&IS~kkE={@k#mMwH9GsYqrL36<pPG?syTH-bEBGwX-17MtG
z?kxbWSo%=Uy=qxR$Lg+G77T&Gc#Ai!4X;}o3<KbXr8&LJ6D+Uj@X1X}A2X<LSwhI{
zZHvb$+PS)8`DZOmBw7wM1!<CH{w?H^EjQ`tSc)b63Aj@&^S?nw?^<S1fa{)R9Cfez
zmSZ&PrCFvnMec!R>=dXxv;=jB$|K7dnjk#3G~)nIw_K+$w=yikXyh_2F0_x8Wm#Cr
z;Q7n8G#rEM6N~4+FqmW6JPx_1mTnY=$+b+W54LBP))W=Vv-~s-mhvtAr-S>sC9F9}
zUsz_)k(2^Ud@5@H((=n_;9gli(wVW>mV<P-;f<y4KIGn75^44M&T{)4yePDE=mKhI
zk)@#njZtjLp-)cUTmGf<>?M|M6h!)98FUKCN6VjQz+Gzjwmme<EEO~X{A5wld$-(T
z_zo(cEw>#=DlCIe!uv0loDoo|w1iOas<I?$!0BRL`Vfh$wOD}{Ypj8ET5PS;dT<YP
z)>#L{0O)4TT?U=?)?dA$v%%VpmTDWVT|;1glQp#qNH<&e(76wHYjP&=9@flGu)D?j
zI1<TLYXuFu+pJwiBH3<Drg@;JRd*3&Ue>x3pyF-)`yY_)u<lcVWvA6yxClBv)@V8t
z>TCU$=G%VO^kq=pWnHozZMoN)PGg|IbyQQ7?X#YzE)-y`?}yxeYZ0AfJ7E1b6v9Aj
zNeQ?QS|6_g_aSQo`qM&(t-o48eZ<;-JiIt+^`?-+F>B98FniouW5Ry`p0G}$8Nx~H
zP}++*WgSl|%^>S;3N4+sc8y0a*!t!rR6?v_^iB@7UZZM<S&uD%iEu016CR$iCd`D&
zS?hr)?~IwXoRRGzjIu7F_<ywZIz`@NtW6C_E?5g`eQ?p*oJO=*Yawk|$5|_<Be`Vl
zuR(IznoSG(E7q|dFm%=0q7s_dta%}@7jGTW4NhFQa`mBk!#d;y?nHuhCq>6^TE|eR
z;g)s2GXUP-whrk5^LMO|Y3nu7nl=wKN!G+gph>pQ4MUP*ZNCX^k!r162jE?+8y#`F
zXDw=uTHm);(ioIxeUgl_2iD%Nkb7vwZN(#IT}SKk$JXFq;Y_-<V;O`Q)`qmK$+Vt~
zae_O`syzbVvaMri4*$gZV-1+kv5tC;vZvPHZX(IGwmbnxpILvSI8&ar)z8q(x2kFa
z_uRTO9<IHx9(e%L0&6dKn0RSzO*4^K)&%-Q<+b$~3rF8rS9Jp5t+k>Un(wUL7SS$X
zq4guJ<cq8uETAd2)?E%yKU$d|fGD*l4+6f-noHaLpR9E*p{(2*Sp?0`*5JKhtFZ3g
z43#fdiMG@$t$Fk*LY4Iyy;EIm^|DbHSKER=ky~S{Pt)zSwm3iJ*4bwLO@G3|&DN9R
zF6(VKyur4?7WW>`Y_yI10oC4Q8%IYcHrsB|>0Wo+@&uH5*rpGH`7Jh2`lCHtZT<3)
z+h)rvM{c{VxF^UwZC<n^<7Hby?;mel799%NVH>v_Wjk$G(_!Anwu+txr?2ff?NR&L
zY(K%$E?eMFP~B})XbG~%R)_lWUR#YuVDq<iqv*mu+lmWN39uc_Mn(7Arh1|5fbH~2
zum#%WUGVUrtrLaQ57{bcm4Ddw4;^<oVk=66=26?wPzaCN#?a*XxYOoZ4|Y%3?$OKT
zq-|FibWYh$O#w}i?Kw>VPup(1K@x1Mpj#PYTiXFisBQfgI1^?Q=!9dqt-+5Fp0U*v
zpn29dhJrB>Hi;$;=WHFXgDle4q%%~`+fq6L7i9~d1)rjA&O7w6M~v+v{r#m2wrxv*
zzi8`EI<dCAOF+cgnzw~(muxjwqU^HmP6SA=*c3WJbk*il4>Z?oJ1BA<ZwsK)(bsLm
zrbFe1ZS+ZSCfM2s;U3(yaR=eWE!&^8v3c7z;4lDpY>S-~I#0A!(E=*Twt6C(CfR1D
zNo9)d>Tn2CZG9;;bl2AE4+!tscsdhy-&QK2?4fPf9$0#0n{x-1cx;<(g1_lD%M+Ak
z*c#J;kxZLmCWKkGzi0)KZJSBm>WR&Z)@C`jPVV#qd1`a~2d8pv$0+>s%yxi|TIJcE
z(!tJr+rYs9KDUM5K-ml1W8yBb?Zuz;;9lBlP+xy#yX6U$*S75uz`e0GnhLVFw&GOy
z`_AS=pCuOB7KZ>(WNSm4dBwJ6w1j?d`&*>QQi*Ndc+h;X-Jr7;A8o%!0bgn}oPdjE
zwpR2B(<j^EU%*ywyWxf0XWI;4)S|-nGo6C}V*8!Cb*0ViU*M{2C!WECi@mHKa<2A;
z1EIObUiTjuTx(xc7v8V4=TxH1%|7^=8qeQ)dpjd6ZLt4Gwb*Enc!wt0WY43IOg7s`
z(H@Swz5OA$?_qBt1GvSWx(b?G?KX-(ZnOWf0V><=-B_6Lv`?ZxX5nQ|rd?%k`?i%(
z*<lZ&ki$;<-~b4H?Ebl+_O-j$0GZRzevL-9UH193vfXXJ{sKCC>=P+;u-87YD}es?
zl{C!mvrqAar2u<F3byUHXVT{q2kc&SG&s;cwK{@lKc|KlhwODJ_;lFbu^h<}`=$1<
zaMT{CMJ0~eS=zxpZa=jghE6!`jq5_^q&;O6vZw5WzJ*SZeI4z5owhgBfGya5VI~kE
z_G`3~54CT<29+?oZ8Av1?Hz+5JYzrgEnGWmU$-8B2zyQiRL<GABFxN1**j4DKiYnP
zLhUj36;Duh!9I)v_ZRK<1~#Ozb`QF1arRv_7r$h0;a&M#ZD%rlAsTP5It}aB?Q0)G
z<A%LwG5k!h*Kds6P5Z44XoFk!CG?`aZErCZxjS|jItiC(?{gWNN%l#H(UQsbcYnf(
z6#GsJ`={Ew(V5)4cK-%2ch5fFiL(3l1+*|tv#)#v+yi^B!LPvf(7v-jxF6YH9RT97
zJ&M*=>GliTQI=tEa1pL$+Ar*ei7flE<^X2fN2Gw}iT&72G)#_tly}zr+Rj`TWb*A{
zv|@j5?@vp?7xsjipe(SvFGudBeKRcuU)ddWvhlTjlnKcjd%Z{i-r55*;PpHEuXMJe
z(0=tZ%oW)K-vCf-A66GF@!tMBtprQ#FCT;RgS{>d2p{cY8+co4&v(-7zRd3I2zNi(
z9jP!_Zr@B_ZGN_=KZ1!0`{`QX{$lU)95j{o+54bUWp6`!G%k*4iWImy(rEdy#xb!J
z=GQt*b&*@=$hM-)%~4KMhV_m+QvulE*ha@iHagm8!~7=4chjB7Zgvz!z+rdCIXcGe
z;dn~p(iTUTWk|L<p3q`uo5Lj&i0zIkx#0G6)TiwnFNcAqUEU6VT2StA<k7o#r^8eL
zp^sx+8FIdkgjTTN=NLf8Gj};kF2KTG$MvJAguf%$PVuvSj*QMg1UQa<fT#N%3*x|b
zz)?zJfIvrXAGFs&N5}cFd&qH$HY*Q1%tU&`G4T{=jyiG_;Ep*Su0wMlcUWmUf5K5o
zr`t|CR%gKADaU2nl?ifuT!G}Y;}vb@20MBu)A}LA(XI|?LLGe;!bF(kI~qB|9h>&T
z;WLhz+mW1g^rVlfA{_47z@Kv*5@9LQ!T*P{^Nw3I9f@*unGQ?Qj=yQkCB`vz2UIRN
zZqX*oMTZCe6bu*ZXsZTwoTJr3XkKy*n24P7vSSqeF@P(MkTn2ab(m<By5{htpmw|?
zwIA$Wcg#AEvKx-xKFB3FT2lb}rsK~z;BGl4CByC84%bi!?>I&rg@=ib7c}una$KgU
zR<ffVZQrIizNf!mk?OeWj^?`SIP)zm+;ckW96;fH$BuhIq&d83KziVKOn+kNp<@}v
zBpx|xQSkDyV-78U(jD9A++T*{ULpXQj*gLlXE_c8!F;x3{|MxsIG&fmryNHV?Q1-B
z_|eDwxsLaA8seGb2O5a-9PN`)mhW)Zq>sFwJ3Nz6_`-2=9845AylpV?($T3Dz*mmH
zDWdt>@%AQwZyZayz|vbs<6xA%b2RoquFz5X3~f>5I6==(v14o>`1{^5mgeduj;1P5
ze{j5{uhTy|x=OH6>bNi*9+o-2bN+(DPmUjl0#WXm(H)4-j!fEmsdOxwi(Hjs>Jpf6
zsquetblq`TR$p98txU_(>fL+qMa!%#t*p!(X`1C|YGy+#%YMDGL556`DMOZ^hzKZx
z3|TIQY}s27kSSY#-_u{`bM8Iod(OSQ&wcJa=iG;2E=<@mu4h2sj&Y8P*6bPi3n1da
zD0>`zj*Q<a)aAr@b0ILD8L#h0qYGpGr{G)}TYiDUQO5CG5OHI?JOz91jJ{rq(t0p9
zb0Oo&XrbWtF-FeYFyX~8{{R_pM%@;e@L{B{!gzfdpVKD8k8v~-oIk^nj;F^NFE7Ec
z0~oVkz~BkSOSBaYWc)%`JAxQ~A`Cm2VWssngz?pLzzk*Bo&^bGgz@R3@<~Qq7evDu
zr`JF+f-!pyFp-RBhG8j+;Svr@rx@@42@=iNr-n!jV=sNmCzjD~0f}QYehT$?MhqJY
zrx`7W;8OzQAgx-74EM$8JHz;#PEThU-_zDRiLsQDs^=I?TiRtOGcx~%;(12KDYT|A
z8r?Bb7Z|p55j~ZGM+Xlc<4anE(iyXKWWLDw=?Ks+F`j+`Tn6Lo55Zk#2qHl;89`K~
zmc^*K2Zbw)xgh|{W|$c8DTgskDWY5kpAKPpj008h(0Y|INvDc@MkMW|3m7jP!w3r*
zKP1C^5n~lnT=R<=Ut0ikjnUNvgVz~4e>C1;^wGV=n~bSwpxt6L(0EH2Z_?hVl<{pg
zM9LWFDHvYP_+b(HZZm4BB(j2W;9vArGX572y(-^*ze=n_p%ANQbkqU9fwA#4q#GFt
zU%+MygL?s1S{YtC=(aIlqZ;sbMmxo+IvDvq(CcKpPm#1P#_zN^bu-EWpm3LAPp`us
zMmKG{dl`jy!QErjeg~U<3@rt;`x#596mNi0W?cdO`;6DSfIY|v-wv4}#v!^7Im|fz
zBS1$OkraU#Wjsr_7{(YA6is=+FkJu{XM{1~%mhPT2Ja^sCQ1fQF&bY&-!y~CN8b#?
zF9>9ovBLufA2NdJ`#p~s{Dt6-Fw+lE4B3{cr0l01Q$XLhuxBc0_wK-)dK_LjG7n4x
z&53DWiJ>_&-ws2g3$y!YfVwij48UNHGVjuZ;l`Y%ZJj&QhZ0~O%zhIrc{08J2Iev5
zZ%bgoiz)sa#G9E-kF^hT=V>}=`Z5O=1I>?FN(ChT%(7kJjx!&80+;}%z6YQun9HR=
z3uMOp1J{C>)fBS}#y>%U-4G`8FhoL`TWGq&nBAGcKFNGi2ZeCvVM-)NFzXMZFOunU
z5ay$pJPJpgVtT$tAFGLGo~Jx(40FaFa}mpoyalv4=9{!C#WPd>06EPRQGs0o)8`LJ
zCNkIk4A3*o4eLP8GVi6sU=p)%2fRPWeCsSsBr_lVfX4I8kQrd6FpuqlzZaO%{+Pp5
zW*Z$%)0l@TeQr%>#x$VwBJ-UZu$P#UyXeed_T2!v%#3(|#!RO1Z`jRZs;&a`3Uhh{
zma>^&P%S|o^M(NGSDCAC!0mkIVY+lwz)Y=xNFg)B2hJ2R_fU?ynE3`h*4LP8jPT+*
zb8ZDBZ&;bJZgBA?)29z}d5c*}A;%J?q#YWi%uSSZDr1(*&{)nqMA^&ROm!vfRxsBs
z1*v4Nq$jwF`GY4stY$iTLZpT{L=oXyX8tG8t7G2ohuu5O$ZjaqGq-rd-v;IdS`QkT
z*6F)wZDOk508BIUxeSQ5FyEr`>sIE~-57lvlS@gXcIN-)fa_rH`~*YmWNv#3To<!~
zlJecmf{h?|nQ>I?)WiJy8b~j5A!SYPF`uM!av!sm4bso_p}qm;2))PeGh?m!KpSL6
zQH}o)^Wauk8fL!#2+oW!hv+pq%50v4zA@%js)~HTl)R0;ab`pn^e33dNPUu-LQ^`$
zTuiBvX{J?y5za8*u)!c^ne(V*@geiW7h(Ppb7CVJkFdghz}d1|tyI)v#|oo+>h>%)
z9h4nd-n1`uWR-mc;>7A2g@!Y$f->eVtgH9ozAH;*i^iiYHkC5Cv4(TOxwBsS5q%!4
z*;p9#WVuuW>=?_5-V9!>u$6Gso0ae`I3L!~HxTh<Ssm~}<@tWBufl=t&#GJsa-6j?
z3zHDQGOPeO!78N>zXq}{)4L>ybz&tHgIP%jz=g0@Z3GEreYXpZVXT)8n39vMf=F=T
ztTB2QM6iCR@XaaK6O<>3X7!Rn3`-vmE|wJ+Mwj*DSo<iA9?$9%!MD?_k7yr|z)H@?
zm=am`eE4*RHAcVSv#e}ya7nDk93gU!_03MWmdx_G4uj`e&pCrjVGU3X`UTbs$`Pcp
z>iU6_#(I1|8q-;IMmTekb*BU563dD5B-RYpLkdP+W>tR&m`v6+3M*!@-sC{>3agQV
z-r20rweT>9l~IQ&$z}CWP&1G9+_zA;%DPTzgnU*7W$_DGUOtd4WW7xX`y!Ut=jbbD
ziEo0t#>%I+<aL${eLmp^Yc8!?H?6FC1L!T*zoi&q2`l0pG)h@ZDgIf;n*0NO<*fI{
z(RZ5_K)I(1mVyTpm8@SVmRrRV&|_H564pbnhE+-L#ah;3N<G!FmQuX-4(sGfkb2gB
zIw>@;%9}tMS^uMbX%owuM7gJC7LVe!Ei6|V^jldabWf^{wQ&-5+gTA*o7Tbl=Oiq3
zvP!qXZWrtQevod~5GD2QvP?qEQxA(rWl_DX*EN{#d#tDFUDL<Hs|^nx>n5Fr2UxfB
zA#$I!<PC6xEIaFSfEi+i+QO+})?2o)G{P!k!I@Fk7xa@KW1XNZ<O9~KV1SOZ5-4dq
z!5Y~FZju$`2bd|Avme}^W*wzq!3=A&2SjFBNtCpG$SSgh`A4iNdype+W-=6P*{|ip
zo*nztMSB0)v;B9$DJS-Gflzd2`_2Wn3p>~g8u+{!6)zlR`_OLDjs55_EV;A2RzlB%
z9Wn(NPqz6X$T2qK9f)|bCClKiH`|}ij6Uq6bYAvl|4GliANwzV==rnXq<qD3_Mzvg
z-ZX%nPQTd`?BZk44`h$igB!%Ye-+LIv%mig21D3aDHavVcFY9{V>_LOiIeONm!S~O
z{)h^gBiO4SgNaDCU>6jk*dI~A<`jD~U3!dWbLWDKVMo#G5zD@p2ZcDcAGX@o`SI*E
zXW`9hb_N~Z64;Ye|B}eQ{S*8?!yczY{8@H0Rp=zK{Wx&{9Q*qsSW0FW)4udPJNza{
z3j3ZToVmbWH2}#}_FalYrm@Egp^(nr`X^8>vNPU<$R&0r{YW#|j(w1{US|J04NIA9
z>kL}6*bzNIyTbmQ*7a<52jxU^*r~JNa@jKa<Xj&64lQ?A*^elzme2l~PSpkMEl&ci
zkp01YjHQUZ;%A@~v%RRs>l$18CPc2Y=TVLG4R$g;;Wybo{soj<R`zi!CMaPaq@+eE
zJHrD8%h)f8z?HK#RI7EH?MI273U&=uYFDziKLLd*_DP!OYIeRoL~7XYy@kG7_CPPV
zI`)=VF#0>}96H3*vyW)OHLwrOLa&jnHek3->^{1;+RV0^={V5B=GK61WnUreHuh$E
zNZQ$t(Ve^w_U&oFbg~!RgyLOx<CkdcVf!8h>1FR7N8>&AFWo@tW8b5j<^62+R`d<9
z_ffd(K6~BM5E*3O{t^>3#P;|B+%WsOG$@R)-L18d8D-C<2*nt?eFWwou#eLHxpDSv
z4rC_S0ViR8lD(e3YB9w=Kv9}$cIYOE%&>pK7Ha-1`>P0uJY+x3z&t-<|LO*?Bb<-{
z5L*tT4nEm&%IGj*&oO-n*Bm(eo&mHYXYph7{5f%+q}$2PoL*Gx&v)T$D+O`oM1KN<
zM>&ogfbGWFMyG0b&SURG!GrTsJrq1S&Gad>W1RK0YI$+Kr__iyXP_Id`EVL@(df(B
zPzNwS&IvJ`@#hSMqVG7zl~S+)oUc3RW8Eh>T^~axkaIH+ph29M=_en|5xHP6A)Lx>
zup7z=rZUVhP9Pn=PIB&l1lPhj_D?}1f|E(1g-FgcMJ1y+rzu-|ic_UQV>IWTFTllc
zK3fLpSk8yEz{GLPJD?ZOk>XHooqw9+UIp_BoJ4w!CUP9;;=vitES-bTatu^7n8ZnW
z6L!yWnkeRz%=v=Wl=GaI=~SJ<IXDY)f%79GD)Uo0OTu9(jpM<DrF2ejIV3M~95zGm
z5=T-Clnl;l`s~ML&N&LbSTi}<&p|PZGw&5>T;WK+fJQcFXbn1ZI0{<layidaI4h6i
zs>8Hh<+SZUV?O6cDgr9tWYHavLXItM6^l5F>9BL1lhumG8=TgEfO(U%I|z-pI64^=
zN;qDQP%q`=-v(D^<vdBHD&?Gc??Ci6hZhLN3Qq7fXjF2(>4z6pobB}dR&z>&V4{Ze
zBt6u%oM))4zm9W}c9nNHP5J1n=M=?3p@HK|=h#NhN_r}qILt3#p_vmz0r3{jZQ2F5
za+ZoPq&5y>a4^`;d4n=L9h^bh{C9F3KSXC2XVcH<>*nmCVc+EhQ2M`zbNL3$_j2NH
zz|uXA+cQw;<1C=8XFq3%;-~|hPu@e{ea_dkJ`QsJC<Mw7$8J8zFz0M6P)0aB+9Qr~
zT&ynuZHy!M9VQ-d29`l%oHIbVf(cI9^FW*A#CAetinES(*wdVpIZ&M8xW9&B&vMqU
zf!&9kc}*aXIKj)&c!cZa3I$v4p#&({aZ{=A#GYF~$u0-3(GTj5T+Mk{aN_O?u|mU{
z`_Y>ab>aSb9IdY0m@ObjxxZ$i(T(f91laD}5EpPB+;BDeJh=sQs6WPCLw_bOu8{H%
z-rV<`VAqFRU<cyMo%1#9`f;P^`h!2WDhB3{bAt+?9>8U^gFC^E?V}h-Ah&-A^A*J1
zO1l<>di*d6AzYV7;6l0QQ0Oy1j5|~Un3LS7tsvptcjrJqf_s@ldy(8l=V3mI`y`bH
zoZ>EBjCqdcis?Tb#BiUa!(=SCRt^%!<<QPLp6e_?Um|xIHp;l~#2ulG(pl~?iq9l*
zcTyzv95?L=OjI(rs05<txdy8DN#XX4LH`1G?_+Q+mAlp-dTHF%y>KR-dwml`E^@<Y
zXqUL#TH#Cvcjr$Kxy;?6#*i|(l7qm^;x6U^<qFqGA84{>bBC!wJ%?LLdzf7AXRW}_
z<9@OQ4qxT|O&2`!xnH!RuYg;-9b6%I3Ejvq;%<2!juvx`9RR(?^&5nx>)gjFe0_uK
zeHbQgaw}4xaEtp(AuN?}i_3vo%H_8~uZ-JFp}BG^cjX4m*KO|pMzmINFFp@vD!C;r
zkScEVbtqPI1L?I=!{t+DK`r+>9pLJ?e)OWh!|kRrmU`~t)!-Vqzr2RNM((pz$<)Ms
zdI+SMd-zL`7Vb(a?``D@C=A`kO<M*J+qu?v{|Ai@uIhUj?Bss177llDPo2Xky19XL
zFu2QomUezU+`lQj+RJ_H3M}2@+BZS6kDGD~>iygo<^ptpE3$yQ&;7m?B7@w|Uj;YB
zZKH7gFn8k`D2#CLP;6$DTm210#<(}FQeZ#e$|?6e&JCh9bb`yGJ9?8`)N0_t<97WE
z(P{3pRJA_CwWk8tS?&tDuJw?+kY16GxL%aOIKqpeQdnEwIohz=@g(@?uk-DBs!)hH
z@HlkLcH~7$Fl;B@0b25%d4Fu8^PdavZ(1&0d7oZ~iKD!RMCiNmcGHW%lQ-UjQ5@ry
zO`*?==RzSeZ{DXS==t#0(bmbAXHOwAKVE_-6#RJ}_d$;HdVT~-0I!0MTqk&jJs4mh
z?>RaF1@R8Xp)Z(sWiRbNLwLO%a50n@KL;>jyw2~zo#Yi$j4Yg|qTgHu@A<Ex7|FY|
z4qO!Pz02_86t9hr;?X=OicQDxGHIU?%lq*z`r>$-C^j9>6Knw3Y2Ise6i?uNM`8X%
z-d0bboZ-DVO7Fk3ycJwHoWxsBrDo@Nda4CV=4D(3=y~2QdJI!|=?T!kz+31G>{Q+d
zA?Qov{jwS6(|Jo@1?WXy6aB0&@ye;BHG{XdAH%-Pvr=Ow&;KMWWbw3=dcMMYcM}X{
z^F~IYZq4Bhe~i{#Ud!`P%;RY~L9X)RsU9nzXQ8cI0q@?c&?w|tb1*?gyf=RaXfbad
zEy&k+$6Vmyb>4bsDBR$g4uag|6;Z7A7O#aqs#C(#Qwpt=x1$w$WxP1z%6TdDqP}hA
z_0h$n3f?{n)l~9ME`dxHZyEVi&D%xGRt@jj?GUNuH9dj8I^N3z81EgPcr`@odD%`t
zYvBDvr3H;VOAJJsc;1x8Z{}65!?0U;dmll)l_%80(KcQmouS)#UCmJM;8{~YfQe3C
zPby@(c=pSI-Oby03{!KL_a;TudU)PTAkxcQME6tf@wV(jV;^r3y~X=^0nKoGkoN+;
zPlk9c|GndQ6*RLWyi<?E{3uUB@s}~4;WX4A@NQA1**H&)2;}?;o{yCxrjxwAw8xy{
zjnLk9npaHqxidV^evnz-yL4y!A<vHLZXWTTSObwG{IwMNv*m{^!zk?d3#eY)o`3KT
zP#pNXDNW$WZ&?5ZC;pFRP;lmdNl&p0{}l>6yYlyTpzkQZSx3*G8~+&&h&%r(rE@&^
z657#t@}Hp#bjSEs9}Luszn(&H-u(Ay<LSenr4nslzI+wX{P?Hrpy1D+riJD>f7uX*
z9l(EwGP5W6pP0}W$X^?U@doj4O+hc1fBz^%LijuPQw}baA0vQF7+<*wGAH?8(-Iuc
zPgxBvg5UcA`Xc#a8dDVCk@gv<_-{~wLo|Osz35~3Qd+fQ`6YDXi{ocev^t(&M}-Eb
z`TU*mFoD0F&OC{HHGNL%41cW|b8(j6priL+5`Qt3nw{gnPjC2S{*KoGbDr-@<uEDy
z$lsuUf&Uae9I5;t*sz<%=SM?7o&QY=EM4RuSr0ER@qgCCiwwRy#o{mXJE*iElkY>>
zt1SLfDxtr^Z(WJLZ2sd^Pn^U5vIc#ETz<&+u$0GV6+-_ie?2W*`TU|&z%JmIob;XR
zy40Gz9irFx%16+@&fohH&~ET^?m*!tKaMV1+~QCC3D6RLyAAY8`8zj)+~&V%3r8#X
zHP668C4ZSW22sVo91Xo{{_Avzt>HURd3`Pa3n?V)`12(oclfS!IIHJ>xgR18{CU>@
z(rtW)K3Hnv|3;D4X8sxq_O<XgzYl*~`LFAN-Ns*Pfqpyx?|0DG!Ix5oxRXCaH<Y^g
zS?SR0=I@~-`Ca}r)kXF21885=%byd0iM_{9azI}nf3On@{ruQ2fDQ0}3bz9LKEK)t
z8iRb_@8QJ|Ut0{BVZP6o=o{fb`7~fg`MLB<7~_9M?myt`=;$)e-$MI~3H~V6GfwhL
zZ86>{e)y-rp5~8I+;oON*8qiCeia=79`dCWNO;75un%BI1pblqUq@{Pi!Z^1oj|k$
zX!e4|l$3Q4Y&#6jQ84#gc;O_dSpp4b!6_a3Tm+Mc;i0RbBL$#G1*fT+%uS%pL!Z0A
zCkLE|AW{ScPr=nxm_H`qQ}L^p!0jlAx8MO?CH4`lEulhhU%`*LVEqJh|AlY<f)7`~
znd5?<PLKe>MS7Y~2sXTnzCeM&1NuRN8QLBN3(7u2Ux*;@GjO4T@T0I4CirtVBu@%H
zrUP=gV73Qbgdq1Kz#;{FiakdO3Qe$gO5ofA5o@&IJ&KCN2#(QSJXY}dRkX$lZc&OO
zUa)Er$Z5fgXMmj`m`8_>M8Ufhoj)UJr$_XxActzMk^~_X^gbupNk`LU!K1m5ydVh6
zg?g%Bj0(Wg1Z!JC(gizc&Alkdqmb?;t00h`u?#^;ALjD1;P44_W(t0I3nWX>KL~O~
zQ2!bH&K7)h37|QG#26^#3PvfUn<uEJjM`PfTuP(n3r^FSzd*2W8N4VIRM63~NRUN=
zlVU+33*0q9hzt6z3*O9vzc&Qd&yN86ra(@6r(1%<yU|%97^eD=Qo&^fxH7@}EVx!K
z*i47f+k)rl{!oSBDHT8~1<e$xsS=1^h52g12eDA75p?{4-(#&{Q8)VP1P=5zyd!w=
zXK?ib5j{-}0=E>9MnSSw1?(olYad~t%>w^WfVK!)w}WdHyyXE)Z2~rxyS59;1n{Xt
zP*)1lDQNi!dR>AyZbPJ7AUg!?y8@9Ac6$UN6A<YYOr~Rk?g<{FLr$OIBE`J>1&(U~
zHXx{f3>NMS$~qT-4hk0gdV4Ih>YV{LDp;z7<e0#NL>>s@QsDi#KzkO@6M~m>05&P;
z_!VSIz=;N#7EDkGY({Vr_lD-r3ZC?Y-a|qA8yMgtL2)JQ9T7VD1JhP`uohr;LI>Jr
z+Y85-&~p%`QJmCK_@^}s)Jb^mC3x>Fth$d*7hxc!{9T3k92uT8;WcM)Zo<J#h`0-1
zcnStRgl9emnx}BnJ~(qsm`9lnFJVRm)V+m+2VvevI8q1VD|{EHoB79u6Gy=X2<>UD
zJt6F)GMqr+2eouw3=%p~qA*xEKLz?BLJn;|Lxr8M!ETsvT!K-Y6dv~g2^R*B!C-_?
z^$gG=g+BLy7A0Iqf$&qpB_$Av7N)-ruoz(k?dD>IA_~jJ2}KToju+O^k?^!oO>wCN
zq0KIe*CYztzlS$xgi%yob5@vr76VNZmeJ1XoX}w%V3LKSv{;@OnsVV&iZFWv^e+hi
zd=cKK3cDNtnkM{t2NcqUA0(skqVS8w;4TTf=rbl6!l8#ixh(XdEO(}GD+PwKgkK_j
zX`O#X_%*d=3uk_ZVvca}eW2wE=TCs-3D>MZ-&LUx73<~;8z?$gAWWq{Q=xF>H{gnd
zO$Q-TEZlJcmaYkV?!dL{!rkA&;0<9n1-otvKcWKDTf!Pz>Pv*3$I(|R-268zSj&V@
z(*~?uI73U|ZQ&~iAyXmT@(x_A6t+@~zDoGn^XRJ<22$|1M%e3&zFOh69WY-f{PYs+
z-Vy#vN#c58F<sMW5Wcktjg7)qTJ4&I85DkO7Ph6rP>WFM1iP)mhqSY8vkHHs>`A+@
zlu{xc!YlN=cM7+eV6aOV*n_@qVcj4a?+U&D0qGHX(h;jyD5VnVd&2Es0lQC_@I9RA
z7v8*%z5(HUD*V4M)VzqX3<^KahRBd`E&VKqh0#tx84>E~e@=}Gtv~&Y!HfxwwA+{v
z{*R*LlfukKkSXE6JTy)VUpoiaW`z3!KxT!LZt&@$5QR~A)P&9S|Amf-=2JA$R<u4I
zdUm4m5SXwRb<pbSAW~cg=O`MChigtEr+fJOIEy}}+C3Lhvh}}5O=O|i=24M}0*7v*
zg(|?fi^AT6zK19+1{$6skMAIIOtdQt#7ks<4_<hSP6fhyA5qpd4AfUt`zHGQL`-^n
z`is65f;%qy;UYW?5G|pA)(KJcP4oqdvS=$1BpTmB0j6M4&2Nwi5tSsNGgK5rHBDin
zcq-#LDXO52LAYqor*JJo<Xa8JNYP7+z(tAHya~`#qC#JA(V|VXYQ>0FQgk3zw3tew
z;zWFUVB<y0sGRY%XiFuy1knvzrxHb-MU*c*Ba+iA{jBJlt+13N+Cm$HbE0o)(M%TQ
zzkq2wFM1&vpedq7biML|Xk$D4O%*wnqcKhNn;m>g7p<bNY+Mw5Ne8Y=B3CmEW{7tE
ziN4Ds<5uWpikhd<mnDj~0l6YNGEH}$vqh;|%wCR&aRml*McY0CcAlu?4t%;Q`uYjL
z<cq#tkHHj(wl4%J6opWDt4Q>AF+ht&K6EO&CTgaH&UMjSsqo^4DBTfm-xTH2zT}o@
zOC~T&L^kwiDit+SDzi+KbOm76a#7K@K)WsSUJJzv(dAw6tx_~dJFhBHTnl8XMRvQ<
zS0fVH!>2o<Z|QYiFN*#Pk`1CMI@mUfULQeUlW2Yr#@j5~O?Qu5M6NWJR?*=dFxVza
zqk`#n5jPQDbcn`Zgh;1V6itg?mne=Nylzo3P3c{ce>y;WM1_0M*ee<fhsHgTcNXTN
zPjr|Mn10cv4RCEh^o0(6_eCYY!0w>vX?utai4L%!J}lZh2oocs=V%EX6$J*PZ%h<H
zcMBefw%&tJ<09+RbatN*iPvMkCPfQqM?WPx|383Ei|XjtIU~|vg27qQ&mY2>hoa5&
zHhd&<I0X|&#2bfU*H(P#DfHQi%gzGKUObZz6bG@0$_yOE@$?pT600A8IE#07fVhYc
z7C^yOEVHIS=BQXnu_QO~))(NLyZEb3;5@|cv}}2bpW;L0m^hV+&Ah~H3V(Ww18864
zBbKIM6u#nhbcxqbtlbT4fAI|6s5&n8qT3e%VqY70ctZSV6Tkw+V)}yyi35{iC|Ilu
zv4RZ|KSdvt2o>AE2`)@rw+04Jia)G`Ot`pX28|KoS0}+mireT*VNv3JlnOm1W+%aJ
zw0JR{>0-n?=(BRM;sGj#i4)iCg<ib4)PTOz;syzPN)X3UTq;rg4lUMa#CaVQuQ@9o
zYJtHd@!t)QIVY~5IAXH+;t^OnFaCsFOA+_evU5Sa?g%7P#g|lQOcS#<!;5tB1u8zj
zD4w?*mM)384d61xSAK$}EV1!Lpj;7mZh=qP;;hTi%Mq`x0ZOhozJl_FdE$znVD~EQ
z!r^?eir$|E;>7;}tx(Lo0#A#?A++%;77M=wxh77bS-&p!kpt$2xV{pgH^t|9(7Por
zq3}nEcp1h2O2yu_@S;o{b_^EE#hEGa_qKSFYI!Tf*qh<`s}z^bg<_TX^>!Gn76;P8
zS|iqe3dLIS6kW%u6Ax4J@{ZVf7qIKa``ppjAl^v@=8fWvB=j|jnN*wCEcOY6NQ*e^
zV~DhhpI8Wg+r&P!`m~Gp&INRbSTY0BDbAqtM3+^ZSpYY>#lj+J+!gPlom7ulNXu5Q
z*g=n>-4oZ-JE~9Yn+X&B;)90(Iv_U3!|r`?brrlH6!-6i-jH~E7c32nm-_>IMEn=6
zETiJ%^s$^VaY;6~2V&VHpp1(Te*-chwyvW3_(`!#FxV-v1Koa_7Ozf1<BT|U5zuDE
z?>vUShvEwq{(L09GY1BbNE|5qX)EzA17{}*m<P^Y!d?%~L6Wo-9y&_KDG%%<IrQJ&
zQt|_Zpj;#&bg|x5Qc9mMJ}TK@r8#kv)bE3$yX4cIFySG2VF<)ivgrUcj!6#D2cEqo
z$+QM~OFpAp**=npdT_pyRt{kNBtf(d^_L`_1lVy&$ulq!AX!O8XeT6}PU0^TDEW{U
zuOP{%w8;vVXsE_2Owy8S#jKx{{7AR9!X>^kbVf*KpM}9ll)huWq9k!*D4vqU(4Q$<
z68bC}V<aU3;9?~oXTwCCq~<eBe!Rr&1WTtSnb*N3NNQeyqluE{dGPRzL`u85vyucl
zt|m#;_knUw@{0KhJsvg5SMLGlyd;G}EGZJ%A;4UaoS+0ts-(098flW3=q;Qsnd_Sw
z$hQ7OUn9ws%%h`9mPAjd^DC0Qi(xif@+t++b0l>;A)hO`j>}K;^CTHhgS#qudk#eM
zC5g1nE|4^Zqp?sjLuDsLl99vkp;$8bUt~m*L%-PTk_B%9`i4a30mp7iI&MJWmL$ts
z1X>~~rIb^tq_F}cE0cUcC0gZ@RLa@hmLyiAuR>z+fHRen&50OFm1H+%cd8}H^Uzl#
zd1Vl!R&tfT$XO@(jy$|0sceO7^%52Rs2e1KJowZoSx@`TCP~t_fNqvFU!=D}i)63}
zXsr@Y%5Akt9DagEyF^WKr4Gr&SFqbDk<fX%OY$MDPu-Hw=m>jPvZD(MJrXJ9JbNV{
ztb@WmiLMHLeUjc60NpS7w;Un^l8W^h*?q|~C76Uk$sbhmHzaxWAG#+yEIBX_8Y7aN
z9JoI!`RZku7?bSRf;^Bcy@kGUN#ryXCnU-AtD2PD?nmR4q+thqnwDtj7&asMr5<Ef
zVn=DlBhv3F7-1__tb=QI(wDqp-d?(#!cq>>#gmY9l>UojCT`P6Z@mS(&eDmy&~T9!
z(+R{?+TZ}iqtgA|@WM?hsfBrWsf<pm9@2EG{q>Z7{tYZ0lSa`#%1hcr^=aNxeiS5q
zq<_((<11|vU`qU?zfvihzjP`GV8^BF*8(L#df;{FSx-p)C;}EJUHmJC79>r22O7cB
zT@(cgk?v0eOsI66l6YZK5!LRTlx9#pL%7tH&eIXn7Am}ml&+?yAxe6Nru&pM=Q&_U
zOU<hx86yp(%SW-&8}EaQle(UVy?E&oI!~XrN&^nSsRU^vU9L`)en{c1Gt$3leL5>$
zK?%Ynshp<toV4u=C?-og=xZ_OrKWA@OOYN50l6S8<im?p>3TZAr%4;>YF)bYOC#)F
zlzu{itV_~*d!S@UTf?DnS-N#D6f&jOFZaWImbC6=v|f?M?}1a<(yBDT<VXwB(3dOy
z^+ky0NmH5udR2PyEVz7W;VqyQNdG+!y+WxgEgnVEcsgDeOLe6{xh8!-0o-+I^G5)?
zA&nFP?4~qAiUHn|wtbDp5^1cJqD7_BX$>^Wq}}l_Q7(0Cgv@Peixx5!(iF<lR7zju
z1FcGGLp!!=sepdLHB#qdI8!UV_zV>4q_#CsxFbDO46u6XD|$3GNJr^)+bI2&szsZm
z>6g&gEZsvl(%Yo(=F#)lF6Gkpq(hoA0sT&Cya4mnCGDc$Y`1iP3P$cqi|nD%Bh98V
z#9nFpZFq4{+Dm08ebVJr2iPxt=??k^q@RYu;C<=(Hy|=7T}1JjAt`$!B!{KD?!t=^
zsf>vsjY=ad6h0i2o;VGI52U-2K*ps{y1?%V>63IPX;Rut$Hpn??N-1{OV7naWJa1q
zpG2CK?xH)m52aSR+WJT;ejI&AWFJrt&{nqA6DI6r9aLdrFYA9FoP%tJ4FyNpo|mEE
zB&!$FKg4sEUEzauk(ucr;wrPHW$UP{cQM>|lYK|$Yj;^J3w<842-;qF%8KeBa!fY&
z4G=FG5?y%kWLyel`N)EgV-kF2EH_~K$-d16@s|nd8t8FZqCG?cWFfT5o{)XMAL`aX
znTVFVAlceR_#G@;5QJfe$f~9x6Ds?(27ZUhhIRt<q^#8!jp4Eq4Sb4_9rzM@k+SXd
z(vOl2(#)Qct)Vz}v~2ieG{(pxV=+&$vi(#N7AGsi8EJmJY!Mx=Ps^T|1$2T{_SFK+
zP@>GU66B2RrXS3ol^vx>R+231V{qqW2k07VvaI|FOq`c(-wOQ{*<)T%xFCDxAe>2+
z`DH^SO}60zK+|Ol{zczK*=rQnx+J?d355(<!#KFhvXAM!m??AZ0hcASE=fV>71`tw
z=x597C{>jsYg+)AT-h&FVUjOv3B<4qWOM$4NTICp21t?YVhjdTEDPsC@|w)09H7@_
z*VX{+hHSDNeK%zXByjDPOhflhOJpmk5};IOuZ4P<ET983Q!dk6n_=R%Y=nMS6|!HK
zLbOsgb__68GUI$`RLesDg^3#3-OnLXD?9QS6zgQCZ=vswY|aCq)yux7_(y~6EjA{o
zQRb;cUz044?gcl?ezc;mMP_b;Gp(}jHbA$@7Tv)(+hq-7bY|#~ReT20DNE)<zf0!-
z8%VdzmbQ;~WeX`+)FaDn0O^%oq{Z`|Y=kyKeX<?jp|M{!L^;3#S>~(o{=O{u9KZ%;
zf770HNEUw|+_3DIJHQ-~mCze@R3-_7hhwsks)cy|9>|`_#VE#Q^XS7}6S8vJ3s1^C
zX}O$|4bb<Kr)3L{L1RX??iE;?l^uQ$pbupo?|^$GQ@jC@Bl1}@ux;h<w1cyg`_uDh
zFBg4<fjY=z=yl>KpQf@cCpniY2=L$Pu}!hgcahIhD$!M*{weGpmEWLid2aF|x;^VI
zPoOey54quEpn1x-(kA$ryo1h!Uh+Sxz<JBJQ>?&8?oClLU-=TMIq;JwHNu3y{0Vv+
z9+y{9N<BdSk{=A6kdM^kFA^xPDgdT6NN(H?jbOPGZSzCqo2MZYD!)kwiZJ=9qaY{c
z3tC_)Tpmf+wj$(TWy5@=yn@nSQSu}o^u@?M4*?}seoF!MIJq0;3*zNl8e#Xe{8<?W
zks$xk5h96lKgzS8kuQH1_Rd=6ItsKV$+?uHIw$`s0Va~=F?3izFHb7O&{E`wsH*;g
zd?}?+Qsraxs!Nl%c>^Y0o<=c>i*hCf058dHC}fu*f8%fTU6!w=#V=ESj<S?l@?~l`
zb44yx!tHGNNeYJK$gS;9!F;Z~>Nk))`EOHDyeeN3477at3)kUAfqXL+Zx_lt>EcU~
zTtbD;#qwD?I9-#E%7AuV-scRx8}ip^<9Sm)Qx1h&@_$RfmB`Q2R<Trm-2n<^avPe;
zayggG-j>H&Y0p+6_odu)rTo%)h*rs!qwuX-{^dgS)yN;ufcv%b<G~ncoji*POLyeo
z9zb8cd<~VGHOQIts5Hv)6UKul|ANX#n&rczn9&yb{ZS~i$~`D%)+RT#0i|7jB@iMV
z@|Ay6pr=z_Nauns`NP+s-z|TY15fYDckjSJd*ptUJ?NG18i0v=a^W(d^~vq&IMXlR
zPH+DKdFJPE=Dz%1G5QAOEvsN+NS;R5V20&Ss6j^L>uHNQD$l3%*O+|Ev)~@c>&>+P
z9G53hf!Tz-_IsdB%0FlZ%#?g446aSf_vJu;M*bA##AoH7oQI`{^2b(!Jd&TKyvh+p
z)p~HYiXBfv!A|iVRe{(m9x*{26iF*U92Mv3%SbMY(GD1LRY)nNeN=HkMlowQg_){c
z-4!2D9Nt6m!mHps6)hbY;W0%w{kpvrzbIkCTX8QNB0dUcG&o;H#8ve9DTWro3x7of
z6>%O{)c*;80~Av`(RV^ocmxW8ig{H27^Dce0?c5=#4jKriorq5g*8+$FCJ)N3ik8(
zC7o2<?1lMoMFO2DA{2kk1sAD!?<;6TDW+b9iBpQ1F@Q!ZcFu#{7)325(_$5mwSvSc
zc%=Z1SCsJ~a#|5K2cu6=gwiQ2Q6UL~PiGXLqyY1*VmuREl2y^!4ECHt<pi{3#YYrb
zI<MFn2E`P`D$4d>Q2a|d?Nr5n3M!^42B}6PT``gb{fmm~$6)Z1!i7?{8H!O3)GsTJ
z&^|6xaf&tpS&CSksOMi%Y@k3`w&Enc=W`SrW+9TRu*R^_ny0vS0s2=JKhtkLUonRQ
z5Cw`qL{KbL@GH<)q;R?f^TmpFRHuDS(Gvvh>xv}$ILQr#%Qj5VO$B=``fe#UDWOoJ
zsLp_TsbXjxmdX^B6tpT=*e76~ZY$Qk1q&65-2Z9}D-{l7(63T#q_<+VVrn@o)hJe$
zL9tdb>;{cG#pWkr>5k%8E*k3<FQ-AWLD3@y*Qi*v8C;X%X-ZQzE8hDWq($MZf?lg)
zFKr3h6#smUX>M0Mx{SsSg=r7CPQ{<mR*bhx5w;xObSn}U1Fct4v<EWx6jf1>=~J*N
zH{GxBr$5YqVn;hf?khg)g5IEFn;F<ciU8Vr4J#JX*>Xhjg%i|A6_b8Y7*n{t0q%jK
zhpq;UD?WP>6EvZyc^We_sqlQAzEd`(u$h6(w8H)dT4xmT0l=PBXlZB<6-G(}JW@1K
z{qPaxEJXlpm19Comz^?--gx#(jV(YOl#kI-+EIDZ7Nd7kuAqI9vvLJx7+jPETY>4S
zJe~z|R2eBlpPO=xGu1e`D|b?Y(L=fNAv!&k8;3E9W6Ir>WA;++q|=JG^2#sJ@KGAR
zgcrWb4WGc0pK>)NmHm}ZBtiYSa>o*=2Po4iiFiV}XdX}kl{cuSGDvyN4_*W-8MNyU
zQ7)k^b*R$R0L~hw{D{hVPb%9M047|yo0hEzrIjvdMk>!fhQ=r*;{sq#DPN(eUbK=+
z+ngAsBo5|dl{~r~8K?Y<!VB?AE#2uktu&s4dV+EjJ*kPxSE&NwjB=6!JZF_&Ua*^_
zOsA_1=d8-GU(lJXWZ){u{PW5!_hCLod6d5XazWWfey1w;QVBwuauK~0)0Nxb1NKGb
z1FE*Ur2J|z6f%_Ely$tUv=u@jQ<*S`$;(o@UxfEplvV-yvXy-w0wqV;PWyyh<s~Yd
z&r@1u?r`d=(%%B?d}UlO&<d27=qg5`Qb@VIBIT+;h!!h7dZB+!dBOqQP359?aJQ6l
zdMZkkmzP1IR2fLMU}Z{~H%yc(A4(x|TY2{|6e^SrCm>R(-1J|BQn~IX3{@+&|NT#q
z8s()c@U&LBSqg)7%8woa=8p0}0vhX;9I9GtP~MvcXrnUrQw*(1>Aeq)&C0dUfwU-p
ztbtyuvUeNC(x&wK2X@<)8|fU?q5P&CdY#Ijeufua$_}dS=vH1>59qtfg?s4y*Q3mw
z3yof7)iCt$DR=D!*Qfk321Dyt?$E;Efbu~e(C#Z=`yBd%%C{)=Fr>Ui!GdAsfyaO{
zqU;ue8&!7F#m_P2SUtE0%8M(YH?Az(4KF5?>jnTlspK4ip($ljJ=Hi(D^>JS*%@Uw
z6(!FqwFY26R36=i`Ff-*rIq4{>IwyQY*o(BLf=khr30hA%Df*QI;hstTgg!+rcIBN
z>Ze=~XVv2W!EG1S4q9(qRh6g|nSWFzc?n*)sic2{b62r!sm94el|faBo+`@|Ajeb-
zDxmMB>hXppZ`He0g5aY%z8q-2s!#q)%BlKKLDFCKZ3tkFtLlqjK0uX8+sPBE$nQV`
zRVDPq1gX|gjZ?6yz8dNws+q0m3sse#gBM{cKGkVjPpa~$&?Q{uc@J!a>gJPhI8x<K
zt7eocLkvr&RHeUzM5}&whifsa3-mIMRV`Qzg*a6TMW5nTYKrZgR+Wc9JwavD2`)wT
z)%#GmpkjJpo>Eo&sC@X6%7L;E8LC|Rsb99LDt?Ddw(2noa^$E|so*MCHDCu5H&lyb
zVfU6QVGl$~RR5#&L8<C9`gND7Hq+myTy?4m*tb>rUqhinwU3U{m8!L0!hDtL6b003
zRApNrS*ywq#Z=a**3e7wj>>~-2<lbVg@XWXP({~4v`M88fu&}ZF&krQQN0k25w@y6
zZG?WCDv6@L9jaV<?{=yVQH-)n^*kNbx>c)b=XY22x+~OsRJUmIdQ}~+Q0P+?(k8lJ
zHU3{9P<1yPefL%02+%mFny^w1bx5^51^UCPYT8VXsHXk`%&6+$E9e_jEsF>DK=r2!
z(8g7-z79txRP|E$G^sMsMtMrr^&Yqx)p8xMXH}dxK_04@1CV^AY99j15%shJD7NZ6
z3PjkeTd%=w2leW|X#eS`cKZc(oz%MzfjFzDdI9RHUPsl8N7Wv*-*!{;=o1<4>T@L^
z9_nH`fO)Dvqh0$kbr%J7ywxWu8{nf(FMuUq^^e~G+E2Z&1&#jd-Y$^i>K;mk1ga0e
z07F6Qwm&HT60FXoUt);belI#h)x8wG3R9=jmLNjCEeAu3RL@!<5~Y@GMq`XR;2C%k
zt7g4|zBu(+Uyua#Pzekss!!~P`7`S46ofjbo}`0rvf7bORp-@zmY^?H9ZGTSH1+RO
zbMXA7t3Ts`%}|@lF{aCEhwm{%nd)>Wpk=EIGGRAI{ni?|pR2B+(xE){Tso~^RWq8=
zm#=Q84`vjptyJq*tnN<-cTJsk8hzK*Cny<kL)}2PT5hV<&%v2ebv6?sWoiK(rLE=a
zo6#_MTYW_i^A&2&ADEg-wLQgcYt;AYFk7o`qJp40b@U~eXi)cXfYzw~wG+-XsjpM5
zMyvX5E)2G*_ffE*UF}FY`3`kXE=+W)Cw5^jy3}9NJ9R+)>sd73S2Ob=GH6x1(_n_w
zX;j2Htlqy2og?aNGH|2neY7haQ}3ap&jYpdXMh=3zZVOU3ANL^usf+XyakadbujIc
zrq#84fX%4?rl9q#y8CIEc&OgK3FMJ_g(Dh|Xd?c=#M)|Z4WiLbV|AqMhP{UQGte9~
zA38wBQFEQXiQ}ZPdmoL?njg|JCKpW(?O0tkX*<w&R1<mzqj%FZM1phIu)AU2Lz8(N
z*q)ln-$9OPKA_8}KAPo}*!0yzQQpl@^IAT};;(U_c*1c_w6zJH0h+pWbe_<NcEVtw
z<}HeZ2WiZ-D-6|qPsge-jdB&pNlg)Lp~5xK%wjGgG>a)Y9jUo|5ne=TcAN#+Db2g|
zGLF`)e;=4J8jt7D7^^wB4eD_k_oaZ2*Q^-^^l8nLvGn1t1Wg^iP0wi7Qhn-K4Ko5H
zNz+Jy#B&-Ox_y_d*^&;C^BUzi8dEj7REd<P`Be%oUGqi^P%dhoW5LoT%_trEGc@}t
zQF2-Hzjxqare?9PdkQY}i7+v_n$O+@R-Wc5dU~&F)KMS>n%^j^RIGWELYvn#^YVav
zU9&6*+BY;m#X{kxX6OpITbi$up-`gX+{W~lYJS~<zB0{Qt3k>&-n6N^t*NVmdWFW9
z4$GCAWt6tA(u`ZZK&v$yzsCI3X(lhjnLC;lr-4?l37}|XgGN6B6OEeZyD`2NO$zPC
zS~V7WrM79#%>mc0`Gekm9U93P%y(**Q0YOJ=1sbN)~z{k7*lsw!>6Ll9!-1}^m;YS
zVKm;;oLfM-^gfNc1ryV+*-Q)RfM)b{G!ALLRlu21jlv(IW14p<()d8rScJZDO>j9B
zCN$Q6F+r1>{`X*MO7p`H=$qC=(2_f&xkVKOvzm^tp#D(vUIiK-X_{#NWv6}lM-Y4M
z$Nm)Ta?oC-8VN`3j>|CNq?Oa>U!1ic(jm}A>lg%3S8ZA-MtD?PP0N&<woVUFckQF~
z;5@Y2VyJs*<LM3Ot-TWmJs)i)Rb%*SGyeqf(;C8o>95^MG4d1Iy5}*@KrIt5U+erJ
zZS79L1Zzv_t79SBBd!=zsP?IUU?N;=PceoFZR#O-5viS|*l(2fL?H~G(!NNO5Umvj
z0W?PYH`S2EYJFaXLY%hZLny>+<Ehg9v^Mbs#+#s>r1V*ecG)I~T+s3;tZYryu3|zl
zO*`a+&UCHS6=)Z=`B9j?OIqtSC}wCc(gn!N+J|!ZovGcq1td$G_Zi3)t&HCG+1kB+
z;BvGl=^{n0b}Ri7^0f2llJ8aR({wK(Uwg?L77Db9$Iw`)y+BKR(K_u21v-nhR{Ad1
zHSLW|_;y{}PbbqG+8rAKb5q;C52ClUk5O4)iB`V{Lo3y~{sz!8?Je3Klxz201-Y$V
z<~x|iwicoCV1A9ZPY#e;?V(rUQk}La2X^jg{pk^|*S`BWuo|>qFd)*X?fo88(WK?j
z!q==FoClE>Z4GT8TD7Ha@VZSKOLv>vwZaYHI<#}>eAlUsqoh!m_Q@33>(+if2Yq+7
z=~gP@=+Wv+(b}uM&<VwR+P?!p`n1negs@-xGX+ftw23Nk_qA&%ygI0L4u;5(wvB3!
zhqYdG!)io(nIgxd+E1u#c1-)>EE*qZ!|2l|<Jzh%P?*r}NduYGrdC68N-Mki3S?%r
z`)LFJP|IUtppUekboR8<P0-R~uiHTNXb!q}MnN2POZy?>q>J=@`{FWd{WBQZQQe)5
z=yKD2%Epk~b#b3T!b7Je&pdUH(;4cRPA<kUy>u?L%k<X0_AL~Abp9={>Z{vJtBjvc
z{T;>^pgTn=^AoxZ5BLzM6SJWZq<faCxPx^g^cCF@o#q16Lv=>$(`XITW$lE_NnNr(
zTElg56u*kl{qr`^B6Uf>p)X3udKP`BbZaRe5v_a2h`t!zD%!Hf>fAK|J+1qP3P%%k
z2kDiYsN0kcpU&vU-p3%$>XN1)lB9d^G6r!@7qSGB$-4GWtuTLHH%^C<6y4KwD7c_|
ztqS_7x{bTRrRj7Uh^Fg2p28$t)UBF^YnOD_=^jCbZaK~5W!;_UA(^RLR154Z-S3Ow
z(-qx~&G0u{S4Ho`9Nk9RO6BV6uYu(0s>9&gRh_Dgf`9osuWc|`pi@(!c%iQFBN!~w
z#Zl^_ShtWOA=h-G5V(I`m-spKZ|FV@fccxceW}2{rE8>9c!@5M3cX8p+i6!_ri<|a
zSFV$ULhrUNj;?H1=uY*+(Mp}ui%_W2+2K5AonNhciS`IJy2V_OTHP}g-Ko=^rxWiT
z-Oqo(V7;!f0g4T}geQR3sAEyCqe&N?fyQRtFP%VZ(Y-bYq*d2R+vql3^j=ItyKdf_
zn63_;{~q*p>K>=d!*_LS=(+CE%}am<Yp-q}6<*)dHNOb9Pv=D&hko744CoK&LTNXC
zUpGbN$%8r{N(m3?Hqe%6Shvj+{*LJKCBPolU3P%pm~JTr!yf2bPr$=*T{2z1n$U^v
zz^6&wC%54Jl<qQJx}4Ts=ma-o)dkLj-C5lmwUBwJOIro(N4l5jYR3`1nhIxZ^>uC-
zg`K`S4vqHuXV<`>gMOAS5j*N1QGJw?eos0;o%JDq!LEz`sYjSYSAAk9%pcXi8x9mV
z{prmh?)pR{hUB5=tpKK{-g@SB=pWPXp~I7xKH(r>y!Bg`V=z8?4c(mc)lXhTqn|$W
zdvN~xAErT$>*p_mUV#2xs$@K&pCZ=+^_2tQg7iPFfcaqk^%yjU=w)eu4%ItS5mA`F
zqY&hze)+dBAFg+^=EC6!{n`B>k@}y%fqs-eib4u8dOO;+#p=JKry@>&`aHad*H3H!
zcUrF$LnJ}Zq8wPFKKwmMp3!gl6x><;3aZ#n(mO^&@|=DPeXB58zj_rE&g&Q7LSu@)
zpHfm6^qYz(_?N2hc?(mTrvGz0I@9&*BpCfg{ocLkyQIJS6cjV`f6&Zc);~*Us7(F3
zWEjlSFQiWaT+tt}gWYVsV;+W`qkq>1Bv&6C2+2Hs1SQ0;>SJibl&=>~K(atTnuo?h
zz2hJS|BCc~M*yZ+KS}S&Yx-6JI<M<*P_E;K-fbZ)-PDI}1G%LirUkr2zmo@rQvEdw
zK9uQqn&Dcx-dF<ewmx|S>{jUeXP{82KP*LKmA?F0kZQfQ2Nr7dqlY0<t6ziaJ?s2B
z{nlT=-qG`hLF)A%(Ql_g{~8tHHtOG5g}G?bFDV3R)|*l=7cKhqV31b5-!=@ULtj8!
ztWLeZ4@`9FS$(kEt?#-A?ykP>RY>;eQz)m}tG`bnn|u1?CXhb;KVz5@YrlT>3ph2P
zf13`s_w_GOy~Uv3gANQsdf7CFHmpyi^!kWCk&@n{`ZwtGGNvDK1n2|(CR!oJ^***B
z6Z)1<U~p3Z!&e|v`tLpf%Cz3!9o&rm1wBM&^*>N0{zLsRl~+Bo>KXAE+7W}N3?^(1
zw*4?~X9!w|q1hYuegQ=X!{aMJ91WI#A?ai&ph%aqp=mu}Tnx+U)Z=P+AqIU%4cDob
z*3ED-361WCDvEu07#>nlf~O&e_7TSnr9~L7mtpJ(%zGQGUtEAwK8E+`mF{aeL<Q%5
zhLEK|^Ec$Z3QNZg5BC5qz)(vCEhh~5ZXkh%*;UXBGIY_ODcG=`3N%6tcC<2u8tkb&
zCCo6&0Om=<O(7a14g6-HL>Wp>ft)hDK|jP;Lx+|2NO1;H1VrNvPpaW?qT%D0F~MgH
zxlcp!tYN|#8tI1r?jl|^?51q!B||sG@-htEDp<N~cy$rbG7VjH&dD;k(IMoDK|pWH
zY{NhuNRHv*caY3A%zqk&@(jaN>Uq`BS7e2ye8Ui}j0J}9&9GExsHU?_k-_N?%tf)`
zLK;M_8O}Tnk?V$EG=RBbs1ZWsra?<Z;kOJ6K8L{)!+;4QrG~^g&?_^%z65&ZhLsf1
zzisHek9n#vD6hepO2Z~+a8(ApBb0b73{ELvYYdZA&QojfN`yw8VZIh)x?|wm0<_)`
zxy`pPhh?2z4TCL)q0b@GYFJ0d!ZyPP&JbxgoTem2hv5lNaGi$5!Em(8@KZT3yAA%a
z=(}rpBMNT!7#6q#rPol=2S@K2R?=Uj&mg6!dA}imvRwm)Nm9RWc-R9&gN6+i;D!t%
z)(Nn~hL3)L=!oHU+JlZ78X|!`X4po5(FcZqo(9^u;fXV_G-1eKgPSxw2uI(P;Ys>;
ztkVX?evpTT4XJSSkztPuu#Xs{`ypa$jBUkK+8Gaoz>vLBPPO+AM*qiQ&(ZkpYAZCH
zj2rg>)Y-V07F`$PcjsZr)%X{^_>LNnr2);&xS$Vc?#6n$Q|MvLpahkt@c|uXju{^x
zLZ6p0Yc)W<jrJ5+_c4Zhf%7${ybDP`qs0Z1{>E`8FpnEMcfpGQqxMfK?+-F=rI$po
z@zNt;hZq-7`D>_gV=Q38j2~TvhbN5(>DGR@@qaRiL>M;?12obYMKDpuAGbi^lyQ<G
z+tJ1!nm}TVYeO)WSYy;$kT_#=EEM96m8}3fZFHq*LxM3C4~2DpqH%gPV9pq0sG9Gr
z@$dz7CK)fw;Ql#d0}~p_#y(1+oi`d>z@-?|^Wn?|;{y8bQmWDaHn=q7Ed34Ajf<(Y
z^`a5=TzIIAO`AY6jD{~jE*rlY1<5oz)3G$mxa%?eMXXnhz7&|xHhxrw)*Rz9Iu_>|
zeb~UxGyanaa@ENC3!wSNJ=-vf0%OWmz!VzKz5%;M#{2W(eX;SY0&v%iTPe(U-8ev*
z&Kt(3=<jpWc$ezFZyB2?`%_{x(6=E<jU0REm069ad6=Pc<Fc1A!rR8mh47-n_z5jg
zmByb;Fj!^0M)~w=V?6~XYK%XBipE;w9{T&#89$&k`;Ia96ZF*^KkkQKgK?q&D2>L$
z#jw<5JW0WTR%5giMB0oS&cR;0arh2K)?u{nJpuhrWAAPF)@5|18&=)M^Hk@4*I1*2
zevk1G-Jj?+{`DF3?-|SEq0nb6p9hhC;|}_34H&B_Eq~wGjcK1hX!LpteM83O6y_T?
zK0SrL5o1pS42~MNo&(sJ@z*)9_rR#K?n3Lh(Ln3tlyQ+6`qRb+I{3^OtzCebHC}Xw
z=tE;2y-Xh&y(my|#3Z~2VrzQ*6eR6TviG59Z+e`zDGsKM^D$kHraved<Ye-)$LO6+
zCG_)fF@1Fj=3PyHQvBzrsqjlHWZX;*zd**_wB#&Ic$jw3rF2h|Bc08TnYze*FOw5R
z8@)~6(e(=-Q~vw#*VnX!Hp+gc)lY--HwA~H@3<+y4hjJ#ds@m)nATBNBhXYq_oaeN
z@$Z8RHpMIl7h<xHqTNcU=_lIMhMDB9ASX?`kwKgvZpyU-7hx(&1$LxKTaCsj)B8VS
zE>4*ycEfJ8DfJDY#h6~9jB>1LG8iIpCKVM*#GABqBl5IqMHxtf>6srf&55Q+`tZpa
z6Ps3nv!*XPsJuVPq+Sd5oM~q=WRgv?B<P<vZJxzMrI;dVOL4)ZcpP4&nhu=?Ni(S_
ztC0>7n7?Rxf}-D-Ob02ekztxo)j*d`W-4pRG`)TU2D40e{LpvB)O-w$xu!z8+>mEl
zy%n7Gs_E0E(9bvBd<HTFroa|>QD{2Wi@7W^ou`w3vFZ70fL=4@QsC^mDbyY0hABM<
z<fdtuUZ1y2TPaXcVp{YLxKfjvR)I28-&-(IZdyi#bGJ>~>hUM6FgekixzdzJ8PY1N
z>D?5_RGZjcAT_2|BSu(j@}ux`ooPN5U)?e7e;pe2rk#`pYB1%{n%`*Z%0yq2DS}GR
znoYH|^tYH?C@$1$s+<pnHdAjYJZv}3(2k(PWKV~yPLqJHI&_(SZ-ZX9>B(R^C*L(C
z`xGy;-kJlK`b<}8<J50zZ3h`J@hLui-!$ic=o>VdeL#jxO>_Zm*yO$rvovBd&^_o;
z(>e~2$4rh{(0gDyLsy~3O_8*YPMC6N(>rNOpqI&%>E<I0VcPTzg=A+;XDN+0YuaOd
zfX;`eFK8R~$mIM4G>({GroX4HIgeH;JG1i@XxN)yp(vJvd6b?^NAtb;P;fCHv_Ye*
zS-uG(N6m}q-kqCyi1L;0=7khi_b@-T51gmDhbjw>nbo)8p_kc)3dg+7K5tM>osap!
z%V_mA_g}-L`I-Nsnhk$*#s-k%=1UY62r$1w*9}jYms4;x(0qUvh9L8PTDpSGi?^UL
z#B2?P!BBJQVqk}vUp2s|lja3)0VUkr^feSB%#Sv~P^4LQ8$LyuYZEAKa?0%ZE7)jr
zI{lnt%<^I=#+u)20d}1E2TC8to4=wg#%c57T=XTFyOskj(X6Lii)YOF7ciG+%{|T#
zNir*Xp?A)lLocdiv(OHG=gn5S50+x?n1j9x=5X3Vr<xxtqjzDN`5xUgNH-@m!PAT8
zt8}0FlKH6`3?{?u^$>lR&2{ve&opOWhx=LPLxJeKVs7h&7un`lUV})EIpA%W&ow_u
zQ<-N@eh~^+%?s&}kZ)c=7mW(cD?h?m3eC-<P$)8gw;p4$7Mod_(70y4;t84S=7UcF
z=7!lb88SD`1vcPH&42$_)oi|z29a{}1*CiC-!_Y1fJlY;SxVJanuT0QR+-Z%a9eHG
zti>Q|%s(x~uxrh>v=gW^e@l{g%qP3R)tjH7&onhy&4OpaHkwm2fYxL#{S-3IX3h72
zX)&i2qp#Kc6fI$GW{(9JQ@i;Y3Tt+l-)RSSr`hENSn4txDc;v@E`AeZx@%@o7QV;q
zOHsyN^WVqe?>)1Qt~K|W*HP_KzxnZnfF3YgJt^FH-yB3m?1Sb-FGGLGoKS|&VY3H?
z??%jj($Y6-Zl)OPn0d_^xc0ytMN8kfd66C>6Xp_M=uMhK>3Zap+1LR~(`K)wFh66S
zUJ8X-^8?xmJT%)a0r$wPGQsU5mKUv~fU&h$_k*>w?3)XHd&{*pC^}dQe}zFu%d{Gb
zPL_|?!V70hYcCXBEXG0fxmxzno#&$#5ml_XS(vM!?ru4L7LpzoMF{#lEg{}8c+ArB
z12DZTzu1F#TaIPHo{#11^E4;EmIHGj6Kr{zq7fmMjFr$2wQL-Mr7+9;1DK1G7O!8?
z7;gEPE>lEU#{a>1BQ0}jZx?0R>4&~k7I{7TqAisap^mexdJ5|CmUmu<$Z5-3Dga5a
zSnfhH(c<_!$Qg_AAw|y4TDI(lr%9IG)sQ)75z|g0*|MDu3Fj@Aw*Z=A*+-2REZb=(
zkZSprUS??)5BhbdTb@4y6BjLZ6uh})S$Gs&hGj1;ewQtsg^<j&DCa^i+tPa<jX9Q4
zHAbClDYK!-S)S#LAK0sw!xR?Ix8zM=yakqpa=;W?R#IH4$WlQGmtxDQrD(inaa)Sn
zyKeCqhTaW}D;;=lT7KV+zFU?*i=j|rS(Ai6TB*hH9Qw*EEfgjyx7>RhBDXC`htOAH
zDR>9OT5XZGp|!>`^(AC#EuT;jrOu+I@W&lX-EG*dw`5azs=;De0n%vMJO>lpWJ#io
zN3&%KJ)$iZ-Yd{+wG=miv{@3q2Uxr1^xHt`u&ko*igsE;Uj|s0rMm;;?6y>f!R+0q
zEPqgGPmiU?*Q;ciwU$o&{gw~35E-xt7s12(miMS2aM1Ge0;msJH0L2QY>7PrkrB(1
zA7Ope@}L7CW0v`JkbPjOehJpcEt|wJJ7sw%2YS<%MZq9578ccS&01bd2KUgyrS#|{
z%XgGZv9+177J#+0VNs&r-saK>>^j(3=&$T(Gtv&bPBz7L;GAvlsxWvLoA)Uq>S`mQ
z;*O&>8|aMgW@DX%h`Y^iOnBj86G0a=JZ%opEA^NSCj$yzHnH?l^0slN=#Y;Mw*uqz
zwR!(DD-``~ex}@pzs;ROv>vzdoC_|%<`s%ep0HU;p@l%3T@*G9vbp*S8iQ@BZU8jI
z=Ey^UhT44I3QJ)&+eOejX)|^WT(}L7N@yc&thCXJv{^*?$tWAiAK*^?pQ9^}tFmgs
zYA%^sR$94cWvN-2<=yvv-(AwO%*-!M%S^LOyMPLciXb2&vI_{vzVC}5$|?w=B8Y$j
ziUNY*!ty;6|IF{4nP+Csx$kn$%$yfS94%AB7;A;JGYe-lz6PZcj4{VCrRNwP8L$-1
z$XN$x&NIHHxL*uoNf#WAW%N=&D2|ct3Vb}Ha4sw*FcvHZJdrW=9l(<qOX&hiW)#vs
zErszvdUmBUrggxXG{zlDwx%;=bdh8*26xjTrUJ&UAv6ma`{_}1fx)16Vi9A;Y?v=*
z{Ot&X7a6Bc1AmFZvtYcJ8NpN}T*^qK9YYx-!viAaj7L8~q>>R+3iDMAr4x8p7;%&V
zt7Z(ap{#~ckO4!rjK%KY)iJ)Iho$`*V=NVy)H5>wiy|<3=z6@tC~E-XCSzPSWEvRj
z!{OR3M$J{2Z)CjA$0(W@O`pN;ZN{6?7-2Kx31#)}FuLD{NDE`I5i`@uxU~@QHpWOj
zblzobqxJtihLTcs?TlVp%XQcph83Wlj0wx3^giQ%&mi-F(KZdhE=D8W_754msXXEl
z<EJ0c+0Dp^L92%$83E~K1W=6nG2<@@%=a;_QN3qBV=lS<grTPp!2rXNmNkQnL?&E&
z&X`Vh94{E5f5F}m<Ml53Wri7FKS1vYL*e;p&0_m+^!a}mrkzSP4lyG?gzCdgA>|}p
znNbucJi>HOg2*xED|)otm{+qPd7LSyu$wz`*<*BiFmo(Wd4hSM3ph{agKqG=n3?Z@
zcr%3*8$QWg^)7He%t<*AImLW=2>`y#U+wAWJ<ar|6|^7ILJ`z6%<b(Ml0P$&4-&w9
zhi<q)<`#OY2Qja0gGey5`5Al)VIC?)E0np00wZUcXQ&W8j9Gpb2E&;ywIC5pKP^Pg
zF;9L4gOSW>W%#Y5m=-G7k7lZ7&<gQ9b9y*_*BEAy7Km8pJPL!wF@0Y{E1sDmgZU)p
z^gu`^Gy7<Bo5IYd5N0aV`BS)^#{8QizUj<^6lBe0_HRNfi^*FKlFj_}bx7tgZ&5Kx
zE;E?IZu!i!&A=5f>w;;wR>%yX6KfZkbMr95BBnYAG8dVzQ<$=ZDWsC@OU#NtA#$0i
zn+0GgbK5;gmN5$`2UgCUKo83briQACE1BO=g>n^h_Yl0l!c3#eg=*#>|Ls?prviby
z%4EC&)wRqWc$e8H)G?bLq4yedNg#$+&lJB0#C7KJ|H^rpom5JC6F)3`YG4-hfp?3!
zC;++}nd9j?YGP(RhZnb*33PEaGx?NyxWgPzo7)!V+w@VYR%Uw!;BCz8n{f0lQ}8$D
z=^pbgm2KJEnO{pG)4@#PfOImqanakw+(vcf51F}n(EW%RI|2A^=6Z@R_Aobp0+C*(
zKW$F>n7nzw^)o$|pz{fH+Pi2CFdN^87lX{D@v!ua89=$L=gcXugS=qgB`rhDFR~yq
zY-c{FTV<44K)Wsn)}KzW>&R;P0xc(2RW$JXS@nOwivz5WXq9o0^}a8NGfO!G+FV#g
zRM2yXRaJ|*ILul$fR-!k*e$e<u%iCNj2>lq)Ae|aHERkCxv@4;(Em8=@7d^dXW6S$
zFee_Y2g_jM1nWBG96eb<Az*s3ey1?MH|rZJraZ~I8U~+ySfgXmd5YCU$r)ePR}%Pp
znpH;2T|ZXne<kxQhaG_XvsTj1E`YW29e5GQ+WI}r2eDZ1LrXC0Tn7w=u->!xqBo4?
z^c-G<vp&cIFoNYsVd!(L`CQ;5S+4YsiDG3N&>79zrUM{`#i0{Iv8+HkmKDePwh&&#
zv!dv|mB8{}g3d&i8%02qST&2mOJSAp0Z3)7q3vQCt1<__K{{(*KSe7uSg$3)QYNcX
z36jO?y$s*7S)cxkG3BtXo<b{^C8O+r9;=!PR|;4sDlrL#tkXegU0^v;VyuYeK^dE3
zR#hWRTx9)Bmq!U}n1b1tSvDb5m$JSKf=C%_J)JfzXKkKI@5Bn$ivXCYWXT=_Sj8Gn
z0jXxyQF@_<mB)petE~TB2BMbL+X-GBtG5ZfYpfG=@Uxy3v<u`0Ym7U{P1c@Vm}p?_
zqNnpM)<mkXX=E+DgwAFbgN;GlVKvk7n-<nTZ;Tn^Sz7;!eTOIfzsu^SXZJnUecD`g
zumqH`?PO)s?(sfLm<5pstVQ2LPZw*;9k}t3^#@h1JYtD|1L<M;(b4^0)}wYf{FvqR
z9sqr;TU0>R&$_!0ttYJMZcshII^hN_gRC(TaPcXt)V?0gXROb?@IyUky+<cAhFEJp
zhniv5<N&xj!Wv5}uu+!lc9?Kr*H1vFBiob0cTVgb5=b6kyIY~{Ap4UIfIGAI{tbW&
zJAk(JhuD|tyzF6icnol^>_0kS?<hMT=PD;0V^<E*F2Rkxm<}u)XFG+X*PU%r!C?>f
zcT}Exg56D5xfgr=dhop2Z~g<oNj8^KYCi0b7J-~%AN&$Z{n#m$&~k=tiie~>`{PWs
z0@$m&&<bSdQY~l@JNpexS1|k9HMkwhUiuIHtHiTxm!BXL#$Hcf2@PlOn*(43d$~V4
z&$0id(MPiXM+^IC_GWj8oM(rXpfiT;9*@pgwkHME;@Iu)qJ{r$eGa??_N%Tin8=Q%
zRcsRbYr1ih*_&2kWGU?b(fyFd-Z6Fzp26wtne_O{V7E@hC^Fd>XwQ(vUaQ5=mCf#=
zBT+f*#9oNxvAJU)lF#;3f)udxv!SMtofm*fxWHbx1g#?W#{Do+%q}hmDPg;mqw^Bm
zix%dW*-J}6O4<2)!7F3u(78K%IeUi)G8OES!yr}cK3_1eu=TXIt!4+(>D?N(t^}P|
z*?!wGGuPO~YK*X+-TVPuyUt!e1d$u;E;<u?lU?D0&IYy%?e}i6MaMvz*k9y=+-A?F
z<wi4mDjlM|!#1pf`4&5S<xc2sWiONh-^RW}brAR1pZEgN&bHG+xr6<ppKb^CYcBzD
zpS`dJ1|P83{RYy--aY`_L-yWzn65``VF_B@>~AT6(8E4+AI>~xFQmsuANw=<4@muN
z!2x*jguTNC)dOsMBW0ro*{@TX)Kj+CyFfh0Pl<uPU?)$4=ny+(D@2FcKHorcg#81Z
z%^PJO{0hH_1Bc@X;>1}^#nk&bA5ft00OzMRkb@jE{jScOYxE3u;mm&m+#ya62a>Lw
zHz|jGg!7~QLzp<q3Huo`$2di2A>+pRhBgKsoH{x)c7jtw?+#Cn><=KkIEP*Z&zm!2
zD*Qdk5s-)vr>zzq`f`@#p>>*5rUk%{v#tWeKEo-cMTkGAoCjP0=PU)g0yz^(U@w?6
z>3utTLpb~YLNk=}%5?a4mLvZIUW9QNRCXQC+2D)8L~t(9^6VUknFtce;nPzqiW9UE
z@MzAzR5KsLX{5(SEazY+aB-X^dGI%$bAfi?37p$oz)R%BQKl-1^XElaNa5_Mru#3I
zvx|xr(>R}Ag|>7KYaRT~;0%pNXEsMpwd*+?CS9|+9DXo>d7LC7`J9iwgSG-r8hKdA
zd522hi#Us@;;5LzbwTSQ=Se2amvBy;hufDp+6|be%N+g@s4nH497BiO$~iC7`>cYq
zg=$eNIbr+Is^WObq5BFa<`r~Sb6B*bui?z4rQcOfmmf$iXC+0Y>o`~Fxc)WHwh?%L
zoij>npc@>oFJb;BXAVUL8#u30asDk%2vv<Vaz62ZGff=sFW}jmIorY^dWUmm0HlS(
z9D=1*&R27xyNz@HGGy90x4yxcIyguD(b>s)Ru24q&LFLEA8;N`MyrdXH9_PdCz+zz
z-JIx3w0byeJ_qULl(a(iW6rogpsbJc&pXi4&-uU%_!B#4kaB>7oXPacdCHkz18vVZ
z-^HNyoa0Kl_ZOT~6oVS#2xxmV%y~d{i6fkCl#3hXMBav^12=~*OGoZnIi_nr_b8Qb
z9N>nJ13Ae3l1}3|bDz?y(uKQ=%KZ*;FD8I@m}^&4eCh}{lna@oTszfdALFW)LB@@{
zmG*zfxj*iJ$O*0`4lPgaSSkwj;)YZ0i#JzH`;3!Zx34i6A8!6sjO7$}dmk*F=K52?
zk{|cAZs5*vm(Y&QpF2z;)d23adi)}R+-&;@nnB!kw9p9QPN%|)P_ENhkh9zu^rj8t
zYA7@l&h1?Yd<1txJ}jN%8fX<B$*s5v$tZ3^FeIb7;nTr8&ppb(SYo+~OaS7zU1QOT
z=kBmUGJzXKOTR?!%1D?`;-;oiem$8Rvme@0xvPH0oTPD!?}DUrO+NvV!M)`P(M)au
zJ*9KF3n}E0%iT}`kv#5%85nOqcQ(bo3b<{Q%P!>p^BZ(t;A+0Wkczm@w3jXB{vC(T
z67Hd?5V^$F>)_L6uG4AyAYv(Z;a89;<NAr9yMmidfw)TU$Miw^D(*uRp-iae=Fw}v
zh8v{ATwLYG(nhY9yOEx#b=<`akZassJ<wgxZH<C!H@Mf2f!yRW>!G@VJ8v8Sx43R}
zG_R5S8todIxKA_`CA-btO&hX1+<}*&yM<eQ7&5Kg85BZj<36OI@m=mGl=i;I{r4+)
z*vWOd1^4fBz11KOxI+}>>f(;0W&1<!&vfHF;!dSn?ryH@6DaH9vT2dn%e}A$q>pQn
zLs>t!gw|#DC)}gakQv|}rkvU!cX|obJmd1{4AygQvK5^#xbl8<4s#Q!j(>!EEf%d&
z?wSqYIq+WDjUUF5r%iwsC*JgawD$8DEa*PS6IVdenKy?@Z(Ml0>GbR&UVakXKFqsQ
z24${xUVsNI9pUNf;P)}!FItGY@xG4+^EfY@-u~{qKj@+D!Q1-^cqe$KxlrTHn|lDQ
zlf2WLFi;<!*Pm#e;+0X5+?N+if&0_E<Yct`c-=O%&hU~7;EX@-I3@N1c?NfQ5ybm4
zcmbNhJUOjQLU<~AFo*IgN-_CiysZ@c4d>-<h8GdMSSs_3<b`_v-ZI;6qs&$;??(Xy
z<9OW?pc8lvdm*35Teb)!iFcV!M<(-(bWf)6v~R+fRNjxjpfio<nu;qRgV#X2vP|CG
z48XH^8=GMuo41kP?>W5Le01jWru#uz0q=kSS_*knt^<C7cYOwxX%_J|(S1|QTXg~C
zB5#c6{MPCARJxc;dHKJBl<`U*15nNzrE|y?yzU3+tmM5Lg;7@V`U23p!dpV&{%W4M
z31(|}aVC(fyaj6ksO4Rc0;%I&D}|QpJO|nf-r)JrUi~KTo8KYXz^kKgOWopaItz~)
zd4kudV4;bJ5&<lEcvC$K;8NO~0JQQ1QW$FE-S>gAyS#5Gx_Xay<N_|3c3vqHsyld#
zf5)IZd2x9_-{)<l)5s5a4J!ff;$_g4-OcO&0%m)7Yl6_~<!zvEO+4m(c^f0@<Hb@8
zzMr@03s`u<oBaiJ4)A#PJy1HxTS<$@r@S5eL7wquQC|2t@3%|v;stLLRe%ifme7iF
znD^WazzFa6y=aZ{;;>Gg;K1+x3`!mOd@AR1;&Yy(wV&^{2|Q>1Agx<m_}do4-$VQv
zbk5)~e~cGYyYg46=m66Zem5<>kMdt8gU9$A>OtK2AJMlEj`I)Fh33wW8V5Be_$_16
z>B;|zLcU)7@<HId`4>09(n<ca8rb#W&-4O0#ZRVKpfCSRTDP3$f9ndkAAe>LcxU)K
zXMqIpkN8rYC6J#$)vrPP$rOnS=5M4eRS5rcDnJS4htXFe&hodP#mt29l~hC!&JUjr
zd<6ee3wY=F!c8Di{7=7!7t#DH^g*xl{PEY|S`6QHB_w0{?k|JH@&C+%7xDa8SAmzn
z?{K5<Pbcy{AEGyjZ<-H$GCzQ>r!@W&S|_IS=e>{dX7Ftr;Y=pqo6@#f{Ec)$Wb+qH
zLT3(t{&tKomw$gDNFIO6>oA|spC<;cfPZT&#&Ur_X%E~k;-}G<n~M1w%A{T7-*gAh
zUc$FN0^$;X(gKjn{LI}LXeodEmq3*9f27))a{inY@GAJHU4gISPaB5&SNLD<KxZ{S
z^L_jjHT>o)z+L6f5yQ1wzT-}qsN)|<2jCjN-4SD{=U<|P`*pr?BSdcSb+k2Uu=A%?
zgWlpl?|^6{UrkqF6JJMXsc-XDjv&qaXg+{<_<=e|w(xm7VYik47Df8n_`dYEyUUOK
z3O;r4b1q>_o%~sJ3i3WbZWQDJzk?FrU3|rCkca$BPvGw(eitoxy7^z$Q5vU*|A?YY
zy?jRs@IU6)+=OU9-|;=jJmHVlz~KS@K?O_<@;~x)XrFEmKMK!Y@Lk^pdWb)PN{xs4
zQVJN4@L&G{#6d8FK3d`^$omD7P6EaUP_kbzN)=281Y4TXIw)`p1aTHzq-(`RaMuTb
zLxO`eF^2`CUqQ92ATJFfM+G&s(>*5mq6~)I1fzC3`fywzPXNMQ(EbyMhu|FD+9w2h
zdgyoxeE!=L2rPJ!PVg3-It*<m1>JNS*H@tMLF=?2_%)2rPq2p)v}Xiw90Bncye$F=
z5NvoGZU+h`904FmP?!h{!GZvKzJv&d_*BdiDiDr9G)(X=ZE(T`AuAvnA+S~hcuwH*
zJxoLjR#PG&O3+3TuV}%f0XTDBz@p`QjNs5l;9>;_-UcpCaF<>>2?7CaR}uxg#=}yQ
zz=hsR$$}gHXr%~xsBj}y;C_j2+cZJr6qrvJlq)do48f{6D9sf7MHQ)8f?sGOnIm{;
z0zOv|mjX+9f}NBk&lmhf>(~Opi-RDAf^LeaUl1(31rtSr3Qv$?LBTHIE($)r2A@g<
zK|-i56&$C9bD7}#PD)vn3mj-qULp8}wnCKxEei&#1j~29nJa>9S}axzisGTBM!=&Q
z<Ew((8UShq3wt4XO|aVq6I3sl!vpWSpdkgiZwNx^y>U};;0{C@1phk&a!as%6=t+i
z&_g?^CP9cJ0QTF0ee?ux7EDNmOpD-56G*F|^fsJn6RfTT@2;RM5x{$bJM_kH7pNbj
zvqSI-eG;HkaP>z>-WNF61NT7i)p&?>3I68*kw=0_bTf4eN;t68BRC#_LG%jNQSsYj
zfrm3lpIwl#9*BOy)_geiL?G^j=zySNJ@A8q-lIS~6)dF?*$aUqZ99ep_vjZH7Vs%F
zJ|b9fA0nfI@n=CCgp+@UK}VqzdFUj(8x68w=;;Lb0ilpeaSjUiuEUJF2;~&?KO|hR
zFBibWLfd?J<0|~w8KOsok3NMnM}-@E@WUPxZuDICV7h&NHI#V>k5kCRQ|L=)l)Qvh
ztD)0dSeXUElfrpd(CH)0-UJ6v2~WR*makAo22Km@alrWrn;u}c&Ilvv@V~$CXb8q0
zC>*8&gCOA%Dx?S&ddkrX5pGRED^$3-0T#{*x7y=jB22iN>gdCT%R3<xA+#4`5a)!S
z_QPPLFe(sA&kHjtdL1Jir7d}^aJ~Zu7AMT6{YkuV9@PdX2*)KtS)%ahP2iG*P4rMt
z7M4b#l_GpXi|JHh4%IKE3*D)bAw%d`NqhKAVFf(|vV_|dz-J5H>2;YS{HGdrbA`Vu
zz{?XZcL&KAZpBMwLV@rl2^=jHhSC0{NVtyT`o+Q|Ds{go^x6YbBK+e#EL{>7(tG`~
zu&M~~QlUo>;AO%~TR_T%7q<QvM-|%UU`&-leI?9a5#nKvdqeo16l!XO-%$qPs&LZ_
z_*5%gN?Y<eVV4@@nsAL3YU+jWxI*`J;gwLdZU_fk;LJ^-N&`Tn@a8ZE(IgzV0OYnX
za0^to2*>;hUaPQu5gpKP6JDT6=n@9_z~Dn+4DEy-3D@VtZnw}%@$Mes@l_zb!p&4y
z{#dv!9wz#PZ~O?!e&GZoM)*Yd{2&G~Anf`VtwG^}SrB<Dd_EhU&xE{hA^BYR!*0M|
z2zSwobx8Q(1emoC3;(7Z;fQd<Mvzfq!w2Yf5dFRb2uD%f4v0F50_bai`$axf{CPms
zJPYGJC~~CSnX@Qdg2A|mzW56U4~g2HpyjY=n*hXB^qBy-Bce?UFzlnEO;j^}Or$;q
zEpDR8l)pG`7bVaW&0W;z0ECBVRy2A~h$d43p{Gc>7CbM}=3jvK7X331yptmJH<)}M
z(WXSGIVG}L(CI7sjb6d0MQiA1_7hE+1l$?XLQ2y4iyG;n6(E{Mg@b{jH|f<KBpOG1
z@L-X>y#l=<q7qvAhKkIeLg`u2V>*lzCK?R|K3r741)>q6Q^OEBCwg}trX*6d^D~er
z(E=OB6fN@I50UetUr%GaF`~CyFf*|ty93;g6aBIrlJO!wT>=TBzo;}OQM6tH$t2O&
zc6!Vui!KDgsT9#&N)M!pTCaeaCTgbDNxDcwdH)R2ZCbf!iay!~K$fWQ4|L{=Yyvo%
zC;FWBo%y0aXf;(J`irUv3Pnp&A#y<!PDMvWqLw(oi$%Ljz`H22Q#pHy=$(g@+rNa#
zfThc#<@B&E6`83hpiERo7hAdL0}6Lnh^E|y-Ad89T>w;xPSSGqim01*b=9J5y8miK
zW~%YMD)Ntn?po0=lt!r&^=yO}*F>L90=!;yor+bji!LXi^M+`Jj$&vxMgMDsng&rH
zrF(CQz8;3%Mv-tWls1Vz%mU)J=r|qwX%-#612uO<3HM;4MI@$U%B><j1<%?<=Q9Af
zE80$%$34*j4S4M$HKq7FM1EVKrBn3s2k5*nx?F;BJ`hDbn1K7QOT?v3_(PF^zAp4g
z<Un_0x2TzeR*%TJ06z7K#<c?YShR2mtv*rLS^)Y*2g@PyL=@Wuy91&vd*R`rXl(;T
zo{H`-hrwr}-8zUo7cHeV^9#|ksTlT<Xmc7whDGz~!Dt^5b<<{QROB!dN*%=Q=YVh&
zXP<<OlQ@@>n)}7C(HruBIQAnbJt&sZHs4wN%kL0z5qrD9wL@apchNd5eu+LG;VRxm
zEBGVgcg-M2#nn{2a7?`W1RQl2pYMPL4{_CaNS?5Z2k1PBr+7S7dw7Xc-v+{4oT~-%
zr1&du0DZ&`^U*pb?!FAXueh)ot<&Nuw*c@HAD~6u8L^oPaQ($0bl(SvA5r0Dpg4<)
zX@bO~w0;W~2Q9$pL&SdV;Dw4~D1?4iZ0}2gOqh6-qJ80F?oS{Q;{4Zf37iu@e+!;Q
zin+f*G)g>Y2Fyo`pP0crFOH&mkQi~U2Sj4UzZIbsCswWoJYHNf49NuX$W*9K6i3i@
zAW8h*F0_)xQMAEN5p$^aG*vv?o(bJ);$(6vT|74nYBI#X216!O{O>gIvc%(P0hTQ;
zptyRDINJ=7TyY#l#Ph^o(^IcdJQ4xG1#t}>p(qlksWCIf;^$PNc~Sg)D^!<=tLeDi
zCGmEu9Jws+Edsn${Nr)TA(e?;n*b~qzkd*<LVPnAqLt#&225#{*suznSHxFeg|=$3
z<80t-#b-1ib>b_O?ztwOBZi~(;sgrVUKgiRB>jeX?Q*ETDXynYNrSky3R-T7b0|I4
zC_X_&KuzLzSz}(s%_Sa#zX{FauRZhorrTelXJ4Cm=m$*mT``}o>U-k6XCUq3aa14M
zA%40L);q-|RI+$qTsRGe9*Fnc2I&$nvjP54Tr?S;JrXyqfuU}(o$^9GVwMa#d&Qq*
zfcIEDbPtk!;_;M7?ib&PL+2CmReL^k4~RdeIMtx|SBjN96>DW^JrhrnLCte<%|ra4
zFT_C<4;&JAdqL^2cuX-yHX?TX79ykK057=aAW7K^-HwvHE=W2_UjGo&v|o}<<!%Qg
zYw7iOP;!}4IL?ySXM*P<**3-w;33J&TVU|8WHsePTqS#U!;2%5Ie)^%qmmg_z#o%r
zI*FmVNlr`y{<!2lDnW9W@Tg+gL&7Qm?}Q{M0+ODRR}E0+C0X|hT=SNQmx6avBKJh6
zk7Q&Gyf`IckQQG_%5~Z~oR)mC3!;9K9?Ei^kv!Q7FZ?Cee#it!+*_bDP%?+g$buxe
zjd5>DGHC4(B3VzhY@w3Re+E2UBA~lJLXu3$jB}D->57k(?2LrYC`mLQozaqyN8!wQ
zNlykW#7LGXsSG|=BBxs4ILU-!^u|lJtwAe6vWH^GiIQhFs7aD+r!7aaq}Cg1QY5cZ
zpf*+VcNAJ_l1;QxOPA!+4mLxw;S~TfCC2s8k|k-QG+egi<6+p%k>tjsGgsn29g=wx
zu^cUXzNE_o%>v0sM={Vs$uobD3zF=;&|M@63WT;|$xaF`UX;}Tizz9Qn7;?_5~_=U
zyDT~XBTSS^ex3(yWs+@;Xq8Jo&qu35^5qkVR7xIS#}8U13C@GEE0Q`|16NCGDIQp3
zm#hrIV6IBc$KYbEq~&8+s*~i<>iN2)s|@%Xk|{ADHzitk02?I7wt{y{^7H{LHA+(G
z8PX&fDTc^xiI8F^&61ZGkh~-Lw+LReNRrONLaQWXJ#cLjCwiscm23=$PxmDDQ99|;
zF8NFb(jl4l5}fLky!17c-k1C~9<2wGlNX?^OX5V)>W7kMI{EQPayk<DZi&YY@OmT%
zY01<p@t+UxA4~qohe)3!oeBy2C7mLS?1^Lr<yQwJyWfEMLCF>>9(pQy!`_T3eJ1e=
z0OGmi$PzGLNOn+ge@Jq{A4-QM-_`&)BC%|Pwo%CdRrotdWBA}XO6OBT$VpmEdyf6m
z5AK0?K+60c$_`4m&?$FkX%=M>U8LL(05~L#<H7D>X{RGZT&13`&=<RoNSD%E<*0Q3
zQfNCS-9VL-ZqjxWfXAh)+R*7PT|`eG59z-mNS=^REdcS9PPW6Ym$cCzJa4Jo2y#;D
zOb38{q=l4oIwc+04lTaYuclx~r={=H)6P$NmI5+oq*rdxM>PDUr>XocKq{c}tUzfS
zt)+vct7!!lEOqEcD@3}3(!-(B5MQ*;N=N<$AWS-s{!>A?G?OCt5z=a3j3r9yMX|AH
z=^K*(I4_+@Z{HZH3q_S;r79!L$4U2n3KB0(nMPmCOOWo{27IE_T@I2Y-FF^plBErl
zkxh|4oD7mG-Qf(^(xg);nvgEt{wuu5kT(4W-I>xqonR?TnogHMwv^=zc#d@F0!-ve
zXHlFmPr6|lNWOIUJy<A^uDAqJD6OK!iv5Cg-h7xSlBUonNQ$N08(?0PPNk!zCDN|X
zK`u$<B8Xg;hGzm%Dh*!&XUe1-=EGpQ^kWewp+fpv9ZXb83+c=9RZ_Mme7YjdrSiFI
z=?`>RzDD}N43Mi*Rx}LNO6w)iS!b7Ww?O8a)R*4A_0k!1nOv8C{RpBrq(k)9za=fB
ze^J^f?fe@`o20?0N11S2+DLh+W@+Rcbl#C>4Z*b*>5><4rd9e@H9TyS7XJ$^cctIb
z?(v?~gBDlq(mINRbx8j>0Y^Kf_Dyu);J$RrZCH9BjkpWaCH>+!fDffhY2Eoq8l4Uk
z-O@80AbO-}Ecn|iJwOM89!s<6gGGJPiIhX_m#(2w+9%SN7Q_62^bSSE2BqZ`5_u{O
zy92;8slo@m=TiP3=zJml)82>PA!#ffbQqRuQqdZb2Gb};r2)P$=pftO3*so_)B4Xz
zrgVU7`(<s5q5FVrE5#BI%3jb*##t6d8wnTL((mELA=%YNC_5}GpfYh+*~@=H=MmYZ
z69Bl$0w@=GT$ZxS4maFo|0DtLA=}c9-V?HAufZ8l*-!E4^pb7p!<2Z-qN$Yjq|Bm&
z`#!RX`=R@kY~|<R`O03Qg1OVOSQ@CGOh#|vGqN9P@9Zxt`vrg?*)J5F2$l`e<|srK
z#DQd}EOG{I$j{0aQFJ0qwwFEy6)wwnh5HdQXK#>mvdVMN7Abp30k|kxG8O(u%T7_6
z^}NhLBt~ZR120yV^BP7UCtLIzl*P;bm0`LPWLw^b7m2bys<}v#J$(rx$+BL`5~av?
zI#FR^s%$6*LrasTO+s(FY<VfPWyl7pYA{pQ(gt9b%$JT;Wy|cehR=~Xi(n#GcD?~3
zd9p6b>F3KX`~i^y**A1u70U9$fV&_IrQ}+Xtdkz(#WDq@qc6(lw?RvZY<LjP*e}Vx
zrYFT^neAUFEtNf&08xg2+>6nd%bJDYRmf)C0IyQ^`7F#{m2B$-jHy}{TMiR7vdxn~
zuF5La;MK}f*Tb1Q+3vY8cugj^L9$-fw;z_S%l6VZZ^&*?Xy&GDCe3eyUG^5Gxo*kY
zD74uqTSLGmnU-?ow`KiwB{a)EqJ(g(%t~J;YLnGcspnmp_5*a@lifQCc)N@r0Hqx=
zBRzCGWs~S3a$lB1m*oT5IbXQeC7Z**upi2vegct4vLF#!-7<T>J7juf-%wd{uk7b`
zsCg`VMi*kAY|1pK>6a-b=zJmz{}jLhnfG}B24#a(XYf>ZlRk#?Ot$JYc+X|358?I;
zS=={JHY8Jef(*+NDq(3vRv!rOM`gW7pwmH~_!36%C?DgQJ2KI}m*Up@<${TjI3Q<a
zLgJu&);y?mme*y2=OW*}7@7~sNAE-BVfpp_Xt~OpKZ4{Dx%Vm<I4ZwEsp4aDT`ff1
z<bS0Ceq27c6(a6(Hihmz<dqc8Iw3d4V|bqOndd;f<jd?upx*M^v;jCN*B4^6KJxG#
zz@L&k(-{+AdDsMu_O$#T+RgaMk1hi_BcB}up1-`54pIfk|D>|OK>5#<4-Jz4MxpUw
zc`ZfpLgcSCK{8ang>n>U<(fX&3zOgR10Y=firEetA-{SWYR<`L{s2Uz{29GcqvSnO
zxF0PKrak(3xo04h#>jsk#wcRtzh<HpC*KtT5-(qy4&4dzbr)bMQJzU5t0Z|nWj2%L
zdb-_H<i{qXl`20)HKb|sqzfSF^5O@y2F{Q>w*!$W|L7hpWyx1iawA)wPZh^G@|oX4
zG*`aBANV}^dlcBum%nxdk_GZX^1e`BLsx3CJlzY<T$G!P=q!<6p)k!Qxswrq%ku4K
zz$=xP-vqBr{{CU`%H=n)t+h|6kk1bVvr_(fDJ)gV!wz7CSL8LcZL5~2xWQ75eCBnK
ztMWZ(0IZdJw}8~i|11XJnw;|j=IiBUsQ_G;*ABw%8}b#aG0!*USH@s04f0pnfZviQ
z)8@QU{sR>(H_0`$cDCP^^GgA2misE<=^c5)bSQ0+v(|#N%Ec^*w#gR`!o$1rt>-Yo
z_vF8R27~SLlrP{#huq~Q@H*wId_nHZizp`XK(3>RS(p5)|86@u`zW+LlD|y#Cf)KP
z3WN2?J>G`0Uc3A-T}hASrQ3n%lk4d<-!DJ-GPFIB2mXTAfc%$rFgPf0pepF6@>x{4
z@l1YyEIfQJANLH}UdUhm4w6IiE1vLaSiX*)0V8s^_n>oBzC!_=gJLqJcpMcc{V+}^
zh5a#n+OM!LOh@kl#dHd39#rJ61JGG9Ks#U;#q0ZE;*eq)z4Q+&(k<w8RWx5k=MhB-
ztxk?A65av)m}1)RFz=>Nv_a&!V(&V1x+_Yy!LEnm;y>{IgksGHAfAey<KeHDV#9~v
zom70hg6<9<MJ`p{oKm#V&E=~o;XwCk#o~MrKgDmKqw|cyb_Tlr74>uwHbAkJUh{#9
zom2x8r1(1)tzd<nN~}T@`+cUpG<Ldu39Yun6`78(6rm8(a`l{Ir2*z66@Tk6&L~C3
zN8m*(dMF5SUZJ=Mkr>5W<!Hq!X1#z&oMQhxXo*)`qV!yXVjn$j5*6D!!Anw<P<|{~
zal-*)NKw4G6|Gc7UJ-a{ifwj!sHZEIQMxNbv34GSnF<+Icx5Su4?#3r@g<qaQQW3&
zSFR$JLbrK}UwzQZSFELx6)1kA5~o7N%sU_#6!Yl_Mv<cZHF#L8sG@kzMa5c*zLzM@
z)ARR|V)K58lq!B6u){=|!sLS9azzwnqAL`8ZURxMNL&p>mEw;q7`&qR;y!+uYQ=;+
zv}zPX3(&f%5K_{&R`C_>3hEU7iE#9qVlG{4^@<H*@UAPaO$6_TB96A>Hx)-|liZ+~
z=77#yiZ24`d%TT`e{29YDHsbd?AwYJ6ftX7{Injf-BDPkKwFDq&usu(6@#>QZBxvr
zb1!!lskBGAr?_1QKs)|190t*$ICdM#Iu+mN!^C~XJ}ORnpqNf6r7p#!YakC5k8q-H
z!Xw46_+9N2x)oJinCMZAb;r<p6<e1>&11#i6szh}yr9QTzvB6KKs-^HFJejt6bsJ7
z?x5mRI$Zoz(Z3YDXNu1$C;MEXptbr7MF_1Gh7{K~!;4|XxqqN@L^1smL`D@$Tj7&~
zawEN)?2gLc=|si>CI7#&XQhWf3_2_S_#MPW$<TrvQmU4K99D8@*XXL;p9X)ADF4m`
zIjS7+h1<uJ$#kaEO&LT%vE$0Aw5@hm8fnSzq5Oe9P<2B2&>byLWhO1+yp&yU!cp&W
z%3PoM6LB9n(s4*%Wz2Q-o>qQLt1&-i2&DzjC?}qVU4LcM&)@|pC({}yP&w%dctOgY
zlr9TaI?_@!L|I5BXranCX-dv2FH?9mOv$47PPp=YdZI-r|NI>AbIP|V%N?mqRDnb(
zTkH!#qm`4qVJTLbzZh!blvSSs5w9Ftgw6!zZMwq~mABn6iX^3mzHO1L<e5QIlp$1I
zlB(=U21!%?7zh*T%A4WvDMKll4|t|>;x6E_lvg+)*~+3kbmk~8QK40?GV&#gGUX`?
z-7vy@rSSvw7AWshSxTW&N2R(Kl>LbS7Ac=3VJ?f6TN5$Q7nLu~hlvv9?^HZ-N%@8|
zT9=iT8-XiTcGH@>O!*<*)8$Iv6%eUVcD@G-mCAcUh*T*n4@1iprQaSpU|OwQbP|K9
zQO=8i`&X4yVu7et&g4RAo$?b(#9vbiz5uUY`6h*1t}AEL`{#yoXC-Flrm~w}m<`H6
z3gg{UhPOkcQQ4LN6HUrGZz#L1%sB!;vvMgHl6REr3L(;>w5}REhCiWI`4w&O+LYt;
zFmYG8i?WOz%A_2Kb}C!H#(dpZZcTxj2g<ieTbHu<50Hn-CZDY@kNv<twGOyGW%(yC
z->>|#0K6y4h(4GfP)?+J)Intem5V)9&UApzXUYJIA3s;ldkXSG`9C^AJEZ)?3tEPi
z^It;ei1OSSm>pHVAqLz*RYVCRN7dsuFo#a6mwtkS`&Gi%F);^Jv+b1SIH)>Fv+k@4
zsYlC2rEP$kLn<RJK@O|NQ_Y;K>e*~`9#Q#Ismf86j|`(erV`vj%T4tQt%Q%Oyl8cF
zN;Mn+yS}Q!uY#Ob4O0DzpDK(tglAOGw!t-jRTX7i0#wHtRN)Y)ils+ckZRYjXa%bt
zQgvR4O708up{lzEw9cxOoj`=CJZOy;u3Ekoya?6X2^hsWRp<zKkt!|if}&LK+=4UF
zD#HPg^C}KbK2C^H9b-Z=R<+_Cco?U8`FoIf)khBWiGT!E#cyaPs=Aa=nxy)T)(6R|
zpQtt=MfD3+p{1%$(ds@;HA2bqbX7_UL^4!-CI*wKI_C}(St`xzAla(Zbi?JSE^UDM
zT-Ef27+Ic5Piu#K)p>d>7pOF8kStPJ_*9rwtf~!0??u%{S|FFG-q;1DmsEQwWqDaO
zpQ<NHRU6DuQ>IF!1b(^dIV~S6RgqkXRH^bPymLkM31x$-Ri&jMHLBy;FmY9N$_bLS
zs(WM5s#Bes54W$Wq9}M$ui7fWSl+#^I{gt4H&h~8(ce@tC==hH`rhaLDR{mqtmte}
z6_fzcs`}{{m~T@Vp8{}KHG}f%_f*Z_z{7S`O%hCWsMr*7?o>_s7PEF=wS!7l9;iM|
z0k2CHPD6UA(uG0fk?QyHaJyUezZU51QEgiZXL?o1bae5t%9}3PKGm?Dl9c_b<q^>K
zMCDfwGN2lzbm*Xp*9@PYs>afd^GwB|fb4Ts{CxmksLbV1I;4_Q^kP^QwG6sPRO2WE
zKdQ1*z|B!zLD73B_2@ZB?pL=^_|94V*E#T9)N^SL52+Ws(baiaZKD{Bt9mcRxR0ni
z7$9zHk6Iv(tJB_wh`W04R)~127g5UJOZ{^dM7-6r=-V(S)lKxH`KWg^Lh_XQ!92{U
zuX<o1Oq^CP-VcL*>d8OA?KA2*lo9Y(zc~%?0QF!s?H~fxA5c6iNPXB7h+uWeZ%`AW
zerFV-q3VF8z@Jrj&_^S~)HCWZ!f<tF7<dut+w>AXr#?pIFp=she}fmL9*P2qR`35W
z(W`#=7nH@QgQ)-}R-G9S*W%Rs=EIqIbv$FjnC~YfsNY(F-b8gh9r8$0f3Y2{WcBVX
zXr-t>>xJ%A^)<?Nr>Qx0a5P<QrGQX|dT1pkC{sQDBuJK;)eNQCYWXy{mZ$DE0GF?R
z*~fh<F0#ceC@WH{=_^^q>R$_?<)WGq4cAK4JMMs7Qh#*`BA3;wB&aS`U!fOenR?4g
zkaG2RZ6Fou5+2}{>V0&ytx8=^;pZ!A)>2rnR!_IUY>j#%1s1QWw--Zat=gYf;C1S0
z_D}$?spp2Gc|-m4$7tPDSMed!px#4kmRssHs%L3be@joaCbh%o5V@_MdJ`s^)x}i&
ze@Fe#D2CLgzC;y>ch$j%VE3Ln%o8Hr>TwI9x<@^cA{xEw<d*>NSG!Wa^od$LgI=No
z>OwmGGN^vm3`<Yd;S>&jrgoWy){wfK;uOQ`4{4P$qW<A4030>%9>lPnG=cM=X1^wa
z(!B>X3x+@rYAQEFnX|@;JapIeFNPKm%?PDKPH5`sz?P?GgboCGX=*M~sMuRGk#f){
zHG6|#!bejz7r;}RrdF8n)ogncqNg>{6chK;tfu|x8I7Gbt^OJXofQty)X-c8X{2-^
z1Z%ce;5P`-%%rqysHTic49;pMcB2)h3HuY~&uR4jz(s1R3Mo_-rFkj?Gg>qF2%etT
z7-*tmH2bKMFjmt+rH65vv2?^UUb8Y2+7dLydf*c^x#8d?X<nX<R<h>n<q%2HtfY`&
zs^&{7rc2YD>VQw_8pU$h&C&?9kj&LwyoOeu=Il2h_I%B=N$4%m?D-4LLXGD`D7~Qh
z_-{-?k*11bO~slk%b@h4=Jp6AOEeoOgMLY4^oFCCHA^XFU#eM0>(w&Nfqk%BuF-x6
zK!xT_SBO+<thBkQ(j4Ca_!W)9f>yPr{W^Fxb`Ae`;OjIsksytlRo}zmCe4=DG5Xt@
z7AgQ})~r2<q21Bkqmrf;O>7rhZJKevfOl8JZH44LO)PoXt~t+!?hef&`l?H(<~AJ^
zyRT8ug5rTD&JBQvntdC=d!+e*R<_+5`|0Co_Gp$+z@t|)E(_)#YvRlR_GwzGp|oGK
z^dMY&qIt~|tpUwcT0;+NgnwaXo@vtPj(e`j7=)G=n%R!v4QZ08if&kA5@3WQnqy8-
zJ*vrZ1aZ&?Q;^kBJB>mNPTEqt75M$yRC?GR&`S5C_n`JCsugzDzWxYGU9^|>!Tm$p
zM|71P*3Jlpq^outeM-?yyOT;v-L)gb(CwkEegh*sq1{UdT|Bk%v_tdK22jM<TYH8I
z4o+!T)2EAkwP_R?Ijt>}QtgPJ_U@-(p3$x;0?=POlcp^|d*?d52-M2xrVP^dehxJu
zT33WuCxmL{0}wf@-4g<BVcIc203NQL@j1*#XsgD+(R14BoiGupHN`+nl(y_&Xo=Qt
z{}_Pt+USYU5~F>6C2i*7v_tfyh}RxGf!+kI+d8O8)D9en(j@IV+T)~X(_LXORXe@`
zUZiQG3ZX4sJNW`cGPK9yfXmb>sE#d5dw>k)Xjf1+C|8@^3}^DR5gN4ewVw2)ngVSl
zAFdT@n+{T{^n!K@o#VKqb^8KyaalWt?zmFzExOaow8tqnQLa5X1-wdaNFKCRX<wxp
z&nwzFjo@9?Dpi2jYMrRWr%qc-v6ySxE{gQkYdh&k=nbv13U+U5J?X4(gZ5<}v@~hG
z7lCKLt*u>y!8B`cP6XnPwva+@En4LTAX>FQeF#LGcJyC}-qVVMA=$3oK{ezZTIVM4
zI<>wO8o95{riJ+fZAURkmsU;}#6#^*J7MXOb}l88dbK-mK<8ua**a+H(+<)$sNb%A
zYdv&7(avcHb3nVF_AyVjU%Z03e5UoMQiJE(>Q5o^Lc2(Z&LQpU|3UYtc6<dS9dw-w
zKpb@|-bJUAZd3*D_v>Wz%s!x7;tTW6y5`vsanb!23UWv{WdM?gbw?=-;i|Jc#6$F$
z?(;yn=%%|t6_LkvbE(?IT_-MtjEBydGEFCRH+q2g)E%U>mzVCNMu_<64ke@WlrD(E
zAHKQ>`t48azNM&wpYG-ibo%QKodh62x004|fjVvwNU-h*ot+EOt+zM8Zm2HV9g}}n
zH?R@r!*sSLs0r6iUku(k-E2D86RF$yDhx*H-lBJ7wC)a7jGot3@_>ucZKlV2oGzYT
zb@4hbDNE4JpiO$B&PH{2NxJ-Uv{H3H{Ek^q)6H88E$KS<#S}cs&~Zs7Q@4mhUs<~K
zWH(#a7X%k`bS<eMxw;xE@yXNaAA^^#dv`2+D$tF@z^6i;D`oI6=vb$qyGZAs1xv-c
zWFB}Ibvx*UW{GY$Rr*}k<yXM%Qr(xI!Cslpd--@Bu5R5S+6q_bvgx!?r7kiW%qrb`
zp1@zxv8iaQTF0PBNsVrID$HNiZKqIbt*+)LD6P}A(u(n#j^Xp&+hb?jyT1gWLHCjp
zmTu|ZSqIXnOQhP?+q!iWT5Q&xDFL~ole`aJi_VKu9<93HUWU##-S`_YbXRv`J$UzY
zhba!wuIs0gqz>KZV?a7}N2svrzAl}T1rKzNVE}aLKI_F89_pUjYtj2i7dsQATlWFI
z{d;uz-$Tt~-JC}N_UV47*Ga$b&6VH{>bz;=^i;R!3I_j7H$>kEc&;0!*U1ar$Mhf`
z(rx+<102>({}sFu-JA3p8rA(oPYnls3Kilz>J!$$ypulpoE?b$`W1AK9ng<ZiQPec
z%Nyu))~~1f1sDB_6qrAxpX&|YVf~6taNkv5^$e46ME@sMyC2naR-<)H?_LC)oBmzO
zRv*{PXdC3N@1imU5B)NVf1l7Vr?-NqzIYW}^U_Dg&;!+5f4B$DlX{;fX!FsVmIHrE
zpOgk|zWNTz)SlLR&?hqe^y}#BJ!kYSW_aPRk9--r1N1v-qZg=e?*kx6f8;qxsD2Z@
zi_hwtC~g?0zd9G*hwBR{z7wH;_zAR}(=WY1pM8tehtMSur5~d8ZnWN~1FaanH$A*!
z_2~&9ae5=|8Its`orc|H{UiEPNQ!<DZNyXcRYUM1O|M!CgX#Lh3h*-Y3W_~t>a{LV
zmZcxag28P4Ou9UB^nb~qELY$2101#I=~w*?X1@N@vtSnJFVaJ#Q2&<+tqc14JrFI@
z>scVhdUF*_T-0~dnyEy8U=r|`^k35zbXh;v3#3$^*AK}ueH~qa<$C9AXsOV<Uj?92
zKQkV#Rq2C21MiAnN+tBwcKyg$$kgb!|A6LI{Ue&aT74hAxa#ypv?#r%&u{^$*H55r
z{dN6J3hm#}r?8;yroJT<tp@!kJAu2UU%v*!Zq#?u<=mt{HU=WM^)J(&xmjN$0Pl`|
zBc&r-^e3o3xK(d=8w20k^!vua#9jTjuR-RXe%~tqw(D!Yg=mL<X(n2o`Y%soX!rFe
zC_eN+KjRZfcIkT_g7;9L8-OuA(kIgEpj+>>00w*X*#l_x>YHoPdaO^U#Y&$(j=sOq
zuaABJf1l_*?6W`z^s8x8HmDacVeq+rJe8@u(90=wJft^=gAD681;NCKKAp;2M)hCM
zhf)VahX*<x4PmWN>SUPrK0MrSm`nNI1BUzbU^-}6@)U4q!{N<v+r_|hg5)8?H<U6w
zY*>&@4^&sf+VN-}F(ljq;;5m7KErd&knsq_&7h!*?YLpt2B>j2OuGgTJq&FW-9BMh
zOHXM}L%?nf!po2mff0He{Qs-=GHB>M;$!fk4;-8_gigkgd<`q}VCb}A^IS;!8}dyQ
zQwcIGl%O}*@PL9xA%=yi&>d>nOAnK?hTngLPhp17JwU<@I(qm;7@{d0e$G(P4HJ<D
z(*(ey44?c75^ZRf!Qb<S8oGUB48F;5JJ#SZ6^_Ok{#1j+8~m=qLW1F|kukXc5)A?&
zWReX3(7rL*kWWe36vGP>WKs>o)6kh_sC9#D=?1MBof(FX+pwEySo$+MvkcQ{GnsA3
zy#t?e3<oGAnrm>N@O_?P-Bonv8#*bvTwt)#Dz?xd^oN!UhTbah>_vt-RA*IesH=t2
zi-sh6%9j}Ce+o}88REWz%w@ye&j2hn?0yVK%M9-_G0<{DFI72L7~Tp5pwiHtfqAYn
zB*{Ro7`|Eq*QyOG|AA{YhDHAXaMf^>(mAz;_uq$>Izt!T9M|jyJFV>N4VxtZUN_Xz
zQHvXfnPI@+H1zP{X@lWwI=9zsSTzv_TMT9j7quE(kAc@_xJCETUBjkIXt`&o8V?ig
zhCEvTbr?c)7+I%5Iu_)<VNeCh9>ZVB@b|G{HC_09275Gp_psk^meOB?h8z!=cxou5
zi0(6k3oRv{8}4p|`4@&yoFOt~=%>u>uz?u>-iYCc^&q2$8T8C{Fv^X9I~xC`Lv>EZ
z&jvyE8|To|_JFbK0fuzYxH=nNI2)NaKwOOZb_XauWUQdw`eEbGw6AbAj%8qIM~vGj
zIegSOhH6`n8T)8`;$|GBx|HL_%Bj%pZhS<qdk<sUU62#T>;D7X)A$?ZZ@rA`>(S|L
z4BQPZCymQq$9R2=b_L+4jLuwG@HL+7qS~+1#xXQBKjX3=;M5u8{TLYZH#&?5KESx3
z5tagtvjzYRG9Fxm&S0bFUyu;v^KIx1H3t5-y)ZHiXoVT=F__VC;~A>|i7-}7LgzW7
zgA%GEjo(p;ca)L)Gf1>?`y9Ie&KpnCA&D3xYcZUOH7+{<5@%e%gHQ3sKTZLkU_8u5
zXQHvW5lWMcQB*yZY%ECtFU9!bSKy@@7v_SOW~>|lF5PHa0WUI)1NmrW8pqL#FU#ml
zLEBv8Viic9al_wq7$o1gL<ltnMqjF@E;I(XVDuM^>!`-H$heud%f-g3Um$YPxZyBH
zQDTgbhR7vj6{Sfo8y!a=Qfi#K5nhxTH?P9b%8l2kYQDm_IS1w|jnVJH-zwvl4*|bo
zY@=4S@jQK#!(L-drLE~zqbvZ;T4VbAK-3u>src%eF|8PC>Ww=aL9QFGm|^gSG2<9`
zH;tQvp{BvuRtodCjMeuc(rBDTrO!>qu+^B0+s5$A5NS51njmt=$e_nYi!q#18Lh_U
znXuPpH}0iZN4s%5AHH=MPkjKHPUDidz`SofG6j?Hz_^qub-RooQ-blKF`p{f9vMGh
z36XB&ydum+k1_ZPTD``sooGEaPWu*;ea0>-Wa&4aJq-90qx5g^28<s*!UPQ(Z^S^$
zQ=@(BRERz^7LljVjY$+&eqp>rQL7>2NCK1&8$arV7bC`gEhI;c@6hVk!L*a=cpObN
z5$JR>N!~|mzo{b_x(}G<Ooy_ArW4)J;%pi@054oj(TC7^$dsNAa@h3aW*Blc@$7*>
z95LOd(vqX5vO`dF%%r1eq?@VwbF_||R`tQ4yD8%+EP0ru6c9LJVjlp&)AZ&G==L(@
z4&sOLHqDX(chdCd2qaILgp>;LH7#ETk<+GD6?lFo2ijVmF};xi;%_ny*r6@J^u~HH
z15K0Tfe12fq?~K8skRE8A*OiRg@&4{6VZ9rwCXbEGR)Kv4uj#Qif=(8Otv^^IcEye
zK_t@jl%AdEO$PcpT8!zK4=lx+_`&cu&Sahmk$96YmAEFD-YupNIwYD{zhZ<*rYU}q
zNj7aDe46Q^2Y~6OC83z043p#<#*}TE^${%Pm@28*I@dJmP4MzeTDp+)O{;%JtH88{
z=CIJTnxd{3Oe=H1D>D7~3UI}yE(t^~npnSpl$iKlQ*i%XGP%-o{jy2%5kyN(SN&kO
z%ybg(hY95-=O);#FwOZA1FbY&%touqH1SJFUNMDE0j}EgJ-u6NOeJOju9}`OVYk*)
z_ZY1@lMmgL*GzUwan+kX5JU31ssA@9yJ32pJ|$wmX?hq5nFdqq7a+GxQ>iq#(PW@1
zk|xt`+NRt#U88MWv*{oUh&!eSN{|-Q#3NAJYMRBxthJeDZv(k&3fl?5JrjQm;O(Zd
z<I(Cc-K09WPSejc&ikf@g^+w;V$-(?y6mRUHlz8_lt`a&cw|~cVTEo}9uEe4ObeAD
zy{0&N!aO#~m>71SDg1p%_L~fcF&9rv&*%j*U^-4&qCwNon_%~;Nx1^JXQsOp4t#Fv
zqiV|+rXy>>8#2YxMLKK>q^#kH$zDrau2B=03LzZKhIVM%Z=P2J-~sa|F(3!c`z^pb
zoByyv(#3pEg4QAP-MjGOu=y=Y!MK`Nr(wE}n8(uM@TmDuItF#jeB(3t<YwOU6s_at
zG+Jc2n=|{N#lt-RC?rpqkK3n$>1qBw97?^+FTVpd-sb!v$ec7Eq9vb?`A>QloiZoV
zR?XKO?}pZC^DGMV_?eG8q4SLS;&|Zv&B?TK3ot+5k3j^QQ{@l|GXFwH1%u5u*Fz-4
zY#jrgq2{pPVg9UnY7!|8Gk11EX}CF>vNaLr3R=pXGw&DzBGT+>2k*T3w^KmGn4fOK
z%*LAgLO|lo>nNKRZ(i#Okpy$pEQ~PGJjEX-lFU(MXeFCj(=iFD=8cZ%Of!r3z_oPq
zW&v;+W>?V^+<%$oo?F0Yo1aZUZ;p9wHW0by$Mj&$GrNBcUcUL)BmfJ{dnnvgWafMa
zkz(`g94NhL-by*h60_L@txM)FsZi^(`DZG%C^dUfyr;}uC4#@@<}tLAsW3NErCz1k
z^JA)xs4@qB0pJz$Yf(^BZ9YE+h#GU+J>ajJ57husYraU|5UMjPN%ETcGy0B9z1dDV
z$m`~Jsf_l9xo`}W-ZZbEgTf8wT^zJ-nZL+}zm4W>HN0;!?^%M*+vZzC(AjL>yA_7)
zcg$0$jHJ~(e=O9rnJ?}IX*X-bp}WKUI~5sqn!maT{C)GHB>+A!v%H|D%e>-S;2)ZQ
zeh;lj=B<sub(<wG0nlUqo_4Rj=5@Ys`>|Qj24zpo>U4+<m_IIuvO)7fx^JJ_&0oI{
z{4?_f8rpNS&tLcrUYO_kLHCgPER}i;n}486>JjtTf5OpGGlxP-4wmulAWoLf*I{tK
z<(CRf-T})?!w@-W@!JMV&XyDVV8X@1J^>5vmTD!4hb5Vc)=pToTOs0Uu|H0NK`+bq
z1u*Yz5xxthr!31U>FR4Kx)1zmi{>xr_Otx(0=zSpQ#MHYTbd~)8DR0CbbX*DmQG;>
zS+-M3G1#)0!Z#t7Rh?*sTAp5pma~?!Fz5`kJn2GbxaBj-$i!Qk?Ub5Nuy~IHBFWNv
z2ZKqr<kRVj6w6}TOQ%{Uz6ZN$mdsZ{(k=0yLNdeh*;`PWY5BVoqsX$fmP0bzGIt+D
zaxBL#!I@l3w*Vq}mPv0zXTD_>6^|8I*c5~<wA}eGZDBcIOR1nDOF%KaDYgh`DRR-0
z^(WMnSo$aue#v4XyO%9l3E-7lG7bS>X7P;#uiUc88Fniyhu(zlN(++`xmA`mw4uLZ
zky9?E+F~U~Yb>+Jz>BMvt@O~XwRDz(S7+(|cr5O}YnH9#O}(Y$Z7{D}o_-3^8<ufY
zesa^YegL8kmiH;Z+hl2?)!l82y&j#-mW4k9aL2ONAJf%h+2#h<S}kpFfV5e@%R}c~
zOXdMMbI%h0FFM;Tiw<FCIxHn+;B{KQKzhhN;l5=nAIt|9=LhKRvb;()9uF-qQyJnT
zi+>ypc3X^8vDjmAqO4`F#cvK=du(x^i>tHG(s2l#{g$+5z@J#oMF2NonN7R>K}*Wt
z;61h6`UqY;vs`-%fajJKS25fdmg%&Gun$>;t}s7rnfEf7BbFz$hZwb7S_z<owenLq
z>}V}HftHgsX&*%PTeJTL@PL&~QSO7*mnk0ZY;91%Ll^72R8Qe*eY+NeIAR?`mD@+H
z+v%fj$E@eWfpfF^(WC#kb@pEnakpD{N5G(m^)y9MPgwc1f%CLVDYENj{rxL+dRzaw
z58z4bO)~Fe%^V98r>uiiwBT#q{WS)2+B%X0o}cyN0+2J-U+A~@w>HoUEWrBaVn_yB
zS5d+*$SU|RH*H<*053wU_D_~TTd38X0^nKem>wX)tS2d29d7+M4R#}}Q`cd-&sja`
zTx+Ct&I_oCvhLdqk!Y*mm*_li)!#%b#(I_>p|RG#XW}=AvwB8Cb-a~P0`m#h1C*pn
zv?fwPP?9x>76|xUlsyMD#k!V4VyV^z3!o;=`UCwdfOM-{2RbvXUbJh-v@Ur9e3rGb
z46STy-Zr?FV@;>Q<XV5VVb=1jnN%yAZw*|HDJih7u>eqL?R^L4FIaEW^0&yEO7F&E
zYx+27xoCa<4JC9-tOf62OqZ-Hsj%U)^<FqcORXznp{>mNj|RHSttL80Rbf3#i|H%Y
z$rOpZYMtT$6SdYUufvNv>${Zuxn|90!(hENCIULITgOqB_l9*M9ZkMzUDSnEgLUgp
zSh!`~x16e?8m-BFn8YUQKfRE-ZLOe(NwYPA3JmU8&ru~&i}kl-aIMv9Tm{KC>t2cy
z+_ifD0B!fILYmoj>$X|&qQe^SJIr@lcW(gTzIFL|kO$TnT8MR7Q~luKLu)OqYaUsT
z<x>2!+d6@6pdRZ#0$A#`Ce47%W9yoi;9{S(jUGGw)-Cn0^u+pCDOv;8T8d#0TF13P
z=~L^^F9H6{8aofX=hm4M;LHo_;tLQNvd(%7T86FnQ@|Us?rQ>I)OwzFs1CNnR54|D
zw0S*%-%hrO6&TY&+gU1oa<+Z*0f>uj&w3yZ*}km@@32jK7R1#yAVTLco6`V9+-#l{
zc|2~j_knl9_Qx!k_q4t74q9He%im!}y=}YVA$iiaZX6_iY;I}bowl9b2G{)THs^_8
zp0Q1!$A`ad;yN$`Y)dR4fwmQMfe5m_O8bjon*%K;Lu|p6rwO%vM)&4f+iebp7H0Ej
zLL}U_i%OFtY~~WQ&e=E=@{hD#p<3H0TZJCOj<$Vw9Xik3D(L7!jLrU_2l!Z9Cq294
zY>gM8JKnab9jyf0fjQ8YXj|j}l4ScK9>8SVq_03yYy}_SXHK=P$8R_x%{Cz!+R|;U
z6rjqmN!CIn)ArwggUqt|P|Q5r7EJ5F9NS0q!pyZzo`KFho80~Yh<w|!9*_dtKLH?x
zwnZ9{3$|VKFe$Qi`a^fIP2q>mi#Ap@Tr05+^`P^TZ5};XFWX)#gYHtBvlgVx#{Dk@
zV3Sc~slxU}9srfLy>vTN*(TSbb;VZO0a9&y;~w3AHMa0bFt6H%|A2{FTONH}sLnPa
z2SdAN6NI9(-gc%NBG+wy-URQ4t(AhvH*J5k0^VSod>zi*vhASzzR|YK8E!Y*#?uEv
z?%33m;bDvIcNTE1w#iha(Pr~IflKbLZKR&=zk9a2S1=jvwov*hI&2q6cc*PKeRAu*
zjZcx*2R8GsKy=w!X`lVjwr~fuJ+ie$L0h*iD+rxEwu@A+)@$=O!I{T4>jjWLTmO4d
z-EWJ{LhFg`Upl)zVDqKi+@Njq$8`4YsZEuHp*^#`;RW*CmP3Kh7q$nF0UWXww?K5*
zHbNKc|2ewuxU8%1uNGOFrD;R6ZJM)THqEbDT9#Jov-jTnAuTH(0YOlZDH}m#Dj)(X
z8yNzMC?IY`0YQdr6_NFOpWk2Sb<REO-skhV<D7Fp&-k`+U$jkZ+wKI;-3+8lusAUW
zUxdG|jAF{8xiNC+K(dG7M9YFZW1tsyJs30SoV=GY(F$drjA43^ycns=AuxR(!<Rn9
zvY%1#e#md1PM(K9um<YKkljG1{2B9Nfdw$$nh&jkj8`d25yY54eBS9GBXAtVU`F*h
zaE37IsIE4Yu~-SiVT|wSWDw5CdlqdGj7fBpD3YO|1uTl8TLSD5<HHBQq8ZPwg;Oz%
zrv)G$X3TJ;Kq8ircnE5aFy>zbPXZ&0A{mK{K03B1F}!KNe~b}v9BnBKDcw#?WymwZ
zlFnF9tN01V5sD9FFn9|v-kFRUbg0Z?{6MqUNyegDc%RKUF@RCXVU%-#<uYQZjw_F`
ztd0Wm`HXnV%@i;yX|q?zSn)hMQ^eRrDgHBzQkqMP8Gln$r-bn=1?x*0tP!XwW4uTC
zp0f-UooUM%XIjx#!PrU>-b%(#RMC2lk<kOy=NU`O(3dKPjh>bZj6zD5RWrVNpDKJV
zGCrcU{Ssr~S2Wfza{AG=TE-6)h^%95c^O_@W=y8gV?E<iJ=(4?MxyXjTxGmN(VT0H
z7-zIyX9PS2@dm^H8wlKFe18jVw-{&0(FR64Rk`2BuZ6ZoMu{`P9YzlxA&1jl1}7ek
zEsVKG;r>0wB3cJq8Rie6w2k5a8^C==Ry5piXWX0v&JKnb55!J}nSAPE{7ebJ2Mh<z
zP~D86y#PIoi<4oumy!7k1o{{$)o`t!aXk`t2N+AOFf_>cbOSgY4;jzVx%UynNR5vf
zLJHLmF+TqXN}n*MP;PUWQAtItPZ`&aqiuu{V#1J)GJKvw%@||mR_GpQJbfK*yD;Cm
z4^CI+uMGfhOxr4`_Fx|Af-`%Wo!>*JCv#dH1iYAGpF;IM2lHFX(eGzo8iRRnCZ9Gj
zKFp7)O6vgAZzg~*^Y}1`e#|+P<nw1vc@1_0n0u)FI*|E`3w#P<jxB|ygUrzz;0$KI
zzaPX9=D<Gyp-dk-^Mo<ai2%Zxo!zh(#gtNp^bpfg6bPl!%tcg-6vO<O&SQs}z6R)y
zWp0^+jvir_)5$N6`5E2Bjb|pG1WN+*&xPn=B6CjzoJnGCrynhuss9+nqs*6=L;M(X
zEEFJxSwlO{ROW9hVJMB+kp-Q{nJCM}`@@{?SPvIZFh?kklfg7oSxP2TONCrnOs)%f
zPBPgiAb5&7m8PH5OvNZzvY9KBLCj$urV8R*ri3EtdCUe%dgU`8P?c^0^Ydu16f)EA
z!nGpi`;=rm!+g&GmSX03Fo-40DSlMpQ_B3;2sLHQuwiucEOQOrV=HGSZ-%7`=13W^
zN@fpbz|S#LTA=$pb3OxY)y$O?zO7--E`!oqrt)ieSjW6av;Ae}MlIy(nH8I1;R<t&
z6~wE|_o&kI8gs_GAYNyV^wMR}8_a+o(b&LjrZ?_3^TUtfMI%!|S=2ksFWv?5E>lRs
ziYDf5%BeOp&ojW%!sN(7yvNKQ!4K2QoI}Uvc4i7KJsnIB+QD@)rJEtp&5T?L(8GK=
z1pf9i8);@4V44w#cQ_3)x4jKZ51I9A!861Rq^nR*n6JMAHN(vJ9${ohnU5>cHpWb+
zfYCT}svVYGSivHwab=zKg)?rf*YDG_&a&LZQ0`@!_hNuNS(gHU?PpD=W3M->rURTl
ztbaCv(~nga4J{6T*6;ISFo0zqN8>@(uWy4jn6=<d=ni3Rq}eu{HQkQ32v)@)v_-O3
zQK?!qYq%K17}h6$Lf|m#wJqR`V@;tnb3BVd$?61F>5J$@GV7HFU`JW+(4P7jYx+m%
zL>kL=3dZ8NgVhlNZ_-&YJ{W{d)}Q~tsVvq_x>j?N<+==l*(?*?%gSN7tOUqq9eV`9
z0@hFef9z&0qDrVD*8O-mQ^G1Z3EicvAgc8$W0g>{tb$cWk@QNIPYj$n$BLw6*9F!L
z`YVPjEXQF=?ObI!(=30D^$e9nTxZ$#LhuIbDn*DJSQAXxz0E48&{iYsjX((8VFgoC
z<Swh=OPFtBJ=+A(%&MmVObe@z?z-G#?a7CDD{F@<%(t;V*az%Bi@yfq9jvk%V4bXm
z4m()8SP2_o_W>)*4yE0!SN+lLURDl$8oiITnTj|1SrL`cJ;2)C0)atRD%B-EWUW~U
zxgl1O7T^hs^8`wVS)QH{A7#az2Im-Si3$eCS)vcniQVjV*C6M@-uW?na%HFMDInp-
zuKNy+d)OsEq1zs8F<k@N%l?ZNdQbLZx<u&3{w^EZ_OWlQhv0s;k>XC?>}SH@uMazO
z5yTI$S5wWSFFS(@ef-#kU%?B1_652N7{C^-g`q(9LLuaW*yYnfJjgz9f7(1eY;3nU
zNQAJn)i58*Hc_TCjD0Pn|7%nr&%O<V(d<RB=wU2-@)IaM!d^h%5Q<~(Tng6`*}wh*
z-AQcDA#^mE{em;ZQ`la^XiH`LFGpX}*#A)x`3ZK-FK{%2{W5J%Gub~-2JIAktQm5r
z*{6PjmTdMpnr`yg=~QZ&&))8cgG2$ls~$XO*h5sORLl-$!<iCxh$}jCmK{a0yK?q8
zz3CNf{$+4hvY%dq7w6blUjp$w+e$BN75fbvlwDv4&^ukt{_6-VU1T4pYS2sU$Lpc2
zhW!r@UevKS(s}nXyD^vow)N~0iWFU8b7uiuWiRJ~^&0ynH3YA-_j!T!CVQAl_iwR}
zJ_q>*c90NW+-85C0K1Ls6pGf}VH@cnc9+ed++-7bd>x!=W`CCh3oY!oJ0Wn7{Tg+*
zm7U=S(9SM;mkM?|*e*Pn=wz4k(d};bJG3|MVW;+h*vsyw3j99yRRwhSvo|aQ7+^mz
z!kIyK(PFSXWdA)0CLXa1egp9_JDX~AhS)bKCj5lGj23`lwva01p0f2;U?c4L&%^vE
zJN6k$SdOt7sc?Usowo;If<2SUcXo5;DbNcSPU<}XSI$A2lH52UbI`Vjvzg8b?ws>f
zR^q{V_7$}4<!EO^sVAqg4lG`r9SVSboc#6R+|T(w3|hQ7bGO3_A5I+Q<_~aUXc=?(
za>jzu=*RJ>gKz$vJ+A=-a1OOWX&^`11fC$y%o0c(<cw3TN-*ceV^9;qIr|1!LOC0r
zfr&8AqPOr<gmbQEz-|P`M3KBmPCS+NL~+i>Vq^|+=1_7yn&UxlY7D0#4Q3BJIJFzm
zi&&28FDO02>AVANah&3lz~VVh$AKkq=33!JBFDM}CXzUOnx~RE-)+OFALRs!VelBo
zjZP~moX92+Q#n?;9h1gsDun9eoWH5CFP#%XEBgt~t}mb^gL7sG0+}3CAOg+e<oH3&
zY0kfa=u<Z5zg+-1oTta2CYSR%O|yBNqO)*6pEF(vZ3UdN=b*cg^FP{_6>)s&#XH0K
z;ygHuIiBwDw}kUWA#|2<KBdrK8E3@{U^&Z4J_9Y~oP<FTD>!EzRMJ$*@uY~)IZoem
z&~}~^@Bsv?ICh%)FL2n~z*^1uFB9M*r}i3%mpI!M;H=?f2%)r=6XFGdI!+V)l9xI0
zThO(7PCXs6u5b(#%eu;$LfOP?oDGwKUFWQ)=i&w@?hC33y2)`}0d2Q9Llntx;H>`>
zmTq${_`s*Toc=$-(!}Xo4VGrk;%IcOg;OyOmV2Dju`tof2|EK~8|O_*#@y!=QV6b{
zGiesuIyg~o;Oyk=jRUcZQ%n!{15VZ-FyGBNIPnbLzaCB_Eu6g^J7rV)I4{yN*w4v0
z0M-G{zg+k|$az3{&xf4o9Q6JXr}H3Od(3&@34tL_SUc=K;TZaW4Rc<hMCnsb+^+y5
zoR{qw?orMx5#+`=E7w8iIHznOzyzlr#XJtD-Q4%+$8+I+69T7Pxk2=!yKzr4A+d)$
zXBy<)xxZ2Mf(JLZ6TR5WjiJjfp4{gs8tcV<D+Jg+?nVv7_j7k%g19%gu@C}2+*hMu
z=>Rv0Dgu4E+t-8W$Bo;D?)r1zq(rnMfSdRbJb~PiAJC^D?%%kh;dGFzryH-q+&Mp@
zErdIbVuqpINf~f7j2r(A#v+_MO#u%hxFb|I5XoH|025K%#R}*?#9cvwn`o|SCpcrc
zZB(Ltm|OQJbjEV+3}8pN2AZzo9NfRA1IBX`17RY8yLkxO61k^lL(NgHtQ+#jxC5&}
zOyT}YAF@Br{c|R|ozC6368@gx_R!`qoBQH1u;g*SSpY5h+<eNS6mTz;0u*wM6m>4*
zwo}^~uJjYQUCiA>0pb$w*Rjh0OSzd>q4X@*OvP>G+#8qRVg>gPDj2Bb{`VY+=eP?V
zV7$(A=QF^0fg2I>$@f@3C)$A3aAoQ6x0d^-1)z>QXAK;^%pKm3p4D?Fc7k|?8}>7F
zUgf^v1A%MY-zcqpox5x?EZpD<=ED1%T*X1O-QospMXwvU<@7P&+uWKqV2xY{)xF)}
zhKB;X%S}E8olRVo<1~C~=C;yL*}{!o2l;#4Jo=ehx!Y)a)W%&%2gdu{1F;Zn=dSPv
zX9u^BPDc;8J18^S&HW+;oITtrjR3t|c`97%<8Gx;azFRbbNJB)xVI?THOTd!iY`6m
zZdncDBkuZI2dIy^Y(6B0xGpclsVCeos6=&``vN6@o^p?T35gNzkFSF`%Kf_+#4)aK
zAS{h@i@gCRxF3=DZr<)cV9<?siqaQ*cyUIUaOWMSW!r<dcMjV2@>HF$;K}Qt)!U0#
z`vNVW`*`=M;B7xIa|JAU^Da_~#D}+d2EYN{>r^7(%j-mKj*}nnbt<gz=M~R~d;o9Z
zBnSlZ!X*$7;;q~W-3NIu&|yEAS4VF{2=9mna-qC6-$5XZ_a;4S;k>H}&>6w&!td&E
zisaSMAF4$0s_7?*;hjGOzYp{NrX?emw~EqZ@jTr>013QZ8^Dst^UKDseUvvl4J^la
zU#p=lg%|q(x{vcN-vTk6*H2dsPVoLa0uQrz)d3JV$y<<u(LTk?9EZJZ-k&pJ$dSWK
zcop)wyqK*pk;nU%jsp3-3-kmQ@|Jvrwjy2u-9$daOQo9B65b1KkT2yurejzcZ$ACL
zXL-{o5?9V^q+hF&H|-X%bG!yRHlF7#kA~d~yjfCU)x7&lA$O6dxDRm2!TWm~l-BT;
zHN)XL-k~9|UgpiA6k|Pa@;zv~!jn^x%2l3%V!GFOxf?;e$;%Q$;1=(>f8bgJ?-x2%
z-R5m1yN$dJ{{Y<K?V&TrT^{cYexD{@{Tt|DGmk?vcqgxSCIq^8j_?}52Rsi-3v}}i
z^+B+QhsXh*VBXg=;95Vga6YgBo@*{T`jEFN9P&dvpFL=M!t0~Oc$oL>2N<WPyxuct
z8{y5&McXLv5}nJ(FhDRr&Xar$e<yfWDm&QC@1$qVg<s>C2MJgHbskU;ek-j?d-;Lu
zLG<MJ(PQGpe{B@n_VL#S(L>6AmUf!n{AEM1>%*69gWLiBYO3xJ<a>Vr5X67>Ep+rC
ze+N~|2lHiJ5D4MBH$i78pFtP5!}wivRte{i{YwRY5&RB18^-V-Q6&B_|M#x|V)@rg
zVD||B9<8)-{Jpi%9naU$o0GujHNiw8f2IZ?iT_(GET!`2Rm0yj{&Y$V9p~#Q)sW8j
zSO@bb_~o=G&EPlE9l1=t`vu5l@lUnW@_CYfaViXE^M|HGcMd<c4vo3|O*t@_$9MS}
zYV!G)K7*P9KJ#}F3;FNw2WJuAa17ec@N4ctpqStO8MKt}@4Sz;QvThiAXf4hy$f)T
z|22Jt>pZ{t1YE1)?|TW|y}<9)(e|~PpGQ;EMZPx`8eHOsz6_-`{I<)`c7@Md3T;>U
z7780(<M&Vq?K;2hIrR4ipV<$kH~H)~$lc;|>M^nn{M#2{;x>OLrM{Z^GdI9e3txN=
z%I@*=eW9$CFRTG*<EL!}aNOrhsSK{2zf2C$!GE_KCOY|vl(_HZyAZLDKe7W@KR-MX
zmInCWeFM9L{E=a}{g7{?J?$g@2V21Tn9p4TFvPzf0E18Y3tj>?!oQmdpGNuFw2vF(
zo4$s!aXy0rViOMjt&7mMTfm^Gq>EsTwoa}BIVIrS1dGJby+<ISAgsF}nd<HK35FAa
z?H2^KLe5*Dpi`ueU{Ms>4hTvIVbE7#rOD4v@NqEw^%qRLhp`9{1bhdBAp-AAbURca
zpvfyt;0T~Pqi{hBRU1YK-lTHuNP!d08&QHZIs+UMG}B$xXo2kq^de3WNsnH<;1hcE
z5(FlC^b!U66naY%Jl_oQWI?e4;HV(^4zwH-ET?HFMR2Db%1#I*CU}t{Fj2W|reN4H
z0BV+?n8E`m1qUWz>6G9XicXvsd@q2SY(b+pbms_Worb}D!O2X>7YOF}11l6vqfLL2
zU}X;k&Il&QLA+S-t}m382$*!au2hgiUrH?#>@7oo&k9tO%r6%_r9fJR;J_c7051r(
zQaqws5YPxU7X|T`FhZ9EMkOrO2)?L+rCLE7<#6i+cjYi~SumvpO0Nr^(E4{nuw@@u
zZVG}!c5j?KNATwpV2y%Fv;n&#_ykD}r+b25C_daOnDib%o8XruShz1(@-aZW;Q7<g
z(jmyB`iM@!qY8+32^u#8^a;*W<ww6jPEpJO!P_Byu;2*tfV+<c;j~Q{60D}L?mrd$
zMM0bqf!pT*qk<?3QH%*DQ*drvAl!&<P6&RdBjH}*lmpP|DcqR`aWA2j;{N-Ds=opD
z3!|DK?k(J928)ldpO%3GLc<+!`U<&;Fytq^>$nBfUnrr<tpMSUaJUvIT$Y9L2@<Zq
z3BiNH)p1Z0B7B+F(oms}s*1yeRTRPv7jCgZJVF>v4|SBV>M_I*3Helo7A=&%1kS_4
zGiRVBR(M4QokxU|C<GfPjG)s@yfEZtnlqDx&%6WO$-<r8Xgn$mr<MJfFxCX6DZ*qA
z5L1OO(dH~oxPms_$A$koLoQv&S%6+-2&d96FjHvy4<JkE{}JR)3OCc~{*-WFIlyV*
z<A>-(j_@xHSaO978^rU3Yh0;DD_`iYgYE)hJAD+ZP<ZJFjB}CjTn&6WBRqKnZN<Wy
zejt_z*HBGosqjZyc*=z9j>5IGLT`Fv%Z1%EF;xhU(W+1>{GP(4=Y&CYc0DirlOpX^
z!lNx<xghL44VG$Q^yf5ZUKBR1hVDy3=N{;;5i03-x-49O119Q)eU!VoBAhoLZC8Z{
ze1KgO#&x0Xy3q9%^x~%Q)grXr5>|AgqYXmuF@W2`@b_S_QCPej;Eu4Gw!%%qt8_$a
z7Jjt^EG@!w_kcNCg+0O0)+UVRgL+@MBM#2A3pE|k-61@giMCGRodEQrOSo|rSh|Jp
zPDfjhP||?T^a}r_+tq!--)Ls&7Y_almO<fX+0gP(D4q-ONcgM}UOX0Fd>sadgiq+V
ze<JLii$NH12t7W4;Hc1ZCj`fY?KBAE!XY}AObCy9LVmZ%`%_>pqQyRN##Qt)C8yj(
zRc$c8M-)wKn!D&y4B9+IuhOR(_KJk_AmAx_OoQ(w%2$GApJ*?IOZSVup|#XoH1$XL
z<RfzI=!M_`(Oin<_=*B4JM1U=h_;yiqWCWX0z~O5s0kD;*a?S&L<21_aZvR4uP_lT
zx)lSZA)=4p2QgGs{{IO=(Y8m>9WMH=1Rz4>H5HtZqCvU<8YP;)2H=pWe?R1+MdJ>t
z6^Rk)zQ&jw7HtiHiC9tBMqo!oUbOJUiRRG58ZWBY1V<A@Oo}8Yikf}`=TXtsxez}l
z+C-<Y6w!35CrlNk_&|4>sG82M$3<SV!I>@+ZbDy9h=vY8ONMCGT=<kJx;SY)bZ3bk
z{07#Oq7MhqcuM3=S?$xJDhiHgi{?^NJV$iRf?>-QvD%<5Pn5m}2J=NfwL?vTNF8$K
zH%w(e(yvu4+WR?lmWaZs$f8t~K-FhuqQ?|JI4k-h6|R+wK8XaeLgYnPfh$Gl--g+9
zqR%JLc3w0=lVz1?9nH}fL>Vi<QY~s)40|=Ak5>WIiqy0_sS~|V|15D?^v?`{deI%n
zCa_)+MV10w75zY2(rcpdd$4p}v}7}QZiw{HfOu0Re-&eROSFpe1r4H|R0wffq^DWE
zQ6!-N=^fEz+WFiSeHRV4n?%o38Go}#u^j>}qEBdFa8L9)J#ww0mVZHP6U}jQfc3uU
zmqPTuQ}k61urARKs&IKA>RSq)ZqbkL!HXWzU0P!LM7vf)zF+jsBv={{eM;A921Pq3
z(8GtK7kbe4NYwBZv<!*9eFX6*qBYOL!(mZXH&~vES}BY$BC?x792NC0ps8$Jv>*hH
z6QW3p67Lqj;t${|Ud@6}ZsL!A0JcY5ycUA);wrjw<{|zs6!M<p?PmeJ#MSxmcc1v~
z_ZWozVjrry@fN#&3E(4MasuMM;#VnQ>?fZ334HPw56=QIK>Q&Vdxuk?IC>H+1&Jq9
zBq~@uLcyO9@unA`G*rwJp)-+U-Tz=IO6>ash=;_Dl!uKLFQu)2jJW<Rl*Wpe*TUct
z@u_C$juRJEL0P;w?;ge}L9C>!Oo`%Js@F^se@m;;QE~Sv5FN+F<|3#`5r;m3e5%-a
z482Gbza0blbn&k*L;i&L_i+ejh>uZ6GsVZLm^w@RtqMbOQrtwx@>Amc4Uo$b@1S#W
zuJ{j1x#o$NQkXSg{MAy(6^I?zfE9`V_XGNJM!fuOfMSPu@IO#X#OehwSSk*90lLe?
z9wlfj7q`(p(h6}py|<NO9;GYJiMLW(_PjXuEf}m4iwqF27QauGCKttiRAhfioJ+G#
zt@!CzV5t+oNA+=+#X2f6sTa#BHgQEPr23j`V#oV=fY-$f9)R_RcprhA;s+E*yCtrm
zTttI-D-|L&icR&<eMh{^jJCVtP+C))#9TTnG>hM$ny?n}T8ciliVc)}XcPar7|QO8
z&r)!$OT6lP$UP8O4uPdxyq&Hd_lRF}%)lV_itk)TxBJD`B4`^BucMl!LGdghz(et`
zu2AzxY@*M-JQl~&Zfr>W8f}w@#qA%Vqff=UPvF{!So0yksMzcR;+Q!7I0Podbzi~Y
zZpnHosdkabsmRw=qNMT-H_4$8dKC6ZhPJ^)cgdnKG<r(@jD-m=$?OpD?30X8(ZGJm
z51#{gOU~0V*GIB=04xV2Cc50_E15MLo$!;GDf#X%dA$y<1xUhaCJdD9@dgNz96bll
zgOdN;VJKK~_7YqRk-YMd{(B=-@<$u&hDqucfEq68y^j7yNPc}A1|uc!)BuZ;+_Ixj
zha@k)3lq_jZd!O^ByJvPJ1n`r3vIEI#k9~Kk(5z&Q=DYm6?8jZa*VcI36i!-a3)Ir
zHy;*~B(EzWkSvK>FbVJ9QAq=pEFP2Wq+8u7k}Fi4kt*3po9;A;i8c?%C95x>7wMAt
z2M|0V`SfQ9WJo+IF_<ZNXEivpBq6_}+ovTzP)a>pa%>AYb0lv~hQWM^mNFp)k|O#E
z3nhwPV8xPeFJLSjC6d`xM^!3$W*B~#O9p5gS|NF#jun-XZ>adCO0r@)EM1WF)5XSW
ziJW%0HIffj0;`owrkq%vM0Oe@b49X(PBT{}o9w`@N!I@a@tYDqFR<K_q*1L?gJgon
z>5gP8C93Z_B&)uHwkAmlMNyh1>&Gx`Es`bA!Qef~UfR{QN<O3tlQzj~i_o?E64xrI
zX_w5SZ{&7J*m+>-l4y<sdm#C2C9rOZE5*ZlB-4~o)+>3QmW+PMBKmsRfTWNnwn521
zFGA--iQ`+^^gohp?SVIsC7l{H4oU88g0?3T#(EHkB}*vy^HdVF13ryNBI==ZRFX!|
z`k17b@-pL+wfDd|AvtG9+ivM=J7L~Ms`>`XT&1=<U~!ku2!}xrX)wjJ_DWA)g#}Nk
zr(+1Zy`(uhQ1?kMIfHe-^im#Jy`>xffwlwE`xK${l{V5|%THRug(ZLK(ivzAkZz*a
zI8ZwHI#`0F)wKWzr5*Ibhf0H6(H15xrY%gkwDUFuqNFa*pzV-!($DBiv~*t@ZH;53
zZ$+W;uyhwaCP$>rQ-H-uGbsERFD=^xEJ50_25pJbZM4uQNteU|OO`smKo5^fmr;25
zn6!mv@D%AMT@W}a4X0W9l=Si*w4Ii2kb#&jeVJ-Pa-<7>0?3svRM2&&Jn5v_u#_)d
zMQ4Wssq%SXh0>BJ=q{3`NC3`A%c7vBSUUP8K#8>WIsBrf(l2SYEt599f-yWRedGo6
z<x;H}EEUpq^B`9#t)K$JbJCZ);mmpIu4u?rNgq&M>jml6hxGncOH&x2UX;3)K>m{S
zdNNpRq^qxhSSwAZ`o}tH)m*5#BHcu_Y*(d=kHFDu(zk{{yeVbSWO7To${zv^Qb`4f
zx1}n|#WhO1sI2IYbS+(_XqMLWz^4}J>r_Q~PuffyH%F^<<p@~Yq|1*${=W1sRaLZ0
zKbQuk9nz3$fKKVMRp?=tG>BfO2hufEYt$`uqL_Y<^x-pT>y`e}3N3xokUxO+OKWNY
z2BiB)=b-eF3$TY$We!*#NnfN2t;f=*RE{|0kmgbn@rg8_cJ{+k8Kse*N@MBk{Ug#W
z1uTt9t0@UMMin%8)}_l<08B_-sd{C%>@PLMU1U!6aNAW@Oz)VREQN+-kIZow2Hj;`
zdeuB+-qo<XS606TL{C{Jy<1)~$M|=!yH9qh87B72?i~QtTc*4QqL1tc+TR?IwR`|i
z{bf>$5(mgOXu%RF+cX&-2FZdG;l)AOMM{PT%Z8269U^<<G2}vJpX~z(lcjG52$!*a
zz!@QHkAc6DGSNHWjFNdc=nEi+WUtW1Gg@Y$JYkHiI0+6PmVHJmb*!v56y}e}R$YLJ
zIN3-H)Wpk@K7@Rt>|eSDo+P_PbAGbytIJ?HD*O09$Q_gU+TmfUOhx(bG}#O1A#hyQ
zMu+tb*%m4r$&{s4IbbkLHXaK3ld@O-1$IjIf*A%+%R(qcmMu$s2*DiL5*3u@%97}!
zM4rr53W0pthjMTh$a1Kts!*0T8=OV5vtPjA8QGFMFkdWVQVg|3)<NYir7|hKn`N?(
zDV=*(CMu`vzU8v(UT~^HwuF}bN*RkzUgu<&sLJQOY?TeHRkFEBaOQ$+IVC%*Wozj#
zKrYIhf?@ZPj7_Ji8d)%11gn(=wnLy!7C<F*mt{c|jjxyea~o|}WU;}(uFJY8rgB53
zLmb=TbW;{6Mb~c0`pQ9Vke$m0xGig;Kw6_Ll0L<DM<)6N#JjStLRe~&J&i-Rn`O<k
zFS;jt;YD<<RaW~9INM~W5}>R{Hn|v}SEi%<Q=e?I1>*g(q+(zLvOV+Q;h^k)bTPy6
zQ1-_l`uj*0Pt`h)Wy9YC49WO3PY%nRY-oEbdyxaXBeHo#Ffl4y%?EKz_F5%~<Fc>m
z&gFz`GZk^V$VcWw&Q*SxBFJv?20Bi8$lvUMrM>c^k3sa5cQ*p_l2^<Iw$CB|hpubv
zm+!g*-@N6*kAV5eo6bS$0eK_+6u$BX`aXcad<I?f2#|Xvf+bL%c@w<|l4npF?4bOW
zQy7F``LsM}36V3Gz(kll{3yi3<qN|g9wG0!2f0Z3A9}bQB|pptOSIgPOJUC#`5W}9
zlvuedZN!eq%V{GPCl9BJ<3zd350Foi=eD9PS>8#}i43{o2rOmFuY^G^OFl3MUYwM_
z(g1^}<g=y%oR;sRc{NvlIR|d%$?wvVlP`~X333JUJ3qogp*+uFhc`v?hf3%^BhUR6
z28-oZJsL~oC3MTARDOC3B+BI8&9Hk`UO+_>74mJfAW$j4Me*Hpa{gst=jFR8j$I}H
zDG8hx<yn*=xFp|1t6`1&NfxkL`58LN*U6_-9nxj_;$}*})yw~-l*kpi=T8v4Di5M9
z&^5WcCy3YOSFeHfhCC((ow+F&QNiRbxs|pe4f5}s;o)t0K@H>@<+Hy4xFfHi$n{<M
zmLq6ul4mag)+~=pf}s}qRH~M_C%<$b;;r&Uu~c2#CZ9zo-1~C*Jm_whue}Sw4*8YC
zFyARZKM8GJ@<5t59?0FR(V1@fU3!0e<gJ|`_R1C60Dbb^RJzbFFD`|a0r?xF=;)wa
zMiG;T^3-=>{*gR+0N7*s<+ErTk{fWf0Oj8Ds<%NMmfN4e;8S^$4BAHIOe&BWl`H5b
z$(Y>37cArQ59`r3A)iXovfYZmbI|6h2%@-+yCRde@*avn`kD7C^8Nvfr=n>a<h&Ga
zbl}{lc=ma;?N`)Xg@Cu>7==w8K8h=i@aBL*`w!grRfHaa2|op6I~x5J12pLdD5_|Y
z2~=#Qh+~AJ>>TVyDp*uM9HlUCMB5?7?h_zJD@JmmJ4P{YGn_fB_?LdkSjDrHb3LN)
zXap9gII#?J@rti#dz0W$%%j&oQ87q0e@P0T@6ed6*ua6rQAK|rv>j8tO}nHN#eAB!
zQWcRN@Gwm=nMUonVjs##oYEDRDbRL8!IVKDLoxGzAZ99R10k2CxI)YCNyU@%0H+im
z3_|?0VmcifvK5X;bf-N>;Yp#+T*aHN;K@^@ZHMlB1<x6vK;cDGc%foBeWImEamoa6
zM$tt-Y_TGhDy>QsFH%ONR8ju`O3M_h<zP9hIC&6VDp&0M5}cKa4O1|_=M;Sl!E#=4
zWjV}NDZX&f6}t<HxHXWdR*1ic#6`vJx1jBkV!0i}8pU^aVWL*CbTdGm;ytR%yR2A4
z>u$YbU>*Furno?H-s_6F6qdN5uu?4drs988(|k+uQWRJk6ldGv#cjn;pF*xtQBDDn
zJBpv9DU^Iy!TuidO$zY@sLhIp{cy2G@m~N0?<o#AK~1aT<^53Frcl$F=f2`6`T$V7
zVvZYFIux^Bf!m#m<pEIErI=6O6nmg}Z!<u*Vmk$4dlZRZK)hEGLs!fD6z#Or>{raw
zQ~YH>F+owuL4}@PnTLuH+KWF@^n3;{9xG;l4=|+o<~ImFQN+>KZCFuv8Frs4!nOj8
zDBhv+$5DlO62!+8wl08i#Ud)_oltC}4;JlKwo=sBO<A7_fj!EXjzNpNvKgh+tDQWR
zrBt-zrF<bCmi8$(Oo5<}at0INfO0K8LcYp3H-g1axrM3{{gwW2z?lH0JVYzQ2g5$1
zonMIZhmWB<R9Utb2E&wgs;3QC`chILLirv|>yb)#dO4z$V~5dpNV)DAXo*%P+y^m6
zd3PGH!^#bB!d|R0fdVc^l$&XZi&MVq1Q4&B|03iPl=0``eWJ3SLL^B_fnyiYW6CH0
zgBK~v#}u?qRleO0XVR6&>FGM5e4aLd8OlWz<jYh}IR`9D*|P;oPb#;)2I48@yK~^^
zY32L#LCjVrg@Tx)bkjgtuF~^ssLoR^x&)p1N~e{;3Y4Gn01B0-BWMRzq})K&I%kv>
zlu9gCM$wl9N|bABp{7*%cPDh0Da+#F{#oT07tmI&+(Dm(t5CYX0%t0f()aPBol~Az
z4`t_-U(tMAr4+k^ctQC&jYYL`3e89tl~dDUw^o@*C$2iBKt>7N%SsE?bk!@9UV!`+
z<&wA1cvV?RH;Qj4hv?98Q#tcB5N|1y3xRbgrv<=^PUTJp%y%inDDC|~IfE9iZe?^f
z%=ajh@}RR<S+xtqK4l-BultoZ*sw65tR=Sxm9?n3aX39xE~hE&k#ZymCLSwapgM{n
zCI33yf1>=F{2o@;(6Q*La`AW2J)&$pi$0AiXVa8Fru-=ta=TS8c|ePcDmMdmT~%&}
zAm^rXKLp|)l^1<($zA0(393C*P8P82RryiC-{Gm^P(;m3_4+cP`&2np2fttSJO!w{
zRr7nm>Z96DNuL8MHqCFos*MzN@>4ZYlGR@|vk#62sJ76<5~$iKftDcEdvuUFsG3S^
zMX+i$B}hV4E>pk~stTqGgfLYxeRwt8p~@A&M1;yNftpB_Js4P&s;CUuA=PnT2u7>6
z(u^3R3KK%<VO1p?#8}lc^gta^o!<m3PF2Q3*Wy)Q(-n*a)lam3C8}Jz@xvsktaN5c
zRz>#0?oriZ%6=bH?VJkn6qVyVZOKzrW(vxrsYEnU99IQXtzf#!osNhnR9L6+0;v36
z1jtm~$^}c7>IjALPpVjSm^`K0@e{P2R{cjAq-<3_MGkXRU6oLstNQRTK%Oeu3wHBW
z_QlXrplbgS;)SYr9Fz$vQk_YL#2M8WQJ@y9#9u;biE1__c1l(17JxF<0*b$!Rh^1N
z56e}CSx{P`l81m;snSz%?m5+(2IxMoI{p>}s#NpNfOtWbOT%5Qn)Efy*QlP41Xio!
zo&r{<O1(oD<}Rx&&q1PI6|o7}6;;Mcbmpq6{xcA-sqO`#zt>fPRG@i7wUV}6H&uyr
zndX)%;1q}rsull(w%e-90*rH`N<-VgCKYoWZOy6*%8$0F&dh<bd#W!Vp{-SQ<qf#q
zrdseFMG!hv;<v%msd{At<hxY;bkyrn&7)Ifuj&IWK%dH;YJ&$=TdCaTp=$NJz#gew
zEO6$rs=5pQ4yiu-9BofjOXmR_R^{)7rKhUT9>BE`)mGYIkE+6`gmg^x+Z%9gT;-oe
z1xypF!a2~kTm9Nku<N2`u7hu`>L3aoxTzE9e&ZhX(#`l`_Nqr)q1#hEmoAriscUIM
z_EwKlDXEWI;0oda_2b_m?yJ5)WdeTc^XU-qS0ADpivabkN*D@Mzw#`wAa&eZaK>>^
zJ&h0fVD%B&orS1hq2yYqdh8=KhN;t=pfp^4v<+B<+KIk97O4(<3f)oax>^up)a&^$
zaajE;MXh4h{~6HHcy$gv`3dU3od6QmGiISJNiEq0*OJwjX8=2@_N2PhV-B_3OOQxW
zM{!{(RlVOGeM(c$?nUEqwV1xLldg_qf#rnyOWH1EsB2@ulBxDz4UnZSq^bX;T14^M
zQ|gr|5Xe#gPW6Mi>hp9PEl-_CN3|05(O=QCQuX%>V5m&}zf^c}R_(Yr1JrW$ecBRK
zs6W0A!AkW)9SojR4}T27^Xk4*uvV$9l&rd-{_i2$s@0V~02kG6YJf}Xn7y!6qwf6@
z=4;i5av@NszL^AYS-oij;Hvs(ns2VDf1~r;b+v_b-cVn6(DHCo9kUWn-BK^O3DBU{
zQ0eS#^_;C}Yg7jZV=S7~E;j(0)n2qAYEl2?3C??J25pvF)l(>))}~IR8k+m+Ei^#w
z>akQ{9qQrf;C!I|8bw)7-Rk!_=x2}mUrI*ws{i<yviN=KpWg@QSIY&U4yc2S@NH1N
zqaFqys_*;&zlYQ>Q~czKdMaftht(4_mpxT~MAgJ2Y7@Qbqw2*45Fb;!7Xgf`_q)OF
zg!&;DoUWR$u0zgEGnMB2J(|Z|7=*o=XfvH)JT(a~g4Ij2kP0rnHE)c=Qy<MOdeshS
zED~V;nw9&21!xAk(WgMo$rAV!ta)uZ+Cnrw|AX#O%>oMYMQHlyJQJz8Lknh<rp5~f
z<1`yp5Qx|O-UTc{Q<4uXQKLof#^IEtDa(Yz$(n%yXgjJoMThodn&4S5n4+0e0%EEr
znU1t+npfAr{Bg}UAA%)aQ?nW@Co~)?mdMcj)DQESnl~@Ne3oV@g_%!kcCCioDb3Gx
zIytRbxC%aHYtl+#K1cIi2-+OEng}^0@-(07p)_Cf=mTH{nzaidQK-rDhQmdg76NB9
z@pSL4SmPE8e@ivqNx;f9Ib#qwtGP*0?sCnabKp~jMnJP=rDlOIi03pp6r4Y=`4|}k
zrz*`FFLdI9=9MGhtafMyd?0^Olkow3yQE263~G($jlIxatLdfhU)E{1S|D**Q+Nt$
z>NP=bFn>+6{04~EHR&<nyrDVg34a?jr+$Qq+ZrXs;~F(DX+dn#@Msg=tWi^KVvA<w
zWnlL-(Vqir)j0k<2sLe*|0wj{p_%^`K&QrwPUKx09+jo{XnHBQ->cz>A=sx`Z$MkW
zX6qriHlV3MM%ZaklYIol$C}*~mmAW2wgBLXrkx^|Bbx7N7dxu?WHC6$G=EUQbGP<2
z>XM7L#X-gOuG;;T=##tlwHcs#XyevF_g?J^N_=~2g%wcarF}OUEc>+6DX!+PeeNmR
z0<_z$@F`H6T?>{Vt%ynu4{B@7AO>s4pT!`AXgNzTzM<M|syz+U=05>vxb`y=h|v1K
zM)#8<wFxOeqqJ%-ICDt5;~NM@Yy00rTa31s4`&W*9sU5Z+KRK#eMH-kh_*PbfWkiU
z+E=LlDM8yypOZ|~7B-+QNqgvDC`;C^_#4WOY7>Lt#WC$t3WKC*FFg-OQ?=dGsDL+3
zd#@PO<J$PS(4DT0pm_WV?YDF{G(#I}MO&seKNMJ&_H#;doz!~124_xbdAEU`)@tcW
zQMR@@2$piRD^uY`uC_lC=JT|{1t8{YD{CQMpdBcK>O$=-y7*P3U5&a$htnDDDXRG^
z*6!wjTB3cG9_v!=dz51@(?(l>oz*J#!L@SjmHogfv_H@uq*9wtDbaIUb0vu9wMD;z
zSf%~<XZ$c1w38y?cD43RN~2%Y`cusNlJ+3gSk-8s3juan>vspvIO?@aXu`OnbuWgR
z>)P0Zpx)4~qVkBF+Q2sWeOr5uGT)6_whILBXunp0*sL9)ykU#hYK7f<+AlA|;C=0a
zyJ&0IN-6Kqp}j}x_fD-S7%W}d?r4ZV(7sKtcDHsX9i@95+7>!6_G&Lu;=NCMm!5=v
zZS33V?|}9S71KP__6)%MBW)T@7>~6!ChQJr-`fEBC))LNcplb<E`z{RZ7^j8Mzn9f
zi?&hiA50L(v_(50KCazFzt4nr@u%qSZrwMy9PQ+ybND_4)m7KTh9x&$_gR2FI^S#X
z!d<sK0Bs(+`Y)kvukI-wi#&A&RG;dl`$7t5_UYV2(7j)`{yd1@x?U;F`{=Uh(!>E>
zhZL^)>b538&QG_B1x|n6&+#Az=zgK^Oa$tZ9ZSI)q?5e^>OoyWE3jalnc|-zx^>~e
zLUlLk%oL^zpAMFA9cvLhjL<DCfcZ$B?@`!|(tUgdjvmr|GYO7H>+aLb9HV1W0{gJ8
ze=pi%b&@U6c|_O#E<l`a3*EYl*Dd+k0o@6@?L`2IIzRF)N%s>?RLMFy1rU$woM_oU
zrqk1ek)pHf0aA7IFF|*j?xP=|=D6<5Dd0@ky-wB7Cv>06A&{Zd{{dy0y4dHTI!jmM
z1b<KJc89~6Q@U%jz;asmRTD)JvUPQpkk8S5`wMjE>W)*9eV&ey0%E?-bs?|<UCT5W
zEY!Jw4fl(5>u6JZMi)mHBZ_sO`9o=m?iJd_mg=IyAy=kLra<di-49cNmFtWKn6J=v
zPz<?J*F|L+=X5R0sDk6Xu8I!IRl1{x(U}XnJ@f=t>wIZByQtehxrIx*Z{CHaI^B;k
zAYRse@ENdrT>yo2ujuOfAbwTnN@elabhT9RdtLWXgSHzwB~=68)NT6}ZMSqCzOdV%
zd+{)Oe_NNv2IgqgZJz~+JG!emaPh9Lor7L9>88-`u36VU2Wnb$o28Jyr^}#lajPzb
zmftp=iY^A;*Zrji)~+l04+0&!2--_`>fZecCc1QAyFl)Nt|S4Lx^=BTfTc(G_Ag-R
z)vc$Z%07o~I)(iEbxXOR4(R5#p)-TJNj_kGsGCXC-6LH%oyZ^SMgzbyq)U1kZBKM<
za{z{QkMBbKsV?R}aE|Df(hhr6_mJ|*V>;6gjOe&7kggI<=>DUM-`)BkF^Deu@lEL2
z9=)TGvM28Ptx8Zm^oDMLy?V(~5Iyw=1EI}Je^mm(efl+@!{Pn<*y&*L*3XCq(MP|X
z-sS^(|JBgutG7G=(NF&l1#$iL3aVBO(AQIfBv9{6v7jJ*>|Yq>gL(%Q$p-6ZImpux
z{R|FxLiLLmqfcS_X%x>3*Wa52)(HK-RJj|e=TlWzl)nFW2p-a3H$xy=Uz!FJG5XdY
z&~{kg_c{EH)h{6NBl<<(!nHX4Qp%ym>oea+TY^4g5I<p}p4|v7N&1=pqxUaa|G%4H
zJ*xLy2WO7y_tUo#QuHbGu%+r-#E?kSbLq@;T(9{V&ZO&;Pk|*<zp4P@S^5JMZ9b{L
z(gy65e(q$reOkYcE}muUThgH=N55ny1akGeUICV;KfW8v^7UW;N);Rh`nqR;7V3Ya
zYNulTIeN!R^!G;qO7*fSFj%gi)&&z4`mobrsnq}34}mKEiU}CJpl7Xwht>LYO4ror
zf3%{lR$og6K6Uzy?*ZJ@3#cOdmOdmE0uB1K94Nc3x8bgc!>Li<uoNcl=;P>i*j@eX
zZSb^7??x$(W_^qf@-6y$I)mTS|3TATtN!T<u(at%^Z@tuDWza(*9X!q#}54#3Ltjs
z$M6kBr!KuW)d@Y&_uYYbx8ABkmwNPXJ%&K9{`<#p+tH_giJriIeLHn#K%Y!Cu!H(l
zA3)7R{TFp$eWZV;9mL1_Y7Nv3>AR{RFrxpM9>h`o>y=;`(`U)x@3{Wmd=Mw}?Ku$G
zZFrfo|1O5JXVK<r_$>@Rc^KkoIofN8SphjuhasBYDlfwq*8%n!JZPfXZ%C)_hIt!A
zbmH?dtl9{oui-8|P<{r<BM|)!$0<h_U~o!@nm~i=O&AO^yh4GzgNB9CuoP_gwHz!V
zhJA~mI@Iv!XMk|SE}Hxz3?HRKAkyGiPB#jp42@NA>X6}s7K~7gLHjD?4;un0WgTny
zijJ6ZhWK=JE#5Fl8Oj7h6fJH^2Bi<wBpV)jVq}gQKBqYGF~eJ75J)k+)dTFfA#fqE
zbi+G+(0Rh}l(y>`1`id8nT8D;)Zoc7Jo*OIlZKLXC_QBedH~kb2ERdIxrW`X=wY70
z)&|ae!#{M9tHAKdj{t>+{xlGa44;O)^A}>d&70v&nPF2W+&*h~z(QNOp@>%Y3Ipd`
zv{f4JQ(4D3!`oC@dfuQSf2#~`U!wCD4XKlWT{3LUhCq$syLUmXHGE(OR%g&tY0G89
zcNEX7H{=$8c*VdnK;Ww3^yl#9njzXj+rjIGir>I`!=TPb<1NGS$>>Cb;hQpa;<h2=
zUw}qK-7KiNV@OX2%Uy%lePB(7S0!j`HWc24_brAWz2V_K!#8wis@3r0Ac$>-xI(bp
zH?${1uHA5HAwY-0@E?eshA$7%Ub@RrLKib07&gYDvD?rv6IhR7Z4i9wH8ALg!GPh#
zTL6QGeM$&CGz^8p{E%TOozI^b?%YBrh7Iq31n|@_*8_tvVi;bCwo$`k733xi0rd61
z-NvHtz~W*=<PAF~<F1Xgm)>Jcr?0QL8<`aU^e}eQ6SUX(4hNX0F^dOJy^Qxepk|-3
zXb05nH{SpMiy+21lvwpKPP_=EenuvRA^nYCQfYL6ahwGZXw;3uiy-4F%F7-!mO4XA
zuyHe`Btwioc)A=;p~i)Dr6J5%N7F{Q@i<M$5ym14MMoOj8sJQn@j)Q^bjY|>2>EDZ
z(m2LB#;BeNfy2h7-LM;LTu14HBgU`307x{tU4(d&v9JSj$;LgD7(HstqA1xh<B|&y
zPcgns!5l}b@%TAV(~M^*gM8e`4*^Iw+OxoO!uSPUn#wRPz6WiY#)G~vm}T5Vbp|Jm
z-@XKJ%9xe~mea<USD+KwMuZA6bsKjyK_J)oHkAV984uD%D&P2xABL;I$e}$%p>gpc
z$Q3z^Zm$8JG1le6V6o9(ir$wP7tcgTOO4%hW+^jHq3!lr;~Vr9&2r-mDnqF-G7_Pt
z(zs~_44yNdd<h*rZ>((qs51U50_O$e(N=I)8|P8n=A!Yr04Td;e1Xz;HAV-`ptVNF
zPMSUHj7KPYa@lCB0H`;n)68<k_~Bb{=Bm-@B074_xaBOc>&A6-gt%dxxdzxx<0JZ}
z`z_-<dQ}>XJ84R}ZLFq1T%%D<rLcF59eZKnuCa;Yc}>Quez@IiY^B6ki&5w31hviB
zb`XO1jUlh2vE8`iClEV~C#n9X)42XUv~?MGRzc|l<1Zhgzum@HH=wP@c=HB2+G|Xw
z@0#`*|Jsf|^&8tvU>Ptjeg+;68f)pTcxZg@ZD2#jH{S&36XR+sTpl*I)Khl)sWE}f
zj~GWSXdE>zrCEB+I5il~j2rDMz&c?ZnGK(In<D6Eb}?<GFp8@wA_FXLraK3K?J)^+
zA-C6bV;P8^rl)Zb@G?bEfA^W<17Tsm=^p`DyiGHCFyv$EnohCY1Ezs>Kz&VbyaqLX
zCb0}Y`J4Qx`a8h1i5}fRllz-c6J)Bo4VHr@Pm1*go8F~3V2DX#1ZSve&ULhfnOqh@
zAl#&U5iAj=xR+os(v(5F!6;KB?XC`)lBoLZu&FY265hX9)9kMxc*K<VBDBSs{;B~_
zyy?R}j8}qbW*B;(XwuL=JIS=4-oIqirgy+{)Rdk9-N#Im6(FXVo}+_Es_Cf=oN1;K
ziU*{dSSO(6gejR$kr}3b+Q(&@BI%}2mZ_G;*KyJ`eGeK>nHJpuIBjyaL20(B!wG6~
zOoH?9DcAHY<$wxIH|S(sXqtHy#3Iv|zQ9UMNlJiH)Bh-HRc88@_7`VO<qu$@+@xIw
ztim+>|2rVlj7YGYGp$!(fX<u#t$?8_hv_9F;0063YiO)CN#2LHi>80+A-`mLmY$0m
z(}^@l)S9Ba;c%U45(nlln_gZI-Swv0IcU3LN`D(|S4})B&Aw(Dpgrw%Q`mc8xnVlG
z2m^G}^e3ImZ<&t&jJ`COrp|@x+a^ap?bRAhlFe}Vj%oKU*u87wCV<#vN~0)Hv#IeO
z47QlG9ca5}O5X?2YI@)T-S<sdLddn7)D&dsFtHawuG6%F7Sk@%i$<_KF!AZ$TDQrk
z7Q`NtQ3hqbrpFX6>NCYT=0dRF<o_NV9xx421aQ!lk1`3Tho%Msk4$&;@Zzy)E#;hs
zOg>pq`o#3YWb|p+^a-6XpPHsq&C`g9{TP-;O>4{`j+stkE_50<?Y{=q6Q%$O9NleR
z9s;6^Iei~EUCqBm()#CSev@iU_L$3QgYRzke1w7WFxP$n7x$VEGr{6%zMBiBUgq1e
z!1kG+&H>AQ^F$|rw^>iuDt*k;C}eTK{815De9fH{7WXqJP)5ezTzngC0p?7K>;{@I
z{SKBOb6&~|c>fNXmr?vA*sON}HN^aS79>K=A=jWg%sh=s3c{fjScJJP9*#zuqiHpa
zGMlMj?2vgHC9<N;{qEq5G4G-2>aaP|3*N_?8>m3wh*>NEOPqN!Rk_C_)COk~%>M24
zt*JzFC*5UAGJF34rOD<Ultw>l?&^TxG4o>DBc_-y(nc)ReCS6gO*0>G1~_gm9fh`Z
z^V<DrJ7JDJjNd22%%%KlruizR53|fxsz^9(u3>{S+q`lVs&mZNWT?(HpE?ZzN1nN_
z7ZUmAW$&Of1?FF9@C(heA3~zY97`vdGv*Eo0Ti3__Q07Ev-elPO3lk@Q(0ziIRx`(
z%^Op|S#Iu(hIob9K_5)0G{5Qv?3~$i3*^q5|JMc1D)VOgg#88c^U(m+4s$q#DleMl
zJZQUQW>ZqW#ym(zkXrNa^mEmjZ&bqIWpk+y+Um`p-3RfC+06{%RdY5~Y+W;V*23U*
z^Xx3N-7rh(y}fDPm4J@kGB2F~vB7*c9N2Ah0EI{z&1;$f?wB1WC0x8~E~msnlevTo
zPn*rhgW*$)xr_y+_sq3);A=JSI02S6^Ex^M+&4G)qOINh$^S1^=9!6L=`{bD4VEr*
zr7N^NFuUXf>o$9Yz*3KS`_CBsUh~Q;@VC$W3~dSep_;0q2h5+%0Xk?tp9buq`T0R;
zdt?^TMTy7e#s^R{WWGQb-=3JO=YnO}yr~}MpPHx8hwDbn-Q5rvH3w6KcFg?l=P)sD
zevziD33KsvIJ4U#ISMaaEdMc~%+<2Wfi^cwjK2e{dn}*PHg>ONb1ry1EmM{Qcv<Wk
zIK0mi;|DMHTW-*H(A$#nDu})opFqg_S^Q|W^tZfD*LZ>~|7?Lz2QANk3Z220fvX^f
zSp3ZZp_UcJAck2QX%8Q6`Rh&eCBoADDShiL(!zNYPDNSH4}<lPWq})bqAm3%bSBo4
za}*|ySj667iL<OIhlzMgDLugnmRC>1nMBKMHdu~Y3Kv1(m_@i0T2d_EeucK<7JCnf
z=@v#CuoD*B-%y=pX`oN7p0vESoId_}%JOptcureR2V$VIEv^*V&9MldfG5`?q)>mJ
zCGiC0^DUoJ0HeU7je(j%i&Tg~D6&LQda1-Rq=(&7%SY81yfRDV2N0;ROxprbY0+N?
zIA^g(psmVs7H4Ru3l@KGm~~WJ=CwoqqU96%tm-ApzZ*fVv8<(Or`9sX9ax>E{w%P|
z7LFCeR&N=mJDXQ5+1ug8HA~;``0cJ+5|@MJhNXlSx0{wDF95q`IYt4Z28(?da<?tp
zz5>>0SwjMMEStVW2k$y8&rrCl#j<|`%-^&0*Q1B67F{x2Y_qJUC-A-{i;581EuIRn
zbXsa?XVGOzI}P~<79Q<gx-E}pz+jK%9SexPmR~~QTA$_Z0~nHiOB}^S2P_4&7!O)j
z-Gnm_Eru9qd1P_?xdS|pE&db}8nT?25A2Dh_9V1DwS<Y_+KA;aohU{vd`y>4W0uSi
z5XUXHxo~a5V%P?O-PUzWpv}cPn_?uc)(pC&=4NfCG2CPQl<M=`t$nnm_OQ<S2w<-@
zg3b<})^P_VU-w%#(DdPLjs65K`dB~v|B#e*^-sY3t+NloZh&>*I0OT&hpDC}$ohF2
zu!Gi4JFrme97>ynS)bCmGu-M<L5c`#z!SI@X{}8`Ta?xPBaF-;Yn~feqOC<1n2oV|
zW>7WQVXNOV^eNW*>HjB6tPj`1w>WFU^XN>x_2f~=Cs;2}hqgqkIu>n7)?@S+-^td|
z)6kY;eUEb7sn%!c1LA4c&Yb|qt$*pEGu`?P1s6|P=kx<)S&zA5NKRTU70`0Z`bIRp
ze>v6}sc<;gI!3YJJnOtSU@+f0N<sPp>qlakD6}sB6H1G$oMn(dV=b{lTd{Q){n<r{
z)fkPoQtQ+RU}aXnS0R4ZdX+M6<<<e3Z7Zxh`(d!s+VBP}oU?u$1M&0LCNW(suCfX#
z3VXr2jIQ%kTfZ<v+ePb-TcGWdHT5HCtFiWWqW87d&99@a&MIyIcG>zJooTOHKc&6+
zHS5=pFu>QXt}y^NtaEpPc+)EM1?Mg6?qGDV!FrFr(sbLJLy@IM>jAng>9}LPO2d8E
z+Dg~Fnyj;F^qQ>~Z$q%fDx{?EJ?l2QPt$5mrOBktTD1n8_pQ-4fwf!DRRim=imsv)
zoz{!9(Csekk%#E^11pL<@N!rqLV@*Ir{sXM*Xl)OD1Fv<DN8iqunxV5#zE`h2CzP~
ze*QbuJhJ{yRp*bbRj&dJStk#nPfx7Xbdzk@Iz*L(Bi5^b0gPI|b%pqt_11K7j$5yN
z1oIQt#nWMFx9zXBAiCHVE`*$$t&IX(du%s~(dKSDzaL(B*c|c@z`eE|l;GKCTOR>z
zzs*kfaJ+32+Vc6>T$7;mfbAxIrpebP8-qbVTh;*D{B7Zz&=z1jPVw+S+eM092iX=-
zkmI0Da1uI$ZMWV+&q8cJQ3Y?PZ3ER4hS{>_LoVF*yW=t%BW%U1AQ5Scu7Rgfwum+O
zMGo0IiU6W*Q=;Hgj4fv$d^&9VTLGo9w#r42KVq{`#3jzwwgFn=ZCmLEOM>lDF0>@t
z=1_1x$@Y#D<dSVqX<|HTTU-K=YD=OlZJO<M4?6!Hx4l0NXu54XrcI|4wiR!KC&RYw
zAo_ID#-~U3l&ys}FQ;t@1!&8*&7#a`j%{iwoXNFG_rrXit(JCf`L@s>K`gNSdK=0L
zZQkwxMYbJk5YN~qWk9aPHlON)N^M;))5ovNY@K=V^sH?f)kl=u61~7$VarSbsI+;k
zg86f{)pR(kvgJ@->4I%TF*vJjHz`|m(KbZ^@k_QZX~$S&Yk2`IwKhj7h;_CDi@<W(
z_8FxJ>TL@Jz^>S`LeYt<HfuNioAEUpV*$|Xwv3Ay%Nw@Hjrb{U+FGYV{+6xwA7Bl(
z)N&}jZ97WuQKM~p9|r%9t$Ymqy=&V=k>MuWJ3qjDvn`UYa<tesW<k8o7EKfReVdOD
z1lnyMe+p%twjb%baF-2Ln0Wsl*j#Kd-);McP7OV_2>R7}Z8O<0*k}9eCUp1Pj%GpW
zfbG-uU>UU4d<*%9Ha7<3AKBLJ26$}ioQ$qLv0Wa8z_6|60)DNhw(RG?Ib!>Vwl|};
zDeE9UZhM(xBonrm=x5sPu&<?Uu#5d$9(;4Pzi|Ytd+ZDDL*CtfBndno_5@n-_S%PE
zg(XjWk{p<q{TzKzV4uC)4cLDBF?u|_?O~C?eC*jYKnLtLnv#6&<&@~~vj<V~)89Uy
zUf2LTYb{s;?G6=1tAp%|Wa#ffy9>qjg6(h99wgk}+yoF|UlsxoX^#zu-%<9@e8F<a
z-u4URqwVr?h{xF9qX5WZyEz(dvG#H;3?8vRDo2;%?c3?ONU$4sgEP^7xDs9@+1)pR
zGui&5BOAkg)ZR`J>0@^5Mf5Pm{_bLEOSQi>4f1LB&|@&4Zcorc@Pz$h0zihn?R|`M
zrakZraAw(4zlXMy_M24Cd&<7qhPKmo@o8Y$_CY${=h*p6p*q(dM)gz$_R;UbQfOa&
ziT0mG_7|x_^^ARx&L_q8>-55x*nQ~ySZdGO4*4?siT}|1v-XXfAy95FX25QR-GgrW
zRoWv~13PE;psQHt?M+)DP-TBi)o&N<`)TV`ZTD*dcF{hEjzyR3!L&iBv47G*@t0bA
z4V`l8?31oR{<3|y5v=w0{@<Yciv90B09Wl{bX>S*7gI6!b^CVOmff&N-vV~i{>@4_
zddt3rDz6&s)2ZtGwtW*lxp(b5UD4KLZ*+y0X1hC`&s*#ZJ22???2Zxo)_1G@xB&fa
zvp4U-IN!JX{{Yr@J1-mZ9rl0T2WzKYNt^I4`xDyxJh1<{7NFby3&nPN?1{GldhP%A
zKue!};Tr(`_6^Sg4A_;F7aFwxNuj@oc4i#p9@!7HK<8t7@+{bM4B3CC&OEWdJ`Uf8
z?RqiHKeeZ}Lg|S8G##l&?W-?>Wz24+{K2?=ULuGS_HUkp?%mF+xlrTcEO;FPuFfGV
zpvBFZ!3A-Tb1w~-yK^FC@jaZ~DA4NVypHmA`<yF2gctiA&QnF8dOOb>1nT3ws{*VC
zoXaNQu&?v+5%j{(SziFm-}z@+F$0|c3jr4BJZ}oxf}Ee!fq2k)5hcljoqcKf4RQWv
z35F}w`83rPhB^Pe8z9^{V-XBRIN#CW7m0NK!wwMT?0D&CP!Bl=Rs)T8zD|j-80SZH
zd_C+uM6sw?=NV^#9dX`r0Gx5o+o~`Y@y@@!04%||jp87Q&VfGzBspKEIXl^TDqRdo
zb$-VNEY10=UC?sec`=<!(w&R`g`pG9r$0wOGo1H3>fmsua};fCvYZX{MUIos<Bh;h
zI|u&-6WPx9njo0toI#&N%60yT-ncyHEp#Z%cP{!8;sws5%V6;TSo#jIsIKR2@7-ON
zUCP4Vd$$6{7!x%;KWmJ!Mvbw>5{=!M7)?wuVO64LY0^P#AW}p?x}Z`-L5hGPprA+*
zP`U_$3MwiHe(&V_KaY>&nKSdwoU^x_Gc)I!ZGUYCm^t=VCqZ)U<0v+hXa7Cbb6mFH
z<_?j3`vVkDFR-7n0DV{O*H@9JMfPq>;LSDr*^6Pf)P4uuE7$GoX{ma{ehXdQH|;+u
zgr!^d`#*z1g}o`obgS&WDA-qRANmxMHTE%~Ab0Fn)PU65=T-o-&i>!05NWUv`wRvf
z?bRCq)@1+LC6H!&n~&)JYq8(A4b4`2BQ5^h>=#o)_rASlI}Enl|GE$4f&D%KK6Tjl
zr31Uu{y1eHAKFJ}VrIMS%N{|b+rHx_$RqpAy|DDyUOx?(PwdA`f%zW$4tihr+8?CI
z|5N)YI?Vpeem>H|M#*z~2X83$*?&XfpBMHuw26LcZ%PJV*&mSLx9_(PjRhI7-|!)r
zukDNI9vieDOF6|M`@iPHr#JR{=A-3ku=R&sC&SWYw44o()gUegGpbT@HM}1Ob$5ez
zAnbV<y1s*+(bG_{9;5Iw{7hL8Z-d4E;G&P=OBTe}&`Zl-Kf^rwh{gfK#{)p~H*`|e
z`JiFveCQoA@DxBiY#5@K;t_)r1%r+nPSdI*!0_q!=nFKI(YE!NA%j-^K?Zl)Zyq;9
zokA<vXfXd9G9iWw6i^Q}MCG6}%&=`X$O(gs2keF$I-4MJ((tkvFcAhW4<;fFC3JQq
z%J4z~<|)G-%3MbqnEyU|VMrbU^?1X0N`ogD{?z~_(Xf~P3y9N(hfZiE89wO4TqGNe
z1DC)(Ye=+*`E!N=JHVtEHk1K7)$lMLGHHfYr7)3UFtq@=U>G$I&RjH<H$frOkfTH^
z%MiC7pqC86RBxJXSV>vl97EYFK<64haRRfz;7R$_Lc{qow5}NZZvgD7;VUC8&5I0+
zYM^n=u*?%^#fEKEAy8uYNDpU94Hr`}itC1dsiL9GFnKXZxuKDQIyVj5SHsa;hUK)Z
zt1y()EnaDuDgm>~&`hVbstw#f0IM-5XzO#w@Rl!HwT7&xnEX1!58EgXbJtKwo1J@x
zn&+_8V3=ozR-?h@Ly#sz@MKtOHfSkn+hSOK6F#*WMufxCeM2urk=hN3jbJ`7Z2t^{
z=rH&(XmuJsr1kPcLn|#&Um1L8@&*l-DG+&M@ZSdFyfbw;tv~ngbnk(N$Ii|TaM62b
z`zjE>owL_MCVXevT}(;B&Ith^XLfc_fGTz8s;dym*g1I?e9GKuw;h(Uch1binDTbU
z(?AP%I_(9sWakWDpw#UgzZrcUJB_7q=IPGQMxt+EXUlb}C3o5Ngf^w_yUw3O=Yd_9
zi(x5fSAP-6Nqp%G`f<DFokHvEuKiM&&)k(H23o<ccs<M)?TVcQk@8(B!_lhTW%DaU
z4(#sK!bI@y4~}DkB6lyF4(PMH+y4eLefR7Kn9=Or+$NwHi*~!+LTCBzZrV}Q?sj*A
zOzZCNsOICr?nxTB*0a0pZ<u(w`@4xye7#$131^%gEGsckFNc*rVEQ_gRAGV-Ib_!W
z^r%AxRZs;x2ow^Iau`nguvmu=EMX|oA?gt%lO1~LPCaLINcDhdnnN4y)6*SF+M#jY
zp`McY84lfaFy)d%2yOGT9UQyhQ?A3L9_Z&eMEaobvcv9!Ao&iutr%#5!%b(nR_HL^
z4&;i%$Okk*4t=yoyXKJm6nZ5NztJ+I)WLNwnAaVQKhs(98xE6b16SryNjLmW2fqP$
zam!)N81z**ycdAhZ3kg1JgjmkqxDU-!(mF0);PQvLhFu$bvuUL?9fGTvo;3-0RbeD
z;TID|i~I_vI}+|yGAm=?P&G4}F0?z$VmCU=Q^#mOfYx2+iViXj%mNi!P0TtS@Y|SL
zJ(!P}VyfqP!7QeCf+O463*yP<?*q&sc3B){v++k&J_XK<+)AI>cxTuym>T7N0mFKi
z&xZDU(G>ife3<rXpYI-r-YE+w(^;l3tbT`$sUkOYfB8G5HK$!(hN+s~@HOCOB)kE{
z%>VU*Gt0gU%ClWAL*}bx>%gDGQ2u1@j!n>=_d^S0zCNZ#?|hqP=zg=N82?_t9K+-+
zEbjql(asY5d-1NB;4euWN%8-03uq^>bV>#OUKX1Rq2*U89<#!6EI_|Iy#b&rPYy@#
zsz`c1e4j1>XZ0$on^?0t9`b9OAHc13lgz<iKZ8Q`8$R~{XJbn)%>1x668z0q>ANOB
zuF*mMr@#EryTyqrh>Sn~FdU7oyM16_?>kh>v7bqMh8{Pju?s5hOfX%N9*hrFu6i=n
zIk4-+l+mlqoALb^!|`Ec1DFe6=3p{J4l*|3&}(F7UV<l&nfF(K`Gg6f$7ertAq;~W
zU>4CjZ9lu`Q+ocnv7^Vqgga|fh{^O||M&|gJlV%|WqPrG{ebaiYbjvo!>Xy|)R(QV
zguxK@5$$3^*}D|LjbR^C#4DD)G7gsF*k@GG8PEQ`9AF7-Djjb~WZUR6Kh0X40dx`@
ze^F$PTai6_2r_5bp97taGjAIW|H9yT_UpZX$zXk`crs1oMbWTy(amn^6J^l}vkcM6
zei*zUTKgExi=tWkfSoCtO1arA(Eyd2UlM&zwWiskp$vGRBl>(dP;y0WTVOs<bde4j
zUKYJYRc863eJi0*AgVUfCbv-Zitg(xBK?PuxhneYG_Z?Aw)SXU6Nx7Qtyr{$YJ5sW
zqi2DXiezsA^tveT8bof0w6kHUOq4{quyWBqE1`Z<bcZ(8w?yu5L7_qvOMBegqDhoD
zsubDN$-yd7+A<^bt3``9g4Bp6lIR_gn9{JdqL>-bs1td4LbP7Aop#)JMW+_Q#66K^
z8K%2IG@VXvG>U4eK&nZUOBY(R$TbrtT0~bZL0Uz1R7ck)danl_-WRpsL91Q#fd%Y6
z5ZSGz>b4G1=_G)5ipqST|4_7@URPbBDcb<rEjl+3ijPDWD6RQebeJkqo`~k}g=CMY
z@Iy>OuZW{k<fo!qO6@)q%|8f#pNsBMX;PoaZ7lj;h;k?&@=_ET3Fud%S(Hla7d^=r
z4^v78M3YBh6prHZEg(+fpun>ss8qT=2^y*5Z>g#-P5j3_Xrzmy`oKId4m$@E8DdMi
z`O3sObjOv8)9PXArg&Q^ByWiq(+5iG#j~lV;;uOQCM4U$?*@Y07hljrp+nrY4kDf6
zo$o`>U9zPM&>oUUlvnqZ>@ZqmXg(6#jhIAV$sB)h{UlrV!kGh-A^I@U3CSO;pm9O+
zJ8fw$O2S(}G9};B-IygwybkqCl6R=GBU_?g2NOAx59qSYmAG7i-8{*s<Zr$t@)LMi
zAld8&W}##mz45O|-d%2l{#8jv13HT&ANIlSHGKLVc8evQV=(%ACZE$sDjG~;7J)RH
zSOr0$$)xf_=r^0h(5s}yWQPq%tI5E9D72X@m_R>_$?!pV*k`ia6n$?@3ikoiQL4-V
zij#ER9eCj^y?c;$3f@u;m6Z5MKRFDpuk`-MaK=wsK#MSc>0FBL9+XaGKn_X86#O_M
z&7=Ru@2GSVt>y!yGb!{FC|!CQtzhXi14xLpjACP<Qi&%>q*S0tSE|&Sc6n*iFX&i$
zy3`ZZhepYHsdpAlur!Q{E;FU(RGgP3o%$u_;*yk`0l%}Qch|s~9BG&hT34kTXk}F-
zjiM|6nzX?e3dPc0Q@|{dW_JVSy0nXa!W+`Yg&2Lcv|a_bYozySm3l|I^cH-om5$5B
z4`ZyCem5Wbcco>t%DpF*t^-Vi^l=cdo1{A^;@m9#AsNh8Y1tIOv`M4rS<)_jnF56e
z(&INE(kZ=?3(_Uke+|iQ>9@3ucqA>NgLTfPdp5)SW2UR<q)3qIJ9of5Zu(vj%m*7y
zKcq-^h-u0mnlIB6Cjk>?8Z#H2Crq2WAR2C(_76lNO*d2nJIZt-)l{4^T}hGkXj3PO
z7sQ%A+65A4`s+tPi8r-)gjRy-r6rI|G_76&lr+;}w5v@w712?E4AXJBaOQ&P+zGh=
zy=dC$51C9;HHC^VnTFE)G~4v+c=Y9%2GjOE*L2AU%u}A}bq6r>O;1r`t-y2~EqDq|
zCkFb2<7PfO9iXMAYq9`#-L#2ffj3OuenqRp^h-K7(rG&IU%`>-8`?K?n^sZa_mSyN
z`fS`|QyIOYdQ4Z}fL^cZ@CxWXGo48frst+wiu??jPNpdI8`B+>4|J4$Yz|2$SyDD!
za+W<arUS-Bc0dIfS6QYL+}<zyot~s_vKg<@=PnyXAubPDAeHg?%UY=3{h(~;b6_8q
z^|wIpi0t$AAOSK@7w84b?$ZV|S+<Y1J7;8CdW)TtO|V5@itNev085qq=!sUE3?D%P
zO_xpm6b_%4F*NxZvc5)4<ptSFD(t@~yY&?MnX-@QwVfrCUIDoztEXd|*)j!1d~;;S
zc0fH>W+R5dJefeN@yjy9C7N`ZFYN#eWcHK=DwHk$0?=1v+e6WJRrc(^kAM`(%vQkC
zHJQa$h!)HKN0(lS?3*PZrLt(s?%$9tsE0_IELDU_D3|?~07q}iF3o~7w`98wkgSk>
z?hR*d%ZA%PvQl=Ne(Wk)MH@(sY}7hP-jUVQ-nLd&NOb^pvP{%O7$x<xF~{KWU76D;
zn7=2Bp+i*-vaje$Xp{wIL9t2Z<qBrA>=$P+TVyXOQ`#zvT@KPF>+OKS`?8N{OzpCJ
zv~YVMJN67<9WraGTR14+CxXZ!`H!DL;kaB=4$NTri~)?y7$WCrsU0d`Ns+D-a?Lb|
zhRb)+XS*Zh6<a_e<q=9KM#=Y6jom4Eh$EOWa?KLJ#L8dM@$xvi;#ZJ(xzA4kO_Zln
z1zD2Z<2QgM%gg8l>_vGcRRd+pgFl5&m*f*EOP+0%qYw~3iG0#MfR@SaX$4d+pGZ6H
zoAMD+7}G7eABVmQ`K))Lcw7ESI?yWRsVV5Ik{gRL!PWAb7}%|m57K_HS-z?nq($yS
z3%6GJ$$4nC$+!IlgZJf?^yF`s@20rq1G(|{TKL@||Hv2E59Kba!0nRDXhG90ub_&%
zM{*~6H$IksK~cje@|+_u*dwp~5q-UK{3nxm!OP950Oy(flR#iUm#@AFkr(m<l%sqp
zmj^@rmHh2dX!Xm#DhA4ceA{M_*K*ECVU9t$jW3!*^0GhCdL#FyRlK8FmK9ucGVA#m
z#Mvx^_6sg%$=lF!H5<mj;C{1viI^uhvlLpDxtk4-h4)@&4)nu%n=Peff{$4e?Uww^
z9_~TwfY~V}T=O?;jsWwZ+3)8l?0v{=?=xT@HVasa))BKCPS6iE>vq6k!px>ptoDRi
z_$iQZv#s=8jWC<tiB_c9P5SMl%+9PrtI4d1;yEwO!af3+qq+HJNIIEMj)XyH^UOr@
z-rVgWL|o1Pxdun~n^!NTMV6=eMcPJrnOARwi{9pSn*i!#{(2iU{LJ682Fw9-voA2v
zgXSsbU>-96E)*gG=FcwTM+-E6Fb#dj%q@4o`yg{EJ+*?(CvJjIA?9VY>JBxp`y72?
z<|n2=A>4c{t-MZ}&qBlqWryY^Ujj7Jyn7JlPnkO`L@U~SvkPQm%&VpYE!I4CJjglo
zd-SkQF`s`8=2OjoTMW0;%$?~qmTq1}B`D|3ms6=uhWR@$K`xs6(4C%XUPM{GZ1Vv+
zmXK?Hc{wEW%=3SNA>&PRC6#C2GM}S{XodM4I>>k1Jc&wOE6u(C0Zf%SI}^-m^8$M8
zG@1`KqSa*ntOtF~<}F4@wwV871(Y`P1wUh;9p)YlAf4vZS|Rz+T%Hc|UFPpo-O*$7
z*%at{VxC5I>pe#EfOjy#z2=K4>d<GNw-w}t`F@HJyflCB1Him8-&PDy`^{ILhou4Y
zT}pWI+PtX`<_FEq=#KHV_=<8-eimOphWY`ED?=du7WQ+&JZKTo26D(EE)RN#Ek2+f
z(-Di0=&m?wVQixh$OKqi{upS17KVH%9<vxpmr0O?!UQtMEuzvuf-NR2fMkfpD_Z}B
zS!}0@yAu}oMIhl8VtU%1wD`yx9!6MPE`VgDMFqVpqAUjQfka#EsKzA3SlpwXf2>9E
zexSrzylZ?5+ysj;t1!?+3kO>JoVHl&1oKH2nR7srEpA)`^NhvsqtQBRG4v5ean54*
zH0Y&R%%j+2szr4-)YC1}l0ZBxcT--$)AHnMNP1cR{vmuiWI5(v*gbCfY66YL(vFJR
zLoAzo>5B}ZmbJ8UJ7GD}2cCvot{w#Qq~-fnFcD#yOm$0<mOsbAe3a!vO2nVG6w}Hp
z%`#^%NV;WS1QgC&+R~?<GAzIR04ODvFXzHispXEjK)G(|KmmYC%Zc=Etg<{)1GlR!
zUEgPL|J7JtpjFl#%OO2vYAsvoDN<*-EF3P@TfYAopm!}LV`1W+B}0j(2FvX;;YFjR
z(E!ON%UvtseY54{tst$I&a{hcvph~I`}>v_mx0o5`3Xg@A6UkOL7~@jH3iR~THbA@
z_un(iO$XuWb4w2~I{Pd~Ek^5wr69v7URsvZZTQOaf*qLsmY=3ValrEYWH4V_&h5Y`
z1}&Xv4u>o`y5<}eF7)3EJ1N%v0TE|KFJ+Wn6utC1aaH^|8)U!Y?i3huQ+%-tEu*_4
z(*RKqMV}7(o{HP_9`aI1eg@N9k-ZcX?4wv&3iG~-MGr7SKSefWFb*i>R7>oy*g{i!
zP|^DueTNjOkzgKHIDd=QQN?R2Qw~t<{2L@t;Y8J1#}s?%Z5X8ZnPT_Hjf!7rBNMFX
z9YQli@eK!qp^DEtVLnXp4duDQ6$hx!_@rX$Mu<cx_EShDQt@pO`l1xmzeV3Eg&9Sh
zq7^<>ATf%Y$uJS8h^LQM#w%{pCNx1YYXK%NQL%w?9H$jtF+fRDD73$Wo2&??EyNkc
z*uW79_%iuVv{y=1%xuGNpRNdbfxh#KujmLvhT@hH3KtZ`bf;fbh(CqFOvTyl0L@a=
z(ew3^LP`tPD~fS_FmYAEtbsz2BEAeWb4~FNrPXgKCLMuDh2j8Jpxsui`U%WRg)tjo
zRf@$%N-$R|>aN0WjUt^MrFRsqInbz83}yhWPO+S7gX$G+Yhm!NVs-?W_Z0gmB-EgA
za0ObUqU{6}niN}SK%_-6<}WZ?732Sf+ii*fs>QgkxZwqbc14N+kp~KAdYyDAT#wMA
zv{SK};zbV?pHabkmtyW5pmi%U-vRTHVvs&s^jHz<4UH!XIo0tzRajCi@0nueb@V+~
zv|NKipJMoJkQa(M9uRq{IO7HASBd~{476V{A|47(R>R1ivsHK)d~&fG45TkZx>`-Q
z$C%u#_R(^~-Rf8~S{_!7pTMA})hb#icv%HdO4!>fgkI)8R&zf9)7NS|l|=bj8R<i|
z2dr9MV9DRgIsxRMRo%C+6l>kUV-WGy)6IdIXuX*#QIf1PM#7mh)-osgu%(i7)(`Ta
zk!qboySa4h)Bl5|i`H$FVy&`1nG5}9>wjjWuf<xIgjTEd*dNepv))U;$bIW^??b)a
z+I$=IdaR5516@utBaFAGBx}HWCG8qsTl-TWVbIz%1<WDq04g|oV_kd}8ji{#N{%`y
zD+ttCxn6}U$whf=2^4&k*F#{?S6MU-D8b5;abSih?;gX@!j#4ITt1<U>4r$SGH*6o
zCzUfkf@GvJ#rP$SRM|!8^<-snEbLxT8dE_oDy3^+FjIMH0z?Xx4J$ydD1SIYSFmzn
zC-jSyvuHVaP3bxfq*%E*8G0qkx-96GD!+FH^SbiR@34DAxn~ndnR4MPFw2#PDPwt4
z**~3PjCINhR7YN~yh)3YyUJ(-MtDzI<pqrfW$q!g8kI-s995IDf(lZam2py#7Ue&$
zpx3IbW6^3;e&2=GedX6~@UUIEeK^z~C`X!r*`ZVqgKM2iV<RLVD$jfavt7!Z&*{8$
zw=$7(_K%b)RKM_8*~&rjiSlV66nm5gO4Ic!y{XRssd6nH!F#5>w;V9fm8a<y*{A%M
zN()~o18X7jQrTIBzE{e!T1fUQ?GK?fplrGf3$K;4C?htgd`6>o<dz`}Zj?B2CBp#Y
z%#9lc85eHl7!X%3={97JawBd6JAmVt0{a*@l8*HSaevaOju37@jkyfvr1TmL<F0%U
ze@}25_rv>euC)@alUx;*I7DzS6X@6Gcs0yNaYv|z;}mC3-_|fjbEDsfehl~g1nkCg
z<GR6(<J>5t9nU?#i&g^HDS@R#&TTlHInA|GG$x6A^54h6xnY+ed4`*93hcAoWHX?g
z<CX~UK84$~8?99CLnol5abDkGoavmd2|k_Y7K{W+hLN+*fanEo`3K-$<Q}J@mC22v
zDzhw3PnAlSxRKMKpUquxhDHw8*9_2H?lqmG%Htl`!tQ16(FqJ9pUb@r^#bm6J1iA)
zpX~#=!Yv}nt6buEs26c-??B`lw}-Nd#hmf*YmBLcOAbb}l(Q0}^E#K?2#p(De<d`^
zxLz-alymdwm35Pwz(evD$4rGt1vf{DnYqm!YJ>Sou8!<haasY)YOYuYks5Bf3)Js$
zvAaNOIcGYUQ^(B>!2s*Ib|Xdj?{acFI&qJyq473wYf3S~M$Up_s!iPPw*cDAEuzyT
zEu4-bQ?1-@6a{VLS}9$9pIbraR@%8Z+7><FCR9VAgM0oM20OX8&qL%Pmq<aNF3$BV
z9PQ@D#zFlNx4OcJF+JvnHNcxET;LZVJ)CVCG<vxZN~JyJiZp0F<G!ba%X2Q4*5ZBK
z>0NN<1?OD_(3f0)87#fxO#MOnIVlBK2DpvCLh>~yTM6|+ZvPcX4skaUFx)rXycnoE
z@_$XC&5jd)hpJ1Rc_sknUHCJ!8g}KsT7}kr{@hJC?8dvhqvg&|rqT=#zP=iuo_udP
zeDdN~&~o3KPj!Nx4<FqOOTPSIKlJ?gM?Mfaz!%Meh(E8bgrS3c&{>Ea;xl*CX6G=U
zVgZMb@L%4A!$<kezraKQ?@CoyfxJD%8jtbM>EwJ6KmGuw>p1Un82Z8dUP|_a@TF8w
z6UyH{2fZ-<YA{4j@D1O=QaFF38a|!mC(<F92>v#un<M!xw5*Ear-VSnc#2<2=O?3i
z`5Gw3@cZc;M=ZbaB+%mcIaI6`&#PuYB!TazRCXetNHcqymkx&)NxaL)08QrWDa~_+
zU;GQ0XZcglA##qNS%bb5{+AgTU@Bkk2!m<7j>4Gf{I50;Id9|#PC_Gt|HBUC0{@gM
zG%oUkG((xZ=mgAX@zWjAy2SrNp|ouN4t-i6hu^*(B$xl;Cn)6c-~SBB%lxv>F;DsY
zx{a_@z$+Q}RLJZ5(YnI#af8BDey$G`ig=e1AlG=K?{3gy-kefqCA=;Mb6LuNa26WZ
z`GQ1%-r$>D0aM0LKZ8+}^ZSy~y2(4yeSeD|Mhoo<{=g>~%xyk-2<9t!e;G&>zxE%H
zYJSmGfYtB~^boqk-@OV$wY<$l^wsf}MlnF^d4|eV?()0oS#*zgr*e-5{$~nfHu5Vh
zq0z*@`39|KzI-KMTKJw2=(qCD6i{g6SJGPkK5sh@eeHZ<2wZ!>zr2jT4*qlc`dlY}
zo9g@@^8HN!>*ALUp|6`aJT(I55ntH?{l~m!EIOa?$LIiZ58t&OL+j;#rLg2vzNr~~
z&v=U@z&z(qG=uc<F}vXJ3*Jlzg_rzj+9bW=C3Ic&^CRh*Fu>244$0U2H$Q_p$iI09
z_J;VK{vdC7?+f(3EJwjZ0T?Ht)f@($g}5A`xd_?$@Y_{*VGhy#LKfvT+yqe+`rL)9
zv^4e*xQD>@6fF0^l9#ZAl6u~Pn<<9oBg~tDA^8gFRN>?&jH4~>0pTbWEcgr3{a_vx
zQmv@Q^^h?0Luecp)=@p`5h0L*6-R|@WsnIFWE6i16nX|hjtR~5Nv<FvxDL)77p9a#
zGFbS9_R=B3p@ZlP71mP7<FsH;CxMcLkC(#HWPzu3(HWtIV&-Rs?G&jwCoH3T#F!#D
z(k41pNT!8gnvh6u!*t=613W!1{Exn0lObSFh?_$=6$`r;g)XWH$rLh50h%TFQeyOy
z(C`8Z*@EH?Oyme1dXQXUs~Z&ZgzL7zye!<#fJna3AA(kaP*9Clp;0(i2ed1~H?(fP
zDy*PQOOfz4J?yUuZ8Om-7AB2>i4wtm5NM@B;c_Tm7jA3<%nc#vJ6I|c_U(tG<w734
z&29=8x4^Yq!m9|hDuko2p>SJ>wuhlg;cJSxR0%CvfUXvd$+S7F5sp*1`i}71Ihd#w
zhEWWyPH4`@u<M1jW)QtAWc&}7?g<6<aI``AVGa};g$}x#n*`HiFwrbrjYMCIFzY9{
z)+*HR1X!E!^;C%57ry!dt#+a4Hb(Y9Fkb_(4q=p$9yFaoGDRXD3U+Ux*d@rdFxV{|
zdIR!E2-*QJ9t(as5P2e;dKY8r5xn;Rv{y*Jiq=!%!6DdvCWJ?#^;}TX`m;|6SP#7y
z!U(Fydnu%kgZWoNw-)yLh5u0n^?<Nu4z0vq3m?7*nL#0g7WhL#!l$tGMi><UXB<_d
zHeqN^DyuxSoK;`as?tUE<X>2FReeOCQrNH3#iHe=+DbR9yXsfk(R-+3J7B_7<w!|A
zFV$muLU^lgWdhnq^&4HlzN+c#sK&uhRZK6L1FBESuD|L`63`B+ykDbrNL5Nd%wbg(
zB{hzyei{atqpB*Z_z6%wC!YdUQF^qFsV33+xFFS`i5SFj74r>7AFP^b3J*h6+vx!l
zs+vxRZNpSye?sJhYR2+mxc|acrx0|IoKzj5YUc>myg)b{sZx2sizwBnwAVVN+DJux
z(W>haXvL_?|3P1@>g7)`5vTg=9oUUmP4ojvP-SI8GEp_3Zk5w2*JA)nQb}kHk*vyW
zfrT@wd`g9$RV7b{GsbhO=!MWoQRzlNCRMe8Zih6L{v$BcRnO>}JFm*T24;q8as?DG
zs6L<rZWmQwQ9M3Vb(R(;S*q#uT)(8Uq{ArLsxO_<m!ndeU=DLt!@odZo@z7|nO;_v
zuK;Gg>Rt$11xD4UI$#&7w3gsrQ8`S7;#JjVe+;ciHAvXkRPQGOrdU-#d5;oR*M0Pr
zs+Q3U=(;Lw00wWUPEegpnMzMrce!dfJ?w9)gh8}!shH1UzCv|>DadWr|2D%yrOKPu
zk5wvTAw{98ReQ|fO^vFXewjO}?>#Y5wJJkCe5zBWkB4Zz>hph~e^=EW155W*!C%5e
zgDPAKy++l=_ux~L>ghu$G^<MbfYPEGPv>k}RWDm%p-nZBHaYiIe+NONU8RnLg$F97
zksi|>DogrkU#DvRGjJcOJUbxMr3#>}M7K&&0`rellh1+qSXKWFttYCcV`%lLg1!Z4
zuWAmhL7u9TXcPTR6+wsCo~w>TK%`Igdm7w+p&DvH>!r%h1Fcu8om9TwuUfQ%B9{ZI
zcWKY_TJ`RD$PB7tCqiaOwSu-OZ&V{zLBvt5l)*zMbv0$<oz=SGXt}7LKS7_X`hz*}
z>4<t6?N^Vg{R`0-pthcjzCiU$%4Hr?D;A(HNd0sWBv{>l6bd2g`H6JKDpWn1;*nwM
zY45`P33X!??1rm<+KJXlwRi;dBh-J;hb$u1Gxx#oD0KmWo>Es)Y&BXvg94{9YX8qb
zV%6Izq#UQ-m;i-%^*f(JGC`f9!q1eb-b?|x)9NZ(5+td!_EL@O8MSmHG|sAh{sK9t
z{-6V(De6cYSV~nd?*~a!AEPL2x_Uwnd^)ebHXPHHq4pR7$qVY+|AW65)o)QiJyYG;
z2<$BN`uAb?lKSf%=*w2yOh#Xhx{*r1a@7*r+vTbMdJGZcWi@_D+z;x^qcBmR&Q!rf
zp}Hjr?q5-xjez;9>IbxCD^jna`nzlDA1K6HtbRpn(-O7cmmsC;X^sHBuI`x!^EcE=
z3b>Z3<7sPJuHF<3a#QUd3+64gJ(ZJIsJrQ0`fa0n#VOEA^}lqov`RhkK1@`rs}@1D
zMjdq;<c@k5ZOm)c?KJv2bq1yS>eZWO!l%3HNwhe;r(PQb&<6GXF?2hqoz4NXN$olb
zJ~gZR=7F@RwNn7rs?K+ZGi~Zuw8XrxHoCV$qg_3PYLFhNgI7SNLp?bIXr1a%6)Zhe
zpIQlKmwMQIkZyI(J)k{OD`_|QSlz@y{fT;t9;8S8=T&&vtG*Zv*Pg2XqQef))Zcqy
zf}X2usIZ|=J^UL;zEFFOfQK*Dql`+}eWgB1OU8cnFZ%#Gpe}d|GOyKxRAe@&p1&KS
zL+b1S=)X~~q^r|W<8}%jI%)QNf|j%9Ct8%cXb!8<a@7n__Hw`G-8x{pY0grOxVy&D
z9ZV0+IR;Em%^go*dTHzjX#MG}iKS$hkEVy}W_&eMD4FS}IY2M-1Dcog@blNS-+;(L
z&1Y9Im_wR>XjgYw6IY48Bbq%F<UgwUpdID|H16bKphkZe<d|mL7my6n92*by<C@JE
zF^9pL@OLo45RK#$s&Ng~w7(65VH$jk1^1ukuV>H**SuW~XHIIG1i(aSre{MjQu9j*
zT2Y#xdZBPi6SEktXiX#)S;c5-m!K7^`D!$Liqn|=4v~0`Zvwy)G_@3@Pt^F)d+4;r
zkJgAunz&bV#yDAX|9`+fqp95nnX{TM+Pt6B<UIgdie|)5=u6f3&{Ho>6TBY!>6$nN
zM9ypW?FBPK^KLy_7c`S7tawqA<Bkc=)NHs7y)2FY9XNAIb8HU`W^2Y!$yJUfm~v0K
zn%>i38uK*n5wLVwQxgreLQTR2w618z&xdG{rh6s~Uegp)ytr7ipa6;`n#f`dtyJ^r
zC+NGbSx1-U4UG+@>dG`H=?5*>EC_)5P0eAt)^BN+iovYV-0=aqt?8v0Nu|bnKK!jR
zYFG-ARBP6608EX>|24RGG~#Uh_O+V)!x&7RCgv-M+|}Ip4$ONRhJry2n%QC)Y}7nn
z0@9>8lnd-;P3Zxkv}iV!V-T&HAE-#XO>>R{;`cQnR5jPGv7}O>2bwP_1=XQ3)_nzT
zr)Ji8=s(ol`wPBxY2Hf*>DJud1kpztKUz~i*0@_j<cVhDO)z^kBk6d<Q_UbP0H0|#
z_k%pw+^37JPZLHl*%z9MYWVw76H65WuQZOdJ?Ync;)&LPW*L>;zt;E}DeyU{vH1>)
zLz=xU;J(p>)3U))d*&rZ;iPS$)q}Iv?jeYacJL?kxoS%)fW2S4lWO?fw1;NFpt}~;
z6u8H<3G_(v)M~$gK`-sgBVc-KM?J(`_-K7Ypx~=LO}D+D*1Lw{F9)>i{@WL6U*tjY
zpw|33n1{5-X`OLc8#4|b9??F02y#?AwE-RmXg`$0e4zHQGfW)Qeo2KkLE1muAaY!r
zzYHW;`!>~sglHeo#TKd^_zJ&dn6`^DXD77p(~clqn-enZXWV1jZaP*N0f%8eQv1sS
zw4$_316rrFlW9!RTGX=Q9@BnD<@2%Hz$n;_)86_Vt$6Lnw?GoKjkMZH)aLKU&`xWY
zT7V>J@0y}7S?d_Mz5tayTj#*hRBhA*fTd}_Er2uW+As<$oY($Jw?l^3fsV&s&^GOd
z*^AoQAs9=h_WA{&WNFXG!@?!)+L1uX*1n~IdXDyU7cg_RJx5_LPdl>+(3iDSqcKhS
z+QlA_EYKcz11Z!_Gp3{Siq<wBidVH`&qJn2tM|h=uW9?@VYgVjIRIXiXy@j`e5tl`
zIa=4XL5>i)p|#I|r84dG1n8A(=e`Ano7zj^aP5|sry9o!ttJ}&-qu!|!C<A<NWqvY
z?d1KCtkxb{M2npoZ3Wec-_id42B5XtGD?QjX)n%1t6tkdnZCQ)r<6~=r*)^8YJ*l7
z1-(XXKK+DE+LUpSY}Qs$io8V|N(q)$?beYn-==lLR}&;X+8+9FcCU6u92A~v-<<(x
zo@qbZL7V;O+7a}a?9<8?fV|M|rnTiu?ccQ1d!>!Oi&no@=tkdw_7Rm~zSe%81%C&%
zS+xHe(pJR-?X>O(OGqZ^R?!uEMwj_1260aJn<e^Ebm^h+B31W!0hnpJ&?8``>)Nox
zGfFaa0g3SYqHcRCxS2XzdedFfZJ~5ewyyDaFmrUXtmzlkdC==5Pxq-k&@StSQE^JX
zE|u~_1v({F_7v(yPlJi8y44iTEYdAa1K2g)SS3VCbg!pDuT&R*6Oz|;8%Kj_yrEM}
zfkv4wk%Hyry25Fgp_{tUTy);jby7^VLbrm}w6}Gm&OowK=Xf2hDxE!5@K)<Sr_4x=
zE+Q7pJGwt;Z&s^Iy8;t+x|j4es@FyB#31hKrvDAed%EQmc5TqPtp~HwsFT~ksWzRQ
zavBeGV`*jHp_@c0pibSuWte}cn?=F>F5PCjsk(Jz=#wIkbUThf;j!-TwUF%5S&so)
zukP*vs6W*`m<jSsmpcsV&vl=jhe)5!lZD+Ex?%++U+PNe6vr!_@mnfU>({-ZW3>ai
z(?`*ItqUlDi9y|cs&5$5y`kFvH@e~(fN|6(P^FoZ{;QGbbJlnH!IF#qIt5Hz^~zu1
z(|)~gA4J^r-x`4Fu5X!%J`ep0%D;K)_u61AUV6_;Sn$@LG9CxlM{h#8GGF~HT2}e#
zf2F0*0sScY42QqIZ8ty<>4T`8@vy#!zL9Z6znPK>NA-?Wc@?1F-HP8XP~YJTkz;yO
z3W@~jZ`H!mas5wJiWjWUSPQTaed>?U3)SBiK_N`PVH`zqPUuIx2hni-CVG3H)aTNP
z{|Nmj&A^V*KTp7XozibvgYib|vsF-t(W_TuN@DfB6nKo+Cp>~)qW(U8U*WXAkZN&~
z^>cm%IisJl6C!8z8?#~eoPIQcrRaaBO?Rq3vX+vV>H75)C_1m7{Tn(n^u8QAFX)3Q
zuzXQ}?H7P%>SrFpn6mU+z5vW6eUu*Nv-MBt-p<iC)PtF;53+?wp5C1@&zJR0%K(<I
zUmps|0{!X}U>52d>@bKc`Zl^QuIj7P=>99xZ~6@|*Yp!8#8RU7p-*|0>bD$*#&!J*
zDlWO9m(i)FGQEbv)aCjr4wG<GA6E}%zdkVumfUT&Q&is5<{Ju1df7y{p)b(p*<N5C
zx4GR6%ut)>6r~QgIrlEqBW((1LDCp&vy7%K&L+MVqVYCCw2?`$Suca7M4O{-kU4Gh
zWInt|vN6&dHrb|g6V0rRI2SNyZQN+xdd}wD3`nNfG}Cma+BDKBpEMhO0x-|p%vlbR
z44b*Lz`Sfz^9c6xZOW+*q|9jZEuFzBx3O%6=uI2jA7S^FO*5^aDr^#dhBLQqRxQQQ
zDs3K!L8@#P(_66GW^WSoYi#m<g5DjQ(U;*&t<B{YwCZg7{sd;d%@sPAde^443n=$&
zc1MHRU^DYQ=r!65UxcwV*%-HHp|ja0l$OS=HXZ`7+icvjfaYTR=VLHkZI{vOe!s2X
z-%xb3{c|5cLu^BqK`+$y3?*;EZ0FNX;DqfIN*jjTPMC()N!!5>p&n@)MLXgs+og19
zG}_kVDo~PbBebw^#x~CQ9OFG}tL4yn&i1w|^iyoVr^rL9?bkQZO0yk7YrJ&ZK8k(i
z*#1Mg`CQv5Z}jEae)tYZiERb_6s5MkD?qN>eoLPcx?wwulH%pIUX)zBWjmENkrlR?
z!{N+5+oi$qu)$V*#R$+w+liDaXtFig0!uBnW~%|yYKsFFc!=4CtOc{r_AM%xePR1q
zBgXX7HurD*KCf)k>G3>ZyLvf9UfU*8AYstfis}@GY!B{(x})7mdZ0Sl<(EOy*={mb
zEW6lU^hBSl-RmER;r`oi=S-izb+c1YwV{U{OI7loc71n1yzI6(Vlduz=SRbDAG_b1
z0pn}Oeg{i_c7b1^b-*s47H|jc9KxV}$SyG(eTVI&R7ZKl&R7S%qjp^kzyj>fe+tP!
zyJU)M9kcsv8-1MqxZPiN7+SDh#COmLwX=vuXPDiiF98#67vX@u7`vym6pyp}h%ShD
zyQ%cJO0?TM90N_V+f94mWV?tQh@7#DqQ%2myER*2@SNRYTbNI=J4{c3RJ)2Cc$j9l
zmn!+v?V2uv7|+|?`x$5%cC&xOBwVmFu?9EOu3ZC-0=pCRv@W#ks6p$Boz+OVf7Nag
zJ-dtSvgruPHM<bHE{g4(XjNBg=dvCs*X@3cM&AuPvuo(9vb#)S#A>_Yfq-tXdz&g-
z8|}7IrF4_gF8OQt-E6114^La{f~Ue@tDRRT^xNz-bHTiCm%9rv?RG7vVg7-gg&z7H
zcG6{FcG~TxYK4b(Z#6-(%PxN}yzn0`d(OfX{=E0iK3EyOax4BG`-mdaF3ecEJ6xIa
zb0GVTOyqxiV&)cA$htF1C&+j(aY0b_WYXxJ<Hg*eAHkcsw_H5TB$zR!MSL1FG7g@m
zGnKU4KhFeHDky_#r;FwS!-b)Bk(o}Xv@)4L@tl=pF{&Goyu=t~(933Q*Tdl)#<+u?
z@43uKTKMKMd2|B*GShkht$b!KCHD%Lc6$AnFz0_9Hq4}*DWa#fD;r1=-u<jV^|Eg4
zlR+@u*?tcwc(6ZaqvgqdLFIE^?2q(%@Mc3P{^`T!%z%O~yEX%oeypAG2VfsypHT+e
zpOsO)&_T9499|q^4G1QgoM1;G;bC%{O~F3f1cyv$4dpEgY!nSMIVjq=2-pFlz|rtG
zSTrB!rvIDv$wO2NIc4Y(aHdWTgv^(VXfZwAB@>(#izmSNnho7>4+k2l3~{IRR`}r%
zOF?@N<`X(j;myQOMC&~Bm@c==Ofjm{{sZR=Xz@EF8h9T@--tf8hC`0xbEjwo;%+Lb
zJ}4eVyP%WOPw6yFgtUMX6OmGDDq)L~&e#a`M#YXgh_nw^wDth@k-};gI-e^R-Gb<A
zMdfU?T&!xx1imR}bVi{cD$!P3RzW4kDt`<t##$LE8y#o0mxA2!Ru^bZn_x9{8-|%^
z)p`r#JZ)9&4(uc=&IcsfYE=*>BGt<OS4d`BJ@f^+Z1v?LfL*gHrbu78)rRk&e#c6~
zqOaC!(K(>hS)DhQqgijI8V&Pzt&VO6d1Muw4CZ4i*IQ^kv3iEUp`^#E;t*QBR{N4*
z@Tt{8iefyo8a@SfpIh0C0(PI(B%0$FR@z+<d1W;_66X7@p3u{3z-n_Jn6Ir?F2j%p
zt#;5-c*x4}2_@6tSox0uwxjh~ia<MAuStZcv-NH|-r;Wj&liC4ur8r#_q1N%21PIH
z1%rU`w*F0w)<Nsjk3bGtuiA=%9=0BL8^6pE>*=Ymd(>Lp2(T#Y328L3)?4UR9&f$4
z5(;Onr;4c}C)GNv12UP`@sB|2txrru=Ur>jV~_^xl9M2f)_q$*TC9)%gJHK?FL?)+
zURkg2!DZs8v{l2Pk5Wu4d0(Z_1QMhypgcvm(tQ@(j#2Kh05eJX;wjYAl)67)C`+kX
zNfDuZ<#o#26)UAO%*9RRG0GL!DD49v+MrxUVZ{5&aj6jLR&Lk~yU&!*{NT)h@^BPj
zoH>sY5Kk_aa!p>GJH<r2x#e`g$cI~sdr9KU_0mSdkNbn(R0p_bDy{VATx!uW9^?WO
zA#;ce>%<Hl<_=T(;0QON4V_21=&?`?;HE4AS|C?a3B_Zac^Q~dTqNDtr?{2HP>ALR
zsSG5BJ4t6DV!1*ZOB^S30wtb%MMY={T#hXy6FE^b$Z75Xtx}SV+#j?lOXmJ}3PU@?
zy-oGUXSoh%7(B<#r9%`cT=ftPrg5*2K{B0dp)}ZeZVO%c8QhNP=)1t}^9H%d+0aWg
zlY2r*_$+Q3)v#US7Si#9Y%Y>^k2ze{uP~I$rF;y@JkEGD6qYV?Cbz-O=YFRu+X8Mq
zRb!QNCb1Y(HCJQ=_C0Q^H#FKfuXo^K7q@9Cu%B{owtzXn?O6ou*W9f;kR0SZCqsRR
z3%H8DH(d9hkaXlbG6C(wJDWqqm%oz;Xg~h0@k_`Y;G50>)Sp*TDfmG?uMRVGnBTD-
zJ{{qU4*~5c|0NYr1@NDI3&lYGs1&VZd{{HcN&dMEA`$%5lW0Zqu`E!c__Fz6p5hxC
zfD+A5rjI<t@BzJO#q#g7uouruV<<?Fz@JKjMk2p@3MT3_|4kyyC-EDoASjuCw+o<W
z_)q@?Im^#42IxiJMv3ue^8eD4H=AEW=R$J$SEE3R`Tx;Z14{UjHITf{kNg69H~8Am
z(5mL&Vu4x1|3QiUT7KMV`s#QcA40ckD<3!l&b0AIX#sbiH@1Pa^AWu;@qnKh2!}iP
zWD0I{@|IK%{E)|?Ui=iiC%vG%`JZ<};Snz}ho#5-sG0EM3EvfqRuAvrjalpEmpB9E
zDR2H9K0W7GZJ<p`AAgQ=axZwE3bkMIo@+r~@kwJb!hYWC1w0+#^KZk_YknS;)C}@}
zUI*F`FQNtV8$OxV!j8hi_0V$?R>nfaS@5LNcNbyB8|b+Tkwxh96_Vct(@(IFLg9cg
z_!hh{`U_6~0PT?QU<>`|!h~1g9uX==!qcO|Ob2)oA^b&Au1MiCT24g?bFQOxO0anX
z$!Ouo34q23i>IL#E2L6LC{7qgCu`${e^TImg7Dix^d$=K$AO#{T<YLVlHk+<*OHBb
zg7&#*gfx1DpB3D~A(JBb(0_1~Djax#R+^AbFV%Fxg!;}4PyP!;3x=PdcR{##8jfBR
zmQuVjQ*fxjbY}@UZ-IG9xEu{HvV}QRH<BY1(GQv{99{qq^MpH}fq7XlzB39MWx~`@
zm@gM>=u>vLgokIKSRq^=17?+AMkoKPh4VC*-9m00rt6V#_G6F%;To0=NU7(y!u+66
zOXpyQgvH;1`9^Scg@U81Tn9&;R2OLJ@2skS0J|=#vnw$(uBr^9BMk0W-J+<Vn`+c5
zbh@jYJ_eeHY5|=z@KpI8fWDXN+eoy0R2(gNd{wOqF#S~d8=!YUWw8X<{;KKY(05Rk
zdL7t@R1rvkA(wv83d|#_KPiWQR5g#*=K-pwAhZHiIu8m(9aB~2K|e?}534{V)Au<6
zJ6Lrg5bnpS>}kamr`q)mnDHuMBU%Zn)o%Dj5>@}uXDm*ue*FaM$*MK^uzN=J-5`c^
zRy9P+&2y@}N_df?T1C~lsj9=3AmJbGpz5!4AEx|E#}86I45<K&$4A@O!$i%;hZQi<
z^l?cMU<SuUQ`~ZB+}T7h4~_Sveax}((e$_q8vhNwa)QTur2;K={Md&uUoif?;Sebt
z-@ODPrQ@UNPH!LYM62!CiErKczlGK>7yRM!uVr0Epl^>HhrfR-Q^Jei9UtTGoj+DV
zdskQ>@OKweS(zhKL~#Nqrk6ga;LMapLcoi;D}}T-bG`x|_%dF!@;u7Sp9f|DGlf2c
z5yni70mupF+aVe`bIu%nvCMr56yg}`7K(_+Gx2m(DuH=38K5alyg!YHkvhRr7W4Bj
zXkB6!(p{d-4Bf*V<uJkqw5~BDC=*@GOlt&a34?>}7&5cA2z^xy_c6e#nRrV~Kn=5y
z-cNU!d46CvF<(%=rkUBcnARUH%!^X!w=%aTV1#W<uQx#NGp_H$?{?<qL-ajh7L&sr
zOjt7ddYEnfX!SB{>DGVBlu=CV8Izp>_2<lT6<UJ~M@fPqriO~d-Y{>@!V5>XiRv?)
z*tpwZI<v>HQo&bO*y!&e>dN*I%zn182rV~uJ?%r?*~U{a@4<e%7TBKbTq?r#Vq@r`
z>dlH5LehtQi;7Eq+00(}>&LE`0CIqx69VGT_R$mXAR9)h_CxGmS}`1EeY5~O!bVXV
z-guP#+!8VYY%(463S?LQfzD%W#u}IiV!Nip)8p(WTZja+V}jsQ2y43-lNic=#(){d
zE*uZNXch@wJO){|2+kz4cc}dJ44abzg|lqH07TBQsdPl~B0EGo-Ar}`#V)dp?A`@{
zxy0IThekGQ<q7>O?A0ykyvja34ACO?BZ@3sV<+y0ela_=46c>1r}jXhlpRIU%{q4M
zGw9W`ANm9AE<0*7^zN~LEP`GWTS6<zR`&61D73Mm{!qWqt{#U$w6n(3tLgV;pL`DY
zJJ?bOXmqlD*64i5E~b2*qe%KMG~7j&6dLmr<-ZGqM@2((!3+^eO<*umWJ}A_1kn#v
zlA9<Bp_IdEQOF1IB1!b=0<@AvkN05m&xmyR)DAvMvAG!*E{RHw47k~%J)_}Uj%XwW
z({e?xY|xn}TB3pZe9?<Z&?peirietL$UP6_is(Q9oVhA0`V-hiqV7hh-xitDTe40x
zM3oKAqG?Cb*CD#K6U-+f*)=G<5M89;+mL9<dMLPw!vkpj?=HSa%MlN8JC#j%il5(v
z2`_ON?a95xZ}b?2k6642tz+V7`pQg@*oux992fub0x-ei%1t04;u6Xeg^K;Zg-DqA
z$aZ)iF5W)^c2A1u-2qC3_zS9hjugK`mHbiS<bNqhb4vWSiY_7X<vmb5Cw@o)s|(`s
z6llv8U;7$9T@??Wg8mKhM`Hn6Dc(yLdA<0$DHK}7wk*^iit8v7&?WYw!_(d3gdVgW
ziFMxr<*|4x6{kHB_tS^3dc=P^0Hs$P@f`(ehQucp!NoV?DYVLUl-#BbzLVr5dapW5
zvi||Li=;9M8m^M(zX5c=<jW+C-d!^MZ}fRc4tGG(Q_>O#XS^hJ?}B(sme9l0N7C<v
zK3~ZJipTg#hEX9{pyVenh#Zp?m!f41l1zyO%yG#N<Z!UW<si+aWV#U~RB|~6q9-H|
ztRNaLS@sKHPD=KAVT2KqN{UiMN+#`tGf~(90Ogb<g%YhvlBsnNNtT$<?SDpcayI(T
zN&={|@0{cd%4erYp3%9BRQ#_m>3~U-I8%}KdC7`Nn1l>TB~|ubkc`QO-HVd!CfLoC
z{Jsz~lO-wi2ihgc*PFn^_bdJe%vDJR3rj_kg=tW@Cb>@W^<qhkFGz`G%+DaDl9*kv
zdtI`#9wIj+|7^uiSSB&<p91}xlBpD3xg|L|1|}*b&#40JwqzA0H7g~56rxonsi4DA
z)sjyZ!`~W73w<}^4!&dz?E8qRgS1PG;{o<S@-8j1J0xXU7)z(*4W-2&;w&7XyCwKs
zAg&9^?EpwVmi%i>gv=9(J6&Eql9e?O?Ufv%PdB`gTyO`|(PWbsJasauq3Ei!$@0U%
zb}?DC7k#cKi>E++zsbrVc<65OXcQzpOosOX+tZ|RE?QnD$+QmlHeo&krjN-wd$fE_
z9K}#LZen6d@4sM^`pXzhh{?6bkO?(exe%=|lVm!Fd&0zy9);m1!zj6V(&X7;co=Ci
zuMpT#CUsJ@PMOp@04>^N%u3jeG0}g9zF3n72uw=iOo9TT7jNP~>88sj><av@`6h9c
zWh*t=SU~IldnPlUf!kp6>%Y(#G}&DVyRp)PROVP9y+(!Kh0;$CfLSlyQ2}Oy)RNM#
zozk^$!?hmi!Hdv)DK%ceT)dJlI!U89Jyiw;FVn(j7~m1p@6urYgsF=oM9!KDFJUjs
zv@xIFe+8zKZULs=R6-|edQ5c@Xt~RFQRe-KYzLi`ijeJ9z>71oQVO1@$wF)(a!s~|
zmY~J5!q1`SEjQu8^pjuw7OowT52I_{Uw(-8v4`XtpMiN;zLaX6kIL2Cpcf#Y(hs+d
z$K^IuF%T@T9SNBbc}5Rp!sJhb@H?H5zi$JBk@CtTXhq50M?&$GTujTNSUGPA{RH{(
zU(lB%AGizkvvPsnSSfO^@6nek-@O}s>GIw%SU4|lr3!-#`QH@Fz94^#?(h<$JmziC
z>+&&Gn3{5V42RANxoZ|oRLZSs(OE6OPpPas@?v@f*UMw+B5jf%>w}21Svuu=UCm5y
zqUC1xatrKwm@x)Sx1X8k9!UC|-KIj>BW5|{pdMg$<rStR$m~-({1swmeEEWcsrVy|
zb->>%N+?J4-6t#H@yZYAi1DgYDlz^3-NWFo-e3a6HB%?z-)na!fWJ<f3)J;&1o#_<
zZ-Lp3eWv(((}Xeb>xbfZ@b~6k`i{+ybI-$#pN`Yc_2*wH8)&%nFa56{JJ-+)Zr9hx
z0kJ!WUf>RqUjuYcAuYD{c}~E;|NY4fK*ndg@NXx^pFzW!v7*X(7iRw3Q1oTqu7R_D
zOa(pu4=^^LqUFyV2?GgYj!%NfapsRT01sxG5p9(uGk-h6E8}^l{Sl@-hnZM{L0x5f
z>A_vbd=)|)e43V3qw)6%b_o@*g|ll40C<wUPZ9YDcFYMFi)8cf!qHfE%|bBa*mvlX
zPhuMzU^AJmr`m!utUnb?rm?T(Xr;3czX3VV&he%3XRx+Apnr)y7YL1Pb}pSg&0%XP
z(pJE3{T=2D*-KPPb%j;aty01oy<xYM6;oZwP4*kQJZ`ah*Wh^t8%S5+ZT4>sMDDPk
zeT`NvdyGCDQ^&qTC320dixjOUR*FT3QPRxn-iLk*oAlo*n4Mn?yB+MrvB2(RM+aco
zkJ;}E!F<NPOA(;wY&fO!``G&3&>LV^d;q(Sq9l5<J(c}(1k?CjUWVk;fAcrQyhV@L
zH_RlO9Y;258eDK<qdYJWXV%*IA(UO%k(Xf2l?_b>+0WirqSKAtNacO*Y#VJ~J=iu{
zY<sec{(H@`^C+t6&Hj%LSopBh7Qm=4JC@#$erzLB1Xuz`yaSOSw*NJpJ<dK%MPD%c
zGzWb#?3^ALietIESpWS0pE>g#xc}Yr4G>=W3*Eh|exl;U?;lCw%j)s8gI~jW!G*PM
z?SNSKst=Ou!>NjF!;(UvZCvaM`At2az@r~pC_}Y*_HAJPXhX*@e%f&Z@>^^v((<$Y
zcpz-6^n#Z0_aDB3vA+*e@_N_X^lsd3Lb*j(=E%3u-p^Pc0nd&3eHjgk*)#_R{TWlL
zpg+ir*TA7e%*pql5X^i<Ma>~hHhpCzl;QK>!U;yT3(N?{hOC@oHgF)Z%(Ou;6ByY7
z+W#amgJ)r>jG0J}+;XOziY{(4Ayu$+i>Z7GyA@3GpJ>%EcV|HVE+eKwgJvc?45X7e
zC_~?KMwSP?ekQsBB7@B3@c?_ngw6!C6KgUWC?{Aqgw1gIry-Z||7ZP@k&4DHFijJn
zbdl-(3w~uXPg#s0i+M+jzDvw^<3X~S7v^B*Fb;ISJeT>1HrdyhVK(rfnBghIQ^Jg+
zYonB@q0H8GrVibb8_f6ycvr@(qcW3n#)E<aEsS_3W~`NYYlRWbHfGmifIeb0l<9fQ
zh-r>rGLz_O|BCsr4QS46PX@ejVRzGF-j%g?fPydULj}TqY%wK#4zSa&L-H7F*apcU
z_RD$rZH}|QHiAU5-%>F|6zfJ?kyC76FGQl*N+}iTB(pc^`FMuaQi2RG(GHC1BAb2*
zmNMDABIswa<MzUtLiTtQm{-^(v@5*IzM=qS5qmZqdN*13pMiagy-c;h73>$2F~Zwy
zKJ9Dnva{(UXZP4olF`?|zE4+bBYXeNFx>x5EH@q#)ydxc9-R-_P4s@~Vn3h*&)w`v
zDwTW0?x3yLV|ML_5P8DxrF2&h`(h8Ud)cf|`1F(=PmiBxYzu9cp0gj*Jom9*Il;9T
z?3*q)`jXB58zXzgM$lrqpY^In%Q(P(UIm%gto25q4YD64pwmYb&;gC(qUG<x{7KQr
zJ29A8Q8qbqR<t?@q)?>X2Id`65`{#%MLxU1bP~VV1<+8j?R#)ESuC0cXL7~A)&R3i
zoUjzkd*YOTq4!k0Z!gGzQM@+u{~iJ55)%PV*GeWUNlwy5l`@U^KRPh<7RlukfVwZq
z{TCvg68Rk%eT46q1EW`Bb`X*;Bo#lx=YGlXv1q-Kq*y`H)uem!FpLX-_}g~?yK3nZ
zz^!g<LFd}JR#XwYej%-^H-?;t(6(RgF&V#nJRE=9D`=l!nAw1T@0_Rs=&qLOP;+D&
zFJU}R%o2JWc`}hy8tui5qlnHSCg5-2A7-Xf3@n&gcpt40=FU3wMKLQV3v!C#DX)2&
zNuoHhF^RcMN!w)RSpz!HGjm?RnG8mtSLFrf+A-)~WW)@tXEJp|(8ywXD2Q^2six1U
zWHZ0*g$V9T30k>KVJXz}nC2Xi%goP|RnBM5Z3J`yqxc%?g-kU)X09;46v(@3WO{yw
zOc9ey0p@FreileE<1Gd$VHP?9w3KQ2uiBis7=%&WV6N{2vy3@e1if;`t`5wb%nv+T
zx0uuQaHf{A55~;ZF=<rFQ_sY`1xt6C<Frb?$Mijd7Y)qYNf2pgjD@2yy$_hFzd@#h
zNeO^{CzDO#!H0}-JFvT$gTn#S&EN$=4~Z;#NStBaw*f7kO`sDM8SD`KNEg{I1}ItV
zm_v}vWzSO?SU#KmBgS%tO`{$EH8!;ddZp}Pino@rtBt*osbIg|42@dW+Z{43>|$T|
z<|w-Qrwm;D5mwV!L)b6&fP}Io+0YGRj}X!cb`8Y|!`XS?z{!*BPp)tzg8hZElaZ`t
z1-y%5hnYe06#KLuwxU_<`7jd0M*IQ2SR=cRYN_JbCpu`vvurv<6WHfUh$gZxnjm_b
z4NHS)66;UP!DMzR)eoFuajoHIWX1oY?;N|DcGl<F!i{L<vR}pmC6Ar58kpDEb_%i<
zv)AY}ehHi34v|v!<M~jiWQ`dHn6F|-)9SmL4aq>OhMiRi#YT2uHU`?n)}IDiGkawb
z6kFICjv%e<0t(5uv9sx{?0q(9C-mCc_8ai&0s9SoKB|MYrk}5q-E0NPhitJWz`EES
z^pNgmzozi_BlfH@7oCq;A36Z>f*ncA+n214&Yr$v`{^p`XRlB=Wq@7V59Vvuz6>IR
z?AAFTLu|)!^tp*@-@|mdi#+L>c|gR`v&&ypz5ydVCTe>NB0-`X?P#48)lz6DLNw|(
zD8!4#out%Of+&U-&MBgQDD#pkde{ZgEK#H%$R$x~A4Cd83#nr6ifH+GU|$stg+sDj
z)c!WeP0`JLaP5}p?OOO$Axhi;$=f1<?&nHT$8_{ni9S6FyVasI^yP>e(FOW_?ug3V
z=|py|=*Ms2O`T{sEp_Te)|4c@E824i<eq2&t=Aev9KF>WMdoy0H;G2<1G7~$F%7P@
ziS93lrTe0aVwi6iO{Q&cr%3w(m=8tu^u4$)k<~3oc8dlRp#Dg-_z6glNU@Io*P&jK
z;Rj$p6|Ikl;-F}&7l!R9&Y@~pCvhtk{5gw<Z3b}>-*!NstN8p_NbVQEmxO_Oh<B)9
z$y0oIDZKX)XZOIMuUMdmlb?7aU4aM0HFV?ni^uFmU!1srLbEAimwYG~v&7~UUMLXP
zBtfQBJm&(q55<Yj^!rLKcfkt}lfOno#K*)v8%#fwGldWdFp)L@`?v|03D97ZF|KHZ
zn5?6yWT;6nrT4>3`nrJ`ZjxyOe<Mu1=EKn_lQJt{Mw={`lQTw>dw$@?n{=oEnqcBi
zG15eneeF;@Z6Yqhu#-)8)28E$NpUbh&zhWc{J*6&AN(VPSA9e~w(l2OqH}dRhkvh`
z`~&=4`v;wpUY9fvGV7xj;O{N1&w%susxbU}>$<=3?`>ZjA4BM`$f;2HJDQ3w?BAxP
zf?-QA{@(f7eGF<>jSK$X<3m|ZS0-!(%{_zHDQ&uJsEW>yDH4Ekfcbz9lKM02I^g_4
zW{wyG3t~Q@FxPQr5#8Xy%$ZvtA<Q>)iH9=l|6gy{;ucl4#rNK4I4B6sr--OmLrv`=
z3^ORgl@bLMMG!+wg2Z7MUJeX0gLQidN&=bB61R_1B1IJPRXTuTl%|=f^e{{`ANVNE
zBn^C|d4Fs2yZ=FVbX;exy<U5NXZG29t+kK8(AH%;AN@IWJNRl!nm6+9dfZ+6`Dd>H
z9Olbu|8<-f4~MoB{8S@+Y~}x=637dD?r(7B8lU|eh@E_)2b5xmLCcxtq7vCfOo&N~
z9@PtZ-5LzSGM@ex)Gp_(!y&qw7Zy-);2ORn96qn*&rs(0J<fw+a|3T21=fxH06l&_
z;-At<-mTnk2L!h9VYD9H&i7JwqK=;*53HUqNx=X#@XlXB+|T<D26ljZQU>*Fo=Fdk
zqx_da@ZtwPgyL*1{L8|z&~}#RZ3lXe$Grj*=eajk8(iSmr$J4Pm>&y?T9JN(ZV54y
zVzgUDJ<aUf#1h)vY!@N)KByg{H_h5R#qtH{+7U5_R`q8^x(?#&6+zk63gz`2w0)rT
z`xX`|6}K)l|9q$<88C7il=4V4ZdCRUgJ6~N7oGduq}U6<QmtgskZe}MO5yJo#X{Mb
zrJ4vjD7sAJPg}<2njCu0zN6Va7ae_9^ECxBS7=T)z^8J}nwe0&Qlr}kqSV}={lhBF
z%T=`gS*_VkHS%jTFHVPD+~W_?wFPQCom;C>J7>f0R<+weU>~bv>EXLub@YZnotpm;
zz1XYX+zFO_st@gun$&ePH+`<o@d0P2da(kWi(D<+V7}JX(htN#u7f@Y_Lb|lB6|JS
z30HO8qZQyU!cK2Dx-Q!5;pXomiL&J#!fh=ax+@k_oT*f~beh%y`0G_a5eCE8?!<^h
z7xcmPq^C~8cFa{uSHybLUS_h#E~tpJyaxJ|^uBQSd07S7q$WB(k?hT=Nb;rml;fL`
z)ecfhM=dBb6Y1QT(Jc{T*$siXp0$UP`!@F(=zzU*Gk9KKeG>FHJi;NhfV-if3%kSz
z$Iw#B)6Rid#x=CvdW(A`L#US5><9lReAHpEH1O4w0&C)h&rqo4Aiwe<s9*DiUI5?n
z1{$D~{Hq8!{1boS60l2rygRU8dH=EKX$PNv1ac3!XD_rBiwk<ly(KD9>h<^7?9GSk
zk>~ngB*sPU1Z%++3aH%XWt17Z!wtir<xhUO@Hr^G&&6)YKjfvAaH>dzP6Dx5B=rI7
zn?h-Zs!}1TfVE6iHKL>Mirn4Myh89E5co)ZoDHl|Y`yqst$kcfrjXl7G4@@k_)#>r
zLE$M8=8f@a6@jS`IxV6o-B);7d=&}SE8<1~(5u4hJ2-Yt9C8*jh&b9k-w<0=7`-b(
zqS1wWqLN~;3zcUS__aiNX%BS2qi85JwL)3E1SZOr8KWP~(LL`@K=UpBDQz_W;8t4n
zcJSH-FxkoHtfBbNZQc?EO?P<pXi$rVSEjSu8|K00A~7fwdKZh|Pr-D#2s;G%m7<!q
zPEt%E;(D==@}*b-(mS?45Lq-%mE!0vaBdNiqhP*9%npS>tyr@Go_`|tC}7zoQm_&(
z#IW_GwBSAw{ScN8irhO;b4bi7!XO<N>nStTEZ*q}!BZlU9=xq$?geN&Ev8cJ{fy{N
zTl}BIeL6vLR(wJ)dOasLQTF@1$Zvu81yM=G<!#~$<@j!jzzp>Bmgs#Lpzse7S4LwZ
zLN`LNQ^@|H-Vrk?J8@4q-&pgfSTGRs#Y!gCvb?GEdlD=aN;C!7YLvn4aOP8`emL4%
zltg+b$XO-i23W2uBWRD;q0E?qwg*bd_uyQhnNO)}srfbv7HSGLsWCwJX)e*a?zm>r
zHTd18sjda<ZB0U7XnWfwnr5wXmm|LcTkEn)Vz?_^@~Gap+U1S8Aik$2P|#$Z+Lyx4
z>s2ob-B+k@aL8>|&r?FIM(sTipjOSMxo@jlbQdf;)WRcYf$mmMCBqAc`aR{$>(xLy
z?XX8(=L?Cw>f3>EZJ&De3M86TM$6#O)K<Ee_p2j)A$~wj>IJzk)QgnNJghD~2!W%j
zBLF&&sc}h=JFd2sz~ArG)=iHlyYcOtFyMtzf!CpL!Wr7BO$_mbe6(L8D3cziBDa_>
zeQ_P@_aS5_Pr8lPxWXSGHs$f1(Ea>3Dq7?3K1AQAYKOyU!g~};oMv4PuU<%^H23sF
zW#CL4aT*$4yg|$Rq{3OyoE%NvnNhgM2V<1d>H$SFk5Z|V@oEYFO*IsQ)zn-9MQJ`%
zGh)6-j;CJ>1SO;716*fTP$D|(t`|77pANzGtflXx)$%6YN;$XJf}VS^0u<}57+A@R
zx{6NDPQC(H^1r!*Yg@FR4h=8wqk@&!vPPp}9#5Hsj+F7Lu~5>)-I3R3$PO`uZC2&Y
zdps>zHzqI7l4Ua5v#hx`UHsITKtp&zs(C_0q`xsQPZw^@wVQM8HeIC2l9gvO>+&oG
z8Cl?ziyrVu-yEaKY6}{kqW7mih5$ogK!`q2A7lv9*{xQKP5$&3_m=+mdDs7op~oKZ
z*niqk^L^ewEGyS!DM&N3e|Gd77`@_p`9+4>$FZ_bxcW<bn7fzsEAkj3qZ>Tj90x9o
z8Q(Zk>Xc_6m!+ZZPs-n0lwPInEegIGM|+FQk4sD2GE{tB@$KSh%jo)_-qKhnMwBMc
z>*`3J=eE>SmhW`$A-7)^ZjOgb-G;==fpyArj;uDf{)vulq3#V4<8%o&bG}VyGUi*X
zHeH0(RFLDmC7yp_YLw2FXEd2p>}F$*E__U^U$`+pEhWa9R$wuw#9PztFB|jCx(IV>
zL53V~OnAw2CtSKoygX#E^xUE8;@CCM{lz=oqv9h|rj41D5a}Bn;QS<%dcNAt;rXhE
zyDH7~8m)Zpgz73o+uVl9C(gKduk>?qbJ&VJzI(NAh~D6*4+;o)%2%)V5A@gj;vO^v
zjMN(#bEN#~Ve8?mH>DbbjA=o}fPj&~dV?`wxM5_l$zU2`(x)1Nf<~6!^z_8{F~?0$
z?K=F&h4_h}s+r*=0TUjKA-K$hmN6}!_@X;wSn)F9#n?20y%@_S*oUzag8dj<N6?qC
zV+02=hPXQuLl{F|hl!^c`!~U1jNzyb6FSDS3Bp@M0GJrT;#mb<V0~Iga1>+B1aT7L
zXM$t!`^C>!L@?$<a6DrO(K9iTF=Szwz*LROKPKWBn@cdBv6WpNsZ+IEy74a3!>FCi
zedS9=?Rx&Cd_Y*7j7bHUDc>iMDX$aAlh2v}%H(1K%N%D++T%jt?CjQb?HtkWD~Dug
zV@2}-Ifr2NKzY!KKOwy{wXvK@b0);P$Xx`&q)QgSD>4B<R0PSYEbxTM4ktQNj>{%h
z!Ez-apDr(DgSkkKm_^K^WXUYFemP41K(IMf4zYkMN)}kqTo)$~{*Cs`0ort4rsp_S
z?;`Z)0aDF%s!Yg*N*}qAK$+|S5a&YVIIB}rxfN6<F9C?AXJt?x>{Nuw5<v9eL>^jK
z$-%P$f@J}KsF)xR&UQBT%y&}F1eVEN1bn574Lo(Ra+(c_s;9^*oAznGS?Y7OJ>*53
zR?7oqhfO;aTMEI3$^mxmAklD7j<ahK8<shC?NC@PCt#P20HXRYd6^o0@HS=bP@lR4
PEyGUee;+K&oS**!#B?*l

delta 127941
zcmZU*2Uu0d7d?8;ZKvMe?7b%T-ZgfkvG-nLqOq5lXiP4Mieg0+QBf2D6_sX1P!O>o
zC`CjOL6If`iYQi)w>JLX_ul`#eCEuZJ$tRaXU@5EX7=n$ap6x1uYTIyfK3Q(_)yKc
z&tRD&DXd4Ox}Ia<eU@3Nsb8RGR%@1b5tu(UPwsQf8qLLe4D*j>66EVO!!~P}|1^I(
z3yg!Uu=5PV-b!E@mW}>RVifE!8^<Ww#3Kqu#olNmFlzQCP#SjEXo=z2i+5BE&ldU!
zjKCfWVi}P&{KYa7+t6QPWLD#-rDn8j)K-zvvCiw2jGnb-@r;4>oUdSv?9k6@#>8r4
zMaImIa8ocAwpTXCSlLDy9Ajg5-QXEJ+dW^!)L^+x4O5ei>7{0BvFs)_Q=1K$#xix-
zw+R}iF1xit$<$+4>r_mAw%II>X~0%YVwr~Q!;=mb(}+Dbg=HGEU*j}P6ZXVVfoaOV
zPE;_>*p$XR)13XGRA5@LR!(GEvSZQ9AJ{AF1?ER~_X3`2#X1>yrZwBLfM?pU3;J?Q
zTQ>ZnhH1xMk~B<vwsr$G(}A6GQerx?x53tlom`V;I<tWV64QnK!fPB%SGKU2W4f{5
zma|NEcGD;g(}T^MEiye><7Oq(i`{)z$@FFy_E#}|SXQNB`m(JG6ih$1>3)v+i9Ps}
z#PnwmCTf@gY=cD{GmxFUP00*m%S(7>Fw4iQm?3OOKam;AE|wI`F!n;FlKGiEks~p~
zS&vu^;~2p<El@GPu)|tQ%t*G!T$UNlo_?WZ#^7#h0=q~I|LbCrQ5;eJz%UT;D;o=p
zN};ZYd!<rvBO`c5rBdHf3k<*h5T1ikHMc0Br{W4a<9XoK!=j<Ua~+@IwyD$$m#(I^
z1Rc-t{ob;Ss$EOVdg$9u<6^&ri)2uLR4A1Uqga;5FzU|=6G<6G-58H3zLv42TE(a<
z6sAZBWk&9F-{Tcu+h+a3GeUPGkw^wb4|WORmw40`YSoi44vIdkkyv;|+$=Qo{ayon
zqQ^L)JsaV%NoZcbV+9lwzc*PFTQcxuCw;HgU}W*SN4(I`uy7)DCMl}P(D?x#6+*2c
zSN{<h#nkUYgJQvKmQhUmUb86T%an{_`uAE5#mK%OouR1qvyNg3o=?Th?`;hf8$4!+
zwTDE0f`4<q%i1aa?F#hV@3l^f!_(D_V&3;!H^p4y`t>_kFNIH*hEdG_-qufX*&_;E
zWf$Ssg731?iq{beMzQdFZM@=NJv#Eo_u6E|8sb{?ool+HxC*$%-`i#@u6Q(*YAd>&
z_vj<latv$2F^UxmqXFalw_^D;7+v{Y(MiGM!BVXHUfamX)3(Cf)e7ZXsEXWdjJ_r+
zR*jjX>JZHz)6QW2z=NUsR)Q&^x}9rYO6~Jy6|Vi)a+qHxHiOe_t*uH%$?&ThdOVVB
z9R@YiFu$^+SE?|R)ZV9t*6YzKaPh&v;Ti0ztN@Aja<YQq6Kr(TwdEf5<vwh8kC}2U
zHo#-8+`P3an_)UAM0#B4zZ&?T^;X}mt72OI|D;zu?#ay^ce<z;S)uuVw3UswDj4>=
zq(L=aS*K89KC#t0|C2OpuVmi*ACf`OB_{v>kVJM-GnxN~B<e?wN&SCI)Mq_bX@69-
zJ>+pzYw6YSx{3*AwdBhG%<Sr<VtoGJlG<H8;M}I~qM=Y^y}M!1jq5y0wXGf3!<5XQ
zthHgar~h~F>ok4IGwcM`O!t8P8;$>2@BIXuEGU@?Y*zv(+?VM_HdHZ_SSu+i-2c*T
z5Cvv3YyaN5hEXqm!7?M*|L@>hiX==>^yJsCrvE<X%4;SSX1?mqw5T>%_qa!dt|sg3
z@laRa$PDM03{uxsx0%<TQ|n8Vb<~s9jIyr8QH#<;A*(I6c^XDpn^W6zJ#^+;w$oLp
zHqt5uom%YO01uC>RBIAF`j~qT>h>F^EoEO*HCXkX!k0CxYmM_07-c)lclrMsPU@}S
z>*`I0Q->u0Pq2cz{tS<6=A~@BM{7%0cDu)XOFKv9JUq+)Q|&r`Bj&Ac+xlr3b@yZo
zrmG&u@v>C+{IHZ~)ctO)kr?%WdgCA;oVo_rA*+@`GIWPK^hb321Fz3ty3~jM$eX<t
zjC$-d%<SrM%po<S9&bLaVSoTV^AiU#^SKt(ne&c(s@RHwV#;ok#?qO<G8rtGnHk>*
z(7&8?eAM7!^yzf{wn@Zw*kY3V2f;UH(H+uXbDORaE9sgTKx`-RWrNi+lDO}u&pn2c
ze)lXTuKr;TYG}EK=p3y$T;oJCVDC@OPrH%%p_tO)TnxEYZy4$8Lx`f_8ljHWr`ABs
z;^+n@Z#A>!B7GJI5ccodgxc^2p$6<D^Ie~l)BCH)N^~~wKoP5;-d|r$q5@}9E&qum
z594Ww=4>a5f*c}kpGrED`;uhhF#5bOg-pt;N&ojUGH{>`wLbQz&zCyWwfP^U^Z6Lb
zL+IWzV@4C3=`+JP;I%9D`@}A~a&O7&2~Ddh9Hg`$gPb^!O06@l64AKMB&qe8S`Uq+
z&sYDWk@)E{8GG@P3{*^|ZX8%dt=(IbrcjHnsR5)J^nhINH34i6W_&lQ1dXE}<fanf
z{RuKtr=)rSGYQagImv(8O>Q;6P4dzr(#dT_X7b0;b!90@{-$S?@w5<I1QtSSW^^NR
zh<i^~W>t?t-^Zl$<{0TXe5;4z2EJQZE$$%E>DAQN7CT51dyP~-gb>BMDdfcUaFV<l
zMQ%mCC&{nhA2EOW{C6i}SP(@n?l?&djY7%r$#(R)MQ7q!YNnC6Qa!qJ9qXv#GLx=3
zSTU-Z8cy_iNVTU|YZKkm8f5HEJoV;T8hxJeh+Ldh-H(7O(&;&m%pbCn8Qo3darGk2
zp698xSvGOr^CGwIC($(q>nAm1-0UEw{tBYo)|gaJ=TSrWUQ#k1B>7+)8UC^Q&b41f
zt<Ad=T~Ro-?l?zxJ$*2lG?b9}8rA(iWh0%|V~A(kLHhgwYfgL>n~~10!*s1<QPT78
z8bV4LvD94Als-3EMx?8&pW8GGsWx0hhR5wCckBF4#%ei8vc4su+-s2JjE!1-oCsTU
z4Be(#pXu|=cl5ag>pVQ#Z-}jXM?zU7k)HokONc1o2{lYEAyx0{>7r)!U>3b2(#Km!
z-aC)X4D3z)o-B}LR1%?9<j}}9@u1eFZHfBx9pZGy+d<8|)sp7FJLq$ED#<enh%*W=
zdOZJ)K2xPkB#M}SX{c8mAOjOJ>GM#$1Jq2rL;^oMLYj%w==0NZYV8$7CKUtdYTrd>
zrmiFT;x=Sv>=)|ss|h5zX{T%9Tw+UgrRz&?(sz8YP{X-sG9O=kFS}tUfGOn@_2d3#
zqG;WSBz|*966r?fLywW9{uz?Y!b%47W(JvDpeO3j*Qj;%Rnq+7F7cO*qw9Wb5HO+5
zBc1WFWU+^%m?#SORbQVIAi+XPslH^`WT(&BHOSMo2_*TLO`ivc5cpS_uE|($sF|Y=
z$%#MQsCE1r8mG=F^f~b^Jpo<ElIFgd<ks2Uq`$d2>6}Tfp8tQ^T>Y3Z)O=<zdDrGI
zYHk=v*C`Lkxmb>L=46siMG1Y*yF(_q)<pO4AL?Im3dwV;pMZE1nH;)}oVeMNbdLW>
zSKZIV_RC=EYQHH8dj4N5rG^<D2<)?tNE=Qd$*SMzdbym4E*zuJb5;_pVmfIyyiFzt
z4I~%ED*AlB4;ic6KphA@O!}YZ)0mYtC6nTR^m(QWu`M}EJkPN&!}H&ABZ*#M$BU;F
zJ8CuK8%*G}{}Sv|OOm^Ul7U4%=;|<#&dAerm42aX>Lt=#*qhuMmrLd?HA%D1RN@Kx
zMDnrDbnVrh3`b6-PR^>rX9qKQ0S)QV_XJy1JwYybMd084iS*)SqL42UplLMqH7tr+
zk5|7Zm(tpT5wV2E{8&r|OdRzxr9W{#SVsDpYe>J=EYc|&O8Wal$%%H`>9gZP^^2jU
zNUGX}<U~Od5#66bus%zPXb{$kn387@?DJnFarGpy(3QsKGnT2Cyd&t!Hzs*X^{eHd
zO~jMipO`Ce(RH&s@&6h{a&|m@X6pB%LUtywaU(UHUO*IwmJ@aD8XgVn*&HKmDn`Ss
z_?ySofIFmN;=;&_;ro^N>~~4T^?FSX*PQXx&9go<bQ7^#(J+&H65XZeG>m(zZ~N{N
z1>|3{sZW1rlF6kEX)gUtoZ<hGW>Oh_9#(^{jT{oG&co&(4+xf-8YXoqd40b=sZLkY
z^(J<48m3Mm0p`3V16BP<bHN;Pap@Rxx<yBFG-n`be)FaQX;y|{3v<6W>CEz@>(yUr
z*aM=8e_QqXj;rOM!Fh{GOT!#rO%0xX2+TL6YwRa%&zPC7$%(sohBZthED<%#n^9!)
zt1qFNAUdL9E<Gl<+V!9wudKf7BmIdvq59F7QvHON9He3Q3zevWQP=!+3A*lR=7N2l
z`iI_sVps<->+pGer$F>{LfZ;7PmI`x&y(7F06KZqWcWX&MPs-&HHMzNc_nT@{XUOg
zDa*gwaWnq9MGH!Ye^W?Y*r34}*6r->I24|28m%t&v#UP9NiTNdJ=6}cj=X<S9%RS7
z2Hzp}^DG!W%+~w>t4G*Dz0q?YcHar$kFujj!0<7)@(DD3+1In+>Tz}|y&3#ie=UUm
z?B&@I2C!3HVd4Zkie7Rj*+~;Yc8U$?4(dQQa|8gV*&jE+^E2#0$18B3WxvoQ9mL*<
z1U{IxML`(CvIw=QL)l>%VRaa*aR>e!J5GnT^K95&a9?1Xy@cJ1Y%42-msktJI_k^p
zH7}5bvm=91yTW!)fcXeE@C@LQtX~L(S6Ti6ifgQ|FU`?WY&JI1>S(qV%{$lG@KC76
zu%8aY{0(+$5Q=0ro9rSs*aw;q*yHms*r{w&A8<cpN8JJ-ja_jYj;6EPnc#lHZnz0t
z23w0}v8U{-wkWdM%J;CB!!ELcC68_3fjF1CfSpP&kC*KAhL9GsdB*`PVP`7Qi#M$D
z9oS0QUP_pF%VsWzW*J+=qU{~Ktq{WZZ21k;%2{C~+CH#-rvUJg?e!70Pi#qRIQoTE
zd;;}XcIFohR|R|J2HL7v7Pr@-c2-QLWzz=5AWyisO%bE{-vipL2#=<^Q^9axmOiDG
z&$1R*VQKmCu`s)WUxUvp8}?)1E&esC-3}UUi&j9|u7MxA*}h9x$UDqx0b?D%(zAP%
zO~SsWT3xlT6`m%ImxET>oV7U^`Q&pD32p-WU8Uih`54a@e#7u3bYb%qaB?F%0W-R0
z3mbL=-P+1NZ-L3hjqQPruzDNo`vbn5N7x&*T=ijf2)1Gz^uyp*C7W^=T$>b)>8W*7
z%p3_X_bH0+GZ_B^ihlx7^-;9kg8>LuL@fa@N)h7*V7y}ZH*8?3gZi~=Ag?up_FD~y
zO$S|DH&@7eivkqKE$e~~E*ZEQ*X?Y!7A^#^yB2~llGSbm<UVVQ#0>JDop<biLm*z6
zgLj15Fz9b|>BlE2=w_>4cpGS1w{ga7(&qL?1f$wgXi(E`T7Pt{ea(E#I~`(;7^aRT
zh^(qR4fV(1cK&BP{OHoy1bNrzAsDA_TW{jp{U9wwdfcJK%7Eyt@bc$$#GBP)8`3Lb
zMtV!=I2KG90iqR4+o1Vx-h>8cR_lr0ZDIBQfZT%}$^gHgovVk2FIy?0ILkIQKzNb;
zHVIx|W~-eKXRE!x!dAN<!B+bp$yRsZDob8#V%X}A++e9E)uZYV-_jg!9g&5>t=Wov
zsa+Nfw;Rrnf~!q)Fcj+M2O44^Teql>*7iwzfb6*AICb#O3OLhy*nLR)=B$KA1MAQ;
zGt7gwL?h2g&>z=-6GClt1MO@Y80%)Y!so_uy<wwe<ObTKbPnhY<9*|4^Ea#o?KH=|
zqV28|n@lTbXSR<wh&Hfsb5QeQYkULw0X7MdE=-&!=q>Kcp56e8<Lvq`!1=K=vf)J#
zJC$(3to#{vLs*p+Dwo;9SAd7JzM;^(!a7#;ht*g%%^8TB?4OZPy~WBQ=u0Y_MqlNJ
z?6Nf2O=Al?0iVyt&|<%UO?(K=mu#{PnjhF{_W}RN)@}uZpV;0zAl$6*tPM?9g+T$9
zEsFd)5PB;1G(oXn;pPo8FGV{CP7KrmiX$h%c0%Fw7aC70{3if-QPIc=I+qmd{sI27
zV){*(xTVOVNXBi&2}Io0iHgP)Z+WE1L~Kr-spw9(EK3nj@E3|JS1`8uirkN=6)DP1
z7_JYB5o^#FC*^{_fZL>eVsQYmU1@NK>JFt3-lA$R<<b|hdqCN(8C3n0e{F!OzjF0B
z6rsv{iLex={PsIYuPdjI2Ruf30n7C2TihURC@_snUZdLNVn+;g(<e^<YwKSFD;o8H
z+6Q53;N0u@JmkYm+9Uq1QvdH^td%<p{ckygqD`&-eTHjWxAwSpnB543oqwdzMYk-x
z_SHSNFNCDe&NmqEpGJ>^zXQko3C$6gX+1N(Exnhg>t4dtuY<p#b@Ab!ab1@85ezG5
zK1UxSG*z^Mbwq01-C^{qX5uKc#cG~W&+cmcWHhE|L^l{q*Cd<4l)zp69h&dBJH4Rd
zEF>!da2H1Y49)YpFxnAC=w4L8vb*8rSk(3!wnzN$*$-lml*6$Mws|^0nQU<*)Uw#Y
zJ`T8&%`UGC{uk_KU)<>&cGnpcdljb>VQrsc)_E}QS47nUqnF~(a1;j>U77)RNHL@d
z*bXZiRG>Jb$cqEZQN{GBs2x*`qDAX*MURo_xSv9~A6{NiY`ucwqN0p;)5(hXLjuM>
zMbS7JCQ=pCJ^=Vo5t9bsBSl}@p+8o%?FZo#MG@^=GZc^L0nJo+c7rfWk?{zc&lSI{
z#!b&wJSjyjN3nMWx|XY0K*7I!#iA<or9g2Gr&sDi1-}fqSBkZWx~hv6V>?icszgzF
z2HZ|ctqU5Rm6~i6E=nhy=cqR-56p!7o0a+HaK=?>@r9+6$|)8IPbs(3tx8eWk3#K%
zvcd?Khsx$_p_!)KbpgW1%FeW1OjmZN2t$VQ1Z|z4D%<~#B1?IBKH!dLO4oZRUnpDr
zhC#?tE;@-?p7OuW0Ol*RV&MKu<=+{o6)Nx2i?>MG=Pz&<D^HU7*UEKAP<x|%!=iYr
z>{k~oWy&~;qrF!)rhQ+zQh5NikII=}(X&s=A@o-GqMVTnz*mQI74^4LDN;!Gn{v=f
z^w3$gKMK9rpo&`s;U-lL3YczICHuqR7L{KXI=WRg;ZO8po60K;2Dhtzp!sX3YC658
zcd1@I2hLsf@;Eg2sA}VYRJ~W_juTS#KGoKNXxp!H?S{fj<zOem{2`TpICQ*K6DSOK
zMCF$OFML!Ib>^6=X&%~qRcs`<{Z*N};YEPzK8^ZGm6|5-Q>r{S08Xox4+7wf>QE2V
zf>bjbgDhC}&I?|Is<^(ug{fQyKzLr|mx(T2PzjDqATF!eh43a^wWk}{B2?`{fsa%*
z{1H0WRGJ!4iBk0nM-Q*7_|a&KQT=oufLPTI1H8DY8rKHJZPkm%5Z+OBy9dp?s@VE)
zJ6@HmM{!SeY!FoLtIRkUR41v%4FF5B>baK#-aJsnJ%LWDD)uowJF0+wpn0U~TL*}A
zRky<^o~Y(f$oZ)%tq?_~YW*(IJX3KR6wg)uv}4RsX(_^)tBT!<B472W3)%`)^`5~(
zp~|Z*gs)U?&ry`9rs4!f{aW>98LfXxRjce6p|`5ewBCECYNAH%z3O2W#_NOX%|0ML
zss{c8w$G}ABhdCm)%F2MD^vw5F<h0Z*{7i5r0z`{3upE2SHQWbo6W@_Y*aUG0oOLG
zKTXC^x~kJ_!|qmfO&xG<C=~eqZC9rmp}IredLB&dQvdJ*CU&bA&H`|cddgS`J=AAz
zK*dvS7zGpi)f->I-~n}AT5lgzTZe<&TixnMXdYG{J`A{z`tU6b@KN=%K2Y&h7gB)W
zxccvOdV<t<Z16rnz2_ooj#FxGG%N+G>otJt8THoFP(7>eK%44dbqMWhL)1IX5S~*P
zmV*1ddMv#xFRB|oh22Z)<@vB1u0Bn1+$-uoX_FkOKAR4etLlU`fJdp%9tJ#Gea#2L
zM{27#YLC_3X+x6XP=6c(;8XRlU*S!bdi+>4K2yKG1Yx$iH~{z;>V%=Nl&daM!|y!x
z^4Cx)P>-W`?n|{Q8IC$>Zr?%StVtdWp^IkGO8B%<vupyK*{mt=3xKOeTmY7>8X*ye
z+%!QWK)plb_=^HvJ2fpS)a0)DkzQ+iG#Br{(msve2!yAmf&z73n(NOnP6ssV8&El<
z*-X(mZ_Ub^u$!crJpi?2&67FMOx1LtCC)=lznN%zq-oU?fXAAgU8p_L{EO30b%rLn
zD>O4TI~^TS&C<N+4~L&?oVBQBYnD(9Cr1-m8$RV~Mp8T?Uo&6`NDDM;mY`Os5zoWJ
zSDJ-?0avVfISZO4n)ti0RH_*(gZr&U2nWl1%^%6Ym1{nRL-Uj7!g6@=S<~?Y+A1`)
zSJM8kQZsxI@Ku_&6c%#gx_^a<4czcYXmjD7SD_ZfH6URy_vr&ngmSljhKVrlg%8-y
zb1Nb+z!$ij_8`5)8M9Ek%=u_x_X-#HA6Ozd=cW)|<x=Pn=^9r$8Ew&Ay;Kh0zw4ZF
z6{I&fr)kiM<-)>Y=@z#YXQJxc+)fHj#&LapVfQZA-4AUE+%DuFsPAzs#a|M+&J4yP
ziBr>?BZa#&7&r6*cak2&huoR&DAKs!Y4!h@bG$|^oeSUq$ly*?QjGd3C)3I<i)(|F
z1obm6YZiRV=IZ|fyDzxN_b`~pt=WlMK9}wTU?I2q5e+`Kj!x4`xJF~Z{hI4q6Y#g(
zt0;I;#)Y*<QO@mn0o(^JX*g6qb5>UXzHsj-=32>BP|U#bjWZ0#AUg3~`$Ou?@AN>;
zg|C70Z}mq0Ofa0;%*Vu_aOE%j0K`^)$Rk*C;~#AS>2}^g0gN5|vN#mG`21ba+|7@5
z0KSL!J_mpY|L!J=eSCxqeDdT!N5iKWz88J(ZaDak!%*JhE7w7Kn?Fs#*}MGL-_h-O
z{#XJm-Q&l70qK3dC-P*}N&JEt5GM19gTVHH?@znJRKDF&usq_g?g8#Guc2+g6aLyl
z2s8LWdtp9{e-jAYGrmb%)L!ttXc?KqJC+c49>3x>8uR%PJAr@6EBk@FkT0jjM-l((
zB|1~g$A!Sd*L;_80KDNv8sN9QZ4`<!eoisk-t+G7;e9#3eF%h~cqN@le&(HM(esrr
zq0nFjzpFLKs`w5oP&f(i9CV1XL0A}%s*A923b;237wO1!vyhaCVvCS^3cc7W_^pLA
z+XSC4FtJ_OQVd6T3TE1j?Gg^mhNipF(-pNnLe5dJ>=TM9_UkEV6JXa%$PGsAfDl8w
z5N~07G{_DMO^(ogIx2Lh^};bBfi^nFg%DSC#!o1qrD}lCl%}*3!d{9_oDzzQPzw~2
z+QN%7!X#RxofZ5|D1wF7Zy*d2=AVEU=LDah;Kg}i;A~J|6xO{(aY@*+9DPX>R5Yce
z3rCV@{r^OWhy(tqaN#_POkwFH*nK8^p#bc2p+0ux>Kvi0D}cE|$Tj$#FZB5j+yz4B
z1dtXAdr|;+C0GVQSR$<K3YFJ_`vuhA3WE_?RhJ1)Nr1l>M$sWfxp0;C8y|)9#SFfG
zpM={#qibJ<8Dzdfu*^d*z6qa@n4+!{6qkW_78iSfZG#w}2JVgGGc(#YiNCf2o2xkL
z4pg>?3(o-OCa%eb<~A|^6I6DH{kA}5r#Pk<!rkHmTHLvdtv900L;Q6daE`s==(zxT
ziev21*)OsIK!k~kX%L<hOK85jAdX7LcwH3#q3FqF@y1Gc5iZ`PZ%l+(D4{J<{3iu%
z*F@zWutbTUIstxNln=pDjM$de39({!EdXwc+kb-QZE+FB+V42Tg=KK+t~h)tNaMwo
zlTo`b4x?>eqBw(&fK$XeWblEwEeXPhqS*|UG;vgCSb8j`B0WW&F7}!a6B*(eI;?vt
z{#XE&XJU9$)SiofodfQLIIT5`9I-haB<6|9w35je9j<Rtz7(_QkhW0Vv;#Cn;*@I;
z7K<kk%~rn_uh5Cf8!;dG73#O5M+n-=#4bnS+Ium-6qd@x!3aXDKZ#ejqxdZD>V;AJ
zDsu0@Ss|9u0^yr@J0E~5abrygoux%|BDq1D?x+d(4@z5Te{x7_G938BQo?fR9FZQ<
ztNo}nsSmt3Cb`i$#c`==IskssTsl??kjx^A6Vi@rP&p+<w!_E<O6)k0osmZNgYc~M
z`5`O?O9N?h79!oDU2T}OMGHgcq)FutR4+)i>GgY2+T8+nFH3(#p}*nM&`hvJNRJ+%
zh?KgVfG|pW&=s1|($BPyi;))7vBeGPpChQ<lAc}0$lR7<Ni$BGIu!=*O6@4;AwgP-
zWI6Rc>9rqfiIQg$YDrSs&g%W2)b$fcA4n(Y-anK+djX#&Euce$$5NmhYU$FjCIDtg
z>sDZ7pGy1bgfdIo*c~d*q_T^^WlMQ4;Qb3}@bBQxl|m1~wLEF@L#Px;5<OinrLXk>
ze<gLI^VK3L{DOq<U!~-H25g(;V+&C1k!R8x(?edd7e4Kkll#H^KDk~I3Qze$C4~Fs
zjt5Y9$vf@?a6mp-8wL-_zEe>1mdDkA7l-A`N8r;Dc`0pzedKrK%u)Gf58#f;aZOS4
zm9cL?P|IKL$<VEouhDY<lzf5C!UN^`V?mQ3_x*~tdvYh5U+>FTJVLu#9Nv|Hr^uJ-
ztl)usl@wFu-|C`xD5qUPktQEA<4!!1S&C9Vm-px(%$5~z(Cb{e?l}}M<%2SODU@H+
zq4X<Rxrs(Z-b*puVtH;diW0fq`u{tuvP=nvMmGxqY3%5og&}QHbsgPp+UhZ!ZkF&H
z+-qL>BjhbMc7syOgL}dE!!Qcx|5$MwI<35DGu4`<-nH3HquF-iPjIr`zdZEY+bM3-
z;cf;vJGLSxI>ihDs&kuR(C>2U7R-13u?+m(-Z?0M(>-(v=z7eL#I@&P4s^ZtYy(~I
zzbGu)w@)gr{f^S3_Y-p#I{jNw+<ri(j?f&~oN^V0yA6SS^2`K${ymkB7yquf4+9(6
zuC&YE!B#Xtaggm;8)`nRVhR}j*gC7}i9N+OqI(v^4oTwx$3HhNc0csCaeHar+|JdY
zBjX+16Iws)<W|w!ZWp)N6K%V>Xo`=xbImDAwuh@h%MTB3&mj=*<q9aWu#a=w2%#r8
zy*4!WbLY!YcyT9u(1k;sqc!cLy}6p5Aobyv)2i(#cY-30$G8VH2)>+RHQ4;QjVpi%
z;2OHZwG&+J3ursZH5!k$Q`{vws|w`YXTyur+_y!rdxrZ|ADm}7FAa(y?r%Es2<CpL
zQ=kw|y#~TiZl6PgY8Y4kD~fa6J|w|m1?+A>ae<TeV9YLZdzS-viTeTB#aIY$r8iPI
zmt2VA3b$$<oQdGPj==3m?&Mzhbd@`K18vv12307cxGvEU#&Df!oNjPSYQWK0?jtSZ
zZ*rLf>p*&oTQm?RZgcgI!|yxXtq-sp$C*xgWb~*teNP9d;sufgl_V~~2tYDdV<7CN
zaKa<pgNNJzf~RqhGXa0Z9o~cDF=ze>n(167h54Rvr+$QH1}FTEem>=LC2(ePB_3mX
zS{%)K!NF|qRZGBLaCm9ry}~`s11y&--h{S1ZY`ao=W`pI!cGAfPaB$-+@EBpkc)|e
zx39P$+MN|~i)dVnxt4v=hQ%~>?={z?0OsCs@rO{9a;|aUe9P6OczhYBcJ#qLd&do@
zBhvTW3Q7$r=Un1o@B>%B9Kw%WE(I*Va2s<`eC6V4ruoJVI||JzE`*N5o%rx_2%Y&H
zdM$0@$B+qE-sp{D3!le9(~b9@5BN5I^?Rsn=bcWYZ3qA26vYg8@~hL(?OpurC#db_
zTPy~tJ3pA#zkB$G^yc&6U%vo;FF%AHj(vRVC8+J^n|p%Ii+@;w+5vv^U06ECSNws(
zmmhQhJ{{*L4g|oDACr#(^5>t^L>It!vd~k^&#P478+ejmX$Q?IzB`3I1Nn^h0G{SQ
zT!2q!cuz{$JIg<%45uLe;!3Cl^YtYNL-?H(S`X!&Mnf3J`$q$Jj-S;Vwe!5+N^oA_
zuh6dHBJY-mp}fR@(t`6czna2(;r#JHI<vXL&-@J42!0){A|m;kU4XyJbF|94#%Bhh
zEsCE?!NO?%+Xd9F^FwKhiQ)Sff%^tOd@I^w`Kj&U%q{*b?c;9q9>YL(hwu6~RO0v_
zqG0zf|0m6i@w_v#|J4cnI*RK#?(zFGVDLWw8@ZUs-}nvEB>wCN=p^&?eu1SFUQ1`j
z5BToIP)X(I`~uR4d=4^))oHxTIH)}0J12qrG5?|nxODylg?OIugDF`rgKsqroKN`-
zx|5mwEZR0_@y9m9(Ps{RofYPv^M`2Dlg;0c1kDRR;|Jh#_<fXBk<0I057j*Wr3}q{
zz7{QB3i#a=SbND2X#~weUQ1DiSNygJSSsSJ&CyoO@1s3H3C~l?)NB4rXTaa^;U57n
z<&`Hv{g!uBAcY&7p2)e7zT<82@a;YCm<!c%{`Y?9_6Fev<vZ*b+PFaTprETnpAHGm
zbQ0z*=!;Pt7TV1R+Y#Z56>uLR{1D(rg`q#A?U<0f3?BLl5|Xa5Az4fLnSR0`+PV1)
z9hy)cL4YuQF^UsHqd$N@DO{}wwo}3ynz;joANF`S_cc3G=qNHoxV0TBp~7-{$ioD-
z2`rrx-qX}|UNCyX#09}^B5)UlnRNbhNw`K|=F38I0)*kh?mp1GB0PErpCW|dj(|rB
zg|slaD%4yGC$0%uAt<7R8kvAc3qSTjaa~CIh1TmaLg6{6-Vm;hKoKkC;8!E+o5Fm0
z@7@xU83=C+jrv3Lj!<wFz&PQF4uf!4XcmD{ix(njI!zExdCcx-ap)-SnI!Z%50{dK
z^}TVkQUu2=a6J&-P@Fea7(n5Khk`qupQZ^lDK7R%SlJOIkA*JHpqVbX&@uKCVec}q
zWC#PsK=@SHw-0^D6y{RLvV>-L(DqEIeIJ_7g`lyhWeZlvHaMRv^riSop0JH(hJ0Zw
zMGOms0o1>jLd<2*6biqLgUT!6<3#|Agf3xlrdTk(M6CpO5Gt>Qv7LZ>BP3A1S*hSd
z$7FAX`!VQJnNa&b2;T`ODR&3cUk-5PLPs5KS3d~NX^rzynA!x0Pr{PE(D^KEv18D_
z2yu1c#aChQLbO!~rTsA^mBN-};J*pGkw=3)-LdH~?<96^1x;sBIttDWVsH?IF5(}w
zz1}FQjzV*j*o+nxo5kK!!Qv{m4`4C%Z4nO+f%&cCUuU7}Cf+H9rEQ`+<(O<2|678#
z9b)lb7~ClaT?6+nG3^-eyTuv{FkJ3pg9zaEh~DF&=^=K%1Qk#5=^|L#FE(*Po0m9j
z3Tg*Lmk1OG#ciYD%ptMOKAQTx#aGA}QXdvO?nQA#>^lvXe8jqxa&%P8?*jZW@$^d6
ze8rHHFmYTw*8ntr;!0Zd`-|%bq1yqXdq3DcA*wc@?W8z_vLsH4n<+IkP+UVx@YCX(
z4siR7=+_gqvtkJ4OgMtX;q;vf7Hd#KT8KF8GHRjXKa@=!CU&D8$T=~JmMG`N89At3
z5W_~m!;9hziXUDQ|BOa)S*)a;TDZ9O3p~6c{<ac;2=Vzua7Kzl&O&%q<nVhX>}YpU
zGD?(qo|0^$9U@EH*6ZS@`5=uEk5MxE4RIz#c4Ng-iXGn+JG#KcEm1rJpKgm&zM{Az
zp7n(@abol-)b5J9hA<H?mScsD-R=Q;0u#mC6gf{40~TPMlEp#vT}%;s^o8aFv67PB
zQbor(diOsRA76tvY2w&DF!)G>Yxr`BvJ${_F>?@vPsAfnQDlg5H9+%JoJ;$*OwpI(
zJXzwJFu<RQL0{2{=VH`isAP*BccJZtxbYp@azuu<Sh?cqH4x^B30I++FZwz@gQh?{
z{|j_piuJ<L(L&MI9F4EUc@$4C5_Pk|RxFk{p-&}ZEFJs47GM5>+8gmNDoVuwq(ERN
zJ?aox%ETx5xrq9m_?Twb_hLu-8kLKuEnxW|&glm8AH}r)0Qe+sji>M5XK@fsvR}mg
zvw-+2_P>wD3i0VO2rI=vI%4=HKBb^!l^8byZB9}T$}w=3(%djk8>HJjOt?tnX_DP2
zt%!umCg~}?j5bTRPs6UObb}(CTcox(0oW>))8W>3sr4dSdhCz_CZW1h>RJ~x?vf`h
zp!P@`XdmVw@pNwBDFv>8%6{nqg$2B%J9I}6Ny(HY>@C$hj^eO%h_>EGrLVLAKPGjd
zOnhI-XBh^_Uuu|)T7We46L2S_C3G|wD7{)hDV3+ChT)K&ky75n#91kvqGUl5NAbg8
ziP;W(h*UvGWuej|ia~`*f8*zf*z9-rhvs?7H4tnUBo{goxhTC_0kTWdGz!OGmcq{f
z5H9sTkK&3HnTWOsNm~g+k&;;f3y!N&k87x2lV-hy-%(QQx6p}}>=W?_T$iRcg!ve0
z(Q&lhkPaecP8};vsfpT6$(N3IZb|WH;l*ufb!Uvs9cc@l&BaO6N5TAE=_Uo);w8Bs
zI1{83G_Bv07Cr^_eJPLDZHa<Z`2}oA(l(FM!4`+hN|2>V77tKAlDhN)?y=-SN51LO
z*JS`ak$8#<WJpsQK;^0QnD#Q6QlD*5$&%L6x#lxzWC094ms+<2S+-<)3&0C$_%=A0
zBY8ZBX0Eim2XJ}P`kw&Emuj5=S%GxRLB|y@rF=@PE0iWvX67qt=OK7eB>5ZBRxHIG
z18IqrejUQs($Ql8zL7@KR-sgirWov7snZJx%cKSyFb40W#9A=;UYbmS%5v!sS~q==
zG!p^;D7D#+wolUS*6{GNv}Y|nL0_cnwBq?H`O|rBg%o!Hjg?Xn1!%rWeQRN~s-#VE
zs5!}lDR$&6XLSZ(gRK09woP)d61dIsn{t?Nl_%1D*&;urT>P!_?q_h+P43nmD%<2t
zI%wN2ccA2{9rEfS621*P<&PqCcFElv!<pUk1j@^Emy`bl_a6Bl3I%z{f6fMCuRKkK
z+CI68-YTB*t}-~YUtU9JV_x!>POy7GUbP7<2ju~DUT{dxumj*N2j)U}Sgxe;Jt7-_
z1(}a*z^lTcJ}U3g!~8MX-Us*4SFXDNI>+UBin#m92WVB}FMpxjfdILPVn8S4hjfs0
zQf{*f#VPr>iLewXXL9iAw0wn@)o0`wI=wq9m(b2ENWK~bm0;O62Eq`zfU<Z(<%Ui$
z<Oq{JX(B%-cc%FJd3m7>(o1r;W~g13n|{NPhRY^8GP)x7po5VJ`PM7+DN_E!0h+6F
zR0ix`ldpt<ElTeE5@gYGA!Wc`m#3cqJVqW$hbA}VX<lfHm5n`N;ijB?5`bF{`Cu26
zx8<pwfVd+UUPoh`yp+~ccjbTD!0&iDl=f)}@<$4c+>_f*hvt2G7M)us%1!CWHc9U3
z2``f6sWsqQihO=4iU;yE5BQrZcc!`ep`5J-AWd#Xzdd*)mmWa}AIpvd17I*+9{n$L
zp2#X%<z&cB#-PZO{ZGK}XYz{zs6Ln9|BfO@?yv;rbLCad(UvEVp_%NZoE8dUq09#X
z_e%bWb_^x5ZXH~EE&mt;+#C5vI?XDRizdO|J9$I($)4=&7zEXF`8S%UKFGl))IQ4N
zX|?-B7U?#Bl@0SiQz4I~1eZ#=l!K*j@^#9VuaajA@WM&kmL_Ru?VTH_ZO~>1V4PgE
zTo~+b)c(>8@J-r%TLIXteMzeYSM5%kpSEZhX3^o{R;`V4L)^3hED+nYn<y=8yS51>
z_V3W%qUiEYt!Go<cWF;e2HS3JcRx7luI>5^fIZsZ^8xVC-s=XHz1p#VpxCGVOq(!I
zt<zet?AI0tqvoYm^hI$%TmBy7bWr>6ZVE*m()Kt99dGR$+EX3Y4m=CeBiivD;G&N<
zkX|)MwP$H3dQ59}1<+SJfsR*>Yuipi%}=|Qj*R@Zle&UCK>Kq&cz8nFnNr+NYWw8D
z(No$$N@EPvex^X$X>D)H-#DYafLq~EpVfMFMPrb*4&}xLYaeEVG)&vzCD_hs>(Qip
zUb~*+(U-I{=t$zSb_)3vuHAbDY*(}mv@j8&jkpfYNUeMi+*h>%{Vw2|_8>+0qqL9g
zz(s3MP}t$R_6`d}F<O^)Fyy$QZJ|dsR{M^o@S9riedx?B?XO_~-qt?siQ<knHUveS
z_BkCq-_;@q4c`iFK8qqj>)jZZ?rDSQMR{L4TMcItweGV(mZa@K!GvV(fL8D+MLVP$
z01vb-6eCL2rd&kZLx(nQ3slpzZrgCz9%<c9gXXceBaLN-Hen^WpKA57KxAqaA#gNH
zTPj2NO#5;+G@omS#-Yg3=KKfOa<%=d!>-yvi6DEe9sMuH>5cYd63mxsA5akOt#(Bw
zSjx1WZh`Zi*3p~NNZxDxK0~Km`*$e@@q;$MDSGiy+jSkh_@r%F3&79XwiH?UqSgO{
z+E;By+ErC(FZ_+7QtRIz#W(GN9JEzww=k$V>4ws*=d5eG36?hK^uytdi|*oNSlFm5
zrTe-`H{3z-lFhoH$tYZP1NWh8TXcP8xW84`htfyfboc&&aJw#vc3eAjUfn^uQx~6w
z(c7g9_zfz%b@S*8@2+b;6m5HSx>e|shi)rnf9=&hngVC`=~_}u!Bclv53>Eb$vt7u
zOV_e9<^CMdrL2bZpl%NRIOLG7StHPR>yl|?59_W_YRM5@I|-ydy2|<R`>3uT{W{~A
zt{J6=`s%h*w)b(}rUn4`>B49==dbHO3V;CJ=Rt7$ly37Ba0cprK91UH-H3enbVk>u
z0qw@l>YCIAB1m_S=GS0dL)vPE=%&!RCREop0$mH!HE0Ph&gnEiqjp~B!o%$gI(-?u
zxTsq|OVdlb8l3^ZtV?SRVYu!iokm^JrBa9>LKn@$Zlvy8AmCSZ)99UgO{c8G;`<k+
z%iayPXx$o$LR{BX{RF!)x^Z-XdqX$jHfpiD;6V6vQ>WMk{4L!i+BV+St<A-#-O;rb
z&=#k2KZ_pT)ph6rK)f!Gp5p{vok<Yh(``(I@V;)L7dR7j_iMw^B;6z#J~@(gyUsy1
zMYqifo<7id4u&*UcWx(y4|Rhm;UrDxk_g}<of}0C9_vI}v_H`eq+i))=r%=w?WxX_
zk_|F-rN@EG(m7Fr%ro8Hju1ZAl_WqjTQ_7Jy8S};mG<m8x*~dg<~nq9zM-0@i>A$Q
zfv$7)(S~kTBM1w1{f7hbN;k9;G)20WHXw?1D<~XMqKlxA<ZE3trNX_@RkjAaR5!X6
zYHxMdXk^NC^);xK>*g<m<_FzydPjZK*{JQ4?$UO+{aNQYOQ`@~bmf$i_EmRcH2kj6
zZR-bvmAV3Vkbcwo%|q|2baT(3aMGJ;*j)6U^fRuF`VO>y+@!Dh5SBLUf8|iP>PvQm
zWsBZI=ZjnQM<|HxrteAl2;20}EKu35Pk#%R9r~4ybI{qTPcMaU?)nOf8SK%QUj^Pn
z|9Clk+N&Rv4-@<J^&6wxp8C>c2>0u&(xKv|Z!-;E9MDe)LUB;Pk0#bb`o2oEdFy)|
zMeVTuf-4Lj(N8ReK_C5~t!O){U-$>i9@AgRq4%G!z8fu7kL$m9!;+ugo1PYb{iKi3
z3DCD|3zZXk4}Snp>i^sYwp03|fzS-pCsAVCX?-LO&>8*v;poI!eLwt74t0=z8I4o0
z{`V@dgy<W1!9u9MOodvQo~472bNcBAD0%I?UjG*EU(i3Nb>Kz4=K<(k(ktkBysTe$
z80N$EA7_K~ihkKRxEAr<r)&BJ2DC-#ci{)>>S+A}+WB19pI!t@G5UtIL%g9M))_3Z
z`d4nCzNyz!*yWafRXtd^qrZnAA~@7>`X7G4klxk*OOt23-a(ni3Ht3}0N&F-rfp54
z{^&2LCFuv#jZM~nq+{q5{T~LfJ<xBY_(!T<Nne0R`ngx(=wp3ZcX*MmpVAJ(C;DHS
z1CXJ=HXWKz^)7=jT$%cyR)9Cp(to2+)H8iII?{TsKQ#xQX6w(1F!(~h<OUEq`sr^x
zjN{FYr(Q5$p!eSowwL<H8_`y%f1e55D}5f_v?9H489Gs{|BZgtT%vcS4BFTF+<#EK
z(R;oHpj7{uBIR%O>&xNA2YrYD>mT*Ll(79tzxEA;pY@R~q4GulPZN-R)sLr;afQBz
zBNZkp^_djm`KAw}6O=0bTtYY*+8u{$&IYbA+BO*4#G}o{a4HYLjfT~<25~j?r0wb!
zgXKB^TMa}1K;dQ>;)4O&X82VJz;;6+ts!<8roV-7r(qt2A$A#lqPOoJ!~M|?c;jJc
zM3M5n1|wyE?lUx|!z)k2R*G@&Hz?YG)XQ+N6;uuweszbzgN93V?sv!#N_M>sJ18sZ
zu;D5Fi14Ukod}j=hITT9z6N^;0LKkmics@2Gz&-JZ|GeEH#ETT+rO0Pb;4kr4d6+`
z{s0&}Ww6qa1{y*uAUtiDP=#?0GNe62XMzoj=qIlsh6`h$5^8u#@w70*ewwGw8De>i
z%y~oPT@)7#b0@*yi-z<7XkId`?FyC4hGvm)JKQkS4Q*Ep15Nk~Md}E{Yx)UYq=6d?
zr=kq?qfv`CL`7qOuN!V}g8MOs1&dL;VGwmNA8Y8a26k^63I>AvmLV?~ZMO|IHPF0k
z=uR7<c*86@&PgzQ91F60hF--G-Z%V9tLH?+l2`ze44WomEF8&(zLQ`##c-bX;13L&
zA3`<NP^$vMhlalbVdAl2?sOp14Ye|%^2E@f0XmamxZEE2r-tqnlFc;Sp#!!o!%8gx
z&kQ}x=;(99D%#6t8z$4C&<n~E#e;9?z78z;h9~rbE^rv;Bmnr*kRAs_q2cTgXnbWz
zIS1|{Lj^qv#fHX|uTo-Ya~8GNhO;fu(KiNz0<}_u+YFGtHB7=^byAlZeDdJ-J45tR
zaKAT<q4m^9!$Jylelpl;<M!EbXB-TDF|54=_*a9YfedMd;n%yURvLcB>s$TJ5HtiP
zstnp7)HWD5&=$nSxPhM4jmE6zXxn65LGR?v#?M|5x*8krhQTeyk#Eqp)i|&V3OC~%
zTDxpB&Yy?2?Z%We2zMA)(=QQr8&fEI#NB9h(9PRp{Ee1g9>&L%60q0kJQ{ZQ8Euq!
z=xJO_XXN{hBd<Wk%lP&d@CS^w|AqO3MjNet4jHR5pmN0cQGqreqv{)QM~zVwa5-jl
zr87%k<ANgG*W*U^JjU10IGVOv{>D2JMeYKObt!k?gz**~KAbd`lw-V38S4bW;2GoG
zC<xCQf6Iq3$T)%C4#CEbG;4(z7t<>;)OdrAz{8BnIUqY{baH`D=Z$rJ(X&fN8)g1o
zHcp`^PPoyP{z$|XV=jfmBaCB{=*Q5J#@!iUyJ{@{0PbtXi?qg!GKNx`O|<d#Viebn
zW(g`W#u6I!o5r0ZL37L4?E#A0#`Cm|yJNi51_tAds{c^jH7;>STfEVi&i4|Gw;RE=
zd&U$xZo6;vZVK~>#)Um;t(Ih5PI)H}j7?*qlWP2%&f^~%vm78zGj{#~wMWKPZQ;dZ
zV?I4e>Bd?VhIwLqu@h_=#td2nJT>l{fHBN8F4+y1EaQc`Fp+Hx)x((=Mhl(O<rwqo
zLzruvPSKP+<3`HXcH|q^Sb!)n9-yiJrO}CAs)fe!RS*^%J5Iomlo;pI#_hFn4lT>x
z808L7DK$E6MeVK8g?<QFW;B^GYVVBWJOOxbbf&FoxiOuNtv?uryD<3CxRN^f#rTr4
zlD-<t7hz;79LC*S0jxB>UysIbMxU|Zt}-@x4{j%uie5m@rgaq4++dncH`c|}dmQ?-
z(L{fJM!m@tG!>d#O<Sh}?q;%6cx{_$3hl_Zn=&$CcZaFp-+=El)u(>Co95Bhe~;-G
ziVJ&~93R?4XRpcn0bcAgDQRZ&H01?DxZkv_H`u&P>*%jF957952mC?PZ?j?dkm()m
zZoEx{>5FsNG?<RMj+pE-;hK-BXf0TdnpRWh-Z9g>Jk)$mJ87kQ+|-bEdVZ#QPf+tW
z-E+|UB)~M17KbNH8*ZXFX_`YhL#Ip)?*kZUnnAx~J8kMi0r)ef@iqw0njX<vNRa70
z?V5v4N%Tz(G5s+Tu7#TJP&hrz6n7WJIa3+=blx<J)`%BOv2>d*ni2;CaLF_}kG_AG
zP5auTG29e-7`?b+nz9YujxYtTL=kB^DnjL|sSE9{u9?^$!4_p&Pbq`ZrcgS>xNhn<
z7nWj7jv-LFVR{`3?pRY1O$|3q>#Y#pGW|FS)VEE157h3Mp8o~vIFq#jt<~<DV%7r@
zZz{Zp#spIgO(yqD!KcvQ`=*eQph+~{+zJy(CTBV)Nj9~tfzeAb&7f`315@mDw56Il
zRH1liI!bZVG*j6T;2xRg*N5;iYQUwNI!B@Q#Pk<ULK&tLIPONGv#B1vw=+$_^xn=g
zeI=S_rc-{XJvYUt!I^B+;h&-M!X)JZm}6Q!8Y;P_&@zzbncCCqH{W#T20Bq-TGkJ>
zS0=w%&@3_yp<j*^n^qRXrxH`h3KXwRLukHuW2!R*g`?EeE*jl_Yq~^Xr!vzQT3o&}
z)v5*a?@fU|Fi~zwjD^7uCIux&d^Bk(NBEN|j}lrxo2JbM?u%*YL9l%_g^Yp03e!#c
zgD91z#S{wuW?I6*Zk1{2J9y}1u4}}-b2fWZcx;2iY#s`ri}}1BjT_CE@v}(vCUY_^
z2REBrh-h;)msLl9&Bi>?Y&E}l15!7$lneYev)cf8vE5v|Jv4WiXHx#ePV)x}GVC(P
zP&UMF^GF(Xck|jFaCDEk^dA%+=33n$+-r91qIJqXv-4fxJ<WwUVN&lm|3%Zgms#b8
z+5z(%+QuC;7gCh{kolM%9(tQ+(F}9goah4F5px11nfaI<v@tkp?nx8PG4t520Qj0W
zErsTB^Doq2KXWE6vi!{r)?k<e%wrw?sGcypj6(IK*^MH!r_2oppa?YE5`jN$zL^da
zXUz5JZ0)Q$ixQ-Q%!zd39BdAvAH{^2_q+s4sQCk>2#1;P)A8y#bKxqC#d)*&3#c!c
zul#`GqB-dy;FrvUePQ9Uc|t=6s^R8+ei+#+=Ja>KN0@g|PG+Q;H-P4<xo%AWubJDa
z;YE}=E*rpTvqwAtH_W>V0f;rvr?k48=EXx`@Rm7;_J+63Zj?cG$K0IW<#Fb3lzej6
zJk|v2cylc$m`yN$SW72Y_ssb&Fmd0UMyK$J=G1u9lFXf60H175c@FLrb1H3~ADHJ*
zfGgE}oF1=-=1iLP(#&U@q4vleITb38&Cxxel5XC#9<?Xt=4!w*%=V}7;;ES*g<7UL
zDG6?8nHQBZ`2IaJuNaN$bMx1KVKCeLWE^TQ%u7XZ=a`q&2V1Ur|6BN!XFfd(mh#PK
zXbLVchqMIgOLGJrgBO~!Q_%ZYW{*+86`2QDL9^Jb{RNyQ<|Ri^du`69-RB$gjZ5&N
z)I7K=s2y+3E9@AIGV}0GF!9b@uolI8^DYV^m752hLGi)7`#iWmn*Z(q%}?eLEm3?n
zFQ)hI7jvUFQ2A<pW=BzB-gg?_SDM?8fXX*BLl0Y(xjRM4oh(l&E7IB0L<=uASY+Dk
zxHv5D4nb$5#Um2HO_pC)Lua$)FAwOrTH4W8ZHuK_2+VJ_H0lOYH;bB5!nRrP(+qs^
zETx@ccZcQ4WfVItBmBU!%i=l$#coRjS_isY8e9X}9!t9kQ1P&=TMx3m7M{*`_E{WL
zmqEwV(v)&S_gm`IdfUtLdKFX;SiE;*EWIs1K7xmbEx$BF+Yw6wJwiSfn-^+FEpI53
z?U<!SD1^S2viIOVZW&0=lb>Zd{b?b8%Y8Gb11#R-;l&9{CG8?lTDCWa*;AGp6aE7*
z(6We9?N3|6=q%=p<yu4NoV9pSXer3zdkeK-3sVG@5KA4(dI_~Wrf!E>J}ricbCxl^
z;Nf{oV_NB6ut*UePv_RcPdFgFVp&e{{|L*w6!az1GEI--s->v~#Wl;cToh53eso|R
zZ5cTS#dXUb6^a;(u|CLdSjKLLp;*iGZ_vDH=}c46Ez5=OaN@RQLVal7v8)foortsK
zRibv+GLJ$H@s<S+A9$Z&8PXHx?^%AhipKjEX(4D5E%laxCdqOs3`MfVo8l)a79%ao
z9#|fxLo?MfjW!|=E#))^rCHu3q3w~Sa}jEfEuCp2lWs|+efbkhP0BgQuyptY;Zw^v
z+SX)RzD7F0on`460N<Wjj?x<bxn)}on9sHxE=Jo6OZZ(BIhK}za5UGlp5jb-mi2TJ
zly6x~IVlB}s#|dFr6v3kNDD2!x530KOA}g&6j^G1g=VqEMCbG+mYmK2yte4yLGz8J
z`%*duEVT?S1@~LaBl@9SnZ=bJ?hlqf#sKlr(qJ&~pDa)4xc{?d^L4a+u{5INzps{D
zZ?IKZUb#V~(jwB4`Zr5w%Au~Ze57}(lXdhn^u^h__)pX}SZ%c2cCki#p|;U_4_iEk
zdXu#W#a%XAD?PyGYBjuvGh3|QW6<rb*5i~q;bzUE?A~qG;5f8xw}w!X#18A%p>SrW
z^>iL;yR4%qA7Zz)tQW}Ktrgwi{T{17y?;EcB1OseTE`tk+dgY-2F!a}*V4DavEMp|
z&Zxbt^QXbm0qY}*s~xn;v;{e2-ArpsZ|eq%z#X<OqUgdA>+!2l@v(k<hK?S!-rj?@
zW7eS4VDq&K2jJmxYby$;`&oaZN!s7Kp3+?ctkWJr^Mo}l6vC6%4e!8m%3)2e2fKk*
z#vj$wR^>V9oUsN@1<hG&SK46)Sv$N&5o{enw=%@~fW9%I)&o1>OqjJcWjLO*E}sbD
zdFxUhnis62DHwCnx|-H5m#oWfgY2^P&n{32w<;+M@rw1_Jopr0bv&mZdqi5V(cfRX
zYW=(%_-oeHouCtC?HmI{v~^}XxOUyT;cv9XSi4>V=?&`|57c6<p7lU;(|Up;=eMkH
zDC_sO_1tWz+_8>24bC|0?`Lrj?pl?{;YGalCLL@hSSR`eaL?-J=mhTj)`hfzO0?!p
z!q6mH1zJ=lTiXnWFvYr<LPHO%tyVyoYF%*=Di5u5B(y!YD!pMT-TK=-bmEEif)V~^
zScg7G+f!>3N*Kws&YBBhmh~j<Af8#n=&^ckt)QHtY-{Ij^a6Qdb^Z@d<yb#a_$SwT
zj8d)gtRs5CQoi-bU;qoO#dpy5(yGq}ccE3&A8oI!3+QJzMb<2Ls1#dIUj(kix@rc<
zURw)O;O`r24BgjKYkCL(Z>_EAFt5ydlD5$AthoY3mfl-aDgUb6dWUi?K3E@K0sf<P
zZ6I9yWSvPd{?AtbnPB^3&Dew5S8M2g^rFH#owDF7t&8Zf{$_piFK|`XFS#(`WE)x^
zHD}w^fzaGw8@nC`U2Ko*!uyT3;k4)9Wb?eK#P@Hr?T`VMTy5^ui!HW`Z!jcVZ8`KK
z6F1u>I>Xs!^Y(-L+imM;f4#%jY8^Cp+S*b4ahEN?6)L-JOIet3x5d!!r}x;B=v3Lm
zw(D=G?6p0kki$OPU>^uQZ6!IN-fzpO0Wyb|?FP+k2W)d_XM50g`z3S^*{;*i-@I){
zx&e6D_JYn}j@Wj&!;+6}+c(sX+FD0o)Q;KqP-?KR?RGE#$8E(*c;RPTQXk#+w{84_
zBES~a0Txc!WJ-)aX=CXG_mnMaH4FthY^&=+=d>;N7gW#Kf?Gi6tnD8<`3ka4RDmtn
zc9pVILu}Sv&<wSGxe1jpn|TUI&)GHxLwMe1YYEpb*upmhaM3or5-OK$pAcqNU$Gtj
z4Ml`aqELIJE&DmzuG;>jDe0QcHo=NA%J!7*TD0v9t;Mg~dV73ZSliKqGK+87s)Ats
zw(Y@VXxy>&DubVKwz^GFyKAex1!E9z^QS;sf^FRl)b81wC=>3!t#1r86KydRzE84E
zSpz4MZQCjApJF>sIk^vPi49;b)wb1vwuiPf+L)%<{!Rz(k!{D|BCtKS-R%$VblU`9
zAfDKo(B3M;rgcZ#Q(Mn#a4pl;{18lJ*&<p3_{`>%44UV*PjfLa*|tj_S%1`abaX}~
z-*%IB>;<+nv=w}5>o^aTg|_n5sJ*g1p{-z%Z3JaD7TY!$QIy!)Uk2c{?Z8ub{l<2l
zaw|%0Z7N{yt*xvCfHK>Vx)_Ofwz;$ud~X|{0nTz;U78R+*jBZLw;yez9kjatWOH<a
zyPs_%Qeg0lE%G%?e6_t!hlvW?H#%yqw6!S!%{SY@BT%Wb^`|o$C%d!`ZO-<7qrtMl
ze*GiNyV(D!i`qteTPxZ&+1t{RVY9vYOaNT%fs`(?#qRwK=C|70%yyvaX8-9D9NuQ<
zD1TzRy~8{Jci3H5q1b8fL7SOf_E!`;-EEJ}0k^w-8D+KZu{WY+mxsON7&Q0VN71`?
zpS?*Tgr4@RpHSOxk81@BUiPzt06$<Kcnuc3?G-1`iNp3P8^zC#*mYfj@Uf?t!_%Yo
z$Y`(~v(E_w-q-%2FUIS*{RkyF``ORXVWq#_M5F=s?Pox9!fw+7cha7=5yO4TzLb{p
zf%cJBz)#!bpTgi7dkme*oV9=W3q_E<CmrSn+ovSa{vpJEs19gC?WdN&M40_QnmNze
z-_iVi-kz`<#RYpnED#s%8=e7w$?hw_(q;RK|Iik0?@S@5D|Xk}uoPiW9Rc%^_Gx>e
za@F3sIjFDM-SDSi)KPXPC8(qA>z6?Dy4_<EYK|EDFZ9O%ZrE>Z05I1656x0H?S2&0
zzGZLJA9ios*My_(j{T%3YH{}cYoT)2zB?MYcza9|+)l6;g+h4G-v0zVyl?Ne4cv+L
zXo_kj*$>h2ZL)m?{r!p*d+9a|*8}_Q7O;@&u#Y*0#)tOYR3OsqyJ<ptWY<t6=dnGL
zViM{0Kj`OxPwZ=H`;%ecMR|Wu?M)H^$h0q{+}JF;6a@3w!;C=fxqZxM_>^rIUxVz0
z-HU$ApJN|z5rAC#W}1ld>`Ri+mT!01=|^4#_H1H%X;;%CztHYsg^5@8&L06RvIkQ{
zv)EpX_N*oLCzQ?i+TJ7>ZEx&5x1&~SFVDqTytO~0?@yWCw=evCXLqHw`g{8t3bdEo
zd(d(B2lNFNKH8fPhlii+|2bx&@v}XEvIM@^J$nH0)t*5|FW>CPe@Cs#ew$`Try7Uq
z!h~~;%qzfes1ZU*Yc4fDYoPLfadh2rRUJ)RlbE8$B&OZodv7FaqNW*RnlT#lsxd{=
z)I<}FB}K0k=|!4|bdin%0s;b3RRrl(5u__10)l`P`JVayn&0fsJTtr8b9Q%T_Ta#%
zdJ=ud82c#H<;d`y4@@V<vfXHOW<-1e&V}*yA5d^*RF^}<jS)Txd+v;l{S>A3U_{e3
zJ5R>P6j$<Mu-=7<<BX7BA>++hM8y$4jM5J<USCEbZ8H2AuBXBIGX|+P{RAWYMGQND
zF|!2*Pcpuwt!N<QG+pgD#pn`Y*g=dGdY=X}&b<W85Jo>$VT3a7^XZ~;7~^ISM8g@e
zYoHjxV3Y#pG~*Bz5=1hb!(r(R<NbpmQH-5xh(t5$5}_Z%SdN3lyjaF!Dh!KbyvTt<
zJmX{fbtW*1>8+K>D4=KaEW?3LPv;o_(AGPNv7M5t$qakczgp*|Fl7Hi@jPQb6_Tbh
z>fA9=X$)Jsh@Q@{rJ{-pjEwi-eg@+gTDCG7r;h?Hi?RP1a2FXTKL(f0`1CYL4x^Hs
z$z}A>Y3~waf({3Hj9`lQ<ukrn0aC!&lMF+JjG}sYXf0xF-wzYTjD-?(US_=Pg%Mt1
z{F(yuR~ZM8;+j{&*lq#LH3s`O43;w9^+#hFgVzU3*BKv21Ff8)VFRs#5lefcO2(l)
zh*U8+f#9kcnG4ZZ!+7s07^-DB9zkCnqdX3J^}fITDY0$|g;+C#c@yxr7?JUiZeb*B
zfz39?nlxBxXH4p#+re<LLtiIjjN(*X3|$}ex*4k}lGelcjb2W77}EhzxXT#mLSHZA
z&FAnZ>SGvs!Syo~zrf}_M!-RE1B@4`6z@Kx)4Ck`gACUmU=J~dzJbgz;}G44e84!d
z3!o#6g%p7pWqeGx7#=dV(NANH5u64x&ZuI-nF+=>Rq*~1;}=Q>PBK>0jp-@ICv*s&
zX2hHVnPGhA0fUbjRrLLySq6VTxTDPUeH25sW&TZ3R6FJ$&%+CQrh<0w4$SADf)~e_
zEp&o%WG2;NXim&`Lec2VeD@E4x-hQ>U@)%CFR7%}jX6czI(KFV9Zx)%Uz=gcli5bA
zq!+XBMOZk_-1iTNH&gj1^n93K$J0sEmnm2TG(Tn~6_EHdRolRwV17tZ@&Kl`7oaDZ
zQBt4<GDH4@Yp0m9UVsKMchU9jU?%flh=ed>=#&%6T$c;%Fy>wz6vCO^Pk=-)SM5jN
zX=c-3FdxY@_QAp#X6sV=SWOf&j`FP0%t?F9MGP~y9B8pjPkJlGF}Vjp;+Zy7V3)x3
zIRME-X4W2no@M5&1v$t3Dia2im^Z$I_sL8zy7ZC4+_3|V=b87Wftkv@y#xNHF{}MC
zhw02udw_X?nM~<(YX)=d7CJMT2OGg=F+K01^CENOb&zak!x$QKn8tr#H<#&G1kg*&
zsS#MpV|q|6K_QbZgnAM4`!cv)%<QI1N0*uDwGg?&obL-~t}?TzK&OQHHa*tYm`9B8
zqLjI-7LsLFW|SLTyw04aG;cYxoI;Kj%)dIJQOR_nq*E2MQijHAW(j34YnUtQV7HcO
z`!Yx!GlAj)^~~=);b8-F&=Vq!%q?ZWZekXG4!s-9ssY%&$xOckg=S{V|8EkRJbE9r
zFs+Md$I{C5r(@M^rsg6<+n8@q`E@%}yB(wNU~(yG)XBUv2V56(-{%-wH?#OTa6QaL
zl$5{2ETZqh-(@bQ6kjhh=^98M^DoMp_A~d==a=s>jU12x=2hyu&)iCh<UwYPwHRna
z%t)&7A7=iw36>r(Q)c1J2vbuH&{5`tIp}-H{F<sF$C#e)pl_VHpaJ?5OfOP@#Jo#W
zI>|gpsgWsWr2>DEY3AED7{m;7!&~4UGf%w+^Rvu}^=LfGnos9sTh=E>sp!d$b^ljP
zw>@hY9h4ndQ?!B~V=em>#F5o93JoV#HD%15SrdbB--RW#MWZY03o2!BWAzq*b7$G^
zLZ1igGYar}vYHwI=EWLf1LZg?<y|=H&3cvUbbMIv{sa+UR<8p-s65Y)^-Vai{aH2i
z6^0Y6Z*nmS0W8CEkdv&XPVh94HAHL4Dc0S0p%}#K+6OL}^*5!%Ls%Cm_7=(tH(*M_
zSg%sWS2#;WUwMjP#Z&m^42wm1k|-9Rw(-%d_u|0Cu);#=vVJVfN@?^s)<!XWi)S6B
zeLw;$wishdWZClJ(^=Lk+TfjI<$8llV!e3`BFU_@@8MbstD_VK&$Ip|M^jn<8v#jU
z#n8f%&Z-&!$_3W%yV01zdfx<RGFdNlgJiL?DNka($TGA6Et@6#1u!|RDGDp*vQ}`Q
zc!||QLGL`)E-gIFXVu@ploYVmU&TNRSwGMu7O^Z(1E!eOLs|UGtm8hAyuym7gZ)+3
z<p0oD!t%Hd?iy=|R>@M<gXh4NvF6fS>$;WIYyd51Ra9bx6|9D2XjHPcn}A)#dUODN
z)vOca=&NDPrQB03>n$Ek)UoU-mRryIk{-hb*2ZS&HL{+jb+L){FQuMtuntqa_9pAO
z_duFim*}K$izTE0RSWA5?Mqu(Rwm`1ZnHQPuWe&pl0m<nwS?|Tb+95I!EPsOco?LM
z<rM}?-K>tyu-n60JpgitHB3ppyDXCs^VG|7rn0C$mMhiQ_OsrhwdNiROB)_M)*DK2
z_gQb#IeC!v4@J<2SpL?R05i-Qu!U0(SYC7>9ARB%!I@FkCi=-gWR+4Da*TD3j+5i8
zgjOg_u-^X)+#^<{A7Ca~seW*Kie*c|f@#)94~WdLm>V#N$E>TiFh9$hv<ErL{yYT=
zwrrPT*t28b&ZPCvo;{1tw$5{8zZ3{XCwAvtU^}yejzhzRJ=qOVSN1gR7Twqu3YoaG
zJ>P|%2m9V6U_9COk3qcHb~Mk&*&APhzus(jIy3sPZ_;_$mwk|)dq4I;f9UzMW9buF
zC)fuTQ@v>bTS&jzlWY^6cLLd~8!-u|*n>rICWsyU6$}QmwUlfMVGkC7gt7zUVIqv3
zlMRJ%b`TXXN3d5t0TZX$U;O}uNcJZbusOqaqgszBwqY)~Xm%65J!05z6+t1E?Srkh
zbzU4hm8$gP*{{&`-~{&iJs^o}5uK{fvVWjiKgWK>5sFD{9}e74W`BDXmQvUyv@bo+
z4!;hP%Kpj`&ZM#bz7NTC_7ue-FR%?1WXxa}(JGqBmaK$G7W;lLJiN%hcn^}+Y<2|&
zFmu=`(`e0QNAv>i65BTuig|1c<wWw?^B#jMV9V%}bA{|`dfgSVcTiTXnC(iZ>dWkc
zXMuKweV#T;SJ_|e0ZIwGjB32Dv9&88Qp#RRHO^)1PI|(xvv>UslyWP34iytru!||F
zQOTZ9bs1IcU+9!t&DKz@Rt@{{K7iJ;<&>POV_$g&3ia$dn&$>~wmn1|*&nP#UlY5#
z58MrQ3LUC%vLDhRrkQ<S3+@)XV+MLH?0*dyZYz5u-CMoQwuaDgppEU+2)3QAcos4p
z?EGSIo$M#*PF@%LDVmvX_QvZ_yvuIcipE~Ht1Cz!`{Fnn``I_|0OcOLmu{91u+^K;
zcb}a@;jTe;*aC<QvETj{6Ew_j`4!v)_P-aPFv7lNZGy}wd&^e1_>lb>6>E&KUFrVZ
zIQtj+u}!dx!eIUpJDYONlk66X(oC_FH$Y^XosTWlycxD@1VkRQ7cel-vup=9fF0!|
z-3PJd{CWdE*>RS6U`X~H)5mblfs?Zc(8o9no}lN?k@GCwPIlsKpvTaeQ(Ot+!g*mW
z47zeI(n8|KiKldeI|u*c4G$h?Q8N@gIW0@Ud2t-+t#zD}L8%dM&iy-Z&4=?`AsT%-
zIX3|2$0-%V8Gp`j2>MQN(&;!Gz$x#dk9D8qd_k|RKu%F1Ku>YPPr<h!j>s8<3Fb()
zz-|bqpUN;pIZskibr@$8o&CZ&_Rm2ig0qm4PNz9vErp3lPA+9@&v2w#G)8fP>7k0|
zeDw;TV>lnv3nrFh{tkL^oOPwo;`xi`jMc+@0%w|*(L~ODH(;OTOwl>`9Oo1j4JL7(
zq*HY=XP9C>DVzj)r<~_FJ_DapImI&|X&gsHROY2~o(YGg3!HE!EM;(()j%?n)4CCQ
zSsc$Mpj_nm?}tJ*hecsuYYr#xB`D@{UVjrBmpJ=rym_20AEPs$Bcu0R0cYDQXe{Jh
z(qY<)IBnmdv6xd&ML?H1&(k7tg>!+nidQ)Y@50|w&hs5;EaSBQ2h8i7>$Jv{bB@TM
zP{Hv$2K7pgt`=OCm9v*hRjN6!(?33_;p`5CVl4-s%f+L{2^@eI^_*|$`EB4#oq~x*
z&inLGH*thL7}E_-8SN@>a^_z~Uo&Sq77DjGu5^xV;Uv&g(aN#k0t>e}rzjxa#;KuQ
za64za2t(@NSihJ9gPokWDYMhXSwQtV-JJT5(b>Z}vj=^5IH5G`yPUbSo$Td|mBD-;
zr-e#d`#Ellpm2}#2W346ICm+IdY_Z|A^HY6+v)u{#JNH@JBB$m^FSVO7_mSZ;q0b8
z;wZ<_`YO;Ka=zLR6JwmYuR>#-v*KIGOmM0e1MLxKyc;5uoDXS-J;ix)E)=IZJ@jLn
z;bc>xz+=wtR*+fFL#p#R%Jp=Cf-QGX0u=1HsZ@Ak&mBGs3l3acKd2w$o}d7qBloXh
zD>R(ApR9nWGq?Q&T3xtfUxT=Ef6Yas8+YnOV7qgDoxyo<ht%lv<m#Dd^x~#o13AvM
zQ2xQ2`++0u`f!WvKzzA#w!^L;_jx)z`*Y{U!2AjBQ<Reo;C|c*?j(2o9>qWcxuOS{
zuT$Jjv}-}A#}AVb%ypav7s8!G-?j<mZlQNV825Sl>Pk5G&>ZMTaI+}1cbdzm($q-q
z>;-suhP(ZF%ySf17=ylO?zSJ$7sH*e0Ey)~(#|@LdrW}7MDC9<l<7Fj-AWmybKKh$
zpGo4D4ud3fpMDk-mBPjUNyMYZJ@p|5n#x^22K_Yd&L`knI@iu0dKb6{Y0s6xwa_QU
zGPzYWv@Gtrb~tm9TlzahvblTJ7*Y=RufKqq%RR^g$|bIXKG0;%<9_oS6!W=Lw1+9+
z{?QKXLT>EWaJY#34_)vm=6bZF?=rXP8*o>+;x~YHl^e4dj+St3y8wEPdu<4oO1U-^
zzAocVQCR0X_kJoA%DKN>fu#y=b2Tt4xh@^htK#Y@AX;tZdVh)es^K=ZptY7OqJ)1P
zcL^J$o?BiD#RhHwEh~*&6IB*8aalf4yurOj3;j**n-n@|=60_FcZ-|96n!mR5mhp^
zau*DP+~#_21!?2HOXa=o+&^-m(7_eF3J*KER^P+W=;HeQ0)yS$k3NILJ>05fjN%SA
zkq!oTxqs6hq?h|Ag;)EyZ(f3>er{+hB=2#bJP!2%?oV?8dY`-30&b8SOzF5GZtN0p
z!`z1yu7AK?zXl2;+z%*KG0J`CCx|@ca;)@D8so|-_dL!`r+4TCcP-t~d&EVx0v<dr
zoAMx2+~=ukeVY3Z6}ZlDJubuGWA0!1P@m;SQU>EFFN;cHZFwEEVYTCl4r12qd43@f
zap1A&n0<`5P>NwY@>=MX@5F1{K<7VaUTHhfTzI=E`sd0UOoYB0?>a36p1jq47=;(F
zViJAFd5#n!^X6SNLC=R5Mq4Leo;`)g{CKZ=LBXFlJ_vGx_x^7{3E(|TN3N5+_jh1`
zfxLf>7|SW16MgPBh?ldI_MgGL4U{Vn;l<4XOek;dui(OXjClAI&QsBEE`s+T9mP-c
zvetr&<k@D!i!;23bQF)`1yXD}nzxW5Z85y;yXcGMxln96j`zox0E_2E(z`Q(S4Cm|
zMBXM(pq%A>G)n8=IbIAG4kz*cpi;AB-p5o6l)@`70_b^O3SI9^<q0Y1nZ|q87ue~%
zEy3u!z_Z^7^BKIuO8}b5`=}ElSv(<?&s^kL2QchxUN8ODb9l31u#n5sQtJ5<@9YK`
z%HxfULfx9rd+;e*3wVZ?p;*ZKuN$O@7f1D2#k`+s>voy<6&1W);T_1w1YPCDQrS%j
zZ^{GQHQsG!cv#9?=LCf^p6M@;>%7Ypt1aiX(MNSEc!88ctK?m4hh7zLF@=q)dGWMR
z*I0QB4|rP3%khETI^N)mkg4arLOwO{eC06T$ot?Mh&1tZ&!X=JFZ@2ndy^+#1(9an
zDDBK|@qVPzf)-wAG(=i?-jv3_&0FyWhTX;so`rfl?@v7(?cnv%8M>1<w+-rDJnIW<
zV4|D%>IKO3@CM!j_8s1OFHFr{o+laX<rTdMkv`tLbU&q^7xM!e@A2l-Dn7uwa~p0C
z@vO9-4D$?6gL}ZMrI{V!EuzceqdXsqzdYo96A$$<-kV$C?>KJ-B9QYYc$cgcF@3~4
zL3_+e-U#h&r+A`GFgVSN7yy~!`O=;3$Gn=|AhWz@)<EPaKZ8Plw*1gnFbX^V(^M~R
z&kw%|6bJr(N)sI88)$pv$lq241t-4G5!iL+J5k`-g@3UNeXjg9dV2oc_=hNb?#|a%
zgLv@&qFb$={6n<Y^Wq=&!9b7m*HH-0o4=eko<4jN50-rS2R{IsAAi&i3jX{>X|Q{O
ze`FZL4&eJxX7(gM)P%l3{%4UG?<xN5B=my#o9NLF<|pr_99#&0OaPfs{@b*t4&#?E
zMrSzx$|`UX{AFv<cbfkOjVY2pNc)U4{OBN%DE@D>&`0y%p|@5Hzk*JDv3$86gNWl-
zQK3ORf6w>uFoEw$XP!j<R{EUOS$+nEX3z08_(53bCGodXDj}J_f>!tx{@$g4InVc{
za+p;9gT2sC<8N9FFVgunv@BfUZ-|0^2EQT|mNNNA*1?M`{vJKNxX8anxrb~%^Dr#s
z@H;4bmCJvLO6V`~jqjl^kH2Ii`ttc#8__2y;3xe8OND%!E6^|EC+xyNi}}VVU|;4h
z3HP1r^0M^>DxSE;|C<T}OZmTk0<<!I^GzsR=SR~;i*mm95I`&VpS=OSN`C2jkQ)9c
zws5qT-?s=B>i9o;V-WTH>?r6p@QrkcZR7_~d3_WAvJ{dx_<JNEH~AxXpx(^ix*H<5
z_#3QL%-zDTy9Z0Hd=HAW-sY!Lu&<4uyc+(t^Ii48?%*G`K);jUMTH<;{QXo*-p$|m
zGemm$O&QR;!_T4>>n?wa>Y{r2MbU7(kH0el6Wh<9bwJ-e{*$z|9pK;U0oZ+hZnzcL
zgZy$wXbkbae}Nan{C7$q^MK#66@4T8<qH5a%D+XwgopeRa(|3}WHZpl`31XxJ;DEg
z>KPyLD{V2}N&ftGz@Fkipt$KYf0qFYGyJ=B1bEDsQXpZLKlU5IjtUA+(|;Yc6)eqy
z2|I!NcR;fj9HgYIgP{0daK{Aeeu5W{g2or2;UpN<q0d>c{y%u=BIrs5sH<R-?uEGt
z0t(URE-23j=OH*Pf`X?&ONliv!5%ta9~Zc|f_MwY=qj;~Afti`y?q6a1z`OI6NllO
zzrea2&YTdidq4sN&(b^lq~Oc<(HAJtc|iY^;M133DM%pLh`wOK;*H=!1oNppK2&gU
z8zjR7!E`_l7mW6Tix3QC0_?QlHHtk)3a*%7?~I_a4I<VkLHKSACR%Wt_Tn*u_5UA0
z5xhyyQJmo1LXddD(X+r#5bUNyN1|XqMd!~7+UXHJCs5JhIZ5y|1-+96?gg-vB3Szb
zB+~@71yD~He0Lt|7X%sYAQ=L0dgo>eG{2!Q%PI(<XY8V&;vVKQTi|&TojHQSl_0r-
zIl~~A1kGQ;?>s?z7C`d_@zGEy5ImreZlR!=GHOMFxs*mN7EIEa|FR(B6?kz)Af}_`
zRe}6z*ewyf#s+syQ0<JqQb8=`QpyC@wMT({UEoc5t#U!~Hgr}9<VWFKrC>+_u1c_(
z1=p$t(R3KC5&Sy~m|DR;Dx9tptf5Fvy+FJK<{Jcm(NUmLU^$52W0T;(9rWE0{7b9h
zO~FwL#xx7|($jQH(3}d=A}F@1fZZza{R9KOEtm}fXq(_I3R$!Z;yhrfL$I34T{{KK
zgz%|Lu!!<u-GY%%pw}aau7SuM!SO@DzAM-(gxy|2^#nxv1Qv=j^$UKZL(V-xCdIr5
z1Q*u;?7jg1RvFKoptJjF&>_JuzTO_MSOY1{JSuou3CV|oyeH5#CJ0M~_v3=Y=Kwt+
z2+s%DBf;lXO*ScTi~^YwY@<54X+a3?4b7VousxyoSYTd`0nQ3W>tOGw(9s{5w!&Ra
z0J9U;QJ%zJxQYcm2jMk}lO7WuwB~|33Rw(z?<8C~gidGSlXR?c5i%YF)KzG92InS}
z=0e0>`0{fw=pmf>6lk8pOLW%o63$Qoz;U7EG}OI?QaXJ42>G;n`U-t<x|w%ED4|M)
z0HH0tYflQ_4nt$0a7z=N7f%TrC{Y+B+>;9ZU?GRLpCQ7v%V0NDI4;2`!h|O%-xw~O
zHwJ?d!tWLV?X<9?A83)ne<=`tMyRI4c9ig$w*VF`Orzagj8H^jxmcmQ1EAxCH|R(h
zFZ3S)N`f%#2a4Au3eA)*IV)`X6)@+7qvtTtB%y$gZ^^=dwSY+x_S4JqyfC-`KBWqk
z>!F_}jC&2<rwe-=0D3`~_Z<{6gj-V3m?=zn9$c324F#Yt3Wpy9C0jU6S?(O+7Ze!E
z6<)>DYn^vVSWc~Z!i@)@m@ix~2($v>lM^6?!qnyHD-vF%V%=h)W&%UIEacOl>59<%
zM{rk#AMJ-oi7+V*maYlcH^a43;r^dtuuRCIjLLOkIu)3f3+w4sUm@&1fxb%N#(!YJ
zS|!{<8?b7jaRo$cgf@RcrdIg%dvLK%I7%`4dZFuL^fd@8DEQkbY<EImlaTp6%-;}(
zXTk1GVe{)S(JU;XYZ|wNUJKFKA~e!Dq*W-P82xSGrx#$TO{jE)-FD$)+Sztkg)v<K
z?G$!UN~BA;=rJ_9g<d8Y>=9P<qVJASNeP3y!uJ0_dWEf0!1M{1IKZ`j;gxTJeNQ+=
z*_Hv}8)fLbFI+~2|ARu+YZ%Lr@IoF$hJ|*2q49z6p(9X6gj)KaQ=>xb?|U$qhe9Lm
zHYSAUDLVd0c((;)Qh0=i#wp>_WVkjh{4D@vMyPX#PmhI2GvZMbPSXDuIx6~#qKUSm
z!*S5F6Ri$`342i&y<HtdhqA#P6K$rCYB`FA`tkR15?z>vPtGE?_5U9=(Q1lqx{87+
zMdv13sRE3<DCI-wdx!)v(C`%9p;g~Y^j9v(aZzSJyzmwU1;TqD(Zn?j)K_Gp7r38j
z2d$p|q5vVd6C(Reco-mhyBL@!MGvo|FHrP=wgRU_<6l#NDM-|~7c#*j9u-rBi2A6e
zDOB``%6P&=J+v_h7u8Z(T7;;i0g9(ZwhO^UijL54=8VYT2QEtV3B9$VMN23;5F^@3
zB~h^=7y8<4oahMs1mZ;nb>I?2Y<f>6iq@7;zVNI_PD}bZ(IwiZCyDH7V~{L5MK8@1
z(JQZE+Rlp>rT{cmbU+IIG|{?F_?s>|T#d#Hq8K~)lp#96fqJIsEG^zyq7h1oTojcZ
zL|?WjXcP2uMEYs;<%%BJfLs#!PSKs`JW;9^vzIUW;1UcLh&F!$>_So3P54wKDyM4B
zVo~}!4Cb;ZaX!cuQ80zKu8QJI09qoNrnvGo(VC+mrJ^s>;YFE9=m@v3i>C7dT`t<2
z1I!B1AM|Ic6fLF*bd_lK62Pq0qN_gvtwz-U85C<p3%0?xI?;k^Xw-`)+91;)x<w@n
zjUtgfe7Y$*M9X!v=;7axyd`?R7+i~J*$DbtMaxcMythT$=<acw$c4tzE=v9m20KK8
zAK+o9h@A*8x<vC|he)?o^pNUEdPEbn(B2W{(Ujg5#byAsSM(aayZb~V;n3(8P32-P
z?uokjfEf@yw;rzD7j4p^Z&0-4PuLw2?YD=>uqcWJ^#`JzLohKSlF%!3RP<yp`W}kX
z=x)K7$gLkfjpLuY(%F4Nv~L~e>yc>Vy8xXOB_9Upl&Fe+oztSgEEt>-<$Vli9*gp6
zHJlX%oPmj>VrL5V*@~Z=k3Ktb)j5FKi$6ul@jM5yfXWPxi67A_>L~tq48%#COyMnO
zaq(p+xQKtSrb5P5tfW|yoA@`1m%59;-2l!*JVsd)Pw_K+h<J(bP_fx@F>@Lwyv28D
z8TApbOT{RB#ST&sKk?yh!1fpaOgE}dhzsfVMSyt51|FUix3>Z;P`r=+pr^!vDKHcy
zJ`!vN8!Uc~J|+<&u3Z5xRNS}*2E)W3*Fh#+Y?(o0gm}p#aHqv>^rf&!aRjA8&xlti
z!ETgz>qi(&wD>#vtXz!ve^d+;E0*tqUYwY3L|?pELodw)aV*8962*!1vOX(b+)eSC
zbK-Z~VK7PDbqg}d;!=turie3-!qR#1=j2+dc+MpZCQba=QAnnXvs7rjAa>XYFEYe!
zRD7N(-tZPIWr^3^0+%DM{vDQb#m3iwa!I`QfAA?!oR$r}e6fEcPzuD4YAIh>C|<rB
zc8kPfM>t$8UQX-hW%2Z3pj{E$UxKGs#ZRk2O2lqkL9U5!)2x?@kIMm5Ca$Ri=yh=y
z4|?U|N&4<eh4=`?|0>1aP4J>h{Ooa9s1^^W!rvP4IMwpjim^At^H(Q+g7#eXV%JU>
zY!Fw_i?vbw&KFQ@694E5#T(-HD0z8Pobv;)o5jDmqwkhDnF`EX#PgHU*DBs2g8FUo
zr9g<ZiBmp>NW1vY`S7<xJWX$(PI28_KzE5ZO@nlc=hJzj$0}~T3^(qGg;$|*R~$?`
zsa~-gy|((q4tfl&U))S<)ID)$4onP)TMq&BzSuqvb_d11_3(a3+`kig!{RISL5>IF
zD1Ts&i2tTH%cyt`MGPN`FXw?96Caob%DA}fN014z)sKPBN8+X+u#@7tOn^>_lc>yn
zTFieQXftA;C(!p;{1nAvXT=NW!r)Pf1BE|rC1<L@*+~MP0%tGTzYd&(g!u|QJSO=e
z3B*y-@jAxhB>9y>P|lL4$I<8_Sy~DUu96%p&54`D=65K%OTxd02@lCn!yulL4RmSJ
zOLB-l@O)gdU^_&-B~km)=OamL2Ing=aslHfdFppK>M!XE1K0`4k{4hiK;qp8w@*s!
z9^o$%C`qH2*C|Q-e&_{BPSEv|P)S?56|){D38!0I;gZWTbVf*KUVy>VD1FC#MM@S+
zpm;`7K!2tvNyrOmjFwacfQyj?=fOm*r2Z>Rew^f2M_7uNjF*B-kjP(yqlpszJa~9k
zBBov4ImxR<;F2VwL7*f{BFxX|@u*48eF&KIl6VTSq)N6><RMK`ObM2B$x;gPU680~
z70!^X^UVolTXRPMog>*zN0nSjAf3)HNq&7EX7ePcDR7=IG5-Mh0*Qsr(}j|I3&0gg
zR?LA&vE;Qh=v|f!hokX|<kO!4c2)8|ZLUfr@BDvcM55XZy;8{^D*#<4ky2#xx@5cz
z3gwb2>s8PS3111tO36emMph*`PZ_pqNh;-RY9!MQ=&P0N@PIRQ61zkUrCxHKvO5iu
zx%1H1C~+DBX_7S17ddZ8PLhW=B`Z4MTC-$1{ittAdU^1vMe-5tH(MoVe**MvNkb;B
z3T=|jwEDJ7TFK!KNh|$;Iwk*7T&YX4?K{}*mUvQqPLJdOy`Sz#*3%L8uH;$|6nZ85
zDd*WIIk^@J{gNZ~=({KBdlk?FlDpLqxi6_*hmj3R4pm?hh9qr&p>bGp`ailS`#|#N
zQ_vWZ<mbcvQHk#xF!4|lsRbF6d|r;eamhm3<4s69=~wkgBBBE7Ny&%b!>1|9e@viF
zOKvuU%t$gQ&3IJ$?Gc!_l^$9P*X*RPd&9iFbR&hO9Ha*yLGqY16~|26rjfR-gk2};
z;9Y1qOH1ek;v&@?gQBZ6{0_WulX^D6yu0)`omM@h8C3i0DJ}dFmb|3T%P@JzrL9z-
z<}G!JgrtwOlU_Q$Qk@V};wSx+O40nKGKwvnkVbq4lmKbVGU!=PN@FMj7AXDYPYmsp
zboM=H1WA9OC`hn0@&aH&r1O2z7b@LLwL4+bOsZ!HmyQU~7a?t<!i&?=q(byXN?#`r
z&q!4ir;L&sS3xpb+Dn&@Vx-qrgNv2AoQJ(Q>5Fupj<-s$?}Jkb(mR*XnJC@b4NGUG
zrIemICymi!FiFyHXiAf%54S)uMf!OQu+K|_DczSU?Vz1Vn)C`EUZhJS=m38~+Co?B
zGNfl|z08z;N`b5_>5C3PxhVZ40t(sEO>?1;BenYMhWT9S`){K4k~D4yoXV3*GXRq>
z9j3r{f%MPUAX+F*y$#SJY0^1x#nP#Apk0>UJpsKd(i`;hxGH^_j@Kp9HI+cQCQV5I
zS1Q%h@w!afC<54ZX{{6kESH+-yjLL|w^FpIQaYu9MwRqV986S8Pqsj&MrzPOrdE2F
z&V6;#qkN#%OT%c#)*yAIUvQ)JNC}*2lJ+fv!VPJ4BNT2*eM<n=EZw0;<1Oj8wA{8x
zqp4c7Ra%pUzT48Q5t!|eE-R$xuT#pU?MavP$w$!dmc|G$Up>+u`pw>v-lu|*yVBPk
zpwTORf$lu^Nk6NF7yZ&@<xsdMjiL?mfb^G}=({hy7y^TX((Jb(G9=|wd}dg>i*}d~
zq$lpeixKG-CWbUBZLm=I@S*fXJPeLWze@rcm$IGV_k{FWx|8%s%I|~5q_n0TFjLZV
zaS)l7GO0{%M*0KY!F?>Pq^qs7QsI;6J1RR&IY3+4-<~jGC$ro{qrFV@5jY3gG#d)X
zWLa-O!BKW!NdFMeNw!D;)>&qxgNTc)pI*|gvJLb}Bsba5biQ_%#jw!lA*-eJ(o<%<
z2@x;Zy0<}&%aG{8gC}#MjE0Y_{{$w%SGLm)n0~VK0uX=Mdb$RBLiU;iL;_?P^p-s-
zE2OQGHBj~+z3xuQ>{{S=kZgudfx)ucDaeG#{%eHap|W>>0BD%3-4~7FvUUx8ijb94
zkn6N8krw?(nUs##XJmmC$BvS{M~`^4Y+)?sDMn^XC1J6$PMneE#mT;*<8{1j=?tI~
ztg>&O#tbFOTI)d0%8LA8{+w)-B3VhY+)u$J%UY<QHAVKcElix3C2oR#s%*}2D5S}R
zf5Dk_+2cHjT#y|}189cqsUzsiltof$SC;H8s)V~J`)~qWwk-H<c$gy_=>?Z7vwok7
z&P%fGw$RU$RZ*%cU-tSlfGLperV5i{Sz926eOb2iZ-`uxt-cO&RaO>_!Ia4Axsbdj
zYpMolsf<ar8D+ACHR!u8bCkffa@h%ASgMeHL6rcNvH>mBt7LP#F*DUNtMxWa)X0YE
zcU3DZpnY7OY!!v!>t);LL8C!da|9+DWj+6cNRzDZ2`Ju><(8xGrfesLu$pDtDgJRw
z7RSZ}waD_7=xddY)4kx^vRzj6waLsKaHd`MW+$LKWKZ72I6GyUF*-AJ$;2B$x@By7
zqxQ&V_k!G!<<R!=u52^qih5-)(WgNBWSR8x?3YO?S9DLd^=C8=$Yfi=-Ipy~3hxJH
z{j`Z4l9et7H!OQJ2=0L_itaFs$aqveGAesB6dpd51=r8V^EW0tRDe;8%buVQcTLEI
zT_BHSMfT8`l!<AFJ0)X!L1S9x@FpzH$jUwh=wli4eQ>ifAF9_pD*wy^Y+L!kPH=Ye
z0($=J<)UvfPzQN5Ehoq1Khg2pQSQV7aguNTmul>t<)6`A2p4(!7qIIpFQjXEZt^GS
zeC;lObvw{J<Uf51G*9^^+5~&aEp#S4F8{qAoVVPQVg)|(GZZEBm48p4&hV2nsp`dF
z{wJ-5C*&&|Kmz2pelT=WzUUVIB7yR`SAc0fCAa+s8bR_v+U5t#^QRyaBEL=tict9(
zSCBCI%xzc-mxt4}tqA$KJeWT%7w-d!lt=rZFIwJu2q-aft`h38@(jus#K{X<U^ia=
zw+w?wkY^u*NTU2P<=M~5KYs!C&ROLrBcPEa|MDO-lI7ndz(k6CYzIWo%L}hyXsL2H
zs;W<uzf38VbooPC>MqD%_W?|X{2Ik5GUZGP0A|T;C}ek09{mscvgQ6%UY8?3M_I~T
z`4L(OF3JC-tzMq|xo5%U%dKY0!WGC@?gJ^5$4o-8Nd96F(2C_hmBNe5@_Ym4@`}8h
zF1}oqucSif68Q`roUX|~kOQq$E_8-oncM|`(RtV9Ki5E^TwYNDu0qbC-DIV_)By@r
za!nghs^!1a-@HaXZlyh2t$c=Z({*xjDn#q$zN7H1L4KA30gdt%7vX-BJT3?Wy&;#g
zVCkkjeINRo<*TXO?3R23Jt{5o)pDS;$}iKA<+fb%5Hs2a0)=*Y7RAgu<f}S>(kWM*
zf=HJ<;U6mucFPTPF6fbez6|<z<ezZh>0SA@?=a9_c|K(i`s69J<?ENby#lm*a(g<?
z49Kt0>VIFpa1)#vlndzkz>s{|Dwr6SzxW5p1Nl-l$cTI`Z81mXujpanq5P{Cz>Ue(
z7TSM~%M+-;Y(oCtuRwbwKYSZ7lk%U#;M$bjO4aexat`IhXXK&hVd=5_%XdL$<pq>i
zIjWF;3C>n=?O7<;DSo6X5PQW86U0Grb~(r~1t%SS&Wipn7;;f~abU<*(SnVmb)K6d
zWH&n96^AJf@1d|R0q3b`?ZODX6s`2@KCZ}D!i2Zt^?Zo<D0W1F^HrQILZ6@FspsK^
zzhZ$0Ku;)a4#D35#pL(sJE@pD3WY$$w@c7?N^$-YFoP5me}DulHd8T`HAJx?4rrl@
zU5oKc3RAp6G1YLz6rCs{6rFRyomPDKEi@t(KQ4udGYTDLs-qP9o`T(I#e5^MV-&Bp
zgTyMFD*+m(m?wZpydroGMxUUlp;K6*f*lH<&MGqLM|MteKL=crRk5}WY_dY-2(%PM
z&=~BVS9}`^#Z-kKW&6_<sg%=BSDd1t;swQKs?o?$^d&(*Qz3g22D22-l(N03_<$}9
zW-E@;J}yTwN}GUO#Y-n4a!K*UVPNJd>S&$MSA01GkphMF4E@)tLPdTW^otbn^jj}h
zd_e(-%Ze)^C|*&#R*Sx?it`jpEm1g7o%S`w(jZ`$DrPC7RHks=j0w7~IQAL($`u=w
zP^eJ6lMVGs#qc;RRVh~7#^hBiP9$KSY7}8BVWC!$_y0A9bqc$O(63kIc0r~=p?@2e
z8WrzWL9t1JfB%XHPZ3Q;Z#NYVTr@T-!YM6#OEE15*P=ML5nQWcKYgd-wjy~uNSh){
z1-*8~3EC2LD0;SInmZMXbI{nO2;Kp%Td_aNit+X+?!N_Z?kMu;m(-^a?u1OgV&xgg
z+*9m|g53c{H~nGmE57T5$e<#s2YN#aFEg-*6>}+v_&_n2&XyyJ-HuQnRjl!c!b3&(
z+u+6&y>vBTT#@%0CTKz-Ux=A`r0`ru-zl3^d^8Q2Da8OK9Htd90l=P7yhB5Ktk_Cv
zfLVo(u8tp7ent@hTjfI`rprz_Vg_fg{DJmG4$4>QD1A)%oE=8*sQiNVMNZ1SZs>DX
z7HtBii?TWw#8sItL!X=Sh!fQ~xhqR4!RVp%evD2}<;M>&3NPh0$}t~TmWBh(TUq@F
zG<=jtx55iwW#Z?s<flxcq_V&A&m^dyP;Pw@>H*4hN+O<AE_@0ofl8Yz@bHxKF<pfS
zQvOQ2{$S-Q+A4-9?QVgyhAPw7fDKcA`V3&gl{r-6AE7)D4E@te#*=7_RNAEh=8V#b
z&ZJRFC)(yjD?R^zbE#Z^16-`Klfnye%58L~Ctj&YhI)e1kzT=x%HOF1;jD5E1$fRW
z+m6F-lJXh4%8+bT*8YLc6y>iyz&@|sISBKqN>}>&OPca^f1sr+>!<|bg7O<$6f>0H
zd<g7J<p5RNWGRn74~2`$Hy1%YTiGv!LXI+S2$Pqq9Lt3Fmz0&Xzt2-{`~)cZ$}!p}
z6e#<rV75?cJ?;*tij>{-mEmG#b|26#D>M8tiC2^i%I#fM{y}lT66JUw^sgz)9l%{z
z9_R#Dt~^LjMTIi!6)03HpQKu_Dy7UDCaRUc${<ps<o*YRTIJ1?5UEo-(h;Iwx$Qbg
zgEHX%|EEZ!QcT<DCgnyc4Bk*4odwKIWlI7Yo0Y%OhZt|cVSu(MW4^%9T9xg;q4Bmd
z<Ry?c<+euXwJVox!B{$!lmEePr}AeyM|CNGtcG5<^7I~f(WCsFYCG;Id0zthu5$hk
zI{)=5Wwfd7Q?49=e!sG8C%Ajc>}U*aK>3{(2Jb7Mqnf)xW#s>$KctMK(8I8j`##J+
zQ0{vIC?m=@>8&-YTzeAO50$Iv=QXBWyaIaT%Fb=@VnUfk^=Xfkjucg&RL(Y2jnkBJ
zIek=iTG>iP$ur6T1F#<}oi}5?W|d2K0_~`3Q3E(z)i8wv?No>9z-X_sr%<kg>hC-Z
z?U>4gHa(82(*+<-s^<^GZD-ZqY(TrHR?xEGs(O?1ByK9Nf55q`cG^;nlZR@4FVH+y
zre{FBRBzQn|F~+s4=j1B&Qb}2kLm=SG<{XEG#Ecs{~1X7t15#5b3*k@3Cstm?oyTc
zNmb*|Ac3kS>F7J93Z&gtkZP;}>cJ}GX7q)qDwE+wsLF-vG_7H(LMn6#S55STjZi&)
z7A8)sGU=@usmc_?(iv6xevl~D8A?}1tDaI}W@A);tb#(U>PgC8#Hqffr8!>J6%6$R
z)i2%PQdK3Zp^&E9;emNdS2<DnaF)t}vJV$kb@WruwyKsNfJ~n12?}!Lt4gTgsz9~E
z9wy3E3u0imT=nWsh*YQ!Q~ID%^%ecPt5h54?^CTBZ3T9X>J<t>*Q#>(;ObO%bRel$
zouPnQqpIR-NH(c-p_s}Wsz6#4Z>kDiA=0d}&K&~iEmhPFh_<SJ42GrKs-QfKsZC{#
z!U)?{;VsbbP%$Ze(51?xb+=p9LA%Nx)iy7n-BJ0=pm0~U#|7%Wsz)?=eX7r0p>R)i
zgEr9vsvjsabzk*L1o{S5C+Ob&km@6AIs6`0MWv$ifvT4_(<7=M>6bLBs-TZzJXEcT
z12?8>cLv(H>XT(~bV7AQ3ZEXS475?6RCRp_Zd&z+4%joQb(BectYY4W<gCj404PV*
zKPiD?s~%sCK6|yX6mC1Hlm4dt=P`9R?G+u>Ikb0jQcv^&)J46Psu^9?v9#ZIQ}gH(
z8Sd(s3J?!9V>R?W)p>j2wwHSDMTmH-2PqriqrP_;mVDLqKLXlMozsR!fAz9EAScw*
zlnMz{pM4dEPN`o%Nb#2-wT$ws!Riw`(HWwiR|T|Cbt-KMBGmr*7}{y|FE$W~R7*CZ
zF<Kq42wudf8E>L5R-NbzlAzvF34@91C-%VnS#>uBp_0`@bkI#v57MdXygIQ0ed+3F
zJ_Na--Zwc1&tHZ*j|cXm+O8U7%2sFnf*HzD3!Q+Lr`A)bKVR*&2JRQA-<<=lP(2$9
zgGFjP+R+rN$LNC@SJj89)~`f8kOA(RT9AOgQgt~c1IpAIDigh~R=)&iD%CYih*YTs
zbd<JMt0yR=T%%s3fcaYW0jk`nQ`b`5woxsif`%sb%a1^AsN1q&;+A?T7icZ&=5CCs
zRn1BV*RGD|!eECwf`SE|>Wh?<?^5R%z(lut;s?w{k9q^GsrS`?o<rlH`txFl3|ZB#
z6nYp|U!x+<2Ws0_&^e->l7SmlZ>L@1L-l`j^chn-eFd0t^@lMKnNT;-yZ4dWuo5DZ
z>VDcKO{p9B0Gn2)Q_y-wy^e~{9;>fVP4le!tz&3Bs#!oE8L-tnF^on#jrBj;ZrE#f
z>;amC<|7Bl9Mf2uF&IZp&1y6{Y5X!UCTC4P?O0tjg74Ais(I!dM(?KikPg`Hnq7Bb
z-a{j!JO7@V?FT@-G+XF0s*mOuN^JUSMt+BgpXO6aar<imD4uXa(`ao)XMjdYxvG<z
zz2C!NpymyVgrCyb)2=W?6I=pMLp8o1fP`tDpg3{3X5kFxB0{s0lGCR((kyrpsc}08
zurr!>X)%t{M9?!5ttos7jWL?m%}|fkxW5eOI87iul<}HpW9Y+O2^u9;Nu1S$P<`q-
z&5j6=B+cSHXe4XG8iAdniOGP-dCj-uXiV1>P$kj@O*2)7W@z4y21=&pLl!J$X})cR
z!bQy~N|a=48sCG5IhupM?y0!YC&I)OXrfjCt5CC#p57vje<a9d%^#FiD$&H!x%`@D
zX(5nHHS$x?F4N@3K;gRPsXTDynvxVKRA@LgnBGcF!Pn@k(s-=`sn)d9s#~L3)ByEb
z%?uNyPIH9P*7X{V)f==yvu-=)=Z0o`4xG8EiHQeVvu5rdkXxGfMqr{v^V}VbuT67>
zc4O_D9kir&XgcPA>(u;3t6!H!@(|{`HR9JmdNk|k_Sqdx(Z86wyP7>zLfxxr&4pf{
zX2%0G_G{)mV}*%(nyqb^m;ucWdXe7OeDD?;hc%T7I5Vm_^#7Z7%^@lu9Mh~WLEpIM
zYBdxlG}a@Sphue3R8%{usreOsQ<?^P<xXqbsDfZdWBCr29&7g2qH$L95$(V1wBfrz
z?6sfzQ?ScH`!W@X9n<<{!-S(&PM?2q(x%;pd1vk5DS*0Y(?T#pSM59WnsU=B4FGl5
z?)Va%hxTv@)Q@XhX@&FFeh>#eAMFaN#_-k34uSY-<y5ceuPvo0$Vu(J#TaLx)`G>?
zI`5SBy&nJ*q<!is=m%?$x?oHp+D-q#M7Xw=Vhj;l{@?K8v{u>#kx1=bx*~Q)`yNd~
zl-8ZD%SCIG7~o>G$Cp4MRxADl3US&vs&tRnz7~k_CTQ2Z482tC;tdc<)4qBNK3UVX
ze^ccBg7#fsbY^IKU4WLUZH&b1Wodh_LGhxts|+I9+L!3HnxozKHAt?u{wt76+5@!O
z=V^EPfy>uc(?yB`?I!vq6l!-L16YxExg21{+UI;=;j;F%<7m91<?%7<t82CIQ=qd%
z+q)K)u4$j9<4~#gYkH5DY4@%N%ysQ&bS<h}``ZW<E3|<-Ftkc-=U#wTX`cu|U$r)(
z2&6{)qwmlKw)OQofHZ11Dge@?J-Y-h-O#>Harc|rQpyE1YtPat=9cy{10pTjzF#mE
zt=gCA#dlk~c^*XCv~mg^wQKqA@VY}AN_U$&wSQ7zrAupL3z2T^#06mXXrE4ny*t{}
zIq18qO}A1JN3V8gC0hHm3Efca*Zvs*a!<RB3gid0XDDcTUpuV=H>eGyQiCDwksyc+
zYfT$r_knh@1!P1!K#}87tv!{^KGdeopm9taN}oO%*Vcaxg$eEVbd&9owxj`)liK4&
zZ$f59+cXzLd#rV4VxY6y2s(S(>Arj)GWNQks2<Hh_thxKG2P(-h&bvV_`Z|*igncs
z7@4civH@Lgx^Omz<gQ!15fUD{!*q+@Q};Wap}cf*F@||umqxoxZ=LT?Q1H>sw!x~e
zu8!U^e!72u#`pqsw<%?QQg_h<J_PFi$A-cw-QVeu4AQ-y2n)fwm2?>*L>FXTfYwmm
zgYO{|rYrVGYq&0&;#U#6>+b;Vw61F}`XY6ozJR_ny3Z&d5vB7nqAyza0c}}hbhk7B
zjn~Ce;b?;HFIsXFbuRSsKC4^x5e9KiH%njjOVW+Kfk7nes$Ya;ite*@R+vAp`@t46
zsk;4iC`i*St%rWPE^-^V3%czZh-T=<pTi_%>inkQT9(f82J|lKqG%?wb*h&knWK|8
z0XtW>e<6Ijq?6JWy*%AYS`YJe>u4)gpc}geQm9)H2G@#oepM9wE7nDBhQZ4^e_E@r
z=%zk_!K=D#N?nxbe%t|=Yr4I`aKBWS_&?~E>CysV{<^M#LVD%8)p6h|bcsWdtkika
zuDVK><pHi*_g4t?YILzV0ISt4x(`R|bVIK}p<d@-NCk5ZI@<-X+o(Ip1!>X=DY|n*
z*Gebeo4P#*V6a)Yntq(ObW_g&twqP8Tt}<!1qv?R*4?B$N}Dc{HfHU*wG=1l&_(UU
zBy{SYSb^#4(#`HbU$<`k7W~of>Qd>s?$sF*V8Pm_YoJ$VzwVXS!QRtN?guxZTXGTl
z_jSp%8z0nt{23I7bRCou9@ed)Eztv=mnZxk(dneX9@R<d)$>rdoq}Owy7rUsa9lUn
z1>A(r{U&^Rqzk2u{-jR28+uc^r+UCmTXhxm8lKTbH$mpH?!pJap4GihS38dC{gcpW
zt8a9}DD3p*v1qi{|GfqV9rUAgiTIda-2!z-eP{+io%F$f!>+UbxmnDii+;Kr=3Vt?
z!-3+apQPv9UEfN<N)J6}IWRr-){bS+_tIx=hd0OdukHtox4!5t48}*ll5WoV>UCLY
z^wYogD>#4szm&o|p<lKTdI5Uhbue*KKTNI#>LrxvIi)|k9Oi@c1<_~>)*rY4=n(xN
z6%mE%KfekRreFFK%!livtp#v6LVs>I$Z35ZrKBVEBNS4I)}NzYTa3Pno{Cug?ep*=
zPXEz*aPj)T#Slr*YbghosIUJJl4tcPUw}KO_gDs$B>i9%B$M?qlp{&e`+oq1^ZJA3
zXiU{Fr`T?q-s>s_|I+pA-@%k#&|m!qof-Np2}Yl(|8*z&vh+(R1#nS+fMzyZ|F;5O
z<mmrRfx%q;UzO0iq<6G~-8}uVLJT`!ztIMyKwlLI$wK`wCB%#LFP;Z<vEDKP$;<i=
ziqLpPZ$CuAzpMH#ss||1kJCDNO>Y#Uvs7P3xsEb@{(M-vuCJkUd%6BSHTo*_r93E9
z>Y01MRq4Ms!?kL?Z3Va*J$pUu*6R5)P^i<FNzquZ7rqG6pg&AuhDQDNR46p**PwdO
zI`4+Q=nrVz)USU4(yaf4eml4Hk-jj|qEGw)bJ42*=L*Pey<IBiqD}t{y$ss*_cvoO
zUHVDdVs-1gePE(T|LHy0y`z8Q9=N-D<x)uY>f<S=+Na<26D0ffJ*^=3^gRzTCDsA`
z)D}2(Ums70+d;jR>Me#a7myj&ODG5ZKtE0C^%4DR^c;=q-=@>cLw(;dfR5=m&>Lc0
z?_&!xp*K)6=aD}1TaZb8)ki>?(s$F6I<0?I50M#tCf#9ttd}G7Id9ggx1;^jQA4W?
zCTtD;12AuAxIQ04vo~Da0!0VI`sE<U453FL>1fEINSBjA_a$JQ4Q_PmaWPn<(dTMt
zISD;C!(b8`-3=?ryocfQW~h4_R6C*IWtd-r;T|`rY+>HpU_Foqr+f^yw50nQI!Ynq
zXL$M*p!pjLm%!2q!{<AJ7GQX9F&a-AbnYO5hM5nbcgpYu)k+5$ys1DV*zh;KnL-Q$
zw;&Q~c)$Q=nBlq*ji(KJZUZIKz$1Up7}nAcF~(rA(jF<+Ac%lyoMEpT4ksGEdjk`E
z)=;njisuX;(GAiJ!%14IG7Z<aK_tt-p^)iCgHt^$WgB)b1X_-PO?CabhI~4NTrvn~
zrOY#Q-vG%s{7My+1%@XVz)+##o3DXVWVm<L3QNU?cPUMG*)T*~vnz%MI?G%&3?0B+
zlo--3K;)WXW&uP>4L3D_DKj(*A#&Ytn2N&74R8Gq1}h9J%n+$GOwWN{mEp4&p;v9#
zKmq+4!`dNuUuzItgEMu8OHSbG4Ok<Tcq|M<sbCuo+v!6LO@`x%(70iEQ;RX(H0-ej
zXtM$Toc3Nm%lg@eFxX~zY7<1-4GwfH>@b{kf=H(!*9{6?hOg-pE!~ELL2$Ik&`5VS
z?-*iZ(0AAHb|l>HHEeVTN}pl*037W%c%K1x&mg9#`GCQbvR(HL+vyvlgNDbwFf?Sy
zsRcJ|7_m-(ePCGgD?~>OduR_jY8X5X?1zTm=`T8FxV`{r<A!I>!qS9cJ_p<*!*dbn
zn>6fogfmkHpWPsj4W}t;Fl(rF2KG^7<^V)&jW^mcm3GE`!7yZR<WcRtgVC4DT8<gh
zS6QLqXpH;~piaj3=%wpy{P{dAxfrj}!slvybOC5?M&>=Bxf{pmPN9c!J|(C;jo;H@
z#>@EHF#3)gvsVGs+c-dhbsuBsad5uICqICspK*sXB>j!6=`ei4*!=^%2rvd5r1Jh#
z#yDCef{YpT0fu1XTT~nnV$6*JOsFxa2p)zRiw{F2+;~_9kqBe%1Av}3MiNY<v7UZ<
zXN=nu;b@exhLZHr#=nCxmKbBxXCSf0HL*~LGfFxD7H=H+4$uk45<C>vd5OlURe(8b
zjHYV7bH?s8bS4?IWN<&(s9`}P#VF4Pciwo^8C<IInagk{&A8+h3_IP}T?6id@s~Z&
z%P<~%86?w)dM-Rv#?}oW7mbE3Alb%kqaZoPVLF!P8vl9%e-Y~?W63Ps&oic1p*7#Q
zhK|Jr#$q<G3yofs*(x$R{0-1zW7cMj;<B-#2ryTSkKcyftH!~3@V>-&j(oai{F=gi
zrN$M*;L42qRsrm~@h;VUmm6Ct`%__jpS}%IX?)opdR12AZ60Q*+PL@)jIhSIVgbCU
zHHPkhew{Jb1cUWP<`)=tgK?D%XpP3aFVNUztfjxt4dY6BXWulcDSz2)3?6{qE#o#?
zTw09(mcSBrCkaq!H{NuFNQd!AGVFC4=QU$wT}JB<C!ybMoL39qdW@IohSeS86Dt98
z*Vw0ney_2E3OxFZonJw}-&hg{g?mQfJctY!uhC!YzVTVg2@M)sG41n)jBU@MZ`c@>
zgT4pG<&)?eF;3rt!BJyTGQb`h|C|GRV@3z-4`>}XzEAJRN#jB@^rws;Qs!dXSlI)Z
z8Dpk9L?0U$jlle@(USrdM@@gy#WGvd?`I%sXOgXkp1o;3ZBrafk@GNJ$4s%5401G0
z+GF%irX}?Aa5j}>!Muy9o#H>Prm3w~$het4{1Y<nrd4#Y%)|8ER-k#Bj?vl7%fuj<
z<E94shK{#sD_y_vF*UA+zrLn_Xrt_B`riU@{wALg^qnvb-GD-XDU)7hCrzJGRwK~#
zEG0EhnPR9~GRV~Y7Pw%OeI)HxLQJ`|9)y|>(%v@A6hO;pxalQ(a1o}f>A*g1+SGu?
zNYm<Fn2R%}ZIq0SGNrx^v}ltPWt3w~QhMTIO@34;5og*~3G?x$y>u}$!Sw4cOmm`X
z;V0nEnszY(ea@87MdkfTrhjQKo^0Be0+|%k@g(S<H|5jEt5Qu1$AFz?dh1Dek#0H^
z4|2iePg#u&Q}hhXXPVxo=y#TBFJ(0@n)ZASy=;^DML3#c+EWIDxuzyR^j$LD_CjNU
z$v{W;Ler{E;H*WaV=qI$*i^a*GM7z>ZSdlX$*~V}dDV1>PW~mP{~7>#%~VH$vr<zs
z<*v(2rBp<5-SiC=6P25a=(JE_I`AI2N|Qgm1*%N<R>DNJ>Bmnoh#FHo?HX!L4zx1Y
znKU0mvfgTXpSErdCT0&vqiNKL5jL4(C{A+2^wkn5-ZcHT3>wWQf64;gGO1{(YcYM1
zi@sLV0v+t$HYsRJ-ewA-xKO*PW*!teOf!}6u+#J@?FhO|0~evtZF2Pj=`r2zfZiR`
zvsH9XzH5s0DS5^E=3KaR&-5~t-wc?HT_E>On<+j$XtFtsz9G}ER3J2LdRYyv2PXHm
zn57Yuf$l+%n!-3herT%Ch2EHHW<JQcDV*M;6Q+l>>3w8+mCEWTO>fKrnKI3zknFUn
zfYNv~rdsP5S|6Jd)&XYLl=BQUj+(>i?`dlur?-@y`N$<`*qgUEf^#sB(vx}2{MOS@
za5l%;pwY!F-vAL;vz+eTxtX7G!4$Zg|Dv$Ehk5&N;5^Oizs3xDng1<^hsVufR5<2s
z_IaCX>U_)}zKK>}^KvRv@-rW#nhk$*=9eHR%+G1j7+`i90y$}3O2O4Yb1dz$Pnjd>
z)fHrZ{%bS_n|niGFvPrc5wJteOAPQS%>2|!poE)0qC97WdF@v)blSX>>Ix&xPbE^?
z<c#_DpJ1cRLPsb@n|UQrj4>ag=w__B#v6XenM<fI-uzSn`V!1vP@!C+*-Ez-&zg(V
zFqh}d>uC#+WZv8dy=3zPTBuUYLOb-GH~Uc1HPy_Vi@r2-IBlWR%}-R(T6n?y7DeYX
z%u}uKG}GKb_nEWI`{=_77tL*t(U)y*q-8$G{6ZPr&oy@hqVJOV^?rDfXLh2~LB4tJ
zyD(p1{@)uADKsa&28AN?N;)JIn>{2@xNJ`N1Y@~k)<1;8RrAm5Fcxcxd1nqZu9+3|
z8!a`rQuRQYxitkc*UkDjz*U<6`TweBvrPs>s?Fz-?wMC(-uEg*YRw-|s;<uLM&Ea-
zH$P2*+XnN>&oGEaa~OTMvdP>Z1HBvOQzUuQ{M;RI&E`KJ!I@iD^B*sOZ86Ww23o6m
zDW$b<oB#U-Fl}bRHT1Qc_t9h9VRm~OW9l?7qp)U|`KwM~cbkJ=g{2;|tsB(um`he*
zOn1$8m*7mVxrCCCedd2oz~6rJyL7Gjo_QzLE)AI1Q$qK?**YPI8-wOkRKz}HUib#|
zht026qw|5ekivH(=5~7ZjhffE0`#Fd@GM*#Ge^*?Z`}N@9wHOw%f8TiWUis>k(1^R
zx?pL_Joz%rPn$oX@2bt1$7m<;*jz(r$XWAp6Wl&(`Pn)O7+Z_aZm@Qi2>N~4TOM~n
z(ZOQa3xmfjQ)(zWS}uGBFPtn!S_GXfK||<svD8xf-_>G66)SF*&p&{=yJZf&%{?qW
zwE6Y4-1CM(FU!X}fO*^!We?(Q@ydlgA4}U}niF43(HzJGS$0u0BG@8%5BedN$YEFt
zwWLtADa<nYCmO>owse^y!gBvVjQ6x<T{~ty(o#ytr!$uI&FG7=lu?8_*7DwSP>-|t
zEQ3hA#f}PB5-g#2A(?0y+z)cr67-lNXXh*h+u&)EC4h1r$(DVzlSr{7t^zr4*|8F!
zsg@jSOtWmJoj|&!fEKe0mO}b<XIQqKg^5f{1_f`jESp`yU9^PJ%P$)<1IZkVd@l6z
zESw=U=38VMjJm+`#2XYjE41YMfi1F>QCPUxqIrbzUbbwO1Llh50L7KATArnZONnKa
zLh;uup)X_hN-g0JpjT!Yq5BKhEtj{UuiO$@0)-08nk4+uDlLP_=&Q1{QkbaP@)lM5
z)mV}ap|93*`8^P8gJnN$kQ*%%TOreA$y^DI8<uw{{BhH=h-w&`E&aCuddsq7IY^6T
zBi(^&wIor-<F@4=8%$oC#raL>wOdS7sM=wP`vqW~mfUxM(q%bE|Kq0H^30n6>#@Aq
zjd9+wNWx(D?sJw{+Q#)-rhSiBykb>+hsFWRNi9U~TZ9YY;h-hi9hgIw8&5-h*z(_b
zh&-^2ABD(><)2-!K59`=nZiTM9y-X5S?XSg^>ND?G0aX{4(3B|%JOay$h3t;^;<KR
z-6`N6Th>x~bk<V!JvdvN1y;)N+u3M|*xQIlVb{TC2mO_g*}PAwC`X%_8{nL5?y4|&
zXPea&5p}Wgq~Z=&n=k2%?q-wr2qNw_e=y;Nht2SIIO=J0j+Rs}8_q>29JiVKJ1ltH
zI8k)S$7Ts_gneyNzOq8m&nAx+34fc1SI~OGrgbj30GkL0m^f*3m_iGIHvglr;VB#K
z5;O+c)RzG?*v9uUKtpU|+hHlxCXv297-nOjD0;ZfZaSMs*!0q)dD`Y1I+8{HA4k_6
zpYzqlt+ZNI9kg^<MXQRU&)$3QR;Rw`)auZoL-mP}g+yeCB(f)wDSPjbAu^Fc78xQ5
ziC7Wu_cZ^U&$;(}&pG!#zj5z5=l;U*+zl>@v51zb(Tp-7?aX2rs(DZv%XsGqrZkS>
zmJLhsjQlNd<}{;%%D@sBTZiCiBBP%ILP?C}hk#FJ6uk~hDGblmfTuE~6o@^;__6_#
zX^eMhpO((Zq-R$KV{1R0$z<p#*_y@JOczNuW80r}h^d(I`y|*BMixDaN*STF#42Mf
zcopW$89(oX!3suyAn<1yein@P9Agfp$Ep~wnL(-<$wwhl!w`NAk@Jl1DwwZhBs-z+
z0^>1d!0H(jY$$7B6lcRw6T`;~ea(z=dRW?97~cnjy~tScUlf5Mrt9%C<9ZtqtqfKk
zWZD>qW8hjl<60xkcQF3qV-!~ySJuMrRmS#sjIfjO_U91kVk~<ZBHauXy;*x0%C`XT
zWf<wpDAyPlf5uc^XB?wcT^~b2Yq@?qBlvyL0me`7LFpi)o}L9a7{=!T9Ab>pZGV%|
zbsioLGwLY+H^O)$5!@&vehTCkV|E(=w;2f%m>*-*QoZLm!%A-7VPw$yV1i+%WzAhi
zFCIP)4;XJ!9mhk)T-t0-GUo9IVEz%~qZ??QV#s{nX;^I!Uj#{4rkzSP+?ZG1fNFPU
z98LN`W;?|R4>2RpK*WP7(u4D4R^>wS2-BCsZeGkUZlm!i^MVB`y_v&9!1*wFw3_l|
zKD`jcj~Pd?;bY9r3xV@z?#hSAaptRQ00>}yWzRxuATx+o&_PTWilClgM)zSz!ORy0
zAR$aW-Eg7ICVHxeG3WdUk#OeNefSi?OsfJH$=peSktpU6t?;6mObRN;FmE-1#4;~v
zAri+txd{eOGS^h&w?4(RP{DpYQ?-Crh^Luf#^85NV2)~mNMyQw4HuJ`1J8m>W-g(E
zf-}tdp^!{t4$|f}o%sxfFf*73-htbh%yX2o%VOqGkTr)Xr`1I+^ALSVFppU<50d%J
z5h^ArV75@$t%y0^30yI=Ih=NDCCn5$u~y1-EyM`Rn7`#irh>Vg!jzTFxHLF(mRY+S
zBIlTzR{*SHUc3&;YGxtjz-pKu(8IEpsiA7(^UP1FLb;CFH3{!8Ff*xgp`Ka#-+qNT
zBMi7k<~PqnbrZ7$?=rhXGgCc+))waSPz>!NQ@jL-OUww0lwD?WC`jAN%%CfwjafK`
zzILW}2y}NaXVG<Zg*k`PU00dY>Eh~Snke<q#eAPOx7|#~aCqOtd@%>`Ugk4xaP%58
z_AkuSb*3o>X6=2<5-DW*nM>%L;Q;d@eFA2P`90N@-(=n|gzjNxj|1={%w&o$jxrnH
zhR7}EP1>A{F{2j)H_m*x290-^e=h_#!JM}oUfgAVnG8$!nX_L;-vj3F^FSUl8P7n=
zBvY0Pkw<psJ1o%0%r)x(bY$&zg57;A{RVJOtXZdl-_L6P6<!=*eL|}YXV&Hb5EoYR
z0%&t(t)no%8>_AfbK%YkngDl@<<SoA5bM-#%;;g(<0v@l!P3uxAy3xvNsQ$P>)fko
z^kUhU(YoL$YhVLRc(dkG6^ak*X{z<`W$mIczaOidiYbq=1TpZ*pY_6YG#+QQQ*tJN
zwMhbh16hm*up7jR{2AN{*5EII2eS^+&Mt)Y!OQR>lvVLRm=9xxFN2nFR%<^DMX)y7
zZ=p4s)$jmb#IO!iwl0=cPhsdd)<G`tCt2m^VCfX=86z6wS(Q2f5?JnAAeqP-p<`J|
ztUpR%H<=Yq@2wQpO-g{IvJO)O^bD(EHTu$7FAD(3V3ktrF_X2p0KY*N>&J15R%Wwg
zXJ9FZ#ilyMT-NJ!Q|Gac{fjZ>vmPG@SHMc3a+yNbvJL=>S>ER{2_>w-FmR=;21<;T
zvARlNx17bf0uvRiEV?`@Sq~|geU6ncgz73*Vi-iKS-;Y0!x~oOB6=s*vfd1ZiSw+4
z+W^+Fz9ARuSx?f>)xes^gPKOxH|Kz8VtqP@zGl{}tLSTC70|)Yi>&6~K`yi2@d9aO
zRna#-+E_d3>D<oZHN$QP>yNW&>|}+qF^Dc!Cmp}(X6<=?+BBc4i%;82sLbLTYlNQN
z*IE6vx$0-d#zA&~^%9jd46;0F19OA*CvAX+SWR7U<0h+v(wf7pQ}l)(WjV}6<1N-l
z{c!j;t6>QMW2_M>pc-c}{sni3^@1l<Pq4Z@q2(^?F6I92v0kxn1ACvf&KEz_1J+-E
z05QorxejU`v7QQnt5d8^y%^hL*7(mb;m96zK;u64BMRR+u}dV7Jizv{LYp)Dz;?i0
z*eQPj;L5I|ZM_@&9G#bSXU8M}caUA$4||8%jW}27;KA;iq+Nn1`|}ZKJHmE~L8})#
zly<F0*`HH+t~Yyxu5w@YuUpaQ$KJUIfMaa#CN%o9SH1;uoZY+;N`u&gR62NqZAyk@
zF#FRSa3Smuhrorh->Qc9VeC~eV7kKDV%h>nvIF+eze<c^2Yv;aXm%AvHe=X*uK^g#
zelHk}aqMIo{YiGf8rY3zH`13SPP6MP(U`!FOh#iO+lPW`N$f@RHce)4ibG!tdpGUr
zQrQc3f}CN0KMf*j?2HdEvUGMPA6hcmzf7NoXK)sKKb<$sW^Z~DqsU>m(4HZe{gD<w
zR~~zajzs0NU!%*jkbQ6(M2grwl;tR9zfCct5_Vw-CZUx5#~N^D?6mzbQO;gKx$H{z
ztr|3*W%p9>=N#KkTb3&Jb9>QO&CaKDclH`~i3l>a><tG&>ew<`fn8vqptWs1d!z=W
zfgMzd#zwZoF3d~|`+*uGyvQC~4%aTRlP4i^nZ3Ci@K$!MD;nF_d9>eaXMgVja)td_
z0mxOhfhMSvJ%<j_cCihcVZPhWj;4RA)5HEl3Vbj7D%C+;XK$wJf<AU2EtLD&U)`bG
zf&J`EAO_igbi?2cb^;|=huEzYQoPCjdoiYKm>oyi>k;;83LuQKPYlAD+w7zC_!wh<
zOaB3BoNYb;FYd5^u|f3&+rD->5O>*gsZ8n~J9Z%u57?GP80bUx^(P@Z$&T0w(MRmQ
zPa!$QuHJyY$Lx_!_(dE!k^4ZLIPSDd+0S86pzi?Zt6mUiP7eL9E}Ry62D@@TxC5LU
zXC)Vs2RZ*x4*L+t&;ABX9OguS3mFg2{V2$Ia^h)YaFnx>&Ww3;W<3KDA5OxrK=^Vl
zJ%c_!&WrT<hhrR%k09dDdE5jK133E%!3A<w(qlS^Q(22)pWwXm92$c;uTg#>gfmXd
zvrx_?C62;5A1<?_HG;GMPq2|3(R}z8#Yy}XUPN==p|a~3&h`KdCYE!LmS=IC?WrIq
zIfv<~b&4}esh)VwQL33w;H+Jb2}<PrGXPu?$B)h{By-l%p`H|u=6m#|auO(0b%qmP
z0SoDzq<XslGB|Dpa5$6mPb0Ktal*I2?`+OGI$E2@@m&O9KF8%B7%brI3J0)|(@&&`
z^Ty}UR?NvH4@)@u!)PqycvHnuIp-%=a21^Y<-&X=r{FZ)KFiT=$2^_mm<~a86=&LX
zI^0&n`H0?UwVb_Fi+Y|jkG8aR9B(;vU*HryjmCOTI4$WLI6oNSMI(n#`Sm8w2NacV
z=FFg-W(y~O3f^Dhyg&zqE_0?f!h9=d=lf`E<2+5p`R$wtsv7CwY(5HSu5b>1k3M@R
zCn5%-T^xtIAl;lWTD$ddHoXqry`0H&km=(nKf{>%IfsMMIKWw13;ZBwTQekYaNeMB
z#1JRV1d*GZN{VKWa2C{o8|9R)1G&YS?1Adr94l2?jB)n73@ziFUnuc&$If{n3+!Fa
zuk^~f$I&-H+kMX21aJ>H<CJ@U$T>nWs7a0o9mjdZSxSM6DNY3C;vREer0I6#&YcV0
z`?x>IF<tw)?Nn!SfIBe*#F@KM3AhV)?QQ^ExmS-sryKXBRP?!X?VnP7>JT@Q3z@^*
zfm6`t!A+qhm?yWT9^?pj_b(9f=H@1W^Wn~?qEKIMHr2lPalKxKPsg}dKEh!9xkYm^
zmgC%rF<1)ZKDijf4&wef0^AAimX`ns=02j3Y6y4hMf@V6+&udf*f6d;Ei@vy|Ly@I
zk~>6^^C<3D6jYDq22f}whWo}_z{hfHieM>@n@OwiliV3?kUYgzL_jj0J24-9r@4n2
z7)v7eqZ|N|pbT6xx7`NG6z&6B`lWJhRMCBgn~_QR^)&9w2cRv38}lvZB$K;<GF4gJ
zY^uh{=C=AkG>7}V7{Gk)XB6@%;HK6>q>$^d0OKv<I#cYcm}_hRDdBql1f8Yaf8WKB
z%D4fvmo4Z1m4wDh?(Mk{Im^}S;L|zoP#}E}v5NcgCdgEC9mLRG%e_T`xbs}E_c5kA
z?oAY-IMj0+=(XR#9o1nj8o3K83fjaCr6+1L_e};!3->Ce@Go*V(LVVy_bpmyv~o2U
zp}LLhHUofmt|uMM>)?L=0Dvo8la``nSGj-ChOCRLd<wd|x%KXl>EYV5psknt;cNh}
zaX;&VPuIEqo8aL9_uqE7Kgjh{gWTZidw?6_?tB-LH@V-^jWf*sgKD`)xCie**(leI
z7KyjGFMa|t#&wZH**N!Qy0`3ixQF8*Gr=v`h}OH@e=DKpKKBPYgY|$rU`69YZsIr^
zA8}`-13$$T(}nn$>$x3$j=bOgzz?&Jr%iztC*Hr~;P&&JDed6QJ5>uw7v4^9aIU=5
z&jR4a%RB?O-FX{opzNTXmvR)A4)MNjhTk5%TrEUBc}el;Ji?2ix4##!lpfkgc{P-S
z@#Y<P9cuh|KO6vej5q5W4Ah_3yBpkb-mA1m4B$;s;69KyD;-=APehT26TH_;;7l+t
zHwf@hp4<ywgz+}EtN<I%^QDzZ1n(buFh}xO)tLNf-hW^IiQ(1nfETg6g_P_($s6<8
z)%~jdYszdT@@fSTOyY^8K&SAA|G`jFd0)_-a)#GVrz6vNM!F}{d4Vs$mki$S@6nja
zE6>0ckj+y(2Y3$ehit%edFSbvZ5}U;-tYOm@A+sf;Jq0HWyQP$0%$4W&A9}4Deuw(
zD$^|EUDywNIj^V`q=IMmS=uw--cJ{E74MawK&p9Fw*jc(P0%^yTHcHyG@j=f=*UMM
z?}<=w7kEMn_t*2h{yU|_du)RBM&61~0BGXXodRj*wNydNCEmZZ7re}yUIcTky!c&^
zY~zWj`n8?+brd}6;Ke>mJCG|pln7wS!;|_H!=+`EKkVW8OJS&&H|P&#*LdX=UA@k`
zQ;G|wk9U?5_WiuSc45#1ysAQ=2YH{;Y2+I`#b&^Vc-eGikMQIhV0M)EaTvH;yc$Yw
z-{yUD6(bts^-v6cocGteuyBXB=w0ZX;2pC64W)N^(X@EH$19;s@O_?%^1=^zm(RkB
zhrEm#@M4nZmk08Qr?mhu#cTTq++$t>)~ODT{27$K-^b@uIhPZk^8nm_{^76D=fZy{
z8g^azKdgqoZv3z4oPj(4J71_i$S+jU0j5Lzk7?<BnEwkI^x)TA1o7nm{uWFe;UA|g
zgBO4POsMhZZzN}Y_;nQW_2o0~0q4gr+YU>|`1c!N*Pp-07vwm97R3Ss_}|dFC6Isg
zAmBm#MPcYW!FPQHB!qt`fZ{Bn{4%P34dXvWk*IKf8f~c}`0J<uC6a%Fz7i3|FN(s<
zMDxR_h#-ca{VMRW{K9VZ#qot-gPh{O{XcjS&#$BpdY$I~*aFuQ_`x4QGLauS8zhMz
zp9?RN`Mc>yOW|9Q`?5Qv^3UEx>lwabDe!6h5W1c+`D<vMn8p8b8OEE<w|xm`a`=y@
zK{A)Woi2zx{)#8jn9u*<XN<6bzvL~DLjIh2Fki&~kzNVK{C8$xET#Nyf5YuE{*y*D
zmh)AVNvq($eH4B6O1@?oh_n1BSAd-3Km8{LTE%B>1frUMgfjg#{1?;FSIeJu2>3ew
z-;dz_1^&ig&{)r3u^c}|1OMH6;2Qa_h~Zijf8TE~(aayt0-%N8w+~~v$Zw;B`z5~q
zONd<N>u77zX6LV|2W{tnIRMcP{&Bhjukh2W!CmF2P;GT5-$4Li7e7=7$!<RHH`wjr
zucAm_FMojEcGvhXQs}gwKldEQG{D!>Dab*7$zzZk{MWZ(5JUXGUj@0z-$=RVVLtyi
z;70fxS0(~6%KwO>Ot<*^D8PT4Kh+A+aen<0$lT$Z8sYE+e?$Qjclm4|$G-XY=RDxq
zLw+lTGAH>9snqxpe+vbSr}*=>fj9~l&__%530Cifq?2INawyp^*g-Ly1A?4RaL$6m
zp&%}Tcd16iRnYDafSbUXCdOT0q9erz1rIVIa#+wnJ6#WftQv+q1zdYRT8{{LDL{A$
z`o01=D#)c<+gp%9nRg$-^xr^y1@Rgn`~>~(&~{8PLZ@*91b+VD0tL68#rT2*y*ijb
zA=pC!{a}G3rGi2PsV~9pP=UiC0Kx>>sjv_(7^br<5rPc@DrSik#7#joTA-y3PK+Sp
zeTc>i@+gZLC%8y4^pgT3B@#{vdMV-+FL-4F&YTwPm<5s`$o~?!M8ScVfJ+jz(@Q5s
z@DXiSQU&F+VCjtDRxt*VCRiN;E?qE8g&P@y__K7|W(rjF<=HI3RRxBfE!dF+r8$D#
zRFRr1*g+e~e8Gp59w-pBrNdI8AZ8GxNDxKq*kZxEE+8d>kEtlKRPaYTOq2;;_XQ~z
ztl14*h2ZrT_*5x)K<9R=1o!FdZ`A_d0ZLia2rfJU(OSWF+6tW)Xjw2=CwT97ICDX;
z>K`br7pzNxng)T<3HV0AdU}6130B^MWQ(BE6%%w(u$zazO9Dj(bYB*X(R-s+@ai7u
zY!iHQ0+Q{5qRp7m4#7;?e_j!!?*qVoRj`Mi;GKe{8Ib7~WL^R35fonquvg%H9(~sY
z3_6y2U9f=*OMQalx6#-y_>E${1A@jcAUP-qr{aklg8j1~G9>uQ5hBBaU7H{>B3Q<S
zrBT8C5Dem$AfW-S-4=AYfQ;D%Pi+HYT(GkUPTdjM1|T{isNM?vUBRawK-?49xiJ4w
z;7i+%NkK3DB98=I3XM+*JSkxISny*Mh@<e=Z((qsuz@^u686M{>=!<A0{no`LZvv)
z!s}ZwqprfgDCqAdT+v6XOm|`AQh0Mv*x&-uL&E86;ml#-G0L}k2+#X$xG~@UX+4x3
z6?#y}#78)@3Wj`zt3QHHKjDL12p$u<T|lG1Fz;(Pcw9JZ4!8he0vQMt?o9$NNZ5P>
zvvmR@Fc2(kkHFYNh2K!AVVJN@2`*gNL*<VV!aQ0BMhgFFgM}#JaeFdML<?gn(Gw#K
zp@&?oFs&Seh!eg&4udC!r$V9hv~a~5*i8_cXiJ_b{Miu$OA@Xcg%`=f1ymcHB3zdW
zWvRm0R^ZME*%a<d6IPu9moA)r30#KoO?r1`2|Fp*kS(k~PkZ<r;hR`ZJLC!@6u{>R
zJ?V9sFWgfPy9L6t^u3uvp~?%SNZ5jxibJu`MzOmRVKnVe%7m2^*Dn{o9sv(4gj0Wm
zR0=yNxp!7rLhto+!tOG_tArI{fL9AQeh*S3T>Ha+aa3XCYZ%jc;h*PW{(_MI6dbM>
zx>LTtLFh#pghpWoB@3E_0Xb0GEZnRCX%UuMq2{9S?Ss&LN$5ZUkjuhtJ#eN~sL%k=
zA#8nwL0l0oSOIcX82TMlcMGRzOWh-6t)>I|y}}o1E{BA(kHg?i;mfoW8WtX=qevsd
z0~GHb6_#xVxg`vtN5XAkWim{R3HMO#+qlrdh!NfqYF#jh31QE_;O+{4dj%r*gjyQe
zePJ~1!5;{Z{Q>wxVYwF?CxyRK-J<=G@Gr^{P6@Yv3G!ID<_)wuirRhwVxMT`uMl+-
zHPY7r_lu^}%pMTE@G8dZEb^t?nTse&g2A|o0{?_TH_;U*XmJ<)AOJZi@~2GLA<@?>
zFzmykFR5nSLzGJ6^c3+Z)px`$nodtNFVUbQ5JyF8<I(CZnnneLKB8lvpwCyd<9p!!
zL<x)0cTAM}DJI`vbRiXLj*Ai~-5MY|hhNPhP_&bN<{;6h6plP0T1-j0VA0xNz=eqT
zR5%za`iEZKVWI`J2M-t7U!)&BLbQQSNJffs-ht96k(2{Ov}hs{_!!ZK?;#p1nlS~D
zIMKI@F(oHOWmJH5O0?XDF~y5c?}x}~QDh*-n;?3r8#9wAvOB`<BvCHCD3e7dx&%^0
z2~--BDyot|@{H&sJ3Z#oL~Fz0RJ!OIr3W%Z3+vIDDbi-6F-!Cr<^8io8d|yMh*tgp
zK(5H}8yX8lkpehcC|XDR&LUCibXY1DC8PjeA`)gmq*RnmMMq^KJ=I*4i%wUfuR>I}
z5t5Z6{Y}d4pB3%A3rpujCVJRbi4IXwK(%NZt+H!G3<`JGie_Ac-SeUs=yM8nqH0>M
zUJ!}qz<j-ERVd&Mq8zI6Z4})+3EfSi9h63C7HR1$U5jY#lYn0oy)}f!OQQA^G+q`J
z=qQHPD$4AEnl{lEO82&l4$|q84w2_4P<lo5In_H~6-CgopH7iu7u0l#ruV@_w@6IK
zlzT+`D0tQ@dMO8hYob=VJg$olXwcUuN~MpC^os(%gO&l&?B!@26!lhOoHs<z4>{oe
z8xkF)Qj?paSo*rqu;>Ckl14;YF1S(ADE$|OTcZ24lD;iEItgw}#HSqcxG1LvB6ma!
zufpzx=(~U5;ayP~oh`p7>VFRg?~A&q%=Ce1J*}A^ioTeOVNZ%0Ga>Rww3Hr<_9@ZF
zOt|=1bYT&cI*MOA3B*3}Du2j0i3=#HxnKM_?THVFPp^bhXK?~;^IgQvRD0wqKI{tD
z+{EJx!MTecB!W9AzDg_jLt-a0$YF8)B+Pq=yS(A3m$<7R7LJPRW<k>1E><REyguS3
zRPEs_UP>uPKXHK;oyWwR`~dV9J1zxxT>SBWRUYE(PH=(ZRrHy;AhAC!>Q0D_RDc^S
zj-dNKL@cCSQmA-NDBKPc@6bbMxVT{jMjs)*(TBcBaRP<Vqr`Su8f2oyJJv%cMjZ7O
zNUZqIJX`{C;xFgJ)01NEPY^vN-njto$BW;#pzpMJ{ya=Vf_UsGL=wf9%fKaxlRpGJ
zS-fEik||>2vrwHXex6o=XT(4K4lYgHP8<AmaU|9CWr$y}=RkL+cowC0vc#?wam^O*
z3x`aO_}}Nymn+`64JPu$YbdUsFJ5JVNP)PQBI1SO5_;;Dh@X!Gpj6y&4|7o_&QxP&
z%EelGLR5&gKR|V*m`Bg-v*K2&962XmMQ_+D@$Ms(L#h@ZyaHg2c$qUutymrb(eq+c
zJEpWwymd1gFNoim3vKn{8?OT2Bz{5*(k$k_4mB;}*Tiu2qIf!0=v)%dE`sD`@!|KN
zx>bCUHYIK1raEY87td9ruS4ubML<`?3t7{i!ObO}hChc+@%KJOWAp7cI*8aS-arwe
zYhpfK)z`&^_d)u^3#dM}U%dS-SRW8?ppwNw@%VEvbVKZM6=X=f&j$ES@w%ts*|50%
zV;C9{dsAL$RJ>CLowvmQ%SPXAv7Ro3G4cBp=ouG3ODXR=Vu77j)DvPaDj>Nl{*huO
z_rz&3aQDSu$)M(em``8Xc_@DRS&&KbtA0@WNNg_0$fm??pF!lYc(xy0bCfvHS&e;?
z)i)vOB$@XHrfI)qcm#k0l2i2hbCxWk%fdx6ZxQ-jCHd3r0J=$j`3?r%CErm_<e=p5
zKj6h7i3>gZ4of6;z<Wr(JcglpO1f!1bVTA#B}iV9LsT(*RPswP`n)AIv5@qU>^4A|
zujI(naLrF5T#vqEl0+Xg`b&)ThC42CCM^My3zul;5GXnLJ4Aydqm<=3A({OHya<*=
zj6)_wQqm2jp^}|%z*3mxR2@jT<PCbKMo6ld@Gw&1_ATHsl32R?V<n4=U@1;=iLUsQ
zlJ8GK=PAho0UF~ayC1`u(~{9_SV)kpR#F*!qJ&4azDW{?a<nE(e)t$%isba0P?{>y
zybm>JBvrKKNRtSUK~1`32?c61Bt56VWlAp4MlDP79PMDUC8<vXkRvf}g_c~2aTh$y
zlk9#3yZMszWHc5?ZqA2fp+qbPXD^cQDdbozu^h%gOC&2pKuRU6_Cj}=<moVIE0_F6
z!Nm&6n|4e|r6lKn=sPR<Xc}<mBrkml6IGIL7eiaMB%%XcjbvpJxLS$R9f+Kl%%zXc
z)Jf(PLD>b#bUJWZFA)mic7t8=Z3G6>C^34##U{y}Rj|}7nX7>4B?+H$ikBsyCV;d`
zc6$NXCb>&H=yu84Az12=EXjj2S0u&?h+LKYO0knp37Y}QF3Im@@S<B%5d{l9lG|H>
z>y-@s4v}k;FJs`-b&1`y39WsSy)uw~$=@^K)PUrNkDzo=a(NcG8<LVzXd99=oPvp)
z5^XdZhb4h0fgh3N)0vA=i8C#kZb_1t!u#8j4q7{mNvg|XcU;mZ!pQDO3MjuiA?bP^
z=I=_HsCej}WShMcQ+i)A6#~Qq$(=Rmd?+cQ;QpkfG#E-BNh%ruoRY*-wcumPI92#N
zN)!0#+b8{i5<*VW1(XKgFa6~@`VL6L=#-PQ^u#;>T%@BMc<3tSE(gF(x`+?E?oyi*
zL=H-Qo~AE$9g<4vt#Vj;b3L?qNVihuq^I;XGk`~=hkDWICH1}zFOEu&iXiDNom&jz
zBmI~z2w$m+HUxfBUy3Ikle*9WV1Ma5lyf>RU9$^X0;KzC=@Ka2MNhjRX$u8pPDn3Y
zrjKX@O9!d^EktUj@~lwldzAMGlNKkz#c=812)GDohzHa}N}mY?7bTti7l3H#k6*%k
zj5LQL_p#Em0T|0EsV~LG;-$(b0XQw?(c3pc8bMK|M5(_K=98qg?|>vr2cM%a=A}rz
z=!Q>~M#@3XNPjyGHEB`>75b!0KYSV_L+b1T*D|F~Q8Xb-+WI5B$d;<<ux*Ys-U*g+
zrCD?d<Vn}L0G=<^m%&7V^gD_Z7D`ho5L+bu<2o!9OW!{WQX=K(0k@Y*-Il^cnRE$#
zo1$FGy^PKZsk#!DDy4(#K+Z}NMG!eBZOZ|oN;>TWI8!a%z7z&)q`O6!gj(t6%`kCZ
z`VK9b>ZD)#z^4n+dMcl*m!{BR`3C7P3qTsB;qfrkB$Y^^v)L{+d<U5pX#l-_FG?5C
zWpYUxHw@9s(y!^Q-!84De^J^YUHmtcUXg~Q9>w9Rw2ksoozg3>p|MLkItkahrF$O2
znI7q?dU)6?T|jHQYtqxSd%P|^N{g#LY4dg%>X&wS!_fh$J>v@03`(15LvTa-{B@8a
zspAm<Z%Xagp>0@tF$*R}q)$-E*Qm6L1%Gcz{pn!PZD}rjuxL#BGv!dnr5}F^?v9kP
z8s;aYuTfO&uC$LrBKM@xT>#vde&mn72U7m8XnZK$Z68DHq;%mWxcEq_$pAMcy+xyV
zES(()gO0MUTOj*nF|_`3k{xq|Yx`y0tD*aVESwI}ILq$SOU6akN@t#2W$XV3FWh8}
z9Z=>jd!EW{56V9J6FLvc#=QaXlnqlZ@`x<`cRSqhl4YC${-`X6*4f^&eb2%fAK4el
zX!MoUjA2UrWSvw>drTIugZuunC-y`4aakc<qye%|T45qkc8&%bB=h+P+zDAN?VW>V
zD|Z4ACTos`&TyHY0SghbFb*UmWiP%&8}cX_kD?RNvVZ7PP%*O1gK$4qw$~3NPPX_Y
zw4Ia*==FU{Hj4`X<7M%bW<4$2N+dxR5`?})*_-n)`XreXWmA%6{W45fimd4+c#$f*
zwHUZFvhA}Vk|vu)mt4B6%!vvMGh}ZiVrZGNswdH!B|A_BZP~KBR5h3*+jtGYT-nU|
z(3U5&(;7Zs)+vIC0@>*{h!o0(D5qZ}Tl*VCie=?=U6si4qk$`xjZt!~OlEUHW4Y|_
znJ`o#TigpRm9mZZ;EesO%!8g3=VV|13#C;utrUoA+55DCs*x?A!v9*?TbI#yUiR-R
zn7uk#ivz|~FB_<Vi3Zs>Pl7bc7HiPgBs;ei&NR!qUWdUJS)vV+7iDi9fTc^axCAJ>
zEE}RcXRGWvn%_3NY!#)s+GR#cxpl}&33x>oNTnNBW%7CW)jDNIC?VV<b6p2~uS}Q@
z$!oH-<!HPvyG~zD?vt59ptN6>Ma8TGvM1>wGAPTX%kqZoUI1JhlD)>juy4xLYalW#
z3lo7Gk=bv1L1t7|{wB2DlI`h(n%goB)n<>$7C#3y<FYUb8t=#^-T`nz=5rc=yRvN*
z<G3f2&w?}eWkvK{ejxLwXvRa?qR*ggQntqj<dLlAJS<JgW`@E0$Ff_8pwm&FIuoPc
zC!gk1F!hA}SBhKjm;dqvBo4?KIgoIcf43MaUF0=+=yR19A$a59CV!7k8@bEhIsopV
zd~78o56S&D!@yzrYKj?o$Q_#?;wkUW0Q`vj^&W_L$=xV)e^kz1i9T<6NHT`!Bi|7R
z;w#^0F9Y?Hucr;bG5P;WFj{~4bH4(AT)vmim;}h@J%P~%$`fce6C^L#0CGb9LIV1N
z<yCZ$Dn#B%byuPC1_~*L$qOko9xfMB6fZ*Va0QZ)^1YO!h>{14!CtgnM@M5~<iDBi
zpt17CK&Xk6@81T*N%<G_N<Af?DTDj*@<!UDpO*K8LTQ3L<`G7bC@;tXmn1Kb1xc3w
zkOkc-^7l(&DOJ8A1@JTS4RkN2$@O%*r^^eU0+%5_Mm40F^5IgDEP3e-S_5axM`?GF
zBmeL^Eal1zD7ld*Z={OjeEG|tL9{^53I@JVzJvn%MRM*TNEXYtIl}uA`Et5a%jL8E
z;7o-)+la<Wc@KqY&dQyP0GyK-oj_leoY{uHYWaKa=&O<6!M4`!P%HmA5}oJeJLsT7
zoxGK9m<#eJY1>vW@A8DD2D#!ANTb~21b|KQxNeYUc}h6|E%L~RFn>`#jZWWOk~iIj
z+n420A7Y+c<=p8QOPgH62E1LKMw{~vdCC^_U6G%mwX^-Id{-5Ko$>%BJnfQSo)4wn
zat3{qvPbU4f@rV&kGt^jn*576Oz?Gi!CDyXllQ#~FZ$&dXQFRF9uojEC|}nOr8ng1
z6fql;Z~E`Hle^J}D~9D<sy7*tkJf^W%8$MTWw-2dN4k=3%ip6{%$R&1z2?W|&9kBH
zj{K>e;3nj`RC#n)uAr^iJ^5NH+_*3ApAHWn$ltpUZ4c$Yd=AM;d5;f#dL-XM&wwfU
zy(Q53Sl+Gx&Qb9(rFix!js;<yPKvtQ@M*uo{zn#C4=BEL2J5V--vXeELP<MdSH;}D
zFyW@yKrelF#cV4Y4=UbmLgOJtIjv3(E2b|5+(Yp<?KM0Veso0Uh@xf-8od-7euUkl
zigzhL?5#Mt9K=U)lFEX76*X_5@0jBC_v!BNSBz5C&2hziN;L*3$~n*-sQ9u7BuEjy
z4vi-ikyK3;tdP(_*bqesz2-v|WptD%OmR37T(}}-B}jzgrvGy@r_Z<h(P}$JvBC+K
zVilgWT#Zv4G{F2x#bF)Bc}nrdD)hxGX3{p~w8F0fA_<CBHQ*8zuRMfElHw*+2PG>i
zC_R^=*h`O_RK?E&=sTm>Acik#iVKbyL%QOho!~MQg=Of=R9yUTcb%o!K<Tb*#V3ma
z%uz@v9G$E9#vP)0ij8C<UonTaT?L8^3f&ee0{y`iDNfPIiWQfs#HmEFzYC;PvGiFe
zD^o0@)qS~Q3B_|N6lD~BuT)IZ^Y^S`>wbt-DH<m1Fj1`tbwz89BAhbOwTh}%AkHgZ
zqb*LI!ZQ~JFDL>B@x#<BmKK6*Q0P~JYgGJ9zeJNFn05utit$u9+M+PgwRTaFCq~~T
zh4@MIT~;ir1fW&XPMhR5g~Aby?Fz?G`W|nG!qW!e6~(3%81_|#E(u<AD(bevwJwFr
z9BAuS^ioW(N1>Vn(yKT~$=hp+rL;%6u4rinpil886^QjKJg!37fWo&3CI%IIsW|C|
z;!R2^4Jlq}0lBGIN|Eki#if;0vNxib#e<1a#dI$W?Uo|%J*c^@I7b)vn1WdipT-sM
z{||^eiku2e$%Ml5H0<70{Nn&;?kQH$9e!VNobvY%6!^!=xYHErv{sl@NWX&@j}-Uz
zK<AX=-?I>TtXS0ppB$Bc(7VaLPq~XuWE@cP|0{b|9tnm)7v-*9Ag;<yl!bCrD%OCw
zD<f&wcu<*?34aeMqjNwGD<=Zrwuf?n&UAVzpQfPL5#<)zR(mN!Xvu$6xs5(h<*gJP
z1?Qv8p+%gpa`TID)Nh6|-GAv5xDWoM<B$Q$moK9=P`QFuV?oLeN(-J){!Gi<V5NEo
z`a+Z+(;6pK`QaV(g(;ILT^6pi(^51-SwbafkxKb`j6O>Fkix6c${iHniBTHpi59D@
zSO<8V((!vt-bv*QHOMLDMmyDR#4C6C!BV2KaW&K=DQB$(B3b$MYBZ)OpC_fM%JsDJ
zKcm#pw=L3?JTpkT@|nGWXDB~O2gy{P35AI)<)s+-l&y?k3V4ok^Y6grDwlFW@|5dn
zD)W_RsnDuGd4DEFnF^Kf9Ki^Sl-sBnxmbDa0Z555h)Q)!m2x_vP^Nq?4Rcwp3{S;8
zS16}1g^5aKu^1v}mGfM{ol|yw30##@M2A$Wm2c2JU85YJFiow}MwiEV<$WPU>XbA8
zi`pw4_Rs;-dgYR17)*om$5^=EsQf(<h$iLBbi%(``8FluTa+H}qVJ;e1q!!ZQZAzR
z&t;|SdCW|!at5Wn+LR+y@z<`5>4QjzauGRtMJYN4WmlEChXCkQx>KUIOSz>4BHc>!
z=IPV;4n4|Ew886DTJ<n-P5C=z8T*wL`4AmY8a~E+4Jun`f^R4t{XmA4>wg2esciS(
zIeYqY`<7<l#+0wEf%$ReiDLBKQMQl4{DhJ>0diN_5riM~p7I?>=)A8SUI38?O1FC;
z50xiqAw8-5+ZS3MDSw`c#wq0s!7%$+xkn7RqiU2AM*CEsy?{A%QoZyQ9Ne!G&cnnU
zP<?NwEQhn|I_-2^RJSjJb5*6aL5-U#ixyDsD$cXOA5>{xL*pUUIVx2-tn!y()E=rG
z?ch9BxwH~KqMD-M@Nw0~P}mJnjXeVrsJct_D?zGg+7O;leeok)3sx<mutkWfj6oF+
zp{infl!d8I{Rl2x)l1cR5vs%hn2%IlGk}Xy9UA~5T2(=7v=~(g)%3@zUP{3z;#6Z)
z_j^*6Mzu?)RNu72nRr$30g%(G$Uo4Spz>fsGEo)vGCWLDee^$&WYs5*^of8J73*iP
zsjAH?C_SSpr1e3Xs_u7i>8kIk3N1s`|29N2Rp0Ih$x=DcsiACD3=@ONQFVC1M6T)#
z?bGs9HS|i&S1qJ^#{$)xZ(?MHs{hg2p-9z5kL6<3zqFhxQ-$-XFsWQMEds3-sy}Ff
zT&dba2kp+Ps(u0foazH-^i`>TH$zRe>NWaEUyW++XW-7O?o+`*ovMMtI~P<6$_CY|
zu2q3FsLJwSqEU6+36f1JGgZ?ztNNG1?H1Jo3Z7h4<q0sBg_l%;D}lJI648pjRkbMz
z*Ls_3v;VR=c)opPMPs+>`LjUusOr9l`CgU&9st)=FH&Cpx@y5^@UTzyWExELt0E}k
zJfM2=GtAncDvC;0Zm71Uqi;wxK|{K!N{@!fuqtvE+#XTYcSGl>D*ppGb4xXA6e71(
z#dOJzsSNfdV8>N!VxjGh%DV<+LN!6@(7UQbo$%?N%JMeIeN`mIj2@__-2mXBDyIfY
zCsm0Qy?CU0umQTKRG(1>{;_I+0&e@%GiWjBq~387lKa(q3g5Y?yQ$Q`Rn4Y3bW?xe
zNmr-4+Kpl`2h}wn!_px&n+f8ne%J)W5%thZ5b;u9r^Td?dKIPoebrfY5b;wlRDnCD
zR@0B>uMX*e<Z<=XV$5iOdg4u(2vqyf^%SK3n5sNZs9h+)AFSR^Ul9mVztBKCh*0%m
zO1_1u-F<)vS5N)~H4*B4k0BbV9$pW8l-fEB60Lr#86%8Qub`8CvFcaoB^;;j&_LTs
z^;dtP@05BTC8p!m$No$7s+a!-WeMtVDu78;=On|mBz5glIFqb?1sC`K98%P)-bZVy
zT5=aA&ZuQSgG*C)eFrXGz4sP$XQ&5AX{P$eW;mLqwo*VSTmAKBOi+&cM+&Xys$Dyw
zG*6xQ99%0@izr@Lq<+=kYc4LbzgSRKrdHEevdYzwCD2l#-WCtnD%DX`b$nJGd=?_-
z)T%R3U8SBuYlmue8O7^r)Vq2?YSooIz|X5|^I@n?{ThXzFQ~)U!+O2?Ukl7OsDJ(m
zsvFfO%AvDK9YibeX7zLSNB~>ZuSSBstp0WtxK{Nn0c6_Ly|iX&S1+T@XNS6io@iIp
zj_V+DRsBaROmwOrJO#-vb@gKmsaM@b6^Pf=bKGI~x_X{3L`Kxp-h}E=^(=~L+)}5_
z1bkdQPQ|Bp)LskdB|4!lqSG&T)n9bM(mi!Hg@f;_Z@mI;Qq6oHb|0xd7J^KvQ)p=W
zG;5qOY$wfAOQ2@I<}QT<4`_ay1aa2X?0_;C%@BF$rTP4AXgR96L+KE2%|$w}<)eAK
z5N`Ww8Y(DM?5BBxa?r;#DPb_-uUSGdg5#Q7JunfViFg5`ftpT=i3e%+)Bf~?#+x>+
z!J5DO&={h*Kyw+U`G78ja7|GyeuD_jB1*ePYF?$KOO)n`5pdC(=-n_Mr`Z<_+)2%n
zQVLa_(#)Y4alB^R2s}Nl(a}UDXi{H=r9=(;JjRrynNCMMlQq#f(3YZEPg(9%&9k&g
zKco5ORd8vV@85$+x+a=Jf*G3CR7{ttiSLI`SsKNAu$!xi(?YU9)71j5P!shjh`mVj
z#cZ?|YySQdY>B4lCX|+Hy#B%@lxaBcV}i>yOE*Gkg=YR^NLFfUC>(rNqxXZO=QIIS
z;ZUVXp!I6CX3t*Ot<eP1(cN0ja|a=EUSp-rO`YcccEB%a6c%vx8rEg>HP|&VyMS-j
z@K1qsXp(8wd_@yF52L@T>81jJPR%FI7+RO+RVohe)+Ex2x?atU@6mTnv$F@1*ELfc
zV6abfnho9knz!hyE(4nRw7?zI{7nmr8=4qT0B&mbQYe2|^NSb!9nshWkANN3?4h~5
zrCE>*^S3p<l%*KcY;1tiaZP|TT)U(BoX#9gXgIWnzN?A*6EkyP^CTT6eW1y_3oQ>d
z=6&d!)Kt=Wq(>Tq03)2zbT~ovW6fM5j@t13=-a2&QHa4w`-<HL{C@2Xde|P&iua?{
zS^MWGyl~OZ9fnd@?W4VL-%UG2SDCw35(&wJ+KA^tJhfLi@WM-Lq&2`%ZT<5Yp|>{W
zcl7yar@5igR~teRV?XT^RQG&bTYL>;3D7=CZ^1zAJ2I*r3DTPAq}U0qa~XiaS|gpW
z3(<~KwO6P%p%cG$n0D5BsEN?FBE0GlsogyRktl61Wx1oZ-)#dtM!R4g%*SeLr@_%U
z?J`<CpVV$ofR<BQ2JIT-wMDA{IIVs71hgb*|MvlH=908u(~}}u+w6_j6s_kLs7cjs
z^@7qf+AXxlN!NyUVJ<SXvnV>7shwX6ZCTo1OCgf2?MMPHN1HSPE?4VM2J^KplnpA-
zKGOwf3boUzIIT$QLtm;X)-I-sn-XoiGo?yPwR7kk$64*YcQF^|wB}lLR%vHb=CWFQ
zl}gcTwA1L}cV6332yJy*A=P+Z(C(!3z>Qj^3h*YaAC>qtYo8cLUyF7#Mfxsk7uNxI
zS-Y(cc3ZWDv>$KNKEZ>QE855O(FXfft?&~Jrc?X&lR$K7n<?bht=(1%M2|M`4Ip~8
z@6pe6U3)4Vl6~4=sD`{>n{@?!1KI%!jSOn@XkmUs+g}bcr1gD-LEO}S@f$1+Yps+_
zx}`lr8PnU^XKB|troBtspmDo)?^fu(qkW|hofFz)w2!%`4Wta!eeF$30Y1?3)<Wc=
z)?0_hNp0*m(EV6Ds}_=uy2%wF`*cwhu5r?RtcLgdbqN$(KA>A20P`-ou~#ADs{1Jt
z#7+0<1SH*c?G%PMsI#XhL)1g}Nhn<O)X55A;)u>w2N%6`UL}w@s%!Za#9McH6nGz9
zGo`(Jbw@fN;;(Z{L*sE>2!%fabUF0f2kJhfs6vqL(gHLF>n<GwAVe2k2@<M17zPrq
zJ49#aB6NrCZLk}uTYMCgAEn#+70gHLzP<uAF*?m^^u_6%>0r-E-T7x=@RUx?M`OHh
zoGM07>lR}b>yV(^L67$&T_U~el66sDXiU*9piO$J&aD;$JfkbB0hgiMwhObKsk40o
zEm^wG)f7C+*8M~>Il5I8`pVV$k=;DqSQuQ)*FDMrDbOva5}!idzqip>q;r}MpNe(g
zCc>u@-MAmPQr)`a&|Rhr&V{9NxQ4z8T?w7gtkii^rO!ECV=dgS(w(3mv|4xVy;(Y3
z-MZTpNUPPYIuAAHbywoiS*LUN0sewcM@3upI%hf(+MtWffcZvUG=)-|bPZoYX|ryM
zR*Wq=XaCP%n*OSN#wGyTbX%0L)UMmL1*AiFl4@J8>OQ5=VyEt6B}kX<*JbGI*40tU
zqepj{UPHaQ_b<cHHQmrw^j+8GQXHU9H%=u<{knD2Kn8S&sIX~Jx15p%H+1#U01WB;
zZ($5Kb=&RDXdTuqq{YLC?l8pxMs;`o2Q{~KFAf7ZrrSlYlX2ZYAE589?lEng?&*3j
zVDR^KU;p<>Ih}!Ccn@_PdJs?QzWy8oe5CuA!j4lq6$OwV>%O9=hNC{63i0>pr+)(T
zPWs9?I}rQz1?0s6{iZ_@b=J>+0gW#D52=2^RsViE%)9BWe&}=8M|}<V59*iDk+ehl
zPO5V{tY>`)&O;wr2ArqfX#~2D=r_|g$V<PBiLo5jZ=m?Mw|*nN6@2vTKZI+(`uhp=
zK=sp)QAzJH{q(EQ=C2QZ5BTHyicDw=&|6P~3)G)(06s{ca2^9aq2FkM7s2`~v!Odg
zf5izRq52170EFp79)LvZzovI_lwQ3Ns-yJ+ieAR(*HC;XRxelsEphtwrS#dillt_H
z@br}a>*rxUUhm%zE<yj89$tz1<rKh9(r3}0;f((CK-f*w57U=I()EARMm$45oe~q7
zdewRu%+hz%qAy#YL_7E#z19`Va`nnQ7|he_=<>+dcgvuxK(E~nN9~3Bn7`0jr2i-i
zoyGc>N};qwpI`!4s+a76Xqi5P1yZh8)xkuCUPOROeFh!3KC3Tjf`{ky-}{18>Bq+*
zS*>rTE3ihNng=bl`p!lG&g&N?!?ikn_*(Q`(0fw}eZ5`3X$E8(^hMjiHtMH8gwiJc
z7`?cf_3J3O(4v3C4dkN!1KQSK((k8o!^`?~7PPhM_4E<YHvIuA4sF+0eT-pu=xua4
zU(tI^gUD6=d*QIqspkvP*QHORbY!=Fl5U3{z5U8G_|~hhodFZq^cBxS=DL3G(*XAA
zms9+_U$4ypH=zF}5JMZ(cT;@mhTi@*B!~3FH_>-fpB{oS4eQJ4bugmOTmgfl`n(Bn
zxAf06gS)NIpvB6VzKXuTF|IGT0e|o4OYN_KPUws2+r@YF9<*P4p#PD|R37RRX%R4~
z&!H{aBmI^zn3&R6Q+dl{y~k20bu?T(ipG70$Q~$lGPo^+hx-k#l<z%YSaKSiv%&8k
z;4X&CJK(mff#(ECH$(YMh`1Ym%cBSCK|>j35Dyuyw*zt5FsX%Z55tXN5Kn`GF190v
zpzToOW!TyR504t!D7x)!_=KL)K8AaLU=Y5B%vg-j&k#fz&trxFdXM-U`u4-Zal_bC
z7*c?tkX~4UhHqYnNU-6KiDD{YhNBX+h8vdBDmKEfI0L#P4M*r<5@l%n0zO3>zBmdJ
zV{oB|U#wvPtv%ul&yT{yNkg^+;HM0}yFua&oig})+Hj3--vq<Vbhw>p@R<uolML=^
zkYs~5eefg2uwiN%?!Qz+ELB0BF<hg4W169elCtTBhbG8m7!1#&G1D;Z2wclDXvJvE
zHn2NkH^=bhw`j~YJV%?!Ji}NQe9AXCQAo7FaDhIwSO`mKEHd;_bh+5zNvqfr10xt(
zN)4+npwC`r*h!}p$_*<il3Zc9Mo;-l!=`uO=~=^~_aJl5@akFss|;PY;b^tNiHU*M
z7-ktEQfpWh3cz`Ti1s>lhM97Z3x;n$hHLeP5B9*d27~t=02&PkDV@_~IJ68}nhisA
zbF|nEb+od-XvmfTc*!7~gU-taMKtiOhEYB|Z8OAug}zS1jwfKS+u%&$q8`IO5A^jK
zlv@C}X2_t8*L6efESTsstfuu}zu~qHBO5SyPX`$^Y*RyW)Nm*b{@ymY(}h1~us<9J
zV%#uJ>94zn{G%{&&rm`U-TQ`Hw3K*YV37HThQH~U%cMb0HGz)|VIk<7GE{E`d2INK
zp4pDZ4{1vF8P6NQIT`&a46)z1^KAeQ7^l;z24`b&9=vcdhFu16H9lwG2c>RC)?7I3
zZVaY<#X;kA28MRXcrggN4;!aZZL5cIjMgWfM$;s;9WgGZ`VcSUbc!+`HD+D|@ixw-
z3&O`3PWfA3<JOC4^fNw1JD+35FDO^!Z>&=Qe%$E7g@pj4#}L(i1scsXv>;>9HaK;{
zIG6x~!A751z=s$;J76i)_}v76VaDShqcPm5`4=R@sQnR*k;eM}wiiZc1Gs48-UQ5O
zj4_Goe`1ZV&qiaMaZm}>Cyi%080RTt)VCn<#^~4R{yS}~rb7}5M%HRLlW2VF07#PY
zHy(USHkKX-KE>$HMq{dRtOH8V7*A34RGRVSRP?1A-`Iq{3?sJyeVN9^l%vfu8s3K&
z*+ykCxE$loZ!rnE#`6@kEiitr0x2}6{zZpDii~@NP*ZI5r+VrVV~8t8Uutysg-n^T
zk+#d_#w9x;Qemud$0#a|$?*_5Yh3aw8qXPTOhKf|IQL6<QEhD8jG@&SYpH6!)|j0S
z^XH8POW<#vvFQ!KFBtC<S8qH;-{i127?=J9-x`gQ5U@?g*~@`wHr5Y=v=|f1q2{9T
z`woyx#-+5oxomvO6Me159pO;ZW;9mAe7o`NAVfNh-|a--731R%F&9^jG3OxCX?(&A
zkuIb2RrGZmCn%NCWBe%x_ImBcU+LA+XKbbQXTPzZ%nuk>zlhF3V-dxGZy488rS6c?
zixP}CjYU+!Hf((71Bi?mIc1oOQDgfBaJP)Pzk$1L{QEOVju|&EhR$(gkUQXajMBf*
zH(~r}7!!2YcsT)D?iuYZb0K=)SVo>cFji1p`Ju6kqE?f}$rLDkWc+XdUQ8K3r~S-h
z<33vbI+{*W9nU@!KMsvfrrpcH?Kiz10o?~o>*qt6v&m}&T3k%uI>QTBQ@k4*-Aq|o
zAnvC89WZpz^s}Af|A$QLDKdN5G|e4qJWMWBf#7L+Vm-JcrlK(z^fJ9cC)kdfq!bYF
zHn~ytiI3@@htTb7diEZE7(dfODR9S3opfsDxam7eg#?&FHb5lM)TKgSkSU0^mM2W_
zWP=2oOcQo!3o*^xiq23IBN>P=(=p1qhMVTmlt!4^X%`x4>P<ysl*w=oa~W+~LkXl9
z)9X~h5Nom}K}($Jfes=kO)FvmIBm-0!ft}e!ylFsO^3tbZ<5Jr5k!(rGpVRG#pF~@
zA9P4Hh5v{Vo-utI1er9GCp~*JO%+E0%rb3_!~|uV;#)ALJk#2hu#|6lssyeTn0CE@
zzCx3lF61IpG5sT)VpFIa;3cMFin^AXyz<dkX4?HUaOI}WQixQT!oLTpG;Q*ogZuBS
zDVUz?=S;Gd5Unyb2ElH%$rtYjhZ@u971*sc?W6_%dDFY}MZh}Ktc{SoV9J;ST)pWR
zdbc*1D$M{iniLeEZ8A092G?xzr<=0H<V`8AizbE`l9x>KpP}rsY4wlb?5(EWlaOgM
z^}GwxZu)~tgF8%486a0oU9?TPYMM<I8=a=(RCd^9no@#vn-(2{(jL=yT+CXp>H8l*
zu9@cj4#0I&3}uD;OqN;T`b}~<rhCA&hsHT*TJshpZ<yGZzzx|=dv}1nX_|2wP7Ry>
zd;*9O(>M<XM@^q8L2j8AJx1eglZ1(3kC`TxL2}%bNnzVNCJntnCQMf;OLW)N@HOn-
zGwpdFxcep(g##a$#;Drzq3O=Y=$ka1ri=8EsVN2Al*ulnfa_zEfeIlU&B1-pw%_d5
z0N??$Zvu$3dA|jC7juUdlCI`B2{<=1<2t->H$P7)n1kkDGBMqU%=2k+c-ZVt$DlmS
ztJlFNPqW88a7WC`sMgfWyy6bD95pXJ3`uWuv3)K&eazp+K&h{J_RCP?XMXz;WR96{
z(~{5M{2M)sj+@JAs}^8R^aK}Z{*E4nLFNc2G@dY5%mOah98W8^5VMx<%~10b^r{Op
z|4TX3aC7Tch(wt4ra@<<IcpcpN12zNA*In~&LEV=m?J1#6Kj5*mNIeXpC^GhX+CO4
z-)Zwt$AL&Nul)uyn`mA_VZ9`?w-+Wc+5C|YL{iN2U&RPh&A(Gd^Ne|Z4Y)M3>wHW?
zhWY$HG-jH;{)TH==0*W<+2(_yIk^9F%;FB<^UPm7f!2I;SsoAt=DFoCUugFH2z^E7
z0?JJnn>{GpRAzSn93tgr=X@xwFn>Wg$Vzk0QE+F??^2=GIrG<4YEfm5qIgfWd6pRd
z)|ky-Vq~>uRS@9k&5uy^Vt1%BKSfWd3ucE?P*ZO%oCZXL`N=-u8_ky*fM_z`t^vN;
zoct~%Tg+?eJ2Dr|14@kWl6fJO(Ox#cK&z})a{(O`ZZns2z_puYdGNQx{0!xFu9&OV
zpz*5tok!5wX+E+OhU{JDuc(Zq$Gmhp)byGw{sHMTr^P^bzqz;(UJRJ`R{%d~{*(5t
zH_YJ_e;hJ@Lz%^!=By>)hRv=Wz>SziGXWSipQGLDEwg(7+`es&?S-;C<}b1!GGX3L
z2MX?*o9Vv2XE(<!1OC2wElt7$^Yp*)8$2{G4ubAU^RvqUd}Q{ZO6n<d>TWpt*!&}f
zlpHP0J`g8M-#i%HZ`odp$va?q=@CSnEkQrPl8dE#FHE>vBK|uBW?80!p`(_{ZiskW
zv^yc<W3j(Uxkz8jxnh|2v;4XcN{?H1P|`KPGXDnfffmi5&>dv)d5FFfmKpCuGT8Eh
z1Js0A9;QQSsAb_tXbiIy4Pt`AElVkU6Jd!N02gUdQ!#CnWg4YKqAiM>XpFIlDI=3?
z(c13=pJMTw0mK>0rfv)-&GPmSXiT?!PJ8JL3vUVRW?Dv`0m-r?zXQo^%ib5EG{^GC
z07j8(Sx5n~Jd1TNMDi_nsR*XPA`(KR(BkkCbQW1QQ}I}_#f^fnC6*1eyeYLzHc=|5
z%#u<LZ^|w2(Nd(sGP)aTDlKCa2|sIbA-m@+sVV5IvOMJue6=OuB>HMBTU=nb*5dX8
zbf32{DUn-e@th981<Qw&OR2X+kfRNjMbqF#qh%*Obek-bRp@KB+*~ys_g{-8kCG@C
zEv+x1^O9xa9f)4G%%Jj<R?Dvw5N)&YDZqQhqW%yDuUfn>qOsG${T6^OOIa|ctJ{+A
z3D<fo@4W!hYdKqp#%q?5190ZLWg6{s`z+pWn3;ad2HIZ_SRC=3u{#V}^7!byVHv%F
z)*;IhDvG>mnN4Mg!<L357#y(}sbX=|l1W+1Tb7{L;M#4=gV%9&j#*xJN8`9<Sr_1U
zEOD{GO;{GuZvU=j$=~R^XL)`Vytr=>&j;XvC8`m_eQ5b|E&%pPizmMA>hQ?oHXEH&
zmbYmS@z}DFma&dj_F6c+&pPQ1&dK`vzYy7PUG+DB2dqE*i$-VbFH|?;VjWh&LszRI
z1dRu+tD7*0LsoMyyf|!a-42|G^`%(gJgq_W=s#lp{ZEK^*{zYWFnH8jM^RL7E0;EK
zKGxG;0^w_o*@Q+v>$O1uk6Gnp-ru@n2232cs;Fooz*_kc1`}xgwg7!W)^}0x<#59K
zFa7qx)+bK@9%9|T8j_*b9hC43vkLypO<O;7gclK3yYCuki?rrYL3NaM<0uf()@fHT
zrWk8~ChW#q=WfAt$5|iIxz>}`^%NmGW$mL(dA!wO6B<ujGg`qVScB*hnrQuN5q^Ut
z>sdNinrwBhg!vR}HYKT2t$p-sov}VmOQ1BXz@879ZY`sbSccVe1=M6(tLa|>WLZo5
z(U@(WqFqCdb;}*#bFC^W7s#`&rX^dxHH!vQVBKlMtQA^E$^a;`j(mtIDYkmjsm&6r
zWFgF#TCdXbx6Jwky&KD|%V$DMg;o2R9cn7AV=rS&XRXmx*l^BzJqDsxR(JY`G}YF>
z=u~};Rau6i)mopW#q<U1G>XJETE&hq(PW)74_-7|7gFx0#rhlv1}|ERVxjYr)k<03
z%hp+RG`ZFK=McCytNk}vXt&nBM^#ZB*2UwP#4Fb7TadYGok0(iPV4h@<gm+{OO-_3
z*2^Ant;d?R8Irx$>rbQan)TW?XuEFxm1efj`ok;mqTf2a3+4x`UE2W|w1!al^oI2j
zEyRYb2|@7ird5~-EyGri0*Zf*Sh;R6IBIPcz|t-2nFWx!ZQVH&E{<8-=&>_y&AA9m
zcdS2Eft#?dhyi!ky0aHb?^zpW0)F3`xEOs8tVRbo^U(Sig)t|sYhQ$xN7k-%^i5g&
zt^n}ZIyr$pM_U0^OxgF@yl=p7C)@KB-*&b=OMz1tTlsPjS6daGS97yfTtuI{EsbK0
z2W?8)z<Jn)CLrQzyGfD9BesDt^m*IjUV(WZ+a5Yo>}#w195d=?yP6EiW40qRAn9+r
zmx;bWTjmdNEy!*geFB{)Y(I5EX|U~Q3a5nF{45}$Hka3d2(vvy`-^bfAf050u!T~d
zCepT@?#(FMRSt$0ZA)fCB*u1?7J0EYb0xSqTjZzEa?<8tgybpP>jn%v-nQ!!be^`c
z-oWS+Z1(O^;1g{F^z2TuEu>UKvTaKrxD?y)YtWWz^QQ9hGq&H70Zg-THi4wuo__;B
zbB1jzenW>$8<*aqSvCVrLbfgF6Nu#4%4y}6YwM$!d7dqe)`9u9BlN;7uzkD$jfJ*E
z`wbw9Y(b+S#kOl9ASE_$4M?f&>I&E`vn{4aTDdJL2#poCb@gzq(zf9i8qeBnD>1Zl
zwq@1OU1jT}v}Ls|>c0?x&4(gOwYE140XT0vLbpSmZCVq!3%2Thkb2vm>vaD$*s@Qe
zv(fg=Z!pnhn@5YDW}8DkhSp+>jYQ)`Tha(bF4-zt(RbOliH*5zwRQ9W-ewbCf-~*5
z61wj@Y(Xw?yVLfNR)t-*y-&fzZre{R;CgJoQee8*7UYdf?wak}OLYHTx2>Fm$>_5M
z(ofNEdy#Yx*nXwYh78&^QKa>T&HN(}L$-y>q3xz^C4J*-*k+7}wh>z&o$461y|fU{
z+_F7shBLQquB9MjHu+Mh9=G+-SFY~Z`swWUgl#5$R`9MZ1aBp~!#&$4XE3z;wiUi0
z4{Z4q_<U&N(E*7`+xi}eKKegL*B#eo_5Cf=mYJrdS(ceCvthO@t<<tCt<=xnd+!h5
zEE^w0MV2TV1O#L$OJv9r5R|DRDhMKoY#Fi@QO56met(_UIrq%x^E~&t_ndQ|&(8U@
zSDV^-?-0hOcOIv;k23?4G+s`OP0zt!7e*1)(e^U3XhX7(!KBy1e#Se4u<ObY3ZU!&
zL)!^uZj3qfDFk=M*$*J_tOui+KE&e5c<0TaUspf2#Bqa)-G>?8HxQH$Lw5|AFXNS0
zq1BJ^B4sK38Pmwm&kA6)O@SE57_R_l5M$j9T(4lpUrHDbVc2MAaD*}V1ja%cGw38y
z7^8{~)P^&3D}fzl9O?rW!7zOXry?0c`5;Cy);f|Paf~r`6l$Uwu2kcTW28|gBc8#d
zZToS?UixJd8MElAPGVem8X%cbM)O@N<0QSsPccT~;C31#VFifk3?XeQGZ<gd?3KxQ
z=L)>fW}F|!Rmfr7-~h{I49<hSJjOp)X`yn4F)hVlKBJr#dj*VOs`V8zPXB-JEMoyR
zMHewFl+`I_tfgfAIR@(y)SPF$LG_*z#%bEqmNJGrFjmGmMj766#*h0jR>3Ighw4g3
zz<I=SfzkLIR9|FVp<>x3#xKjM!>5Yzrwm?PW(c-ou$qxIgy^p@k|_~+m67*6BD}`f
zZUjpWqo)RAwT$s_{1n$249e!zF$SG5R?ldqBHazfBl?b41LKdI7`w?hOO7@&W}byy
z6T^=x$hR1)sDHAV(T`imG3z#i6N|w%#t#W_znvkV_h1L3@GU6qWVHMW(8YKy67Jt&
zG%N&XH{%8m#2!W=`P7SF3y$_NE-wdmm(hLzpr6t580-!((tn1)AfxLNTpMC+42Rue
zhJ?<?jxhFY2B%|`VWEBRJw_d!4Z6<|QmS^0arAE}eZY8}YMbMX#Ye#UkWqCKV~-d^
zCS1}9M&U!KnPkk}0o_v!1$AKUVVb+Z>B0<c1lY@L{0ypHnbEy)<^c1njnL`Fd@2S4
z?#z(YQ0?JheoZxcPv+VwnD=5HrbWy_<_FZJ<<0b-2XKhlJ`Unx=703A@?n1Q672di
zYp8?7kGWwFeDY_iSHV&Mb9Dna1DP*-f*8c?rjJ+!GmFzf3}LPj0~}%Y+=abxrj#nA
zN12ZI{Gl|0`4;seMKVMF1Wy#RnbMlan0pr@&}ilj+WEyWKc<tovCLbUV2NXvyp0Is
znW>F%<~TEvezX(JypKRkV2VG0cp`Hfoy|#NPSA=onVC&Xw-n|?26Uceq9q5<5A#*W
z4{-4mQ%QN8G-edFrKB@+C?k-;<n94aCbNh>;dPq%BuzhA%v}>;$!3P105OLdMIFSs
z%u33n=P_65Aa{nj?rGS~XC93JO98XvHe4%YdeJ7}EYnJv<s#;qAP|e0UmT{^k#o#{
zj8Jo)88VJQOPI&$99t=K=C80+##EL7D`#@9KwAZKq7Aw$nSU@ac8R%{(zn%2`FSY4
z!c?w>hgX^HG}~Werqki#8s_R>VWF1!jTOY}%x%=^S;yS948(e-a*z&#-eCHEkHJRf
zR$8w#F~6i<qFc-is-iYCU6+A)n^`ss5-rRos;Razn;2keV;0LnY-c_-fgh%W`5kSW
z?=TbS)zi%!q!nBbQ@RZTcbQ>p0Q#BYAox4L{OK@a8D<tD5$~8a!i;_mmPVO1-+^b0
zS)L1}5122$05#)GPs$%nFy~ibY?7Hu38N|IIy)@wVa*UjjSDOD5S-b|+S5h%I!oPv
zOL>6hasU^|jaBLk%#-y$>PYuuRd<8)Agg05I1jT1BcR3M!^(LT27OuPDGUa%LSF-G
zAj_MQJ3*{;nr)A;UbAB?lvOYSZDFic)T$Q28ZQDdl68b`ohX(weYGTpwS&scu`E|A
zR>!f5<{*d@thXA0C9qziHFYBES?Y33VO@P3*W#puwUa(9k;)o8h>MWUO86U2Ww2J#
zOrFWgSOvjsR>2&M<*=@-0mx-Nx(C60)~WyBcC&U;&toC0D;CZav+6UU`y9)kdcDrG
zR?+INjP)U9(#u(%k#MGh6-LFbi!32^_1Cf-QB>Nw&N@#k<~r7wbbg_p)kvqUZm`~_
z<9m&)-&nBQ#CqvPu-sxT_Jcq(E0BsJw^_qqz<dkq^A><s){G+nZLEGe>(b7uIRo(y
zR*MVFce3mrz`9tbZy?^yT6hIm4{L?P4%S}QydPn=kCj2WrMs+meGv8lD~CRfKFA8^
z!tM~OtQ@+BS=DV27-21<Ke8BQ9e*2gW32Zm|N4M+`~j4XvqIe<KEZ0v0_P-ay$S}W
zSShrCbY>^jL2eJbotkf5*fR{2kl4#!P9>pz>{V1UbY-8UH{Jnu487>x*djVa=+6E#
z8`?bBn<xq9$<|Ze$%{QR1pXdm&wLl+-t2YM^LU7Tf*O4evlp+07e4HZbQaK;o$?(F
z`LS0BA?MF7eHO$3ws+SvOK`KXcgH{?h`n3`^TBK-RXRi1JwZcj(SiJL6AVVM1yt%d
z#$HIt)o8Z&OW=%QpL`###j`_yhVJ8R&QSz<g8ejo95acXH;%DncFPBdC57GfHME>!
zFZ%_Krm>gP;xwJjq6*q+_GByMve>hKf|hLd8k%nM*ypI#@(jDw5d(>Qc5e-M&az*i
ztXmO#1_#a*vjbcZObPqRc<3%=PtlWJ#^zrGXE}SQ4qjBSug?Xsk{w46>;<;Q24xr7
z6ZA}9Vz)-aQWg6ob%S1JkNyB<)$9vAcyX1TZp7F%_D~=tY-`xVlqsrZbLRtGXTQ${
zYaM&88iMugQFpL5u;r9Nyvcqz8}g0pcp<!KVoRtta*G{J*}7(SK5fKqvkRy;*~0#H
z6P#&f|DFR2ZS2>2AkfZMQMeuK$9(|qu%CZ}8g{zbSEzlchyAetVc%uHPHW?S_9A-i
z53rX{f;h;2o7RCt?7&q3!)zAyB8{-0UkR2`cH#_}xW|6yHxTc$ms4-f7<<z<01wzw
zdI5~H`P3ozkX>s9_K0nuBI*QtcqSDrC)vLw!~H3C+CG43_M6nc<ILHoKoom8i#h;Y
zI9@a*?d2pa#MnMg7VQ)Eb1JE=#Fg{J3m7}V$yorUZk$_J!Q#&GPyl#v=4=M1Cnqrk
zTD&-m{(u(;IipmY_vQ>fg;*SiIO-q_9_Hj-g>OEb{+9rJIRTwe>c=_N0v>;kq!<zb
zoL^T11ah89gqk2u$zresa{_0=L<mQ)6hFlgPW}Hk|8b%zlNZLh_a_9xIUhyi${gkV
zN5%CB&UJcHBRQM@|6?Ey&Xp~Q;uuHqCzM8W7_@JV;Y?%#i{+S40*m8lt?(kA6Sop3
zj&l+z1%HAQv=di7ffFZ2poyGoi$F}`oNNIxnRAm)$E0v33ZVKVXBRd0rE*f}&3=lL
zP90onoR##-Nar}_(S|C6lXDnqvN(1>#FWi(`VSz7qez09T+SZq?aAZ3R|@yfaMn^6
zYCh-uZ0IiFoLGcF3pvd{Bc`*QNNUzE;?(blzr~!-3!w8HXEmk%&U5~I8Z0H81x3(O
z%83~Pv5Yh1pq8d`jw@w+DmXkkds)eeeG`HgI1x1UU*xcNg7p$7I31vhGg$}XWzKB{
zIIB62i=gxhC&(QFS2@4XFL{k~Z#zP(;dD_(pq6u;a#`0o0;(p~aZ(=xR?i9e0W3E-
zbHAXTpaxFghtPJD^CM;Q8#zDx50;uZl?UO|Z4Unru(WV^RO4vn{1t)F+BhXsU}@)M
z9fOGuPWM?5J30HQ7}LdhcNIAAa2CwRST`qpFF1QRXJSC?<<!v4-N$)?JiN>4n4XE}
zub)#(FU|qZIjW`%as>1m9O9&TgLRm5oeRH5IDJ(29OYcdLG<@HcLLzrea<>}2#j%N
zcEj!i&KYXo8Rz^%h0=$dxwHs)#QDpP%RRx_EP~u5XY)qroZ{5I4KU65CX>Ei=ghUz
zkGF>#69lJRxKp$X-plP_LSi5HKWfF@&pk@r3$EOO9z=0~n@)#a+_)AhF1T|)4g%)E
zP1iu&liPk7;$GYj3n6fj`(ijOd2?SFf|f(v(jP!P%#GQJaDBM@sSxe(<;IVK$B#R{
z2{HL|D{w|*Rsc8rGbjz@zVkiCg1AnUGYsbbo(4xlxUpa1S{&hitAK~0+(*<m5XMdL
zg^6(PdkW}2$_=K(O$67p8=R5c&r=~6#a%@Ok7L|(3}DgR>%W2}#=&iU7BH4OpBnDs
zxZCKQeLVN{0;oygO722FkvnTWh)LW~`l{4PZu2~Zoyz@j4g5XD{e~8Y+1xpaV9Ddg
ztbmp?++3=n<a3`q4^Y6ZqrF2RcgI@*XSsnN!|ft&&U*mG+_iP90MBvnT!+#UZfFg#
zQto@zaIuX0D>V$1bJJ#nSi$w~!}Y4<x-!6dk$WlV;|+LyeoBWxs=3@$_<M!>KMTNB
zu7XMx*SK;oL{`I{-VI_cxBDmPyw3gRAOz~Td#S8l&s|C1e7V6jzYOmixFOUOdXwwB
z15r0}Kc-)@iCfhP>=w71`rewkM}mRf=0+w$XA8I5K`G@{?r)<2ZQMDVAm7e?HXW8a
zxY4vc>g4`G8^$iK_b~|G;RgGFvzt3eyQ4mC%LJ6(<+>(;v!A=;7Qg`aP%>N_<Q||@
z@({OrHh#2W?tLnDjc^}5iI7IQiR(bT$CX^6Z_V82dhsDK#@+KgoO;03e+F!v%cb7?
zhur7Bgv2B6UyDGT;8qNPILU4HgQY3%{DT0~Tp@`&^Li-LvzIq}J^bCrn=-=0eqIE<
zwq1Ec3o&+pC+vX*H{MRlR=e}wc!pk|9=z?}A_`C5Qd)C)@n-Iawu3y;a{%7FJsTi+
zi1!se+J|}SG3fT;&0h+6U*6#v5b)zYL7OXo-kL4Y9l+z#W<QWuO;1A*Z$tyRV4nAS
z2!!zT^f{0tyl3N~GnChh-_<cIj5px}OX0lp^piyLnvTNnC|(7<GLG@~_d#1MFZXYN
zINpDo!4l6qoQ+>QfhSJ^OCm2?4Q)xh;Xdd-$$PUA#8lp@v%pUAy6DA~!Mo%OflS_t
zBwX#&ypAc@%jU(;gCR!_Zyvocb9sY1U?PwAD{TeN@Lv5EY6^J%?_#Ww_gp%#v%E<u
zqA2El-3j?~yr(~g((}Au>Gv(+eM=oLrM#c$*DB|IeiK*)uaUNmmAnrkVD}<#z7*Ic
z-oy7HSH)9w0bF+QDt1C?HSZrP^<CwKje+$VZy}W!Yj}Dpl-Bb8qb8N>yj_&jt>dlu
z8N>!&niv8%d91(TS|e`*?W&r1|0BD%cz^#5(9GLMdyd<@^Jnq<wD4BEi~w7CdYZv|
zcmwkw(93i9R0H<$u1`SCU0(Gd1p9f&9N-S-xjzTjhIj?90vqN9<RZ{f-qs_KALEVf
z!`K7fTeQ6x=b0#b{E#<r7GsZiyK^x%!CRXKM<;o%vtfRUC;ABfPV;V3Z>KY#LHF7o
zew$+nBwY9#`9NLyZS+<;z>oU@L^u9hbep*IohP8pgP%b2n<xJfHA{N&MPsmgkY7nD
zaBsfXNqFzaZ+sKLpU+r|Km)L1gTX*Pw-*9I{QWJ^8O&E#A&3zEBHB6};eYZkHTZ?{
zckY0iNWM55CZhN`UjiKCZ#)OP(fm(o1s21vqy11U|0=C}<M;_JFcHs}XaJ7$k9NRP
zGXFO!l%(+2Q(@>N|34}<r1D)i!u%<IDXmG<_zR-IlFqNa2)PXY>~4B}X7ay$3I?<J
zKhA;f9RBcC4CeB~a$qoz@4psm&hRgP0yX*k*xx`b;Cp$3vydN^2yJKi%Q_%X#NR=c
z{$l<|Z({5m|6}@IRylvyGJp#HTKWiAC4Vk`o%#ZQbS}cZ$p2PP%hyZ%>ohf0@gu0w
z;4=SldOK9}f3JbIT7Ckx2wdmK-T<+V{|&AD>iO-n5$_HD)*&cu;Ilg+cayKL!If>~
zKYbY{n)oNF^wrAWO}nu+enkb8we#PmlN}xWvTA@%{?rZtM;HH8Gh({K|3?nc&9_iJ
zyoaAlh5G^i6(SDunN*t`;vb2JrD6X1uV8nCKRyn(NBPCne|?W{-ww|E{1enTHpbuX
z2ZIm!PIG}h;?K!|PZRuXTE|WD%W2;?#V>dtEYlAD)hcLn78Foca*tq=mQF5$04l)k
z73>m2_dY=?C1Ljq7Et?*hhWQbV4ecc4#;^43cdvAL4glt4!s2nMq%)fz)X|hVZld%
z@YhH1Z9A@ouV7+53<e4Arz7lOK@v?~Ap%EhBD5V5v{1KUsNfZ9#|{(BqIn}+P(*ux
zqk?rTn1~R>Z$cC?f<C(SVg=50>%|EQ=+=uD<WlPGxL|fG#7{sDAVCn>3@wR*4`|v+
z5;Wg|vQvUeIz*o)s6PsS(*@&>VNf#!Ba|M<6huwK(rLlZl%2>DY!E<AwxH1qx^o25
zEEqf^cs&F1`2xcbumZtTwCFDstn7!tS;0d3sAG{}>mevB78KIqx^sdz-vu}?s5_5%
zO9Tok=9dZ{QX;KP5cT_3z>9+4DIal3;C>5gsszu|{c%}Pr-Y?yfh#Q~t_V7*hI>`;
zl>#QN2@J(hS}*vC-hVd)QB*N+5cmf<Z+UE?poE(LZV5i21z58{iK51=c0oo2lywMn
zZvb=(GLFMSmtglt0CxnOENDT&ixwR{f*;Bu-YfW!^2&pPY3lqK5*(r|=CELO&>$>0
zeCewb_XRz)ni~^%(O35$3R-Deek8d2DZqr_E~O|Y1=}e(HzlxaL73Bm9NH2d5Psne
zoo>R)6o|VE_fg*8LwNQt08inQtq}JT-l5aR2ZclQ8t@jLX$I#Z;fZ({IxPIyLAhfe
zVdW^a`3j>crQ;|3F$34fU$~p{y8*(u7^n#nE~j^Cuuw`}#Ua89O5q+6M%f@9DjcAj
zI$StOy~0O@T<SuL5K8BQGfH^xEVLXG*2<tWS~!DJurb0i+RelYFFsFm=5gU?uS53<
zq4h2X6NEkVW=|9jo1ipF80iXPvTzP9&QgSOT6CWjo^pa*s_^&<M3E-6(kd`r82v9m
zhOp&b$Ylz{X?K5GxbZ`PETQBcg2)lJYQT~!bhkk~PxzS&^=O?D?$tqezHkTS3JQd;
ze~;^2C~T~TPiKX*s3=z?{GOI-#lml>r}LaJg<d@8g=-VwT8VHk-La)YHtqMyga!0g
zC>JJDy0k)gnf9)g!UW2+Ul1;A2g^m_<Jn-jBpkrEY8<nwgsW*mb6M!r58c&5CH+p<
zgeR%wR3rRuJ|e6Ye();Bt_yF`Jz6K6OVy=%VHTZ-ZV<j$h_Rc(MZE~LQP@b^wkF{d
z%VF@A@O|3LH487%Qn*F<Hf@nwg>Eas(k6Vl1DK;j$O(eBPT>F_)GlF544k<mJkkx_
z-NM&1FxDe%@<kNA!Vvnp;9Vi}S&a1yD;p8afbbtWT|FrLm1c$^;iiAVG9nDihL%y`
z$(I4{2~9$HabNh_Vi+6~uJD5R1K}Igr2ohvbbS+o6T<r45S$d=p^Gpj{E-Q4TDXwX
zJ<g&=N;T{e`B9gyi|AV_PVE(aMk(NZqBMG^?H8?$!kDXQ4t<*8fGBwh1l&ZcPs43@
z(PbrAJVeJRUFs>?M(<KDk@b7{bWr4I8GxX-NK3h#L!wEl4j&f%Nxz7X=-w9qzM>Qr
z)cA@1+YN{PMcr*M5g@9d>{_7cW+apbi9T8mVzB5X6|{ti-0ng55s|GJAXIeYNpOaV
zhUfrjxM;~Y07pebo{)<WX&lrm5-EyUi)#`kQu@NgG0`%ryG4seeBn%tXbat}v7*)6
z;AosEmNLolqOX4fXM*UvB@j;(ou>C}lIUsbCrlP49fa-_(HE4kI4R0o0M1lV@>axh
zN+dl5Eoq|tw0=t$&3x<!=*|$aegkW!=+H0*PmA_aRXa=c3N_zli{?>LJV(@H!DY)8
zX*;1UPqgG)7(62ix&t-&qTNAff5lXmLPx2JL}xyQ&SFtAHCdb!#ZmX!dC@544@yLz
zC&RT;(K}%vmWkT7Kv}uy)7N3PLiEWr#wta>(PVi+w2|iMi=y@q!E#CT%Sza*7KMBU
za7A?G6S#X-wEStXToe8M96*g|tz#QlYegr|0bCdPQI)h#<kJpI^`e#Az;i>CHxtAL
zQTmIxhBrm4s9w-0N}@)HCQ&WT>bFD^N{}{-wl7C4w?$t^!0i^1jm}xLiWGl9piSgV
z>w<RCo=6ZoL=FFd*eQBpmIJI^qCW}{eUHeV1FTo%K^-oAqQUpUb652J8}OoE^sy(r
z7!=*1Z+#4jJZ8YsuxK?Mrx_8QoJNGBB6~l^?ui<{gqAVUC-)%!Ky>^GcsMSa(GQk~
zqTeWu@JQ5T25~|(u!5$tDG`@yP1B-2$`U(^Wj+8dVk-+i?G^vI3D`dI`!sp&7taU<
zr>nS&DiUtu+a&<*;@fB7uZMVK11^H6_#k!Nc!^!U05~Y#eG1}-#11ML9~M9PF?{k7
zZ+QVkU-6fC**j+WiEC!SlD~Mn5D^B7m6ZGm694x!lm?4A)UXmJuAvQLxVU>0h)2cG
zBtjrUETKGHr1(M!lpYiRbOi>Z#k1R>J4XCGEpTJSZ*|~0#fdX(K#Ui^zYF5W#h=jI
zC_%iQ-nx!NacCjbB#8qbKt5UQG>Iru#HL8dr;0<Lhx{qAYzl&D;sOdZUEI!qK!!M0
zg-entZlP`YY4PRFkjoL5(Y`oW{414Q^TYv^W<4X;y$`v3ad#cCLh*@Bh~=y}h|WS3
zImE*MKrI$$t$@LE;xbAmo)-@mW3W`*PUlF=#Lv)kTP_Zuaz%xB2bE<j#hFWC@PfG9
z0P#!Wf2h->O8k(T>@SNK{tfJk_&J*9u8KV$!xg<ImQssJjaW{(iCVFc`fKXMj+gTQ
z>%}Yjz<NXML7+jrj`nmn#U)gWXcV7ez?oa(`WonN7XM?$*lqD8dZ)ICPtabWRs0h5
zgtdtiW`o!vzD~u5PO;m2P}U{>h>~l);{6*S*C(DF1Iu0UA4+)9FLri3hl@BMezpc-
z4~dHkp>0^ai+Ywu#G8cxqvBs&pyr-9`cGi@#ly538xy}o%j9wKlJ^kkLvilMaP5&e
z`z?S8vCAG1C&i5?Auugow-yGSB>|1_aE~PYD|q1|kyHD|UP(X@-3t38Qi^cDWEYi#
z-6SQ{;^8it9|Rr`$uG39@RV%$6u?VTMBChhlD~$*;w>ql3c(@C-wP1LVTp>0?>>@G
zuEI56Ne`6?{UrTf0REDP72phzbnS<sK*<p8QGz5tj?#Z`1WO`2VK+qbB=rs*kql5v
zYN%w(YcLoldA%A~xa2b@#B@|LXBkXHNY+#NI#RON6=PA7-v2OmO!61KXrm<yF9XC#
z+-ebatmFhOx#A?9<=~8$IK2uB$0b%J1Wri8SIofkmmt}^2JR<HGO5)nN%9sw{>hRb
zY0;e`DWJu}NlDyAM3E}V?t|bdN$5`yNRzlxVK7~?bR9S|BtgF+>@102Fa)wCvvz<p
zN3!EF7(64n)(`P~$teAV1(GVNixf#>FXCD_iY5P2AJsX@&T;r%D%nae%rc3MwiV?P
z6*a$HkZgDsmM%($=wRa|$t7ChR!iPo1MG@KuZH+l2{#K@rdIMF?Pjh^w%UQ!Np}AT
z@dn95cd*=)EPe%`QS#g8U}=`@phER+ha`d$CM}Xt%A&MNc2DB6wMo{`hQW48-6nY2
zAvyFsSUM%DcMw{ar0)XM+>tCk3=g{{MR{Q9m8cSc^+{aT0J|&6qI_7t#7PNd1CnVU
zI5Q;iF+y%wGDs8Kh@@i<bdE|Kp6j9Xp5*s_cynL!y%vLGlBTWD_CUh;0mO01?liDG
zl=$z0Pmd(kHBdSsnWB4rQo=m~rBjk`+QB(3S>uE;XX!7yVSbPF>{n3cB5iC2%YNyu
zBQWSH?WBCx0qLwdSa6fpJI0{fUHY^hR1fLe|AEz0y7mlMy`<@M*4kUTot9;Xq#sfS
z?69<$3rjxIfafsgE8R+uv7dC)VzBs2zo3uO2S|6)10O8)@4#4yw2+oCN2IUcf<U;m
zcP7S;N*DZuSR$kzDYP_>l<o+}V3hO@-6qk}tuukeNFS$!RIGG-AFw#-+HWxyFOA*?
zFOEz7j{!R&J@q*vOppdrdN@(qLNj=hRM`uGOzCBsrB6%O(-W5^O_hO|EfrHwNRHI$
zM}S=EVFev`%9Bn}C&3x%e%d?aOXW`iE0ETPLwBKcHZ?w-m3~N#fJIUjWoC+{S7zfE
zJtvK#+4j72)dF0@66rm6m@k!H6N9Bp>O?Ema_MSXAXG><+=Vlh(*H$3?t*mPFf3e@
z){N5gcS)MW0JTaQUJUum(kH0Ns9L(F7Q`#k-cqn$m3~HTdbQG@sh91#^si_*S|>d)
z24aKMnI@B)(p7YqHA*YXKx~qRQZ4S5^lkc@W3%)-I!e(hZR>|mZPGo|McFRhIs)M6
zkZK-*wNttx8uDGzTXZe%NIB0yX}9#;C4e63Kc6AOUTFnAPJL4E5SYI!UAzvzUBC4E
zConc3b#y?>ptS3EU_;Vnv?U#u?jfBc(jQ!ajY^N?faRX_9qQ1!FCEIj*qB554E4f1
zkoLa}-^QgfDkDFX9;2`KKaxJ7gry1T(!T&ErDm!QO-Tbk1eligQTK|otXvK8Ju+qu
z+;)+@PsxS7vU<8C`(zo^ShHVtjvh5vS^Oo~Js|sL2Z(O6bb7YjWe(0au<Idvy$vQj
zW$oUedddE*1M#3NnbtSnvbHzjsgLX+Wr=-do3&u^lZhXLhyJn|w2=>xwNNoUP$oA)
zcaY5GKIDRBVIBY>vL(9!j>w7*f-_Y1Wfc4kla;>?&T!eFBN>B7WincLM#vhdP8cbB
zpIV2aWS`KR`k1Ud80Mp8Khf7`V`R!GsEL)mKy3~2vg6+H>A38Dn)6S{ez^vg1ldRb
zLM~Bu%nlEeWv8j$og(|D5&|b>FN8uMO}3ZXM$%=AFFIf_L-s5EqM5RP{sDGc_OuxW
zvt$8OBFmOFjzTa;wo(P9xw1SuD3K?-Duuuq*;{gO=F6U@3|N6|@j`GG%3k~e2G7b?
zHp6_8%p(rOV%aOyH+4=HNYCbZS;#R2SR(T%rQ^P(vgbVDRGCanul;hFmUdnhvM2Ju
zS}BXLf%SrH(Q!C)QO2cW=Ox+U3oub7V+O+RWm!D!s;XuFbP(){Z1N5SuFA@&h3=ZH
z{U$hTWEYw+Rx2B(PXN@*mSscr4Oz_=I_}gU^OGX9o3gjcKy8#w(O{Eo4JFcU$@)IQ
z<!+Xhe+=Sn+1Io_X^{=ZAnaDzRwgc2yX@;Z2(3f*2KC2u%1*~YS-<SnB7gyzhU!m)
zGQ9=jL$bCaV8gQhCGc=W_AMREaE!`+A3?nLWY1SX+kKgQBfyxfgyzX{*<u^U9?Aq9
z*nK41R|pdmvfub1PRdl2Cz_H)zX09SvTfAFxks*C3ON_~vugqN$_HpW<tl%<8<q~p
z-=o7?Zt|y^fw{|9F9hb{kay5=4NrMhGko)sm%R(@p!_AeTfF5%^iv#?U!#<_k9^l(
zFz+iLi3f|HeCbU@;V<u^GFX88t<$&&f$|^npe0DoTnQ5)@*@clKO$dB|G^O|=X5|W
zOdd(Ens9j(8!QoW#|r8@iIl%jpGr9<@7oEUX!%P=aPed0Pt;>9UcP4&<d4f&P_ym{
zIfJqjX>wUKETzlugg`Ds{?3c=B2)fCBMhFFuXqw5Oa33ttGV*^R1C<IkI*aUjQr?a
z$mPpFqC#qc{8<MTiwfl;6?C7Kuh<HMMe-u#rDqk(SJC;KbMnmXkT@?dYK7er`Ev^)
zP$tix4}o&|`_F^3LSAwWSfxCa^4J&T{~QNrmAsQG1efKf?_jK2z9JLY6?p;e<gd#4
z)Q5CU{!S~E-)iKCs3cM=AN~=7*X8|`iK~<EcLT9r{&qcBZ^(m^5KM!dNez=X<wdj<
zX_P0n!ow!{a5dy^$^ZQvpjqBPnd{r~yl9NI$a_`-Yn8_whoLt466%&|m%n}o;vMpL
zj!}1Qr(8M{F?Gr1OQ8FXJb@Z0y5+S|FyA9z@)*W?<%N{w>yr;$LNIsbKT}n!U%sdp
z!~yx?Y=A*|52dn(<k{z-WmvAEs_uyVB4tcQ<;lxn{+|5SFtGdbx%5&SlV3;k8QQ(&
zpV3@6F1J5`!H4oD8MHl;7aCz=Lav~bB$M*ILtvSbZ>Md-w0sF=%bXSdIT&+Mv{T+@
zzaoK_@~(<F`k4<XUi=3vZi-(RkaJgDqlB1;V$o9=^HeOO55;;Z9??6>aZvFV-TB^%
zYk$N2LyGfskn^x2<_`?|C}v%P8ehdLR7CVs?4yihsG_+7cEc2&H=#RRQMd(TM-|Se
zK#WlQk_X+9iY43NOqAj}{gTHNCaSqcD?)Aoi&4Dt0pwy8Zd6^3b10V3;~%dWp`O3v
zim~+=JfTSCKq5i0fs)*biq~kBl%&{Bso-SA6<2teqR>;9&`HH8+DK-lDol?<+bKn?
z3<7D2-QR+kuDId{xeUcy^!m+I{6v%HX$5lx;#rE<Xw#6baIE|YXpUld6cV`#J+bB~
z7Vm=YGm7)HoXl4g&=g*v2%=B46e^aP0nRFzKY&=INTg1yV#OS)h@4Y&(f;7PB2EsL
z5=CYJLMm0Xe*w;NMe5_Yz7>k)?|`LJ@yv%XdqJ_qK}YN^D&~^ImlWa+kf>5LErqtr
ziXc0P)ry0+Vd9G7y=?$j6`mh~cujGfj*itRHd1z?PEkpD-g?DeN=w{O6j3g>LGdm1
zG~ZN+!okw0cz6e1G%12sL++O1V+%N&6;2V9O1`aNZh(A?qGB4<R>hN)5N}gl@`Yf#
zB5D@YbST80P}-?b)1IeGaq0ln+)*g@f~8wA{{^_+qu}~NS+BzIHOBfB)@=ZH74DRT
z?N^M^rei=6L`Ta96<?Zx4JnrBDgQF8&{9@%M3G02%&4MEhrxS_WozKYeT8uYz?kBz
zUm^HFF?T7VA6G1=e8xjX_YQzZ3Ny7oPAH5sAU>%m?gf}qyhH80(~A5Cj5#ZpEP!i!
zl`AqJuuu6X9bDV5+=}j#b+g=*3n=^Ru6#8XmOPZ3ABW&U<#S8`Z{>G%3msDGw}9oa
zayxY;`Y3%C!x>-YA3<6fJ{TsXm0yt3?<43ARxaECgCWW$YK}UhOrWAbsM3?B^)O{E
zbxnsW)wFm&s@ymeS|XJ9sUJO3dHWe)QA+MBuy;(EGX-CwmErV?i&0u;0mLc|b08O|
zeEtHwk5_(k4myu3OC59wFi|P{4qhZF?^Dt`S!tpPE>&4fch@PUjTV4u%C9KNm##Ea
z0LxH*vja*qmHS@;@w9T;LO7bGw7m*qwlXgm#2n>b4V2|7hbe=Qr`&ZJI?pK0Yk=h|
zLwNuN$~VGj1y!gFEWqGd<)YgFMaon<ol>maNnboUr`**8-RG4b#=-p(<>wbMR;u)+
z&%%`{2VQ_P<x25#{Ad-*SE!g!sdS_H_<~ZnAH<8wAL&|LQtqG`sY<yn6?U&E#}+}^
zRb`Tl3b@ylVRiU@Ym_fM1NmCzZt9M>t}Le$#W$4wwCQM2N?ro-rZTbsShw;SUwF}@
zY-hlHuQG_r-hIlA^y0d!9LR?Geq~J_bPgzII6xd!cG3QNNV$mv3&YB<7eH=AIlGSj
z=6X~aL^->AN@V~{+*i(^K8i7AVm;h{pmZm{$CY16Aox)E*LvuFq#P<iOcTllH04h!
zPbEXnS+&U(TK1?q(_q&{b?qqR_NsD^g1Apr-~+H<wRZ+oyQ;pjfaQSdHuWJn+*HMz
zpxa%gUIo-c^(OVfd#ct`g33$vYd=^Is!FNo<E@IP`R$M@ow81cRSOow3m=ta5RUq)
z6m+xrsVXJV;;*vOMkYYTz78x<<wcK3kjnpYumr0DsRJQI^*$vvk2q8V0+<L@StU>t
zriusz7Or|ool8em(}y4!p*lk|Vx+2D2&GY~#k8C|rrJq2RJ3XdZE0gv=XnS%R^?95
zPn;@>GI;SS=ezh}j;n5Nhouv$umRXjP`xu7suNX}PeMFN<!GWMd9vyTC1p}nBAO^p
zsyeAxFjX}`Tf|eUo~NKDO?7w<K)UK`E?6>D^_0fXRK-Pu^R%k$M`+7Zbx{Q=TXp$M
zSjtgNl|yx|>dPpAJXO3q?4D8C--DKX)lw2KP`Nt-AyKG0djb+?RkCnUi&Q7SfYM@>
z{2zdGs;oAE^D1xJ#FnU*g(JdJ)zSG-TBf>09f#$r+E{3*P;ncfyHYj16ap7i`_6)R
zQI$)V`;uyk^4is^r^0|;QTbDu=BjGZZ8|V_O?7rQBx+Q>TY=T89{&`<Tvx52KEOKF
zO@G8&ukt$#!5gYIwB%|~&8K?#O_lFy5F1sizJ<0X)q1Kq-BMkpcK8+*a|&avs)ql6
z9jNBf0l{`v6x9SfRNuY~w>wqd>nVfKt@3#d!Sty9*$nw!72g|P^s7FgUF3l3U&`qW
zss{KN8&Pecc9&6A+%jPIRC_FN=DuoaAN(Cteex;B9;p6a0&HCMwi_%xRJruQwMQx?
zEwCq4GpU7iQYBps*QQi%Db&C;t$O!GXmeJp=z{`#)P=N#a8X~TRn}hhJUT0~Pc7Mo
zALf91E2SFU)br?YnY;Q8TCI4gA5tsnLG?}-5WUrs-ywcT{dorD4y%_?0^dh{lzJ?D
z)tk#<$WQ&&6Ttk{b6<lqjsW#De8>l?FVpHQNc|RNorBft_b?cuj&Fg|BkF}+z(UnC
z>APcL>Y0zAJ6yf)Du|Kl06t7ashufnbxd7nK%lYeEV}dK)PKzah*xi%kFn$G%KzZn
z3H4KRfhDMi8-OJ`)R}W3k)#gi!cwyO=6=MKqW*UPgD2HO`pQnKdWr>>Q|bd7VJS`h
zMif}m)h+7)GSme$^=GP6C|`S8y*dd3IqC@7QRk{Z{T=b<sq<*7R;<qd1(BUoZ&(3C
z=hgaTcu}Huv^)oDsd_sVvdYwsdI*-Qopmr+p&tJTf|cr5&x7@X+Dyf&i|WIp7`vpt
zc@UsV-J}M%tgbx(OV#STU%>nob!9FDuBvCB0Jx_9ZyMmbI_*iY)Ty<%pru|Nb`HcF
z>Rt!E9vak<Yv9yP^(zekjq1Otb+$=uqAct!^$dE(TGYKa09w^IXhGDbHoJkdT^&P<
zr4F@$e#%aDF7?oKsiPu6yrZ6%0<2p-{wz5A)b41?nsrxg;~>s{bruyP2Go%sQ5Ans
z9lRW1NG%nBI;^fR!nYB1OAQQ;s<+S{U`+ir<xd`{*HP7STs=*5*+aE2brU~Q*VB_e
zp;qKWd{TY35MWB}vKMxz)lc%k>7r58LvF8zO>_P}&1f$!!U0X1nRYO4nz%V&b=MrO
zf;KOWW(uAj)Lf-U&0BL;0?bFV(gT>UW)|hZ{4_nq@F`HEdKP0rn&NMvJ6Pi#4)IXU
ztJESKrum3ovEiC!)Y}oGNmoH2Ruj<+EKV~<pPY-=T>F>)1mU=5Ivoz5&}<xmwggQD
zZQ2txf%9Q7NuwwRF<CQCwS^Ro`5Tx&soC}xSW-3B>%ekKQ%ubgX_`|*FrTjZ@gmG;
zXaXqBoT;f=2f5RlG}@hHY5w>OK4oj#&cS?+=3o%U9J!imIVAEl-|M0DjArEuVELMa
zw;@rWd6rHM6>8QHIIFowg@Yo^o@4O$oTl+Ou=ASUNeGl^zMls#N;Usm2%pL{0-7z$
zHQrSEt<XIE5aN}Zk5Dm~bwRV;9YI{wJRJ?rOAgIzl!U6%JiY?HUDm|E2WquOa{#)p
zXt+GcU)3a8AaPAIms)sgG`@RbzE1Pq4G`-!Gbkf=L$ijG^o^R+-@`<cCbJcsw={oh
zL2S_&X%XG3QBrSWn`X^5VC|ZSPl0u49Bu(n)2X>csrPP;;Y)xX%?Rztdo|}NS<tU}
zgAQ8_X!K$T4r)#sFgBz)Lmf!NnsHQwXN_o<$AEZW(?fgFF-_PCfCrkTxd4we0$RmR
zXk_n!b5avI6aG4DEfmroZJUFd>s_>^<%ns&_NV7Sb=A(@1l<R;8>sN@ruC)FlDqb`
z6JYVsK23QwAMMKzG3Kjvx56hs?cFP2@z<79t6_k)%?x6o_E%c>25Aqj#Pto<W>fEJ
zh<4}!IFD%6BoL}?dC389!n8M&fQD<;?r`R)w(KhiMrb!I$5^D6D}Xam+HN0!W7@J3
z=#JK|qTfD7n?#%6SnWLOe~Qx%(B~xMwR4*=c3gY(A1FJa{g1M*3EFG^@FGzwp)^R6
z_VuUXXtH+wv(&(wqJ5bjr<2<3m!UgVJL>~n%TwC5bT%|iJI98xbZu@huneu1?#@i@
z@Jn#!wAQr=SeEwMd1%Ylei8snIog%U@FG_`6bAEo+Rl6s&uC{}g?PSJKq=V*?R+};
zRj7@7k}?QqwXIc9Q>1m~fLg3oQfTM2i>bzbUOQj`R-#pSz_n8CTVBA*w8>#GSguW{
zl4ymtupGon?enyFxS+jG)z*vJ&%)sLCG87TMz7MgP=@rfcA9#us<o^jVAr${o8gS3
zM$4iENUgTE2x{uJa{@uVp^f+zph4T#3BQ}P6;%1YrH$VM!Dj6jDiB+>%7xI@roCx}
z-FB^kKF!&sb-InQJK8)6yy(_``aN{^Xv+h^(yLuh^KzfojUMg0+N8I^((ll&p^Vyq
zwu%bxgW4C9p=L;%`5NLK*1oj_f}`4wVVJ+CouUcjzP6DGyJOnFH$(n`b`x!$$F+&8
zAn;H-gQ^0LwA+?pY(gt%f;g!y+y(I|ZJ0j{O>0G~5w5fDD;$oVwMXY@9tG7!x0>Dy
zdv)wmfPK32*cr^)ulv^*W3IXnsYmgE?m4=x-E;%gpX#o2mBJYh-ChxNd+Mx}AbRPz
zGMGQ8dyS41c<Z{PaP5$8M;zo1>po+F(?_>C7DQj&&-9%MKivYyDzN(NB(H-SpnIni
zSfK6()oFrsNmTO+);)g;&V=ZKp9RYiUEDkHFjV(PKFo*d@)BS-T<55Tqepdy8E`a0
zx4Z(Jkva_(u%mPv+%R@bSGgTJqjfu|gD*yxN2l&$b^brm_9#x5SO^fW^CsVp>wch#
z>V)nReWoTsH<MobiMkS+Fp_ka^Z?1aS1&_%iq4lNij%qnkApK+w}rZ&Pw7_6A&{oi
z{tjj7x;alnb%t&k<?%Ch)komWX<glXuw>~zYM~55wr*Vo<a2ZZKSOt}E{>Y)^K=DC
zAfC~=ybUa0cmEj}EYJ<Ch5Lm%CM{~u>Tb}%h$5Yf50n<`zNb~}Io*??kUOtiKyzn_
z&hJTJrMi3r%$MnQQVzLX*G+916}lHcpbm~o-38hxU(hY2wEjh14$VcEbmR0otI`Dq
zL-%E!c^NES)ulv&cumLo1Xzu3f>Oe@x{5)FU)N<&TYR1Fja4vMuM^SKe?xcqc_?ep
zx&4B%o4T$;u-mAc6NTuTbV+Prj$69Y`H*PVy`2jeZ|gR45k-q`2d(Z}bvs^!nl_z_
z6!Pu5k`Rn_=o0Al+o`LjPO&bXryAHD-3$Lgpj$VK*3vz?Wk141ug<gwa(%k9aj<k(
z_u2Pg>DRga43+^Mhngw}9lB>J<v*kg;DS1=o7ah8Ms&Z^3wKoa15J1LbUm~qzpq>E
z2bMA2gXb~!K=(QAD8_a3TOj^WSNktGAL%5t!k*9#Q$2Z7SHBBabV^sw#MrdXi8_9r
z^;2RH_vkg-5ZOMxW5gYU`}Jq&%LT6b>vsVT=mXvd(M?}T2Ho}7B@pz`Z~qhyd+O&<
zI>bx=#4!*L>J#Z{_SQdI2W^M+>OK$;>tCWIu8+Qo?sZ>%jT9dG>76JS<gXw86PGza
z-+dV&1?r!7kf%ZV=Q!XA*8lY$VhYhaeFGCm^q)Qk)=>RLdhLhl`P9`FuHW!G1dr<L
z%@Byte{d2eBJ~}cFczifQLol9y*G(R>jhuKwHSQ>)m~%uOW(v;oW5iPKViJS=oYjb
z*YEz8p1%`%eFIn%^sXD>OrrkY-xy5NzZ3<*Wc_-YN>lW|)1K#~KKmy)ld4~k1(tNZ
zE+66<`UjM4&eT8C1?;q5OKxZBH`2kgZ2h)V(2}FyJr4r8`a3TG%hSg>L)jU9^e@!G
zk*~ix6KH|{C~cOC^lQEXPqBXc1i(3c+T$=-s(0#zi86h67Ff#lh9L-C(95S`@S@(0
za($Qd=crs$t^eMNu`Bv^YVf(L7rX(`pcha__D%gon%x`qi*uo@NxvUwMI5tk=~q$a
zqgg*nMUC5fIUVR|(O;uiN2@+v2l+PrigvKH>;IwYu0#JbH6C~Bl?H$=ebPCw+|m2c
zDaUSo6eSRQ^y)H<_3FK-PpD7--ED~9)!(E#Nxy#SeFzNb8Ta9~V^F_|?!Y1aQtIOx
z)}Nss*b)7jH=$-!|M^w0-qXKy2gLjOrCO*N(=VbW?jwB&&GHlaMde_b)ITAIzf*b-
zYCf3OKgxlCv*CNH{_iooSc)+hLv{#!ay7)z>*#<X{X@vPISe(v;BhzT>j69rc{I^@
z8d9Esc`ri>?f4EFbX!0?WO#8Mz+pq`JrI2il|}e{eGRixp~lY;&;Wz}1{o#t0t|;E
zU@6d`Dg{fBVe}oS4mOCl030#=Lz7>q;p<cggc%%M+Af3}YA?X4qlSZRxI&SJ96Aag
zWtgOr^)bVjw8e}uJbwzI#Tta&0C9#;dbu4p{7Kuu6Nc~Iab*$=`zTMGXjmEofh2>m
zAJ|EQ-`l`a4eo=`dCIVgrpYves|v()L*QmLcrpwt=~>A%oK1z&(}t-&ux1%<j{wUx
zICmhzJVS9OIL{bT7lAY1p!^=7z_8&Yh=m5vpx6IIE_dCpaOS+>bPwDvF|1=_tkm#4
zz1hnQX<uWk+|WU79Tf&QDwS0lPLsbE412#o@Kp#G*kwa{HUz2->z9Fe#c<FJ?5d$e
z1MzDH8|CwA3@ZvitTn_LAaLE#_bGg-GhA@ca<Ja;#&2M~VaPgz!JCHU#}GuL;j8lq
zqR9~S55O(MI;wg$8)lpW%WXpeJ-01}cO@8WHN4vb@7oM1UhuHp;6Z1mIt(czAa)vJ
z3c%83_%Z=<cMPw;1JG?S{0m}_;lNQ^OZOU9Q9DVWA><ea?;1AG2i9-c=?|X<3~D-I
zFl>1JCcucHK?#9T!>SONA2S3z3Gl%1Y$JjgH?ZFYcxagCii_~bAg4QM!mw8bxoJZy
zy=t6|qwB%4$B4`uR!+vMEwq;2XH1Dfy!(x@l>c-!vLA!_14c6kn47VT_QLMQhuu))
zVSN5isPQ!3`u~F<Mg=Vc4;nvx4oVLj_fQ(r$M^-cM*AA)vjO~!5fkvj-}o8TWdn>$
z{|7CB#$Tu;8Dt#8-Q}1SZ2W^($RWlKnl_FYU#1B;)R<4H=rH5&O>idM*ycyKx-m%z
z`3U0+)40x&#@+KE5M>nJh23MujZ{8}Hh%dzK)kVl+E9)gGrJ*o!g!hrqY1{>C`*=T
z^uGx4B;#L{%yA?eU#<i-#dww~$R~~bAb?b3QwDfW8D;c=hcx3~?a-EP3^)XX8OE*D
zXOL<9buPeZV?zd5vW(&n5k$5TsX|QM#<CU&<Qm=f!9<?1V;08F7(EW-a^)LYw1y}!
zGLJ&8&|%De3Gl3OT^<Y;86QazeX)^04}qRDvKN7P-nfJ6GbKh%1=N%pcTpQknQ=!v
z)RY^yeh7mV#>}}0w9;7K2ynr8Q3TG5#)X~Wyky)=d7CPu#TUvh8|_rSt2SoP40^@r
zXs6lZs`0sTuwFAZ(iB`{jHj8U)_7<soVjkCRfRz7jIJfX>WxX1h`(Xn{SB}N<2&T&
zP2&=JR2q$yv~F!OenE-2TgEHxP}XeR=>`k8jV+YVYcak;ok*?5-)4ZN&8TzqfZA#N
zJP?9i#(+f_ykqqE5yWoe>oN%T7z5tGSg*1D0wns3Kfi@|?;0Icx9B&nY(Ss`#u-1t
z(x5T<55zQN?4*Nd!$v=9>KZZ5eh<V^qvvbD#*F$`!1=%!M~%zl#``r?oqlM%Pusvp
zMip&~CXAbDmYy`u3WPIL#-<O!I&GZ05I#AZdg*80W7<J!6c<xS8d&z4u6qO9XZkZ2
zatBOxt3Y%!J&b{XyQy~wn1|_}A1rv9{uY46%Ov5!&_NS(4&`#aO&h7{?~rNnOHgyz
zlp}*rKBn8${q1Y|k8WK*)81F0#@|%j1eO3(E9LqEO=~C*7-UK{f-~6kY(2(8OsC(0
zz!6gr^@xO;V&=kNnCWp!HHMphT8^uB)D*V>%A!o=$usc$9WyQX5`xjDsyWaWV`{Ai
zPppYIi0c(++8u)E<4srT+`@5F2R(l$Os8K5OM)pi4Z0Ied^(?$WO{-&BFQEN)g4ky
zFMN%7Q%#<<4?1NUj{uft+VB?~O*hT9fS6&rOxM?uY2xq0;AzvY8vt1*CmWPzn|98I
znjDj$5<cacOl%m;H&xTlxWF{;I*5g)4-Ww=HXT<2oHHGwtkro_tR8`um>%`PM5!r<
z7WQSPE!h|=HwnW4Donc-xImSrpfVV`;4sZK0$wz|un2>fOp@i$R%Pm>oBXngLH9+q
zsVM~#S4^Q^aQLce0SD%<nZ!Rpca3Q_^?}ryQeMN@brX+Tv+GRVw5F{$b-w|Y8>U7o
zKsT65XkUKQ^zs(O(r9A84Ao60#|Emr-7-~fgTu|Hp8sI?w&?^lXSJ9rC=1kTy44PY
zZKiAV5^pyx@dW5Fv0R|L%k-KEa(7Hwp76fg6i;uL9#b&AOnXg#7{StKN~DthUDMbV
z5c^HeGAJ7`NoW^1Xc~3A48b9j&l_-f*d)COo)OdAB7jlTW&-z2&3bro-}FDKIgOdd
zC`tdo^z~ziY24&t0eEQQQ_s^QQ~Z5cnlJ^ML7X&YQrTq6<WdLK)20at9CbE-5Cq~L
z^9-tOyO@uL(fe<&`JG$Pz0dq{HFWPc*Wbg1ay5Uw0xljf4>7^wW**6fQg`zQ(ZD>+
z4;F&O)BGDP9KFnWbgc5A*@;pX-sV3G!E(s_72QvV&G$b6@G-wni+5jhDHrDb%&$|a
z&EH&=^faEo0CQjf0u40h?Ey8&tj>T$u(_)ax<ky*P)orPvz!vdq2{Jo1QTXXqqkwW
zIfjyTN6kDcWJQ>V_JcFhTtm}UlzFxXygz2%90JwR=92=j#F)4528cED=qyE?x#bRh
zYbxH%hy{Aw-1$3{o-psCGJ1lUNxxyDc^$10lgwWZfhF1e)DKXaVt(KRaMHYB653MD
z33M{{l({Mj*D%d|j_RxF=C`NdMTXf*9SK?HW%Mr3Hm{z5>KyaU6HuLNZq0&#BhSnm
zgv1$h;Oht`-+Y8Fet}s|&1i+@5Zb|<HLneYwjy)YJ~&fsZu}D1Idc%Ty`492qjhVE
z`8(<sDmCAUfOwfXgFcv0ZeHLHtis&79decC6V%;w!7TX#K3z0F6#;O`VZK}jyH(~(
zl(xNWW>ZnV+B|zX2CtZ9^mAP`zgGc+*UY&GF;-*#qzlAa^EESw*UihRW2?^m(p4C&
zH!sM**bVb3dTtxccj6G}P4oNHAU2vmqOR{I^8}?xZkdm_05qE&1|?j)ZT`3xgDvJ)
zdGNH=+#U#@+RWoDC~Y^-b_UjAZlPUSr<qB6fG+b>hcR}?yy^d6RpuY!!O~-H&IU`b
z`KAlB^qG6l0K01*41%S8^B+Iq;t!a^YvJ#pc_%FihRkm`=q?*JyDS7cVlGbsHfml!
z0&VxqOgboW-~7{Es2MZADnLvR%okn;%eeW^8km1*e*7++d1PMR4}l5u1<KG)nms;+
zi7E3lG+j-bYwF>Qv!yZtUhJ`SF`>-Gvc`e2y_RQu9bnyO`GJ<P2P|3Cx8`Qq@d1Fl
z#jb(F9+sfP@WRvb9v2>ZS<+qv@sP#S5AugChiSI-v8d@7kG~~#JA4YT*j7Vlpk-qn
zh(VSXGeEE<xCq1$%TL<?j#$cHK`fz`t)I}h-oh-!)FvNpS@IC9M=joa!4qNmhR%Z?
zv!o`#M6{*C3oJ1fUMWn(T0Tes7H9c53(mw_7O=sRV0rgl2qapP--nhY%hz9G?4;#5
zU71wNj!s~wERBCbb%tg05X3VrzkEO+|2%E^Hw`>lmP$WdsBB9LWp;BcWe>oUYq3zO
zKhF|Ry;f%|?@|II-*PPyY6>i3I;>J?siyK$vE@ffSDmx?Uc$vYZwY%70%ewGwgZ$~
zT<ZZUEKQW=x?rit9(vYAOQ{#kIxbnZ-hq6T#hFfUUbb}7j<4GC9Zfq|EMM#gcGWUa
z0_>XQxD}VJ#v)gMSZi5MnVLGw%-`|b)m!2}0Lu-_7`@yYEYVK`yJ>lmT1FZz=f)w|
zWXb;$*e%QU-yqOzIsF9!yzQ_UDc#j(ao-H{?Up+=h_J)*?+LirX<0*eV3(zgnh@?-
zToqvHu{=%%hhEEKy4U+G2^$g9UCX`aV6flfPF+p|mW*JyHfS+<<B|+n=7s_rwme6-
z)re((1DqMPI3l6tp2bnJ3q1ENrIZsIvplvG*aJ&nCbT`Y%oM}5N0unsQA}78F<s7@
zwA={-amr$Q8LmxR&g_JMv(;%OwC%AzLpc%`YZ@I=+iPv5Yq-z)J@x19w=SpZzpHiA
zy8s8QDYSQRvragY5R<3Xb_M3WtOFmz#e>%O{y!yU^`cd!k5zsYc73h0QX%MPeU^G^
z{H;Gyp)$bAZ~_)=RXhQf5Uauh?1(j(k`$rV)(3Dc%=$($#=@-w)aH8B`qn<ML|F4J
zFdJ#jNTY7BDC@&ji0PPh_5T-2tWR!$Z!y-mrw~l6bygze<E(Gafwp+7`WVKJTaVFS
ze4ntYXxp1)eVuCD$yQ?~u5*f&@i)LpYbzbuOtr>Pi}We$mLY%)YoZG-Nv73O1}&$p
zE)n$n<ye;`!{J=(M?-KX&#GGtgJ-M{DM_Di{ZkAR1=gVdL203tvkLNOt*fZOQe^!f
z{n<sawJri<=d4plfStGArW|95wT3EgrB(sW`DNDKLoirwo&Pc{R9F>}5U;eZme9fC
z3)VxFUbtvoMaOwAStF_2ugdy8I=^OJwobkaZPnIqdlCH=YZmQ?u3Aqv0=s5CNPF7r
z*44BYud_zq!v(Il_EEa`hIJl&4XeSLd<dL3t$u+Bu+jSIrx0keK7AYDmi57(Q08d1
zc7F%oZd*UQ0&0u(-`$|LT3@>b!8R+OioWgEpXmr@hqaX^lTPa^--5HtTGIgRj`ig#
zVBJ=a>j<L9dT~C&?zKL54`KIN@o_dh9M)NsMC!Nh$N}eoHIHt@L92zTM8gj2kI!Ln
z#CoO?tfN-#Z%}j3`u7=t`_>t>HypF-#}Ly4>(Z|wF>aO8Gxo^(9U2v8O;}@T9XM&7
zHwT<k*4lSre%kuiv#{iBOa2bTJ+?pIhTLA;D>Rqvv%Oc0vHi9tPk7;KbNmqmc)->|
z1s)F@Clr{ct?6&Ddf5VK$#>A^Or7xFwg&o4(;?f%Nf<nA>m0_Ik1cpB#(Ztlln?i_
z&2$0L-{$l-Oa$0UGodrkc5^8r3$mS}RDG~5m5zdh*wS8w+!343aSel^w)vFQ39}7U
z!_#nE$~X8$j@r5l0U~TK(y^FGTfYZ<in6sSp!Arn^c~1Y+Zrh25@YM!3@x#?Ep&n<
z&h|qdw8YyKIRM9P?z13w!uF98t|i!*#Q@2+7d`?p#kSIw_J1dBUe5qcwYg*3oOQ}3
ze+@iowtVU>%e3+7);(?8_W$`U+tqxGW!vUcWi-cTrH;T{o75BL^K4gW<#xvQ_zxiF
z+eA%JR$z<R4^U`pQG<BaHg*bf#kK|h0OxF9&!dlDpSOK=2A-DK9;5z<QrmnFu$I}D
zCIgh)LOz4}3fphAIlEx%r(V2^w)I8eykxse)uJlf4h6(7+oHN5P;J{rv0SlTJ_q7e
zThu#Xxn_HhN(42wwE|$Zw%fr7;<~NqF8!Nvoz0yp2KBaAFXLL?u=Q=hPtjoe>?z3K
zw7u~Uutr;JDU>$Z^65FcWh))T#c#HqpG3U3ZFh1Y*J5+0mbg}17#-zkvxQLKXQwTf
zCh{(uCmpN4V{@#AvL4$;YOCtCp$ikwU!U!?4d(CKYH8QdZ|kLBZNRph4TFQW)&}Sv
zvPES;>9Ec72e6FTs=kK&sBJF;^7m{TodNFKCLcp+4{YlvAuw+Hir&HxZKr30^O4P)
zmNyeN!A6Kr*=9FF*|hD?@8Per!)~Bu@E*G-55BqB7e|A2pWV9)^84-2(Ms9XUQc`J
z1NQM3Vad(@IPG`c?G^Mv0T25OS`&NPU!>c^%bpYl?4bQA+Vp$d8)-^9WdC?Qz+rno
z6+eCKuJpkA+8N)0#n0|gQMTIO?ju9I0ru0u0D<<OX$^A3zOWS_)XoV42(yRK{2Fdo
z9|Fr!d;8CjkFd*2As%VBZidn*drSnzj@duf!C<ughcbi|YrjqRMV#H}49<9aMmfAV
zZXehR&J%Wj2W^cL>~|<5ooM%}LWD_n%X`q4Y&Sjw`4szkI{TbzpFuf?Q}&iPfHeE>
zZ{j+q+uJ?|XNG;zMrg~l-=%)u)AlSI#<J|TEMVF8P1GHgW9PpQ)w%YW)V!K+S8W7K
zfj#artv?IxbErf0tbK^~Cq?#Ndf<!g2WkI!&i=$M$e*_#{}<7h*wbkNS!$opgxxax
zK04`FZtq<OtinEMgzifF>YWg{V3%O>opsS3M@y$m_L4SWRdxk+RbI9S(gLB{ex#f7
zFIVhkw9C0_*VRG(n!U#e)*Ac3uh3m<-?b0mx_xFVOw`#=t_G;LC(=}U!~S$5um=0K
zHE{H%eLHntHQN98IJ7j`Pt%=y+rHZcV=eYZ7iej<*V6vH&HhI>E_%D&@rb_l-C=*4
zvMQbSMf-7`yX=QHf%T64d^Y5}?H8z_qQ@?vMR>3M1G+u>?9JZ++_nEqxt)G{aTCCR
z{SdVo4ca->VLD|0b2h-R{W8^FN9@g%`Wv--#6a$z{Z<=v-nZYH4||R=`@a;-1G}1b
zjN^8#80H_^6FZ>vk^K$YyG+=vRbZL4o2h;<W#1PM;<P<xHgr2Xh0;5HkCR{#1YDfD
zK7^LNPVQU~_c?t_XPNdpjZqcf)#)ykjNP3!Qr*tOX%W4ZJRMGK5vX2HI_hLP=u}1b
zthdvLGhpzLQ}H82aoDLgAMX1&1=AbT*QqNAn4i<u$1&#b^wTvE1Dt%QNEYaHkY2w*
zPG7CW<qCFs<9854oZ6fLjyOI3E)0b_4Qud=ggMFW0O3v!(NCZrb@ICeG{UK#3Sp5>
zD`_<v<updQsAEoROMpc?<x%!H#>wphT#I!&`ZTaOr^Vz&ywlyE0FFDYr#btC(-bW}
zlAYXbz*3yP{0~}AI{iial2oU{e_-g8)03Ye&NQc+4r($<cY1O$V#;uex(D5vPMT(5
zSxz(lf{ARWPg^0F<1~i_6S+=*(i4~Gl-CE{XPolCfOx*s#3~ppa9TqK3!QdT5%R3l
zOe+M6oK9?lc(Ie@09ejBjW_-uOWy$&<?;OQ``#UJ$HBq9<r-i#CNV~nm}nA>i5e4Q
zOrkNy5_{|=P32S)&C#SISm}abL8MtI(os-~3W!n!1O!x2R0Ksq<o}uP|MxsR47)q?
znc02Y?#%3hwgShnAJBH$ab6W|VJUK~`U%z)J0{MC-YbsB=~=nzIGv`d*BqVb?yhj$
zR0vJi9e2~AT$PSnJONYX*h9G!)sE&p;H+`9Jq%Lom|FvK%hBcrFzX!eQ+7wAWBEr=
z*yK2BIl!77KgtHV<LL1|J%25Zfg4b4bu6=krEQLp??Ujd<Fb2Dc+YXeE|B|<_b5i*
z?zn<ts2z?S?}6okV}2$^_MziYIv}vqaRd$JBgbpB59hJt`;&qB#Bo1u_UdwMr|<Ps
z$A0qscRTishN2$F(AgA!c;>j>7lO|n!^r*9>u7ZynqD|=A%!m;3uL(VeU8PkApMTT
zV^I0Zv5%gy0mu2JsC?~sVJ2)EbWEO!lC#l15PDsV|0SX1Y8;^jaWgtlmXf=1#Yu>J
z8oh&{&&xPz0pv{H#)4(&g^w|fq9DG;?H|KLKVvKl;&1$l#$u2047q3mjKB2*Ezo$M
zyv}=#+h#&;pK&z>d-oe((MR!s@c}u54jS`l)^W(_@+;bcjF)KH8f;9bS$~M}JgqlF
zjYp566lO9m*$SR;<D1{&ibfdAbJ2L%c$h+Uk;YC+2#zvNyaSda#>XXqi8k)ahl&`Z
zVE_t`8hcf!JZAitBG<=_b8es$CycGbARcE7SPm;r8Sm509dEp12Dt>|JXe$wjlVs|
zSR@%uYjRL~+9(>K{*1BT0WfEcp=H26XME!ncv6hBuRuk*(ZUMkywNxV#$>=I2xJ;n
z97<V6ZaF}+jWP=9<QVfQ%A0GP&<E%|W2g%%3yj_W^HUjzk$d}+(eoO>E*q0f!Qd$}
zrq@8C*cjstv=U=wB6v!T?;Bvu730-&=*3mzf0WTsW}Gk^q}(`@<SL9C7s1f$#_!Ld
zveNhl-B&k_pUY5LWz^Ke`fB5@e*jiv{F?5BTBDCYO1F$z-5C5j<BARBhiNe0q{Yr{
z<AZ0=)M%XHfKrpuZVX7X@xcUWx?>zoLE9Fiu>v-=88=5k(_Q0NW+3;Bmzz*|-&pk#
zI?-<2!=Th*TuJlg2gX?iQ25g5M}s$D+;J8xgT}rMAg<e_Z_xa6_qN?#knq|zbOlWG
z-DXGc?mgQQDTgm=+tAw>l2h9}C_t0E?H)O(&TVtQ43_k5`=`OC%xzx3LsQPSukz8S
z{B4cY(ZX%1J5gD>?UX-I>bA{Tg|_x>?f>&HZwsfqivDf4u2L?!+x924DD~Vv>?|w|
z*sd;xrjYG3i$RWTm&zf3a(nPGlumDVGl%-j?fFum6>P6JKz-46^#rh#Z*QZmayPf@
zH-RN!$1i%Q2-~qU6ay5qBYO&<Pw$vRyUS8{B;Ln}=InU;H=vk`c09R`#_}BxXhm^r
zN0tkCT6b)qoR9lEKGVXqt{oG|;re37@lPT6YR3j^7~|?R@g_Rz<CO1*N`I#dRT$uX
zPB}FIJ?Qj>oYXrB<PtvW^b4)SVx10ILs7g_*duTzIV~Z%GbX2YFR-RK&8GKFs#Ebj
zNTfN97SWjQq&o}2Y$r2X=I1!=e+ZlMoIdD+e7;keAKETB9o-9Z(P`s)bhN-}m>Wzh
zblU9za>?nF`!qmKJ+wwEb~@e-xl*TScL-c@a{U&SSDj21+hEi+CofvSl{roJMn@~0
z{Q6<Vb*I92(N^j7&LNa;IGNVN!YZc;5>!?@4V(jKjni*~DAhXI-b1(VI8CYqXq%G>
z4uK&u{9I%X(<Hx=`Qj+dyUA=k0fVZUrORPLE#vM%dwJ>@&1gt9FrooGjm%6DrDo=`
z9{6p{DEcNmV)W_gP%jfn-vnoNA|)Akvo9!rX&)PNlA_u85hqec(VOe(n2iyOwnNoh
zUFXrQw^!#t`W+iu*-zL{Yqg1S<Iwtf#01*QG-<`3(DB6|9%%luhQgYYFU-YIP5Evn
z;HC<|mVGsf(ix|1c?jXJ(<$}zo0z45o<4`-C*Rin2H6?Ewt(k5R*Tk|9`t(pKClFT
z|G)%eaDJTl6g9K9mE!N&%`{*B>D8O$|DSV#Rsui!($LLS=Y#2&TjY<K*D(s9^AnZ>
zbV1}$v@T4g_rtHLGSn<O^CSLVTtJS{B~ABX*3!?Es9(01vh|iv^g_)FZ9dejoEwAs
zRo(Fztks2j@UPjj2d!&eD1*qfZskxE)^GEJf}O)Dmt!{*--8wpMoocrPbP$JNiW8Y
zGFQEsj$G*VVWe?@_GO|zKzIC@t^F7af5s~bEPI(5QIKn5_E8$`W9GeisC>eN)9bU3
zc@wvWte^RT=4rcGr?K?@^I%7gg9=af_d*P&7hAjqD!kcWx5HK+_I4j&eA!NN*!i&<
zN;&msr&mE?IJ=OdW)ZCVEXWD=S9%Y{vX{m|(@Az2eFWmztG@v36x&4G8{*mVYRDz9
z+mivE$o6GOlz0@`*nQwhX4eF{gfhcTh5tce8arhtVA9#UlsuUt@gi?ns$>|Y$D~P=
z<g`qeRP{mOc}e_ZRAxvLkeV;clmyW_DNABaftzf}M9MYIk-Sca^|_MIb^s+$GMk(M
z`4R=~Ai5y&84i?-lIjHzD3FXb(K4}6^42~Wd`Yrt40tX}suO@+B>BS;rDBQZGoY17
z)>4j7sbu6dkSmg{ZvgbF#I^)1*Cd*+p{Y#rnqpz)k`kI~R7j>Rgr@5f&o>}YDN)mF
z@P=eH#f@%CJS(8KN+SD(c2`tOB3FRaNIoUjT8Wgxu(u?=Qz20&iSPz%y~IQ-?gq)T
zSx|9XvV*(_jgl#}bE8S3qAb8>Ngmy3cO=P~P|+fJWew6Q`KA#lZIbP@M!qYVa|@+=
zlATu2cVFVQgtFV(C3X`4+94_PgZu+Y6@9KAN{(#+Xs0B31_U2T<a8j?V@V4w51&Y8
z?gVF-<b(Gy2u~$%Qz~+|<Q9c?dn8Nu!ro_+_j@4sToN)0ZM~9rPeJbsi4|>xcq!Tc
z3i|pai;xwrmi0>}yoFvkOUu`SxJYjVoeoE)(g^wxpOa=jfJBNkmmGwtQtMt+rb$nq
zfr@nLGJ5#Rq^b18l}l6Vp{YW8{t7s+OCu{l>ZOU4Q_&!OPTs~g>9!z{yVCOp2((Kl
zQQAg_)cZZidCJPkrQjudNO5&<S)IuiUGtOuOdn}~+1G)n-6JdC31b3euRlgdBXOob
zB+konXi1YHQ&9RvrffGojaf4B8pN|@2FmQnk&Rjk6}hs}bX(@hDk;}3UpAKPy(qI9
z3kwTmXFX6^D4RoH{7d+6WVCR<EbDAUW05R~{_$Tij(&&U5}6%&-*20Zr9&zj%}&e$
zX)^nVBA?A>m17`($INyVN-bt}b|9^0*7qRLX7=AFbYaZq48X$YW_K*mHfUD33z*L4
z@?4;}m?zZ23Rm-Q_t8qh*W8u*<Y(@@AGQAGKYa*e_LyIwNm!tH(8n0dz2=?_$UgI5
zE`b~{Pp5z5chEeVzOIMNCy?tW$lNmlr7-i8Mv!pxOXM4iFn>kfw;1!8<mozRKAl#1
zDdxwwfux#yBm2-KOEZ6#MFVX9h>|Wd&9}`!W0v^|N*&EM=cdB$9P_%xFecahupLU5
z&6m>5s>r;S?)+kNeh&mn%(s7z%2IRdM?kr1K7SX)ubI!Bh2B@2kJiBK8uOoMmRf86
z-F4V>%Y0lOE{v((JZ~oC8_XxrEcdp#`BK0%nj1oa-E3Y*Yp^@!E0a*!YCe=wk=x8)
zlf&$u`O0$;xNk0{{Miok4{84X(A@AHI6KXE(KO<b`9}`0!qviQ6|4`o*whEP5Q{yv
zs0_7uCj{!lOcuMY0yNwrjt+!~u#iUs=CDP^w`h#C_@NW5Q5Ld)!4hNfPc^WQT6l`+
z;W3L7bb#7%iwEQ{h_zU_1LUN|ruTsoXR-YeN~bKW=72NaV(J{Aq*%QE1XiS4h_n?T
z-QwFk7<1m@+c|jv&9L}|HkD*rtRq)(wnYSePjf83i$hzkMHnsL^DHukVVv?Ut~#Oe
zqQx@`tQA;%L=&Dui@ia9QFxdiPXXu^i$Y5MylU}1xoodlJlTX&yTv5hH_~CTh8Bwt
zEjC1<pPd$L4vmvVbS21Ri&gZA>ar-Hhw7<?cO^J`ET+(l>6wKad4677cxS-CL5n)_
zL^{hul;Cuc7w5nvSNR(zayq)n^F_e8%g?yL?A`JldXsv{x4uG~r`-4p1ij=8rSS#I
zTh@bRue|9Qu=mTYS|N8peqb5MA$hGE<bvb|N?1>l-=pPDvU~%5#m>k*D4=#$K7|sF
z&dJYtqm&|_*Gp*^sq)Xq!r(OdoS#rimp^a9P@b3P7lAcHKD-C=nezAPvz;Y>T?mpb
zzts)%bL39s@y(SV+6?hLxrY=A^X1>tZ2W>eFq;Nlet}ki1@bKv1uB%UoCN4g^4}xS
zc3Ix@ze7NZ<crCPS1kW(Jy=WRW9il_m4EjW$QAi>itb;Nr;>-QOzt4XAe76qPr=X%
zdG<6Ib6vj82+m6RQC}EyL;jZ?IB&{F)S<FU{wC$x)X3jj3eH;jbXwcqk{41QK%G1j
zIT0pVy?jzI3~rF8z6JHS<tOICwnljpd4-$gfmsl2mixG)@{at5D=J&$D{Wv!t6V(~
zq)onr@(AwA-={v^lh2@u+kJUS55U^xBPefSui~l%Ec+DKK7v4~LRAjTFvZ?}^vo2l
z*hOpW2u1!NNTg!@WUxjlVrar2t*}@J5~EOZ5Im|#Q^C+<iV9~`o=|9i0!*ypySFeF
zCl$*#fy625*8ntLagH*`5*1JX09cY@0_}j!P)vRR(=ru_V_{Ra;t1VOIVQ!se**N9
zV&iRqmMJ`G22`$ipH|uxieX35r|XJ~bc92tV*c9@yrBq91=>wT*;%wzDKbhhz}1S8
zvCvzic((|gcN9M4uWnI1rzJ(JqG|?8ZHh{Y72Z`$wnybXMI8Ah?<-6>w_ta>;(dQ$
zKTtF*MD0U`oF+7#iZ4EZrbmhj`ZhjR94D{g6Gip`DC|;vO?wWWD!jh|cDG_`2C#b+
zp+UfYrZ`vumR>~w#VB7W7E#X1OU3ZFQ0h}8l>nt*QMn4_m144q+#CZ64}TP2E2NuI
z8dN-^S-i8Q(iWz<SWf*A#MLsL)(dWygBwtCx7^4;;cm;D@far$OZ!BKds==J3+sI>
zi|NApT1J0{N<T|2O;+|;&fAGnfMtvtrUhDRVo<r)vgV8ln)X@#(*tZ|w$4TAfTe>g
z<RdH>kiX!t<rebQMq1uH1`=hN{tw!sEuA`0im@C<*Z!!bp0<B9TXOBNzSr{b`v7xR
zE?EUm7v-lhQ0S`6j3?`r=?}o-uJkX4p}Un+=h7t0TdAOBl#lYA-(aGz^1YP+^;5pu
z0Es=y?Y4jkP+CqxNB1hvDp9#lc{~Cvhm<`TxM)Gj`;*ZYtlY5~)`uu3&|51^dE__P
z6s~-C9yCQLzaj72Vda_6ArPhff@WSvl+)lbLfWCS^h<!oC>Okj`eRC`A5l84T;&Fy
z6H3deK#Ns2j0ZWR{ESW{IjamUhWc~LO|xNkit=F|<WiMYl!B6`^rlpubmjaPAQ?(O
zdeSqMA5oMqNBR9XkjqnE_ywH#%8MJJ$W)=+N$J_wmA`7hTB)2)8~JW16Dig8rZVpz
zz*H&OuTWX7<l`aVr0i)zsag3p1wQX6TTI|=QQoitN}Dou9Xi^seA)=oq5Py3oDY<f
zQ=$H$@?a=f9xD^GVeb=V3gxYLnUr@&V1S=0e<ZKNb7k&&kY43uYp}jh?i~%7mrC~%
zSlXvtkOoct%FAk4@k+_{Lj8bp4LvdbR*|bf_E?3G2Q<J+90Uopy7nz9_gba2f$Xz-
znGd=BR)=mv{Q;~0=&3kpWon}XWDZ&N(pfw~R>>D37;H6<Zj%tJ<+LsdwdzR$3A6g-
z2XKa4t#XEGhpn<Yz!_=PDglYI`h`BNN35pW!op~)h5~TLSe0Bt506^)+y*&rb)2^4
zov`Ynm4B?&I1iwlv<fu6f!b46`xm04@m4KAqBg;5uM5;CT0NN#l4SK+2`ZDVVn(8L
z+G^GZ=*1bUJCh-I)+(6JtvP2km9ltKt%fFncv<hDxPrHJ*CKHGSi6jYP5Z1T{Rh3F
z*57?feX$-($?W0Q&Hi*ELxlC$lOY&st@neaQPv9wP<h09MHN&;TMts+QjGQflTd%u
z+Lf|A6RiKNg-t2e@9qLgwa$-*K$`U*^u9>9{&F->O08#*d-95P-M2uwYMn?9fScAE
z=-Y_@J68*{tF2w%WAOadSYM%8R;~4VJMi4H?xnX#o%P%(m{@Q9?_+>ASj$F1#ck_N
zb+~wq)<?dA6;0N)MsPM;H!pzocdTR9gS1*dq*Y{_bs2^1?^;`30Lne<HRQd%Z=G=%
z0#B_AQi0NK-EfD#e?8Wx_rlU=))`VXKDRc`Myc0YkfRqbtjp;!d}%EoipoCguyYXX
zw=S80%2(Dw?dZjTwF`~mYwK07QF2zf(Z3gVQT_cFSX@=_&^Ogh)lQ!ich%otgX~s)
zIthwARFk%&Wb#yH8o}zN>d`~qTV>V=2_Kbq9V&fQBj;j({ZuEeK)t^zoe~ZAs8T3`
z5ujQWiON7#Fb(Nm)e?&L?o&yRqH@3LA<Z8Ts^<T1UZg7D3YH+%1IpG4R^6q2njxwX
z^4*7;RFSlh2~)`iQ4Ck5a8MYbn%DvLhgIKEoGVHdKzYVTR6(?vD_XUiTq-dtzaq39
zRn47)wqq*zdU2Dho>zgKP<@^Z6(?1V-=Z&Zs#aQro>J}q0fQH>+Cnjo1eMPTpd_kP
zZhxXSNhSLZRwS!N1`RuflgU@nTIrl>UmLD{s;Z(FZE31Ww1pvEHOUzQ=T&+Ny=SQY
z91De+s)FAEnx%R~@7HYA=2ED?r26PNR9sfgSqy<9RbLrKrdU-%VfE{(=mTJ>R7Fz;
z+6`6g8dTm?wdVk=N;Ta?0p@CzO%e3gsP5CNv{p4M4-&Uj>&TH-r#ecxLG`K^OQ5hp
zl}Jl~+p0iv2{o#U-GSDmnoYyqtonB<SXxw0TTt1m`uIPX-KH912I#x0W*-RLQ(Y3k
za$n_2pObdgjRQ0(?NF^Ef6)WghXzPIRGpp<v`$s#2vj~&_0yq6k5v)Aka(h6)Cgm`
zRa3~9*Q45X6>ZN{KbAn?xyt(nNU!RU7g%1XhWG;drD}*DI@+fi7Y6|so1aLZtIf^B
zu*uEl-C#Ny(%mM`5q<Ko`In{}o;GX?N?tbIA3~wGjsM?tliD1hkg%^!MKlEcY<7-D
zrN2$&W|a2Wv}ZzZfXys-XbQCX_Y}xpoA>C{tXSJd9-WA@4O9X%-ZtO@<PvQ=-h?s9
zwsIH6ke_8|Y=6E0iF3B^J_Apx?WvEUDZ^H;2WypWa319E*p_^awia94M3h=>|5=Gr
zn{5DHk-N5s--Gx)Tg3**b=iKjH^?o48D<(TVifvqH?~04E89MDBn;RtJd4WLwxyJC
zG-z9N8WPTGTe?eK)L+mv$yL2f#GT}(X6Hb_PhAiWh5qW{v~mhlTaxE7Ts<ZPT|2BE
zM-k~r_2EviM5*8V2BjnFt?z>~Mt$G(CG}K2zXlRXYW+#*J+Cf12a=)IFNVTQ_0vzl
zQmE$XD}G76@&Mhz>J=T3FH$Gabh23eXfjBN`fL*9O4W5)kh`M3NaK7}UHd2WUQ_@3
z8%UWt?IkM9)z>IuS)qP0g?x;4Y7fdIuUEIyB&0!Yvkg7Gt-k65iAMFP{U|l5^Xs6#
zS#7Zu<c|8bIY^7T<R#=<)ix58+SDf>qI6gNod+zur~Z8?#P6%OQW&OPy>19h>rkI=
z0_OvD;`dPdP@OxG_DgrF#i<yRM{4_7xIZ4NTR8|mQBMnoV3)d(!gNp7zLe+Rt&S%j
zV~?7f2bgDS&98JntMAj6wqAA6EwH>$i`8g*sUBJf&OUV%xeEK$;zek9rQWYb<$(Gr
z_1c+BfE(N-bK%A_fN|vxQ(WDR%YPTdoqK%)JO?@73Sb}N-uW5W!Q8@$KnvkYD9a_B
zTcgETMsOd~XYep5(zi8|Td*6}M{(n-P&&d@QHnz}XBkgdn_Eo|jHBEM%HcT1Dd}tt
z({XO;dyqfDjf#TaSni`v)Sl#;Xp$Jm+1y6y6!#0c2jaP^p)e+ayX_4XiQJSuP?5xO
z+2Bm(4p;#DG#6tDlr!8c0oI@8N_U`ijvM0wloYP#d-OAv(>KGWH13Btfs$_Gen<!F
zd2Zck)Mjv_Qc%j|CQ+7I7PpBqm9n`vCqq7mOLm1sF83aV!1K5tmZL47`^*7)FK~MD
zq+R6tFF?G2)6iF`kP9dG%_Z(Ix$Z7=@#7(0#KqHxzL;yHsA36c8hC|1m2$dp6t8gB
zQZ!!WY?>i)jq9SEwK8rA#cj*EX!>MTa8W!suXA(0081s8tj5UP;0oHH{wDVg>8;}2
z1XNaYdIeZ&xEwc#*K+C|Ah$SI+L%+veH)Gr)^qnv<l%4N7Da>gHa9W_q>&4}f*v+;
z+i987%-wkdpm(_Rr6{#<8#}?$%KbrJ&^GQ4g{$v!xig^f9`}+aV)wbIY6!G*%dv$|
z*1;`J1Iq(WBqz{AF8MSJ?c|1?g!m)wk4h8z^q3pc2y32jag#v0xP^2Lo^lT<l-A8%
z(xTMEUHlFzo^i1>7k|!a=)(4L&#D0Wf?G{{Ltb)Q0zvw?1>{`m=T>Y2=PS;90mKKm
z$CtqQn!9!i-5un1QA)luU;jBRc3k*c$}V-~nL|+T#_K75;La~xh|+HUb_ERf;5|K2
z^5nh8!6q+$bPYhg`6U&w$%mgu(|upw!4-0TyiE%<`STx8Jbn+qkYc(4eBCs#1oGo<
zLeXAcat18>_{<%&*xAoZtYPp0etZKAKFFV?4Sk1rcgng7;!l#VF_<5903?K;5rE+e
z<vaI7K8)WfgFraXEP|#8egwU<5A(Oez!J$f&WENb{<9j`bcFY$O)$~?mvn4T48NMD
zRY&>H!@*)Y#(#%ZrtCPsdNBk~@WGU`7RyH*0oqCa5KSrKcyTINPVrq7%8uvbX=D@l
z%|l^DBH#G|K$H0CbRQ@4=QpDAG#~y9ENA$5daa-3Gp3@0=lF7GC`{ou(ibO{-(&}t
zG!wrj8WQPzEjby_^JcrCK7(IJBb3QAkx-w-$2p^v&EFtbS`I&LEl4h3^*cx&pS1=8
z`TT-);Jm<RPsBJ~<d?31rUHH?1DgtYT^~x9_%;s+T;><~L7<3F83t0!o9^uZE#cQv
z$gGr~egb28g&%zy5?A>P@c_NXf4>_rWqe>VdQr~bOG2rFub@NWuJapdqFu=ce2C86
z;9Flq{Y}144pPNm`Uj+%-*6dVHGCtzglhRGm!aqu@9`<x>iA_QDM0J_Igg;Jfj>*{
zqT776A1WL9G;(7$@t)R@Xy#}CfYKeld;wru__re<-^yPnhe8|gM|1hRy!{Nc-Q$G_
zn0B9Ec@b^xywAsw>)=OFsO$l6bq8P%`D|KPck*%FCcr%6&08V=n4d|$`X_uaZ9wkg
z=PyUsp7I{#mh9$xNU(=rnh2O@{A0@cc+MZ&4tslf2R#H{@Nd&1=_N0t`>K!kr*}d>
zzjq2aU-93sL*)R!;VtNU&7TSc8RUJ>(|K9Wf`<w)F2XD;D0CH0<^s)4ur7ez?!s?Y
zVBIZbP)x%^kQ_yur!bbL#$Ljz2f+3gcF=9@BV;Hb?kiMTplg1@F7gui3ua#fWsfk9
zmb3vvTLT0Fg$27&xmP%2LpiSdgneTmv0vCh`KSkkVscg-6m&HBhlH&^12jlj{2C-!
z_<_!T2oWBTBQaE1cLkhb!Y*1%hYPRvqAfzWL@tj6!IO3ZB?=)w!_Xw*&&gm(7Jek}
z?`h!(d1}rGGwB&IofVvE5q(Y=BsX`8&`e*$RAD$db<%{0LYS5=U`>dJLx_om-VEU(
zWrSo3rB?u&B{UR5E?fBE1q5;gr$MO573SK3<Oyp%AdoMx4#2!1jG!Fzi^AIxC>02N
z4N8S3A)pRumxS+W-h5ferA14T;72d}VqrGr?Uo2$??OeXP)%7qR|H`m1g{E`m4LY>
zNaz756YkM7QZBql3E&k1zYeBd7goifR4KH*g1`;oxFZzZ6hi2VR0%(31G-u;CDG!r
zM(CksS*@^%(wA-ty{AxFCk$Lfx9f#VmSAlVhL3}$+d{P?3~dy$C=}WxyrQSMSy&hh
z6?cToF=%TMcC3MEt-`Hs0BaLsz5vTzVcJTR?g;}o(6jr(w#5Kz7XnPDK|6$2@<cok
zej0?}L%~r8g`L7H%3pXSglvWtkA;i5V0j`udmDY~659R+=u<&Q4)Jc`{yymK5fn#J
zdM0RS{`p)uv<z~+f-hy`y%5fggZh`k0!m%z6Wq)(2>rsZ(`hF5N(g!fJOjdTn&7_{
z1o8<F3Udy@7-!M=8@lEqPRd8gRs51>m2To96EwMt@6%BVyG8d{lsv@i%Yf}E{zof%
zFY!e?RCtTqOCjJRj-aD;d`0stK>LZ=bOZZ~flDdJVUIXSADI9#jDmZCqMlxGd&Rt0
zDD4y9UJkVV;)gW(I3R`&0n9=1ZF0XJ5{J<;B}nWspcE|bqmynz#8;o96QLsWJ$fG|
z&a;4p;o{*Ia7KuMX|U<AXt5bAk>b=}hT!>&5|6>@AUh%+pls)8adHq0juD-`V8v1K
z16pex6O$>a@3>eRjnWBm;=gE%6<@4@ij(5e5zrea&fEiXN>pZnGhUoQk4l30Z!o|T
zMG4IzlElmwXh;^hUm<>49Gn7UOlQRBKSJWHs2v8LbK-n@98$zh@1rtRTt@d?ns}xd
zmFZ$kB?QllqxOR{L)=XM_)O6-6P?Kt=hAyUTU^!w&>V5AE823!owTOS6P?JrkuUCe
z2jUmRiSvPZQJfKhQh`Yvs|R+W=w^-DOJd>|5WFm|3Pjh6#C3#SEUt(LOo_<<4Vy~E
zj=N~PBF4}M=&Jar9}2ID5tJuWCjLZsce(i2OSDypGY3$*E-s!3^_Ak3xga;h^>jSn
zO|g#Vk5!_nkGxRTVyPvpsSy{@m8lhf^~ONm5*shVraIB=6R_5c2mXP4gV=Tgnr@2^
zzJ!WK@rgO)n#7EEU{kZW^dSW9h~s;K(jtzgRM%E<OdB+`iAQJ|cvox)0n0s6a}pZv
zi{F~)HQg>w^atq>XZE1>f!N&+o`<48EhRd|<)u*nNQ|K=!DDgsGnAf)-xExiD53Z3
zQ!$z5Al+gjEuwqG6xzi0Onglfi|3+C3e4^m*EgZ`LLBRb(o69YrLXsi>GLRZ-7f~x
zn&*`mI37F$BKsM5UW@B#nKCH)E(D9S=36-|bkS5(G~QJ+dnih7n&n++bJy&g4x0{W
z*3x?QpeCyjZHF}fPC#3b<^{zvgEhl{KwF5WdjKR%GxHDx!ZqjOX^&Ne=5z8#9@d<E
z8|ou9-Br*Vr77En(h-ex804chM=0MWMze1h>^`a~Akbr)cJi$r*PPl7O(!&cAA!Vb
zs>r2$QsZ|D0&$uVW5Ib!Bhlb8#cR%zLoPw{_Bg0d)Vz(P6q77jvv~z1PHUcT0Xd@?
z-44*Rnr=I2I;S~G(}olcOA+W)O;i_bO4EG&28JtL6E+N-=QU>JW699?ypPIE%|u$d
zWNDVY2ff*v7|Juw(Rk3A)wvp60z3|y<+QfT*KBwU7SjbyFx6hvymbgF3N&wNprTNt
zq8!;vn#HtX`m*LeE!m1Rfi8e4)?C>M&JxXcUFb}y#_vmzE1I930eV$4^*gA)rcsl_
zwM<h*OVe_Ve;7!G=D%1}Uf0}qgm|Uqi+XV0Flmk*1HGxaPdiJiG{4`4ifT>OEU?yS
z!V*AgHO)Vw?UrWFQ;<5%a0>O+YaG9VO%0l8cZ}?9&7}~4HfnCt?uaH$#Tj5WYi`qx
zbVu{kcOWeq-RA&n)x7Y8F>RWcG{wBDF?F><;+|$*25RqX!sdaeT@#ZIv<{8A2AUpd
zjx9jtL(PzxAf1})w}JLZ^E<teA8W?)5PzcaHGp(!Ze50jPc<1~Fs)m2;b#n9k7j`n
z2I!f_DiL7MHGh2%&R)%}VX*LpW|2t^y)QLw;b864?4sFszlI+Mo>!W6?*VN<6S@Pe
zuQlEMkRQ}+q`T8u`{WobbkQb!h?1*z4NXejw1pa!+_h^cQE<0*8+jl+v;~wS?y2qY
zM5ULOrHo{6?Ylm}^wFN|r}?L^_BaK*{IpXWQR}b$n}V5pv;p)n573UGgp5EfTLzZB
z+CMI#GyAkVXjQjgd;2EZ4rtpFfqhUr`5x3C(uR_SLE85lK!UaFCV?|V8$2H3q1r_m
z7{f5_lM(1(xOU!$l;awqwR;l^4{NIrqEC_93q6pC(r%$W%15*uh2f*MpXNX?M!TyN
zrK8#)it`-PGPEoIxHg88tWIdh%|R(vn=}$OozzbG6D)CB-%|iPrTw}d3gfkY^c_mj
zzMwf`qPFfO?J-W$-u)QZ$=a_sg6Fh$z6dMMXm3z{=2`8qHE27ht?z*`DcX=_kWbZe
z6j(~rUfqexbZsD|?Vs01yMbhARpiyo)Xu*Fxh!pAEsV+5vXlyxqkWfBu5z{I6no0k
zE}>B~<!eKuq3MEl<O!e^YIEqMt4rGPGr?M<eee|&7HjoOU|NaRr2vAZ+A=yE@rw3?
z57Bm2yOeIrYg!MQ`ITv_=z^AOe>ep33T+YH>({ke6r!)xTKj|C(2k*i(oO9%`nFY>
zw7-*+q*}XdIbdqEeXmektCi;9+TYT02hf>1t?hKMG-#XWqw=<PlMF14+5=K3Y|>7i
z1JbO$oCoYX+KT}|Y0)~CqZ6&#m6W92rnRFN<6UhLWy9Xn?x0kn``Ymof@;^AY$&4C
zp-mVM`3KtiEwJsOc4aC^r}oR0V11;0L38TI+AeFbJkcJhK;=`d|4LMLYuC{Put$59
z(#fA`Tj^$duC1hPFTL8zYS{ZitELO{QrkhxlRj;zH%k55nUr?_O8df8jpBe-KOcgx
zwOd<IJE&EdLzA=a;tTY`MfU~GUtM)$AAq>&)~!XGyRNhn*t>O?a&gf-beE?=p{Gt;
z2o^7$Kyz_#o!cZR^wC)!M5V9p%?B6@KV3sO1pIY(=&|3UJ6uElmjGSD|JFsi-!4FK
zuWslwRPNIS(>!Cp&UQR3JfNFL)7XQ$agDI>kZy_s>VtFxl&>GG`?3_J5M3<=@IrNC
zegO&7y+QdP;X3;?*c+kyembt?Vcn#^p*~XgFRciobh+U}*5Mh`eK8ZoXx)ZMP#>eq
z_yMJ(x=oY{cue;L_35|{9%VdZx?d=LK32yZgWi+6@`)(L={8;mIi(Y5@g1*wu^U}W
z(0N*cB<kuc(3Yg@2wGNv%$|Rz!_afOqn`jQMR$Z&n5jAo3J0X=ZYF@F>xwO*{k*Pc
zH`He662sA#Or1prP_lFn<Dem1_t%?1$<h6-g?O&+FE>=?>FjB?p08V41n3L8amO)C
z7j?6}z*(RR^#Cc<Ei$E|@sjS3I0#<W4NC)0k#6@M^s`tu{S@?;=&l}u6{WgG7oq-&
z?w5HeUDZikz;aD@G98-Abf41Vs9YEH1_UZ}nNcw9x{jwD$4Z^+aoBr9*I@~TH+Ajg
zjH%Lj(=NMe-K$wN*{RW$P>y)5u3-?Mw{#P3f~QWWn1)ilZUSxgY0ypMVBu|DHThH<
zb*8r<*QDd<5;p53<H31HH>C%aExI!L__ylTzX|niy38>cgf89a9N6?!x0k&6-MR@=
zVN8$io6WS?f2RAFUYgH!t9}6K)fJ70rWd+Bw9<R2d)|OjpKfF)+WK`1DGl?LZfq9p
z9nf{r`s=l>Dh_A~`ZMG+OVnS;2TQX4t&h-&GkRxhw4K%8p#|<a{ZTs1Dn%c00F|kF
zeGMg)r|XB%HmnT&@8?jPssG~*$Y<+QDcqBz@BR~&x%vcKx}y3p`kdtJ*E$02g8m~)
zPPwSRO!1)ty_zz63ibOYL&atN9P(xs>9bM*R;*v521}`a>=ejd(HB;L^QwN|NK~4x
z>76L+p-lhkS12sk3sW#c75d~nG+x(tkWaNzpF0QYZ|DOkV0crXauua2{cXzNt=9Wc
zWTZx49gE6ZeK9SXZ|Tb~K}DVZXByag{n2gcM1wwXD>!fKb7)51s1I3&$|jS3vK@?S
z(>v~irT6vATLIIq_o7|-9r~vip#FhAf}Hyg_1>R?bn4%sBSjwR>kdHRvHs!`aCYfO
zybH9adNp}*y7fO#1L@J{4T1PGy=xj+p6k0==<U@vsKEI`UrM_;Ug}Mml%m$Be=i+Y
z^y@WrufNh)ltRUT{wEcB_*%cgfXYF={wu&Z8~VFJTntHXqRrJXjJCJB8LpDU#NDuy
zzL&cV4bQ>iVel{l)6>xM723QEJ`{iRHYD1i6F!F8o6z8ExMd1Ot)F2a7nb@PrqQ%&
zk0Fz$J^_X)bPPwJVYU-M_ZiwLopHZm@gfKuFkGde!a+mITBtZ=C~C#E3o=aD1D0UJ
zLUM|P7}{<@Q>bALrQ(Gd(w6`%+~BYVauJ3RQV1M2EFVW+oJhmmcfcBDI89&gBZjB8
zC`B7q-U0Se!?RNuuVaSt#pv&GLyic669$(>7?N1Sl4O_`XXt+fxp+eZov)B!5GbOP
zWH_`MB-wC`B3Gvk2XmnJjA0~!oi*gpqWheo>=p$vQw@o|U`;bD_ydjUh6Z}l&l?iS
zv7BKj-U!f4!<2pKQ<kB85@50o*5pgdF}(FYEX+0V4XDgB1lfZn-_S*Vhzo|Exd6Lp
zD2f1QfuSH0m4$}yhN2Uf3~h8@Ts9~%=`hKP42S*zOtB$~Tr8!A=Q2oKF_cq`?W*Bh
zbC`C`@GB)#ml;HIQ<od6I1ECCfonizpCLXGnmp}-$t&+|w~U;UK6Xk^v<2BMqtuH~
zyD!NBA7S@w6ZA&eop~GLF?J4LgVPjiH<O0#q#a)e);K!}Eo4sFEs;Z0yj`pZcoOWU
zd=D!U?M(EAO|qM~l1A2UXdYlr+f{jExX#!qzXIo3yC1eg?>W1flqr^C_unVLOtU-m
z3s}<ag6M^M!LIBP^j)-jgA#PgOm;_HfmUv}qZO<bc81l^d)@91&7dmng!M4yhMoV<
z=-N#?dvfVk*`24aV71+qM9A0Jy|)%}wRY1kz?fThqY0(XZu(|m*4y>du}Tegx=x_n
zwktZ0%0|0=??A4}?xR`gOS7Hn2)Tdm*d^1{xYe#k0Ct<*ku0FO*}FYPrMrFhIDqc9
zzr7WL9`?s}0W{p+>=(#I*w<6==CHkqRsxas$A(~>qwJ$5qjbdngZ~9|?X77=eAGUg
zz9Yx&Yc2yN$v#>K4axQ|P0!HZ)Ak!UG@h~layR79+MguP!#Vr2*HB8aA4hY%RQuty
ztv%Pigq8_;_SSxA%eN1rL%&MxAJL__V*hj=$W{9z6llC=pU?x8a{F5pT)S?6LIh`}
z{af_Xylw9p1`8YQKfGiDXp{YT3KcZl>()Y3i@oI{z_i+9g9Tn<_DM@n`P_aU?bqzJ
z|E38;^1?oEE3VH=`&4>8_uK#R3s_#+=aM5~!2V6jQ+RE^cNfH+9jfSs>f(@522NLp
zn4e&Un?r^-+T0yptsa8sZ@0ts7WCf3!D$r?_Htk;OWxbT_7;ebL#i`6<LfYt_Ez~h
zthoaie}^UWp=pmp&^IUrIB=9_x7VSC_S5cj$jw39euvGJM|r@Zo$l&`4i6cC9da=L
z2%JF<3FOxbb_m}<htr2ToFHFtn1gZwBqAIvkE8Lh!wm9IA9tvBLfZ+4ZkmdpbeKvv
zM4ZE4^ty_72pEcvCOX_94?vPb2)#m+9js~caN1$<S|~i@FhFUXXB`IUEpX1^3(CPu
zaoG7K+EN`}Wq_E{96nnQv~-69e_#;KJDAy`Hq&8_4iW_p74)_)beLO<(j|u#Z^Hb`
z4u|R8UF0yb9F@fmMKsGQaWK)W?utX@GN4>_xON<E*Bm}AMq8D`1#%-+I}8m1bfd#~
z%4}_Nxc)Y}+iY@3`VMyAad5p0OIsYC(agHlp{E1#Z4R!K34GV#*>=F(bNHB^xcd%o
z7$D#7FljC-I~)=yTj7C&Pct|lI^^$!6@f#4ea1o+e%^831uY}<={X+tWe99@V-C>M
z;m*it7t(GM)BV3SF=IuaJWpn&3wXSklOYiHW@Oh;@?ot1fev5h{dv+MW?{@0n#89t
zpU|00smxon+D~I1d=J~w8J2FE^USKlC}l8T(k`t`=2!|eWiigzz?sdQmP0Ow@ubuG
zav9TRdcWr}TWR8(&)Cuq{0q#uK$I>rUs7<dfSI}m5~WPq>LEkS?lA-OwsvRlk%xCT
zD^R|y2Rr;VDm~dQ+7#i%2IipT&CaIuIUhEp9_oGB>*W9RV{>WWgFibr9h`gE9j2AQ
z4q%rF=u;s3E9DFAWfvTQ75i8(IFrmG*#HDQ%x<uku+BE~kc^)U7+=Y~Cdm-9y^@ky
zz&<3oHxl-SNtR;Y^#6u^g02*Qe7^oMaK6|Q1fDMs#{qguXC`Xq&He<+7ccLGd8T!H
zDGhPkCb|ioV##Um#e|k&Y<!u_Pf<!^CRbq;FEIJYPWvA?|Nh%(el7WaG?WfXR@=fL
zXQ>_Cae>lKN~zu}4WL!f5%UjdH%zp-!?ysBF}I}@wxi~!RzSQ-RaXa=dqY)sx&Zq~
z_2x7*K2!a69jvcZ_rFHT&1Tf7puuuRZ!+~k<hV^a<v*UVdGRhZ#@g(oX!J>&0CIB2
z*_@|2?I|1o4d`aP%`9?DC)iYb0z1)$^8-n;@uyRO&)LLm0%xYp1AmYUHd|)_tk`DU
zR%j@<NtzGwTATM+wB52vKLeCHn>157iuE?mBcZ;*W^fhABb%@!R6e$ObRDH9Hp}2R
zly%vBL1E~pHoFp`u-oQG@?!MZcz+JP&uo5w3)s(XKBF=2wb5+{%S)TTW1zmzX3<u#
z^xORQ9F?zZPLo@Dz$Sk(1YX-XKcQgypiSSqz;?DZ&>Y^yc5ysdU2X3KqU33tGzl<X
zw&TfT=WQGA0YM+z<pY56wau2IwAXgv5y(E<3+vI*{kHCu%W}Zhcn*3G+J4jou%oss
zQ)pmq^C*8f&NlKU1Wwz2A*GC*bGG5_;K{U&eFRc(`}k8dHrUR64AN+8hz4o0{ohH~
zEw-Wmpxdps86%+SrEOvtZWCv<K?8+;>OW~F@2{TO3=*P#PH~DTb=NeQeL~%4g~~+r
zqi%?&sP%tAQI`701>_OBs4k_rU5Q#R$5>RT+0VdQquz7~tc~iq<VL)!{_7lAI@QIi
zptnc;bpUMYSMNUx7*{Ta9tdwvO|d2)?mzO0_;TLleevU>@hr*wxvx?nu!mbqU#bA^
z8KqVRa{t^y$+VZd7Z09&TzLmZXg}9U;e!L*m^L&X<era$;34kVPe2ReN^e3im|IeY
z%A=eWJ=n*%jU^B`&aI;imlK>N?S+WtYN#(KIb{b>;<#Q)LOaEE*@H8l6O%v^xM-TC
zB$~KfT9hSm5#(Y_=9ZGX=rrd*%j`3p6K$e6%e^xQg(=+H5OAh)EffYz<JQuhpU&k^
zLECxmsxL?e$I(YLle46Cc^3CG9q^IOxzhH79L|dT9l6}wze7<TclHBt=5wZ!2xz*%
z{e1(q7r8$v%eH_^48o9<bAQL8Pt}~(8Q8bE<-U+;<Ge<|!iSvW&%o~H25DnpKUX>n
z*sr+Zx4=2T)lPu;YtH{N+6K8Ho5AVKOKIZe$6r^1#h;%>{)at$gXv4~1n`Z?01f2V
zjzHsH{ze@}Xg^;^mLA~s`+;_l|MF|dAL2vjKro0uXpT}aAASeq2>*=&EYbWIM^K94
zU$8(q$`7UQ1`<A+fO4FlK!-e>;D=DIdo2Gh3w?3?<`d*3IK@9pghV_a@Hqx5fnOF6
z^@)5jB?Kk$BOU@YnIB94E$%cQS_04v{&zL{o5^3JH*XIAC+!Q#<&{KA`1K2cQp#_w
z0q0fz%}J2E#*g|KrE1=X1!fKZ7X|ij@$Lz9>UbSrL62%H&kTn#ZF~t$;O_G0D3ElI
ze@dG>@AFfFU~oG>NY0H8ei@|$Kj7z)`iFcseV{w}ifs^h#LrVg(_?<oSFqv<Kj|b&
zU3_0BM(rs-%M~cyyy6*bdd6Q^PK%W1{27YL_45BwqV@~EdkM%({`DyIu#flYg{A#G
zM=y+5{2AJjF~Hxt3bfb!2Q)z*<eSG}xSWNwWsq|b@?*i`DmYW>yPI%~?p$}FrU-5R
zLekr)+#^gjhd_WZ@CK|f1qu)T0op#{t95kIg>f%YdqAjo6P6wn;%R{zEu0`PSB&6C
zEJuYcS5Z19=%0Y|xZoQJ&=bP!$tcAN4kw`gq_FWe<l=;X&cgar!XJCl7B9Sa5+p%L
zuY)m(LPa}FOEL*x(>ga<kiCuKX~823JZA+z`Uf}X1poUer3k6?QB4)hs4Y#HvI|3+
zF2t>Y+<75A0fuG>Ysg=jDHK<tElbFL1C`mrXgVG!NBElZMskG#x}bT&zz?u6U#R{F
zl@|n)<6Dp@6Z|8fzFhFwfyV2?yweb@6zu8kQza~>;{d7!^C2Le!l*b5*CWC3AxOWV
z^F-w<p{f<?2ZXO_AIxhZay}{tg&Xb=cNS#^80sRPr>VcIIJzBr-Nb?g7#VkQxQX`2
z?G`7ISI|Rzb0Hc%#j_s(%}We_A28nH`2fiKh(}^j@)Kv!l*eDx*`RWdIA#Up0z|8y
zfE_5tjYHdB@!VBl?-P~HXxlILQvm6Jc<VoO>7Y2B=I4jR??X`v5;uC0D=Jugk`MV1
zG58nMhKgrgfE^~vDa#>Nyd8zglVbe$sEiZWtU&3MIL8B5BwlQ#Z)<|M=|hMoiHk2n
zZ?c#-fG(XDXVK#GjQCy^tT-#iQhw<<vE?R6)R<Dr{yH<}^nbMd;Ov-+O2Bx%e`Fa{
z)O^sQf{Nx3#uo!-U|a<GEnkl_B%pHN_-<Oq1dl&Tud9&pDKwK08y|5FXy?X{dI0qW
z<F^k5OX2tjKY``S_~Z1X-y8pcX4|o!YHI&)qP6jSAWYtL>7fbezsHQj?>{DRu;R~@
z$N0VN98Ju&TOe2{+cB;dvd)ZlB5+-pB`qkqG9@u!@L|5S0JkqwQV9$E85f#)9%RnV
zK;<FEmkz=>%$zs@kVxjpYw9^;M<3!?Moa#^lgx+~@`%SVeY92T6f-aZpl6xvK<W>(
znQo0NCVwMJ*^G&v@*L*FMvPG|^B3hw6f?dQi7sIrn*dtM%xi&)E6iU-XscpuKLA)Y
zlWmOws9_@L`&7$J--F6#=3|Q2++jA%rujz;Gx{pzTbbdXqK9qF5<h_6WgbyH?jB?I
z5N-Dv7a2g?84EhDpo`hrhtgAKE<O6)%uw?2^e`jOL;M+YloIX+m>Co#c+J$zz&H;w
zgQsDIGuuP?87^$W4OF_aS20t;sVi(99rNPOP9>P#Y!~g|^I+3y9qP#n$D!VfJwhQN
zZ#KvuJ@jFFV?lh`2|t3<k9~uZOa0lmx?%4gHun>d05&-sB#?bhZ@j&%1y$~2@A4q~
z*?Jwo4zSjv0Bt(RPP7KkA-0t~s6lN0UuX<wEtWt<2>WmfEDdFUvj<BUJ1GP<g|i0Q
z_7%Z?#Gvvp>pC8C$5~7d@fu{=A{djzPNVeKWcK=52%Kh%`oVIBmBylj8LaISRA#cd
zPw4WR*quKBCY$yA9TGXLjW^^kv18Yv@iJ?60IWr9F!{EMS<fAiFJWhq%cqo8?S#M;
zc1{|w>)25}kgI1$(CKUqtcf;b-DYbkj^4}~o<OdZo%{_1+SpE7fZb&mjzcHzu_n!8
zy1wj_i7>yN{e(U+9c+&+8XvIk6wh;(Ecg!+o)T+vjqQ=VcpC~2N@mSKWw^xL3<_f;
zf2@UyQ<5{3k{d61NFj#=$+gk2B2nV<14>DfUw2~glO?t|Y6pi>oV^1L*^*C8<hjj}
zl#YaLxf1_7DCJ3d?a-Jn$<RXmMM>{xkSLIRO&*Ct$$$AEmm~p)V9aHSb~CVxBnz4$
zenYbG2CS%)tbYe6cO(G^(bg^*z8#fMBqNF;&?`wN=i6&Z)G`QoNTUwX{NGbrPty@E
zX&<FccuOBvK!uO=Q3B+BrDMrY;3xfM7D~ZVn?Vdvh}4|67lcY{djS(BeT#NJgiFU$
zoG3!tHwP?-rLXA>kSOWyVbFU-y0{i7(NaIke2$SiQYQaVY0`h>q&X&CAkr-)9laBR
zXQZF=F!;Q5H|5{tN$bCZO_!xM$02`B8cg@>P3c{_pX;Tc$|2Aq{h5XM1F01UmWNUw
z+C1GU&FMnvk#r-ix*ki{ZbJv3NM}<1OqcYQ6HuN?l?%v8^I94?3nmUqeP4ssSvDdP
zwz<eg(|6TX)=mBaH<=;{67I6ue*$#3Y<wbm?<xC*b|-krTIh@BE&CBcGntR<n|DBb
zv7Z70ezF%XX!DoFkw0dS>?cYD3zC)jfF)Qaqir&#5ZSs|z=X<-WN?_Qb1#jhEY1WH
zAsbDznMm1P8?Z*n=57Sc5!p^3^e|d>pS%<?vJZB_n4?HC2g)&790ghvWna{RB}ryR
zkAJePip~%_EgPZ)*coh+0y!&NM&9dlCfTV}z@*61C`mg_cI-0@Lb_}+tt-#VR#Rvx
zLzdMHy_vF{A2BjnvaUd&Wy`+%4V5`KuM;qrWtA*670J9PnY>swcn2&cvPyrDQrWU~
zAXj9zG`F}ayHpRBYxp0YxP)ag)6LHzUm;sq3$*L9ws)bTQudHCz;4LqQ&97!Y;7S*
zRkAN~Azv-?nGJhuWY6i`j9Q$x3+%hHM>NN{Co7|9*?n2yQ*gG+hGwHL9kOv=XnTMy
zSAg!6U7H2*N3t)2!1-8q%@hxwC$i9EsO^%u)qwS>>;N6zFetm?iAra)QXg3AVm7h}
z@~&n%`+@CdwrMBY+|43Chxl%@Ss}2{(`+H76nU9>KL@tA*~}Rz`IrsTJlxle`3RVP
zW(kfc`I|XQArNZznKga?!p!O~pfllSmmh;C!ffM@C>=ISqJ6lLW?tlljxrlU!ObIP
zZybPyF=l59fqm4>#sZ~dX7x@$J8tH*0D4cD?WXWttl4Ls80V8_AwiIfGy9vuO&835
zpNH#u(d;%w*{+x+7ts9ww%N8G)Ha%J_zw~TX8UhKZ>)Jgr8yRufBXl~3eCp`pt9b)
zj+`Hj<`WM>zQg<yEf~7YuTZ@9g?SkzyuLI~Cl8aiMP3;Md@O2u(7^*1Kc+x^q(vpI
z<W5`6d;xt~76K9+OgIlB`Z{3hEo8K#rpv-T8YNG8GevU_$lYnDRJ8oA3RWb`@6j4A
zMQ%o}&tiEY?M^R|*Gz<*ui|eWm3tJA=fJc8#YW0v4OCoq1<F1}=SQgAulSjAoewHp
z=n$Jj3g14MZ3<O*xPmoIp&9|6a7B6-cn&M3h2lCzD&Dh$!WhL{^eR27=z0@^#}t1C
zfy64*){sA?=-7z1M8$}+D4kY}+z)%tD!hJ0>71fy2ij5<OCq5mP0>pk2I&e9@@1b_
z_|OwxYEtwL2feCrs>0BeD{AQ_R;hTD1r;|H(`nLKt+-2}tXhSBHqh!7H|Qp9R<ONb
zakVU_c(1$VmI{<SET6B1UN1|=h~eI2ne#6=11-Ni3JnJ=RpTLk$g=+>h9tz&g+9jN
zmZp_2$eD^CVU!bo&l_(Bp!uQmVDW;Tw8ePgC!gW(UjxbgwCI2t5Eq~L6n`&iqAhhx
z7vuqT+56F`Up{m#)UJ4Lf#1J<_b%*O*)RgXS1qAb*VU)fV8)sbTDh*<MA1NF`G53Z
zKejEV58QTRC?IyE(g)nB`#XUC`vFb1cGXfo<bOLX0c84`#?ys~VNh^oY$$WyjWG>}
zpg*&v2FC7TD(Uqf!05-K6v*s53=+bWeFm0L=C8#74`c4EMn{vFSZ7#eN@MySVaRit
zBeZApGP8tc!DY-p;k3Y~VOcm5za!bGI;f6f4;29L2-}bgq-gftNGOY8$J~aYvFzd>
zQF)U6ly3P%R^0@hN$g|FEl6eqDOoawecuwLRQ4MR$EUHs`cwbYS<lUo&t`8^7$%4P
zW(-v1vZFk4feP65e?omBdyZ16F0n53sFboMU+BHUPN2M!3if-tJ+8CQi(z>s8%KBG
z4c0>omRi=2vf*yA!E|s;9s3`p$ThKt%u#A)7huw1lHFnT??JwWZJ~Wgt!!us^tQ9V
zj{<fFyMuBkAG5~`QQ5-=2IJyAW1}dX|D3Jg0l9uQcQoXjC9mnt)-Atr0K@o9G4wfu
zM*O^H{-#&#AoCfGjx+n3f*&rdwKqEA%KmE_17SCIb~d!Rv&EE$xSRcn_5gdZ$&}vb
z$+pn))r+mC$+kC}eiCgy>=}x|__EWRf#%1a`~gb+*-`X;+{1qO90~(i<y&A0Vf$Xe
z*ihCi1#MyMv^=z(V0Uyu(MgtT!2IX`UuH{M2hX=y0p<nk>FHe<O38`8E~EseMdN7&
zzgXb|6P8rn1H{so&%wD&K~eGLI}3rf!rdMGzr8sY7OiZd2-T_sH-Nc%4h8PlY`zBm
zwLg=mWnIB|AZ%cKA!Yh=#Wzs4wSP4lwr`<t<BrcMw&>2Z(iVl?jOqaDJeZuh)G6jP
z9WNcod{GVdz07zm4BE$3y#s+TCW(@o!<mr}U~vTVK|V}~WSqC7GMdqomSfCP4kVU2
zIe^MjjQj^$|0FU$QUYZebA(>G<xC4DT~sh;)zEaEd5e;pD;eEplxmo|sgQ4AG?Zv?
zhlx52(!n&-0ld!`yL`y?G0z*pGQf=f1Ym<q=U0GsVdswoN+g>Jw;68#c*HXP|EOo1
zC~53G)A$L5GMFV>VOJ)zRDvF4F(Y(n%Vy?}2gzZ6vqEJqQyc@NJSLbH*~JWJ2MbD=
z*(DG!We(H5afMNkpYtjsQsp%!vJuvmF_$ULq?~!$1Pv|Bgs(7St&Gn+6N+uj<=Fsz
z#H=Te-DBn#8sisCG`;O#GE>@s=E^G1!wNUHh$i#yY=IL5{MmX+5Z=R%TMoSe?A)v1
z3}%fRz!}1RIRn=wlwC<@Rm89!lnil{ts<xPF}CL^SdO#z%_&JIiT#}3kIC#-3XtI=
z+KxVDux2^Xl*y(SK|YH;Osj`NwuAD0FR{CiLEtjG>JR8GVhf@mSHV`V1NL?H0_6f%
zvYRKMhd0=Zw61Aj56~fJx7l}+(ALPVpgXmRZ5<qf=f9b?9gl(PU@Lw_;{)~(eIFjO
zqiDl(CmT5*<Pn=sORvZ5k}+U;!rrBDR~Os+FR-7oN{Wbevm5F4)5CsD9+hWo2#xb|
zcA*PQ>t#1|!q69N#a8s}C0k9ov3;yhHA<#__Qxvlykc!v0BwL>bqbAsk|7<C2$lT&
zHq;-Htloys#7eTrnA4JlAs~g4Z#ST_R-#=EV>%^1J5cE&?cEO02&w%$Ff>UzcQTC0
zlSUyM35UU*`WcnCrT71XT(|VhPLO_+bV=s_y#mT*f0IZ3mTZEW_+;-~0b-L(wgp{p
zk*T8qbyqfuZkP_4V=a_El1XVE^;9O`3(j8I7i(a1pUi#~N`o?cTX4FYbxs(9e&L5N
zh4V$WFq#&li)OZ>aY@ks{_DW92%1-~NJ|6LhC)XS#>U@<;<uv{trLv%8u9nG@mhdx
z|8XkBoEd>KPF$F8>2>7Iq*7|M4+4vj-^bjgOr-tH7vuvAV<PUN6wcHxMcYv(mz*!h
znAIGNPheWePi#tLZc@-TiFuctC~3^0UKo?k2=u8u&*(xRpTV#Uv}ZC_gOJE#9+ML#
zo0*yem>ed1Cs^=Y%23K<gsTwGXFkdUxxl1RRQV!f_Zy%Kn6JNscp)>Daw;z|7s!!!
z*~Co!3p_<k4mp^M8QnCH62@B!g1D$NK(8>*|CepfWQ3p>*O*VqlUK%c(R{p|nNWwy
z3g!%t(sgE_9>&~aZiivy>X@Ol?WmsNhCx#U6H2q>+sw$vu%eOiO9ab3#?(6!!+W1O
z@dtR?8A%Z2JD8E=9(=%<eh2nLrhh14I++m?lpZlkdIKc0o*RIc$~MuCigebNau+h#
z`Q%>DV&B~d&OEk+(!egVS*y{PODx_x=pcKl269)}7V@{2v5QPk!Bff3Sp|t(thXn4
zTG;dcu+3RAY_lA-_z~i$ui>oUzaSB;As4cTSzkhmWDASH9L1iY?bb)w9quqBn%zjz
z$ryHGC9FHj4zUF1F}AxNx{kA|nNV_qRsIdRSQGm<<x-twpXebG$G)VA`YG0e18Y3{
zEqN&tSc_D!CbCT(C?&C3T4+jUC6u;wn*H-Xw4Gt&=t$`__JiM0%45gJ0wtgQd=W5<
z*-xEeb_v^06QWXf%zdz2VNEk3aFaEuw?TasyOff`tJ$P<lxo;zg%E6FzyAguZDuPI
zfOd!da5e;6*i+6Rt*i^V<lES<X|L>EwwqAyvBS$?(|tCDj*n_*ZRzrLu)*Xie!%Kg
z0DH)~(@VOO{g&L{kJtuN9vUCB>4_k{>_VE}zF;>d!{C?fYD!1#V?QK!N<SOlhssxM
zR2f(X*of&Mui3d_X!DSCzJuZNlz7rRGeEMd9ddz^H^@~SESWtFEFqH5?xS=>QbVqt
zXvt@PKp;-ye#8W$PDxJC#QCfwi6SrOB=b7KnkBIc0Lhj}$t_qYSx*^rmn1oqAADKz
z@ey#AOXj=@QXv^e4yx;tS+`(Qr6hhiIB!U1HlppOWWrRmRY^WL2))&k6LfM!jU<__
z4-OOcq8-_{B-`h}nmUQMIk4*`78E3HkZjopa$9no=4*|TRrFPFk}SyuTC-%_E>yNk
zJSnW%Ci#gLm3JkBB~X7)67wzk+ab~Q0`q}nx)f~>B`dCjvs3b8Jj5SKBA<YCNtQ3A
z|2p(kvUMe}yCp>wSQwC8_d&Ovr7AfjT%_Y(qs>+NnpoVVU;cwOcj+*4&F+@IlZcLb
zN!>+g@|F(#4D0=*-Ca=VFEwR@bB}Zd-GKqpk(B)xC|$M_Z6~EK$u)ac+IbNIrYxz1
z+zSQLkxAgWB27Mz+6U5RSGvA3btkOwGTSl|EPiHZDfwcLnf?-34w(&a1a_#|j7)%r
znZ4_d5|;3^SuVm1@U(=V{s@>+W^dWU-e|LknK1OI*-$#r>$q8tf{Zbl-QI)RIJ3DL
zfSxj|K7qz~v#a+Ym|!-!2;ELHJ4=g>WV3PM06lFM>HL3FYyQD%FfR<20sYqqYcwu;
zgFL*8|6B<>m;6P$q?f*)0iI<&Kj8P;anFFWF7`0~UcY!N{@yUf^cYNAYG@zaRvSvb
zaNI&u1!HO$esBBmE;_Zn#tpy!t*5A_J7Y1N#-91B4C?$Dk9Fw89;QeDN&xd_JV+pu
z&<^AGGQUdEu@GhxeMUnWH+sOsnELA=;Y<phs2ag6X{V*j|Lg5q+^VXw_}=SW4lkiw
zAZU(-n5Gqv%S%zx3h@0xq*76NbCH*FL3A9wIEd&>f~d4LeBd+VQR<{uNex9Yv&1rm
zd}NZLX_{l9rkV3w<Tu|pf53FVd;Q(D_F8MNy}h2Z_gZTox69H)ux*nkmcrV88No~F
z2H9;6;Fv7q{a2HGI|$ZJ%ZLN;@tpLF2GuIB-h?yP<++<+-jQcrV6=cX@^Yq(I>o`*
z2C9DRalMfH6s}5ICg&`H*)ka!4As@rdXdZe-jSEX;d6zY%bDXfQuarmo26$MM7PLh
zzWvn7>uccp`%)p0hTG-PJsqBVq@!(*yfhTlURg2?6Hq4|Z-Ch#pXmkau$;;n)X$`u
zZy2A;=;z?Y899sNY|S#j8V+k0W&L)L-^!xd=;D%$;%b9dITU4bxEBA&g*Y{|`zQWM
zkcDHk@6-2uW&eOmcyqIzM)C8YcF;>t0d~@ZA`I;~HSU1IMLOvR_4Qf?XICq=HV)@(
z(BAwKJ#5q_Iq>yolUB{ONt?Atk!akax%ohGt7hh(^1IsMJcw-5(s)YV)2fQ$Z<V%=
zvoWQHl`o=gnPEO}8OsdKUg%=Ep>{q7y222$9O^3#Ep_mz++g5K^4o^hyk<}aGJ?6v
zaA_-_2wH8Z<r?{S3{`KU-wHzjuQH1CT0XZ{t>eGm!g%#T-k|=aFXt8dZr#=u3VZZJ
zk1&dT`t6+%IiQ<)hg7fc;A_(%y|D`<@95_$A^Dd58GbNXjs3pvU>>z!dI;2~_8%1R
z<F`)RcOCM01^5Hy^3#oO(4;!J`ENSHxAS%isenVjQYFWkinZViybi$I-H}UI!x2iw
z^Tm%mjqjtvTG03C30~lgDab)5V_(|^6XP2B{Bl%MH@G`qZH4aSc0Mc`J5pF-ddeKm
z@l9QK3#@59YQc$nkI#+8CryOfbf+MEPe0KMy;~+v#Q<`>t040?jn|;_^0^+oNOng-
z7j}t#`R;@Vh4Wf&u?*$y))F~|b2&A#^I^z;C{wv`uTC!G6j;5q&gD=`qjcL0?q~92
zcfgnOxd!;&B0q_M!{5k*--G&IMmmG~QD(h{k+#ci$D#L7&h|uGA$f9uZ3+E`Qm;Se
z#=`>FBS&<@Obl7Y+snKw98kF{Z|B2{d-Cru!O8=9**XYDf0Mquq5nwE-w3A)Xuv2i
z3#s~Ph%O|LlQ30Gl7H2UY3qIrbOp8Wl4K=GHz?Fn_jFMEspj(IwRRKjT?bAJ)vSPt
zugT>y44$Pb56s6o3QT~~d0G{MHftLN4T0zt8f*f2jgn5mvFl{Yhv-eJ<K6R5v|mT3
zzf$N(4B<YVSOI7Mp-s`?SBbXjBiLT9O~}U}S89h!pjWQN4t{)%?tFJRntzsk3t;FM
zxtSNe?b2fry1XNoyu<OIyVAr#ntSr8SHLZ#`R0ycZ(e{t-y%yG>@KBFyv!}9yra;6
zo3`=RNm0gGFxS&s&X-owFn-4N20FD6J#8f7m~It?4@CFXv@i?`HPpy|%O6rN14MRF
z*-fs0+D}%#X&j)6N9d`MGVa05QOYd9BsI}m&J3NTqn)96mKt7wB*I9ouy&r7aP0j8
zCGZyi8%o)Mwu|&3Kj`&ay356um*`M4)LW^Ni_5>Gs7#FPHm&94-p^Ec3}F3*iWc*n
zP~a9Q-XZxcxcBJOJc!<>HY<kqfC{~#U#OY6mSv$<+y^3++B{ALS8Kg)!I_V>y+LSe
z)=KzT(nW34PY}7GP3JvcyEZinZ4b3YUqQ0SP{65cW$+%39;&T|xX~aF7@j-{(I&(B
z>+t(K!?qfT-ZgyO4c7i?w~Mb@IIhU4@d~?Y1)nzBo#lGtZFW27gSkdGbI@d+Uc_PN
z^}0KU?kn}rCG_6YNAk*~S}){id5u1gV<+$H^M8fN4&8eEBFNo(ODw#w>CdHMF8At%
zOX0;wx<e0W?9=N5;o1TH>J@0z>(e=@c~Fn^M86IC2rsA~)^X+-i$s0QWH68EA2mYZ
zbA6XTY@X1^O@>~RKDrqGp3={~`}krv^vb)KaO<$Oyf+{2gWZkYh)u50AE_pSGb)=;
zT#U})f5BtaCg_e`a2KuPW}SgrRQH{*J$@js7^6E0_%I<d2%W~P;aKA9*=69oF^kjO
zZys3;$%*UF!@?xmi&>i7ln%?W!+AJUt<Ic`o)+l}LvhEs)G7YjBK(;USqRa@lZ#*|
z$$S+ik}tF4DZdATle%aFzMI!^B0BBG&XAnmhieDYOV^?`V=n)cGM(0dpLMwsoa}I}
z51X;-8U{JD@d{kY>A@*TONEag8uDG=05SIzpD$V<SB}C!7R#-#!AQMyMqXRsb|p07
zZm(|Nmq~u%17f2m;5|ApAUrQ2d3Z$RG?TB%-`Dg%yx18Td8uhxmRMEtKt}e;Ps<7n
zU^!oZ-vIxBK>y%?KvS@PNNjF)c7`Q3AuY?#*H>+SD4%im^~Kje-s*$jq-Vd(_(XGB
zR<ih$JN|!<wD+GqlODDuzst<Ms<^;0SS6izdQy28x^%S-*h3e5RLoGvC)A`;Cs$ik
z8=1dQC9O__Y;`s*?AfsJ0e&%-<Q$7%Vth_UzF$PLB|SHLhF@;BPp&!HCo?-c%P&7W
zC*3k5J~0_GSw6YRmRt+u67o`2)Phc3ii4Xqd<?eWX1lLT)qNXz6g#Er_}Js)U~@`!
zoY%E@UxA}-Ux8DptJ|>X$Z4;?Iw~g8D<Igv;}v5|Ep>W6TFv}Q@1~AfUHaILw>mvL
zQ5jb2Pb&Ln&C_;mpmSY>GVQc;v;AJ+yyBk2`0(&)qr=Arl$)GAiyP*2vNg<cxo)RY
z%r35KaImJU7u%?}>Q_r1Hv0mX3xDkzYzp-;g$9}WdYMeVfxad${7wV>`<Vi4kM6rz
z+`K}ALW4v6lLJFSO+kq%@%{VvPd4=n^f#Fjl9KubC5IF*cXh?*3EOg4<GKhd_ND^G
z&H@V*K`ug=8I3~BWqe8q+$jaQ3vrOqQ;4q_5rx18PEdCt936mOLLiVSsHYG}><Q{E
z1d_^v`U<gy@g*UUIuPV1#A(I=A#O1Si)evdiy$mpdom6bVjv?9NJKNfDg>79f>70o
zD~+I`LR2u05MnnYuHauVjuYYs#%Lj=lZ_@At2#-us*N*_l?CcyoN>Ketk%YZ+OBRe
z)T@^h0H3I(3@6nEhO5da5pc^kFVWaU<nXi_lVY4j<9evZ6yq53_f{UMK!=_xh0(v4
z+6|O(%FYZmvx;G;R9hHYR6Bq~KQ$x`GL@=4jmiG14J7%8s*vem?@>k5A^fd64ImMw
zdZ(kcPnep;=>M{61j=oya|W8bM5&aF4ssWhUad;c>@XdZ338aX+REe})ech5R*_kN
ztEwD8uMALaSskju+2F>hA^>>}QfIQ!k9bw}o`F`g%A0}Kd+G?oD%E)=gv1DyGP9#`
z7f5jJasanf3`2q10-!Eq)twv|au~0MSd1@7cU6{ZbW;m0Mx$J&$}Ps{QNKar8FkQN
z>`8xlpxUsDg%>Wl#^=#%FvC}B3V<9QsYSVHoULj>cIooEQDB4g-xt<v9k2fYE^|9{

diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
index dbeaf563bd3988dcd9348b33fb8625ed90901769..93540a242909c0c1b8937759664fcc3d44e558d4 100644
GIT binary patch
delta 127132
zcmYIw2Ut|e()OH5Cr!@goU^VuXIEWyjcZ&to5Sw9s~a3aL_`cYDnUU|0YQRf1r!Ap
z6az?5KoJEI1yoF6K>xS6_kREL=;^8Idf%$<Ij2u|bq@hSW6mERv$r*~F1pPbqipFP
zyyKp+$&Ww&E0f5&*@jCb5`p0+w%{d#RMF&5849*rJSP$43ir>PMDfYNN@UZU{6uzg
z_HA#eMBo(Tl3>8Gt?sZAlU%WU&F@tAfra^umZC&%GxmYGqQ7H-sehMM848J_NFM-=
zTzYmNgyKellP>rJ!reweB~fHLPMcbH89$$qC@TJI?c4>z<NsP$XdzVo&syPN%sr*&
zzjX9557iFMk|EHR<U%Da$#(p09<J>(O)il$QBsLy3&Xwfb!3<qHXoA9N>mJ)nWS8g
z!J<UX?1x~JaybUa2#bvw@0e%VFyirkP9ovA1~U?P9CurkDAQygK_qZ;MI|HAQ=hS&
zrpREVVdc0US<gxs{$y*ZM9TMY2-X&zq<Jj#+dfL5_Z5}UU&|0AGJc*1dVxP=<t1qP
zttpOaR;&Hlb4J3AP*EfjY3F|-jBXU<(hwgA;~E7{dSIkN!cA%vR8oHurZfsV>6Z->
z2{+AXLO>?z5G5z!zHSuE(%q?|gqz(cSfoQrAk1qNtWw8&nS@(F!YH)AUmZY;8>^Z~
z6y2Be5^kx?8+>AC?xzeiQF`KEsf7Eb(V;}@-VFvT8wI&^xud<Uqjp^o82)KgnWPU3
z9rJAyH45|~=ks68Z;nV?zurHT0ePa)kqLLjE09LYa^XO1&c*sF;HVK4|9>ETlYaJ(
z`3U^tf4K|(1ZifYV3Q~oj00bmYygl=BCjeWow;mXCDGWn0CTG~eU?Zkc0^<ITJ?q>
zxzx!6kb+hYw63)@ED&aQS_QzWy+rjKU$Wwi1@+Hl!9c3qpl_<)Rv}9GrviOJ@@9_g
zCY_lsj(1JkG0hw;ns#CKIVLt8#LRVUY1*Dy;RwPt+;J7xbjNdC&pAxZ+B01pgK^#J
zSb}SeV=Jx)9Vc*|?6}^ny|h;6c-5>O)5l?L-k#a+7}mVK^r_bIee?Fi)0=RTv&zQC
zN<Dv<r3{oy&izkZCtG)clcfGnTqT>mK`uG}KXI9?jU&Bz5BRBV-kIs?XxgHs^yvV{
zkQSX7*71FdiMor6SjhzCL~4}ObD8Wr#~D~$%W@RL;-Z6T*+N?Tr=xYtDXng~@sg{G
zvHvmrMpi#bDY>TjzmQHk+*^)fRy(p<cJ9^BUoHt#{2yhP=5k5+|F?Xil}I8Kw(aP5
zspoGJ`C>=gRudVsV@0dZOh1RC)!bIKe<~yo<-fe6@6U4)Be}~%{Ob=DiQmXhI=I$@
znEj5?t*QT4v~DTQcXqh9?!>q`Vp{iLdN@j350c*b%F(pV0A{%3>ox<WS-l<ZZ926s
zz9f}Qkj?I*A)ckOp8MpINwWVoV3q9oen(E5wv6a_-KISg>}b-qJ@bQOMBC2N7vDOT
zwH?sB9fm|{zN{6sU)JW&fJUhoNo^BjliE7Tr+zt0A(6EZ@W8{uAr%#-pB5=4vSzHp
z;_l6$O8K8E7e?`)55bH|(fU;#Y}%@2yhb4`X^OE}B~vJa9ost%ZQ9~HnM5udX=t>T
z{|9rFF)Eq{IPP|8rCQ{TAyyW`m=&#7IM~i>m}tizod-(u-Z-K<_p%RM!btvukt=E#
zr{+qD9Agds-C~rumYHbiIZ;BNTU20tlRP+22B!H^T%Udra7}(k_G@a$rVjrVl396l
z?chYU!9S5cDFlPPr1?b=*G}nleX@$K_WD4gldqxc`WjNP4*LA}7y{hAgOOTtF@p4}
zT|}2Rg`Blgl7rHrR6BYQX{I$$KyE2?EgD1i?L&#-k28cyYeJSiUz4WkGWzTnMW5H&
z#}L@dOt8a05-fBtx$l36qGsQdn<vF&%6=lt7VAj!{BN=xF^u{n>@xMxF;`-Ec#kYM
z+$0-e2x$Vw(dQ=D$>pduWbai&{B62WEfZ)bVKzn@g{1dSWE6LZDi#eP_xmRk-R;-p
zSQbSt-)?7dt*$0bSSzyZvx#g93n+-+u2b#zr-^55FVaN5q}m0O=yUm|#;+rmd=-=u
zf5$nZ9YxHKRGrX~OqUz!niEK-FK<xnWz&i7L_hlc(==*<ESu~rjyAUG35Ak=o9xT*
z9#BZ4-6^asmq`C_1=)=0NTFZ&imq%GX@b|$=XAWG?Fz}@D+EyC&cnCzoZK{R?1Kxr
zWVHM+xqQ^v6DM$^D<oarNMl+}Z5`@H8s8+cynBKe#?PW4yy8g{Hkra2`hqm)S5v$9
z9ih(`dJ=>D97429?8k_rUj#W0?Mk0@y@=>n74?MYLDHZ6jXryQL)Uh1NVC4N+og?x
zzP1qEbt5@jg~3B1nVdtP2WC@<g^kVdeMdIC7Lj{@EqU2{fq3jcImq<uNUEORc%vQl
zrmh=!lddyUD3n2s57Nc=^m%qmvJAaPpLb(eQAmRJk(=>4a@@J`i`%`5Y9IHdaL>k2
z?aN4NeY-K_((f_37aE&wwCl(yVg?b7b<pQe-_x~CYcle~I~@<3hOYc6vZ+5uwX-|W
z=aS__`fuZHTi9r``A2fB+e1y7|2;YTbt7rswIx)wvC+MrYIXk*_Woo$eNVr?CgJ8Y
z`W!`*NXgSD<nmQ_`g~JC0Oc=4#OIU#N+nsU8||AncINvUvdMBLeO)QJVf$0NU1g+c
zNAo?&m3!24nY*dBsxvX~IIpDp|6et=rWHq~19#Eqq-*4?{sED8&7zL&^NKz*N}}k#
zku-|NZnxd0&&x3&gYG(EJ$=a1e<6L2zzjhlnG!}Wok!4Bx`Vu2{GIgvot1R|OW)E>
z5julZ7xi?#v6$!{JJa=$7XjXANPjAc-1m;6-uf_r+80nu?a(_B!_Q4gb9y0ZBHYP+
z6JOGF!Bh)FuP3=bkxLERz!USWMAX_PK|EE5q?3c_X>=X*B^gavLPlSoBbTxYvI*Qx
z*XR<WzNaCZHh$z-p{LKRkpi8TL7GAL=(B$qVSi)kI{G8IFVCjy92ctnYd!UoJ>fbD
zDVL~C&!&>;mAMr4rX57Ov@IF+XtZ&0BAbWxq#rn%f}8y-)eZ=v>+tIo+!QI<bSof+
z+DiKT%O!F-xD%m9{z1*Vex3B+bs_sAyP90~+eSguwIiea4s@M9j;dqEQ(HgJBG|}f
zq!)S+_`?Pw-8+pmY2VT{0+VvQ9en9?mtP6xKaVUE&l9%GND9&Ljy|s(M7|`OsR2z6
z+6gfETk5p6t;nVOM*19uX+2&u;Y2iaI1z2$Oqvsu3H)^?eRc~W?2A7LHMbq<N1P-F
zfAy#9Zjo#<gXrork*?m24{#;sgbIoEKDqB_l+yjba~2V$zoLrt#^*Ay@s-NVrB<GO
zPeEK+N?qFbIl*Q%j*oR^<mN|za=-5sF|>#!`?w@(>!dSO+c%LMKWiLAmwh0f^2g*Q
zPeP5{I)tVB|H%ph)UPAJWLnNi`ZvBbJ4F*9Z#$7rc|q55IaykMq#!c0i0Jok2zBLW
z3XYW%X{W`6n!AoP<7o9L$?i>kb7m6hYm(^tV@uLcr8mns$+;~=R6m@k|GYrg{T}3C
zeG=(?rqSms{plLHg}}2LU)hyE5Jl(;qW;67>ua^&)5#@DNz!@_*ZK?w*PbUSi23_u
z`0N=Y;M$;ParK=}jr8%Ro*RL+qf(NF1&Klu-#F*6M35K5V=451-=ijtxkHgGxK0fH
zUJ|Fiaa8?OMW46n8Z~wWnXWJqb+U@w+*wXRyEmb)=4t~uI98y9zQ;oX*s93EsX=7<
z)glV91D-ym<ZcggvvdSmp7NsZNU6c-EAbjgHdBt!wfDEw>r0Y}zp`<9_pXVZqLy!^
z>X5Zm5jL2>sm<uR15+5KWM&10vKP0oQt~rqh)T)7lgTCTPpG)_<npgu6xQ)CsKs34
zm!5c>m~9KFVW!3#+;M<<Jw05c3W=hL<`*>G-f<O{Yl^N5hQi6%_)YjcJLxD|I_G{J
zs^_+L!RL9mcLDlMUwWYD-*17?7Tlxz?uYj4@cEa#8q}_vORuRvuhD$cu4)a<R_5I(
zc=uqAr=vK?gwy20i&<EUAibH}nUH)K`^P^~`ZBrr;uMFNDf8jfkD2%!Ui}%%Km>J!
z(H;dpfSEcG&H|b9d9Xany#5xU9%IJSi{Uuq!9p3toLdTIFmu=$E<%`@^o~2h?4Jg*
zQ0C8mpblevCIE1farqm!Q8*@&<=~EBVrYzxWUeOzAH}pd1LY~^dJ9O=Od)z$5yQ;d
z34AQ`J&(FL=KLOT$20K{;5UI8p@TA!c|*hTY32`4key-T!yqLwO)tTHGGhw?JcSX%
zp*+hxp~3VVGsll!<f+V)_n<k?1k<o{f$0<u(==w2AKa%icj?B?VP25mTg;+C@SDq&
zE<tDKF}u9LozJwt06+o5q$1ElCh8k-7csTzz!ftmXb`*0^y`Y^0kh@>{FN~tI<P!q
zB6iY?{4ukeULBRp!)DM{Gd~{#u!d>%5z6OGzh_{3!F>9NHq|l{mP7fH34f2`6;o9X
zzpt65G`V@hWRHjPE%RU&0CmiY7m(_iFS{Vn_sqhVp#H#gevNj1WVWTC?lW_10KLea
zq?>5c<Seb)ix788b0q)0K|A)OA>#|53BauRiU!!VibQx?_ht&*uK#&0KL5IQB$k78
zJGag33X5KU|Aq$k&h^K&&!GX(_f2dKXZ@1s-VI>B#j>W+T)wsw?k441dk0vuPg{eL
z+Z_oN?;~gaW71{>y`nn*_$3~~txPpiQwkU64hD3k8}r3^G;0U57!x$5JJS(sUd2x4
zQwKbp{)~As$c`|X4`EWr92<+U8W@i>aBY+Jrn}Z%dSnt}KOh}{U4s7ik<Rk~_YrB9
z2Ra~1`eYe^sZxb2fLT&Y9ag5)KyChd=$n?Vgi)KAIiTxR;R^lmSQ!jwZSDh()w|c=
z>cO055kfF?<p<cNFy_r@;|-=d5hKWJ#(em{T_Dsg!bC!$JBmSH+0C4TW_JH1<0Z--
z-hX2>=~?+NCz1A|tfR7b@o+S)&-zk~JAKco&`td=KR^?{IOK=U?f+pG;usK=jyMKh
zI*BiH(CG8H4*s2{Aw#~r0rz8N+fX~Xi!TD3nZ5<~i^cY^>9fpt0*KZtx}bXFdp#<g
z7~kD!og1_2H;_A+dGEpE#eCvnaTK|Ose_u?8{<r38Usyc8Y4|%8bdwHP<+ZXrZMDn
zhGK5)KjGU?=s$B}A+AkUlhbCW!ob|7LlR=@@YO%)xlX~&(PKS2%*M6P{(S)UJA_eI
zG5BAMl8WI+uR$|XznYeR<5n&~kYDbnrO&i%Ip}7M--4tIeO1=r98k6x+#R3W-5Ufa
zUCRE&wg0=`a6YpAW$3@$MJvi#P3iI4!jvlD(TVAC06fl&Y7r!F=IeTJ`!KCt5ScHd
z`vtvml$o>{6!v4x@izb-XBHMBib&>50!A?@ui^I;vp@$Mj6;urKf~}5uuNhKM#Jkx
zrqka5Tw?ks!tyfH?IgaNJZ9r;nB+4(v*EXZ8Aef7F#ph;{xS1AwWX4&)4}pBGv+ej
zb#}(P102>fowq~lDs^iH)9uo3AK}nVs<lFSQ2GsW)Cw=D;0-o!>6#rd36`pkfh|P3
zcRlJ(NIT4dGC`X9H%t<x(SIO{)6!~Myj_-d>wxxVNV(6byD5#Mw90MinD$WKliJ^%
z0ZoZ?3gI70L*mi771HQekgBAwRp_s`(k<)Im@TqP>j2y)i`D?(A$zqGmb+x%<8`U<
zmUS)xw~vfz1IyzwFY1{fS=m$+(Xw-y@Dw8}`30O8WRYJ1o+j&n={SAEc17!^V*zS+
z>nY^+zx6=7JDC1bHdZRebi~|6G4|bl_!`$V1)nEwEyES>+yCB+O}PbVf0sXg0BiSG
zMY#4lh-9y#@8ve2=)Z+h6oab$fEl`OIW!~YK0$Ynj+lmc$BAos+<#L;Xy!7z^;T3Y
z>h=(>eoUxG^{U6?ab25G3yNPS7ori#$~Cjmq!i^q4>&!moH-d)7nP~hva8BAEb4A4
zTWo`~LS>o;MAz7=?_l|g?J*1{PW+_?G}V(oG8UF`nrSK2{$$ODckt|~>pT-S`*ofP
z|GoDknWnV}teAO9eSD9(&>T_;6G?BX2TUg$_#ZO)e)y)#m=_@^_Dj2G!P^1p?-3yM
zl14WLp|{k28ilVkpYm#lq=#FA%uo9C4GMqhxAu#m36M(XKn#@5r`hQ-sn?fi_;Kmp
zJqR;iIz9$Pg0zg5%{kI$2NA_BDVqfsdD8ALfXkOQ<N<eEI*C@|ccc#}@l+(W)B3bn
z`j~Fed(xnOP?ks^<ioO5>O`5S2h!APnzfZlr>z8OxpWa_`6{Fl?-A)^>BccoK9Me8
z4&YPiQ{=Q2)zWKy0H~2}4FdNT*`G-AE1YCkicoBo&B30K!bMgvAJMzYHoibG+hx0H
zl6^uJrG+w7ww%7ITe5GHA?3<E1Qy?azD)A~4hv)f(a_$JEu?i}q3j@~5{hMoSR*U$
z%C;;;Q6lsH3HbZ6(kv7YW!k0agfdxP2&6}{LA`;ikbOD}vP#**d`M4Z&8H%!Dw*%E
zpstp=k^5(|_dbxG%O*C+@%`7z0xY0;DLX?6v)8ih?!dp1&2m7hlXa%=sb1EG#{c&+
zYbk&qWCMz!Y>;_tVEIY5X%$-NBwv<<_BzX(t%Y)%yb~oxUFAc9;LuIJ_cpp~hdgEt
z8nIIzaT5MK<UismQ`mRQbNaw^k36*)Ku`J5!!X?^KlC@;@0Wj|?92gqi;<}FlDFxH
z!drfxG6jd^KgGf1u>2CG+x+Fe`H13(d?mFdP##>0x}$PsB4P@Xd+kLO!E#LsqCX+;
z{ulg($|r6E;G|t%HWG+%dHEL*BjvFzz!oLn?ujU(<#R>=7$fgL0?Igf!5!QJ@$$*H
z0XQu`_5*@BBVW}IY{_!BlYpnl?d@T5PX4nVCaH2;G+KB;?puT?(&TNg0B})WCL)SU
z@+g{4WytO6xzJ|HTU~<bRk=?S#GNHi=22XiSB-+r4f%^Wuw}~+4~L5!xx|5Ba^*uP
z;h85NnhWj%xppX6Zp%+u0VtH8rh&Rh?oOHIyYkd>6!+wt+`w{Qp7{waE0upwE5kDR
zL;DTTl*?Hc6cuvM-mrNre{csbp2)qsK>1WIVp~B`BOl%ko}S6m)}l*Z$TPH{sg-Zs
z4DMI*;08qhTJCojb#LV(_X1ESPyQWb@8sW&gXMd<?=^6KlsBwKcQwdw(92_sqC+iB
z44o8N6##BkY*+{y7ll(h#OA6n%|c&pSG+gF?+!&C2cSFFM4<6d+`ty0VwYm{Vz}6&
z7+MS$dlkV8fZM0oG!;sRVsSD|4k~{B5+1x1<&WUdM-g!jN?%3JI8Yx}gtq7K{P`(b
z9R&V}V$XSWaDd{}AlMvLEch3|V~Xe0!9j`)9sC9>=I^C@NAcqncnVV#(b6(p@iZ8g
z5sL8hsEbncrCI(dMRR&MVine>ppH|VKMMB=irKf}H&L;&6cL_Lcp_hGS0pLA({eaP
zF*6@FXBClu0H3NT@dp09LPOK6+lpVkAl*@f1VbuTOd1WpcNM{J5L$_%Vk+wHE3QUC
z`9Luz81RP*H`)OxSKR*$>PL#7p1|a>qM#jusZ_XTA<!+#(dj7cPRipWpxvsxv=TwN
zC_Byo!d1Cs2oT$qgT4pN4&}Wo@Z_%iaVofXDP38Z>{c$Ml#-{iBfZx4DW|5PgAOSB
zivS!{j--T~x3YUN`pHN6`vsUBQaUK>c34@R3cuM(b_ApxyR!R2nC2-{%OU0~pM8VM
z+e*(NK-^JYc864?{CplX#mb|7V0lmZpeLjf<(%P&w^VtXgY-ZdGY3VPa-$hBl`CVz
z(4-3G4N8(dRx*?wd7``&fe4=}Gu8oDt^9gEENhhZ_E+HPg|dqh+_lOt<3aOU+4LHK
zZ<KklFs)Z+twa>>lvip|_fgq}wrv`enMe>QJ}bLZ`ezIK=@nc!v)6B-ZYz7T9#SOx
zh?G(6rI+v!&8`^-4>9b1Uy#MI5eewucy@rj2S^jyV#;uwX2V(dO=3$of+m@5)f&pP
z>{i+>I>&m=Lfv^*Lt7jd*paKDOlRB9g~>(Mg>u}N*?YxMX0ShGz|$4>d?5T@Wj$y>
zy~fU^B+zwsB_&#JvR&TeE6irsgwXr%7Hb?0F_-<8Zp3`{O+OR`Y?uqU@35}e!B-Tr
zz6^S=m`$id_;=aEG_xyVyWm)Z;y#<c0HHl#OD4eYL-uJ696n;tU>j6X!8XvG^$9yL
zhdQ5aO}l0_Y}^zmpRryBdj4uzSK5ep$#$oA>l;>60^nPAzy#R5W7jwV@t(avcVGis
zM%jT+tZD+H*us?#MVp+s^}8W$<yt*Ppe~$e7%W}6zs{oA&b8<Ozz(ik4gz)Ono^TI
zxK5O**u}NJB;xto!@YBd>0Zu%6Y%@Ed32jNxE-k|4seUNBBq1fnPkM2#_bw~W~Xy5
zV^Cb?@_&aigUg{L>{V_vB?z;)ZI|KcI+ykuoHw{~4i2-qf964%!+kLxWVxI_E&uX3
zZ*Q>JZ*$-71n>^mla>KRT(cjbE#`7}!+i<&?ih727fzdH54p)Sk1XTv689r+a3$(0
zxI?ahS8`ut`K)-t^`$Yeifdnnwp4QiPa?u++=Z_Ic+R=>hDj}Va2kr2+=a)edu`_e
zo+11<+|-HC)^nS%*{gWRJ)lX?2kt$k0Ff`~47ShQ0$Q+c;eY!Ymd^aYmmqEBb+f^}
zjXz6Uqptk%D=6If%0M(?2QQ&4@lHPSH9UCmnU4_YZvMI_;CuMHl+W_y?Ov`B_wlud
zKy!c}ZHM+C|LijSdh^35f9}IqS@3lo=C9G~+mFABEn-Cguc7HeAit9qI>-1|G~OKN
z!*UUJFke3$o<jH`o~R4uyOZBAKCCOE2<N-gBrSsfM};DapKN~u?J52SjheCiGTKj#
z<0}?`JAn_YMv=%rT8_pP@XKjTDdb1dR!R}S_ag9j`F2q#?(scl!tZ_lLLUTL%0G}n
zS;iOj0j`{Xk%X`-_{E!md(6+60nR6U1MR6i<&#I+p{?OB_l3<fe%mQXwLBjP=_S80
z6ZqG>lr|&Y@Z0vIu8zM`i9qZ5Ipfi^4}4Z6JbmP!Ek+|g@rm&u{mc)G#(m)={IweZ
zXF+=lWG+I98g<)*gB?M(T^N@J6E|UVh=AwMU109Qbf=K`5;nVpFPvbrTPUHe%e}&3
zn%#K{uA5Qk5L~_jaKF%%93B*Y)x*R~_|hMM7@=qml(B+84Oj8P$gAkC1i_8cB&UT|
zYY@d5;V3;Z$-*Y=w<}VF@@xs7zjK0q7idz2m|nnN5V{|Lr!-+aO%yH)StcMZ2}Pqo
zlOZsaRL>NaR3oOV!iMD_%@QhSLb@Rgp=I7pp*d~!-V!#hMqRG(_Z2Afg|-@)6bPzb
zaCAq=wBb7_6xuC?2Ya!=nqYcY_~`*`?hEENkV=KSl)8Q>oS>y^nGi=ihK~eqn#xoN
z@$^ow6w+xk_KC2}4K!6k-$W>@g)Wr+d?s|6jxKpFbej#bTA^tu>Rt-_=w1F=D1Hh@
zZ-j;^DC+IP%IzrM2@?jO+dc?BH6Z;c#L*1llQ8Ka5TAu0Ba}{}8)fI5#cn2q?<>xy
z<;fv2hVBGEF?%IU{Ka|K5KMr`4@MM$;#Jy@I3_Cd05~oN(e_cWm?B3JBDOmXlTgu~
z+zw)xIE&T^NGK15HbT626P}{Pb2LLZC5|XYU5x0(!Bec5OS{SO;@n{{Nf4vk!tZIZ
zUn1IjM${GKYf2Ukw@{>rn~y-5Dn|5y<#|y_%eXXgDs4}si)9BPT^6J5(de2CQ5693
zirANKp{t^+0&!mxU4DUdUECM|>85C-SxdIq4#SG#mY7uw(p<5{EX0&Ax_Sa$AU>g)
z>K)O4E2Kg(s1<O<qT5Pz>|Jpg?L?M{b0~LwU*w{Jdm!$(N6+6wvB&q|E*D*W5!)j%
zoVNELi~Z^Lsub&Nz&{ngr;XGqu}?IL260$0*tV&pKcLvBilaHEL)B#$V%o3zcL>}c
zP#MZl98^uhNil_&s>&0Ew@S<ez(=*y0)K~8KQt(oVq{bOZa@@%swF-M%3rmS7QshU
znG{TbYTFk82CCY0fOJ&#Iu)LRRKLFmAXwGQh6qDdF|_9$rg||I%4@1$-ooU%Y7338
zH&kJcz$qsC`+A^nsaF4mB3CtuUI%%q?N$`|s^oYS1*-cZzKGkZ6_k!FRUP4=e4zU6
zDOy{uS{{j_Qgu#&P@bs1eFEvJN~DB$m1=Z1xT{u;y@sMj<=CKv3;b)nfwm9Y?k)qQ
zojtY?J=*?2GE^Pb<s#^g%I^?fr&}GM?>vt7>AQ^D1HP`aC~x0w^F`Qne@lz09-jix
zx}Gl7o4we<2(ot|1N%M;$AF>lu6%IzE2NC^7pk#9_3t_k_5;4VfCdcQQUm@$Il~S>
zHMss4&<z=S8rPvcrJx&Dw-t25XHfogWZN6Kj(SUX-spBGU^C_oHhdIgn>(IQwc3Xd
zf`g4YS3u{?M2&;zT})0>NWRP>GmMWgmRZ0bX9`wB8OkiAFDQ~}bCdl~cet}F_Q7l?
zyJ{{%@n9Ea!_O}E98DH>v$6DM+rv)xMBQHY=Q(JSCmS*w(0%N3nrqk{?DK<&U_U#Y
z5`qU<_kW>1$o_4HsTaGl8ih9-?+d4gST9;LA7(rEg7OHvlBQ?@Y!GD^1KB|?Xz@{Y
zHZ9VFShrOG1hXb5gciasjX>QA_P{jMg|glHqX=WYmLiIicDC~`@Egv4)fA)=tcL_e
zB)gq<GNRZ)w7GMNZA}|V(d=6Zq!@PG5)`rQQ5jssvHk*zc=j6)^iBeMV+C-D?5ej=
zo@Pz-_Bq2Yp#?w^d*F8jlgw`SLf9$n<XwpAEIV=OIaHow=f6Xd%4*L*o5mK;hQoBW
zj}ehxWJ74qeu>>P63WYL+z7bHU_<>8b|(ABOZdIQdONO8Yqn@ZcNpGe-`<8rHk&2F
zK8L+99Byy1zvtj9$Y(tWUBHf|4D)SvG@Y2Z!(O7Xv5@WC8buMiwIeKx*>5N>bC<1E
zfb$;f=NLWRWPj2R;XPm{U=sn;;T!a=ma&`e16Izi*o?YIY%|&$uVBAw4L^@r-CS5!
zvQ5a(6V^Ei!9HbwqJ>x$>q@;^&4vy^T@CAOf%J@h_yF#nvxNsyykKXhfwPwVgOcno
z*;)4C_{v_fEG<r7v*tYjzG2s0gu}P&6gs0;$4+hwllQFpA&L)d(s|T<Vsj6{@-sW;
zIY_r~fiIwR;(nwz&^E3)x!BG*_M>p)hRR^+&i(Tf;5)e&&tc-hDUYLW7q{%F9p!HB
zem0uDhZ~g(X)m{rLHBxcmF|%Cak2E0b8v2@!0+c~)4g$kd$S6X7xyP654^cM4<Pw)
z9G!&@<U0P0;wYEAA2A){8ffKsoC_^Q2L*8lXiy907HH@u=7Q?wn9`i!7U@9~%GJ_v
z62`evPU|FBb_y|ta}zJZG=ei)fsf=i{|b{R?kfe9r??18qhkU!1IidKCK<R`E`qYB
zaomzs;Ed-s&;lWWbE6YTiCiq@B~Ej40WCYjEyO8UEa^GT8<-|@qiMpB!foyk{8{dE
z1`y}CDWRxK<?<*oc%EBz3ep8GgH9!+aTm+Moz6M7qV6Ksts8>5%vlGb^%>mHqd}I*
z&HNQ6SGY6S|H7){42^<WT-Y5vF4wpfl)|%L=aj8bd4v0rLcGZ_OQFr?M!$ef4(Bov
zo^Elmv=N-k^(co)9%q~c(tK`88x#dx)mJdN&GA>keTO^w2)IIS^#&A0+yOd(SIljm
z4bHpV>Sy>W?r|Gvg<Qh*aYmr`?c6Fe+FQ!We8ByHD^CE;L++dQz?X6B>7+zCSBImk
zSi|J0U|GQ}poz+3u9A{ym0WQ%SU%y7T|h8TxhV<oRK*=>gSu*NHqG~IIC~!aKI6Wn
zj(yHee+BppZVF8zYB_sKG!QSjcZ;EY#qGU>*j{tnzK7`>uH_Ik+nMjM1ugXA-TsB8
zFQ5AcZ92qDX?yE1zvVFsKi*CQm_J{o1N;cT@etqvyqpq8fxKxsB0S2+DZz4#*V38G
z<NS46qy_Oo?U$eo=Fk3&B82CE0{#TQ$p*Gi{tp_r!}uG!9P4Kp?d@rQ@f07r9VXGd
z?@x#~hX17<JjL>xk3fp!|MY~5c>W#DClmOVwAYi!pQMNRG{5sAlxKJy4Gl^Bks8F5
z%y;PrcnW`jCLw3}zm_40bG%O&id2609l+1?9|xkiz!!W)bMrL*=1G{Q^AjhaxX3T2
z?93&82fbr2^P@k2JA+?08kU)S$Y}tt@I85S!d1RL7QL3m`_piGjSq6nm~FB@&qQR|
z{Pa_R<?xpV;>)_lJLZEcm;dq~p!4`#N*(0$d9;gIz<;JQJh%B?JwS4YkEIhpg?#lg
zFc<OXR)D3Lcbx(ymRft!hI@QJYFG(>f@TQ!`Hz=jS;~vkAU)vg?b{H1IbSgoY>)U+
zG%{51zLXt&%<mr$U?smZ1~gCjM>Gd|%5!w%Rq=k5q^RbD${^M7+i8p98NakUaL@TK
z=nUBlK8be3YWb`bGzn|7KcIZY|Db@s*L)J~KE2_`@U(h;%Rih2Z5?0V5~TIK(-27S
z_((lE?LEKEiYPwtm6SaG$X^(SE@|MKUI+dYe+`FYuzs635AL@JztB?6N!aEKPG@1o
z2`IM;n`kNRBCPU;<u>7(CpcY&J+r{FT{s!QVCZubibtcrb_gCPVCpVpSHaUxVJaOQ
z@eo{pLESDPWiK4=7UEBXdygPL4E$c9o;C+O1$6>&`-GHfuyhF1X`*~kX!kQbc?nbg
zMxD3t6J=(7g!$NpR`?3PPDC(=geq{_6^8|XJskQ8K6_C33oi6(J0ir>DWU)&fKvT|
zLey$VM}?w5xHu+6H3iLa;q_J21qtscuNEv64T0YfLG=&nP6+uEA%zMH_ankE;Tlc1
zPYNHpBkXX&HULtDkV6L{?2&@sB50$8n*#wnCGfG3qJ`3d0LBOcEjD6>*0ci|C#<;(
zDPH(E5fLT`tH%JJD700f?zC`{7G-CIhF6F%Nl0G_WwMYw1Dq+sqF^Y`3N;Z>o)bLi
zgh{H<;Th`A+XXLLR$UPKe+SYu;nW~V=|ZFrqPQr0O`BwwgaMo3>9X+KNyL;P9D9o*
zQ;-}&Fjs^wp^&Z$N1MV$mhjCVaB)Lm=nlLoNFSpvTiEpj`YA`i^N(js*f1EDxk7Uj
z9OVgihBhqng-ALNTp*m@1&6l<{EP(;mk{#_h(clgC@71BWw%ij3$X?$?+U|cjdo8+
zpqx&La3BKk`$EgNXhf;7{AZXv5b}4R?xFC88d@f7{S%ES7w)fv@{yow%y9?<?9^Y6
zg>@5QQz^*eVDm)ywJm6#3iF~NRS8SygRNRvxe0Bm5z=Xg_nENr2T0F__ur#<A$)^#
z4Olh5p;JyTg~@bs>y@y(D=c3N^XV~qBRJD0@LM6QFWlD&4VwU{7yK^K^Y=~|PlN1x
zVfX?dJ_r}lxmZyTrYuf_kVU%*pM*7(Gyg1XUxc37BAy@@PGW{TBxmuB6fU-kqiK+J
z5tk$azD@j<(%Y_Le@eh_7hNfv=_dN81F%D!K-<k8;?19E>aj~Se+_ZB*v|?YPti&f
zsC}ZE#v6y|OnU?eMV4+TFVTG};`J7z=o>vGIzFTG4vQ=O0Pqu={e>bxWWIxoKyjlh
z93B-p8W@8_$5lwd;=Gr@g@_+$ry)%Az>s2BoD?;2(1wejs^KC+{D(4Pkz(Rwa7T$H
zv|K(VGN%ztw3tQdrWo<aQUn?+zV?S@oLCtIws`S1ozh7VC6t9p6o*sh{j|6t1b{PQ
zpC}Yb;s|<Rlf^l2;3!4Rqk}~Dv*O!$i08yPj}UjNIIIdb=f&T@Mh9OI9Zg`9CRQIs
zUAnlGj&fcUr!;|dNlc)voXetX2%^Xk&-Ox~nPPL=hPxs*`x5T2B9Q><EV1=aa9$Hn
z)3APB%)1Th8=@S!3&l-doJfyTwixUvU0||bUj?!Pv1TWzZ;O)$0(VEOqTSs>(MTs3
zi$n)4K8nSfCNQ}xhSEyrp6KKXlM>O5_Au{@-<HBrsaQrg-~%zF3V?@V#5M$2CN85a
zWVty13*a7!{U{$@A&v_G*<-P}okwVuVhWv>dm`RC1jJME%Yz`T5<jR=S1r060%?u-
zV+xedL=Rs8pNmx`P`(gfQ@XWQ{EMdEFU7y;?fFXdH^bp;F`n+`H)0sQzTS%EGXSp>
z*KbE%y_nev5xx_r{$>Z_y||HPJRi^sn0^#*QyQ^B454JqC$Udc^www5d;!uHRVT_5
zIjMqr0pP6qj(*g#O~rnO(pB~8Ib3X49ii{VP1Scb06SE(3K6Kg%Hs=A?^OAW2hKzF
z8=Z*SrRqJJ&erT!RmowqN2Q^(>t59lblA>Q<-Y;k`&8+aAaba7EC6D^D&-Ss4yf|!
zt#VM6S_8jcsu0=+^H$~14;Fk>3DhKCRp@vq52<eG0Y9wjMti+}sy}Hy?XT*v1Y}24
zj~o&_4FM`o9_|BGMRXYcsA}H#usNohzX!_Ws!uel2~zE*a{|FCGtD+aRKBkvoltqL
zL=mbgq;zeVN~9s-q{_JvfN<3>v{4tK;?{#DQq`Ug2S%xmOosB5YPcRO(a5yGkv&G$
zm8P<>ssog3k5j#qgEUd4rZZ}%RbSMjOV6n8*Mc-jRd5zXvMT8z+LWSV{|3!jRYL*%
zo>Lhjz?Q1|M2U*?sv0`hdO;OVd$nn*K-wQkR~ae4bW!!JFFagQO*sa@WxJ}ZH_8l^
zwI>jns<<RnUQtEUeCn#o&;@a4shZP@_nIo3xUZ|E^I&;H6;FHAH&tpn;F+y@uoqF}
zsJ=2Fv|B1Y9Rtr*wL%9YiS+mo;Q6Y-3;+eH6gszfTQ!Q_cXw3wRYT#hQ1$0V*c7P_
zUV}}s%4sT!64lZ`#C=~ihF0dKs=nW$C{qofUnZ5SifI}0NHu~+vPxBQIFwIRR{9aa
zQ&kUIG1RD<KSkX$RaFXb&s7hnp`9;PEoQ*qD^*(KCZ4LoJ`SdDRFzj?`c@TafK;a%
zLbKiXs++H1`au=57%lv$;^{C;gGwrer%$R^bO8RdYPJkfY*ANGp4Lgd<SZm-wMftQ
zR`rH(_;pcNwFZ2fdWSOruIg2<QMX-vl*T7F^@T!8knK>Pp!Kx7df5k5?o{V*1&xQA
zyAElW`ZZ;ecdP$x4g4PUlv!Zgt3G-RfqJSVir`|OT3!l(Lml52Ci~S<v^#V_J;@EY
zgX$~4g2hYy+X+bC>PrJq_^5ZjKtK7aue#IOqC@KG;jlTZ-r5|6pE@Q4r2gujIOD81
zqOPM?O@O+SA6giwK1QpzqiS#3N;#(fol@7w)o!#q6r}#C7r2AfBbp$>5cL{5&UQkb
zLFt1~b@>l~hpC%~(lesY83B`U_2cPuv^_$7w+|{K)!!~e5vA@*le8Fhp9f%zRiB_i
zH%@(HDjX)Nd(!U1X>~BgbVj`b?;b^xTBU}IWOYI^EK}4q8Q?yv9@G|f=hX9hfh<*B
zpa<@}TD}pS7u3oI0MgV2-4MM!T|H2M--~KFIlQE9m<;@7^_LL<W~lx9qsUZ;o<wm)
z{rv?XuBr<tO`N4J`T*QD^~M(PbX|RvUX(Y~Us7W8rn-6_$g<U~D4CF>F6s!*Tk5%V
zyeL=Qe;A59b!s%~^6lzAPB1M{Z+5}Ac3V9m7&Ld(qp2^8)$eH^`K~&M?yGz11z~Vl
zqHf7Td0%~fAuLPPl8Y$H)D!+fXyxj5jVV_3B+4Q@Q)mB)etNFHL%#xep<Y6-v0C*n
zl+${tzDj$Suhe!|Ix+HEedaZ6-l#`CMJK*hkLZ9_)T#IXiYV&UlT84=QwLFI<-J<?
z1JVbzDFbyM)rR#b8q{-#p!lR-T!OmKYSlZq-=c{M1;9zO*$z+6nnc>$-m1Ae6CPYN
zE;M`Hrcu~eLF=lK%tWzW^OW+tZkiM&@H;e0Ix6C>Dc=C4ho(a-(CpIm{Q{)BHI_p3
z-X4wX&oJ4mnNAP9rzUv}>h@{ItVWX@ntgQAYrm$;OoVnoqoAC^K}|~mWL}ys{o&7B
zQ`XB48Xt{hEwsLx4)lYMLz;`tL33EMgL>9a6C(oXuNg_dYC57R{}yovXv*ma7lE3|
zbQ1Ka<~?np9@7Lj1>m@*AI;{1G}&JQ5Ue>l3Soz8I?o1Ym<FfX@BnBQ-$zX0nz7Aj
zH5Q?HWC0>l6HMc4lxF%NNT)P4dtno;8JvWs#b{=>Llm)^%U?o@(|nX6?08KOesrKn
z&=k<rG*NS_C*Y?weY-$9qq$2vPf403lp;vh#7W^dMe|D-;Ab_*=$(2_GX%*kyCPL{
zaVOZ$YYtKt;)3QB<<HYJ3uv=8UDNtJq>GvsL5S&+CS^D9mo=+s*_fe8x{qGV)YM8*
zcSTcw0xi6%(bC%`OA|=<@ion!uc5rI*^mk44UN_T&YPN^W(1n88KFc>_8iUDNSNNz
zbp8jC=4vL5hBi-gc?XpFn&0SbNr7hG6##E*R$c+y9nC2^AW)=Pxdl-aYrc;M+g;6^
ziHPE!=952gB^pmU3v*vn&;!a+%`X|Se4t67vz`w%d=CUurg5X!XSrR|y$<3d&EK^6
zeXMbcgu_aWcT*^zXdL5!c&e$d2Thg6PVen%%{&~*QPgNMDJA(#<4dRBo@=&s2K<Gl
zE1fg1)qJL&d8xU?KzgHDz5<qSHNEK_Ri~Lpb@iI4Z3z3F#(sge{oiY%==j+O&FZm0
zeAFx&0*4KnWgZ~?q$yd9)_>Nx2cy`ceXoFWtJX+A&2rJY(b1M|T9=!^xoSU1QEb=t
z_CV|1wCjAqvO~N74sh<;bKjy#JGI$bn0RRSR)J-gw$vU0o88(qG-LJD{^$dneOl=m
z;2qk4b%<%dR-~it2eh@#(d>iT`Ph(Ecxg-XVB)PEGY3)lXjjk=mwmOlA5nKmyPyGN
zhqZB(mGINvb%sNKt@<e(9?`nF02iQjrn9ht+7Bi4{yVBYKvUIY+P~;b+HvhJx?6&@
z>?_y=Yu|K+Nr*Nj0KgO4Z`{Eas+~3pmSNf%bV%`}_APZ#xYj-aej~K{BQS~7&ZXNc
zN^AW9mQ&h@z3>pNjr)W^W3)Qj_lVW@@u3s>aoXE7>cwmC(>yRiTj2mAQG0~$kJH*7
z-f(|Lo3jw4N!su!2rc<PF`d)yrokjtt8W1Jd2M@I`CQO)KS4^<PN(T$y7q8yuw2x3
z-v;VS+8Lwa=(2W_4IVPJGrptu-xaNM7j)ZI?PwZ2v$Q|bA>(UWzeoVDYrSY$b5q+e
z2~xIp$4+!Yj&@u}L~%>IhX-4()`RjNdD=8OS#w)E{WJo-qfPFIC<?XnyFyu{4Qd5I
zv9@w9EbnTsjYN0d({}3!c*hd$IoevguT^`)Z>e_rB1HN?%hPYiA8N;@0#T-&v2U5l
zK9k1($J)U(E>&tv>1PH{v?;Wk`&8Sh6tP!nhu5H}*0!ZvrAGUA35sXhiP-N`JlC@H
zyP+4_j<oYot6l#bF}&60N#VOryNHrw_1Y~@pnRt_QGdMG9&QP;5884k)P2;BvcCsS
zgEofpJD;>0zCaY8waW>yMYj`wBthY%Tiq6Q&N}Ty)NR%M@Bly;T|Lb}w(G)avFfJN
zCj+oU=lmlIcbykaLU-yaK7iUoS57mCUApLMD0l1PDG9Mhcbne5`*icC&@Qk;_dERx
zaldZt9W>^Eu0QQu9n>|W47Zo=H#!32ty|j>CO*2W^bq>$vS`omkS>z^9@g!r^GANV
zC6vMs(4CNjB~Uk#h4QFw^GN`X>GnK=bX+$q7DbS*rx9Ogur7TAodOQgB~rfPgl<P5
z9ER##tAP*G9eE4oNu6IES`n#ByMxw8>Bi+kI;Gn?1t!tD($xUO=vvVz6{~A1N6*CR
zM$pDdye@7A;!V)S;jeZm5_N8UVRBk0OF-CXbb&6YOVTw{@wiiybv?_#oubQ_il9<;
z^`{}7*DXv%2Vc+$baWt1*O|6x(skQ8xWA|yupWLd>GqBQ_hsELQK-w%#Y$j#Rkue6
z_gT6q+RVA8`+}aV>$>d6P~Om0g+qB$cQ*}yY~8T0(HHg{U5lCUdrP;CR^Yk1tJyHk
z({*_ZWxj4(5M12R^`UG{p{^niCPlgpv=v#bW4Z%>S9g#SviEcoXnU<h7tlD3(tYj$
zlTuv{tz;kQ#?Y3~LmhT<aog(-{|1%{U6d8d$9CPAO8{2tZlt4Yp6KqkN99vp4XwMX
zbi5o5t=5gDgDEw-r!*8i(@mjs6VG+Fk5InQtym1wT3wU|EH8B__Yw9h-HK)4ey!_E
zv#C1WPn71Y*O`u@?wzjkD>!<uTM`4Z4?26X655Zt=9eHg=$vS0>XU8^O?f`+`k#R0
zthdq4x>X<e7ff9A|FlKjHvKeuBfIKZTGemYuXBe(H~rYBsN11`&>Mxj-kD}DJN1c_
z7xmD`=0Lei|APY3UcC#Q6Y<o0*&`ADK7I5ZMB&gsqRs#PdX5%82lS`s0C7-1W)PHK
z`l0bK@z!6y0KAWW;|93*)#n@r%_05w1u*f~pP?U^9nnvC2V8*O`T<3te*8n!9o2uV
z!1sDg|CknG$Mw#%&<fJuR#M(BSnntVX^8$Q1N;g7l3MgvsJ>4q9ER%`pMf$$AMyao
zNPRxNOrrFm4sf5+-=-I2v_6Nnzhm?hXsHpaFZ>rV#p(S6(XvE+7kAX1)@!>#c}5>S
z8!SnB<{{w8`iocSN5Coi^#u^m>YZPL`<y<NW|*n^esrMbyk5Qx#RYwe0w!tttJLe4
z^xsYb&1L-=+BVA2AEHHEroMGgIJ}|{{ujknz0m`8S$dI<4_wplZGq6P>s=-xiW~YS
zwApb}AJd;^YT0^!I$)BkZ%e;7&(jyuW_-SWT@|{dK!3U|q}%$hx+01@`iFEU73%+7
z1&2lYnLEH%tY1RM5AW(9PXpkdUb_=4C3>?JE*|Lpv<T**zANq0mFd^gva4Kg@&xXY
z{`oZ&_6q$mEfA0Ofi(12>eY0h=81mNJ1DF5duO0aYV^O+D(abj1Wn4G>qm5l$qRj;
zGo)I5{|TUZsc)r5uf5Xi_5tu(&(Xs4jef8db#L`0bY!khzm^*KUcZ?V<sbB3Kci<p
z+V#g=0Bq2I_a`bp=`}Q)`>d~~Ev+qvH}n8G8G@^!bT-7(7rWJPb|%{7VpxM;`YN^=
z(q_YQhe0+EaCgIMO0MlR+@ox?hv93wt#%nstOtCzVJfxL)1X)azxxbfl+17#?9%SA
z*>4DWfhZ0bSQ^<58fJw->1B962yEVl+dsq9$8fwW@V<r%-@xx7!+2WT95#5;gX3pd
zFdq*64Rtga95MXt0V%-nkk04@8tT77*hdWw)UsoS=}L6-aYJ1Wq##2-J0<Fa4XtQu
z7-IPR8>AD4)^xlf)KHj-V8RRu*FbvG5Jl<taKi>#NJkiY(1JG7FxnruD8sLFA)PYx
znSjuu4O1wm9%BegM-glIyaez#!wi}s#v3x|Yf3QuFdBeF!-@O!{GB$e?T*SbhJb^J
zJIT=Cie@Jplxt9=7@`y~Ics2PZFSBtzbn{M4X5aA;CaIb%DG-Jq%44^G{cP1FiAJe
zp)IwGhG0K5;*w#O7Rt+pkza#4!%)}{Ql??pZ=k+n$Zth6wX25S8-d6&oXbSzHA4p)
zOs*SNA4hv{7{b2<%}qlOXSm2VJUs!2Ifmwq2`R&w&Y;OPSmvNE&(J_q{(QrsyYN(C
zsPG2vwjt39<sHLs{=gL)H1uvOGAs^9=NB8aIPYRt+%-hd&-w2e?$LX@#BjMDHunun
zjzB6kOv^zq4-C`C!{niXr)~8z!?%-QQf@f-45W_?KAlikVdz1C$A&g^R^+KcJs*};
zhGz5|k!r)x3dB@nc(nq>Geb`rFP<A#k3wO8VR(^*X4e`{Qqt+A;j2Dq(<{SR6WCrG
zx*dUwHwNFcaQN0RwGL99p&1<pt~X2zf%MM6EClYoA%7p(J{Z=~OZ=lD@fb`R4Aq-J
z{mC#&0>7UP{?E|OTa4XR`0kvHEw94T*>3!CG=N);GXzw+7?ZaExXt(zO$S|#QF7F6
zHx8v_qMK25A2d6RooQrpH_j~qey8#I7)0S={Hhx)cNt5jL)vYeMF&#$7=L{O%e}@<
z)a#x`xBduppK$^GB?^bJt~ZqXjrIpLPdQ*5ng;wq;}=BgWvrp$-P`!t1(J`kIW6LR
zjr%Cae#jWv_*(*FMF{YI#+&~D=Wh(8<77vSy=YkwU>rmPO`x$!9{`RTo9u;j%y^TM
zfya$EX_6IW{AWG7IoLSD9sn`KSUMTv3FEhvpA9v>9EKvy=yetNlSY4fRKtz0&p?VW
z&ZN^(k;WKTutgbre?r|Uqn0{2+893*fyNl~X>&E!82uaiBF;GL4XERdmX0VAjM3SE
zCmMf03=gM`y_?goV9pqw{D4m~`qu!TY-H(|aVbWt2%59TjdV!$oYC_$id5s|djOs{
zwr)HvVr)rw?nR?W36@L7?i1ngvayg>h8f0UIzE<ZjGPSVig6VkJ-KQes|IzJap&J~
zd(Aj(1MOQ~H*U3q`-X8=YeaF=sL6zsZR}eFe2&q07u>gu>SpNfT;nuKZ{-;e(Cw9P
ztff(}z<8rIq}xW#ESTIe`u2xOq4DAGkcx~0K0_)tstXXsU1K4=H}4t8&@NVqaYnTS
z&)<FH>M0OQjZ6N7!v{tm`a>)ajr(NaE;F`o3VgYduSdX-jC&WrQ-x7KAKZ_PZQ6sh
z(x|2bDNl^ebI|&y#=I|qt1{Z@yjZpIARTR}G5+lX>6y`!)}GIeKCy`6g|TU0Q0r@r
z9Sq=pY4q=fX1_9yb%-09**o-ruHMMENAb@1oEF*djUPJ$@WGgEK=IKyBM5Oe7`-OI
z<dg9w-AA8|o;U)j*kWp(hr-G9K?#4(roYYsu+_wP!NkQhGXc15rqH!8aW!S^g2{H1
zl2&AHrX-q5?=Yp<`-0Tnw2jVp>@?LDz`chltT$+OnKEKg>^8BqX}8BTcp{3urn5BT
z^E8#x*6=>li|H_Nn413sw*981pHO$eWLkmZplSCU^oW<~9*wTvrlD(L>0|QQflfPY
zilo8L&lK0%j!J*iS-M${m{REcVu0y%YxH)Ysp2G*M@^|Oz<td0U^5~-ZYuf{Q3RRp
ztHB*?diE8f2r=EH_2LOr*Ou@bY8pv9wPB`FG!-~$x=SZ)!%crRgGq#G1Z9vSO?}Tn
ziZU&&;5*}?G94Zan`qNMYIcli{x5J5Yic?GA;y_D(402jl;OzwqnW*m&Y>ikzNa*Q
zvg!6Uv?ayl&Y?JK>Y_$*&NR0KMXIR-?Mt6G^;?AEg30?6DAP<8v~Eu~^{2Bq7fsLW
zV0p>(A`EqxO|AMPh78jmO#sL=Nsr-+xMFHaN${(tSjs45nI78d@a{EJ_z<|iZt6ul
ztT#-?A3$@{WM2-NY}2pdC~{2qDNS<Aw37C+a!ph7V3}vyMJtYc(;r#r<pNV?7V2)B
zg6TJ>cTDIyJWHmZX#rkjn!6Oi6q`Q3g7U7(MC+G(rlbT)#Fm&s{Sn)J({h@umzt{d
zaR0#6sseQnO#?2XC^H>9jzG&zMoKe2GEJuqp9<3nI(qWh^y~sct28ai1?dx0&z*4b
z)O3KR995=;^lP(flk-QouQAn9qV1XK$7is7ZrZYpHv3+fhCT&%t?4J)k$!0^qnrD!
zNt}YF)tOF?0>0j~<sjJJnJ%A2-Fwqa+U5IT`uPCZKAI*EgTn^X=Pr;wndZ`|=+CAc
zdU<X!Zz@DvoXq>yL2@=TJHfKm?C*f&V($Gr{g7^(xfP{XT+K&3fZuLbJVP*U<{ze_
z**nZ>MilPm*eeKlr#U?xbspw%bQWTlc|85Oo!#awrI7ZRQ)#H)YnG3KiKn@oHeU9b
zyVF$GVQxjqu>I!FzHoHF+_M1g51I#tqp*9KQ)nyN+bqt7Cm(YarO$lL@g9&4nU!=K
zA2!c!0X9GLC`u#vo3|vw<cPTqC5Hmcvv;B{(3~C&wxi}KdK!+IZ_%KB+#Ep5`5<$@
zL6CyYU)+Rch&eq1$`j_vG)oS(n>#jvr!aFhy+ux%pM=3C+&pj&Xd=v6G}DVTcY1;%
z%DkJt%2VdOJy1lO?`}shG3Ejmeq+tnuc3@HzmdW+-kd;Lmjv@AnxrI}zq<gk)8@Xt
zVRFX&swZ$s=Ay-jDcNjqLGR!cbGyMnoHfU;1pb`)N3uyZ*Q5Y(-Yj%QXcx>rG`~$V
z8>0Y7H{ab2>7sd`4K$a``II2PY(79|pfk+P7r-Rbe40|*SIjj*_ztd`|Mf!@S>{Ew
ze|gPZc?5v#<|TH@kl!#@(@N>4xyvkcO}4q{7)W!>Z^l4*%lr%FfO5@4RzjI)c8-Bb
zzPVP0x;y5T`{Ak3TuIsFB6FIEc#F+n6r%2~IeiD*-!qR}3}uNqt{WWQH*ccbs?<Dx
z6>tyCHdoqgcxZmU2|<;aKU1Ek-0ZXrz(?i;I=@+AUONiF$7TuLdX?r6#QntVIvjOR
z%{%nqt}=J?fJwEvWdd+DX7e{7duCoi>&xfnRDVSO!u&KGfLe11?RLL3U!%41EA!t{
zwihOf=AP3*^TwRi1o*dReFE@x=3Pe-V!gRF{VM65`Q|rZdvEUM5dUdrUrgbCHqX2d
zvMrWjO(8j1){aEWoGn*2fO@N?s|9hoSa#8=iEWl?=i$KBViQ5R-BPj>lx~(>`VG|%
z%S-xwh`WWSJ(-=Bjsb|%!_rO(+%8MSZ?N2LsV_ocdn}qQFxhMAWq*&-(-L|KZ2K&A
z8$si+tltQm{gyz=A{?;P`#^cnGQI@dUX}^TaPMsy9t6q9vYghczLxTbFgauyNVCPm
zmbHE1$<Jb<@zmcUp##T9EV*wX1y~FTfCpO6(^21}mY(?WHy$xd#7Ed1x1`bI6J(i2
zf7mA2!u5cQ5Q|-kR-CXn)0S+gMMZ;8m?e+avnMTylOTm##P%?Wu<WCqtVoNs0c25@
z^zQ*UW!Xk+^JvRIX)uYg?3e}4Sj)&zDB~<^+OSjbh*^s4XlQ~ZxehjomcNlVRwP+k
z(_ACjvW#-)DVC{sQFqqjPJ_=m%X|%rRLd9irJc7dqS^HYi^1{i-)8pX17LXB;za43
z49mV-u*kGbsYaYvEEO#wUA6SwiayA)gsMPt&GOYZkgi)6(#f_PmaB9O<))>I((&1r
zgf)mE$8u~F>TX#EzXElx<#<!L%d=GciMo8tSz2lqSRUpAciYl*Vg=alSccOta|<o^
z{eUR4w58Qjv8A;K>h4-@ry#U@7MFu?QDQmJ9>DvSbyq=CYFW7$9rM8Q;Ah9p%}woo
ze?zLU^rJ=iW6P)6FsZbxTLR7}mNBa#J+<7R)m@ck6&+Qqwwx4D)L3d`0C;A}x{a`(
zTTatqi5Hf+b?{ef`Ta2fFD;vG=!#bsGp*HLTT%<a`NrZ!kN#UrP#1(-XW46~w?Mt6
zydUCyXBn0Shwm*em2mOF;>d@KkCs++maM_D_919KS(<yn<g?`zZMtl+DmS3c$?8Wx
z6nC~3yoCF$)>rg<9T#g~E$X&e2h!xg)w*dO0Nbq-=r^!#*1vAU{SNCFOYIQdtshSz
z;GNdBbRfdRYFz^0F6+)UD0W-L;Q;QjCgcOL*Sh&WxIL}zA5pi@T9=MGhxNl@Nc*jJ
zddnWLx|BnC(0c0?Brj{5?(pDk?K%>0AFGVgF^8?r0ceDu^^=ZLV*b__y@5DlUHu%9
z23UWmr!UZ&Nh|xKR)LN=9J6N9spaEVGY!!}))n1Q1X~R>QioW_D}g&<?MCT^Q0w_w
zAPci5Y5_lK-CY2O;nqspW{I#We?<{#Eu`JqC~MjcS`wVH-Zp_I+M2rzE@G@lXpD@t
zE<AvM<E-90P{dmg&<~;#tVKn@Ct9QB@O0XGh1L*ftjB5Mk!0;bOXFm#gZ5BTtPQ(i
za@M+%c1_M%_edb6T3s7pa^8B6W|tSNL+JRhJ<WPE9F0l0w)hvoi`MUHl)7Yfrabj!
z>&{{Dn_(Rghq_FwhJH1B#rpnNm|V4Xr=)q7bvB)Mxn|7?h4Q+!#Zg3f!@AfN+&8U5
zC{dMdojMp%<X8{T-=4T-t#m<m<yr&V!9$+idd3Hp`PTh6fhe#RQl9&^_00j;+_7Fe
z2Zx1LBjqEDtX*CqiehU59pt-ft-k`mJ?qeDz)P%2L2!THnllzssnzo}VtQcJSAy)J
z)j+2a%d7*V0VubI&_MLaI{GT=Dy-VCm!f=ZjlYV@O6xqwdS{c}DH1HzR_!HN)>zZ}
zfclwra2QygTNiAD^uoINAsSz6y-5$uORG2p0lu<^(=`0G^&d)>zp?hD4ePho?s7z3
zXI(!5A=O)dm=8bitV6~E@ZLI?e)aYNe>?#(e6qTK2kEo5y?q5-Y_aWX0T)g-zj)xC
zZL8?m*;ZTHXE=1Rospq#o6VWhRj#%}l)2w-ldgf%&DMPiq#d@kD*$k}oyma7PFv<1
zIP|bhrr($CvSnCdvfI|1QbT)eRg{n0Ya2<2wLNWZXHp04vqg?XdmXl1nm_Ef4fBI^
zz_yW=m<MgWc|_r5yS5Mxy=_0!tKP?!ML*8)wGD28W*@S-(g=FkHdzHyKikYO6#h0X
zCFzgY4wu3*z*apLxIo+bOt2iaX`aE+G24(s^kd!Qw&lOVVUVr318jnA{b^@D#8%V`
z#R=OSI@%R#n{Ndo%oahn<4M~iI^q#-dqEFlgl!ouj3RA*I{=TeP395PDO=uOu#C2C
z{R6ld+a+35#@bR{(NA%<54{mZysd*99q&%CxlvXm(e{+m&8KZ2Hi7Mot?o1MNw&gq
zkdkeK4xvb~8K$B*Yn%KSfO9r~n)j#L_84G!-qwTu#>NF(S6W}C*$z1%rQ1^1!Tm+s
zeVQX*vc*$`mu>Z@;6B6l6?Ul<^D=GPo}js6WADKIRh#D?XtQjO%i!snO%VXL>$b0G
zSiWIPp=r-e+aSuTW&b~pt~)Nv>WiCZmX%ss@$S9%GFzrL%(T=pwQQP}X2X`%FY5)_
z8=0cAMMVU`#S&x*B74h{y+LFvApE|kzs~2}d(QWqdwHMx+<VTs4>mDJ!Ij(Gcnp0N
zHpi)`vC`%-3XE0RxcKdGR9JK9Mrwo2Xa$fPZN7+xV3SStM=;l7^LZQ$wAyS}!ofBh
zkAKkDZgY~tOdU4DHt2QQ_)^TO%O;l=qHdeZK2Yef>2E||uT9GWnCr6<w}R`pas3Kz
z4%loC0vWWa^2PY>+DuwkL4U~R9lF_d&n9pOI)`nx)5XORo2I=09ktm*VTCc9^>hVc
z+~z(Nh)meTC4fxYq%Mau_iZ-Oedh-@f3|^4*+ec!-?R;%fxa1=Nq>-sHVpb0*sP6+
zJ_|8t^W<W1wv65%XpOdGJWdg%BaD9*!3%qanD*ojj7xJ+bY#3o<={>XzY+}1nK5z<
zuDLL#_oL61v5ivjZVcZ`5OHTD&=$^vaftF)o(xA7EO{{+=#A*j$XW~wK8&W{K#nq;
z=!y1a?2V@LqaR~(5zzb@6IA^Xz&N}MTp;7*2EYU{L|p(q#;D=|Etqln5L`RXxYQ2N
z6O07f?w@4L{0|}_3@uG}DC6lXzz$<vr-XVq<6FuDM=*j8qA!vm{0Zix7)Lu{;S^)g
zJRiU9XvY62O?sNK`CrV%8OHMzaX-rt(ux$r`0y8ybBsT!Ixd!xc@UE48Nz+Qj$=fv
z2Z?7Gs0`@>!}$|<pTKyRZfqnn@^+)~BBOr-n3otmd*JV7hN~Cm@CrlT3e2kvw_>R8
zO=1MsqBEJXwG3<u<BxW9rZQfnnzuB@qxaBwjqxGfj!b8~l?KoZ#$qbYyUy^WLV#?>
zt1PJJFj5NOb}nPv7Kq$n@Jk?)$B6WVGx>}!{JwNqVg0%gU4@KAPH?G+;nRb;D`q%Q
zwy%WoViN>Q8Os@Pu#E9BUAih~d_&2`3dZtM*r{afd>W*Rv5215YR0=R@Ti7ibc0AO
z<GCC_-)3yt0KGa!RWDqrXRK_8LIdN<e>*_Nko85#G%<dp-N+rr9376D87osD+QLBP
zDIPRN%r1<!jS)gQo_59oDmm+5yuATK>16DhkG?L3m~!adjQ>&PXAfh@fW}@%T@Bps
zV|+wO&VI(XJs<;&c`twrGR|g0<SrxgSHE9enO4CR%#JeV6+(TCacl;@j5ETiSaE`}
z<W=-dGCGQ3_CDi@>oEI(5vc<76r=JN^i4DF(Y5y(#sVGOeaPTgz|At=e+Gu;7?tm#
z(Uy6T&b4;T9x63C!rc5d=GC7044rEon6Lb|yL4natVgF4^Zk3!aAq>;74O27_QFwD
z=BmHZ=*HYbH3sg?>*?S;m{09NpC|KmioAL;Pm}@8oB0wg_dd)Uufoxz%mFIP@?}cD
zgoq#0$rgS7%o?iK31H4G0SROxw1|lfV*X3<mSfDrN1zeR<Sl}w<IKcYpm>70`Uh|)
znZfUYgfLG~tSppSp~RGgF-4)^!kO>V0w2NLMB$cG%z9dAqnWSMX8bfWAqw0X<_E!W
z`z-TiiY>%2FLL3`Ip!KOefA}m`Ee#X&ojN4a4L@3PvsBs%r88^U109~7cdFT?YrPw
zBJ()q#V;~5$k9to7s_B<W-g%M{T1d~x{iL8xpY4olbAm%;Y>1<e+MLmxtS6esmzb-
z0hY$Z9ezAR%n3vRtqaqc-#!n;3}*ZWkn7C1D6E^wJXMP+$zrxs5Hg$jHces<^D4#n
zbD1VO?%rVj>Ium_W*QyD^O@?cFmaQaPvP<cW+T1&ZZY4XYvhH@tF#^!F+ZX=XfbnB
z0R~vY{453v)>7u%6t65}HXK4{IrH0LbXG8Xc(7E-9I=6kD&}t#daY(E=z*(YK3@gJ
zT4pJ|>~1q>{>x=CU!w48Jv00jkOpQE?e`m*xpg2-%wx2>yu&>0i@s)Nwl5~Oh4~7F
z_gk$@ZaiAsn7@s}ZaecVm5g;Tn}cDglbQMv>~=Btbc1v=KZ${dJ<PcE;Ch*z?_g+s
zOo0s3-Ouzp0TTmEY*F!uF}(!f?lLo|ly->uni<?ZruS3O8)iO5FU=9=13J}>GOb0=
z!J9E=qzYu58A0j63Febj**D3YxDAc_%&VKhJz)Oq379G70Z;fn&2*(R{|xgb7l=G$
zy1a)$%rf`e!TcQaq&<i&tC}X*j<xnW3?5;PUxWpF)~lbvCnwer1q_{8v({;Jy0AX-
zfrcyV6{;$5W3BuPXzr|73Ve95YF~k(C##kYiC(O0_o3j;V!R3wAC_hb{5{Glrjws9
z>svbZ`msKs=iZ-nKNxNYu%@*z7|3#b8Yn@mt@M*U#+r43dN6BoIYn!av;1}N<^=27
zW*9ul3jH5sLRd@FK|)!Js46pz_2(sMgtOjz6$%loZ8K1aWbNMtg(%iOio2X*^-vK;
zG^>Wzu+yx^X!SV5D!&GWv#bc(K*zAMsdoMx>l@0E#Ihdlqtfv6EGeCh<5(GV7LRB7
zQt8YERsq$XB(Rp!S6mWVcWJYEk;SC5@g>#<E1bE^I@1lwE3DP@fv2l1Aq54KSP$s^
zn9Lfdja>>WiGHN1tf@{&rm>byz|b|8ZUT+ztc>=>c>Xe2G4z+Y&Ke4Vr<tq=li;#g
z>pp<pY}OfC?s8bSDBYFIlG54u25aXdK+9t-eguvAtZ%-9Pd8aNsragZ_4jKKxy34`
z_f{e64h8y)Sf0NErI_^@CHYHOyD0@x%G%@td)6}6LJrt+*2ue%sbGCVvFb_|hq7i>
ztR3^AQO)Y1d9GpQ`~#6%mgh_8yUp58LHRn?5xNpp&uXNjNdwDS2Ck8%q&QO(>#!2z
zy~FCG>!i)BM`?@S!YZr)*UCyE=r${B9X%xNtc<sT*1>Wa2TUhxNj?;NSc@n|*US3d
z0i=($d<2dCteiH$46rnGHW*~Brz@CuS<g@r)DY|ZLWtaB9o&uy8fJBU4Q_<hk_d%S
zR#*i@##nLN;o&&zuK}2!U|Ij5Yi*M(=WCF;&$>XLVt>GTY8^VKSUSq2PqPkE{%D3(
zip|l&hpa<%H))pj@CD5C94p@uXtwO}UJyIBtP(yQVc)?KVWB<y?i+B;fxYtyKs&N`
zJ%oZ2`_sqK=*&L)DMVb@+pUG5uI%J@V9<?SPcIU8cDf_{_F!*Z3p7vmhc(dfVoT|4
z?9E<4%a#xOB}!!+Wj{$FKVSBv*U;$4o>vVpe|8uL&IGWdXk!}4{*7vAgV=?%13$)&
zqg5-I9h?Eo<Lu`HDe`xMeZm>Oon%jb1iK;d4cMXVZ!Tl>VeGcIpcu~n=?RELu%D$Q
zQ6yVxf{7@$iqfd3*isqvqS<%psXER6dkL`5u;u<Rf0n)G3+TnL-_C^>=h!co!+b2e
zmENM~*{KfnvF<qbVhWhXv;U%Mz6<Q{UxH5w>^w@1C9+r1nsSl-zeiyA68qvL$Yu5r
z;vx&Luv3r2(pC1+6|j`V?kj?1GFwj>^c40_l|V^l=g^Kcjs5*|AlKN5&p<Do-A}h~
zGuZEJUx4TDI$KLo@l5tlw9aL*_bvfUHv1Jh9L`~@KS5(I`wyzlxxv0eS2Ob1Yv|$1
zXCG*Rzqi<B4QMQ6KmI2`i`XC25w4ic7C@ndT|=jdQufjkaAoY0A29lIw(2!VR<OPN
zpl7XQU#ClFRqXsOcu~zhN6&8!yWI~aYT0Y(p}x(IY{i)B*qdnoSkIPSM_&W`NCXrb
z*}v22w2AFcPsJVf&FwJJ%>Ie;GA-;)29Q>^0~<qXW4}2Cuy*!0RP@!s-b1_kPAmJ%
zx6s+eUicln>1MNN*gfnv%FFk%7w18vkDWoarv2<cmOx{Gt)?vHAbXC&p?BHttI;>a
zcBS?49{bZwpbWF~=AbviUK<6JQMNbj5y#lamZ5Q+ed$M7m|%}Ag~BA;+Cs7Y`|OFQ
zfcAjBxdk#)Yy<73r`b<V18s(#L_fBN?5Ey<-C6d_H6U~BJPR6aIW_iBu;cu58VW}^
z52+%=p7R*RhaEWH-mvS)F=Ru;iIW=$1!vCuRgiSy?4UrEE9aQ?15h{4YN}>%=ln_G
zd=HM(5pbRyXDRx;IKt&<^ya)le<mM}6Xm#$ay)DS>dRUB4~QS<v9Dp*pR=ECB?NF(
z;V>V_8O?-x5a+EXaK|_f-EbzDv!x%?b(~XAo0b!tbT7)5oaA&&feqpO`aU#5IfJ(V
z6UO=ABam>;OAnwC!O55hOOYH;su_*qL|=r5r#SB}!URQgPDG&ZH0Sas=sUw{7J!`P
z<WYnxhU3dZ-+9jVNSKe~h$;FN&-t5TE*Cgc161&kz_FQ+&O}blO^9CPyg)gwOPt<e
z=wIf1I3KQE;fTGUc$KrJ1A|H8MA82{N#+#N&{8<QR1=ZP`RE&nq;WRU_h7DZ{`?7;
z>6{D(P%=1rN}*rpr0j)WCg&1uVX`=?=6QJjvN==q#O83!-msL*x!Qov8=T}%!R2w9
zDBYdUdE;p~e3SDQ-CZf*Owz0U7N@ftl7*a|f51c$=c`LlDCXE?!%_(+p$M3zoX?w}
zSH`hWShJk7lS<DjIFYx}SjjO_dfr;a8CwBb&G|PEiZz@D`i@8~=bay6_cllF34?W<
zNqW)ObMmOZq=A!6U)5{mxSG({#A(|I$vYfoKS(p@)tw+MoS&%fww0qxf<hbT&@y<~
z&bjy}6goIsdewAtW;em#E-R-q2BYZad`l;T9!?GIL3%lxC`j7JS(XG#{hV(aAv(Z$
z-W~dboR6pB;a!eS3vP%LR}YbUoS%*0hB;ryW7s2{<r|<d%2`JlhcQmhXAl|Zr1Akh
z!NIo-@ZfQ{r4YH#u^ywVa}PK&y3#ep`IFKa)0{wxUCwa&={WX~Bf5@J%yR6~pg+fX
zhVl@$TwOhg9XEwGtVg(ee}+%?+#AOr;=n!Z2+onakB?zHaRs#IJ9A&#0^-8;q}9@u
zn@b@*H|}TFGthVE9&>=FUfik<jKZ61Lv?gMT)7)yj&h%-4Wuu(bsT+uTph)|{JE{p
zPzd1mcY_3S2loOch%2Wf*D<bg4@MZwy`aEYj&sK&(RYG7LB;SVxe7{chj5dpAQH+Q
z-c9enFm7cOoC@bYplD?T_dXrEBe^e8@m3T!=n521ac|P0JDR&;6lkZp3<{r};f}YV
z?<{v0MVMo_^WOv5Ij#d8x?{Oh`{4F@?s6}n#BrD1g=_KLuU~+_7q}a!1T2Ajsf-H#
z61kok0KLe~c?6)BxJS-F|1$TSC$O(@V`<sC%Kd69%qMZnO#n^ia_&GRg<DCrrm5Vu
z^c<vdGw8Q|jr%QqO*5SvNO_11Zr>(Yy3U<H1ocerS^CXoadl5aFPqC~rf5$NcRv+M
z<#J!4t=kQ*ks=6r+)dXo&-vWlR3>wi+vN<dfIC7tvs>IaCnywhRlk8N;;xj!(PC}|
zee0%#`z2+<O1Ytp&@1CUAg-MI*$JpuaF;p3(Ms+%iosNI-JgVrwVFHS0+|}_K3cYF
zxjVN*<~H}re00`vIei#!J=cXUur_diu|l$uyVwV4P2Btlh}_{OQ`)_m+q?n8ZsF=4
zK)sdwivq5-aXsh^-Oep&f_ewHY8@<ea+Mb#(#73D@s@5YccmMqric3+#maiQ#}`AU
zkDDQZOh0$Sr)V7DenD^XLGHOa_<fJtMQNX5u6Q1}5pElWo<_Mp%>r$V>r9cBaqc%!
zP@mwsQVG~3cbox{``kkm3VpymLR-u!E{C?Z(_HIsR5&}seS|iU54rL5k*is*X+Ovu
zH)kDWY<V*j)U)IHtiULa@SLfT+n(o81sDgOg<}7XJTYyLoOtb2HRH@1qB{UCycf$b
z39h^ychKj?i>8>ZJFk~wBp$r$l#}t~y=A2xjTbMAqUYW`9{uKgc)wC`?I`aEZ9IK>
zzEnHy$K$>ZG=JXb|3D#tcbFEMK;HLMixtG%N(t6uyuUQ)3+ByHCg3>Fehhjic<<4p
zeUkSK4Jm}Tkp&XUn|U81VZ1v}DbN|tJGTaG1aIICbVl+fD3=t)i=}<WDc%w)NQmZL
z_FHyxh1H%05yRU`l>p~>+jhaFSe`2#a?bOHDLEI%>!c`aJWoTvfD61S$_FIy4D?1%
z<ZUv;&PCqCYLH93i60<xnYZ&PSiQpYdJcB3^3H@nJ&D(R0fv%!mQ5H~3NK%aIZx$1
ze2+2+X*{1puyl>*PD!V99+!&QGk8-JF1pS$Z$V!s?`#G7vUq{JVJVyEl?(kGUhW<Y
zESHx?6#+MR&VKhWqQo5#EZ|*y0PS16iMN1N$UAo%@<qJav*3z(?mq*vgcojrS}9Mq
z8Ki<&@E827<V8OL168~#cZ{K$Cys_*4X=&ffwjE21L(WW8>2vR9WRs(QqOayvseS~
z)INwb@}9E(mm}jfbivXcURMG1n|Vurg-i?2ZY|tx<vpteb{o%K4gGfBp4I5<;Q7$A
z-^n}s1w^`doFwRV^NQ#N)x(>l4}SFW2E*WXAFm=9^V-jwZ;QSGo&)V<2YG|d0K3aO
zdYsPxL%d8|Xx!r!eg!XvdCyVKc7*4$6Mdt+uO0==81F55UybuVA@?VE5<00&^0>60
zxX)WjMXV2a6NfS0Dc(4hBTw^UC?Gn+%b*L;4|&&&=$qx4DQ+;wyZSxAZ255~DE?;0
zfBq6o9N~}e1e!hno9p<CIPhh^gLCBPegQ9>_yx<L;mmiZS{oPsJBQ$*D?cJ0Xm0#R
zsMyP$pG5Hr5B{xGaGw0fg;4O~ucqXfH-9f3r+xSX4j@PQHFTlZmw&8)3a<V5!c4IK
z{H1?l5(4-~UW7A&{O2hH7Q~OHhxZtN`c?D=^BbL^f1F=WyP*^O<}K(u$#>iWE`%RX
zW$K~)&`%*5#vi64j&T0oPH+)?*+qaw@&_)1i{h^_!rm$V@p_0@qxtXB?VQv67h8aR
zhTr>NyoA4(o}w83>V+WZ_<zIzJC?tL&KT$Uzf+h!j<2A>#Pk1Ni+Q@huccsi0^d0e
zmJ<2j&EPL`nID=8^(*{?@le0Y|G5byiNBAQ*kpbZMQ~HB{P*b*OXc@>VJ_47cYM)#
zjqmpoNIL(c0gw#-)y?qxI=}fc%xCh&wA;<%^XUFUHvd2(29v`dWrO7M)9H+VgCG4g
zyvXBw&`C0%Z>2cNO@1eRF{FS$Vu!w4{5_NuDdbzf`5&;0_}+9pF6QTcip~;#^q=sp
zl>dVeTp54kb8xMk?@wpX3VtOO09Eo!>7#~K{BsnTsph-92=g`kP}=#|@>l(W(ck8O
z*9^=$zLs8o_53CZzBKTs6hLX@2gZRk@k6Z=VBg`t@)ic#%(v22&lbKXg(zD211_-C
z#($HlQQP^yGT>7OfA%IwCx7T|=yma(iy_j@AN?8FJ$yeF?Dp~lhau9(f0x2a{ruj=
z=o{caM(4^w{`4CFyUQ=7qM{-Go>nT!y~khWXBV-;+IR$DWBdbhNRIRENMwTF9}n**
z`MYBPeV_knGQb}2V-J8#@k>HLrulzS8QToM3-@;xKIDH+(Xd(mx>Xq99RGF+P;3Re
z0)S~J7_0=?5kVUzK<ou8=nvu`$f3BXqhOCU8PrLzeHpxW7Nq5axCl1UDaKWB^8rBJ
z1UdHL+y#3LQ1lQ8smQ@o;IbZQUIG?fOYs(zQ`X)`@M{P}jtZ=F*z^@FpqHheU~CV3
z3KVc1zy%4Gz75G^0(~$Vg9Y=dtT1t0(7p(0Cj?dT&_5}-se!{Gf)oqvh6*-|F^Vw3
z7D^n33k-K*Fhbx(*@8$xZzs^A1mB(jcS_(uhwErTnHgZG1-`U-J0mbs6z;5`l=hr4
zf=|LAa!!!d50qHJ<GUyna$exS8{WhTT6O~_UhwxBOu_}hHQFg92zI;+m_)%HS}ZRL
z8q?v^CBd;x(7!D3TL$m12)=dz=vBd2pFkl=P!Nm8WWlz_!KDa7g@8^K%zFToG{L{~
z0DVm$r9e=+;25Hn2t^7uQ|ooXvV%~}6x{0rT9%-UDr~a_hb-vJ5y+l}Yq<hP3dY?K
zi28w@Cph#4xO_nXl_T90d>0Q(1p+n2b8ZPf{R##P1+P*9rAT0*`p;s)(%qP@5<&b?
z^py&pr2K%jOz@Dh9OVM@Du`AH_WuZ(O2Ir@`>F(6j>D&F!KEkBS0hl-7N=HFWrx1o
zf>|nruM_OQ1iSTumCIqGK@dydz-ts7dJK(Cf-zd{?g&m(w6R%`NFl)%fukerwh9V=
z18K7glA8e9F1SV+kPgA~_o2}#*r0~NF2Ry^^mPkb`q0=T*!TxXui!8psrm%I|H8F?
z!GceKJs^0LqK<=t7xK_|SMc`+s1FHVeFkH>Czwcs$grUC2Q-cd-nRqFs9<UY=Enp^
z$Nd=0xWJV*8}|hj6byeLP*Bapl;B-18m9%5RAMqCu=s*J6#V12CVGW+A4Lo8gwBx=
zJR;mqDRO(^Bb2gm5U#xf3y#9HX!znJ?4a5XXQ6ZwPPhp7{P$=HJ!$9ZChVdNoV)Ov
z2q+%HfVEKf6z&Uyf|pS8B}BZ1W-6!m5#H~>OdJ)i^@kx};ZxRJjLc8CfL3gOVI#dR
z1BBnRzy%6#(!L-__;Ch6j|pw_&=)LR&;tGA!sQg;J|PVI1tKSfbus7*5pLWE5-KdF
zTAMIo8f^r^h5Ai!EkYQHZwN1p6xJ>R7bUc#-^eN9JRiEO5iJa&W$LuBHw)y9@X-&T
ze^z*95bnna=TX(+IpOglaIr!qEllTy<@DXeIAKQ|1{yD1_8}}?5PnG;fdpX#Es}}C
z=w+C-i$c|TU|te_#)tZ4VSfw!y&{|~LgQ7T<ZrsNoFv>c1JGpQyEsuTOcB1V19qxV
zeh?0)2^W6|#cRR`<LFBlK5hWX5WX=9gV%*(IVLYtC`g9EEFp6vu(O5l)Alq+C|UrN
zT;ZBc7|RV|3RUpr2|uLpRle}$Okmy=hTzbH%k@HgO4!^IW?lejp>U5K{4Nqcpp8he
z@NgPHON0(N;7Wx?iZGW6%TOM)uv~ce3!qg9&#i}Er7)4=zE#5CXs1;zv~Pe&jZjNh
z3u=WM{)JEV!khGZZV+myXrWP9Oy^c>lW@ZzI`0Ted@<f;p|u%Yi*N%Crd62xF$}f|
zU8#V%UHHanc+nx8eg-0)!tJ!!bqVLugVrrvQw(Q%g!`y$u~+y9t<`<PA5K7_U-(KY
z=3+n?!2rsj(EmNSc2{_dCU3|pjMxvm_k_>VFJV~dy#o3p!oT`pVpKRu$M!LyeGvM_
zg&V2Xe?qv8KIA$nyg}>uec{4Qn63vx9_`<!gfo8tbXwR=(ajm*M~N`_Q1~<5cbgR+
zrnldmu!C+H+KR4HD9=u0eYgOfM?@dQ1I=FaXeMABM7?~#IEwDjYtu>e^e~9C=r;;q
zxrjcw4h2`y;W&u6iFQz^$X)c=GPvd;dg*;|o}xc#neq~?W<tbUR6_+~KBBKFx_MM|
zm0p{^qHoS)5PqUZtUOSE(QYcr4iMG;jm|)kJ>7-~5<RJfi^oKp>VXz4dXE00$3;6R
zf_XyZ5d`j}=*9Uk7$Q2k3S6j&^(G94iLR7DBwS=SiN*-g`cZI^qBvTnqC{hq={zO+
z^eoIqi<Z7&#b8d0nDjNbGomY0#&TAq{|1UNqA3;n&WUdE;8U!~i2_gOMT=;4juU;?
z3`_B%$~E9Fh~jG@k|3&}FkzzT6I)oiC^}58T@q!|vU6D!{68pM5xpQr<5khs_u)m7
zs40|o@X4aDSHe<?$dAe%u8F$$!BV<N^gLiPL>XJ*({+&>eNHV?w5=R4S)$}(kZe)&
zKG@9>t+a!`xuRHlU)~UX^C!UaL^<@E%NOmYn`$>jH+O;*h{kBvZ;6;fs27U1mC-*=
zDH5g7ota|M2z~CPL{$7G43>&!D&R$#Xrnt!l#8~Xhr<;jEdz>`B5cO+sEKl?p-?S)
zk7`Y7L`x`1SSy-G0ma**Gmg-!6TQ73uGNdmc0sa1wAmSbjiSe?3cN`)bPj#iJE9CW
z^qWP8d?C{!3Rn-BR#85s-rGb6X!U6qZJz?^5OK$0qEmF74iH@;JsnHCMJKYL&?7oX
zJEvYz&rcBP6Kzmny81<<^iCQOMba&;LD9><0rRft_fxPtB=Rc9sP9=tlD$wI7Ny>S
zi4oD0M}a*m3a6!IO!N#z1jj`u(!foK{(S(LNzrP0N!%ChT#mj6qWb~hrbH>106Hyt
zJ{FBLD9QrZLy^-Apl3zJ6y2N?l}urPw&FJ_x@jl=s}Saoh^@Adg0&aVz6;ht{L@mn
z=qUar7Q{)s^1scbm`ial7xBpvG`fnVH(<g|d?^eAbr&~(13eG1<1U!+6wey~@e;Ft
zg@U)Z$qeEn{*2bZqvDu@=<^jzYQg!5=h*<oU;LGo_MHLZO~-&1DE3+m6G7r(A;x=5
z{QM{!4i=B4pz*kP4{~S=Pl$h^>mH%v;snfkm{=MGy>Rhyx@s9A9$E^6k>X_(o{SRz
z$b;S~@sm3-3DM%=CxCfc92EqSGh$;3X6>xlW6M5t#)w_1B=em3$s6Ee#qZFq==0*Z
zIgmK<<NeTx7h9-Q_JY{24=@ShQaa!zioaY7n2TZ+1ynAHPf?`dvbgRv$QAJtis4-q
z&t=24B=Iu8^KmTeX8H=qHE|*xP140GI*n(D|9Bi$uZw?w4Um~)M@mCviGy$#X<@eb
zussaqh)+(#hg|XB7oc}T%=_<hi`eiL!1Bd$hahrO-1c82L>x>%*jwUzv`;J)FQdR?
zk+>)in8o5~EBR6)UL%5Hsn}Ej&@%D&+0ZB#Pus$a3bC~ueU;*5M>ta@4vNN5s>PpD
z@}@?-XbzTY#q55F+!puIcQEV3&I^HAFJ4aJ(+2TBW#AgctLgmQBz}eVmv_Y7UjVvU
zeEu@6Pc7oU>p*K2+wO!$o7m-BXtay}M`5H6arzF}?G#_5@|!O4uc0vCEiMj+evdf1
z6$-uL`IOS^6Z^jlg?{mCrRW<FFIxuaL2*G5MDB_|+=`J6i6;s$3HQWCs?{47FZ+|y
zH6!9fbLbouZ%%{zW8(Md^M~VNz6@kSypoD}C&h=UMDe~jnSNCd#EKp?PKhIS!l!BR
z#uY%D5vSFFJQTl1SwvgO?-YEnlPq`_t{st-Q#pveL_%RG2Z_fRBpoGx;#g^2=p-3?
z8Frl|wjI!Lk-SAG4p)iJ7K(0?zgppiyQHEL<~<}o)9KVxvi}4Wyd-aZ220+OG1^D@
zNa8+*-ciZ&Fi84J*3eeTPhwBeL4Qd<-4G3s2q=~iD4ARjlpsm{SrF?n$!>~x1xo}6
zFtp>6#Mhv4LgGSEkCT$$F90S)@`)$<LM2a7X-=5rk(V+0aEY4E&k>Rt+IB`tN-0<q
zCAm-2eM&M()hyAH|Gf^$(~>8Afq6#q^g3{7C2!LXF-Gz;U70y&l}Ksp9xJ(<jL!3t
zJ1wvjC-I~8DPFRG@_!d3ZQ-z#ASvDs#Y73S8rT;lt(48XB-woo<gz520WYpdvRTl(
zDjA`hZb=dsHS8u!7Es_SMdEcBD5;X_lTb*L?3;$jHHp=3AIzsqf{bX*ka+ILBwm*+
zz6h91$zuuV%aR1qFDY9xTL+CCNkt5}TuEad&~8YgeW8~p`H2>fd`T1?r*BFki-A%g
zIeP}&ElKLz04tOnU<0g3a+Zey7E4~B^IeI=)0z&&QptyEXp~82PQgUEWJw)lDkKIu
zWGW?(Qxc|1lFtNMwPY9V*lHw=KVhD0CAwTVb6b-2I27t6+bW<?FB!-KSc7E00*#H5
zRC?VuNvek6?;S~FGWwb&7i)piCRvt2&tJR5g|;Uhl21pW-zm9F8O|<A_)&;<OZ1f8
z?vWh)7moHyu27j_pX4nn^z4_6<U?UV(nI^>L5Z>oeRm}<Q_N*Z;;|AU_aqPKBF-@W
z29O+)oN0v@qmnc_@{UP-w6xh6mn@5h!3jxH49KM9^CR&4zNDRER1YLy&@pjJ!f6D|
zv_yUiA~TYo=u<=wC3!Ey!&yn>4q(qo)?J09t#mu3`0S)VJHx~g>5?ia*h{}&2hKry
zmjwk!=^?si=p>D1Q@N0{R7WN9F4Dplbh=72X_0o5mOl>n-K9D@PkTs%ndtMB2GI7x
zOZsdzM7*UpR)Y9Q@$}-sllD-;!dI%IkDvHS|8WAQzx0P|AOTXj6hjJ>KK~CegQO$n
zP&g*tLv@ALV5yXryW`SL6!||PjiOWFNhyc6rXkWV%V987+Pw>)VbW+nG=@vlWbi3M
z%A@N&k<x?o(vOm^Y=inK=@TB1jFy%z0e4#J83mutNQX{A@~qU4jz}@mUv9#}IcXBr
zOvPHI+aAFTotK7`fW%4nd!sX6`l3BRFG&BQ8lnX0)e`ufD0QF+`9<l6+c2g}(nv}s
zUY7p&6P&psO-+KxRjFSbK$E0f{zPB0wC)$6q)7e8ppYuvH3}|G8v7zVye4hz0GBSc
zZi`1}hI9)>u&zrFQ6?%=+A;@AS<<9e0Fx`d5{zNrkQURWgFNXYxghz{mm)Bjn^Ftq
zQVOJR6aw^?^wgU`DU`NSuDVG2B@eC@OJ}@bsYIGViT+Y4PY(4mX<7?rrd;~FwGJjK
zqzCACRVm%P1fo^aofLMjmP+P;T_fG_CrGXIQ@Ue!Te@x*B6U*Vn?S3V22#kXL8_;C
zN29cJIoxiN28hsiNBSfs-kPOPThZ4d{g-~gt<r`jK(|R9t1-@YX~sP(*beEfEg+rJ
zZ8p&FlI}YI(k=C&?PHIWL8+i#>7rVYKI!kYc=k(UXdg5n4f+y|gVL9GfV(R_ZGvk<
z(y~~9-IIPoThd{vS0A_$sbeKDN2Qtch8>eSAA^VE(nV!-@nb@&NWmy3r72s0c3=7z
z?S&sm*V1x1CG8mlnU;Rz3XK`*=LT4MDBZpmptDjBx{fy|{fNpjZDmthVB5)D8o?cr
zrO@+dFWa;e19gxU)9b`hW<xneC)pcRAmA*^{hiXKF0u*A6uQb@r8;pp*&ksLb(cL)
z$7>JSQA!<q%1*xxG%uMg?SZ{z1J_~RM>d4R!os7nL(juCUzs~a#r$MLZTKbl%R1>L
z5g?lm#h*D)W=|ROAX&FJ3>}lz)Zs4@EaPSZ(|TMc+X0Oevb_$lbW+wc0hth4(LBh6
z$^zU#!ek#cz*4x3xdT2$$gHU_A1Ral2ofdR<cYr1GUcy8IU}nVLH(?3I1$(}GIbs7
zo|6T00Uaw_VGEJ-GBxdF;$%-OhQIMvS@%h3T#zLkghqm_hL*xa*$z6aUz7!9VQ80R
z=So2?%NA0~<ce&VUUgSxDQ<vClD(LKzGPX+U+7Db=_y2)DqHX?`qE_EsCw?2YzrkJ
z(`EJaBFK<M(N^!e><bEpWXi0KkHUPG?E4=<vSr_oLNQ0yc^qiDvbG#}aYHsjwb^;H
zrQ2aQU-nil`fkcv=-^Z!+baOtEt#t=^a^F8_=_$ql6`&)3dOQbH^G(2YG|uiDjTNC
zoHCgMO=Y?4c`{oe8@1A&tx_h91Y0G0A{L_6GQ~akRwIje6n(X_ZI|KxZP|kW475)6
z^|P>4FPr-TeGM|3At*G;<n*XC$vOo<xg%pybx5-;nJNTYWFOpxLaVHXLS}8Uye6Qu
z%TfX$(ji;&n-%(<G7mZzbjh;K(C?Pbe*vEM$bR|)1MQWiQ?{T_mP}i|ep$g&KpT*4
zq~pw>%%0x<cV&gB=~*}=>(4^pJ=v45!^E)c)_#x?*%ArJsB9Z;F~?-(?LZlq?O6;m
zA-k=m{pX~tnqIN@W!A5O_CU7(HejY?B|&g)TK0Mx^k-z1l=6Nk`}jO8&B`8q6=Y6!
zk@6_E@_|j@?Bt&;fWi^^W3(>Y%O9mOXb1Vkiy-*SXdL=n<mwg}a+S}c+oEprL;(f6
z+~rf>qSHfup5pGF@^6jcyyV|f#frDwfqvaSa=92Lj>?}+g@~_Q90tx${^ND@`OB{_
zf)@eu3sj>SC?EP6{szgpyU=$`zU_Zd2$t)NXgn@|KOLAS<e3LSPRiW|Fx%D;`O+w$
zh06bY3csW<xspPv;c_23QAEf;oB?R0{KL<o5hd^b5}>E#*_4-#mNVwT?rHgA6|m39
z0~<lk%J<&_XpG#O3JTB3r|6IrD`))z?!3I@7}VqBq4Xn*m**yfyI_^ScN=Vie5)PM
z66G2SEM1g8O5fbLB;QNP{LAvkLh%>5BL9PeidW@psRA-d{zNSFljUn4LLo)&Kq=Z(
z`Q8`6rO5+mA9qc@$QfL^+}RI4WysSh5O!UjN$>eg`B#$=$&y<eo=0o8d{qMUbL5%y
zThEn8Q~cqEd=CeTdGa7SOXkbHDVBOuez6Do1@iTQz`iA4Mb+bl@*SUGphfacZ=tVP
zZcm5h68Yh)P%o9w8-b-Vc?`v@%H@xq#ynNXx4sMumGW{c)eu(6HxEO<TK)&U6>H?r
zt%RjodCn~;-j=`P1dTd*GS#%z%U`iUV}m^LA|xB-m$=}X<Re?b-H|)dXCs>BgP()6
z$i2kSYn8{+mY_{;`3%$CF0Z(X#t!*|-QYUqLt#`1(j|XL(WY+s{~iZgpZtrjA=58+
zJ_(rt`Hpbd9h3+3g1aj}*94Iv`NJ0I-IH(70DD-zdkzLi<YSb_8I>p6LVZlW!v}if
z@~bPsO~}o(d7qRoUy2F3FE68S2Rx9EzC`6hQ}X+?F`AZ_P=aAb{+=(eAIc{=(3q9?
zI{<r5o<QZnwu(Xu0N5#Z2{2tp6yfy7vsX0JzQ{q*M~k(i;`BdIa8iWOzQ|coYmYt`
z#g=WrbXD9=0&!D#3()7T2(zW@A|8tMPhx1E3dj5C^ire^ViewrMgvUvD7MjQ<*1^Y
zDi3@W(w*?aPjTQKSn^lADuiBuV#gVfK>YJ)s0S%#DQS32!J36autJ;#505Lt>88U8
z1#b}QCl%Xis~Dnqs|K7kRN=A~Y?z|y5x|5i4$-m|p<oBWi%5mjLzs_JbW@b!l)}vx
zqmNeP&^G6^V(BULol$7$TH{&8*Dr&MQ9SAa?wn#hJshzLCOxU=6-TM!AWmUJ0iJlp
z7Amc{ptwa>j1sJh=jo$mi3({eurDeS`e6Q&BH<w1zpO|hzpp4{YG7Ygq<;;KB!$fy
zU?(e7wIC^qZx=x!Rq-Z$Su#x_W<ueb!fODNm#(OwYjYWjd$hm5t_Xh{D4B{T+9zZw
zexkbgY=yPb8BXOW#^~F=xe8Vn&~7L`qfdI}Delr;fqaFW!hkmw?p@F?P~80oT#-WG
z46az=N>4?J;?P#uEmgGWLCO?Qc)&!tB3A&B3WY!2`lwXc`T?^_@y>q{O2v!$FjS)$
zv_1}*T1E3!czRor&V#`^#m4)9saJSJp|L^1rJ}S(#nd=Jn-sDw7}_1hI=WEatT_23
zNQ<JQ0(z~A#*Z+THpORu0<&EaL+7XtMOPv8Iu)IC&h1jTZvb?+!gC{_dlaj_wnDL2
z@$W+@_9=e43(~I`r;GOkins_2ZBUU!N7K8Cf^?t_DXO<X|DHlkp@(5bDFq8g6i28C
zWK`intJavJk#1~`D;}qx*My?|Md(c`(m#X9eZ@*DKYO5<q@engBD<PC1~9Gg^nuKb
z;*m3O=AoiP4(wUQb01;8<`jWn1I<=hOhFwx<@zU~e?&P++jV=TGlg;;l)t55XpYLh
zU!dot{DDd&oRt?2!)+I(k=7emC68VUZc6#H@WNf0_d7TbrR!lTSNBxDNiStD<=Xim
z-bz&w^nH|*p0IRO89^lnzRGDjY5FPuS_L$J<=!wz1}IzTQc<9CCJW|+l=zQ(c<_`N
zUxEZHLlV$;T)B=anocMU)lfgFd}|x}LX@7d@FG;%sDTA*m{LxKE#XR!Zm<!`%=s`8
zsVt^dGfHVkpVq*KArFE?D@SRIdRqBCy^PN&@6!(Ztg?clPch05=+%5qX%2#Vta5iV
zxJ$|tuS4Oo@~{i$>56h)GYq9D{V4m8sx;G2J<Y0g`w=qNm2wJlWGXLEeN~q7vER^H
zsC1;tkYeSr-4H2J#!~vARJn?N-DS#FTGGmuL3AUmLh1ZDe5zD7F~C(R1L;6gtu#?U
ztya1914!Oh1_oj(>y+o|WL&SjWDk)BrS+G7fHo?ZRzdWRvdbTqnw4i$F{T#fvs!r3
zstl}!ew*@RN*{D6YtKQUQ+bkNlwHc--GJ7uG||qlM_FqJ^<L$YcwqM_M;xIrpp2(=
zc~H5IVrO@i^Nyo$NO^#X#(T<2E2U6}m5XVC8&U3{&Ge`;i+)LC%00>G8&{S_fSXYM
zOfP~-rNjb9?<*tu@acha;R#IXlv1}A+>CNi2JDB*ZInr!Rj%xT<eajvA1Jn}bOBK8
zRI4ZuVXx}Vh1(9QXMd%WkfSQ>JJ@wn9r^{tS!MFOki)XdZ(*FCswg^Yd8t^mKlfHW
znF4!9Rg)C<_f;ij0Mkz;{v06wDk~-A15^bqAc3lDl=KKzIZ!$Aan<j1x;UZwiz<Il
zs;<&E`$JSemH;eNWlQh=2$gRt#t^AW)k7poRc-wUt*2G}bi3w^>MOdxdRFzm7f7t?
z^L!XQuR8E8%*Ux#=R-0<WufB6MAZwEaP*?eld4UwsOl+#eN~k{4v{3)GcSNkRT+yg
zq%>9dSMceY>N#70U03}?A^l9%+Be~SmMVCfYC5u2e?`Gyj%twhF1e~Q`hG>eD*7xM
zZ>s7qf-6wH@L!Zo^&y4*3svi>-m^%x^+`BWs>-2@EM=-DO3;<7#wm7Oq0$LqzEY(>
zh?%KUeNF+|T9u^<>bF(5snVxTHF1gl#X_Sh_ywRfsS>Eh`HrfZsxVqrLI#{^Q`t~h
zpj}l+g?AmQjn`nJQ#Jb)2HK^X3WWK)DyJAU4yhRF5V@y%loqXFl`9pPj;MZFioQ`*
z83mNbR1FuPFs>@1GtPu+5$4{ya8mU~BxLTZTvo&G16B7b$V{o4!r}0=s+|e68C3{{
zryr_XABBlo)q?jx=2SkktFl$^JBXRJQ|tTCctkx&`wDyYt^ELVP>0Y>bVqeq4aVZ6
zc36i-XLSt4J6+VJv^BN5sz2L>PB-<BF&MqOx{Qv}9%@A!%zLUYc>~)^o%s`pxB6K+
zo%pH`Qwq~hJ-H7e{_3Z$V=w{g4vHKEs^`_AFG#(Fl2XUiHWbhbR_C|Fr{ij0+Wv*8
zzs-W9q3Um51qrjNpP-0vxca;Mn9>Nfg0j$&>b+OsMU*=H4A4%gf25MNXtjDBKu@dt
z=`%fN)cOyhe^!0*X<)~ww+sOLocia}K#5hm(Q7kKov{K6@#;TLf?QDdQ^YVq-ChCc
zMD@W$h+I^^>~RmRSJdrPV{}!$n2zvC>S(G5O;(>?4ofNO0y^HOsxMGVBu#zxRd{$!
z-J9U|Pd?N7F&i_JrQY!p(6ZH~KVS}X)b~O`Zm2(^{LxMIEFHlM)Q_eC`j+|+f2bF#
z|BQe_kvca8T(Mdg2Za)KXc6YORBihK`pVR6*MO9(PtgmuLfumW^-A?ibS|z^duTwa
z)ge|_&>FS-XPBTmHSaQ<saHRK8fXpbC<;6_s)O#rM3eg6HVm*u{Zv1=R<)Vlo^9$=
zQy5aa`fe!HJJhBjnD11tpdy1VwKNx!-Rg`(n7khKJ9IYcRVPvKwNL%%AR7DC&X3UJ
zJD_%|2h5=Q4O%nrs*^2f99BOff-_@kr~mfn>WM$0IH6vdgT6_1Y#|ixt5HmaU%c98
zEi6r`fBPDJ)9Mf9=$lb%!qE6o&7caUS@rf}G|s6{(N^n-=GHeL_L?VrD6Zw8`HjjU
z95n~%LZy@D_3toHXN@m~zFjn%0s-o(`Q#Wz=%!h|8eX_-luCelXimQi&Qr5I8|prq
z5qg;&)$ELbp0DN%)m`{$yr@9XUsF#P<^nX?6!18vX?hyt4Au<Yp~v^QX8vA`;)LeL
z4A4$$9=L!D(d_yICc-uK6i$fH?EMX1L~5R>fQcy0znL(2N+YF7h}JOt0D4-plw##)
zG<8NOoYlC#1%()mG7@0tG`IaR-dN2$PebpLrhxJsmo;e=LAGAe)RE#<O{ph3lQd07
zfR?NgQ>jIY=0F}4Q#ChlKqO7mFNELMG+RFaN!MK30+OL&(2M=LM&=DJQ{&eS$t=x2
z`Xyv*e*70;Ihtn$0L#_5QOx;<rp*P7d76W?$meg?^ifRnrsnO9uvDO7)5+(SCYu)W
zLXDBC)r&N@_d>K-bF3eVC7M_EU}&Y9knaInrf~>BU%BS{YakVx=lxo4v8**zV^FKP
zC<4fB%@0PnRHrFTgPnR!6g|WZ8Wu(28#VkDAWa&Z-I$6y8V6eXnl+6NVW&lNgZ2uo
zny;MTb(>~0-BN1Tta=YzhvpI;<vKM@^xdK^&F555(yci&1=6EAVx@YGUd`$Puzi{V
zily{xUhoAO(0oIs?}M6uDL#5vBa(m{(hN62@}5RaZ-Ze?G?f*PXmW3ZjB2teNIa&Q
zCxpVdX5u~?Cp0(c^CXj+;jK`(uX*eu$OFv}6_A|LBxJk@nTHxZ?bT;BZ!X7R<}`PI
zg2oZ8=rzdLYh!ys9JJ?#KpeF{cS6KTo93r4T4AkTgps*vo!&#2yY~8X7_NubZZjl2
zwf8my(o4I6j!WKJPuh?AXfM!)@~F1+b13*~ziY&V`e~QZD&w#H@+*ulNIRN~@g38K
zxWI>CZSo2z9M`%fLh^)mmOfv5QX5Ct8bY+g*2mBqs(p;AF2b}cXu}__eTPC-5!!&4
zfflJ<{XP1kw4x`_cS`#Nr5>WSzpK!9TKgUCPS0rHlmYad*8c<~W3>zDoqJxpI~hL3
zY3tTu5b@fAF^F8y?pldKBxt9efMlZf+$Jl`U({9{hRh}HdD{P9)}AVb{uS+8pMkro
zZIM7UN&D}kn1p1l-#A=L(K^!=fmCfU&19NZMA_qOT1^eG)3s5L!KV!EA6ww>b!`#7
z5Hq!0+Dv6>H`8sbZ0)aQ@IFWTdm+X7a<zYd1cNuUl7(<MPx~sxwDYwAl%=?-job~G
z0<CW#+`pw&?1X-y_K+V87HO|h^sZQYlMdV^+DE8{yHtCGHqd3-8E0_i+Py*0tI!4{
z0jyHHpcg}`(!TvH6sol!;pk>vSfhQ0HVL)b0=l|;TYH<LoORkjU%=FBw;qDQ2JJKS
z<80IpJp!~QZ5u^7?`Stt9I09B-wL!A?esLbR_$flF}G>2@4+OrYd5aKbaiMIbaL#}
zO1ER!J=$h^u6wmFpMnKzpY|on-}Gz$T?TeQyMuNPgW4rmp?_D)rH%KHwwfxB?`dNx
z`#Y@7qD|3=_Kp+$9o4$=fjy>`(9$!mO`uAu3GLNm@NiPQ!U5cU?GM%P>48>}5AUb6
z3Ex0(S{u;}ZpNzhehBuV*0~Zgv)V6K1A9*UIo;Z@)y<qkqn++0Cye5VE;I^__PU%m
zVbDR>>;%qH_kAtgcG4Y80E)A2D}~!#bT$t#hpxKR7MOR_&71&=yY7drARf9tic5Ox
z_Pz*AFP$~g41I5%n$Af+y4^nj=BUo!g2DLehDIRjr<->XjsCiAUx5qIsVFEFsQY{&
z^n!HUO)zmxmrbq(>-JFW|G3V770jQ|`9`4eq|T54=n&mUR4x>%do3FzO!w;-Fdwd4
zXU&Ae5xPS^f<)?0QT91XH$u^a)4Ckmww=)}Is}cgx;JBi9ivNl58OFj2?rvvy7`pu
zI<I?vEhOV~FH>buyly)cV_(qOL_jh@7fb1oMBVz=p>R>R^ClWE=_>lrcv)wcMLW_f
zy2@8DrB`+PsW2r;7tX`zlXa1M(3hf9Q?x%-r=pon)0Ok##WkJJIT%dWJyr<43|-4%
z*uAb>mX2X(>Xzw2vUGcVA(^fFjdI^Px<6>cl&kBYTZK1tGwEo|)9o9eIA6Z*#}L5W
z)WvUx!2;a}R4Z^xH%=eoD%5o>fTbc`7ah@yb^B=nFVQ{2ghHu~^BuS{UA+;mmFr$A
z09T>gxe<0Nbs>~St<nwf&{(b0E(WR5B~e77R#$To3b%DK)ah9l*6Gw#R#~sJ>j!Dj
zeL}yTM%{XEm}t@|R%0&i=oV*yH0xfA!(6oJWV9Hx>eg(-U^;Y_w8iSwje5dFm+rYP
z*zMNkQ0YsLZWVn>p;x!X2V?2eHGT%keqBW^$bhco9;U=PsQZ08oVu%fna;68x&}GO
zJ)N0O48yt~C*bLbu9PzAqq@l|XpHH$((z?nH$pL@3EfIsAtrTZJCOT2HRWv{=sy1#
zWJ(vc1}M`ynKQT<-49f6{ZO~<NubQ?-a(Xe;ha?$Nc$&S{Tv@A?DW=Nm_MRVqe4u3
z{g>OJ=%C-d3dB)A@dqTG^sDJ^gR?$!6JT8Q|Aa%&Ri7V<J~zF_4|?wUs&i=c&_7G&
zJ@wC2L)}YXMEeMD{Y(~y>!Y{-AIu+xy-RS)SAUXT>3;fBs#x>azpw;o0eV*>ECuR!
z>;+no{==uxcuYS<*X)AzyWfP~aXsG${+`e$z6Z3E`e9m`Li9yd5DC>kx&oMC`m-!F
zM(Urf2TGKFG5LE+KSw{rGx|I$?YYnDk5lz+jDB1MhtKO72260AerO>S<Mq4jp^>Dw
z{0&RV`gbVtnWFz<KMbbozbuBOH2vDgfObv)CY9``>-qG;&CoZ#1@-ItZz-jmsZXL>
z$t?Y|kHJv3-fJ^Za`fM1Q}QiWf1Osw8~UKFu#~5Noz6u0dMRb;Z|WlwAyT04SO}3@
z`ln=oDb&A4f$k!`_yZ^u>o<P@gC+X+v=AxPzc7u)GX44|p;xY7O0oM2eNjKWuhf@Q
zT}qYyeS2`#`t487ljE__Kav2pR)3a0sc>5#eFhqJu!J$y>+AjoXoG&MUqcnkdV39^
zTl7civTLh;Go1_D^utu#->#oW>4*+}K7DMZQ{POR<SzaGVnBB5pN~Xek3OAt$G!Uf
zlz!>c8+$Ome*HgT;0E;HQ+#|-Z}x<PclCw-P#@B>I^fDZ{pCV%!}|GFija-y?deLz
zsQzWzf{y854FUGJo-+nAp|4vAv`PKJ^RRSZuX-Nb1O1Csg*T<2e+14<>#ywxnbm)G
z0gle;^X-6bYZ$76q@7`YBWCi5K@tQ*_J&d_vUe~f&jQTR@a-BaG@J})zJ;i>!F~-y
zT?}=J=yWyAr+kl_p*kLD?uNg*VbH_yN)q}!4H8O4c^OP}mhm<mplyPW;f*h#e$=pr
zLg>DRHSQRapCM>9{rnB(l(h{o?4#3gpy4UX(FYkue_4pd^0>i^-VrAZ&ru5Pq+uS_
zxrP{4M*$|(V4$j{Fhe`tzYjN5OCS<q7#sv>q#>U&e^G`-6evDrc=i+=jW#6EHzrOS
z_65M1GX};xAZHD~L_s0O(A@yAa|S&{8)6Md@Jv`2o;RF&9WZeQ=~iIJ8z$(NbHVV2
z0PZIkHm-n1qT#hG;4T{Kj)1#lxPBeZTsACSf?;1V1Qdh2YB>5G^pXt4OF)thIIQ8B
zGJL)bB-JoSIkPlF_sekfnn6UT(sToJ7V6dvgCB+9uN&fSqBYa7f=<O*hWO{unQhpd
z1d?ND`3<1ChFu?F6gLd7WdkkGkiQak^9{3e_`}{be3J>Tz~I}3zFUS$%4rrF-hK^W
zMFxMW$tyPOq?byGfkPj8C^fL?gFt0g!|OJfp>o46Jw{kzxUmpkR2t6gfqs?YI}Hq0
z8=l*UVb>V;QedLipxlVY+lFoQ_o*|irzN}I@GNC28w`pb=rtNf(t*-s7|({KJBIHl
z7SL+gX@y9e!7m2(+6{+lFtQGVb&((RI}K~f;ais>Z#O!-4TV(E-ebsBK)=^uPo*4v
z2LAid?>9J|g2I47HV2;u4fXWbx@$N|3HTwyBj?a}&oH<E>cfW4Wb};~vZ#P%)bPt~
z7#uUioCVmp;pcg<H({u;Qo-w_;UT@?rwmPM=uaC$>D)78@T5G^L&Gl~5S=x=Iso%?
zhQ}!&Z)^Os6U5Fq83q$ajBS)BvNy76m*QXynnRzXQB7$dC*x}rpKvzrrk{t4(Sa@{
zxEdu?Wa(yHy3-07cjLV8A>&~zJPi|`M%Nuc^D=%(M>B8Z$uWrd7>DU&k4KGn=<bTI
zF>M|E^)s4jpX_g3{usCb<6D$;4m4I(LLta#PfOV`V?KofgN@m0G#)qhQ}p<R@q`83
zN#mnYv{?x;meK1V)aXWA+c0A?y+y-~EB*x+VZ59G>`3ElWoV2tE;@j@IAsi@v}?3+
zW+l*08zmfgf5y0ip18BdJ}TmlF@8vQ9nTqe7l6bX?e<`r&l@Y(fr~SGEC+PFaX~Zv
z)36K1$KC;(U~G+rOrkL&7Wx;Bk56EtE*ZyYM{(KMO3%s_qh~anxoT8U{vyeEd=lo9
zjsMV2F~#@_<u6i=Ht#?$%_yM)mTSf>xiFY+{GT`aGK|6AXv{LY(=CQ<V>TUptT{&4
zr=Xu}ta}17H;fue?&ldN>GEy9@eCdOZyG<Ms<Z;5m|~{4jHC2gC^WiJxkQoiHoZNI
zjX88!C^5?D5id3N(<)GAeED^lC^z1E8-u7Y{y>|CO5-fOn5&F)Yav-}HD0BiTaD4F
z9i-M+qQ(es8|^6kTxT3ILb2X>#SD!G<6+A8G#XQB&2KV#B%|++@ijT@HXGY%>2EQ5
zP*|wdSUV32ZN`dQ@UY!@isI`XMg^U%I*r9{AYI0$dgyf<AMf}CpgqQa{q8lau%<mg
z<ABjDz#nALI8Oi4;jZ!EC4dbXeSe3)_l%3(L57V!VyKN6Kihz58a39@HNP?Ak1qgv
z+*qFsy$R#u|K3~1ukF!y-^ifE>;vO4y-lW!r>8K6X=5M-WoL{hC}a1~IA^_!&ROGY
zv<;gxw#<Wut!V@OLG4UCXqh@<+Lj6pd((O<R&+4M)1&EVT44u+E~c+_XmmBrr)xNF
zrrp)(b2qKG#~gT=Hc(vM)AaN=;Ji#hAHck~$#fHXKBiqOVBx4~@)avId`$}sX!SFt
zQbm%#i9_WX0j8hc0|_+!Oi_U#(`vd&c+AA5;A*g`hIZM<O|i6goiJr=N8?EolfIxA
zV!HY`utQBxDB)9>>AjbL5^gH|6bcchiOnz+X<AYYpQ21lqNzgllqvWC*l3f0%7spw
zN^_ui#uP!(&9kOMlqrlcU8BBpruu8>i#08$nz-|(+qUp2&Xjloa~W@1PkVq1CQ%3U
z5=;g3rb;xu^AGwinm)(?cga-$0D6~A_h}1##pHkr415~dG)R{Ul1#(5;c2p|g03p3
zn6_15FsY`V`{+wE3D=<SnkoMV+)p>{3_xFoX-5apuA2hsbdYI^dl}}lOwZ{dl5NVO
z3zRt~6&(_CO)9!lbi*|MHpY@?nl}W6eAC*E7>o6$>8B)U6qpXskMx%5r}=;>GzG^(
zrpWYy9$cxZLIsD*Ovf)mq}((!4z9xV%TkC`n$Fw7M3rg%3y`cf^?wYo8q>4yU=X#Y
zL-Ym8+olz?6{s`KKLW{mQ)er<22<h~oN2V0o>~mH$y9O~Xm?Cv%3wE}zS<3#7Sq$Y
z=xa5-O>0=2$^H?HsokWbux5v;<_@qsO&-f&smqk(2=#80m9i*3rqz^i?=`(kQN}*g
z=0Nz{Z_4@$3InFcs7z_lG(#n7cTLu96mA?c^}LGKd!|Yq^oLCoh3FhHy-wk~QPc0V
z_Klfdvj^z7>EE+(ZNl^&t$mZG3<_J{Hy!YT-UHL}H^EJrZZyNvv}qMplg*gkUjl`P
zrh~K<m^C%i8FJ3_f(CBens-_60>;jKc0br7=G{}!us1Jl1aUBX9)Lkd^M^F~PUhts
z;Dxh!6}<&r%rDXPURU!vy3XuoUYrfi-JG==<~__(s;BZaPtoqz%REK3x8COBuYl=e
z799pTYCcSt$9>I7Pg$YpXD*z=?42-sQ#9hF`P6H$6k<Ns4@;ru(-dtAGjIO^jp625
zDMTX73;)1)Bh4#la~EYkPRFNH<`=8c7j6DI0DWi8TOWmbj5)#rk#lCTC+x<WjUA9Y
zZ{GMbNSwLp0Y%Q@&C5Q8rx(mWmqI4NY)e~-MDvSuO1Nk~^%6iYnG2}#vbl;<7FWz|
z^ftR{j;CLDl9_V`CX&sr6ue0>pL771YR;h(f0}tP3zFB&e};j(Ztmy>$uv(>)n1l)
zL`RXcZ1Xa2usP-g3Jd3&*N$PlH_X`rz~q@<q_|SP`7cVi+%%6;D89h#y#%v&%RD{^
zy+ZRUI`9;kOEbY0n~!C~M2WdD9)E*U^Sn6pm6>G}Kr1&7z5?|MbFvwYm1gBSh*)dP
zs~XW-Yu>gKGPljED2P&Lp3=cYy?M3}b{ouU3Qskfzkd;=$-I}YJKZs-e}{Q)Ht*J9
z@><M|M(DMgLvDk#ncKetSi8CW6-aiNZ_$I-X?{)z(q*1*#yGppHo-94v)KG9Rq^zi
z2bcTVwJo=n(2;-894v#(UGvjV!Nno-HY)zRXWlgjOT*?D&qHLy{5<L_7LJ;0_n>ji
zENTYIxcMDA$xfKNo`v~I^Exi3a>~3V1$L*+Ies8B=DoM!(?j!k47gddm@=euX3NLm
z>@1&I7eM2PWj-bK?JX%ou<Ky?i2lrumdEbEu9Ky<0-UquZ81jgVlh)l)YWpN8Ft+)
zS~{e=TmBk>h==75I=OpVYUsaTcv*7ko$76Q;tCXeEV1-fI%-Lz@Q|<NSK12uS?<0^
z`(=O2H<a86u)Kc*t$~)VY1j?2L{NGEG0S%pTL`wiL2<+5mglIP@`Pn`9zai8-k1Vt
zh^3+dmO?GXY@mc$-lQ;kxMhG2=Mk1E+G<5w{-Hxzl%<cJgHx6_Xrmf!dGlpDo1M1g
zJ^|1(7KIC@^sMFcE3g!63Hc1poVQ%bg84X0cqbf<w|G%R=z=BB3Hk|^NgG&7v}Dp*
z=c462MPe^mw$U%>vZWykjaMuuY4N&h8ES<yNfviXw<cS@qhCpiCF3AnSjw_EOn}X{
z{6%X~jwOsXS-F-)bhqM$#rba-%(FZm0R5X5?naEaz_NhyW4A2nbY>{DZ1;djktOU)
zh?H1za)455Df=6JWtM<UG?rU-tpZquCH^uDRaw4pMPIdL0j-wS8cSsW*jmf}|H25C
zF8V#zS>o%UQEyp%1u_kmkpDrX(UMvM^G%j^`ZCoW%TXEZHe0x-F~Szh>YW&UtL4dO
zAkt=ejb5$omQV^ic37UFuby;Tjvl~Nc3DCwSJ!Qsq1{}M)$-|P&|XWn4xoLOE?Nxw
zEq9)P;((=<p8G+|%{-XDYuWe-8iy<u(ctb`MrrdrZ0V&S^@yeC6__8jyk82R#w-$Y
zd)#u4HV6}zm9(#!wB+gG+LWdHU0_aI_S125#<H}q4dx$Oe(yx<tmOkgc9+8Hz8sRy
zD=Vp3!)4_z4xn9EhSQ|Gt&FBXq5H~bC=uhi(w34AUMs_sAnCpGWs1A`tW*u4@#spQ
zO@Q=W+13F)zm+4s=<{ExcormJW%KXwI&kIxIlAt+tg9}rre!wF9I0hx+R!xf)t<fg
z-kF-(&XL;AvhrcbawEtd0x|@Vy;MX*_8x+O0|8}-g2+%nc)ut9IiGva`JQv`eSYKK
zbI$$o&#S=sGFGNR#E&ufE&%=v?)Fsl1~BH*e~t=d1W*Vyh>_lcAq6w)X(1HCm_;{S
zDC1+goKG@Fwn8L~5itm#!WpNppcTO=>qP4mWBU~tjAXog5(c9fHI*RIj9GGs#4t8{
zt?YQ+zAg+uU_4_Tr9#g#8oq!p2@IF#(Mn|Wb73ciaUuj)Ln`AK?PJpz(<xY)&KP_T
z{$()wmI9v1@S<?)ImR+tN1SJ<J_5PG$bKG@*^Cyd8@b3}P=M_cqq_;XT*kUE=)BDE
zu+uTLJVxPp4CM;LoB^2v#xKX=d?Dk=88}nKc=R(wiW#Q40G2R3TOnD>_=>V!WsKkc
zhNW`G7Ag_0U^r3PaV293<^QS}zT04;nz4)y=+!XVP6JoV5WE1@b&RRBe!0rX@1|5%
zJ>#lBhStEC^cE1;7<XJC)5y5B9x_b~JN@L%j8nbfU1#LcqW1=4F<me>88Zgq#Vy7$
zx{6vD6GOn=W`z8RRx6{^AKtey`l!&jo$=#UIC_UM^%u<3T}D+H%yuv~@aVHDos7;k
z5ba`!8R+d{4BUpL`;4J1=zhRBH4a2C!<Qn7eT-G_LF6Ih0&PPcF}|7)+yLXV_t81X
z*!3z}LyY#<;l(iHUJP(g7+WZ7HNq&J0W!*X<5_4KV?0B3d`}rKBb9HTHo@3T8!QLr
zd?(m-WbXSAEhpxIQ@}ejpWh8H_A|#0q2<Et_5^WdK06EA+?c;p?T$N>LzzDh=IVa5
z4lu9PqjivZ?I+CWA!b7;96ikB(jnF(%y|^vKg#r*ht6ZnxwHVVdousG0w#_#8B}oM
z#r%${I=q<<6wp7x9HzjR57UJL)xONkF{trl&ifJof2N}d{su6AAB5dN<`4hX!7~+9
z+7--PL3_9m=HIj6MJRLr2H;LIH`6EE!k7`QFci*oqmW*tohha-H%2jwXzv)!{EY(6
zG0d(11O7C#F%OnvnZC4rk7K&Zfrw{*xE_*cnQdp$nZTT#3ojCxhv)^B#GLaUI+K|N
z6zoi4E?)*-8uK9Kn$ww~v@y(J-pIgjkjY&003?fPkBNh&bIcd0xbQslRl0jGFrWN|
zF=aC|Jkh$yoKJcF9A<kx5V_1b#h97P%!>hN<uT=y0=vTWr`$|Fa~eek3z%+nc@#2d
z&{xHanGOu7E@55>gh(k<Pmh^0=0|g(vz$54?gtYU%*Jj2E17z7v6?wViG&)a^CwVK
z%e<WjL><%E3f@)b-X`$snY9VPH89uw2-3)0<^j^g49tRwX6Ah=vA@ooOSLpNn5**8
z*}{CZ1_p04^IV{;mAPvcW~Pl9w%aS`-ZZ=E2nKP78AVU(yUY>VOLa0opag9fvx+v0
z-OSI@AaaknnF>{Um^F>?<vx?W7$Ogtb@V>(V>&&D&WB8K8@%pkzP}KFM@-%Uzz3M2
zf1)+WyyOnmL(D-BXc=bKP^#}SbHe^PnopR|c*Ca=<{CP4F~$@vgPNzz^M3GmocYmB
z3~+*J-T@O1tYeeW>B!<xxXy|7ArF%KSwHBY&4pF}IpD6WkzW9CW1Xd4ygMtNPQrSy
z&c^_EfMsffy+f=6Z=iLU<@uO41xHwi=qSQbmOTu;$5>_w9QI^Q`WL|CEWQ}To3;3J
z@J_H~zXRaIN~Il+FYDj;LHt;mE1)!x)l8*=L9CakDmIw4G6k&=)^B&w3T3rYmFG#;
zKQCdr!dQ!G#~Z;K`jx&BbBg8oC1fI5A4a1$inU}efYGeG6jG02#nI?bvv$)uK8`i-
z5Jb+f3UbjI&zcp7&a*5B3Zf;jo}qVVB5QLPcuA}sw1rD%{qh}13TqbKy{W9<>AP@g
ztPkm?$YA|4c@myMnXEKQkz}#tlQD{OtoLY(aGrHnhM(&KYc>^fWV1e?Ycz*-oHkFF
zSi8lL%w>H~F`~;X5xt`FSZm)y>k8|oeGtiKouqQqLRL*7I*V8_v<@$3F)xFZu=ef&
zuawoX9zUABjP)T0GUcq_TtF&W-*|&r#d4&TY&9#o5Tu5+Iv1U_tlir&GxaR46eDb4
z#V&$t*I1oH5NTw6cmwbz)_@Z_n^`Tiy}Qo(#uelyi=7E_i^Ze~YGFmTz~9@f4@@xM
zYG?KChVC|24P8m?tTPY6yvur-iU~SckLWWPovhJ5x*b@Ho<eswYsw86yvItSTxt*N
z@<ZV6vyv8Ix*o86DOugiilcZzA1jNpG5xGDs;+y)`i}l7(EuxUAG{c3^;@8Nh-Ft%
z@@bg0j;f*_v;1ZQF~T}L3j-Zx#Y~3i80+hu5Piz>SO?wXtPh&Nn_xAp#4qB&9-#H1
z6MH}HNu1d;DX_Pnop=+(h22BHt1Ekq9>i{J=Lf*Kv+t~d<N@|KZ-IA^y~Dl;CJwP{
zslMniTNezOBkUB~26(dD=``4Jb~C*|yx22#0pZQQ^DO*5!G32t{Pkh$NW_=TsfCCB
z?ANl;3SgJZ00?Bui!tmV_JSGc3})Z?1h^1(9L2Um+3}ZQFO2=?>vr^pv%P*nGlDIB
z3BH|TzqS)zM6!dapgM{z^2T7I*)M(yUJQFr9LQ<*LV9Y&vafytcpTe_s^R0=P4w6}
z%f8<ZTmsvi0e=(O|ImgziGA-o@RHe~v~N#g|B(X=Y3$Gvy8qJIDymV;V6UivwoLZT
z_3%53-8T-=3+!*^0GQ40`vV3qvK##Y%wd}XKrXTEw2#eYpCAt}vjg{|^9uWEGvN8`
z2HIa0uwPGs`9gMWB$O4gO<!Z4irL3qV6TMz(<uGFurl_@XE0IDUQ4y773_ciLaUP9
zEP(DR_TSUcS<U{O7VtIfx76^Wmc7Xbq>inmDD+i!!&}f+&mN+L+BNoNs<vokulNw=
zo7ht+2-wUP{0L>&+2^Q8<ObV%0M6WGdwma{y@mZsC`50w*Ytt3vWtdcsg3>aBIs^s
zr(S_f2m9b>7*i+vrC@Y+v7avlzMCzng5*86lA;ei>{(if+-J|ADxO}pR|#5u?6;PK
zJY>Ig1FHMk>vlugBlfP>pk;tvqyc=;&i;&Ye#7hmO87ixe_RG_PuTOyG3*ic^l;4H
zDEku%IgPPR)fo0u_U$of8)vsEAvwX`N7L=VS@;}uJ95lI;G8)>ccZnRGd2c*3+Dl4
z;9NNe>3!+OiF1cech2Y;h<I@9KT|mBAZN!~$Q<H?MM2wPP8+Smj&Lf9L5^|`?Sja0
zPFOTrUYrMO(embOr+oMc&e2&g;lpvTVlcj(GcRE*ew-cmVJU#KVICX}<m~JKE{LOi
z1%O~qH$_lGIB(I%hC(@|_Qz<R<cMjt5zcA;6^IDV?hznPalUB+iRAcEBqoaUm}(TG
zIgRIGDTebiEyYiBT5AD_<(zv7opGEmW`dmISShl1mNP#MfCSFyC@ds$7U&?E#3`or
zUoxkh%F$Ce5y_NJPvxZ2QaqiL@D1i9gHziAlF8w10V0d@50%QF<LsrUbT;P`3UFNH
z?4a0o4rh1{#(RmgfI?lloR)Hs%bZg?pfiuNd^v`6g|nM>uKAoJvFI%1sGf&N5obDO
z`inV#dC?lYg!A1>$dq!@nb2L%+5J9%6`Tn@MqkM(Ma{{yYR;eZ+OOe+D=-(eoI2XJ
z)p3I8iF%du(<+d9&ZZvdZs7Dr!nH;Ym)03goCj2M*vxrM$1ksQ8gD?$4bJ8P0B&;T
z;5lWVc8fEQ&PLznaGrtgR!-S|$h2{CQh{jabW)7?4#%Y#KHcTaTLBNdIEi#(tD9q%
zfZXHEya8MfCuBJ!?{hZNjq`w0Y=LAi$G;cK`Z%MTA@Y!uWdnJ{c|x(v0Zt_?&g_G@
z<{&e~`IB;J!<?6Mpyml@)hJpcoad=bW0cd>gU+X%?6bg+bKav1ae@=R2|NdG>@WCX
z9J$l!Xn+&<`(Cu1xdzHIxNtr5A?eE9OO-Zm+~(&1aObX~nhy`|*?cHFVCRk>#0(we
zhS4MZFjpam=n?LYNHC9b%jxns#@$N~ZBK6FRPc^-+vh>e3GPqy==R~deSv}cayx%U
z%a1#W)`<Sxmnae%z<r#6Rv>rWfL0K<f)3{gb0fR~59O{p0548*|7U#@%`mQ&Rwm(G
zB|VrUxIY(S@*}x6iuFcuGrxrw(cA&5>O9T8?DZA?Ig5xgS!cO=HUty64|zZ*alhRI
z`D8BZ9gq~R7ai$L<#OnrOyfqs2w&2<KHsA=gWH^lD<F#-_yXYPxQrCQ&vVP@0PO|t
zdV0TSbN4dQd6Bz^vU0iH8VZ_U=KfIwcpjHOkAdbD?k>7-^0|^rAO+lpDPFUNXWIwp
zYA)ek*#=U|ZR`P}jN6cd;g)m1raFfTZf!V*S;<}Jk5&~ohr;{S+%;6ET*Ez}0jcF0
z=qPm^_eLbhRjw%?TCQ=EcfsvOuJ{7%HE|PmLb93rI?c;<Ze;{qy1{jMnf4(!xt~u$
z^A<POD`|L+eGerJ+qm0!Fx1YylMdD$ZahU(?{eEO;)?0u&Z2`co!q7$FzPPu_ZK13
z&3&2n=J&YaX25&6adc_-a^I&));?}iC|VD>OUD84=UT5}M31;%QOtdSYyA-J4syR<
z4xK~XLHln|I?Roy)#GDsKBa!2aDSpi@CbMNC3rE)tsX<?7`HkD+MaS}=^#1IRsV_B
z1o!q%sBz$3{{TuIdE*_xIq_5jXgTu=z68&eXQzdW8!zY``0LJlO$4|HZ}<>YAK<+r
zwu2tzCD7XY5N`?@Jj{!%1UbT+y#ywX@^;acc8upUiq7LaJvrmWi=hawH?Qmwa3^@<
zn_$U@_bt7de0lXpK>T>$eF;ncydP-c62Kdx;Bz3aGyuFH-k)<pLU>>LQyM&!w}AG%
zCwZ$V@D#@Tm-bZQJXfkXiQv6ijm}fNGoi2>$?K=8fhgXQd?=0PO}YtQ3@m}f@-}XO
z7jZlmt&Ps`lB?lbJa4lJmd^6tm<p1>+m{M25_x-Q0iVP>fn1k;S~73wE_zdV8(&9n
zDsMhrPZ_*FXrY+NQ@?>p$l`7I7S5dGIa8YUJTHz)HZJg%KZnk2o*$KOUE~EV2Fc-l
zK_48u#A~2;LN4#^F-Yd|*uTN;E4<ArbmsFsDRWl93pj{z+6#H-x_~I+wJicE=DqwY
z23o?CtN@~vw~tc$WxRul;Fa@~uE1CFy6ID-RlF~EqO+RULg9lNUP~!(wY+aQFj&Vk
z(8o%y^5&-kP|tgr(vJ<iO_X83#&g{Qkw#t_tyr4vJa77P<#nFE9ilgQfpi7l<oOh!
zb&L1TzaTBVdIo^Ed0%KD*~;6#8+O}x^;9I)&I_a0-5uWd6e;cGMO?<1x_B>70k50)
z%P7b_-s;aWh#p=OMcVH3wotD50Z;TJaJ{@WEtIzD<1Jo`-iN$fOQ5@-*IEbB0bc(C
z$PDscE{DTIJhm7nhIx;ZynY^?ZMV9^wNc&^3SExzToYjFDQ^V@h{t(zzXEaK^QhR#
zkze{fB%Syo`r^DZKafH<`}v6!?{ncl8vx?U|E&h9-S|$&0dVI(OS?7?{+3lxeSrT;
zGDHsX-=@9pVgCFA7&^ii+v%*sQU1m=Kpf-0Ojn>M{{-FJ$N9$-FcvTVmj8AI{GX&i
zoZz!4A?3qYu7nzY{#E*dPyl~?ItCcX|40e*LHxJeK!W*`xF8|??`Og7Q2r3Tflu<U
z#lu1vzjrwR;rz8sDqo4<&wm2ZNWPr5I8pp}sOBk}A6y1t4FBJaFmal{loAKA`~eDl
z#qoU}!kIJt4`~4(&#&GBa+d$cJm3=eh4k7<;(OJgmCP?42RwxzPH(1EKGPp|)A&!R
zR3n`~wUF-H41Vx)FrUfK6Jgj{{D#xeeU3l!DP+#`pScY++5E?p4!Fqgqtlu>{2wVR
zeu?i+E7@GWnFev0f0ZKWdHkk&n7G3K@F++=-~C763izRP_ZRX@=}c}3e-AC4OZj!J
zl%go(w@!j+Ilq=}_zHdky>}}48-Ic`Rea~)ptPDl=QPyR@MHb~zLtMZ20$Hu#(hZE
z^WS#D2pjmyPr$pzUzZHsjr?JHaWwHa-hxOo|GglP>-;rT?R|qkKzpg1{F$W8ev5yF
z9^ox~uQbTC^6l3_+V~5a;Y>UK`y%k}@B_{Qc$Y7tcYX)|a1S~=`Qw4G)Wsj!49RZ(
z_j}R0$KNv!UJpNMFUSM_6*|M&%kN(UOMU#Wd@+cJ{LNJE*3Tbs1bJlVCwva21N_l*
zaB7gB(hkuf{>z^OKg@sM6^O_DM{8kzl;1#QGh_UH^ou;@$5DiQobN<&vk87WeSpD1
zkoXM@ItmKOLnpxtQ6SC&(LTWU3&OkscM&XHhZ%Jf2q?(!E?62t$#oCGm4)!;fMBi@
zL=Os@>8n+T1Y5fC!yXna_gXwL$G)l*$~*<H%R#&ZE(I{;E%@6EohJkhX%O@gEG$E(
zuOR4qIOr$X_$*rfg6(7=KyZ~l7#1i{bYQlE1QB1sK(N3!2xAWw9HWYYlY+xkIT0q<
zBSb4)uqOen2*G_Sb2}x7w^P+yq~L2RoR1Q?(Niv3V84h##0X~g!Qg4ZCVDBI5jao~
zJ6>R*P5D{DQ3~NF2o`q2i$uX;S{Nn?q_o9O7W{DyxD>%F6!1zFtcgV{O%Pv;R=Qvk
zy*x7oU6gXj5_lBTQt+IhhaLjw1#?BfUl0`0`!ZYbv=nwP3jBrO<p{hfBzQ?MZ4q3{
z6<pxL(aVBV+M!$#%nLv(Ul2{T?F9n&*FXvdhp6nbNboj2GK&S_Ie?c4KB8TCsUZ6s
zkTSt%+bEY<E_miOjHyDfsR-t)1Rp#PhpPq83!tV(uz?Z@wSqLt8Po|rO@`8|f@ldy
zy<n0SY8nK)_CxnI!TKPy8U>7-aHdJ%AqC)uplcW&-V~J4it?7=iyctiD)`?|;I#?X
zFQLQt?SlW&T=ob`ykPLY;56-p9thm%>`|{kPhsyq!8H@eLqQHb68Z%noq>r*f=sG*
z8xYhhF~UJXgaZaKBpCS<tzm(5E<_#+V&|driJ+Bs;Uj{9p8y{fd_r&5F@XzJD%zh4
zR!~lGT;Q<<WI~`@1ZNzC%-ujZ3V+-M87E<C0fy!*-26K__Y247V7x9u8|BJeh4;A_
zjGHj&R~U2`-u(w!JcLV`AP0mSKLPHbuxts2eMtDnY)Bp!{^kuWM}!|zYVW9BIFp`e
z$Apt9Y3eBqj70BoVTvzWUP3<oOAc@0vLApyA#|D#o{#YLPciwv!rNz|#!tx5qSId(
zK=0rH;R^bh1BJUNAQ>baNP(7M;p$yzg$UoKQo&H+W_ov@6z0=`lQ5xuxDdVJ!kG<F
z8X=rVM*>iHy9S6z;pq_IqlB7oAsQ{z3_&DDm^~j;a$2bS03=q}NYU>&;j<K)J0oOL
z_C8+t)pg9wS>a*_xSb#@p%-PMaM@evOcE|%27AfEzuAyX5!&tam`fG@69lKygj*>~
zkS?5F0%nHrH(H)#3RhE}KTGIAOZRiaom&AoFMMt{Ixh-$GT~^B@CDj=UJ_=E!kJv*
ztFeGz7M`I4MR~$QRAqEUxcLm=`NBPyz$*~Ou7pp8!o7DX)>I_4^}|xJ@Bo#jl?cPA
z2%r@1!_zWh&+EXK3#D|{uR{36ZU8EUA3K9o33XITS1tUV?!Ox0VLm!*g)#IoqdH*(
zWmB#SgSNnndLeHz;0?l6chPxGs5yhqMxl$8qG(ORzi&cKvoMR&yVr%&hhg`I@Z(RR
z^rrB)G$3vX(^>GMMVNaXYHkZdT4178X!;ecHenTo&)S8eGyv`hrF41R6^f+bbqK$r
zlzykM_FHJ_61G$6L${D$fN|avMs`pXtw*T84sG{^yXnh84}`sY;Y_daeaa>E2|vCF
zpB@VJw3O}_PNt>hBVp^O01OBN^C2=Qyx$1BL&9Tw;Nh@vRRcsG3s+NQ;fXLt3Xu`v
z=_}xk3OUbV*ki)k6d-si^f(PK?BhZ)m5)sbduKzbgD5-<2uD%pamYA{_EB!rS+r{{
zc>6`azYV1>B7P14uA<euAmS#nJHj=0k#P=M9->9DXdMtOv7mKObc;f3heRz@tZ-PQ
zJOW3LiTZEDf~V-_I69BpMIXjtyk4S>RNdh%`r}m~PKfr(pvFhkcN8+dqJI{m<tI}7
zSJfdJp?7$I=m9Mz14Td6qAp0}OC`6#q78K4hlr$<QVJDK_`&Uyq7+)cg^8ly#OT9C
zr(3~`5V=zj{glW)9uJvFQ9i}{qC~g91c??cd>)rTj41p?czRl7*$&ZI(N&63#ff%l
z!8;@Jd>)e!FFHZTz|M-cUqCBCG(f{n6#e=Hl1ZXZrbBhI$nh~cQ$$%mqLnI2qAh-!
z=q?rVrHeZ4wEoKwT_&e8MN*2nW{DC4A#+Z2Y6f`cMV%X9;(}-^Mb@)Lg&K%l6usJu
zR*tBVo_d!>_HY35M7R4f7gt1kRG683QO)}>SRgWNgX%(2cpM~)L`_sFQY?Cy4S0zt
z&%+L2spu+|`;>`Plrkw7c?CnXLL{%plvauaW^`7GW;_RN)uQORz}JaBlY(3o9ioI!
zy{MKAM;k<+8)501D1>6^jiP@(g6bxbFYQX2Me9&TIqkYAhZ0mbM7~t?b5ry$gBGf{
zM3eA0twpq817vQC-rfoGt)jr`=xh_cK?f1rMRE!m-4T6F7x`UL1)UD*5cO^X=@fat
z182HK3tNHf7M0F`-Fu>Enn8L*3k-nY7cH0#4<CrO+hDg>)OrNGKG7|FJJCMvp=fn7
zM$s>tLBGKxktz{nKy-pK;e(<F^m+Ut(H~JD!=l<x;L~H#YCc*|L<~CdJ0hy;!tXmO
z`jP^KW1`x_aP+C@?nMlAT(oi>L?%SLkHIwu@lrah;V91Tgrt-B-W%}A?krC40%E`T
z0=*7h#NW_m;wom5!*1ehBS5%|E5Ct353!7rBnQNs_P~pS;x>8|9umJ>4ESO33{MR0
zi1;=wkB*A}qza^C;zc?TPw|iE!8<M<ItfWH@q_}(yv6&b!nG52vD-2*eZ*V}IrxeP
zZ7}F3-cM@$#r5^D6d;!U2+=?>YX-~*iQn7?5-i^O03spcY&u30DxUEsES(e|ECC4<
z-=U>MxcJ&f@GwGL@D<=u;;A}xMvI#$yAdOP{U9Vyi|xx!VW6?%yA1TkiFZ7KGiSs%
zQeh%q{F?}^v*MmSh$M*ZIp|Cjdsxv*5<5~*Iaz$c05vJ%K-z(%ic60`OPY9~9IbTm
za5!2S;@@cBmMNY?JK8Mq=hFZ<C;nw4w44`b*eNl0LA--X=Cj3hap=7$?t2-cIpQup
zT9?Ecib3Xz)h-z5W$_$ekUX)+AJBb8yn)V}=8FR<+E^g={0mc3C|<Gwydv?J6f`Op
zAKwHECE{=ALs_Z#NIhC*;?eVHm5b;6_wmsR@$3f7bESAbMaZkf^I~D5T6~crgf-%{
zAPlBfJVyT}t4>_G7?!Sz!)P&mO*~Kl*BZsI#eg)4fAs*aS?s?RyzAm!RDE_s+)R&@
zo8o74A#zI`MzNF@asNk<ye)q3(hIo%TE(+NVWLg!{W*Z`Vm4h@cf{q9@ae92jE=f=
zh-V2vI>j~PAYJ0?^zR3{#j7X5!+YY6Y-sBdAEEH|eR17MbUqM2LvNQ}aTp!C=o8Cn
z1@%z8mEPt3;zijIc_coHVodwA0rAHa6d4qUQpR;i{PPT$9~Lj6Lv)YDOPer>PsIBI
zfEW>PTngT(xRj#(V`3SFNS=zL%Yhpgf4UWem=H^-!qY+WDn&gVC3ztLI7td=3*sy(
zX@Q~rk{cVL%ti7mopQIkN)jor=q5S27zlSs_b0IHA?f=UG6y8NQ}H_;l)OPNnL`rJ
z2hes{@(UGC9+7;Z0q&?I=mt8ENp@4gw5KGJ1Igo(pz|PJl03Q~yd{77gLgvGP4Oik
ziGdCP`$}G-B$S_BvU>;A_)Ct_QYJvcp~qdI#E&90K@v_K)C5Z&QuSMiB$2AKLM6{o
zBIKl`hKdx!B>CNFg-d)WUmPKEI)T<HiRv!^A|<z}%p*!tOriW}$!_{6MXV%%Vr6lX
zJD;O<Mq<~|+c;kGLKS+?O5Rb!e1fEc3Q`g!vu8kQk|c_5_+*Kj5F|z78x3HpWDk}9
zq)Bd01xc3_Il#3Hi4O%AG9~|PhZk9rq-{`rPEz(aw49gxNteI{$zlh<vn5k=VBw-<
zot*-QIg%3;nY|?OZh?thNd=vcx-6L_13ph8TL=?ZB)Q)}X};uCEqDbIPA)7JN<OED
zSCPcdhDfm_o(dOABo+glDV4nQHVl?YKHy*y$|Wz;cK|9RK|`3eN(uiEe5#Vfy+=20
zwPgP~Fl!{g&jhKJOrdIqI>|LIlwOtW`VJ!Xk{o&&H%R`btK^#GlP*X$O4?`<a9wgx
ziOw66t-nI)O^Fv(soau$dJ3+!NCcE~xGhN=glnx5`5>HWlZ=+a!*<Eqz0ctOyCa!P
z8T`8vGcC3{Bx4j8>y$Vifu~)PGgKAXEvcdX!9B^$n;<<BuLCfDU-Cu^v^|i_N`{GE
z$xojE&?gD`AN+kN;ZMLszvLHsH9wMsEQk34iSwsu4N7J#0dGih0>M{&<4CfRqUw(&
zea!$qk;Hg{IU<=#A08N$xZFqQnB)nSeLR&g=z!|D<UEaHLgIe{1|6h(?t?f=r_gfH
zNt#BRNoT2bDcs&KO`}sZE>a1_VqB#q#qh#SYTW=Y+@){QqQmYX{U4Rt9+3X}3zQy|
zmLCM-i1Z~293GWA{SGgVNvq?5_mrw{qw~0Q5!D%bNzcck(_8xZ9;W1kR5J@WAL-#8
z(CsT-xevPiqz~yL^_N!H!9swPN8=2XChtKjNa{gb>0rCG@;i+8q;xzSO2ed|e+(1h
z(rIjnMo70)$=WID846ZJN<G7&G)fx2A10!uOOAoWNMAVxZKtJQ&Vxv-^aU#XkCWz7
z-t~<14<hl>Gd>VGE6t$Ke<VnG+aZ}K-6n+UB&pr71~SRg4;BKLB5faoQ>oH>ls8I~
ze)KP#Ntg1YF|-Wn(HlTyN_qLvmL;7-)j8*+2XIzw+Ii^)I$U-^+DQ-HY-ti3CN4_n
zQBhrvw8R_alGNizh~!GQ(`9v8$~*~Np7es9(rs6yar7k5mvSjVT_DY*P*kDxOZpO5
zk@U++FkdXa`zMr^NN4i^D3yLg`>8VNd@B4emzLLoS0N3a1Ai-}%t;tTwY0hbCTgUA
zOaZBtR!PCDlkWK(&RmslSO9zV(nWeZL>r`0lzh1+&5nY$MyV%-YMP|!M`5B_s-V2r
zb?F2}I&Vn11iUGYrdp0$(iXZBTBKzZ2WgW|rDGoL(xvf`yd%B85S@3W#q^Qn4r!<#
zbaqPpsg|`%`U^cox}{T>(>KQMN#}dRw;rkES`7QXblQ86c_4itK&w~kO~-Znq>HF3
z`Jr^I6>9pW*XTlgB%S{P)C@>}=Av^@diZ_dhNR~yIyWqhqL9a9Y2-M_6KNb3c#KFh
zDY!8z{lNxhW70*3o}2XIw5QT{%VB9;+Uw^V@ap7+_Tv<^c9wA`Ahcih4wb^Y$hIti
z0#{jhCU|bLenf7jxyycQhlq#lLkeOYkd?m;$%8V*I%qp2`+x#Qhh-bfA#y~fOa}a@
zY#U{fkI7C`;NDZVm10@PWgB8K7%$n<a1d|VYj#?>o{+sutA8KaTljFvG+)_FdfE8N
zy#IiCf7#Z_Xa&fe-T^OAR`MZ8knEEf@PcLUtb+Lv*^6{nhRSS(kUS~7L~-#jSpbFb
z!eyHqAsHcCISAY-ndv_4Maoj>AWW2Ou7<9NXju$>{yIi>X%i5qW#04xjg`G7fctT>
z?`ea6M)oiOO5<goLm0(bSwtFI39^iEkVM(a6zEQpEvMXNvg{zmt5Rgml-Ep^B~f8}
zn#}PTw9;j_KEyaPWcRW`GG!edv?IxqHPT+<oXpY!OXp?NDYbDy7Pk)Ovt^#^AbL^e
z<_mm|EYu2Zmt<@ALo!zu_!qptEW1e8Wxj0QF*s8o`&xz0LK&Z8G)1y01^|j>6~5q=
z$Y$1pS1Q}%3|^TmyJ-@h$mOzqAz)U>{=EWAm9q8!VuV$)8rri}%NpHasYbS}2BcPY
z!w0}R*|M7;S7i}70MyG$hhV-zR+9k0HCfw3xZNoG#)5fnk{urduUR(ve}G??<<ZXk
zhU_ycTD~d!j8@9_TQW-?fGx6dIXt~ByEhX`TV<DN@6;v>{U1czWmOO1;T_r92u$!@
z*{2^sX@{(1IlSnU-FOO-E?KHKM7m}E6p*+lE1+;$kIe7CdrVeBUw(QZn?mI#y|Oxr
zf%VBUUV*ZQc3A{nN&T{8JArs4v(ig_K-Mt@+6HCb-=Z}n+f3E8!?No<%-&;}l<GE~
z$liMje@A3R{m?cli=u$|m~0L0^`6QK>5d<l315fK3E2iAa1QeCDZk?=|CGKU=_GgU
zfltnI`=%81?w4oNCjeaJ_Voa|%2(3%*G;~64<^A~zJy-!9`Z^`_8yS;QUdItoIz`m
zL-KcC1^lqQjW!lX<o~+~k)!g^_2@h%Ke82eJ>?;L;QevAauJA^e8*Erddou=f#)Ot
z-9~qZue^zhZv5nLQ=-vd{_<Mr4v>F!4kS?i2SUWtg5-HrOcgAzrgN_$@?Ytt9x8Wg
zfu)o3kr=eX<gRalgv-@FuT7qVf6EF(QSwbx#}h4oOl#8^d8rb!bz1JOKxeFc#$q@T
zCtpo_jx+KPFF_<;K1xZov+`ww5J`{=UxSuJxhMdxB*{Obr%kf_a2t3j@+8WQrOG?@
zVhCySsI6$F%h|MV%aFU<=?R`G|AJCoS@QSZ1n`{vcdG9?FMol)6M8`|CKK865g+(;
zQU1nKh~&sE$I!YY-$nz=mA|k8S}w~S8$t5qztM4vEAqbS@GxKAM6sL#`L7gtFO)BO
z6M!Q5wtpc~BHz|e6%VEIWGD2N$zP?cRJr_c9S{}rgS4Nil>427!791)9sDlU@(bB$
z)yTW)SZ1yKANnEc<lXOM^jGCc@o=<W-bR;NgZwZDyle8y6VTEqpMDvDCi!045jV^8
z=;M0V<-hsUcXn^c4fNTyn{xbfbiBXhJ1AP#B7c#da<}ENQ=zR@p49|ko4k)Us_pU{
zl)1el&!+vzUHN)SxOK=^QF&OW{8}TFb;);8WmC7DO{Gcq<U1&x)FaQS2DvYPg`(UK
z<T-ECcjkNLSJuKrpZq)>_<kt=>m$rXzdVty?MHG=K71OGN3929P_DU%!3@b=VqkYz
zJ~9Ex$MW~+27e;IPRaWb`46-(AC-Ud7dpq}`Cr3}r}9UCKoU=me27fQ_fp)_L1Cs>
zlig9_ONTP{D_;Ar=vncJ9}K!G{C@y(Q+!N!p}QjeU9>zDZ5Mz)ptzC<e-A30Qb7(W
zO8p^nSg~A&))9q*0%AuMy}dAaOktq)y{CfV2a)3nXDaCTQdH84&0DecB{+IwilWT-
zm4&zu-aG-P{1tsw=nYVOz5oUT6-ks53{p(?f!$z5<k#SZDE_1cO{hZG3*JeEGo{MH
z6b-cQ3|DmRh3*K2Y#By>N>M|h)kwu^iseKpR?`D5T47iQc#Ps5%5a}n_((uv6;<|k
zK;sl2dBW0JMf_5zNl-Yx2SlRc@=|mrDQ1z<WQBy5`6-I^6A(#Nyr_ZOX^Op6T9U5F
zNd(DIMEk=;ros{ipRyFsy#e?+#m1k2JFn=XEW!oFZkoz$#rPipTvW^%r`1A^;;|b>
zcu6sT5p?G&2B;?GvVy-3GI<KtS%_RwIHzDP^A*q1S%U(_%df*kp<+2@zKRr|IiOXn
zIR6E3C5rH?0F)|v7XeVF*kpuAxnd?=9u<n0Xh&SB_`wNUsua9G=rn1yBA-^zHHu|n
zaKBb@{WK7DiZAIYcU9rE0&40N(htFFP_Su>c1;mQub)Q6ree%YlR{1@uVzL3ZP>l8
z$h!@Z8;X6gFmY26NnhW(rC8(&K#OAIT1ehjbY6f+tKvEH<VpN#ZHf)Fn`>80Rl>v_
z#ru?D>{PgBLbOY9+=lt;R&bM`=APm%h3<M3jz5CjSIpbuyZMdDi|ub$0{BQFeHZoz
z6c;XlIjER%ANGe7+bJ|VtjPDqFZx(<W-pXJQP^LB$cQ5N5y+^bftJl<is?t8<*DM}
zQ)n4i9QT9W3B?K);10?<$`&~)cfE*7bW%R0d3IJVpNW~-uYAu=DGnE<nx@@VnMT#6
zZpst&(Cw~#g_a;5%5Bd9e?U3^HFO?SW>TTbA*F~ST8EV>^=KVYHhTegRQVmPj{KAX
zzOd`Bbe;whpnP{1Bm<SHwEYWG9^MYuf|V;MMiHXiw~Eq$p-M-3mYr1kZ$m3gxruVH
z;Y#jtn2%7VQ&RAha!ET7k;)`mqeUr4siZ$z8I_1p#3)xh0q?YuL0g_!<??zs6Q>;7
z2XaO^3CA3##Vh+M-g;KK{#AIGpd8r%lBi7ii#`aDq<pvo&17Y?2>29bHLVX)l`E()
zAx(LLYS7Y^k?%qzLm9UZBvbh$5h7X2C#x}-b4r5;Oq^Frr-NKj`e<;qWGfF+x#LCU
z<aaQ#9A&~`{C1a=)2JjrS7}Ow<Q3&yCY2@SD|-UaTcBjp0=ZDx@Dr34Dd+40zF7Ik
zKJZGEpJ<_`RJq|>@XC~TX!%&7oX&tqrE-23a8=5Xe2lPKDJTZ1QTnFAM6EK13WDmC
zbx$ystIFqJhuihayA&yDP`=B;Sms|-_S4I;QF(w?^i9fxl!k9suJE1p79Mc(_2_I>
z7GDOUP5I<|m~U4u7y#go@^LT7UFEWM@UTNE$^x!aIYIH|F6C-`C2Cr?GL-67?kO+F
z!<inXh=z1u`7{_J50u|gX-cp1;7#c4Q+{lMGY^%nbWX8f8A+GyBW1XK0h$BKXTzaw
zP$?|}8B&&|f($Eb#$o=k(s?Odd!l@i7D*#Yr*;5Fl><dkI;Ol%v5Ke4=oQdCu3Ra^
zJWVL`DZJ*Ws-sZ7ld79e`8cZ<QP9{`B|Qb6o63_u_~@?EyV2F@q0&>t<$&r}3TPix
z4Xy$?qN*zc;;3rfD-b!R`uRJEc&WBizTaDQs01P>RNsiv@=>|akLIho)c{F9RT@>e
z`>PCeY9>HcPuEkRYJy5Uf>aAB{vWLRaR%Tas=upf2N9~WQs(WXO78_km`b=EYQj|y
zsURpq6}TMuQz~T_NTh086-F4PiVOoUTJ;gVg=19Ps21k5>aAbFi&gzgS?M@c-@hPd
zR6qOzW$~&nsru!t>d!d1mY{m)bvTo#+J%ezi)l%!yL4|RtCmq>HAS`I2eeXE&flSx
zrkdXa-RY{&qM$89rK*6VnW|ul{$#1H8ZklVRHGC~Kd;hI^!0*j>WgqKM^&N%?vhIF
z>#!IX+3f#8*%j6KBzTdp+I=2c3RFLwf@_7U@@9}C)uB9y6sxA5h3XR36k0r#s^%F%
z%2fTgK+07sxPVuv4$<+pN>woho2yi{%V51))l3P48dc*~sIFCI<v?ehs)JVGS5=<&
zZ~*I7CxX#zR9$)(ttQoTOvp5=nrYE;T@_IPaznL_o@h5!*Qm7XmTLV~m}pVGNwxpC
zRZ}Uy(yp>ig@<=k6Lj|XuIl%r5b0GNSPa#Ds@W93c&G|~2JivZ^;HlVR6Ut#hs==b
z`88k;s}@mc=CP`rUUg4YoOx)CseYxp^{1-hS3t&9TRsB7QSD;Ku$|QTbOzH|J&%HA
z`_<_~ATH`>DM{?AE+-F<sn5L&EuQMAE4Xitt5<yh^IqzAv*5P3T9-THOI)k!d6a<m
zQ7@pX5?}RfiV^s!f1#Q6SC_s3(Ezm}6udz7-?TpsQn%8kHCTPH1)U-4H~xgdlj=OW
zy28}jLi`5d>Uzq#MyMlve_n!L`57Nbo>r$_054YE``-p!eX|>`ol$S3nTc1wIv1+X
zs{4vChy?Y{3cwT9yHf#3QV&rGH(5O?9K00u+1Y5Ns^3}#ku>!~3izd~Ra82cp?;wq
zPGqWM*I=CI)qhJMc~Sj_ohkxy)W4!8c-kfP$RzaUsyF?K)@Aiiolu&muKx|AzM_uN
zV@C7Uqbs1aKz(Z%l7(s><;#oI501joVs#$XGnA-fXoXs;KE4Nb%haL`0F<lO?}tc*
z`Wf2JRH}ccZx>am^G$X%tJOm_VAiNV-wFIxb#Nre4fT`_aQLSB%5;qWmO6ye{Vi%o
z%Anp>-=zYkR&^=G=-Sn9d<Whg_0}7ZysK^`4?EPeC<@W3cK8saOZ_Pw4C_|M^Z<8H
z?dcA{eYNwq^eB0tb~y-#d(}2twD+lZ(Of=MUrmGge)ap5jeevKE``zo^>qihHmL47
zjMk8P9<7>()i3;lnR%ivpj&K2z5fxkjH*xX1#e89Ni}m%)jmuNa9rK;FH}#cR}gW~
z6d{IcpXR7hQBc82b6XF*vqtt8fcrI`|Dw}HQ+^L#xN7>lpwvyX@ejD~u3^z-<)K*_
z1jz%MQc5Bm(L}F-7soVibk@gHGyDQZcw94+4z_q{W;>(PThrA5XHIB*av<ra@oB+W
z?Ead$^xg~5OmLt(P~-SMm_eHGivR{|j!Hm6H2xHR4AsoPj$iwv=H@b}3D?Ldcp9OZ
z(Fc)J8es^uMQUm{0v@F)qLQO%&4*)fJ4W*^EtgMgs-mGKR#QV2e{q^Eivc)e*Yr+;
znt08dROO$bDWgY2qGlIOaFQnTGpI?{tnh%+6b*}ZHEEig&M=s+*?kpWWMDARmZ@2K
z9wJ#9ztg~-(?oQjbzU=#_UPFf73F#^YNj+})^aojQnW5<UZP`~xf**11HN6>ET!dk
zo~BR?6GfU8%P<$kn(1`Mm1rhWVzN{dMZt(N&9SNARcM;%#a^j-t{uE8&8i0QYBf^`
zUZ>fS3lmp06%>4_*Tm3PsX;Td2)IVgIf_L#Y0mnB*Q_zxKY^N?n$H%4c}wH`DF)M`
zNtz7AZOsXav9)Tda)D^md_-S7XxDh|f#hAy+F(d_X#A*Tyi;@g8hBkASBiynYn0iT
znR}YAFM;%EZVzJ+_cgwBV*G(7j&em0HCrej+OM%x)1Lj2CYyFX1Db2=p?gr{)(+;7
zMo&AJ$C|~{Fqcm>p;TBfqH%v0BBPo%89K)_iC;tagl1nMBptN%Z-F>!^C>>#q+Kq7
z_s-gG3LWp)R(ip_t2TBXMBKECLqOcM_xmV4<Dm^`0pfs`cN(IHwTrtUdPF;s4iiVU
z)e3lcOsmR<h^O}SI*{Yq&Tinnw3(FD^45-AgNUy-e+uA!+8PRY_-j9)-#$RQfZ_;&
z+U{4-8LYkQ2|$Q;Gp*Y~wSIwAo)@P5mk!H?YwNFKY9h2>9m3?F(k5(y`AF^cMyQF>
z7Q6#qj5dP~@|@N#oeqPs+K(9MjMK_aK;(?}I0LwNt!ozyCTLmjz+j@bgOcz`S}twN
zleOEa$}UCAq3KH3{`dnX-JYS{YJ-|gt!gPII7@3HnR8m-4}d?feRT<V7qq{fgooMM
zpD4d_QTrSf^yFw2J>Xr^_K(7uT<xA%kjq*}T36(0>!_0ZiuOP{Eahw6ncx*@9j&lX
zsNIMd=(J*OOcC5JS*PuyU$j)~v<jY<X}_e+Z@Km*`nX4h_S;k7Rccor1-?rA1(j%3
zYY)>A&>C$f9W}4jE}__Ioi_P9D7~uvjF#E;+Bv?4<&$5xr>_K{S^JR)mac2_s8r*I
zc3}rxyQTG~M?;IYn9_{5wW`;_Yt?2@Mx#yp(`4vu*Ot~|oOiSWI`eQ>>r6ZU4s9G2
zAa!c_BT(I?Rm#xn)^4R-z&&l=NdS7Zg*_O<eQlJz3cU}sU(E&S)ppX(zfb!-CCvJ@
z`{~fZBds63P6o7%Ch&%}j<i#Hti4_Y@<c0102$GKuoA-^)gGY-@tF44EpYp(wwdCL
z<Jwp0H8i1JOsBmZbmzYU&rug)gLx<2ClRy~an?<#hVK13KWB)#=<dCMPFLN^3qZK(
z#B@B{T{l3Vh4RpOd<FLp=-wQ_BplS4XeoP0_W&E}X@_;+<N$X>x0#aBM|JaP-*ZgY
zyb5FS)FtU*_qZ;U7H(d;5EESU)}=;MJnV!{*@dQ$Zf6s;`RaJ|EBonOlcCLDmqK~i
z0G-<*v;uV>7Ga=4x@;}H2-Z!R0^K3H#k3L+)fsysa#Cj)0*TPQL+|2Ky1f)BjMN>S
z2k)bF?iA69)<wPxEit-tcm~<0oz`uqOCVNvffl%Ny3|&*;&mSM@H(qoLlNr)os>2S
zDY~5}U^i9QwGD$w)A_qYO}frL1TQjlFD`?@OdX>Pye!=%+OnV1{p<u~=XKN4A$dVJ
zn=X%RT^fBG<)SX=b2w_x(cSzN%u701FqpZz3VMiK*2T~UBu^LeD@3p8uB-yd*A<n(
zM1gKE0Sa}0P6ob6_bgpO#X9aWkP_WH4<K2pJ49DtneJ#hbe8M1<p5OZ0u$g`rOrn0
zy(--_Dwwaf>jp-EsL_4B3C&tv63t$nZgV~SzN(u^(S&;4_s$><y4E(hc1`!79+nz)
z3z^W?q^l1_t63-54cv7d+lpb|&;`-ud{cLL5=3t4-lk1*i|!>Bc(--`QnImC$6gPS
zHl4j@1Osi?b<&xoJ31-l((meUs1^5-Ztyd7cIs?dXm#mEkHgV!ogYPn?&*@2Lb69!
zYlfQpx^4a#(*xZ<^g8I(t$h;)`*fv!Xg$>RRiM?cdto08J<_r1O*No<vjhGP>f-HG
zMm(fT@5Bg)b()W1a71UMB9u{`_HXDO({aN=p6Xr+go$yT)9X+=p<BEVN*(krhtTP$
z=TolKNuRp_9y;s&UV&@-^^x>oa?wAg^H;8V&bM&eO@G4?lJ5F7lo9mMuSuu;!U6re
z6KEdPM_mQtke)Ax?!)?&PLLz|cj;m~s=u}wBFFS?Rq)VL-$wE5<NCS+IOC;H{uzVt
z)~^o72v6wS|EuNFN7H-6S1+Piil07+KBDKZ|C{Qr0`wvCAsMV^X()(tQqQL%hcLa7
zR<YswD@o8Dp>L;$$tnG3RJjzXucJUols<qSe$o1`sRkxSAJq*Lr}Yad)f=mSNKuzK
zy<7@^&*&rR_KnxiNrKyF^@iziG(qno1xeJ;u7rgo{n00raQ`Li-{(LkMPEZ3#Z>*v
zLg3T%WopQz>$_e+XNJCxp6;3Y$sBZM>6@Bh_ncn)HT*rV|D6NC1^v`!_>`?5I|&aj
z>UUGXK1c6VhR#d+_3xoGS06eXotO2UzR;4VpH~c?{fd4Pl~LvEuU0~7f&Lsl<qP#M
z(J6@{{aUK~DApf(ANUgeo(J%vRKJ62Wy|ypD)7qnfA|AXp`T8Bol1S00HjL)j}@*}
z>!Yb^vqnGo8vwQXTG}Vp={qPsdsW{<H%Gl)-%1Pn2K^5_0I%u2p9Ql~F9`v@NgvIC
zr_K83zXY#EKXVEUw(8eYe5g&o(+#|Ky))fMcl5i9q2;c=W&%n(^jWn2>(sATU}RnT
z_)+k>^>I>2_UWITg}?p!U+Kbsq__9cXAKARjg;>i)}K5C6OZ*yl$Uv;Uqa`|NAxjY
z!2GEGup>mq^v_et-&6f`U+~8DYiTV#p?{U0*$#%~YQP;0OR2`m$zZ3rgR`NI77hCi
zC3i3+7sKQ%c;RYjuLE&2tg`<DrS678+MatD=Fq<4fFb@P4DFynNZH^+hD%gfbJ(!p
z7wA4>STF=_M-7G3q5GI&E*qVmhPqoI#|;Bt0q$j3NTns-hSF+uo-q7O{~^f7z<D0y
z^))z(0QWQK*FwbKFy28QXbv!ZLqiKRT-yYvf($$3VKCUho&<b|Vf{5&3N>*106b~<
z$%f7_!%u&Kgd5_vp)<np-GAE)15<@oq#-gIGa6;sUj~EGhFMe48Dm&0f$GzS$kiBU
ztl|ByK;jJ3=F$Ck#<1*X_#JQfo{oQ>HGI4eB*DP{1U@Ai+KvOCWH9{?oymsnwA4#6
zEX{-YR6|W1cxi@#72u^CMksQfVeqG<Y^GtV5nf~&#?Pa5&QSanCgHpxo1(NA4WVL?
z97FkUw6?rtSjmQ(Ttf>3h|7i%SByT-Af^)5D~6}EUCuW+d=HTV!%vi<D>N*KgGiA<
zFc+Q0hLs}_DKV_w0xwDp(~KBenc?LdXq6i-X2N`h;rE5`x6<(OTYy&?&Qhz|kTo6l
z>@@~w+M3oHI{eVAGc0=ph^vMzR9jVV_#zi-8VteLK&}}&v@qCcc*6s{Cd2DNP}6K!
zMMo*F8`yUta>KBDD|j~zW;5pEmf>wGd2can(m>?4;RAYXv>Lvk<VBmoB^CDC?S}X0
z)zM+t$bxU3hUXVSrpv&38O&}&`&3NAJ;Qpc!|gE$DW!PdaH9oE9~jzbf_n`ymoXQ8
zhQt!I9va+#L#yA=M&<vH48c^VGGMq*#j1mbVTxD`8C*LsLBoazG0^hZV7E?(=o5p0
zJRLE(QXqNMz^2d6ju~ucp!BKX?KXHZZb+d0%!Hwr^2QFv9aN>`Xmq4UsgrTW>kx4^
zx&)wezwzyvQ08L%{T{Tq8Xr5r3pb;?GdkUkktrY^#?h}~=z#Isb_)0(G=4>)*h9v}
zPEd2$7(gWlM~u!Npmo&P_W%Zu8GBt|-qW}p0fA}9jRz@#<Ynv`gl=!+t%vwwP8h%9
z0q0}<U>K5qMhoRW{EZJ+KqSEUuJ46Uu-yK9BSb=tn$zH&G=@_?HO$ynjLvXlDeX5S
zjFxzGo-&S8%q!A(_aszD8S_2^i8gMFh4mO?mK-9djf+D8IAdJQfQ5MD*S;9;Sz|yD
zJWDX{oDGpg<L47_KFRoMHe5<JO8@)!4=Kj&K9ET@9;ByihS9+jz)WLGAf_VAxW59T
z7mUxn4NKX^XD`6Di^j<>fR|(Zj4s(r#^n@@%r#ze1pKn`8w#lA8GSRryJB2D4Y+*c
za}=p4Fs}F(q|n$%UjQjGN~cg7tJwJB+Yl`=9;akysWGz?q|8`R54+_?B`xJEj6JDn
zRT}jxAX#Pn`B~tqjVtLbT4Pk20H`(IS`E8(#>@w3T{T{$+ppeep@%?&QO$+qHDlxs
zC~Gtdv7VaNWDGw=mA=i!)a4MpZoIM!zTGg|5<qSmXWfUkTgEEdu(cR>QvKj<W2+dX
z)wsz8O52QU)?(J$jX!P!xnun5Cjjmmmwf|xhjHgPIy;TgLi`k6#>Moe>Ne`$LFYYV
zL=9R!M%QoYadY38O&@1?V4Ro)e6KO}6Bz6>28%!*8b7CJNx$&`9o~Lq)V=}90b`sK
z=3>yejb0T)M#qg188&|U1?)aH1{#2SV!TL!zY*iY%^2CJQE35h%s5Dw<5MG>GJ@mA
z01BnrCyZ(;a&Rzx-U@BbCWjIL_nV}VATFjYTHswx90Nq%OlB@x?xvbs@WR8iow6$j
zO!`pF#X(akJ;M%}h7-{`Y`R3HFGo!L0kn>qGHE$=%yg~~T0Bk9xIyx`$&YfwUUm~Z
z3`)ICBlGa9oiGJZY|_Vs|1N}=lgXK$I({ZOWefdHn>^48Fs-JLPM~RwPP7J@5~czd
zY%(W9ONdENcVVb0QwWihrd-O0hM8Kvgh;q)4%PTXm@0O{{3+8Bx~U>fc2PT&Mw$Mk
zL`<~lZVG@grgOtUoHpI~3%oNXy%!MiraAO7J!^V_0(c3g+wPdeMAOJ&h$NY+=3s=$
zra?cronorULo3xZcP0#`n|}Bgof)Qszr(dmlg}r>Wtqfm*gI!p*c*VqV7fC7M7C*C
zCJ+}*|K!1Zj%lhDyi2BJ$~)(p^b}aSV)~HMefg$*S~V1y63#+Rp=rxuw2DlzRD)G)
zTJ;u4iD@52c1le`4*V@M<!!;p%1x(y0Ix7rQ$<UqY10ZjfK{fvQ&3ZF`fdy+YE0tW
zz}K3jWkA%K>I;CsYI=sATJ@&4=EAiG6Nl1^*Gw(Hpw(zvN$aU5(<~~=Xf{Qy1@F4)
znG7hqVe*xNchmG_5_H}&EgXi<7E|O_xOUsb;5?7}ug!$JANP@I+dm*3rm+y<J53H$
zKh$O7<^tbsYM~wKJ=1gl<(*B!&w#&gI<pXid0;X&1J`T%mXc_FCM)ezADYC+;dZ|%
z@;a0anqo4*8!~-FpC21Gh0uNb*yQ{M<t(3=9B61GrY%3?ml-uBnlTq+rV`52KQ+zy
z7{GDU&Yv)t36qV2M-Jwhw?UlDLo?u^v$>5@dHc-;k0Ih>{$>{duI9;q!GxQ6`Vn||
z%$z0$@ieQb9__e!27Uj_%e?ap?Ag7|&tHW36Xsef)%7!TDWB?Z4!Z+<fO*3&&>d)g
zZ4kU5^A|=)2Ak`~(F!qtNvZfy^Cl}gPnso^Eetbz(px{={7D;H5#~u$6?@9Oo9g`|
z&4qW-8D$Qj5J#f<ivhrs?B-Krn9CIN=Ia<ts<~_{deh8@C~2Q=&YurU8Rpr~f@GRs
zeh<2{%m-eA(sSlr^uI&So1f%E@`Abe4~S%&|H_9m7tPaI5XmvWHVZm0nN?I5mTT5h
zxb?F6;(rMW^BLM*Trt~!r;`c!<_<sTE-)K@f|^3JfQq1t%(0YWE;d)60k6dTwKMRg
z=Ch~3D>FCmgWYoT-dCZ!!u%!WXe-S|+PYVnGuoiD+MGa+)|mH<LZsH*Ko8wIb9Fv=
zSIv7Uja6?}+sT^-bLlKFubH>fwx-cMYXYq%bMHflHk;#UgM8Dxm)3E&%*<MJwwM=x
z1CiV2K|f4at9hjdTx&D0c@d=DeDxeU@0efN2k-Bicl?FU4)Z(vF*BX!S7|5RWmePX
zsM}o1r0woKbK_m~_F#n2ec!x`DhwZ(H^jhTuX*zjEcKZ^DIxjLd}SU6+HX#O4OizQ
zvx_4-2h2mwfDf8yMFTfv-a$!-Ve>z~fcMyZ<Slsd#B6>UfDyB;0>d3OzeJmbF>}>^
z3O7A9FL(ybaq}$NK2Df_Gyv#e@%{h~J6b{xqUB_9*aHz~%jVw!+;1tNl!l8XgK9!t
zEj1E&=w_*;q}Tz=cm)P=&=PYKUL3M4+XUQUi!dCxBbI&i=s#*%^$SFfS;}$p%0A80
zqN8}}af^_)YF?Jn%|LitzFdjU6PAiQ0Qy*-{{uW<OVkK>ewK4okKk|FZN*>$EK4co
z9B6qB#az>ZEH~-554H@^S}Vj-vILT$mIlh@owQ8;FYRpE_cy!<x4gC#{@NofC*uJ;
zWf`GZRHWsHMvN)SqECU{XbY2a88MbK5fC|Txka&{Sj(*MAQES}Pm#1U7BPj><1MG@
z!#-y%KP-Tw2^K>*bSGL~&xQFU%a{hLlPyLkbf#Di(*hyY@|bq5X?BY*1;5fQ-Lw_R
zu)MznB-2uN8=YB}jnsM0^6&xh=Piy@32?zux(%*nTmGTJT(m4PV4ia<=co+!lEudY
zXL2pol>fSH`SMkm&$C>hh3*y0^Ym`ax9lAUyui}44y4dxzcCAADzeO{nuTIZTNp%3
zEHk5_t<;iDr{&8m!~cEj$Pz-!<|>OL#oTHw{<Jf#vkbosFRof1(K?~t^43}yY_NP3
z4xQI5-a|0hXc2r3Elrkb9cVRM%6^1}>y{m~KfYnn*n2REH!YX$LFSgFjUFZ~mPo1{
zxNYJ74K=NnH#{KPW_h1Nr0o_S#RKkGN;W~;T}wL6Y=`BGh47-&qNWe9c3GS^1JG@m
zpg`$8%lrvQ_E@Yw@bJFnKCNpWSl-Bj7rmBn2RdopXNh9M(nCw*Ovv<GUY$Vek!6G)
zI|CMe4e*1Ow+ql3vdjxZYuF;b1>KJ=Hi|tzvBc6Twh_zBaVQ(LtiA}5G0U4T!^Bg|
z1_~aHTap?9n6T`jy{Ln=rx%ir*7X1Cs-3L6DU$7CeU?I`u2$bSK-{c5>D-ySbw(|C
z9##RJA3I=8;GpxcHG2f)h&7sGj7P2ZUhs}vr_aIYy{z?gR@mFRWCLdOgf%|~%6zQm
zG4On?tW@v<tmWI_TA<Z&GL=6DS!MM22)4#k;3UM_uLB9SDqn-{lh(zwzX-E#pygz^
zHHk7Z5!N^8-aKWET7#iQT6e65NR;&t9z>$8CAnzDSUcB2%W11Z1<6=zj1t3+v(BT8
z<QeNvuVeJ_R%;L7_OsU6bdM!iXHZfh(Hhc<R+2S#9<(J}%cyKC#o8JRV5(KV5+u#~
z{UTgt>DJy%Sjw>4={1^ZZKF_Bmi4|BBIm5L_Cnct>vt3#zhE7vbzru2AQ9udXk9-O
zojF!X2LPAs*7-f4xz_IjKrUOa%Rut11#iLb73)cQq~%*z`J%JHnotJU3awvsqqE3b
z^(KZ^Y#pNaNr}~622yIRr)OuG)tzEU<<_U?0I0A&4Fj*zI)_dKRarN+qqExj8I|tT
zSncnh0<+ed_am5f)`~I!uUh*vFtmE>>QHnxSO>cya?N_O4!lO|7=??QtjRZlZ??{_
zhQaIB?R4MYupYI;?H22=2{3Wn8b;ZGR%_;J;M%MgC<NVZ{q#6)l{;2-E#P;p3+&S{
z86DOa=(p&!UMJmMR$V33bX&O;Q@v-MzZ-}i>lxZn-?whq32hIo@@Q!5wbuHhv(MT@
zrDzYW{Yp5~Z?#+id1Uop2-O4DbozYNp!K8QATng#Kv}q9>+5d=_t;t#Piv7U*58hR
zj98CQh;!81-vi*7wTr5$o?73hz1q07#RI$v>y8Nk9q0fBZXlcKIr!^jJ4+ceXWPtJ
zxVGOmMswj}`?L#oU2V_MKH1H-q!r5CZF}Qj$io)!0RRVV0f|%4d(h_W%a>y-UOow;
z$85jQ;Y?54yFq9jw^?3;QZL(43NU%w-lH(r30uQsbo$sH<U!KcHn$qn<!9USCG7g!
za%p1_U`wL<^+4Oq$#6T!wwhj_!M36$Xoc9E+tCWOJ)pYqleWSvbcWfa_DE<8w@nLx
znh4u2O6En`d?{oRZA+$IdyK7;miuwGd(q&Xv00{q#M`#h<1W!AqL+A*?d(aooorLR
zh0YXPJMAe`ZTIqlOS7FWh4-1Z1rIO@S+)!-TIXy}sY2_#t)rBdA{T6CO2TB@-lMhN
zMcXP$>gCv++@brD?IU`W=Gs=N;P++QUK#w&vwcU^=~rwjO6=s@a<HeJR$#k-3%o*G
z8ijI;Y`g#4<=bAM>$t@BS}x$Fwm>Q+E3<i0R;=7MWfA>n^a|UX^lGoPEs?=)l`ZH#
zMqh2)LlMUs8*2u<sI?_;g-D(4-CFRj+CnKxR&TpNVVedUht7##v)!g_T%)awb|OtS
zMjd#~wn}pJx-Ik~a5rqNlq$Yy^Vkh?%hrr5$Ud#bmU{}!Hk&a5?zh`oqX4{PoAWl5
z-nF5)1-FVVCJ=si+RElYvdd<tk4|*k-ln+cJ=<Z*^!3=5(gW(gjqe2Vz~=T8!|t{H
zssW(SR#^zw9@=70z;3@SVh0R8`aeh49hY_W{k1a7S*BLD)iO)7OfyY$G|a3l^Vxgv
z{g8gkdT=0ngY3P*0WuU2L2xhyQ4~;=A>w8WGW7R8zrW7w-h0mboO_?o=Z<sE{X9Fq
z+z3v`z>dQd(-_>bo*EzTSV%tEp&bo>0d#mry8!Y}c6=QK){z|#)6q7%BSH=Au^rzH
z0A_s0*<XPDbVn@ZR_$RtZ3X9EhLBQ7_c4}z0q6sal1>bQD<feoFx?n?qaonVc<l>7
zdpH=M9z~-kW6xu#_hQVYJ&ZR)B?FHSBWfy$FC(oFm3|CgTB`gRFU*AA07fIFiUcy)
z|G=goM%f~03T8~b1kQtu7hF&o!kF+ENGM|wP1a!y9~MYBWAYv7i(<6>3iZ(pN1hiz
zV;F9fbQH^YYz9vpqeBJkcm{U{I-0<6rGsB0qlj+QCNVOPfF+r+^aJ!Th0%Kj#-uX*
zD5)fkVfh4==?w8Ah-WZ(K_G`1AH{*?Fe7#;SdK8X^!>G?j4sMy%VeB&d<zq^7{|$t
zbBrOQ{F7|PUfQVVFh-rhlgmg+gJ2$`hkOpl8H?z|cY=`>hsu0Ltsde9jLGy97Bajk
zx^<HA+w;&{#CS0jET<S3n_zD-!$4<%5=K3_kWVwt`=YXxalnnXB4vy+6=2RVQv1=-
zvyAD-z<Q2Rx*3|zGj^1qRL=Ol0%#SCk{iITWR(Akwi-qvxryr-Pl^C~kx@x`RP~Hh
zn(Qwz7;?y6W(@xT4GoMJEvUT0@Sz;etBlMyP}#_6$EV}*$}ol~SaqE-m$oY{j9H(+
ziW`jgC|r7zA$bdxt&A<?t7v10C||jq5w#609gJ@&Dt3!8`7wT&PR5&bk@yaypH`l`
zj4x>ecaQNp{mc&;bH4<6#4rTF-fqThcYyUVEbzEHCiOFh=`%h9jQJbDGsFm|OHRX#
zh0_7^gz-TyMs|#$J&(3=M*Qm_PZ<aG(6ooCVFP9_Gt>jd>|?&xLC-q#ZUctWm3ej#
z2FQ)6r$1KpWP0?&7%%3-4sd!i|MxQV`7y84#?j%=9Gne>0nGn~(HPA1rOd&D%%A4~
zJA}E0X4`P)3M1Mgn9I6>7Rh{_a?)a$`zen;mid4lojB$PTfv#gJo`IJNz9)pDxJ)%
zn~YARF%MovDV_P-3@FNA$|!U82(xhvRvcZ!oD&4QGnvcXP|Rk2-~^*`nC0&RCYR~{
z5d=>#lU_tyKC|^RkOHQ64?SMYFGD8%GI72`LmRmBOb5Be%bAlRps<3erpQ$_b3f(e
zH!#a-{kp=uNzTcu%vd^*G&1%3AlJlPL3i)2GiUq(=oY4foL4uPquvm>$$XX$lvZZ-
z7ci-fDWXKycIF9kv2-x!(~jU4v&nHB@}10yyP^Iz^MDIVUCh0!A%B;7rV6EdOtt~6
z_n95vLhl3SZW}-!GMzlpvu@_iS22`5%=MIr(aStp3hX}S$8?J9XI4{=;Q;f-yO0}V
z9+H9#Gbi=~^9l3DUWkt|2eTYt9cM0-K;cv7^Y5Y;&MfbG2<~Ccr4*pOte0sn*~hy4
zHQM&G{-W^T0oE2;B3)Tww3fTE-dzsj&hnw}Cwj0-)<e#d<wu?+FIHnHh&M|&AL2f&
zeU!iG%i0zQ;>WtX{N;6+5m{eQZhio3=Nf1VWJR+86U2gV63-JWqYb7VWPO?qy&)`-
z3?!8GJ4G$SSaBh3zap`8O9K?fu*?skBA#`oA6-je-Fg+AiL50b!n73DM?U~Ml{F;{
zU}>yXMu;C`ZR<zdVb(5kyB=YkSP7IYR{ak^ImYs%?PoS?ZazpJ>!%jT9cTG(0?G;2
ze40@TS^M(Pc9ONn5e<nV7PA&SC9G!3IXcZ+{yT=dl-0HyeL2h876a^atpDg`KF>N=
z1I}`m?Gmi0V3pEgu#z>w0As3H$MgWJW(Ck|Tf<rx15FoLlj#;qEo=P-fYq_A3|LXm
zV$g~95^JMB?FKKik|+Sxz;aMF<P}yNc|otT9?^I98d<Acz}n2pARpm1*0hO`zs_Q?
zVMPl|5Cgq8SPLs4cayb^j#{m(mnhEI#+pE3=yujCIndC-`sNk{Zm~X~?sl@Qo*;Kv
z^0&wva+hUeK*c@Q-W}-nLspjodLOZ-(aPS<>Ka644{IuI^?F$$^g)O|RyO4o^|PuM
zf@Og9?Fg(GWYztI%Ev4_<=G6eUi=DVn01Qs0H3gYDcfy?^{p1AQI?njqGPP#ahd|h
zS;kbD|CCigLC<Hb@g=a-nSEM>UhH9CYz5iN-bu60K6b=RwC!hm(MiCCjU5agXZ9!4
z(B{fMF&&_8>?JPH<j$6h!0Ew`-2hHc_S#^ec(IYOg~yqlOmTJ}_H(pSIegiR1JUTm
z&ZvTI{_IUNK?2xU+5j5JUV9xpLF~tckO*ckUIKEEy*~*sA?*9Jz!J*N8V5@l`{Y~<
zLO474F!V;SKcJ;8lD(1AbfVZhBQP@2>@E&S4Es}hQDfPx|Nm}>gYCZsy@+S0SOJ>A
zUQ8#`ME0yql#<w2(osrg8|Z77DeMIcp(2&Nn&zoA_T69b!=|%$aG@}R?Mmm7L+sC6
zP<fcWY&p7ggdIvZ7mu><P?BCITS$v{7TfSSP>!+J)2fiocC4TyQw}@Q6EMfwZ&H-%
z1lw~LNIsjF3YY@+IZ9hAWam==?IgQ~3@u_KXo3ZvJx;?_%=V`juY^4xr<6&j+1H$5
zZz=mM9aqcP2g$j2hHZTwEN9ujQs%`uwmV%vInTb}$b<TF_B!(ERIsl<gNjNv|6K@H
zu|xKwt(tvxJ6LPjQ?o%Xu-h)8vX(6qKyMv8l`bq_WZU;cpq@RQe#uL0*I&@J%j|JF
z^Ea@UQ?Ak#_6t9t_gC33jiarRy_lYhCbo3B1C7n>)r)|3jlGh5_1D?6oS><Ny~_<Y
zwX%;}z|zKkhoTtmY*#v~bg&nUfaMlj69pBW>^O?B-)6Ur0<??mO<uM;?CI0cc9*?=
zA2{!^XGWp&KHF_6Dj%>9ZUyH<_PZmLSo(;4paf&m%|1o(k{-5>R=Qqxusc}$*dNpJ
zzMp-XBAWy3)NJ&AknQ6K(;l<8?T5e+JLDED9A^J<AEhVk+bdBTVY4@bjIyujF`{E^
zE*o;=Z0<T>K4oWp0P>8zEsMT8=ge6^Ki(eByg(SWmou0G!F`-5ze8d_XA-5=x^Pr0
zfqj6p>=t_A%IT+@DsG$_3Lm(0oc&Sq;4tXBES{Xdsvz#gd6o|WZ_fD;X!7ACr=il9
z^T!5M`f(h;qPzZ_TnZ{X0yue(z!S*X^ey@n#3?!oo?wpmGJqcBOkIz*5Ki5@kPqcd
zJp@C;I8!LwC!F)A5Ee#o4pR<5BxjW;42|OaPBGAE&N6b%#Bdh;4bE6jFQr?@ac-M{
z8PD0f4W$H*gQly*mpP&rL6bPSA(kCjjvj3RXa?uauK{|9lSZF>I?6G<jE-h<{FcJP
zEY3RG@txp&kPMbW&V=`2+DT3YMMjD^FPs87#rg7MR2FlNP+JLS(<i_@&H0L)zNMTU
zbi=cZQ(6nmvm6Iyrk&$NRKTY5oaDDNAYab;=NTF+IQzOVLY17dUr?&%h(q3Iz``Hs
z&PE+)R|YzIk<(4F(|XQQ3O`)pETaJZWzKXbv^8)dz60nLj<*X0u5uD7RNctgyac5t
zj(9e#Z{~dCgVHt5EPBPRb4uyMy)B$?D6#qm=L_09+~k;O575dvk_^l?&Pqo%Y-;DM
z>IUiHa3~sZi*t^Cm`+YA?T2o2YWJYj#hFPrbMA1SQlj!*j`=r~9&rAkXy-%DrW9~K
z;tV!|baN7uVOkGIoCjliIRO*!Gxc#MoPa<-$Ll$CX@Il)D^w10Drz05eawkvKw^l~
z@G^`V=6pyArcXHgD06;<Gx!B0MmZg?pmK~;cNdl8oQFQp^pvyE4dfZeLgLQchM%Bt
zA9v3G?~b^sDyVSb-dPWU1KefP(dNp%&<PE0+(BBe-MMpKpas)|dy&%BJh|HzLz5SG
zA%#7>x!x2r^5HID4MAV-N_v_7xL;FRgg>{Hu3rXlCr}b}Aa^4r83l2>DIYhOn_vXX
zLGGLM{D*MIWRMHx4&ip;q%f|QzTOee{a*|)Be-ketb+TJ+u#9BQQQP_tH*MeQubLK
zw}uvpc<y8hc_ncd{sofEU9$lyQn>$8#z#8$r!=r+a6b}5?hyCMZD1ee9=L+aOzz?W
zl(M+XBGIKBZYFJlbGhD><&($VH4J?xxc^OoB1b+qixP7RxW|8mibC!g+TWk#cG44g
ziu>SwU>9>IQUtez8^cF0O1WRr=QGN<9dx!j!+nK*-?Q9Hls<Wm`}uMxEa%Q^K&gVe
zKn;5<xksX*x0<_>hf)pq@<))nz}-We$yx_@?Qa0B<6frlT|HOR57tZEg%mct%+*{6
zS_8L_K1Xqd`vv)FuX3HfLuE7fDfx%5asT)Wrd{Wj(NU>|yMoR!H@JOvsK3eG6N^$S
z_k|+-K5g9ZUPA}lxj)dHeUCebHfQ&_j#=areZZYD1ek~1(0dSk#1+zsx`(^`C79OB
z&3qfBJ}!f<<_vH@35NU-ca1aJhPlsZ`F+AoA&>9~_rF54jdJsH(Kg0?FCB)CbDvCv
z`lsBK#jy7o*Gj1b&b$NktnJ}lcFcjqUS8G?6c6w=(mLeI^Von&H(nq;Chok{A)tBi
z{-$(bPu>xVGkWp*dZ5>vx0>AAK0Hf0tPkXkQ>s%CFXwf1G?<r7x$XyfmA4@f!mGOm
z%uwE1x@aB7n?{F)a9-M94$uf*DING?c`@W&kK;{W0TR!Xo`T*4UOBC;i9FY8U?=hH
z^yVb<4A-C{g?CyClFEC06J0yZ`<yNj9N}H0V9!yWiNXh&yk%>lK8xo=KG<Wtf5O0$
z%@d!4Tn;a=gBHwOp3n18c!JmSBCzv$f@(At@b=_DVIj}B0x&0eu}c6`#QXebRG#A1
z9sp-CZ&4!9N_a&#AaI(O^che}c{T5#t&BG^fXZ@SHTiHWcrpgWD|rhtU|JQ=@-n(x
z&HG77?_UkCm164`ct23`KrJueC4koPf@*=*z*Bt$v@1MEJu0vA0^b2zBd>oV`rE`S
zdH~R7o}IGCuJJb1Li{@KVL4Q^@cyQ7Ry%Kq&R-q8t#oDa7EeR>GCFywRUo%{e!qe^
zx_CR9(Wg5+2_CvhcX@sE!r$X*p8&0!mq(R7yqOel?ByMeho(N>3*=Vo=Y2N_vj=#)
zD0_O4_jD^bAM@%c?Q4iP=mUi#yge_WG|KznFl-v*z4Idk#(8010_-Vo9(lR&cXxkM
zILw*vO0LE|{7Tv^?d3ZtsJ4&)4j0(_`Sbn;ap9LHg2jXXLOe>I{OVT7dGURhgVUS;
zggkye{G>-v=*vH`4g=)JANGU2{`}utFcty)-K(K6gwH#QZin*yY4Qr=JED?+7S4AK
zgG2<sh?1!z`M;14DT*IKyZ&gt&o-!t;m`XPy-4IArAIG`-$svKGJkF><Wl%6C~+i}
zf8!>^)A;A*AnE+!W}sy7|Db8-5Pz&4U|IYDy7PXFzaa$nX7gWiJVb2{|84r*WiJ1Z
zQE1BJ&-@q?$N8`D0ds=y;R@`0{@Ynlc#{8lCgh9w3+|(Iiocb1&&B+RyAUYhOQIou
zn!m*jV5R)p6HrmcXUqpV!}l#lf6ww8C~x^3|7H3x!+E}B>o1_y{9QWK*6`b!0CR!g
zQ;89(<<FKtQyqVp_7WHQjTD!y=X(jD;u8Oz0)RI1d9?mD@jLc|rI}wIViruC%|F<O
z(hdH6+H&3Gx4#EtZt+);)3=j<jxv>R^IH<2p^Lxh6OcRnb;p2mmw$N`$UXiw3i;mW
zw^HhB5C0-%bM*4(&=#?e-xkse4UT4KnERNYMB9WR{@NPIjqtxDugxgG;WLmizUu@)
zkMn;ZkK0qe{(E%u8UHaI0$l|M4gk|l;F1b)cR|xbKzj)Owt;vGCN)FcOYnypEZ%~N
zHVlZ5z|jOwUqM7X6!{7I9Stb@3&fO-6(H~oL<a)}1$3SW5^%|B8!UK4>t2Y!8Vb-*
z!LI)SCQJ}w1ZTM5z8>Nc0uDXYQ38LONTUVulvx%d$bAW%ae@o^K#3PzlL9kAkVbyh
zL_sl~Uy=m9FVUQtDwy&nu+s$XchHzFxJxU0hTu;PKo1E5>1&9G1qT<P@`xaz187GD
zQ%QZMpyFNh;+WtF?E<p}6aE6p5p1C_f3AQ{=lMKA<;Nh$1zr!)iF|>AQi}@&9Xf~?
z3fAqWl)saLA~~>&1d$st2&V+u-(sAL1zA<FsYGz*6537+(rK$!Dp355!7me}^`Ue|
zFhrSBX9WZF#GVs0(ZqCK5J;;+xnL3bKq~~DM<HG*_?+D5Re}pQ!BQ<KrR@J2!J*G+
z&b%N<q76;0z@Hr8bpj_^t}hAPD2{Yl@at6cut9KZF50dLdg&RxDtPV|+8PC|Q_+iN
zL1I4It_i{@=jXcM79G@D1ncHO;SIsAk3en;u4#eUCRj~}qIN;gLa=lQT5h7`=oEDN
z0`0aSn2FjhK|Z-=?g(TZz`iS(bO>$t1P*WX;=Ul2zWn!4@V^((_DHa@5uNE4tfq;n
zM_{Fyp;vHtCs_Ig6DcuzK=9vekU_y1E%T2B>t{jXkl<|>hz|><Qi}bkLm+(zf@6YB
zP7oXyOu7r!r-B#hF6lD?Yd_?jg~ykmv_~j90AuzFm+ynXK4B9D@%9V7Xiakw#)YBn
zfUxL1+FXUzvmxLn+)S<lcVV6wEFQu+xp)FSh2PRz>LvVsEk?#$=xCseranR~d2f7$
zn|}bPpYSV6jPn=zE(Zw^-Vp;PP{_2y;2_~AH=!a}_|K0}aZt#Q1!#zH>f5Lc6^@F5
z5+=-h1nh9(x<Zf$Va-HvMhZV9KTniU_BBYfu-y}KF~WYw|8G=<qAxKfal%}>#}zM>
ze2-FsFoYJKL}3CwtVzOxA7N;+FoWE~DZ*)+z?m-GJqs!_gg??L?2yp09oUD3N^f8v
z5q?H4ilf4S>EO&1zP1^C$r3K5;N3A{BJJO@g=d~n6d*^K{WDl|g@yOfm?z{EqBF;Z
zGby3&gwUThb@{>xlqp#tyw?V_LSYNJuucj;Y6nb_aC=Cm6jNC*U4%L<{OdE=TPpmM
z5+}-pxs*|MMi@^XgR{bfgD9O7)=>V%d12~zU?~^&yaBZpLO<HDRSG9=0cMqO1<ldb
z!doAMrAByRKJ?WIQ<j2U6fUIQNxcwJAiOC;)pU@{!ePgcU~LeZPJvtz{uT?EtHOHv
zwHk%3zksJncyt_AGz;@);%B-htoK6Ob)kWh8(M@6n$>RzGp@tJo5F6S15Roc=F(Ey
zCKRuQc)KuwzRT4i{EU8(Tf(~($LSRIQZVbb@bwAga_$oTc><01gzniW-4{-wtd$4C
z-#!G-L*d(h1N4#5>H^bxg!x}VzE_wu0%Q7wv;TpLe&OH4=;44+bsKGi!UbOfWk{IN
z1My)Y7_dJUe%1w+5ux%fSVo1Db*LN@=Dtf)*;C;|3Lrfb?j*mkv&ifPvRCBtJ8aq~
zdhc75_KU8rfuM^hC=i?nL}?Uea1%*OLEJ^L$6>FBXfioNJVlOqQ0XP=`U=EbBsv6f
zU(sBO0{e*?7sDoh5px<U14MU5=sU%MqTnZJ3=$2o(8GhGN^<vvh&DVA&`?nh8=Z+1
z?f3?oqC^GjP#G<noe0xnMDu9tA1m5T7aHP4S+!7@AWClmcB07ZEWnaPBR4U4$sz@%
z3Z{rUDF-uEw1rlqbkTfTbsZU^gZY3tB$Cm0Tn>x&4WSoDM4Q4PpD9{31@c*<S+I1{
zG0}h2(QMHR+aQo58W3Sfaz#=)mgkAGH$pC7)IjIr0@0*jVRoTNOODl(qV*p_u1Hi#
zp@d@5;`QiDiRcF1WH{{*Rs9dOrJ`x?L1CHbKDiIih^)nEJSS4oyLn!8Z6oB%MHyKr
zRfwu7p|nz@e*+4uL|PTZYeX9<d*p&Bk`m`@MGt7!xhU%T5-jzinUwQ(Nz~VYZeJF4
z`~mR>kt-9Wt0G5t9%!Rz<881uiBgC(i&oK@?waTW8vN^`Hz~R3hA6)l*f&MaTC}x_
zrjzTcO*EU%3hg2;<#~08mXN=(Q?!H<h;ECd3jx+8DkFE=ebH~<K<<I)(_Y9u6fx=I
z@FUT<V=^SVMcp;%cCUz)541kf)z?t!7jao210w6cfEg4$pc_4pMe<6p42e4ER>%`k
z_k478M5Ou@rj3f2?}Lnq{v_ArxTrT30?$NmegTEfV$UnEaF2L5CGPGOhf_|*KJhmJ
zbXjS?_|!I-=pt6pvC&QJOnDpb;^Y3{@euz^8w*dd$7dj3;uo(#z+3$J1F-mr&EJCf
zioK?z6MkYBim3aGBkEvUfcOT*{sP5cxPb(T{mQ@@EZ(^XiVlh!DqvcO*y$ntPe!O%
z*aoA*#QP~9C|u0Fg#Jc|o!^AQNO4>xN>So&1Nsy#erX<5#E8FL1c6v_`X02!iFN-&
zTfEqf7TN@HKsiXFSb727P7+Te_kFThOvxuH;>&ZOAyr%^gg~13`Gphk{-ujQTMF|t
z#3__Mbx8a*z5a*Ag9lJLBECqQhofRw3OHwq-?#(8Eb)Vl5I812N}<4PvGOZ$=7?Y4
zhHf7h#|1**gxF^*IP=A?Q9A8OaXEdFr%1exKCp92oOTbT)8d=u7z;<Kc>Ew}nRsD8
z>^>)6NRRG$aV4E-%f<gtMoX1=jBbEbi<#d*MU6O@cDQxosO2bK6sJldUN3%z5ZR;#
z@oGBFToM0GpV_)9F5C$5W^uF&SgwgBb3v|)g<pW>ruZ^l-EDP<UCCk6Ce9--O1n5a
z0Gc|)9TP!riFLHA>l9C$0+!oi*ALLOF7ZcX_Z@M82Q0iR9?t{IeQ|3dN)N=#K11oD
zxQhH?kHkadRPPoi(UQ?CE>uIVPkf9fwtlgc9{d5ZV+U>e2gNJz!J5b7y;3v|iFKQS
zHZ0En9+gkTqQhVr5f@lt)2KMT2B2f&NP5=C#rG%@^HhAb2At2tk$SW_OM+}rzenP~
z0$_V3o3DYzMe;%*6dsVM>3HiZIa3D>Zjvt?eZY2?XcegSkOZ5->M0q_2CJ9k6+6&;
zBzfea^p%9tUdvD7&w(a?$%ikZEkLq_UgJQ?<k!FwBzc3r7#}R@q8C0?QoIpuVUm6$
zG=)p1UWGuE<hy5JiIxm)LSJGeF=>?76DzqKjK(-g3q2+Yk_)3ypD0;E4yh!`&VSLC
zEQw!@wiF42PDQDbjwqDUB!Qo!hv||&I!R|pl4%A%BuS!~DOb|{8wMdyQsa!a<B}yj
zRGyIBC!c=4<fBbMDUjS0(7(+VN~X_%rjwG}YSb1<tk0u#O7bBcU5X`a`V2vd<VYA`
zPD={D1SyrYPQWi(Ci#wL+cT2YlqG&v666l`=OnN2z;a$9oDI2hNfspqR!E-jf-#kn
zkHaBXCHdk3G*nCCdg%SDk+}Yb+6$5|C}p-*G9v-3b&}jVR9=*{lz_Ef^4}c5G)Us<
z!ps%PiYOR*Rq{?hDw`#8noO=q>OCQFUGmErRJKSwDf)IpGNT*<HzgY;!nAhDVoIOt
zkgTK3$Xk+K_dy(;lBEM+y)C&K1^F(?!|9N?Bia2tK<`RY=!1**B&(O9hxa8@Hlg%D
zawHJyA4>YZ!f*FT^7B)ax+Q)$fYKwek{6^`QdbSqCs`2<%zjDwPUszw=#PPAP$I2|
zF^?shOtcL-ByUsLa9Gm#8hD;aYAyhDM3U7FGAh|A0`{0>`cklrOU_d~=&7V{F?#q+
z;zKDZ&eDsNJiSLc`vT0~D`k*#VW0FQ4at6KY!ei^NH@@{c0f9z8hTx&|NM+fH|ZM`
zMRS)r7Jm)B9@6&f(BvtN_Cc+e^qotn^p-B8{f&>bm<}8MQV;SH2S_(+z!E5(L^)YO
z(#3R;50=JJ`1_#rkrLP;(l`1b7b@Lw03=NMmlY&j`U2&!L`Z*(guRi{d6YC0C4J_g
zNKUl$omi-kk-kp(7qQayln)dqJw_{aywphf0SVG~&O=3_G$#@;Nz#p!$dDq9b%jl-
z(lna$)1>cT086^`;%>-gNV|;~!^6_@2~c=M`d%3Xj!H-9uzpO+rd*J0>GpC56y`t$
z<a4D>J5kD$exQNE<I-;^D0V_Rh0Z1U(kV)S7D)XlS+!8Qiw}X5(q9DNERq&erqn4Z
za~e2{rS){<zeMWP1ofw-!_lZLm9|WTT$%I=y_;vGZQ<zPS?S>kwEmrwKHUqW&P$7F
z*)Ny=PA9Jl=@m-dsg#cCz*;5sr;GU2(yu7IStI@F98_G8cKAVWt&~HjsygW=y4-b9
z+S>|&dg&C}Z(ovbCU5*@>1nzo)gYY^fKsEhk9;ak(huRsc1&uPhDp%1Yto)#)Lxg?
zWr4Iv&ypkUhBS=6oOV;%AqHrx^x_F<YLmV<41soO8tsd2NoT!?u60V+K83(->3hj&
zdn7$k4ALzvq4-me^fGx<dZn#}DD_FxX9KKXno69G0jY>QV1rVBy7=-~+OZB~Ncs-V
zlTW0d8PGN&ed|x?9hLeQpmI#Qh>6N^=@|Kmo=U%@dz8<lwUn8;M;1y)pS>~>d64(X
zg6TMQKsNI>G`Y%le~L;sS>1J%+-0saQSxxeK4E}*%FZ;wHZR$Ng(!K;hDrhIBWt9e
z!dG^HT;Be&B1*swkl7Q!5-59Ik6r}HUZUSFSQeNGO$TMXT%d%=4ljm^Fxk;0h=<F{
z=mCz9&1!>Oq->%RW=F}kv%nG~a}1K(Ggfw=4q)-JEwm9!kSz?xSSHF^D2q5n_Q^WP
zr^;@Se3~qdyc5S{*Q1~*TlRGj<Z@)6&VUuUvSeB*^JIn3LGN)HhvwA+*?+FkR4D8I
z4wWZmhhK(Vkxbcy%2P6igMvlHvIq&VOJq(zK;dawCH&HpN@a8CPEDCiPdSliWcAme
z_pEH%3<#W;y*3>J<+86|24{ur<yw>~WuJTsE2?DA#ewsJ?C)NbYGpsuYFH;*eFUY8
zvdOCfRxit;W%rV7Cx^~|mt}kD7}+2@yB>m9WU1tdyDF3JgTalm-Q>Awk`<(YG|Ti9
zio7Okr>)3!nR5#)Y>~CoXBTeBJU;`uDf1xDb*pSH`DEH;#S2ktmrYMae>-I1v{k$%
zYiWmgr>rTGQf6<<7<9tzl6lPr_8pny8U*jkTqzEGPc~x|ZTDp<G;chR87g4tLs<YN
zU_6qw-a=)!tTGFvM|N-<Kzn6jbl0O#rlP2BzbuA4CId3V`%ph9oAv;u$Fd2us13<p
z<50YOSmydVYM;pV_Ceu@td|e8QQ6xns2G#|J`;lDvMFw0c`93Z0d3D@-R0<ovpkw2
zntSEX&%rO^B0o*1x&!if`k7tjQ~m;ro7|0@eD3mAa)^1z{hmjgr@W&M0$%cr8dN&G
z<!{lG?<4=5CO=<!CSA_-lc!qH=r3=kNjE^gkb;PTat?VMBjjI~LvN&f>t$d^$$$PH
zZPD^qvQQZ#pPdWrSoxJ7VN9IdkABH``Ll`WOM-l6GfIha^@os4k{_e!YO+JVm|p)B
z`PPpipDHh)w1_nMd)pzAE+4)Jv<&$V<Ul+mUqI8=VR;|9Kaa?Z=Av{|zW*dRGvz1N
zpp+%wDuBQ-`PS8_%$6s$qcTVS{lBm<S3ZFz%{=)#4<UYB9=!|3oRB+GK1MNL{w}#X
z3*<&(EtET%Ab3*#8>M;_$(K+V?38@cQ<RG3|Ej@RBL8?DDo@M5-hp0}$}fG1{+7u%
z)A`_xe2@>8vvQAMbm^SDZy7kt<u5(OV^tv^dLJy6a@R#rTP0uPplfs0@|#~nqDFpr
z10*iUn_dT6t$cuTE$Za^nxW#N{5b82>*Ylhx4R_2NY}wG%kQp(y;tSmEJRzQ{0DMN
zG|3l}FSl9Fr$psza(yURuFI#=ShUE$Ujn%saxOVQZpy`>G?uOM=x-q3CSN^*+IBgg
z9O51FYu*sNCErX(flhgx3qWtnedx^7B_G%em^*USe_**Qe|{Fsz9(Pq39$R})|F^`
zAU{vOvxo8xuS4LG{Ke%E@0K&j`P(B8BQJHYe1(GiFMaaScIfSw7tkv+ApeQ>;)C)f
zOJT)h`M2MI49Tbd1i@i>C2ifF$m=ga?}*&~E6Aw)RZ4gqlULC##c_E>Cs3ZsyUi#)
zlSen8%~|o?G?=ze@y1aI>{l#G0E&wu4f!UHNp6aX<o$J59EpJ@55=<QAn2{|-T~sH
zSl|QmeHHI~4;DWKCStr5isO{26`=U;KClB7A8bJ>ND-+A308Q~e(a#aNZY{>MbKiD
zLKXjh1I{o-Uq48=;+-6zL@4h3hF&`&715L+9i_;lEq%1&k8voBQMk0BGFCBT5<ue=
zKa(drUZEj3OoHOeQnV#1@LElnl%$w58FI;ric<6`MNvYIlT^jKyHLtdy!JJ$IHY(%
z2b9B#B^@v(Q;|)NT$ZAn@>GsF6eC3d%~p(+pqQhWL_zpmh3OSk<|$^)hNZ_9^>a~q
zLNPTEmHCP+DbNZOwd7YQRBWvT=t)J?rzjOE9&QIYrHBiG6~&4&I){}g@+rP}T5*o9
zp_D2<t_Dh(;ux*TXA}-r9Lztf$UKL}bBamyskifr3FJ^HSLokC4=WUkjX<kZ?50_|
zN^y*qjB3RY&GI!0Ce2e96lJN<dr?tHS!?wQe*r2lDV!;_>#{;U3E~ZkEpMRhio#6~
z4NZzTI*BwZW;<R*?KQ<;1t{KCJoJJU_Y{Br2KDz9gHOQvKv5nG?1zdI$1n(w6j`|d
z?N$gV53xs4lnuFF#g%fD`V_yA+5L)EO2rva+*$}SsHpOThR2E-l<zX6(ALBHVTCuD
z{Y0^oNBhqag&Spzj4E<V(5ErQd|C*`6>p?L&{=u<Kfvr!j%GmbUS(St1otV|hM;o4
za+wE+i!xvY0tb};YQW;EjG=raH|3`FfOc2beuR>T@~sM(=BfObB0*ltxp%<nt?YW2
z!rwm1bei>im7l)^9zW$cg<k!YjC-&&K*^w|B~WSR0VYT}_A@wxmGfu?IjH=bUYro+
znx_y5RoW?F5vIH`0V=|k&y({iLYcz_N~DtIi&B(wh|-y&l_n3!#VDuZo~mO~tnwrq
zpmEBp+ff^@Ttp94g0h-Ep`NIGv;)JIr0k;?C|UVGCumAh?!Sv4CRO<con+FK`4s&~
zSH4Fv@eJkli4Z@eJVyKU!^%%Kp-V@U%V_pEs%(B9n3+l!IyYu1aoGXy-!bLxX`tE4
zRB{C7D7S8arMXH89WnEi+cyF2xUz)eN+*<Q<WJ03UMd52fl?U(QmE|S2fZhiRkVH;
zDgD+%{FHJog@=lj4T%saQT}ldm8X@bXbvn@)=(-<ney)zkTVYDRXW<9RenL4Pv?|Q
zQvrHj=}Vc1<;r&`Nw-4zK{K!`l{?;mM3r*G2~<`qLut5cl$*)hU8gLd7{NtlIt6d)
zl@FQ$c1f8t0Roqmf6z?ape$aBzFbj$N$G%Bm3w^A-A1M3FG|#GQa1bt70t^3Q55}}
z(vgMA>q;luthFe885rjq$_2DJY*WgI(ble9MpvLZlrv`n?Uu5Jmd{RQ_-vScTPa$F
z(p{zU4Y1r(Zu=JE_m$Cf{(GdXuSaFKvXC4-J<5#^$`S5YR#w590p(3P6%H!5(A@o4
znSL7v4=HafMcc44ayCj&l=Jogdqn9@$ws5fOSJ7CQwCBh>9}(HYcTDpG9wKF&y-5a
zxN=sF(3b=DsMdcA)Ap)Pmq2cx%873N?^nfbruENNHH93IZmQcSAn2~TM-#G_>Si~r
z@K*75qtZuJv=#Ecst8IR@KZg@fPlZMuoVgeRIi?fra)B{oi>70m9N8?U{w<r;s;gP
zv}FrXJ)=h_R28-WZDFcA*MS+Xdg&(lUm{fY4`EcK>eI)-j#8~aD(s|Km6{0^ajGGj
zL*rF@l)z3>71EQRtb)rA?}17;1#PLSrGLY;G}WrfD5b03d<J7OR9-JZ;E*c+PiQ)<
zTH%Z?9Z`+Y2bPbj@@*((s($~S;tyG>-`7IZG1WjLShH0<tI(LE%A~13R~1iQ+&mR0
z85ZWN-l0^00@ZszK}DfzA>EcQRptMPu9d0Yc^BemRL+!pcUBeo5-QKBf+)ImUbU$n
za^<Qp8EmRh{jm&km8zM`VT_|nRYM`HYSpwJG}frzbpyGedP@RQt6Jv_O?9fTmP7qT
zRZ0%9>s6n}gIrR*`UK>PY6Z<VS5;rosjg9Vn*KAgNfkjWWwR>kF7#egMNw|nb(Irk
z(6*>b$TfRIRT=>GZ4TA42GDj@7j2U|RMNd*y``E)Tc}Re$8X@LxUFiU%$hEh6U9XC
zsQybu>8@(gi{N~q@}`?x4^^}OL`NT~YA8g}t#T(9c8}`e+YsngU1OrMPjyiR)B05(
z)<NHZ>TNn045=JnlUHR}HAc54o~XW}@c)SF-WbqERYCNokEwLWAwRAv$_II>^7t1l
z&r~;eK*e75PxX-7r=Cl5{(kivcQ6R9>T)gG+|-xJLU;8H%EI(g#|^_!Z}p!Pne<U7
z@lf(t&vEQWF+jbQ{xu*_olC*jgKFC(G=`|hR|7j#J%e0-5o+c!lp@s~v|vW5&6M$x
zsQyX>fh6?@ohT)%D|1mwQE#M(PO5s|5!joizWfki>FS$wlFv||q^!3?>bHwfd00I;
z*a3P(y@8xiN7ako2T!Kj^(*jXsi#Dt_s7(m>C$hu`qOhzpQEllk5aBW<SWSKsb|ue
z<+%E_&!O;y`p8MB&sRr~lcPX=O8|jFwOk3zlj;=ujBt_q#rY68rT*0w_7<z1Tq*ss
zME#h;38&SgkubPSeIWs*GwT0_AaPcGntb2q)Dbga(|PrJnk~!KTnY$RsBcUJTBSO8
z0Y<$_9kdUfs8*kh0%whSE_tRdsAJ!SX|?Jr^HEu+{%0?sFRIJwla}>rrIy~mOX`YD
zSaVt3^)J+4Rd-$nOrv@R`N^8pW&5Gxy812hgtw@7k(cg<x{Ns6)C*~A-L76v8H*k2
z=o*x6sb5%uQm4An7bv&Yf0IA{uKL9<LGGzn(J}qL`c=wKf28gpkH4c^{U&An_o$mx
zXzW!lq`ag)^@X?5*snemgUZM1GvSaJQdhkVGOX?<Kjx^qmJ(jZ)T<VNb6lM~4%3`9
zpP)~Z_Gn~(qHV9HxfF)FXx^KQ$^)9DwSacjl(wPdrV*3?#oeI^O#qLFCc_uRUsExN
z#sEzW1<nICEtTL2()3UQVzA~3J=O;`n`qw~qM5P~101TcZ@|cgY4Uo(8LnZGK!oPG
zS21{z8c7mLQJPja7!$3zvJw`?XrynWEml*?fH83z2gd_6UbC?T*a@0<>9<eR#M6;D
zN%J*jMI~#J*FZ&zChIENQZ*aMyO^eV>jSi<YdpPSMTW*g&XGf!^5<dbVa*qlpy`O_
zRskxHYSLx{I#VP07(<z*`DrTTj%l2<Xv@}!9f2t3Xl~QvnXBof&wS=-&R<38xTdri
zXeTr!zCg>@{F(|Y3N)FKP+zD?I*!VdnyXb1FVfsN4eV2zRdfNYSTpt<N+p_e<v=;D
ziQJCLQVolGR;F3@7fNR|{W_G+YBrvt_3xbKYgZJ{YfgngVY%jex?f+R*;$6lN{!Qx
zsI1aNY{CyytvMb9yK6N2D7bz>GcgEO)M|dG%&R)hL4TAkX%rN1xvcRcuSkQ&`y@~r
zH5LA-Y|@Nv0cqB}(+0C!G~u7n`R|72)!h)hsj-Mr+phU*2GBY*etPJ=rQugYVV6cr
zhu}M!=@gB)tGPx&`Fomg1Hf`$^D52D4>Y$v0QN)89y(w@(ge{dvRhL^(fA%s1U(78
z8vUF2Df%=6lwmWVVLqCQ_is=$jY4*hHCwkq?~vw~4Uiw!<Sc-~CmNSUkQmV{p;*DF
zX8t_1jcFGAj>>UOtp$VdRPzb_KF>5$$ob{0U6hBmJ=(-asNAc)v>lrEX@5KovR@lr
z2P<5(HC|{tpndiQz#OjH1^+)=Yxi|S-d(HX!x#_kVK%TmwaPQ7^wOsCpx#@XM3*Og
zw4d-{ny+?S95nf9U-=!J{@RilR0e2YB}YV{_J@za8KgDLLuIh`Pz+EGYL}8zG(@|a
z0%4)rgK01(%%M$r5j^4A@8`qB2<<;7pgvN2mVz)*+D)~vG+O(NR@xZtS7qRg)o!A&
zcAPeRFWTa@i+%-Yg7ygI^(AUu8-SgpRc!!vvUdLokQD7pv5-sE&Z2oLO`AvGqe<6F
zXw}cqIvg}%9MayFgB;dIR{;BncIG<39M#5;!I(_#tM{NjOS?)2iDTNHpMjRGO_&Jm
z9PRQ6V9C|?(1Vz#t#}nI$F*kKUY*b`J_Akp+ITD43be1^MrEP)y;M}5)ZTp`r6O&X
zgCeV^w49YNzgU}2o{ti3JZ+&)Yy0R{TdDR<+Qyb?<&@rZMk^-w>sjr*=TJJQJ*|TJ
z^V($cESGC%a!{(!-lO0`rS=J(ldH75$=6@4T~AM7jn<b|vkTh106^DjpPxtXU%mG0
zNYq}^&RT-fWo=#?N)6gI4<LU<yP1;ZuWC<F9&n>}kaA<1w4#@Q)~v1g0d3c`?i7l>
zuJw*Z?_0FXC~4w`Ryqv=H?>o9VN<I%XglQEv=Z9fwQEyffrbw4K^}c9^p<uGIgvZH
z`)T>Tt$mFy2zF_$Qk3p!ckhD4UF~<YnZBoW`4KAaYtR1;y$`f&;-KlFwu`a=9%*@-
zz|yVVL8+EKT6+>Wd$nDEpt4W<2VH;b*9OqKJD@G4*=|sK11ECFq{rGzp5PhM4!w-V
zVeQJ9AWyW_Hy}Tv{beUuN41~Q4tq?ir<-!)+6@*A=~L|;%0qdk&20s?vra{~;r8gx
z{)DdW*WDtwyo+us<)|FcRd#~7>SodXPdA<33t;ZL5iaB$9=b`(V6dmoo%|tQy5o_k
z_0}oqZT8Xq^EJ?Xb&Xx9^wT{!1>&#!<Q-H7=$a{P5~yR5hbTz**oJWq)>TsK>_MG7
zg~LO1r^v}4s%xX&WSH)Uuc0Aaw{{ez2wgCx^F}&!TFUi`(uMpC!DwBq2@)~7Z!@4G
zR_8;W|2UnRGPvS(B9c$gy}c5qCF<r-WHm|0d<$*Kx_RCB2~%{QO+ZQ2eYy&jX}WEf
z!I`eBrPR_4oopxC4(Vd)Sv#!r<v`$w&hb$`R2<c5zk@ZIx?RV>ldb!ZZqDTB803S_
z)xFh<Ql8F2b|1&c!om|e;bFk!>*h{{K!NVt87LL%iv9-JNq|A1NY_TLtW&yulmc~H
z7e%jFsqXY+kTPBJ7;HMHQ#(4K;=Jy{G4Pb@TIi9l(tS1z`D$Gdc>rs48ah_h>9&&-
z>!L1#(thf7ue}Y@tV^Ig?Q6R2$q=}%yPO5E7TxGo2;9&Gk>}&4&ar`B09_R&ySM57
zUXN0{?veuH9lEX-`eer~-2s~JI(0*f!E;+TSq0LiTXhONcXZFuwTZjBRB|ic(=kiY
zc3+prgx&|b=bIt^Q1=GTW0M}~mh?cNTUXZ$^*uT{J%PQtJJgpxoj)bU_Up#TqcxyA
zQ4P*P-CrH_^}fft|73s}(v6;l#Hj9ldJxBS{-xj<*WD#w)>GY&IjDT5E6f3mv%YjU
zK=<ftO3=1f|5-3>I-t*?<;Yd<y%=(C`oHL<a@YTG5yV5kjV{M{>a(BWxAW5PTnjmG
zea3h6^)O$313gfF`b~5d-e0dQ0Z)LwEFCa`dM*p{L3$NkzYEsi42PzJ`r<QS3DN)Z
zKH5U{%Qu3A>l-OqDng%@4htjoUu6R`N`HV-OQZFhZ(@LA^{M2Dh|@FZbQ7=tgie@_
zMEzhYx|XE>qYWfke}e~@RDGc<VAAwK`!F);`anuq$<X)F)v-hR?k<#$>hFJuQl{RY
zys%mNV%n}B(<_yz%+?P{z>=fCw*r;9`Zp*FnWyjX0_Smk!$Xt`^iem_!NPa-qE@h;
z)X#ertVQ}p%JDy?A4^4Lv3_O9OfP)aW^^-*IivsiHhOVZKl%sS&grvgX+N*uw-RmT
z`t2RiTcLmTM|7f6f0pd6(*OJgdVfLRI|7BZ`m$7zI{oT-sJy7(tc7^J{(16)T+$C5
z#28-If02*M2K{6e#INX+KZ7k-_0t@UppE+0pTOFr|0@rT*Yx+tpzyjrhaS=vebG*k
z8~W-gfVrtJOb1J=zLwtGHvJXa-?!`AufzHd{ogLI@RoiFADTM#-*=<(w*Jd}uypDB
z6Cig-@A?7AU47s#RNm7EhtV1BzTS<JOdjZWM56JbK5`mLkMs#Xu&G<06AjX*_qzhp
zuP+uuU_f8u5A{R(*C&7s>ltvjO?slg`~k>_elq18j_M2FL))0XK?J#H`d{cff6j)X
zRcPB|KolKYCxi3%bVl26_?Y%LE{1IKe;zO#rANrsF!xWC+zc@cSn6)zb^^x3@CmK=
zo`&~m$?-CrrG22cK}MJ9{0ytf59x2%L0RJghVDN=0uAy(SP^9SnWDA9hO0)P95e(`
z%5jL{8J;f3q)>x9?U2I^ljt-VZdgPUa)e=$Gk78mg_P4BWpMYQXWj6W3HcZUcL?Jg
zYp_p+K%C*dF6fOnl<q*E5)4r*K~f9>l$?@k_=v6qrWt<j1xva?LT<7Q!*6FGe#lTn
z&I!k1!;5E8d&Ka@ClEYp_?#~9W*W*U&pgY(Duv)N!^Imw%Qo!tfWjO@NE1k|;pLY>
z@(kUF!E)Rn{urG&VQ`~+?)ipZ3cwW@KBNSpLc`EAjMGWO2)Sm94AW^3amw(02;_<#
zhWW36mKcVQLE&k`PA+<1YFIu69W68b{3<HX7_#LMJZpIW3{;#myh+I^=MB}gK`1vQ
zE``Dh7=w;h8b+>yR2i~pvs7)k+X~Ja!^R?LxL_Ek(^#!xHU;(S42{V!?V`aEP18rc
zVg3MEFBz(63chS$)6~*nXqy9Lt{7a)(b21hKTe_4Xec5_e3M}vC0sWfp3-;PuNlH9
zAbj1hfToldgN8hDHw?))QF+tQu@4$r4Nu9R*JgNy@{`&P#S{+fFt|Eyq4u`nj2{HM
z3@NkFc*kI*46eHdK7Fj_p5fkGXuEHSE(7QTLp%}-Cp|P&Y((25L)>L_wA&Cwe#jof
zR5Lo-YdAvJ(fSN?#vssd*f$@Q1BMm~X$~3I%mwGLA^bMlo*2HWbHMx&!+ugfYT(c*
zbj;9B`4!`a49Zb?YM4nu!DohNGhmam@d5qJdyKQmjk4F+dk8H1jHlgD+Hc&O4>?!k
zPm56LW*mxvfV;8vK1v?OeLm3OY5bWF7BAy-3|Qf9tbdVwls?8Q>rnJHe)|ew{ESoi
zu*u)pF%y~sjI-#`4K#Yp1x%1}UK3b?jico3J7|0~87e}IIcji*8oe)}EzI~O%>v;@
zBV~?682x5IVWjaf1!$s-iL|?lHeRBfv^e9>hbQ3ui#ImYRGMIPC$vPPy&618Mz^~d
zuVmxo0Q5e^xP~^`sm4_-fTkJ8=Yb{NxZoJDGmMAn*3u#4e>904HfB?N_K5L=uh8F2
zW6DmHvWzuhC>=BM?JzXkXi@_@$LK^ku#Q|~&VOjkGp@M=a@@Gq3eXeAoCy%jH(ogd
zn+lA_wnJf&abqtGJ!Sl-4wc2mH{DSxHP(ti%8YFCTAeX&R-&V4jf-zX#W~~ei%>dm
z{45)7<wjiyNQKcyhykiJ_MC;Hs*tFFi7z?6B%el&aqZiHx?milC%o3!PG`?LV_yo`
zFB-SdMX`Eg?{?_EWb9uL;LFA-Gtkyx?0ge#SB%%<fOyr&y#tg+quU#3YcghifYE6-
z9$N?v*Nn37(UI%Mzg`1$i*Y4I-EJ8D9Y4U@o5oGMptsd1k40mfacvIJ+Ko$Sm)v1I
zPb>H><Ba_voyM?#p}xzwoe8-+#>xZ0zH6L0A9DAMOK2s%Z+wI9ay~Fh=_=bpqk9c1
z9~rp<Sl?|7u%oiaIA=EGdX0v+C{el37(uzG{YDuwCngOT_YoO1#^_+hW1~A0of$In
zGXXkm9H)<nJTZPx$IB7psRqD|8h7;obj-M2gUWHEDg>II8egDi@|jV>fuYW($Ns3?
zW7^~b&b_8X^mFVpEp{SD#eUPPRls&J)pTP_4w%yF(dcRl{T;;3lufsD-A&&_qvT<l
z@(NfyO-$M~dYOKu&8N4i*&oEmw50$nzNT?<iu;)^E(P&74K|`Jz!Xhx-9S@1#o2;P
zYg2$3Z2A+<6UU^3rsmzK4Kd9>0*O#l@<m{WnQjK5_u(cnd50rRM`F>LNYgA@3ZqPa
zQ4U$OsdFRbVobqnF(k33#pIQaGmY%U&lGQZDHvmzVA{(9OQPu)Cy*r5AC$0>Y%;fl
zGsX08EKGBxnoK_fG|jZ$0)^?OyPXisFts(H@{mdW06d3HF5g1%h>2kYIcnN41hh=k
z!vko`G8KeF{V~&W3a)0GJ{tyhj>(6T6powDZwKcI(?3Ii&NuOs09{~un><K`rr+*B
z;H1NJ=XG?Z$mC0df66pS`Dw)_6CGblOq^h#oi=?;Q)Q{?{+B3~nLH^I?u;ptHmzq(
zvJ`NhGfBfCe%>Vh1lZ*!9tH0zOgah)RGI>AgR{!CVmWN8HWh?{)R@9cp!R~vv33X0
zYE3RL0H)4VMCXr-rZx0))tibbB7e!0<chY-rfqGgY%s0RqVkGql#;lvnntRiu+da^
z1Z_>G^)#6`n>6w0=rz-tC#bw`I(iVL7E>oVNN$+^y$*8Ilq`aUttR{b|EpJ<$@nKM
zZ8sgD8!H{A>3;z9mTCVklsZj)bR@fNT1E$eF4H7;wB0c+`u}yxR22i3d#3kt!E)cU
z@?W4lFnyYj(nFIn5SkvDzWND+-);J<2KM%t6to}cHMQ13eV@r?25kcSP480z?tn>0
zc}#<*PmiO&k4@L_0A|Qk%7nzQseU$Co|yO)_Zl(1*9BunO~2Fin=w-%xo5{s*3Y2g
zsYy>M_RmcJBZs%M`O{=rvB&)V9{}5HcKi=*`^+J<AJ}j1=Tf4UtGPcHJZ|Q@G-bM*
z|5U?Z5A$9RSm9}|qrIS)IdKjuea%aKAn#|^(`@N)?xP%~Aanm#*c5C|{1l)E&1Wy7
zGQ`}e1qn58$wy_F`66xL!_8fkQx##3Sqft!%~M~e_b<w98vtvx*=IL+V$3NjbSB<>
zDhVnQ%mz2GCYpDaKt+=I2tC2c<^)P-NHISm7hSs9na)cY=F1-f<&Zgc721xPuh7V3
znv3cDkY!$P19XnLjJ~LvYcBr?V0q^Dbg(#%o9EGH`-C}w{JQz(PX@qKU@jp?f1!C5
zrC*&iUnB2Dk@*|C*mug@L?6#8Hv4@Efl~8U@>P|YZRHreGv?<OK;XRD<9Cp9v)2`n
z3iBFr09ToRYXoMsd5#P8)|ltCL;Qln%)Jb>T5~=f_v*}ZD7opPIhV52>&-vWiSUy7
zWj%)NviUY2l?`Tx8CG01m;H=Kpwawn30RuUQ$;{)Hp6N>`DPX6i(EGc^+T@3%&CHf
zH_V&{u-r6Hp<MG;^Y~=2beJ8NH$eR@v$hUB>@?p`fQh%wFVhp)WyTf{&$_up2$p;1
zCfZiqH?wmf|G+$nHZBj%ZPTIfk-3u+pSsN({b5><d5=33_L`4Ogj}CFkshml^G}yy
z%z*hRWi}6*E39C7Y<6~#Lukl6|8*3H&7xeOjhI)_>3Gz9ijEUw<~1~3j+=M;q4KFY
z;x(A|%)H|_2sm4|P#WSM%Ln8j*=yNB_ty4Vj?)<Kw|q<~doGqIw4Xj;d1F3^t0k2V
z4sMo(DKO2`!mJ`kp_e7{QyArK3GV`opXL2cDEV8Yq0k#(v86*W(6WLOYJx1e6r~Kd
zB%4qQwXmN8Cd~4#4yAC*>^`(bSib3pX_1!e$q<jSY+Z<viMFU6V2QB|X(146smOrZ
zILqb_DN#Azl2Ht!5-e}61xd7AehyY7SxOQipKSU3MWCfv-i$(9s^#B!w53_9vVnHU
z;zt4Q!<Ih}W7LmWj@v<wS`2cGQ>LYT8c3F9=RJ@d%dg~J%C+1(4U{~~bCegFZ}Gu0
z=$KSs86rn;p~Za`6rQx`DCw=pGLH)trz``s<P=*nKZSgWC0Glz)0VgBQcS63eJI+>
zEQ!G=ow3{`2jf}G;{PCi&hi7z`R6U}_o1-dVwnXE6_)Byh*w(XQjoODGM_xKj%v%H
z-+*0X8CL`Cf@R89pw(Iw3xHN<sqO^pMN2vzhUzV|uA+3wGDN=9E0*Dv;Jj*C-HXmN
zTK*#cTa#tcE>t#KN<6@M&C=nAU*x*wyJZk)u~gG_^BWeP6<{|l<MhWXtqw~{C2HF&
ztu#fnTTVAZu*32{BN}g6dc1(vX?f)i?7nTOSq;uEOAcK{zhg-}kJ4R>u@1esXSp^F
z-M()b>_)dASfrEDrH7V(f>3&7c`F;7-If5#LFuvBDMr+1>6whSev4y&Ggt>K>01CZ
zXkq7pJho)eF?Gl?kuqwAEw@)d;)%tR-my_jq#b0;a)<VT<CYbZAn?>8qOi&{i<ly0
z&el6?P`Sq%@;>DDS;J^9*>5c_M4OBC{R6P#fc2a|h^uv-gCe&c*3@7WJ*{i(VD+-5
z(U#BKIzq|uKGun}%l5U-cmjof)*}zl=5PIo(k26}5#$XIwDReHV1umJ--n7|>(wk^
z9<&BK0W-w<gw7A4Rz0N{hFR~@4Y_b@(na(-!utLf<S2}^#?TBEWi4HeQIEFnDgcSG
zDncM1YyEQ{Y>KnKF9vA5_4oOZPp~GFyCu=OmHg&O)+(C3lC7WQ0VTz{B?lzcI+eZ#
znr8j@6KF`c{(ce`9=3`W0qls?;0)-a*0-Oh_b=0WB?`qXYuW4IIc8lz+sRz3mLA<a
z>!vQ0j$4l&N81VO_ZFznxAqsqm;&o|x;R~E4WpggNvmQ5DvPX_X_h}_ZKpj`vGrXU
zDod<$55vMzYd-lh%B)wX0P~D>{c*Z;f7Uv%2es#{xh`NmZ=Fq7H_EMleh&2&)+ux{
ztFk&#RH@qfS`j#Ftmi3IbiukxgpSr)SJIBL&f4-EST0&!Poc8j`p<l@T(WA(TXWg^
zDhs6sYp6duam8BRg-%?xzW6Rmjz;Ty=P^)C)@aJbY_@KG4)WKmo|H{>-Fmnfpe@$v
z^t9Zt7E<ooP3wG0;A^!el3TdV`to|HZ@1=XpsB;^O{t)_txIVl@3O9@o7Q)%+$8|J
zXZ56Xll#^>$^?C2eT6=d`p{wZrBlNrYaRV+-PS|fps>eUSP$%8>zkPX?X&XNgQeg4
z`d5%2us%=To<Zv^2gqY<!Z_N7tuBKQcw&8vR^bur!7Rv)TG#T>?J?`pwP1N_eV+RH
z%zBONb++xvg!(-;#}^FPw%1lk^Xq=w&UVPV*nASfbHH|#Ry<eR{W;L&X4^rBU3Xi6
zA2>a1-2YJWw2hD_$;&o&5G8NhI1P}G%}P^}uPu|#Z+^C7ihTOpD(Hm`utlu_OQ7uz
zxvGO~(;YnYH`w+wIrR?OKBGNIxNY5akO<o=ejt&y^)$am+45Y$5^b~o0QneO3kB9=
zZIj6R5oeo56KlMUtAN4;+qDvODamH1=OWn_^ba^wZ0=>SBGs1nJvh^B|D$7Zx-B__
zF3M%tI;+vcL$;+0fp*v?c>(fAY!?!tKGXIsIUKTV+u}fu+2+54LCm)O`vo|2Y~`zg
zmTTk1qAkxhn-Z&!+m_Q8B~I8P>DA7+Ws`5Mz!po%R7JLN`byF%+d29vifsqZ(f+f<
zwv8^noVI-v3c*s_dOAOr+1|52{*0}7CwhO@wstcl&e`^FgWmJD6GjX|xlObRr3%|T
z4X`V1Q<K3`WjjWxZ`HOrv~{YnUAd0Z1>1H?sjRhqO&f$dn-86+FWRDT$Z<@nw;id6
z{3V-{60DbP|84<xgRPp@u`9MlIxbwb@t1%!+7?sNXp`+MMWLH*6F-BY*KBE@0ra}9
zW*jUnHeY&jTWxXwqOHxglu}CCZR_ZK-eG(G7DoM+&1Vp8oi-kMG?(7Cef=NCxy#nL
z4y<=<v6+y+YkTlESnt_3(<c1B?KJIu9@zXszDU5g4H_t`sK>Tx7D%sc%><A>+v=6*
zM88e%3Go42OC$saZSgmN^4K<cDl`n)Mrk1!wwdUN_{5gWfxZ#j8?-|nwS`d3f6TW1
zJXpqU$0%Cx)OI)?mCtOiQ{scOeUujQJ@(%muR~(5-Lx1m`|MGFqISRi0S%Cg-Gv+{
z2kgxhB6hd;v%u+L|C-hzPx})#D!uGul(^(=m(w*PANya!u-Dga9YQDk?EbkZ`P(CD
zi43sY{ZI<D&lrP-Ap39)DueA^(;cwppgocn+z@-{0t`^7{lBfK46{4$1_`&v&WEN5
zdy@>~9BI#_wLHq+N4vUc`yBFU#@KID*elk4h0d#S_G0op#oL+1C?(jRlCL<?t~rCT
zNV0E!0i|Sn^C;R<?8i1yY$?^gf@bM7`<(v)=CHlffYK3r^S^*OYLBIpNTxkJ3w_G6
z&;1-7J!TKDhP~PL5!%V**lX$bTdw`bt0*0}|7eGb6ZYckkju9Vw?VGJK8IehLi;v4
z1)j9ONONbAo%<0zvZw66q_EijLKH}ey@<Rqr|rK}`bMe!Pg+jO>~eCSpRsd)MB91$
z)r+Vsw~K30s<3a{0=?Dt<MeXW*xhMwdcnSw9_Nd8bul#6+nGxsaLN80d2p}Tza!V)
zReK85W67{@3WG$GJ@yhvv;ChM^zfQ}_5<+Tv|nEW6|MG04$#`{@0|c?x1abJZ5{TV
za+Ge_d*;H>PW$AAkh^UUrL2`Mdp2!v?$|$^0h{jH&r-zno_#w78}Hkz3NWw_>>u3)
z=R=2mn9_3|*}vZjP2KiQYXI6~m#>71UV9QHF7?^lX$RGBAN&ZK2JAgsfHr7va)I1q
zdja`-hV0{XY96*{QV9Nu-Q_9Bh`m1!Kl7-4E~O)k*>BM+Hg4Za5yYqV0Xld+vpagf
zN7317f+zIuaSBXDX|L1%S3&kU&7`cP{Z6;zAn)q5EC34KoR0nh_3lm=>8lwYPL&k%
z@N^O_1)7)B8{_D<w^KUpcYT~*yo*X-r_KR@`8jPk3~_&_uYQJHfD@ZyyMazWIA|FR
za{9~_putYh(^lr7(}o?84{`b*Wyys)EvF!7nA2W5Vum}##iA79lxzS?q?2J26h=8!
zQK%@|>DBchF-~oJpf}cO{2Ex|oMO)bCEh9OBs3&AakhdaI+b=qQIgX;`)J)wcA8j=
zUZgnfqCekAcWPs!F~jNFEWjLc`g0;A4m&yhgVGTv-)@Y>Q70<};j)~pbQk=XQ{lTn
z$#ybUpf5R2$q8V|b(&BPy(gT$nhcWfwCFn+Q{Xhv0)axO8PicZ>9m_oe)A%yEwt{Q
za{Bf~s3>-l3<A5vY1O}|Jma(}0;RJ~*;Oc=b9$)~Xy=_iq`i2#lYboqDxCWNkEZtk
zi|Tsb$G!LNF6>ek_LkjcVU3ANG_fVNPt>Tf#>7~Y*n5mgY%vA}+ftQYZHOoe0v4Jg
zA|OS;2BL^`5u^x$ioGH7e<$DH|9N;A=A3zF=A6BI?>RGbE|jgf=GbroB88408Q@Hj
z<H$q|;=1EeDqy(bsG0(D(=mslI3<p+=|Ivg$G@<SLv5j>{$n^?<~X(oTFV_PZiB0E
zta605O2=rr5~>^rc!R5UETnT-HI4^XK(f{`iFP-49alYtr8>t6I&k%lTj*PL&vD5R
zSZZ)wPbu0)$GbP+Q?sKf9MgQ?@#h{OEslXyy<uu~%<6|xJa9xX2450KM~ca|JKoHJ
z!MBd-G<#i+i%&wN+i}hc5VuWl?4a9o(_fDO@Y*zZJ^;R(2GOlMV3YP&h(vB`sKAt*
z+@vmn`J_!_C?b`z$vGDyX`6og7L6I3_>~xEmT6N-2F8@TX$(CO3O4bMXf52dc_-A=
zZ2EXH`W|eu_!bU7-&96r6rGzET!l~Wn?q<9x@+^-iEuP<b6`FUhHb8=Am5SAz8v7k
zH_tu{E_rhZ3-cM9SM`9h{LPm{n7^|5-PaJgx!IIX=jF;a|GW}1flfghm<V_B*#m=7
zPT!7#?qsL*HE2wA+SiC-XF2s)2sKxnh7_akrjsLWA*!85Y=KCVQx+B6w>o{HgKJNn
z_O6AAH%?=}2JXGn40AZ+=4`xyar!vRywK?HJi&Aeg9&l&OU1~0oNqH^-Z{hr_-N-q
z+Iht}KUBifDQC+zNG3WTrf=$L=b5gMJnQUF_nTDbVa))XbG~4MzBK0nr+~ZQyqfm)
zS<cT};8TusB$aLCI$!og-$m#4|K85&ym1AE4D+3Rx5Kvr=V~3uCFi}3G(*mAv@5&n
ztfl_}Q0Sbu9l#>zOW&dKx^w@3;8U@4Z`!fla2`xy>JsPjSMcJNbFWX)SL*zp0w=ef
z*=6vs+&P#|)>Sw+QaZHKx#TTGs+<Shqa|B|b0<B{nw?uv*4jgkpF9RNNYKHIrvPUe
zQ%TFk3TDGRxKPEgCTOf-ygmb{mKiQ$1a-_pTX6RncLDmFnIGwy@R(^#2K+TsMb88m
zb|BRhc(dy_LrVy|Cz^8CJz!so9u99lX-fp(Ti5_opBgBJ`B?-lEI;2!d--oXXm>W^
zzyS1){CzOAkNWLT{Qh>C3B9AkDTz5I;wQ}1*wBg4_TAb}Xc!m%2rc9HwgNlBJp(cm
zC(^oQ(my<~lUJA1*_!X;??PzG1^W8^FqZxs(2pDPAUd@!1lPn*Hy@#8+LHqOJw0Ru
z+Gor(VpKCN=s4i4AFku~>{%Be^Yix<P5Q<DQ#kZ%$vo(sbBam}=YCE1hj|6v&@g|)
zWc<Bg8|7>lmeWOJTJ*aDqKlKMIB&@rI)=Qo@jT2dSI~PAR+!UKf#0kp09N)3K=1EC
zT~M^@<DU5YkKVgrVB3}x`0dF!JON-QbNfCJyBGy&_hJO9Q}t#}q{FTc<8u_6eVHv^
zK!qO@j<Xadxjz$o0y4qOkT3x2nVD2I+rcQNqwxuoL-)^jj4v(?c_*`g)@h#X#V<j2
zvfn)>OKk5POr{s>z6K_|*|T(I`mk{?pv9MMp$MHHtE383fA;edO#VT(C#A_E*v%(F
z#>KKt6yu6x{}}*F$Ju5%ES+F`PJ_0S?1dDVIK`IGbso=por3NJw(cwpCbDn*Ad<v(
z@7s{Td~6y>g%Ri2IaIrw#(Gnp^ep$5A}Og{6cxjq<7_BQnZ|`bhrRRM06O=O&KaB`
znZYH|#we3JLz$Wj+;3D_n#HxBf%n<m)_<TShx1zw>$%*AZg3a5JUeK~<ND47AfIDR
zv@a~+KKQ`jOWgC%q5Cp7`Z#o7;m)lCca>|Wl*u)2u7J5H<ow5h6mdxgD80@_)WBdd
zw{$dg-{5Xg^6MtIhN@>uIL8^Vbc>t(5dfuJCv9qPb2ARWP#L$74hoiY`O|2BR>4hN
z08+`lri-JB+d)a!YHsN$AZoaJcZlBMKBX;oE$1=?Chl@u=_^*pt)nB9^;|O5L*3)H
z&~?_p`O_)BM(#^<kS5Nq8d{pUHIxRw&wX76u7z7+279es_0JS~dB8P)4W(_Iw;%BB
z++ccIJ>>czekOm!y%-1JV=jmCm>t{)+7CYA9?}->Dd*c4lkkkIrLwi>+|jjYe8HXY
zg`+RIPaXsJire@p`d)KBlmL0d{c;eh-*SboVDB9_C0o`*Bk$zObx`9X`>+&)ah1jG
zJCcODq^!X}q{tE*fjBE$UIj#|?A22=o|E;Ahlw=V4*Krhko`$txSO&b6|hty+i)3@
zw`9}lB_-H4Qq@7NY*`^Bn`NoNAopbrA^;C$t@IJL$yR&@+%9<mg_ykLzemDtZ~0dy
zD|GtFf2W7Ezx=)rS_9;RH^G@exzk__^ss!{Y#`3dXN?C*m)G3|$&hcLFJq>B_f^0z
z$ctzVmxX^!0TbDBJzbVLa^GCImMh;@4lYmrU0-;ZFTdo9#saxB)lpr-e|@I?)n$2A
zB|5Lj^B%+QRk`gv*u5ry`UysVSJ6bnu2VRD4^pp)ISg`7F`*Ce4T`n&C}~torHO4)
z1U3NBtXMjTJ{ZM~SMcza;(s#qbt_iUZpp>0E*)@Jv);Gig`3%JA6nn}n$4-hnEcEF
z0?_Jj7SRXJ1ei_#1tx;bVg_I?gUz;ff(tQg%LcdGYzn=GY>!zzJze*jt)^m_eP&iv
zz!+}!YAwh?GqVOXMwoTDfkc^!6xvEL`<!-pXU(|vAgN~iQEO<DpELU^jV9Qvlxi$9
z%%+S*XQr7G6^dRkTQ(McXPNy%$B(kjg6zRvHXBDPt1D*abmd<)Td@;>Yi4&wps~;_
zycJrmo1LeRu-Ghi3PxXH_N6V{t~6_)MQWAVwd?Sy+ANPEpQbxzq2qwBHQP>$+`DEi
zR5?;-RvH4`_ssGr#N1%klz_%2vjJ3j+-!D(B4jOQ8<PNNHEX^Kkv6j#w0?hRRznHM
zM`n(+jCgGJSPL)Q%+D->_xsHauYe0PUsZy}1LpGGFduF*H@^&}2hDRGX}-+oMnKIW
z^Fx&JJZwI;8KRNq>m4ByWq!5{x}(kGY%s!O=6VXH$CxjsctM<b%0`gm=7ah`%L(&$
zZP0SkeE*M-JZ0YS1GJnqpZpcPNHs5?4%KPqW*Kniy!qruSx}m8{t+c9Gt7&RLCpno
z?Ip-$nV&w6zHIa3w0+Mpf3C+o<(j)WqcP9?24&Ln&9~Efr@;KjecMv-WzHD^rA6kh
zROor#Jb_}g#pXY)1oyzafwpID<~?bz_|QC!whfQW>nPIu*nH=8kPdSPdPF@nA4iA1
zo|(HALh^;V2i=%nnlGeK&j<5$^la%i&!o_!i?YKElCH{?^glh^ltWDvW^`Acw1FBA
zW%^dQ?WvqXcha58r!UdBOW8^<O7~I@?}@PlDQ#CkBv@%l-@8y{Kpk+qmG|d>>{Z^`
z0o*?2!im5oDm`eolcX%AY{+S4EM?HnC>wr;vJ~ZI4{&Fd!)j@<n5y)kr|&uC9V&lF
zQ+`*2sXVVt$b)FQvgHx*8OmAo)Xr2U=7L;MW_Q5-EM*7nOtO_(s{zkZ-t7h;SNRpK
z#xE-SWzwW8f29pzzH-@Xs4h@$8V=Q$l#dRg@3Jx`f)<Ncl*JUayQ=KF9HQ5htLf4!
zRNnjnq)0i3()q<omkNm7P)5GTux~1zW1y`>`8(BV-%_5Sx0RMEyFAf&TRB<_$ui{!
z`moEDTkAn8mDA@yvPv05d)sQ|ZA$#tC@WC}VUpib`h~#ZTIJxLFn?G1Ih~=ZQ)=i+
zs8{};2H-uV87<!%lpA)Su~GSqjsY|&r~d@ftei-N1NW7C@4!-v(u)>ut;)r;ka?hd
zKO2^URjplcEkyPH3jhwNf(oHCT(#gOMrJyw+CY2j2$hl|U58aA-#}ZWDvcKWM^zn5
zL84SYSO6HU3ZRO*W2!H<pfOhUfHt6Us=s<d_i@!9zk{4meY+G&PpPVH(3hav{RfmK
zs`}SKb-JpQ%6~FcUj5+H1=U-+p0Z4;(p6A;Nfk=ft~XQ_v;w-Rs=Ew)iOToCSdZ$m
zCHhKLgL(mYTji1fZDp!)XD}t@s^WYMyF%4?1a>P`#*2__P<c{-x=}TY7H&-{Eef9H
z&8ktWVeq~xiSGO@_*ddE)T%P|Dudq-RJN#&l((w}&O+-$RVNSKk5ucazV5N=DLorI
zRG}0!e4<)HC)S>-LKma&nd&{oC!VW#s<?TfT1e-&U#k8rgve`E3neArsJ83@{H<zB
zZ*cEa2dSj9Q{}iA<h^Qy={)dVs;jhj`=FZq7r1WK1UmQQVxhNyYpxdKz5sEvI8NII
zcMJ2C;5;lIzlDgW#hX~n(@qNyT9xgxh&&4KeJn!hgY~r-Mau*~i*VX41z6;51{Y{?
z+6t}(S^O1_#$b!A6SUU|v6zfkvdKd&)=veu+ro>^Wkpz=p>V+=ivkMO9=7On2qe<t
zW4f;%wK(4hF3MsYefH57Q)hy^XK{zZIj=2V^@lPS%NvUz>1vrA0fTOqy-$(%mafeZ
z@vvN;4@W&Mcl=0;EN{#1hmi5Hyt)7``dZph>ARohPaY5ru-s$;HG!75D47~;dDs$a
zLM&7ELu9Yzy|ehx_E{eO27UW2%l?A*VV39Ut`%<SK-H=TEw|F5JHk?;;M*ZfzhMAG
zT54(Kb;NR?l7b~iE%l?JG|DpUEzBRYOy~ndjHS;G$i!Ms8VPN2miq>RoVHZbTS?AX
z&dP`R6w9|1i9c)kHUqd+%hObIa?Ubh1|-ug+n$1?TZYp&J;TyOX}v7V@-e{WSVl~P
zWUi(AUodMbvD8p8_ASdFG!QMdTu$fqZd(qb6H#TB!~cbva?6t=(O6-5lWsfpmP7A=
zyJz{h9eoX!D$1WUT7E&5+0B;xG7R*A<r50rwpnhjgJip<Z6eG+wET<;jXEqdXzlRC
za@$wvdup;A*%K4|%(9{v2J_1D?Q)RUmJ?MFePfyT8PvSBti1wH-&syL4NIMtw=Lnt
zd&}4-FyCc)j&=+FR!^xiG{7p7BA|g*s<$9PR)@bsW3bh*dmtfJ$(g`~T5ZO9RKDBl
z5Pd85SeYv5B{F-hqWVJHKC5`_S>^k!jC7fVS<UVNnFCgdi6G%t4}XN@L8~4VLqBAd
z*96JKRu4X)G16)P-EEIpjkJV^N3Evjp)ty8>qU$(+G=VwNQ{-sO-w?p)e`!S#98IL
zLd$Wht0o;<Pg=3FFwj$0V`=RZZ`DROxCE=Oz5_|LO2350B&&};2A6C#y)Q;_+A4H7
zaA&Ocy@K5otD*M+PqmWAf_Pc`=7M-z=l=ppAL|8u;8TcorW5QQu%7!hjm26?rRxW+
z!~H2(8DTAc1H@r#e3LO4>r_fN9kCv91164IbChg|vW_?k^U>BjtwG|gPv3@5XRZC5
zKvJ#89R=W=^%lBcq*)*Q6j}<c-;IN%BI|@P&~n{6koNy&*0br^SZ<wt3vO3fKmU}$
z_pj1=8?CactfK|UR9ml%0#{>=Cj_<$);4WWT5G+iFHGFEo?4C%ug+Td7GBg_hpva@
zJ?j}W;eCU3kL4gu)}K;Ht=YPfa`gAD_h&*&i}hy|y>7Kug#qx)x-SLKpIi5-rRU!Z
z>t1v)@}>2*4?w)K-tYss*Vf}XjN*;;Yx)|#wO*`8<2&mfNdR_QM-M^cd+Xy=NY-Wj
z3C-aL>p5@0xu}yF;9S)^|AL5{I+}9G?&`4*f%8!7N2AYEZ9WWM>{L(P0M4{aeeZ9G
zdZ{}_;JwuYtAOxPcP~SuuiA4OCfHB?^(C11SD&KF!T@y~B`^Zj)56dgq;{hz4OT}}
zf;U8+9f8JB_0%}b+8%Y>f9oQ(&svD=Q_rUIto`chyC7j|cZ%H~FsXfMBNMJZ`wr|u
zwS^i6Bh+)6VE&NWkMdlR>UTH69Z^4^vs*{iA1I;{rH;IazGyW+6@AClb;E#*QIDWh
zVXV3rovk^p{%9P=azY)hhsa6w+ew&&Q|ft?<A_&3kAap1wffUP(VD2Pq%A~}`shB}
zY-I3me-7O#>KXMIMXI{{3Hr{d<0<ZvrjFkVz<Kr9!%&m1&g}<-8S3g);4;-$=>B>^
z{be4^Us88Jg^A1R=f41OMZM-KX6C9ok@D!b)C2t?QmWQbF~V)N|57xTsrzO?S-JY5
zX*VoYsB3ayw^F_B8Aeg1R;2+^tqx9swi<OF6$9N-$I$k%R^3HgfV=7$6cVaa7tx}!
zUVUyq0Qb~^RJGKo-o6%%O=^=9M%Ju$qvDJE>fW9Jw5ZS7K%`Z@o*pL;)D3}F5N%VB
zrf^ZadicIUIhc}s2LL<NE;}LfMD0)o^Uu|TD0ufmz49{pUaHM5Lg_2@@*<Ge>JB%E
zyitF;6UyGIqjzCw@6<=50dTchzXgqMHgoo2fbKT;D39)8^L{-BvD3zZ))%{MDr&)b
z*<Ak;_PlLwn&>4zJ~j_1>+5UNn;zeOHg7*gqrZ(gRXqjR96JNMfi~^5KMu0_Cl(~w
zCUq(-#o5Z$7|RLUZ_J?dl&udHn<Us~JHVMF+d<o4;<WAUEC5n$ZJ$6S)%Hby7)rO@
z!b7s$c3mbtEE;SVk3nan?U3W(nr!VCfory1MW4Za+jpM<-(ov~5(!UjKX~ukn9KAs
z^|HY%blSGxg{k+pGbnV>Wy{B-@q?}P4^ZB1`_U;NTr_Ve8|td5Bc*Pd84|7?cg>Qi
z0QhM(?}I^q&GT=dC0yf2JFbJ8k-IUpLz-r~6Cc*7A3!8h^I;UYBbx8&As(e^H~o)B
zsyR>!M53nbDD0ls_)sBry5<?(gEKTmgCJ6%X`?&aCCzXutG=wsp+f2_8YL|tuWHtf
z1i7YJcO1Av&6RV&6={~bpz*rq=^wCLtU0^@<c8)oRcGGR<j}gcMDyK96KIX5Kb4B#
z(PYuGqgJzg11#Ouq<H{QrwIxGSFf=shZpxW%c<z3LBld2jhath0N11`>BN|tHN#rK
z-PauRgoiDfKlFgNYCL<O@quOmoi%IIR96Gnt{F86+(XUIAymHpNOSprz(3Ypq7sD;
zjmjFpCz_d|06x{Mro7xUP5E88_FOZd72FHWU^-#@QnQmDimx<B>B!n^4O0e@H=1`h
z(f3x<a2t~EG|s-@IyLt)VBx(c#1f5Nn$cTe-i2R<xVK5}${*{*oVf8H(~8xdpFo)@
z5B@?iWcKiDilBQh-$FOB{k(1nw1x5Zi!u2J`5Yd&2!0Vg_zv+Geulq?`6YB9Ad=rt
z&(<S+7gaGF<(*^b)8<!D$Re75y${?me#3aolPQL;?hSk_AF>~I<M?0cO*+T<uct%i
z1YcPL?j(PTfu&RYHA+Io^H<$rB7vXn4HJoc={ZOy@m?%+C-Z}4&~lnzN@f0M_&yuJ
zrSLagpyez-aUuqo%CDr|>p8xU1GJ=>_~oY|dY=F8bF`-OV-vw;@H4&vm&q@oVx$ZF
z23mh+@oC$D$mT~;(mRL$YCigMd4I~ET;vrLJImwWWCEVgThMc;fbXV&%_ZKQPE=jy
zHx2~+3ctD(B3Jn=$|GLmO=I3*OohDbZm>l>-wjLG`S2PbiusL{bHBkK-U*SL{6cz2
zmGH^dki5m)4Tnf6ub>0IxB2Wkm@nhMA-m;#6&)k5;6Il^q>^V$fLHO~Zv?64Us6GG
z4gYp826%^$HBs2Mmj5FHqIY@wB#=6OLjguu&%dLM$vys%9h5fk4}SsI$iJqGyotZv
z6RtJ$UK9Yi&nxL@N(=vvmR_yAGga0<;8(T7U>m<N86xexio!k*`GOO0^b!B_k7#_%
zk1M7kw+{ZtDtPmR&!Wx$Q+^$N2G96XN}fIEF#ufhywyaQc**C}>iZS{@859dHD6o|
zrEmC&g|PINKkEzfjvqzglukZ&B_!YTSu+9e;!RnQ{J;-CiQ#thTqNKw!ui3py>S)h
zO-HMna4iVt-GxqC|9S|+XlL#zTr7mcJB0){aJz*4R0!%Nw3k4sxA3?KKKTgSwxG{f
zc%A^_Cs^0OlD}|<GVlSydn!K<6b^czFGyHl3PZudgX0hh5eomI?M<j)V-AOR3#%&O
z@E$>+gOPiMaVLS;C-_iwalcSRN8`hUJ>HnE1Hu+R;KK!9O79#L#Ghd)LZ~|h+#%tM
zy%0Gp1pNw2k%GPyV>u$|>72_^A$${@i4s=RLMmE#7Y-5AF`>gBc4LIpp8<>&o>5s^
zoG>>W+KvmpRF8H-xIO|RCxvelKu!tIX=dYv{(5+kAdLMIN)v^3uVErdkbXmBvS9TT
zBBzBXbXz|oxR1mDQ-pv1`x**=(i10D*eyZioJokM^3F72j}GL#ux&HUrwc!w0GA=?
zlfh*QP0rvh2<c;h$Pz;6-2vIc;NL-V1nVUb$rXZ^!O@Gtfv+)7dBTdN7+Suty%Tl|
zgcUErT@tEjD}7mr*a^TD!N&k{RWKd-2lSfoDJ97Yg});)mqkKm5)jvgwiqZa76M!_
zv>SrsNocz%Ogjm#L@3?@ky}F53@9xXmVN=(ZVQR8VZKZVW<kn@Pd0*72p0<=St+=>
zf>a3w7h$Mc*gX(^HNtNudQ15oVQwod)e2YXUUXMzqXLgQ;oEQEOuew!9Ef{D^&~Vl
z2(DBT)hNX60lrCCLm`A_;U`+X-xq2pqpwA9*aw}hf?F2)9te~B1J@=zrc(ZPA)pq@
z9tz#Gm3|~tJ~RRNSYYqMQisr!is7FK*>u48sgOMvLwhECOo7Pff+H;uUI;omfc;W9
zeFx-~(7FNsz82IX0B-~j+7`VP^69#ICsd5bXWuD|9|_6#!k4Si*d^?DfV~fby*Eg=
z;FLn)Jr{A03Tj-%LNge26aPmsY<KYz)uDQbPvsEx6c_qJWT$xc5c+nBvhUF7B{nxf
zx3^eEm$i@hog8pq(ZpeBeqtKM1^mT$DrpK3Kch`-pcqFb3PIw07c>ToxfTq*e<5Pu
zK0t(u?J1DiEl#E!!yfU`HOTB08-9e+ePYxrko{s&7%YW}_sZbR0rAI6kPH_;)MI82
zijn^4ix59q4as<M86EaX5X*mnqlw}eS{EgWpHaLwS-eNFnbTqh<xWj!#9>omH%0WJ
zh2U9nF)bNW#rglj({rL<4qQtUqjo^#yyy@GyXoR(ssYImBQHZ~rnn~uxC>&BX8>f0
zxvya&TU1LRIbwnf0J-9Fs!P5oJ~|DNJW<>WE?=xD0asuWua`sHC2;_)n=gxfDKCCS
z%%Pk8Rq+PBobQ^L{s~MJiiNMCtw_8*9l-0Nb|KUhi~rCU;D-2xD;&KkuBE40i8yO1
zT)QP^9RgP>mc9buws?CT43&vvDaKMR`qLSw3ei+c+rdh464n1yiFvfttQPGkYE~nz
zxrkxk5$!1=UMs2wz|viDf((*%qCX`+>%}p<K<<f7Au!P(I@9IRC@xt7*P29Yx;mT1
ze}_ZlzPNoMxE8VEI!4wi*8L1+4@5^3-HO}9EQ&p}i;Z-m;GuX!fWb%N8aikESX@Tc
z*&X7+G>AMALwjLNPsM6SD19cHQwaRISm+PCFT|CH!Mzk^wElc0MlA;Jwb+yD@7{=A
z17QBG$WyVxJ8=(#N$3=#$I|-qz4-iN$aIO(w8H-&j;APax2U8u@h*~KA%^BE4bK4Q
zCXJv~rMpzP1(rOdAM0SrQ;LrQw^JHPU)Wtz@qW1GC3!Z%gtyd(0<}I;Gu<J4rRo$A
zKj{oz!2Z&Tx&OUqRH~<kOrUgw(s@CW>j`KJmONjA3z3}Yg9(+|D2=gOTJRQ)d!*kf
z;JR0`r)|nU>1PSteyNE<vtiPV!5G8=DVJ)_!lhyk9v+m!Y9SdRIi7}3hos-uK;*EL
zi$MCm&g+b=sW})<MoD?@upBLwpe#v#Owv*5UW_!6;*+t`hE3>;lPXt2?QzN32wNv4
ze=m@eQsG%ho{}yeg=D<cD-_BSB$3t)iIRdA&PmeQ*?=cYS4O~r(^A~`0GyFNwTDQG
z6mFugz**^eAGD@Qlju4-C#@(zW18eq4B&aG$RDEV(oTxHXGkk)F_J0up?moSshwsz
zOImgYfNbdl?Ob!DA1H>AD@jyIdQmz~@36{~ocDvvm*&$8%?qR+N;F=Ql82k1^s?j-
zgrQxLl1cYf>3%e3`kLfO*^NSJP80fyB#suF*QG&}gD#e=DF|>w`hu?Lo6=ai!Iwzt
zSKw|*{f5ANsT495<hHbJ5iFFU=mofPsfI#L71F;7I8!N|StG|yxJnvEOO$FU<_(;x
zk@5yY^p3RVU*Kz{B{Z{lrHF4}qE6b(0$49;K8H{Dq?t_sG)RTd;C7=l-U&l%l1AT!
ziDqdQZEWsKe}zD#Md}v~3$2nH-I*UqU+)BIljc397*o5{at|^Or9HHLcqC~r!Te*%
zo0b6`QdS4JCsJiFxTn%sx~D#qI9hi+mu}N;>4oG-huL0AlfohLO6s6Oyw}q2mEhh;
z|GI&DE2UFa`a4OS30$Yt+6!9VOHKnJV(OAgzk<vMDUG%!-O|n3ka5wjX5pf%wg;_L
z+_Y6XaPHbW57FnLHKVh;yS1Z#h21^cs%-S_)iw`7-#+aH%2@8#8YiPKOv}Cj3D?dI
z2H>FfWE?~yv?2u^4{5jeg89QH?fzS^8>#L0H`pWE9tPl#YFE(9DWbIRH^c8}tv4w>
zrfsAMYK(Ryg-2txKMeqh)2`YJa$LKY3hqy6U(#aar1qRGKBiOJSPHwvYa3}9kf7b|
zgvKOo!U6!2wX@cNoYtDAG(zba?QAV9rD)f^06D8&Lb29V?WqUw>6~_r4)c|!on;Tn
z^I98Psi$izsLC}%TR_{DOl@Xw*u9`#v>Ic{(ysUlec4(BUh#F%CR3O{S6kf%k&D_x
z)R?Dj2!@4xt<FR>%>~-tR0w-Xn`D6b%i6(rVB(6_dJEKC)efXU>NV}?b_}LaTShMd
zDbn8B0;SirMdM+<So=4HRc~nPX*+sT>$n@FL_0kSjkmNTsA#lQ8(9v?+uD7RAZ6NC
zIxkwT-CjqFpbBm5_YkerX2pS2X?<ujUaj5U22!IvO$og_TCZ>6Q?0g{c2sw@bM`=K
zoi>CHJ=ALp;-U1OHt}ot)Swl|gEVUEhd^1AR__XDnzi1v_qwmWR0lwdc0vjoTeX{}
zQxM>RwlM|T+O!MQu+*+~nF-)SZRU88N80bJq3yBuGui=mXtS+>f1;f)fjrgzl?@M{
zX&q@p_gw4!6DIG4Hr)dg^ims2<qNO0WfLL!TH9%Whi|k<QQ_;L<wHT<X}hrCHpx4+
z9R|p}*M@xxZC%<!8zK5ZoAv_uZmpWGP8Z#VBk<5w7ykt~H=RTaQFmRUEjSO|JSqqD
z)O}M1^E-7;R0+OIch?1tUb<IQXW^|IMd?=`-8$0gtJ_E!Ek9io6~~zTbyuC?O@Qt@
zdVmM&&K!eGkZ!?s$OP+_<NzO{+q@hip}MqU^zGIa#z6NTT}}hc@70YV5BKS!DO$N-
zmqZ25VY;p%fFIBeO2r(8>jHXWfCqK#mmm?kBzq`3q}xqb;9-;Q998^8>R!^(<0HB*
zHPjr{Sy5q0ly24~aM8LY4}mzQ8|(!0F*<V!Uc~Ay{D8hVof+Lsj_U^g0g)5B9mSZ0
zlR9h4NT1RjqUTV&?iX4YCg|2bhe)C>q(4+A>F)mqkz}3elr7vitsBw=ZD(}fFF|LD
zZXMnA&gx#y1wK{xrv*gL=^k!IW16nB0^E7s7z!n(>;9lfW`?fv25_0W!?)nf1>H(V
z7|hZ&`oqy|-BHRg<><!ItmW!j4#Lnyo!wC=E70vQrGUMpdpQN7S9C+Zg~6-3%wOT#
zHQm$;02b=<^Wk@q&gl#EUDxR+z*4d93a$2T=uS##ys7K87w{6@0~bi%(v9wdrBdA@
zPrz^MzM!;GnQqJ^_*<^KL2;1^of{P_R_gwGO{1vNg;J$|weCm&22-O87z3GFT{gW6
z=&mjgWt;LkUE&8gT(2wn5q9tCBB^GvL6_hSHI2F{g&0JW?q>tMXx6Ro55Rrh5vq-A
z(G_#xT6O+akbI!CqjhYXE~7u-?K+#alw*0Qb4o(%Bi+_T5Phs0OOL@0ovRsSp6CW&
zN8>Zy9ZLH?*ZoS1z8AWeR5Sik*MB&0uXKYc5c^s;`WF0sqf4YZfVa90v?Y0`8|?|M
zQ`bd@z~Ade(WbadS26>*54y{DDG1Q5^XrDFi+<w^jKWoKO>0&+eeit{cYWJpc;TTR
zRt(*q`h8TXw^Ki2Gz{+2S7t-ROFx(PsNVXYhe3;venB7_ef5i5Fc*IM_I&{O>n$ir
zAD|z98-0QLzyI3`>0K`XXA0Jb(_5ZH^m1BfgzA4A1Q&PfAGCn%(fd(;Zm+&m2J`#$
zCnmzgetlX2xG?>nZV)-3_n8h7u9s8Q$3cAuU2GBhuCe$e59!BJe(bRRPuc}U>UU6O
z#}R$U1aL?7wZmXO>R0`m$zY@PW2xZpnBFo6&cx_L<q(b4&+CDSiqlV_*A5@o>xY6n
zp&wlYa#CMUtDRGNJ*}YP^{EPw1brKazC`_+ebXvYzq8~!IGUnY4ui6@`gz%KCRKlr
z>Tu5KJ&u8->67Tx>v{cf7nn`g57>{fWay14(2}YDCkhrW=sz<;OO`%Z19-On(N;9(
z=*t3NFIS&>392vZ<wr10dHR0tkj&TTx`GtwukUNEWUNe=PowXO{)#uocU8|EgS~6|
z`GK%rsJF|4*&==3G;r7T|89dwv3_eZEZopfi~;VZ{-GTJCHkS^aOsvlbt~+Z>baxv
z^S1t&0*1=;lPK^~u5b9SC{sW02lQ3yM?M0)N<Y-p38mF~&2`As=vRIV?v8%wk5F2x
zpFzo#yZS<kpVsMXJ_4{_UqBz-J$>XrNH*xpDFNQ7&!%KblfL+4m~Ynq?{f_PseW)8
ze0rvz8U?^}{ZEw3d7)ph2IQq)Mt8?o`j013l<&3Plh%}P^j*2YztxA)LFspTuU7PR
z>d#Y=<$JvuRnv6ouhCxXgTDP3)Wq9mQ+zDJu7Rr2lI-U6!yr!Ejifhdov|yS&1{O@
zkW4h5wVNM^##Fl(w3|z_dreENbh};g6y?jXtKI;a3wC9c+R3t0QvNa9?pqaol6Llu
z@FLePXDzf{w0qGFl4m#c7#j2KO6ZC$uv_sB;Fs;x(ez2$^-6{_SM3H{LZr}c%?JRB
z>;~L~<aN7MAEU9@?guJqxM3HCxVTAv)9&&J%utEl-&CV^%WmdJP*ZC6ehSRrwsWL(
zV42<COW?}wM%cse3cHDv1*x=KbOeo6b_UvqRonHYU{Z};%@lBV?5=IVAZqQZ*Fy5H
z-Dz5h*V#>;hsJul!y<fYwyXAsqo!87ziXl9f!!`OMBD7HWWjv9UB@D*d1&_!eVHEF
zeItN8w)-v!hz`3y=RoqQ-G@)0?U~&&FTkJMeL524h24#JXnbk+V=_cu*_C|>^4hLK
zg~m5_Yu)JMwQG3<XWrSZOokVoCcEeWu<z}f3t*zlE{3WXKG=OKqOseqXcX`+h8(IR
zb2V7>M4y}CZ#u2&Zg8jIh=;+r5<Ynv5}rV0r=e*bl<qQoKMs9fhS~#=^fv63Fcu%f
z{u{91YgiYGMn6Mo2FB@cFd1n%6=0~@3w)qqQaOM@hCTm6X^7!pDpm|N#M3J;b{iH^
z0%4EgAk|gvHTc!xV%cZd>IISghN<-62s8Xz4oe3Nq06B&-0+B!8V3zW76BJw_=4hj
zhYb0HVd1c$PcKMD8g82CseQz7l@9P9H7vRV-O&bBEavN&L7ao}#u$<$AYu(qW@Ad?
z40#k}JYn#90Ng2qJKa6v4FY9v5)H~FAW4STl%+~GtUCw0rw!l6K-n2X6m76m3}<e`
zLaM>^6q4r*YyU8zGtE#>-}Li_P6{HY8ybIu(hNg`AI6kv2ps}77Yx_v6Uj0hrSEpO
z;dU7sa}32gh~yfUQ(pO^A!Qnr<rxO;g=D^g4@YBxA&B1Ub;<C8u8Yfty9vNuF&tV2
zEmsYl0&Or04Rd+`QDhhv2*h>6NCv(Y8=g}D^M=8JLee)4SE#J3#868sr+0?j<IuLt
zej7#Lz3uBLa_M6~-3@*F>~m>9aKL^P1=}O+NBxemMB1x913b#U<6B6^**{4}<8gaa
zIlUz2g#9Smz?`&SErX>~_U&}9kGFp|5nd$Nx6wP=6Yc9M)RJVMkp(r$_76NTU8n79
z|0^l7cl!r+Q|$ez4(zOb$yYFc&OUSjaB22mjz;4}`?0jS$+PcI<u^C%E$DpBP5ZCw
zA!#bH|79`k-m*VLE2mQX{Y&A@ZTtAC7+RVA-7awD_5t+ttFTW#4t%BkAIku&vaid5
zGu8I@>%i66$F7FbJNB_(09R{2`95%W?cF2MSZ9Bx7jX6V@+t7?p8daP(br)ASrx|F
zWU~L$2D+Q=Pi8=yyTjEsw0bz$&|}`yp<x|>J00xlkjz1c@lyeeaCl0InnMl~XtjRW
zL8KI6q{B=~<sNa6{g=FT@THw_w8J5Kj>I?wU4)iIhuwNuNOE}7f#D`Q{9%Q@(+;N5
zJMcN3ahOFRhZKhcm%yEM(9qg0)uEc=T-gq_v^~gisP;f#uEUO=AcYP-+0a(x@Xs$G
z*ByG(^1Rq#PY1NzbO@tF+AW7P8%UNqEH}WJyAI0T@UYI|ryS_4cUVtZfqM=;OjIn=
z=uk~X=uHmTn&BqqurnFjUODWY0MXYD88w)aHx7^2;`4dy;6S(MPKW+fSNz_Abw^*9
zgFsaX9~=h%S9We}p&P2JaU|7hx)~?@059B)gT0~J!zdm@qo;9CEk?i7Xjn}9MK7ai
zE;_x9^%WpK#<Hz2?`z!N8-Dv4V`_o$HzrWpGr%~OG97`&UQ|UFZ2bBF;2}oSdGv)E
ztN()C-Nv732e8M8KpyT>#<njZxzCtR0j>SUOTVG-fYFQs7U9Ox)9LvaVf2hd=OLq>
zV$m_ik2az+)~KBiOUI47=z=(5oIv-hQ^rYl7-)j=G41>ljqB+inq+LDs)=Od$lqb`
zv~dTWvOQy5Nq2!1;}03|@T~FLx9CeXD$+sD88<D1vNYq%RV==L=Z$Y{(3)ZNxd6NQ
z#t2%26d3!J0DsBo>HzmI8yC^N`-<_SD`>oGbfN3wnlXS@b45nyd6>)VM(Hs6ijDp9
z&{u98P2bxJ;|tn()EU+Nz||Ygd&0GQ#?`cSZZM8&z+9LbjhARe-DGTS0KVB+G!Cuz
zjk7mEO^Z=S-?&zztpxl7<HDcN*k(+k%7k{~gjz^GG!EDdFM@i0(ZRwLem<{tgq1!M
zmf`moi$md?J2R2K9UjbIbjHY&N&Rmt%=Drso@p0Tv=uU5%#JXCy_q0-=J+sk=tJ;j
zj!c*JP=qt%Y4LuRiH?G&smvML<)33VQQ9YsDWQwzJhLGTTsjj;g;g0$;C6^)GRvr1
z{{pj-11^inp9hDt8DF}+=P+N=dN<d^Wc7p0MP{-u*gR%YJUa84(8WL$G8ca9(L>R~
zJfz#T2fL*acu#gMRm1LN&%Q?EF1Cq|Jb1Bd)4+MNpHpFm4?B+@55Da4t!VUPt-b@m
zpY59h$pH4+0;mpT*Q+t4Aa=PERRaaHF$dvA2s;KrB*kHN2a+3#+iW=Y*NUCo|0vt#
z%l(5`k|LN(o&?={IdjT9gmcqyDEhx?|K^{o_+#XW3TXdU5d@jh^P-`8Y~Ov~H8EP#
zak}Q5eJLF8#q^`25xz_yoq;;Xe4vZ#B9rpb|N8_5pI+$xz)k%OCb~I)70kQHenV(V
z9wg&!F^XVW;#P1+%;wO^mZN4JlyZnN8~!)+MVqx!2(4b7UJ8*G^<_G~@mQxGJ{p}b
z)x)ks^u4-h3^;e2mfrh1nixA%_it#8u^B^U8?iQypTJ_A&EJ$~K5lb|LfI#5Hqi?9
zq|M_M7}P17ffRg>w;8+($`fp4ejtf9y+SbT6q~%?A(>%QOm)#0ZBo96va2>h6wteA
zvu-BfRW>DE&{=KckN_<;Hs6>EA$rH=^v5t?Ycp*T$YYydra-jA=KeKsPi%@PJowb+
znlHF#Hr??s_}s=w!HO3)zYm7pmo~Xnj{3^RKy&=srgIZS-r6iY2=ni3@~DEl(`LXk
zG`_dteuDWfn~k*a{a_Q=Myrr+n|{5a+r>6B1H{!fpAzzJwh7+gcG>P31~p!`Ln$!l
zZTr#%Kp$K6Td481P5yunA=uW`ipCJz?iCnlsO@;FQrT^rehPN?*uJZUvS{1Q2{f^`
z!SvuhVY~bW0LivfKTxhQ#a6x+Bh0Y%Z-eL^+Yeu(v(~nZl-AjnQ_{QMHg*|EqiyED
z7<QAbL_4Clwo@MBGI7!L*TA5k<|M7#{WS}!LBceJl#Phgtos&j$7&oEXiU&7=>Yt!
zrePfnWonkqq<4DfX?R!QuW7oC=q%CL41#E-#x@vSoyLwzsPAh$6Cm<PqgVpFFElCM
zaHdo9K8ogve@~acH($)dk`MnUMLvA_N{X@g@%<?Z>(6)5wjqFTxrV+#{?2ktdJz9H
zJ^oF>d{iuCLin&I%upzwH3WX|=GWCjbPvDyQvmn!LEl5$K7QCu0Qd9NSI`*E8|iy|
zj2}|~Kny?jCJmH-(FCP&d?>{Qj`Q1_q2&bs)o<|rB!5W@$y2<?agcc4k=7&$CjNi{
zh(z8<fy5+!J_Uu6`Gd5XKFtUAfKO-mfp1~(EPrP=Bvbhw^#GpZzoF?)<2O<+`8==Q
z36jqLOpnYA{x{lvXY${yfaC=}ZydB_@%<^Rk<HIo1w%Q!Q(s8t@}{YKq2?l=as#b-
z{H4AC=JS~$n39{kM<m8n!MkmN?z{XCo<KD7Gke0rhy0MAp!+%Be;FD(`Ce0?`#s-W
z3dt`1=wQG<@T2q4*Ud|`@pTcbX_@6GoL4}^Uw9S`)d9k8)Bhk7C=5Rdr9nal9qA1g
zCep1eRFMAxpLPp<=(yS*A&R1ldxeod0=Q2Y?*neXFsvTrh%k$)dX5TNk>H|)hwq^*
zS~xKgjmLzP8fb|ThSB>PVuihr!Nm#AU64E>JUdEZwv$3q9PFMFrVqtL#S29-FrOey
zr2~_R!uND)IZ1fC9wb?qRRE>wg1HsOn<049eKt$@z87?73-><)xh8Cz1uca_+bu|5
z7raISS1efiL$X4!?1cA~!kWX7tQN+^()+?|1SuYtnuJ9TaHd(9O3StTLII_VT7=^d
z0c;iS2V+bRgt_$fZxbFAfV2xXWd5NLPmkkA!hrPvJQkKKV7EiKJ_=qu5e7tqdn!C`
zhTUhvfo;(8T&SQp^Gm^DF8xo@S3(V?-d+nc#{mCEnD`6GTOs39jPRWh_7t9W3gr~O
zeJ@y3RY8}KTL5hzgbB19?iNx%$8@=f?Y{!&DvpbWh@1Eom9e{v@pR>Sh*7!d^B1LF
zXbcb;27o|u5oLBwLE^N3p)EvoSxO(e`1S>S+bte2!qYwCGun<G6|d}or6}<liA0OP
zUIuqe>~4o-j5zuLl*Wn?RF4)X9;N`$adAi$a3{p!3Gn`;_<1n;PKmqYK;lKG+i)g9
zT-pfN5>4Wlw5v@L=YIq?Su~?d=!`gfFqEc<?#<xNirWW)OBHt=26s+e;)E$p6N8rk
zcV4WIg`??W0YxP<MCW4kWs27fXuKf)aui-<iMuH0o-JC}!ETN?|9g0tD}F?^suxAm
zo}NJ55O?f@`I}<HMs(g1Gfx3nDth)tW4X9Zgh+*`eh2Q6IQl52>#_LL7a*NtKl(3S
z@5MRwFyAHar86xb#7Q&J*e&*_xR;BxQh=kblGl8A?<W1;2)pjm(OH-o4=LM32NOIc
zkruK$rLbA(+$Ejq3vFIfL?5W}mQuZd_mL70f%B8hX@TP}jaH&DK-xPGxIoFDip7GY
zw0`IdmWEw{?hr{;g}zY9SBb{m(vMp(q&?DXT8;0Oa`%ASCvA5(LFs<UF9-NA$pULW
zq{%I4@f0rgrTT?9sXwicj!TawqVa@ewgB8oX@UzrkyFx7YoI$GiCMrCrTZ6PH%S`w
z2181g(zXG9T9OsRi!)LxRgR`e{x?A)`#b!C0iN#P<wRlbGyQXmpvG&!*|{)LInYEe
zlDjwXTmjT{4H-`v><>eJi$i0`&^?Pm_78o30;32Ux`7@!;X^Gbvzjt=ax={54_$2s
zk%FN|e}qWU&?x$*w+tOhg+Fn_!){x^Q~dn3F$lj`4{xQ^?waWX@O$lMI<K~_u@%2J
zZKPM(Zr&3F{Z3A|fpua0hCr_?BhjYUjhS!=0zS-zkD$hvIa~}6{Fynl&fLT78VePB
zncXWe)<aAO?G6qz)o*Cz%qc1ziesuNns=Nzc9)`%Cz!R1F;^#<NkgFY45OkG-zkjs
zc38?}s#k!!!2C?#@+@Xv6@b}HE=At1GIzg#$TenZ6_ge-Z);(qh?$UwzH-Kf3gapm
zCyGf{GIgG?P{q9Pf`xm`S<1>ZFe9c=ny-<uq8MKjllc`!*v$0sg3|lUN1ws(7G_d2
z`daY@4A_0Z=ue^VDbw#2Ogv*0^wodPJfR5K3uaad;4hgdDy8dUGU&9&2WCH=)9q$5
zPr(Zpb}c=YUD@tiXmn%mVx?k|yR#j$A?m?uC^F>9-oFTLC##wP6T4XVLon~fj-LbF
z-s}l4jL?UD5C!7PZkY^8KlT=78U5Lr?eI5%jU5CM$m;fh1hI?gju*^6p^SP6``Q{L
zlszdx*={zNii%Bp*Z_0L>}7jW3BW#fD-|y9XKQ|ii7<A=Sa^DXU8IFbIO|9M)c7EK
zoQ`lsu-|pU?jd&6K;U9nEEaJaWVg{viW1rJ`!SXzc5DIw$?Q}*U3QwyrsIa`?3{Kq
zX0W3uQjuw5|2GM`FR*=A!EP4&h$8iu*mcX%d71q+0HRmeI*MdnWlR47{u+CK8eA)6
zw{HfZi2XeYx@*{P9s_rWRr^3$En7kdtM0PHDB^yPz4ZXNCbo180L^R<Kfv#^M+RUJ
zEv)I!+4T9czl?zU57-bozSqWbbl|U@T})X!7jBa?5GennKv)3h_z?{5;i|@=@gOJl
zfWauPcqvSr<jzpB?I|wq7)U%9^%=ZK;4CMDOXM;gG5JYc$Q1xGIg46YxWL7j-os!P
z_va_@Et~VLhD;7O;J@G=_sRz5^SG?9fyn0`(K(y~?&k|2m$=_(dwrR+UjyA&xPEs4
zzs==chZi-R))yiTTtpE19&q1oK;si``(*%LbC)U9_JJEW4}hJrKZ9xgzf0Eh13JBA
z*Qq$dTekK(@IJEAIN*I{28!YO$?Cobw_oN$Z;T0(IkiIMfb8)zs0o){UI=nfww<y;
z5wbZyLFACkdnLS&l(o|x;)twA8MGXg9iW=#DB1PrAkng!JLtVH$7H?LbP374Hv@QD
zHo_VXpO@XIDw`Zx<plV2S+*k*_+pvi6DTc{71Kq2N9HdBpi#zmqOo1pL~;Lzva)Ib
z9?AGe;2z8R(ypsRcHnOe`-!ZC-eL7rHvAs|p2=p+qA27CS<h*3v0E1U2BI$VuMfaC
zSNYHMTy>NG^)Fm=mj}lJ;emfT3Z<U%xyLd3UGjuA=<|}d(G$&EE{}mTKJp_UgZRqF
zP!h~fK7kfI{_>Rbun-`hL?vGP<QsQFWWW5;C2*!NdGHaaIUv9G5W2(Vvne-lP;S@?
z5+RR|g6LuSOH@V5Bjx;GP;*4S#1kVtD*rVafGGK-&2T1KUPqb4V{(@Af(i0iI(LvL
zUrQmgB>9vv=u4LWN;P|@aex-&4BjRT3n?b~Y^vuyEB}_tug}R-24fP^<o2|$JTG5O
ziKKM-?mF1bkWZmYAXEO>8`>_&r!PZe7XEhv)LfP~yobRn@<WLLT$R70X!<pIA(ayq
z$|o)ZDUz?HwZ(OLW;sNP<=-vGM|eYSnnKye68Wch!QPT<d&5MjJfZ-8-<FT0)Mc4m
zn+vX7zC8o@3i%XDvsB8X=fYr>e9mg<zAv9fiIo=lnn6(3D*ucY*$?D*Q!$n{`7c!H
z(T>yMQ2j{m|2^Q3<tZVM?7;ujjDgG(xj9{4Pvxs_LG+niN`&2RxteN}Tol>vaLrXw
zPq9=t#qvPtc2~r1LZ62sVHn_^iWgMgwoB2EDu=uj8=gY9w<7#Ia6XDnrNH?rwtfYj
zev0Jv;QSSVAK?7~h1#5+f8mN%v~oD8I7KVU2*tPGgFB=c_!GFpiUNu`M=C<^fE-a&
z`oY5}#kdR59jzF`fIFu6uo32C6oy%_8>{FS2@<Cm(}H<Eu2>!dWhWGqD7kb|ar`HI
zu6c_8QL?58jkNy1tB8Jt);h&mCm^~M#ig(tXSOgJYVys3eut$3vvztH%pJ2#3Vzg?
zJ@W^?&Fo_%e0pluKv~&0X8X@zF5a4%ML@*cyl*i8KIT7D4tuwGK@!X#Hvg6aZpr2o
zx-kiv=JlEM{L432NNBxdzWz2meQIuf2ugP;f1~{RZY4f8T<gjeDtM8k97Dn4v&zjn
zh+I{^?u*82%F{!E^Hp6^qcK3$yct}eDn|h>NHvl6u_3D1e(*O`b?-d-_NeaCrMFk*
z^8#+04yZn%x`1$%p95qLsxG%f=8$UU9=Lc|<zNqkQL4doD~(n?r|9-ERVU?$<5azr
z;7+QZuS8#h>eouZlT}Xs@b`?$@@Mp=sERhCFI9Et04$tS#ZnzXn(8WDR_9fnv>+`s
zsrER4URRB}iAlJrO0q&{sp>=uOq8j1(W0|L<z<2wRjOlCpzV$-jV{uAsu3L!akHqU
z?5>B!Usu8Hv=~IebuWv7>oMH{7DF8&8Dz2XG{|m?q5**Kwa9sfDG9R}MaQ}hT9|sH
zNbkQTp;+gHKYrOu8KGZa&w$5s+?$|nuFqinJ<oy8H_Ttu4e)}%ukiQ6ideKS>XQMj
zi|xW;V#%bXFuSxjhu_OS=?%Y@pX-U=D}wq0^_z4C16{d=cCM=?QSQ%ihBLi)bJNH4
zfZMz%6e^sK&;#6g#{?+dI+hk&+xHH_-#Z3VM&0y1&8I6fg<@!K%y6oScV~Ee0R5S-
zZo%0A#z-fL0+|(Gf(v5)7X}iBa3e$xFk!zyc{tOG*s45{`OFz!na(j|DbAkFETHq3
zmze{!3ckU-$0qpyrX}ff{BfA&s7x)A4b6hWBkUQ9zaM35!eA_l-CqSq<5=xvG#+RD
zI-oCs9ZAQ^64^wmBuHXYsU-3&>mUc0%E~5zoMR8}qVcD(jcb6v!0x3Zjah6em5^q$
z?ymTN^4UQYt14i9s9@?6%NIkkkX^nLc8l2MR5ez@KH341TWrNecwWlBqbu+>yP1bb
z6+3f0xN3G2y#%I)olb>t^=y9*+&%W?$MoK>2KJvXfNx~;3xIE8wfV67fPFxb&^C5w
zFoxa1j><;k3s$ikAKpvWKN0v>Y%pCgovh`jz`1bj-;jK+Tt;V9U#g5xC<%g}56qWz
zi|uA!&^phBy+NrCSN4zx2I9tEF%j6E?MLrt@nG*#wV@{)V~x(82zSHUF7~s3FdtrQ
zAT74N*>8@a&xbWoRMVHed<WY6*smwSs6X5GCkzI#46Vll*^v$q31gM7;p_p{nNAXf
zvsLHO7t4-qhoR%_;tH&P{_kV%NBiJkQ|Ci?&e%0DHTNX#m**vLus6Shwo40Mx}$yJ
z%6m|;$eaQbi%(Ip*pjepXj{r|hy1cnzJy21Jt-fxV!{pR{4J8w^edm!ru6rH6ck-m
zItUv6>~sgpwC?yA3~%F(Md;Z42R$2|TIg862eW=E(4I_k0NQpk+o#c>n2F!PU=X9F
zYKmZHfd&qRFtd9B5YF^dVipcEnfKvw1XD<9y2DKE-)KC_tRO4Lm^IcQam>?~XgtXj
zOr-r!0`oPMN#0<3(=GQVGm}azN|=@sSh~f$dIr0tOzCQHl}ztZz}GUjXj9d|%%aP`
zjq#D8?<I351Gsn0!zze$F(U>*SvQk93aVY%tdF7PFuN!Kjj8NmWG?=1))P$z{B@q`
z^A$kp%=tC&D}y=v0SYr2Nsqn@Oa_$<W-;f?F|2IHgU*WQFy^$$zRFyq^w2eCMLyt#
zOi#KtikL!Lv0i7spvGe6-)bnk!OWqelAFvEDnD*y{-x+t6Z3YO32ZZy_XCtZW}Z{T
zu7hbE3&b1dUkCKPWpXLB;l@g7@WP#)O^bOC_Wecx{MkuPAOY-#`LG+v_PGK{Y@H5(
zgt70w!)J4VO|1cmV(mg<KAN3NTajaI)nh1&VV7|f|4wAr)BQ1toj~cZ^Q=Q7#+1%l
zoQI_h_RoCaGg)R6oGD-(>21Q7*vbe1F0=j=puEC9BZDRE|CU4dE%u{N0Vrj^8jKO%
zX8X{-rj}I{qVF!dgyLs)?A>jE*R$g~d*J(jkDWgd6V=9I?rGDrfSwNz*^Lw*dc^)Z
z6XY>#MdR&Y)t^K66ZSGCx1O?LTLE~++EM=NIXjeYKQGu>RLb*`-AD8MimluV*Iu(-
zt+4xsHLl0V-m;5nG5wBxSpv?~$v!KA%zIY56xzD5w?(HPx4RjL1KcZGW*y-!uE${F
zxQ*mYGWQ`Aq=1{g0*zH%I)y|Yaj)qv;VN_32&EA+Ya`4j%Iv>^GdZ#?CD3_8wsR`H
zzbjkf1l)63-%TK$CfStK|91<xi8mksRV`m)NpkX$v_7wwPhW$fH_AT>hpPK>Hz$Z-
zO?eweAIle0ZPGLONnc35mTy@KpWn#?dV}khZ=y|&hho+@Juoi(2tSoU?c8~7P&fbk
zJ5aN5u!Rht|KdKhu3q{+6+(ZS)?vVZ4b$WIzYerda4e)c<4u#PVs-P|5rDZck5e%o
zSLSOEDD-BoQ313M^EeRr5N6Oi=nrLf%?37{8Bq`JAai~Z`l6ZXlm$7)JflZ&Jo9=M
z95f{`iIk#EWJC(0oMSqk!kIK?3_U8(Gv9;)pUy0O4}1m_`38tgX5uR}USOu3hng(r
z^UdJ0nH4?2<uKPT1D?xpv?{pBR8kH(k8zy`)%lF)c)$yoe7enCV%#W@ciF^D{0lNy
znBPJ$z^lx1Ds;WZ1a!k-A=76Ylom0Y=qkF-1csrpm^tQ*#v9D>Jm79J=2d7cVa{5E
zyT#;`!<lMk@ji^ch6$hpMR%B~dRVGuGHI23mwD0(FY1`^6A)=(Ohr@}*2;YSJ7gX(
z<AZ^3V-8Vxu$>vR2D%?I=k!qXh(V<e-6Zx=@;8Y+y8_x$Sp(fj(%4-!(2~wpzJp{Y
z+eq==9M*}7zVg^ti!r22>>}FnUuF9v1cyiWZHl+vVE;5dgiI+rX9W<|Yzbwe8renO
z@Xdv*`Admb{D{kGtOwa$n?NGi<TPLpu~ww%Fgv*b!jUXTC7?&xTRY&$QTEbKz@k{=
zb$A!e4v<6g7(2QGwqn@X6JR8k9kv>{I1?+D196;fumj=*yMYRHPO@*UAbN`3a0jCC
zto}4a6WEp}a9Gi3U@3_`Mny`=Y>6}aPP1Rp&iWj?W+Av7)+P#Ca#<CHe6O;<ZiU;|
z*xog8rjX5Tgh&y~Q~i4xYbsg~^X2SQTEtbb>(79zWUuD|SkHEi!9ee^uc-RJf%T_o
zP9yt0MU0!+qZE>FW;;iq?>-y<H*hWNt1IxSl{GGahY#42)zH$$=2ED*on@3z_K=-N
zH|a-gP(MgMW-CqU=<Hyx$AY|Ouf2xM8+Q6hIQ*7vqO0f~EBhGQI$6U@G`?p&u0pbl
zy*n1<1Dg?wzMb6Vk1<`lxSMp(4CHL--W9}MoR1Oi=PV2m3FCS-f;+;gDYSExoAw6)
zC%7@;6e2%~@DWCFhWm;#FDcv)tq{%RX83?y;L2z<Q^2h&$6zjTwp8SFnF|kt<W0`U
z08+w@r2y3}?rW+rE9K5Ff#hv&SS9+(ICdoZ%DIw2*sb8U_`sP;&Xqo&DsGJnRiRXK
z!>7WV8qR})g?BjT#~`(w&L8A1x0%*!b=*99s@HS<sm}Qx*Pp)ZP29LdxYo@1)28x1
z_kzmNTeufvVWN%eL+hh<?#g>`54l2m{ygH8v4B73hO~n`<-VRvRhZAX_=V8@oV#-r
zqFtOwC+l5g90!D}tj`<txyk;w2*h3H=!iZK+3Zgt=_xx-sc<iuqb)3X%jQqR%=pQA
zwZj>I*)1y44Ui3_D=<*@1=acm$uj;$-*MR*s?t6qTb~1fDN~k`1JQh$)d|QH$)21=
zYrBlyMxU>I_kDQbr8q(}<EIEpLt}vA;6;e+RkYoK?gI+D6etZ>6uN^us2EC7$q2<?
zl-@t2C~bw#NX0z~{vK6?O@yP-3Zn&d#wez7<cvv?>y6eEisKq6J*fzx80jg6Zv%kw
zirMtKnnXnsZ90+^!)rj2743La#Q!}}7B7MD+_&98&ih6Qi}Syt2=4;7h46FX*e~Gp
zqNMSVSsX*P+`sqjfPz)A6r24ca4r7+GuhMzp?_+I1F&%o6<_?@bPe5(<$LgZQ$!;y
zZQepd+j{do03J*}UCy4&jB7CG&nT&8E`WKghL%8P5*-l@Vn#H<`Cz8I8&^&kW1`3C
z0Y*#P>u@Hg2;?Ahg5HiA!OXf(JKH4Y(@a=9$2jbSwhPPzT0-YBW&eO&WggJ}>jv|~
zKul8^<B<*@YnTqo{x&do?!%dOW^NlAUor0HQ0l_A({d)5U4`r-ZitU|{{OWl+l^=l
zVlv&KHkj#8A#r#YRuAj}#&<M)4re9|206(5J{&fqnbx5YJ;uzT$4@*{y$7x*Fmdq!
zBr<;I{_}hwm5-z`M<#<i&zz>y6Y0#Kt!T_+ny8>4pAjj8TEy(72gY^A%^qHqGoFLd
zSizh&jfS>5X6p&C^-M9<KHXzhQMEw>6Gkb3lWgfEAWpGAw$UZQuBRAn0(+J2?1^l|
zD{x8dXY_8TWY&T1+Nar0D(ov{Po4sxj&<k*_+f4gWmhA)@vG2xgzHxX3%CujbpMIs
z=Jv<TMRVK6pz|0fd=6j?cX$&TW4XHZ5Q*c8X-bZBBi!Nd32q~0V*+LGsXQS_)|m$q
zEVH5KY=|tMjvI!`4pJa<x2)hSeA**hJ0Gg|%3^5Euut}$%98iXR7Yw36DBi00^)#d
z=4{vvmle<|!&A{cjYhA?+5o!=3f>;v8HEEqd{Y(mJOF8mRC;4trefu3h-4`~ryWv`
z;wvXeUR1PbAo)rW5DrN{v&>kSKV?>{MdM|&(dpo>nU!y)V~%BJU1R^>3h)7Ymi9-F
z*u7`r=2LbuWy@c(#@%q}ExU!{OuM+s3J&J*BV<g3!SPZeX5_~v0e?@uR|?xd1ykAM
zwA$4GPmiM1`iu-ZnLKkfoynQiBL>(7D`!CGLg}pu-HUpjfs>1i9^mgK!(z~}R6Pj}
zEK8jQ*k9)c;P2IOl-%Dqb{+=sZ@(zWY-=h-`}QA30_DlvHlTYaV?|G=U5sZH8oihr
ze-LkG&>VnHF|usPr!WiiAd=2#Zo*~`V^aKoy<7`d71tF$vj+wr0R|M?Bvxo$ib~-=
zP!u06l&1)YJQUFtyj(5{0WNYOMiWGrMDUG9JW^vNtW-lKCSg@?G>uY|7&X2%4L+g?
zSy}<9wt|3E?YD`4A)UKseY5vD`*F^iIdkUheJ(GxoKT*<1MV5+b9cZc<s0sx7R8G{
z8gDAcz5{hzN!38zQ~YM2rQOP+6OenNyvo}I*U-fP$gQKPS<h!I!!P8+^{BT;peLfs
z`17*#vK!jnql|OFi(aLDEVT41f#so4`d=mDL&!f<OuOOKDmobr<{DbzgQ^wOaT=;B
zN#VP?iaJ_R<!x%?Dam&7cL((W#pHncj3%`{pKG6|P+oFtA#YA>zDl;6P<V}=a)RV_
z%2)`Y8#IZ-edTv(WjLz-lkNq8Y^U>Q;8+K39!O@O-|+r~`(!2bZXfl<p$U&^Ew90@
zSACxVHme5?LiaW`y%>$$u6l8be2w~NG;81{@tMZ6t%r(rITUp%**xj(R`#xj$w$i7
z?Y#ceqdfWpTG*>>n+EP0^0N*!`|CGhb0bX;f!<AYy#@MeD6ARsJ80M?lu4S#%ste;
z9^!SR7l3+~E|<YlJsEjT_b;?@63p+XoxC@+k(zeH<-gL}r!aJo=3^#Yj&7^wm&Q@L
z(g#Z?D6|V|zM_g1=%n-XJtwMMpszh3c#XO_PwYCKx&duB=u94%-%$X6;@_nB29)93
zlK-^zd$Mr!`v+Qm5$0QIpAX<iddM-p|IjrK?mZ;@FE#qVi#k_vpO8x(1RqiCOW^j>
zNRCcCrkoXMT0cF#18R+WmUCGu)E`HqN}alwL&5viiS2Oam^zAA3BFb5_dwY#)vp6p
zI@KR|0km7anS`<@>c0o}YPme#4QHgwp$O>QU+(g+7?4L@y7|dD@A3))ga|2p#`^$z
zT>6JW+XmO;JZjar261S7muvr4_*C!uMjYDvzN_alFyGPs!NHh6Y1cK_-J_l69TIig
z-G1~;gZ4fL#P(~qIK8G(TgGGG0ZlsqxsSE-5ge{Mq$SUT7fvlO8xn`LFDv22r&{(%
zNc>G(5eV0gYFqBYV6*lWZvp<hR_h7*&ozag`!BRJUXc4zt4jg%l(w%K0%x_SyfN^c
z=DPsSoY%rvLHx4zp#J$_7jwKG9bO)5YJ<L+iKCz(F4zt7vu>n<6Mw4;J|uj~PjKR`
zU67sq;RBQ=^<IS7oYF?<PCh^=O=;>!+f$#hmuX!SU~F#kMtC*vV-9ntyRSjb`75tL
zL&kBQ-Y+obK=Z;wyshn(@@vD;x0$;JL(!u9oa$tW=5Lp*J!PnB?cp6;+4ZeZVMFp8
z<}gh`;4F4~7uQRE8wY+ad7@_C(qLS_8om>y`SE-!6=duHzi`JcaO}0Quu?SUHX6C~
z$St^1yy79Q9kGEEP_XPEC#<~jUMLDyE8j$;Ayvxk=}^+FbYZ9$US2||;sZ^#dQj37
zLwHe9ey-J0l4~z?7*bLbg3S@7S+<#xQ9+iXB143|u*6na;xI&6^K*+FHbYT<>Ec|}
zlon5l@++`d?T(O%nWiBAnT_UPW2h<E6k-lBl-TY04tdU-MuZzsZAosSP5d8>$qt>e
ze(qK^>NF}Wx6qnjn*DP(%84Glb59=HJIF&`SgL7K*0_(A&I7LQ&YREZ`dR0rv+AQ!
zvS-fFaWcG9{Y7P1r;5`Brz=hkryI^e&alqGflj$(r0VIOk{pqlWOw+DGn>=KJ6F9o
zWMQg2d{+IP)30yHx9Lvb<e}Y>(S|gKt=M6(T8i`S4nw5fT3Rr0BP7pDjWsxmELK})
ziOo`AhzL&%jIb1EXC~OQOY?1+DfXO_WtL)_A<~vrx>#CHxej;w%b|IF-mxiBnRCPA
z)1v&Q7zd8D%IfMDoYmFt4_)MKR~KD=)S<aaThj}^KV4Z)(n$GHshj4!TH|hd^W{*J
zInWehG>-Q(nSz3YOn$iG%*M$kvk=bF-X6g|ekN;{CB%{)Vlf&gPcfM-#);<1Q><p|
zB&#XQ91=3Q@-=@CoSx3t{Pj!G<=E6G@YIXdc%2hY3}b@u)<=e&AS~-%VRRP)JN^af
zLLgUNkhc)=s6)erz<@4jgb=3~vA`?vRMX2sG%@~4h+altArhdAek}yzL4rmLfxiP0
zGzR$s9#BsHLd;?uFT`@j03r4<1`1K@2{Z`N$cUipF-C0ty2Ln1h}(>q%=R*3ac(G_
zB)nKgG0qUe#Q1w5A{oPln8z3)L>^-l;(=v+5hFx3<4hqgGtLsCLw9D`^$-uLGs{1g
z>4|jGEZfU;tk#-k(@M~H%}y%UgNS;~PV;L094U*WQlT$Xs^#(ueKvhEU7oH$y_OmB
zrML7%rAp?$#q0!m1SB;l$sucjy-6|ys2F9#T79;XF8ct~J4eP<f}1XDE5WUjZ49~$
ztpZGu>lo7IRfbh^{5n9DT+SfmDTX5X;`#w9m*I7J7(l&K<&X_9SvOr~0HLm71K1a0
z<YOko<jjqzyi?XP2-yapPv*+0n^5?=T(=2a*aT4X0y$wbxJh#PW{?lE<Y^|;<%?Um
zG)Lxbft?3A@(56gm4mCnZdoETszDaX29W5jzG^){@sVS;>Z9pyfsEU#k9EE8OJa*G
x1xr~eYq#qD^o5r^juK^%Yy+ueORsH!oig+%umFA;yHporcxZoqV7fMN{15Ii)(!vw

delta 127137
zcmYIw2Ut}{^Zq@zopyV-m#9%=@3FUNqDEtlG0|v@B_^@NM2#sIu>guFTor5xD5xkP
zf=Cgi2nvFTSm**G0)mPSM8W?%eBbx`KM&8@JG1k?GrOnl&h8=M#CX5J@q0Tmx57Kc
z7-e1=jHAfd>c@ls$Rx5)Y@;L+iNJ7ww&Nv&R55*{3<dl31x_N!6_-A662-uMtVA}W
z)iSb^v!C>rN(4@^HWmgPJ13WwnB<C|R{u_Q{WzF^)n1gyZN~mESFCa@Fb(eEe@!7#
z<m>&QkxO5AK`3YuIO(1Z5DHral|<3xh&FZX(fu1nqNw<<^|Bri9{<-mO$(v&f7Zht
zjJc1r^%O^c^9b$Q8#0Naxjng1NsZZ#zs#ew%csjFawbeFkvK72&%=&u=5O1s$zdfb
zhRjS-uJ@;+M9u7jV3Tr6qhqwi#%y+cZTVxgaX%-K@XLc32|SLtFG`e2viBeoIQj5O
zMxv)aV?UlMgV6+5j^mwmtc2l9I!Yx{{s)I(ZTIoeJ1q1o-%Fs+5|z+rToWWR{%d#i
z0-tH+C1^T3%`x3-wSV-Sk#M6`6p2JC{sUoLiy)WoJP2W8i@-_K$0#J+=PiOtnnS|W
z7C|TN)g+N{(~TwsWRk8?auRN4i(r;+zamPwIW2-k+P@gW*DZoodc9F5;TDiE7VTeF
z575Gvs#X%kj-Pl5w^-%_KCwHu>>8RVE&4|);a0Rblt?dq0)wAh1i94L(Z$wHdn6DH
zf48ViQft2B8{1?}Wgx;o_+QK^N2qOJzYPz8Jk{dJBvEKzfizT>0|#PTF5-{^j#@w$
z{tu*YHPHU@E&{*$U+$QVAidrq*d&U`iQu~-8v<mjhv^DQckY(1l4!I}z})Ugza`SY
zyP>gnI`o4dxpbd9Aon^r(7KLNe}9<ecJPB$7m4Z_PO{>O1@%v5K|rcpp>M7JyF!%k
z)dHO$`B#oxt-3Rd9B*5F#7uUyYu$sn=9t`i7_-aa)Vd3E%n^uVsUsc72FEiT{T-$@
zU6}73pW+zpScKza$5tHwbezI*oFlVM7il-W<7JzVnB@*@+b+x{$H=x_q-}MMAKG>q
z)zFHQ#4B4GEA{+cRyR~Gx%@wIt?Wo5C%N)J@fVrfA96{;|HPHDd5+|^y_wUFy0+b!
zrH<C^+DkhObqsI!F*DNfL%Yekx8JdnNy^F8D5>X4*#SokESL;O9xUEEnD*_Y-8MNo
zwx8PJkt;7rS4{Yi;e1)|FO-rD#s7s=;@H`KEc2D)M*Hr4SNh5&!HWN*T+~)BIs5-D
ztF#hHh{EQAewTW#m&m;wojXisrZ`r0=+3NkI6BPh&~1}KQYK&Vmd>B&cZ{)+hq!rz
zip2S{5(n3D7?b80*OB^vRmb*HVXI?j$B&sv$N7%EnI9Y_9fwKP(;cll4PkzB%<ME&
zD(Uao+3Dksx>TuTl59>74e>0NE%lO1K9~Ks0l&!F>~~~$>dcIFyz112DR8vv+=cOR
zjPBfBDqHMW*?CCY`FJEs@5(w*`(>TZ`n5=XN$Ok^5!-o-eA>UW6%tuH0XIA>98ytX
zI`o}VB5T7cEWi3Ns8ar?Y8#{Y&yOHRrRdnb0XCi0GG3z)9If#zR>>5~T!+iYBU;Z|
zB9q8vV+<|U^8a807^9+fgro4|4yxHcc*M$1GG;}GV-B|aYNo=mq5DuN|Hcv4y|2CX
zB1ZBbj9gL6M732)<apNLkCiHMG@I$sQ&dd9XI0?&Cb1-v!5801ajbqP;OP67?2p%y
zO)mxyDv9eII(FScwFS#aUvUx-dx`O?h-3R?I#&HcM|<x8qWg3;9aq+pYNUgHpBqmA
zeIB0FlDH7kt9BFJovGw(j*=XhM^f#$VWipGL;=NLqGSGevj6HdF>Ht-RDCP5T>OeO
zGgi{?v@rU;#y+0F8D@eV`H^77d&&K(T#9;RBe`i)NT$_zYN8L;lBVJ>vg|aH`XfG-
zdMI}XF_?<UGB}HD#tbLT-HG&jdM3I2Xf@eq)Dr)^9#lKT-%f%Xo-_){vSnmcb(ktV
zhm-rXDMT0hiX1nFlFLtASsb%!Nb{frSuX#RY-;XN5T`P!);pSb{^(1Zk{47P`8oYA
z|Fh+EM367Bl=!>N740Zg%c%NEH!}4#(lOhgOh0aEhwUq(D;h}c_<VZH6>y8}+Z=Cc
zQx%1he4p$`ts;HJP72E@h4kku$Yy*u3O(^lI*xoonxM7xI|y%RyF#)$jR50t<tZe$
zpOKpxEqxH3Lq^k%kjvInDXbz~=n9G2l{8=cN^M>1N*d2tvecg@hGVlS2#*V-iJwAY
zO@B_B*S}J`1CP<~6Mcw5ei<R!C6O)dSQ$c&i+d8?XMKt2q>5ao9w2?mditF)pN{ii
zlP0L8+lRIUdf!5HB}Q`QpF)k9l1;yVxkVw~YH3E+Te5ll9l6iZl9!Z3;;}Dtkm<Tm
zs@_sS4g!3r>xO30(d80_GOXoBdfQ09hqfon;v)L(fyWB2b}w?XSx1h$x16}-U#Pb2
zKw^7wo@zf1qt?$KPcCmiCii1nn*F(5M@AuE5z!h4{T{fKj`KQ_(QUlbakFXY$e$yd
zE?1~_PFMPETt%ekTP|BoOPeBoB*(fv)Fh7|$l1wFr0Me!p*opJb52jSpZ!hP2UF~H
zo=(3aA@wQ!E~P=Fq(e2i?B1JxmnjG^Vg(V6zDxRqO0tx<*w1Wn+*nICNzSD2RZ4C~
z4yJbRkdbCSjrSzYMbvXm9#q@02QgnxP}24PkD6N3fg{tQyXp6{406^`N~GW4ppNbT
zl75#fh+@em(hP6u_Al?#Z(lr+aT{k6*7G1)`hH8l%P>N~y%0<;FOH_;TUYY(_IJ|f
zbXU^#Z+=4;Me$dpdaI|SY!T75-AYF<ZvynxlKxgKxnI_DF8d9o_T8?dc68Z742N5j
zruJLXgzO~u(+`nmE{0kP$xKgjUz9@)3+9QLjYh3qlFw6hVKO<Wm`=xE@yb?6{%Q$g
z-DPq)xPojlJ?I!-Ow<M~*$g^Lj)&{%H*2Ioms}%F-y-_GC77`DSUPTaPwrb~({b81
zs@=Sf`pF)WNkUx;T>;tC$h3JLMIGu!r0YAAQI{5*m@Q;ueM|aZ#!(CA{6@7y0_pfu
zCI#mtC7Z?fh@o2*{XUXHE?0j{sNXkG^Q1RPf1u?Gh_|cBWzX#tM6WJnBy^+WwuwY{
z{xfRppg9EleI@C~^d@jWnu$nKrjw@rdpedqBc54@=y#9b2$l0SS=J;FcH|feaq?UG
z{qr#LHTYj@!1M!l0-X4sI_*RUa(Q$U{r1AJ9+%-+B3e6&h?e|Inp0B<yzV;vjz3A*
zt{Vw8?<3N$KSK_}2Gen!NH%9Mq*h4&o=iudmK(U;Fk+kbfZVS%O6mGfm`y|tFR7xT
z<-YW9d8H1SN3Ha0q#&9XQ<tuIMljcw=VPyOa<kW$++RCK46`E0J~Ect`cDki&bmmB
zKk_F1)OW<ws*=1Y8ERzoaF(wB_p1oddmRCK({xU<s^z8maX0~ZR{}ddr(?aGET{fR
zK{VYUqSNyU)x4a7`&3S(A1@@-uC=83lV*>STm7hSVm>E*Z7dxRwkLgGdb3QFymTTW
zaWqkHOr&F)J2?o7CH>9m^t*X59YdW6?AG$iZucWmoL)uLXB@f#R=YtjmnbFA)^Rx6
zaDtSQrDrGz4=)*hd!83?9Dp&JQu5CXYGjHJ_1vm`WM7X72}T$#V-8CQd71oJ3cW`W
zHEClmMY1517*@U@&Pgp#)qyqiJ61=>33dgUerY1==PGieUPVD)X+@{zLlZg3y{Cl!
zhcW_u`Gg!i8b+4R-%*Gh?mjf2H@VqAnk>(GQ+L$W;)F>uhLVlbF*+{$o_gI8NBr%U
z6aU**c8dB_JhGIM!ZlP8|0#iQx1r-N7{VweE)`_D7niV7au_2-rDX9Gayi<UP*n-!
zGVC^ml{bi5JgViSUpzs~?^-U5FIq0}o%^ZRW6z3IAyKqixdKhMcl!m?HAT-oBj9Ah
zg+K9o&a(itbnc6KRL`5c4Zpv>xf{^=D`q49Z(g)RXbTK<-7Ph4!^v22qZYMmcNx)F
z8<}S4?W&H@Y-I|^qFddWtH~%1Fvn?d;mz!=Ly$hq&Fhd3GWM4nQ66HrO5hGNf#1OC
zQReSw@aoG<9g3iiF)#dq_hY`F49EV=>pQRvU|xNXP>(Ys-2gwqB(hKjGM5)a8N_5e
z!^KI)h2C+en6&92JI!Pd1a&ZTa1sD#n3%s1`B~<ky&T*jOffy9Lz&Dt;KP_vF;Jdk
zGTT84XEce3;ykl_7w{3xXFTd6nb&*3eSxVih2JQqlMc#@OwUyKjb;KoK^DVQ2SbWw
zW~9J<9P`OZz%Mal&q5i`w5NyZWoFt@dXZmY+P?!$0^>%HokV8%S(qj<e;$SVWTucV
z>})27{N83fhrw?SWBwkUeTPZ%2KQZNXd(djm?2jXXdY8OAKdv&T{3V5%r1I}6*88d
zC`y@S&*ASOlc)pBBc^N@y~rOk$@J=|WUOtWtzniQ2e6iz^B&4)%*v-=d(QN0LYwNC
zzkY)91ykCH;w95u4!^IMNtaRgno&%G@(p8|13*1<>^Y<c=HDI&w2|5S0@UxAg~&uG
z-ZQb6Q1^jhaeD2FEz(dLG&xIe?nQ{Zq}h`HUZCBU(j#Ng%}KzlcBTjHn*JBzY3+<@
zaJ%mC8vOok%@|Av>2mJe)Dsqc|5}d*_DlE0vH#&A&=08T2xkMI(Y1?f2-BJtbGh@!
zxSEu2>|J5Ww(SH)&Lb2m{%<++ACpe&=@r%e$1iXbZe=>rL}?qNUV=N{mH8<F&2nSB
zI^!|4lj(*zuVNQ7up4epUuMlhkR4;1%3xB@<W4|XO-y1ExVB6C(N()sdgpV*zF+!T
zrUd<eQ0ndu?qkwWcXU9QwEa&2UXc#p0pJbk)OyTJsexMIH|Sd@{|uu}kLQA}Z^aJi
zM^(yTI6DF<L&dMjt8sK^s#$~(#GG9U+e?h<U$pTi^Y9{`Ag>tnk^gpq&}$(E5(?dY
zJoJ^Hn6uH$Uj6VgQ1;IJ3r~|i?f&H?(!P{+RQA(h6sGJSRD$QufNT}IX<$PsnlR|r
zQFQL$ce4@4ko;uCF|_dvPUf%;2{?Z0Lc@^ZV{gL!gkjrJJ7we{1U4(#3HA%ec7aX*
zm06QOv~GA0RBvk3qhbq_<$>0@GXCp9?qI%d1dBH_P=G}MatG6fwXwIv8OyW;8ppIm
zdWmTXHJ+jPlu1lW$jJ=F+|qx-zGn2Fxh4<CRsrO+&ADJOcN!Lpn7TUujh_41tu1=2
zH#Y~z{`<TD9C!;)S;eR4@sw1I3dn$FjQ&@e{!R2-gdo32qp8nyg#vW5H#;HeLZ`|a
zlMTvtpZ3D<kDd>MlO7NM!Etb({%}5~ODgnVB+-m=_6)kcoS0-9A#Y*6K}uBN%sl%R
zk`J?^0o(_fx!VxgA?C9c=#2p8pMODNKhEU62Ji&4HxE&SGJg;-jLCWhzvq}eI@m-r
zXC46`!;B7rWh`@V9K2p-zWWP+6z21buuNq-pTW7g!-UX1dzV>y3x4l0>-qs+!Te2Q
z`p1k5wWX4&*TM1)voRI$dOMTZ6%HGi4ldB{kh->ksf%>+dpLBJYOPQnkj_VrTH!4n
z;{!Gy>1sEa1W7v_2ir;M-gT%uCG9#F$|&ipzhH7vTCo99L`yrx!$qoeaaXkWnsn3$
z)MZJl7%1;cH+F%tNNQKnIV+Y<C48Cm<OOtYg>>IbNKd3a)ab7_(xq$B7$;fdS^&4p
z9%=w^m%ZEt%iS_>ye<_!vW3OqJ}4{i2+I?)4C<Lcne9sy;j)+4;px1rcm+5UW!!YY
zlVl4p9H%pES9EL|570*!sv&nd)f?^Z`o(5tOQmA`w-~!9CcNDTUlV6s!tcq^4{=;k
z^Wnb_tJd5Cw7<u#rC{x)EWokvbtHQg15!JIV(<k@Q4H%uSKf%VKS49vwF=!mu53Eu
zow#fbkLzz*9*tb)%-xEL?>;Gms~?{<p!%1#lW<(~qz)9n+4IndIOXv<XwoHRA9py7
zSGr6=)m7ycYFWB+9*er$%30gtEKhk?1ELJ}$r4z;WP6W<$riq`2~G9n?@WMYq-Odh
zYJZ&O<Xd?5)ODW)n|->}sQ+I3p-k^O1XjRw$bp+8=4D$*#mqx`Q<XBqZQw6s1f($W
z8tQrq#XjjrH{fl*)Gq{t-qP^aAoP*iqfs1^3JgpROS9X9?5MQE8x+3M@9kGX<0l<D
z7oxxP8ycM+mu7r{hM$n8>_M0pq?^y9h?2gcX>+!;&jCbnTRQLtT-=c^c@ErNY119x
z?o0onnRu?$G6KqcX(Y{03#5<f0xgo}4}`K<T6!0jCDI=$6ICh=sIfzQC_VKvNXw<3
zl;x|CmNg>M$I{#5p{$bn{sdsPv=ljQMU6D0KLEAT=s<8g$<89luh=4M&PTCT=7KdL
z#WtC^0MYM|g*-<vF0yqr$UY@2*Ft$(_7k0|+p>LekaA>+0*mv1S2m#(4)4kChC`bx
z`<CW~d9oXnN+^(NdY~wjU095wSmv_~_y@9*8z{<T6BnZs9?I^Vg!D)@wI6U5vVoUD
zRw*mH3#m%Bf!?rBWLfmasgb#o`=_$LSU6BTll|Q!$N8_5-L-(`h3p9>%wEY9G{Ji<
zTke2VFI)H;O>2-1qUV33Y+4C`?_@t0K-nbA)WEV?_T4XN;THMPShUw!{?!^Nx641K
z#OMzB@IW|pm8aZCce%+QuSO$w$@9*@pS%1Z?lOhlLtfq=rhDYC3IOz!uRQ`&FL~%+
zaKBI9PY=`m@>ye0=PjQ%5QUHYHDwA8%Qr>B<cPeH(rv!-th<QfnB0%r;xCUWL0y1+
z#6`puDEHorD1zh@E+P6;@?M+a@3g$<b^y-U<+iavoRwc21Tj=z*$!-B@=KnGB3wRq
zG=S&jt42c^DbLKsC2&E$;XVM-^4z5eCPr=_2(~!+&u0L?B)4~g$z}Or3j2!u%W$+X
zQJ$5LD3at~rvY$PZc`zO6nQxfr>@EE4LQ(Wm(NLoX}bJIE5v<6UdyA%ly@8lo15~s
zSY1@ylG{hYMYepf1Ht6Tzodlc9r@ZEaNm<p908X5@<&zx^5nJjpw5?H@rSZd{;C{B
zkvz~9EDz*O&1hMP+?!^G59P1zH$hV_Z@mpgg*>$%Y#z%kd2mrBPwxR`wY)u+6%@7d
z-#&q-r}CsV=#uC1_gc`@$wU4H_e*&}6QX}5KU#>oH}Y9~0jQTh{~cs+<p(ChvQeIu
z0nYbw-D-4Klf0B(9!`n{bu=*Cq6n=3aH}HtThMG%M16$Vb|_4<(U&fYz83g(Q#|GX
z+^HDMfyP}SQ^9h#V#7kX*rQlm02g}|1$5(iDMF_~=}>sZ!Q_DA@E7plt*CzlhX)m9
zm!UkQ$esx5BZ}fK9PYoPia7^>Kc)yvKnMFN9u0#{fMU--03KI#xdZosiuaUV3{rfv
zm#!Vf!Kv^RtkAZG<yl3Cldud?oJ~Mom|_5p^3N$|(#;W}m{twyNJUNn+(#*<-iP0d
zilZfnFh-Gjibl<`3N1~CFDaJYg-yI7bOZ2L6vl(VCn!46FzdeJq&K8oMQjkH0>wY$
z;I~jw@EV~NE82XCx(A96VNjMT<^};?rf{VdfO3UNg0LSc4pAoPu|lMGZlz+!4Fu|>
z9G8s3zD1cg8rrSO#-9<?HYNWRg4v;T3<ttRIqV0}xG4?k@U&C;<1}#ZR{q4o#6!84
zQc9l6ZuDC7Qf^6tr~S&oA^-=JvnV0wqg+yeembc9JrO2{mDefjc0^fo1%7WSM~;S+
zZCCF27N&QUugW3bRWje8^1jk@I1stY)SZy>m4hf#T%dg4AC^T*OJ7LE%AKPSZ;4XH
zLn>81o{Qq4GQ^CS%9WMDXi|kzHXfXhl|v{yQl)GRL4?)H_iKTxQSSH#mbFTImo#{K
zuKZRB?mFea7eMn$IU@tW*GfqwOdFKNKO>5_%H}%My;t_2Wt%2t6A}c956bzJ{&8Xl
zzJd#9_UdiaZDmUuAceB6Ng2kTdI1mN?DdK8aGu?F2xO6LSrq#B0{gSQH%KqCx;%){
zY$*%BvF!a#powGWbc8aV-At=Rm)VTjs7qic&=N-?JLXp?li9E5!Q?6%a~{f6_D%tm
z*Vqk|f=pu*{NXp9O{52E20M?EK$)x`C0erBMU6Oxx7gJu>HT+`eKQtf4m+MM#Jg<n
zKos}b2iw4%%f?{^Uy;XVG3dPlHmV-s7qZ!umM>=KVq1ga0o$+up_Q`3Cc|$T+u<o3
zK4LSl463ML2ZVy9iv1;<I-i|Ot7f%q)l?{-vKa=t|LWKsv=H%v?M3g_*KDU^0N=1b
zPlC-`_V^Yc8re5#aM8rt==N`BJ4`|pPF%?dv}p^s&I8g`Zq8!_x{XT>hUE?}EFOgm
zH>)cEZrs<|2y`bmgPP>dwWmzQZqAw_;{Myi_1Oi}z1)^Rf%oFv=`wL}m#?7M&n?`F
zm=16mafm62OB#!2Cv!35QKWKx|A6uumrY67bS{Dtgg3bGRCvnd>R*BLCfACG!&_YV
z*HC72gFXXU4wthI=im;P=>rz~eQw__0CTyeG!4k-zFG=x0mtou`(m!^3F=_3lord%
zIQvnMKIHUt-#_Ahu0&l0cWVdWmE6oR;I86U&@=D}_sv7JrG}ew1`$5x-h2tbGj3Zy
znAC9xrlWYl-Fb|<S9Z?tDZ+ovO`8mD0~d<LUd3C^vI-90aed<;z2_c&47Ly4D4MW3
z@#|;8(wRS+0%<G%*&J|h=U>p$=nnpB8VXmwT>u*4#t;4j!R+EgU%`Vr-}DH9dhnT^
zfbZe2EP$maZ};8-(TneP1T_2kE_P@S@E>6dg~EsLK>727{1XdK*AbqH2is9T1WUvU
zKYjuY7yS7In&=$omCk6)3H||%RD<~5^h7(!xAR2ZX?_X$4d&x}B8s#8A{wNH@S!Rc
zVf++(6}0F0oAlI-;E#?#6p?(JZ^0eKKd3=*k#D^Ujk(AB(laHG|AUrN^7-RefiL8T
zgrO+nf0zZo5BS9X2(*MZV(P7U$ZH1xSI&2(v0er5^(SzT`R!kUvx*-;Z^LT-`4~I2
zwfwsQuzAYIo`Y1!kM@W3f)BY4{40JaEk?ZNWA~x1o{y_Upbh-6&(O4Yd~ql|z2})l
zXhbt#a{;6u_?6+fF183^9soEC6K{iTn_$$SZo6=Ua{DgA+9a5`3jdxIaR2QTh7`hd
zmr(NpHoJwNw!p?iFw!d7UcpYIJ5M3*U(`8-m@fg`CyZJMhX;g{dYE_%|M~)OUZ|Z5
zWrVPw9#<EH-_y}uQG)CDh&Ni8vl>yv2=9MKym3OP9Ceq3@>>$zf0u<xyFqhBNa+iF
zqOfE?JS7S9e}!~aXfgqjBIJ(+%{5^NCDpGBjvB<2E(BA0<%V!$7NncP8k**12^(ms
z_qGu7E9!EDb7@fC6%-nn+!Mz2g`-@d$%b=~Ck$B(5B36KB(2I73WrKz^FWx=2~vrm
zKMP=)P()MLhe8$g#Umk;hB6gGHNDd-g$7!TtrAwcg64^^;v$qa!Xl)t6;FjlGtec^
zgvE0}Rwv9jjk*^?Aic|93A!h6^javHilV_TOm{)~R+uyd-S$qnSqswlLIsTwnuTx6
zfcPNf8=>4HMpAapSzK&F_=m)Z@u)j2?x!o^sHpe_Ccfg=83@Kt9Q`Sx@E1SOdc<*Y
z#2o-mi21a96eQNkQJfU#N5kZ_Xn+0@#9%Rm<_TxT!8COW5&2v26eeD#5yClfCQWP4
zi<>!kiV!PkHTi<LYa~pf#EQ=F8!fK9i1x;ax&oZ0IMHw$#U(M~7?fAUvi`745J%87
zE=in5%M;0>%^OmxSYZ!G*IX0F`9Vw*Kch=1U5ry8?hMg;1*A+d#1B%IXrocfEpdn&
z+}{?P>OhKx<=Keot{CSD_&xDGjZ|~RoUM@Z#QYAx6^O1sqhkxjqqGuPEQV3;_<`6x
z9Jo^PauMBsW#ZT$z+EoxIE2_9iC1WO|FO7=F0V?l-UfWN_yaAZJ^>I#lejJjY}-{s
zm!j}eRnZvJp_;oJG3`^G9}f5XRg)j0IH1~G52d%t>V?8bHTF6H2UWfn_&cofX;Li4
zlTCHnfGCct#vMdZzN$?$2|lK}PQm!8Vg~`}uj<qlQh=&Q0z3t(PB#J&r25f@2v4id
z)0%g%sw+L^GgL?3z$8<(l%B6QRSz8gQ%&}w2B2@Ne%*{BNA(XG-cen$qPVMiegVZj
zl?h8Giu<Z#l#VP>-Ql1tRjsN<Ys*!OY3oI$>LumIs#No;AXTfRl<<C{+VBb7)u=XQ
zpr}<{|3e8E`0E%<S=P=84*~heo|=aq?UEh`RoB2A1l_G_F~a*;-VOThe-40AkD+_O
z*K;=I?LUdQ3Y%VUXfoBi*$=Jj6GOe(cjTuCvfn)h_Wegw+Gaq~U2qQ6P!NO0O#o`}
zsEM#2av%{680x46|FG<l`=R=@VFl=h4~WKb#8N5fM)ukUx>3%Q{~R;@CXQo2p=~we
zTAzZ=_@0!YpD@$$Y?{^n8!Z}cDo+EQGvhT8o_8~{HjoZ6-<e^2jF~zc_!CUO)li;h
z_R<LoW#(nE|LKmM>=G}S?PBfo5Q;nNc?*7av(+?M@L(%xV!DT&;fcDv?BTg+k|%p|
z4xnDFFO4<q4z>%;0QRxJQ9^J(d*vT!53uLVF!g5rYEbyF)ra8pFq=U;8ji3F`$Bn)
z^`;@3ADd6vMSu2JYH<MTMw9eFHl7|DL9Dn1p`B#+hoJ5hn?4<Nr`g4WQ3SKzixI^c
zJG*cN{GMf<TZ1%&O_ZPrWmnNkMi~1mE$*CS=dOh^oc)CId*|6d7omt?@5|sKlFboN
zV7Tj!-iczvR{?jC^?w6pH2Vd;ePUP#O#ouq{l6oaI5xr?VP9hHyAe}7J9+<QR9<F1
z-lDj|PK<#ziPcd@C9}(oi1aF3NMrUC_UafYQ(5oPaB+<-_C?s&S+^JPo5p53(x<oi
zF1QyAv)E5^VQ~xlTVbEgCXRyJ+wAYzI0bjvHH5y$ZlVnHeRc!wn8;-t>DidauIPv&
zpFPkGmIdr?%F7h8-IU-gV$V6o%`n;94?=jQ>|b30D`RicS$)WcJ^-woJ@zl^9<g81
z+IR)quOs|CW<R5K=1O)t`Ke;}Q%1C!{hTIZPuMu>)f%>VIO=NIixx;vS!)^GJ!3WA
zD4w$}N#Lww&rp*61v}e53a9KPJCfEtU$Im60Qi~>yb6bJSSQ+}R?kl943kFoc`1r_
z>@#|(G_%|hSbktPJ_D%}ckelrTeyw%2HMWeBo{8+^?fK@xwSG_?&SVn2KX*cMlS?+
zZo~=H?dFaK*im|L4{o8^d$>QagBW9LF9zM~$+e@Qt`}EHFF6PIa|!VKI5)aB_H(a)
zf#l8Yq~w7Q7e}ET<VMk6Xn*e8<tPHU=lc-Tac;mE08VhlCFr0)Za+QLg17}5x`?^_
z204Z_r#KHiXijr=^f(FT;(GyjhI@DpF`eZ`UxjH1_l9;Yg>wJ?29q%EO9hnYxD%8{
z#{lXpD9>|`Y5W_(g;4f1l8gQYoENxYnjl1R@kQv$i(D$@C8D`c1+*-N+Z#j+F|k~y
z*D#IaHqe0K68G<5;N!VLG@!f8Ejo?5E8Im&3?^{)bC43b_e0?+iF-?X3X-`ETTyqF
z`{WY@lgdpSiq>D_4vz!bb<X8Cn51zrSpUMT;|M(kZ*YaVxLq>1Bb36kXL7ANpz<bn
zkV4GjzFiFMEpGjD*kp4tli}$$7fcJmIouEBFuB8h{y9kRa!#F4+~YdZBj7&QBOTni
zT+t)o^0<IMP~>yzE{LLl%bf$xLN4GbPDK&tN;BkQZn-l8ePHK)F{8aD+^~b-F6HF3
z2cnGI-39oEToCP)DCc@@g6SjfjtZ6)+#VXJJmzjt60MTcwS{FBmz#)Ss<}l`@brXp
z?u5D;&W*<VwOk}+Wu9{1Q^#Ur^AhmqoD&Tq>NtB=I1n$mK8v7z$?Z)+Y_GWOKfv@g
z*M2yf?aVK5LJPh5!~ekY5YN3qn-24DGf{Vh-}o5CQ9hC$V7`2_4)A0Aro({y@p4KW
z`SV}=ga`xpDkWHs^Al;$<q2Ne6Gb4O-(?ZXApXU26esz%%YZ+{huXk)nm<F&ZR|es
zaIBkcwEs)%i|6>$E-(q_vz8&=^ZbgB;3<NSI0h+_KkEq>7x+G30T;#hr?sAod<osm
z(R{*HC}a4~=+O|%XV)U8IKIa~z%TLXGzf|3!&V}Q%lyq?6jylvT)-3fdBad7^7p=^
zv3U|NKMT`j{_jaBuJQ{hJCnj+rgv;Azu_IYukmZg!SXsE8x3F@--kyhr1QNa(Q7yO
z9D1B)@X?O1=9rL8L1ef1ZRY^X=1&d9$-2#7{{~z+{C9r?eTV1b;pZ;T)1v4-eh_kC
ziu?SJy+M-8SJDokJiZgHP3QA3SAnH~kE5-Rh5Y=zXhRXdk{VXb7tsje0pI@`EKB&Y
zw474PH`uo$_;S7trAi+0W9i9I!Dmr+@G+nE8Gx01!g<hC@vUiFOEo`=F1#oFZCY5X
z;qxCts^u@y62((~e=p#k@juZXvgiD>_W;!KPcETJn44{Y@+H4P0e`RfXSDkCn(xZf
z?DY-*dN#E6eD4k*ZQ%C}hxC>Y)uYoI`B*EWc*nQ<5q0nRHlxrbP5g{Z;G1~{n`1D4
z`}=FScM^`!RBel}@(?(kg=43n+$#J@Q|WDjzYi?83(20~+#yuW28)Z};m6?7=PKxE
z<FK3HehQ{L1qDrFcL`f)<A}Quw*qy$g}S|P=po#V2KOGpdIb2rLIW)hcnaz$;Jk#o
z>9BMNYiOW+K=^1mJb4RK|3aOQu#7UZ2ZgV&46QgMoSckc4htPU>CtyY$iX%s#Zlqr
z9u&Sp487Wp3DwlyenJGL`u&CSUm*nu$^f`HE`+rP%?aUEI_d(2K4Z}AAR&G@{GJqK
zf1~b{5Iq^vY2n*_h%i`Srhxj4(7QLnJ}Z1V1X75gq`9a)RH*+B+Atw&D1hgLwh@rR
zg_5BFo)^Z@WFtbDOCyv>;dmjW3qt?T5n+@NK)J$;!q=2ojut#<QWhiheT4{Pg@&J@
zj1%I%0_P>cH3-Uhp>rsdmxZ&m!{mz4_9^NT>_P@js}hA(OF)_=JQ@ZmSx7vHD6R@S
zC{LUs{QNIGr3&lMAf{`=jyEW-3xf|Mm^7isX-Mh9{nl`CL)g6mE^Z1#=nBjd9#x?3
zmf*J({gf@(=w7@n1b+(49ATyjj_wF{h88UD3W2mA_?}R^8xHRa_>2WNmyps7M4k{d
z7Rr3#=zSCg!XpEeg~B?TqZJAFD5p~_xQ77#K$!gojVKY4m&2q~h;~C=nNULweJDh4
zL?g<Dq_t2!62`^CvO-vCe+in$!rIBOsT77q!lp_%*%_79f_pfmCqgXk3#t+P{zRK<
zg$5dZJw=-!Jrnv;@m!dXeGQm3*U&Df7lNI3ZoL$e>FN4P_=awy*FvNQEN_I}1K_@1
zX!;X?1|dF$?!ULfW_rjr3coD?;+=5yIx61_tAB#BNs!QLLbGsu8e0EBaQO~B<0KZ5
zi!I`{osgWx*HXCHDsG^M>^5=HMZmX<Cn>$XL;Rc)@GfE;Wiwqx-(&#X#J^~{*<F+`
zr=iDgamq}H9^ybNXgtN9G=TCF$J3n4Av)6<!2xk3T~OZQuhS5(kC;Sf^styh8-I_8
z{~iV4sMu#S3O|uq0vG;b$PPFR5J#;<2L+1P(;)?kU%vqEq}Wf3K!e3ZtVh`uXGBdT
zv}eVEG|~$Z!zm*cDpoxPcbJ$+)8%vGkZ1&hi7cIw^Ww3^2sA?MaSWD`V!I%)T@ZWF
z>PM7lq%6!uaSdhOqs8Ep0K|yP!%)PEqv?i?6L%s{j>$g%4x!oO#ZRIjUKWQvLflux
zkxyWgAfBFy4o(!Ww}MTQSQCJ{WN|TV<-96RZ3QVsd_qe(sbbtoL~%{@>x)3Ii!*5%
zE=~O73%E~5A_3Gl#DOEgnIYEFV?9&kb3uJmd`IK9EMDwMx6>`Lz)`ZmWS9O5vU_4H
zcTnFK7Y+q3SM2x>Ez1*)v~w|EyiSvk0<kmQaD`$q&18ziD0(*)i>|bW`9R!P0!JmH
z?GuodiiJ-AC=>T?M}QB-qm+d#7d-|6_Xv@JvqD_!2eQZFOgk-2REiO_TdqpHa2SYc
z@rwf>eIoW#qpn7bISkTT@yAP0J{6-60r*VpNK=L9;(bcD)`?*>^nM}krnl!yF~<yt
zuf%G)nqP|#==JqRtp5t|dNIfabq!+E$B6K)7_{CFM5DNgMm+D(3YfkZRr^udBo<OK
zrdjOY8ol*FoRSF1N%bA&iMFT$`vTysnn)kDY*&r^0Obx<^E0?`Q909jaaFDO6#zGt
zE3FgmR3#1q^)A)H&wz7RouVC4yH)+h(cT&lRYwJE_Nd0TLoj<)KD61+Q|0>yxV=;j
zlpu1bE-wILpQ^4IH2YN<^j0~bdQ}U*-l{?$6h5j*`e5OpDvg?SNLBn9l!sL^1K>wg
zqiL=8sA>U?r+rlm7J=-T>XAc&yTMPD%EP_CN;?Fd7@!*d18k0~JSe$-Le)&8nm|=D
z?Gp%6O`*}oNmUjt+MH5l{EXtXN;4Clf>k0t63(cc^8h%j+Dr>|A*xa9z!IwZhBgO=
zsoqY3@|@~7Jy^n3Uu}jX`+3#(Z4ga_>J;VLBUODAAiby>(-Bg%YET2ZG)9$F2hv#8
zy?7LHs%K?r(<Rl&zd#eOdUX$eFRNak1=|%>zcP>|s5-AgA110w`$0-l-J|u9WYri?
zNLN)K4TOgjRiEPkq}o-f{ZL+0P3r^1byZa?D$`UIG@eRVP40oXZ>ZYRj5k9iCGJes
z(63>6Q&la(eU@rGZScIM%H4}7vQ^I1-M3YfR-(vJbwCFriS+m|;CEH483697>aL*f
zzG^nT?{Zak{}FJQr`os)Hu<U>8L%l(MNLCdtlIC7xF4wI(#*U><-P>PL)FjpWm36H
z*BNz>RHNxhR;hY^7RoBsH2R33TGg9o47IAZ)u?-_YQ6;AGgZoTwDW~()>rWNQdQrw
zh^MNsPlV}fRb?7X->Cczkm^-y&LG4_m7GrVJJsWbXyJQRTiVRhq#7!Pr)E`m8hL$C
zxycZPlRAy^v|H4Ucu3Cbp>%I=RlA;r-)-uSodDmizU&OZ4z(|h7F^U9==tQTj?SY5
znVY(Z=F>aXhu)!bms+4LVD9QcnUHp?dptoD9_sTQf#0KcnhmzS>VV@2)Ki_14;NnQ
zPfGxBsH+FSWS_d6R)_Yh|Dms-4yc=d1B<u%)G0_l>PEW852_QMqn{3`i+0l9qQmOH
z&cf!1I-2HGN7X4OLF%g>hds`UV`{+{lAl^QiWd5-b7}S#pgu!Ox5w3|DRq59?Mkad
zf$Bqj!5ySt-wF|)R3E49Y^T)0WeD`N`Wo#`3|1RY(><bA(pHVL>b5u)c14K#N`F*_
zs>jnlxG?qiv|IJOdU+|>BGg5#5L2YO`<HNdQN5H_AEMPU^!kfYFNp$MtXidpi#T;z
z94s%XJ6{KPyn0w?)LmA)_XXJ%wP*k?LH+3_a3-p&-UE=N7JDIjd$PK<0KZq&pOV8A
z^#EFSOjZ9I0^l`u&R`VR)x~E}q^Z3Vfk;=2&%t&>t$hz%hI&&wc*<1Yr*)Z|>Mtm<
znWgSDA7r=G9VnTQt=4`F&fDr;w7n=ty=o+iJL)UpsJm-dFW&;wd+La7IBWOSe+7Xi
zSG|GyvOwKP>&S)be7dfR)T3yrt61Hhh4O(~`W-Aw)Pt|0c&PqsGeRp@&u>Yws{gqL
zvZv~Y8_`eC)M`>bS3Br6R;NC4A1p7_AFhD&rP}@z?HGBbe)<YFuhqX*qZ8k#M|VXl
z>eXq#A&LgI-2~uUbv|WQ8r5SqKzgVCf@W3k)sxquXj1PQj-pxZRgAh1>Tz%3-bqt_
z8h|aD2s=DEYxJKXn5~)*v*2NyCWc<7+cn?YDPOWfvtSkq7fmVUcU?7gO5oizO4=&2
zQ&aE<l<t}Z9YC{NvtkfPJv5d)^xhuLj^!}ftC>MJyr<^*c+`1my8enLIW*U3r`JBs
zqFD%Szh*e)6b@+G3n25>Y#j`LKAJau?VvfRk*tCCkY>RHAP#HZ;u~AV5zS@l*`u1r
zB7nY{&PtFT)3jQQxcxM(=z|M?ja?2YK%=HR{kW!}H2^0xlV~&-sEPOjfFMoDScH9A
zvv3YLgEhmCLOP@IdVrYDYPz+d*;t6iY6T)xlS@hFFwGB#A)V87rg2TU=F?a-?Yze2
zBSaCQN&Ny+q()2McwErr*CL82jYu!WiyF2s;L(~DJs`zs^gke&SdD{H1aX=wDg0j2
ztOy1?UXx4j)XSQ7R{FH?istGruq9|tQx+mo^N8~2Nt!*hSevYwn*iymre7dpO3_^M
z06tao3r!oZX~G|%*RE?mlA$h5)0@tAx@O`40B&gR(RG}mxk~TGOieJYyWP~h@B(L+
zW~mv0-qNgBA|`vbCOQ<Rw>1m@Mx;5Kf5t(3NAu1N%DbBNw72A*W+N>b-`Dt2<{($|
zh&Bl1Ykqb@6a^X&+WAzd38Re#MVf)ffGgIdQYQR?hU)`miDtz$Se9y@OhdEFG^2YX
zn1`BpdVQALHA}GNTJcD8jwZj4HJd`=uu_xR8p<lo^@%`KYs9ypd7_D=_jZlOozfAt
znkGs~KGlTKuD55J*zSNo*Nmcl=5?Ak)H5$MxeTP&8ee)DztJqCcT~M*I@L933brHc
zw;KB!TJ~?$gwgi1cN(V&K)lyP4Tr-f%~5xdHfs_WqV*p%zXqXj()Oip+p7JXKF!*u
zjpq>4cI~z-;C5&=G88V_W$tLbt9I)lu()Z{D2csO`|^7<X_xk)7AEf6lqX=>t$k?^
zfsKduIE`36wFeKv#!EXi26%_oZ!KclryWaM+xKg`wL`NHXurXNtioGsz6%o{?Z&x?
z;-K~beYku`8$}P+!`eMfAUmS<rmVzKZJ{$9`fA5l!{IS){5IhHw1u=6)?fRgnBIQ@
z+H@MK9@mD^p0pF%B)VDxwXI*mCP@3bJ4{Y$>-+#brJcVMY^Swb$HFpLyZs=FGuk}r
zptIV@N$?w@)gOaNsCF0iQ<%2rJFuM7mhFXyaBW310zI$&jMhCOwEYj#j{Hb1{{-3#
zT9W{6l=iIyh>O}gbbUl?yZFF;jJEt+kj83Dry{ht|HO1z>p>5bE80m-;7-tfLo=U5
z?WkptlC(2uIGC)>?gy5u+9lgToub`74vtc_n{DuLUAuh=z5mj*&OOj=>DmqS@Vud&
zOq+}|w6{Y6%+%J=v?fbC0PhvWE$!u9=!9(TpWP6}ZS7SaY&qJkl>fM+ZA&-6eeH~B
z1e&XTJ`hplX?OL6GGCkD0e}K+<vdsxYQx5$yNa}ny8+&<So@Ne)*fipKJZ(j-S!<K
zE!B>uMXoaK@GC$()Nc1$X|lV}^Z&7S^<HpQYVXr$236Wiw3=J3{jLPDKhgeHi=syR
zHGQUBt36kY;;Hs;toJFNX`5>Rc&_b6D-U(rpl68Tjh2_ecfHn=l4A|p3sq3Q)tab3
z8nxN&LH17DiiRBTwSU+fLDQr?Px+l@ZSWvO@j>fL2q#?v?J(Y=`<0d~oOKhgqHe3s
zrxd_#x&j)3xadmhlM+{5|2P2LbjyB3u~QdJgV0^NHt#|0uG3vYFuQeEYoPSdX&0c_
zqf=c*e|YIUrqU{~LwA$DLfoeto{Prp*R7(Js{^{Po}%#9&Fc<QADurfSRT}UpqucJ
zPBI6ihjll}?-5<vV-!bq4oczs=}yVP;;-w>LK&coI0L|O-PK2sPUyaiKoO`LXT<3Y
z(lz`+yMRyXYA9cEN_W{G4o~a;p)L*9-JyNbXLPsg(TY%AeJ)xbru&mVVm+tZI~6A3
zI`e7(&g<sTQz}9?Lyn$_)UBt5lM6b{OvD?dJL3<_i@Nv$Fp1XnjY8Nly2x#)i`9Lp
z;&G+M>6ShO_a$BaGz4`;*E<GMg6`WZ=-@=%7}`3Jr0Y&gG|A{nxWB6Vc^&+w==P2V
zcdBkh80xO+DkZQ?*Im`Y{S93bE#_qCexf@oQ-`gGcvI+_>5ZDDD@+35mafB0^o2cJ
z*KZd5-qyv^3_M5o;TBBq=z6??@~-ahK)A@&^`~r2p03SZnB?n%X(_TmSN;j`g}NJ*
zkS)^vMayf&I=_}-lx|QTn3U)uX(n5$`<<4A%5+%C#bvL{UJsTET`9euAKP^sQvj^g
zH728Ls&uBVsI1nhL&5z-H(HK{*623v2V1SK!zoBlbxyQz;+gKt_fS69t)g8Gb-Hp5
zSYGHZJwVtmbyrt{`;~45ji%~#%P7s+pfd%a?yasJrB@quj`JXUr?Wp*Li=7fGX-Lk
z?nk`570tShH01f9vz>zEtpAb*id*&fHp66_KD;yPw(Gaj8+nI*ByA3I(Qn-ehpzff
z)u?mRTl%BeslP}gmtA`OLe#nIE3={8t>3SJv{xTP`$RnT-u6(0@1+mVMHCKwYucx|
zPyb{J{O;G+&IRItej}}hd+SGBfQgSjFA?~I`j9{1{*YctBcH>1?|U%u)jxTUrXAD&
z^%gik{WMCq`0F>*ie-Sl|6`oj<NCI=<ZwcNk-9lhAFHIiU64K~52Ppc9i+gY($B3!
zf1TF%KMjXx^=>gxhUk4up$ydv^lk{#7dyaxPJf?Xkl}jeVYoQ2??F?I2)%|jEJf;l
z{n4_E`b9fY7p<R2Ih+`M_#Cjr>W7p89;bhsMjruR(g)px7_Yzh0^FDNuV{pMML&=>
z)FkMwD^Vos>l83a(tn^{Ptkw>IcQS#=We37roTm#xa<0kec&)nAM_83biLq?x*Phj
zw0$5$zrGzp%hbnwjwo*Gr_*9bmVW<W8mZmV`_cxJ9Q}Cu-u#YU6ABl1^;@5yOYZ4w
zJ43p!U)&Q><m$`lO3Krp{RIy5^)7B;E6_V=`(dGe+zbGU^e=XTrC2}33KymNqxerU
ziZcBuTBUoaKS9&3a{U*cz&+A;$wXnV(C^R!@mTLekN!&ic-l}?rT^zGlr{R4uh1p6
z`cpKEda7SVgR*D(^}S&7Tz}6QQk{O)B+$Ij&rze-Ug|%i-Q}<JqiACKTEE(gx;Oed
z+A>$K-$M;-)JIUF{GC2yIeO;3U7x!Rz$X2~ji_waPoUA<2Yvge;C3?fq%p%5LqQFc
z&W7rL0NiSbpM^GUGaRRFE87kA^dxpORLlc>ry)QE_qz;Qnvc61ex%E4x1neq;2ws)
z)J{*s@I~<JWq3fz42Qu!s26PZ84Br}js1p^^kh3=SRM?ex1r0YVDmAkR>1V2!KEkg
zhYW9M5_s5fjOI2+44!o395w9u1`d4<_4F_}X7Hl4qo3h5?a}i$^rrtT5MUTU-y|J3
z%uu46PZ)aLh7@R6X{SVekl{}n8lE%^`W@0K!(966{<J|uJ70qhQ5hgTV+f-3`&mOU
zO{7B%KhR1@s9_Gx<HHOmX*2LS!*cq1Gu+@r$@KGv2gxWR3?CK&9%)!gBg6}a_jH<~
z3_jxkxM(PPK=)s?!MPVIV+<Jw5O=I$fD4)(XBe>>#U+E60w(c>B{a9XZ1|=p*sd5H
zv^OxpP)s@3L_^&IcuFz^kAq3FVJ9uAT{RTYqanqxT?=KZ;rE%KzGfIW2-0=Ky7iz=
zGu-V!BeitHvQ0qTFl1jxWrkq^JxnqUKb}B)ZyHL!08N(R2WPmrWvD&{huMaiEeR>Z
z)9#?jF-)C{x;use4Jhs!G7I79o}tY_;O-l0tWf3}*82jNXP6KTDc|6A7M)*Un25!0
zyQ0ug_7J8;h9Y`z7aQIY%>%>SV~|P=TeA^NsbSk^Fex*PE&}kOVc+L4DL4H26r_&~
zH$O&Qg`o=p9vkM-UXg0U_-|nO#L$Pn5vei!T7j5q4c%#@{ZqqIdR{y;1dK&te{PV)
zq1knY5=uI~FgW)|n_e0wn85bR@X0Z_cx}jvhr>69zV(pm4PVh_;0D9=laSsThI|WL
zqd{<h?VVvOy~N)eYL3IC$?)M%P&XU?kihQ;L(Wrlvy)M)!nxaGY)?siXS?y>H~_aA
zw+pD;W_<1h;CAC78V>F-mdjD+Vr);zL|5bJ2cU5?j-V&gPUE~{;CC6HjYkyjM(0mp
zx!YJg1Coc)l{Td8F>Zei%e}_$sMkG>@q-blmvImMCkltLSAQt?8SNuzoU-4zHVOCx
z#z92tZR|{gQXk`oZIBKcXVN6@kkN~B?1zmH=^b^%*oK}kM~!k?@$oh0bOp;X<9M1D
z_!;NZgT~+3sy_e$#`k+59XDoCGVp{^9sqctF?=1mImo!)?g#Ot(M+FpoHBY+e)hC+
z+9(vkMvrvh&lq#E;o_|ENerYAqYLeh3N@bJ0k$yXvS!qsGft!q4mVcMLZIi3uW4~L
z!Wh0DeGzGNeGTdh#;M&<L>Vh?0e;cwLJP0a#$|2kE0`E#$Wh>9jXAZz#~E4rGVYSG
zQ2<T6F@!d$UN)wFKyk&mun52e<J^|rBF5Qt<z6*PDZ!Fr>_r>7Q;nKD;I0{U6A;>U
zqbI$~(~Nf7dXjFOrv~*6W5Qo>n_*n{2d!IW8l&ytzG-yrh$ym*6RtzLWn7UDe6~?2
z1ov&@_%`V79OHCKZ{0Db)8%#7*p1Tn_l&YmknS5N%!Wy>F=Q}I@{Cp*Amkf|e1KG7
z9Dff{6dLpBy;)@3NUK=I#(^~w+<y;@0aGEC7#$nou+(^y9+zdtYcz*=XdK!a_;Tau
z1_b=bn6dz#DvXo90rz90ybDMxjVowFN|mu~Hd<e8<mn$rJuyboez6+k4cgjJYdm)l
z(o^FJntMJo?u|ec&yBqYfLdQ?TwnnA3u6v_T=LSm$szvH#=f98bPdMQT~NF=cA+<H
zqfy%ffOp1+1{Cj&+XE42lQClwOqz`!)7brkF%?@N6;7tPcTj9G^=9GE*|hmG09#E%
zXwTL*lS>qE+fBu5V6wxMzZ)hlrl!jX$<-7~LuoftoqYgEcbZ~pf5$FUH~NOo-4x#s
zG`mgLB2ajkM*4zgk7@N}6njlC=-+60nqJb<u$M_jt3nP_+rPoK&$Pc8b^A?UtU__X
zlsp$b;%&M^Pgft)^fj<NXi9NIryVgpq=(&6Q)EY)zx$eQ(ZzDi6hZqJ{Y-~DqPP7`
z6=$FfFa<mZ_i>YjuACDl?IuJKXfkQQ9c21^I-)pfl2dBol<E8S@O#=chE{5WO|xkz
zaK@ykC6}|Nur@FWF?Di)I@Gk{GNdrm`U<`~ZYonYy?w(?fz<5tCXW?x5n-A!1R+M6
zvS_XUg6X~E#)dZbj=iCaHT^(o{y3A266}{uS2z^$rbTKLmrbt4D6W_m(7JSjX(c6D
z6HS@TpiDB^T7fIsG?@0{Ts3uSfMtrQD?M{kO>+h#hHIuXtpK=g8hRWjBF!|LlHlp4
zRLUsaFs0aO^KORe>~OfxH2p{`tT#=cF9l7ODe@=K+%la!iz3@(qVMN#oBpM>tQ^yp
zJFvWCO6r1E-!=Vu1HF9DRB!`z_f1FXo6}qqx(@e}=`c;e^G&-JBbWkH*-I!3O_ON;
zQe=7-MTyvAQ?V~%dtmaV!Fq|QqXF(qO>-(xS7!S8DvF1u9VZZIxv3kalOCD2(SlEf
zsYnmpW79`T2(8kzE(fGlrarsiqT1w6Lyjk=z4X;djp^chxUV&J>jS`3)5fQ;d}eZ5
zNsE2YO>3*cU1vI^0nH1OZ7odSn8r>;)9OtnV}WllZ9D+Bx2AXWF-N1xg;x3AnGWv<
z+k4ZLk#N{#8q^a~vuPLYivD0Kr<bRb`Ai<#vc>GR7Lv2MVJBF&ntdIRwwagxP9M^3
zH%lqKvcr7G9e5Y>@TUmI)$B73&2}@_8&T{ur=}s`UFL_$sB<^}NqZr7n>SBHFdpU$
zC6M-*U(us_ulX@$QasJADB0p=UP3P#hj}U`!}giGAA+O(=05k}{(yPtSrm3}bKQLa
zeavI$!P7x=$9XV4WUi(>-(m9zx{QyQ-RN#OYW|JV2)^dC7h!VDJdct?erC5_sPi``
z2Z1fX>_vCOadR3y)K8f2(sVx1Ja8DKAoEXIusmsQ2!ZmH`ET0zb=q$JwiP@Dn{B=j
z&zRevfz4TS>$#u_F-vGF8EXEn3PqSXnNH<7a|+!t;pS&92<E)GiiO_@^R$^zMw)xd
zV0pnDMOl|9b0ZB>E}FL_f-Ks+q906R%w1`-VXQfSA!3R%+h_d^n@i@8J_RD)T=_Hb
zm(2$#NqfcInLfr!Fpuep&=Soz*P|}U{5gHFm~7V5Mxm=_FB@o5%$1ZNPc^60*4}I8
znG0ZY-5gD+?KE@eAe@7A^Wvk3;)dC?2XGnYcgFz8G&}5lz<tx)=_A-=nHSAQ*W5B^
z9|vi+x#t8ZZ<`&oij-p>{xg(!%ooqY<gU4!9Cf*7zkTqOXRf4da=y7<M7#y&pYl*w
zXij#6`y%t73!yAFS9}7856q!-S(TVQegUr3Y}-ML4Q1von-SDQ^B_vFmz%e&1n`mh
z3GLskFsF?L@UgigU3!(~e)-_8GRKWVUA6hL9^6mNqupUrV{RV>T&;P^e2_ggFQNJ6
zGxHNVug}dL=%m+~chYM23o}D=<(KAjQnoJ!isq#=K=axh+Y0zM=1Eb&*PD|95MqOQ
z7NzpvnzQDEt<gN%A^zRQ?)4`uKA2q|fXvCVt~I1BmJ?&pGG|NkAE4f9`QCy!w^@?t
zoA~XPtqE|j!}6sFN*7DrE>OB!a;ngFH_Ki6K4hn5^eg~&S-$l{obHzSO5k=|#{LdV
z4@*Nn0^4Jm-~^MsmLKhnC_OF3DPZ%m)NcZf!?JD@Z1!1lD2uS)(r^&U1D4Ij;P$rs
zMgMWh$I>wn(m~5&nyVhNl$XKeu;mv@1{|@Z4S=VkmM`de>T4Oi6CRFPI7*-SStdsT
z?r%w;t-b-4rTF+8x0t2uJ#0=`>go0gv}~n+Y!hU8(hDw5S|X)r#VLz3Ey<p?bfAY%
zu!Xn5<cuZ#b4X_`W4pj4#NtLPS)rC`O&|-iB>w=wIZG_f&BHC>NiaEY`Gt1hL|A@5
z4P~U|cqeu$ZZV722@Q?1Jg<k%MawzljTNz$xs=e4vmB+|`6bJiLe#}uqUhms+2Wx=
zamDfzowNkY8X8?ETDm%({?o>uHw1>MmMxUdxn{X`8y43sQ)>`snkB70q;$*Dt>}Xr
zmSPo1GAz#XA!S;=rJZdzE$OrkCCk#$AN_L6@?<q)$hI8%6Lq&Ot6zdT$8xVV+}*LX
z*@U{gmKQYDyk{xP0q(wK#^egH<ywBDFLU!OCSM@(Enm}YslYPV9d(74`<D<}ktOB;
zTohYQbph~!B`_T{B^JMh=$KNAWrZW_-`4iqe?h9SOrlBnW6MCA-Bnrw7lE_Nvhi0)
z)fO4e?w(luDVJ7bDG^ZATI3M`Jhdd<N7&CSwLih_bIY!J_^Y#=ehk11%Mu&9;-y7J
zbG28NSNFjA+Tu;O{u@hv4}@E9NwL#gputi;5b?gXth)h+jg~0-<no;*=q_Bmx6Cnv
zyUDV=3^dJ_ncgt@U`eJ$7bok8KTx;DdYfhx&Q|dy+;6pZZv|<ab%hpn+pWLQ;9!R}
z=W765tdr;)SXXP<eYkhC4q9x7xYOD{90BjLp6G<a-8yX%fV-^;l<@ViE~EL$9_tfI
zhwimTJOH<+^~!tHd07P-U^%S)XpXqg8cA>2{Z{XCC=XcKSCG7|oqEB8kM(=nZ+Xx<
zjM6bjtQY;zh@;kldP<4;T07IeuVdC@&k(7f^)%gm{?;a%*#}tL(Kd(U)+XAue8Os`
zM|7Zd)h8%|tdj#lbJDt53EU~GhSCeCt*vQ<9&D|l?P_PN$@k#!thJJsSwgJJ-%x~F
zHSJIrW=*<DQ-X6=l^HbQR_-UbIB&f}&&UYt-u(zT(wgap;(|5(3J_7&?0n!aTKCD}
zDcaghbBGvg9t}KVtv}GzIL=x-3GOdhOFUo_Z}p>9lgrlMB#^FH<C<WSU^T2nk!W2r
z3y$nb)~vH=OtQ7#KLB2}dec)X#k!yJ)T!2lk??!X`b8w_u3IP2SF>r>zLZl=xAvl>
z`3<WZ?RUwrDubcSw3-4C;Z3X84sd5#+kFkcx2#(}MHJcAP4vGfZd*;XY?xz>{0JWI
z*sV_wqVldaEenWy)=Tt2x^L}7$(dX$L(R^!eopzweCtS>(G*ytXd_>twRbuIMb@?9
zfEQbz1;YIUtCGG%D6yu#LQJLBNtGZgvl?hO;zR2%;Q*9d3+<qOWL=Vux(cgy&|;L2
zt<}U<X$^O*b2izdC@WcG9gzadT5CP+$9ro1G#D(;tb4XYdTw1(hQ`-f<r%PiVI52V
zM&PBjl!oE2tl^X_e{Ee#3)XL}i{yy9-WoIsAvIWizJZ^&)-@9VXteGc1i(9MCas<{
zTdypE^uhX#oxa3%vh8jM7h7!SE&%Ur`-QfhZMD^ZfWvLJ7#Zre+m=zfYKQF>W$s;U
z($!G9+Lla(<Yrs53V@xqylXJoWovp3hwe5zeP6cQ_TCB;58E<I4ehagHUb{@+J48*
zN`<HG>si!6Ube(BXs^S@(cZg#wvk66?YD){6!U;>8ILHuZ5iLfp^t3`z3LCzn&{(<
zL$=lJ(CovuXnKMkvDsB1J!*3aM&WClNJ;u*wwooe^s{A60M6gG?mAckY!jZs(Q(`G
z!}PK43ENM<!C|27a#z>{*;dg%-Z^R0(#-FaZ6|H*I&Jf?0ugL0`wcOjv9+eh)LC0s
z7Ih)EeHkc1ZBA~0huQ2rVmfEzX$Nb#EqViR=WUHNsf@5i?La?8+TQg;6c=m@TxolE
zl&x$e!oO(iK<}w&Tffa<i?Q{RK#H|#K7$lz`|&V}OSZ|=P{i97J_g{jZ9k3suh_0q
z&Mv|B1O1PUMBDel@RVe`MOmw4+bfzcT(z0nLrSsvP=u+rhI4R#4c!Hnudmy*eL$0D
z8<`7->9!MlpuJ&hRSr)Xw&8wY%d|ODdvDt6XxNiwn;Hv~Tef0KXlL6Rm8iRI%ld%s
z%CY@FlCC?h%j)}^WtvuMTJhO?@8u{hv*m1Srlwh1*-qP;A5c)X2qFT?#)TlD2q=3g
zvIGQV$p&TbJ$~=={rz=b_ug~f=iJNZxzD-hocq9_z}S78WUo&h6xPwx;Hb8d(}krP
zn^WOnthFiI0(JE^&XG{iVB?~MfsHol|6#1j<|>7mnr%L9gj|b_C&jE<ZEn#<)Miuf
z0f9$0e0ujiwt4X>sB5?RtO2bKo0L5;v(v`j2c*m9z9;6_Z8P7x67oGZ|1|)+*Cvnd
z0QA{xrHhOGHnsZzI$+~VVTD1PZ<4SuLpB=vSq$4WMuUvlbS{B0qc(PQ-+9a?vJqt5
zreX=kCTu>UqwS>4d~c8`8wPz0Y}#fUeHLQIX2E>4Y#I4K(jINcSWOY7BaGO&u;M5~
zOg_0iBWDJJ4vZsI4t|W0T8OC~XY`+eX^xC7-(k#&;Y2BTXU1)MCR`ZN<ifc!BIwZJ
z#<;11CU?f7KY)3HF-(bg55^0>gPdgCq9@vuu``^`k6sMLJfNLo3{&-oH=}$9TBjMs
z>jC4#c$&)J&oG|h0?n5Z@dr%vV?1gCs6V6SW9U80nEVGU=NMnn*(HFnHV)W<j6q7M
z2Qki0pcTx>{{>?qj8A`t`cOt#3p9i=gosI6=Y%tUr8MbzhVd}g;sWC(inw27d`dgg
zC5Gbxkjo4gs*a0br2PWUD~wOS1$HFk0o{OzVth?yNLLwt+hKh)!+H@aVi*%&qBEAk
z9|7hy28Xgr*BNo{Si?BR=MBKT!ALED_`Y~XVFd;g7{~6RnaH@(gu$DPA8v!(Vyx^%
zXA<LMx*eI!_~#ZtQyBB9I4_lvs)S7$j9*z0&txR#!t5-D(+6P5X7CHalEbKQgE6-m
zr@X#!Txva&hoL-1y8}$hXJk`Wwt(>sl{pqNey9aw5n~<Yi0&~~(WR?mhQAOtlrW@4
z&{N8Aeh%b5V--EEWsEl*VNp5b8)vXoFg9cY`T@hV9&(k8_{T7%im|>40@aN6|9OB6
zv6Y_vT815YBM%wo6@aN@EK3AyJ>yBLm2O}>+=1CPGR{$sr->0nC1=fy&(>oqEewy@
z7;9y`MLF~~#^+S|`G_H=jND@eF0J7~V>nZivx9M#KDFD)u)GY?#i-2yOE+Wapw|H>
zrgiH$)DAHCc@Q6DL`=e#A;wWERvc!$xe8+=3`QZ;jxwG}h1xMjg$mH)jClt!Ho=gH
zu-21|Cv`A)it&*Jt!c*5#ZWZEDBX-sTV}XBT6Rnhl|CI|+JA+0J<5EC&b9W;U;gJ^
zIxrL8#o#gK+r5xD&YYrDwj*=LV;Jhh)cuQ2XQnURD|TVtNJh(*`Nm$1xiNpE$g4Z^
z-aVk5VE#ngy$AEbDj0f_DfkF_J()Yc0E-v%mMz9kF%zj?$D7&sJjiM0(j@XOeVB(S
z-g1T+a|9B;%unbA;m2%!6@vcEgFm8mmRYzN<Q(%J#mWMhb5&T9K<2gpw1Svc+Teqk
zb`)+2V|LL-8_xWVobmI_%uuv0FxUIS?2F9J6kE8&Y~#Y1%go=+^x2mP<_BpQyu$pI
z38NyJd~(yGm}_0py2^Ar447!9%MO?p!z`k_cr0^(486uorVPe)<_Zel$1zvXb@Us|
zxAvnmo_U^PM+wX=4?z-{_LRW5$#kg#*e&K7Dw|7U%8|gZ&Pir|^AZG8m{IFNQkmQ2
zFfol8R)Hl+XWCF9a|ZKYTEt9d2gUcZnD5YWH=B9T4V*d5-YZalo4MyhsJO$Nq;PpI
zbKY5Ky372JK46f?yg~a>K64AbK?|66xtL%f)AJGptVPU!)xf^Tto{Ro#muvP7%X9O
zC@ECRoWp>M`^@7MdM#t_pa-s;x$!;(E0|Bv%kBYl@_)H3=1)|PQ^hQM6{MQ^1o`_l
z%&|(4T4n)xmk*iMo*1iRhEsuFJ@Xd|?>AVPAJg@vM&_jf=xt)wc7QZ9`+cFQg;}r#
zdRv)$+d$fw+b_YwN6fT$(R$2eQngY$b1Rj-b};YwLq#VOE-D@|W~KnGZsq`$()KV9
zP#I4zGvryw^)cU|mu5dxdkBgKnAWQ=!kR&*1O4QOn5C2+9A>Ve%DxfiFlAFmnH}$=
zHO4$oSHQ=aK5npkf@w=<{z>LaN3cvWlPQ}z&D?JX^)t+~M?q{^^Djfdj`c?>6dqx{
zNc+T5)~}z#remxg3K$+|nXGh7a%64sfP@pvNL2;StndE@nhUF*0w1odo3BF9ja5j8
zM0Zx-C<IQh-dhD057zGIVed&+7M=V&S!e0k>&5zrp8HcQjUUYRX6Y%BaGLckeO}#%
zb&P(pXILgWwD_`KFQ#a%AM1h+*7&pf-iN}otkQqLbB^^^GDrZ6NmZGFtjKGS2x1*s
z1%Y7JCzB8eVFm1fKq%{5io1ldI8^!)&U#FH*m>5gw0m4&J)I1Ji!6I`pf9mTsCND`
zD~(QI5v))5Q)&1W)($!wN3sU!EFQ(WO{FteSy!m`B%1X!eZ?h))lJT3EQ?8J<7=$L
zRv2@gRnrE}IM#=bK)b<OOF_YSmX?Bg2`uGGuq3h`H^IW2EL|%&Z?WDUhN2|ao?&z*
zvr?Mo<M~Tr<;FrVl_e%`GmWJkMJt`P_9N)cU<J^2m&ux;bXOKjN@wG2mfI6R%VE7v
zcMWc{{{9X&-C;eV;;UTNzpKG=mo=M8kMmfIC`Xykaytl=0+uHw`3qS-l!7Q?**QX=
z^&aaLI%^iQ`Zs{5gmr=vF{P}JsGjmZ%XKy+%2=G8fGKC){0}S@tY21Q>;Y>t1?4MQ
zHFPwtVlDm>EY++;8Co^0-NTTpWyL5l--j$-GcfB|E6K&LXU!@_tAW)`(2Z8spY)J4
zu~OavS~KhB5MWwZZ{CLBBi3As(LHAUU=PyHTGx-x4%TQRU^-cg=xor%dY7(XcC+50
zBB&l#!yK^mvck7wf%;giy=e8bUW|pn0PB7USO!^hDa<g$ilQQlVV3nzy4E(rN=gFH
zD65)2#XiP*V=V^9S$iqgGQm3fK3FDMPr*5wGsOz=1IsjP>Se6+46DikXtwNm?I3pS
zou#np2z!YWrgW6u{U%JaXS+QEXb1LdQxG`D-Z>AQ$JseM!Q#kvvF3p~vAfnmp)-3S
zy<}Y2{SL6(m92dPXm0Ec<&bb^KSO8Z6YLeVZF#VNqEyC7_5up|d9w9M==5S+$^dqX
zUCe<o-t16vOi!~fQ4OsRdlq@%XV{JFz~amHpah#Ad*f+}{Q0x}kHfaJZ1q;?JqO!>
z9l-X#j@bvYU#0_H5c}t6z!J=Umy$#wY+DmlgtA|wG-?=ohYWJz>~&kvI?w+1d0<~)
z%TGc5MfRHAkh{b_kOeC)vwtpz`Uv(*pF`jZyT_hB)*Z?2qK7kz9aRcVSJ}ZUVN*1_
zk|H-T>>p`QiDh4X0(!5p+eSdHvwIL1nG?s3@q?xt?69TK6wl@rfHQ&Z`~l<=*<qzX
zxyc?SkMtHhm;xwC?3l%nOJ+~g?b{Ugf0!;x!`WZ0#b6ryBiiTE*?!LhCWHNp90q5y
z7j8#q7W)cS=VY^&&`TnR{X02@x7k7Uu=g%|P7ONq*z+iAo6mNqBU}OdLjeQ|*@<+T
zC}O`=h}J#!lT<=d%zkY(I7`@>UXZhvvIptX*?smTZ4qVc%k=z~vlpI%iVF4@^iV%w
z$2DM1mF(T*KUT3nPQ_R?J3bf!HS8bgbXv>KrKjQ{dul6G)Uki2yi7fNlL4fGoyf+N
z8rgr31FVVtH5Gj|v-gr$-(qEZzm36G_AB4Pnl|<aH0?+1m&tK_%vR<=qMbcJwWb~H
zKc9z0CwmVI_I9y{DID6(PJ0bwJ!~i1AA8v+(}2>)o|u7LKl_hRpbW6HgwQa^{&x{N
zhuDvPf`(!CoJ9~AVOwAP3_PRk;b(z1#<s5q&p2C7zVrlp%>>XU*^AAX_7wXK%HU74
ze=Y}^Ve^-v)0UHX6asdf-_Aqe2&bMZLXL8b6d$(dWSxLs2hN8XU^&LAI1Pd0oY^bD
z>Bw=VK$R1xz)DV{Gsi;J3@)5V3g^3W{yTz}8z)JMF?Y_VOVD|O^B4V@JUGWF$90nP
zvn@b9IsJz~yf{yP1-+*@0SYX>H|NtJs6Wk-r$gL_^JgtuXE=#%FvgeT(1GRh<5ZE;
z;?GHTr)<et&h2qD&v7ok2Z;cVkoJT?&hafEL7bn)AQ8+7o&`-IoFJ+h4dtATg@s`p
z>s%~QIOlLM#?Et|r(@y;&SD|RMa~38xGr&iXJPCL$A#)VA~~N?0w{_TO);0N99<U`
zJVbLg&&FU3XZQ|SV>z2B$90XvrSiY)oR4S2v^dUZ?hw4eIY2&FJm<lCU`gOi(bN(-
zPE-?dljHm~SZ;B4)AwMKIFUaCGnq3$k=_)Jj8f>SobG*)OXJj$3zN=K)y=~5m%;gj
zYF;uq<`dAA#d%bX!E8>#PPB43y?UVC=KS>>48FtphwiTAa@6h6beHoo1)=jeZht~W
zK4;H02o!J@W<XORCo><IMI5hM$lc?7M`6ukj@xFC5>CYfbe3|yeGbN0?{gF{f|hZ9
z&w*e$CxyNvQo-5r6ZAgdeC`H?l^pdWD6Ha4P<=@?r)xD@HJlU^#%ei38^QUI!|VX5
z<GjBOq@MFL)!jC5_Qpe?krS~97B+F({(?X==PP>Ev~Z?3!QNIYXYpmsqK)$poeUmv
z7Le!nnDZtDN!vMZ$3s&G=j$4<c5*hlK)#FPJ^>56IeWEe^>7*~eb&o4Z$zt)^G6h>
z-OpLF9s&dS>0xGroYBw0GQ{cO1A3T)ZyDgh<8X_>GRm<Q(ABvyj*PB!jdLRZ1nUIn
zZ;D+`avJG4HpSVNidjr^Zrp<W3`b0P2wU#jDiAwv2RW=qxa)p}O-H%oXTW05-AxB-
z2ktpOrhSaNmG=DO+yftgIC3+p0p`TbqL7|5_ZRC0$h&Y0>|v=p_n8*V;skeM2!kHn
z1<rsu$z7|3peOew@}0c6I*NOp;=bev0dFq<5y)xoyI%vvhx<7lxz2D`@5Ky#xy=g9
z#g99W4q*P=N-Bmw%iTq(?Q`6Oaj*n%|Ns9n1ajwv!Kfha7)2|Cxtg624B@V%;;m3_
zd>jPBxYcy%4(INq2=jUFdlWvqz*RP3>>}5LBFvY#%Qpl2GB=U-&IqoKg7sIpOWc7H
z$z9tG)1tU%UWUC_xreC)ESh`m9u@q>aD!3+8p|Dh0-)Ep@fRR}o$KZX>^N=;ZCf|E
zzkLYx@!Y4)08QY2^bjnG+<8>(a+7<o4cNE11N2)@;-00iX(n?|QywCP%i9c1sodE;
z5KrS?q~BaRckgqM%iz9ON70^4?tUti%HsY=u3I+u8v`VAxNjz5oo{n}s7&S#xAr(%
zxm+0)r{3j89)mz0_lw`q%I7kqFtmVMLf^V6<a)mY@gi<%4dm`|we<Qe=6>Q2@e=N;
zV=%Oo>qIe_``okzV6m2Qbxz<Z=lThtzJlvU)dCN=?Xxjh$^EDu^R41K(goIP?gcA2
zYq(E%0IilgN!huF+yqLy*KwC_z_jbRd&VH%z`dY=X^q^U=?vY(&8>xaGgtd2G_-KH
zUIj}l*L69d+pOGW&RCj9+zk{fd(6$B51w}JfCM}p+`~K3*~wi?Z}Bc}T_x=9<+7sC
z*~k5C7Fzw>MhZO*aKom7Hpoq)NXrn{GZf;(+!QJS8{y8QqODPG2!%q&xKZR{j&nKW
z+D>q-g;Y2@$zA#wWQyBFAGw<5e!CxJhMTz-JhnW;C&0Gjc`U^&j_{6CA@@;U^nJkC
z^VU)9-+}iTxktx%Ra7-|oF}HI*pc_cJuHF~&-Ee3oOx9gvvuKdZ9rUkgOrnT<Nagp
z$DliJn4;$=c(ds@=fOKj!L^gTzsd3R<lUy)X)oT#uLJEA&+9)3c=JxsMsu1MTn<e>
zyknGLJ;RIAV9b{{Lzw_SUK~{&`}2;_qkWe54o&GC&z1!ez*|Tzbs%rabChHZ;w7&^
zGnglM3xgrNXJ}5Lyn6C8!gy~|K|(ms$7|8qrPc(R#3kN3ssy;qbJ_uuB6zo`n&}Ep
z)C&^HW2#|N6z@y=1zhFnC?62blhYeLhPT@cJ+Zv0GLUOL6{Qca^W2_=);L}!y#{XZ
zYR*ACp0|{u$q780O_*3B@3t0eev@b1OcC{4yzD=qDT$XxNvCAq6I9He!qct7SSoM-
z2N+A^)s|o^op<R=Xv*NZXF)!b$K8jCW$}8cA|RWW<kgEAwSEf5TwdE4r0?=7-v(A5
z@A3oi=kprq!b1Ts?N>k+^2!VlE8^{ZAEbmg{Wt6^<t01=1^0Q+P;pHePaF=pa$Y69
z11orG-(&0nPeFm=N?s`&q>7hBpZ2Ndg?$T_8r~b$T<ERkEoy_NhrHHY$k*}SqS#(N
zubK*&8+h+3f!)YUqjhcK`M!p+W?nWu`z^fLUx1~R$BBnr8}A7UY(C<R&<8&r^BCj?
zwe#lsVO=|T%WW~%$@3vkwu>jM2Us^R$B)kcJ-m2ZNc8fe_P~lho;(vg{k-ID7#rZ7
zehM&yytnCnHN-nX<`46>Zvol}?_=^OMtR>;wc!|V_z>nh&Qq=j_5{zB0-}?=0Tl$M
zctu8xP4mnYH<;nw_yJ(H{7Qd{zuEEEUW1Awd?ghrALaW~O3|Lb^LMly_+z_a#W8;F
zB1jzPr%|nqBR}L1Sm?wLjslu9e;E~fx$rwFUg64bzloL`f1VHm?)-yPTyui&N5^Ro
zevv)MNq#w9==J0m<Wj-47hjl$<|+Que_;{4`SHtP%xV6*dJrFe6+OIX_!Fxz=F3k#
z4tYQR!snsMpTG1&jGg7*`~a<U{H9~j6u=MI3C=*il+MFJ{GBam1@k|S1y~5b={j1W
z{53}C3*#46fyElm52M>T=lMU>1N#D>`@eVz-;Z(?m-q+iLk*YtS1tiNg6~Raj4S*L
z6lRa)KTDH|;zz%Mb-K!bmV(*Q{A*NN6vGdsu+nvY=}m~o@x!AaeuIC$79^hUM_X(H
zzmp=kiB`UW9<iJJj#jMYEq<RT29x+*D?yU^-*$qe@Nc{iyHoi~<Dfo`KbO4SbpC9*
zzmUQIJ_eJ?<PWexviSXU#?R(gJqIgt_~~?#yv@H(agsZH=1XYh@?}Rbc9-uP2Yd7Q
z*3bU|c0NC=2F(Kg7zH{C`BhZaQN#}sqIHkI>qVGW%+IB>X9<5E-Qy|cKSc%1_xW`c
zm?`5sE{FPZ{$2XXSMYy4fZ0Fb2i5_zk}si`Ulsp_{b*J5b@VjV@be-;YWXo%39ujX
zz2C+}>-g7wfmY9N+lp2LU*H5yjr?Dz8nuakkpY{U`KDZu7XEAsLbmdg3c%9Fms5iC
z5&sS)J|6S)`oPl8|Bk{+9eggGX*&5&)48&XuYU_*-TWt}KzjIpHarbYy?jqEyWpkP
z#YX`)$p2mr&LRG_Nw5s_8>3+T2;b)tphx*9696{Gum2uood0A1$OJ!%B3_gHT-@K8
zGsXXvqG8kgKUZLaGyJEDfMP4y;SEeXL31g<jtE{RullH9{fm&Z7nD<6)IqS<ngDuC
z;IatT9~boA25}VF(J97BP(21vXTj)Ev|I#!1_-(e=1`G?n;`jJpt%b^_!`EX5cE;j
z-a~Nl99T{YuG3-DQ=p@lrI$dl4>p|^Y_LbmN6=4u?HR#7s-5u_EV*xm3O|7jeel&^
z@XS@npB3EEz~FO&ZVU7V2;LWC7J-5fC~+7h__`Ykg9VwCEeH{CsnRV};6*9lFo8WC
zuEPa$C?9fO5Khk91%Z*Ga2Ewn*#i2KV0$1~E(?Y`fD$2Cy@Ns_R|L6V!kS3Ii&PR5
zC5XO&MYt;HBTp$>@ZAQ$#0bi0vy2riPJvC=1O=NQe_fEh2-e35zOo1C4Z-Q{5QrDl
zM4&T4;4}}dL_w(#&^HCM#(;85aE&t6NdgW9f|3OVczO|v6xdU5s^Gg{Aebg7Z3kMq
z;2KrfW(XoI7|Rswq*~f6!A%OrWec`-06Rwzu^X-1g1c0XbVm>v1x>kvJrvKmEBJX2
z6y^zjrPx-!;5(}SED-e5R$nNHI*G9&!2-$;Snmmp<Zl%V_OAeIiD1)D;3*Z%qP_3F
z;444aR3><|0AuBXFDTYqA;`1C*aLxy9Dzzfz%}Tt5`4b|Dyjt$4#2JvL_CeoT7iPj
z9S;T76m6^%w8lVDy}-c%dK(0JzkxJb1zoiOZ4wkw2BcZAaTF3Qg2QSkY!$rOgt0ck
zi<BRDB(VJx<gp-zj#TY}@WU{zL$G2yusa1Szk)Gcf=xLX>lQ?>hj@>Gw-|Hj6{wQH
z(kEC<Kg)i>Q9Gav2x|MGeo$a^*pJB!37p8;7!}MVM`BE{g=!|o1sk~NoDhsqiOHnE
z;t4V(i1k_%zSMe-qJ?(CYaw7fBHT(T@}t5h+Q4Bi{38w;9E82$u;rML(TqRHap8^;
z7~v@N{okV{3?k3dS;(Tmpo_3i1Qb`{#Wx`CCOj7i0e7L5-ts4e?@~Fvhfvdkl{hI}
zaSDn&g=%XSX67aQoObL}!o^=ep|>!Ah1O}|9r6o&gbpbHJtK_E!I-ab1-<+Igi9#E
z?Jo>G0G6}D=PzUIoY0mEj{=0V^Dw1AVIesJLBf5TU|O)S0^bmx6C!+e9$KNo8}u6q
z6Iwi|<UU;JPTSOZVSPHt1>wq%Ab(NV-Uah72`yB0cv)DKk5+_mH*HK;gimLqGg8<b
ziHSxDzxx=Pt_oer5r`HpqD?YJShWbN7Aq890p>NKCuO9r3k&OEZ=7%_ADuUZ+yA92
z%ke_rNq{B@tvFH5NfiD|DUX}N&wqizw}h{M48bI!b{J#H!qo<l6yeqpC`=X3m1FVJ
zgqstfFkQ&p2<!~ud*q&G3b#E8lq})zn=qGbVK-Iq<On~e@YQYM&uPHCBP>}@k8Q3n
zff6=%g{4;knkV$NgWdT;2E`5wgokbcv``q9iB^&D8%kB)6VAB_v|?fRZlIM2pIQgG
zQei8_eeVl@BTuVLm{1Lta-kz#EvOK#KMb3ygw^zVt`>gz8#rr(^>l8v)(Y2mVep~w
zNiWQ|4vT<Ry>LBEra?IN85A}OQ>cKsNhm!JE1HGRzW|mNp$lzxtwIYuXl=sf1u*83
z@ZVT~J{Dfti_Ui82mTP~5dLx#YtbnzX8@&3n7bLKbqgbD@p`Pn^8L`;D}0xJ34Ox!
zrI7Cz{@o501H$>VXATMzd@wd7+(oti!@^@NuxUh?P5bz$@Rdzit})>!uL5*jSVtEx
zCxj0vx;ZIyj)B4{;d#36HZ6>yx8IC#Bmf$0MI98%vlHQR3I>meK8ga`QPIjYz}SoO
z`G9c{ExC-=G11ySkmI6D6uxp4ok)d%ljv+DSe!+lQmDv9^b5s9T}3P3L(5GRN!ygW
zNI)6k6QX%@pwL6~4n;RliaO}E=_&HOf=PIZmRWhAr$jy!Quh`;dkBN4MR9Z+!bh}*
zE+?E3*;N6}SG0ltqJE-JDT3)QN~ilbXGP0rL*Y45@d~s8MAL6VVW23EiY0<XH%8DI
zEP8hUtq_q1ZBwBl1=Y)hi5xFNZMf*IH_3xPFJjWy+%AaPsf^{KXy4Zmyd=`8F?Lxr
z!-Gu`qGJ?zx*}RdyK|%{unwA{MDyN2>#C@!0xZ#@TnZD$h_>58Q>^F^nRZQ7O54tL
z(V>4J5GQ(BjLsXPj`v_iyy%%g^57FhXO=-zqA0Z-MkR^HzlEk`k?1ABq=*JSgiWa;
zJNlejn#idbFzKSM0+0;R(*4kzDf-?H_GXDv=zW<j^8X89IigYe&D|FHkfV1;G_?&R
zSHzEmhP$FE0mSn}8}HFSPRSQ_(6=rML|lq*6pCi=fx;ruWC^UeC$e>cieiz=6&PG1
zTFii8sR+&(9yQVM1O&=NM{1$4T=XVwtQDdq6i|F1s&Rl^rRd-NFs({7haA&t(fh|S
zRwG(XRp7NEaRkP!4@CoP$k&NNJi${hx=5~JgJ_ac?~S4$+I^ZtF5@80qK}85qD53h
z;nY@<o{pt$BL8#<JQ8`3=k!>_p<Sz8v|fSb>JSakJE>DtaRVB<L_hxq%x=-;FzD?O
z1s7x1y;jk@eGu#u^*n@%e$kqfz#b3<(bh63dWRx{Ln6;xXbp?5jR9svbdb(eqawE@
z7#kC5PNOw0>b?fh3DL#~bWVzj>3{f5iEh#7r=~@-DbzY6nnlZHD}IZjn|5N?Jg7e+
zw!)plgD2j$5lwq>*g}}-AifX*a!maF|C~uNm*QTI;$jMEJBfE>Lxr>WQ6MJjB3}6o
z<Xpu!$%SweTRK79#q5I+I3cbzgLsJJX%9Rpe)tQ<JjE+2(DD*nY=Ck~eA-HWr?=Sd
z4A4%CGv`BvkGM~W`JNH4qtAf)iWT%r@)M^Zhc?Gwe1Wce1c(cwvFd^19ifm566f<V
z7A)>r2!$cyMHHS46^HU57bfne8rg7h-!s5GFAntq%LVZ_iCDFZ;-5eG7K4|>DOPB@
zELLTs6(RnQZbe@aH_m`WiaW@SixPjA0)wxLo!bEuEq;oQ^D$!YHvkhW7E(avnz)i8
z4cEo^d^jF8@tYLGyCHso-oo+Xx4o`JvaI&qfJ_p%I$|hU`~{uHQ^ecnL2Ih`GR4Ky
z#C6-jpDxbFU8Fe~;+UgQkSVrKz=kYwG`ZE;VxvD;a>QTn0oZME;~!wTBYt@s#&X4l
z^n<-Cmb?P!Jn>u#Jm!n*av)G3POxTx7K(qTs-q&YsRW?+#K9SmC>B4og%u^@>%|x=
z6?ZwnnET?)a7?94e3Ftk<>FN{&{QG*umda)#8dPg%t~=0?XFegbre3W7JJ-7t44f~
z0nS>nk^IYt;=8*6T_+B`PWw~6m`88l25}r2+$e6OA5fF{Dut1n#r>Z`Z;QB(%5Pf5
zfpk};O&lEr`A6ca1_(SBFQ=4dyEu0P1UkeAiZIqGUbG0%UE=9{uyl(*{tz?k5v%TE
z5qibnP_15{`0c+aUDGfAYzBh^;`eXC{6X;%JyZ;dx5z+-#anL!ZA2VHC5ofscKTI~
ziFZ9h=eW3h8*G{o+b#v#q`0>nWJ-L1vWT{lA1L@>Ct0xprX7(KQ#r^{iG;#X_L6j}
zlXs9r;#g^&b4)Uq>fMh^{%nSXqvUNmaX3l#+CtD-5<y@0a*@ov5B08+^K?3OlkE40
zfV<=$N<*BGC<ItM4@u-_kUJ?^7YI&I$?vr3cu5i{I(SObK{rIbC7UUha9W~X2NWO4
z!b>35Gm_sa;^iy(_j^puPtv*?68;iLih7)tT)qmJbCMtF7HNRwH7d;slr&ShLXcz+
zou7jxljL@WNS>mHAylFv3&SMp)vzgC^7-rFJTH086POnyy>Fm(QSuIXh?gYiZ(xF#
zt&$x-!l($z^NAR|BI&D#rbx*h%DzNNR#5)$s^n!_(r8KjRtUyO-Y)}otmGw1%wCiD
z(AS@?OEMU+B2F^Gg4_*BKizbTmn75cGC|V18PJK6%tJuADVcu`0=FdJPJkszV!iP#
z)F(^wjp$90xb4Rxrb=Fq1x%X67>%)Xi4XmfG9=TLkjRweUP3ENvY3w3*^(+x$mK}F
zX!E!&c|gbMJCcwBpyWzwFQ9c-((?|$@+3iQfaOc7c$i>;WD}k53MCm<iVhV?K2}5G
zo@6o%DvBk7O7N6OzLtZhRI-|qF!v>sOrVuXJji1!mn^1VaD_yg1!Epa2IfJaQsPts
zfhtL74#27<{t9%~NP6gXTPt~{7xq4s)Ffc6PSQq~K^i4<Q|S3?k~ork(kwYS0QnY)
z4-4znDhWCX);5WrvfGa&;fG=9V@W%e8MaIQ$%A}{M0N)Pof6Iw7}F)$eIH}plAkH&
z(j!S<29{pQvlNf%ldO0Toc)rT23Rp5>7^s@pd?#M&c={rAPfqJC4QGcMkK!;f!(8$
zCW=vwNlwu*aa_Ww0nCJC0dY=B!st^(Q<9ulVBxf+;!|MHNdCM5PFtx9rTFZm=Z-_g
z5$T)vA#hZBW-VIw(ry+69HbF+&G48sflcK?$EACzMBY&vRgXa@=@4zw&eEr!f%z^{
z9i69LrM^szxk+!+`_f(dZW&lkNXM6fct~HFkFk?d&J1kwlzwp%i{K@VJqFBE(vTz&
zZ|Qa^rgU1m@jqbtNc)Q+a7OA&u9DSPYD?RlpVW>b|Nc@xIt8AU&LY?JoYb`#3In8U
zI!FXc!@bZMBrTM|reNvcRCg014X2lWsPy|rh=)mEqqudr^r?ktotI{W!lnz-+2P>4
zC_PU{q)XEMcc9_2^fA>;MOdZFpTG)Tk(LyKL`uJ)TcJ_XA1HElRr)v85JgKns9rTj
znn)4ySgGSDnA0_>10@r$OYMG!F>%tKc(B}%rjj=oFE#yzu>|S!6vs-G<_<#Orqp8q
zty|Li<*+bGy0`_cWU19D3WF(92a0s3N`ItGRGRd~S%68G`n?L6ENPrCrkyRFeGn>g
zq|35EZc8@>V={N7-%&0lSNc~TK<`Q`-vUaWbdYk@`O<?tm{uS)oPef6X)z`Gi=>~(
zA%0KVTaT3~mR`12LPd%6J^EdhO6@5Qd|&EDdEqkYr!&AVmmdBLq(b`o$6$FN{c{>D
zmD2D#K&z7GQOK%Vs;78Ijg+|*3sft;EyCDC=^9GB)k&YTVys?zn0~+w(nWM5w^4ei
z4D)P~4)j{lY?jV^0Ma6LvVnZ7^xXF#ZPI9RA0J8Iqg2pi>8c8lcIof5d3H#v$q(w3
z{__PoyQDvVidMI@+62?^xL*NSuk-}Dq<zxNcC`AXH|g@hfOLr7u!B;+Gq7+-I`<x3
z{1}$*O2jNiq-Q?>+Nd;&eBm+aAGBSLOF87=PDuZDg2bfM%K%MNQkORXIxS77>v%I#
zXDY|EmFaZAwv#2-pmjvnLeJk(*`{rnsJ*O!UMCK+%{X4qIVSsSDadiz*zc4sb(E>-
z5`&YBM|I-PvY!IM>LOc4$7@$v4%KVB$*SK0n!C)FeBcu@K^oM1$Xan&m~&Eg@g<n%
zDGQ*en3qgUB?YHsOe$*emg(tjcv_Y~8FL>Q+XITu$jU467x9&CNCT$TPqy<@NchYA
z?4jwbj57kBb25Y*@!-k4ok0R+o2sEHNH#?u0ScB~r?Y;DY$s*ALS=8dVeGtY_d%ds
zkS(MyI$V@-C_ivXwx<$$FUtxkVH6=-Zwr<yvOVO<M9SFnVQ-XG#-_mPRawg~kcgHg
zhC@Y+%#{x7v9inQnA$a2auLXN*&Irl#L4>TRd++y?F^WB*@kG0CCCc@##o|EPa(RS
zvK0q0c1z|&)pJQQ6D1*&WeZV~FegR!fLy&)*(nN!q{*y{=RkeBEchpo3|a611T$qV
zen88Ty_^LrvSl(A)-p%7a4YoQmc3npu{*MQIymLZ`~*O|D@(D3T%Jr$j%U8i>n;Qe
zWOjGZDwHiCZ?Z_%N0mAEWdG7q7Rxr$-@HU7w{8Sascc6Gn)hX|MS!(TwyPJmmCMR0
z4p1Tc?K;eVAbXbb_LZ_TFF;e3%={C^s%4vdAW$P)M~_Oaj41@lL)iyZ9a1N2rwW03
z+3{`&G{|OCjaQ?rlD==!B<uDDOSA0F->B}iMV3zIf>zmx8S-ti7hi^@k7PgZ#zY^>
z9#giUUDib|Ux#e^S)g^wHqvpXOO`-y|8ChV`kqpcj8FFfdS&}whl)O#_&bn(*%}GR
zfNVLrn1iyXn}ISUdv`v_u<SV<`JW@QGJ3_1%C3I}v@u!01Hg>So;(B7CS)Jog8Zbc
zmFl*qWbRj>X<D{&708S%oAM~Oa=~V_?Bpk&guoH`W4hgRRNl4}#9m&x9K=DsJQ8D$
za#1}LIms=QvUZlY!f~|Dagpo3#h|OaVJ;@>CO>OL%U!;KDppR&|D|8Ihx~IfRGgH*
zb`va~^3MX%@{;dM#n>r%$y`|BEpK)N=xO=-1F+Xe&fS5rGjgYYAmA%^GNRK@{$4UL
z{pD%DfSi@5c4D=y=j3mN0xduu`7C}(f%4r=P#+}ErV~Z5+;I}1A@YxRK_XP%_60!0
z<b!l+G+eHp1-<9xt5m?gAiq=ta#0>|7oeBqSyWJXSzb$rqzL&32hh4A&pre3NO>v!
z$fD%8641J8l^=P4X0-f6JD|nLzofuYti0_EmhGC{kCOS<<*x?dFA^sYrJ&*s`5#n*
z5ig$=0r>>^A5#!Wl-pB^_NLtLWwdU|y~&SDlCL_BR<b<F3pS<5gD4P|Dj%Zve42dE
z2w2kP)|8jfn<3XlLq1bpPrvmnc@@PUvgN)U2<FJ$=`49$ev4wMcjRqUI+ZIwbQ;)q
z<v&vOc%J;z?U-o3-0p3R708d$VYyHqa|7Z<@>%`RbWi@U3QJimfB8JtsYHJ46=*1x
zU$;^X;eENW5AtR5EA&<@mv2}GO%?LYyAXUJ-*F5QmGUmCX{(aIXM@gad21{<Yvegx
zv})zDkI;H3zeQgVsFMqKgVf8@#E@%{SCC84DF5zrEOV2*<pw&N<=U^%YLS-&TA{vG
zZX}<eP3|@iXzlXEufWqGPdW>pPPuCk^mfVbK1Qosez_JbJ#u3M<a*_YHNftZ`;hC^
zFYll{&VW427UF|)R}aVy$rmk0Ygle3=Y2%Jj{Krg`JA~}nKAjmN-7r`moFFv&xHKR
z+vuH?>pg)zC7(}Io0jt(fITB`q4Ho`#jIIiu~Y02V7ZPc%Cu-5RV@7np!SL>+N>QE
z)&D`@m?E0|qT`BZ>8;|ZFnt0{C&g$yh_fO@fH4=veOtON;;J~b08?{Q+#JQAyCSv=
zvpAusF+hcf!s#r~PAbN!^1xHEV;ijSQe;zj`IO>UA>_Ojt`|T~E8brKaUVqkB@NFg
zSkn;jReY8X3;h&jbko6K@ktlN&njHVRXnHoryMP7fFk(~Gy@ec%mz%5;@*B>2P>BN
zz={yXttqGvRj{K06Q)SD#gc|AMwdX~yyC4ej9pNCS%TI@#Tg1OTvDubMeDNSHF`KA
z6r1Qty`spWii1eSW(x2`DI8p&_o`xst{6pI6&t_9V2ol%1F&Nine9-2O%eSI%)hSa
zCcEPlJJrCxq3Hh#67dR~HNZ|#2rEDm6~1#Ja8vO&Wf^ZNK4U^4N%3nZ7B5*bmx9eH
z3JDzwQx#?J03}V)OMXJSBADvpGZfZ&6nM#0DD=S2QfOO&maSOhfkn(ww9s9F+lo&p
z40uP8)(ZJtg^2DC<tz5pp;e$rp{Jry5%D4P7AamdfZS6&;|dkUiZKCLN))+t>!Vch
zl@~DYEB^Ukgi^8LHWZaBg#Y_b9u<nE<UT)8B=exKQeis^m?}kjC_1YZAHM_BY82x`
z0IgNXKETu-D*mL;71b$<7l70&s!Jf(pjf;Wb7@p~{sp~FiX=KmH7i>4AlIT`?uQkv
ziZrU_Xj5ct1oR`tim$8?e5|-O1;KVjST{(ALisi1I~9$=m|B-2o{py7ikf7g^(f}k
zM0*u`DD=>$c<ME%?^hh5B9H+^I_+A6ip6vxc1W?BeqO_h)hi%3qPX`tSVk4!w*z`i
zp{AhvxMHM?J_azM2=V~Wq+*n6j;9n11+b?Tqx8tkDDr5huvN~!hnAi4&;rOGQC5+=
zepH!6p<H`qP$H)0pyZL$b4(dRB@)M#R}aB#N9EhJ-#95hq1S@5@>NQcxF{!nN6S^2
za)`>+-IRYf0nJ@0o(*zB`9(hDJ(Oy9XgaAZr;-Ct<piBHy_BUinN!Mjf#CF3zIX;O
zr<L*ysP|DC$elc+9QXpnS6M<&jGyvP@~-@qhBAnsRsQn{#?C3-B49;;axs-*S_74G
zDr^Z-rnjLPtn8l+6(Pzo+BHL!d+E~}Van#8LBf@C3c;OM2Gh&<f>P`VmW#@{l)bp5
zJWQ|V%gT3sAReJSRfpC!<-OM-a9tVWh;@onuC0TjM5PyHA8sn&rJwpOt1|T`@T4l`
z6y!)#W>9@qy7G(PFqo(OHW+#flm%acrBE3`>4PHW3i@^5Q)bcMr&yU!H^NGkNxNWE
zsqzInO5a!J(Sf8)X`+Byh0^>HI3FnUPGc!6l?`+<u2Mca3YKc6b$<syYm^J`gY}`3
z<qb`B%G#TlQ@!#nEv#rz=F!ooQR#jY3)HMEybOUBWife`t;);JKx<QeD}cZw<+Dd1
z{#f}+6tLTsvSSeFRHoCu+@<`JB2(Q;HQhGpQJ!O>vsXFKdK-54DPN~BYQOS3a;68A
z!v_E}sPs+1*pTw65VVGs=k0+uqFiBtp`%I%K5QCO&hf{Rjw@fF$kwD%C<peG(up#u
z)5>L!z&WGjbppj!)h_^wo$5ylL>yIdvthQq>fM8M5^_+Dk*|16b&q_f<Eoduu4b~V
zyt|mEo9Y1_wcJ%7kbizcwIC7tPO8-7!1PpgrU27R_1P|foKjt<@*{86bUnyvRS_jU
zd{sB7oY+rwnNAn}swn!&omJ)T!`M01PlW&rP<=)3{$N$?P0S%g)uRVXsH)7m1-<80
z9dx_qg6b{0zj{$+a0iJ{dC@<LxS|UB2I?bKuiXY`v`S6IjWMcCbbg9eWl(r5PPOng
zkQ=I?A+W@&-gz0Vo2qZ}F{N9oGWzyHl4^r3z*1FViO`#-`r|EFpROvLpnEhKs-2-w
zn5hz0V=znAMBlHtt#Z7G&O55AShR9goBkJNQ#n%DKTmat>OJ#SA1;6~MXGYT$Z}6r
zO9{GSl^_rbOH_M>P+zKY{sk*@U*$ys+6vWoRH^Vl^;|zlrRt^Y^e+}_RD~}Ctya}i
z4`Uvx=3hmtLG>vE#x$xnQ&^x$HH(t(&8m$_P|>2A-h+v@s`^eteYfh^C3N<v-b)5c
zud0pa(x*C0#hCpnhlLm$P|X&gHK;1N3V|V2oi|#;s<~Ku>zonQn<3yCRVC9dJEm$|
z0iJQy3$!gysB)M<n^YxJczR0p(j2ImR;{4o<QdgL@~Ujr=YGM;+Nt+ZasLr@Gx-%q
z)iYE!YOl7Xo9GVe`{kI+F?HfvbRJiiQM}VpT|};_)k*ES1B1@$P>K_~sOJQt<*MG*
z2=#92M<;;ot{(as<b+y6rxQ>0MM`0MsnxVCpHlNuF&S_52t^J~tBsWy^HIM^NvSjH
z%{!pbSDn%XoBY(bm!Wk|eKsA22B`g4fdpFBiUgP#q~1J=B@I^Zpe%HV+Aj`PgsSr|
z04+@YA(gC!tM{x0=y^4tDp@Y5_k9fci|W|tfPG2rK#$*L^{?lF5}{6|*Jh-8U?~Km
z)K|`eTvhWEAP}v#DFt+lIy?p}vFcaSDPS6>ZlW5a8|v5T2p_Kwr+Ux?b@dWxN>oqN
z@&2Z|no=US)U#K^!X)*JF<$@OW?J3ZSebOS>q?+ysGp+8H&ZPM1j$yf=m5$cwTYsb
zx$2d-0DV{Od<x=u>d0US<f|(Z(JD~yjf6m<Iv^kGTcnQr2xIruf2;v1R#(yswnWV-
zf_SO=Cps73SEp-0%G4!RC(v^BPoHCfD%GD{hcQ*^)#rg$t$sj(#~StJZm6hLztM;Z
z)~k6PXf>$!)7!IAT|SN}HK~gOAl|Gt^+0`#TDBOZRlSn#k+rD@{=nirQvXM1qsQt_
z3cj|hS9YPZL!I;lJ-(glget&vskhRe*{$xfptDcCOax;F)wllVpQ}|AR2)`+pNX*%
zbwwToM%9ADSfDZWfj6LOTz%;)j7_K=X?LAeuL(rwl={8x&@`<+Qh?4GbtSo4M>I3!
zxg6Cz<3VvPd(9;(hj7qj(}l`on%BR>M2~B3Q|Q}KV|N;$PMXzp&~w(TqkYOnvs(#J
zS55T>wA?i7G9d1uk!^#DlNz^R$a!jNsP4i`lld#iDNQk5nDf?*P{8AiruR9_(^u2;
zkRD$@&Fp=cg}-Ke5@=^NV~%K@(|G&|6+xPXkD)hM<M$h^2+>$dpdwUrEe#68G#}9-
zglpdO0_b_oTQ8t>L6c;Jz(q~U+Yq><QHB8QvgSDoV?=2Fdk%8fG*_rV_qryQBFNS_
z&GYmly`g!^9fR?j7mflgL9?7nEfO_BIS{<58O#RDEzPtLb|-1}egu-N$@u^zMe`oL
z*i$vK6KJJrvfIF!uKAXJ2^pHu!vM?FyhWQ=mL}B|8nQJnJE1d26Hc4_?e{gj4<Ua?
z^Y2Dz%GIo*lh0kv2pvN6G;hBLn0(E1bit`WQ_umyLd`FGF|{Ji$PWO$r%5DFpjZ=}
z1X7~e=v9B0WnDlq>IzMp2p|tMAx4-~sd<V*>{Xfv6!x#yd_dO*YBXDxg4AkkzQj^I
z)ci|ZU!7+0H1yPK#>rP`(40O7s~a`%&@H7V&5smAY1TZVUt^2r1<L=lYTlrNk~U4v
zILIT-J}cF0Jl5>WMYCPgM6r|(&GVihof`iiA<?C|M)A>Z%{B>IJsK%RQhPNldK>g<
zsy=|;e$ChekO9pg1&IeW79j+NG^#Ol4r{XM^CTmhz7HWVs+o!b8PnL7fOA~alCm5;
zQ<{C`t50kGUV_QYXr7>h(h=={wD%m<raT6**CzLXIB3tefaRFB*Gr$j)H;72X6CG|
z-;5y_?cj@;uB-OO``~cXO2{&I?P2=L$O)|*`J*1%YH}z~YG2<C0Z(mU4Hnc(`!?+|
zr?lRCFh3vd5=xGr(VlaJ4Zhm0r4aDbrpAENUu!xK4QI7!Q4l|;m0IVbH$eO94)6qO
zW#sS&X;qX$2-e<x1!y7KgFj#_RJ-LFjD=~Rq0~dT_Oc3N=e6IFcX~nlw+x_{wQ2s~
zjL<$w@7ya|AKJbnwa>qaNknO<=_`9zwL6w!646>6eYq`0Teryy^|9Ky|AFV4wt@Wr
z>)Nm)$j52_`5dhq+83o@jn`g#3X71Sy)y*U617QmMc}5kkXG`Rc3Uo5Nm@-gu#>f+
zPs64ZZSe=NH&y$D2UyayPmnW}u6>_wV`XSB-h=g-+RJ$q=gZQ%Z-K&W?RI)u=V*VW
znD%Y$Maoj#(N2B|m|X4c(=h+8R<RB8dD;jsD9qRPQS`1rJ4FZXLhaH{a29Ff$$`G7
zUFe8bvDVKAawS^tcz~5^S3Jg)?rZ;j0Rm;(Z*g?9&MDWv^Az+}Xs2HUd7$l}C}*WM
zgATV<+7Ibt5!Kpv=*L;370(7*t+tV(oDa3O6i2Gl<~9JWUaOx(t3msiJmyAi>Rv2D
zlUBO|%hjyiwGS*U+8tXl?ME;aW<S<`9R>~7cI{78Q{ADxwg}Bmtt)vBU0VDnP&_bN
z13BJ3+WG4s*sHCl>~Ehoft;d#?ULiLcR-uU2lk+LJ8eBf+7_y$8rI%80}DsA>**TR
zs5YbwHjQa_kxxIaZK2&|LR(&k)}&RNHHGGsHmMXm)7ssy0eeQfi*9Y$>I_sPW2a*u
z!z_;IyhG7>R5$t-6x!>`kD=wDJ5vF(kLkjrfpT2;A%)u=bv9#ILnmENJ=8nv3}=Dj
zq6_&D#8t;uV@htib<2V2uCrE{A%8-*ht5eJI-ef_b5fUU!DKvjv*`|;m(CK4&QrRm
zJ!pCBUZZT?X`R;`$oc3#-UJnAbctk|ug;fZ|9-j)E1=$A=M;?2v%0UN0ew#AOyxoW
zx&s*?fx4}`p*~2r)|v)`gLQxW1QMdFr0jF3PWCJ$&g*)}ZM&db^#>#_>i&)Z_9b1*
zX0$Hrp5%fhLiZx2yRPUqz5&ii-Kh;|Md@73K)I^h91PBAT|K2kVswXIhd`{(?G8Gx
z>E==x_qr}PojlSw-Mm#;(i^&fPcay;E8}7I2|9<p7)#Xcp=ke2or+fWmhNdfE+y%b
z=q_in?$tcVrRW9@L2s&VQ8K2TrW5Hw(sjO`;LOlnqTF|;?g}|fS-KHg(QKU|1)Vv%
zjhz(dyR8eQ)c+mb$@if!S9hGkLU(mT^dYW19fM+2`8w7XkOEx*ZQzBvcbE_;(tY$D
zTK9BSMwnKt`zaT#5}n&d=q=S1Q5yBWPQXWJneMCkAmzGFiYQd*%3~q$Kqo_;o^?*8
zZV#1JR_ShZfK=<Y({HCncjyFE)arJ<hP8O8dp!lDPIn*@Yf-P;Nt;1~&hHaUrdc<S
z-f%5CxjR&}>fUXI-ZtGRmA*XE{b&Z~W8J$Rm`l5E@h)(7=;l5E>C`>hhb6Ig>9$e!
zs$2Inonw1+i>S1sSGS)|41Kx}hhb^I?x}4+8_=ogIU3Y`NXM5U-D8Ro4eOTC4l$xL
z+kuSg_E4?On9l1nka69EH9(or?L3awr0z#8Sf+GN3xG1M`wvmhIWtyW9{EqUdb0p3
z?DW?kL;Vqb*Hf6<QN8z82-@p?R)9F@Reyo=nBGEn8;<LTsG8JK9~%TYC;emq#+>zQ
zyddYIe<lK*uKIULy_^1>GKjnDpV$Y16MA+Art6_k_y_7w>aCBj!6;9C61~#B^iNSO
z`6>OT=Yi&}cQQiLX}#+{p!w(>pGD^xz0Lu|SO4W(kn_`T@qoSl`qs@rJF9<0JJUJ+
z6I6*3pl@3O%s~A`7CJ-p?^XdNRR22J8>W9@5QbjRPgu$4zNr6?s&6mpm0}otMXxqs
zfg|-jb08R{_c#iPc>Q<(`wwFJ|0wa9s6RzvyPJCN0%*FWKln7zlJtMmK_^+ig<iNR
z`kJ>Po~qwPDdjYM=NI5i*ALBsq6~fJ`#{Omf1N?ew=Df2?Tp#_d~(fl^sm#I=(c{x
z0ho429~=XgTs`Ayu-w(ZAp=aFel-QU^Yx#71c3s*{YOw(s6V0wOObxl1Um2Ow=aNP
zv0g~A`x5;Vomi(*{T-@HxvxKZ6s<D-)&;ZVcr5hGqS36-*HY!q1AX`fNL1=ylVMI(
z`sWV;v|4}6tNK36`Wyv4>h(Ev^|e87Pv^o$z4Qn;n)FL39nq|xq>rt%=$D>?ovr$S
z0zkIu6(JaVq)#UA__02K(l71$ZysTO9s1Znv^w?gQ+&KjuX2Nd-TGPH5bx2mnqf+>
z{&5~!efrr}ijei|zy1=e1NxuI1s&ACe-79~dOiI?hxN}t4YU#cFIS*xRR6_GXpQMN
zP!-;|e)$m?GokO>4>GOyq^QA+e$o!uwgzz-IPDDP8m#0IgTx1ljv8{P$ll)IKMgPk
z!`U@fNE|cNd;`|whJ-a>bu?7QV9?31obo-+hWS^4=3;PdgF;ustMM3fGi;|+l)K?u
zI?J3e940rx!|>N`h@Uk4P9bzpgUAI_@-pPVMn8YU({|wWHk_l=@M*)dl%w}C$PdoJ
zX6a|hq<4hBVRRhWXAKrA12|_m7z&sG!`D=`6lk#d8!SPFG6`6M4XCKc@858nGJm0l
zRUbeg%<yg)3=KE5P&)p+;gmOwxnOv29mqw)g-{4wGO%j^cG<9xq74xSZ#)y$Iadr}
zuLCC1ApH>7Q3e$`l~)Z?0nCp!*e-=cjN$V*v|<g<Q$gf4!(b|mxo&vlc}zRbaJK-h
z8-|?kAQx|#O*O0u1{~J#Oc{240&>$ZLpifs2KK8kG|8}yPNm5P%{0WVDTX_v=uI^=
z-a&7gVLhFS(+%}6Vlcz-Wjsix;l<wpnq~0Vf>~r6R%ZY$$1u4JdT$%1XYhx;WAINy
zE7$OQE5_~`=5?Z#XZUwD!14{Js3xz#u#H|Sg$6x+<e|v$0(}tZp4IT14OXbw@R}Yo
zEHRAFffc2On!S*}ZwS;tVVPkAWzNeDeq5kc7<O+&=L3Ti{e3D8uhEuWWq6k|mDPq_
zk04iLkkPxP)-aR-O%Dx$6booDxX}&pMnmc)=xZ`Km1Abj2J18(YFZ3yieX!;Vd6^+
zwi#xv1k58tg#z-A4GC1r(Qep6W#b)&|H2^9Y1lafo4O1O>95soD5L~@k71Mw=6Vgn
zry$;EU{ai~-!MQ0ECU9I2T(X@cz6+DLxx{xLEo@JZ{3035yK+d9>)!}YRFF*O6lA)
zX~<{*%#`7PD_Exuzji|XjG=?#6t>3577#n5ItVI`7#k^1bkz7Ec`5eB{27cn7<W<H
z=a}&T#V3v%edy=mXiTI$k&|&d1%RB5Z*8-J$Hi#*0X(k8Sr?$f&FJ(g(A<q*(9!IK
zv2YM99!4oe8&4X`=<bTAv2ZQy^)l`!KlzkV`ZQYJ##NMbK5d+J9|Atc1lr2Z7%x-)
z!q+%LH=+EDg%myZH{P?Lb=LS)C^;+VjC07R4KSt>2{d-mTQtbH{xDj>#_Q3*4l(Y(
zht5#r-0!g#VaEHrpf}uDw+v|KjoUe}{(^B0J#iO}JSvH}WOTd(^_Pu4xgZh7>b+Rz
zE5><mq7`XOUjpbT<BB@^r(su(uaYYsZ5)gMPmHmgs=s56tB0{r*Nh7CD6Sg^=~;<0
zx`o4-8^&Ffzlb*$jX-^ZF_t{VL?f4r)=lH)b&$Jdlu!XnlF=ax3X_eWpTJm((f0&8
z(~W6MAf92&po5P!)0pxs<g<)P&wwY}xQ3GZImT|fe0$qiLkIsmMrW!@%QY^inCV^P
z)5k&bjOVCaBH#GjPN*m_jvfX}p>gLcXcZaxv<uubzVbR$6dPyW!6ZtIA>=fa8XM@v
zeBWqZ3(hjD@dkNr<;ML@AQi?2HD>t0c#6W$l}0g@SydU&m?2SZjG=r_jj@OJ{90pr
z0>&O156Gdn&S*m(dA$+;4jYe}@#ZWDG#Xp(!ontF7{%9{jl1Y<)nc6O0@7-Hp&D{+
z#(4}nCO<O%?$ukp)Y?0S&Q9Zga-6!1$~us4qsKLX^%!se4tslzue*Ts8MDO@>o<PB
z9?LXftfXsxgT~O80X<|~m<YLH<Lh%kMvU8!Vr<m-9yz^ZMk&2b#*NkEn8Sq8je@e1
z#wg0zO&QJB9t=(!50D!+V|?)mNZ6VV(;w8%<VxGr5!1$-kT_~ONX3fwrYL$e9Zc)(
zpvlp6Mu$!((`>qi<81n}3}Y^)?MJZ&uBO8jS9ddg^EF!TrhF<QIAQws4&*#c9+Vk5
zX&QOe3JFis3Ilq*Og))c(Nm^bzL>qY=_4xaJ#9KqQ2`&*!FG@{rY9)4>T6m+JA<F8
zp7t((Q_5C!o;AJi3x(%Q9rJ)4V0uOgn*vSx|CKYFW_=EUV3UeU@j^_30@xI4dL^7H
zRKrXI-=i6B+Dhd@=S?}85WHY2rRe5GQ-mArzGUj7vCF37B#cFv)=^E|71MKcAu-Yv
za}{eDWjaJYz*W<hX2?aGCg@ESV_Nqg#$rwTQqa0)S~w25>!wk1q2o;UsKCIdkxjz2
zfQdIrsaP?=)bb7_5=~C@MTDCs&KSmSndYp)SdwWn8|EjQ+`KWCVsdQ;TB<3JP6uhG
z##f*|-LydumJCxEU7*Y~eNh3HEYlY}2xOa-?_w@FCQA<lZkyiNh`Ctrn8M;Ak!uQa
z2G3nn7!?ZSnF=GolW*FjN2|zGqJqKqOhvI^DK^y&p;cnKun;VzrUr5|?wbz149+qW
zp8~h#CdoQXqQZ2MzCiiFw4PjnO4D-6-&L8Ijc8SyS_ffFjn(wVd^BrKPsRc5q3N^r
z;Hfj6{t__trnOlZYcTyw&uydW>nAX$CescIYc`u6KLmD*DR2=qwVFm9Al_!OQWoWr
z>EI0*^VnpiC}X?n{nN0w!*u^|2y~jBrZS~2lYw%#-6pFOg&TWJk5-|#*Ho&5e4j~`
zkHLP^Zxp^8FkPm-Z_sprVyr`^YZqbKuxT^xeIup;3R{nwzI2D&m}%WxXpNg5)IrmP
z>BncGe$sUGc?e9Iej!(2+O%{5S~Di424>ruJ*?e;u`}P=kLD4x5B)xln%}Acu{URY
z4}}iqk7@Cbnb)m{701m#(p%8cyos*&I+_2Z>&(t(P6k>o=Hb_%-qkFndMY=wj=W!Y
zv(60)Pnc(a2}}?3wnHE%&4=jnxTpE?vsMUtnP*L4_596Q6pc7*u3QaG=gb8i&=g><
zrf5^3+2u!c2ANGVumqbY|G<1h%<HQm7iun|<5QUVt1^s*o4@tO*hRDXDTrS(ms`Mc
z+5DLs^hTJ!X$I#Nv+b`Sk>(f1DRLHNetRb@y=p#BxsGUa+><ak#{9z?kXUo&N`PK7
zPgCc0b3C~MapsrFr@dirqF;Bs`J)R^kzh`t;7y{r*dDE$=Ful1cgrly0B4dpjFN+?
z=9k(*(##quW}R*p>nU=UVHTZ0Gt=A>1J*3_A9Q^q+dLuwOpf^niYwhVM^VD%j#>UZ
zI&;k-&tvuOn&(l9CC~gL9eDE1jcI5Vn6omVqR^Zdg}*_O*+Ml__ssJtfL3f4u7Y@p
zxyy{sQnPX`SghsdAIU?mFfZQ*o(JY1U&Uah`8f)IRGCdwu25~>M&YR%bMSJITJt`-
z?)1={Oc{?lvyTpoS8rZyf?R{S<N-*dIcE>Rn#|2~_oUf8Ll0hyd4mq5)vT|_Jlo8h
zeWCWzeDhCK#q-!aYpIuA;}YwW+tJ%)E|h_%+x*<KFtNw%M8$u-W{(+Y>NEdv1uXsM
zji|4fGhlvpA36ukTk3!^Wd4s%vcu-w7odK`{3jPnIc|1Hgx(4Bs29kjdEW!rG-Xy^
zMr+!<m5)`MF@N_NT6Pvs>ywZ;VtFwgy+<wGJ<w}!ai%}BgXPtS(0k1CY$;mDE$@gi
zdq<0zLZVKV_&VrywrJ^)?qZ4R2aBs^`%+lpW?4W-9d}DJy;DzEo{58ihh@$;&~VZc
zL*XG$%RzF5y)2^l$X`BX@u#<hx8=QT^q#h`CZX5IQcmUlXDor)u+Z1?3dIfmEE}kt
z(%<ra4nWUZwvGezoMmneGzC~@bAS?P*_(w{kVQb{vcVSJ6-+6_5=%eePz&z>T49#I
z$WaZq{QU}@&CXlKo&o3u%N9p0=|#(yIB1HnockQcT(PuM$ycPMtObTfSsW-Lbk#CJ
zr4Z4UDjR5uu?*2!C)UzHk=Sb%r#x_8w=ANQTAZbrHm@5NaU+b0x1>?JHNo;9{Ynxo
z1HaIPrF4ru{qy7uOBC%znU?$HWMx_A(%p(|%i({aFvqgm8}fH7e{IBkb1f?<KX%vB
zPiKZa%Vt-w<Xi540hU6`XeLmKEOQQF?4IRr8aj(DJ5~U!#1eHKitbxZQD&*kvVwL?
zYq@0}6_Qj~0{$09u(0U&SZRr>ghZ9)^*HcUTT1=`OO2(V5bA3!HY+fThnABv=&iGS
zd>%8bw;ZIjUV~-zVz4w?4m`lhG+9dd5O21;Lti~<vE+P@rEIm7Q0Z@*#X#QNBdg`)
z`=F04BRYV#TUbNj>98!B55Z2$AU*e8mZ==5@3z=(M`w>^?s>F&E%FhNJ`1-T0{s@w
zDySc@yj=vF1})pk>>*1XIS9iR2KhB3mQn0JbH**>bmMx$67U=JO<EStYJ&PH%kM4d
zowiuK*sTg{@)B?!Usg)R8jj06IDmFqRz{2NysUx(g)Ym)QDAXf7Dq`3_hmlu;5@PH
zXNtRdEc?6@ohO%tZUUs|vX?2@;k8Ug?$oJeyIuhCUbd8i!>5-WdI54i%f5^Q%b8{K
z=+NrB%((wLdi|D-k`L{_tmqS<{U1ly9hY_0#Wf?dVOeRWnQ3Ziw)NS2@7>U>w9Kq5
z&9`BeJ`7P%L1oC^LqHUfDJV+>*&qnAK~Mw{1VI!L-tUQj&ga~FzUQ2KpWnFmoO6E!
zGj3C1L<r;AwIHDk1>JCAjPL2O9?tk+D?}m~>7(!|l5w>VToj}I7Px3eXdw*7Fr?uy
z7|WPh4RV5^kV7PnvBUelo`v>95%>X5F%D5G^fco+3V0<kvSxuh!+4tqJ1Gp`P+SeE
zj04_qERDgZU}ZYv8huwSgRz`qyP1s3l(EiYd`;_!Y{s7VLC!OVXF>7;;~v$G<S>4w
z09zhoaWioFjL#yVvw#t7r(<Xr857wUN+DxU24spDu3m7ym~k-?&Rk~P`wb!`j8EnQ
zSjs564#_fxjIv$jjQD?Gse<t}l?YcdoT==%it)t*cwf!%+X@pkjIWj8t}x~&09VV{
z@hnu=G1#<zxyl&tqf}NsqdWjZYhX-U48%3Y16Rm2GG3u@Y!f4ye)49<fkE`OFdopN
zx0SJkE|@lkkP=(%j7xNXcQ9U}Bts{oc00K1j75R)zKijCD&XCWXbM%`V6b;$o^CQ6
zB4M_N;mM=Vs@!5MS_9Eu#-9wd_A?qfVd)NI9+eOcFd8R;7-W<?K<Qn^<`obbV&EUQ
z;Cg2qpAXy!<M7*P9A!kl1nxd#-s|vUjPYhXa1R;Yl(iaXOrui2M+`H?BPSU1sE+S3
zLxfbm-C>I1MH?(f=6q+^bz-Kx3(lFD8x6b*v;P-(v5)x?ttVWWizz*@pUIsAZ3mbM
zRJ-HG<WT0%ow;Qg+(G8GdT@uB*LGk=4>O;m3(tf33mszhWU45<e}q{v4~<8e8d?C@
zk1^-2h6yj`&y-#CW(J0$(}(Fu0exTQYO0Vt&dj1fwI8!=0&4u34=D{3z;qJ9-#})<
zDC`C?fBvryp7{^ehJ-LT(H<_8`Oh495ysrP4!Cfp7k#oVf_e2i3`H^nDWn%;XZ|?~
zH)5HOY43P~8BYP{IA-w2z{fKmUWBCtW;t!&Pcl2?K%8Q3`~s4vne&s-n8bWJA6}ec
zy3h+MnW<iZ#<R?L3U;P2SE0n&A&r?wx#o0c-D#N5V7^3!aGA`l10d&^_STcIl*JTL
zabY%7KzHwX=KH%brVGrjW8iX_ddl<XGGA)|BA@w631+5%c`p#$MdofwffX_<FTn04
zCWj(}Ma=Vbc@#76JOwXGm}v~CE@ch{L8OeiaXH}S%<twxX9ZJY_lJo}=4`4OsA4*k
zi#5!5=;yk^%v=jKwam_oK-4k!T}R(lrbiR{>X}nXz%?+pZU<>(e(Da=#H^-maWk`<
zO6*&hno8JhWp2KR#t!B?v<mBFUUY@B>&#!~U}n0Q5x;up-gdCNQdPwbraL{UZ!%kH
zFLjIg6(wkUnX9(JULW%??N@Fyy=cGF&z#u=U+yq}r9zbf=B%GV?lLpzQ2r3}&n|d9
z%-pa5fO|~iLBL0tb-TcgGNas}`aW~jL1-CcmQbqi0dtLg1K5Ym89wl7oayl!5EINl
zRzl5VX0|{4on&ro!vLq4`+tH7M^@ByG&-@iQ@GBVwUGzOeXO5#(B{hea0B4`Ss(ll
zfCH>1+QqxEPW=eg?yT%M;104}yI}7yE97->9<1mGv?=gp<<n7wBP@FaT92~!(<b#8
zYuX+Fy;yuPh!1Pcm+13lh5iA+aaJnraQs+%-Ujh!-B}H#L97=kC>6|lo~mL)Sl_0A
z3uXO&6I>YU)r;^xoR$1MrYnN=8SQwZSnvK$--wB3`D}zt3~S>Fw8pZ&m<!+u)=dhj
z$FW*z^zp3l<*<8_r9BLhMAmRV8c(s7okZhlmLmnxl2~i$-Fb%P9)Z4ORv2yJ&azI>
znl**BjPBl4R)Ps5OJi-Mn<9g?bNVzqgECotlp;CD+C3ek$YQZ+i;&GKk>Te$&w7~(
zIWDli>Vrrwt9TsvJXVw#lKHG4iV+pCMD&Wf$og>wxI&g>FGMb}t`>n5vu0BE^fIfJ
zVm&3SZL~uvWhMQEzA{$N7x>Za<*bby$W*Z6T|uf?{yyleW~F}((Hd4uF~}9xmV7kU
zvZ8*(%+#}XNHM|&)`dlI?HX$lCD0pL8(RTyVvRVXv6(gZDTuVNj_e0%V|||q($4yk
zCa8nu)&YMzS?`!&{<@vDj9wXCteJe^yIDtu(0P-^p<;p_);;<R#x2%|Lv%Z^7CnaU
zJ{GeT25+-&QZBWhHAW%CJ1n2qFkJ(za!OVYvN|YUaF=zCvN6M~kLVe4kL7wEA|tE|
zd*Q_>YuEzS_gVHmlzbXvv8gKR0qf+;K#a2r=3t<YSWVL*I>GvO8$=(oaz2CZN!C|Q
z=$m3a_db3RNA}8pK%Cj>v?p<4FQvfVKK7Y55LfmRdbjLnPtb$-06TL4I5+l!HIO{W
z_Fs&?L+oJtBA7VLuBG}S54KYXWIWloXpel1{hAHLi~T(1>b%*)Ux4soFPI5`ec29A
z!{6g<Cwv6j!H><Ug@*xb-8pc9?6>Jz9mL*Uf?)@<4bPx4guQ_B38Cx`T8xFUqYGd!
zf{o8cpf!^1y%TH{d)M>uEt;*{1}|dRK2%U0%NF@yFeljJPth00jyeev&o<IiD}nvY
zM!-+9eW@D$6#Io$n4r__?rz|c*!$@u!WnilZMc)!Z*D=~S#}xi+f&#lb73KkT~|u?
zUpo6ss!_~fZ>og0O!mv`;P*N9(kY0ZXZybb;05+_x@L3OvjYLlWxEo|V}DEg*nGAx
zd04=%-iO9Q_QzCUbcy|(Be){ADFx<>*;6r4cA0JZ7V}iXj&X&(Qg+NE`hQ{N><{Rr
zR>4+M?P(?Z?BC$3*f|2|u4a2Wps|L1los$;*fur1sAV6cbb1|INm1yl>{+z0tY^Rb
z5Z+&7U!{dmBYV@kFyF*x8`0RzUP5K}E$l2R5@}`I55k!?_T??;vv;uNVG!+PZ@mk0
zo&9(Wmb%!>7eRM7ySETBJ?y;CF{WGW=R?rg%U)Xyd>{KSTG8HS|4Y$_ezrmjkvr@~
z6ull~UoHiAmu*`GGQ^g&LiI5F(63N-kNwN5&@#e)tO0z~&i<Toeq-#F^vZd_-cSy0
z583l7Fzj(QKN7R|h`pLZP7`d`8Vvg}dmhCpCfV~T_cp~&X$H=bW2DQ{iL+S<oC_zm
z58OV^M~?w;<qS{;Za*iF-j@eB9d6L+#`*9RMBF*{eH4y5#QA9rWDaxcW1-E1Gk-N?
zJUKIH<8g!&_6tP3IQ1vMd2^;y4X6+2-+LISFQ;%0OdRK=Suq$tPU7<zi$5p$4lD(7
zJm<mDAWlRNaKW6vUj!h8(?=21P>zj0HWbDwvp)bE&iRE_8<CtBe+MFp6EzM*G{>Lb
zv@x6tDvFHdtXc~E3C`^EuoTCMrKNa0=hZp@5;%j;qwyri=LL{Nj+G*Nr#bJY0g%Lb
z^avKta11&~CUYif{dbmghDx|oI8kRQou10+rKNZ}r~5n1Ne1WXPLNE_Z&ZA7j`Izb
z%4czs=qY`H^AiO)ayVfW+s@^Ty@K)PaSRmd%ID0j1S#NT`~;mBIp3_pkP10Yv~#`0
z@k~HtF=x*#h+O78O_}}@&S`I2gO_sr-h)gT=Qb0%D>zXUcdO*AF<|snoHEp$IMi?s
z(QE$-r$K?asO8L}pl2QDJUvmbV!R;roMV)+Z{RGWU2!94hdW3UXL>DEH*?;j<6kYD
z##U%)<#>$%(8l>yMr-hP&OACB-O1TL1G=ws%J)I0i!+i6L^o&A3|P9s$!La8H#yqX
z@UWM2f=+Dpam*5s+Z<UdaQ&RxRgk>HSx-040B6zy$w5xQAe7zZd`K(BA<h6jQ15Zx
z7ed(x=SjM^?4z8BSjgPxoT41s7)P25H4izP9)TO@2&hcs5$A<FXnf2WJ`MaN=S#W}
zr#KDt;U`CKJ5@b6ai6B60nXf@L2xcy7s@iYa*HlOaz8hT;-Uw*FFp-`8+QfOe7JMF
zE<xErJ9o}u%+Mij1U<q%xc|r@>d6g@LFW-}1zjFTxk>cUKE|C*DHkv9Yp+6$FE@rB
z-N(7-zrjHLxQljz^XIOmHDUl)LXprw?t5pz1#v&2I72XZMi!h2;a2$o9>!g95MG3H
zKX!WqYy{VhRwj|$f9b&-#f>e-<i~J-pjdA#w`?=KIKf>>$<27~nD-|9a~3OQvQBfI
z*$_<PuHXZm%>C;x$e-o@M0ZLGH<r#lrgAxSPo{BOo`Wyx-1seM%-}vcgDc=1x0<$Q
zS=^uL>yX*p>5VXOp6fyH_Y2%4CK_|N2PrF;&%HuH^8)UlR{+1r<<Db)E#yYheRGNX
zR~|?a_qiF~bH-k_uXrDbQtlgc{;-VO*bhWGw=x&Qt>FGabq<x>r|FDG75B#gaMj!^
z6yC4lZf%6!E8JWSNG;buN2%+$bul1Uxu#3da*gXtJHkfppXXt(iQBymlFeKbRlBxu
ztD@jiD>rL4?L*qQUrqzt&TaQj9(%=}I2(X2ZUGO5y16&f(RG7+oua8Xxv%Bois|8w
zP=@{%_l0d3buV{I4n+F64zxGF&22CP-p@Trm-Zlc168u#<u-+Z8{)2`&qxe&-Ka$C
z9``uK+()=u-i5oPT=^>Kyw6=_{{u?LxYud*_<%c3so#g(7)k_>b3^HiNsqWsJx1dM
z_bFOZKISTPkeuZ1-34xnTeuBs9C?H9K&cb&!&|^P^Hd|?TzK&t(YK$MN(+|*yx^tq
z*NvwW0q)LQ?E%#Xd2+EG^boI`*4~GCOfu-fYpMeA<f-0*i6cBmy3&sF${wN7i|0H6
zXS{i>6yf#ZO&<Zym)E%gmX7l_)0@eUSMLep&kNiLO98xaTDS!A-gSW&LA<g+^ab+{
z%>@bNZ496^co=Ur?Rmp_A5h>af_IkoRFS;>RB;l;n_Gj%XkKR+?8fkPR5cLG%cA7Z
z3Eo&M`r>%sZv;u;@z=qNle`aTZIsCCsex;!csoq6bei|UlORdFlvH?ehPR#;@X5SV
z<htw*XL;}Tpf!cZUx?OJ-h8^AGI)Q|LNSxK_jOFdIo`U>a3+hFNom?_9_r6<H}F=?
zMB@cs1(k2*@M@NT<nq3u502&Wp5p?S&--)&k{5a2zr*c9o|g)Zmw3NZ=B$WUMQ3E~
z#k}NRATIN|7J-!Tr2oS}OL@Pq2BM6YK&kz5p7R;>Rq+1Z4}2AG@dFI4nzwNq8f$oS
z=@7~l-rREFYIzC{4A$`s^s$nwJbfwv^}N}Xer(`vZ-LHhydS@YNF%SDRxHhSo=+8M
z3(vV5qOH7Yx&qsHWkulHd7tkA>EM0H1hA9$jTVyEc|ZONyIs6qDw68v)zj<l1}}&r
zrMGz33NWT#p6Chm_3>OEf!yY8p-gu_?}fP_cX-|d@OOas2mPy)LEa~G<AAu!`;1~u
zL%jC4pnI4%o7SQuytfxXW|SwbfW!BBzlvdEjQ8wW@82H1Y<F{mYma#EzYO>UFCYn)
z9`jaHfOwKOcN2&spGU<`PW)*<K+>827JYHvg<nlIOZ)gYn!vg8djmlB^W(2T^#T6h
zUI4i9pQ2rxJKy^Qs6NR5@GL|Q^WUVst_T0!A{g@IZ?e-_ha-G*A`nOUv*`*v#*d?W
z+lybEgt2(@z5m-4@JppY`0{_Dgw%1q@;#^t;6LL9E|CApEDSJ+|D6)%gZZ`tAR+v<
zl=}(g2hD-oVf_2_1`g*}oq~l3{xW*NMDl-R+A%><eEma+#_<25Elw<dDb+lk;9sG%
zWgP$PdYFjkFQmjl0)K=8UnlwTLvSXM|J5V_r}$5O19F=G=RDw&_&N02N#=WB0e6-^
zjmmsd_zm>gm{k6@0N73AcTlNDI{(RHx^FZ1S7yR|Ccj>UVV~po#Y1-%zx7kdWb<!!
zK+OgIdm7+#_^(r3CYK*US@Ar6Dy?Mm`TJ=Q1^j2I3i2ZVg$9@?<ZnCza*2OoJ8(t(
z<8=2I^Ov)sx|E+tOXo8FtS(AXl=EMuU3mq+ly3M+eiFTRs`%@7z?o`(CM_3h`09A5
zxx&x>7x-HKpbUUI{+)hE*7HAg#t0ku5o^(RjeqDYbT{%>{{oRF{>nd~vzfml7?Lgg
zt!B(<D}N^KK->6BNtwN!e}W$29enRJ$Xw^!TR^(_FE#_%&EJ0+eK+`3rvbdl|AXH7
zJ^X@xG~VKW5)4bd{PC|K*~br}nA&ZA;w1X|`98Zr2KW!@4Cf$Uw+5E(@{jvr5JP;g
z3b;1RU+D~T&(81u5=uw-kFwy@D8Hy1qWAej>wzERZ`cpS1O7V{DSO24+mF5p{-#cN
z_?YiW5%NiX2F1;$__u>W90fPNgFz?31bOHz7>EIJ5&W?i@O^?*AHZD&#?LUL2L%5c
z25}QCyGH9wcfmutMGp!z&JaB$7@)6K9Tps=1gnSO8}B7kuh@-cP<Bi(NzYtwK^7fK
z@)2A$L#MA`MmhwK3ykGx^b-VcfrI{nBTs<~5QLI}KtX0aa6tlo4`wS^kiH29LImZ(
z7<-uD5>*t03kt;GA_R#-aFK$<BydrJX$`OtEoih;)mx0fj}kkvg7fs0J0VET!64!U
z!xTJ^7i^%HQlcP@g4m}7F0?5>EhwZAev-g=3tpTN?4yNYvS2%HvCj(ryarr~;3o=r
zr3yYt0GB4nqvdqEU@g5oGX-zZe&L)Tr-YV*Spo&t(+=4J4b^#`7o4Q`<psgxGT6-#
z+!LZNS8#$tf_VbYBDj_>7^3$_fgqK3D1`!TAh=6{7OHJ85?pu{q*#zo$-K*gH|ddC
zB1p>xyj1XA0N`bU;qO4o1&6m%F0n$udKF`;6u4c6`D(#Cv*2)zKp=pcD}qCmNT?O`
zQO=-FaPTaYUKO-RK<Wi+wNTR_aNGyo*90EH;2H%#x51ev!8R!Xt%BY$c-SUrrxj(p
z;G3VI`nq854)k>iJl>+i_uYaYXfFE&Q*_ehj-agqWI&KYXO9L2b_#pn6+CYS84`@p
zBVkzZT_Q}}6WpO{w-G_T5+fWHTyw-A?hA%?fg2O-nhTK!g7$f6d?<MJ3rLO&R{jR~
zBf(GfW}OgZ(Id?MSg@LMf|COGuR*2+PK)4-qj1}=KsX7be}Rm%u(t?9a}jz`x#vFN
z`*Sf~SK$woE88!u=3+1hgg5^OgKomsf1$-)xQq#MP<VtgUx$R{Z(-Pnh3lwD+(Q`e
z11+AyuPC*5#4eQ46YZ$*0sYT}W5UxhX!Q~%_<{2l?)(&eKEjnh1Me$LosYibLer<1
zd_Up5B&hKh9;NhZfN+EX5-1eX&m1I-q(@({@OBEcgb26LLn~CMqf)^zp%=Zo!-dy|
zAsHdGzePWKq)^rXrBOodJ5U-e6nz3jj4(VD_*h}|W{92;+V4XoPB=UtQxY$9dIuyy
zc%Gu)Cxx$3Xf9E>jk5QrgqvD0GpB`19N~77aEe}(XN0`PXiOG<vl8~s3eT`1nIg2?
z=`oioOr~=)X~G{UOOP()m!dO67*ETSOrebO{O5!@v~<rBZu<d%Y~iL~(U>EQV8YQ{
z;j^^!%oFxMf;0I-B~=X+2y@Rs<f1T)s*DPSUX)Y6BuvahUy-o=J@`~COuA_Yds*l{
z3`-@#gH)PUD$J)MfHL7{w9GCSPAvq!Ldc=Bew9L>Uje8ReoyPwYM~SD>uQ7vbpKru
z7VyznD{PH|?mFRq%BEZu-v1h2)C+mj0dEj)zKO<b!mkq1*eJ}BQWUL8c%}_%nuP<u
z!^IXMXAE{*h2MV)rENl=G$7iAB`kQ+A<S%nnoePD2TWWSn*Il_OXxt~gy<Ijkp{pG
z;V!y7ZVE+G^z{gjM}fN~Oy3MGy~1uPedrVNi!jdH!loXIqV)@%skY>fFiH+J1Hxr=
zHx3FnP%i1N@cSJ2G$fR@0XQsV&{yv7316k0@rbbc5=2IYOPgT#zVPT@@Ni7Hxd9>%
zgs)I!;i0fq3XySPd?ETC3AfF}uqT8n3J^RNy2rx{`=szsDj%B?E_($^9YqZhKsbpO
z(Zj%5w3l+5E~3aa=-Vgy;!P-Z744*r{(jMxUm$Wo^rsVCa}(`*1)RI+l>~4HMPFFJ
z9TL5w134_}pkf6N(Z8N>^r-0V>#%T4)HaDmFS}?X9U$=*t*7b^AJNH|fbbRVmO;&N
z(cL4E@e}>K0Gz+*pZ}^lL__or4-^g1Vlqgyj}~>oqTN(-8zNdq_kE~n7p0WKL~E#e
zCR}uj)^8D_#y2qfNKxB$^hJr>D2N^{vVTI6i5Ss1#rtAK^EQE;5E*CT5{MHuP_;w6
z$nqmZ6GYFv2=`BlBDLsC6cthZ$0<?iL5Q3dg`NkOBwA?&{ER4$j*=#eetH_J&x+D%
zKae6C*bXjL)J0qTG|@t;Hcc0`+iCrmAsQp6GDW*6=6X(45CoYlQS>wD%N8x75{C1l
zV2Z3?5Ka8IViPF`!R3l({|+?;BCkjQE{ZybF&BlRzf_o+OQM<dgeVfZY=!D#QNu|{
zUKYJTJIWH#3VOqqit61di&Q4MO65M~A{C`fDnyq<AX+KfU5_cP5}D0ttVX60+G<2C
zbAhiD9hQPz73EXHr(RUchNBIlqZG2eCaR@adZXwx1rwS?ezYrT7JY^?N{1HF2qmam
zMZ2l!r%kknK?~J((KP%ybcj~3gG{IB(`_(+T@>^*8oNYhI*8aU+D##&8=`ONBEKoB
zq|+fiq9?urxg{!D3TJvnMk-nC6Fq(gc5jR3HG}kv3<kjOh+cac9uA0fHrO2$je4T*
zuILp3ef()iwB;;DF)R|&Z*WhvheAIiqS81tj*8x*1@?W>Nva<i6V<MTPY*;}_~0Ij
zj?#(WagjqGe&0tTUkVUTh^9Q?=ws2sTnuzlbl@|HOo^h7!Zk<nx?NE1Bp$v6NoVox
z*Wr`hMSQClh<)NAdL6oo{pm8<FJ_U$2gJ`)j>S#<<YpLj7k^Gkl7r$6f5D4G;`!U*
z;bF141aJ@Woue3<r+D78fFBW`q6(y=Vv7#snD|IG`n<$TDZl0|UZaFEAMu$d;hL{q
z{L@Nw9vAO8j8;GKDthDji_g(2D?nUd4@-gK(CrWn5^JA<`C#!!TR}p^!2=Kp6%V#R
zX_#2}1}ue(^GZP?#0%&Z8!3LCYT2U1Z+;7Ste8y?gA?KxGGQoAY@!<=UTl9e8Usxb
zFJz+iq&Vy$oJkb7rozN2@#i9Nr^Q_tA(AAv=c4h9*xd>)S)8&2O3#Xi3{aCI9;L4W
zrHZE=ftED!%t~<S;??x*%@D`azAaO%rXB4$@lgi=vcx;rLrb=}-%g3S^WrcnnZF<|
zJBijD@$wfSnk(+*gUb`!J;3FQ|8T`X3&bKnkc;A+KcTx&>=^`Ym&8F7Z7dQO{f#Lp
z7Jso0eV4_)6f`Ok7jJ-tQt{^bP*x_sSP!mTJe&=#LahGp<D-@0mm4t8RbqWMv{j2G
z2{2J3zDE(lE8@$+7)-6Wo&HT$o%s3^Sh^~%r^WO&@k&ZEHi~s|AWh;hci@`Em9(L5
z5l2$>S*!TPR5;Tn=H^4BU0i<?jUD2*KY(PXcv0T7xc{z;SA@Ytm$>9h0K3J%(ku3c
zxFQBV-4uWHJ{o((3IWJ1@yscZUhy0Yl=g|YOoNBF#V_YTTfg{X3{2b+&x%0ffOrPI
zT?WM!wdlJmmeUGqNW7cg<-=mj1&G`eN1_<h?l2;LnS-H?itCD@`@T5#8JHgve?c`x
z55()5Fo_SvDS<$Yi;pZr-y`v~&9F2fmQjf0vACrIxJhvm6$?&@KZQ~UN6AYR^>mUv
z2nE1dGC^Aq7s*ry4DFM=^d*$JN@D1gyM4dp#wT#`fFyhg5N?vi4A^y-EZ+;6gOdCw
z@jD%od_XUm!;<aqK%0l;Q!1SFl=x_XJ0huRMdMLPR42SRCduSL(n}JY4dN|%Ko^9M
z<P??v_(~S5L5@odzrv88L_$d@f4d~=C#VUKT%x5+pkzBe?t&zxPr$ce38xNfLL@7C
zVK7v3k*c%8BrHmVgiB`9f+|8X-UlvHQb76QC`pDdxM<0{e*+LBnfDFM$4W{llz&3<
zJ$;lSK@v!@vXhb<UxG`N*qu7z{wc|`)o48}`CJY2Ns<|FgPf75o`KS2$vL{=&q@M?
zASn{h69A@45-CNSCVANbBwf<%2-h+se^YQFQ<D56yf`PhxfQCjB-8(emTbu`x&+Qk
z<~ss@LBh_3g&fHtI|UANC8ZQN$&>hWz(l^JlFmmJNY=`LzbN^80ZbH1?tcfRmn6}(
z=qr+}&xfUAiGUtnmnEreh?GdKQ{h6XB+&q8$|OtQgu!yjR~$@2g+y8n3zd?Z`<S&V
z$&ZKOQ?(>#1>Lwcl5=!g{)!}l?)zE^ld2i&B+v7p^s2=1dx+Faa_ME<Ao+)`l53Km
zdLh{;ng0w#S|o>*Xl#`PQ}srh#G9&A+9j-LxYi;0-#j#SO8Q3O+I7k9Q8?2jnOzPK
zyCpyFo`L)ChD1ZPAU7puT5R=5CMYg;OOoyhPkSYuR2A7LnMt3>ye*Nnf%Ho*AB6ck
z5_1Q%4M_NBVPa4cvlf86lH`x!?~uea1rx)Po%CwHC#hWp^CJ?MPr;2!c=X|m`;s^W
zU-6A2$$E;aKakvQ2JoRI`xrXMB~Q|a2OddW@1Su)@_sEmd@NxkgPWAxrBO^tDt%$l
zQJQ!M#7T;BE!=9-K3cxINEyrE_C9Ifdbs8)T~4u>{nDutcyT~#T?a4Rq;Jro!|pEq
zfy!(TO5=7y=^^RELqK>+B~<fxMC$wpyf`WyItBbO>E2E>dPyx*XXq^rO+cfM^u2ye
ziLcZ?2e{)>kDs91Px{_o==PVcSc$#>=~Glj7bxY?ID@1;e}M~@=FnC;#4cUA1>+5u
zenP>D2<g!eVIorMz=mj)G?Yr#qNTZXCND;MED}m%r2+e3;)Ha;QII&PJQ~{KrC#$O
zk{}gP;r~f#9pzmUrS3#dNjr~2<g~PZCPtqmJx<w`Gtv+tR3}UAn?8ZeS?RM208Ej-
z_83m3N+&6AlqUUd51dJt{&)gI%a9hf0+A{G?Gm(|lfFXLIa$(NoE3A(mU_N`zVp&s
z^w7N^eU<|gInsGlRF^9)r6hlzG-o?R@};44SrteZgada`I%KDGTcNarp5&LLJ0{>_
zku<0iYKo=4L*On;eW$^EiS*$vC@qz$cmR}1zoY$Bxl~Vu{}s}XI`maauh15vO1f<t
z22mp&DuRhC(sfUO)Jh#>=&O?+{1VPwm3qDgd-YO_o|dBx(q>A&T$A?3LR+IWnnE>A
z(o;uZqFK6*@?I^{HI##EmF^&5o3!OAc+oDM`wV`x4(W8t5O+!0?*QH{U3UtSH>67!
zqVcA*gg%noBR%U6owuZwRRHu#chW<oPujDRzA<)Ns`r6!{Zgkj81@}0X9Z*iqyqwQ
zgVMj~xb9u4<xOZClD^OdHN(>9uLE#T`tGw(Ga@bHqH$DO@HTMwrJ=C^j7giR@Zf>8
zX%gh2w1eux#-(>Cxba9DZiBK3spas@Y0o)4mM*9NRWK=C7~mK9()0y(cM4j&$aYLY
zXrF8;mBPEqykCQY{jz{e^c|4By$pKXWbxe)ahGkRAl5-y$D5EmBvX6_ZHHxFQNYMU
zcBBF#p0a=GP|y+CR>~qDm9@PFz%f}c#j?C)o(UL?w`^S`h>uKX&jIz7t*6!haoNZC
zaEXJTOm-5(@RuE;6D0w%;OXE3WvNTi7bKf_7bIA=Iu3myvZWuue5g!JrGa5G_hLwf
z%SKnhV1%rSLU@rfTO%Z+WTH{vqGhgkU@t~?%Ljm1nMOlb#0gnkAk@UkMmGQvFDs!J
zXo75&0PdfZ`O^kHQMMuoN>9m(?qd|EW!KWcCCU0DLC(lTDbSrPTSB?Zv$8yjSEb0-
z(w&zoOQyp1G+D|FaOtvwcQMWk*|RwynX=Lz+L4@-&F%ssOSZ2Ama=7hF}yf0%lQoE
zFUWrX45B%*KtJGfWnorm%ad)~2g!U{_22NmKz5IwP?u!dqj083=BGkqvCKp<n#-~$
z3;>kKX85D8R3@uMUzzNn3;N1s7n-KwiCiH|2}Nh6ETj;Ys$?E}Fv4otOxm;6$Q;~Y
z>5A;rD<HM9yT<{nlkwU>uF5Xv0#GlTMwKuPvYB+&=9;W)2yQpZ{4JR0CRy<W`kG}7
zI>6Z?yGT3pR@vb%(AOqAOe<x3yX?S406S!pa(LP)t9$`UughX+@6;u$`xv6#GKXP!
zctiGX6ejql?BF|4+9P|7u7q2%mnI?7E9>=vNS~~d0ur}nk4}U1%l!Yl$7ECcAu=Fa
zL**uevS}0pyDQ6h5z2<_vOv0$hGmzw0dY^}Mlbad+3Pc)ZB$mW8QguD7Zo0j$>z{T
z?1Ahvs@r%doAns}j?2b}q3w~ZnF8VyG6n7R9?Od9j-QnMz7RU6WS&Cc9OXezL#LDc
zQ~H9Wvpl;WKDo&4$5PO`Pd;o1>niv90>J(9Z)y8`K>pQVm;^WZTl9)|mp`dT<3af{
z`X<&P`D?TmIV}JDCBQx8^M8VQPx%jR5IG{Rqpx}#m0$b;c8|$x|AO~k@_!eBc+0~c
zL()fHy9j;9<=g(dJN)F&&4J(katkFI1LQ-WKzE?rDGMY>9)}RIL$Le-6;p-CpK`&N
zLgg{^QV)}7bih)${CUduM94E2gG9>r9)ETEEB5uYvW}H+pgNut^7nQF9Vefr!feIM
zgA`~?kPDZ<iIZ{}?Ku+V8}lG?N<O<7+-dpBQHUhTe}5HP&dA>ige%GN_vvYKR_@V-
zz7+XQ%8jMU+bEWrCU5=$T)Lc1`?d`E1^YSZ&Xj*csjhSK6>k8TCI5ozyRzjX`o!~j
zxtL5`kguRUR*wAjWe~}g?>!1GPaZ-8%a@C&z^Oo<-UxD0{yQDFD3mXyrTiuN3lz&K
zlE+cxy;yE}1Axo&Z}vc>R30)+6%S?d9%r<c%V$wmszP2+2SlYj&kRJB+&>EjtL2$D
z@VnH=&tCv{MZWk=aJBN&^h4Ci7t<Etsyz7=9Icnny$9DC<URDhy(S-<f|f=(pDHPv
z<Vmz6Zk9jT1we~DK7hWn+bZ8gpIvK{x4(g5x63zCw5&rerl(w|y!}aNyDlG~cwU!$
z`BNa>@|QkD-wpZj9*~=IBPHB=<eTZV(=GY6Mkwo*M^a@|pPWslNw?*DD4o<VzfuEo
zM=qf#_keulP5RFKp!^}#P~MeiAHmRu<frMx#jyMaUEBBMKV5=PBl2nMfEbnAb1<0u
z@~k-69g}}B4bD7}f3XUE59M<xA3H7&r-k_=x$18;PRPf<g%^+I@6hUMQoi;QM5g4w
zQQXo|v6)^?b|-}&9m?3Jc=f-cXT^Mf7~HS;_h*m;iVx{7bW;Q@2j{MsPg}%;io0jv
z?;*u$Iu3DIQ5FCZ55+e!aGr{PC?Ix3vFt7k9#y!|`u>=L;SUinMdq*Y*IQ9VD>ffR
z@bhrg_X)*CzZVzaKA7tZrvenqYtR~~5WEJ1L5dnm2?i?|$6+@_(ey3)LKUZIK@+BM
z8bn{XB8pOF5sEBYcSb6DcSCoS;?I>BeYE1qr$J&A-%%_lR`C_p8J<wMtOPtx@%a`w
z6R#+ffFvj!>~DddRD5>~mQE}3mO)LDB7FrAXB1=0(3q@{lG3w^zi64CqWEG8BB_e!
zG;ljjkwm2>>57pvAQ_4l3UOvC)<(dma|+(;fM+R=>;NuX@x~gE^NOhRXuP2KgdRFM
z3iTwd7IGEuQ88hj;@w5iov#?7nv?>?PAb&BsQBeHL<$uyDVWPk3ND>BC{hg33bk1A
z4HqJp6&y!!C5p;#fGbrr&;q+mF}MhTa>X$tL@E?Ax;!csZ_<vqN)hf1E!B$O{-o2S
zHH!1JdcLCgIs)$3D&`~rQKyiufzqoA=haYCuh{i2`Wh5$+M-=kxYO&WQL()QGt;E_
zf>K`1itC-Q+oHJG36WMsN&-x@DVmN!S-WD|egHZYsg$JcRNSHu)m>NgnWj(UJ9H`5
z(Qd9=!B)b=4aM7m=)9!}$b@LGqS%J{>Qn4UhML=og`}-tk-i<|j^g20eqX&leTn_k
zDgf^(b}fhf5yjAXbdD;7cVPd%B9ub2V~QcF7JHz`-3_G=6{!?F9#>qs2l7bq90z?9
z3jPsjd928z3Zh9xu|MoiDK@bHcT`TRfryhb@;OYRv+~7_@X$rM>IKZqKINBoN^!U<
z_tLcQSN2hL=>cVFJ#@P%<+KEGSBA_4{-9F-DjE+dyQxs+uu?=3Ee~aTJvdM0i?r-L
zq70<fk-xIa4|W5TnGPU<%H_X6GDw+9+rMCC!H;k)M7fD#6rswL4=4>7ru3m_S-7%t
zE4T=ym2$9=${k)XAEivEq+qo2i*6udls9RO7OVVl3;IqdW6xj|amq~((HF1$c>;|I
z%5Uo7%t__D^wv#OuEjA&hf~U7inpFtdb|V=lawE<2RWm>^*4PGAX&MBDvQr5TSUO8
zD4(MBL8@{S6(*!9eW?a5UD>o8A{ok#y&##&_vz@+IpzBwV=!4t7k8M*R_=Nl<h=54
z4X&08%Dk^&K1cb=Qj9EDS>S=+E>FpEzyR}=uC$ygRBD)1mUKxu9|3BIBBh2F$i>R%
zeuL7>N;TyxOOz+~qOVk`(n3v{(sMKV%9Rgj`B<ssGayo>e76_4YGvppjIc&2C;_>m
zEKh@pT4gR31l1{LjbkiVm4bzEyI#349Hc?Ho`tc@zos0fmt&*yAg$<|l)uKq{buD`
zesdP%0r##Rjn|cv1weEu->27bw{qeh05_D)lvKZ|{Q5I^*rVKd4!B#&H56a&Repr8
zL^<>+YueFwTRC<L&h#t)pdsB+eoTj{29$nOnlh-&YlF_a%I{5ZW=NUc3z1=E4JA15
zDI4ssfgMpkj)1mNCFe58edWbekTGT2B+NfhX3_@cp;AoI*KuV=Hvo^6E2->$LOF*D
zz#l7HRzvrs@_-QYG^HG;@S2lq7A*#yRf}UF>7uewtZu(*S2X$#sE*MGAKg@cAE2w#
zUFA#>mxHP}8!R1Ct@;qeQ#FeU<Bq5fy$F$`s@U%#;;qtAzTZccUkVXll|l^exGIZ&
zG(Xj|*C6Syx=a=B0V)HXnh8`rYlp!g)tU`(J6L7xg=B~-`We7ORsU4e4kAqDMwz#8
zmEIeO2-WXDLQSM<#W+NxRMo41k5>KL3lakaMi{GVqPXb^m4V*EajFm*w8g9b{vY}h
zR7WW*eNr`pb`XiG@SRY0O0|)yUrwuborG&is?Qg~nKP=$j~u3b<B+U+NcZMh)z_3*
zO;K(88C<F=^Lub<Dt$k6r>lO7g|-aUo=P~HsS2U!&pFjICQMM4>O%^oXRGWKeLb&Y
zKL^)xRZ}Y9@>CoA9GBoCQ+*6&g{tgicyUP;l?^RLD!*vBR;-$82Dz-tzX*{M)sv^8
zx>U7>77t~r9Y&CHl|u(eg=#ey@JdyF1`JiHCh5CM)vBkdAh|~Mq8?_isAf|bu~u~>
z7dq=yrL+RSsyb$m1h8JUD+Fw#DsMTsCKZnfnP%0C@c_1{u2C^dtLhLv(b`nksI;qH
z<#81zI#gDw{qIz<$1$XC)eld?!yBqK&ait^m2d<igQ{PaK=obK{plb>s*o9gkErHQ
zvUF7S{)==8+*kF};g>O$g+enAR2}rHd#Ktz58Q+*j-nEeRg*7*Osc#oj_#!Pw`17O
z>Tx=Q>7v$Buxy|D_I(gnb?<jjwqN}OJ;#r#2bV+3F?C2G?i(-l2k*eVx7vITZu_Wp
z`Oj>`wW^*+3FzZ$167sysZ|ss@K?LG!$g33+H(*MRJ(+sFGziY_NT$>QQEYIsPj6|
z7^<G4xeQm=)72HBb}Ytk5UH-GoNJW&n%{44;a6rIhh)6E?>zbv)K3V}cT)ZGZMc@G
z=2K+nlv+uJgQwNYOE8Ee^|nfgoKZ)m0+6hJR}T1D^;+7Mr>MJL2A8V-_ydTfsaO0D
zBI#-&mCj|T-{^)Dnd*d3FwSiC83`nF)UVsGg3VR`4>iFKdFl_QqcvZ>VHdapb<8a&
zy{LZn4~)7{-KxioUQ&Pf9+VcTU!iY@6{~-veEDT{%@H_SqJBX245jMUKY=S#yZ;5d
z<?27y0Z^gl?t@6BdIoK0s?-To^H#0CWU_;;QNLS@&MWGp+kn5Sz7hk{s@_2B<Tmxg
zr!o3=btt9#JJe2&7+R-#Ar*sPSC>(Yu3P>3_vpK!4rqnsP4#T@utz<Iq7b*#j_-o>
zst?k^us(HbKXA9zZf*eFQM+uWN6COX>ku3sRNH9Lepekyb2+5Gl?L;}>J5~QzNfxY
z2BjnFIZkkGRK3I#+<mo#R?TB-(N4_FL-ixN#m3b?&}-n4x@|Z5Ce&pw!NbSuznK`|
zq<St@mrkiS?E!JrTt*Dl?%<@^N<jr@%{&9}E}Fmp25_I|_dRHI)pXp37yC6=d!h7z
z=E$FL-%Yb{7y8^a>w+P9P&4gW5Km3ZC-CB^<~)5o@0e!nS&Yz2Bcp>Y-Wrt)8htdq
z4RFR+Q<e)!e@$5j#$pf9XedJvs9D2>?jTM2+vp6|R8q<*L{lgM3DqQ0_%TeQZ^5q}
zt{GYhHIbUXDR>&C;oXHuwC49vXp7N2{UzYBn#)vjbV4(G0&d4?*3)u1Uek2~S`suf
z|ACg18t)|lB-%C0rbEpsjg_kWlQh$hqV<d>(gR$wCi8QsIjh-3-$qE$uxMA4rdi((
zrRkbqufmHA3<laVHS4k=a!ykb4_ub!S`WBv&HOkRyr9`lxt<&ivl+9Nt9erfE>H73
z9n;L$*k7jtn*z;DT5ey|6pLZvvS!mt%teWYe;IwHn$?t;EYmbo<$1a0(v#?`)Qr=M
zy-LIGMqjmNa|8NnHBS({PP2y!dai1w(YN91HLbK&YS73o1J|g@qF7{;ripgo&6<zx
zYoVr1b9f0l+clY=VlW+=o6~{l)WlJY?YgEqABZl^cl5=BZcWi&ki4n+F$9u58h<Jo
zzomJ(5q-UyY>I{SX_OZ*Gq*M0=7IEU=FtUlN3;7^7#h%Y`~%4$&DWF<9o8JEp*{OO
z%>~-|jA));2i>EZpSsa`U$c>RE)O)HQ3C3rrj7~=#x)m~L*$WWz8sAcnj7Cj_mpOD
zF(e(ey^BGdwBr<?an|mWz<U?%VtPpL)1LK)`Tg1p^B{6SyCf9EO}li6(lhSbstzCy
zYJZD|sE78mK8Sj1*JQxN5$#h-cz9I1=K@5IY1=4|<fXmU2fVlT4kfjGv>!A=#7{f^
z1mOPKGzxeGXu0&;2WnrVI6{!N;zcxuXcu|`5UTZ}bz7LW0`X0|Lxgq@9hQsKK0%B2
zDDCmXnEYsM_t!8VqaAF7npo|lrRa;(_S1VaUc2sT7);Q9$3Wvr?dQG_Nz@iIfIFq#
z-wT6D+J#GD@Qn6#QkJac(zg7pHk7LDQnVbJu5|78pE2q73~jItYBIHZmSKX=X<bPs
zOS}6W;Ip;Lx6pT9`+GP%yrA7d`IQ_kj|zHnwY&P!m#2Mu0?y=X6B9rRwCSGk@S?Vi
zD!B`_2h(BclJ)`<eMQ=ID=ZXi*CPh%P@>Jg47W=^)4s6+2FtV=AHdUctuJkUE3}d#
zsHxNjM5C`t`|T0ntF=3+M5{(yKu18YXuGMTxmNoH#ZK$AXTOKitJ=?LnO(0{`x#bE
zUuZ9R4}fN^n+TR#w2M9mY1Pi@fotvBf9cWCq3zAbI6Jkw7ozXFwt+GlUD_CW4Rvd$
z)nS}BwEpYScT<~2JO3W-Nh(0PrR9%9b+1+_1J|bwrd+^n?SpUt`n41N7{eWHv%MOv
z1KQ(rK?b#p=yiWrE1-ngu=XE1bZ}4WPp^{^?QApp#<c0QQ+lACQv&i(`&Sakxb`c0
zojlS;(1UnF`@gT@_G9gfThTYERZ_%wO1p$kdpYW|H=)l-cg+U#&N@{TtwdaO%o^z4
zr>k&*sH<+#b7<VJTXr6Z13EDs&vw(T^hBS#E@u<mKd7^gU=j}LTpt2=SXW~P=b`&E
z7dTIy7bT;Q=vLCc=cw+*4>6Wwx@0}<dg+{LvEi+&r3I#suJ;7R!+drB_JTdGi=czX
ze!Ac2SN7KhoQ1Xk-7U()2I>M2gA3Aayo`Yc>xQ-PB1Ff00=h$WpV7`PO!w^|M8b8O
z?t?_>meRX8T9-tT!WdoQJa`|gyFd}06S}75&=RN1!ZXP35U=}}E`bEy5G`;|>Qb+R
zJEhB^hu3M{R*G0B>2}d3Aw?JA3%jYh-mMr+ny%6fYSMMd_u)l`?zxpPn5kowqwkz<
zl(y_yy5F3kEL+D(hva#koGy<Gx;}b~<>>Bz2}kX@x|e@PXP$0H2s-n1Gjd>}KzE2X
zAQyGD|AT0u?jhCCT+-#1!bFiSiPlWTx`gS#U)FKy3M$d<pf7us>OLQUWSQ<TU4iAg
z>~!d?&^cBBP^k+_f@@Ve8@>0cbsQ>~ud(Y^J_6#3&Tj+QT3sQ{UY+i%diZ@+C!<wp
zy)MWFq(S#8?c=ZM-lAB3qiz8c+M0CFhJ$O?`Tq)Bi|$t|hTW>Gq06~V=P?Z;?K)i`
zyy(zLSm^82ouy>sb=|L24cw)(&!lqEZrvgZf85aRngyAgIvi@neWY7O0rOir+c|K(
zx(~hKXrHcvB0{%yH<v-OU-vZC7~au+6M!)d=#J3qU{Lqt8!&iRS9TZNknZ&=aKpL*
zTCCjDvFS}UqWh=^{*LO}?XQ5|*WJE_5svBXv_Tx#?V}=;M><DZ1Wf35&=*%8>t+VQ
z#H7x5A(T$(K3f2#j{1KOqtQwKCgn<<_4i+chc5bx7vb7IeG@&HT=nmb0KQ+peKXuX
zpl@}8q?>*#Wdz;zThl4haZta03hW_$^Hm@Y>vzhb+e3fj7Ko>QIbCc=^v{0{k)!(g
zHSqA5zKP=5Ui!KsIODB<ZYKueqkkn5BlOi5Qwrj^zU3Gs{q%qAg#~|o&65~Xfc^}<
zumbf?^C1$V|3yPVlyLn{E?Oh>`)Cy#sn1S^?kN2jJxrqYhpBQYMnCHyNUT1K9)2hE
zeiQ(Y(>M3QM7-Weson(riX9*)^>QivP1I-7?R!eEPKMj3^_!lCqe*&yDaaZ9GgYvV
ztl#-?8t%Wd`VAb&r08cB!o^hmY$5Pz`f@d7()DjVhsF&3EV{Zg_0u_MJg0x58FsVu
zj^D!HZ2cb`0M6^#&G6}hzC9cs=IEmq1DC7MC`V(Sp1T5#`TDw-(O95w_k)&;dTj~%
z?1lQZLbP7eKT{2*Mf!ev$`|Y3q*D@?^-8MyDA8|!8~9Rv;sCrT(}&UauUy}!LSKd6
zJph18J)ibERr)>wNVPuM3fF4%Ewos<qF?m~0JZvb%HP!KUta_*SM@mHf_uxZfAuiz
zHt5570AACV(7}pE{jZ_GH|b9>;Ayj7un~P7`lV06;B~zR#fQ4|-yJ|-w?32ZqZ|4t
z+IZd6r%gd=kA8sGf4B4=3XH5*fBg~q`t%)ANZ!>yN5`;+^)Yne-_zTdQ&@XMKRXpN
zWBTyJF!4a|OnI4y`Y-5vKI8gUsvvr#FK~j$gkC@;e~<NiKlDxNe_RhTrB~83+tI*R
z1MXy4M`!4q4XG4&a52oHr|mw&#0?C|)xbChFZLT=y9#o^u-Q)ErgJk)(DvNjpr(Dr
zLBpx{F|<R5-zgh>*pNqsH6Di7c0#wO!Ehhiju<AMhVG+=ci3n=W~gfi@iMHW3&Pv5
zfJ#ez3}rQF^fko(1}(=8+h$?Beui`r;Qj{v8i)iKMtkT3&4C7g8d{Ly`LEzquwmON
z7z{D!rU4&n@VEv`VTK)d0Sq^|*w7eZ*zq?=q@iOg8lwz;|7|Y}+f?9U3~nbdqp=3R
zau_^eP&|RgIKz(;sE#)@eS~o)7&dGIIcea`qx&z>@HHKYIAz#E$3IUS-rft6WZ1bD
zKAkbl_Xa-MVEP!1XAS?-QZL1@>>|vk8fGS<FU>Hr8hz=8=g*-p!%#T{T&AJN058rN
zJ~<CA%P_eKlaOr~rYLQWp-v2vYk1-hT3hBBzGXvAzTqMRhyug-evJO2;TI}lEi`;g
z_3W1nX<HytWQcLaD2ffQorK6`!~f=@vBdE0I7CVfYrcjTWd?l805^xhp%q+(;a(=p
zR~p<Fz~3sv_lp6qHsljmV+ej4_Uu;-nY1;nHIz~!sLt^9>p)yJcvEdvz2UQbsA(|x
zTm!jgc%61PjRvzj`kD+2gQ2F`u(=54TMQrGgh;C)>Id|-8BUrp7wv{OspP%Ga7+V{
zPQzDC=(}$4q2xuEAtn{}y6uKV^y=s_9AUw?TL!@*$n+W(&PHdS;WY~S-Zp$eb-4Y8
z-zlYd$I#jVr2~c{BSZ!baRr!*yN2pga6<++I@399nEx3h?-{O8oyv&e4i&488pbGM
zao><lCt1e~198yuz+iWK8ln#k0`hd+5I}+CM+P>1c6P$ROoY<M21^&bm^5_DAUS1N
zMyp>(V;EKGI2m`*qtw|bTnG^tV-|hbW1sPp7og15_{D8#*>8N$30@p9y1Agy%@~sc
z;%@x(I~Y1>eEvs&APyOiQz-VZ@iS+r@i1ml$$_Ua^Br(UjLQdM@ThUwewaUI{E>>P
zyo`C2K=L*&p-MU*<154XVSJ4;9&pEvUyVW1-?*1@9|6V{??EKc__W{owODQo)<Y!B
z_-8!&!i{y5PmM6npvj9gj?sQI%J}^$G)5aoDdrVpTu8~GSmT4wK~5OACct`}@nr=>
z;*I(+01}O#F<{}8@moI(_q4Gp7@j2=Ltlo-8RO9@IG=1(UVuwyjl2H)_YWz?P%6es
zHD=ILHpA$648Tm|tsqRrIpeuXh@LktcoUW`7+0K!YdJ>7v*^n;a_ExHGk)^}xP0TN
z6W|3#e+sBxG-hO=uh1xS0Pd2J$AL(ZanojyVq-OZ0pzmrvnMExRbm`m4AD}f7bQE(
zj6t_R%8fG`V7J2fFD>OOjZ4zNRT)2A4asWbzNdhzF^cFddc~+T0Z?mvg<`LD#-IUk
zSB*Jz`_&u2r}R~WaRV2U*Nja+L0O~Gg7uU`lQAHgDt()csjDE`Vtn`ud}}qjCxNsX
z6?dSm-S`9*V{{npR6p2h92J9HH*Tj7zH}M4QYx|A7`+wbhVl3g0B#z;{toaSW5gsH
zZy8&J_$hjgYv@hYXLMSM#@oiIE8zN#*_-KcbH_MLA7>aauAu<Jps{x?4Bj<f5rGUD
zkJ7Vb*!atb81_A*<Li(dF?LWycGMU`uZsJ|bV>k?84rE~yAO=j2H+kV?@{1y+_>N?
zjO>x|U;28*gz*|(j*pGMQbusnSVem)`;>756*)MXj$Vg07gJg(fcs3lVnAF?Uu%Ki
zZ`y8v=mC?N3(n0nvjbkZn{<?2IcVA#hPgOoYNKb^Vbe3o;5<yDRQlp+GL3*cV!A`i
zsiUUByU=pXG=pl-yiBDt(dTV9eHa0yKBn<`_|<$(RTP^%ZrV(XJ3rGFdg}O_zMyPj
zfJx{MF3_}v9(qBh7xthr*p&1na3LnuS!fA0In!MjX1XJUNVutv@}Uu?j*SqBG^we^
zC(6{h4d$aw5p+|<nCyRaLussOJ0)UHm=@BaCC(Hw21L9m?{D-an)Kd4oHD65VP;R8
zm=wTEGR<?xB%U#~dO#%E<Uj{N&YD&Q!0i;%j6!g!Cd~^lm~IN+gT@R~9$qdEnWnO}
zz@0OR*|3*o`q|z9{CU#?Dw4QhTAK+(j_KcvFrRDcv7j%{)I)jaeA7k>EESqIu7k)W
z(>SdficGPmp{Cg6?E&tx$%AUJN=z^PcQ=`iQDmpg^g9RsmYW`YjgeKD8jk~BX?kiY
z>{XeLt)@^?wJ9qaYHCcoCSc-<>CaB6sWt5?2cpjO1ZC~7npmqLS#MfA7p^s!wo`iX
znyF(axJJ{rw4Q1*DL#Nmv#FU*#kZK|Wk6Z0sa%S_HdD(q=xjF`$Dp&rl=%Z(>ogtZ
z%)<TGWqNZu)O4G+{tMD$`X~(eTc)%MAbL$Z@`3L&&0PWDZ4-|ojr}Ie=fK}FbuIum
zU@|rXH)v8)678<ZjrOTSreD0^_OPj`1<FQEaT(~lZ~Bf-28@|%>Arnn%6y%2mJdy7
zG_-M(_iy-R9+}RVF&7i2DazA7Hofv8fRm=89T?1%$(@2nj%INuh_kuz8F=VoZlYA)
zK6B#(h`5@+`vrjgX2#zzalp*?goj7XePWPf<}axp&CC4EHi&qeBNAcH?qe3@z`U>d
z>6f6?-@JqJsR8Et8^8ye*X@MvAhUWDeZgiQBP2u2PfdXfHTzO3KFoZKPFIDS|DtSR
zgxQVW`jO_J=v%B&=CxE68*PrFdjA;n#7#8Dnom)P<BZv71n^|LIeG$fnPT>8!C+F&
z)3>5E&74n3`*id8d|1jbtDXYMG|yfE-RI1?&qHaJ*+l<4B-{Kxg}%<4C;x=V1@q}k
za3;shXF(*_JWc_;JhO`G!t%|I6mBgr-}^5?VeYJgNTJ#8mIrSxncMuKyU6Ua18R!R
z0xE*OY;LF3Mv3`yBKk_relEb5nNLTfuiX5i9d;|syI+FtO7lj_(N>xFjia&JT-pVl
zHRf(|^on`?BZ$<R8|a~1XYRg)zN_Z-OW<0)d9R(kX)w3VLFYBIhPE}0<~dW~n#@lO
zL$uj^k~YX~<|JCjwVO4yXzVbr`3@qT=2cXJdENZ2J6!8BZ+#A=+x$#68gH28d*S^}
zbJ*W#>@k174>NPitfZZEuX!&$XZp<3ShU@}ZJynO)_(IJRPT7l{0mhW4wyaTU~tg<
z)qPmHYc8UM<dC^=9tJvWzWpk$&U@x8Cp3<j-)#YW)I8?|aQDr6+SiYnlXs%;f%)QM
zc=6D@e>MQ)X7@@A_mNpbn}rFpgDZub9-9p_&^c*V&~9PM9Bly5(Ngjb9CotQ9s=iV
zN&5>TE*39JEA6vPQA)$r(oZ!Z`z<#l@bG};Nh*~%Xqi)mK^(HQw!w?TmajJe=VAFh
z5;#xGUV8K&vAEOr{HWz&IGr>*W^tl;sh4FbZPmOjA5sk0$Kv}Q8htG@ZUT7RGV4$D
z`B|DN_wR2Rq<Vw^OOzFZ3AC(BM`Mshhhi>=V9OBw_92#~zJP~Xrrv^Nn5B<$dEu7n
z|D~NRd;ftKkrv%D_-l`{Ts;L~v}JW45HXhUMvN)e;+z7zCoD|LWyD!J>C9BTWtd_?
z2^Pio5IJdC`W_k+Eq_ut{gfq~KJ0Va^7CtOG|A!;3EgKbrhJ%BwtPhCsI!)R&S*@r
z6wm@8)$(3CNSfVJPQkBq%i=eoG{dstEs#vhtm|kzXE{RqgDlHigTQB7(l3KMZ<+QZ
zT)SZTmj;t#d5X3*xt75T0OVQ9EN~{@@{|sM0*fyl7r1CSPYc~bi-6vZmn=z>fEQVo
zd=64<vA^&V#&p@Dr<#QlOIHL$OD(b!&{k#%r_=J~mVy7ib!4e^g!yXAE{eI;S}JL0
zT4x!X4KJ=*?$J7--eOw=gAEpOBy?W0lu!b<(X!-QXlb%=dcZYX+PA|(izSTq$E_B-
zy&sd<W*NN=nRd&3dYE)rny7Z5(_;7sYOY(%?hx&=Y@iTnx8*mA2i&ksZGg6$mfIS5
z(PQ~$0lc_n`GY>d+H1-D3V=S#nmCZ#7X1_?`z@N|@bHdhX)Lr1SYAH|F9t0Qj`S3{
zYnjG^r6Eh>3y>MMES~~*&oV@hoe|5<E5MIhUM&K5-=d8GH)i>>9l9S_+$r|_(2_u>
z*v2igNho_{*+K!!3Cl;bVdAmHM8Ts;%gsgrrYwoH7j?8QxeG}rYrubX)y~!^6UO9f
z<x+@rzqR~zkOS6;FM)8g3Tx5lZv7uc6%SgwIcW5-4%4d8(>i@S96e%99Ymj(mH!Gx
z?`?hdWpF;$r`BOceXZkhP<GtvGJ!rn>o2M33$%7@g=<09^yyUo7;OE!8QMau*C}uk
zYJHpP3&N~_zY5*q)+MyRh_HInax&8DLl5*QtC{Z2Xlv{z7+Q>V&qol6wVvcb<b<^}
zA6%Su5e4_-t^cSXnP6>IV%R6GE9;;$(HgT5qd#TU^aE}`ZGD;Uu_Ws%N-CVO`d$Z@
zY;B(hZD+01cY~x@M-u={wf^-UNSZZh5w5ay>tH4<Wmr?`HJWLiPm^%Ys<c5Q%Q`|U
zw`^-5MaR!upP}XY1?x(BVdhvpUO;26^{*ZP^6XZ9KWM%+kj~N-Sm($=E?OTghTTHz
z)#K28$-3DOjYZbja=2D(_31<7Wvc@{SWB$4ilDpHdYuxKW!7i^+w5B}48VMabtDUb
zO6!YsJ5*WKcc7)(YVAg2jrDLRoVjAPbE45%YkjaCopsh3wCK5N9nQee>aAPC(AZ#o
zngWm4tXJ#M*J%CdW6WifwWkgEW~;si&a_xV>Ar8Z7TV!<hxMl<nCP_DKLHP~TZ29V
zuFE<^A?R-Fr(U>KZdmu$0)EqKusdKfdaO^-Z*j{yhjjN^ovNUw&-yXNRBv17{|ZFE
zwUc(#cdWc^&^BP*eFEABty2MLylZ`d;)p}mw^eXv*m~eR$UST20;nFb-lor2jat9^
z9U}Lwo|J_fvzp!n?t!)WzqQCi>j5f9AGdl^i1U&4?K=QYSl?)e=wmB~_G**X26yyL
zS%Ycq<7g{(fKN^~*O~Cw*>;*TW-hj2+K}wCeMGMXSKGl}*xheq(LVWr?F;(8qMOa*
zBn-LRPQ3%bL0i?CC(wGxmg&crV=MjyCAE**LTh2-m~DM9I4|4USE1C~c7y^<KDHGU
z=JK^Y_YjT8Z3_w^>1WeW$*jN4dn4=y*zUW*ZlLWZ)vpKHUYHKIgKb;r^%-Kj{1&)S
zTV^-7Fxy)^SP!@5oI_)TZM!`N+9GY7K&XkbMN%>^*0!5M7AI^yv}=#E71474r0q?*
zsS|Ano&-5%3#G^18QUN95>K{ug~RQ$wmpl{m|}a4_LQl%>z9B_v&EOe`%K&F0ZhU<
zTd5UXmhIzbVK3YEdO0mc&f88>66S(!1+DdRY?~>mmut&#gYG=rcl0RDw{2Fz?*dzr
z4E|oUeNWZtg*Fu>b}rdQu%~q>vMr_~BE`18L*Opke*JHkZ+oK;s!MIUe89_W)&JH1
z*`g^cR$-gFi2gHrrOisO_A1*KGT5!Q+3#TVHMT^GI9{>+Lgxx=Z9P9gq|Uay7JXN3
z&J-o9w++$aqrtYF&WT^M&7)&Jjkf7)0cf)QT!+49TNOFlVhhUwuGRMHH|T4#<@^fL
zZfnLBWOwMW<wv8l%l1zc-0!x%O0U5iHualOdeioj2BgQ<8U*)m*~(vmWUnptQ#AJ3
zKBc(lZCe3l`uc6_=mB-dw$mA8z!vxz!ydH#PXoYR+h8$V8?v?g!tSu`+D|Za&$d+z
zN&ATH{~TR;TvpZ7S4+!mG0U_?D|0EcMN8W(Ev;W_Wtq>u@B99cE!M*-s|d(0n}DEf
zvI~f)fXb$#2+A&^2%><Xf~@a%-oNH^=FEI&&VBAZ_netI_qjpw)`vUo)cI)VQi{nA
z?|g<zlt<79{l_~E!4MtYc{2rlV>=(Jfjz#{=>cFSb{_r-*poZ!skX|6@ks|HT^akS
zgw%~8Uk&Izj8nI85j+{!)&tXvp@@NkH{+$%fc9}P-am>?Uq=2TnD=9BqczN4##XAo
z@@F{D0oliB8w4|eQBJR_K*kp@z-|!ZISYQ~{fzDZz^7ow$O>2rVQj2}WGG|I9n3Js
zuoFl)gHMxn1fz@v63KX~8}_0Z9Y4c-48zgu2hdoCj*5=r81K_|>>y(y1y|x3e$Qi|
z35-bE_$4yp=tS)y#;pv9Br&9KV}!|!MOWd>Va6FMDmlVPS_x(fBV+~CQyBrlAZd&p
z2O*NqsHc@%2IF4}{2ygtU4rL_amMitT+CwJr7%u5BZTTtau~;Gp`ObabB0VFqvZ$`
z^BDsab2!HMl6HIrjIM)V7BVjCp<cvTPe0*tMk!^tiWzQHe|v)QRX9XS7_*w-?@2~H
z?Ey|Po}&BsG-G@pn5B&4UbGY`W0a`?Q_eU%gn^!6e3uQ;vy3->gr#!~?^9@1Fgz&L
zUCDUZ2J9-vl3&nwp3z8Q;#$UsB>=s|sG>Tm%Z$S`+1D|A<j}jq_}~XvsAtTwfZ4z(
zqRVxaacd!%*BA@#(npsX8N-yUYGG`n<w`4K*-CiP#@I>e(soAZ>tJ4I{5J{n9Sl(>
zByTV>w?m|pVWX_rO~(31_+f4_zNdr4-HZl$^Yk#(w1B(ASU^AXJ;p1afb=oqgWzvJ
zV~aPy1{q0+xI1PJF+O+|mL4#cY=q1(<6;g#M;K2%2bjkU=6zh*afbFB`X(6h3qU3r
z)p}TRVaBil<H`*8firH*A3Nz@XI`(zrSxQ8bHN4jV#?@`RehN!hv1AK^Ij(;_cAkP
z!(IUMX?l%00+}o4!(b5ezY%nXFw0+sXeiS`v7IociDuhK=KqZ7JHTAt540%e^Hh@-
z%XFtY`Z(s>7APEKGPgl8kvU3B>O;)GDJz}C%y|lfIKn(~6|EGe+w(A#%9K&%YzFhW
z33zezOXk*K_?^jAd7+uZWIDmAT;{}Lz~nKHFNb0QvuPIk3Yqgi0x4pa4$$qzREN#{
zY5EdJ3@zZ!F>^P=d<C<cjv`eu)s(raVHQ$Nem%2--d_#OmuVuu%B-gi$u;IdIx5x3
z)P#ZA!rb&5pj(-_6ufF<j_rj)J9COY7j~UFeGOddU<Ohl>kZ~j3bAxDXVQw`Ci8g*
zr8aIc*X@S+F6MC$v~Dv)zJPuY^Kms=cbH!pAll1ZxB+(WGI!emdXMSli;?v++h4?`
z9AMh15aT|xyA;@iOabj8hnUk1U_M~J^d|I%nH^G)5$3ufU_NHvcZK>mbAGl1q7%%|
zBrrJ1{CqJ+;mj(%3`G~#HYx#fWqqT9h8t@(rFYy}sg(ZP!}^a7@p!V%l)<1E>vtNV
zH!Fj_pXkGSxB+^;EE`3Z{8-n*LH4rZmO$N~<wo_3`&d8h2MJ(p`egRkm=Rg4sWv}|
zmG&hp?Ps~L029nYY!deqE42fzg|fssup7n-mVtz`{zqBM2v%-b$ImD%{jVMdV_Ao2
z1r*P^I)tGmuwJFF|0J>`%ivlvi}yXC53`<$0N4@MXGW-}v0UiLRXQu3!mb&tduxG`
z#d_)opk%WW4gw{I^&Vxz@>xH&Lhl&s>~}yZV6kXMInD~rM_(~3-w^|i6D;OM$edy|
zQO(h5mg-kr?ow9yZj9v&%RLs@XIcNz!+ef)_B<pjSlT*xQOPQ$&0rO4tpUzdvu^7F
zR>L|+kL`JuH5QgGu%4n*EEiczHUg}cmCS$_msvg(bgE<R45Y}^6;>1_pz2u;s)lS}
zx&IE)tE@iy&fYba-UFgdtm`rGqM7yWbm+IR)NFXs%JPnd-8R<imC$QvxzkqbI_qo7
zGj_1negkK2u-?gqg-+I2H=%Ho#iZfhVkP^6bh9E}r)WqI>o5Z*?y!#0apZff+XmR}
zV|`0+_I}nIkH8#YZKS2%eO3+qL&+eko6au|v8FGB$OD#n6ka@J&D;X!Bi4~upfJq(
zY8}W3Yl!LqAG54f?KaA?Y0(;Eg-}9tob|yZO@R|E#bLNV$;zUn=M-x$mEt(FABivu
z7xt_U5LdR5W*s+n#tZ0kXP>5>fCn2Z7~Ib6mCvHjlYQ?wfO@fC@PH+6_AU`5ec1II
zA?eGugaE~l{h=9sd)dvDXZL4+MsF&|KDKZ_Is@3(tKnN9d)EsfLG1G#0Nu~Fv_K}9
z{eCetLfFDpAfas4A;5&Od*?wUoZUrbD-rDbuizp?vP05g_W+woueK=mA5^9j%}zUj
zD-*+hgA(PjZ1G|+<Jf+5l=`599k>Ofh-dp)0h+)T(#|xIy(SZ_L+m;9v8E(;ydEZ!
z+3ck-ahPqSdFlvz)6e)}Q`jml45qS+=Yg5V-qZ?aI$KUhTQb<;baL@1yPAshGT9b-
zd1tZXsTwPrZKt<F4%?xjEmJN#$`>%l*mEgMRls)r6QqzGa2PN}>@nKe9%uJa0<D;x
zNsgXiBWZ#cJbMkTyiT&uevdJoVzaPInR%K$mvZT)>@&1oEn|mLaIc)5`~*bKus2iX
z#aXtVj-Q-kk2>;UzJmQ0#dIp!FHQqm72C8Jiq-5gcl6b;ukL{8dG?$fkPGbRE`xcI
z9WH=mExVNtEMH>V-Jx)q{T=<1b?oAwFtjV|xwMU{XR8{(Y+wt&$LO!Jzn(zfHMWrM
zi$-?X8V5R?*v1t=Yi4UHR^P&&=LAcwY@Qc<y3W39fk+2?2W2sCu#0K0(#f7R3Xz*^
zO*Bm0VmBNIvx_~C(k-{yr4(iBX210;`g+(K+#q>}y*V1pUiJaHx$m;8w?XnA`}a{Q
zEbU|edkWX2pFKqRk^y$yhw$P)JH#8JgKXE|;r9^xG-Wm)u&?A`^bgsV0J!#u?d}eR
zVRp?;csRn|(~H()_Un`i9cAzRAIKPcjsZW~IC~!(dJ}BJ*T9@)m%j}%#dgo4@6I`M
z*!1JMaJKJ<Q?8tq^rO3RHv9?=cg~koR_nouS_|ww9QjR*!jm(L&Xjs_W>CD<o3lR<
zEgz1L4C=m|)M}{vaXu}A!d}j~Fj(^EG}A$heVjcT!3^Lye#USEId}S?;0WU6_d#Yq
zXW2IxQ!r=nC}cu7CqDvcC};5o^o4O|z6t$s&c-x28o_yns(m6kUP5?yfRj!&08t#h
zFC2~L{7N~{7>=AmGqId^{)S{6XE}Y@;2>usr8MF>$F`%Dz{&j)B8js(!LvXQaqfg!
zcH(vP4u#iJIjcSgXd0)DKKXQ%lQ<g#&E(iVfQMNeE3NnnIBzFG<Tz(7MKOyxX_Of`
z!C6`YQo>Qc3+72qC-t4;>{<!T(;OWIeM>psbi%WYGkg)4XE>=B&^pVht%OhKINooh
zLcfBOIfc$jP5}kUt2iS+p;f~P3VVwI5C5h!8?_u$Dh7IqvveKwFLR`neyHQfJusFl
zoabokQO~K}1keUfsRtCUavCXBeT}nw6<UoP+sp92iDULhtC=&89<dhAa25P*<t(Pc
z>Nbv&)(-6)6RiQRa}Ff|vxB2`<iMvJ9DP4XC&xb=<R)i~ewbUF)??7<;yg*az}uV`
z=wwbe=aan<>EW1vLF+DO4`n;=adss`vX8T}5u~3}n*`SeI3f9P=02x<8h)lh&a?t3
z3~^4+z>pqr8rFgNkW+cl0q!GCJp&rUoch^tYJ|i62(8DQ0;-%J<*Zx-jWNzb`Vh=G
zXXYI+Cpb&?!O|p$;{`IsNg{P;?lW6p(2cwGbNK7dok2TG4{r4aDD2_NpF^J~_slI=
z@Zzqd2(&kM>yz}t^x@8;^X<M|_xE7QkISL7$6jtJ<&6BfsxP3pkE^AJIe=@p59~nh
z{DsgD;;tQo-hS>Me2`#nKh@)gaIYC563QL_8g|3Dt0|li&Rz966e75>w5^ZiX2b&X
z0N1pd(&tg!>GW-!Xzn!%tH*ISQuWzE?hFGI<GJf8<#mY5`2!@0`{hQMNap@a6(1?w
ze~&;UmCF-DFOB=*ZD1ee9&Z3Mle?t|tt_rQ3PZ}}X6}VT9(ONQ`Q&p`MqsaioB0e3
zISRR5RG3r5z56pv9Oqu8^?fn-wJ*Rd;lBMguupQ=Q3m%E_X;1QDCMdtHd4lYM0=}p
z?sxS2p5Z=C(Y3Q&1^rqT+#l-Es^q?-hQC$Zj2PIh;jZPOb)I{BIrJ`YU1%|R(ZRL+
z0?=CS>{d8@nfucaMC-UqDQ$R#8`A=`dTtMWj-r9Pnc}opxhb2#Y~prMe7Kpr=MT8n
z!Y!h$QY-gU+Q+nUSJ2L*o$C^Z)^+X|C-D1paQ}P>1H8dy)0};WJD(P3y<Ep^iizIk
zZW;#6J#N(<DE4uMw4)y2swm5JpPTsxT7z6Q9nE>bT^R!XVXny;eIwjYS3}`3w}m3Y
zqul?Fqi>AcOC?t0+?^?Kbb|XK#pouvK2*dx#Z9JC0%zWFy4PHIw;l7L;mYgUiRK>O
zQhE=0@}f6_>BXy{+r*pKIt(-)-cc%;^yM9*Jfk0P>3!JU%QI3~+n<+|0`K?p)+`1I
z=JhPVKtp(;RO=qfJKY6^FkWplFvEG<>7aE4?{nHLMDp7HaDX1*4bz4%j(3Hk>j!z?
zeF_rK3oC)$1l|O_TN8Q3HNZZ^J3=enBwl<oOeFIjNkI<t-oK8arSlY&{K()vLCKz@
zJXcB|Wb!^*5A#_(e~Q6o^D-kKlEVu*3%y)kMJK&5^LS-Xz+eGy*;BwS<OS8Bvxt{Z
z^^3=OE}sIXm>0JSFeiA5tzee$p7ey|Ngh8DXs39CZBRJPYx)o<rMwxm-7MpML?5%N
z;7zCVla)Lf1L{@0?Wu6BnwK;i!>!@{i~k$KXIXgHDYt%s$EM<ei@bAB1GJV`c@b#!
zyr|_sYvAQx2J<Sfg5qM=cn#Ar-bP;TU4S<6>{LD0%=?|vhAq5TD`BFQca+juH+ZY4
z%%GF!Oh*=P@?z-Yh_`sH)gWEGGe3hkZu7jGFs5!^C~mr$J-ijSVd4(&-^W1f=k*eE
zfTy8+<9*)Icvu?bJxO7;A>Q(baQgu-ovNoF@;><ql8<;ZX`4LETe%MgM|t^Aqcz6+
zIUPQY^A`O8g$dr!Cjgt|ZKo*Ll!LdG(qYd0Vk&xY;aAaO$(5h=B4ph7JGj7h=WqWT
z#DhPa2oWFt7x8HM^2@G6&yU};29kUEABLjOpWoC6gZuagXz~l-j|9NqK)y#Su0;?(
z>kAkR;|CnYu*3OhY4VETJ1$f0P$XX)0gVIv6I4tc#s7(7NYVTZTJ^{9ySKwcEPwkq
z7)2ugCf$06_^-%7lK9)`)=TCupu&;E{L}4FKf*sJ2T9@gHvuJ;{~Jv^Y5egU0L$XP
zr-c{Ue5Ww@o5O$FaSz;F{x2=S&g09+U@4#f!n@Eo#-GavOab5E3G71tZ&@%{%vWSW
z{{)}ii&hE$Ls~tb<OlUY;S}E<1NGB<Coh1N@}Hy+qm=P|s8XezUw#tfJ;N`cy5+O{
z+4NzCbA0<Y`q*_1pQi)&JpWoFU@q{N(fx6ezeNH|wfqmNVCfS78s%j#^ScBvQODm=
z1kh{z0DAv5@)vqQq=}yzW)@6;nO{w%du{xkwB%~%FQ7!lO}>VLzPI>eZ-8|1=Ox0z
zZ9ab`NH^b_4U``KY+7{O;m<9FdM|(e7LWn{tStO?_xbPAVdg>pgRtwc;5gw7cOUVa
zXqhm~x15LGC|^xcn=$?~AAyYXi>Cp4g8w%~+$Q;s%^2ns|9vs6dkT*40j8Ir=rGj1
z1$XZO+DCB32I4FDvI**bf<0=8>=jJ6;ez-JavLGJPf!~VLji(!9TX4_6ogPUR*>M>
zehhHGposPp!Ge7hv<(rw6AhR!fk!w%!v&_l023joF+ws@@RkAU2L%3fQ%4KRsM0q^
z;6asTv4Xs(A$d^nL=jNp1<g`mCJ2sDTs2Y9OZ%5Yg5|Sm&O9tw|0=ML2pYT5nIc$B
ztH@M=mj<9|0w4MsV!Gh3cfiaLT<ZkdQNczspDCE6Njh85Nvpsd!P-ASas~fUnm<pl
zHwGkMF!e6TF~RA37(}5Ul1ht<1PdupcwF%5ZYudJ7R1SceL`^QTU>+^LH9Sf&L;)s
z)$r+*;4vL+JuPUbV_>BM#oxI2WrDUrw8{m2R4H{v&`WphS;6zP!#gKPqPIeYfKM^d
zO2JIptyT#X6h5yOJaHW&HG=wVh@2O6d`NTV1wj)&moW39Admv!wE`!4UDpXtP#)=u
zz?Bj*^@8D7(AOYXPPM&P1)tqS-!;MfXEBN<L1H2LngtiA=BGvQ>Ig`y!1@{twh7Xg
zgR~2pwZQBU7->^<L$GWaL^=iYuA}9+C3r0WXkCITCb+i+eH5DM7KC&HyGQV48v5=C
zq<b-nUO_8;`R|?}<4N@O3AEQRn0~<*G%*bbtTZ#+7u?tdks-mlT%bG<<h%^>P%uuf
z`9}i#JQy4n{OAGo5y96l<06bX1ky!N92e|zg5rc=W)DOs1z*uw(kX$TJM^7}cUPh1
zA`GS)TUX(GZcuO&KHmxR?!s7lr+Ek)BG9)-n0pR=p2F!=d+jAu(Z%-`R*E6wBb=Xy
zJJ4778@)^YgnzBamDwwFJkt$De_<>|Z}tgyQ^q$ysH4KTKw<eBkRV~T7%=;VnRYlF
zEPT5iCPIXn6i*8k^5Xy+CY<vInBl^YB|wP~_VxigQfNI6azHp^1|*||Pg9&HTKL1~
zATh!lzR-&mzUz=fCQcaq39iXOVFjJziWi1%Mk_&B;}2&Nh1Yaw9TN8c07sLA*T;dD
zEL466$rNGMJgBD%|Dj!2nozm}*y%#$USMYkWwcv8DlC5vl9|FE|A(<;38j?0%N91$
z`YlKJ`0@8p%oTQTg=n5|;0`+Tg})xhV2%klQ$byU(2Evzg~FGpQnE-m(E+sM!g-%T
zuUN>t0hkj)MOda3Q`vI*wN49DKZL)fLM0VWlnL{wqO4r#K@o#9!h}$?&I-$^{^Fc)
z2Ia{sgv(xq*-D{}7Hn0*bu?L43qPefx<>fQdk{G<eBvG0s};6<0CGvlq1DM{A+kVt
zQiQ7KK&}XPIQ|FGdZB9xNQ2NV4lq}RmGo;}6JGxbGL6EU6Y!!**h?QVZ5CGgp|3?4
zOT`VXLLZvd+k~kt@UUIDbP>jKT^LTU(hi|`J=AXqgXp_lokAJ?AUB1J>6W`C?EVAH
zF5&1DZNF{{9R=vTBRrA=#a`hes#>`#{AC$r?g@YU8=!r{WO~I62>aGS|Guzk6wV9^
zU;YQ`L&BqUD*u5nstbJ&g|p~P%&;(W0O}*cwbS6?W1;LeL`H=NdLS|;T(1LjT$s0*
zrm{)lk^pp03DYPp>?}G&r)OM6MHH}b6Ycy4EqBqgv}*PcRnmd6J)$;BGkA%@N<q9u
zImh6ykLWcDhWLscufZoj(d~60dqu%%P~RuoMp@th(Y5#BQ=rKASule{W25w);{Bqk
z$LI_etzu(@p`s}Y_k@Y8PXIJr6voD2qD0=bL5vo?{0*2fqK%1gEmpLhB5!db8y#qf
z7iC?9!30rzE3gwqr_TWFkm#f9xOhpTNGcUf7HzOV{jg{wy^T^tEPCrYQbnbOfJqbm
z@BsShBDZ0TB15z*68f1U{WH+d5-o$LGqXj3G|(K;7u%tbD|%0iOOhv&(zZNbboN{5
z6^fpreQ}YfoARi~MX_yAFBVyrLGOfUic$$DMZygj%PG-IuYsI)h^Eo+TPphYO&BZ_
zz4ZjJ%SFj2(Ro(1m7dLWqP6tgR*0&z(5e*GP(f*x$gvOxt3|OYsGk=dpr_)3=n@sq
zUlje|gw`d|=qC`lEZRH@N9#mAof!5NQRi<^uNQeT(Yh*fbmfCy6MfqS(MC}+ktUIz
z_H@mnC+Xt1h<>5sqBc?AMPRp!^0er?F8Yo_R~@1)v{$$x`kLyzIz^HxSh^*WP`aT@
z<g^rEw?!iqPU{u9eFeR{BJq9b-4ikC;BcR4jpJ!(^ow4nu+4puUm?&2MbA<l(vWB$
z3*>>w`Y&J}ir%)O^+*&!tFd8GC!Gp;EPDGL40Kc!^*&r16ZyUcGA>G|(By<@5gmw_
z68*9o2A##H8sMReIExB*UB&-WO@^CzO^^elcNY(Bhl?KKDB3o9iSwv#!&@8~2pJ!-
zgF*(rV#9|Ze&Pw*=I#|M?n1<0eCQjHed5#4VGsf0-IP%e6d$OCYeC|dXeQh*R(gR1
zi_ernGDMu_0z;wV=~ZwoOq_C${wE_`yuSlZMTiR*gBvO4)?vH{#IjdmFiL!|3ax1I
z79++KBYyfdn1~hIRzM+6oZ^DMgW~`GLSMZ21ifez#OEqN62)N`FziF(eoBQWiN#cW
zk}RH0LG{DpMItC15kIkX8lJxtvFro5pDI2_<x^>513muf;%j@*$`H?@#lul?@i~kl
zQ~Z866tl!{e+PwZ@li?z=7_hfgJiCF!FCM$n7Cm-6bi)M+aOse{*lUQi^UT?P(LBI
z(oa|-Zlg@dY4OXIxE795@fxa)Did>t;P+YafAqpUC!T5tXoWbLDq5<=FU*3a8Zq-L
zm^d%K^C8UFilf({bxGVRh5BXjBc#Y?){BjYfYKoTn?AF3RXp%5)SJY09uR33hrR;R
zBHq6mBJJWUbaeN+LtIP&lMZn=MNw{ubAn*0Q~YQ;$W3t^t?F)xzkLQGUE<=mF|^xa
zUIk#f#nC?Sut&V+7({x-Wr=9r70W+F>z;TT6L$N=tArSRzc`9s8TZ8lYUmA$Z_>mz
zBo2EDm=DAb@6Q1GP`vOCym=&Uk)m^0{LBA<HX<(E4CZ5Ta5_Xr#YI;5G$w98572S(
zCA!xq#BYWIbW(ivJS3;Ym-Og!mQ>nc-bK>;DZpGMyPF~6A^BoI4DOLcQ#{L4^0*cj
zyd+A;Ah5k9u?lc~BvodJ`bt*jLex+4y&Y)&l3t2X?vtFSwN`*6kONDB67DSY1xZ%X
zW4vFo{w0V6OMX5N5+Zry7Er<^C%;8sgrva;OOcX|SD_Fs`Ev>)F_LFCVJxwd*dq?m
zILYi#bRLw<qZ=bZ^29jICrTt#Pku;}_AmO9Bv-#cU$VsKM|g2qvM>g%Ba$;8V}vP^
z6%-y$m3Y$(o+fFcnJG`QlxFFC$qahpj!7guFbgDa-NkSVCA{x|QY3j<NdGo_TrxoA
z0mYKnY431C!gvC$63OSZbvY@?rq2+Zl62C!jMI|-Pe4i~*QenZEtC97vu(M=_#8mb
zNP@j#{;cGC9z@Pb0%)aLA?c!`z)H#5+i<2z@@6FTswK+1uuvm$AE4*&yu|Yta4$%d
zR4a5*@?`=<Yb9y5U|y0;oPy|ONe-3X)k{36KCMBbiH4(BB|C<|Y?1^}z@u4G=?jGx
ziAy<{t&&reeQT3^SOJB0$;Rn$?S^DMl}~j_tW+6!Q<B~b;<zP|K7eSK<U%y`Z%b<F
zT69aY=snaUsiUJCcO=G-Fv4ERhVRh2E9u-1^Y<h(Kf`a=Cvi-o)h{{I29yCw@-|4`
zm&~Ls>7eBO7+?-bPV9o+2a<!?5P2w(UWPM|B;ri;4Lc;iQQB}s@(f+C$CC3G06Hqk
z>IWH<q=|q%F8S^Qh)hVv$8fnPB`a29gj13-Ia<!rSu*swNVi;o+pba{4f@=q-E>LZ
zrS*+4=pl8YM{SRES`F-aN;9{D=_OrASu}5{!|ij}^^q=Ug(Y8Uj6b-3(vR!F+$)vS
z`o>>+k~SNG(tIC)21&owKxDskA=P9BON9yWB1D=?>F-eKJ1Ss@Nq-)MUbxh04@iVG
z)d~_R{eo&(4oLrrg1=GH?Nl@qE&bGyg3cJ}jyRZ)mHtHa7jaTM)dL-rX49KGUaFw_
zfCTBs=U^gH+7ktsL()GMLqAzs;|ZS*OWSD9KO+6)0z^`zmv%!hRXW3jYnU#bm<EFx
z(w${cI4WIECkV5pK2!^mBlWDHd|j?Ifqv0E>GOZ0l`nl;1B1t;izz8qAl*Rwl0xY-
zlszw!CY*udacMdq3dPc&1du!-eXtU(5~=UAkUS}U3Q_f$r=(7eFn?P50mV>Dr7z5Y
zUYT^xEwsv|uTTQ_jP%AddjFl3e&PnF&PgA<1X3ZD(ax(<Iwu#RRnpaZh*nGObP&Hr
zDy8)1dFj7rVd8>xVIb^Yl={=Is#dy;4tHIWF7JTCW$6Z5Z`Vn8Q#AgH^bsABs+X<}
zLhG7z1;tbvrCh|Z9W$Gx5fTioS-R{LxGmC|beFbDM=6ljCcW?hE_b_hp#-4UrL$;#
z(jlEO0)-pWHd+_mly07dq1}>NCZW(JeKQGtebR!HApOz=%0CTAXKR3YUplQAtwCw~
z%K#ga9wtf01F482U=O8d&j9U_bm2E3!_plzPd=7@Ye3(q^w-~EcT9S=2+VQmmrO7x
zq^nE8oRq5R9OabsB2{L($g19jGp@2=iXgkm4%2pOk8JQ3EP2YZ-Uri5R@;J>x2*UD
zw0s;g5d+j$_P7zg`N`Nz(b_9pMR$w8te1X@eX@Tk<Q*s*qypR^*^vZ@?3cY?hfxH}
zzIMfR4v{5g!cwU0pFE(1$<p70i3r)zLr{;D710fRK=!{5=taraDdBdsYzGS>u`<U>
zsx*m{P0|J|UiKd?#1dqj5M0Yd*}PixCCgTR4gJHimu{f%h^&F46WOwp(Xf;w+ZGJH
zT$%WJc#$V-rZ;82?7|G#JtpJOyjmpt&l8r8%VtmrtXLK>8+s>X%0@6tWIhf`7M+yU
zN`QSzmO|e*IxU+*TzY1yY%84{DU)rdwS2kksTSBhBm4GwD4di1_#6}}WQN(0tdxCo
z5v?kj=zVxmE&J>sBrnL)C_`{j=Ah+otxS=D)+N~;+R0y*_0Vg#PR8X>$<Y<rG1^Af
z%SJaqu|YP&jxk-8N!{S^HJObf7mc#4WRNDAj8c)!vIR?^-y+Lvg@>)O1y#^%lb!ky
zq+J$Gk?ZTSZ4{H~klkO3)(zQnhcVtxSvoBhZ_4I%Lj9JkF^WoNyJSAJ!@Vu@dl}f>
zvRo>e=#hC+9{7%I6MamiS5`+szPqw`TC?4goulWsPd4usnEkRxSs(+l>g@o%FAJcv
z9)q$dipLGfu296}fz0q0%s-TUdl#)ovbX4^HZ1#*L;3O%S@8mJAIn?^VQ^HoTmZB&
z*>6-5GcNn}1t?C)Hc(0Qq)bBFgeln!ik3OcV<@BPD*v3~HXiZ<+STom=h4c-Q!f7l
zB3|+n6y)=k&!-Kik38WC^!dscUV?(3{5rj(9DC)z(w*-wSM0*j_Q_l5aAttKl?qY=
z<@adP4U%){C9_}dOA*Hd^3N+^H%jh&1=!JY$7b}!$meE(87tqC2kba`!w+!gp!^QS
zRO98J&cIj_<V%{+N|Z-0gWe(eZOX1DIppur<DV?w_Ac}f%loM;;)s0b4rrvvKcFCY
zs{DHjAg0OLndnQGuW*Kk8S=qb&^jtFEQVyJ{N9&nWyzfdP{@`$e*tEWyy*s*x$?jM
zg@<|awKQqw%eUWy`Z0OdpKzu??r5PC>4oy&Db!gcPax6b@)Q#ki{)-q>TyCYp((sX
z{^cZEC*|2{NS=}lz6SHO{B`<#aH+iR6O6Y^&ZYf9xqPJnB4^}2AsEtG`HGJrSt0*=
z61P>Q{Jpm!QY9~50khTepB;2;u15YcIecE8z7ZN1<c$k}c2WMG0nA!?K@&_|l1I{-
z__BPE@^*FdS@hn$B413=iL3I(OVM{t{x^js8s$QY<u=LrRH)o6KNt>?7WqcH7OnEX
zRza^#zK;SR?Q*|x3MF5cyL<)x4!Lm@+#7Ne1;jh$bN!)sQ_iKWz%6-$2SB^z{<P=0
zEq~7qFx~Q~{~*#Me_|foz9Sd<0<2d)pS}ooS3XX$vwQO27eJv;{?!_&_sf5x;O~I^
z0<ARf%Rg06{AE!7F-0YZ<o)!>JdpoOYw?G2;Ro>Ikv#k>kYV|pAE7uRpQ5GPWBF4T
zVRux1<Y$mE`43d^I4;kiQ;HMv$y-2~l=qv_nv&Pmqt99KCq;eT6h9w@g1dsB02B{J
zn}z;R*h{gF%5=OHr(<EsM}fLfya5z@cY^pU-tmX~`xHAiLnJ_fi5O3X;uuwG1u6dQ
z1@?Z$+gs2IRz&GRLKLUzFk7f1ftG_|ipuxU3Rh%*1<44-iU%N(ibc6VIiOfXbG;)<
zQAY*R(Td(^bjB!tn}ESsMG=*r$0?ql3DAQI0Y$Ro6}u@6lb}%3i!V_TF@=F1Qfz$+
zdP$1OQj95C@sI*1hZVp7iB_uO$IszKn&L?vP|_6=n)NajXX%#9QY@uaVYWl@9KCsR
z6su38nXCAclJI$ogLA>mSIm1Eo*q*?MfuzU#p3;77Amr&Kr2!_xdzzB70y)vEmmB9
zAFUILCBK7|C>m%>dr~n%`><1rKFTkiRy0!mRH@=C`iM!HBBTq@<qC)2LAZZLk$D!K
zXB9K^!9Ax~`y8C9P;6g>5mqW9zXe*AB8z6}YDEaWGHMjh(6u<P@TGa`f@0(_>|Rm~
zP}SOH#aRKEb&9l0Fn>i6JrnBnivOr&qCw%MhlNH(IPFB56k8lGg4?Vx6rtIpxaS8i
z?kK!|f%#s=wZ{;>tC)xb_C3YDY+QssMQa{F`xQY{hd7|f&4J#1#hgmC1{E&k_K;$J
zEm{v0uhKmCP%$kK79J^PQoYNtBK9)8A5oN&+m97#JX(K_Do%V3>@h{fDU4}cv4ma(
z6N;aYK+#$G=s&=?C|9JxuB-BuNGQ4~En#4~E9E{Q9?GCmDC|*YYarsOyh8OzUdmk?
z0PU@Oas^sG%3mwtny)gOGC_XIAG;yBSNX=9l>YWtw$rS)PpP0-RDkj$I?ouW^r1qR
zAf=k_mi@{@Jir7iSJU<;M7g~dtx)ArdT_#&KTkp-Txq9-MTGJt3Ux**Kd0c;0c98$
zC{aqceP~517o0>ZMw#dXy;$W&Op}h8amxE_fF4vnON+dCC7*7n1m$$v=q4)rcH*)f
zQm$B!Ymua^qqttOQq_YW=CJZ-+Q}SI7E<;jMLC0V;;G6PXFxqod4|^M=}OUe7*dAv
zBbq&qDqnaKn3>8V+Baq?8=eM=BU`!qS<oD1ECm8{mChUCX`V8awwU=!&+mYCO!<)V
zN(IVdiYFE-yUKuFr2Oju$Z_RmH`py!R@3|Ig!0S=sFx_W(RYqdD(e%Wa7y`aD43^}
zLo^4LDrf8hDN`P$9ap(S`7A|c&M1{s`E*v9JO`lXl;u=;SfSiOMY@&Bx0`@nrSx71
zjcTP+0hl$)aJt;*l`ARQU8^jj9Kj`J6(w&jE8nIiOr5f48WgT5_s~pSuY5qe$OfgF
z$^ow`|J;Y+UQ;^$phC??W&M9J(WJ}>0d}*}kp*UplKlnHT9xGtT<10=n-+&1O8E%-
zZYaO&gQK0w%`X7$rgBCf`fe#Nz6`g!l);~&)uRkw2$4HV_iv!ytE{8_U!U^UWib1d
z^JO3d%0C=C(K)0%T@7y@C|`aRt%u4jG<QEzws*ndVP)F~=o?X9dKs<9%Iz+|9#xif
z!L>1E7cINTl@(M<I-yj&1lJ~&@kgLAr940tSI(-B=<g9+RCd}|xT-o%LC;N<LI)Y$
zRSo~6_n)U~0|g+xRILS2^j5t|YZyOOX+ON!tJ<*}On=qjHt6qD)l%_5fa=pUC<LmG
zUx&dU)eom(X}_wCb{oN}sReK*MAgWJdZ?<MmTY0Fd6aPrS6z4qeG#hm7GOrIzHX=Z
z%K;T@8Jvnzi5~$wTBSiL?94b-G!rHcs#e*dAFpaw0{f6EhVJ|%6+(V^4pec^pzp9s
z`ZruVqS8NwR*LGEDL9j=DtQ_TX{y5CVJTguamJ7`R3G(1@~EoMhE}F3<yXo-WT`yX
z!&0`Y_ZmcVRLf{C%2j33)SsuiN+&q-RqK=BVWDbACHjg~JAZ_U<Eo`}TE0|O^8<!f
zrdqTZ>gB35s=Yg-I{Gx2XH}K7PB^F9bs2gUsv-K(D^<UJ1idQNW-2OnRI4&6g;k?^
za{!&^Rja)~E~uO&AQx3uXIQFLy}AbGFRAKsfqhxUj|Zt!ZF&sSpwdi($W_&9+SOfC
z-8%thqbh^m4o#}dJ+RxX3Z|fSi^_{CXj@gU{e-?Y)o>8ZcQ{n?de9rHHzIHmI#nE3
zh~89vOG~I*D#1eh6kV#jR9SOdl|ng@ZdKr6w0cx4W<m0<s+2zRdr!6HcMP;ob&paM
z{VHz?VGpR5EP}#)RS6T!LDeiZTpLnxYhmw!>NnaL467V+imHsLR(}HWShbGQ|D&om
zCxAAls-!1<T;+QV`V*?wLXb(7%fAqrQVs5e30Jk9%9q{L+i1>rSC8GsMetNNYtiSW
zzCs>)t2b4_pr5*71di@iZ>7wnzq*NsR-pP>2OTa8QVV-9rv2(Wlza_UAD)TMF!dVx
z?n$_M6NUZ`s9m$sic&A6S8TNUkUI<}s&yhL98xoHp_Qbb%0nwz{l{MrIjsIN1O6US
z&!#{^ih7WC@~P@#s(MRP|8@e*boKfW2WW;ml7di2)nC2^nM}3kI>=<HH&6*hwt6=m
z`pr?Z&cb}I`bi2t=c#MfK`&punf5Hl)IWX<g9Yl&Vwf*f*HVz9Nd2l13dhyEl)x-j
zw=6>Ig!-!`P$*Hmdcxn6>J(2ZzdWUW|6ORDR<}jL;WG6TiD;FpGl!vZM*WCl-)Gea
zo`+B8)Ej8FtWfWxgm9($r5Ql0Qir^Qt6r^6cEccQ)H%_RJg@$aB2yRC^^4)!MRmgx
zFl*JBu7JLzo}f=!URIyd((_lRp3H<dSJYMi!u(bB$Q8g`Q*WX;S)+Qy9VS}TuTvzv
zRh`}f$u@NoNp`3|qowr?^?a&W>{Q2`N9(5g$xqR`rS9DalrHsAipTe;zxo8^j#^LK
z^j`H3RGr?Zo<AKTj(+tjs`wvJKTqNL`)Ur=B@L>lEkfszx+50MN9xCs&=>|2WJJA`
z4wa3mFH*tFxLWfLBq!9(6L8I0<Bl=SbkWFuN1v-^v=okdXnvy)746Y9tp~KHroIC$
zFHO)Xpm;kp|0F=hN8`T_Bv8}x5S>AqY)YK(*UY0RZm?$A2;2|RJgWmURI`iLy<wUS
zOL2k2HTI3TvJskIN~=X`{3sG|K=av)xOh>T&_ifNYp#32nHbHSb?`7&6ZQuB;xxky
zICD_r@b>|Y*L-^l*a@276VREcxk_8&Lz>sADk@2n^d(FrYr3wY@33YgMHi1~Cf`C|
zissl}c#*0}YKEmW&BPOMG+m>d2}>E8SLtawswsXM(3zT03esn3-k$@#Y)y(5eL0#<
zj{RunYF?+*SDxmz7vW64W{3_J9@7k;1X_XS;Xa@hYBnE+7e$)PD40L4X*vdGv1Yg$
z>L)ZWl>)m2!-mL7&FUx6I;9z`0Lp1i)DAF9HGVX*GR^Wo&??uwt4HgM#!y1<zq1;H
zCz|IpLt!vjq50}2WGXdjWnflmQhorlTJw-{ur->y!SMUM=5I=_U(l?hqqG+_9#nZ%
ztEr}NWSu6G@-0_1#S|5(*OV3m<(g(P5X?r+YO0xN((LGf+pU_&m9+nB)BLa-itU=6
zVsLM0QlAG}r{;_vc5i9|YhduUCYCnA-5M1aUi4_@ZUE>VjV%Zwy_z3rUcRe&m7eW;
znw+;F(x<7UU1Y!J6lLQFG_`am+}Ai>#ZNJ)d2c@S9%z2<n}g@?q2^mk**(%YZ-?Ds
zP0~i_k7&Z)fx*X`aQbNHs76A$f-%j`*U&evS@$cL6Pk+_T!cxDh<=|b%?1j7Icrzs
zqt8X#*axPo_Gx-8xM}}64dSk?qm6-wcE(=x?a^|maM9tZUHAX9wKk8cR=u@xd^qEy
zO=kn!R~u9grk}Qz2lIQiO>}s|U;7*%uI<xqKL|?!+PS|%GEkck3uch^MG8dh*Z#d6
zlEK<vUjs8ldo30yp;{>gMZ>g4N`!@LtB=5$2#3~Z7Gxr|e=UKF2eg?5FdwD8Pf3_)
z?XHXPG)B9c4rIk@nPrfS(=sTneNcPR6@BqqK7H&WLEA}neTmxQdSD;YMr{OklD4n_
zBw5=_t{v7s9Ha+F+j|R!QnZ`tt)HrOG}45TrroFjN!P|y0y{&y`D?%&)m|NkGnv{=
zcVIqC`<V<H+1k3TK+Dlyqisg6Ry7SGdD>+ma3)_{`65J)X;rkmD$okcVX07i)r!6%
z?ekq=9@p+X3}&&m=Pk5OXv-b+ZM_n$|5~_zQhS0TAE&feX$f^&yTT8OrP^(@j4jhf
zP<d0iHiW{jXSCaApmkRJh|V;e(>7CNxk9^{gI1;XjTKO+(mtkra<w)q5@V^++UX8F
zuPvvy*#&KH5TGw=KYxv$zsp)f6u5QT|E)sninf;m#r4|NccI^){fmm_uWIj69WV~N
z?*?|GHu!0vHEAcmM_;p6PpQ}z?cO+yzEwMqiYD5$Vb4OLUAr+4K3&)L?SNi~HuN*t
zy`gQL3k#jvY94(o^rrS*3L@XqhSBS{OZ%e-6mM%iq-b?(v;KrekM>VmOyALZ`~VZZ
z+VQ_(_pWx)L0Gz{ePaVe`m_PxL8M=+qB!#a#tX^&+BbH9IjH@Sj=v3Q&(VALfp(Z)
z#t*eGVQuM{`AGY;A7qBLtDZsUh*tXo$YX6y8}vuDF1sK)rWMl)dtAGnPRdPaoh-Pd
zliEd8p);jTyAEt;T@(jQ7v1QO7@E88RZ6LN=r)SL+@qVi1>&ju-!d@0bO*_vw{DaR
zJ%^8O;YV=TS64C%GJd*@C~)`cBI#-N*JXYVw0*jZx4{h1b(Vkx>O_mc4AM1G+GM|u
zMG>N4-TQW2=Mddg6)s+=PEYCZFkJ}+`NMUuEX9x_bbo&i3z0g@7+ME(RaqcW4xN^2
zy`ptBTcH@Ei!(tZR%c6vi8!4<Mg9-!qN#!_UKdRI3A*3b!nH)*R?4g%()qrQz9iiT
z{rCx!b*CDEa#$z+49p|Cf383>MVGxE&ZO$XccCv$S5Nm^x~_)<g$$izQ6Wqm)x~at
zH<`NhY{=y3xO8$RSLZ`9=sex8*U`$?C6V99bT?h$VS#RcI$#QQ+vY%_NN0N<t>e1f
zzX4VZFeseRbx<g)L{~t2rPI30^oW(}9z6mn(>0I7r?a|fM<-02(>;*`nF`$%y5*~N
zGOFjQ(Ve9T;CbC{+E&%-c2E%Ok}iYFelF{lzX8&uOQ1UKW}Rme6k2q%vjNtsd;S^}
z+H{r6;cvSxcOyLjx@mOEqeFL;-W)e{T?(jo>fUH`K<1_{o2I*4x>YM7)1_Ol0=cdG
ztOPRMx?6PGu}9ZRVZ}Q--%|AT>hhVedsp{)6V&hNewJcPeY#cjaqxa!=Y5zT&_z&U
z=)P_d6?YBl5~(nDNY_pgtp~b-8c06Wd3Vy+`yT0XWPlmgt)M0Dn2td=;<zrb6fzUK
z#X>kdsr!dY5~g$)aslJ4AKnd67yXRW=yTP}Lg3RLeJ;I@JoRz!LC;H{>I)HX{oj{B
zeDv<G0oqp|I)&fPPoK6PdVBTPH__L__UWHlht2@~E;<Sys8^nXOpv}T1u*;d`&iHq
z)<+ehFGT<H0ayyvpDc$+nBL_r^o8qH--1Nyk5jSK0ex`_JdDyybATDG|CdTjWAwY*
zae?CWtrUnjsP`EMiPx{B9i}5uzw!u%c1XX6@|H>Z(>%Z&)?e@h%n^O18?H=>zG5{<
zs(z4;j-~0BcB6Gv-@6R0O#NAk!e;63({epquT+AWqhBS3NUr`(dQ|fCV=2JQ*T35h
z$z%Fw`p_!UN4H~u#~15^uS2w0zx_psp3pzH0i;B~`UsdO_4~qJ@WW?q7(c?9a=oJq
zqd24gcnA8<>brIT?VP@KE&3|-Ydc}LQvbsb7(|tRl>DvMZ(WViU(he76w*a~(qWKV
z{THu+c}c%p3-!x-0TsN|>EEMx-W9#F5X^f0dKJ_g^vxf_m#g~E9oImw>A&0p(MEl0
zK02HA7sg?*MW0JIX{-LkE|50;^f`cO*AJvX<huUJ4zxP-J+!{Rp<mDn?>qHJJ>cO@
zy@U@-xAcGYgW0A3q!1#v_3tJ^uUlVCUjymU@Bb6bJNl{!+N1UAPtb9VyLxXb4!ftn
zME`8ir_c9?PyPCHF(8Bbga(iy{R1%+9_Swi!u+uQr)eM~dKZM-W<J)>UIH=-gCJx2
zfj7}NuK!33y(zuRUx0Qttoj^%E{2bvzyRG0d7EjE=5ClniwF-xH*M4R7;e%n<Z0OU
zJ6c|bYz92_HW+RJ#>XI{_r0&-6?*0P8AfRxxYrO)hv@<g3W`Gp8g^3Ec#vVn4v_tZ
zh==eZ*sztdwIPPpCZL2Gc2S}-%<$=5dPjvDN@#@~VOU7J$w&jACgcN#ZU<zd3<Fft
z9c^&-r+eMNW<fvJux}XGInLlY2MPxbzuku2cthz<j48noy%r?dkWIxYhYgG9NZ=8}
z?)wl)F@#c>EY;vv4)rv{AO$BJ>4vY)fSX}hxDtv-4IhVrWEw`O&OFQDRtm*z!>o3o
z<rx0-fx%ouSR+WD;f>iK`G(gsAacwQLi^kTgBP81FElJ~fkKgi>kJde4XbD&Rc!c(
zPV%2H4E%<^5`#GmdM6zQ)?Cn2h7WRJ@U$U~i_w=F<j-KBWd;ZBS;`IFawwiLFv<aQ
z*6<4zr<^k!r3FHTA@KtktTfD?je%Af?q3C|HgwTqsm8FFzT$P>V4%3o1;ZLTb$ijU
zg_3%;hUb#u+9iXdj;4>x1{S4H>I~D$K&}|J)6`OLc!kn{4F=B&4D_mDPYGJr41*Mi
zZ!}ofq19ygm>g|3T%d$-i-Ap3N~<A;B5`eo=5{dK4GU?Tecdog@w^Vh_f(&B!|;I8
zVVwp~$4zj%437h#c-!DJ51rixm+!#rF$4-AbI0)J8|dpb)Rh7Bt|1<Ug){FNCMj>x
zXK1*Bf%Y3JzlEg%!$va(df$*i$I%82TdCA*$WTB}#RJ2<1@L#+V0s0TBZiAz=zDC~
zQtN>GqlQ8<KW6Z!UFf*s2Gv(g82qV5Wzw*jl7dr)dGt90XXD$HbaFAiOkosP<CQds
zxETw)&~i7r7DCU{`2Gqoy^O=LQ1CX+r}6q23;bch*SM7r5kKQ+40y5E_|#Jrqx3h<
zp;Ewo#&6~VCcvoR!>2&w!nv>%WZX=*?tY`;6~F`=Uu=X(h>;<ONT_i-1p>p2J!(jX
z8{O;B7hzPt4TVT!9951SFa|sigHgu!u^gNkZEU2~Rg5wJd4L@>ZcU$t=P%yaL{n*k
zG3qIxB^r;^K<1F~L=Uc4l5u?yMxSgn(L(#MF_50WBgQqaLnOucPBySpjZX=|OfyPo
z5=l39^C6jGWKuvN)7Y{Ltt{gV+C^p?18E(XV@y;7I@idi8dyi3vFAT@<{M3QAjgdB
ztpF`B_Dq9fp|PPHJ{1{n?|{J*#?SA=(Guf7wP2n!&h<vC)Ob+@QfAysQLA#}ZY2hK
z#whH9iL*wJ6=<C^%Km=^WQ+@gNTsoif>%|>fio~v9Tpul{b`4qVjAa->)!y>1>-8(
zBwsWxpqrxBxcD%{FBw<SL9xrmCx3_SI^(+=0er={;d%7c8!KK#UxTsvAP}z_f9nRy
zHRFke=xa1~zKyHXWW2o;7MhLWn=z0UW9mzQZZ&Et>(*vG>-Zktwi|c-3A@*g5pn43
zFs{!9+6|+GR>_^lae9N_G;VSSxn;cYFU;RIdNQHcZJgQz>>lIhCD6NLl+c^B*Z4D?
z<-BVQqb&bDW660i`-}zwyze)jvx7Nc-1;)~?i&rSQ=#&pv6jMrL&k7aPRx8@EFkjG
z7^{O9kBlWu3})CEm<iAk<40p?JvPSB_HxuXR1cUjWBLF<$Bk(kFei+vFj$&2j$H=y
zlrfY8N1aWN0>N}K?ec)6tEq#24mXqQHQFe-n|`PUwufoP0Ita%Q`=>9dYaDv3gTrt
zn+H&DlQ{-0AJe@TAmVHCrB$P!$(2r8?lrwY@d|&_e?<`4XIeuyQ-Em}<zoU(D{18(
zWXhtj?tW7{9WxC!ZBGVfh{+4V6UWR@(+iZR3p24Ypb>6rz69(DQ+qH*A8B%?=<os4
zp*RdC%CwALh0&%|iqyrJUZX5ltf^`}E=in8NORRe(?@Rjnc_`fhu|6}n2xa^l4x?F
zQ|5<Ed#0l=$#m!jB$G|qad6FX*i^X{phrv_EHId2T1>xTs_8*Jm}#bHyeDU-n~J`H
zVus1b2y)cqGz_#%(-KegWtqAnVLscW`UQPCCfNwEb4~tKq;SkMz5|j4CgCuk3r&HC
z09|DIks?UPO>W&#D0Y|@QOV#5Q+YoIT4Gw+4~>&1C2e0$nfz)0f7<jFO_imlw?0Ly
z%yjBH6w6JQB4PfFiJJ_`v!?GOp?=O3vJ%)8rf(>DS7|y!)!J32b5!tDZTjCD_*7#m
ziU2upx_Am^FPI#boj|*2@^}(3wWeCye_S&COh4CU(}PkNtTRP<qVI}ndk2{HCXE)%
z2Ghq>#C6rQyaooZnQAl8*J!fSbK7K!iN`>jO<z6+v&D2X6s=a%Yve_nDZ2%v-Q+ET
zhu2L<{{LUSI!qP6!_yn4<Mhe1PSbb40raM+@K3aEnO0;#zsvL;Z2)eYR(qqb+w|rC
zzo$&o;vjOzv@;JPy`~@k1<GBMxDc&-rUUz7sn4|TM_l}VQ|fv6J79{Of`|7_^XVoV
zG!;Ehi@+h%6I6ivz!Y~EXb(+Gj$yoyOfU8TX4o`LXW>Rnc`rlcvB~QK%#WJhybWi@
zOdfRnX52JD;n@jO@`o@nY1&RD_ERQ53V1u4#YynO#r)TA0CP1<|3aUexrU;%?&euM
zD%A2cznc#kFZ1GeLA=estKqPZ`7a-M;cK3`6CV1R6X%1u&pg*3`T=G=&6a`Y6?C#E
z*!=EK@F~RH_&z{G&7+sV3^Tu`0|__(R|sZ=dDj0xBF%5Sg0UPhU-<yeM42}(pyw~z
zeE0!GW6Wi{ArotEp<>r~bKW7CNHE8HK{U~va0(_4nLFtYPBJG@IYY9!k3w`Q<~-Uj
zrJ83i2TGbb?lbfqHP7h=Gt(ST`-d#E-3I7f^9X%WHP1Y;9ANq81*s5m95a7Fi|qn)
z3B`2_&7ud8DKghlp#Qk}Gb+C-HeaUb#R;=H0x%`!V)}U2N%I-XEtQ&`DOOcxK3su|
zS8ks14iwIreSQV0F#9!tRGLi`0IoJmXaiki-s%Cn=gt4S0rd+G^FI1|>P2%OZTD);
z^QpM$lKBo*r(ZVzNISwh^EY~2wkzh>1z^^jbItJLs<~k+Zh>p&sZ|hZG;b6Et;r0p
zap#+(C_L0+t{j41tJ%LA9=4f1>LJo@-axhH*Uf7v)YWNr9NP%<H_eh-jPRCuG661j
znWxbmc-!nu6$stt1R+H3nCDQsq1U`O7y5V2Uw(}--7|O4fww;MYkDyI&3^>KwE=TJ
zo$k1A4y4k7L31O$iHFSpUV$?Y%%3Ep_0T+Ng~%gwo`V8H!)De3G)K&$JfMx5^|U)4
zGndeIV%%(^>2kuH6#(X>`M^tXZOZKZ3ly9!|4<pCi)A4NNL(#D>D-!|<rrN<cgt5)
zvgcuWpHlyOEL)d=cv_Cr#=*<-R5D!iwYXMOpwQ29>3ul0*AjReFaZ_@rM3etVd1bF
zWZ9Df#r+ly71RV<Dkw`CVre#^6>ix(3781W?>e+1Eh`4mcfevEf@@Kh7n7kLZE;?T
zD-&ahc0eT7(xin#oaJFE%pSDtUPgt=@s`w+a4Ny_;d+on%as}M;*jMb?HZFTidjHQ
zw!9jRzQY!KJo=7UrsV=H&0?bjce=$Z9alZWa@P)W)DlmpI5RB^D6*JkNxK7*Yx$X?
zOL>+%r-71h`Hbp93oQrn8g$Govb@&|Z;o3^=D}dG<rgY?J7L+*g^3c&dnSOMv}C>y
z{Zp1IO0S%@%%ejwr51ZQ`pPT^LeMI=ygV1`XDrYD2lca-ziGBTXYuZZ!3s;#JXol-
zOpkzim1P?xNvkb8DFW-Lv84S1?DLj28lYXUJhKgG7cG(R0Ik+CooW>>S=wncblLL1
zt7z3(R?&vG!7{QIl2<Lp`xwkMODe_R8ZC?e1hdKV&<B#umPY~jMOrL>eguV9%XA7W
zwOInJ0Bg6*rK^42VQHxXx5F}@uHFsHqiay?wD=j(dDC*+4`{b6-_vB$Wts6MByU@K
z>d@-8G@e7N#}ZkKQQWbVJd0uXT2|r<oHOrQq)%Z;_bi#gX!Tis&4FaUrJQcW0m~7Z
z7zZuOo<`r0#o^ur(Fd0HEr5AwanA>NWVue;)M3jys;C*UyuKD1k1eNkXpLDe*+IrF
zi~fWDghewG3X_)aD6KMu@2A0%vvtu|V7gdq-h!T+^#aW$?$!s#(dS|PWDmU9V{N3b
zL3vuO4$AKMSdWLG>1#FFA?jysqb1*7YbzDU`&*~eDtn)G(_<J6uwK85zCi12Dw_<l
z)>1Tlzcuh5FoUfxQiLPK`fN5ZL#_Qzzznl~NJYKj)`L`H7-6lU6LOK(Lzgh>16Iar
z3KT|Juh0w?ZLR+TS3So1XAwxO_0KTq$63AH;L|}XLk!S(>nBT~pI~jKa7&_f8^z5J
zSxag1O0tUbfs$<fFBjynbt8QZ^oUik5*AXdyNlsrx;2<`v>8@sXFwmd{`Letf0@>v
zXf(5|BMTstZDmtsS)Nr(w{E_5*KM?pS(}fcufV#(0`rB|cTd5YBI^!1IDOn2K`Xan
zYve{SPgrl$EMH=MNNc8(*574dp0Yld4i8JMnH0+?vpzcqnB`XcF*<X9#@g!w?pf;{
z4~U+#ZaD%{VO4$%^Oe>`v@@%=rchR?#`??&NS?PgQL5;IRWHIoFIu&?pipa__XI>P
zS&K`+ylnMf0+BkagrYT9tV>yF)mzI0F^C51#BB`Xs`V>MjykSccb>zAYP8mE#)WFK
z?xsSoX6vax&}y;XI0?{J>sxfUv{?u4K(XCAlM48*TN|^W*J1sJ3gT{9b2YHkX)UEv
z&@Sr-G?Cx7zTpLhZtK2P0J~!~Qn^X5wU#PD?^?gt!~8vmwTE^Meb$+jQ0cdJY=^-C
z>%e7T-?z@q1n8hOe*;8@tfOn8|G@eLMSC7vZ#qC8S@Y?@%!sw<Aru~4f2FtZsC91^
z^v0~)c^LM%)pI>WCas^-IH#<0>1T4brDwvti_M{Az&BT070s{iwzM12_pp^ELS~Px
zgErEhw%+-$<Ymhcpyh1~3V@`K&F~*uzP67VAn9j&f$r74wl%%*(BGC!Q_?=$E!w{Y
z*k1h>eSx+~+PDSToWF#~ep@$%s)KFcId~Xvh|NJky-*vM)*z8KQwzue+xh^IDBC)k
zU!!fko)C$#F}{a>tgV$2>v6U(Df)5H_H8)&;%)mBFqmMQdm2MJWIIClMUpM}A4n$K
zqRQaKVO#HJNFK3e(6%_mmXt~d<x*|8YB0hyn{+AA(ruwnLO;Vcnh5imws08~vux6X
zAlWw7B3#5ATlQ*5=GrE{09u~S7>B-m+ZH-gbIkUAHd+O?OY~?L+HxqiR%ENEVyY9i
zHR~Z#VjH8M;-qcQSz3RdvaO+mFQ;w4ghR2^wt@DKWwxCb=$G5_cVYBrY!+HTp0yQj
zhuw3w14dkg3S01JXjR&_)9I`#+r}h_RNHP->06C$J}sTj+vc>Qb;0I246uu~&uM{B
zYb&E2^(9*{HaU)&mu;Pwp<ic9Q9|^JO}quz^|qt*9&4~Y*9sF?ZGo#muGxfCG}>qz
zr7U!l?d1>QXtV9ehX8G{&7eZ`R$DpUxz}w6|3zPiZ7!9R+^|_`f8J^P{3fpYO`HEi
z^xd-MF)`c^x^O4qI^VV({~Ds*w)#xy_t@TE1kpRTZ)g$TYkNd%pS!j*VXG7HZG-L}
zC=S@{^FZ#~^wU5FZN{}2#E|VEMfx7t=0!u{q3voLP#)RV&w+(u+sEYnh%J$}h>vaI
z9M~JRjopCvW40RFLyy}$&p~9u7DCyAN!yKhFsE!k%>cBs{o|K_;$r{Bu>cyb_Qdx9
z<7U77JGk!lx9LEWhrNiB_IvCvP+Zm9KE#5gkKI7;Az%B495DUttEq5luRVfpQh$5u
z2>jh=_ZY??0_<n=&<eC)qE}>){YU^>`|TUYVIkQ5!38iw>~B2pfH$Fb2fc8^?BVa=
z0)^Xiwt*R8&)W?WX|G=bO9$+CWw_2!_A+{xN849y0yD-wpCX#E_AW|$#o6c3^7Ekm
zBt@R$?XD-$O0a+81Ia{tOgXN_A^Ywp(MqyEOI{?~pWQ^crNed&&C*Bg&;A9Nbo*;Y
zv@+~X{{rTyy?z-y&9tXyVN6-}Z69Nx+4hSy@HfZ)(L9VP*ZyQbu=DKyTt(}c{U19_
z6xbiMK(EkVupN3u_O0}Y9k;u81G?DWvl{9r?A+ya%a+*74d9-%e-RCG%DzAcjnj6I
zZ=hdl-%78OGJ6Dt&&%z(KcMfN{lX<ME9|z5XjR(Xx4>?V{ca1qIBzeZwdn=>M!KCZ
z*}YD}(q%hy6%^|1pSc00!Tu+O_O9BKVIHpx`>qIRG}`OyK$`5C=P|-&`<A<qX}3R5
z>BZ~zUJlSY>~9u;+_2w!7k!;}A30h#?aOGjf6KmpDfGJR=c#Jtw!NE{H{Evb^YE$1
zK1vzWJ9bY>Hul=9i*RA@+Ic;Yyyvhlq-)t{XYGQeemmn!fDYIr*22Vn`ynb^8niDs
zgVvCJ<qBAOU|&XA;D`2N59mFz_wNRC*uJJ3mPYKiXrcVrUNi|ZYJW2xKl7M<8<iuB
z+h2JJ7AEYw&VV^-f6oHUDZ67il?OOGP4k6a7pIdHBy@Eud=bRWX$e&&xjVfc4}DLk
zc|kDf<#h8mnD=(NB*Z9uoTez};p-Iq0nq%MexAUv_d2!Hde`6Ss~#}-IW2eyumGob
z(xD#cv~DZ(f}HkJZg;=ayN-3B!A>#?|AaWbLQ9!YC#Rjz4|6h8m0Y;f8cK3TIOWn7
zGt%i`99jpQn(6yUQBLvS!C<u0Fr|uOoPMChT&&Y8uCN>Dw5A0j2c5#s0wvz*axp9<
zIQee_Np!03hoM7Gi`?kFo8+{P&Wa>ErPJpDQ=Gn{w0El0+?N28=HxXU8tG0c|DcuO
zR8IH$QK#fWFtePJ=`47*)A7YX$#L?p#8`5jniC+B=QK>YhXSW{Pk|IV@i)PlBB%G-
zpm5x2({pGQJ7uvcZhpe)zj|;>oNScTJ?Rws5ZI@j^#6ic{(m&R2Urx>_df2->@Mt5
z7ItQ~u&^dZqe+Y=F~&4oOpGnId}7q7v1^*ff`XbXy+{>ML`0;BGywqt=@w9=2o?kZ
z=_(*77R3I4PrkqZ^YC!E_n!BhbMMa1oO{l>gZ)lQr<T~?Ek~=={!JOAU9ewDzW7D^
zQVJWD*^hFAv`hAyB(Rj*zomyU74~yeF^Nk1Xewa1Y_FIJQf>c)qBu47H|apq75i22
z<4{{@KX(`mzHa}{5cJmCn_oxkhP~wuNUO82rz@e}evLO;H|@*m99Dz<KWo6*WS>U6
zn_Kp~D3{%A|E(6S7W-ZFt!lLo`4pPk>|H2D+irjBGHmL!&kV;h-?sN20&>SbfT}l)
zckLgI#w@z*5sbl?#Qr$d5%t(h&p_cb`&?SRSN6e4V0mNjy9UH%$A@~zcHi+sF92RU
zHZBFgXU96ab^Gs_vj{9lcWCOcBuP7l)j)mPj$ss$%G`163|Mk@6i!5E-i{gTFwa8c
zj+#8o>CBGpw5u!GF~c6c<vWr+Af{o*_!SuI+A(D!41TmjVT-XBI~LMs;JP!2cA=g-
zH>ASQfSu>hLt)rX@f=9h&SDPmgq>cIXr06hn4msy=dK|Tc7Ere2=y0tjvWV<>Yc`W
zbYAZI&I#+l6W~yyf{Jj5qWw@9<FNH>$Uf<C|4(#gIaIV`+Jz4MGKjh8@LLtesvQ>7
z7UHJE=3QXvaHyez`@0VBYhhZyL-}7&G3a3b32-kR+)ZJOi{q@znCD){FTBv{=lGS8
z0^323?@=-Gen&Y=>K%jJfRA-N|0P)C9p6?!Q?eu14bD`@YxGS`cl2-u=PAdtbic`R
z)O7-o?fB3NV>ymXlYuL6Jeq-4p`+|BY$|pPrLv7Pj*r|icGl6Z737>_{2B@wo_8$%
z2ey?sDs>>GjtT9wLXPWbS61d|N&f?&+;Q+9ASxUarlPabarIW%ROPsYc5Ig&H_{ir
z#_{w3thnO1XavTtI=-a9$u-9bt6*WRV<|Z_HypJTU8r-EQP!^BaZD?@Y;BGoRYGW|
zqb))JL!|gQ$DjrYG8hL6a9(G6$X&d_#4Ujd^~?k#BsMUAybDkh^QVXzG&7T}(Q0LK
z1jz4XoYd&-W3=gjKV>Z2Fy_Rr?FI2>V|PMI5PJy~#83wP>iP+==AG_Tw1;on0#zgC
zpMtgTULnVFWIToYzHp=6*_Rb#F#1*aI7t6G>^J<Lc)*C!N!66ZoE-53R%*({?;vez
z^b1J%Ca4!Z(;V*t`)v+Yntr!yG5V(;=YjqHXf2(snGt&nOfw7U>o?1u?oYGh&VhAK
za}chHAEbTgnfsswf6u!>2Po%z7%-~^edPKtG}6lb=ve@s|NTPIq@NayfI*9DmO$pu
z0aRMJ_&d5kEGc;d2}{er$KSu4j069&({#}om#>$Bb;a!v2>msKjv=qq=0eTtS9JGZ
z^JyGbYwa{O0P9BkV|0DsD+t;!Y$*QTXyOS4dzMq_hC3rX003DDN~3!+T^(TXV$7&c
z)tf2Eh2FhP5k1L#7{B)+!k4KYpuD{wbL78w(l9H-0Bm7AsA~2;Bbx`{1E!enpU;_M
zs(60EOd>zcojvvehzGl^k2JAMim{kpY}21m;mvl_mARK~dJHK(>~o6H`Lc4VF!f`X
z)nM@tv;U(sSp=I*A=__`vpTvF#j{(-KvM#1Ll1#O)^RSRC9z#}njx8$Spax~El7s!
z6jq?nKq_nI2bMIpEp$r?Gt9V_;z-%-T&ms8VGHRX+bOP*A}Lv1-5na^zN0W@4p;pM
z`c89e=-fjtH{TJQd7OeWvH4snWoinzwNzPJ$n|8v`XX+{R!Ax4&a8&^Gu*f#z@6m=
zZ6M_w=ehuZ^V~Ay6wngxeIM9c%8eQYo(tSII-PcrySE9gGVV2{OfGSY1*}Cm=l2ar
z1=mR_*h(&>0Sc?QX_KJoGAGG{q19Z}LcnXd#QD&4h5P<30IqT$(OvKww}%o%*SXDf
zP_UMJHkbBiH@IDN0<DgFN*6~x_b(+~Z*u#;2BLv`<O<eC?sM8=H*u$CLd7jEjlN>d
z+$K6g*}~oSfu>e&7hPv<-04$L(ax<j1?k}C-Gr1*E{ZnAx48}1(YnJOG=aXmobo3M
zy>xLl^u_GvynTW1;WpCK>K?azHH7wZH@*R|k9$IS%=_Fpsy}(a-J>mBKUe%77U3cH
zfXdb$anXOF^D$T814Ey1i~E2Z;5<fP>?v1736Mc<?_r33#tnH2eb2dnizGu-(ifbW
z4q}`nuUBF+&XS9vQE8}4dNdA*Oi4#O5T_)e^+04vK6r@EY{@4lpdv?-LEpX0l9lu#
zl4{A28_-lEiMs&KD-yQ~kVeUPs-S3+94H58r=({e$ZbiR2tb#_&K7FBB|F{)&QtoF
zLQG!LnMYx^w{*SH0)xJIk2Dt1Pg=GYz5ddTJ77$J)L|SZ8j1g#2gGTqCv9nRr2-XO
z<Vhpw%a|`MD+9bhdX9X!LTL|0eu|_zx-5&O#Z=jLM!KgKt#i^H@4>?J(ihI?ERimw
zI;v9Xu=%vVx*)Zz$KXZjU?23BNv)Sa?<MIw6mGvIYoKX2%N%Baw8$bNL0V-aM*-g^
zi>60OyUbY&(jkj(1E5nD^bvh9GUh2P9FYAb!Ppzw2HGt-nbhV2?rgH;8mw?Jk^7K;
z=VRhabMiGg=Z{`LlPjZOjK9ezKS4#HNyC4sU6VAb{|Yi0T8xzqF`3d1G5bwK+CCgG
zSxv<-p(fu@0b{ty2b(|+o4lrAScJ)K7myf}SrppJG+9Qwyi+EhZwARSIfz<Aqcq!O
zeGV<Ki7CDKA<yLBDHzN*Iq^BxqQGR;6xdy8@;MzpDl!SQMeBme2=c5hnoOiCzs%&I
z2LP8$8oxwmxk>e1NU1dGqmQu4q;V!@f5T*@HO#Iv(NM`ny~&wM*mTq697R5jjV2er
z0lvv3ot)fTCU>ZEq}k+65M;NS4Bm%nZ6+Nl=<G0ALzTy!ChyU`<c>*v8US}qY%YPN
z+r*vx_j@J{lz{9ti6S?m&*U8~tZ*?supHJOG#xVlT$t(M8gw2qm4-llxY2at1qeNC
znqyDvW$G6JF-J^KQpPjV)V>p}M@?hx!4hM7>N;e{nl@3v$}!Wq6iSaX4W@WOylK}q
zkOb3@MnOuV>DV4fNiwaR4bEg!&1^_HW%@qtYO_qc=0S9hsZAb?Ic@rVZy|){n*Kyd
z$~;q!o_qzSno{r-nx-dUtjIKhw(rHJqv(!$#?-|To##v?*CFk^=}Pi<N=%Q1?#aZL
z*@h0fSD0pHLRh6~I|cu$OkLKY)n!^j+p})d|53F4o@p;_8+uL6a%i1Q(<?#lo9?7X
zRKMv?I_&k(G^-q(k4-nwjp>Q$J__}`HjSak<r~v}3Ozc>hns@aS-y_`r-zGtm65`X
zuJR@;h;fsj+zqqc<^R&1)I<Kx0LDD!b`;a{lK)9Xdx3K6HDK8%pGx1mV0lzCa3S(3
zi$M;^t;zKZmG7hdXR7=(?RL`Srt}m`mp9U$Izz6Z@}f-nOE<Jm$^U2~M3#I5J$<v~
z*0lIJ@~I72%G2`pb70Mt+fpzqPri_z+WGRhGav=>==(6gP=23wCPnh7KL9V5^KibT
zXXI<h8$T-_ollD{_n{5odHDglua?NYCqQ(my!SB1F395|$XUE7=jKCGnS8}+uwIhS
zrAx0|o-qrgLheiH{3`jW8(_ICzy1=_u9m07L0XM`J=JMnk^5~1=T-S99_YL#-=+cQ
zb@@2@uxsUMEg*IBc|U`*US2|b+ne%hl=yFu*P#f)C~cHS2EpJa`NpA8e@i}+&QLYW
zzo#pqMZP=-z*e~lx$kZAxPQ^vE*~k!N6{g7`vIg=zKc#)+?JP9UEdvf0Xc4W<$>hL
zbjg)esIX6A_Zp@JDL(!HfI|w;a>xu<1U|vcjE5C*&X`k#ViHBVA{DYPA?>K5gB<>7
z#qd=iF$$v@fU$~VISf6f_;nXLk1M)p0~)W0917V9iiq_fiHfZ&Av9TW(+XoLin5Im
zma16Y4AHp?(>pLNPZ2&EHWetwP+GjusQ7RrgqA8w>LB#8qT3g(YDF#Wv}+Ve|HXO~
zFU>J_RWa>t0Iw-dr9j$s#W!>gtya-@9@D;|&_+XVonqEmaJDJ3DL~z>@Fd5rLoo*h
z&(coCmOr5IwxW~n{C5;bC@gtbVO(?_c6TYPy&$_s;k^*O_Y^O9$nI6dz6VWxig$w`
z`@Z7hc}(Vk;+p^{>{nb|fw6~*kLld_BgG7=xOuGDN9VVnD7?$T@>Fq$l9GdpR4P(=
zrr0$ct>=mw3O&A1B(4B?saS734g4#`YudZLR_ys5tv3osI``vbHrEWMIh*Z#AH>Bh
zfwl{-W)s(;<!1H{z1-5>?EZ1AlZV-9^2$8TGNNJqUbBnz!TOkOAveL-teSR9{$_(a
z(F!ozZvoQ+%_76mxzFrTBJDMT%-+W<*`&c{v2)N0F)P>ue1zFudrant+4I9-jWk<+
z1mvjM&vajnHtTCgE5>XmefF_t&I{0LHM4Ao^-s+PK7=qQbIA&DI-7??K%tBI@MN;y
zJfjmVZszvqVW_)##%yx3yv;wQZPZ@#*T29-AM@{)L#VI0qZ?TL&6CU^Ccyj(B~$mA
zN18)Ska^cZupBUNJ%tY~)I9PFj2$#r`~mC3%)2Ny6>h$8DQr4yex01|2=mz#d^=(u
z`56F5&EF@_E6O}nPQj9BbKN8ejWMr!2KC3xTSfs9XTJAe@EkYaO{vOw^NO(`>E>(b
zW}RW~c^>LB%^N8af69CeJ;t)k)2Zep+x*IWaORlXJ_N}%52tT>o_Qvv^$N|+rT|xL
z9x)f3XUtuHhgxHe`S(<eeZ_pa3anSnSJSz@Yvv!(iKy%5e{P4ETJxl@(0RjLdK~x`
z^U;lHwVJ<m4`XfS3d*0foBwJKDV^psR$-!D<|FDry3IE=gR{qcdMec4GyjDOjqaO2
zAm8DE`JRt4)^9Zbdngw8p?U7xn9P8A<7$wn=DR3BFlavbF2p=DZ@LIepPPT14oxr2
z<rc8wrFs1WsDEW{P2U(li`kTX^0&B75zqjO$<IInEuQ_CS+bbfim@Pz+xfr+TO`9D
zm4;YcrEkT43*!wHWFN4odk@k=Eh@2Rl^(R1PnSuUh1U@99J1(01qrvfHyfOXEyhy}
z{fNb22RI`wDqf@WsKpv8Qi-ydYYq#eE#{m<XN<+xvzTG5#k89saTcelu?WX4w$gVb
z-r|`vq$F6pHd1w2lEs9Dm}s(vJ^4N-EQaoe`V@=xQ$bQK?w6u7&EltFXq~ihdk?cn
zx41X~xD1Pm0qD)N`29BESr%U&2l28jJ_F)y`Rpff?zP-B3N{5<UUq=qLzaG@&|EBS
zsdW9YWw;*&D<dpt(R+X*Enm9B(xaAPlx~W$+<X}-qAfqCWJ8Q)Sv1tgTINw%=LyR@
z*I?5r%QFrjS(e{K1CVW*O81K#%fllerQC8Xg(oX4+b2UxrR90r|6jLsr)OiW<>M<b
z`-Wxh2nOH3I?Dj^vg$4C1@PRobcjK#!4gjhY!fWM>xR%K%jNGu#Vt$cT6}oTmNO^9
ziWbY>&ERacbYB4L+bqYg2I;U|N+**#Eww*`<+kO)d`P)t`3ps_?^@c00r1dr1qII^
zS&nL==ig(?MRefqiDk-bAO<YsW})@eavFzO3|c;=ui-PxU<xBWw;Z1a;0w#_Ptp0(
z(w7R!URl0FYxvsIcMvTn<w*uOXJy#$U~y5_Qx4fxX-{Q}Zc5!GjJYdUe+DZ&lykPA
zW%N|G{tZ?y<t-6-Z{@0bAoeO%tI_GB%$<t`_El~ug?c|_D^(WyD<dg^5ukJpLua5e
zla_R!vYryWLCVJw=nPgm$79v@E7|}2B4x*4U<p-vQF+!urIMb8VaijK9y?@I7S~~E
z!j%{4)dh!@Q<P8`q5Qc6>W?TlQ=aRn@_98{QOap_3N~8#nj$JO%Hp#ai&efm2V=*S
z0tKAnl$$A4cwD(C9x4))KYfF_Bq~#MU`bMr`5udqto)O594C~I;vgkOsa*OSdQ+7a
zRNj@QbPu&ILIy8;BxGkQ-CHn=Eaj*D7|T}1Qrsm+*|r;i)5<ASL!PS~7!8Ga%H9oV
z<trQL{#u}1c@FAJm2Le{aX~q15dasJQDs<}GGzx<KU`6+^#jXQ<p*_`(lzDTmFT>#
zT#*N1waRv52sGVLTAhL3I%NvoO6!%AbAY(1EX{<p2IZg%(i)YgY5Ulu{NxBaZz<PM
zNT^xKI6+#A^4>uJT9wgMN7JrM{|lWR%GC~-S*J3aiZ5;}C%6M}M|sH#EO(Wg>2cDf
z)CAHEu3I^Y!bLqwo6wJnu_VXs0KBhs@&L~R<-&TXf23SZ!Mn#w_X`+%qWt<SgbpY}
zD?pwqhr5DhP`Q-6!e`2QPfYE(@>DDU&Q`Iz(CK338;S|KT3JxpgPYaIe`69JRzt|Y
z@U$|&g_f69%LmZsZ6!65XRz0*g0j9oR!ivd?Q1oL3I+YFCQ{XtztznQ=nb%X%L$qS
zt&Y<nihWi+bD$~STB^ic60J9xKxndcRz7ek*8O%cCe8YzJy4NuEiVEf(|Y;?uw+@^
z_z;S6ty3wdT5G*7pB@%%*1?l8*lztn0$Lr`3znnRX}ya+gWJ|)M*@GxdL$(h`mM+9
z4c&HzdE2;%s;*vGzrF=kFRk4vbnwc0#tC%3ww^W%!rxeP$v`-%%;>swRte-7xv1u=
zaqYOOLgoPAtJ)L_g?_3ZzJ!!;)tO`HJgoXV1XDYrviTgdk5tLJz;aYIZX#Mys$KLD
zk5Rp4{DNkxx_lLgRFxtIdQYp0Qb2N5(nV01r(!+^ONnYIIrycj2~<{nL3Nc1sV}M~
zkpo$#iunrUk}4(vxN_CSY~U(X`)QpkRs9>Gw@MZH3&>^F=qKo`R<)4dTB92Nl@YW-
zwVF!B8&x&rb~LF%w?NY^RjL~h&8iZAv|3aXYGFmID)di~Hq`_Mq+PZ6F>oC!*-Ol+
zQ}xFkv~H`8xx>Ocs*O6p@2YZ#ptDOA_#BG5Rpt%A^{9qUN9&%-<5N0k->Z5_E7YfY
zK_v?JRSHW0AE-Qn0qj>DrM%ojRqZX9_DHpcj@Ug`ZJY-&PgHsIP#jR*pd)KfRm^p;
z465F(!PqmE<~lf^tBz4{@P$g94-GF>7tGQ5O7-?GsCVMeAnt9HI`cPQU`<^3pPxaR
zEAKcAtZw|nD)8**qbeZ#0RNnBVh8yjK83U}eg~b}ILtrcfs5e1>A`n|fA~Mx8_6%C
z0|7_*N_w_N@vo?gA)5D%qfeVZNFj?@UU3kuWBitBSSMo~uN(pVasI+V=#A&Upf~9x
z@V@iFlgQUKpq0e8GSHOFzp;TaC-`Dls7T?xyrCkMznu-vG`@g^?34UP38bX+)2v{9
z2ETj@TABQ1CrCNP@A?iC%;MM4?lqeqWd|uaM&2bItf%?^jYMxQzcLlAJbuj=Xyx-E
zRE$)>Zz2D)kWbwML=nHG5kiak^-D2!hCi!?-n0BCVVJ}@UQ6!Ld438#hf4TQ=>$tD
zpF=0AF7VsN0)CM{dKD~X{3FUEUgC}02QjB|J}U&x3VwjRrAofK0f;L8cgne6=C65x
zrJB#8hg1!J+Y+2t_<0k+a+Uwe5-W3!?{9|s>-;9tTgzKoqw@y8OahiV{xc)s_545E
zKyLC+s35t4e|7*9Y~+s{DQw%sM?`@27QY}3q?wN^!3<mYu@psZ<*(X6XdC}F9T;in
zM^h}SgTFQurgidvPypmMKZ%Z}+~LR4M(8e|av6Xw{xAh>y7}OfVCmr}Q`qMo-=7FW
zd-(~o(b>oUR7FK@_xaiNu;u|@L!1A8-k&~$hrFpAEBlDg<I#G|e?uvjC;WNxz6bb(
zzhTT%o+C|z{H}6ndd7GAfIR27P&nlUe|#M{U-D540Dr}27J~CNKOqUzeZzl#6mTb@
zZyarJoP{Ox(CZ>x3WR!B;UmfzxCt}qw2r&bR}O<cgcKLFJcUXs1oaZ$BKOQ&c&8FJ
z?G^Uy!kCZnC<Vk<nAQMIenRJC;QWP;y}=S79CpK4ps@KW6zvlXiC_s5%D2+?CRq5+
z6b6R~E9zkIeqkmZj65KGlLSPlP(;zig976R5+=lZW4R6qslLF63qF+IIV{ZjA2dY>
z0^PHZ2on#0B~l1n1WiYUxmPilC}A$0bBPwJDZd;e%q2%ER(Ku`7UMDDwjcDy306M=
zcwCUuClW9Cg+p3`P)r4Ti9+R<U`Y}_O#w+39?{C45LWA8MT%hm0feRsF;Af)O_;qF
zohJoJKUmU*5#$AD2svM2f|<hB|GtL85qjce2_b5*WE+JxIv$oIT+)J^76PawBUf;t
z70MGvpF}HP(CtF2K**g8M4@ouSG0<Rjq5>*g^j<0<&3a>6%0KqT&9;Fo)gxr#MI6U
z=`WzSM40{rty00#34jYi8r82}6!P^TWrFd=R?thrfB$c#TsV9bYgr-WrvXtZRK`JQ
zm2l1pQ@boACP7-Y;F^S1jZn1<ELQ|ea;>ilE8mA{*MyFzP=8%0WkG6%#oIt`2xm*c
zStmF<gVYOkXQA(=P&O804MNy|Zz*pS{O&?ilh8%?qFcgHFKB8Ow$ih)MF=znqE%3S
zkIpv1nM$JCg{J+$cL-4wLg*A+$a}vnG<}b;JHo<HEbv_+yAWet!k!O->lWUj<XDdo
z)dXSpgioJitXHt;H3HZte0mF-?h6YjI{!c@q65bL!sEr5+CyO&1tK2_UgRJ=7Ji6_
zm?y#=s`D5S%D2GYr@}B1fI(pcZHt}>=jpn7E|}9j;f3Jv6*ylCA8bJ9E1}X3`d$kQ
zyg}Xw4w)3*a}pgC5aTQkF@-`G@pFn{yNWNU4%JP3R|Zyhak39sJj7E+Fy<+KLC&z3
zXwwPV-lBruHnmsWAqCt=%;YdNU$K|s0)Ao}l{EQ_@6skVKy11JK%f{v{^ve1){MdT
zFGyT53W#8_Clfp&q9X-W_lv{I!E->=P{buvtQ!D1C^GbJhcHoH3u6w6J4?YCE?U#>
z`LKB14`UJHVhVDc5VzA|pA^w-HVjP_!@dAZn)nOFdryk$4s@oA>6AM)W{987f!<89
zh#bLFVlX`ov&4YyurymdQw-B`#F&4<a#|b`1HHN81*!qb6EiMAXuf!<7`Os){6hc=
z#et_#Q6zq=1}PTzIRS7+4Ans9S#cPZk)IQ%9zg57XnqB)5~Fy&7Sc+^G2}O25LeJP
z<)ZlHCzx0!N~kpVl6e0es3;eQ&<3tTl+OpSQk=64VyeXB^P%ao_^UGvtrnx{X;vd9
zuY_q=#7E@yUlmQC0&q>dwh4-^i}sTttX4crXPj<`#wOYh)`>@HBUUfQk*j%Aw5F(8
zgZSrJOuJEBU;@@Aaq<{wx+U(AfU{Y=LkWu(aUm7Ew2CK!prTE5q|2jS4EYtNb%_0c
zLs+L+H32NQ#g)s@x+9ubVP<zl;U@^|5)+LHpxxpliaqp*;xhp6i4qYCd&MZKSm+a1
zQFZoxu_gyB55$XaV^00zr#m3@p*WF3;E%*|Kj?id9*RWki6|leb3lw)0o+sZe^h@r
zD7K7&`e)({Dpq(dUShBaFGSBN<bS>tN4*1{S7Lo3$ZOHzeQ0_kj;Ay6PU`u~Fg0iO
znmn{z)L)WU>8c(=dptMw>}F_kSGUEW<)QwYzObI^R&uYr)VUo{;jJD@f!e)ln>Uc@
zqgI{*@m1fY*tehh;Nt(@GpZKpc^{ybklsLbRwAVBQ|CTGD@c8XKA2$jx8!_;r~{v&
zbH6&Al9310GiaL<s`jQsSqIgV=m=bx+I<`*aY%iJYR<ydt@LW^!|L)Ta7L&T(_zyQ
zb=aR^iBz9KAU*U&C1Y)D+y^6L)Pt_j9IMVmS(5aa`UfiAi&KxH_~dbQ+zyPztLxT5
zY=Sz;09}ddqh26M>LFR+OjaL@2ImR2HW<QE)PpLtQq?kYoYU0ZKLUPI{pw2?kgjf;
z0YHY@)D|q6>L4S11x~3)y@%c`^=`V(veipV(3zt?T?OE2b*dj&bJgh-b<a~DB4;FD
z{T1EI3)F9QLTI6SaRvZI>Tz!XFILA=4C9P?HdT_IRo|j_Se;X+97OB9dMUloyhJ@-
zj?Pl`?FmK*y`Z)W#MCaTZ<FjYwf-1Z`jR@4vK!^<FR8MkLj5^8o0aNy15j9{?x$*)
z%j#b%!C9@gr?Xl$>Td_ox}x^@6zZ?4@67?ZrarkG8m^=01-M$Z75Nl5)Cn>eQ>VWB
zrxZ8gdi7`IqTEzB48o`e_25{rHmXav1K*_nhF12L`pOqj(X38p0c=sLM#836wMPd4
zZR#P9V0OFuO9xD?L%r=5RCKC6X=8I+9T^0cJL=J~&~R6sO?T!l^$HJ=ZuOEriZS)5
zZQH<ePwh+FhhFuZQmF4!7m^!rU;XGlS`X9~B&J_&KMO)1sy`>c<B|Fr?Uo*^z34F8
z6ZLL7D>9&F(_r>fb$A_GgKAF~w4SN&Q&swN^{fTJy-?fHHs_`K#8|KxU#UO*1U#?R
z<)I*N)YAWf$4PUPg^A9ZA>^sJXe@PTxoWI?G3KWEdMa!R(JY`n>V6GUiTFZjY{p|O
zR8v41%Y&MazsFdZh8+Y6*ZA!N;IO789xM@>Q51AMqDg-n>LZPsq$|*SRI}=DG@~>_
z^uR}J_ES|&jOJqp*d43!CZWeP0~A4x)BH{0(c>DIF(C1p!xT79(43`$`$WwXaz>Ig
z_pI?TC2Jb#u6;tI9Ru|#nlcA;rfJ%L0pO&@a}!9q#yGPbLNhd88fePY#E`3SN)tk{
z)+|jcRg`9HqO@4A9L+jgaGut@L!NrB#+<_Dd79_6UCGzv4~O0YO*R!17itcEjIkmO
z0<ZWwXv}CocSch~1#M?FN2v3hMiT@L=QViQI#iTs=2IbTsisp8^%peb8lmE%X4)=@
zDbuW_K<XvUwjNBTT$A%TNQI_z7lc-7m~WxJO7k~`RWEDI>77B<ny3(v8qM?=bY9VH
zrlQfSn(MXTyr!u*3UXaz_Yc(8YSNp@3A&*<J_D?Enp5#0^_n8ujNjCxcY`!&?$BY!
zMosuc*wm!4A&2mm#&<u2Hft`>p@$aD^Aix-s*#U_O>LUZ(?HraEuTVIhi0xbjOo;P
z)86a0<^`1|+|m4<iO##49rGv%(52Cyg0yZ;pc0yTG)@Zuyr;>Z2GXnf<tC){X`JXL
zd|&g}68Hxi+_3R=&_ou&!iO4r+R#1H6#jt4d#s6Y!va0gT%_`a0gYlhIG<`hvW10%
znjACeeWsZl4DwuK<v>Az7n<R=;CZR38UbmqG*`EQ^|hw=G4O9R!|3XC(#A!>LT7FB
z`)Ijn)#Qk}YFn+*a?|=#IiS0C6Ga_7v_4b`?y2P|ap|S~fa;FDwOiaFbFVgrWcp|q
zQAW#GtGkI#qo4M*Bdqb)PNfHUfc7rk`~tPVRDx%p)>sUDkT!WWSc0{^^Z*ah4xv!~
ze(lvZs6U`xNEU`_v+F<(YJ;i3IZXTNQ@{^tM`mFS!?ovzVuFXY6FvZm(01BF*b!~n
zK1?ansJ%xOKS#CiUx77I+Od>ukJd`4up~yit`x0U?LNxp9Mf)efciMCDFrW%Yc;bm
z7O(yKZFDAR*KPz$qBf%ni;$$9Mggm2tuyUkPiXg&UznnedIXkKZP14hou<{V1ItOR
zv6VLL>Duo*AT2{X<5vu3YGdfGcS>8g82Bvh5i_u4Yu|Q2XO8xxI<!t}w^ON2t~SC2
z3iGs=F9Vmay><o06lf3GLt&w|-4BKqX>U-5saU%+4xMMT&ksY<S?#=N2rJR<Gt%3u
zO0`dBg7u<SGZ6~QwEYwnzNB?70I*#9fL?f5q5b83j8$rN-$GNB_7!=1m$m+CbXIHM
zJ^*-))<D<#745cH&~#NB<PP{X?JSCmT-R=&4ts005{ir5(7I5;Vx2bfDb1o@8%&k{
zH?_6?m`sEA++^@HX|F6m=Pm6ZRSq<3J19-wqLs~o-d64P(~#Y!J?0HD?b>DKm_&#6
ze|lKasg3;*fZN*2y)fpEmZO59yIQw;aCT|uJ%usd+6Ny3-lKi=C*@e~X%D8Mw^y6C
z9ISm>dwLAs*Jhc3=Ye)3ZS)^%t?3ZMBdrfPeUG*84}d(;T1^0MK)aCwu}`&=uE5?w
zZ3oo>Jk!R}mgKp1n>$)Bw2$c!_)F~;igmuyX3huhwYCtIphoE%?HO_#oOB+KF$-ti
zM)Fx*bg{QVTy;Z#g%xhP&#EBXU00EdMexvVo&<%Sx}GAic<KD;mgKGT{tQy~>NW+S
z(?>V;4%Wg~_ZB5%{d7~z0r1x?x`wd;-Le0+Lb|L1;EelpDG$&aq`TV=M6fRGBbXSX
zGmz`LU*}5sxdS>&Db$DRn!kgJgSwm&w8C^pT)=WjS2PbKTz9t*@WZ;{X|Oj!_sLXz
zl1Fs*lpl-K9T`CDsP12??1<70{|>EaooWKq$1KuCeUE0W&YlYXj_HOL!<aZ-uoSGv
zbzcv`LdEO;jey<+-OEqWO4O~O6C6o8kv81Py1C>*ozV5jKvHy-9L7?0QK56|P`|Tv
zDh$ok$v=azQ#$`57?Y(_QwktkclsDej;@nVy`I+1a)R1i-I{}#OP+30CZy!+j?>A4
z0^Jt|NGa5nssJz24cmjxVjV*s`WanTDMX*uy`)!soYReV1?PF)8E23ZU1jLqI>y3S
zn2xcFx>xiPsWRPX$Dr?$E+7Ef%XJ?XLT!a^a4uSvx`aJosnVsLgoewyuj7EL*1b)S
z#2TG8941}SW$lK(tGdslVdphnjtq*f>vmJ%rB<hL0_P2#|16Bv=|1TNyk7Ua@dbq5
z)O}wGo(A2aiD)(IexD82CY?JaQ*P;oaA-B_tlkE&MfZFPTCKY4W5L;`Gkbu}c3nRu
zQ#y22!=S!X_t!{FzF+ra4s3d;bEe4sBi%~M<viAH`V-`dZUw!VWI(rPI>nTp>T=1a
z9Mru!1N<{x6&;j*t_#15u@|~NDzbd3dz}q~U+Lb^UhB24=NQDCuz5`Ju@oB(U8-p|
zzN0aTbep;K2CWR6SG1YUwD~O`ou_P;2B0&`=Dixgb8JQ@!0cR`{1X)A%d=5#1y6yE
zVmG7}+SpS5vB+ktf<8%`vF)(pjLnn3AnmNpyF<`AXEWm%$a$L@x?)Rg4pIvEf{iSe
zK1rKJCt*yP%{p_il-op6)qaJ|m}+oV+Jp^5XO)eSN*XTP)FCczlvdlkq{H7eHm+2o
zcEx7FTM%>A=40|@uh}G0I`Fzpc_~`8Hk+xq^M=hX%7WC{1Vy2<-o~ExVK;5wqhL~l
z&3IbbMw?4pFo`A`<tA|6vbjT^c(cvYCFpFixhBG<P8%hqFN}9>jx|9{mrcGBtlc(6
zg;3vPGjj#R+_Q=J7^K(6R=`KuXR{*^i2F82eg<d1jrDLyduVgO3-CuaOTPknY;*ZJ
zI-l4$odnB(je<_+KDFsqpmWgXFBkfFZEX8s%yXN4Ct<}4qfNa(nlEjnrBLz8rh%##
zUfV1c(fP)PnFzd-{z)&0vwq4@jJfEKc|wz`-j#wQZu%eTLFuk<e*hK_y>2svdg^C<
zgE23?igIn<`ip8zVz0jPGBo(;V}jA?tG|?odHU&%26CtT^;V(42k58Q0vM>jM5pG0
z^a)g~7_4tw2t<fJh!P0<^))M@;(-24GcJ};eVP|o4(grh!4anatrnUN>4R58X1IPB
zB{~o5YnKBTq5qZs>);Xn`Ek$?sbBgwIFIV3MtW*T>0g+k8Lba!gzQ+o;yBjpn10sJ
zm~WguO%23x{fPfzN#gZ`6l6@)7jyxatlvd<j}!Wtl)XvSPx=)kO+R`oSWfC=vY|I!
zKQRu%GW2z{!Oqk-UxS7$eP%y6v-M6JjTp?)i<THXt+(6@D{}SiYaujGU*d~7<?Ang
z3NZ!xH}r`V>Tl3@yGSpuMQ5@8q!uh^^q~}UIIF)f7sAfz*Bt=odHsxVbe8B#Y%qyZ
z{bRZ=F6eo3HZJO~Zh(|B{YN5gFw6D6Lx8Bz{}BL0rT%XQwpHmz(V3;o`XLmOuGU|q
zvaTAvst%pc^=A?w&C@oXBJkd}4=HlF*VfGiW1+SKv>!NRyM==75w>5i$6SuuD&7S=
z#&+f;aK_u-If>2$+ss;eNlc>c7TUlh+0K<fQ?l)Ay4Rnu9XTCVq}X=TJK9ri#pSfJ
zwt0mRbJEs8{%X4I1UmekVVh0MooRcP>cCFf%07YmY}>eBfXlI6ISHL-Z70y?=A7+n
zbKox9PNDNP)wUa2z-g?p{d@)VUa>twp3_y^%9SwYnr+)0OzpZYPvP5I+jI2vyJ34f
z0r)!Gh*bdA+cp=&n47kG64PMY_y>eG+BUuqT$Amd+rZtj%{hwBX4|`O1J`1!oe7&-
zZ4)Tc(`NfcJ*@9A+8(ij>`vRHJV<l3YwSj^o85Qxn0L3+YzEN7ZUG&VIc(=J2fzqB
zyCk%Z*g2B79%(m=QiMnCJSLzOW%t>C$y>YPd+3a{yGqZIIJ=UwkdkT_qJxGsyAK~=
zx+m=-EHIXCXWaHLKBo*jPYO9?+FdS1>y+IH^6j$hWOPcs$WBFh_+mSyJI2n~Wef!=
zx7%9;X%%)`e*&qrTS9LJs<OL81<ciURg_4(V%KX0&Z~BzdKh!dZc+#=Y_@Zx{dkMr
zLdpuX+VRF!(9~{slZwzg?65V%P0TLuB%}@4m46G?r*>5hSdu}zzQ6GKJhQW-+w%*%
zDO6Yd(oS^6*ekn{RE6-`Zrp!m=LTB}aX1@3p;}EBgX1h%;c6J?4bg4}^JD0AH(YAM
z>^%(gS5OAd%V1oLL2pCL4UoMC1sx*wF{BTN-M)s1CLsI_rt_i6-!O$T9RY?#<hboK
zY&ZmXkRj+a#)1t>s*(&bc;5hSzX5?f+@}mfM}sre5J3U0gN7GtF?PuCHN8bH+^}sP
zJ^vyM8;@e}h+!MWqT>udZNuPkgJvl-B^VCT1(9gjLHDa<!x9@zG{x`^?R`@X>**ev
zX0Rpa;iTcK^-!2@$e=R$48tM13uGFMd9d)5;nGBmWf^32*f!fxy$Zr|4DWAb@%=k(
z7_>rfo*}CMde0lKkPlK~SVeW?rG_jztbV}|MECBChMz8?v&@i8-qj_;7V_pQ3@J;n
zmX(Itkr=BoEIx;^TEisz-rg`grkzK#Vc2N2S_~71!n9VyAGCFDGi+(YS{U06Z+#AH
zIt+GnCZp59OhfN&gVz>_xnuZ&zHxUA!_~ld8TS2v&Td2J=O8@>$0l&zGg$A06@f#4
zz0X1wenzTxK+7n{RrvjWa4>9hWp>fG!;Ohd0&!=0{@V&OQ%e9edNK^vY<e;Oh5_u&
zl+ZJ0FXKxef)7)R0&ZD2<3P^)DJDAxmS!<`X_uePBu$5HIZO>*G^d%kFtl<RR}Toy
zW6u8rmVD+w8At(hj03Kac}6eaD`I@;_Fl}aB!Bmek$E&4JZG6bK4_j}{&xa{=b2u5
z{FgHYYljSx-C^FQ-K!g$+77%s`xjNida!rs#Dyo@Kt~?D*f1(>_h!GO;<&x6|8-2%
zhaI&CoxZHaQ~><gw=%)$&kkP((E)6%5>pCfSD&DV<UY3HFsuk-7b1uxi)1s9+>l*k
zQ?S35d2oMGw#$b*j#!dxA9s5?WFO!rQsyC?TO}wU96w)dEyM4x3T{C9#IFLuGs!;|
zqNl6~o!Y@@jNEDrIQmdH-iujPj+yu{(R2nXn;BP)H9O06z4iY-L7|9T-PfG+yHN3l
zJF9?tCrKDWQ_?^QZ;e^(lXUDxE6U_cI@uC!GIJ_~$Cym`8}edJ?3MxEqP%|<EO(TN
zbbO;vtDH3ngHMz*E5Z6w**qC7S1a2Qq4zr&8{?97=#8`5z7UY(R*COGW4x6s<(U(#
z?o%i`(P{^Iut`?$ti_~~t=3ZT`GnOtPY6%3lK6t8S}h8~v@@-0*Ml?9s*38O&sufO
zfUq*F5(?;5Tg5B@yxywg6=dGDT9^VU4OU+m%fZ@cb!QmVH(9wZ2kEogI}@z;t@Pz+
zJ+NZvWLm$~8y~bDTD>^|g^#QZ6s&k`6+RAnpI8l0IqHCwp4RxO)r%cqd1mEx80w!}
z4br{og_ZR~biTA&{sYv%vWh3i_qA0(H+dm%tX2(&Y$xmfJP>E=^OTTxv2OQ9%hUSO
zXAt9M{reuYysh7N25_(SuxAkCV}1KIK7@VNnRn3{Wc?}K;)1Oms7fWo`hGI>?zev4
z1Yxn(F)6gL);&}UoM;_-8Gw`4b6!)fG1L0Xzc9l*>%Y6f+Gss)90r@L6<r|B)@Fx6
zTC5vafwWuaZ^yJdtY^OkP0y_Vy@$)hNo7S@1z%OmOepkI1>OV+Q@t`k(@|B-M3{YC
zl_*1JifYk)z)z{#HbGIo>c9eer}sJ4fD`bSRBsFztWkaU5m@U~ru)!pR@qPqHR^{_
zz|yPw>R0G}tm^WHF)vgvV`!cDmvs4i^BiT7_VOz!^5Mf<ctDCTznY@3e*7n?0QmE_
zE@3QyzfWb7f&9<(_&4t3>!?6Eh%fKJ3I+4p@vu9DU)KWG{e18U01xmbGaxOL|EwCo
zgS@f~ow59n^gTYtFDwBdj<>I-iSqB!xrTT?P6EyZetRdRB=W*qSf9iXYQUMyhbDlW
z;JwHvNip)5^+2TZKT;qujo(E<p_6>gZYWIW&kuo38T{I3P<V>B-Ve?!en<;|+59G2
z?i@aza>=LpZ#_VA`PuZy%;VS6?mM5Kvj&_6{2*0S7V@iUuUN#pZ-Am=-r+rPp5cwo
z2O#Dw-*p+i=lIh106fq42VqI7`O`-+ryG3sF37&cPjv^PlmB!mEWF2m{{v({;y+x4
z&KLZmnUMXGx48z+SNsh+fB2doe-2}B`1fez>m*o`o8>F?$-v?#jHD=ozYt>l96SMn
zO%j9#3J>T=?>=EM-O7T6FE_%b5MenTSKBYdP;~Kt@b_#0LxpL3(K;yTT0o)%PpayP
z77CA|6(hX;3c_NA=I_vXOz3KWlsMrtdSAnFp}Y^RcwyNqa3%^PV<^m)By`3@Z?fPv
z9t(9sXpV#W6v3HFeNu%F=+ttW@N6^4Nx`!OLUV<QbPzUAD5U#rq3{cx@hB3Wy#;bf
zIJpo~%7vj<!C5JIeFa>VFx3y7H-xD#V11qNXCydp3fqs<`@$Q9*(ac>LkO~iF`a@l
zxofwD=j2P>5pLZB@UBp{4|D1g{G8D077V2zJ;HaS{+`fAkK<lp&1L}lgismu-WOP^
zc77nNiAAelcn2v5)Ghq82T~phxfEx9A}m}?|5J28XrR>FQ^8|0@PopxpFo}o4@O{y
z&xNplSo%URqZ`IcVHy?7yb=aVAnmpAH`Oh@5$=w}ayf}_{S2J5xHA?kF5)OEV|NwX
z=*o2y>&{@zPgK8+PJeM613-WnM44S<py;|C(t^aBE9pZQ8y~~A5b+-aEZr}Tw1*YZ
z;;Vn5DMlPl-czjTasjPlVp|V5<HYfYAoRExF$t}B@frny62#x?flCx8q`>+lapXRX
zC5s{PASc8V*I-PFxW65yr5eSRw5v@M1Mmz)9fAp6LK)(Z;~+FsT;GY-De<3=(8>}$
zBhkthLuligBbHJ^{j_-QI1J4d>nJLjC#F<kEMGjKM`wY!HyTzHioa7uNRc?L8G4Jw
zfElpxjL1=~>RHivX($kv#SGeoSBskM7`!6(Cj)p@%pH!-TJfX^mK)-?&(Z1?w?$*Q
z`b3xaL0*WfTrl=h{JjP0Uy0=lpyIW-djUG%h^y%^vXlCd07ISCUQ1!Ui#og=dR^70
z7Gh=G)Q^pHFu`3ti(-Es>OBiF=&9~}57NBUS4KgMx4O*>_`T|mBWU@mCz6BXr`{$<
zr@y*<32*^wKPnarRQHa?*go}V7a==HJ-HrZ!Rlf<_Z6ac+J!0YSARy{_yP3*-O57M
z>8?fyJ*f6A20lzZ1wJ3r<WqJ-cDQ;4)i1=WSCfB~pdL0Ior&tNe?cor{go3wkz}<C
zy^-RC`rKH+Q`NT%pf^puZV*#CsqQ7`GF|;e6|Bfm_XI;xruu9($k7jXQe9X2hb;~i
z=Fa$VpaNpN#&j=+in_6x3aDrud#?myUVZu{Ww2j=8WxYvpz)VhfE*m(oQPS3jgR9Y
zJAAw$71A=tf8Po9=f@wl0ZYkv_t{{n7#~C5^gH8!C*L}LLf|zsSc;$Dw*}(&A7k!P
zYWL51WAOX0WHVT?N!x|rJL1VP+j%Jv@*Pf4!I%?shN1$_%<N{gT$qtZz_6Docne~D
znDi=G;K$4*KXX5mKLsKVFlB2n*CWhux`{_J%4allrd5iuc*dNfc?nF;Es8=WGSPJG
zDT#TH;>a0{oe#~2nf4Df<ujkIMXP}Epl^90<5Q0{Dq{3Y&?;ki$~RwP_S3QEa%Rje
zsHk9mK8LYd#)JyvZZJL+ldNL|dOp=NH@u*sl}V<oOdIp%OiJ^$GvAZ~-@){Mj2U(^
z<GmpCHuKZFu=@_PyAxw~8T&WT+r`XH##lcyc>pRNGOxlQ<`FZ3LOPEbPb#v1!qibI
z-7Dq+-Tz)Q2kD&d8zw&)RyeUv^jLOg-&{eb3(Ggq{m+#h{y(s~vEP#zcUDE)C=Yfm
z?K(Z#oFh>0#X9^9+1_k36`}2A4RllWVN<^cr!RYjvW$MLM-S}vXB$5P31ENN4-&{O
zr#s$0b_8_>v7^aj2xeOZ2n%6LDcf$`&-$B!=K%XZDgg*()2MLyAZztARD`i#PJyL|
z*yS3qgtL*su<0=COGmgO*r_j|_XxXXEO2owoJHIQ**#~`naVmG#9Y$YA5#E0$^J{H
z%hK7$QRvKNfA2wO9=nAi75PT?^XZUXz^>Q;y@hNqMe0l0nAI4(!2aeB){Cq_afC9~
zbQ|!OSp7VhR?epH1fYTqqO-US>=%8&HL|k35Z1(gupGEs>>m_yZ)Huof$LyRrvT8&
zj`s!pHtRM9leohgkNilVFZ&an>h5AM*aOkc-ZsZz4;xHbJ0~v55eQFi2nE9Yxx}}i
za6gB$HdqTzJp>A4IF8)YB<}8e=uGCCj)9!uuD=T_Qn;y9B$&$e+hg(5IPZ%9<a1M+
zprL?kFusJsLhi^ru&szIz6qXU&icRL9`}JY)Su%DKLO%A*GuPcO1RktAf?<|+FoDa
z7W@g>7r9l9fM4SVD`7<gXXyi$HttFw#=5wzThRG{`{x1xPq{=2wY}zcE&;$p^4mW0
z|2-w_YYcixTBta}Te7wi_`MQS+JXB>exMkxuSA%M)<MasXRtR+viUAp4oTj51To=~
zm&-s7OVTMD6e02b0W3!(h3jDbQArQoA)+Mwbx4VpT&9}l7zs-?`mvG)|I&M3j!Bj%
z=@OC@Qq5qxWV0m<J}uExSglyn^DS(;AlY{m_$tZ#cOdk-g!>qp8YO2X0JKYHyg+A<
zL~Q|<dy?xn0qB*y+lyA8WCiWI?o0mp8`FLukx`XQzvR!Y06dhqFQh2sYst{LF!7D#
z;viU^q#F*wHfQMsdak<QrE)OMRa$x+2si1E8zIzPIxhjU_ryPl!I+nHXa_jGrC-vK
z_Px^DVIV%z?NsvPD;-G=kDoO2G&J~2cT<U1s5IUKEC;0)bO6Q}CM}49m_yR0dypM2
z_41>&l+ND`5+QAi0c)hR4pouTqf-8Nh>4Q^>W&#kOMi<6AVxZICya@e3Ko!ZO!|z{
zsVUOqbnYNk`WJ=F(xm@R#@I=`fC0kNr5{t)Is<ROg@#O{bUoGco|0~*^6PAA7j3?B
zqzh<Yd0Og2iKJZV&SvP%lm0scE0Zs^q5N%ublxg-7D`PwL(Bzf+e;|CC@rKi@iOV?
zCa_$RKBaP^a_O#BAQjT+ZO~gO?WaP`D(Q~Z_y{jcjsJcIe2sMJEi|u4=M0C6tJ07X
z*nLfExDOTArIu&Vs+Fea0e?dpGZXgKNwXJ2VLko{8D!svrw4LJ8ubx`-Ie}APIi}+
z&&FK3rF$v)-6Itg5Zx=iGXwBGX;%<9@8c+S9C#i`^>lglOM|a~^`TUq3cYWn!>C5d
zN%q(kra8;RbHKaELIWV%RhGL0V{Wqc&j5Fq^-y`6r)(8f4tdGq`XSp}Ry`H1y|N_o
z!+m7CKZZ<S*=>sJ`pE)b!}>$AsiyS&3zuym&*88vfIP|w+58!39g&Uw0j)^cbBZ}1
zm0fHEiIPeDU}21GX8~l#%6?<eIwpI)4eH}$^A|$zaoMV)An~&8cd*V0veiKlmMEJ@
z$)&ThTR-4)JtzBX6L1x>-G$`;-;&k$qPJOg&;f{7vZ|}l8*j2N7Glnul&puQ5|bW(
zbT*pwQ}CnN#NZEnx5>{2*wk;ro&s*rq%s3*@yz7w2(WmYzE=gnUegVf!wxacPlNhM
z)2+L~a?;fC4HhBaR74qr5$|^RifR=bO*dbIrTwPUjzFlVJZuGQ3XyA@fsd9SRKSWf
z`D6+fpOPnQ!BQq4O)lsqdC7R-d=xK~==4`~?nEm<@kEAJpkf#8V}lfpqhW8bqV+V!
z_AB@`z#UK&J%-uFLyE;z7Z9#EV+WqYiVHp9Iim2`4-+F5cD7I$qu5Bd(pbf)Yd{=R
zd_-<hyh0*JD@ieGJ;qWLzn(zrq{7D!_GT#V|A<zmg4vF-EQNJAG-NAssg58=(MXro
zX~jqM4KFt;F4=)rDz;Q(5vmn!bQ8O(XwHO+>x%sEVABnSml0OfD{j&)xKYtT7ip_v
z^L?<mm_4BEuA5n88Co7@JO$Ui%*JlUa{HV8ZVyhJTTcfGF=Hszd%*0;Lo7*{*%mtc
zf7r}80Y!TMxrAb~1OE7_oH9a-MpHrF&pC8wTU;~_e=k|+i~glSZvg(~Jl%emna87l
z`SLtST`@fzDt?{55^7ft=kR;gXOyE{eQ79uuPJ#CsI{{*Fwu3Xv~%4sopOKnYaHpl
zn>&Wl18%2xFhn>UqzAZT#<vi<+n$`Qf670?-~UdhjJolkZTQ=nSw=B57iI$0#Je&x
zsBFlOS$_q_`ZESPNff|L{{XE(Mjr+e#+?5IEQgq|pCCM(xr^AUG?n?q5mp(qnI9?6
zUc>~_`O6E;W%7bAGav6a`G3ojHWGhCvY%6#+EF&65CWsvM2f#hvkhTT7Q<H7!_atE
z^F2Bf*vR{km%{#a6FO7bvxR7-u~}3Sd5WDUMJtP4F&!kEP4%St=djwpfG=RrQqrZ6
z4I2p+MQjd5+Rn2dQLL(jb*6%;Qg%iaILq199?)CChEmm74cq%KSgx?<bXxf;Ye7EK
zHFhr#mU=d68d^8m9U*8nunAOA*}_iY&}wDhhtpw{wy|5^2fm$sRswtnJLf#~cCm)x
zkloGZQHA7vc1saDAG2SD;KO^u`lSLt!0w|9<^?--1aMB=gulW0NPd9Ms6J8rh+NZu
zm(^=#CEa4*FptU4b7J44<A~1eRX0q;g?(ituq(Sb8`|7hMFNOBi*wYtnAvD5;`3zX
zTd^KqtOxD0z1dC2Ft(SSPf<-D_GTlb`LY|PL#ZFz{Tp=pv!78$I)MG#4lH4;{3(n*
z#5&SRf^gO{7h}iStvyhbz^=Ff|L6a%{#CROUR1Ue%s)^06RH-s(0+MII|qGB@6&ea
zmwT@0Uv{V!B9@y{U}8n<TA282NfD&2obV6$SN-$>EL!bO`KUFHmmzcQbxPB(dqkVk
z^%WEp-C+7LB>Xng4JhL#-^rNXwhT&D?~I^lqk}DF65W{CIY7HJA^zy|VAAK(q?ldw
zZs<T}4%No*V}4P=pdiNUZ2-cVRdTGtVW$5!ERJBxDNPs2sJ5Upnwd^ojxqBrLE@Qr
z2hf?slzd0~pA=>Tl}TP^me4J?npsOF7B!6R6==G`eDDZ*uQH~8qJ{q>`!(=QOebxs
z+L(oO`FAr#5{x}z?o$=TbLQ=vV0p!C9s^--n4Yg8+L?Vc3{oQ5Ab)gbu?LX3_`g+8
zHR|!#X~yhhfO46>KVerM)BPF(^BJ`cV+Bkel?)a#_e?RZBIa}iBo#9gX_H;XG*No!
z661Ov@N(vVbZt~HugGJqWM)xk6_Y?2+{=tF6_r#oBPb})&Ln(|73*Ne%rm0d$qded
z&^~4q<#p~ecC^NWOoAQ8o-x-bwBf?4b6|xl>qXAI8~ZUG1@U8dQyH*78@CjC1K6)F
zg7YBTcL*emeLfYR%^~(g14s-zFBs}$Sw9MDA7k_TAS{mE&Qbh3m5rtQV;Xy80)VGk
zyLQYemz{DNn)29{=Yh{>KidIgO4!6kbe6Ifv@5*8p4|w&7g=dIa5d~-t0DUe`_>2m
zuCnXLVTRY(QM9jVV!tZK*ey1M;%Ch)PgiOSJL1I<eE(b7iDR))-7MCgHa&s#e7MIh
zqWDlR`^5r~KK2{hdfjK0BO&_%`;wAd{cPB703NdQ!eG-Q_V=^EJ!U<3q4k8Vpfc|P
zwr4j?d&+*&1-*mp$D1*;XKXMz)6dx_HE0=Muy`2|LP)G;C8WK=-WG$tTv;a&hdB98
zj74!zskkJbTSUg3<XVG4N;tPQ=&a}NQ%IzjyGeHmXNlc52#t_TGeCW+WWg6OrdX0n
zwMUmF9&=#*ElG$2aE~M_c7VJvN@iyLzgs{xPVEDAQ~Ikp@kxK7x|kNJ+n<<vyY#1U
zh`KG!b^r@}%4<;ChyRBN84soYKHz*RO<f6_pG&t4N9zsV9e^=6*}^Y|U|#qUzP%2y
zi~VUcy7Zq$h*`GLOoGpU#d7kiSH8>w({J^gFyY@f>hOE}LfR+T-=aF>9q&`c>drA=
z0p`TKla2W}Gw-=Upf}S*1<-q$z5w8Zm~~Wl6wKuR2y8gBxdpAm%<1JAi)Gv>3v!GZ
zNm<Mj%;+CspfQCxODWn^W)=levYFuzVN4D)nI4s=nN7jK=Q7h?0-wiR83ZDq*+o@@
z1&r%yh$&>2?L@1HIXDEZVurm4_!;JN@(Ru}76y=WOx6;JKF{P%1H6QJMz@(#CYu6z
z7mUoV-@$W{`925}EMvZ#2y%(p@&*dandN&Rw1V-btEiF*2t#KTbCdF6mzi7Sk5@CM
z_2{f&x~Y!l3iG5E#@u9rLoxdX<{TC7G&0UQXli2e$xFV)4C{gw%}jM7Sne>!*HjpG
zm)Wo$JY9^#KH$5Vs}vsWVJ80x+4q=xI*93IP?JYDi3++&q_L;gKw1_%pKc^M?4bro
z$z?4lyq?dtQ@ppB^`WA#b8P(zOsSL&q8)!3I~*Z6Ji6r+Ai2!`X1oWUtL)EffVjzK
zI)kU34Wa|8PTcrE<mknZ7)o<J%;xU^iC}N%0DFX$kfca<55)<OvY&qk)lqEczc3`4
zE%g8_hMiRj>tfk4Qg9w)C*6RqIQFw|q2xIG#~;AO8`)8{KqRnjHb5k@8>v7ii8Z$b
zYcd<x2-Xwq+;p&}u(q9OrLs6%PYd8hMM@`G*)EKwv+EhGST-9)3D{!RBnDE>u!^OS
zS;qS8hS`_cMGY{foE@NCb_F}*I{>b;#&`dQ`dao~^1g4dE*WUmv6bflY+*l{f{C`W
zz44IN#-62UPCNS#MT|Sx8x)f7WM6!VvD>W47U1r%>N41Lm;Lb<SlGqZ`~fN5>;Q#|
zd)Uw95O$CKlWx+z?6%S1>|-UyJPh7vpB)Ez%D#CDo<Y_v2?jr7bqAs8Is3&hNPEG~
ze}c}JY+4yOU$OjDkk{;kV2pWiH-}-lJh=?IX9jT7>E0E{Jza_!9^|Iz!4k$TYDX)I
zd#C|RG`DIa0Eyi8a0-zpaaH6vXK?E&^ODIK?}9a-bKeV6z$yB{Qo?Pj#bipk=^sP(
z1+F>_oYh>B9;Ak|rvTLzZUt4CUFA;y3eIcXA9WbJ&Q16VW3^mn0QBDAQuo4`I?jPU
zpL#CJiK<X;a<k^Zng-5|f`yIT-+drWoYD{E7FR>1Db1XJJ@75uYN~T?<yO;|y@T6H
zY0XaVENv=pb8nSE{T=Q-+V*yHqsTw%;a<H&3u)R4aQ1SODAn1={ni80&uv&tRhSRC
zz-5sAh_j9X>nm=S2V^@*KBwAOXUXzGjJZhk%RyWviIk3UlX#5)r@JJ9QsG__FKcM>
zmITbj%J@na^}rZENm(4M_m_;ND=<Lv>rN;Plswpuu>?sJRcU8PVv7MV=1Y=_!Fpcu
zO(J+IBqOrW+asB<hdy6v*=<<iC5xh!@s;IMsfE9+<}6qa$hsRL`;cs2CWMB|%3aYq
zEc>0Jk`b~<O79<$nRY?uQJGo;d!uE^-@(vW*^g$B87Fh)$QYySj5m4{Ww%rink2gr
zg~4Q5aT|aqWZUR<HL0>{+H|DJ{%im_DXYSpBL44*68tNe7muMG+mcOkXk5D95`X`a
zy$p6PoAN%4UfwwkJS!TgmV5n*`w+09k#0R3xBi8{e~UMEgK4YP=KySrqT-9~I&u~4
z%?{xA4ySf#+PRCSwi`Yj)}DDrm$N(LehKRQm`PMK=g;&hAtivBNJm5inav$AejlS6
zf{BGOk@Ofn#LS^DcsO&f0^~5$Om9bxV8-93ooyPkG#}csnT3=zFJN|%3w@3myA7m_
z>7xDDWoG$UNW0FQ&V`K)3`+%%ZH)CD7}LY}b)$2D$uWgcC$@^*nSJbGWEXKm9On7|
z*OsIk&=JU7c7@n|%<8d#hB3yf7GMuC#gkxjIO8}D<S?^-0(8bQ-+TtvW6baL_&LGI
zsH{1KX*vNwD&w2|pXJ_^oycLLzDMgclTN26a+y7M(Rq&Ppn`()%q+^FRxk(Xfl<k1
z+ro-kCU+b<Z!mX^lOU~`NlQeth2geBMJwY;)dp?MBT4}zv8LYxk<2=E(<Q;WP>eQ(
zeL{EkR5oG&tu*$FPeD$yA6bB;vmcRDTh6v51JKMa90hnJx1F-9M>&TL7>nZOR6s*C
z=gQLkCx-L;5GxnUot%upW8BP<0LF3GcA)b(C;SbTc&>_;B!S!P3VRc|W0Z{vkbL|u
z#sVcD(Ux(a<U4xK21)YhxM8rQh60%(l9E%fX}=_TDMTNTG?32_Dp8uD^PpsMH2FVa
z60sMELlTc4p*LLel)Mag*%CUPmLx0O0=+4+?`+Y^kS(N#Z<efu2Ovk*LvKvWm#s?&
zOQCET?U0IP-{SBTB3-sTI0t0z;o$T&>8F!P$tEf-Ixm=P%SG#wN$qYr=6K!23a1hN
z`$BcG2WfxQ%a)&lnf>e@dYnIDXNAC^XRIH^nLIg*I`03tg$HzAV%qFftjKJgh`;AN
zz6#wxlv284u8Q_D^Xe$IK3}A0;exqzCTHQ0IKY27G#@gT&3<OY@N#tqj9kHV<L_Tr
z$6;XQw{$vemDP`c{eEu@{{AD6lKb22mtX?h7sr5SkB)rMe~e!N<<8vEW7vcFf}T#E
zOm00oy%;OnZh157D3_DWd{G4c|F5@ejf(2J!sqTga}gA|ARx98u|_~$3^NQMXtB#8
z3MNrdQ9?*na8y(nbWj#if(8}A7aHM+(Te1ciiuHEM`N_MJ`!z2#M<Bs6O1h)UD5~v
z@zrmmf4cHJoyA?>-TUm<IWYI0bM`)q&y{tYU;09Et%J|gO5teUYB{fr*ahx4N|!sJ
zUU55t*c+7gF$lO(X}=BXo-$Gc)v6@Npr;*5`FZF)Q>r}CRzw<au$9m@lzP2<G!4%}
z=y6~BVkE{N=H=zmtGuDosl4kz6kW=oAXs^#=!MZR`c$zWg#HU9co%|NNj2laETV%x
z5M52rFTzwYMRK|7I%;Zy$cN;A1eUi^kUOYPXvJJmC&{nr)m-~BW$yr|fhKH*iR-kZ
z5e9FNmCy0rq|`Jh-J%7Y?koH!9T^MJf6-vB#%m!1=TIKdnVw<>n!&5*hqR0^x{vAc
zM0BB>4sSrPrE1bMz$UepcR#nP8<(Jy+tl$~B44hqL$`Vc!pEOyTaT3O`7qS3RPv;^
zL%F#ME`L&5xAFc@r;^B<G+oM9qrokr<cywf|7`_)ZlJ}Hu)C3NHo#svEj<nW3hGyn
zHc6wIxtpGqLcNOgEKqx>7mrgl*?3QPKiMPTzJ_W>Lg4^4@^ATbI`JHi{zU7Wx&G-S
zo#U6rDRS+Gr}Ok07eIVP%iqHwU8XZ!sDiCYUd-H};r!ygNf&Ox+AUIe@BKE-;w63~
zt=fmSJJdJ>df!n6XTQIvqgUX*iAsF{cPV&2diEoEWWfC+8g(8}*iOG$#bZKGc0=(e
zD)<$+U6jPxiEhe&4_$jgR(@R+sh7BxWwq+}Iz+0}22KUnsNpRL=Fh4>?-G2gZt8@w
zJ8JR+i2Pgi<uzW1+L(y8XX<}yA-TqIdl!O{h6k~*SyO1ZG6Cc%!{Cb$y=?gK9^$@h
zILYS#It^xTSX*!G<fm4-F{2sON5;Ne5mUACvx(^MUgNktFn4PAIT`auP3IKLZtWtU
zkf_oIKE=rF({6J@tVZ+p2OQ8!`AEj6+UQTAcStMr<#g3iEn)_uaBAsupmAL5#!Jh1
zLaTfY8eeJ$LlD|2?QAm~p4Oi75#YaQwfwhyM)T(H{aH=%g5Ejp8YeR^Xji$?`jYlN
z9}KM32EBt|E^EtHLj9`NR{iQ>H{p0S2D~tSF0aiKig=|qalQ-m-|$QZ=S^=ea(k<d
zzrmBdcS3ja4{c~oe0T+FNht?ld&*rx>(p~k(D!NKCOA!Q9}Z{Jr))q}GY)Z@JEiRd
zNWOjK@34@1ji>kT*yh4=S|uN!|3je%C!=T9xx&z_dM<UEJ)YMt>4ys-n$gK8w&r}>
z1QRwCzhMq@&IHapmp!<j?=cbl%y17#E|_M;{lc-^(Yh$M3L$1?Re+ye@ew%o+IV=$
zNxg?oE`E3ip)5K02=|VHkl|>^YvF>G<=3Opuu5^`wE8+_@^4|}w9<|Rm{{Q{gev@8
zWK&;C42>O?Hgy_)-m-?pE={*3jEkFTF<Hze%m47wauzL}mznKIlg~XVZfIU+wl$39
zOlDJ<Im~K~2(wxu%#mricKaenT6$)7sL3R&JjuVe$%NaNKk~8%4f=mO>@TZzn*9rV
z4g7`e|7;k2o%vo=*DC)p-RL1VcJy&E1_XzNB|BHWpq5K=&|-HVncC$x%(>{2+TkA)
zJ1R8UVO!z|&6vGpQC{dcn`2?FJts8R9+ErX7LsMRXNTt5mn?MT%+9buCOah8=E!wG
zE`8}dA@{VZ{fnzwRa^#KMqC;$7hJuZRjsZe&VKPz<7Q4D`(|=nKv;yi=acNb|FK)z
zG+CTu>?cQ*yPKUKbh$O8$l!3*OFCLrUuSAk?~ZYDMVrx0e)F}_)w!>t_kzd8fn|N1
zfo1ML8f0X0Z*TeT3ksCWzU<Radi>t#?p$8(9<pLUge5w}5*=<C7GSZMtR_nU{shC!
zBQ0UhGoF2|J^|6;(Gihmn>8}p5}q-4c2rc9%`(zzwph~V%o!POi!AmH>Wj<6=^Lci
zk1q_uyBuGA(aMNxKrbL({g?#^!rm_O&4S#8Kr%~^E(A{t$V&((qqh+E7=4Anv{evx
zc^5MNT8M$rrGY|Vsw`-b5XTq?3(>(iM2N9{fJ0F<kPqV&B*an1VM6@CI6?@ozQ7P6
z3~)-Q%IeRE%<FJQod1epj1VG`5i{BhM(ofnW5nB~gfT{los7Q|;vnN#A^yr3E5tR%
zI3xv|`DTI;PZ$$~7=tGSy&=SOPbb;+NR%*G<){LE5(QgjX@P#8qO5Yt`=H~k&g%Dd
z6H$uQS-(=RCHzm7Jw<w+(k2J2)+du+j9jo9a#3UC7eJ+1x~^gNB$>Jf?0_V>pD`s#
zb_10%nXp!$tQ?b-07{u6Th@YmOhy-j+bl~Ma^!V}?Q+<<9?^V;@8kuBW;vh)FiU1K
z)XC#7Dc4d^4f1UOrHq#QOW{()$ZjCaC9DVA94~jQ2U#WWgH*a?^oAZoB>?i9A#ZFz
zV}l&F5!_=kA3y<V^5RBtKa&GCflSPh3pRl~CXX{2Fi*N|hM&ZFG8L%omHRe>9hE7&
znXHouWiWMGR+i}_l$G*anLdQ#vt>(}9%xJrAhA~ZY|)3HW6@jmAbQ<Prf<;$mHDy+
gq;ggsV(60BUxKn#5Axf)SQkV2`TpvIIa|-?zbwPA@c;k-

diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
index 4af989867a47aca597371e24739d261a45983d0b..88d9b23fe3f3c9fad98b6999a3d8045b3657cb91 100644
GIT binary patch
delta 128572
zcmY(r2V51$_ddLP@7=rg_JSoEd+%LiuSrboHBn<UnwZ$5QDe*n8x~LzqzE=t6cE7<
z2#N|=5mZo-svx3*AXY&1ea=nt{k?xbva@sMInOyWyE{8`X7;+S85p#B;I;<r+G7o8
z3hJ5_qPM$H-|=G#%PbZKKjD}q!raaxvs4(C!ZUveuj(_*O5rca{}No*X_>!;Ne+>5
zu+QuQ!?5SBvkc41vt&lazOe9&n(e(y#c0^`twn}ob;TT`WnYYt8J_KRRl^8u$}W)+
z+3E<Ek=Qp&Sw?0X?UxyaO>xxW7#-{5E-`v`;a_UTz}CtV7$ZC5ClzC2$5wKTnT@z8
zF&4JvMipaa@8|K1jSb4=89V#!1%Yv4pA>1BT5Qe(EmNBf?ZYv3*aqu4rY?K^JC^y3
zExV>=>alA+sG0g~u3p1@&K6JMnFg$3BFi*n7lb-AOd~dF63aAZGcIeHCT!FYk!i}#
zxT#{Au}2ySOmp^&7b4SweaJ~nOZI$_ifP4q|0y!9*|OOJ(}taI5SX^?`vQS!#|nLT
zraim(q?YNxW=UG6Bm1ZU$8=)93z3=5>^`t{VPCqiOjq`Oq0Dq+>kC>3)1B3n@JtW3
zVgbwaWc^2InO<y{A0*}rHf^1n>CJ{ksF^-&#6S(xmu;%nGX2=g-Be6}_Ja@43}El|
zlbM06e~OkF#MYg|GlSU)o7Kz^HsYDU3}rp8YnWkdi(rZQlC2h1%vWq;jhgwIt<IO3
z;q0)BTE_7Wd*_LU`If!kT4qMD?S5pLQS6IHYGyR9qxMM`nGyf~Rbn)|)vXwY5xcBb
zGhFLhb5#tAh3e07wN+g4N(fc_m>7W(Z%*YI?%P_P1kiBnRJiN|0w5Y$d#_W(*YB!g
zIDzBO2}t<VjyXJ2Ps7cbzXW(bQ3ncDW0}#`vP=hFx`czM8_zP@HWoKJzf|TuTK;@e
zWID(Av(ak!q*~cWW&+rFoHtNunn=t}r`%Pw<g~y9I^}z1KNl?%^beku*Fj;|KMJfo
z^`@HH{f`DK>%6bX1K6*;CFPf%olkMhL00n?R_z|qtd)bQqorylmVF5kqsq@$GiTWn
zoNH7wXE98i^ITAsd50_Qn|=ACmbu`RG*PLbaM5|*LiNB;%Up7vw^4nF+^)0h#^L@=
zc1n7vwtF|$wbyS*)iBrDNiaA{m3hW{y3Won^<JiPI2I)eOe(83XyB6Zo$3a;lvKzt
zl`3+BQJuTUF;&iUjWS`tH%ztjTu@EpG|UI`f>9WA_ze|Pqf&cA+1}=|W|kI;m0xI>
ztD1l6MTFNh&Uz_hMvP&uJI@7G^cFn-H=G$owREz;q&Uxws<D5F%uVOHRaO5E%cMHb
zYpK46Jk5FjnW`D&x18q<R5KyJ?L2RyY6tlp=XndpoP+x}U8BAa&ua5?;VmDt3Er{Y
zZi@`laO@DrIEKYdqd8W>GL4KvJJHIc@oVi6m=1KGFq%#+Sf&%5vYO9^@=TX}oN6?#
zQ#qz9Nd?X3H4M|;c~5DYU(qr>=~U7*xh^wb(5bAcmw<<jP8E%06`6i?s?+>ZS7ruW
zQq5r)y{7D)h8aX+10xnqk{Mx$$_q|5e#HxnI*--C4@QqaHmJ#j?^TTYE{jrXcoJFo
zFIXm#B|#6TU@mH)J|3%P)QN0sa#!WGgsIcfJKIo;UE%%4(A2zQm4;CVvn|It3zso<
zyuI5PYdM_a?QHA+#4cS>A6F;yXHI4X-L%??a%G$U59QOAV-`74ZJekX|3fWeoBoSZ
zbE)uW5$kL|mDfVGt68G_w**#s%~dD=tsO#wIsXWLVd|3SCdxH!HUV{>z)B>cfB!Uv
zrSnDVH%YJoe{4`F**)zom|C&3y*ryav0c4qo0_pz-kzpjj`^uFbCt0F)MO>DzJY3T
zwaI_=u%7yhWn%shvim<sOymDSraTat{RH`^rAz*U?Ekl(3k)rbBxe7=wfx2K%mDld
z_^m}He`;~e`x|p(BQ=F*oBu9M%P4P$xsJJWyozCq_)h<cTQ&6#H;-^+rN|6Bga4QC
zCucJvKkOgabZ0XnKl^8AGftsqB>aYd@{@GxH)`f5{$Em^Tu)?X{hM2;`z%{#X8)U;
z%h;aPXPIHnELCte{@5Vx92srOdH-$s+(C6=hw;DuLpH@p{nh_N{q_GtJ^cTummcDo
zcK@Ru<)ro|X1W4wJHGpW4Q$*PsbXs3{$-ePPSn-^p&YgN&i~y^n)6Vr#Si?)m4%Eg
z@fgpj{%2sYQ}xyVR8@S}{~3t*$TBaTPfu?rsx}^?f82Pf{XaL-%hb%H{~xNK!dU->
zJ<|S<%=UwKq?MkjE7qnszOZ&;*LgRzS)C6O>#yzjpVii5UZd?iv~|c~`uERGXzW!k
zFe{v9zJ!ns>VPNxpG&+#+v}go&DGV<mzb5>f2-<j^}qhjEn#YnJt{EE)wNRY3d}rp
zt;2SXnW1J*oU}FMKGRI*7<E0#*_di?mCRZ1;r*emt8n&)-Y@IavHR8_+eoJt^_=v3
zeLS8D$7%O@H>~@Gs$iD)w7M>A2k$@Xey*$wlo^fs5NqQ;-{!rq?tFH-xAC*?>@x2!
zKkMLlIfG?1P8%8xgHD!XW@)uJo^iozocX(u&aXa07t8#SOn_cf@v3HaGBS>l9|+IB
zBFs=NhvSk=I^J0$;aKZ8lD`YbJDr)FO!%LY=vcmxj&lwXTaM#*N_v-(=x={Iw+$nO
zWw{tWFy2ulFWO3UU$nxAf!QRJfm{8l^e!G^4*eUQPrX2Htr|x7A0voib3AF?t4F2t
z-jO7KE}iF}pmTW;=~mZvklM{(NUeh}nU{0P>$@MxOnfdu?JU*)@KTbbI|!N3pCqnV
zsfGG(CWh1bguHTxFb(^Xr0LgmzU(%cRDLJC?G^C{x24j>A#^^ho5q3U?HmFP-Ae^N
z{m6Xdkwka>9r^fXE!BIyCmpYpk))(CAw5<Rrh8{1vfQE4C=7QvW@IOFtMm<(9vDvN
z+yA1L(8Lh(ND=Xmm`v4J@(af99AjuhP*ZI>mK-4H5NADJjw8A+dQv@N#!wA*;GGNV
zLnP06POiMnBK(edB(J}f+%jG!xvGRPzhn3awlQ>^QBIQhC3N22LTv3ZoaP+N_J-t9
zo7ZIK$R47|$RJR^eFR$KY>D}^N%@KgNxoT3b#3NJl1Fib+<cT6K1?7d^3IT??g(=0
zT?I)3oOf7GFr9boObkBf$;I`DiNWD<j0{h1PZ^gkL^Q=rEivEOyv57ty!BK%zQDYL
zV{SO*K2ArM)FHaQE@W)>HFAA<2A$u_AQwxW)u@mDiep+$C-aFGvJ#m@JnMW3IoWZ7
ziW@s`v@8DP*V;5X{()gQ?tJHi)apm7(~X9NbQF;Mqz_?={hVg3WO$JC!nIyZrCoZE
zyY-`~bks?@>W7Ds$wnBc;zB#??PnuQyU`9J%J-wpc)WA)$TcC*hFx?VVy0tJ6k)tB
zQfcjGbbfFFkq-KmN<TR<<#WjJ=<QUe4?mMJ6<%Z<Go}S;O{z^2y^TtP+(>u%NUBm<
zrStyZSx%WSOba;XTXfvGB|DMYdXW^C&n2R>4@my!GeX{X_7(%3jTu%!n56Y2|LZZC
zDeOh{?jw+-ZyITBc|<KY%!f(`w<G3=Wa9KfZ;ku^u0qh|o>a3lx2eDbV*uQeY1FU}
z-_iL@kti<zMUpR_&Ava2&i_WYi%v6@bkl<f8UH<<TVGRY$Wbymv>wSbJ;+Lj6(rx@
zmaLq9j|w}OV7z2NYNw+QI)7XOcRD8SB!yiTl3zSe=C?Sn<^A4Nzr5E}kK(n|X4CCt
z@|)=-@!dq{KkgySA`GZFW`Qp`u_u#E2I`2}7Eh&n;|b~5cZCdujd30^&qQxElRz^s
zk;%$pq6qb-<1hK7AX*7?Y%dueX{U2{7jm@8HIfX^qw|nR(#??Q_y$8KbnqGEM4Js%
z+F}W{$90V7IA*K^lTnTtIGUgnF$u?uVJj&-Zc3nbPLR=^Ftrd}!1WtS&Z(ACY0txS
z^iLz_Yyx4jvWOw<1)Z<IN+#R3A-3>8sd`KAkUZ9T2Mje4o3zo{pK~n<RM3i!ProF(
z5ksl2wn?ORY#zx!b9S`rR}$%?u_Wn&SrYok*F==Qht5YXCM~b2WM*Fy=}sL;E)J}r
z^M}2u#%VNJX3_!)|73<p{r{CFWU>@PT8^2pn&?(X5K)ssMAUQ*Nd`C{n5BrzpwEvW
z<+dwH%e@7WejY^zyn52nWFSmH7#)j-)3MDdLSE`aY`%qL-p_@QIg>Ee$3s#{1tV9}
zv0G0veD-^)<*^z%H_xUf^?Xfg-#Poo)5WCB?<dkJr^%I{&Jh0UIjU>Db5z<Zjttii
zBKee$#IviE_*2zX$yNP{^X5F@9Zcv_QgE3@3b9|2!rNn{FxHdKA2{C&fdWxy|3XeI
zyhTJir;t`%OqFmq@I=~mDrv1<N)kUm(jD5B+NKIaGxR8Nbj)l_@<z@#%h&6P$MK;*
zQEyA4qr-~~C<#<>dMus0_o8E!D=Fu%CHdw#M3FY1s2|m$^Gz5NA_7yNBoDjOd9YoB
z<GZB-jsh;3mRTP~ZVmQR<GlT83CGzkJdQ6MW2xRfcTr<z`IADw-bA|DISdJP-UqqQ
zY5q|!pK8hGk`u!|k@A4|M7nPkU4pombpFCdM@1my2gH<6S2H1Z&!=h_KPRNCijD!<
zTF8ZB2Ps6Bk%6$j1hxD~KCT!=Ub}ZBPa_5q^wmykq2Uz>;xXfU6K2u@I&Pdv7a|%{
zWZWOl5#MihsI{WdiD{X6OGuv4n{;P<PRCUk)M%L&CFDfQk+K6BcMKY}%(W3@@^vt&
z-ADfnz&&y+z8BTl&v_p-K1kG8o%hNc%rtQBPtCqP5_1I_yw*<p6?Jd6MuYQKd5h7i
zgI=t_`MB4Z!Eoafs!%#%=SG}Qe6<allN?`81kL2t4dL5&Tj*Atd3!O=f8JAu;)NIK
z3NQOeLrh1PCXlRQR}4YBda%c@An|2i(|E&=ZHNE>=g;1|hFkz^`3uQTb`RnuTp+8O
z3ZuJN?hUN&W?S_}#rClIAyD7Tx;egvv3>0DOhAL#j340Ze)cm@=pSIaC=ecGRYq`!
zuq`$qIm9lf*WO{a$vCiuvVV31cNp7yI26L!JO?U#gq{5q+!1Un_1Z_-GP?64*{0_p
zjAHvDg3BFaYv=`doXw%|4R?Y~R8V-54fg@}DRxN_?4D+mXq0w_^`{;>njPc|wiwnD
zg<LEfat-FsvhHC}k7MT?gD{@;qW<+9`}bZrbDpjJ2`mZhGU|vfu)dK%USuEdg855q
z%uyt_*fBa5{oif&+di;+hh6g%8athR76k4Lw(1fz?y^mj;AtisJPq6rShpl7X0dOm
zU(064wnOre?O6eX1+0%1ERR`NL|(Wj>}T{cDQ3qtfUtzUjY&UO%63<w5@qbMS0F2A
zD?bV7|6a0x&j+-EO=M8`iaq)Sc3-n65J%?TuwKJa_Lfbb42^eei?_(VXS3VE(JJ=N
zJ8)OCzVA`d5A2l-DEq_~eF5`ss^>I}TCG~W10HTxxpDvApUq;a6X~+$YpBf6#8Ak=
zEqD_POAC*TgxN(~e#iOZM*SJMi~o(%I{@B(`!ZCpL;YYJJ9a=1!*%M}48}UA(Y?Eu
zU4og86RvsP3U`yXISsq{-HkygJUs@9Sj{8MLWB*Yeu8@~4t|A)a1C3ZRipjavJKJ4
zYd5fC6H%>=?CIv{hBmRi5T)TZvwyY5!?~M1P6OCIY-fc2(GFw3f?G9g8p2Bm=bGrQ
z-K6U9Eqvdhio1zifU52R<o2j$d!Yd$RUz}CcV6YS8G6@MO=>XVBzFwc9m`Nq=g2~!
z8fv}=UHhNhQPAgm5y-J26c?V??{^$M*b@?52w~U!0&E;x<%UY$WV^&7F8rFEwCCR@
zkao@hp)n1w0d4DTw^7YDm0FR}w(abS&ZOO-)dHhxPl07^hk=7oGe^g6kJ0aR>Sjbc
zb&e~9(_P*Nqj9_bg#ZTEZ3oG_S4H7!_L!A~W6w$&ne>{L2J?fqZi1Iz$73CX8)I+-
ze(Ky7!2B|PICvJB+M{&&AT#7{>^vV-ZUY;>9NgY4{|O|1>}vy-8t~kYP>@8h*?N$k
zW=kf*?P%8NeGKb#KbCd+f0lJt08bp%Af6?!wHH}uO)jxi6KAtZHY^EnwoSQcirO=a
zaI7mGg~5iM;^Ar2Vl)NU{K4mF$F`1I_2FvA>)WB(dHsH>;PGG-^r=mkv0tr4@Mv((
zOwfHbnC3_$4oJX{wP6*)Y09NXIw<R@+alXopnkrkmn)84J-WecKUD)%_p9g8sNPtA
zdg@%+fi#qMV@m?Svzm3pPe<0DZT=DD0c^wuxVDpBOYikycKaG|>}Qo~C>~%t=D~}j
ztgsV`k?g{Eup7lD*#L=VtDiwVhW+_Ckg@FIf$%1gO>~7q5<4&!$Yi!E0#!+8fBO!Q
z40dS-%-&^FzwZkDA~v2z|4&#gRi>C-W&`vsJNX9m-?1-S!QgxL(<TVlt19aP>8={0
z0?h{15(I%cUzLQ_3C>T|YZu7;Rbg0&;zCp_y^poEIz%_f&Zu_(1$?y1cnOrrs+|<e
zxU9NPmnl^>OpD~6Dxf8VIVvq(qg>UE@v!qqH6#X&S)@An7P;rDAQPJBt*Rpy%Q#o{
zj6a~aPJPJ)1rK$~79c&<rFQ}GS08x<vjOTAjwXN}P|tD$^q{)y7$nEky>7zNadn+v
zKzczvYc%vPsx$Gfbzag2$A&?t@zGLbn|##?4cqjX<KMD@CJbS?LACv1Yw(f_I3FfF
z#qs9}>VNOOI^CwBEm{ux8KiCY=Ft14{rYw|cG}zsgk3LE@S?{(yym$t4$pz4@6Zyo
z?|_lx;PBx1#Xx=&Oaqv4#qN+#IZt!3pVrl&bne{YI4-D%)faAYRW9mqR+}&xHHy=Y
z-3p`eTKxzVC2FgG2JbcP6`97jx3zCK!dRwukQq!jcwsi6ulS3-fpHV3tDxZ}*7^!G
zC-u2BCpxR&^8uE<jG<$Y^D*X~{r6r!%HDki$FkU^7?^N5>{43k%4OwU@Z=#IT^IC^
z*fINYp$piS5lDPgeH@7YqEkF`42*uNMs)M|tM(yE&Fxefn?Ny8mD>nxyHt~^knC11
zzXF=Qs*aP9+oxK27Rddoo+DB51FD%j;N>ZmAsWeP)i|0@-%>>ez>C|e+Bab#UFA&^
z&kWV_yU@F*(*No})$gm)DJ1nkb&+PSS*njq;Zu$(t~-ReDzAHh=BvK_9T)wfDv%;f
z1uA9%NDEb+DEwEXGULABo~Yum3d%iIspmuQnJTatEG4S%J3*mT6(0s_SG9RH%G}iB
z@{p`iiw$UgvsS(02k5U?-$X2%b65XF!|%iDI`rg*st?k&x~=v;kK7&gD+6dU)GwC<
zc~|}96omKHB25@G)xxiECQF?{ljm%81<k&4)#<aKo~NFeg5;6f{U<a+fx7=;<Q}UF
zI!n0zMQZO$xE94~;{(t<Ro|f(?Q?b0<=`$+CzAOW>XZAyR;Kn<LHJVL;WN-wsFNs?
z_FDa@6V%_R-}oZ;PVHNXs=Zf-&|9EN9asp3YV{kcZ;g7L708e3Ay`b|+%%`pqY~=X
zn#SG<9j%W3SkvS-YDO-Bq0O4|NLcXDu+&3s(fBYxZq@w$5b9nU|9wDi*L?gN_IxxB
zEUj}pG%15o=BKgtMB=ZBp_oCSX7L$7f;62d@U~kM_5f!0XsYW%VV~y90+a=7#>Ij9
zpys|~8|oRNS&#sK4{IJ!L@-qIcq25zHLC_g<A`QlPvnkj-ZTVTq~@A0yf~&2`a$ow
zro})APikss;hLY)40!;BXwBF;a3)6ct{ceCYPLl|Jx&wV5|DG6*W~tj%_Ev0UeFYb
zaG>y_Cg~<L5;Y@C@FGbwusxE?n%^=ZyrSuL9nfo<)t|xd>zX|Zk`&Ftp@7`fxWs@h
zO;dj$SZ-;)^@B4QYi0tHuF1Sl_lo9Of3V!sXzM{CQ&UVm@dHgYg;}#TYoAe^DM!=W
z6Eu06d<~L(%_*8B7HFbxfu>NC>yD&IbG<9do@nOgz{FFHPa6oIX(Dowlxj-p1^7Z!
zyZ}v7uBk<Ht(O`N4d`BJnyHa{tr?e#vbUOt-cWd_dA}TFm6}Fh^SBSIG^=ib^n>Qn
zLbO+nrq3Z@T)F3Oq3_0xehS4k+{5W;gtgqK7I1AnH*q4`(w#HZf!&SVW(9hixWhCn
z@ZhS9Kzec+Kf=UTE;%3Ow{c%hhu(Hh7!9E}x9|cWzTCKxu;B3H4i&>-0Cy`9(w*Fr
zufQF|sp#dli<=P${XN{iBsB0|uDA~%!CVoA1om^DnRE+r!)>q|!ks;hTqvg<4NGC%
zbed8g;Tj(SGJ;D=golw_QUvM}#fkJZoZvFbKz-7|wGV;$)0|%>?4IHJVQ&N%!}X`o
zZ7k<Xv*0+c@E#!XT<jmvKhLe$4gCZzm_}FkxQ9W=-RJBy<H+JJ4251c*R>kX<Z|c7
zpe&E`IR)WE?m`IEA91Z|EufJ5Qv<gjbB_9Dz&zpF(o43O+m#AWUA5m`M&hPjHW<P+
zTHQkUv{w7)I5@Lj+mmi6ckOt3U2N1o!;S!MlQ!}jaC>TtDYUgkJCcG+UfN;w8r!bz
zb{Up-Xp;?4@YUMa!BKzhr#!S%fL7zU1Wcedh5~Rw+DPmw;nKA42O@V%dwCk5>Ds|G
zhRM)wodTckX`6ikh5OpQp2$7W)~A?pmiAy5Aak@!x*(UUEgJxT^R)x@$UW4~rJzlL
z_G2AT7iwh+I238KC|veLJN7r4=Rehk9EXd~v}H@6SfbrO4bW0;;5Aq(*ESKs{ZhLs
z1~jj=lW#%sjkfv>kngoo^WjCMcG6pvebA0th#J;tZG)lyNt+rBh%2vD!NO|(VLHmz
z@G&2eJIcSRL=wrzykYSC9ph7n!NhU?-Y&46<h#V7flu*QJAw2JzmozR(fn;0c4PS@
znn9oCn>2$ko=>24qjUVhNhnL;{cnTx0zZL<rk8lz6hIRB$7di+=5ul&yv+B!218f*
zHo>UbHU23&R0rPtH?VPqOW}*ZfWcHgkplB+{DVWl+~&P$R)2>-K{sLsKdT3lyL>kq
z-rwgtl_HnPch#ctviR8_;C(iqKmqz(z9b&C&*L}#0M{P!Exv}`NBrSeaON?;$OE||
z{`(VPaXjTOW>DkvLumo6l=mDB=?lJJE$F}G?FsOrf<N04$s0b3LOpMJ>o<T@@>T1g
zP{jvOn6-xAOppIZe!y4o!c|z(A3`_5!wb1J!u98Hbghsa31`*|=@*f>3!yEcu+br`
zPlu&VLdZstdI)`2LeW#0dKt-9p>Qjp+k~(GhW>V;2i+y!!taSlb_lU+;FGVAd=5Tc
z6twi<T@q@BAxRe8mP2@1a8Nk*ns9j*s(oGXy9z@oLX#?R-V_dEe-)P|IE+&uy(Od#
z0oxs+B~AO%g^{~Kb5HQu2F3e=Zxx^q1kYa}#C|Vtn9mhf9EM(=(6$|NkA$u?ZY&V`
z68B@F<#Uu339UV#UMy((gZinEL4%Fw!qX?HONkJ26dt}1o;$`sqfD?+1HTkpMk1*Y
zJf5NOwJ_=x+<zl@4ukN$Q0_;qF07<cPPMRuf`K1|qSj#hBs8OWs;l^VG?1&s&DW4y
zBi5e`>UH8AYW(%$m77R5h&K<R5*x+Mf5Mr~;<QQ!On8X<pTpBFqMl}3TSd<w0QC}W
z?#OKyv-g5#hj_CwAikp44cPS;2U8?HK&+;2GDvKD0c^X(A9q2xSG<@H$UgBl&1CkA
z*QmcaAa=bEw?oA1gTQh~yhY)MP?3Mm<M|5{+qZ)kN5p&@w?>Go4M-xzl2Qnx#9s6q
zoDe7XhZiTssOjK7Ew-pYaz<Re0Os$CNs%DU6g_EC<$*Z+GSst0zvD=9#6j5N!R3kF
zyWxJy7qc<t<_g4z-Jn+}Ho@2q<1n%9-%xxaE}j6=r{X7CUU?=S84O{mIJpO^_Ckz3
zh1^T=212J?g*f3R^k0iJXj$To7*8{dcj8i7cziDge}$@5i~Y#_2XW?)sKiHcYAiTE
ziQiGc+fAC~4YJkJ&v!xXSSzhJqi~&cpf%Xsr6EbcY>?c-ptwnjc?jrcss1}aJSDw5
zAX}uFw1~M)`h|vbUQ(wuDD##qW1#0F?U@ceUuljF5I?D!hL6Xk(UT!OA!Si_bxOLL
zism{k&7tT>v_lH}9d5)(Bj}MiD?Jxc7$<eSjly%%2MRo&m!@LC%3Y9F1i;cosTGYA
z5~V$~5T7J@4gm79bT=MlSEQ11_;gL`v;dsfC131Y<Zeo*u}70jm1fhT?`=s<_U=gN
z>CmG|jxDs{aaVfO8J6x#e)Vw;GNsKkVIoWVoz~~FrB+3N<VoJmkjt04U`qz~NOEb7
zq(JIPYln}e$r#FTMbhu(NQ$M6v@H8n8n_uO&!wet5SB=95Uu83NGr#oNy?<hlR@@U
z8s|8Q!V0O*Zus_Eno|Z#Z=}(qki3^fTGy?V;(DRks-@QzApIa+paH^1=~*EZK1o3?
z5W2|?X%TX@TvZ$1@07i0J`yN@qB~)i?7I+<-SYf2II~x7&<9@ZlRut;`Tg?IOp3D{
zkUP>!Qi%MMgyfK15eH1DoYVm=8zxJmz;;A_MN_2+xyKz?ij?os03k|#o`bUEa-|GQ
zC*-X(3p^#apx5tdxp8yYjh1WTP~RB&ayH1$%AR+S#K|2FLU>-z?<U~+OOVsfAbU~%
zj#erz$vcCPOP0;_=DIAOBj{B*bP^0+lV3{k`-Z#$yDYgBdBZ{EQswqEXi1ZA(QD<l
zEWLsGJMwk9_8IbIY$4?C%A500c3)n;5xGpcaZ~7J$&m}NuawJ{Q(vKKx$-268RyBy
z(@=aUw<v)7kL2mIz+EV3?}TfQ<-T_Sc_LTL_g>W3;y82y7p6v*!lAxSnfEi2?Mg6>
zD!rAC+u?<ea;hH;?of)0k@zZ$t044KqA6tTuV_-B5THD&4GV$FGFnp$Qhu|;>@MXE
zb!EGioixqeqtp*XvRAp?6MFlUqNd0ND;ph2uyjya$k4S@*3kezR7s)r?l7eeb?Y~j
zB8m{DC>^Ooy{UAeTRv6Uy&n2$%9_qdZYeLSk=#~7{zP&|SxkEAN>E)S8H$J*K6h6c
zYJ%Q9CGI;^B40^TAbhAaDWN68LPb7?q*&Q5!?&l3@i}tOl=9U`o-1QJ!hDJHoK~hv
zm0BzR4VE-GMC%5P))qmf@$_soX_H?QQ2VA=?x7CN5@x~M=9MiVZ{gJ)n3jKR2VJYB
z6tHi->k2S!nzxeCb+&!GAGK}w-BUQ$p6v%OJ51-H(6M4DC_2@80MgEtZDFj7*OyT1
z`ol2byRA!xq<imj80hhmA~rp3b77#@8pKSwFD_8jsrMpU3+XeI;-39h-NLc|kF>*P
zz>6?o1{PtVhjR>S-U-mbjc9wq@TWsiFsa=Qoc~;_FDktJ&<z+^&Gx5xwI{o-9+I7G
zW^KUsuvaI7@&LPG5rm=aM7o4W*$e4BwDErvzjp^<oB0CjI6e52=`iidr_lgn3vZ>j
z-By0B!v}@i_#G4x@#0%hTx>i4hz20u{4|;s`0$4*mav1Lv<5<7KCd>AetdKz(D?Iv
z_n;1ed|jH52Jxdhqihe~j&>UF<yTTjaUXx28X=gUvJ_+o`4Nkt5W?%%!L>vD)8jOB
zKFrS?hr&>PFgC?<Vf^yx@FJXlJQsG4@LTJHG=gu=AvwxFrNxv;{u^58iQ;c9f$$g~
z!y$K^KRpx43H}NX6DRpZJ(5#=%~rI|X@0{3=$+xKX-*T(-=H^A3}5h6{UZ&Ck1U5b
zXZfK)@H>uoY==+reC#D)&hg_vAvw>FIS1iIUZQro#52@KCh|ozj!)uO4}vh6?=}b~
zF7q+_;r122_8Zu}%I6&Po;I+KqiIJVQ+YlIkTm{xBNT4&%Lc;iZ9X^ymmq`JllooW
zPI2XXe1bQU`+RgiAT#+TO^`g`1zLf~;;&J3CYyJWz?sAMCqudXlXR5j@fm-i?eh8L
zo^baepV$g4k9f6X2MP=L9)+MO<m1<%@G-BarSu{`sWI$6;jhsQr<nIAyHEM86eoSg
z$Ixu;Ip3X@?n-!Lf0UK-MRkyS!T<aO=F9lRKqTdS?qzVk<WErqzJk~Gg%_`Q&-!rm
zHSgo&fZ`jTzXpSE`P>Rf-|>dVz*O-m1xTv-k;y3g$QSGd@)N&{R>WO}pPkcpLHiia
ztP>8C33uUc0Fn)YhXCXzA(}!|n}s74fOrV~Ls8}_1k-xt7C}c1yH$8_p9W~#gmGFl
zx0kSeACm2Y{uNAk3tv8hzK`%H-7GtVy7Q3p6KeZ_&0p{**8+s**I{X&Q1Ba)V4?m_
zIJ#eWF$f9=g!xz%;0_8mspAU~o|{2^NRU1Pa#-kK1xu(f3t>+O7bfhaNLRSvb`nk<
z5!NOH8X<VoCa0sqfyK~|6f_cqQNmwGksK4;MnQO7`1S(yP6*TcAa_zQE(GZ*VFJw}
zP7Bit(3EF{UnzJIE&OIcwPOTbI2?@?E>aBtte~Png(FUA)D8OaLQV=a&Iz$cP<UPl
zqiA7*kbeTX3qmk$Vz?-5dkXGL!tf0!OT<oZIFl^+(8Bp;q4_YdT@lpF0J$pM#M&69
zCZi~%eO>q)(+ci}@COC<QUrSz?A;W4k%y@c;pR+8(*)O7z}ymMd<#prg;ZK4z9Xog
z0h2BW-+(kj2y2Suu8=qukb6SgRB+!H_R&_EOd)Iqk_SRl+OL--be#mwY~c!B$sFN3
znnvdeUhZ%-Pk3m9`FtUk=0FbxN6A^xJQ9wzgnohW1qIFug_WxSeJm7XlPe}V`)D-t
zL@1|7Td~lvA&^f6&ty3BOqdh{OV5Q_O;J`N1k$9SRH*j=c3%i;YS=O%_Z`&Bg&G=Z
zycFJ^ghGW7G!w#CLa6t`p;pJSb*Pb_XmUf*PVr$i>JTWp&{9{B*zqZnUE)jX!FG#N
ztf<N!vC#R(77u-ivVG!|dGIJ$oI<Nv`^7?f*BuZ?(9G?i_;Ci35YhY_l0#zeU!Z<i
z{8SHQq2k~*NW#Q#9rR>}i=WfJo}=Qo)bB@%7ii@%N?fxExntr)y2X!+ZJMA)C&VoW
zkUJ@U^o7Aw;_&gHIW4xP^`0~0Kzfv;#nfvM#)!-M0U0ZXVZ$zWR*a@GL7bREqn3El
zIuAab6Mv3$AU!XBkp=w(@l!7(7sN9(e7`6L9|QD~xOX^`L~+d}IFlrPNiX4K(TJ53
z?y}gJR-LYhC(lCfs(4<9Cb=d~jzJq<7e`R%dP96b@8uLR?+B1L#qP8yoGNaoplF(S
z_#`&NaJR%^y>aPoi_NEj`;K^<7Esc~cNA^N5U11n>0R+CZ2-C_a-BeWUsRd`nJG4*
zRqO}i%7v(CmS`IVVYWER2UW@uf1`@#ikE3jktc4r0c5@yF&4Rp;_VIasZe}9QH?&}
zvABZzi6XJ-LtvhWrC&p_Se$kSG*3m<SQvaJj-=c0xmbN1&XkDVijgZ7uQmeYg{X9b
zUYYpU9wg;rI<1nu6mu@1N)=+sN(f(xb!c1PYq4(u^xlXE=xzB{>_P(|$2+m62{hh|
zNBRI$DYmnt5vxR*Zj)-!pW@9Q#L9kXk{WT|E$Dv~yJ8;=rhN18Sq0}REv3nwoAmu2
zkgk?`L_oMkYFP=gwbE5ur&%YdXvnc%8afdy?$RFzf!rW19SZXs9n#itKsQN$yo9CA
zQd`<q<ss$#hC)xtKpW|{Nb#75a$BVm3fgUxy3iV$mlPfYz3tNQu|RrD6KQDeE4BC)
zmi(m3RVee94pT5UK-w3BWT#~L7S04peTg$jTIB+JyQC%!b|Bp?^_>Fg9_cnU_g-mu
zSLpAPmM%svSo+Sp;n!BjP>Q{UNK^X3&>`t14N(tEjlMxHRC1%up<z-i4ba1-=k4L=
z5$Pk1TOy=P+9PpP>P62~q%?$fq(w>g)5sl@meO|W<I-=Z;n@kPfCellrAoRFPD#7J
zg-55QKZim6j5NYwLSeM@6;0e?q~7mP>sV>}A_&h){l<edP6`NvFkVVH0pU4mH|;(-
zFO}1#ngnSsO=2%d_h*CjqI9`8a+jom6z5HpHc==!Nz$%?rDRD<Ps(M<uM)`>Y3g1$
zb5+_A>Ol6I^z3t(xGv>jyp7rKS9HszN*gGUo+c&CMx))5%=9qcmWK5O@{Z(M3zpKQ
zll1D(klx0@nY&U$Zy3BMVGju&Ch0y4y-ca$PzWDL&2x}sN$xhVWJ?RWfh9*uyhgiL
za;2Z5pr0p|R-qR8QtMxVd5C#7D*8xDC`Va=)PrVRh0-=!uYD}_KL=!ywDc`#o=BE&
z04bJ+#h{{3rSj$|dnS2Mbp5&HG8JSc(z(A;rBdlPTJ?P)75su+nY0**gDaN;vE>0X
z>(&9FsgORhXoOdip*^6lrA!-yZzLaD8Gb9(=??Snq;OjFc`t=i)T&alP@h{R&71~>
zYANFe%05VU=R;T{<=2K6AEjXwR{tbbeT_0#c^d5-bCaWJgQ;V+yoHB}HS+zdz^s)&
z!~(NUo<bq;_40vG*majpv=qHTZkGg&jdB64b$Q6Xzd^xM{&@m&TjV5KKlhSjXqLZS
z?oP8ZZ#j^b5q#wX3jy(yb16vRFF&FS8Ypj}UBW>Qxq2_sUGm?nknEMsKf=U5*|Hf1
zgXRA7&`<~E9jVBL$UJS}JtP;?YDAdaoBEJ&`N$avkH}s$&Wn(F3Ys02&p*S3iInqb
zHV`F`q}}wG^wAYLE?@cyj-HU$?+5avJf&ecXimwlv_f)Pe!Ku|XXJ?#osX999DzoR
zJo_Y)Sb5}4l%18|SHV)8Tta({;^l<1$eok3p1|$%a!DB=39@}6Zh;GOdv9q(UB}lm
z08Ez09f7^ea@#IwgDdh6v?g~|p7jmvT$4{ybnUv_q%X8@$b;xXO_2{}gXE@shsI~A
z@)z{nq{-t~z?D1l?jgvf%V~p=WXOLn0`*-veH#qjlLLE!<-Xht^D+buIyh*5;{$p4
zBPeFcUFku~mLJlLCP&tJpwhW=5BdZoPk#0ocJt+*=*D{}t6oCkkvx18{4J0_qXo@E
z+0hevkL8$tP$-fU4}k26>`to|#j++E!l&}#y-;{2dj!CX=kjbbjmAr4`(BWi%BvC}
zeId8m1I02q46D;zxty>N8ZTw-6_~G()vjogSMt2NF!)*?L-EQtaxT56-pb?0LH(Uv
zLvFv9N49~7m9l*q6sqKpePO;@E}&)H5AwwTl-0<KqVWYT_fg(o2MzT}?s*w(u1YE`
zQ@SZVM#11}W&8(}ty3mwptxQ+`WhzO6$4$S4NB@_C~Q=6bKvME<?~*EY*u=I4ND%1
zhBirgDtBlWy+v7%&u_V{%0&vuZc|41z`U1oekp?oe7mxg#%bP4y&s_Aqd3&a?NI8`
z+}&5{^9s)RDFb&S@mB_PhTQ<ga}8*AD(=G}3{-02>sAC>QXWCLOZk?D(Yuuxx~=vo
zGQA@9Dn0cuzfU>y1*#ORn0^Lizp|d<?v4Y>P8!Y}RBq9pfe__3MH&w&hiR4Pu#&nE
zNvKjyk=!sPg=Q_`N>3V2A5kjr!C-_ELld&2%IZi!B9+faKp3SQwS(oDQriJb$CZT*
z;LHhSIz{16D!)nKJfmD_gj}>kDWqkV80F4ukj5&r&m%djY@_&6oHE)KH1SFoT1q^p
z)Hx2e^U7<AVI(Lg=A#iWC`%4P{i4!#J-oQ2<nKUPqH?_lOe86v9fm@(GPWy{%StJY
zqOK_K&ZF$A(x1jn*Az$n_VD|<@-@xRZYasbouU+e59m#$0WDvrDtBn=m!`P*z>8Z-
z5H<I0Wz9S!ca#a<@Hbs)MSXOJvOx=lyGni%%I+!YL8#$<rQZM;%v74L1muD8G!2j}
zrSTXfxk`oOApFi#Fc8DTrF{AcNrCcVF3cAyy_%uyv64+)Sg}%m48o_%;-gS}rVOBo
zLaEYeC0u)<ygv`UGNl_WYE>u^<6-cX^47V)r>v&V;Eht50+zSRGc$7U6djFntCXBd
zig{EkGiHM3gR+x$w$vysw6OG1VQGl<Nh#yug{!U?_0Dd(FE1juTDO^=?KQf>NZ4Jg
zE2q`Fb-I}wps-#SPNM{OT?lno8*~M<lVGE62*n0B>1KXJ*=F4g+WqCBn~CKjJS4i~
z6lLC`yWa%*TXlUWgKe8me*m6(>AuT>iS4>e6fW@A#dQb7N7rx;k{!DHH23n=X_tZ2
zPZtq^oWCx(H<AEdoi}Kwox0^)pdP5(9tB8{?kdfscIg_1L%3Uaq62Lk*`sschwNTm
z4Lv#gbm|RI4Aw26WtRQAcHbd)K-Ys-jt=TfUBMlq(|ryP59tQeR<^@BpF%hqs@qN5
z6~lB-!s!{&xzRR`Bf4dDDI#>=bVJ!uopCynNS%eYY#rArPf+GKp{uG7r%vkDQCRwn
zZU=38iq>@_pJH^!sn?9vHPFGtS>1~BK*s5|rGPtL=ieM<=X7nmz>D*`@9fY^&@EpD
z(hIse3@lyL&FKhBmvpf@<PvpxMJP+s?es=nl68L{hu&p}Zb~ntS9H0w^YN<Ajn<#9
z>H5&_qU*Y)43ZnVR*hgOMR$+ZY;NkNb8seAH+Cx6(sc1Bz;;Vl)CNA?*3Ih<g*&<y
z{gI^Wrk+AshVJlsAn)p$Z^A{pr#lc1mixNWE)Ztv94xKwX6v@neU+n|5eZLobr~{*
zc{=aufadF(Tt!l#yGHMdLfv&|@Kra6f(I{jo#|tWGMy_4%XM~ojlI+@&jw3{?j)^i
zzS0S_ndG&u3oSan(RC<A8@|=4o1qf#bax!f;KqC1fLc(j)Cm+&snTWsiCndAFHN65
z=)V60NsVq)e<UAu*%U_qq}%-w=3VtV>h;|8t=7WQYJIIQ;mjKSs);bMR)2$Drt9=)
z7C^XOe`Y)qcYOnVP0MZ2&y=CQQ6HaUg&Ujn)hi(N(Er>RG@kmV-YqB8b^P`vsJH9&
zi{ZVue$uZn>!S~t2q$*vQ)vT)uRfBtk^1S|^Z>QLehV!s1?XLVhj6F<0Db=vsK43>
zEJ6ARYQkOmT-r;rTfdKXX715X`3Vm0)z75wFZSu{OUMQ5=g=d)U!U!uVc!9L1`XH_
z>g!?8J{O`N?FC_|zV3G*4b%JWgS+AS;zIazM8BdwAQAdUwV`lSA4DB#q#lt2ybkmo
zoO_J)-=9TokL#zmfEOq9{MX2x)W6Zf?Nj<L_~3v$t@oh8=NbKr&JO5D>yz3+8lw-U
z^`}_<e2M~`)sLheDNcVU4Epi<@$~jQr;nxR)p`ByEnrK~Z=<lo1$|gQxOP#mr4`#t
z`XfomCF(s6!>1&D%@(L9>le^O@UlMTA!>F-U&5j6s@`&x_7Ppvmvo25b^Ry0WpC(@
zO+>X*^e<B&yr~cI18J)MTpc)?rZ1A<(=C1U2_SFl7t>zQJNiCDAWYXE+X7*R{vd5I
zxvO7E>&Ex=`c#nJ*WaBA$OC<C`u;CVzmc{-W$X7~cY%Y;(Ldb}#a#V2y8zA8CwG8v
z`FhvufIid<V^Hl!`cpIwFVNqn7iFQoR}FHH^;2j%`$XT^xssu;+W^9+dWB~A&-9tq
zV0o@Drx$dIUQ6rErTP~Xa(toxycwv=^xC#ica-ZRDa89yZ+-;7EA-Db$i30GUjXP^
z{VaMLz0?0n&GufuY!m#h)Q_j7|0;bsZ9%KnKOY6RKj?qx1A{gC#BCt`sP~_N+JDkt
z3`gQ>2&PtBW0*@{YOOWA(!r;7hU0f&XuZS0(T(A5i1Px?2E+SZpxJ16ItZ9e2A*~x
zY&HzA0ODb2UJe>h!?<IBY%yFdhihJjBfA0FZiqeyb#FuRLiprk_@fBwI}ATILbZJj
zA-5p(Gi-POh`-_PWOxx^I24X#r@`^$6AA+jOVlU~GHjwi!!E<7buhTwaNq?D?lD+t
z+sIzS$e&?%pFvM;5p3v0W77SGFxr@Qz#!5N+=GTN3XF#s?zRQwkfCh|^bQ+3(UzZ3
zL+lVB!wjywk%SwfsDX|cJRHMOiwHwk{CW#_)bNoSD$?-21~gFyS6`SoW{6~wJ8tMf
zD;*~c69eGyNyBC8-%c6aX~cKhu)z<IGlr*hdqf*11j2lbVdxLwj5YKg4cE^8<I_3A
z=d_#YyunKaVS-`x5eLj)F#P!|EL}91s57`^Xx|MqiH6G?!JTAyHUyTE4IS&k#1%sT
zJ}uy`8op@-FRmF9sF%EM=wFK54a3{x&`U8qr0GnmVb2KU(hN4buD1*)XxaI;VG@2w
zhr44~<O)OS2IXtoPkPT#dKRAEH$3bCFES0|+d}_=p?OniWEqU#1Db6ZF&OQYV_4f7
z`nd+V2a-HPXIjC^H!PhFM;{uN$T0ZGu=xTM3JlFkK~`wET@LEUhQY&tEHa!5fHO}F
zf9(Kuu^|boeGcxa;rARAJ~ND=YxvyYUx7N67!K2C%%z6Wg-Bi)Zv2U)%y9b!xXTTh
z6c~SL`1A@sy)_&b;LJNiKE3YW8``{pu+os*5|Ao`zA?zE4Zl-__=Djj?R2U!+^5m{
zN5dHUu+{O&U?UAz;|JPk>}KplYZR-Efmczu##sCqiffJ6Xzbx`>_OAh4aUX^P}pef
zJqO7qV{3Y1HXCQNQ1CDwqOpUgab6jOTa0t3BH3!ZKyTgc#@VCbjJMH5ad98x`Uj}X
z4u|o3TD$T!{_zTlpK)><kop^aTLKec?7STYcN+hm1kylb0@)2R_Af!Q%h-xy_Ir&#
zh@jbL+($d;f{oeqInjQjIvc_R#=+4L9yIQ;;~In*yHmLEkTHiM6o-x5LSQe{=;%&O
z8fJV-yQRa8{cF(9M~#bf0gW^cppRUmjMh<r95aS2hQ@K@-Zns<F#aZ@WlkEWUPp4u
z_}e)6d)oNm0FY;lQQZKEHnxg|+cC!F8&DQ&Y-m7o*7%?p)N#fhqu|qd;};HEWJ@qU
zPe21-F#4{C`xlK9<|22=*iHxYiN+60VK>P*bP%|cjf105cG>u=7RYPHDq5(#ZXE3c
z?i<ELnoFh_e=LFUrtya;2vd!76QPi1^dFD5xMkcj9(HdV<7w)B$Ji)?20Q7-%qmDT
zjI$2I#C_waDbUC?mOlXIf$<D2MrIkuc7T4iQThuea*P4Ao|bEzNS`|A8C#f9(R^bP
z&0!xJ?N-=*WE`nMuE5xE1z3uV{&gUHV!U|`dd0@nWGFl}mbRpc@iXHansGfhwii&*
z65}@7u2O3JG6K05#!)R%(K6$g407eh<x@fW()a<t2F6tw8x_LsSH?DT!Ts8Jj>b{%
zjPK~f$@j+gG-0bWE~D)=RmR{mP_H&_mmvIL?0*fp8Y5em#q;;kSTPJHJ{jjlz>C$U
zQu^hGHKs+>Gp#kbwLsZAQ)`;(tv6NpL+Ea*Pow<}rVnK(+h|JfhGdh;uRh8)o5oQn
z)Wh`sJqSHb(*)$UnF49|h?i+eB)s2l%FBiq-X@v$ZaRESQ%1t>4paE|(C{^Nrf=8$
zOqtQZ_?v<fp&wu>`4i@Mnr6~SD9~ih24uJC<R?^Zk13p%-u9YiGq{rbOxI|MGT7w#
z9J&3bSekzwFl}pv<e;f1JtHBe{<L%8kSUZF8xA{6EnlI%LQP$cz~B*61KNKWVLDj=
z;ZYMuFN;W11M0S-ObB)2IWWcTfr;a$cRzsbglXMs_;k`F(bmW_CM#|Hi#Bbe=uM1i
zD}Doui!}|J3(m8q<eL!2nQCW)EZ$_I#iMg3$2uBuo;Q6>+iVg{!f!|}n0}IhxoA4%
zoL`$tDYBVtx|xRLvgs{N->#URwS&Q{rixWau9@0zMcH*z5iRH4FbNIeT8e1}t*+fP
zc{PFgR8yl~5T=>N3qam6b-9FGx@oB61X?!3^!2xZ-ZdFoAa~DnyDhx9Z(8y>pqVBs
zg<l?+&U*rqWjaJdf^5_7F=)gbQ`lC}<eCoB2LFeqV+J_$$Yh{pxdPJ#ns61G2JC>|
zW7BQgtX*U>SfKF4v>shQS8U4nb%6V+=|&BtC8kaj&?cp(5j10aVVXswv@%ntj)0V#
zdeYY`FHNn!22F)&hzYIs$~4mt3a?EAX-fLWw5u-4-kMI*M!I(<H>zQkX)MLYt4-79
zqGdjq{-RG;YD}3cQTEX^eKb9PpG@z{!R=~ZL?cc&bI%GGTy6f5F6<g}-?6CET5|^N
zWm#vA-2>!C^MUW7zsY=`0vDUjpV3U*!~8J|c0J8)mqC4tIob?}m-!S;`L~-tqd>5?
zxuP8)KIWP?@M4EK1s$7%^EF?LfYi@Cp)c6{&0oz0G{BtL4*EOIou<KVp!ow$Yl6(@
z>B-q;elZmWcbmCsaBYwI6h$NVnkUfCy?y48$H)bnN7A@;zgbH&yaVRf_mDei4x-md
zh`CW8AP<>GUP9tHZ0<G*6%94lq(Cvu+?Kvm3pf8s0rw;3RkXelVXjMK%%kR8G+T}|
z&!R2DQRa%_aP64+65{9FadS6%VV*GOlTRnj7wFrdQ|3~-OsCBj>R`^8=M|z#(dO6f
zQ5IwVArO^_b(sJ1K()`By?#d$XExECDc&s6T<e^<aci)hH~&RD1{2I>6n(v5R;I(!
zMe~NifLt=4I1cVabB|zDBFQ|<3}LdlVm!Dno3m+W))n(*`ZVRLc}xSSUo)Ry1%>No
zpX(^QVRqchf{Q8UU58NLo918WIY>1haEFOB^Mp`n+%nI0hN8^h&?M=OdHr`NOE=3O
zkz|+`<iXNi^AEeAch4-<gYdpNZ#VQZ&7<RydtmNx9F3o4E~eG(Z1Y_D+CRtaL$B>z
zbGn0Q^30*Z$mW|L&^Yp;dGJ@jJTm7!f?|Q0839P4dGSk-J~lU{*Kd(|IVn6bTWPb%
zGxHDAfP8K~LSK%Qm^(g&Po?HB79e?H-bnpLnYm~Pl5%rRJS@C44;7$SVb1SH@4r{(
zgj!&GZT8y(6K~ATu-k=uYwll#+&i<Dwg|sB$I^b*N^|ocpjc&I;SaWI^TUxa_`!UR
zegdV&JaQGdKbl8rVfT~yv)8Dvt0mHaYv*QZPhtDjmK@sdyvEYUh_bboW$WmB*>#q~
zG#*@U`9?&cyCvKi^|j<b1kFavt5T3|vTS(-{mqumgW!dSWk3fYJuN@bc8M*P?X&}B
ztEJg{Ah%h5rB?T{?CA+dw_B3`MB;5p?*^fd#h->LJ1mYXQ1`XW1*e1avy7td-QSYw
z4if>Enn-Buv^1lg;DMHOdPxOY8c+|j%d%@V6n9&$v;fT>i}53py_T=3quFQK+7$}H
zmKk$_+;7RJIN$-xT^eN_wD8N&%psQH2a!8uSv?B5!xl?ps5?R}t@<MkvmCww{cuYl
zJ*r16y=gHm!txs}Gaj{gYy?}RB}xtMD9h*6z{f1tC&1C;mK<6?Jz=@`JKEx;r9Q2m
zowE3}MsnIR`7YGYSZXLd5N&zi5V;sj*I=l}T1*vCKkKkGxB~7t%T7IL;w^==b@iNO
zoCaQ;x0K{TF~PF&3N$WRa-KjV(K3K`)g@Wx(U3mba+~%yUABz-5(-x=Dteb+wPev=
zlWUelBdD)iT-;#yhNTV#QBy43I#{@AIYO)KsTRjl{J<iYW)bqCf6LM=7u>fk+h{I*
z$5L_<`stP+y1g<i>!v~DuBCrd<nCGio&?B!OVgf!WLhTB0O5h9NDcKYOZ_Z(k!|_;
zTjX*qgHz#luBA;G{LQnp9En`MrQk2vduZA27=!F1%WM(c1(wV8z*cC9dkLQ&TPFMf
zOGTFD)CE7W;O9y4%CaO*MAe>J{Ai=`Gs~<I(0guK`3cApOBwBED7DPqjob@Mm$yKc
zSstE(7v+|4T6KPD(bPgCR9HH8g@sp^n}5>t_uBFkEor~8ObtWw))IFT-0v(iXtUsZ
zOBoFSD=j_fy<25*YXeBNWdIH7KUf}x!uuM_(r*CyXsM*z>yss)1E;HXKqeA5>s$H^
zWwq7&A{5qGOK9uXTI>5*=&iGMSxQ?Z)?4Rz0po5RK{K}vRzDhHZ?s1C0O=-cNk7nR
zw(iS@c@OLOE}-$W&Z1cP7Ha@?x?8R7h9lW#jiPa&m$mdP$hKR591DoI^%vTl=3|Xi
zgJp*`YXKm>)_mF#>Sxtqxb5Kltxp#L8epBW1#KB*?SBt0?y_dnuS4v%_BEkwkF{b4
za(k^E=<C~k*8Y(Y23t?O0{4FF%(dV?U|mW-CUnp$TfiM+JvbU(9J2PK2*hD)d)fsN
zYAvO;fiSC`1_<HS09t|>c*M%kOf$loL4l^D)(MHoMOqs_1t!X>rrIB~_MvJYw;rX<
zHYcq2DU^HCYNnCyDXW+Fv|sBw0y{z$YYnHk|5<CNG*l(dI#!P)-fFQRIcIG}9ol*8
zoERVztd-M|T(DkKA-QNxrP=)@t6>xDBwA}%1DRyKMLkinHHa3xE?YO(1M-Ts_hDR!
ztJc>w$X&CJrx(U`>p{nEIDf-B;0u^fv96+})|=K}e+Esewf20_q*=!vLvqXd8wFEt
zTXnRyb;tTF6UcOHU`tdw!|F~S*WR`6zKODX)``W)-M4n7c}%AD0!_;wSSx42nJnw8
zw-9DqO*E^?u}(irJAHDk+5_+{&-xt=;q$F4Twwm8_4zZDJ+gMVilo50BovMoTI*5J
z>9Mur6d;SNCKu>Ev97rc*NUy>86bUXb=eFP&#cpFAoAS$tP02yYd2b!FSYLK422ig
z1}}juv+kOUpFQEqt(7#9e`y^<E7KL$`AgyHTkEP((0FH!9s>RM*3-1QUukWA5oJ}@
zv<e`rt)V-?_Q9Ih8wP8v{<MVt(fTcIsQzS~(jAVv+P=+3UEFN_e@AY$?fw=(*4WPZ
zBDdCd3NyUf+&Wuz3G~<7(!IduZu72yGaGE<MxojpZOv$>#3tLu8*q5D?ba2PdDvbL
zfq75cHTsdBEw;%;$ZfU7Yy;^w+Z%Gm%l5oGyx(q{O|Kts+Z6Atxpf^|X-V4O*6TY^
z2G|_m!LyyV-zLGOK-)YTLk8Ir>9*fx`<bE$yKO(71!Rw{Yd&hU*Vfz%W&3Q&p|BHd
z8|n{N_S*!Cmmje4)EOVNh0;Ej5L?F#AP?C-qp;Fp+jtrzhuVH|)PvnH+g^H$gxlhx
zfH`8jIT<t&wv{x{J8H|PAB>8$)vJcVDBJ8#NRHV~Y=$$(ZJsjhp0G8Y0O3j7dHR{D
zQ?`{9bUAJ7OQVA`w%?OM7Ht!{0up2U)De2IwvRu;r?a-_ZZu<vvqkrWM!fCMMbJNI
zTS%DmwqX~ckzni69<E)mg{(l?MO*nvC|t75^g%As)}$V2l5CsljhJjpq`keDZS#Ks
z<ce*0I5@A`nunvYui3^1!;9;-U)n?OhOP5{D5Ti_>`Y5(H*JGxqLgYYoP?%Hvq>~~
zyk$H6C4{$attbR^$Mz$>65!HpS5E_yVVfzU?7pqbPFTvcRZ?*Ifvwm8f3s|bxhTuF
zecTB1IW}nqgt@i@G*!s6{Yv*wzU}QI=smPmU~id&du02YKEEiig+GIfg|>LwGxgZk
zxeqKA*$xeY;uD*m?y+K9cpkW)+DZqa?3vBg2JYv!w5@=Y*zTQ%Ua3u(2C^462Td=_
zY%})5`*Pc$V^DZ$TSbd?6}HVZSAJzH;z8zkZQD2wG;eHeXg&X}&HpU)-`RdY3>V+q
z>e8o5m9}?Nz*c2T*@j%Tt-dd6@xgYMR_SYOzB{4!(N^*|^gh{KXjb5Amm47GW}iVD
zt5@5#f5PAz`>MJyxYl0r31#c-i<4k>y~BRq088%nU#J!v>`PyuEjQZ7DWKV8UqLH3
zo9*2W!hH|>b(%+e+M|{Mxy2rt4ZB<I>(&9X%|48_j(FJ<u7hm5{UE&>yzQ%&1L9*3
zqR_$)`xm<)^tDR`p!T!xO@MiSyF(v_Y=C_PO<{N1mp=g}(0-JDYct5cxGOB}vNxjs
zbhmx}R#@6&|KkI4d+pQDLVurq8SVHDwtF}ub@n6`EFG|GD9Cis9`_zei2b{cuyDwJ
zf=49|+h6R5Poef$`WdA#dk@EFz=Ydv-ynO$zOf}R5%y48**a=(uLfJBJ$(i=qU;qk
zV?SmOOa|n*y*qw?ojYOI9fk0uy}TJ*J7w>>77C~Bn?3+?#-2#Q<yiZipOBoja};5Z
zvw!{&W%2gQ6t6#LA7r&6J#Vk1Hc7A>Y0Q1WUhM6*sIH@7Zy=NH(<sVw*`9e1h%5H$
za`<`GKCKaQ*X$46(FWJ;-V`vqVedN?xfFZeI5>aPUO?MYQteYHYM*9rl>o9^_6@60
zcH4f1q9u3ilj^}-y8XLVa4^F@?HeR_?Z*4iyJz3ycn-Gv_Im@sooO!%hQ<T?dzwRK
z*<~-3W!rx~2iJ1!uL5Br*IuUu6!Yv=^m$9ZJ@H30%tQO`xzKxL5BM2&3+$gnC=}X@
zoj-tJ@8Jqakv*8^>rd?SX(Cu`xBLW!r*_}Pw8sC;K8$99&+XL|cPp_kG$JXre>??^
z7j`{`e9P>A)0T>Id&UQN@zUPE1PT@Qj|j$buk6!lUiaD_lLgW@_9*Hn-r57&p%U-x
z-_zLsy?sL$_*7|6PJ_KF`;zCdP;GB|pF;T`?DpE=uCf1B2%3-fAA*4SWN&f|=3QMf
zC{W<$(r+|qR=bRT5A$nW2G&Pzt;-|}%GSATp&`S1mk!@U!QJI9?GoAGvM>kcH@euS
zBe%&V=M?<i>~fR#Y<sxmP;cewGWvH4Wo&U7M01&~E(uxC*yf@t1h<#V0ot{?-6bU%
zW!^4D`=H_DQbX_F9WKM3K<Ml8Z6$JkF3;P*gulzO!B7uy38nAJf?O^iL?w2)thOPy
z+ePXEg*`4uD&Xi|mz(rV?sI8&0_sw*i=H+^?03PB4ll7fz6pcgAs0P<q?<eJa(fNh
zH`HYr4d26D4%na&?oyk6bn=MH3R;wjaH;nPlA|uUw3Zv`Vn~B8Q7--KfaRFWw)v>a
zaTj0eKu@?d350_uT{dh*a>}I@eNc7U<pBlV&$w6w7>ah8>{x}u7?-y+{)lxMOY`Ql
zE;(Ppe4LBFH!$%ohNj>?=aQ{P?z~GhechDc(rGS`7hJx?{$cK-%Zvzkamgjb6?%#P
zA4k_6mu2<E%QDl3nilWgdoP=o<|r#0j)rNLX=%%rnU%j@KtP5dOHf1+L_h^Zrm{t3
z4*`+A_Xb6ljNkY4*ZG`#&-a{jFYj}od(S!d!R9YotZv!dryzEY&9`e{H`iuu68iFN
zPS8Eud>iW_h!ohQW?BI(v<as=m?E3dD`+jYS$hF4me{=L2HmALbri+AZSxjoZ_8}v
z)8{J6ZDL$7T@^MmIZWKKc{B)pl{WY80C3kvP3uyXO?&`Es%>^<!(fd~$|8_jo1zEs
zqRyt4>iX(!mX*@UzQHCi5%@-%bC+Sh$;SH~aLqP5CgD?yO&aAfT5Z%+o!DmcBh>}A
z+svZ{sl(=*QuKA&JVjT!x@>NjqOaTL*-bFfWAn;#nCP_`eE?ja%^(FZ`)!uc5p}>O
zpKAC9ZB|CndveI;T{p19Ht$jTX2fP&8AR{dbgqKK_ig^5&H1QJ^dr#yz$TwAqmS9h
z7r?~0&9aT~aKdKIPV`OM^iqkyl+F290C;G#kuELH+RXbF+?>q~S|n{5vs_rPV_doh
zxIJSr)uvgGFv{mc#({DBF?2dI+UbYk#JE9G{-X@Vel$8WUZI?j3**>+AY2*wMG$dg
z7#_mlF@~TAy4@M|Y>0R;9-}bQamFA8?>rep`yk@QsQd&Lycw-)Fc&@yRubIyWmwOF
zJ7Hy%y$6IJBji~O+n>?59R^P_4$!{f6eFk(zyQWSLJa#f<5gN$0~s$p2c>5iF;_s&
zG9(nx4`N)Ti=*clM>YT#%;?UCmJr4nDkC`0_}^Jr3T4>*0dj$HLkW>E#{MY4!x`3M
zoE+vyFxo!^{vxA_1H>hUiGH4!8TC{M63Mtu&t??k?^2LxMiYgvt}yOB1D|3Tzfyhc
zRmL-ifs18)N`<0v3_n-QQ#`|!uAL_^LaC%8k&(Fy-X}54^!B>O_~c(GyUzI2Iv;E@
z<M(&KrZ5^QaGS~q{s<(Eae%I4r!(%*X&{5qNb$W)#y78n++a-53o?sQRtXPpGTuE1
z6WNRp#OS-l_|gL-%wgnSh51~@7RqSlF%nJClFvwLfV~2S*$0h<jE2rPV5x}V9|~>7
zjCHgumoP$Tk5tN7p9Y!RjKlum${2l%&{xjrc^sB17~dU6-yH_ar}vQ3`gb5C>KH!N
zP+iYRy9B`o#>_U@Yi0z~Cy-hgJ$k@e89VIJ*T%@AkW@Qkq6@eVMgaxQIvLrtFm*BP
zsA#X7af9B7Jq+iCn1Wu$R42GT#^^V2v!CI05ZnOcDIbh)kRe*U68IrTaVK;SGg7zv
z1pl?n8b{%UQO33#n2HCCqx3@<V?2=nGS2XL0p=$dcPW!Q$=K2jGR1h7LP`%A3pwbU
zX1JXMnPGhH4imEs+hB;yG5CwX*)kKT2*-|@OCeHw=J}^!_6ReP1MeM}HS^$$Ba>r&
z2yITxLAqOcl(`}ht<KD-pP<x*DW`<JD>Ls0Al#Tew3j=^l+n}c&RlAQB@gB$syRB&
z{BAK!crxGl3&e{l{slO1=6Xv1`7rM-f-+xbDAkIbU^2f1=f`yY5L*117rSX$J;~f9
zhPG48!oPtCV7}Y~rKg$SZ-Z-r%mx2I<P39yjy7kRRmspD#MEg3ILGXI1SFUlbP#<Z
z%!=P({ycMQH%x>wAE$`r1?DBnp@uQX>@gSNO!s0ai(r=1ATBcBJVXUEmzW<?)!b!f
z)d7e`GC%(bN~4(T-Uo?hKBS_hD@?^sxF5r0L_z6Q=F9ug7|Z<mA(X~3qrZc{@k}ot
z%wYm^iVmKMOjQNoNzA7j(07eFQVH%lb7c?ul9{zdASukO2UIGb%KZKi?4~h4y8)%?
z%;bBpl)-e-!lx|ePki8SG7W|BJDV9sSBP#gKPZPt4ztt?&g3#3DFdCyTu%>iK69%9
zUKB9jEQ4er^MWfpEMf`=FqOs3Y6>ToFvnT|C}n=bgQWE~lTUZD%9uYW;8Z!Yrwn#0
znBOk}xx@6PQ-38>cnluiWu_m8NELHiK6F<z&%6&@4bzLx>9x#ix?)(zJon$ukSV8!
zzkz9_?MNf@Fde0un4cv>vYELx3CdcSlazO8wK92I(AvhFq0+Q=W+?5$JD53iH0oq(
zDC6G6EZGdw%`Bq2rXJ><8u;DIoS|TBA5%bw<9=o-2V{V0$%Dusb3J8=hnR2EJ*Z*k
zi?={Vm|t&$p?l2XSvYf_`R#4!9A#S5u_vAXfVqTf9mkk|yot_nW=jR|6HGnfCz<Iq
zrBlqEl=pbZ{92B`$Tah~8KanC*1ZC5mZ_y1GIPvNH>1&(HSPn>j%A{HDtlJ)UQG89
z)@nK&JFuRhU8f^U_CAOci)qEhj`>GfKT<l}nbkfB_gz?Ax-jF)vY|Q!H`anoaK~7O
zzeArp>n)1jdaz`b&~}`aM6Ur)R{knD>cwhb2hN+-zXu{dtS6no`LZIZ2IvIq2TGv%
zv7FN|3H~hO>mVmtPdd}d_Y|v}UK|0ekktU5W;y)|E|8_5J@*;bu3cz6%gWJXN`hF=
zQgPQgRt+uu!7Mup&V;hMXaT;!Dj`4^iysayob^v2+>T(4P>%c}OD=&kmssxf(!b2|
z%R*lyE1OGKRiao+X*U<mn(~B;S6FfOkcnXlcEPo)taM7Q$Fkma1{cSAg0dj-EDw5(
zB(U!FLQNv;?tU~Tv1ase<{ImA8_0E*Hzh%mS=t6DOJS8!DPAh8fMSMetacV~>8zC>
zP{1^URiK88nXIifn3Ef<1ylx|#d`W1Aa1f=d>m@BS!o^^(=FC6iYDc-meXlImzDYn
z`tn%1VsQB^`*YA;z>1?!BNVcR{)Vz5R=WYDn6-v-)g>(dXaGuCV+N?c&FVUcK5H4P
z<N-R%S!*e=RKYsJfr&e;2NdhCWW7d@;a%448UU+Uw>n{>nzb(oz#3Kt1zKxa1FJ#m
zSV?pasAqlI1k%9rrcG!g>s`t#HL<o)EVh~DOF4oT)(G8sYGu`p!)%+CwTjBn+F8G!
zfu#<XaU1M*vL^aKx>z}svFm1KQs%mcb(Bh=dRba6rn`?dd=4i1S$LV@!DB6vgBxTu
z+=9pui}fnFVb%f~#0ab24nEyu`P#zJeb!DUoEc?}>Omf`tZ|fL9Ao_*2&LmJNdpiQ
zEQgQ5O|ru19{CjOcW?OpkhPy81k<c#ZV;Ja)lx=wmX%-!^K-1pBOtcy#a95ZW1r53
zL3{R05=<OnH+>DCoY;%~fji1((CNvU?dJ)A3wwi=Did7U75_q;8@u~2SUSeuwi-Zp
zb{YjqJ=oV~L5{P(eG?*{>{UzQuNS+PPK4g<emW%ku<vdH=gW@w1?~jfgT8;|$L{(Q
zmi*bJ_d!mw2R#5k#XdpLZ2)_f8P1$$zqi#2gMn<7Eo9EHFJ*z8Wgm=yi6Hix>p+}i
zuU-vAF#GXGVIqV*^CbZ1*^4Mj6UyE}HAolO)3k<#v9oFQ2xo`g03d?>7;UUCvbk5_
z%q2GWGl*PfXHacRB)k77xE;mT2GaX4n%!{(z$@%`=*%3$-gpa^uCfDZ7aGep)0sJr
zEp~)6@$7Co_9d{NKL$04Yzsvelh|E{;Py4P_6>+!XGhVGG?`u52c0SGAPQQhviDD-
zF^#>s8_LqzSLqLv!L~!b!#Y2c{l96jH`tD!z-|_MC<Ejs+nrKo+3ds&{GD#GZ$1HS
zIqYq8Qz4iA-cL}I$F9u;E}yM?10n_N=lL*E$d08)yoeq8C$to^OX<Et341RkEK1p3
z$1pRu*^9*B%GhonLd06m?l=IY6>J@4-tMq_>AMq^?89F{&0Thc9b~H5i{C(BHG3I_
z@N3wPbY`w)Z>1wk9XnbDuAW`|5V!`mMvw6}vj3r5r%mjyY3tw27FU65VQ*XjkyiFD
zdPdsVyWWGcb}Kt~0%|(grXm2l+4>!5?O|_p2I*zHjia%T?c5DD{p@VIB|gA*rJI_A
z>@5`I8e*3(gvc;^b~`3$gdMpL+&%UiNdVkutEwO}%HH!iJbb`@`X0=Wv7e{v#BsKW
zerpqK>xXAxev<7-AFP;S2T>5_A-iQWWTx4jF9Scret|aov+SQ4nCCh6Sr=%t<z)7Q
z*m3q(!zX*r7akbX5sudexaPq5U@>$%a=v&3eNLPKs_Ht*vCw1a%(++!;=&Pq0DG>S
z@2s1k+l}Mr3crtW3fBYS&T*{<!h_@YGPvWM9kgtDa`1gwJb0X-PPpdH$<08c4@X!F
zZN8i>0yuMm(|H<wew@p6c=hK5)6V=P=R;bxPH|f3EgHaaq*&Ey&h$}?C6H6|`5Ul%
zhLiLabf4wq(rxG<&TDkgJI6sv2M-=+-8_hdaFkU1aGnzo2@=YQQls$#=Yr36N4E9t
zT-dwB@velS%baj}Uq*6v)4hQx&X4pIMst3t0e6M-Hl3AYIDxrPa+Q-ti$^Tyc{(e{
zai$-F#B)|soFswMb_VVya^^8Gq9o3Sa!6j|bZr6dI>)94T9P??XoH%<$*@vLC6zO^
z6u>mj;T1rnb5z@b$lwgUjlN9I$SQbogX8ub8nZaQTKIdD)36hb*_=11l;;*_J-rTc
zINr1=%;mgE=a>S{@n$p@auWZB&LYkXy-kWaLOB2>91jP;OF2muw1v3M*+vB?WgPu#
zh?aBe`~j@sG|}C(JDm7_cu~puf*#bn9NUvHQN`IzPj5A69hK_Wa0Y4nSj)-GLSG#x
zHw=J!&PF<(HgLAl&%cplzXKMUIJYR=-OQ<@?QRQaOhA#5R!-9_w6$?gQ{JYXQ%BqU
z4$e>SV!WN4Aj;TvaSqV1yE(43Z|vdR+z8itIqy;hVIRlsSpfPuu>v#>aM~$KI>_0%
z4t+zMmuMjz=Dc+aT1Gg#9tXL{iH(4k`<zFy8MMwH<?xro`~%MTZ!j^&*-ZuB<D3f0
z1Wa&_E`_#9&hie3OmUv1t@K0AYjaRD%}J(T)eOgx(*3iXb@d=~ocx#3Xv_6*2EdN{
z#YF(@xg%5X@CbJ;#f=@ffBRx&j@(tb5V1OOKMMfjDEH7xh&ppiD0Jn*b^8p&mFtv(
zMmH{h33MOh+B$)A=lW>S=fVAzfyU$9z4T}D<jN?!;Kg0%2&LZK6gv<fuFY=P_2o|M
zF!?9AmqTIRkL#QRxIdTK4DO_ryKn&BoZ>z^g82&IzD3)U)7)A5=wBeWdIsDX?webI
zILlp4Pk#{iY5G*kIqs%80D`$sJq}AD+(%<z{ycXe9v+5r?>&VHy1@N041HnTALu%J
zIJZIq62bMNh}T7K9uIwyT<aI%FdxP3pnOp@cOOMvu5b@gKs1K?#uMnf%AG2PXe@UR
zRqe!a4~+pI&;5QLTub0?^8qfA`(hUclf-?n1tQnDK{T}M+zV7dk<1PM0U{~fG9`wT
z%6;Pibf$6N;6qC~_j&6P$YgNUKLD7?O`*-o4Q^{QbZ2p|QiaS-?jOg&WpiB{(RYiR
zvjbcX*O{{5xm?3CIGV@JrkgMM+=L-mD&P*#UEe}(D@ALHxGbt*DCT~g4MQbdr&8!F
z<v!O2+->gON38&sao^d5`6}n`YD8-V_si$t%pLCEERafWN*;iBxxdl-ql&Ag`haTg
zGH>8&xCsL=Sj%;!AVD41Z7sNZ?w2p4uYtRT>X90`1w$ZB+=lHS&0HBR=PlgI6aZSe
zEzeWULmSure?YWz^KZa>2lt)#;czEc6pc}Iad}Sx*v(x}Tf83bZxl4`<!(uZr9LjV
z5t9AfM?C=_;EvA0!$IzRGq@q{%gqoO=Dz(BxDjp@Mcwalx4r|weJ-O7BOB#Dy_=5E
z54agJ=pN%rDTO@F{ejld32x;<n4jb#hl>Y~+fSv&54pQ3csb2Yq;uB{_ZhluHOu9Y
z+jCr7%0$@m>ZzjDj#o%KQ+wWmgYfAH@2j&Aap1A&K<&uul;RKL#QTeueCttO)5oCB
zyp6P6y6|2rfC*P#(Iw#BcyH2+z=OA~7o#}Ndzy;wJbC35`SRkOGXv+%`-L`1KD@gW
z`SRtJxdU*5cY`Ya{diZtgBE{Y5}mD1^1j%M0iNQmprcLzZ%-KdPFr~~R5~BXo9Tdy
zXL$SOAaj-%yboLu@0$qtbdJZM-&`<n!!7_rc*!4vJI@PB1}>B*dmn%cynYHfhw)Y|
zf-~W~<Sz6@@KPz_e34hT8Okp4G*uv%c}e@>b|i1B2ed@-tn3l^7R~G7z~L*rV^lB}
z!+V4(dam*UZa`@)uV+4##_>`jfsf~{_lE8S-YQzP5_#oYVLpks=M^Zu#w(+r^>tnz
z6{aThUZUq9h4&jZrt)}aVIhq-j}pu2yuUZYPzEp7r|Z}=)~cnD&*D|n?dzMoOH@pi
z&HI|RX192YDQ=L%^G(O}=JJ%kKvy0w%?(^W@2oQ%E8wYVKTyaM8~`ceaa8cHnD_Pz
z;7WKx%8QlqHn#$In-@S_8PDk~;N`q(x<XXJv$Ikt<__=BQpi;Dp5F-IUEU5_t*Uta
zR8mmQvp$Kw8s4oz46~Leq5G|MJZ?O+)$>+Uy+8x+<#32J^6Du!-^APWAx7KG+cph&
z3s0njqpdu-7hG%O*){>*&SSg<3mv?l;;fMA<lR{b-CevT?wHVSUK1JY;r;szWO{iv
zbk(Gfx9n>)_VaA$<vqY#(FnJPdFv?OGs4UG@72chz7P0)o{4UBkMdSieB}YJGaT?S
z-XxWYjq^@&Au_>ROCiunp6JYz20UTB^|W_=$Wwm;gVVgCK9CvSmw&*-EU)+{kU8GB
zZ$reEpSaB@*khTsqY8Kj{u&DNJMuH;L&S;SPE|8U`Mc?Hb>^R-xUmcW1^T<X@?SP!
zfNuO%T##e@=gL6b`H^Gj^WaZWocuUHnI_1S?@BQ>FaCAfNqX}|Tp04<FJ1>_zWhl$
z08a3St+b-}@j3Od<j+4z3D%SRN+UW?@z(@ngaQ04szpA{ccq|BApbHA;tb!N4|10O
z6K#@%_={+%J;!fc3oe-7@;3TH_>a+$&hw3QL=WXxodUVQ|B+tkVf?XD{O!W|?t@k!
zBKR-Rm@e|arFwx&eAZWR@iPAlI>kit4fL_6DE_Y$Y>no}YteUwKR}6q7`~d`<X8Ds
zR8bSlSJ#5X@l$_;NId@$dKwb=%h|A-$bbAi;7R<K<6-C;-{m8Cah>m_r;i>d^G7Ll
zkisvf3V~F<nKJxo{LKQ$r1Se$qc4NswH1At{Ew>9cY~k*4J>8xc{v!xO}^7U3^bcx
zcmcX^@gEO{NDlwIwdl*`=Y9f`#}EAijrsiOIVdaOuYDJ)3;CbdK7xh2i2p=1*kXR%
zA23nEH@^fmrTqM@Amx0H6@FLncRT}wcld95Voa5M&kIm`m(Qm|Y8Bs`YU8W<c4A1@
z@YN!aT0VmgUv>N&KSHFQZzzG?2L91L7;5ByL4njJegMVttj+xERQ24#_t8OjEB~ec
zt|jsd>9$@we--6-JNWB&L!^`c_%#5#_(}Al>gKy}pu30v6K#ij`7S}2=RSV91N!>;
zGTPA&@DFvsnL+-dAgCVVCp!Qz%y;}2UX1YjZb9Upl^?wWo%i`G7D3G@-<w`r5BLLJ
zFh9mOe-3Tqd{4T|Ho<>A4BR9?lzuZ){EHtz_e1^+#YLz2n~VU=@ZYC=&n&<F5m=hz
zxBm!bwt_7bm9i7Oo&;hqczY+59T7aFRHK8y8u>R^M*(*ayl@gcM+b<b0)IU^odq3#
z!9^Fr^i?Qz6+}@jn44hpP4pcT)MtQm7Zi&C@DMmsNzQS>K{`Ks3S3-3yadnfMW46e
zwNe0l1hF^3`3hu*;o1qov6XPfPta>^1@#x~p=bM~;Od*`JSF)181MmtT-p_#7F5%J
z5(pH8e**4|Kzj_9&I*dYf@F}uOb6g|0#O&ZV8QxCC<_r-D7buHP-=p~P=T}wA{PWt
zQ`93&FioW~;ez!4;v<3)1O2=%3S#KP4wnSIQP6!^!0CpiNWrfZeUB2f&=VUi7^On0
zD}u!o)Q%CnOGnSE0*85!j2E<I0G=Sor>d?*!2_!9ND^$MHTRle;rHmfE(oC~E?Hou
zm|BX!)(?HD0>711VUQ+RIs`Ud@G2E;WC#u=Lusbq!37|02;3-Un<Ws%VlX!adnhTI
zE!aSZ`dfnIR0WwM*h?qMTtNv1M)CylY;gI4Czk?OAkd}2-$KEA|3Y<<;2Sy)7Yjby
z1zd?>0yQ7j`K5v!IoR8R5ISd;2^#4PS}qXL<(~?{`&9LONAMFxVk!mPmtp>{fOi3a
zD#7eQ{2r?Xt2@wFBlwiwhP8qZ=~_me;2(OL>IHw&7xo$iV%jt}3IaD^oK1o&XQ8uM
zu#Q3!))v7b4>;T^SU|O^ZGy#o%vZa>Xo0p4f#h8PI|cd*h;#`K{R!ROg82g2?Gc2I
zL$X(}nF2|D0?)<h>la+7p!R^^#0DrE6co&X3<;i~r*T;D3q9x~f<Gpq^Pb>7#a`}P
z1^b+#dsMJO3E%_4VM2@v-01@HxWGRemL>$Ubm*QGY@mv<DS_j8kcR>%s)d^td_s4C
zW(1E?Okq~AZ6(G#Coq>oi>=V^1a#U7AH54@_QGOHiyRTQu^{One2wCwjza6aR8S{j
z#`74=QQ^QaI-P~j(&5HMcySsIy9&iF;M|0ty@bAFLWcz~=q^055!yV2?sVcfE_~@W
z8a;)>ArSEr=F$<=Teyc_tv<ppzk^SH!cJ#!{=yx!_MQ}8q?(#jLT}Dpm<SLqd>YzL
z3r+FB2MT|tP3Rfni#~7qEw^UhhlOC_r_TT$B0SLx_<7+ow4{UzAJQ57g3yB!AYsDC
zKE_bOh3`<<Ekd}RKGb(nm_sMQOTw)q&~jP$`Bxy3!nto@Jxch}UTBFHCPZTFSA-X7
z;}j#zqn+qgVKpt5vBKA_Sr~kruy+%H@j~xqa5q7i=>VmP!mX5ZP7=O+1&!B)&p!+9
zx^RZRJ(4VpnSq)V;Vh-BQ-%8}@{=aKO;2ySu#_4zgjv4>mnke7fU+CH>@kom;g;9X
zcT<>P1J|;JGvgE-x+N^8ze|pA<sNXk!k*tClP7#H4wmwTN{Z_g2#@c9!9rmn1+$8T
zfjDu@FBazec=<24=I#QzO!&s@=qeYk_#IPNA@p4hm+lCwDdt`&JhT*jcZER|%&iiZ
zIHIpwnEfTp)d*K!gPmGo2m>nXgpMd!oL?{G(b>2`7)PsHqwp5R6PtvKDdyKKe2hLT
z+#>9!oouUct+fqG+k|gYoqN0Rt!W@Sgx?rpuv3^!3FR)~pF?Qu7AE}z(j&B^lT@$J
zVh`8)gkfJocfYV;FPs?=CKsY_Q26u*fDZ|8Qp{sm_$gJEjR+<5ySpc>b%d7t!odeH
zKPn9Qi85Iagj@7rCxp9bBQYuLs|A@7rtr}CP`D`?u1yQSKLIi$e8v?%%?f)c_BJPs
zp@05kD|(ZngLa|?v<I~p#h-?WBcc<uoH~fQu7h(Fjb4IlPNHP0@i;1aKv`{Pk!+F<
zr!Jz;C|2nza;BV{o9KBZ)EpD#uLIs)#JT{4hv*)?<&TTrq-uLlQAIDj@Dly$5AVH2
ztb7dANA$!>^!bWb(A)BaNWcT<C%Qu00)NrH8_;=D^kX6VPKi9|)gK`G1OaX9{L`Xa
zzd<HY6dsMvGolVENIEO(rXrjmkr!2QofDN)5m~Tk4W)@gL~EV_cV6U1znM_cmJ{GE
zh+d&(DNH1zAV9e2IjU!h5N)6b^rDEL1CdK2|8j7bMQ_qV6e$|cL!&iHw2EHg(V|@1
zmR}JarJX>G=nq;XuZq5Z0n-*Mnu><fIMFpqLB)$Mx5D29(Od}{6Gew?;Zu^xLSM+Z
zCR*4I-Pc7ml;TJheewtTQbapG11?pxmo7c0i3}@1(nXRf05YtiMH<Xrrf6O&4BilJ
ze-FB|M2BnO(@oKVC!r==^!+9b=9Z|5N_lcb`72>JSF|$+O7ldE=@gVN5>TCTfyfdE
zrG=tlC%9cCdMXpDi$!Nsp|eEfod>Q|bc0fpw?(`RC@T|LpW6d%<)YDd0jv;JeFfj{
zh;GnMt5Wn@3uNw!3aKWcN;GZ@pK3+l)BCwjbm|Z!>qWJ6er*s<j-anm^oj{yG>JOe
zz%`3pX)G<G&vwFKtEi5up4&v<UWOO#q931!NQdZ#l~%h>k%1n(F43E%aHd=I2h}h3
zh+6ldu~)SA91wk?pVKiH{USLZY6e8<o8j7^D266)NK~^Q^E@o_b%4l-XtxdE_e4qx
z%iI@zOl#(-C@v6v4@4i+O@J}cyWQ|<T=ay86)sMQ8aH9SCPhnDL+O<0#9=6XC@P{T
z=d_5Q1cNi8Z|RcUtmrLz-OY&(gusNY_y9%p?8GOZM4!D_e+9~ph!s>f>>%DHffh&c
zvMb=6#Jk5pj*9P76w6t>E*k(Bu|q87cU{HLQpm_nTtZ>dW8$>U;M~Rjv}}2Z4{)L8
zxVVfe#XQBIQk2t6>`40<Z}G(#jKW9!mjuLDtf1P+6XM-==<^fXvH<WGC(+e~lVW}o
zl${b^ZH7pI_$pm!IW7J(kb<*;;z{}d*cq|=>*zcyj@<x*LE<*5p*SaAJA=kx@%T8n
z5OFXqTj#}_sEj65d@2%lFNhzfBVCyIi&GE@7jLHGmI(3K_rP5ge_}x2C2^?~K3x`v
zQTQoR{5vhyQDQx9H?7fPLo?_V@lOqqi4iAJwD77p%odhn#cwPC7bh;JWhY*|-U`VC
z@dhOt6UA?Bg%?R;TdE+xCjR?XSh_CupyG#AanTR3lqN2q2t~Sh$*1rsLtK6xxJ>cs
zyU=n&oJBQKSypivWyf!dTOGk>i&^x(#0RVY2W>gxar({WikoSpmnZ&VCrG~drK>Pe
zAa0gIO`&*SIg}QOL+D0Lu{fFH9VOyb-@;(2SXBitZi}ltVWCVMeHH$ei=#QfRfw?{
z!;>bqX3PRnDSo;Y2Jeb{Xko1q|M~%d)nc<7fHmT$serduyyq)O)`^vLX{TOX+zK@f
zVo4188pV$Y0dEqo^@m8axRrK>En?GC@V8Z*MypSoxOWbuU95Qs3mxL4bbja*XIgK;
zjV^IKm4I}MeW?zzNBjaUTfJhH4nyk`FWC>$FWx`_%>nVPzo2wbeC8tT4v7VKFzjJ*
z69w2t#GdUiaZl{+2i^C@*}H)o6&IZW_dwj125w9oJp(P{V*lMB6Jj}&k|UGi^#Nd~
z#532R^r84b3>v4!YoCU;8L{wD^v#OTQ<QT~oIisR+DaTL%4sM0kgg8dOAyb;gD3g-
z18@$K+U4-jQBp{WT_?%W|2B`3?<nNtEKyTow~HjL02W*&<#Ti)+f5SuJ%Gm~?|lUm
z?vm{zARdx6bi?tu#BK$Mr(}xOKrhM9f1uA>QdI-aM^eg#8ed5T?K4kEE}p@x`AH@h
z!-T)2i2}waB_Gq*LQhE)^g{}eyg<9E(~=LVX6mfuhxq@#R3`Z<0>E>U55(vUmdq@M
z!4OI2EdC<rCH+(v5-N$@feF4Kv40km7$(X0he)_&K{`xCNSe2z@1msr2rONaFblw4
zmVC4vjz&uM%!h|jl6Kn0MN10kczQ*$t{+-rB-<%!qP;5lcs<m_N>)>VB~H>pk%oB5
z3zSDmkYu$0ktnI8^LUcvQ=e7AZ0jZZbV#b?bvl})Nz&;wo-V1OJYI%m!&>Ofl&qw5
z#0?3D&d*trh0ZW=Q{p)bC$c3qw2!_esXPmj9LYG9k>pC4w7JTYRQ?wVk@V3owm|YJ
z-G(cabWxV8ND`6{K(XW>EBR6)iKQ~5Qb}|Ll-`!a<N;A8iKEm^xnyY-`YI$F+~CX|
z$(@TBN~Oe>k~nuIuRMmnD#@S2Ak~uBUc)TcNbH}4&RR)sD_pCSEUo}oFR|sqrv}Li
z+HW>Wg7-jmlVmiJc5Ka(XX)+RBKe(CSgn$Ge*mIQBBHQTyF~H@>~=^t7(hBDFVOnb
zB{@k))^5q4T>$h*j#6r~SMt#Z0Q5;5?x3$<;<+5E2PD6iLu62LXA?#?B>AEQlQ1lK
z^&lEYBtie9iiCTToAZFUFWHj;_eUj1SHQ#r$zK|fG09t0)jKYEkM?*Ik{{_;H7Tj=
zN8^;_Il5f>P{N{f*0f}IJ;;p2p0bIy($6XSU?*MjAzZVUKIaAVN2HZh^y461Fa=3R
zsS}Qs*7;7-iPvHGsPy$tAe^NkbmDN4&QW;BRr+%~yl|7=uZH<!QYM{F-KCLKx$7bI
z_!^duOFxui@;s$QRB+}c6^BC7Te_bX9Uti}3Lg4Omr`lj32A#el=(?J-iH={Y0)dd
zSx-ut6!AJGt=NyD1xQ2R1md(bk)j@f(z_HfJ|mr`T-{me^HhryBt1g)3FoAFJoE)i
zS5bjLh_p-%ZRe%uXu3nC>(+p~Ae~+d$uQ|Bbb}~d8u}Kv2x)K(>|K;*q+o!TtkV6z
z!l}#Bu{3l>N^RR<DN6bstxwTXKgt7Mk;-XGW2Eao2k@#?QU~3!($kdHi<5fOH>BdF
zTY2yzL23~ImneNe_v4bJ?exC9CjFEGSJ$O2cF>Y6?Fa@SMap;tfK(}W<VToKld4`u
zYr6E-cbLQs=?6(rlPP`2XE=1Z^-Lrrv!(lr0KX-j@P}ZIbRDf0xzfkzz?>&#Qjj%Y
z%8mqAAkBRb=tAjLAv70BchEOHi=_>_(O4q=GYhy<DOU@?ZRuP%{4A5E)Ip?NdQAh7
z3aLLOU+zfX7C>30v}Fem!@VnQ{{s_SCH*l6&QwcNp8}#r+DVUQt#o%DwAD$!(V($j
z`mzSV2C4T0_}eI*y^g*n>BtD|wn{&v(`lPDk+vi4(mNAAO&3^J&JpzWNZYAouvaRk
zTFyS{3&l{~FFkM+W(TAR)#w|Pet#CKhot9TgUGP-U%G-bA{A_b<UOf<7wp}a?q<OI
zQE8+Z<bky1BBp*!nn7{bap?*tI5;8QOVOuE=~F!bOi4esHbc!r>0|_Crlpw+VPZzQ
zoi4-9N*(Bq>74ZUN6}|1J4IPMJJ~D8pxa*dY7H8X$Y$OG=OFu%1AwD!;|c(rWE%v~
zc~rKJs^FbvZgj+OksY7~$yIiUzD(pM+v5w7W3okT+O)dMJZb0PAxo}>%yHS}l^~un
zY#i`R$u3iJ!dv#)2~2{IY@ZvH`pR-|fSizhsKl83WbO74@t6HX3+PFi`e(pT$-3!H
z7$BRjgWIQNHFUlUlr5!A=NVZF{Rg_UvS+@Uhb1UTR_}w>bF$THI2A0rO9878*(xT~
zoR=-7lXIx-Acdqa$eifu4U>gMV4lKdJE?jrLUw?TKNn>S=;VA!Hb(VNmu1C|V}c@O
z?G+$VvLJ7mkCxq}Ak-BZhhkDOvba0+UxBa6s{VzESlO;^z{klp9tR>`#`z7-B*+}n
zFtkM3UD~K6$);&Le@&K4Ran<$PgBuavh3~zxD;8|Yw$2t7TgOiP397ZzI54Z6pYG{
zMN-l!Q#L#wT5iZ*Sq&}Ovbs|kwe^;4^C6hXk*zNP$(2QfVla8KTO5ey%hun9(gNAl
zcc7+FmPG03B3ZKtt`*CU_`*_&%tX2TQrR*s;J0O~J1{e4vi*%PQ7&6azrYIF%H@!}
zBU?)W^-7sw9sqY`PKRNk$|_q#x9h59UUbjBMz*gIowYLMD74kdHc@D!UiJYK6VxDc
zk)f|q7DP$5CfPRn=`_m{=?B~*`@0RgTV>WN475$QoQ^2%vg(gPI%LCKz&mB<egWx{
z#nZ;HTlN*@fO=$BMm=b+>^7~7eX?%a<MhimeS^jUS;=;AgR)bv!2KZ^{#`X5JlWf{
z-5ini41v2R<5RijeOVm6JV#~hKzR5-w&D(yjmc)|fHf|Ap1z+oA$y|@WK!l!3*nS(
zYzpL|Y`N7Ph-sPEi?B2!+x-@l&dOwKz|F}_R9a~(AFx2ToqSm<ID5GrJ%2~!2X<hf
z4)TZerf`%Wq7o}7c|H^5sNC>3{%Fqfvvg0vMeg|_?7GUc=z5%+TtX-3WAc`-pv+yq
z>pjXQddNd*e|ucMgpPZj^2aK`dC50Y7{FVeP600;c{F{(!dE^->;DP)Q}m+qlh;vF
z++V)`1T3ADyVv0_a!Q_b6FLLr70;mYw7h^e@PYEZ)8Nj?i|D9uR{pOmNRa&F2D*NJ
zPM$*7se<LjbdC>^4^U$3ynLT0ya<zD`V)4;<(c#?hY0y%3jJS{&o#jACHWQ!MsZpG
z2t|S-<<}@v9wpDDH)^ze55-8Y$g2+k5F-!21PfQ?S#%7KmH(8Dk;TbZmeW@(<K@ei
zz?%g55qgUy%EyjFO_KaFg&(fT7yOOB>+(eujZ2oVIfT9x`Dv<zOO^Lg{xMDd87=wg
z^2Zf$J3}5ragI#61KsVqAwO^cBuoDHBycz7ubqanY<YbiytpOrq%v!3j{K$1VK-O)
zpc<Wd@?<&_<;$z2&{iOS#0kJc`Iqz;Et0Ri4Meg0M^v-SFOiSYF0fP{WDme?xkCfA
zl*!ZSk6tdnLc6gFxj$u@@5t+8AXzEDHVW77%2zH#UzL2vb$DNGmAjw9Kx^bhHn3DH
zkNFLqb@FvP(OECwNY6@xyjKo2jdG{wfp3zJk6=oh<x55ZXp#S%1+G=TuNhj}<O@zi
zq+Raw7YugD7fHc&%IjVQyi4xGf}`E?kG{k>d*rs12k4bs_YA;9pWN^qwDrq>rIX5l
z{4Txc2jwlF!kHoYpSkE8makm{6C?7&KY`qnuTX&8mj~1Caa8Wt4e~(V^$f_EypW!l
zarq2Yh)u{v-$B`=oY@F1Q*y^MaP6UdV>;l|@`F}NZ_mhIy$VaS^6^z5bMl2uG}<Z}
zJ_2W_7+3&=y&{I{IF2a%7$6RcLn}cX6_v5*b5^Wsg(VloCzPyqRXi<2qnqN#pFoZ&
z{-B7uyJG)K;5-ylzr%~;igWbi_Ef|xtT5rFs7!;5w<7U8I3Gpg4Rrb{4n74hPAGI9
zQ0k`${sRvCD>i<KzLSb8{{nDIVOoL407YXuX6>}1^B0gn#gkMHbw&{!4rON*XP4lI
z6r@=6JjgjkADtC~6$>7PGa(AgPD%`)SG@NsOoS>Pr4;l9#j3|(H%#$_4!Xk?FE@ci
zD3;!a(u;}~9z-rF2I>5BS@GFHaFL4f)9@)u@#|G6jaEEOMQB$P;zn>Win$|Dc2#kN
z7UWpP=`)zMI7Jbq@#7V{&(jt>LGc;I3lkNsRBn-^sEz{unqvE7FnC?@0tZ~O;%_$a
zDT<S{WlL4uqfJ1XV)i6N(iJP{rI?}kg>w6uilx&KxuMw3LSvR9Iu`Joiah$QXDhk{
zuzO4Kofx<rMI@aPt+|Rs3X|q3exZ`;e1+*WbQdU|rAqKZ#lg=p&?3b%@1d_)(Iy9?
zMDbWE@TH2FF<82-I85=VGR5x~F;C@+y>Gxoh2k>`nBP&X9R<8n@vt2tcNHsNgP|%#
zZ3%GI3cf1<HC9C<m95n(ir8qaQ%q2XwO;WFy<!^_QJ;cqR5Z~ggeHaO9*|~*y&S+6
z#UO17S{316W1ia-P1n)buK0m&D|IN6Lt(yCv7EL9T?*sVP}Zx^?1f05;*Ai9^egsU
zfY||sb;A(YK}Bl|WQG)39RLn1zA-`fh(b!~z<Y{8%F*0cI6DA8s#tRZzz2%!uYem<
zeBA)txMI(8Owfel(9@WiNrm&P81|H+hW14d6~7jtaaz&t2h}r*03iUgitk-9mN~^?
zE0y}%D(&fTZ>K~$5|5hFho0XfN)u&m9h8~0T01I-?SXJozDN6_qsmP#=yO(f(dNNL
z*_;aEs$4EbpPO>Z0p1@|4laiG?#hKT=<`rI4Pg++l|N9n*i*TO&LLjPqWzR)_f~G)
z0WW-%3Gcy@uaX&!&J)TfqJZ~P4m}IJzj8k%08c6l=RwUW<@FqR7@(~5h8L%m=V*T)
zs5H`6@r?3zEx5DFcc>mWNcqbX&~i?xpj9haxj6vv5ar5wXgsf6pFl_8P~}^Wn9>VM
z4Q+G6l!}WmAFeE}0vDkypvb{R<ttv`E-7D#2L7^g+dYghQuz%P6GSPyD0UOAOgj#{
zSCk*qwSySt&i&}Ss=V9@)v?Nd24Fr;x$}1nH(ohNZYL;{QA}W+pQu#OTQNzQvJSeh
zDZj1(xvu<r5fI7B?<r%LqRgapZL0G7A<SNyGB6SDrz?eg^kpd5Y=noI$|Y1RazhzS
zHSSr;FWuqOO(n+y)!E9%ZYaB@9QDN<<|tpJb5O4GfgdETc}h+n@cGJj?7<c(<J-U$
zE3eQ~QKH;TA3ZEpro9OBx0P)kFj1ylBZo-2vW#wUR48puLgbEeEgc~$mCqEw(p}|e
z&qAb1c`+4^Rx3NiFj%A9HVZAa%HJ-cu}-;+%FgPo%1cvF+Mta12t#XB`u~8|Cgr*%
zAkE5&I{>yQOSfY%t;&}FL1~-PmJU+w%9&E&I+WU<V7F5_KxG<T%BGK?yIcAFUf_C^
z#q$8@RSw(-yiXbX1Gs)=d>BSHptPey=%CViHxt^1l;6+=qhaMA6jc~eW>FmAp3?Lv
z)ZAB=(6TkEyh3+0A1Hn3=QXD6d=<EHrD+$um{2wjLieQd2nEcil<$+sL#5sqBGbwu
zsw$pQZqY&YtTJ*NrfW|5<abbJt6FZY1Z$^?T>`wlDv$Q-M^x`ql-5D@61|liRZ80Q
zIH_W&`r)YR;bHjgtXf6ujf*OmiauObrzi#Dri%Lq+%eTQJHXvl3+bKgp*lYw<hUxK
z3~*1?K_3|MQvFHA1l}so*Ju;(qdNQ=wE3zGv}~PFou)9WpK2x>=KWP?X*+pR_2M@m
zr&JFU&=;WUrR~*eRped31632Bq3?{UD;i#$RsBqrmO-ikT1(EUxc%UQRVnjfAw;z#
z7Lw;xlR_8@RmC2lq{Ri*5z0h{sU{Sdws6&|w}6OH1yf+@qU!l{ATFu$0)W4)da)H;
zoNE7i0OD19-7(Mv)nqd)U01E0fca$AIQ`aBRE_ka&rn5BAS_eW`rpH$T5Asrg{n`e
z(z#f*WFNi%N>txdEVESg+;QM<s}9j0s7z&Qg6?uv^VdLBsP1vW-BGD_z<i}@1I5a!
zR4t!CvRd^%U3IQe`O{0WR`n0%|LauZ0obiqy-r{FXjCZ!;7pThZ6*vgtC(RJV2di8
zPCnLFl{*D=+f`xo-tAB|Q~0q{_0@4`>r%Z;JHKw#2S<VLQEj5x>s9^g20*{cf!5^#
zRquZ>KGnIi=o?b;xo8|#Wl(l>M71v-@O!F4+DqS8JwiXEQPnGH=zE}A9u98Isv35I
zwsBR=%kXqU#gf3ON!51RDNm`ctOqx(dW*{WXH+{WNjj@4=!fK-%5E5HY}KpeP-CYq
zr$EFJ^)m%<+d=J5M_NbqCW@*#sTBu7j;gQsK&Oj3`fZHURV}Azpqtvd{tvLn)UOnQ
zxT|B{0^UPC`aAqSuGS_)#!D@qg(YwG+H6?zQTy$NZeR5x%E+HkJ9mKiskI-%r&DS_
zsv{0ipP@s?Y4y{TISo|D>_gufbqa;4&Z-a4mLOOiN_ABs>i4ZLLgu_$O7(ML>ch{#
zi*R+>3Uo%Od#HByvU*!F3`VMl=q^Q+I)TDXG3p<w+VQH|kB(KbYGyH9OHfBq$U0Gd
zbpj$u>OCBA$?9LrFr*YUgRU^8s)rn*EJJ-h4Q4adFK(dy=M8l?RRLwG-=!$fO?4*i
zXtLEG(}yf_)eTW-%u^pq1edRNy^OvBwL8W63)K?`054Lv(pNxA)hwzkx~+bhj?!i7
zlN2m2R|m^rzCztf>4H1zA1ESQrOu?YY_+;`oc`Hpje7PPOw_Aq*wEIXcIm{J8r6wZ
zcG05#l?Q{Z>W?W}(5C)`((Uc)J()1kp<eto2HL4M&`Wht?GlN`A@z<dhzzSMX)GgZ
zKdR2Wr*3-=efQN46hR(UZ=zk{1NB!p`B>+VshvNDnsN2c3y_&m|FZ^mC)HoP4w)%+
zJ8hF5s+n~EU|JnT@#q=#mPIfztM=IpGN<0)fJR%*eEI@_on~+djrN*rwB0zO*|Q(Y
z95n0bE}f(1R2|0Rr1|SDG#=IT$74uVXN{G1tS*{IcA?W%QxuKSyJ?!wgFB{)?t*!D
zjnfI}_RxIs2gq^FdAc|1t+^fvypJaBCy4lJm{}Ow35_?!6Z|xH=pz;Wn$47jI;nZ%
zOBg(*ap-_g0h)`if;*$Rp94qFS~ah%0S(eDr4aBr&CZ9Ii(t*n3s4iHIdvUgoYyo^
z1|?KeOEqd2G_Sl3rD2+wC1?!SoTD<~2+i8(p!=exiyq2LnuaiFxvXiTmuZwHf$C19
zHD3pVT+!&#0Ep4NRt42pHLKSqLMB%8?igAVG*f><O`^tM3@%Btl+;|)e87aI>zcqu
zAd)rxlmki8G_Qh(sTz*Y;uN;EiHdJ;X!gGjU0Iq4dU|hac7=l6(ijJ!Bv13<LZI_C
zZ)ZYtf##``Ko@Ejg#l2cDN6-ctZ|P8phS~!8`E2=@%sdQw>6e^AY~eT9Z0#x`3~R}
znh-iH-_g8G8R<&RQ&tKY+|{iA8uL@5>A4PPYBg_OhPFD*_Y{q+*K8Sqi3ZK5?HFIP
zri!*>Et)^+mD;KaqC{Yu=K6WS+cj-elii_lTn^Hyna+V^m&W}c%w4zU0!~cxdo)ui
zAibI|@1e0zvuOck9{V+)H$csRri2#KK~33fXdKZjR=}B2&9DD$+BNS`q;X7Bn1{Y`
zO<D;66Plm?#RN@iK3WG$QyR&4=zFM%q$PJ+lNN%;8BNnpSen&by^Y2>jfnPN_S&OA
zf*jGl>$3<Cv4ggW${!rHfBp^`C+!Z(v>w$uH^98JHsv&wx@boNF+x{uCoNNM+FBiy
z9@9QapPqNu&g1~@sdb_^oR{{EaNxYPlT>Koqg_S?fxg<usPyoJ_8dh)PHJ~9#W+uC
z!|?L8&JWN&`z6$z);7!oK2ZC)3&wOtD?SVp=d?}~V+hu+{Tp6{X!le?<h*v@Ef@^d
zzD$#FL7R3GO2f2gs2(g_`_4-ML}>TE2f#(GUkH?4(#irb-pkry%8bQnxmzF-uN|Sd
zvNb_#N0IkL?X(v<le9_B&~{B5PhWk$u5~Q{Fj-rh2ay!*FEaR@s?DM*x-_k1D@eLF
zz7dXQX!m)8%hbB`Lh^=|F$ykAyV3#5ZfbjJ?aJ16dcwjjZ8_aB&e7haH9ps>ouEi(
zp0@iVSjyK*=r~lMJwfYuq4xYHs43E_=wef`R!tRpCE7mvGnZ;V`~^yHYjbITP^P_d
z1EgHLa4k$!Xs@*ccSpPMEJk0cO<-Z5ceQPH090uWN~o^ZCcgwnYqVA+h2v|ros=S|
z)0WZcre1rD37H1%if;jI)P6_{Vv}~qV-RW97SO(;MLX>ZORd^tbZMzgtK0;xUHgO;
zA{|;GrGYxN-^OArUD`EtU8q}okg7I%v|pEi>(x$D*riYVzLmal+OO46;BY{Dm13!b
zS_dV#A#EZR7Yu7ZKLwEyZ7x+8-_stUt5f&2i4;&C)o!E0*azC}vuGUC{!S5#ajk`}
zC{JiVhzFU}&QWo|ly*H;Q_pCvw6CAl7BDc*Ic?x?bcnRqZC?$UBf5iBf##t5_8y3%
z?(IIvIO#lSl{>1t`75+J>t3RCiHq*-XE0D#-Rqkm>82C2AaYDsu@wM!UHZqc<e^(e
zC#~bU&0+vNb-&SG)JtdoH2~ha*Qo&6NB5Tvy+nO=vTre7f8C>$G(V~P(+xhI(rsV?
z5uhtefaqzR=Ovg3)CpsOKcn06G#bz90=|SukS@^&jpuatD9RPAb6N#uAv&jD(05+9
z>{WOXs*8LV-e1s34d@Hg_0rBZTz6YdH@h$CUZqme%Q^<VnIm-<XpxW7xop5FqIEA#
z!tNE_@QWBlj4op_B(Lf=Zie|--A;Rm#OY4a(IH+}UIBQ5Zt-q#iMm(lB1@8vy%6TF
z>1?Lp+I1c4CE${EKhwmf=v?WG4AxX#1C<Y^={|o7PNnN~TQQgnT@bxCGj-3=mg|Nt
zCm$qBcRLWS-PCc*U?N+0?=u*@rSqpZdXDbyyD*rmdtQvjJl)UVLQB4`DFEIV=mI_i
zyik{Y5(bNO$K#;7Sl2>l^%AQtZ4jcRx_4>weOp)I2ChukavH#LojC>CDs-uXFnC9o
zWCKK{?rS>s-PIjg2)k7}4jZIe_Z`K6YIM7)^rcq!#X%UX)7@?Wu3qQ*1e7)Co}`RO
zqpmy!jZHdcCzLhotnWSw+M;`o4o9uJk$sqiHeK;b%vZav^LzAl=$_n;zgoBMH+uYg
zbjcAg(W^_Rg|$yN?*(xEy3qsR26UfX1AI{DO`G;1T`LtJ59{nGCp@BiiFQu+bo-CN
z-}|~JWl%k;yKg-L-~-)nRA4oxt3L@B$90*`;3jm>*TJVr-Sb6oe@Zv+M*tt{zM|5?
zX<hhZusfsE(<SFw-ScaqdrtSyk07@C&#7|8PG9AULD=g{!q9j`zu{dNbkHYK8HJ;M
zFBO+M>B|ym!8odS{R?)T^?6hg?4n=Q3G=S{zk;F0O@I7TkYoB<ifOv*yIzA*5B<<9
zz#rE;(h<v3pZFWJc<CePx9+X?rW<lT`dvwA^wkT$0e3?GGzGN$^rokP^Ve_K1Pdqi
z_rfTNaZ1mjgiwG!gUT>Y>$5`PVxa!H1n54auctDiv-<K}kRZKw56qv_m(xv&V13|z
zkP!X%RC9b@A3%YJF#RJ@FcGdFrKci79~c8KF6v#jfV-q$B7(?eeKkcoBK0xrpTzSQ
zrB8kzY_xtk)o5SQyM#eBM*r*Y;I8Ulr3F1!|F9U1ae6JqfaCQ85;P|0Uwso(nyBAF
z<tj<~hhmKWntlfrL0#A9J_(Uz{T`aw6#W(%yhznoM8mZ-{WiMZo38)P7G|v(dgToa
zJ5!%x2DzaR_lIbf{)uW>x~Z?EeO0#p=omzA=|8!N#vJ`R3MJ+0{|$kfJpH__Fqp4D
zLJ_3`J@<1=UZMWlLRc!&|Gf>QSYJTvd5PYO4?wBDjY1T+_1~GHrOc}Tx&&;wzMJ+E
z75e%~AnxdQO3+xT-})@bUHxGSM^x#j{(?xg{%xw?tI_YFYRg*vsu7Sn{URz<s@LcE
z!bF4q;9AT@qh6N{(xm6n6^Ca10a^@N^yBm~#CH7)^up`VTN}M$qEr7=5A1g7H}r$+
z)_+K!ROrz=QSP-@FWn8%KD~VdNWb293{x_oe}NKTgZk@q1Rm1w*MSV{v*}ndqW^jl
zL%XNvpM$0Q`XEY;kLtJ58Rvn%>Iig>>DSN-F|N0@+JR2!yWfYwNxj1tAXEB1Z$ZsN
zeU=-zY5hxjh|K8Uq~iNo{dtOz&gl=+F3Z;NE9IK(3`;16WN%1Z0E0&i$3F+o!SELq
z7&{uA{s&1X!{$oZJ!&|$8CskT4s<qhG5i&3MW?Hwl&Wdn3=3n>dd$#4Arf~(U=8pd
zhQr?jaon(oF0p$W8vliPFGEN?eDXGg(i`5#@NFSPd<|=tLD>nz+>5Z}XW&xprN807
z|MGp(aGvhho-)j?11`YuI~7ZxHmu%E9~KTY?4_mYjNxW2WX>AgY@jsA@VNkuA%-Xl
zrkpp}ki(&d5c(m88{BDU9%1<993(FqHY(w7q#@ga363&^Ednmuuz=REB!kr!maZ92
zQquIgA)F$9$%Zc~U?|0~av>ceQw<B3qBYGBLuZwAgOy&D8HQbyj?OeFsfO}~;lM&z
z$};dihMJoOYYr@B8?Mp9c*}6%6IjYIT&5FGu3<SP`11^_5+IUqIJO8P1%^j7&{Ala
zM{%tpgXvQMiVgEVg}t36hCfV@DK!`$1@N{Z<5>X93^|lRDmNS$hWizUXLI4q9YeG;
zxJtwKPeILH!{_nfstjM#2N$Xh5tjg{F_=}DpjyKLTj;DaJms@Lk8SN(4|~mqEuTW7
z#ZX6w$5w-v94@sPs$3x7Zm_sRzQYi43XPqH)H0~-GB{p9U$;Sd9_D%sTaQ6Yuc2=M
zZuS{mL&5bM>R-XU3>ZG5oY<hjHvsS<!<B9r8a8-SLClCD)=E{o_YAM^h3I|5|7fE+
zYAB*-<AEWQ{+?roxrNX+Zg?yTmL?3VS>PrO15}$gW#}-#;6uY-Kf|Y4!yEB%bj}cb
z6uNDVO|*-&Gu~~)Oxhdw1;Ee|<I~w_bTD>M?Te%F^K}#_aWek&Ba|LBa<S&lcQ!`R
zWi1zDHNEy+jj{32=4M>i3xmguqHE}LH?E>AmWS~P`n<$(qns{)c^aM8L8+Iq0^#@h
z-o`qr_wX^ky$+JT#tlx8JYoEjj?8|>S1G;kZ~XTVU2X_4Zl!m`Y2!l5z6BberSjJ^
z#!smh<*f0EEO;1XjQbx%&KZMb5D7N^K#}JV;{!?>o;Ui_4=>a>LGkYk#xVK<MVL_@
zfU$%dFKq;gFt$YiaM2jn3}u&$6<<O1WutZl6?aBr7N91|7*5rE(Z<(lPkF_-Pzv{B
zj8_;yTs5vw1{Z7m_9(bGV_P<yi8l(DV%Q1B`{m#gjUW61T$1tS<sjFL$Y<c0GB#}m
zNjCDfgQOV6_d!yPMmoEu8CO4wzlb&67);^&45M2KS~HEG(%Jcj(VhX_S;ig7AUBOa
z{0*hq#t*h*6t|4UH=!oS==d7!<{G0Phxd6#*IVH7jSLC~78rFS;0ldQI*}F`le1u{
z*w{rmq7q{W-DWE_K4J&lZL6`Aiy1027FsaEa^u&F;6;V;r|*EjWBkGlgO$cI%DUe*
z@~JGL%J>*n;#V7gqQ6g#QA101tuc<0oOQ<Z-_TcYe1YCA4aR44VX4u0o+1V<#>);6
zX*J%aEkK)bWerBwZnVDc2YiPyr5wI>8o6|(s>_)AI?Q()-_Zi!V|+kWAic(zEx`8~
z6T<=MH*TXM(E;NV^jjS?)=}<$$XG;Gb;HJGPoi(c$fRK4J>w(e=(}&^Q$5_M@v~?s
zdtm(a5#Yv*A=Xbp$BhxRJWd&7jle%N4$wJh+V~s=sb-Ac#~?CmoT7K>oUwwU8Mda^
zdqM0>3oby?-sHF*xFe?8mjQ4vnI6Y<IhuZ;jFFQm-vOgPYU0z+!`bvf63n}p{zp+F
zSJU|&RHx!*%Ka5G$4v7hVZz;Xbvv|qnA$%EIc};W_dQJ^6q58ZHI<;z+cdNu{`#1%
zQ&p0$sbC?v6Q=!?ul6&or~<&>v^W>aPMS_q>f@BD(TK(XlRZ^So;G#A3NFy}%X!L^
zpD`V#*TGrSZWoXs(=tbNo-?)6_d|nCo8zH7#B{O(jpt1(e!yIWn$}Rp_JZkO+HZ!L
zRFroPH&vX1NQCKQs;0PTDy7ivB~yP1$Ys;oeVF`6lkWy_QKlm{P#tZ`L*<Zl{uR@*
z_rb=PKBBt*tEMR`3Xe5ieu#;RGbPi8BHpxM9=u2}c}9RFnvyBAmSo~h!~8Xq4TZ?B
zo8l<<k!-SmAGj2gnQC8BP4)ROm}Yw37k%lb+T&=vVH&5)4Ou4hHgMLPrr)0fKHKyf
z)mYpzl{UhQ98-K3<}%kb`V#u`Oq=gOX};+iMb`>U1+E~4CjWGhB9melOca~ED4J1X
z60QbUYWjp$f!n5mRWMOzir9!jl$$1K&ro5yLoen#rp&h?S!p%7#zE$;=|l%em1&Cs
zBdj((K{4tYQ|rqB)|#aBBB?Wt?twG)CKkQu8cfU5(bs4)YGJp@lub*2v*{TM9<`Vx
zj|0$ZiYSJMZKkCZylFSZ(AlcPw9ONw(-hYXT$jmuh>pqKrko^<x5spq-pswG?P@sF
zXL_IRBlMfXr1<*`m=3gq44Mv6P<zPq#6NI<*tE(MWW>~?gqC}zzW1T!zUesKgB~@#
zPWjshCPg}MV<y9YuQAhe*|0ES8lXM!q^ZP8Z<i_4A9EPfL(>+D<W8HGQ1Wlals<~S
zS<?%&E1NR~JpqKRIgb9mcIGZxwd~D-sQ?@?hui_@U>>3;)zN(H2>_hURtp+k%ubsj
z;%aWVi#|6q?<l6^n3+qlcz1K@cUG_-=FOkM{BiTARG#W-ZlQ8BFY~dLKzN&LR-n<x
z9G{0t^fkv*rN;^L%}pSF<{1PD=KGr~2SHAnr>KPgl-ZXSiU9LGTFOqFpQQyR(424<
z2G5wkcm}G^nj3ZSDac&<I_2rknU_;`G}!z&1-nAb?Np6;-u%f$;6u&t{S5Acd5C^q
zVdkf)Qa9ZE2Zcl<%n!Wb_C>QF<vuQ%MH%S3Y#x3E$|B8s=oVv?`NKF&WwcpHTY@WQ
zW*2ZV<~n+DT{Vv(zGIyqYyOfhh{c)j%>fv1&Y~T4g82khb0nHu>E=O_xwir1y=GoO
zMQ_*5(^VKuvY9c1z7%r^z4lYheUzd~Gp7WgFWvlDFO+4Nqv))VY3^7B^Eb?W7Kmh-
zH#`r(O><p6M6B6n1Km8jW%j3ZdyaYUeIRnpw?4#R^2}+eK;)apk3*!uJZ}Ni6q^5z
zfk=^=w*p+LIZy+CZ<{CR?r52Lm~uqrX4Z0uRG7s_Vd9Rtm_F-LX)d5>?_KjR?_m&C
zX6Gdsb+y&(NLzy%^Is%dYfkC{S7$yv31{lfMiEGZIruuXHJYm_7v5x+?}eIXb7(#!
zTg(e+NozGv(-YTbHc%|I-F&D8x;xA>%V4R~ypy7VUFHWXF{Ezula#yfF}qV}ve#_=
z!w(MknI-=NqTlS74sO64N@?IhbGZWMhs>wxQuwg>9SiUy=Cc&wxo18}!M*$DCnya(
zYPNBK(g)_aD7ZFeZl$Gg+-#$R$b>oA3%E&h)CO=<=Dn>j^w1o%6y~SR2dvKlF=L*i
zt--8${$g-*=0IA6Y%M+apvKPP{v$Yh%ioUxf5Z~d0-%FM^(zcITDUa%PL_lZ;KfnP
zOb-CgmTv~p=VI~Q1mbFGrgW;CW&2vdk6FH_)!p54lQzR1mJTl~3?8?<uop@_EeGvD
zyeurbQ|@g^TMVF&<soG$Pg{0Va3aw1)LP)rSY*Snbk_3a5auGt(()S`&sjdzKqT10
z`3K_-u~bkZ^Sot%PE(<llhx?EU<p5oz6eVkT|&QTx%LXxNnf&Tqq>pHmYdxWjkMf7
z2ohykGY8$#7W-ZB^onI^B}8H@VGH2zRm(a$G{jmCz5%6imLY14w*=A7Ai+{YFSkU?
zPC5`LS^6%+i))tN1aQ|aFS&qAw)oTHmtt9(OPBjnEq~2n5;H7!`q7$c5mD{;4a=+v
zB+C-(4RX^mnh2%Ymefi3bju=?K~0Y3LkctHTDm--JI`|ZIW*>5mQY5pz;bmMxI)W4
zy3bH#@!EyHV#}#p0F+oFuE1WYWgAsrS#Mh|Qar89(!2^X<(4yt&{<*0Sp#y{GEN)j
zD$9c%5UI8Vtp=jTa)E*&wHD_x*sZh3DOy!;Ik*y}!SehZ`Wh|mlqPAid}qPrHCukB
zdk`&_Um8GKEoZ)kvNlWQ8<1?bS}s$Tr^9l?0&Sg^zdJC{E{oS0*zLCbL-jyC|L5qs
z<Fc;0xFc+tWkY?l(kx5M(#&V?y(gA7G%YR7%u3Bl^Fc%q6j>t3-b0p50Vhjk$`Awr
zSq_jT$WTChzbF1VpL6f|o^$Sfe&gPA&i%1!{alFNUll;5CEcrb(>aWuRYMdG=v}pN
z8328&-kpiQ{#7;ZF!5kj<1<h;uxef^L<U#gb%4mjRT}yX$<V6NHs~B)rJ!x@$ST|R
zIq+t5mFj(XF}BL*0)XSIW}F0>Smo0MOHWoUPXRZ%s(uls^y#Xg_23RL>I=X*GJGxr
zevqLaf?X$u9sTHs7)9-{>&)0w56*?Lht5JCW>n`wnJZ&0RfxDTS{I=42*btp2r@?*
z&(DJzcSaDM=QzeFqgSj4BQ_fdPsaA2Vabcp@D&i=j6PZ@`!M#?V)!^?7riok8MiK@
z@dRVe6mWiw9Tc|oXH2EQ!%4=Q6jTggyhU}Ifs8FB&>6&d{|R&kGyGcVxMm1L^e%v*
z3~MpCFvcC)x`#9DPh(6Gj9s*4i)8HH11^d&g_g0=j06!#3}f3YD2-+G9L1EzF=A*9
zk-$h;2WJu)S_%p#G4^)D(PTy;MT=4xile}tX6$(jhEf?7OXzT48e;{;Y10|EDj}M|
z$fJE+CZmd;Wm$~myKv?V<055jvl+kAMU%tm*$v4&#;S2}`3x_5G8Hhk(<`!&@z;Eq
zFJk;+gTc#;FHQn}l@VgZc#9cr*C0~DSZ)F-W&Ghmhug~-FKmWP1;a#Z#cPa^1L&+|
z*eH!w#dyGmwrYl+ev0c1lLz{089&p*vyQRjza<;vz5ikijG5~JXkct^1mGrPTP{Qz
z8C(Ydni!r{FyGABAiyAQF`SmcwHC&{1PsvD%BZH)U>jpQWs2JwMtakBFcwl!@-`!=
z4odGZ*3$mqE<;24zI%*jTI+Q(zOV=BVtm1X())~!V-V?P?3skp9>(|d6zFBNl)-!-
zBk(&Y>t|#qfP26=F#$5b@S*_rpqh~@hWUq#AFANg5W|`L9%eYvdSQg&M$4R0M(gKr
ze~hu#2&LnUp}%2pg5gGm^G_Jh-$&ylqt+*-VX5uAIS_PVZlZFJ!_1mR(Co_GPkBu@
zW?&b%Bg{jo5OHVnbl{FLJL$Zy2XiY0<vf}5`_bsdoN9(jZ)Wy=;Cz^_w75FXbe{v_
z%PgbF@d@U{9N_$zqqz|AXZ}Mw+LO$Kwk)&;FuQ4i9mq6Ld^LzExr-46Gt;>sA<PAI
zzlAc-(lb7c`SULj31_Z(1fL?9r>=mDWcqc3i(>vz41>{3TQm&DF#o9qiDf2eAQH!X
zZY2!HGso#Gd8e2kQ`LV0Gx-fF`buQ3i@{Hj#9T#5)?}t;Gh9qz?tK~DX=afG=F^!|
zLm`>Lyi9xFOlBd)H?x?HAHnT2Ov_Thvzc|23(sZtQ}*jD^PSH@&M`O7g5-H7YaYyB
zU|yz}+$Cm53vhYN{BYXL<uj*zjm`q*_(hDckXdjOotK%fpTL-|FgH?J_f=;2E{GH}
z+v%ZG!knOFODXe3ir17e<@B&DXKtj5<O=2rCy;B*!%yISC9{V9tymTFSp&FgW>6S#
zHB9*|sJ_k&#jDL`SIgYqkJdWoWDtgSgZb|QAnKXtD3I2`w4+D%P3CU85*nEfgXn8w
zt`CK_W@cs=EZt%rdkimHm?pZoTA8hnfoo%$Xz$z33=M_%9n87efZt}m+XzSRFlBo%
zPj{JJRQqMS$BdCcrjt2~1JcF3z(Z>fGou5RdYR8rZBife+%v%UGes1Ae85cl7$O7A
zBeYj}$h`M9a6`=6WoR5`o|_A9gz5hdyclIJPKKq&%xjeB8e=kF0U2i&l9mbPD^xc4
z#Kv5*3iK({LYp!N)+R^TJ;3^71vp1mVLb2$S+#$_3n$iRwB|U(`h+qH&aB_(K${C|
zn2Lf9v$oV=E?ilcM!>nTW;B93!s_3J89mBU)Ai`iVm=2$$5>xH##lU9KfQ%UPnJzf
z%LFf$(+ZgIW{p!q(uY+SiO%D!6_f<<Ww}s6<_Q)n3O@O<Zasw>e^%ut08X-2N#Jh)
zOH7}N3uJlyS9Z@@Ku0}-SsQ7i7s48U173u(u6+w!7^`C;w1l%x-hrVAmdw_V)@W8F
zo!^RKnW&sRmi2NgxHy)a4SYQ7-c?vS#fqXWe*&vg4L}m>o%N7RX3fh$V+t!WA6}eh
z{Xp-nRMzf~(3r+@pa5w)YiKF@GFiV10LWtPqs`+P*1>c54YFA=gA~lnVNFSerCio6
zicOwny+$|nIo7{6jOjef=>)h7tZpi~xyaf<#V>iR#pRfpd=@JdTmdVD(q@IMhxxEu
z#Cn;ciI-Vl(&cf5^~($JqL{Ug57i~C*f5BcvZ|K=Ud9S|lY*J$tlA)$s9^o_0KjXk
zh2&xtYk-mu)vO>M)YP!XC@yxLwYU>~wX6@D(O1WsLuFGpSksn(Yhd-bgS*M<qP=q?
zYZ^VAn^>7Ou-nYCzlz3ImNN%~Xk!H*hO%~6*6b-$d<-ow*#7l~|94np^yt3JIzW4^
zPL_o7xm_$r+DzVOJ)!+fH|xFcpr?lw*8(?sS!XEe*@s^p<N<3bo$McA&FF%|gRHIZ
z0Pv7?pNg=CSloZX4YSs}L-h!&^%%5_vK~=l@DZ!%n+;$evz8vm4>iWRvkQm`mVP<Z
zJYh`+!qrLEG+Kc@W%ccV2?uu8GiW@(E};dDBYTDvl1}V?GqfFI@B9vMXEtjO050t3
zeLibNVQ(i49A$q(hcVsRe~d%o7+c#1v<EvN3XPs@r4kN$vGxDL2XFQRx~h+}^Vg%#
zm;K-`08X%Flwk8?tCoQHv$uQ(oq_B%6tfCq|3vk+!R%w%;6m8Xb%P6Ke^3l>!`Sz1
zuVQ|}*~PR4j$|_^>lVdMr4yym>`nA-&=~g7H_;f&UP_~lW7}x7@oZoET@%<5UJyxS
zU!fY{B(_5`8k5=YP>d~wed7&qr`gTX=u2hGX-k*JzD=vvbT*4_)C~5otLYlgWY4A>
z;0zm&5?uN0c*>yUu(#R4i(K|q+A^GFf3CsLbB>)y$EeP;8~Y)0k)2PQsY~p=N=W9h
zd(T5lK0A>rVG7u9E(2G{&T)iD5&LK<$QAZ(%B@~ye@M&nV)i#z=u_1t>^JtIvy}bv
zI{Zpy>=|Onl(VNC0lCIL?T@}nwu+XrRqWC-kZSh)%V?}&$NY+!sbklwFv1&b!@F>;
zo_%TpA`R>oI!Jqy9dQVajqD8C?lrMLJ_2%!{pLB47WRu+UfAqf*_+$pa2q>uHO#lO
z!*)V<2m35tIk(wiL+HE9ZloLi9{V6Ij62zG!*uzx%c<`CK0CJ^2D{mNc7XJ-503)Z
z%bxi*rmK&=j7rG*+4dAac)&K$OKFgOjUE>d*?aOJVjE)X9WlYf?49<|J;MH;Qd6Vs
z%S?1WVn0t?l`;0n91L`v9r+9-C)l39K=KKD-?xyQWFK0NzNhS4^dTMxju)*E9XV^M
z0Q(^4I2BPjaXQ;U4slxPcXj6Mqs5L3M?weF4%;{@IS_T@T%eTp5zadcVd5yq?kC8&
zbK)Z)bBxpR6z+R*#^{`xH>Zx?6+WEUKL9w+dGSRI+n3`+UxPTo`JP1lIGNYs;Ym)<
zd2j)oPwBB7$VsFclpszXEjofZkzC+HI5sJLYb%s<pAt#ooOsG?M{rL42`-ZJ$!l;e
zievg6UPN<@y=aW#Z1BTiVmV>79E;=RrhvqARP>ZO#R;U$PXg!R8xTq2+@;4vGUwD?
z;8HmA&%@u-oIcusr*hJ^p)ZZ|)JB=Bbk4LQn8@TTr7c4i=L;%yJi~FTfwpYUf%Wh^
zhtoY3jpsNk-vsbH=i9w7c!Be7C;%5Z{zNWu7OsP`JWeKgn9uo`%H<0=m92mmag2w+
zUFO`$hWRU;S5Cq0tDKGB(;Basvy~P!C7fMCkTOp1I+!Tu6jA+Z1!pF0Xs>bB$)LNE
zv+{W~R&f^53ci~2IxY2TIPsKizs~WbAayP02yHCuID@owujfQkF-8L?dj-tj<h;8Y
zjg6cac0pMa=f;2k*SMK8#{=Hn;(WCYovobhQ4nq83=D&`b5u`Yse^OkZRozusV|1e
zJ&s}>#?;CAI~a{!ocSey-{;(?HElO%K1CyXIO%4H^m5uLxZTegs{r?aleQdWfaBi|
z)q|Y3c2dCNA!qGD$P96^%)k$Ggp?8-<-A0%m`5DxHE4UxS(yxOjMEp3*&F9<qY%^t
zr;(2EJmEa1TE<DvE<MOoj)kV%fh(rV@&Nac6w`H(`y$n#IB`Fn3UY|+MF~1*ZaS4<
z+FZDS$Ds5ucSRaHUAbRUc<KnZl?|DrTzjhHcIV!pCD$=-;x!Nt?(e@r#G7kQ0_Vg1
zn+@(bcP3?5eYvmEzTyOT=T{huANSHr7>hr5_XAi8;3iV}QXp5_3tSLa`5FMhHtt~x
zsfKWWtiw+d%H2z4Ibqyc^t_4SzDe(cNba;LAW>Wn#n_{{Vv5YfaC_bdK9;*H50>J%
zO|<Hc=k9BO<SB0KYiLa1>fZoK<hFc{u_SXBX9JMJO_&1iG&kM?$yBb*pVoS5+z_e*
zPv=Ugd_9B9JOpi7+}&F+C1<#6sYWQ9dx%Oia=3GSAeqbkf}YanxqnfF;{x{>g}N_t
ze|ZDry~I65k*_@N=hYzjT-WW;S-@Sr978JP%4zRf#Pv!-;}veYZ5Cv%auYOgs+jvW
z<-|+4U#x&kDfgrRy34s&mH}A7wb-NY8n>G&QmVKi^qQ~c`e`v2HQbQ1=)2BMrYCAG
zxAk+7I_@(AP<?}IpnY)z_XAp2+~hjcLUkiIaVh{!+}Z6^li18{dj!NS?phT(Teue5
zfVFXJpM~yrZj1{=I=BzBq3t$zFU5@SaKEA~_+4(qXYjC#`;g9p-RBM|LAtpWZNT+#
zy_Z9>ms?6VP9K-E7Lxs3%@CA5;I5`c;Q+UDEd>l8a(yV6ImCTP3$bBtR6JxxxW_5Q
zHp*RD1T~MjA5DTA<N8}b#<|-E(fEWLk`6VK+}cENPr1yE=yTxtQ&GeL-uEfc;>cSz
z4DKNBeI`^N;>DFh(wVoJ>Tq0mQ7=(V)L~w9D*Sfk#g#yt8}G0OCgBM0ty=i)&a>A-
z^cZg<9(^9Xz4Z3?<jtmMwioZ|bLjKt?RpD#eR*Oha3^?`n=nv6Uh<#d{CS5aVelmH
zeGUKtyiYRG7|0v7f(znBUPPZQnD^C5;6r&cj=_sCUg>+_!g>1Dkcr^c6hd1huf7zM
zAI<xSJ_HoQ>;4H|#PTjs(Puo*>wg&GDc-A8S)af=Nnc=3<jE-Bn8Yhu4#{L*h7j-+
z-fb~-rt+@*11)L1Ws5=5Z9L{8$Yk)0bgO3a%3pztSv=3JXgtH~$i#J#!<#W1_*~xe
z*}$LWMbMGmbG%V{?Vsm)@z8jI_aY8S*yZsK37{pP7gYy%0Z&YefI?os6W~R>jfEhW
zdEw8&-zz+CTC`u~*<OnSqL_D^F8LCkGkur0l;=tx*DK?_o{uq=^FE<ki3;9JbeQBC
z?>>Dzp^~?easpMnid*oan&(FcMrwEm*8*^zcRmiJmbbMSTIzZGX@}Uri?{^yH+j2%
zhh!t~P9_G?#N*kbV7{5Rm-Z#Mc&IDD4ZwSs-c_x<SPFf$@fL7E+Ij7-0pGz36T$9n
zUZ*c~-{ECYMD{N4Zz}k`$2&j=ayogte#4Y>@kTBJcb~_it$R05z6S6f-dpdWv7dKi
zIlOqlQ-;y|Z-BRxzG^YZn|=#+AM!FNZa>7U{}d*Md5)h#=?HJ*-%vWrYo-<FBcAU;
z;2-l!sX%Lt=T4ty8s~LSgBKILwX_U<!kcD><Rq{DUvN)(Nxwsj1ApT(=sdvxh$_My
z`Hvn^P5wc?!)A0k^P6b3<HDc#5Dp*azaR(Rm0#iw-EMqWCCCx}n=}bW`5%x$cYZ`I
z$T9xBr7+>am(kVf$)7V7TD<u`kuyI0Xo?FT=YR7EIA4DDMi@H5_pX8$e*C#8W4GD)
z^D8&O(n<aowAu;a|8^MoK>n-{$OQ4PQEVoJ?|c#thw^LtU?Pm4LMym%{(HH=Mexm3
z#1hG0NuQ&L;^#zRW}^A->meD#pZX@?vHaIs(HF;e-2`%q{~>*~Ac5c21J0Jnf1wV(
zCGjilA)3s8<5`dteoGF#IL+TpzgjB)T}tw%@jH6Zn9ld4Q$88|&*<_x!%wEgWj25I
zB8cShf8GRVa`|sO#jwxv=hFpoj{p9%XgtqvrHZf%{NWEkF7h8xRPU0FpGGf|JpS1!
z7)$~G&K~$($k!RsSj0a>>9@=LXFbt(g}<#Eh^u_xMIgoe>w7TJ68_5N0F?3tRG(AE
zpPG)oa(>N!dk22b1iY{0|MVLgtN1^@3!kd_3#x#t;olL$wd;J_j$JTO%TLXL!8-mq
zdLP{2Pu_ykdcODv$TaZTw4rI_w^f2P@n5|U$!7jGx&m+UIdp2fg`eyQ(#mh(0N2J3
z(?PPG@9+ogcJSRs(RiC*M6bv@{Ku={Qzzg33Wn5$FJ9ZB^FH5x5~Q17MA`Em{?BiM
z^zsKD!r?ytj9mcs^OF;Sc)(XtC~AQJ3S|KX`7+8w4e_6S2O`7#UDfb+gnvN^6QlgI
z)cA<M&>hY^=5J7fjPYCC;pjMj-CQV};E$!*VD|~X=_WcS`5$ZqaS;4W<x~d*-oHT9
zQLt+vlpYj(Oo1LJK|DnV4+)AxK%50-bm_PVvgu&KVZk3XPp$&z&!O8*Fps`OeN<3G
z+hun_-&GhoCeWNiqlaK=3ILvhm7Az0*h}yxJ*K?{j}Jndk6`@2jfEgX352hp=rFXM
z5X}A*YEBBKod6dgc>g5~El^NNIo=>a2xS3+1wV;FLIjGra644cLND<!LF{Q*3KxXZ
z^Cm(d<YT%b1^1pnGFtFIY?5qtF@ng|5RDZmssW4>L{i{AUhoTLA5IBg+zpZ-*ggbj
z5(OX79w14u`3I;;7Q8(dxD-JMy|_{ZvuMwgCU`OpmeK`#=;f9nSQG*-Q}7)XgJcQz
z(xJpNg6HUCw%LMF8Aff(5h#<OG*{sDHDt~T3TQKWUhuOC_zQy1(_!hNVDmkYOM(De
z4Ce_F4}#<i7E_&Nf#7HpOcV;{90w^9EZz;=WkEVU46X<&=)iD^;1;dEO9c*{0F()y
zqkVn3z=^g~6*hsK1%uZF&+UXam4bX)aaIWmsH~}4@EMgY*9fj?fVeKW+YiY)L6S2j
z=!QVcMqj-kI19QP1n23sa#Jw74I+&K?;wyS!53>Vqs@ZNbD;W`z@M(Q7Qt<Lp0^70
zSrBO#*qFCKI|Tou@3Pz$xRs;xj^I%`fOiFJXxVU2Fn<7zoq}26u+$}Z=X*%r7p%Df
zT({uW=@97=tfRzJpI{B$T>XM!CM-P=%nQaK1_WoRpl(nQ<_z*sQ2QMKLxNW>!lz-u
zpSF7t9T8mo4){^Q+@nA|63nEy+PEN@_AV0wA%%ON2)rnsJ}FpBQMRXo?euvF2ci8|
z7(5{Sf;@B-eo9}uJt!<Y2)L7w;ScyBVca*EQ5T_}G6jc)+s^^#DjcSJ(@hxeLYuoI
z!VMq8o1;QwFMe2eVdn2pdQ7;1hk<$sFU6qGQ|L?IH1`s2p)ib(FpADf9T%?r0w#Qg
zlR3bh5N@wTqo1(;NBHY6EP4^#N#W;YFhJOx3|ydav=cgmgms&sGg!DZ{J#%-38%)x
zi!h-h6=#GCKU9E=5U!=PP^2)l0Vbk^_mf~ES}3DJ{TQL1o`JE#7io1CC+w!kd%Q3-
z7)ld`lN13@5{}R|KUw&l0|uHRd_a4i)57Uge4HwDPJyyC;Rkr?*zD4U=O~7jAq+hQ
zHJL(D9k?vvlj}fa3sa~%B1f1;h3mP(6|_J<D@>6Ce@^H~Z`1R_*DGQ7g0M=8zKcTX
zF_23_??rGePv|Fsqxr&3wC5=l`cQ75NO*>d=`RcK>;<u15&m%smaYmdOCVD$Ovwkn
zMEGY2@TI~}wt|!iU;h=N<-(ulV@wsoUrS-WQpkTE{#FTpqY{E@p^35(H9`)ZzPT=3
zK->IU;X*Y?ozT+^EjNVn!%$r>%nS$DAiUoJXKvac14Og%<OD`>OSpqpqb)-BpP{>5
z*g^aB4q?fM82xSGG@8pE;k=VD*ejf<0_hWKFTifUP)0HH2f`y?fD8!Vq;=7t@MtPb
zJQRLI<#j{CO?nJ)Sh)NU1~DRR*#~Y^XnS=&WF84;(a;_X57EYcO!yXk5_DV`L7&Q)
z5GG8A-6z5YlxLh2Cei)(RCs}MybhxLod6sVE&KzLjv{dxhIUZYN%f^pqDuNI^C3}@
z2}5!g?GR%uE}{#6!`@+0sROjQiUMqOk-LdlJOGb~yxzyKkBXkmfvCGEp9XqN#G-Ve
zhiJ?P20cZ0_XFT1dLbT--lC=ea6Tg4*XTPgT0`Z8zM^gO(RV_${cB9VpNN|dE&ie`
zBN|VNg6Rz%AmY%k94PX!qk@qj5kCuRf<>eB5DO9Qt-<I+MN{b29wyo{4AF4W^Yo)f
zi0qo7G*T4*36w^O+E@TYi-y7hj}gt>0?AlWFO?d`iJrcNDTx=AF9SIx`oxMMC5Su@
zKqOK0k3WW+Bs$qj>(6A-b_e*KA{wL@=V?(qT>`11gH&#lCfY56Xu2qJBTQt79*4uH
zOwnJIV#pGCUqjy+(M!2#%oaUMl`%P@`?Su_75%;qfU}~U-_dwM^bsG9UKCBIz3e5C
zmDXB$qF+&nV6)2?EzE#Sf#^OJG8KxlP6J;gnogzbmqjyHLiCF0CtCSk6-`iZvsh$D
z&)yPIJk=GHiuTdPRwnXT0C>6R%XZkU5T)+~;F{<ZEoLi4e^9Yrm1vOeziQD2DkH8D
zapR!cc3rfNaxt|c&iC-5PBdu;{0&hf6~xwya#GOPAW~|8xG5UzfSN{;oGz~>k!lQf
zn?>(^1Ese_`>3S4MbyTF7p<b}x1gm>wC)Z}w2OY)1Fl1~fdX>3MGZ7vcSOE)dEB*$
zI#lSqCsI+FK&QxkE7Wv}PAo*@eNo00476Ls?18}^(M;Od_llO&SC0Bb7wOXJ7d^uU
z_dw*850L?pp%u76QRO(ehoae(haM7rSPGG0QFsgNj);W+z{63|(k6&J64}BjSn*i2
zl}0!w%D;-vaS`JM40}SPqL{-I(QrJxm=vk0K<%l>o=V6a#P?zVI3Q;FL&Q-$PKnWj
zVkfGPa}xKy2c3t+8!2?)EIvo&OfKTT55cv=;<Nt)=PK?@1m`Bc#i0fM5%B>F$WgK9
zILy0?D}3Oor?~tcOn8ZpO^2wrcmo|+@e$Wj!N_s(y}3U6$8Xx2OCWht{1Q!ffH<0p
z6#~U0v~dd(|Bs2^Cs=%q?(h(?*9E{s#eW6E!!Yp|2G|Q1fAcQJ86p0ZaxjtNnN*=1
zC2mQBNVItE3W&sroqhy~6?e>nvN-YcufnBx@s90~JSEPzQGhE!JYhm-qL@wPBT3?F
z56C2o-Sfevh*Q=Ae_C8W3CUD(^GxVY6PsxPm@fXA62TebXo>`6ivOTZPL_BDo$EUz
zR*_HH;+JxuB}cqD6e77|#>?nCD`ryx#5r;092@9)F~<y<3*t%&s9zM{r3YNTxGx%r
z0<qU9=AuxXt;Wn0iG}nqxGa8sJ9J+WPoc;2RdE~@niPxwEdabk{5vJZO2yNgfh!Y_
zID(XmU!k09h4{-x{I1u;DXY;~DNcKl-riN>Pv!%EU0g};np$xSWsB;>UkTyq4RIF5
zd+WtJFTiet`0!`YeN$Xd+mlA|PZdzpB+j7hR<n31W$$l^U!~Pxi+BqD>{`XS-$JBK
z>>LQLU5vLjZX@v^#gcA|8#d7D`HuJ%x}NWf_df!;C*HIHq*FXf#j;)E7Ak+dFHU(0
zcDu!=DKpt4X4(VaD_-#&9PJZNq3^i#i=8OT^g#T#6u1GgH=QRO6nor*<U{el6gC<X
zUrR#cu(;p?#yKKhOhGT(sCW+(PCXLumx6sP{#6V$W8#f{_<hI4r4(G85I1^5=@W5f
z0R}oLzWo(Mo{EQk;hKYFXdiSRkQjR*=_m<)7qfOy64L{Klcb&Adxs>i(^cXu$()Nm
z7s=oh;0{Y9TVc=DCMl*2i<@N29(Zv?GJ6+XJSt(80q-se_r=hTNnBqB-b3;d6)<^9
zMl2v+k^`5}=Pmh@l5;+iwR&hfF8Q0%y1tUwPtbQlGK(S)ev;|*Zu6HcBP}N-&h;=9
zAQ|}sl7SMNlu~9vl11C#MX==NAY?)$UM)}>DtVb|(8462SAv8~KBt#ygv5#J;vywJ
zn}Ls!#L#UYD~Y1iNSq{=Zh&~nSFzA}N;1YnV}hjb37kok?9GOSB*_pJ=O#;*Qr&Qh
zB-&Ph*3*)*HDFUEyD1`_CUIL0HR+NN+IwV3LXJaCrlh12T$ZFc4%`{ZL)x)rOKu_o
zV3#AA{vrUmlCbsAa#qq$NxgHDzHwMOFNsV>;|0l_*C2UO5-J6ENy4D`Wu9cV8y$DZ
zm(&D;6i8<6gYH5}T^O_#Ni=llT$U``k14q#*}WcpS0$blJt~&8Z-j{w$;eyKRw@xv
z;c%Hmb^%<u<mX}Nu8<VaJYSQfUxKnq$yaokvr4j<%G9bQiZG0&MiOw8%B`<URxgI7
zT8V|0&GnLbl%Z^p>`nr?DPbN1uu-yMJNlX=YARl9mPFGt<(A~5%MfXi9HUojt7I14
zF>R6`^5I3hBr*afIwb2i0(V>DPA}6t5>5<!x-03YQ#AJ^d9r74|8+{<eFjc-Nj_Zz
zrS~NccHp`t4tdblBk4H>6TOn#bgZOLvV-0u{gP>PpyPpLCoPr+Brniwdr-1J4<ZjG
z{#1rIBuS&-$go68+1e3F{mU>vD)FV#qeqgITbRSg5}!~2Y-5ttrRW@&cx{2D3CU^7
z2tARQY5<&+%-sfUPbHhFnAt%ZO9k);qzj_}aFm{-&Bj5g#~t)JNgXyo+ac+inE*IT
zpRnPfi*)lM01ithxv=Xh<x+IOP5RgKn4lxlaC*lawMpYYfi`#P<2Rt@n6%FbpojFs
z4m5g7#q{*?l2!^J>Mc#B9iNYMJzWsTrLWOa#8+BRai$Z}U39qEPnuZ^&R?4KE3}-H
zX3?T0K>7-;@dBkj6sQT3ZmEZsU}<nK?1e~ed#Si9R9a1o=rHNWv~&uW`ab{{Aze?&
z=1A$C0B}*#p?`shmU4f9`55Wnln02FM)_edr=$rKG)s`awgFtC^h0{>CP~*;p)pyy
z+z9h2(l0&+IW4V!89Gy?N9cY}lb*FnLDQw*p8_yLx{b<&GNpT;2g#C#I>EIw(oZO?
zkS&$%fEPK^uI<pBEB(*`YR*by=n^<5o$mzrdFlE>n7APQfdYsZrHU0Gm!xC2VIfa?
zk4|CcOY>-zQXnl^01JiE-?!SJv`AWg1D%(pda7N$BDJTd*H!5mA!LfBvnY;OB7NQp
zXG*1^3t_NKYP<#A<<ehjK`Nx%Xt8un`o0%@s+6wy2+FFYKhin;YH1+d_cc;pA`D%Z
zE|x%Nt@NiY5UG=zU#95M4XKzelX_`bA4D6ZZnOw!l9s8^*es2rQjc5GCRDT7wMajR
zhik3Uiuq`4lNOA_wRUOxWBei=(y9u0cw71mt?KSbAJD$>uC#)dRrjQVH-YPvPB{)o
zyQI<0;O<M~uoJM^bxZGbz+jJbzXyQ5(#G4+)+b$_1rz<!UM>(1q|2FbctHBYG>}2*
zBl=|0L+MA9ksXpIP#x~DbduH}Bhnf4Y9E!pb_RAINtd*Odo0!ZqHj$4(M~juOBsV`
zoREgs!$aE>>Gce-lhUPQu=`YcF8~G|WHSaq4#?bT<>x3n<N((W$~a5lx06gmF~&o(
z?<ox9EL%-m2p8D_dXF5I>8V25RkoCBblqg{?}5%EvJ6iEj>&$f%%+DdayPv2lr^LQ
z?q!obcNeYRvhG>%#z$6=g4W}*BLkQcUs=T*08hv=DE;pzYjl8af7u<nNKeXk+=Ph$
z*)T<c0%eZ$77mix)2=yK=Cu`oFxd_|Nf9nPxC#~`WC4_gh?L!&gCRx9{-CHtw9Iy#
zK1LNI`};85kClDp0}>~j8xL*qvfcFhJ|(N{f=>yu7)shE%Dy3zB=ZYIU$SiJOBj8M
ztdFuTr)6j4(48uqJqKQ-$<|ZyCSA5^8bmT=@6a`uDJwnzXR>7fBw%D`WZP^r(3&mV
zKxb8QWN}oxnkzHi2Joz`@O5ZACtFQXjq|b$L<{UL$mBO6a#41lDg-XcUf&IoJXxm?
zNWN@ZG;jqnZ(3dz%EstHUL>=p<o0FRUlfD7BC{KXGgoE5(b=V9nPwkF)JkN}NPsAn
zEuMkVm&q2<DS~p@cQ?>iA)ER?IDAbu_6){UC2K2%iE3HB9Y~F=NQJ)ZvU%UZnOa%g
zJ1|%$+hK*|4cX%Zuv9M_qdJ8K*?Sa|xhd=MhJ{9%n37{nvg;SA+`3ujM!;LL@)zJm
zi>!_+Q(I-<QhK>Vw(b+)Z_7s0p!AOHw}oiDD~ogk{+{e}N@R7)B=pejl7-Pj<i6~E
zx-7e8o2lxjN4A)OVfV_qKZZ!3EL;SxU$)#6A`fJti=UnHo!x*e<POvf%KYd;d?@pr
z1vNvmcp(~xWhXxYa76Zy;&P+14HVpXB-=6_&ODZ#q3Vz^*++}u_PDI^E4VfxvwDF%
zkp)%2(xlA8Z`q8g^KBa`T76Kiv%^@N<d<kAbV&Zm0>GW+_jA$bBDY@xEr;a`>6ntM
zeEc9dH@WqFNFI@&_!7#F$`h#+)m=VT4UuE==re$O$ivzo;wiuIHUM7oAqrY~%RfxP
zP<-TBF(Aj~Q*E?v^_4Se@qa?T>=H)iCs$AzrN2DkADBNW&zgae1<3!The)72_fwD{
z`IH3o1<QNr09J@RlnMw#<vS^p8YcgZ;^E=)dCR~>$p2}CWTd=}5*1PMssY%GmhTGy
zAV%(DvVq3RCj+1+PX5F9K*Y<J)9dq;e7*$kC&)c%C!Q#83Wd@ndFTX2kt`p`1(zbf
z5DRiz&dq}ERQVryu#_h6qMc8=Jecmg47rkS?M(T;8Q`+ypHa2x8TpfZkZifreJVrF
zk%x2wkt_e81D4Lp-6_LyPQK`Cm_ILH`3*!b$ma(Fe^I`WqWPEP6ZDOlJUN@Z&zEP=
zRaqpT>I-Ks%gYRCydu9$!I-P^gGK;~<vBs<E0ND^Kwqic=z_j7`L3oZc*vK_w??9~
zLVlzemafSY95KR5`Fh&1RmsDT!cw)|iN2RrBmX@B!0YnTR*+hGW+4D|a_t1n-;jS!
z$9C%FJ|l3uLH_rbnCF}Fwy79Pquj^>yh*;3cHqtOf4@cFEqNWSlWi^XTUP;Wl?PA`
zr%nFHYf#!Q|B7}_9daeDu5QcKqww&Kd{Yc2_^y28r!aU=-th^%=#;-qIf*WL=t+?K
z@?R+O&@Ep;aj_mb|G!&IzL~y%(I+45hZp_wyHwHhK+dA-+yR^XSGtl0<@4!v@=%_U
z4QGbrFFgxw!}7aZ!HvkxRC7BjUrO7sNAe|9^6^;CodVa!<j;;k+qityw~(BW*LuOH
zC-Pys-zVi47eeP#d5j!52gT8u(0M?SNBd1j#j|uF9#q)EveD|K*y;rKkYXY2Nu3q7
zFM@MX4DN-A!-`+%1@Ef3L^)qK1+xZ?M--pZO5~{Ge{%qLSIpl5^T!ke?GW)$c&<aE
zr(()>*!5DZrX;bqLjN9!kHT>}{5`IiMHO);6n-|kJNy(4RIlT&c!lzfCl&kI&>f)I
zNj2bsir|mY7^HY55W0gEpB=`SLKHvIXR|^T&r<bFm||-pxNrq`5lDohiQ<QmiZ-g)
zic-X~U?Ey@l-AiXidPT7ZmhzG7OHWIZ}qgviC3K0VA!V=n-`-qL6J-Gh(yI3MUY8S
zR273uRy5GRa!pZqzXdg?71KlETB>3{J$=#??{=auT`^AryBUhI{V<rR_+dM^EX8-U
zi#wxOM=7gp#h+9do}=)42e@2?<iBsfo>jQHLG+wrfJ~fM<j{`mf})MWwHFl&e8F8(
z^iol0p5iIhO64oow15;S>?q4ysOWwX9u_IiQfTM0;wy@{Ur~6_qxY)9Z~!7DiqR2R
zC{?U?L1USsfRfYYig^um44^{M{3Q_A6uD<%uu`G!#_v?6&|d^st>|A2u14_-{V>-R
zU(tr3RxvXbj@Bs_(WQ4o;VD30y+Ue-z6M1w?Zj^?Y_vaaRLt3r#wJBC1*V!67cIcu
zQtVoU$!k$?lHi4{Rgtn0zO^a#zW{CRitVicb}0O5+j?8^8y%RzXIyA|a#!&SCEo5S
zzMFzkbSh@tg0?QjX)2PsuV|tor*4IW(n>uF%XN@m#ak5J?o+%;ziYo@HWwBiC?-5G
zvH^wZb7&c~Db`Zd>Y-w737i^Itos&-Va2b7K#V9JCBp8gBGnGgJW?#88~(9k73F2e
z6axz&GOqC7hsFtoU<<r>qR8J1rIU&U#SnR__=f_P4$7+c;OGIRVi$;$GVs50X=Pau
z>^UoKn|}j!QO?qU999M`1#wl%X~XEId^QsfA5q5BA&R5Q0V-2)R~FLQ&|}IJs#^6>
zDriUTsZ6BRzL)Y_e~5T1kI?(eM_Enlx8q8mSK+9yvV-1cCzQ=6AmXPyN{7e&m8)%Z
z$nvDJw+=D^${kd=5~!>#hZjLgQy{zuR?gjm#t>x_g+@b_Hy@%eOxZ;lvv6e#tw|%4
ze*Z#Sq*A;La}lL1rvPiT@?8q_#3*I-xQkU@`vmYfW!E;i7OzyQK~5=amr!*_g7Ux#
zSV~r|Tmm&I%9|epaat+<2#u-Amq=-v@)N%ev!=dodwxFvS<1JwK+Y%^hCpey^1T>%
zk)!<MT>x^G3wL8K&MIT+0}tnv*C=9tUfD_&TNjj{J_FoEWv4rabV+%3AsX|PQFPzs
zD_2m-Z-H`qI&g(beg@{LNV)zrruni`PE{FKly)}Sx?EMhd<bl@a>Wk-mMB-#>6TLE
z2D+)slplQok#eOkT^<!mHtmnEDckA9a;0+VKJ-;7$7v~DtvnkI?`xFY6f|B}R?<VS
zR;j0hlXc3%<><SiymtWbdZmEgMh(i9Wwa)}seFraU5(0>6v1m!uDJ`DX65{an6+EV
zWq#1sqCD#cM5}Tg3zBWhsd*4-SN`w?8atHtXTkh!<zp)EyQBO$7=4{epR<tcQtH3P
zblq2;r1|YuZa)FiqjcR3(yOfeeyZQV%TpKH5^8{asEk?)`$Nh#`RE;1ULC{`N0c8@
zW$UPNFV&qrQog(&S|2Orb09LNoc9=HTp3S`=m{mm2U?yeqo<>BQkfqN!%vkT2myCc
zEx!(t1FDm=F^P_<%{0#kRl=7sHBPE*TP%QwRO7VEaaM`zz`3XdO;B@K6}BG;SJh`P
z0q>@|_ZAwDsP+VaJE|IyVBGGi<OXoZR7+?T?4c^4)snwzGzfN2s)k<x2~aKe1PN4a
zqTOJSO1lHD1*@zSvItQHtfF^DsA`ZNW?`!5w}T5;Ra2Q?gsR04<|9>d$_7TM;<|u{
zR$ZhuTa0S^HuS}+cBf(#ajGRx(HF1Enu@+ts?3{kCP5W(5F}Cc>25S8sZKB<nXF>X
zgNG@q-tRz8t7h$|Pfew&vVQ}crdmj)Q|YSF8PJxYD&7SyQ&mEhYFVlyw6Z^=VmX0i
zt3J(wNRH|#3xmm3ojV2-XH}WBM?0swO0U@Ss@of3{({PxVr~~z7FtVOQZ>+XIZu^J
z%d0}wIG+MzMXIBrXuYhG(}MYm>ia*T^s1`pci@XvRgUN@QN<Xcrc^aSS^P59x3rwB
zP%Yp><eI93LOYeJPbmddrOGS;sa8G8g^3!~cG}BcSN-@DW2sef7r^a0)k6xL+)zys
zVl1|L)tSXWG^p}vg@04!L;3ec)vogxc9UxNpXh5*l~c_{tIE|3(yr>g0(^%m>lZk4
zTlLZ?MDD1rQ*QmP>ipO6_nxXY73Motzf<tJOZC;)P<CInvmJfis^#hE>roBR0DEn!
zWliYpQ*D@vQS_@`?tsz<D(jc<Z9rwEGmwL-DRc!tRNa0X+>mNnGyuaYhZ2wx)$3<K
zMpebF@ad82Hf?VntK<}#9a9;*02o(&Qx2UIsx1`9c%sT#3DuLT%~IHVs<Qb}?CpS>
zL2E@v_4HE^J*fVSLdwqSeN=AXqJEC1^sxF3T0Xm~zoBT1oBF_4uyjOSx(ei&x~dug
z5B1GAAmXVm_!%NT>NhFve_S1V4I;kk4h6Uq>LowJf}cA4CM5mUO4~}bo>b3U0uur1
z@9FXiR4?8Dzk}2X6zdOG`_2MBM17UQY@zDcDY6x&cJcuiu6Ch2CPIB_5|WYX*cE_B
zsi*XVM61WDF~S)2g&6e3s`>Ozj#KZ}Kv}%H>reEZQuoBsLoh-8H*GKy)p379Tavnr
ziei%0)yep^Q`DOlz?swPDRix;s@GW2n5Itn72{1;3x5Tdq1MuiC{w+20J^i(mnq|Y
zM%`HhN3+$XEfC33fA|Fex#|iEvY%DgQfT&^ddF-!I(AWg!vNqVbv3OO^VI)PA#%Rj
zycVQDJ%bJ1g=&v9a7F6WOHg`Q-5m!<uc*Usfm~I;TMUt6^>?(ADp60;JFZk+PJz5K
z_3?I)a&;aL@Cx-xIx%-meU1XtmFg>>Qedn~{jU{6t5(mZkYkP7S^%Zj)eieGU$yEd
z5dhYyw?%+!P`iBq?xuP+RcAG-jY+^Ysq;%fn$=h7ad%4{LG@oP>M4yd(W)MN4w7xi
zse!w#Hc-jp9d!d8GQO*xIF3eJzuLSQx*w=_Q><e^oiQEwA$7+p$PBCRz5$sL_22aU
z;!$;Y8!SCi|3jZ-d92Q!4{ky|-3q%;)GKKXGpV+$0^oq=LprJ8sL{OxEeADsZJ1vt
zjbZ}ikmk}BD09~ACJ#Mr8a9=|cxgH)Q{t_8Oc$b$rjrgH9oK9wg2TR=Pxheigyw-A
zI6qDMI{^A?UZ<Hosqvf*$pB3P1<M09GFNaxnm=iW8?2c_N037_S7|E4G%M-42-mR6
z;C+N<t`C$&YHaV*S|&<U)C)FR<3rDzIE^w8z<7;Y9{Nsc-lO1gg2tIn*d}Vu(L5z-
zBHo0hWX<bTZ<C@4sD{XCjU)$vRLvPJ;Axs?W6_tcnfpI*8Jd!n5Xsd1PO-u)&0H$C
zJEN(v-Gx)x8sjS1J*(lXA$mdMR|oE*#`_zPOE}1k#yriIzrf{d8hfF%K$GzgCZSL>
zMnR||&6>}k^s=V+2_&y*UZiTys~T7O_)@XvTgu{>X!g)*wp0_p7k0}uKdu9yT=R;n
z4KfuP`!AvUnx=>f<tjBw3%DwcpdNkInh*Z~zE)Fr3Zz++Lu=|=8uwWkeTzn-hPGDC
z@`D&!o8}Lya%$In*A4Er#<&%IcQm|KNZ!>j$isV@7&cUQYP9tEk}gfZir#<sH9yjF
zqg%7(C=k7x;}qoY)BNTMhx;|Yw8DR&*+p|XplPS08H1WE%40v&gjPc7kY<ZBTpQN>
z&l}u`MnEg<QH|#w%*<oWFLcL^Y5p34mT}E9^tzwWETuZTCz^SD`VQ8l=CmVpKh;be
z0CCX%Nz1eY+OH`f;i#>)0Dn*$`Y(V^TDBt^4{2Td;Dxicq6bP{v=w{d{bB8Gy2@O&
zZDEjf(|W!Fa!gy!h8LdNb(2u-r9J!#2I#G|r}H#E+KVn|v>n&ZrC74BHkXPJ{Ixsi
z3rQ!nQ|KKTpsf}|cc6CnGV}#$dHDbaYnRe7z7Xxl6u1o4cDLf!4%7bd3A99LTPW@t
zsntA$NR;+8rNg7Oi#GrsqdmI}=3})Bp2F=oZTBu%h_`7)2~cxN`<4ULBxry55Qs#r
zn;q07Y3Hs6NzvN-qVcpgzzbZew)GpRNz=aN0j25MbF>A@)W%R0DN7sF058sHGYg<B
zTg%FWNRIZ$WZ-hOfA@krtKCKR&TD0qCc2=tjkjRhE^1$(g0)N9pq20~PaDmHZ~59L
zC-fC)e^$c8Rc+d*n2TcVvU2p5Xs^<pUaIw@Kt`E%8a@0fv^^I9xTbw_7k!o5+(z`(
zXrmQ?U)PGM>ZexQKu3(~w5MrXbwhi^Rt{i;_OolSdsDkT2%U}EiyWxArET~CeJxtS
zHyBK-cJH%5v}q$KKG&|@Pyj%OcGn^RZfouSh2&kWoa*K7Y3I#_!A@-^{m+Cht)c^7
z+}CcPWqY@FZy`vJHu4Du(X0JoC*6O2+8LB)8qm&afYL$jsamLcsQuCeHA7m>dgvb3
zp16y?5$yxo<~-6~pw!i4?Qtb^k7-9gg2=d5au!-9w155t-A}cCrI2*cefi&pRd<eJ
zJC3^V74ZI`?jH&|JL!J(r^KwYj`t=+U38nmK@RI=BM^1fEue6Wo9@qKh`Q^Z3x@7v
zx?(Dl^w90p!$VJ9L_S2kbVt4c@z(kG1MZ{SLiw=cy7Fd-_~~lW(CDu_NcDLqb$;~Q
z2k3U4Mq{Av_t)wE3)WSg03t+p;0j2n?qC>5xb8AVd?IvJ^{^YM>-ECqN9o?(1oP24
z*Cwcm(JfelzBpaNax}*4JYIsqQ@SsBXiU)6Q%z~2?k_BH?UHm$`d~0cH%V{0)4H9c
zELGP<i%MIXZkVc$(slMUUs<{nJ22~KbZ>qIHQBoBOEAGXx+W6I)&08+__MlgWcQq|
zH4Gk}*Da+K)CC=%s(vo&m=qVhq>GsXpYn9o$?z#(x0+TR1-chbKy{&RNiGZ(>FfmP
zyKK|>(MixNy4eVz+7;{em%{H7-P(^~uvE930Z+?x{S<X8*S%i`H5Iy$c=TP<B~p^D
zQny42pQ?1{>Evm(Zk)=XYjl57-1WMyZ!>h(>MCgcSf{JG1CblLcm4raudCO=nFie#
zS7{@5Q@8OmIMt~8Q3mr(x_`a~Y1Wle5p0Vti5?iOx*L?XY|~A=jlOo>70Qrw=o;ze
zbX&Kz0i(a88(xRLySklz+INr+cy}E<?ADb;qpwG&7{nlYb(7c8*r#iG6Qp1FBgF+C
z=z`b7?Li%*8}=URl=M0o((U~ceWSXmlvjGB%dNoRAL|xSRAWr%M6Z)^ot7TN6S~#w
z;ouXUfnt=Cx)6#sKh+i5=&|9TFQZ!h1NswR!@Q$DDh7yy`mgC0bJD-+3eiLQfmvvD
z*6*gm1{ZxxI?Nx|FZDs6tKRe@ym!+_Ji>5~=oipJ_o!a`B{+BeZ~4F-)32a3wuj!u
z2%M+>4F<;IrC({Z!LGM{F1;3f^bctLd0g+92)}*x=lj5&(2H82%}>9aer12XPbRdT
z)b~&dH$eY=HQ<5z_sanY(wCUwMX)~aS?CVYCmn=HsQ$%40K)Xs9)m>ci>N#=O8@I;
zP#vvrpHE-$kI|3)1U6Rx*+)<lr>~)hP`v(i`ms;xKYSJD6ZGnP;F9zw>EV^EKbi)T
zqWAq7qfghb34q-U{R>;+Os3wQcIjFA3y<N&8GY|3Fqo}RDo0<AzK6E=x%vf%pzN$Z
zA(z6D=k(JlZggIMSORSq^qlYD=|#QvFF12a|0o=NdHN*<P@1o|QAI+5zWFam7V3Xv
zfE4K)%3$KM{zU>@(eHc)@T>Z-=n5*<AM*t%(YHQ?WT}1{AChJItXya**MC|KfUQFR
z*J=26O|POCU#0%THJG+4{miM5sn#$19$byyn`ZC2{>V-EU8_Gsi_$v%;9-y(`k!de
zU$5_Mgrx?33Jc0^>hDH@Yt%oWdeJ8Rk+m3hv;Iw53*XY?1PN{!{iP6CXtn7T0(7?N
z?U_*1u5Y5-p+mp@DK3cH`e_s@xud`T5=8Fm5p%<vLx1;MNOtP~%mvq_7y4sp_x1l<
zfx&d^FD`{-k3NMK9ld(5APlKbzu;ZC-LFr44+bCT_YQ*_(Cezf4eD)av|4$nFU|*I
zNZ-~4hllkC=7Nmqcl5#hsD2>>2FLV+RKYv0_oX$!gno4_$P+y$1STf+i>dDAsebDM
zD0MJ|d!X@v;YmAmIvUn3fQJVSg>S$$CqoN8m<}0o=?IszA=<VDe!Cc!IzsfYp=%ms
zTn!DlFznn6os?QUV%X3K#8JZy4RpI3BD+D388&VKz{9Zj2dMEh{8|SOy$n|=_U&!x
zErByWhE2OMh~tK7u^6DQ;TcMWo-laRYsAmc;|L4>2KftAb8*t3ppvZs!#i(5CfIO=
zuCg%0ZZR6e4fALf8)2B40o{>?FnX9o8DgpCDcT_Q0Esb#(_=2yP({J=IK$KjFcEKP
zrX=wx!?E2U35GTq{7p2Z(e0aL_$Cu>CmZZ$QpIwLVH17b=d@u7eMltLaBu>mX@+A|
z9+hs`O8dqPL!JnYnTD^85Xmys%|_!H!zJ46XB%9EXv{JE*$TV4hJqi_c-HU&Z6?nd
zJX+z?dBc@xSh!%=Nx}V#hMAN#y<`x6M6cF7!>|8CYrbK2Ak-8X!Ya^NXgDoLW0B!=
ziZfp}{Q3_3zGCpEa+0ftn$I9oZ2042C@nF}cnC*J4Zkxm&@ux<50P@i3&8+X7#g!N
z&({obQjki+^0jcS${^bd*QyQw`~!fk#vr3O=yk)li=d{~fGZa_m!aGfc5fKgivg@R
zJf+hY4Td`rz~3~y&4Z(jhFzP`*J@zUhOga_L$Ra|gX{?UZW}&W55OIRA8owu8Wv24
zg?omNY5mt}VCpflF2j|nAop#C6&i>>Fl<kQ!-EDDUHK0U`zh!>WOzFV_))_@9x(C9
z@RZ`cj}3DvB{OE2O6JE69A}7381_-I;1k2eAoNWdoWBEkYOtecwuA97P00b{t5hB3
zX#DUI$U)<Vr2se?ZI?PRrb9-?d3fP$w7Uu7VtncVrH7527vZq0(L(zQH{<HhF|;Gb
z=O~kW)HoIUbvt+C70NLjGrEjHn}_i*6^?is#e6h+8M#z#<Zb+gE(jmvZyg}VjgM>5
z=xZGL6IxCf-?7cac>RpK<iPtI3)nDm(wNc(5@39ph8AetOG)Y=<I^M<3^sl@9rzIA
z+*_~|YK#~HF3fmu4I0CZ@9YDKFe<jAG13_I-}b_|Ob;&F*qn$NjWK?G4fbM<i8Ig`
zXUtLApgZ2^$ihHR8Gri`B*ExAAD$)}ExSRIjF;&EX|nMRN01cbI0rtRHm>jkKGk@c
ziN-YJ99rt78wFQjKEs%P8hx3@;?K~RWqkG=`py{pM}W&VuC<33ImWel;Bt+;pQz^I
ztWhKc;)0Q*gu#o(eSf3#l2I-|W1caDW+vbGmkUN;VAN3YYoYN3ZI_FTwLhcpva#O{
zgScW$On}H$V+7TR6dS#tLZrmF_Ir3yYV=)=k(C+WZ2?zqoJrN&6~=k*(23P+#^m>b
zuQXb~+Ep3n&xDKB#^?UR4^(5^9}MogF>oOewZ>wq%BnL46+q1mW9v<jdSkr_1{;je
z9z)+v<N8o&X*5=s!hDl)<Q_ztjjMh^-!0>FUtlg;jGU_wX*Fui5V5rx3tG_GZsby?
zqr>Q)1B17XCVF+;Gv?9yv(vcuU5IoUqh_P;zA>8u#NEbP+QIY~7gPGN*C@LKrF}-$
zYKZh3*@c*k2gd8yzzrDVcYzx;GQNT2L*v^EpmWH$&IRycn{mb8=o~Tb?8OX?8V3@f
z=8<u1CPW__*N~@UMjr|~j~k~ihvbCu+f*ohVw^+!w@Kp?EhL{B_tWav!Q?m%jR#E3
z7&JPX%#<NHXetkdYA2J|t59~xWa)zzXOoLFyg)gIgELwWn`CD|TuoPhge5l<BN&Jy
zrhE$29yR4SLyfyBj>;8|nVP5w$HVmN5Da>nT8_Yymuc<+z`af1I04{eIy(m4$4$x+
z{4l<z4l!^iOr;Z$^f$eI2Yn|^PAfqIOy_L0G7mKErLAR<X>ATjuxS>(qC-qGze8WB
z$t4K}!%W_kkqtLJOH&$Qa-&UXr0Mc$G)9?tS1^~+roSk^6l3c81|-(BEeTrUOw%<G
zi8mES0+475;lXZ_>98LRC7TX~Q_wBNB%TAA)236;pflCPEP$tJrWbZ#gz2W$fe^_s
zeM<N<raUhIvrVsrV}f!_2d+c%oXLf@kLOME^5EJ9)0S7zchQvdBDhPYkYB*%ndZ|R
z=9@mEAZ&pt^c?yMO`Xrt`>)6}l>!)-O+i~hu9#k?x~QwBt@K<kHaXGhixSghAncZ!
zzUT%iGZi+$Zn-Iv7WfsWtXy!{OrccjQfXT90&rEP+b@Dto35Gxs4-QuVE4M|_yD+C
zQ#;+1b*Ar-0khfNFd2jptv88wKwE?9efng{O;dF&WExGb%R!n<^LE0uW>aPc$Ssox
z?NVAymuMT;YI?!|pv^Q#0n%>z+!a&VVH%)h<ZTmUJIEc=);|HbYYL~F@ja6><s>^z
zuPHFwwl0&3272Fg;RA?vo2u%-^_cWq!S$L<r{GhcshB>R-EW#o+tvprmI7qJbcvoY
zgQl@n81_Sx`$9+#nGPMsTnwAo6s8(66;du`)D*G_b|0BOvIp+5=@t6)$CydD5hEM7
zna-?1=Y(mG1Ztj`d{e+pn&wfw^{Ht;l}R|5Tkk>5LG$`b0G-TB6F?4`+bQzkY;LlL
zq>K5E2;5<_*KK&=YW|(_Gj8S(+VvhW|4I+GqvmaNFv{IrM#VJ8%&jBfJj^ybszUWN
zYlfl5%iQb=QE#&kC6s;4Tce=#xH)_-)cBgWQpECvxtf-Ie&&997Wtdw{)Oa8^O!rh
z0P`XW^aPp@IiNAfeEAvRg3Tvs<rZRoo9@j}bAk*aVP=2IsD_&dY#SgGVg6w%lt!A<
zcffp<d0Hwuqs?|*P#R;tM90};%{jD`i8CjU0T6F?-H*OR^Y#+}B$<zH#>^(0FH%@9
z#r*p*%;9OXuQx<e&0oHW0j8N3hrmL*`PC9|8RltkU=p&-nU3`SJ7fO(ANZDS-pK<n
z$9#oKT64{+Cg9JRH$Q{M^JbUxKwL1-EQ0xq=Cn2FyJWscsp~xR*A#9lG`~X$!y@xz
zT1s3tTPQ(!#oX)-?y6ZwRb9pASgOP*F;6an+ok5&A_}dRncw;WLn}AG76g2SdD#bW
z@tV2+GXN{i59vOrG9P&g6V>J!cY&`lE2;pvZtg6`cx%lkNV3j+{0+Ev!<?=Fyxu&6
z>T4U!Dq3aTG)Jw1NTb=x1=nPLB^Sz?%~5LlV$m)0_GM^oF>e}&(pGc)&+x6y%n?AQ
z!@O`R)Z8{_>;t)HPL6`^PV?Prc+qA4?lMMy-~0=0Tf5E2e4(YsoJDEJUi03C;QGun
znt|&#drbx4f%ym8y$+aX`N8c$^WJtSvkjX)vLQ2Kw$f39QS-O7z<6ZVEdu_r`89e>
zkC|it#BVTee(NN3PngXM0eoUMP>J=V`JG*G^r?9--J1>;yW1d+mcM7g;6Y0VrT?5P
zvEvXqWO3aNL(Z0}e__GJ;_=_HFq>tw3YNSq_gf+3ZDIcc86V3qr6!MCe$Iz^U(3e1
zQ0i|9qKxcG%Lm=S2Uvdl6S@N}Up_)#kY(x@kPNn5qXcD$<w6#8hFa!+g~l+;EXpv3
zTci}IiLeaa0~cv|pQ>!5EVj}}D2=xGbfY!K!l#tXY0FK@+oxJqPX!{~vZxJ%$*}m)
zv5QQLmiE$FmY_gP!WqlG7hyizBKjDTIhND2p)}X>uoHtgYdJ&#v2&Igdm(b(;!h<q
z7c7tY5V>dxL0Hf3lEuq58=`rZI*P*PTb9!Lroi$7Z8{1q`|0>Zk>wRyid?q*xeIEp
zSbm{E_*Kh(vRiBkOF>_WrQZecQcG$q`pPVyI>BzarQlVluCN@YyzVv2Pg4M>wERP<
zlqyRtIa+PmHc9c98jBs3&t12~UPWiEML-e2I!gv6QEpiHZ=kQ<VxY}VgC&oS@7=Uq
z9)e_}g+~G2Tb38TfWa0^aV;8KEvtV7pv~eLg6V3v1h~Vs4ol-JAh#{QT|(m>%Qi<i
zbJt?GpU#}!vxK{1YC0{Mw88GOyhZt;`<8YdNVg@V2aP=z4pmV0TArtx#XgHq5)AfR
zUZV2G2bRySgB!3&=EJo?3;%8WFb^#g&S)I6oN5Dn*z#{Ia3hx4wAmlEoZW-IN0xi<
z)0wl!mVaLZV$70OgYk}Al3xO1!m`a3=AT#+=?hJh7S|u)@KeiEdjK7*AASmd4_Irc
zXu{EI_b)^aTD5zDbFvEeq4ALQcPcA!w$4z(Ll^6-RBYj9y<UYu9I<ZifEP!tfg6Fd
zxm!=i0(i{2)(xT_*0$Y{@w6J~D3_Ntnxd%Q)}zya@Ud?H0f^()eJj!EYxU^{?u2z2
znfJ4Dr@(~2^|kNe_DSo$wHQl)weKwY0<C|%4-#Yzr{6x<nt2lN5bKu|wGFjdmGNi|
zv$FroRa=+shZhmnUzb8#q;+RHfKk@_6rhT>3U6UdG1i1^*p0P*M;VSdt9Lv^;;ok`
zLUhVn@iRmctdA(ZmS~+%F`*=@YaAq#t<C?#Z;)a=91GQ_t#+4TKGkYFLRqRb>t(7J
zO1Ik45-7v^)me~C>(3Ms%d&1+3^ivk7a-Zz6gtq7W38u6L#}njAmC@Mon_$8S-pRS
zYv--$G?ok2Jyy)xMXQoRotLapYcM5w)(vI=@~wq*{-D5`VWZ`5p|yc(tc$G0)1l_F
zwdGr=xnfOy9b>v`<x-hLv2`*Ek|kD6BD9rSSJOHBGV3ZjU{!AYgcj44R&R>L)mVpU
zzk1#JA_a|Wt$Qf<Q)gweVep1EI2t<Zt?yBmx54`8M@ntnw7T_xZM6RL2TU|s*U`4Q
z+1fmSNxWq>K7dGzbq766TCGevi`Zrjp)#X(YuqtNc3A(Wxan<cEJX?KSUopF*<GuG
zCib57rTdWVw08Xl^Ig`@e*oaVm7N6AZCz>i4DP=ktLsU)*lVq!g-xGz-g$V@Z~Y(L
zKo6|(T;K<+U%d{IK`WaMojkM_(_?4IdhG@*4O`b;1vg@SI|kgSb@(=PKeAq*3ix9y
z|84Y*SwDOR&Wu}+P#AN<8af+Vo>;G?(<ja+t-rMZ@zh#QTT}=8Q^Noru(!XD*>kji
zh2q<X>{n9Y)Y<;oMIbKr%#8pXw*USH`dsae(I9U2ZeldL+us<1$T9n`{(##a_Opi2
z=WQQMm%NX?bRM|l_J!*(qrUdLk|Ak3VXuFRPCxr!ve6k}pSBIY1=_zp1D!$kk6NKL
z*xpRxlo0#lR*+D8`J2!kX8%6zFT(8;D7zeC&!z`@q&=JN%_#e~D3B0s{{}6MW9$oP
zjTdX*Q3Ni|KH^(wiMPL@hvX@neWo76POy)wgVIF%hYK<KB>QLjfKRsP(LI)8{}v?`
zPTMEk2A68T;w@-Pv)^h1Nw>Eo1D9dXpf7%9+Q+?%pE=9E`y4Etv41WN%ChbMpa4~l
zebgF=<l6tAqbrZE>3ZT+b=6i;wAG!`Ru{CiMO&(S(Kc`2_kDj_rTTk>kjNtYg6#W(
z1d&7%**9btK{iAZ5!pjT68U|nf6eF2nfcC~`|dsWoS8ZI<<iP6+lfyx^BgBf6)gmF
zo&KOV<~gTn^T5q>s_%hDzEl1HNP*MNaF9YL>CYfVPH)j<QtZ@z1lT1`;-g@eI;B>@
zwKAvI2EZ(L`VkZB%nGNA^g223)J<8-3r?#4LI6(lDY8`Q^c|HhRXG_P^gL8M1ybm*
z#_8owkXonry5LNmQ(!#$>YcXy2@{u`KBYxZgOhhQhIZL$0|l5Ho$`Aja>eQ5RrFnT
zs#}dqdCf^hcVLrK=4Ck3?6jSp`xYmy3*5f$)J?0x8%}>d1rKjJEn7{`U%S(n6q&x|
z6zGe4uES~Y3iLajPCt!n(dCrW3ys@OCkeaT>8A$3+;Mu7BCS16UzwnA*J+6M*}YCn
ztN`nC%1j1WzmuKf+XGIC3jsFh<hL2l3^@f9fDAh|y$<LRrv+yz|8UP~)=tRWcPggj
z+^EyGB~X0ew2l_xV@~sZK^{6SqQK|4lYJ116Hdl<NKQJ<qOIB^rwmW@O*ttagXC@o
zCTToBjK7|Rzs`(bDUY_7vET$;+sAl@UJEXax&82BKVv2K$#2a(!0_q>nk%E5?j$$H
z8_S__kns<Fo5h{+;GLk_&!@jKUqiWWZ$|xP_~ygNh(ODiQ5Q7*3zVqxCjlPF=r2WI
z5Mxdwu23*zu@a_27{AkA;4q_N2KtUL@@B%*ql`1VAQH+LTZUE`gL?<9a0YV&yog}D
zkOO8U!#xoSQH+5wphPqFQBp6CVW-eVJY)JyNG33>^iw7?4m*yaGlkLr6v#0~(kaNK
zGV1BQoyPcvA_6BFn<?&ligBE_k*68UXue8k<X2;$nT&=33_FXlj6!&48SlIRgV~Jk
z8tCOPoYrDwxePX~?#?j|QyMRiVe<lXKI2EKkuG4=Zl*0vA!8ne=ZhFGJp@cK<NiL7
z5{3)yVoMnXH_=zdh@hBmIb)GC`YITg@51hR#_AHNUtn<P#d(qO*jDsaGGZx#UB%c$
z<%!jdTR*{W4dd?tjI5Tinj(*NjJD_DMLpw511+I0F(NLZvw^Xi!ey5kFH`)ck<nv^
z{uPFD49u&HJM^uuYm9-b=xbs)$kArT$NA7}VK5ZvYh}E<4Wx~+gKnDZj1Obc*UqSp
zhxfM_i|EDI!C);0W+x+LGe{RBGh!yD@Y{?HwD;*|9Or_2hw-NYq=zA)l;2&3isqzV
z#`*mqeT-w%fZfkH{WBB>7;P8f+91PDi|HXoj|rBB8Oy$d<Ot(8+UVY6JVkx?8HZ^`
z9c2{m0_Fq8fDr0q43}U?Ivz4|sIq>XAvEBUPB5HD0W-;X`FCJHVmwVXS9_Sb9T0V9
zc3%V8%Pd?C?EOr}9XNA<`M-?-b!BdjhJqV2Y6Y+lGWSzb-krIa!d4zkKCN0jnQu{9
zmKXEQ7eEd%Gai8Hy^)zsZzmt-5-Ke8Wrk5XwjXmn{l|wtbHj(Q6u?Zr0?|NblPj1(
z%mq}M9?W#mE+>R}PZ0F`y6JNrZoYsCXD)FAcmy+T9^8mzCQ|4!ifMQeLyKlE<HM;K
zCWDUQ#xnPP1pPRs#}bSwo_Y5w%qK9Tsh%W}IrI^jNz5)f>6^^_J_IC%8Aq$iW6b!K
z5IN3lrI7y#CdzK`#4!JHd<&=2n0XYdImr}J>B%W3lNRHrnLq4-OgeMt2`HXnK1owd
z2J<P})@3q-;=#;fUbaB}EHjCs<=M;!l-J5(ZhI1TbD6oJ5IM)((*}R@n6oQkA)mQa
z50L`qGXY>0GUs~*$=2f{=rhn+%AEBJu*;a;C1{m1KdOd)1@r4$Ks(QL{Eog#=6nju
z)-c-(0aMEqe*vHBm~AwL*E478pm&Lx^$V~Yn9HqTUS?i(g+e3q*Vn<k!aPVXx2sIQ
zP3UW8HqcYm!VGdyg-|Q=G0Kg$F+X_=-0RGW8PK@FT$cvXo6P5(AkxnCl7e}Q>HZKu
zMF(>lZH8|%<*U)^X6Dhl><&}584A73*i|5XOimEY_cI?qgs}`UT`9ai%>44da#?1>
zHxL<Rj%U(0KprsTX9H%8nMy&S3FeJ*bWSqoEd+VQY_-7B9#*yxFwQKSC!E>KitB>p
zepY)UeuD$7qb|5Wt}It?wA@)UX*27=+H)I{o~*a%OIqHnT~w;#!xGW=J$zXoO`<P=
zC3=I_gMq9X3fTm)8fiv7%zD|1&Lgac13){<>Z1fxI4d+C%m~&9-7JwTzuzDk!|I}y
zaxCjxN<qi5R#E^ok@e#>w31k1a*$-!hs!XC<E&?<<64|x$>}o^sjNy5_;iXT+ClrV
z)2zzHfJtYiz6Xs=)@C}ImBo6BK4)~6)qW3(xvW3_+f1`oQcfn1)f^3H3R#bzL92-M
zC8gYpS+i)(R>pep6I?52HHE{O3f9&Cjx4Y`-UCVl>o3aJTxN|?JhG9sz!lfRafNk}
z4qRPjy>S#W&8#Pxu-n2iP{68{HQxssZ7g3(bzEmnt;R*X!CFNXt~XgO6jo_x^;ux)
z7HerP)H_(!dtknkB|eB&7wgzMsCTnw)S`8Vwb%y99@d#nuzQykWd~-jgEi%aVfVAd
z^D&A6)=H|#7-Z#^0DFkldlMSNEElRa9AP;xhT<q|F-27$uy#BE=ol+~Kh!5!lV>0~
z$zm&D@Db~~w=sy_?9XUnvxof*)dD%QtMyRW%kEi+zJ2WRAL$NaJEqY)@&NlVz06(N
z`ZXYK>_GbZ;z9Ov6xwoU=TbDugZ(HN4tuiCzYBdYwkuUK9%8!$f_Ss<eg-dm*bQ_X
z(3h?G8kYRnUkjk;&qfU^ZZ`Idop3FXZOedNl=o;sg4s(QbbE!cSH6nQ!|Z4mh=#HQ
z=%xu{J2k<4ID1wE#v8>}QvfxZ&0GM*7`Ds%a5SF1>StI=U~fJO^+fg-8^BW7UiZ;=
zjJ=NnugBRJzXVDeyX+^peUd#D1C&$jcPLAChQ0fS1Bw~!upa=E$<CnJC!6h^h0YxI
z+-PXzviH?PB%kd=rAP(rLJEBpvOV`;XeI3FvA`~6PtkK<#vZAKWI6jl1H7nUUw$6U
z^Xwn3aOMJAZUxvy_FMPieI@&N3=CDVYnRjU)M|F#CZN@@ck|#y9eWXNYU|nU{_x@w
zyNaSg4eZ&oK`yhmav<5reqRmjE9|0!ki5ngQk1ZXy^_An*v!69uZ$M<v>4cJWq)=7
zdTs1j+G|~Bd;S3PH`v1);LJ_-YZ;UeXlGZ`OmT~SDhk{VcH1G4+w3^1Fz;ro_%LyY
zJwykbd)d#?`nQi=LbdGu?0e&24zOz#z#e43PH&ze_7bW$8fKq-A0i`c%_O|I$Nq8)
znD^ObuR>vz-M$v&0edCY2Rg>sztO?PhwQ)1Ami+D%9Kv9-={;Tlk6{&;r=6bI3+`;
z*v_B8(cK({5~J9|VRe8wbGCS(Z!c%oT=ebZd_#Ky7tVPq9of&xrmJ><BbftCSI&0&
zecU)#WgrJRzkLr$cL(R-VZeBBCbr?qdU8U(fv6W}8NJ62akdAe&ztjEEnM^A_{{_H
z<+Qg0)Q>ZA10w#M3;9q8;JADO63AgD0VRl|r&M7u=K__pgm8Xcgo|*PGw@%5A7>jy
z>yB~?sN^}6<M=2NmnMw!1!d5~IYxSLBRHuiU^kLe_Y+1D#rbJFK%+S=v^S06ypoPq
zEa%fywBk6ctneb9v+F&WNZ`CnvsNM};y2tnNt}B^3^bXeq8&*Jr>+gmW1K=dGH{%;
zEDz8pI8%-VP)y}~O|SMePCS)qo#dQ-0F6_er)bl3n)8<zU@|zL`Cv?$9Lp|{EKXGl
zV9s*hcY*nAP77twayUOyrD-mw_z7U2<7{~e1I^>?rw1>ev*7|13OGTeP{=8u4Qml+
z<@XeiEap7-6l6*`A?E;7%25u1S;kpRLFjUh4@Gq<I08C-d7d*xwLKR&VmG*Uk;8F<
zWF@DV_5f9!bq!!vb5dlGtl?DAA?R9;;Q$osIDGmg>p7A?FtSUWo3!a~;H+(;qYjrj
z${#WMMh^Qi$XwxE{SGo$Irr#7UE?Gy2U-)yLBaZF&Z<9Qsf9D2(l6IJ8@EH`2It|I
z5V^^*g=1*#oCT8*xy4C|fQb&ycs`h&oaK~n>Ehg?Fxzd8%M0l1<{aHS4bR^ljv)%%
z9?q&2;NIn!e~0;A&MVVE`Zz@taO&rHQo>|_<F^uC406mKkR0N)vEcSFr;Bo%Bb@3C
zjQ$>H34J!|K4+O56h=AAx?%SLCxuFM#yE0HhCbvxq(aqkj@^c<?U>;737|O15q$&D
zN1WA5K&Ci>>5$pYT}VIP9<EO?oN?xA=ttkn4PiiGA2*81ZC$uaz6ADuZc{e~ae(Vm
z51(AQvnb-~#(g^gt%KZ|TBy5oE2^RH!QGq(1yAlXM_|ay!ENpX%ptDmJ8-?ZGycGM
zeYmSA+w99#4MWC{Tf7lt^5+iW7{<&1Zpcc226DgNh`u21cN7;4=H5+(qaobzFL5mn
zbGu~l@CbK+Y6FgPpYef(Q0_L$f`)N-QE(=lE1-(c2(BZK>aZiZ!FGT~asP2bE1KKA
z88R{4C!Pg~<$f9f6LH*G_kkAAHO>J{689}CIZNj1)`FSB^`~!2o#5Vh9>Y%M-dq8H
z)3^n+RLtZqPJ~D{_kT-(lEeL#G9|g(`9&b-xTOx-F642SzYCJjHGB-e3%G|U3S7uN
zM#n^pxUvR-mT<4tqE*Tbt%8ST+~cXxFXy_?1hay>t{0c<JlE+DNM7U~oB*?un@G=A
z6?bkG%vW=3I?z|c{oy#gujMA0K<c=!uXn)jdhQ$U80aPL;vL{NaJ}iv9+$bVxkICo
zJLLkjE8Lw+Vel%qb^*|?aV>u6YvTI-0Ta#Km*|IW;r>k3*sa`AT4%Iz18BK$o$Hkd
z%o|+4On7*cJ4wH5JNG0dz;AKm(`Yl>!M&dYjZQ9~c8p!zf9Q12ZLZoEqTSrVEoj~4
zzDdc@UT#DRB>TADtswo}8%c0&fE%3+v_Y=t4E%&c+_$NwV3_*`1q4R8jxWHx$DLmb
z=6&v`bP#Tot9l+jJ>YKm^uK%n_s8oP+C%QdYG{me)$<`U!QIsd<|OxuA1poMzTgQm
z#hpp|yLoO~U~n&Q`F|@Zo=y)FE<7E*#P{<8=b-NZ&%FyKTzNV4E_dUl()@Oi_xU#%
zggfusk6_4y=b)sB!;{CF1?t6H{xuX2@gAoq-J2JF4;nta6R$zvmsdRnML*sxDTqJM
z_Xl7H@EEk)59A%8ha-qrsDWNEuWmgQLU?@?0yxaO90SZFyxA1XI?BsA1Vf>`lk|&3
z@CuH??MMgDkKQ0ry!typi{*Lm1c~FdY=TTY?^UW2N#gx`93sg)vl3`2yx1OKpWuDo
z3}z~CZ5~=_yiR(Jo#uskLm{2_W(qF%8D7*l3}*6V^Z~ytUiw_9pXDX|4hz{lD{T{U
zc;8%J514a2)4S-*<E^FyZ$3{;WvGR`XQ+g$h^P4opvAmr>Gv(+{oV)HN_lJ6z+gG=
zpP-OmP*u%+A0kz}t`3lD-ZKoS*YH9pk5|VN(lM8M-df5ZUgCXCS<nXF+mz<L%xnG>
z3XQzJAHlrFJ0XHX6Yotr71YejrOj0f?<^JDxAH#5W@Tm@ZwGBXuJe=y_$6-e;ul~n
zH+knBv@p5Di+ceYJ-oS9Aa{8+6!Y)px%NV_kB1-u?p59}Wt#?hZ_#nOA)bs*?u_t$
z4u<+Duha#74|pqSmodis^etSGhdjSL^o{e@XQOX|H$)rqN#2Lpk<Wa@E2B?TO!4x*
zq0sPd{!Y5D_V7P=85+*~89cQ1^FO24(E<LsZ^3ls56}(a#$P%Kw1fOgn%La=jYr_G
z2Y<x~?0WLuDZcH+k2?YH{rG13%7Q<C;UWw)fL}HRut5Glx1kWkf7AxdVE&woPva>L
z;Xg-Ph{OEOoghc}^L__R1izl5?2-J4FF>OBqeZYA&HtO0UNQVq+7`v~*U~c*$6tOO
zCgS<a)gTG{>{}SxF@6qZL5}lhQ`YAMf8a$JOyw7S1M_M8)3g{p$uA0{@6ev&|9Sz6
zr}+!J0h-QldkO|K`N6Y*oy9*hALJ~*Bny4n{INBF$>IOG0x-G!^;^L_$LD)MB#$pm
zgu#6NE;^r5!2g`m_=WtschFbF*NlN#&VQa(#ua>b`t;U$zUl;Ab6nsrd>-Sy$bX(D
zze@gNGznGl^;AVr&3~L;3pM<%dZ0D%H!la;W&Rr!A!_6|P_*m{pGgPkuJT>!=Dx<i
zMwN_B{P}fIZ{|;3fQc4<ZXpzI@;A|@tevkr53pPOd)@%+aPWVt1?}W(oj|(y{cZ5#
zHh-xcq?><^a@}|Mzf1tFpTCQk1N;KYI}Y+s#=_DNe<wxThWTqA!0i$K*vC+~$6xk4
zB=7TA(B^rRzs(;8AM)d8p*7A|q`{{Neir3tC;5(}tAX~2AG{ngQ+x&G#dZshQ2=s}
zpoi8>&H^XOuI&|kD+2aDLHhqdTm%VJOm|Qa7>Aa-U}p!s_YnBfX3|rTN`XKx!L$(=
zJS6y%ra5oHhyL)_N6>T=*TPrO{uS&639?=~4aHzVDa}(Mf{&?)=&<1Rpn|Q4R?n70
zBTVp}6F|cSr#Hgy7=ejywphWhbhE_?n&@VW7c@|mEkO`)1O6rouF#3QB*BAbj3rs%
z5QC%$yy;j#njp;#yC(&sN8#ZqLFOQsrv(EP7DyMYd;~*h1OrrFpCS0zAplIKV3`N7
zvjmeAWzP|~orZp{;A}ry=LEffp)XJHYY#N?1%r{$FA&V~1X`isIGvR%68y0gq*!pO
z7y~R3WTTLIW~m_S0qm9u>gb5YMZqSDLsSYvo&%{81lQn-R0}dx6s@iiJfu}at>EWZ
z;7pz1Jt<7o3x@IldPVR(z1yw|{^tgfYXW}?QZxy^kwLOqP`L#@wFoAuvaeO}5v{!1
z1Z$VTwOfKMhy~B=5bWOpW~X2a9n0<#toj7xwqQ>NFuMgM>t<kTxFaYjg?^8qfl6Zs
z1S`+r#~T#H)7?EJ2zUT8EJ&c_z=+^GHtgOL_`1N0`-1&xP#6^)rf={+6r@mSXI#*{
z3S>g?6$LIP1@kCm_ec==11`dpAcVGt2ZZxIV8K=Bbc_yMxCsL&<bP1OX*-C!u&E9D
z9zr)GWITlnx5KWN@R?RvIwXvWhb3>}|0rtgBkcb#n<!isjPd#j?Wf_Izi@<}+W=u~
z6i|YMPtaR5SSb7#C?UcM3gsRa9;MCx5#b2k<Bm{a4HX852^VibXSneD=O7v>d@&C&
zQNp`)ouh?fip9nV574$IR(O_5@Dqf?uL3(!=ywNwNkSv7CX<D|Mu4UWJ?X29$Akh}
zl^qvurN#FNp_2`Islv7IU=SyTU(sstltZ}fAJEgnhNVzU7v7;={u$vfAA)2E-x$Uy
zvV_M~5IHOSfI^Mg!nbz=J4d)(3+!CsTNE=mCzNl(b<PtWsDe-V!e=P~S0J2AYqUb)
zT%6RHStRtO0|dpwr3p|k5ysN(Tq<-tpoywXsJ#fqa^ZH0qE-ldPecE_FnI+uE(rg)
z1(A!w>U4-y3Y}NM{VJh5tz@c&OL~D_BlMuRcfHVsl1-O{cFNi`2>*NqeV2vJbOSdE
zuXLmDiZJ#?4C0zFi?Z5HLZzb{18o-0n*eDMUVQ`RTZLU8fV2r8GXwO7a1QO2ZVGq3
z2a$H6paZQAVP*i(I)%kNFuR2B$HJN0LT)FpyM<TM(051piZ2GyBdnoM4E72)Q<ZR^
z@TnGzrC+$y59SAi5n{>;3<`hT1({)?I14Z%!p*OM+!KDnhZpyStLMYusPGp3_78+@
z^KlWzh4bEq-h}Y@4(Lq^#kC-hgj2LTnG&|UL4CJq?h3T_h_-sb8E4V*15ns2;&s9N
zKGA~DVctc=38#YZ{i25z=sY0$<Yj2MindY&!A;an6XQWqRXXlKcTpa_TRlVzHo_-Q
zQF1Rpy+niW!?i=Ai<AlW7R4TcT_2J2=ODhKC?!z*M34OqfBi-4Z@@x;$nrBR1d7Td
zfEgspeUlRY!J+~sU_wOOMu2@-v^yW<h)6?$o};2cJ77XZ9qT~CL>Jtl7%q})Arc`<
z`5c!dQpEO#i73(dk7z}U=F@v9M$}_QD^@i3S2!9cYMBNL@uE%NK{83yu>k7HqD*@2
zI#NW7sCe+0DBcs;$3>B}i9I2TnGMlY(crHbOq%F5FTk7>J+%-%of0)qLGiSR`5PqD
zMOy~YcSaOR8SD&E>l;wW6#3E`FH6*6!c{vf^0)=CY|+_u(902ZbOI$;RKY>tIftmn
z3eh~#9@-D(i~gk_uR!Fx3hoz*c2Ipqkw{5}XT_p#D6CK->ZG!}QqhdVV3vvQeh=(&
z(O>k{fC|w*TF#vp-KUxKf+&tkY%Yqfe*lq6(UN5_Un6o_1yU=@SOxFvM2@$ghD^Qa
zpXWd>i8lTW(FW130+7q1>oI_76m`&#cSZC8g)y&+etrzhYog}4xTH;@zC-A17U`%4
zqD5q;IlooZejOgRiAJbs@Ve;lFt~j~G<QAJZ;BG>3t;V{zv%b5C5mu_!S4>yQ~!Y5
zDN@XUXqV{I9CY3h`DCKiBQjEP%UzM<eTejm_Phm{KGAar;l+TcaxK&cMR^nr84|rg
zCuxR7u8%On5z+d)=({KKTLY9)k!c9(4@6sM!oxAqt5jb9Q1o&?Ese)T#TIZUMCx}S
z^GNgwrJ$xn`zUz4Tg>+XaTb5hgim|Lv%f`apZEou%Ur~b!I0c99;Lj6t9VZ-h@1G>
zS@?TU{451b+{FX*PW2G)S_9%K_D_TQA@Lqc9eaz9ee~a76p44u2G>_yF$qOK@iDr+
z{Kc;cFv39bTXar2NWAt5^aYEVRI74SoJ~8$Q1Q?=V1|kP6X067m_gCG2ys>s1`#EG
zR0D(2;-A_99V6a<9$>NJDq2CsiHk0Q87~gnMgiUg@kjJ_N)oH+rJOA0<^m=~%pQgQ
zG4ZMijN-UBI}G}%;>EL}pC%rrrQ%7kI}P-d*pKR{Pm5JbT#|Hg6>ZPYh`TmHFH4+H
z`{T1>F6Cac#jjKJHAk#k2EAOd?Fw3sJn`R~FqnL?=naqpG0y>Rp?J$XFjyqcqZnhc
z*ry16rQ%UKLRu!COOJ86_!Q+dD#U!s&z=`gQi|Y$c!d$_m0}kvGN}^FslL8i988l?
zt=L8j`#N#t6dbJ=pXk7-FU=M!C`i#DK0$Snjp8*ywOp(UpP)Tnlemyl6wTsnCd{{r
zr42x96Mt_;-*s^oy;N_A=hNJKQ#|+sB-_O)kAvAE4y7zar?_h=40eeb6lLoXfBg;g
z?uu*fL!?*itAyD;am*|@(=Yy+qBn!$<>vr4Bz8DnMsrx)#|Ie^zquPQ_r&l0h1Pws
zsv0t*;>T&(JSJ{mf}uSW?^prX#>M=1K_<jX2bh!MkLaYtl=%K?7~Cy6+5`{xNWP?k
zUT4WGucEbAVhzBk_emr)Ko^OH(!#EiIgt*SaFc8agv>!n6$K02B@b7Ecu3Y?frh7~
zYycu&68T1uLz2un7=^clL3wu{$!&_J_)3n^ROlzk^#t*k3{wg=K=Q-^SPGPMU4&~v
zl2yZSEm+dt3A-VZiFd#}EOBk5V-QCqO^aagsN^ICs6r)?R*Wf3a`<(a2$z&lHX%a7
zp}LAlN!2d&MM+ZWO&cw7tptgYJVs@pv64hubHzz^ltD6HqIeZ15+o8C6cQ!ni{WUJ
z#O*66Bumn%tSUwF4xV?%%wrNicQlVna%lB%Lh^nk+)tIXQ~6w)MEL{8dr~6Y1<+HH
z%U?qBv?O>d&@v<*!BEJQJiir^S&|Q^&NfG~hf*TBlAZJuo|EhvK&wFVeI>3%q2xoV
znJSXFkHU*mNe!(+9c7Y3wCO09WF|u6g5=cGuyj$<L#G%kB{{Ujt&uFJL~^a<7Y+35
zBtN9%$}~tWBm(BL#E0H0jS}YfP`@U5%^f05k~XSqYL@K(3?glkG&<;eUE)QNk{gmV
z3ZLARR4s?uc8BEYnJ{=u@+vLsIwYrP_u45LTY{l=NjxtC=C&k+mR{YGeK`>6k)$O;
z@vh|UPtod?h$#}*C;3K>-=JSoKre|w$=@dE4M~pCR5mPmn(q7&$((h-yeE0F7tY+5
zY*nFeRN~0|1!xZ>%<sS*llY&6%tMLhPZ%7R{9F&v2}vZ~>ywhtj{x+MWDA`bnvz_y
zqHnjfc00`Pk@~LznzQtk>kx5~CIrLae(9&Q-8~?E_A)HEN)tx`?Ivx|f_YH-=3kI>
zm*zR>Bl;fFtvi6`C7nmhvP06xDfZ<pP36Lpk2L66^!Z9P^ced|FE50MzcjxNBtZH%
zJ@CQOJGammBF&>E%wcJEGZaFlzK^3XO!@&;0*6bZQa~c43yz>KQW{8iNwjp!bO)L-
z(!uLcjFp~uMk`MG@7L&zm;Owz_5`UU8m&a>u~ishlGH+B;$-PznzK`+zu$pEy7YfE
zFQ1VLs2DXvx=R9Pru6$kj5kaA>i0l7EB&1+h_j_TUWB0>>2BIP<Vr6+L0`ByC(Swn
z>^$iUB9MG(YZzb(q?;*HQz-SO%B>>lGc>;zOT{k&v_x9%2J@xTQxb@jNmnj_Ub(b1
z9IXoJST~$GFa13fdKaX512A||8ZZonO6jvsU{*=>R8dqd^+J7-V`h!Cq7K|zX@3bs
z>!cH}0H#5jL?>x3OG_i+X`?h{6wGVVzi2XPlJ<E)p;@Xg2eU=`5+&tYrLR{)p-uYD
zbXdA69ibwtc4^V881^mcvx6WV(zOpE*(seC3H2^1m#&55w)D5B0opCiIuCM3`ogCe
zVUIM19;ds~aXN0<EB*IN{CIuRU6hOLm%e%nFauJ@Z)golzn%u{A*ql+ho#T`1G^*A
z$_$9yleW~unfubVljs|jZlqk|18E8^?8l_zb-;Y+kV;2D$E7uLSelS_Q#No?I-k-+
zkEAXigG@=kq8W9!EJzLgJu-eh{C1Yjq0qx#SruK9eX`%$V9-U@MTv_2vh9_ydqCE*
z6--yzX?nKYWXspW?m=1P4OnoOwRwT*A#<E)0M}Etg;q3PGAr#id}Ny`K<q1%X(8h$
z`(PS8^p_o`52**pj#E-RQ1*=h*g>**%3}x1@@U!#kxl;_<gm=!3zA1<D<a|VQJL{I
zNQTOI^tF#L*$G-{hRe<h(Tb2QaZn9Wq-+(vnxkYfR74Oh8?Jzf7}<&_z{JY#z61Su
znZ^S?CCI{Q&QFxxuYpLC?6rTPmn;jl!oy>-zQ<wkxGcFG3MXViv|B$Zb5J$ODOnax
zWv6A?^n<3$<o}{|M)sAFc4Zl|I)7Z!Oj$X-q_Sk+s{nddrlKm=Y+0BD8aXnH6q32J
zZzv*mPL}&3B=ckmpTS_hEV>2e3uH`+sTRtvP!&v(ERCMcVp(tm23R8drWnqY%1RG_
zl*!ce)-RW3%IW=AAzPCL(ettpD?~5IWOQ!-qD*)eGL<sJ1(>Lk%?^OwYS|XrR@KO^
z)Bd1VR@MoHI@uqz!mgK%H9_){tgab-4YHm<w64gUD8zDA7WQ9UTb3ln$eLukO2BNE
zt-wv{nAswGlLBk4G7tLhTAPfi0_b&FTrMo#kj)*3#!cBTEL^W!h~Hyq9WvJAknEJX
z$DyxJ_G1A^zpR`RQ3JABCSVWBhVs!Gl6^u2MZ>arbP8ic_QDXZ(>+;g1;Fmh@R1`t
zf1@%3&68uYxfXOjl&xUH?zn7uK1@u=!nj~g$~q}*^hkD?4p>gfI;nnhk9_&-&~ug#
z(LA+Ro=qF5{qg`hfpb9q0-elql^<wD%S}Es53PgpTXZzTU7p(t*F5Br@1f=Ckng3t
z#Y_Gy70euxpP&%9kNgM~=K9J#6CmR!AHIT7_{$^q<2nb(pFE9=5Ga?Q1x%29`};5v
zB0re`^~3Tpx`B_#gQz0msJ!zZxE(5YraK{AzAF)zIYRz`c3e^N9tK3B<&GB)gBv5i
zM&-rv^6ML*pCEUo5KW?dHl>_T%D<%pQ>Wy~??Cai{H1yDB3<4@Z^|?B7f!)$hP>qu
z=$(~MqvSxgd@;qqa^x>i1Ta@#wh5Bw<WEqRC{O;C8g}#LRdjl|K<@3JFm<8)8XYMq
zlIQ;hjbgd*2JDu|PgAu-nf!lqpiwRtJqO7OxqxEV=jCOY81@DE4{?yJl4nuIpjzH^
z8+|qMT_@41mAkD6Se<-1l_%B9=jOxUC3znuNE+n9-$C!P+_s(8uZ?mZ9mcpKUwZ|j
zSLH5A7|b>KUP?kX$r*G!v|0XXJ3MTW8>*q$Dqr&{NSj<w+mq|^12O2kAwRVgt()>4
z32?1lK1oZ(TXNZLsCUR0MZiL*d|*0;)FprVWkBDSuew2HZ{70qlpek#Pn?3oJ@QR7
zZ`_q%qBUEu{3pt1^~o=Hf!Qy=oenY}cc&VLLHXqZzzoTIC?Gd1w^77oM1JQ@n7=1K
zKZw?S`5bzwjmpnZP1*zbwMAf#$ybiT-b1;Il-_^iaxVi+Ovn{<Y-Cb?*b_33<leMT
zn39)Vz$kVr@+pnrtWZ<j#zhfF+qnITMp{`MP{dQ*)m5>OqI_<OCuoOxP~r9j`rH+!
z1}Jzao~{SeQ!$V3d@se>U2x`*LJ<iIN^gbfFLe4SQqKd%S8<14GJcAUi_kivI8gz+
zM-?-#0XtN|{t10yiZ&{T3|G8JTjB`Cj$hzRq=HAQ*(ilC9iNC+<TRrdqiCcpZLDH@
z&?jnawSv~7m8h_?A(EsxL^1DV#W1a`QxyBs(RWO-c^`Z_u9!{N>4YMo5R$2i{AqAI
zO<|Qn;iO{kS74q}RQo{hv|^q!TuN6grdjfg;yL<!S%zXd{q&iNX&<4LrAQls!db;v
z4ie2)L~jFjjzVbz$yK<~oPAD_{TO8O6#Z1Ql&=`4U$Q_^O*K}9ik~PYQlyyE1JGiH
zS_Y94MQQ-9L8&6_Gf0*z*fVfND-`L6AaY)DeL3u2P$bWThZhwK$lpqZWW#@1c!hou
z(5e+aRC7_I*wqFTwTj1o1*ub{eFSE`Vk5n1FDb5Vguji7SC*mgio%Z~4_6iGG&5XN
z40Hp#Nx=?<NVB4oPDZsTSSz8|s#su!WShcBQ^|G3o8LhFhT^Fys&KifSV$4@c10<b
zDcn*R9|uf_VjYE8Iu+~ar|44brqBD_R;<|zk#5DWb1=|5ikH1HrXIz##ZbSiNZ$;R
zUPUd1UHcRtt%iEP!i6%a1Bz89v<4L_DhnJ^cu^Q~Sn<_3eQ{+(af(*o_Y{jh0nB~H
zhOa<I6(PSu^nv2HMHu~<;u8v4JXD1J0Wz+5oXQ|46nT%}#iZiTI~dF(#Y<MSrWD^d
zp>MbHsX1_MuX6KgDC|={mk1OW<?X+4NnDk`P_>Smax4mlg7UP}7dYnp2#&Y%cdAA7
zQLdr-EMKKlH2VFNCpM$yuZ*^U1StQYCm~Qd)()f~<))9&3RZG9z-EZjI0kZ9d6_Z+
zN0bL?E<dWYW&t`>xr!F-Van-`0VQ0yiDG~e%95wiid05AC?^}G{Fwqk(aP7#&>5qg
zngJ54JVQCkIOTH{7(u+Utq7nA%Hwp(FIjniJ-kR!en5fhW6Cs|)KZm;>4avQGLRO1
zCzVgqi{+H^%`&u3EARgX%ygw`E|_POda5bUP_BNJ_WPO2V}amiDce;*JF84t1MF<2
zsv4j<%J){Fm8%qTK+Y*^Y0H|Yoc1@aalVpy9U=wFWIBFQsC+~zfFkAR-M}tZmdC;S
z5@iJ{?q-%M&rwNknQ}RW3(A!dZ{l~WP~O33#qoeB7f@jFf>O5++>6R96M(5yE~06u
zN;!E9c59UfX`5B2WXr&;S2kUO`Af?BXW&eOa^dUfyR1AzCx)*o&(lWZnsS&jyG_b-
zIcRk&%MQVdJIYumnD0?`PeAgn@;SV$95Z{B?in!Or@WE{(0*m@E*Kn8&O8IfLFGm+
zObjXiCclT3yQ$)4MCnA+*gfSRfiQ7j*+*%OQDs^qynmo{BDcqsuTVwCLuL3nK#wcW
z6=6sd$~r0(npFOE9D2J|^Y#J7u}Ae)D(pI|F475?y(-61aQCS~4}rL-HcmlfzpBIt
zkprq=3iG?Fd?;+@rs98q)<M-+6<l*yy+=VQ57iSrkn~h>DbwSn+DTK~Ayp%7xV=@i
zlxX!)&FzPyzN%81j{F>|KrvwaRZr9IB|sH>39Ud?F+C?iD#>)n1gre13?W4IA;m5a
ztAZ#tbws5U1Lmko?2lHc>gi&%!c@&(&<j`nOOs-R>X;Cik*Z!6m{F>YbU#I_3VuN=
zMm3+Z<gqG8B|SiKswMQ&idSu*;;97HPTHs>s`!1do1_YU9N5XK$DV+GiprIi;m1_b
z6o@&l%B8vDgz8VKqe)fGdw?sGrn>VKP)@46XMvnj4P-*(w5nqh98FgZ(+2X4O8f)B
zGE}(^${S^>KBWL*mMXCn*k@IX!a=fC@vg9&qY8KrFuAJtN&lRxo4!t%r@9gkg?!cQ
zBVZP&8feBVRDD6~yCT&WH$jS3Op3XbsP2YhfTgN`o(E=`s)fo8%T?9UK&en&X>tPg
zdDRPb@aBT*nRDP?RAtiTu2f}E__{_lNkRWw)k(_D)Ttt_1Fc@QbtX()QhiMGZi6ad
zCDbpg_*4YgsLBY6FyZaGk+S4Xs@Kw?-mDs>#aD}JiiZo^s@g@Xy&I}|ljyst>iO>-
zpvssF^;;?lW&S!;PtdlzQ)OR=R<~*^WgPFQ-rfZD9@YDYV75=CpsixR%9SEF1FAHt
z1Rhqc2|?e8>K_LkuDGW%TQI=;s*mr&!%>yXO8gWLRDKK58dHtz2lhkNXH+&cuKIzN
z(G#i+su-PA70rihk5qr9Kw(N%NwrhE)k*Y)fIaFs+9)`y>uD*qS6zPw%zf(R6!tox
zK12aUSM^8Pw2^aD=h77Hq0SzH7oO^GD1Ygt7XJ?YL+UZA4e(Zfng$IY^;=XS<f{%X
zg(W}rAnhLf)xW(4X9Cm@cu)^iKVOF*J4k(y?v-G5{4(@~sK;A@d05?g3#}t+-h1%r
zs5)t!7LuXrIrO2B2=&i=n21z=N|R=k`db|a8ms=BZuL0zj+r3w>Q82)FF~C~S@}fu
zwCB)DQnQ=TN>(3u778iq2{tSpQ|Ir)kdCXP`q6hn{ZAGAO;tb1fJmBp!v+{SsWydE
zdi#|6Nt%65tCze46X|LzMP<*ZcO}EcEcIMU{GV0lZ-#!h+M70Hh3dYaFtj3dHSPL~
z)wxtfSE6>B1!k%GP0CM|sVgr-uU!4YSJ10a|NS`(o>xb$fioA>1(bujs4gFZGmc92
zJ$KM5^=$=6wfeLRG-}jwt6{!YU6l#!I(2FsNWFS36((L*pPmVkM)mC$z+6%D3c$Ro
z-bJs*YwF<@@To~1M73AV>Ru|8ZBcKhP;0AtHa%1~)W2N=xv8$BMNqp#E!YpyTWUS6
zkUG@I>8I>e>#4S&OWj9Vjoa$pWVE`~t<OO6uG)#tYxSz1<YJ(G>IO<O^s6%(VQE19
z@mo+BRPW-0Iiy}@fNR6*zc0byh`N6R+#Xerdx7~t{nO_lV`|4an!FyWzo6RTakYpZ
z?FqF#2l|uh>T@8E)aE^~JEdk(KG0bcO;yT!H80R4zfY4+$DR*pjv3MCs&Ri7l5Uzm
zs{rPq3B^gRnVuR3r5e37dI?%Sn!A+e_0`O$K$oB9frFB%ftrw~(HW$v{tDQ^ny)C7
zcSQ5=8MKaS3Kw9Yp_)lo7>v<46i|rO^md~ar}-cot$0n%{~(f}dHWRnP1Jlm46r0k
zG40HgHJho1K1K6aA(+QBLzF={uKAXNN+&e&?>Hcns+s%}GHIHED2)E3=JFuSpVF+a
zfcev!)f9nA*D%*Y@r)*fHX#|BCsxB?re?4J=Cd^W>7>+I&EHhDo2?OPftjOugOUZg
znte;5a87gE9scHNX4A=`e9gbhp-`Zyjif+kk)|O5&0<Z$Luiy}G%vu5QcVN}jLS4H
zdjYLn^RpM26`BnXpnqP&qrAWcjs5^eaZ%F|0q-j{t?p2-(!?%?Yt@?7RF6`lS$Y7_
zwVGGBP_NT0G(n+WlSEZKmo#3^w7PB7Y;Oejie@YVqE|H=55nPQO~xjeXwj^>0nt{C
z4x%$}Xwqrrd{gr-RV21+F4m%TOOx;^S{<65en9Ee7%9Hqtr?>v`yI_e+IIJ7c2h*4
zPt!^v{C>?@A@l|`fkyN>1~pAog*2pbegmDunw%JL?`!fX`ZlWJybba|^IIm!xW<*%
ztrMCL-i73(=E`*VyIb3AL~D=s7QLdJwYSUQsEhWMXTaRA9im$416l>8w_UZ}6hCs)
zY7-!GQ2RXv&wL!(f2n@QSG&&)r~I_)8p!x-%~W6*plzkwI#Am}3*8{C{5@RYVC@3>
z^mK@}codR{wKr&Ie?)uj1jteCktC2%?FKhE6Q=F`0(#-vOK-x_2<<#RoQc%_<P8#~
z<rM=uTI*OszkQ7M2<>rWwU1js;<U@ZhKYFXJ1yu-(0b6vbP}~U7Najo>*otElC=}p
zVJSsxc^Zx$Lvac$9oH_Ur|E>Y^=VwgRP6`_-P5!eo`>E^?J+a@PH9Jj&^oOZ(cPJ@
z{n#-d-kj08T|+ZN%Ps+0rnc7)Xj$5Y$?)Q=c2OwIXKR1S0W(Ltz83nq+Q|}NpVMZ%
z1d%-L=BLog*IuDQzXEL=3(P{Th(=bV{eCA}#o8<jS|!?RG+UNx-|;}JOuHkLlBwm|
z>2!|1LVKhf-1Ax|s%f~OZKEveMeV~7_+6>pG6az-?G`#gTdl32QmPtl5rr4)wVzY|
z<dXI{ML8O@T?Ih7qFodO=2dOjR*-Ajn;mewMQi>TD6QI*-Oy{(exRi1@1{0tF3{Sw
zKiOdSmbSAN2D`L!+T-5V77O7;xAr2X)$eH2gCNqQJxKHNU9F6s?OyF?6yfUAPSGZ@
zU%TQ}T&@9a1KkOO+Q~)unTNDRR53H6eQN;b@8LH9*nMp%gZ?UFRJ-q6=s(c<Q7zP%
z_L&c$@lcybRU6~lmO{WxX#JhQoYZ#y3H?V}HvK+R+D|{hcz5ecve36jw_q4dXI&`=
zmiFqJN<sGNzPb!`7u`l5^zGL@Mumw7bWi;^S?daipzd(ft&qZ-gSrL*u-$d)GH^X~
z^Q18EsoVGrh?lNO0@n`dbTP2xt@CF<(nseW1E#O;z#6ptbWR^Y(q9+-8khmP<uO1B
z)a6r<Gf3A$iLGE=&2cyrqI>!oh#c1av<w~|ap)>?Vg9J@JE{=~)m7HR(=gq8bnYr#
zx2YVW5xO!;Q%CBS9zb7|u7bX55v_aqZIBq9PZO|Xb<4g7cATy(7bIR+Pp&2Co}hUu
zQTGo;36pe8dhI9cR?r-nqD#<#9Md^YR08|BPOuR$Cv-WFK{Qo2y%*-wbU(_WaZ<Nw
zE6`5qo_`Y9r*#~P)~D;%hrpRLx;YeQ$k6Sj<yEFGzXIx6x-d%apVeLJ0yA63IR<8q
z?!_f&<?1w)C_SgU{3X24)2SS^sLj`%q;n7jI<YrE3w4jtGPX!pe*}ufx@s!+D$(6~
z60K6*0RzmJ>As*yak;LO$}K8%FTM|j^STezFmXY*iemQ{bvx(|tkk_e1j#Dh49Xx>
z>wcjx{?_S!j0Ce@_t6Ua?}SUbwVh}-=z4mge_3Z82eVOEOm)6jbYJPvcU4#W9MG=m
z<UgaYNw?|{>^AGhA~5<ET^<XqR^8S)P-xR_Jqr)7>waOuryIJz*TU{i-Q4*=Y1h3k
zf%+|7MiBZsbWbm)L_()7oX!Du>0*_*G`DpN{)I-jE{PV?cXV(4024jBx5?4Fx@Y5H
zsaJQ6vig0xML$BMU*|?~;{o0ESV#`)*laL|bfR{QWmxwiy>Lf#U($4UPj`&A;P-V;
z`9Ne;7ydl0KOg8?=0avnxA!{qAL`uxf#|p{gI3rRy7hD*Zc<l5pI?2X+s;7Wl&<_H
zuy^aTL}2dGtG8fi`}8T4BXQCHOJ63~uaD>fIiT0S52mX=k_@`(mx-ZwP@lRI{<`Zw
zq4>vA5B>FUa6R>V=xO%S-&_y0LwdJvFunDkQmEEPAO3bw!9O@`p7S>@ZGhfZgJA^f
zd6dx((vMTgX|Ue745J9q|GOTjhxLXjw2tUCXF!hXUzrY=P`%4<&<oR-nxPP`4>|!$
z5&BIV(HE(oM^#r*`XEw|)@#3nGco%2DK{FczxpQn;`EmtgZSCv^*^@(CPDuS#dZ?)
zsf`d#(*I7?p~?D}|3zPlK9%mTWBTuD@;t6LWy8b?z4!+>ld8W=C+1J-_tVntw7!g@
z$m#mH4z$kbBgyRy{U<nCHZxP7kp`43{frl(a8{o<mv$Z5`l$Z_El2;sPteHK`%t{<
zoIaDbM+N#<)<UFE?>!Duq~9<dXr=nEsIan3KPM9+<@$s^C|uC5qZ+J>`h67AtJEK&
zjZ}?(2gRvs^~-6}uG61+1LT@MK@Vn=-Xoble$uQD%K%!7K7r1EwCdla=ti5~gHC^4
z*T+!#`VGCFQWrP%l^W=`>*HvjeM|oYO>iCh8J|F;Q(t8O>C*pJ2$9?Rhg8(it!Gf2
z@Q%Kx41GQNRx0?ptM_V!dapiPO<%6)(>GJzwO=1U0`mj<3CisZ>hIHFhV*KRYz^zT
zy#<&NeRT~a@9Dqj1oOVWTMd{|{d2Ua9oOg5ygs2%Duu|T{se`q9_eSF1#?PYo&km3
zhL@ayxyLYAf<9-1&tdrF*l)N%Z=eH)IUhpN)sReI6mv6l&|Bu9A&BM{cf&NQk@GNU
zXp`q@`0htA4;kKG3*v1ErsMEFhWnIz^EJG794LN<i&tRK-;jO|eE|kR1S|y_ww6L9
z$WXNe(7}dbn%)mP3_EDPJ7QRP92!RrLOL=SYAB-W&@jV=cKqlOh8HNJ7HNo~RCJVK
zFGUbz3^B(sv{=K^E|56GA$px97<_5tmuPs4HWo>S?9V`w4GTk{kYdQbi`EH4`nzbQ
z8rBQ~GtJ=WrWN{0LzD{KQwEs|GN%n|=vhfOyqOBnGlrC2h-Mh%Luj2f%(#USW*c6o
zk9p)6!sbIV*I@e=<ecIBF);HCqgr^8Z#YL^i!Ly%_yo{}hCLK0FEV`h3;K!;O?NPs
z62pjt35`-i487vZ4EsMvXSrc*2Q(@Sx?eD~^M+m;#RWtDXF#hmcu;Dn+VB_EhtwD@
zP-#-F;du*Mb%q)x)awmvD3Eu_&~*;X27^Ek^~;7rs_twwRMD#NisAiVA$irXDEkR?
zHW{XZe&3D2%__=jwi%9|0Q0&bsS~XmhV3Hwebb=20f*ZSI(PVV%Wz)`><&ZyFqoZ&
zk8>f?WpGJ=-fcrCeG8=9u;Cvt?-+JdaIwem1T9?e8agA;*K2r^5_x@w?|k7!zhM)_
z#D@$l$5qf_gA0}Bju>VH!ThKph<4@=48L84-(!Xkmx4SrOzy?7#|`W0PMR>-<j|Wk
zbkR#@w{iM<i0m;U%7#Ug@y{Q@+-Dq)##M7MhLJP-jgRO?I$&JPLCe)RpEA2{#@B9B
z2JoP<=`U!w8<*3|#>4oD4lPgP@>u}&Hg2GhqmS|SU1<0kB}@=Mqiq~s_!~D<-ZjAJ
zW&=u~aXv-8f{d|rmjxTQ(b_n~I7PF^VPpMDC>$~7?t{otqZd_YhZ^&Is4g?in9hTK
zxN&j<*Ezy?_jzbU8ec+Oab}e9TPDU7ZQQULB;I(2%1jcB?X=KNG`fvIB+1xI1rNza
z-}6vUF}6}%;+Qe?JebFgHz`4U!pI5&Ni_zZgh-l^Qv$t{#=v&kIG!^8;R%DMjU_E0
z>Bf8tz??CzJPDZ$V;604GmS^-AbXba%ypPQYm9e+iEQI*w1mnrst@6E<r=lLdN^mC
zaTI!a#<-V2@{NU=Fj!zL6Jzv+#`$ytugK_6o0VeY>$K2*vBbEk0x+e<3N0KiGlm8Y
zI^(une+?tNVDuKD@1n7=6MdD&$7$D5WvrpCSG93zAxMqUNH6SK<J-63Q=KuCQX}<7
zNjb<RV*pJl4aQGjh55_I;ENbpqp_t3tt-ZE3bJ1{zOoLjYsQ<i;98UM87i=EHl{jg
zjoM<|PEog3Bag~i+l(?dn7D3KQ0(r8F>C<iy=nBC0<+!tDn03)#zBARbs0aJkG|W+
zsPDk+HcrVPa>uy*P4x8`Z&HHgu2H=NSG3o-<p=cj8Na@UarPTGQOI$?xM~|MlLn2K
z=xEuHF<?4e95y!7b1-83WD#1U#-|rS^nuZG7ieR~atbs(G^UaHabuSieG^6-P0y3Y
zjdT?Ik#Pp4_oj?h9$@Y^**}EAJ*I;cF>yAHr9ot`DcA$8eWsYR^gW0JrjI@V*VWV?
zg;BVfOf=qurc_^;a5rh`Jdua#9wo>;O*?1}<Yn6bEn0_6=jfw--lhaGeDX0pJr9<A
zO~2E<>StQ?3Q+t_YnmVuV9HfPB+wK~AB_$&?KDC%*c917<@zBek9VPQ*rcVZk0Yj-
z=V9=usf3n(p{AGL!DS0GeLV+gk*1bo=!-J_wi=+(rf&!>##B}Vkyz9B{kU9lCPy3G
zjyDa4!_fp&A3bo1rhngrNRnyvB-E2lKTE+(G5tiF4#zRm63QwZH+}vk6jM#VQeYs>
z^gZnuPnw?H0Z&hv;*DUQHq8ozM!HF|7ky_;C5<2%CYcSOnWpVCfs$qFFNaTOO-2q3
z=9*>=!_jl5#7ki2nFi>p7n+9UAVsG66rd`0n4YJVMTu$tU6?2}2|h%t%w+p-?PFpc
zg-nI%Z8<K`dDHGPSh`@EFo0Y%z5f#WDouSj^Dwi@^bT!_t4%M^eNkijI0Xu|rY?8*
zTW6B7V7}fI{T-k$nMUTKufep6vPG9ojvuJJy3zD39s0Rq@}LU)tEO1Wzg{!VeGev@
zOt*i+V46+W767}&R6~ojR?{E9z~44g-M_GV-E^PIt!|j^QNZV>N!kvB?WRzAd*3qM
zb_3}!E!hj`F4J{B^lqEd-2vTgGCAIb;vG{iy)k=CZAQr4HH}fuzSq=T3ud3GS^~6w
z)1$w^95BsV2*p9u8#L@8(_>UUF>HE53^HPRm&iR+r5;|~H@(KkKu1ky(}DTG^niA#
zW2XBQeR^oJP!ZF(scpmo&<WGy#GN!H9fqYxriHjKXHJ>QMeuaD`GWv3_n2GUAn9xl
zqF-dM`5P)4*=Nq8g}sZJKZ5JL-~8`880Z0W91|k0=KM@xx|!dNM(d#2XD&qC&9Bmm
z(Zl>Mtvfx<(jbcGdzpji3k8SFu5?3rn?Iy{i;wwqD`b4lFHscN&z!LpBL3#&B!C8(
z;{q|zKy%U_FoVo9PC+5q+<O_=A?BG>GH}>zqge0}b89plJ!)>~f?lY(k>YY;=ArMQ
z7jC}bG7ZmPgjrAXRiycnE8LGVvkn70+N=;jCdT|K9S@H+ADRYd;>;g+K{DRlN0VoQ
zxqmZ26U|CWlP8&X(odLdw$tJ;#oS5n#$)EXZ-IH-JY)wsVSa29V5#OE9_ULm^TP3q
zI8K`PIid5ESu_Fc)8@D7lW7^|1~x=9&E|)|&NBbIAAM)dUsAv*+q}3B3OVMr6mrZp
zzeX4TocXsADCC(lXzP-1j-%avf%&{MoGCOv_BmQbW+~ON6`NnC1#5}<BP#zXb(lX7
zhklv);K#r&H_xTyT!p!33lz_r*>@p&!Cdkge7b0!#LIDJrTJajX;zuNC`4OrUPl@C
z8nfh0^wpZv*dTT0#4;GHH}7&s-z9T8y+<0%RaCKX+5CV?uo}&?s$uVn+3~?ibY3+Z
z=)t{ac8<qIY%<@O1hd)Pb_A^!a}vcvTFonNg0z_>3V3+ke36m_H_S`eaP+1*+aEr)
zoAa3fy=89v7p)HSFDD_=X+FIiU|r^NPxRe3^Z$EQnP<mB<c`_Nkp-C^^SRxCxoZ~Z
zqSb3|35KOU^Y$Nc@%zp8dN@2_cAtR@JZN4@ciE6Rc@A2`=4DhqJ7Rus2x#}r_AHF|
zzS-Cdlu`2_9c6o9RxE_bm^p(AjUJj$^}v~N^ZH&WOqjo`p~B=z^Nv+8@yPrP%~w<A
zXDPnD+oDK@7kez7R1@fI`QU%(+iTI$l3<_3pVqAhEIYFy;%d1^lct;HkOux9v~a0x
z*WJ=e3qTLc%k#lJWGSb!bKaKM-$I{{W$GvN`CFWSqwli^Sb{$RXrP7N2yT!inT}%w
zTVBrtGsN=#uONplzr2FM9I>oi1!s<0+!ld^T6)GH8D<eULnPeNMy0AzmN3fOM_cZC
zLL|mAyBNccwFD)h6=xA-z?pc9jR}z?%VY0Sp+K_bGdlH_V)^WIbe^#I)1^tZRM9pe
z%~Jd~uuog`l;TLYytN!?XDnZ)LL|eI<AdvzX^EjIZkFXPC8^I^WE9rVwxqoS6FHX0
zDb<i`843f+Im=EueUfKsp;S_#<wc52If^Xvt8n#-EoJY(V43CF-$BYP>#l%QSQ3w-
z?}BBVHqRF=u?Jzd((-Hv^s6lU=}cy|W#<oI)>zikv{P$&YA;%KmMbM_)mx%1xN4Uy
zAIrdOuq>jWOrzz~E%@!OSSmh*$W@0WoL+9%EYVM+*<@*?Xi&3dd=!c;mhG$2YPC3T
zhDMtu^mB~xy2VV9t#%9JJD9&^`ClDI*kR$t!^2L??{o)tS^TKL;I?I_93potmuO+p
zWAVs@`dv%kMhvOfa_>3V>$5m4R&e_*^Mc^pfW_d2Ycgp0Is~mDODf%0!<PChaAw3J
z4+G3S%c1QMxo<g2;h#~<npe?!U|DzuXb&wV0=PDA`J)%+CoE%~(3`a61%Ua;vTz|>
zo3dD)ps?Gzeks8ASf6lEaKzafK?lwDT3hHM?z0N0;?Bi7MXTuj)>(8S=YaK1%1ydj
z1t}PlyH!&K^B&gYE8wB0^_TymPu3b*Rr*+Kj>4|5_2x0?`B`JBV8-9NI0dZ$>+wI)
z3bqbE29XeJhlS$#hpjynoj77W^#HydwI(H_Gt^q~9<EH7bz~nz!mVj$*p0BxN`>7>
z>zVg4rYLJ|5qyfazVS6kjMexg#u97&BN6IxR@O5Bi?<4>A~L}m9gDt1>wC1bO|kw(
z`RrrXcTdrA(c{*2J8`*BSQjT_^r_aLD3F+D{cHf_v^B&T%yjDvihP{0E{K3nS=LE<
z4W6}jQP?-z+B+WxbF9BF18A=GISEXhv-;4dM)RyYmqR_@T1m;20;~KqyePEZ4@F;*
z^;$5kKZ~sg=0U&2T0=RrQtLA`=a*T(7=XcY>&pvaqQd%K81&Cuo5dK@1?#UAaJ^{#
za4WDYt!5L@s;tplfn9AKTnexn>+d~~thJ8N4yevr+>BPe)t5H0m#rpRi#J-!?_n&C
zE7tuKd%J4=Y8SZItjUKU+GKU{#|WFP`c=?qv9c+q)M~xH9cXRV>2$fTTNA6nykS-D
z0Q07GRV(z`t&1qXd&@e@8(<yQDw<0=t+&=gvdg;VDq6R#-WSp8wpP?*5O*9_(QFL6
z$C`Z)!@g_94UDJ5+8TmZpS3RoqW#w3=i$tN^-D?#4OxAjL*KA<Z8IcCtZTOb=APAY
z7UaIQZyv~~)tk;yJg~-m0fjN^kMxL*TbJ$xnXqo7b>O7+sb?Yi$m&=^S(GX3Q_sNC
zZrj<f!QEqfn$897wcVwV);^nmKKfj2qi*nGzfBVWa=?~NxtxQxbs=cE+ji`Lq=#)i
zE%`ic7pSz|%eI6T+J|iRM=<DZ3+qRpkInuI`h0D!6#MqGWjJU9=5Jd|VT}OW>t_HO
zXxl(lLqWDwipvMvhUjodh)qie+z#8`q_Y-BY(G-m=BTZ;29Ac>de`9>3A1^g0|~c{
z9fo>@t<n`fMcRs#z>KoZe;4Y}wm=H8#MrvN2TH81t&ZwR;%t9s118?)nFW$ybDsgl
zL|fuVFp*@Nn-33<*{Ucdd)&5ZAFxl@yq-cU)uxI>E6wKg8bnUolBjSj-S!IIxo2$S
zbRTEfytC1lX|vD=cCu`9is8&z+gf*+&$i`RY5$jFtNjk#T-%-|pq;a2?FGrR6==ZB
zw{@I=Vxg_y2c*bWJR6|JHqRV5T4L*S0khQhDV@qFvmH1FQf_;+3g#<p1<!z7u$`bB
z(nT9T50aI(UzdSdWt)^kz1mjVO(D`6+g2J(t?fn;xOKK^??R^Dw!Ix1mu#*)v>I&6
zK#bzDZQEU3#75iyC_8Y)_DUtL<yD&>MS-r_j8w<fWE-VJRn4|9N`Tp7J3)_8tL-PM
zO>48wpTMxM+e{P@zG34~y_@5vt=0%j?Y2TH?Ci94rbDL7*60C^+qN^G0PT)#d^K7<
zHmrW}jMz99nD4c1piM)cZ62jh`fcl&FgRe#q#FJ~+o6-d9J2XugvhY%0G;O>vF&3(
z{hsZU-5~dE71J=X2M*h^acGR$&Q;>dKC~^J3DI#|3$1S^Y|5{p|H$^wRiI7TexRRe
zx4rl@%<r*FxNyzc{#+y^_u1FohPsPAJ`p1O?Md{;J7D*vwU4WPP=c15y^KB)aL_)n
z2Q7Dd5#1ghc853Jte$pvx<X#|>Gz?3$iCn!5O4b^B|3fVOnPE{?QeVy5kLDBg{l4R
zLJ7tjVD}6J3ABGhYmmeC7u!IN*zZ+C@~Hh!%&#*;?caMsB+Q=o6PV%l`;<qIu%~|y
z%t*V|5sJ<z`vN@-M%znDFs4}hOxjAs**E?VqVaYyRnH~ZxBm>uM0+mnjFarsPM|N@
zE~vr?Q|xo!2ih_F#8Xf|Zl9kBFH-H#Qp_REel7;&q}}&zT;@}D%Nj_YwikX4uyp(R
zXbKCSv8U0Im<;>Z>1buzf22~VEc?G70Q;={4rMWN?LSj#!Z~{k-E(>Na4J8|w|`5=
zRtoIZN1#_|cc$%Qk-g?ms2AHW|AWz&*aK+&SZe=+3A<(XeROoM-2NSXYofy5X!@^E
z)!zL(G%ncRrYgFN_E=gwRobOD(W<f^rIN{N`#xGA)YuiYrLMJi&@QLW{zM~OtGAcw
zA$iGuelxHe?DoANm+c<3TWGYKs95`oeHSguuG)Q@(Yj_&Spi3z?DmhR;rVN}FPZ_E
z7P|-Cy4USnccb%${n8%5+_WF1{dv3HwHsIcmi?=T=<Bf0p{Poy-H$#f)@A2ygye0z
z?hMqs?V`6JdB^@bEy8>3kJIgO*M9ITkY4-G6x!*tZ=gb~etQI!6gdX$^IrlTw0|}O
zWXOJo60O7buYG_vV*fG<iudeq-2&)+`^DKXIBMTQgLz;Nrw!wnT_u9~hxX~TULLnU
zPg|D>d+SArOxooV^gXh_o&e^Q{g)>Jy?a|Uz0&t=ySD%e&W>#Z9|C6Yw%<75?%Vc=
zu9wTUlYU_C-)5!Qs@t|tI1oL!Eom{laNl-U1g6Kf|FiTRU{M|4+qrjlfnCbN?!9*#
ztTAd#^cOXWnxe5J(HKjL8jVq-F-DDvNz`2xO|taf1QF>)nur2Yr3s2CAYeg25d;KO
zP*kuZ`n@Or?|FPU&dfRQIWxD+%sFT7E~l&|f5TUm;0!QmUc%l$!;<IdM37-+5lVXv
z>uACZHhi%kr4WPk6*TNKETcmbp@zju7_;AC8bQ-<n4yZ&e-0R4{}#33hH7V!2t(3;
zA$Nn-MvQut;YT`s7HvqF2lX+AH_68tYp|vy@;Jk5v>J^!bdxVC!Eo;+N(T)-luwyx
zcvOY4NHW}`%#&op<(FtnF+8SZjZ{O5iC)@=49{utam4V~c9f19-uxFZ83u;-C7FhX
z9I$2?W=uv$j~QOO2z#>)pR3TP9E1NuVCNd9x1yA97`+=R3Jg0tA$Q!sFM(X4!GfN+
zB18KfKo=W!(3`Zx;5#1rN)6iW^l+Upa0wt~hCly+M7d%1XOKT>SVXhSDZ>ZkLa#6+
zeu=g-hQ3RvJZlK}8pc!^%D;l%bB0gpQK>cX?$A_cXr{aSf?;<BG+i`|rv$%ChIL**
zX*A?gnnaT!_aQi&4XrWcf4O3qcLl|(h955iw8fA@r#P=0&e87ywi_H*1FgeQQUuaz
zNPh=yHw<ZXMY;?UTKsn#Lf(R0k70EW6y7v^^*6{ZgP#&M-8PIW0CcaRZ5&wo40nq#
zuy+g>?}Fv7;YXzAAVg?L*$qwi3|l?{=zYVkkD=m$Vcs0rJz#i7zWzbO-{Ya_p`q<-
zpgl6|^nv_igAciXo)|pOL(@}(iWELGM2m5KpBuJQ2IP>zopKRg7z*eS8#XLFi^`V<
zvjsqTW$^tHC6kl!Dn$jHjpxZ{=wei;KwOPZDpa}|$J1x&J&l$7q0q~CVL1f7jmLgO
zFMN!-6!-8oZg>wC`WeqLApXXwG!_BIzsW@tXdL|%U_r)t#~{AfxN|<_f{lZ(fhEM4
zOOxV0ld;ebprOXAwCdPzT=qR0!;A^EZ#`gKK&$?6<1X58Mi|2nq7-Rdz6~r<#sPAu
zM;il5&=zAnOfkAxW05EH#u<y-!4hw5Jqwfs<A*1q;h^!oZ$T1`{|-P=lJQpxStlD!
zYZ}mt6l3Y@kWVunScS&J#&K%Eq#GS5h2x0vGiQ{J8W%mnSY#NjPoOf(IBbOaW5y3h
z04CcQT!+r&7~509l56~=8hQ(icP&AV8|}Y<F@?rmoe(H8=GmcCY^+-i%o5{f69sWf
zjolRAJz=bR4(u|cvkNLKj3@qcR2j|4zg=n6oCDe!qZh5r&l&?7Ay8#>@&a15@e@i7
zs4?!<!I*Q#jAQ6Tt?~Si5U4jEpwlMjjlVoY<ppEF3K)9P_)#V*FBwzE%|P!j8~sJ7
zZ8Yws^H)vA^?QKUY<!RIge%4)0VrKH?x91KEyksrz}ae?{0-#WjHAMWq7cK`^)YPf
zG|r{?><#1i3$UWwxH%5cJ;vP>JGyC{+m6ax#;SK=_HAPTgHo??Hm#8RjQ40!`pmf1
z3Yf#jceB9q%2>4t#AU~s*8%OmWA1$jc<ngzBTVw$abr11z>Z&6f+cRp7SlBh!r>k9
zm!Lj##~0+1%Gt4-94`esqGqA8XvZ&`p{aC7&k1y*d`B(y?DP)L-KebDvC$7OEjz+~
zLfh>fFDMK?xMST&v<>a}y#_Y9?rft?sOL`KY#182)4K}#!gp4alP`YfTNd=mmqR<d
z52Bd0^C2zZigx;ofL5_HLJjq2cQPM><^0Zr_9$K6X|owDfxDimpdxaYF#-w??n;~u
z?5te_TTz*}Yt?OZyL6Xv4N%VR^1O()^Sh?e7UJqIfAX1i?b=Pr9k+Hxsc8-WVAuQP
zVtu;n{SP7dV%JkE7~|sTNU7yMjzRvY^mqKe0i6kUTu!OSp^h^tJu1@io*TNB==c+D
zyiy&P%b_XVv7`^28II#g?wI3Q4{+u>KBRqlp5vUG5Xg6Qp|E{{<5u_sOp+4EDtgbA
zI+pgrs4_?Yolsxy80Z7glaA{HK~6b-v<V%paD3ARZKoaW9Y87_S5UUYS;u<Xl~p-*
z-iO{AM?Ebp&N;50i^^KZf}OCb&e4u`Z1s-T<fXpgSp5uETy%^bhc?qC$2az)*x<Ne
z159jmY^McHlVctQL7N@pUZQlxaUXeMI~{+b`K#M81}=ctB=~oVL8J%I0y8xc=3QpK
zNP<C4jD+sAE6jIvn5KpKV;qE9nF$)OTxV`@D0MJWI&|F4tku#tZTp!#O5J(F#Lz6@
z#Fjh&@n+Na04A6%IYa?#{1Zk}y3nXInfU+cN&{4l$tgs?-mEHy^w_7n0Qu1t+MRuz
z{4QFjP5%(!)5raRzn@HVN9&AT6vv!7axq3~mU;ouW}AwEE%|iAJyd=6ejkKCucXA%
zIUmwWW$v#k2!FAEErjPCX$Q}jDLh)|SI`S-!SGr9f8i?%ax7Xysb^nFX>I$p-z?OB
z6Y>Vk`qrOT{);nd<d$TYgJ)^}VHo$_xN*Q-_R6#xpvyZclkofgK{Tu|ic#}J(R}=W
z<%Gi!SheaF%v$Y0Z^R#89suYX&I>hb-#h^|>n6sd{^vPq7_9YvI`IFpB>=4(W>K=x
z##nmCZaPWM;lEun@YkKW^#BbXO!aL@c$yfV?ny7^LN{u?nfwyy^<gS#?($_`y@T%f
zG1?ax3x8(E5wPrK8loZC&O9lCCHEK~`d-9+rk`Gz&zVojJ2b?!$w?E-O#<;?-<=E%
zp6oozuJK~0`~?l(?5tfd)rU0+&j91gt|1SdAG?P>(B#k7H$q_)+fLh-XtthQwkhmX
zdJm<t8cH5H#JbR1KaFkt7HEgrt^(MU&X&@BeuVAF1olz(9r6rhun|FE$z)G-06L3(
zItk*(SdTF%WwWX<O#)+WswU@BKKsXRv=y-5>w%IhY9{YWp6E}?j>#7_(jl?}(V=HB
z;<)JfT~ro|(*6Z!k!Tz3mWoAlD11{Q@}uO^QjvE)dUQhMuoEa{qKV`YC>Mo`A$L+V
z_jRD0616XdK!xaI6YUjGi@NDquM`>n2c9#cC<-#36>Zv%QkCfMsX(h1)p9VqM)dY)
zAm>CMj|6C~D7qC2>qMQjm#7!LT?RwXi`IM(@e3l!GHALes(2j&mqcZ>(`^vlkAb4g
zqW9{dwoz2Fm;!lCqTkklG>Z(xdPNjQ!Pu*!Y2@*35#@V=^_pk_?Ymn={$D{wn`j5^
z=dO#!&{2(cQBM#wb%=`S=Ia#Y(8;|UqK9;9rb|>uS#;f^=d@Ao5na8C(oK;iy=QNU
z=KnysX17H}9{{vhbcjOleWE0q!tRK+ZUpFEk?$7}>=!M+4~cuC3`#_~FZ%Fra6S;}
zCt?r=M1N2o+o0&|7F0eIO{QbMk3?Amkb5k8O0JV9qEi$Uc`C9>0Q57F{|o4QE^4a~
z<0U*KIy@SdI*E0^pfk>58_N976wjqtQkM94BS4RdpC_Y~EzbG~Fgap(%CyTB50mdO
zPh9*2mHFb3Oz15T*U(d1FV3My^SpRM3*;_{L(hTpqB!6J$Tjg2O1Eeg|9l>trf%_#
zP|zOn8Z9I+e^Ew9ulUy65cHJ%dl%SVl6R9}leZ*_QiS~Qy)@YCFL4e;Wq_n$4~z+v
znA4LMD_Ob%0>>rnmmr0bkS>rSi5*?^V#!b~#7iVnO8O|3IIe_-6DCQ19%z{)qY`?{
zC23btIwd(X0VY;Rwt1lPv?S{YG*#l4l^}mc;@yU}vyx>Gp|=X3n}^<NNjDu<XfvCb
z0PO2#X0&)}H+w*(4zqFpgLtP|A5A(p%n}?xy3F3~hCsKOY4`hdxy)=R<?OMUw-k-9
z%(DLhsFV5F639E7pS%JqT+CA_hUIH+Ny#RD=8hq#^f$L6Lj%lvXnhuBUiV)N*j#uG
zBN}YpPyw>f+>Bmtq2^!ELVv&cQF01}nSXH@rAYJnrtP3n=3EzQqs?#AA*F-n@fE1d
zG0&zQV6OSQbR<2`eBL9BOul(R2@SBh#WAQaGXLrt>@7CW`~;?zm~*pXcB%Q}A7IQ0
zbH)LsGv<0)gPk?MK#xO}`JgYrs?E1fLuHM*SwBsJwdOPahJ2m*mtO;|$vlIH-Oc7x
zXaRf0{CYiXx@z7`PSR`UOXoqp)jWpQzisA^D9hx!d0ZH<JIuYw7u{)Io`K3P^Es4}
z+-+`7FPNL==W-x$%iO;nEWPG^<sf&=?Z2c&&|ULSXu;8MZg7AVE*4wX!TbXj^-m!f
zZn3@zl@S(W!k|9V;$aOyqb!;oX}BydCjchK;v&UHV=aU}aK>4*ID+M%#iS-!k!X=g
z*)2&HI&!)vTLhCUA=P3gj@d~LS=hZpfrK=RsD2a=TO@r0)^v-d-vB1pB7X|3$g}u@
zP6QNKaHTNjxWzwZ04=nzr8}X>Vi|dnODrbQ#9L~iPea=Yi}QcNv@(mp5g4a(iy}u<
zp0XICm|KO#FvY%3TMQckR%x-2;<RDfRL0hH>J!wQvsgfxp|uv;xv;0s;>2c@Zd*9g
zNs?ZRpQ};2V=*NjUA}8kM(*K$i;nXk_blrFg!luCLv$W&z+%k>a6Yuq(TnSm#R_r{
zy|gGMcjqgMH54>-lKx-~PG{+(Qdr<3-DM)zq^mSd2^cqNEIGH`rOW6|>mi-=3~ip$
zyrmHIlD3RSw}PafQ3m{8Y3v}dL!^^BA-7K&y%J=<G~E?)VbaI6P0f(j(Vi$%`UlN&
z$E3xy^UjuD{sCY)(l~FFa;0xRp_?#Inm7>#=Sy!>%0z+m&+8b~<I*`*U@esXFaY@?
zsS{20#nL;cKuV;M12Df-+BqJj6H=eQAYLYYM*@ZAQVFf#PfCkRX#Ay7v`ws#j-o_{
z)6z2^1G-YWA{uRHq_^WJJN~RRid=nF()bNvt(K0Vo3KVY`fHGL(g&0SP$!+)3YL25
z>nsN0ytL^s&@M>rKZW{>(v=2qUXnKYpt3<~?Eucp(s5T&*(jaW4bm*#xe}aLr2ITs
zcvb555>~WGfA5vyCcGw{K!@&IrFCi0)Fw@(V^-It|B~ytU3#<-f*sQJwC3-W7P+GG
zhIG9Rtmu+nUkuVMmGwbkk91`RG~JZmrq$jpY4ij1<+gPDa%kEsW5r+zmU&HrK!hy5
z7MPK;Dp~`XqGStb2Ocd;9|nn)rOyOwoNNfY1WAHy<1ZiwWm&cmOq6Y-OuQtS`@g76
zk?s5nFsZU@qtNX`vI)O|q{&j(12kRs1CO?&vXy@TEJG&h26UlpeIHCKl37oJO(n8D
zlr36nl7;>T&`R0H7J$~v9BJ8fUS?1G@e8u(|2#snECt#w$#O?SutByY2WXdNL)jRT
zM%lG0bh}ArOorZO*$7IX?3Aq_ul5aDEA2zNWLaOJ)Gago1%*8_Gd(JA$~Kbo@|MhW
z=_>5LE$j0EcAu>0JJjBhEu{s|UD?kQps8OrV?VI($;Odu@xJVN2oye$N$3>9fNcNg
zz#fztC{5>~EbRcWAIa*^gXM`Viz1m%WoN=6{!BKL)_%`r@7DljNH%6Y$P3x9iN13>
zEc-41#h0?cKTvul%cPaRljTe~Omnszm;mBp8BBW&SIfFzQF60%qAyswTb`nn7!S)%
zTD5sv%9CNek0tXQ3Vkgn(u%>)vWs?D0hYluX9im8?O<Av<(W8C?zP;TNju?S%V~qa
z4zVo%7NvcbqnsfhZ8?LS3Ne;%kV7}t()}PvoMiyLViPQXp^pq4w9KJvpJ<8SM8i#L
zd6AqxPb|wO0L;nit##mZw(?AXLKmz2bh6%R=Pj_fS$%j0hPqqXd}}@uiwi4%+Ism|
zg-{l=uT|qu0QIxty}=q_r4O5Z1P+VXXjJaEGSNw_Fsm^$(Cq_O+x~*R;Z~2yXBBC+
zWeu!|vU+bZu%oTUky9?lN<|NRoK+O9#p12rvVmNJ)wvlk=AhNfm(Z7FwR;gt$yOga
zgC)gEJquu|R@sw5j#*jJhe)!mc9^Q5KF4bAS1>f!Y9GyEc~<L30xjR_8%p6RuzLFu
zNTJmNdbW$K`YHHVYIWmt$dy@*r0q(%Rn}%`x?mMQh=ILmRm6kyl2y_&v^7}Gu0`px
zm0=f98m(r|LS>WHgmj3vTg_{u_i~3-TR$2*tqT4D>kX?=JHT{XxzlI4Zd+Bhg7jMX
zbbzzZYFiG}-?1`KI?_F>t);N{zSY1Kv^}u;XA~~XfK~Ju^yRTt_C}B=R+;2RcxrXK
z9vYrmEv<&3&#gLhp=ikJxh;L8{e@M}AR33Q{-9^X-#UO|Q~}lt`yn4_9WV?MWZm>R
zD)(A9-v9}=wxkomA=V>kU$xJ=kDh~2>(`aQ-fvwy0bpU)Cr(1{fHg<=MYwf8ZB!zx
zgK|J3tv^@@&M52o&J=WvvG%$R)>!MQEJ&R74>YgFTW8Y_F2VX*1y~PS7gV5!iPj6R
zfh1eM-iSd+v92TkK&tf;PxSDR^)Gr<9=2Y(9K)4v-AN~lj#$qzLH$wdnmHgD)>o=g
znQ84vNxfOtjg*dSI%d6t4&!87>+r!ENshH8CHLl8=cI#p*=(S2gSSoc4`B7NX{Ymr
z!8Rl4V?z-(PE)BfHcpfk7-e(KADq!Pi)KJB*5;Zw42`o%8$xBg&D92INU*7*Y^H-Y
z4k=KdX!94v=Z~0dE?t39xi+@{g5=p8O@KtcO&q-;3T$e}0j9?0-dt!pXX88vFts*1
zT0&m78B4Qaqm5ZJ%x<!|LTMb$Hj~J;c*VwA3zn-k4fNV*v6&YG3$NL1zX!}#o3Z1d
zq0QzYeM;xLjp^uYn9*)CXFFIsY!a5i{7#!~8$r5kQfXh=ZL@PFSbA)-$^diIW(Ik+
zZ`s5|L14hfGaoR6HfuZ3_RuCE2!=kg*~y^ovCTVQq4dP&Ipv}}wMnAK@R>~<Ih&r_
z{Fn>5A)AS&4^jKV<_q#D4BPxkUrc&w)A9l(C;4_W2s+Du+X5CBxjpTuT;&-wfw;-*
zX@+)}TYdyh9`c`!D0#{Qw}aD5?yrHkw_J1$0zUHhenF+LeC$$;ub*5`i%oyI3*{dM
z$P?V@`3sbviAHUZd>IYtUilXk1`d{gn}Es?`4L(>hRWCcw-S<1-wKv6xhxiy2jrRb
zO^9&$a`Nd%$fwaJCQ`nC7^Nur4h{;V<$brHK1Tk@TG$jPf9o<z@$xu2+?60-<3(%b
zgYu(i(3mK9`x=c&@>SCzm@E%&1WA#fKLQnp<b`w5nKb$T9Kdo|-n0;-moE3C*vAq1
zniP!MQTd(!=45&JTv(AQ-*OO`S@KnpU^ymlrG0F+yl^}!bL5x1aVO--6CYF3TfTfV
zoopzOf8-3%<MLX1?hEBh--G%hdD~{l7t5E>+qOjhC*{#s$_F0;?Tox<B?QjO|ER+_
zRmle_W8$Km4FSs~`RS|ZVS{`LoiVvAUwr~#jq*1r3f&~%SP2W8<wf*fHC>T6ltALD
zd>lF7TI6F@K)WXYf_9Rv^4$kf*(P62Zlvq-C^w+B%m1Jhx(;~=<=)(of3^*kUGnk&
z!0c{0D+YFte8>v|H|1~97jSOLt!Z+(Ew9}N&R+RRdS~~^tLQGdW0LQg1GKyH_bE%S
zUp}1<fZdb-;0=lU^3+xsGbo=<{=bKE1Xgf&%NLx5z+?HEiy%+re|v)Esr)6a5ueFN
z`J<!H<#wqMaJHREi(nVqh$z_PYI`&k{dKby??9J4Yzt_$;c08~y@8^a?c#}0=xwW}
zb%Kv=5Cx8XZJlW{_p@C*9+m#KvnX*Y!1mAM&>LvG#T}Z0Y`e*&x7W7)TWCtPb627h
zX?9nwfSGQ$h|*P#+HHRw#$?*H{R<7p>;_LlAjhtW_H}u7>u0?OO@(%EXu#TNmsbk;
zPCFY)PrqUJ>M%-Oc0KD*>b7h90rEX|yZ#6Hn|3d0c6nge9~fqq%ZxNtQQp>&oqq>Z
zy|61HpTe-+!z@(3w2S@<*stu~%7TQGVm#fm&WgaF0qUZ7LTM4M3T80`{1kB!Q0T9C
zJRK;J3S$~7qZDt3qiZpWv-FmZRh0FDB~EeSQ<UNre~t&|LB%7}C)88L00rSQ6dO~Z
z_qgIW%Ec~J{7T1;iWEIlz;aq~YAHyiV)Z_{gB7l~Ab(b|kCu~Fip#S=suk0ZLas)!
zp$Ky46rD8AwF;Xp&|9adT?10DIQa~f=M@)e6?;K(YNiRaMKO)C&95mwBR5N{V)IV)
zuuT!@1&Qkl)jpKk6=rn2szZ_X7f7d~+zjM~BJvsJx)iq=l)4o~cTnn4jPihmHx<tv
zAbv}6m_j$V6^~y+QLo}?D>(ZU-t$qqqj>QlooKqND5uDNzhcrN+#mN8kqQXjS4=+u
z!3T;6iscO`Z0Iz=pyE0CARj7DE&<FVMKjHqj}^bt*|sN&iC4h#RPkK{+MX%4Tmk2E
z#o8d0h7_aen;kC{A5+|HSkX&qz)ngHcD^QwvvS32fN@dgQ1snZ895fLZc1?jctVxj
zMPTn&e*X=y4=8{62x#HT<3C~Wqm=*CU@W7RtrR7VQP!-0y|K#AU15Ek^3z6?;+2Of
z4<bQ%>kwUS<xO&BBr1I=(<4b~{W-?Tl&pMz9OP4!_b7=aRXIqm_e09tv}8<E2DYMf
zSUF?{P3g*Tienv7#(6@;QRR#PsK`*Z7lJcWIm#T^S;{0SP>v~Y(n*1A<<=c2<tTN|
zK*?3c%tr_Flp(a2%~xKfrDB0exj7%K$CZ`iP+O>+mxEG~au4OA6)X2qI#Y>q^i0T?
zDx;ksaYA{f1E6KfC*+zdSJvA@?@47c`NB^rWwdsxP<GJn>a^00966QBb;Nl_`RaX$
zpH&{CX}?NYM6t(er73Y3eX3E;k3jL9axJZ-YL!bmAW^6Eyab7Q<#-D2o>$t?1a?8$
zss!gnW%D$!TvBdTVq_YWA)QcvSt+N<u~GTCfXXK2A`7rIEB)OdenmOe5#*|}ijMEJ
zD5poDgV&U!!$uru%uGuXz}cq!HW%c&a=02DY*&6pF4qp_=+}YSsoYIRPHrgwz6+Kv
z<qLY}b}L7aH>5`y@Fn!!RHo6c=$3K^<>ud3TGQc$Uge%Vu=FY0dr^5uX^{at?<!Mi
zBj2x7UqFxUDIHC%Fy_8eJ`Lo7atB?40p%WR4D6tCjS8iQ%Ha7>@knV--&uOBOfbTj
zC(4=zfId~;r2{0-l(YAOJXboAZ)HfC{wp|ND7DKVKCC=g0nV4o>ci;#E9E@O+jrvj
ze+1&pUHzKYE-u_FO6_vx4${)tjZ2~PKJHvY9Srv1R=K0($(2zisTcQN6F|MW*%x4w
z4>yk1{=VE-bOynX>uQH4e{SFj<N~-o6!#6}24|x!i0f^DqP<)({T^H}*SP~0hHz7@
zXeqysOS_6<C}*N`e*3v7Iwc&&33MqAa7-{rIQN-9#w&tb6b$)DZW_ghqPVl)LsK+Y
zMz8D`t~4Ahv0VEyXo};?o6(neZeTG;0ypMw7;}&trn3Zz+=eKyBypC=Ni<24xh>yA
zFooMkhdolc-dLa=;!acKE{$6<6PgZl*D2ne&ON1(J;G({VZ~AI(j<UpaCa#(l*xJh
zipngmc>pZOI6GP(XLE*GxFR`RsS_0Da(46*$m8sEV9Dp!$3ehU!08C>ICq`0I10Jf
zGf^tyX2ihKV$PX%#3fuBdD2Qb@h>1JxTN1e%DBVpAW+UN*Z|Ix+|CbS?<wx{wa`?-
zg)y+{G`IXIN|ju;I|R;f1|JBV<!0zXs<_{FfK;2fKPk#q!`)BBSf1m2vmjB+y^#*k
zI!@~Wn0hWP6TLXkrDvjafeWR_{vtP?R^6AlDHG9|2Cifn>MwII%t0Etb-O^CxW#7x
z*38w?JLn1*c^ZnYa<itOt%cjq0`nSY5>qZqD|aCuq>Z~wIU(1%WO8V>b1N(%(ZStZ
zfKn${x*RY!xV{L;cX4aTpU}<yLJRvIPERh(o19A|OuNOYD$sVDbD;0f^>VA8qOy;h
z)DEya-1=8&yUXn#07^gCXljT2Jx)0mjrX}NdvNPL;Ou@x*9N#_<dq!cRJ1;L$n~TH
z<`K7*K9Ka7^VtD=pKu%05O~V%qAk-iZW7&B&$(6fP8i~*&IIQRZsSH&4s&BhLE%fz
zCjjIXClo-=iC5duB<##@vw}hweo-lEUHR85V7D9pvn5#F`6m?J@Zg`uqs@~)O$%i&
zKI=BHz4<kCTl?^BQi%KVW2NYtAMZmx1Ajh-vY-O^KNV0P$iGiH4ncgN1H||8pUZ(6
z%uks>`AZ>uBIT^^<2}g38p>PH;P2-rllvu%pG#+r5AZKypedXmAU|RRzq$&Xk$fC&
ztfTl5A!v){%gFz6gzur_LPz-x-#}9a|0yktGWk*D{LSM1$x(BR_n>Dan|H>J+9b*0
zb7&oy%jeT%n8#P{f~EQV$VzmkfWP-IOgql^r$BEZzkt$4iufJX04?T^Q!urJ-}o2;
zrTlvG7@pumbs%N@26qUQ^8@z4Jjs_)9{MT1Ap)feeqAF<r+G02Kundq1udJ;@X54;
zIm>@VFZ(K9PszR2yzVWisNuh+z1=y!b_oP)`NL}gQ^!|)2Tk>S9z7%H`HM7}UEoKo
zhiMo2iHRs(;vFdYvVrg022Gdwcgg+I$d}V0sU|*_Hj2$Aewg-XSNIxQX<p^K523b&
ze{l-kzQ%i6fwh&ldmozG_?hP5yw0DdKt?++_=0rsr^y}I$rsb@af5H7!!TX^2_wL|
z`JEqwrHB9ECzNjTJ1?PUxA=E|0N8DQ9=(ZsdDD;NmgwWHUqJ8<KTQjTcll|rK>B%4
zI+=Hmzg_~C`}~2i=+gs!Lj)=Z_~^4J4e~uf(EE^Yr2anQ6ADp!%)9*vmM45BrR+WB
zx4aMa&-ic+6h7yRBp8Gtel$fOUhrE@Z-Hl+KSc}tmwf$1XnMul?SnB+!tAx^nzQh{
z6eSno94#tch2>7r<R)a%qR?H?A417P@LvsVPhlNx@4W<BFI0F7zf?iMM;N9zgs(8I
z5YT>t(`YF27nZIDOMviuHRZwt3g405AmMrj(Dn);Lns9c6ITH(M2MnT{XSv)D^!LG
zArzzBFI+zX&@iEZPIVm+BI(mN;ld3%Ulbv*3()&W;fxt9j1soc3np4Po)3jF!aX|5
z5G#DT6fAMVTOH)_j~Cvd533~zx=<K=Q25##RwN3)(_Sk{NTkfaWI>mJQi|~7-)Kt}
zIQk&PA>o~o(3>XA@dG(5Y%K(5x)4H-$`N7tet;bnq6CyOgc+UCkSU~6P&7+8J`=_q
z6QURX_dP~o#R%}^2p5|nkt-M|pEXZdME6|25O)TZ1;YOtAb4EZ7!1xrp^Dt`MM5tv
zOp1k<6;NLy{6(W)Djdp%zzN}B+R~N@i^$bcF6bx`^`tPg6qu(3E(WCvp-Bx+(`g~a
z8nu-|(R6^G5q=Cp*Uk!4DKn)?cs&g;)q?y_*i<8I=t0{#VIxgIwZe%ZD6A76Qf^JX
zP<;`c=Y^CfXuBXdyg=!qF!2MZza)J54M>AvyAB#I3!&2?*C=cxk5rRMu%~@zvoK>D
z6kZV~cw(Tg3SZKOphXCu4AyIcdKctdg-JBBZ9>i`P;p(DZ2`G<;o4Z()FF(eMP8@y
z!xNy~5Kc}6XO~cQ11h?Og|x@%5o`{C<)$z(1sZM%OX)3rTQEJRkYleP9Yk%PP;wJI
zcZA)vlejBPtAYA{VHGV2?g`u@l<o_M!%%u4Bzz6f0bxI_K?a4Tw1<8u^eh6(BVm|U
z7LSFWvtjlVVR{=%PlW{@C_NLtlfwGvLjE$y4GEh~wB>mrm?nc~SZJIKo|nQx+NHb_
z@I&Z$3{^8NV4<_>9}3I6sK)D2a#guKK%1M2n+u!vsd8z%8miiM3T^vU>nH^~OcjHu
zrsRNX$$YehtB$<@iBx^I9|BP-J*5ptt0KmmP#dFa9s~8Us&SX0H%?V$L@8bsJOc6w
zsujHeJ*W!%8+IqEHWO%)YNajYl2z3nfJsrczYmhC$|e8uA=MSyf2FCaX<>3$wO@tH
zl&%_29^oUZ<Fq6=sv1Q(E19Zqf1>>PELH1v2p&_l-UMj2DqjapIjU>4Y{*qH6pGGM
zt+@xA@>Le(uPsnL8UfDZDwbR<g{ryaT`yAoLpzsZ)!nzDw?rkUP-v-Y)(2=ip~A`-
zkArFxZSBfczIVWKQib~g^WQ1elrX5MP^}Z7;<V}~%A>7R4UB;LGpgU(q3NvZCwfm+
zsj~k8XSM3wJ#?l<wfqy1bE+x-0<>0jWggVmsp84|TCZA5{@U}Z@!=pBRHkH9UR0f?
zoYPCH#dMmiK^2n(V!Eu#qvNNIDvNHYXi`mC1lDGiH@Q)+s2(mv+f|kAeUKK_Xo~b*
zQ~Aw;O|7b}lrG(-N{RsJb=599LeZ{zPU!$0s$)}NQ>SXhT#y^8Wgh{oOJ#6}G2N<J
zv<>S~MNs;}O_S<3N?W?6dcFiaw^gd+K<ibdbI{bM5>qtdj%v+3kh`i!*MQcqYNi+R
zJ+MIjzUpmzkO!)O)39(rRS*u-235Pi#o#?uE%(L%JyO+Dio;`7_5yG|QEho07Cu$Y
zvxC}aD$`<GGCo(W-2>1eRq06Zyilc#1KO}^{VuS+R8>BQ{3}&_16Z8YKFP4qS$*go
zlw8ysXi@5_cI8lVQ@>Bih3@JKazJ>fN4*DQJk<prsPt0reGQe~YMy*<KI*>-(^tLG
zM6oVEwdp!){neu>mKmUSqscr_eV1N-LF$WjVA-qQdK#SxR{PSfE=2u3dFS`3caz6I
zRK1RJNcO8QkcDCDZ(BePs7Fl$XSh0k3dAGSy9zLdk?N2!=wOtZqjR6p>c=A~)DWY-
zxgULsRnHlOM4Z~Q3C6^$Unl^Rp#H8Hf(O-aRiTuq{`wvSlGL(AC?%^CDF-V>{Ry3R
zPgQ%r37Zb7V}A!rnz}I!V29PU*Ptm~J%;wON7MtfMm(xM`WP%3>W|(dCs3w(|7P%H
zsU1|X;+XnL574sJzyA!qIqIs1FeX>Me>LRu)D5;^$yXQujmiRb-8GbstIOR$3e}H1
zFu+CXI~O2Vte)8nV@lM$yP>dDJ(@DIPN+q>s4P=IIE>12_0BkQ0-aQkOaa<ywJ&`K
zt5Q96K3LDH^JYU~l{#Y;OsiH0o`hhH`t%vteNKH~0@`ZT#dKTNso$Z%UA;QxAF!NP
ze?gg~7u28Ay?#+$N)h@?>bpK54eIISBDt)tpt-G4y_8%erY3dfYQQwBKYD@ME9$^v
zT>Go)x?pssMcwi_cv{tyzC&f3T0y>`>*^{o6t=6=C?CB;eWMiEooaV~pxjW8s6!{Z
z)Tec@qFc?<i?K)T6$oQ)sz*>x(JggG3pj79V<>dgYf^7~AM$<bYg<vgqjsY2dEZs*
ze+Fy6`Ub73@2Ll^z;a*hL7V;o^;dKTVo=>j3&4l!)k7eU)ERWMJyy4<q3MbG_eR+J
zRQ)bpm}hDm83dlIOMFloQok7o^)J->not^6o8I{jf-lu)+EM#TZ6$#wCyn_6z&LB{
zX#MJ<S$Z49RrCIOw7F^4Uj(+hruzggnun(0Q*e4}x=(_|OVdTKByY{8X;A2+84gCJ
zucqrZ#==k27zF`;&3St612mT#(H5u~GPPiwgEaQ1Ah=hvd=Rz48jjW(A(|&sVB$W_
zZd%5MYWygSw_kJ20_wvwq6JWKKy#rArEpCZMe`yw|D(LHNKMBBh(~F@p_?sQGw?Yy
z#AwX^g8EoZHbukZG`+M_jMsF{GohHEIW-;X4{Cl|fKsC7A!Q0CX*8!`OtJ<JWjte=
zWJ<A5)x1VuXg{R!{s^TsP2vTR!<v3t?WAiAuISnkjmZk+sAi!#+A=hE=nl-(2()U?
z(kx2?Ii@M52w}D+<a1ho=4g&gMKM<sKNp?J)3lMZAz!nZ9+Cph_jIuKxW>i}#uRFP
zj7ATOG;baUcCjX%jw_UCszyStRO2O}hbJ_%oKab(X$^rD<(hZS0{Wz8N+JgDlxDOC
zI4d-Nx`CY5c;wOiSE=z#gWwsBoK}u!HA@50`zlSyA?U5vyb}s5YBXcZq5hnPrv+rK
z<~0|v)M>8eK~ueE3~iatYbMZyc|l_t2h%QU*uSColEyv-_BLo%$)NDErhr^DjhX;A
za5ia%Xl6GxYs~IJ{))zplAy0@<d?wHqWS7GsJNziK+(Wf%?>+Q*rwS)j@Ij%6>oyG
zT~kOGwnGy#1)QClUml|JhNgy=1YMetQBdEl+50~X!UN5;64*4LX(Jc^pypc&0X@{r
z`V-`lN#jPZ(#M+L>3q@?%}QEvKGpcs{_mN_k`gPQYnJq(ZAddfxtlLEUsDp!u*RC6
z`<I&jRKOh3c3Xk-sP><eV9C@jco&^GrX8?CTedbR5?17Bzdwn}Ty119D)Y4aXx~?$
zHEpJqSfMtbTzEy=H9NsmqD`V0P^q^6cT}FxCd%oGYD;O7Dc4$T1KLULJr<=?+C&N(
zRcJq<6sFVK$Qcknqn(*TS5j-rgE3XwkK|yf(ax9&xpUe*bh@KfyK)RF>$E?bC^4d5
zn?)Y<^V-507@-T=e<;cAqSkRVU@mEYq?K-icJxtjUe>-rC-WM$NtE{6q<xdZCC%D|
zWK>?!UZkz`RqgRgsA$oyq=CJr-DN;0TD87(>ZeWXMeFqI+FPqo*{+?aqxr8}`xE_i
z)h+E%Ctz-CCsJIfS8H1i^?h1D^7!A;Hq)baS6fE&SikmcC<N|l16P9cf!1{_&<3;*
z=%DJL_USB;hg#DsR6f$`^T6_0t74(|iS}#yWZP5iaXJt3OuKuKzF+WM>zWHIhO|5P
zf#-#Guo^0cwRSYsz0@AoqVkpY#4Nx#>E5UGGiTibn*UsMuaQDmT^(g6xasO>7IoM0
zkHF%gduux|J#}55qRmV9F$Lwkb-!!S7a!eq3UK)9vJOxv)la9R0Ghup;X9B3-CMLE
z3e-KOw8bFZ_T2yt)~!8<$`GBy_kh`_tEWgqsE+#uD)#FvyJ1Y2PVfiI0o{3;R>F1m
zSD-0EcX|UbBX!BE02Za|T?e^n-70eZ#ppIoMx`lMmwXr!ak@C_Q@pO8z7>$5d-po9
z6Lr>U7_TH<{VI$_vTnHw5-GY*S71m|btAK2TAFUKA9Crs8u~QD5nZt@tjN%<`xzut
zS3u#cEL~PH^d8gAIs~w6-A&qx=jga*Xvj0^dT6}zb&G#PV}Z_0fyU#yL;kR$P{;oY
z&?4PGdtqU*?yrvlQ=<EZJWQp!A$qn?=mJ_$S*H8S9xUa$e)3M7)QwpTuv5C5k>IS*
z1;wHAw9fW*bfQw1NcY7V-OL=woz<Bh{RWsS-9~b})abMlNSxD^P~fdr*C>H$b-EsM
zb=K=L$a#HUH<H63T+l_eqVl<}A{}U+_5tLp_qKN?AE%FfiznK`?B`H+Mufeh1DMhF
zvp1tJarO;wLj0ip*xBGrwg1pW!*<Btu?4JY_RZuTJZxV}Q%Ab}NqXlWvA_8xtT<|~
zrg=BR-s~qDS^EWLfXT8yNtu(!?0Gt8o^AivF6hm%*HHRcuKoHCfSGT<U@2G%>|5xC
zdeZ(uAM~BFUt){Odi!K&n*Yw*=XHVgg1!7_=)Gt^`%Ca#vhVl>#x&SZ{}x@lZ2wpU
z(rEu_J7AjZdyYcB+1_#^<gVENc@oB4wckuAE%vkj0_HXQ3lkyGYCri7P}=PIBvf9v
zAM+;U+U<W{h`w~#UoNDy`%e2yv|#SCpCACc+rG9KXs!<X?xNDo;UFyn+#OQ4L(s!v
z#U6l0Ib8Y{pwSMKDWntQu$b2Ju?}72G>dbX{0U0&4&(oe@;bav`{YE2ALzVkvO~@p
zpkz3h(Fu=Chrb`v`OPc`TLl`AIas;jI%PXNw}cfr4q4|=%5`vE3QO}GI>{q;!Xb|~
z4`mLnK4>d<xI*6xt8vhl1MQr{;CCRk4jHujt#epOq4M(%?G$ml=+MQ3^OD0Ix&zxB
z7KX#Z>kd7%TQ{{kyiEaw4u|*GL(>h1XOza?<$%vZ;U(tqlH%u&9VSr@?GuMhZ5WcL
z4ia)_K698uuje6$7`oSAI9wt3!mxw85~Y_8rhg#rq~Ask5NG|uT5!7P^S*`^uKIo6
zXmisme*tkf>6dn*_a6EhimiL;@Bf#(qz}4+Mjw5W6FTFoA9@>h`{|Eg2aLb|mnF~?
zpnv=sN`ZPSO2yl&&xnP1u->m2Z6SIEC0Fj#|ML>1Q2iYSVEgqElfW6K?<a590ln*H
zU`FUoVGih8q`qz`B%<}-B%v`zZ$BM^$@<kh(Uzj0L&?5}^o!|+NYj5f8YEqRo03|N
z>f^~TkfG0~1pQ2X7o}HZ>342`!ejahJyc}t?W0hcqwg+*g}M5FW}q!k|5g!5zWy`Q
zFF-5M&;K2Ra9lsz4z)%45H%z!^nvuYKCOSd38hN?;7FK%MxRLU?z8%rbnc`|??v}T
zwf?>tD$nU-R|BP1e>M?qb^3QI(blM6NzTP4y*3Qc*Y*1-Wusl6J{sNa(A&&2!R}6d
zN)If(p|7I#c9*{N7UaA2-%@&TkA9C4FgNv!=!v_f-=u;3ZG9g-l)d^wN@3{JpX~tW
z9ewg1SP?X0?;s0R_&4_3J<#%&{|5XWcQ_2TxiY87cjv~O%tW0#Gy5t%{~pXln({oE
zjZP?eF^S<2_GbR3Imd_DM;F1D`SUyRYi5zma$4HwGRhQKn#aVE4<Mg$r2tU@<4iZr
zab{HvN`=e}%FZfcbgp12X2g{5U&8!h2DwsZ;~E%zf+^WV`_D4QodPc9%=!1gbCP*4
z2&GfZ|0v{F!AznkTMbjU{<YW4ZZfNAZ|lasmy1ew_PsGs=)qp6BO9J<n+F8E*sqFF
z@@8Ww!_J3Q()8fVe&vKpKelW(1pL{pdEg9SH{!dOCP^S0$)Qg{>@@-X-OG-mvjo9x
zCtOTsv8)nd5VHn$D|X*z9->cY0LE7|4xT2ny`senfxTa}do1jY6rE7X0FHkj-KKoW
zX~KQreDY-|cxLpa0(w?vF>1c^n+)YEZSTOmjX@O@|J|{JZbC;#a^-t5rh1HxFY`Jb
zw#sMbT*fG#WRzq6|25?-#-jP9=+ZbSeI;6K3xk}*0^M;z;t(Ftd&U3IdFOcZKsqdw
zU_SP9fFCsP-UhrxbKjpJ-Y(C&0+yTdgZD{)zkJ$kG(M7Bod@d+`D>q{<Z4?>9wi@J
zS32jn*Y;yNvv$BXX(vjtw&k0^nQXgvIbc$3>)wJDskR*yw?1U+L+<c2+x%dZ4%@ES
zgs!LCHeCYP5!)<Jh#$4R>kE=$yFQHG|2eiLzk;>MHq{s8r0twVK&!IV8DQyo+l}8r
z{)+9B*U)y=c2727T5P|mN9mev*;uG=wJlo*(r=r61eNz}E6$^I-*zRr7$4Y1??q|A
z_S#V>9JF2J0qBRepHcMvk*#Pn`&!ugD~z4VHXilQZHMT!HDvq7BQU?PEhMk?ux$@+
ze924OnfHMH%J$>8f#+mbUk>7Ix192rUF>24QS!7ao(2>zI}!QwyzQLbVYrXo{UM<E
z+AS2JwAXIIU65eAgkRCO5IdhsxI+8vJ~JJI-cY-&>p)AiE2IzlrrK4_pkcJTdkGR*
zb}v{Ae~w+-HW*W6_v>A7UbEvrKwGO_Jb_-f+Y|@VZl~A)a>MS@E(mnl?HdD4&+HN(
z;C69R<nU1Fr?93Ky}zR8I!L&}G?G4|5~nEo6n3X5Zc^CusA3$Q(9Bg>(6{T072Gn|
zbV^Y}QN3z~pE<_jf}(f|IGYt;>;va@MG!d|dldfJV7aR}v>tjNDn<stm?6ccL>edM
z_8Jgx<x+}7`6y?R$HZ5;$(L>dKV^42O!QZ_(T*ZO`IJt}2P)+opeacCn10>~pWr+K
zmSAPzO&AlRET`bYKBaRf+Cr7RZ$oas^7F4?Q<!pn1LO`U&)1?dQ8}L;@FXRF76Qr2
zPbmE*MR~jzLz$|a4}XFQSwA1&1WcN;kIu&*R%U3ynyws72RWj=M9Y<<%3sMjnW6lE
z9FUpH-^rPjrM%|^g~yZ&AHb$;<(gqA%vH{e0B4?ZLl@-om9zZN?E>Y7nP@w%O!EOL
zRBoinv`E=PA$n7>@^|WJiE{N9fGJg;rETO1rS%qQDpRhQ0M>G4U?eo1RGK%S@{}@&
zGIA@FDPb6r^UBT1=u?x@fnMir%8}j>=vG#}0SoUalPG~|P&uDY6%HxoUjzDu@~>ua
z4lA2!CG*mx+;bX@uarZ7fYphcL@O{q?k7v|_;bx^;0fSlpMWKho0$pFAa0lr7VqVr
z&^9B4J4uG_<CJt1E|i-|*;V_w*tH;G9A1F96x`zuka%tvB?cvM<Kj^|$a&JYXcIY8
z{(RIXah~mfN#-UTgcT{=m_d|MxjnBzVH#(diqc{3-y@Jn=b}EwI33}pr9u5sE|k)R
zGPv$ufM#+d{sPJ3c2onikb9&+e~UOBxid<+S~@gxg8Pj~H8*iNP--|YQ!`j=Ifv;G
ztm8`FMX8DNdkvt?+<N+`@>R|{9r7()EIp}R+{HIwOg9%u3%MTdn=X)>+_(o|xyAjn
zANJnny2#1V%U!Mp>EjY;0=UDy+X=b5+$sYE`Z+Hd6y4)C&ZbT9eQwGj6d!OEeHiWm
zZmu(62DuvYPe0<^Rzu=3_q_(!;0ZT+4oXkC+#f)maq;8P!{^+Wk74K#_Y=J@UU1=b
zTw|DPuA%G8c^-v^S6u5j43`t{xC(O4{K`XMapC`{ph?)3Z>3w;jh}c1jsE<MG0+si
zzYswpkpFljtO(*SIRY)1U$mYsI)C>GD);dUy30cO^R!V-;75@U>>wXTEQ$Q4YLt@r
zmVR(1^BbdqnZkcF6QxwXfLud|_`x<h`<liFXTki#{HDEVOy^%a1agFb?<$Nr%8$4O
z(=zyj>w%WZN8z=NT!!s&V9DmI=;v^9c<C*aa`{1;T=V$BSd{YliT_|k@$D3nJI<?V
zJ}l(D$eUTjH(f$oG5=DJN>d46nF8}m`L`*p<OCm1SG0_Ou?QxX^V{A<<w@RrG$iWz
z=d?dR&u?)=+eKb`404xvJ9_&x^4m3FY2s(TMCmR+Iu*m!&(EF+GQ>C25!M&{vrecV
z=FR9knJ@XJ%TW2s#9wiRgp=?{152HSlpkQei!lBc^tuX4npWKesS6ak3kq7|dI(dO
zqs>#u_#e=`gwb>=!CP?jhq#XraS$ax;Uo>7zhEv$Wq@#ta%utvn{NOeB&>fAZF_|;
z&H*}DFtt;NGDH}r_|iV1$%H<I3ZAr3-!DvxL@7*o+Y6uv1bf=*g$q}fqB26*KzDAW
zu!C|SQiZg5R2~vM=c6)BxUd$b!@>+VT#<CaoxY24L@-Q(c!uz*9C|Z_SLAZf5|)_g
zh|w{DX@C{kLOf-k<_HfigT%elK*?dp-Z}ISjLCjy0Y#a;CVaUXDw-$$ZVMG16C0}l
zGd$Us{Fg5$M;}3D@RT|0K@Ln2)9WgH$`e}AM@}&v16a<KmfKKYG3Dde!E$=a<F6?R
z=-iY@deU!BDWqk0>IX*}EnzDDZO#e8-`{TC2Kw)h-^1T6ZMLxDkNAH4-BCyjw4Iyw
z1AkXIC7n4jNgo5(nTfc8k_#iJoO&PTOEYl$GDgZf^k-se1sclCn~Tc*jOm9>=xYoU
zp9GXxrtu~9oYB)noXT7#N8cgliw=-9rjpK49cJ=A1ZXz%!wVWJ=6kv|ikYa5U@2kt
z&{JN@ymJj>bb{GMSrk>wR*F+sGqyD4*DwceK<*r)twdWRv)l9z(3+Tu));_hW;abx
zSD0XbRCX{`6wc{n&Qe(N1`}Qb`7S2o1N5+)G5G_uhnX-QX5VB+_Mz<-GlT5C&1}m=
z+XJTkDM|y(M0)fGndRi`dC2q~hxj9AY!?Q0nECG0u+C2W*v<x8RXDS|DO1sf{k0uv
zu51FO7`m~JB<RlGJdKhETTVMrPqv*7p?R@WR|CzP4fRK#eAxS`AinIBh2ZpKdCE2Q
zXS*nV8o(Z%0usn}M1Tab?(~Y=%RZTmQZPHpM2mzFcDEL2``B9)mk(t}Sc7Lj`(P%}
z!q`v$LfZkhWF=IDvv+5~&<OS(WfMlS6T)Cq6#IA)MlG6sKu)F@_WQ|@OJ-foz?s5^
zR-!V4-RKCEOg1MA0$Hr@Q?MLkzfGp8yO4dOAGJj=n64<>G9TC_?ET*%QOb6c_r8*~
z+l00=?9;vAJj<?m9i=LE$xet@vm$c#)UfaW1A%kwp&Vehu(t;wca80#^;RqU$6Cm>
zvCZUt?_huJhg=uyI)^gRy4gP3d-bq(@1qwt*(>C3yv6o@4D)ZZ4m73ovL3c*>tkOw
zq0LD&_g@HjioT>{TmhoGF;EyP>cQ`ONTNiQVkkT)`sf#^I4t^^QgqWrW`{wJh^pU)
z6-Pyyg(zi+X78b2X3G=_Pf%MdI^O{mC88e~T#-`IA8(^GCqzFXhL4X}9Mz$%T(m}j
z`ctCG^!Be19VB1GX;IV(kV=scg#gcpI{yOpSy6ij#2ZA(7hy$<DC|w3bc(z}(RN$Z
zZ$#yN(L)N7n4XB<wgC1^(Udii@DRuB!?1aZCorh=5|3YilDF8U9x8mq7PK4p72i|C
zUO(}jMJOE*fBg~z6fS<7P8&pse|-v+Nb%lvAW`DU6gP?%Kch1XG2)iZus%+lNz-b)
zIJgNY2_~^Sr9vMR&v^!tD2}GgyCm@(o^Bzrk}?mDi95+vbzJO3`8Z`_>v^#0jQH+B
z$k&Oty#>(A;>&cCUlTu-Lg0pYJe?2d6F;UHz#XyZIt1>D>+hk|FMflzR`<jUjOgHf
zu_=<imi0iqV<%t+#FpPf{-rqXD_HSLeCh>Qog@yiFwI%wN7<<^l9XM*c9qnmL%<C`
z6a`Rs$*6Sn-V+~KMw^!;gQhTVNj`#T5+BKkw?KR)izr;?C%Ny0Hh)QDAv6R?mYFEE
zF-$Vx3!Vd#;Tn{}C3ckHA0hD|gCixy!8DeV6eo~qNhPfaV<o#NmoiQ=doy6-B_DaA
zhY6C?<exYwS-l6wB;u3?P?99mX%l!<a+wY*WJp5EeU>S?@fq5(a2(SFv}2NuwjkLO
zb2(JxNc?jElPhsag2DNc8rp6ZNS=L&(s9Xl3Mv&!7SOu3NV1G>fnrHk0MJS#Ykxvz
zDZWJqlrxfG2Aa-Fk}0{oN>WFj^=e6oFGvl3K^^2AKKw+PFtw7}7Vy;JH+pdm>m?H@
zEO|jPbOWV}l3i~>#U;sA$_Q(asOZf5Wy#W0C^bs5PQdIYNytLj+bo$w(UmLsg#cjp
zAm{>eQ?h0%z-~!$2f%q-;#P#d^hz?_(bgxC*og4_-IX*gfPBAX`~k4ulPo_Bp8JxW
zbbCFJoV*Oy0m&eJ)Zvw+#~qbUX5rp2&Dl(R7N)tFb?gJStJ&wf(dK4$`eTT@n~e*D
zg`Q@flw#y%_Q4ZCdz*1zpyXr5U4fjhne07an*7Xm8c_5%n<;`sgqh3|Fp*|Xv{r~R
z^P)9mv{@uQhB0QDi%^O++eH57IJ3)?A|G$oz84lAG}~|r*okI?W+)|@@w5+4HnaI2
zdQ;4zlR#3<`uZ@;hs?r4A(v(rPzIKhCbN&0;KH6VbD{v-IkQQpV1Ap~x<OQ4H~Wd!
zAH!x}UWVRO^H55AtT1PPho;l!{|iLrHS_fisJw3eJQ(7==3%2?+5_`miqt+e|E&OE
z&&=J(x8!XRN8Uys3tNhI@3WYe4fU}Wre>M}vMd~)Kw+`PsFNTS7Mr!Gyk-&I3`-wa
z=nn$aQ+niQwC$6o(2^iQDwD&COsTR2R^&=+9l%m0?W4o$)zVKsf}F4HT^^MIvXI><
z1<J-#R%?*#0PS3ZWvAYSy&<y4rV=!U%D&kI!TmCuXRtd$w#5~!kuvcp@I=XW-UmyJ
zY<dJPQ>-k&9tsc2^z<rCl)XO+a!InfP>@uas};l#%Z_hG+fmuL7Kmrbv@~O7%hJC`
zTaGN4l6&%G4`QJqU$*iIIUx#UapcB6F7u>Eyhau=3ZzzcrU8R+UUt$JZI@(*La4Yb
z8%fK|CRqb{u&&6CeFd~@GG!wwJ7jksg2lzMV<zl%vz%9tl80sQFVO2{Id?mTJHT?A
zBRGRBBl1A@Sth(sCn5G*);-0Tgj?1nLt&Jq=Tlk$;vcVe#NY2$P;_WnIHm3_pGW79
zzjycu|6g&RoJ>D#kpODt{;Bx?s`=@tU+q!`qkjCT2Ue`vydG-TmYC!3PpK5IT=&5!
z{QX&&2#xCv1vLNuvQdftZmgz2pfUSz^mfOAsrdiS=V5@}wTr&V>gf9=K=*{x^6H=8
zr{Mqp_DTU{vZ3*GX8t5cnG4fRm)ezCF%p9Q%&sOF8^A22*MA`6O4*S?Ono#+ICJd-
zutYHBrWHVsWS+s%D#>6R|Akrkj3xQpPcX4n=+qg8u|s7&Gc$s=^fWBH-@@NmHn#<;
z<JhEA0E}mc$QPf$>Z76TAp2Vz3{7PV7ohSGJ8uAZM_G9*bY`%{<tSycQz>~e*TkwV
zP|Rb$qDXu`yWJP0fc=B=LQB}6Lm^ShMvaGx6Rez4jVjn>e?a|d_9CTLRk9l{g0qI5
z?hU=?*s*pHxWIlyx5q{HXZlLoB{qugzy|h~0G2Ck=v<Vpvis?aGA-<^#gsGG&VFEq
zVh8)2Qf52Z>Ej`PgZ<{ebuVjI1--Y~Pu~W1FS~U=x_ys*vjUY5*<Zur?&8w~d&WVN
zljtnH$_AyALojfUWC@5g{WoGSnUXYczhc5@Je=5z6zFhf9Vj)&h5cYWWL;VNBEY+`
zx+5U&tR06o4|WN8V?Eikv_bV^3ury<%`X0LUS*e%-_n=;^*Z^p{aD`xQ0mXBX+{iS
zH$8;HK=$k#;0b4s521GvaG;|tl090AwiI?!KQtX;{aR%IXC)s)UvgNs{73LE_oK)4
z`>EX!U-8NUw)`-O_UJ3mdBTKMqkDj`y5JEwe_VwCxJk0+J&J3s{mumfKaH4x{;j(}
z(Wsvj8UVU}QUL0I5!XUs!|UWt**G*A5Wk-Cg47@5KZmmIXDCj+(~;)FU3L^kbYsHl
zjDkC}Fa&iT%#Ov>C+5*yj7boae;Mq1nHB*CnSz=0Hz5(pT%xq*C}vR~Opaz&mcxWt
zX7>(MCNSNf0VauQwgX9J_6?!(Ftdpk+eev=ltEd~Y@v7Td8Ul=D=sjBP0)0aS^Wfh
zFEJ5YQEFzAXF<G`@uqE4CleY4(raSglcDhubDMG~o-^HT;2CCmD9P&;lQJ9FxZGm_
z6UzpNpfZmQN8IB79;esoje49pFa<J&%(87TtB4Vc(Sc&dOM|u&X3Z3kQsxaCRGwf2
zI&EIYG|@h~idm^8S7tS{wF>ez%!hPyoMX;X6swl`kSgn#x7uM{JyS|4CFhw++V|gJ
z=FY~5bukN;qJ&)?<=o&rHwAU>F$ZXjpE6x<pzRs+^9_Kxupb_W6|U@BTD`lmo9M)d
zKifeW!lnS0TMNB`>`OW%a)90YD_FzX=(!l&2sW=3<RH8H0MsY4qiOSz#O6K#OETN>
zpBImPGy!dy>=zUZJI-d^#HbdsD@viMh)u49crojN?E;?rcREp7$xfkd;2C!QA5eSN
z#HPkT@B({~+~614Z^uF668rCm=wSm}LOYpO)`C8G*2eNj&~}}Dm+sVdcIr#Cb+Fa6
z_333NeUG+2_E(w@?y#rH19X=?_8mw+`<U_v@3HLvz;d76Op&bzZ1*0B53u+&1&kVG
z%gK%QkbQ#^c^<J_Xq+Fj(`b%+!Uo)h{8RSaR&?zddw`bD&)HFpC=Ic0ltTJ~eYyr{
z!|bR-X!8?|>4iXqC}cF$$BTL?vm{kiPsU`4LJxqP7A0>)<rUFp6S+O^ivHY*T4!;M
z5unlHblT}=h^=S9m@=`Jc5d}z*|(@{6G#0G!9nqc-5^8ao5%nEE8sl5tFZYhA}Pcs
z`IOe<?UL8FV&rZ}EaQOGBT@VdmR`y573l28Plf=(G$5H91lA`KhYc|Lxy0}mO0Oid
zZNchhcJrgx&@ueu%qflH`}=eU{Gjhd<Eq!~0Q2J%T1c<Gk&o72-`$46*gV1>e+^Nz
zFEH+E#s7EI3BcU>?kq?-G4E1xi8CXmBh%iDsg9DPeVB>lv<YT9wgEqcIbVZH%xzsL
zMKNbqqb-psw}fC4bDiegBTO3kf{!wjCxJ7AIo*b~d}iYl7*oJ(q^a>Z;}Hh&LT2eJ
zh!-){Ll7utrUk&35+-~)j45S8Onbm{g3+1*w2XOh4)W#9>N1d%%=|Y%PBFKB1a<{8
zVjkpAGuD(<S;<VNIOQ3}lD_tFmKh=+auw4x8>E_PVL@t`9A{vjW3K#*A*f|?!(l}o
zGnssK^-L`-z|S)US82Mtz_d^n%|&KG3yitS1VmxzT9|f9+quTv(nC`#b7?1CSEjuW
zR$ONu9|g-zrfdwbZ!vDaf#o*yS181Lnb#9BBz?@5-vNDx`D6r8?lSO&(n}(dUJ{w?
z&5Z!dgGYpZkEwv2+y<CJ_IvW67qg>-!CJ;@Rs-e~oB1<3Q^~&3Nj+p|!^?)r`kN?d
zs%JG1z;cP*^fLsmvfdtGxxrqebF5Ax|34@r0{?gq>T49cY!65@>rn#H7<ME9#j+dh
z$rl*Mu9^=k<5`0X3`t-=r>NsW)-i1MBh1jf^MISe4*mtsR5qm<EQi=7l(3t|-lVno
zVRpA23`u9Fk{{v-yEYG;N7-~*@nx_tRe;W9XYEBPi~a7uZ6iBG*E^q;uLEZpJ2e?7
z<?P$!#;s!Cbb_JP>{D9v)Ub<9x4?6bJvAQ^m)U=}LwzIr!5e67V*k!VshM4U8iMWY
z{m;;~4z`?*0(7zyzk%EhHW=T(fx~9l1p?iy^Gvk$uxkvEyUA+nVAC!3ueGr7Hv8%~
zpuk^4{@*_KkTt;WuoG+O9dwuNoCMZ>Hj>VE-D73xAWztLX$AX~b<2do&sdIfO`o%C
z$YV0Z{_`A_FWCL(z%tD4ngjBZbqhzEhiKuO7%orI8}wO-KvBYN$OVb~)}n(4M0;Nc
zOSq`#7E1A=KplfSBtdjROT#U?5DTLYiw0<IoGmg?I3-6U>IZAF=vp91iD)``{!WYZ
z%@C**B~AtQ8PSaxaGn>bMuJ=r*^&?Hq9~*ZHeC`$(5tgS)YFQ#%c8-VXloSxz7M7~
ziCpom2ot_9nnf4ris*(rc&>_4zlQlOqDi#4xhDGjKH6GElY>CoM7wE$c3rfXrtx;s
zo)bXp5OqmlT9;^44ovG7IncJTNA&0n)ZY|snT!7RikfLf)F+z9qV0~TmL{CLqK)Yg
zH}#7G?}I)NjiN(v1EP&T0eet%lA;B}qIh3mJBec`)zw*?P6r=d!~?|QDqgn-ZEoV9
z#(~pa>_P4fFL4hCP2S=cOJKd9`1*Y)^cR0x3eEuWS9AvkiU;UX2@+4-jkZH3u^G8M
zvc&-vkSG>EIEju{h(FB$&pGkvLR9vNS5v;kOUc?kSm9;Hj0KCI*;dM|2rw(E1k3;H
z<x2dbtk&>3=Nk?Rp`(I7aD%y7xuh&2h?T(wQgBB!MG=Q#5oMEM5k-dr1(Fm?Jpyi+
znj)^GgGP$`Qij?smr6x*gA~)Nsj1!PCGY(Yx&t%MyzhC}^ZVxP-?vOwT!QT~IeQO`
zmdhUbpjODH9Qa)+kJC2&DmmybY_5^<T@deD`7Nzht&^6cZDDkStZPNl$ns)vD`h8V
z7~L$p)5NPv>Tf}Di!>fX+S}wonpbR>Y$c5DkP55ye{~^N6NJat>R^3BU=j2qB0J#w
z#EwS9ImwCcKZ;yG7&4Q~>0o!9^#Sa}Tbx#cm^v{HL_##(36ysIZ77%<Ux$hG8}%s7
zc(n|lnN`=}DeGJwK4(v-t;&2JYM{F3kEzrDn1{t8hlM=Z5mpxQc9nn<zW+9YU(8?A
zkXR|7PaS6&kE9=XIX_!ZE#wMrqQ|MO<mYMEYCC^g2isP@WdW>x#r<i_e2A~6`@>K0
zYMNrz^M_ur_C2rJhZuk4Q$~Zj%6I;XV6c?Y4CW&q)CM+l#YAs7TrAGhj$wr;T=3t6
zBffOxs02M!0qid3-rmqH<v%-sD&skHvvN7_Gyt%I|KSUt>v+=ul&$A`sl(aAOUsbK
zR?c_A**0#jX^H$d+H$DjR|kXI!>>f50`_w6CNK~2Wv_xd%&YDpISfOoi#WyG{)6tM
z`hl;YwX}1b2f^B99<mM86>gsi7Y#h68W~*Wqrzckvq+~?HdSIPJ&0<HSVwoWZ57?m
zKysTHPP3WqVuvqahghWt>=Y;H9N*XC$_^-87R7y_zFKP^3|OP>N~9CN71}3f;9{+I
zTf*;W+R%Qexpmr!ASkZa%6mg`gH}wJ^5<GfIz%>VrUA%slU7!Ucq_Fs+G1IxE9`}`
z65Ye&fW^8h>R3O~ZOTESpX%_Bg$11n11g)Py8Tfwy-XLdpJqr(mrlo!m+NNJremq@
z_FZU{>7vHNZ@I3S#ufAA?l8(;{xSo8x5{JPKvm0L)ZOluk<L)4kpo{KiCXDb4Uv7)
zjpjska>;B+9+a2pW`IZ1x(brTw$r!3eU<I~&R|-O*^aIQdD1qY9`5tKt!L27G2d-r
zXb+2bMAt77*Kgt&_1_Q0m&*~*6JbM3Nd;Qy&(!nd-*I~g90sOTqeg}fal!XtX1b|k
zcxO5qK4R7k_!z0LhKW(}+2D_U?gHasiIxpep6EOlMkjUu6UCA7v~f52qh@@MGFO5>
z<<3w9U`!eZwP}^!_&&W4?bw@LCnJIMs?Q;lQ%s}IIb8#wHIHYxqIf=crQWH4_orR1
zLawLzRS|DL2})JG^f2VV;E|T2klD*$KMSXIyaTPK9Ocy&V1C25bO4;?x2S&3^G|7(
zc!@8i<=5+ccWY3;@(uyW^dZmx8hX$9u8t_n6L&nIS0rrXUXD>5KTJjF!R@-BCf?gg
z6UvO6v}W=<@0d*kw#PiPH_ZIOx4i?S&-nam=>N$h=+>NE;WQM?JQ30vlKJAmDVQn{
z^?C4AC_HPC=%>QN3d>7GO*<%T5xPWBUx|m;UJkD7#RyteJ1<I?z{Ca7>lzGR6eAr`
zA3s_|;S^~7Bzn*$-VLD*hUiW4!V^@Z*m(wVHHq4m6AI#Unl3ksA{#h;A_fjc3Qxtt
z#R&EztrJ6B3$@*QVfz!UTNaXBqE!^b#Zv8!K`+~Ar?WKJLc2@P(fBv-hEc8swb#D@
zJ|FR<<uLI(A4uykkNFdSF!RLesV!+|Ti~-;JRJzTABzPS;d-g~<_OF$!>AEuN;F*n
zbG2B$5bA4$4?V4{LR3&atrd6gL$Xpl^Mm`%;`Tr&REfB?h}`mp2+<(3ON7wa_bX9L
zoyI<K`cHT|D*Di=hGQaOF6yXWG&AU*7P}lFc~NN8@nSUI0Bb)9M_OM0S#+T}{UzbL
z4P}>woCLiq;#n@Lu|XXF0qR$UA6@y^#NH%icHbiAOhuv(ME8?`e~Xy;i1eZG{tSwb
z#Bo<JAB*l;5Pd36%t2~@h{JBs&(osmd`iA%><N)I+AP}N-K_m`7s2e;4$@)%b6Wg!
z7`v<;ryk*s){Q2054EV#D0{BCeh0~UI?Iu@u%>izA#kx-_tr2_`*gOaAX=~M)rh#S
z>FVg%|L?jO7g$?h6Ny&KW~t4ucR-cftXzti*4o?|iF`NO<mG_5LI%?^$tw9Ctt_vW
zPP96|MhXGFO)`{5CYxnAEr?giW(zHsY?Wqe8Ft8^OQ3ek2NMy6RX&)Cy4)kD6eEf+
zWj!?{wQ`vkLfa=}Zo+7tOrU+s1G15><wJ5^H>e+$hn%2yMCvDic|!I&50O){8!dBw
zD+f)4UcKx*AMt)CAFRi9)zW?qzO^1TKI9-x#zX38Y8JZw73dFL76Hz%VIL!g;ePZB
z9<i(fx+5cQpmfwL|AN-&IXhrG?5ZtF$DDtG+`~KfLzH9p(Q@IqHy0tQ_ur(A?D0nm
zAUPr9A}mDI)9~Ihao#kTo^<2}iYIS!K^;ZOwlFlMxCtEN;raNC?(qRcP3!YvC?@_U
zOvL^|amPi{I3V6!f$vkZM}VK;*dCJ88hr76dVV=d6LaWNO1fJLe)5G?;G`6cfS1(D
zMkG07V99mFl6L<w2y?gx3bGE-DU{hi4FdlIUNRJk6!L5SFjB|uCEAqmR~XaScBwLi
zm@~jVAT>2H!DLKNNJ%!kj|m^%&nqw^IyNLIxUVra)jcpJIXyNx-RvH0N=!&K$GWE`
zX2d5zQW-Q6?3QFSrI>xZqdfc4pO=SMKMz08ex5#FKJMu$DT!ufl%ivRJH)0YB*(J<
zgEO^RC;I>0StaU3H~)lWQ({KU-<^~dHJDwis?%gAYuiI&cpvqBoODzho;q|;FNWw^
zsnvxJ_Ucl#?4m|3u<fqq>g{Z;b@#;m)7It#TDYq!sdmt*ra=4d1-T6x-a2b;gN^Uv
zf-`9nZ(F=uS<j@kKGacFEwZ;)*AI$b1xt!rTbC5sWwlY(z4jec$~|FcbzN>3AEtI5
z&<0sgHrjQaU~L;@KQnl+`&e^qn%UiCOiN5Ly9cG1GLl-Zm$3K4hq#+lji%VB^jKq(
zdtktbK7q!xn5f|?F&T-mQDai#(zA?dvF<^!(HZef4Z33Es_Noezov2nguV5LBKvnA
zw;wVlIBHzLu(82z13X$@V+$PdykW-=9VSVY*<h<zwT*VI)T&0i-pa|>zN59S(4i^Y
z#n02LkEf4^M^86T&%XWodb;7l^z!ia^s*imZ6ci9JWbI?A7hM<(Zj=cfTx$y!`sVu
zfXU0$-{cwX<>TX9;P2c9@3vNdXZ_p3mi_qE2n>>%2{9(HL+39X81p7<#~6B7CY%^s
zN9e-Xw}f38!)hZF2F7rnnu*sK!@)HsdNPLXA13-RhIM)-aD)omyiD|CYzZL->-B_h
zF@~dUOuU2VgJMUBiFX;p784TzjJ-n`h+i^cFk?99$;4pB&^j;?%GfzVwAwT5fuk5(
zKp4gtnn)(X8N<N}CdM&#fe^QdJRrp6(g7`ln8cU|Atv6TghuPE$@)QU`AoGZNk5Y3
zs@BPXLNx&())-V}vVMfvXi!fHw;NPw3b4kY%2M=4MV&!Kr-D9iP&*0F8<dy<ykbyc
zgtrW8E#W<bx<5moDIOctv^0GtXR0AhpT%3L31&Fct4)8w6M(4ct3uOB_ia^1c<)`+
z2;@DKUj~Gys3L+wb%CIV>Y3R>WdlUbKh?=hi25s+EO4i)1cE}f2OzcwE4!JnSM#2V
z0CEqtX(pu@p`QLlhGc`>*rdv`TfE&S@^o)Ca8`@OqFFG-)CGc6)pIrqj|Zw*vs)~k
zAo5nQ>XZWq8waatK=PXd_PtPLHwR>{nlJ~tZfX-jp?U%k_r|KwxhQl~rE|fZscsXr
zQhpW`t{JaBvY@a;U9jkT^YO|iSN|$^Ry}j|Z`d4ZBUpqQOB`2~4Gxb{6$H-e1VB8K
g>VB^Nb)@O?0l5Au0O0IAMbEJD^S>8Hel4&602mq*%K!iX

delta 128617
zcmY(r2V51$_ddLP@7=rg_JSq$5_|7G_TGEcn8cdcV@uRr5euTC2ns4quz(H3f(Y19
ztSE}8C`~~?#R4h{D8A3RNxr}LpHJM`Idh)poSEI7a%L|6YkIDB>$$BaTX4MAuY%fg
zkM-UlRCo9%vCJajSU$%r76My~%o1T`63;9Z-dAUs6+#~5D+SkeTIO%zcZbM0*cvVZ
z!?2|{S%zih=`y2Y$6I+u&2A1*F&eh0vB+@jvI36LvTugU4A1Vnu3-c=J3wSaw)7~=
zNbLJ1EF-g(LuE!`+dHaqjE?o$ATfIO!b&w`V0%9i7$X}sO~shl_)?BBvqvvUjD`Jk
zql&Szx@?}Yv3JvW#?JnEQD9uy5&0UX65H>ImZ{8Ix^YYu)?+=#RAsMEWSQ^S2{*M&
zH8$monyJn<GiaC^?8wPHQ<K$=W0_iPTDU{Q)MgXLvrHYf`!y|7mzDa8Og%R0wu-6G
zKCLY<-?KyCh)e_a11B*JSp#a>h&}L^$TVi_&J>s?Y^XtCnzD^@1*RFhs4LGjXVXt=
znHFpxS<AF!2iM}5R_uraGSixU0Jb*lTNjpT%f8K(nRcwZpmi|q*^Y%g(}8_ApJh6-
zs$p8D6Wi}6iRsMNT(4%juw_TpOjq`6PYu(J-Ky3y-C39RDy9e9atF`+z&`9QGd)?=
zZ7tJ_T{oL&db0;MshK`()=Pou%a+{KF#XsDArjM{9VDrk0j#w`%?xCVvt?!wd;F4?
zaSUd=7HF6u?4!mqGn8%eGs_HTyXB~v5qOT;{5CQpdi^Fbnm~0UhGE3DYt#(axY8UI
zgJPj+O+0NC*8$IsQ}KVt2#nZa3eRvuDs3SJ4HvD#V_&)pqG6STog#i-TNT3zT<dcJ
z5?<3XlV_@FxY_d-L!U3zfkIVBX0(+oQ=u;<;3CRnSVr5#;!5|Hcito98sjUca*Q8)
zMh%}-E4s?eE;b(bHB~NkC1$r%zFHN0T444#<-syrNz3^EqtD9g00{U8z{*E&tC_%m
z5Ujk+`<na%d%{~%W_1iW#WDL?O$n^pH=kjx986WbRx@YWB8V7Oi>GQPmMz4+M)m7-
zhKY0D3#!-Nhn42_qkh&h7oC#2s*wO(a^5#k_4d;;3C{Z_DnsOUon3b>Ps1cSB^^{7
zz3b?j>x=Jbn49c)7#yzZb;f(D&dz3eFVi_30ha~l4y(p%%-D^eRJX{bgj|LxRgoKv
zszCzBlsWG;%Ge(UGv&^EL3NDNFke*Uw!)apZ>gBCDz!Jj_9j;~)3pE&=%Qh+YyPPh
z5#G=^>!pkwI+D5RycbkAJ@NhDa%L3Op$P($<h(bkjxH6M+s=EdYF-M<+;QGlQk{Z4
z*?Iq+YANJ*o%c0W@sQth-q%(A4S9<5z5!$I_Z!dL*Qg)Cv&#G&c+1Clz&m!pJ&|E*
zjq2kV&9HcBH0*1ZscjURiRgG3P4687(}La;M$@7J%e10fR<ph@&$P+Ltw!^5GRL$f
zsi4{9#xU)j@07+1UwcQol{8gv%1mdvl{IrO;A5j(MbpJ9GTrG`r<qk%W`0Oe&1M+A
zX2NF;(~HCgM$8*8GeRGg7o4oqKoA&p7OR6Fj2{13|GEc$R59uYEJ~^2No3(Vv&?0d
z1Rb1$IjDhJ6{}{{m)XYTuF7jMQ)Q2Lx}g%A<NeW4&z!SL!>B{phNGQ@%a|%(y_*;-
zIh^9{Y~%mLE`g}eYA5q|PG$w&wA!h)n*IKNS`|$>W}#E7iBs#B|7k5`>;0>x9&-o&
zEM%R{r}A2$_BKnDA41A1uQ}=#4s9P2%>G9(i>XSUn<!Ur=~&cxEGv<O{`;pXEN+*m
z-z0%M{;~eyWcQ@EU~0r(@NR8t#rF4}VXDs-d2cawa!kJ?GuKJ?pPH<|(>G8}uGjsq
z9@Y~pStjQHR097~iK+8HmHCfFCX`hEY3aiMR6_r)=X^uMJc$YYx0bUE-x;Al6n<+_
z$!QHTya$`>7^x|?H2LqrG)(Yzn5&rG;#CZr$G7@V+^CNCVe?SOy(F1of8qZnoaSss
z<oo@jHr3gT$j`vA0Sl9;8A;#$pZs{;sE=x98vie;u4^@snf`BXfzFaHGc*3p&0%Z>
z)mf&WGfNemfq$&OcD9T*9pnACrG|s*!uI2T`-g0jlX}4aLp|{Sp&s;q)Q1l8Otb${
z4|h^~6Ei&lwi)04zXmp@MW~occz+pYv{UQ)|Fj&H_}2fuO!LkIR*CQVk1GopTj_D0
zQT@+AZzuHq|DY<q?f(pXtzelV=hxH4sZ|*t(LZh!Y5&iSy6@D?v;Ut~cZIS3tM*L$
zKQdc{cZ8L`scY7HxW2KrV%@xJ*{seFiS^UA{LgCR=^xN`o3&NQVfyc%m(V!poxuF*
zG}9kK*1rY5^nV`lpW06URBn#0dbY%@(EeLhXRELLH@BFn<TxfU%hi=i9|+7`btSV4
z$NZvZPMoyW;=Y?Vfn(IwBxhr)y;U-2{oxlaqpqrO_8Q(rRjSyT3S?{R)S{k~5~}0#
zR5(tX;$5q1XI1MN-czc&u)VyOR;{6|+#@p@^+DFg)yVeVTXi0L!`t{>d-kb!|L<Bj
z-u}We8mA47hCwIGF?Y0DTwl0g7-tG{>AvzSbg@i!A}M%G#!$`dW@KECej)we-;++H
zmcunOjjkzf60U20CwZMC7}J^IiKPGI6}rA#K-ZLm#MaNTn3C3SNmSrR_XGP8;A$qO
z4~$17$@8`n-Tp?HF)$xwGEnOWDt&;Dm}8Pzx<7i6+*;L-^tT)(hE4H=`X24VF+rb5
z(qb;%D<|n*?nT%^RU8DnJ&Rzwcar%fndEhkZ)E0eCaGFks=awBNp3nw^IQ*-cweU$
z^4vrW1=*z8>OSc#>_(EU1L^+iJu)f%LHdsO#9!Q$O4AR}y>B~>14-ZCNNHy<6;yO5
z^W%pR-Sto8W21Fc@7OJLO?*p|E_F%s;wsYF(3*()r%)+#j(A*Kky|xNsI+1b-EUt>
zEio^KH0}AsKXd|B<Mu4f-8rUr6H@J4nXZNVNHrpbeE(q#(e3X@_t7J%24NU;Ii_nE
z$)CI;SBjpH{@b}EpSP9VYJ8RCBMV9A4@@69rq4*aM&XO(nE1tX-_+u44@{>y2lJ&C
zd9?EbnfVe#6t_}Isq0=+3U{`|xfujb+)R?wi>R(kw~!<)jx;|WBZjf#$cYEhBxyF3
z+>+jtMD2XT-i6S8^VY-=ah_a!;H-wD<Tx1)Z%%ZsZHUOrOf3=WY~E_i>3-^Dx{fa+
zP4;iP&viPws0z`Ia3N!-Z;<QDQ|VrLKrZGwt1%D#700ZdO6ILrvQjybc-HMCO&`Yz
zDjwr}(XRQCUqQ)q&BinwZ@%+GYV<SJ=|(Nme33))lRl(V&5z7<wUOao&Ih++5tYvF
zKrW6tL#1a=(o;A0CzFdXQRSGQo%OzDBb{a=97Lq}QN{yf4#(uwC8b9JblqX5YhEPj
z#9yM)%Ju2quz*Otov-aM3+YV!jSP?2PIa0wi;T_rn<N_=5b9E8lGL(Msdf!vmk*;V
zO(=7||6cDXla6Hp#{|43y56k_wo4?yvpGa0KOy<Tm!x^e*;{OP8a`A^I&tesp7)&0
z4DIY}6@et4$%M*$MlE;Thf4o!M$9f(iPH<cHQxUR3aKvNLN%+ELIs;K2fz|HnHu)#
zC%XSxBnp>RBw6K42HroR``ga$rRp8R-uEZX_#f$h+6O8%Mv%z~)kvPanXIh-ljL8T
zl9lV9QDFyDj6nwL7CT*Y(fQ*MY@loGZUVfvko@a;GXL56EPG--$uXvnRFCqt)Miud
zWYTpiNp^bB{mvlL3BZI3-^fmKLVQdnU+IW>U_6z^#*?O_=o%R)8%b9y)|nhL=~q$;
zOdykuUl2vAH(lMb3Gj!NbS?*z;TSvJZ*U<;+utBb&n&v%7eUw*iLO6ks>?A4ur$M1
z;7+9t7E^m%!h8;`<-lST-R%fcy*P>dO4&+)&-F;Do>S?s4Wu&)(FJ@keaSi15-RN&
zM%T;9<lJ<Dbd2f5V0}yX@2-<c-zLOX{ufm*D~055oo_&I6S1)yo&EXzhNLv4F<q+<
zAiAM_sjkz<6RheylFxB=wC`3B>EO{M3B)Q1!^{UF>K07*!xj<h>0~lfbcL`BdXkIV
zzta8FE>z>1Zd8Fz{-poIuOjvTU+a=dW+gS?=ru&Q<|q*@?nOj(+(`0+^Mi>*T!v%z
z9wqQED+slr0g=v+bQ<VLSA&6cd=JqzcMx62pCV05H)6}nCG+_%q}gu*mip+`OQ|5n
z`CYc_NQUc8qFP3LrTdjLs7W(E5bUzEf7HGpaO+SaO*~Dm+>R#w>*uJhbI(!fk~lK#
z?oaZG6~x28AuFtgDw*GdIG@gizJn=ULIB$o0@QU5nkB~x5Wj`My+6|Rm_XD`W|I?-
z?-J3=NrYO5r4q-q;fb{EWJ0}JLK4=GP<`7{+mvByhEX(*uD$A#yry$xIk}#A9EKl=
zdfOGc-ti&>OD|A?b~N2T>_peH)dU{6j^rO_6Gieoq8{w**E}#ML<FWfNuIW+`(nEW
z*CtB^Tzlb>X_?qaa?8h8jr-=OC0vtTcw7q|qp04~1E?|iT?7d4LIyrMry=3a_n;Zp
z-H0A#Q!RhbBqvsWBk<DCL@GNw+M*)5A8)5?H-R+E5K}@|W+u%y^Qans)u4y<QbkvF
zh8FU!1r7pydrJna-AVP=pUKB%!^!L2Ey+`t-lY0|H?`2IVzdmizYFPv?W1ejuk;{<
zi)7%kbH?|36>2TUol4^ulf0k{VVBgP>k3S2w9NKGa-!id*?~+ECXHI=+E6mtJCtBO
z(LZaMF%QWtU1zE>>wFLD>?i80&UdAc^PRuoN6o%50&4}><SIA%9d)noronw9>mO*<
zUT^-y{pf~asOXrKGL(+Jvk~{>UTy<&yu)uC{GYI+7JQqSNw4CsPuu~Ux$`ZG7c`+K
zylkinwQ#hl3yB-MtPk3CGyD1)lAY`;ns4~Bn?AuwKlb(w<aV*rN+i44w|H*c9(K}X
z7!6=MeT3CO)~5?<9>iuI06duWaSVjvz3iSesD`kqKf%{f*0Kfoee7BV!u{+>Be)N+
z+ue~IWUtY%7sh&y23t6Lza6*_v0VlMaG15OhUZ7v(=Wh%l+B}F`xq-xKOezPJqKYV
z+YJ$1?l?P>2EZux9ffbW6YM1gg(ul^A8?;yFXzGTX*PjoY0<3e7VMs3=kEkt47(~4
zxwGt(8!#Ws?mh%~9Gh|+!g#iv`qy*pl3+M<o}K*-EEm`%)Dc}|!y}-1iG3ab^9gLs
zF(h}{;W`%m-#s><E9|DQucx80@3S=mz@5tKE(7s^-FgL{rm@9S!2Ou@zXISB_C57$
z>FkJRNS?ASieWH^&9#E%Ir|ck7cQS&PlHJTyRRmMh3q{n`nlKa92F|@maX~$WbfF<
z49$Ow*n)XbEoMs@6uxIK=ELp>HVbiN?ju`12xTQ~-HAYaVkeg%_nGb69FCT;bv}c;
zoXz`;ihg0gUPRe9b~rs>S5@bFC|jdiy#pR@Qn_;fzMu8$QYX?Tb08q|dZEj8aPw=$
z!qNimaF|_~K(Fkg+C3P!i~noaZ3*?}+n1q&Eo>pUwrqhOhHDjCAI4hOr12@3U5u5E
zQ(eP1#@nR*o~GS=avcx~FOEYZmhuR*5Miw<G-x&0KL8)08#|9xqy5*io6yH=-P!od
zsMbdI)%WOzJlIZ%(r}yDyvF!A16k!~um!OJ2>qiSLI=RDuWYC5AX}$0(Oc`Gnmz=+
z?@&FwjodC(zkSFBsit|M0U}h!`M{l5m2U#>rfR}hEI7#>!wttW6jV9109v)?{Rq0|
z(>9=>>tPX^qe>_)Ja_9KxNc^jOK{-;>pBa%acq$*DtVi2d=_!x5A67$f15zk{0c&2
zr=_S-<HPq*%_fa8JZPJ`twv|kZ2202Q8lN)vbM#MUZ|O)<@)F7cUlcFqMcg5$%WHx
znuelr+pa_agKHN?^7aFd<7sv{bp_XsN_|K=jY)?2UZo!Ja$qv{F}RTiSLjcUYXF^D
z9)rNM@aN_zUEa$Kxhwn72bFVYZGVE>o8`ZO#Fy=D#8v~o`#=TBQ8rx<($j3=IJkX=
zb$TDeI^93ZI{lAjofU{<oi&JO$!qN;)>)GTmTKZ`R>^@a0nYXz6HQS$DG%4G(lHpU
z)h8aF*6V<vIrsge8feF+jv>|IYRjA3fo%N%oiEohG6V%(+t6d|UTGmb>fLV|=mz-E
z8fj>n1pQId*Qx(8<ud3#D66TPB3q{__45tAR^!^Xq#ew5pHman9WaKLo}*Os)vacG
z&{W!$t+X3FYgk9@RAl|wWfdUb#eQ{%YrEMuG_HrRU);bE$}TMja38xT3tk*!+Ym5<
zb^8Rnk!*82RL-!2UI8A%-i?ChS$0uRcypO;<_f?ScFb95CbC6GQI-2_EPctT?3GlQ
zeZY47k=)E<<7xJv&sL_&6tK%|P%U8-ZUO&^t=||1KeHts5Uy91R)yvU)eaSC+*OMa
z1m<?CB<xObzN&ozAoEjYVIzt=pz`!S-qh;&!xge<m4HAQcSiMB0w@zzn#Rz$s%oo2
z?vCm>1zaAg)D+;zP*tX9l&QKk26mpQ`oy3y^HiZF$h}e(n$SEYs^-`%<5sJ0Ed_3!
z`lAVe&FUmiXl_w=#h}UgsqHy1yGy;yQ5UNF)OV;U_N#+NA~~*}e;byf)KzAI^rHIw
z2;eWNdtsvPe0yp}^aG~Ok=Mx9-PH;WTd(Tsf6IFQj42G)tFj+#^}bAle!uZAaGg0?
z{qMV1rQH;?MZ<uZAZ>CYgT|NUXPV*KYEx|xwl!1mqQm#}rgaXR4N14<g=pU&Vn)N^
z-Y$PYbMSqdz>Ka&<M5>Ov=*E8_A5%~JQ#%Q{JGeD;TAQ|LLFkYjV7W-aoT}fVKiPl
zWhja+Ys+VX_lCBWLi5{u+P)qzmZlwxh&6YM7iK{9J%0(|L(Wx<Q~}{7t{DKDlloE`
zD`WL{zreDWF?=L)KE~#8|Gw+T*cTL0c*0(xHqKxV)<7<k?Lp(!Q}$+6&_842Lh+z;
zSns1qd{k{5i2tHf%sCE5UsY{-dHhsyh*ERARe#k5aF4249k2zc!pe{Ys+L~^O|Z&!
z0&;s*J7b|4stO&3itke;?SPl3RDYg9a#}T$*3)-Ymv+I6d#XOSVd1_ihZdfxD(?rt
zJycEk&4H>vQq}Da>0{L=TDd+^RV;x|87id%gqf-%522c^8uSMq`cu^|iZJD<Ce8<G
zuF9Xne|f5vcrUnol^wgF+zZvHdBD9?Z7%>zq3Xw00K8Te9|HAi^)G8s=BnP8g~UzW
zxhAb|)~a)U0)D-^dI_A_p#FuX-(l*tHVDJj`{`NTQ-3{=T#9<K5j3glAO3{q1NDg0
z5I$0iv|vnAFQOR36LtG$NYd4lW+2H_-=7Y6mU>YVl4t6;X=sETb&oLQo~uh*OL+cy
z>aPiS76oeKW6-=%H>H90m3r%Pa2KjClleF5>ifWk(1RMnBK7p|KvS&#M3J-)>Q=P!
z`=}Otk^7|1D@D~lt7B+=TBhbG<WR2egXk{zRh?>uW`(*JHd8oPjTYNRoO+FBi}!_=
zR>zVI)NG?BW-$zH(tH;Q3!62+<GbQKHMtBlw`ww;0`8?r+6&F?8WVjwKAMwuXztKd
z>w_|1&9sh4{50Yi*xRF77Y!AE%^C{41!~G3!)%bI1v$T0^J5OmLNxpE@^bq%j~v@j
z&jXsY3-C8g^Oz!n;hLO{KpfUY^#<aIW@Ja?j%oVT23v&Y+fI0KTqAS`E=se!Cxj<8
z#wU2@r!)&618_zYKO4@(Xr%Tai`95W0v@M{YzUQenua(Lz@66&jz$G9YMu^tpzxBW
zIW{r5%bGJLcyUE@gr-qfHK}P3Ueg5Mgz62=$?xFzP0d{eNs{JqU#Q&H^ojvnvgW&<
zV7aRa@P#ue8cP~f?rR#R(YvDQ^aEHPY8F%jAWbte5XocBbP6)3Yu>!1I8%mZ))vrY
zX>1&lY)uVXB<5&t-UUsrrf36_JPp$hW%-)8448PKNo)e)OU;E$B(F7HTfovAO~HIL
z$ve#&8ycucGjA<Syw_|~BlkfwKNDponh)Lpe9|=i6J({D%>#M7hh>_iyCD6d`M3b>
z^;I+cAaqu9V`$~z$_;w~pc^;nXEefEZgxYsww@a|4sE%C`>6`-ZsY<L;5@j`v?|!l
zO*27r3nyWNjoZqVXT$t9?!;8!wsT!aK<Ldqz6h0_+`eJ3;PB<n7Qo;xt}{)jcXNve
zfZLyI-w3J!obMjsgShl7Xy9OOWH+dUaKo{T;zGF$YT*6c9vkc);N)oJ!np+_VCfKd
zgO-#>xGhJZd6c_y86HM(SB|1Ck=z9O8cuN1J5Zl=a6J#e{AtcJ4R)isg*mVr!yTf~
z?OE<`S_Q{(pB_Rbo;$k~`14#&An+HsQ#8AJ$PEfW?h)6JRvb^b#{Gax=hl_OnM}?w
z3T0Vb#VH7%au*K({tPNGl#4eCZa?Q7?i3Wt=X@K&n*uK24m@40op=?AtM+Mc2;H<j
z7r>{r+U29+%zEv{9sq36j-laVqqfr>Sn|+D3<mcWZ61ZTJhd@RV9-n3kA|`B+Vxjq
zX@@q^0KiUd!*y`fPdhss?X*i<!;t`;Jz7x@8h>qN?8|b=+Wx(eyQ{7B6IAbOeO@A$
zstuV0pB`%KcLv~*Hh2qikG1YsK=VZVtqn9Yw3%&?%hcBG34gP-NA$=&)js$UNse|_
zRZ!<@dr-h3PusX3IP<mfztcMZg|;LLF22;(T>@aCR`(NBUu#d_fTefZu_CyOwD~ch
z`JfHI3*blX_h+E_S(`8qUX*Gtm7wg4cK8C+@T=C*8}M)1@(`%3=6@)Ig*E)6`zUkc
z-&7!XjBh}~2tN8FgYWM+->^SSMDY&;z;==kj6(yT;#;={X*93NLhcM-TY=rPd>pNy
zWBJAPA&lpvY2WA^|8YFZF7QeBKzflMOH<PXe)=S+T;{7#v^$Z%p8?@jelP_iuk%ep
zP_r9+^$`00Zt=HpaD_|aM^b?04sZR2XPC@CJ_wzAycezNQ~2ZbBBt`cc0lrg52oq;
zBYq8z7I10&IxQOS2|wctyieyF(M&FruXGNz&*Ia5f@@FtH3MPy8K3bU&OGPWZbmMT
zzj6XBju*W70X06qlQz&^^BE%`eZw!V1bh+S@&ddl=3`qT`N$_wsHcRVHW(_U{J`}9
zl<~VL%=(poLZ5#HKY9SXSS>8>0imm~*$X*0p=u!<T`Sll;mmrWZUT}GLTN()Hadi;
z`>^C87^zO1g|;gI+#-y=ie#(MW*bzu3H|>De!JjKZ;7{%a2d%C;j9~c+9{-+gHM-)
z1$|NN1Yu@>B#FY4<q%#K92AbdA+)4W;Y}goIt(QVi_5@yTllDly=1}BXA-1$h2%b9
zOA)+j*>_)v2?WhU;rccJ9|;W2^B)VJW<mHw814=8nZo`s;If2O&5(O0tP25Yj^Ih$
z&xIdfp)60Bx*6~SLDK`&FNE&Y2fh+I7N9PLLd-FE_(tgL7zM;z!9opOB)AMiQY-|$
zMBxWv_<OkjQP|QC!q37)+J!6?Zqh8LT=+)8z%N2>W3YV_>e4!OwfJEKG}nlUH;{7^
z=S=|hIx*%Ia_dF)9VG5zhcHxPqxkVJII~HdQtE(-&Elh1@YGY((`sw0xalXTdWp6T
z$ZZ#!>;=sZu>(yCcZ%f{b@3B>QY3wsI6VSv{-W<iumy-e1wa@qHlgXlUa|HA<U+*^
z>TmXm>mI@F17ch1(GH4tDEtsEc6r6)`#U7|Yz8lmh~}D5Ju03wAc+tQUqcuvcB1d#
zgc#lfUYrz}pTT`v++K_%S}dFo^AE(b2#}_U8MLYLSp4%U;OXL_C?px8_gL7?65F@K
z`;;x}c?fgFLG6Ld6+JPx!#qq}^*4a|;-#@5eIX8`(eS1Cr8k7H#e@#1+8a?ija-q)
zB6P|Xix+MK|3SPp6v;<1o>my2#6M``@v|5_097j&N0Rw3;?kc{i3;)PS#W+6*HggT
zRXXJjvNh7(2cUMWl^&Q;xK7ejr@cX1cm+D{lItM=JtXlNR5wZUK0#%Rw0r|pJf#z~
ziMdUhLDM-eX^k7oyruplf%B1~rUJK9im^e(SDH@K$0%vq1PD(^_o%x%B~{!(bDfrE
zQ*`8vL$WT08!=KCeKN7q7zu@O(%^e2JSPp_4x01Q0!&!Bi_-O7uyjf4O7n!v(p?t-
zu1H&cfaX=HK84q>NnMKI(+$a=!YVf<ADmm{ZcDFlMw7cEU7$_hd(zxLP?jQfA}>-U
z$7U0B9!Ra)z|tcrzdD{lniTjeOgxb?D9V{G{gnrmEa_`~<g%sNIFi9VlU!-3nj>wb
zy~F2H0;V!to)ku7dV!Qi+p;gDo}0k(N;(t=VWHHAqMmQ0=d?%iRvI=DWJS_O$1xNZ
zOHFYohx;JKyoIHY(lA7sxz7?$`?{r4TqiVJxzzhTNWVz$X@XE8ea!{nn^fomp{qRP
z5`=5yfmPuBZuwOol<kqf(wh(<=PiIrpgb=b&IHQ~y26XS@~ks3A1YUROmUWd@*dhr
zIv}5vkQ|hI#zQAuzS06Mdq|!}>w+V4FIp-cm8Ye^QiS}FCJ2#oMFz^E<WDjzosdIl
z6?jUX`~y@@%YS?iyJzH?@u+W%{45=0v2s`nk~n$yehAOYw)O(PzYB6FTDV=3C(=$u
zf~*NZE>Z3mjh4A8H#mUYbvbT44Bn7`q+<@Z<UKfL$tB6f`;ogNH>XKUvYbo9%00OY
z?Et38*Xh}($_c)JKac~nQ1(cEwh_5Bc}qRup2!jNajuk0mut}4FjJ1Am~oao=rn*&
z<>fhW|C#*9ba3a&>AT_Db9qDxRPyCX^Su{#vp51z;K6*ACmsfTof1D2$#$ifW|iK`
z<n8dnN2$>R26reUUm)43>??!NSIMQ2v7a(J34mS7$I7s<N4ZKdOMfNS4zmHud+N#p
zl~c6L4N|J_K@zO+oq*e`<kdqiM0xMH0!#aq3k*Fw<t<I{!<8i3?>?mbHWD<ql;K}c
zmZUVN4)wM&n_l@lO5l3nlNGntNbV|y<w))+2mV5mqFf@}eWkD}l2l~^&f0Mglt>eB
z50&~9hRjxMv{(96sai-|gt?09IFbV8stn&=DEuqrUMl%(ki1etDN0+YjJb#8wX$Z#
zzrm84pIA`TKAi_hoj=miq;=0;K<(?bdW1UEKQ|rTe&4tu<P8$rL#N@~?VxM4jkc;9
z^R#{0<oiZ4y3VF0p{Q-M%hbBffA0=2TkPNgX!))$C|b>W4ARyEn!#9`a@y%{yQm-Z
z+odK#(tg-G80b($5u1*-IWW-aFT_l_&W(AnbvZzLAzhbK+_QW5U0i$Iq*w2U=ZB!v
zvmFKI9lg9-LA7^nI-W4-MIRK5A8-rzGiP-}g_obb1p{l?-NTS<VWX=d+0CX^hFTC?
zF%Fdb*k=nN3}+A0BRs~I+~<MD{~o;W4ybM7OQ_@A%vYyf;w}6anm~B+f758Um0#=d
zLE$$3IYmUg_y!ag+s+TB35Yj;%^!?Dyx9)b9sDIX2zT<$t3cD2e_b0ie*C*2)L{=l
zoYv9)d~j=&1@RMU+7`?|r;y@aKA##Pgil-ovi*GELI4i%+&Z{+kgtA%rp{sfiP0zw
z=Y425>JYztD!e$%51R|SNBFGjAU(=2<B%NV^Jz0Bf<H|g0g-$y+EY5t*P$3+6kl^1
zk`sI-0VYoJRs)h#ym1>^=QO{5K5)_epf3=f;lHC1DTZ(TQvEYch>t9XH?jO8fA}58
zpWF_g;(6&Zbk6bnzacr#Z#W0xC4M5cQvyG{G910kx4Vb3EBw7)5GL|%dcnk1zRo_l
zeT{GO5q7Wh<^$eSdRB2PX$j3c{J0FLB=ZSI0Pgb3dcy2IJ|q>7AeC1L{(xUiapi}6
zBRWv=h!=W5GmXDYalOZU)ke^K!ndL5OgcYP0%rz4iVS7)`S($l#iy=B+hy}DI>Fti
zd^7AXV9Km^>_A}-@16^qT)x;1h0pmZw3VL6C)9!6e7+5BOBe7evipJ$p*ZPFKAKi*
zulNnr%!T}4Jy7<VZ&ww$H+*zH%)jNW{z%^OmTTZF;%iU@zL?i`gBS1lPu1b*2fo4w
z8{wFFFT4SRC47H6()Nir)PYVJe=`S3IUkdVvI>64UTA*fUw;7UYT<4Pgswv6=Wu47
zkZ~2<8w7bb5_h3QfTo9VhC)=Eg!9Ev*(@vxN7)wPAx>0so`Q}VcB^1WqY2tJVYC*_
z?Imp7i)6bng+@Yeq3<)`eS{mdblf3Sor|2W(8LF9e!@<2ZI|G66PET0L*^g}5!`pf
zr%<6A&8+qb=ddfl?H6uS$9F(@Wd`*@VQ~di!h~O}U<nsiBkbwm4hb(?L3&tlJqf3d
z2rCkydQ|YDLr%wpeT#sP5Hu2mk-{IxkQ^6WheH@8L|+8%gfO)$awmn~7J&4WaDY}3
zr-f@dXv%0|6$LNO2&o2CJ4RS`7>=G5Qa?d6R+vMR3P+q!yB+ZHLO+`IofDFdpzyp9
zM$y6x!uu1*T@;GD!qO!nn~oqP2m{<vb{QwV;Y^}XLF>A!f>%GVT@ywvgUWT`Hk|^z
zAq=IE_DvxYKO^C831Jl2OA=Z>fxX+pKJxI6LufD!(qtj(J#_90QA1$qo{&hp#3{nu
zm(aN{j2{frRH3XMk_Up7x`c<qtUKU-B%~AomnLLU%;&K%k<RNq5w?y8XSz^{UX~1D
zE-j-oh4Kw>G)s7DgZXTsZV;%S3XbpT$iy=tuOaX`!hSkfkt;l31=Z(50S>uhp(E35
zCSQ0%k+uS1Y%OTM5Hb?s%uC_-7+88G{8|rXg~BV^-gqs{eGI#A1T{76TcQ7Fz~2co
zX{J#mh^GK37PPeK`d$e4UeMR-s7hxde8sx1DB3OBzn~6#L_KYF`HKx+APEqEq#i6#
zoNq-{g2Y_sh%FxMkFvd@*IalMA|9dLtWdEH9m(7$2GYuHzc`f62^<iA`5nnYao8-t
z!^GM2^@WSasNX&$MmzBP1MaX`gU<CF6Nga0A0bwyoySPg%>%jP;>F*g5+ydNiyEB}
zKT}6`Qk>-rgQvt(V?c9S>_+=N(c%&Ml+TDADXbVHKJ5<8vtl|9>~gW<8JZKsiS23D
z5-(1h3!l!3(Gd=$=f$B<fWIJ4=#1o|7){gnOQI45)dW!*jO4QDmH=n2h^uH2P89!Q
zAiOHpp<SnI;?-E-u8Ze&Xp$SEXAIi#rWi<_>n-s$jmt@5))8pl7TeRN@E!5XZ8(}N
znor>{40l)T(*=+2o;Ya=xKqUE6a~I7{+s|4sp1XVKYbupqNv$JaZD?aJ`#VZ2hB9m
zlXkHmi_aIJqEEzu!y!x;gMCn?3^BDk0GVP-np0$n@wcFvExL?G?x}ds9X{oXy%Ah-
zaL>g*sh`LbCq9KvzBq0WfCb{QXwbY6N75qtr5HoUeO`&vDXvi{1{WarTC7aF7;nU-
zt$=$g9uGqDPOPhjN|9LU5~@@z)>;YSd$B1U>-!*v(GJx|F@#3T5^*+7fE=I1A@zXx
zES~QQol>!x9gSEfE~y4D%0<<0DElIg>VYQtDn7gme1#Z<b2M1;#p7oc+-fPSF*IGJ
z2|*xTBe@@i&`oMs3bM6Q1?|(UlS+NSxn2q$2bK-e;{DKcmk#xX`Hc=~>tU#RNZCcO
zv`Jb;M@%+L<~b<bBK^4&20f+ESch_3rM?uj+a|T4Jv1-ra13zUrPZUL=`C%isr62&
z!EdnSE0wN7nV%F!!Q5SvUksAn(yAeFW{(s`oc>ah3+x3*bv<?<4V1!YpbL^}k4AF`
zOH<kczgN1l2)Phxy?3pFR!1bo-VR6;yTi~yseq=aVN%V($c0O;bU5^oBn=1GVX0aR
z_<2Mc+6B3zQbSs=9+P~gLKq?Sp%ZD5Qp3~89ha8Saq1{3_%u8_Aq}Ak%Sox(GvrQ5
z!ccg0TDn2u#AxY^gM!azq<*w;i@~ZHwLUA|SO{UP)O`#{<D@HxAdHt9orLh5lt!md
z&P(}psOEwcM+>iuQqP$ny(GENQY}FmLvh~A(gzA9Uy;VT!BV26r7z{Gw4)TsHEDY=
zoVhOT2zMZRL#j~|CT>doR>H(>>2G@F?nvt?ke)21%s`{vmFm&Qcu!i{4Vo!ZawS;0
zFP)^JKUI1i2WK8go4jH0p@cIe_?V<uEO2Sk!oCnbmb@~MJi#g-Ea}od+8fA_zTKcx
zE1A-dk-%q3<H}KsY-!zZ(0MAY@<c_SNzw06mLs{phrwLQllE($ONY)uGfz5L0-Aiu
zG8ifal5Y$u`a+u60A(+wbc%nxk`_(|S)ug)Z&c~E6id6lZ=@l!k$Wqp&!TANJ82J&
zJYZ#AdlzVmrCD^U>%H_-bEtlh(r5$wqm)QH!zEIs_AviRI!v2BpQSvCT9rzxsLw5v
zPD}xyTuQx#vM*8(3iN!HTF{0=h2%RDwf`pR2BB=Ve2px)%8?#uC&wDulZOd6xhM6q
zYvnIzp|egtLLu<=a&$QCZjgVbfTz1W;0h2M<sq~MjYF_=0N5hm9gCc&e1-PUz2sZ8
z%HJ+;pjDZ-yoa_CcFKBspM2$X3KICqAL)VakuT6GVSk6L--|Rr_F9D`ST_F*6MN-f
z=`4PTd}uBjYQOya4sr)%o(}LHlsnj9_mF&m_N)%eN1`D-B9|A##8G)11<j7hMfiCn
z*8Elvz$4`#{CJQ%E)S<C5+x^0gQF+p2cghBDNovT7&NEkmvm_IwETHK*rMf)6rDdK
z*EtGAjC}eelC$!#+bD~be<_EhIJp)J6Y+ARIONXBY58#byj=JeDi`F{<M0Yxly`Yc
zL#sL*zd$ij-ggA{uF8$upbf6cKC~xyT|Pe;c5cYkDY|x3Zr=^)Tk>-1u#;p{21stp
zH)wu#NA5`9O|rcIPq>mI2lhekzMR|}NveE%A*dh7j28?&l#g`+%OiOo)@2ABv~bY*
z#>es=T7*22f2#qVba_x$7|f8DZAPUt<qq@{kSw`I9_(hzC+Wp|DvvAz;F&zY1ODd7
z>nTE+E5GOn+;cgmI{<m|yL}+bmy2lEqChT>hVX@aAQ*s`^5$Le;+33irrCI*JR=yS
zujN%2Ablf`4+8M5T$TgjJNX=iVvFR?G^sC^?W@rw@8$TaF!(`^qu2PO+@GdPCGxD%
zfPa!_Zb8{+Ij9LdER`251E5T<=mzuU@(|j_{UV!pqwK5v<P3g+%T>ssRnSo1<WM>*
zw_54=7<gADWH=12QAT}1**fKd2Eg^ou@5k@LDA7;a#uS30l-G3StcCyP&Rgg$|j}D
zKv>$WbfiO4Ta*-9MSCg_M5t_4KGc9S+mt{bnD<i7FJbV3Z&$J?c;u~&{0Rsj<%Jr#
z9g3CK?mLx(@8OKEa)h?X{FLskVRx4j>;{_M%ELhr?ormb0N}4=KZ7tp8AQ|QK;;d+
zRzZqPLqxE$Q4jNbm0Dd;r4Yq16Dpy~1B$yl_9?q*I<sHV`l0ZE(uJlK2bB!k&<RsI
zE<_Tp3>pVZhm<5*wH#JP({%cXqCA4Zql&l`G{=;}2&hCTe-4E(QmNzumg9<x1D2wc
z{nUS-Q2wAO{7EI1BBIgC``XBzaVWX8%@U*B{Q%OlitBkKu}WD1>J+EMt_DrK(wMdq
z&ncCnz;<4#{~T-=6!m;G;zecge!wp&t7z{eK~X3Yby;cK5hkuERl)#BR7SK#a#iWt
z8h~p`lM5)jt}LN>(+$NjuQ~j_sSKp`*)8QW#Yd8qHj|)wTk)Xn>pMzU+PO_u^faHi
zt7t31wR_6zxkyr!vEK0azS4;L=v1Xx3%~<qU?R#MD*67X;Ugvd2N+CK>aBpvV`UW0
zW}YZpMk2{ndO8lk?<}QK9#pfH3Dc3}D1+z1e6HeAA7#&#bn3zilpawKzEIMS0r*n+
zfffp{75^1*?TsQ|0Pd~QhBmc|6_>Fv_+FWM7MdTFHPjh=R7#V;Qlh*xBlk&Jb{rm-
zDdsYYd6X-+eg(}J<tUwO`Km0}!cv9uJ58~^DcuElv0B%GdS_Ri-zDVM=%VS{cGG>L
z!=7t(J-!Egoi528fc3fznk8(|#ZY(Uu6s-;2{!6>P;Agcx1$1On{-ih`fIapE4GX9
zk?8U%%IvA@Sr7QFI?oAU+osd+gQs4)xfw9AU1xa?gtxAK2dMbyHqAz|L#OiuZl|vE
zGLZV}o*hNbPp5Q6vP-v?&Jpj{ZSn+skM3L~RQz=nw2}(YwK)u7pf0fm9UBSK?WQ3n
zSXWM8&R*SIcK}0lYiOG#ROd%w?R~lqv~#pyx1ue$59lV>fQJWlK6I2VOt(E3j)v>}
zX90dlmwA}J5#8P1P&uM|ItGBFx`FLbc1)+AiX=j}>KQnrbU);y%yB~3oI2f;x~$<a
z7_EC=f{LEe4IrOlbm3>fc2-wY2NSWn{pX<>rz=YWcf8K;dz78it!e`=&g%}@fxDnP
zx(cKhb(I)cx}-~K2}=pOGdkoh>#St(if*?z>XN9tP4ClHhwexxq}O!Kjw89Qdqw-t
zH*{Mlf_zhVg+X#l*QhouCF#DW5%RWfDhFro=;9}XEm;?T0&I76?V7@;d%F1c0Ho-a
z_ds%AH~AFGQgs>Yq4_}Pg`abC4|N|7gXNKK95v+=or9&_-E>_Ry;m8!sS)rrQ<o}3
zn5D~^3e{}g;_FCqbZw|J$knxV248hYlfd>y*LMZl>8<YNU6_BTn?b`^k?vYLSc-KT
z`env@ot6%he9#4!LFJ?Fm)B^+5}mp}D)C9z)v+9IeAanY0<cuKhyp5Qx`r!|E7zsc
z^6882%2Fg>b!U4Zsn9jaMcFr<@D1iy>z7fl=c@l}EiA3kFQRR4H+|GNm{_Z4sn=Vl
zH&K*iz1}ny$p*a(eof1{>yu=_H|if{SmB0;zW7f_H|wKmX|+Ya#Jl0xs*c$Hpx&-m
z7QuUOeHi@)%SW#s4<~l$J5tbKr#^y?k^1V_cL24YelKk*?b5sa0pV`_2l8`|zH%L~
z`0Kw?69(w}({w&iA4DfJgY;h0;9#&miGF{vS3io*dxq#&(kC6NPj}F?Z=b$^CT#ol
zRdHsYJD~6H1!1`U_lY1qq|e_AcMt2UJ%>+6^vkM4<*43T1%PAv+tiUp=qm*w7pb34
z^O@uNrLm}Ol>SBocyU6{4@B;yUf|*ODSaS*aKN3`m(b)hT3@G)1Nbxg=5%r>Mqf<(
zPiOUyC<+j(58`1rPM>lJ_;~$!8a>bH&rtO0ygtwqY!~#Q6n40%x6(7aq#sK=wh8*D
zSCG4`4+?`%SM*;!0Z-J=r-k5E{pF{q*)@H2Ey}LzR~@5sL^t$fI{<N0KkNw1-_o<=
zQSBsseL7TmTffg2q<8f1tH9A@eLERG-PH>;7rduWr?a3b`YnARysyU}?!afD-#-H;
z9_UZs2JWGL`5llw($}YH`D1-$`u*P%{V6*Bl&&wu=>i9rq3^g4z)byVIuVnl|4a+K
zZ2jt+P<^UjG!oT*rmxW&&gAI3kilI2{IAG8*B_zfY`(sVb0<T;t|o*p^h*Z<@KRq`
z4whH?i8MeL>K9Oe;kCXS#i!rsThWQ<xB9V70e8I9U!o9ikzRZTzl-%18st9e9W?Bg
z=uc61@k#$PHQQ%>s0aKm)qBv^f0_Or9YHJCccz06U-U6uVeqTo>IKpY{mx%d`)~RS
zhmou{6iX1g8TQgIwbmLY(@b%lAu0ui);kQ9v`9A?>Td^)yFsQ6#f^qhy`ke_SU4SZ
z+GH4Qfy!pXvUi}_VwiaxDxQYQG&S`yJPm}(c0=v+fO{Jf7r-YULpGg}-eI^|8`a)v
zxOf*rUqdlX`1}m=M0l~wka8HwZiD0bHx%wMT&Bo|zrmdX4FLv^bubuc`0xe>gA9Lr
zpe)!BJ`;BL8Zaxy2W0T4IcccDN(a;S8M@KSvfmI-f$;-|2Th@J(BOLjxG+O2I`R{4
zs7puR4jEn&;IQEsHP8`5x?>P(an#Tjf4zk}W*ADZSA;>X08OOf<xZG5Zg|Qf7iDm#
zosJWRal7E}Nkb|1Z>J0oX~uWju*VlF(S}j<dYmx~*#q-2h6z7`^Q_^(2)Gvek5A_e
zHRv?cc|*Ah!V89bN9a81MMEwf#k^!NQD=}~*wqd+mkll+;J#w0L7|jH!>?6g;+jD{
z6Ts_+!HwX>4TF(-pPPnmuaUcDn0f-ZBtz#R(7a<1has12aCo5+?i#8!0q&k*3;vJ}
zmtvT;8iwv0W(=hBqz?_RW8vu|!ysB$q!~6e1^%(Ys~!+f48|X!nr;}}8|{^0h@rFF
znT8%6kYpKJ(+*a);mTAv`qYpq!{9T+nu`GB7`D9zS+3#UJ5WD2^zH}EJVOoY`11|N
zcYwOU5Qp792lv9@nSsKWh7I%#Ul|IDQKv$Knckh(hS*#rZw&3Q2gtoOTz>=ZcZM_y
zj29V(eSl9Th71ADd@>BA_}6E{$~O>}8ZsL~rOYs;4#>(485AM@Vt7F(oxU0#(QLiK
z5Jwv(j&FwPgjj8yu@Anv8e7pG#TsMsbriZ8N79SD)_9HP9vh4yv^;e;PPqWUMq{Vh
zNIZ<)0?=HWjL9qjn~f<nci3WF{T4z`W8!2aTaBg!G|+bA>EUq3+xYvh5c(KbJw{!2
zIE;sRNOu|&X>-EYIIamu{fyUW7ju^}fIiCI#uMW~y2n^fcKwap3XudD|Du?Eu<<7m
zG<%Ifbb>C#*!MU9p~f<r4em2K&Oo@|7-h#ZIAEN!0v;YTHvI{>Fk|)s*b6s0no*M;
zGIlJ7^sw>JSG4mn<H1a*Mi>vLAs1=14u{HdW62^QqKxmFK=Xt#RYc32G+w=l<dpHs
zX!v{Dcy}K(qm2wrPtF*}o`u^n#!c=hJ8K+eKoV;-ya08aanNx1bl$kYaSquFM(ss3
z@I@m-=Ls$u$Id}6!RV)h`OC(^OJVnlv2QPMCmMT4qU@^itQML#jMHeN@}_Yb?cUrn
zHlt51$#}C6!rR70kr3W7Znz9UvT^4aw8dTH-Z8Ly&-gtpy;F>vQ)yv*-<VbgX{vEj
z7)(4e4xa=>nsMS2=sY&^HBgx+#t|)mPd9d_m}`ddHtnZn8pkOBWEm&ZFWj?@3ABcN
zYV1#&K+lZBG|1%`H~k5gJmU=-uk(%So4^$q%M$^3VI0?p7RE1)Elz;@mC-@Fn1#k{
zI<E5C=tp6XH^$(GsOVdxAA{UG<MPQMEi%r)ALZeSjkR;(_Iu;{IpF?ad{6VJPsUI5
z!^zLa=CoidH6EekHD$(PI%QgJ+%G}+#klPTa$k+#FqS*G3S&>20(~?7eiUA;F?FRW
zqMPX=^-OC`cN?H=ooNS+(CbY-cR{$p)RJcV?xq><P`1%jw>=UMQ+{=nZ89CBQ0QjU
zm4^^+F>Mo&+h%%2AxSUO;s|)Z-ISFMFT71Z(t!Ynk7?pC*xg|&{}G6tCO6t5_cf)R
zfsUUk;xh2NOtt9M-EBHSGod}EY3Wc2H06Cm)q+g6Z@>kck{LY7y{0M!C<`%tdWBr5
zsV?m@>@$@$LbBh~p1zR-rcrcq;Gij!HXFhmrkd~3Ug4%TM_}-XX>dHGM@@%wAUtN8
zPlH8-$zvBxM4Axl#CKp)f?*=c^zkRKoiL@Yflnt*5*>|<Hcg{B$Qe^MMQ>tETk$ur
zxU;6^6z`5T*(rV&XL3siS-fe*Cs3a=IZ|oHdEPXTj@eu=Rs9{wMbk+cI+si)=la_8
znj)KtrYp2>bk#JKmT%WgFPp*ObyM*wBsWa;x1#K(sU004xMkATf@?{p>$JOe+mu)r
z=I@wlc7ib3G)91CifMiVa`#Ou94FASsixgSp!&e{X9MIOnw~d>7mrMfYd|&4^!Fkd
zd~7m!Lgk6cM28a7O`k`i5i?9-TS1d)di)(sJT)CRz?o;J+O#c~V=Ac*VXnz*2XN0#
zweKOxGwCb<<eOHZ>*oqg1AQIfeqs8q0@6a0|5&uiYm*x-px&6gXqNWY<lho1?@aSH
zAXjAiYanQfO*>3zwfCkZUjROsmeG>*qv<v6QkR&n(m}dUrZ}o$nJJWF<K?Dn6ej&*
zy0sCwucn79P*!2OF@nCoZ>EMt;9hM$kOUf6b0`Hd*O-sfgLN}^8-+TpHFr0oY@InT
z2$~zsAwL4|VeV;$`Az1bv=ZNJHqm>v#q7Hba8L7TGgQ3HHKxJtcJumq5PF;IHiwFj
zc}NMo*kP`Qj?KaCG^ZYg)Yp8W8`%8JC+0wPm-$jN;CGw-r@-zW^H^He_?yqumlI&F
zLwi|)W^M{x3o>(mfi2iPn@;ZSHJ3a`F2o!|^VU$amR5NC%u^mAx8JO#(EI`ON}4Jj
zH2;!-#1Up*PbY}N%|mVjc*xwJey4WWypRI!N6bl92#=b7r@fD3=3H7WN0?7dLN3xg
zX)s(nZf;6p^eFT1G+>@EXOmAS&G+fIL8r`J&48aa|Jo0LXmflns&vN8BObuTm^bY~
zCC)m`d7Dw~SaUfYuZuGqXw4LFo<?h}bLKjY!FJyK7o8ZqV17-}*Nf(*Q(@_n`B`tM
zB$%twuGwX?dk89V#q4W_Fwy+|Sa4r8w`-5wHFL{9L4DmkvL@g+%nknr;HLTDO_bd-
zJHDsRB+2Y^5cR!nK11KZ9dp_Sm`FB{4F}?`Ihi7V_spl8fhNWLZX(L=n|o9sNj2}y
zf~5!MhydUonip4t@R2zy5V$n+`gr6Xn|D(u^u*kOcDK{baRt!KF#FK3ooN;w-=LFa
z4h}&!+x(j5kx$J&1EBNFJRk?a9P@8Op^|G}Pz2KF<|Q=z=9%XcAm2QVPS?FOU!MZa
zSLXBW(6WW*Uthqd*X9NDk-Ra#uZyy`=HY#jyfYi=*m040Cq<iz%>&!h`1js?p%U0W
zn0<p_;-mS;1Q;wacPm5glX+|i8tAk6ES+a9H7}#tLzy|p4{YV;55r*ai&-BIm9OSs
zR)M?1yiN<d-^}YjpuVduM-6y(u9oH$wqIlEN53<0vurV<Y^~+$I{LlrI!gx42iIFp
zizwV+33o<)E#_yS*=W(e0jY<@^BM4)ESq}4i_Mn9Eugu@@)I4G@U(oP;KEi*$IsB*
zW(lHJ_p-e02uHVD>?@FXTe`J}(8p3t)07>S7uNvaX_*5~2j^=!OWnJlC2a#t?6M4@
zRo!k&eL4xg$5NM0iTGQ_P!AJe;c1g6&{Ea_G(na+v`h%LtfP)*uVrgn075Lc=0G#l
zl1*{IeU|zM0pD*~xD3sFz_MpQatAGi!;uTK^r-{5BiypK2hu~9pj*Hnw%|7k`0y;P
zX*2DpC6<my9kXoS2(}1I6%Du}Eu*P{k6WsagQHQFO0*St!t(GBw8cq_dl|S-St=SM
zIc-UJ0C=>;7z_(%Ed6UE7i0N31n{$#pNj#Hby#X%19zOoPY;@S%g`zSp0k|Oz>D*i
zZ&?6du$;OEM1rL$y}Fkz9q3fu70X<j(kEJKX99QCa;`rB*DMT;<<~85=&Z>N%R?im
zZ(3YkVfU70Ed^1NEc4gF!fne_+GW3Eab)2SEON<~McKgLwN%Rl_dQD)t)){eg(rc(
zZz&8zv!z<jQm^;GvaKF+4=n{0qIqQL&=D$WmQ8;l_t=uB2K<R--V=C{Zkag*xeSXB
zjk}qaMsMM7mgUc3$YooGtb)C#mS>KU$Ud{|5y72fd0Y)_xt97ABzbN*@DnWMS)NfB
zoNuZ49;5}9>f=$h7nUeGX#CQ$dnj<PEH~-ISfOPCoo0A#IUR`H8%w_uXuh>PIt4G@
zS<ca}bCG3qB{V{@WlvjJcyH;jg1)~GmT9!5{n0Y{5Rwwh!;|3tWQpnmn$MQ*jesb%
zgwRsF%;M7oD&>~ZG^PJyX>|zRf3;j043!GY0GiT&vkau@_-gCnG$gLp1`@njWA(lS
zfSa|8KUCIQ`^N&e&KkIcj!3MxuJnS=25TQ$xw%_?X@<Sg`mF;<J*;DUfM%2RK|0KD
zw$5q;nl0Ap6f5_%zMxKbtM%_eNVZuSng@DWnK+Pbw=Nz96>sY-I-KTXtxWqmJFI;c
zKxL<O;E!l0U#kYwZ3pLP{jw0MyR7b>XiI<Vwuf*rz?x2f9U{;=!i2IQ>x&)81zVfZ
zuW$ESdqhAOVm<yI+@aQ_wcy@oy|NNs?6)qlfct>;+X#4Z&>Bvw$S|v;F6@R|U(?>e
zA!|dLARM-;X$z+35$kWYpmWrkLV>1Z)(e-Bi?FtP0i8(e-0sjhZXHh5j<Qz#4ihJ=
z4LZZalh!#j(>-M^_nz`wRmZEAke#(2rnrBsbxJa-5@&VSBZ;^6w;(xZo%9sRd20-9
zP+zbP_!-GXYZWz;OIG$fa3xp`bSUStbx=7puUKnQPn2lYc7_jEtxu{!^O|*G7#_rR
zYi|mQ->}Z20pq4M)DZ~hZ&`on4D(6WB-(1dZ4H_Unmg9n^FWhq4Ly$Jt~Hf{Dfg^3
zX>TjV+UYSg?^`*VAg5aYrXSZnupYmSvWM281;{<JwxxAUn$<+>)5q3dXTX^!)}j&!
z)2+Q|Rg+<jjCFuJ)7p6-e9N*PqA7f~^_UCHKecv#g|cVX)z^{aSQmxE(Ohc_3OYTv
zx=w;-o^=JCImx%az6#e0tm+3KePMOk1QRc<<7guC%G#+MnuXS27LLBQ@@)WkV{Kgo
z&9~NoIry_D+&k-lx8N?ahFC#UY<;u@o|ahihXe7+D)a^Zv-K$L?w4A<E}^W<+KG1k
z%B`8Z!S=<P)ddE>TK%d*rNSCu2jH7^etS5&+U7_{U0iKF{y=Vx?T#l@+-&D|BDdC7
z<1Z~UgIi}SEd+kOO{BA=8*DknaK_!XZ#b&G(YBOMN_g1(Z^7YBHsw0XHrsmBp@=QE
zHuOh&JZ%Yi$ZfU7Yy;^w+edQ7%Ql8KVz%4%(D37JbN7BSr>dhg9r}JYkBOk%WjjgX
zwB5Gf$HS#Pwudx_^tUyu16Y7<7ex^QZCmIMVg%XNWur#HHZL!f?X@L_!%m2;w;x;y
zwSA*LeV=V1b;kQ`;dGAWfNf7IG!NR=M?n~7+wcx7;kGl5YOs6Ac8f-l!?yag!*#@V
zYXWGF+HTTB@0e}iTO<*-x%A8;ZKqoyIc`hb1ZSdb!7}Wguq_!2;Ypi8gyt#R3JSWM
zwuR9gCE9i@5oBj<<J&?d#@3P!7oN3M{0yIBZDZEZiXqN+rXvvXw%molpR<LugwA=J
z?<F8E*k(6}YZq<Czfg9`Hj#eCm|#otLGH4xZZ*(cu?14VJke&QHoR(k^b=IB*#;d3
z=XKkp!)WXqwh<xl;->9PbKq{-`i26KWQ%A`TWPm#M`@vS$2N2VnkL!C(&X{3t>yp-
z@7cyu2q?w&Gkzt&-M6)lhDxd}NkrKrTi|Y3O0$(xaQU&VgAx8du~p7OS-P!aBg|*m
zCjJ6prtLv97|gPrrS~V>HkH<3Pi@6GTjt=N*$U|A7df`_mvAxH7EfoUp4$St!cv}%
zrFn6_ZNN2@71*+g`-N>>FO<EsCDU=GSGJt3P${$(p9b!=ZTu9Fy|FE&<>gzOC;c6&
zcebO)0VuMqpv}5s+XY%Hzqbt+K<4;hOB)TEkG3YXpI>5A#R31xmJtRQKih^-Xus6<
zX%g7VY}wn8E4R(tiCTQI#nLYQSKH3rz*X4BQYF6GX40x)wf)DM$hq31dO>rIz4Ko%
z=w{Ea3WICylW1+f&VK0%%&vFX8yaD0gM9_n!ri{)4cc;}eWU^!4|~oyAU4^9_XDxn
zUR43<7Q3_@nx6I>>9D)ies&#Hw%J$GpQrJ%H@XF~?e_gNG<e%rEr*Ja{WgUbcGx=y
zK)BOBF$dJX_IDRx-p}q(4k5eC-iMa3yY0*Kp|i(ciRO_0_FHXXDZswDAxH!5p<7`o
z$e#TLxnO%_Ebx2n%jm>!h`l5dfKYpx3YPZSN7IS-{dT1k$pQQLmauTpUX9K>huPnR
z!l!V1(jpi-WOsLb2c5(A27{43Vt-G+Y(8oark$;0_GxOcMcD8E0z{;}C#~3z+qtVy
ziL$rF-(TlW*e4%@@T7g>_i*i${kOFMoVI`X0+nccGYT%BwWmx&5^JAN5%xIy#-}KY
zx4)-&{W<$`s}<>a`v7`s7wmOt&VA8d?(Mp;s$)|ZXeQdHP?YDYz2PHhT(g(IgP+&!
zlWHS(!`{dpZE(|mjRI!3?4Fa6OR{H;hV!@WIdm-Ljy;j0_Q`gi3n05|cdSC$J$oxU
zYMWyBs0MTQ?ORvD!BqP-T7W*V8y^Ap(Eipzf3xI~UFiw#H2Z{5ARgO)p*7SK`;T5I
zOSi8%2iG#}ll@^L)84cJfLZqD$)L%$TYo{rJhcn-6NG2>T{B@f$No(OAlF{t`~wJf
z_tj9zv!9~%dcOS;Ed&eftEK_)!p{8RK=!5GmsWzW>@DczVxfJ%5y@-2=`;{;>^K30
zPt1OM9-Mh+@BS5D6xp{G0#I!KQWXvK-ad}jbsy|?sE_|>kEDL0#IA0RN_?_kp}GBM
zyL%h>RBA6Lx6AAYUco}Sy~864<$tlys0{9}_CIn#Q(^b<ht4;9`{OXb+NB-^3S3>n
zM}TIHOYCQucXK&X9l5nGVHT9Fb4j2n!+IBw9|73lQbeaj++7}L!2CuR+f?K{T$-MS
zznfgD)2WHgE=_+0Zi~y_KPZ&p=@LL|nXN93(t+6KGA9?@UM?T#Z@X-F$xcL>w@W)(
zPx`pbq_KC0%fx&Lce+HEBIoP!stHW^xjgL+_%4^yIGFHv`LZ9C2ynSazn2em>Cy&(
zAeYQyI2!Cyo&IFXUYBhY1du{pYSCecP?xvfwH8|)u7`j-=+aApW|&K|8`?MA<?cAZ
z54n7x(`$!aW<LSv5tlz{Q|72kwWUaoxiq7_+z6LO$?zr8<xmx{9Cs<3hpI%m<WUED
z!o_nB96ae#ycNkQ7a#gT)oGWz>3~POm;@L)<C5T@6-JE9)DcL|x`fiYIo72;wj8-Q
zm!00w`Tsb&?zk?i?_Ze>%Q72$_TGD$mG;fl%Ce<trdd{6nN6Ek+6UQtFIg%}K(-87
zDobPtg6u6D1OW#KBK+Rx_t$xyd*;1-p8K48&bbeTHh)uz<(y615@6?T9(xG7FWA`q
z0L~(tkR8B^ZN8$r|0OoLwva2e>8paWGMh&}#xyV5WUq(aa+{BHK)YnK7!0h!X5<i9
zDs7rCSRq(t^GqH5uC{q94WpNBUWtW^H8xJ}&|PcON?EKcHfgWHi#nSn^tp<9n+{hj
z*HxRB<uK7;^Wt&P8g14$LZHb;N&8Z>O;0FTT5PIHVX)Qa3CdNr*>qFst=*=L`uaL-
z_SVwLzSE{I8}eN?%aUNe+h(3#kUcgRXW`Q|o8@#3yw^re-HClR1=%psZ?l><qyd`~
zwV(~!JWf}-hHM0MLw49^KgIMTHZMO16Qee_??CRljW`oJ$86Tp5p~?gyc&jX*sM*a
z_vD04raRC{o42WaGiBpd2iBW5FRp{bw`>wAIKOSP@Bnn*v0+lNd)j8_qcAaJbL3rk
zc-O}7bI@jOUU?e=b2cq6L*SmxJ9KGr!DjV0z!q)PzrcbmV}T0`M;V1@A#TTbntIc$
z_KZjApzgqc_jtA#z4XIyVm$LWlsYpMKVi^?;Yu|jSBA$=kZ@x>d>Jh6jL>^9=)rIs
zfo@NRh65Ha#*dUn@@8!MA58c#c76vIU&b=(f$(G8S&y~wXE;!-5x}sX02XLvtfAv*
z5aUU@BNEKG{wWNGFj6TlIL4@>n;W5wDj}vF#`uBu)o_OMN+^wBu;|qk$@rZT`o|gV
zbaC_q<LD;Hon$PjgqA4AqqkrwnsFo&mSPw-e*nZX&MUzZ$7o50_$h{!`yyaGgZUxk
z6Bw`4J;OvsIQ=|NGc>eKB{6Q$vzg3@s|845+@$nXDr5aq@F|VaZVS$I#$Sgam%%s{
zjlnYvPdBVnCc}-coo6wg@&YZJ!J<tkhY>-U>9Y*?|DY_Fam~6EXdWZ}ZJ_y#WhVd%
z7)|6%A*1vQxOR?FMW=!Dj7<z!y1=NVnotpAQz|SKGlWg>u!NEMCrp$w&Qd^K#`w$&
zGrY(sPlx$(h9gz9E-|uA&{Dw|>x8{Z#+&{atYSPp^gmdtW(>tZ+hs-o&9{c}WCGOG
zGCnB;&lSdCFt9qtnkPW3XMD62maZ}m9|o;~aln7{kkZ;84vu!lr532}U@Sik#!kll
zov_!#xSS3H*BBoeAlA!BvIDJ;(MTz&e#TeBkQ-oBQqpXYkxv`b5F<Gd0>cb7y%9$k
zEfjf=GWHDtyUy774cr`K-1`&QIO7R_%<l$c)zfPsKf&PAwXaFWle_&-{{5_#OX-E%
zjDR96#T~{JrAnq5zhnW-FfP0R^LH6f)WY9chRZO(9ODoZw0n#-bi|!!M1}y|XYBHX
zi3LX1Nw6$3_{)IVGS5&G&QYcfRW|LIw`g7Lnb{n8@4y^;2);NnovhRz?!;u(V=~Un
zRpA(QVLtj3l)5r~sbKHMy!1UJ+?gX3%Xu*Wr0SL@^Isz@c`@hc9q7%>eHtcwn8*GG
z@MU_^L+r;~OXWX*rsN4I3t+}juSg*Cw>`jum~ANMEe&R#8m4VEgjpqqwqwlVe;^Uc
zbQyutFlGat2Ev(-{tK1}<|bO;NapML(0!a4qJh8(<`$|FpJYD%7idvT@$WDn&HQ#4
zCSsV|C}SDRJV`awIOc6Tti>s2{ADPMXNqVGN?@KoL=7{E%&(|x?liOccd#ZgOMisY
zWM;~H04dC`sc9*dx#n}YpT^vu45jJJsQnnsV4lARrDvE6-@)HZW}!dUFpIfw2)eVG
zd+3|zIm}NxK|9NoH37?I#*KiM$J|J*aQV!cJJc#)z&t>gCkvUy^gWz&%)Fbhbe@?{
zZ3D&3LO$e6n47EMcPVql$6zUAzF!ZPi%h;BoGE8EQZvpa<{R`7S1?@-@S>7=x(=LG
z%xE`wSj}`F$5LKqHc>jUhWTbM1ZtU~JaAgCFu8OmtB#pZrOA5cd>!mwWrnW+XkgCM
zslSoQKx6#UCZ@s%EX~Z43g~WOhP?;5R;D+d)7zNW>55@HbMpTqL#8i1{GH5=6pnN;
z2k9u)&HOD7oIT9V)Kh(px%W#fNw1a3`v{|b%x|eRt)H1gargk!Ku4oN=C@RFA7WN-
z1sG<&NLAAj<^yf;dzAStl|-*I-EIJkG5K78aprfIz;c6`N>$<s=38_RYLfY48Nd|t
ztDP`(leudV&fH?2yaJuKnbtbQq)YEGpQ2vJX=eB9AkHv1H$eU_Q%~}<%v-dibIePJ
zK)c7xkmD~h&-6B97WbLzSAZ=rkJ!NcB6G)94BE23q{H!1Ryg&q*s*Z=0S_L_XD5II
z>lcbT9a%o_0XVT%SZ_kYnRS55;VvxZ1l)IJJx3R2+*t2YpMpDU;XE)8*5G%bd9s2i
zd+Wvevk}_7SweaZ_^>)&gQLEz_ul~K$6EU}So~SPIspq{B~lMiAnQ9Sparp_3$X~n
zEaR&HA*^3r=+JnK#a#|dp{$$hAQ;BVKL{+G^%>Q=BUtH_S&L*D3|Nxmtk0u?onSq+
z1+<f_Y+v{k!<wTFIF_}9g7i3+=@hV2tY5?7c0B80N>C)Qd?j!ukyT7D{nISZV$hOU
z#az0olFa&&qPY~-T_3oZ${Mx<Pa5l&FX37`>!~Uj%wT1@06W9_g{mN#th@9Y$zqL+
zLQOVn-Om`zVSQ_WGiO;neE_+vaw>x4vG#OASw2hnEwmJ{<|$`b$m(Z7?i_3F`;;&}
z&+1ge#S5&TTd^iZtb=8kXfbOyEn*4l1l0&iSy#L;r!v-;luf$G`j1ZY<t!N;jxVu7
zE(5DzrO+#}lEtOAohsJEKTuZ9>NfyfX8F}%f;Ft_6bRI^-lXK_71q$7pjqo!JnEgT
zXC+f%=_)IT0}~Cb$0$+T$oi2U!zLDPF5|&t%?!ds3u`~sm0DR!O2)RacDxSI&U%#2
z0UfN=Zh%hKJO!a$tjrM5x>-9Y7u&<Cpc=t7)~9smsh6d`3$uMzmiHuJKg%fsmIhcG
zcf#%<>+W@cA=X8z*bTETQ001rHT6EGHp)6eO|#coQhL{nu?8s`8)yAP2jCm5w=RNZ
zg5~fEut^q+3Kml=4ZTcnvifad=oV`?6VBXb-P8lzVOa;L#5m3Br!(XXOVSC6yR3%o
zz-C$Pl>3`w9ruIZ_gG(3hG3rctUFllvo?N&SuC)!j>7yRYt|mXmc20*0!P``OJUHC
z{SxgS_UyO!!Y3#8)4`B)X78udlM6e@2Li6_*R0f;;KqKH(qQgvF6Bu)*gMui(38EK
z5^i4X$EX_N&AvkG?883z4E*(F*U^d4kG+<@!Q#(u+5#+qoe==JK=xe=3<j~c9D=1_
z_RI8>4Pk#mhnr*U0eWsj*;~zUCX8*n%?g9z>;PNvM6jPL0f=O~#>2#Mc2X`RPOyE}
zLE<F);Rj(Nif#G=0@3Vcl%<Jb`%)uEEc@vPfW@(AZvZ>Ro-TqwJo`ZktP|MIsc<Hd
z{nsbZd791q5g>`ZmX6HH?BH;E|D~{54iHRbzeQ)}H1>uvSW0JyQxuxPHdg_hVS75l
znN0Q|9s9D_3J<8sX8%l?#T@pQzv1>-cJTkelFRO<A88(Y*%)-@vnOZ`3)m-SF<8jn
zIt*p!*kd`6JI}5|y~Dcn0{ikj&?2_u$FN(>9;EHAggrwgvr={)otewn+DD=7BD;iw
zrE>P?KSIqV_VW}oRj_sc14||Q9X?D{vHR%}uV%;m1ud7^FH@sH4LgSl7Paivo>-YH
z>|Jystz)}?02XUK`vZE%U1k4AUlwR!Z=>%{G_uoaotxOlkAkO}z5IWmwXl~_3cr=z
zO=spdwksW3+SxrSU>)q$l$GjaAJ${OUF-q6b=u9YPKBi&wr4Z2YwT=N-OH{j1J=j>
zax;|mTiLUBp=N+>R}H~owthE8N7x%&07lvEGZ?(izBvpvW9(wOB|gq}qnnyH*wK{Z
znqZ6Q8wQi?{kyS1Q|$Tuz;3eRb0Bbw{ZBJkZnMwrf`@n5f8K=oY4-EfojAkxC<e=2
zw)J27w)-r5f-1>#?8iTantSZqTfsBWevv|``|S0{!Lq>qnSpg)WT(4An=R++7{F1^
zIZ8{}amwlFV9)X01lJrmkxxUnBj?ixKy%`ZQ&*QWC-N(>xNx4m0^rK=cpvuMIFVL*
zk+^dP-Qc$er{WDrcyf-mK*Ea?@Dea@jxTLnKAi1T`0(W%AB1auoLlEH=+AL)gSG&U
zqX5nXat6ad3*t1>;We1^1V!c{oLt(qj&WKpKxZgtA`GsDaps*dmvD~q)BnM41n1E&
zp*xZ@Pq(3ub7D6`@B{}X9XxoP0LmjoaqM4&iD*tTm11K!_thAT<t+Mt>d3bKRt|fK
zocTr=I?b7(_hl02vKy2na}Ll`n8InJ*1uFv@N2N1#z`%Ql61~;+B`BiUq1rlXE^W9
z17vb`P@W`<(-r}DvpLT*Fryq!NIf{ua$cu;doJf_E41WsYA8U>=P0d|)h*!6Jp;i)
zjyDxX&vE|w6cXn-J2!!Lfiv+MyeQ(dQ~yXYr$P&VOE~SHW3ZGHPpv#<oWL2FzsM=4
zps<{CdJz6ra=LpkSjEZy2Rf@c-yXx@WzIo41Zp@Q4iK;92pcGbxWXx+hLbwZ`gLHf
z=cq#<c$M?^B}g=IMrbc+<a|aCY7-|Z1SXm}o);kB!r4Ks`mLM?=_*khXRH{scFuep
z1Ufhy=y=-6DWRW#7iVlYEOc|qDBaz|X{T`a8s|+RWkz~A`bB8#<AhP&rk^uSVg3N8
z@Ey!|kTdZUoEhRI(6om+x2cFf!qL75*G4(kN?5wiaeoQ|V;qhUgX5fb%97sTT-pfQ
z1ZOpEgp-^gx|cD<Nq-pNCWn&%Ew?yZ5DZ$E-sW(hgZVog&2KO<&H0lWyk|J#J>a>^
zaefBcW;y!?z%s{KbO&~i<Gu(r^PJ~aW7_vQ6PsXnfs;aczD17sWenPKJzOAgl)Ehf
z0(RVqIe2K#{h9K{4&2HB%*>JdPdQkuPTcQ9A>qtDv=*!`+?PUN*OlA;34j~-NInML
zxvndq+k^X;6EIJ1p9VB9ZaW>-y}5Pe06yH8sk-3HUGE5`e%#!n0RCK?y|5d={f4eI
z1ag~WU_OX@^CHB9xtn`{g;=>e$KlN}?uIF>S19*Q3Qxkg3-r;yaBkCmU=dv3ZIFoM
zCe}jDaqgd=0-WGFEkfWV_wk2eDT@1C8q7y?`!nHT40rvLSfE($fjH3OxMiP%c8a@H
z3J}k|M;WgK?nNGGNnC64DVR^@en9E46z*Bdx}<V@Zvv!oy&eHAox7?AtQp*zH!#sN
z+}>%(XL1ib1lO{-UjC5F=I$TDWOBHB=)+)Vxpg$PTy8iuP~>r+`2j5X+<qmdRKWH6
z9XboS@qB1G$9>Xj51#Yf!0#b=fjdOON)h*d4|ErEpV$tEOSpe{11segbb(gJy|^3L
zMQ#{X!OOX}&%)75+~)?Mw1PWICxA*WpVH7(+;@+_L^XF6bue7!zFP`IHQZyh&{@kp
z+y}WU+?)rk5Uk@K+k*9~=T>!L^eVSvC7fyC_Ok#Qxfz!r*u?#X-XG1}b<`iw!rki!
zxmNDzI1ILN8>tzkoqJ~kununOOQ3afzoCAlE^Z}V0Pf~aehSdTmC<&7jVq;WaxZuD
z3)J(_$E`mCiGHq`-YNs!x8H-qgWUI1FpD9s@d*eHb5kkA8{vLONz+lTO93oh=f2bh
z&N1#5ABc~0H$DKRH@Mr)z$Umq_JC!Q8@w9W6nB)e?l-yH-iE*}t{rXex4D1rr6cqm
z?$fj<O>?DGLZ0C|(H?r2yX-HRpXH*4iwBP@q$<Zf?w6FjoaZLfx$8dnvr-sb;5rpS
ze39!<l?YqjL<hi8-hGNp?RZQ7#H!izDkH(-z+=#X+L8C641X9WULS4wR%hPZ)M@F$
z3#aYUmG?0v_1t*fiI8{aou(Io7cXHHv+(9Eqoz9_-WAGx`SO-gr0B=HKtYl}uZc2W
z0lYO{5D4U{ZvX`G9zOsr!Mrg#jD_%i`4$sA#yhUZTtaz&#eo)P<)wTFZQ;CcspK8O
z+rJ2&NZu3Q0Xxpiiib}pcntc@o#bWEp*xC~_W`hIURxgIVt6mV2Z31L;{V_F;CWL(
zaf-KW7_@la6lI(fc<PU!ERh#PXYSKH;m>e8iMP!QT9SFz_om=m3hyH>98TpGQNvgo
zk4+st>Ad73xR}9vnI6M4JSpWeGkF{QpgW7Vm3FOc-oQ4P&*9a)45epzYx=>G%VSUz
zOdjt$y7QjT>!9Cy0na5877BR}QDONUuYW5Ho#$ov4|y!N%2$HFn5XCmDB&eiGgT=s
zfI_n}-rv-%c9G|P4$E84^QWenOT0|lhbwqDsDf6>Q&T)p#S{DvP|ahh;NNB5TQ2~s
z;kmyH@mgL%FXXQ99;UZ$9q&ja#OrwvyTiY$ygDo06KddHdImg=yyxGAU=z<v0`tv0
z;iuqf;nh9{S}RXKfoZn!By_*Eowt?J?H#<;{?OLRi#i3CE?x)K=DT_MA7HjUJokBs
zU*r9%gQLAXsV`jX<ArrYyr1{$o3JpzJ9dVS5re${QJ!Upx55((I?U5Q4s9d6wB_I#
z<-My0%XQw~uP`{qd!An2<2=VMxIM{Bp?c30@9Cw$Zu0zYLHrgkd<o3o<|R^o<qmIU
zJjADYdw0U$8Qy7X?7GYQnNpy$y!Rs>GvEp1y+N_-J)YyoFgVZaz7BAom-+{kF7UYY
z4qoJa^A=ca`GQ^kC%vAvKGOnu2mW?S^E>jNrZ~un-%edK&is(Wu;juYpi+q||C>J0
z-1t$Hopt9YP}akPf0&9fp8R<_KYQ`_rNB{d{#jZeAHEyq)O`7A6iNE=cW`0IpTB1#
zlm+nLwu3+*e~C2%c7ym^I$$Z7Kimw#5Wds|;xYdElbB&B|2Fj^hw*Py(k7gL??=!g
z_?>)!NWLuv$;bJ>(^h+eKeYkaNxpFtXi@wZXiCxiFp4K)_^(r&LM;CPz0l+M=&i>C
z#`nBog+x5xmgbbe|BU(t68Q(dfQzU3-gJsd;(v7uAerAz$<`G9!}JqK<-baWfHb~{
z-sI{0QR=A4;H%pJ&hVc^;c#gt|HEhCMHc@*Htc5eUyg=&4nHarhR*VxKZF;#d|y3%
z^f-^dky7dT{D=O9r2@V^Ri6s^9}2*8j=$!0(9ZKY+d;d)&uam#h~M!wEEV%#zKB_r
z@O$=SqNV&*anN1H|LG)HF7m(I09rY}{9}Mi{M(;lu!6rp$LLD_>+e8y75|U62e5Hh
z^B+zDdYM1`2TauPBUVFAE#JHypq{_Q3cs)Ne_jrQ4SZi8%&C#@6APtH{1@nu+RTro
z-uM>&bul<w`GF#UHohGlzS{XkKY*o!Z(9Sqo&4tOFx16AM2XaH{=<KR#oEJv_6@jy
zjo+t(?q2>$6Xg5&t2Tnz&-eZtf&={Hd%-fu=bwe(5dTriZw~WaInX`AKStruDF4=R
ztn+og$Pu(L{>v26j`NcTpzH>J*Kw$x;HNu4V3KeD4ZN7*FO-4hrj@_28^l}u19XY?
zHb0qu7<c$P$o*-){Vr&m;m;j_?z?=?IAF8<82Zi3@t^$wy6^GtQC@VOpKpY~ef}3z
z?^)pY(}yn>`TajYnXSNj0;-P+zRLly6QomPv%TPJs<1i;tS|fv)KT!`K6v3ISV;#6
zXTgvjL>Iwp|G-68!F)QDx(V*zfF*Z90VOCr1U46dc?vFzAmAmK$cA}u!9_Yh`v{y}
z0el53zXi=t5L*iYf5BzCj}#!_9)@dyf}*u>CP=`sQYkE0kV(&Wh#>uS5RVBC(MNki
z1vbw?FifD>4qCWi=3`(Hf?(=xj}%mY0nXzBdpZE05HN>;ofI6*hO#Junv%=Wf?5*{
z#t8oC21~5qn;$TjIKjIVfu9mQRgA%S!KX(0c_j!~PXHtewxvM#X@L`+HIf9;lzmSY
zbkh@?BKVvR$Ekw9DXE<%_>+#F>4Jubz?ms{;R3|71ZKJ{m@U{tm*jH<|Iwa%R`A;a
z&~gPQ=!we{SShELFYpfntw1ojmO2ay1(FG%=LD}%)5dv0ZyuCh5ZsD|M3KOia<;_+
zQ3fVcBG|_TC>4azp}tH|`YgP-D9E7`Wx3#`M`8Dp;9(B13c(}KK(0~{LbZ}A!TSH8
zx>``%3+%GM^GnFp2(<rE;8ZKPCkJ{(kVWUrI)RSPp!EU|Y7n|A$f2(120=4rVj2b9
zmtek0@J=iQng#Fwh2LX~AaMY+R>Ax9Hf$5*QnsaCP(@EuhoC$Ipi}T71<hT8=}nkt
zw}5#ZI(r0>l#;Ms6ZCq);a-86dR6-bfAg_k{Q{!}+6Dxx-+|zu;Mi5L3<-Mwg6?6#
zb^+{;2wG>rIV$j^MACJ^+|!_q334f^Juax+1Z6h_^NRoz0wz6;lY+{P08@fLW})+@
z;1=axZdnEOF3^2juu2KRJAxFFm=-wD1>_mQPzo&F75JQk?pZ;`L4Y~IL^QxX!6aq8
z<^|j64$ytU_mopu5G1U{d=~|K>Y>F}cr*|?j|%TLLYbYAOTo6i(98y>gYbRIi#iIe
z4;27936(EkGS0#sQy{ts57FVqRah_&huwspuE5-d@vA}e5ZXNogPy{HccINoI7256
zZ{e?3Fz6%P6%7_&;ry>K?<e$W2JjcAeg~g|ge$2FAy~MJ_TCWTEcMhJ6UK6yU?Nnw
z^GRq66NYC(K3w=S1)&kb6aKFUJ!jS3hJ}+t4=N8t2?s_Y9xZ&Cwv-s*3v{z3R@n72
zq~nAyY{yhi3E!r)TfDH$5xNqD7wIIJC_Fa>EvJR0UjQTtKcElvCJTR{)|eFGXcFe0
zDx9UjDNWc;k!ZTGmNv@_;VCQim7Wo9+X}%<Vd=AQH%oZI0ZOxlF;sKT5pGV!;923<
zPXWsnz9)z7JYm{>sL2=Ze+0S<gkMwUr%?C`r6<n`U#7wHLeB4yyCAF_hq5AJ@iaiO
zuy74%CBjh~xK=8B?=B^W%7m-w?{ZP-u@6|e@T1?rb4eI>29_#>{*>3L6h`fX!7AYc
z6r@)RAE7Si%ffPh-{9x0HWYBx34ePPq<W$GH!R^*VZb`L)F8Z0Irm0k@-v_{2^%Px
z+l;jXtws3U7ckc<^f(JUZNev+P}weYM8o3J4&hHvV6aoTgpM0sLj6V1x`lsJ&aX$f
zggz^LO*lr8Y_IT;wGT@Bgxjdky<Zqa&-Z{Z)Chxv!iizfhJ@u47#tQpdKh3tSSN#;
zQQ=#5aP7Kq#TU>$CS*}saa<^=2JMFM_4gq@AuOVt$E2``I?JYnJLz|KQ>b!+mRrKH
zJ1~D+81<tSler`ONDuU`FlZZiW`#D?EHNj{=V9=ka7zkYn-?Ak1h_9;?*^Y1glHGX
zvm~sdfBs`D@}=zHQIYu+<m^Nbhr@)uD3G>O2hr+0V2+~CPs24Qkz^Eq4`<PydHCca
z@|mT>sjKLF%2m3FZc@$7UG$C;YCJ?88zJv0a)^b5m+0MnVDT1h%LnigJ$4;l_=<iC
zhWCD=?bKiFFZyCFXaOQedRqpHw(@`li7F{92o~`uZxtdcr~>VnsDxhqp`wqG(6%lO
z6P5i6o^a7j3WyP+RTM-<ie927oa3Sx>f$;fTDujlofQ4m2*D^((sE$Yq6_q!i4heB
z0*e(HXj_UCaVZIKO7s==GsTNC=u5B(B3JqeB#Iuq3hcDVmo}m#(JuO&qBU9c8ok0(
zL_%uSN)?@<NFYs=NSkE3DDMR<TZU*V1xn9|L{i9SiV}L^Z<c7f27}q6WLx-@Bl?C3
z@w1|xbim3LZCC}}d7=w{fR-=1_zC0+L^*Sy6^d+E0h|-9o`b-7tLQPhf_*`xD}ccw
z(WjfCyI6F%6+V@Sx~L_yRFt;`lPMGFsg>uVsDiRs<)TaUIigFVzv&cIA#$SvO{M59
z`p#;VXqPkGt`@yXamZy+ZUJ=Gh%R3ORx6sOo|G%1pUy*BoyfX!AGFnr-ro$tt0Fli
zdK*L?6lpbz+^>PBNhJLOv}VzaEqrPd9ijJgyJ+MPI6Fk+bbjp=%}#;VC5kq|i*C_C
zAFv*g8_ngK$n$d;>=nI1+gqP#-)VT!FS0%lmI2W-R@&_bMYi<d4T)Z=g)_q<mn<k9
z5t(Rn9u>WQ0ut9nt>>^7V<KNZ)QpRs`UtMw5T(%KO^7!9jCGzAEjWN>N)%`V@tYzg
zrDbl3_S2quTf~h3?T%<a-2|8x9Ug{HGonYltZ?zJNVgU1H7ojJ9hA<A{0~FvJy8i|
zIp;;LIWTx%l>IiGSrDbs>uyox90e1$;sna*9Tg8h2AZ8%Po1dt;zMQ7;vn85ffh&c
z-c(>t;xp3#&f*P}#c~k`ltRE&d_IHfyKdsAC}rd>zD8+L4{_mEV4mU!={M^o{*?<g
z-r^;X!Jv<LJ7qb2#f|iy^b<FxVHW=46bV3p_|R9-9Voth6tp051`7hgVj*2!2obw>
zL)kI$gY*Xt6{pjMmN0QSZs%B+hKpzE17H#2&R0Q<6sK*1!Q<jS>Y+Fx_P>w8lj4~f
zU{T`Zv~5L;ov5@KBQ8sV-B|Iqw=kJF@n^@ta!Oo4%`NfbH@}Bmf;i3qTB4Xwo91b8
z9HpO<#GMQ{lPtFO!;m#aY}*5vDsJusPntM|vW4m5I9piC5dZH{U}wZVwC!YyH(0@$
zCEldOV754I8@$L7Cq=`Hv*OBEU@2Fe*9xpa-2FW)6^bh<Lvc?0&kp!>UR;q2xeMa!
zP0&&#Ude)o#a8i(pJBH|Y;poxD%R5bvP`_?2((=ke|a9BmW$uf09+C`ehyF}-kS~+
zmEtZb)KrQ0)I({txPiWxaalY_pG>I{Cwv2gwPIB>ytpEM-4_<>#C_@Tw_cpYf!tLw
zVlg~vV(ZibBpSuLdttCi%%hF9S?usW1Y5)r?htGh@BRs{wTX{?0nT=@k}mCZh`D`G
z(<%Nv4YV%theC*Vi+>IVOON;tMTXbJ;Z$nx70Y+RnLhEh2cWuN{N+7>0dX^BRR_iG
z)-t#;B+jH3kYRBx^+Aq^ZE4#Y6{~cZ+I8`Yp8&?hA#{mrT&({GN^gkA6JU2jY;M4`
zC&itVV4D)p^~2Il@q7?;-x8PZh1_lNi<B6=BW^1MHZ5Mb4=pp|p}hci#eXrWI5H~^
z3<WwTelHhF?}@vpA#h%t{3Nv97ax2Ov<2}k%5pA>@7>1?Z6%JB<vc3+imndXNrLIl
zkiDekeP9lfjnBhFN6D%*04K@R^O%dX<U2|^xkv(MFz70gSHXgtWbFg=-EMcuJ<1_^
zNWv(j@RXdM0`QWoryGvmlB25td?edw5A>Cs{{u8X$!IGue+i!lH35=We}JQblCB6?
z3X<$y0TaOzJ$03ZNSx_wp~obCw0VU}e)$b@VUk?BBN8e3KJ)*-R3-_Ghu{f`tr*0U
zlKW4?V3g#-0{$Y=l8>bjjFBYn#sbGm?4H6R#z`uI!E#En;~Y%HOS-m!mLOqLD{G=;
zTP3j5k`vFt(IiRcQh1mw>7_6(MPi{A+EmG!F=$DXlu_11n=Xl^?-^xCR#SrIjO2ws
zp(azZp6V!B5=}28vL(ZG9?y}S@_+3l+d6j(stY8i=x9<XQP64poTQoRc;_V<8=&)o
zB#6opMG_}mRa#ms+35lUB@(X%I8iFukOjFi$#5iCE=u0|2Fl7M-_gC<OA_hlpjAk=
z(=WDCQbciLm86TRT-B1S3J6@5cv;Dp8p%Tn2-Zp}u0rV*35!~;>Llq@nyHt3*$moM
z$q{!r(;#^u5mRZDj8YM&N#aU3;F=}nlK?G}_t#*RTP2yayS7P;ltyirh^_+bkX+%y
zr%s86;>|9}@qJL;ExDde5nGSs5WRh`NlM7!UP;XNkm!^AN@=BjiPvYaJ0QuRew#tb
zdfK0cBtdj!9hO`hg20HR`8v#xN>02Ff$Nfn2GGVNKF>k*xTL)vEH@+#TQIW;NqG$x
zVNw$FCkCe^kN-y<2{$E04?*IVWZ!wXe_K+p3MTGIQZxY5lB3n2%}BDSbMdYul73aQ
z5-D{*&q)r`<<fhS11xBpmt5`uxG%|}YND-l3uPaUO27C3uGvXf`og@ubds8W9Ha;5
z!09N>$Fb77)Jgip|6tcyY8ixti!_Q(9Inz2D81t*J=qU0+@+tj!n}vno=&Hp(xgZT
zcuDVm1xw!2T#BQ7q}9}L<}3A#0jHm|g*F|3>GJ|CNr3bjYAp+tuAp2(kaX4i&=M?t
z@fFBfL!=tYcpZ~!f5y~8rMF*)M3^+2vL4~mC$gX>Li)5XXpz#dsTb$C^eFWwoRFI6
z{CraS8Z`(+N!MtgEn2#aJdBa1tOph=o!bD;IB6W+AUY+DdJ|Z@^kf?BB}ktxzyuSm
z(&&S5>a^5&4#Xs>e;+I*OLJ*|N|8RG$7E8ayJ<<&q&s#&FkR}^4&52jrBt9jBb}#6
zBvZPL2QRXu4g$z!OYhMAxE!g)2)k#c+bMCCD}BKZTJoeHL_r{5%6I?*1yZi;N0={^
z2E2sPbJDW!u!!fSkvULvLHdXPWXyBcfFy91N+YTvUMBr21dJD@0km6`OMj#T^ChXJ
z7Gf1r$0T5tQX4ujS4jtj&|EF`qHlO!mTKuhS0gQ_bWp97tA)T7>EbE)StqS&2TQ&5
zF)diGN~`Hy*C0(7Kv|=7^KJ^!nxya3PqtaQ_adBWk=~#-*H-C^Es$uF{&xx5+NHr7
z40cGP=>6I$Ex!YQyQIuK(7L6s--O*>=?8Q=?UQCxIMOeb%=&l7vaCPYgEk_y>;f2-
zdQvavb?G;kp?XZ(MX~R=bZIMSH>3@bP(2}CwiYatQeV1)GbR0ng2$WEoFUk|B@JP~
z``glMW`H}=?gT9Tw6u`&t~1h2PH^z9^jpe4%}UpeKwwU~-P!{+_oOrN;F*`Imchh*
z>8ErVc0t-ecT5+h2Ok8@R#rn*yrZ(OJ)ql8=GKZqdztAiU=Ff990)kd!dF4SN%pA#
zI-O+!)CKP%bEPAOtE`K*UpHAVeVNEzwl4rI9<pU@3R*p7#S}Ss$t3OI@s{0N3*aL|
z;DBdJ_B`dJ{ABTgSOkCBS$8N6kl7Ri1j>%mHO(N|`}SZ7mbuUd8X^m%DCn4MJ#A#6
zG9#t@!(><Jd>1Zznu5*<*%18)x=7h)Up#~@=(w!IAEPH^AF1KgNtxkO2u8`gnNSlg
zdy`JiF|v!4l8%)%y@$a#*@^_L(<#}(cyPwcoay+JAlpHWhlw)99CV+SRXvOaN|IS<
zKTMVd`N4dOOzR5qR2heIQfV?SZi!l#rpunB>|};4eJAA4$lmdWM5avtE1b!a-6+J=
zvSkltKxvL_j>7q~G9%@ra%H>cAdn|pHw!FZwvvv51+piu11prZo&oKg%$;)B=Vj4U
zbh;pu(yfXj+3I!BQYvddhFM$7WCe#{;-W0I5};g`AA`wUlFf0zS|JO(0;QF*2dTTF
zN>*75TD9z!2(De0jR(L|jqDAo<=4uNXd!+@mN<Zwsgs@Sf{A+BEA$JzD)XQWZ-dOA
zD!+}gtq(z<NtS;Y7MiWH$36j1i|pPK2)4@ptpc%4=1<wEcG(t6ZFI=aGO<9NvV0k6
zU9yH<5bT!iq@PZYESrA7*JPD_(A_Khvl$cZlkKA;O216;F~ERq7Z2itvSkMWhGY{I
z7!J$Qs0K75v+nNz9F<+6eet@CH3QvavJbw-;J9qbZeTZLBQL}K3EB2^Xq%J;Q@A-L
zdzs$4H)Y#eq4bt)3H5*6mg&Ob;T_qk1}K}B?LUu6%*dXl?`PeWc~O)*E2}sPfjOC)
zV%K{zxz!UA^RkOC!qR=&nKz+yLH6l-V2iSFYOS=Dzq$&#kIFao0<)7R)AMI9|9v+m
z>L9;IZwg0wFSS@X$<5RQ;4HWO2Y)md`3))xy2`yifL%9vE?tjvm+zsIvxj^$6^A|L
zL7T16<|U7z_|{wg1s(T%<a2Zm@Rk2ZX#hWY9VNW{<qJbl8X(_EeJg?TKj=jlB!8m`
zAXwfK2umUI_;&n7j>-E<pfgl1raWDkypsa>aCzN4un2iI9Tg(w|G5Dim%rOd*UwML
zbLl$ONjdid%ty&z{S6>mzQ+e%#L4IWg56W{74$8Kc=;Mi{U^x3>w?`xd7%WeI4wUw
zw|$c2A_`KH<yYyAnj)`>f<UT#IaQm|<gtmckS<?I$M6ifZ7F7UM*cxPeZ?|U{_F~P
zlO?yOw^+7Z?E^JA@^h4aI4ghjAJB5;%P1R{Cr>&ATE6@`b;1?MN2vZ-C@-ch|D1dq
zMRDiltjB>}kT)!Y`67AO?*PT})LF=t$k&8HS*cu80WZqrA5xpO^`d<BF4!%Xub}Yc
zl01*jL=|$m4B9H?tDGQMB~PWlXtg}<3M4Me3((E7v_}2~bzIfTkJ~}uiu~VBXsMGw
zMRx1uixiDrl|L8{tU>-}Iyf8UqC0S{N$&ADXwCBATzKDNm7h3<iMGmLWWZ9J{DI#<
zY?rV99K;T}Gd(Mv@>dj4(<Psz(@3{mc@s<8BY)#I1g^=$C>_=-|F;KP`s4@0z|t?j
z|2GT{$bYAZe^9Po1Mwkw91D&P%Rk(Md5*}Fs17hHw`Ni_cU>O3657V(2kE3TE?-CQ
z`5SWMCvav$o>UInq&#9hOiam}egwEF|5gETOMaZ9$J_G3VSqdGf#m?xayC6NGxGb?
zA$C{p@g0=S%HQvTmO1%E1YEl(-*XP)^Kw@!mACK9-O^!cLH^b{fJHfni9uV1b_=kh
ziXD$Z!cLJweH`|R00w}A;?K1Jj*8dLfaaoju@{zH6&I*j?WXushCz2l(~kfiibTq&
zdn#I11M^bs`yF0*D}w3A?W1^DX@v=2#e?U-<EMBe2AIDhxd_Anh3gaWB2W=R{gy$B
zdw;;;V8y$8Knqdy{|A9%3XfG73{}jY!>WZT27dtvSNuxtP!Wo$Q&1MExUm91q~nTR
z&jXxLtf2$pNyWhj;Y^gm@;McTqZL`Nz(kC~OeN@8#nvUT8>e_l2i>O>o4Wzx75`p=
z(gei|e6S=c#_0TWTH#3ttR%&aF!+?LXs2IUied>hp`|K3yMU!B7VV)dU2&B*<P62J
z2&~!}1&10CGZi7x6oO|d94KFyt$3H(EpimK$&f#*IK2c0a}_UefaNJF*^tjygiy#<
zpjht#tWdH47+B6J%=A(`uZX1={RPD{^I$1b?8F!PmKG~wGaz1~SVG+|rHa**S}0TG
ziXnGV5lyE=Yq_GA(xjIZvD8vsp|A^s?n=ey3jkG$KX+lG)r!A1gLYZbCx=9h;>QBW
z*DBJcVd;uukn&M=3a13DQ@tYRe=u=X@i8UL8x*hKhIpgmYkDa*DGsiIp=L!}4dhxB
zCN~JQS{1rSVW~~g&BkcE;w!p{*rE82Ua_4Dn@@msDc+{<NOUXa_5t)LGUX7wreIM>
z(5rZ6FV?wFaWfZ#{ffr@zy=g&V_<$zv2P8W8B%O~63RvuPTzv%x*|RbEMtnySePAG
zSTiPo-ca;j1J8tF<sbwn6`>~Ro>F*I=yg*uKsB0MiZBPr-&XhqLhz2_*;jx~E54#G
z{uxEhb6B9eic9p>fLVphE1342VvORVdx~}{CCn>&gP{7pB3TH51x14!=CY`$wo<FF
zt+JjD_eYfiDl^+D`z*lhmETfa<e<DtyS1Zompvq$l%G>v<g9dZ1<ge{K*58nl3fVk
zrj$!Tb64se;k}3Q6KaF>RPMYFnwRp(1Sa9F{GO`CKFXStQ0A-b{)vk0e#-FO@WNmD
z^t-SWptPs@aG>&+WXK08$De|Hu<{2g0EQ^59)g-<N^v<n3{@_pe!?*2<P^limETaP
z7@-u<)#ym&nYVx)SGGL@Ehm(Av}>JIz8wnjC}rG37>rh?X3-HiMj1rM%~)j+g*kCb
zzyA*|l@GN5i&t9K!I=c*PrkqsmCI8ge_H8ITX2#xl$r^Wm8&UtlcHQsA!@2Jwh<sr
z>HiaG>B@V9P@SRl8i)Ba%FlnpbTgG=ayv^YG0}g+%~l@T4~ZOQ{zm9NtK8WNkgE(>
z28ldn9#stUl_~)w3Y7aNuzH2cM<|bcPI-_I+IeNtyYTRWQcTSvMarJLuv@IG@Ptn#
z${#FHU8<ZKhO#o{%>b<7MWvR`LFGyzW%#U@lup+nU!nZZ4rsNK*AMKna`6%9u2FtS
zA3dy9%BijEin7lOChC+)a<J4ZAE6r@SC!9)fTcnC$NwiEm4ZrGYEl+I1(s&zvlKnI
zC<nwa*sAnefR;982VEs?SMH_nA$C}miE~iesf_;+Q|nR=eUH&@Wxxu69_2&>1g|Oi
zyD^zw<>vpOv`^_z2dRGL{aVNkD8Hg3?4WW7wP_3~-`)b<!^#8SLT*I4nqt~f<&N7B
zzpmu`0BlV8FtxCbE05A4^oG(pask>Vl(ip2ep1;@S%oR(%JndRQ)zk-YHlfcv~As1
zGJ~P}j<T-}*tBxp8pzEk-}n+<+*NL(R<l{<I3>*Ilo7;oPq{t-Ec40|>MFjkEYv~u
zf--R@mTOV@>vvFQtJ-I61bS4(c?R-!s*4n_+p8idOY5N8TZpMSs{ASFaZ(MO2XI#1
zI}E>FR9k7kaa9@Vwcw^oq7sO^ihCHChbrMH#649z>7DGQI=K|UTQyn-aUWHWKMeV*
zu2D0ApUP(q1@Zo>CYnruN=MsPplWF()C8%NWiTJCs-$o-MD_jG0LN5cXM+~1dgTd#
zFjaXI#KTqEouEaihEm`~q^i{n6USBKw3nPvIgbH5sTyAj3sI`Iv}s1GW`r;lqe}ao
ziWae|vs8(UQ*BaW*-ohv-h@QFYKjs|398rW)tsnm4~6_`)&5>!XH+e3Kp<0<<B5r8
zsh+zAOS!5IcVRwHwG0K#rTMB&^rAnnil;=_1=XGZe>hbBcCb*T+D4tumsS7lr}tlt
zs-XmyYE>(}A%8{nC;fryRCe9aU9U1wcKNDmJ)NZ+RD0+^(x}=*xw2+e_s8IDQRReV
zEn8JXbTV#JrMZBmUBw!Q-44~O^o5Tu)#ssbrdySK0fu^1_HmftHPsBAe5}2y8A|B(
zt0L&VJD_@p(vO3xH2NItkjh04iD8w!Gvr59M`-m%RqgH&7*hq)zC5nlMoFg|s_ID4
zCRAIv7@Sl+T@AOVRP~vl-Bfi^EPYFLfPP4~Rj!4g-BG=L3fQz&wTs>aGpdr8;OSiz
zLjtE}Ri9F%Jf}*21K7OkUoCXsSNT(sbU{@)2F^uQ-6Yi5suSc;gMST8i3of3XO(c<
zLH!`bpN{I&Kf$h(+U`#PXLZg9bh@fj-oiZH)axnSc2`^9_yeei+E5MPsea%s$a|?j
zr?A~yy(teozUsdgV98H?s1%m`)er20?f~^J>Ng5hw+sLTsn>k~pN^?7Q6F)ry8d@K
z6Q=%?T7JXTCHp~(P&ZMUDpLI`g#;(n-RCj0D0PnYMeszcrPMzcr#`$KUYt_b(*J{r
zR}c9CoK}}yhQTB?`xulatFKVHDNVhXx*gNi573uTGSu&1hHF`B8@k1itxmlQmK=2r
z2UwoEs18%gSHDMBm<rT8ouKTzdO7{gFQ}b1QT$n?-ufWWV)Z7<0+py$J-|xU`{_d#
z<?8li3|>+n$_7@UzI__BN_8>i`K#2M{(yM3y7y@~Q>)feXVDe)OLUa3Q<qY*xL!R)
z2brttwbX>spw6d^Y_s|fon>3p?7LL7XjQ*VN0AQodmL!%RNtcB<}URknZT~8+j%h9
zt9CmKZGCEYD!2Em_g#RA0rk^gVWNX-IlWYGs9lpVIHC3}2Fs-SD$Qj|oj~20H`UWC
zLA#~SrVR3J^(Kl6@2G#n$;Y~MTJ5qOYG%}*$Aagsx{CJRS@mbHf@e-`iG#!U)HXb5
zn^zB0KKj18a2ZT2sP9u(@}l}p2MpS3ex@$~9My;?F=(errEtSullc>rIcV0~gT+y^
zqyuwt(p0>OL1zsk3sbVXXsi^mx@r!538I_k#Z=7RUGokdust*jLon~DnGA$(FHQL$
z0N$Exx;N^l8K9b_zh*gY)&Uw#F{T!%iKTo(kmivN(1JBlXF&_mc<q6~W14>l;8Un(
z_7z|e8bvuAjkIc_*8?8cyh|a}3C-?%Sc{VyJ=L9~G)wZ}MYQH|vJ|6fp&qqZjVnDP
zahib@7(As}wiDv<nhh(VJ3+IWBB4Z0XB@Pg*64o#maJLIgg}ZW<0L?;X7B$ujca1*
zqFlOWoj-jPCqrYMhMFwR++R?Wt$C0R_BonoNX=P|JrkC4HIGoBou^??4J2Rl$~t&h
zpmFklI-hNQTZDxv(wuu0x{5U`>FF)eRK)<4Y4kUs<dP<r&gB)F!_>o9so{k{x=OPv
z4g%Gh{sLf^H8U9ysL^Cy!SdE>20sSvipF6hK%K@)L0!G3umR#%HBZuExj_?U258i*
zvw8zIX*PU?^=Z|7lm}<pG^bBPTf3%#vXLE{Z>C_PQ}cd5=GUVcrEu(;CW&6Dy_z~I
z1omliq9NX|>7$<P0Zqtr0E3#R%fUIM>HHUKH>_#HiD~JGMo+2OQBCSi3|`lqe3UAW
zV;YZ6s2SH>qmA^2Mz|J(Q<}dOaOSqA=>LOu&42$va9Xpf0<;;;NDTz;YJU6=3pA@q
z+z3l^8n5p_yQjHETkgE(N)!g~YxH|yX+hI@1%rzk4~oC+v{Mw%*lXYMUxtU+L93_s
z2S;tvZ{Ts#?xsqsv-V~u%)4l%;ZW+Toe0Ma-LxOlHs!8W>7mp^`|F3mJhktYL)=H3
zPj5J1ZTu<7`Dyo3qlLfr$X@^f+PMhm4Ad^89C?WL;4_%#F>O)L19*r-wTJdVO_+A&
z63B;Zce!Ft5!&Al!^8<~6Xh6AYLowg7g1WDMzBO{&(bBY80|h<gjlWo7?j3o>urFY
z(!RAC0`c0M%@9b?21P+xqShxA^F6IyN7oO|XxSfuB~v?0d1Y&sHk&f<+1hvgK+Mq!
zU7_u)ww%8DoU6TE3Bf$=BNbrD*V@bAcY(H%y66hEtG5B1(>_dZ`}5lUe!wnh^GCs1
zq-ER&R;-P4fU*)TM*?M~+82Fcp-j8h8-o|MS}tZ?Zq;t0Oy?!-)-AA9q1{se-zv3>
z^uSbUv$sG^wKm{;uwK>%PC>9nyZr#BR;x|;1xl}I=P5p@)Aknu)N6NcfQhTxv;B~3
z&^{iC**9vl=pucScKRp;nzf-ysBY0ttcIhlTI=6MFyE$S)1%$4U9$uxI<(W&$kwS{
z^$i5Ov~SXe*sZ;|1S~yT7G;#KY2S5+rCzN)U0UkX{!RIoe(f4M_6=wcQW<DayDtNC
z8PfXErN3eA@6@$1qK&8lHmaSZw99qvMk{^ebWD5rS4fO&2Pv0&L))MPHlcll(yo)*
zEyutzrM1}syEnDtT>!VV!<10It@V;a;EuLz0fW=p-zZ}-qqWc#<-6K9G680_D;vQ%
zr%k1*^L_2eLzvlu*22U*7qzLs(jn4Lmqk00z0Q?7&>VDs-vn^frC$e+ldg+)IcHtT
zL1=T)t)_B`t1f*xChDdO-U3c{-ES<gc<5f;4gpWyQy;^Um+lCClEhoLRSW?iT_nY#
zzPgUDAmFDvbq!wl>-ucyB^sdn^Bc@JShtpn<{`Sj+~LzP-4PZfLUn7XZ#zuaLm#~j
z*IDQ?M1=0*lNgND)$Reyab1N!22bcFDa&<I*Yp~cMd|W?0WDg0go>3hx}<mDeXQ;e
z188x&QHpF&=>!_O*`28ShFV2W>lpNAPSUl}FCkgix(TyL(K*k;ZmMqbMa&{icboo`
zO1dta`rtBjm+ZiDMz@5H4w<_8s}Rr9?b!<~TlW)PWXaJvJ`VF|b>GgxwOpM8T^z{M
zwbH`o>u%E*8LS1myVO2dsN3}foI0m-*@nrS*F7Eto(sAa6mk{mu2ldO>y}2qwGy3k
z9ZZz!mhObXGTnnuVDO^uiOn!ru2YCHcu80B4YX9~^kMM6QWyFO#H)0=V=!2)o2A6x
zW!>gPU^Q0Vl^bBK)mbU{zM>m+2Ue#uhC{GkXU>PVt2)^P3^wS53`jKU{-9%DlWzQR
z*lpH1u>o3ihbafts`I9UahvY5KVh(4_X_=1J9KT2Kv}2mF{+4k>DCrtuv=$82xUDw
zYbM2S*K~)oFxsn|+K)x((^aj-diCo*{2sIc-6x;ouQsgfpvQkiHy95SqdEnZey;0Q
zzW{7Z_c?_Z<GT0GLi~m<mV)*Po#{QuP3r2XCOoCnQRH+}7wrLmZ|Q!OLG^9jXI9#w
z?&ylC!D?F95ds%ybSqqe-PKvCrZ=nmnhpeWx*vXk;5}U$wHD6nI%u=LuRGQXmIdAO
z8=!kp_wNq?w)#@)oH?p*bi*X<^ks1vwAW|61A`9wWNM>u)cdzV+)4jPHf<Qrdbht}
z*F}GcI)YvG-h(jjrtdomHSYRudhR{+PwFuzPyN6eDD~1yUV*%~zVRzK<D(Z)x38~$
z<r>VzPak^+oc{Wt91I5N|NR<Rpq@_&tswokPe3kMAF>4&Li8hXRKz%@|6u}XsJ@=s
zFv9e?F>o<l|5X-rN9f-~ThG!+{n|?a$Mx!cFn>ZnPB$e^>cf8mh|=d#i8@+8N{NR!
zy(SqZPU%0Vry^comj*8q^sOHOOVocM0?TRrb;@)k=?C6;49{P({yFLxO40A59_>{9
ztvIlz>5Hh8lCF274Lw8ubqxm3=#Nn4DpUWe6oXm%nAfqS+4>~9xs#*+T7uc1)$gJv
zs9XerV9C?(qlL}a7s}v8fqpRst`+J_Y9V({f7ljgt>^X1B24>&zQzntr0)m@Yq9=g
zs*soHUpoWcrTWlmu$JlLN-%g)zn)S_<@#Z22)LwwU>gip=&$lYtJHI;B2uLve;k&o
z^{I5azpQ7eK&#Q;<3pfUZ~htB75#T+XsNU6Gird=>$h%!-K+Yi<{;6aPmy4-Q6KXZ
zK$E_j(h<%2#50g+(Z5Cgd#(DKpCHht|9uLeUB8SPl{)l>K$z&%_iVsgbm>D%0lM`+
z(G`ateQ7AbHT{-PFqeM)W(vdx^j4ieObqH@9f92;eaINFVg2!!z&fHoLbcaXz4u<Q
zUf1Vz0*vVwrm-aB`sb+dbwe+vBk+X2MF%jc*L?(*Dg76-aP+3$bOM%c=^v-Z=(c_v
zopJ8yYwV$OTECulh#9@D^(f$7{YzBznbkLZ1~8|uc@t{x=~sFHo7b<_gXO;7mzwVv
z^exn2wWuGYD9hGRB!$064gcJLc{{`KqcCW1=-vf62SWu_l^qR}N5JW1c$=;`I2%T`
zLW_%`fl|n>hQ1hT*mX1XQa7!;VP_gfJq#a^c~8R_^)7fB1}WU|HoQTX*nJGoQq|Gd
zP?!my{0!anhW9sIsRB!YA^BM-3p6ag2uneR9}hrTuwmpG42Bq%y8|3EENp~asG*bo
zOksvUw$g`%!wsL)))ZmTQiDpQ!PN#zj~jLgFc@XHPvKRx;ahSz#*jrn#8ZYDip=8;
zKb-()f+1T8f0GQ&7A$bGA#NGuQVcuj%4m*Z#1@v$8XlseX|ADzGJbi6a_Yd&H~jQC
z9U==1|D(?SLc;)^Rn8f#^r}2>_=L*Q7YzR2fVIf*>*KIgY;f5QH6;e?MOZ2|Ja!oi
zRA#tC0o+ByX*%(g8~!^4*De`e%K}S<p<@|XDh&sy$*0Qj5aqS14R$*qaM`eW2kd=b
zV<<C$r`B-vK?q(k)ISBmIzuZ}km?OxlW_m40sp-jPlbWu3ars^;0dT{GL+Iy!Dd4>
z_4BkC;u9gzYWP}(1!^;t+Cpc$;Sc|xF0rkv-h{m#!#6v?am}!T4v)QtdvdtcXBc$_
zf4{+jzPU1BSQ(1JL4&LwDu)aqv7ikbl+iFZVu+#2&8T7f4Y+yT&=v!1%+U5S)@9uA
z7S+UV7#2u;!jL))Lz9Mi3ihWA8CL4ry=hqUEm&_EGAK~JZRn<F<Bs7f{XM4*A1s5m
z8N-rfSh{QQp`O@T!vn`bn=`C3!r(na-_P)A!Qe%yg+;>?F3@djY@#UgsPVCGtfZZB
ze<%#u8<&(~(81V8y)TZ&#Eq0EaWWSE0Hw~xt=Myyx)_t`vX-k+L8T%$BPR>m+>JX%
zVbH_)DqR-vG<s7N%ggu+op`*BuS|gEV|3UErM|{jk$zw5XKbZ@4}W9uMsNlgk5Iuk
z(3r}A&LHC}RNfCZ4j-b+4WY&udPjsAAEoMBxN!ru5JVV@;-Mze_;E2jJZ@a_A6QNp
zkITSv(%5(lN~4T-sAw2%e2{X?F~+YF;b^RJ1s%=ej30$!E~kv$?*had-%Ef%f^oVB
z$`XyQQcB{qaos9v?o2Z7q5?s(@f3CQr5I0TftYH1R0{XgjEf9Nq#JFi(3WA$b_RCF
zXfA^@nZ}Qv!L+lC8?FM&HlF<jayiDR=K#(cQP03LW$fMtkZ0t53XpFU-U28vhSAxz
z(D>1V_={N28Jj45f8Kbf2BQ~@9&~mtGG;QMyV&@19zcn)kve)yjgg;X7G=ia5~#Uo
zY+M7o<;IkU;r%6J8~IdWe1VdImB#<59$ICz-vDLR#=K%!x@;Vx8c~fgi*B>k8fR=F
zcg1Ran1>arGgeqI!+K-&GI(*-Soj^}8;r?j7;H2O=|5yN8C@xR(QN!^3kF+^&Gh$a
zHHvA=ZZmSJ$k}dG{03Tw(U#sVoyMoiVX4cwJPCu>j6Duu={3$%2+(KzpcOOgH(D)0
zkRLEM)x)<z<JNCM95O!nKbRjj?$$zn#JGp<PmCH_+aQ14n0yKXW5xt(5*;@_Lci4;
z#^qEvnlP47SKXv>?_;1%8SM+<;Z37y2DDp76ZOO0HWsHq*&XA-2Ou|XjI!<koH6Fp
z_BdzEFhc&GaR=2m=8a!blIp(E&jTzAM*U5gUo_THHpABBISO#pbTAg2b|%L+AZKq<
zQIO(bvU?cI<!FkaijkAaOc%+VO|JCwa50^w5|gWGh_Xa(rk36G#&9<oe+7?+=@q(3
z=4nd*6xzH@{o4V&P0LA*kLf0T8PeC(RD(f3(?f5<Uw@OB;^Y8R=i|TvO<z;JI>_{8
zGX#Q78)+*GF$GcS<Cy7L69z*~w$v>dX5v!CHr(_}G}Xx?Ox5%{h%}v{$o9BtlOu>H
zOcr}!Crw*3p*zY{dKH7wrd8i#En-YbRI!aU9j16Q&h!t}ollt-DUlm*I#1mc38sf@
zU_Q|#tOYo2irA0EPckiR0+wvLY6I0NCPqK~x4Bf)UJAw2OnXzolWy9V2Kfxr^Yd7!
zGbYIlbZ44a55bEplTSQAwn;*@j~vra^Duwb^zNImn`=s^+DD#g>^;cko6OYvQeb+f
z5(W!R&r*TzoT<$lgGHt<=>T7BGVcUtEiuKfgnX&#W$LjgGxc`Ci;JeyLs-jllkz3d
zE}04%ptQnNMcK7VQ>Pn1l_`;0Evij^^!B`Lx<_Y)8k74vV6~<Tv<qA@jlTvHb*8)T
zViNVHO>OuSUNzOzi@Cw1qP1wWn%pRGYclx{05qGvF<^!*CMM;mTTLeF&}uV@=|$3R
zQc|g?!{p!s-JPZ*=RoT+g=t~8+w>d-<UJ+<C6BI|L=Qut*OY%59`>2Oq|{2kiA86t
z0aJ+&z@UkH4RS*!Ycd^^hfRe!nD2-wo!-o&rcc#y=DI0o5j<n2X(|3b<EGMnfE%VW
zXQ6w-wB}#9KWX}%x{9VuJQcLuG+loWT5g%V=^pfLlP4FJ?wAgpgWR;q_Hlq2)5=m<
zxN8zoiFelYl9k>rbEfV^%;}!#9m?d+o5WQ7yKhq50d2wb4Mk;(rUq*Avo&+6CG4n~
zL%Wup*}nh+_U0Pudvq{Q(39$D?sx<OF6K-N23^fgTfyRHzS{(vyV>ZBCGjvjQ!d`q
ztUO=^>SZpVegtpxsmpND$Gn*Z6TW7TwUF>LD__K*zxiQmZVE7GP^U+rxo8VOkoi3%
z36=(%rF8u;#C(@p_>Y+@DCiC~ucoam%={E>FyUtYaTts+moJCvNOPACJ{>n-ewFHU
zC(Qp*b@Zfp+jdxrGS5&qVzk*V0rD~C*q?#Lns+)vFwVS$I(1K(Pf<!V-n@s3jtS-m
zsP>U)W}XM_w0ReG*Cm-V9pO{5`GYf9$`rG^Ggwm1n};BmW?oL^oOJUv@;lb08RlQ<
zg4h|e`~eU%&BYW^XPE=3n<Lw7qMUw?`4#GWJZolA(_60j8~Thwo_YU$(DKbE=(S&9
zUQ-3{3(e9n(9W4(8ig0<&G+f7aKZe+I+!mquUQ3_V)L8NL!iXGf{qN<QnRfT5@qHG
z>1yLebIvVDl$*;wz+^6&mlr~!!u%!uW-HA<JPI{c=E^j%RGVE^0jo8KYvAt{^H*oV
zQfIzFHKKa+f#<+-)%=MwOf;BRbHUkYX6=EpCbRu!OrqJGw*s?nv6?61A=qk8A=Wmt
za2Qy-d2klabeO|L0G;NkTxjbuucumgxB0Jcp{B?DR3$jCnGe!q+-shrC$7)D`x4f$
z-|T)3x(CcFo`a=9bBY_phs<}@VoJm2Ukl*Oh`E?jlcQ$qA3<>Vx_R{xNQ{}&&jA}Z
z-==Q28|Jl?jhrxt(WUT7^V=54PnjR92koZ$G9~wJnSY_J@V5CVC1&rKm!!b8X>$*4
zg)`=Nbzr$`4)KNDthsj+usQQTy)bmo{5bWc&6`WDD<N^;yhx$Jf_eMXz!uG^v<cZ-
zUcLo2M=d9Q0A^=NrJskrrS=*G9V`I{VbIaSrNwu$@IQbT&X)J+rRZX*y#bo5Wnl||
zo8=ajQ{62-8zAmsX-Ea9r$rkEnwMpjpA`nZEw<l6sgLFKQ2<{Hi|&;BStg!_puc7F
zB33WV5<<y|aLXSXARl4*a}t&!Efth|I&Rtg8wO8UJTzcAX?gZv%s0v+rdTi9vLgtz
z7)xmjXt9>a5YXZ+>2wJ_!SdKE)F+*2@$!S+(-!RrSd%R4{sKt0BrQUBie>Cec$#W?
zvk@$5mgz^~Z@MMm4S)>G>Hk6L8Ov)FZe&^_C^E>hC@I9vw)oSpJIAsn30|DF@UwyC
zTAW>h<yopJ0g!L`vYamW6<GdS#3G)zJTi{a3zlt4OuNWpFas1@%KQLIEE_3lTxyZg
z9gi~0K^fFsv^Y?jsocV$D$OO!b;{pYSj1EjthAI)LaxfPo6bMgmTO;vcG*%^27ww&
zd@AhKT1wJEvtF^BqI_DN#jp-M^_GZ3AYQdxTo2G>dFvVmn=Q9?gQdmtIOSAYEoUhi
z(q<{7&WCo(N0hDVu$*4|e;i$RT-H?=cVt<brKL99<(sB$p1t>;Se99uTB&7L&dPic
z8G;HT0?OW~2*{A>Vk1ihLD?WEC@Mn`koA5~{Bu5MpL?I*xc8iMe*iSt%^nA@(XNfk
zBu#dec9^_oyBaq1TI^~Y0Pfla`~+jIb{%v;rOjqH+W}*`XSad@YxnJn?_r?rb}d2h
z+hG?+%en`4f6RsGLpy(JE$Ot|MdvUc*~!0$$YZ<TS3=>5-Qwxsb=e6#;G)}3F$KnY
z>^3Jtq}Pr~eH%~hlD8t5KD*`A>d<eOK-=7BcD7&UAesR?zxNTvbGxF;P#m`7odOuK
z^R9=dQM*kEz{c!ep(5+J-HTL^Il$=51?I>oFM#?%Mp7UAIx)EPqdPNZx5BRr;~aH5
zxia?9S;#|-icA=DW8_eWh&!WsA&7?=7j1)(Il_2}x-XA19&JRV9*mc$ZtTg3Nr%QU
zM&VX?@?z9{1C8U1mn$()Z$<|tQ%*4Q=#}Ba7%BkKm+{jCV1A4mIyP{U@e3s$PBCUu
zQqiB`!U8dXvAGyF0~xGQ*bHK{H`8&=V20;nD26bOUIP}&V9?e*jB$w;V&RNDx}GB#
zO>|d8GPcq(Hi|Kuy0@YkRWo2ThVj->OzCMx5Un9%8L{6Xm~)I2Y9)(fobN=S@r*3W
z79}tejzI4`W7j-5N@TE?(|=n{V*E&X+GNHXbU~#sR?t4~0%I{f%TgI*_Yq7QV>wl9
z(-{ZoqRC)<wHuPz47*`qIgA2&GUYOE(+Vt)vG-lL&u473!C?U->J-$A7=x5WyvEQ`
zqj53g6m2L<7+XB)aC<3Z&5w{NXE<Gh(d&$<j$qzkT&FVHO-45x)+!i!`YCQPGN?LL
z#ke&SlGTiD|1H@VNB_$)FxJxbSi^9rgF-DMG!r6qj7SG4)H5P(!hHjySb#w^GMrW-
zv?fMrECy(6X1w$r!f#=OQ>FMWBe(%m)5>tCq+}c8Q8kR-W90mSxxCLfMfJXR#z(Z)
z>tICL13X|{VZi7^MhQI{IvItuX@A7nMNfgp3=OqdJYh^(4`W@7CFg*3GbW4z^e~1g
z^VX|obcx~qDPzq|1l7mLqPY7RPiVdHjB$vTIRlJYb_oAD;};{04l}-|&FBcDwjJ(A
z881Hsag0&volvvf<~0X`uFOr;?s14Y^*va2V|LJ_yEDruiFlZKG7%z2nZHv-!h_jF
z=Y2hy8I+Ve#x!(+=*4`~43o#1OQ;g!&8&F>-U(*I8~`6ClQPG?%#k_J^JD&y1(B1?
zqqL(v#r)fr3aUTz0WGitn2wZR4P@@Vj}Zki=kox9nXBl23t=v$t2vYz@+(Bbm|F)C
zQ#iA_5Lg8BY$vctW-=}KqL>e&;4qrmRs|5lY}P>JH1plh;qVM|P6>YNv&<FL^&iWO
zpG{3)=a_NSS`o)|q9SWNGx<k^n7}M~4cK|+C)AXX%$yhk$rR=#+WTH$zDfDbRA$YG
z2s@1#wjAo|%xRQ@&18ybv6036?F)d5%nLIhd5Ni|hLp?9Vamx}Wq#2Ny=-Pq7;WZq
zm~X5BGne_}Rg5r?`9>X>1<Vh8F{VOhNfLr7VutO6$Tem&J#>nhKea=$g!wY%Yf70X
z9N?*p`2%$%moq<g0=UlXrFNVf%u4#VVmFzq>99}*^TjaeRWf(afazPzF1*@oQ>vJ^
zyFjgG_6K5Ux0(MggvK4_bxNewFu$Y>ZY?v0u7o<~{$B9vnMJfRZeU(`08fp~#vw$}
z#0;T}tC{(92zo8d5Ze3RWxgDW=v$exbf~v6|ENQt_n2{eFi-cH_Azj4YiGVLg-i!?
zF9+ZOa~U7hN6e&FczVo~QE$={X3q=I?_zpV_OY8ecO^u6n02&QdCIgbfL<R{^bv^t
z%>TUw>>0Co0iqaSu8D`IAtr|kUC)`JuLBG--<$?3Bh2@xZE)1aTtj!tI5UejWe%)O
zj_`YcRsSh4N7m38=pSTN{)s4@SU=I4!<n^#Dhe*Fx;e1s%34Q7fJ3a!R4sI4eK-Kj
zo%LcJu*0mbotV)htR%V~kFqvTg(DA^>k!7`$x53C;xU%ZKNWN0#d7=<E{?N4rA`)a
zmYDiQPOv_uB7hI8hmvK!tguML<j3lve;sg=RlW%dr&x9p#Ou#G`y74)SYH3N-Lu@N
z>m-QfOB=ml*6?gZ5yD#j9rQw3hQ+WF#wxi7N8zlmY+ay6v7XZTt!P#T?Kfjs>zaX`
zX2r9ie}=V$UNL7`eYE9|WqqiDLLBS2?;#n_+MEJn0_$=PqBzf5L+`CbRz8(Sl34pG
zL7L3!TMpg@R<-~NsjT}caG%Diyolc*o%O7jl9?GSMj||AveeYen8gy&O?{EoZo`-^
zvCjJfyUhBs3D_0Z6>5ITW-Tql%;d0KLxAP7o>18=k0qmWPCn}|Iu}&Hil)n>khS#{
zL~)H($cO1-)<7skN?7-nLA{jq!n>5rEMrX!f{SuibvG2Rv)n1fo2>Wf=c-^m;=xQM
z>pA7cZm~Q&z^h_$8^Eh(NmHPAn`O5QSPknf4`8({&K0<*V+~PDe?9AACHyw9B8ot4
zW_5Egh!$4RAsD;MN}V}jg14dR6<Zm#YTRQD(xdx6%SL;x4p!_L$Ub1z(`ND^%a93?
zPSy_E4?SYdYDO53S&OOr<q2z;Uhv&4@97}+uzr7lfO}aP3!w0nHA+obeJuBXf%UW2
z9);;=tWP~*Wq{R1g~37A>~DVnI>cIj0zcGqmS`6=Mp%KLz|1IXEC8X7vFzx}fa9#M
ze}@YP_O%y4JixZ2?4Be0D=8$M*j;8=b7q&VgSrd**F8{hWiz}#Ykt$V^Z^_kVT<W7
z=25ouFeE(KwkOc`Wcx>gc#Q2!n^rHj{$Ip!oZU@V^$B*>_u%=kwSPgumo57OL_fA_
z8Nf+)`e(2iz&=9lhJoy#soyq;otq9Um_4-<SP1(V^^b<KEw(o>KVj@IXbT*{4*3f*
zk?e`zK|hLJPKnNF_Oo|DjA1XQ(Vk`}(rC}H3+Z=_Wluj2k#p>)c_7BIz2iZQXD^@}
zTLSxKdV8K{zZ?x-B0HY8bV+REF96AGE#0Uo?8~d@8o$8)fo^~_HXbFo^4V|D<0gZh
zH3d;*vg>Hekj4H?gP-RjJDZMCU1BTfa=gNxMVqOs>=G(^WV2UO3Mq$ujyhp-*;`iv
z%VWQM5F+{P`VxRbc2gOMMeIGaEWgH%Eu>FX7qfrd2WAQTweRpNm9oDQL#B+q^)SG7
z_5@mS-C+CCQuZeMT}r7`uzx84v6B7zcFasQ`xV-X-e#{~jL`0|pN~MKhOKFZdM!KL
z8N@pF1KRG@vsWJmXk;rd0yMD&m>}DfX7<Lr2)KoPZWY|$Wp~rju2%Lm8T8xO!F}M}
zXTRhJjdpf0EsQ(Zef@O#v&*RO{2}|5Rygcr7gDM95xbW%jE~u`%*S*+Vf#`kyNew`
z`Gan@fnG|zYz{pxp0bm&A!6%euXDr%_p^7{!}c?F5|yR~*m+Da2ifyztMZ(^el7+&
z%&vL?k|XS6zd~}9UAh*MW9+U^z#C_)zrZizz!|0$q9ezhb|nWnG1Nrm#Ob&T;LOp|
z@9M(YM~fX-&h9?w9kOwL=0Mb)v+R8^4|B|m;Nl2p%FmEF%4rOTj0fk72^g9eNBcEK
zahx;tWr%olX6}H(3C_3E!1Lia($^q-IZ3M_;>Wph3lW~;@Gk@N=NwW)A%HWd9K#Oe
z%%uN}6vTPTg<dencAS!3A)FQ}B!zK?7J?eiIlCKJ1ZTq=2rZJ6@du)a;wT=27|mJl
zhrz^fs%SZOnsYw^;0(u)o>FHyomBaW<-9ltB5@q%r<kC4PS}0uC2*WCA>Q+xuQvcB
za_0RCUJ_^2MwP2%4l5rnE^xlT0g%esOpT6doLZ{Hq;opIN8A~l`IA7r$Z@28_e-2}
z|G?p8&Q~E&xWXwTaFw&*I~dF6T%ZVZIP0lhK99p~fqFjYpfj)njwu7~3psr1&Me~m
zuz}Wi*EsuVK~u~r7Xp-W1oZwY<J_VC)pE{mYFoU{`BnzoH#mxyLA=R1LM!+R&L#t*
zsN@X!1Ki>qqa<||=h6~bspd$>5&a!bDm7!&aF%=q_qCiqR)JW@nYt6k>N&Un`@hBw
z9H}RwY2=*w1<YnncqBwyIRE=^1Hnlgg{M}I?|j&9<18zNNINItJB+D=^H&gv4>+n~
zs6XVas)l4I$4uFXN1XZ8WA~WTN6GCj&Zg_Yx;gVc1?b_F-Gzr<&aXQtVeypn%R$KW
zabBcCP(SAzDhUp7_RuS4kn`JhSR3L5#shoK`T8_wZ<w=zQcxqD6||cf<$O$ei!sg_
zD$R{^vZyQDfqRTD%LCk#QcTxD?zhx~;>6uQ5x|-2MFlz+ZU?ns+FZF)Xcu;f>yQMd
z8+Qw(rw((Q*^oKHy+nQ7N4b*EAmYKDa|6JW>-0NBj&n2PfO&I|P$TIH?!spngb#Nk
z?JIn_x!+(ce%!0CVk{@QG2QUw&z&<5!w%q{dknom?%p?`5M<*XqLgYdH?<l+NeK5J
zYRd`ba%o`^&UK>qK?L{L2>_AY2zs+dagR}ECYrloDfDBwjoI*YnyaK$_Ze<t4J6NU
z2i^cNmK!)5;2gK<3ydY6%T9+v0ylO7u=CtEtdLCP+B#^hm&6UEKJa9&gxc3rxS`Il
zmdefFj44Uuo~9n5bZ!^5W@K<@dqXml8%0m)OWZiha9rj#(sTI=_t)7N?^W)bl=;f$
z22p7{ha0#JHgmadpI}IN+|{&q&F6Z>fmq0$Z+i_gMch~og1W|arS{TduIs0eDdA2Q
z!gd*Vgz|9Z+$?+Wu5&x7BjqMHkzVr^+;%PIqLMq6lAyP^59o<n#cliopql$z4@}?Y
z2GPE_hP&GXpqA@R9g20_Ig_AJ&z*UfdJ-GBpV2m<k(;Cfvx#e=4Ok0zDShMXE;rg0
zBCXu-GGMKZdyjI)_qc}}5z~F{^v@CD1MWjQ3-*xPrv&KaF1QQ5N8FK5Ao-YELO0G6
zZp7D+?BZ(rV62-PNsGcBF8dow7(V3|Q8KfSE4zje`?-;4AoGlSjXp^@zzxiYnIZ1l
zF<{TRWfp*8?(JR>N4ZauVP=dgq6=}H`wM-?)PXnYFZ?hEcpDO6#gXUR59}asCsiGs
zd9z9(>B75k9GEMw=2hy6I>ZZ1MBHw?!D3i*=LL9T5)SiNRfzj2FG34Z51#%kc%Hm}
z=<R=u_X9n%y?7=n!5rtEnFqf<ykkzle0kg-F;G9=*lu7ad0k_0c#5}^0|kHHzZXCZ
z;HfCn5XgJ=DtNXap7SZ_hww&^B8pJng!h4k@d8&tCY(2wp34zDX(=W@iYLfNXwkf}
zpAkh2ZyD7-&+uB_#t6^yW>IH-Ebo*D!am27QNA&bcjpsG#`6}4pq{|9lfY&oul8?P
zN#cD^_fN8or&$7-6rPc8)eF4&GZA7cFJcRbX}krgxGpkyzt4nzChwbc=x6b!H^J{k
zo{C=kmv}8a5HIr<oPxD%p0fZ}a(I!|P|xKFX%Ude`-bkOd|pW&Kmo63D&j5V9j8Tm
z5zqF<X=q&I&G`)a#k}TU0ZMpo^l`mX-n1Nysf;J4UWsy^ln#?z=Z(_G6K?Q!Qcd6{
zZ$T5HsNl7m04jM0zlOpsUdm~JD&CfBuyTjDk9LSPyy@9+U(3t?1Cn(-6Lrki^LVyM
zxNqRyqkTyu4}Ar=0eD~0yQ-NNL#eM8-a-z*U7nt5kgdGuBKU3Nb@;&cJ>CK;n%w8L
zQp0aM&qfDwI(T`%V@e+IW?qHfL*B=<b?@ZGuZH>~-n<1McJV%-=GbnYGL+tbJ-i00
zkoWS~jqv-F_ki;DeZ0<(;i8}C@G*=&<0bwDqXWE;XvI0myLS-!L%a!8TYk<PC_og$
zJRWtCjPP<U0gUpjW=M|lr2B!5^J4#i6$k##m9Tk${~>jRIr0YwsVDy+e?NW4!i7IG
z0)AcjBOf5(L;N*z=)3XlykXm&|5OQZnD0c(^&|Xa<nSnedNqItfAey<@Z^6*SLZRl
z!$ep)&QF^JqBs9FD)pY==MO^9hoAZb9QpE(-$WFC{JCgjw@o?8UqlJRQ+#(??fCPf
z4naSFKO-12f&9Can+fK-oI=1M{EjDZ5z0@X6<ip92kpDU`DSWjiQq4<1Tm8TaujAJ
zir@Y{B%}Fnz613b{wvMko#wl30yxWGN?$FA<u^Y9W;@5<S&i7@_$~Gjjpr|W2_S+0
zCME99^PA{bOXMG>f>{#(t;ZlH^F8R4PYVAty1df(@wB*1=l`$-A{qRxn-EMU-$te0
zEdJYcL0sgc(F3;%fA((};AQ@YRBF1y@20HYRU3bj1d7@GX%jJ+T)t>8;?Cm-7(vYE
zAEfeI0e|%|@Cx}GI-ya-_gMmPjsN~$478ZP=@TfF@V8KZPAPwoy4%Y5f+JAB&VO$d
z(cj?z{5yy@`8O!LP{H4R6MB{WRv|*W#kXzW2^UrTcQc_;&A&+RgWLR>O)z?gFWd;3
z8a|sgG<E!u8vynEeGehoz|W#9u#q283ap9$)<J+~{uf;6weUlAki5%x_!E9x`9T99
zw()0|L*X8OBjr~+_ziT9;{l&%n*!!T{!e27o&4uiJ%7Xxc?aMz|JyzU{Dl7%{d1Kr
z{uq^hy7`Heit6FNPE~+j{&uQE_3>9PfJi?-uLAKt<1bUe#Q=XAt)&O~i;g0gA^v(L
zz;nLF1Az|n<L1KH2>;b&8~l#)2Wr6_<Nxmm00+TVYNt9N7@;Myqu|d)FnUnnLx~<I
z!B7)0XF*{wfQx{68=hPR33RaFkl;_6CpSU$7qIOvu%|Ck9}!g2cKN7a;x#z(5I9`~
z(NnM}0Sd<ipKqd`U@yT(^q4*_*ysdn-hv<h+gJ!@(976IFq>*zzJi$_!^|mx)fbq*
zVCSnCT7ZB{HQqqM)T01Ff}2!C2p0IvMc5&NCVGj73WCqWQ<$LZ6DWiWc2HF*LSPw#
zWRyUMO_FU&v>;*?L}LUAR0%yTcuI-)GlGp&eK;$awhJIu;LwL)&I!Jr2oNXm-v~4D
zg86fymmu)*fJmZXIqi9p1cu4*lq_huf}be`Qv&RQ;5%vtNfr3gp~N)7pRdAwy5JQ#
zMs3Rwd=m$wnF7x>kjWBc(`NLN;1<;sE(_Kr!_yUkUpv56K>;m>vjr^&0dfSMl!nh0
z)YrpBp5Uhw0QmyXUC=8KoTZ0Bp<o#wri%q?T78!YE_6VlRPZ(J>&pcH&~~caCXln>
z@Va2?4n%W9u<~!n+!TD205cT=IkhcU3g*%x;Fh4R3zF4>Q5Q_mZ9ya(ygP!I(qOwr
z@G2cDsTGL-g3&s`@jyt{3!+wIMjHfsX*<>^h^1?-NpP2*=goqjQz3F!V6!v=whCUS
z@3OQB^2@-yC)hv-V($xLXxY#%_@xKL4#8eZ5I+zs*Z|3gf<JFVuT!vLGDIE;zNNy`
z6G65eM7jhf7Cdze9D^{39>Fx)#`OxiT>zd6mad0FpWyW?h^b%TW^0G&Gr^^G&>s*S
zI0B79!CK0z4GXeq?=m9bQ@VFl;7R%PF+mPx*~SI8!vP$Gm$ty+0bvwH=qOwn3vf`#
zbb`8*P<;~W&ca!1F{7@+15_zEB)m;4RX3r6?oD^$wEzCw=wacG6^Q1D(1A*}M}-Uj
zgi#OSdL9PqDZCmD-Z9|~`lh*;@Fz;ccnfEgK;(q*$d_>8Bm6KEdcMNjH$e0g-uVgf
zo)msE9oQ*h5IOW0*2P0FK=`BsHUotZHo<0)@UO7{KI|p@h1wZIg%t`+O_*?x0$8~4
zbPBKtVNwlTL<;9nJA0JSn`%YT!c=+&#t6lE7}IIt1IoOg5rzc8=sDqL%7DiSm9))|
z7bZAhpb5e?RKq_nd`>IPL}5|_j3o&rc<R`uBn#(I4lP9(au#MT2(8t?QiVTPK_gu_
zP6dk$;iT&TnL>AZCS(cQ<j}t;bfCBCCE=Sl;P<j{g$%qa!Y@4lt_nw%Ahc{@JH1?T
zgqvv3lP4Ud+CaW=aReeP5SsP@*b0U9R3I!8T9!fPnlL8^`o+T7VCa_!{k8y<3itm8
z(K2D$yBJfs(7y!kZwPU3;Z_mWQVT(a@BmdIDur%z`sS9<Egd$igzjp9YT<J;tlSo^
zJ_OTugb%}j)d*L$A(&d5aDf^c4Z>3+7)7JdkyfKk!lPSZ`>wEs_UWy{ca~xFZ9*%}
z<s+fvDL8yA{E2o~PlUTK!*7>x7v;>mg;&1>=n<Nn0D6Vb65-;hFrV7%`h=VG7+}B9
z=8Qo+6ISm7HXyWZco#B*!tZHlL&7fF*gqFq=yOoR!d_1hM}))lNE;O{q&nl6FploO
zap8<5AUcRv?u5bt(eHmk(owXFzCU<SWc>$3C()$0FkWZT9TSG+BHAX#SX@QR{)WFp
zq8tZUaTEF5=puI)g;6=}u*mCu4Eu;^cn(C5idOo=jE86owJvyywDf>GCTgJn-QXpf
ze+I<kqDnf`>@5md1KtVIYHBC+5e2;qp0DWk8ce>QC^8vVPKsVPfp|(Zzya_V>FHMv
z5VcORK`~JDMJmh$iB$9u3l_yxV)P-Rt@LUS75&o>(J&E%e)MqB_68V@5WVp+j7Ew+
zV?!ZI)ENf#XwgrbAsHiDJpz%_BGY_K$r;i7j{we!aCRK;5mER7h@2B8oWyYBM5mf*
z{TVOX=76{pL{dA5o)=xDOCV8{PVF{Hq9zeUlSL6fz(tB^V>n{EAlgeMhE!4Eb@0+e
zduZ*FE_#PLV=_dmXq}%a`r{WUWQpGR6U57+zxfFCifA(JWv`0DC%{p*C<2WLwkbKH
zFH#_rD;lLnraaLi>f^{4u?t|kK=jq;5G@o1J_1%G`e_iJu89`Wv$t5(My-1#qC~pb
zN=4xdp<X63+=btA(fplIxGrj<#q14H4($|giq?igy+Tw>ZN!x#_tP+KyCwRTYB5zJ
z?+u8eS~NBV`nN?ZIzhZ6Dop^fMs!{SjareGS_bPx@l-Lc7yb1dej7wPzJ<|7Q5v;W
zH;MXqh@x3k(g-UpqPTl-aaZ*79$>8^A4<rziDX$&xF;H?%j3RH)T#orU6gnRXou+V
z7MOV;@?8YtL(%m@475`e`UnmmiPlp0%45+f`pVH0(Q9-!c8Pvt1M3zI=Rl-KByWaZ
zuZTMW?5XI7HBjgitu28_zi3)B{5}&2|3-uZBJX;L42o<al&lyMRniEbi*ky<92Wij
z3Whx*N=%2$sHp!8q8Jk;(Ozp@6!8{}I*8}RK;eKm^dv+a#lut>Jt)4#2G2>{`5tUK
zi%TeV;3EDXwKKVje|JV`hr~<Y0p=!dItR>Mtmb?T^su;-vUNwq$A;nlsF-~Mk>bDX
z(t5#5>@gXl$HnLAz>2rHy8@n0h%Ik<>xbU4ss3vU5x+pw?JvGc%?bhHmuWc{C^j<j
z`vi%v(;XfxZlSi#5OEQ8;)IH?(8?`Ld~`9!87|)60bYc7I&~;Via(*OMwB>*a)r_2
zCqDtih~Ih*#!icO%tA<K#M`$)@~n84Z4LsB6@O+1^PD)G+DGEVFHvbRUObQkEJ6JC
zH_$&XmX1R*QT)-Xu$?5%q>VwcICCek6!C4!1Y8i;(<UcX`~jWoOB4H1OzGl1l&{SY
z?+t-SrkL>>cv<4`b?|Ue%$;ikyd;h=L*}x03VqD<ir7pKxE%4sXlUe$y#_EBdE#_6
zW+q?kK@FY-;!WFNyHLE99?wPMS<X<uCQizQda>Aviee?=$@IafQt>lKfHLvl5s)kw
zM^p9vx;SSQh&RNOrqkQ|rr7UY=-(1^H2_s&&ATvDE&fJ`NN<Z@q=ue5;#^9^*N8JI
z$xti4L)()&@z3QjQ!jo&1zv;r1FGIPif7Skut_`te^Z*pWoseQB6bM?c2|tIHf|%a
zl+HM|iDw|)WSeqN{5oCF_r?1M0ouiT)&q2iS2FO6JP>QB{qdo=<yH9Y6z5W9@{!oZ
z9{P{P{!<a?6Y<#B@Y^N!qbgIkI9>|99&uqBc)jALc1S)Imr>fNPy7NE%=^V3(aQRn
z*ps?XYy;vwOawJ3?vMf<5*LYK=DE1!34Y&U{9FJd;+MQ(bX2@34+9+&3)etoT)fT~
zp*cw8|HAeGN%~_*I!b~TW7ZBz?mU8mljQRkz;l*tqN~J3a$zobt`g})=pB;8Zh=2H
zo1~s9Ebfxcdl1E8$v^beJ0jUw3jL#!5FZT9LsCO4Ay3I3YG67hQBwP{m*nDA@QzEu
zqaf)m$<f2w2}$fr2+c<l^$~c!lD)@4^pn`ryX~Z8A6Ypi3A+PF{u1*JNCrr3QYx7R
zN*KQ&iXh2{PazX5$)zJYA(D0P!&9gv=mtQTB#2fG;gTnIh%iF(_($kROJ28v7$cc+
z8J<o{W_m&LjKmxRn`b4P_#nnggkuQioaCQ$c!-nqQgd#+WD)fZCrF}fxuBkxl&%Jv
zD2bt?_eql4RWOq*8KjRDrAVgwz{~|n!wq1m5*0mV(<I-~jxAmCA?<84B=*ywkSPiM
z9#*m>-%wHSqC_|XPnRVA@gQE7{PYGSuSi0qz^+Q1DSw$Q5xCQFhaAax06?x}?>^Yh
zlZeA$EnlLcJEuUhZ$GA_P}1~0ctw)tF<{pu`VDYVEO|B$)=DHh>VcI?xR-&INizFk
zyIj&p^L$-0KO4qwNStZ)dsE^`dBh6I*P$3orR3xhYPY^6`FSZkRY}5V*?dQ`xfJ>}
zlKeP;TFC|vDAq}ew}DqL`Inm48YHh}BA7<W-vtn9lH}5>wOJyg_VO0VnjA!NSCSeI
z7p;=`AE4JJ8K5(__avNX#B^UGvIDVQGE@En?!OMn;TI6p1IfwNF#1sPa0;+a$+>J;
zdnDmg?)$OC7!BeR$#!~=bV)v@10CIx9kf{Lk<6#pcCVy^Rt--jvDAjxCpk~ak$%ZJ
zs@6V}NMDEh0m(SE9t}#y8!?ANlF<+-*q%$?{SeGyNeh(<MkME{A~Y(=sD$E}<PZ9`
z@VI0nH8VR%W2gcCfb>f$FF8u5Q&Ih(wCNsrPSS_#Va-|UHXRBs($A?R=_>tk2^0=V
zH}l}vO&WO+BJR??FJpoZOH(L0c*G`s<6~GmDjlG{1P|$ZCMbGJ*S3OqOnSB*QFuvP
z1rR+hO{5*4w=|wEh!fI(X)E9(U1kFCmF}d&#eUL-RKYqa?feZ^PDx*U1w-<euBXRc
zfHa>HHG$I2cVHz*`uH*Y1xsxn)Z7&!T|z~aP^r&(gcv5B)B`MB>Q2Sx2&pLmSfsS~
zUuZ;0-8aI0wDd2k1H?!J{4kia(pXBG#Y*2;5A2+DZ9AfmlkT_)V!YI5g!=?()Cz#}
z(pRYmCs7(q_j{7G+$IG~mVR><iYd}6s_$Nq-g_A!Rhs04(9)zUD6Nn#joXeWGNksu
z!FHx}tpm(tNu%i!xG0_F1ocbO_&m6{EKQCCxFYqT4DD6v^EP<MmbMoF<VaU&p`I(X
zTLcez(z-1+7|oYf+y=8i>Po$<g;EPWy^5rZMUc5Bm1RJqSh~@QU`nJRi{P+S8r%rm
zWzvgP0Oisu`fUAmso4uL-H^&Ygt42_R62)WA?>95zET=>4vua~JteSNCH;FdM5?9c
z*C=~*TPmi@<c_ra2}En8eY6OumzJtPY>?Jat4E`>9^EWcnxyZaL1@j=$yBgtkq!<c
zw7b&D&+&`2O54g2VViUnZ3ym3#ZoxDFD<8KRlAh;4)i*tTTdX+2h#oqU=O9U8tJpt
zol;X996pkkdqVNCbOo(ApGdz=g^MofY92JYrBWsW?vd`E1kfuT6kxiaN>6+W_kGe>
z>cj1qeoEiicqV<DUhM<YkJI3HP`a!c*pT!)AMl<_KimQ0u$0jY;)rxw4I;FSN^hkA
z9h3e=qZpT3=)<xOvfq0F4#);5k>Dt+qLu1F8EYBhc9QL<9HX;rJ*8n>WNx&DaFrdP
z_sAico;sA>WPeeQuDfg}eN*_btoaxeJY?Ba+4Ph}>_QaBWN#)z-ODEX`aY<~WjyLf
z^p<5OfO<mK--9XfkxiZpMPJzr4Z`=6)j7cSNtx+m@J`9D)WU_o>~$JwfUJT(Kocmt
zM7!o7S?3lggvx48!)BPQl6FPmGJmQ<M9AcGF{DVDGi4>BWVRFZF{)_U?}re6jLb}3
z!KY<EpMkYAvV7XMo|P@4Qv|WH3@X~5ll?{@PSzd(UcAhkJ}r_UQ*VQ{^RmSX*iMxF
zGY3&5$<|WwCRtWK2_h-7&*+-FAbZ;p!KBKfV==Nc*?!xLpr*^tQ&l`ecA9!uGi4!d
zP|T8jOb6F4%2rWU<C1KK04^@e<h2mFB6~<30#{}GcR?guW~J*YM>Zh}dbzT@RI1C9
zZF&*JeA%H%@Khk%O*yDS8Fv7|6v?9K?9w&a+I^H!E0(R2K%+#q^hJ!mRJNK<5tPaP
zybWHt%<?t@zAoD|1!KA?n@1n!s*qJr0jQMCR)cp-wqhNEsgliF2#3|O8Y?7k%RY95
zr#rI$(LiftOv=gB%36=ZL!Hc?ievRM;Z<t4ZjklSr^gy)^Qq$AB>Ug%_|=+a1s3SH
z%8q{o{WjST$uN3PR=Wtq`?3gk=(o$1RLJU(#ZoKm16e3NL>|hP&}G>vyKoYrJ(4YD
zVAzjkyp<4nA`24%>ymwR3?kjKm(kL^Zc2|V@gB_d%G&8dd@75W0W*EF$s!Q@We+}r
z;xkzf<>dxs#gyC_lvU7ocZOsyeG1-l+254M7?vs4AhZ#gs~5niEUg@##$;K3D_@-W
zuI+2eRv(l*Ou<;3<X34W<ShSpA=F*uEt%lC$|ER4b4dQ>L#VsSbxy$C<v+d;$-{Er
zuVCzme1vMuN9CVT)18O>H9BA9DGzOd$T9g0%HMm*zkd(B<MKTT7>c+2#TbASa*Hh&
z&`0h<i+^9a=qg6$Cr{W3{gd+Wzv2Fre9=o7nZNw>Qt$%gk3I$nln>BbAxQp+4qye#
zU#5F9MBYG&!%+EE%7=%^9Vu5AF8`wrk`eMgDpW+u7x%(nl>ELw6r$xlCL3Uke9Rwa
zPRq+SK;w-36umyr%0HGM{8)Jo?ZnT?SBAo9ocz`ZMiDQUWC2T%&o~WmUT#Q*?L_&O
zY<NnN+b2OiSw2A3&J?+lZtV;5_!oht%0HoQ(=<6d7a(2k_>kI=GvrerKqFKBbt^n&
z$p@5(;-Z|f2JSD(Km8V>m*pP^K>vz-5oPnQ%9pu8GFu)_(dWotpsO-pZt+1d1#+el
z#6o!uC1Z-@2aQm;CVx2yykhz88t_WwKe&QdD)+3PfQNjUJR<_ka(Tfuc)Bicrkmr2
z+?#f6H|1qV;Hg4>p1zk=DR=UR;w^b&GeDKRI}Zxg@{|#{zb)T<0Sb5I-p>$rjr`hI
znCDu#ZW6{)CqKx7dcAxH?Z6x4WoyA}l#6MdY-^IgaSe*ia(}Afw8(#d14i%4SAPT0
zDwoshs!e`!01@7ke;bVnzAsPw7!KRzv*}9ckguBr-UE5pDS(IaYRWux%H1e0_DIhE
z?-r9^pifLak-y)KD7xgcDB0C5XHj=<k4^q#EMTwPnO-MP<qy&kOrQL_mtd`5Zr%#)
znLLzwmImbBv<(}S^Qh%xNY0*s(4NaV&tPp>9!!bw5qXCfVj7kA)BQdsU%nVN$K|gp
zpy!~dpAMS`6xp=jbX2VFK}-h~w(fLLofH{PK%Es|(4N#qv2;2xS4H<faB)cSE4|>|
z6tB~#vD_6dl^`BgtfZC55yh4{P(P}0rhSEnLedHmPen7eSRPYs-3Gs2ip&2Z`s0eg
z_W-;VX_FD}3B}&`!1Gmj*y!%?Q%rjkai3I3sor=>v5yVg{)+f300D~YD?kiXtPg<g
zAVmP3s0~(}qE~u|Vl{Qogevx(0~V(EbqPSYLP`0<2t^BZY(*+!Snv>~c=j41j8^PB
z0KYMcR$8c@R(R=YlXFIKLxW+TRa{>RW~`!&@)740KjuRwPSHliwRlC%5JVCbBlBS9
zykcSqLQ7Qar>9SnVsQs}$qGja{H7>!_ru`@McFoBsfu;9i%U}!(#ASnv6~vhGZcOc
zpqHr-{rBzHEJYuEd*z~{hg@7z+@l@WWkn06Yp*DDKESRj1T@fW#TM$7%28xD0pu#C
zP?a}NF`pLp`HE?j+9^=vQpUYd(L|5lB8B__M2ZzZ48TK)BHk6mQbi^er^^(ZYv>q2
zxk5#|o9l|IEI7QONb1DzbW`#36<`$#(f@!|DuU^UxuwYc2&1o3Oix6h)rwVg>D^X5
zq_^)K#kncq)hJ#nf<mq0I_;0^6uSK&)++?T2(3X;VS!$w;?E_Rye7q`afrg!tazKA
zdM%1%I%RxUahno(t%?rXwzes1si1pL@ds^B?khG@;jLYfFae|JP`ua(YY!CnF2lt`
zMLjh+bt+a-S?Q5t(=C9<3L|B=pD3K@ckNOrx$w}f81cl&dK4jFz)G)8ahk66rwZ?4
z1l6ZVTMLbT#hpB8JX36lgWmzgL^`BAs95z8cteU{D(OF0d`s)}VMXjd5Jwa-n-RsR
zViv8n#uRSXATqA_gA$ew$~O9x*8!zsCxDYO;J<chWpN<<xhQQLe+P6`PN&k-A*KIv
z05@ekZ5Z8^UtB=Ihm}=yh~kK{huRd5Du<{c*F*U>b**|TeP~C0OgTcUeJ|zOlMp$s
z?5Fpax3YrPZzq(avk<6{vX<UvzRCt)i1;aw(BbiuN}Y`kS)Nj^z6}|FWz7YE0OjlD
zh$2v#LF?Th<$=v01}j(6VkboTVIO#*%J**qgee<nO&YHB`xn+Clz*<oTtq6zDZv`0
zw5LQ*v~oK&Fvchsehl@~N_(n%pHcd%0nRFyE?*89tL&tMpYck?GMGtFzP1t?=apwa
z1Tj%5BBM#lfBn|anE0k`2X&mJDqT|n(v-i`b(OAM9E~V4l=bwu%T)fp3v-dB9H8>S
zMJ0!(@{+PS0j4i2_rCzWD@v;ehICa~z6iu@WhC8qIZ6j=`OQ^cN`_vZa&-#kDPQS*
z9@AW)lrDgWLgkk>31o_tuQ~(0rj%`jVzDx^4jLuO^>kC0D*yfxB4x_)g>X@>)Y1O<
zx^nJ+sd}aNKJacTdub_Mp_~?t=qr_x2_W85meWJ8N~x!Vlhw*MKLzi$vi$(m?<jfn
zHmXr7N@-16tNes&U3E%F%HY*2SKo(BgVMYRv(~8e^@Fu0WrjO6nw4o(tZh+F%!bHa
z<quzi*s6Ru1Mb_D8Xa8RQ*I3cuR|G~1<41>)HRr{hsw!mu+pi#O?kXW%BQ;k9xKZ?
zO!Vt{ZQ>%^a3wUKD*Kkhf1fft2i$(;XfI~!nQ|>9Y6p}t)OR+hT(Tclhm<GgK;*g7
zaR^{o*+`4%5v8*?tc)uACxbYqTp0|<<H}<~s5_{>rH=$0P)(*w*HN{X=J}vX_!_3h
zNj23*wGC&Lj;7s3b*vhgt16}*W)7)dp(Tl%>L+yHO>tMT=7V@x72yx;i0YXH<36gY
ztpVnt+DofoPt`}XS~{s(83ezlRO_Yz_^Z}XmODVTiFSj5s+8>rEl3qkb(Ub&bvt@z
zgs7%i!3<Riw*d=NU8CY_xJq*p?juxkss=`?1|L8pO4UbewrJIDIvo(B+Lee=oL21}
z2k(q(5$%A^s;1N-m{?WsL4b3rle<8SQ~6T%HD2ZV79vbg3DyIgSIPF%r=}8BOa1_w
zq;jX$sbrOk)(a`BFLnXDpem+LwNzEz3W%hs!khroRr^yRlA(IW!eBC0Jsxn8rCK-x
z;G*g|y<#t^?5K0{vg#D&+^(oL(OTlFYQ{7SFk5w>mRETyoq!T!`Kt5~PzzM6X~A5m
zD%}mEMXK3UsJy0nky<E<RT)N@DN+5j6}(c_c3MuBtG06?a$WU|Qad+P8Y%(ZRNW{B
zs8D^B1s9d7ZM2uYrMfYWu~eztshD4_l2PZ?ZIxMwvDogY(w0J_MwLS={92V4)!*w>
zzg)tw>s7mUgV&@gqn?XqRiGK*u1Zh@{Z`c?dMUT5rVT*ko~nXs>-SZ?YY=a{>Xjt8
z?@-lI^7(=4n>8@@P!)wXmMNX8P08RrQb}llk8P^=>cM=XIzADj=u-XF3Zvbs@UIYC
zk1CwbK=!Iu(iQwvWw!uWpX$9RDD<oL6azd{O-ln9P`%xPm<CmLbQ=w+;wgLdTowEP
z3d5@WGT0nZRZt#dRP{1_+h<I5MGAl8D%->kpa;}jX|3p}-gXwE2h{<T$#YTPr*;EZ
z^?Nj>htv{UKD()pQ8vb1ee)Z5I;?(|0pOwLRYJj2{n{Le98-Vv3q-utZ&BI*gnEEl
z0({gh3ShqK<Mb2ysmp31c~UL6eGcj=^;^r}!e3oVmsfy#*LuVqsGd#5fgtt08PE?_
zw^EudM7^KtZ=q@@Z(w2Si*(0?t3MovWQ2Nvc8Zbetz7_7>Q^f<!f5rf81Q1$d+42f
zTAi<fu`_Df9`Mep$4}EkFjjqpHW=sB4ZC42PF+e(G4bk(c>LN4>Xd~D=Dd0<UF(VJ
zt#qd*sb_D;c$3wZ-+-m4Q+|QN3+mh+*iKc~P{lh<J^vO0O;?vRK_o-%^(7QC)oe<#
zXQ`Jq!RAGE%}hEvc18UGr4FyE@6lQ@Tm3gRBIl^hUjyW-zhc97p4u}BSibuHRTwQ$
z&pm@c3)Pj407dG<*C29Dy^dB=#p+LKWl^I3z#gDf9dj3;Or6bxdb!$>PRw0bPp8E6
z4fSVee6~%wscxs@LWTODZLnRb-k%Gjx77RhVZN%=qv24jR&NOhR-<<RAFx`rlDf0%
z)akUMsaLP0ooa*nb9&r0s>7-Ot4Y1J4lbJ2AJ7?t7PWZ-ur~F2YFWIemL0+*+*kkP
z1EQ@<ZCnc5-Rd2b>*!IZOoo1++Q5KJznV!8`)BGs^!?%i^|ZV2G^j2v!YGE+OXdL^
zQE#)t@2EO(4#1c?jD~hV!=;l7j+zS#VCA5O>45ol()f%3IBPC%hA|gS6GeE;rU_pG
zGhUins+1hp4AF(?t$Fhj;y$7IF&_c@Xg=Blp08#yC6W9zpHo8Nq~-&f*;AT)`c9s|
zrkRrE0h;Z!nGMvq(GE9AqoX6p!I}b^%217hu8S~@Ybl}+*Ua^Xu?UTAC$$|!YVscg
zjna72^X9bXp8zPH(bQ&xcUHrs<Z-N~y9<Gy(`3>-#c6K815fdqP30I<g2ulBBIh+;
z8Bj>nEY?9iNwYczykyORw}GW-8a{`}1x+^P3R5*RsNF72(_*`ipwcx)JNV7gM5`fs
zS(8)^?26|2w*Xf)*IxuNTeEpDupG?_%HHN`7W{)r$kS}H#{}nVVm^b>0?m>!NET{#
zQBl1}<9Y&tUegp%(?hYQ@E_=vXhQ#i-%?E~od_<|%y6?ord(tH6>MMEeDVYIZ)lVj
zU^g{K?|@gK@%j_`RT^<DK!fIu?+|aJCT9jl-=vYKVXay7$w3UQMH53^PIooyI)Sxm
zj9b9Fr`gsF$@>~-im+W1&4%d?jg~%N@<8*xn%;j8H378T=+vw`0*%L-6O`nCqPcnu
z0e5M9XocUc$)maK(e$UoeXpjI$`?;HT{mE~PgCK7(E2r7jstt9*+MJq0nPJ0n3*BX
zMY`jjYj!__m0=BsUiTv!KK0p+YUc3iJ6L0y2?t?&T%&gcaM13iW!eF)4<#fVwM(qf
zKd8O+FBF}$Oh*u%wSi9%g^RZI5sbQOC+|b_hqQO;Ds$7m8U{&sZ9df>JhUuoLOrI9
z8-r;t?V;B(z~kCOJHYeSzIF&i+X?Ml$|d_~-=|jTliC{kLeeR%nTiYkTD}Cf1GG&m
z!3)&>oCC!m?e{8xV6Bi6mm%6OTkva#YIlDGE8*HtDDN7f{pTq}BDL>C!dR5nb3N3f
zwOK3SK1Mr#9ATf<@@Q#&#-_E#!pvE%iv!HWYLn?7bez-HPJx*??a!+K6111-NpW8L
z&<j|iw)tC_Nz%G_!f3MgB5i>#XjittXsR}_22rGG7g7g*x;88uA{pA$c<5znTj@AY
zme!U0UDEENGSOwNP1lTRyQ1Ah4Qp4mfuF-nwzi*#*mAVBPT=Kgw<_VHNIUNn%*8eB
zzB2HNwS9D_muTCmdA(Ho>nq@uYd@eY!*%T^)CGD&`$|1{mD(r;)Ng6+sq3doJFN%2
zYVA9;48E<sYAb_cjaGjhervU-0>P})UgE$^qgM6-cum@vZ!wr=ZOKc}XwhDv{M=pb
zKe<q7)t*@bg*GksUr659#)m_)UHjHtIPB22*Mavy>qB{zhuZbDZ12?mlLzof`*ak8
zc&z<l2i<>9v^**^^=OyZz-X`bP1=+`)qZ7ynLcgu_psfsJ#inrXWGe&p+Bfy_6p{5
zNZY1_?dRGbRzPG}yDbY=MzjS#!}hq=uLP0~x-I{0Sas9qg6OEbs6g}wb#0V%cG7J+
zNrhP#o$(!ry6QHC0UXkKKZB^7ZaZZu+;y?>5Iw51qtn$Mx-aN#pr@`uj|h+HdUGJ+
zrK|fE;JEH&7u3CV=~NFpp<^{d#7|e51ma2E0qV~?r8`T%y}xefc@P71+ux-7FG#o8
z4;sO`n}q-&y2?<1FkJy<e8P33)VCd>TYVgpAE`UM3GSnGf%PyGty{GWywkebpMrQs
zH}onTp4GYYK#bLOQcvkQT@fF8ak^zs;4ncqLT|eBx&|uWC+Z&1qSBV6`;dC^l6Cep
zU#U9Z?U?m6o#`8xN!Pu<921<On@J*>x_?$eKT8)%elO~pLlNO6ot!E&mvu*|>*tDY
za~F75b+1oEOxZeq0%FS1T|NOUS2xiYrt@^mGT|s+w_N~Uflb#=CqWB!E0I8*a!uz|
zg1C!yIrNK`=<*qev{d&EZIsJ&9;Gl-uB$u)-gVs^AL!rE{ZEOQZt7m00QVKT59ly^
zr7o88uD5hgeuT{`-2+-bR_orQ#Q$yGg1>>?(cRG@m>S)eMYIvC)$RNYLDlK5Qg3Lz
z?iRIvH0W}u3ARZWOAm}@-K;`*YSDeX0KB`pNmL<e)hS+rr#4+i4cy<;nZ5__zAnm7
zy8z{Y!&FA-)V&i8-XmQ?F9z{gx48<$Cpyi$0A0Eplo#mMReX=Idvz=6+`?0xl3pi$
zx_e)NH=z54c2$GA_pf8{Lprw$0MB)|=yfuz`;H#OBf3@JBfwEz8s#X*bd{8C9@pjB
z=&|9TFZ}_`1N!@G;NDT677dMq`aFulNw0E)sI&gP*Fbd9|4NMwuKK2AxId)--WxnO
zeaKIU-d*22h~XaAyHP{@5xx2=U`O=_bD-y;_wR;jPrX0wk&fxL)Y0Rm|J-PU-{bn(
z^jh%NulWkGozPdDL)<?454wQ)>d!R6nxEcAzw$|a^aWTurT;1pn7{sCY99;G?<|8t
zp#B{Tq6pGIdkMCK^>b;N9-?2+3x!bq>>+>%eLl74Me6TRRxwJipGRNukJfLZginnA
zz=tq%T3<;Ip)>jq=*K>*_nHOwv3hkousHqX2w?I0XGs7F`f<uuC+lPU;WtJ9$`%B3
zLEk{N$W(pz5TZ!aKmG^~)AdDV;AQB)qV0XAexWmrW$A}ADIIxH&!D`~C4Dcw#xCo<
z*CEm?djGu$=BobvaPYGAdvjqlN1tK@maA9MLC!pVEdwB5f1?yG3iRKSLZLqD1*jM4
zb8jKSYx+UD{)_dq`yg4OpTvh`ss3&ztd!~ZS3tp5uHSnev0c}z=*4$KzlXZ)Z|Wrz
zAyc8>w*gqCK8j}Vmi}-p;;zy!rp!aNeytn8ZG9T;`S0khR0pWhC$M0wR&S01R;Sle
zzi7R_|7#4pLGMJDbE6(7NN~gG9|glhvrV5M0JB9OL50e@dgb?!Y1LmE#|6=*w^FL)
zo_-Zo;qU8_bHkfM&!l8~hu$j_*aQ6zYJPpF-$Lo5PW|!^A^AujM~jZf`a^*j(i8pX
z^g8I$x4Z|3-THs}f%WM3Q~>MM+s@N!<*B|c2O53)z6S`nU!Ob|;F-RLzL-3q|DCpv
z&-H7me`Q!dPHTV>{bky*jp{!QhKn&hoBCeH^}!2a)WLAl6T}0C;k&TuXeeBW2oD-Q
zrb4ij;mxzaoDJ^}LEXjBZ`+KxT@A|}A$rJQPsKzx!}2T;-3`_kfE_mY)IsBjVY(K!
zj~c2v0Xz&pY=(lT;oe4=IcB(AjR?IAS19*=-0-*<!FU@k@4_HX7$(GEfIfyvR0{Pq
z-1UW|pMg(#my?DQuTam$DMJFivHT75=0PUNFhW;ZsG&&=Vwk}|tJrYE<P_MBFeKB%
zB+@W*17eCY?C}JMHq@6uFUG+87}#lpr5i5J7*tdwK5H1<1rTd!ks;o5hJ3nx;{XtL
zyy30s)Uljk*g#+RId52a6D|@B2Sy;8WEd1dCfQI)`^FSQwg|)vhBZcrq#FJ=3&b?T
zBiihz8(f7TW*7>Z;WyJT_!Ed(hF54adC`#9jF>JN@}uD4vLSaV^sX2r6(C+U@IRzi
zYqsGso%zf$ObvjUTtihkn0bZ?)PR+5I9LUv1%^<1o);RTKE%ux83dn0<eK646);+C
z`28sYEiu&5X0X(t)<dMsFh2+i<%Sis*ST&Olmgr^Z2B6Z-89JlL1-0*w!fiZt29U`
z4|>Z`umonR47hS}a~bA)!S8KDycmji3|ppyS7VqN0sUITd>#U=GvsXoui2oU0*7}E
zPw0qUtATqMyf(uzx{dA`+G*o;-!OkNJhU5pX#Lk=aM5FA4-9iB0X(!B{525mHaH|9
z;9kRDbmc!als|<=pJ7`D^al)od&0$_VVv^4Lxuyilz48iko#eSn+rrn45humMh(k@
zz#B7kuLBr2d`Zu22V($D$pPaAI)&$G^cn;>Xgp7g1}CGfw*zBxHile66fVZ?wE(V0
z(*YPgWQ?HQx|`93_7(2NRbOCehmC(yCHaVPq8h;*H5O8h!NYi)8df}wcV@u$F{3>n
zL@y(kx{Zz-!{~zWHiowXoG=bmf#_pgPdgu9quEBKBtK)G9Qr4Xxoo&NWsH6R;BQ<<
zLklq8qjF84aXbzVgN%PphJLW|KqEYb7<>Dm7ixUI8pJT;f_(ttMxSjUMi{IA+g=#=
z>48NV>&{_DqmA3H!(WVX<V6rq8{bpgVEc^m5eox7YpneVAl6v?E+Rc=blC+EXDpxt
zr18e-jsOWp9Tzd3H#+!1Khapg1To3DoR)gYMnNImrx+(Ef_K4q?KALFjqh9pFU=^T
zf^NF;D|<wdVLY7;EYleEGxc0#89jy2xNQ7Q35QpVrGJ5W)p$YxVz%)K%}kDQuPa8M
zYut4lB6-FMSr~o3ap^DM6&Sxcj6oC{&&5Kd$k<C|lWWG2aflQfzutf-N{r*HFtSqP
zTTQ^qjBBZTyWF^90i9UAZhUJg^lun90iANw`1W*!SYiBgFMgm(<GvtZw~U>OpiyOf
zy9=P&=$#8Qw~e=J0qz)=(e9?kxY`4}TI2U2uu^B_m%@F$@o_su8jMc#3He6jhA%M}
zO-4=;M4FBMW{B8YjBn6$<F3)2DjluHq6|1}Gb-uT(QaHJL}(qxlEn~tU<{uL-b3SK
zD%^D%t7r%F$mmJs$Hzw5Js5prWUPWnm(e~CbJ1;ljgDFM7|-kk)@uy;7Lremt_xwa
z&$!AJ>ist3r+<O@%y{}SW@y0J6ALqg#!at6bjY}xB7JU*rlj+*aq=gS95Jp*gwau>
z`aYr<GalDMa@^QKHD?D?+9VJUm_nmLbTm0rh2)@VQYcJ2nIdPwn6t_B1Xf&3JuZmC
z)ns#U0rikcmImNvTJkeIxtq39ap16N7A0zrn4Y-6%u!P-wJUg-W_}FJ({!f~4v(2M
zN8riJH1`11kDFqtRmI!1bQrczn0%k%hw(ABh@t0eVvIuaq{;Ojc&AKHJ_qnOW!h+E
z9$@mNt!1ETM+QKUX$HNbgH5lj124ps90!M?raY?1hMA<-K@2yg(k3**RC6B0NYm$q
zn9C?rQ4}0Tn>cF$Voblp!OCgVcN&PCF?G|k^PFiaAAaLZhy36u-c%Jv4SETtKj%Q^
zyy?v;U?!SEa}jBhX(u%~CYvGyAd+HQL;7i^Y%eILn-pP~pbS$doyWdt@~7?NC6j$N
zLc46LcpbbernG6mu9~J&!ZO=rra8<pouDLauBrASczLGbsr3HKH~k`pOo8b|T22<4
zUZlRLBAh3K(Q770I(<=W8Vi8m5|e!=K&k2D2KX&AJ*5SHxoJ@ru<NEEYIV6`;=KaB
zo2G$j02QVpGZZRKODI8m%XGX4Se5B6-IUd)KT!d*O}TAaFNEkFljn9=t1+?YlO?sL
zYcY_iGr4^NP;YXip5X@5!xVr<(-7@anoPa4jcYc&PW^~2rsWENyC$U@rn1!};b7L<
zOwM#R;hw2-Hx%xhrfq?GyQ%sGU>&A^6_{<?1JfEB=tI+t4<OoUx>*hEktuKsu*aql
z`clLb)7z9*=rS>B+uCjVRRPdr`fvjDdrgCO81_?B!y-ubnYt)#+iyBVFOX-ZH|eo4
zV46x_kr*_svxnZ0>2FF0J~s(}z{rMero~@_Ibzx+ftgWLaRRV0lOyF@$4y?;CgEWI
zv;$@inv3XzEly_dSO919UCKPTn3by_>1w_w0(QvU(uOG9%-g9x<8IENUGHJ@0eY|<
zG4H2?QAf@5KEYT#%uk;I^EBJGOJMDoIk_KZyvz-55It_rr-HJ#d3_{|o-l{ag&7}n
zC1osq&3rn4=VyLQ&!Us&tbZYS$~<@!n7{c?dK3njPdb1YXfAjGdO_x6v~mkJZ=-uN
z#5^p6NT@lMDym`T9@~1zgqzDI!f1rKU_0DLnrA118D;+R0gOhQ)95%`jQM3+%A7Wz
zdk%#&X4n1ToilIqg+iP;`$x=dyty+JAi*5%fjK;H_C5}gMDx{mFu)|UXD~b@oA(t1
zOEFt#V-ix$3lGx!FU@@RZ^V{vZs0*N!(2!$t(j)Odgxy?Uw;9_OXi+S(70^=ARq3p
zn9r{U@2Z)FMEsO&^EOI1<(Yq52a$a9#>=o-U{+Isve2yZ23BO&P*>MAa};%A6q{$#
z4O?PXiYT>OYW{U2hE`_&HxT;eX5arI#Ovm7=m~Yh{E+U0o95tgxTr9HbszebW}ll-
zxMhBmD*aXF2_#u<J~11i-8Rps0_7d^i_~9RWA>W}o3-W{42aa3!@0of&F^KxScADw
zO<yc(G+&~I#3pmfFpM^vFK$I_EoN_OGHEq0ng}y(=9GN^?dG?lV7tT2q>iKq=7a)_
z{-OCIZCg9dgFdkG$b5~;j*rbHi-0{bFK&Qdm)Ub76uQl2lzQtibNvu@ule3x7_;@8
z&!$7>nK_(}8Vs1v(TzK34p;*HA@jd9wCCoTd+-|!o9CT^?GbY(HG+(q|DqP_G4tM?
z2z1<hp6*Qt3#$#l(XwX-93HgPQu)uxk~s_!XN%i5IC8Np-VYD1mLYF=IA*h4Pyu>b
zMybW^xP|>IWV|gOCc)te%dH%^_p$g=>+ea+O{&PAvh41JzQ5)7-LM^CIW!1fpyih@
zAsJ+uI0;sQEz78yA7VK`r?o;Y-&2J#%)+5WO}Itg0W89@le%mpEw%|%6N$34c7hsh
zF;Pk8yhZ*T`iYiR6QPl8`LhLsNwJJ>1Mz~z_7n=KmKOst32Byj)8RhdB3c2-49kRB
zFq&!U>A)beESV*cylCP51CdLXNyP}}vPC0+$Q4T<(t1;_TD)vCA)0OZA7x>4EPwr1
zx3H|CO-G)^i;hp^TVA52NP#7GC(IODex*csktLam)YmM23E&l5M2DbWVo8hvuhg>9
z34Y5gxwBxp+;WKOy4Nj%6QFRza+FFbH!Vvk&<e|zG0MMGTBcC@+$~FH5tvmL9%TTl
zEiX_ow=JgG;N7w4XtPse$)@9bwU(MbNY+`tq6BZFW#^Z0*kq}%0<qch^G{G{u{;mP
zbltT)Jc`g-Eh}aMv{`Def_Tpo>WE<OTfW>+XU^I!)7&vN9hQZ(!G2)*l^!$?EuZrN
zIxSNlgZRjzrw+=;mY1n#@rk7<4i394uTpzsx8)})V)j@h?;^BbOZ0sFFi$O?xq{ed
zdGjvR`z`;*K<}C5HQMYCSeEVuZ_qMtDV;eRvb4Vejpvq0w=mve%h;>X7_nrz!TqRZ
z&Q$QmESG;mz~h!Jw2XDIdQrdK0qaz1?{&0p{}&<$ttnJ&a<cBALWi@pj@n9GtZyq3
zp{rFD2%@{S{U!!+*m|iIQ5>;O*#JG;QR_R@neJiz+8v^vR^D#N9JBrv1&3bNTFRmx
zx4KV)hPU<hMrfR{CVmd0k9D*YdcIa)a_?u2oB$UmtsAMM;gq%XYmCL;`t?Qd0<87#
z0|Z)A=(i8Dww!``ur+!aBtvZ0Z_a=kYGwadtG2G(k0`>ecb3CigtZ|VijmfNkD(D|
zJ>7^gMO$ZQz;BFo9aT6^TSw>&)){LhWr)sN*}p&}*1F+y5YJhi>wv{s9Zo|s-rDds
zeuD(-r5Kn#Z~d|W?h~yxtdQ_}unyDDm2BNkD})rQM;5>Z>n+NNrCKX!e~@N<Z8<=?
zwXGe*46Brgnbr;T5%w&rmAVHmT1S3EXqT+XG?vTOU35zNiuE5#bzZght;UpOTYbz>
z$g#dT7w&VdDK=XE=2@51%Q4^j1)Y8>uzvC#%oJK%-^7@TtnSq2aLqav3CUvX{&TQa
zVztsa`%>!)I$%|1^`ph~4XYbv;wr7n_rt|4>oiIlS6TN^?Wfx6!iK}!*7H%YdB?hg
zs=PJUXFpMCqt;sc2xy)4=$~*=Z;hjEbAwgYi%D#>26scG$r?!ylV)ouwHvfp6RFMU
zu633tBwMYmUqZ6YI+L;l_pHr7z}S83-!!r9)<q8?*<t1U0rwBAK^vj)&>9{G&}ns?
z@&fL^M^=YZ2=TF1a1LgkSl_yYD7vgh7dY&;PUb<s$NJ5i5b3q*=+Mbi>s5N}^jR0)
zfv0}!sv=;|tlOf24OrLRgY7}9kTTLkR{nhOo?F+xfMABLb(F>&u_n!gl~HR!GJWEF
z%v#$7jdAOI+M+txH}ymDfW74*X3x?7Z^~~w+Xv1>XfF1DECFz}ccFu9hwMvlgXd<S
z9tGfTUn>UjsJ)~gA|Ce1lzH^D-`fY?ar<j@$$Q(MdkfeJ`<(AEqdxYH@sPCn+V39+
z)6c$|jz|03=l_D(0_^v{2xg%Dh87qNvd{b;ykPq=D?o_-?ss52)c$?iUxeAursZU~
zJ(C{j5%$~Y-i)-LM~Q?e`(+G>MB9HveatcTt@*%C+fS#A{~7z~21uT@*-tTG*s=Cm
z)i8R_{=3B(eVqO9W9Y}*^XMK+uwPvO+vn}W+khq7`_F^5|8sPmVO1SX*b>qcOVs#j
ziqV+Fmc*D?Vl>f2jp_0B-h00{(ZrN1ps0Wfh=3qP5COqTk=|55r3i{3MUX0r6hT3X
zeDCDfJUct{&g{A8?Ae`}J@*{rIu(8;GL)yFm&DM}NA8jtgYV#HPGQ{7gr)P0HS`uu
zWz<oCDvj}!1Cew_2CdvO81WP{&ty37&_Xbak(q*lW;1@725t^xO(!&R84Kx~cX^DK
zaFBe))$c$qFuZ6oxyYDFQ`#lQ<s)DgFk(vKS|MXg512)af8NE=E;AbFb#jIA^|v5b
z8Q1;`0Wj1QSt?<CL8VKj45yQxhcd=K3jJMUOl|`yXB=#YGZl=u81!9dr2Y;QHyArB
zpjgT9$-vNVGUAVcS;e^i03y|lH)_y#i!pZvE@chlS_{-`84qs4nL0)xJ@@sD>$~7~
zBcqX4g?AVyo`;7`jQ5t)^ViHcMv>_jMt~pgxmJdN4nwsuo_P`1qMeaQKgC_f1j6oM
zBvu0E9^-Y2wBBc|HAA73@%}qNd%&1y16UVhZUVr%8Q~P)?qNKkVzyq!=#OybA>&FO
zNFQSnmFx5~en_YM!z0Gl?T~rQ`0!OI4lv^IT5=g={7j4RCyWJtAVZ8dDDXMVxX=s5
z5k?giV2v`~rmfmj#;JYi8)F30+Ght7lQf<mW&s_babx~Kc{F$CbShij$>h^(VHfk;
zZg}CrbQ4S%_m0bM=3pDp_Ap22PTI@-WHB^6nOEuCEM83cyMg5^$IqIPO1W+y=Gaa6
z=F5EUC|Z8ZYk}iep+q%)6yO2O*@fr}Wd2Q+wL#3^R4{dz=|OveVCK__=nG-yxWLmR
z%sKSR3S~a|0Ie|Qg?ng)GjrC#iwNeknP47eo~PoWNak1JK#5{@QBv<X(?+3-7^cAm
zlCexJ{gm;{XPopLCop+*Q1K+woo2W*%r*4hKFjo>h`>2!D8+pfnNO*#If?l;%~#3H
z+%gO_m3g-Z!%kzarVw5_(=iDKGnlJrfuG6zbu~to#pKZHE}Qwxa~Mkwv+loIT4s<7
z!19=@f1)i+K6CSCIDCOQeF!iYnU8mZTw+$zF1CQ#*Mz=8W{(eAMa(zc(07^H(Fwa(
zm=TwtewCT82PtMw{~3KH%v7q=EoJ)4;6)kpr|)3*8gpw8Mqkd1pvYqdbMqt&@H&%Y
zq$Si1X2uP4Rx&@OaM?}fPZYnYVy^xT`qj+jCt%)UGCzk#4Rd}C`f8a@a<q>5T`u(M
znc0*xzRmRc4WxnjC*3rS%q7w2Yi16|!21^Fuk_+;WgdSQm~G6CA3@rgbC0@U3ct%-
zM|+<R=2ITH_n4QAAorP9DCO75OrbgH0dv-FkS=EKIAC`(lfHvO4|7%tT<c}lhrsSb
z<{S$w^)dh00Lgx4I^{MVG40g%m>Enn>Hu>w#kmHVJtC+-VO9n~(mBLTJc-U>=6NG7
z=?F7v05GG>*M9}}Q>KGzu3TBKP-54OwTkLa-C2vNP|kzJya#7?vr5+kbPwzMC@Ab@
zMJ@%lC(DD9@?Na{BQWpH@}X7BKGxe*mbIVt)+CSvtj<9&eb%$)Q(DiL#h(tleylF4
z89B)M)Cr&bS@BC?=@6^28lnNLialTkvR<Xq^dMH!SuhW?B%;7yzZn0Tv(FDO;jDRk
z0Up6RI}L6eWj&$LWh5(X3WgTNS}lN6$5>nF7;ZGHixMu!S#|R<rWn>ts#c6;y^;@<
zIM(`)z&ycPu^8&{tboHH39JfQRi0!`Sq70)tX>NFpJt)#22Tv@FXz{A>MU!)He8Hz
zEFUU8Nn}OSVmyhp$rUomtd`SIOkv@C7+x=|*|e=oWsQ#oGmUlA3iWi>H2T#tSl{ZP
zm&v;L9PDPX-VcLFHY=q8{^qc@(>gzwwT+_3d8{uFftk<xet)2R4K6|@ZQTl3>hFPF
z$YLOd;Znp3qP+HH)`1qFU18n&6@4WvH3em_v6fu`OgT%k3O-e^8fXf?&a&vCcY`(W
z2VhsS7TdtQ$y%@%3RSF>x4^7s_4mNhTdafMps$YgC9Of~Stp!SA#|Iyg>s_}tR3%w
z+sIl*A&5JyFU~@=iS-TxBF(Hp8JI1s+9CWDt*phg8NSPsEk~<^wSd-T_gL~Dq40ne
zy$qy_6&nci-7NC~jO8J#n!@XSEYCMV`dO7<L1cjSaT<LCWRMj-88A;+vmV365!Of%
zI!9U4W`aCry=H?YSN41{VBFaDeQ?H|J^3yqJ=ir>_ziZmPw&D7+QWAGpykE3P!YN}
z+m+7j>|@(rg+U*7ES0MGvWsTHo*(<eQS=>RpL(0tg8}T%X9GKsy^dzoVD@4gIz!mK
zJwQ9cZlwfMI6E{K%m}uaZkD6$QTk@dG4=`$TG8y^DFuC;{V@eV<Jf{4v`(-G6(I5K
zB_CiAr`Y`QxE80`CG;7IGwe5MkC@0l_$TehlGtz3Y@N(*S^$kycIZp!Ok;DGfuysS
zQQb`zJCn|vWV1h^oJ<b8E(*@%v)@iZ>jL}pCGhYfdn>Kk3fXdsj~B6Tg~OT4>|6gG
zSzv#*5Ga-Gt(331$=*yec@_HyI<nxbW-s3h#anF45y;fBIV{+%XJ=Bt>Nb0ZFEkq1
zew6BHWPeJh?C!8tw?UfNXDO`G%<i<pQVV-q7SvnWtK49|jeXh^t#)?q7f|nDGs@Ar
z$DV74<bC#>4Y1qEj--Im11Edx0SvpFEt!E)^swEiBBPhxaS7ND*=uO$*vIa+gW1pS
zd>4uX?EQ2SXOMk)5TH-kMIKNeVXvg`C62Q7N*H{~J~S7D*ue>}hMp_uw~yeH8|Q7B
zS=>3R=|<eiQBfMugX8>#-jTaG1qCp;hZ8{~+{-B^G*8a94N&yrWKcB8oAWdX4)5d4
zdLR1xIeVy*@c`%V01zL}#^vzBms3f{0sT0sU&7Ks&Ke=~{5hy$#m&Z<(gxQ8ICbY?
zH;`l0fdp~ha?<T}n6qIvI)gb;yC53MIYc*27$>V1=EFJbD4h|>+5Q+NqBuFPL-80V
zeIXo;;kbVXOR=0Ek3c<+^AmkCGl7%)7=0%>H$KG3PH~p62Fh8^>)*lcbDXKP{!HX7
zrz}|tXU82U6wh<IHUTD;^A62E8JwszbY^lCQP9ZZ?7R+<TuuU&BIR)w(}yhcIbN<9
z+9i&G;&TO@F?#L`IsN63EaLoI2`?^lZoUfU70y5O_+I5C(tfO%<3&$+31?<B43%=q
z7t`_7GEUYvK)c4d#)lUb91q&mUgtdahZi?Emna%k$(cME<R<4wE+nfs3pK#5<}C4o
zWDTeA7`&+ExY3sx>o_k6;YB@X@iExF%~^aEdJUXM^cXdA1~$R`9nRO3o^IlNe4g?F
z&73ltDOxxaX}qnRk9<Jxavsx?wS$u)fQfq?Asujjz<Gt%zg?V<=tbYnSvUe_59b|P
z`So(li$ET74p6;OA7{cMi1c%UN8!aI&at1se9T$;1{4N3KYjr+$k9-Jpz{eQeG=#p
zr_lm3%=!K~*d5_)r$eWsoR8z-{!>l>B}2zJhdzd*JGiAPjKY<h+X~{w-QbNrckbJ-
zp>HSm1nmWOaj#J6hzB==uG((ynW@0s!`()|&t7h)9K@3wu@RD9PHulNV7$3Qzv0U6
z<92)n(f!;%=sk9TdxyS{<-^sN!!=*-=rj;NZcQ^l4|2b0f`~tNb{-TCaVx1FC4kE~
z0hB<lfl`G*+}V`)ILvjWFGd7&d;Tl%<Hk|6?g)1ZmG6Xdok2%&X~MWsltB;YX3>Ki
z!JYNrr$D$Bn=y(=?xt-3jpA;iz3DM7D;ce5ZrB;Lj&t2@@FIqLb^%Ppa<|f~6~`U=
z1-H%#?(<>{G@hG6JCX!$YXg`kxr<j~NT;}8=K%UN_fzLgD4yYNp;!A^ZXK0ro#Vbs
zZ;(Xp8rn1^akuUV%z5r&UyLc0tN9xwjl1$BVA8qUcfouHchg09pUHL4hHF_|G%#6n
zQ>SB~Ioz9@F{E5>{8cFAaob5DpPQEn%nRI4Hc~wDB3JZ0WG-<h<^ZOEt9S@zA$R{)
z=ofJhP*mqKw}4JxUg1ui3&pEkFDi5`=5iU3Ea5gJf|PQ#m0*@}XDA?fjr*1enB`pK
zZYWf6FVQb~oqJ{rMs|byh&KI|+~`_5>Tr{rLp#<gZr%jQRC5>5jd6=Bp$k>Row@{Q
zwcIia*4J^D{SHg@+-a14Y2+qsgUB7OlF}GW+<e-*G;^nqLZpS85CIdd-0$<iY~uz{
zzNMY}(?Uqz<pxbcUkCSy`#3y*_qazR!M)GjxD?z@ZqBbT|A4Ef(+OSNbP70ibL%N#
z(!*{31YY!VE#8oP$X!Jn{620w<u?1d!{;&jN8EYz*{H|dKWObU!1e2Z-9hdMmFPU-
zmaIl=h^zb&WSCoT$JKU@aOa7jILfts1<<G5&GSLVxZ_eFvxBFlAJ3IH90X_FconqM
zb?22bp|F$p@{7>l#rvHq6g+s7?_m(Tc|ml(We;yFB@p)VK0Ab#C(ojTx)*QRHK=>@
zLUW+7kN08-4DEOFHg*H%0PoZWaD8|aw_v=!yim$E`|;F$kU7Z9Uym{Q^VTOr<Ph)b
zCjbrLZCQ`LK;G$h0UE^n;w&6J%nSb<*CLqrh5{aj@Or2=;0W(GUswp`{YF{PFkTxa
z;KF%As`!lHIVaKQ5{~j7Ish8UyUIW-ipQY&>KM=Z5=b;J><~;G=e_(GXfZs~RKT3z
zy-g)&@w|UlgPFi<p>Il^=6z37*%@BrQuuq8H)R+kmG^EOL^61H=L02^_Z?+QvUtB<
z0LkWk?4;0g4lm$6kX+u;kKlJ6?;=Hk^Lb5+KrZkCD*<|m_iP1P1-u8P@UW1Va0dEC
zyj&MBFY}I5(EJK7YYQZcd6^?%mhj@}*(&9|RtocFJQq6lagDe36ud9zoiKw`@XTwR
z@cTM%uNMY-gZD0df47p?xCth1^0s(Eql)(_WwNVzf4mQaw|FhD1FeP^O?9BPyn|a{
zqK@Y*gZK5kZ>bvlHg6NHGa7h@Xt~hH+Z6}QJG{|Uc-X|#JOXLvy+MKA7T&;F+RV1{
zHqzRujTi3$yY0Nc=ycCrUb!DcJ9xc6q1DOrq-5v=UQYrfyLgSaLArUb#KW~7UNuFJ
zdwDq%@e@Aet)ZHNKHgsXtA&2vtyN$?;w>!)^D$4yhr$3){VIGK<Zb=*zkC2Ms1ZXO
z;;C0aW0-ej24qHf#a&>I@;>l~rKdc}K9Diq=cK=b-}e&?y7T|0jKxm=MFULi;%n(8
z?!h1T8v1tg-P&Pd5C1)?DcH*&_W~q6`H^2?5MKO~AHt9~KZ%ke&V76@N-6E<2Yd;|
z1AHbu=|24KN6_%)kG%<fKmMw5&^XBdi7J!)`F@*#eTaX|0g(XyVR|?M`BN$M5X7Im
z77B;?YiXAf%zr5wm?3=Wa`YYH-#q|Bq5L@dMI!h&j==4sPJT1JK_dC{C?OWjZ`=-Y
zoL~P9WMcTUsY>JozvL7|;`z5It)9StbRXEK`FrZXJj36bgVtI8FOl#ti67<zg=GGm
z1YGVE{*7T6Oy&E(0!wN9x9Rnn&L8|07BcudX`7JA|LVQ9fXU`pzlY8oz6YI6&gG}c
zF^YWt7tPSW!2jz*fL`RUq2Kos|JyFOR=__>zg7`HCh+k0sH!$Dgh(mBy%nU4&u2pY
z8oz_`colpB9do(PUrqVL8~nH?=vDInM`_-h{O(VoP{rqN2D65LQVfM!zLib|)$x;P
zb5+l8qhkBpd?hw3E)D!YY3tF*FU!L(afd%ZS%oHky^|Iu_xQ&rLE}FE#Zr(?{+v<3
zJm9BOGNp@;AOY@G{?}Bo*2{l~j?+El|4t`&`uX1lL4AP#u?PAF`I_ZWc)|~($nX&V
zU=I3*`7u<1HNqF3fup1RK<vm}p7JlzCo0DH3)WF+c!!{c?kiWp+W$erO<>}q<sn!`
zucO_9@~^?%BbZM&#9o2#D9}6wD+1_#6qJU*UvGh;A9nW%9&Lf%e!=6@@cy76XD*1p
zK>G#;dPs0-3}68Q`&}pm3Z6CqGe|JM_ys)0hXt!>3lS`sP3g}N!N0!(CPJ_#4JM8X
zUi=&+QXsnsyHSE7dcz(Q%%}i%v>=++yT=88H^M}W;BO5`tl*_q4DF<#m$D$I1nVj5
zb6PNwDw@s+E_?;^X9Y>L7(FK#45RPRCJK&Rg<_IG+X2vI!R8lWFja8(WniZXo_!r8
zT`)ZzeHnt6R{|ze@cUB0WC`~D3}&|Ak~c(h1Oag{m@6o523VdT@>8JX3+BFyz6*lX
zCtwx{#I!QLEbyXFZ(R}iorY`9s{*%IG2UW<*Z{N=!J9M*l?wi)DuObB`Bi{k6Z}dw
z+LeM(O8?&!FeyS*C74euzG?x(1>?OXaMI0PBdDQD##+IG3aHl!78S!pz2IR!6q*F5
zXj9fKxIyXV7J-D0ZL~TC>E)npf;0w5yWq=4cyU*-O##v&c(oHI?g_*rK<gG16SGG!
zoAQpmf^*TZ^iZ&!qHTSG&j#UkzhE;hW*-Uu_!W|m1+EJ~1_ZbLVQ@$=@G@G%0-v++
zX+)4l`Por{^D*uJo(d*V@M}yUpuE@);p-HDbQRvGHItig7iHJng$KpJ-YIl(g6tAb
zrP>-#VcT)Eyo4>S@ZMY4`57el31?BpeZTORei%F;TuIZMk8p`U{Ph)1ZpO9n6aM%m
z>;($vO;3hmkZ=awvxkLFDk2INz7d%BGosb=6wnA0hSSm0aAC)K_<c;6O*dP#@Ce;(
z$AydNW{VMCrzl&j@F1PqiW64TiMtcR?mCPmUg(s7BnW-zSio7~Y%A=Z6Usv2VWKd#
z7tAE#+y+1=3pYH4p%h^cmDisae&iGaCRO;JH?Y%$Kc>K7rm!yw`dPvkd(g@j-rtJ8
z9O2jZp^+<mCKCF2!j=1gmM@%1XXP#kGv5cfD4ci+1H2?mLm{(EfiP_lb_<2AKY<hr
z*Hav#L>TxANU3lF-4A8LcQh2Oz9#&x43^4;-_3$E6+(9zOk5WVa{*c{44`-0En(?i
zh|~!EC`eH&{7MeVI$_CA@Tp$-;{f_@3#GL3Y7kl}VbLN?jR173u<=hY+k~lcbms}(
zKL)ugEI$v-4&n4Q^cQ{igwqS5e_uGCg2+8WO$vUzUST@j-4BJagCKpvSV|7`3pa3J
z_mR+N7rb~Zyh*FN0pUHGD29YHD6}&y-1sTTh;aY2urw-EQpoP9FliGm!kBQP8b0k7
zeeVqmdqhzu>A=NaQ7nc0Jw;*LK)gg78lmqk>Z3xveWID$V0XWWe;bw#h#tnkl8>mg
z1}$F^?-9`aM9d(J_n>Hh5?u2aEucTiIwYDD1(ZP1|L83mBx3#pl*6Jz3grfiI%%^X
zBKn5zac8J#0!^%8qPgqP87|uR3Pg{JHs$~(Qq)P;IZ7m<SnM%TB5iA;Mcq__A1j*w
z2C(Bqp7+pqLX<_X^mx%4Ge8qWJL#*7Cq;Z(m7Nmp>;Twl(H=YW&WOC`VG!p;v9uaY
zbc*8s0!<Rlr~H4i=yTfTr-(w9fSecY?ZYV2L^CxINf$}2(9aP4ZwIh5MZfESoh9<3
zm_fEE@f%#{98qv7e99FGZlNzv^bf7k@<p%Vq=w4{(a2W-yC`}q7V4KoN9cAg5IN<v
z@hcSlT@1w{(H)ASUKV{oo7gL&>7PL3swlGsBE_PnWQdfAD(Jg4rJ~w3z%CQbe*o-j
zB5!(oUl(;#vgwBC0%dI~MSEtU@1|%mRRULu)>B@oT2wOygQyXuQC7QFl<e%lK<h-x
z5s-S(*K=V0w&>TzAPu4k7J%Ln$!V|DBr0A2k!DdsD_X6hxdA|H6HP<T%%xrAPXU{|
zBCj@JcZk-XL*G5oOg{|bzG%*85P2YSqblJpk-Z*c=@xB22=hIn2nl5cdPPBhL#9u3
znMx`8MWM4m9*Kel@Zzz^V+ITkh$eeNe^4~#bzFpD(X_eH8xcMI6MCbf)8!yfML*NY
z(=pMHo>1Q*RxCx!Rh&i@xo+ZlyP@DNzSs`)JH-p>6}L;AA5I0|9^&51=-e&d@jqzn
z5qr|b-zy%WiP2Nsk&HXgOI$GpEpM^wdib<YJiQB``^D=hrgK2N{Cj}<h$m6KoUgcI
zC5WFmLIsqAV&Na~*I)eU9auOd&ZQ_@fVe0En1SM~Ih61Z5>HVB=CC-fAK1a-<Xn&t
zaq6=WJtFRQ047x2`~^su_^KBa!^I_377`)8vl5r&s95g<6OrPNDdQF;-a+r7W8yh<
zuSSdi`2mg|7cZgsa*Q}^10+v~f1U~Tc=24?jX4v<v#5CRq&Q|Duuq9!qR7Q*@y*E)
zJtJQCBL;I;yn8=j&WX7*;Zve`3e`>}iF1B|WU@H52Yo5xAj)8$7k@~FcB$gMw8l#l
z51Mh+(#7E|0Lu`+y9Nd`#h<kUB}-h#MPIg4eBTDq9I-3yhjPX3bc!lZT(}G-^2Od0
zAag;iqQbL_;<Xf3xFl|)vbzHD5LIauiZ{|B;39D&eKp{+*o~HRSHv4>CcP>?P9-+Q
z;;D-vQX)R^0nA?$XDtIM7r*l<ysr>D=e_`$>*Bv&0l6VQ@*PAg#Ru|0Zi+vqbZM2i
zj()sq@gfRi-Vz5-0JBECcp5Hgt+@37`s&0-s0N~5e2eD%+v4U%c-SERW*)}UDBc<d
zx9^BwTLbkbaolfEXcos)Zm&iBqB9(Rw~EIo1J)*%PlRZ@Sel8>d*b3$wC;;{P;pDA
z*trlQ55%tT0H#YU@`M*X;uT*&y;nSGJS;sFzfC7;`ovjuq`zMr(}})EV&4@&84#-;
zLVZx2<^m6&h<|wiks+~rH!Y2a#UI+h9T98hLFTDgMJcE;@eK+d?~ug%g1AXcEcoOu
zk$#QVPRXA%m+g|gd>E1*5*ft^_eky+fb5mzro&%P$y*dK@sjk=JJnnA_X?1Gl9sbj
zKOnjPEcARNCqMk}FN!3^lfm_q)Qv*%prmOGo&FM&5F-qbcu`C!P-1!(eL)fi)v6qk
z%%|jdsN{!rV1`L@W8qr3WG_YMA|z)nU=Wd#|IwB<N^-av(8nY<uK+Asva$`=>A2)I
zDkzMR^!`Qx-dM?edOMwvq|i$_Ua~6-FbNXY0Q65vmW^N(rz9_hL;sBAx5>~yD|wb2
zJtqmHfhJ0dsE#^Ga!rLxk}N5u?Rko1=o{#zNhZ_&I9<Y_+-rtpPYcvDB|#rRFH2Ha
zjg~V<()0}mlPf8D8zfJ1(Ftz8By1iGUXb)tjPasm_yYP0B#-C_X`#eKk8zQtD+R5~
z62Vd!yds(W1`J-6gqWaSB59zfqEu2s_4Q?vhcpS5OLnb*NCj4ExT4o3$6GP#8<QnU
z3Q|-`PE%cEmE^;~avoNNY}(`1N^&VhQ74(thWXo)tCc`&kOWxJ*C^?tm+Bpfn&#dn
zN%tm5HcMtu7_wFJ+)OC6Nrv8s!FEYDMcM944txc@PKnC^L>@@|R505md6iCfbW66D
zW1PK`zq0}MP?F^QADVrVc|wqW$($X4c_a~UMeDI7h1O~Vl4oey{6sSSJq&F~a(O9S
z8<xbs2Qni0!wKf7gntqWV-hKyCfXtGtc8cJQco)Ab(7AVjh4GqdkCZ6DZN7Fvb&_Y
zlosA2l^>;*$zJIX0g&;OzC|kwFX`YXAl}kXtD&(^`g$)!_Dd5fRd7H$_ce^dNBTYG
z-F>AKE8v=+bo6aFb5Q#Jeh`1Dh<=JgQtNJ53Xr~50@nhiS}L9mk}hk9-NVwQR3{WH
z-BU%!AVQ?K-hja)(sLA`3Y8AqFs3kR@LMnuE}gy@8WB=1)m0po-uWASk<xMWrj3$T
zmw+6TuDAj0XlV?sxsFT!EQDl?^zdw$h?S<xp%5o6dKZqKkltDgg?MQXl~pB39eCcI
zE+?hFUTB_@zD%o!(^7v*QlF7Nrt-P7(y~n$?>VXHZ-6FBZ+s5PBx%skKszt33xYzb
zRQod|)1*>*S7b`>cSAi(dYXR1Y-t-MNb;m-N^mXmrGZp4bwOH7i|7LBLb_L-h0=x=
zfEGzx;-GO=TJQoa6-)2aDaI1%d$h#8CS6R4<Z@}U7Wx&^waK_LmD1U?ySXX#rMF6z
z)N>=$YoxoqAW|#c{02y!^d?=W2I*Nk=-VhAq)5pfX)}dSnxw^xVYb;ReZvI?TcieB
z*0oCCoCKLR>E`z^w07x0F<|aW57W}CL)w)Ik^9oqaZv1(+UZ+152XGS3G0%cpjdmi
zG?iWwz0xK#^d3qZXe#TII$j25zf}GOFds=LJ%BThrEzNX4M?3S-vez>%Gv<#6KTsi
z$P7ufzr*0L)Oj7CBhp^F*GHw1Apm_U)zOKeG3i=6`gX{k{R8G*WnC+P<|f<O2$5Z~
zsfS_EL$;G5S-WL|o3OA)_GAFidu8+WV0y|tw?fiOw!oPVQEyoq9jx9j`<Iqw2V_i&
zefh}F@L<VTHvVPw`N_2O7$20q_dkgE%NEk7=?}@8=z$NC-EBeNVObU}VS;5nbx;VE
zjXZ<CFxgtF1P+%)CV)i9eh5L|QQ0`UFQR0r<0<WbOty{!RME0AH?)q+O1?yAj4YVW
z55~%_M4=TYYgmR6o{-hh#yVaWM00k6%!6X>$+AS6ms4Z~9_TwSYm<VRDhuevc++Ht
zjX+74Wl#lihHTpu7|N7gGl7{Ut9X{aaFH!54gq$KOeY4(m3<oym^|6}RUr8?AFABC
zAp4CT>Wi||QviBNR<;-B3uJG~AW|q((n_^R_AxC9F3T3(gELoT--bf(s%%m(3>M1{
z_CcXU_7VfkQdvX-JS>x?qrS-La!r<70dBc$Aw889GBuUtRmx)NB+X6Pj7WG|C7Uq_
zW{oV80wA@r*8NbZlT{XhSugvJl5)3Yyb>rh$i5m6OHH!ps6Mb+wuDM1TV%iYg0#x4
zLy&Bf4Mae_UB;nn;k+x`^#VXUWUW^~?#U#dVubf)x9D-|lzmTiMh|2@pX0~tk`+@f
zvRn2`3t)O=Wxt@+D~lTk?1wVuQGoWz=KKY_{jv$E5P2jUybfm`%Wj@S-+;`Ia*2bo
z+cO~YL^fOj%ps>t)(<)?o1=uK5!our29C;hP@3qetotL7F<C4Xwd|0$YoPBckEcT*
zZt}k^=yR73(Iwd_-_-zvyX3#pqvj#^D}mkJ@=d>hxksKv&(>bK$7<O1l=t3&1uuES
zelWe|&U~uf-zQI{70rIRjdmNp@;@m+>?fDghYb$O*N%gS{_<yNV}D4VM@jJj`3WPi
z1Lac&pcf=x;0<zEZukQvSUyBAf)KguQTTgAUiBs<L**Awp)X86b`0jj<?m9FMuhx;
zGX@SHl`o@LbEG_kiU^|Q&t8FvWAczlz(mX0RP7KW_xFZRvGQ)3^W)?%ltbi%{LO!$
z7cW0!gNG;OYh7UQl)SMB3a8~4Xt#b&ewM0966Nz~3Qm&0L_cV<yyPFWQsiq*v@1I=
zzvhoinkpZqmsFa3qZ**;@;|AHHACJdg+`{_DuZN}+~*^-vgPkjg=CI=@G}_9l}FXX
ze4gC%7?}C;7hRxtLEc8s=0*7gO6y*d8!y6{0{QT6kV5$pdg~X-uPW&McUf*sgXk6c
zM9RZml}qW|ezAOSI%G=ZnO9+=R4zRPyJhmQ??A4}Z`1yuT)wm&3KjC*w8FkF-%N4%
z8}hmJ=&O{krlO;2`5p?f+>$^4UtC*$LWYsm%FkW`vreu)PXW_<xs?KIx8-&8>AePd
zjvAni^2b@QbVojA7#dCTWLg)s$iI96Lu-{Ee+H6ma<Aj)>yj(-K)U4xl!)q)Z#4tE
zSH2_<t%vg9Spe&kPoq;9{qji<ah)E?XHmrRu{`N(5a)pWCe4#i<nLM0IV5-G!0xa-
zAQvV^<Y#$cj>?x)*yySJnJK^?leba*rmG_0E$F!^gcMPBSCrBQ%0qFGPT=fT{J9j&
zJ&MTNXzf)9r=#Vm_(=fbrFf+Qu6Zk7T8P#@ry`Z^mi>yis9@%R;y8uCeHAWrro&G$
z5DS@u3K4zG+h0-Xf$MxoF)IldAwUt94wyj2wuLZpSaB{E>cNU0x`9I!<J+KjM6sMU
z`=N^SbSH!>isNvZBNQ*?Lp@T#qJ>zL!YK&`_n6|Fn=lchXj}*VSVi^wP>fS-r|85v
z#Ys9am8htn2gM}CchlfSvSJY>NKzD&5@GkeqJ9hX(iM724rC}+Pz)?n@yaXkFiY|J
z21sTr*pwy8QN(IsH&?Opd)UiUG&(6vov-+&6N(oU*}p*JqQdVE>|Rnl^BOb?6?dmX
zqeyY;6-ZuI6kJE^ilQkM!@jEc`#2;^756EyRi@ZLZ^LVf*mG!=D|W8|ScT$mDo?tu
z_$L<zZz#r7Zo5)3VI%ZzDvGz!`n5{Ir^6W43a@I2-ctO10)wehY^Nk-t>PFhMd}n`
z&G4{ZakLDIw-rY}1!++HOOfnGMei~6-BGl@k5-f7&sezDteE@{S}lrmbcC~2@kRtJ
zv?;!#Ep5Bvh5rHit|IgfmA!Q+u26dTp5n<E9KNrx(!9~BSX+w0JWwRk^V_9({w|o^
zifJhzJ&H#Z%IZ~=<N@ZPVl}0A`xJE)G3i&_n*;NY6l1+;Jy!g934H^KIT9!gD!!qq
z@QLD+0oWT-q|502H>?;m!o-L|NykP;6=nM%^Hh;Z`-Cw?HGT1Dhq9K^2yV*r6t~%>
z45e+Hhw>h+EOsl$Z->Ypr5i>0_A1%5!}L@hc@}+M%Ir!gcq@6=!Q7`*-i9;#mG9Ez
zcR=ZL6c$uI%IvM^^i^J<N!L&LxfZR1%HJsD7^1v#8Fr5-Kc~{+P-V<!^o1!Ks2nm}
zxiJXL2<4yO!<nPXB#Nm<Do5z}M3l0u4y|L#b&DVptt<@uSc9$Bcq;daQ`T}IazfeA
z4cFq8eYCPpP^KlL@1)XgCww}k+)njDr<GIbJoXu7_BgnGR+%S*!a3!GwO}SH%Y31i
zq*S`WrDWxAG)tx^zwCkfdF3?PC8R1pqXX+{%Gng!OjquAl4yqVmEVD#sVt-QW0o?T
z=Im_c{E3jsQS!_nxk}a7VCE@HsKzQ^xtUTT7nJkw1N5S@Tn>>-$}@*>4GNUcFNb82
zGH)WT=w)RQRq$O=PG17MSC!e*;9;@SmHaJHO4t3Dg;yHh09u)HnCALx%3_*}%9Rs-
z0I5*Uruw|=$^<$Wc0;+40uWWonIE99S~*G;led&E6uhlb_H+QdRv8ltkviq<yYQl3
zdHfUT-B!9%h@(MiqN$`&`4$#LE_amnF{*HBQZAwhc(ZcGK`6E;cRT}_R;9NmK--jG
z&`;5>ytfB1ca^){A=07zVJZfCPr1PdW4f>W<XxzDDqVhp$OB~yg<ZRp|1O7mxAJew
zr1mJ?DK6csR8v{tL**caA^Vj3@rXEG`jr!D_5Dcs)5m~$tPEKTGN3&C14IXv>9kgR
zqTF!<c88Q*TR?`DOe%vMQD!}b7o*Bc_b`~J%IP+=#*}Aj(YHgjW-45BSA`})VW(<a
z98h+twou*49#sfc>+Ds%90fyxIlA$$JLTVk<D>eOY7u=^E2uupPo<{*gR0X%qUEoO
zvVt5^MbdIBK=mQ5_5xM@AEFhcid_erhgDTiK!R1hlnDq?^)oTZBdWYKK!>VAX~7<*
z8b1Lj;VS<&Fe6l#UO?-p3j2LrvPhMP;wn)p6TR1tseXP2BwF?CD^NVH+IATuh*536
z2+&y7%zx2}S4r2xiv-mo3RIs|jqiXnXH+Zbgyvb*I9l|bQ_Z4KUZTpg5UnKD#$SP%
ztcrLI%oLS@YRb>6JZ95=KUI|*0B)M9Sq-#w)r^(E&QPV40W?!}a4A|@szNSEwrX`K
zyvR{~M%%1hRdgdn@>JP${3KsBr3@$+RLeVneNpvE47|Ujx{QiDmjcx-D#<NW1x$rA
zMXInl_}wn6n49P(yrR<3EPPd^r4JYutM1bzUZOJ6G*qhk<P_|dt7>KftwI$e2lKk>
zIV$M7p<442oT*f4-$LI_RSKOLzNN~ejYf^?Ys&1_s**F&>QEIPfEV{vlbA4nU)4SW
z$xhXJysVrq4^*}1VZKZC3@xy_RnJoOVUKErHr2hV1RhL0R5g*`eX3-txan7AQDp9s
zDl-5k9;;d@tude)Uk&dERZ-;j6V*=I3Js~czX0^Gs{8_mG@`1YLZMMr<0<IvP;cG|
z6sN0Ne+G8l)NfFgn7caZ2)H}d6$e0esn?G|!$Un}g2-+)4j<trRu5CyY_B?g5n7&V
zMHyW4Qi~}l<*i;xUxnJIj++Ot{pu?;#T`(uqfnENdg63=;j313!%;u=Et-xFI@N6w
z!1$|qw0k+Eeslw^0QIyHkU+I#JY<5@{y`vz)qxbd3|1ElU?N1VkO1b0+RGoUQ1v$#
z(F#*9J^;ONbvsRp5$aJ9FpsL&&=M|E?ML@hlzIwnV~?q4P?kJe?R;}RF2-@Slahro
z>MyByDpuX{Gc3ia1zoUvLLKl7u;bNRo`rsbI)s+tC)KZf3lpc*Su|IiR$rnz!87WA
zX<K+!jU6W*0JYD{Ac^YsREQ+0XKjF^$?C6Z1DT>ey$N9F)$cp20h6lUL;=Dyb!Gvu
z)72k^gJh_q_rPwZ`p^QvWT_?JKtEf}I0S_pb#)9Ba@AjifSISBzXG87>b-w~Tu|?A
z0=cNpp^fV$H9HIgEKr|(6_|zUO*Cy6saH{D?qzjfEd$tB)Dp^LURD2=4Q{bIl`eOQ
zI+?=P*VLmF^e<OGpxjJ_`bDbsysi#+fr%Sx=Z|Prs#`yS`b~8_6#-VMPX$Jp@perJ
z0a&g2&19(8sUOket6r_6%+hUj8zoHdsHai2f0O#@fA0YGbJL*SqP{|}$5yp<794F;
z*Hf6iL+v^n-rrMue*^XVYJWP_(52o+Tg7g56Gd)%)U&A)xKDlbF#7t{txh^z@knj4
zVt_c^+6fN_)Vn^xPcf)&o{82IwRktMht#{MY-m``r)Bhr`W>nm9aZ0)0oR_YO$ksK
zQ?GapU^_HJ^o0Od&1Aa&-88RKe863^<~*1?HH#_iwOiBB2IxJS`5Cm4+pBpc9b@v=
zq&<We`!p*kf4N_C`B&&4&?u-jz(=!_0`tC_cc?<hPg79<O9wU2Ohn6Hll~^0Iiwln
zLp?zAc?Ev#Kusv!D?yqm3($91^YAt>gEil_q7|ayE`U!*G}A_CAsMRqn?4j0p$Qhi
z#8HioCe27qs2&52)@-F){kY~&7myf@YBKs_HM4iXwK&aZub_28lUIvYye91>C?se`
zIIwh5GkF(=bV~Db5Bg4P&XmI6Ga4BaB4;(e>tN`dCL1w(RK939H2WlJ=1+%-WKAAL
zWm7cU<KbeO1{);Y>Y9Z=K|e#|LmRSu&G_#yv<sRt+Vx-5bew<}mo(~^!7R{tQhusX
z^JW$FiZp-H`{%NzXeA6@(Y(A8&Ro^xP!6hCQ~MCkI7>9odxMs0)~i6uG#$I3aZPh<
zIn0-9hEjoDp{Y9#a$RGh!o-`Jw`hW?(oCdXTD8U_56oMd1N3UF(ey2aPqmu;RC`sY
z88;a|)oaQr)OuU9JqYISXwqvynly96;8U|x!|;G;izb8iPOX}mZ{eqC)BH=d1?`%(
zxI!*>HRBS{>d@SN5t5ynD3oHkJkW4>7-*Mf@_9JgtvO!>OFbIrJ5cD=Y!`s}P$M$J
zwLVSL4H)d#@Mxhwpn0EyB!ilNSAsmzIJ0T;8q!2j?eMUsh#u_`&8bZ2k7{1b0ePxX
zyTb06Mo0NTH*Fcc)ZDcan&fwC6Y1FVZf&j!eS5TCFF|szwt@B_-r5H^spYay`#q%^
z_iHnxX!&ZJDbMStUC@ak9n>yy=E11|ZO04f4AegJC9s3Ev0=~;(Z<oP<%o7Fy;DQA
zKT>_iF>Qwu3enm%_s}}7m1dw7qy3z6GO=1wBK(chI{N^2LR&>U^LXu#R70PjEyxG+
zq;@^+TTf|2DX4T>n?BD8nKRna&mnVGyNGHc&S}4T2=j?r-DQ|h(ne4)IawRM8j2~}
ziL?nhuVpWX!Bp*g`7ocRy-7ifbnQtw6f(3n9WXPs%z0>KX}jKsLbi6LH~h`fN{QrZ
zODH>#r!6~5fy@iq`LxBpsI3`-#wBe9#j*>u85A%s)c$Wj(2BH4l;FLr^&N!%6)m6g
z0#~*F?#3vJwRIF2EYZG5k)~4Zqj%w2nRYqVqg>N&+YRV)?M@!lE3|eq6s~KBl7VtV
z>+MFX+bXSR6}Z*f%@p^#rA_dJ!*$y8-@rt@b~lCHZfms=b-AN0qLp)#_Fbw-Y}OW+
zqt&8~{S>WM?Y@IRY13v=e7!@vc@@Y#Z9i?h?`!W-M4(GMnGRZYYfD7X>(P#*XuGpl
zyMd~Z9%_@`MrWV)y=ZVBYZuVGJfO{=3o@wPMRCbtZ4|9rN3^2%AUUf2U;_Nzp<7O4
za@DoaE6PnbuLzFr(*5uvm>xRedO+{iZKL$|9^G3sY3|i&Vj<$G`-XyNzD}JF)$jP}
z0xfXrpzg>u$oT7SQGwwhT`%3%0lFo$&<)fDEx-j1(!IU`SN5>(38l$`bu&mIL^tUS
z$PwMO6Ck0wb$j7Vm~PGI&<oeS`wkq9(ETfbGe>oaJ|K}g{zX7X>72jEqVt&UKJ9U%
zbrYxv>bP$4moO2dbJU|RR_9G0(}~kHyo<gQx*R`v5wBZH!Hxu7?hA1Ar0$IuVd<1k
zNTms<b>F^-Yj{Q{{t)D>?lM(upVPf=MPH)sQ6O4Lx`T9gChHD6=_{Wpy5t%(&+GCo
z0WDRx#vf>Dx=HcyB3<`JD9mT*LNdY3)csKo{Vbh^0<YP+^V1=cqdWgRTDiJsD5#sK
zYhZ(!uRBE}yP#V`ne&Uf7i?%<(mk6Gkpi8=8?8cJb0|HyMY=&sbzaupF9P?9F6sv`
zuj*E9#1B)f`zRQGm*_S;gh;6_i~^x$x@EL7xTbq80Iln~NXnnw(A6XZyHdA;p7d&+
zM<AHDbk9=}M2+r~Hn?4{vwQ@U+q#h*&}+~wP|@?(q<eW9(3*9LcGzvv&8~pKc3mRv
zaqsHhqU=J4?u~B%dQbOu5Jc|lYQmu3sVk;u`+-hF5w0%X&$LPG)-9cl%hjWMF&-$r
zy2)?iXMU)AZ8r4!bu)Wl{*i7|5WpVmp2KG_oGt^p+h0R}Q0GgvP)~GkE`r98ZUM#q
zhjmjg0A@rN!vJ$s*Y-Q~pXy=`!qS*d_c6x1Lw_j^eXe><ADC|X8T49k*Ka5U*{OHj
zg!(SMpD+46^uo_zXt#d$f0MPo{~^?!d-bj|c;l(B6aw2ze~?bad+Yy|!Tdgb!iymL
z^|z#O?SNi?43>QK{!B>v>h~T4(@(#91zHF7S&Ja)uRr=Gn1}S-V?YVeFQg!6pnel2
zwu1C7r{T<D{c|ruBv^m=19%wX)c-FV=8x!YR3i|of0GvWVR`|by9(Dk>1mG8*HD`J
zsD9gS^hN5IF#sB+cb^M#Og~%;>}b8;MqnS;k7R+w=*!79q#tOWiqp5=houvG2EF#<
z^<FezB<LsTKu+qNr%Ql+N?$-T#cBP^6Crv=zw80bpVfb>fW|rf`k#T8sQ-hG(<kX;
zpMk&0`hADtOp1Og#Tm})x6|?}Rlo2G)YJ5Xl-y6(Uu_37L!W;V%uM~1`DkV7|Dr@`
zw*ITt@IFWXr;`@7x%zfG2a%^gO=s8g^`Fu*_JV#5)hk`pucFEGlK#`@(JIha8DYLq
zA4QSkB7KVpu3grDy$}jl^oukwaaA80fw2_pPtjadqTfSrvr;`iw}1ynzk|N`TcJO9
z6wK>-#Zo7lH}ugI_^s48J%IjAebg|RRr+a5V6a*rt4H50{pweNR-+I44t=%yr3YZQ
zPX8nVqp#OzvC+D%51$H!27NeHDL3k)+3@L(zGyY<HtGMF0hDIFL<;p5{gpuUwd&t^
zml6qW`WL*Q*sf1i;nLjIYyN>ohkhC@rtj(B*#r~!^&E1vQ~$zoSbCse_%%ej^d8?r
zq+5T4;>JDt#%M_P>hm~YKGd_CF_u34KlH-w*IQ`1d!!$wE%;;o8efPE=(}H~_2-~|
z3GFDJ=))SJKcvt83!=mNPI_64=vUK$xKaH_+i*#r>Jymg8`I}B0egpGo&-!+L-|h_
z+D^kA%8~3cv@5~%Fud3avfB``5X?P>n`CgW;RBR*xOf^ad;)*H48bo!<b7{LRXDi&
z3@P+9?>GFg7H9_yJ37GhF)X4`t*_yQd4YL<;jsD3f8x>}GSpqeFaiu*%4i1~hN<K<
z$dE-Lw!?<@H9!qEWR9T~Vo0TW-6Mus;{g+DsQd+bVTJ+=6v7ST&%jcI;hXj7J8JlM
z8C;Asj9&}&C_~uiaORl7pK_|vhOgg2-*H2Svll;Gj3KE3FtLW6Yru^&)Kx+BgyCnZ
z4vjas|AW2+!>mXso-{;=pm55d%7BT}hSQti%o)R1sSrstWYE$r$*`2pTP7Q7ThU4}
z^pe}>4IjJ1!&JjN=YW!CU`&BRy5Y5HPBb$NhyMjyrs2?LXk;0DDPEOrc%Cxwd4`?z
zSmhgrhCwbEe8&T=z!2L36NLtODnyD5;ayO;YOp<pdNHm#JS;IpQX1x(;ZKTFl^edK
zQk@FJ<+nj<46z0<YYlnv^zoBA!}F;?t2boSK=HQ0O3{r5Lmee68V&tazJAA$K`)CY
zL!%b@&4$Oc&u%e%LK9r8f$=d!+6*gAAnk@<@*#59Fi1rW9fo5RC%k816`}9G;Wicg
zbQ*5ohWZ1;d=ybQUAhc)ly~hmr1!&ok6|g@biIZ}RFU=2u)P$_K7;)o!1No+u0isV
z;fFRb9~)L_0W)A&MT^>D!~1majTlZ8KxEV~CWpUI4cn=xV9Zc^9tt~*-?;(P)wr$z
zeQw6#VEE+pFkYoM&~D@WB~aXBZ1jQ5UgNAP5Km(<%`INWrxRe_+n7q5ynV*)--3C-
z$XN~IW4!waOkd-aeEhzC#y3v^<)E>l8V3E1E_AN$kg*^FmI93W0*C|}SH1`6Afsp#
zNU+nmjpn-$<Dyg0IAYvOM+QTU=~NvWX8f!LKYD~wG6VWYjjz&%Cer9m5yWH0S5IST
z(MDg&JRUdhqt{uiG1?0#aYox7T$vNbmna+@Z=87;3JJ!S9-wvFnEW1EXN*UCfqB;G
zoJ}+1Ib$ScS`&@u)R0Ls8tGX{HoirP#1!L<E{L8tCO$+f-8iuYBg`<GTOpZgygmbx
zS;m;JL9&grPJx+Y{FV0ExyEezT6CUq>BoT1H@Z@w{DLw3d-Pp2Zn%%JTrz&+WJ9CC
z*w2NDLSy4fbQT#`wL;^v@djnat{B(QD6SfFKLc8+v2F}rlo=b-pm5E2l}eM!jel6t
zsxU63c*u35kpg))jKAi9S!ql#K>en1fT}yIj6<|4tTyia0g|_j#tf=>tu>AY{<;H!
zo6yNnY%q472D8!F(1z9>qbD8NZ8BcF1BaW9H@x6ei*chI*saDj{b05kKgxngyRkAB
zdUuV>-vj9|uKNqjd&X<DC%$jAQng5@arsg7Juup)qSa;O`oW8CBZrO`JT&T@w?O-h
zl`3fT8&?Lx{D5)%vmk@Uzi+|sCr0`EAVbD}cMN;j7&9MzBgSF{^u~-U{ss09)ABVC
zaWx^zhDDR<(zjslH1$T|s_im$kux49E!{}FO}}x`+GAQknccmnkMB|j(9^VN8#KI3
z^XO&cZQ4OAz<nm!%K-H;nJDDwYr5MB4L_5E1#-|7GYl{MO+QlJ^^mFA4wL}XG>Uo!
znkGHObqX?Fq_y#3(^T3<2AkH<yc}Z6*a?v%ronnR6KYEFrMk>8(<A}(!%dn|T;~YW
z*sIVuYTAUjqD!RdYZk^7Wm>l!B*xTBWhSwv8v0;WoGF76pC?Ql3XsK{My^0T!SpSK
zaZZ|^y9(whQxheKPn+0*AZJYD5+QQdwDS`5&Y9YpY2%n^+OiJ@lT4TDL6S|^DFBmV
z5}$+2dDDs|7)7e-2pwckGd)X{Lg}U{9x#z%GSLz$({!GquvsPztsb&XA02^Sj;VG!
zNUmvd8Vu%{mQqnrzUf;!fp@|5lr}3DO=cbRrd%@lUj|HpX&IH76q-T;d);tbep-VO
zUNtp}(N}C*Okd_IF?~!ino`r}bda{p<eLw2%@j#<XSvCnri}{Ib3>54Zn{Eq?+ueT
zO(~V8u-Pzw(-c&UkyV+dUPP<f#GqQjTc(|q7OXK%BiCw8zfpmGooSqtCX;&8oev;$
z+jNl*1T~n7_rgS@NlCH0JEpE4jJL@&I0k03X*NCSZKicpDA8_OJOh1qP01U;>@evR
z5V>didk*^Un|`35snevHk1P7Xl)4FhU8Vyy7-zT1pF)m3Chc#uOzJh=prd6EO=IKX
zVxMWs2VnM_f+;&WVB)<2(LqxUEl{4AYAMh(WExNAhfTlI4rs)*k4hs(O<&Pb?58Hv
zhmagIm3o7@!+e2$S68zqMNHhx17{)PZa(0R)=qOyI(-jfw|Vg*aQB$IBQc7-=4=|T
zr+FN0TD;6UI#1+n-XMUbedcC*5A8SK{2HwT=4|?CpO1Nh6h8TydDCFY&+Jb3>Ou3Y
zSwQhOe^?8VL+01D5D74+(nq5M%~wp23^E5*Qn~(NbKZN<2sVdM)klc=*sCyj#610N
zm<Tny&%<R4Gq0Hnw4>(wljw^y|FRsQQDz3A9WyU2he)*fuWnqf<L0skxE*5_(3(2d
z{4G6japv|p5IJEUI0yB3^D!Bi3Fb|->2RJjAE2zlDf1rM{GTzq(x&IEIe>PI=gb0H
zz$Kcen88dkzZd|GWb+w!^re`mSA(24%k2P7HQ#XoN}9R52tK8otGF<jWuDjvN3+dw
zH^9s>x6@V6H}@$(E|}F6pt|TZ|6#;HFPXpZgoy%k0xjYT&H4YWeay#?K<2WUqre5a
zVh$;UrK{!<BS^7%`*ie`n7ifxt<=1aZt^m-gdzdg%z^|cl$%?<;BSTbcQ(vlH}`D-
z^bPZZY3Qpohf=oarrEiP%B!o)6X?)SwYhFCxVOwzlz*);D;B^+t$E9L7)+gc;Y?uH
zo99dbxoyt;9{x6%zxWq+8_gT3u>X#Eax%c0%(7+}Y&Ji47kw?}EuJ8)<^%44Za04?
zgx+1V3r(6G=4>auPwtuDr#I$(^JX(-I?bEuoZ18P#tJaI%uQ0Db(??s6U-j7a3&Oc
z&2Q7NADWF+Zq;YDQr$zp*@ws@bBO_7JT`9;V4wr$cj?Q6gXV=#(RyP3g?5ue=G<DK
z44XfC<OJx5S!@D#)O;csmY$j?;l6YkGk+q1r#mc*4uR=vS>g#vH%mMHBJLJ;Ezova
z=FzFQU6%NMTxSnU`#cPEx8*SlB6}>?Q-QhHvNZ}VPs@SVAmU{)(2CL9vX$1I`z%)j
zDW1RI(oQR>1D0xvf%{ngp?r(4<t<vZ`&mAqDDFYabCgH(w`89H=poBwij@RdhFrl6
zv@jB(5M)_X1?<BX7b+PDww%mHE5uS6g|Qs5+--+msO4p<01LCMrz};t<?60+c>W?R
z88lxVwXEF>_aiO2!N88PBncsN%wpIM5^ZT12WO63ob8Z|v2c&06>Hi26F}oEDoT@|
zu(aHRUcAMF7KaIzU+CR<((=VOz&vFU{swZ|vV~44pRqK1qwlQ6BOKSzdCt<sKxd-m
z6y*k!EOYN+yyq?R>GhpzF%1Db%~IllzI2P40!A5@{asMVv_!v&!DLxXbn&w-5&cle
zv7Dl<ORnWH?e_C5^=@z`-?C*TS{E!=+n{&R;!X?JOP2Xm{!`$zEDwi%p(W=dU>8}Y
zP;&0FWdmgZu2}M@Ug@f(`ZM@cY#GJN(WS&9pq*x^WspL&WtJ}}<9^NJn1jA@%S8@I
zh2=>h3|_Z5ywG>Ul1%TBO3PaoFmGDqRDxAySy={q)fVTXbLhNf$)pFj#?l#si&$&9
zHwtE*Wiu6W*ITBM7q=}TO&|>xu@W9OT9#L$?~cXEful{99)I}MY<a{2Xp80Lf6;2S
zB-3`R%~H4+VC|OvedxPuG5`0fvTTTk$URGzGYvBLE#>q@_fE^@EVLe2HXVkgF3YxW
zaq+t?_1EEWkEM1ZE^x19+fA5%Xc?Z0R-ffPDxdAQh#vy&kwu?|@jkXxJpjspWgQ)5
z8??x0Lgb01nF@`DEQ$Bw%&^5y$7Mz=+pjr6M=j0EVB)Fed77`rEN@YKdxy0&9$vUw
zf8hYl&AQ-U^toGaP&9U@HHOx$yR9u55ZPnh@FB=v>j5qN^|by%WxHP14|(v=+xov5
zU>>j*(Aha3>s#-j&)51hoy76Cp8tiu&wj`{VJScZtT9#K23m*dI7X0lPY#%et^PlN
z1Y1L9VK5=qBg^2-5o;gSy@y&?4?!}_THpqeaO-9|;2CK>M0xutD|<ggj#<B;g3M^^
z_;|FATeqEuGci^>3nC}1M(mZGF7eh~3jvd0{cI&VPg^h3r8#3QrftGm>xX{=JIPwv
z3;kp(doj>btQHDhpSPCz;yR^TuU!Q*&B}fPk#y_t6xPqMo}C91nbu*7Rb*L(bSNs@
z`Ujmp$+1pd1%-U8j3QIc3)UT_xOx|@h4Wyr(E8G^AVpSAHOOV_YoX}7YJIg9pvBf2
zPuMN7u4#pSsr4qE$t<(B&{pr7bu~>p<<>RsXjNGIE}?bZ+GoX8yJ0;n2eZ=Zu@zoa
zSvUQJ->%wvc?m>rIjuM7<yK>jdI8N^>pH3jsk44R2*rBq9jbe}Z9ViOG#aeWt-=T!
zt+!qQv)Q_31I)Krf3Ls@Tdk%Tc-UtBmhQlI>v1YDxNH4G0g-#wXDPXG-}*Qe>YdiL
zw03!5ee??Kby=M?HgLPG{|3Uh9&08Y&giwqQ2_LzbsXJSeb#xm;7q@DYZzc2SsS)N
z<gvA!!aoDn-Lugev@S~l+K}}l5nLO#Zg~LnBi79{TaH@$4}tmAI&&sm8?)vyps>Sc
zc^_b|woxb5*tyvv=%AUqt)4F8PMd`)?snOhz6u!++uHdcyKT$pBR+d<`~-~2%jRDS
z^WL_nbWCTTZT)}IC)=EF(eky;358uh+oO}vJ7}8}1E#-i1?40U*=BA<E6DcsM2H-=
z{cLlh8Ekt>(TNb-#3%6Wh;1kyouRg63vp$_Y~o!I3AdfLz;1+X<r&yLYMVn9cagU8
z3-Bq*_Q{tZ$84tOFqUXrWE|9w+m62ouo#<=Dk5WT!O`f8vmK<JZG!DL%4eUn`6SYD
z(NnhL+i|&1+un`G=+D>^rvm$|P2U5OWIOBzX0mM}MLtq&u2lS=W}6%jf75OM>w+^G
zwl%NAV5aTo4*;5F6G>qr+cr$EoE+Qs#Zb?+t*`<t&&E%J7x^}682T>Q%7bYAdC^uy
z@x)8EQp%YX*nXqgw$Qe!2L_95Kh1=R%QkTs^sm?!OEIRawtp$CP;6WBGq6i+x2T%0
z)E4zKu*+=gJ^<J?+tK@wEVqeYM_+|)8YPCV+nOj+dedg6wRn~7lgAi~v)a}}vE5s?
z&;ACt#x{HaqP4ale~hrsmaz;P^|ly_Dc!bxNB>#WV4FslyV3Tf49q*WGMXWpZ0@(A
z*KC_b`P~-VL?3{)+9r0v?Kaz|Ya!WgbH9bwU0Y)@S{=4W*D;8DPMdHthJD{Q|1pN$
zX~XIaPlxSW3LkaZ)}}(V+jfO+#2%Zc6(%0q?!1D&J{!9ZlKnR8Pk?!3i%$o6Y@0{B
z!2#P4mFo}M`d2~WiR~OcV#7Ay?I0tz+q4cGwXJyxl22{Ud6Y#NvvDaQw!_~2CAhA3
z-h3#!+uxzdWT(9)7k#_zFM7fY5Bpz-Kz7^be*iR3`_G5b^0GJ6!5VM7otAw2?3byu
zeZPG^Ewm5V>z~4)kNsLV`h4xS@6qRHucp}dL3^i@HemjCulX=>$i629paJ#}su~Kk
z&!U>#AiIzX1`pdcbiggxzM9TjgxG^VgTfK}hvjfI)IM$vevvTyzHE?i`^zCvkFZbJ
z3!jeKm#BdmX`l8U)T8X<ya9I1-o6ni(e|4aPPlm7UX%ft7<+vhNUZ(QL@37DpL_@t
zC+uJ5!o!pHl}o@pW#{Y!_G$az^Jty1|9KRxv-Ul2Lgbu%S|G-hY@bDUZi-#?0Il=(
z%nbCU+O70~oizL37vW60eYF?NXV`OWwExSruigl5mffFb`D}Z!J4lXwkq*pUd);X$
z=G)tRK`z**QE2y~y*?9;Ub46D0<*v#<^{<@d+$k*BKwq2Vg9oH#)}|V?JcL^Xt8}u
z4kSzLk`KTvwg0GudYS!WtQc`H$DT%mDYq}Z2yTV_wf7)%-Hxp$ULE!jK3bJ_-vEr_
zru||kE@G8Ek+K8T_MIiTmbdK96a}iWXHgwjt$h;}OV!!Umw;Js&!@-ew*4^GrZw27
zjbPY~_UiM{yJOF%dLL(#z1###&GxCu&~LMkr<uInUg-^uyY^?70_~pt$#S&r+cBTx
z8L{uP!u$h!2yGg=>`F?XblZ=!V6ewN_ZF~w?H=cV`Ox0A9wL4AU38wW-@cOx^+)!P
zcYr*$*Nwx-2Ay`lVQ4(De?V{HA^Ut6hz{F(Xniwc&-oJiPwn<wKpV54-2jJoIC_#`
z-qmr22iM#juN;NsPRH@PP~YX4asnbAjyl>(?{@gn+GmgBd)n{rbrjMk0z4g)Xie<p
zSVFglx5F6~jOIQ^EnT7g4g<|e2OO@H)bMfq`VIPg9Xa&G`Z?bG5+Vm3V-%+LcN9{j
z=a3^m03^U+q%}ye<Ld^H5XZ;YAbG@L#Qf?K>iBCPM8X_do52isJf=K)gu{gbAV(cx
z&QNqlI$RAf80DB=fH6foEVPw4?pXgXL}MKG0(cSYxbqz(;~cNhGjhT)?lk)19otGV
z!UTt6A<#}bes}@uryT3!;Kdn-N&~&Kj`Cw5=Nuz*ahVexxho)<<XHR_z>*#HQ4|(T
zam=PN>GO^)$!MiIf_4HX&GFA7V5d8nR6CXBNLmMxY{#pmAUTe3DnHG2tfONqd5$J}
z;PV}Bw0*qbn6nk?7ab*kVf2?AW3+xOa740Tx6t86NB4>xhv-`qmmTXY{}rk_R&9aC
zRfji~x)nQeY3)?v2xvm9)X_PNzB0#7S|D6=lu|&v+)+onoC=4v3a(vuEHy&%hNI|5
zU{^Y9?jScEk7>71<;ea7q}p+oX3|@Zkvg<$965A4qSoQ~XdIruI)?|9mDf8SQ_W(d
z<L4ddyyK{F1x%BpllJG$j_M9v^%lq4A@sF6jC_o@%~9lr>)h_(u7~7Z$Bh)IcQ{T_
z@x(pHbXtVpcdVk@qtns97UY5BI|}V|IfV5f-Ht>mDRTBWzMT%*>(ERDdFYr!8KFK$
z9EJY+9hOKaK62Pv0Q%T5o<6lP;BcqG3_7}L!}!FZ6vO<GV~oy54m<v!g#U=+wGxPo
zI%HDxJ$3Af1#|5GEPV-BQ`hsh_a*@n0)gBm2?1QH)@rNPs?}EOR&A@TU0qtM)>dt+
z-Az!mHGu4^qJRnr%8u-dAe$Q^2%;zgg0hN&3kr&&qI~cC{@?TXIG#B(@60*(=H7E=
z=3KYrngiO!&_J(rS3|!B3T`IDTzbszGI*>6*WIv`PA7R7SlW(x8k#6S>|>a`5~99_
z=cD0;pJCQoF#Qb)RJ9afI7GK>pkdc5_#0%{_#A`SZ8%$q)*eF^y)c6fnW1RyHM~Cr
z3;PW5SHKK06mf7S)L?R;*Ke4ig35pP8+^Y6_kdxl8^}RJ|2S9*Hw^z7vmRmi`)`m)
zLmw^j4jIN$j5Eq$MMdP%hH11KJ#6TtSkw`N{tQ|%hQ|~xjx~%wkGY65%u%2fZ!jk>
z5)5BZu|}f7)|3WINrqlpe54v0x1g0~7`qcN>4q<9Uy@<CodeNKL*P^lG|TYCW%!$I
zNTY>Kj^Q+YVk6fOe*>*NL*RCp$Tys8hu(3+pI<|-z_5~jafOD(v?(ky80bk_Z19@^
zdnE?<EtDcWVc1FO$CHK%3eKD|>{$T)(}oY}?Q+I&m_q2KhF71U@0_9i3Yg`F=Fj0w
zg<-<yuv=x=N<Wng1{1ARs||PQ?yfQ9mcr6y!vreuyJD#F21=b_IK}$v4a55(*<ko6
zisCQV3|ZIEY&4`@256JPwhuBbhF6ndu+`wd8fa~X;zE#igGjN}4nr|rk(-8PwD|8d
zbkLITmLZi&R&E<U{THOm@PyLg-G%^4p58G`q_pE*gGCW0_MTx>4@B-84xls#DMCZR
zc365~aG^!SLqq#}FwtxHcp?1mGyGJE)+0mJ1Xy}(m`DlXeuL2$`cDjv6#jW?D7pko
z0|r+z_{?xwitGE_5JeS`FANW8ojz!|LqD;XhHd3wzA`Ld0+b=c$xqNSxfmNME8uDz
zq?n<b@goh$F5_MenC`|O5}@y8ETzDww{avTvV4qLYcL95qbvaC{fw8Uz(arIbQUDQ
z=t*-CXuL%snjquy0f6l`F3N)X9^=-<&<i#$pe*lRV>Z1M_nC~N0{|Lgyico+P-FZ`
zbcPuZP>I}r;}Tl+A224<hV!8DKnz;p#)N+$5@G!QV_eZlV?i<c4jEe)fJ7O`c*AbA
zQAt&BhmE!6KsjPOavBz5jBa0o#2WYX!BCv>S4vsO8%^o87)65d(Fo`#8~eUT=TYN6
zEnrfNzneoN)tKsvR+`bRA9Imz+<F4cOykc^FrQ_dF&r@2#tYRLOpZ}Vf=I4$>Ur4B
zH{Q1dId1&zBRErFY;T7`q0vl@R*`YW8ekS1YfV&KT4Ma1;_4@i@4Nu^N#kAm`Ij2s
zIE>a=<6oE1Dl^(t0qvZzk76_B#sP{VRTwXM1MR#qAsr%>#ywQZRAoG!g+W{}URnc%
zi^lzQ+T@aP+cPk0jQ-!k(aXlk8DL&94vhZ*qrYnOlYm=iETi*R^~UNQKx;7mOn1UH
zqb3NgM&k}TRM}+w>K91fFi!mf`pw4aVY?%c!zq6cKD8UarTlD%aZwGt=rk5Y1NxTn
zycFcNaa}8zUB-9lX6ZHt(&_0tMkjCByKDUREG#@T{;dS&OJjH@M23v-{0idcq!|fl
z52p_wLc!Z<a1C7YbJEhYI?(9~73f7f6`QVO5{^3MT!Hxvr-c-f%5jRPz)QZ<leu6P
zI$hiZOC?UXPGAtHoLG7ToOLSN4rZlO4K2x=oRZg}uiNR<`SACVQx%m^ym0!d5<czP
z+Dw~JudV&ra5QM^wF=lfu+^>{<nY#D3;N_s($;Bo;y80_A1&Ytw?<2VR=TxH3-je$
zH_w2`rL9-((Ym@-xd|dc+kVo*MEJI|2VpQ~oArEPXKwqR&Wjz}R@RMSmu&N13zYJ0
zy%Y$)v~4DBAsV-xrkL5yZ2?r=(X}l?OKbSvZIN4GVqn{@8BiSD_OTV5adVEN(sEzt
z=kyZ`aQ?g&g9&zCL8Zqb&Ph}r74H1N9Yc$C4xIzZMCVf~SW0ouxeLj3=Md7%a(?Lv
z$z10(^nf|$yx=wz@|-VI+CJYo67c|&tl0S-+Sr#k*W7_qC!KFln)Q@(p)WvBJMX3n
z<}=PdbmXtp*~txkXPtj@04a0+jjA2WoiEU?tit))L)fi!{+bpRRnDsxfqB7s)He83
z?Yxe5Y!{uk(l5Nmx%?Ttxa=&SfIia|=TV_();i~Igo|~~i>2V!JCDeQXoItY5_i{}
z_fZtK-8qxqU!Bet2muU};m;WcnI8NW7|&R^ca`}r4i42b@6nxhjq!B{U=#D(cqrXq
zcIqI~!nE;dwJ}@h&~Yb|VMpJz?P1LFFrcSQ54{CkSgSq|AGU1=V1ikzWJ*}$kLWiW
z&b)Rm1OFa9!U$7i94Ur5R#yz|*MFqF{LJ5JclKVx+vt7Ye+Iy3ZT|y*&yMpz?+5La
z$DA|rE6mhfw<SQEXBx|Z%wPQgtOal1h4P0lPC{s*_ZmPiI<A58N5j@Z`QzAD$b4ce
zqIdDc4rnczQh|SeIz&m1&no)BSt_Ts?dMNuh5SXwD7f{dAFceq8b%)k_}bw#WWG61
z0hnd`#shQtkZCnQSF}<k;Yx-gN#7c!;Cv@gHN>j@N1^cjcU^F6wF5m7*DR&r{94`{
zoF7)5fSDi19tQuXzmqXp>!0W$zv1^l^lqF>#X>(v(KGg!lN22O*Cic)doV4%=<s9)
zyP@G_VmP`dy_xb(aDABb#jxwkJfnA)AETa#;rKJ|gP4l|=J!;H>|ur-f?_N45!J{(
zV0`I&5f7OjdSE_hQmDT91#?|RmRR*<5Ks2)sj%S1?mvsU^k#$pf(0KoneI$q*0k{%
zVEovBC_?AY?w}7e1+X*gVK9PSOnI_MR+<Ttz(&(^D3R4s@kkPTPXSBG?BuV2c9gX_
z4xdt3YYuv;?2=4ir?LN0WFVbQ-3^fpwzv(@ne4!1sAsXBW6;WGHDS6VjFri5C!EM*
zH*7~=KAT9DbGec_imn`!oVZ7QlCc!J%$GDjgA>Oki+jK<knj`&ER<ByZmCGJlF~QD
z5`QW#Es^--VMHe+`mI1YDLH_WCfO-TH&s`kmSl_o${ERf%b-vy*=Je+dRAh)8-pm5
zl)ed>a}u+3V3$ksx1d!a37QVH^O6fx;!`PkV*yB&Bz7b~FG%*?fWc}>EA1sNN}Nx^
z(MytaT5r@y{#*`AmnEempm0Spo*s?068k6^x++<C5oYToR$o&huU=BP7NkL9Akk}*
zFiOTYO8n+Sqe*h!3!>L0YiQqnLvmv&Of*YcDTdG@8AC@kS|xg_`)iXF(#_W{X{8I&
zA$h|Z<fddsD^NNmiyy+nTapi((7G*IrG&jMNzQjvYt}8Xq+jbDNfM>r?@Cnk3cDw1
z`Wc}2B|aZPu}6|Xxy=WXA=)H9l+5@SlD!h|NtlE_i7VByJ(86F4(4OYM?vtnU&1_s
z-V=%C8|Zr~c`F5W2P95M0R2pIV-WV9OFlj;#Y6aoq;)hrb&={fU@)%IPpI-cL%QfC
z6f>p283CFleIAciwv?eac8>HxH(+w5pS1wym~`v_n0eCp4A{+=>giW{QF@eqnwO*#
zo1j-C?W}_2Woa{oy{=1(sodg*H2V@HO`XzrLP2jy*V;j&Tlxi6blj1?Aiuq2T@-Hc
zmQ9L-Pd+j;+Wh#-Cas0P0Wwn%n1QlU|H7FdnK}K^qVP3zC>)o4^$AFU?Bz|6LfLHk
z*%rw*R6`x9Dk}OY!Iy+#;e<(+cMSBTY={crPRWuR(K;i0dlFnMm7Vqk^Q<gA6_(2I
zKi@$AoUEi7edV%~k72h0pPPr>^D+$u=9|sN9szcXnHepfTFtts)n+!1%KqBTmeEV6
z!%XQ2a?|X?PAGJmnNr@N%VjqAIb3{V_DGJ-A+zlN0P14ySPXqvb9E!Ua5J~1y{(_Q
zu@htRH?P<WW`McVL^u;@ev{T`yUiUb?z_i)<1mn5^U-HP_L;xD36v1?OnMK8n#WO4
zD9rrdqiBVj=a{yDMwnZYOr&`$9a4%hucHc>9P=)E#^;)c8$gbkf839m$ul2SLKAGh
zk_s^k&GWCr-y(Cn58zs{IX@3>mzY2P4$hn~XB^NvXKqhxuyS)V`Z-jXkMjrEdGo*D
z2eZ<Ac@Mn=FPJCNHLNzz{v2ra=0gJfZZMCc1?)BRx{L6s(Y%3zq}R<$s22E!xdjz5
zHJkT;511D7sxV-;nLncKS-bhEbTDt4hfqawr};X1z}z;Uo(qL8^QRXfa>slbE$#1_
z+kZlfp!?>((t@MMyx9R>xLIue5$^A|Xdi&$0gLK-Fb`Uc34{4?iw`LX9$|6OnWoEP
zP7GiUS#(lvG|Ix|E+nHZCTxdDjKz|AcoAzcjLI$IEH+cnJ>FuFLJ5f$NjPRFOR}(i
zixLUR7G@97JZjNTx%w1~k}m+0Ymqw*UL3Rdj!p#RTfANZXO3I!KMBwRi|v%nEVPKf
z1chRY$@Jnav2aXA-wBILf5Nqs7SD!bo=#a5I)iz}Vo4*wN-bVc?(3|@3MYV-S$s-)
z+AzCB#>V9E0XS6_xl|c?!NQ&5y44nMY(}fwVk?~_xnptRe`QG)QM9?ZZ*h;p!#x&O
zl%0KG@dmxudM&t%(Cf3PsDa*N3mrYU`Yp~-c<7adl3qwd78Mk(bdi@@LDE%ja{?Z?
z$zx3vn%pJ7&H=_<9!kM&4|zO2X+7mXK0}|E+>8QY-tvW1-M3r5fGXhk$mR4C+$&$u
z4!wQyr>j6h<%7GR7bc&u7<%dQ8M|O9Lta8Dlq|W@9(~#JF{=QUBY)_FR<7LXDcyv}
z<VPmK;XL_Fx(xa9KU*-X$K~l25G{}=_d&l<?n1BnB6-IdkYf3PKDb{ZZ=ZnH3Ay)Q
zP(LXTlfmFA`Mb1&KP|5>rumoG&^EDDzJ&@I&dM9#19X}E+eq}ClXpi`b$q$}9*wX<
zUbhjV=jE@_O;{-(^*KnDd>+*RRLhfYK;)v_m&GJplE0n;v>Lhne3-v1|JDG>EAp{^
zVAjf4J3#WPd^=tDI{EHSkOukIRgk<UH_;BbQSSZ<UNp&nyQ9EOcwIh^4&C37J5my_
zS)NG8tXkw<6gqB|#}z=aO}?Ji{O$5F?qGJvtF7V1P5CEZgLKLbcVY0B{3sOw-j;t&
ztGzDy#a@i1Tkg36mi8#Vl0qa{(Ki_i2NnA-05e>ndk%Z12t_WPzKv9f6c3A149<aQ
zwBq$l=pRu;YygQ-=xw1GtB6&?(KtoHPB0S`TbBYRQSm0l*pd`GH-jWA2G#>KMe&`0
zzBI+zKLD1l_?^zg7AUIk!nH!hh{^D&SkX!MQ;A9OU^76=6bG6BdQss|%ce^Tj`rg<
ziiZD1gcP^b=)0mQ9}UG?MR5+$t}4VFOi7(Wa~{L4SDcN9-3G-HDxYju__cs^C_bXq
z-c7}=kI?E=G*d?Lmf|mZ3EWm3px|Yf!t`1b{O(rV^#%4_#aud4aZm9LEqLxLE>P^K
zM-fPG$p?yk6k2?!7}yJgy^25S6hfb(@<U)hQY6vwxyK6r0I>TN3VM$}Rb)~ob3mav
z2=!-*IkfhBu86Dz$_qu%dXPcI8zu^dyi}YBMDvxR^bfR#6n3=ocd-mo!8KRQ`IA80
zEQ4u}vCGnN6I$+;cZMM1VOc;WF`ky6(yGnNa#TFL_qF_zF07xWX(pKdmP=_d6KFX|
zKiD8kdt11++j1}(%srMbGH53pY&r80u=iR{_zJCkmRnq*A8DCLL4`w>D=45FWmymd
z5^dS+jJ_k52fNXVv6RxakF{Jx2SVB`rMKYyQ_GVR0p_CI_9G-+l^#c6&`p__Lf$Kr
zx*+1NTyhSMdMLMjX+9E*3+0Vo$oMKd*1=&v<yfkf_gBvIfoP!ekFa^E2v|Ib1T$1=
zqLWx*$}t~c*!z{&|AM~<l;h|*6|Ssb3ojy+{<JoaRPLjo+#%(7`oTvl(<zO0SUJub
zdPkI1AHbOy<u6097pL6*8Cvnm8LkjXP<}QSV2R4EsUTU(jr4TRR+gEl5H?5o;Ziu7
zt9*3|ipP}esWc@|=|Lqt`N~!OAO*@L^xG~}uB7B&iSivfwQy27lC~?Sl$o1gsYYo@
zW!jgO)dD21DC6iXU#)W91+=azlePh+PB~{TnDxq?^qgr`&S|FSa+}hI5~A(O{Qn@@
zp&YUWOsDbzeU__RIk_3+j?%Ral6RE}IWT`u*&Gg$2g)W|I6PGLO+#O=^1^GlFn!AK
zF&N7eW#-QyPnC8ykQ`77mtf(U^3U^d^trM<7lvLa7u(V|+6R@|$LM^iET{cLfK?aO
zkOo>s^gutzs`(|zZmYK!g1N`)ZU;!P)vD8Qf3KBK9n9~udY^s=Ayy+eV24_<lK>WG
z_53vS_FFBY`{IDr2Qr8pv}(-(3AcLpQ%FWw<+xJP@sL$RH$<bXrm`T>R>@S$a@eYj
zc5p|mo|Zy1#wxuOBaF3La2+JxYFQm7A;GGR;sc3R#a<X;lGQ~=FppZ5tiW`oSba*%
zo>Z&tCYVpN8ny@|-D*K4m>E`SRNS6vHFhEfVal><oejlotIhOHryMKeJ?I~^a!dvB
zw%$nT1|RDu-$B&Z`VpNk47Q#^9~(MoeQ7!k#(FPR1x8q34}fH(bsnwSqO7m@z|m;y
zL`q5>wpLw*g(KEF%0a|ff06+6vDR@sNUF(tHiaE?t+($4IcA-91R8nP59tY!Z+&4r
zU@EQWP}s7{`tCx&T(JIvmXKGizooZfo%M41C`r9_J(Y1ZSTCT^;x+57b`WW_zD<vf
zChLz6!Ncp;XC46ahV|>?VWHW24dtI&tW6#B;6|%;)E0=gSu1Jw+O4nu406+2O_8@w
z>y%Xxxn-Ss5-_)|w@A_Ivd)ZvLZ5YS9$+3>|ImiM$JWie;b^~g5`(@c*8eR<>#6l~
zszn*Fj-#L9GwX*GY<g~8o(sJf*7Hp>z#X(+ND+mX)_<Dd+bin{bkDh{wwOWDRkibX
zh`6b~q#e~RRXn{w+*KFp4eg=YFcX$MRX-Wg@=^tDfuy&}PX~1$)wJtS@Kr6`0H&X6
z4}G!6U-d^N%m=9MQT<_{>VOCR{(@8*1fFEORo*nEdsLZ}1`bvoJ_6=mmF7#dLR829
zw-Qo?{tb~Zm4T|b_N(mZ{dYj+Loxk>s=sIx6Rt|4&lyChT6q|ZRNd`@`9rGre}GTX
zs&QA*I;?t5hr5ob)_T)gIY!le4xO>8u+PyMrz)ET#dy_V9Y})ey)>9eQazwMI9WBv
z0U}3LuYZQwOHoBp?ju#THUYDirds|dnCU9XNAMy;wK)cunX2!@A(ExKLHpQjRsIAp
zb5vt);Z8WFy7q*M-ttuI=ww5_D#jK1$5jpwAXA_!nF8~Ls@_e|FH&u!r){z7S_Pab
zQ}sRu+Bwzq@1anxDyhaiRj3wF^8K>vx4jU#qH1Ww2y0a_bjIYW>f8x{)v0upg|1gc
zP}OFG>OMVJP1jT(lt80VwXXnZO{%R_L3Ca99qlA<sBY43pjq`7g^^lR_uPTjs%kg{
zg*H_@)!uZd_WlFrP1PI!!R=1fZ&G02Qd#>z;kN319wJ>TD|)$fs~kcgc}I1cp4oR*
z=jblEXHs=81loPoJ5;6Dqk4}HfIU!s=L3z0s(~AD=8@_TivK-UWmKWBUzJ-9g(s?t
z%OFoxRbCJoP%Wi3;xko100#P8H98Rrt~Nom2zIl%7y+Ml*))b=yzVxCP}!HK%`sYS
zc-ffxJJ9sD*)RzPeQZ9Xb%L)=ASI6dY>v^(+~3A)0+<0d$$z31Xmjm2>;~D?d%)6e
zo6l1~_Sj7R3YHRWJva;^*>=1YFjH)usaz$^Hf{u*$*^tS2@6@atIt3o$95jo7#*|y
zaqbjYDzIIlgJ_*?Y6<k)ZPzSBXNT>RqiEf<o&FPAowmK-LI0L*`<u|eZ97PBmtNbI
zyTi<KnUN+PZ7*NgMz_J#pzRonDZI4(Fbm9AwwIRzd&qWdCNx~sAJ9GPs(wbGZtAC0
z7O_jc`70>+tHTb$V1W9I*+2<bw@?8^gxcu<hIU9jh4R)>>byG;iB`YA0IkF7!xJDG
zqaJVifJUnRz5yEP>bwNlJ+3aKTI>S#zjW-VP_3U1k+bT7Z$Qe_tM}0ztPbshe!2S9
zR_Ilz=gb2+ul7%aUZr|tA@r)$pL&9ML2dmz>{hEUtOdEKe)Bn)m(*5gF{B#xsW~Rl
zCbb_`n_pKir!dP6b?sJ+uvzWt4UHDH>prwv)l;s)e4D!EFOYWi6Elzw_1$OCyQy|$
z(dtxN-bd?}`ZZ5@cw7D40qR}q7g8|0)r*E;=#IMe1|;vQy%wW&Pdzw;PBh(DPnd%_
z=}{m24EM(ab+{Ue57qwrq1dawL%F;@wKbgvc%)uTC-fexpVCK!`_=PT(*3NyLTB5a
zswZ88$bj0l7Jbju#n&MDT<uSx#24ysPr<^V+SeA$m+CGm19suIAarh$xpHTQ0mhAU
zr1k4APBspr?%X%EkO|>-UIun3xA_ZT@8=HA1lj?P`w^2L!G-EDmyw*D-in7fJ-un8
zxc7I#`)Dq>4z0u7QL2MD!o5hMtIfSD!h9@uh$=neII9maPo{Y8m+{a~;6@*U-9)aJ
zLhni3g0CTy%q8DI>nOK@A_Xa2_Xs$X%7uBsL>d<u2ovetqXI}~a9hlQoyn;bK*{1d
zIe4GVH94V`!|7dtlFL~v!2pkOducD5$2HPYG2g_+<w5i~cWpel1>CM2v<kVvS!fk;
zH*;X3m>WF@`X$^x7igT|2HOC7lKW^a`c84f>8*I0yBvu@oZ%MI+NqRVLNBSaTn`0u
z%D5~F;+^A$C|+I8v9wC6;KooS<veGyeuXhraybXltm4+tO6md^(*})dZs!$fT;xLh
zA##cPg<fDa+($elFLUE&LF5Y8L_gSC?rb~EU*(+1ZXK5<f?3Z+T0o?Md+HALYh1K5
zNF!H~g|Reovkqc_*SXPQ!;dp&rkEp;Y~~K<g0yf`Dlx!TE|qpEZCv08V77BNSE1Fx
zRna|ulN+RGZYSqJ(U4o*z$dVGn|n^nvM#RmDipf8t-Y{!hdXu*B6qpP6b`z_O-+ZN
z_qll5$oFs)YA~V)oU`c$oO#HNdLN{h%cM)t$5m4H?Gd+HgVtkia4}5ubLRA&r6-({
zuIp278d)0PR@A`KGw$dfkmuYbdYirAQhtTxAg5gp^_QI0SxCO(&L73#hq(XZpzgvC
zdk@5wZ~UCrE^hn~m3HmottjQ-&KJ;m9}j-mML6uqfA4{o7jHx58{WKIJwSc<qc!l!
zmmg1Se?NXHok8&Dm$t!D06&_N_JMpS6|e{KX7kavo0naMp*{TA42T5t?N0D;FYl?O
zrTjkra3h)_{6#wF7s^M_Dd8}F36-7f=cfmQ9N?D+V7?CWdBM;R=ijINPz3*y^0<+_
z4L!0C@ihk^62-SJhoxwK!ZnQLFh8G8${gW?{)IC!{0llu5X*0jfJhwAq9)NKi|5a+
zgkl1pK!t6I{Cm+rOX8nX<}R84dJZfd<?ATlox%^$%%<`V!{J35Kl^Qfrt>Ra!bAq&
zN74FB{$d|QviKd>(3j1Z&czkU;Y(a#FqdCPFPvk%tsWwId^H_0Gv)Ihj-bc+KC0p<
z;C*R^3i(-w;As(mmv+R(JWsFf68?`3ASZa$Zy+am*-ub7#ecF9lBfB$8SwWE|KSg?
zRLb9G;L}-t*#KH)yn`nc&hcJU09(%g<p@&2pQYg6c@tl;7_^eNkHcJ6@qU@mxWJD{
z0cbVv?g^NS{PPTq;u0@rqE*9p+G7-#`H<xRy~0nMgu&GEeJ^4DD!-9RG3)rMZ6Njh
z@8<y4z+a$e&^12oEDSaB$<xr+#NT3pd7U?Xb03y&@XCCUW`0ZnxGnq>3TU?SewNT^
z<KO)ht#-a-1z<Y(5#i9k$){61p_4yI3;SEVBZV+;^OwWnS{LtHioS0C_bJf3!>7<$
zfV=#HR)F2(t7)5kpRc47Cq2A{sSWxM_=Oa;f5`v71Gio;zhe!C*2iBc0q7%sJgpBN
z^V3rS)6bux(vT;-w-fw*$~$YJFu*&}mgyNkneMCSd>K6xUhtlCAUVkY{4<y@`JmTe
z@D+a|5M+oK^P%S=h}QHHb``EGVbD$ZtOVR$!e6EE+g-R|2~iKBKL{e8!oXqlc?pwf
zq3kU%cYy69RM2hhD|}3OKtExt97FRLPEgDsK<J?=s6gRQHOvPIyQs!txA4pX>U)Iw
zDqsc+9uuj4X|Hf17c%>Ve2QFz2rFswLxn@Mg$NTe20``<__QB>hQj<NC>|7iDj*py
zWYfkvLh#v(zDQyG-;hidp3!lkG~v=0u#_%D%z{XU5J17-OyM*IYO;j?=r@urxMD|b
zlH~|eS_kF|_vmGKOb{uilPCC<VKDi^gPm~gxNt84b_;|hR5ns5_?!o5kszl`O|g*o
z1PUcWH64mRAq?q3P73Qipm0if-2s@V1skeEKO+naN2^rGszd9n@S*`=rZT~Tmd)n`
z8_KMg3;Fc0uMoVcxc9uUc^phs3Q>bVs}dZ(f#L<B^#{OI3lr%Fa8VfH1xGIlv*=}3
zBRH>zYnO!sv1nZpey8HgTH)?Luyj>${SaVv!h{k)*9%d!QEV^?E53)uHKBr5nvKHs
zBygJq4Mh;H3%yE+-Vk=s@up_sZ*xet2*atWwpDn;52Q^H!eF9ZD5Be=Lr|`VYd3{r
zBfvU^n)e`bOPIC}t=mG%6^yJ)2>%XX-9i?9A>oc-+FJ+iU18236z>Ufb})Efh@+B+
z9>I%F<~<Pj5{Nt$x?abadWDS#!R!;vDIWevxV0O09}9Ei(CQbC6rlA)a9;zFr-B`o
z><tK;-+}pOg2WC6p9_{|n1mO?sD)q-3QeYQka;P*MGO2_!b}PY4+*pP!5J5E&kq=y
zt2p)qT5e($Eh=}3r(9skUCg9Kp@-<5gqElHbTzQOL?dnQy~XeDz=V(ZeFYSJ#VInV
z`-y)Q0NP)?Ga7~h#Mspk2^0^XH-Q@@o}et>Zt;^0pzRUMU!WB%`p|{hD?Xu|#y&A|
z2+R<%BLqH$ik7rX2@@^!XzdsKDNcJp{A?z$4~py(j6Pg!G=ql`VpJ<6BSm>W3?34{
z{RbjZ;{0zQ5-pBvqlo`u@h$qW+7VG50*7P7<38{rR@_8;tvK=Vc$kP6k)p>tN-X~u
zeTgE!5&B8u+L5rEEUxqiIVzqifMklehkh!l;?hunrHKbcw9>^7+F>C>9QYRMnWCKD
zN?GFlPyhElMsdY($mEC>^n1t^OWy*_F)@$sxjZrK9GLlHXe|_viyML=Ss?ajU`&PL
zH%l;>BGHzf>&4<pn)MPfIu{Bj#4g&>o)i-()NxAOOogbY#SQoXmh6nU^AK94V!alU
zrn920HMnKs!&v}5C$8Czp_Pl#gk2#nO9sq&aV@1iD#i7;&{rkq(F^E;sG{U`wb)0s
zH5bL9%aFVzK7ES58u6<^v@VN2@51~QG3E=9T5;izuy9rEq~&9s7(o%KdXxB@65ce3
ziF9SIi4(mrQH^5uEBMqTc29-qb@88V(7z#0q?v6NrF0smMciWny;kx1>+q>f+;ayC
z?P4h%T<H)`PJ-l3@l^**bc)Al7kEqDwjUz5#YqXU&?WlNQ@UF;jr9Y)Bg!9vdslp&
zjy&HJ|E8V9ebKKH=6l34S`s`E*Y~6KP!tHJS5(sTwND&IYmi6cH?)U-EI#`TDE;Ek
zhavJrbjpU?PsR9Vv<AdAo@hN2<EX~{xj1qK^j?Uyrq=;8h=D@pr8s#SWL}ADX_qo2
zKK>RmE*gUcJapCkM`?LC%@2-f?b7u0qR(Bkei3}yrzxlHYKZ0#)eVPgs@_9inC1|&
znzH?xjf>HDK$A5H60X@B3WW%bcPd08HK`L!;2zS<9}DwQn%P%jH(K+K6IzEg!NZ|{
zMB{e{pfQ@;|HAKB%_ahk)BIrry?D)3ilQcH7Ec99)C`XRNz%MQ$1syM=V@VbRC7y%
z%ao$oLD9KXjr<+-rD+0of|;QyTu1funVOFbP|VWYxDC*3jXB+3Ihr@0f#hm7Q%v@l
zrs4s7%G3Pgi0R7LSd4(=am`c;u@q=B=!0E_nhUgZDbn1319powzy6875>4{E=sTfl
zrE0O0n$wgGIHhsB2a(enTu8kC&S;{-V4_r0CBnp6O#s!=mTBgXfcbNp&8@Iht_h{*
zRE5TY;;rX3_EbYssaZA~q)PMgPJmv}yzvRlS8EPa^!1{~pLV8~G%F5()M%XI!Mv=Q
zL^Y>ZG)JyOvR2a*2V%Oa8L<m?>ol`FVWM6$?K6lrXj~|aa!s>__T`P5?GHhkG=Y@q
zyRM0v3!iRinmjOx%^DR&^;<OMbcCW+vp5@|Z5rit_|&e+UIfyiSw0hBH#JEfaHdl;
zm$qTJEVrO=+oTE02e(V}{A<W`Yg~^5?T$tiVCk+#x*W`VnzbK;+}Bv#09ub`3T*}-
zXa;%cKh!wegY;?!XqVHc$v*(s9%;_gSH&M|mib_U`Za6{z@BI%pF;Afrg#KA9MJqn
zX91pROh;(R_*}DP2S8tFtVcm+P-8m*XfHK6+aUT%^Wr)5hcr305OL8yj)#Y?+NQVA
za?@_4Md>bWE{~SGHj;`9J+yoyFg>-?r@$F6?I_A<dTZN;f$5{&;0sJ&Z6;y*X*ZZC
z*X6Ih*aB{V_FKwj25Q~uWges*MWq?LwfCzbvPYXjahqVR5AEvqY6EJ~w@-UB1=t~4
zV<*gqYHyN<VcPXgAp5l=--qM@?cr%qKdAjPA9EP4?HGdrMrhZ+4HBuHFp5$QhqPbP
z9T=qzc?6AUZ9V;f4r?b;7XFC#(;_IwXy30uD^}}DNuN0F`p?jc*Tzx}R)RK+4)P~z
zAK^T*EJ<7Y8$^<|waEZGs(qJI)hXK7XfK<p{hro{Y1-B&5J}h0oI*jM4DGPZkjd0~
zY2ZbcR&g6>+1lTJg54agj-GnC+I_2`e@y#<EkyFP%KyO3*Uq5Q{^QyS6jdzHE~KDl
zp|+z2dPQ181Dq+=ezOAxOSGe@BI|^9MlP5qwX0~>PHBCkDF}30`*#A+&T0?k!ETv$
z`eKNdYjftoV1;&w!o}ycrKh1-sqH-nzpJ#N6VZ1;TST{IwKj}aeiyaZ|AWXS?MGBe
zTBCKQd;PL@oCM4(+EIQWwc4!|BDt!a_$mCY)0R+(#8j`%SPhs4ZOkCJ*R(-Jxb}@&
z$GsR#lXfA+d2eVJECaJy`>z>9TC_SD47O^Ye+km2)t&%$yY}Azpmb=bRAUe~wP&f4
zyHoqyJ5ac#%?W}tx3xZ0Q`Du6Z-QjEwue$jcTC!vcc6b)+xRz{_q2udJ@5Nk@1G#r
zqy3CtgAcT;tswGH`>+PgK5ahbgCA*^(E{+X_S_4Qer+n<Y)`Z{I#_zD{jCoE4rs%v
zK;W5n8*NXXYhU+6>xI@K8s-PJuj<iysWnYl2E|v}l2&ksv`#Wua?#CN0vK1_W?H|x
z>3;48*`<qIk3M(Z`pdxf&`mpui{`15Q{BFoZs0UTymd=yzv`pA{5}l&>TLFc>8ER_
z5C8k?#!}8UKqsT@eW0$Z4t+toCI74a-mUXI1I0bMO^?70)~RWou~)ZlI$YeRyLk^J
zM7N95c%izp7BC;C`<()6`*k%HXdTeK;|-C6x=^YM3)i*uLOnv~K{s2ZZvH}C$wRv3
zlt+uwNoYq9t-C`z#lyO(pHSK15gj)h=3{i3OVEndt)WW6INh6P;7q&@0cHHgbg@)o
zpQzhJpDa$&dCf#CS=Ukna#Z&kZN5`<NxLw#R9%h|Bu%&29DV7!<#Y#T=tNqzXX=*6
zfn@25C_|X7i~o?;pE<hJ>1gKaau#7Q$8;Z4upv)ZdlV#Jmq-U|kLyOd!<hnIc_c<y
zs9Sd&*hRXwL|_-|u8)LXiLOD!2v6vYu3(<j$!QILO80R&pik@GjK$=g(T(<mWU1~?
zcaXEX!^i0TSEj2^hT=J$8Lb@4btOR<eTA+g33kux!b0FhrS82`FkhuJeS_8o-6l7P
zRO@W>VCkaHp0-SvbUTMbp++Z<hHIB~?7y&kMdz6Se`|GrDq!%cZqz2I*Xf$+d|th7
z!x!i?HRxXUK>wPq2L;x$MxFB&$TaB=Er5yZx_NX?=!UM$79KY1j!~esMR#T_BwKX~
zy0C4!j%ko=*Ij%JW{2)2EeUSw_Pz%5ow~9&F$ujor(*cjr<<4vg-5#elmdFJ`}$9i
zev_`59;HuoWuJgN)g7f3=YTHp4D_GrR?(sC=emt|(f304J=Jaw>K0KE&P&~V+LgW1
z^&|o&)oz*<B-89}Q$1UTUGCc$M3$Y*3VqpjMYQeBu{(Vl%v`(hU@(u_RnWdK-_BG^
zE3pE*JPP3z+Er|YOtD=*<$y};7)oNEu(P(ID{5CmFPT$zv;P6wX}ggUw9eS&QPQZ?
zZZ?%LowbwAf%-YS=?Qct?YfV_nF_njDu`6tZJ7hTD!WiR-EqM#U<{bmcI752jJRmW
zPz3#woq|FpHFmp8(0SR;c{E_I*p+_{^R;$?lvBKFx1tKIIy==UxLt4OMCp<SyZU%A
zui3pxJGMr<+A^4Evdg83y>7S7fI-}_Yx)P0&31jXPH(Y$@jaNWcI)-@{_C`>+zU^;
z>?YHCz1z;jL-dZF`6-ycYj<lMVD8!FO$E7cS3>Wx9=j=_P<UY1vI>&DcA>8Wt<P>O
z#daRq{WuTgv7KoM%znE+jzQ#!ohu!0dTRG0eX?!9?l_$Xd1iO>5q-blxm|iLym(>P
zwhuCcb`vXM;-%dVs)2ZACr~_N$WAp6FfRICRDR~F5C0d_<))uTCu4W%tEn=<T|a}~
zq8|DU{SfiguigSoFa6E===0Y9Nl7^${UIF&;j5o?6&C#TxAs#i)nBis1X_Up$TE;X
z{We+<1?g=YptxIqgO20{>ocg_aj)KMC1CdHXHupiME}VKm<ZLc>Vz|4`i%h)*{>f#
zp^^joN!MWMp#JPeV211CzXw=^{+pkm7pYI7(BC2bFH^xZMd@RYLL*xLkj8Xa&(Pg+
zME_F@uw(UB$(XM={mj*vi+KGCI&ztyPx%&8lBoBiaAdN60aXa3=ugw98B+C1O7o=a
zvwi}}(2v>%kxc!qBG}E+&rJeYw*Fn(is$I(Ho(F$lYTmdkMi^zHls6Nzg&&Z<NBfi
zcu}Aieg$Zue#ahoSfp>Hpn0*rfUZc1e)3z;KcPR<1m;Qor}hvzrC&+u=+pWcUjgil
z{>unRmg=8JgLziJeFO$krjMoj;+)<<H8JIS(|B4fRp@Id@KULFmqDXS|9S{CF6hUa
z!L@4rbSk#Ks86Nf^(FmC9+Oa`H){s-xxO?7XkPXO)j;vF-$yY{U;BmL=nJz?r`^Iq
z`+q4cA89{t6UGv4Upp4+G4`(WAem@C$wbqZWZyw$w8{4KX?t_jzLH)YDfU<CnV)L^
z?qYb6X0N69Zo2*Qbu_c~8&3iz(_T%h*)01%>704CeIreGj{PnwAIr6`eixW|_Tk?^
zB;S6*hhUzz@45?nXY6Baz`SVx#FgHEm+VJ$LbS%->L=K}Y(MW4$Xu~sLWgl`?f?D~
zL%V7}fdajC_9^skthb+@4*dpu<Im8$X776%&NSNB-bAa(e$QXPyl!tc845S-f4v8k
zX8R3sV7AyB$3m~w-sw|}rOjSZNM-l!_P1!keA9lX2<%S#t|FlAa!9xjrn`d`Edo3o
z2DU)a(;;vNKqDMxe+AG;haV`VbI8Gq*78vfODUHa?Qm!|T8AB0|1Zny5J~&wSchbK
zkHkAj%Yl;aU`8iAG90QN)A`Lzhac4F%yMvYhkmxhVv0xPIOyqML9RpSH}LeBgEgh$
zPdJ!S!v3VgeP8sQa#%1Lq|#y9DWFw3JX!{F!C{E9kJS!m`+;)FVKQahE;}rxt>qPm
z<#bk}*}?SyJZy1Lmjct&>hL-x5ZW9Tt%s!!hi6pAe$!zEeNN}GgDq7wJaO1SM?If9
z>}bZ63^>RrocYXQAw8a7IAqejKIm|d!V51Q_H$^xaxnb|br;73dZ4;GF1P?mH^&iQ
zz>8gu`{-l&?vC6B5D$}MY&%Bp={RjY9QJm6_`ljE$D`NK>Fe0<g2DJXZWs^0{T(w}
z02APN;%it6bbPV^tsuwmX<4_&QAfYAV8^H;^zC*0_b=Gp=eYY7S|N`27=VR3-kA)^
zFvoio?b`2ne-khdI-05|LLBZmV;M9e9hb(T^N^#{EGWi125&`Qg5yFe_Dyo!KsQ9P
z<EGIdDUO3w)RN|CNju|o$22O?&v0Byi-%0dts7x5%W>jxn8<eYq^CfR<L6YSm+SZ+
zRr?)tTu=y-=NM_)0JMC^gTG-Cjyuk?1-H=gr4|~cj;H8peb#X=rAx~k7mR}Y=NunX
za=P5{mufI89CK)ub>6YZ49qIW2djZ{!Es6)`l=njEkj?O<0=X+);rpT0lLL8fl4-7
z9mO#iZkwa^$0qpQ?r3`(o_09C_C5^WbR0*gIyxN-sXX|WV}=nhw;dzXV7|+7hYtGP
zjw8MT^N!<#*&ufvr?f-zo@49|c(HqU+angH@aJ{U9k4R)DgBPezo0nvE{3C=u{-lL
z13V9APb2;QJ(*2ZHtWUYxuE6E#2$dM4^u_&9ABn_E`lF(VwrT9SvYfwmiD>K*aUcb
zjCn{gfIQ~P68M(SM9@uhoJl!^Rsl1Ms<R3ik6jQcV*a=YQp`k~L9c|VSqq0xFvY*n
z{_`Yrl@czem=Sb#|1{&a8?7_UYn1XUWqc{&U&&OjA2!VFHnWGG*6!@WTrfS@DPv&J
zleK*TrWbqF6AIq!_9C==*vyrfC|~wtdOi5DyIjEZXHU+9LIC^AF-Qior`FQ`Gl-Q5
z7}IX{O)4VV!v-9I7r|`*aK$jQDE2?3LCk7dckI5+JSAJHWW-Oh9g!xpJ(8kNfgLJ2
z|2q5)mt58;0FFO1rIq;meV2#8nY}XvG9SE8i|M&`#o#RSp9<rvZ0^CmpO2PO{@3Xe
z-Gt806w3Ezx~X{Ik9mg<Tjen!v{X3F{50nOUsL{{*U|k-^4bI#9g=w2z#$i@ODv5*
zx>o@79_ejYv<{mG&|#S)=B|{kh%xW{2Y9jO{p+CKs?s+?<hJVYL$cqaS~?G%{i@-Y
zAUdex7NE7u#$f{7^|jeW=lu5Ayhmr&_S?j5MJvii|0^WpZC<PZOoEN%4S11g^O*A1
zNj8xb4o|kp3r6dxP0}wIdWy|F3Sg(&WO_k8&E~!zNV?5|Fna#y*j)M*qJ=hzejul9
zwtoh+3L6g!3SP3wTL%4WHVOuPjW(UxfN8S%;v!ntZN`s-`5QLle*)>T$xa3Hfz8Ak
zv>w`=r4VDUjd?IyeKyzAVDOQRn<t<j+oaCKMd`QsdNeyMZ2dLH)->xd_|I)N{0;sK
zn-TpG9<<@V#5i8sOkWP5S2lAV0DZ_N_6^{<*v_Q2ysPaBs$+Juwb+f8mu>I+K=HQy
z-3=`t+Zqoz?rSR<1d5++1bwh;k8SvUkYHOSJ^c3CHeSIM+Go4Xlm)vXwpA@ai?zL#
z1(-zJ*XW&|Y&*La8kx3(ET%ul_Tw#ZrqK51`;feDyWw5*-LUN?&=%YLXpmOhA2)(@
z*k0KNg`2jo#=z1u+sD1QU0l>z0u1`Ax6+C}K&@{DIiSuQNgq*(R*zW#zZ2A7D#1-t
zkE9ctxoQjgc72ihljZQ~jJkrddgs+q=9r5b_1Ni<Y*2r&50WkF-4tZJr7q8g$bB`p
z0d^m&{|<yRFVw%p(mZj2^uzGsN^~&f%e_kx6F)A}k8T2gZW@Je1GtGf&<Nxn&}sP~
zZq!Ct+Rfdk|K4d2_hl+Xg1J+-;mlr6KLc*><F>V<FNAxK@-(4b+EVxw#;vb~-hOTb
zRT;)|IXn!;apTIN5YHvl(Kxx+?qVtvxz&g#m{9fe_HDo<bKP`4{wUXG2hkMHEEOb`
zyG6^DH17CFXryz8DFB(lB~UOalN(Lj?JRC5ov_H}(qF=0E|+u=lE=7>H=&ou&GpBy
z^SNWRxjN20_XR27*3iqekb6QYdQ%Z+qJb83!5;ypgquR)kQ3b2-(l$__w7W8p5jWw
zVd*sYcP*G_xZPBdTgp8R!<1a&YU44cdhU06oHuh?A1HKk=SIQ9dt5#hP(9)n)2YH2
z+}h6pJ;<GGfaFVVz8~~nnYe$>qH~C|raiF>zl2s`{(Pn-WCHm46o?4q6|*4{#LvzE
z=x+WqDjVO!D;hCDd-*s2fKU7QpXexD2tS9at3vsxA3(x*JOFVi_{VJ^hxu|U3_8M(
zKa5rkU(Wy~mN%Kx3nY&3Z3Rp`KQRVgB=A9x&`RW;hrwVnZ%jn%C|{iljTF9yz5$=g
zFHMH|G=7N6h0^(sI{?k#hyMkV$(Nl6W&yvD!*~n%&GZB=;af)o`UJm|$a#MK3ZPW-
z4W<T&Uf>;OL9v>*nu1n6|6~|I8~F9~QRPN{bqe&G_*(j<-sES!24_0?Qd-E};yrGH
z+~&9ULZpk|5ek31`Kk2tzr&BA(&4*&AB7(7@!|BMzR#D@LB1ZoK><S#_=tJ534X|X
zB%#^MPrQfe?&Cjn1<WJ9g5uNte9vlVJmFXBa1EaFfeX<Z;D@gQdB*qBbNV^|$rCvG
zg3r7HOM|?GDidDv^Q-9k^4V#yFvP29P3$6cd=EWW;cOB_+=LCK^b+1By!8r-?!x+W
z=nN1(7z0az!bB-Ff`s=*!i(L)?Cn4c782IeMHlWq1#_QZLw8w-@ZJu1aYR^2F|Zh+
zmqcQPedp1N6R!0@GG15{3CslHi#cc|3Zv+PCJC!s=<I8<5S$73j|#u+L1&6EED0o4
z__-0zqzQj^!L@Xufs*SP!aY2;QOmF;8Y0<31^st8If8i?TDig_dbu7G9z~&*Cz$>h
zrWQURz2kyN@52HioT8b9!t1q|?IK~&5lmCDFgX$Kmk6&@S;+~Zny%<cVdGM`cuM%|
zZ7@#@D@H@(qOdpu<}V5L&gi==xMxA{im>htFzbXf^nrnTA&92(z7Uv*>FN=VP6Bx$
zjPpX@prE9hjhDh-bV%lv5W5`AA(QY1g~VLM@pkakRZRE}?z@RQx?p#gIF??k?&20V
z81xYTrRboiICTa3yu`LQf#xk5-U5t|7)PIo^%d{Lpye+<rO68rXQ{vp6u(*vy&%#0
z3qbD{tEZrEkN8m)po2xz;udu76@ONNyHA|wf-!}N9<)#o6%U4^6(%}+19ZRmE^YM=
zh;Lvuh*Wzx-MQgnStz_mR-9H&Nn+7rFq6fR>(DwXPIJc<Nf95=t2I?LOon>8ICKhj
zGsItCVn~@{jL8-HS>onec#$pk?uVruaUN}?qTibMEk>C2R>FU9Ci^Xy%YgBoxN|j3
zG)yY8fr++BbI$|j<y1F{U%r}Zo(5*{v~=3f;46RhxH>Rx9ldhGrv+yLEN5C%H_Vq#
z^Bn<^v(p}bZh}nJv~c>R-<~#_s)rKajjgkUtN61ihce=uTe^Y%+mk8y`}dFO0NfvS
zJ^0&6Q3vI%mqUTSP0|Qe7p9-$1+I*gw!?0W71h-HGTCO3_G7$j;6VTrN-NM1CTkIx
zp^Pc{7mW1~V@Xf(C}!*sjhykO`lCd~oC1AG%y(@d$&5&Wm7`3~41i`c$%8ai%xStc
zikK%qL!_8V9S>5%ti6soI>B6~m|O+ZG#Mi2nT0LDtYo@6pjXAbRffJgW}E3Ppw%<;
zDO}mWoTnGmHD-4Jm~G5SO6RmQ<&>7}V5%#jf0G${7bEOsx&r`ui`hQ`Zr^5>-$h>+
z^A`)yZsvLh`g)m118DUzW9g^=h)JN>*kfi{0o41MF*h->FB#wYVeRes&vu+?RpH8p
z)Pn2A9-_s`F1DUZ4BgoZQuJUs+ERJ4`fmX0#R{<y@n$_&1I>r+q|!BCb}l_d{n$;P
zLeifVsMa)qUD^u|16l2KkRWzRILL0+gC22v*mcv;3T6XLv`E;?p0@+qKK3grMGj$y
zTR|q29ZSUmVQdOjJMU+$zK4ke?ESfL^dS3ystLo{d13G=f_?lMW-XHKr6AKGHef3B
z;#nkk@!(@a%D_x#Yp5DFgFTlCg-o`103uoJ;dpv=7qHWMz%7KsbVb>w#lS9Rzxy2;
zC2S`}@5|U7zo73NYZ(m5a<*awS`}=}R;Zt6zouYMB^&u46sp*(IlyjWyZfMboxMTp
zts89l57297=YIjcHuiWA^lq|O7E&czC;R>$=-*;h?_d<S*#+Oy6=m<d2lu;KFFFBu
zhjq6>-(B_{%I~>ILU%&JOY#XF;|i2W#=>BTWctToMo7w}Fc>58*#HwqCD~M>n<80$
z6eLwL_y)X4ll)4hh3S%`JLrFA%aFYB6x<@oh<2DLmXtEMA|;ZNH!zqJl1k+8@ezv@
zJ^D^bDnyt+BbiE1|58Z|#Ujp1_MQMKllW2!@SJ4I-@q=HEN+K-t>npNc+n(bUI$9M
zq#*=--I5QSz<elCRY1Y?RPwq7uwO|$)<VNmdT1Y}%}e?w1E#n1gC%JBNS!ajgs*fZ
z?Z*A2BPl}QFP*g%t^LyDuP{Leq$B9G!9nR2`Wi#HwCzWb2<aip8%0Wg`WhmKqzgC0
z`)Fwfy;cuP<LZHO#3a2+rO+|b5UT8tl}1wKU7U2gfGLfa{`Vggv!qivIDA}siRy7q
zN=JMQpUz2##X`SYdYx|BtI|1ilV6wqsDMI;^alp&cctTOAaYMCX@SChY5N1TdZho*
z*6M-u6C(!rP-?nMU(4#1wr&MXpVYV#`mdzXOX0<kl%sX6i|qF(xaKPJrRr2S+4XI}
z-X$BB3I%tW@EbrqWOgYSy_aml-{|v}4bdyiM>g^(z<gys<3RjmZd4rPFY9qZUx2K)
z02Tse@g_PV9VYwUA2R!8Gw9gN0om+$z#NnvAcw<cWB1Zr%4{jf8!4Mi>z62*6V*~i
z%jRtY%wgF~Z;bGWtbyVaF|u!Vz?oRtE6O>>$!5_eFim!q4lAU~LMVKeA=7?{zD(H!
zD-+PNWHmM**|HTXn8=Yu=Kv;GmKO(y^JMxNn1p=UPqceHE=!}NQi1FfTGtlJ;y=U8
z6v=J`0<Bo~!#XfaWDAWzIVTHdV5wZzM#be7vSF<dIWIdwbw`!>Kg2<*WIsAnCCmkx
z!*$41%N%~eHM}S@&4PZ7Y{N~oF3ZZt!Ne6=4ON8I%7i|cxGGz62CX`o{v_P4m)-vq
z{x--~Qg-DUzFZINTQW`$a$A-@9bjFu;k2smmem$wEO%s`lqSC`TV^f6@9)0sZPM?N
zh3tpu16jgR$UKz!#(>!?>$wWiKG`GssKb!#nFp9IW)g~ox|)4c4%ghwmV^L%m)VN#
z=yNv{-iNw}*~l<>=w;SB29n-pho1u4$86_EX!)A0zXm-&GsP5On*7bq8PE(cn<Ih7
zL9<zwfC)Eqp|wJUnJ29wBhAw2XL!gggHGv2nO&y%bF|r2Dv>{IrVNIMF=m&}06W%f
zoH<%?W&-Vl<IUErgxv%)^LUU%v-c5_lqH#kg+MRa%;O|PPMgeP=mh;4v)q56SY_sN
z2JSbTg*^hZ#cVCDKVF)xzY4pF=0jBWSZe;;Z?JUM{LLURubWp>h@-`P>|UtfF=wdI
zvDbV|0rUpU3#kD1nRySbkbEp2Qnb<6;x)>4@3WYa4f9bJrg0Q~%e46FDGU}_tfY#E
zQi}pRFt1xgHo((f3-1_!ddW4EiQgwLpe4Z(xj_XlGUOAB;YF_eT}Oyi$d}Qg^Su0v
znb7l7gbQE>D)w$iD@YMSRjs=f7hHf6tQdG3{_a&gF%_dTL{UJuUZ`TtGx&W_QIDTD
zJ`OPRHONFLwmyW&A%*`zT&5^Rpgj!6DE^>FX{;jhHR#1DX3#<?QQ@kD`cZ{^Gy2jL
zZdqt$D&E=yf3p?IE78hPv{P}<F~zEASjbcS@sxrP`HE}`V;@)a(h{^%apyIV3kuCu
zOu{9_V|s{PQ8X98#8t&|T4vTOYAJ$sO~HN+wCjpFbzrtBR`f%}&GPXa`0H+&brCI3
z%dQQu>utGc3#L2JGQk;=yDiI(f$X#FdxuU!gj!0TVNMQMI?`dV2+Q69S^(mYpmoOI
z%g#`CXt`tsJYKP%&L6Mznu&jZ`yB<DzB?iV)T&|c;@{urq=3Kr@<}+gX67w;v3ApX
znEj#H9DlDXq<rO%i(kXvKe<rp>-y$=djD?7qs{8i=P40rEc+Lub=p52|K2)wKcKh$
z8Hj&7H&LD04oM~q{8uy$|K9mh4j|JSnon28Z5SGEOebCHT}<FeC<ZX)bZR7!`IH|2
zL5wR^NA6}WM1mY(Y-d2^Aaly}EzrZ6X9%>)(wVfKa4U~-q?r2&Mt&ZHI>&6Lb?-&S
zaFDk2G%ef5;qNFGUuDA2kZnB!z{6}G#o~{!j*&1H!(MHMqls+65-^k4ReiuqW9Qv~
z&2;wSDYP=!=~O(KYho8$pm~f<`~)PA_4EVDXB((4w3rQ|1WXBgkj|o>VAp!$`joQE
z|A6_kYz388m9dvDL$Z>c<paA_?Dw`%s9|T)?QxmiUk=Z&u<3LM*0L`|h+JbIEJCZ1
z4W%#2G_iA2sQ9v#U2KMC8@rfR9qsI_3DECgJ^r`uW!F`}Za2G?;+=QcQ=u641J<b&
z%*X7Nu;}~vG(qQhSaOkQjp%zMKeQJU*RSY9rs;n(_KLBhhw2a$M)TpqzDcJRU0E+*
zxbDUto&eol?8k+GcV|CJ1@T~a@aXeoW2nB*i!GxKsyCZX>uDdhC>edeY%!%<{Mdh6
zD4y-l_Ai0a09H$H#6ULxF$@N=Q(lA20rvO{jP4-&SuXm**;gg#OJINOfu$tYze(|b
zUJ5<0!TaT#)<AZJFa2CsZtjHox4+6^@4LygM_+Zu3od+bxCMmO`TdYwQ?`k=@@v<e
z0oo6~ZcteF<wT6{#~R8;{nST0?)4ieNxwmQ0SX(JQ8eY}CDQ=$>jQ6S{qe?!Ft+7w
z%2RKxXu`j@Et&+rJJbCols%Zmd%^Q$%D$p8F$+J!oa|=qU4{4_rb&cDreLOx7NOzH
zY$|JxVDj$5<w(Zq6kLd6ZaRT^gy~oSm^h}+79^2*^#aVJ%rCUqPGj=2VCf=LPd;2?
zu26kN4fBjnW?g1dpTh1HM*0t04NUA@sNY~BXxr4zghYVcF)?lmboMiYR73HcnbrcC
zm&_Mafi}cEod;}J_V?ET6UCm}3+6F)H}V$$_j4LSPt@Z~=rrgQFem?kTZPOYQVgJo
z@z$ZQm{~gwq=fOe2J-~7kxrYRWaiO6x`O$`jzXE|nUo6XS29QF=BQ$x(;D>xvxS(|
zOmHi_yU2{Q`QPX!)4soh*)b0@c9Y5d2CYu!;!=S2Fketi?g7)a2nqwtQhK~UW1J{@
z;l_S_9A4~VGideh&gO4}LIC^re;}qncIOYU8^qdHLUcd7=U0dxU?Ue{au2epH$Y<8
zU{pTHVp#)iKH}KyUWmlAOMU?}on1>0#0>T@)t((^GjC&73)rL*SSn;A%b;GwKE!qb
zzx)5%!7O7p#X#X4n?o_kauZv42#PiABMO6GX1^Q{jVo+6J>+WHV%o{vU{}%y&zf0f
zD*9U3jdZ8BvQuB7uZ=CIt<N2H@=EmGWe*LY?;d-GB0%@qjAbA_><^#9(gT)#6Cw}U
zTFPwovYk7i-p87jQTFQ*`-H-1kJ*2ykf)!mrxNfd>{5EiJ!J>(Lw|s6`5Qxf#$HH)
z<a745I<#J}VN^mo$PTOp+Dmq268iilL3f~VP_kz<%paBvH()G@k_+TareyDakhAzm
z9hlc7wI&LC+?V{m6<k+or4gW!(iGb1rb}0U0B250Kd%SqMXBOTFq@?{|3dMRG<-YA
z3+e6S|NjwiNv5H!SR*niBqsZhieg%2U;K@k>yWLA2GT9rzdIpvNA`0gZ1&(ky#R!%
zPxj$%h(48hZG_X$W&eyrYY2%Th`O8Io;eHy!yn$9$|zROeE_`gyxY<F{a?0#S>r(q
z=^tL@q4!t6e=r%FzO={R1~b|h82zXO*{Mnd=GO4J&~jlmQgI1_rF3N4hcUHLakMWp
ziGnu4%-dUlzn8gG31&F+Nhewn%(>O*i)AKIq9cx(L^;e<riEg`Y0O8HA(_rRZ$@7p
zllK(P<TF3htMNEf7Y6kL=Bpv77czq{pisoj41_PmjAS;PDPcNHJ0Np{*<=P#{4g&-
z{}hvY667><kTS?;n6K6XyOjCnW9Xk{w$fUzjQN}Ll;@aLe?p|3c@_%L3Z|WEV9ztx
zSddD_(G8eY%)OnMf(uOU0eDf(95R7<k#VSi9-dZ>^t!8ICU9t8X2P4`Od~Tub@@%q
z;_u+%b>^$#uyljDvX!nYqrL|(T9_ZwA#$7P8w2bvriZqt-OR}lsNZ2m#9~VBGQa-@
z=zC1UaG>005DTS;#AA9$WU#k?2G}un)I9qCnDW_=ngLV5o~8(T5j#2<q9@rmR|Dn@
zoAwh1Q^x*7Tl@-k2BK_uSw~Y$^&+e5g~%25m!F`}$a;A~q=Q`)1lL?7xBrlXi$6jg
zZ8jp<_#GgTY+W%_53yPTiefL>V}pgINZDd|d6@O0Bc(^!4=L*y!^VZp>&F|q>to<1
zu&e)uBo-zO5J_Ucrh?sMwwc!AN7(>dIFiD8wm~wLJ%0?6Y3v}a_|n;5s5l^l{a_DT
znJm6rNa33$w0F*9oqt5@B>Pr8P)@OLP#Cv@b#j5D=h^YinCVKk$kYXyDwbOUjjL?K
z7MQPNe;b9)dN$}7S`F;Bvrueh=YEKxwXykh6ri0wKmnT$b`amcLBM7T#o0Sq*E#6B
z#U3|6?>4)v8a{QgjX%J{ZgyxhQ0}mW6#u=;KC=SYJ$8O2J%jGEt&<_z!=5Wa=L2?n
z3dmD-BduTu*xC#@{EXch2}{q}3OXC|g1zt@%t7{a6+~XLsS80~u{{US=P6k`7SrV=
z89|?g2$Cr2X|-E&{Ra$izvRUTh#Zi7(T&z&Nr0Zg9dblcV@K0185s?yj!ODyZJaGh
zqI61*<o6zk7D*QE2Emt1`yp~xGLy>T$|TlQ({xUvje_JQiR(y^8p#h7gSsp^Q4gQ4
zNDk7YvsR*~U+`7Qg1P9clWf`t*XkwP@vR6GzAu_c7wDQq>j{}gN#W;kze#e?0@&9j
z?>|J}4atPvAkC86S(vUC$&qI0w@NBc0If|jm44kfC0i&}*(vd&ZR0J;$a0v!Eva9G
z@!pX%(2D4;B#TAgJ&8jNB=1Y|=mSos9!bkX&|b-w)gXP64eNmYNb+V96kkd#{ekTw
z?V(avSLq;C^SMbMlE^M;73EmmrIq6$=^^!`aE7<^84pW7(v9E1dw(ha|C+n<sH&<p
ze)c}+Zp85>g8HIRN_(XYmr2ny6|STpih_wCGI&)G0l6R!*wrNn8lsrE6HwF?4R8we
zI_0cXYGyfyf^&&OK82jJ_xs5Hc>lfCT5qlAy667R_w8@mn{)TPj}PH+p;oyMlKEON
zJ%Nj~0kpMmu{Lf7(!Q{0z5NhrmG<NaH1=vgA3{ctXiI2E*9k3uH<<O>6522EQn#fZ
zQRE8t4n*?A3fftbFS=AiWSQ7|1-6UCmR&GfEdH4Vszij*#N!I#u??_N<ll$QRpPWG
z;$0)I(rndQVR6vIXqkA=mZA~GdEl0dtPU_*A=1i_Rw<%?hT=w1QjKhH7QfTDVv9&v
z0i#<*A!h4eH6i05JgO@V%EC9!hyLhlJKRSE#vsl}dpdtKrXc__QT2iN9&dwQxNd^Q
zv;xG$@Kg}-;dBxx^&hm2#vDpJE7E+ZZ;)=Lw^L0mzX?wn=jY;k<{nzA%wpR*Q`xiF
z?-9#Fw%3F_<g=u9u(F6XD+erQZSElW0@hPS#+I{#)NmHDCG-O?W-m`s4OzlY-lKA2
z=V;Yx3mbe8wyo^iC$RPvOQk;ZVfJ(?;2Ty&L#$J*nJ28BWzPE%<4?>S0_qxbyoX@w
zS;7M_8`;v<usNHDd%<A=9}op&tNDdb{@OUQ`fV^4vocE#>=v+<UeI06+O!5$#7@v*
z<zkl56HvmQ_kho}%;<}>b?hWHI2+l~BIIBboAf1|ZD#p9n<5XKh_s#TS^%hBtZobn
zU^fe>2lFsn_7<ok?8UFh+zIwIH4!J-bY}~~ILGeN)`jzIl0U4~vgMmW)v<n4;o>SQ
zuR;#4v2vQ_ui#gLpis$QKA=Z}Tj@00CO+&mBscRRG@9AMkMsa+<y-ZDFS%zna(0}%
zQ$N0zH`1%uO4UpwV3q1LnRfiHR!^RWi#4h*{mMR9i#<_tYgJDp6xXTs-Jn>eHqueg
z^=e%jL^h~#J(0sNRE-|9a`gl)u`JRq(4K?Envq6@1)2jjtV^_2naJp;S~AU5F4f}D
zq0$v<?^2b#Osm*WBP6Ni&^F}Hw43W8vs|mA4e&+U=27rltaW~YtYr&5?Xs&7H>SYv
zCh_!5P*q|EHMcv&m<~|bDHgm$CiV*7Dv0b8DKsWJAlB1CszbuHJtP~&rj?M)vpKsF
z?kjBuID%=Zw%Kz4<hM3i^m3oGHvayv`h34|r?#+okLT<`To1W{Awv!PHcdV}<sE1$
zDMu~3Of5e??UccA=y$OSB@*~qN8AU^qeC4-vT2uN@C`a?G}KrH6T=Qp2S4O_M;ITT
zXeono#E>u;jST+-$z!5u;Vx?b1Kf`-EeAikPY?o#sU8WnglAs3pVW_5?9Ith$UxeK
z^^nPIq!&!g%IOcSY_`A&$@5qswN5!Kp%%<sW~A}ed=^W~HI+;~3i)kpzJ=D1cC$Br
zfYSpkj%HJivD(#Oo?zGP06(zd2NC-PRzRb~E9{T!pl-5lwxI5^xc<m#13PmZdcQNL
z_DGw{oej{N&tt~F>Z7!)NkQnwnT{xlfxHT$>9=Xl<To~ZI(68duw&g|<~iHg2S#78
zFRP&c2MeL2IkV9<0CO&1{yHSH_?eS1mBW3r;3=0I=y=knyvPd6OZm>%ps<lAC4%~j
zKf12``KLL>cb0;4fvbfuagoos4uhBYu68JopDa8#8d^1c8ZF}8;*$d)dYcD(fV#su
zEtAyquIUiH&tJ=c(+9jn2d7VYuRxf8#&;JW*ad2kg1GY4hcv;tL`}*-CYP$`@}O6!
zcIo@7j<)}vI$Muef(3>ivk~a!T2OkWIq=!YW`70~zp<q>5Ay^i3+7zjE50e)(=G6s
z#|QU@-G#jD5?mK@b`0j1@%}Vcl3Wn8lvm_KeHHhix0S8tEvTH<@V6d8vYbEjh5HKr
zq8Ah@`I0q=+_DXS5XfxjGwVTq#k<nN-#*?+f!|}i8|`YS=FuOcj85@;3iQ9{ciKVn
z5}!;B?@ydvg|!+!h^E&s^F$icU*YpNBdwN;Na)q^AX?GB$~(}!+cn;Up8V_l?Id{k
zmxbS^1-wT*|69OgzMMKC4ZPduP;BHLoxps;^D`j&jMvOU)}Hf2ouEHgjivo5S?ck3
zA+k!Xr1jkj^~QY!vtK>rg|zc(37tf$RXu)%$USug4eA=yu^~wNU3K~qlG&Q&@ETZ?
z+KxeRQK9(;f!e2eo`mQrZN?qMeO)_1+x~ykzUv5UpXjPlYv~GgooT(hShuARF|E;k
zM4O2>=yqm;St3T!Gzq5VTf%Rtu&3GiRbn`Y-WOsUt$9_5eY9t$Qg92^eVfDvsu{Kl
z|0|$&h=&n~!YcgYQI@;JmOMnUNBBBJW3M>wfzbAe*xN9AK>Roq%!4A-9_ojM^-ZWB
z5q1vHJ1S;`gZYhEN^kT!DI95<^E=Tu0(z%J_B_P<qj<Cq&s9_X6;QhlCH`Ue`w$+a
zrwOmYZRng`pb`O2P{~5XFywRk1qUl@pgVNYEu;=p&p<0==2qAq9z;FH5%n*T_t0UU
zh%#&+O&5;rz6eo$6hI5vqYmdlGQ9Q@ER4QJ-Fr*K*#wx5JbVkuQBOOfjK-$4fuZOH
z_29%DnTPM#-g6)tw=N5Y##wK}gy{ywJwC+)oC)UDxSyC241WB;wvbGy?ScDAS;a_A
zG}EIrnH7Pbba5p($>)RNCFL1)Os4dDb`!Cr4xm*=^ICT#WY~R#`<Vkj0DlfUN@xFa
z+4X)fa)7nK(zUX`rJ|_H>ozi-^I2|wy&^}1;xok4!!JG7G|1mL*5GPzcQyP6FES-D
zeL{SaIZ_trxG^{*KFQOA<XqidJ={G!-Mu|L4c_iPk!i`viRQ@I_#`)1SGUCYShopr
zac(iGlU<UMlT0qAnAmtXgTd9))j;WgedHpQJN>@|(q6`D-0N>e)8)S^7U`+uUH_K-
z|3R@kSX&Anw^#1Zwe_~nKg5T)NJ9%@CqI_Wn_Kn2a^KVP!7t7GS_dCgM>zHI>*W?^
zHl>=~;$l)0Gu-@5=1FPEDQ;=WE@=}@E|Zg!liV_rQzw~IV&Y7YNpeXunbXXWi%p-P
z$jfzV`<$9O6_;kMsnc~Tkmf_&A?L{yfy)M0GwYKnw$%<fk8^FUk8_)6w6^<jgmLW1
z{y|~JP9EOwP5;8IIkNf0;c|dSGdr1Fq0`AXa$9w?cE8j7&2X9BRc$Lb*QpNH!G0~K
z8Re;dyrXpdv{hSK+Pg(Z=`>B(%o;Yo#egR{<#SqE%jdL;5c1pu-b?lfv9*&c;%#hY
zw6{*PPRwm}b$T;zgRhIh*UKP7@ZW$~V|nY*_MLpae7$|#O`bl!2CumBF+F?sG#Pq$
zx*H6!<Hq&yGWq1xv~P{8jkTt|{(Ykb%LfWa|7tWLx)W%K72ZlwN(o<66m)GAZm%d9
z)hirx!oGxWC`ue*XGOv4qr$r=^ztx;zl#etxQn8M6Jqz3mC#dB{vbp@A1$N8dn*dg
zxhT93UM-qNHy<cUK4E`F*+A%rN`TO)C>IF>6veg$aIm5bAVh_a<GBhSrYMbs!xcr3
zN`r?g%6o((6~&(rr%R#;F)p1(7^x`5gc!4LCycQ=MCtpsVKp*rvVJJLA=eSyl??!{
zIm>}b`e5GDSuP`N=PYj#Iyy_AWc@MzwzGVh47$6s3{C;Q?<`jm`a8?}gh9@-?-XFD
zv&^5OpUNYhrAXCJW#i<mRDA|ZlntqHmL`qnCMX1OM>l!POuBufPa5g=lk<QqPo7PK
z)DhVwy(z$Sf;@TjPs)BOsrt$BQz5!mZU@OuNL@ygXc&OE8z{>%V9zl?HUimFX`Dt`
zjF8KwHIX-oY<XAuOmFg*JsqT1cX^J;wX(|$m>MV33C_r)0N&kSI?QZRHO&MWG*IpU
z$y<IXMJCvHWmqQIp@FiD$Q!Z&B+HV<SxrF|0(j_1d21FDv!wUO;MT}&f<$>1z_oDM
z)q=#wGTox@#tzHX7X4c+Qy#VG-_g0Z;Yx^nNSry+ezyJ{_O<LokSR?79&ID@XY0En
Wo7;)IR$d0^GNbiMf;^q6xBEA!uQ|a0

diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
index be49b2f9e0a625965b0ad396c1a348cd1240dc14..afc119bfd271189b80a608097a2d047dc20c4a70 100644
GIT binary patch
delta 128672
zcmYgY2UrzH*S>q(*4rDFXzVfe9!spz#BQvKJ;oL_YBW)!i5JB}6Qzj?Vxb5Kh@gT9
z0-~rWHV{w{L{y|%upx^6?;*+e{64s|bLPD7IWxOEJ9B3C<`fQjUNB_W=gfrTEqt`n
zaJeY^?6g6UP5OiPPScw0vM!=bb@^|FOy0raYne=@W;oxbyi6@u{j^qrg#8r9$<#_!
z?~j~Jb=aGg$;UTZKzd3xx4T@X=2V9gpun-Fd{$;rs(xAiJC#+iP`}Vrlqnoc-Jq^<
z#zFP8nvp5Gnt#N(b}tUrA>Na9z1r+>R?22FArL6V2}35zW;L91l534pHoM_mk{WwQ
z>l{W+z9Pt!KQW3c&}GS8)#;&(Os4oMi<iloOd38}#=sZl*$U>LVs*P;skkGn#PRk@
zR>mkyt>iMf;;6S?|Cv2KlY@Lwi3phLH<6X8dnx_|K-ZP+I#e!`F*|cP8QWbVUu8_=
z<w_abt0ALg0x!aYz6}|U@qYq)0~#_CQ&gdnv4a{idL}njkg-D>GG=DJ9csfHG7ikR
z%c5Pzj%vs?Wr|t=G`1o0Ig`rsGInA^rZp2>1sA3?WWHclTj0WshD=A9s;<96#?F=R
zhsO<#!7kberxgk3;H{$Xcm--3(wjqVx5eT@D9$Q*nNkrEu9T@{DtBMC%+4;Cj{`zW
zuzwhSKSB&;%c#}Xw?}))R3(R58M{`#^M5*jmy^!wi)eC1<8M{4vTCIoR%Q=U!%Fa5
z4p!olas3tB0tJ~`rn=r53|r-KfHhs&M3Bv8UG=9GGMSx;-6+af_vVz5F)!MpIv&la
z;g!sUt|-~n%oC3EWY)W(LA;u|qNEqIdICy(nx6&cD@M#iW_ODl$P8c>e+{)g4Vl5r
z+y`j+eGQp!nCYj{ya5fF@0ix9xD0{Fbd<@)FrJOTaIm3h0#k4RnZwQKR-DZIJOQBK
zW_0m?U@m)4F}7!1z3s*}vsO1(%9vG#h8vcdS_s!yH)K%d!Xb=|`CaiC{xpv(6=i&d
zKzQT1LQa;fY)p3}{d<G|Ou$;)mGZJLSd<Jd0YdJ%Oxf9+F*Rp~c(*V$vQyC^<$(W+
zx*t-=f|LyxU+($4a>8>?7OHf}0F?@0{A*Fu8F#W>siDkF{AU8Js(($`m7V|L`CTsF
z6J>Vg*W{PnbESNqRgUb$f3nNu;c>Vy%0<ZHS@&El<7a!P{_D$v|8dCpoMv*_bfuN<
z9QxN3|CxX#|5=-^?DwxV89(TI+yY9|e^tNLpc(t0rb;>F-}=c{oWgyn{E6-^x#v=4
z=cc&Vl@`LuJ(X)^yr=g}^FNJpQ8DQMgDxuO{0oxbPhe#i6|2o^0?lvW$W;8xu~w!h
zxq+ZEj>l<BYX{uo6>^-)WM+t&fWHVy4PPPe_>T>+xbU(n`9BS>!Zj*Q_kL$?y41Iu
zTJ}P2Ye0CelyO#EPQiZ$E1M_(ud-+1JQHAI|K*$~ANUXFO!@phD(L-0kDJ_chCHh;
zkL;iST!hIDe$SWx>-P%fSZ_zmXP=WBi~e=PbET5ZFZs{>d>MbzJK55xFS-7Wyw5*o
zewPVdyUAtD|NOa+dNKi9{_}^C_xwk3nbOx=XKlvx_U>$TXt?jvnSVK!HQX=h%!q${
zTikHJq%$-A$<A-MU(%VC|77Pjcz%KTuf-djyu|#kjfC2Ih0KrnuX)xqxHAi#a6^;(
zF%9n6@f<W5^<#$pf1`fP5C7jNX#T&^z5g>R6CUB_?Dan@Nexzf|FhDI>Gi)#qY3-`
z=iTqJR%6}?GA6?N8=D^fcu%!`$@s=?vTajL`2$^n;xhs5hCa_*E~?CZXP~odqE=at
z@54LoGu1yuTNvd(C!vg_`h4<R=(N-*c&$qK&{!c;NOF~WA<N4YoK9u^%zI{&?#x{8
zolP8=zTRO?noHAmi|9I!Fr2Enk9T&H<?^Q?-ou*qW_o$AZ`##9VJ;*4hh3@KF#8#L
zS@h%hd-f5JjZA6gaol(h&zdY3uOpSLZwe`BX2@}Ls}o4_p7aB&NN3<jDs{d|*!>%+
z)OkM1Z-=56lR2khR3P(CrQ_wLbgZx+BtZVJbUaW&qETLSo-~92(j5hkQAbH$?Mig!
zF=TACf($GgK&1n|BFUDI<WR<0Iz|p5{Xt>Ga5bJ#bJ0wwKn+ReEvEC`(R3a=)J|ZF
z1Hmr;Ot23-$-FL)yq@@$%zSy5R5yMi%~rpX#AQ8cjvGkr;dP!`=(#g7G(mR^%`2o+
z(VrwQhtT<VS!8m>O49$LlK6k=&`^3nX-CGTD~VPwAf+q&sbElFGG8*1=!T(JSIN$A
zWO3ZGosMmvlEm1OG!LyKonLdvi9fQaG$ny}qC1mh#0x4dA3^6m)>2C>jwM^=#l$~&
zGJ0&4?7`1e{6kw(tuWFt>j0^~&m`Z+;)So0rFErqj|o%*Ka7f0vYtUCUtdA4^v)%H
z#V;hk;ZAPdzd-T;ys%WVyw=oOhsMxxOeIOSt!QXJ1K8}cU#>LNqY-)JUqxoRHMBv`
zo1~N!NG7|FBDX4kBJdbjk_=o%bv^A&5@P~sHVPw#;S<RTT^va|eMfFto|43;;SQ_X
zPv>!6iDAN7a?zgEP>*3@WOz~sqC47&h;~V2(y5_&>sQfv?ld|suOZEn26>|fN0&Gd
z-B%d>s$>xtsWMxx)A@Hd$i*=Y)foAKbau=j^V9WYB{+$ArrJG8)q0$YcikZat@e;#
z!Pn{NbcS4sX?T#Vb##8bIcYi-(z(uubVhoSnS3J|ZryO<RxYK|!`+E(RxFjCh@z{$
zW)PW7DkJkhG*sJ1XD6lV2}E?%i_TljqhsOcq!hD<js;peCLbf6DKr3+b!<cD2Yw;a
z)P~#ES4TQ?e<s5%cTknK%pqf+uO-P3EeSQyKoU+zrG6U-n==xFRh7&E19FwDzLKul
z44M$gx>OLIZ$~=+Q$c_y3yA2?+a!Pch&1~*=;t>WUS35y3pSDb@;x&1uqV}<$Gk)(
z>wJY!{`aZnLS3nJ#}~w$n1aD7>VbicO7@qURFmE5Jn;${TY8^JJ2iAZAus6Moh6Dz
z>#3=|J;^{qKAp2o$iSN{!fy6!(40Z%ZC_AnyAU#Ypg$c0wv&}lYe@dAEv(pOVK3>X
z$e2i?X=XYaW)s~4Cpzx-C4jSm<PphazNX<?=JzJ^Z7^6v2kb};jT)2W?R1iib0zb6
zdr2}rm?YQS$^7A4R52%kn1kY})b7Jm@uLf5;MxQ_j{A<3TpFC1l}08PK5Q`KLC54`
zqP9z<lju)|i?wwAtAQNteW5{em(G8VBJ4+wj_&WseDzg2KHE&C5zDEazO-MVjQKp>
z0m|{Dnl^>}I^;~G^3O@>P$ua#-9$R2mq_RSV5-5E6;#?dh>jsw$hlwSq|-c?7&0Hz
z`G!<7>Dq?a)~}=LwYf@iMSId;pu^k={hbpT_^u@>wQWtuUBjrjW;oTg=~RNXSVZzc
zoe2EdY9ie=mL$7p({W)9@f_Ss=O2F~)Rt+a`T87TR}3H*C)d$=LT|G5%SNieU|%)e
z|D$G8qg`u8CjVYb=amg^1w|6kg0G1v(UA=7A4%X=SLpmgC>a~NhESC)NWL<P3{3As
z$3_~`SsF&iu#t3paEvsKUlCi^Vlp3U!4O>~n=_G!7QLW?QGd}fpy8F;aT3+C{|9p7
z_#A4|e$NQ@w4s0Wdqig9_Y>*cW5m!Yn)HR!RM%~1sI+4u8UEXg<c}M8k{=Pj<0nGR
z?FUY~Y{Fs!Oj=EVT{8&a-0;%OiXp?XP6QrVO-BzoY5q8$ocKJGh@7Vr>g57*E>2D@
zr<_G7_Z1|0vx87`C=?-k_Z`VI6Y03J3CRyMyjkp19f@dQf1<vbLdP0+GEkX7^0njW
zeAOzdU%DfKt2Q?1|3nnwzYz5$J)LjBkXtR&JCNktK6HLnuf$RM4RH)vW+oyCvWf_D
zE8Ytc5SdpDO=1t)4G0g&(!ZyA*ZWbkgnAR;LJuO{*)R;rY`71uJwaSVrYxXZ?#m@7
zy1gT8?F%AJS<~QRC7pkvr(?2$H1$?u?kkbz=S!$E&26M<dr$oPZ`;)<Xz_pm2dc=x
zj;}~{*G%%U|2Xpc=MLoQ4_}k!Azx}Ccf=ypvi4t*j^_b7&isik#F;Z>AhTh_*P=1C
z)@F2KYT2_DB!AwUuoD{5@%3wJp#_f`?*Fa0tJN}p3>wuk_c3I$Qy{?}p?_A(8t0H(
zcY0Ed)eZN-#$ckJJ(FrSqT!zR_oikKix8<mrfM{BA?n`tcg&nrU*`XcRvi}qC(bAT
zfuMtGO6+TtPTk{#^J(@|Zh-zUehU2maSNgds_9?Rt@!igUva)jPA{32VRVJp%0EGF
zKhz8oC#LZ*Sa)Y)GLY<MTGM#LkEwbJC-*QjGLYNL6s|$CkJ*Vyq{^Qe{R52dXQXGa
z8pyosg^O^2*&Iv{`a#C~8yGvp%*}=BVJ3YJd<|lX>0J@bumXf3%$EYVLz$kNksM*P
zG=>OcBFBO)oO#e4+!4&u;Q$<EUad!kBbn7@ppIfjQLi1%Ts#BLV~i~c!WicDXUH9A
zgj8z(SZ0hX@NrDFfWi|@vt8gm$xJDQ-BZj%8l}ZEW2uKuV6>iKJI%OIv?q~KU4Z#B
z%=aOHCox$O5GFH2sDC}nZ1aaRDNKhCU`b_0Qb&}=%#DENIcD&Fm``VRMIk1jy2)%1
zQFx1aiu*~G&4@G6*g4E-KXBh>q!b`>neJ!NUUwMZAHaQ=`Tjic1x!5kYlTdkjz~(F
zfNB^lWxh0k<q?zM3P2gNjb0{Cm=V3uzEw=8AmFN*79Svd#+;{-xcxa3@g8-0!K_>i
zX$=!yhvX&W`v7)dF>8}h_L`YL9Ktuu#YsTCWx6~^u9oT27LL|2Ki9zEdnW8PD*Az$
zn}o7Y%t^Ywo8&!Pplq|8^@fLT^3|UN*vDVn4C+LB{`npCzsqxIEVSazNmyF>Vie5&
z7PK7at1b`1w2;(W)_)0&E;Cl4f?bvSaqPCcH{{)Cd=6th^61_@$ehGXr$Jr$rZsA-
zcB5f8JNt7Ga_*6k@U7K|8xUa&BfYe~2p);{S35CXY3{UzNkt#8c4odigKD`jNiEO~
zxia5rq3_1jx5UF2$XI5A?Etf{7%FcWpJ8yTo=Hvv*;e_d+0b;ASA7fLedVz<7}_hp
z5{TRZd4&fW;F!GoLf}&5yS4&%MXr5|NiE(#GL^1iISLx<mP4z>w#lID(sVoIU*A+f
zbJFY{@bA~el{mUH>(p=|lzFfKx=GBjzfj3*%>0w+L0&QHeg8Ir&~iEm_4#-Ws5`{m
zL|@Y}0<Q;kr|iGcnRNc)Z-g(qG{ltcU2FTHYTbsFqTlJ>UO+qbXn!A0_guaojoYjL
zWcbm$J`H~KF-78PeziCi$G%n?ne<Dh(aSK8EhrsTvImY$%%_*ctdp&wv$$+Hcz)~G
z9;NH186n@qgzP}&oSDO`!0pXc)(Uw3{FtWnY#(OMtC2)8$2pLmVxCQd+X+mA_otZ#
z_Y;{0|IaWD6-Z(lYLLv3*XnajLq*aVs!79D79y#Sx17qwu~9Vn(j+PjUbkqS08iUE
zZ$x{xvn!gRAv+0EaqQO43&<WR=zLXuzh4GtzShxY9Q0x-Jo;wPEciZhAkC4+Why~8
zDcuplExLfVe%C?ynV}=jTeYHozWt01IQBAjhVemLG9Vv0o~E9Yj?z=-$SkFy^d=_I
z?gOIDOq<!r?qP=2f_yLY>o&NykLkA%t#p`ayB-`tjOrzT!A!4wcoEGc67Co?uLgEw
znBy9#Brv{@06)!KISS20rqNJXJ<lZk3BU!W=SgU0F#2#*C5M?k87j9KSvK{*xy+PK
zz&~c>JAf!-II7GOW|j`BZ<y5=fPc&MYXgI|%(<-)Zj;9}f#!C3{|_+eEMH}TaJM`Q
z3ll0o`Cf03?U6sthWDZJ;fFwWM80w*%EIIerT}+JzJD!L;^iyW(EL9^{#g=CWXRp-
zAh{@?@&Sd{<u@q+lP7=N3N-iRweg@SlDiT9fjm79jr&;s8Q!9*O8Isjn(K|+e--ND
zs5r6$EL#=ZGyu3Oa$KOfLm|gYRJBJ@cNd&{6|-AHGg$HCdYb=)D6WhK;<zIG5-i0k
z?k@sqnj&Hh@aGgOF>r6V#Gm&c4p1wp3fb1fI-}lg&aFdKlZuCK!H`BZtilVnzFC`u
z^KTEA;<zY~`S)IIJmyE#zkTRDkapajk7JidU*g!^9@qi|y`Hpye_!e8&g(zz7f1%4
zE<<|{DH{!kzv-|Xs$(W$p+PnI&SuDG2GZPYKJx~p%lZw&aYdJxU|2Qq4(f15J#-Rk
zl%%%0!f3L(`xq3RSEo_MGSvf>D7&Th-wIoI)b>sin69!8KSA{+`^5n0Y~lyYfbis_
zheGv)c3%>NXS6M9VcAo^cp`E>`lqM<z4xP;R}^6=U|gw<?=d>8bE%4$W%T|kVG=B$
zf55cfkNd5Zc@T=kM;>zt#(d>FBRRCcpZpFDmG;PICLq}-e@PKIf4P!cWWRjLTO@(<
z%yXbQDF132a);!-X&4(MuNZ-f2h06E;N?kq#Bn62<l|_5eN&$8121mL=Us-+Ir0#i
zh~Ad(xeZ*N+-(7>o-a=u0HOV^Ttfkb0{KO{L+{DA_JXuXemobd_vJAZvnr9lt46L=
zzI+KtAIb+)IPkIj)mu1PCa)L_VY%FQDR32XhlgOPk_TgTPE{@M90F=bMXViVn-sqk
zB5_g#Q3GvJFw@}uHoL;{IlS4fD52qam_kiYa=2nCU8`G)QbaXX*@~+?Xl^SS6~kbz
zA|?_l`3g6hK;BWTqnJa1;>&hO3Kf&-5h_w7F95t)G4?8w2a4`<&<Ldp=Of5HQlxYO
z?y+KO63Ct?>{D`(Emt^<hNViy!4=@HQn-@&rwSKe<en)!>Y(~U!COI7qiEd)ny(Zp
znhCyEh+fFORfN4k)oK;#%|TYDC@%!=y&{+DTdz2#h2}>^7`@##DK8|Vx|@~nu<EDU
zs=Q=JY*@8TNz0KcXXTbWRMbW3^DAoMro0pZgYHTrbzmOK(0Z`#R9?LUpr=wB08KBY
z$9kCeQU0Zerms>v2xWfCsXdVFQQo7Fg1>TpEK~xN4=FAes63btFAgYkEC3u*b}6!>
z@UZgdcsLcJ{A?Gz2vv&la6e4BfdYo%%3rnvaa7rQ5D<~d+}_AVE1P@{wqr^Q1woE0
zmk$IkR%saw;R&TzE^dL7N~hZZBq&{ehBK#?*<C?)MmaVb@Fb<V6;#eD%k&)jzZB))
zF{ojhG6Z9P)j8$*i$I)L>Uel@LFr4Qtc%Jfw;;TvoNykRnacIl)m>3;=HPvna^OIy
zTvMLMlCtWCGI9{gZYnc;;7qpiS~gU2lz!Q$V6L)nf3V~!Z<+zPqx{wffeh7M<zEzo
zE>vbdKypvn$r&`o%FK_b+I^+j1FEIU#H*lrsQktW$z$cRu23mcZn_H-<;q)MKv<#l
zxr3xySw`>2r%JySXp-m3i8`>nP=5Lw)Gw8_AK?8fW%xamy;1hx34r~rQu905-YH)X
zgKC}9>l#QuDCaLld(|u1!_aY5ouY}wCe_n20G(7Lr-NpTYVGH6ZJVm|M6~60)gCMC
zx~Mj)fpb-Dph<(fY9*GVR6A6TGhtz;s!IVZ>{8vN2hU5DF&aW|yUHUGI=fZ=BVoc%
z<xvWQdsRir5bje24Fh+8ifawk{i<|d;18($)6u{ORo;D|a#&SD5rZJr=p4F(RMSnc
z8>-4Vj$F7Z@H<$FP_3XDXQZky1e#GQHBGXQsUFj$Hb!OdK~G1Vs<0f~Csgka!u%<f
z{x<B!t9*-K_q6KT5#SS5Q)rT$q<VY{D#<D*tn#Q*RGsz!o~p{A!B?KjcQ<nRs{6sn
z6{w~S2Ch)G=QW%uQmMzHtXS2BVihH-rlEj8P))ZFfu)D4>2mn}NHwqwI%TT$^v->v
z3b+hU9o3O(NH(e8e+{9N`t}m|v_(CBBAnT#cJ2qjcJ%^!d$_2dT!tlAb?_K)?@$|f
zsCcL&DfZ;4*3etcOYM3dhJ4ljJOI1ZiyZ0s+oSG~kA~W-PECW3zxoix=K|Ct&cf~u
zb<Eeu-Bfp+4$T~O(L>~JtNo{<EKlv;4}g625ohG?s!bG9E>LT_LGzxvt^;yK>fHn2
z?|rpGja-TP-b5s&>WL=!^iaJbg2nUqSiN=#NXyh6D2`IDetQfqR;ZOL0jyHD`2nic
zYR}8C^juv|@8B2eA7eoCN<H!_aIe*2vCynlcmD-myi;F%in0&t_B3X!SEnLup!%e?
zQ=G_=ZTbopHnW3opv;L4s%7!~MY9T$9%H+`f{Ej7{ZN>QWw-7D+X=SaNi^_Dw&|B3
zjc0r0A(y}=a<H4ormh9e8MgE15GJ$FXj$nj%S=L9DqD9IoM~+HWe}#b+*GKXXIoP+
zJcHeG2f~Z&Xo^+ZFSFYZ!EPoyhkDejY#tW7RaxwEioaZE^C@nBgKbH#j$3R`n)GM0
z&U7Q*X3KgZ$z_Mq=s%wwREgXj)}ln?6|ke;!23cri{kf1?6w5dzL-_dfNLe}uft*Y
z0eh?(_8!^UH`|eY%%((wrku^YMUBrknt`O6%^3~hQ`W%<{0sILtyt8sN_w}xX8kA<
z^oE@>0xIv=L?;01SUW{w>)F}#_<v+44TBes+|qs!ZsKOSBj?2Bm&4I5TyX@P*~Z!P
zl96ubwzdPph4a1+ORik36G+`TmLeECIQMf%c5>6)pt*~?y8(DF&V}w0Z|-6m5?^kW
z6MWjuC7gy&=eU4DsCGK%Jp@Sxm$w?iiyX5O<}<m46iK|o-9HaQS=<TxE0A8}<U9=C
z;2uwf^d`4<IM}keV44-?a5;XU$>XYB0nF!i(qh3~uKp(o3%I?zV7`cJ9t2!5_lj24
z9&oevgR_*oM%0hEfX66%%(dSJ_!I6ZCe^BPZWi@{mE4<0H2$yRR))jHr(EP%Af9nE
zyF%v$mpcwg4Y%|W%3g8iYPkQJbN?2?S}w_xTAkA@gTeRQ@28Rbz(uqN*(c5g>(DAk
zKJI&HZsw;_z}kslPq*b(ehoGLHh#@jB+mTILll2;;VrA+jT_(cB}};UJ08JP4}QES
z@H_dIv!Lq9XKh2yi&qAK#+Uzl6NJ0@5f@;056@7beJ?+bW+4ImWqNz>=U-p}S#^+~
zLBoYZ{H$!`g7~hRP?unS)NQyO%8y5nW>+2Ir&4$#oPY5Ub|d(1U%-n<em#xSqWJGc
zB**xeG6-XMU+OjEcv)vO=?VVoba0>I`&S@|=PxeC70Knz6yv<Z|4nNyclmYa059Zc
zMj^S!kD3g-#r(=pklp8Z$RV_s@_%#%@F6dweHxGXz&`;j;}=W-X*qAEw_yc8e-MP#
zd~p}3Jms@vkbA+GPzP1R@3;u~E8c-tEnf2&Utm1O8!M31^7Fq%&EE4$GXH`1p8>lc
z`GR<Ge&Y2pfN!!3`5s`~EcCn%?k&P^dK7LI%4ii}yKo>CI?lqp5CC0;eudC<6S}^F
z$_}A}BUC(udRpV$C0wD=ou_ci5oO-O%`w3F2zk?i+b!sgQ1KI7_5%<r%$fvYoFJs(
zYMm799Wv2gr-W$~^GgugEQJ@Rg<yJQ&Iry5lqCt@-$dD2VZ{#6qzHX!{F)}z?1rUt
zLgW(U&I?s004@kUhd}e9Fo>e>mjv50_>?J}rKrmlp<ps{*Mv4S%eyWdr8VJO!bbZN
z6lM#HE<<`-h|)nPS19ZPOZh^U1FpdxA$=B16bL`k@?D|O=OI*z1+f`&_k}%2fqNi~
zYJ;Ry$fl*mM?%MMkb5kwuR!udP|t&~To}0xER{mZDF~~CM+j!Co(k>9+0iD?gsI<y
z?S*h5423nqsJ-y*mEcniORojfI3%^g4i_Zv1n-_`w)a9&HAp`QwqmsNN8x5M0H1_m
z*lVNOBtD{;-Da`18Q$*`uh8_wUreJrVZZ3G3@U-*ubFV>pjh5dj_2=?csCm6gT&c1
z#tas}riG?Z@vaid5%H%)cp5Hdwn8pK98c4PNbx>Roub6y*I?<G*q$b5G2$(n*2ao0
zDT*2=M$x43q<FnQR8EP@TET9DxaSnAds?&=;xe5Pqp)eou1XTm211%5F75`^RB<WI
z<IaigXF(@jY`z=04DtKpXqk)Rm;=aN7Eexu!Avn$4!5t0mGhCy5-kD9T^Bddpyh@*
z)fwh*i9bIFXSS%H0-tV+p1T0g6<6IwS-zOD89DnM@pw}J3q<E7XxT!s<T<KVB&K$U
zPO+F32VjYK?jGEKAZE=0_d~JIKDhQs9DEHbW#UG<y`G5EZGcyZj~FDCVp=qkdU1Ie
z$hJzI7a;MH%4vw{Ev31`Cm(5UUzqo`OKlz?-7OWohSX1Tq5$(AsedLAd!?pk81$Dm
z(h6LFWHiBx{nA!{_!KBjp-J!o=}&UzpftEAaEGLKt&uw{jX4WTA=1J+079h+7I+vg
zMIQiJgj6sF!mH9H3MXYr_6%A^xF+qU2jIFimAcs*($(%rZc6Lwkld11tVfb9^`N&y
zj?~5h$!*C2^M6&YWZi%yPZ~%;%llFkk6ej#s0_7#D7A@1@<d8d!L@Q}$7AFwq>#Un
zR7z_)z<ibDZ_h+pEe-iy4IB9T{3r!uTfQg(rq#E3XyMk`$&j=Oxq(WwZT>U7ZTDpx
z$iMhR_e=ZcJHYqlSPJiV@JfMBM>m>Wb*jTANmXY*YTPalv8JQy>d!#G+h5;+p?jx1
zaQ4u4p!ieIIfDV~_1h2tdON3~27RVi!oXMOydmjZyAX8!;t*j~^&kBSngdoif$r-#
zdiDmnUd3^6OWKb!L>UU5q1!2pKP<ij41e>tAKV(P9t`;pt+BgSwP?{-sPDRP?D9m^
zZ|f)?_IEJN8zZ}qNijk10OLFnl)=oKWe|olW9b@3Gp(+(faA}VU9}5pZtOGaN8Q;4
zw5Gg+ZFB)34>pEgemmJIJ5jca4WMv|CtF4_TrYMV4M)7$0bL>VVSOmj;LF;_V56OC
zH~Y>8sUKTYjbsmdX&;RGvkrQY2Cx=vc2gZ-FVQIOAZw=p<RLbO8sRY8eFf?h!rq{M
zC6tY}!?h!9(<qdMu@U1?7S7J?g(QMqI2T?VWq+FwyOC^eQ*cJHtX+XLnl;iA$T7A_
zZ*a%38&*MhoE=6Hz*yE{7KCx^RV7TEU?W8&C)w}a&^o8s`eneyv$Nkon81#u7u0F?
zZ<-?{vVW|GGiTV^-EcdJ&3A`S$!zjjl$~WqzeAG3RwURVJ;xfTq0-qeP4M(Qn@hv`
z3+##^5N5FF2gAfgcEmn7bBS&G9Ck0WlMVuRg+2ZiOk8C*(GqJGJNp7!{Tkc66X4g`
z4|jpP!Oqr#<t963090<V(bu7Jn++gN44rea{;SGko71L@d^Y53sNP}s(Z;5`tU#+6
z1#Cx(=oGS_)F8db4kPnL?8|E?D`o@#LX+NSGkU<85_UM&C@`+hp=)2tHYx$jLw4Wa
zD0{>*v>N}Ijc5V8Wo&<1*?z*lb)orxIlGDC;T5b0P3bDx5^DS^Hlq)8Fhp;J+*6i$
z0Q1k-K7L4^vz^X?^aUG9QT!Tq+1K#mB^zLcqp#SPRF~K6rE@U&hTTBB;@+|?TSBFd
zZB&ZnJ!_;bbRXGye$cdkVn@-cx+B-UVUEvL)4Oad_cjgO+qphINSwJvxb-nCKePaN
zH!iapD(>9zAe8OkTG5)O2iJ&Nb|=@7qRzXx-xq<?lUqY$W-qRm-j?2+PYK{Y+&sF2
ze7VeJ$obj1)f9%<!##X}>|U<vIaoTxt@s(qVXnd(o(6HD1Az$UHeh8z6~g&ZcNog0
zO1Pp&xT@Ds3FDgS!4l4WO`*~VF1aIwN4ba5@F|juqoGa|=R*6WqPa<{pmL16p@1-k
zvwKlM{x~<7wjjlF9TNeJ<1z*ycY@ov6r?A)BQ(`G#m%ElPx0I=if|-w-|(o~X>Q*k
zIGV_vsDb7g?)ESUlej;70iMj6X=Heo+j0bDDO|e)FrUhWL?f5Rz32l&=Qv0EV{oT)
z*SDhZJa@P~oXOxC_XO!hE^RQ_E^$%6L*+83OMu->?k@G8SGdYtJXKe@+nvFd#r@F~
zW!JcY<l%L$+Z+gQa8Xa8a+3@C7M5;tUT&by<_4ESC5L-C5}dcWxK<Py&E-VuDe|}i
znik}9TH0=NhfATj&|R(-?fEO<HckR*As71;m*O5*NSh{#INe4#TFhOxpuYFHL3_Ym
z!WEqc%L6XH72u^@F2y?@auvTr^AYz(g63mx2@QD4xTt6b&)*ZSUlXX7b0z6;rh*%F
z0+uSd541>7#kHlGLp4`G@tvpKbZXgW+}P*9Kj++NIP!u!a}0nQuJsHEUvlr$;o2*1
z%RFel=2lY=v6)Y{qk?|?hQFY>kALwRRr2T8VD-$78A~+9jQ8`CsGkeur)q&ezz^~V
z{ve+_6lI6_K8xYuVg44akOlE$X`5#-Z|R66gugi#Nhn{w7|9Vnd>-Ioyq2EEaQ-Xm
z-6Qx&Jn5>Vyo|OAMf1(5hd9Q!o(X5{F}&+mWRLTu^Pm&U4{8OwaeNbh<WBIJyI}An
z|85*;PVt}78d5y3NQW?iPfCaIG~bCjibP&s1rN{gt$P5T#IK{lO)?+41U{YRuS6nA
z;albcp2~0OgCva)p%MQ%J1-rDYC1o4IFj>xd@`K5z&p{qI)itw1@}chlZN$|_|Q`T
zUgmvRG)X4ECk~Bxh5wFv+pByPy}h$|8Aa8u@z@A}8<GE(BB?j{IY+^AlaKF<D|w5*
z^#iE0`2ib1mc!eXNw9mHpF?Z1x%>bMwdL`jh%}!!HizmR-ntl;?(%OIfu?}ZroEVj
ze7Ps;bdR@EMT__(8hI4+Wf{=C&kv_nn-czx6MTBePnZa@NBmIgHXidH6of3}gT4Xo
z34hFf0yO1(`dH{x@D6leR`PQw7E;Bpy^mZq|Lk+9Jmsa106ybuXj9vBKJx<rFZc^7
zs8bDp`40$R@)`vUzT({rfP2kn(LnqSzu<ca-}3d%z*);*?1S7p-mFI(*71!kH2-+d
zU!x%P2fp6`v`IbR>N4;j`4!ljgLxuPQ87m$fo6o8g!}-IZWaO};FFV3T?4i)!k2rX
zvQ^003DRxC&WT{zE;I{*rnAs=2%5`9aG^P`tMF4f47mv#Y1fLo5WbM&-#dimv^md1
zICchzokG$+;CBgii_l)4Li-Z{dI_D!fyP@fpMc74q16Id@)P#0L)jj|P7&a}!p##%
z_6he#z!`sGKXC>KM+`8yU#Rjx5-1#_7vBNFdmI|?pwO<1famX!@b*_^4-2wGFcBme
z@#TstSeQohh!Eig#qUCes{>&7h!9E}pTmTQBasUi3ccZBgusjf_fcU~N4Om+jO~qF
zl(2%fVMGi2XFzyNXiA&jVg&9ua>s=NY>&c3I3fm)+T(;@X_#|Dm{*AGNn!kO<W33J
zp}@xr=P7`lAY{?x@3at70}m60kR=eF5w48~X_Bxu1j1xtVibgDg>6aDOc5qkqAXRo
zO_R4YVeV{jo)dQULoQudNU`Gc!Z2EkyI>a%Y=or@q1{n9by3jOBDo}F?}Ia!g?nMh
zWeQAVn7AUS|A2{WLJHl1*M&AuP<BJ;^b^|Yrl6!}^Oo@RD`;j5`>e2(BQ&OUk=sIB
z+Mk>&h&x~~Pmoa;oG<MA0Kgr=K5sCjcZJm3ND72d1Eht*+peIwC+wuyQIW9mDDcI?
zFE3Gx`@-G@P$>}<?kIa8w5mc`sc;@&)u|o|b+j(>NN9QznvaERFTheJ3>^WLC&Jtl
zP$?G{H%D285JD09N@1@32e4HM{_9YuYGEp^BtI1b<{|e?=s?MHVI+1{U~*nhd#q{%
z-#Xx53c1wxz7kSsjr_GRO#_xULO@TLe=Cfkg`-+w4SD}gV5tkP6MD}C;Jwi9BFa7p
zO(<AYFZ^P)!;O!E#~9T9lOPR8p`-YkOl%StyP}~si|c4c=_Kx@0o4|9{Yj{76=Nuj
zzD-<Cf&T4c+ic{V#gFL#xQKawg4<m@xd4D2qGbYd9^!5aj(Lg)X>{c!*3ul%TP!?F
z`!9Bj<-b73PdrGGhCSkVx}yH#Aliu>ASwfZ*e`1TL~>A+{R9(-#0$<acv$Sd2n`e>
zre8%aRJ`&WxFe!b2fGpCD(X^>in>?`BgM`%4vZ3;Qs6CGY)m1^W8ytbA?yeo%uawe
z$Hhi;Nn*v)Iq)=26c0i5gm^a?G$+Lkw90ZyTtv~HcrmOioJkPVj{tC5v>!u~C?2|m
zvNPhTSFn^M=F&E%WO2qx<j#ug9>eVvF{T_Usbcgvv~QX?q7hW==ft?fC`=cpjD+3u
z;_61oT@YW>l2L}35DqUcipRR4WiE*kyMVYXMtlqNnc{a8x4R-P{0gL3#YpPcv&6a_
za9<P4X;gPzjC%{R8{*U7;bFEod^mDB;@WSJ+!o(02X(Gp-0B8PdE(lhpvf1z*P^0#
zMAI+8-xaUYgr-0o(+DbsqC3rw?upVis1%9q>En}PangO*y)Sm?1hx{fsuF+);&ocH
zEEP{u@bjVQ&;z(fqH|wxJ{Ff809l#%9W97F5$!!`>t4CohL)cz#C|>?trXh{D6A6w
z_k*-rJevsNQ}Ov;0H29&_aS^PwxWRF3vmif1!}}!>23N_46?xBE76bc?$=@>z0KZ;
zi^c)|R{TJ2*NUsYfQRqIWvc+F6SM3zK6)>9qfP4{#9qEAtQVzN;6I8#Hbz5z5=W#W
z=P21JI<-k^OY0MxrQ$l2ZI#A-fN-0%>M2ZYmpth*IZNhc0JummX?fCB3h4%FH)-iN
zz`0AQv^{Hw^n4I<9@0XV#-BT-nN8u%E-7s%%zH|!{{Xj_q@dBAw{+=8AbceL1897u
zu@nc`ElsF|T|eoKACf&%I(<;FS1Q^FmVMHt;Sl;uVLHGAq!afb+%IKP`vyw$XMya1
zw2<B$2PH{rh`&kkz0in<rIquc6C^dKkwvgHWGHk(q@JH343);x;NystKubkoQrZ$E
z;nGtI5=TfLGWc{<a=8mYr1bt43`R*muLeuBR2v4BW77PQ5XMM8TCg0K!v6witmJ}j
z-L8t022q6ngv8-9C{?^Pqd9U3(j{8KIW3KT3DQKVB`v+2k+MoqrzGjo8qg$5Q8}=C
zR?0gDwiM|n+BKFc^`cF-Y0{K~fS;49o!~{fbaWTW&P!Li!@>pWYzP1u((Ud@>=&i7
z&Ols}b|#|mvh<OLSDDhc?cw(oX)4X?u1Y<KJ4>276`I$i5)S6COMx_Dydjl)z>Aww
zJ3U;xCB0mTBwLF0g1<RZ{$9XuOO79*nJZP(Cdxdi)(;iTms<9Ry*qX(;}7WEl@442
zX@PWRB$6U&Z4mq}ma6VU^}aN3E|OAd<6@Y9C=F|kvPaS&>e-%1d=!M`(#v4rDx~rB
za;ugUf56~VsUi`$XOc+kWi?W-@i6#Oy4A3DD7B}~;I(8QP2JWT>7x<Zx6;}OxL7Au
zzl7?0Y0oUse316h9-4ZoqXL#bO5e~x?2~j|1uq;mAI5@vlO`Yqxy_nx^lUq6qG_Ay
z7EK*33~tppZUSJN#{3dx+ci(9yK>en#uvUS7fp<vCf}|aa~%rZG%ac4nY(5seN3=J
zbD9F!9-8-`0l!nzZ4%gaX?_WUqn?@}6zuiV1XGm3TQdP){Hc62p7W6SYI14Dwp-I=
z6<GW<%_yk7M{}4y*x0LasYW~P)1>30OO?N7$x%CW0yGb30=8dM83Jjb=H!=f@qlI*
zy?G95*3-Q8kY*E2^$u%N9U%<T9H4-Cu;xP*G($9oF5nK;3~K}rk7(xBqDo<!Yzj7n
zYwBsEWQ3-kVsl3|=LSM0QuApX08yH2J!t+Ht-1XUs>d{gXm?nwrcDV7<1_~9bWdn9
zN5f#e<_K-CO3(}<pH6EYP^X!w>8t_njK-7*%_Pn63~(oFvOY)ISxvjH@FGR?iy637
z&6Ks^Ow(-s2*5c_(ibq4t~rOGmtA#UQ%ha=1<g_qR3<~?M>o_(&6wUuE@|E#MRHlQ
zhL*N7HREX?(-qCYkEqjCO?4Ak%F;Zi<)CXCv<RLG&BLi6yP^3!8e}&$x_0pCmZmpt
zYRcAF1|rGPq#i@rZB4i%H0`;XP$yiqJdIB%X!14HogppI++7OpLQN^%SNAl{X@#vw
zvq1%6u|_`=n)fyB&Lb(+%%;xZp=LuvAXhUh17uG%>1)tV&oo_0_*~;hudx@JUnwG1
zqv7bAke8a>gOGb=*UX{?&DWZsCuqbs8fzQW;;kn0H+WI2d140eohFCEFm;-VYmj@d
z`9zbf51Q{*BB|H(=!fK^W=#>wK51sw!n~u_iF&<F+RRO`v{^f17@Tp^4xqT|7HuhA
z*R9$%6kFM*wSSm^bi4L4g^``LcND<8XpOW(#Z`O$cL?3JJ6eEdhjtNd!S~R*U<j+)
zsXe+7D!a75(F5<PjU0+HFYRwDP$zHgZQ5Ywqiyj$T=Uf~p$Noo?H1bB>ZkST3443A
zOK25qulBzES4j712hs;A{@Tk;K@*^jp_bjRolJxOKy4-q(gRv{4*Wi-Jx3pe9MXP6
z8&D5xd(e{}r2U3IzzWtT(daHjTRa+oP_5fgxE-$5(pJw1ZPNqD9o2qc44)#k2b)4A
zO54S12O?U_Q~!EQ%hJp%M!SKAImfluL{u$S8`J_`#A(%|kUOCbW#IQo?H?8J;*_=(
z?XZp4?xgk51g%3`<W6gw(}Gu`_B{nm&uF_)Kb53y5&?L!wv?87&T3;Q6qce5aiQ^N
zs<xhD7HQfYePQ>U)<kQ>>Du=x$eq_t4T4V>v_n0B&(KbwY2-z%72n#cE@}5OD7&n^
zdIUAh)K+x^;EMJc-N#q8!QVrerJYO5eb=<TeZhHM>t}|eH?*fY_;gcyGg^V?@0M1*
z4xVOfzZeE-j<&Tc@VB)Ge}aizZF>qy<!RF?l8~<rr)>#$wWWW<ivn%$6JRUUJ{%4&
z?rB@%Ll9MwRz^dDVr`pF5Z>3`qL6TjHjs9hKG2?|DSWAR;ab>xsBMk?-zxhfZ4^z0
z%d}rNtd?j;H-@xadw3WS723;hKvSvBrT2D~)`y}K)!JMNU_R9jpe@+Xv{_#Q{#<*U
z!o@GNGpJ>1w9cP^d#ycAFXK1bjgd&+YAXv-R;yjS6>h)N%II^>I=i+PZF+mJ?LHcQ
zf6(6U3t+u=jR#0SYTwR5?LTRK!jU-Y{-9=a(w(G_2e;@>sNmC9-PtVI-KIM$L$X~L
z>IN2P-50ci>7v_L0Gz8XbT+Ewrt7bPio4E6OAI@7jUu7qp|i))h}Bcqk|vd2y1(Lq
z_tyQf5<dCp?iIm=uWn^yRC~8B;|7F&y05aKvPXAfGQ8NU+e#l+@6%1Bj@4hcq#k4e
zIu^g(q1vyT><EK_I-g1yJfQoW_Ng4y#m<A>L%N;R7Ke3f?KD&k((%{|rwZ1sqq`+U
z7e!I_P~EzA&^e-uJ^)~tuCFuL!gbDHLo-5GOn{?0-CS6T)QuYfyHUC~0Z@t7-K2Ip
zrh8HgmKa^aPFOgun_CY@V|Dek`Vyy$rH@=s==zn@`|qS~l?3T2U7!~b@w&h1{z%Y$
zu^Z-3>o)!f(nQ_)QE=_dKR%t+y`s(}MfdXuaHr~4(L^XsSMf7)=XAGdIGC<GNqf4_
z>;Bvh>I*v0!7!Ae+h~J@OS*}3L3UX;y}b<2U#4z4b)Hvrft7ITsxB%Vz${(c@1S~J
zH(>;FH*}v|(Fiwnk7=R%mTn_`G?}eyy8)JRbl=khkf&RE3XbOM)^~>&cXZzEA-t;_
z*&KiZoqQ@Z3w6(ipt<hpvf2P%r2DfwjX#TZ9<)k!U-#W?cv_<CMQdpfbZ3%)DAoP^
z7;F!9yDPx`NcUs}G#~3W(fgoGcX21UpXk=piekC$QX$GJbZK-6D|MTzQKc$fd?UcC
zbxmoD?^E6D)yO^5^{N2ixo!}xTi9RdzN~>$Z*<q>aO$nDGX>9Tb$zQKe5b4W0y=fN
zY0bg*UU%+qlzq@yv%prb>p`C%f7DIviQFe$O9D9RuhB;5P5R+2QMOrMk&ZGaeJ{F?
zx9F7*A>6L-L33GWy?7P?7rWknAyQZUc#6un>A!jp7v1$kXh^X`?^Xe!hyEl5DR$~D
zsc0ZC{WqiGjJN)G`fAcg|LHa=<Ex)Tt7E(Mb16LTr~mp(aPHAxYy*|O`p?{9aG(C`
zN#OL?hmqX?{n!d5`}Ow5v;c5W-+`7R4(T&FNDu1=M*tC||LF;G!TR2(kc8;>>TwN1
z^=67S9?{28JR?k>cL)Z<^(V>!kI=t=3*k}y$2X`%wEk2+G>_@OxrJPee&r~r9M^xb
z9DrE;BI>o`^dsyHn&yOlA}za|)W?j6!>9C*@Ov?;c>Us@&`HqeQ8#;9UqpLP6ZOvp
zBxm$5AAmbaKWY?wO3`0VKrU5(Bn1tera$Zm@6YK~%aBXg2diNIynf?vuzNw@<ZDo8
z=$p{j+!ysX@tZ7o0Q8S(G4zW5C@lqD)sLY^ElYp+A%xfTtr0g@UDpqw;K~hsmq}=g
zoBD&}VfU7PG0n)c_1Uxro1@?V3c}m^g+VZpuWvpRfIIs8*-*Kw|48ed1^Snr058;+
zQ5)XVulbwy9~SBB8^%@onGz~`UqAjmfF*h*ttdUvBRq!ZKtFC3XddeySs^Ubce()l
z6Mg%00F>*ywnABjJ~js2mHHkkRJ2MTUJqQg{;M$Lp6aK!LOq}9r_&zl=lXAFq3nge
zx0d2BHTo_^@cX5H-y(3o(tmal+;8=l98il|y`JWA@ASRK!cv|7Of1;m>$fT){GcCp
z0l9kpTY8y))c2qv&?mj_C~}((Q)%GnWO%S1Dq9S0Em5}B(1GTE+YAeQAlz>Fh2{Wu
zXG7B`D0DGcyCHEkd`?3dH$yxHPTdXS4G4D_bhPbqmtlT?ka`+MN5g$DLu(p{c^h8R
zo&z64Gnxqb8Um*Pu-lMBi|~GiX>m~5V~9=xe6Qj1?=Zj5@FWl{{)St*Pzkgf7SQK!
z2Mjyj0C><ao8m8r4D)Hd^RVGsDK2b~p*1a01RJucokI-s=otw$w4==lM+^^Xr6SDW
z{uIp>Zs>dj1|toL@eoECGK(OLHq57Y#W6#b7pP+lhHFqcZg@yb?6C&BJMC|aGqiDp
zQzr}y4xwuChV3*4Nia;Kpw4N-l}VsUG)VV>KVx`BzZa2YxSWGrvcd5gxX&8o3js(m
zjLZags$uB@Bx#1bDyW<@9BG(!8=8I#mJCCut4J;y8Z|>*E*Wa=onY{?;mqGiG7U8@
zD7<3mMVl0^8mgPYwJgK@Q80MTu#UdZzHSKa1K|xr3pq5i4V}}F%Q5^(3;wqaqsq}F
zxrUi7k;^mWw1XG<hT#-Xzhn4uDGc5<{N@I-0>g+oP$@K&j-~PEJwxXmpeZtJq%RCg
z3@JJ|^T6OqYkZ}Kd<O_08t!@l_{dO38{!@tIvW5eGxVpf|B1nY_Vtt--oA&h%8)r0
zO;T-GMANvZ1|#(z&kQ@igvxWnm-O|_3xnl5u+$g|GzvU_FAe8*0P)HYcLa#nhIm@?
zeq+d>t$S|`8>ohLh9rulzc<(yqGdi9T5Lsg*Bk!AubQbo8s3Zo_b0=6S^;x3-lykh
zlQFjv!p%m8uB(%=ej=*0#aJbxY^$*+ja^)fpZ!SlKUd>k9_HPQTPeElZhVvryE}|Y
zA5eP_W1b!+JdKqU3GgzyF9NBz@%s)?@i88wFGqZh<EdxcZFCQV(9bCK2H76t=>^c-
zYuw!t@O{S9(_q)%xcLS+1B^;~aP}Mb(n6R$(3nHL!2#n(ibEbWHi-hwA>-itAU$k+
zL<83#W26%89Bh1h1Gy06HhQ0g8q;V7bi_F1EC6A~uW64`xKT!1z$1*UvQT!^c#oDL
zB8?^kgi*$MqkxMx-laM8G2;)kCppG$yf7TT9XI|(!S-0=R(fN`8L!O-{)F+21W!*I
zowUH8GEN=>M7(kR1Jo(O_@+I|P8$uhy(7_Buo=}pW0YwBV3M&PO_`F7t7xuu*4XV!
zkfj)lDPoywTu3V%X-4lKVd$LEer^zS(v3D+ayxHKrdiSj;}=>8GmOV4fcv8Hn;ytr
zGJd}j+?S2@&4JG}#;*n7ig9BG%B~uHsWZtk1|CLzuNmD(gXOw0WD`u>Fb2{h%1z@N
ziU-~@9%uuWY@>EE%5sda?KBCvZOpj~OS#5}`vA-{uC_s#Z|oNc;2mReJaTu9`=}Et
zFm|D(@<QWS`uTx-#<}#`E;632g-Wq;=YHhw8zXMQnG$1{Z=v$QSXuyFsqyl+P<d#)
z@eG`gj10Yg9~)=yrwu!0Muv8tR2WO9LABE8+!ZZbWelWc_-dnqHvB&|Mp6{$nened
zNS+&?C7{|bjBVAx)fg9cMx9<7LyaJNWvn5$UmO2OhQT++cxvvq#?G`Sxz;GBjpXl)
zbu@UWGv4>4{lD*xFGs@Q2O~bo!&7A}UI*@v#(px`{bcM?h59<0;x)K<n@pQ1TDIA=
zn!apsGA$5Lw#C$U6L4EiFKIZq&2*JP*>+PWiY_{vdfx+!i%CvBldI`+A>eMN?!(}P
zyD6|eegC(^)Qt9Cc$i#P0l(Aa@Di%KOtsYNo~Ffp;Hj6%mwr0K+mzE4LLbvT8m9P~
zmZibcZqpGW^)of4LFpdTVT!ixHI1W5-9FQ2wDsKIlqA5z0Fx(mF#AoO8=w+sde<5(
z_5&u_JER9q-%v+$$P`9<i4L23c_9~M>Q40yHhp#&_z=_P<!I+n)0TtC9WgbguS>#A
zQOyAlH!U52B*N5$KCL@y3Zy4B(zGldxhT{2UT`hi<h=!C$4r~+Q5J&@vuK&)cGIoN
z@HEzRofco?OxsqYEl!vMYruWdG>dM_Qzrg8@bRXO{xFeX>P10{)22rOC`&Zio&kQw
zw2JnCCYcUPU`aNm82~?PDx#QqiYfapaH*zLx@FT%XCERtZ>n&IYZpxRWwfC@!&FRD
z#fzqjA@J>z>HHYvE}KGV=Srq2S^)PIlaam?ziO)d9Z8nyrw!n~W{PbNFRq(bq$793
zB;5i0rYZ3bxNn(KX)2v<8c*S_98+l!TJ5%}D~0oOO)f2v%QLC%6QPrDVtPR5j;RNY
z5bm1t>yaxkneM=gLep+~ao#hnqE)UUlPi4+SZo?Q7P<Q-X$=gPm`+VV?t#f&0q#=M
zNgLn~P4(sQ>5(aWIxIaleVPX9GLv5$a6U0<Xg5o_DgLG%Y!#*!BLS>5{YJaes!SoY
z6{6bYu@||gramvA`pon`23|ZjZSMl^7pBfeG(wFjz9US$G_9qNQ(l==v>g80G%y6o
z8`Ft62;Z8f(|3BcCWqEY-kI`fDqd%DY73S3rv7@0zkDz)Is*6WO{Ydc=c8#b4e39j
z5s-5<Pq_&bo6Kia@M5z$Cka3&^Bmd-w#B?A0l2N^W6Pkj&7AHImF?z@G;wn_FQ*Z<
zi}^)&u(+BJ(<Tu&^CS9Y8h3NI&S2SLzI2?{-#yID4uWQ<xe@IN+GVck3WTS*_!QW@
z%&W&j)!W?dFR=NTkGw~jule>bNOqg&(WX;BvzEr&d(2ChL36KpiVK=Dz%1N?hx^SV
zo1-ky{Dp|J1LpIzbMm0sLOXj7nM=bVv>!Hir~!A7Ib}Uu3^rTV!;28}CK24B=87@!
z;)r=1MIge=U1$$QxY=V3fDz^|Xn=6kY^If&NVAS+no;Hj6ljVz|D256F|&Ye{i+!A
zX?iCgH#eec$C|hP0t<2GNDA<tu$%v&k?u)zM_ThbWqv`;7H|HE78erC`(2ToHv4vh
zYN9!X)(Fm+2T^oB$^0jWB-#9}2FY3T&O#(9=FKOdnQC4`5!y8KwNJ2g&OF5d7Sheu
ztspyZ-uwod7tAfGgUT@5TXu(U7tQ9zKwL5>AI1f`Y}Qi<J=46D;t^NOy#i3DtL7v9
zU_Q(2POG)o%)RG<=DPXlQqbHm2S+2hX|APd{w?!tS_sQFhvh&s$6VABHM?!Dqn;_(
zeDE^L^2|A<$mN^cV*Z5(&wP}o>vzqYX2F>P^U~K47Mf?%Wapl_i0-l?^Iw5*t=RmY
zM)vp3%M37IVlF5{*#q<M8AwXa)+2EAp*fdgQIE_~Q=$3TJesz#l$l4Q;@Uki*W3VS
zx%oP+tyh@SE9w1LX&y_T$W@uM=vSJm&HFn6@zgx93aZb{j*Fo3-295>_b<$UX+cwC
zE~i`mjk%}~%HEnM4+gx}?CgWwJ9Byh%IeIe70`Td7JNbW!908b4Az@>wMXuw`4xQ;
z@yYyEH+udYEs1%k%qGjZU*Y#=i$4v*oh&;&k=tS^qKV&D%a0VB*=FfPyI8kd&OV1T
z&X#rKP;D1WFWPP4YH_;=f88wC=_gs-Exj;tRPC_rq2Chnu(%Z=x6>lf7K&Y#8RU$o
z#g0`QyUNRwN3SJsOFs&w`B=jDqR`iJC<o?uTY5$y@v}UjW$itdAwR&<Udya0(A;N9
zry!xfr4`-X0hVlfM)q6wP|P9FGWir#4p?s8MMV!<=D4ElkmX1)$PQa_=@|*K9H)@G
zJ=nrf-yLFcq&+gBmY&z3dc=|)24R>bsuDEemSas|DZ(;=zM?y7X&V8RNK4acpoy|1
z(Wo%mA}d33%;HE_GR88uGm_($M%&>`ti@3UyK$CH6CgZcF)5&V(&9lOnp1X54vlEy
zEx(=zTY^R24LYYSvuR&rqNUj^_;kinydEk^mS%l{NVaTV3jA5ib&Bw&SVkoSkZOr+
z57*KxYgeP}oMl}!0O^)4wCm`+<+T+o7c4s{x}IUVLVJxbTAtH)g_kV$WfT~{Y}pfn
zYmjNVL5p2iES|LbdDSvB5Qr>G6AG_iv+Sa2)pbkZWEi|*5oxG-(=uTwgtsi`PeUc!
z(vQAj$gy}uq4928WD1n!TfDqs>5gS|1{&e6<%$G&f#r)kC@Zv_vb(_iJ<Il4kQP}K
zG_feQc+h=y-_n06fF+i9w2ke7WzC=Psnn7{F`<VRr^UcMvSjy!rN@?%fxwknB)avU
zSe_Agxh1F{$|@}F=w7e1w046^mF4<L;HoX}r-AILrRWMhf6pvN`k9pHmbxQAys*>-
zf~LljK{M-@7AFR5uPoAd(7d)hpzRrNEN&-&e`{e5!^2w3RayslXVLrsvN}sUdJny~
z<Oaa)50?Bv5Y}5>&|Uq}@^Bq+pDe9u3gKuS(wO%DZ?cXbg8FW@Hu(bvovgJM7~Epb
zc?;F8)<05Vcbl~r2TR+nd9L7gw)TAjZWrs{w8PHT%FsHGn>F1Z-n(0esDayIRj-Do
zhxJnd?C!KqwnJr?wObt$PwU<DAoH@0z<b25^0tmx2OS^lSPDe=TFd>wz1wOl0k@wu
z=nTy7vEHYiZLd{9^WA;cX(dqcx2~svLV)#dH(1(lT|nJzpw+_#CJtD8QV8y#b;T*b
z4_QB>`P*UZ^Kbxytj9h;CD=NeLQ?h+>$TTNL#=h4Vd9AO=qKoeSx3?`Z@6^;bx9G{
ziH)Ih)Y@(Ya*<Z11u7b4T}7*7(bh)wU^`|#HxGaqYcS34k6U*oLnYSw7kzgVXZ`Ic
zgeR=V7SKFt9YrzkQ&#nBsKnc?e^V?v(aO=t<cxI`#p9E#qwk<F*&0G!(pl?TEs_+g
znyy-^RZau+G;1Bbe$QF0P2oklwdoin=dHCicyYmcqzB*`)?O4Sx@g^a8@Nl>lnQu%
z**ffV<T9<1PH34cR_s3j_f_lBX~<?-m(!lQYu46hpnBbUk0Sp!tX03lwVPI_btt=K
z?L&Kiv#m9aU_Qs%XD!NZTfe7Ghq=}%w}8vD_I(VpeCx&mpuS`MYcBwItsiI}R$$%e
zj<P~)t7N!#&zf%cg^40-pOyd?TW4m1=DyW$4%(~4`XzlT@xbac4|YqfSUtgmXYER}
z$w$`wzoGKjx{N0MW!5*7fO}%~p8-I*b^3E~R#>mnWU|tFnnHI~)?fiiwe@)n08g#k
zDQf)8DqBMP&z@W3UjgyL+O-^r8tbb@XrY(Z5j2~8Wqp(l($`iwbsul6Z`z?2Z><G1
zKd7}9_kc6+tY2J#`8sPEZR>h(ZI=xbAFRn1P}f_%iox>Hnz|b*pRDB+Om(!4`vYa0
zY<b_&_Ya$G>&am!o7oD|Ew-mR6mGRmrvb(`+n-Z`*lzPW3ro(n-*aK!#ip2xoU5&K
z9Q<{&<+VcMZks+ExE;1^3NU-vw$OZNr!6K2fL*o;g`oDd?fZZ-FI#aM%Din_%t`Gk
zADg}s=6!9QA3(a>w&n$LeztcVU}BH0<v`%~+J+>;M1bw<gQ&%Ro2Lo6K--M2035L0
zsfMEmZ8zyjJ!EsGK*C|$1lnd1WHbB>yTP{0;UEjK4JFP{TXHa1j@WvtfwPC%7HvXv
zhucyof-S;!jkeDnwRO&iiAdWx9<3K;d%O}!w5^C{UdL=*u7f7VcE${v<F=;s{aLK-
zYwBj>Y@2=H?+II~Gm?|G>SO>;**4_^9&a0<hM@%8TAH(*wz*T(D$#ChI}4W1*jmye
zPLi#WCv=i+-Duh7tgW>ixfEN{N2sLQ_$5fvY{B2d(m9(`B)mws>Hh-myv>`sv<o)X
z1XMf2c5(phUbOX!McF0WPoBtKwnhF1l}y_@3esP(&7%D_S8aA}IHXy&aoAg^x@Ifb
z2JY*&$%u@pZrIxQg%>w%+vztqZrKiPL3?G}hP8l+9NXHxD7$S-zYajI?Fw~XdA5bV
zP|3HorfT1@b))#_UEB5N@S?z0HwP99ZHi0)?%4`r057t2wuiucv904UWbfMwU%;sn
zTPCfIJg_aJA0Q~TZ9NXeLz|7dtw%Of7Rnymmdry^W=kcuC$>p6O(?fD*TO`FE#Vn(
zm9`eq;H<JONe8alHmfTPJ+<`?L)kOi<}JuQx4D+m{O^VB3_U<KwqEpW3NLN`G_rqX
zOQm4_Yg@Py$s1d~946k{&JTl!wYFnF!0tO+hhYHJ*$h1acyIfIhfg1EQFD>|WK+|o
zPDh86pTWW=hk!W1H#-cZU2skgNuOYEi$faje>`dq8VZ+fbGSe&2iqO;eg(qW!A8qW
zE)FYx0m9Y6EfXqk4((sUpu5AY2jJe}u)qN-9uB`!WNN3w{C+U8%c0HBQ1Nu|`5s<)
zIlLNx`g%K*(ul;zp_4yyz7E@Ig1g&cB}eNIeh!KM$I+F?Wm!CNvoy=nN~`z2@B1RN
zvNAQTOtUo84mC})UuD^0X88gFa)TUl%B`Xxq9O=_fPmbBAcq`sAA%srDRTV2(_izM
z-I?#qF7LC??#%4NmoON}*iXBMAjWgF84hMd@-gfX#%)?=LmAti1Lz5cj9y@2jB|8Y
z31`gE=P@D}&%Y17NJee}P@)(QsWKs&p{B~O7)H=OkdurJa)_K_$f;1^G-Dy1Fk=}}
zRB2{C!-!f8jkAnx^z)2k9HC_^p3y`P=Q&1s5l8~#Dn-Q3GxFxcr$okgRA7675%U}L
zE;1S-(0GZl#S!zA#HcjDi_45B9nhD|c!Cz86h;L_yRR_*cMxEyj1Oj@p2lFU1b5ZS
z2n_~JXKecjB!e+bC&p`xQ*@NbWbAzbqFIa==u;!vjIZKh={h5-93JK{@_vGeT*lXI
z^yM+y+%Uo$jIczQ&u56{1EqiwrvXYK<8ckl7co3M(OAs*uoZ?%7@R18l`^coG~SyG
z1MQ^B7)vOwSI$WC26u~5`84_}7%h{SuS&+F1L(WW2tNtMD#kHySgK~ooj__BOV)$b
zGD2uGdx!A^y`$<FGyXuSXLMA+d;{a$Nq{vn9&Ch9&5VQb@S=tBmQ{{Xv@+(?&aaK(
zK%ua9hD{3;I~b?{$D_vhAFW<pjI~rl*v-hJ*XTXQG;QL07)zSL^)fE+girSw)%(Ep
zG4}Ytd_QB^Yfyi{*wX^L1B|m<ATr2U?Tf~TjK*ES9Ad;xQT}h3u{;yAH^L~O-_9r_
zgYJurG3sA}Gvkcc>1OOB#*eKa6O7>((D#_(MMvsM#(7_mDMq+E3{EpfLm)E4(9(<A
zmdW@9n0Cxqih9{I-RP4YN0>+HDB!^Sa|(Kn%)lXf|2Z)qmtbf|nQh16n=_NW7o9H5
zZB#el%8W{YK{w__+9SF%_fV3}gZVnu3wScce*)Btx$${$-b}^;kYmj6>ACk|zE4pR
zUuFt@F3^wp^I<^yGymBN?l|+-2S5p6zTY(q&tD+(C>MSQG5!94MliFY4WJ>+`cGgt
zlv(~a?4Dq*rRff1?oR@CICF;#3K7iI32>3jKYl@96m#9LFdxl)lRlsm!z_Ib+(~9!
zI51B!-E1)zr<q4e02a$!M61>rrg1-r^(-@jO8VlM5&Iw-&s@6)*yorpt_De99zPEg
z=b4r-;C>?WpR)kHz>M92#*570M*zLVRDTD5lbAwJ%;9CGxe1`jOm|Arr!Wg^(07IT
zZ8^A9rhN<g(wJU(AXk}%573xyWtxA3-3;cRX#l;(JWLgZnapk_e7er8qhw?bQ&t4O
zbD100LnM#6wFDwJnBRNBnSACK6v{4OdeU=W$b5&QnMKUMiXd6cR64`M66UuZn95RS
zFl8ujGHdQap^W(trM1eL)?^V{Z!!O%3~2?kw*+=8ncC+-ZZn^!N4$#J?gS63nXxVq
zsbRi<9oV(ZZB*oShq-{_0(HzxDpaj!F7klC4a|zyAkxTW(1zwNlVbyvCg!44NH#Nn
zz6h`urtMaYzLnW%rNmSl^D5QNwKJ1xgWtj2Nk^_uCXe#|UCiiDK)RVFR9<zD`BD}9
z?qQyzkZ>>a-A<7E%sH=u^f8ZIhe$s&{V2Ex%tLgQYk+xxzIQapG;V>Rhs+<x;LH%S
zg5ILTOxp>{|BWzx%wR{E>ZRx$W44#TnQ`V$(tpHUsfNJ`=9zFvK4!*=F~UivgBGKh
zViwzgn`Ul)5e8?Nm*@;&%gUj9CU&eFR7GRYI`kc;`v_|_ow^-ZPPA`zWYw$$abo?`
zN8evR%6g7=56-OKZn*Elil>j{yRxdOT+ofR<SIbjS<7~!&x7SbL1a(XoAi|$FP1&M
zIlNi(-+-gXSQp;{=fm2&9U{K0UH^ddV=1W=$)Dv)X}sgC?dh0=09F9SUjkW+?VrN)
z7sOgX|J5m&_4->-3}Nl~5nL#%b1ldT)?JF^g|Wm)Rm=%ztqubh!3v;vMI@`v4L-%N
z?$DZjlI2eO{8OxZk>F0VJ`RA}v8;B=)SqEpW5b!VtjA`E#IbH<pf8^F6x9G)&#~I+
z7o5O4><RWftKeVAB(mQ65|em=m7NEJ7g?Xf(>a$|Ov=S1v7Vtc#AVjLPQWCy%D+cr
z3Tw6s&Rk(Fz6+AdYNT9D8Y{RKU{_h|s3I_(C7@hP2CHZ>^scd@*MMYNStU}qn8k{#
z#hhfb7E_J(b(RZFVh(HGG`L)rhECmitc`Avyum7_cSSyH<tH#vz*6LbD`dSJ0_-Bz
z@3X-bv#!vpRl?HJLs`oDrx*jg$(nZt3T3PT4WP?eiS+%fTP$nyLv&WKc2jz*l6B-2
zn7GYqqKrcoYnoo8)vU$0p;*H*(TlT|mGfU#j&+mby>+a>H$duHO`!m7U`^fuX=MFD
z`_{Xx3&+sc#JcB)iEU;DQ>LPYb%gF|wX*t#VYZE>xAuXyvjPHPse`rbGuZ89rFVdI
zu@=y&p_}z(B=qmGUZ+B=9@gh_Om{D9H@$1_v#`G5!DE@|WZloINQcM+7Rv%|fHm<9
zPzG7Q{tKTTvMh&TXo$7{Re%k%{Inn=tUnjf^Eb-U9S7(bYcC~+$63Ye!98NlP^@u+
z^`r;<e#{b6=wXt@a)QVd%XuwEG0i$`2lF$m3r9d~*|s#ncI>cB7_?`nU51Gx>^)oI
zlM}m{qM1k83+Mpm%&zx>f(!ebyY&3IvfB>;&5b?vJ1n`gyOu%GgFP<{20hsc<IwP8
zzxXCZyxFtqqSZ0>039lQ*iLlL_GO#sx%XqQ4uaeM?8TH5InI88KIIa?Zl$wbAX`S~
zp&<5IdTxW+Y`mi9gs^q%ss1dKE&UrZC)j(gf`qZ(rGnFNb|b~(BiP!vp%KX*q02T=
z?AWdFFq(anz6KP-UP@IwC)w8~pm2&^OsmIf_QFgk#IiNC7eB)eI|*mbvUh(5kvO*Y
zdyshc&wJtaIrbDC{jCY?>;FRWJo_Cwbtke9WnnNE*t}n0;v(BI59AWNFCNY$v48A>
z<Yo3DifSgabri8oVb{=W^a{I{_K2x$7X3)m*qI%Wyvm+E3QOtinqf3%u#K$%yT<;R
z{xF&BxwLQ1va(|*z-F_*+5o%P*?d~=a@em<!S7u5emZsMvA53x+70#wx<--DF5Lr|
z0`_&PBP(S4ErUoATSHaV#q4?Xh?lT`+7Fac_B&LraFe}<(k5l>AXgYHXFtmYcZ=Qi
z0Yoa;*6kEYuVjlU|96}HJAGiIiY@;VFxBj@|A9;m+xjN@YS|8yGPuL;qf>VsdxlOq
z_3S1YxCXY{2rM<SWonG~E<2qr&Ni`YsS3QAJ*ymC3%i=2TiKt}Gt$QPUInmrw!unM
z)4{gMhhjH-)n>HbV=p`c(!*vyL}M@eCe_{CXRliYFZ$R!=(1@)JD7rJ57=pQAu_=J
zeiJ5WkgePW?jbuW5eh@>cWy&un0;;&JRD)4>4k@*Y+t&+H^y$Fd;a6>MS*mve8gr`
z+H-;}-w2q;?4h-gnPi`*Ez}gdE(jviY$*ftJi~s<5oorYvMvxi&Z27gWY0;b)5Z}_
z)_ZWxf%E4xz;@*1O+&$n<2x6PM>*+RAmYr~mJi~>sa*|wt{nMVx_|4&d6Q1v?wlW2
z0L_E*<ZWnpau{^#_Tqd?%a%81gc2>sIES0znh$438XA2$HWfhg<MeUhj6cVZwy(!I
zuTUgBfOC@e>4BVCv}y%$UZkX8FlQD0<U=?~N8ws1XVWH%zntK>ego_<&fFx7KAbbS
z5{eO=W6wY)lCy?VSW%o~CYXrk>^cn+!zq`;-;<nvda6!wTAl;;X%5o|=3_Yvw?Xd=
zC-OSHILp~~6XxSM5(;m}b6Sr8`W(lfp3MZ#Zx!II=Q+oh!l^_~0>u+Aa5mGLa*;Fg
zB<x<|EO-Qx#QBOME|)pIfv}X!5xoRUDI8`gB(HEZR1A>H$-f1ZG|v3}P`Ju@gJQ_(
zoCTDz%iw%LN!x3jQyA}@OpeQP^ks2&&@z{8<p?R<b)C~Fhr>CX{a>Lqmy^baZ+V=}
z^p?26IYWEJe9qw}G!}7wX+&c&XEWVfD&g$%L1QULErj`-oR{pOUdGu|0<N5M`v;8v
z7Ux&mpHy%*`a`dhGeFnrZgbo_;YAh4nnTZTHRmH=n5f~rK@W8;N8N-m-QiTxuCk8f
zkb%B>&ay~oG;kKuLAQ|;PEW;M&d_Ht(Zmr11ErZGp-=O*aNgl!NUfZqNr1I+Y^i*$
zopXye{~a9tD)e=7j6cGeE>4D(hTYA1gSM0RI0xT{Z#|qdxv<pB30eS+`<!eB8v8h@
ze*vbS)4B|O4>+lGupi(A(_NB5&hptH4>{&2pbT+7q&?y==k1qZeuOjd6D*8!zDE3X
z&KT#$7Z4fed^I0nk2u0MD`X}(#k9kI%=vf{Fq0gS8N;69u-}8-X^y1|WQJq3L8C4A
zB_}A@aleUyf<5>9NAU0nS4d%M2X3Di>^gFn<w3-W`;R{qj&j#iTFaRmOffJQ?%_{C
zT)D}~XmsQH&!hSmcdoz=tOqw;hE7lJBpv#_xWCii$(w8I2AE^q0{X-Ha6ck{eYtaX
z!mb~8y$qA@&)pCX^T)X#WkNlGd$=B4AUC=T&IEB^?!|Nkb0cZf62dKW$0USuznuhk
zg6oV@BI}$m?&uA`gmeG>6eNQC<|AlCazC35OHte#XJI~?`!rP_#BlST!33S;E{H+j
zDQ?mh^quA|5rV{WU!<+|8SVqxRmO8;sAA<D*GlQB1g<xQZ_abwC?%T6eeX&1UEszR
zL(+PYyO0uam$+U1&`;vxh6Nrq?nMtMCUc|db(X@7{um-xxKB}%JC(bX{=H5b*ZLhq
zu5v5I7*jeoYac)}xJ?v8zQ!%0-AX1mWEb?ZxF69LCY!sY8PM0cqx8V$aMS2UNv@SU
zb_bn#T>r1Y-r(+{9DP3bi|65K0r#6GfEIGo@4-?LcMZk2i@6(qhlvvI(^Owk%5}(u
zrJG#mB7l~0zupbKa_;}8F;BO+KdlF;;7(Mdv65T$ES$N`z4;PI6?b+n^s2em$(5Le
z8t!@e-fb<{i4JggxastwujB5f*g-vaA^qeVxLYjfYvg`M#Zq^<p7%hSxc4@JG;>R+
zg1CkIQz{f%xuws;!#3{FUr=c0R&ImA4({6@!{1KstTPxy7xzU<iFR{ew$je;9`|1g
zzxHr5lVPcsyT1{l_qo5jLBEfiF$E9%xigefeZY;ZgUA4Pxf$FbH#8o@e#rgo11Jn}
zISsHh%#HgBA|u>F0iZ{@qu#JI#&x45be!AsE6hLQ;zNdb?zn}2QeNyaH>wTnB$r7=
zv{T$2*%-w%_i-xpXSg3yio=$dL*=%1JWs03v*+3V2A_`b76(GaffsfZoFnfWE{5&I
zd!N?)qr3wjgE;fFv|76GUM++LSKjfHP<P{H(Tl*7H`Gq`pI$r%x~A>T``jHc$9O|3
zDEja!M=(NPUNObc{CLkCg@!+Gnyw=p=W)LSOaSi>I&uZ_is-_85O1pzV+rQz=l~YN
zTet^cp*#yE-cRthJc39VujX5D;k+ISp+)ez5ckCQCwOIa7LVc`q!?N>@7NV6#_(QW
z4ULn$2Nb+M#gkJc?ldpI1AVc)#}vFi!xMcBw6nYhT07%-D|W-}cwUePP|opwyARhA
zc;k!V?|B}J>f;l60{W2R1)h64Ffa1@W&_iDiTC>{=qK?Cy?}k0x09BwWM2C^m`~yL
z7yx>OH?ILAsk}>6Hk-za=>Yas-kEwdrt_i$U?PL}A%*^~@n)}urA*$ReNfNhb+1KZ
zHt+gE=w0WfHiP8w&QOdbm*-16w>&FvA;lGL@N!cz&-py@4*)IT+0ues$os_sE*A0H
zD9BjM`|WpdCA@eF=9cpGub}ZJZ<xwQ%Xo2h&@1Qdp*-9zo@Wr$D|m%;)2WijqDakc
zUc`KeRPmghAyUoD62N>7&swwzGPS(Q+338(o7;u)*71tziheyW>M%qbc=xDKp^=vw
z0g=1B$*;gQ@kZ8Q*v-89F{rojI4Zc-%8R2jbQ`bgF4Wt3?=Odm4xTsxBAvXglq&Dy
zz3Pma>E@X!pmvY9!}<(ldU)IEMoceH{}o#A^Fk;i)W`d<9)1t-V&l;`$P54P9mo5e
zW_E~|{upS(yzLZ!8R5A{L4A~GN5yPoJSVC@8|N*cfaxP%X8_0q?@QX+KIZ+t0rn<&
zah)Jjyk~y1!o)Oh+y6jjc>c>FW6PK0D(M_Me&1q@!k)j5O45(;?^giEfp574MMr)(
zZI7Jzn+u_El>hFZu<Oj<O@V0_{#X<GT={Ntpt$j$rH>D~^9v~5<H5g1*JwTYmnabL
z#edt2?%#UzKcf)bF}{g5o<97?R0ZzK&wm?ee*7Tv(4T*q7MkPy?NmS(z+Xlg-9Ub*
z9(_Ul0m>=_^VM|0IfVZQJ=>xDWi+G{{M%fRFus+x)Zu(vT7o0^1Ixfg@=I3H|DTEC
zk5HN_n*T1H=wtXcR4#FnKi~)xr}(eXvUQrjffD|){Jk`$GyJ?_IC_>J@FhHq<J(cC
zXgvSxewaVU|5XhxfnTFU-+8{CQVogxVp}L&;9oKV<s$zVDy_N1f147O)+B!K0=RgY
z|NSD^P3Hf70{SWZ2WMgF3jd>Z@FJBTu7ek8{E(NSah2ct2P~!Y&ro_RgMWys^sn*l
zD0-C1KZP^xoGkt<+Kp!OU)v5#*ZKXqP|x8H@5DHB`Co(rI*(r+43QgF{tGM6na@x8
z9Hf9BK!q8F{1~c4EaJ~u1MFh{g*)gg;n&82E9Dpb0uwj+sXD-v@pr5Rso+2Q3vO5P
z*FOz|xA{XJ7*Z9#HwJpu{B?Ast>G`;i@sX^X)Yx1@HcQk>iE_zbXKe9$55431K&*L
z<Bfd3d$4qu{~5(yoA{DnAkxeqdI#>e@V9D!-O69`-(5<+-J9rZ=hxEG(7})W1|psO
z$z<qt@l}*+@8)l%nEO5cBHAVO@D~JOntS=Sw&=Uhf8I(v-9COx6TIo?dxZk~0e`C%
z8Uy_Ho$z9iKa~ZMhy2j3=o{jH`4nJ=`4{PTF~Zl7_oI9-s>vDS&!X+dINyN^C?D}x
z{f+TX@VBi2^kaSnMNudDF$yS5@s*TNn&wwcSV3p_zCQxZR`4PPvFrpr7eMR<g`0tP
zL~xCgnGS-g-@rKv26n&;CxPrmC>#}JDbeRFc=Hc<=pqP@2bilMjVjgL1PjyA=Pt<2
z0OuiS7DB;Ou<jhpdkOwWr)_V+^GE6VJ0_^5N`4=~Kt42l1wUtj^AkMy6O-UCFfV~K
z#|7_Ft}Q^Yik9#|fzzAl3ldDb047*4NSmb)!Q`jt3l#)^0`7#soeJ{91g&2}GF<RC
z9hV~nzOCRQ1&<Q}7A07RP_%VUw18oP!5G0C4Ujo0_<Iiqb4u_`8?a9c<e6xU6^v4J
z@r>YO`b5Q9!GRcH#|gfrBS^ep)8{}tC-{zb<_QAVcQH@r1!)ulPZYGLqVIy>Zwfml
z2@a+~{j$K8E;uF&gmoa+6oH<W;46Y|itwficF_};CRjlsxT^vW97E@%3)o9RG6eb_
zkZXeD>oAH;!T&D7e3l>}8VcEhvlQXIE_m?*#*!moQ`R+C@HK@1@&q~0!;2e&WIAZ(
z3vN&tr9ja0GDx9SaL5jwMS?;~trQCc2Z3E8*h{D9Qo)m7q3@=kii%9i1SLXn<$?w}
ze%=xcj03wuz#0ckrQoIrgSjmjn*^y699aVM)q-65$=3*M_ha<6_!9#2j$j+T8|ws_
z6q~6RSl^?^sX<V19;8tqrOotRLD32fv`MhQA85@2k4@lO1b;ZgQmbIx8K7+f852IW
z3wjDbIs~t+gkGnhsTd+%f|I`hyIWx7!0tW4mxB=L5iF#zQ?Fp|JoMcc@afpuCwR-c
z0%-k$Lytio2>R~A(tzMBJ?Vpjr9%LHC=k65hld2e+XH)8utEXF5rLKzMg^zi(KjYY
zJOfMPg6tGvKN5KS05Tz1a02A9U^A8EO$uu1-qMsHgkopY0?`{7?u_8wQY&C=g$;C-
z(@wbk7SQa4@6smxi12y(133tF6bp6~+9rcI2_G%QV2%n;<%2j21E^lWMHn;&P*-83
z6`Y$e*a$s$;kh|5=po#^8epEnDOwu5gwd4u@D^SVg~%~s)=w0F@e%%y-mShu!5%nu
zTv&4iT!4^AYj2=X7lOthq2Dc-2o?@f8Zkt8{2cT{g}Z2PdP10Pg55BoT!KM_3#;8h
zB7{5oU@%hnFXa}Zgi%zr7cDHNTyu<YkdERfg@<h@{&GtA@_G#IwD2Vg+Qka@P)hWS
zP#6xGv%<k1z{Cj~wt&P7vv$FmbHXRT1x$iab{dm#UU-Z4Rf)nn+OS>_{zYr&Md2MP
zg1scP{RnzV!c7a|{bk`_4!}$nuHFiT6ya<-T3W9N_s;{HDx50?cAC&{3@}%P<ug!B
z7lu(dGDCQXf}7Wbk<^$eH0*<7mQZycXxYNIs95;A@G~1YlOv3!y5L-)2ZiqPgh}0i
zz9CHA1}<M%|06^SgrSKrR4CL?_@~G!ocsm`i-j(fZz&OeO2w?DLd7o3*G*xP7y8PC
z&r>>~T-ZiAkz2wJS`jORfxkecQs_oEJZ=l;1;M8(Vf=jbRSW;2$Z(DDXL{||3YXJ9
z;f~PbGVIm~onL^3dZ9a2RW=B%gLGNEQRqjD-(6uEMJJntzflCSS$NeEc3XrIzk{?2
z;~N3mCR`zdV!QAQicEC~dnr5CDXgUIbeC|?eKd9poeqNB6S@h2(j#>I7q0aRb(;Zw
zU$}ZFoaqzp%SB(mu)w+o`VWMy6e}4J4kbfoP&h*=sE5MfBY+ta?jDBuVWH#q7|e)p
z2W>^hg)3>F@ksb>HOPc;KM#$Mg~L?bGAVqMPJC0s`3~@DT8L)@kD9Q&8pKxA=?L?7
zqH~eZvlqSg-|p^+XbY{j4x;Z;V9-%?j=uTjBpPeQALyv)*J1eNEIR++qbAxzflpV_
z(p6}56S2jBaTnFU4RsGuY#0<gMVq!k#7ktR3k2SxjCOc&O!R>dy!R1xP>qSN$nACX
z`HALzOW$Ae7p1Yl9vAiGKqf$xoDR@HQDOm{2@;Lb&LCK%rSN!&==c2?MW|?gJo-+E
z4p2c<n5dSDfWk%5*+7X9{qO-?ixkC_K`#m)h6WccGQAGW7|}&Ha3@8d(W-Syv<aaD
z{Qm*b&s0zqE9$rp_s@tHQ|aVcQE)N1IMK7TP{oTnGSPTW)Eb9@CWv166qe45EEfTq
zDB{o(dO_s(0%q-^=!LVuz9g!rd{&ZZtOfpF7VR%WW3p(|-|#6#WcM=EuZVh@0c}kc
zZKH%qn&_K-=)5Yry8(*nqJv}T%n)^(K(2{i8G%No=%y00mn9mZ+U{)8){lUFU6fr3
zpK?U&X8|Qwq+W}$<cZqmfZPy8Q1B~X^uJ7C7Kkp<k*QE*{0pQ=^oTAR7F$J=w(z?|
zG(`K9QqiAR0eVy9O@F5{k(Cmi<sxkw&~AxL+kjRfTKYZ|D@A81YJ6MNLL0FvQF=W@
zszo}wOi?4sJ_MiYL<i{YT`&6nPe?Y1O6b_zD9Y$X-(Asu9}KriWPM0QCe0!j8cd7m
z$t^J0D*Bq1yEf75XW&J<X!k;hbcpO}@#_@5M-N_?D2b-DTeK$;p!Y=4yV2Mq$~pms
zUeQOFF&Fnmue}PCK9TifxYjT7Q=#vHsQ7!>9S{xBZIeM!qID7UABy_ud@&^2Lu=@;
z=p|otj))dK0d7>3(gvT#L?6+?eq1D7i|KkKy6`4ICq%FR4baD;NQ#Y4iqaBca7wgc
zHJq6iwb0veM)WVGvu(wPC=h5T{)=wx*^B2U0PKiZokjJZ4&wJkfN>OS&Vq9izdQ(X
zRO~^)FK2NeMPppV%M&5uDo&z6lbg7JqN(m;=EvYX#O}0ed5V+R5b+Y*KM8~0;+x|z
zaZG%b-l9HYyEqKOSG=7r5&MZxQas*Y{LLY%zdkN5rHdW`;uI}h3>1G<1GFIVI{J$S
zi#O5*gb;BL-8c#rr_F-F6Jp&`aAD%N-iN_(@q-eGM2LSILt~`)>L9o%F_TuUXmLK}
zNn^wZPQ&g=@q?8Z%PH}E`pVsDaR4f1taD<;zwL(N88KIf&a>h>d^j8@K0pb}c<~lm
zt<Q<yYK5f)@v^%h=f!g=pqD8A@i3gZAl_#SOBcm6<k}^1CM`Qj;;Mfjd08AULSwS{
z=Ev|NMQorl_bcKRuftHPxa2lCYr1&dZdl3?+fqE^n)uo$_^V}#XJ3Y5mRNKfFxg_)
za**rdi0@%HN1S8_e{;p{XJ9E$9QilUZip-CH<vG7BL*oD4{ZV|6fca2i6Zd<G1QC2
z`K7=t5i6*6sZ<<C!I7I*aR!A4%f$O`!HaTnwku5B62BA=hbzP}EGSlru~);RCjMmt
z8dc)HyD(TSuB3&vMto!q^lHT>N9f%Vds1q%PQ36-NY;xDj_7L;*EIvBQM@b;eRst&
zKGd7U3w$8bEVd5Q&ap*2M2Y)W@jIWwnKp6kBan9STO%;hAwEy%i%zjOonpJhBUDe)
zEq;%7Quo9>TD5w_C2|a{S3E@TsQcm@S74$~y#7~U_KS1qTImC^s0_m%5Wh`vxk0ga
zBP=`=e`ECq_K>*!8z>HoZ3DoKh!;^TYE+yx0hlrI4|L=j7jIaEzDMHN0B{rHSCRnw
zSX_Gsjg#Wkr+_vk?wJPmwD<(YMrXu-Kf(xYB@PrDwUcZpgn4@j_Rx6nBsm{|bCBG4
zj<$@Bl69v*oFv)*Z7wC>tc8rTB$%%DyGRb_z=W&Bo2JA~vT!#P-6aLIrSOofx)0(h
z8Kk$8m!#GL;w|}_*1%(u!C%nlBT2mt&Q~&r0Te&U3c42VFL^c)vvypP_B7R>1xTEP
z7;m5?VGs@nNuHu#Qn19~XDEh9YUnCUnB-;xW<6X|N&h7#LekAgU!-L13osZZi5W*<
zwB&CN`eG!~t(b(9lFjpgc}gM)fXHddFIO>Zv69Q5qVJ64(P0=mD{0TC`|oj*&KKZm
zyrg&r<ecO^+SVmVJm~m(UXtAfm_*5!6jiw(d3Ob1E=s~F{&Gn&N`Z(Z$?!>#%Mvz4
z0FxzMbXrf5wBCZHE0V?>xRxqe!Gc1X<RvknuS)#-VJKbl2L2XvtQnH2Cis0#GW%I*
zWJ*fjf~72pBjq--C9CMveO*%M2)j8F))e$}CCd_^m?x>BE#D2v?>m5&FX{dZA_bCy
z|KcZ-pXhg7Bzb-bpo=AEDP>k7Ny>#nsl<akyeWAshF+Ofa<c-U<&qQG(6}X8as*yf
zNa}B)vr_WDBb>P{xfp{HRzVRW)skhi&{reb(F;;5dDR9ZydyC`1<*Q)fMT-sk{54+
zYmnr#;Zvieinio;C9}Q-bdzKOPTg~wC2V>pw@9qJDIwM>xkA6IHp%l8scn~B{v38Y
zBp=hMyHj%G1k86y-lc<Xw<NI%3il*J%9Hj;eqRfPUdh4=^xc>INd?e-5+NM}`z5{`
zFtP`dMU-9|ki75<8V4l-2S6T5=05?2A<0Q=D%>BIC=4($BDpRD8I{bVV&gGM{ty($
zC36LE?UAIl2aOYwpv~~<v1H|9z)VUORe?-N#;GpfR=Vi`%-c!(KY(lY(#_s5e?+RG
z;FW{a@DP%Y(q(iQb&|e8<@raY2`w}=&eE-PFmaKdvxTCow4n)JxJjSB1@rFGLK=*R
zbSo7UdrGyG+whX^=VA7|r6E+*c1)TW3`rm9pR^YFN}uClO8lg&sC>;|dYB>*$EC70
zKnajmQ;<GT`W%JHf~3oTp#T37EIsxPG(w~$6e|gpzI+}qC#0XdW7uKRx2fJITslNG
z5E0TQ2KpkUuY3y0D5;#Dk!a~B<YA2T0hP#{l)5g5<SA*HFECF_b(CI;m9C_X;~D8q
zx(;+!`T_0l<D}hJ>G_M7?x9onIq6PXwi2ZGq;T=P^aM?5qV$uEP`n^rd>hyorO#2e
z_mXsw_9sbFDFa?ymTsqGezLThF88HK<LE7VMaujHc2lL-4gn=ix<3#KSEbKT6-~M{
zW)I9~NE49+nq$2t{e3ScF;lwdB4DzlGZZb)mQK+x>ALjST4>}*FP#RLE6u+Fv^?o%
zPbl7yo})D-Uus87Xn}O$O`sG?W23+oNnPFtSh2K-4X_gFC=UZHm2RbD;7w^Ug_O#q
zY7G?1t<vTwn7Ad4s)kI3v|a(3O6exb?A(@izY4S}>A))(eYG@gALhA68j=lXYNd8h
zL*b4zu>uNp(zW?OtCvPA(AXf2pto?NH0S~Ry(>+<g1#o{SU>ExN}cIQ+a|qEo0fK|
zb=MH|JESjiF<+fh(J_d2Nk62NdABs(78>`Yy_-RLq+5&NMX!`u0EPQfTRS+@CoQT%
zU%#}_4+bAdKeB<yfHXt|>_KS@Z9E@JLt5a)ko2vWFr;DW$2yP^%qZ-QO8>FOgN{i<
z?BMsfbd(}nkED_|XiP}G>j3ju8gdFElhP3SQqz<)`we(FEuFO)*fY}l8F02T{0kO5
zcrw*dVB5=@s4C@%EM_@42iYqeh&amLH$uTl_8JSAM`fi{!S5`qX`%ZMF0xWuyIp1d
zbKt(4%!W?g?y_ta`aERIY1iQ?`=JsdUb2bTK)hvNQH}L6nGJ=zd}M<@m;_(hV<&+6
z$%@iJ{AIRM4C%P6_7E@wWFEB22Fj#+p&lgroL0MF*}K*B{iP6D932irWzMu?Js~Tg
z{{a{#YyKLb;j$&ZXpE4(CxuUuGXCdKjFRo8y+E`~MW^l<nZgs2CuRAo(RfN`4u?;t
zWr}D>#>#fn$?1%2G!GWe%C?OFI!-n^8xs^S+lP0Qb<R228p<yv$jT_dbzb(-DsYLi
z<Wl&3L6$^u^^3BM&oHJ-vU18$CdtBngfo|AeA?hA%Mxglmm+hgqreqe3YCMU%0h>s
zkS3cM0C!d9wiF(w%eq>@Wyqou(05IiK;dy~rficZ3}(sdW?(5>mcI-zxw6-SFzh^;
zl`cixkePBo@@2l^7)*gIj1n}3vaO{6Et37V5-`QGR7!xC$jUfytyH$2Zob}>jZuiF
zO!kWm>g6(zM$F7D*`WqlsF2;IpH-z*wtE3YZ_AP?*<2;NH3jTyS;zs98rk|ykg1iq
zJch^}*{3&vRwuhbk*#{!9EyrG$O;$1?M7Lj2z_^D|57%uNhYG7RkLi6e!wlV#q@c*
zR@rz3#@QyjF#xVzX88o9LuP%NR@6?J&krD7vTtcu*)2Ox|McUY?D;y79@%fSc=pOR
zJOuWASt7kg`(!Z`b?%qdo8j668804a1G0UzQyr95_JDgR`?V67L$Xu!h8>o@695lK
zWXo>?Y*ZF>1%nuqwOVOMG%ow71>}+JS6VJ7WOHfX`&bs_42?+{(+EpbvYB@QIxQ=u
zONBEs6V-Uy%Jq6++sXfF0B0}XPtV^Gxhtjm9ON%jqS8^Wqf@t&oJ(Z~N98jI@JDl&
zFMbMoF7i)5rg{=rc`RM^bCZkc)a@?+p7PNi@}X5g^OWb(*4RtFC=2Gj<=@@}cT65c
zAp{?}dK(7gEB9&#sGq!vUK0NDKzbV<m&Z~XK0yA47c2$J8|&~F36gKP2Fzgj*IS?v
zB5znp_uoV1AJFx~6Y>%|W`xOKa|H>PPu9Xxgxo?`!6M}i6at8n@1vYqv|R0mzEkpz
ze*osR{GJ%<vGP31Dx8t4t6}%7{0|-m5hven50Q9z2Ic0@$uH4+H$nayg<sFh`}R@&
zXQKRIEKFRGAE7h+MY%N-L%Sq@yA&iz{w-~BFUvR5t1el-+7&P<@?R3rcST-)5Phlg
z7b%jLCSSTAeOKl0(&Cpc-$&W>40#s42(HOLmcZ>yxf{huvg8vq`PuRhe+IE$m%Gx(
zo^#~KgMpSS7tp5+^5iS1;QNMLxe0dj<uBKwuRxwn=cz)uKm@cR`4hI#E0*hM<5?pA
ztq=;O@_&lJ-IPB~yU8;7-hZJ`E?3_H$}PEt>{iGtY0FkAXGDU#ZI!=&7NS*hc^`bM
zmUEs)XN`Pa3f!-iU+}{~@5txA1WR>t^)KkFm#^uELW6vw1R{;{VJbYkE8kBgCrxrm
zAN~f-@>lzz&>}Ze;aIDDeLYax<hzeSq+OoAAL<?QKsqgS%B^D-=y%C|7sJzT`P<tt
z(0lTO^bwC9`LDe&(JNp59MJB|1;3%MPi{kR|9*M*COGpzej^)w1M+{D!Nj1vhYD;T
z%6CgZhUE8VL48;r-3c-xe=r|pRQ^0YF=O%v^oAXmS6R0M?UDTJTEI-mpACR-kL7Qt
zLVr@ei}L7Ga<>FnnwGaO1DTPpScFDf#S`nn*(napf`YxmLhJGo#o1Rt92DJ4K^zt9
zsc6?(;oJyIE(+nxFyyMx^U>(0XxI(nt_XRW@(&)0*+#IQir=UV#!Io2e%;;*Zy8J+
zQ|!9}5g)~yk>Gq4om5Ear`S6OUid3KsPOZ+V&SjwH$d_2R`dlbat}fwND*vAW3VDP
z1DGKS|6f2t6>O@&I-!tJ0ZN#{^56H*!WGLX(i)+tq7y}=BJ2@BqZEd3pb@ROWds+a
z&{1~#q@rO8pr;hysX$IE_;nz$itGY_o>7cbmEu{&Uvx-{Q~dNRxOhe3arksjQBOaz
z1jSp);La=LHQ*8zg}9VtopV89L-D4I3Uvsk?ULdyl?Ws$?ob~5vf`r@z$7cqQ(Z@j
zqCXb;R}>qjppdHQdKp}r;z_!NcvW$b_HpS7$D`mf6h%Jp>6)VUATTo(NmMqFr5G83
zNVZ}FeX#JlqTn3VtvQM``mN_Go~O7(o?<VRC*M%aFF|L%Vkd=I3ls;sp<k#tc^ue9
z3Kf;47b{k6#Xw6G%`4GYs$kF=`lezu3F>8v-v?l+ToFs5tXqm@F_@<ch4C#|s8k%F
zSo>|o)rU~8vMN5Hw_>%T+y<6v6tY4n)+!vS%=eC>^+{N&Q<S`n#(G6IC2t!PB6`I(
zDm3fC-Blc?4`nnd7+--jD>}u{Yf;>wEkUc|nXfR<ZHik-Xlz&1?*P}K_%;gWI~9!-
zgz8dQC3At+qwx9`GQEoY5XjtDoQQzkK1D}2xPAq<0U{3+Wo=L#Q1ohmJ*YTOTd#)-
zPdY#iDehRIKCHOx4ZRV?+pmEeRh*{l1Y?RYd}eaaxT1e9X6BKie<_ANp(v(((PM?o
zN|&)F6?^H9#FQeG4UK6<p)Igy6hC&uMO)=PiVN5&&6L5mS61nua74NAAV3|I6|`78
zDjg0&!AV(4`=X=D^+(X>thD(Ym@dkSG!R#%k&iw%rNS28yDN9i!^k|8mdEt|^HkpJ
z!6>|xNk*9PR<;EI?U-^M)hqZY-`EN-e3cXL!;+u!6s4a1m42t7e_T2C9Ml7p1C(0~
zR2oMi5~Tbm6CMUDbyUF^qC7>r{!rzIv{gKz?5F`3rfho`T)1*#n&K}J%Hy<bMJgr!
z@FGfCIRO*V$}<UoiBZm@VBbmQY1-zTQeOUVbE$m00$i-pmck2Xls<0Y&MGx$pdP1m
zq9r(9=|*)5=agKE`y?p$Q9;Ie<qs7giOQ9^P`IF6)k68di%QpSn7^cK{t4qvQm!Vy
zFDsu{0y|lG?>lIuC~Mya_7!D4Rp_KD<#VBsru_67xOP=pLz&=oWkDY%FGIP6V$j!=
zo^14GDu-48B}@4)?Gv(<uTru7b>%ll;Zu(Cwh_?QTxDJx(DIZAeK3hPl)LG8l&{P>
z2GIiL*KN=*RDSa>xDw^;25_ayOY~ISRQ^iefGksH7+}6!+2aBex0Go-h*T&$e}_V)
z^0YrhZYzf=5?7_<=fP05k~tS5HOiIAaJ1H{{FDcSca$r}0aK@(6^+(<<urxR8<al}
z1GG`O=MxO=uJUL4a8r{~zW}6Jxw#yAEz0YgFql^5Cw~C6P1#B3sCMNfJ;fc$dEdis
zr!tx<K)RHFd<f`n<#*pg@18Pm0(w14>#X~ry~?+DLjS(<aU_P;r}Uz;X}_}ID$pJ%
z`_@B$K)IMg4};3{6fAhC6hDTEA>}Xy8-|r#bXjyn8B0H}QRV-ZKyOU>!<P^lSMsT*
z?UC~EAsCuaeoG>cl`dWonN+q~sgQX}>7)Smv~q$TnHl9@-vZ566<z_(PW9V7=-aD)
zpcCT}RT)Ki9aOhyU3OFnXw&1QT0?~uM^(B1z-?!hk=7d*)d6}fxT<_9d*Y^Y_ye4~
zs{bFTd#GNace1Cd<Vkw|yi~82K;K(c<pN8`R0pU~!ACXv2GD#}PyCmwQ`JU7(qFZn
zBDBX<o3mg(K=nFpCj(V2+dzU;+s>meShbz%qC!+9RZtIArO;Q8PpDkaz>6@|b*k+Q
zSIwet|3s+1X{YBeQuX5#a5zf!0o~q;R^8>pQjE&5ALOLU&H=8SQr)JP@oClbZ$m#;
zRZP*RGph6SYCfyF?+^7jm3t$&ODe(tK$27w&H%ftTGtFqsj8<R!hD+QF8$Q6s>*)?
zW~Ry$F%IjTEY*6d(#lq~Sz)4BHBMo+QdQv&$lO%vp1|LyOvQACNV)0;{e5n!%E-|Q
z)uruFs8k)Iv-EA%yVKyRR4x=yt5L1o2+3Mi1zo|uqf*gJu}<|PRTk8%BD#Uupt7%k
zr1h@K)en}MR3a+3ZC0HM#Rywep>*_VRqdr%aJwp<-n$*DQrcB^sw!Q9)}?xnc7ENe
z^>$Fdr+WGvuzOVHc2KylI!^0ypDOsjK%i<@5c(ddQkiHRP(4`)M+a3URKxJls`94I
z^pI-oSHKLbqSDYgqH>J{H>z4sFM=_Zy9u6-t7e4o>5(d#Hp&yKPga1NRC&pPJ*ApM
z3D#+qXD1|QRKL=#I$QM)AyDkp2PqJ7MEyb@+;&js(vj9tow*lgoz&Ljw0AnH{=6HY
zF6zeR7^tiIFzvV9)C=gd8}91(d=L-y+U3yqR6qC$etW6ADX4Qyz4S3G`KW!a!IH0f
zoL;zoYCa|N{ndM0L5{26`2aozskbbEp<wkz96IKNsJE#xvQRbGx)Yrz)b$j-3RB;w
zJwc?}opPa3>PjtSqSY@`W!@?EhNt1hY4vAxRW?@rgEvT=`nMY}7_au<4fE&Ju@r<#
zRCiQD@`Cy=I#pd%|3#%Lm(|8)AjxVal{%-Wn_dBzrruFv#h9+DbLcWvy81aQ&@$E5
zB-qVT3*U$P+3MzTz+6|~KM8|5>ie{#$yM*Ck8tFxtyB?Mpsr5@SEzpVzu234Ittju
z>ZtutFHxsF182(A8()G*xw@XRdAHPSC=phn?h#S_b*1_fD(JYa{@_D6Q=?W=okOkq
z1Vw7^s0Wf^qCx#C3uuk%t5i;XSN-$_a4qT;RP5iX{(*u8ZR$+Q)VHforolvqdTIv-
z+NqvR@6>+vk<(~=pdL<#$bk9)g&qdg&ZuR@_pjBB&!KZj{cJDLhSmS0ZQ+R8fsQ_-
z>eZV7Gp2qg0wUw;@85;pM{3Iwh)k%tv{*k@Z=o9xlj?mGw4PEAJP8xiYW7-?8Fh&r
z8f`Tn?!&~|X-4QCfxU*^3-u$KQL0e2I%w|LLdH>(R|)e@nq8ElJgSL0k1;uGc8<cX
zi^lm2^to!@i^b^OG(XV++g-D!73MuO*F1sksfqd-#7h%R7g&8X0jHtvt9geOYd_8W
z42;EJ^QsHTan14?^aW`CcL{xgR?UkP=L*vFG{dQ2&3@Vzp3uCP4Nt=~oVP&2HBTZ?
zJSRdkI~9GAnhz;u9i{mr5ne=VuF~C?7|o*>AaYVuMbF47O*?&T=(I-hDb!;%jOPG-
zMpHu%<yp<^r!b>&nq+#Jp3_*rqMFtOjcX{#c}+S65)(Cya$sN3_+5g`Ma_l*G+x%^
z><3J;CW8wuMf2lHz+BPD7r|1hrhpFpX__KRlw8#a>9ZT@n$KzDnW2e`#*|#sxYF+;
zQ{%h{C|R0*CZ;P}v&8x)OkCGQ(?gx3F^7TVX}l-}RiIH(#IsP-L@&1@joufa#Tu_@
zD3oY&QoxmJ2IHV`Q<GE#>@v-Xjp!@a2;T#_rCC`EQlaU&3H3@%!;2udHLq(ysx)dB
zkZMiLHhTZv(KuX!H+7l`DtxKe?4lrLgXY)!Fwv;_sR<4@YdUF@)}mQR&a`Sip&d<|
zW;wkS+cl@DCcHyqT>#RlSwI)rx-@eSU`D$&>@X<Y)9g+L>Ct@9hsIvb$tPgpz9zqx
z>d*Q#XK8)y*Yw$-bx`xE5Y7y1+W*_jYh)CF9MyPcqi;+zm%fKGu6gY+Cg_pI^&ME6
z&}`j_zQ>voT8Sq$B~))PrTJ<rEKO^!6{B%R6HMDOd+nlKAV;)pPuO$NMxda=I>%94
zO*cB7wD0W2K#ywOt6|<*d&nQ4E?T=_jL=p41Fc?e+S@9Cx@)g}0M0|ZAr}+utu=0j
ziDTN52<Z7}4^iocul9>yK>W1xso2q9TSLK-K<%3Oup6X(+yw7~wf<iK#Tuf`p9Brn
zzT|?|6WUOkwg{~+g&rcci+_g~QQBY2VIo?aejNs5w04EyPHH7S06nGkei7VhZLtLk
zvD(;GP&lI<j0D(Ot)n-_8>hwpzrfBw`;c-XN!lEWHec3mrFeX@RqOAC&J^t&d!Sv>
zW`trcQnl7>D5hz}xsbW4^$@`CbnWf+AQ{@%)`48p4$-+JQ@hjyT$XmU1CrU=2Kpsj
z*Bbr>SdP|-GH1EkK#EW2X`gjQ;|=ZGuVT3Q+Km+dEYMnQ*T7Pt_7yrM6=}0+c`w#p
z{s=H7+8Bxqmud@opm<X&+=Zc)X*2!@&~mN9A27GHt7%28(2ml=SgFms3%%RgT_-U5
zDs2c|^sm;&mIJy*8!G^GtyW=zqj$6#3ewkUKef^WU$6b1t}`@f@9YC<)UMhA#k<;z
zbSi7o>ZV}6S$mtd8!g%dXIN_0UZq;CHtok0hH2Nf(T}u4`v#?uI<?|N80^x1J_XXP
z?H__O_p~oixT;6Hd;`4i)$+ZeeqWpL6TScXv`dX}s$W|w1@}Ok(+tr8t;P>BgW9xD
zVE3VxQv))jWzhk9Si6l%aYwYvM$tH`U4}r$oH6Zusu3I4et#b1k@kslNKR<yQTg_i
z_5f}7r?tEnF_sxEkB(aQy3n^M|93>^NJVW9I)^?GN1a1EWSn$OwD=v>x&H_>XI(!V
zqj1r+&&5Dpb@po^>84x8fQY-!ZXFanbaTj2PhA3iGQ~^x9c^*Fb<d^3(PO%fuc6?h
z+j|G|>#Ms&YmuKWdIz2V0(2$F!_NuS9d?3KK|0}LXawtm;~^TNdpQ;+LUo;V{o;g<
z`xF|(bgQ;PBwY6bogpH0e^T%(QYWX1q$u4E+WtoC4miM>7+w8Jcz;sI*P!o|t{fZQ
zIj42;N?@MVjZ-nIHBPsM7Up=J`3jsmrz?67iV3<8Mj>-v_xWoWMWXKBGZ4L?Yp2q>
zi@GiUK;)9{2RczC>F$<7{jyH|HMnG*y%drux{xO@30HLQjl;E6T?AcKNYlmB#9q~v
zQII}eH$?@B8CKmas%W~V`)xf2lc}qrw`rEnl{RA8x~Kw>>pEiqT+7jw7D6#sH~lFL
z=IJa?q49?9Uy73F>z?AGu|QX`11N>M_X6R4k#6r7P%qYry<omXCp-t}Qr*uH;BM;b
z??JLmXML0Q<mI}hRF`~9w=)Qe6}k(TfmW$&pxZsSbte`=qe{1tPJ`7t0c|j9bOA4e
z)av$9Xy}ek=L3{Fo$OB-tk><O`lJTk4^IKCQI|q-)4RGnicB@>cGLf&Y1X~>2waQq
zPb)<kT6On#ViMYP%ih3zwd?kO3z-g`!zTRIx^)Zb=K4L|_Gp;s(e={8+N+yc2=2aa
zDeXG?bWWF`-mlwCTlojNEGl^(&>f<D@}O=5?WZ2<esqGrLpoc!qc^PU`UiR=x~MUF
z{zi360^#DA&WEmhjqCC#)%QrZh0X~Rx;nb%`B=BS1>B_W*c7-aT@&4Jnb!5Z1?(B!
zH+w*A_1CBv$4>vHGX`O=FN;Lu5&bLg!JvcwAeCS^>Q7d|Z72N;bb;=u{<DMh{WE8M
zJk=b#=<hVcysQ4B5Wu+U?Kgn9>zArACJ+5)is^dlzqUZ%OaH}oIODC4{Sh$7^q*NU
z7$3bqUDfl|M_fRopWb0RIDh^0FvxNJ7jvK&pnqm9EClL@$h9E-Lu>-9bAt7CHZUKe
z&k09ssD9@~V4u*(dc%B}-aiW@T<^XE<|Fi;S(v9t{YO88MCrS>0WDhZNb!hM`n$B{
zJFU;7ry^EAD-K?q(U*S=?yUYb0Yu{T*C_xJuiyMGB+uz*)_}7n=w&DapL1USYy?CT
z^+S|lxuBOXhsH&H;te!j(!WZP;Uv9BF1)y`A9x*8nyg<>r7kIY9v7p(qQANueX07>
zbD@`}*HUWas{RiFyhzu_(Vf!_{la|cUDH<{g56C04_7hjEUP|13!1HecnqS~_2raK
z&(SZXJ8!vq*FlKp>9<@%;|+ZjMVRvS^Me3Wps(2ggN6D53N#hz7gD06Sbz6PSSrzf
zu@R(Hzet9@n|jl$P$<)X_XD_c{Y4W{Zt1rdf~(M5fB6u0EA^{JpmAG&T7cFn{af=v
zs`V}urKr*Wa}gS~dInVl-qC+f1)O#I_j^I=_5JkIY0yilu(we!T!y*0tA8^Cq)ET;
zJm#WVUlRb*qJQ@@jHO*~PaClg{RU51=+ysZZHL`1eJfSdbn6-P$%lJ-J-v5(^toR_
zv{!$l2IRheTR*0xPw({weCpRT=w$prpH0OY1Nyae+8ET=(c$i)UQ4<8A^m!KjE42=
z=;$+|cRviwQT=>cA;$C{*ny1epIb{Yhe!I&UxG~Nr{4k0WBu<g;3oB}bdZ_S@0|~r
zY5gtARLtm~jl|Gw4QWD{urqAvgn4_zo+mN1BZlK&K+nPO-Wwo}hL}Gg>14P-VX~u!
zW-42CHe^IV&&BXGRcgB$p7EylpPNAxhgNsPPh{T1aG@Ido`#FG-S9HZ%fooR4MPWE
z{+Pk*5`6M8?4UQiuR)#*5kEufe4zOostvGo+z|X7zyb^-&!92TAaVc+GMroqy<kHH
z{h2}x(`x}1YOuq~gzrxnZd5`h%y9N)fQB2mR4W!`_^=Kz(S}dR;TXe7`XQb+9HpIk
ztfB7&B+nRv#PB!X5TU~apEIm|3VI2KJ4c|9VpwzlmaZ81luAuC*i#@d&9J=$hOQc(
zm;<nM!?O8kv}PDw=m>MokU+1>OhX-Isk02HsVXzuaN=oLx^6hN4lp@}tSnf{H9Vk&
zG0*VC23Wdbm`mrWe8W?e_b)I+org%FVcR^26dAsj0;SmSGKJ1d44$M=YRKLIdp8Y(
zJK$lN)gXV2)^fwec~HD%NTtM5h2e5HIx7v!uEUwz1`U<iR2lx7514Ahi*ev;43$(1
zRBLcK357d`T{4WR&an6}?A9Cpp}q#gN;4E14JCAC=dR)F;~-52yLVx)*&wBiPK&{+
zqLXH;;kE#twi%XD-lN^nNuP@8Ff<$k*J;>a2(&K4`Ur5{28SrX+%t4hNUO&%pI(u@
zhMaJ4_YL1rAimGAh!SZ1hKIhud|>#k6&?;43X8xE8vdm6;D?4#y5KQnc-cz(*I`3d
z2(U*CIrL{9HFV7d+L%ES4@={Q!dJjOGCZJizX?P0zi{TUVVDZJrVU;ch?p^4vjw)T
zQE?Y`?TjnxFv0f5SNvh=h_PoIEI1fHo&|%B#?^E-bTU5J1I(kw+;`}yayDA&)|iWN
zcnqzs#y1jx=4KRkz@WR4m4ZGGqYdS}JdLh&5b`pv>Or5kQT`r4j~Qi3IOAj7<^j&v
z==?T46~+%JJ?w9sOXut3#!slWEWkML7f1#hZ_%40#OOOo@4rwZkLnFh7~8|p8D`v<
z2^YhSl7o<mFrK4-$Qo%p+zZes<9vdNHsYQqo(iKA1<Oww&(aq%P8sj`VJxSOyH|t6
z8h1rO;f(QUBf!oYzoY<0obeewrX=3Di?RvljJr`EXq}T_oJ(8H^Tr4f+)p$Xz5<O4
z#wAz4T{Oz5^74|gGZW4v8QY)3urC{POTi@@3->@T#rSAG$Q2_Jqj=PeVH-ixjD3`x
zyJ`#>1W7mkPDk1d<LpVOUo*Om!~0C*^?Wp1vy2Z?!DbuF7NhgJaouH*9ODSp4(A$|
zZ^9_@j4sy!bHli03GC(@Bc?Hm0;5M3xI*LQF7y={8TY{z8&A9iuo7c`Iz&p1271@r
zG{%U*l^HJ|!m!JYv9Dr+ZW%u|VSp7@W9w|VQEBYi1^wH`a4ig08Am8bUu|4YMGQ5@
z4?jX<t#N|>K6i{Q^lgheqb)r^^~N>b&}%S?>6O!H+@1|fca2}2ghGqa`7lIUjR~<Z
z*k*k8Hb&NNTzCxX9me`waIMp5y|)9MUB<7eqQ2YsksSK>j6rLF)?<AAW9au9Q=*`8
z-}v<`i1ZnI=<)A2&Z9Kb17j;y<_#EMrTZR(#*s_tduZJI5Pd_&xz#W@Z0tM@uo2_0
zvtV%4SiJ>}V@3yBG$)K3t!n5$Hg?eQXwn$p0+=b|xEn;LjZfT%`5EIO3Ub(*KBOyb
zb|$|Nn6NiRy#u`?ru!BsIGA3Vjp=eU-KHDhPNu5E06S_5rk{ti=^iDdTufUjq~vN^
zN5KL&Q`!F@;%@r$locjCOwpeM&C~SvCm>#?l?3B$T1x@UW2R5(qKA*^iFe_!uW2rA
zpZ!c3PlEF|y-V5c<EFPNpb%jChL*BG(;Jj12{P@XJZZ4$IV!*mF?~+y-B438EnX)~
z>u94JW}4?n@y~G6a!N`@nEpMC)=1Ok1Yk#*PToXgw5k0EXvCO`zJ%SArvBG~cFLrp
zB=u>NBRz4krsY(7amMs^0nDE@tt$kHGhNt;d5$;f-UD~eq*@H<1XEQD)X$p+X@j0<
zVxc+<`FGR5r=Wk)w08s(b;;yN`-~)0<_pljZ2FagXUV3=l!r?(eJ}z2E2e9-flM_8
zQlccy^!jS(T{YQLrA)d>O}WJk)A3{IyJq5hp)uRk_yW|gn`UnTmt#8p9Mp47yQm<;
znrBMB14}nd(l*RxzUf<v4-}X-QTbb;seyuSMJ9t2NU_N!6{N&;o?fb@CdYpva?|wG
z8{o=JTewg!H~GB-6SqwF-p3#+OwUuYtJ1U~43=)2wl0TcmFX+m&Q+Vvw1d=GO`B90
zVXa9_5$!uB6jI~iGM#=68ug}dN-Q;)0uRIeM$_CB^xZXiQZ-wX>1EodH=D+ug<gy4
z$JtP5HJvShhi#^IiW;|@qUp%hVOl|VDmqOmcc9m064T+i+cbI+{@ycL7gOxK$Fx@k
zjb77ys`9^YdO+K&KGT9Gkbct-6as%>YWp4T510a}25HdrKn$3Nrcc)ZX2`VbO^{*J
zZ?D4Ah-pbG^hQmV|6XIJDLeFyn-)C<g-52(>E$wE8XUur9-C6F6!x7ot)W!mlu6%@
z&S}%vv{{=m)y;y2t$8o~eeKLyv~1a%OH!b4#C*OCoP*io4!0f6K6WtZY!>Lz=wfbN
z3lUfI6eZx?%ntUL5_j`PirjmcmwgA$(|n7H7re|{3#?G|Hrr5f+A;IPH=*HUuB1{?
zU-Nh#CfLuslFCB-&5r9qj+^gL>>$9L*9#J8{(=IvLFN$JiwB!;(oz;;p8gz-q2|4T
zFnGdTNj0TmW?Kb(3OB#=CQu^Gm%fBTq<Q;#dj6u!okege+H8q|evCQw2XH6NZS?ax
zWqvaoil@!3wdjjAZ*+m*XUvxlqwlQw(=_zOnFq{3i#JQ?y5u?Y#dDa-1oPXpB{*+(
zYK2~+IgGwrc)=X-H~KD`H_%PAOXh}0bpA^+m(xc3vbn1Ooyq1>y5o>y9;=6^SIkVh
z9+PU0FUMfg%&H0WT{W+u*M7RWpAuRb=A(Y-yJqIJ!;4JwpLB%CGJ7wD`D}BC0V3DU
zdlo?<$IPdbM6TIDH=Od!YgS?`)*I%71JKAf3qQnQ3h?)ZMxnXI1u{iu_Zi3(n~Tpu
zq{Mtt2hcL}SvCAEH-B{jBDc)n)1jlnJm)2dRGKArFmc=5uo#k6<|SJIR&BOlg+bJq
zKccsHt$8l(4DOi!CdoRhd4TQ{)SD*<VX47fzyxVDKTHPNU9%@;&YR3J-vXxD{M~g(
zwwNR7F>W<WpTwBj%&s|@;CA!224HuX$DW6!PV);CB<wPmyoMolo1-tonS17b%5(OZ
z%l+YRuQ};2DBL$&Kc)JpJ~NAw#{K3GDM<Oi{KPUe4wyIUpg(9{SA@QY<}ix+4VhQB
zLuA<e9mQ)$%q6jKZPc7kOW~M#y8<HP<`3PW_sG0)1-J?Gx<*)fY)+mJ^ONRh>2q&W
z<~6i4m^SxW>7+Sh4x>fL*0OjIFm{%Od%)RSc1=Lzh~>!!5C_Y?A7IeYqNd4rvh02z
zUL3VNOD{!d%U~c(xL8zl+uGIgkdm)%mf3H^yu0N|s^jvo2>sCKY5Bqf_Pi`*+kxqA
z`RowA|BhKikD%dWai0(3Yk7VWvln7<p_oOeCHoCnI$_z+4@+SdYZvAs-0~HDSuVm7
zLH9KxEggSgyit}UN_$3I*1DrF#u8qMzLS=NzUYg!G|+AMGZwog5IJkP=nk`SmZw@M
z{~mAI@G~^dStMh?PO!9Zg{S8&zm-8I(Q@`FIDEm<{0_)P3wJ3%FIk4DG07sQoxx>`
zExp{5Em8FAPO+>%0~1#)N(%9$TJAZ4OS5E9T;Qr@@pVY1TiU5aEz`2Po9aKaET2g+
z>}<=|dXVdu=R84jEYDLcIoHxL2%qvSDhXh2Se8=sDc|xm0ylFCEKV<=vCuL>S%o4?
zSuga8Ej#JxQ)1b*4Sl7Sp)A<FX|X22V439ws?{pDFe%D*%Th`Oh1Lqo?!VAkY5D0r
zkZMaUZJ28;KW~Lhtz{F1TJBivC`M9e=_!WYddqhd#A>i`mw+@{9?|WqyOs>fo-|pe
zw3xhR%ZMI&Etb$KkXFm&PJp#pUR?^wcFTMAK<Th#>p(iKmc`8&XqV-c5ZLXu#L~9z
zp5==dA=+b!)xf7-%ja~p<Gv-Iq6B@G6$&WyTlCMN?}5eS022e2bJMUpXxW<pk%yK;
zROK;bN!^LYVavx<7%^g5L#N+Si~C|YGiF)M!^BQltZLeQKep`g1(~$eR>RViCE^UY
zY0G{-rgX+4rbLaM&7miuVQ<rO4UI=^Qtrd9gUtu@M|ZS2)dagvHic9db=0PwZe2Rt
zd_qxF7n?7roW#{8nu$g?n}CN9akt^V0xvvlnAUCZ)YIk~y<)v=p1lMOZ<~60NgcB(
z-UtmJn*|jZsISdj+6?>Il&^<^zfD3O8jss3reHU~W+#O+18uI;RlOjaMhEBx+awy$
z7-Ex_3(QcP#pA#{VG~0)NW*NL=?jVBHr)LGb9CKtSyx@$T~=mgrKYy5)LdCTd+)uq
z%(Pdn%rdiK!`8zT6c-36OZE_yDN6-GL6E(Xp-cr71!OrG@At$%=X35o-*e8r&u`p&
z&bdD*{};koOjWy~j8qC6hcOn>mMxsoPj^KG<1bpqMl!asK%($vd?<}(+;GE`#xUw=
z5fR7ua|@g~!<a*{!n2I8Z^6-c#%>BCB`_kKfJ<cTehr3_7%#pJcrs)43xKCE#Km;}
z;T*$6`?yrb9eS3fF^+b?i*!anB7hl;L^>&z$r#!LrMZlUR1kHU@fSUrt}wRID>9F<
zmU0vMjJN)T!K;iiU%(3)9dyF+8e;)v-ijF2w4o?wFb+bbgi*X5B4vzISLpp$&hYvZ
zofV8~%C1#1K4C*!6(b=TmTDMol(ed4IMTzjj`5ftV)YE~|3VLp7P=lA7^#f_G&1VX
zL8OV%Or-_Q46hQHzrmQoz#wii-g^&rTNvL*VSufSe`pWT#weW&5qmpBMsL~<hLmEJ
zos6VvD80qlN*jdRj87;H*u_{wYrSs9J_|?>qiGeC-eH`hlCQgr*JlIQ%g|F1!9B*K
ze0X@D@%CqE>|-b+!SyrNkAMs?BsI|afU%7S^Mj1bCGcs;&Uiq64>Lk(y)eSi(=un2
zv5r!rj~U;oq4WvkU)qe0F?Myr{5Yeu1C0}m8_z>>l2Jg#{*KHLI%VU;oJHXuXJ#NB
zYIk9-oR2<N<{A1&25w9a6_B_y&o74g1I$$VVGc6wPu~LT!PHWM=P+|#KhzvyE=Yyw
zQRa^n&^yLFat9)w%z0WU^<oZp0C=3ak5*vb%)pmHe3(HLb@pYpzX03`rq?-$oMiq@
z+g?9rP!bybnLB9_9>9E#LbHL)*j9`>h?!#l81xjgZU7{h$)rm@gt_D!$b>RAgYYSg
zIfLHt;mqG|gNtBBUxmR)rX?5#qnPiPfkZQ{a)`t*J6FQsY39H+3?i1<K?&VBrtd2t
zXP6P8`0dX!f2I6vJTvYKc$mNppKS-5$c*8^d<t{(DTtn9o}?XeDzjS$OKHsD<?uV5
z=})=A45pOAx96GP(~9H*bHQ4Wi%j!#kj!HK^b*WxGlMCfm&5G80bDL~31xyWW7z1s
z!px%&Y~(TDr7tL4WxnM}@y`NgaU8rUWG>wUnQP1udNdU=zifeMG4m*8*GiZTf5B2I
zQ%Xh7Wz5Hva4ctjHw^D9n0`B9qLQhm^G8+8OA)|TGv_^n>8fE`+~8U*GrkLrb<Bzr
z7+F1Y`5ORSXTI%9`@aUJp#s_(ne7ycZel*9OQ4zgk{`6)VD6)f?ItsG6kfD2KcFkH
zm03kejW%Y{PvF{_yZqpN2Qx1j@J?n+EgZeY<o<+ty3PD82zI-e7CM^P&5ZsKq=za0
z2#vkWDOBxlzsKyq2;KLYQ4>J)F<+v{Wk2(krH~n5=F)~{kU8=SfJ02dJ7^qcs$Kv$
z!u)U%yclKr#sK$-nMz5r$IQ{EK%Ov9kd`s#v~v&{XYQlBX_6UF8#f2mYA4urWR<S~
z=VWIwB7k>hv44aYF06yJGI3@7LD`7?tS!$&n;XlQ>Wti3drL7F2Uu(Sz#U}iYQcH1
zGU(q{9Adpj*W+PU7e&I4u(F3R7e`q^ucGl7>&qlei6`rwHL&2tTJ;N5A7{k`q0gIT
zf0<t2KCHQBwED90gW%K&RtSAk{3L7bb|Cy%O=39g&&r_>tOl^eKY|Nnz4HU`L9Fw%
z8$88on+q?3SqnA-7s7f#U(5|<&1!=eVXSR;&=|@3Xc%5Zv81WMMYGOOcsqtAw|@xy
zY1T>lx=}34NsZPx)+=%#&az&lgG=$ObqQ!pVEr!_b`x3eQ6epgmHi$XlUXekMonQ&
zTY<h*Rt^h*G}a8-Vy3eeoyTvG!8+3ilF9li4u;ONwhKWnuy$XDYZqBB{zj4IESAX=
zY&L6tJ-ACOm+L^}vVJdsPnTI21HoNk{j?P%k2R77yZNli8ko4sIz*R80n6uUcyW!j
zg$dn7tnvVe6timR5M&AK_m`lvl=bHcSSVx7rc#D-Rx+hxD_LRF>He!?WiX(onx(%C
zL=9_u8#-%Q&tJzR)Uit90jy{J_yb4->xMf>BkLh;u$x%h=n>w`nokuzH&~xsL1QcH
zIXW=W#)@!;vUXO{i<p@Xmg8<ncCubQhC$q7U8INnZB__&W%ilftg>JrdRYCm@4UnM
zD;+X-Ss_$E)5|(@9nRcit$iIL_gT;F1nFl5)8_^TSo$`&{eYFY7=S?*gQ~lRSdD*z
z8)mg1gozQBjY>5~S<^#c{vk`c8Qde5%W?Shm}UDB0Q(s0*A-AR&N|}@hbLIyG-HI5
ztdG8h2?w@q5;Bf#E3JK;*c<qebYbgs(B{gn+l0RTZ2ivwxUpZQ5*c^4_qWh}fSnNq
zWe3@NI$-b+d(ms)4zssYef$x&r5nnQvi}N3<1ssXog5B(vS0ZJKri+Q35YklY$G~-
z*vh>?__7btX6Xcb!!nSQ?Cq<eG=P1T>KX&t&ro4+5W6%P+$nZRC%9ntyvy)DgdOt?
zrYn@ak2cTYY!CVXX9WALFCY@hUJ`}ID7O76%A-fK>nT_t!>*;#pJrdB14MD`LmrSh
z!+whv@n_lE(`bxmJ5qQqf&C7>R1?|GA?QnDd(mz%nZ5oikQDYK+D@Hgds#8ERQ6W7
zE7I90C&ul-o<$F#O!l5>7{qz@+jiP*Two6?@pD~dd(e5UEcPEgkh#RJc>;V6d%gss
zx$M?7sJYC3ir!II*s}M)<*`3=fJi>Oq7bBj{r*)n7P50&0Jz5ff;Kxv?9_eeD`vmD
z5kFc9djl6DrR+&6&nRcF@TL4;1v~Exh*q-83P7sZd#<3dntgI7W~Pq)w-h6+XY&@p
zwd?Fg`i}w)Y<3gyjqL9o(AdOoq@7|jd+~mdo9sF1AT8{TG(oNGq&E25#^#w|zMZ{@
zUKt(iF}jdC*$W0K|8ScfMYn$!+eT~ZZuX;l_?>##*-xPR4x4ua2Jf;TQS!EzZR-Q@
z9(&m$OxJyOA1!$M*g^_D^s`^2SJead6DkE9WdH9HM26Tw|G<l3_J=m89${~!T-PXD
zO|@DN+0(JfvCn+W{@_In^a*?Y6o`(oMc+eooW180=$>FNZbaWC`{z~oMI1P;`#_vH
z@wB0F<|I*BmJ4SoEw)@a0{UV1bGFkG$c>}E51czE<ReHP<g_hDp9d#nF)SS7OraA1
zhdFNqLBxK9GfdlUPtMd&K)g6^Gaz%E)4K}@Z_eOTaM*`)b~YUL<$OzL-cE38tKp#^
zXTt?>{+!J+00KDM^D*o|&KX*Y1aW?60(Xk@VK2B~&cYlR4CTDK7>!|^Uw#4?&e=8x
zu0_~6l3j2kl2hD`)+o+8FAOG{^DnK^VmMy0Ag4L4N1-N`vtTRmah!W|A##>8_kB!I
zJZDima0#5WH29myF@Fw{#HsumeaW2b6aq-$ST4arD#xP;B#on@%E@%j=Vefq!LiT&
z1b%070>>eGk+b<_0JAtN>6*>vobUtU66bk;kQ|O5ZHaR^`^m%0oE0u;%;St*2Rxs%
zgyI-iIS$D%U%<IffxJSFX*=fW8mHU^28%cs9zwE&)A}halydT^PPU9Q!@dt}Ip?kz
zx+^&EPDg7c=Y3lIS8*n_@S>XY9PP?#I1v=zuI0Q-d(t{iH=O~y&hepRObwi@_hG(~
z({4m#6KD5NP}a;jPgN;5IL8FwZgT2&ps$tFaSD=coQHiN?VJ_EwEpbi7?wbHC#NY7
zGF_as_3*TtQxk~B9?n<!7|b1xKdp4{awHVU=;i3t5V^-uQCz%_lXw+eKWFALkO9ur
z8_@lLbBYQ%205qyg~$+RTnqRxhe^rAQI0>oaUS9qq5989oK?jb_G8Z9l-qy8d6}YD
zW1Rjf411i@F$QfDoDV3gH_7>jrrUwL{AuWR<euOI=gdvJ1I~q;F&~y(x$%_T+s`ee
z7p5Dx+6_A0xtg;OIl#TX0{{<h`iBrX#BB|oiTm#`_v7~=bA;Pb2y&D=_#I@txHqG~
z9p`TN5S%x6E+uAtxNp;L!<W0mhQXZRmd(LnPI61{!jeCC*{g6gfNQ@ETp)KgZSI1&
zcPSWqihGaFa|d((N5vW;+=gQSgmGV_g_u2@n?o`82(F+3B$B(5f;v%L^IO12b8Y8g
zDTXVfwfJdnSv3%`+z<RA8OQx?F8a=JYgS`0@!a_-03>h&AHzf<cbyKBN!&78048(A
zRBxWbji6BfIj+}VP?pAh@Fk`s-Ohc`3Yx)vXA2OS+>^&3dY&6WkLfJ#3ltp5=6V)F
z<Pvv1?PPMecUyta<@Qik{4)31olts(Te1RU%Ht|&+ndkzh(Tikcke8S6mlD7@bDVf
zh3Zv{xaU?uq?mi01=Xco`wPneEaOh<(OJ&DNHs2%TpqpltGG^T%tbYqL-ErZt}i`N
zYq{Ikfz)voJ<wgx70{Ntf$Mhwq><}X0bCPTMkm;sxq3P`c!T>K?Hz7%_e;^&!kta0
zyW6;_GoiYjd&KSpnGSAw0uY^uG{Vv??$rkPbekKt5-#>|zpsV+ceqO>Aa}V5Hv#PB
z_AQ6xJ+2eoIQO}^7D)DS=iG;~e(tiZ5E<b1(F1jm%cU^r5O;)DXTw}q3T2IOU!&yQ
zC|8tCCmtSgn;wCE%>9JwLY{D+=|$r>w=WU+3GSD4Ax?7J=#y3sJa;Oyz(<E;p~i_f
zN{6?cd9Qy6-LAaLd63-CyG|iiH(t?G0J!rmoq^j2c)bNsc91uE5R>4+<JZ9L!@O4%
zlz%wFbBspkQJ#X{{>OMz>7nh(n?4I_ym$us*n$tQ!4A%sx91BC^aSsNpTV8v$sWR>
zAMYL$0Dqn`5sd-7MHHk6<W15C27-9cQi?E`cg-DMgz%D=fD7gQNDGrN-rIOC<NLe3
zs>_)CNFF~2zD4miZig4qyw50YdYX4(9!40;>v|UWINr^}@cRt!4lUBo@(NZ!GM@Jx
z6YvCHr4UM!c%S|TEy=uNbpNFArY(lZIo@WvQ&V|g&Vh$%yzwv5n9d7H!F6HJ<P|&(
z{CVD{RNyc0qUdb!MV=?U_Op1KIB3k~t@VbsT;5$i)LiEE(0=s_kIe*^$J5d6l+XL*
z0?1X~@HF^a!0V(ucp>leXoy_n$yNhi#2fksq?l*8i@p+`JPSiAwez04h1N3O5jwR}
z&U>CB=@mRRr4uT7yBgp{74KIqNHuS#4Tu_Eb~s2a@4^+Rxz20bgHbf_gy}Hf$Q%70
zl1)4Zs=;mM`G&*%4W7Lg+)du+Q^2+G`u~NYR^AsBG;8D8T`Anv&I_j^h7MjE4|Y3w
zna7~}7Eew2mfJi&l@NFFrhf!W-Mm>pU`l#;$=Sf&;mxKU{as$O5%6AKHQf$<yvmjE
zqMsKU3~qq8>j~fwc&h8LJIM2-PfQH)8kfVuFmJtm6_k$fKKLC<M|pj;;(W+kLl@g4
z-XkhbdCc>_1TUWO+Q!g0#?#R<be#8|5t0+Uir>La@?M}xaNvLW9+W!rx7`NLiGT3{
zIA?wfZDRNHt+d*4<F9)Q{<`x=sl4z2f7&6s{|@rs5QBK|n`pg$i2o58Jj{<Q13AKf
zo4)RFl)r(l&SU)U$7uB8Zy{%n^J6Ha?9DIg2hN8-|9`OL%RfbLvlIO8Lm(&lo)l~J
z;~${ajz9kgihT$0FP=mns;}qK_a{#A+o=3Bm_JA*xgmTXTET_#Lunrt#{YuqU&8sG
zWoV4xKM021NdAM*AQ{E)p~zG;Ke`EhG5pj21BvB_d=4+-_&aDlb%tMG2G`E=TMaN6
z&%ZhqB!T}rh5QovC$Z>9{+<6U<%g5`7jC09g`ZBxiO%tz>GDeF_s}ymgKu06kxc%^
zui(siel^|q7x+O`L2{9g9XxIo{)L@zCY%4{O^{3cd<ypE@Tc;C%jLUFK=KNo_Y2(4
z<9pG!sPg&aBf#0O@-yjdZ~?#jHV}pUjf+99@jv+m11;ivQuS*wzmJ|GCHzJ4=qu${
zxdLC#XAEO#6@2k7G*<F|T?n75_;X8utLAUu!(a`6DSe}*mLHJ}KplSzWk2irw;G`H
zIzM<TL>lb;<3W&V;!mvrY36Tihv*Id47vhu^6yiDUkm><6@0hyzhDB`#t+s(vYoG?
zEp-R~?+0k?<QLK_@)qAtq1kSJTONkg!#__e`aAqhv>m(4|B({!y?oirAouu3?!n*t
ze7pM|0Q>ka#RAdKZ>0#;0Dmtf5FYTgw0<4pAA1cV!~E8AI6T5XB!r1k{%8V}KIDIW
z2+lm>&rpIq<~P&H<|q8`UxBhQ{-v`J8RvgQ@#zWv%iBO41P)X|<tRwm0ZAu8ko|Qi
zbrz&hL6wUjjbetbg3kg$_6z*VVaZK!@E8#8f>N5N0|MbX=sqZ@JqM9Pf<Ng=d{{6g
z50;Jyc<0f0R3M54;F!Ql*Q2LkF+HWd1fvv`IW7=?58^FomjK`+aNSS)KVQKctD(kE
z5O5rvzu>uNFx~)xqa5Y~1>=-J2ofxzOw=jCo)_VFu;2u}#X|(SaWD}o@T2EVnBW!@
z(-kiGas-l*f<3fJiV|$6daP){Fy&BV1ix*Dh0}sS%3H(=YWC3o|BDm+*avUU2<pdx
zI4gMJ3y^q0^{W6T2(}%7Xp&$J?Rk>1l!m1gK{dVH&Iz=B;8F$dR7jF0_^JRR>4IxB
zU_L`ITZmz23SNkT>hpq^H$vosU~W4^vINg-0M8cmoTdEVB|#PC=yL@9bhas1kozyl
zWx*MW;9n7F>tP~KaNsCNzTmqb0K6)AsT@8P2yATVE)sat>bqFr*A765;5pjZmkOr#
zK%`6%OYf+1!NJ{drb19dE6z%RB?elm1OZeBZLby_kONU8kl%-BonW^MW~g3}{4qMO
z3wF>a9~uOr-4JOM>}Z8Zli*$eNV7mq1?o2h|9b(tZwjW7wiZDeJ<nSO@>Gbl3p{Rs
zbO>^;!<kM2yBK}91e?zScU$l#rDD760%adsy9I|&z*3JuxCNqj1i#k-cvtXX3S@c(
z_x^^+eZh^D5a|<a`3RQ!1wp<T#em>YDO`IX_}K|$P!O{PfFXf}4j~T<wzNZXM6iAf
z;G+VQD*z7#%PH9QMDQ|gUB(3VgY=V(3*MqA`-H%UVsDdz5&8^;gK!p=s5%NA$U`UL
z6#5#kv#{VF;9Z2D9S7c3_|gVUshe;*W%b;JPtz{+fN=XFICD^V))A5(!tL+EnM1-{
zWP4{G7Jl$8bRH417#QbKVW>S6oyUYz%b?p+_`V9{xX_PIUwI3EH^YRFFzy_HzQU!2
zXgnc&OA8Yxh5M(2^AncQ(%4_<e+IY!;oeRt4HU}gYX?EX_*0mRV4)M0JA?>#Q&~r-
zaHj}dnDBHGxNxCkjU6T;goQCM5h?UeMr)MNi=Khe!cEy2Q;hISDq%b=G|(&SjBp3V
z#m@@cXqz7|9HOj1f^c;gyhs!-K|S-#B;gmdX-^jZ(*RtG@FfbNofCGQ2A3+7RDw$r
zPN7$8hH%xFwEoN#CQ>c@dEpndLcbvVL<IarVcQoNQ<iXE5$t9QpB19-lJGDE8FPdg
zi{V<X@HV|&E(<r%o+nTEHDwI)g>ov-zbgFu7mxzsln7WV6sFQ^|C%r~3-BUg?@7Rm
zh4;79`m;nB@-;+Dg^mj`rZQprRhX|3YG=dYO5uAv^i>HjQf{JJ_|-%BR3ki}1f{jY
zGzmzZaDf)u>V>h+(0yIFG7wyY@U3Pz(<qEp0B}S2&j>ucDdf>=v_;6LlDc-`Hag&M
z?-0&=2cz#4o}jtx75;t{2JZ=zX?JyB*hwe+`-F+DApJtE8Dv1XmexfNg#EEFF(~Z#
z9FjxA<Mdw&hJ}4j7{rLM@po{eLjEfdc_>^?BYPyAvjLKih3kF<{E2Wqy>`d!!UTGx
zjSF+%1!6*2O84KS@Tu3)=pYj80>V)gum_?}qTs6-nzP9MGa6k)OJ2r!T}AbDx_rNA
zoT3bFqNBgSpu5O{DoqcFexi%~poql)&O;PIUq3x0T1;i`hedB4gO(#AyYE`4IV##s
z54dBZ3;TfZ6xD>I(MuHX1MavedOiBQMYDDR?;{$ZZN9Il&xXlAAsRRhH77++G-&h_
zy-jauf6+?%nFB;8=usFb`h@a-L85*13_B%qr?SRiQ7XOJLqxmm{SXZmS?Na)6V0xJ
z(s0oj<#{4RO>}@LQq&j-e3a<VFCiH%iW`PVj7Yf%Q*v75{XR&nsLzBk#fcvM4UsdV
zCNGTltf;0DGZQajI>7A&Q7pYT6GbQK5=au2EQh^h(MAr%jZ#EcHp9d@QE>pAN);7R
z;vr2mM1_>;qA4k8%n&WS1l^gU{j|<MFZzB502f5dcB3&{G(mO2mqewGz~zV*(PArC
zltncRmqoYeOw<+87?nWfiFQW=o-eZIpzo@vbS-^<zCa|Rm0zLg76mu2iQc7WZ;>c~
zN)n1iv2?MOi2hj!e5ok-2JDuJB6kB&E{dVmY=!7I+9_6w^637n5_R&?SS`8~iSgEm
zE>eP~Rus4eUet+hPC`q)sJk1D*G0~;|K<Ngtx_NwMcy}|rb$#r$>wHJA{~giA$oNK
zl-?BmkO4%CXp8}Tt7vB<yl4{%+hL+z^uf>IIz(SkK(13%Leq6iG=DvQrrV;Ir0DAs
z)rNuV7WM9cmLAb(bi(3}DCjE2X}>G_y%Pp|Mfa%i<(_C7{Xeh!qV;q)_K9X-aXYhL
zv^o<a1EMxsXg?6?hrkVr7EpG2NVGp6BEur?b=Vyd<?MxrqoNHp5P2wCO0kMZqUkb-
zJQlr7OX?@0$1^b(W1^)Lau~OZ1oUK_5H+uXi<6?=uR^JVcuOb{j$)r9kZ}@6QNGk!
zY@mI%i@547D0LP8kPX0oF^ejp+{6nV;F`Pm<cr`Ah$pBj`k;7=37m&`p$6oTc<(UG
z9~S!`hNH*Cx7%RBQ*3t_N2`~3A02@?E*_?;Y;SStTp)bJdJ5e5il-fc$O&=F0&pkA
zr~WH45r@(@-TcMFw73iqKcwwkp!fhAt_6vs=)ONC4xubnuz1`bZik3xDWEe{JiG*>
z4-*%*qc2<>V5hizg!luBbwrBeD1sOze(np9Xz^@1br~am^Er5WT5R13$yjkOMZMz0
z=e6iNBaWYiNjNKBN?FKwvHt~d3F0+oz!SyiM<AIbPJ9Nclf@;pTSyV#`U%`Q@$9$Z
zMXGr7L5hE-iMP`E!E|vOIh7%fp(t*q_#1!7oEJYc8+{kVm#7HnqWBq#)n|!s{I`M=
z*He`Jk~p27dY8o+Apl$vZ=e$%dE#_6W+q?!8a*MdihXxNb%FRRdS(}j1F3N3nz$s3
z>R*b)Bklkei`DeKsuFPyg<(p??ST+26YCl<rRCyWBN{8juCt-7QtUVn_!{vJDM+n&
z6Qz*q#LL-mv|ilBfU@i2W{S=?h`T8C&?v5_Jxh}~vk+RE#le*Fx*--I(Qlu5Q~U=l
z5?jPm@HewneDxE^w29mN!L^ICo(Aa<_fmwZQ|v-Ps9Rz$y2x*frL@8B5(jPq=@y@)
z;@ckayRC5hj@WB9?A{fhpd@Cmc+>#+J#pz&IC@`f`~*Yl6W=_HK6}6TO#y%d;>sj+
zJ`k^<-(XPeOTnZev6zzU!{RS!y*(mMp>mc{aTx<XJru9tgL@=S;6u%0aoBDAzE8x5
zDC9UM-gOu{$HnjDVxSY^)f*r(Db76#*Bm5Y)4!#3lpMVUNhiBx>mp2>vt%JH&s-$8
z>22sLIZBtweo4TK=yQ{FKSrawBxySg9+2Fow97%sy5Hf2hh*Uo@bHktp#bp1lJ|~d
zXh$S_=Ky|GQgI0ek4Xen&g?1qHXD6jlEsv<J1%)%31!|A`}@=3n~!AQN_6^4lpbh3
zA^9J@@lHzSlNvusR6Q*DOTPL6k^z#9lt>GdxPA>Uf+Ve!-99B5p(8)RlDSmW79#1O
zFCT?Uyl5#ACUIE<55pxRTLF)f2<c%EEfJ-|P>jUWPJ92;l1*Vy8Y{WRKx>?2;TW7b
zBe|Ij6K5qpRP7rt*_aEF1W7{{8WSbqR&Ys@hBu)!SyE|)mK4cS+K`-+)E$PFR7puO
zxHQQwdiJJEtj@5TA=ymZ-Au_oDtA3EN&CzWH5Vjpl<K=ES@;;1vLu<O(U>hcGZ&(l
zBzyVbawIW_!R1P(xniJ~C9b|8S0t=op*v3!;}325l6iFFT$Pmkg()eJjDCu~LP;2f
zl&(p>rHbn!Nx`d7RxEL<16LyXC6o4lrIN+{&|N0!pm{Ercx6Icg=8Ha8m*KxQFO6N
zVhq4wswJ;eTDwN_(;Ki<EAgVm^mWN1N?SHazK#KDlz4ieuSw$g4f>iTA5t;g4T(4f
z&fJu&&V@*eWCy)(TO|o=X#dwHIi3Zl+9f(l?sZ81{2aheiJe}tw<O+?@aeW>-5NA@
zNu~)wy7Bvf^hlb`0Nj!MF%IsoM1B$e_DY%~Vd9?TC;E)ieMx!@;C+(WRp{%NyiF^p
z0m;J!@bH1;wG4>Z2PFropm9j@Hib-vC8PP!HX=!)s<KhZDAg%Fl;kyG5+6zC_yX}*
zGC}7KpGcnn3YNws&r)1qTryb<+=Rq+2b4`pj!c6x2k9INm^w;*PXXX0jixP#vox>+
zeJ;|cH$s`KUCMnLi2c%Cl&N%+{_z$N?$XmA!|nlT**?e|l**@Lf;^<*^pZIwZC(a#
zhouXsj`N80j0U))(qoi#IwsxM0xvwJcUh41l0Kkq;Bn~$T@c>V0xHP&k-nh;@s%$9
z0ftUU?O#(~>!kGGZ=uFd>arM0{iV;)$}d1Fp9<FkrDv<4CP*4fwRoqbo2U*fSo$=j
zRzjrlQSdNSYVQUYCN)t8I$WAW74Z>Lm%jjrl+M`(^HEX(B?qFVzj<LSu~I*Zq{T^B
z*eM)yMk=Pa@mc8~6oiVG&e6bpg7lANAc@jx&p>ICbPnaNlBK15kQC`3k-(jk7QTmh
zN|ipD3X&%6r`=q-H1Si|&5#P{uxO^V=^Lm%FXjIQEf=I4=n}Xny+EgNv!vTDQJgDV
z8c1QqOH$D)kR0h#EijQQ<>Z1~mU`3T<%+anK1}3EqrZgGeCd3elB-f>9xN3|-=&9F
zp>#VNBG;sb6ab2(MgyEFmTKRG!4m1yd`v>AR8Rp6Wzw!e%v!m$)`RkY719sifwoF%
z`v!DYN!PsqQY{^dgryp31s6(dr8SflsFS`+FXMWtjjodG()B%%Y>-ZQ3L?$YVig*1
zNHeJ(<fgQr3SU~Jg_Qbgl}5jU#x`m7FkEYw=8wRc4r%o@T7Py*fBh3`Zb?Oa7`!dr
zM~kg4shF1J-O~RZgr_~yWUA4;BRxa=gS*n6W{_U#z(L^dNiViR+kNS+M40H4{_-IJ
z{nBSYfWHIMDdU)g2ht=KlnqMPQkr&18bo!y!_w`v2C<Jw7tpJHRQhZh>^_u!NxOze
z(oc_}^RcwyXEZ*MKBAPtnAB1U567h}DzcoA@<w5IQmXWXK?j-Y4v3@dX<80C$zJ;#
zt~txDy$iQpWJ909HCNfk6r0&EOQU^-o9qO=N8If)&pK#3AgiDv_Jgvry-?~Q``QDD
zBQgidcOI2}`YXIRCiA6J&z`a#T6TNMc(dWmahbzeG<wUH-^G;p$ckS8&R2H$Tj)L^
zi~I|!Ps*gr(B~&xO_h26vU?O73Xl!{4lYn;zfXJVAlc+s7;lKIKNLzsWxNkzB1|@g
z1JQ6<&hr>kgiKrmkx1FEAy676<2%Cyo+wmh93%T80@_Z?_R-rrR(7KcKE=tF?}FqR
z*$qnQo|Qdw0)6qatFtir1li`DP?jijwez7nNf!D%yhxUvqPmV08FLKWIhhAtbE&d#
zDMpzl+ZctRrOV!#ipC7tmvr_eQ}#X8`<$0;ZU^pyEb%!gyC@5!6@8YB!-0ux*?}5}
zT#{Yz0?Cmb{T?E@G8J7`mu0bGRDXR%c8Hc&d9nxeB+r)#DCK=smPe7P0@=F*;0k4%
zroj9)S;Oy8S|s!515hlRIR&FHkzJ#Y&y~uyRiUp;wrD>5Etk2B!$hSl{2DA&$)?T#
zsg@-w&{rdS=QB7{EBo_RI{#27n@P#ndRZN%X0FSwM?zbJ>|F}gG|GGq!$gzp?3X|^
z%Rb12<PF*8SE2i+ES0K5T4WP+CA7*qDGt&hi=u>Xr|hRQkh~=ec@2%XWwEY+cga3I
z0iE5lfl>f^WVb4*{^gErgdQJvWjB4`Td(Zzk1_0fvX`mA=)O!X0@o)?p`*q9vfMYI
zZ9wMQ3N;U8e{=vaD06-qx`$+UxM&=fU0w#<h%BFib)&LMDrI;md+-G0k*swE`X0-E
zq2R_7*_SpbvyaK*JV3`~UZt=!A+w!?`;)R%7bta*Zyy73l$Rd{agzT|fo*3wV-f%t
z`BEy@ca?v+5K8yUUrR%un>>($Iqq@}9fmp}_om0|LHVB7A?YFC{|PJ{lGjr{`mlU+
zDMXIg<+GE3KPqo(g3K|wiemkq^4FH2(@XAg1|vK!=S6^c%QxhJ_{dk%j=)#``UQ;l
zg#2zKhIUfE_g9$rlgCd$nZLY|vY!F+g_J!Bl)oB<z99MIH86il&ZiQ@VEIl;x`xQ@
z-%;#5RPI1=y)gM;9Yn+B)s)nTkk{Xb!AN-{onw!ZucSRswEQ#L7{ti$eg?p4c?Z2z
zW93_T@IFrdh&JtK<TC=G^Q`>92nG=^pOOYHK|V7aBvHO9396IiVHaU2S#Ge$0iPm&
zmTt#$@-vi-OqH*m1};rrxf%mamyhOvWXRv@L0_i4llB+q<$vFVr3>=UDH(E6zJ{us
zv*d9UWzUw2d;z~CZ=ss29Qi$GNao5lf57|8@@BeL^W}Sw!I`UaCl%%Y3gjRB14N-*
zY6Rk%eAP*G7Rl#Up|4ne&Ix@b^1LSWmCD0Tp|4E-NdYXC%iaIR2rJ}gvp_24UT&~d
zCHJfVsh0cr09PYVZUU*5CtL=gPQGdg=IiA@Cjf9={%Jqu{~F{D>oL!b@`gv~Y?5E3
zk3ludKc(&Z4f(E3=({Or(DJ!OzWNG)t#Toyd)nllFG6X%Jeu}X9di4}knEISAApCq
z<X?wkf^W+YE{D!8x%7Q_(Jh}h36UQ8OFj^}Bfo?og?;8-c^$>jdgaIeyYb}n4?yO=
z{A;Re>65Rez*xV03Dx%w$X)14dLZ}x7JxzdU^1K;lD{|u+J@!%UxFKv%cy8~R9?fw
z<UN$f(n+#M@~{c``&hnp0Lq@oPf^T#OuqKN{olBpOKXV<`PKzcIw`jZ0d!F8oeiaq
zip7*_a8k^n3(;ATnSw?a#cYakx++%DMs>d;hPK3R3ZH$L1b2l4z4i|%Iw?JTP?1}K
zMi0dldcYh~<h%s<Va1$pVg87sss$oP?TYbF(Rxhr;||#MRJ=<GWiN$(3CMB9_u~-t
zRxDYBK3~P+dW`;rB9KaZPAc}$&E=<<!h~*r#phWd0gAF^Xbe>RLM2;4iiCeLq*IDw
zdeH|fLR(=dMDbBHxKKsS>mXqY``ULQ6RsGh>aGaIzw2NkQt>sdzM~Yg=wM2;;-kNz
zEk?0Gh1ol;D3@W_u?qLs(HE!ap&-Q>#kZFsa#qnndAN8*&>%z-6m#Z7OQPa<AY4mQ
z{6J5iWW|(r^ra}uD4ljr5o)J^YpSB}E3j#b<FvU;S7g$5J3}GbgT73K@pS;tD<Y_>
z?1G|)KKyb~kxC}A6uW32maQ0~(C#J0oulA#6mB%oT*YQ8tGcZC{5r@LMcgbX%Tpvi
z1rPHT&r!VRs-i3Wzxz*dou0^rifMmCrbw})4<?EgA2_42L?Na`cBx`@9S~&-58CsT
zD}Fr>gB6M+9r&3l6;D$wLY3mt8{n!H#q`6}C=Ss!p;nO)2S@7^f6=8^ub4$IiR+4&
zC!wW5u{DSO|6ilRPTS@t#o+HiG%J1%fTbIXN*#bV6`#F{VYetuG4P^Q!J?;Ln<8Qc
zw6!Z{H2~M4czza0r(%S1zqb?tv}d`kD5ivcm*OWnpw+F=U5BzBg_`QA?kJw6Pp#Zl
zME`gGp;uumhg0_ye^Dg-zCu7hY@fpZF--I;By@m%K%rTSxp<&hNwKU!#nM9fG^B|7
z6o6sHUs(W*C|tu~cT}-p3Y>YU*t!CJj}%kO(fC*~WdTH<D3<?$#xcdnHh3|v;L!@q
zKB0Iy2Qrh2=bPb_gED6cJatqS`~c#j9Mz)HRk_(82KOrqcZ0YoD^NEu(_Oi08OQ-;
zD@CLaDzg&cuZQxJ6p%woy&v2@tlT97cSPCq0t_Bij`qReG37tB2k=y;pMZ#$UAgTC
zIDA~0Ld!aD<?LtSsgLpuz0Q1<Y+uNnQ1;P+_oVVYI?Cy%>@SCizq0Z*m=91o7lQ;U
z<7pKfq;%VczEjGPS20h)%9#()7oyxi$+b{rAgxrxl<YsCEL{2Ta?C}9((W}2G*ao^
z1y7@thp5;wTIstI_!#BWlq5f`bd!R_DqG$LiBq;7f~9z+>20V<P%eEBfJ9}+TWCyD
z>PTs_GK4k;Dayy=5ILuus)5_7%Bg<<o~Cq607+Ly(nXe`%(sWbsZ8bUg}|RzhW!ZO
z1!d;PAQzRpXlApN&Q$A_t^9BTjhB>fx?zMl%G0l*F;}^hZo|vUrJq3Q73KbTh~z0(
zq+r(am6u~N>sOV3(QdFnxt?-mh05bj;I1imZUL@H`BEJ%P>PlF=@u_h{$zqosWO7L
zdSyx*ZKBJS9ga{_p?v%+`YM&BwBD{#io@Z4wK6dVjWtRuJp*f%o9MJ=ozi19`s$TQ
ze*=D9=|L~22Ib-c%uJ)w$r+?cS<(ix%}Qn~z5i|~SCFSSl@IBYV=YRNI}okPd`k1S
zDWw;nrd|2iipCD*rKe%OQ`t#{fwz<kC@0yibWMX~k21@G>AIsFrwP8R<dCvn<^T48
z+*7XI3iy5H<0J5}PdRTlNWZdKI|c8*0p+Jueegh;Qvs!e%6oLsYDoF=1ptSY<-Kri
zM7f6QWk;2(sSf3#GI$>hK2rYh0z@7wB?BN&lx8{_Jf<u=1})>tfN^M<P`>32pC*;F
z*?>E!_~j6BRLy+`^XsGvqTj&otkTbgc^8#{5+<&yOxh*wS8bqUfNrXLbY#z6mHj&q
z2UMRv1^hwPlKE)#P_6I*cSu#t!;~CW_11tpq6(!&^ikC^T2`G@Z9D<Hek!jSApWYE
z-$OD$wY(R0166O*0zJsC`h>DKr&K%&-v+B@=+POXy7&#aP*pD#4~D6fo)8UJ{h|aH
zp^|n25UDy%tGg)G4LWiVt<ooA5HYIPAEEEG%KZr%V^u}<a3)SAbp$!1V(tOptm+;`
zZ{t<lUV?`SDtqf^poyxb`(Q9hmHZvJWL267_!QNX>Ckpg_52UuQdJ35{+6aX_bx=z
zRUiHflA%)3*``d@OKa)=Q8l~6#0Ax_$6(^3Y8Ks%S*rB^!F;wVoMLvDRB?yUn4_Ac
zCwQ)^-%cyBJe8IOZTTv*KU%M<n6$JmP~F%KrG+XnWk0W}ZvTV6B2|VOYKm0}+t62{
z+DQw~GF3O#GL)+xP-v(^H9_YHDphgUK&n(<rNTnBO8O97jq0687)z}xdJ){NQ>_Z2
z`>$SQV#EA(Rna?;X;6*RR-jS!H6`_%R1p~%cC$+O8~R#QCVDQnssgki?W+FEfOn{*
z^!Dylxei0*mP$_v``fC34e+;1#k~kE-KsW<UH7PT8=&lt>KfI?+*NHqOZkUh)%P^Q
zdny4P{<^PvaU7j}sx3`W+OJZW;o5*oO2;i9sOHcWJg8c^7~GJG6#{L;s)Brw5!D(h
zsu@*%GX(}8s#eo&^hm{|$nIm6@HPNXR2%Z3b4<0H;vnOy=2bIr|4pcZ1(>!;RRzWF
z9MyYiRq3QY76MUcbu$G5_p2G<=yOwd7Gh}b>RE2^;(&S=MRN|SZ`feTL!JKt$Psl-
zF#t!^^>ZO|Oda+WM2@SSsFuK6eWC~=K57>kIA3)W{e<=t>IHQWJ*igC$CUc1-&+O~
z{^~7sc?GB+Qawqax|ebVLF#{=1^$$}y8<G?>Uc_9hNxS;z=f)}?}U~xHGdS6;p&R_
z0gq6>*##1*9xKHFqtrS&j2Nwcir(HaYL*<zPTSR@pV1ksP74Q#Q+NEALRM$}1Z`*4
z%culDUi~YbF-lO!ErBzM>iuh=CQ1D*-Kojy^L;RpqR!a~?wtDDufe6Nx6sF+($vQy
zpfg>qErX*O>K7=ol&P*YVuH@AXB`2#ptj#>g3^oX4`xH@C3UJAz#R2digxF!*DZnh
z%WB(3kSl8ShtQp;-j)O|U#+<SrB~IS;c&D-{XFF#3e}yt5V@wFb_SM;)O=cl6sun{
zf|RKLx&czEUd98wOkI=-v*qduJAH4eLj4YvQ&*~A(ZY)=^>hkZR;zonptMH4^iRxJ
zt$Je^fOYEbU~moUlT;SjsLr60uO@X9t$mu+>A4^`)L+x%?xs4C9_uaY#A;Y*RWFzh
z$u{)}J)k<(6BNa{r5<sh_2+GM;StF6sk`2W?tb;D=^z7Y1k!PltAAeukzw@<^spaM
zKcS;Lqw3NISbC_Q$A+3mYUg?2#?&5EbU&{Co>n^(>f;o$chvkr=O3Ijn_h($XU$)f
zR(8?E&?zQY%^N$W;{MyOd6%B@$26I5Lyf2ArOUXFyfjZOhxy|gCpyjKt%<q>OFo(r
zIy>X5siy*#6Pg7SdN`?hLdC*<nmqcRpTFj<VDtrOK6U{YsPU)0aFE7M$DL1UHqumv
zXvXMT3)TE}jlO>!rs<~WM!4oKWhx^y2fDyTYBtmJCPowO1K?@RU^e<<H4F+q$7u?>
z;OH66Et;pZn!jF#rFhMJD&k4dM3q1!QR9^cK$7O59Png~F${ev8n1ca&S|1nK_peP
z=vRo?(=@vr(3!4DZG%%8n#hk}_kyNQ0?}+udM&t1nr)wh<Y*R6L1V6F-5=mCYmRmU
zcSYm67n6{uiJ=%)zUK9{P<mBUKMKhLjoT0$Ez~^Y1xK%GOjH_Br0M?+xMI!EzhNp%
z>>AGJK$L2{_d}*kBcokXxkkSU_zKNT3%E*6doB8^G;6;HzE*QI0_28f+D7<$Q<L&E
zM&F|OkqQl3HIM$m(AqS)R65nJS$Ydxr$+M?`fh1Lnjm>wGqwiyx-`#GsH0nB-?$RA
zN8?MU-0o<0({kgkW~Cbt_cTtFB)G5X@PNa8nnqf@^lL8ATn=bzQeggpW-sNz2Q}wP
zp>#;I*8#2#Ym$$G8`0cJM&GC=>qpGYBh3st4*OWsKLjmLGz<Sk-<W2povQc7HSQdY
za6+T`7rG}kp8tS2XvMUGbJVV<(1nwB#00#v_S_!;x@b!&aOtXz?tvHkwX5zzshc+L
zS9tHP-Ah;50j*~MBoAuyD1C86yMroQk7@VOxg}5SmS-?PFRlIusxCRM^`xzyw{|my
zqJ6Xl*$_Rc4ZVrM_-Q$moAB4Ba-lmwTlFsb0=1Kr><ZFWNI*_$S5x3KSUaC?$`I|>
z%b+DpYp1Ynxc0aE5Q)$_1wmP)Hu^KbqqJMzgZXG}T@=MXW3;<z*?n3&I|^!IwTZt$
zO`LZ3TR@!Aem5Oz&T4sdWFbNO#!)mTYCob0PSRF=0yW9n_3lubqFtZ^m#RHM@uoCw
zTQ$5$*T$ZQvJCBp^AO3@7R3Q~UYm9s+y$)=_UtpWv_n&1H(UGkO-$P*En5mMM|*1>
zrZiW(j|JB*Yq!#}{fgF23=@UgMUD`;rd?Zzz9MZV-RZ^J3l#Dw(FRY)Je6r{=(S(2
z{jME-720w-(Oj*)OdqYQ(ORjLs8+kK7k&0R?S9&T)oULY0N9{iRtCF`+BfLDa+6lV
zf|{G!CvT#!MH_F$U|O~1QvqnxdQ&8?UAy=)03F)Hivj4=w*Lmn+uF*LknGY<P$_%2
z_U(G~^=RK~g%@|Up|qmEtG$>F(redNk75+}v{&i;`+e;qN>dGJzrGHo5469RLCv5x
znRZY^+KNx1dsrKL3w<Nno3sOZs1;7bTt3p;sifht_WgGu@<jVUhQ=}N;C85<)b`{<
z(m|(K0^+FqavmC;bb(@c@2s;=qldPOZo~)X_v?5sL&i<_QXq)CZnz(!2XvXOAP03_
zREuy}*VqfmBf77s)bptB9XUKari;vih^OwUPe8nMn|lC1uG>!OG;iIbT8Ny`{dN|O
zCv{VQ2Ha1#jjlC+-F!QRCjxZGUP5b-PVNQ7DV+-~>w<N06h;lzHNJrHhUw<g0zX_=
z?}5pW&^d2``AFT5^-vR~d-rYh#ps@1fyUE1^Gq0w)%7sY7^fSfLe(?60w!>0b-na-
zPtf@+g}p@G77sgGlXSaiRhg_?e-$H4(M8gHrRny3hgnb8HQ1mgLznm-COA{aBa!pE
zZSMnrLH85cy{O}bz{4!vTWKKKx(!rHbV+ym4*GI*f=6&BS7)Oz^<~{5Dh;@zYo?O&
zJYCc|+W+P2B0omwRo$r#Fj1h})&w=zbUUxY?;;)k4>qoDUHV!$TB7Ts@LZ`*m=85&
zy15bPE7v{i0eFQjl8VDBb>(BwQl(3ZhxuxqjUu!)y85r7vsRZ!OY%D1Im%$w>$>($
z!Ton#_Z01G8gzBE4{Ov3RzgjaE`$nBn{`*HbmWFkO_jARx&;#uY1P$I+OtjP`x^S%
zbq6TJ(xLl<UQV65Wi=T6EuHW)^xf9orm#Yn?jZy4Ze8U=sP54%q_V0zI<NI`+kRI!
zJrsyu-Nri@+C5!D30m*#V(GI1eY!4+EA;Esl)!tSOTG=@pzei#p=L-o&xpQJT{Z2s
z9_j`PKpyF$<3S$lbo3g0qT5N2=P})JAE+MJWl@N8LU)g%)swnGdX_lY_2;)?Opf{k
z>mlQ${~;6zXZ<p|@m%yTI78G`pYseF_v<4wfpF7H<6+)i?{pY_2lOS|;Qc{;=?Esl
zLmw~#+#!9N4cuY<_AKCz=$)g%9o75M&gqywjW(K|`T+yXdg<-wDQ<gQf64^ky!E$F
z!*3t`rfzV)`d#(Vc0&IX{q`sIu8Gj*r;m&R=dX9F1U^9jc@Y4C`WPL&2-1&Dh3-@O
zn13J=tY2{tfDrxAAV|1=NCNL8^u-jFjMQ&=72Zebzq3=oC|W;fIn>1HU%m(zPwV^N
z2Z_~p)0#L=zpM@1S^ax{;NtbN(;x}@y|l4N(HBu9{hYpHC!9&u>uB$ure8)`kaYdg
zWiXhb4=+JqrhYqZ`p@fo>`-<=zaj(nF6w{lqW52xeiskgvh{(R;OQm(!r#!DqmKzh
zU#@;-Hk4l0U!zUS6@AUmkj&HnxE3T|uP=m&tNK)0Nfqedq4!9kelA@>*Yx-3t|-!X
z-GgMYzJad568)E{&{?XNl><<wHzm;d_i}v?)&5rKU!#KlO8v-VAgc80&ETr_E<;dS
zqpzSWX084kTB+9QC!9d)^;0Pla9#g$4J<Y2UtwXOjrv~#z%}W=*bQ8>evTExzM;QG
zm-9{i;VBSl(YyG;i&lL<a~AHuHobwepY8gus64qt?>LTucIqF}39DQBt+Rl?t@n5a
zz%IRwV)fnnb(!FL^ub<m^p3uj;!St;)0RTAS3k!DE%)?a(z&$z`Z<f>cAx(E5*X~)
zi~7I~=r@*vd!Sc2z>s}V@0ts3L;Au_I6SN`n+GzYKYAM@9M!)@pMrd>kEWuSC;An?
zL-&}zjrMWldWj!QOz7uPW$dKhVIh<{7`{4)Mn{8&a<@)~y$j)?v!RG8Y+MXxdR)00
zRtx~X->_o`+;+1Y9ymhO-QYke$^(W^>B2Z@_<0PRhasXCh(m^d<<NcD@G3n_ju@8F
z#dg#%{d0&MGl(kTp{L;=3Y~iyMD*xBZm9YZ2E7dt5g4J5p^nlYzJ{6fayel*<NymN
z4d-WINPY%;E4|134KGtPHOSyf)ifc7H>v0%)F7m_ZJ6P`1n3SoWYfbW!mx%asUi*A
z4}e4&zNd#@v|+|_a509vcVObQ;TuXl#~P}CfR;FeyA1xGF+|Yqd)DyI8T7>)9?pcL
z35IU_A>b1YZY400WSH{=qR9q13o<E&_b<c6bB3Li0!}sLsv(kQn0OYA>4qc<0c03H
zp_<1`!@MTgJ#YA78yYVde&hmh(eSVlK4ls9gu_C%;U7v4Tr&Jng2o&}8O5%14JYT(
z`|q-$!v|`v7^YEWM4n+lh{k-wj0z~dYIu4P{4OwfQ;kZYp_<MFUo$XQ0AFPI^)4JO
zHq2a$ftDClN{Eyi)|>>O%&>}fK;;G>F-V2sz7?)j8lL+Lu2mVre*vJ{kk6p~UyWgK
zA=K0wdg<<{Gl&ntZoNTA=UJ~Ca;BrN!Qc}Fe4}CLV>sGmU~ETUtD$NVmf8*ProyKV
z!>s-2>ommEZFI}vL))?2hHs|A(Jn(FtqQvhzbi4a9z)g>^xZK`h$;WqZ}{*m)I2bF
z)0IDHI6VNwkb!v)GNT5^gBa68Lo5Y|9~t)20^_lvhANt#7@l>4$e6*Y58Svx?u)(&
z!_&0Fo;0ZFneAZorzvqXCQu~6$@oD(8l8>&WdOJsS9fAac30zz=iu;u<H9NsH={RI
zuDBcPX29VC#vQcVIB3++8Fvrk4oXBHGEPy$nZriS9_T(|^rJGEqsCiLL-#S`=S(zu
z8dWzzyo~edf;euxO37kx<ID;)`WSh%AM!O$eHuQUup75Yfj?>V{}3kpjH_;e_#4|C
z;YEOP`X=}kXngZ53<ep;#(_9xOss>YVB@&~;6jXp7AOrhUiu9r%vk>&8pDm1|7|*q
z^R?h2jrLf~Xq0ht5#Z6rLo?7AV{{Wi^=YHsX&nX{Yh1AvB+mH5EAaG;aR(jIIBR_J
zCY*^k7SX+(V7$wKPl?9U-oPgrgFZlGvT?i)N>hwSsaETpaYj7)QjNP-qA$((h~nbu
z#!yNKXBbyo;6<kK^NZll8{@WO5-u29?ccyswy{+Va>@A0ujtG%&f!5#uCa=$xi1?(
zaKq@Y7#j{jB+qz&HqrUUGdm%2)o66YC<=_Fu@EUVUZl#CYsS5!5GgYLK}Si7jZ2Ie
zS&1=~YW7Qwi>M~N%s6WS{4F=~7u$iaFp7w+G|HcW!73x;C-_!vd_DkNjj?kv5VgjC
zsMf2_SdtAj^~TSrPT{(7%m9N8#y=0BuhICNKeRL%-RNjXv+<h_h}<xyeS^N6MuQo1
z(PH$t43So&rxqe@#;uKX{;1t}fN~=pMteF8b{gNJS4WrecLrSRHs&n>zQ=fFF8b~m
zZ_dCZ+%;aHy5L@8N;n+7XEam2+<oJ7l%nV}K79pq(QkAr1vg;avKQO~V>%s27&K;6
z-OP~jDT-td8y_K#VV^l-)OBHoMvZr)pyr|R$C(g)WIRotJ~p~iDEf)<#WhefW?Yy6
zrQ=5DHh3{%%%)w=r13Xe6FZo`r>Y@GQ(iC{olM`p1`%hI%pZ*|CXeT!%+-{DC(O+K
zrn<l3g_}w1h(^1+DJlu{fNAA+SUPC(rIdk(=~)Wj9x}x`Ld{{*FI4Vu#PsfRa7Rs!
zy)bypG~X4LJWXwX0q$iQqDb~}6N@VQyiFSi@x%C-ei8!bYdSCj$&;q@#{u^<)vthv
zzey=aAL{>qq77%DX<i0Mkg4iEw4E}AZboOY>FXFELQDgc(G4}FmY^}r)IvFeaFa(I
z8Y4{KQM4@5G#&<nQKtIOK%#+zmKc*-4w2KQy{Dk%jOm?^VE3%4!xx6)O=kn)Z-U8w
z_$A0Bn!>20HpwKr2v3tuGrk3vVk+>3%sJCddiJK9rg;LGVcH*n3Cc9NltS{N={MR`
zW|^j3f@|3($usD?WNM!cF2}Tf2e@35hUW0HNkgI8D<;qL=*u%TO#?39)M@8H=BjB6
z6;BkHG7e!dg;)xs^P1^fI_Obk`YZr;i%k!x{-wlJSPQ$QrtfHhUuLqL16OVm(Wl)i
zOp9g!S81xJcWaf&%?v=b>17Jr)|ejjfvYu5`vMl~Ocr`H)SHg7X*qh`RQWx$HJGBP
z#I(^=O~v3%rj;u|noZA8A@U8=P&~*@QyA@1T1+2Nbx5nJVJ!e{rsX1#c9WkAly;b=
z({rlRl)e+>mPzy@0Jlw>wgcW}I!H;(Zc`go-SwC{C+YiVcT7($MeAMDtEdN?*=xG?
z6}Wq*8u}>3ebW*OHuRbH&}O#ZbW;Q}U<#ur%mdTkA7a>prl)9uFl4HB#9R!UO6dhM
zV)|wiL`F@5FJSkfX^s)NN2Y8F5<WJ4u^A(KViH;C{NI>qrU+`rO`WG9I$`poDD0%^
z7?oK#nEz~tHfOWXH2_`A>2#XV)hwi}_<r+V9VFe%%^Yy<=AWqy^nh7LS(}4qU)l?M
zm^agd?U4C{1kB7~^Dq_T95HtcfIDhVq(zqfm^p*KH|1&Wq>3{y^Tt`|JZ}Cj7)rg(
zpU#IGAM>pti1?Z}(UR|k`S}-M;-r~PSx7(gzaHTH%}NUY1ep8&LSvvgeFktr<`i1F
zoieA<y%}siDS=3cd4h7Vq2`vY5DBxJKc}jra5LjOn2#_Q&|MX2eyIyeqs)y-z(<>(
zp`}cW`Q1lAoHj4~8+~WYLQeqBnps;hv+?FV6zoed@1X=-qS<3598EIEzJw7bn_axY
zrI;r#gF9zlH5c~M%$j{@OgG!B>6MdV{)GWxrrCiCWzU=WjWBW1%$fiq%lu~=5ZUHt
zdazzHkFG~wj(JJ~aJgnZ1)=iHFH#mU-&{*eiL2&al(sA|^ACV4H0M!O*fsN^H$jTb
z_ZGwLVsi!u{+5{g>{~IkQga9Gkju=bH(;>bETtz@g?WhXgG#gEF-%mM=XC;KZQfJ{
zK#h4F6$;dvdzM48&iwZ)aIM}vNDqVS=2R-$Z7>UHmDOl|e-%WU%wK;5)y?K<sZe&q
zyhDb*n`YnlX#Lq@{_P=@wwj;&8u&JIGzT&rX84Qy$o$XWAYEquDd4-!R;p;~F>lWW
z{*GBq+t$10O-G@n*L<0hk@w6=uYtR7{=6BuKJ%kVkbZMN1>^?I4W4lOf!W>!Wy5B-
zblU%om^aV?hEcPgZrq1v_r<_JGVh>Ccx?9m5kJfmbCDTyF=qZB6_Sjbd)Gqgg!#}O
zI67&bOGy|9%g-$!P8P@K;GwhSo2vl0SWb*U#MQ#y4ZwbjbRR6ZSw8>o2%05ILis;W
zOJx&eyewT*ntt4}{0t0wTV`d#ypLu5i%@#f(nM)mKTFOn;QcKe%7O$~E)AkD(Bh|u
zWRS&S9Na0(+llZ#*y2uSz(On&w=hAWmP@o22(#37f(y4S%ZHW-i-b-k*dr~@-Dr)n
z9HvA~qGkF6;FBzhCz#6=%i0zU=A32Y&(M}?vCv*R&9Y_zETvoK%mT@<guesbnHJ^q
zP<q~StP6v<VCkeoffp@{euGGs<uFy)WLx~%5V>T@qF7&!CGtf`=GrZHDK>lAa^t^j
zhNY<-GI^FCX~&pvY4?Ths}_$vP*Y$@qVRa3C1NJHYnHTF^c7hWTmdh(c!i;_#PaOF
zuv==We+jzFEPrl*NV&yA8~O^%HcGHmT6U46RhHo~h*VqbT6*Z#STe7mv({2W8L&Fb
zPI9K+!kmk~>y{U3v(sQn83)&Bxz-2CCd(-8nr~XXXm!_ODXu_ct0i|UMA|HJDhh44
z=sn<Chvn+?Ae|OdCK_*99R7j#w=I!>p|Q&{#qNNq>9%}F8|)s-ZhFw%vBYse?piuK
z(b#JVc7pDEmP7>%-nY!4C~TjlatN0CEypRfIbd1#3I_VXqI(5b=b&ZW0gXeJ>5YI7
zTWn@{KVpfZgvF>O`6u)}wA_0gUOci4K1=z(#}?-@jQ5FUCG8=`EKA&Ae%!*Gg1!mM
z$Fzr-w73}nbg=$O<$8|RRa7(VWL@(cM4YXQs5ZvMx`<-muGV&{L)mX#Aclu-)?a+l
zc+gr$AI9>q{@DgE4q3-H0e9HCE|luej#&Ta3elrh(@&5&W*rQMK~HNO#a6wnHB*2%
zZY|#ogtv9tYBc&-8>sHh*Lw3;OvwrBL#in_X}wK#4u00_R*c2pdLR{z0al+SAc0nQ
z`t5_P-%$O^DeH$6%MG@^fb_6^W{B1MzYMmu^bdFuX1%Z!4u@N3o&_+%x}_V4Nb7fX
z7*mvWZZhmfTP>9Lh_Sv&%iq)1WQq{QS~qQnNSxJuB^u9IT`2T^)_O1;lJVB#3*l&j
zb#@q3Ct5$d0`o~$4W+K^$<_iYFiNpz(+c67HJ>)Ksa69;#L}$M=>Vo%m%Itx8P>u!
zG-g_NECzSpy5%157p(19z+JQ++6mXPtV2s6l5OSCkABJOL!r(b>lB)jT<hyP04`gr
z=}^NJ>%X-8&9hs7rk7*BHTMbdSFKf4NmXFIPnUe5b+sAXHET;SM2oEFqoA$WdXvud
zmsr1|Q(L9hziBaDVVy~lxN7U{eK1jDT}YwiT5C0}6Y8v!3>d7peiMRux^CT1x!(rs
zr(Z!!qt*US7uY82*!M8eYz?Mu^9}2tbeiI(b>Dr+v{=jNVbW^-olZEmS=amtHSJa}
zcSv?vmr>lb)4G$Q1h=enwm{i!>vWpgF00#X@S@v#mQp!A)^E1}aK}18;nTZT<|HJ0
zt)JWJpUmE~Zi|GP`_}d8@S@N98r?ws)-^0x8nB9<hsXnK?HIU0YYRPghOB;7zz<sw
zT>&>@{fa`^qt;b7p!=aUiXzgFtaIk0@3Hm82`GDFJwjp3G3$Y6VPV|b6OX<L>+I|F
z{+qPgX^ZM$OX`EDqpiOiemmJ>3>cHEEoL^f?YF)98i<?C`Z)mZHc<uo4%nI~)_Bm?
zz(wO>+l+@GM{ETYc|2<Srx$%*HWOX)$8F1B0OxHJe2y9Qu}z~dp!nLxAJh4x6E<}M
zI{j@Q)ABdKc4`7#pv|)Z+JbD?DV%c3wu&kff^D9!LU)Mmb=qHq+CHP@WSH$!dZ35f
zvgw;{5w^i~7+R!lU=2i~Y(MZI5^Z}Y2V9J8-g;;`Z9A@lWGo2%|JyiQY$cSQu`OMM
z(Vw+B_5dGmTTS;^g6-8j=uWidwt!2riC%`bWZR#AfTY+Kod)il&6_@`muf3}16Ns^
zZ5jQ9={6p{MKf$|6rjqq-LpdEyv;x>w+l8OikV-ueN4-BdzLLN0Rzpp-F*?QmuxS0
z0+C~z+5?hn8}b3UY+EY@xnh&k!z9lpr$<`8E!zu?S8Yp+;97z0ojYhOw5_EF>owa=
zdYu&6=F32eZTIQfSz?n=WU18lD-|@A*_d=Yl-q5?6#A>M9c%-sv~6#JGgY>&Vd$*3
zUHcv;YHT6p0M^=`Ps7maY-RpvthbeSL*%;cr+V}?*h)Uc71U@8YW_b**BzH-^~G(F
zrIy*xv}vx)mYG^snwBlgmhtYr_kL|!y^6?|JyfO)2cUus1wjRrAwvNbWhzUCY!unQ
z@9D4ex%Zy)J?Gx%dG9#q+~<XOo%5TOP+0F=y&aVe&Tjw0?Ay+d(dS9-IEOz93!9x2
z>1$>!&JHKa-Dq_lq{CgC^C7xn)$SZT6Jv4L`D1z%9nQ&w-Rb;&1z@_IukS=<w{s8e
zXzn@Bei>*z&K@S9^*VnQ3$Q-t_2l2~cdmX8U<1yAZ(z)z^Se19L(WSniD%fEMW5ih
z@7&;^tK$!x_fp7i#QCq+Ao$Svkz{mj)Y-BRWXyRFIX=go|Lld}g!9=ta85e=(z`n4
z{FevXrkxi|L2efV$-emgFhoznUKhsYbg=AUT%!YtD?>$d;9kZ{ozUyX_?XVg?u`45
z<bUyCq|uw?$yl-i5?+il`V5RW!|!FZ`7mx=LFGQi^J}5WmoY(EIDU++6czVp)K)@o
z0AnM4X(o_S`~oxuF~-Oj70mdRJYpdXw{cX4GQQ0RXBgx8s~E%mj6)I_bAa)a2j!m~
zWTZ{PsBlK=G$bMzO?0U@k|A6Qg;9*q7L=kHvp<G0F^tWpQF(}=jR#sR<AsBOiDN`j
zH1IH^lDr#77^8HOKg#f?Ge8n!<q@<cGt6{B@;Kusngdf9LR#5V8JFNQa5$Y}{O}rT
z(-@D^Ni&_nrYS9halQn`oM8-gV`Q=zpKM1dn=yM16rN>FQMN@6V>^Xwav5i719*<H
zp5lM!8HxYp=Q6&h`8AK>@)gX^XPl)x=mN$q%GSNexIl;QON>XAU~v>O7B-@>i19yi
z`xZ0WDe0nw(RLTuml<#8K)#gmKD|O^jQRAfm2yT9MZPN-3u(Q-!Z`f}+O9Hg^rH8b
zj4R}vtYR={qKDOtMlD#bF)q-@tFAK&58_eWVEjcMo*IVAinf~$hW`j^Z!x^-d{WC;
zcMXkoj4x<=RnO=?2f+qLCIy=t8G0i~6JvzltJ@5Zc(k=JevO6ot&DxNHnuVTUJB55
zM(#F{yNvZ=u)c%wCY_Et85wL;b}_yu7il-+n+_OykKyp4X{(3f<qFcvFps0#eT+0@
z<~sE=4qb+61B}XG=pAIF(G}ex#{a$m=P=_Yxn}P(RMhr>VI}YF2qWk>fIeiL7eaiL
zF%<&NF-Fx<w2d=L)qtL0bPob$l2P{~pr;sLI4D_bH#4dktS-!{8jwBAt*e0T#(bd_
z9d&1xZv?0Z^Lh*<Jel3Af$hb7lcM?F%;x)0@58J-1eATuT}rU{GFLtg;>Ro+M5RCT
zeG2>qFqcw7Vjy#|6;C;cIrt}R3T7T#PQSkp=42IELzz)~P#ea)y#r)Fvn2_Y2bgXw
zkb_KdI}}DTm;4CzQOrDVfJQTqQPNTj^Bp>)9b&#s9+z0=drzaIam;m02*fjM*kDOu
z{!H$h!_1In=-?6NTi0RCQD$ED6ZridV`jaB+C=88m5@(jW(9*JGry<r6dY%6cn6wJ
zFykmjaFU4(e*A!#dq0JRsmu`a?VMuHeFSZ3%)_*KPiH<$@vIDHD=o2^Of1P*j+kTj
z!E%QA`XN+iF;D6tp3Pi?N9b@m%gmxkSPt`#$Ducuxg`ud=a`pn!Qk`EOLQ=}z?>p?
za~_lFhsu2BeDX3BFbh<GxyXEF5FNe5yg~=RLgx0bp{a<Od=8~zrm`4dCCpomfWFMU
z_&wUnnPPJ3US+Po08B?E^AcrZRWUcvF1VVxK>@*QOrNiy;ySa=g324rA{wt6ru+p|
z-ei_`;Gx}Oe)1*S>Y1h*2sAJcP}Wf+b0I}mo0zJXQF)sgJ_+@AnEy)wXESs04`69w
zK2HI(R%YfyJeW2IGu0c|9n3abk2;yhXj|9CWd8t(9_CyxwDmGe17UC<bE5~)2ASK*
zJ3qwS{W8cf^Y72VIl}yeE?qxlo_q!<qs-TOVc`VxS`peNnU~3lG{wx)18g_zQ#Mds
zSbuuJm^~~<TNAzOEI~EK(w)__3nS#g+UAXtH)|DTw)?Q&@Pyz#*6?g7^k;oW7bF8%
zx8_4(AnUmiz=W`ZUj%0;Yx)0x9mZnQY<rLuu18xqOLz}p5v)`SPerpDvr!qtx=gRm
zAr{~99a!U8wY1SrU=2?L`!I`7{?lWux30sOMAjo>kR;XyO3XdMdSwb$oMh$u!R!>4
z!waP}mVF20(plw;fRe$w^Ew31uogdswk%fpYLIMJ2<7tRvcCE6D9&<D2H1Jl?I@ax
z^H~$=C>F5lSHQ%JtYF&m6|sEDy<W`XM8cR7mOn+n%2=yb0OmSt;qQ>U!I~s@W)15F
z7kV#P-_eix7Ar6emG!K*ouRjZ6-w@|M%G<Ku$`J%X%r~A&2oPq_TFK|+@k$wGwbI-
z6kAx^X%o@P`tS_o+gJsEL47;xaW|CivWh>1d?#zD6s0bfyBVC_tWP#U?>*LbJ3xC_
zCNFfmkM$MhT=lbFr+kh9*1|kM53<H?Ltuy%Lm7<2toTKc8(}p_$^ZF~_0$kRM_Dh^
zIeUVYoetJX)<qE%PO<ch(TiQ|wyO}_%~r33O)l*3DW<ZAo&E{hT-ha`(Hq28)5Rlq
z_An{*VBex1da|7}0OrL$vk7wE?AK?Y<iqCfhrRpQ)ypC7@MZ5&z+gW%I{?I=%~%5~
z0@&|-0G>ehQyZWuh<%0&!C>~a*{BR*FS-rWLfIQmKyMg3Ljtm&-L)6u2iR+#N83R*
ze=j&A*>UvFM6tiP2KCWw7Yc^NvULN{5Xasy7jp3qcExg7dW3zS(y@=S$3r21jJ?nZ
zv}E?(0kj=wA76>ConZgI4lt?gQ{TYuQ|yvxz@)LCKMj(}K3fO5(`?BWpqyd<MYGRY
zwo5wNa@hN0Adt)UF9*v7_8m%Z%42``6O74cJ6<Kf#3i;Lx%Ud$=jeA|#GXM(w8iZ9
ztFWSk-TDkFFSC~!U`#2y(FC+Iwm<#E%h|i4ps9l0L|LR)pdMgX*%J&{QN>=ML0dKZ
z^;wX+#*U$|)^&E<Qy@3k!Ax-0u=^b<2;OApyMncr-5m)l>ewGX3i*2Wqbyj_z)p#R
zd?WiPIrN&?Y&xplX7e{g{T=r0%`m2!J@*tk+QJTMhCnO(BkFG(J76D32fK$hyq#<=
z6B@eMf6=Au9(E4xo_pDCcj^4s$98&v+J5$rv@IN9fBpu@AUlN8m4?`L%fT|t?s^C-
z?z8*9LFEJXmIV+PVYiUi_#u1l?;xY>b5`_ejIGh4G|sN0IO_y^)ilT?`=`UOeu~Zb
z2V|P<N(nx@IQImU|GAqJ*MQEraOP3g?H<k(PovS5^E(|S_Hu4g=7}4}e-_%@IoqBE
zng?f3DOfx?^MoK?oPf{3>CNf%2Z|4;lV16K95)Kz`*Pl)Ma_?M!xwG-oUl@u7QiWg
z1|*O(+DQNZ9>n>z9z4OEb>|=v!ufs`NGRuxqkswHY@Y|c`#E`&U^&2feE|mHASWmZ
zdc!%}$=Mgd(Np$MB&UW>Fj1Vd91Ku2Cy0KxF`TvkeV&9<`7PRFIr%$)8OQmJPPXx!
zno}q_5;&jGJA0UuVE{S8aajfxM>#*!v~`Trwha$9k@E-#3X?egbf8J*WYwbbIA`m7
z=+g;KYc8-)a!yf3U<#+;N7$Rn*}57ir#LPB5J=;!q9a#2=O0g?oaQ{F#pMh~|2s&Q
zgTtrX{cO$v9gWX&x+nmb!|5PPb2+$yjlBTJV=g*+o@1pS-UZHw`QXgsa4AHe&zZ~w
zXaVPUoTZ&Ea(bM=a*4C<3{VO=4gC-=;>2b^eKAKxKA{rMs%f-c=9E%qP$|dpvnv|Q
zI18P@TFyy51yaHJmacGL;cOE??^R9?UBRy8eCPs+Do!>%%4*J$@6oku90i@ju5;AY
zsJy`mqVsMI=ch5W-Q>JP@5L?7P8z3LPTdNC)o}vI)nCuKOL5@_&OwJ4jJnOqHG$_2
zXKWpKnmGsQT+_liMA<N{99}q7v~i}+qOzT{d=#K}IqxqAX9wqxr_k2PVeA2C7pFM_
zmED}VZ=>=aCvzJ(dpOUIL9UlGMDD6S&J&dU-p}FCqBy|$&7Ic2LC#9@4-9d(gaKxl
z^Ec&<-{&L-!n6mRa#u)<aI|+|;X_VnH%g<N&NV2Fagr$eb)0iXk0G7l9AHCkk`wa@
zFsC@quYpW+#K~aU#eIyP-EOWh5H`7R@6$PX5BKk%X#I2LE~Omaz1-(N1hyM@xCOm%
z=ek$GCJ*jo<goSRzUPmU7k2}Fe#V>YD1y8XSC9>XecUr4(B#YgvjZr8+_BB5^yiAd
zM}GsjUsJ3)ko#5-Sc15}e1<Lsb7!Z3C4~EM75P6yx!X6QF^pSJ=iU9>Pfx(o16(Ic
zB09(o6rxYz+$c&dh~RGVf{I9Pun^c$+&9R#6U}}7FL1_im(jNx4soBLm`E%)dOJ#S
z+-RDv;<<l629m%H@`i@P+^c;6JHp*E2Plq2?gq-aO5%z?KrO!d>kHdXa!)>qZl`cv
z-h;uZ+<UZFJi~R02g_OR1M+|7a2XV6$>lzq2Xc=4A~~kdbK_qHxxj6G6PS72kfk8`
z+y}3N6mUPL1Jot%-7=6uZfPkjEOK!5Cm>(U{gpmyQNk6pVZ1JL>$ag(#+^fxZaLTH
zKo2Xp%3`R$!u|L*+OBei$6$UXH<1FfRowFw+o<NUUD45N+#WmHu5)*O1r;~AFYkpw
z4fkD&gWu%Nqi@pO;ttFMSS{C4vJZ`Q++Tiyih6EoA<S>!irP?W<o-jMa!uTRdM$5r
z{o(<7hdYuA3!Ayc^k7@KA)i3JmHUt$S{v7iwodKbm+3HhmwV$7<T|+9eZbktO`((1
zJ#NG>FnhTEN5I+3ecf>jw2yl}0k-vX=Vk(JfV+vdp@ZB8ay}1nk4-~jm>Wipwfo!;
zucGn+_c<n5Mz|ZEgiQ~*&8tuv<uWOQe~jzD8iO#-RXmHz39jcoR8DfY`9aYXH`W7W
zn%lxa+b-Vbtqv&M!@Exb4_Dqz72ch_yxFvhyYY_CL7O{oq8TbYc$u`Ad-D9B0H+tP
zmontMc`<K5lMgSLVk-N1e^Wrpmp7ME3jBEgP+--cmpTZ60AAZdhzIhvJ%n5k&%gx<
z=H-1(-#-iCU9o^Cl=mk6I>LCH6%gFdTk;Vk4)9*2SMMP2`~Pkg@n(@LEP`jGb4euc
z8oBIacx_=Y`w;JW`oL-|ui!4g5_sZ2Ko0Z9Ho^KMynj<Mc!|8wV_-?*JtKx(GVfF;
zeSh#I@4*e!rtp^0Clpe7=5X{WowwyE<TH4mCt<iVd9z2L@C@&(r=Tf|SN1gIvw3Ad
zf#ocZL&t<1-tQj+<s8p{G1|`aema5D1>Rl(I+4$lkc*{&r&|dtF7k57TXu=JhEil4
zg}hRFT*W+>Y7|R&%hWLVGVj+Y=q=;@$wR4}$6pS?3f^!N$Q9o99|3xmcbH;>RlMtT
zp{APmxD}k&cwf{3>^g55g^q9V&X5zhhUdBkm9@MtDXFE7cYvngdftb0;%ad4@<?wZ
z?@KzuH1SkXkhslz<P09r9bV@1=wUOjjJ7LXyq&al>*l$YfZXHF`0w5XZ=3=&y*w2i
z%=>viKMB(YcsE}`X^_WA!^jNtUJioz2(OCvS`T^Iv^0<Mc;sy!<2kO;H`2y=tJBdq
z!4n*VrIWnZr%{^X9iYU~X`YS}6?XA!=w;i@SN;zIF8saDD7o>^(;DT@zxpXEJ@_hm
zOFa2c-G{gr{~aHCN%_Ypi0Q-sy$^c#@t2U#+?Rho5rYuKKjT;g8q8nw5;_{fUo!=?
zQ2xUfNQCjfs0HYL{sdhFIKWra!Qvo){8x~0ej=S4WB4aeLd7BeiuXZc`Pn(p8^_P0
zbvK@$SqA6?{s;8KIm~~$0UD0*dlVo?`NhrX*>V2Mh4lM7!T*#(NhkTWv!O7BpZy8c
zr}E_{7;}pM@d2=;@%@V-n9e`d0?-V8_6#UI!+&Nbu(SBLp9RV0H&V*vS^o9+fs(^t
zNJ)6P{FlE&<vBjj4J_yRRdE2jz!%;ISRVh}+qD18=U2Uo#sdCd4^UgoXVQkbg#Ql%
z@|XFW5@A{?-<R^B%lO`S&Q9h0T$-6G`0r9?!WDkiOn_eHN0!2->-^tV0PF_epIk~c
z{Bd%x-Q@rK82WpQ-`xq!TK-+ij;!OqP)_S#J%4KvR5b9J6fA4z_t9Ccg)gSNl&$<G
zFQB#YXIutp=coJta+mK@3oAPK@gk5;{t1eockwrjz?eS%C{_0J-=kRO06!=Ong;pX
z$vrp3KluP=5A!cj!uEZBC*|xr9`OI7RI?F&HGL9mjPLgpO5^;E$*^gHFQgCMO!6OJ
z3$!WzjOAdN=GPPfZI|F{@>uQ`L{kvdMezBvVA&&BAON<jfJvWB*(>;v@^!ofFUO<g
zEl8#Cl#gKSeQ@p*EDk}NuS3w)3x$4y;>{Q#f5DV53=R-{*?_SK6dd>v3d01io`B$f
zK@-hh2L$OyfOb%Dg3=Si1y$tkiV%FSf=!Wvt#l%Y5_r*-*JuI%Q*<I;@Dsgy34*7U
zAcqAV^y(cE{Kx@0DsXh&hWs%>p#mgP5PcIcNrDiXc9I3=J3vbnyrYH{rv!gff^C}M
z?`~A43qmL@GDGn3C^TgX0?Bi6T7V(KYbi+f1a_9-$22I+5qy>e@mxXTJ(SJ~RJ5}`
zFDPk;zy-mWBLebyf=NoJ&KG<`m-Gq*A&WsS3Np__#U+7bB_s+3|B#!lNYJ_!q)c#x
zJ_S-P@TdVyg<xw52Iz`lGkv%Bs$gXqG*t>_Q24P*;3I&BYQc|Lz`QBAMeE-!!D@G~
z)Cxw-bo#9mtdfDXUa;<4pfw2Q4x_PAun*farzXMY6ccF`6odl1O;EoBmF<EnvGgJe
z1aE<K2o9bCXs19$dyp={ix(l@Ex16*xBUWZ3ZCSE;27R@r$K@H5Xg{V4#gIR1s|{}
z|K+}5!5&!gKu|-Qh!KIl957>oE#&?g7g*i}nGht9cVklU9r^X91ZkgR5T*r7gs{n7
zINuE_JcOqcA?_(mqlkf*@SqLETiA3H;y%KiYOw4R-l0XpSNK{TIQ@j3u@wLF7Y32n
zIY20)Jg`9F5IKW_gpxE2NwDziY6yl1S499OO!yY9wEKmeKLB$;_=7vlJ}6vhhIqIz
zm|pov;UuLVM+r|+=4G_-<(c3-Bs`V{lvrUc4Rf4u9eHo#g@4e=$B`hs{Uqp7;h!%6
z`<U=qdNC4(`)S!v5<2t%O%}dOpJ_cV99oXb6G9Db&`%04UI9rFy1s_tIwdTm9b=ks
z`>!DB!qnFxmmxIAfMg1vdmH4mFy|gRktI}1z>+N-(n0N6hp^@^VCM*LsDPa-?4u8Q
zofF1y!Z@E7dX~VZ3&NBeXv-5$($%+oVLJKV3WT51s&rAfG7jRGgiG&&6bgH2)+!P@
z)7M6dg;P9eDiJ2qLHDw-o1FBe!kBunlnL`vz)~)B{QVxxuMpO*2lf?VCwbYg3Yqkr
zs)ZgDt-2=sD;<K@g}=^6+YRAQlx$ohe4gS`H-)!mqZhTpG1?r~37PHaXuWX7C`f~_
z|3%0(3SXjwUz4y-3(Pyh({!9_7INMION;P<qY1?}VZSfX+J&VY)ZP_NkW;5aSa=86
zox&|iXzLP2`JorxLXS0I=@Hr=M_aFue;u9a6K<nft6zwH65e%T$Dd#s67Hj9jbY*M
z^Fi(lduS8zK-lmc^o<Cw)3bjleCK}-jKa9E=4A*@2><yVf|J4>6(Cc>Wxs$-3;Xs!
zewV0r6-v8B?v(WFA}ZSrfjy$6Ca8B64bh6XSJbc{ZEm8^>2nb7qVE<$z(X`A4Q6|a
zSmaLh5*3o8)mwCo7Fr+C*anLK?GtshL(o?=pZq?4qJtD{_7^EBB`-j9aSceI=n*+!
zf<zoU><t#3qi+?3i1=HfB2=_22B2Z0T`!?>zi5*bC<jD4dok(<MK7EM2^VdB9Gnp%
z26>1gMa)k?qC|VVXW;i2Em|%IPmJiLwHT8_qEv6Fh!w?B$SzLwE3HcLqBMG06GSCn
z!O+8^zDb}R5&ioaI1@#$JqPh5ksF=Zl0`NKu#b!G`M{<VqE+PFI4M%k0cVP6%{S;v
zs)*?hlvARG3xMKC6BUj^FkRI14OlZo-JNL66jf4?{IqC3<?@{oIZ=!~OQhCf*s?|T
zCZL@aWq$~{98qBlU~)y*e?i+hQMv(~=SB5&WV#^oq-U2WT1&^1e9;2Bzfd4zQEJ;o
z(M9q+TyltlgHbFLU8h8lBGF4*z*8*Ry8u>{h@PP&vCE=6G?kW$1eC>7CR#+FRVf$Q
zmO}kik@LGCm7-a1!}==G>Zia`E%JOC<eJF+D{x*HnQ}mGh?JC~T_al607W-Ni^<b@
zOXPTK25M_XwrBCw>O`qtXsj2VrZkHNQ7g^)jiN>5TWt~zzk<%(7CjjOyYGnp+z9z*
zk&V7l)*{+O&!<)NI=z8yqRL-U*)B@{@9vA}jnioB679)^T(@YFvS#mzT9$#OM-=zp
z|8Mq+&eM9-FS<oJW&@%Oa+wT@I_O|OB(gn34~Ip6wE_FS==l!-Ga{<&f&4?!H<Pew
zR5a8MmN8K#c_79`n>8?dLiE<FV3`u_q?pyT=<Bb5xl3F@QC=7E$WO3okGS|#2a2xZ
z?2jS1SNu^BSlz@dawK|)f6E2&6h~9WsF(N$@~U`?kI<s(BX0f>WS{tWGQ|DF8_z?N
zzxbz>AOYg%o<?P$IO`$gg2Z9;b_I)PlMgFYY$CT&nD`z=?DmT*cy#|LLTvpAnj*z(
zKSgbn_>(x;7A?O29!QM1^Bh29#f#|J8z*jQ0Cv3iauLuH#7>Rq{b6x1<t!c%J6Rxp
zRQx6_PKja%t;tE^AsYN-@s;}!KQ3PQ0G&7?{wxCGDdO*EQT}JDxP^9(r^NqIN7KZ=
zQL1*jxLAZC$q>Iu`39Nd(M=G{60fC0bhh~ApYROMikal0%@Kz!hg`0BDWz_l7k|AG
zeYqf>UI3CO{^d_p=8JbMfx-fD8~GtGiruo&Rw(AtFV#^b{(*kR#bQf3iY4Os)lhg@
zJV|kcQt>Zp$d`-L=vPr8c2S~qMchl1P^I`sn)Ry0V#>a&7C%q<E7!!!$d7Sde26kH
zYsBhwkelKI6iB`$o+eT&cF_5+PP~B!ef18pGo?8-isw}TyGdNEL*s366)mxM#Bb9~
z+$`Qn8D}lxf2W|SO}vK!7wzK5mjdmsIE4Ii-QwF6D7h!@?}uEEc&8Fp^on0{f<T{`
zO%9&{amZPK4T?GcLup8Skp(g=cI5p9nET>QRumtIgK6tFB0fXj$x-n)OVQCWam3p&
zZCtEe3^E~ZCLiadcn)37m=-@+4TZZT0k>e`Zppwuu);<1?29Pvk$mBg-n&X3eh&-x
zN?Ita>>&xGToF%6br4v*B%=<>KJb?Oy&A+vl1XRceUj5X;PI9G{27R!WYui+!e64J
zFn)mK$x4_OC~2X9W02%#EwF<n6_>ynB4Pf6QmABgF-!}Se9{Bc_DlY`1HA_%Ew7^T
zprpJK-3^yKcnSI<B#)Pn|1(lD*N8qvN%Sv3MYN=Y)}a{5QffOS5&eO-Sc!(#-8f19
zWsrD@g7QuiB=6D=?69PiGG2~IK7Af4j!FuI5I82OTLwcDB_(ge`Xosj<#8oTLh0v!
zT(Xch=qDr|23r44N}4Fhog&F^gJ7y;{4+?Ll1%*u&@>6>Be14R*gpa7v}8I6@@FK@
z-+?nr^86UA$dMePuMFi%{OA#$lgK+z%9DI{5o3`r@u4KG0!buosS715=*=yXM9>kW
zSP~jf-=8m)9DWR%$|T!2Kt;LaXWH;ymHfH}rAo<^81hvTX$nT>y5#30fVm;z(IQhL
znV?H!wUWPggQZTANQqSSl1*#D(j@UX3Gv&KrSAjmjzmTdwPuNs!aOaK!_%;$RU)80
zo}*3j=1lOkOSUXU*X~N(3jot05z==GIwiknfTvsHd;|vHlPFf9)Fb(nd~dyyCi2er
zNnB~k7?3=!g501)^eC{0B#y^{IV@>k56t@#b2p56AUP#P+lb_^ZvpmDGC|?{QHSLC
zaqx^uy39~GE=ev2=!7JR-t|dISO7q$Bwtp5by`xWN82uGyAA4hODEO>%|-h4O|a~h
z&JBb@H|cUZ3%g63+dw>|9}fcBQyQv9$x9k;1gE!@mj+HBsniZIU#a5{+NJqPt7+@y
zFLiLCDL}f;35|i$?esGalFs-aSc0XNQjid77X9G&OP9Bz?SOPC?Pv~4r*A+YQtCAU
zmMH0`pP?_&(ugA<G15Om&~`|gNpDG<bn!UU$4jTkRhb|?;`kelhoxm7qw$FJ16t^h
zO4mf9bWA$+9(tH4y-BC;B<XW>cu$t<S|N}jmC`JoDNXttZKtJ=(MJ1>boD*-H%t1&
zmq5vurcuiBS?T_{(3B&6j!qJ}(#gkBIwx%i1@w6-hfDj<3(`+1%`i_|y&5E6>M{+x
z3#4z-Y<p39pO&*rQg=_NFO+WJfTc+4_#fnorJvCTp+u@`gE5z-%l6|<D3x~gLPeSM
z=|KpTOVvN1vO-#a7#3cUu8RfdRq4tKR8~qm3uyhTk`_G&nCsGAbfmr^-4+c?Yosst
zqq0_do}43f(o|1K)JrAjQQ08<o#J?n(%Y1u)Fl1v5ol_bK1K<NEz&B=foPQ;?E-0&
zZW{(?yY$Hjh~Jg|L1WP&{p~Sec1j;Dq~Bkc^r_X*+b!MpIco1ocTm<+kCeL(gU~D8
zMd8anscR!(`lUj0nG8s$%RmODN&+2{M*ar9!_qmYz;a(YSp{PrNJlBzaYXtxg&!YE
zN1p@BsB|VppvR=I_kxT|<D`IgOh|($emE(8h5}1d(wi&L!)fUbN`u)Yn=gm_Zdv<P
z*zF>VqTkpa*+QCMU1h<ypm48DNIx|<nXwFd-DN@FqS8agr;U`SEOkBfddXZGp}||W
z+!vKTvec`n+$Z~jwl}^G*}7L?X@G307eE7LE4APWlJ$^hD_Hh29rHtEF%(A+mA#+>
zc9?8I9|ZTy7P){Nko|22IVjVS=P+ExjexxovY$mLMat^p(H13JM;p&**%nIch>@km
zz}`c$!R=s)l{tP3fciL@(<P{gmpv8%g$c4(DM8|hj7wgTqq18x=O2?jECoxVto?5Y
zCdpo-gze+9!AGF*glsGy0w-m%APAh2rBDJ&nk<c`vUJ%xdY~DysvRh0%9d!L@3f3f
z!L>88D-K$uvSja37(QF}M*#%S%B&(t<jDL5V9k}yBzM_4*|pi=JTHrV9||wXI%=Rk
zPgWX*%6ysU49FG8!s)kpQRaFOJ-j5VJqKe7Wv5+0ie#VBvR^FgCkIuD?6)*<UY0fL
z=>9{g?C}IxQzo000iJT1xezKUWXA%b_loReI%HjyDd?J6rR?$B5U7&9MEmV(*=h3J
zUy~KpqV2j&6o}GISs-~_ZpqgD=k%8Cm!fBNveNUYte06*K^kPU`oP&Jt9Y00KQzfs
zuSD%_*<9M7+>v?FHM3?}3+;<qWmS)(Yi%+fW!kjM+7r;$D|`F`NS|ykg|7N#Q{-G3
zKz~shl)2KSvmu%JFj$6V)#NR^FH5)pum`dk8$d>63YsQIWg)oo=5QL5eZ+*`aoOxF
z)K16}ogpzP`-HqmQ!+c<=$w|dm7sFBy#Eat<0Aiq+|7IB96C?A$=A@8A9uNou7Y{U
z>l;w=lsC>n$xF`s1;kr^xgMtZ$X{H7(mr_=y)3@+Kj=v8@RRQ*|9F7humkD?<u65p
zCrJLF61@nP2kgc;hseuLKvSrkc?K|H^1W|D#Q}Lx9OMtmOX&p;m$x=RE<*mU24+Xf
z1KD7SmZy`8G)CS<2e4TA9@>b-$z4J)l=1QgN@qUekY~{MLyyW+8qs)6{slQJPRZYk
zfu=Nhe;@?Y<=;L7D>CH6v{Giu|D6H7r{y2h#F{N1qWj=y<sXtqEJyy)Y{=!xjkQpJ
zPQIJsO6TQ;<QBXjcl{Cy^W;yffs!v@+zPn@xx?j0NL-W`)<N$jc{Jr$6v;Qwf<&?W
z>seqekv~U{?aT7Aw_ru7JU0fM74m5cCtQ)gLaX6b`I_S>Rmw-{U|%KAp>?-fo=eI8
z*W~jk3-!8u@n*=~kQb9*u13CmH|)JBU*K>-FK)@h6F_R^-|qmalSk54q+YJCgNY6D
ziV_Gm%Ga*~X_E8luyR|@B^S*d`9eB-G|Tgjpua8heY90<l}|K7yiI<YV#e+AtJARJ
zuDtI#KzGO&Ee1=c{10mDk}sU&fNkCKxioLwlY3o4sYm|IPBiw)zi2^apFAoBq+k9E
zIr#_VPvin-P`+RkphNPjozOHa&!fzQ`|`?euso2@DL~tZd=m>`59KfVqckdi&<~a|
z`Dy{c#^qB=Jc<dqZ7%sgC*}LyAvh(Eq;tZw{3OL&b}4q!g=`naZgS)7RpfnzHaA5l
z?JV3CljMc<P{eG5oTp;;zd-X+Yzza7w_;Bf1bh^=<uGlZVhO$ZzKXd)0P|DKr%&4W
zEBYx3HbB9jL;lY|g_;(bAVo1bAj1`dn*bW2`1Tq|q~gUd(H5o1Oo4o~;-k~Rj!_)_
z3WIP+kwT9$R`JR-IvS^lt3fGVG3#~6B`92Je{)z7Nk9K1ie)PyepC@g=|aa8uWg6D
zi3$ff#2rbBVDcv>D+*4c@wh_ffQcs*-V0DVsmM4B))d7`x<r|(_)-jsQ;Jm|p)ySo
z;{&;L#W6bbWGLRCNi$Qis~h5{6#>7)m@|rRSE7`q_>ml+*@|l7JgZ1D0Xj#)Hh|<h
z6w@??pHuuYj$WKsh}B@dpm1zNWuD?y7J8AdSWMxQ0>uEG4=yT7_+YuDm>mL}3KdcB
zfwNfg(>UJ85`~^#ugi)z-+<myMZz<%uuPG^9s=cxnV&<TLa}iHz^*86P|n6xg~PJ}
zDk>F)v?;DqJVOb7)rx{cK)a?0{1gV)C{ih6e^W8&2Mcd00?4&nt4MDFcAdhpA1w8X
z={vBZLGkB1kZV)~k^`hkagkn#+lmy5MBP!ij-awx@gcd#TNEEtnnSB%mV?d$ZHiv<
zzqBhF=*)9h;o}0B4#m}f!PBXbJO{hG6qjj((5-m>L$uvfJRnzEkD`)%vb~CSI&}0Y
z+$ieWued~8%>jj!@(KqP<xS8#q|nkYW>~R<_Tu*yJL%5M1I6i2X#Y8)DE=C(4;AA1
z=>4eT5%On@Da1d3j4MW*p=m<#?If(2R9K&dz?9;m1*K`lgKD(xQf{0B)AlG;Cn4af
z437oMUS*R7-S$ulDc{Fa`D7I2yp-!7h1@=6IRnI3IoF52f99v0{0cn&O7U#e1}I;h
z2V(-2*XSG<q+GBSrC{aXlrkNnydr~&P^GL9*kQ^|Z=tkbd1M1P4=6(^Tlb){f&vHO
z%B3{fM=0|tDLYc>L_7K@<siBKqLr_c%P>Y6@EGNv9a7d&L^oFX2|0}7lvY~!;+0L0
zfFvl_&V=A$<yap2bVPZLJSRt$WpwQ^N!h<1RwOGQ*TJ;o%54-GO;IkQJEN(}IkYQ0
zr5vTtSEMQ5y?|1>@+At`XDHvFi^@!;c|HtvoL2t)B5Kblvjb3@rEHV}EnAuVKCsU!
zS(gEtqkQvilya4A+d<ALR|mn0^UCM#81)OvK?+9ZDc@B?Z@zK{ePpFTd7akei^^|f
zVErZK%a_nrsLaejWsx#=7K|xYmMp>xQQ}aZp@_p}<p@pFrOMvjAZ5y8n&r!tQ8ZCi
zC{0J9w^Et@9MGzi*Mz97R(4#0`fJMIM<IS)`Qr;{yP;GXpyHOYicTW6c#^2BQ})uO
zl}=@a7p&+~I{yIm-AX$J&hIH5duTc9QP!tp5PFq+(*fG2Jn<VU`<1VyLU2Ht_A^ur
zDtpQ9A>{ytU51q&<jK3QT;vZG50rgz;2cr1uEY9=%IjqIs4|w$N@Ge5rRk0<Q|L<Z
zgff&Cf=T7QBaqvr8gTprnBA%cNzm(}8a@EQJ*wNGsB~53dV=g#tr&%bn<_>F7I#$+
zB{q4e#N=l4RIPs#B`?+LVwmQw+Cp9{AJw1j;M}K*rNEG{>VNbr_EY^pz9@fHKmC3J
zRL}Il&_LCNXUNAAq|yoj6Rf)X9auwD*_9}Ts&3FPCrq_;0uuXGN{U|`P)$?z-a(a-
zyjS6>G0LcjQ1$tu6sdYFAEhXjuMgy+RZTQa#;9K60P~P)n1RYz)f#%A;#A4sq7<)s
zl0o?|3945%VlWP?cG9YLM0KtUPv)p<HJxORsb1@V-b7X2qrgs5J@FXilT`<4pMG5R
z@#j!+LUoU3kCQ4UrRJol_RzU8RfWtc`~Xx@b3oEmi^&m~uJYLoLo-x=&<QhBHU2rR
zf2UO!D9m(5^(^@lvs7pEfSs*cbP(jM>TSB=k)w*E1uR!pxe4;;R7)sYbY7Je3xNx&
z{18;;siM{aG+*^31%C=uFExQ&R4pc_%q3M!7&=&}`fe65i&PtFA}>}6DcRRiqFPx8
z?8~YKO2H^qC7ecWnaY!fyIl1#dAqNwk|;({sWMY6r%LtlEudAa-g^uJ*HjjoiLa~t
zR$*jrsFqS<VU0?%5B<HVVpGQFEmhaQ&`_(2p}RVDs$C~hS+7!W09b=V<<7u3H>%dq
z?(mN4A$f?KRZrc6r7f!1c|dDbP15?=rfQi7yW3S;K18Wg6|oR3U8=*MLcCiw-xF5!
zs#J8g>{E4<r>9@_u`}9+RF4IrZCDjZw>R#q7SYuGKvmKXdq-4`zutkR4^^K$kK(9m
z-Y#H|skU^&wsF;*lYp5}U8J1UNmVX=DtAida|8m@s#eO*+NJKsHw>J1s|9qha8Z}j
z)@zS?eF`dF)xBTi!MLm6BnPC2T9gSnPxUjjh4E3Z9e@@4)b||}{q$9jY=yj^T1bfo
z{^}o+ArYWn)dYos>U$TUDM;;0r;T8>_<0x;qAub=K2-g3IaGwHRrKoYS9dKz+X1y-
zEiezN8yipxS9h&|O%ZCJAwWl}zoieE#Hb6I&~Qlot(|r|vFcPMuoKkx>CHc^);WP3
zQ7dMl?Wp>z-(cD?^@^D&C93yOqHB`+`<W0(R#*Q5O~=){T+pWz>K6Je^hxzF`4dvq
z-~R-bRCUcpXgZ}HBA0)f`s&9Z>FTGShlULGkr(Owm#O~o7);Dk|4@p?Y_;b%=<iwe
zO*+8kt7m+Pt`(>Q$xCoi9Zq?Am(*WBfyzSlI~3k3Qa4vau2@|ngTfN^oAhmp%j%Wy
z!I)C@Hi}@CsoQ(dR<7o|gH))uNkFcs_aOPl;dE8KavjuHs&}RVyGqSE1X8We9Raza
zcBA>GM*S(B>TaqR<)HGG+CVF1t-6CUeCpKClGD0geVbBo8`L@Enr&2@DNFc{T2Tek
ztRACXQj2<G7dTthJ7@>hrp~1&>1bCQDK+7)+D;?Xp+0>WrB1c$<6ym~zHWhFk9zDE
zbhK9;NFj<o^#u8_`_;_XATXf5Pl+Uh>R}a38&a<-gTi5T)dq~=h<ccA?mSeVUIQ|!
zcA=?kO#MD(Cy%Q~>4!eyP%E<`KdC;Q12Uyv{x|eat7Q~TbkU?x9`qi~TAK4+HNSLX
z5ZpEIY0&1OdEW_~o|?BQW79_y^bm&b(-f7U(pS^LM=3yak`7man%D25OF<fc3dM$M
zBA-B8nC3V70Ly-jBQhBB;hMKnQH;>sqZKn!lj{bB@tQ><NF-<)D5`!~6PAI}5l!(Q
zU^%L3N`bw{G%r&2PNL>(J#0$SES&{~$(lcNQF&aWq=W7WP4RlDKdA|Q6)Y*5YwN(0
zs`-u*Do$w@I=Y}fP2+YE>eDr=$zzkDd6V46nVQw)u{o{Tx*7`4XgqVEK1(x7PL6EN
zGRg}+t0|QOG)MCU1s8HP6N?~lPIJ%`_MX?|6S<&?p<8u%njfQKZ-M5Oc$6+`<~@MG
zB~9Z@^1l>n9(fu@6=@dJbXlx%q4;o##`!+vFKdhxM<~@)x}X<jnx1fQmTRuKLB2wh
zun4AI(dd_;@~URk1=y9Eh+iOHrE$|jpjtD23Mkh!%XUG1jpolPRNmAqAvf7A&7obC
ze^##%kt@7G^8&f)8a30DlXFLtL0ju)P1G>jS~NFHQEJspuSKa%bIlhp?V6M1kMGoM
zSPRmn`HYU~-I_G=AoObd$mQRsDP%*gU$az+wgHWVQkVucue<{BA<ehpbpP*x=Eg!u
zjA;IS1>~W|kNlY9nqO%fJE8HT5Y(imehQ}T(tbyM+O3UqMw^Sa{Spk_t8H>ZrJFW#
z1F+q-+nP}F(0)Xdrl)rHVX$~<ivmCbwB{kS1!|vw-^VFPTXGpJj$rL}%2o`~O6au?
z)#lQ^H%zNt2J`o8*KNkg9?<R_0P8{R7bFp`jhTnhi_p$VKq*o?>H%Y-w3*o2J4I_>
zeHCpn+E50JIi%g~2@<OfKL_YItsxF=@!F$wBu>z(DTC^;Lp%NvR2<RXsX^mWEt9;9
z$FzSeMPs6N**;j2q*ao0Bw5@37z{nGO`Zu&C$#6YQF&7P$#cL?(SAee->KSa$_YQE
zjn<+qP3s<lQo8mldOI_;=bwQwnc5jQP&%!B=^Vh$XdP|=K+DpuIt(kawZBI|{aI~G
z7AkYJ$0{J7s~yY%_Bn0jT(F$iuB6n*3)&^*7thmXZbxOlHi5cUpq)#B_lw#M29z#o
zqiD7))MmP)RHS{E_8`St8^uXWv{419ysQm&&=)C7wNHPJCsU^72gB}iZE6pADzrr*
zu;PkVOo>=mwSpj&s<jG=w_MXI$SZPP+m!>Do7$cGP<c!HA*E2%YWrGXc7t}_n?PyQ
ze*Z7znzUXrR5oj0m;<mDt-=7ct=g?+l>d2GYoSAMhxTbMtmxFbZUShRc6R`Hy0vp@
zUcRTTrQdds_R4Eu>D6AKV`QJUgQD^M+OO$N7|>2Gz@r${_E5sju-3I3>hEiH6tR1t
z-S#8&j%d$qg7`!2TXdox)y{dH&VOTC0mTZ&wU!srIH5iK17Ie#CoPbl()Rm9)3i33
zoL{?iU!<dLx9-(`RJ!Q0Xj#~!i#iYDsylfVR_xW)`J&BDr=u)Kcbyj<i#&9Fl;G;A
zJ0XBEUb=2JpuKf@`4oTf(f!SX`hB{5x`pAZ`$7cU{B+x*A?UAL_7hkGbZcW#8K@Jz
zk5Z5>bU8SKbuBNWGDJ6Bk5Z`aYjTQ)>As{u*nZvT$6(9>-I^!Ca!}{I6c&c-Zk~bq
z2wit9jEU4WUxlHLC|wd=GKkh~DFkbbu5}6Y9@5=)MPsZ^`W-;ybSW=_#Oron19pNg
zpFDYob<8s$M|3;Mw4=IzX`VW!%WHwAL|qe|u99@oG+!j^7AQcD>mDfv^a<U}jX*i6
zJ2e4gQXIM+9Z;XD`%n&vQ@SU909u+ZX$G*<bprD4XXr9RVN9lO1vw&4>lV`X>Wpr8
zJ~U<N%C-PITlZB9D$nZX(XlE=_wQ>c<?8qpSUsl`tbz6Cb*|+3xS)%e26Uco9zCXf
zo#Q9k#un&&DTZ`W_b5%CmvkRJ3YbFOQyQo*()o~QxmYJAcV>xh%L)iw)~%31MX7H3
z06J5q>xze5xlT;0S%vQJU|?U-$zDXys&qx<|E$)fzm3v0okt@|*L9jsh~LoFI%pxP
z(e+T$@J(IEU%<YlizZ)Vt!@_i{OWY4eW15q$B2Q24Z5Y2HPNX1eGUYgbearUcv}~|
z9ddVcpVRKHSvUPORJ7=>^B~@;D<>avn{LG-j77UHiY^-7)jcOcsY7@AF9#$#b$PUz
z?$TZQ8Y;SV>*>EK?&*%lK~s;e=rgeN>M}nEOP?;B{LKBj4HO3$&^7&x%0b-@T%>av
z(lyb7JFHtm)7^bt3!TUx=%n6Y8PR#oLEA%JF&!vIbvK(JKBkNMjqV?f>z>F1&xCF+
zUAddo&9Y!fr*u3@(V5oGBkW!J4IEVN*1zyIy5_2nbV1u*eUlKCZu*8+5O;n0a#VWg
z$4H^4eiILJUV5K*V6V6SFkJxh(RUm~<v#sPdKA9;{U6Z!=cj+74YmGyMGi=S{==7`
zB2a&e;wC}*FUZLltlzW);~b)2N_n=S`UzUq!t_(*<lnFVb_M!$K);f_d<XUaPM{R7
z&q@P{(9b4^Po%!=JIF=pe>FoOTL02vXo%6jxDomshxGF)gDY0Qh2-P(HS1toygr^H
zvI+X9UPjwt{V*NJj_6xz0CQCTB>8=g=}%XIGg05P3C1MpyXeyk$@=&9L+-fVj{|`d
z`Y1Z{oYa3u{;d@KC#hgb(+|=<E?vK#u6JfQ^mA{cn5j=AyHD#!U0~uFz3C`mvhW>S
zNM!4Evr#&$|D8UXkfXn}1p>KxmkD(3oW7FIN_qMi`i<r5=L~}s=x32Lr%=DM87hkO
zZ>NE!SU<Z9;-&f(l+IPAZy^t0x!&;(9jmVDe<3GUrT!h7!mIT0^iA(teVhuFb^1w~
z-s|-rrvj}(?{^&njrxg|u(wIS@-zAY=({N~{*HdxW|W%spU|$bMej~$@K${?O?Pej
zcPLl6UEikyxvLMz0ZWIz%t6;CJN18cfOP3kTtH*D{wie;-P6ZWnsAT)3o-iCtB;|m
zZJ$1|59<5%Jro!k(BG!c4C=L%Cp)C)z6O+GeZ^&P-q$a_gUSc`L?uv0^eo!pj_W_A
z7jZ&AaRDro`gcT>e>SC0qMU?jefB9x>@p1Q1n6$V@CCHF7=*#F$;}W<%aOZb{u>bV
zFg*U>OKxCQg44@zf+iYo!&b_-^D#_qgxo&Ey)CHpGx&c1;&1q_AC&=yQy1`f0}U6B
z0wu`s3ybn!f(;k5&=_J^br70D4X<4SPne<qHDK>I?E4Jlpka^)>~KT#QCJvZm~{%E
zk%n29U{jRg#d-`-jNxOtg>lFbL2>L@gZq4-#2eNeMb8op3JO~uHjD^?a@6q94JgM9
zclOfvUlI*=@*XD{>~t+X*^tzU(n&+X>nNodmUaRy)$j{Vlcx;c6sAoxEK`6b-H<>(
zl?+3}ae!tT%G$tr+Th!dQnumQM)dHkVfqd@a}43nf-~3f;(zWN!>S}yo;N7z(CxTj
zNP8E($TM*0+?sFriu~#Y2CuKtc+v1m3%Yj6@B(?S3Jqbj-WM5q*P*T0@GE72lo%F&
zg|1yTBv2<x4Y%F{ScM^G5>{L>L?(e;HAGNeQ>Eca9mJ~)YsooMZP-svzH1Ic(rMIQ
zH>}k{{)R!m3YOLwzM@UyO@sLxu--BpJcG76L)KE5R&RJF7o@?^vje2jFoy!9O@^Li
zu-rBj(2x0!VGrFGZZ-tog7qziSXWrsYIsfnMQw&H_fXkx&{M|rU4vuRVF-2@`j&xo
z8k&DaZI|IF`60UvCdxdyXV6EXt;bOO6iU5@=zXxM&+tPe$e>~QHIO00qf!VA8-5Ic
z`VoVc4($&OzSq!+QN!9LAY%pvWg?Cn#PnKC7_N&TH*Iit>;(2M<I(kK+->~mF%0P*
zqvUH;x*Ed|Vf6MI3&|Ka;{$rH+>N__LCM3ol%m9*#>ZO#<7M2t0|MU0Ewonn7zb!`
zxX<{@6TtL0R+4ivz?e*#<$*@qPar`?m;10H*tjZ={GTDl5hGwijcyda3^V%EJGb9B
zldeh}FdAqwIcThY2NL1N&t1S0Va&dcv4}Kke4sGOIK_l`wDIf%bUVh_^dtlh8C}|-
zH`e$l6J3fk?*9Pfh*41r@uNmYGvtmLuk_LSmuRf<fWjoBqX6>B#zFE~95;#zP<g`G
zPr>Gs#?(-d6yuC!u%sGKT>$neW858}r5U*%P?&C<g{$&T8OAj7&14!o=mO7a<E%H)
zi8IDTx<#L5ETE`dw(&8_8aiuSg58zFDaZKYK8#ncaR%)y&KWa8A$Z;xHy7lBQFsap
z^Nc@o(ffSk=#%JZfpPg<R9-YTsUUaB_{~MAC^SyXVQ-Ofb39Orjeoxjg(XHa-G8`j
z%)Aa#YMkVNv&=Z$2+ne2)LCe7R2ZN10@@YhS7$-48b!3UR~juer&JjW2f$iwT$TrN
z%~*dCFxQPIpNBCwj9rE3XpQlmb12<3iYZI+mhq(zQK~gwB17wp^%NzpH(D^!I5ilv
z$vxL-44`XBO~yP5{oZyMt>opqV=U=~-Oa{X4^i7<Y-&bjyU~kMFzy<En2)v&WBO)P
zb{gGzVCgd27on}&cqJd8_l$onM}K>auWUwJuW|AkI@)L4OU}uD<5n}eG+^9A_t^%G
z>Tw7R8Jp=>F>G`sEr7uz#?1@B`p|g14UMD5%jA+8Gk!<v$Blh@v`rXS(cC?0ETYVn
zDWl{Ka84U_b70dhQz$*=-6knHS6ob)C&9AE#CJ!@)g;b>oV#g|t`T{d>LVfGX*xjN
z^)h|ypyQ3V=_3Jnd`uk-XxeA$qeaTsRP-rIex`W({-D2UHXk+xn4&3BJkS)@2lInW
zt6u<2uqovRSVBy1%fS+A+V2DvVWtV%J?}Tos6^WVQ{Z9<95k&WXF<5>)HBc*VH$sd
z?nFkKQfSW=WfDCLv_qz;WHiQ_n5!WeXIe{W@uq)@!IEJ5p%cS(*z{ZgEIeY$rQP>Y
z(|Q&_kC_&|0G32kNh-vXOveSNOg0VBBy!y3PSJ=Hrbj+PcT-GE3ZSK$O2Z$;@9&f;
zo_2R>rUPnVr<(#OH8#UEV>ehcO|{oRPMhZ00D8vs$P`p$nLaOoP1&Y<KcSRsGWWvJ
zbEb?6RGv4b(WvK}{)cFyQ-P`LLqK0Ny-T}}OQzm7Xec!8eFLQ;lQ;H74yR&MNf>xa
zOyxq1&}Gxlh0s)LN}@<snW>U|9p$Ffmw;AbIzTV^71L4j8C*3zeFOrPCcP)@tupQS
z8S1M|t($>;&9w3vv|Tsx>4<p46nh9@H6{<*=-xC9EJWKa(^E?@K#p3IfbRd*nKC~|
zXX;Iz&jY)`ltMeWM$_wG!QduSKaJOI(@sj{x?}1g*HE+RTWp`5T1>UHw6~f*+yl~P
zTKo^x-!*;5gj|PdE4dyzO}{UPT$gF883Ns=TWYY}Gj&q<zsF$;EJ1CrX(k`$_nFFn
zLv6n)Z9W7COwBLC;6c*_xdn$zzLZfhY&t>YzUgm0taxA=r)1O-(<1ta;zQH1QItka
z3OaX=nO0GH)VOJ20GJadn+BDWCJueAV9NCSRX|Uh96xbj=`QnxA8L1-{oKLoVxF}h
zf_uzQQ96pNSxdYAy=J#T42hfBsTytW=0|@9@i3oC1E{B29EFmXIb|MLyv-|VH|b+G
z(x!Bu`Cam3_?i!AgT>DrN$-=tdH6k$0P_zH+R_J_myo|V$Q(iexM1_I2>=Z-JCRo<
z)V%p0REC)uDUjH2-f<1s2h5US^!}ikM_%J_b5j%yjWFjlLoU+1fRf9i%)XyPF50|j
zFF0e&r)au5WM1lm#}sSM@CS69`8JF8pYi74UqKSgd+FZAVe_-CU_D|sN5izE=5^l!
z^q6_R6)=hBv-Av;%)eHnGTA&zE9G(XKc52hgn2!EpYEi2%?MCZ%zwC{E!Di}AfCu6
z^BRh}rkO3HfKE5J(<bY*`Tbw${~ykn+aCfu%ls+%9J0;*Cn0gxEWHbf9CJK5Cv(kP
zY4FdP|M&ov=goKNTyw$vR2T&E%rE~7WAe?VAD~oVj%otSMRWH7sJ~?XG69^0=8Oo4
z7nvU=FHW&JY%fYB=G6!lIGiq<BPkWC)O_eY7*%FY3Ii!O|9Sy>E6mS21MQ0WNrdX1
zu9|;*32l|;-0dJ$=E;jtSZ&_yhPG?wd|F4Yn<WNR-Y}0-c2|v=c^L|Cnk$mgcFXKU
z^Led#ZWP9_&Rj8qN=LnUQy_{B=6>>=G@89?L7L3xr7-cf`5y`=+%cPeK@XeF^XV!}
zi`nrrKwHh}zoXP<e)Jev+Rd3OfOglM<$<;iv+=*B%Ip>mmM-&qDPZX~ulyS*_skp8
zQR*=t3xuLxhxxay82mo-Z)GsJ-|RO74{yMHq8jQ4&7aRjX~;ZA+t^|A>U%)DZ;qo_
z>I3tMHo%OSA9B#Ahvq*PfMwKtky4n(%)ht6m~r#-cOfugK0<EWN%PZ`*gj?U^#JFz
z`DyZm@3J^vO@JA@E&u)qG#AU+ooL)+i6y_St0jiEvF;XQI#@g`i&lboT9_Kx>t%U`
z5`w)gpE$!pAIl>PQ0Zs+)*s^jmOC_C23YbacPZHN**4e|V!8h&Fhea%s!$nbc~=jz
z-{S1p3eW?V+q8*4Xi>g^&V*a`z6E0<ER6Xek(QmqV2!f;yb~<ZmP$&3jkQEmz(3Bi
z%@r*1mPAVROt36JgwkOPBNN6Pu{`oKSQ0JE7egS)^6v_uBwNDQqwS<6oJJ<a(%ed4
z_DHo1Sb?2xNv4m!W>|D9fR<^AN(9eo%L3YOpRx25qB6_E9{@|XC5Hk4XDtnsmX%|f
zLqUmL%kOmi>YQbWi$OSV*|rt}`IaC`_bafJ7NVaQEwxJ_P-MCMGf1&TP(%4=B^F^Q
z8cQwBbh0k9#JNImx#f@Bkgu@3P2YFDVwq3wpR1NonszEJZIrcMWjT5grE1FuCXCuO
zO9da5*DX>rtf;Yky%o>yrlsZ`u-vkICjwZlCG{zk>MUZ)BdNDMjR1?osloF5Y7`qS
z!QVil$+B!UdU)G1hkRfymit?vzSYuDjvlsImdC=vcFS&h1Mgaxl$p?Bxg`Nhm*oKM
zEV?b4lMugWd5`ukJ(kC4pV4dS)}XS_^1VMy>$fz~4blP2Ve*tZ1}(Q}H6F5bTt_d4
zE&Z`5-M7rMgXe)|DS3)UEEg7{^w9DwC9sTH-ebYEam#|cuy?{zOUXQwmRbI&oU%;K
zgK5*2H9taNm-Wyx*tFYP_XjFntlFIr-(&qK1jN;9qEx=U4r|3z;Bm8BXf<}X{*R)V
z9@bTf=##fKwFK&Ytd(>DXrHyX6)^tRd0S8luu2X>Z=f}qPUJz>6_jZcZ0)7!Wr)?)
zjM9E<^$f5auzpT6;z4UKc`m}OUkt&t2<tP)&=zTRe7*!j6J?!28?k8X3JQwESX&dJ
z_mH)da$I7qPXC2ZtkRERTD+D02&_o3*3h}}uyxZ+pdGQ!3P;;f>xme&9kceXK@XFy
zPrL!J<JK5Dvz)Lh?I0(uQFPfe#VR3>W2$wdqYE_MDkHa3hV@Hwi)2~@LSa*uwTPC%
zY%8x5#+<cI%!k4p>m734=UQj*VDCBW4O()}TRq-}_yy~E3cKW4|2YXO@~u0=&{kkg
z4npao)%G03FIknlAYN$wnWp?A>*Rlb2Uu(!oCg&pR<He#zij1F^t9BPK|Y5v>%AX=
zU2bhs1Fgb3{VmY0Sj%4r+Er_J8#pViu5=!%vbs<RsoJ`Rj<h$dU#$aYjdgu5`f}6i
zM1Hwj)|vFtty=3MZ*bOGoBZhiSL&@B)6ne(tAYGYjn=1WGH9}XLBoC9T2qF~J62yC
zDx0kXHzC+!&FX+nt=21EKx?yJr^%$<dVB*o?^<K3QR=W>D?zE#dZPlJ=(4JwLASfD
zZawJsJ*#de#CxoX$jfjz^;$P)fVI!6rtFk{YYxqfgVtxB1nZF1o03z8ts`3jbKm+7
zC8$5J*3&_C#5&!FK0UMse*l3|YXSYn#;vJVkO`}q_JNbuRZb9?vgXjm^=WGzMb38F
zq@SR2x9yiDkaO&@mC$73YMabO<6fI^FRXC0{pt_mZd>~r(7bGtV3fRV-ga>M*j{Eq
zexJ>l08n4sS0W68pN;td3jJ;Ky3rP3`+(9Z18phfB@eQdkwZJ!_9gi^LTq=Fff;HG
zqimxvhb@A#_4nHzq1?j*HZfhDJ81i?3f&I3%^;^vgsq|!mPXp1T#qLbWve&?5^Z~x
zuF%BTN?l;nA=@?~Kx1vkmq9$vRzV(@c$+u*(-Ul)=(fvYn|mfuj@S;TgB-O9C&6;e
z=CHg26^XXv*)Z|A?U6TtcET1yX^|&wZ$FAsip?B>QmXA8+P0sv{YDvQ8MekwSdnR4
z`y5zK+xBFl?Tk%qhx#nr%(E~i+cx9{^=EA++PUS}qCZ7tu1#|TVCQVJNW*#C4u=G_
z7i{B+Ffre@pZpmGwtKUn;-W3$G%USj^QEkbLR-*oa2DC-)18iDTkX40Ut&vt9Hi8?
zn4(Q(Ht%e3mfN)Cr>e01C5HGF+f3RqUbWqO1T2-d)^n(=vc0+(EY-GsjSfg$vjsCy
zylz_^fL`3N?e0P^YHUi1BiyvDE5tzEvi(awp<0`j62R(gg@2$_Z}T`0&<5K!I@&hc
zcJzQW*<!}f-`lpQ$X$HLwqhgHH`~(b+DD76j#5P1ZH?(*xohKl(fy+i+dr#-)@A!=
z9pt-hHz`N-o^7oj>U(S_>D16`dzS(&eYT4~LSet{Y$dP<Y{!lRbkJ7uDOiSVPti@m
zVcQoBh~Kx3(#rn8=1m_|erRhShQO%JPOI>k?dQk9Id1F3_6GldWIMb8JX5yeYe1W}
zJx|YRm;Eo=1@E@2*)Yw;ewOA}SG&t?$nUkUivf$9-ApT<yL~I|eLU<8I`4Yg_xpm=
z%l^YZD0$o8qjVu3dwK{;`|O!CK)!YhO-X+Cayq{`{O#{=Mq_~eXZpnk+Wj_yC&)fU
zKI~w7EBSpw>^Es~3$=UF9^|0?w_1>J`%yoT2>UlQzed`>bO%e6efKvIkG8Kr5AhiL
zgU^6@$bLBtZL#(^85G9ZUo1eE66{~odvVxdZ}|hPN9@)-SaH<;-IriJX1|e!;ZC&2
z9Yb4^{g-m|FxkFwIna*V>z{!93Hxvy)Th`@GRURcXFm&;Q}#nIVVu+Kr``u=x;^1z
zfMwV-qQH`Af1pF#Y5V&rD4nr)(D6RY?(lvKg4y<eDa$I?e*Y8joU_-_J9pkba1rV+
z*t6+EOrCv+e(?GB)pUL=u>WO;{6%~8Z|MCc`?jwkP-s8!6Z96@?^-Yj#rEL!D3#dd
zbZhIf{pp_}P-;)4oVYUkue5b4w_kSDqgY`-@eqwy>_5;B;i~-*9jPnr&r{xNm3{SD
zR94%gmEgQ)_t^&Q>-HyigWRyU(P^Q^9zc2DH|<<XCcS0f)DN&)yT{uww9dYJ6~yc9
z^C>~S!R|+I?rnQN-8#Nw*E%TIq}iT82lN*E(pHRmtNqboG`89K<kf7qAN>d8eAnKw
z8Jrz<rxeI{+K*70MVI}K2Q2Ki|3t6HJ-hKEkRChdzde^dv>tl<>?bMtsNep<Jdgo<
z`xL+i?HegtG-UtXi@tw7Y)^@R;C=hqMu0xB&zKFK5&PTJnTPgNIx&vg$0_(aX5T<Q
z_i=kI9jPbmpB8~-(q2kYg(-V9CCyLUznBKuwd3#SfU<i>(n1Kh>^S{4Q1<MY>x@d*
z9ZTK?%ibN^;6`ycx$Rg(o>tEtYdK)`+A*{kR(S7d;-J!J$LEyav~Nc&y|cbMYDUoe
z|FiTZ;4xm`|9#(?NivgVl6l{EmP`^YrLDHKMOBrm(pIS|MOBNomM?8lW)Re5L-q&}
zvdJ!yi0pf0lLZNhL}ZglWRpY$K|(D5&*}g7JRZln_ngl;_s+ZAd(OEpAKm=N7|apf
zlQeL?x=wmw9@QCqz#Y@&Jc9{8-CI}DcwEO(=FDIB7QKE?=-wZT={l*)`UZ^wx;1-1
z41v1Dv9J`Rv;PgV9;|DlN~#cD2QBhW>Gn{JGgQ}2*|9L)9@@T!>-;Dd6`}iw@|}@7
zof{;hbZcnE7_HkN26tL_h`fl=z4-+kjnz%1XZ9K0V_JM9==!&SJEt4`7buAa-M6$c
zNzw&St!1+A$%hzditeu}prz`r)50cA=XVeDoUWU516-!=@lKe?(v94NUbgP%#n8*q
zeM@&-uI>%m6z1thra=9?ZtzVQ%-0<!g9W;9S^^d7S|~PCq<cCG>cu+40KEY&=vIFT
z6D7LddFU+HeOrabi@KEW;LIi6hHqfEQWsCR$`#!kv{JpQOQWm%nod^?OEtPH6QNM6
zYdZiFH*_ir_SNe?8;`~Yo$pB~H0nmKfi&rMRspkFH?JQew{-6sC=J=BJGc^P?Yfy6
zAh&f=imi6&RKJ7k)Opk5ze~4m0u;M-TRLH|NB6)U<c==V96t5x4krV<PnSbE$$njI
z4rcbQ?p8lU26UINg51+h-vvX1I#*gl+}Dkp3JVW(8$PGeKh$w0V25;}Z^6<d-S}^T
z_E<N17>ZAHV<`MHtm~ys^oVW}8GNcc{1W7uPD8blqq?l|;GXN&wgBaY?(_vTzSMm^
zA1JSMAI$^jpl_!ffusH$g$$ka5?b#%>-Snw{fmn}JRJIm^$Y!A&{bdZ0~Fo#VRVMm
zUH=VbK|J)&-UYU&{*PyvU@yIb=E7UAxr0U@z1I-Xj_4&xQ1{jE`WAXe^?5JB9n(*z
zm!h9On}R{d_3zTE!(adF3aFpZ$6?!Qket+e(yBi|-$fhFKz+z5a6$SS`l?c}zK{ay
zA^Nwo(059|bT&w+zJaQQ!}K975DC}6Nm+pi{o@>%h}7FJ1c}lI55Q8i{v&5Nb6WpF
z6$TNbueXMJoW6Y}`r`HJmOwF_)&IjlBSAlXFW7VX9|tiPiTb;gl}py|`5Wd_^c{A9
zN!8D(#9-3&KSV+#UGGBK&n*2h2}riycs`uT(ML5wAy*$R2bZT`vJ#l*^#>@UldoS*
zVf6xi@k2lt>IHi=mKgNDfnZDZdF5cs^q%EFE7$*srMcvy-nR-Gm-KTE0qwFrKN=zx
z`fs#wrc$p<z$mWhyH`P>N?-mpNVR_DBQ##q-=uR(HTq@oXsp$re*^y3>FXFY-q6?4
z!LEA!=njB2=ndoPQfSnh9R%B?|NJf{zgeHU0irGXBi};5RsRKT9B=7kl;GO*a=NS9
z^?p;~;cfj{O67Lw7gockF8$FU%yYN?01``*9(@p1dEC*jqD!Y&Uup!sKK&aMq3zdq
z(h~KlUS*)x7y6($$h^|e_#MP)*9&W4AKVpn5BjdVcC3Pi$F7K_Al|$Be}qWbE~iFJ
zN&K$Jt1zFmOLLZfm|fQkAd<DK<uf$q?wYqA1I^#{Rt|<#w5yQDS-NYz4viJNLJtC^
zc~{kH13G(mxs<@0p<S+2Z85s*RvCP9-W@}G(!;yw#-Yz=_mwgj4A^Z~3KG6M_BH6A
z*}WwkT=H&PI#i##d*VyjE!o|}gIwGl_#s59cbiaAS>5ixH$lW_kB*k>L3{2T#{@<0
z`FRG_e<ttg{1dGidm`E~?EF0mtKiecJ+m&uZuOoT+EFy^*<ufo&OIlo5aiCDrE0kL
zV9%bvU}9vC{v+r;-%}xjGfwu0s3hIp-sdnHz3emTNqW>im`aw9+uwYR%-hGfKt0Od
z<Ws6Yi?vr9!_ry%PkSJmXg`q@Q|vD}Ks4Rnl%6*k_N%&~k!gRHQv6x=3*uqoy#4zr
z;PUN5y5Lix{Z*=HDzbMth`wU`#kW8%*k}BKftJ{pQJGPx{U2J8GW$90G(q;hv_~^s
zvY&q!iWT-#Xq{1M-}5C}uh>u72A{6l&!7!lmHk9V4D_1)o$nx0WB>YC^wrw`OL3Iz
z_TqK$@P>T@t#9h>KcNJ6gS`zMc5Ac`r<m+*`z!P|>#`q*fB=do;TPjWYy4VfTPVf9
z>lmvrcvR0M{RI3*=A#2ZY-V0k_@afW6Ci@qSRA-^=2rzg>0)}7XuQW5r(r<DOgz04
z9N0U9AZ~2YE}$G`J5Xu-pEYICR5&y46n&B7&8gdAX?#p7oSl$@Ri;7m)_B_5&lvB4
z?oTC?&^`0xsX+hi>}LEu>nA$gIeQPKH9!A%5oT&m_guhzkv0N|xtIFT@?|v@hR<7*
z3z_-v(z@j<OUj>oy`c`e-+XZsG7H+}=>1mF4Bdr`F5usbs*hlD4Bv(Ip=t4ITIznk
z?Nf9t$$lN9`r!p_1eV%V<L_nPXF=viM+z=2|9c!jR|xdjSvl4Qy+4`J^I_Gdmq7UW
zHL9CfolAkxU!KxM^XmmMB-iYw627&ShtaYwKO0tlpB{|%KMdodF<a|b(m9z8DPHK_
z_#qV*ZTfZ${{6qND7Ur$bE@z-$SkC?)I-d4N~|Ad-XU~XW;)fgx-n<6VAq|Q9|33&
zhItzhp3L(h%!L=@84D3#=HyA}wJ|=~@MMtb{tk`z8H4y|&}U4!KSnjmbeoeUHtl_o
zLu|rbvcxVd#ALd%k$=L38=Fg4raSxg6To<|ODSIG$$m(Ms9vn03I>DORNBOZuv6ke
zVpxHmL$R#I`!IBdW$7gl$7;U=SUl@%phFL5*>1Yd6WEh6z&^)*Mv;O<_K^o<l33Gr
zU?;PIw8Tka1KtFe%06j>-86Q`+u$<TEfjLfWT#X4Zx-vV23Wdi8%4@8L~E&@CR6m&
z4q#@9vWMVIwy3WUjX9!-J^zDfuBeSRQF)@TDXVi{6hY;w`J%hYFi{}#*8!$bl(`nJ
z6^ZOwC>D!$Sp(*RX#5f=l!$b*K}tpb?ifp%Xy!zSl#3LxfW9c|*beTJ=qLY3hBsVO
z1LTTmULy=#6>Xmb<SNm7x$vx7v~(%tuZg_A2Xc*Q+v^xut;mQTiPuGG0YI)3O}z{|
zH$?5Uld2cZrbBBDqA?`dDC#YSw@o5<I!e|ovUP^!O_4e6zFS0pE`Wtr(Gde}>u!nU
z$3WUdpHmH0yXZA<=-(FomIf0YB5M<nPSK_Yz;ubmQ<l72<X#J|N7O2X!8@WF+QIdT
z(x(8lPbBw*dcR1ZH`iU!#NW_2AQI+7@1E#u`i|0|Xq67+zKGdRA%O>?e<olO9*VY7
zsoRif_upuIB#Ly0r;kN9??ds4=ov*&hDG}+H!>nR9t7;CqVrE+@R=z5JQ_zu!vato
z#P6=dR62_H(jqfSJaHI$$>P`bz)TT0hl5KM4^4qWnz;BjZMM?IfsKI45FZ{yYo_?8
zc-YMn&!gM3N*qY{WVLu_9TcyLPnJWnMtq<W<fiy4Rb8}*_gsNwmw5j%kZ$pO9tyqU
zzp1dJPuw>SdWR*as1nOn(ny8DZjxVRaMTlDU#FLimjw4CUgKD6V@y7hophcdRPyyQ
zXk<&i{1PNba``4muB49c*E~sbDfG`vme49MUvh9cOcY40>Dnxmq!ht!k!0{XxC@fI
z^cjm1$virSQ7TzRNvkr+Ti-#wTymuWeTIvYp#j*vB>929^K)6Ufa3G5MnVX%Zy8Oa
zHB_5XJ#p<u7E~E{+vqQP*>o8FP1D_Jq;7*kmr=!J`n8O9KZb`-jMg*gdu6nrHdGGA
zE3=^PXzXwuUN{-wqD+>D@!S>+$<ttb*Bh-~#-Ed?-o{hu|AsnZeCz|vrLXZVsu??K
z{B|)oKjXjJ0CU`U4ZVN;jo+dIniIxZ(cprNKl>Xb*m&YCG=><vIf6tQ-={j5G-I{|
zB;9xh9dgewHXFpuWE#h3(EJ)3-k>i?<QhkPj?O&e)zjhIdE?wU@H^jl8=Ye+FwU|8
zS8lwY)?OElhw0SWCF2JNp>Wx_{!=to80Xvp$`#{HdZ=GDenus^^~U)e+-@-Lr)6xT
z@$3rt)MTv5hWVSu_r8F7i*bs9*1@gDB~)y3%lOZuz-~AGkz&%fjZdCKW2dpj48U|5
ze?d=_9%JWtDBLlgbrB+c#<8@*ziX^r0LcO4Nwm<oXY5R;xSUKX*TVagCPj3@B*0`-
zH5vm=p7_FikjW<$3J*33*U@Gx#3UvdFsDp9DMcD;vW$v{!%X6KLnhK>$qisfnS4c6
z7ttmQDE5BZ#GN7vu_l+c!<jQCsS|(_XVTIQF5bj>AtcY5j4S|3y2%XM_hy)^q7wvJ
zCPvwCCfj620Wfn+zHy`bFW2NN3MQX7aiSM)zRAWj=qxZfvjw1qCZ{!+s3H>=do*4!
z38U0oiODHi5tW+!`47;_OcqkQ_M*uHN=RQaX?_5d%O*2EMPH>!H<giIF}Xt##H%Kg
z*MsXdk<uZQK9ePg*&8HxO^kyum;sYi3K-urxmN))XflglZ4XS=mO=5MiT`CNJ~D}(
z2gS!Gzfi>JrAY+^Kwp{g<xqE!Y9)|#lqR2tGfvV;6svTW{w)WJi}c66aP6RUDm`=$
zNdq3C@38d6V(1xMr7!F-!XwhzR6Xx2{fzF$V^UQM6#b;#D?t3E^Jz_XLK;FF*F@>>
zv`tEqTF@IVMLJ)NzEtT&s#8jn&OZn)UAnCWBtyE3UfP+`a;l-olBP9cX0oM5#gNRA
zt{a4Uu0iTg%a%N;O##SxDfa;G=Sy8^M^hjj_#66#((x~#Q6ybTtN3E+o;>;~r0KMC
zERil726m}5aw@RPq-nwEE0><2*z84V2gUv_Nf-SF$;(m~x*jW}-HSjfrOs3oa8+t(
zsDn(E^x-ImT`es?4YX_02lN4$8fhbaNvu}7?+_ZVOTSb>vQGMX0~&8gzv}>LkZxW9
z$wp}h?TMSD{~LkbX6Xl=AUCBmec^A5^r#)ow@NqB39VbwMRX;!Nn6vQ*Dkd&(7OM&
z^!vSN?T~(Cf}f&OinFA+<D^Td{GeO<zgw`>BRxn9zB|&(v;gXr8h(HYUzyQMxOP<L
zH4zGdGX4@kgJjLL4hok2kGA9?vMm%K3zdz|09cr;mi7q|GQ~QONZC!90g6$w<y4y&
zEeo_qYmBUwzON7~8~-}6&&c98g2c%-{|?ZzvN>|}os%u6MM|Pf)C%kzSu~a8=E~#~
z;nR6p$QWSe%S4-iSth%F1DI8^T3R?&%l@DZ`Zd{!|3XBvE;A~&td-T+LGik*D*<SA
zvO6i5k{hy^atym(_AC;18)Wu{fVnNpZvyF%{X`4CPT5aXPu(Tkh~$~1TXv1!2R$-1
zowB<l^R0v1y|RY~0o^Zq_Xn82EBlED^nk38f=TyenRsCuB!jYkx*+e%_R)#B2eM6c
zg5jZT*5`m3lBLqoyGJsq53nE0X3{%-SXMx}%@Nr|s&#oPTT08nXR=2WvK*DIUIX%6
zc7jT4U&xlaf_o`jxf$FmnfhlyJD9#@2G<--?@k24$9BG@ZHBYy!VO?uOlQ-#GY^_J
zMq{E5nf^p8w!@~4v>9?Y<%VI<!}K3oJ$Rai&@Ri{^xNIwd`xG_;o1??SwU#@H61+z
zl%uApbT=I{UAYjPpXmiU_7!4UM`4CjrY9-F8)`5e4FL@^{gs}!5vB(^z(tzA7z1ab
zOxG^~*KYcGJKP^Oy-Ee74rZfkA?au)4ue4_vxa!`-mH_p%;RGAZ801@Xy*Sd^xVv{
zX!qrAmbe-odYCQy6_}o8MlO)_Hj`Qa#mCGrhH|pLW<_RzIcio;RbKvPFDUzZ!tBv>
z^qn-z+zj^v%+}IlE6D5-Rfh$e?WWawh*{kf^qn#rngWF|Gxw8F2se9S3=(1X(QIHw
znzd0HGTQ9)3^blLWA{Tc#;gDvZAq-zkA}&hDP~Uev`#g%r@GlRGZT75q?_%ems^I}
zTUsb)n#rleC(F#~K1hz)WV+LH&EBBoV7{5*bLbVC{Yx8|BC~Z{VE3AtB~^9Tn5D}h
zS!=eRP6b{!J5~;^&dhBmP;Qug{3*Tv>dow8px<V8lNRCaW<T_y^S0S4%EEM*t)Lq3
zF0;pLG0<MK%M|eKGusyeg?_W-b1;9`tkxGIgJ#nxKz85El!`PTm_@#U34Ulcm4X#d
z%oG$p8aDff;tC^X{CJ=|HT&Qa6`MRWo1X+rqh?3U0s7pG8-)26W~sE1@G^fuHKyL?
ztL{SI$2@x!<cPV|95nix7qo&LHMckqy<_H8S7F}Id@<b>$IYj5m;`_G`R@Sign4!$
z^iG;P(p3^*ewB7Cf#&VWbpHjJzqbgY!RD>I;oB+m<2?`!H9zngNSOJn8zAB4r)f_Y
zVSe@kBqPmx=v@(IK2#5K+T6DqlMrKmlJ1dM^N4?ea>jhW8jbPh><<{|S@UDGAWAU*
zc`wYLGv6@>B+>k85gH9i<_0SJO*Vh}4n~n;zMW3;q?&(4-^NKZ|AvZxGtB3n2645>
zD+F<~7`q&j?iRPl!>6MbiMwGp(BhM+7*mjiCshpwTf9Nr<`9b!TF!-9gu1}dFpH^_
z1r4|OtO^z)EEZCZBGO=Sfda-+7Ex3knqbj$4Nj$781x_+7Saf4WLh}W10&1g!#4p_
zVbL@XmMSfzv|_wsv4sK$brw2$H{P&_r>~vVTWqE{NrS~$3OzPjxbhHbvN#nEuG!+r
zNqBhEVtF4hTPzII-hqi$i>T}P@orfx{|sKVS)^`-XuHLdC2;??#qD(<ofZwW!R)fI
zybsB4i-#1$>#=y7qTY8bicdh{p+$cZ`i3lmn$h>jVh)|>du;Lc3t&F6_+b&aVT&@V
zRT;6^Mz`Tpiyi~TpPpG1pM&D4h3Q9VeQr@f^=L0FKB3LoOA8~q<{acxUxT8fd|(qq
zoa7>UsXEKAQMIFsJc`b39hC2!1}_fD-`fuEu-s}ZBwgj<DyX~3x7S0#T^_m?jUMuX
zg_vJY`R^Ag3g#s*pmH2<`CLk?`^Xmsq49`3lBU#Gj!gxAX8Da!G#--&#$wuz%VYmr
z7s=!Pg2)NE4^?@clqXTJKR~{V@@j!{18r}D<cH|P2*L8-&0sJ@o_HJPPsyVxJr*XP
zT1CPBaCt8s4U3SgTru8A`Pou*M#=pbKr~u@dkPd!%hy(c#K_mgz{DB(Z(m?Aaq{<6
z5Q&$ozs4k-l|Q9yRf0U{G*HgTyZ?Jb%csnN7fJHR^sr8r%lsjdBKM>XZmRsiJM^Co
zrOCIoVN4nFlKT+Nls8lKCQCkbA3(F^<Eb`1M;`MI%;(C#*Z?k1KA9F<=jFdpoqd`7
z&mo|d%Nv(N;i5d4zF2WdZboa<8u_Q55UG`)t-}DX%d6L+u}(fC17J7gkB-8Sp<bR*
z2)hk({sG3+DBqR|jV8HmD$ttc9}7UcDPKlg%oh2g5Hz;Rzo)>`E%`JDptZ?|PC%hu
zUPrY#9rDt@(by@^-HY*d$*)sIN4NYp7bx_|$67$-j@*M@F1_+OM<Cf}klQVW8~ySY
zx=ilMCwvZ#0r?XfG~ScHF$Rr;(1*r-`S~U|Gb9gsA83!{(=Vg%vHX)FC_It>UI8*J
z|BQ|`jL0Kt#rRb2<cxtnlQ&a|oTFvZUNkycj{0M`&X)E^FkBZ)L(?{l>5%0NT6`R~
zEN%wpYWd?kFz9AE^gp_0Eyq)0*~4-;5Q?6bLF3WrW%&^mR(V^>Xn)~jd1)Uk9kJXI
z0pe>Jz6h3Lt^PE}AmXf68UypJRZkA|&RLn;!kHv1gFP&ySluyXLnF;9f_8ivR^5|f
zDaUG*616w1y0f8w+v@wz(br)m#DMFxVt)nKW!3j1^t-Lv#zDQu>Q{QZJg}NTJL`v5
ze@=qr6Du_(Cq}H?DBb(i>WC@GGpjVJ`5Lv--Gmp<t@g_d(0^eyKM}1jtyV99-B(s!
z=YZy*I7!#DqoR}yIw=yUq{3MdumB34iXF#+?WNc^1291fmSUU1iU2<h`;?-Xp5UR1
zS=|r`Q!M`sT(~0aEl5Txf<K{2P*hbzAyIKRiVhoOEAo<HK1ZQn27|eZ!yiDVR56z}
z24#w@V{~;Zwsb)MqC!p!&r1rAPe3j!!sygmg`zVZdX<XVbcE-M;=v}^y{hP-AZC?f
z?n5+ID=KNhdrdKA7D%(=#P@LYreZ!~GbpxH%=rhFS`|y3p>a#m;RUWuG4DFOXjdHk
z6Xdqy`D-8@igzDDu~ShyiZOL5miK_`Ry0#Jd5@w(1@$|ML`wAZDr6M7=u>DLq1Ufi
z_zk$bidy<;-hd+N6R6))bW?$ZVNkK%46XMSiN~P$KoPzIV|u7q(1I}yDf%c<`A8AH
z7%-0&KhxXviQ*4BG&ii!)k0)M@p~2eo+_MfK=PTw$^+b}B98*!&lTe-=k`LecR$QK
zaEB?-?#SIA!IU_0J4OKJY~b!tD$IrRxdxfzT*+l%`*T~q1@=j<b_&n}IGbOg7|bcG
zpcukA(+l$y_tuZ_H<Ww&FT4-qxNG3TIsHE9MQ|xm^lNiZC;$@0CHjMl=F+~zJe}rd
zP>w!^TXGU+V>!c-KD3_UCQ;5jj_bS$E}k2D2`|oaRh0Bf;QnxeiE~`C8%!i}HR+H{
z;zSZ)Cv$T}fJxzu6!1QkTeBTp8rSInlyvULc^F{^*Ff9eOfH0$ky+eZ>5$CkF20Gz
z98O|L0h`PDe+)K{OQ2e)^PD>^T=Ti5`=C+4eLzX}LQeNH`ieLuy)cWpEfk5nz&$L0
zdI{G~`>;|jfx<s!Tor}>%DG1r-M+}Jq!rX9E}!z2m$^gqWseFjmg23IT<mKGbY9`E
zH$&qp*G*M%Roq0%3|Dje>E(8fTV@8)8t&|Lh}3c)QT4=iuD1o|>o_^RH*atsSfH_<
z`#}Pc2F~>W)El`8J3*Sbpk$1tnd|ez0B>?tltO6XQfS-R%56!a!v?pwUrNEYanET(
z)6Pv%1N1i6`6IXvPDzoiPHwXuT<hXKr4M#=bH986gFRdn?V#>(_Egy4%Z=QD!9MPj
zGz_Vqv!x)?U9Rm6939}ce22z+oOLCJG|1)G!<qYBKVD-7$pdZ*{RR)Y#ip3qA?|<x
z?h&_+QaX>hR$8_{;o`QznPKkg6@ZR#A$0oWDfg}i$TKd0UUj2f%z8*Z=aQE}{RNkF
z9+EG){y2>H6_+0hbqC&m3Wy^g@I4xx_-ZN(GdT0hC_~}GXVYP!gS_o!IDCko-~jG0
zzlUl+T>0$l0CnSs>A;mcU$Gl~9{dA3!Qjc?X@n&&e)SOay!j@oe)r+mIHB(dFS`y)
zzWjv$c7uHUKk)DvZzqMne*Cx_;Eo&kIdnABpa1*}G*0k(idCNEfA$0k;4ivjz5@A!
z9xxHazfb9;VE*tjSPJ2-=$U<rzwHN+P`-KvEQRs^P(?>LKjS-)2tIEooQdSE=+zp<
z7X?8in!oA+yQle#WzdV^4P8_f7t3!80ooaU-T*}7__4HCi|3zGvivMRL^GSf7c1e#
zIex<108Qkp9>GKsKSDwNWPav7h@|l2Y4x1S%jmdu8h`k|+mL@wubd2inBwA@{E|Q@
zWbqRTESukE*ah=BygSWME`K!$=JWWYd%&IN_s)h!KEH7dxB_0-08+?XtbsxiANL0&
zi}~FjVV*AVAFadCN_ekP*e&I&o`5Uks}De-oNuD)*^7LGHOM8th(d;!`Ly{U6}*3_
z0drZ&|4xSnuJDh}0Q4$;dkn3LzYq_!YThyq+%-OtzC~BVH+~P$TE6~mxOSb78HV{f
zK7awa!LQl@QqPYq16Tv^?+DV!Clta`6F+A%`kMK`S3tSRTTvZM3-6sy#g?u7|EQqk
z7Vl4C&^F%A7#i*TnXkaz=8Ncy3LX5S<IwNq!zuL8#eYw${%+ou0-rs+H~^q`_@+Gc
z_42Ao(Cg#3K1O3duWAO^UH+?K^bPPKbX?^gKl3I=J;?7ysNW#D&s*%mb@hNhwh}{o
z$Zw?p<`Dmq6d&>5#sTIrzqA$P2`{3=*DxPOANU#JS=vuM<vr-Sdd5$rXTm5yZWbh;
z^Y3p$;|qSFEeyWo<6J>r@%Aaua}ZuP1B#<?M+|!gC&4=lt<J)@0{HDBye5I@L1CX4
zWDW_ZgVA?bSWByDS0TI`*lxlTx~$!WH7xW!gb)#i<|%wQ6JzocR?G&9x8SURc^}~$
zDv3BEG|)=bS6E~Y%%j4Zx1n%M2u_2DpFtR;u*Pv=<T7OZh0EUp^n@UO0&-GVeH@ko
zgdPex1`4N3AQ>bard@ZiaKH_HA%cWTC=-M`bk^vcaBl$|O%%#Mfk=`tf#Sr;!fA@>
zqzJtOxMos?U9{Uy6ZEu3OcxBV(Q-0FIKB&>W(uA8@GVQoIsln$;Yc*><_IxVbCN5#
zmI5?S$SZ{6dBJ`N3i-m=VVEcoqBxL3q0b2lMM8xVn8kusIz%oAhmM0Q5q8&tD;55w
zlG-vsPD|=?;XMN-;x7tW^sv7q+?@&TvatS5n5Yo;J_A~%@Zbk1UJ+KT2Fz7q2i*Ww
zLNVPV)j}G*&aMegYvEdrz?=eCD@>-!&Fezi->_6C^wKYKLkOWGR`tR<+C?@9Us1hL
zqu`oI@4qHtGzzWFLS-?AeN*^G4AB-L`aM``74EYTy(PS&^hcYppNebRh1q^Eaa-6z
zmq&--v<9wq3h(R$SeNkpV~BJM{`AqH9-;9HMs`O?T?VjTA%(uZ&?i(;$f94^HB9l(
zyMkH)g9Ab)RY=?uKK=(@3<`f|LFT>?@dn29Kqv}8<3nLx5x5~C(*t%N39&TZ$HMEh
z{(K_rSObw^;Xx-*Mufo+VE(BvU<HHEgaQ_mFe;SJMdNd!cML>c2w7PB8ze7<>+itQ
zD<Rw)qi|62YcMoNrC&BUCuIn&DxH-}_rj8kGM`q32bG}_;0`I}bi*E29-_U!t1^lz
zRo#?lOQ7Jc?4c)whcYG&#8a6~7qFMIXeC6vl@;`k@lh6cL(gzTx%>>!e3g-p(Rx(5
zhklu3N*OIa{FJ{wMdNYhdx+FZ{FU~!g*l<DQG+|F?4+1(fO0b(P6|{q3o-g2<sJqe
z1}kftAsM2qNrAyr$}O8A5~^f=gh-h34~kBNE3Li;7hzBi_`u;v<!Wbm5v3eB0#Bor
z4pcUHT6r=QT#Rz^F7(AJUu=NJ8D%-`pyHI54}-)j2QwjgRymDsl?3HGz5qL?%;mu)
zD(!E=Qj#)g8Pt=NKhK0SDN5IGp^&O{vV};R(y);3hjisks)o%_w$nA2sjMnSW0vw}
zB^0xj{XP)QQHE3KK3ADV3zIyhB|X>AD`j-tC0}_V2?_<uB`={~s7$9gNRe{<Sg02(
z&n!mc1?9yP;7XL|6_6}d+8Uv;O!>QEIzY>nkv<sOMWy&lU|&-DMq$=3E5j*8QlZ@2
zg}zFqBfWsGD92LD`>HaF>iesd@6pv=t;~LezH7?&pMa}To|ppjwMy@WAlH?-zraGB
z^5ajScSD&$;i`J&Q6o6hpv>M(`@crzh$AMdNoh=5f@bBh4<LF|xpgP>Ta-0Xu+*yj
zcP32SQXXfa*rx280H4~G>pP%uTX|^^C>_diyD_v*<wvbB(WRVByPR&N-WMW0O3MgX
zxT74Uuy3!jpAwaQ$}4v%{?e~})&`lo%E<?yKcJjl2J`onWwaz1RF(~byRYmx0`7tG
zCwjg<RQA3FgG0(sX@mVpIYOu89xHokW${G$_BpsctejI1ZbX^v2=1wJ8XdEFru?3c
zRE{b=Y0L9m$xWjC-wWmJ4<YkXxt+Etuau)pAmgCgz`{jG)gQEKaZ=4ygL77u_M*>4
zl{5!F`KgL%zj|C{mXAJv)twK~cS1GiEhwB+ZJ39?0G0m}kRVltFBF1R@sSV-Q3X@r
z@|0@S4jvjpRqs{9ZkWnq8`yBw9~$UKsLHwk8mXGT7k)>n%m_4EwO9tl(<%*xSYuRE
z-UW$O@kc?<sPd@xKTh@6JCKZ56<XnEI;&bip}PcCDlG}lskD30n51g_2@1)opZ)|%
zF{tv|0h+41rh%n2)je7^q^nXWV4I<OPSvcLsxfNJSC*<n1IcXFZxnyYQQ6aX!E#kE
zY3q`w`e7XGo>%?51%3IdIUl00Ky}XuS4p8Nfl>uUDw8`9DOMqri`zlvM<=;URECEZ
zFj1=doT_lkR5R#EcDd?w6D(a+&9(>3CDm98#$Hwp)7rE`RZd?dsZ^EP1N4e2=u4Qt
zs*=13>?)N}1W>9~EyqBvsT{)5SfiRl1*^3x%X&y&SJj7s)T!d==;{sCKZaW{QLkG6
zHAEX!p{GF_RdKX4Z&D@nf;6ih8bjo!>guQPsYUfK)mpcz#J&K%r3$C>7i}u;96;Mu
z)*r#A+p5D<V&0*8e+s}lRS^zwrb{)M_F>(sYb{XdQK?hWct^EjG36h6RYQqD>r-`G
zz*4^|a0wdks=Vid45)6_1MQybD|#Rgs%}_7|GsLi66Ap@C?6g^RBfcq-H__k_n5p#
zs^&wOpvS7&rvdgv^@wVohgBIi@Nh)6-xPMAs;-}e<TKU%U3A!PRP{&;ndhoLDr0-0
z>fQ;_m#Q0&p#Mr0Sp~ZeYE=k4bX1#61m~n)L5osnwXY>O7xfY<MLei(qzJ?z^((4E
zKdi1ZpwU(RGu1r1sdFeT?XLDDOb_*~2T=D^+ceR~9=y~uDDCO3{)k@YKI%18&~Ze4
z@d{*o)qh@q{!w+{ZxA`A&bf*{KeY+2A<1#|f;O1<SJ#q<C)A(Z06D3S_yh_8>XE5X
z4^+pdVh)4UA!9JWVD)r5G#a9o+W_p8`YXBu4Wa7o51<jI{((+GhpP)L0284;m<h#5
z^`|A^qSVEd5sFrS{|&g)>V*`@h*3MyR{&zw@vp<DGwP+AAQGpJjRjb|dLsp|&Z_6p
zUN%8Joz{rw)W#1XlBk~a9-x!dmFpprY*35ja3e+CN)@1~YR@(3OjGZor(U{Rz8d-&
z>f<I5$yC3;2aQ?kH|oG;t8FRdn4?aoF9hVO7hZv0p1PH;<MV2cN{RB-n<)!Ypq`ru
z4-3_XXfzh79fDw}SpB~UfR(BZ|I!Dx%GA@SME#<A-sdoQNgc5QzFk(obsmZp>M>M3
zU#Z^m9{R4R`{}a0s+Ln$uS)H*8zR-}2r4|irrtr<dX4(Xb6BcX_q(9)y87cn=+&u@
z(!1@3`d^BX)T_&W0!o8A-S7yljp~XF{Ps=iO-C@8X7!=jkZDoR{T_|2YS~Lzx~0BC
zsrEMY11e^3SMQ^O$=m90TmjRee&Z4b(W%}~W#C=v<r9I~t)4-(cRlK7s5q6}QBSRh
zWUu-X<(2x>o8E_dzxwn4{<G)1>RG919Z;YC8KU>p;k2e6R39;d%zgD|m(ci7okY3g
zA@w<006tQ$7y@~$9y0@aPt<7?uN_t=SHs^CwHMVAJXL$s_T-t`#u418dQuR~KUe=l
zfzKD}xwJ}psa}1PKKA}f-Ac;_2aV<-M&YROr}e9oW@aadv!>=(c;TYiUI~qZnnyX9
zghQHrvtaPBrv5xcTs8OUk>sY~rUAuWv(g)l9va6xm<vzM0!rw5X~bqw@Yd8{L!Xbv
z^1p47rZJZeyZUPM_t1J&^ERzBj%ogVA1?Z7a%mZRTr;Hse*0^pS(rbe$)<?fNzJ$t
zZ~>aH>1auyreqOFkY?3=s0V9&=wb`ew9LgXc}n9-Nw!c;DJ9OsH1nxCBwSPV6}SkE
zVmjP5L~0f-02`(8qWZ#UjcGodIjsqjKr}{kj|%i-HE#52<TD!6>EPltmQ^6}ng&|!
zoYlA;z|ayj(MBNWG<pg85;ggB1tw|!p;ddbCOHZuMdLxInNl^;v*CT3M*K0jbb}^!
z4%iG$J5~5(YDS_!vNZ3Sz^81@S~{GOqd9*JBh1yPGl89_v5kb?^O_!t3FT`ha~NTP
z#&#bX3pIb!8oo%QEC+V6=HpOI-UZD)iY1k3W>8^$spddB`pPs_J3-1dhIeS?cu_N(
zjx1f$sAFLFvSx!fyr|G<@?gGFbKyI1S2UxP5xT0;Cc{#dW&&-Qsx^9BC|uLHhQOH`
zO~pQd)@shs!}_}Bdoc{wY2N+=>Nhl#oFG}RIrcUB8Z?`!O1e?A-!KBuCXJ#JGR+#F
zS>SGJ1Uh8YqA|0;&{{QLQKa>j=9(=O+ceSi!?tVcCPVVJ<~rrrJ2Vp~!O>35>9H{1
zrD>XgNqC@nKNmhd)cg?*g(1x`$`3u#6mJH3thq!_(kGhac{IVpn&q_O9MLSG{ohl~
zr3P@%G#}CaWK<JR6`#*F1}fNjp$Vd0*-K4TBw!M(uTUuMob{);kR?ghu@f<f6zeV{
z^rc$Q^@kT})*Eusm~Q=-7aB9HCD)*yWj#y_u^j846KMUJYwfumGUu&7-3PRM>+O``
zEU^ApO24ReG`(bstULY!TCsK5OOOlJTO-j}VttaX=ThshK7o3<^_&R$C9OLW;mjp#
z6H|y(Sa;2ULZx*O9R|5#UGN4PuUbp#s8f}-IU?xz*t>PiXPBXD*4wByuEx5XBCWO7
zJgs!ETc=RMvCi7D4BQRt&ouD6-g-CXOB$@z;b?5M*3yox$=a<HCYr6oXl8F(KcnPp
zi?z{qNVZy+(mMT?^`jMNY_m2I;8U0N`;_P~+_7HY0+?QFYYNl#S<lIX`F`s`Iy!sT
zdLG?s1J<|bJ$BF9&j%WV*8i@8<OA!lH-PrgdXP@J4p}!-o%|!~?N8D8*m_$kM4nim
zdj@}pt>>Dcam3omiGE&d)c~A%W<4VbUW^*76TQGbx6Z!^6ECc5s6gVS^(#74@XGq^
zY`{2ZXAFWkYE?GqbJD&%1WV4^3lv9j(TX>~r-RzJ9zx`h_KmFoJ*@SZi#}Iv5@qb%
zwAlj2;;!9N0}CEn#W6H`Y8O&+%}Z<ekQQ6sS`S(g`Dm5(P&}fYrvvCwZ4^~W9@9qC
zw>kW@e^IL8xVB&|O!#Y~Z{cD&p}pu1k(1g{daVR#`)Xk+P+RyLFoU%EUjP=Yb^8T+
zA=-5m`a7j9n1aSo?H&p>hH0$~^iB`go{~W^LhIiI>?rNMD9l&1cFvC&?`f?$CGcXj
zB}*|SvD$+aj*QdB^g{2fwkr{q60|W?%#)~{_8Ul&wvO^y$y(b?*iF&CL13xc*HWR7
zrq$NMLWXvPrYlo>eFHs{vb4c;r)O*Rk6<E4Yq=hvxmt#{y?NU0Qvq{c8|4QsUpwzD
z=oe^f>d;uIoo9{4B5f~4CyKSx7Xj>ocI9!PlxTksL}RHoS%pEAX^+!&QLa5e1v3}5
zMH_)~NjpzLhkYuvQ7<4<sde*)#uaUb2)<p_zC9IOmG%OCMW<Rjp2s9y(@wjA#%J36
z7@!@tslNmmH=F-asM6i0#}R!eY!<D;SORU7P4FVb=CchLOPI~=@lcPnF}(squ{KL-
z*3Q^O*HZi?&Sp>rr{Zm%(5vID4d(!~1e=<#;l(+dH|f2bXwyhRnIs!ys#{IA*+i?^
z6q^+@A(?8kZU^k9*(hB>(rx-C!9=FboK?`vvay+s#$ubTJurB|rkCnSs%*Y80Ib?Z
z+yY6%HJh#LV7JC*`<IZZwQ*PrXRg~kTZp06*|fa?cf+Qc-i`G(ug*Zf!RFW+C^p)>
zTLfpCY_jOHfXz0we*^TU&4P*0Yq2rwhF+^pU<4X(*=!vPy*3;DSMaIb=8JUn-L}c0
z^>U}d<|jJ9)MXQ$3p8ij$UA6tv3-XY0S9d-ZiC_>+pW6*8f?3IArwPw&EmkFvi+Ub
z@}aitD4Q5&J83$&aNA%0OY_?5XrCNqdw|{}r)@Kffs$yOr-6ke+n9$KZnEvD9DOOa
zhS&bZ@04o0odObRwiTt|(ru3~hNl^}JA7cNz;-od^9yZR7xWd`KDPm>u)RS)MWt=Z
za*!*w4wQbpYCD0_=+(9dDdkpUtD~)Dt*x^f&a~Pl(0zZ))`52GZMLqIKWMiNGpvE7
z4%>^X0Mlu^K??H7Rz~FxPi*VIgy^vC_l=m65!<VO;rDrJn?jH0QQIWC)}Pyc?u5P<
zwgz)>FKxg1uiV|PnI5Q)b_Ew9>16lw0(jwUx5y39E_TcYkb`#9ZejF??3gvQbaS;U
zpp}W6T~7muyWOYzF&GcKoo~QzPrL7$0pn#Cw-}bZ?OvM=&c|-j-*C;>&XK<8b=2-a
zCi;%qiK!0L&u;H^=pDCfVF2cD=l34KPS~mJFy51P^54-HXt$ldn-OHUVljQ}HpFfu
z0-dMq!YOKf+HS`VbjH}NUIj~M?0%yQBF--Ob&#`m^(qYXoZW2N87JEHP+fnLT@Te>
zB-^dq2!knh657P3+J)0oAkD5M8y=?Hb<9FvhFwQCNT%KCbpXq<dt(dLpJm%Ew?b>K
zT@QWyvc&EtJ*`Xa-lKZ;GP}?0;C{K?WO{aAw3}9r#!Gf;x-Kr;Y3PQnwA-;7b9u#X
z#VPb%wL4sdz8iL%D&T0no!%eNx9t3>o}<m~svTTwx0^*fnA>(1w=frm4!gzEVX)I~
zv>p0gc4OwCwcGB<cEI%5ZKONyj$H%?{a(8>i_q9-_Zt;4^xHjZgydbj1@`db$e76c
zEKK3gTa)y#^7dDhOr7}VaroxUjHSE7g_%I7pAIrB>gmU4o>76V;V@%-0IVzX>Liri
zm_mBzxHD(yNAO@Wz8Ak{6vVK!v`=SR!r^HKbD3fQnaq4j5M?n9bkSrpF7!#*9H!V6
zpt+3lUx?%}*;JZ-o*6?S^n7NJz7kl#Wc`8R7c#DtZz(b`L-e79VkX)H>;>j4O8J#A
z$0*}p!Q`!f?KPtwMoxQM7j{t_^bfN0sowSw`^^(H9%c_XLcx{&g6eJE*f=V`b7xo5
z>%oKlV;>ql*-c+S!He}shNL%p`DZ};uvX?6(h=6s&tts4?BgJKag?pr$X+uFWpCtT
z*w<NS?7oc-iF#?iJw)+{G#UAd=6?ljf6;|;@Ha@*K8NaB@Mp%YOZa={>^h*&^7Dbr
z?CqxkJts09$jeVqP0Z@+U2t#HI;vva)kqhiz2Pqk<-0P|$}u(%<~e=vE|aOI%dMEP
z8TWs`Deqv1?w6t`6JYd}=#UH!If$b|Xb56^D#`X0|FaidxbcT{#wNn}x6gqdX}sxg
z;6)j8tDxQ{Ppg4QkDM8V{d@9%XQI#WSZ+}P(dTl-EU?a&Pbi|~ZaI@`(R?j$QaJCV
z<<{NcLM<n+hvaF?H|Z0fF_zcI!i!kTA<A2yv6Q=_FV51H*17SP)*CVOvzCV`fSq8u
zna&uVvyAotNwiG##pI+}PFxSkT!UreA<$w=hCXL>$<m*qg4LED%b?$AnLP^7Cd*rA
z0n=<*Zw2nArRWWqZ?PQv3&=goX$v7aXgPWb+<nVs6k>c}S?3P!p=D|U3=UZye;0#z
zWcej!-yd7PGZqR@ET6l>?69SwdKYA#S{4Su{4>h|dW4Ny22x4ebIVs0!G2-6jMm35
zEk(W1cxCzTSYSI?4dj40TJ4F4q?6SRS8#`|mV68pSF2(ADcr2SaE6|{RofGwcv!v1
zfb+GQ*#~meYWZ&%=P@h6KxHp}R=du^?r|%lTR@Al+MYl&YbB%idz=+}4I0T-_nyOi
znpNXp7-6nec|Rm?TD4NuX^WLFf!?wjpd@;mRqY=j9ah0RG3-t&Guk&jwer4;OUFS`
z%fX(f;=(tu=cV|*i3%|S6dF5N3R7(S41UKbTqp&4PT_SI`ss?yt+14*s9ge|E-1ct
zhW=%RpDp^XDe@?*+@R1<3gwn!69pW*72hU9WI*xZFR=SaQR@L`Mimz#X`Z;vmqFaP
zSjtMdb0SxYKX`B(4+6%M+eo2YFK#l*f+gPEpY;0j;r6e?u#a%tYQgz(52#T3DEIs}
zoH@q5GZk+8ahF@rcbqGG3wr+Cv#$Ymg4=!-dM7zq1sbEcLMmd3=H9vhh11*|s)dQ+
zUfrhnLo7Fof(vK3_}hSq<G$Sp_v5+eN{F82&c}cxa9y-?Imd-+G5LvHNic?%#BD5u
zWHMK|7Y0)}H!9Ie<^FjFgXx^9A0#ulovqNz<Q$5jki{*d+;legiz`SDH`)YyhFq?s
zj3$_Cq=BC2#B%|Y&mE*KWdRqk9*TwBD8=84xckRpshB%ofyN8mDXQEp;jF1{tC|}L
z#hB{3^ZS9_%5^$Jp^H2BIy}6~Wl}ZO5cl&sG>&pB76AG=cd!nUFAUs{snCDP#TBCS
z756Xgj~)2_9AJC$Q>Bpc;x|%I!kcgZ7$QFW^8|n%;m1*Zxi8;%9TRknU%UZ6`SFLm
z0d}14rU<1!@3ju(1dn(HehPkWJ4iUcpQ?l+_=92KB6-86S3ry6?dPL4non&2%xNC`
z5&S^BUq855zT+iC<M@-Oz{T^o<6!qJFPnyWO5i2YFn^9;{2OK_k$38aWD<XM8%Q#5
zUkc0|-qsxB&E>=BX`IjZ*#WwMcO`O}zi0RXFcth)wGh3+JI{pTRX+25aP|C}XBc(^
z|3e5woA`guK);!<p*yvc-)s$My7>FFsO#plDdp6|e{c^XcX*bzD!qIZ1w8tA%|(!Y
z{w*?pm;bd1dIS9Wtx&kfZ#Oo;(jad^W!Lxl{ZZf^@C+55Kjd#50L&2o<wN-Nm={(;
z;|V{T!*4Lm$Ib>f!q55<<SBo7JVyA8H@^=@NBLdVu=Je&fT|Q;@DED>_L5&qbx^N(
z3tAsL2p!9zhYE;L+W$BSAyiNAEDX}6>mnQ|LZ_DyKL(B7Lc%L3`Uw9ZSBy%A=R1IQ
zR7hG&Kf18t30(6NhR49s<3c!XS|fx{C>|CmJR^}PA-NP>v@l};lBb0kbUq_S$e{YR
zSYbYXP=n-*;8_pFIAPjZxF0W^IfBl!!Z)!X3Bs=HaORxwS{GbP6c*FoH%Ta_M|iSu
zH54MLLfD4@O%qOcgG(38CWFfm7E@oQ5cXflT1Z<1y=)<eKFE_JY@^6#t`K__vu(%|
z-l9zGdEx7Dc#$teP!hjDU@0$CC?w3su!{u6WHc5FOJ0XYm9Rem=BtI_?dYo!4#Y#R
zRv4Io#v6jQ5+e1&52N4)gp_bh*FE9X+aRMtoD=$<3vDeh|3dIy0t+t<Ledhnz7p&m
zq2Zvs%E41d<*uLMzLWBkZrF8Jj;B|wi!x*n3?5VpwA?+U^!yQhhm`|w1I<<W^*cau
zQ*LpEy1TOW6gW?%5iNtfl<!N?=&juH6ZCwPSE%~zh;sdV=<`(?0?L4WRM|=C%45n3
zI)LV<tg*+Kjw_RBX8e`+=~;F{IqD41lgfrd=m#iY$I1|C_kDYT9i$wj1bwV>Kdqw9
zC@0NFW1Mo}XK?Y#)&uxO&MJ5R3Fri6&}675D(B?EY?5-H;W5UPtQ?{>Xo^yN1zw~o
zc|TZ6Qx;c)guQS3BSx6={)~NaCiVS<O2D{IdbAQI8YcV6V4{6;MIlgLOpT^k=F6!o
zV$gVW+P*a)C#MzB<0@d<LVD!{O`Dehu(WBR9WY-qZM!w?e@drieFvG!X|8mq_e^u0
z1GL!bW;Oq}wA=F32R{F~p$q7L^;7obZ>cG~*cy8WfA5-K3+3HmKEU6TKm}+HOcBKn
z9GN@K;GCEfVGwX<j=v5R4`w&jAbK&`v>H9m7;b+K41cDczRGcmnM_adP^NN(M$Y7l
z(HF}cqM+XyW)js*$1wrxFjeu)Cm#bel@ZY)^)%)#T^f0e><@6~nX?l>@|nPT=oK(U
z6ra1qlu*w4GV^02Fe{jkT4AA*dCyRU&Ku04cY#*Vj5WptG%)Yc3#yS(dZ4kLd7Dx@
zx0%V`fOIe;rO@wW9(;%qb}_Ba0PSY}c@u8;Fs5DTyTc69fsbD1ofz~zU}}b7;UUA&
ztv|$Urohi5rj@=^@|gLUqfo>P<~cq8UNQ|-Pxgw*iGvpotcqUCj%;8p8lBjhCSW_W
zzb%8L3+q8J2iY%Zvvr6y`W_|@vnx(P#Fc$#C9vJtx7{#8cXm2GQ$5)7uOR8kUZ6~+
z7wgyuf4$kclj;1g5Bs?v*dy#idgA%A9+SWwWdmr*aEy)Of#%0f8w>2?>?0$H__HUe
zjNk<O*%tJjWM`~^i2&Ab4jc_+3k8S-vGb0?r(iZ~A?7fIy-ne#Q|!}8&^yhdBms{>
zwx^KlPZQZM0x_5**8VIslG#T?kV#>0M4~Z={je8}x$JlfXymc7`M^HUT5W>ed^VA)
zCd$}=wdgBnmwG`G?;46WTw-77pnjPxSq#@ISn+NsRI+Om0o{ymXh82KdxmmXh8FhP
zYACj{+rNflJG-hMik)o9=g{b4*LXs|n>|LwL_O?pOX>GzmwXEMd)YKPN7%=DTcEF>
z-ByD>2T`Uy6b_4i<sjlMx;_R5kBegGqA^&M^%8a?MbCbRg?Q1gRJ?oEAbJuFnjjh-
z4=>J%nrTy+DB3~^#3Yfj3@+x0T5iF_dC`NXFqkjeGY+m5h&E8&YoRDggT5kBfF;ad
z5Sh}uphT1~3#3$3nFCTL>Z0UexoG`gfW9c2(FFDDqTDKY(JV4FjRDMU(dZF$_KHsK
zMC*M~59LpWMN5r<{ZjPyDrg)MZ}WlshsFM{(B~?iH6NUtxcxFrxQpMQeY%JEGm0H}
ziZ6cy?xeWl3H%KZpQh(Vp!g`An+g&q`~ngzJ|7ITA!1*{w~#p{&RGxl!^9Wp5fLu-
zs{u@eIG+yrMT+Z&K%&GO51=nvJXcPakl0BFy%g~kOZb~DR#5P*P&{TXd@2_=oPzpQ
zaRFVjb>hvFVd<tgn}I@ySfHZ={o-uO4%`)g(@62x0r5Z|*n8ryXxB9;PTzrH-xm)u
z@brQB?|-22Q0)Fa^k0hCE`}Gc#C1<0=^&XO2-h4XRrOGClH~1#YtE9-VxZt6d1n(a
z4@zdlVDyLa|45<FRgy<9G&jk-aDcf>PK=@Thlj*n1`SV%11)&GB)$}+@s=#2nz0j-
zADke1Qc`dUT!17q3^0L`DDpQ*a@v#TQWCKjBt)_-6q2D52Xjb<;lCgRO1NZ>GX@wT
z@u4F)k&+3!;7k+_Hv%PEat0|`gXEmV`Z{D1B`n?kNfP(j=uDP4Q4wH@<ZViQr%Jpj
zq@5;Nnh2P5$w(;t&6M~}!z5%$o>C2PwqygPn{p&!ZLpgwnM#*Ho+Qo<VCN-^e?wzF
z{(B3cluMjPVeg{kj}#~vE=i_Pt=eUY%OQ{o$^X`YRN}kquzN*P+z6Sgl5xM`H>{Ez
z_!#=vB$FuOQX?sP6DDdU(hG3=y2R%`8tWu3`QUCy_R<lndP&3A@V7zo1La*BC7ZSY
zx*IjnAU%@s4*+(@AbFD(*}W2*Yz(GP(n=Zhew>j8_JG8O^zTWAeIYt1$&H1`eaY{1
zc|DL+RYUTj<T8CE;+15PBN`oydYs^>qml6is5=?W@c^{5QJ@}uE=Jy;K>eW6b6<FP
z*eK2plCDMub`aQZMsah%x*OHdI^4r(*@po2G<r(mUoWE%U%>r9qbei71Q`|Of(th4
zz6+5MqXfDQPZ@3d4qT|weTqzn8HG~9Gu&vqCp?Ta+L;IFD5FUXxM-u+9WZ~|h@ns0
z#2A?v-bH7u(MT`m`Ha#3jzBTaC_fi6#YRPo@WWm(vZq*QrIAY^+;277Jb=bqMi1zK
z*$bo1*I_r-cyT1qN{n|<iFm2;Ki+7(Y0O_i<1J%%FR1q!PtwA*2gWxkhdW}NmkzL}
z#w&tp{o!Wfe-#?;CX*-;?q{<69L$HB?D-cm$tJ(Q!X)IG<mSO{iHQr<KHfCBT?0oS
zn8XJF^ssah<>>vS-n2l7kUAK{izI131=Q1}Ck2RHl72%=(92TI6zF-#Y|YW=Efe&V
zfAo>v6@fh>)6+)wsBFP|aQK*PI+aBqmle{b=P#Qv48H?q4Am9{$@-~+C0I7I4<e^z
ziO1n#sBFFs3`WX)=}8(To2!Lhw9JT>MX|E8GN{MPKHiAFbFvdRpq?z#c~bp%s_emX
zbf(F89Xc~)fBM5jrtCW^M#z#GQGh#J=0vx6g)Gn(<cjPjMMSD)2hGq|E0d?eM4jv+
zeVn3R7Gi)Gjj|&P0CrRM`ZYAR%eLHuh?D6!Dxq>QHCzOD$aDdP;0>;(@~xO|Z_~p%
zh#oQhIvK>zG<Y)f{Y_gRVoCx`mqo!~u<4Wg6zRhsp?wejUfw}@qZJ=gQQyktbZq&j
z$Pe)ERd0L1z|SjRL3j1U5Ag3_>Lbwp>%m-rt~n403v1oi!s@yh0|W9~DWx)hpJ0o>
z|Csp>)Ydm7W275=XzRLZ6{QIEU+%$ZcP*WcfA20m3Wz;3-SBVw@8$t?-x6AE{k!o)
z{QE$Q2srqPF#hexd`KZQC+3hIZO+UNEfl>N+d4Sw&G<I{_xm%;-v@hySsMfrz<m1=
zWCEGgAAugk^dJN)Nn}>+fmfM~HAUkK7|&u1s+@U`R>4(Fm>+HMX<A(0!r!6n&Koct
z#)cLFFPwdsGMy1@<q3EY$)30YM`PJuTFIPYHyQ>2c#hrQ0Go;IIVw0vVr{6dGM&97
z0++!an+KA~HXZ`WVtY43|2#YC2o&<!b??AL0b50pwh~sd73ND>HVx`!tj%ReR<K{X
zz-}eGnkvt(u{iLDXD6Fd49{!XC!Pj?UT1GxLZ*?u@CCRgcGFRC&1?>pWwx>RUjx_9
zifPqxoBeho^gGzZ|5m~5@-o=%Wxp8*>^`=Wsw@ZDy+vqz#7;W~g~zOS0@R<d$LN9?
zWs}~7T?f&(+aWn5{mYZqpO0l%9#XCZe_k@b(lhoIQ%2L{z^<GD7aZCB4j73OyJb9-
zG13fJb77xS#o|G>#uR;r*!>i?J<NWg!+f~1g|ygqV{e6_&z+r5K}`>KNfW?4*)Qhf
zxAS7l>HX-<8umVbK_B*>4P*k?kjL;gke!%@&LCEmhrSp#vKN-lu-EEj|KCfYXAIn5
z@yAb)U3rae-k(BgyS%CigOL0@oiJAWIKhQqFjctj_Yb0F&C&I6ac$*!fUWyzKjeQq
zFp=v2eh;Ly)gL>n0J?q>oz&Q{q8thvmr<x?Q|d>6*qr7JwXNA-z}U`>l+fP2m0pc|
z+}=UE3-j|LC?905Q1$j9CU6OjiTU^o7(BwfO~v-UOpzrVI?ANH4uv3Q0o6YTGv0;{
zxE#W$3gJR1Q?L!K5zJ096U_|EL1LMukI@*<oR|mwbBqIhuc?YLqepHv<4%Pb*O<?%
zVX21MMrF{oOvIny8kniGq29vmr#;ne=1aQ#`<PfU`W`dQRBQ2!d3e(RnHNkqm4m%v
zX3YY&BRgR{U_#k`FEnPbGmzl;@8S^ZwfILiV?6~rIZV)>a4VO2J_^7*W;P`^&odcQ
zLGqan`W8?D6BG)dLS`B5u`e;Jd3bP{`Ha#&6-+5z8<mVfpg89hMntVwnIcN`Rxu}}
z|Bdc41qC{ofti@HPUh)%;JTPdI>&#HDW-tkAk#>n6CYuQtkL(B`L-2cPV7)7yl`g6
zehm>9b~+s`!JdmsiM`q2m9Xo>-YJFTN%oi_05pKjK^g_u-LH)xk!=1^n2%z4+KNQ8
z@6*cWG#mI|h>x|V$72#(`7!je*(2>3Qx5yTY*@-=>x!VB$0pL|p_DyGUqdcq<3pfO
z&fcH^<wZ7*>|JBmuLpDun?B9}jav3DJ@T%z<7i{k!hU=OovrM<vFN+STF|B1#uh$D
zUpu?#L(Eej3k$UASx%YzyX*!E4-K#jmVw;EC;y;6$VQEa`h9lHMNH5G_S`-wJY?Ue
zEZGoiNspgL?6JLc{_!#U56$xvwqh@Q8)mDz;OPjv_%96YDJ!Mb^fPvHHMmjs5Y?JK
zXS>$|?FH*cm0+Htjklo?DC(tUR=DUDm7v6mHj*>RqVfJ9rJ^0bqp?vGMj?>_kwT9~
zNAY*tY5y4__M}&JqWIhl_*N+Ppc17j@y3O4zg3*P8;V2XeR_~l@rJbjdjwQV#!>#P
zNm42!F^M@X&)X#XwqocVk|{wz>Xv-48zOy@gc=yVhyOhl5LhpIL2_6U{VRNaCJ`GZ
zfPE#&G=Zp#(RVXm!@%%|FGTP~@>3gK0Y8szM&~czm;z=EN9*c!%^8r{9Qro~yd_$V
zzjdRIz|*g7z`u75@W9-Ca|W~=n2-z%$C0U|$B`RjNjWcfMn?giqs%Yc>HPOGW-P_P
zf|#auSPN$Se??~$vql2NXhurO&ID%jQh0xk`FJ8E6B#K5Q8Jm~2XH2fSw(NkZ0408
z)N`1E7f{b-rVK+Nk13!S%6aBuCQ$O3-|Zn%z&O4Ju8?_DPW4ws%sN^Y6f?&t)qH{3
z_7kv6m@>)(lrm@OIa9_sP$aLM@!A5Bi;M#Wm@hFqJ_otXjH4RG3MO$MKr5NebP-))
zECb-hRpvbk<W(`%v>vZ!<V|S2#{44(SHrApfHQ_BW`GL#o0;F~gwjps71i3eFu}A;
zZe^DBz>8bV?r4bgFmH|p_8sPz4G`&Nq!jb(W3Etiu%EH{3)pv=MJk{SFoFo&J!T{A
z=9AdlzXL3T^`qxV7OQOpN)9`bqU(7Ec7rcO3)%52F|!v~`EM9Z89TX+M#zR;gJLCH
zLjl(+wuP3Pwd{&NpwPscyFjFaop}(hIfzE_3G@H|lysx92D4SWKtkBT9H^dR9SA6t
zU0n#_Fjg@Sro-9Ne`)<0!9G6()kyYG1>B2blSL4XW|Q%@!&6816|BUtTmJ{eSoRFn
zSDj&H^dOF787kw6XV;rT@+|u$1t}8PcM>3Zj?Jd!U?S^g2}?<Ai8r`pwpWk76!v@C
zSZA^)C@E_wWWNXpOc6V>3ZR$R+<ox-GP{8e?pLtK+8|TOim8acj=j4T=5Me|X!Tvs
zZcPT)z`kDsy*9Sx3k<ZKt)~+Nx7l(E=5(+VC@k2?Dkvo1#V(nFzHau)Ht6-R7c1b?
z9RvGt6<q9P&;1FQJ~oMB#r^DlQ=r{tHDwSTV4WsG^d38nj)V=ecTR&0vszl-j<6wg
zO7$tblS)*du}&0C8D-5MqwzU=s~nOq*fDcJUb6j1(RWC+`E^X!VNo$XGkrvcj&>*>
z5yk$D5uOx<sUZ^}daoT^xac6ob|OUS8=w&<T0z;(c#(p#SgE2q%DkkB#&tt7PgF+b
ztLH_FDJ)njnoU)7Wul2x3RNyz6#&U<(JU><HIX9)sA@!kHSnoc<Z7TN>2=Y>26Wbm
z{AQx_hG@VScI!pU=_3;jq7?dl8bzH3h%||E7QmTik>+(Y-W0|3gS3c--9cJKuc(0K
zmT2uwsJDsSsaCpOw2*H0PLYnXnq8u3+EaFmzP|wTJtEN@1IF7Y3Z?~8zsUMIxVxg;
z^!^zTt)yJ%J&}Ds$OF+4Iy?7JRJI1#L!u=SkbEHuI|ytC@d2ukbrjdrc}XYn4{Jf3
z#Z&a?a}h_;p^AgzUnv#tDsHoYAvdw#Ld=Y(xcmRrb|rpM9ZC3gzenQ{U=)m+#6S+u
z$TcY75jF-eUMQeO2nY<rAg6;2heipyN>JAWRP5l1tQZvVh{nMK#Ap;(MP1{Hw_p_G
zu`w~IM2-6uzwDn7^;xf~tG=r4dA!%%Rr9z<^*2kk-BioFOzZU-be3z$+3-}Ly_SJU
zw`x^X>b+Z=e*hK-wRdQH;iwj|4Jyd(?}G5YmOh(4Uz^~&h+?7erjc19TxjLAOzf<I
z%4+fC8lcyR{ktJtD{jsQw@w_)qWtT6F|Z1eZV<oT1!#%LazenR;wJ57Z5F%i0J=p?
z<rIu4&4+NCP;>yT5L;=Bv{GzqhFz72{vO@lAr2k}*(vs{2Iel&H|NipwbNn)l*2~S
ziY<IfM>KwRzB3%<MjVbn^pVznh<a*4Ae5rM9F70un|}e&v@+V8O{g{FJn;rq(WNi(
zfxab{3NkXB=#$F)lHPcgRre!0mA#z0Hhb(V=r3U5J!$M&IZXkUvR|TTMA#&Ipe$#7
z%RmZPZupOgzL0(Q5|>Uf3!&%e8kR*r;cHnxx+AS)^KZj`J<DtX^iF21g*Pj!$OBpp
z+c*GrM_B6&kQ3}Mt-sE&a|1C<7uc$A5#tq>J{DXv`<b$e_t}UR2%oS`9e_EPU(2QW
zOd*e^?BXUqbkY9{PQu@Ypn$c}^1G1LyTZ1ZC0~Q>8cb{v@>=FZiQ{$5-~*qV*~G!n
zEMsHn@l(ad(szEhv+8mf>|n_>AKb~JDLYZknmz%yk39*)0PN3Yj&~qE!e&uL!BMvE
zA$oU;9ib=2X*QTvCI4Y2+GxAT&I|+E4OUeN?k01Y0T)ed;4XBanH5nApn|7&fl4JW
zxJQ=+-y49QZ|9z;pt*y0p>@elzSI+B7hl*3<Qtw_L-l_rd0QncZtz2W;c%n6n$oK!
zYVUZoZBqYefQwS~ga*I=RF}G9<Tk4rerPLGYx}}(i#ipTvd!1(&~&Jjt0!nkwyHho
z%Z=OAlYJ1{axJbO+6uHGv}7#Qj?iOvg|<028y#J#{Y*QVtF)%w2&zaMLAT`9noBi=
zQkzEA%U@|PO28Fs<EU_cjdmaue%ESYG|R{n&x5G<V&x3@-7XAog4-<~&<uUA@b3zP
zYGHbTP8<}S>E(*GB7jy%b>jVOTK|40@*JW1L>wxH>Jr;F`g&8P?d%>99=A2`1NSf6
z-m?(J1zUf=KWBhH@sD&se8_cs5Z5ofm>%b?{L7UHsEs%2p`EXGXry@n{yD9sa#sI7
z+b|+yW4q&gT;@5r4$A$8@)hF`CBb@ve-#ELxF!P)AzgX^J@j}Pj3X{i0BEFr8(OE%
zqa0sU;ZHb^4k?2?#%&}5FzgM1Rnh}DoF|W=<i2G|7~;<eErrgU;WP)$QHH@PkC{;9
zg;in#J)KbhHj5^63t1v9w-&Kwl+3AQku@;b!>p8G+RySR1y;u{_@nI@Gp>X16l<~r
z`8N~$5qcwght`bOS@BhHx7iI_aCl|j-_X-mmVXR(FIk`i+U9f12e4bjlMFOtq3sB#
zN6Cmi@Twz5V&q9$UuL%2LjIHq3!-?&Li+>eIddKc&=+j@cG$mSvGk3ex%}cN2<P+M
zZqQu7kJJMxpC6e6PYb#IO{lEoZ8RlW#g}#lSH%mA;A;4YTMAsz`~S}H`XY!LxoH_N
zE^(hGAYSH+sE+aq-w*+-t2~MFeRuddKWMh_cLsvH$B#E4uKWCGdocrlK#S*}c^}#@
zY2!o20{(aYHtoSKR!=?$S*Dg(1A2v8LN7jFrEWwaeJ;{N68&nwO1eeTZ0j-WG80I@
zu~?e)wz35|@cD!lu0+?KvIN?rdB%45LO7obV|%yX_#8f$@CI+-F6GUa09VA{tb_S#
zexA}}l7CFXjr`Ukn3wR|G+W)oi{{Ytx0JU&fa*5>g%8|U@b3o!t&+dK9x?CX=byv=
zTYm5kxEijftY9ra)&@_<cv&l8j&r|R7^5?M$}4bZ`A_!Hyv#?^gZBy_eg$Ax`PD=S
zukml_%_P_PqH?s|;BQT#`lp+G9c90p_=F$ezL^Jg2f4-fP?GOg?hym`k9p6-Air_b
zTpAKScmo_h;fYk+{*3>g2F>4j_$+koIqyhMi}`B(Fa)zez2pLw61C+b+*hdOcM;4X
zwI}ToTvS7z()iy{JKlxPL)DAcc&+N&A!vN5esCJ9d0J2jf|1(S{s67eUXBJ=s|D9X
z^NjXJ3&OsoZ7PH2Q|*Q$Li>l!aJp#~**tCmx7KD`0b(k(DWn?Ya+{be2-gV*+BDf9
zY$?N%yHRwaz55dJ>^X*Jt7xW#ScSMx^);2EnKn<hi!F3x*d-P<g4-)n!V!g4q{YEt
zpXj<6Q5+EQJz;QAyyc3}YDH-a9M*|o$^#x2?>oT!h*;4B=0`<RSJ-_oz6yo#1b*4c
zAy}LikLcTl4Z<!0!JHAkbX}YmKa~7=xBKLA36Msqci?1nN80`x^Ra;aSlduY#{EGt
z1Zhq<AMd;trV}zAp*1-946H(i?f`V?<yRP(iEG->_eq;5%E_k&C>Z}wy%r;^DdQ;3
z9X2`-s^K%w1LCv8G{29COaOG`rQ2wYI`0UG=;H!zV*1~M#4v}JF0m`-K+|ZZTwYwp
zZ6KI_rMTmV&^%yTLkZ3khK++f@uD3xlZ=CLo~&Pu*6@@Zx|UMA7NKE!elbMmhEZ^n
z7H}KAoKbKcp``zvQjnIM0gz`qhv0m6zAxnS*t;Xqk%jE?P+-)t7r50c9UT-!RjP!n
z;@rpAeMDMXN}|z_k!YT7ai2IT$V=~^8EYCH5a?z|OLO-(PtPz-&#<@$8dDO}EGGA~
zl+0;~(3GFp@IaSTgVAj99u)2AMt}7ldM}S5o?f2bdT;j(vpK~gx2W9tulA9z@xs5_
z$1WS*=P&kQEf(A%F8^E-x1LK<_hreq{5$uPApu(V{Oe7s^?H*Q|Dh~T;{Edt&Nes%
z4qF@@aCEd9oIB-Z$vX*l4t5hm{iB1;7MFf{{p9}EwxUk&Rapc4JLd$9bf0W7rCZ#M
zhV&G(#XZ1m%uH?na6_j|8s%<DGZ;<L874!jyZ?ysuKtGfxac5rTxN<XdZIZ#BioQ}
zat|=YW=^x#<##^twCkvefzh9i7&kf4#n+?#&*c2ib6>N5o@+O6Ue6((dRI?x50CyX
zo}O-AZk{f<HuN4oo_g!+%>G>m7f)lX!P^k$ZSe5$@%7XjJO=4~e2seJV54WO-rL(J
zKTKzj!@(M+)1`criwvQ{aq(`(V;5B?${QU(UsIGAqPU(f5bdHU*kMyRN*gv3?WQP)
zpv$`}$~owAYzhps19euEYNGEc%2}el73D5b%+2-op#2pkgQ%;bIN|4o$0}C;5Zw@D
z$Yf50ZUS?Wr-}5Fy&^$8WGWF~Sre(tW~1cbso-K{9+3ojfyh^~ca-ipYS-m|qjckW
zV^8T9t;=FP<hRi<36ridx(U3|S$+|t8_$B}X|V9s%K!p&B0wjSChcOOTJ9yIVgYp4
zOKt~+_$7(Y4wB=IU=_LE2<3(HAqd~;EB)d~*;g(j`pj2e2Zffa30gB{4hX*+BpXbS
z&Xm34!9Kb!r^mM=*MLQ&cGKDsrxF<@t3Y`5VEM;1=;&lnLOalUA|CP~2!AwG`X!Rr
z59KmYbl_Sd#PuIZw<NF$GA9Y_*^#n=SYO#I8MX;B6@=G~k+sQ?21~mXuy@DGs1!go
zj+fh0bOV^3yp*DQ4@3MiMb{Uv$mB|m?4JsWSq7!*`tm)B%u3bu;f=v^1E`ILUuZo@
gZc^<X<<(T34$dAz4If{(>9DU4(J6VdDO%_FKLHRV#sB~S

delta 128711
zcmYgY2UrzH*S>q(*4rDFSYx8G#2QWP-PjVlvBy|qi5iV1Msu+%MWqQU7L=+8D4-w+
zC<+RqC`C|21VsTsMMV_U|2-u6o<EP-xpU^c?>RHOJLSwQFYXP@E*QAC1rv3;rKeWv
zBNt_#B^w0UZ#Nl_i(0e&Z6{Hts@tfL$=f^hmC0mkhD&J5%hYm}$65svwrvzAQ!7=o
zKXNivwg)Sd|IlbY=_y%rH@QsBsnTMgz_CN~SeZqsTD0sBDr?F?J-(?ZQ#hEqKwYyF
z7gdKUMyBX&{t3Ue`*E=@_L!*a(I#=HQZ|DLfIun!IB>jdX2Wkzimz76W;Ohlq|qK>
zI){;?(gm6FXGW0@U6$Nc#SUU*GR2?_UM6cYVdz8|17DQ&<;*|D>Mwtz;#sT`SN3;S
z#wf<MmdoUd`yP7zXZB}l9F;y40aG0pS(&<r;!gl{o!QQV<T4o(lgr82t`hkwV@5Ai
z%Ge$a86}gN3J<<*$Z$;lQ`qa%kdYXDg-XWuZ^-DGj3hzE4r<7l8CN^hhBjmzn4#B1
zyNn&#kZa25TLCntA=82><9Qi7z9I8Dlkp5LOlruqWdba4VR}QR1DdmsLdMRKAA-jX
zjlnMb8%`@8UV^uZB|j)o+dJQIsO`oxxDkpcN?xW^6oe>cDw!(5OD(gr%j9E$&=Tw)
zhChOcLEq47q3zIKGL`8#D`VHn_xw+1V;SjeOhuC`Mh{oPivJ2VtnBTthLw!B99g-5
z`>)t|Sdgh@Dy9t>w#g#_Yr4LPAe+NF>0=c#nVkvwTa>Xb%_$>eT7QY^>~2O4uVjXI
zM#<i0Zm3&#W~(zA#J!mlN_sGhe?*CA^8{deG4eae>}#2cOdlq;FVuV*G6R??#c25h
z4VfW~ODvk#w;?lv8Iy$Da2S~mGTCTmXCp8iZ7BMYxqSqgW6kJMoXB|n2#|j>y7^O?
zERRXXc1*m7-PmSkKy#&xS!rl^U>SP>Twm3YL6uc_9GO29rSPZui4sx9mkWe9Rupiu
z3(CgSuJm6G{%3sG;;EE3LMvZT4tNNJ+-<3Hjt66E&aCoiX=-GrB0puH|BB}MDP+f$
z4L4uz_J{J%7o03m>5u{{6~OqfWf@*(#;(**W(NLee66Z~P1u#4{^9vUF266z?8?66
zm)vcI{HRrq?D&7OOXasCabuJVk;S|2_N$EF>yh-YFZ2J$A>)nB<+5o?D?K^%UsL?g
z_%8m>+BD^N|5}srzmLNspfvqg_1g`aXa3VvDF^;rKe^voJeSI!>FJWYEm6*Cif3JE
zA)MSzxmLy}d(1HZ(<rHm{{J78s+j#RNN$W}WvPl)W;KE4HE^UU{^eLJ)05mlP#MSL
zXR8tI@rakp@lz%<L(KSYAS5+>xxB+aHs&dN?c!z6<o`6h3in95?D5XrbV+I#wd|$b
z)_`zZA>*vLokGTRRyJ4uUu6^EJmYI(|K*%3@AnVq4Ea7E74&|l*G=v=UEb_F9@#(t
zxd{^+{GKQO*YD*@yN9FYvlisW!hhXxTcITLi~ln}PsTs-xL|4YExA5K-t!+bf5?Po
zUF0(6fBqDqo{aC-|NLR(-TzTss!a9JS(`DxdUUcnG(307%)cB<8=jYBX4pTz{o3%n
zBs0_h$<AwdUXqy=|77Phcz%WXuf-djyvqEqjfAg0DrDZwf6cR|!JV1tgd3XNn`v;z
zj`yI!s5dkC{~PsYrv87Up!xqs_y5nROlXaVv&a9e#5Y*+`p-%arpNy(jVA2*pLc)A
zS`U6F$e0rzLu`8Z<1yLx6_Xmd$+lfFDF|JG;xhs5hCa_jE~?B+rlYfKqE=b&9>AFP
znd+aSt&H-YAAyXdYO(z-bXsW?yjCT2YNC)SB)Lkxhvj7oPN%Y(J!UlN%D8*%Y2v^P
z_6Tm$TpGJiMAsR_aH{6FJ+hiCleY-;7~J$5W}(OWrk(A7&S7N#uq#!6?Rbt}7X3K>
zwfuzFM%K~H;~H@v@0!e9hHhK7B#{(GO_$@k`MrSa+&a?Fd`3DeK2quVTZHxen@Z2m
zBl*Wb^kOpmMa&9hPDyl4T0+;Rc0U3L7z0(ZedQ$D;7-4*1`?oOz5-YOlO%uSM0DoS
zWNf2?4D821rIPjOMUqP&$suJTU5^hW{a=HLA^9Ak+#8eTr)rXT{z|_S!|3;!L3RR9
za3EOHF9hqfm&^~mLtbxvOJ*kACDou$q&ev~k~pp>&9(igJ$x@y3w7E>3`5WzqqWjW
zr)?jSv>8Od*JqGPpB1D(t%CT2+BcLQRoan>>rA46`J}`jrh?zUCG)0{M7I>Zx=L2_
zH;e1p9d!MniX=a_BF(IIq_Z}goCwOG(w8yBbEgwYmcOLZ?}pRwuhvpa95_R^niLU#
z&xz=<RkCjLsMzTXQf+FY>*XV)+OeS?b`1C`*{jY}k8?j#4g4@GQppw^C;9Pma;0M~
z=}%lla;+=5#ix+`1_mr#Kd0968BN!}D@d|&c|-ddz-E^Pr8m^05qXsHjLa-QM3VNm
zNa^umGC8lIB|e)=;MGnfS+SJrTCtNPd<<!h3MPhq<H-qiBuRRXAh()VktF3es&~yH
z`d!eO82(Hk7ww-K>ajYQ3~y^sboV<F(ItsmBD$e@zg|VZxv6wLT1}d!Kk4_B21h*{
zh;9&Ozbe_&RC4{VoAi5qCb>Acp&C2tNvCi+nRn5XmE3sZ8Dn=N)&8fcI5wY1NBfXp
z88_(~9Y?MNHM~e8-qY{9%}F!5fPVM#B%Qz9$&A%RhMP3pxMNGGG`lOY?KwlGrKhO&
z!Trf()e|!B)KKjdot=~_e<Y%8clteHE?u=PNvYU}t{NR(OT$U$Z<>I~I<%qRw-ym;
zb;Dzu+Mwh93mI<YN>w^Ln~aTLOA@D6gj!)BiBU(T*Zv}G`uCWus$?TEAy>&>SI|A%
zN(%zn&*fw?wFCX$q98!y1w?c*hvZd{NwaH%zR=K^^PiE<j7=o3yH94UJ*eI?tV>j~
zIq8JTFQS&qbE4A3w#57_5tCJw><A_{D%mPEsg}CX?`P>`Y;F;ee%{de_`amy(JWB}
ztf!{F;zkB)^62-s=!Nm1-5~6r-VK`5>G!;sRQgi@nY`7Tt{ywcO5e34Z}}yx*kxy4
z(L<q}Kq4<QT?fx1I`1uXb@d`Zih<-=7s&kQVboeePclCilQrl&62qv*BxyIDBx{|>
zJb!>B>-<R~b0zcHx2a+m1!B%QN2T@@o{C$ikO65NT^&b|Qe1-*+b@#IJ&#Cd?ryr4
zJ|ODT66st%NQMnM`aRD;jt;m&lH9xW+vOBtzvStf@Q%zk&!B7RW-9etM(xzno=%xz
zm#I!2e<0OYlgO{EokS|NASItP(iyvnbfjyfV;o2|_-i?p8jjQTMmjlnP)<7Ia*3h7
zlzyK|B9rlLh%IIvRd335lJ{sw`nz>lJE0z1$iVtmq%`$&x?UPg#nnTpuG1zHY{Ej4
z|K5?nKdd6sOJhiKbrxOytBL3Ke)|38N<y8TLYm!@3HxUsa?$-g{SN<zY#scYDzMT^
zP0#<qS=4B<=45imTKa8vB)aRNMC9F<h)NnHp5GIAbUKy34J2cKtRYl!OOl73A_G1>
z={iV5I-bFFz4bj^#R$?I(u>&UJ|OdtESRFJWNzb$X#Yzp*sy`Fz70d_tO-=hdG+K(
z$!u!UrOyf0q7&)oJSH<mhlsRY1W9Ixkv<bkb-f%%rIXH+;c$17>pl?A^T)&=@`+IH
z-+|LEoAxUK+*T1Fb~*vh4<tZM1OXmxq2GU1($z;!n$GjciScPflroJ_Z5EJo1#)V+
zjx!0Bu$&}qcN1#z*VH!eMv(l~dAc5JLh`E(Ba3~fBN2`0P1IKt>H4`V8Tc%=!PBwy
z+kYk1@0lZko7qXe;%A~bx`?RX>*@Djm~yLStOH4g_oUw+^-5g({f;<>>{S{f2(qRp
z$*nSXL_lP_B4`nN+ipO3K=y1L)%yz{YL=TG1bEwxNG~=_LtZsJ2ND(|YMJ&P)$)2S
zIq}Oo!hTgvq%YTyi*G9E_cT3SOBJN~t(BOUNTfM_F;!-qjWoZnBmSE?b~Oqn6cgb7
zGcu6ai&QVoARp(AC9i*LPo6sUB~2eMYN3R346(B5y+|kd2we~SOgEx3jttZ{%=lV1
zrq+r=C#IIQTtV{p-w<|MBf2)jq(&|Ce%$c<Z@^QnmStelsFp>KCX=%d6U>%GCZ}eT
zTVfBYaj%BwAjqGncg&!gZEbkw-94z;kDL&xK&EQ6X94Q|#UEHXslF1Hp;ZSL{fXZb
zgN~u1lj7f?baL7j{GMVz<qYUl*GcgIr`?DmsHUx<NAZ_yTL4@5j;5q5?$RAzJKz)K
zcAsXDY+(iuhIJPvKLyD?rU}hAyqRXt;iL~UJ_Wh`Ox7AC2bc`pH`PJLcPfk?V){LY
z)x%8tZ*UWiFem+~|2fJW8Un+9%;8+99%G)(hOft&TpBC<nV|xN0n7{m+=0x3%}9cn
z0W|CdGlgTo7Q%Gv2JREg+@S!RWWM+do`*80pMd%lvx<7{Fy=)ZIK!C%@eoEZZ$3lr
zG}9-E+W!nQ*$Mba#wwyPiurLbxT6`564*V<Xp9h^W9-yJ$1pwJz!uBIQMBhg)AI_<
z$1&3b0FP%roq+HHvx@rH1ZLwwIFraMss~FFvywWZi_GE^(7ePfIt25{OzbJd1XQ;e
zf3ka<Y4I)WW-)zdps}-=jo#qSVXTQj<TCRT&|djW>Qr#wW!7H?{vK0A{aOJtwgZxf
zj7KF5mM}96V0p}xI|1;7iJ`&dDf43wwC^)!@^RoQnF;j}K4)rZCT@ShWYwWgFPUS%
zLR!rfy+`tjIZ_O}ubHFqD0{=~8wz0!^KJqVZ<(K8AXm%$`~@6+&v;eCU>#HX1{JMm
z+~ZO9iFwik<~PX~&@^hZyt4;9be1pvB)~rYeNp>2h`OH}LH+MCHTAj6<!51O#h_6z
z`+E*OvMaCk$Fh*rTYcRg8eflJi3)bE^ToBxzHcD!>e>Rvx>;y^I?9A%rPH9Ul(j)^
z)thPB&F*LcLT*baB>WgP;s!+6atIAtZT-JT`>VGw%V_Pim8nJ_uinY5k3+R~F;y+m
z4LLC*w9t2EzHW_|^Dwhu2H1`;*B?OTEt4`BZhc^$Uj*4Ud0TpFo#f3%z;`eCy$s~`
z%U>Tx?ugv92MrJ|pSJ+GMERv{z@^Ivyv3px<Bv?G(=10p<6g_4)iP!x=)NAh1M<EK
zB{V1ac7uPv)vmzRh4E9vg+NAJ0Nr>da04oNgP9(U9^^IiVgJ8PAWWPFLcOp8HEN%K
z3w=$8EDR6ojs`@Q)Sa9*B7FIELrmG;`72D!)Lk}}px^1*O+Y(!8(##cyB|G-#_iF2
zBK-K~>r3#X=g?5x&0YtRaQ(Ig%}l<FqS?#fq^&3&S>Xf6#xt9sKl91w(D}8|F!21o
zv>i&<O))~giMiv7%I##bSAyGvDXtap{&_QF>D@lY)Toi1VuCr4o@Jg-f!i@mgZHsa
zgZt;12LI!jh6=<p4K=vHkk{%<OhZMI8LCOcT^0(dkGDL{#kEn<Q25fsKNw!O>=Xk}
z+oYf=RA1UVG($sn>^2$KE<d^h+3h7dU)8r;mcp67z34Xff4T%74f%a0eE)t0t&zso
zD?vBmjU$3vbOUWeZi4bNLkIkB-I4nFcH{rTwa1W7Fy8+Ztp>l}L`%;J_vx*3WISmq
zy@^S+dxB^)Gj<lTKFsP`knd+sZij0Jn58tXA7iGj2gh-y=PLmHnT2`qB8({^TsX6|
z8g?U?5)D*hnAFFB$1)#ILi0S+Xb`MkX3GBr;0n_(8k#8#8-l82GkYgOC5P#kMg4Cs
zv!f&MrA&KQAf7Nrs?1Ynq7JGxOu!Z3-!e<vz+f#CyA8ta@`xtT+#&z19tL;H7g-?O
zC%=r136-}z-2-Gk@)p_fK2ZLHAIO5_3s;~lSU!IeaA)N=*Fxo-+;0u7|6}Ao#KT02
z{K9M`sq!85D7-0Gd_r<Z?(jKi?#tzL&kE(vgfEt#k3{2^%7?u{u0noAhvur0UtWp2
zI4bg&gJqi{TmyiMB7GM$T@?c`h^l-P9qxg1zhXx#X!<Lh*VFnZK=EM|5T_OQuENq8
z1^+8ZFDmLr1Aj?z3={W;TijyaP=H$Zc!uoft2?3IZC<ZKRFjGaoyC+!HTa=BYz+yC
z$M50UCAcn3W&V8@8xQ^o^>6ofE=W7L<>C6Zwmq(0?T1@}pvM;!%;+_Up1j_Uiy-M&
z`~>Yiu+eBZJY>T%sE*!%jRw_3k;dg2UbHrw*R2MnOP3DDb@^|vz_4;fKI#ys{$m1a
z6tC7e!RQ6`iqR;#tS(;&-Zb?JCCYBAGq%B2zS`bX0@HO?_cK&qv2FW6XA}Ro3<x*A
zXb@DRw8;qdsp7OFYhl?<|Lb_<JoPQk{rl{PF&`<yaF4l4ZG4~Ug?%nnA#<3<uZPSf
z3+RiP$%pW~l`!TYB%bo1t1#vzj|t__{@(I@nkxCox5XeiAaBD!=b(I0ORyc12fsyf
zSbp&mXpYL)OhL|1KAWbo$K_42OQQ0ZXY7WT(ei@RNY2Wq()#+A{Jtl=xGi_S2A{L#
zCA1LDkzdRK?vDHdE!p$rpD03Qzbo%g0fc+<1bRa6%aeORS}4Dp3)LcdKE<pa%3D#y
zsYIT*7^IKnD=8dUD*vJujy{q19tdHXJZlMX<#OF4usoCdV|PwfDW4MnYDdKjJIXdG
zf(npqQCz16+N$U_1>SGBE6%)tH#-!<5m*XV^rAO8MBz#I>b64Spqi!l$b%+FG3o&f
z<|>Lqp^~TAObf_-#R-Zz+*8b;#dLvUJH0}MiqiRjKTxc>j-*&IZ#EjCL~%L@xyOoY
z9f2!V?2HH5Q-ytWHnL@kMKthMC~nh0^h^;+=BpHOUdTOHB)x~~OGR%hXsQ)szJ}&&
zMNe7@zEN1*k$bBstwGgl6&cMz_FmD1LJ)Nd^L+?EC?0B|`B8C;Mz>AMx93sa&C2%6
zA>5`+v?DgG+OGU600ws|&)z{rcPUeTLoJ+@FHgXri*g8cV7rx%K7ehH@?$=LZps0^
z&~#V&tcQ6|WtbkCUdjReQRc1O*$s)0vdIJh4l0+Ofr_uP6~*NaD+}}B#Sx{N>f)#T
zw$P5kV@fYP%&Gw8u)XjiP}%n!+z(c+q<~?F(tQUICzX@?0}-nH^bK-h%AZ<*EnGRA
zf*_}r%lZL#Mmb>sgi*>}xp)Mkm7zHR#3<u_fitnn`<+1+r(6>Tc)U_<4V46CBLj#2
zFHspz>&J`A8<_j6E-6D(fw-(3$is^(%2b+Vr7FkVhVZI#^JQqJDUVZEm##cXk4J`b
zML($AP*z65V5TysKgw<?m0oZrOPQAim2Bm;EL1R8xuiE(?kE)&0P>Z8dLsUzx~mL3
z3Tc6|z8J}U<>Z~9d7!NSh^iGShtV3cM0xo-XdWrYZb4G2Jlq*7Pn3ywVWLb~*A~KZ
z<>7oJmC8mPV5v%(v>Z+HLb+83mY2#dG~aur{OSX|f33WIA7wSlp?d(Zzg71C18nb<
zUk-uldu8Sgkk%`gEkS#IP#TUw$5HjP3iwSb+fx9ysQ#J;nyspk7I1C5s?B(`<qlPv
z6?S*2cB+AMQpM7u!9{fp+fgc4)tMQvut)XtJy_VQQcMNTT~#{@LJzwt={$7ysWQHY
z32&882@LL6>1n=wKy_d+xP4XMeGb(_syAN1A5mRSMgt#JUFivxV=B`|;Et;{X44a-
z@-e|~ph|rPxe!(62v|Cy@}m`Js7f0M%~Prm3GgsnrNiW36```vr?(?gr7Z_{luALP
z<yjS*1H0!`35BqWJyweBo>%=%i{yCKi`!7SpbA|Be4=W$58z3vOqzV%QKjxfE>BhN
zkK8@gt^vRmsM6lRnL<^sF(`YW`Z*lJhpM50fETOA*$2YXBlN!T`>|@p6X-lqg|>z>
zPgNe*;Hjhf_(dd})E)alxJAt_flpi2>&C;G?dtR20kA_ogGP^C>c(lX<fQf=4Q^NU
zcNF>BtuCb4lbiY*8r9s@S1-emm)e~NV4wPTM|%H!)HCzYQ2W(o7ol@d{ea?gzUscz
zP?_rDzR2BDZ=43rY_*=II63No$tb&{cKHr~JoVw7$lX;BrI7MH^{g(?ysz%i0l7l;
z)jsgINZmt?+(WgFVmc-2ttR;NNbPrm#rs#P4xw<`6ZOpbs9~A9M+96fSAVktz-Q_y
zQ=wX^K7S3CUZ{;KaKBVLM}X$F`mgK2y;0vf1I=1>pGENEo%&rB%IeiEXwLXSU5&7T
z>XSN{;zW+@*w?VIneCa0vMp>*EsOUrjO{_vaCX{jm^jUj9Sjp^*bP2li(-F@MgvE)
zW4{9FId=XX<YL%b4tCG8=hlKIj-As2!V7FEZ7U_P-6o(ciS0mpAs1QeQV5gT?<Pa#
zGCP@q;VJB2`4FbElPFeczs5%R!EPGsMm_3v_6D6?$zYFC{N*NV{eXLz$&R9-<2E~!
z7X4Z5X?hTISUq)xx$GY_`_E%HRv?$pPEexp?y&=F;C%u6iQ@N#Y<LW6|A6f^9j-lO
z6NbWWG5fF*_8!|=*-m6j*_WZ9DPt{J)cEWa+Fz?=)uSP-Vn-T*f63O-jzu-Aq_Oo4
z>qn8G8g|DpsJvrqw*c^-T|-gW53Db}{vY8lyl~{^eh1+uZlVivTR1CDv8c9khLdn+
zJ7?z;knZ4;zXW0z7k?9$oVZ6@K<dJMTn(Trx8)L&J=`v5Xzt|{8-RD`Qo{l8;8d58
zcyR}}z^8rOrC9iMiM!Ds)lTNF3`CN`wfzIaRIZkywP~CWMH16F{t66baHaOwAicqL
z=V36DbC?3@EpF{luw`+%%Ww~}IkgXH?r_bW0nFnr(q_S3?(4Y_-sA4<h515m#Btyr
za9ukfSIq4>1kMspM(_P&?n)`jO1bIV0e{M!#G+bN#_gfWM+Mitl;;1>xb-1$v5G4k
z1H^M~MrY`}<Z{O%speKcM%imltc3e-IG5oN)^b&D)au-*r7&2>1yZcAp37<nvQONZ
z-;g-+k>jAbnYUj>ZVMkukL5N#stmd9{E_QOcJjOZDE_jGAHEXaIP;BO!GsH+_!yq<
z=GVCazlR?+6RK`}&35G6`EPtd<HZMVf^Z+d?h5Ss@L!!mZa+ViRw2H89gW_H_{Ikz
zJj%P$bit25n1$SN{<}@6i$A|J2W|)QoBGoG7sT5sJQ2dTCc7v2-fiJUD1V%0X{Y%0
zB9d@E=m~@od;;~Fk$l%qXwoSD<1}!e<$o(ja*luZEAB`xKkNip^7(MubGgfJz65vy
zzu**-`~1#{u={{t7znZ={w!AHDtieZ)EU4>d{;WBQOalj3E&gn`$v$L@#ASUEa&(2
zhp>`2bcRY5kF^T!4{t(bRaMO=rUL$&A4$6wZ+OfvFdyT4mm{g=U5BG)b-b3$*Yg3>
zVfQ27C<dIL_-`Ws-((krJz(1`EVv2otwOjSh1-Ni)M@V!t|mcer|?q%fKI~F0%$r5
z%U(mpRha1rmEFSEw4JtBculiAH$lG%WgdcJ3~-*p!)d_n69yTf;w{7-0^p3WZ~}yp
z0&@{}D_XG6OhbE}6&xvg5+h7m0xx2PH>==qoN!)&vUp+rEtDk)eiWBZ6b94$^`g+(
z8<s8!XBQ)PS+LMP{S~46Kxn248!7sJRhaY~KBWmSDC&|fC?_FzLzqIVyqiM(FaT}~
z5q2D|QDq7HuR)q4<m#Z4D`-2zQl9Y10rwzZ$e0Ne_XKC!zAF$`KZ42wp>H$fii9+Z
zXcr3`+8`+rFrUU7C(NRmOsNn`L;6#p7wy`X2?Mr+r9v>BgYcQqnu4NL!t}9-KdYV#
zJI8_TrSLWwh1J5u{qXIzaJv$g-UxlhBB>S5?n3fTaO#d`s}uB9Agvb$JU}~t6z)9$
z;FGW#XKhrQL@n)6ZWbq-;r#)zDJ@S9iskeq91=$^h00-ZUK*S^Dt_5pj`z<`l)_>D
zxVV?*nEv8&+Gq+CB^8n&@yL028Y0%WM(%`ol$HshVza&wo)VYcfTeJ;1uf1Z!~$B@
zo)Je0uoNktqeWq~$k6b6Ry^Dqc4Ne}v#4&YIG_NxDNfA2EyMd4FTOYoX`*<b3sjTD
zL$r>&B#x(zjAU`#KIBrwEvL~ksp8*9kh>-(j)%cC@sS*EUl-rZLoP!c?u*<_aV1S!
zGQ~MGs@xV`UVt-8{Fd&0j+nd`@LX}jU6kdCwVRQ%=Zhsx0lX*L7o%kh#OAbAEEEkC
zQhp%TL<0Cwe0?A87mIghgZq&<=Kx%LERMVZl_z2ZJzh`6aW=rq#R3LNg%}ft<bxO*
z46<#~()mc-r6wcMh8|M63w-jF+`ol+FS|6Q80kJqSp%uJ6iNYRAL-9DAofdNm|^gs
z6i*ROUulR5UL2CbsAoGY{Y{JDBhoQ)=BTu?J8*u|yU&q3CjFfNO97J4djJBZ%{1K)
zkphl@?1ZGDPX4;|p2A5PlKnYtBixX#(hG1?vQsykDP8Z1<d)?39?5OVXFZZEX+8n7
zr6~?ba-@-Gk>pAv{z7s`T0ud}BB_E$?xE!K1hs!8H4R1bR4P}&wK8dIDRSkK??xmQ
zQZR*dpGg_^G^CZ%sz21QfqyN^C>YzSaWOEh$K62-e{M*Cq|Kd7RN{*fzrfosC$xdQ
zZ5P_$Z)bG{-&boWyx;zEB6K=zro~mqmxoc?PS>b$zqWph%5~0Qpx-562pGC9xdYB_
z1KLyksk_?%z<T^O5P)yaUqlUh&Z~fdUa=mKeEWO>=)OA<jcf0X6qD-XM>{8d3+UbJ
zA9)?u0TUIF53CD-&Y)Oq3#kT|wTIy$f!=Uy)QA3%PaT8PwW@{td!fGTB5}$SQNP@g
zJnXwNBN`)nfH`Y|-Vx^fcu@K?!+(P?gt5~-3}YtUWC6!NCw9?Zs5!Ims2_D<y|2Tx
zD?5nh6T8`B8vORKqxYa}FMF55C2s5!is8DmCuln2!LIKNp(mR{fd((u{x=TVsrIow
z=?IWF+qnvf5BvTAj2>i1>OtzuPUr&R5%wj`;*PSXDFErm7E>b}W9QL2K7f_~20$Pi
zV25i#?ATK%3uX((qAY}Ur>(0K?4CLB;v{=~9_)s)=Fh-+iXCcKAPr-C(-ufLJBGG}
zBG}lK5T0gNe}w88cH~S5BUwQO6H#orh$Nbw?u^zs%YH#~jdSeY8VF-pI}K2=Z1^K2
z=h>yJ;7lCb(i?8avw|ypy1+iC>0Sc6@g0&xwrMQppQ=mj57bb}><kk;z07hMD7?a+
z8VF$uTR8wGQrUF};LKI_ix;qajoo$>xO6tS7ff7d*U=Vh1}4;K^&9NCj)31}zq<!q
zChMyO%Pn?rAE?}B18zbkhrL3am^$ZT|5tT~9Y=>U^4JpURrA?AiUr<f&7VW{9y^O7
zIt6TB7NqytF=W1wEx&=X2W;vFG-(lA+YQb<WY^-bGv?Llbni>pDG$N&h`qiMWsliz
zv>RW_X0?RfC+u&u3VO=6gIPP~+|CqREoaZslCFYnz6!u+Y;8~IRI>dVAy>tAD~9>!
z>>_U@FWA|aK>Cs`q$qwhyR<L7c*WkZ!qL}k8)x9&u<vQdpoTp~r{dnSty)3lJv*ob
zNgX?cj?jH%J-wl6|HN*fU3EupUc(xndrM>4Hm)6+*ugFGM6#3Hk4GQV^0fKDJ9F8U
zP;uc(j-$+#n?!q>yE#3z>>h4b7IJ&Jz=hy+<AR-#bLYOI(b9vv@DOlM?kGJ$Ufipt
z$a&kjjTDCP;WXsies1g~Sn}iienE1KYw8J4k8^qbfbi#Hv9q8G;F7324CKy9xT8T_
zvl^%bbHnvu3E>t{sPqK)yaR+MxqD&oDU>@wQ=L=X89FBw#%)*$m2fUq0bvAZ-$eoW
z)7$_$f^>$PbsoS-E~O80QQXZXAdTi8(^BIs=Shd2&T$JV!V$x*p_pJScij(;p63#1
zA0UonY332n{n-QX3*0c8876SMgHV>p{YU}EBrZG*xr<zD>W40I3HDNOCv&yiP<WZ!
z-ww{CaHG3}G?jZb0Bl#eia(%ojZ??KZW^bcFnBs=zJs^wI`^>?*fKbKQ<UA{R*;7`
zxy`d7%;a*bpmK}L84gRgv3de^7PqnlD%o6@k>JeXUbd#lXfD^6dWt)oG6URsTu(Y~
zlh3`RxX@j05}o<G$K9L&(gN-g-OBr1DIJ<9<Oco?M;~z4EU0f0_d6|=9&#+5x+vz#
zS_59faTHs7#5G+F&Bt7g1kF;;Hw?KaTy7YH_wOmUv<XzpxaJg_DCZ_d!BPd+rZs4u
zar0>9P|0cN<W&_njav3OXMX|w3+@6<M_zJQ!U3q}CQpa(6<3`M*Isj{=0fugx0rf}
z&HQsZHQ~)~+W^f2eCrxi=^+1GI-NiC<pU^Ye2Cvh{oG-Gju!YM{I3UrKgwqeLYW`G
z=vR1nj90RtInF!Ni0IExpygfwulpHEAphkeBtd-ST)>0*0rWP8@QbN;KfxF7f@>%F
zx5rQx##^X|2<KPNfHU?8e$zH&PxBUf<j?T^Tf=T7Kjt8EQG7j}294(1{{Wh^{Fk(c
zbdK+l3}Fmkl?-7lKbty=^L+bf@Gy@5yc^*0{0W-eT;LxqhEEARPlpr|`3|{&C-FHw
zkzC|&(2W0*o$q%Ns>%G$p-3+CVHe=c6+W8A>J&bq7Tl?P8cpl3@)2hNyv94TXp%HO
zEfS5G&abE5_Bvlfqjv`1E)<$KcpL=4gUJ6$k<?7y?Ic)k@kQU_PTuB~KY==nANCi>
zvU&SA@vxi2yV0I(F25`YxjTFp+TY3Jhct(3K0ktX#_#fNe+A7wUPW=k0{%;P)agDy
zf+||bSJBMl0pBPUnnnEDQOG^yGq=E}NBrjTAbZR&p>Cs;Pof~?6Fz4Ma8LP4dlYEO
z_%~yqQ_hd1=dyx#qgco@KBNe_O1@)Ds8sR&Iso{b|C|oBz2NKX0eA_!s8cmxw;IA%
zyiEavulWSp<$A-{&_uk3Up@}PxBS=5!CA}S>WSPtUeu!v-}9p_wEn2$W%E#2&pY=)
zn|$CWT?76j?}wu~SSR+TsF<Tr{y8)^2@F1q!D{jD3HY={cvKCxt-=f+sB9C`_keV}
zP&6JaJA~oKp}A8SO9z>E368YpbrL+vV8~gBrw77CxVM1f->$+@7Z}_v<i!E8M@TsU
z{9d6o?ZdeVEusK)7v_uwjfc=T3M%`A#`9sxTX0*4G9O_LMS%AUSEG;|5RAj&%t7HM
zarz4R1{gdfG~0vZu<(!uz9Yhwv1q)bLYJ=vynlW|yJg586WaN~#BqVgmn$lNVJxj9
z0)*E6Q0+kBO&{0|5)RS9=U_oI61fmTMdwdX2;FE}e^OZ00d9v1_HU3oCHT=Xj4+{U
zI)veZi4MI*2*%UMofhulcoY`G1rc!69w{85X-<^jS%7S`uxTiAXN3`ifIlbHPyjnd
zsG-GQtZ<_m9-bHOEQT;nxbg!?<AtLE5MB_ro`Ntz2&V%siNeSVlqCr!S_oeh+-HIF
zl5pcY<dTII6f3?gtfp}E6}xcjZ&*qZemn`MQiWc%NUjQ){NYs-)FH^F3EdjQM7q#x
zHB8(PUhYTPO<^nr<1>YxKck&)30itLZwoEHg=UtJXN9F~p)u`?<OrY9`Q%)ouPY4R
z5oFW_=L!Dx0OSjH&jFC$6{>TP+!JmZAT1Eu(Ngff5JRz}LSgku;2#JFU!fL7Liv2C
zJQO;(psZME{0wC!LJhvEQ#}$|uY&NgFg6;RrNY~nV0j{ZI}9pM1@|bZlnDo#qpV!G
zLot*J;k11!*q#X)>rkgk!IO59tArbKk$W!8q~wJ#-~ej)Qg}^gtg407_rSjr%pIZm
zS~yF4<ZlE=4OnV~E8SuKtuUB2j%tM?<o!G0Tk3+}3xCW2piXF(in4lP3<Zlm2nVfp
zxbaa)qB!R#!8#O$j^dYfFtJH=b3#LH7MIhCa*LQw6RNG^@6k}%CRWi<wOw3Cf&Lxh
zJPMlb6u+cnLAyjA+uAA@@yUDuT*cu(BDY&~rQn#Gc!FkE?&4R}-FS#u33UEqpV)*R
zC~xr^MH+m>pXiPr6n~|Y$iAZ17l=cm!=FfwitT=e2|rP>3kHvg^A@6k0z@VQxj^yK
z3*dspAv)MSA^Ow4*GW-*2EtHr4$T8kiPI?X7A6j+kYu>1+e-1b2yt%=yg4n7qFZuC
zygM77MvCA2K{ZO00zeZjo}x2CXT{$s+H+34)fvvjh;M=bh!szVBRMbnTt!)&`1Ca_
z#fw}WT)QB;MkALX`jx`%L@}rgDoJ9|ShVj&aa|***e{6%$55Coj{Y8YFN>=hA$LXm
zawc3%5o<!=MXH$B1ub(`EZ7UgHL;GqCrA_5Q`|0HT+s`p*Tq8W*E7TpIpDq_7SXKk
zrdaS6WSL@%)$lM&97<u`Y;o-nBspTw<)F^Bi($^NbVuCO9W;63yjoN=UlbMre^>lS
z3z~c4-;JPBASTf2=)Tx*J5&nA7WDDS194js>=ucO=y`l7HhTs@u~<ucmL=j73VuEk
zM|K15v1tDmoTZ}25s*C**VBf`Q_<d@j_#F-W9c+#x!A=Mq!r>%0t%mr`G-JSDMp`%
zuu5!n0Kn(swIT>#h@&as_fp(J^Ym(QEsdtH#2gC@z80_1)BQ$#Mx$Ac`1@GE--?}f
zpsZH(Zwn9Ki5FG^@Ls%Zr}<Hx_zUeA*NY3iQ20UYcLw;6;!lmyP@lwgNys@$rztwM
zN&1ZTCpJr59m=*zj`a|3mljpQ#182^-KL$=u%!U(lDgc3qfXMDE}(Xn<_-bQMXDZ-
zO1Mf-Xi2_X@@HxOxkuX86yEHWUQsC2P4Zn0Zg;5%&F(y;_cUMdlzP*t6fbEA#R2w7
zo9Psfx75}LiI4P*KB(9)J^dRj2c-8yAv`GErDNf~Qo?-*4@s}6eGg0f=&?E??eTzx
zqtZyJA^s+n^*|#YllISp&T(m`8+`JY2Ga4J0BPkX2m>YiLYNPd%4w@8SbDV>Nr=>9
z94wuXw#nerN$Jd80750qZSbl|ezc4WlfDXpO1KpLJ%kZbiWV%VrQ5WHaYl+mw{BNO
zO5an2KT7&e3DR@Y*5=5?NQtzA6D$4k3Z&<yQMC0ECw+Q|I>k%2wV=5m`Dep!f+ULo
zTcYGdr^b?`g>=aFqBQy_;FqNKTj52rl)V>am!%I~Vd0AOBmjUE>0?(U_Ef3S*FapA
zE}lo>HK{XAuhOJH+rjU2X$-CEu1hnBJ414x49y#oiFU?sN}04^%#@0D!;4$ePkOj^
zTWYfqNtSfa9sXuZH*p{iv8prlRaUOlJP~DgBsq<LdD6t*u$OO_F06*mUFp_UklvFj
zzeiFiMIVRX52TtRs1`|)bC8rs5x>IxBWcs;D0?h@Lp|G5srM-e%cM5+kwdxk0}XDK
zQjgUzSS7ta58QL9JMEWMOACL1!B>*<G&EmJ?Wi+&BiRR0w^bv3G$Q*}3ONB6-%HKu
zHrGjMGeJ`?`O_Ji57J@<EPa&L&_wK$q*22QM@<{*vo~q(CL*_4GmYNuEt(iQX1Z0=
zp(WtkG-oyeuwB#l70PyKs;Rr$shN#0d{w(N#dcbJJ8Am9N1?N34jnvm(d<u0&Q()E
z0qotHj?IAIqxoe5*!F7NkHb+n&8R$>aMu)5l)*!@8DIRVJT=L*DdnZ%b^^CgGiD`N
zyfr^kP}@h7{SA`+nz%~T{(vR}A6=>rYCKNbq2sGDH$`$t^Cke&!<xje;NlU@0UCLZ
zYL3&o)lU;iOTA;7H2T)#xaJlG%>6a5=)0Ey&ET)W9jIB|2p$G$+-p&#U`;(O=tDGL
z&_T%)n%9B!j%Z%@gG#8T3*CxSnz!9({THVB_ztS!n&0n&^o(Z8Llj1822-aSrD;Ov
zz|LtNzd}W0G~bg?v6_79G|y`~X@HB<^f?dBc+J`ra9_||Zh^7{%}=z4kf;eV1DB-P
zu@;;cH77p;a7k0u7KV~F6$pCSRhKnik-;mPxw}!B6wNhypi(t|e}m+zrd=qKYnou%
z+D_BBQgAw5v*9D^bY1hP2`pu3TG6<9LxUE<TcNQ|0a>QT76!6gnt@-!r`wu8=ulIZ
zW<ozC*_w0VD9h2@bA+ZnSCh8|ckPZQB@i@un&#A&_cXVbfV)7`G6{(Lnh~_aR;XF2
zg7AT6&<to6X@0tlq(rlK4P1MqIn@xz)$B<DS(PSZ4ch6sW-bX|Xs*#P_EK~5E?BBH
z!)VL&l_s%2a<A>0J+z_uMsxis8nH%WZG&38)ztqEFKRW7EdajLs3{EdUbA%#a&?+6
zw8*O0tjFP2)d$Ud`ikPCCb$q~pESE`Vct<29Sp!GEw>q#Hfz0UM}3QS8O2q%YAxvX
zRNJ&`D7La)YacTX=?-lYg^_n^MJ4dNw7uzsijy|(4+vef>9hcI)$Z>O(%o7|Okq`f
zwAl-wvRC^%z3^_@!a*o=*B)4oI(cZ>1#rewJ7FAL^V0g#iHm*Ozvx)2xAt*&*z?i;
zLAzM{wRh~lL3%*D;sFo`wRKHF<Et&EmOZ51PLuz`+E*+{k7&Q04Zn|SUvEKk`)SwE
z0n}sKzVxOa*RE*-fWJ0{W_JNvj?NJUYOf7~+acNk6Tx{xJM9Q^C$(E1z^72{wWd%x
zrJZWE0}-a}O8slN)<7$-2<<7F=A72{KaZ-N(dM*-7m-@^NaUil5e)o})&`Zsi?iBE
zG*dmNy-53^G1`$|AQ!70M;l(}wH+yf5U2f31-tRuAtwO8ptaDLnxM_6P*|eYcNfh+
zleFwFAibzfq%i#@?Ks*aPS$ozLhiD5&T;s3MZ07-@G08iw2VyEYVfVS>Z&${LD@C!
z#~{=&P1}q{mvn7QniXEx=F-@hp>@9s;SKF<FL2(}UNghdOzm3^KHbtPFmbf2Zfkq3
zgQr>A1%n~Y)=qW;K1b{QGfd=a$J0*r9qk*6B;;wI(6NNO+PfR!#XarpD6kc1d(c+m
zeeJ{}z!hq{dPDPpc5Fuoi?r7$B>YgDNheH;wNGdXU!wJ);q#Gp@>}HWkF^!F7=EJd
z-mqJu-Pjn?GHv!?Aj-8_HK3``;=^Xl$FwOFov75BC0MG`4x=O3&$S|bO8Y_^N8#d^
z+VRvf)mryYz`fCy&|qAnji65Ct+u!TWwlzjZE*XYwkw@AcyHIvqC;<W+IgekcfIzD
z?*ROujoJ;;kJ=V<Q2S5X3n54xb&=F;TXav_0=QLIs)A43bkP~GyIprxhGd5>&lxN`
zbzNx(bC)iULf}riyjiG{vu>ycDlWQ7m0)qzwGM>}zCU|h0pHwo6KPTDt_wQ{yoc`a
z3i#xy(>;I*FWs@msP;bH^Gpc6b&Ip0;-f2_2ru^Q!UB;T(EUXn>p`9G2ax&dI#ZD1
zkZzPC3?A0qu7JTKy76>Q<)}{a3+(#owo_Xi(}mb+s(M`48%N<({<;(Nv;^qRQItJU
zxBN@!1nG*702r+6yc298y7PUZc|vFKLUK~qiyA0Y=Qs>@Pw6Usp%SLk@h}*!tF8r0
zgsyxKES%Qu`T$4I=z7y$N~G={edHRY`=yM=zi3^A1nF5_usaavbm8=T#ORvugZWt9
z&YwVfURN^`uEqW1Q-ZF7I+H}5S3S6sbpG_nU(_|7hukIIHJT14>z>e=?#sG!J3xI!
zmplN5QglH!Sh%X&ItOIebko|&@cyOgT&VL**QHj#sq4B2ApmCR){cPcP2J{U$Ytuf
z(2c#NbNB+l+qwuIY+1U`{(_}!-Law2yrY|Y7LMlWLc79?d|iAy2=D6tY7W3X-MdN9
zEYLaN?|7*0>prysyij+tE6qP2=+4nDS&?r0EO`1*w~+SIigjn=fhf^=m4fY&&b1ue
zk9ALnL9<jB=>cb+=-%xC_fy^Pw4+$2dr6zh<+@jN3oCR{m8jA)U0EZ*D|KVtA*|AU
ziCsq3b6p4esOg2SKkZxCU+R9XhEp{<nF3C|)y<*cS*>pEGYH@5p0$O}d)=<)V5`%;
z-iWe#-3U5c^+7j-!apB%Te~CoNjHZ8j(XW)xVA|@lr}sz>ziIi*%tl6Lg2RQJ3fMN
zhkib-Wq0bkCjhX^uD?tZ6es;pG%I!1FRp`&F8akZrEt}Il|#5&ul@<i9{mIwjNSEX
zM!^{m{T2FZ(o<iPgUWd64=Ewsr+26DxVL`6SK#!~zi0!M{rVqVVDNx``2=tt)ZZez
zzIx|!B!~3&sk8xbRNsoWBmDHQI7pA_SDpakxc<mf<oxxs&msxXAJ^j^1nP%TtT9Mm
zMe&SaJ%0=aL-Z%h06(Gswid#Z`p$1ri7@@sJZOgN*W5-fLcee%R8H%sQLycdKHw{8
zM(Wqu88l6lek*OeMC+L!;qX~~!4asQ(+75kPK;g_4ZmacPq(1#yuOi$Bu?L^1l;lZ
zi6h}tqP{K$xg>pNA{zLjKHCxAU($D4id?cjR|WHz^%1|r?iIbUFQ`-WL+ESnRJ{U!
z)&(zs-htLd>H28e3c9ZUn_jgHefA>=Z|FOngz%<*elif5`l%Dp7Ps^#et_NE`UA8g
z&(f<hpqZ`rd<|iae&%tQ$kUIQ0YJXqm<^S?`aZPZc~9T86W|5<Mr&Z<zCL&(oj)wp
zziyaU>32)0Xpw#$Eo~p_JJOC)u^!<uya#&6m7porYw7)cqMv;Q_^0~umjEc!&uxve
za{WD8hgIl*r+w0A`r99XtJE(JMy^WlLdQ3r>wP}Jix>J8Gg0<Z|ErebFV*@l3gP!F
zeZ@j>zt;ai)2p}oL<iKOR?pHp?wx)i9q4(lucULWb^1L@2<!E$uORn9-=Y!he$>yW
zDbOc<uan4aHh9v4WQ)N}#{;$+F0?|~Hp5IBp|=~nJt5p-SVe09`%c5yrzqTI7|{iZ
zlVLnfWt<J%3>3N;`es7tYUo9uKI}Cd>kU#j!yjRA-`&uJCSo3jE&>3ahT&si*UOMO
z34nbDHGNCxZ5SH~6(2)PBH;TCb$`J80mBzG6FO*6-hs+tyJ0td{&vKWNc(t44SOm6
z;%C@L`<=%OGI|7#8z$2hg}*^XE3W{9Grc2$hAwnCA;@5r10HPHQibLUF|-MS!B9iV
zIS5Y~E*3%<X4prAOSqvK^;!`I?gms&8>|Om;f%o^P3PMp4Zk?TsVKv4KUD3UA(rMK
zF$OOR>cko@O#sb#L%$;6;|yJ|Ll|$U%SP^k;mmVzCm6cZj5E<NAPw9}hSl?tTr@~(
zs9ZASQ>$Mwn1+KT#qjxcB&mi`w5YpksI_;5!E1&`8<C_L%66eJ-LQ~02d^8f&EZ;x
z;TY}J-7uVJhC1CeWb}kE)8IgVSs=?Wg}#r^Hk_ml{~W`_GBio9VRtL!?idQcgco^+
zJ`_*SH#jeW!MlcVXOP`9tfNzq1%~cpY5sZNFvS%#g@y<^mH*I?sDm@bhJ&=nS7H!o
z9rnoJ-~r%cLz|mON)1yC06Z~trLO;}VdP$Lml=B0L-@>4KL$-wY1mJzswzWonxs89
zT>J_uFAOs_BlprU0bd@fstp>g0`K1|!)sR{UK<_<0rAH0hPJ$G44HIv@2$a~YWUvp
zo{mA)8BQ-i%hVetY(sN@Fa+SQnyEe-+S2UqlVKh0fH@kCGyrWfauo60Z0t|>b&K)C
zcvNYtv6+OjZN>#OciCke_7koDoQ&xd&u}(|QFPzM_&gVOU5%0TsQqrEj4JA8{A?EN
zx*HQHy5V75-ySNS#)tIfh?j8_^=$i$`+_0#Hun1lWIo1<`Ow^NOzZ&o0b>O%3J)6p
z%mk;eu`U<MA!GVf*s~utexTmqi1AAoWRDu#oC1xXab*!mj~Q*FL37-AT#0t}H@3Tl
zT!1l##*;u}Ijw+#jH40&2sZvjXOu#WU9SOm!Z<nuWhaf<v<(qz9BP2@l+kk}aAC$r
zw1y5hI?<Wr2)ps^Q22J*7)HVNGsbhtNFt4IX8|8&yh0x*MH{2Fz@Ig49|*)bV@xsX
z6l0W8lpxml-9ET|-l(BvQJk^g5+w1)Uuem6!I(^ItpsD2uRxY)<Y;l0WZXkL92bpO
zeuAM(M!RVMbdrtV)0W$1V;%JkSB&Gd5T+PQegt=_(TmQ4T{Ui50q$$Y56yv3GnTCd
zAl<k#1!dQbsk!hl!{~Jk^}S(C8wHk|#ygu}BGZ@}48Sd8+lBy@@m3qKWElrcL|L}+
zOM5NS9OH+(u#{_Tbr8Ti#sC|HdB$H31DJ0#(BO90c%3?-d&Zw>tGvMIOn-jhzHtf-
z+l9s##PYzn{Sb0R#)4aL=ArSo;ZP|yS_*(GG1d)-$|K{u=iq#7>`%jQsd3UFI<WJ^
z*q=_Glp9S`p;}>d?~ImxW=y4R_)24s#Yn1*g`c79xiPFik{8BzF{t)S<2(vNRU3Ue
zp-!)ihm0V5ZESJ`Cf*o>F2G=ov51=ct#J;WNv<`vr-S70jJ;+8_ugo9r}Mvc#t+}a
zV7;-YKXg7A%hrMWqj9MWc0U<^eunxwnu;{Id7Dh@C|b7J6hL1#Y%zHYDBEgUvI)3t
zrZ%)}-ER8GplpX}GDR16nr7bz%Px~dJ(H6usQ_?iQ`f=p!o`%?j=ukMH8rEN7rRYy
zD}mo*YV``Ldre<atGk&3d%{z9Qx^T{3=fmK3xuAgPBcyNG9A7MOZ!ZRiPYOPmb!Nz
zQ#M80_M2R2QFp*(rlaQvP48)p@--z>2Xn}j{1;RXn_AKA%znfqyhD1_^c!_Fex@T|
z198kW%N@Dnrgl_cf71^%%L*_>Ekip8n$8|YF32=`1aiTq+~$CXnBw~&Ibkx=r*$Vy
znVB#VYWn3Ia;HqOJ>XiH$!ROd!c9>hP!?h8P3?QyZqiSJr)NyHwD}ro3SWh`h%#l;
zU-^kPZKucbtf}`+;Ln-9IS3OmriB!wh&5>sq3pbA(sRJ$OpE9YXuK(10?P%{D+AyO
zCjAE_iKhE^flD%dq(?T{RR0LcWz$0!xOT;4UrGncQ%s)~0GMiOItad9HC2vA?wTo_
zPOhYxVgzufn}*Qe%(-s*jAE-9CXc_seZ%yqIlQ=O@=Hc8)6_2?@LQ(S^nt@|Q#CE6
zvrNM%+?8#z(9@M;noHsQTvHr<nSRIA%RU}Dc_y(Nbn;E}X@+pubn^pp_e|sR;YEST
zl?KlHrU)8$3r&%g@b`hqc?@zzrhaQ+@S*ATkH{695@-ogVoJ0D{>bz-#Yi5TRMTOp
z)YN4vsGpdU+JN(^X%?MkDKiz_vV*PMG~s&yD@@1fRN6Ds9Xbk8X-e9UT$O3yOQ=3K
zRY$;!7bdr_!Tr)S$B0I#HkHvgF0V{S>Eo2wrh3|Ud}HbnfTYHBKN7;XCKvinuhum3
zb0qIfJdL~WO|D-+rOq@|Pw|&}Q$P^h|6qDL3_2f8EB#>ilS!bUxubc<EtuG3ex!mI
zo6YI*0B$k6(K)cK<|sNzzRmn_DO9$bGhCpu!@QanZadB1G{fFyZru$mPUh^MP;oZf
z?!df@xpyb9xSA7B)BgKz^NgdQ*<+saJ(9iV&uJd$W-g-*Wq0$&F;Mj|Pul=CPjh}9
z%Dl|%VkG;_o)ghd-ewiew|&g3mqK&D`R`q5N?&uI+wky^c|dcN9X59rQFg=}M<*wb
zn)}h`zkcSsArRV+nI~3*`?&cfeP-=%p0FNX1eha5a0i-ukAW9KW=D!Z1e<?u2D>5V
zZEFBLVeU#3gp=lBv@;WG9!M+AQ|8?iXbLlXT|h3}Y<>il2y+FE$*0Y&soH1E$%|ki
z(p*RZ-YB~{g^mbBn`hCU*I9Gp2sm@jJe4*VV$7aSNMg;Y9ie*OoJe~FapqqsIv;O7
z$sxI5{!@b_!5mY7B+(p2o7_p}V2aRQG)pohm&|`Vz(TTFvkhdI%_r%g@fGtN>Y!50
z_K98LTdH|jW2jy=KR<>Wbj>`7Lg;Dc)fA6NH_!4#ovxdMzJvJ;a{}$w-Z1|<7c@7`
zWlKPlX)X>!a?AXDG8*`{`B&Nq%QD~1hGw=|Ps@`W^GoWPa?K~Mq3n)1y#%>D^A}iu
z;l(rGr{(%xbL31obI<Jg2EqdK4l7jeo14ahyU-kV7_L1qcchtpk@>Iz<{z3HJw;iu
z`AiCu5_A6`IQqz3M6syH<_D9ZS!&)$$5@`2*CpZJJvG;7g0swAOMC0(=JORa{#BUm
zZ=m|j{E7ZbQ>FQ4M<A-qBc4I^xq0nEsJt+DtpxW=bC?!1)#fI@L9@o3(-UQH&D#e6
zUTd~{BKOYxCI)5i%@*1stTXqaj|S__L+M1{2lJ(N$bB?_K_|ICnFn>D_s`K%LWk)#
zSz>>K-<vJ&Gzs5g+3tqiR*QZWT5p?WGsR}MTV}fezr#}h0?zEToE?j5@3O3-(-uw^
zuT=Q!Y^hB_nTus17LF=cOB($xq1~1Xg~;u(^r0gZdo9z+88^#m?Aq8>?iM~6q#l-E
zD3s=Dxs5;nsPeM-WW)SEOZyW@ye($h*7mX3r^3>H%brQlJYZq=Aa~F*iJop>i>e76
zJ!H8^quOE1#<Ng4Vo}~hMUPtCoKWUxIqVOzW0p_!jvTiHQ^?)!Z|O#TcYtLroskK&
zEVu#HAPc^p#2aVHtpH7krLqYuov{2#L(WOdRN5p9wG5pCnp2i4niYmwx;{Y?ZaG7D
zGQ#5C3CU?o>m6|BjKxU>yOEa2A0dpg3{^lg+OnHMG-vG=HO(c?S@vB9Ta2Z97wE)V
zcF?)T^A^iY_!MU`(10CpY4$A;7c5arfKRa0QiM0rvf%;%NtVKPaP6WcWEILTSx$rj
zkZk#RH*%LP&#Yj%V)3TvdWwaoHcYj&`UxsmEp{&oj9;^)1>hc}S>DlRSGpycc0aFM
zMjr+u!!m}#>o+WyXjygBqMZbTnHD)sHE&rq4}$Qvr7{*OS(YyJ4MVo&@+mZ4j-{&t
zWqFp%9<Y>e8I*!XxNG4xfZwxB%STy(<$-+{%-^@f&V;nk(t#Eh4=mT|xhk^!MoYGb
zmKSu4t=JO$CwwZg)KE<5ktLK)XFay4dcabtrE7oSo>+R&qxaO(@-Dc`EIHqytlaVw
zef?8m>EsNRXO`M%;3_R0r-H1?l9NvF-*ZcE`ZFmnEFFS@cxh=(jZkf=r89u9EYS?u
zUR(P80Gc<JVmh8tW4RCo{98-6WAL!n@`m;S-dU7WLH6F#g~p*eONKApuD9Im58($(
z;{(8bv{<PUpDc4}3E^m6)tJuzZ?d`$M140~$E=3IE!MBBFu2vKrbxgxYfuvGZnrMv
zU}=Z-p%b`wT01`l_bzLo02(K2H`?cMw!Wba4;SkyT6Mcxr>uhJZfn~D*xh5@ZimWV
z>o4z-xLKtuAal3&#W-SDd03aPgN~<l4Fw{+tVQ17-e;Zk5ZvC@oH&^GvGT#l?YF+)
zfXW=Oj(rG~gVs=YSn{>D?+QzYtlq6adf1w@3nq?O7t|nk)arK@a6hY=)^EqGts265
z)`#^_@we`3idx$PtWpiqKx^x-VIs(S{}V`qtt)ApH^e%Ox}+1<y^W!A(%NMha-r64
zEm6@^)<v{C7G@pw0c_#cin#zpSc_?Wf7*KK0#wde1L(V(NNe~>2&1e+T0%40x`ATe
zXRW>7K;@j>8cwn3^VaWZlOWEzf#UJ;){XfnykNaST~dNIM2jTRI)v_8l2xJ!`bDcU
z8ObH9rYXEgwwgvGxooYq!HX-_{BD4!SZ7h7DAgLD1Kd^X*>ZS)&APM&a%tAWEohl^
ztNk4X-L6~jPeC@rI-kze-LN)^gX&GI?kL(K)7oqqT)SmmzYb-$t&8aFZ<e)5W0=pj
zE?SGS9P5^0NOG;CZv%J7x}+3jdDaN}_9@>QwjY4I)=snzyJwAXL0N%y^aZ$f-}=Vx
z1rvqVfvo_1VBMVtnj&k?Y_!)y>kRr-qS)#@7j{dm*ge6EXZ?v*laH<RC!$rQ)-|-~
ze`0M*tI4O<jOhTBSzTU$v)n4sVzR<oL7}^6)?5KerS*LT09Dq%DQf)O+I2CVKYL*<
zdkw@(>#{N+s;!?jMhm^N_NCS2YpX3Aq;IV6uE4_@YumP{#apX}29jFqgKlu<opo9|
z%)htl=}(r_S-WJxM7{Mn?cIK`?s@>0kJjpaQ2AtiMZr`@o8xMfZL;y-)AtXXZK34w
z7TYi@NVnQr=ux=M=0X#U?Y6YZK<u!^CBV{7TVO8C@3M86gPfCXX(ar0wpr*vhKtQ*
z7I3aM)p8`eZ8@|a+G8uG@ataN<^oW=*{;{4%-vRY5oI2>0a%mTRi3s%G*WxndKE*u
z&lda=Id9v$_AudNn@HzB_uK3g{_(XfKZ;r$vfVTxci6VIGXO_y@+vrb)TW3Bx1TMZ
z0tv@#)99GRaogZuVAtPPP3I^BY=ek1(DvLPEJ3yfYT)d_w!NFs+#xmtEeTH8WP0FF
z+Lq?QM5t{jkJdY7yT1ZSm`(o~%EE0^Z-OSmR%r&!Y1>%({_KoxId!v<wkS{d8)d8B
zi6q+AJOO~Swsm=cpR>(Z!%&PZgw`yvwuF&L&f9JCXe}ORTQwBs<86c7pmV|Y3vJsZ
z*v80_OSHZJ2$dw;@Wn_j+H%Li(j{AHD7;9vHQoT+W!sg@V7p?|{fKI(*q-!(-Beru
zGbp=i^Ke7%nyv76sHEBaC`g}f+e7DVuG{PbLLkks4Lu4MZ`d?Dz<txU5s@)frfoWH
z2;Z_r(1+%?ZE0K4URky=Eny<t7D5|_Ikq=90m!wzrnveY+a52d<k==)fWds*FDfK=
zZTT<Y#XZ~0*|1Px>yZY)eVgVq;Dxq1_5hfFV4F1<*&>^kmc0*cTm{&QZNDVIQi<){
zX&@fizNc>Mv8_)A%1Uh>bCEo;RTJA&oBwE-D6?6$Fi~y`e-2!QZ9*70pV>T;fvdFb
z=?p_vwvNFldv1%`irfoZWC^YRUfL?@1**0!q`#){%9cSh``5OQ6s&(^d!j^AV`CIB
z@zz!|7#`Nz9!`bbcea^>0eEj4+#P^A+hHC)eY8E8gWM-uuSGE7=n(xGENpTJj0AkM
zLk~Iyx5c6A6YOnuz_)IA|F$`NL*cUR4hl6$cR0wF0kPBJd)j8&<*;B85KazJX;5)?
znEna|T^#llgWJ`?+W{)O9ga|BYL7!SZ5{7*m_i3X-5gTJ!3%eXk9|;I4+l#a-1c<%
z{2+2(4zaYr-RE$Oqx}bOhmz?q=;LsZW)J%vdeCI}fWw34sP;jJ4~;<T>)<AV^pL|;
zI?Z<Y|2VqtxGbwLt|?iWm6iJLz4szbZCI(9nx<)KR$7_uY^PQ)i0lor#KGR6GGr=K
z0Rcrorc4o0h9DpUg1_(i{dGR)-gCa^+{^pi=iYP9ePFcHVdWG<(GJNl#w%-}7tR<c
z14;x#(g#bC3=vg+MKOGS28m`IltUzjv4aW)Vi~IpAaRVk_n>Z#XVkq6jRb}-{X7#H
z8MJIAF&554XEI~rGDr&JB1ObbGw`KxJa~+t1CTt+sQ(RmsSFkss-`hEJ7S*F8MOv@
zk-@M%g1&Q%Ewl(_GUn1NE{k#E0Kl>thaN*chq2)uaJg2-#bcm(4Bz!2=NU6}V!XgO
zK}U&vMkvJ$3m9+Fr$!1H$C6;Fh*4J!4~rS&bOb43c+<A~BI8*PjPMepl#Y+3jP>(@
zQpSkT0HvIvZG`#Dj36&GRxp0+f}u*r&Io{2F|6FhK)b^Df_73@8LKF+SIy}00e6kD
z@G11wFkYI*eAP1MP+YE#(HafK>x>*9SgL1ib^>W&EZqds$S9%BY!gF8@2F;mF%T#%
zj3sm>>jtAe8epxAo)6(u2O}a0UUV{kvdS@vF2-xIAU7Fa6bkER?CXT$Eykl8nDrjU
z7qoiaX8b`lguRUM7WCa=80NyKyNqu;!1XakzJyQxjHmX48({eO!Tca&?JH2f#|Y_!
z-62Nr4u}jhUZ*>q_Zf9x0ds`WI!*b%QO0-qn7uK^Bt>i<FzzLSj5FrG1ZN&HzN4G5
z6O5BxAd?IkMYg6GS#+d+#K`ssnP!xEz~Br+L0`~#%+S({+K#zuKQQf?Jrwmi%q*v=
zbYT8RM}Z?uyJ_e-GB1zN`_G9fslw2lnazRl&4u~Hx9D_b`cmD18?%m{9Cv05?GZhg
zA(UkEWd2D%L@(yHKLP5^^jiSVhq?VP5MSmodhY$0uTfOQpV{#wz>YHa{s-s)X4Ot`
zfy_A+h!0}^e0vt2zhGuI7k-B@-T#2bG3MNEfQB-up3LSrbK)TEo?!k*XQq?PsB~bT
zV)|1RKp3-c5?nYlc0c+em>$2td?a)AO_+#c&ZoF(G&AB9Fk_hMc9@G;W>O`<;+U&x
z)rx0+`74Muftf%heTmGVpCOvW{BIwylbLT*xH^SdMzvF?nXi8g_s=kM5&(LZ*}Mmh
zsm#U+fTl4&-3x!yneTaF4l|g0+W~rxd4W>&nanB5@ntcOR)foCrgx$*hgo<LB$qjL
z4~=<Nrs_A?J<p8G0q6zhA5>A8&s?a2PesgUInXa=Zn_M=OPEfZAaarUK_x^kF=OcT
zTgnWiJa`$?i=O*(<{K2vyv$6v49N=S78iI}$vk=sQ(46<-U#jrb5T1Kt};^?@VA<2
zZ5N^S8Z(wMq&3X3O4zMsZhsb}j`;>X;@6oiPVlgv+3X6D2Ik*Iz;0x^tcP9`b1B6I
znwjMtP-tPU_JqGTm~&~pXl06ML(|55pU!CQ%$3=Y>|pLq1z0CDbtgvO#cZ`wV(KPy
zfa>PDnFX}Lzr_roBUcY|E#>`hGb=ZP^fG5C_I-!B;yV1k%WS8Ra3Ay69*}<K(j_1R
z%#0$43^E6u!QEs2N>{mtm_Ox%3^RA`fT8=$ljCq^ggHfT(NU(`B<26cn7L-K51606
ziq3K7;wm`vkhzoeCzyY#VQ`X}b_$YH%vSo4z$4}%Ek-fToVEow!*pE;gO8aBbOx|v
zjnO?5d)7m$qB+dU-izsWU^&ta-y^Indcixgo?Z>&#QJT3zQ69wvZdXF3yXUP?z^(i
z(MR&#SWi*8ggZ-@3s4W%&tIa?la(I{gI=ryH9+%brPG_khqY)q9Q9>&uLS4E3f&D6
ze^%f>;EuAkP$^OXEA0i4K$dGBCLxFwMDdqk)|$g}@%)9b-lTWUG1hl0p%}{Y{{h@_
z7K66!Cs;4g!Tcm^8&VZEr&tG0f(v7n)4L*^^(+O0qF6U+&5mYWAcYv#NI1Ay);mFP
zJB~F-nfiFv5F5@Uu(Y&KNMxNqkG>?9mTCa4$t)3V08?18USLnNCjW)Z8P-pqU=q)=
zMkvLf%5s6HHfgN&l#5Act)MhS2J7n{z?@?}@huuNSr!$X$zrW(1IcDRPq~;JR&gW1
za#?m%5tzqXN4c2utiqR}cY$^6U66b$t6mBh3s`lHn3F=*nhO|c5i6G_v6!`d23!g2
z6*_faWUY6H<R#WLy(>yte{P0}GS<!#aOJFTLxFvn6+@qds9<%{s#VF-(nDFr%BjEr
zudtTKL*Xh*M8VW*Rug?c>l(|-qr%=ARxqWvYFVC(VWN(8hcXV=S#o*|>sf2+pxD6r
zgkGGDtp5LJ<yf;QB;3rpyd0#3wGc-Mn;R@$Ge|2dmiDb}ted{*YiGSk;jRu=C1ol)
zSs8RstBa)`gV~#`AFTtR-K_9nSh~epOLzKvSZTLFZnKussiBv3Bpmv8Sl>}0)?Jp1
z9Mj#$3Z@HM{Vc3+c<@+X(aCy{HJ47^_gEV&;D%UpX%NG#$baF}eb%pZU>sqEE&<pm
z>%10ZjCJZcdj1};b_W7<oVA-ODju??H-VdA89f0r$<lbj?<p4RU;Mcqu@*W(WSW&j
zdEpsWtUb&>W;Hv2*s)V-g6-MW`7n5xeKP|l9M~Z{;gb`)fufnt>^JEE=E9y!n+I3+
zwl;eH+}Ml%2AVrtPw^KI_6x5=(Ubj{j-Oua4hltkv)^6;5g)dC0sQr4-=;&QA3KZA
z+5T)LJ@-f12SVU>0DBGPL;~5b(x+U4*e}yhHkkb}orgl$z4Y83V@vUhwh3kL-bD3h
z$Jrkpgv<$cNG`}p_Ir^qaf<zX8Z^S#-@guxaCSdkwuxXj?}Ueu?2Gg@peXkDR0$Q$
zE}Mix412m4Tr7KIJ{02E+h{Ky&#sP!GYRZWI@=|(|N90ci5>PW+)ifeY0|AJ?9qRr
zc$)nU6B=jOzZPIHXW5JP!$d0kA3AlXvHA3)NoSwD4ap3)BSkgOu|J}SWhVP+3OQ!6
zpIHWxZ1&sqBh6tC--2W=+wuUG^4PP+(0HD$=mOXUb`bqx^4af%!O;RMyJr$?A$#iw
zuv^4lOv_y{dmUx&O4y-v>b}VKn+3E>YzN8+m9iW50j7-IM|EW7?4z$i<TCp+s?w-n
z8|e|RWPkN5P^#F!P`Sbtb_k_SuCg24V6d9Kk`A%g*lp_|Qp2|TQSzvky@yIg>)0{$
zfsO0z9iITEp8X+(yBgSWE6~@-K13;lCid$_jJ}y|+yjvo_EU0jH`wRLV5yb;u^QuT
zV-M2B*>?6bbXw?Oo9N3SooxE5yiFI|g(~T9vYl50ted^VItrLu?0uzB>}9X~2(5S6
zPdb3yWpBKX#y<8e+BWpF|DucU1MH8tpl^`fNWrsv?1yw@8e$*Yh6x&GfAST$`|P?i
zP#9tVTL+O*_RKbTIL2=2gZT$+H@d$!&R$5rwTJAL!E~scU~gQ7&PnzT3gb+%r#C?6
z5qsbj=uflf(D`77EoESyAG4ox1ezVE={ATx=Yx9qbeJ<prws>A=38*>2q*4oU^{XK
zXQ1H3aeESt&YZy=5OLx7mV&r)o_QDc+&DWn(EVF?&W}#;+k+GEHqbmdleN(B;;f=m
zw>Re~En7YuGbLJlIe&D(H9wA94jTPA`)Yu8l(U!%X976xw0#Zayi1YrAWj4A(}OuC
zTD3wrPf=3v80RmFc7<|Uo#EPXj`KE(zntKdeFp54oMq`4{V9%^4u@eJ-=`rH&T)E-
zz6eei#W*85KgEJXah_1X-)PPoAA*bFG(HRLSk4Q6FdxTR_Br(8IhTvzMFPk73d|>R
zw$ocQiSsg@x|2B<=-Eu+L{nX&^)#pKRXBBqlSS#gvm94iQ&Kr*I(4UUHcWt|a~vt+
zlELW;hNW{H&5N*<$yr|o$t=#lo1mA?nYad&9L_rWbV)Afhea4m9_KmA*q!HmK}p*S
zoJNe-CZChL3Vj6}x7XlBp_Q}sd9)UBo~NqnVovBTw3cxC`S9%`Ctwt4mpCo7S1je6
zX-DH_PD(2pD>(1dy`@S{pdT8mIG+k({t9QsVW?l_gj9m7<~&K&FxNPTXn#_}@e6=n
zEk{%cg*wiK9(Zw`V=boVx1RI6KTI@mzNCk`kz?DAF*R}8X;<0INj{Ih7S7M%(73^Q
zk`B79oNH8#*2a;32ovp`brfFj;7I7xe4U(MxEN9w$2bkJo1DL>e65=^Nt^#$oIR`2
z*Tebw2RL(^bI&RVb}#1#+D_i#B(8yPcR4LoHrvMuc@7%=oDl{Z2RLW`2FxJm<=4@7
zk8_3&_CuUTx=S+5u|5HEpR+dtC?lMIXpcC`+4myMk8wml!NLR1KEzLL#yJlu@$itd
zbw0o*IG^9NLS~XvL_6#$j{76PJmUOj#;~V38{dN68P3<&K^}7s+oI8qyTS<y_S|hz
zP&mx>oq&f9-1jI<eT2*Rfn7)L*B2q;#B~aQf-`pwrL|nRl@tSW<(}CB;>Jxrhemg9
z=~Gny;=x^F57v`AC_|?gSGN!by}2<3AU<3-%A5Fdhv^UN$NioB_2=rogx#ZDdl@D_
zfP3&1%m;G+&4+prH?{>_F!%axI1|EM+lT2o#=T6NmQd~`4@|;wuKOc!C%8E%C9>L_
z<SJ-UIK@4^1tg67;{-Iqx&J%?OA*}a1elNH&YXsaQQSGtV1lB#OQX;i!?mH)WGr{L
z5G0QKHf^orxePA)lDPF$v69R^OX;Z;ZV`oVPIJ%S1v$gDn}fcy+-nt(w5D=bQAtr6
zmr0e3>D*7AfNvSxZrXgD<5tq^ER%bEBSf;eT1s+fa}D(Gb#l08_d+C>+bYJG^0@aY
z?0cTOa0yT@a0_X-lFzOB3VH?H-)Rd|$lcum=pydg&G5IFd(#VCiIpp8M(0KDg<W7T
zaety5eJR&%0X!|^`m_VIoI6MdgUj4sdLUWBb@&}7D!B%#uc+c4%7>*ZT))czy~_3e
z8hX{-cnX+a<0ftbso`oG&{)fzM<oSy+*vPyT<1;{L$97|mC|daftyX=yKUrV(E+ZB
zJ4i43W^NS44qCXYUITZ7>uy0`EB9wAmTKcV-T`Unj%)+z;1=5et&^Kbsq!xF;|1{W
zCRcg@3f)|r-7t8I`}#)s+rw4HV-UBwY#ZqHa@SgE6LN?9JB45Ga)-~sQXe<86{7vz
z7<cFoaHr@o9^@MJ;O=p2DY-Yq{ml$+m>ZLXVc+L&T?d5`?)#MD80EI^g2)(mN&x5w
z+yNh08t10d68ezKp-X`iTs>V@o8(UYNqMm;ZpBTokGL;T5$!bhR3Sz&!`0Haa2|6%
zq!fo8uZqfT?RlA0nRl2MPZ#|icx!?oa)ejv49=0~!^N<jcz@HH@63ze2;#!~o>og&
z-kasH;KmD!hPpfNK3#e9;z@5&{iioCnXYO3@T?R=^W{m^Q1s*3(B8?PS41(iqr4T)
z&<NleZi58!e%cF|AYLpTxq^9hdoaQfo`(`+ImTN?2e44yvV8zM&ik4Y?<aVh=`+_S
zc~4Vp^b}7K1E0cpFW@JK?@#b%e*(n_-T{iCMe=g8pcut_Yb`XQc@q@8j^XW{2WMh=
z_(ne-HJ+A&*YUg$Hv%nz_gpndBJU5%10?Z^Jb{wTJKhi1Qh2IG@b@%t0~NEK;jN<&
zDW2s8<^eO6r>4iyn#PNXfqpvgzBjNlct6szb&faqKFnwGI7WbG@s{6!NH%Yn%4TzT
zRkwhh%WG*tV;=8%5KNrs{YIg`3p~pPSjy-9H~{qmUhf7p7V>7%M<t7R;~gNyym*R{
zl<@LoFm%z%TSak&OT64{%yTJk8<qBy@&2L(xtteq1TJ3YJxlwA3SRW@;3|37DVSTu
z(=SHj6`qVTZ&!J(&Csjng%Ed*=NJO@8s2@n=~T=6m?AZGyqftCxz5XRfk-{?jsWHx
zc-BYTAk)aRp#WDCZ`o~(x0zQ#SM*zWb^k&12Cst(6<T?Hlnrd-jqC!~&Xcdhuse8j
zA40v8_r40Qb@A%x41JR~(+2f!UeGF-xW(I$0+Ak`hXv5LdC$3EW_o#h$=)5FoAqhP
z+~xVvjhH^(o?U3|=ao=KXn^O^0>6iN%}Hn+=HY)J;8Ejkq?sMz4Nd`Vl;=nBmoZ*O
z1k@k!(x{kioaaOJXAgNxDPTImdp;OslDCDnwo|-|AHd!tUPcedG;i&1R)Eg%PEZxk
zW1hz<$k_3BQ0UK|Kkza}ahU%Xm83iH7u5ph2><moC_3_6=Rm=U|9&|XocX{03A--*
zU<ypT@@?tQ?8ZMY2Z}p?<suLd{v@S)Jo%64wC%;eMS*y4{yuNIf9u14k3w+1d}SSo
zA78r!mi+k>uLJEUzkxgq;OEmq6Ug_ghovC?A<F0m^PBbP3*q0Utimz=ha=Dn<;T*q
zeVl)YhIE4eA`j#w-<7u1r}(MQpf8L+`5L%z{xfUn|IbA5A5)qtlK(4Ja7FR=QMp7k
zpGhzJ82%fyY{l~5rG$SRKa|E4&(EuXqY3<Ss_aYTr)9#YB)$`+0h9TWYH%t1r|AcA
zn!krq4QKd8c2GFWKW_v|Dt{l9)}-<G(@hv_I$!xbT+HAfqxZr&e$ol(XYz#<gU;gr
z{yx0O=AY8RiyVFx<tB3ZFaHTkdHfbiZ=L5y@gQ=6pGMK6e10R&v^E8N6YWL|`ETxq
zr6T^4i%>7-ul@?-EaAHy2lPe$Q=t&KWaYo`HabiBncG3i_~jp=wVYp1m57)5x_5zH
z!EbItUnPHb61Xb<<bIgA!tc`o<|^NR14s>DeE@FP@^{RG!8*Q?t`A=4zZ?y{dj4uU
z(l+pU-=eRP-^7Jv6W@UY(#*HI(^;*BA4*kLH~4$0e7u!ka|f2%`2SGcwVl763a>l(
z@4N~3JNdyHV0ZDq)j<CyKWzp2y7|xi0li!N3Az*2!<S}4?>2uIrP_P>A5hHw4u2)>
zlJ4@~48b(_@l);4*Uw*KrJe2o|D_I~4f3mw1N$ET11mI!_zUQJ48#0+g%G*VZ{CT%
z5xyr~ydCAY(C=c5{~3AzfM56_(8l>D+HO4LpQ8fG3I58181E$C_gz3w@uw(?`iNhz
zfWkE2ObMkKe&wVU^f5p02cX#rmQxVRUhq;X$YH_MM?iBB3{f)kh+y9D;2Z_IFW`lf
zK(-JH&Vu_&^tlK;{(y(Bg1{tzxd|Tj!;-sTRUZ001Ow;6c?vp&Q1BAiCBwY8Af8U!
zK7v=A>G|^&%-)AiKY^$W8vcTy0&qtKJ%3^n0t9=P!kIw9xAZCcAb|rt+rff=SD-IM
zAa?`IF@czB;z9+>x1#U3pmH;~6M_qeVd<ox=@Uqv5@gYFIZWWz1uk45ISa4|!D@t}
ztu~PYh6x6v1b^RvOthe49|jX6SbG!Lv4Xw-52pwe^i;(Qtn`VB1VMZhuoDGG=?Ib}
zaNZ8IWPukwuqlGPH!)AA1^uspoDnRbgX&p95`~@81&KLO&k&?iZP_`&R=VzQ%@ll0
zOK_He^%Xj^1)lW8<p`Ej2rgF;gkz{pp5TX9LCy<ay$f;yA{a%!;6xhC7YGU>p-?EO
zr3i14VEI{$rC7kGtZRuNltKU(1!D`~#U(*69W+Y?4=IdNCg3avDYpue?a_HzFh!}A
z3c->Cz^)X8(&@QMV7m)_R|NC^hHF;^GeU6Hf*v}4UK8l(Xj&uKKxIm`f>~k=rcR)w
zxXpEe!%~>97Yxu(zCn=sD@NZa__Ym~O@i(8Zfq6|Q*5S1V6~&i>4xCRGa#)3J#D7j
z1nhS((00L_0YK{zv~2^|DTsA}r7nSx3T$r*K4!wFZULtp<d)#gcc9lJSV-s2+kytl
z!}SWj<iPG7f#)zp?h2Ms*r`vj>?!p13;1;G91#3ueH&<lf~YBwdxG&cSQ-*cy#X>T
zFpL27zJR#~4vz?8C<Z+$cv}I*F~N3Hcpx~LguZb>S3E2|6pUm7dqR-^9mu5M%@ZI~
z0#}NUJrc}b2J_Q`XlFpr2zD>Wa32f4t+E2fPG}PVP<!D=*MN3d_$zI~9fWTzg5nY3
zG76(Q3jaC>;v`hRfWbHm8%sf4gyqASAXj1JI6&QmwN`NM!b&6bJcRW&Fz6|CT?;TT
zp?)u%@fKE6-or;YdK@CY!uvl`{KZdrv<6=I3qRWjrvinusLmlsxR%!5VBrr`#S<bt
zc?~9x3H46{EmT;R4E^K6PiSv?LO5uG-IGGO1cNvweCz=dCiEYG!EoVe$}L0)J9+^Y
zDIBF(Qk0NIw{xO}XKX3{5+meq!q8%cPgBq?P8dQd(Rkr|ry!Fc6jRtLQTW_WkR;*E
zS8yg-X!`|VQiLDJViHaZ=g{HqjIf(FtY?Kk)7qIToSzM!(uAq&p_eZF?|FEiAq+nP
z%yYs6JE4#%e3p)u)+}MvQ(&`&??{22BXl1JOs?<=3OVKp11KDMUYJY?tqa0h%ADs5
z?SF=1fpBX-&<cfnsaUv3=x7UtVqr7Y1(yi(DRg&H*h5zfFA4iT2UjXw@FPUZgw6C*
zFBg7B;h)P^;gj@H=L%u&1}Ihvk5DmdmGA>v`mYERz0r47_zI;Hs)dVacXmy<WEmuD
zgoXPdQY$=6H$3WuFNVOU>%zAA=&Ki|P-M74xR+l0jl$n(pU@<%$bj8uVa^M%&?0o8
zs>&NetDY{4w+d@$@oN+IQ*^Rj7)=qx4q>+=>~;#ve+TIjwzUHErf{PSirvCMdi-w*
zxf&Sk5#ocdc<_YL{b=kJmK*@NBRo$Bu)9L<f8ko6aQ8=m?iU{T63z?=!%NUND4evu
z3;lb-`7dEGLqcgLWQK*tAJKSU*ysS55ux`e%#RBH`38d-6Yim{$V1_uw9l9jy4QnD
z3V-FHaZ1=n#VwD7COYv=3tu||pJs%3Ht?tkC+b1$L<|Zw+KcMLp?6sHdkF3B97LOG
zwLKz=%mn8sYL9|%P9o(^{DGWBk)!a*Mb!EKM@{q#1wP$G-%|q5U9?dQ7!T2{*P-qy
zYCZ`CFHy|r5b+khMi&TtMEAPkg|FyMKX~sadae}X^cUS&hQ6bsHDA#8mjXmLSzrT2
zopdA*61C?6G*~oP24_M<O4=D56G<pM9x6KVD@Ji#v@QvKCqx<Fft(aQQ-Lv^5+&0<
zAxw099b5|+)nA2PgvizgT%_nL`pra%y4}G=i{7JED@L>dp#%K?0Z|wgRK<yw&=VUk
zT0=>k1W{!LxJ1#rv`{69mK2~dS=5w>fu@M|Y=NcIqEBg`a7Oe#Eum*cmtMfErHbYy
z06R^zfCu$-k)R9yW{AGMjK*^!=Y#MmQ<Sg>>RBR1C!np_B40|F<cNHJMrW?*g)LCb
z6J?I0^SnrA2Du;-j6ow`G_J(#6^MA5Fjy$sxgOX>qO4l@R4lTe1(XueryDSqiy|S#
z#V?71DEL(>I*|{|GSMxHI+u&Sq-@V+(VP@uR#-(kd-z=`;!xzVN^~k0pjSlMm%v>W
zoux!)wdnI4pj{IwKL=Wk$ZZW2Yel^jHLepqQw@ddqCqM&uNPVAGDU+Z>kxcu7TMF=
zyG0c9CnRr(>gm|qDoXD|Uz;e(55sL2S?{!h?GU-rU^+#%J7BO&<h=tf-W2VLhZo(V
z{m(<>mZ*RhzaEhtJ$Sc8i8Q6XqF>Gc^p2?WYc$>!-8lh;KGDA!n2UbVH%ovrAUeAd
zt__OLtI&5(H2n?i4v9pEATlg!vc3fU`=V|-UyO);p*3_=^o~C|$3%?T;2wxNZo;Q=
z(eHGye<=EB1Ey<2baMqjCq;V>0(43gOtH~NqW&{5I4$y~i+?ksm$JY;7CBQo+fJNJ
zfk1olxhK(gSgcP0n1lG!0xMvSh<_FV#!>uP0yrn}+F=l9aeh09i@2VmF|Ok8&OpRX
zoJfHtcX16xQ$55lYy{^izCf#%m$;P;5pQuKRjT=j#~;FkuXupoqJH9pL=3`T>_?Y~
zkBS>89v>j~IYjl>f#L^r(IZHFM++B&#s4+{EktZbf6-&&^$D;PD&_=(J1#yu3kFY!
zche=1lj6N=VDOZ<rxGGz;^=WShKo~&!9|GQqE#zWJVANVC~;UU>_&^Vt1*@s@e@ZO
z5-To8rHs`kP8|I;6ywF8=+K!Uo=>Z0qWC9DSSE?xX|+xkAMApq6!D=pkkjI2^$<BD
z{_;OKb5<N|2TQ5q2jp6sxSW=qbn(nTkjxNAiqLpYJnMaUktyCmW$syG`(-ecEgq`_
zXU!9T{533{7u!)h<AQi-GyZD%;)!%97KnG(0j5w~Rt-`luK5Obi^V<m@V7)f7!OMq
z#q9@yc1eu?8ihwqe315mWn$@ekaF>|B$&7?4iiJYLVTeLn3duWsCKDJTt~r?D^~Hn
z&tdSY`0H!%qFOxS1{2rB?<B$D8gUg>0@sSMSHq(w4w;0;b+Nh~2J6N6syH4svFE$c
zYZQOw2)!n80i`yZ#j8GnWQ$nth`t+QMki2O#Xl#auTA_FAL{MmrG60U5L;(x=h!Kh
z&Vj>S;$LX>xhZa*0O=P0GzJs5#GMq3?Ga~}z>C}BeyS(w6@O1VsXOA$v})ZI7t1lU
zKJi_8NA-*6X2ZmQ*!~w_4vNR<;@>^7<|>9gB;H4HxnXfpD=gd>`&fN|JtA)T42q-T
z)F5zU;%6up^*}r`37Bzl+#ZmJVuzQ|HzDo`0yimsHyxl;;%5@j_(<G07iiOB#baR4
zh_6y?^szW{0wc7O9HH2#z2uW}m_IDR9vTmx<mLCk9g#eImbQ$J61x}>C&|e37>u*z
zGm4tINGd5H?kYJ`3=?jWBAOC+$?mVA=pmV;ErqA#uYM3O3F|i~cuN{BAU={5S_6G0
z;$P6`Cn>H2=Py~x0LoFxAG8e(kgN=bp+HIhJgPqnlKd;gc!MPk!*Do6@(Qh9$0XN(
zf?}xTX{x|FDY=+}SwAJQp<HU1WFZC5!X+DCfWZh!=tJ~HN|HF}i;}#*6O#}vdH*S3
z#z-~>K_pg^l8af3leBF?U%W(3yY2+Zf-<`Qo+x1~gr`Z8>Bk_+lJ99-mm<lh<LhZj
z)@{I?k$BSi@2up%w*iwX38eT-nndvnVA3UA%D!YsHc|xeoMgBFu4PIDHL#Q=sVjzS
z*^=cfDC9_96azX}a%m8T@+3dtZ((CSFVT0v?+X$&UFOJ_%&df^0!jT2z!XaU`VFHm
zlFW00-D1hx)6g%G{G0;Ci;_;-@?Da|>;YP-L`HkAGRfrs<0q0+^gF&Rd1EP{D<t8R
zGOLtaD1kziB#1n`BGF2qchxExuK{Sa<SM1*u1R(~z>6Bmf*N$zO8$0)Gj)=dD2(vB
zB%d-u^^!xg(AOaG?*nO+2yHRKCdsb30Bx3Rp_puognb3v4T%k%x?3fcv?XtoD8B%7
zy9A$D#e*l=NblrMi8YuKVqKD_>C}BwvYuj5-ICkeVfU8AN;N$_l6xm${<h>>I_UOF
zx~RhLj$|w4N$*NhH$b6JvXQ2{U-BarKo3Z^RzPG>;{O3gc2BbU5+-3t^45Md4ok}a
z0=X}-%!a~<<hV5(?vF}#8en2fGAaXkATd(0@wjB-|CbCTdit?VNCZ@rJt?X92tG|o
z{(KoQk0h(FgG@_Ql$x}YZukr4?WKbE;M!rS9Tk~4NVie&>WK7<`;c^${!E8aC+Ry>
zp6@J;?xd-4kvh=9#8ujE2Sqn2J|&MwP5SCJ`0XK`qQQ7dKcIqQFX`u$+whh~(e}zm
zT0%u_zS6E^ko1$r(OTp$eUCzpN2M#Nd@Vp4n+>o)>BsK^B}n?zK1c>j7gLxlMC$h)
z{r`_+(yMPkBUD;Uv6AD`wWk4dLb}@n!#*k9PxU^hq@0x)eVBA1ow~!N3${QqLb`*V
zkx1!b@-Rv&TnV3|rD>}m86#bA6qvEnkKO?nCtX1s$9U<iObjqVdgurElqg-8N6%l9
z^cOmHCrblp*-DYJDXDl`dNmA|&PaED2*tC~HFdyFmA<|eeQ8qhQIK>ghXF4#q<(bF
zKPRoC%YB*BJM<RKlD@SWcC)2Jhk%kJjS7ZBu5=bv(d0?%_rd&mX%~_}Hr5N$6W?MI
z^Q9rFfGLnFPNTC>I!eE!BI!4c&?uHB#DXi4PFw=oMX9S76fa5pXiX`VrqL2wCS7&~
zDCN@T2ymCBxoZGcA$`OKSf!ND#{jFO9-pJ}iuCCM=v|enHBhLwN*f|z;+iz69x^r3
z1xm=&N}VaQQzvCHfOcIfqK#a=wEt(!bA!~c5Y9A86XrpoN!mqEYP0l@QlPa+D-~$G
zA+4deaI3W99{g>Sc4eWjU21y|cDtljI?~>hX49snTWSp)f&MM&a!Q-_NZ0#9^tN;r
zrObP!lXlR!BURFk!MjoqDk|-ht}lZ^zciJ$%>&Y>>d`kSoua?UJ?X!;5E+t2(`}+*
z=}YfJ^1igH6JCr+e|ix^8kJggAY;-Sv9R|*8f~SR?zlAC9)3TR4p3xkLb{z!lao^C
zX248IOJX4MNLoc-YMPc7E{BIRQqxDkek`3k3w?I7r4$0Umu+<h_F);f0gVo_`c>eL
z$QE;;;3)gs2n8qEn=D{D%N|n&zl&^E7u|nwl|81l+f62T67IXpG<53rkQK7f=PCP+
zb{$@_<Fyd+mT8uP_{erqjkT|A-y`_sC)4|568vRaXMi4+J<0<Kki|<eq(Ip-{{S;c
zc8*rrVA)6CLOnzlOK;I*vR~`z`%9s+2s#`dmz|{@>j~NLRTw-e<I(xzlx(*@8pC88
zr0^+RwtqVmBV?hp7l@SY>cX(2WM5OXJ6ble7L75oy{F()tjt7ZWO1_nbaIN94P1nU
z1epsJVkOG>b1*?kvgB*@{3XlYp!`ybY_<dRPs`p~4epGrw+eormGw~QFI9GLE5?*2
zo1hG3x-9MoIFlj!fWlqpWDT^*%amo%Q6NiphpMWxWmiU_kRvk=gUgkbzX}iYWXzl3
z&dcgj(04)BLE&+0zHEaR3>L_qrSCx$%7$J8Oo{CC5DfdG>?~c1xFq|k7^GBo;uHo`
zCaYcy$#Pk66+kb`qTc~bg{+to;FYo_4qU5}+0)I}E3(;i-Rr6>LI(9}S$->K=9(<~
z1}xOb=Fu;()+!68=y9E_my*rbWs}puu9sE)1=1k<dmCgLWw}!jX_D=_1hi(^Lpmq7
z$aEAHxgnc+2@}*RTP#Ljo9r}Y^V((W>1Wj;>!lxXr)*6dpu1%EYB0{5vWG+9x@BK)
z2Dv4(zRG}pkF4Z7klQkM+Ew<->S{sm$ksQ5+?9Pti)Wwg;C*2C%bMslIv}g3sPmv~
zfd#JJlWk4{+K?=qcB;cN{3B&Nc(O>k_%I@Cq&MuSY+VpM9Fr}(0<Z_N3ObyP%jR3R
z0_~y9mA1$evPfDkCuPfM-#aCXbb-br*?J=^P0Ng{06HUkyb|1F*;iEKX(!*K2e!RD
z<p#LJ@=$vI9OU+t>N_HTiV~HM^4)amc9L&;5yV;k+TZx2xyaYdg`TVY&_=2!ag(2-
zT1$8NdOCG`$d6HNxTjpY254ULT-q9Y%U2h`ypMdx6>z@tA_^h+$!#fi<}a`62Ix`w
zLaLMrkYA>^VW7O3((pm@AG~2HSpH-S{vsjrgBO5#Odh%e3Ze3zcj*56arq&-et1G&
zNym(n^3UBsPRU0aVJS@hDP08%mp_*a^AYlJ%9%yVMegW}k^B7tm{>Vm0`)lg;2B`Y
z%RjA$-2{0o4}(aQpF9kaB>6qc%_qyx(|b2X{tbm+Ps{m8Wa0bs@`yN?I4dutGkmJt
zH6KGulfPR9k}m&(wzwJc_4KMcCqLi@m`wRW3SDH$Ck~)5TmBS9@^a+g)8}Jy<^NGh
zUY<OdvgzmL_vuA&L2jkJUcUT1#YhU|8cN(1%K!NZ#9AcJ8-Zf6JfBLaO5~qif)^L%
ze^9~qCAomUn^-D;y%Bw7@+>+}mCLt?fOc7Kwu4@U{0I7rR?4Hxp-?5yxeV@#{8idb
zUX}0u7YfyKQ4>(E$-kyQdX0SHMu^nP-wOv<XO;h*0MYC69Ru*KUcPf4IveDFWy1YN
zdG1jRv`N0~MObQ<f4d)jE%JkdP`Du%)1%TVmx%z=CXb?$lXm&W0sIX*<m(2Z&?(<V
zg=1av9W6k)DG&CANVk0OSE%2TU#8PSkKC%Xh5l{%iI?GNuY4a>@7<9{P>$iQ{4{O(
z`s4?m1zNv+9i4Ip<ooFDKPZ=Nhcox&4-3&ZB){?+Obp9cd<$}4?kxcsk-tcL%u#t~
z56GCD@hr##`5W}ajLUoI4f{|&&$<U_6LRlHz)Z?l2En%}`McTBe<c5j^61m@@)TH_
zk&9jjc`V=f5*qCkZ)^f*uZW)og~N(ZX<c?u)Gh`&qFA^b#8F|NggzIAwH20J6<a9}
z?xxtoN29yqIm*6xD5~bsNyt-SF@p6{9H%lEZ^cgfb^9o;$Y8=(5u61PKgEG?aQ=!`
zDx^HB_{|1h1Ss;U@H0@c`xp2dq}Z_&eZh(c2cQt5=rf}6n4<VRFhdm=_JbT(Y@`aT
z6N;~*0d`XH^#ZDYIi>iy3+BTV^XN1guBe^>XoO<NXV8dL%%S8$l;R`GZbvJ6rU4qG
z@KS-qDwNG2af*>LfW|9SOo${X!s(Eds5nK3vm`}9Abd(zEJ%cf6ovU5xYLRq4dBiw
z3UDdOYI9bxkK#?KiVs6EZD|S))jXyv=AXo0Bt!8##Tw5kI;pNBQ*kQ}`dJExX((hX
z+7^M!QP|Qg#9YOG+Q;Q7GHDZVUh&8eK3!1Erk7&AqKC=`3Kacg5Ghm~q^}PbDe{w{
zZY@^aq~CgpVm-wrE-FH)Jo%F1iAr>qDm*B}TBeBag?_oBArRP?6}zY;y+ZNRP7JhC
z@#1RqRVkjQGxQaOA_MAI72glRQnjL)LRr@oYojnvHHx2C!a}Vg>_ynCQ*_^l`gN<~
z5WN-a6;HeZOAQKcITRZe-c;t>q!7%7rDjF_A~d!rMkslEL!qHpY^&n4P2k!TWpN<w
ziuZPbbSR#uUw)_J9&HJ_6f1UNo^L8z($UzhSnvh7TMG9GnD0@rX-jZhVbwhew7ZIq
zFCf#Wm<WYTzv5~b><%cF+yOVJc$x0u-BT>+hT@Qds|EJ3qLa2>_Z5zGfErQUv_gGU
zahob2#}wYLfP0`gN!JO+71hsSf*vXa^Dr|LiosVg>`BFS+80eJKDJ&&>m!BVQD9Fi
zV%X4_QB2tZ`>`T{YL4xc>{$@8SDGn<eONh<o?i#$Dyla)qP#(iwWIRf0Vp^r8)#qT
zth9GPpNsOd?Z9+ZPUV2ODOd2(=dRpo2k$+Ufs}>xRQ@_e?>{eP$6buVTbXWz2_NMm
zI<5FBKc;#GKjq&$;f23){aRQ$s%)gxbAa+v4D<t)f(1|yQZgyG7_40J03spE6sp5K
zrrb>xjG@ZzL8u>B{zF^E6H0L-xRc67tH7O7Y93SkB}{pn?gfM^*#Yn(LTN*#J(0?m
z6u?9&ms7AWTG>R~oEYWp|8Fjp`)k0(DN`xD5U(t82bZ7}$3s0)d775sB;|RkQ%F{B
zqPS0rGT9S$Pb=f-{=*sNpCwQ@tNg2z@_(tyqrEVnrfm2T<4so{Aipz|ZzzF%PAR9C
zVy5!y>%h)Z)=-5`wsP~6P{>jGP%<)C`7{d(dCK7dOx}6rw-kfEpe$gcFJCEr2Pg$f
zXWAzeD&M4H`y!=}GkhvmzGwopwM2RKCeSV_Bm6Llmz1B<@u*aJ#}}eyO7EM{FIW2f
z3$9XWxdE<9IZTCXSCq%-(}-7<_Y5#!t?YD#iEGM!9z<%Cj6a}ItE>)yNS%`V|G=eE
zc@c){mFu5`NQ3gvb8xiLs$9o|!6xM&4*}DxG)1DdMY)nH-EJuNjsmn*xo<Ou)}~CN
z4>z?de|!$4L-~F+^g5NJ+c20e<>5a7dQ&+>=csPw2tCEOl*_+?7d^`BQ~`2Z8T%ff
zdzHJsfZiSD_$2i1Dy^n|&_3n<FQMPB)Kb~(fYO`Jri03wT%g@k^6942ka7)$9)^_z
z6fC%}WKF@uh|)x>)~J%{1MD$nPXo9I%Dkn}8(04R2}B+$KcJen3FVnXFf^$QBatbk
zzc)l4DVwZR$ULpgQUH5KDgFra^;nreD}|k^m4Z6<s_3Vne^}*D`*jD^?C;>=5!EEE
z%Z{oowCQnD9i+kvXVt(zaN9+-g4P>XRXn{G+*Bthd*ZG-_Xju+mEd2fd#XO9ce0mi
zYz{qt-l}z#(DzZzbAu&cRXi0c_^BSyNz-4o<^Q=l)ofa}0#x=Cp$$~o6~KIuY7cEE
zgH<o>1_@F5o<`p>l^<=dLRDkep?+L-hpzFRP}#@Bi<7ER6)c=m%@Uz6Oy$!}&tJGI
zU^X0%P#tQ5Z;`5b0$7St?f4ZWT9rmw%ox>+a!gyS>W$Z-AE%n8=u^C^kzUOSss{m3
zPgG^Jf=g3v`5q))rEvvVhU%{lSjtw-P*NgC)k{D1T-6gl0W)9ah!}^}ra-lWs<aAK
zLOYnKPzj@8w@Nj&2QpVw(%Ja?Tvff`29avjJzCPPsb<qPvl`X#ZYb2MlIbj6r}}RO
z+;x>51=Jc;KYj?wM%7%pg59LrMK8r>)kz1q)}jjP1?COa0s2^pwM~_G6qedmA7*1r
z9jeCT7-6TXnT|ePs!)mrcdOFqy?aabn0A#tDjPbg-B$fBghH>%-X7|AREA_=-&H+9
zWk3C@Fj|)fRF(e^1gbnk(05PO#YE$fYE?NL9ahay4a0q_>KJXNM^sAsC5@^&a?m-Z
z$_oegKxI!af^k)#37$SwDMavTLe)+i<w@0nx4}J970Q7<ty)S6))|#!4<sL}PSdSA
zJGH+MDE8_^3Pd=l-=e#WN7N7KNb9J6;X9ahQd@7+-pN^Q?FFc-x^5K)>ZXpR{kFT>
zhCaLDp^hvC@l^ju2QV+SkhbmK>V?@5@m2pd1xtSFk_)ipuU35u?4#;WDVZOjj_m>o
zRIghHpF-4!pM#-e>h7Q6OsLwIij0q|<<>9Jc|tvx%E?Zu7ma{~t23x(D?)9fgG{7)
z5mn~JsNbCjFJjgIn9&!f_V)ovR7YQe!6bF**D#-~zD7Z)GwK_)kUXnSpi@<<I)O@6
zGSpvE5&1dw7AkelR4-ftE=TQOX~mdw)noJk<*8q{0xe&CHXU{g)Ss_``-SQkCje8V
zUPMu#Vl}T3eI@FDgmAl59hZp4GIh-vaOLWC|Bt<?4UxdEP<PNxm`ZiZ({Sdh`ZFq8
zs#e!fHt(AH7fOWHs5xTVf7YtQsi31yeTd?=4eC#*&Y@9#l_IrGY9{T@Zm74hfYz!W
zpmORq_3E?WI@NzHhBIC2;}k5osUB{JLbv*O4ouuq%f7%sd(;z0VSZ43FcyvX)Uxvs
z8B&MQSccVpsAa|XuhqAoMdyfmWgpN+)nCxIa7^t*N1q4kwc7wQu6`v9A`jIuZ^G_`
zTD=q^lj=?3@OMgmm;<y&>R<|5Ppd_9VPZzTaRbO>^_V>x?KJ=VjES|^$nT=@u;#@+
zs5@vZKLE^nMDqm6IBLdgVctm-@eW#@H5C*Fb<ym60K2Z5oR87xrujV%qj%Swq64;v
z=3p1hduoQffbFHJ`w7Hble`!Tewu<<sQYVvp>*6)&7$)dOMph`3KFRKt^s{PniFa0
z3$|)D(e>XDO=kz3I;J_Z4BQFL?}hO6q~?7}hMdx9a^Yc^=FM#Mg=>DJly!tA_6)p;
z)O1t!B}yZrmvOXa-dg~T(JZDim{`ruEl`isJpU}9<28$DCzPPs6N4E|)Qr;0G+ATy
zqMFteP2O>k)0#mFB%aZ{M`@<Bnwm7oq-q?7(3qjg`4uqdH21jRGBp8ITbiZW@e(X$
zYbNQ?pQ9O}L`kmZSNiNmp2meXp64|Yk(iPT8hiR(<ZG-i0i{4ApzFJZnm?>7V4_HK
z{YT7fv1ac{kc*luN<o!rc2UH$T(dA2Fqbv2`UA8=Qxyq?N=;QJxGIe}2?|#<iI;(W
zRnzhz`l>abzXftlbC~veH5$%UsMl(qdl95g^Bv{5uWLSa1*z9meNOMcCe67tc+;%W
zL<6lw6G%bI8=6D?Fwv^{svQn@XohH$)~Q)VZ`v-+fe8%srslhFsCR2lQcd_Rjq7tD
zJsJjGWV@|d_7`TfSF@4MQFk=K=Rodi4h^8OPt!0P7Wy?qjZ}X&ph>6obx^~91+BxH
zBSJVcs#)v{(J{@(6o7o7DJVqWxJFOkLwTtA{69?4gr?;USen#$e2Km(jht?<J<`-u
zy}`7`YbVraG`B0z_*hd(+p@#j)n9=)XkYY#y(8K-6jWGk9JO*fsXA$2`4$6p)?TQG
zc^7SR06<-}3CA!(H|=p+z1+1=ssZYu9a;y@Q|n!V3HH%``4LR`YG=Zr=ci4k(hYyD
z+kTLv+9#;kF+lq?h0cSuTjs-Vh*m=H<YU^>kAY$h)lNJDJ+58hiq;d_D>Q9k+G`Yg
z2-mLp9bQCek5$7&q;|3h2BWkI<=~>V+x-9<qb*tpE>=5A|NAjc+q@bI@mf{{z!J2X
zJ{WJJmPz*?(zNUkAd;@lp=fi4)`Q~l=d9XVZ**pAmmUUMmbUab<|12rwh)Rr+6^U;
z$<+o4;CG(3Z4=0O?VIm|T+kXnfnL7W;0dlk%kP0?p|+NO2}Rm3{smaE_B3VAO0@M}
zki4i}>4L^f+WoZjmuj6T{#mBAroIbH<=Qvslyq4;LI>6gZT@<|RBA&hGF+vdybHxE
z+O1z<Xjiq*{Q%Hv?alzeT+<%N1F6wkR>4HAHm?nObz09882xpv-^)<1*Y;5HLW8zh
z0O&^TP7@q$(tbuk`eyABD?RWn+GBL)xuKoEAEZ^gat{>SwDEK*YuE0chWQTdlN4y`
z)b_i;QkOQBYPD`^-6;&ytzAT?!CTrND23Fc-Eam5Z)=ZEgY;^bP$9@2?W>jG?rQx$
zfcJgc#XeB)*LM6!@4o@<_Y`6s)IOGiyQiJq3DF^~m|h*j+WyV3dtdv01IUQ>ZHhCG
zYJI5`cTD^912jI+S`f&v8P`5RHDV97pVM8r3GMu9NKR^(Q~CC^HlDWoGuq8`x9_o5
z@go!t>jqX*{?9?@O+{@-bY24>j=FQ*ka5y+(=jw>ox=}6bI}d5F$!1R;&~XTo33^P
zB;9p~7!dK$rM(XYPu)^-)JxYv343qdUfSaN=xnp$sITr7DvbBjg*IV+{dKn%0_CXg
z`W`y}1?k30G2UR^A5L&8M7Q;2XdKg3CP6e*w>1tXj_Zb!pnpQQX)YR1>i*gZkyAPr
zogu<>rzrRpuG_H!lNX`$r|oZ~F8&CdiPF{3_okwCA861QqbtRR*CtkXR|(7noiG%V
z)<oTAT9}h`d$ZtFvhLAaP)yM|KY+|>-S$^7iZePkeZ20hZt;6CpQ>~J2O?>@<8-1(
z*IloIdWP=PPr;qjrPD>4OkLG%OhT5<?jc;u*45BPDo58w6Pv4>{Tw9obg~9OpSSA9
z=fbHAx{^&8Oup`EZ^#tr(kM7nsH>oFN)_q841#OLy2s^EEYUr+6$UTrzNQ!bCEe-O
zFj%U4j*G@JotVNX<vP1ycz;><?Z;5B&~5XE`AXf^WI$Kx!ot8^(cQWO$*Vf+kF+PR
z*1hcv_L?p{1d27fxD24x>Ylp|gLS&A&qL$7?lU?K*6X&+f!zjO`67@;-ER~cYSMk=
z2b5;rraxh@MHfo-NjG$Ha{<<>>!7%4n{GTEjqSSNHh^{Ley3esr!LM)QHCzv%`Y(t
zH+5ex$9#3`qP~F4E#0|o_^b8mR`tQ}J37}$n7FIs()PJeXM6!%zwUe5bqwhKO@sQN
zZVzqc@9FMS$@7pdnexfQx_4<mbzgVV3I2}gQn`R0)iG&-8q?K{)ARR0w>uavj_XQ}
zfP1JLr&QmBE{M(vle%YVZ#$*4c7l7PE1m{7ty@?Fkr`d*N?<?MZQBQ8ryq((qrLu!
z3kGpme<>V|4*GZBg25yD{ZxYCsK0U@ZaeAUIs+7E{XYlj`)4ltNUAw@)z3#f#Kukk
zFI|jr*Qb8~;-UXSjWK!Z?Op|_m)_d~eQ$l>ZaCwkZ~g%=zIsOs2IHqcMOXFw^)+YF
zcvOFVH@E=(QxxY4)VtY0FG#;)11tpV?~-dFdI_=#R-0q`Zd;fS)#sc->v4T}DzH!J
zo2fAAq`tHO<di;R56p+@GYc?J;ricy0*TNwcLOa_Urh0c82!9Bn26Pn(^C<rHzmT0
zc>NRagG<o=E`Ug)zLEkUNqW~eA(^b-ybhc-MgK9%z-><JSB63Kj9yCjXwT~R(t@6<
z@4AG>H2peCXr=4VmB5P(z35d;={ddqN9fDcZ{}k3S^Dm;(U+~i^(6Fi^xG*llB<su
zz>7S69o;!SuU}OPy$kx*L$I5#-;;|`7g+V-TF^qh#1EoH`X_2(saXF#?W;=kM~5ML
zQSW{MjhFNl6k#gWzZL?RGX1PAFj%e^QT4%P{gad^snEYbQLjq9+lL@k`qeV@UD1EF
z1PWL6K@_>D)~A|)a!v174z5OTjd%}sYxO@-X0}e>BtYwR{lWPl_4-nZQZ(qJQ=!qQ
zf1WA=oAfSJz}c+-yAPyAe~W%PH}oI5!$hlo>uZ>cHvNz1LE81nr!f~D`bD%Dbn1P#
zVl3VIblQmB(mQy;LXSS&+6}w6^)KHB+pFLH3PkVdW%S;?tA9WNpFaJ=29SQe?;xgR
zK%ez7d>YihM<?TZ`VlF}kp4e9Z4B$@JcOh7^`BF2enf9ikI|@pH64A%^bY?4^MT$%
zE5x||S9_3$`u8?iVQ@kpKzoTvz2Qy3OzBfy!9CKirb_Q=edv6^%;@LX!O_S1mEjng
zouOX{6ZQs&9+*FD@R@_5IT-3bhTai_-Et5|L;atSbTY(In9SMm;zppj8198Z&(-iM
zRcgB#Uh<*$pS$71M6`MsPQ3y1o`!o=(%@z2rtOBe!AQ61eGJlrFz;)~N`p^+1~+=c
z`x|zYK;)>QZ$8ih3{?hL3N%#i1z3<l{tOy}4Idr>2{A;!1HEI0xgPL0)L_^Mu;Yfm
zu`=QN6NZPikU43nT?EimhL@>UEW+>)#aJQ@hsoh6!)f{<#u~C|XC7x*d=irJh6*wK
zO)@0tFu}=&x9L5SVwg{BSf*k1U$B&A_<&NW*@koq1m+n0Dq$$spt1p2p5bRYBw5cJ
za_I<j0WLy6-*Anx)CGnns>&=hT$%?<MTW-r0aI+qEP$mFgO+l97Y*hQVCj-UPv@yp
z!z+~cFEfOkhDf>L#8VKtZ19!>rNXd?Lg$r+0#c|ljC=rlR}5lW<gZ!{JEqWDZOD5H
ziq{Oqlvt`U-0nqZt-(?RXX*@}QHjlU1B#6CR2be)1lM4&`4FVhU>6OACWEI8V`?^R
z`44tm3@KD6bi?qD849h2O1iSsW^f7wX*Z<3340xek0_(lX|V31lV+FUNjh}gG_0k(
zN4G)Z4wzep9$#=hhNyC&-8Sq91J`RvrmgiI1JeaCcMY%61=v2r*eP)R2Ir-it^va{
zlt3FaNR9&Yp5ePLcsOL3x(sgE@FPXy?i((C1<4V^S}W~eM-A<vz#cPH(VzK&K{^j;
z<A#k%u=LO{wHVxlVS>v2CJitC2WO@XGAiVnF;r0?;;~`K4%l`^ejDuC8-HlV1Rpjo
z2!JIABWE`(95Mbm3kDsHj&wG3G77%|rnB+E8<hWZF~*&RC0C=25=(BzA5wtkZq(j_
zK@a2GndtL0?xUQSmobkHLf*zrchTo#-24_meT^SetlrP);t9^*nDaV46~;r99u6=r
zqw{s3aV^!B1sRvq2K$(C&Tce@8uK2}`|r4MGu0cMFfOL#!bxLtK3qIy+)iH)2s0*2
zVLse=rVpSI#wQ3S()ht9C`1{vC|DkCyg_;Y7~>NG7)z`%cr8erF)#uO@y3gE{XW6y
zNdb&R<4bx>Ns{ps$|fWmzy4qrp1&01GTLgMHkMO(?~HNY5@?(??#=?2YW&I(T$+(l
z0B6#T3+VGt8O8@y;LaJR=x>l|R6h%nWkg~WkDBr1hafq|#q>?lTw}>FNS-l<eqHB{
z&pv|s1><=N_2(N$OVMa8Fbe5NU1)sxGCGTlA7_9R8|A+Ow8Z$^HjLt;F|`OVmyGU9
zVYk#6G=ou;8S}}fa%0<V^j$W-N6FI)<JFY_t2ExqgGiOpK<}C>#uPEQtHz{57<RR>
zc?l-yn(<E)23TV?zB~tR)EYUoY}FaBX<_iX(M&n|dgE_Y#L!^;XFVDljT-v<G#MM|
z+ZN5nRC<6~j0bz6cf+`iUOBDCj|yR_&FDpegid45e-P<1Hqg%Crt#%EjI7)Eq%YKO
z8Ryo(wH~9DO?SC&8@;KbzSp=-4*fgE3aS~oYy55_^!tn{5zy#2hR%Y>fRRIgtwE!4
z0DAX~O;njTWZY(hzG0)BB8T^le)rKgVtj#0>PC%>IDm~Af0+e?4~%m9XvnzHix$mE
z<9e$a`cuXwRN?c;*hV|BX`|2sqBBNwKg>TiMp2N%&g4Q@*z8T0LSf>tDdY|4Ihc5~
zcR6C(`~;@U(KJmrz@1F<=mwj!sgiykE++O_n0GaKRD*Lf*-@~--8B0Lh<KRdV(9x5
zo~C2lf#zlUWiyDk=|_U`F}YCy)7P|)E_(Qx=D!Jt{Y}eg`+U??ItN^UX(?s515JBt
zpb%v8p`|R?^d%)qLQH`gG#)eAz5_1Q<YEi%xM`FYuM;LadP$r#EqDBX{@wH&y<5Xf
zr~gB1xG5<G*b$~HSI`(~TJSwIqD+rIf!%1+6558wn08T;I@XkO6e4k^->CK?-n73A
z<`YbIbR#p-^u$+~=Ookax4<QvcD)Sf6w^yxP(N)FzYFe+Ns>VE&$Fh}G0;yng^ppO
z(oC7O&qz1*z5x9U(>D}6J7>~%LnPDWJPG|Q(-3VSvrUD3a5<*$)<Q4WbeJk-@=Tvn
zZt=V+-xqxsOz(Q5vC#DVLZ}y+)H}cxo0^`5dWp$%K18e+O$AM`bjifIiMcE_9i{j{
znaP>T-^xur6m+|6TJ8i=Ve-!gsWf%cOSQ_B`7cDSm|j^9?y6}s7wXlfqi?{(H4}R+
z22o>LPsy%Y(?NP)*O@$4LGrrEk+yU7rkZY$2CM0F6-L--(o#gb$+X=J#b#6WE6`{$
zUHcr)+%R3HHNVxgEE9cgrUI&FYd3ABeR_v!HpP@WO#x3pq05wB1`ltVx+!YhZMsfJ
zu3M%*=uSnC=}r^$Zkx8z;knl|kP3hAn5^?Dc7E6NtqK}_rq`&-zuzRJ3ZDVfo9!Tj
zCjWE5zGqtW2izYrU8WkOVUth-nER%6?*eAT^vMd4QB(91SQ;~Zn+?4OreB`~88?mE
zqwk?<HEoS2OfK|tnKX$XVn|b_Ggb=wJ~C~gRN=H~&mcNyOx_y+^Vsz4Y-re-L+S5p
zZ@y2<)?ssTCKMdZjZ`Fg#QZ5esgC9ndsuQYZ_%UC)!eiJB5r0`J^I|uUWYLy9%d(s
z+<Th6_JZ>=&)E#~-e!+7I{*2Y_fc`0ulfE8X!x0JOlb5szj6r^eAN6Sm4yVDQ#OGF
znwO~17-XJ97afDm_7tcMF;~%E{Fr$bEoGtRneAviZVnBG!4qbiCjouZ{Feegoicy3
z0w`hTTc1E7-0ZiBp1%n5&}BFkY5p_{`cdX*z6Td=Ui2RnW6Y*PD8`!SH=!@i?Boi+
z<IT6IFTuPn2YrcV5!K=)nZKaxlF8=yWK3m>c|UClPMc46LGO&YlwMqC&0Yu5mumhb
z4_uo0xk)<zrJJj1qn%-HD?{fw^Za)JlWDf4D#<Lfn6AfUo7<`}m>lyrljzGe|3I((
zJhR{u=IOjS`zZP@nBVV)7y0INIzkkfi(ZBKLh}+MM2gHlbiK3K`~jULO3YvIp>WZB
zkaF|ZOXkcWXq1{6?_n@y=9x@rl$&3o-|S`cg~yPoFh89FkxFy74xm@f32OLTZT30~
zk!xmO$|%*C-+mDywdU>iFi~fIZV@D}o4?%wuzIt{Y7C;m{QI*QcB6S2?F^dCNhH~9
zHH$jHwwQJIVd;i>k_pmkHe>>=&0Ij4^LBIn7l7$72NglG(_BlBahLghDx$q<PAkR)
zcbmVx0qk4m+0VgJkNJHH65ci!zk(t4ny+WTnLB0yMJ(@{Cj#JapZUVyQ0O;X4^e&8
zfO!KYjR(#DP>}MTdG>2)95S!hL4Vk6cNu;6&D9k18!;cCrEt_7MDf}&^GqCEdte@-
zrEuKrM<MWs=2afhn=m`Q4Q|r>aVsoMnS1BM{3G*9`rO;J`CZx>%$U{IXTd%;$I&8W
zXW23g7<&tIAGpJoK>R*z94xjsK#o|#zk@+Xi<&0i$r8K<UN~FcrI(_MWhxjZTrIoS
zL&VMUh?1}F7R&1}?_tqU9hawND{Y3oEN*nS-P<yI4={Z!j)&;|=WEeSK*P_HF(1U=
zvi=cfFVvDtF^l7tk>#*-!s0y$OD8R7DI|5u;`JRG!z?v)UnAUd;}48C!g8O|o{^US
zJkS?qDXT?av}M0P`r<4$PeMK3lD`xp36^dTm`$|2(n<OEB#XmO&`7py9|v}dW$`EQ
z^t2_K@+N02y;K5q*7D+;AgPv3uL3m9Vx;Xxx@9x%3^FXK^m03AsiR+aro}TJCbBG_
zP>3hnB6kLtW4Sj6dbyT0MUc$1ESSNR<XiUlQvGLv<sT`AU1)LAgA`d7dw~>N-k?}=
ziDk)s_;k_ojRY{4EZ<Y~snqf+WpBzXB^1^#x6GyV;bluxAM`3L0d(}Kv_yQ4zA6i+
z5O%Lv;!<Gns^u-J)vC6<MNzhEmibgrXsxk$|BcRC%a3n?)LRy}p|!yhv=cIo7UyNq
zXtKCdjHKDZsf67Yix&m4Zdf)g1!=Vm(e0}?OFCsw+AVr|L^~{U1N1sASFVF}S)_E>
zxoHu;3dwHE?}veM%QB(^>9JbYbYP&jEgy!$Zm;DUZR_q>zE}v+yOuZ&eCo4oq^lkM
z7MooV8L<4JfWn|f|1A3MS-v^~6GN8v8Q2}R#L_}>-;(?fL`E!qU!rl;@+TEWj9CuS
z>Gy#p<7GHAZaKii#7<hQpJv02DNBey$Ro?udRUsa)Wn0Ev4rw5rH?J!C{bf?n>+^^
zhiykMpwYqhPCx7(u{}h8bVu9ncGz{YovH!nY+FOOE?sQbQWVwI)~yY8-E5CB(dcel
zejg$pwrdu{3s2ki*3aRom+ftO#d_P$PJ@Pzt>$Z(@U<=a5E_2AOKGR<Z@Y{(!$)nO
zpu9<dZNo)02HJi-4ZA_M0d&bA*mkrS9){S~9f964TO4Zf7}=gJ0p@XA-a}xXu<fE7
zq$h22xIj5&yQY-#e_^&e=|mrHJ3^772-}TxWQ(*F{frSt*(TFAHrm#oYQ17?Uz!Kd
zSlcIEFr{&}RkVpnw2l1qe;i$Re9l)FS4z<;rL@)3R$HaIsAuoJcdONn4t*8XY1NY<
zL6DG55((K$rc6m>k%dHt42dixA%l>}^nOqC&-vVY&i9;i@ADh?o^$Rma3+o+qF7-(
z!;cPTo@M+%L8JsmofB}04By2tl*EuN13a1W9Yt?b7{8a(`G-`7BkkkPF<y&?-89DK
z4tSByxSR-J1|y43N@X&Z{|2S`jD9MJDqzIZlc|v5MJuo(#z&N!C}zC88wM{jp7R5|
zgt1nO@s={QRF+)En63dSXT0wQkqXAFO%S=ls4S%S-&ID@ZZInuFBGD;im{FjZPyqP
z$*@$z$fTrIEhB{<o^_1(ebBnjxJdU{J!1)7j}45LMgSTav(7=Ji7`DGL%YEUtbqAu
z#u^4BTNq20!|qMSsR#_Pm61SufHua^T!`4)8IDbunhwUF6szoH^jAaaEr#b7%;jx{
zH>CmZFn*=AUKb<X0@BTx^8u9hFm6-H*IkBr7I60%>*y)a%UDGP8GVdT*Q2wau`?X4
z0fy@k$bH5iHPHEh;l+dbK}Kc;e0peSyiI;TVpP+5VTkb;Epvt$Uw#bVMj3yqp>&Lq
zxC55P8PT0EKfx&KK<6Z5##~4~VdPS=zauk*PT4pyCur~B%=Dr|?faR_UINdBSvw!f
z4lqBa0+NHwd#}O#A?6+WVceMZ)wj?*%>0xRJV%-Q0jP0j&OHZF59V14=pAFG_dw)0
zbBPv8J(=%P7R8I1eiuA%X5)(>KFq5Wb@pX8%mdDkS(FM9f2J#KdrvUElhApRd7KvE
z0Zbu<W&@cwS~2P%<}Ev|olY@l(p?$M+)OWm5T@y8$ed={2I12g<_GkK4`n*sMk|bY
zi&ll<Oy^)2j9`9!1tgNWUk;HdX5T6pjAkyT&ql>CpQCdGu}t5EAaTsP)A;S<nUR#A
zJ<DwV79J)rYiH3`F_GEGgZUJu%PEMaGCgRAe2%%Cjy9$-OIE<|bY{gnz-KW3r0{JP
z^AxQ}vYA@?CgORf`*V=YVeX+Cmt1BQ#q%yOKcqW7pQ$_zodwKAbdIi&Ih2M07BP)!
z5V^=)b)4d#mzWc=@TP>hcspcDnXkVDU>VcrCPd4b8I)bCU_MJv)XPi`6**sF-lv4)
zRc7ELcwfmZ*bEa@%-#R(d6@UZfU9QmXJfi*m>%^0t7W#{L1!KFk{?EPow?$50P30V
zBiLr2-oTVsLR%yAS-KLMm~T?Z<OWlI0=k=-ztP3k!W<rk7dM&P=n8CQ-gpSzZOoap
zL2hRToq+cp%-&?cJDD%k!O>gHUw2@hZZo5TVD}EwnFo<BX2TkgZsy;gpz|JcB~`oI
zdzr6LwNoFneiDd&rkNs_156bioVd>%qz%m=bHyS6A2PSUjm}5RUGvZyVt(~1yclMd
zL;*L#yhBN{QRYf2Rvcs2l9qAibEy!SV4k77=?SxyHf|2AbxyGB$a?BMw4Cg$pTmH6
zW^MQlUhHR`r<I8dE9N+eE6d|~Xgk0vp*o|3tSyvjJjB}2kCq!tT8q|URs#LoiX$vN
zU5`gu^PYw!ch;SUm<tcq)kWw$#_~zRlpJRnK7<8N*0+B^wHK=~2t03={aJc_`>-Tt
z^!l=fgW!}OD`pgG{8?XY1mXm%NeqWivL4V1Ie_)cZ)gRw)@=hmh;@&4gQr;abKylW
z>z6Np3t_$e3bdSNebfdo&ak%hpfjBH<0E(x!TR$YaFMJQ3U5cT{<g0HKAPo0UpI<j
zrBYxZmi3byh<KKa4lbQ#ZAw6A0_$Kt>?X37P$DgfH9)DAWY)|d;b97E>Pqm=u^zAh
zNMkW+i<!<^Po;brte$?5OqOpf3}vyrg&^51-vYRHo+bO+jxpu1c2c!(E=xnz2YIZ5
zdLZ&y+b+SU0@i3CT7|5H??H-KD<~CI%vxOw6Bk*zba`B2<<5i`r7RC7beFN73WP{G
ztA!3hR<NSyL+52ys2?m`Vexu^yUOaMRBRQid>Y+<*H}FasHtYj3V^6#dAEUC%X+yU
zlTgQcbQZwttTWp{8dx*vU`iwFy)2k$Vtql6@Ea`671(WN9V|p=D@(W<2HRKx&QR9Q
zDtiGl)4|%g6_TB-Pmf^`w^+C6A%B}yid~s~dKYU7WrVv~654n6urg`ubC-3E>Syk;
zTI%6UFKfe6i1e|9n?VLxRZpYyK5Jha+<w67dkug=mWZmm9<pBEgVrO~vxi|~h~?r2
zEyJu)N-aKS{rNRoBdmBY_%zB2`wam5I4g1`)J(8Kec|vV>(~v9@Cob3Utq$4{mm1|
zII{QC+Q*4~fDg(2Y^e^~T-fh^1)eK=-|qk%V2h|k<{&$V4)Y#jCqzJ*8~bzz3?5;>
zvly+T>|d!q-kt5-1!W%W--FS4%+B6U``zPg;lBWSvi&3=-t77>!1Q7J{RxCG`v`58
z{Metp3*yiA{s2k?*pI2MF_8Tf74`<PpCqGoie1==Rxn#p0PjQCjk7Ubr`fTzc@Aag
ztVJt~z3N+tgtJW%=!{_7IST=dWM83ReH43=Mjy@Yr(+bc?A*hUiDPRopfjHRX*4>|
zvUk!eHi2!RmuezAE(E+Jb`k9cli996fTXae(e0bcuC!ug=h&WfSERF1PK?`u&8CM?
zCOdvA29d=^{ToEH*-KUUxz4kl=)6`AJEj{ldF=V)z+Yf%BoNJK&rgS%0`|xBjw)pT
zwH&P?wx0t;irLRos{9iBYs%J^um>q@RLVX^o1HTD;4bjW*{^+pAFYCYfD4h!?A0zH
zSJ^-NQvR=!J@hR^tJqUYK(4XlX(3k4F58Tmsbim&VuaV(idW%UJ^Q&~h%~VO*93ec
zdy@k?o7m6IfXEHD!WE>2%}fWm$#$d(YGpUJ!QVFa8WYU7v)Au{>JIjY0>C@jl0nKp
z+-6^;+y4%GFRiJ&*sJ>RJ9V?qjX`%0duuZc-es@a0&<V-(hp!S+x#k~tB?IA6{YpF
z_s)mX0rpIKRXt#TKo5~Y_Q5=eJY+}y3ojnA*Vv$Xi0wwXu3`2Ls?~bTo`X$}eflVS
zBbCF9vHzU{(Q)?XUm-fdKD`dQC)vhE@Sd>4-p4QEz)9Z);>5X58yaU$HkD=V=Pahh
zmJ4S){jjc_^|S;!z}ejg+(FK@Pax^WS+E4W!<@F)VBrX7cmqU^ax6g*vAc6Vp*_TL
zj%Xc-Cnu5KAYPoMzXIXSSv?aD`*7-J!C_xc<Yy4^<4jh=!xJ2@Y_v{t;$;8?aJ-8#
z>_AQrEk%Mj(M;e@aekvPSukhb1sFWdQNM=HGo1hJKr58vH3zPR**Sk~fg9nR0xAlR
z;H>b(U?Mq*v`UNOWXFI+bC%L$D~6-}9{5<!@LY(*b0qI!g3fa0w*!~J=}LpYi5w@|
zyC-p`{RCbz=cyXNQ#j6fuyBr(QwEa8u~6k?I_KyWD9hm3dF$YJCZ~7;qUSm8F9Mju
z`Gv08Tu$i;Ao4iklOPv31+*p3=ln|^7I41WkIo{_hg8v2%rQ|M<02<H8Rjo>UJ8e@
z63)(zn5R-s!+sbn<MdL*vw}09UTT*)SE)|+3WsUmh2~YxixTLr<a{&@y;YpAY4LxJ
zBhbN%YL1q6Wi^~Iif`9)jI<}M<18M5`}Le)D(`6E^uGu5jhq)v=xpNn?trozoFuAB
zY35`K&}!k#{29Df&ca|wwsGDY0BPrZ^@!G=9UQ|F=<ejqDTd4)P8VfXyEqep=<Mbk
zEyiGaI2E+gz03K70vY!>|EeL<%dt>gyr0v45v>6Z>s^rhoKKpe`vIqtj>-;lQuaaQ
zA?G7XAwA-JN6ExtP6cI>9&=L5sQz<=^Hw>AJ<2&tx&1NDvlP7==X^*Tp$X1H3VBR&
zHd0pa2`8Z*KnLzmbXhubPxFCu=63a<wV&Je5-hoJ!zsDv${nQ_<^k?>+P@v-?um!U
zA#VFm037C?T?3IL-1%pw<NiC!{fSm$?%aj6Bk|x){0}mo+<B2`d2zp6gO)e<6-vzd
zaKESBhA-FOhQau8ugt+<{JBGSVd*4y{USITz)iXhTp)K1ZSI1&?G%hX#a&f{-yoQ~
zj*2xxxKrtIbA~IUg_u2*`(Ol!Fz)sSkZ|rV6x4~}?s^mWNUlp3EJbnuqP2K5cS;Qq
zG2D$OAsNe!nhRbWxBLSP<}CNk6aW&qUZXIP$lauaWD<7@txuA<zfiq-3O9g4{i)od
zJy4d$eftMYNxGf;Hs!oBxa+<FB9ohc45C@wI(kg!aHSL+$>kQ(b2*RuDeYt~aF?_J
zpU-`@45Wa&a5Iz^awk_}OhsHXZF`HkPEqK*#EqB%krHl|3?7zp)2LpxjNAM^M9R6v
zEU3QBwM*Xx@CtXe0nDr16smEl;wtF1e~o)Vjk&1iZlU;T4L6UTsI}a~t3m3x|8zt5
zb?$cBQa5nR>9k8D_edphP29gm!Mnkg(Ye89u9o%=E!^u;@NRO~(5|eFJ2)Mx+qo`w
zC&+YgpQ2zxCzmw^mTqzTDcF9STeAu-c5^q?!u=lZVhPAyZZE~h?s4B-3CUir6Wus{
z+(8Q@`?*i|LD>NJ$L}F>pZme*AcNdrDGd6MyP^mlKH~1BP}UGvPszDq?v7kK@i4-D
zdKAr3?m<1s7?*z!ofF&-D7Qb!^@%|133tKQ;5qQJsLaBVH%_Y#C*I0lw48ZnN?5q?
z9u`5;l{cG8dk*l%p8?<?FD(vkAL6}N0%dNzrw(Hh4)cDjf!jxUDh1^q+<AGCV0!TQ
z^!7i-6VXHaI8QPIYCL&%`q+XG?^y@5e0it8#X$Xd8-GX3pZC{e7(BsSMM2e*yq$^Y
z4B)M&AVnZ=btZU0ytUqd2lFl*gcl*a&LwD_=AEU5$r;|KcrN4nyS%3hG5O&<<puZ_
z!P~eIUPST^CjuYM>s^2m#_(F61wNMdj63{}<Mq%YEuL4k5|U?mflR;?cymQin#9}i
zH?$=4GU@(F;XU^nL{fQQ)17*b=Q9T$rtzNn0iEf*(iB`5_DtRgZP~JT{`7gwY+gN`
z4L;8+q}P59&!2<NTpq_8+VXjK`A}29Yo+~aA&<>OtBCh6-A={4gV`V#dGAt?@Di_y
z^57-B{gDtU<^B2r;AK1o9kVRw$?t+!!Q<s%NSE!rMO0>Sg?Hf$X7(!YWs0O%@~o6j
zsNw}Rz>90VNIIBO&HK&<L=Ep;C`c_Yxe#jVd9!KX*ueWO9p)Q(E4M<jiI+?@xHout
zp)lXfOQOw63l9|uxB+;}=vCFq`<8-cZ9KaRg}d5$wa)_I!CS+J-A-QOG3dU<+fBjT
z+q`W#7}Fiz`*iZBiznZPDe2}l<pS5kn?gJKyS(R3fZyX))9ujDn?~if1H7_ewC?kQ
zD7XHAx2qm@2YH2iKpyfsSHQv}-oN(up>&A1?H?!|=6ygb&d0p(DJwU^TSaN<QC>wJ
zycpvxpaPU}-oI(kHo^PB2+2v_)SYNO;c>P@ivxe_awv7=yHPE=6F=nvTF(5Lo4|AB
z@2Azy0se|N;qO5{gUVnI@z)-q`_GMU5rZ7&&!I^;!vB#B9_3%Z0^-j9^eve1;D1L~
z=P~}`F?4$JJ;vdT7r&80%HI6(0pNW2;_qO|m+wPwGe7>#BOw0#s~chI1V5WrJ16-e
z6#EX~r}%>x$X~F4zCUq_Kl=nGDwsb(CAlH|Bea4$&A&<eurvH`ss1IDfA9)A!}xE9
zz-~BSMnwz}{P{&t8p%J^1YQ(B<U5cUe(6{6B9{LRt*7Gnv#!Fmcz%xo2G8;<p8`qX
zn^WOMB0pbA`@bZ<fO2ig{NCH>P2soFaiUcIZo0hE`K|N}&EPw{29Zp@;}38qi$9&-
zSlRrGR6%l{j~zU26@Kq#IFrl&fU;D1{PPs-yTJd12V6eCU=osr{3CzB?IL~=eT%A?
zznl_x_KW;sIvae6fAcmFC4AFsAf^0+e_)_x{H#?#l=EMv(w++b{IlR)=0EKU{8j$X
zk1(`KK5Gj)tN4+xz^7|`Nd<7#{C#{Ftl{hF8!ff`x?}+A_@7et^E$tu^8NMvlJ6nX
zVCSC?f=m<ty-JW9e7AOpHuITu1-9_tC`RihzljRITloo00NeP%I!Lzj#k8gF;JZFR
zXD5G@UXi!>N$<m_F8=Gq7*aRCgI4rC{2wU0b(epJ67To;f4vCO%fHYIfBX3MtnC2y
z^UX0p4DjcFg5LZ5EtEib!2g3%SP%IHiy`uezqAq#5Akz_Ffq)3DiKN_^WBfYnGyce
zN{~_h^9SMR7(Zqql#TOC;~_G^|C-{{lYGGj5C_3OR6*q^xJ4^uC&5MgQYdv6+@gZ2
z{ep+hXt@ZS0zq5_<#g>F5I7zK;-FxN=IM}N?`r6F6HKN;<cMH5J&BJBW*5PdyWoc`
zbb1JwF#sGBXy|%8E?7=aX-~mQdL(%Xe*bS@A^3z|#y)~VSK9yi3SR#JYEB3m=sQX$
z1=`sdZ-5|04)cM6kDNh*1SZNvof4dW0e%MyF3?*%M34~+6Q>2`s{lA7c!?5Hp#q;F
zNQMjiX_FKo*huwQk%D*2fr}EPehmxJ0x!y2#0bi_)BpdA73}VZH*ta~v<HY6NWTR+
zE2v%sV1nR_Ll8|8d`^3wWPxZ3ETssh)5|SYu=fO7=LAVqNRlQvdI=)wg0ZJzK0~lT
zh+$_67DqvKmOwyNv)KZ6J4A8>Vh!NAg82yT*r(?S#wbUBLGTJ4Rmv9(?gJ?hv`_@U
zP_XwpOcV*SJwS>Df!hGQD42B>K3x)ov7x(6aFJHu<%05d04fAp+Sp$fJf_?KiXevG
zQC9_yTj5NlV8)*isS-F-LDV%t_#VLR)q-p}5H*6WeGsh^#O}uoT^CGafLSl_r%ygK
z2zJnGrBUF~3XvwkBH9?-5bUM`^=82@^Psy$@EmEoDY!|`^H#yua}a44q&9<e2-4|O
zI-P<I<>1{CxW@x`TktKd8t&Ky`}@(`CCKxGrEUS^8;JG@Lh1m#EBN>+$lMbw`WGU7
zg1K~a^$X5^0!ssetG*b;eL?PJxb{F0<^(b*xJ`!%9}3iT2>FrV=XOXA3I6>C@L_?Y
z3jmJ=UsAAbOt6%;F5?1w3jHJ#0xd<^Ck2-%_Vz@uA`rwu$fl38I0|#gLnq-%`WmmZ
zaO7X$_X{_90q-J|e}*YNAY@Sf;GmF8yU;^I?^ofBoA9P1Bo7OJeFx4Q5%wV4JN>9|
z<1f(ZF8q*zae4^-?We&!CVcM-bRQSmC=BBzET_{~-og?yO!x?EQUUZ8epZ4`KcP(v
z6aK=CX=t4gP9cLQg@tjz1qiovLTRATKwmou65cz7xd;}fQn^EjFjj`vY2ir`T4#iJ
zXl)rPJX~Xki7?^)D3}NrUQ0%Ags_O7fsw)^xfoNF@Ce1@qlI#MWyJ~oDJ~u_e0>fi
z&kC3C#Xu8;-`#;1iNY6A&pbUzcz`zT$-;;R;8KK}D1??OoEL-EIiao!tu)~pdbMT<
zzuiRZ&rD%E)xu{96X>CkEj%a!{=9HDy-jn3v&&#NSNOFMygZ>F1sN|0dtQTU`NEee
z9#|mM)1IeD=tmiYV&UIZo_|qz_79Lt!Zl&AR3eO{*M6xmHV5!B;ZoYymkZz6MC;EA
z;k6$jdRdtF3dVFr*m@D>D}_iO;$9Jc!2|D_@Kz@}tA%GC!>1bIJu2y|6?REL>V#S?
zv|SgbIzxB8@S8xi8ickRaHdgMP5)i1S@`D=JZupvXf=9M_~ZYex?Sjoh}?90hfwi0
zM&Btc-2-w@80`Ury~55?kUrs@OxW!gHnf5a2=|&n?h7|i(e4A`vRIfH6fUGMuRIjG
z(SIp;B>cb`gBTK4{e#x9aN9zNJQn^$BO4KlK7-__aMN#qj|n~LwL5MX_R=G5LYVOm
z5R<|py8oUCIZM&$AlkkK2uD%Fc8EHOsxD$^&Z4B>(Yarwd=cYy5w&SBCRfpNAqI0m
zl>Y||9u)mUm8OS8o9QBV6aB&f?yxBAEe!jJNI_-pM@6<{(Bdw#=TX&zhbWjHaK}W+
zyMQ<@Y6(TBrzqS9EiX~Sr{H;uKB7uQAJO8M!SfZp`6(vfPxMv{)cA|^l<hqs`h(uk
zCq)eUnFB<%^e7Az87Ti3B#NbH*eOxc6^uSubcag!Lqvbs2OxS{w1<B5Ga_Ccl!l5v
zq*D!HqB(1U2p3fa0v{nN-vr4>QS&2+M2YsliYbW}U88ca7}3jSj44($je>n~qB&Gc
z5HBik#LS!(edhqT6GUC~-b@sop-Ui1G`Rxyl0|MDT8yWNvc86iRMA8LoH{4Ur^G{=
zXgS5J(nV`h(3v56D-XIeMH#ft&k}9=34m<T&aLRo6@AQxqj{ntN8m1q*3)7uU(`=E
z3<aWoIulhWnxO=*NE93ic(G{z1@JD4p8c4<KYvNIgI0beqL&6>sZ?a7XK$IPh)NR5
zMK|bTs}LP{1^CM%-)7joBD%g6fUBZLTFq99Qfa4HB^sjp@0w_l0G-vMiExa!Ms$lx
zKWat2-@uDHQSB3Gxh`7Xjm~<}(U|}8f1>#^AR0v%TcD;%G=(m&8={6su-hzBe+H#3
zB0s9ezA2i)1in@DT_e0`6YXt>iFVPuzoXS5Iz|DxPSGSy*DaBTE|1%ySyJ%sh@PPW
zgD%m+pP{8&WL}KU9?`{%7^nTND7q5{?}=8?#=cjymOiJ{Cvv5`v0ucb^wfapyG)4O
z7uC~3`+;cRL$n4(>nJ<@P?S*&kw>Cm>tT0Dl>R3?92Om@fyiT#o?;avA_fg`RP-z@
zsmDZb&A?oYi#|($$b?<=Q#9O|6g~eDTzn#mT?C~LVvo~6IEpX1L&ixQLHSZ=@nI^h
z+b<q_6G~mgA-Mp!ihrR>r~~484sh+DxQq&24~ZX9RkWMf!-Uphu}%YWM7-q@%pVn3
z9EGFD#4pow;kelT&jfls#j$h*#!I}EYE8VwPv!#QBbHI%##cOY6e51&I{F5kzqs<h
zA``Jcebeovcxe*=0ph8&$O{xFv*B8hIEe21Q{rox&>1Y|1;FhPF<Swhr^QQ`V)SRk
zqwU~@iaqTVmk$$fON30gxS1k|5n|!DAdzC;EL;LnV(WA8G+M0L49OVr(s^({R(wwj
zUYxjf1|}h1{Fxg>&WbCt(Mk}1Zw5S3d~XPnN#efQP@OEEq}@V__^sd3N)@kJ1~1Nu
z-Q6hunI`_6&JU)G7f`w=L)=JF+)VL~laR?0KSdvq$QIwHBB1kPKE>*D#B=E_oGYHy
zk5-<zo1S_F;(`zW3dMRl;ZY<`S7T<1#b3}9;-a`@GgMy^`^G@BM0|w`S4zc`IaL2r
zCZ0lXwQ{lOI)D}8bPB^<7QaXd+AHEi4Vcoa;&LN8E5(Jgpsh-rvH<uRvA-0gR(ym~
zNOj`Z*>Lo_m`%^Xdhz1(kZcgo`w*>0@pam>G>H>Spyh_RnNnWO;-651WS`z5-bstZ
zo8l?>o8Bs}TnCvp@$3M!+Qm6DK{~`s=`3ZZIE}umeoK6aF7n%A4sEdSh$FrP=@OSw
z@ol&Gb1J9o5ogbW-Miw`l*GIzUTFlpSN!BDINB%vXB~#rFYY=Do_#=U6##f&JdHAF
z55!;5g)t~Dp<vQO@$Zyee<VIeU#lDv-=cDsVeu6Pe0nVYijUTac!~gOM#VL^@%xU6
zb1CFFF7`eOofG1X`55S=c;9Cbc_JS4fNKsCznxI+D9OJCNhiDH^H(u#&Jrmt&-P2+
zehN$%$>kjYx=K7>0Plcg@fbP}N;)>e;33HXrCr=4U;YCx4oh^~;NcNT^d-QLN=#lD
zn!6;KmPa0vsZ<bkOtPKInU706bHVeJC@5p+B@rv3%v)l&O@nVfk~6Eo^p)&9j9x#<
zaeCwVOFkntCnQ&|!_rB~xowaPkeDcu7AW!f5ncpImJUGVl;rg$C=HfKsHiPOvXBl6
zpOzHSQsRsx?L&ANDp73!JVNptJq#ixJLuc3QIbMC?fs)AmNQTqBN=0$H&*ibIGl--
z)F#73yd;;Zea}iv`4CBvROX;FQF79XR+3~Yh1rrN(@fBkBKeaxB&m{_?$B~hQdf>v
znk489TIrJgw2jM<xYKqwQxZ$%u33`!^>(PqmMr)ME}oZsJ_<`YlEi3q=1N-TLNrgZ
zg^$(+N#jwp@+GTWFwg?YSznMs$uECFcafy=B(xPvX48#xQ8IfkrsR@j<rm<UNLt6x
zDwPCK#dVn^cM+78OH%95s*wCIllFg?CB^~hz9M<99`k%vQj`g8m69*%&}fxp4hw!?
zlY9|?!Bk6BZt$>1vgdVJs+APcV!B>pxCD5E#4ie@QF8DwcukU&pTWB!`GJbznkB!}
z2R2$H-{nK(ro^A#x2=-44{86`CUMJwQ|*#}cR{8@689B=osuMa#om(Sgu|!Xl1(3?
z^NwUK9j)q;=*B_1CC^&`=#j)spmkTW^*sE&CwZO%;=Phk`ixSaq%{ige#sg-ATl7)
z(F*FmWGcPOA4v2W5U~$RymK+MhY}ryOdd&AQVw@W(m_>a!;+QX!Ng<9)Ek(@5sAnb
zh*8PMZ-X}`5mN$TT(Xwp0uz$e6~IkO>VAT<CzAB3Q05?=LjhAqX~`)7oTRsC3*szo
z>;P}Sl=}sgx!9$fW&+_V4Wdlt0qM>+fjB5_S_`{}q*Hc7#!bqbh6y?>ji;F55$W?Q
zpzWwsLUo+((iRPH9@2tlbRLt&-h>y&rH@#U^ptkfHqcATrwhVcI^qwWkJO?8@s;Yg
z!H}QS?nikoe`(?`P;){W{~DB@l=A6u7a-mG6kH3GhFyc2AZgcK@J>m8xQ)(WDVJ(%
zLZqz`@bI)WsSB+$(w&rn4wZILMSPeveh&cQQr!lakC3jV<Upi!t0%@1BQ2mvTCDU9
zJB4H7q`$Yp{dnnV3PPQgiZn2vAdPt!BvHC{Hk2kwU!vSqvh+G1Bt^PC9Jo~J=yJ@{
zIq3&eLDHn7w3|zpHhd1d8Pe@^STs{QhtlX-(rtU7C0n|WE`jsXWIBzTBlXIoI9IOp
zN-#*CbO*(4FGwd_U?N}oaXv_a^dc=@3Z>7!3=>7thD}gfEPbA)<f3$Y5iDJj8tLIx
zBK2lNq*Q880iaA8Y=AT6QtcZsSRqyNF$tHY+bdz=iu4s)L0y$j9;W<XrIi0Rv{gx8
zTnFYg>85!g)zak=uv8<RN~K%1(iX}J)Jb2Xm+^I}jjob<scSbR8>DNfCiRB2T!qeN
z>0PP^X^{?4;mb|weM)_`N*flUvrRgE2(GnDrwzlI4ry~Ktv@@Zk-MShmUIX0CT~l3
z(PHb4ltoMOF6nVMc-k!;pc>5{X$$QS?n+;62DvAF>o9P=($O|(>ytj81QY$z@HGGo
zNEdz#fA33YPhb)rNTXO#HYnXdY1)TUZ>sBkBt1-P5c`mH8NJ$vrEAk*_p$U#+BJ+w
zHyi_VR66w!bdE^}C}l7%b*_Sk6VeaqjP0a!7mebHbmwsxbdc@p0dbUZX*uX5)6>S>
zS@z%^xV>MtoFb1dvTrCh<0|Vag%<~8?(`lxXqO$VgSJDmsZ{jqCVP%PX?$4bei#UM
zSuW)}J!B4l!HZ+EyhPxS%iirkr>AV|EI8vOi;hR9x9rQim=Yh^1QquB%J%;P-F~vb
zJy7j0`}1A!PRPEig@u!{MKsO;**o+W4wTv7pv6{@%uMHULS)M*SaDjmYYj}Ckxk)1
zG*tG0s^G$8+8T(2%YF@k(g@in&M*-v8#xLRB|8=dZP7TY3KAoGwF^GQ%GPXwWSr~{
zC3NFud_VBc${x?a=o4h|l#5A}rQ7+?og}M%9$qBNE>T@aifr>ZTB$N0y5`QwA}L0h
zCUcCy(9&feK84N<nGdDPGi94P(aMsYYzHn|*8UunotG8Uiatl?#({}knL`ak@?^=L
zAQxo$zd|Hmwu>&S0$KGLJAj3<TuR^-$=;sC=!<3B$Km2dSuaJVF3CQ>k5-B7$P}0_
zm390BrDd`TJ^<yiaoSH+$j0d7bC+dXu7P(&w*DpfdsUV;0TWfSic(m(CVTH`kZM_<
z0=yd8hwFi>mBlTh^AB}0mLB81E}OX*mg;3s(LftyA5o~LQFeqTxJj1235XlAjTHE7
zmbov2?iSe~om0Lk`*=3oZj~*foO6e)o)Ws9vd}n4-jZEgjLzG#(=LGDk!|pU&Mw(o
z^vvy+-Ke7ammb;cbY0$+z2*zw?#cG9#jty2%H@#hlc_~$^~-M1(c%Hw;Oo$KU*^#Y
zH4kKIbRiDPj?RSchcX@yosVP>-vw?+)<?m*Vc9eac|4ZAJq|J=oBtkoqq1-cZj8x%
zY*1z&mo*;-oseZ;hNVf_UVpg%L>9LnN*(0u$3YzB7ikCNB;Q7XZD;w<PXO32UrfdN
zE^?n&pww0VLK=7n<X0$|b5Ope6C#J?7wPfpCf~Ibl85E4>tNxCd?5vqj>_FHL&V)K
z=g~1H5Baqw$Q+aJqFDcNxqb<lp7PQ-jL=KID-6V2?sWmgNB#@#2z=!$vN2vi`4V~o
z`OCNb1@kB5t#k#Qlux5aOMqNT*^@x|oCxrO<f9+L{3-di9{e!D@{<L?g~;uJ6gxjH
zPo}uu8F^0~L__7xl+*~5FQn4RaQSoIKt#yDp{RAF+=)Ja7$slwB>>U#g|z99k^jtt
z_p$P2LzuicIWqt{<K@}(v^^_dlZIA;oD~X^C}$=?b&~wVc^FET+wBy@N|Ap}w_~b2
zj*^k*<m;xQl_nqk00T{zzmX4;A=h?;mnmP=20)fPyakrB<wq$Qa$e4+>gF7I%@>f&
zm1}$f&y(MznyU-)Mf)L{FW<8h-WSN9r)#xX9&rrLT$HD(DF1g!&ZWRjiCk&~qE!B^
zKbU25$u;oG<+)DaRmgj3qkCCia|*mGa{DD%x+>42JEl^8GY6zfo_zq8uF12g60uqy
z>;qhl{CpEgt-QVffI9iN4`KegJS+i#dbx3c@_!BT+)pvjjq+zl!EBQEtp@&v+(_H?
zW_k3N;I+tqrseZZ`FDi?w#tQ+?rD=}y#S@{@=DrIb;xtpLb6jn`vE+>CI9*~Ciu4e
z{0iv2Bj55Kyy%i!o<O8qF86^*kNiG@6!z(N<uhZT`<~qEzZ*~f8GU`DPwq}tE&cK@
zC@?l4f062Y@5}elmGnSfLNV+?`8)KYe<(LS4Q-F)!<*0=lK(~ZO~djTv^je$Po<M&
zBl2=O@H8qvbRWvb<dqaNAD46f+y70-SJPTzQttUOls=I=3juUcB+r6UM}>lRp-u{2
zAAE9F+)Y8}euc^jEf)ooHma_Q+q5M<pvc{YNjRu*px6E(#WE8*-4stKWp-GxlGZ0j
z6c6SDepDf%&4#;TUMoaA?23=RK<_cdnV(?yxZ?AF;J&9~-x3fn#i<F1dMiw?g6FGP
za2=!fQxsEakH5m7ZmtuGl}zY9so0+b5}+7<7oCBMBr4eoQnc;EkWMKc(%l%WsBVR!
z5QQKTt<#E$|KcDD`v!_NhAJLWbyt|;uhlRSuJEJPcZ7mX2U8*yJ81nHrO>J{d(nyp
z8HOFB$XW_stYVOY6mg2k0*J&bdMOWgR^dGekpzY4C1^=hoTqGFl42V@eUcT!ZQ!LS
zrf^_3RpD=^fa^KMn?ItNrf{RpUAp3K26SgAnA^e2R2Y{6n5DQ(Rb|<VR~;dFUJ*wo
zaunXQ56e|Nq|k1jV!<)AE+{f-p!o{-_n@UfakL(!P;q7klocr&o`HwO3N6KZE-GFL
z`|ti!%zhn+62%CGjms4N{V-9k*yxPT3I&TYS(g=C>VUYS$T36PRmG_+7_3xW=)liZ
zrC3e12-g&=-axBb@sNI)8b$8A7=5iGA{LI;DZ=Q|yRP`03tqiK`2<=T6rLC8|Nk{A
zl4#r9q<Cj15H}Qw6t8MlH0c0rQ8>MUVc%3Jqu@oW;+OSstxZw)G_<uV*bTsSD8w^B
zIu$GESk5iQ<y|1R6$O;AzoST?;>s?Cv>wX36}zdPsz))EKDBaJk@VmBhkJ@|uEMEa
zMHofG`xM*hhwWD+t%ZpJ#sBC4`+dcpk1!Vx6u(d`Yfzytflm(=!=D52ND-d{z>p$6
z6n2Ld+9`16vEtB5@J1A$Tt(-oV$I7C8B?s;iOzAwijDAMLb3H9=(JBNloufLL^1sa
zoN`c>ErF+w%G_-r`;~oKbh;>APQsw8^8Qwk1IiK94NO0%{OnzjL(2KIjdWAqrVoZ5
zR@zfQjwt`4iiV@gAQ@Wj%2z39=Am3k+w5b?1lj`}SGM{=#M7?y+6ITclrgld^H%bn
zg{MBsP<oyDDmVB-#t*u|^H(mRqnsy{%PJvqQaQR9<^z;*<sgB|R$2uIDKj^KcS^aI
zmO#Nu*#q!Gl=~>Tc3N3XE7dc~k9I;?s4{W|<|0gK&!%W>xH9JsJdIGEqhiNMWz8z!
zqm<mA;99gYQwkEJeBmvSSmpequyj_rei_sxC_h^cK%%neO>`zH|0Jc!%4<~ho}#=z
z0g+VYV>R49r~HIURnn9x2_Wgp4!X!PlzsM4IF+g7y#joevgS7cvz2!#@o-)lM6v!H
z<?a}$$yNR^iOxKw^#DeAL7B1`o%zb|=r$}+en!Q@h02Vx5GhhxQ!s1A%7-zS^^3|d
z+6`V(x>6-ZiSoP?TBXY0zX7gHDX*giO1bhSy2UG$p%listgL$pCax&Ip-uEv<--4h
z{L1(L2Cqt4M5p?$DfflK{c2@<6gq2^d*~ThtNfBqYt|`CKLGE#GHNg2^~zLwIW;Jk
zU&72ZDvvmWG$|+BVD^UcgI0R~H7ma&Pg|7l9f!7?%FPFXXjLv+3(+<uCmU+om2cV5
z*`Z9E3G<!GWg3{crJPGS$u6Zw8YH`w{T57DkMg5LXt}H0at!32^7wX;Uga0x1Ky{6
zi|(d=C4Vc(fbxcR3f_PBm7i1f!2{)FC6o>-UtbR29x9dD06tPa)eF~#l;2aJcUZZO
zs@WbZqj$mJh%$si(WA;g?t_deo#<%rxbnH<&@!RCOw~%0N}D%)dZOg90e4XSNFOb5
zR7qxIew|d2^c&cnRr<LwzhAY75+*LHyR=JkRe4eM>jBm4wa|S~HSiA*hg6520p3kz
zqN>irDk~Mm98neUFeOJ-3v1DGSKagh&O^1HmR0^LH$T`tp(=VB<fLkxDrEvxuit~+
zK$Vpi=s|XsH)U^5skT!1Hdyt%9?TF`-_K~BR&`ME;2G7<;}8v1{ZENjnCj0?0K!#G
zw7QE>&HWL)NY!777(|rHJOW;{DvPS5VpKEfAWf{w!4V`*wRt-L@v2^m-kw!?&4-5x
zD*OB|K@(M<?SjE1Rp<ZEN>+7=fKO3zXl0SA5>wT~IaLIezon^ezXOqU)erkXGE}?h
zY*VI6{t?|js^<^EM7HYGF_<{7`iSnv9Mz-mU_MtBPcgeZ)wv_+yr5b=9rp57%j|Sa
zyGXT{1#QKuT_@3dQHAI=ZW-0wZBSaG+DF;XQq{{;mr<rFP(w|*s%-;!6{_E9;dw>1
zoDGqys&NVpRjS^l#8Q>2rWE9w%J&>BRI9c;Myp1(ZUkegRW-Z{x9e2jhS2?YUFFDz
z`Fd5^+mLBcJ*2HbqspC<`c0~U3=I2*>gT_~yQxyrbGcO&t_5jVEh_}PL-pqmaHdmr
z_7OyGss5sb{cY9d&*1MJ)u!{%(xqBJN1?k_($Ao*NA-YeWA3WF<0=1ePZdKW>{V?K
zf=r)^OJy+qDvu^89Z>yahHLj#4s_h|fr?32@Sy6K*U);X`Y;6A9;tGRL55WCP*KgW
z>ev(*e60G8&MS_nHdFLzRJHdu0As2HMbJ5}3Z^*7gz9;GYsfx*QZ+yk{3oiZlsRxz
zM^GNXNnJpPlAP7gQ$*TT{c|XI2h?+DN)M_(Ish*Yse>Lt(oH>=g5`(R!ykjVt7lXI
z;Gv#Hfrw-3njawIrH=g;K6$H4%OK*Tj+de3tDdtF7VLg%NgYJ})#jHlr6<(O--U^j
zY7e@+0@TcJ;dh{VDJ2(z)Y;Dhe@gvA6-0v7ty1U?QP1*1>$KW?GqjvhZySbWsCw!u
zz{Av5`dUG_dd3wDFhcz=9Y%~)e@t)hDD^LLD2ukMkNpm2jQT<-NUXYdFG!rae+RV1
ztIbqtb5{LpG+awicQ1i6iRz3Gp(aWF2i>X3>U;e#k)kf!j8>{T;77F1sXgvNcbfWS
z7?h=}_g;ac8R};!vXrTQ#)JvVQnM*YpRKm9xB;c-)f;C)X`cFy8o&$cX9EDtSFc_I
z^95?#7a)b|-D{w`NbQz{R<U|dHk4jeXNAJiOKMglNQrt;0YpmGBedo!Q~yY7kaG1V
zBS?kXr5WV1`duF2SJX4<aNbq*$94*ASE|>ofHzfYl@?xHQ!{>s?rQbITqvzk>vv<m
zYSoTs0IXBL5Q0{N+MmiI8`V8bh%~9^gaLO$-JK88toEbFU5h%A9_u&N?bWc*s@BrM
zg*NqyQ4FwCJ##8Nyro{@NbAqr>QQ&d^sDE+1>FPcOVdE^tHY-O|4<$MAw(XjrSz~L
zQoqdrZ&>}L0hS)Cm$0E`M15`nTI1>*3V=+gPt60FR2S3895qh+Fl;Bykwwtrtcl+P
z^ZPZ8Lm)01^-oXX{&UrQP6xA(Y3?qAn&X;T1-OqqHP5Voc`r>Yoo4dZ1m(e!kEWN-
z&iHC(Q2~peMoXawf6a87*%O+fXCZk~V+#f^K=Tc4djmCLv=<K2B++r_QyNE_$`H*A
zx-L#@GE3?E*Jm_0DY_A=SxJkYFpa|<w8Awm^t_4EH244*ty!H1UW`UW!RJ`b$Q?Ku
zr+J=YO7WU_Drh{b(Uf9L37Vh^h$Lz%(*Q`)oR<ThtZ_I4UW%q@0a~e=#P=a`PP3ju
zjrKH6kOP?Mn!GkRm7xj$1a`AEGwJ5a)wI^4m8Wt03gm*uFa@3YnlE>vRiMf50<KV#
z{wF4(NYh9$tYXdAA3^Cw&8)|eyrjvbICF{S6Hho=s&S;!fHKW8TKAS~e)$_ySz*`w
z^A!-6H94-3xuTKLF6pXf-<QBwYNlJzs?xks2i`T!2Ks1MttLMVq*-J80{*sWZq3B#
zZ)$#~LW5S#z`qz;n`V$or`k1(Z=uzx5&r<*Elnxq=x%Gc<l!C7a}?_6(%8RP1=_7C
zp;K->n&5i?-qkES07S1QmXZX0nuSN;aKC06EnWsRy)>8iH7#`B<AElE^5BD-2bZDr
zp(ersu07HWc%U_;SwL&?VNL&Un3)lcl<v4u%`5bh7}Mx>gEy}Ez)sbB6PhFrMmVY2
zvk$tTXbS%YanQ181?Q;!mqHg#+O=ljowc`j0=Qp0M1e~eZBjS9aMgZx7fKIkoBx9M
z2em<Tl^xP%1whhGJ4ERVcdh>#cyUY{`xvT^Yd@Wh0eWipZKLWEFKr=h^}Mw<3Pt;9
zN2s#FUt8UR!JN=;2?p<^_6`@i1GG<5!Xr?-0(t4_LE5P_Yp1j<3Va4@HFQ&kXt%!$
zEoZbj6t)f32KPZEOq)vC^l)v%dcY&JpDu^_NbSr>iho9FgK60vtz8fSH8I-uzo8~p
z8~i2^aoVV9P!q4+MMoAAv=$F^CTe%k1Se@r*FjCP)|Ji}rD*5s&^o7mcMg=LY3r-u
zMY{Gz7L;XZ4`e|kQ#+I5d0E=7+h}EL)v#xuo}*ntX{KDQvIWzYr#&P^>w@;yYD{Uq
zHkJi#1=>TjY%kRA6T?J__8muvlxjDWfLEq%r#rn|J3<xl722w4n5Qe+33}~c)p}8B
zX{B~f19;WiOcCHU+OMgUs8;*sJ@D*x+6>x&UDv)}0$_vId<AwJwQ4%A+@$><3u;=l
zAG`_PO>L_cgK5=1H5Gt1?J0`nwQCgx0CZ^cUIU<0`{F;4yse#f0+M&MkEoQrORKvM
zUbps#R(R2)^`{m6U2RG($UVDuI$aUH+Wy~QsZVR5G}V2rdp(ps&_-W@nn7)}25KH^
zr&0;VBW?99@P@Qqv;%sq{f$yzBibA)X&BXh{SHLNv~SDNIj((Y6I4IZwiZLuL1$V5
z;;8dkfKDe}uNdAt>+Eakp}k-Cx-ZPT>J%?R=74TiAjm=8yZ0e_NO!jt#7*}~G$fDe
zUhajYyUv#?FFkbY<nZvA?s^VHj_Wv-!SdAEx&imnc~d&gTeqqXB7VB9@#yr|y+>7l
zCv;orT05zG-cGN|0A1#M^aknv_5|XTF0BA0Sl3Kp)YG~~3Jsmnv1>3hp}JW|F!^D+
zbKk&xxNi4#sEN>hz6`u59hVLzMeCfV!(fc=ReCqZ>SlODBu+QN1TJ3JK~MJtT`s-p
z5_KMjss1HNw~<zr$vW4I7-5Pokmf5*_tXC{>*=~@KZTkMUEgv{aHei6iDc>A-UB{c
z7fN=|>wXA<hdDZJ8c4400F@Hu>8|yFcR{y(1kU8^T*5&Lbh$_2VWF;?O3I6LL8-L=
zE7o0K3+6@Ljn81>lFp4Ht);r(FT(FKT@L-C<+|>V;An;J71~5!*8NrtHCJ?!Fz~MG
z1cw2y)Fm+Bc9m`pMO?1w8c|$5y;|o&5!xEvl%JrpR@Y1G$2#2uDjd76o40!k?!S87
zqypYF=;~-6)~Hjhf|@4XeId->(7m`0q**7T%G#Sc3B@s6b(56#Y}4f}2CrS0Oc|CA
zT@1aPI(6%7F#20MkM-c)*3G4=k~_M72H;(~lE+Zpt(!+>RXw_*PvN%xu8wgUh<iG>
z9t^El*H(evKHZJ^ApN>mXh|@j+r1uY9_XTP130LAW*^i%)G3VM4eO>;vg)z!trCzC
zUBg+BQQaYW$&BfKr^oZSuGj~vCv^Q3;+)jIPA{h?x*mF#IN0?a8!#qEefFo2ankQR
z4TQ6PJ>7Ww^-^buy6C%SqtjI%m<hxIJ?AXUAJnHF1@Dl4as#|~(?3gx><;TM4*_>X
zKl@X(j_QBS0nS|?7m1dKK9qJ&$Mjva(LAodZ-7}(y}g6twqE*5T9tb1-;RObKKdhF
zX!+`cu0xxjK9qiYf4v8tcsQZIPI=*z`dC_o2k1|f0T8Hf)WM4&{fASb`;@-%Ux)<j
zKj{S^L_awQ5~{x|f%jqh35rUF>pd31`v`rYodQOYdff`BiPArN9xg`fN8ba9(J!72
z^RfD+6fuq0e?gD5v--cHK@#*4w6RFhk5eQ)RX?&B&YaW#OMCY;z4;NmNY}f*3xgT@
ziVE;D_1?7U&(gQrp)6bfa|Z04*9YIB_g{`ahzD)C`ra?$X`cS`zrnnquL=Y&U;j-m
zlose8(59tOKjRNb7U|D?1X8S*mB7SB{UEKRF6j+Z058!?=n5*;zkURyO#ezBB+K=c
zbOl!EkDP<f%X-JF09?`UOrZ1cSM{w_`&+5kTQF@^`W0h9T+{FV8m(%*`$H(L(O;r0
zX084NtyJsuA3K9w*MCBhfO@^M29_H13t1Rwqdq(UttNfKR^V>vMOF;ES^pBPkX!Ue
zr$FSUKK=x}Xw@%c&A|QFrnj$wns&V}<?1^0c@r3Dr~W+(pxn}X&H(<l{_t!7@914V
zM`xG*%S^Po^;Mp5v`4@6Lk#Awe(hV3yr&nLpru#;C7ny_)4%j8-0s&GFM+`UJ+mLJ
z`+CRAXg$#X<^V(XLH*f$XnUx?)(M9n>4z794C(W4V}!$c{c0E-)i=;NpfUYd|3LS+
ze!(e_2|fD+Oib#RP&LgHeex?%>R|ZF4V{jL-zj(NWQceL9y%LpsKREy!HFJME{3n}
z1MX@F`w4Czup3@=g6Kg*@)&v#8GPu%a5IEa!t$`8t`>+RhD14ZA2o<5M(J)a)5Ydt
zV0;CUV}>17@bI|d&%LngX<*W$+sp9Q4jA+{Tn@tseGE@1{o!k1(aXipQ04#&{)T%`
zV@M|q_W4u@cG4iAXljrlovLX<3|1~WPaA%twe1<hk_6}uHI&f9B+T$VRZ@i;yeZTY
zVep}cU!;LaH91j+C3j&W+HitW&oPGS+o2`aa8L$+;|yo%_Ki2Jiv#bhVd@MxnqYXr
zeiZmb!@dfbNHQ?TAewCWn+2H^!`HN%Of_t#6!1Ai28B`63?Dy-&U8Z~g#a=P1~xh~
z4T>h%%`${+Kxek$H!c9@4evF<ryPTSC@ka}5?%)`&k#bNu)AOwrr349p=<%Y{|XF^
zK2TF=SX&Bak>M>7I*ScVic?=StbP@KUoxDc8kG{m^!FiBYWQv?@MVU`yKuDJz@pmS
z3WJ4etS=kb{s3Gt{Ev1(R}Ix-kV?ZFHn>)0VC;cw*9^6P08nk{W6=Ju#_-N!sHrvF
zqr0Qd@H;K{uNw{t0jxJXm<C>hAvXy4M#J5;aJ0$r$42m44L6>^QoG^vbMUFdFyR7T
zr=gW@qg#ecv>m%`IQA4Ay<-@qRbiJQT8WW$8~Vq<>oI&Rq5R)~fgcYw4-7eU<qsO}
z+y~;JVRI^Eh7CL2Fs8?b7zz-N7$RtaF>07k=En>ICy0z2F7%@{Vffn@yh#I>R@hGr
zyXcwiU<{)vaWvLbB*4kIaR8mp#@+P44EGz?bz(?%7o#i{4!at4*FX*!FH+^oLF3Hn
zaQKkXpLQE=M)3z2+F_%=7jz#nPEo^|qek&|=yo?=r!p81<4aVIa?JQ66P?G6!WIxu
zqlPXBFJnI?i@lBGSJCNX+)Dc)U*mf-;gg@;7%T<e-*|itOq?*jbqnOAaRCi2z{sE^
zcc4)d4}(F*8IwSqGPc*jQn2yCec(cj6BZ~vZA|+c<cx9Q7IcOhNB`S&7(dgZ6>f}*
z!Hh;2e<}k!(pdI1I-`u4BB+iw+EZ6!pfSd;z6XglhAf1qaYp~&K;n%L-heY_jrnwM
zCm5G7;ZvgVjyLd0M(>Z&nQVN97Jw;6SE|)YHA>Hdch0zR6?kdJY3bml8>?v*n_*mM
zfft#^qvz4eGB$sYNys+Nw^P_E*EnASl4n%?1?B~#jt4dQ#xbhqE-<b?fYBEkr&396
zkujS#(Z$A|%@Db0ba2EdE*XdDbWe$Kl+rGx#)x5vlo_|vQIc|_$%v6v7~`mB|FY3Q
zHQ`r`^InF(SB=|Vvjbmg)KIg^xOFxRUNio@1HM%oSpjI(7#A%8qSlzu4N_+;%!Qik
zMl;nZ)El|9=V>s;9Rjb>IPD~~G#NALXvYoXw;d2^Hg?f>FItSJ%$SRtMyCRZv>FSw
z5NR`dHq!Z{c4Ic>Mmmg9=`h%7e3@PycZ|^txYlJHBJ<tGdvn3-G0vl~@m*sw)dk-(
z-U@}Iy++kdDD5*ctPtrpt}et}3>afCqjlftN+(bs7`y2>!k}?r5p+H@PFewfWL&n3
z)}KShfA3(1hK=nJQ1jS$W;#Sij3MOdsL_K$(PPFJsCHxAC{2LU31eIvyqGi&$RPQ|
z7)2>-2h%C48geuZ1*6l+6tEZ~&ZfWU(<S>&KF>j!i>V$@nCY&jng7Cz115<hI_(Ed
zK}n#8OnW!NlAEc7QU-@j0t(+AG2L*4nxm#bDtB-<eZB%M4^zrL7(8auxWLkJQ~e&m
zJx$9U0Pr&XG6>z?Cf`B)Fg~V}Lg0K&*+Y=@H+6Uce!?{CJ&2q%ZI^==U^ktl4QHT<
zp8*nND(!=|Q>L=7!3;LJM*$IHT1=meIBjaFK<63L3tM15)Z`P3&M?ykik5|&c$AQe
zFfF8NiAdAeQP2`)Iw6Nhv?=Hmw8WX#eFD4jrspW{c-C|?5dJ2Z>}m5MlW3};lG-HG
zU+3XzvWZEhlPRVVU&y4Io*{g?Y1MH6GfWu)n4nBk+GR+dH#yLzGRL$s53c2!{+JD3
zp6OY-jxU&8e?lwYw1?)fz_f=#vxTOtEbxj<w<rKvY+7Weu*OA`2Nh3TG9?_rU`kB$
zrhr*$@}z?vWhSQp*ey4`+5=Ky8m)!h%cdw=;9oI0r=oS$w3$BbR%v?YY2d0%ZPP)n
znGTo%s5U7nY+GY`bpWke(+J&^b*8T<Wp>?kf=$cOdehvk(AHo|{0Xf_QyCS5H<^~L
z1i4}2Z-r~krsY(!(qgKiUCK?<*Hj(SYU=n1fHu<_5lFi!bU&1Km>3MqTBoUdGsrE|
zj^6;dZ8}0Z=R2nJl*H^ZEfC<R=r;8|q3@sdm^g2t_pWIU>cOVpGmZU#R<CJ(6nyG4
znVtf^-*lP*g9D~{Vvzf$8hXM!Fomzdum?@g&;sG1X}S~U;*seIy+DRcCn&EpY})=U
z>^?S$jKGbU1}I24YWnPJjBL!b!$Rl(#!VlJpk~6fh_aBArgGYHJu#i6G7ATDTsyQm
zn=h3DxZm7OrwLum49beTnj>_OJYcTopmorkNM)dh%)e6B#?72Zd*Q?8pXkAM#LP{=
z%p5hpyAnRRn|tr0<za58MV9@Txu+Luj+>kIL)6pkI0H;C^M+t3^)`S064dyZUwQ-)
zU-J=K^7)xr^I*c?ETt^u33KFOv`(7$)1xrJJhBI!f#&q5feSLn(8}$Uxr?$)!R9&%
zL_*9n>1R4^o=N+@Gj{XQ5jYiU7X1(A!^~B5SB0C+cc3)FT$KcTq*+Z%nJBYy1c+#}
zbT4>uX2x*<;?2K&kC{Dd_NQQ9g8B48%weKAXB8YxGT)ew5hk0{ywOTAuP#I@)%@*T
z*h@3-*@ez@vwiyC@GZj}&Hyme{0|k%W|?<4!o+#=FOxvznB&rb$Td$dg84l28=rx9
z!Mr8`xP0?E3PKf`W$PhQY<}h(lwLG%q_pKF^R`21m6&^}Dy-Ce?hTMK^YCkMyWHHv
zfxi{z59}K-w9Dp&zQA8GJH8HsSIvK}1hCS4m+pfq^XH>5am{S$1isqre+7UV^Osa8
zP-}jbB<sw37s9pc<_UTj)SFv=N2|fSomN?m=C9v}NR!#`6R5sne(oHUHJklq;I)`b
zmecz4raAR7l(w1|{Rn)U`7srac9`KW?jv)=UXVNHZKr_mG9ROgrf#!$KJYzeSK7AT
zH6QVSmV4$3N=EjYI~JqWXWoAUxPJ4pDF6(Zm(lL^zIm!A+<stAYJ##y=EQW`{|%WB
z&;f>F^FF$9ADgpY1AfHpPeU6uU;GU}%$PafjJX&$AE!c+3G=;=pnKBXyd91{F-s`W
z<X{Q73F2glc@74hE#F=QV87+`5JX%o8@2-AYWZ^)EF7>L{qG2xrCvh$zvGssCdhbN
z=KTs8FUyy4Fz9VzXTrRX#q|X!^|#ESH0=q?gImC#w0ulikN`{9Ab5e6ay=x2EYTBa
zow9tI2=9X}S#$<0#KNb%<7rD8tp(0l7TiKB)Uv)9TEZ-U(5VD_xFx>}y%82aO4KA;
z7!QC?vhc?+mnoL5H!+x0i`(zecFy8V#Q<rR?_Y+cbc<*PNQUL)+t8h9+4($_W?3@t
zU=Z1sMHD7GZ!!E0ksM1NRoLWOD%cRov)raw-vvwf3y{pWTUJtRw!ku%);EQgIkf30
zvh1cEW3i>d7rHN6a<)UwB}){A$4e}Av<4})#K(YFX6bbSyxel=40sh5!9Li%Y`H!k
zy02JvP`3A~#d#E+m6k1(V5zbMk)zivOD7;wZLv$}p<81qECjRGGO-N4)mctbYUR2`
zJQuur3zs%K4VIV*v>Gkd{g7<3yg^~#7E2MW?rvIYE793%DgPcKZI-|NF^BCIx5IF)
z!}9c8kWPzZCOU6flK+MGw=Ere(0RwQ#_oWr>9PdU2D{r5OAneJOE(APu4U0Jbl$T>
zQvqhLB~bx`eHLaE4E9?}9>UUqrI=Ei_bp2oVxSK!|1QMUIcWLF5uFb$j7Gp8S@xRY
z{gCA<B`k(5ojbsLY<c~4crjvm=Q+y%jatrK!Fb0k-^>JJ-0~HDvv$I=c?x)wmY+62
z^ob?Y0HA|4j>`2Mt>043u#@%szaipmHT(tKeyibcbh=nyv_izyx=aiY4_L!}(dlMw
zr4M5rwq~@!izC*Lz5?#3b<=68KXbRPbAhObHH3EU$E>f>0kPxOW{RzPS|{lK^|C%i
z@m_E1+7Hm_V|}(027Rs1P>#;e`rasb{?@m@hubHtvuzm5No)2wbOu;2EddF%deUzn
zWIaapE2pf#Q7kvux;TvT4<XhZPpCO<E!qh$&RBcjg2SO!Ry=@VR@W{d!mWW6!;Y{@
zl3_Q}s;0b0l+{Yh-)QT3iV($Ek5D>2)|#~nopIK*jqoDg>KF>ivsSNHU?IWEI|J2;
zR=+}+PqOZz)RjHiIzm5Jigkci2&vX#+RUD_+Ib*p*2;7M)2*gApgY4l+J??dtN&|g
zWm#Q&fzP(SNHqoLt+|`wT8?%3Qi$YQH`0%uXT3y)xfiT!tZ*jZYSsZzV0~dB%oke!
zqUCRq-5N$O$71W?81NUZPk#<_$@&t-w@a+wnb9h>)&)bf%z7^Z+RClZQ2ASh^(#8H
zb=i7$FU(h3$1kB(ZRPEPi5lxG6iTkOmeD$)&MIKS;C1Vc5X@7(HDd_&8mtaKKue?5
zzU~g1P1YG(Vd93hinh(o);Ky%(PB;SgUn6q6ndDnTBE55q0P$P4K?l7qJxm^u&$@L
zX{YrhMG0<MMc+W#Z7YLj_Kx+yVtCPIt)o;<w>97!0D7!%MS|S5ZhivEdseHR{>f~w
z)hiro`mDNic+qdwJHX(8)y{&Y`&Q=j5P4v|IgZw#wT>P;53S|bfPZ9lE<|g{>PsQ)
zVe7Ze(EZq2Pt`vo)~8<rZ`3NAgt9T~1qx%1TfLrzg$ZjbeaUCi%B!dM-xF&RZBZR;
z9aLrIXnTb!y`5~028_wY);J5=Ty5&bAO~#wzXIT(ZAT?|hir2KLELQ5(*EtJjrkbF
z-S#q_lk~79+yl?kwv#S-FWZ;%(DJtZ^c7~*$F?>K%6x6h$LRc#pKW&nm?v#QTK)#u
zDksqjv=uf$Taaz`I<!vNzNN~9U|ZHA=nk<hr2WNd+hJNxp0PR513lC>K;Lu=v-PaT
z(86tFA3`L;7Q%x_r0vxUXhqo+6!MR@6{{c_1494*HrAF}1*LJe&tApo<83>;fj?_|
zo9?j$o2Ur76Kxqc(Mq!IcoEu?ZE-t6Qf%);1D9&cq219r+jDQ=Doe91rJpd}ww2zZ
z8MXy937Iyb4I){#ziH)`ZL6l3`FWd=)`9jMTUP=GnrmA*AH8`tWhW39Y@c+4<lC0}
zf)v;`NI?p1f78RH$o4lq(u!>Zp6I-2TU-X$F4@-gptHobVJU`IYU`rcNttc445Zxl
z#(yCIo1G#{mu<gNLDLnRm~MxwcH2D){Z-l=+d!&p-Z$aQHQWErfLU!D`xPc?Y%Ny-
zthG%~!_ew%Qz*cE-PX_rk$PLgb?_Q&lN3X4v|YUcc$4j`DmZh)Hl6PKW?RNSxZP?S
zrBz{@?K0&E+W*hdb;o5{eQ`@kE7P>JtSmEEKU=m<E1NdVOy0fs-Y+(_7jdxn6cLpn
zARt3PL<MBK5J5yhKp6_i5>Qaq?|b^|e9pON-TOYz9p{|;yv{ZBHM2Hn$0rn-Zg+l}
z=D-f;nk$gM?OZ(*V{ym%J^Cp+otsH_m-D}sP}A*vk&2Y>IxjRqpvU?1m!YlKIl}~P
zea?TxKv}=DgyP!+&Q8xk**#~!jc{hrS$rB`$XP-~Jj2c&^a-x}&T}19z3{;K1f}do
zoKt978g+g;1zmgS{5KWIKXU$?0-s~fC;A{b?%dl5&I#uTdR8Z$tsZEba{h7>a;^*%
z`{Mm!M9qS~Zj7^8VA;i(paaQnMg)z;9>%6F*xk$cg9~NujFl}EfAL_Pp(n|cv3dn0
zycka%N2536?8|8LVO*l9nJ;7Z2e9PFSRM-#{*1kp6%Sxcr+cM=jKAqiGeL}dFTzqV
z;~vGLLKp^$h=npr#y|{X*owdz&e%w`yAg~U37px-*y%y_XOWB!Dzo3uNSuO16k{GO
zss|X1r7#%HsAvOrkn#CiICF^c@d*$QGlJrvEr#(^B-F$*swf+Hgz<=?8wrfn6ByA%
zh8z9b$qZfs+EN&Y9|K5b?4&s`o#9U_dj?}VVg?SUOorn%P>(Y{q?2YAV>3-@*^HcX
za3+^AaTg<VlJV_t!15SB&W6ELjP-N|IL(Nmbj=w?CT#%o8CuH!6)<l6SD(xHm*&^A
zjI8hAb`hhO>Y$4mRaC88!Z<;P?o!5wO0YP}7#o_=SkCy4!oC%ZrtN4v$LPNU-RBv?
z(~!Twkkcb{k@4z}XuHHXK$-7K29xR<FEhHnL0c7Lst>)t!g#C>ov3EG&qNPv7_aES
za+T3lgSJ{me<Xg2Ym5|%@YFHl=!*Mw2cwcQclC@jbUtZdsOS@;jf~G|dv$~Hd;tWT
z7@f5FXl5KR0<<vt=()Pd$cRH*8zVXf-nTOfXl?9Z<Sm8L+l;ZF0q!ug;qbnb@g|*)
zx)?)j5W5*(<kMZoU!8EYhv7K?8qi)w#cqH;#$RLTc0c1dDs!C%80XK!wR?=|p|Cs1
z=%6dQLyX_P0p~E|DLM<^XGGB5qz4QQMQ=wKrN2YzDEx)^L&o|ra6V$3OGMik;}s25
zk29X9L&F4P#;;I4$=K$gVy&Ib8?9h<W3Imru#5RORoLxi&TU6W-I-JCq11ypc?c4o
z%)9SFw-<8>W%Iq6&r@W}hdG@#HonXx`Wn3-^S5UJ{Fx62K@4EZDe)J`WXy%#Am&yp
ze&t|h*I)1{gxR=^-oH@hyER}9V}|YmHJn-J0uaGmKvVcWW-bdLlF7Oag9n(eZ-)73
z=8!j(9%NQi(b6HNh|Xw-nL>)V#4tI}prf(OFPIRBV@{*fZ#>iO7+8)lYu-Qy6PV7m
za3+yCl=lSQza-|!Tc93gu3rWDWaixvfE4C7+J>ewjc>uyF=i^|2-2ASR1=rZ-2OQ{
z%wU#NY$ucX>0@X+&TOa6dlqx;POxM%7bZb2hlwQ_%Mo)19RqWj?86|QWFDbH<UFPV
z(RGK@Ddq@e!cH@DsM_}o(<K}{`OJ}eI9$LSp@TsobG;TUXPNH)AQmydrzk@)GfxFI
zCCujr(a}=oV;SHqW5#?BOXbYwd|(yKaLS6GV?Nyi)#sTDenHzMW*~)htC-sgq0@1N
zSxS{y)l3Dg05wdb0)khW`QO1rEpvty#B0m}8m~HL=!+m;XHInDN2_Ok_AT0OFb~li
z*Tjsas-tEmlQOF<%!rpkyve*Y0rR(*>(jy6%KYCiU}<A+<U>n4b9fX#OoxNn;0@iK
z%sC$d?P504wyvAWrtEkx^HVRh^)V-c;BY_F<N<AiOn-{b4>1c~1{h{;-vG`Lrr|i0
zjxw*$ftH8N-}>O;ICG*LZ4=D%6hxY2-ql0dPL`PsEp9A}2b|f(a=dVpo^_UU4aU-)
zHR6g9@?d@K4a}P*p~`k2))r3)`m)}i4TAwJZ3M7D*3%1MFo^Z!2-JkK$`*k$jKz8m
zy2DwXG}}h9;`M0T&tmjISrjXAFTg=oZ61h+SmX5Q9A^1CegbP8Yc{2x<5`O-gMEax
z`$_a7iS=PEu%oQ4Vt{1UIx5UP#^O!Fi!|1-Kip1do$&&8oE7f^pR!m}uR=>U>!}qG
z$YqJ>V%SO6(`x|oSmgusbg};W?<mgNo&seBth#8Lii=pwvw;?~YF5C-5>^>y(8^hb
z6ke}j?K}Wy&andiyCT7o(CvU))|@{eca8Nf&GL1upWNuVU~Q+Dxt>)L4&n`#)){u2
zSQQlRYGySfgYDG9x<QGOo2-*-;O{Ngxq8}vwzB@Bs7xE{Z`wq(voyJo?_k~k8|H7b
zKHdxL4y*cO$ak@pUj)|8N;iY^F3a!*?Dnw!wnJ$z>rXFqyPvh5YOV%YY^vwD$J%ff
zss~x0(z$bpRZSI)!>ns`NE%_y#fi(|G|E~x1f>sI%jujw&T6ACJ5I1FMKCzYN?L+m
zxUyfMebG+#zE$wajr}j>RCcikKSSGY_Sgn`g4p}$;*mRhF)j2S?5E!c@MLe#hB7a9
z_ZN`!W^bMb%!ln30e^kj^Oi&0;m7`)$|L>Rn*#v?*zxbfi$L~UAAu)`y>1;W1+#B)
zAsE8G`ZS24>;*UBS{U1S40glWcO(E2>|2!m+{a$O0Bw=%-Fv`!fE`QEOf-AjRhU1>
z&Z1;U4BLgmud!_7T*$>a*wdE7(**X)?_epBJs1Z0B=#I5w57109Yk9yyJZ!+c8s0$
zA=G5B2R6d*Om@vds5#Dljgo9R?94{UonQxj4K2Cs6q<cbv3;`8cA9<d5CqP!-7kTq
zko^?J<<7FV{|aY{*pBZhE>X%pOX0mTc0RrL<?N9QV69*`Rl$pM?Djbzo@X-+aOML0
z6*IJ5WEasZeu<qK4NH~m7OEn>%=Y{m%BtA!FyTct`v(o$YS`?jAa|7=PHC-L_Khb2
zuCdQh6t#}M$f1Vdb@uRXur{z4lNXI_m&YN0gFTxCFPhl(l>TUDAEba@3)_>9YB$-w
zU&8z?_NyD<Oe=d)COX>2_G*PdJNtL)ZwLFbFF+@I^{W6~Y;XFIS2sJw8Qtz>cThaA
zkNrX?o&WmTpF99{fbB}#!h3A{N`OIjIh897v7cEEmSOgD58=gq_R=3fe86^D2!Rpy
zf{y`4*<Vr7;Y0Qvx}o@p9jOI2#$MzEyW?!b6u<=g`y=pvlKt}zfGM^g75KPvUKLXP
z=T1&-6FTF@nMGB%yExB2gT~#QBsxm$;aq<Tp6=ziKZQ1Tj_0$`=E3=!ejiWH%R&Gz
zPVokCdUIZ;D`-BP`8n{yms3LNdq0kj7Bzp)ESjzYIOi_FwLs3)9DpFsKr{XSdoU;A
z26#d^wtPs0a=hLF2;*!?gqm>95A$F*f-^J$mVF%dLJUGA$153j_j7jr3pG)kB&z;7
zz?nwtS2U-Wg8@3oxv~VrLmcIQpC{p5`4Md~oVza28OuqelWiPl+Hqixc#eUd*(01g
z27m-k)*CR9$Z?}-D~a>*Cj78RIZtz7Fqu;{AH)<+aRZ2{oWI{ipN?^!$%pPVP9sH3
z(m8pX;co`#@Asf3le2&pkmDQ)9l5eNE}qbGg40inOD;$D2f#@O$CvIc=5gMjN%s`z
zl{0YvG-uv6XgkBf4Q%WMIC*o?(E?5yy?BKjO%XWHa=drK-y+U%4wM#il5m!GD&eet
z0xYE*RW7uYah|vb@p8_EY?!a$_)|>i97i&Rw)31?stmfoar{NqvllrpID_>Pry&!d
zl4Gj^@iJ$J0CuZ5k0_~lh4Z!>B&s<*elTCdso#XIUFDeQ99GNOR|DcTPCK1<>o_|f
zq3t?n6FnF8oKza82F^1pp{$W}nL_<HIL~f_p(YN#zXYdla{5i+xy5;lvLLOTi*&AO
z<D92zn0C%@`(dJk^ByJcZ*y1=q4W+%z6_k59JeRY*2USe3!L4Y=MR8*m$PU!h&`On
zpTXJ7`I>G#^l`c=T-DF{l+rB&oUr%c#XXMEoz}lW&R<*M_Yg-<snKChd?tE-pHmYA
z*B)@Dc0*!>v;P)69OYC{h0jCI%aluf#A%}H*D+4F9z#0Lxxj|p1n1~y&^gHwz6LPG
z2}}WtEB7n<?RIkggW!`JcP0JiyST@GrS)$&mq9hWd$=1vhVH%G747JSJ2#Ln&3JG>
zqJXU@cWnSLFRoDzd2en;Iplq~et8h^<)($gk{>s@6I%SaZ*2fEfXmv1{swaYq+E3n
z_w`<|1atq{fG&k_KTiisDED<-xOF&%arx`f7|xwTVZ{jUKgZzdKCTlL5k+!Kgy_?L
zZYY%&L~&ibVB!GRTL|6JTrS0S4sti6jMV86S4y?rhq-LZiNtW5eghWEy|NK3aol6m
z0phu(RH%A{Tiy?43EZ`_p~Z2OYowa1WUiLVS5vra{oq>~_tq?QJDr>SE*#F_{_i0`
zE_XZ@ET_1u7DLTx?hZ<{oZ+rL3y{zKnF7-V+-uZU$X)n9=se3UUkXsfT}78vi@AC_
zK$UWzrSi8j?voecVY!1Fat!hn+ywfl#W}7Y#oW(xpV<WLBKM<FuwLTscc6!rTtNlQ
zU*_s>qOFR{NP_!UxHl*<Tg|;kxs4jG=WcZLD!1K^wp#AV?_lB@_m@2osN;$$4}P8d
z8GVzco;x-V${M(iF)AZ%<Zj&x6F0aMWpKZV>rN%!&D=DqlxyKGqW!{6?%p^ky~TZ#
zV$iMJNA$zCamy)x-p>6v4VF5%pU~FnHkV6>$vfPs!;tIb?(zX=7dM?wPCeYpVd(7T
z7A1hQkIQz{1NL(}<Kf!?_p2OeyT?^e0UP8#K_v-8+{P(L40HV`uy&s-t^)A^_gf}d
zM!4_Kf={E|=c%UkAvc&R_#bhL-oqe_al@VkahzM;1L6dChd&HWa<6&-OmP>GxGT^4
zg98S4@jm!(C&hbHjb~>M??YO}_wrh1qs^T+)Cv<GyiQuoJ$aQh!FlnPd<vhudDSan
z$%j`)ITc^tF-l1J@xEFMIe%Un)$#=J`UfEp$a~>MhzId@j6yD$7tI9-;pKis-#-iG
zJwu^@Fy2;rJHmNZ%D+eOoIi!cJ|3HnDUrN?|GQPhTTh{|C|($yOAhd!psIyKy#8>w
zeVDhAKCl|YdyLX)@w@|n0vzGp`vTr4@U~@O@Q(5-lE9M8+aQKq3U8o`zCW18TU7^Y
zI&TwwLLq~9ct84-#dD?fe>P8-jN#7VeK-PxxjfU8uym3)`3&Uqcu&!dlv6wz9TQIT
zlGZ{?KCfsA+6s6(j{z&>oe-cCMLbUmu@v)MR>6xBUI#_XN_h$@k#UsqCg|s?;3d}p
zJ;!@V4TsP3qN8E=BG1ADc8RB42Ej_+-4=k$yj`22w2IeGxxs4Q<S;mEcw-iDUgd3T
zgtA)ROO!gk#w(&Aa2+q_YY-cFMk;D)<XxaC_y+H7I&n2Qc->^TnfE&#VOn^?Xh_`T
zeL$D$Z}EmHRnf}3M%$Hco{hF{cX>O`0rc?RAAy=)-m)&p_3>16FdyK#&4O$9c-LP6
zHpmkl$H)xx<_AN3gg1jO2aWQ2XlZ`P^Py<-Bc9^|eIsp*C(A<PIM0tx?Grrq6tGEN
z5fzS3@uH|u!Il3cZT@%i&Cfx=jeo)!*j|1otx@j$hR;Ft;78C?;>llkAL3qokq<qj
z{6mz)^x+@shh1O3GsVpP`1g*&`(S>z<5j>AzU3u!G?dSugtjn#e;Xvi`JXjFX$1cX
zx;nm(A3!IWNdDWDQr*wLLFdLp{99=-ahT6p0}#XSISsq9{JXU7#_>DptQ5~z(~EP2
z|8o;8B=A=&0TTI7w4rCI{9nrG{X522Q7S2o-~KcVrt>pCgZT`;j|t9X^7VAr?l`})
z0)kom_BJTZ=J!m4!Cd}^nb3WbKYt!T9{<^Fw4LI&tbvx({5e#FcZUDVPax*=efEN-
zfIovufD8HiZ$jBw{=jP5e-`m)(7CmkpZfsR3Vtv}h|lp|7?3~DS09CI7x;x#2Yr!$
z2EVh@CH`$ni&gSJp~{5I{28=XRPirgfKRpj#1&9>jbBs^VjX|&5-7XQPneGW*7IAt
zptFJBOx2N%{H2#@{ky@pmcv97-<^_Wt^C)&grzoqAl;>G=g;$owhsRL=K*f>TYmw#
z!_RMk7oGfTB7iP_554f+{O?BKOh13M7{md-E9Elp@x2bg(jfl_3eOGkuRnm>!~9A5
zK)`+e%bURIc)(9t4miShqQ&tM|I(Ad#`ww<_%zNJ(uZy)_{<NWZIb`~GO$eXD=F9J
zD)^HkmOBL%w3BiZ=$-}3E&)RT-Ma<B^vRSx0u9yccnP?1z`O-*l%Dbt{7ffIU%^(2
zD*8DDuOO!7<S)4QB}OPfaNiFO2MT^~!dL_eE_@7w;eua}K`=rvkDl3mg24o6ixkvR
zdE$P-7=^o{1mCFO(*eO&IuS$*8tKaGL4oh*=tP{rmma-%!O!&Q9TBXcM=wF}2gT(Q
z1&-%#K|V>)uK+kI2)hn7$pRmmc2WeYThNvv5UJrsrr=l@96m0v-vu#CQ2q*>$rgO`
z5SDTTo)oz_Ay_GZmRv!tCv=|__)r}Gw7`}O@iT(X9$@(be>wvc2nugQpinTwaRBmX
z1uHz@X_4SBx};YuC|?3lBIqoDiBdu0DoB(GTqw*|F6jFK;G&?)2;wDyqYi2+1%IEz
z09_VXMX*#QP|?ofieMV0AFBmT0$8XKxYC!yt_z-~Qq6jS$sH^Wf+ZF@{Wc2NGO*qd
zto{+&ngqWLqp?|#^9}@C1a``av<vQ2CaOd5_BIf23m&8U;CBRm{{!e0T+D>hE<ptC
zLAnL(5{TawO#TEgAc&>Pk$ZyUc-EZ;1%X2VLxSm)TNoC6#HRX}`+_fb!HWli1+<A6
z5gfP#HID=?6#f|##JmkKE~uLZOA~_a6xW*+ocRiaFePvn!Y6m(_j_T&LwNrv#65*)
zC}ZFyylVsS7S5}OxQ{SZ4HjSFbt+u(6ABx_=`VaamhyiA!Yg$^1BC%p2NooJB^dn;
z7J44Xkc0^Tq{winP!a_-;ldATrHv5&`X|)v6aMZFw<Cp23JB~MR?{PYK)8aY*=S)S
zRbCzx&Yua+!@|as&=Mn@E{D!o;cANB#t9G8$;S~doc|<XqA=z~=uQ&OqzB`u@ER@q
z$-*;K&zvG$MxSX-6~01Sw`0P{HfT!|KDZ2!F3foi!<8u<rF(S8g}b%^WC{D1LoQpG
zdI%s#xMelK31MFkI&o6CPXd-a;c^N`o^l8)|Ay|<!YLJWpAo)JafN*0wJ$Kv1;XHS
z@TpMPNB3{f3g4xTT#+!DVsFJlGp$M`!q;LUUMgI42cS&&8l4Txg+f{~DunM*r1hMz
zCKKZ4g^MXje?eG%11uMX7t+CUN$5ECF5Isa&ZgbYW#LVVvR4T=(eG3v%%g18RbdL{
z>S~3K=h1dexRajXI^jmjOI;T}JsZ7f5Z<HBVWTkkHadDksCWp_BwYFu<eG(>RsggJ
ztF_R1OV~xnsa9dwO0cvES2=D1?GP^Yhql|oCn+s=NBGV`IMXTYzXjc0LYHK;bqmY=
z(TlsnGWs-PuP}ZF+WLgPwdhR0@N1g2285|JZQK*C_!}%k!UEbT4-1o?2e>b6r%k{E
z;as}?I3k>+-+olce9nPU7!y{$48d{XsXrh%A<U%o)}&BMS6-)tuTyBqRrKP!z;=pG
zQqixQsCXv?c8Qu=V1Bn~f>yjeqPhFfwpa9NDcamc9#jnOA^M1-44xthg%iC*{aJVd
zy+y}qq4g2HwVv{SzM_}zK+sS0J;i<eMHeaA93Tp(OKX9m2k!#}iT)>tnqX0q9sY)h
zvgunzp`v|1z(km6(;+Ag7ya=Ph!G+ST}ay}O6|j_M~Z$r1+ZVVcLq44L^~)#bU^g)
zX8_Tn6z^$x{|<^+|7~MMn?Asp92TAOhKU%_RZ7{#iW0owOq{4g2P|GR_8lBOB6^!*
z&<Uc;8^C!~^xJ%xNEYSNDx4zP&w%b!(E?xibW9|ngKnBAU^Y0@MT(8+ONPkZ9a=I)
z%!Sb6I4&A}2*E7TYxI|j*`meWXv`5+P?G$F=zFT=%N32&mhYs<s>QJ7iFUL=+bK~G
z1;0*<X0$`i8BxntwB?JE4d5&gInj}+P;`p!X`K}*-+}i<q9qfMD;E7irEMjmUWz=F
zIz-+fK+8lIsSu=Gr2iT`6`~Uh;l(-8C*x3aUi2EJ^Dc-4RK;^qw2?lma!C}o6y~c$
zd)@}PB3i#1-dBs>dlD=)BF|?4u8OXI2hLj2pQiz?iDF}*rB1ZG35KqVmQbX#UgXeB
z1GPaE_bh(3Mp2>{8gGbhQkg}QXd&efn?(yKw%Q_Eu^64XDOwW+zi)~DS`YbFk(Rzu
z)+Vyh@6#?~N5Jh4QN=b8Z;NUl1LqylmJ?{}7Nt;J?yhJimCy8u8r}d)uc-FF|KIEr
zP0)HYAgZStvwNaD6fzkU&7;dYL!vnPmcXzmr31R}i@x{>YDPpAy^tRj{YA;<hoa?o
z!174cNfC%KkyQh?$3?F%2Fs)<m2y^7qCY9V>?)o{pRslmzqtiI?Giuw+yQjAxMwW{
z_lR}DVBIVB2!OnYIPnaCr#Oi!M!m#rimG^v6KGNO5x0H};45xPfw;f;g92Cz5P!c4
zAW-}*T|f^K7mq?NSbUD2t`PB$6vGM=AEK~PxOl<iXp0b!@aX<glsJ}7lLy4RKL<5h
zERTh62gNJtoN!2dGapK0#2e|@8!KMW4Bc_!S+p6B7k|=>-X9T{T?R2h%(6f{QM`l}
zr=#KwT9cE-ujE2Yig@%s#8bs{9-tG)#Q#P?JYD?nQ&j(%A?~G}W2V@hI(l53NTu3Y
z;zuG3Nw#=v3<Pt;)4zn^NwJa+(Rt!;DS3NJ>`oEd)8fKqkUJx0P>P~J{O5Y~rBJ-)
z1%R{S-G6~tB+h&t28+cnOo!?caW37-FB9*gH`P%tj;7bRLcA{v=s9s5<#*4EXD)=n
z3*y~s$X^oAptxS8I7<oaviM6EU{}N(n)Ry1fe+zmjd(WIuUr+sL2-;)aRgOf)`>+~
z0N2F<lt``@KOoQ`&Y<&OqgcU%y&Dek9x8Kc7JpL--7VrrIyBxC&!8CCEwPqn;#P6o
zcVKN3r%%FChd6sK1a6DxEQPi^;&O`1-4)MY54j%k(tD8W6~`&zMW1++69oFjt{2hm
zd*Yf?P&O#`dJfo-_yG%GSnSCC8*1*0E%d>e2jXhlx{Zi$(XEw-V#`u=^pUudK4vo}
z4qpN=F8<(K5GTYR(bbG8@v1d2=qkBf4-a=r-uM?@xJlM70=7%?Spa&!Tk^mE>bN8e
zLeb_Ssf~sOPsw;NSiB^kIB1{YEs1{*z(<lwXJTK;{a*0+N&Ged_)8>DqZa`ZDW&lP
zC2Ow0wIIm?nizv6Pf;~Yh-7vdI721wJAj2rxD{|MTw>^jYY~#PTd=!Nvfxz^BPAtQ
z(B1u#*ItIbD9Km_#Xk>7Bu4ZpS|WQ9CJstoqCEH^$s%eyEYbXlwiw9~T6be5(=GtS
zNx~|jJ6^(~9oP{`5mme-NX!dhB2n_Z2m(ox#y8;TQOVe9c%Lk}L3Layk_sQFPL*t+
z4f-)jo`KfCG|9X&bS7PLk^TuXL-O`lkjRwW{~bz?OLl$=)+`D8S7<vSSwp$`TuIzd
z;5;eW_y}H{mekyV_!-Gr`U&$Tp`F0aN^DdXStQA)BCTRcBW<b6B!AHISuSa4h0Y2|
zK^%R5{(>ZZIxJn3{I(7zE=k;I!&@cU_CByHlJ_K#ua<DqF*3ChKRWtcll(@DOr7MN
zuVAo2a*XbPHA-$!A=M4Z_7A|)BFRXD_)Q684V2xIcvC>FRpS2u{<cZdr{G1q#E<rP
zjt<->1<!4X%Tjdhj^t!9)O1Q1^qqn(Nm4d=?n<^Nz~LTA*gL>_C1whq^-1Olp{-x?
z4=ow@Bp<6FHz;wZnQcgtF#|e>B`?y6;Jzf{E}VHFnJz=yh$Qw$C>xcGQ~Lg)L(-B8
zo=1{fW*8ikG+%<!aY++B>l2c5l+u}$7%Ra#B^lMD%~krM9p-mRfB6vF+@ybA2g@Gm
zS3xkiS1O~ku)A~#?E^ie`a!7nlwMT>^O9aNg40{-a~zyL(qKE3`AHo|X_w|Nok!ua
z0BIr@mI9?Jy8Rd={hMCnVCnl*M;0QDxd0F<y-P2Ag!GqowC$7rOgoxL>6$tS9FU$K
z2TQbc;|BEQpforE;E?oaDB2E7JLxHjm2Mq_`8er%3SPxa>mA$Cctkq67L5r~JDr&l
zrHTW<lB6rKnmZkpK1Gq`Wa&COyr)Q`XlBZm2GcB^BW>D_wiD8icp&CVWj*NcN$I!W
zLQ9^sLjX&sq-W>C(rM`yI!T<7u5bdDFTE26)dkWdF6}=HrRGqmIV*LdFiw&5uPOLl
zEalT|TOwUa_3EY4bWfNslNvc-DVHWb2e}HVjShw9r2ZXn=DhT!2s{ZFq^tU2;-d89
zK?q!uihcpHQaUFA9$uCTW58J@eXSD2E7JKTwEk5~AI^uGT4^R7sjo>r55m(r=`RBy
zHb^@uIMOIh^n}C>X;1-(P0}RF<26g4yZ}or(hZNnQmgbCDoAXT&Y&92c4-6c<2s}}
zhQWDTI<+6-cch1DEIOr$v<`JiSC`TI*DYQ59_-$g?x5GHN17Q5^Sx5}hZuxDX+EVd
z`=vR}P%|L)r_UVRldho?>Y!8*1*JpMgx_IzSo%dKSnf+#P_5Sk=|C#lMx?tb{WvOJ
zO2hR~I!WJVdL(_N4`57si>|&n#-&#%e>frCK#8SE=~FAw!zt+zDuZ#AeJ_XnPT8_6
z@Y_vRMeo=y*#??lcgxD^VQ`PkpI)`SvapM=>n<z(5kwCepEgpSvd2G#T`yT-Gc0(^
ze(?j*M|P?TL|@r9+TQp%WUF6+r-8DcDWn`E`%Md;VA%*ownAjT#K4PC*-^@)hsl0Y
zL3g<9hkgh~$hNov?2{cc14PP#DRQ`9<{brpqhx=HfE|!M6OXoNnT<A{2W2jlVLT-3
zI0SzW%Lab~ON`86q_Trp+1yf?h?9L31%vUjU#UPMLFPu6%oAlV(43znd;B6;j>_il
zfMBxhO#=ooRrVgG%8$w3DuzIs%$v^cnX>xj;5;ttps6fNW}_c8TQ*}GupHTo8rVA_
zbEV{3uIw=f9aB!qIP`szJeeDn&7P8_i6C)W=1$kt&d9!_a9O_W2}%bP$gZw|!9rO}
z9n7DVO+<rOB+I0_nPS-`dN)gCIg#jLscd=yoGFuaxdD{RY_#lG$R1IE>YOa`I5^MC
zp4HR+hYPZ|<KfLk*$3I+xg<MW1{0OCJ3+8}S@s7VvZ`dhbj|FF?BkmdsFrP_{dSG4
z>l!$(%A6X}Rx1k#0(M<iLJ^mGnd-lwx9qGGJ!_Or6o7a`7Lx(cBwJ50w`SS2cj*2@
zi>zxEs5fQ5&<5p}>^NOBYn3h7jPYuhjm<#UI%GbRkhm?IdjxHLvbPHX`enx`bu}P+
zPXqCL=r6EASq@z~8<Is3=dkQNMa%BX>I$Lkf$aTt03)(6nkFC04&ut2!|9RicP8wP
z$v!^`>bNY+84?q+KPiedDT}8Yol~+K=Rn*kUqnYAH~CSTr*_F@be`HP=ih-PcX`Mv
z5Iy8h&A>e6&prdpOYTm0LA>R&n&6s`{O8w!`O0U|!{R4*qa(4yU;Zb>#{=cjE-)V?
z-*gZ>!SYo|eLIE7i+5t2L*>_w!BUv~-(08(m+yHKCicm_C>t0lFQNx{zkFdc<f7zy
z4ctB;4`PGmp!_z4NDs+}=>QfZ&)x)<Sa}w0#Ny<0FQYBNAx~Kc`9ygu$tTITQLrLY
z&N&22$K{WLAebfpXAZo`mam|kN{-xP8tk5szef{mo_ska4o=B8P(<vsT>3QR&d9?W
zU_M`7V1Y9Q@=*#47RqzJg~7A(FV)aeB;VQ&xnj8^c{3zR<fDzSTPkm&`igS7mA<@E
zA>aKJSkKA7rNH)i`Q-oL#RYl)A#hg8R}BEWEZ<D4VU?Vp3hat}={hK@miN)RTO+^C
z2X<Bd4V@xu<y*gm+%@?k+5*+dU)~9SugjltxS<#I@}PKt2KhHG0FCm?v=zA_KhOvl
zo8;5ZL$Fz{eFvaLuB5}tO}Te8+HT1=(AlF^-kpH{w#mb3tJp4ohjIiR^0SmPzAc|K
z4PCk;zdawSJLMaffTc@rrnYYRkFy={?XLV&nm2mnr%QqL%ANi}W1rm624cUwJRM*_
zzI!Ij-;+<AhMGY+gA&3+^2fVjX;_|1l?nId(|f@3K>krN+D7CS7L<+3zYYNQP~JNL
zmPc}#0LsSX?@?*ZxZF0E;-3@p^X?Fwl$X&tVM>0IKD^|rh@<SMo1%ciIC~UB-=S@<
zVu*GY?uyM6h4oNWQ_Rm(@%g{d=A}^5Jri%m*=h**C}vl}HD87J2F&{@J`IL4f5qqY
zNt*!0QXAR=75ipW{4+?gj~1C=#l07ybiZO5{Z3Jef2a`ofa2$G(H5;}p$f`_ir-H_
z_aVi>?=T356_3$R8Kc-dg^tE5QtN=lDb_ECT)d))Qn5!AA@uquDBhrNDJCk;QF%p@
z;y3!=q@#*66cBeLE4(S5n4-9!hQ?GyhyyMjQ=C}{EKPCe6j;+0zfD0tL*XWdM5aRW
zDTv1v;XaVdQZ(*>huI1)O`181q`MG5q1gWioXJ)EvkKTrg)0R<^At}1g5{K=$pqD>
z6`lrwGY-X?gMj&p-DBuQfg(^1)<Q+bdJxYlzGtBqMT!?FeNwC#qw_(DVvG-#QpJa%
z@Tp8u^)5Io6g$W8Jf2g8(BpMp!Cwix7Zho8;NeBZFut?nbV)JuD+p97K3E84mld-N
zAXX_H<uo;2QS{TMxLUD+a(p$4`-h?Js-om`I9#V_SdO;qie(g*s8?L3&~AewxedA-
z6&Vp=xuICo3NM-z$!|ffSy4g(kQPNRJrFk)t(1wnrN|ipu~o5w!sBfUy&vS-70)~9
zEYP8N%L7VpE3VR+=Z+%Z4Qe_Sk5h1@OCgyLzq=Jfv_ZJ5*!VHpdK9aE0O(aTQcSi_
zvFt;L_bYZ#)^$KJ-2m*Kf<twMgNmsZ*d0<N&>J(X$fUjaeMQ_`F#A9;YaQ)BM-&C$
zgLPC9NL#muiVrBB@kkN)3&5D-O$IEDD{ORMazYXLECePMy%u0oid9$9=BhMN5O|j|
zA`Jq&m6u|mWsh>672Wnw?x%VmPv!h*$ayJ0c^q=S%1aCYKjjlX^!+n`<+|^|6QC47
z4QinB`FU_ANclt;bO$S+`2kpn(oQAQp~}bTRS8pu&~`9fY55<p2xa{`aPCu9P_b2{
za)c5G`;`ou?4y*^=#4p`{DgM&(aJ6g{T)=w+dw>|^q5ZdXNQ#?l+le*eme>mW0h&N
z@Wm+?KMoMDRL+Fp5#?J&=u?97iBnLTsGOu58p+C~pTdh2<roFFQ<Xbt)=O8eqC2A*
z$}ebFn5mpjE6;JIxDZ&DlJhHcW-EDfLCjH_pNFH46H32Dpynz|0zo~gtd&Arp0b(Z
z3a6AF=b`kplD`_*8RZLG0rHiyV0clW+(_rJLgh00_Rm@6Cu-O&Qa(i=St(Xd(wbbN
z{O1t7FICQ`uOgKxTe3kcS6+Pz&QvG|U&RA)&Y|r70@}_iKcZ>+g7O77P%kR0X_mjF
ztfFfDO68$M*uA2>Js;Ytl~0I3tWnOZg88e;vd1A_t8}IMifc+gy2D(rJVz&y2Ia4m
z7j9H`(500wWvLgu=vMCe1?KN6qbPCSqjY4`a@MPSDI4bdl*h85v|oAicMu1Z3o{^i
zPuZ~rCI*#DC=N2De4`3&!^%90<lR?p34n<Q%G<Hv98reU!uwI>OqyRGDzDO6>5=jX
z6_<=D^XN+PxYCyvf(hlTiI8(uz2W#5YIdr=Oom-I)rv?6?o!RC8zQ?^{hk1OREr-%
zVy~)N0~UAHBPwk2Pz6$$%~Q4QO<-OsSp{74R=H4O$VU}(8=StXtCSe>Q+-FXp1;aL
zv8VvmqIvKlP_?NSjs~gD&!HGguqr_aH6f}+bi4^wja~s3rh1;TDB-HN#vu`*5>WnP
zpK8rCn21yzr0CUt)f+;niBi4j5A1;Its-F2s*665JE)pR$InBmO&sVvta_jJcrhvk
zJx{T!?jM20sivH%{v}?uc|8W>i0UH6^%7Kf=tCQcDjA(*l2i*jVfU!2`*G+_R((4i
z@+qn~+NY<g^c1N%rfQ?vBTW_j1eB($vgzEIp+e;pUI10}Y=Gmc7bp;zrON*jj%KTJ
z=!BW0di!fy|4yg|Db19tdWqtRCsn0qp*v5tDiYw7ia|F#POD;R0Ymbi<nvX|^zG&X
zReB5r3RQPQK|HIvL33b{>ifR{idCEzfD+YK3d)qKs>9L2GL`))=qy*6{6VZx`5%B5
z$2rw+jnI8w^)lTjxS*<|?}1%Zxzcc7QpqUVU8Rbl9KjV;1m$w7Rr-2pt5F%JL*S|^
zW+Sj#)!BD2GS^fRDlDv1v3=3s>#EIE@ma5Wj_Su6RMjC+-KhE_4a6I&0NSfHIaDVZ
z80Th{f_8_uRQ(hoZdE<k15evjH|IfHyXxIuv~{Q!&@uhC%H?BVU8>R-z|yU{{yD_&
zs=oJx7kw%Voh|!S>nYMRpwc^|ZAkS|FxrMyC3Jh^zG@>)-49e_x8d)I%3*yAo{p*v
z3xGaUed7w<k5sN*@NG=BFb!(PRS)Q+FcYeB`c&?uYF7dTrc?{52FX>u_-p9isrI9T
zg`4^TZM}A>wdo-4RxjCzAI4qHrvRjfnwbMRPxU66kbTqwDoyoO_c$o~>8F14N67oD
z{i)C(K<!9@M4)<k3k(LSUp)&;!RiP)ZG@-;>5hA-dVmM{F!i@o%NMS;(4!Nfeq|}z
z_Nn(aKxd@-*=At-)z7VjPf_apA*eo}{)awfa!5VOgoVTEf9$l|iBUhUg6??rs}v_Y
zqSiS9B&frlLR+HxkKf^1lA1FU*im(M4X|YOwwVw}QJ>!mOR4I7H}vV4dO;`J($w$&
z4lG@L;8(C@sGp=gM5cPp0T7R?=g?e~rG91sEM%+e7t#4INBu_<Ts*1vrgL_l`qW1B
z_muiE+EW*)pZXSED^`0_l%PaiLUnqj>Mc)zSf&<HdaGQ$<SOJU)Gx_l@SOTh`ZmRR
zHSb+Gb3yGw8LW%yfnKy-QY+m7D%DXEfXnJ^2i<?DQvdcL%wJK*9f$5}wc{{AjrulK
zoLy7rQnhfMTGa$K*VP+OgIKTromR>QbqiJaG^%G((E5hDn@Vw;)X)5kwr2HVsuI4X
z4yy)eRll_lgV3fPas_9*I+J!#9qNAiB^|fbe^6<{9d!mJMLN}Ij{xgZ|1$%uJ?fdX
z0QIWhaz;n{)Tby#(XSq&81{fV_%#UJQ@_duaZtTN4cCU$l8Z1nte!#p#}V~n+B1!+
zyXZ2;L-k)Yl|53+sXBQ~y_#yI#~o_FJjhR|Z=MF2RKL6(cBj+^$|kyL>S>MJrLoeS
zzgzQ97Y4yyvsQyP56vnkaC&NlRI%x!DIJBQzM6bWRQhRN5&#R-9HGNikmlVx=u)tz
zh*Gg(n#L#47OqL853odN9GB_iF#9#m89<{nuhJ5GKr^-%2IDkaM39KrynF}P5zV=5
zU<sN>e}W}ZGb;oBCTV`|gSMlZEqeHrtXV`=`YD>^Ga#mF!s(!UOta`ym`~FjS`3zS
z&4mxalA+m71r?c^A06E=e_WGR0`plK8AWWeHT+K?n4^)o06U@i`#l)U)tovF^CvZ{
zgVC0!VNzZ2DNU^$N>6J(T@37u=AG9dkgvJ!34aST)97wep{AO$31>Bb9E88cn$2;*
zN;IE6fIz9{*;y2SDbtKnDR8;w1)44^G+C4%KBo!15Bc*NBjph;Xd2zni;J3e3M5|A
zjP8YerKavxxOQ11dmY3o&FWpyeMM8b72?&JIxPfhG;65{=&ELuE6mqvc2$FTUE@q)
zvU*L8E7hOf(1<7$-lSnsn66o~idb)H3TSKHswp2vTbt(c1z_!(sSkj4Xqx??=C<Y*
z#pAm)#t#6xH8wh?-_>+b1ffrpI|UE>HC1fL4QLojwB6GLQ3=za=DSxQKBW0)Ki&U(
zpqWJz^N1$>6@XFAS&CzhX`*QxJFdxH3f2kDOH**oRlA@1v{M`Fj5asz+%h=2M?32Y
z5cg^?uY+!PEwcrfhgMezEuPvBkATHXI}ivEsQqgQZ9&>+5%+Nl){fD+-VvhRMb(O-
zS{*&sVcN0BU@2U?{|&ewp<VqYMs}Yz^&VIwwcAKyzqWcFMlVYHMLe(r+NBhjj@Axi
zYwvVW`|Dz~9nw}X;LKs|aZi94ZBRZ`$7-Wv(H5t@O-JH*Z2(nJ9dT#}KZS_|?Q_@B
zn5g}CJG3Qf4=+XIQSByQc#*6Pr{GA6_Qe@+G*#O@6PAu?@8yA*ru}w4bf;_oq9A>S
zcARR$GqqRf3e0hBdML0g?H}}XW^3=wfipSUH?ILZq1}`ZWw}~MNg%YH)Gj{)FY>g9
zqG0}%_VqjvPiw0yA%8}@j3Tx9+K{<mDbVt$^s!L;Q#sU})u#RiVv)9vx>l@xf)ei~
zTB8A2skWSE%Q9`JJFs%CnD!tQS}o;C&uOcQK|HT5bI=zlFK9(y;g`9n^$mgFm$Zq!
z;HlI)g~5x<+CVDAs?tUV1FO-7QNHD>)|a9pwc1zcO~0;9^#!qBtJw(9pnaRZ)YPP%
z^(M45YrX!3T#NR&48&ILPqU${O&ex_*>>&U7qJ95-O(PSLvW{7L?3PL(&l^trQO=&
zf#A8T{e|Y`9_?&;w|ljtuYsjcJ4wgLer+dZ;|H{V(vxscJM#tn6ocB=7C>%T`_EmN
zzpss=`Qm|g$7a|a(a!x6;-gw;I#EB=E?iFMzeid>$`y=h_bo!>xHg@xiB4#bP(kse
z_8t0trnJrfLw{X$pJkzKr;a}WqMPpSR#@7lt11B4t-D1BgFU)M{%G5)JGBPN+;t&z
zEb`F3*avY>-A$U8y>zW?sP@)%7g7GfM|X?|^S-*_#{v9w1`&Mo*L{5uf&sdheg$iw
zP7niPkdC<qSg@{Q88}09vtI!*RJW!HSeWil3W|p7ey2oOgwCD>XZGp%v%nIm+p`oN
z?$<qa66T|H&&R@<1G*(w;HV>7ca<&~9MtLQZ9b&ydmVNU>z409V~j5NCn$~8wJrjP
z(;dGG-SN6%iVz*qx#t2T=;Fw=L|p>SQ%Sm^Hds2Un?=ihvTlIpixiz&0g$R2Er;r3
zy0z<}B~8~p4rkIGx&xgspP>^|ZCs}A-Cv;XxUPwg8Ckl>$H0@V8>R;_N4J6k5hrwW
zXnU2bJ6;4!Cv}UdG$2p6z751vx^EIdJgwXI8n81uB_&q#b$;)|`vRRGMLr63l~YiC
zR`;tPbQb9xf6_L#Sm#GMq!QhSG<lZlbdN(#nQom1=F4^Y6j`p&c~Cg>oKC+20_Sy$
zWiW9;w}xW<7j>`D6L?7%NUK?;E-wVSFY7`Up=Z^)hZO&;(cNAR?5Zx0;=HvwaTmm|
z>83kqn^UKIZ6yp|*9}r}Oug<3#TpxQ>nY~fsJrO{yEk+@4#C4F-Op4t(X30F4S^P2
zWHvm!sq6R+a<_DjwXoZ&TQdhH+H^Dd5O3GjQ4G05_ui`*i`%*?swTUmdqo1QQ+NMw
z2PC?5LzLU-)|FDV?_Hgi{+pslcP$o{dUZ};fu&E^`4w3Db@3Eu9?&V`!Ff+N?>7(!
zb$VQ+a~jeurUiFc=S<VxecggZu=GF|><yL?UBzs)jq0A55Aaa;*iDE((pCLV_m9SO
zpVAI{T=ywmxtq|fw_r#obw0mB&6I8y>2}o{IUw%T|MWe&wp)Lhaw>cD^QcB;uYN97
z2D$5RF9Xp-|CSGwdFnsnLC#Ab_7?p0)?cR!KtB4GNDzJXYw4%()1Uu{)<1v!L_4Sf
zdOn4A1N9pE7;upOaVm)o)_+Dp#t^;51>+p5XHcDOn0`5>!^8EH6y%T4yRSf>_UU;P
z<%`sx9tXBxKSIlXl>TuF_#Dtr{sg&beY6<@2lbndz``N@v+H5caajL7RdB`VT}VDw
z|KvyTElz(e6g=_zbuXjsh<=ieV+r~N*P$j+|Jf%XCh2chgY&3<)|YT5S^vr(XiL#c
zBOsTmzsZ5XF?}eVdD8SA-@%!5y&(fE$Mwr{AfBbyQVcrVq5tY8&>a0e^818-=`OgK
zt3Q+oH7E7Lry-H2k9r!|DZPn4ns8b_@-+m`=>Hl=*Yfq#DSdxdUrp~=k^T$1-BYap
zVG2H#=~G)_qFgUL4wef2<J}Oypy!N2{GxvL+wky`-tjRVtE%)r>d<&a|1p*QRO^q?
zH@zG5ktz@y_3s{m#0|YZ1KOJO`)VQ3tpAK6A1!*`26_SXi#Nm3TYBb~z*_a+(yp*g
zUrJ~2c71IO#;HRuqFUwK`q$L}ck~{o!P2R}@1SdwUHaTkfNuTGLNwmhms9mnkNy^w
z3HR!^iP5J%eK=)p`}JA<Fh8Jwjh?`J`uSAdHK?~!o$Qd_?KNl_)|Z|K=Y9SEZh`nf
z->HO_5xs+UxMO-VJ&5D_p+c}s=tUw5u}<ons3u`bUy=z4SHrUHP`cBw;w;+S4E`bT
zX|KVXmLqq=t1BVsVfdKdDo=yQ6#y^8O`2%D4OXhR^D(?fCq7@ptKWd=Zz!VYDZsFu
zuHOe58Vm9B1{qEyLQAk=H;d|DLJSXRT?jQuB4H`a@Ixth!VOE8KzD?pU;{v;;bofq
z_8WQ<;bD~F1G=Gj!0;GVnnoLbri$J}2K}=TKWwO^Ja&x1ouZ3z21O!z7H<fnwB-@Q
z5?b354Uf|?Fv;*5P8klTqlOGBSxGiTQO#tEp{om6nxS|(uyg~1qOci;e`vp+X~<H6
zc-$aWfF;XN_aTVch9@WsnPZrwn{y`&7YBf$u%{V4JZ1R26`ZFHm!1XZ8N<(C0OT7C
z$siUOa+L7GQD`{&HhOW^z@c+%kzqZ>)r$>{-=nd_u(=IgD>bkfkSH^pqxHVr@a0En
zt1v`U1;{zW*6+}@^M*F+#05juyHHkXXr6!<mknjf09A%ys%yGp_)G`!YQt_R#A^)a
z!!WQ{9fqb8pw=3!TF75BguVk8>kKB^BwjZZZUk$+;d(CG8V$u%adyMtbOxZw(Cz}z
zZ200SsA(~*P6f+N!+m<0Zy9{)zHqCdq#oY48LsYzhwX-M1u)cMaOnZ@wn26REO!i!
zAC5q<)A05(fG$J*Hc-0_4Rl_<YdA#rJ$ejD(P-;6JbDsXpCQQ?KJ^>e2LJ{Q?_32K
zGJGh7z_7tJ5ave=`{~d=YB+Hfop@+az7Fun;CljK%n<k*SjG)2#E_dZlsf)_ZdYT&
zCurPh{B$~obeA#udk}XUOAcf7_83RWnZ3qUbZmAvW^M)MVSJ0S#Gb}EZBXN7EOvo_
zw{b146+XsyDF^Fo+)dZ<0*sIR00ND%R9PNm-2N*-urcdCya+KakEQr$sPP9A)Pxz+
zs4h9&SVYfUgmEoh72Ie1ohFk=qZ7^2`;9s`utXVqYB3fEjA9=cj5hwtg7`sW?*nxE
zkg;nP1P&XMsVFAK_&5_?iZw=j1dw3#rHYkA<Ik;-OEQl3)B1PR_#_3-l8qU~kWVo#
zqYzK3F`yX4W5xkWHm4aI!T{2Z@27wz!`N5|-I>N)x1jB~af=5GW*HyDRe7gu;~9$0
z<QV5sM)rhp{hR1SuJI_{qCaVTtOWvj#*e6K=#){6-Ic@Xw2|$L@j7FClXe#Q#^x{x
z78q;i0u&nkGhy(o(Uptd7a5m6iH;T<S#v=wF)pS}c&YKP5|}76uAz#Ra-${=S}Kg&
z--f|+Mit$EIB!g?1-M{*mkZ8|#uY8#yksmt1q+T!<7ZybcG>s`rTVIj0W`5*F~-oG
zQf(Z)2i6)R^DMwsV@(Ov)EaLsfHT*Ox607bI-@8b*mabVK)l|#>0@9G#=co_w9z<+
z3i)pskI`nf$=LHcSelK+O(3=yha9kQ(_z$5l<$^tCRHu98rP44+Gf1g3gT^J1(jgj
zG5-EM+B%K-UxL_WJV_s=?>1(<inhDP$LL4vG5);_{p~ew{t|6{#&>Jc(SG9zd|=gS
z!1%WrUAkvXq5Euu#(iTD7&1P;6vSbpqiG==9x+-Mf_2o`LR*=K#;X*PdSvt<^JB)>
z>990zWYgR|VH}{!l}TgJN^njYU1q~4S5pQ3%sWjS3a+@BTGGI>%e2)U*lv@@NyxdI
zUValq4^zzn2zZ+6`ha<v+#LZh;cb!%z~f_ji3v--rq^dcx1Z_Z=fM0;`|10G0VV+-
zJ_VYtP@#B`sjwgJ2b;JrLQRM%;Tl*%P1`8~7-ov0?_Y<T-qC_H!ZcEawtc3OB@l=-
zv7NxO-;_BA_M%L0FLJ=d0aGjOxuQ+(&qCW_)5=sd#+Wv}2f<j==cFyplvV+jc$1?G
z!*#^;Z6G{MF!j@oheVSHy?;rjEiZ!QsA(_*;>o5-0f;H4m*{wsYC1_t+he9LKSg)b
zP41LH%P>6|^*G+YOw%>m-5obwP(yc?DUV8HvrS*@1Z$4z#ae(9rq66pnrr%C5++WX
zJ}rh%d8St>F?7bH>Vu>Crj$w$3rt68)Qe0{A)Dw_Y<h)4StTa13jHiKEx8Q~Wu_Cf
z+b=hr!M@1hRACwm2hTav6os_ToBk?;r3<F3l*zhinm!+GmrRK-L0hHi0zKrHO}FVx
zT4nk;0RmS{A)fHJ+Vt-hn6EJ{+yLEIO*|?YsWt6>8Ew~07Y;*NoypMwE!RzNyok1X
z)BCSufE*1bKf3?dXzKh5ow;FJNw*@JOntP2Yc{dJgTpPRrGLQgP18v#<ho^Am<4UE
zrhl+~c4{-tzJ<1SlV%q{hiU5$n7?D%&V*d2>2C@>beXbgap^X_M~mrQ)6;Yzw8ylP
zii~?5rjm1@_L=7K;eNmA=|4anFm*f+!F#6qMR0h~^bXb14w(w6qGH%|lfZpbydGXW
zFulz}XGTn0=p%}wrfT|1$wN~%ojV_yBvc+XW_ouJI>$}L8W1N;ztYzVCQT-KET>G4
zog8@TY98_jb*K4~J6PS!>mwkz%RG(BQFfd6)2@GyxnvMSve*1c4cgqzA8rBgFrPjS
zrJm-%XkcFE`gvgSHmhhi>0>@fw>5puVv1w<nXl)8#oydW!SVp}`;?~%G&>x1Xbdv1
zrg(3#x%?;agqR)iP#S9fgrX{8X6p_R!_7hIkccp6UWM*`X3r4xKGM94qQ?8p*P`KQ
zl)0=GatF*mP;ptbx$rB<9W<xx0p}s}08Lki%?vmEOflv=R7((Rp3kQJXPmig8$i7I
z1l_whV&2>i)&%omnmiNDdwzt{B=hH1s5xrxZG~X6*--;xig|T6SW?YtpF`;}v(^ZZ
zW>(O}=ydbZy=coYZ;Zq*l4({@*7dmg808eR%uTe(I$@S?rT>4(HP5Arvy<k3cB3)R
zyof?er_8~3AaUA!?FDq^jCn5&e!ltWM<5oMo9SFrXx<nOfwSi2|H7Ff^OGL~D>hfP
zfThH|m^QPe=5_JlEHgJpLA>1jAw_X2%!PY^oip!56}Q9by!kSfLR~N?zYC`>nq$HN
zE}0VwVYkx!wKKF`HcvecHC1NLOK7`dF8>Xn+Ptn525Zb8??u~H^GRAqYR%D9{BX_u
zHdS}kng2ZxgV)WaDQK%Ve?#+mgZZmyjA5g>bOc1l4YMT(Xp?y<dC_b>-2l*H?v%pC
zo8~l1C)_d@Y()=S&EL~imNs+77AS2u-~Izwhxx-Ku-rBmu7I{X=2j21b(;V9Z>cip
z9t2CbS(*-(yXN<|Lrag@m<6oY+!zEyeGc>Q^lvWx=ERF|c))yV8h*Tc=AIguA2i$N
z0vj^FkpgVkETj6S`{qc>r9Lp<?0}jP^T%BDY1DjpAy^)od#Qx!k=fJ%XU5DM??7PO
zTu))!3G<h4!@{Kbga<gM%r8(R+|}avH6Cv4w4_tDp_`@sA2jZ=T&1|}Zp%^H#=2V$
zQi+>~Wy>l6Ps_g=`0HhP&J$jETMW+d(8u!FLJ<8eHY&CXuw19vGSD(awM!uu+t2VR
z)Uxt_&>3cNt_CsOBGv;$SoS!mj%A-^{`Y8%w8XxM&g{3G_#d2!vg~~x;D9A{7_8A2
zw|~Hbf2yQKBE}L%3IABjj@@91v()6nM7)J{7}ycZjvP3XU>T**-BAmR&QZyh^cB#O
zV%h%*+R`kSXk^kYPj^seHpB9U4Z5=|&0UbswnVLfwj4{<QSh9wETR2&u4N&`drw+?
z?|~)HQbq}YQ<f)asXJ|%PDzO~mZS)1$+x^h7h4J}J3fFwk)@Q%{faFUbj6{>(y$Z)
z<(BhX04gkd>ZtzgoW-BMzJI~eLnrHtmfGF0d&zS6CgdwETKc~0Wy|*z{;9GQ(6n>K
z^1=>a)s`zIz-laZ6GrW-WtsrQT1&7QUesB({D9x?x~1+du+&?&i=eE*lJO+4MoS=t
zjc!<eMuNrR)MQC|4`{O`dLtxSEX?=N!<&{bW`fvedG#BZZ?{~%gdTQS-id*Sw=I9t
z6L`lW9tYNGd7NIAZc7pEEbdw&(;(hsk<#9!*D{^<8GV+;S`hm!{|3Od0n0ou49Pvq
zb&8Za1}#t1b2VgHaSgo~wk(YWcHi=i9Xt;#42l$uSO#AJHfmW*1uTy&QWjhrvpjPL
z{*GH-q}g)9vOWOBNy~jI9-6W!HbcPGdj1Xgw9{JsCx~v=AiB@C%PI{8*lqojO8NFU
ztRu9i-fP`QtFgOvF=a75tn8!clee|u9L)Pzr&C#%ueIR6IF<DqN_hubqa$HA$eKeZ
z@?a~6Ds4inqep;+T64_6BCPW$m$J`lrx`KQI!cj?{nl+ma4pKZDG6-{tPcC@7@BD7
z`?L`|X#JIvB8RNcB*X4u>&wg0rx@!v9XMmH`n3RY*3FNhGx63136MWx-98iA60DEy
zM_Zyb{t()dtbOmJhbh)~Df69bt)?@}F>AOTAkA7ump#+1K@@S!u$mm*fLT^=H%Me#
z*HKs`$66c)pH5n@&@z~3-9=y6IA#580SunDKD7c$&sg8*!QXuAEEAL#SUpxlywHji
z0M-MmOB%c=vZjWkt=JkH46MYOJ|E(xRzFvWms#CtvMsj`cR66N!n$leOq{cxj)44m
zt2ZBgx?pXln8QVD&t~YpWSyshwo2=RAEE8C^=XRvRaqBP5yKU04xNXptyy)zYOEGI
z(q6N!r@eTcRojQYT(^Egak+Zy<nJIhShskCv(eh+PyfGi!}`H-c+q4%O7W&<>z7t&
zYq9=9!+q1b;1Y<ptc5f~v|8V&hhUqvwG%$ITg&L`O^0=6C)~bmy}J&acdXSlz&fq-
z&jahSPF124-B$lO==NP}ZZEpsW7W-sc(3&a>M|Toebyb>VC}aCP<6_HwU1`TLF<ND
zU>&k%QE|$!_01ol=DwAg4e-D^rv%Q7Sl0}oPovhdk09{SdS3%<%-UuJ7`Gm#ec*&u
z;sk+7YsWH}pRz8R1w*d3;LkwZY1{oe<Q%(fV-)V%ZCjU*#yvLm9(b|W<_G|Aw<#&>
z<7Lx@0Q0t;v4hjc_6u$Kd~IRzQ0iw}FTx=B+uR?(V1VtjyJ!oviGD;|kgb)X<iWN{
z3TTJe-00)0p|(Y-&>3dyq-vvZhpmz#_z|`bsP=H5&4aGaMcTC0==Ofw7ZlWqvQ4`P
zPY>AUe}Z2m+E$tiaL~4ruFxE^O}N3Q!?qnlD2=gQdjsOJwrP8yEY9Xl@$`7xM|9ie
zi0xz!v?SQBX8|PI{3pPYWOE#Q3nq@*uI0hSRNDtDq3xLMpaZ(oY{JKZrQ80B0+wMD
zy#SU>TVeqElx?f+f)_b9<$SQ5u%+anE!XB@hxwDXwNxgUXM4pP=1<weY3Fv@cI9&r
z&)96&pe*0^JXt8P9dXe8vO?S7QMg!S^QU-5vF%j~`<B=$Pr%bs+a9W#D6^IB1ZTPJ
z`#69KTl?EEf6kUa1K@&fD`lH5+T8NMdC6v{I8~)BMGW!Fwzafltg^jIeYs*=SO8+R
zZRHZM)Yx`6J0Nk@7R>-!YvTr@7uReB-RMP~Eu8WQ*KMjY3{<`CG{uA(Y-!UW-)Nih
z7qA<)yaFg~vbn5+K(j5AirQLi=N_TIH*M=ETzt#Mp+dP<TQXhyXtO<&4)NQznKY5#
zvF-Mv`$wI&Q|~}qx9!M>kiToYPBo%EHl-fsdu`L`DA8vVQ=+Bc_Fyv%4%m9HK=(b{
zp;Raxw7vEPScYux(@nu)+cyk|-?uGw1$bZ!r4K5P+Fra5frqwuT7@6k{+bTXG20Nf
zH~9Y}+sHcbOxo^Vg|;c%M*5vx?XhVvztbMihHGy2OqySJ+p}&$eve&s2rPT;5wzmD
z+kc?FkB2>;&byv=e?M?~+1WdQdE2EFOY*VjhXV7p57Pko*<)x*^0!aX`OOhvccYwW
zpxuq$*dTlEdhi6>?^6sr#J-R&mWA4%qPSj|J+llxMcNNG0PMG4@dt>qe?jx>0sHUn
zV2QRL-3al6_IC;(e#pLx0w9O&<5bTWW3QFLV62^8j4s97|D@;Qh{N9SCs-5g|D1&v
ziT3T^f;GuLi(ZnW_Q)i(CENeGgdV2YP0OGy)&9~<$RD#W#_dU`bbEmeavAogp9M>%
zz2+s1^KpCo8gORW>()Y9w!MIAe{<}s^k_R_UzZLn*S>;krcT-&-v5JOo;{tatj^e1
zt^-fL{h4xr0()l(%op0*=y-D0K0z;hk$okdAB*j|cF335!)QV;weO()W10QJudrKg
zf7XgYsIZrP0_>bUlx}UExBt8a0vGHzs3z{BJ({*om+a$?8$c`VJ)>y6Z2z5h2vznP
zik4ro&!)Q7YCHE7h&A>rN^oAaXa5Y{we~eT0j}9!peqt}_F~!~T(^7EwyfU1eE`ZD
z>_MyHXrq1SI}pEN|DFoeo9t)l$-Qa6L${7^*@GMosA;vg(E+{9&S=M|x7!~Mp|QiB
z!bE>>+Z%RZobTA@Z2)Jd{gZUaciHQy%%a<V-2)!pweO_8PmlfJrvSZn&VPF@d%+FZ
z?YEz#;-dk(Xdb{l`&_C@8MK=yTQp=(@}low58GR#Ab8*2+YF@-?C(Dfo)No{Ix}kT
zrxW8t`!WH{Ke8(*=00YhO=p*JySW@J6ZT=MLY=f<p`!UI`?e_nSC?b7r0;Y|egOh*
zF85bM%PyC%oI%{};`}yP_PBT=jN)+G>!P4YtEbBc9I$%1ET?73+hraXL?0JB)i?RN
z+@xpL&*jNc^xog)*Zb&9fXk|EV1X_RsoEmQCBq+BuuIz`m<Vy<R)QGn@*QQ)!d$k{
z@*D25Y$=8-!lnBM5cjzR{0ZQQbh-6ka^7W^6r&#H(*1vyz5^_(>v=o(?k=!PS=d{)
z0jVZYqef#%Vu~7#F)^l@XpFH%V`5@rbQeVvm!|Y0B8o^yL6F{?fD}bg6r>6wO##J<
zV)uLJ_y3-Uhhff{d1ubqyZ4?mGv`8;R1pT@6PS-Q{7o^=C_^V@$D$2Mw0(^+lu#@x
z)(}Ve&N#yn3LeKBJZZ&v*sxy;?ua3cyhtz@XT#A%!>@GDK5DqW6(}hNhd;oj8Z<kB
zl4dgeOB<7PLmbswW*DYU!9X(&N%cU>GML$7OxcENIwY54*xU>*&+vu;Ch`sAI-yr!
zNL~cJLc_oGjVm&IN1MW8!^?ChEiqhq4F-=JPHsSBsiBdUKxKxB8=z2b7*9nWCk&=O
zdID4!{6B$-O2hl}(0S4@yB>|F47a|7Gc|_&pTTaOp_9HUXAIxbO7*PaI9=W64G||`
zsliY=4hoG16~%O$4GSpP*J5~Q3>sSv6$hZuW*FB1(r(D82j)eC(=~{685W!9Ai`xs
z;1Zy98>Zxf^cZGRY_-?$@)~e`hB8|G_Zw1Z$#=z&NX0Ez4Z7_h1BNE5LLD>|WB_}}
z@Ze2|Tr-?6#LQkdIM9m+hYfeng4{67c7mashG1Gl+%kMW6&7wAmVZp6zhjt33#z+@
z^KZb?h+zq3i|-j;qmA-?!#5QE88zr@Vd;Tk6&ZYJD0l|)$S{X$B_A7xXr2DVu!jmk
zo*L>a(D=;YJP#<(4QuCub1}A3j=<H}LLoyp;|x0xccX_L)xUTc8)KmFX*7hupqKIf
zH&FC8*3cPFALDk)g7_NWdJEWo#(j@4!T!dtX)XecUksoz(3pD{XhFt_=}_Nebov~6
z!Ny0=!0k1zqK9IL@frn#_8F(qsw31G{sYwa8)L9-HOUSb-D%YyX0+)B%t2#FB)D*+
z?Iy?^GTxzpdW7*CdW}V-(Ss6rQAUL;>_!_e(tEvPjC#rn#2Viyf{8d|@)scS#v{Y9
zblCV4rL&J1*U*WQ1f!h(SxAy`3MI#rjaTX7HXSp@G0;dc{=OY-s&V&C%te~fF&~W?
z#-xofpK0uM1WcCk_c{zF+vpw#ksRX=%6{e>ePkd7#(9)uFElo{L!rpnr36=ObXx+<
z5@UJ;8jl<ODfe4y9JvGNGUI$_G*+6775@uV8E>2fTWxed3AB^O-B_B-P8lmGid19V
zxf^JwjkgX%q}KSE9?sMmccx$zXN;XcLZRMxd_KrI<LVJKo;S*tz|jWd=gDYnG~Rp}
z{x%t(F=%Wynm2)KF;3V5uvVjK30(?p#*cP^Z8uK8j>*4h>{tiUPNV1N(7$B-f;Ns_
z#z+y|WuqB=tGbQVQ{iEcF?TomdX0v2@TuQe8IF0rVk|~tNp{s(*@eadqwjbOVi5n?
z6M93&&nZHC%_tVb-b15}iCUi;&m=+Sx$%!RAZ|{R^uXTbbmj*1y`18Igodxvg>OLu
zoE*M~NVHQ~8>S@LDdjB8r#sD|09Cfr(^81!J5Br$jYUpQYcbH{PL72bQn}L|8fTSL
zr~!?&PUmTXe$lDzC))oFI_3T^!0c2=)fSJPnycZH`_^-`C-vNFNP?$<TP;t*VA$5>
z6!VMO+WrFck8Vwj0hh7$Qz^_BZJqiIb}P5q3LvMp)=h@Uxvi6_sH|yg=z53*ZaYHD
z_3&-FP)tzVHoy0%{xf5n_$OL(w_WJQu#a!c`w>2!+V=Np*gd!HG3_YYw;ghZNZ+<t
zDg+tW_N@l4-QJe;CrmupmM{f+PqxV|;f$Me8kMB`IG1~((cd|h?xexad#Pl3pR)}^
z=AF-ZKt101{r9Q<EYbOMb67g&Jozd_)0~%+Vy5$B7l`IKe@OS6TxYi{(8zPXL@EA!
z=gkxzC~;ny3GTRaLO*;ebFLbMdb#t_UFbXEytNCY!g=5q47Ac&>H^oQoMZGL)y|)H
z(*!ve(jLuJ<NU#ODAqc!qjg4|v+Z28o^f7B$I8z-|3MqLdgtZzg+K4CTLh5?=Wky@
zU!(I8ilba`p1ukmHajcmOmU0zBuZenIxnKbZf(v7y1?}~Tb=`Ezw`G92%vZpele)g
z0|XNjMe*+@Mjs82T9}@tz;9#L(wUr#%p0_;=w!@Ah;%XIIdI)fpbDP!GkSU^++gNq
zV?d+KAUzXY*w=4?c(Zq%fD+6KhbftjAMx%~IP>aBdLzecyEehnn6@l9`+6UCHYV8{
zOK5BV-Xhwpy+3gxx@Z1273d#aqWsy1K6JSAqa;deer#BXnVO~f1aPyjJOIR;vLUp5
z@{kI{=LS)I_q?B%qW#l3Jap&pZ-VY;?{+|D0cVTe&*xr*?iV{N@b|)#L6{uVmkmQ`
zTJ$X~b-#*vA01zhzJyVI^ZJJv&9}>F>b`T$hs<JM3NC#g^(sJru%g?}k}vGhyHuq6
z!;dST0b$uUR5$U{Fa<)Fze0z=elC<kaz#!kFjwC5M9ZpM1+cPa;vuyEVp@0@v$fWn
zgTlIt{^<VoO)4x}|M`pf`?tR-xApIDDfqpMnL}l%yO~w}(C}owrAyL_nMn1l-b_|L
z?D{ZUV*%~USiT7eKW5?x=E9$GPlU)Gru+c(E;DBe;K@y<^Gh_|VoZ-|Adi@bR2lu4
zQPM(f7uz`jWH;M<oh-5cm0>cy*pWYA!kZnYE7OPl^*&&H+2s_k^J6DdA*w%{Q4fQM
z*nZl?M6m0UK@!;cbRSA&WfNfNC_9xN0!i$jUji(dEi}=ghhwb98j30G=>%Y>vVT#e
zAdP+I3z>9wYB#Vm*gdqw$z;P`1DC}PUxwXmb~Bwz%4HKN<dnxwr1IZ<woC)C9LWJH
za?O=QP(4ka#D~tL<x8&Jg);?`H?N_wP;z10ZxAh#Os2$bvE&=d>Xb;rs66$!q&EX5
zN+qQRz?4Y_SHiV&NgfNu6Ou$7U@9a|Uqhi%Qbil!DoLpi#!@YD9tV+=lDUb1J|%hi
zA8<92HKB0~Z<0_Q=^4q)HW)Z738O7Vy<|lZJUb`x_!jc#C8b{hxk2*xOBh(A<XyTY
zUXXN#0l7)?(P`Lemb~~4AX_B=(xJ6h$%`b}Cb@h9-nL7M=_uJn$s6vF?2xEw_uVOp
zSO5!`BqvN1O6Zcz-V1VB@(<NebxXzuK)*-gLnr@wB?~P;`Xphkfa#a~aswV-krX$A
zyDG6)z~F#HN(ZI}C0E}8=#b=HKd4`m%%>;Ub;<J8=o^-NG!J?=B)cfZc~i2Vs#9)B
z#{Emd{@aqc*D(oqB-^Oe?XDzxBN|5}DL(M@o<w&WiuWbbSJ5{rNu}J#1Ifv7U_X@H
zybptqB#k9#d@LC&0>wr8$|_8yt2B-lnd#D(DW#MlU0?)ernDgjT$XeUJ*l&$BR#a)
z%8}Ml2r*Y$a1*V0(lyDjn=f^vuV=k<4}B-kNjEe>@x1i(Nk}$G(<%DZA$@@g6*{H4
z6p!qe7VZVPBK?4e!k{#2DMW^(BjmQH>>O2MdCAx~_~b1MRKQU`ynmb?HvY1S{%8%5
zaYl?OP_~86GepUpzk^1B%t)J_LfI1-lNHIH(f74j)>{Sr64`uO<sHYrb%KdfnH^o5
zWwO3<*e#b`xd5(0<~SA}R?3{*&{!q=muj!7Wj}ri^^>yat>`nIl8w0myEU@yKf>;5
z*=CB*Uox|b0CtzzTeOC{Y<8BoZnGKVpx<K_Ne`P|vnT<i&+L`UQ0O-snM9wKS@b=4
zc;76PLEm$;!}MYj7xP8=P<J)YyZ|rU%<ZVS#n;@>i6Qx!%pC*K>TmuJy>KJI{AXIG
z1(~0J8*{nG+<{ii!REi702gBZ%VogqGY_KYZ>YH=70~QAA36*!-2AVNAcxFf?m}aP
zxr-}EocSvh3(Gd2S_zV4{s$d$&o!6a#LVQGcjnUknw!3(V$CA+=8w@?Z0<h;zLl64
z&4S;@%?~Vv`BL+IdvGVs57XM~l=)ctI@FlIx*H0o&0F3_W3Bo10ic{Q52KIptod8>
zG5QwsCmh^vHFuygjW+XXweYFk+_nJbJIr621NBbxJ`=5jFPRThu}PPCNHDOw&398w
zy2rdc6^(u73*Q4wzj-j-QLdWjBtv1q{O?l`88UA#1i5amUjWHr^Ch&<xM7|nzza8v
zdn@7n0gGBXVG?E$b`FgPEr$2Ne7J>E4KNQ`95B#kE5f4f5MUxLZhVZ+D2rWv5RJAN
zpt^%N3+HBF$6IWp6DEf(JnPVS#G;rY3W*kvH^G^s7D=xICCNg06<o4K4jq|2W-;z_
zpyXJrc?VwPTKqyM2=Xm#3*bzF#hOxJ7Fulgrte>o#kN{#lvp^^1NXQ^;8ApzT10OE
zXqiQ;786x&k>ZTT3X4mWdaJZJ`3XpsMe#pCtG4)p(zT~725@#<R%6j{8z`qOeBMW2
zorNYFUYxPe(TVD_7OU5S8?=~0hfszr+$w0Xaoys*a13VHqJsj)H!ReYuf1szK##WD
z7JI6pc*o+@X(*0ZoTZi6J&OQ}7(KIiN&(R47N4Gkx{Lfv86;ih?Im!=O}>O;mG1IT
zB~U!%Uu=hKyX3#pO?S8a#0dI4<&!8fX7Z9xdJ!WGl24=R`91Q#=wRty`OBS943W=R
z0un0UN^7$H@_O31rpZHSo0KkJNKd#-`Bn}3vgD5z11(#=br-lCc??A&a^+F<(9V-T
zq#BBRd2$<Ora=BKof0UNN8W^bkxA}PPy1pyR|--h|KK*<KQ7-vJDO6t_!soc<V&7H
zqg=j&hchSSF~#&z$gk?)Or?C+D6p&KDN})6E$=*pzLW9*ip`#q3tvO8M!s`3Bu~pz
z=z6S`E58J(lb2Ibz*)IT(F~b-`D;%w>~r#mM}T%-K0q&kX^^v<A=)TU*^R~va-$lO
zP4X43Xl$1I_JXv^SN#CVHn}hhQ_?P9`2cn=%HQY%>5$Lc1AjZ^m5wlfNxq&=Xm!bV
zQY`thyeS8I-ST-RTKD(JUALpPSH9K)A4Q)$Y#~U$+^rV|ugH&d!O~TE9xeC=<acQS
zG${A}1}63>-hBqwf)%CXpm0!OSp(2;g?1D}JES=1f+0mH4vm6DDJHxRuxP~-+9$*+
z=B@&XQ`lIVpct>%Nws;06?M*NO;9w^`xO!uOI`x@QAOvkAW4dZH2^)Pn4v^ps=|{N
zDQSvnbe^_Q(Lz;3MGEaW_*9~(r|apsV)1%lRx6%11G8SyNeicQie<DxKd&hJUx-Md
zwx(jsMnwl5gt(wkrvj}>VMoW@nic0xV%RN;cjIBVRS`?&l|729?I67hA6oGBDSYOD
z>sK5=@=SI`A)&|bRmE(IXAUSTn&9@JVsICruPOfh2Ij9TmhyleR@|Xr(hbEuJTOhN
zn+gXCHr`Ui(}}p-im;#2c}Ma0$AG!3=%=H1BZ`@Uz`mzgOV9LCMJeSrA1HpKT9=24
zZ)y4WNb!0lP#!D%SAaZGlu>EzQ-y~YxMvFQ-@!dse7+3OE|%-8;F_zY<9HCfY-bB?
zGu$ozTL;#|audBfbC>10!<eYumOiv%^R(=x&5)1fH}t{!TE@MDMnB7X+GPb;{<{@i
zpyjXh9<?CLzr)eE$8rK~-h(YW=-af{()$Z=A(jlCEQzo*r!YgL<!OrWMwu)pM1n?J
zhSS|P)-t^pT%6@3`t0K^L%#;sZTTC8fkrLQP5_#V)qATT>1s708V230m}BI<m31FP
zJggR<fTO#tPJIqNZ>#%M!0BVv{S!R&wc7PFF#W71c|bD2YQ7Cn0<BCU<z)9*m0JNO
z*y<rwd4*byQ1*4d)wLPuJ76{VJKPVm@}k>TxYg@F0{f8FDO#;ZSeaAQF4F4hJ5Y$W
zay<Zr7^@L;kXWlJ9|1GYN;L}ehpi&sL*o&vhdUsdV09ZCZCRq#Zqp>tOsht^TW47%
zQ{8N~)#QcnJICrUJ=}7w9Q9DlvzkpMKKWM3w?GQ5UZ-z*k=1vU96WB7@iFwutPHe)
zDYx?80K4a{=1^64gH@>#l8shd=v3eZD<3*=)nrw)1t`r{6W*uiUyIe(3DCc6)kur*
zZmaD>=<KojnzAsxR$g+z^jp2L3IiRqdO`u;A*+-KC|tAZO@;aERx&DAx@omO5B}b=
zVyQ^;wpI7bnBY5BKU1*czST?$AB|eYnM3k{)u&^C^3dwX8Y(t<Wc5KhEIqb5VGYnH
zRv+Ai`KMM=`pWoQ&!HSvfc1WgoCaEtJ_ZT0UNZ}gd#r0NfdpI6DuLc!Yle1OA=ZBM
zt=MNhmBS>2T5lZ-u>ICOWzaidozx31%-V`xlW@@b#Z3DCg<HS15Tb{yZ7KL3Y2A1g
zqEXffFMvc_e@GA980&P})5TghRX{S%`Vu`W;;n~TK#o{foWmp}SjW<LB+>f9e?U2E
zovJ}&vh~z&FwkSxRiC0U#oBK>%%@t%&jLxae&GZfP3hJdFN4jn9zPDF$h3~7lRR10
z9`tUUZ0qg)(9g9t90BpNxlsn<ZL|1$Ncz}Z9|NC)Z3?!+?m-);sTfnZO(<0j9<uqI
zw#^YX<KBfrluf7y9F4a5nX;fUHh<N_Lafbyl+=$i*<6o-`FNXVst!%D(b9S>$0oxF
zl4~<178-dr<#fZyw|Vn5z|`7kD6Cm$Gm}<~XKW5p;GoGSf}V}dHiPuGlNOucH$Yl#
z-lEWBn@u4Pk#?KJ7;qPDh7Z8Q4ja!QV0PM=rj3P(OE%3H@ZojYczyscF55`|hG@5q
z+t+Zv$A(`G(r2TfP+Y&woLi8*VlzlFysI|LDC#|6Q@0-qcWfLe=ziBG_#*m7Y<ALl
zzI!&`JO$=`o4|$OMr}%{R^@@sum3{iq0JbRJz5{xjL=&i9@_|0(E7w?gu?7kZC2Cf
z?3vA6y5?Mz<6nTHt8#QbMBJ3q=%MPalu)&!hccYbZS7K4PJ<V_m9K6B=c%;#3zA;S
z(`u-DE5ll#;G;ac5{<sf+h1UQ{glzC=$7cOyiMge0m}C%tsbcK2}fg)vW}*7k8;L6
z^aU&VXf*Cs)+J)v_9-9!fWA=W<3B<6E6b_M>wvO{g8gC2C_6MBRA$ijCR`cx0Nf#E
zh!qS*D34GPd!+I#rN^R`<LfEdAESK#N65q~XL(_~amuDDbjB;A7eMr|lBY=35#^qG
zkOXB=0!$oL?wyUnBq^t>A(E{8d_E@Om{LNykrZX`5ul_hHNT@VO}TCsyhv9%#sD)z
z$%H~AQ<*~>+$?3nSo&u}*~*y97*nqD{w;{+DH|wyldt@B2lNY+_Eei*sB9Yx^F_)p
z)`2TlzDJ9#5@o;%I8&_*xeK(DO3NRha7x);i+QS1ene~22IZfA5NTBAHerAll<aCW
zHYxwe1z5B4S}+WmT9gB2u-mHq@HWQOri{shM!WK>ETCOf8mPjkL-{jpF*}tzBhYwB
z`6C6Ex|Hi(fOc6qh9<vT*+sQEy~@#zXzWw=Q7))oY4!|#SCoHvK;f$LEgOgoDBbAc
zGN{}f1j!+jQdk5xt|`ql(73K#`Y|+ymBaREyrKO3MKs=2F7<%ME#>2OICEE7IRR)R
z%2lV)cTc&Y918c9A+;c*%I&)#@<7={E5?V)Y<CRwk+Ppk<XmlgwxiL_b^>MI-ECuo
zFkBB?lhr1SX}9efT6}ogj$8!iWxHZ540_v+p=E=Q?IKDn``V7BN4uZxnK5Yew_Qtx
zRROjiWWjEr?c*J=6l5D83$n+yaUm=v+O4t1Ad>97&4GE$&X&%0q}ok)fHUcKPR_89
zX{R$4LL=Mm0`2&6?UZlBQlZ@h4x-I=odwYEv2*<xeZ6*83E=wdrv41B-wyw68Z&FB
zdJXDV?RL}C<+j~Ysu8_ow`L+F@7pOUIq|^Go6@}x?Sd>p9@*WYny<%pJ3HXT6T4Ie
zWe1<yxu>D^nVtUv*nMtiLuVyiRI!wObyba$K{r(jl~lN^Y8ODkPxbpgVEe1;-UCdy
zYAVGx52<QHFziUx2;IS>R8y}&BwFS90k{}d%^Q%6Q=NU6CPBrVheDca++jLwP@sC0
z4)cX7(|0gfq$+qDGF2)=6YN&2y7$u6tupjN|CDMrEj(*fCGUcqR$WSlUajh44)p3&
zo9GD78P&jg*gdOiUj|aIGTcGqIn_N{@SayKrvUCnRn1p$v_th3VlybVRBiqTmM*Cl
zxI?2$B?N%GtlD@1UUaMSsN|(bHIV`7RsB2y#Xgnn3C7f~^1KQTZ{XSu53j0DsG&Zf
z8m2_gpz5=yur#Ea+XlUBD#K^suB%SdOY??R%~TX{L#3IIPs?;uwcZM?w=hsB-d1%{
zBJhrCRwu@ESM}x)xDizgMfvZk{OD<VU$t)oJRDX1(Fl<TD&KnaJyex7L-LX8eP3{o
zRW~T`{Y3Q(<=mdC;{Jts7p|28?XKJ_4>2WfTs$T2-A$bC6^MFpXU;=rA9w#WutPb+
z=fFO|$)*A=jNAA#6c2H8?VuRJ9is<kB=_TD_#4ID`VZbmbMwxFi{bvH)m<!C98aG%
zH<gF^c&>n|L=JP=pJ1MjaDTi8^#soC0L&(Grh*}~9_37wGf(2I>7_Qw+!zWk9OD>0
zND8;i4JJ~#UT>I4<2rI6na<6Y0Xu^;NC1<`O;W-8EG}phxNOea6(~8}?ztFYE>}<6
z-aIaZmXZ0~*Ex_Z;2K^-V<9)ulnJ(oi=Ga)nCnV|i4x9-7Ouy+1v{Wo%B`U!dl`3R
z8T!h(#gwo)!R@6;Tm`2ugL);$(etZ{>!R>aHOJ7Iu9Ms~if*6c_BBJKhPy?1%hOyw
zz1gFdYo~Z?9e4f(6FSduW*yKt%XLy!Ts^m(GQ;P%GxTsf&+W2;Xajd?21FXUwNyQE
zfm2<A`6g~Q*=^?5*r2h63zR{ml`Gr{^)_zl7LazXlIo!^a@`>qU<X%EDTGe0kG7qc
zxI^i5*r1CGr~-SLn@Ew`Zf>0hpgo*O=T&;S&nU9h$E|XNYyI4xHt4&;1<Z!Qt6VcJ
z*#@}evuGUT#tp*Y5VtxTL%PO&MM0$NoIDAR4s&~H(|?0|tqw!F$>p@bnOodFJjP72
z+uU;c4DN7#l&rhUB?#a~xZpW3agS@FW&3@u<8L@K%Dq6A9&q(^`s5+^voFXau9hBk
zkGaUTkbJ_me+TuaTu%ukpK*LL#`~PR6$Nz{{?t1lu6)>6XmsOGQdyYEo!>?4W)HrC
z4h!w#KRpeHck>P|;5_-<$?(aGAH4ujZ+>hIeDdK>Y(<|hKR_oK{CHhEEcx>uccB-+
zTT#+DkpJEdeL?&?7hq`*zw{_Xg8A5g;Nf0=xg7q6@VaJj`%L`K^)M02Pd^Hc{d@w&
zDi82}ejs6dgBRxOAfM+8{c!#@N+%uS3%-M;2>vU&XGikaLm(2xpZfupqWQS<7)uQQ
z$Cn_n{0-V^#_{jd3M`%<3WvyHzRDMNkMQP;p_jm$ZvF?F$fwZDu#WO>!w^m4wX|1D
z=5JB5{1`t(Gn>MXi0~qnU-~9M(|Cq1<aB=AFKEo*r`&)@CclL4>skB<A7F&pe7Xw^
z=J4-R7&Mo^L2>as-t8b1^7-WiR=_)(s0O5vFQyqP;zz?_zL>Av2Cjtv=Obtw=MT^;
z4NCd>>p;r*l`Ei7&Nu!7$rJq1DVV1U{-;&2RLPe<hTSUu!F_PmJZpl&NxqM&XHW5r
z9;Aj>Z3a2b%P1#T%a=x(Fqd__Z#p#2@D5Zkbe3Q0f}z#(_mY8jj-QhR?mR!N!zdbf
zOIngQ@@L<KYZv&oQJ8PyYbl4^%=>NzY2m-923RX!N;jc4KCcXx+WF0s(07q<eGZfk
z{;O*+)XC@NP_gAD{vZ{Ubn&Ms40@TLZw`%a{^F<LdiZjBqe3sgb075k_(lpn^z*K?
z>c7G}P~h__KPL>J1H4rU`Ud$06QMW6AHzuk*){&<ivYXMZ=*f<FkgQidN=sB9T@dZ
zJ{qBZlk65RbHa6Xo3C1eq21y4QvmZWZ$T@B5#B2aF!%VNOCb08w<z&7$|unaejf1S
zX+QOl&!+3@5x<=736J^JA42j8|HFDTKIQ*&fWc>chZo3mep4p&T!aNyKyejxGT1Y@
z3A^&q>Mnd=3co#sDKd!e65{<Kvs;Kbgg#GU53QoTgsv;V_7>hWz><#;#6sU!sFz@9
ze!?#^F(!Y(i)yF>1a}q82MW8XBqB&qxT0~7V6+Biun_bn6!r>L*$@da2^z{+>=VY(
z<cA7RC~Cc5n0_DRfZ)FmmcoQFZBRTY)K@|>T-Zaq?n6SlH~J!k85<y(BHW>~MybL}
z6nIG!G_)>C7nV|-I74Wqm`<i}c^KDBmf%FY?Q9`|)`&TRX$mbTbA?7Hc$z1OrSL6Z
z=-vsL0-@kA>=p`<pF^=o2(AKXv2dddiX}qcT__wE7E^SwRA}Zv$^_0G3gyC65tt{0
zuc(N<LP*;Ou2RTp1Xm>(sHC=9Fry{)NnwSFwl}AQAxhxY2#!=4d|C*74JK-Z{6|2m
z6DEBN#WRA}Pk=cq#D4`#^}+~!N6raX=q_+xXj}=`8iaQu!8HmSsdDpzkh~F=ngl(?
zW}1ciY(TdNOK2C_D(t7YcAJoqM$f-?;Z8hSFADcgVAvhPb}2+Vg_gHq>5`z8K(tHv
zno4pn3%jYfrd#+o1SWcf)pU9E3fU{*TA%Rk7J&5&U(SHY6`_<~tZ-GZJd2SH2>ssy
zY*6S+1Q`;T^Ju&#M2%AX^Sbc43I>OTL8_3rA*`h0@S8$ZK4fkQ7hcAgZVN+UXuKl?
zmxH@2r24|{h|o^sy(g$?{dr#qUjdO(;njYiJP<UKVg8};A{9qG5}wjK`5y~6=AiM3
zpnnM>PlcfZdfCb|!HlBE&xO+g7=?@Y?FtOdRV*n0=O%{Gs?uHb*bYk`Vh*hecZug?
z!R;1j(-+oL45Gcim)J~|s@`H;B@}!_?Q>xIif!2-e&Q&_%>Bi?OCS;;KBZ?&pjdYW
zdZr-J^C-~vh)ws<8Z6e(C$m@li54FrV&FqG?h`lcg-@YkY$1HwFWPFs9T2C{3A`{d
zoDL@)6qzqD`f$;Wfrp30#}^?PAxg7gFj749J4B*HW-&yf#bp$oh!O4PgNrqZeSvT|
zPV{$&7xAJ<`>?~}aVi@;B9=#iOAuE(p)XN<{a0ul6>rfFDoMQH36d;M$cN-HaRq%<
zQpA_`04!DP<H4ngn>t`AT|Dz0)H6iCnQ$gkto|GdSz@vSM6yNG9Qr=wh|c5Dnk#a2
zATLj>K7q!3(dG;k3q(E$qJ`pV3f&ipL$oj{7Ik!AFA+cJ2k3FJFdYh|q8sgZ%S5y3
z=qneOP!;P5@!}#hR)~-GgR2y?RgkO_zcNE(wHRWew>+E_>jE*fQ{r^0W2q4<;xX%|
z#V$&b)QWNa=&KV;=>c>`TudqNvtl<@;?#>P&Oq{<I68v9^Ww_;;2Ok%cVNCz?D_)a
zf;hY!7MjH0-i2PXI6&d57O~O{&a{fxey9Ckn|RX|6V)!hM_Yo6V%6Ia?GQ`1K)+Lb
z91lyE#G;un(IuW_p?FywdL2G>i=n+x=n)^^1WK={+lry}iEA&xM8CM2b~#tXggp?s
zDw@Z_!hkq|?$U!IPwxsG5-YD${N<YXRySm>i?8p5{;;^I8s=|^4`@knQ+#j}+$~Wc
znA@Vy0)XBT^|S`LD^8{j_K3*Rxw?Czo@xT_i&IkJ_NchI1>6I%$Q9f}aSIj5KN4N(
zNabVk_{%_fBF>vg`M;-P;AF@=6Svbg<+(WF8_2k*_p@-(RlST>EpBRq2AsQkbP#<W
z>YiEfDMVdM`_+BwX~)qQs@6?G-+uLsH=uAp{r6n-g{l4TgM_OG_CVo~x-$+U5$Yop
zxQtX!co80&qSVvR!EUsA*56=b)XTKck5%8Kik>*NaXb8uS4#-=uzINiibvF6P>3}_
zy>2{6qWaTdkfZ8;dV^V#`j@egOjh5q!^d<?9YUeI6m>r>2~yQxZbM_b+VV#zWT<`q
z0Le6|v$_GArB>4Am92j3K1hzbj{>&2>WPE!DNp^42J@A#9@av#K<z{EmqK+iy%(%V
z{Wfh~iq)UJ3cDrhvsB4^T)lZR`byO|%y5;Ish?4*pj`d@Dnw4G5z58aL0wHJxhvJC
z*OV|(rT&eoaI4i@=}7iTbwoQXol<Xd22725F$H5!tEW-rNv-<U`yh4ddS`&1QJ?t)
z=Fh61kokJ`q*$PwQ=5f=oL6s+L1Tk@GZm~hs^_#o@`73(1Jb1K*a5T6>NryuOth$f
znh()db?6b0Hg(6R=xkSa(daL#U$cNnhr0EB_|&ORGhq@hsi*G&XqUQ?&R<+s&r1bp
zxB8DM@To`LN+ssK>et=@SfBcW3!Ld!FQt9h6}99N6t1dgXQ6RG{pBLcKMbnJqyue8
ztx>|#HT9ma(Rf|GYYxb;`brDXZm9Ru4f&?pLJ9p_>OCUJZS|Ss@bHfMXWHD|Rd;-a
z$s18iJuyM|)SKuPQTNrae+tP_^?*G*e4tLXgx!Z~6|EQ_sUJDfVY|ob*X<$mL~Z{X
z(4ML_28cdWThR01xjLmDc3m_JBH*E`X7V_2ZkiuxQR=QKv<2s(aidbiT^e-@KzD28
zZ^0Q)jX7mMy)*}?g2P*Lozl`in&TtD^wn70fx4e&Q9Hft!C&(Sr9A^QW9eZYs0pHi
zjv&qLGmzP%38{d7u%>P`MD}W~)5APO^FFR2**?v8mtj6s(@7rg*UV`KIiRV17YbpT
z2UDSbP!pAfISkj-zlZ@I()>OiBtkRW9$=B0ZFB{iqBN<up%JZdr&G`|ngJWY#A^P{
zgJPU!ZY8*Q%{9sh9o9sD2JVRF3kqZ;Xd3A)0EwE;m*CS;jmLV3Bx%kk0xVf`fPz=Y
zG#hCzo1*!h)`+Q^x9>nCO*7^#K&NY-t%XR2Ni$6eH!?K?Q~{c$abJPXY)vBF^>Q@t
z{sjG8%}EQ0<Y`uJLu0<?yC!f2ny)D2Sg5&6ZwM&T%sB(SVoeiW$0eG11{gf938pMa
zsm72756d(ehtXKB@d<~a6Pkmu0ISlNJTt*oYo<|&`YFxEk72MzbAe*Xr!_y8K(SWy
z8CB2MY4*N_zB8I0x-8FXX5WWMy(V`nM9yhysqpl?CZ4YK2F(dd<~M2_cA@WrW@Q=l
znlzR4Y-`q}QH-QTQ?e8&t(vQ*5wx~xPUPaVZ`T|S!eB0H@;`!1r)J?-XuPEP;2A7+
zX`WN6{j%oOh2Xk1DFwjp(R@s&ZF)81YcPmD&A(Iz-mmc-2h1y)H9m0Ws^%>!MH<kI
zZ-L~X#+=r)Lz=J&P`{@6?QdFtUf2AZ1v0E@T?Ww`nnqev-_)EigUl_>U$p7Jqv@gC
z@m<YjS^$n{yzYYB(|q<G^zLh}s9<SSlXwpPKG2j>Ex|)g8EsD<X%@MHd#o7~4)aem
zap%B2)hwh{(lgDs9rUvI=NjAR5OvYMdIzI$)n295gPV3<ABekFx&mH!XxG<4W0&@I
zDh%AMP5BT8J+<8>5b@H!LThnv?YwC~@zJghK%=iVX#jKKr`<sbU4QL#D<}kLyU(L9
zP`l`V+aj%HF&%c@qcz<?Yq0hkT4(IlrcHp0A==?SkbT;5t?)Zko5sTYe(g1is2$Mi
zD#3+mop(ayp!WVkkZ`TrEvO&Tmea)+q1AtaPcl+lNJ+LRt%P<2(b~VLIwVGGJs(`G
zcJ2(gZHm+SEC3s?Ev5Rx!&>1uoH?Qmr!wILt(wIICu)lh!R}G*)EVHCwC~YLoMf$n
zHs8mzMLRLH6m1K=+A38WDMMeH_7+`%>Dq&|YR}NN$Ae^Qv*|QbmNxApc%QA6P6wA`
z(w58uo2%t0fsm&iM_-bB?eBCfw?O+l9nL7!-rS237HMba0lQfHRUGV=Xva{h@3?j~
zhY^-)zuJMuGHocW;mfrjp9J;^?Sv>yUWK-wVo8<Sx2dqcN}E6jEvvN;wt$?}nqH!n
z<0<VXZ;ZZ1`$Gckp4RRUfETseSBqi3PJ8c5aA&j={)Na{?Uxy_RIhcQEz>z|mID;d
zYcnF?OoMi02S6LO7wKkwLHnZ=2Aj0YC`8k&{gY1jwP>rTHmy~=imIgBw5g^C0BzUK
zt%J-(ZTW}bI<()>A)`+1M>ZJRC9MZVTD!CoM<`y__Ray<tu=oel090pVKnw?znch0
z`?N=1f%$%|)f<?E+u9$B;L{y#%wZ_p)kaW$Xhd80JIFn)j_#fJwd_2a;8Cq7tvDZO
zH`D&_q4serxJTL#Xn*op+esClPqa={u=7-VhIVDowAFEdNzqv<AepNBvj`&Ty7qAx
zM5gYh8Tztxe}uw|Y~B7MH0J1j@ke8>ZU$}q@^xe5;dY_!n-p4q7U_;}f=r3-&mBNJ
zuG>x-&Qe{PoIX)q8a-snb;3rVozT@h1F6t$i$i0juAHvtD&4ksp?*>~BbGi%osbS^
zYIKt=AyTVTQ=LPdu96OeoY4)ujK;INnN&1UulpDgbiC|c*Z%=#=)BIk0G$oGPKvZP
z>OQ5F?gd>RB^;Y{S=Hd0b$@B$cZ)8E@+Gah&tuToru&n2Z0)+tDww#ayG_ri4&7}^
zzIN*7Zi3_`-6*ZoyL8WfK;vcI`vQFG*RAx2qox5}XeVF>bxSETG^CqR4D;7?vnb?$
zUHANLkYSw#y~^Z<t~wAJH+4lnLh`mQ>1CkZ(Y;Kuox3{gnII#&^$*c_PnVJfk^8#K
zkKpg9ZlMJlALx?Z=;PHbpbED~x;5$W;;~8B?GN^e?&>L+c&d}qqwbk*GQ~5V>xMo8
zjEjEjO%PZ80(<ni>EEVfweI=~ilcbwr>}!gyY%bsKxDW6yT1VHsrQ|OJ}-UGK}dS*
zd+79uk3O*h7JT({_oC5HKZlZQ{(94!wAc#J*BpR;p#I|)C<f`B3;+$*_fVDOUVY0q
z&<N2-QmSE}{`N|k2-UZA;bPgZH}i$a0sVXQSP9dQP__6$ecozdhU+7j1MHB#XgTyE
z^pO<$i`19CgT^R*%uy&r>pwBkGd)IsQUS$SeQ7(e<MsXVn6Jb7&5JSKBYJB};3eqq
ze~T$e)aOw+GD+Vy2)$$ajx<<G(f3m^Pnv$qYLIlj`DTb@=)cN?-AuiPz_RpHXe*wr
zpW6rvx%%mMA(^MYw2tmc`TDc;O)t<VjKBm={7}5NNIxzRE*9%!rvj!#e<lRnalI3L
zw@dZXW;B-RH|o$>uGdqp`h<S=LV#81z4rm7QXg^<jaB+yH3m_w_oM6Lq&}SrW=`qv
z{tA>Dy_1R#`_$^2pF*ZiUqqR=Gx`y#PC2VzMm5^?`s;M*ozsuuF$w4O>zmQ|NS~7c
zG*9~%C|2)nznNm3KK5ES^zFCbN!gc!_McH$KEnQ;br?&uea{%E$Ju{)28I&t7tpL7
zwQp&p_)C)g%e1{owtvwKmX6swxBxB1-u5$ik!r7}=Wd$4dL_-Q{o7QxnqePCtJzHZ
zgqe`cvJa-|&bI%IO3iZY?I*!Rp8e-PLNDKb(MM=JVZV;HJ{9)9^Z=^2_n@MObN16a
zA!#~qzke0%HrTKK1Tu~GnJeMU1^c%aVrWhFDhl*A+grB*rp1186706xSFM0zoBiT)
zptai%b%48QZ}%5KJM4FigI=foM^~VC$-Xrfja~N9uR!mzz3Ef<)NQ{d2Yo&Em9$>&
zGuivt0=wV-Y!T4h9a09+>f!JcEdq8qEdLvdyB(sP0D8#5{|hKaI7~|d7wHf}YxyXL
z;0KV5c33q7T#Uo6|D|~yj?g|i-l3SDBS#ztPXHy&p;!wG=??vOFx(7>_iWLZ>0p}j
zA3monhgb?oWIH^q0+-_uwFsW(I)n$pQmKPKW%J7%rh1^S++m^vNUg(j`Y7rgGQS5o
z<B&<|$FmMgDUE*4p@LFw4Gu?aAlc}Uqk%J*9J=Ux-{o+WcI%fNGAMu0?T}<z0ZY9O
zw|@jopTjyi$cO_^<qr29<Z~f9>hNP5rsRP`)t~r$9y%PQ+w)_GLb}$UI4p2O-%|%~
zYjDpT{`n8;E{@g|0C9E9Jq1ZON52K|!rjs6jXn>@aqB>KId18~=yyB5vx0V$UXBBF
zVR$>*wt@IK{`oHk<Lh|%W%%vqIQJr8{2d=Jf~5e*(GS4|I<BI}(H_UFFsKJRdgY;S
zuj6#8!whjeb^&_(96K3+g*sNh1+e{&vm7zr1CF!Tpzok#EWI})+|g?hz3eu^@#Q#l
zMmpYk7cfU0<2R!-!SUN4Vd<#jA9O(^Iaa*{a?G)tDqd0@H_^^G&G8b|^`|>(Y4MQZ
z=uP3dOvf2E@FL5xk?sQ7j`s`TVUA<(hv>_7v?>J2a~xd-uzbgr8>s%Q!0~%Kv=%wq
z7Q=3(qfA6+mE#JkSFd*b%MtFMblgby?o*EIPolBLaW-8Sryb|eTCdJA{U^-j8Aq>3
z^qqA~FGpXq<BD21+Ts`)3g|A!XsYM9?D)cqaIM>MD(zr;9A|Z5E=;|SQ8Qq$&v8Nz
z^!pvZp-SQ_jwdz&=Bnd?qcA_<c#MPopyNgQQVu!pr6PuFj<2^v^19<@XLu3xV)rc;
zrttH|DkH4Cxos7Gk6W`3zPU4t>D%GKETz*=yO@ywZIqc;>4|6ZWajOJj2H7JtyR65
zXY|bRVJ^~#;L8krC4IpxoS8~X`yA$K3_Q(cp4ebc^O&uaAj)SLx@ZcR+%Ry3%r!57
z7BQdw2a#gt8kMG(FrTr|JI=hk1P+%nX}@6jWlSOETgpw$m<f<M!L;~-tzbT+lwT#&
zN00wnrhn}VFPL3rX4Br*gWY)<`n%Y9RByYR{pUU!Jz1kG6uj6CRB!9eW>fi{59{58
zf%>xhcA(LZT|XNN{;XRDBm-FePk;_&Ke5J;f>_g7sxaEazCkAtg4uSh;svuP)}j={
zzQFop_ieUYqJIxCzLL(1k{8VONVa|o>`=+QSK)8Cq;(e6wczJHi_`c$^E0Y+`mj0>
zG9RTL0rae<93X!mKs7Nx)%L@^_1;v)=rnFMB%MvaP$=JvS$`5^^JUE52A9X!G-4J{
zFw0*3|DP$JNsHfSk~irz`g2LX0uH%In<Hol(oIy7y+<0i9bAn0GCE@uYo1Bzia7HX
z8-W*ZK953fmz7r<AaYeX?k4QtP<qZppXr`bQwz~2O8XDNy4$`v2JZUUuBBQuR1#4*
z?||+8t>B_;UDiVKi0u#biq8aFvsd9oqU}@4TOYO6dZ91L)<o;vWZR{`V(7<g3+e!t
zVjE0n3{!2-`huj{cJIODWZO<%3&|pr?UCJ}Cv4yO3}`jBrzk3T&bH<|=(pKcJO*gH
ztz8OWF514J0@q<X?PZwnv|YR$<c95*FCcl-cEV|Jw`_M&i1D_qIVG&`*mk7A;9Xn4
z@fgI2t&y_t_iWd{0)_jwcYR=X)YkOS2{I3D2g70hk?o6rK<2S+1(mctvHf}>3_i8p
zL+j&bwvPs&@!U4;6=1vAy-4eNSGyQW@VnVrc!Tq_bDItnFT1f6-1D|GxkJy#Zs<Nx
zeC;;So4@whIa5VVu$|{>jB~HucP1)(39(B&2D|(0CUpTV-YzVKX4dW}dcG&w%{mW_
z47>g(FrRH_xe+5Qvb%K+k{x#T)6myxS5Kf_cH<*KF5B6y1?jchy9LAUv-`*amLA%b
zUB{*4qI$x?o}cR8XRzn5a&0$(hN<Q_!cw&Azz6U<L6u7>&{UPjb?E1)F8>8f#VXl1
z@To$zjWT?vRlW}BJFmJi36iZUTS}pHsa8<H@rr6o21JHczbuE{5tW@EoO!Ie9!K-U
z1=E+rn`^g&As_CMC&eFpxdRla@#7BQ3nugDHfBI0fLlY4uRw11DhxY_`?V3=9`02t
zzYONaP#y7JZu?ZY9m17&qHiB3rJPMD_ZAIpKezrY^bT;J)uJ(;yF*1Rhq=iWP&mSE
zrdpT;ZZghS;IK6}pMncVx!4}SByn4Qh5IN0QbY6@cQOGag}X^hmsIXN6$GVm_YYxc
z>0DqLBr~{Y+hH)1D|!JwWpQbbU@(XKFa(mh+=ffg%i}UnKp~&oL%Hb!?w}V)A$O-8
z_Dn_Ga5YUZ*GmH};il7>hT~iwZ7EB++O<$D<L<lx(Q@vUP*^&_-K<4p1s6$`yOrER
zs@popjf=*ZTDZsm0{aqo(H#o?T+2)F@H$sc)l_%6Z&so4G3T`a&`-FECP+Rtaq&~3
z|BQ<%L+5kOllI3hJWs1JKYp_uGXDI5cwh(ct<xbA$d5?{Xb``e>dW`=y%#V+dwG|2
z@F|4P4*=Lc{t87XL;2iQAp3d5EAUb9e{_Sy@P$+*6w9YZgNx%$ho1v2o=={K*28>%
zD`1ZBsz`W|z*k=bm&jW^hiDRiIucwm|57sS9^*flhIvZim4{(Im3N`ip)@{u5R&Qq
z=-(h2d~y{q3;D0CG2SBn65WlD^COOcF6D!XoaSFLeG8acep@3%&+zUup?H=boB*zc
z4|;@QxALD+32Zx`b`<&-d1(qP_3`04IMdI+5(4fDe~ngLSNXqgKxBX)Pg|8izJ~%H
zL;R9cAlLYHWd1rINDu8{KJ+gr+~8BqO|W#6pY;K}xW%W&gS*YY(+|6M_~$zTbC>^<
zg4Or<`AeX2pP$CzGZ^LDKLYoF|9dgWL;eZfvmf!&TX6I-pM4INp73j^_~t498m(xb
z@m@z^;W<Bp*2gY_@B{Qv0TE66A2%U{>gnBu36G)ZA*7e1(_e^v5sd*t^K&Q$3USC4
zqmp6b7N7+S3@xDc3ISB;5+b}rSJ^(Hkv6Td!Ul?m#R*@KNW9Qq1@5r0W*Cx3gtzH@
zMuLz_^=*m5R(zl)*-_zm3lx)tw~oR6WT7DloyUZK5<yag#0zjHRrshMuB8bswD(OH
zUchq^bq%9Y5XlnuPX=hVP=5tnjv$!?E?3w}eR)E||3cQnl@-t{5PGS;rciLE$Yzny
zeipNBDi*$`Ol*nZ90M<o3$>KQFBPUzUZzawnulSR3o|F7@r2;^5;W?CLdss86UP37
zz6K#Z8G4Pv_&3nlEG!fu(jo-XR1OP$F_^9!!nrp=9t$0A=zAgzb;A5pp^VPfJTnPB
zU!(Q8kmm{w7x4uip1O)r%izA7=yU~k-Ni}ti1iTbx53~paXv)~cZ)fT(dQ|OV}a%+
zI*$d4x44(yHR~hFqQLoy@6s~JUtB3iV}N*QDf9xxGgN&RB!<3)zCEHTs2bS8qS%Vg
zz2Z~KHHC;$O84&*+h}G&#aH%$+b>S=0O$dcp>1E7_$^k3NV})dk&19}0@Xt#imBmf
zJSwi5hsGrF#h<_>i%pbPJtiKdM{9~0J_+h+;*4ULO&3#4_b{dmaWZX5GsWp=;6;}B
zX$UN3izDYiq9^=Cm13C_*6e^YSrfYI0OK|B^`$V;I;mO#6Wx=ZmI3AI)I$`@d^Xi9
z0gb`aQdWQ*m^PFGy|8Kj(IY2(+M*PIWlsz3h55>9u{zrSR88yt5;AquO!Q5^I<0UP
z&=O}z8Z6-|em1;9m*gMI`+@#v4`oj_&a{LVf3*+bx05?9*0weT0)JZ<6`;8=cPVz@
z%IIio?8cNuL%@gG_YzQi8P_^^;LoJfYIGlC;;FPKl##E+SR<L$Q9y}eo;{$EGs9B!
zB{FFg^gGJDOBGQ`Ov@@vRWh@BIzY1+Yabd9<LC@a#mrB?fGc5|UI#hORJ1^^lu<1O
zSHs+Y10tuH-EF|EW!7GTg*s-ssT`fnjBz~BT9~)YF#)a226{lXF(3P)v7333Qae4&
z>z{%2GUF%`*vGs&1taWdY&`&ag^8og-Bsqpe)J768uE9L`6&T?x0wz)|9gjdupjDo
znFNZHjWD)ZP`}3*IQrb5G7~AE@Qi7tda~zCMiRVmVPB@lvMXEBh(<S7dJ)*}>|QE9
z^k8cUW*57GHe0*dC11gWC+ign5ij<qCBXJ(mw97^KJ4#wPxWOVehNuHwvaNF{%qC|
z{0(3Ylj!_!Ap1`U*dTV0?s$9H5~Ss^6{w{p!(O(T2U-Zbo~o4hvDeHX63U*YsOo<9
zuMOxs!2a<AOoXu^v*74KHcx;^IJ+nqJ{@AazrY+uux%86ie$%6g5D7pwFI~gvX{!J
z{xpp>9mHVLS@&bm$Y32tAd|`RbndZ`ojHicB6bM{G>Tbf9<WQ;Pu9ckarOvRO;oeB
z^cskh>~eodo?@p^w4sKbX@vS|_WmNcR?AM`3WYk>D-F;W+4$?w>tLfPcV+5iUs(>t
zOKj|XD0Z{^uR*boz5g*Z`q>~q=wD%r>0H27cJH_J`LbWX5BCSzE1RJ(#OB$c?;0D^
zfIb(=pfeOaB|mcz36Pk*1cUn|?Q_t0NRsvpcH<=P{sIfhl0YinJ!X=;c?2{?@)}*U
zsS@k?;L;?AD1n$Rv95-T#S;Bxm?)9FO3~colB8GRTB&4z8$`+^XSC=mm(<$Ae1(Li
zXF;VTo}v_0k_vkHWwpeHHsL2Fp??DUl;n?gs9%sgtcMpDB_^wv0MjFxKot^$lIAUF
zy(O_d1&vY34vNS<lPvoY8oQ;x2Eu($X(_EnyrlEzf%BHOo`wk@>36hG_m!@rNUxvt
z$!FjWNT1$^zhTk{x^EnmR^9?ixU_3I$RX)X$|yxhD@>n5CQ^ERE!>ZmR?saXMjF`w
zm{{p8I^-88H6H<qmj+Tz-eIXhNtci`+W@^xsihtKEs%b_5u{8yb`E?xDeZ}b`dR61
zx@4QA;gevgLwb$UkiF9RkI{Hd+C$la>(Y<gDE>Mu9UTIDL+U}huA9<Jn=$NL(wC{!
z=C(BIA86c>7Jmi(XVR66;Kg$(N2^>H+17(_%~fVi<y~&F8(ZL-yX>z7D0s-WuLtHX
z+1m*iy{Am_C;Gf(kLZEsEpv(in2)UHMOuIO%8C`x@RJ>-1&_b1umC0kWIhDCU*_%x
z(F3x98gOB<%h7;2C`%=O!)2|0G?%gq^t6hQ?TUhA6wdxZGFqnH0F)Tn40jALRu)D_
zaN=YRPH-k(Hpv<&hh@=7$(m%TGP?_qNs~RK$XdFr_#<>?;O!hh%akpnd_WdnWDFD8
zvgK)j$&rnVhQE2T2HJe(%f{2bvOpF<>83(i&1KjvlKo1TK(VaR8(<}}t*g;^9RHaC
zC?{pxAH&`$nO`OpOf|CQRI7GcmO?d2wX%b&K<e=3ao9z)xE(TQW#6yHXIL*wpAP-=
zvL&rRYmnW24JHsmu7KMYWcif-Y?AFb4z5{tjE-2f$i`AKrd9S6<z3qFzXt(*1uIjK
ztFlJQpbeO0KhPq3P`0c9gBg<9x}x)%Y`i6~hh-b*L;r?sY%oM`${r>{<d*DDy1Z`7
z9-M>Z9ogMf*nKYh!4-`zW?FYR>T3301=QWlHv0nF-7MaSJ`c0HccH$^?Cu_T=xNsB
z2uUw9)6|>5_BQL71=hz*dI5^QX5UQ)sGr&RP2l{^-h2x851KtN15CJCei67sW=dL7
zMwsQ%*D%uT?=QhcnY}`{!f3NlN_fVYh55n5IJ3jWfQ~m?#eh3(*0dSskC?slEzBmE
zy>A+i&P226Lzw5IW-EiBm}Hhy1ep_NcNgM=tuRZbSZAHti88o<$t-*rja_CsT8%t4
z3%&rmiRLbGK&v#5Uk9)%^Me6s>@ffI3>v%4v;3hxWWGud*KV65V1|Xe`J)_wJv8?^
zMC%W4i_){u@UeK865$~h3sYe}$|Cna$YfZAJjWyyTMQS&Zl%Qu4H`Qv+8W^KZHvw@
zfO^Vz{*1m5`2kuW#L6?x;YGTfF9v3g{Imd(8u@lwf}WPY`VRDb6<=ASF+gEur2J!`
z!jZ1^AVmUgWP=qu-h#t>6%(l}dY|GBU3#I4t)uY!pyHkFkPKHiI6&l(V#*LiA{E{H
z;9-<vo;?i4DJp`%#VZVY=p9zPOUt4}MUw*R$%@~8MPI6-tQqPVik*H`|DC1K{eaGF
z#is^z<|-mWVIohlgo+XJ6}A-ME>L9CSG-nH=Kyj>p=-b-oKvJ)p|4RfI~yjN6ptuc
z-lC{B!HYJ<i3I@bP%Jo)#%{$SRD#LeEGJM2m4{`<DR8?jH&Y1S<Yj607p6PFvcLe*
zAj?e|AR(4#CqX~d()KQ<B+POTJ&X@ozImILgZL2?&iMVk@C>g0@Cz07E!j)QmX|hB
zG3t-YDEzd{`#E%fTK+cvUM{D~yPxx@dSXSwL0DMnx)N4bMVc6p)%BFhT=TXAe*dy@
zEY#L2GBMJ1<+OEO|23rujbCoVXq^_!z~5VM1OsB*6mR_PY?=$u9d5MP`tQJG{Jrz4
z1URM>Tky9lGm}DSZp?p1w7E0!dMNrcKT+*K0OQs6zt5l9IRR`C;}s4P#{4@4G6$KY
z#Xt{dY}a9=X^hu4c$LSzM$!0E=J*K=>Ljy*R>Ad512)0`H!WUo;EyQwa5GFtv!}{|
z7sI|nna)_YVm~~HV{4k>Xd-)=Rx(G~O{QT0rm}}yVKa@*r-FlYmZQ4L9QF=XUgxrX
zb3yXh-rXSitbPOZOV}krP&m$d;|Qy)l(nWJq)K+;Uoc<AKFor8HM{6EBx~9CJz%$v
z^{2|S^Xz!KJQ~=(6Y#u|eZimd{}<TnwvcIK`8nX)*%iUyF0z(Wz+Gk^y#TJ8oldKc
z9`^Hb(C=lttDxV<?yZL1L3TSuLWfu}7{k8F=9i;!gk8TE3isGuDNw)97H@;zW47lt
z=($M#r5oE_d88k$Kkq3l?=tAc&od^R?y=9A5}F<tHj(Q1UD;F@jKqySGzQA<?ATmb
z^I%^|1lh$(>0t40HkAqiJ=qNg%!e17NBeAV*6x3gS#~SsWqjFX?Ev#*x6H$5=g;2y
z9rglPQ~qrj3}j!TgA!Q7-h;OX+3&K^8P0xRjJ^c6ZV;A^vZtC9|L3KkrG4-Z8<#?M
z$)oRKap`&5F8^pnYm8+R3FD{TZg64wC%r)Uc?-SrXhkIzoUOc90<cwU|AqYOgmF~=
zx2A&9R=*ss2k6>WUg%i&<w+>~x{HFM>u*m1#P6N%Q2VQAHjHgKKnd-w$LLVRwxY3U
z_h9@MLU|W+pDLwyGp%3Kn3&&Y!(b4z>>R}RF!{D{D46M^C22UbgX*6TF=eJ+xE#UE
zDuWAA%<aF?8p|9aGl!X%Y(Wwkk9%lLW&-9yKb6U(_chfsAJHxM91}u?80VRP&cRXx
zlR{<Cjm(8Vz_l_ze+2bTW;gArdYJd=@*iT_rRclI^i!?HBj)W+s{eY*XeI*fIrI02
zz;<QVjsZ**>kxp(T=s1wIR5Y3)uP8A1<WV!K&Oy7^9S52VkSNTU@`NN7JVg5?o^QD
zj9`XQl`?Hn04ig4(H^^oS;xbJ)6BY)P_Jc1qtRH$m_DL(*BRz5YCX%`r6Q<$riN-y
z&M{A@hPjt{k)l(5%=ks%`k8Jz$A5zvp@7{@#**gv0W*f~_79oGmjLF*+ULUycXlzY
z<vmy<9WC)^OSgjruxBX=6v*D8!z2gT2vZnn7@L7K3a-1wZ6I;%tzejsXTPPb$YJ&e
zTG<?7>;4zwV;9oxF`adwq*(#$*^Mz3vIh%bsfevBhk7yFO`C@*_A*rlSF@cFP&mn2
z{0h6L*le<Qo{gmtc>{awRTDHCS;u!U!VB!Hw6W=A4fH;>OZbAJuZx{Um+ED9@Co|5
zS>t5P(+~>_wCV9wqwhK!K;fZbcJp^2H&`QWy>7DMW1xPE{pJ)V=r-H30}6N8m6RpB
z%g&+O&j?$!oz6erW8-L^@3T$xuZBli<_bK0z%Kn0Lwm^1q}B8z_Vsh%9<xDIYx;y$
zt^(Rqwwfxz{3Hi@pm0!fmzG&ElF5H#EQyjpawbEvC={eh62AtGZIT8Gi403-8qw$~
zox6$lpApjI^x>sRFTV%h%A_S!qEs*a`3tyzN!q&=ig%?cMv%wS<=OxL7I04XJ>}2Z
zv2-Uf*>qZ-U&g;-!_a$W>%xI_MYd)uM22Kt4KR8G|05I-STFiRa#YsxGkks|n_zk!
z>~p*m3!)xoU%vMO28JI#55X7NQpfASTekQjI+t&^1k8$gw60zy&4bMEw>DzH8_sI*
z+c1H)3C7=B@wbyG0CTI&`_OV>>T@w1SEhn)N8XH%a$Y`6L?HBonS-0?{P$i)OEIu;
zM$-dphnUiz(HYMK$)I?cnMujc6egVF#Hq}zaga=7W>OF(j~ROh&g3&+)047*`EVc9
z3z>nZP%mPZk3ylC8K4+S3G*lqD94#-XNZ(CSucPqV_rW+^;hLgFf9vCFjbUlu3%!8
z0=trVKzV>F<`Ug!s+mlR<eg+nH$dbRb2J2?HB2}a%bsQyG9a}~_YQ#8F<a;&I>Wpd
z1~1MsE1c0-&#;xyJIB1+j>hv$oDy6E6WI!9Ozq5zdogtvnGiam)WJ;F!cr%*mzK$w
zn18Rri!SEqVTfF1zI+AP15Cg=hzv6G_d<V&c}|&*Ys|bqfqk9XsRqh0BS^sAU=C1<
zIGt@<1F&4SdM3c~*)eTEDP)&ZbiLTb2JC@o89QkSX10QTcQpo6&2GF*BV_lVhhiOT
zO97I4_5v+88(GsYP-thTdqAX@-M9;`xkwgnkfRkpLJ{pf4zbKukO+1{5mY1DtppUs
z`j<gCnw?8!q%my$f3*ILWyer@GLB8Fg?sUAq6DIc*+e|;aMy|W6jl=0=-;52$YxP}
z)lpVKH{vAr0j<-M*}p6yd5m@Kf@BK&Qwk(g*-=^!rm;n~u$0aY2Y}09^-k!^WL+7|
zSRPwLNm)}F`)&+i%GsAG<XgiI?||Q@*#J7YU&~fqhD;qheI7KL*bo1P`DWIQ>c?By
zZ5iNN*&iyQcbV1C!9cs&vvh)>hkZ!FoL+V*MU4B{xjUiI&(41jeOFjVI);Chy<H2R
z22AX0%i!W5+wuoshS(m86<=cuErE8OeYF~*!))?Ih~8jV(2=m4tX%@gDElQXZy&Jr
z$?*3fdzdbwM{G8oDS6C(d=HIJSc_ATe9C?^3*;H=uor#1C0ky?ba_gy(LFOzg7`NS
zgCy<CFv0_p1`TAwBrCeX#Yj>qwi7EUT?dUMNk{~IN|wkei<KoYr_4*X<ohd-ES5Z=
z^3@WFAB6?0B<rb)u3EBuBA`!7e8V7lPV%=N<h&${0#pr>iU#=9D9JFbgy;py@>X;<
zNvda}vsoer!)}XYA-!axRdSR*pEil;0+Dt}<pMZ!QDXZN8apJB*FZWYH+(=YNxps$
z)72%3=z#iVNpT^-x+VY7m%UGtNm<Q)Nek^MuSm94!2DIov{@#McSy3A7D(453!i|y
zE_vxJM298b3DCbGNxlYhTXKTV&fSsRTmkI661P}LK9w}=0=A2^m?~slrNU$Mxk<OL
z1aX(HGosH!+WaaccS(0sD%?vtWCKIq(&{fTGk#LdHLAbymnKmyZ-Deux&i~G5%kRo
zl73`>r$?n-6q?PF<`hArSgN7$LZ#H73c>26Q!>zaO&Y(0K401Y>*dPBs;aj5+56nP
z88o;mJ*5maOA}=t1VqblNWlTb5<!vSG7HLO((s`V2~nKE9fJxgrZPB$A`XN@4vCRz
zr8poCkfg6tQ8E2`zeV-O``+KZ``vTbS!=Ip@9&(m*WPQLyXr@Hu}s*|$m9yYhY(*S
zZXE^72GQ>ZR2Pc-pMzK=OqK#G7XMD6{Od+ByAqym5^vpu(h{-50uFBx?X;J*P5k@{
zlx`QRIXNQ=vO(M>9Cc7yF50%DtwLP81-VMG>`Qcex43%@V2^0s0G)fq)J1<r))r?%
zz&s=EB_soKOwc$}OB=iyfsX>=eNfdq@OswQW5G20<OKXi^nVCNk+<p56V;Z0^XTuX
ziY~EkIQR{DRFIM6N0CDEN&3gDlzVs3snmm+`29HNcknM|D=ca3Srdf-E7`zc8WHAg
z1}&?ZRT;n<ma*avykE;2UgFXzU<+v;Eo3|B4liQ9^h7FV`|m=2Biqyl)q7ZJ9jw)`
z>siotl%27L+zB==5#TI4M(eLec6Atr={t66KYYB((!GJ*Vgp*?%umeF2I3QT(HJ@x
zbCKZ)gKPO($}X1jw4A>RPF7ffu!gCb(7TpBw}ET{+jt$ag)CweTrOhcoB@hi$Z*))
z#<sbDvyA!E^i#=_=$+px*1iJ*yICGh*L&C=%1#_)E#raJvIjFT0EaTz8?B(8VDqS=
z;3R8$fZjE*Lo{QYXOVs3#rJG0ZM6Nsm?yL~v!5z}-DH0AVWNdir)q;+td&v#<$PNY
zuvGBl?Q}`-`Z4Hv6`$Dv&fVOY)+KwmbO6}P*O>zB<M{spbnP4;N@0C7|8+17ZdT7w
zdbLFTC<1Mz>flD0*rFQIUA9&I!UiL^P2EoKh?J?nP({vmbu}(!?PqFQB3O2)XK6@w
zsuMHd%r5ouAh@<#v*jJMt<j{?l5wr3gK9q4X^JvZ(b4sq0V^S&r@8z&oXXc20-$??
z#_u4AQZt{bmp|3mmI5o#c(p^IQ1ieKc8fGiD9XqZK2)4nE{@EH-72yCbzq+hE1G-{
z2#=l+I4HKhKqrm}=Y3$Q6aS(WQoXQErS<P|QPT^oPsD)&u;v;KrJC;wqsl%Yo;E72
z1@@Iu-v#jEJEKXX{)_<c@n~8eJ>c(G!>?cYIhxKp`0n*^sFVNX2<~jv<1)no_*z_{
zcP_kU?81n6m-NQDPX@gUGAZK@<trxt8UyJm$&_24YDRIauSXwf_xq&`!ht4Jp)}~d
zPPEQSqa5Gt6Zdc)ys!-PIdkX@vk)UcNX1y$;XKx#lKY0b8Sp>pV|pboJ)UCFMUGS>
zp2ZSS<b_q@+S6!3{ag7JP?xcyl>j-co{~8gY!&^PK{dNc38q6Vol;=+%!syHPO;o#
z5F1!8Gk|ZI+ab7qnN6fM;|+H18nC;}*cjM-HtJpUw1d^2g4|1%YL2!{UN#hRIs7o{
zzhIvRXLKBVA8TfTkr?-qF2v*xBha5RHv_zQ#?}mhn%~$5BcSvJ(^o<McNRcz^epDe
z1Q0X%-dDl7l%GEXP1(F79hR1H?M<+(=R>QYIFB#w2CR}F4+D0T$K37;wekFK<j?a#
zy3FM&=(xg@TcELtAEr9Wt2{ptQrCE~1KL`-`Yt%z__Sfb+BrliSa{M^%z(H8Mt|n^
zv|rN6-M!I+=X^Zv!7f)H{|2y1y+FI4>(p-((Z@XX!Y4*}{^zUp=+_^yTNXuIkC;~)
zG(Bc{6!dnm1B+nu2`gHUu03V7qXC|=7B>(xxm#FQw|gvv&0MYwhu)RE8-=;~d{RBc
zH*oD7a7rF~1;ow#K@P-AxY=A_rTla{&A(gtVA|B(#XqC>d&+sEGqhFkcQ?Z4YOZ|&
z`ThKEE3l(HoF<Jr{;U(0PVuihpyo7pS%5KW<cog?_6>iXGBiy*jV9i!-03QmUE^l7
z_kNw<@r2wBes~Aknt88}sQ&3DZ=wp!7QXTl%-`ZEy#a3XR!Z_c<e}vLBkp|+;4zmJ
zgmmy>n_%z>FQVG^XM7kXC!X`L1?bvud<4xFnd%uTWm&3r8vvFPRY&`4<?3cCVf#Y0
zq+Nm^)Xb+e{>|!$AHnlL)zccUL$&fn<4g6;^I*-=q?EuJsk!0>rRADI6M@xf7EoN*
zsF~3Qw{L4cEd%FMO%DsWwn7_E53PLd+msqF(pIm5Pg}Gns0Mk5c3ldH#ln&{O*RR4
z+I7y@EKF(dzC>8Rz|iaz78IJ4i#KSyyh7Zk&66r|nH~&##p27r4v72!cu^y^ghQZK
zOkEBy4vSAMA#g-Ywt;JP;!+z7){F6!2RtS|G>7;JQQQaOCq;2j$bBikqGaaT4B`9*
zB+d&<+5`PsxCX+RMiE2T#YJ(h<j<$w`1TTL`oM*j<`YKrgMx`k0`lJOexUexu7D4d
zT<Hd$>{|rUDcgTR>(tOjNco2ChHAg=xWu*7wsoTK{ujy1=?&Hj#{Wa><#6kxWJ+_-
zNX!Cjz^;o>G4mY7_ko2`P#wgnxMjAMa?!z^w7E0KuN{<-vQO|ETAU8fun5ZKh3~ry
z4f==VcZ3(k0g+Eja2^%z1A4S#2F{pV7o5iq*?`u7xFouk=Jw4;L;ODrKuS=kKx|&h
zUG#GP@f&a@vHB6t4ZE#DPxbZ1`Ny?xpf6$mlvZEHE_gskJ;R-%C`smuqAGoiWF_ar
z?YumKrupML$;r_xIaEJk%-CQDTL*hvhyS7l&5KKpjE*-1$-XKd`*vz{yptpG+1lGW
z+B-VgyEr;IxY)Y}B_$-p8G=Hi<Lzv1WvrH4b+fg_=^tOYMCJYd-v)b2e+^&wH(MR_
zH|zhOVf;tU7{NQkWRaD2NcPAWUNbUAtxXx}<zYA7pieZ|g@q)>rP__r8)B0Z=Gi4B
z*d#^iZRRE<#M`ANB*q%%g@ozB6K|8GHzXOr7n&TY$Zxzfy|Z0f)Ebu-O~gnk3XRR>
zo}(I#49Yh(%|_up4uQi6hcOP5nv+(hSt-3fm^L=}!_hv|$M$!0vG4j!uhHk54y=^p
zN<|N8)S~vTS@wRnMPp>if$paA`XQ}JO>lO%&z@#mW^}Ky%y?z-5@Qz!cN+(HXNUY!
zvtIl6nZ0S=-`&~W#noQ#<m&F=92ODc=H{k%817{6;1C)fKHORFn*G?^42OBmV{={H
zdl`re6^_dr&vpfMDM}W>?uvp4UE#Rm-@|0idnn3Hf+&7KbgA%H6~!8xx4gHac)kLN
zZG-Iu`zgvmGr)n0GJ@dSiZYELqW6sihbT%jK^sM}z#YXym73<MI(JhRE-eFfQ`k}&
zO(0j+63CM#K>)=vAV`<WD&z&iPRaqZ02<_c0x#sTS-R8Q`8BzGwr(=_d`&jZ)}^p?
z=^G4@Bl2vpZVLD8FJGIZo6M?Z^c={9%US}^9s&UE1TM*)0KB`id>#Tt&dzdTC`2yF
zf>4m1U1U3<;nF<}%=cvu0Jm_LO<~0BF0I1>gWTmpKyaN62iG-esRx(OWErCe^_r|D
z)W2DpMs#TohyYW%+)3cR>?BYjCq#m$ud6JK1W%H@2NaU-Q2==|2Y~yJkWEo!b(FM@
z22-(I5DoIM(ef)o8>D3nQ0MV7CZ?;k7AUADv7o-?Eoa7pS}k`H>f<Ay1LdAm<it3g
zHA|Dpak_yR;(|EcVC@?{xl%2^B+3PO4;0>q$)0m{gSe-!^Z;a0GGwl9Fg(a1kSq5B
T^cm)-Q?jty`s;%bsO$3|7eVS>

diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
index 54f725bf89eaf43fbbb672f71d1292007f1a8256..0f4bc9acd3da9bc0d8477c38c0445d0a3c298fbc 100644
GIT binary patch
delta 127467
zcmY)W2V7N0_XdofecG<4S2gw)dpAa7H=0C^Ew&g-)WnjgiP5Nu@gP_bE1(oX6c7*v
z6i}3+pdu(>Lqr9n2+|Z31sj(8EZ+aU_xtjTd-kkZ&$HId*?Y>G*+is|yqY$0UmN-J
z3DNELS{$)5QP%SON42ci8eS&J{@?#88Flv_qD;wfD_Za}rCb%fMuCL&jp1ZUrK<Kl
zCsUnpXJzt9&1M6sRI-2ck;{~vYRFkAaO~||R;E{~maSYvWi@K3|M8TODSDeHLS5V_
zlX>>GS{z<mm9n20S7Hz*kDMx-+jP&V_0N^Ec}@3{da18kHoxg!FN_^MRkon%-YnDX
zy(Y+hW_ANC=@&6=8JSEyVHhX-rKwz|E?Xtaer>u}s>ikwWJ{XvIrWKKYT44Jd&wcw
zO#eYCTgFt92b}VcDn`ck!M&>UOwh?UDV4a^tYl@3JfN*yCYM)iR>%}G)x|c@>8|Jp
zrT^*o{g?EEuW`8cC=z9iOr;c9nQDMy5ef{w)xCM(Wz4F(oUE^e>f^riZw{qwKvPD^
zOiq)@zHGYZn28mP?5n1GiRoIUk_~UV*E5D>K{l%C-pnlC#K^vGy0<gK(nZ;KP4}NM
zp{-T2iB0!yn14B5Hnr)#1LOCElTB~B|D3sERLbViy+hVrruyegg-pFbzWx7O7xj|4
z@KnD1B7Bs`Pf(!lzYO3|_qC@)nL_@zf}V#bp-P!brfR!iEmN<Q_W(d7lyO{hLAF5c
zrthFY1($CWWxHC_t&I5<$(~l!21;gQPf@n76<W+8>(6X+<7FPLmZ4w()A4&zw!d{3
z00uE7Iik#~?GW65#r*pfFY{@-AHj6{q?R3Qx*x+VIIEKRH{E~3%t>Zs0ZsQ4m`^rQ
zcBJWkGV{+NQ5MvS9<d*ox!<c~M_W<r&tk$Fd6{R5z2lPWcT_U<G5Jb((DYlfy%)o%
z{Mc9)*LG-r{FW~^%4KXnIT}O8jljjaNrK$WXh0>KfPaktMTq%6omttJe-PY#4PTNc
z%Dy3Ea`!*@EYAtenvXrU29L%w6Fpq?Uw`~#{MC5K6oh;>^#7oWaUp8ivkCu)Rs5z`
z$)5ez<dyp>ncd+T(X3fZ0vsIkKfvz_vUPCU{{TxBS)PxYbs6c@OeynkdXC-K$(kLn
zmCKmL|3A}SO{Sa7E*|;+WLZ4<|Iad^c^Aeh_V4EH<<nQ8=@cz_v<aN`lnW|z-fXo@
z(L$xNru*W>ZYln+XbYqK-%ThZsoFR-K&PEX!E04Qu^q3DBv+|hsd<@#)2Xa8J!?Pf
z%M^RIZE0t|_8i=@we-ppeU2iGv8r0H_xz>hO6DuioR(iOKYL28dON1hXJr2)$7`v=
z3n-iQ0neZ;*~sJiBwvlID_$LyEF_5(F3*<Z`tFT@Yx!H!7oU($Y9p0q-X!d+jZ~^y
zMDl?l=%r-qlSN!zF3{C&8C`V&r2p8loRZm<B$~FD?!O&DfK$2X5M=)0Bp<tj=<?d(
z&6nNAKb5QkZ<k7T?F%x$^gTILoJ3dm;iP{glo-r$gc^hPQOUyUNb=|xy6+uH_a8?R
z)?sxJ%<X4_sdkh3jd#iGfCe%nJRsFSK9cI2<s=!oo-}(6rS=H8OfB@sc4AQElV;F0
z(%CYYBss(BJ|crm&RIqJH!6w0z6+Jw57B*g52XXi%Y~%0*q;i{enI9}enWK6>&bBS
zMymJmt#rNflq84RkY@XJq_g1;IWa1WN`H$Zp6DJV>HM5Z-+xW_yVg=mgr6jnGYX0S
z#T2T>g@wG#0be?jYK?)eb%#i`byGdA<HbasdQv_1O`;kEXAxcT5t4VVB3G8=kbcn;
zlCR!LZh54Vd{7zb7}}GWZQs$gvXUg@R?vMrJ+Zl5gT6y1*vX@cYBH1IM-&}yl2Y~|
zQc7-WiQncEc;OC`{IHzr%55VF6Gxh>LW!a66msGtx>J?x;8=32?kPzEo1U;Y{&c^+
z7ct1slZzVyiNWzHgbZK(oHFL_MC2(_OQ@Qf*YPLaFPcHugy*EWs7W5v<mfOP(GAd(
zvD7Q%dh&I;SKlNTziO&R<~!0^_9K}erX?%K6NqQ+UefIDI7P*O+$RI$yveT_H|Y8x
zo?PMoBc)Mq=zeP}(tMsr_x(IcXX-vOGs-}QziIm6YL-#y!al_I?<p#6I8ML%%%Nm*
z)?+fSY^t}nmUKo>b`X)|PMN3$be+<Ql$LwZHCdwTt|-!ZmPn;vb)@^~Ux{?YA}ZaW
zq3gq+$?(XX<nE@qWbDjZlFVsKs83pwsI*jibUk6?$I;Ie@T}?iKU+l^(+5(`tRTAS
z-RORsoB+QpCZdPgB#$m7&4#AlBB{x6LN)2MbdX#sATtyDQN7n;9)^eUDxoG8QOnJ7
zZ7S_d%=!z&c^Cr?p8skksYdLinzhZK0{=oH{j90;Y5Sb+H>rt2vw@o0e=ixx&ZYY&
zP2J0}EW(~YK$?$!q<i5RmD+;Iq|=vl9kP|I#H}Uytd3-5%L_ac4%yFBNOaLiSNA#O
zZ=e%h2cXx+o2nyuNfMdwcY>O3<Nz|Sct-UQ9rRfJW+%y(*(4ddgUlCuljKwoNrK$S
zyzVxcT*49a;WJd~%~7f2(`7QSY!Y4b$C48N6DjRaA(L}UN$KD&x-Ksy>Pmrh(hid0
zZ!~nDuOmlCrIO^#eY)QeLD=UkUGKjp^M*{i?s1}0#R_Vt=GW-n$#IeDr2d{%jX#iI
z1Gf{YODj@xze-B>O{CNOD(Ng3M$SEKq8JuPI$JZyxx`OR@*HBARz~`pFObQX?TM|;
zI;!6KYb3wi^aRY*65H>an;x9#Hl(z-9bH?FBD!H;Q(e#gK(K&cNbcH|z%TwFQq=^K
zd@+}<mCuQ&)|>8o{z)h=On%Ye7YTcBFu6GB4c(XZr^<x<OOD?4B>hfvdFuafw<MF3
z{-y?ef*B~f(i21!HJFIv93*jWdSQOdpnDVMG3apC5UOJvB0YP84Ac*xt0<AqlrXxw
zenZ!dQKUI%0I_8ika@kCG-XrN^!(S<Qo+m(bnP;T40oDBwXA$c_sl$M(%h#6o7vPq
zMwb%U?oXr>qsW!26Qn=&EY<Z$Je4krZ*pQE$vqp1XKX3)5Bf-`YlDb0{8#9s|6ff2
zj~@xJtZC5nKS_Wkn+bg230?gdqJHo*Iq_FI5w-u{G-MGG{l-ws{rD51j;<g{#!f=*
z#9B)w`}!M_`^M9CP&1OBX&PCk{zp8H&@YKvx<J>T-N-=qI4XEOp6=N{seUm{y=3LT
zB-hL*iseg)dPh^g_AlnRYS|_$Npc3#eJiaJ*FCE^Tp9diYMD8l-0HLsivn3glz?kL
zJ&WrV$7HJaJTGb%)`I|{eaOK3rfG<8({s>JE{9y7N42cELr(O6L*T~eMEXNhN1Ikn
z_la7%u9cH!nVFcguwGKjjx3?dxLT+(i{28ykb^abtf<&QfY53(@M<8b>VG63hfXA~
zGrN$dw}y~vfhV<4c_m&}S;_#?8Gnebh6VKVEr}-s<C<oCeVS8KUqC0OmaSSr@>v52
z+u2UnAWUl1vg}fFW%)SKflMJLjcBg%WU|7KU_;P9t7ZMO$*p#Msm4>Ao`Z?OM7>}R
z)ogduGe6j!n%(=DNCh%gv*y2`?w!_P@~`Up<L_wI(G}})|HGyusOa=P^(dWjVKeS$
zPTv9KEJyV;_&<9NR#>VZ3;x9YqR8KHza)tUnLn1%FTAdtrkD<)B_u9P<w#iH#Z+8D
z;>DPvA@pWEp2A5VW_&7gzRUqENK^-zxC+4hn9eg{^bn(~h1CFNZhzGLFyj*p_z^7D
zM#ESj^G^;`gP3OX;cGCniN=bf%nlC15N0C_?og&T*0riI<^>IV$CwY}!4}Ru?gQ@Q
z%;eDkoM8UmfC@)29m~NT$(*2GJBrzm0M3)l_lXdmVpOe=i)I$k02sr}+Cc+IEK|gz
z@HDe~H@MF*t4d%ujyXrOw6jb+_0Z>-ReQk}&t%XNHG#>#4D*T1+@pXeG1_Ago@e$`
z|9XMx=nH3(8QnXuq%ggxBf7}^9uCb*jLskCFEjHaklbcg2n_naY-Z~~*uBH3eneyE
zFh3js_g%(*0f=12H3^<RV8W(@JC9LZ1~8xTrhct}dD|692{Ypf43;ul9atVS6L$bm
z!Q7h$mP#h7AKLdR^F9!`8m2=dgwL4eRUmuLEPThI|Epux{R-&|Ci*RsmrP&@?A9{|
zn(s6)*GEJ6ig`I1h}TTtXUM%_^c~>nJLc0f7;I#Ay+lRdGgA{#_K9gmzwc&wI8CFR
z<t;tn;ZAwU2Lbl+f2T{-iS##(17u|hra}(Ys=rRd(jV8qh1owluE70j%W$j*Nxj|J
z&!OJS{0A!7JNO{3ecGdkQT2^%1!MhI)A)3R`Ecg{*p>6zqqgcR?V!m1+!}=3v*VEP
zRu$I9MA$a=C%E_dbM%R77smWvj`rWe=+VckU77FWQLP<JavO9*Zp=4Y=<j5%w86_6
zz|_$M_AvACAyi&74@bbQ56qV-AloXRJ`b91@(p9*`vLi4nhg2MyB|XCuw1qW4RBJ<
zE(R`H?&}O(rrhuft66eKcgpcQ3Ys_m4z0GGr-81QxD5qE+cVId_NEUixMJQaTz4_O
zRd6AcDO(KPBxcD!sN@Z1TC6Bj*E1u1{;vsy&t`#8{~W`By4%8AsAl(t7#`F;Hf%&^
z(lhU0#9Vq&08QQd!64Mk(WjvV{Z8M3Jld&Wn<6;ff1Mv1cYyme_%U!<GW_@=IUK*{
zAoB%Wzx1Y=$>2zuzKr(XjMDFFyy4i?bQ&b)c5MfprEA83=TGNOC|y6(2>E7a@Gex&
zl}Y#m+@8#m*C6p`R<iU`2QgM!dq*;@S&+stU(bZw=a?q%<C!M+6PPCd6Pcz8Br#1j
zIM0yR>Pt*hO)fK3lcr`B-cTQJd7Fc4vmxY53w;<2w(Wfuo_6H^Lwk0<_Zix;heMi<
zq|bPFAp33brwYzn24{v|%!Fik%rba1rg#o~|2CG^NZ(&qfNt8S{}7I$U(h!81}Iy)
zbi;l7o&8~?%jpfc4tUuO#)l8Q0{OT5Xz4j^3cYns%v_pEZ)QGWuv0lRj?QzD^<k15
zK<>-bY=LVBnURapN<mEHI&cItI}x`;cNmllFQS+ho&cU?hSkCDDQ1-jm2*s=Qo!RG
zDIA&!%rCUKPh}>q2jB`b;xshVm`|aoN)F>T1uAzLMK;XlG6NmtW;s*06Nn1NOqHo*
zGBr?r#pGQE{x$QiJq*5Kes+Oyn>?ijG`GvozJ)<od9evXFZq-fNWA4M+(G6ekI07i
zq4Ft5Ko%w+wGw5=<cU837bjo67Aj}u8~=hA=j4ASIA9`8{$+b0(&d5gP<T^5_ydxA
z@<9~vcqmuWZ&oNTA^an`7=y+wmuI|0?uookgXVfA_xlr-aZ+?x39_w<krDvA6g^y_
zxm)oW22qudV(0^K`YQS&psPBnsHK((QOx>IjrTuV@pn2b#VGVkKzdQJZ9MRo6iJx4
zH~qwI_%Q&rkFQ3y!?|v#cgLCQ)c-3R^>Q!rqj`7O8q+=j_v40@;JRd=?Ejv{=6N$v
z|1QoygS5NnJzRTLcEPo8R9jFCaQsEVj6oR~_Ekf+FNJ8>sdBXU$dYg2@ECRlR40gt
zj;ekbwHflCZWhAS;)(Sr{k_FVTvwUuz_9xLJ=7slU5YuaDoK52JB*%JXMKmFRCV32
z;LT8n$x)WAzUK^E57dK25M_B<`{*2(KB9u|{E(3-KdqgR2<=4egI6%;uD>t^x&8Ws
zr~mJPk791sz?*#LC^hUurlL7=h0IzSv`U!0W{^H&zCDPax0Gpr6v=-1ku*4SK>qwV
z2)*T1G(GZ>cRP#Zp#1BP3XB1M^1ZFWc1Zqx1Cju_>LO^4$nQ)?E>NzbxofaIa|~*G
zRNi|xygVb9ok9{PA5V+w+wvk$c#$n1brmLZ<U45fc~|~j4siG6BCXT!%jXP%Fi&pX
z2S@YezVuW+l(+5=p`%c~=q^-?<^B|?Dv^g$n5k6$-7=7t$s;KSST6sk0hOtce;5v7
zmHf-)09MPhOF;8fZbf)sRU;o43~nby-%TjntZ>Og;-dH$TOFz`ipC${{WisCwQy#;
z;x$ddk10|G2*Vu;Kl*{P6$?)zdq**!1I=B<9|bU&tN8smg!dI?zoViL6b%$;$X9sM
z3c5hiKufSfMa^Qsixi(SkUUZ(&qX7YDrSZv_gK-nJ8<QS_;`?2Dz;@KSEZ<@!S;z_
z?FvvoRX7sJe63=xC$i5J<~LBSQ%Dxjyij!R3DtVV_q6<LP}tm&d#%`2kE*><jG>|6
zouYd_aE*%RRNoH@MuO%?#r_qj;b!HZ=TKi~rTTXWw<^D&u<17CEt<x<Do0^EN3}y~
zaQu#1>{NCMhrwOSFuYr;JxaGmu<cd0zXzbZ(smH49?At9V1B>Sp@ZfD<;<^8=B+&3
z8;Or{{S*NFlz&7+#b3FNf^h-LsrTT;VdXtD0D;OO4^bAR)SZD(A<B_^;YFy@a0Y8Y
z)iGrbMG3=|j%`4kP?ik^B0_m~0CG{v&{kkOscc1&k7#A%Pyl0;Cx=0JTDcTk3aT^8
zML7VRQ~E7{Gx5qHy+D?zToeg-lJfhuP`RM2CbyH7cWBLcQ5lB$zUq>)Je6WVsmcRt
zcyUGfH%+b5l`C(8=BhI55>zvk$u{_%sqDuhxvp&e6;y60=V8-KbxXN>7-()QmwLjP
zJIcIlsN^UcZ=r^{O6Ngfxu^6s0`NfD!UIX3GLS;A1<JO?NFFM^w$U80NO}DOs#dJ5
z+zFjhWmYC=%9K`TB<0HPy<n+A>31I{s+4y-Ls+dmavw>J@+a)8sA`qzE72s+m5()G
zsZ&Zc$$P2n&<OAAl`{%Z_DVT!4*;)~dsl<(t#aNdXueZMWP#K1UU_~Q+UtYT6bKzB
z)lamV*sSs^2hc@TJqt8jRKr`rwQZ{6NodRMs*PsY-J#m40?tkKfmRB;R1a8a?pA5$
zz{Flv%>$U&r^=iToQG=KcMy82%FaQ>OO-wr7Q9slAHkllL)D)q*#}jwBf;&j5^2CY
zguW5@!>a5{Xy7BN*8`vuq^hMbL9puNZF+=MsRq~$RXLqRE?ng^7M6~y?$a_eLe(-D
znvtrJ=i%W=)tM8h%PG}X5yDtiQ6;EPt5h^X#;F|T*|2+7wd*15#;ZC|I5$BxlUBw_
zsu#DRb6yp@7Wib<)C0h$sIt8wyr)X=MDD)oX)tp6s<L6g6{z~ZgfoSzzTcs&NVPQ*
z!V=Y!qkunB4X6EqGF5>LZa-F~Q=F(mmE~v)Zz@&y(&4F-x&r%ws?F-fUqR@iUb_rF
zZBb8|0%x|VZ+`*Ac6F!upxL3GkPb_3>UZP8y<4r|pt478=>UW7>Y+50d8m(Gf~5m$
zo&&&3{UxooeAFv*(N4bV)hST%Q*Y%Qpz&85lL5S??mYy#+iGq$RCCn-JVNfSnwt)v
z?x~v%2I9V2wjH@Vbu)@1=d1O-q4`jq-vzls^^76#w^+SHfn16D-ee@D>O=#m%hbNd
zP^EJ9YYL%NsQWHLu1Y;Diq-(t>TN3le5y{H0o5Ay=&P{wTpdUQZ=HHV6lm(zk=Foh
zP>+g+<{S0SCGg^{+EjzG_v-4UsNo0opsxV`q%QV@iWA%VB}_Q8y>Fn*g$;d;TokJ&
z;Yqge1uR6f`cbq85yPf<f$cQAGzJZPhW*ePq-WV}Imn%31Jtmaz^-2lnnd>RmJpt2
zi)b(D0=s!K%2L?$Opsn=i)p%gne9IfDyi(KQxK-HKi-2dot;Sm%4_V5Be0vnE~O4N
zi#1S)$Z?&WL_wFE?2nE34R5h^A<)TY<)e_h!@ALfc$dA}A4x7djHdke**a`$<9+j%
z<M+*H)9T@U0oy(SwJ&7bV7FdX#BQ4f*GgEYF|hlHjd==#kJ+o+kSk|p6qc`I>uv#F
z?O<<GG^>V{eG6$V+rj{R9lM3LDPFLD_eRpd22=Rw6&o-bDsS1r&H%h)Ybf;kfi0%j
z|0A0+5?(lQ-h&|A%$;yU&V_TUgri%yoyXwJHqIpx$#zcP34k5kUpHXLjdMgffpiy_
z@)v-+xs54E_Ht>iP~FGn{R6xQcPkPIPp%{x$pP+XXZYmBrJjRNm$)wU;$7z2j6jmc
z#jb`ho%?Ym%x7?Mb5ZR~F6A;TUFRmh0Ot+v2Q}>7;{KWr;cf1+V+`2ta2seTn8Pje
z0?j?H&K1D>oQ3B8dECAQ5ax43_QHH2=M)HF5$EWN+#}9LbH`F{IdMPcJRhU1oSU=-
z@JjCWFi=-<GpP@J!W}C^U7m6qkHN!Qt~*8eo^dyN(Za2c>;65G7u>os6xMSKp1}PE
z?*3Q^-*8v<P^)v%H0f#N&QO5xJ-6v|uzljz(%RLD=V_kk%<oP|&V_$RkL6bWb87r;
zd}JmPSN`~6RAL8Ty$a6k<OAwpVHZEXjK%x6hyQCI@O$|VKS9-<Puhx{2Y<mAGza(%
zP7r$WF_&Q1hqqC5-Iq_IrH4O%^9<My@$5kekMJ?MPzmH0(CQ|bmph>@NBPBf;C3i~
zZU~wrjQ^cN65;&GQsj>FzMTZTe-Zptnx#eZl7QqS|Nb$2JH;=i_aK%}>5e8n%@@uD
zcN||*f#fVdW(g{j%TJ;{<pE!E6^`cdTP^}#z%PwJ@{oT#6?TjG{YODo%zuq#xT=&d
z><L^M|1uVCm-EGc1LvsV-6w*yitkCoVKra&6{IzMN)PDN@{TCv>i9*g;Kd8R{tEE*
zd<bn-H1JWh%6QEuS0Z`Cj~R=qHS&5g|DLa(4Z9!t2F#UJpZMbx1m7%-+XXUbVb*m}
zZxQmfDBJ1~Cetp#c41L6bX<jP!2r4mxeuVaQ!u}P&Tb)P6IAvHzO=EqPdH1nJ9l9!
zZ6A9I^Tq?WUl>CMy@Yy-LwO7L`~Zj%GNwQnE4-ub>WuK_Dw-=!h@^<gIpN(>co8o+
zoamKF6k5npm?S6=wNPCU3Mm+!EChA~{-Ut|04!Y+R5VXW6~c@FToIf`Kr>yKO(FNI
zf^Q9c$`Cv$)RHMYoQB*D;YAuaZweP^BRE@_Mh5Q){mF~F!eQD2$rYwJdce|sp|usi
z!2{v5pI{<iXs&~5fl&1bIz_^r7RVI~mne+=NbsWNYN@d5F>sHC12mN>7yhe4QYmbs
zt=cLfXbV`L2%k<v_*9T65?U(+(7wqtVe%x9;pq=U*$ZKY4~>fTg7qmZH3*i8NZts+
zu1MYr$$immjlw@qK>A+L7NVU$3J(hb_#|{TLbzFUBtqyc{%wHw2gO2Kp7@D@^duY-
zeU?EbKs<I8&Kwb4zJwQnqE`gW2aC}(#XKs0xryeVp<;JAvSH%C=b#fV8rvdwT<rE8
z*doM#Xz3IwcDxQtC&k4nU^^ui(pok~G*jp_R@_00!ZYID!BB}4OWMHhIkEOM>KiX!
z%fru<D9*o)BuSJGL6|Il-W!@J;>DA+2Xjeu(C)=$@$`NarirUgqG{5_gQR**Y)6k!
zhByeTaaEQ$W)X7N#e84nZi;a<X}KkSz8&VX#h%YVdPg+=0H5xPo%RBrD{gv#vistk
z&B#3vH#7$>U;LKF>jLo#&aYtoCtmIYog%R`2EY<=UOwD^BzBqy?lSQ+U%2*IoNyf~
z72-5{yeh@37T~MJX|&DyL_8IN<b!x76l`0i>_tdCB+EFop{LYtCw$s3-KT>M2PBVT
zBwkWPJ%rv;*<K_*h(TQi!dH4}gh4;487+JLrB`}*aY*u`o-IJ?K#SnR(mZnJh$QO=
zV4%czL@r1=mk3KC(xcY^gi3Z3JPenzX-E9HH0L`Av!w6qpmJThN?Qjvq($@s+?2ki
zUiOyc7}gi*ZK>m1B-zs84M^@tu>{PKcq@{-Qfe%cTxr&NB=@AEsi;M<<jx{jBF%Y>
z+LuY@<47u{L?v9SlE#%GS1rx`7s(STnc}!lrP_2PHB#<sHB8|DHhY_P7TQ%71Jiz5
zE?T%lO(JUFG5!WB(W&i1xZAl$2gpB9rU$0W1vl_@{X~t?&F4IHx?iEiRgYFw+n&l2
z_|<FT7pPtD02%cAd^Z{leaGDeXTO=`ME?=PfEr*M0sVpflTm>$90RLiU{HxWL|?`)
z2HoHwgjH2TPE#Q2s{^!MGW0mTd&8G!;yU6OJ&7Y<21935D~jEZZqpTp#{}a1lWP2j
zp^(qYy@vZGr)bl0ePSB;otc2I;mdC3wH>*GOb;W}4l|Z19Nxd9O!jY(hBMdbH;iJQ
zU;n=du^VgH1HGN>PgCLDE_O!-Oz&pj(tKhM8%KlRUUtoHl<i}`n1NclvqLFT=E16H
zI^xNGL2HEl>{N;q9$-uUfzXRxWQC?T`}PSEAJ*aQ1EYRy3mr)P*`QvK9%dKPEba*V
zl%kG-Y%VoI5IdaK@geNw<p6}Tzy1f;!q~AVP<D*X9gnhbHk|gWj<ZR$m2-j}yAXCG
z*byzj8OiQokVLUc0S$4Ib<kG9DYmuaPe`NLi1$#9VdE*-8q1!N!^CNJACKe=I~V8q
zRB>$8ZvdWU-_a8199u;LR6N^^)(8n~&p+WzB0Kv4+)iRk+~CuBc3Be2F0kpZkR-DO
zaS&c&Bk29Q%x=`f(NuPD2CYA?u>1%})7X&VFp<tmK5*tL`=%CludzP`0GP=>90(Ix
zY$Q#Zud}|F(dswY{apdS$woZ@?iPDh0?Tc7{a~nMvsH8)<}UjmaptmHbHI6z&DoCR
zK0Ev?Xg**&wx#t)9=p07RP)*E6wxVQOO+sf$hLk4^M!0rqA6l`|BEIqW_$I8GbOC1
z4QL**FX^{0W&0I@t&ENN7iEvx9<&8t&TeW0yA|vJ+Rm<IBgk$QyZbCStJ!_DqI<$_
zMcX@6PuZ{mD6C<Z+dxyx9x8(QXKd(xB+pslB1r4lR0`d{VBdZPFJ7`LTIJTW$6SGH
zVEd=Q;48MW8p79X-*!-W$EKAaX=FFixw((*zyr|y#Fo=ex)XQ*351)uw=|SFwsKX;
z;NH%S@Id0q)qFsq8+V(+T06N=I>xk%%Lqi-Zmv6RWbWa9peEVNRo_N#A6JiKj4F5T
zA6Mi&xcxL*dU7L+0pHJ!r6=eB_wG03yg3I&A$&M@a?O`(mja&x9o(3okp^)u_rY#3
z*NLWIN4Xv}^oMZi)E$O$Jw^PYVchDMP&vju(1IqMdq#VU$2m0x$4+qLBH>d67n}^u
zNNz42j*8-3{)Ea&ZkQaxQ{3h-B+;DLBnV@;6=#8q<s8$fNl$Y>E(hruu9lV>aokNh
z>2#J`P7#iC+&vami{};`hNB7GzB*_oa>Homk;JJ70DhkPmu7|+xP750OXh|Kz<df9
z9f{mUZZP#jm$<MpP+#UAZ$ViqSI`;Gq;ZW7TKuJRU5A71D!2GA=v?Dw((%Cz?ilr-
znOx>wyj5A;{T^Vu&guHW;0^8sd3cl4%!BY2ceDm7x4D~RU@4pHL%Yj&xJc@dbGY5#
zfb%XltR0eE?hEQD?s3K}P~YcNr49fea3lXhlE-~Z2mSK7AE$z}fcu`FmWSK`T5A__
zW&gs_BJP0&=8L%;S}2up7CLJ2h)ZY(cq!MNf@@`5@@i;4=3YtAEay7WjHiOTOwqVX
zZfJ98R&kAVK&6_S5ld%Ko^ZElXW%K<g;owV+;BQ>Rm)ZM2mTr7TMPVi?g33l>bUeM
zxb}i;H5<a0+`vn4t)9#K8JZ2;Vd^2A`S^{fp*KJAUuYiW>+4Y^KmJ$RGV|w`K0<Pc
zucvM<fS;zJ^~Ygedl2{|eBuZc2J)%D!o?uI18s{1^GlN8=~4a&E%!qBCG(Ml^1GKH
z3FGBI!~8LRof&N5{B`QykMlp%n|^}t5QwrUekk=2CwbW%ICF|GbwMtgKeqrXG5n<V
zFzblrOQ^d$&EKITplA4%6G0QlccG1=v-~Q0x6ko|C>9ydYpJ71;NMom!$jVTW)4aG
zbDG?o=fA^&Yt;qbNGB7L`JQ(HPvN%@L~@aDq$&R;eqlH?FY~3Nk)-mU65-4h2fvNR
z>NNiTD{!at){#)X%Ez1m@ER{yqe(LOxM(zDCV!rK+bn)I4d2)Ko5!Jfga2AYa+8lu
zg`>Cl7U5vI&HD_(FPY8Hp9$(ay!IcE<?ufy!0ugsDec4N@*W|`-Qyi=XjA7tZ)pY9
z2YgG~4$tE=e*sNCzu;R43;3P;P^X9d9;#>|e~D%uMf~Y2&@ASM(^gFh-`5#FmGQSG
zf$TBAn!1g0enK8pD)`=1-%9>f3|Ol8(X{fe=5tN}_k=&<pk2GCd_p0zHT*xVp;ODR
z?F!&CzL8F{J?F>11EP+9e*txR!I%66;Y+?boe!+%Z_?IQ1D{M2@mGBIBnV&glRg9I
z8@|^-<lgemTD0Li-o*qj8u{V{D0|OO9D*kKz;{Wf`1eO%t_SHSUQb~$C!sB^2saD0
zejs%gN{_)O7hxF|Em$@7^McA&;ji5w-6s4t1vJ}*{z1@m6~c$3xpoMVwB~gaSXwLZ
z6t2(%u}c{E3(9s2qv$~19-%w|fW5+1UwZ%c30-OP&0YAD_V+x5#0gOK6uQPj$4e+%
z2ut3=%fC_PBlMY!oUf1)gXEy_?bmR|PxzBa{e`zUd89fdH0(qYAcWJvcUUk@K;s<|
z_VxfgP+0dHazVn+hhZUDaKfQ}hw7-{LF<SRVHw5mLWRg7up1`KqtnjEgw$`43m0Ub
z@bI|MgQoQ-go)iy?FhlEA99hxG+OgU2^;8?z)9g7I_Y*wFrPv$T3AZQv}1&;QE)U?
z$fa4%X`xL%a%Y6zqmgsO30}j2KP&X$VE&v?N{hdE;qN-Qm>{&HL#>H|(?pOa3HO5`
zJTDwO0pSJVd?GZH1x*#oQiNx;c)KY4_!CGk30-NqcUf3XvEo!=3x%Vv2>JiQP@3>6
z96qHBNw1JxbqEDM@aCEj5r%Arplk*cnS$S6FmXe;N>AWTA)A8nx3IiLJKYxa^loMg
zQC~pwj-a%_QjQQt`yzJ*OB|fZ70hlhcu$~@fUvk;-w411;lxk~^90i!B>BS6dI$>y
z$Jt(>c_^e&?5I#!5e|HjaHbBmC>GW(hE9plY$wVd2@k2FrGk1bYEdS<qkZ4Ug03l+
zBAlcn-xWgVF;J-#q!_4F3B6l_rCOLm5&9>>S2IEOREYf>RjLtEX!p2Q2zD$$_L<O^
zlIOw}9HqeO+@B6sy%0*?0RK|>xf@jLg&y=CH3&x9VSXk2fiHDbuZ0lWIC>*QlJ{=~
zf9itY2~U3npix+O1!eCApI;&TAWWo9i;qGAg*iV78%CqdNgVl>-oMS_Ogg#hES7(Q
z)J0TLr@KYG6pP$eF@wVB+r)n;(7#<AaT_^T@zf;%c8I^P2lp;9eIWq5MYr#f+aoH?
zaMWFlpy`!|xSp1Bo}!JmBD}<3mqNu`45C1Tk9cgpfcMW&d`%x;`HOl#AP$Me>yR7~
zXDon;K=JGCFc>6$`3o8-M0}WmT&Oti8Q8+a#kAdbT--u^$_a7xDF`D(Kbi+diUTR|
z79|=eBzaO)I0Jr46yo4aw0MQ0S~23Dx%i$6@q?p>p?X?u5d@kuqATsP#EB_O!FE<W
z(F@L;6IX=*5ifR&M3NvDq@gTPeDngAlEepecImtr9gExrvEyU7oh-hufJ%yZYy#T%
zqUhs!V^Rx;GwltfiJ!t?E?so#jW)O{#_j?7ns|OJ>|}`16rsx$Z&25nB`&89{JJ>w
z4oGf@_i6riQ(Qpr%`LI_YPfPobf@@jj(B-AlDp!e6`;-)%Xh%gJ+Y`SSniAGX!H1i
znB({r_&jlG9)S7cBs+8p#OJgQdMH|4pi?ON&>m@#Xeff+Vlj>$yb{s13V=uAW7?c7
z6(!mfEfY8P0q(JQ`U`NDi<xxbs6xC!J0F!|dpeg_B@Ur|=4x@a2RNUIkt{uGPsRTJ
zAgvMA@sQSvQ+xn?CWaJ3_*~Sj0HRLpOLP7g;&2)^Uy2Pz7_1k~6!UBl|EB5GD=}vR
z;IBp17L>gaD>}l%x8gT{0`N|JOY@*caSiPZzZZ{spzMRV@Dv@l_$V%Gj)wXq`d<K>
zlax(ysLj%X?m#$8yWXN~tCaH=!fjIRQ<&H;{X##JtK_~MfE|+N0UULcw)Fz{PHFNe
z;C4w9>G0KVse;ztd!$MgRQ5{!TfmupQg1re=Pm`Wk)f;ikfzWy&QqE`3yA&FbUJf#
zK>CUn{9e+lO4#+5TF^F|kK|3COZZBs{sYZH$v|5Vev&~8xWANA0O292m>M`hs-ws1
zu;k_e?~h1(1egz$+Vn>o21%>&v7Rbex=68m$5ClF&2B=ZxDSwqO6_Qt5hf+lrqD6z
z-clstQuFU&>A3X%BWiy_8u9>u2#L*x!APn3YS2VUUxq^Eq_plE2v12<C9p(G;s1g&
zM%qRFcdRs?BKfB!KZ>fJmFBfV?wms!(*V+V=}jF-6QrCZB#F{sib^F(32Q)eUUH%B
z$O}>pg3GF8X;u-~Qlv9<g!ZDeApr18(hAytxhzQ(ze<(*_koEkQqEBT(xmV{NYbUB
zx&v@k+I$XW*QA{^jmnT5dpp7JOv(K^XtJcP#C=^Vo(9z$(h}MNzbTEO-QQc1>n?b4
zTiQp>oh|+G3z9oht~>nAkxbM_-<8zwp_wa<K990{l9C3x`_j%YVeo;}dJR<aq>wal
z=1XVBAt{vfjv)A5B)utuYOyqIK9W-D<1a8@Cf%Ub$zv&qy0A*=%y9^-q|zV&tEEXa
ziq%N^)i78qy^06!nWUkOu@};|i7@z5y3({sD6OT=ph4P3-P0@SqY=5+()DBT@SXJh
z1sykTl#c%hn)lM5bXewtq-S91qZCQU?>|XXl<>ky^Kk;WH*4a~Bj>E~pm*CvlMoKO
zTQs9u0lrmZaROkQ<}u9@wreJT0Ww$3u)Aor9hwO>;B?buy+PSdO%R<b+ohSDL7}GI
znk0%;@6jy&4EVj8xs$=RPctY8p1Nx$-h&Ab%>@c4cxvK%L1n*2ONUMlXx`J(%u93V
z50H9mW``o@qY>$I3}4ONCupaGnwzeG`)M-6q2jN3Oe?KJn%74m4A8Xf(zMjk_|p(`
zM6-_;sDYXp8vzW`cu){LSmR5f@uQk=X!j{Z^G^?OhiVQ`U_MM!Ku6?`X`CLx(QwVD
z#eg5zJUxo~p3sP2K_x;nnSP2$O;BHyMQNPhK=Y)=`93&fG^Ny`I$||u>U2+QLcfE-
zvzncCsOUM(c=9P;bDMh21WiwT7^6zmM4p3Yk|z2xxX)__wno_njX!M`Bx~*%flJY>
zSPRmNn(sdVa7lBh6D(cUoTl(rswR#MUeUPiLS51{qfY>r?$DI>LwZ#c9FF9gW+Uxk
zXK4D-fu&4M%6kB_G;^B6(shkLjgU7qn8V_&&<vOkwp$vP2(aDO%<KT4vNgB*0e44p
zl0r#2n)WzYuez(bxe1!Nnjy~k(e7zR90kjL%?xVFe2v3z8Mq5HALzMys2M<8X@#09
z1%ySKeY2rjthsX$NvWnEbp~ac8%-fwO=>FGYBdMeqMe>;TuAs_(~pL+I!$W|eZA1M
zO9AIg&AMU8)oV(hL8U=+umWxPO4F$$D)CzL$gv7;ywPMC0eq`@Nb#0;n*Dzv*Qm*&
z)zo{<f|W=<X#D9LiH{m%0m?pUTwlSwlQuO3fX&+PoM6dWI~#lFDi`gw$uO}+TTZ|0
zRxLw8lx^DklaOrJF5QWmxoStr0pFob&Zn(TH|>9`A>F05w*k#=?WsN>-J?yoi`Lt#
z&Hn`|`?P=33-7LN7>+Uz?c9~9lc#n%og~|@T|Eh|9nhxG(F!l^3tFFgYrXryppQ12
zwyS)#fxkg`P@6~I`)OM=2aCV<r%MXFe}}Z^>6l7@Hc1WA!`l6G;r9{ky3J_rK<zjM
zazWbR^ri=EKW_&7QSDWl#)W80z5^gs+i@h^4%ZH*gPg~;XAU8ELaQr;PZ8QREua#q
zEjI%YrIk_ldQxlhMedY#3uZYERkZf;IaDo1E46_avD&HMB6nIFD}&!>v^Oi^MVxlk
zTO?<-lX?JuPW!e!a`D>3^WjW__9BG}61C9^*iF(_9|QcnwhxV|7qnX_=9R4dxE*9E
z+8Gp^xTt+a;rL71D-|enT-Mf{M>bWvFbGav(f*1r?Nw>oHMCw#*FMcdvt89rm!a&M
zRztsbhIV>y05Y|H^dM(xZ_(IzUE70>Y~IjL*bma1+Jh!IdP_Tmg-^G&|3yGETbsWY
zj^5E;qUOrcdTxjCu0#7Xon6V*E}$*xd)i)Cz;<6dpJwZM+OO!l-F)pWI$2eqeLV(V
zJk%EW16Zi-xF4ED+RwW~Sgh5gLbF8M?K@Qak+xMgI8&+}LI%sUonImMSX)nv-U@B^
zrd<*3Av=UsT1T%@KvZkP8bI?z>rLbKQ*AZHA!@V<6sfG$o~KiF&$P4XL)qurX6=!y
z)Aq@S+b^`gegv*T+h-{>UunD281-6vky`DI_O=V$eyiP0rwZO_XVdAnM(w<B;P!iM
z<sjfbXzh;OApNL)I}f%0r2Xd@5+~hjHH0p@we(@w7TsW)KyKB&&4k@;I{!}qZr7c3
z1&yn&zYlUdbQAJ`bJM;033b}38zez<m#)<lu<X`#JOPzGx=A!)b=P&H#iNJr{As{F
zbs?+h{oAi=^AIKu=pNWnZ7<#Wn-F^IcHV-Hk8b2Nc;TxnKZ@j_t`&8xe!6lBfB5TK
z`or!aUF0Sh4A3Q3!Qf%tXLKOth;9!ZunpAxLTwSGtEUB5u<oHd3?0>dO%F?mZpSkU
zHH7M7IzlH*cgG*VV>*v*U<=nR8v@nix>!0ScS2{F4@(ic8>3-2QrE{1Dp9&=^mv`r
zrM-rwQ@V+JU?N&)r*%_|&W$!rVs+m13F~QHpGpYN=n7~a7^ge#4!~L6R6HII)j3_d
zC(Os|p3DSkg3j_Sd`tYFPZx9xS(GK~_Pzsmimnx{crNOeEJW^-ZUn6iFYCOz!NXMD
z+pXZfqH8rAmeO<stT1s^=ZX&*RM&J_pTmm`-7DJ0%+!sigUeaEWnsWMuIs)W2i2Rp
zK6IM)mX4zz_O`BX2LQ8mo9Ua#JGw%Od*tXA(+hA<7ke6Z@9PSC!;1$xug@XO)A_Xo
zAYXTS8Z--Z=SQHq9_n^?0K8E5WgjF(x)|CGE7pDd367TN5^2xukwbSp0f<uFtunBc
z=^j;r`?0P+9WyD{xzTt~p}Vyk+?Be%v~^geTbqxvYTX|C4WHmCL!F-L+R&p@qwBa2
z!djgh_7hdlbk8aPc&^K$XnLJ4;yHYJrMu0*nb*2MDM<E4=Xg>L>08}AYN2<!tk1yK
zsPm?{@_St=9isZ6n@Mq=kGe$KX8EMcA%K(qC7o#Ate;Lh8_xRlODJ>EuP*>@i$0oW
zB-`~PXwmAbA9Wsp9r{DRAaT>rp-JgZ{o=RqaF;&cK~sv|`XyD6?$Nu?M6y@k>jGNH
zL!bH$obl98o(tiA{oOmL%mMvq+6ME|zo%+@>kVB%>Z8x-02N<-ryVeOP@gdcoPPQu
zvg@z^REgw}ek4WukLZ0FumtLpSO|mko5SdHi(tKpy5ggH+ZiMwdM_P*gHU~U3Mz)_
zf1Ly1F}=%S7!231q$WMCFKU4BguZJ7Y7wPha}Sy)_0jl~C#qBW>EA#lT7T>}0Alnn
zK8I$kKI<b4oz~By{gpHNUEjmsIQ^DG_}oo(RxhVn%Q^j@vG6-yf65t!3HlQ}l0<!U
z3AmH=XTO0@$@(j_VV9zxeE|)8Q6KOhNH6IJ&`!=}y+#T1srrvAVfTuD+z@z?rmv1f
zS-QSGPL-=N^hasaGgE(-_I$GRhrXfl@4Ei|BS>%Pdmo4NroQ$f5V!PwrlKuw>owoQ
zZni#)R^)f|uW7S2N8juvgm?AR17YI6e(f9p9_S}#LnTkYlr}c=_37OKFVKIYHhiex
zL%VQ=`rniQ6zS)SsAsYMJ*{jVCHiFAI(noZp+vS+U-}1V%Ju#h2rKmOE(2JpuSo%-
zO7GhiW!3ttC&B$hZ&RR7PxU7bz+jEOjJk$eeNY=T$us@1MhKtl5B&trI{h^XEHCs6
z3gGrj{olWWx?W#Rv#Zw*{XhgfRd4kDX&v`ge~C`+ywfi^1-3@LhXTU)`e&Dr`=HOH
z!Th6sBTa!m={p`r&e`w>O&nbe9q1gu7Q>y^DBEh-Pb2g;LykLy+YM`J4d7}BevGmm
zhWR~_xEYi*li6u-cv6IPmto#@NOv33<;d+be56RFyP-M#cpir7G!gSO+@r$<`weYq
zA#}iyF%<wW!*8_P?rk_64HX|l!Ue#64JE5#{-9wq&4m0619PAfU}%Yt+f;`Qrh4Fx
z7|JOA5@?V)icuJ3_?#YrV8cJO8FAF`RXZdhh9Br92{rViQwU*(3fhu5W*GYv%@uB#
z8Ulk6h9BY}j5Hi6fH2B1h{lSOhK9Z1K4qAY1(j$+0PUs681~RPwpc^RCiryP(EkW(
zcGmD}y90&i438+N6L0u$3TP4xiyi`>XwXtvEy?g%Hge|;S#+%Qg29<)oXLhQbbu$t
zkh%!TMMHN5R4y6xO{;DLgWV5RnxSO|l5~SJE$XfsmiK_cYlh<+kz^R$x1%i6uxS7t
z^~o|^Yzg148$Qye+zrFOEm5bNhOGl3yk*!+2U_kJen~+t#}G_A`*#hUD$yjlhNw2k
z-7|cJBXg?zhFE%#9vE^dI-O@Qxq&R-;6=wB3k=B<0C;E^vkNSRhRqgOC^01KWO)A`
z8LEE;zSNL!gS5=B(H+3Y2Ie}Fa)VqCM1|qyKj5x3MA8sjW!Ufz!l#DR@o177L&sv6
zs5L~;B<-2u&F4^gZt!$MuFi0BELdI`l0~%IOM}-=0O}33ApkTO+S*a(cxA|@GkUKL
zF;v5MhFl7nHyYd*p-JBx<~jrT!LV^X%03!gz6JLu!`LU_b}~lNNwUqx(G=QrHg2XL
z*2Oq&DjIl;(SfgwRa=c0r$TdwvGpv#-HfeSnBQrfLF@Bf#=5&OyW3%Wwi5U~#uGZ|
zxEnuEB*4SS({#nt_(NCd>^F|Dg%<~mH>qdyGWvu;=xwa&2R0w$z{Sw?H7@T4_(7vE
z19tt4u{Y47{>B0H;v6z|q8+aQW7oNG?XYpa8*)dCog=^!Xmk`j1Zj|QHBDTDjm>G{
zchorVCUPOhy)>SL8tZ5U6lR=w9*ASc`}B=vxN&hBaL0{zGf{TJ=uKhx2;*xlgptNQ
zv?CH_ET=W}N#mAj$el9w90S*)jV=^ak1;N!0W;Rv!9lx#r;S%dczVXTL;^m}cxV_9
zXN}$Q`JU>Wao*=Bi#M*`55E(P`<zhiL}LjZ+)FZcrzO*Q<62s4T`&fB0a>y!lOmQW
zM$>ELE*cwW!qO$<-C<C<Y@9_~YpKQ=0jR_kW2r<@hBV`_N#IU5j_ZruRb!`>;J#+m
zv;jWDn7RgtOrzTslw}#;-hqeLjYE&1zBi1Wz5~roV<ts$ZW&k5Zpm%q{H6ev(TNsG
zcZ~C=qAbVwhSmUgjY$t+DA)L(FL3vaS1feY^}dlm1mFW>{u$`x8J|-ply96vo8kq=
zCG^Jy9vW}ZxLs(x_!=rj#-4u26&tlT;Y^9~+SgEdWSpD_T&c0|Sg4d4|EmS(W8*Fw
ze#?y?4gyeN^c#X)wb6M7G@lrs_oVpCQ{#bBI8|c|UW%mFXrT_{nUSY6%+HODXHo4s
z<1q?Cy)cgJjyk<Gnhjv9H(n&S8;na5Vepl4F*WyVW932k^u~BQ1i81yQ#5&aXI#4v
zWR1oJG>E@9Mh8OWgE4v?s2v}TLq7rk$#}O4^>s3ZOZf3No02G8=4_G;2hhcImPOeX
z)7nh{ZZ*B9>EJfg02#`*n;42Nx|(_v!22Dh!U~YOncn3AzSFd66uj7FVyREqZCXQz
zEcTcJ{{Vcish*BZ>~omvsny+0@`3Qw!!(5cFovgTXfFu&o8oDna==tcUm|#!?h~oE
zsUuBFeN10aw9VIafL3(}P2bWPb3fA&4j%fOvZ#kSWa>m)KLMuq?ZI-`RQMXn5!1ia
z&jgxs=*&=%$uZs?*<jNOs_#+LHJW9Gm}dTtb`CWS3qUT+WTwwZj+sui0zTZdX$X?z
zCXv3OJ7H4Mn;K!7a|XFc)2+U6Ez0ziHl9zKqUdv*QznVpH`=sf8XS!=scC~S))coI
zZE@OE?RXCEGp2`aki?mO$^!nZY0yEKIA_}447qsISo(G$!PKe-_(W4A9rjEz?H56F
z-sDV&VlSAwHX=zj716=U6jRtG04|&EKLQ}tw1W=lT``@b8GV|`omPtJrgbCW+Er89
zcn7lAOwn{iCBu}+gFDmIn*JhAmg&u(NUoa(ZUFZU(;3=}ziC=~5xHBY4flY*ZQ6Ga
z+}S2$Gt}^oDJBx|9MfKUyzZLLQ?Hk6`q&D&d#0I_p>p4}tPfNkn8wotA<s1SJ#BU6
zo37ADVFjjtY2bWl+C}4Tq3MgKaJa}+IUc!UQ{WmHEHO=)gxn+3UOBi+O}ngMD>Kcc
z7|CPPv{|rJZkkM8aE0l&4&babRnca6m1!9rVXihsjRWq9sfJFUJvH?mLq}a}Oy77T
zTWc~shw3v^brigKZhA(W({&~%9U9?<$)_t!yfk&W3YvP;JlgkeFf9y5^2+2A1L12^
zFr7JiV_HB5b>Esg)42Q2^rQn+8cl;}M*rS)Ed<_wFg>Dui;t$K^mI8sndUVj>ty!1
z2@{*me<|UGv-vYRh~Z+sK?lCJnD@m2xYfL6IaIcpZ|;Q3cJm5axVf5#M#20J^WffK
zaWlKnX^@@f;JYxt%k0}7EW6F!D1yGne3m-hz2?|)NcNeB&^*xHVSaK3Y#!#~@zC)!
zx1l3#`^`OQyXSzp;#VYIW(9o*?`@8xPS?krx*VFm=D6)>OMml9>H`m%V_Kptz&t=e
z*<te{IwE<*T-64@L7;i;F$jaq_n(70*t~x|JUnVnTn{fo%#Lav+@a>Q@$e$de3q7x
z$IP2sz;3v?g0>8foBPuQ;e@%04*Euz*V~{HY5tc2O;P6fMC4AIt));oWj@#+D$(Z6
zRP7jZm!&WfYaZPn9-cN&p^5Gpv-2qc;>;=3YG=)<4r-cn=2xyr;>|)gs3w?`X_Fw)
z+&Tj_Ofqj|k(@VwCn33DUYCy~+1xV*nknX26rsInj`;vfm&}q4CN7&-xqvLyJgotm
zSIo<(gGw_idc(DJ^BWrgSIuch@cUdd?`oj=XNGwl1tc=f<NZ*lEOY<CFn`@Vi1uY~
zm@h8?%}w*9<)FD`eiDJ?w)roLv1FTj(?-}Gvy=_Z9P>C@p4>H8Q_qxZj=74md*(eQ
z$lW(%mj^GNc^oZU^UVLwfiwALdp-U(qpHAcp~cQa^Ba1~3e8*n;aic}gJ$-{=2d!_
zFEPu@QTE8ZClyJlxqB!aEi<2{Skz;4j~}2}ZZ6aTS7DAh57#QqA8(?p%6x$~(W}k>
z(fs6zx#|TppPHM!f%zJ<x;w4^YR%1`K=qk<<S)>9ZVr6{?mF`g5i~E%7wD0HWfo}r
z^0hf<DDZF0ojs6yYrYnTvUlbkv_;rxHhIGQdvo>>82n(a?~L3>^L;w9{mFc!7k&{Z
z%fVdKWwWKl@5nh@2Gb<m;bMu}i|iK5U-XxCwp!E_oY`g>NXJ#TTSh#CGp-iXL{xi+
z<**rvo8?d%{M~6$r=e_@WfPsC*lpP`9M0^qJjzFIuVn_EmDp#gBxl?$m9%T)VKLGM
zji<$rB5C_AdwfuKz+uVGhIucGH@zg@mX5To?PDpJ0ZYD?YKpxbwERLrLO+X=o^F53
zSIxk7$l^yahX70MX{a2wth|qk9<kKBqAbvo83eK*%Tszsf-RFN=6=+|Qr8_~iJ-GE
zp%%X^XoguFdqW{TW;sg7$HFbmn#0m@OEe8RCoCIjmn_24Y6fT`Eh<`fMp<^0AvtOJ
z>?I7IvfQONCff33E1Ze3>{h~VtcCd=!qb*tWY9cg37`;7oaJYl(44g#y$rH*mUTU$
z5^wq0K?fKUEZ2U7Q;C)}8=#Y9IWY)`^OpTffxlqMrU-Ac<y8U@DVE<qhiextTmC@V
zCCiNn04`ew(ea{G%Od&);EKhU!s}_4U#Sh#E$%a+a@8^<9GurI(ZTo)GA!k^*Oh5`
z(23$NS(fh)0dd`uPu~^Yusot=)lJJ!Q(^Fy<@jNc-nPV#fH2!KkK#plER9Pb%&~lb
z0*!aq;>n=wzNNDVEIqJnqfm67<)i?3zNMUEGX<6qSD1fjVdp?tXi?L;qR7%^A{{j@
zww$9STZv^VO&cCrT>genrIzIs6DqUB(lM;ZmeYM<soYXO6u=70X!=_}m6pi+;I6W4
z8HBQGi%8G<6H9M5s64d<oCdDOqL~h|TFZ@V@b{VJFZvr<&n<Bw0MuFZXatAqh2<Kp
ztY2EJGO*QKcG2Oi2Fr_Pz`wF&MFaoZGU*6Bd}G-{`v7k(e$&DB&eD&@p+<{=g0b%{
zH)*H;gC&<9>yMVYwZMI{<QBtGC#$Coxy{z9;rK<It%v@CJs0bDX4rFVvHnP*fUVZH
z7hrdrH9!qZ+pVQL!0l??S`O|V)>U+r&doZN_IY+%clg5nT~<$8b?>%5`V*RatkHR}
zyVv^9e^A+H?N7%~+^sV%gUrKvn8p!L>)-33vfrwrK*RxS2QLV{9M)?^;P$poiide0
zYZ~=zzScxq?;f<e7D30)>Ouhpf9u2Euyn|JqYX#{tRCB8;;?l=J#t5^ElvX-Xx&Mt
zii50u!T<=i#xz3ZsPzoJR3X-wmq<dbH+sNAn6=Lbs2sC8>_KoU+<M?QSUPS^qBZde
z>;5swMOd%V7uJ#1ZnQfVW&P|u*iKsQ3jsJ~9ZT!`XscHuRAQ`~egJ8#^;|fFr>%=y
zL-UL^>pxU9&N}raRL)vsDHNSxoke>DiPm&l;3ir3IPRhFyj2|n)eF{tG)R)I=jc~U
zu@=${{i0QU3CShvmgex{vX%J`Nvf5z!;33c*FJ!!S(QyuKI`Tj;I3N5DtLd*YHN*L
zhPBcOEt6@@prBipwcB*$u3OvC*|{6m-{T!ny=j#nLSx*r%72G%x2;3|Mq#$qg%0`N
zv1ZWM89CNTYf*OBnn0`AT<f-5z}>UnEd|?s>#!l<eqbHt4M3iC8Lh+etu;GPR$#rG
z2uB}Uvpis-(0aHHa7ETG*T7P2?J<wuzY^;wI&J>QI(-4`mRdCe5M|a+p-3KEH*G|d
zmRr};qQAmAj#iVE)&sKvsImquN3PoX3#}%fSjW;4$*0yZ9!ZV$Jr4M)YOQlAYW&RV
zM29t=TZg`Y7j@Q|6#%@jUbWNv_tN_KAav@jpJ#)#!8(+>k5|_DoluL{*3LALys`dH
z2fW`}8_4f>)<QbJ)oATU2T<Ny15M!mU|sqUEFZ1c_Cw{9wSj`EPPTokQMTE3n^rK+
zHd!sqyVwd$$ZfG@Yf$FcYOA0L#x~pZ=|F6^jX4iXuC|gKnBQTWO&^W8+15tG;hnaH
zbRc7wEsr{}-L`4JBiUo~ruEQXTgy8D?6Z01f!p0?rTrlf+mjTOdD^bhnsmP{jt1%j
zw!tM3dfDESGu{r{Z{1+R$99kodivVtQ258+HZ}mYIAm)yAQxbpN9WBB+ipFDqepE2
z(VH4*%cMv`knJ3u3JbQCFM!>nHlJf43$dN<iX_yQ8w8dx+ZQU}j@cGD;du<V`O}Kv
zxUG!_@Dn!2H@PqoVM}7sdXctsE0ILmdei>!Nn6Qv(44YqOrVLj)h&XF7+YKFW@BwO
zPxyP<HhnviGq&0E!B?DZW-j1oZ9VbVtyJf1(pr?o+nQ0-D#2DjOYub80NTSzvh~^r
zmGd?i2W{J2uvr;olWj-dLnp-+NfXzLwhohE>5^^g33zeY_UIn~Q*Aox(yrK6Q(QdF
z_VG*DO}CAVM%h){@;%61vyG$>c80Ah1?e+wi_+kBmThqugx75~hv4B2Th}e1zG<5=
zi`IX)Y#v|0i`%xP^v5-_Z369E-m#^&hKU@TlQ+ul+B#ncBG-19darx7bWf<<x9v-S
z!3Q=M`cyH`cH$Yl$hU>eg^2>&l5_wb+TPMB+d|vMV3;qm9T<sRvF&qO^_JK+R?(kZ
zdt?hsf~8VhA376SX7i<P>#^;-ELbYH{r)qO3R?&Ip10E0i<Svhw%rm;RNMO30{6r=
zJ_4jqZ9Qq(TVqS>2}`v$-%yl2v)Npbdv5#U5!#~8=9&S`7q(4bz~7g)08H#1s(Rbe
zMl^SWts8Bizq0LPVB)ncWF%aCW9u~ocHi38V0S?E&UU*mOf=e-aPaA)ZSZ{LKG|I8
z5T29$N=um7Y(EwQxU;=Ioq}_*Cx3*&Ep{B>zz}EuM9;-GdpK<zY`3#3AauCey=j|i
zhrKsVDctOru0dy~{p52P+-1)w2KR3Jw^pd^v0tXh)L#3#FJWSz{fh-qaksan(-t1~
zpN62mp7z5uBiV0X>Wka~yBRB7m6u(?!V7P^ehv)!*u!b^;A?++7r28Cd-qnTwx2zM
zx><jFG!N24_9b+hEx_(>huy>WR}Z0j#GXF}z(D)o>7WU+537QuVEeD$uyoY^Vg-^A
zd&f>t3AHah3V4`(Ru3e{?7iryS-5?<5rE_N`c?4hgnbG1S`l`~BYHU_?We9GiL$q+
ziTX+VH~~JLvcFpg)oA;MKLL!fucZ^IvGzC4Xs6TmuY1FbGxl?vQ5I)6QzvxR-j2q&
zbM~5bAd9!J{Q!7^J!}+miS`dZNRsSN$(i$ZSs4Hq>|Z-*DUoc?rkG)hea!$Q7wy5v
zVd;`xeFH9DwjcZrCQ|KbH0{1(f9r-CrrB4Vg!y#)L)s*}YJc1nEZ6MuxiFt$_uUO)
zrhQ}yEM?ix90A#N`%S9v4f`gVNZquLrm)^E`?q^rAbZ<>R)xZB`;vEPuRHe4zfqWD
zALJSJPZ!7j{m{s_2h(>|1@_s&P<&_)oC<rz_Ppb;P-1V{5e`1G_o0*IrS^qyfG)EK
z6#@6yJ}@5*T5can9aDupat{EN_P#ViR@o;rFjs9qT8P{e`|O4A^QnCrg~My?JLz0s
ztv$riANXf>MG?54+rOR#ojUuk^kL=;d%!}FzO?tD_(i>a{RK2kgZ(Eu!12nyfxh{8
zZTB+3nKyQPxcC3z=(^*wuD*YoHms~n%V+Psm!_GT4a>@=vodX1zs$^*mgU2qvWKE<
zP-G~AASfVP5ReTr1lfWhvILR!d!O%L=XLKr=Y7t-&*yW;Ip=;JyhY2E6ia-xJasYJ
zrk1}$r{(G88NMJh%RSwpaCZ4z5Lo7x!})@Dim~7T%}=(BJaWR?F%HmoH|!Y?D3{uS
z@%c0a9T{D;LOL;;OVKrF1~&kvxiBVvK$|OL%mbZqW9&)*i#wx(_J7A17w8=0!T3i3
zO`eSJe+Q-)<LWce;LWJ`6U2wnO|P^s!xBO9Q9s53`p}<0qlmIm0vOwOpcKfMc?U4Z
z8Kd0*J;7*X0WFB};qNf*B;%KMfSzL1ZHC@p#$*40C4>=5$DvS0aWb&O80RR!AI|80
zh*AW@Za>;086yXvK8mri0~(?kKUnB0;AzGtnzPR^oM|j#7#8yQpJjYWGg2&L?E#QD
z#&6_Dk7w-J56%R}XWs++9OIw2LC!M<C@m_H5wR84Utr{)g^DD`Yr9dI%wRtR=0!&Q
zH?TK_VRsB;n96Xw1<Xr~9c2)=rZM){p)sAouR!rKqp=l@R~S=yAQ_CZK~!ck2IzZ`
zS&XuDfL>*k+=ZrWMn5Gc<T0*NpfR7(K(4a_#`O=uQpgA>0n0VUB2O4o#8^yAV=?0~
zdZn*3+{sf}!nj=w&QdF5oij`<V`O$>EN?J^Df(E>7`_FG3Wk+JR+S7lx++%1$fDq9
zHDjg}dTSWHi$H1_9ppf$W7s>u!g@xM6IgCC@^XOPz*x5la*d3PJ}7Krl-`CwGsDge
z_TFNwpsApRVHMMErIj&5=dat0jx?~gF}}J0w01`CcJ#i3Vfqx6os2t_64%8Ly^XGQ
zGsfpo>S4^KK*b%#>5o8q85TVR`WPcMF#9g!F^akNGp=`n3^2AW1-ZxAoeP#hMj<6}
z-)H1o$qzWhNT!<t!wl!`&@{qGe*j}f8BgB;=on+yBrJTu*h@K<<BVrlqHTileks&H
zWW<yBBx8XR3Li02L%})4;0w^hX~tC*Ix)le#)Q%=BX%(q&M{8V_TGkBMt4PQnWz4w
z{B%1e?>h{)J+osAhy$~lR&PgU`UVgu=8AquI5XSSQ18MVyaV%Hnd$U(dpG8{lnLR^
zlwJnQG3Hx)(B{EhMgCz=<`(+Yj2CkgtqR`E-(Q8HK1{#WDETt`z5<IMbJaii9P>hd
z<~m9<3SjP{5M3a13GL{QGsToua)S8+o#2C*FFpZHCz<K1Ab5&7Zy!p*%-`P!31RNq
ziONvsF&Ty=j5&|e$HJN7O=yc?cDll*Xl6If$ETSL+QOe<J_tuChB@F*SCP&#hbaml
z%XDJEwm4=6?E&JMsTt@~0<(b$o6a#$(i421>F<G3B6HKfV7b8Dyd9<`F(vs>n9Tf?
z486$ArZ7tivy~Q=RHmW}D3_QW-=i{(xmONj(wWt_KrS<TD9mEL!u;nZ&@!0iUjrtS
z`3l8ZvY4;F1i`CJmv=z2nPxF8%wc|Y6GM{A{3#P1&0{{j3j+B}^E65Y%vb3^UC2D=
z3eIaxXYv3PF#|S3MKM#GhthRsL=d1$n2+XQOewSXZ-A9qnPEE68_dA#=wUhY%@{~j
zFuzv<yOP;PAHk|(77U@Snpr`MSq*dNGN`C!4p1<mj(M40!+K_QHRNtG6|^QcFn#|Q
zaAU3{Z*LRxg;gNU%pf`?++v=%3DUxBr7dYI)A|mDu5L5u{4la@%n*t~v@;v&vQ-DO
zioS%>i6;=Giy3tsn!1^BpFnR9^QkV7JIoe}3HCA%hC{rM$)FsoyUb8Z*6n8=ptWXz
z34M6+m=1Jk9%MF90`PsNy%D7$=95<H#W3^YKQL;9*+hrIQRX`@18t1?BR%pDn1<(|
zcbxf|A3!IVCn@IpkU8-IN|Vf|+yV25`JFq=o?<qWS7Dm@y8~Eem@^deon`K~f%-XS
zxE+WMD}%<@mbEDh`s`ShDKzKXv-WI<QBJHm@>Dvr+$PcJ!kY7hge%KTxesovzyAW7
zJIhMGm1C^pHIVaQ#Za8mlcgMofEUY^#@U;d^$hIwVO^v1qAyF>g*HFdEA-y`vwjYQ
z*#WEv3g`=D&0kFW^W!WRdS*|sGMpeE#44Z{_aw_+1!GRJGCqXDV3zR^SVCAO=^&x3
z4<ex=jAcrKKsc*t4Fn=s-%Uawl4aQefhZP}JUh{>Pbfj>G%J|qursW3nmuAz3d(6Y
z%i?02ZCx14@{EEtajXrWf+wE!G%f83tiipo`yA^D8ujz6CQ9&0WW9tF^}-9Ree`Xc
zB-Wu{pdy)-lMix{^(H+tDXarM;7nzG=meBYtnbMina1j(RWzNoW(8O-vtFc!^a|_0
zE^t~iSfQiPl*u|firOsJH*G+>%5tE2J)0FqA(b4KauTIn)?)e;ULI>PO?UY$8w$!5
zu*7trE@Yja1@<-8P1-CKv7~!}Qp}p96tU|p!RuftVd*Ggx|B6X5r#6Bl-AT6R#qlm
zv?ym?W<jum#c+kfO4gTjK&@hxZ3Is>%R*~h4XcjQzH3=6^pT7@Rtk-CJ!=^~b2nML
zSEH?gwTYqujjSO$P&cuT(E+BJ)geLY7AtKOidtBw<mhfIYmP3z-ey@DbP{M|EiFf}
zowaTjq=WS(y(FEiKi>pe7i%7kOgAg20D`@&n$J<$$2xBVa+j5MAC>(q3GEsNSZq2$
z++)2&7e)tJ3s~sOeOBlKune&-e}>^6X2tG7X@u2z4g#aB9oA~_jImrlhlvkZFH^3^
zIIEd1;Z3kM(8KnS^#^^cev);TLe-C0hsi@T#oA5btZCMJ*g`FwVZBCs|5=uWoK|zJ
zdV7G`u;Y6`Y}qf@!6rNQK|6HGo_%^fOmkotKLKb*cG?W($2zg+Ekvy|`_eY>xUj!3
z1aW15{|*$ou~TRvac8^P!|r43)f<53!EUUAfG2y>jFK1odz!Vp*=&lT_^=aOVVW;{
ziag1F?8B7+^JfpSU`znJ!XIsc?0Om6j<c6E(fzCw?DjXo6U2V(3P4Y?H<K&t6g$cZ
zrUkR>$V(l<UjG%aL)qeF^gfJz^i7x+&h~j4ED>xqMW-U!{syRsV*g69-e~sQ63Crq
zm(WXfhW*hqfR16m>J9a0+22!ANG$vNTsj}evF*#CKAs&-%V+}okR7nkv7PA*e4gD_
ziBcl__6pc^fqjJ{bxG{ePH-l(56y?(i|mnckQDafa)73?-2$QM5_|FmXi8)MR|3v-
z_EQw+zszP<0Oblh@mC0Bu#q=__b-#Zn4)o6>>LWnUS&%^gG4raWE~oF*c)h`%VjSl
zS5_W7M2ca{XaDg9Dht>mE=((AzebD1HFg4R6^q#YEvPJEyEUV-lzriMV3x5bX^pwT
z{+$c;<!rev#4FfWuA@}>9XpmXU8>lPv_Yw6kNZKehW#^TB-FCKx?x2f`(t{4>)8oD
zP;rxekY4Hr_R3cDsgd1IyUHduHxq5m?03Q-aEpDO&af@)@fN6PW#97)cUfwk&q5zM
z*ndtzx|40BRJ1O(J#F^8*@+v_*2Au&7~mcDf7H!hwg)8(^s%3K8>ZZ4|3#UK{p_H{
z5Ex)9DM)&ceULn<gY5U$pzS_;3C)K??35g!472ke0~uj&4+F|5JKM^KiZS+*7oq+E
z`?sH=Vw}D6Sx8K<8z_kIkX`aL&?eb6?O=Jt{)u+fQ*6T{z)Z6xMs#zAeRe(c&axxO
z892u_n^9@Qkvl@bmh)jG1nfA=9>PL<jvYn895`QkK&>O^j{;igoH#E2kZ|T4p%|45
zCyM-8uAI1!K-@T|Q&8#7nSBD-$2bi~QS#s{przcC^ZoOv^x~9U1@Yz_qY#J>r<Hz4
zU(WkSLHsyhkl);&qZi}n4B#Y(Kz$%5EfeC$IeVMvBGw7cx^7q##94k9<8_krEA3KF
zaR%Km2*I4^r%(#vq)=K=C}+9=FkzfSAA^K*);@$l1n2E}&=kq3j)nRt&iFZ47|q%E
z6b9%tM;wK=GaT>jXp7;j=7XH&d__CySWZ5R7P<t^$Kg<aj?+t_rt_Q*a>XQa4CFPv
zz>&^FTN3AX31E^r&ab1R7da+MN=)Hk^NClBlR=w}OPrIme5G-g)3?piIRi~7UFJOB
z0AsFjoakc$8JyRI=u#$U{eEC(ablJN#d?)vcLY4yoaNs_Fo%;sdzM^IS1YjdIMwuq
z=5ty-P%7ZuY(QHfr=J{3*EnSqZZG1*ErOxNoJVxU<~k?47n({iqTnp$NPmNhGERLG
z1a5Ht$bzDB&dKY*tl%7=RKH3q=Oc1{;;&~mgH&@qtVL}NXYJE427eAm9}KPIjO0SF
zo>THB2H_^>sh^;?f%AY4Y>k|3TG*R7HsmU3<{W+vrCXeG1KL_R)f>Ut%4wqe$G16K
zKL=^!tfp+>c8+rz1UfiY_h(>YC&%&^B)T|#X;9zI@&5n@_i*;apci*I+yxNq<#1`w
z(Z^wjLjEqNB?X%LIlNoo9N=`iK>QwO-83v5<ouyV=|1P{Mz9QVF6mJk=A4a3w?{Z(
z??Pad<4V4mG0v2ACwLxkUZgo_oU@E}dJ~-2Y0iAe`I#>GO>%I*7B3#B{SR<XaXuoK
z<}{~<j$bpJBiZQ1EN2awJ;&Kf(Fz-G1!d0Ka^Is3svXznH`rv)T@?Tp2X2ZJN{(D9
z3%z#Y{!~T>J!kI0_d#5^8)<rU<z6RGpBpza8uISkEj00aa=kjx3oovLZd`kFe|86q
z54TnhIbZGp+A8^R7t+bnpBw53fdKBlZjeCk<hMXM&Ye$3tP@<(Zgen+8!ba$PI6a=
z(?yU|+!yx(Etu=x3=>1R#S`EO<@SAzQW)1h8a9P<U#Dj-g1d4D1S7c>n^B757N<cj
zntPg#-lw^x<cB`PeTJNBG2Fkq&~}!~NQ6Kvck?EI#c_3X^p58)|6fW8*X7t_c>m6E
zf9i*A=ec`cg29R0moGu$0=K#XDw4P-G60&)t$GZg7rCiXkWb;>_5^k+_W;dWm$;vN
z2=!^)QZ2?Jo%?koST1uvq->ij+*4hE&fq>qm6_aE1EC>{%b=L_Rqkh-pvaod&FhDJ
z4tFg*bGcmgVhHAOYg$3_xev%GQos$Qty&@XunrQ}xEIqf&P80y4*)IZ@@PW7&P}j|
zg(ci-M+lU1QxBq4#<d~8><#X^mr+^H{fdHU72Np^kgMcYQmM+y)f|U>HP`3>OKZ59
zlygwa9eD~ob==+WL$IEk&x87#+-;wOrGYCUhgKtZcQ^Xm#C?VC**0_kA!qz8u8TXs
zTDYwg*lXp+>_q7{*KQ-a-NyB!581bKePl4LgPTid=1#8Ft_AX4+#TzoqMMtQ0G=N1
zYvgvh!~N9>Bh$-uB!zuk_ETWF%jJu~($9Tk2Py}+$87*}kNX|nMIYk!#iDYUE1=Jt
zjc_ArU`M%6Jp$Mmw~zcS54iWjAwJHnro^-f?pM~A!Sj%NfIOs=+>NxSe8laez3deC
z<By?mnw!=QGQ&N05THnFqs4fR`_DSC*zg2&Pu7+<vlN}M<8i`4?0IEXKyl!$PllW$
zPe9utC*H;)2srb$(_8GqE1|H8EAPctD;nK+Ka(rhomWjxkz>4a3f*|{B8SoD$r~f5
zx)<+rdgi=&&mIJf5AUgJ5MSObWpw-THm(7hKaX(~0s*{SnrH%fT*?JI&Rb8x*%LgO
z7HvU1)k$>sByV~ca;JEU>}aDI%xnKYG=}ijvOz+51Dn7T#_M|uzgjpia1BZkyuELs
zEs{5n`V_^BrF}*;ufzxBH17#o=+E$qDQp(Q3!xL<S>7h<QY<f(G7#c;uk3(@@w_-X
z<0SAtzXx)T*92Frb>Vs52lPZF@(ydz(F;6#TH%v;EInY7c@dN*bCGv-A6Qa&Tb_dz
zsk|y$7B2DZPoalty!f-wl+OF`Ls)T{_o5b7T;W+?f<OlEyFZ{QlQ%_?sx00|lyHBQ
zH*YoCvU#S>XtU<<J}XCKF3)QhH0ANa^C6$ltNaEXE#Pra0=tkmbsQ|$cwcTnTM_TM
ztsup`*w0aUoyVU5S_!ZF9blL8zHLBT8E=qoY24s#Isg^rypxo_TfzHc6G%1h#X~T=
zhWF(Y&{u2a1sp@4>UdY8AXv{^OJ~@dy!}6*v4J;9?&U^a6ceP07ffffX5ROdFm;P}
zoHD^%c<=N=Q!8)bb%@{QP3{Lv8}EsAu)dwwtps!jFI)-nPTn`G(ALFcQf#=J=kOI+
zdU)2-R0!VT1yR_%msh+L*nPY|Xq$AG7j+!t+|SGW4{ZZH2JLL`@xoexHpr8o0``60
zlK&tu#Ot9CL=N+wroitAZ{-fOjq-NU9ojM8ceI*4;2j|A$9d1w!DWK?AKj&U$kSWH
zP@Lq29!7s3@h(sj^%Sp`+@{k!M=2y`cs^RR&GOzNKf)X@e;?3n_`i|U%9ihN0mP2~
z(^jC_^OYI+MI87)(KR$jzW;7m;l!7|2mxpQQ!=!<@L%}@7P|81#{<lb|8qa>Ki&Di
zT}I<E{!}JP9{eEzBs}?x;-TJ)&!N;=Z@!2YP9OeLd(r00|3Avw^yBlhQS#@%K(lQC
zf7AkF0{JT`Y<8UgHO=5B_{pm<KtcSat`I-Tf0NSNPVtX_g0^7(wGZhcNC^K8O0Ey(
zd+Y#f7{811M#A|!+E9w%2P6V5lK(ono}>6~1}Kc?f8GR^)BLS_(U~*+4BDB;@Zb2K
z`-H!f0vxgYHu~H|9RKS`K*#eh(~%>A-$66@IsOrPVbAkl!O_{eFp<wCpZ5j+Q979>
z@yE%{l)~Sa4*6968oI4`iT_;#NE-jeA+V(L?~_OOGJh|<aaZ_Wofyjuevmhe$>gti
z6(o!QOdrTq{*e!0b~ZoZ0@Ua5&(XK3a`{Kep_|8Vqga|XpReM87Vr<zk-w0C?OCX}
z#-F2;WfA{_X^>+6nwLPX^Si8QE8+7l!roGT1D$fp`1Oq_-QaugL|Zxk9_5Qv@GJNz
zRq`*s2-B+gwR9A%=7&?pQ4K$klCEp{yU9;eXXU@J66)*ul2Az8<UjT+df&i5cMG76
z{8>7+Hu2Z&MX8y8gI=dw{O8YuwD3Iyz;5NYY(PhE^E-Tj*2e$8&rxdUA9aML4*niz
zV0Q8kzXF@O_-RET-TbHxkn7<a>703oZ(U7s(O&*CCiM34cMXB(E?+`!rhfhbI`a(h
z6UgO#kAM9Qpbhd(l*e?RKiL9JL;S3@AjACBVStYCpL`4Uj`DvcpYs?$RR*~S{O(Bz
zjPnEI&^E#UG6sqs@?W_G=t=$}>;Hj1;(vJxWQzYCrPodKFVh{Q8UB89md)}rUqyfC
z`1~@!*a#l;2dJ&!;|ieJ2@+`&ZZG(H3FI6EuaVc(QBa%$;v_h>7=3XT{C*9@MbLR4
z1LP_=G!9HR!C(KO<SyvclBLH4VGE$pLvZsgpm_@Zp_7Q0poua8yajiHz~Up=@H5o=
z3f`x+)lX3HJ!}dTthYnyxL}s%-V=f%O2`QkgjYhvNkJV&4NnPf#z8z-5UPZ|A%YM+
z^o9yniqVNML7_V(!iEdV`=KyGU_-%#NWtfnffprE(+m?Wh@zwTX~8lR(9Q_#Xs;I|
zc(WKVX9eH>3+!0I5FHrf1iSix5-<2~J4k}yyKiC4Ie|B2*_;=wqnind0ui0<E(kWh
z1C%6z9&;!Db3kyL5?U_`o+HO_ir@vhmzXN}!5*NO1Ut4tB2BQE&X(zdf`uqu7WjyO
zeMRuXIAAga(-iN{6nK#PF-vfpUgoQU8&sJsc=i{_<p^$4c5AMnZxkd?kZFQ3`GWWt
zV4Af+pcq2e3I#iRfPGD{iefNDg5jUQQ!MDDXZ^askK8>af-PS`VX5F{im#LjOq7>;
zL!kT?!&NS*@jzRJ;B^WgR0<w!2UwNh^a^lR3mguBrAClOmo;hyOHaV2Izi$hwAEV$
z{^Sb2DUi~#-yq1PZ2m?;?M3Kq61+zt<7Pp(EwFD1ey4liErRnj`Lzmi$QgNCkU}2A
zHbI;N^tKBse+TIh{6wLYPC-1yN4f-SCLqu)h^J^+kHDuLZFdBocTw3Zu&NJ(_6ce@
zfVnH!_AhMf7s$5&dq7aM8^+udH0PpiP_Shq<nIeEk*j1#Fqs0DVL{kFRE`Lkc0d^w
zyhH;$CU|Er`tm?fqe1DRpo(1OlY$MDc=1SJ$3^9oU|S4Kn-=V}dV<af40bSTRxm-H
zyE%bf9f*x^X+8AX3K!Fk)lOJ(94hREr)joz5L#1Faug0mfW=ApT|0gsXJOU|Y;qA!
z{qI#1zDbTwHzAX}i0(qJ5Gcolwy#6nLpUA`0Z*Y}mlZr-!gX{Rz*~5v6IS>Ld%a-3
zuaJEW9rY7>u0)%^Fo9On0HH4fr9fd5oyd<1Kh6N?31P`Kv;_%MX=iX!czZM2P6?wA
zq7%WwPvg)QB4p7PGgP>S@_E99iL_4$7k;;q0(}v}gXIv66uQobrBT8WdT64BKe(cF
zTDXCxtuw;6$#)PV9HbQEv%*j5g^d+5DGM@AIIjeycwscnQwhTUEL5Hoz8!~-o)-?#
z9zIc6PWyxl!dRL@lY~9bVbqd^b20S(T@=2>hJ1=Jx(x=W3co3arc1*8hhbBi@YSV|
zPZut@4eZOp^-5r05&pFwZ5cxA$B@eue)RxtSwcGl$W`IUC<L;Fk#Y=Pj?gO=3Uh^L
zHUT<MI8p_h@`ZIXP+uU7e-C}J77B|V2fZdNBj;C<FgFXJ#lrP;X1XrC_7_Nr5dVmP
z7f<-`KM0lymE>u>A(USMXt}V6@_H(S&yqj7QrMUVuqt88mjJ64e(*NrYJ|JVOI$1T
zqm5XdaC;+I>V=EwV#H0WkogacY7*Mh^4%=t{R!4v!Uj6_wg{iTi?&wbA3H#93q^F1
zxlLF{ooN?(Z-c@P;p{e8*eT?mg%w@GZx@55TPUT;uSY1Q7w?WRnntu&_<JHS`-B^5
z>b@(i4~9U$(7N^_hIBv}whS=$gmar<+o14Ax?g`^SiKkHJR~eU43=Txz9o<!5w0R{
z&Zw}K4*g@o9&fZg5Dv_tZCrT112#<vSL0y6@S*UN_b^<OLc=OxJ`%qAH!!D!J80K1
zEqoyn`euavR=UJDD_lv-;hfNw;@38!qvQy*6+K#jHak&W0?_P5Hz_vfAYuvt<0xvN
zWz<QOGzj7>QnY}$h?2=0<0{&g2o^VykQ`0!qC#?}9uv({q|HO*OS6`z$c5s^UZU0W
z>HYH-9hra%AJKEP&G8j=#G)5|qHj4M{vrvbT?UBu9Y$NA$bs%`92fD`u<(S)vkquM
zqPuhp;G`&x?h>35?Fc|ASR|*<RD_5MSD+LsTJ$y)hKZD=s0<g~A46q?Xyp)H#EKMM
z8-e;LQ6&XNqeTs;q4%`N^-Xl<j7UkJtcwvX{SgCnRy6u81Y<>K)o6<o324%c7X^~n
zDnZ1g$@-jVunn5di|*e7Nfhm<0m}uE_+RusNwkaND#@b#WZFehDP|q(!W2>65wNC;
zdidbEB;tJlE7C+hl(U{LYFPnImqiJbI*}=g`3{0vB5(3%Tosu<f=$_?;bh3=h$J;Y
z$rX82faHmiDYTw18afJl3q(U_F=~aPjei5|n&=umaz!GA0K{4>y7w9Ab<wYJP*Ea!
zUkLe9QCcZL%S5+dhTsj+QgV)zi#F_n!U|D%1+1tPl{iC1m1s>I?5!3ZW<ah+^!j5k
ztyUzbJy)IR$rdQA7x~b<dQ&t+%YK9CH9N>PiWdI>)0(WJ;2mIX7P;D^@s{Y=ZNRjM
z`p%-URg}bm{B6+zZ?Lq9_Phy}cG2ID!QKv08_hnQqS^_NF44L%sOT2Wqw__NXhS}%
zxFgbEg+Q<9Z`w%piB{08byxI+6g}$~rO+BRAhNbyf{J@0@d1DiiVj3V?|qTB9Niug
zt=|j5VbM%8RE&sz@BsFx$cv_yG0|y%lpcuYlP_vq6#Wn=6Cxfh5)VaDFQ9Ewv^x-`
zN20tWU`~k`F{qpt2_Fa8jOgbXK+lSnSjkg6Co(=n4{gMi<Q%mXe@l0m?8Gi~dC6W}
z|1L@nVuwYr&{4cL8pKKb`TsVT;uLaFxrlqnA?_-^n*$YY;!GM6cX9uBkUJ)Rms}4X
z;&%EFj;C1g8w9+>-<v_a#jAGG`{yG*_zN0+#f3E}`H8nJ1B|~ohqj>s;+Fz3Y=PqS
z3!&n;xTzC;IwAI=gHVuoA{mt@#k==I?vz+V8CRiV!#Rw4nD}lu<if@MT(m`qKX?HO
zBgK63ZAOVVFd-K$mhGTG`)P6E6BxuZ;&%hV6C-xJ3>9a^X`f((V#P=PgQhq!s|cld
zamivBnjl^^19DD$pSE@9#Y1#@O%xyL2Fe9-0iFMn#7*?MrDU-e`Cl%I50fJzMZ6^%
zBvt&|O$b~Pk7m>RmnQD61a`W3c^+)LEKXVui7R5E2-q27{Qxv&ir=IIO_q2)o#C&F
z$0!JxEw+%eJx9EUVjH>Qri18xp7=cn=*<@wQP`wFd^8?%h2l=y@?8^;QEEz&*z*ur
zip5RjKe1jHFa89ACE`KaPL_(_vxoXJaZWxYZis_m;=*$AuL1~Gh;6C>S}A5w8dsJ0
zLpxYeEnY`A5o^Rh+ryYz@k>$YVV$^>B0}|I!7Mc06wma6r9o^pp@WU${`tUc5+5Qr
zXtPz!xq;#>v4KwAEn*MyXS9mv?*aC0@k}C0ZQ_HpCbx?ZZ-GRI*#CP7bczp=FRDxY
z#1`o77AH{-Pmfqev(_E)RyyeRil1zOK%Y3P6YB4Z7t@v2e({njv<-;6D3|%3*!o8?
zcm~CNAERsc#SDrs4T(AXQ8_G*{sUx0JTr&3QSrSrm_H`&)k4Jsv7H2DT)d9*h9|@?
z(a!Io_-P(Yn-u%^q4JUVE}1qZ4tx<P)8f6=AT#256pFNwJohKm+e&`1ZiH=ik|SPF
zVJ~T=Od<!#rTbuYl&q)2sFNg;Qth23f82(Ii{w2zm$*v${)3#Gq^1>CxJy{%4ml=a
z)0x&o5^x*>o|6A4wBaRbrrnjdWOzH|d?bIJ0H?3Sljb5n$zN>pfBH*2C|@l=vYb2+
zfs#+(2F!6uJbCF)NEqZN3zBgD4_!McQLTl*Daj#nl>|#n=KvET`Nkb>p%Nzw3WiB)
zDd!<vVxUuZgrt~~Ga@B!^o~SHqG+_EB|of&O{XRM*3<iUMsm;>pfQr^4G=sliHU{6
zSjj(hwI@!}_Y-W2m+&&smLU0^PTl7u4HVKjFDVhh!bHiLP-wa!$@&y>NfKN7AWgF5
ziBHgWQBvpwk|ObY8CIl9-l9|fCCQ^maHdICXeiM$UBdbZ*q0^se*@-<<kdh(WJnG_
z1W%^KuovpHBt9BcUX?`uh(XMjymSFDIg+4rXv>xCdk)xnlE``p<Vzw?qf{XAF9cYj
zM0E^u*Ca(Wr4&iF(y6;xl3NCp>ylr>QL>guo~BcGspJL|Xl0T~4tjV)()1-N%O&09
zQ>u`Js31`(Sr7pgRg&{{V5ydTECoxAq=Qa_wUP_VfL15jLHoFRNzu<3=bIAuY#7rZ
zS@i@28YN3BA<!h5Ed*Gz<ctiJx2zIdT83LB!GkckRpOF{#@mwF0qE_J9HKLAr(~uC
zdb=c#4MV<L(v7g`!XC*x-r&3=nWm(YUdbAIkoqJ}TS4whaw&<lU-Dle1O_Dk9)&UY
zBwaOV8<d2Qr{=yS(FB$uiS==E;|xpoybsn9$&NNyF)CU2BKkBYc}@fJKoWEY3dbeB
z@gNhD{Wh@sq2w%iwk9PVbeeo5$!!42lqBgiSf(X{IVhZwY^Dpnvl1J+Cp#y(F^iIo
zRFnz<TdAKTpzWj`R!T#$mm1ci=pdD{!Q&{+&_cpV`WyqG&e9~x#&?lAw4u#aDyC`6
zO}dS~y5uhXoKD@xq*Y9`c}OQ|74?*6Rf5G!`lcDgTl(c9wE0MFAEDd6Qa>LIf}eDg
z12Fxie_gSH21xD2=u@C{|33gdE?q~{><Q`0y^s%*8fm&aDV?o_-KV6RywUAosf9MI
zA=0zuP#7u={1TvH(l2~b87_?z!KMi56uH78r5Usrh?4fwz(z|;$k}~bI{FqW&qybO
z>HHTXHAjN=taQT|NUXFcA1dOc`Y~X~OMB;GfD)v?(HeD5ddCfI=cT3OHcFK0DG}*{
zltXt~lcZ&TK}E9k^-s{Hi_#v7P^L&Heu6Qn(mzwda!LApJTTLw$LJ`KE-gU%mv!M~
z>8m4<xFU5N1Zaj-LdVEV>Do4wvZR|6&~{bIAwO5Pbd17VIntI{Xv&qIT?3c`DeDBf
zT_|1pD^y&Qp3em-l7@w%FU8Ub3ea4a{!t3d66xq0Kq-}$QUJV6YR`gc)*I68?$A^&
zeVndtRY)7fkgt?hHsj~2l4_cvqFOpe&sB{yopyJ%QVIF$>!hyJz^<2a{sOrv{p547
zG)SMH1WTiIS0TWfq^1FYHA^kz6}cs4ErHoB(jfubTBVD~7kt|)eeoz7+oZxqSko@O
z&<yMjX?Z0&+9~~pjyGM>ln+6=r8{1Re2?_(k05uXLA0yvl?GLV^hvWDK<-NGY3}To
z3MsxcAWf!K^q$nP1*Ji$*Z|Y+OG{z_HYClZw1Hu%^#HBSBT`*8Ku4wNw8V}{-w%X|
z52XK=0c~7*pAKge(k|K%J(SMS4tY}QO0(r7>C?3Dos#ZzhQPG6Q3p*kQtMh^&PqM#
ze&C$+lo2d8vcqaX+salqqhu#*ruWZYw%kg0S{-DWw4ON1GAOspN#^tdh_md{U-;Er
zWP9npgsbfH51`jgwvlox-DNxI)O}1=xgBU8GMl%6<|#WsTVpR-Hk}l`WuKOz<Rkl-
zJP5ur2lAcy$znTz=`Z_$GGzi}yG~I2Jy2FgsaD5jZytlD6Ed$x{31cJWmy0{DSNmL
z5~pPE(dIu`Rxu2g5E*80ym&H+D@d5Ex*nRsWh=JBrU;o!I@CwX?o-GtN><{6wllJ4
z{s2mh%pidHS=rYVREU-RQcLe&oUDkAUc}4VY`~Ks6VO)XoGgdd-Se_9$o-lqJMar6
zF37%)fr=!VjLz`MGWV<K+C|x>GLRJ6H?+k~mF3Y=cS-iX3sBNz|B~k-UG^Bc1ux5f
zB1hg8*(blEEkpJu=05AfOqnBvHnU_Av=CgC<<VX*TlV5C^ybJupvYaWY}-DNJekJ`
z1oLG_f`C>aTU`Jv3S|kD;C)TjOqXMdWJUF8E0!@Gpy|3SfCsP=nd~U!N@cIp4y;Vp
zR0M$=vcO`LtmQI$O6sbR<sE@UrEK0!z*Nbc=tr-X{X!Bove!dVs+9$w1!tY?_kI{!
zFAH6Wwwp4?OR&B{mgR?zHp+rtfTku{#V=@UmZj4BcS~lVSEWU^h6j{ZnVvFEZp&B$
z7|}MXjCl_d?Xnx>O6!n)(FB-I*=jHFbjd!UJ$1KiHysyxWb2KPza#tUB^cT(^WTMz
z_Q{$k#&B0Ax(gNkvZh4<8<2fWr<{ATr)l*cl-bj#qwdSnv(Yvr^IiiD!?J5XfQ-nj
z|0e<+l{M2Ib4<3S8!!)K?TbLhWn1Z$nUF<LQrbgV^e&)H%2+o6^GFsJ0Mn*qo6;dZ
zEqjf^=rgkF1ZbL-9i`0QIT>>aDsAM!AEIO{Z<~d<oqQ9`%l7i4%Rn6D*R8LDI?7MS
z0nJ6es~MVH<$X)Q>Lx$IL8ZHV2W7$@lZTRb-b21mhmxn9PiZh-^7*b1@RqYAP~jtg
zIt?to^4c(z{N#0%H|a0`YXPhXkZ-U9W}v+P0PH<3AKHet6Y_TsQ$#699->F>N%;qv
z06iryJOC0b&%J}*hsd*|fEFrW{tTX^FnL@X)Q8It(rGe6es=<(k#eW6AP^-_)}a(F
zmr!*3wEW66Fwe+;RDi_DRgEBL<x8&tGgdxDS&4CS$uz|u;^p`0be16h(H};glN(~8
z;=Ejyf>NT~zYe7fa^ZjIMUuRVCgf!K8z(Vp7v*`BA&?^PIE7y%Ro+d$#!K?$bp0ny
z-f{-w>GB(oAaGf}h2pwb<ad^#lpzlZ2Uw=O7MlR;!Yp}>7mT_pZ#WFlZ250>kk64H
z90O0TTtXio%#)|ZLq1<VOwW1&ei-O2lxI*j@-_Js9WjgKGvs0|mj6S!+}Gtx{h_Hu
ze&zv4sr=Lq3{aW;y*JTzLvG81K)HNnGQ_PF@}WU!s+9MWFRM!aUK9qZT3)&uDr)5K
zzX*l3@*jsGUnf6Ci(<Xp+YC)N<$H=C*C5~K0D(sNwRzCgB#&B(%4Ye06uZ48pJbxc
zBA0%MQmg#aGa$F+OLl^^$@_$mYq!cHB2es*$L+*8cgkBXqP9!^%Wjmq<%c7nzDIs&
zC5*WvH!K9&UHQH}VCk1HI|-Hn`L<B#y(j<l4oZXa%}rprFSqT0+>kt81w)7BQ?&IO
zk-tMn%Tam!QHYPp#h#FRAh*6@L2+E(K=%hG<c8-kLJ#HZ7hq^6<wsVb+mGZiv@e>H
z`{to?T5hE)5i|1NscW<HZd#+}<bIT6Y@^slegRv>n-svdQ*i0^wO7a}-@rl9N|Uvt
zV#gsE<D`)8gSfNePpd5&T@)*~0Mu3S^c4^{MKTAC?h2oyF#nk121Ow~6qhE^=BbG4
zMK8P*QUg?YE7Agh=A($AbOm2U-F8^vr+DriX!2KhQs_BA(Gd;tKt<m(5I?S{qR`?A
zg=z`{L5ki?+Q^+$tfUmiQ;Ku6>kn2uMSJQH#ataqp^6XIp%kY0meSk96~EE66`{!Y
zg%yzs-Xtoc6nDwX5UqHNoPDPilP^NxjN(WL+F}&bl_;H6?6IH}t2jmXe&Q4?c>Wj0
zEB+gx{Lci1CnYMJQyd__&w0g*v`0-;IM98E3yNz$pe;$!-U{qw#ojwme^IgOXPBR&
z_?XO2RSZ&|!X<^rcMwQZRICAZx*~}(bS^7yFMz-m#fm2(o}o}Ihd`#{&jAcxmcrva
z#ow<geq*39TT%N4U~&}ov{A@a^o~Gpp5g}w*p#pMMGx!(MO6pT3Kd>H7{qIeEp$36
zQV7U9Sgc5Ehxm0x+Yyw?6mK`7bVG5R-imU?+w?id3Wb#N$0`+X(pQhF6n1Q|SgRF3
z(%q37MV3E!Y844|hNx4h3ZSW85%xHEZYoZu;5TegWU!&IQSr_MV44)0BT(6_IPnfl
zyQR200?-yk)<@`Ct76HIsJyKRdKRQjv9TO-?TW!q(U%T|<ac0pD$?m3)n!$zEQVmW
zB7hFMJ&G~P0J)=>{~oY=71G@h>{Gn|5Q29VXZk?;6))|9{D2~cGDq$y=Bc4@P*HmY
zX!jLsH$!|#@g2Dyh86FTvtUHwI|&V=3M<W8V~T%00sTOcM^D$d!urb!2u>*ScYx=i
z;_q%?Pb%EW+5SlJFY!z%0zAPot*D|z<{3q`6xg$hX?kPk6c1>kuu(>mQ^!_0NlrpL
zr41bz?Uf&qhu1;5?-F|EsC<<+Jx<Eilvm-bym$m=yC`4Bf4<?xQ<fA$p_|g1!YA%Z
zpWjeArqurfc@JeVWiomyug(YYQg)R<-dpMB3{5`Du3J#=tF)(+rk`@b|3Y=j!EkT}
zDE}Z2ZJ?5s4fV&B)0ByRLix)skRWAv0@_Y0ljqa>cS?D*7V^Q$w?0K<i1HrACPS4`
zl-wDnd_jn|aAkT2N)bx&W3V?;xtk7BQOaa4G({`f2SH9NV<?DuM)@@@#xcsl*C23K
z$yovovC8*oX^vAq^oMx7(*71o7nM2xNAF*X@;xVXG*vm(3Qd=l_CrvAMR}K=^$cat
zK7eK`r^#KGqdZGVTDi(^k3vPMaxo=W-%wV54VH3cFhvzAl)ur_U8yXl-=|8s57)dF
zRx9888Ui)SujwdVs}xhpah<XX4mIn-o62`S18alw2fA|IsQjCb#!bpPTbS6a+}Q)Y
zx0Dwv0otnc^M$6{%5N{BPi@MdPojtI%FT@s?@)e8QH3sLJgvLk%J;}e*`wUx0<b$u
zH%jmARsLy(c%L$Y2Jf!Yk@o)90c9jj%=eV{{^tl(79L0AeWlNGR1PUQMX+>O`5aAf
zBg$afOphv`rzdGlnVF8Z2TH#%l*X0fqd=Qbj#1j&LuCygHccu|(MI`^l1q-QY2`;!
zK+h-(DZV<ZZ0Z8%oK<<aA22qmi#)*Cs-7T6guN;=4|Y4KcF>vDQFZD^=yg*4_A7|9
z>hU`Obyek22Be!xPcB1uRU2JFKBfvT1o2Rn(E-d;HT@IJ_EM#hPsc~anS>%=l|v>J
z`Kf}w0JOi#x{9Lt0V?}8kU&+!Mi>>OTKXI`om83W&~Zw&p01?@tNz-9wh)yEr5T2*
zf@n(+p~|O}tw>dh3M^5oeOpj@MwPt~R>Y`eMzoz(*?57(tC|X+FhLdk9n_yw?Ysug
z3#tq&-PlP|&C;<dS@kyMs-&t;l4JXls{R3Z(o}|JC|yw%UPqrYR3FpjsZ3SGe?ZGt
z{YC+R9970!us&C{cN{2rs`+$U&sXW{(N>@urSEAJsRAe?uvoP=5vA*@mN2xHs9uSn
zC!$pK&OykRsU%Oqm<pAOvX&}UYw0XqrHUn&a<%GfKGfH!)RfRstGZ5Z+ncI8beL^W
zg%5!=s${e~yQQ*S4zL#061vXas@j~0QoHIIO7`zi4g3kPPSt-Dsqa$VOQ-l>x9YP!
z=xC2Bf)>?5RnKYYy|3!I0-hn22X$sx<xh#9BdRi*?nYHx`+zp4+DW^@2P$tm`i!eW
zJ_pK#>f2C=KUB?M2fdT3-4?JsQr)Co(v(U=uDfZ~8FE_BsO*uVW?eX|`gs#H&8doQ
zP-~+u+7A`B>W96kv{Tp7cEetM@+Y7<sOu<Q&r$tUHPkz)XE&hIS-s{w`sAX%O&eBM
zwcS><xvA|>qxbG=6S<p@sk?4Ny@&cU4?ugWd8ENh{SRGOwfd?bQoPeooxK-4{_0mU
z(U|~sA2}2P)q;Ao9aq0XA*>VXBHXxG7^L>5OIs(^&(f|iL~YK7p`mKW)gWQ&)wF{O
zSF_X57NK59A?rx>kLO`Ul$uS7qSZH^2g_;omUX~9V^!aI8nrR%zdwfjS+&z5^fy-B
zN-t%c`pMH6(s=bwT20TX*HcdGdG%W-K@!#J<Vd`rR+j@iN!^?TmSpwk_feUu{`Xg)
zTv9(z=lV4DYtcYSS1Xr5(Pi~Bw9mexR#BiNLv1y`1`{*Yeb0h5OI<-8-mB{BbdYTI
z_=|waQE#LBy1DAARZx+qzCbT^zIyv9kV5sEeqa}?FVJcIy1I%Mw-WVhzQ8P1%OfFB
zrmnbz(hapS7A)oJ`?TCws9*gIZI$W_>w3^C^{#r5YIWKT$k(V3yZ}<Gj!=QrsddgE
z_3AUbFl>$LrX(2Cq<$?DXwB-s$VYig{b4^;w5Z=~fxT_&JldqStLKq19qOlOL({3=
z77p<)^(f_pcdP$>4x~rT%%%9>9re3^U`Tt_;$TShsU1>4?y9@*qOxB-F$*%Fj=2e#
zd+H?y2o9=On4ou9oxy`KW9rZTx0hG1B?siV`q5RiO{jZ{A@EQw`40m$sSa5SMUT`!
z??&5{I+bSPX>~&|-G7)--`WNhv+B?i)Xu5Dp?#U1rkA!k_L|klpwL0{7G+d8Y8rKb
zand~Y13K!gnWV2Zxo8}G0qUwb9)upcX=-Tla@V{k2j(%&^Y5bMq1l%Qac|94^2GUQ
zm|>9f)v%GN##rd5siSXy_-o<<0UDrLOTP0Hnk{~9SC?8#rXU`yndgE|glJl6n8G!0
zldmB{BRB}Pk(y5`fElH!&w++$%^vFYY0YJCfSl3zy?|1TCd>qZvzp-z5Qx>}gaa&2
zv%?epi`Trp7;+aiV-y2P(R@Sh<y6gA<bS`US!wk|W18lq4bajx*H5AImo<*r^Z;uf
z&j(M2W-(2#nVL5?gJfx<J^;C@xmOQEvo+h@QOeQW>jG!4Mm~U2o~G~!!16V&6e=sw
ztoDG0LQR+xDz9n0X{s;M)RMomSo6<2v_fCke0UkQm1q{wd|s*%ZURi1=FMZU^oGVl
zNq^-U(;jrKLKE~8Kr1x{KfqLJR?!Svt?{OrutqaZ*)z2oQ!sj8r+Jz#^4DwPD*$~{
z^D7t74Vqp(3~kgjT!#84&9ABSnd)Xu3LSE8Y0gt>cZ=qUuOZl~`I+X$+nSwIP~WCu
zlV_=2qjiR+4oy5IXLV|N$?wvonWCq%Thl{dS?bZON`%5YnuaNmUd<^={OHqcEJf+A
zhC{hh{hF&D5FgNJ;XlM@ay66WQytW75JCRF=1=mz4rxk#z%#7r`4D<XGzV%yMl~Ed
zQIBc9;X~koCVv!_<C?&K(d`LM7A1u})NDHkGO2m40-TRD)e&Hs(acPM%xavUM_=YN
zhv;N#r%j}J$!f3N(*x?D-8}%}s2%PAkCRrKjIKFrKl}-3F4|cZdf}=)v=AM2)9!j7
zobK9~m%(yOJ5JZ(JhTQf)Kj|vC$5EF+COPa>#aRQdr}{5?w1ho)h67;`1)zzp}EIj
zEBYGUJ#N)LPI31W+MDD~4AP2Ug2YMf);O@9(jGbk6~WpOx^EGpjhctbP;K>gu!L#Z
zbY=+G9wTp8gf`|?pharuQ7kb^dy2wg(b}91u>Q2xUxBtW+O^N26r)`!2WFgh2PL1z
zYpoG95hrMMmtfR6?Mv&?i}PB|7<dx3ofh=sf_C63uqJ6+H$r`~cJJR{xu`uvCx{d+
zqYUDy+ShlYbV<8G49+y|g2ylj>Dq#En08rfOLr5lXc?WT%+Ly+0cWN*krEKIw7*y%
zhf!CxA8m%g+1j6J`OML-q@7o;_H()=mZx1E0Mqid{2~YzX!m^rg@xK8tn3S~X%~@O
zyhxi)fsSJB`Q1Rdu6+~;>r1rR+aO-5ogf!wnf4If(!ZfKhoV%jP3r|`g*MujymOV>
zXPi*1(oP?TV6}FVZh_Zmzwd&=TJ5gqAW^5?O~=1_?ZtV}dsEv-SBM+5>&X|?sP&@r
zag%oIpHSGW&7_2+TiSv70Bh0SAxCMe_K9Rv-qyy_|H!myi)kCzu1$-l?EDVxxjh(!
zPAzv8#;Z%aaW{CnwF^GOuhy&mmtOxqZEgfq+|}9~K&f9l|9O-Kw3mKH>7Mq_B!~}c
zzootVeeL?UAvdHQq5$%+c0FyNMzp>Tuy<7ZE(_3O+J9++dZ6XPb!J^SuKnUTOq|e`
z+d|@@c6k+So7DbJ=YmJt_HQ9LrTyYIO4C~ZX_RKP#tN{^YF~a0*mGLm_aHX9xihG=
z)g5$3C+u{;grU-2H?a;19dyen<-$?tSPQeAblUSkan{)%hFYtOPEJY2uDU<T|KX<l
z^#owtb>}yO9Mi2)qE8;WSILL#spFU+@1+~u1!KH*SAPPGk1oxK&iLvM-Up|j?ke5J
z^VjYE8l?bT(<n%w?u!MGJFatm4;oJBe95#R-8e1!C-FC3W~e`<`z8dn!MeB$zz)$R
zQ6^HTZXPYPVLH#<P#>;aPj@jQbVv4sMCyL{3TRQf`{aN)qg!_dDq?ii^j4hJDPw^h
ztDD}0Qk*WA3zm3YIXOHMbX{w~c}};4a*odHtf!2CNz~~=z<NRV`_CvP>2hg8Pu8&u
zP<c^zkpfsLx`KRIk*cd&fg!!5+w(cv(sa%&^gdme^*!1y>l73)xT5=tMm9rN#Dx`^
zx@XTqVU})LA>^*=PX7bF*}CM*=yi^6&Z+{<)lGSUHBV=z_<6qWAKFM2==KhQwNSS(
z6P4F=ACXI`NLLjIm||Vy$541(S4)ni5?wAuMoM+<^P#Cs*G-4~8#))7&&zd>=v+{t
z>n2x4rA}-FN|mnQ8cNl=+;{18QlopBBC)kPHW#&ZI{woj^}5$6QgBoEei9@abSo(Z
zuu=CFC2Th7-n$FZtow-`om;vl7pQ2_1-*u`Xw~^-fZWzyI)|}n(|OTk(5_>DioSH|
z!fE5xt;=zTh92F4PVx@i(H-qVu~(OD25X<LoI<d7bxXehYroE+9%MkbZ~#McPv^4@
zHVx|TQJTYjT_j~^4CzAXbTO=R9*3bLx^onaAJs)th<r@<8y$5X=-&DlnB%(FXoi^3
zy=nvUP<Lh%WoJz4p4$n%k90q*1<aIgjF#AGT^gl!&*(Cq0?e##H91P>blYiLWuw>e
zpu$!k-v#w{dft3=&0cTV1~~`)Eeb9>>R0^<PA7c?`Nf>|&(eeFqCZ4uBv<{GV6?gE
zmw7?X>aH(8i`rxQ`q!b}Ltk18c~5--Z8yC1>k80cZ~dQ#q25QoD;YNV>JQNh@2B_6
z1&hC4xCm$g`uRF&3e+>d1=w-@uBT9WLZ3!AdxP}DZ$j>*-kI{PPwCy?2UxKFSDKkZ
zta=k=vxMr8E(K_q-koy8BK1AwREg3rB7>v#w)7yz=!0l0epdf@2smT){Q}sVpnpn(
z0Y0a{G9Pm1^~-1uOVjuM0Zr+8=j~v*tbd*ytXK3!l*FB(zx+7BGWF{hp)yNvJw|7i
zt9n0LDzo($C@P(!S5q2huHNejXv))1P`+rseu{D(3-nJ@P_IyLyBV6U>Fem^Q>1?p
zf&PWXdi*gw-U@yD6JROPUlRePR4*Z4d6|CkM-aH7-~2K3mFtVNV5!hYSs$XdQlI@K
z1grGdD3VmIfBp{4uhDCAU`(xk9zASz`oqrvre1&JEJ`=^Hz@h1L4Pg^0*(3~B<NF<
z{>r}qZPx!qZMXE7=v8acua$$e>TLr+ZtLf*g}yeu=UeDfyB=R>0PWDfPN$4c{qqih
z>C(H<r(nAEz1}GG=noeG?T-G7FqC@rpG5$sPrt$uFn9I-bmO&O|6d471NwF3dB3Mm
zc7fT0dS_o?-q&Z-XKjY``s*kS>qqXRG@=is8y%ziC$G@{b4=fU64(#)Ve~VP>q{2^
zZ9+d92Tc$4=a!;0sh^_!zDN4hBQR!4f1MJyX7%;td6?6GW(Bs5VU|LBwgyon2H4K<
zi61oC8&p}SbTF)=;G?6VeLV!63<tgkrnBJ_%*57(E{4q)(CBLTl_E)Q2JZx*xf^s{
zP<YJHmx?wILlOnKJPo6C^6@eV`q1WWc(5M5@G(3ogE78_KaZj0XQ+CO-U`D3iU$W6
z?k<5`pkZn|tT=9Hp$+y)!zZ+IoHDGZ1V(GHK|l!xA%?hMG=>^nDIY4#u$R6T5N^nl
zfG5HrCcku~A&6k248MK|foMZ5dB;y1UZEq}8N+HnbUVf{`ZmZ}gKHQBVhs^=-9FB+
zg*+DVhJ*B~BpAM+@WDAlCglU3f5VU$i^fF59|D+v!C+bji6p}>bniXcaK;{`iw55;
z7?WZMdj{Q3HONa*x?~9b9&%|0tKZ2omi65sfMpt5=sC(Vv^@gjRf8va@v{wzYpBdI
zw5OqzYjArBZFz>BDIocV5=sg#Fzo*n<`x=W%LU3c!;l#YiVTZqU~aKt)m4<P8@}m5
zTZtj152aGW6ZAur8CGO~<%S{BO0lAH!?QvZD-8SpMh7bm@h@X2stf`Hx>9X;e;%x;
zG5qum<ZBJRN+_%|cvJAb-rz@GjGKnP-bH1DA%}j5MnljMpfnl!=uK%hbag}Smf>$&
zTUrdKvZ1Ke5JE13c0>5T|9guJ&&NPvr{U!qbgj#9-V^fO29HXZ)?@f<H`?wP#wb_5
z*Kkn+`96b`u3+3XxV{e+{f4dK5EwALF$<gS8P3qpGH96VhunQb73JIw8K&k#eAv*N
zgtigGYRZ8bH7u#4Gya%i%^9FQFdTdg3daq}+hN6oVL%N{j|`p)$WIyeQJ7=e@Gd#4
zW(;@Sz&UGJ&=2)<2A^<@lZ|n@2gKI6GYBf|j6ttM&fd6(HYpB9|HojOqw(|z^g0=<
zjsVQrcmU4<f1!(UT_V)G8h;^gk(;rZ`~dF8_8-A>%;@D;Rld}^jO4tHL-Z9MALE8%
zK>HeF*1|wP<9oC*_BWQyM=8K~+YfDlMs^hhjvGHF|JMoQ#}xAjGKy8GJZWqqkMk+x
z%M_^%HlCzuDa7bT(|@S(Ejy4fV;n7-;l|7K`O*mEa_c!@M;aY(pf<|5^e0F}8w++o
z?`dPjN}!!F{!8)Z7-NqwSk4;fC?7o5_zc~uj5D%|LE?=b-(Xx5jK|lbbk4Y#-tY59
z=QfBZ8V}Oe`+`v#3zj6~{%D9N8v{l$E*Fie0Sbhq82@=5jj6@}a)VtmZlRb*nz8gD
z<kOAsuY=yp#-AzXam85pHUu+_b}zutOyg7eP?%**@J8EJ<C~tS%r%BChIpQFJ7vD+
z8{?jVc!6;%rB)Og^BSP&nz6qPLs?`L8fdFiY|JbL=yhW+`Oiv>^BqA-jREN(WyV)_
zK*bFs^Ix!(8~4A8QiZXF1^G&2+ghloGA?@yov1d-C~Q?@{DD^DT4Vk?aMl@Bv{9=!
zZtVoQY0Q$NgAK-La-K9A_v<MUuF2?Pfkd-Wy$hD!GVcEu=C>F(rU10nI6--7w~b%Y
z4!q5{U=ak{jk_p0ufv#G1PeQjtG58V%h;6!fo|gmbUmWSC~kn<9peQ$7WW#vFTmbD
z;~`p!?;4vG5a>6qq<nqrfbl!pINdYG(U)Wfjqj%d`@V7NH<&+U45oCVVdDthVjD58
zd<QV2M(<T1W5&Xz(DcCAc?ojk#^wK8pp2fGQ1Q_CGKF?0jR~}DJTksMjxJ3Zy;>nR
zZH%Cp-;6PM0By5Yqw9NsnKQP`L6ePXoPJ+hQ$9^ocBYI}NZ6aaDBsb+Byxw{j;8XX
zQ0QW6qbyNZQxRS8aWf@SD9zop)fPi?%oN`YOb-*|JCr<4rId%@Wx84jId4-aWtsVy
ztgk`9*JOQHhgv_=5=v_FH|?Yhj{uYNW{^PBcjOf~ZW`zVIbm8zKGz^qDDAROn!cd9
z>y+v9t*8t(c?LjXh-u9NV27HnNMTc$iN6{s;iktaDjH#G`v8g}O%EvxG0GGW3GrxC
zfc5`SJZ(BmkJlNKDjR|^raW?bo;5w~47+1Z?^4Vo&h$n)+Tu++j6h2;MccxrbEahp
z7|ZjfnxkMzH2v2OxeKNp&jK^aG;|nk$)>L|P`YTk{Sa~~rVU!yn`#mkq3x3ChYeQ1
zq?uxyU}?I^X#;96o91qyGgnNDAEGV8^x_+6%QStO5A(B3-acr%YHI2LTDIv03s`bY
zPrVBDxu%_3u;iIuTLOW6Q%fCK3QTrv2o#zW8_<_)CYwPB6q%lQ7kw!<9Zscx1ix;&
z>ja(>(*w#iC^aof08g2Tr2%M#iLHXcm8OvMV5u@KqvJ%i>A(wMsWEM$C8pN&_DkTb
zGo@{X`g+rS%GkSUdV<#F29t``{6<qaaW<JY(#?Qo)4TK`s9PrQSLh#!TTH7`f!1oe
zO)>D>Ch=~-w3({1!P;(GL{nOa=@p6scbYcmVSu|#`<j8>Z5n$PntDv$P7uFidPo-u
zdrgxUVN9QC!WVLPO=JGBx8LM+2m%A91(fJ?&-C+rKo6RhkoVDg-{iRlwL>OPHROj)
z5#-SsF-4F!Z`2e)Q{kBD5qV-Cm=2$TY2&6-G!;&m_%g6OH1$y~)}*PO?pQuD?Ysp|
zQ>OP8LH)F8@L34Vn6A)HVAfPcN60zT6AGAZV-CCz6kDtL$L~?JGygCN343#H6NrO(
z;72HQG>0f5=w#mb7OZeKXVNO@VxBn;6|Uwq$`x=k&r%rG-JG`u>W`UsP)e4E`4Vk&
zJ<UawzUyUP_%$%S&HE^I)W`hTLkReqH!cG4Gh2r#JbB7|jJy%S=Ezr}Da2ee08OFh
zEp&Z5%xw4(mEq>y60k&=Lw`qqBhBR$z>G5U-Ov_owpOF<w0SxCN6(te>0W!RnY98e
zapnv+pv0Ru-UeraS^6``Idj|?hWWhN(YgbcCYslmgXe<TleQ8`=H0J@B%51S0`#K!
zCRL`GUk?Xps`)!w+%B1S(+N1u92f%?>E?~(yt!=tKSz|Vm~-gFpJC3)24|-E!Zd~?
z+r0J;Ds#+R#prgfdAAlM&%E4&0wMY4%j6|4Fz>q$qYBNbLcm-zuOYuuk@*>N$rPK1
z$YFoo{NywEwMxwKcOh45{)!GYW#&g;q3wn_EgLGz&703bVTHNuG}<c7kH||@W&VM3
z1FOw}htO7IzWfGAy?LaW{*mLR`PUubX)v!KCrYEakGvmE=Cl&%Z8pD6?x|bm77Iv=
z`OgWowVIDoAmp}ruNs5bX0F#juHAgQ2BgD0`whT4&DNFR>@xpo1C(yFQUlUszR-ex
z-Z3Wz!I)li7*a8<3;WDlUI6P|Gm}zE`py5)EsX*5e{}x8XHJ(uV$iI67H#*<cWj|z
z$lN#$y~E}UG*OJ0v;GFlsCfl_+GNc97UeiRFelQvcHF%CB^Wbd4q{<oADKC{+nzH2
z>H{)uewuQ>tTX237!+sCe{wOTbLKy`qGW5i@falREaO?Iw6{Fo54{eSC+SCbwB)ov
zuam`@J`(S2Sth_(xL8h*f7I1dcnf;nEH5rcrMu<iFj$URhUpmZVF{wk9iEmjT4B8`
z`;#ExZMCG)BIRTGkGw^`mK@p{`&qWp?$_V)F-1fIEV~O(8EAQS3VM%Q9@2Gz6BaFb
z8iFkU+ClE5g+ck5rz{Wh02*u=83$&FWorvGg<9UHZyknNKEH-ixMc+$)gvs|Xd@PB
zvCh%+9Azn_*CN{TF`ZvdTQ*SI))~vDg#eAQyyJu+J!>hXO+>t<@=F+#VEH=>>d#q3
zT`=^#<yi{LBwBXZK<<L&4F)tNS^nWeJlUcrzwAZJbM!o=SVHK4mTC#4sqB&^*4hqh
z(k!0mA((DiP7lpx%d@|LHP`aTC`x&jqck(+TgHz-u)wm8q7H?Y#zRne&GKsi#EUKC
z<Tt!-u~LR{iDfsPAWAK@&R{9C9M}Vva?6oCpj237f1|C^axVv!RhG_`R-jc|me6le
zYhgR1vCguTCeM0{mmf+uEuQ~#Dp&&Od2F=&&<KGh%Y$UFG+SN|LDz0sqD!H^#nNs>
zCt5AL#n5}(vOF3+Y_lxd3YK<@%VMx}SROQDWI8SW<b>?9lvdIE*KPTY4g@`xrzpU8
z$MPrb^?EH!KL+WuWGVrA*WyaqTm6=#Cm}ds*+H|wJv<k%aM0qm4VCvT{!u6mS!~8Y
zhAsZ&u^zDqRzv-$CAkDPjago}2+jwV733Qjw`|5P$GULBV%EX7N0ys(Pj<@k8J#|-
zEsh;fKVxBZpmNqy@f=K>vuvTXecKfm*cb%675_(P2m2K_nn4^^1T90G<BA{XKM0&x
z#857X%Ze-()Vr?07hdsJteERW$$iCEirjdt$QcBR)pNy@7s2Ya;u&()d9QHn1CP%N
zn|A@~yW$%PJo&8%ryZF8iYHzI30M(F{^bAX=(^*wuDW<-<j5?ur7g`&+nM?7z4y+Q
zm6nyht}L5ckD`JD6xn;qQkH-SC{y;7AyX7&DT1Ja%Jlu7_~(4?J?DGQx%c^vd(S!d
zhd0CYJa9gYo5>LIWpph9z>ncVM+f~G|I#8nfZ=C>vOvb>>lk(r<Bb&{!Hi}q+X!Ji
zOILiTopJgH$b>PL+=El$jFLRGA{dU{Xq{r@(W)?#@p~W)Mlt>=2Z?4}mp~+jq5A*^
zV;K=87{zHuEv0JDFrr=tiDQ^T@Y}~TvMKYLz|egS4-*+9&!CmWm`fE4DU1(;AeqXr
zGf%+ba|}m>Jsr{*zb=K}=NZpalsKKSfdaFcjQ(%Yy1;P#2;?Foa~34C7^=B2pUnt=
z5zgc?!s*y|9-}`5O7j_i(UG`IjIvaWuz-=13Xvkl#}v6LW-OwT?-It|?GPztl-XYf
zu#6Ga2GMdxB<0O27_ZY4wUY58)hkyqtW*PC%^11|_b)R_e}ah`#_s?2JdEgY;OZDv
zGoZVkQA6*)D~uUE=xku@^uov*8LYPfXkrW>fJigr_*#gxFq-K~Xk|nW(*1Xp!Ssgi
zHb!9wEL~%8DMfajp`k0VosmH4iVnt(pV7L($nb&tos4hJ0^h}u*1^$khGi$_sfWP}
zfZbk3DSdeRCga)VAh#GxmZP(u5#Iqr1B|6qw{(XQI|;xb!}A%s|ArV37DDDOV;&Wv
z-e-LK5`e>ux86bL2qS3@S`Qer7Ql;#jG8C_M;X6U`fH5wj|0d!WBzowHo=&a0+C6^
zUb>qeGhST++&<<T`(bxKleG*jN2Vbh@B_?ucfyN<Opl{fh;xX!pYjY&%-3f_n=|tp
zN(~%lCYEC^jxhHOpmmhFw+^ji%)kCC_hJg^dUR!mP>lOH^Td73#R=x%JaoD-pQok7
zN#>)EV8Wd#+XdAg%u0XoJeh8k8Sr9mFrd?$IWG`C*?pM*($~O!naei<;m2Gmg2VpI
z*>_<#fcf)(HTlftTY(Q^X47skm}#7YA2x(Jyb8Eb=2x#mO&D|XI=l#H@+k@!$*jHy
zFQS+Sl7Wk6s+!P>Va9(3cr3F$6<(ZXKBYkC89Q^C6o`1{VmgA9z-)^{Zz6MUF1$!$
z7ShY@EOW)X=uBpIP=GXrxtn6Q=a@5B0+7aBM_bJE%#~D?m(ENX0Lfq;r&LoWvz!NV
zfw`RS>5I%BdW2>%lTM(O&0I(II5|vva03u|%;Z8imCyW=KCgC(IsIFZ0%rIH*ezsk
ztAmLm<~7>y7Biiv!;4a8(HGEN#ysK&k#Z)Fo<0>!)(cQt$!zt4i7MvrH-W2W&L9tK
znCs}*s%1V&B`kGJ=Uf2lnbr2|U|wM^Xauu?`C~kQjm&%W(WPdl!WpE6d5XR*(#kZ`
zBm63}s{(f0m`~-Qvz<Bc2@G~HC-+0!4QAO~%uFX!vK5kD%yg>a=w@cqUbct1n|5V4
znVvxa++tSHwzH4vb&mFbx0wsqKwCd^ej}V2U_PXT=pAMUtp$ddGp3>QE;Hg9{JzIr
z@HznZnc~C14>R}uh1Ll3(Glo=z|41smWRx6N*X?5=C4I-lo{g=pT?M<?gU_hne`sD
zOfq{t;qMgF*h=x2$IPUkU}7I@`4nXKvm$8i<H!nTL-Zi)Gc~jwVkNHy&xuv_Gp59u
z^?(8bhgk)iq5BBy>M3YD%6hf~23=V9UPH^3B^m+XILp=xWhYo6LFja2l}q67N!HVQ
zfpced;!?Lec(S;w!SrIi^D7YEtSQ<o`LO)n1My`wegLHbEDx$s3}kJm65Sxy?Ig5<
zS+8}X6~a1^3-3c&pUl8?g|RAV^Blq2Mr(mntiRVoB$D+_1UjQwYbik<&3chWAH%9>
z#USjltkT7>dxqt87&39J?rikNvsT5RGlA7b`};)J^%u}eVs!<Bcb2tuKMW?bYG}cm
z!fK@bR4VIZGlq7K75fFWoM-*=B)m^&?WE{Y2Fv;c29e47#1)bkSXbouwJx%{_CR%(
zoz>k7nH*L+?Za|eK9mZ{V=YRBntWD6Ak<u99b1f60jrtHe+yZCMIgm2?@Q<`VSP<Y
z`cl@cT#z!>SAT+6&Pt(mLIo?B36V<H3`dY^R=Fp5msv7e1=p}Xr)W$q%YGyey>+Y*
zN?|szX3{RUk@X^-vS?!cJ`9;=)`=$ITUdqvqO+CNMmxo;tV0JuuCb!efm~<Jqg6*c
z>zj7?+rb*p!Tb$Y4*h?hPL`Ylco(biE_gkx=~R}`%W|M4^-Y%C-jCnu7VG0N=<Z`R
zw!q+R)?b@J`dOp@r8imQw3@xc`ij!tgRB?|Jq)qFrdQQHmVllj_gUWA5E*9e+zT&8
zScfgp{eV?ZS*(YwH>e8h5$g%s<czT{J&$pYvt~br7Za?VTj~8b$qKMS_Y|w83Czc=
z)(`ND>|-zZ6U31nNgJ92?9VA?c#v(Q#nvHq6#cMH?922dc4lh_fIH0I@Hr%pvNf-R
zcZ_}EbvWa~&ZEL5SN5_1h#Y4(kHPzs>_8icJ6kx7g5)0TE&l_;lilb5hrQS#^qC27
z_R}Qe!*;HPhkopx8EE;lcS@i%fW7$=h8@U$<ymwFvFA`~BAC6l53LaPO!|~&7<+6!
zI>XuWooGd{H_e7?r`W5vz>7%sA*$|<Vw>Ek5ImawtQE`{_I*mp$Fd#iv2~j5`!(=q
z*nL!*AJ3MK!(alt<2rze?AdgzIEj6i_U>odo!?>dlG*7L0!U#?vtZ&Jdrc`w8rw=m
zkmuPsl%2tUtFb{#2HQ3P$&2iSxxm@8*foE^U^Y9{2Z$W@tG*z)>;T#l=dmN<qC-C0
z=!nh&wvcL-3fa<s&?;g#B*A<!+ZX|DCG5zJn5R;97%g+k*wY_EvVwij1{0O+Kq`5y
zV$b~@t!j3K5UMY;KYt3HHFh?S7XP(uKQ+9lV;4|nzMg%G;@el)%V<y9z~1x#?l-Y_
z(Sf99_M-P;zJ>iA#S>fEYk!8etL!~gZ_>uzMQ5Y0u~%&Zubtf=2+0oi_#KcN>_l3?
zb+W&H6RNw|&iN4OW!sZ1@bo4-A^^R&*s=l)rjI>9E8W{{83i)>*>VL$2H5i{E<VUk
zD?n?A-SaNUU3N|@bl+pYwGG<tv-kW1kzw}xD!@nB4r$Q&kiCIkIgi*|OQCF({ZlE1
zJ;p8z!Q_pzQ|uJInqbeW!LTRUJ>$?e#m=I9-D7rc1AzNDv!8+P{hY@f01t31RQGX^
zv-1^LI>d>jw4D=2vmF3u&SoknJj@w64Ur?9<rLUD#_9YFA}*Y$5GZry1kpn5I7d?q
za)P7VVuy@7=c7n8JvdpPq2<ZBJqX=i9G4g2lQ+lRgu(c5s-DAOd^rVuu;kDA>m@iE
z!0GP-E|60|b@M?S13j#RIYYJh4MI4rBWQ(kIJDdd=e$n~u?S8-#oSMEPScAvlH)ap
z)}K)v>q6k8IiBZXDTd=jYw=i)ODzzmIsf`X^bDtDHh6KIITR#J;4DrCAd&Mdov=yb
zII1Cema~x7C&`>ukuaaanNAh&shpqwg0eKuFB>r>=Q+o(fuwVGe+57WC*cI`|1voP
z^q9`#JVnuwY|aQhm~%LrXeX1)`Glfod7MGYcjt39{RpL(I4;XDrUK3y+V&Q5?nI%p
zm@`IamP$A|Vt81}nST;)mvPR22$6Em#7d~H<Xol*UKMAz7QAXsD;2NUYdG`iwO`A5
zLrFIP=LE%1>p7M5M7_dcd<N3M3F(FIM$WAWxYo>>LF<eb&hcvCS~({kfp?YjPYblQ
zagL7waE;?92JbrO5$(!4ILxP^`Ua<WA4EDi`SAdBadu3BblW*mO>nA*^Xvz3@fJr?
z2lx9pGlU?wIi*(t?B}dm3ZDiz?sVte;k;;q<RE8lKeP>TvZ(IrF6Zc%Aon?AJSZFH
zgwyJ5gcD1ltOuNy577CL<8={QMmZjj&>G`(YCy(0_CNa2JIP^C)_#g}_7qx=IXmd9
zs{6QJR6wzxyEz7G9JxV#XdU2sP{QI6S8xfEPFy7w?KpEQp8?=7H{mqgKEi#5-q1(6
z(~e>ij&bkM6Wo>SC4uB|Zf7KTC%D1%_IKkhv(rQSB)4}OnC@KD%TVLRefb}>ytz5+
zF;E|F(oVE|xjP@gpdZ(nLjL~Td-3QD;HDYT3gmuy9=ss#Hg~{7xSO5eMJV^&8)$`b
zpQVLKIQJ!bE=O>iaxv?XTvZNSi{hT$K=)rXH<1cNW4X`K6Ztgv%UQsm;XdUGzvH+J
zF-Sc3Q%apBaJ63mpUB<Hhtjj$6~94EGS`FdpA>F0tr}9f>*-EC$5lQH57W4-zC-7E
zZdx*~iwv&*8Nf5SVf3BL3*31P^datx+>hz&3t8M@CVI2ETn}i=<NnEmntbkpYTz$%
z3s<65z+FhUQz3VK21pTCNkPJ5?%TAMFX4U=1(8y&g8qSe8Tay!Amv=YTi{i2S6sl5
zD!H#w{X`YlClqs0&0T;%y4~S2*GB1t8t(M}&P;Jf=!{7ncYzs*dTx9e$QAB`Jg8~n
zR_?$knz^!bFyF%c<A0EB<u=4)@~(1!2#5JLZa-~Su5rJ50<G)ZSLjvM&fP&lvkvZy
zERY-A_h$m$$sOjvti6ldbR4?7xo0Vu+ry2?#F%=yjZ`3TlY4p_rsNiPQx<@I+!#73
zeVf~$1HPZzNw>owSMff)7~=jMjMiQ5T}r0k<2p3L?tN}7h5U!PlBKXP!d><ubUxtr
z{sx^7xplPQd}QbTZ!hqp-0vtaJ;oi%f*0f5uc@?Tg6on3ZIj$Q9Ym+NZM)HW%$?W{
zHT!tw??UN*-kNUU9C@s}XdU2n&?eT2_Z6*noO%9l!{5WalOn*6@O+L!^-*4&0OS~N
zBQ4imc=jV?(3Lm46684Ve+yya1aBi<o^HICM$zfcYaWF&9=zu%OYF&eWe`9w-u!Q1
z$(z?quQMOs^kX2typ<Gd^y9hEYR8}FNwMz$-a~Kj0(tEeunFcBQC(>Wulgn|gz~1@
zDTo!uyKoM`aNZ88Y>D9QuR!N1UR)6DM)IoGKs1V1O1Y<K-apOY#qexjgPi7tuY(t7
zcnfJk6~`N|fNSwQy$+TVcy&*JB=UF^s!ZbjNUQ#{yq73FoXpGaMrR5S|G^Bssl05u
zyw39$(Bd+k7djs@8N7t=;Y=p)G2QnUc)RF=xXAl_Iy$p>s-NIYHgD=}kQ^S8ZFpDk
zG%Voqc+X5i@)GaWU*L8DFPpw9RmeL%0$dUAD;JEjm>1p!KnbsC0sY6%QeMN)7-$*K
zlj>T_c_u2_so>3ugG?o_^}o#nZ~uJ^?K1DlE$FP_U3(Qi)$)EV1+I?A;KE=%&q|+L
zxx(vCguw=08f8Bld3T$jvxyh>Ekv4m-_d@im6uWla+Q~Oo$~K(JP}=i*Ldsl0ldyj
zqf+j6-bOkg-od-Af#?n1EZS0c^48o%XBY3IA^^I18z?k;lQ*7^G2P<*LQDES9*eeP
zw|SG4c<<*a=79|G#&5&lJG>d&fg9wljR9bYC!+wB`YtbFA#~s4eL(BiVczc7ATz@2
ztb)T2c-wg}@sKwy5lSENY?J^W<(cFlW4!KzaCDs4Kta(7Ub#o#(ChZX@6qST-}NTY
z2l!7@pywceGX)0^@plG*IPtS8q0*WEK2_oz<_FS@9N{;83MEJRw^JbE!Y>k`)0IE_
z609EQ|B`{u6Z}tN0C3|^t_L~EKS;N<J6})F9uI!je;Ww?h+PDP7vF*6fZqI*l+f|x
z^XW5R{`{fo7+3)RJ4yrx@{=i35X7INL_;t?Zw}lJ;XBcHRYLhmu`m(FpF<CpaDL=U
z%u576aTt=3{2#BP6~#}tLNc1KDgiEr|It^l5X(Q7WC!pxKZ>GcXZX51a3+p_VjPHg
ze$aZ51b*i$04DOEpxnS&etQjC$^7m~;8XbT(_1W+|FjS6p5y;b6(ec<SLnpzdA{)}
zm`~>?@-XZS{u|LyoymWN3STeqFSbJ@iyxq*w@EhtKpZUP@Jl;Da`~5O*_+3g()R@O
z`7f=(FLH^WP!AIY{6{Vzh5X)auv^4`suDgG^H(vUyNvHo%j|OgYC4o(!5?}I4=ec>
z=svIFGZ`>g&F|a_XD;*mX=z!*k4B}F-JzDh{cqsw_%rEsU(dfw1<DQl0Y~5)`R7)E
z*TjE^KGV?5&!P863xD2qh_v!A`h#5M@1`2_HvanOq5B%Y{x1No^N-S#yPZET6(TqI
ztg9fMd~f>vO&5P>8F=0Npwqz3?crzA`k<FzGJxKj{EZ$b@4sZ<{TPjY{=goPJN)eT
zVSSLl;d7`S;(tybG`Y(kDuXZg_z8B9`}}X#L&-4T?>w9s;cw}H<OBYy^?*O*cO3xW
z5r5a`us6={ISAeapV<MICix@pL1c>mR69f-^JVm@h<$=9_HSTtzu>7mU^)tVqCpM_
z>i-7*px_60;13DDw_*;R1<z2v?y%sSQ~-|%6tsmsDv13TlE(yPi{XrmAf58Kt^$Xj
zp!2xk`xTgj6N17J@Z1EfN~k_5n56*m5QOAF#8Y53QjXV4AWs3%Tkw7ndVK^5DwyyU
z%%;;Teu8(&puZsL41fWGPi{bIpdgUGNDw4Y24OBj1kqH;5Gt5X5v(x5Ssq&9f+1Qp
zMhIN%VBwVD{b*Q-6tq(QC`xb(PdA5Xf$k!elg0>M7{Uz23J%lDC{CbU1iSG9Ep6Zv
z1dP8h&_scMH@rv^%%&RTvw|GjjwcH~Z2~SuaEG4ese-f^w9X0im(fZS{8Rxzx*%=?
z;2DCKia|03yJ+csLGX$I@QZ@ZuW65wB`}o0ZnoepKA1TIKMEh_3TC~I>CO{;N|C;N
zLBS)46bOz|E}&2_%Lg773Cz1diUo#nSSk?=(hI#*5PuQyGQo&9;N^mm4ImYQ-@b=r
zrQr6f7*dtMrx4~Z3p6v~uf0YvoegHKAcfKnb%GvBFw_fPpbh*Lfm8(2AlO1j_8J9y
z9ih8P@P$8G&4NFh;Y^F*PZ<Dhg3)1kcunx)>mb(!+qOXW4S}9c;dcrSFT&`%1kHbf
z^b54Eus0w`r)|?6yWn3s@-!%jrWpB<pwR$wS8$dd3HJocV_@RGplvNghhYgL91-l?
zk5N1jxc`RML&5PEA@WGzPD2|NOt(UEOpvkz@NvO|W9Xa^cu;}lq+on808@fLzXEwI
zD5J#hKB4`^EkNuS3U@%pQMj!TLpva}{fy3o!loB7-a|qe<=dQu*C>AAEDZb^1`i8a
zR5N-+7(^HOQDG>h&yERG7h~8i!Xe76y9!5WpvQ%NRL^iic$FS#Zo*$FIeSvr9*$0T
zq2BI+riXB;1x!yNgK7-DgfX;%_ZGTYF!?^h_-Lr{70ywk(@(gB-o5@pCjHC-!aYv_
z7buidW-mxMN)N4I;btmW3=uA(cXp^yNjvs1;pg<DhYNqNht3FL8zpc~2~ErCnGz}d
z%OChC;i~T-8ZB(R51ANY(tJ!wtnlskK~4+rQmFiluzU|h;)Gpp7;n7Lp&2uiAY4L`
zx<sMuGe{;0b#w`w6}l{i!DL|`6Ot*y9rS;fQiVgl@ade;p$H;r!n_i?|IQ1=N$5=%
zF3E=O4516H;4_6EZvx_iaN0I>W(&Pm!qFVzd$di>6$VYfnLObms!qrk-lcO)mxNnn
z;1vkpr`nD}p)4D`BH@}(;8U?sLTkDb;jsZ2Dit<TL0p+|FNzK94&}mmw7jkm+9)_)
zDg3P!cB_OJwgOQttfF=5W#Kxi;HwedqWiB_sOO@yPPpb2bk_^BDfMzi_~&|f(IC`K
zK})01zZacN!V|IRY!<4;0JI1{y9zC>!U)PDUls1BGc5Ktp~M2E*MyN&L494g=?mc7
zg@Pt{(IH&Z4ih(ow<uEBDLhD_wl3jwX94IIrqkuoBYY?XuUEL3Y6or#@B9EQw}i!1
zW6>ux7Gj{cg*7)|uwOWxcI*Sft@O#GJ3?=|8wc&e?UZ>M60SH8nY+UCw1mDV^u34H
zePPNfAclq30*H(VU9Z6I1L6E%;o(D}Z!JU~2_Jq6gQLQ2G{P~VkrvD2!sMqh><QuZ
zIEYLNXVZgmN+_qIwa3E7m!NZ>=*JKM_KWOWTp;5pN_!hJ2SmMJfO$|9wGc`Vi3%tx
z;3S$&HBQc=nt$NhVbR*>(K;d;paSQkqSbn|j)~?eL0m*bR2AVWiZ}{K-9)F_VdA9d
z&Nw>VMN48aUJp?;6_I#~jz0&0muR`2LNeZ>MJ|x>5$Rt=%U3k(zw!~$AB|}Fi=wHl
zAwaZ&R&{}*|54#@kf@gK`(Tld@=qZmZ$G#lD(a>6TbSt48yJ1KXj40Q5hA@FlBYy}
zBtRrm<gx@JQKDzogG7sF&#>bfh!LewRYk05-j5JHEfPEj_s@uwYVhJjuTr5&yl5%q
z7ZXH78E7SnmKlIg5{ZT(c~<oKOz2J)y++Hx6wwjN2B(T<FM=26L_g4`CQW3dBY)>b
z|Bz4VqA7a1XNZ3FqZoIl=+Eh3UJxx^4HFkdK@^7168(?f!r7u0il66*3h1eqFDeLu
z(o3S6LCi&gXqpN$Qz(k0QqUsND?dVau_!Vck|m<$djT&MWnTciOjJVOE+`lMMP)@5
zqWOD4Dn-+gd9^!Ki6$E{rPZQO^ys}Tnmz;CYD9f=fv*?crx(x_Q5<E58bme*9BmZ!
zeF1Gvq6ZXrZx;1YP@zS%SPN%bMZ@%Hxhi5y!D|!Er4;@(kpnFXuZy0*pF_K7#g`E2
z5IwmCj@oaC@J&P9T%wJ1{;^9mm%>ZkqT9bfrbm=L1kx*-NoBb=MQc6*@0MsURZ8}W
z^fO@hwkU$qll`JUw15wYHar1G?}$ua!tS7`&jq|8Q9Bp7yQ0BF@a~BUuS4>_NRj|D
zY!~gJwE2iAmA)wXK=dR9xgLtXqL9iXQ5XlUQBgh@YQ{tpUHE;+MK3-LG9jus2BniC
zK@J8wC7Nl2$YW8N3tZbLj{Xh0_ls|JLef!OH6OEfK>Px&&JK#p=xumNyn?P0C$W9z
z3t&2nH&H_7u=taWFnC1#6D3rRiZ}iaFOG>n-3AX`#2bo$cNO#8F|_02YqUH%A?8u3
zlbd)86)K+;hh~B2F8+sdaUS9T8I*a7Z#)Utyu|ts!1ETj9zmy%_&R+O)mOaVPHOzb
zYZ_q5Uo6@V(ExD|rN{!s*S?1rLE>J@TL+7;(J`G6@kT0F3l%epK*Gd7(knJxJn#`b
zj1bp;3wV^6MGu2$u@_}RV#NM*1H_6)L!k4t_~S3oc}5&C24~{L;<FTEix+=Sb-W2;
zRSskl#fvVYGfDiV39Yl@t8YVTvUpMpH7VlvXa|xi-s%E1=fu~_&`J|$grap`Je?}=
z(#2OP-k%{Ze+qz1v1~Q8ToB)+9NtB70M+ehiDRPCnJspEj%s{!#GxECbH%SxyfRO`
z^#BH%FYfUKxg@Um6}k(=l|Il`DBiXQt`&)Y`5RMGEcRUmUWwR=qD7_Rnzb-dCSLh6
zl$DD`RAO8q{_Z?lmE!aPsIC%w(KJ_!>(Zd?ve+GKV!K0)_#(v(YsKsQF_=2>7nHEB
z7vFmmmad3fX))a-wif{3ES?($(js<qhHI^2k4@lR6%Td7Qk&TOES$L}Zl=>W*Tq}t
zh1)LPNrmVgVn+(`-4M6`0g+Cz%NpRi#9s7<wRelZrxS5K;=eycZ?9O(1-U5>83nl|
zHXDKH6Hkqybz6Kb6WaR4hbh!OAZF6Hj_!z^q5&Ti-?|Lmkk~>isJr6oSK<9V@xnBS
z+!uROrQ)!78pT3J#NShL_JLS71Lhyv#lBR5^az(1CUI2U;Q_>$*z^vV<Kp9#8ki8b
zPy%RDY$*kBO1$w0XnQQ)_awCKllXJN+b;>BbdsY)Ok0ox62lGf4oaR{1!adMx9M=b
zljK86K{`tgF9P7O<hd0vdqiT7_yaOWCCN`>hK@;|rI(D0WZ8Sr<|^rb5o(T0*eU=|
zNDNoe=_a{+6<(Z_SQ(IXmvGWSJS3;+g7B2|dx7UA(JDZ^CD!e*<ReL^gq5%4t<BKl
zCt344boxu|^t20*OxP(h6DYZM8ES$g>-)eAmi$N+ULlfo^8gH$1fPP3VUi_1XoXAC
zDYqOU$vlbHDapaV0f?03Q%y*eB!j~K(UO<lFqYGjL5h)`k<_n2D^4;+b!PFB5313b
zAaPZ|e4+#&n+HvjILw67vyvY-0iP^c$puM~{1gFTs$@A83!Rf}dIBU(lK(GUJ1<FI
z1-t1I<B#wnLvrH>=+2a6{{<}<B!}n{xG4FRPS9pap38!TY{@E$7v@M(DQ=Q0VYR_R
zo@93peQYRSGD(Y<OA^T|Fi{}M*Z`%45*1BJk>sCCuv9D=eIKMm(!zj9sbuR}0LmmE
z=-^DbWZgm-tdN9rFbS2Cuu7PylB}Q=RJDY06h2*+_`d^XHInb>h<>f)<vAdAl9dtk
z{;QX$s3_}-<l~KyX^?o(%eYbUJzXYElA#`mHcPh9BH*gzRV6yxB-~w4dQCD!B`wz_
z*C?sgE;;=YIy)o{bU5&aBz73ibV|BQ;9-~K{2$QLEjdh^$sWlOT5I)6Zm)$Q`%TG9
zhvDfh$tF7I&?lLH1(t40R<(lkOEw$^a6r;<9op_l?1?ZjD6xG8z>wtEPvGxe$+dBq
zxF=~_32pZ!9?M{USYo7#-4V$Tv<7(~IYdF%hmsZwkvx)kHlZ~t`ThiWV|K~RU(h=)
zk@ul@LUO7KE>24PseE!u^7aVqK9(#v0fYObVK+hcOWS?|ag?s7jrjp-(7SN^pmaaQ
z6c0&fP%y?xdY}YeI7^qTf)|IS`SnnCM4C#~yho*neud6s(xM{(9GBYrD3f_Y>bx6X
zxJly@fj=po)`3oUsp~Uv#zX2IhfYta7kya4OIk%GyWUd6Ptffno%##9eWhpUBK4D=
ztc3}G=|vi7fOI9jg#)EBT5JVLTffJ6L!~cMtRhT$h4xC}Qdc{r9U`O+6tX@g)lsk_
zQtB5BrBTw>edvsqh8+Wmk<JQ-wpi)c^!h$6J<$W7&Pexffn=PNK_p)KmnTFLq-z~8
z`a~(~Cn!sj{>Z^}ot4gd4qhZne^~%riuAiNv{I#A|K*s@NpJlFrD@WPQyAKLtel`N
zUHbebXv>hM-#{x<I;R7`3(_5Q#O<PVD=q1>q&5~zWJ@z^A(A6)aRbSfZu%cY@}v{a
zAo<eVFyJmppQPtaf%MODjJ{AR8i$8P(p??&vDsqjvLQ4}q+dS<DV3i29ZJij3phZO
zOMj*PRE6{ioj0hIZm$8aN_yyJ_**R<pvs3DX-f%A)JpF^1yU!~$iS<Yo}|L1D^kfz
z5NVLQYcSqM=^e_sG)dVs&SvRyL~3xxO!@^)aI5qg%7$H)I#HyvP5LeYuSxx=?&G@D
zG#!4oOIK1hxl{V%d%$-|i%&zcTYB#`boNN69R$2r`n@+iyeXB@L-&^S6?%yDNy}*M
zb6dL46R!13XMTan8<4JF3=#VssVAM38<dvPao{28JSu;_D?ND~YVJwh=|a3Ob(;<~
z!_rAMI!C0lmH_xbdWQbL)kA5y1&%(F3dTT2rOTFrHzsAg0k_Acsb(mfkft61nUu;Z
zU}#F3>J9H7OXnPb&V6=S4VCxom))T(jic;Giew*<v8I4HD04cC&O@?uuRy7jY$kpF
z*I73A9q2wRdw2sPM`V{NL2y(y^ado4$*z706E3o~6hv~By-)Rc$7LEipL9Yto3hYu
zvJYPa;G}FD#kbsL_S(}Jp@*zK9K=($GaJN9)<!!5Z`lW#7_X14H3CEPm3{mx%=^i{
zn1D8aSsUdw17vSdUL;WFa0<L2*)}@C6)cOT;=&Nw4$7y7%C0Yi!7$lI3hRZ-O6wsR
zAxore#VOe}dp`_D%68JBoG4kk5+qtCpl=k$$hubp5i6TPoBq?XLN?q#BP*j_dz>uW
z7fR!0E+ZI4f-Eittwh<`P>>`UD+#*K%1+Y9o|9$ADTb9I>!qA$s*Fwd`#D+n6KJK$
zB0r)W(|Oq^xghDXs$MWNWLzpI%#{7w21^%YJW6w1lm$@Ta+WN9H6*iTS})*pWGgAu
zpDSDC2+2Izwcp`=zU&jaRtsgFu5hME_Phd}#j>aN0#G9J)dNr}3-AK3O!oU_iprPE
zoc4oRA^W`r%u3n%KrpLhu0^m^Eerh{BfKmNp?zG9Z2S-`)yj5NgVf2wJb|m1Ww(G_
zk@e&O&>%~`3-gUKw|D@WWOaAocC+ktE2g<c_U%LPT4j4b1N^G24!d>am}Jka1@oG$
zkJ293WwY`DY?mFSL{5k7hZmsqhAfu$Q=PK;D<Ih=+dT*myJb()lD<b)OSeO>O#VK+
zxG8%$0g+p>{q7LylRZ@jowsG~(IEY@h5y}nG9UV2#vR#uDp#=&%ATjl*pTelbI^8I
z_A6aU_heh?C39akmtOS4vXLjDZA4bF5v>QZFR2{&p-e}cvq!RNKVpQVGS5l)J0=qk
zLD{%$kYeT&GA`}^CS_acDKI5l_6l@9mX-2=+b3T`IiLM@`E9z`9OW<3g?K>z1AW%-
zp!~=_v<}JrYydjRKcFqKv)t=XOu}LLK6>pRk=yB8T1Vvt)#yAXuc!5ii~Q6JfV;}K
zQlk2}yuS@1C*=QpiB329z$Vx|DgT@@#qRRp1t1=B`_2h?>M3`c52m;L9^D;2^3`-A
z!&m+b-CTb1jxV6wU+#VpBtTyC9y$Z%ANoLdko+K>$PJcP(ThGr&ZiohP`NM)tuT4x
zn;_xx7ZyV#LOw!eTc_lwKZS)z`6D{45hV|>Qz2ipyqVUoG4e<`W-nIGlVI4V<#*oz
z?~HuJ4{GA%2XY}2FCV1DTY`N4J%}XAzkL~MlH{?JzB?-~pr=o=e0e)~De^=H?54`s
z{sDvM<OScMl_qb!0N#1|^YoBUmp`%H4rYe@o3{YWl)F*A*adm;zYx7BUrr{n<Q23J
zL#Fm!h~&t%$I;4_FQ$R!$qT7sDqmjG0CGt_pU!m@$T!n+zff+afKQQpB}M0p<pK0S
zE|F(a)VNHZJOB&j@@@NQ|5qU&>qc*-Tv-o9mHY|X^Hj@a88CQR-rbJhsYaf85v^Le
z_)WCx<W=;;)XSTeVDwkyFP?^@4f6GL={3sd(@UaBE}DdvW_bne&s*d*v}<maKl?iX
zSLM(8!%&-CprQNkn*8IpG3@JdK@_}bmoKNMUWYt-8noSzf879Jr+mXSkS=*6Wp%sd
zKhvJ2M}C1)@xAgd>FCu>`Q8S2aZApjN~u2i5XIGQ%m1PjRKNV&Dv$yBzZ40-Bafor
zbx<x`0Sopa`47i2w7c@`k1#{`<neT^-<Pi|hEKzC$5lX#$ZO~;3J>JkFxY)4cbbIc
zBl-8sz#Ek>sYK_Pd<!k!$K_+Rc$kn+ehV)q<^Sx4<dl3tHbfrFyC}A~PqCX`Rr?hS
z>6FJoyW%RHw>_lz#SaFZ6sg-loE1fMQyx}4K{>M{iXMtcA62YQfWyZWLv+5vMX}r$
zBCd)@RF!*Nv6q5oClnsE&vsLE&>rBVqSYHB?us2-F?k+}Mq1T*Dt?&>N4*q3(A&&g
zVPEeB86Slu0Zd;-A#I)f6sxNs<FAOM>e>KBW*JDJ!jV?NL5c+%zzbGvpe0a<!g&b1
zP=yO+*TNLZv{DUMoctZiA{6_VVlGZ8G!7t<ieo)+G)l3Jsu-gci#`B6MzO&DJ$#E*
zTo!_yRxG6wk28wYqp*~qIKL2T5*3~A0+FQH_cl7uDh#AFS@Aq=3{n)ECm@ol=uyD!
zbBZ~?0iLGFj{`Zc5YSbYu4oO1PZ^3DdiZ53-q``%1;r<ygIrYXI%h|3mZFEMxUv<Y
z<LJ#%oI8XO<|_8hM`xa*i>g=h6-FupzNGj(4k87LM`tl>g^K<d%zBaHAKDETD}t!T
zqC^q9AFWbF-dDhtDSoG8Fy)G+bca_cf^-n6R6Iu)OO@inO4|QbD`x%|<X24p70epN
zHWv)0R?!>=_v;jQBhgu}Sg{gHuP7?$#C3z>m5;!~nJ|jRG$~x^<<zWLR)m>pQP?O+
z)~eV{QNF8+pRPfqO|gj_y{35bIFwyieCZ58yP^bHUX4SC;%EkBZYU<q=<QT|O#8ns
z#lKYY*R8NpPV%PW<T)t4r8sZIboD6&@lbPHA#nxiS8Uq`GN4%QlQQ?ockC@yz};7T
zw;1M!6@R3IH=?M$4f78a%c<D)q2f4|qCHaV`V%@w6}c2`9#a(G0U1}kzyfbV@$(62
znN++=Kgg6~<Rr{KR{X*Me4p}-Dv0b?{y774=%{=^(|kawdma;WP}yLQ0Pv9VO`3Hl
z<xVPHbykXMq5H7XO6!v&%5~2Ge^j}XN-~crk9wfxqI}54s9lv6b!Z(|N@<~dLb;ii
zPQJ>GUa;$@Trv&BUs*(DE&<Bjv|kKV{!VM~ASH+LGr`L7k13uWqTGcin?tBl{Ucgo
z%2ulU3s<(DfM|qr4P_BeDX(<^5vh!$1zePJ-S^-{D_>8<C}NcUR8t(QOr;X1)5@+Z
zaOR9M-wqO|G;9YTUimi#XcLqv&%?t+<-JuPNy^AS=*-4hWx-EqCM%^>O_id&PK$?B
z<uR&cIH%l5wQFh0iFY7!UMbuIlCHc@vEU5l{g3D#QMNn5#090_37EL3oJluamQw!>
z%x5d#eG4PYQJz1B&RpeFPh)_2$~g%D6evBupm;)|@~kg<i<A;tJr^sJw?b)&vTHl=
zrOM5F!7EcPQ9@0*^51X4t59B{wPlskk<NryE2}8_b6J^0rvPe{UzdQ?Djic`qE0#Z
z0IhnZ=^@5)MR|;h02-7%6kBOj`mV%S>`lrRdQ&zlKcVG*i*gU;?OT-|X&ClZ<&NLL
zyRMAc241^zh8pCCGB6kTPUWlghVD{+J`9m=<>(+tk8+s}{`M+&U4WLG%5Nw<eM>n>
z(S<%`F4eo-R=S*lYyHX>cEI}qyYg57WbP<SskCKK8QKh`L&{xx_;y#hh0aReQw~sq
z^uE$-0b0Y#20D{7qC9^I<bm?dB#?*7wU1%`kuse2I-^QHMQ_KHKXd^wuKX$=IwzDh
z6zZ5%E}<_2O(~Okn6<}B`_eWv_p98Kz;slt3Wn$bm573UPO5dG;5n<ji=q3lYA3Cw
zkEnJ~z~-pxYYK=TQ*k~4Ij-WC0dPXqG6y1Vs@U%!;-NZ-dI1Md)i~7>c&RKBw7gZP
z=_mA2J*tPKuj)<vE0|J0)&J;(j=$=Eba@4+5~yS(P^F;!L6B<WOyGl6{?!l(QN2pB
zuTa&~?r4Rn2I-CoR~;UKWQ1z|GQdx%V!J>hRWm9v!YI{TI!PF<63`1eMs;2cWwEN)
zcY$|Wl^<>gJ)=7JUzS)U{2AKfRS&3oCPCE{4c8J?FTVk2l2kv@wSHFBKzC}gYQq3b
zq^RcqgjT9*&v$5@Q;pt&?le_k1azKPy;=!J(^X=M9%ZOBdQ4EJDuCkf7gSHTK<7nO
z+B5XeqjFR$DY}@edX56xc`7m0V&<!2SA$$qo%|HK3sj#ap;f5jW<Y6?>RuQeEmqxW
z0x40Mav)Nw`r$Mzm8pcZ%qUmgp;%vq%K0itr7D&FyFrzz>pbjMtCSSFzN~V6kE)Dn
zRL`q0v|80Hib~e0k}g7Ny=w7an6E3UrC|UzsHTF^YF5QiO=FAdPb%YTRb8Ux%~e%a
z4oI8o(Nln5Q@!&sM6Ro*)xbo%>UBDG(4qR}AqLo`diF_p*sVH7N0xh3HOC-gA5>jf
z1l>a_HwuT`RYgt%epuE15oAVG-_gVVfvTF$-8@vi&;(15RC^duGpf?gMQcKJm0}!|
zs>gFcrc_sHX#3R~I=tYhzVs5b98hQd3G)ZlvSE-z>P3`tc2fUI9=h4p`xipZN%d2?
zxR2b`+NCh>p?)I`etW7rvS7(eT|((>Z*@D>sQ9S=_X>c%>ghDIe(K^`kn~r75CmR;
zI*4|*f$AvQ?gpv(6hjVHuc4_7RnMU7B24X7jNc$!J)JVR5o-JIRIYGJeWe@CNVN++
zZ(`I*9stIwpUVR8v^t0b-Wl~GI*J>oZlrmNSN}T?mJ-x^iZG@`bw?RQlGM$q0Gw6d
zmjIru9t#04Mcp+QtyJ}#4<T|+T}$D_G<Ebp;GI|J+1ue%y881KuzNu*6hSmwy`>(l
z9QFBiAh~Mg6eclGy^%gQk+1%c0=$>h?z=Dv1?o4c{J&5g`!SRjsaqZZUaYR8P;!ZS
z;Ym1Js&=Ddi8A%)w6rZ(f4Cb{S)m@JEp(;&^dX8TRH^;Ggzjo}Dpk~7R)1wet47^j
z4_>XBM`_P1>eMihHuW`HU|&<GO~>f3tG^UMTf5q_7enh%r(6X5hI(fwT3zZ{-+|Yy
zKHLJy9<?)h*sJzqLiJ5`*#{uE)QiRR{_9i!Ov{bi>av4C45*tZ4{%3qIRb|V)l;r$
z4XJ+$MeDA*JsIZjsh^}&_kDF$Ig}2ofBpxqji_zM(R!dhNXzYqYRgW{%&7V;I?Fny
z4!RF5<LZDv!JAMoq=LLj^%i{210U~KAKC-mkJWX5gY47z{SD@R%`u8jIBHHBfIpyN
z`~l!WP36DnJft~r6J9uJnr}g=v*yyT@cyu7H(g~%H23JU$452Al%Y7TDf<jwxM@a4
zp!%eyd<F*SuBoCUsUDijedx4%YFsJY?4@~=il==wk6JMpKh1p#s`zW(VncU;hWjpf
zff~OH00wEk7J&q7*c96g(X4C4uN|tXTmmiOn#UBGjnHf#fXFFLG&1H6ks8$+z@s!i
z@4|evX4M4Tj?oNkhlN<X=H*DJIjuRg8*0vI&b<XhoTmRtsEOA!m_QOW%P32nq`BgX
z)>+L#8`LCgZqWgu6wM@Uht6r9pc^ku^I|Q$IIl@chq83dnRJL`Xy#JLE>p9(8?6f(
z4cW`m#8DzCTVv0>ifPNyXvOHw)vR6)-|{pstb}j*n%`+<eo6DM047Q_1N5#a)p*dE
znljBhl=UpvtkOewh30d5_*H41rI16lW@86<mo>NOIC7mPgAaJU<{PROx}sS|-@9wj
zc+eiJQB!O$0<c-rOrg#e%|0(MTQ%=6pyrxJ|2BBnH8Ca(rd_k>G3<6|LMd2xLsOLt
zK&Qs-bpX0FW4j^Qqw(>EWUpr1^DuZ*^Hc+Pw=|+_@S;z1ix%y-H4iU>^lOZCK@4b;
zchdcLM-xPusJoh18=>@`CZGap?rVIMP&2Gqv<kXMG^@M7d!RW-o190QXv%JlYUWeb
z!kFgw#Sj_S*d^$k(EPdqx*u!aEr8@c?da<u`?bos=ycR33gP_$t(BhH2eq@k=${8W
zX<wWN8E38DALOw1<Q<3}(SAuGi=*0isAkGl>v9{89@l14apeiEg9IMBY0VcPa#HI|
zSt@sJOfTRb+D1y5d1`s}5b@DApFyXuc7P%!e%kHy+xu((jzwpHcGFzC|AMqBCx8gn
zewGUoqW!@SBuv{v;h%8rAXRclXxk6t=Q^c*cRkEUYWFrkO_X-oBJg6gyXZtwthV7P
z7(A_w{Q{k5v@_`7Nu2ftEO8y;wX7Z(Ow?|92VNv;e<WpRwFR`Ov?ps96=H-b+V)Fm
zrfEOhj9EXg{m}w7>00g*OmK#F28m>9S5naIf_69Ay{MfP0uQsaL#ZIy+9zY-c8)gm
z7I?YZBM;$Bo>oec=zQ%WT6J8~?x8aA0_~k-7%J2{eGXpHDlOXv6UEwj6ihAE?k<Gi
zW!gsiMa#8Md<;)3w8IpFtJH?MK%`2$EF8RQZ7!wZE^D8o`mY*o${4iNYPIn&U#H#b
z<M#HGFWIZw(b=ed^)KL>wEa?;Z`L+Ek5-E|@_pc1wJB6YdQ}@j<sfa^r>I)?y0(j+
z5bfI81sHCJcE^11ZfJ8UYtpHGL~o-m?XemRw_Cel4R}4;Hi{MWYTx|=@S9rwL#V!`
zowC#0p-<~V35VO-tY9GewNt$q%Ye4744rqhztAE7L2csOAVb<KtD)wec3T&4_qAK-
ztum~AP6ysY?PJ<pJ<_fz0vXj##(|7!8|bYvu9eaActRWK4%L%d&JW;CX|G@K319f+
zJo`B_dL4CtheGCnPD}UJK^<d1=J1ei&rEbW={%|E!C4m>2ZM)o$Buz_M5p@}{vOpC
zM=<PTy53>nTy&ilv|M#NE&_L4m(>l`Cv?xy=EzO=`zP@Jq)tg8b9Y@P1z$aM^XvwA
z<Ei^N2A+E9ihI!V)+JnlHXmK)N5K2)PSS}4KV1*fyAJ-kFD?Tgp!=-^fI!_cHM|JY
zJ$?eZgLUWrhDeCcp&x)y-Q{~A5xQm}yg#M;;(e%&)Fsks$|&9Bw`fJ{eBYy8XpC-s
zCR~iwt)U<Nv~I_Am_MUia~-XCT|Ygw5_FHFKoWI(z5_l*$M%5TRNWJs;mkQ*BIPO5
zbdT=Ci}SkDB`}z-`?4Io3|%?x>oawdf1&JxPMQXL7j@g|g2>X<v#DS+TleQ$c$%ZT
zyc^71-OK<m^K^~$^vKuwNH9^Cbp1cWZh@}(V~|1}uLvfJblV6}th+h|K#6VzT{ES+
z@FO5)y1sr$mg^konyb)Fra+`p_jM%zRl2tl;99kAF<y8$6sA)cFl{xu(NQ33b?erm
zRj1o<A3oLVo~(o4S9F=Q8g0;x*+Ck0LA2R#(ygwArDk0?1KL`2Y(KPGb)0R$UDYL+
zFzhy6JYB%obXcU|#?f{Az>9XBZ6$aey8KU}#ePHg4HX%8>ZVZ<YL{*|9mnd{l|Bub
z9v!l1xN~%MHgw+9J&}&qEnSQo9PQI>rKr(u-PT2r?AJ}#L(72fDKCuoj;@Q|1A{v6
zH(+o`cVPgnyE;|{TK9BPda2ykG3gaGY}eIy!r>9!5h_l8pnHurXAgBJXx})dn|BGV
zaorTX{3mqLv{jqbwR^+Fl&+6zVjk-byauKF^wSQbbHDyUJCr)=i(Z9?2lNe8D05K1
zg`P-<^uG-P?xdgf1Kf7jckF}YVZFU#6un3EyXe9=s?Vmh<1zhr^+34jpOr$ltNuB<
zT8`^i{{+Md{p1>mxalLR;NeOA%D-XPUH>;dojvpkJ7LgMpBaG>dg)J7n$%mro8BKj
z`q^};`|4*?9hIM+LDgLT`kVIGAQPm2k!oT>^}a0hhUvw$d=1yX91q<QdVhL+oYH%*
zg-?<CADuy>^bz#9i`JW{vL;6FOedvd^_MAud|GeX4lQT&^%D3Sr%$5WH(uW!3tocW
z!2ymY>ZgtYo}~Yy>?N2utIr&TXtI9EO30+>y?sPW@OU=Ogs12A3!LCgy55m$6*KgS
zO|X=yAO9Ae7xa^C;4bRZn&Cy3{!loSX6p;z04_(*Ek|drKAd9CdHTK=(3!7y^njL2
z`s!lv3iKSR#wyfrrtor+zMUTA#rg@VEh*9S>~u=ER6lDO@MZeETX3yhzk`ZyEA*){
z$W-b%I92ITrT>+-HP!l0g&>#pd(3dHM&Cp0l3G3M7Xa$?z8Yw$*I#%QTCV7EPzHCC
zK9QF2jrwjLa7}u}li)S$AJE<3qF=azQYo$a<_%!B>yxHn>4siPVWUoc<N@%y^f7ef
zbn8cHkJY1J`vgq%>c66;-c5ZweE{{Ao;?a)pZ>Z4l0$ky9JJii8|hNNum6x@-NX7D
zlp=emZ#j%1J<?}VV0TpCwv<wtWBNbI{J36ehs=cj$N*ZC`esjzX-Xfv8sxFwjh@o`
z4AbSn?>8jV_TJIZKmmvYhGJSD95lS!i7_2AJe>?LoDAzPgE$)+sNm$VVGD&Jj~H(L
z4w0jV10TZeV}@}Y>9#w#7<5W_<7x<}+`@6gKUBVQ!oZ|55;wyodb6K2{CO3`-EfL7
z2oFORC3!s!qAGNH8Pa#aLvKSeWsrOf<08O)4Mm^9grA{@-sS#=H)&)6hRN0NDbO%@
z2KIssEfWCPgALQ_VJXDmI|yK?VS@=u!wj$e1`=-Avjv?IhLZnw5{9!Xv?2{&v6#{*
z!;VtmqYZPWp)<y?nGfBuhTETFpr;MregksGu<Io_8fUn<10>$C>1{ZZU~r_HInm&_
z0zM_#4O$Q2&l*ZUL2t5QCavmH3}rbmpK8#?fp^Xj`964Q28T58&KvlY$W1qVYJwLT
zhUuATWf}zZs=Hv={v#}98@3BUaty0~0Wa4O&4!jdLkbmP=NsO3!sss<I8+H+V6d0b
z&bZKE`Ux^chG}+;qSz1^3z-tbd#|9g)G#&-kut+#Is;N}*rCJFDh$V{*1pnEOdsp5
zGPF?yt=jPP0>CdDUZIC(je#)}25Svvv<a;<yz7rvy&-x509Oq2dqElu7wi|IrqS?e
zJxG(mM+bw=hFeZxwiuMYP}6F-Ple@I4Ig(vq|Lzi0laI5_l=l~>xQCSh_oBBlo07K
zOf-Ub!%#~pjZQ;a8Vq(Bay^0THLO_y*KQh|Ux&yo!?`)&^%****)a>Z4e!4InSR5Q
zly)32?59GvJBB%wS{O8B=3y>|3>g(@-8H!Wiq<{D8Y?948=PK((qTh}3Gfla`+tJ>
zz+mXX1U)o79|<jw49(LZIcn%4N5>2&DZD&xIPftfCk&q^(AHzp@OL}Bm@;T->+;xe
zfEK#@j612^XTR~qV01bfx6Oyh0i%vSCUVf|`z*8_GOoW3HBQDef5QuBV+57u9yZQQ
z0y$!wz7dv=8bc@zaLl-mLb5K#dHbNn)p(k!6pkCa-=k926UL?V9RN3D9G!zZY2?t>
z-`)5b#b!K=2k5h1o<`nX{4icd3m-sl<GEo-`Wj!Sl!%`(eJMozjW0>T3otIOginFS
z8)+axMgzT*gN+eiffr&diUJ_iI82GyFk^o?I_=@cyA=43F#4QE?<wOt3V}r$y(y6t
zW&C9gNVKse3Tk4EUr8YnYrGN&HE~9V<**xXoKE?|1mjQs@Hf$@nhTL6<FYa6JZtpJ
zgrmvESE%AK#mMl4NUBjt@bkv^+<;5B8&CLQhBAz|=`i+1;|FiRQkIcPUyH~#*3SSh
z2L!EL<5!!|$}=X@HIr}risG%8j3pW16&P<)RI$*gXF;UMxQS{WijAv}Vk{-bE_$q&
z8u<$$S!P^Df!%Ur$W4$6qkUyP>{c2_Xc1p!j7~<Y+BolHh+Z}>n+Byd#;&J9YK?71
zAnJ@?Q!KXL7;*=#E5>-bDI1JmQ>v@c_>h8<O~&80LRqu%@g}rdjK73Jq}BMtQjn|0
zg<IiToAE`eG`VI}*>6JIb>jzA*3oVhQ*~m8v5F6J!?^VTly(~bq_ks~k@+J?w^6qp
zfF9$<4Z!yrAC05)rZJy`pW>D=p9b1z+`AB+w~fkbXz4eqze8)l$cTbZcZ@ry&>A#;
zN*mN6<5mI9<z3^l5h%T9G%d%l?;8bgLUh=;c^~Ft#Q6N*Ks+%1wHhK1jjroq_mR<G
z2i&M}1x5bGj5F6^XyZmVBX|?W9=b>;jc-%-aLTxmBCC&$lVUit&-6+=lpQcl6a#nA
z<PbsczeA?Q6uxmX?NCG1*))TN)?t&&b$D^aw3bpaM@>JR!*m}rt)M5Hi;0(jfx4Rb
z@4=_zrko+PPMDTaMXH<W>3(QAY2qJ%q`T<_2k<;hGbvr-Y5M6^Xz?;FzYh^_lMN^I
z><&JrC!U81U(+l~E&7=}kD}#o>YztqfGO{9bOxHvKMi1zDV)}7!KQnAF^Uk==k%%z
zHC?9MX_#r{28e{4Iv&8M2-ES+Fn`KaM>kcZsh}G=qfDiVfJd9mw33N2)jkBk9&4Jv
z2h2Fr*C&98Hx+z?nN2WVrU+i5$;%0om}J`aJ{&%4nn%Y=l1*#e(MmDx$wMpE^zUpK
zOf$Xp2RhH2Uj7xXrJJs<04~E6NA<0lraMiraMASr1OQp43n>6(n~vwhe2(2TY6Uab
z6h}GgJkuJAEESj*Q*N-(R6=WsBGWp`MHZXxI-yl!DxzwxQqu-1z$i0?QD~>!^d}4c
zR+vtGi=kDT`e_qfWlDb&2CGer=>c`w<U#jAjp@TtSg17>-T=JLWZzu@M7?P)W%#d{
z%HD%$gURJ(_||A@-~-=e>fVJ`vnk^dJZv#N`vF8+O{L4hyK0(~3T<ts9uaugOxG5}
z?se0;2hiDW`r&)H)?v!0de2T1?ta`xrfqvbdQC?I0l#Vb(oU5~w@h<#fbTQay$9fJ
z)Atl=>^FUC1%ALZ?KQOSm}ayBIB2>(1u|qxqy6e#6UPm1-!t_$L)(aH6+Ltxm@??x
z!9!Cg-M5cSE%N~%H7RKl#!PWL@WYIo_8Kr36Q+_^C<`)a`sPyrr%ao7z|+U3YPvc1
znYUa6aWwz>EId45UR?mhLGy1T5IJPtybS;+^TFR?!r8p(zoTR3K>;kCG`F=t#NGVr
zR)~0*EvI47(>(h;%zK$vzW|-S=23e3_?g#tQYnwW`B_SB1eo3Kff;D_&_FcE%$h(e
z*!+Dwl!llc>Fidhc?l&G!_0rtS|Hp!cmu5nb6q~XIAzuZLTRM=bPqbC%->S-CCPkb
z5b(3+)KN@jin*f=V@WlC{4<oDGuyCvwmYPmm%j>2=gluTfTWw--hu86^9Qq`G}FxQ
z!6+`6&(dMOi{_x+5XmxoP-#rIc{u|jIp&jy;5p=)Bj-Xg&+O0$^ZDk#{>xC9g|z7?
zFz=-;Vxf6IEk%mV&(U(Q*nERR-u4o6H07g9&5<!+mYF|22z<FYEfmZO^Wwd*TWM~5
z5xT3)A6X$%ZMM-C{<3*HWld_#Msl>)96k<_I`bZS=+>JH^TE4fj-jkpgZXK4rqR4&
z4tP!G?xpB#HZPh$tHo}PyaUlzb8If~*UX)?y1Q;}tVU<MdBL}k=`e5c!X(}>-#G%;
zI?bOw2hwGBOG9V3`Ki6|zQ?Tn8=bx8EB|0-ZkikN!MkNnr3X!)S<V8vZRXxUXTNzD
z)lCkVCuFd9$7~ly!Qh}-kFrLGA@c^xSKc*y&BH+NnN#QC>b!4WY)9v?d0iv$BjzuS
zaQ}fhin0(7&1E~mdt@GZ6JCs(*UtiA%-ma!@s6ASaR6Y#97G?Fm^6n>!L=!K-nWo^
zY;Mv5x6ksGo$BoNTORI$jHBh!Zr~4Cmi+?YLCXpXXdkj%rTP&kOSS+WI$QR7qVuTb
zCVi^vnB}8(c;R9RUJIP7WmPb6$1Umf=s#ik@Mnm)S!}^Dc+!$U@ltn75v9mIEI)q*
zfTtz@Lwf&tSw8Ck(AzSH5^p}1cOQZ2YuQW13x1Y0CJe^kay<o|0hX!PK>{tF^xFqn
zN@xWZY{_~Tk|CBiD7P1CNk0iKVV3v)fEVGG=iY(85tgsc0C&n_>jfav5>IjID2pkP
z{xf2<Wtt7s9b?%M2ANpPaf%6@wtTt)GG{DzDWVo<d3po9h`0O|2FV0V#C(`Yw7eJ!
z-AR^T^I-n0rGcUg$(8~7wNfmFv_MF;bkbh-oF$D7l4kjx9#H2k-ETs5y2YuT?!OGn
zC$wwGwAlKAzhJqUht@?)@DG@hEQ{g|0JAMz`q6VN&QwsFYuRUnGkKOXlmN@O@aMt&
zB}*eMe+w)L^lmJ)DCsCvk!6Yspo%T|w7oB}tkt7cYMB-c$udjbDJZj-TjJ;}euc$K
z$E_+YW?D>Nwu}^_RcARyDX)6Vd<qv|v82;Fp~2$!1q?P?ehtAqHCf)Fgl@BC?f1~q
zV#)17tJU)5R+zYIxk<a`HcKxZg1BZG?}x~BO8`Af+ATFySkPg&Jn<LQ+^_^3f@r5D
zkW%zrmOD>?*==!M2W>qTH=5aAi_Zdhanmw~O3`mw_N)V-&+_>xklU716Oin;jM4uq
z7_cNpK+7FV;5m3PXc7GjgF}|(3>dm=iJuLTdzKVBfpXtsucF7!uw}9u_z}zAJhUEI
zUI;<!q2)jebU(7xQq+0WvWL#djagorgtl=D=ORQVEZ(zVV$#w?-`1J3tiJ-lW6SHb
zL)~Xhy#vYp)}UUv?Pv|xVn~Oqb172lWVOEr;%wbyUjxKptF;QuBi1mAE*`bMLmN0(
z>rq-29=AqNtnq}kv=2OYYZ6`Z9@bmWq2*~6uEUgiS=U5Co457cD0n{Br{lr%x4P2u
zH^4f560Jb%%?2n7ver^GCD{5NRU3p@RWDOIE!4W7_7`E+Dh<?xTR)@+dW7}g525Xp
z^=*nIL|WH=43Q{n4=wVdt>0#&6=QwQ0yVMLg$hWXw$77d*k`P1m!UJx`rCYrKHkdh
z1w6reogUqZRy`ezO0xR2p>@_8^CGQ3ldaGH0i`L{r7-}eT7Bpfcjv5Y-@;XvX5C4@
z;d$#1^cqdKeoT{)VJ$U7B-5&=mD>etB1OqBTA!iidY1KJ90r<g{qhBL=2&;!03g@;
zRWC@MwZsD?-}-_G<dQWW&l0;sfmKhBv_h-98+wbZ^Ge`bv32P!be32@rw41PwU6E>
zW!4WQAmvu!e<1+tr9qglv~Hp*r7Ek0Zii}XcNtojt)}ZBHP#F|cUNoO76x9OHTZw9
zP;ZT>0`7`+RVqeiZ?Jm$qPNj{rWZ0z*4+(YHe1DX^rgi*+zfoHwYM71T(w&1zHhU>
z{tu?B-FlB!g&o%5C*k1@>%X4^*J-V!P;{5|6?z7CTZgLv@3Fq}4CbQOdcOyNo7P37
z`j$1N0$Td)R#&PnzHNPTI}rWWISZg|z`A=owB4~j8wzcMR$q!}4_TK`bn&jWP!4DA
zS>MhCxo>r$?-vhSchg6)My!25L*#+=*=fK%wEpuJaF49dox#XPt$STS#;lvE>~q|@
zuOGMxt9_~&qLbEMx>%>I^PRwaY^|cT&punV1AN+VlRN{59c?eBK;(d}k2WL+Z9Oy>
zhiq@&gk2|F{c31)wz1lv?656|E~F#2Bkuxm)Hd%dc*kt3=Y!{Bn@d46SDSb_3>~+X
z+o`nXgsqHH-EOwb%dmUWb|nxkcU$1Au;gJ|Nudi*Th(q5FWZbUbb8yK%Y&qkZ7<c_
z`q~zK184kfztL{N-<CE35@36K3V=Y{ZhEH%*?bnlV6bi44YWdR{R}u0YWw6I#XrMr
zW#P~kZmacynh2Xi0c4_V|59`#+GeM%e2ndH`nAv4{*44L&err8_;}k!dIl!his;pT
z*7gm>43cdj6d6vj*=VPkYE#k^?VN3_7|x{Is{1fA8MbI6TA8-NnY8}AV0(@B02gf^
zuLU#9HbM))Y};PS@#WZrl;O{{WzzFC&-T3(mhx>X3H-fe`|=*t6xinf3sPuvq>XNo
zZ4Lz|i*1e+_ARjqsoJ&Fme&K-Wwzy+fS23+=?bc_?MKSY?oes_AEhy>Y?WWbi)!0K
z37D5{2L>?u8rwS*oUFBFJHU%No8$jEy3X*biY5#Q77#@QK@?FCL2M|BiXe(z0Y!3q
z@4esP2Z}cx(mM%+R8k-zkP0Lr9n$C}kc0%%2?>NW5=zSVj=$#F*_n4{&pl_)?#%4D
zYKUBQveE|_Yn>YR;-|Rg<W3=;>rT_@Y<iv3>|rqLo$k~2q`_(6GWu>f6_cZlPSJ(X
zYjR>y0{Ny>mkz{n%V|B`SIthW1L$mXx)ulb+nti><=El$%v%8MbYlGqa@%P}INa}Y
z`jU1>cbxuUg4ylVM?Up9-J>+%U8i|8Yu$62?hexHwCOR1ecx%~7bx^O)m6i_ekWxp
z><&0>rK7cj4yW{QAv)xAnGzlkoSx8`qG6|Knsi5;;;6Xzq0?Le^dC9Jg+cPMQ)x2#
zo;al_fj#PUvL7&GPEDJDJ??ak3b0%mCz>JY#+ZK%#GUc(`+)Xh$mvYpF2*ZsfVrE|
z6AJ}zhC{Ft*ggzDO40i=UKoOTKSo0=VEh?wa>xWQ7Ca9U$f)TDGl;Q|USPqDrBr1Y
z!iY2CXAWhg(s_w6hR<SH3TG5tg5(~?I#)0w7<;WCk&Kx%gYRWrcLLeRNNb0^XvSZT
zO)wwBVEO<wmQm~pOL2_vX_FSuNTX0^0;78d26})IPrJcHMm-ZENsOnKK_r>+=3<O6
zg)#jqoH@vtmj{$XjPKtAGnL_33iUL`@(_^2jC5LtrZW;(K;#JHDCG!_GVbI4#{<Op
z=PS6F$w;8sP8Oqb0;1WBd$fAbVN8%nE@Mp!6pt|;QXt|u<Ju7PPcUq;VCFH*R9&3U
zc%Od40)~K6Und#-DX?3}xE>CXB8Gb%{4HjDOsTdKMgm2fOBq6c%8ZsV*3i6B&hU@}
z<`g5c4+A~Tm~{lA6%6?guvE#Ie-f=K##zdIS2LU&fnCFh`we~P7>g;Udy%oF2%wi3
ze|`ZEFEd2+2Drl5B!S*l#)I!*p_Vbj4CXaP3SF-2jNDgf{aMFYN-xKHhSzuKY-E(u
z6W7F;{0_Xh$@rLZskay>Xb;}ZsC)wREsR#mthO@ze}hOHV<!jL?Tjx*@WXU4X8QoU
zi;+jKqdSZ&TGe$k(l<ik9>csFeZ7n|LGbrJ;}Xp*jsZpwh35wuJ+FccF{;)>bcDgC
zGgJ>5@iPJQh@qpH(kR1=J{>p4XrL(4ID?}Fnk(}r12AsP%U*ECow@ubB)yoQT*9T?
z#Vn@f&2DD*ZnS)vIaICg#|&<Uq(5`pbl3}WFym=C8O(g|Wf%-$20TD#IJ5H=i0)zf
zQ@|&JSwgezKIV`HeNoJL-9X#V{KEqzmibN|m~qVObnC=3yMBg3BJ*j=H779-j{`cH
zxrxH3hnTCc!kJWNlK>=*>7ZiUBTUDnQMhrGxyK(SGME#)(aL5%utG71xrk=+TxR>*
z&^W<Ncm{oWOfG#{FrWD`73dT)H~qI2XD+6cPBC+8G@L18p2<e5ocRi+=ua^NXvtT}
ze2t>(RZQc4I8)7x`|oH2^MHd&{%e_LO7~o2>S&g~&ivX1*P@QOh&Ho$-on9bWL9i}
z-6m!ig}ZJtKl6dYEv6eKN}8EJt%ScVOqV*4R%RvzW!jkQXbsWMY|Vvw2a~-W<~x~N
z-O;+uT=^N)?=V@_l$h#f+KdqGVIEiuyLXwcbh!H-bB8yEeV>{A0!Got+(H!`{mdK1
zz#d>8z6FIrW;&H64l##mlQhC?7lAxvCiMaH5%Zo4)JK^Y=?jcw%!L9N9A^&G^z6d=
zg4RW@tc&l^`qPbdRt^n!)@Hg9Jy@w<W7uA-JUTG6i*=#|26wae(g?j-njE0{uvSuF
z%$GHfHnV=Loe?1ZEa4KU2e7`E!rwsFFxB}4u~;9&i(pnB9U=^2d4B=SP*y%0C}FIt
zGbZ8r3upa)6Ta<XjnGE~BUm0nkVuv{Wk2__o|}WdeXL(SpdZb;O*c&pE8{ZE$Fh7W
z8Ir*Ik;1PBSfkHFFOe0n1dgV#oHxMILDuSUs2^h0X#sYaRn>>Sbk>8V82u5}jZc8$
z$YgE&5q@W}YGVMC&3cQHY{yu4>!Em@)w~`sCs>^Y&?sO9WTWpS>*H7`6td2ofk+7}
zlxmhrSy7wdOc`q-g(Xh2nkc+i!J0#}dnM~DDvYgST{{mis#)zXfLX&Tr^ok<gXLxb
z+F4d3J>utBNl~zLp0(vY$XsB3_$|;bvi|uKUR-7^SD^0-YdKX_US+MP8i-of)@MPk
zvGzDY@;d8HCG_f8XIvrK!1|KBxWQU53F?h3lM}pXV!ad%^_#3nis#*8IR@!DYG$on
z2lFkg9bdzlR@Q5o7-$>o7R?mxtV=OqcCc3YfpoE0REmCw<@qN}bhFNE!LaYK?ovFk
zm!+pgz<t)UbUvhybzT7Ie%7(KK?Yc}sUm5RwPZ0whFA$B@Zte$r{hO(hgo5BpfSSQ
z_$kOk)-q?1N32w;mwU|mSB2ISmVolCqpaCuAY-hr6XE_i>-oPyCRlfu!%-J@Cl`Zo
zWp~~HabsuD1m(_t>Us2eu+P&@!jp|cc--9Vak^@|*tst_fVP`mR1Fz#ww8|N_^=z+
zLDZLB7yuYQw$cJG{Mm1=gJb}E7QNL1*{Oc$3u4P_;94+SJQE~@eW4Mcq3o9$AQHyj
zd=d)b?CbA?>|xJL0ZIhBn5rTp+3P56vX{MlE|vc7V-FvK-6*!^AHeKqFSbJ?n*D_G
zQ!#8l<=<o3Z!7{cj=ki+&x)`Y(t;|1U1kI50rolC+9tB^WuleD&Zk>8nf)1k)-HwZ
zxfs{^AUlC(twZe6U-7%9vW-mGOJld<9FAk!VfN{IaMRiEet<C@Veg?slSkQJROXk#
zo=NfEO!l)M0Va#Bp*Ki2`(xU2<*={q0?cuCgg3@?g1y8UB#-?T)#K;0duV4|!2YHH
z-k)T5k)wrdJhoU1uwSD^S}}VDJ$HYUu-BGAw3HqGFB~po|BwsNa`wpgXq{r4rb6a4
z+vgZyD%d{vp<l^fn*;MzY&FG%s@dEz^wqEv7C`R|J1;`~6RJwyrL)!-*il?qy2xg6
zfO3f)=mL?;>;U@huCTBCg0Wm>7t+S7mYsSD%xmmq+TdPi*N&jCjxD1bp`OjB3)8?}
zwiIAD*v=H(Z)DH2!<Qy@hBusOW{2n@(!!Qe+M|{2<cNg#ZS2jDA=Azd-wP8R?9@Ck
zJK3qj0KLt2r?^}f+w)oU-C=*{2FY%A&pt4F*nd%l+Ff?*&yc*w_M>wPz3f(sPu*w#
zObM1gcE^YCqMv=i6Ose$sT2<wWGg8ZI>de@lcI_b*d@X6ZJ7O>8#G4Phi}2fhwM-8
zp!JAdvl6YxY(J`DeS(_>*Km~m4ikF#(D0W49cN!%2r|KbEfpdzoai55(3PVMgimgq
z0@@h6bDrA_1rLrd72<kw4pT*g7bmNgR&~2Lp>*_RH|I5q(0X&e3Pj6?vx&YF<IC|p
z4She(vnQb8&lwDbr2tN6Ctw0OJJx|2#QFYLj5nBb_YM?7INN$463SV%9zzP_98ZTx
zIOoX+z}&;hTZ6s`P9kk^BRL+2r{J#M%L$>Xp?#c1e7G3Jsi#_k{haH&VIrEdo(Jq0
zPAmm;VmXZMkc{JKsX{xR(@LMyO5m)as_z4w_i27g<aA61N#gwM4HL<njlBR%;bcq)
zN-C%7Cs;`1RIUQ^FlQTmkIHeBv*8&GJA=dg5DsT@jI=mB!Fe|UG6kF>3V5F6{79LV
zLe5VmAVr+Vw09`x=wAaV;Uq2xXelR>qQ+&MV|1FdoD+N=n5Q|FXV9wPbX3E`N{(wf
z)T=oEqmNHib2=!<UgO}r|0|kjIj4ppdX6Lc7b85+iK~G53!IUg=)1_-m;(1NakQU8
z<T8gz$&4$UyKWfhRZg-6eYKpq-^0W;&bRJRxX#%_w^bddV+jn_bE;+mtbucx3Po>l
z4sL;kM$V;E@V<%Tn9+{rO-?lx!`<S{p#?%S=idZ?ws5{U3Kv^BMyfh!<BU_ryq&W?
z9hN#cnY38y<V3llb(@nE2fZ#1*Bg>|I8Sdz>n^8j0GRhUYm*?^%c;Hwa-Z{NB3$d^
ze2@dMe$KFC49x+~VG1`7a%PW1V~BH$W|jw>uJd3Hb7HqbWQ23*Y54Szlkfprk2udz
ze&{jh(TBJQPdF<2Xw4|+s~#}NIQf3CG|uVw1exHNN!^9}!slqYa|0>E;la&O;MVcv
z)_>!Gh8Opn8SrKox2zc^c5|!f?d{E-Jq@Bh+zV6$=gWQW9a!??zCuY9f3AZvPyyWk
z(bqo%xy4ps2XVvupb*Ucd@j^OxDmt93*{=Qk|~UvydKcuT$>3Zd$`l-;fUZCODL)l
z$<=-ajlJ9`3JC1uGX6Uo#C3cG(EZ%=v=fQu-k>0T9JhZD{Ep{_(<>u^+uZ@QB<{4o
zK$5xrYhfaV+j0~aFO|C?1tMu&p#XY^x$-VRALVkdf|<eP(z%07ZsA^vD&}yzy`hoI
zot28qeT>`q00vKRCp`;Gd0f%+(9h?p=v+wwS56y)lUyBzZHu_AZ=kQ3`y>sZCEN%O
z22sXkQBb9vdzm(6r?__dc~5gcqnels?x!E&8dh<om(i-`w#(sfgnHBDS&nk5@jK65
zO3TX&+?~Gx=^~eX6JB2Cy3tvfE8J^FNMGe<)B~cHTNaDfHSU`f>b=f=>02-xxIa?u
z$_?%fns*zy&(p@Li5pMGZgMMVpK^;EzaI+C+-Htq04>}%=U`N=+)o`ei+6MHJOhm$
z?zT#hyWIVhEx5-Wpgc@37bO+AZMg~4;95Vo>vgmSxMDiqGsImJ4D}K2`G3&&kh_Ck
zz>m0xDX9FI`}zs=J>gn1(KpJ?qOJKDH*FNHajt>tK_|GaUr=h-h4&5JVXnNjv!UU}
zd*@HIym)$gG40}QTMOoHo{4S^Z(iU4^nG}2G2Hj%{Y<$^KOUnOcKvxrC^8<v(;bBO
zp}fCe2MOctpAX4!-Z&M?@8M;&Kp}!>#|mp&B=6Y@`by?r-g~rt*vH#x2Z`c+{tIB@
zcnS1N$Mc@~2qb~GFdudg@TO4qIFYx2zT2I|`-z^GWZtqHFp<IwmVq4P?P$T!(s^B!
zKsmzul=4MKdABJ8k-_Vvs*OxuD1~vecpD;UYoE<at$<<<4~1U17kS@|1M~z>JQXC5
z_sI(&`8=O2^cC>dtpv<T-WDpgE96D}1ZELW<_?i!UQav>mhk?%39wRLEEPkP@!oz7
zedRpi5SUfGVhRIS^FE?Owl%!igK*7phBrd>&1ZQtXn%E%=SS1gdEN{vK)AqDJPpu`
zywYl*)$)p{a^M<oGewTB^So%AR>w0>!FcO=Nw)#oz?<I$4{z{RoP~NLZ+QhwH1U3-
zj94pAMH{j<o}w6F?YypC0PAq@wpN06@)~~yxy@T%2QRvKZ}UO!@M=3@qMP^XFwpMv
zwiC0DH-l1^{k-Ebur$EiNkO<l9{&N{9^(B*3)u%e4b|cg^X@MO8R6}w^B0eKwr9|K
z!i!FYPoum;^c9*hp5vKMfHux+c?&WVyh_Tbx$sjdFzL#_K+7jL{^$!3ap#}q0^5WC
zgp$afe2)Z(`0#TQ(DLO!OJ~9S_+u*}>Cexl;9&sY>n;oi@(+ED3lzj(=nsE``BNHk
zEkgJ^K83vqzR-~d#Yny{O<8;SuOtI)AO93pAx7~_U0{Ace<n>9(foK?_s8&+n_wcA
z|JquNB9X75TQ7;9Nw;1ye;?g?Df~aE_T(Tx;uh2o@n4sNr1G7w0VR#U<iBtB@#Ag*
zER#Q3;eZ=i{Ff;HmCdiZ18xp~T|KaK`STva(lP$ox1o5P@5BSl34YmbVCV6}DO`V&
zKY9@Ah5XEJw2JsjT0j@`-P@s1!hd={)JyqFFMyTt)983zIe+{OkW+kVA%=UJzjYav
z7FO^dQ82BNzlBa`oaKk=0dtNotOd+@epCf6&;|aNd|0~3-%tZfm-w?N$#|Ks=E1}j
ze&TU}*728n0koc<;R%rjej7zAZty)MkZk0?`V+vK_=ElEyU7otCD|?h_sD!WrnU1U
z!hqeuKVbv6lRp$oHzGf28AuoZ#|(hp;g5X=(#>C02K^pB_ZN^pe&7-Ol>Pi%y4MHz
zvH_4m{*RPG7~=afVfO+5eK&Y9%zuLx4kP>vG;KWQU!Xbr3BUe55XUHggkl(D{QVTY
z8|N=e!}Xfrzs7@4y98@IU}Cpm{2=tb1%Z?p@DXgYfcOeFUWdM)z)b-We?c~trvwPT
ztcPTvAUqD3L4tJpz(KGewFh7!0;ga=hYCK*f@@)dsT6e&cL@I32bc)KYI?m!3TABs
z%wB=a3x4kt6wtOmO0ec{kZ8dW6&S||LaB5uR^UAilJSBl`YKF<V5JnG2Lxh@(IyI7
z=!{{KppA<64+>V!1N0$5O&j`B1q*1EnI>4G1?FLaqvIcN(*>2ZUOOUqrxj>N1?P28
z%n&@HDLhLskCutq0*wtMN3fRa2yz9_Qhei>Ao^X9<AQg4Fo--sv=Acsf=~_A3j~4x
z1N2Ej9i3t>6kJ@3i%=xE_Z2R4u^_4nK9vZv9ku8z6+BI=w=%)ZZMXx=1-W$g;FO?}
zYOziW8tHzn5De0^RVfhBw?L`{N{Xje3rc7^TO$~vQ2ZG|TLVPS3eM3ngL8uZ_u>6{
z!4g{GTo8QL0qBc@W%M&$5!|Pg)Kx)b7S$ot3O2rs&TE1qx`VF^+*;6CCup3GQ8WlP
z97Ep?!9VR7Xro~I2uPD)!+hx76e!;Yxh2@I0%(h1&=u;fg0`g)X%mDrq17Sq^aog{
zKuNi`+k&_D!<jBYVKbob2qF(rXsuh26M#|l2o`?~nR|k5Poc9{5OW2Cxi8St>FYkh
z_cU+x3j+QJkwL+ES{)Aws$T+mAb36mBEy2xSui*v_}U%n4+Xbh!bNx@_+bI`Mg^a4
zgWi}R;4H|vpoq3D6M`NW+S<Da6(6AKDtz4op1KJ=DBI>P?4>NBhmc2aJWruD0)1Y>
zkIT`wOPE7n$k{DioCUYNg-7`i@ezhoJk?itjNY_<LfINz8Gj+819|~MZ;I{&3jd~*
za*)tSg?GWinJYmYA;PDmfC&|TYK6mL!mtLI2p2w}eg7WeKny@5guU~@j1(6Amq8T%
zdk@(AgwyjtqJ%Y5Ah}=o4aI??g{!{=i4j_TpcgBAk4kLggbg3#lEe!OePAI$_z~sh
z4hUD!TPe{Y+)6iVl92g5JWUo}c>=T)Veop0rV6uWK|f9SDs9sa3+-Ehoi4oL3+yAp
zA==#@6)vX4ONLPRJqD90?Dhmome7?}ciF<~htSIr-u?lSxk7dq`i==pC=-5MsGJ9d
z6GF!WTJq%yOH{aQ`9jA{pcM$0d<Mmn!sZsh6bd(NL0^&3nc|bh!b!AGDiM0($D39v
z9DE<%mkEccP@`OU`Vk~g2^%Qha9Ws6_eF)!9s<2e;RkeXxJuYN2VPVQ3utjyBmCPz
zQ|TF@o@#Z@3g4nHqMQ?+dK2a^3QxWVa!J^;9PVEh;?;^LN9a8h<f?Gr_mHd=?kE7c
zCLE6g%5~w?8?aO-+(wCvdg0-5c+ntazJTBUhVTzcFEk2`bD_{AJV8_bP2unLRF88@
z_~QZ$rdjw#6f|0dPp^f3t8kS88g0UxYK*X5n7;>pcL;rKV0H>)CPDJHurwEa-9mXT
zT0O!GR2zF&xR6q__k<bSfY~ct?*-TTgiC3;(J%b?A)FZy&fkI7pwM}Qf)GQ(+ik#p
zAiT2*Fe5_W9_T+5o_h@aN5bI_T!hEMCAT5+L^wwYzej~fUW3TE(8C{n6T%7#BfE&!
z`GB~IJSg1ZF8cW^v^+$g&{XCr`ZgGnUZNEgE!-{orvSuTl!mfU$21>N?iaWSzM|vw
zQuPy=R)hG9IH}MN6v-&T93=972L^*h!_&bG5k-t(prN9DbbEz~lGzyH9#IL!iXudb
zlh79_y2!y;_KW_c6neDi$F*R_h@#@*TC6DdLy$O8-AQ0N5=0kiuX{k`xB=`$QTu72
zC5ia7ph^}!JPT%usD)}i4~kkSdY3ACkKV~?BL8E6IV}2T2<qvg&>;-sh^T%a)H6ge
z&p<s>R7wlSERi<`IxSoD)Fvq8h%^EWDOdC`4tmENqS$p%%o8Qh&N*MSa5MZa5FMsK
z>`BqSB~UCBIa4O0ShQ>n22&!coC8uS64CElCYqp_XSt}0qK&6SekagZA>z}MS}79K
zQ(PtT%0{bN^a>?$YeZKmS#U-qmqY!W=<N!6EY6F<q-b6c)zBn#Np$QZ$Xpirj=<9^
zB4vaN58*;)7Ditu>Yxm9z38_#kOomH?f7np*3so|6m6pNrJEx88Gzjq{j5e`vnYt(
zsV$-(Xzpzl{X&IgZKBjsKzE3~p9zIdk^W79-4@kR^sPrE{t|k3MT7UDcTbc?>&IS^
zyW=Tn+!uXLah-nA(LA6Hh<LNn8We3|fDDNiYzNE(QHcqyVbKv<tBr`d=rGD7(XVe|
zWRFE1%i-D+QTjrVQPBg6WR8gpbmU?}B>D&jUBur}A-1cy^b>gDCT^dHmb<vspI!?d
z;(=e`qNn)J5OnSquZ)HXZ}FWF$oPo=rXYf^_>Yf3{KS5=3HBEk^*|&*+)X)yKyk!#
z7(|emL)rOYasCCk79#$ProvG1YgFVCChjVSWVm?6-)QX-&#HuL5#n`s=}C<gzj_OH
z_li4T2X~)%oa$Jk#5J$N;C}J?O0=TIJvxjjMqK|2OvH)>l;4gM|Gg7^@#2+#p)Wx^
zg<iA=#En%TiQ<pXVc1FH?`X-DEPlEKk}2YE=D@;1aV#GShr~TgCgDj<6@NmB@icKa
z6=)q6PooDuUHkzp$&ZL*Xz_4V{2L{&GsNfHp_nP&y&ei#VwN*Nv&CP24#^yGI>o4t
zi;clhI3ZU40?9n_{73NOq<A?cM+(I+nPI+2{9GqmrQ#pUa4j5VVlfq8m5W^m;CF?1
z3f-%f;?1<_s1lDPK;w)!dkQR_72jL~6X(Qvw8XtAzWp&;m&E4;P`@nx;|Q)ytvD+Q
zDA&ZV(Oc!Z*n2(H8^j;ee&mMON*}Cg6xY#px+P{EfqJt;>`O6}7V!c~*tUwrl)q^c
zd(d%?c5xCd>pH|CRD#keKE4P;yDj#oD$OqOAzFIf5ueC{NRL>P41e#6)89kup16iW
zWWC~#cmTUEUP3R4esR4FdIREDCIfm<+%*N5Lt@8H+5<cgzupaRhQ$G5bdHF*KLhQd
z_~-Azd?e;jJm|3)-%`d+F5Z3?prhhJy4T0Vx<G)Ai-*rbazfmwL7$66ZGm}L$;2lB
zbCY;qgNUajF$e~|B)`$-cbDWjTKMgj)H<kM(Oa@ciKdUltb?epBqI}|ev<7Lpan?s
zXjv90@u9_5kffFkOTm&#I@K5=aizyNRPra4hlNSXt3bjfqx8T>N-njcZ?EJ9TEgs;
z6xKo^S~82?KQWTFuQ8Tb$wU&pDdQxrq3Dd4tfSlHfMnw%m`{{sP((6GQoI9w$&$IB
zqc25r;b(YpP{P`W)*;E{k1)biNgl<I(<H?-XCIa<Z-YXvq?gXg9Fw^0K;LnRjt%As
z$yrJP<VoT-03~1I#G{pJfyCzpSUM>=rUAE5a{no`iX?Z!fn6;5lnqiMd5OvgOC>oU
zf|N=6#^83j<SUw9Pf6-$0Q9tE+isYzkbK63NTp=WZ0J=<=FpO$S|VtNGc}SjN?e|i
z=<mV8SxJ5$J%8sU8-D}$yyOAZ9bJ%w$3gU>WIlZ?^OEFEdMGbT0;#sIRw7>jOV=dr
zG(laLsCvO{ki=3r<c8#rT~KJ0C=0=Cl6+6;xto%CHBi4L`GyW)v`TJKDOQ{0tJ%1|
z?UK1vn(OG0Y#xMYrzB-B^lwYFbS=6h+ou5Zj->SzNVnwQ4`8=PQb&)|UCAq9Fn>={
z`Ux&VuS8B+$@`KGO+e|BH2n<8eu=CGWI!@?A20_cGyX<vNU|aWA`c`-FTt5%Nmm;B
zMjVnAlvaEw$)T0~BgqEJEI*dS-vxOhSxhAZqmp0kFfk?xqx8|ZB=2pEa6;lm<t;AK
zFfl}2rFSmCZ8xb+jy`wk2wf5n>7R8l=qatBN6kyR=nU-clD7W@=5A>UJzL&VN6u>4
z^^xvxgb82i&;H>0Nek%=fWPz?TG0eZ6KJ;)EOn>Aafp;npF{|io}o}ynDiUk*N00F
zQ+j-lbdem`5mM<r=tWAe(6qBxy2SvpPr7;xdQsAs_rc%&(qyXZik80Npc67N(sOYz
zA1hr;^%`-~$y8euFa4Pk3klM>fiQnS`qC*#CQ6s@g~24LiRvCwq-FF?xP#I`n)44y
zr=NjHs<f8Q*`!JTr^Pi)mtLDd-x2BcQYajimeX!MOPWn}CE3!vQgSgzdW{a^=1Nnn
zXdRQbDq!%q)Id436Vl6fp_nHXDFB);^`L6l0_idV6i!ON;zF`e8bVc9MN-vtNES=y
zQJlR*`sy{9FO^>14`!M4+X>h$mvZRYJSDvxi2<IL#uQQ#xI+4-D>^Hs-_dKoO8N`!
zysD*PnGmg!@-z@VBVCXPXU<9!|NG2?^h!BQoR|I<47(SkS7=vtQM!Xpk6n^lZbIR*
zG@lmOSER2|fc~m<dp-JUrRM_Cs*`3=h^1ay`VEEa8>GEr4DE)run^ovX~0pCCTTK-
z*=|bb(S&|W$`%5&S^6%mPg<m(KZHW7w29V5?NXnoa7j9(Rg~E7l;$R)uUC4k2;{yr
ziZWDv(rHRy_Df$XLTf;JZx+A?rC%pO#4#jY)Q#~zkfu>N&#<)R3y=|M_aoSSB<-cM
zY>%Z^w!-cc>BeJVj!NhK3Fes8iNZ$X(x;yT_Js7!DllDTgYUo@HyMZG%kHw(bk5sL
zcB=!HcFDe@6JEPz-i>H^%l1!4%f})6{SQ!I**`bno1d)Z4Yd4aN9k?}kX@pmB2e}w
z1;m48+bu93B5U3ckx-f7B1RD=drX<Ja9LeCEbWo`9S2H;Y-Bl1?3Eplhx$I5mTurE
z*|J9H?U!AmS5366i$YnkGRJ%>MTwIQ)0Qhiwv!fO2W0)U5KEMOe-3>qvX(EQe^53^
z`iEqJ6rISD{SXUF*|O1K=;g>Z&V(1avN(EE9+UAWz&tK{gXYzI*{75$D3CR-hchQ-
zE2cxQP`0QZ=8I%Y9h5&RmX+{<T_StwI~XjL`BTukO!gNYO(~aoY=XuqnMVWco|ZlL
zA`~iRr=NjBm2AbckgS%irbu>;%<o-zaYj}V1IhEUCdwaNkcsGRcu{tiB5;>v4POH6
zvW!iIN>^mXTuPT+m37ctqE_a;4vN=gi4=*uF55}(#yZ)5b;9*Bp92_7gKQdARNj!y
zeiQnQva&jO*d&Xpg5FJ8-1{K6WM9(uq*?ZF6#80Z3uv>^Dho=+c-v$mS}L~7BAcP!
zA)B_BzGvGh`;+#xw`GEtfZZi~YY}Ab$g(MI+%2np4zBgc%rtM@l?9cfbx)?EC3&xG
zO)Hr9WnUZx>63L#gZX~hgM6S2$Ra5qHz?EJhNU6d0#_(JkX`MD$gu3YGW3nezHp*L
zpbupq1)}*#X1x!Y$Ff5DL#-#WzvcKTMrBqyeljL2@`U2JY$t6KCS(Qlkt7%SugB5n
zChwuRji-F`_vrJI2hz{HOI}Z5*WL1d`p}iPJnkQW`N*T`^IpF4=!;PBlYe~%t~vbW
zR~leGK)xyjXn}I)eUJ%~n@#8pmaqSBYbw7jMk`eAppavfoJT*?e)%(3K%(V)zeQh+
z-18{ZW95I-r(5FW{@>vu#LNBYmrRg*j^U~ukRQE<R-!z=9L^-kpQXi4vO|7{!s99O
z=4a4(P(F#ufDXySeuqq|yo5e-ktV-K3+==5mUQ%`%iDLt!z1!0sv9~gpF!umGvo`#
zVLnq{o&ZZ(@|E7`%a-q@53%RSdv?IXT)8hzn#bgSbwmBQT(%ANPRJe4EkiR;UeFDg
zd^wBa(*^SG88CQKZqNdzQ2uN*NRd3|5wMHpja1B3BJZM5SgCvweapB^zLD}J<?=Dw
zADohFxez%m|0oPTRmh+D5Rz5$TGY=@tCkz-?y8aBSqigf<Oz<Muyj`b&T43!lW+Y7
z8t3JybAWb1zLiQdF3P`Zgo#V?WLgtnmj6Xby({uAI&XGWKAYkZ*X5pXqpwb0;SUe%
z<*!pLw?RIMwzN0oU+#fOqr9*gUNp(e-i6*xxr!nlx8zIz%j-AGjg)(8kzafOZmWDY
z1;pFr2YsQ~F7Fyct3z(|0%)gvHT@K~<-6%SL0$6a|AELIxp+3*?v}sjjWPAeg{#na
zSHAcMkbClj6ol=SyL<xm`|_m}{Oyx#C`{ciUo55n>>iNMx(U03@*a9*hUD{Uf_xzV
z_dVDhme+g<G9pj^9*Pg;RkU<_Bv()X<FWkKuOLt4OSZt$sC<}?L5|7ae-R4f@*xvi
z6Y^g!q0dFJeg<4~SInm35f8<kIG}hcMvTu)T03pG;#(@~@m9=<hN6$+^C?jDS1fS?
z2~Y@p;C`SY;(Le$DMTn+oEEI`eG$%tD0W0-=nz5pogR)oiZ`2Z4I>oU%g~Bc^nC%l
zdlj$W2id2HrsP1B;&qzc_bZ;u1z5CV1+C#@6q3iV5UW^EQNcLH#AHCnE3#&TnV^_Y
zA)x~bUwYFeDkPIYk`$hl!%S9eE5RUA6b%jvjvQ1-oY72Ea8|>M!-~@syG~c!rg<(y
z@fw}}%v3njIxtHyjb1g`3il$kaum6n0Gg|~I}^-f3dbBcdR&n|56lyaiXbra6tNig
zw0y<fm4Gf#<W~aoq$1>9v<elg|DafVkz#5vyeL*g(9Www5kUFIQiYcScFPpA>1!$F
z3b#&RpHdj3;r?j_vmAXD3eOxcD-|;+f>5Q1UWhxOTCsO6z-koRX<9y`nCc30R*_88
z`Z>iLG%=l597=}SONysw(J{u$3MU@8R}@v}Vg9OO!6fL{D&nYa;+i5{2NU%Q%N~rP
zL1CiQ?+ry$E?RdK%cxSJTT%5J%=akXr10rog&)1Y?kSdJ<0AAb7SWRHzM{eoW}o7P
zqtNSDq;H0W0R;<gJEjdPj-E&7kYa#>bq^HF{9$5PaWfvGBMJ_EM)aYAL4H3{?5Ew)
zW5tv&f&D~rvJhh$Rm`TDe@yW~67*b@&rvO)tMacyu<NEgLI-2qm3P9x^iY=W0`XKP
zj6lIl`GE=|j$KL?MgDgyzoAH)x3X**T0Y8%3XI8DIf>#_eoAu(ME#ZX76L6m`8#b$
z0+q)o_!Oi}qbDX<Swh7wA<9CUkwTS=_&^C$s%SqGuDp5ytv$+odQu{klPE47sq~;S
zg}n~tdlb#wr+n-L6H&@hDw^1@{KFruXyuwxv|^MieW4hubfJkcPPvZ((0FAat?Ck#
zd+3Hbp!|_`wu#F8Ex2k)O2wDB7RgE$y~a|Mx;yw`4k}$~>vBk`>xA7@W%gu1rzzj=
zo&^2F%4AxZrz<NcHgiOIiRO!=%Ii}BnxVW9Au-`eeUV~)Im(Y}fSs#+iE3MqDgUOT
z$>Yjp7oc}S`9F#g<|!*n0G6*@u@|I3`7NEzIH{aVtGYsE@H&jFNO_DtYFMmnii1Ll
za!DANrOGc>0kceb<S&qN<)=*`r<7f^c|EN>?FfV23gxut09vV>MU!=vGA#-))yf81
zkJTuDdKDUHluvTOJgYoN7x<iVCcVZkDr+e4e@W>{`I*bgplblTqRgBOg{#W_l&Gjx
zPJJI^xu#5~3c>5j2_Fo%PMJZqn)S;1ophR`LHQY_(Qhc*(!p(1{=5cgP0G4Iab<5R
zi#MRJMQMM4zE)+&fA0b1^Rs}~uGCU8utS;nBHZp&CVz_79p%<nFqUrRi)*3Yqg?0(
zFM5?$+CAP^R#GgdPwBG-eS^y9gXl>eQnusd#k2>?%``m^D;4c<ctn}A0-iopzVR|z
zkCe&(0{gLY=r&w?qMUyOFr&%^R8Bgk%zqKCjVu37g2IIIFDkQgQGL1|c3oBLzJzOT
zs;Lw*a98~=9ZV0^-#_4o*`+#t^C>*3yH%TVpy;h)&=l;aYQ7II{8j0c(hN}b{|Nm+
zRZJQbgH(?W!I@x{h)OR)R5y!YDO9DW4Mmu$>SZ_+u3E^2`X1F2T9rkp&eN?EsoMG`
z`u3_6b->)G`mGVIC{@u?_~h8Hn%xiVXjKM%gd|S&<5rl6SDm3rGePAq2X>Mwf$sHW
zm3A6Pic0ky`VOiV*x}kC)w@rlm8z<siq$mL)Tg0vSmpT#ETyX^xnf91RO>p?cT|-|
zA%hIn^34#*RI%2;P?kgG7X@y%N=r3sIjV(pm@8NH=oR>MO!etOxR|F>RiiIoHShz*
zTcApzJzAN{umM9WS52Y>$tl(70eEp*wRIYp6{_WwvZ_>#UV>hgDoFx^)vBlup;x1N
z?gKb;M)i>9)w3!`*<Ey=Q+?nCa$dDe1ad)jXeTUPRE^T9nM<m<S-`%mIvxvhMdeI2
zjMr3IROfqL)qMjnb*dBjVAiXCrFUb4YBAk9H&mS$K^j%}sHV0_6-m+8o2u`q+_y!Q
zauK9emE)k5P@5{}Ux>D=CYHeA4%Iu9IqOtyr*ebas^{qfb*aje(7K}<m;%YWDh3_&
zx~F>Q4-B+db&&E7_f;QUgrz=J^Fk=}t43I04yareaBWcaXAKMvslK8m;)setag&Ft
zzdoj&;v?00n!O&Yj#HiS6V>lj-aM+>p9lRhRc`^vxT<kG>`tgI`~gWfb<hRqxvS6r
z4oe>D2|7}}OTAl(zTN8Bry%LA{+Mbn{nRfG!%=_raY{Z0sMQ>_g4LT{&<asc?xd=$
zP_-N7SNEu0r=l}Ly_&wA5~;R?KtD=-iZ(L))nC5|*P_+ysN^G2ZRA5CNj<d#tz>m>
zHd-m_T4#tHR6jThe-Ej1djOWIj@7`YG<6Ua*dJCeEdVoJeU-MdN7QFlQ&#M#`q$SX
zlcAop3No4MNUD;^Qd_!UK3lCUhxr`!YKkxCs!KkF;xY9!ipd;T2Y&#AC)9uE!+f4v
z9fZDobp{U#1?sn@z&xpbj?xE(>Qk>np-8=8H~cMDZy-{lp8F0I9HnY`3>+?3SH+`w
zO5HjHjnnF%o`x3{YSRq(RH@!h(`A)<o)?(a>dyzEU!&fMRKc_}>I1I0FV3p{C{%b(
z{e>sg&#OmXgKHPmR~LbKQT>?<pf9P{ZGrk_wNwp-E9woIK)LErFQV=4b+zXuaO>1J
z_CmB?z3pE(+^A0d4knt^pHLv~rn*D~W{cX7R?n^K->77<P5p8WTJ37TRcLjnoBe^(
zseVWinmcL_%DZ=~<+Ky;QBP2ipjZ791@-T%S23a2r*@1;(b=zl5C-1{)I$rPKd63j
zFPOvX<uosks4p%6d8kgOP~{W#_q1*uRfoI<$uV`wC|q;VyhCGh)jawWeQuhCr!gc?
zO~h0%y)<*z0D6~(MG5cSniVu@dTZWFf{2f%$q@t^todyKogo?#g?2(Ud#WK5rnycP
zh~b(%x~=zU*3(KiLZe>{_aim$(Fd&eYX0qm<UY+TQi#%cyoigpU$gW8TG5)WU2rBw
z^T%rF#cG-<OdO~Ad@G!Z*Stc7-wB#)Cn=tAKr^3y`$P?w;yp>4tyC73tXcLsOr&T$
zYteU5^F0L+4{0{Og}zjchcCQH(=2I#rNj7UIvh>ceE2jh9noZ-0Q0EkrI!Gmp;^8J
zmoigxnu@!#G`TADWox3t(8|&L{5r+@ay83m!kc57=BofbuJI}W+6m3_AfV-G7AC@r
ze9ezhFkhe<I}YYaP4hYE7iu2n1G`8w;{}KmYmSUTuS7GM;=H9A_3vPoX|~YF$~9FK
zA~~fg(4ci%^F;wfDm2qjyX=@&sri%EAXS<#Zb7D6^J^(&YBVL^fq6#r<~R6Z&T8Z#
z@cW!b*8`FB8Vv=zFKF&kb=5`9I7J+<Xi_Mpa#b^a1lYBjJ^4VX)BNrWX1!)5)kQRD
z;#=W%ljgT&K)I<ISc)MzZfX1^;I?X9rvt4`W6{8FyJqeg7`&}nO#9p}%^eoJxTBf6
z7NFf4p8$yTXbw^W`mQE{p6z>@%WpuWS0ks5;(g7-1;Fmpi0Dq}*Ib>8pJG6>em3-m
zG+*C=`3IVMnlFYOnv#vMJEFO?4*Cx@<4a)hk;c9R8jm&ARLJo}^YeW4jcQ)r2<Di^
zm5PMNH6ekpG@;Q`e9J}an}t4C?c2Rzx@kLphb4FI^g<91t>FT^@YL?~N1vD0K$VNT
zv~9Ex+O2hTQrW7v_Cqeb@zHK)0NYpVSqi3~b|DAm{k88+1_{vqAb@LuT2nL>gS539
zAsMXwB_7NWt<Ohjg=!}jLo!Tzd;yr@TKx^Q_Gp(;+%rO3Pr0s0?LR4SX0P_`XCSgq
z8|7F87o)Tu$6$WHc4Iv3Mr%jU!_ye8j1FbRYPZwV9H-q#nd^A1${l?PTHen9J)r&H
zJdi|f?`2>oY2W)A*vZ;0$3RlF!Q|RO?Rzv&9n#LHz+tM^k6!y}+P`VOIIJCzIzZF4
zYb$_#MC+iL;;8n+$8aV?tGf;JnOZ+7G_thMZUkDk_Uj3V<Y>R40Di8P9S(9#`_62L
z9M|5vj*D<Yd#@Ol^0c?U1$4f42Gt=KX#Y$E^Q89nLbM9C>M5{Sq+Pf2zyCVXifK_>
zqKzGg-=*4YKY*5LpQdGOxfTUmcyhFxY4SX+^_hTc6<TivNTt?5!Q(2egbUZIwLdI{
zLXGw|?TpW8H&HnMtoA9o1J7ym=xugh`$j0BFK89>F|y0rD4d^nOuM4BuR!yv_DmyW
zYPE}RL;spKjVk1?Yd?D%e%ER9w*$Lg`w0~ZH)tciL*EVUIbYaq)GmpIhfUhIsS@I*
zw)#0J+|tg;hKJ2s^B>S_(cVA+V_K`Wa0V>2X{8*fw`=PuOzh~;rqJuRQ=8%n#oJn)
z5Unn)U^_JKXq{*=-K~A;N0{i*=KT+fceUjSuyju=Sr3t3?V@iWa$o!HH_+?TPNz_R
zzjo#CU=C=1ZNyjxwIX`q4r$+}m+=GbXSB8))@mspH{#F^O-JWL?I*OOc%=2b3H`^~
zH=QB+MEj6l7Ngn+lt>=a?xHWdj%#mIamj@CHkBZ`=o*<|y6PT%hoO1so~Epcr_O~B
zrkC#5HjrI9`w}pB>z?ufn78gM3wl1fp%w7gSLb+<0w8|6U6J7W>niDK4$y611++k2
zNh_E^x~&ww4c3j*y&j_bi0WKJb-@$_3e&k*aGk?-&Qv?QM>m@sjnFx<AQGv&N-?*+
zI=|0gVV_R=7_BJXq%4sAx*b%%6|H;d_z8+Jx+EhsVs+CKVIofV!x|Wj*X^XLtOQ*$
z=^xNVtb%Kay8ltqHA%;N6@AINi#_-aQ*^6qfpSo1p<=Q_x`<1VOx2Z8^=O)Igg%;Z
zSohQ(=%wp)G?O0D`O}u?sIL7x2fWG9{e1*7*}7Rd(9hB3P?$MackU)y$8-_o_i<g9
zD?B`*TagTyJl)P`p^&fZdlsz%-ADAfgOj=szlB1fuAhQeMY^4-xH6?W*Od?{)3NE8
zPPxu+3_expx|(63Qg=Orj;2)UPSY)aM)&Rr^v~)#DadzDH=VXs7j-YI(RWGr6iwlm
zb$`zXY0$~#VBXNZk_d%HUEoomHR+=0+{jJcE(&$r(j8n!4}fmoZ*a6lcYxj;t-4SN
z)Z29Nv<Gk3&BScynAV|lrT}lJZn7NYwyr)OGF`ejI`DW$_dabnyLAhS(AT4LqtEu-
z)fLu5|DJ9gRax}vUcU#0`#P^)nD5guU2yUHb!{}30o~tJ{5q)n;0>S*>7J{G<OALN
z&0r4eHp_wH7}2e!CGHblGR^X%y3dOtGp0LC!K-oI<SZ~JbQPJ<aM4fS0Z><cToL-*
z^vYoP<fT{A>u8t$pQX^-t$&uDDsTOqiy%JwOqytX^=l@<yr2HxHPG|dZ~qp|K>Z(|
zf&@AAo%g^E*2|0W`-bS3qyQ#Vf4~X)VS4j%^o8rUM!?b@{iSk<MCdoXfxbxn@Yf*w
z^g|qAN9lW0;NgCKVg^8?^^eQoQ;eS9fD06-_nis#c>QA9-6ZHED4dw6-<^z+CFvcP
zZh|K3AMpWmP+#K-m_vGr2QE#jekKKo)ATLgfH|zcd>gH!`YW_-$k10&!Az!p2~Cq(
z`T_-*+4@Q;L~`^BdQ@`tgNK26OwVY8<Z=D1`)K9sziq?-3-qrxL-M3P#_=LV3-$F>
z<X@zBJ_K&D{#)90m+0@khf$R3YiQqErVnm`V!1y02lSoNZ)<^1r}f!?LZL!mPVf6l
zeg7)-Rp}SEL7`foPKmP`{dyY28U3^m0d`)$cobe-&}XNDT+~mW=K%MTet`=5m-R1F
zbmWRYp5l5}^>=f?tkqvvLI0Y5$p`T8x_)UbNS)s8M@ZJ|bB>|!hW@R$;98@eSpd?c
z|Ir3=Qy)totG%WFGz}unde>WMwdnh3)!(YGy$<i&^q;#^tw+25Z4NAT=mWaJ?bK)I
zLgu#qKq3^o^g9-V+|hq!2eVr*rO0EC{&y-axvQTVjlO&O&6M}+)u;Kvr~7)&evkqE
z$}1p)dN(TM9n!M`VSYp(PMh|JdgB!g;*oy!oAmrW){p0+`9z<&5Hh3sOaT-p^dIa1
zwu?c%8hx&YFP_3BbvHcz9!w8IW*n}br@@7s@iP2F_th@Lq(9KwZ3v_iT5rRwR-pJ8
z*4m)pYnV^(AwNSnEe`z+jA_6OGJHbONJp^YA$@x##Bgg9NT|Vc2wsF4{)|T}+;Bw?
zm^}s+Whf&It8c?nq=AWb^R&H&(=?gvGpwaqI?BLug~)!x*cDuhXu~rUW{WX2I6*zu
zaC->Djx*eS1`6?p?Ns-YU|>@+;XuS$_sP#XqH3Ug(6FExT89kjlq5|xG<(8Yn&C+)
zln)y|qxep`p{4}PBL?ZaP(Es?4F}0EFjFCtY1mc_y(|Nx8DQClEH7BgF?>ZO2f2n4
z3d|fcxTQhlxWPeN-xG#ZI{lt!aCS67Bi~TB9VQA4(`apV(ojI**+Rn<T2>SpUI~X{
zu_5^dkP<_71`L)Oj<GQGGD9k*>B<fMw2L`qa92R@v|*685fz4)B=EP=z&HSuDnsx4
zFj#G9q5};z2EQvHXAC=;4v3yL{MHE3bA~S{lylw?O*^y;hNwJ{i-t;?RWBK`X+pVd
z*mxh3R}6tPDPJ|5rOBq&FnJD~xn@{;8Uwv<c;h5mb%rX+A=De(KSis-u#FtOVVF#%
z`HhA?TFEvUmb^(1!A(O~1Gu*gdv?M^vmt>(d@Y9Gs4A(|z#Im%&F~&g0iA~TX~T2d
z@Yc)d>oRbuZ0nA}l?{<@L(}W%>oNRBKiXY`&)XR9J;NB~E_w};%NXZ<!}+gasLxPi
zz>xY4*@j7Y2nGzHRNyse=)f~EZOAZ2gBdXdzYNibh6U~Ddt|sq@u<g!yR<QUV)%ge
zrK5&sDykSWG*My7xS@I}Bqt1iQLfU(ID_&|u15b)aDm*6XOBR{-T2r8Ef3>|C!n{>
zSg{OD$8O`i{m}3>zDDEqG4=$&gs(Ax2N^%(oIl}(zmZKVr2ykBs{ac#&YlUFAmeQg
zd<r(YQ|Whz(V6btP~+5jKnXK?U4=-v@fj&Z_860<!a{`cA0;FsjeY0Qx7QfH2nzcg
z#!jjii85xr0E7FDn`ng?ZT#PST(%hFCocjm-gqtzeF;Wannw>9zag|lqk9EJl8k@Q
zXU~$2DS_}X#W;hO-Up2@Gk|%>*f|#>sm90*sHYjdd0^tJx3o7&H!i2#!x5t+iedyA
z#%?>BnMOHnEVGQAw6x1M#wmcEV@#pS*Ic6uEtrlOhc1I0H-2jY=n12C6ejYF|CGX~
zd}HS(v<i*y-i4z@#=f&)790QcM61kL#0M!ix>6kLlySWb<2-FV>}ZFH3gbCi>sJ~-
zr~hWCGJX*bQf=h&afND(Q%=Lu8RHGgTb(uLQlR6UanY+lJ8zsqJLe0=U+KQMXf!54
z;gZpnYE>^ATQ<Y|72^l%0DaZ?-c0n>8b6}_;WeWr4q(@f8`|h4RA(G|1)cTA=ikH?
zYA{}+6MZ*~5$iFSM&s5wz-}^rLfN;Q#(?kO?=7Pzr5BrxbK=q0VmwK4p;qGxS~|BG
zf4YUfcH<dWkPhPqJ7E5{5no@#6Jw0<0Q4Q>6biO>8`&+i3F|TT(DLi9v9BB4d&bC0
z!1NkNUWPOGjULWm_8B8)L$TlZ$9(uZV4PA0kwN2bR7^}8G9D!Iz<5{-FNVRySVoK@
z`uO2PqvRo4kBr~Yrt`5e<O)!p7;EnXbJVz5MM20hV`wNY)VNVa_vM5!jtNg)Os@ri
z>1uk>3!-kO?evSdo60N@@i3jFCBLWX*?wFSFO%jX`gWPzHi7Im6=lJax9QdWX!)2t
zW<kW))X)jyXWC20Fa1rcDTonZ`tt-t9D%0ebVCK19F(OAHpS6Lr$S5t6zmN(&82)>
zn8`H}py8%^9}IMl$#n;q5vHgkP>3}Bbp_aaO&*~b{XSDLg^Z(2|L%vQ`%P6X(2F*G
zO0{D#rWYu+6>GA3Kr+tsI)$p^9j4<h_?;3=-gIi=fJy8GnMBhyD@c-QGM%JIHmzud
zXo@L}CeMSWpMD1DA=CF}z@(by(rPHp<a!y*!=_kzO{SY3d<D!SrW_r}QPcS$pk$a_
z-O-n6azx@6$ugx-jy2ola2f%2j_DJsPB?DL{2ihvOrayd&NCIdp)cR$Lvf`7)A<f)
zoHPy3#b63eHGLRpk*RSNn8l`Rw5cgEl~Pck)O7D3I8$a)e2P}NX$CDbPnl-XO7^sA
z6%`Iun9f8&z0y?XSPtweQ@RJ5)u!(#QBY$VqJYI2({mrfr?aNcaFBB*6>Uh*n=&bq
zd%?7g67v^LOJ7CbCDRJ}wJw|HmBZi_(@l5uT{R8Td!*JhRR`uZlaz|LuA4rqhP^t|
z$7$%RH>Cv8oYG*bjlxB|Vfu9#+(y&vAheoHKam$VO)b|!ZkbBO@UYnwPq~B^)300L
zXsc-<olR*oJ^wpE+f8Sk(dsZ2(LSxy^akw;ZkrbGLSL8Z<^Nt)ra-D)={7As0+Alm
z;~kU)xNG__3(b3`tUy@mHI>nyu-rE_)xhCClWiOx_M0*<!~B40=}i1SgQi(&XbqWG
z^#JXGDTMN<!=`83fihwWWkKPgY2#doJTfIxGVHOboDNbvG0pFU!l=nkG21cIw)ZGq
zK5k0f1<?u9s}u%zF$)vmg{%308-eC#F4%!Sck}18B=9iLWC3QE`A8;2cAJ$;LA=eL
zD){STF7SdEzUF*d3;LN~dIiitvxsV`g3Q0uY#D6+md@~mna}+KpTf<;<-m08F?(JB
zH^Q8*28lE~s7__C*+3`7_L(odg26<YmCNDGe)H?IL88s`1|S(@?${2ISaY2mgGn$4
zP<sD>d6FAM63xa!m`E~r$DoyLUXlxEQq0+#Ad+g{Mw_TK^WYMo9CnzOe~!+h<`}v(
z8RkIRKxCS|%)rhuKTWZtT=R;hKs#oxItY>D=EbzwK4Ct08q7R%%6*9Bo2w}LUtm6b
z6zV6<X%x~ZG(S%V`ijgC=p$Rj<{6(rq0Ia;1+dD^pP#}wPnjdu2TY#pa0^A_jJcP#
z(Pz!oZm@ICY`O*c^X3n)LHmMv=Xx+Nn)7Lzxnv%r?dWAQm$rph%=LO)rK{#QxM0?r
zZyI3rx;gtt{8n}5UufM|Z@y0NvIa9Yv$)aC85ARGH1`icugTo(ppvMY=E<aS%RKc%
zjHuZhOZ9VY=JIc0zTJH83`W#pUKtM$JI!Xg<8GT*QQ<+C`GyE0-R3QnbLcU@oeuT8
z=Krn1knWkEqGd&|xkL%(eRE3yT<bG$-i1rhZ~iJ6tpW2}OR0Kk&^+ZTycsgjjYI2!
zIoJ%DVRI`*g+|PYbJ2QezLgEM$7UBNxc0;>?SQ|d<{>K888g2e0Oq(^KMSr+n6rL^
zf{P__F?@2hgl+@V&BERRb$1It48+4Shf4E2E#A-4L+E9((aU$2<xNUi?zYT1gfaPA
zf~#QO&$58ZwEQh@{{^KiT*_|;TOLKiZiwXsZNEb;zfm1cnB_60D#I<odbA=fj0vFZ
zwH#@}K=)Z{C`=J$xzz{P_FEV!P>;4ew}>K<F_zK4p%H7Dt%pXO<%dJC8*gDO!I%;(
zn@+-~1D5K~K@u&eCqR-cU((T%WXs}dKufXwuoujOmQ67j=pl>v6O8b%rGe7i>6T&I
zqa3k3wtyV9BuRjoVHunbl4)6g2gH$M*+Ma<T#KU!Fvl#4F#KG3mMiqy%eQRlf-?mc
z<;yU5(vnNXZH1QEEcjbw*{TO<vE}g!sFzr3DaTT3(bJz}lv!r&L0`G$w_vnRSsE$I
zc-kVNoLhw@g(lZZ%P(E9SLLugm<1Enme4)Wud&p#F{U#XFA6Z6wQSf7>~j{r5@_cw
z?LPtSf`$Dy&@NhbwL$Wd<sR*SE?YXUqIJbmM*-Ap77MMtuUp*jVk~u*dPIDu)mw_~
zU^ZC%cSG`qr6&LbY_vEEKY~V+#fySVH!TS!pxv^h(dBNo^wSBi7RwU4daai5Yfx;n
zC@JmRZZXnPnhr}H%^jVVpVmO~wna#1&butVm1y0u96N_WbX(XnG3*}8`#l);T?+~s
z@o-qOgV5@=csa5mdf&2`DpC3@YbjGSU=dG4=b&X>14M@`9zOx*fu$lFWZ1$kgEJ$R
z-+D2ohnDwNLE(`llAf_A7B3UXsO2A8_l;RTo(hF=OAzH&CM*I<let*m`Vvf6Yvmiz
zbGNqapqeoc>%5cb^t68D0WZ9)u7M!CtWPM#<73r_qUCEnV1cBc^&l<r{H^X(1Rr3<
z$0{(@TW<`)V374$s^<*0&ZY9m5bKobV1`;ZZwE8Xdf_ct2)7<c1?C>B%?8W}Yj-4V
z0wb+jswLcOT{Rzy`>X>OG3+SozK@}?-}*^4JdL)RKf^B)V}0c~NUZf;IuR3R?RSAs
z@zx)B08OyEE{6I6tIQo>iPq~s042%#Ast>xwyw$nN{aQ*ERcg%?<WvBWPP%NK2nux
z{V5MFrdu~H1=<m->R(_VwH8f6E5rJC6k3_qk7$*iWpz+JS*~>j-MYuDiLGcIw=SeW
z$_cB;3iEl^nR##~-`eU8^99xzTB)71x_kv@q19dsup(>YPLN{jcS0~7CD!hPaIwt#
zIR!7utzT1&_muVLTzGog`Xg0HR9Js@K(x|28V^!s-S9rlS6fS;0y$&lQEKU|b;k)v
zp0i$}e9?L9V?NX`SbuGX!bPit#&XFTbP~+V)|fXSa>Xj6=*(4zb@Em;Ypub77{xW~
zsyi6Pb*q|^26fh`Q@Bv|*7-l+r)aP;CPV**RsR=Sjn*B70By1^qOI&r>oAq9-Lh_a
zgz+|8MHCxuu|7j(aIIEnB`mdBcTve_r!}1>^4nGmouTfsI-aG&@!i%ftI+JR)=|ml
zUF#JM%-^&6VwW(j*IG}%+I{QXO)%JJT};*f{np4dfDTw&)<R^^+Pxa;L)N`pq5i<y
z^)JY<RYM;>erTON2!%)1TjjX0kF6V~K=O%|Nz0j0Yo22bWX7#Emw`569VUleY;$PU
z>uQ_AgllfLVVYk(Z1qjh_q08ZhKQGK8NKm#+1Rw!*=<`%`&)0@aX(1<*cQ<m*w<#I
z*pZ*DBn&No+ZT6XH^6q1rldgI5!$Z>*}ngpGI7B+0X?xHHuG1I3AKGm0qZc^Mmi`K
zZfl{J+a8;S)*Sn6!g`P>+j9XR`)!>;a68(j^@K=_P4XkuV{O(#sK?pXQ@|tMb|oBr
z3AX=<Veo)$RVjv)WLr(4r)1mOzo_ay#kR8qUL3S#Z-D3_n;Y$fQ*BQl1WcN3DxK#$
zZ1Z>vXz4cLH0U3(F%n=t!}hBLdYQHvvmlaXoBk@UbGGfthmg#%z3>IVa&4v25IJVE
z(b<{fwsl9*I$=}0042{hhH#o=TE1;7l~fhl3|~T~$hP4$NU`nxa+oi%spx=9scnKD
z_%fT0wu|MqkFC%@Wn<HXe%e+?>%|J&>5Z^kX}e;=(5h@rpQ2T5`$7)r8r#9mP&i|I
zLIrSVZOdrsbk4T>23n5uwvb_TUa+mD6~aZ^3$%s4WSdG=sh4dd=b(SZmMnwlRh#}-
zVAtBFx`14>t)(Lm*KG~7K&Z1>{)R}s?T21~HQ4&zg`+oYgC791(YB8Y&YNt*7XaOC
z`(-=&T5Otsfzs-*t)vZko2{q?SH0c#?*KYGY@bsIv(vWXA6)0#w(74T+GXP%f&Lwv
z_BBX$+gxbT-D6|Z?Qz$3Z8gX}8~eXCm+d>M&$@5(?F34nt&gfo`)x7w!L9+@LP`w{
z+Mf3Y*pSVUw-1UBY^+9r4%?ohZ*q*-zN5iBw1v|K@sVweGOdqoU9A9pVr!!<^r&rm
z1w_Vd=O}|PZaWnN=7g<!6vV~ucnK)3_JVm(aI<f~G&{}RzJCjt9(L^th<MuX1%l~i
zk8x0B)!Xh(xjP@bnqEu3_I?JKe)c9RX7ab6q<c2N{?srW4z#~Dguw*aH)f+1Y?spu
zGsHfJ7MG!R>m!&5v-_R_Gu*zH(qwz=uhQ!`!mfG~mn+hq^&^;j?W?wd?6Z$7qV;E#
z{jvyGeZT!nEl9Ne{cpgGv1gw`E7qPusjxWv7ql9Ux1XZeQ-XcdNwf~wcT$;UqW!IM
zT#F?8@yTc<+rK6+QtY3914j?qUr&IgL-urMprqSN)My>C-~0zCNA1N+C=-`qPdWn8
zOncBu3^dC==f7$d`??n}rW||3Jz(eB)32g++&;wu6DRCp4H#jbef1{j<=aE)i7T-G
z-3IKF_On#JS7?8C2@Dq5wPdi^uA)3-i9L^EF{SqHUqQXhp0tzxl(^h}iZY0&?4#eI
zv(moi92BeUn>NCkYWu*CuzS|7p=afsec?Z_bl(0tWpOXr(@J6Kvi%wQTGthO?msYb
z&3=Ldh3ochWWLUREF22;_TMgmG}!&m0rQ4E^A1FA**~O=qodhAzyMl{-8~1S)o!I&
zYMb3GMyuU!rNw`T{V^^1I_<Bw!QgFs|NlU`?5m%LPj~E9M}XaJ|6v(KdhCDY;mY2%
z2X{l{o_+FpkY4-C&aiaf-bZVQKKrguV4>g6r&^`~hdq!MRD<?8OJQlqzU3#NJ+Qw-
z`{H4{gu*=|_G7eZerPYHwEQEx&lt#K`;J)r%uno7sYGGaewL~}#_ZZMFvsmd8-Oxl
zFW!Kbi}M<)V{>(WF&Qm4=VxiX>+by5EHFKs9jUR<-{mX`g~8p<eVd`^?L16pGJTvQ
zDCObnEL#C=Kj)(lae@7vqv=`%ID2)18R#q=09ugqYe%6T>|FK>^g^7!rhIRx^Zd_2
z!ko(}_!I6tMyrlJ&JUfS9^w2870yLESN^x^-|O5+8_s>srT=H?JHVp4p0~aC?gG1%
zh249%0%~F`i6zFC#FD6q8Z{a<mc$wpqtU1_iij~;iiKWnbfklH5s<Eef)qidh)NL<
zL`6}t1K&Hp@BchLjx%TGojGT3IcLtCE9IjDZT9biPLR!+nQ$0vb14IDAvSU<whpz~
zsfXV%o6Or#Ib*}qE<m`=nk=}8u!&j#5@~bb5j;iN40l8@(Kg5Fgh-4{qXy>jHhHVi
zcGkvP29yMw%LB9tk!VwX0Bn-Y>K=?mvdy^jfJwFao{oU0**v!f%sCs|GIS>0X8Rea
zoVVF`8Gf^D7!k+?n=^9}OtwvD0}OI(jLpF1+VrjjW}eMODml%!DWZMe0-FU-0bOX*
zO}BrMO~xszgf6zZL?1%EVsoe%Xjg64)6~4g<~3!FN^J@c1MQkkQUp}WY}V)yOu3DH
z0(wzlvyX}zuG=Jh3sPk>={bbeHcfO6>4wdmI0$QOWWx||t<BXT5Z2lF(Lt?xo2tJ6
z)?hOlSAt%A%jO~_E*fpzx-s~-ZO;D&)w?z}3t-=5V?_(cW*b2O*JAS>-BqnNcPApk
zdp7^kwr!hDe<fn-uvttsjQ4Fe(>_wC%>t_E=(4#q2Az0dGl{l-x@~SzY0*QQZknRL
zu{lD6r|-AvjfKvjO-vNrJMLeq2KJHt%O1ntdH>*QSh($<K+kT^{q8HE8MZ&D9xl%A
zPp*Lbl>HMZA(g)WbUswF_CK8tVb1<Vo6*ty{kyY(d2#<`y5x)ZANm`@vi*|}1LgMq
z(LbZ@fquX1{}Rgk8>zJ7-Tv!E2+GO!B&|u0*$%`YQZL)iA~^K7{hV@qXKXD7A&j%-
z!oa24$~d^su{G+4-y+*^%3PP&4orZHD%%znxLVuYzeC0Az!h_N2t2Ub591VZVEQzm
zq#n?}{R7gB18<tp?fe7UH3+KYz%M0etU3@)D~iSgj<!%~Kd_IgKDrKURwK0D1AW`!
z;`M?239x&A;Cl&zakTrr936GFJAD{J54#w8lKR?JTnFX}yWLbn6=-+T3FeV@C7(kx
z)-FUZf~N$#7wu3@wwpwTX?9QkgTwQ7A@sb-urug@MW)>V?dNCN#Z!79&u&*TxO}^~
zcEnU@=S-y>7wsN6q3x30w@o0I?WX>MjuzR?`wyWN+f`^luGlSZp#ienLu<5ByTJ#v
z2~lQu{vTMB+nt{SX@#B9PQ+Ac=SDS6*X;`EhOf4>p^q5cu<Jt3LR@2ahVm#k?Y`WA
z2<z-N&=KK!J0IEtZ?N0e2bEiPHz)^t&#sCd!5wy4C+M@&_;Z=Tn;#I&m|%ogt7oi2
z5m7xeldiN|%tAVHbDOy_5>|Ja3kv8oGj$f=TA3^6h@^w5;34c`mZYIWubB1pPOxXU
z_kg&tb8Ud)%X)=#|KFQ3{4)ge;m#zmBg}Wh(??w?2zI1~W|^b1|Dw))!MmdQOQUgU
zo_=;B&}WR@ioa(*ro)=ET4@{etIZ2BQeR*F8gR3}d<lp-PF;}9{kIFY-~2$e+~3Zm
zdCR;P7O<UvqXxDMRE^O2Zl4)i7p}Yo+eKq8;opm&&=$w{Z@Xv{X35D*V3sz}g!zYW
zhN4%?nrI=geCT!jy<%ks%zpHs<kHHz;Q(C~u?nE8U($Bcny$x?|5W=P2tO;RNMfx+
zDD>Aw(?zp>A_vV48cNM?%sC3lrj$&0*<43Y|6dPB(DUcFp%yUMQs<85-@~YiXzR~I
z@$YTxXfNx~N-F0#!icE`^(Zr*cF~V9b?s1aX8P$+s0(vG6MkKpC1HSeWBwQk2zSP@
z7h~bU{PVvr(J*gL!mfph%S0qkn6gE%d&>CY@rg<VW*x2#@jIr$ggmj%V?mCxkq^le
z`zjBE>CEc4!-Wg$O;@HXYw`jxZtO<N*SWK^wFt(8y-^N_L98Y1k_EHt<3M6qOL`8)
zvI{<e!#H*ay#(UfSBn64mi>edIOr4D&nZ!n$o?1w>?F4992_RIL)@T~!e%uCJC(gT
z8un>y9BnM0V@EZ^Z#vsP3S0(jP9+nW?9;!YlEt<N06WjkrA%1{ceIn*xQ5-p%;IvN
zA(#uC#RCYlxnvt?=IFUxT14e?D`*!dkNcELQS-T_DR5E1o!kqULN1j`o-T6lhQRO=
zSE2^YWsX@2gCg$OOps#kl`}eXg}X8uDp$D`QNS+Yj_n3l$`#UP$~CT-N4#a6<s6W5
z&R+@43Qn)Bhr>#4*;nv%ook?tu`2GrrLeE&nrOv+gVPU#MGd!}9+5XWfi{t9xp}4V
zTgM$*3K#X<i?tvP+yv6R#f_jX*+#C0PLAE?o;X1B4)^d4$X)K?Ja}m0UQuSDnTym@
zBDjTH-~vyr+z1cY-{aoVFVn_Z8G^KP*|mV_;9_V2eV@Bq1+J6ZWCVv@+=t6y_kjDD
zZrW~cfbQdmT<j)bKH@fQMB8JoZ7%G3xFru^@Psp`(v+v%Q(Elxa?3|hV&xh4t$=`^
zb1{EH`hrV#L8N`$h9@w5$!#8vwpUyp?Tx(V+Wdk2hWm;3)!uTZR5bpMD^LK%Ui4@^
zhSEWlS^>KhQFI^dQbj-P17@0NFcjQ5(F}TXr;8@E0_D7DYCX;WGeqMaLz*f2EgpWe
zME8#)#OtCj0)SQ}imZWQwdj2j9NrM!qion6(J(4hxGVB4gJy@w+85-$=$sq|4@8ew
z(pZR=e*n8<;!$mYb{0ROop%>;8`TWCi$7a~f%OpU+!@?|p5py`5sjC)gEGgV;=Mn>
z;)2+n7D3tK;f)|U;;E-#kt@!;4EsFs*EH+P$A7;D7X{*flR*l_8w%j}qIej^ds#en
z6e27V+td86So{YSUR@Cnr_WSe6}#1=twg-(5!~ua@&6;h?=|sa%GWm;q*J$>4YV|;
zYBAU!2-0eBZ#3-h8B87q`!<6qG~De5Bbs5*VNf}qel3FqFA(8NgYE&uJ7}<j7FhO%
z^D<!WVAx)bC>#y<(N30|p+9xW-EgftgdTcBw~>g(({So4xbQX{HUVSlWB3adjQJYQ
zDFk=ia1K4^P8jym`}m|`Kjn%}8CFMt3p8B510=|B$Xy774QJE)G{W#6)xo42Hq*2I
zyy4P6K{5=TsbVqH@X<NAzhGEFg_=2rded2G%rz{Sg4ps54ZlX*`G$Mw5L1C+i6ywJ
zhGS?hR$};;j+~Vmst&{8n&EF>LRe<F>ONp94ByjFSZR3s8;nf7;b=L+ZZPbnY3(h;
z@ui5V(eM{ao!&8A{WZ+*8urn&xXDnfUk8|G!*Xw6w;I0fMr`*Cw<bc^ZWucaFdc?J
z(i5iB@T)jjbQyXVL#5l$m}dNs47V<T=3~QCH1X&$e561Wjz*Om5dCSRU^-pmZ&X<c
zVStg~4flaY%PBP;Wb`vVErX59{b~IjV&qC&q@hNI_n;bP^vizeL>RHPz>YNfn5r(K
zjDDqDe6*2yKMZ1xLUtjTIHSiS026OCtpnUyBkntBCKw%A0F?7arnC;uFuJk`&{;<E
zECh4G=wTi(vyJW^gG!E3d<oruc}98k0?s#@5{t$HqwTcdFEo0s!a!X#N<RSMWupk%
ziYqeulV(W8M)Usy+7+Wy^U+pfw2_5DsnP1EK)GhL_zSd^8_l2^(h8$e%KTOuC2R)w
zz-TC)K<PFrzX<M;(b&`UebC27-%|p)$Efle$P*(Cz3O_6wiLnenNfcUR9_hFrH5Fb
z(PhdY4H((dJ8IC#p7s&#C1+S@I!J!aMKF$%l0=|5Nk*Fi<*>x$075$=NvDVIQOWk_
zXgekuLzyyX$x<tHQ12}n+z1^XNgSOj^^<&f2ZqNbmsWzDlsFuM;VH?-b77b)nPv-5
zDUx*BWJ!~ZQKIdf<i#?erAr(f!JU^F-v-H$ETorsrer?VP-ICu>M=4GB!3q`Gh4Ft
zG0bx$BWUrItCtw(f#yjH=>TZHB%f9|1(I8T!oE;)_AM+fN=#{1e@XIj4*e98ELuqx
zNd_r@RxB}|1neskr$Dq_mE53QZHYwoJ?u&)w>Coan&c>5k7bgsMIhypQB)LADfy%Z
zD%T}?>$m83m1J)uBCVEKQ4RPFNilsXtVVLp3BsF_6FgLFB{%32sFMt~f;32UKSJ}C
zq=?qYjgodMAGj?!M5PpWB=hOC{$0rlE4Xix<Sj>N&606+CA3H?&cUu#Vob|`dy*0Q
z1CX{!iVg5vv`exUf^<k?THx@$MB4;Uof0>i0Cq_((uC-N<k3>N@R9C&htPbby`y0e
zAQfE&XrQ!!=0!o$emb=qEIru=5-R;>8o<J&ljC6?E)CrP5+U6!fnB83z>xCKQBunT
zkj6+a&jU=XG=Pq#$4Ni=4J2M_`U^l4q)Db|OOkHg0<>i5Uv!u@TRKP;C^=Hw(TFKe
z`h+g1d};F*U|x}?*8=mpwAmG0m2|~rm{&_H|Cch7b{V6sM!Ld^^3OM=(-VMJE6q&B
znAAy|uAtlXQonHcZII3^fa*PI^evD!={TAIwo5y{2G=1yv<(jLOa1A6&?&8={AQQ5
z?*_ttAYF7AF+G$T(ou{@(rq;Nc`O|>5{`PLKhX>GiF7q`k9zS_sSllo>y;YO@r7s7
ze#&z^msZocyBE^Cba1s#`ZvAPUr8r^0+`p*do-bbBi&5X!MD;)7cnI7q&wGwyq8X-
zY)QX#?GbPT(pOu-4N5Pp0kplbF@3|u!T6WaAdbdg&}>ETWL&lx>|x{W^fAmM#w8IL
zsH4XIQLsN|+(C;YSL0XzoA4TEe+r?yaSg4yJdIcH1LtKt!3?2!8_)BH(8qXLEKq!n
zH$4TmpK<$l;Eo&5{TJ~D8^=@HA;kC$Wqd=8MR;k6!}P{HJ#E8{XWRoDVf;7!_L0Wt
zmw;<Ep4x)&Um1Tr4rul!J{zFvV4@9$Lr0UCcnF<LZr_8-VUtxC5$F+<&IPb@G5L~K
zW3DC_*C0YSlbWA_>29*y5t^PRdrg4iWwPiq^wY;gf6)Xmz9tSQp>xvYTRPBn%4FD7
zG@dq@yba;|n|w--tw57?tAQP4vSKkj1)F?9S-cRFwV%Nt%w)_-7@RTLVE__tQZN&k
z5hlOCfcq$u8`B_+Hd%WRnlUE&F8~&6!jA_@Gdb}UJ+04~d~^x!(@muGh&XSOo(aPY
zlM__Bl4%mO1gcpk-#-D#HaSaodXC9X+APdB89Y^$jL#XYqZ;lTCTV79t1%f*hX8My
zR8mcBt%>p9u&XoK{5gd6CfDdW(_)fFv+h=t1rN}6&m?U>G}}z>7yzZi#CZdH_P}IX
zEl9V?lt36fG`XGte~(OJyrA;LWPdsWd}=a{sxo^`#_NY+NS~P)QM%%#2~P>6S0=A0
zv+&yF-wy%v#^l~r49Q!Q*d%y*XR^;2pzlqjJ#gP|;zcV757UaDK|D>3AHv+rboyHm
zZ_^Q9LFi*zb{E9gG&>u1ex@JLQtP;>!AZD1VLDl%2lh!*G1YUOGJRSA!_%e*=(_MX
z{egi_fa&NIkU&$%MbHc~J!gZ^LQLo1hi0hhUxN^anX>eFJ!5)~7IopK8!kZ@VOmcw
zhe*@XT99bdrF5h(#x#;{ida+Ie}EEaTB)Q@m!37XU5bt-nC_z~P@?G_dZHzn4$cBe
zHoaK@VT!3EmHDQc?xF(SG}BvCfOgKb<Q4p;o1UjrOBtr#ks!`ypBI3*n1wHgrmNY)
z5s1mx%wa$L2AJLWjQV2s<_8Fa%*@?~;2{!hwr(mcLd|A5BGNFkR@$~YV<xGDi*U2D
zZGed|8xaQgk!CSe4w`88G0nivoBg;KB*UyB3<jBITj>drWwzr3pp=>Iqr7Ih+21pP
zQeifqW|OsM6X<1FXO=`CGpRS5Nr@7DgV_L0wr-g<%AwO}79R%gw%No}2=R_tZzn+S
zn#IsZGn&j^RpZBNHWQ{JiWW1kozQGGD_(-=@0r<b1Zg+>m~wF)W*M|Bxo`I61)y}A
zebNtMms#aW7(6o@OIi2lX63ig_CjxV&mEEWnYFwF=u5MQ3&FiIn>+-)cx_ffH{Khw
zWm*W|nsEs*d}p@zQwZOiwNjqF-)t0Z*bbOEzX4}23m-t6gKXaKAdWHvdW$;AY^l8Q
zu&jz+&_`tZCnJiZvVoo8j>+`f|AeZu%ti@&7ugSWuyB>VUJs$0?80{#V0YP}D{${2
z8%q_5p0c<9!q7|B;SZs=Yy%Cck8I*|wE4<*hd}5jn-`5yJ0Uy#zlo6S=nklyl8vCU
zuG2Crdj0v!CYnPSAe*VD1x=vrw^v|;WW%Iz7%Y3&0{0=Z7}_8UlkKhmcScsc8Y<y3
zgJbA#gsiOyZILo=0otNumnXt5TINJsjxn<ID7c7|^?ZfC#LGA(RL;u2`38fKAX`qG
zBZ)GXD4-<CUT>jEbh0dnRuU;P<1m1x%Dz1goitf4EoslmmeT?%U1r>bK4r+RK7nSY
z>`XHTAxk#<0L(AQHU+{UTjo3p?sH@Tzk<t^oubEUo~)q|!CaB4p8@QuOuPaHC9;fC
zj8myBD~%@6H)Pjcp;IHvx``g%l>I;_P-<mk(}7ke^P_$0dRc5f{5Hs%=}CG^R(u`?
zjj|1tkGm}kqY|S#vO-!@-j(eMfUrrnmNHAtvOWI-tVQNbMMbT$nV&<YP4?{$2-{^j
zcC?7?kPUf{#{05KPO#{d4K;;Mm#iig<bf>N1FGFJjt=iWl%>*D@<<jk69$iE2Xzqk
z$oi}xd?L$sguzo;J?ap|&t)NF0ro<+s}ya0vUGYTyp)xeg1nODIzi>N>={iF^>1X;
z9MI9Xvd%NGa4>&n3#p^Ii1yx{%o}O5{;+xHpXk$3^QAP~IA*T71<u(#cN84DnA_7l
z!PR`YJ=)yNhtRv+-F)o`2tCXf(0-t&`KDC(^)e5k<09VXpNE0?m=9kFN3nW~TgK=`
zyhWS{pa~WZ7hsrVVQz_FQY;#5;UdkVCleOw77M5hDZ?UrJUnGv4A4$(okeXX%<oy8
zo`JSD3sDrfb_@Pza2*z_=@+?gad9}zJ1sWS%ca*MhZa!JETYCj^QDFUC=dGD!k;#L
z-&o+s##mTbTVRCVS=ir36z?rq+KuhEa8HDAz@m$4ng%W2B?8S}-b>rB4)S_(=qS&l
znhGbm-+UOj%Psr>?IAx&UndQemrzw_kle@@-42m|LYv;9@>lvc=!D7hzXW?m9x)QC
z5%P7@Xb|LWm9R*bABlk93vv#bJ#n`D9vxT8k<Xt1m16mc8}NHYe#e)tZux#X!&D+~
z{}Xnl@;|47T$6Xk!LCd`mi8#i<%)w4R>;$~z-^^`&l+0vUzdA6g|te}T|%F#<@^kg
z+j13^rr(h#QWEK|{QF(-)Fkh<he5Oakt?_s`3O3f)hhpJJIFox;2=8DCcoMXyLNfq
zTW}rn-ga>J<=3cuyi@*#66RfUKicVeAa{R9|H(|Z{9QflAId+O55JG(gP%g@vD|bT
z?0e*Uzs1k>MBXHY@TuI|2WY+W87pD`On&e-LVGT^=mPgb{@M3H>65>sm+4En%~nMC
zN*+}WmDln)m1uh-54s7>xAMPTz`c_vA@i*lzn6QNLfS7s_z(S}ieD+!?x2|Q3Pa+k
z2%)WeC&ibv7j{_TTLqO93RMZPPb%u^;dff$_ZiUq6|bp~CP-0Z2D@NIdnkk<ikM}H
zH&l`O526oK*j9o&qo|}Rif~1K1Pt^MicOUAh*ad902`$kG8Y3Ct(fs4>|+!^QE6eU
zV&($~;}p{Gp%Sm~p%RI+3OlM;NKgz{gCr_g`eBk3!>C9#S<#dZ%@oBE4$!HJS_UX-
zibiupe@?M~7r1mq4NZN{>lLkY(8COcqya%?DvY&&$x_Trhw25zryoL?t<a@{%TWwW
z2A8Y&iHf1}6slRU&sRw8U{IjwX#{AY;>BvTT~yf9j?E=S8KurIE5^{Ysz|Yf>Pd?g
zbLh;>6~)q3(7dY9kEi>vMDcSibV?N;QO4z(!i1{w$`mtw!IdilXqHu>`0ExdDiw89
z7I$4SiMEET6l>_^R;|dDLi2`V?i8rhD6;5=y{Txq1NXIxL*%zk(L-n1>lITts5B@}
zP~qw=#U%Y-ppA;{DR6OH;Y%~2JBsF^;O;6K{zadf6v`x6G%LmwfooBGMyc6WMUWDj
z_Y_m;fJ&Pptph6UiW`;)twRxEg0}mLnP0(Sr$R$ZrY=QGIfM@sA#@70Te0LEy8BS!
zdQT7OBgO1kMEY3q=VC~E6l2TKrzeUhwHWTFiWQV4=v912zriy_746nNS1jkjy->`i
zJ)J&<H_h5#DlY9rFs~F-$kS`ZQ#x+)MlsnL<gMac%DcQ%Y}*XY_lk4NVcxGW$fY92
z0Y!Ek`a7t&8Vq}TesCg)1OH?RgpT|ZDhzYtqiNoJm>)??_#=FO3F1A<>;D6HjF(gK
zhclmB15g*f{|aJq<wwxMz>WWrjx4zID;p4#2S4^1>^yld+BNp#Gwr3g|GfF!8}Q`A
zABusFFaPgugy_e!h6wmL|AvnIo#5NIz{N>EoDLhG;^$D&%4z;rI-l>)2OPt21@KyW
zi3jq5w4W5j^UL8Wm|sKB>=3@k4=SPj$W?F@#urthFK75I3qkbZyw4s)6Tx@T(Su0d
zI{-RS{7x76jpluq!!U-=JOmQU8wCL^j?bozzIc8KEzZvJU9?-Cz^Bv5Ci0&Mh$4wM
z90|;1ekFa7CWW{81;SLmk2a#x_%E)b?Hup=1v;3n=lB2bKIDI=S55}MMFE{mK7>xB
zW$}JI$OV3p4cuq*Ei^zme0u-_&E-egg3IIg%z!~YZ@3;@0q^@ONFm?74h9$bgw4>r
z#J7BkcrWwL8_}~OUh)Qhi}^!+;I8ocE&syeDxX00vn70r2Bee^rX=At{^~a%W&EpP
zjAc1LkxmIz@Qtwmt>i!W7hSu~?~Vgn6~8P7Ts5zu`~C*Mgr?**yu~Plc9V~P3HP=9
z*dZWw{GPu+>iL^R0Bhin=<Pvo@fQl<sgaKxhsN9dfBk^D!(XO?&bxdhJ&T(7OsXhp
z=HHfpwD5Ie7_{<Zz5#cSS5XaC8^6*I=Iwkp<r+Hp<uvQR&;LQ0&Q3n~6fnE^nb~N2
zz`K6}yKa8@b2>@$kpHj|Xpi`ET6I6>!ydx0hyU<4y8VPdNXh-D{MLQAu6p^&tI)M)
z{4mN`KIf%0L3qLY!~&&{|ML#WOP-^huUEXS1q@#E$+Vn$!~aZ|)mz?}o(b>xyy?(<
z&#(V|2=2drK3E5b1ANj^kU{=V3JmQ9xiMfIgk>BYItq0e5IPChsSftA;KxDph~R@=
z5b;r=H2`hLgc6!WI}0W4z;+SJ=&E)Vt`32@oA6`^dgd<lQU<|8sG}k(Pr*q(1oxkp
zu$hV?yaoP0NPUD^CIIynqCbL#pRj{UUXKffl*c$BtfRp{DXga4%qij17a*sF34ZY8
zFZkEPE<iYX8JdBDAFaBBgh|KH7A!bYHY8E_fesfX313mBC0V#O4J!H+!GkixslsoR
z#Yqz)=q5QQl+$uMUFf5{_<5m_-i8^%VjBdSDg2O&(6WS>f1z?gh>nEcY{8w1PI83f
zMF7new&lYvPgvgzgM48Lr4tJTQ#nYXFvJlC7lldzn3wdz8Y*MIEOh#TEfRdH!4(TD
zXrttcu#M)_R|Qkri7yc(^sp}#D!u@BO}I52F3N=WuYp!Bxc>mV3Zd;Mpi~N--^0^&
zA)oG%D&b3dn^g-NHXyVc!pJ~yHG+alH*X4hn;q~}EBrA7Xmx@&ovEr9Drp(nAbda-
zN4JEKB)Di4y2GJ)TlnuHx_w8eWT1IhFvDpmagz|sK(kqp&jM)?mK*_T6<R1)cu$C;
z%cD(@tw(6>!kE7S)*%c|fy#a1w0=F<P9eG+UF#BlTn@Acf)PDvy79w6_)wVt5{8e2
zTQWF&EO0MDdW7GpI{b<7M+Q`$3f<P|Q?C$x8p3Bnc|N%3g4h*)UkDY{-#%g6IdCt9
zlJ!t|B`l(Xzt_U$33|AHBdntGh_^z-5DdaQ!EZK%?}bz===2NuH2EJ8KBsi?pul<{
z7<=Wlb?BOda(oszN2M{%DxH)YZQ<##@(Ilfk0^^m!5vkmtOWEir7x}hot0nTg9jI7
z&?OkSD!cnB|Kg@BP6M{PatB?(9?IFY3+bsmO)nWQWfAQLdMi&x1I<Sn{Q{h?@<;k%
z{FL`;zvH-a(`yJ%C@Xys(@CX*RxqcOGgRPCD+?)!>#tlm9-RnKe!mdC4^$o*f(V0@
z*^N}h5Ul(!1r9@$Uu}g>sB$$Gf`=)OQ+nczay@-WCtT_7fq)~FtL+g*q>`g`Sd`M3
z>IS2gNg?23lr#3CEmk>h3k>3v*JuG1uM9d0a#ktHfM$Yn5#1_@$`Vh2B`LiW;PlDL
z_(ph2QC|H4_NmIo&k;<T@`LYSaZb6)5<2P1;dDEkS6&$dVTN)cU2~brf<g$hl)(~&
zeL=~1K{H#)Qm#Hn=}!}rT%{#F*7KCnH0t@vv?Lf5C=bzcw@{fyd60{G<<6n-dr4_c
zx6Ebb<Ky6pl%LR7)QgozMG#(5elQiFSCv;i(X|p~2Vs{g<HIrP*OcGVo=BN;R6E+r
zl@Hb6DwO%p;jmKaP6htgm2b+RS)~kqhPG<ur+wgVC<8u&`x>Qw`$Ev0$^~oTqE=Z!
z6UaKHALXm+mF*mYX;6C74|7Yo4AT{HqjD0h2yQEl#zXUta^c@FzpLzufTt#<iq6tB
zD?10#)}kCg5;3(Zt7*slo>J%mN}KXFRerZCpWcCo4&`Y*tpo2XrQXo#R89_qi!Nmj
zJ*FQhe>@D*t<*e(@S$>RGgKZaJ83ELSQ&m9E_#%flrw*#-252aQ{@3KaJ|a7`M`Xp
zy!H_sK3B%l`uc@(3muc|Q%<8IfS1b2i3t0ZGO?ECpRbip_F&&AGpR)Wt@69YFnp(M
z8VZ>A%0pwJ(yyHTDO3iOhiH{DsO(z;6?@e-1`#@_s^xIusQOj~&Pg@23vGv0pUy%|
z$5rE(!|w@I6;&OdRFzIZ+bPw-k6>_Gbz=@~qWG)iRBsTd`p63wL8?7xpcAYTQRXs4
z^_vykhpIlm4!>b4x1He5sH#=44_D<;Nl%38?g4}yshUTiQL42P*hQ;)XrUXU;>Uo*
zs=6ro9H+7hhe5n5nkFV^RdN|^q9mvqD0i2r8cpB5O;U}f;+7Ou%_>-=s>b~RlBRl0
zbu;Hw)9La`SKW9Ha$e;}`PvNCADxIPQ?*Bl;mT5FtD$*8^&911vQ@=YVw<B1pruQ$
z%56CO=Ba-A18w=LxCv;}7pQuuysS{=LYo5@RhK%Tb4e9V!po{{Zg5egT5Ady#j3C<
zgnva9VF~wFRrR!DD^abo1x%^x)!)#(rm}m4zLcqA>H8z)s#6DmS)tO+hWkp@S04cS
zx@s%sa;sFcd_k)9s-dBf-cSitvRb3sM~BgFs(eB~YE@qygx@;VgeJJCSAF*_G#gZ&
zks!BJ(`aGdsM2<U+*Tc-UBEl4sb3(byDB>>wr)~2cmlIo^?(jww5STs0<%?RH4!o0
zQw4kt(x%e?G!ba+Dq}sO=}-;O9P_?v^leyls?t&+>{3mq<kth${Y0R3tL#kS>7i=z
z5(pou_I?fWSk+Yrv>w$5v>JS(8f^mer>ay1NUy3l7ZE;F9q~nI&sAU0d5RaR-Xj>G
zKGkY{B+y=}X3mA`E0vuVA--1WrSSVkwUefdZ&jCQ_We#ZPXm?rsudpqtzR{I4>Si<
zx1Pg%P?cN>6?^sF07U4ZHXZ}cQJp}m4JY+t8Mwph4!YBhsGm~?;;4Enm7yO~Z~u>^
z&gwf<v*DtC=?G9)wHJZ9soiNK%w3&T521$|b)tAHsdv)L+)Hgs6&&8`gXK{1QHN9B
z##cRR6IA@v$12cvT)m3615T({HpBf%bu&eHO8reO$Z56HG#L1+k4&cdXMp-tDh4r7
z-C>Cy2C3~wg9NMPI-rH9wR8oBs-ICsQJDJtbp&%peb5vz;p%<oVHcsEcNtuy`U33;
zMX5K>2N$hAMYUQn>JxPAKUUpujhN!p&0C-nul9@q*je=jB(HG)snxWYO;o4TBr!?d
z^%OeE>TMqbJ4M~}3xY{i7nvZ6G<7$XfSyxNTZguEwVa-M=hYT;#v?<mqb;aR^==yo
zv(&%UfV-f6MtjuR>M4}*%u!D-gI%urGF``c>e#>GPoJ+|gKZFTfqGLSLM&8QL_m5`
z?H&M6m(+Y1(2CVAIDss_qIRGf^%C_*v*55)UAY3GT~ljvU{|JYyNIyM)w4c9TZOuc
zF3U>w37Yv`R|nZZrAmE;Do?A`xBr9Y4RtQ<-q+~W7EWlqsoqIRl3MlN*$B8!EvF<&
zz52&hfN4-O&mp{}R-DIg->8;&p)<GD12dp<SDj2>A!<^4zk{b{_4N0Mw?%FB9k^EY
z&P+hxQ+FN#N}GC82|CfPcGn?_4)xU0z`U>42T=80r`n#1kGj-S+O2w^UPP1HZgtfs
zuz#rjWEZ$c>J@1qkJVvoVA!LspgHvu^@n1pJXO!R3gI*LGCD!=T&<;Qi5KcSPeJ<B
zLq3PyOLZpYYhS7FRU+Qk>do}Syivc>)B5DCx|%*;`%Ya!C(z%kk5q!|S1+Y$(tvtm
zBZPx$X+JdWHGNOf3kQuq&0ifg^V>k2G#{)(6o)luufgDmCX6Zpk7}mRfWu>&wp^$<
zYaY=f$wgy32`H|bUp*jn(~R$=#kadA>jW%3G={Xd@2P34LZg@F<Nqy-G&3&1&_}cE
zF@(OF+BO*YX*PU<2#;$7n#P{cNa_&bNlh99_op=T=EB8k&4x?h{56(zwj@B4zYru)
zV?d=ML7GIm)`B&*vsv7KAsVAU;679n*M}cAOv6(>$QjKa-+~L*tep(^5t{q+!9{9X
zsGu-Pqsl`t(V9RpG-EU^LomRxn)(3vjnh1u0xn)NzY^rE<~GfC5;VsDqGySkSTRVF
zW~&Ho$(n9lfqHR@W))4_Q#JMxAZeObT1%hPESib%(=|R*z@69p^cA=a%>vp$$kfcE
zdn8MfNau1dXeQFB(`=284|<rRS(*XtT+LKE?2xDFrkqf|Mqz;t7HFo}L0G7%bVn2y
zH6_J>)?d=p24VCrYv$|WqDbTWFG#WG`*bv3(G30#a#f?InPZ7&KAl-A)f|k1-)ow;
z?uepH^HC1mmuo&>46Z_BWCxW>%@@h=bX_CRlBr75tb;+dCL{>K+|XoG0cDM5H%1SK
zNHy!|ENZPLigGk{nk0Lu)@wYzMPq~JL#mU$rD3UPx=~|y4Jx-a4PS!0qe)o=&AXbX
zv>)B1DWObjv&LTsyB5t?v%$4$tj9s~o@UrX2-`H{#v#ylO~was-=PWk2!qh8(f^i>
zpq^>oQ<DF==G`;|^FpKB2GXawLyyvznxeTNuQb=j!P9HayF%E%(d?un-ETFsI?(n`
z^N313-)nYJg-*Zb6s^hzG|$ffB~hD7nY1Kra28Zjv=(E~i8SpqG1|^)BlO1+M!GiV
z0;K1)Zf=lfXfM;kFH74@6R~V<9;NVdw8M8pB~N?k0MPQarCT5@(3%_3FRD$Ym&`@2
z(++@L(yr+TxvV`H4q=gYD_zdT+I&i_Uez|!Y@<XwA`!uqYA;Ll&?(bKeGZFq?f2KA
zTA{r(48lt7&d*?RUF$(9^eXLaN|{t^|Dj^I8``B-fT_`Lp_%SYtr2ER;#%#JVsLd@
zkqTkgYx9#}(4ZY23gIp7tCg^8)J~_g({1fJ8rVD96+3DEc~=`xhlZN8pHU58v-X#j
z=vs@`m`6+<+NreD(WU)>=Ial%hs~kct(}k!_YbvYl=6S1{fBO~$J%rB8tc&pyTjm#
zR=ozAz1rc!0QO8PP-^G7_M0z2UTB+NLD;9wNToyEFST!9Bj8usrS!G8*V;XFe&mhz
zFx9lZ)z%~-ig(&?=vsfT?YjyW{n|BR7z}8)SwJ|boi`Jn>~&vLZJL9wS%Wr5-H0Rb
z<fPLq2H0Vpax-E&qBDL9m7}_dKY@8nS3etVdS~5*(@=HM{l%j*uDYGoaN(xY`9SEd
z`;vCoJalc}gLvxZ(uBxMS3=c|-nwOb0P3sDr?N;t-OHsgIIbI{t%ei2#Z;?xQaAf9
ze!Ek;1ujrIt^1eWD*n2cH{d8h=dcl&fqGrpTA&5#Zv70yVBI&A`U}x5o&;g2ZUf~S
z!*na?oqk65lLUt0y8mtgJ5nc)z;H$BzFdy}M(eC-|1L(iWf_JfR(FNck@32@R6UTO
zyO{`2i8>3~=1JCdZv;uv-J|`iRGohMdH7A!eH#w6bGigtil^(|Rl`Mw?hcJtrf%GC
zXv@;so1pE2Ziq9Y$ktW=0?-_t$`cXh>TZ1olssLwAGmy-Xe7)Fblx{1EYztr5MI>1
zr0m2cUF1T5UDiGFL!d>vWBOB&7VGQ;^x}$6^csy<bwN}yQ=(f!v!zm<*c@$TI@9+c
z<vL$C7*yy!XAxSZ4qr;ZJ)%2Bx$7$36e<;~);ZTe_*OSO8eqpPGbvZ^V!4k}oUWE_
z|Do-aWjXD>1XwyX(EKylvVSu=6K2U4!f%A-gfe)FwVX}E7H8R24KChtHZ5<?T6WQ^
zBf+wRp81KEf6hY`NtPSwy_;<5wVp=S@<JY>NVSZh$!wbCA74WAoaN5l@SAQqlxoY)
zTb7LlW~OE0YP$cjEVoRD^pfRhTKZhJte`@Y>y}sk1zMHm{M%5iw)|@&{NAu!IU6c9
zmR0K!%uUN<3(>V&%eMF6>MTF214_N+*%+8NSbD63-7U+z1qi0m@?9gi+m^QU$(cKr
zk}<HmYk94m_WznJC!K+`*|KdY3|lPkeS^-lT5dcC(0i6wXu{lX8E*>g4$IZqKy$Lv
zcS3mBN=lP}BUbT$!tSWm(|rI9vP$?4cEMIVX-6l-Y70%}L#+}hX%=R6Y6`eBRvZ7f
z%WGBH3E}EUD-9i2jkfx=5HQJB<r=t1u^Q8h{-#=Op#y<wRww?!&vee}66GV(tv;gz
z2<NR>n)zi|)lf#Pz$%`0^9!v`Iil^N)s|C#)uOnooi-dRt;(r3y2{GAmd4QPt_f6X
ztQINZzR4<sZuDlWZ}NcBV&zIZ2CY_a)&aWB%K9h7(r$&KNIbQyY-u<BrPXh9p!v#b
zZ3D*OwUyU){2*_vbo4xaXJxerD(|f<=-5QR)giqJ*a53)hhT4S?N5(T2kYc3P<6EK
zoR27+tfxDp?XY!67=%Zxm)=Epk6J6%B3@@}VGY_`to`djT&)k;p)YRM(}yB#ck2&t
z!N9}%==bpCY5i(CI4|oSn#TE9N1uebueECiy<GgPwcFtLxOLtQ7@n}k=L7I$vX*=d
z)l=3FDZh2vx_u+s0<8Bc(X~M9n8h#%wl)h#TZnZerKzK>U;Kr(80!Z#BagG5NmoF;
zb?8u#1nVR!aY?d1ONoGF>$(i6q*yPxMw@G?*4~tmOS3+00?>2TQ;$O@-5N(G@Dp19
zH4|+a)@fNFnbwXQftF=mybXhJ!Fr_yggMp@^mWT3Yd?BA7hC(${^%9!K^>yMYW*2K
zt4pkd=s;MhwH;ju*Q|}{4lTDH{WHB>Dy$=e&{%1`s1S{H*5UMhhI(uN6Toh^9-s=2
z7VBYF2(8un16s4(vtD)=W6@^4Y$_bKTW@QDd586oSrFd0mhT2ir?s4Ju`X*nIm{ne
zPhA9IxAkx;T6kzZtpS>ktiL;eDD>V#Kc69mEBqNXZ!f%zKC}UUe|*IcU36mH=zciN
z{6Ghujxc}K(vQzfq<7pgCh-tBXQurWY+aZ}ddavlpX`ATH|E}A(GY_`=69OQpJyI~
zA<_)Sk{11$Oz~XAmc_WzMWesK%%V@eW-|@P0Gh*mcn~_d%tyr_c})Ef80Iq%=tF=7
zj2%7D3z^AzFu2If_!uge7~TckWo8QP@f9(<X<My~k^eSih(RY4M33jgtXC7vkFYC8
zz~NC=(+A-(b}H3XIP2NlR3Gocs;Fqgl@;iP;Kp{?LFmq&`x+J=?7?KHda}_!0o#i`
zXpBC2vn#2j$cNSXBMM(O200~zP<Bo(x_y)N!gAZ-C>KZL?Z(YVYRSNdOZo=TC%MmQ
zQzDSdF#q4E<NEu;rvzT6FT4r#nZX`VnkAv>^VjWZfL>WmyYFj<wIjT(a;jV0f1WNv
zyJ8neoSEsx=$jk!8=b<+WNPSgyTrr{XQ7Bc`~pif4{$q1!0908B0)g*qGy5B15u|b
zosjbp8Q6h6V>q9V(S#fBqYa7(!@?Z^j5IV|4f__^@M@@Z%97};NRO<8Qb>KWVb`Gf
zUUqOgI4AR2A0S#+^N*?c%*R|wXWCAihwKLzYHs{1G^5SamjWfmynZ;Mh&A6t8`b(a
z^HxfL$D7B{#P+Ot{%`1df_Y;p&=Sqp9EE+7`Egf}Wb-U93{JYa(`IPqm>V4dxn%A+
z4``+4J17fSWj=B_%x{^WdJD`(^I`Eoxoz%i4(^WmpF`pPuKDGkL3+%uQ~Lag-h6Wj
z*r(>3D5uzKzTE}fGjqoTIDBq?eGGc>!aRYt+xyJZhr!~d`AQo2SLQ>gYj4bl2f+PX
zbM6nQyfdHw48r&3w<%-YZ~mBa%>(93J7F+ret#IC?JefgJl?@#empcCE%ZB%fjwqn
zJ_Rt&7Vh*@xL90tfT62Jeji}mERqKC!}wTirWzVwixKo7^s`V?oy&2Huz2`AVR7y*
z&>}6Q2{f`6R`f!Tx3IhpgH(%k@8CY&;{G4#V2;JUZfM@II4}uqcP+B?1lnwIGzg@{
z!ge!Ao5jjK=ytosO)WgVvG}+f*N(kBMh=JWa-Qb%9&*!LApUYoD|iZ%H+_k)W8^9k
zgh}%G-7r5d@7xJbx$;d*5z}S)7TVIgChw<$xN7-F<DuCg&vGZWS?)&}#{2S3DbRT=
z|Kw-*eId6w<#PuwNDJC{a#e&=hQv+bPN^7o1xwjl55;~exbjr2rT3MWqILs1>aF;;
z8k~<JI0`Dhis!9x@240$34tD0gxyBl3B|IJusf;vbsoS@DbAL|?zCb=DTI-VF?4%J
zDJETlL9`-9UqM|{tZKpN#VQt3{vb}Vrv)(aip5(H?^(q;0jdd#(rA!G#qw{VlBDRR
znxABaE9Dzg6v31_N>#KUfWtI}J5^zwQ>=UqhvyZ%4>U6rk#}I1sW@5)gDk~kT1#C}
z+&N0S-`R@l1~|-7?5Fj3E(%<rny2vj8ePj*bkVA@K(T8x3=0)gMndzV;*B3%TvD`_
zLU>tWJ_dG03Kwq-NtI$=2)b0S`1Kz^Hz}MPV9=p(9Eu1ZDMow;=;sRE1_<9N9OsFC
z!u6~Ot$}L4qH`kb2NVJMXdG13ZH1~mpH1JyaOX1&q2j@(hXdP_H=P0%FJ4X+c;0-{
zP_+5*9W@vrKmNmC5z}$L@6<m{j86Zg8RlpBO;qy}&i@z+E`onRpO}c`-^_t9iho%L
zgJ^zL5d6jPEf2uO^0ocYjORB5fji5OiGzm({@NsrNFr|$2}eo%VX6a4<|lMPGld`6
z1(M23{D6|p@0McFa(EYg3+(gx9afMQ@Dd`|_<w!?Oc@_v1@{%a`E(do@?)tUp`Ler
zjSe>O?t##3<g;Sn_cs5Y?!tC{q8eZw{2Q9D-REuZf^_oJ9zmsxSJS%V0Y8H7>~4M%
z)eAr53nS_0eZ+^+8~HJR@K0Fu@IQ*-=?P!?C8BuBj}8ad%kOG~-)DT?zkqqpKc&QT
zAOHJG7`)^YEHK)yc#E0fUh|&ILEiB457EQ7yh{%PeaCxO!qIzPOeF{X{I1IY8{i9L
z=>IAj<Sl5nYcEXx5rz&zQZRHJ1rI8YcM@voB0VhpRe&}RfwzXxQ`j<q(7Xg&+V}Mq
zeD(m%S8(4zKd&ICs+HqHnKc4EAtccXG+f9&1cL~nj#MHApCWKk!u^Ls@cxMw8cqN-
zMwm<0YO#Vb{i1O~^Gz7W3#a1|{#l{I3vCI4Dh4D`m|TNkk_2rVLQ58I)2?}n@IBsn
zs8I+GfeMNfCIB;CSkVFQyzu!ra2bLXwPgzT{+E9iW|N)%f>0HQNVA21C{LLqn3Q9<
zbA@+02=jzLLl8y25KcSt1wtYHqJ@IzTts+LxIYfUOF}W7X}K;4r{TUzDBp#)8$v-W
z>}rGqA3<0r3@D&dFHCs@?y)c=48zqU7>)vYrx)(iA=dZ8qdRclFElTKivi)&B@hk@
zZ|L%{S60grse`hd=K7Ax?soWfQu;2z$Q)Mwy&n#bC=XHE@2Jvq1=@}&pN;~Uvod!i
zP+XKXM`7-&^aujyt}LR#^H6?j1fi!=Z@e0YUdj)b0^3_z@i7{GlsAij?W<f?hc-Xu
z215vsE1UPDPbZXzX+C~Z`G%far<Bti0D4;KN^3ZO<zmeGu!r7H$0GujK2+Qgt2}cW
z!Z>9Po$`xU4z31wR(bLeevt&Fho0V>iAvK6uuoPxXTvY{xha{Rs@zM<%QWSVGDLAs
z>Er`X>B^C`UJ4uchN`~O#(i-R!JHd+khYJV$2+Woi-rmJ4dJ47LUle+`X?W!#N@!_
zQ;`t*PVu01%jqfg39$2@k}jjgb>NgA5`dOI<zXw_7frdOf==<2?8VS2pK_V*^v)@N
z(DXWX+WYHNevCict>}{6F_emf|NQ6^{Jk?sf+%*K?Zn^v7u<lc?G#VIA9zaDWcG~o
zGr&49pU^tjkx2}Nf-9qs8U`3Q#)S$BJ(yUUX`WyfQJv69X7w-VYY6jiFi=971uv=R
z%n}Z5vCJ&W;KeatQh8H6Ghri!>MWy~0?>1ejE<P6GZ*R7$Yt*T0xpk9{s<(WIamj~
z0w$QsBTAVlJ?%hWW8@70En_Ng!$mpsc_A9>m|-6St)7`+fB|S=5{|;fEoQ7MgsqI4
z_G#`h{5+60rnm^^?aY@G(8CVK&jFbCnMT@%>tssX(ALGoyocWhOh+WzdYPnW@bHWY
zJ3*81=gjw%#d*ODO@VzM6J`OfpUIsLivecD0u0a~V-<%e?Aa0Y0(M{*Q$3<1>rJx|
zC$?u9G!L`83FQcj)3r3szenrNW9-Hts5rB`=yl=3+8#v*UD>uXAa3lB-_rBXoxMl<
zjvj0e?UQ=4XUBnfu{V7|yxFz%#PeZaj0NY*vNSpHV_#Yz(BteeDmgyEZWcr3B)f)6
z0#30@sH*uidtn7!__Hlv!EXRNo=VsQ*&lomQxKcI5Mvn3E<-8_Uub17jDuk`>qGm=
zG3*Bg2qu|rq~}Qrd*m!EQrTjv%1mQ-)2YR5*0c-499B=+iCp%{9AM|MAN~fv`K%F@
zKwM${)}!qzyTKirC2R@hu1eYTy)eJVezO>%m9ZB4V4yE&-y{P2Hv6U<hIiNnM}c;i
zP5c>#P3(3`vbVDK4`A5Nn$Cnp2U|fauKVoP3Ft*9oAv|!zU<vE5d8zz<u4d?v-YNF
zd&rKfMw>nNW<Ly$aqAUO@#N~Q;qL@D`fCV-^xVjP_>JH~eu0a#+>KF?CUD^qAc@?-
z2t<*@t)&veWNwgl15-Ey`iM_1=SAmN^SGImna$@4hat2A?nXUS3b_Mnv|Z%J%HaMo
zH;vu}MO-9hAd0!1ERZXlgx1$rIej~A?38fc^{~Im)m9*i+uU4hz}(}ud!p?DxAboa
zpK|_JVDXCkMhxr$?#op$I4bh=K=j8%&I4$37RAp6=OU^ufeTkr1)cG66ZIp9C3Y7r
zoCof-NY#gU{Y9JTxe*{z>w5qbC@S~~BuHdT3$tL6+XCo>h%Ro1VVJ0fo)Bk5VbvIm
zaM1xeu@@oQ(+d(QTKO;9qD0@C(G?_GO$7#NqG>Y3dqI>zWjBQ)_pcGtRZ)8|%qv9}
z!+}{Vx<S|Y9nn{VbhxKYq^5%a4@LW=(0L@XtB1v7QRxG4J)+iSfO#T1zX#oZDw<7o
zGrgiCyJ7H5bohHX91xxV9#IU6F1&)Ky?Bt;^A6%~=(Xx7p7l3Ea}wJ|!Qil1{5vp@
zh(|}E_s7J0w$uIREZ)@tRTr@|6lkvEjZ{?TCbpudsk_*oCOjVEO_YD}6c5lbzEffY
zd#IcizbpagFIH0_e}LGY;tdohyU<XIlWjqQ#TuH-go^(*fo7O^*dIVSBldSd2gAjI
zI8LJ%M~IvEA{soGOaK!l*3<rKl6cV#=p>7GP}VF(yl^JkQpHAe7(NZHAm{LZTfjxS
zctaBWo)<GAh&NL_eli9jOT3wuj2FZ~v~`p%{+=eeIpXwhF*3PgV`qTni6b{bsL#iL
zs|A>=;%9H*utaQ^3X4*)4uxm<Y{g@$FDeuFQLesRyqYE#72<sjP^lDWY{YMPU3_&C
z%&WyMbwIlzp85e?)QH~{BJ7*u8BZXr74OXjS0}co<5KnFhw~6`gE;?3_`9VS8~y?8
z`&eUubc(xaKdejq7frGsh^J<vGu`6(RQd5xTx|sG$KnZO-y<I41<fa7mS(_D#k=V8
z>J=wnhvqY}e<J)2immM-v^O~9fIuA#&K1Jk(V)*6&`t*X_o3~ufqwKf*dH+n^g@Wo
z3=~vK<ZKZ82-q$L)4l@dYB04LhHeJMp90j~z-}iv4}(xz)dm<G69XpDKtdCTAOk<l
zD8<1BTFMWH7!=daN~l3MrJ2JFUQ;Ff8G~w9L>OUEnhoekgNgbfV51C9{RQ{Y2IH2(
zZ;Zhn+JK8Si0{HU#~B>+gkiiv;svN&GLSFA4}00*9qpr)8-(N|`X+-vA3@k`(2LVz
z;(h~N4gAI$?hON2k>QhH0ak2y!UMuPhFh;e*lhUF4d&g3FV%X))@!K9gyCyLE*)rZ
z4F92&l8e!T3Rt)rNoiO6xY0KWa35-9O*ywzqbe#Q$TdpLhTkHi9wmf#j1+W`rq^iC
zDPSIx1g%BeaY+D85W*!7#E2qA5=`0g^O8*psFX@lM^gUtn#5ru4Be!+>1d&+bk|;R
zUedoAaNbf6TC(~|C7&Q*KdGK-oKHwsYy#RzX-*%)4v^N_LNid>L)9oj(qmmv36Wa+
zA;M7UN=rDzHV{2YBc*3Gu#1ugdVs`ALnL&#?yNN9S2QL`ZEInlDz$e*z~`jTe*|{A
zbk!cTWk|m|4i}lyF}-NZk~YwFbwTPyw|JTKkrt#v`jWC8Rno7G(N-hfk_H#G(v>vn
zte3j~hbV4I&F2FQ%j_x$Tc!1nprUs)cKaLwA2z;!1?*AdMU-B5Hm=%%;r29^?1ieg
zaceTjabpYG-aTpD+KVCaH-1Df;~?WXPiQ)bKZ3;p{JnDVdxW~`6DrVKZAfR3*Bl;?
zfB%$6nWdk99)Rsyzw!9@y5KPSLi_rO7l68<`7~T?oU$HnHwi=V_b*3iPPe&Hhv<Gi
zG74tDX_C>?Ev>Y4-D*t5RW^bxdb|HWT5a2o^Z~+wMtXnSRm=wFKPFLd{O|4Y`1gO^
zEO7MI=Mj(tBct?~Bh$Q>Hg}vD8!aq7m|-{3=*e87$G;adW-K^w#wGy7pOH?4N&vHE
zInV={nMkjSlbK!n5mhGh@;=ZC7^92m)K#W{p4-=%IA6p68<z5s_(v#PUxP5h*t$aC
zonf`KYZ=ZO>QBO11lxEMk;bx>b0Ljm=R5*n61%P*K9kvOsvbyTU5(Lpo^@csWw6n6
zK{DC1M?kXJd@BFUW4-7oWIj82G+Y$0OC2$OMeLNFa9_;!ro#LR`#}jb%h(`CxGiTl
zNa@K|&Gyo3^aks75uw+xEKQnjvduE+++yp#2G__Q^#*sF&7&I27PfK_q?KJvvyOXg
zE~Qu6*hBxD1+%;9dx8(xMIQjVn_WQ_lTX;=1rWYqXL-Y*kL{)X`j_lwTPp5)$7(->
zUwiHvJ=va17&nY#pLA(2ZG+&?023Jv<3Z*ujgCG0Hyu`VV3+-eo;b1@Wb4ERq{G``
z_UCAjBkURp+K#eCRMmHkoxK<1;mmG433C@VDg<q=>{{A#abxxCZUN05BM+w@?5k~X
z=*ez)0*7Ag*L3K?pVhoTv;pj!G_(b>6SL74!v=K0Qyk0Q{9hUySN}R%2d}DH1>My(
zbn~uR-vslYHc{Eq&*z>)zIMDlLRdGn6$tBJKZaz3K9Z`(HhNR->86DTVepH?7(}$$
zg?6NVt*6!aZ$Hx3{1%^L82tV(rCPRrKM@drSUJLKSHRbBwl{+|r)`JPtMR~hqai=c
zG=2x;BTO5WJs)MJETuj%`dRSj&D^hqx(_o!FGEDW%=w|P2xQWzm^p~)YQ+!*Go|?m
zA(WZ13&L>bM{*OzJTL=^W&V2(;aTPo&ApSDu~avComoeZ+$!cIRaI0oz7_CvgIPf}
z%{5H=HgFA$Fcao?85dep-DCbcK@~OK%v%PHeM~1+PP}CzZ$qb_SvnSIgG}C+z;<9$
zKLkuD`@#*v47T^b|67I%ojL@0f$5nDn`}nC9bx4#j&FdM%Pi5LEsvQy86=<igF~+h
zn8|biy^sl|HFhbZ|4e}ht}%P*vnXYZ8(kdbOgU|3RWM(Yu#)Mv2f5CCOob#>%rr_0
zv@wa4ooZ)xEe6-Y?0E!~9%c^h>^xyUpfP^UtfQy>8)nsAfH|_4G7yCm8%}fi!)(t!
zMB%}X(%XT0vL{!<uNV7*j)t6OLr;VFv#GN%xB={>dXNbAsyEz6veRiP62&(504<sw
zM)haO>~HjVOkuB2f!zi6Vl#x<ET0KaIc#wO%yZdq_9B>Kc3~rgSJ?DG7+ht~{z~uP
z5;lVzR<lOG0{aI0WH>Bp*aUjy-DFc}VRM)Lp$u(JtTq~L&Fo0JQd`)a@6guD4*L`X
z)XkzGkQO~L0@@z2UyO(FF}r9vNDtdXORpzv(}ysB%KlBeTfJ=XLAw8+v7ILo)N?j-
z4H{ptwYK2;*rr+p{E`i}LujwqG3^NSH5;=XU3<fRK(pz$?Dk4<?^s_d9DUEu*a-Li
zY$BC)xpRdrFbLp^X_|G0bJ&T##B$pxm{e~136NrLaMS<35X+@ePUJBs-v_CKD0&w_
zgGGJx<0Xs6PeU+;qVK8zdR?^WJ4DzdnzSEi&qe+8a(pLBO#8n_Ko!0o1EWUqBnhdB
zzoF@Qi+JcxbiGad_%x92<9oPJ!3RyM;Il_OTu<|;XW|xjsJ;@1u0_yq#SJ6C4T^^u
zLiMmg<L5)rG5q0mR6Mc9up4+kd)-3gx&R}<Z1AIb^``jqX#L}#Khfds>s0uAUkd%Y
zHaqI^@BJ4Qz_k7Gb6D9kIqB$*1GB^47~}849H9LySLQSwUhrjx>;}Fcvz~Hbfy|3$
za6!zYb!dxZdMWu5#jG`k+eGFi<%yG+kkQagX0FzwEtBzkf?%>3V|r6wV9xl#JezTQ
z5Az&G^b!WSOfBV5@)*f^Dz43Ej1EAjfT`)Hp=Q<;gIr`xXjX8ES!D@wnJHWa>>_5x
zY}gkw@98;ng_%Wrl~)<lZBQv;PEvxolvzQQuh$r12uK-|djNr!Gt=oJs$lwPr?!&$
zf)aVxnL`(0r>|lzHb7d<tTY9C1Nk8Y)5u)(#?aknxaAnHJIpc_Jl$nh(k!`&S$H2&
zG&5Txpwh{V8V>9(=GR}L@_;$(1M_aCj<SOfnZ-K*{fId)0Oc_waNv5F`}B}VVIwvH
zEJM%!NDq=Mc2omkve{LXUe9G+yrEji`cj?OW!7R7I&+0>r4@fE>wO)D<?IehkX&cS
zJb(&r*3B?zWIuF*N*nu>POsW?_1mZ{0)K=l)Yl-SJV1h3$px5(uzvwak7w#H`Opqy
zL+8Nt8TQm61QO0ZJOaB2_V;UuE|ML}!e<nFuLjPd**V|BOAI^rci6?U=c!mKj@8nG
zIG%k<^YpXq9w{^v*uJ~aOk_Lap_#<)py^;T`^*fEQrJchaQaj>e=i!-*fRr&EtB=3
z4c9`pB?K@R*(H?nEoJ+uqVF2}Z3BWSW9yorQqF!q2V-2zmh6Q4I(7xkzU$e8Dc~B|
zX4)ujVQs%gM_bt|bR6Iwdy$ekZR|T6kaqSsrQ|#G?4fCBywAq%f?+2+cnv{yv3_e1
z;sds6J7BumbCfH7$PP$=_K5wc7@CjSRh0hjVXtSR?Fsu`6v!*qnx?m}+3(^I?;CbL
z)tkO$AJU@k9UJ!y!uM>!6=?Re39~>3SiL>cUgD!%w>8G=7<ZB$nqJ&UdU$zr*{jjR
z)0{*F6@SjD3EUa(C(7-Fb7sH6Af9^?h?vfDc{Fc6$2HN;OFEa(2F+aVI@O})ai39I
zu$X&Vi@sdpjH#~aD!2I*G^;o-y#}<JyG$9X8{ENa1XaT|ZGh@cuB#4hwH*Hi+UhvY
z2Y&G_QeSv#;Fg7g+~TDFL8Xx!MV}eC%{fx8@DBIO1CYDiNoSBIj{O|N)y!GYOTC4g
zN`=p@oShAX?OaZ>9<g<BFBbylKBu?@_nn;gEcCaVQ}+P$AvX^t!1&(idwTyo=C~->
z_i(}kkY3JwCCD?bWIeE-b0J~S?C0Vf(QSLt5D^R<L_g8V8As8I4IoaUum48dVUa1N
zW{-%*CeZuGS#;MFo?Jwp-(hInMGqbz7!Of+IKuZ7?WHTwOO!}=j<;yU-)M^y?VN!?
z&xu?vz#vy-PU(drkzp)U%0<tUAbco#K@}7OV%z(O!r35{M#kOXLs~g`8f4@^<)lHx
zogujY0t^~bAq_OR?g&po2BmuuVz9wZ+PV)h@VpPuFoR|}0uDF$el`M)G|-s<G}_?l
z5DLcN9n}HE8(cI6=vjj~v?@z5nAZZkM1zw>=ytNf^FojmgIj*UOf?vF=>KNc{8yW3
z{MRJEgXvFk259|xh7_LGF8LYJuj?I&sMmk|4RkgPTY$fR|LrM&w$Ad$zqiHj!oUCU
zr;5107f*%$-j6MTvu`~8QZ}<r;_v-CsTSS#KkC^(75&gZ%v_?Y`3UolrT`v{e)f7A
z66TT#V7wS*1c*1&*NW(Un6US_O8gmTdXEM$c65gaGDh@73Svy?8V_bZxDV(Q=HFa+
z%VesZ0G7vu(+v7DQ~ei6DI*>QmFvtGpJ143nPcY=<87vy_Id9y>-6o2<{=Z<0qIK|
zVgRT;n@aN;A2x+{7tgTS$5;U14}aDY0&k{_YR7z-iIfueXOgJ;FMvs>1IvMo%S4bM
zre`YjBbil`p&7+k((5OYN$^ADNzA@z7$h@a(tI#Q&rIKp#w=#se6Sao!&JPL%?#~;
z@G^6eHbje<h==H1Idhoa7!}MhErfN<;3Np^nG`ze+swR(2iL-cQ}t6TGlvQZ?lF6o
z0Oc$@Nd}b!c5D}266}YRqfKHh%AlFd>OE*-lEU^)07+#}NI=rq<%iI<GBzq67R{{j
zNH`4T24{eTapAwA?F=`i5-!5IMI8J_aCIMJ;3Bz4bl@Y3oAeRvqPgvKCC6}0|F5*G
zkBZ{D;yZ6<2cm-O2NF|@cv>;i$bO&;M(vTp>Y{)MEFz-IvaGlYyIXb<Pt>9Z1+1nT
zM4umtVv<rK)@TT>wNXhFG>wWj!LOi1qo^^WN#sMQvA@f)e|t^?%z1Oa?|sbdym#*%
zaDk;-OpQQ*ABYcDz?r?`xzTWKqx7&S1jJ2JGVK}Pk^<;CTP|f3AkfWHH)S#_q_J3E
zDYr;BsZh67vS87m<dTOvk+(^sb^+Qh$<zeDLz<KbyE~<^w8~g3Uy7sX<r6O0-7imk
z1yHS=OAp^e@<9~@4$F6XiV(#o^3?<2IVQIzz>9jhlRlh2lkJ1R+9@yKVBO#|>#s1s
z&&NCr$WuNIUO@ly`BNdhX!g1HzYel{ESwrT9<bR5;nxqWfu80a><(onp0HR-GnI<_
znrR(?pP>_`(aROlH~)qynRzAv#^Y9>hwb<`sPQpjvK`X1@@g<AiQC=4&%RB6Tq$Ym
z`w*U&odBg7gStVT@1h#tf{MF1H-GdV@R^0taKKWY2&u&rUc>p4FGj$+dq67u_taK`
zXT`=QT7RvyPlVW7VKO?nuuU}5<Ed1Lpn_PLkWbsKb%K8ir1lA?k3iAK!g4Aw9T5ts
z1XeGYqCjgDPVNBmjBtyR$p02H4#V}!0-FkduM0B$`;Obf1sTxy!j35jv_rUm0&-7_
zg#CUX7PIhB2(Dw(GM_J5hMrjr-wp2%!c0snr2S<<2W3>cgdr|?(JfpX12w&Z;&mwf
zk8qJXf1U}#cKEc4d8Y$e%q|QD=Ni_03Ytn;8g;0av0K-`vYFM@Kyd{t>ZP^%-<iz<
z@F;7)@qDe_#NOTv%w^`FX67sGUMn<SWh4ABA78WBxe#h$wPB#Ov5zK$^A1})7SMO>
z#u@l^pSAS$GB7)Bo*y!a@+D8$+8KzThZRu{_RnH*5A8qxBDPZYvs?^zA;=1`VGT@d
z5tkvZzN;i4lvZ0m2~|s>=`oU2Aa@9Jm&0bK@J>1Ob_vTVN7F5A(gRt{Ue4?b+r13G
z&<)Hs9%|oY6|~CT!u*awd@C!XofBt|FBJj1n?0n4@k$nu3uq4urHOi%b>9c;US`(A
zd<`2H4vBrNa3@^<n2qd#r8-u78_-d<lb#vJ*dMxJsgWf;hL%&Tb1CMiiN#W7=sf%0
z51d!ohoivxHOspKWi4#QBC3B}V>;U6UuUiKjzlZln*zaa*a)hA-(X2!!u(A(imv=`
zStAwseq_(6y7v<sc^t!Iww@Lt9qg-}kn3bxs`Yg<A1Y4tu-`31WW6l&CZJ-`M6E1q
z#63Y^sT5CLr1`HAAGg7q<6;#x^j{KFI-#vqw6=lgfmla-ybjTm2-;I|;TPasD_N;_
z&80_Ep|nQ2W(0Ih(wqWklN5CuZhtE^Q0sq}q#X=p>y<0%Lu-q&vklNr<)Mx6>0M=z
z5#bh9E0=kIeOvw&WleU;Z&KQMx1342`%2mK1T*u2+(HGh8o8GGYxc<xDS5JAK2IME
z2jwFd0UeSZY4E};Ke9mJA98say!fXa76^e)<Q7U^ACm{R!C<}IOYa1KDtqZtK2apw
z10jD>PEbLxLB2=T%+KYfqmVc&pQKj>&&k$wIMXDbT?zRw<?db2_q)@}X_0Q6Ph0cY
z9D2&mXqF&8Q%D3Ru5ulGh(AL&a6;a8h|Vf}2x{WIvyhsdxF4#MGK-#KW|Eh6BlZ-_
zYcOj1eJB*AZYYCSbAG;n^EC4su+F_rEtu(NX?;IWkptBkCAUCbFq&%7=6DHaGA~lA
zlVu5QU9z&5gVTC?CG=#6+=2$%kL35lJ)ywlyt5nUi>Az^&wqRQ0I)8O7?1NMc@-e%
zj-VI5@`5UWcYMZyarPKs#`Voj%+ep9w!oGApdWDVZX5%A;qC;SFMmca5UmzIj6ob_
zf;<sA>IJ036^cldenrIrBuJRh>+h!!@CCG>;4>r^5~+@IxpM7Ri^uMCxYfxi@!`7Y
zf-GBXj3Lb8a;c-84v)>@ajOm1T)WF{Q@e5ta_r#btCY-8lxMLz-TLunZ5Vy)G`euj
zL~XcMuhXkNPG_!LZOP9Y=Wse~<7}2JyV~xs<`!hz)DT-_ci0sFuW_q0FU;);bMrDK
zn-csYC-@MVz4glieX)%xKEHG_UueTS+Ltx9b3?Q^l<!~X7sAJs`1tXcYvqCbxJvn3
zud$1@xAUs${a<}4DJ9w*6_*qr#cz~K0X(zE$ES2#n}|cgp~NBMAe^svTiZ*KwY>X1
zsCo3MB=Mg+S-$~>w3JwLTx^2Dtc~QBG;xSm+|h4RGH?I2?=Y^8_Z#C~{h;6Ibnm(8
z{ZnJ6sZDNMzFTdz<mWow>KLcBAg}MDNt%;lRJ&aktIh1OS@P7;Q3>OsE&18zcxQG&
zuFah6T<9sZ<lEFSwyc62?z+x~@&iUDd#7yZAJjG2m~1eoM#Y&7!I7H2FOxUDc);<`
zy{YkjF_XEz%}>P>9`p<6cV6#5%=_IszmhkGPt@whY4sY-*kG+TEIdpbjEhpIiO}l2
z>m~o*e!*I6mPK#L)>|~1h)Au@q8YD?h_vdg6Rg@Son9YNS~bug$3Sn@Kvn0Y;m7H|
z!EH1W3jpS;P_zuj7>GN{TQ^gc<IAc8c~FWffgK3sjuh1{b~upxn^a5L-B);tNtGa|
zc(X}0OVIGqsj6A*@(8{(6<A;101(80IT(!GM#Cyzhk;dxaXAe<Ms7+YP|d3VvdbFY
zN$5;&m<#4Iz6ArT4(DxiK|LSN_36Ylo|j-05_xkv$n{1ZGOrITm<RCm72Zgokq2Y|
zd^DUd%;-~D2T%y+%J~>JaT5l1SIevB_lb58)|VR=kcJ6->jK!Rj^u3^5y1pA(3O*T
zi5cKj-b`S16c5SlqZVXBb}Db6VH*#yV0e|=FtGY*{E!8j4#aXfOBE_i=GrXPZ-hv0
z%2JI{<^?iEAzuv)yCw3fEL8~P&VnMO@eT~^D~ShLfrVdIfYtuo0Z_SZrb;n~3#qCh
F{{`pj7sLPn

delta 127441
zcmY)W2V7N0_XdofecG<4S4}k5#NIU~CYIPWMq`bMi7iH>vBr|b!~-@E0Ywy~D5!t}
z3QDnoB8Vc0SSTtW2#5kwL`6|V@3VOS_ulXGm+aZIW<AeZGiR5XwPthe>WJfMBX+lw
zPoH$E!!C<sy-bv~iGQz_{gTDVB-#J_pOR76^$=xBhFkCvFH_1@0c#Z~Sl1X%rc|oR
z-f=S35ieFIpWJFTkV+-Hq_142<W$|xK!Ib^^H`Z)srr4zT52m-Lw!j#BUAJ-PlCGm
zuT19M$7*qSZd1zUFs{TPOc^m%_H)ZQr{<n1WxuqXOX_)kYT4YDbG<NT<W$+bmUFXA
zGc{e1&1XCSmh=mm_KZxX9yOGcEoy0(sUNKrWxutYE7c#j6J(29&N=mwTWZ;omUGD=
z(@dJKl>N?BkO!P{NhKp=`{G>n*(}h>*DIAcmakxCjNGTaTqc(nJ1b-gnJT#*bb2WI
zL+O9|{Wg;Ro^%e!PQ{{(k*VJCtV}gfu@DW0KI%R^@G|C?Tu#<cLich0$ufshHn63l
zWTsq|$-Zbg=a|t?7}-}X=MvMQQY9PKa;|4`E()@5TF%YP*iDRVbj!J&8JH%@CbXP?
z%pCkgC7aZ8-i}$t@v^Bc=bf0{PdV9)mh&#m1*1~-6P-I`J!GmiUnpeid2*NkZ(r1l
ze}<>>rOEJ7e(GBV`u_7k4t@XQq$pF!mnrCaC<{}{R5Deoy=s|yg}f&KBB6|JS_`sy
zYBzl+1v)tYUs2}%37w+jC_LNJ7$})xy+qmWwiq#oYydOIjhF3d`#Ty2GM&E@WqUvA
z3cz6IUXCd9X+H$#Uorc?;${0=&WAG{Kd5E?E$5?{AI_*`fi36bn4w9G>|o3Jw@ivn
zlm)k(PhnOc5M_tk(j_*Xnem-U7SfhR{|Dy3CSK-!$=-SKm28zveN4Ur9<=<HY@c6Y
zR31Er#j!PpAHQYQzj7JdUyi|$al>)2u9qM;Ga69IzQzAcU^2vf*Uwnl7pn;FwU)n^
zFUrP|F}c?&KGpl%R;|Ybt;MBLXQGRX{tdwYOrRPUnSzjYU;iIeF)UOqtNZr<u!@Cx
zm8@=Ai&tJNW%e1~$6K{(LjeC#{{#G?AY1;^{s&m1NcApl)pf*Qt(3CBmh0GSgRIrz
zTDgq*_5Wwur^R%O*<VNeKUsdA^8aV~wslwLuh{jiJIZG)#?UF+;F88ag|}Q#neWV2
z%M>4}RMrST+}Lfz|21u8l>a*kV<c6(zZ#&^L8IWcD&d|Tw~i!NsZDBLrr>lcYisY?
zkNYwAyxX_2Gaq?>+2#|e#v9KZ#Zktp`ec>&qBbj-0p2-nK4)foOKtl&2F_(<|0Bn3
zslp8?o6?MHP!?z8aV#rP<LHE2M<qLuND2wF<v3nw6mU#`L;8xRq?6c0t(R{S_T0bJ
z+Pr||okQ`IlC4Y<as1~Z9o>GXBYTkaA2^m$F{Oe;6L-=1h~We{mWKy|%sZUq{0^eK
z(*bwBEFJ%=WW~6<aQ-=&pZAU&x|c{tuVJLWD~uTK#uMr*j1Mm7dXnTXqVrEq(E0lj
zgxz3u5X@~p!J6I4{Muad+NXice7Hxd)83Qnv!x^%{1<5&zozk6dznUPi3>3_=98v>
zI_doTB}p=e(RoM)nH;*3^siPBe|1-C)gPeqjGjsdil+-mX-*(DM1M}^e;Y@1*)Pd(
z>A%$P!`tY1x|$^W+L7i*8%SqzHaYQSCbcd+O*~;eN%HYCYHc-!&L^*<kvJ4hCci5p
z{^#FQHwqT;G6#I=OseGuI>sF!Ra;9xuHeQ*pL$V0{+vub_&by6?gf)vs3cdq<&gfn
z#Ux+4lib>qO7cFBNGGQQnb|&pjt?tHGIlwgtMtUSF&+92ncPku6<3j&lz^6=-6W;>
z1Eh4OWh55PCGhASB>8qJ^;Nc=B#rT;xj2j%hJH^@G~jWnlC2s;ZlzU|#INNF%L;69
zu{SZuFOZ9?4-tdobtoCW)P*Wi4<gzr(nvI~r{jjzbo^;19b=x6=1(od9?{}xdmGV-
zdNP)Hg<Ri!gU;V)k&FFXx^ej}>1_Xz%n#C%mBZ(WXYel4)HzO4^P-juZLBZ(H8YEj
zx6hF)nJqWcmyLA3q%CPy<kNY7Z_=5to6LM^Aj4wI4_E#>wf@+b-2L+;wbn$?uRi%}
zGC8H3%)e{-`F3eZXXF$I5jE|mO4vL)j&Dm!3w-E!Mxvv86zLQtQ0rHn={)>5A|1St
zT32i6m^+^gD|b?#*8fb#POKxzwDyF0ttCl;hFSyvBJ8=b^fUR?wOs#El~m!HN%is*
zqMOv6&gaMp@bj-klzWHd$I3{vy5(sR*JAj;D$+4KNUkg-Go$;rj0)yqxUsJhYIHG;
z+%(sg*3XEUyGWctc+uecKcOVm<2$Kmtum-#ZV{21S{^=+>gasFnkZC%(@^i-MFukR
z=)A1u@p3Gauul6(v-C$gm)B9N?g*Lu>kB&e+eTKR){%TlXR`9+b6gV++3fF0bk0b}
z9Y2x3eol1kfv2`gR;43(Y9g8M9!W#@#XvIOSWEpV*+iGsLOV(RolTOjcaZsez9b1c
zOcH-LGSA*_=@>`MzVXz$i=$S@>&s+d{$x64k0B*y4k>N8L?)+}k<t!#Ixa0D>W2d9
z1p1TV;Tk$Ws3S-1sU$gmkIv^DCu}xL$6K$-Jb#^z+nlKN>K`;thIBgr%aKfds+>fs
z!gTVhmkW{3Zc9q8*GNgfiFBINNau&4<XrG_YGn@5acu@U7yE(axjDoz@e%3&eUVH)
z?MQ6)4b;6==_F5RxdOh_65B%OmJ27m9VxkVprhp*q8mDz`Wii*U_OgT?$nLIRjY`!
zc_K-A|4he+&xq);FP-;VO(;)Helg(5ggx;kx!9+X&W{eD&K%fCj^6Ml{gFTO^!!h6
zLnb?~rvc2u3{)js6G=p2UlNg@gCv_<ZkVq#=v>4+1`nLIgsS+2NTVakK=nX6){3Mv
z;3yrJjcYkZk><34#Fkn}<~cKIHcnB~^<Q2~4U_+-W7olCxb64U%j<9H{LRlaq*>Jj
zo80nz3@;-v8%U(1qsWz#NYb~Qp}y`vN3CPdk>T;XNxr^`c!rh{f6w=XN*+v{j^Ch<
z=l>c4toxAw^IKk;fzbq*>r7yer*vG+5cTc(<ixTxBKoLh8uEN05zS+0<bIq(sKDhU
zN!dxL?|RbMj2=gFzjJi#(~9K#Tiz@a{v#g8zh4mb%?os#?M4PVou-DmiFE#974<Ks
z<th1aBgs{BiDKzuqIPb1u5H8|S1lW1B}vX8I=5<-IBs9b;rJ+>!BGk)x7zN;qCj>w
zO2DzZp2hK)V+!?qk`E2bD=z{Z>`Mk-woF6(TCRhd$8yLY-=|)dXOj~>8VUU38IgY5
z@}Rv~Mdz_vIxdxyW}2CpQw7r8znD7XWTDRd^oIE5Iap)J?ml!7;9wOQs2xPA+>hjA
zJKT_J*`coF>9rxG8stqQR8)a!z3l8j(iwSxj{H3O`R1M@1H%@QfxfM2s88b|rj{*U
zPV!y@3EOO=<2Foc)Uu2+(p)-LbfA)lNuye}dLo%D4j@>6JfGFF9(TyC*8Ql*6I!l=
zNk@o!<WJPIZ7tV)UoRSV&toDrVCnSvBJ};!wV3>?x=sB9qdM}*UpSw>J{TRH@#{;p
z&OGgm^I6~S0P+V%=`{F1yDwH)svmP!<9uPGGhmBj=_RvjKK;TQifD@IxbZP0TbS!3
zVBMX`xProm5l%tq%eYm;$^FbXsi^re?pTnh{F$gHfCVt4X2IwIhOLFwgUpNp=y?#c
z@d)6-OrGN#7(T?T$${!&rqx{ddW2a=?}`w{nS(HtS<8YujOl`Pt?DRKMX$YMOv6O5
zg){Pg;ErIXj07N(S@AbKKhCsy4DJ(*KRvahn7_}1Gn(m}0O3hS)fTl=%n$SejA451
zZ~!06r0{5rW43vKJDyow0=uV~0Gg$pVNTH#`YiLyF0h?rQfP^Kp2@fj^9fA<5Wo`|
z^)U!9Fz)nxy~up*2WOHP_AOX0F-Ce2B{ScILo<cZ1;YGgX6|tmx0xvdgXiBJ=D$I(
zo6R)O#$e|#-|ho<E>n8}h&;wA5uV;>f@Xj_pHW-}uz>l8o@<3nVK)>d%%rC<SjMPz
zU@2!t?*QNlb8{M4DwwVPF}~HzyF<X$FdsKTSjQ}=1lcoY)>{tGzj|inZ;(D`!r!2H
z!E7jj-It7v<~t3{m5~s>VxCR`;x*H)4z)&x>jX#NGOz1ku!-6F0v&zFOgN9W4~&6+
zUuXFtnnrDw%l5#-o$`=o0rv6Vr|0P*GC&*)$cp=z3OQ6O7sSERs;coYySmMCoUgGA
z!+Ma^I}Ggt_1@-H=wKgze;oUE#1lr<FSIR;^<PTwr(ot1Ryr-}$^jkGTeT}qyV;qa
zfRKxcfP{ae#M+n$+eglUdtIL4nW)~vNblqr|E&!73+{YZX3RNsYX@_t9Uen&%s4Id
zcQO~+;pRNZXnz7*5R>}=DzBN`;c%;&>3a!e+vGETfu@^$^%(fRPyQ=ShWz9o9Y8He
zUgm)Th?aj?2walfYcp`y<@_tGX2~7hF~=WhXkGLNwAz0%4RpQ5?P&P=BL<q&o+13D
zT0V0nj_yon6<i2o(td?*BJ;~X=wuc%Ay$;BUoy)5|2G7J`3Df{EASdncVBP|-Rv<7
zuLpI{)&JsQ((BGf#9Vq)08QQJ_F(kP(YK}q&z*h}k8$d6DTdPnRt8{j2YO9|AA{y6
z!H>_+gyYv7EM3I$i{&&k`7(s2FC%w3qjkb%UpO{3jb0Kzcjy3}C4Y<p&+30ZMeAR)
zjF3As{oK(xS0-i^xV@QfuR-F={KnEveVEbG+WQ1kss`z4X7nt$eU@qQ{v6Zd{&}Xw
z{{*I`1Bpya4=ym|wK|1q>B(h=deSni!ZUitTk3OgY}KE9`6xRK2HUI8z|+pM|1h4P
zo&Ol)*waxr9Yx=XUO@I=9Y`IV`8%BXI{7*z!(x7iN2Bij1mDL;(i-WzD+<s}d;K56
zG4u=CKF$JVn=RdO-f{i_80os<ZyX0c?GEF^23>)Cyelm|r;Vq(&WRaLQ)y?Wb`N+q
zGY;WrRQEGy8bI#Hly8M={>&G@Vw4UuFE)VV2(txoOFRz!^Wa4kBX|QC&6w+9_aw7e
zgvwc_YZ>6@7-cv#&ohf?ai7YJ{tJLBj5Q9LSD9B~=t>T=`Fp73GEKK(HjnA$AU7W~
z^*e!h!c^UWY6at|f$A&f&Sl_VGtWE1U?cOx76`Y?FMR|}7kTs>7<82%F+u1fH-Ch}
zSH8##Wc%eIci?@P{Ig(?9hHBx0&U0S3Dbc)Enm70Dre+t|AZH3<;%`HVB)I0Z$}`~
z<bH3_cvIf58O2?B9}0LpkmsKUO_98W@TKysQyARG@)Ivmdn&KgV7Ok%H?2lzoD?6g
z0NFOhAPE3>#WNRZdMM0ziK_N12Hpp!pTdHGt|~<Fm_{a4F=c`p_x~xyiZob?QRo+g
zG+A+EBJe4SI85AIe&Tl3BLV6dScPh*liktp&XYH&|JU}-(_N^K%-juIqdq#1^Ra_U
za9sQ+0(>p#*7-Bh|E@vvLE7W@yEyiK&=tpiQSG5H(6Nky8G}>s+E)#6Spw0}(8n0>
z5%<T#;ZdEIL-ku3qNA$mU($Pd&K_Eu{W|(3TK_POz;UHm4~8`_@1hS0>VoglvqbfA
z7Z|;uPMv_JRCWDt;LT76$<cO4eRDHx-B;^H5M_E>`|2F$-=l+GeE$(>kJEme0PO^A
z)+?Cv(qH@@wY~a1asPM0M=@bF@TPzXq=9|F6t+gKh*?fAtrBLD8KkAm2!H&%Wz0t*
zDE7*Iufmyq^5O^(`pPS5dbD5O{R|3!`Pc6icn1W?T|NQZ0r{8)6bI$kE`cUketiaN
zhvX`nyB?8W9);e9$h&yJ%XoQXG>X&m_F8D(mdAU;i#zhZ*I*(??o6xCT=|3?;O@#5
zv`)V#pEd--e7SZv94(Oh(N+0CZW{ohqe#9m7pf2C4hmG2$ahefsZ753caT1khf)mi
zv3yMfI`c%{dN_oY^1e#}tdggffTmh*MR;FTBOi7I+)j#ao6zR0*qD!Ei((a09jdL0
z7t`VWc7?eX&bTP@X$pQ!ktjeI?ob5K4|GTIV;rj4idh_JaurJoVK7heYXpS%6h~>*
zcwbRNfrbLbPFg`1Dr#s6R-~x;74TxkhYS>@iZefB5Xuy@!cZ$$G<OH?vEtM@kX0zg
z-$AWXVVD4)o+_3v2X(c=ah}ZADrR`2TBnd2p<1s{T0rw$@o_JxzEq5%<zIuMW;bfD
z6<c4TYmJK5^eT9(=u`k)lcIw9+pKsaLi4?1!*cY{S^4`}^mnuJ{W1u*Dc{m#f4lM)
zO=De^Um~5O+M(nff1npTmG*ELbXNx9-corgH#dQ8m-3^#0D38P{!rbc9P~HL?^SNl
zL35vS@>gi{Rr>Zpv0u50;s^oCF{hvssN6)sxP!_Gci}~l@}?PpLrTK~v>jHm@$e~B
zIbs*Q2vhR$SOcn#DSatQ7_MBf9f(L};nzSMSNab`ElPQ?E!d)!R*HO_QZ{`JV2twU
zPzd9cbCFU|#Ve=g0B~06JrB;DQyO}MEI~Qu1mKBELwl%PRF;z4Ny_WAW=vMPVZN_Q
zQ5L0A3@BCUp@tV%lq+azm8SgdCTOlHQ&XUtp^US^@9WAgEQ%XS+gDJ@QcgnBOm$1S
zYA9%KE9ZH`nQZ0BJ5b3{zPN=R<|+Rf43@h}FCzf=m8Lx?@|AuRdM#A8dWhnIa@%&A
z0~RZ<G^1+|l@E79r%ZYHI%pm#tDR9iR(9$QOHY*E_h6z@neiEfRm%1EP}C@=Bd?;W
zRi>@LkUUd9(14|0siaBX3+2a6@cyN8W+B>MDcg7g@LK7z24ruPGrxi6TV+TlI34el
z-oInKnw6FG%5YLmr`3eBYSUu?x2Q^g0L@m_=WXHIcGbhl7)uw`S~KkKP|a5X=ca0)
zm4dtKHVaJ;mFg#$*rh7J4->mpmuCRCM>TN*gx;#cvrzF-C5?dvU)8Eo*z<F!de9`>
zU*$Ri+<__uz3>jGQoVr>QpKlWfP+<a1EF$Q^_ap0M^r~|(<P)zG{A0{>aS?j!d1J+
zz*2<j7A-T6t1L&Lc|xV6m36c#J`#O7srrv@j#$;*3Q)(X3W8w%w94_|4(y&$IX{5i
zbE=OioO@pNC9RATRo8Aq=YlGB9q>u23HyM*q&h}3uDhxjZ`AIoQjVZjpeh^+T%oGR
z3pi7x>NWvw#j5{KKv<%B8UlE!Y8d4Q9;tF<aJyWUL~)`gs#HgNcvGSBPlKmU>WCy1
z&gwZ|LAXV|{CD`YRXyN)II~@y{y7jX>QCo_W`}xI8Z5b~-%bR#hx#!K6;HLM6AXH(
zzou8&9(7;}EbUWgvH<v~b+p>rul_9$<K(Aaa|tQ|>i;+gXadzj5`eeVU521`Titm!
zRCCm8N>R&I7fpvxch#-F1md3h@^;kn)dq?q7pQyof#w5sc30Gj)ZYz(zYo>U3e-x}
zH>aQ|Q^y)W{YdR~3|)GxuA>mz6Lq(Rs8y;5MbR3dO1)_XfYs`YGof0e9(fIxo~eE4
z#api)6$P4?>d<rm8`OPIL9<ake=)pxqZVt>_D)^31U+n4_xTF&59*r%P;p{yFJNLb
z`&ky+wy+0ZqZY-!e~u!WO@0mwr`Vp~P!1x7-QokbICfqP1~{H=_za|H*iAX8on?L0
zuzQ|exehc5?20xJUSRVmmvoW+dkWevu}RlKn#?|=>FQ;+$26#<vR|Hr@GATLT?o_I
zo)n-=XJ-b(ZU#G#9;lgY4$|>h*|TFQ=yH>t+JxWm7F!<*ojYtft@N|m<#ZwDvXKK&
z<gtTj%72foL{eLIpWP+L?_0p`cnR+d*^kbn_eHD@*?LtmyXgnGR>B?_1-qqeL^TYS
zvj?}M_Lyy?iE1TVc?<9=2b)IGtQxj)9Hh0Z$pCykyOq)u&)M~TP&BZA=L7hP^%)73
zH*7yFEmd#XlN5SwX7ADM|DN?30WX|5-@y<%b1U3X+rn+GfTLTvEyv)@c5Y(=3Kx$1
z6o4Jvf-D$v;~Zg5Aa&=?{0X23_va-PySR(4P~FX4_y_ns+_e)xcysrYQ0(L8Z-!4k
zoc~$)l)|;A8}Bk_ACBTGcWVuVX<VBXFrUFiQTXsW7kwF)ZgAtCgENc!Rt<Z%xMedS
zyv<#9i~?IWx0;rMIoy07(A?!JT>-quX=v`B&$-Tnuz>5o3+9Wsm4^T<<~DRgt(4Qz
z+_8*XK-}e=YdP8;b7QvxUctQ{3hGL3GCc#Ia>0+#muhb6F?d+Zb)pDg9hcRc7H;)i
zkMB@C=O#Tu<4dmNQ@G#2-5Ud8BX_}*Mx6_%Nlz1Zf&zr^xcObc_JR9>)~-%GPxHjh
z{Hiq6w(!sCvfReEqru<K@4k-0l|LMWPVC@ISHhW{{QP=YaOX!pVsZa@@_+6IeizTq
zfvOjuxDB;E{AoYX?BnM+LFmIrq`>Ze{%s^`e!PR09)WyXJlGEKRY(`Bg87I%s2t*d
zxP#ge{vJJVLijn^a661YIRry;l%Gr?iE#dC8EO&y%1;H{f5-W;G)p_dGXjceKB*kO
zo#cO|`yiG-+XF)y$LGxg_i6tA6BK9ouNI>-dHh&<rrhW6UxTCh{Ex|i7xF`oqj<nS
zm<qea{Hzd=J><W{GF(;0=k)^a5&tw6Za?Pltq0EWgx@g<q?P=q^g68K3%`Q2hCkaA
zI<@?UDAeltpH{+)=X~`Q;9v3wC{@wGN6{+dHGjAQMI-;&7<8?Pe;f%*@A!<_u=}2`
zi3jHg-j9Od&cZNvkZl&G+yM1fAzO>KZ4O}^WeHq_sY%dr6~-R{&`rp?57nK5^c*@K
z!r4tw@f5r$vAJ9Dr`esCFoDv?-ong@!0i=UlR+P$n&MEt!p#5xVuaxDA&eF3>2Vb=
zJiCVBIxU=_h{;*u`4V_>PH-HcTP8s;$<df7C=j(!T@>;t7@Z_+p!sXE;Jy!*QiOsf
zsHF;lMgXn|PQ#&@CVWpJ_iKVz4SdQFcK!;|>%ygJsAUONSHXExC>RaE9bqCF%oci(
z7rDY_%7Nqw;~hO=>7HP-;y1W2JpTzM3IwALs)a&HDRhd3>mQ-^P&iLv>{7v#maApL
zV#+6$3m!C;c`U4}L{TAZqEv0AuxKk-o(iwyAgmUY6bY>re7?ny)CuDzgREX?3`5&<
zp~rr@N?!`vYFKIz8ox!+C~S8{@kZF(55v|Zta%F3cY>k_<NRKTEdt<!@QD#ZXK_UW
zgqy_`26*o;HVs2tfVh>egahL4-=T6)Ty_o41dAKLfER~E&*LzEL=2}XW{B8#6U{%v
z#7=TlkBWbug-*CAv_~yM97pSf<Kh}xI-L;BH()7R{EQZ7C&f5g%f^VWIarDn=hC7u
zUUc~qDyPN!?O^w;_&5&zJtwB;<7Y|`=iWw<C@K#?m?XCA1I<g~IV|HGsua;d*^A5K
z@x5rgDlU%3(4>ibNHtw-oC1RxVjrxhRheSzg{a*Sv;9!JDgI59mRsU`dac|MJJx|T
zTWp};K38nJ3-CN~IwcP7iPM}>yDzS84P1dZp5E7m;sxwq!TL{p*cUp*;?)=cOT?K4
zaKBW1_cOR3i68sHwQ{io#YUcp6Y27*5O-RDuM(}4W_>CiJ&vMTJP`)AZBoWU6niAi
zSd5{!WY`Ix_DZ*CW5Yhl?I8*u>Cj6EeWmPODE2#~N!NhzlhTba7$6yF*&8U;>fyx!
zX_G&EIw*CbMR1Vx3po=kHTDDWki>UJ?XYw*0hU6g{MP`4NqQ4J443vD09k}IZ32Xu
z(wKUv+>jzEb&w_fL^r@qX*4}$Z%K}!{ZQVPxHl;7NI`$2$d)1rm?JS(6uDAjEQ&m7
z%3mn%N_VHC7Z0T!ENUgv)N=Ixkt9Z-sE}fnaII1r`UtfuY5GPKPo*;y$E}tgQ|_up
z%37m_3H;a2r6se_;lV>-I(E&&2zM$^K<_)B%0eeTRW5+LpLOU2d6zSE!E}vx17Eif
zG#K4?Uw}>zS6W>4ED1z!d%dI4?LGQ)^sbMO4ElY0QtYPRuv~EVpG-~+7(5iHfi=UR
zKd46%I`Fwes)B*RAzl!Daqd^ped&j=s%pq_3PgS7LFtmOgXrEHHv2k`!-MHc98q-y
zI^S3+c0bbI4TeV@!u}`K#OALd{~<3O=ZlX~((x~^tKi?vIFE)e9!#|zHGk%r0ct^v
z=6eqJUkFpT4AO8WnSR44rsBr`MTp&4&J%h&*?v>uojdEC0n;9A1<fZs*(iGX?P5Ro
zK-+G%_e}KCi~X7+Wqa7>VQ|Tt?M-Whz3c>v6YgX0{{x{9`;!%#zHI$d6#H4nKl@=c
zfHmnr8p!(hhBS!%o@Q~u>?4Xg9%8d-5Dv4S{{gm8cHB|`!q}hxgKJ0Gp^<1i#%4`K
zTR3}&@>LORBBgR7*`W(y_c%NFBXFKzof#BS>=R12M6(+xRdABEIaWh@iVb-O)fn~^
z1zTg;V{({?V_kU^@oaxLjLvB`a~XhV*ypswIm?#N3+fzepf$pIw%2MnlfaJK2e%X1
z`)=^*0y{quZ5P?3S16L$oYN4dupxARU1rzn;b<z`FN4+}S6F5^q*qzjVK9-#D)+;g
zYiw36?54BR4+40deJ}_nGTBv>SG~c`xr|ZIV%@s|ev=Km58N&Gk_499>|b9(<qmtC
zw!`GI^N2H#{VxZcciBuA6!+NAzk=p{woQ9lf8?{{IzY96y+RS4LbgB&(g$n<nJ;4N
zGtpMedThjyK4d@Z2WLuHRXfm>vZv{{FJrqGgY6L;u@P<MY-dWrKW68*gWV@=PfBN3
zupwl(l3jQPoK@_fw4!^;{)e%5sH)kZfoQB@7uY~k%kC?N`8xLCUKGz*c```r*+dH6
zKWE>31utH(&1N|Ik_~nRu7T}w2?k%W533-2&Gzd6mA7no35q6mJ?)!&&-U5}%@1r5
zWzwCvTTdZ$=5Erf%(0CtNdmVEH+T;USFXGnjc(j+3Ty4;{-te9?p(?tw0UryD3R&O
z*=S^UaizCW+s##D8>7mLTjPq_9?qTKmfl>ahk)<phSC+Zk9)feHD7K9MIrWcYsob~
zuJtAObjZPdH6P_+?&)sWJ;Jr6=~oEXnO^;&TpB$N!?=0@zvxkJ=?kbF<Fd4%3Fqo4
zw-~{_?+RfgC!By!$2tEbXrADP)8?osZp&(@M01QB!js%zM^T*Od?rH}!!0@kTrB69
zMnf9MZCDD@c<wPRHBNJBwA1MfH=H6IXStg!x^|BHAqbA1=YFH$e*!m%W*&*0dLZBz
zxIbxTc#-=p3~fnVyMr))iE}xDS~Ay<o<k{I&?8V^=B{l;TPhdy8JxMwy>QUtFOBOk
z3~bl9Ie$VYoojs>b~Cu0^!&WeUCPB>mC4=c3AP)Yu0ITBaYx9*n_RbFAiTx-)j;Jo
zmo^HP?r>cwyPVC1mOv$k+cplIx!j-*DDt@8^q{!QHPEWy9{0A?0pNY^i$781b0cV@
zUjesaDo6{tF?6*&;6z$$7jcCf;b<{;-vaXwxlCFpm2iz`K~u`bbO5}J>qNn|N8Fh;
z&@AU(Nzi=EwWS%)6E2LRaTVOa*3hivUeE@WDy~N??Lm3U#ZqRVnrlxhhZ^p4+HO_L
zJsALe9p_aG{4?%0O-Jgv15t48IcJ>>;S26fGF*Gf<<Ey^0~bV3h|T<|f6+r<zT-w{
z`t#K<(WL<XXG)m`@^ed39N??zF?W#fs-g8q5U=$IKA2A!j>bcL;%{*AF#j>7#g6cE
z6X9tHzn_+Sq5RyrD8l${i%}fq@6ChxWBf|G8^if4^mvcpXVaY?$v+838=Un(5zV)u
z4CYBbYzu0q_>=RX62njK2(yk@{yshK;`r+xFc{DOHVHJR`46!`oZ%PKy?vJNL$Szn
zyqX>q=lR+yc$mQZ(99u`ub|1z1^ydsxK>@{1=^XA#4B?Fzr=?OLXpfj(Ud=h|1lhz
zm-&K`C{p>91UPfW!Ed5>^;Q1XD{!ar))7#>#=FJ?n9g5OVMsFgs8blk>wG*tZ8Q1a
z!vVa(-;97}7C%}<ag&csg`>B4Q#e>|^BV`_m%PKzng!}?{t-ovbNH#}VK<kbM|s#h
z-i<aA-9`MFk~;TzO<Snm=Pi^D&*v{M0!;z`!*~b_`7OKArw9CY>Sz&vo@O4!{P8Q$
ze8_)JshSeL!5Kb1;;&5xSvkLk9vhGOQTb4L!grzmR`9hkV5#JX(8{}t&x{1_DZk%A
z!H{Y`rU=y<e$6M)spXe<1F(*NK|9%=@k8GNQO_4&M4z7X_y2_O1^<k81-<0cD7DqV
zAEuY;EB@GI2w(GKKL%$buNs8f8-BDFWB8WeXo43_xMtAyj$b+iL(<H*Powzvd;YBs
zq#t;W!eUNBD_Rjc3%3J6x>+bV2A{SFJ!r|kRp{;mm2JXO50GvbT)zj6i(oqpO;_R2
zFbvlYVHK@;-GmR1VQHsufi4Jlq1Pg`c?e(9hCELp{X77>go9Yg(~7biCEvV+0WkpX
z5n{iEs<)ttg^rK#XaOww3a8hjZNJcW3Tl4BnHUuQ!idpuCP4U|NCSm>>^xE(5NdX!
zI4B&V7hjMdev82i78dmc{E)D68ES`xDM7GsL>P%p{SH-#FoV_+p~8HM--QXghrsSp
zVFvAXJ|-L;hg!HG^M;2JLT8%RM+)C`N4Jj)p8ZifAxxw-Z<OFe+gzgsk#@SB6sn?8
zJ0&ckZQ3!yr6@QWD`e3uCr+>zpcXH58Ht+XwBR`m_%lLh4(87aS84HgPFPkC7taf=
zX;W*0;4}%Oi9*^D2rmf1kq}-Kf)k*bBq%G<c1d_bi??K9>Ku@!2pwp-cUc%mvEo$W
zUkXQG5wbVJ&{g48IDASIf?lDx<`8oB!<%&B_)%0dgm-qBxGs4A2@_euCAtD{3h@+-
zza`9>i*dRwJf@uT9U<&<Xl4uV%&?Rr9HqQSt{|O;GkJpK27`A6`UnV%>+hNXxGx;}
z8p3=*%tlcl%+y0zC^({fgXVz{PO+mR;n#5Bi-i;Q=*2@}&#%xa5#G6>tyIXNj+P1U
z@!gQ>k??@>zU2bj5=#+6Xv_B#;j>XtsSuPgP^lEUv;j+%FrFgxPlegDKvpe8u1A+@
zgtL@At`!0t^H8l5x>4~=7>lhGSe<**#;WJS{YKzl2(!CG^`-EP65|a5OBv=@!nFP{
z|5{i=iK9kgH+la?*h`P#x5A?z0ca9BUqRbDVfSwkHVdOEY4Ki&8IRt75GIdAo0Is(
z8@m6T#aXm-b+Z`$0n#mEGwr+BDsGEKZJU@vVf5|d6bkgah=XsV<|>{{0bqytE9J7?
z#iRuQc!-<7L(Nl6qu`jAxS6I`d&E_=l=Bwz6G7%9{;~urzT&n?@OQtsX|90#FF>rO
zkFNs7$F#BafOvWXiePc(JeW8ne(eH-hsC~&FhHSVZU$;$qCgvikBW07*o_eXrDsZ{
zIPfHd$3<_N2c8gnQQ$2~R8vSYT5O^v#7R+p8qS;&FHlq~M)dp{-%}xe5Eum2IMH+%
zH1VPnWm!&(J{0XaBL??|GiSxcp+KAyJDxysUJSa5wgfT%IV>fLw`uRv1u;ApwTmKG
z4!4uUq$g0hBnE$r@l6(YduL7l$ng*5hOUaQkHTD<_*);0!8I|`6X<j?e+=woh~X5W
zyDo;%qcc-nKo9U6;=pW>WQjLv{&rIwN%zeyvCA5`k}Y~s{5D6tJQ78&xNkYA^Tga8
zFmzXp?+2E9;>iYd=)Rca_zn1cab7-v1>#t`(F(;1S_eH4HCv!lB>qI7mK2M8G3-7R
zqv*mb5uGXlC>5_!a<WWRQd0DhxVA5F<zn3D;Cw8erwvC>#H*C~s1RGzzPw7YE#;Z3
z#E<uY^Qjoh(xp}{_6P)NjhKEG(pqu&egNyl14R%%6Q5H!w_fZ<bN=U|<sS^m3$exs
zgD*viVxA4+3Yt#65+l9^{I%FjZa0d>o#EjdanWi3-imK%9@HfML7CxqV&ERMHH$x<
zr0o{(#ot?FpgxFuX%C*0ltFPQXQ?A)A~s7a-=J-ql=%k2?b4}gm~fHC(a+>6?N|!H
z4oP(%j=D*kdV_nXH02xM+@;a9`N~6jLThhN>7fcLyQHok!I|As7uwe6B^_BS!=rwW
zG@hn$-qNHWfY>WdqCF@3r2e$v_mOHVVAoeN?L)C&`iDN3@RPRx2O58gr_@7$#A^W$
zlza*yJRn`B0X`^I(q$DSx$S}X!P0gC<_}5s0T{!>(u{>rIU=2-*u5h}@}SvGs1(%<
zX_(ZSW*JANSjrR~lWs0S5iS|OgQW;5={<TMDGj*~z;WrpZ5TWu8P|X&O6nU1m1t@2
zI0#Ql6C|*llH50fGe+9l3eLnz?J1HUCwWs;^^7#FEox^S659aMb5cP)NY6_-i6|1J
zeiS!Jlw#I`=7RJOr6Vs&w-8)bB}tQt!FEYHL0f2(rLPVGo+2%x{L5vj$rEj<Qjfkc
zaYZ^40>D+ty)TM1X?hO;u1SBNMO(VGg{Dy%lEdXw_<dcPegia_(kH}yL%KH&s#(%p
zN`c>$zM||eqEhbg;<n^U!+l3uvIs@Cl;;J1bEG_9z;mVdP0-AfhFn0~T`AuOJ-jDv
z`2q&-OQnB8C0{yl6`TdqiLoe(B+hXdeiutw#ZY}H{WKRvne=KA%s-N@((0sKT11bq
z3h6`ygq2dkVF0V7$@CVhk+?N5SSw|o1FlYbHW?j#E^V3wgD<2DElEOY9X$*hr1A84
zdL_L#qV`(4att26l`5XocH<`L@Q<K*Cyk}eGR+dlz|wmul(yf0kj5+Fg_EX)!obd&
zs0*lV);QC>y+yN|Hj!@CeAyQ8Z5oXe0NXYBG)r*NeEK=aTr~r8F={(BqiVqErb%u@
z+fI!??J9HE49lQUlZPgbBGsOnIUfVROEY5%*mi3MABLx1nvQp2VvpuDg%i9rr+PzW
zuSQLqPWEYD($dUFvu_nheKp@x_<FxaL7!vzX>L5lIQeTrT>%f!oDYXepymOsv<_%)
zgg|&u^P)@3Qb)5U0M%g4pR_<dr1|b&01s=HI3PTt@uJXph(@IBQ>bQ5PjH86JSZ@K
zRFgwn<c?_;mcr3+O(|`IjL?*YpudqC1#Ja6t{F!^#R<)}erSu*ENX;iwC10C;Ed4}
z&;!*GtC8rT8>hKUq3tu8E%oT=SxtNL>73>oJvGm3df~$uRe~n)EHo1};g`XELGz|9
z+AeDLQnDaPbKMBsCC#FBAWhcvZ3ZAkv+q+_x~%aPU_Mn7MFy{ECb^?8S2aT-flG5}
z3i_kGrU?i~k*--wIqVEgciOOYU32ywfSH=MtzqegW-q-Vvox5);;zv2oB_65nlZ=0
zc3U&K6MVX(xz-=JY|T*$CFN)ypFmr#CT$Zm^ECZ8<43!z85{zZdz$ZPC<`=>fZxGg
zsA-_<>Vd|790rRt#}yD3Yg}hT^`Yi^GKw-ycX}8+(p+r`*=iC~!B(qTwhrS|r`brt
zXPWNx8mrgXDD?GQ)A|xPUub@$4Jj`*1$9tq(Cm7GF?^-@v@<&KT9fZs2{#%wsYU?b
zXmTmu@>b*iCu&WaR9a2F)BLakMYCoveIxN+BNU?TgU0C<%sXilLjiEse&Ym7o3-na
zJ6CPdCQpHht=b~`UAJl5QV?akwqY^~7wz1g=$WhbOF7^>v`Gb&>U7htT?47RR^JXZ
z9@=AlLF%dfFBhY?OIxrAD!a9->4x{x)(k`29_{cI=##g0673}0t6e%7uI<yFrL7e{
z+IZTu>Z^_G4}<%)$0%Lpr#-X`LVxWY@;*RoY7Le^?er7{?!N=tc-p3NP#dHMX^__a
zXZRhgUFnSBKBOI{K<%*BLU;NRZM#;$hiDJdG%i$|Ist$%ZJQBrJ6zk3HgZO2PaHrk
zQp*;>r{mgLA3^1Ww!jQPl(vCl*3sI^{ivPP{)<_TLv>19eimJe(JI@)i&*W{@u<aV
zcgWy(yf&=@UYyo0euLtSc5F}J&uZ&CqIOQ}I~UHJ*Pf$LL4r110lSIXs$+m(&~~MF
z>P78hig_hzlU+b|N!w#Siezmqh2vAS7oMQaaamh_0o7FP;KOk0iuN~rX|KAf{hZc|
zY1*=U4BIvB1R2`Wwb-MDn?pOP4*=J--gF^nYOm3|@rJfDZQ0Dy_TCH9o7z1lIC@Ll
zpM_7iwd;;U^Nu!q9URTpo~Pl;(e8ACFxR1-PkUGLv?D3_bXWV?6|mjY&Z60RzV^dL
zcu}BDqMcQRS~KMgA82y|0W8wC*$d5LZJQntKGfc#*l&rp;{<fORBP=HXUeqw$>1aH
zC$CT|*H+V__ldS+OIAd?&kkXw*74alKvZe}YXHqt?Jjz6S8Gct4pF0xp-5$|)|+<K
z)oG{DhqBMKbrct_*LEp@+t0OMy$7yA+jR*vUuiqgJL<LeER9;D_R<!({YJZub``wU
z&ZgaMP1>2XrQ)4d^#yRvTD`*qr0=zbzo7RYv_Bt1;iRimL%2n^oIVWOs_RD+$ZfjB
z>#)0Bx8?(YF1n+xpmEg+bS3T3jmihkO;<YyecGwhO3-xIS)YQ%L)R1m6;It*ny`B5
zI@02Ck1jqAaBp4cO1l5{>g*3-VxR7|9o_cP{dE&UU)`2l(Als1Vj8^g)8&Ss@YgZ)
zU=7d}QTQWJCkuq#1G-h4VDO+Wwh{(|bY|L+60D1)4Yr4Lb7(9M>#AwNbwroz1w$da
zujyh5)y=J=P(zq*U1#VV)m;w+@R)AKcCdx(<`02tgf5ac$wlg3(f}RTT^$L#Cv-3U
zp%SH=NS9Z%F7P!hoz#u?go#r+4XvAEbekz@607s2Pgvu0pH@H^ugjr%;Ax$c7XW8;
z6L5JrRA+S;y<z^GE_oJ6&+9bf;akH0e7dOXOdF+=bS`hfeMx7f6;HBm?gG?ObP8G-
zUe<Ybhli=U`fcF8qO(%G<*Kfm6(+9fobVxoDqWY^1zu$6YAKC*UDt~?E@$fI9|g{F
zLpO6QRB!6K(r(&YIvM@2w{_h*0eDCEH+>VCt;?mjM~=>U6g2PZ*2lr_JzZWOcyV91
zvkQdzI`1|B6zJlnL9<X7JRHOIK)0<E;6=K=eNhzaVkjH-Q1@yM94*nsQqHW@p*wUQ
zh%()^M__xT3#|Zmxo!Y$GkL7rOz(pyx@#WbuF!R*)M2G=T>;vvbld4Se2S|KeX7>k
z>C&muwV}<twYts7C#vdnkDmbWOqWT~^m<*$Gx+pMm(IYM*Sg;+NY<!xlvP3cM)wPi
z&|6*V$6#yH?V`ByJ6!>7qH5O7qBzfcT`Z+pKIk$D;G};_JDQ#KGbppMS)Y`Gwk`Tq
zg}`mq@1+@ui+(UIT3z*>F95JZ@3aVoo4&6vhHIyO&Kr2>uFr7Ll)^**btR;p`lwkb
zcIiL6h!NVOPaFqly!Fd}hH$SwGaH@RryoLTFdzL(>b9@`Wfzd{*C%y?il4si4jA;;
zr+g320DTJC4b;D`Kyg6-1x5OU^>Y}o9MT7|5FXb5eUv`8IHDKnQ5>Rw8;2rP|A!90
zL72W11r?9#fB6Z(WBQFjFc_|1L_->(zuN#|q`pG~dJ(1n<1RF#_2KxFC#sYB8RMXG
zN*_#NwHSR>7ih-nQ{Tf-oPG-BSK{^I-@)J0`i%$hxtr>Y{%t?#oYl{Zh2Q7&+c%@}
zygrymk)RJR0e7O_V;p=+(qEv2-6j3(ix}W!z0ZFjP0<geOwMJ!N(u9+`d2Gp_lkb(
z5O{G_Uv&a)Y5I?_t6Y_#52U2$b-jlts5ABZ#?kxlhW=$Kq*;13J*aN#Ym<Svr8iH-
zSlrf^O@iG!`cztxXY1=I*_xv-d=6o*{@X(^aZkVQCjjp2N8f=;zJ4AhHVgC-JpeD%
zzos#Kpx;hexFUToB>=_xSt9!RP+v?dTStjLP7AxG`r%4c%k%~Gf#qYpmj%Kn`sbGc
ztk4%;0-{py)gEnC`p9T-Kh^6L=u@@+$UYdX(HGLAp;qtT4ntC>AJhclGyQ=%;H=jt
zOJI4f?^p=8U+BGm1NBRNDb224JM?d?aH>)Nnsx`g(VwTCJ8$)KPlByUzeEAyJN=Us
z)SC5C^fG_1UrSS<4|*;FwatblG;!Qw_?Y$qY&Bf}1Z~?4?(~M<Zpie4(8Vy3)&Q=C
zfO53$FwE+O!p-o`j<%f!$4QEix*KNRfYif~C`WC#;T1(Hy$r4C$J=AD(?rbMaFaF{
z>@_H8A+*nsG8F(H!$Qio`x+LUg35lw?u&r?8Sbxvd4I#-G!qIi^vZ$CL4)xvdKP35
zUji3wD5UtyAw#2s5}St&?dTFXVpv1Th!Deo4k$tmpVLheX5eWT!cjvpr6i6SzOKe_
zg&QoPFnHWB@-&1e48DaBMj86hyCT|9vkTlO4Z2LIoHF=OE<MJun)b298V+oNPjQ9;
z!RXl;L#>Mgjb{z{6x2Cq`0snroHzXR0Qdxhn!;*{2J;=%E*Mg2Tj@o^KQ!Y^GK{?j
z?n?&$g(#8@ofJ?>F>o!bZUckthw7@qoPi?E@DDBOt{Im0gu!$}#J?yq46ZI{yKY!N
zkhc0{8baE@w;P66l$6Ud{MiP5x@lN42*O*2skEUb+c54DYB`1g%IxPF-aWyP<Qc-+
zp?23`{1jf?GptACTy@`&MbYVegXjjb0)r=QcPum%eha_@!)NYbDKh+RfrS!7l1_&E
zuhekqH{i<**)~WY8P<9MSZ;VjJKr7~%5^|IF;x8n?g~RFy<#g3tKULcZAhGmA*nI6
zc?c7=h5(wR)ft|3fyy((PAAmr4M)d-<+<UEh*5iC@Z1T&OT*((02&Of>}YemG905l
zdan)psE2P2SrjsFGVEB0A$@0<u^GT-!`#2n_TI2@Jh(p?hCBtglQEQbk~tfPP-t_r
z@o)NJw-~2Q#Q<+LZopT@s%^$|Q=z%TDE|R)H=~V(`JKjzv_5w?rscw{hr{?}1@N9m
zPwJ?bv4J81dyEWCSG<kmyFq8KabzvL*k??mC!3FP#Zd@-jphBpw%^$6S7`bfCv^wh
z-zc96y8*`aSs2kkV`C1A1ID(L@j7Vi_A^`yGJfZVTClO1_5>a>I&vO>^ssR$O<a!{
zA5d00#5nUNYN19KdY^<D>uCja)Yy@}KRsr=H60xdH_o{VT!b<AI@%(Qo)m^ZZmiQn
zc*3}yG9ppNL|Q{f8~>e#+DYT5qu|;p<3<Xq#~6R47iO%nlY_E=amIrpJdHQbm4H8O
z+&2`6GsaH%d{1@OH~?V+)j8w*z3}_I(bWmvPB7l5jeChk9W9wI828Xx>!R^USCAzc
zqi8SUCF3iK$tD|L%z~v9<MW|Vxon(5skKz&cL&jlE5>^gMH#Ld2TcZdn(^0us9iI*
zT><WNqoy738OFr5KwLM@yMne%V|_L}ykQ&=jQ(aB+fD$@P2**X;@mPWr)<e><E)kd
zmGLiHBxM_CO+{Od@focFa*e0%!%&`aogZ*_jTbDm)%Bi{KLFr;V|F}r@{JYr5GpWE
zqojDDaW4IFfd@t}dT$pQ&%K69v9WUiY7dR-n{cMYm^>OPrN(jjz?B)hje*J|<GfmM
zmK(Ry>-Vwor9S{qjNU^~t1|vG6PizrS9?+XrP}CL2B&I_0ZUNS8a4F5s53IOhxwWD
z_8D}$-WW_lsOQFEJ<z8Y#=Cm3y)-71+YQFK2{8D|IQBJauZ<7=;ZvjWb|`9ZjK^s5
z@Yc9|H^`cdgXksx&KQ0OD$Pch4WM?sHxB#&{0HNWO7z#s<SyaIb2d3BT(;TNNM39)
zMYCwzYFfStz-^|NG#%V->M28;i|J8IEZEec5Z>=F#nF?=&2%9j@SUbj-@prZ(}&NX
z>0w$+n=Cv{eza|6mnowjn!6pQY8rJf)7ydYbdRY&{b3Am)4<*k?ltAnJY}EhA$^J9
zV+tTrUsD^Jl<qh6rf8d=$%9sP{-*J?$2`EapM!^irc`>u95A(|)XzaveMhhanc`lf
z2sZsf&zVCeU)nQt*yQNth3XMgAL?(2DVb(jp{B`yV4TBDgASs0)FjboB*#plZGjIr
z1q?wEVUp7~bdjd!ESNZMni`MV3DdQHa4pIdy%}WDrZD>4=A=nU<9o`qXc`=iF;!BQ
zHP&=`4aOqQRO)yJ?s!vfI~1o)(=&lTW71O2=d8)m3bk{lf%NUdd6TsU_yp6cOW;m4
zZ4g0o!Ss&~xQnI^O(>E~@wBn>lF26pfXk*^r2wRwoM?mI71LRo(O)&~pp{~pY2|RZ
zcFhz%k^YuPy2*vMsAQPD@b#|hy2(a=5hv61Y&D7-re1%8JIi!}a`87!%ac*NWm<g~
z_}eBI`jX*}Noa*0W}DVgxGTrxLYG&rDW0Bsd8SuwQM+rJJOwKEOvCy@<-TboO%U=;
z{5wi@6__s2M`4Agjr8JtVA@LW-6B)#YB*eMdN>iahbF(ZFj!(5KN+=BlZzbOWu^sI
zust$OrWi@NY2pvC^w>0x9>Gsc-*p0Kg-K1@Rw_-u(-!6`Q`lJGo|?*O_gS^6+bG)V
zT4NgSi)yW@vJR?srjjUl@yv9kC%EfPf9Ws?&rQ3#!Ndzw*K448X=+b-?*>!nBPd>(
zw!}dA+7v(^<TaXpppCk3OrOwu_pK?p6I7Z^TAI<nGbM+@`({%<<t^Tu9?{k1_+Xkz
zL31bb?wc^-Y+j;-7n{w+=YiN_zDgUuwwhf}1Gvrn?^392H;3+oii`PITDZBIzm9_W
z9p-+0z~W}!NV`FHngeoS-rc;i2UtAJwb3X%&C&GG-DQp(i(<FAKg|QZ9OmSBu<bFQ
zo(LUpb35A7w%6R5(mngk#lNBOF*i-c;QN|G=%Ksc?7tM6e&$dYjAfwtH+lvhFt2Na
zwu5F-KwFUcN7^D8Y|d<l-{6p$KL+7pbHX!FA2GZC1rI~av46pfP_v_y2X~mcY$Cik
zYL2F5<T3N#AHi<8Ibtn<5oUoV2$ALz+UR@SyvhcZ6Xsti&=h4pm4I5bxw;f8C(U~X
zK;@Kq7Iizu+<pm6#F~c;fQNDB6*SR}H~(`IfYatnG-_weE)GgAoHd_wMRCq7?+(@T
z<|IlIB$%}s=wYIHEsNrU`5OtvMe`p8D3Z*dQa1aNxt1cd$>xY=SV}Q7Hki0<?zaVG
zspfGF(7a-vPY<Z8<|fLHrJ0}E0Jvtp7>wU1-MqDd=ARknNfeN{ZtfL;K4qE*d<pY6
z%zY>?n`KUz2b!Dau}eX7%UpIG#clI4im}`=t0@tdZC2iaW{!CnEl+aICG=#<GrL|x
z+g<av64dUQk>$aSXC6k&)_n7yKf##-bJGj_ZAMk0S)j$v1M@Sw%8JbY1;V#tvm4Fq
zADS2IVZOxtwj6Dx=IyB{%FMbjIQq!!MzN@JbLZ*Md~D96{VGq)5f|WEg*oRY+A7T#
zDT!WXUQ6?nr{<F9(5yBa8ezW1{2oy{hpN{6tO}}i<`Ija^UQqkDY)y+S4Ge~H=m|U
z{*_sv^yO=F=GVYCn%nL{?TtD4G}_*pohe1wWEQ<){+;>G5EyJWSAT}ud-E;Yvi-rl
zzBhgmC(Eup^u^gyv<$V)mcBFzcWkk&-i7K`%d*uNy=|7tO5nF!deL@O7t7!}IOA#&
zC!yOrEWWg@!p-vMRrtHpQb~Vs#oe-=c2Ia&Ru6+So|gOq)OK0EqrDQlEfwU9m*pX4
zZT46MO3-*)+$fT^*W$S!ZTlRSeRp8q$MPfHB)*n5l-AyF$(adDewI>-z4=>yrXXQ}
z<sHp911$quf$e~0H^m$dS{}qfCCKvIJ#;kKQtgViLl)1&AUkZiN%zPR%UFuJhgd$)
z+CS8?lJ>%cS-dl$dDP-?34`>Q#gDd+g<A}*VJX5AOs||s%Ua5k9k(zuL36^=OtZo$
zi}NEC(H8Ry7(8jYL3hk4OY$~26JuGZgxy%nn@JGHS$>v5Gv0ELLNuo>vuP@E#^Q1r
zWM?fadqL%#Wu}8RFrK%h{|KiNEPwnBokUCIU?477+?N1<(UL|H-Xu%yc_1!Xe(eI+
zk}dzPLR*UE>Tv)rTl&!UqEySL^bNoj%St~0u3CPfF-)`Um<5$<mLcKbOt*v|!EcaZ
zNvB-bb<6EfDgKga>2v^y8<uSPt|-frPs^&Cmg!Sr@RsFJ5J+!ZP7R0fj%5<Xi?S_E
ziy_RhjEThH<yv+!XuD_mWDhLew~SB4Amm$)3V;__iYPWyXbE+N`3IH{KSEe!Y3d4l
z#g_JyXshu<%Sl?Yl~^n^Z78*DTo0ehEDI<m^vDuR+px+l$NRz3V~c@i(N8R&(xq2n
z3B3pIO3S~4(N<+q(6#>5qIQEywdG(Oa5Way43O1YuB5}?I?Dq38(GgRQK10TTV5Q%
z-)2=kw<Ocb`h`U+1KUf>R@$7^V0qpO_*a(HQ^3Erj17i|jh4SD5AenkFavCFEj+!4
znk+dKjD2UhNtym;OCDX;?=6+<fcs#{dI(3ItUGO}Ia^DH;TPF#-S;Q#ZLxl1hCRnt
z>r@H_Y_qny2)o;@K5AHUv7XxjZddEL$Kc*!ol0Bj+^iEQ&$H9&><9PVtvhMe?P2|}
z8k(NgQ~9vF%ev-2sO+}(pzSAK*6%KZY>#yTy+^#Q>o-7Uul4O4nBQl8vJXNZhc&qv
z+`iVa=U{%nHJqMoe%2UT@A_LO7DFe%x{(43f!4S5Ve0|w)pj5~XmxXei6H9_FHsA&
zn&JRIWc`lTZ-=d2j{<PS8qoxm5bFuLsY0z0FHnS8PxXX_qt>p?P&sCG*bl?0aO*O9
zCPi4|XiXexT{;T2<JM&Q!uo`@17*jetmb!Mi?-Sq0C3Vel-BpBtey!_iLuU~4$@fb
z$#4kctaCnrX1q1^KXml8b;1j%oUukyDEhp03grkAtVy)MO|))z+(qLBYXd!#E?U=U
zP$XGT(yw;O8b>qqWNRV4ep9StTf>XXR%QZ<R4ZqP7gwxKeF48}RklR=tbgYKcg>nr
z0q@hTZ`-1lVSVU?k-2V7p`cr)wc`xbZdlvV-nlGm?{f~Q-n71@$p0<t+hy?Wwzc1S
zG~Tgpq)oor)+G8mBgZ;+9ollOF|>-!vyQ(7++FL9GO*pV4jKaP`_?ag0m!$`r*&9?
zwR{KK3az;baP)ySbq_2QS=Y4#uGrc>9V`#6oqwVGuf+PAcAJ-4XUv1$GOI=a;*s@3
z7>aW1`hPK`kFDR)qW_6?7_BBNtRAxgsI>YlMXk#EGp#0{T8GjW$!cp5kD|tUCmMiS
z>vW15*IECf%^J_F1E0f-dh6sT06e!w+Ufp#VJ-BB&P!{%J0NYa;xDA(#<R})6uo$D
z{e)g5jn+SCgZCS24f*}nnoaw+nymaCn0ROPGl9F=I`;us-dmIRLgj<?It5dmY_4n2
z=4?x+70hN^V-3u2vE`Uh+iJ_upv|$(R!kF&?Y1>DfN-&mx&TYAw);6Szr!}0J{obe
zEk6Z^ciMiW4H@pXJ3j&FVVn2|3Qt=ct%r8mEZG3;w(ZOZx0g*z`Jp|w<V$Gtwq2q%
z>0VnDy{Pxu^d%7b*k0D6=IgL6>kbq9ZF^{=r=M*ag?|EVLl2@C2W&44s2#LT>kUMZ
z?MgKq4YsYLJN1z5GDQ*&+dOGk*b!UNJlGAf?LP*xP+MF#6k)ck!(cgT>#YLrm~D&`
zuE%iOx$i+1VY6!hkF+_4=fT8rn}fyZov@u<fg;M*h4RDEwvrp5IcZawKy%7gxez8|
zY^~@q8*9^f!{0dDBo`F%w(k=FIBokb5AZWKg9?_;+LY_icFty?sMUE}4lTtKY*Q(R
zlV~&UhROxoMhB&BF52G6P))M!e+QjQwosb5Cfh!q3`;4tsgdyFvhD0Y0H)eldZb;k
zjr$JWzG{2*1?;BTY^Tt6&9=Z3wRGDT6vEE1b)z8tb=yx@;dZ8N&QS<&*d85#hgr4`
zTS0x(_Qemh{<~#!`y5`}woRlzu5riqW;4bs+vfiXOyt=9@<m&&?UNfo<k>dU)9bG7
zv^P}l*<8=V;C<Uh`cyIB=1dEy0$b?MFi~imn+CuGTRrWvEwZgW0`tW-j}fRnw6&vE
zZ;5SfCH=XzQrlA62U%w8N_#>d*}UknRc`B<2}_S{ljoy&V*8lB=dG}POUr~x+Y|{V
zs%)=ofO~2ic^stGwl=ivt+8F~1xvNIIbmq4v+1^=_RQA06k}0ubIO3`bKCmQ;qMEZ
z4<_~w)k|Ao6NbCN){zqEuWZ{Gn0ReFFaj<%+CG~JyKiiNAUmLXYfGoE{F-bNIQaD5
z)^9FqA8Z>J!-SLlN*kDPwr`37e6zhH?Sk84Kl2_2x7x9R1FtxHDP0%a?T09F;9_T&
zL+Eg|@1iu*4tpP(Qn=Ye)1kA|e)Jg(y4zD8g4@GB!U`2ndjdtKcG>q*?s&Jo_dKY0
z*;~<Wi#_&!L(pGuyD!a1_S(Dqp|;O1VTG&mu{WvVg|A)z6AbRRyVK;s&t5`bkoY_7
zo!X+?0ro@mm<_at^B_H7pG&*h4%&B6k|4<b^Z`_Z?H5M@c*wp!4K#=CgDPR^h`lTA
z{0gzhFGmq-=RSo>n0;Od;79FKdZIXH|BSYph1(Yx0f?|yuY^yL_PO-bI&OF5)6IFp
z9+ZwE%Kio+F;%pEm;j$n+MjQL>M8r`)d0rWm(z~aSbN=Oj8mL_bRT#TZ$C-9G)~+5
z(nIKsy*0h#&f3d2fb5)oc{AYW?Lpt5mSC^mk0R0jh@81#&npAqqWvoeEhUod85A?T
zWdDQyrbx0qAOe<B?C<H4zii*L3?@?T7irpk#a`%!9$vLCkB0d)`yEP>U9%tS29|XD
zsXUm^u&?xh@Vb3a2`pvWPXvSPhCPk?n`K{56RDf_RutB|WgoHYBUEqOqg80UW1ssL
z<CSecv>uH)_CDTG|8#Y@?}bKzJ>WK|3+>+@f#L)Ep{cO<(4HOv3ng|-XE<1D?@Bw#
z%j|<2fqrE7F9xpM{)S>^kL`o$!Suu)NZSJ|?A_=MS!o}~z+9C*un4uM_U{+K&uaU`
z6{ywNchbJTTKh)F0O0HFO-0~-X8-yJ=+xW0(ubMP?FSct^o6}E#V=mkf4Yc)X|PYH
z4IHoRtLdAM*Y=$TIMZlvrd;tGdk4xTzP0~<IJ)lm9Ir2qR);QBTkqa`FI2Tkr?!+<
zi&kliYIRV*YK`*Bl*o`xB*-E|rtC<B5Sg-MFWDlAkReMXzwhZ^=X35o=X=h*d7t~-
zd(OE}VqQky<Arb0X?b#?rx(bRh3+meIJI!pA0pEW5q!Zj#kl(itxq<L3<|>9GIr8;
zH|!W`3t-otp`3)G1EZ1NkdBPPA`I;qqtyqlIWZRej6P>ZAAOqYIOFSRh`2D?X#eNR
zh@kwL8)L5mmfRWN{STNY7%4Bnf(IjSABZQTi5_V$hB}z?quz||vw`NrIQ}oNeHr^U
zf%9WL`VcTD8P%NtJ;f+z0nMNB{{P_GX~s{j01aT=S_8X*j2Q<Za)#kY$Dy-~tCxU%
zj&Yt6{6UPSF>t|*gTJFMgweAb=0h1Aie`i{wjv~Ioqe9Mg4XN{j9oMr;S38!{396a
zX+?@;EZPkc#rT-w=ocA3{0_-z#-}@g9mClB0Z1&PgUX`f82@|?@8cPlBVZzdVfr48
zmlzAifSJe${Sp2qG5&PL940et8-ba^SV!M*x27_7RG~ACv9J_uI-|T9of(Xw9FWV5
z8~td^Wc1PZAhQ@Z(g1pe;no97*^Cw{OvquRP|4JFMlFTTZZNLVO{QGN#zKhPWXy7h
zGkJ_>=+&6dm_d(p0mFqNm4%F&d`K2q8Ny?5v6zw6j=8+Wuu}H1gmJGC8l{YXC}mZ~
z_?@nbl{1nl`B}lZT?D(g8BKFQDjD?@K&WCIw1<b)j7Ud_)G#ux0=t$W`~-S+jI(s)
zuV)0`fkFf0;Bold$k5VK(8RD#w4k+_@rce}cNlG{5N%<sj|W;Sqh%vT-^MUe&Z(Vo
zhf3l)7~`~e?_~5(gX?0nCBej9hSTRD-3*N$3ilYTx8ZgVV~nD`y^L$^AbpI_7l7Pn
zY`g}Menyr(xCabJD_zKX$k<08EgE1P+Xzd8jQB@zW{A;8Z^&VWc^n=-VyvPX%Mr%Y
zi_tgAc&`ZN#~6Q*`Z!}!0fQ3^m$Q(3%vdPE2qzgfDh%QY;~NvWDMs+iFgVRPMcezM
z%o}u9#D?j;kLuHHnQv^zblWlOzXGvm7Sh|>ff>IN#F44#g~l=Fbv4X8F}v=<eP^aS
zeck>z^INKfaA9)NA>zth_5=Fdm<EauyE9kQr)EwtSJGR-gSl!69Q9<nECuJqZ2b-*
z-b}+me2#gx4^v2GM!w7yl%n%v&ZiyyNv4>pN=`AKqZ7P8^Z93B=`=I`O(+I1$9I7X
zWd2IY^fSz_>Ck<aX)nW+oMVm$fD2->KS5tGv%wiYg)uMFdVHQakGAj^m_<S0!kO(p
zbQLLrnMYapNahg+e2Zcx(jMR<Gx{>d6wSQMgikR{FZu<?GXHS{7sp)rFGS**A8v$e
z2~5s)7`(*%gd9y|rc#<EiCIlAm1HKr11KrX`W<LYWp0tfnKWi$BS<>4nbIuQ4Cd|{
zpj~F(+zOaX=8KeP$znd955+4?rw>80nRCSO@GA4W8cfMG=8u^eXbyAc7ARb2swctS
zV7^QT>Rjd?XGq>;S}6jM$8=i*6ZuSO4!8oQhd-bTnS;}Crij^n0AR&d<~becEv9<`
zMp(jpD;yf7%<q)IE@QUPN3hD7nGexd!OWwV*=?r&HJGSm=1?-BiWy6fVKuX`0(vz}
zF1-_LnO^@T+?YCw_SQ3>dlRIA=}D)AMy5v%NE5S~wxrEW>pPUXy2EVq#>}=beJKmk
z$}FeLR&C6JLD+3)YI{LCm<LY6QYZ81I@s-E7PW)iWj0Yxu$#F)2<rEk^QgwEhv`Sf
zy1mSu^seb+!X6$x=D&1k?q`-!0q_InAtShl%qHt|fEi$3JP4--nH6*x9AYY72ih?6
zQ~Jq2VoG0v-4W)e-T)nCen-U;W6TGifg5MeZ~@E&^Gg@F{g_!nQH4q7B72BDVLqai
z?-cX*qcA_s46+3|%1Wg9wPCHyf<0SSViK+ScC1Ys;glmQha#27ShnNnbYe}rL&KS+
zqS}Y!tUvz-nhWb6imkY^E-r(f8|y6PDcxDZ5h$Es+0Z<Dur9p-e?3`QbYApgF+0%b
z&3c2Ldmq+zKe+A7y03seKUU{Uv_C(|I!eFUQ>;Ws==-xW>A^kC+N6Rr0j$K;Fc`>E
z{sWOSteiBEvn*i<Oq^q>5}**o%3cPAV3uqg3Lz}bCMblmn&^u@VXReDpmUzJm)5Wg
ztedoYgtG)$P>5j7#5UVHJCfxX3U8uVTPc-uktN*;63y!R34X`0rs!NB%c`IPpE%YC
zRmjA%exz^PB(RqL0TY*4cGp1?S#QyACW*DP3zEq!kt0x2SRYd~GL_XxZ_zZCc@ad?
zS<ldqG=sIT1CrLuEWaUG%4D4xLTeUF(gL(Atev#3XR}UHO64j`I1cU_>t*^BUJeU)
zqVV9c_ES>s21`r_>Ri^DDPZ4ZmC|M@k2SdiDEX{LDiJGS3EqZCAxpLp7K&KIlwl}l
zN$H(>%gRckixwrU1QrxaS@WD>u#B~y4yfg<;*TIx!P3w>?l$Wdm3>#Ts^}vbRjg>5
z=W5oA^qZ?;y|)y7wX7AC4X9(iM3Jm|mOUL{8dx<FaE+|EAsA|6dCM`}X4WWOe!au8
z&ZCn+3+u%au&u1cQy^`u_4JUmv-Z(fzB^bWgMjH|dES6xH|zF#G~Q#KKMK;rihF>@
zUKWRT4SlR>y1ag$_3B#m^|K}^F7|-s_cTNvvJ$?;bPuqCe*ibgYKVct5Nn;a0y4v_
z3+v(HBi74Q>oLMQOPBCQSxf21HpbdU->M&H1<~g<CRlqYLi3olh|*b;tQFWo&3?jC
z(%yfHWuc(eG%MN;U`N?DT_85>m#g5DE&CT+49Sjt{$03c&%XK$pdHw!pHO|QBl`vw
zjvZsiZh(vv`@38aXZCj=!r*asG`&b%*tT}?+m+2(2{bo$SveHk*^Op!C)nT7s^!66
z&;@5a*?XJeniso=BFWzDJ!Js%VRy3Nj4#`Zwy%Ed5*hkVvgg#({j5{$y7wUC&mN`U
z)oJ#J^pg)@hdRQwK=v()QlDWj`3~4;+3ZUg{W<pE@4>Yow&(K@31*9*pf7}-V1S8G
z_J@?~4P(D8f!=xcU3#c4u;;%3=y3L9T3{mBJE$lmlD+;KosXl~hl*kTB0G>?qtWc$
zw!n^I@1iqsEW5T0TpYV*5qyegdr+t_f!*5<$xH0rvtT!o-7^A`#D2L1pvi0-KUhj(
zm(GQyRQA3?NT#tRl;=-p&o2c^20MHY6fU#vDePj+WWP+=xGc6G&IGfsu(@ACBb(i`
z9GzF$5?bf3v7b=gN)FpsifOyf-ta9NZ?IWhxR%Q{(M#ecJB+r9dF=KkG#0XL8_-z9
z{vX{*DrOJRJLVSqS1!z#uwSr&dMW!-0l2d5>|m;NDQCyg2Bm`C?+wM<?Cn&MP{}^l
z2`{SHYw7u|W(Rn}L=AgAJ=C@AmzpuAI(91UD(l%VWumWv{mwZkG_udr8McYtPlaa9
z>`w0>rv=stCdSal{{1nu+u24cMeAVO(PqDs9ljEMUF=(w1H8-LN5kx9JJ9y=9(#(;
z_&w}Ds8X?)?f)_q`q)BBlHO<kOp(-n_Iu0F_kdkRXY_~c=&L{(U|*gAGRR(g4k$zH
zR4X4QhS`ti!u%uluHRr{gsrDa@=<mfB@xEhZqEa4oLxj^K@;pBXh;2+t(XAJBzvV1
z!+gRHdKY%5*!~m@oMx{xqwy%`1qUeDaNZArf-Prk6du}f{-lVrJ!ice%sOy3+@Keo
zBWH^bG>&oJp&XSHCxGHv&YY0XL5_0*lhEkG8F>cSuAI^%;M_QqBJ{a)zIz3YCpbA*
zKs-1<QVPVAbB+FxUL5Ta5O2=66gT(b$i?_``f`HLz`P$PE)(h}Ip5aPMXXbt#hviR
zpEI`y^L3iDhju9eoP^_;gh0;V1h_MtXetXj%Nf1_m~))nYe9lIi^iZ3%#qK8r4UX;
zB+Q3$?#IBxFwXMlFhS=z&xWG!0w-o8`ocLnK1c-TE80m%axUPK2)=p8`8WvXV>m68
zYKrC5Qz#~mqoAm1Jcm0IeF>bLLcm<&Sl`A#6FDj>N=)Kl^NB}`lSrG56wV2HeWh~d
z(znghIIZ>I(mBu6!kG-t5&D?GWzIah!;r~Y@;flIIOi4s#d?Kv;1Fc8Idiu`@hT^P
z_AJ*p9nHYb;XI%x^g5^64crY*aV`3CIlUB6y2%NlbbB5rWDXq7=M2&nn*vU1H!Kx$
z%oM6F;&AuEL@}p20SdP`zh=Qu31?3MFiSZ*w?VJW%K3<bpXHnxYd|VEA5^0CHfPcE
zaHf)@qYs8waqeA%Vl^j*UL!S}=3ij9mUEvDY;~Meda>7Y_EV^!fwSi=aE+Xs2J|&?
zB0hp-Gv^H5Kfc3JuLo)2JfTZgtsHAA6xujeyBFYMJ4f?3G&(q~sW9Kk@%ao6cX8H+
zV-$Be!*men=Dbcjy?dNj&qBY4Q<Vfuy&PU6B>OlGPEfzkSv(03`#Ha<!9Cz?sDsEu
zPOKi>0O!a>4117s?qetnacn3SGt3#Xegm0Doabo`8sXHs!_p|{ZCW$OINRxh-#7;q
z1bFZ`b$>zfF~>+D%}Gun9lxG%{+EqWOmWQQ_B2OL*@~mw^He!&!+nP~sJ7f~d*PEE
z*We2gd+td`a1LB93!`@A{#Z;0y<^;8J_T{&E~n+unOi`SzT@2eVbFKsuBL_GoqMbe
zqd37`K-GO7+|OMA<H;?SL(hx5leS9U+<Xd$`EdOlpy12h)(PUreSJGnPI4#cOm>Pp
zz7+%X=LX6!meX7mo8$Ql;12HqS|Hc10WO~5x{N~REVp$lxO3b?Vel!4`!@aNg1Nd)
zPz>Rgt^pUyy_gEUFz%rbpm3fWOmXN7+@~n07S8>%1AP(Pd2vvP<bL=Gz@oUaTOb#?
zbN?$T;X1j_!1EWw-P#M^V!4}Mg~M^&ms6k-&#fqhi3IK+mjQZ-TQCEliQJe_=qGV=
z+<~3U{eV`j6s~MF%%^g%YcUsT+zoXQN#}k*)ixPij}Aaz=8n~(F_WwJgM}<EgL2YW
zxSxIkL)L7rLof8Na^Iof+%>NFWhmxwi<&{Mb01Mq<ObJ;wraWDJvwOI<VK}pp7Xex
zodC_}zD^5r0XNJB9u{&d9H3CdjrkK?F?SoqWp8npzmCQd?pKsVE9FkqK(CCOPh7c`
zD?SPR3a-E&p5EprQO!Xmx92&?RB^xm6pGc{G#<>?a6exUky<W?0$O$4jhz^8J@*Z|
zXWPKtOTqX?uGIx#P2B1;5NYOye*^9g_uxkub_>^uK4jm@b(X=kHf|W5ncKNm+a~CD
zaQ}W6COWy%(U9rlnkejYmuqsw%ye@Plfir3dCx(lhr3V=kzVebo6y+DJ$Mu__qm(v
z;PyjqYa|*6xD5Kd*&ufZP3#bN#st8Ixvdm$dBklDg8B%za4q~D<(jNiOE$*cLJ`t&
z?jqV#PH^whUiLBf_q8xM$#v@ldBQ#aCqSpTkADG~<{n%Qk)u4u=fJk%Jz0Q3*z!0*
zAa=aV<v_9Ly?zOL4m<{Jha7qD<U!#WZ!JB=PP`n7F+1~~Z?>ZIIBz?Ja$R_Z6clmg
z-K5lw8}IZ0`rLVa6jVRKTTH(>58jJ^0>+a!O&d)w-UwB6d-Ikr1DX$S-VrGH@=nr1
z<HviQYQawOmQZr`6pyDxpFgjk5(KAt15^tgz?)@D8_hso9gXP>ZxI{hEHCF1$eiP~
zK8L?r5bw8T;DUKu-bY^uuZA*Cp}b()XN2)`JVDO$?%Bh{1ztX-&BA%#Q|>;3w~~ew
z$&026gecxCo8aL^-Z?tsMDteN2Z`ZTAQWqz9m{*4ei3oJJ(M<x=N+Usd;)KPYIiR2
zwo{o*A}{4vh$Qh=zXUImc?I-ZNZ}m{zz9=$p%Ji@#?!Bc7wNotT6mGc`{z|CT;^^5
z3zjl@LzJn?;u)#n{t9oLqD9#})f)6!ukt=ELFYBzjxDg1!wb3&{p-B@KVqOac(0!Z
zb}nz|Bt&lVHm^iq9`B{ELGpRQ>(N-iTQ~}|LSFudz%Jr#t3_Wiubgga+~Td=4HG3i
zFRI@y<$d`HNCoftf8h3Qp79yjtF-dmTrs99UPdSst9ceW!`ATL+lkIv-T;M{>v#c7
zkb0gEoy{6}JE&l)k#~YB!JByRbi-0JZ*~FH@9+kGhe!)gv>e{I@|u)@ZsVO&LcN{$
z&70`!;LWGpa3?RAt~Yh@tVPLCyvy^Xw0SqrWdX47@wU-6sfQPE67$^4OFE3cKHh^S
zXx!(WYzA6Cj~@W+2fXJGL*XH>fIbj8z`K(TkwKnr6Z(dDU(+4hVcvFnn?2&~B=1Lf
z&(gtVl(&!W(v9)tR;s)m=l!rB<DK9|d<g8vyi^LCPVx>*q49*blafPIyk{wnFwMLE
zE6|Sef1se14gY`fAh!G;zXqBeUw9dR5qtiRd%-#IUB8DHj(q7nC>-O@kfG0sZ~hA&
zI`ea*0Ct?ey_fc%F8p2T=yc^bXM%I%KNLX2oj>a$%%9-DMy0bJ{AcLJ>B)cYC-iyo
zf1s*OZ$3X8oDcswT5Wy#y%sp*$5%IjoaAqy75o(c(wmqdfBvWw)KBx@qVl!?{)u(y
z3*=u}O&3AV@ZY53`m=nuO%OfDZ=~~a5Pxk8xM0409MD4eW(qxr@{b!}FpU3MJw(p)
z|MwFHbAg{oJM(b<oBxGR_+L<hBa&ZBpPPu{ZwLYOMScPuIimUXw1UU*x6sZ!mj4Ql
z&eqv+{MRYw9nb%rPNoU`ehM=s@wcTxKbdc)+lndt&9xw@{AV6QB#nQUBD(4PRrJJV
z@V}st+hzW44>*&_|8faP7QeL{<O=`LXK*{49~KYuSNR_FZK`YhA1I)k!*8Knn)Nzg
z#R0v+-%UsUT>h08Vd5r#lunj;{P!n8^7-ahK??YdR`eC}-$;bNMf_4a<rMQv>cHLN
zJAH$`5`HJui<I*7_~6R;&hy|}Ilq{Wq80p8RB?2h@6N|qD)}2JPE%#&&s_}j)%*o#
zp;5yh+l|rJ^3OK{w2uFXPObHP^H1O!___2rHS(X01!>}M69BuJKd}-6y~D5f0$K~-
zaXq+J{@)I;)W%<X44CcwJ#WCL4t`u7NGJcmO6Ya*m2}R$%eNXSFWSw2iH?Ey_+LMS
zOb`D#3N!WcchZ@sj~`7T@B92~D}dI|m(zu+2mDfc8XxlOsWNPUzkdLrgZyXThrdJo
zpDE@%%ukj<?-9R#910_Rw<z?D^4EvM&=~)f6hM#jXIXy%o#3wz0C~*cOyzZx{6M;c
z^o0K&1<R)RNlP%^Y5pt4fH^9d;R8?`!AGS)vlWEXCfrW2VLtTi1@kEO>mYDR0&x`B
zzl^aQ6a0D;#7WTb02AaaSUm#F<AOg9gL4ryXvtGof$h^U=q4zAA877^y>t>eA;_XU
zhlk*fKSVqQOX+CpC0I)DR&PP(4*29J&{4_4NkJ>Ey{81({%G_U{9OhUrv<ktYZxFX
zje>fh;0M~9o)P%!VfU<Hu^59mC&+c7Lf9a|&0ZJ`7VM{FLWtlqs=x~suxNz|6NJ)H
z{Jh{L6VNUQHqu@%T<}&tU?K$H{tN6#!9zMQMhU*Y2b7C~eH%fd1)I0QnHYf+RoTP}
z7SqjyI01{!cJTtvhd@aX$gp<ee+~$0sGv1bFq;CyNrKrg!~JBzPCJ062-a<YMyjAA
z0*z^c%-P`51<oR1X9#XT0?cK>Fy*^51@;ss$`aJj!+b@MOO4qA#UIeSD#)O#$JYeK
zLm)YVBomyuE(o0q*Q_@Lf`=GduHcI<VBZuNC<l`#xVH;3`GN-etrrMfDBM#hP<;o3
zMS_=UFJCNBQPuS=!AsjPT_plPH}sVX-lp_HnczO<K*|MY7D2K?uyZ#=ZVOWBvPPw#
zhXVFhg77)$tF{VUDHL2I;LvNoR*+8B{B?rjMA)qtte})}gCN2N*o}f;>E3sf-~ugv
z&4M%vM&1!bQ^c@E5M>X$t%9=ufwT#Jq*O|~z=rZ89Rl+x6gmZ=N*L@CIJctjuE4Pe
zjokvPct7YpK@kTqJp#?Y@U2(C{|eZBg6!|%%zeS_Yv}72to{i44+Q@6Fqnsefh33w
z2u}Wr#zDb+Tc8XHMh0PiSn%Ob7|SEUZ4J0FK>>xz#{~u|yqFN!a?$u$zzm0LlLC&F
zPJB-U3R^feB^ag1-L$~A3goEp#cJ5K5k5HwMO$IsNtmz`{!FW_z3`u8a1O$*V2C&h
zH@D*Nb4-{#2%nsUL;pQ$LIwpoj|=Bh6wyWax)3O?!VPaj-A&jZ2nBcHnk`nyoDjZ7
zmjOJ4|7(XAp29mP;J%k|nhHj|g%=m2&qo+WZ&P34F$Oq4VL6@1PYRb`2Iwha&Q0|B
z3u9<!a9Vh04f+CvVSi!}fx=Is(04}oDs3^(3e8l{b57`R6(~W%%^y*sFIf0X2^2$w
zHnZSqsIZ5AG-1N6&fv}q-=t;hf^Zqd4#I_9YoH$?{DdCZNa1{{f{YT57l6Ac45W1`
zTG*b2#u(vq^oEZWKEDo@;)GeWPly)=(-N8>Y<>x|c1buAPS0PWa2Xr=Ny1|-a5!1G
zDIb<nggf@br&OV40rb;^lk_rA7cNl(J45)#@94WM{AVrnGKF6~LSL5fpaJBHFn<UN
z*+K_7Chw~7NHPpw6JGcP&^f~7a`<#zc<Tww-w=kb!dR@i!tAF&ZwgOP@GDQ4o(0f+
z;SxGC6$r2V4N@p<hz4kp@Zn)777JgZNaHP`JOiL5!YKMPl?tDxcyyVtJQZN&!lumt
zs}TP30rYMQH&T?iQs_+^u`1!(I*3#YWppv3#wu(&0H^AOo9Ol3AbevVL>q;%bnI;s
z7T-f(v+$EmAa{ga4InMTDjH0y&}jn<wh2czz{7Uo%m{eVA$;>?h;$0MwD@%ix%A-O
z6$a3Zb_-WgY2-cOa$353gz14$=oMNQC1OhZgePAE%zfeLC-ALb_^AS&4}^t3VV)lf
zv-U$|K=}Q9=no1f>3lIHjG{yTu&~(!eUF4W)94!!hPJ_{QQ=Y?>}QV&SFOTyjSCgD
z-JcM$4gmA9a4qc`CWX(%!QK;LyY&NjGbPl~>u_4QmGaj|MSoKu&_*=)H2Q2sRnb7R
z6O~eK&R+C{4;Tkg8NEgwMUnj=$3%iA5GPR-MPr;rOXDDNT+~T{CKpiv1yfx`Q=foy
z6CI~j%U$#<<&RH@bhGIB^AK&J;Hal)Hf?jfMCFkfg}3Ni4v3G4LuHq~qHX)p=O;Qq
zcQ#In7OLUlDUo9p(ELShbPM3L=pfxC2oSCF1s5plodS18l(h)lS<!te;yNd~Ux>ya
z(cNJ*28$*h&_%2eQ6w!}p`v_BjE0Hw&cp6`k<EJ;%mvYXPiTaTUi=vo6d~%}2E|BG
zkQ#kaA_gs*7e$*WeGo00Pm6VosH+8*VnufwLE=Q~ZbKwq#QGPbPY`XPyvik!ei{mi
zqF}5#*4as-v_lY07De(QlOlTKGkB3II!ZO`X`-q{u#_$epwfv<(c$e-%o2G}JmZQ;
z^*MaX7Ij~O-c=FjHc+mK97;iQL{XGlzb@)N0)KCaZqn;BSG4>9z;24J&`&N;BoKgD
z^F^Isf)<FjM!`g(NGpVXktntZpv9uf*P(bz^b`e0N<>Syz+kCpTPeIK6XhI(iE@!S
z3jS7zzGXn~w&?8{aII3rp*>fXXu1&wt3}SVuGWZd(rdp~WU_@`o#>gJaIM}d^4SE@
z2GM7B=xh|(-vLaMs5Jte&7w#S^zVqactE5@wD>)Uw2J<m0e{;>wY2)Qi;71<Iz)?y
zVWLwsPQlnN(MmeR-W3f|`AD~DGi{{qiL|t8^@s{27+J3<iQZ9tB5Q35Oxzc-cLTIv
zv@-;DABdhV!LT2SL_a}sK=h~qCI&@Y-GDtLIzdazu;`2rxJRP#6mTP=z%ihVir%1?
z#F!{xF8anr8~wmdh%yp@`B*fMisL6m%%=eMM6~@0pr=H0tQ4u87Rkmi!lU9c3Xa-{
z-^_=3Td@;eUa}JpeGJZC{O=ri=pbGc2I46G?7z*WIEeyOPU2<?h&zkhuENA|aS~05
zi}<-6&~p{Py9pND#C7x`9Cxu`FBDFQcbGvu#9x0y&!4CGmp{<yB@Va^&RhKXYk=_)
zr_nalSNwt>rp-^hWHwBk6j!ukOsB;5bP)0vKe&X()8fOwLoYxqp^B@s;^An_`Z;l1
z5cGn?EnM^ki$9wSgCXMf5%h(MmolLjCZ4m267A>3PS0QxFNi<(gG{*CHXSA+#HZI`
zh9brPI}A%v;;Eb9E{bzrhNID9!xNAgaRqJbV#VEbdW{qB?F34^IFrtQ3E~R++|nhn
zBgJ15#d|0aktBXU3?x~+iz0w2;(}~?{!+zFWx!4oH(Y~n>Egc@LL);g6ao9PSl$Oq
znc}zTK$9h2LTC6Z;+p56kS*3wu>Gp|2<0}ei7WoZ=ySv?>|yu1IO;LfZ;1cC2)$f!
z`YDLq6!%eSN}ky9ABg0OD=2<qEf7Dm4vK~1F4|5OiQlz@`C_r(b!glY?}m%BOT<45
zpjawCS`N@M@jNQyDi`Z*;YEdbaVh$4i?`dsnM(1jP>irj+&~$jYB6I9mTJV0x*<|4
z{>p>_)`?qY0kdAbn_{vJR`F0V*haB}PTfsndx~c?i#xvu_8swX9Jm(oFZ51s74P{9
z8g1eP`dzh)cT+5?Lp-$}c00w9RKwFHew|jWyW%(LpxZ5;ri!|I;^cOi?-4&kS6X|;
zbIQ@zCl04t=KEsnZ~2hv7vEcpp*;}Kqx{lC@oT@MaX=jS7s#NvWg2}$;`mg!KP+z1
z!o(x-K?%r+SV(olqv986=Qk#vq95D1*!3P7C&X=E!KcS!_jy2>6mO{jc_JP^i^ijp
zr}x3UjpQfmNAS&7a_9t1*h!kHlE_{X`v9U2k|lH)b(HL<Qu||)U++M}NwSL0CC-x8
z!_Ye}$!~@iE|OO%9O5cjKxbMv$wsOTc9-m<)W!+PZQ5OVNCv2e%~SHnDM)%r9BD1`
zmi)n{_@|F#E!C^}N}i<%grDS-4*+vg5=v3}Q<4X>(dRE&`U{43S|WM}3IURTC{z+C
zQN;k}jAV%m`p!y@P<_uiNh;Mm1W6Qh>JFCVQ*lO!#Fn0sP)PvIc9>-AQuuUUvgTcS
z{w_#<@d9YL<jzVcMo4x=!eFFiFJ0}4lC<uEPZuS#E~776vWiaKF_JP$>BLHMMDQ?9
za+anvUgG@)^b#ZoDu8`SGDRuEL`jw>NRs61*WpF7WEq|EQzTg-kW7_mHB{)CCYf3T
z>~u-V0l;KP^nTE|EO~1TGMN&^PcWY)an_*miX`l3Ok%d=g?PYRl{m$q@0vvW60mb5
zJF1~@UE+Tp+zp9qF2HgnB3J0$lw{MAk|$Y1r|x{owPK(YNPY?eXDyV>q*Hg1B$o-a
zVo5&-BfKT4*o?*!NfX7CN+oAh&?uAS1;IqQ#J&n56_Sso5V<X>r_*4iB;qxoRY}&-
zKCW7l{Tt@FMq--{XKE$dXP{6gd9e%%^^&PvfHg=0WN2)(N)FI#xJlyE4~Ls2PO0d;
zBN^#~-8RV|bf#^WT%}!0hh&Tns-2R2q)lgcNj~&|<Xy=m6_s>L%=AOLCpq#pNRK3)
zib#7U`*NYsC;96LoVhP)yp6toi7!QJ9!SDX5P2xE*3s3V0m-IMAv!2o*8(qwB#Y-^
zOv94d8jwele=oq`h-BYIkWtBdN8$IFB!VJa<C1zhO-@McYk~4u;&UD%lM==>3_g*p
zSqcxQB>U-}?6f3)3fxgCD;WwlQd<W=+e+)LREA<FRlEz<UMgin#zC5>g@&WFeIY=P
zNh7Hm-$}Z&1%1v^HZ5DnrJp|y_g$oK(5c&1TFykDo3x+aqVCe<GKidzzGVjSkZzuX
zK2Pa^2@Kmy>f(t>@RqK$2d0noj|{qq>?_?*mrDJlI}QT$q;xqgv!|rGpP=tA{hXG&
z)6$Vj_#Gf!;elZXN*B_G^^Ejn2@IZ<x^D*PIqA1vXbh4b6~U)q>B6s|7a~ohy+Ek6
zg(fyknnS_v^U~h;(Re{R5J>00aOs>7h(<^k4ueEWo36t|lvFYd?2FPOO0GvschNg4
zM%sKFeX-K(6gG;J>fZwwFMW;fv?fSz{0$SAq?UCUQlhkgGL%WuTf5*)vh??4h@?oT
zXpfgF-AzY<G-)QvzpS&<rTRf=WJnM91N5?#L&wNW>7o{JS<(-q(RW4q8pXM?rM;Bi
zx+<-jf~9Lxmt}ytA!VJyuyds^?tzJ$(hJu>@}&FDVl4Sme@f64NPjB=W}&oq1yG8l
z!IS_mmTqFfHR~<uTDrwrBCVtHfl_I?82V+>{098F%B7M9n5dA}(C_NDG@hczl~NAH
z>Z_zjCV^coeeG|M8mW0bL~5najzgqQYR&~%y;Ri)um-7xq9TpbSLeg+CTXVtea+HY
z6brs%mCieY&K7AW{eoMi5e>j@ljfFTpzYFc=y=m1jb07XDP8wE^t+@%KZD$r{!6>c
zZmDMl$USLlEl7{lpVrP^=^K<^>XZ8ZfX4e$#aH0^rECLSdmzn;1lU7qI_*>kq}HAE
zZXT4%DgZhpji*=auvFj&7avKN7XxiXdY2AoqtZOu5RFM6(GGcBYD25#gmfnDdml?z
z9D~B7v|I;EPo)361I#I@1KkgtmU<f@a#XfQ4QLygu>qW|tdO2RJJ~`j-D$O#Wzze^
zL6-O-EIG=K%mq0ni~SpaH7D5?x-a1@Tl^X99+$mCwUsWiWpwIxmE~^)nwxC@`#^J-
z?WV2q30W$g6g_0CiotoxKA;GKm+Tvgoq5ZG+kojKd!H(0d}UvsqWrs`>;{!uos_-h
z3QMPCC+hGQ@s~ZF1<=#7hZ~>~Amh>IKTwu80Fg5?tl)U?WD;kPbFzYJSPGIc=zB-O
zvZHA*A0oR;DYH=7H7E34kUjMmP{L&j0n{U8YbdD@Df_9Cp1&wrHXEb3D62gRnP?e<
zwlXm?Kgv(V%D$xVYn*K7AJB-Gtqg~W1R0Oc@RwviT*1&1WqjH}CCPrIEpD>RfnIef
zviF>Tk}CTm27PI=859;wmuV=FmmyoV2Yr`iZ(;4T&d!wmOsUN*nLoV<uE;WIua_-*
zehPN4%HF5U-8I?gzk=k*90s9yU3SPHXg6fW8}K4m7Dff$H)RcUIVMk*SB<`WSrZ+n
z3S@3PfECJkN1#_Ev(OH#SXPk-g<CTBd~nth*&!<GDwR1Lf<~EajOMajc7*=u6|$d5
z<F?Fl7F?ywCjydHvR`}QXtm65Hu`F0Kc~R^TA8;u23jZcoC{0!vb;ag*C30b=dV$=
zfF6}5nVAQaW|^ESPVUI&_F+a_tg`v{q0uVKq)=L$%uo-QcA4=6WIAN4XiwcK+epWS
zF4+<z^zX{veHD&&%Y3$Ap!Z}2lw;_Tv3g*lS5`3xV12T+bjrCen@Ml~e%T@VbkqY`
zd^Y+X%3_wm!ho!u>S+gM)-58?A=wq$V-Cw!cLL^-?8Y3B5!o7gWJYDdRFpO*3)}*<
zaoMXifSHh;^o47WW&AX#Ps-*|8vTi^FdCMoWPdLMnU+1I?8{NP&uVZs^4ck=+sZYx
zF5Ag}cn!o}9&KF$>L5Q81vDr5R}HY_EN`6;(c^Lt4jNtL>!=deRqjX8c{lks9XNOS
zQ&a|XLOxEvZV&mZ5}5FmkEKAwOI~~qoVUC<1ARX7&z^=CzVfA1=;<eaZV&uDDSx;D
zeW&E_?5B*9zdS>a*3<IOG65PO&)p3YC{MqO(Vvm0h63%ZeC`YQC7qLpw7`6j{1-Y+
z2Fu$<0U9EA{0<7C@+cj+FgcU5+vnvTlfb+n|4soCE}vNk5+Q%_CNLxALsXR*C4X*`
z@(&l~cj<H%E#K+`r()!aNSKI~3zNXb$z7|!#mhVC5>kS^fEMISa`9=*TB1CIDg=_`
z^^^xsmRC}&F-1O?uK%RUD=$DjO`baeg>?Bs%Ijvx@4N=?viy76$7RZku?euw&XO0M
zfKylGm-hoSTfU3x2CmA@!;rZqe~wD4bL6oXp?_UoNx$_Q_`|?%t~`;dk#EWe>4=#p
z@1qcFzI^Xps29jz^ns;9`PoMxMe=}6n4n_$iucfWOa49&3MF#gC8%3V<%#{UR3>ky
zSXQ~57mA6hkY8U46Sw7B3bt3uKOKO6mE4|Qiq&!_Gc47}#d*-Hm22#wP$$1K6PD`b
z2Ns~QLB5Z2w~g{rCb%X!cQv?X`6m}Z?#SnS1JWXI7DBJpD)$ct+a?eB2J_r5PfSE>
zhy17S!F9^N4TkwH`R>JV=C1r%I*Ihioqm8wul%Lc5b2YDeinA`%Rjjbu3tWn?%h3*
zA83Q#LwTqQjt<C&XzMj7f18e$LvouVP#>1F-J$nLZrx%5J0cID`vaqL#Y>o>G5M0G
zF*W1zLvLc(6Y|5fFM2FLo`c3o`HyrZ;)#3}4Q)!^MDM6+xeL`8A60x#aRD2}dz8So
zRlH7*ubqNN^#=BeBwDN;6zl$hGmeT$+7}&D{BE^Dr;~#D6+oR8ed!>_6;2#<x+t8F
zz<pOmE@dIz6tUyzb61@1#wboGqz0JqP{jEH%~Nrh$`!m6w>H8HZ-w$hSn^RgQtH`P
zQ6C0%KSl8iP(P_iqSWFkMgIg8{1q*kw2?cl&`}9vfZ{yu`U4d+Xit4cF<J%gtm1tt
z`8}ujmde|M6enoe3RYxz!HW>Z8{=pURkTr*AxyE1f_>)|1M{G8LGiyc=nGd2mw}5=
zY_fohRCv?9pD4wAME+-ARP61e`p;;EBNZydD0WiZCsy%1?NQ?t|I&Sjc*T{S=u1%4
zH3R#SV%c4oPgG3)3ip!~ACue3iY}^CNKrU!heE2NbQ!SI6cH65>59syp^%}_J`45B
z3c*4sWGXiHVe+yR4zZMfzoOX1Kxek1cm-gtDxztla81!f)%7`wt@iNgy5c82ux}{B
z+klp<*z1W&ys7w%PDgo)xfC7DSH!hKy+BcW2wbt^?Rs#x6esAZC{f6%yth=rrTVcl
z#WPN@P_8)0hKRL7@jcxgxvdEDflQ?$n9dMYikUZHsakRJDah0)ypr%YtW_Lg!(g4_
zol(HlD?SWHV}rtjzV+Csh@p?OHYu_`$IzM;bLcAj9fjwMAT5e_N}$)O==uU<X;X0i
z2h4VbJDsCCtcnSGj5`%>bkOZm^ic)KUB$%5!0uK^zlY*I#d~8=>`|P(2hyu};RopV
zDb7*l$bH33H4OGEqB4N?K(S~I)E_D~Q|Mtpv4VmHgNm=Ha%4#H53O3mioe_e{Ya5P
zzpfF5)nySBM-~2*;uur>Nkwhr3Ofq6PbmH(na7G>-61lm$frW)CyGKTu%{Gv=!uzD
z+^2=&sPZ%gb!?Oa6eP4&ZleREo$@1!@Y*ZCp|_HQQcs&6N2QVKDvl`=55a9G<*Qa&
zZ=97mxiENK`4gp2T$Ijx!MQ5s2chq#yxIXYcV+M_kQ2(rLg;%aZI8i{r?Qdi6ugvn
zbkg)z3jRygDa(T(>8t#WBD8+WIoU9OQrSzD=%<uFZ2|FDo{C1_X=T(bdj0~GM=GHo
zs9g31I?pKMDK~jm89>FI=ah4W=nGQDw}A^*GG@Tv5as6=AsMRlrEh(NDW~^<oL8Qs
zB<2O>26`EXE4$u;LWJ_Q`LGbFT#^cfC}oKc)GsRcH-bx4ru{<CUy^c#BL<qReB2C6
z>B<iu!hDAED*e_kE1Q1>Xtpw&!ev*LN2o~an)2HtFj1r&2!Y*O%KWVmDN$~vtU{^M
zLci`Z<wg4Ylq<K<wXzE3imgz%t=vFI=}IMg5?qzi2LUzf>>8!wONiDgx6+mCI^~~q
zG_F_PvVn^Y%5`0^+o=4TK0MN_bn$|vJIZfUFs2se_R|<)tMbD-sJAKCQ&yov8A9*f
zPUQ-UQFbYpIsxpi(w545yOqCNp?**4L6g^`JWP9kYoBsIEzI|oo&N;_l}RVj`9SHo
z5RDI&ujRqh0p)C3;0Bd@X)`^fe3pJm!^)&I^gU9#oC7zaWFG<AsIpKGN5_;YeE2l3
z44{qjgmUIeaFfc9q=0^+%%c42l=4gmB&V&)J-vWAs=CMnjE!n)IXdlBNjdP_UbT+S
zv<|AYpJCTgb%ORz$5dTi0CiU7PzB_1m7YR|E~*x~g6yjD&INH(-Jk=QyJ~nB+&-a7
zrI?PV>a}qg@>2bq2}9m0&u;<kqp}((oA0YS)B@tCvi%57`Kz9%(&f`CH61zvR7>bu
zTA=E)AJBJ3<wj+OXI1~wmLOPlfl9VQRM9GkgsOi13XK<3wzJ_yxM~hvjg3%kI{|W0
zRdE9bqg6iJVLnFn%}q$gt1elokTO9vLdU90s<)|DC0XS~f$bDk`Xk7ssuZt*%TQ$%
zU`&@)A8&<EnJWLoK+9I`q6ENIRpR^b{+epb2vBlVonbI|T_vkV-wjm(eNQ7#wVx^i
z^HnqBz!j*f&Y`bR^-3`PB8pV+{0aSHRrj-Src^bP_RVFgnRJ#eSDm7ea)oLGALehX
zR#8DmrRo}mZEI9_=rCKWI`t5wPBn*iXN{@@3jx-onnS_oX4Qvr;96BrQL%rUs$(C(
z+Ex3Sq0pg<Pow-_r|QceFwid5DSD~)t0K?C?gLeG24o(p_E6|y00V{HLDdaf?uJxr
z?g4FBwT^a$k5oU=(Pu<;W<5|wRnoIiA5%@x+B>ciSs*f@Dy3c0W7S*=-A$^TDQNvf
zbqFPD*4b04?VrHXwCdtfv>sJw{|*y2>WAHEv{e_=cEe8XwF_wW>NG0Xb5PHyfO$vt
z$VxOGQ>$VzCMR_WZCIVv2fs$&arL3|7`=;HMd4;wb>khFcT<1r255Kn8)V^xdhKga
zuzIQQQohq$o%$1GeAM?T^X;q7rhtN<`t@q`om9U<DXdfKY}~k*?XPyAOIxSaPt&gO
zj9Q%yN6)GcF9kWL=48ObAoYS&^aZOY=0P$<{e3LF2vxs8hQieGuR!Fydi8Q(Ua+d~
zJdf6J^`C2@AE90~2jh)YSJOiorGEB2ru3rv3woQzsFzSpYpi<NX^=Q|JOvWt)#4Ih
zC#Y{HK;)A8vj=EQR{y&PC@Jb^>0F<xek%+pX=>qo7)n<^Mf>awHIou0m(|vFZ^6Y(
zb?b`|%~E>>V@|H9ebYd))#>v9b5;F0-PgUQE_f3ra?}y@P+wQC4FJhi^Ll}uua2P8
zdV#utUT%fzd0xOQQu9NgP^><m0`8Vt83~aR^`(43m#Xz&qOVMyXnhy7T>W)5NQFA?
z7W8kccg_W=RQszys?@S$Ak}K;Ets}CbwvW4saKmqfYzY?gJP78YEdstG^v+1!QU43
zDcYp9s>f5I*QS0lih;JPmj*$-L!Cl3;hpL)UIOV-KfFr$zq{&p|H71ZtJ#6jxTpR%
z38Y8e)Pu%e^@AypK6PLXVD78CX?^WiYfZ2_pibn$nPK&(|Lx_~izom&q8_}0zEO2m
zJ`~2(lEavwadpN!Ff^gw{yq90t7B*-o>a#M(*1`g>dFl;F{O4ZMC-Kr8`_uIYFcQU
zW2brI0)zINW!o@84w@1AB$A_M#!d|Mm}Y>!*5su5*9)M|nuGor;c-n7EnY5~6>?y@
zYM%WVoSSA_4%9s~DHMtG)XYBzJul4yRH`v%duwjdw?BL|!F~Ys)hwde`6-RcyXDFP
zYtCb+2Wn<IVGw6D)ig~(nzt#|5UgSR39})ZcT0g8swue&3t^hIH0tx31P_2*(74P6
z7p}22K_NnOZzU8WHCKZG7NuF|j`3a8y!|rt5;ZlSLnKMFiNedtny)DSo}$rN-O-t<
z@j42$G|jmH3_e|RIGcXJn!y~%T-J1OF+Z7_H`ah;X%2h_az)cw4M(#zESkHknzjx|
zUeol_pFT&EbqHYBHAi>=yP+|<!9uR)q$3({YMf}P&(joByfa_3_d|L^7ijc!Dk{`W
z(t}f^8CwOIV$D)lczR2tp`yPMjp_#styGh;3!r5hg*RZzH3nKiD>P2aVdAzXy%Bnq
z8dD%fU!^IY5A|wIC{-)eXny7bx>nPohog0xvUHfQ*ZiDJpQ&!pMAIRsQFGyUkS5JD
zTcOyj*+%Q)9nBYyVZKGPfFet+8tE}uYSV;JaaOygh2kz9nj!jCc50gGD@$D(b{q`e
z)s#I3>DC;f!jF3zWf8a@&C<2-zE_j%2K7FT6!AlRCRZ~+G1Y#}QW5kYXnv>Y>qAYB
zCu9aR&8uN|P_wfVWJoigPSnGiZ>aY6k>>Ic8b>snC~z^V$)cjLG0hsf95=3Mr}}~k
zO<^!Zo@gG8f=p?wuV5_Gn$^ET!B$&L>yp(@yO^rj?6r&fKpeF9+92bo<zB+jj%io#
z0-BR{iiJ@)Yj@AaK#yw=eF{kz?YY+>;;QYZ>u_#b1v%=joumx?3GF`G(t2opX;12@
zZQcw8FKt*2=GR;M4y`>tTGmz!_oP+ZMS1sA+SB%M%3sTV6&k0tYoZ_;pxu1|CIYqj
zbl>6(KH`eTv)aOq5ILtEbVFm1b~i=4g0<(C04+p2{tNm-wH}lX3)5a*3GdHqT@~oN
zpq)usyl|~f4$LU+$5ecJQES~!3vskomI9|@v@g7iQN(H`!;p#7wp%cYcx}gX5KYil
ze+2WFv|A29BvHGYP7q1j#v-UEYc1b^OVKVBLo!u6ISt7)ZRQAEOV=Kty9pWEdF_~)
z%UT9y7&5hSRDhVJHCU;H>5BHZHE=jvyPaO2SG7#qd0o@4r(0q<TB9#qyRKcB2gMuO
z73*LySDTGD`|O+ASrit})4EflBVSweJx~g?gMRS7P@BC0>P6ZI6rwEF?xtJ%x3ucB
z;7YV^-H<HR2HH?`u1wqN0JdB^d=iQk+RQ|t-PV5B0fUv=uU~>jm39#w|EjeYXTolc
zww10B*J@v<SWunz2%V4XwO{Xp!3J#-6(lukJ7xi_Nqd(9rOn!@1T@~!2GjqMY0+M#
zZCtB1?jlv^w`pU3z$CP5XTFK~>d-F#9x|QUNxH_+t^JE0|9jf_V3_F9?%xfrS3B`C
zxIS&{Z{Y50e@lRRzxGYqyFbt_`2czkwcV6J9?&kP4b-6axIO$G(!R?A^sx3XTA&_j
zUq|T7I(tO>?Mb*es=a9gjWO-qa`-l`{guuI6WY3MP<*WY@(#F3t?MMXCt77GM5eT_
zzXj}REpG?NQQhbTG}`Fa(^qwDbvw?X(N6bZISktCUZIi;2i;$laNAKQjRndvo!x$z
zwL0l~smRz__dCTuj_ZCt1sE6Ig*70qI)f5pa?`OWhU>0-%>?}ux~?s7#zU8~3oxF#
zI3ot*rTd8P=6UN<;?U@$JG>Q~uP%NF#83C-)6hGqvsncTr*zKbn!m1}Uizo4x`k$#
z572EogVsP@NIbC5=pv~S>8x%%3*?;c&+lPANcS$?#R%3N`W+-hxAi-qh3f870OEp9
zdjTfGb%pd)MCgQ(z>d@ne*!K_m(GRAMO_#LJfd}t??5s}r=yyqSe@0|2$(pX><mQX
zb-(@wE<u-03;HG9f*WW|)Lo<mR+29KI=o2M6)eJ(rsy`UM_;PW%EIW=bU{1Nm#z~~
z!XQKU9nI`zT{ah9Wa=J=!(f)~rCjJ;(H%MnyV<&Z=@|7@U6oY@dQCTU0-`xOHRaE*
z>-N${>V|IFLx|?;o?J%bO`VZKN_n~hDjvw!Wv+$60$ni$mI`&(zQE)a>FQ>|Qn9Xy
z4*9oqM`=AT(GAkMpj6jHp^7q{*a(zzUFJ=26}t3~>2z{i_X1^ND|HLFXsyyMd>*7)
zXQE6&jqcL~Xw>Q^+~H`Q?kg(Ttk<pR0cp@_sMx7dSK$N`O*+rFFc-}_=gS~>bg?m*
zix%B6S`1osZ+?NXbm&ge#;a48<^l^{y6x>09k{Fey8~>uF3Jqid%9do!S?80{1&3U
zx__%d`gBivF(vnPe{FzI{kl#nb9kUTP1P9>b-r}E7|`t+fun=E^OTGq(w(Lh`LNDH
zN1aEyxBdm@i0&;~Ax3pej)IKo&VEAG8RNRy-@xvKZtFXMd93TBSL~!Nl}fvx=n|g;
z%#_YZfzoN+TH00})ysG=VWSW2fO%W}f>{`vonEm4diMHCN-jI-4f`PJs6Rz<v19tD
z>4)f~-%V#EXZ`9x^c~mtx<k+EqQ4n|R#$z=+c58@zg`J_cYP*pH%{n<H!xlg{qOr>
z-c!Hj5`6N~e?xD0Z@tSki1_H4bAaZn&(*?`pML%}fSuHT{Tv!k>Eq~TufKlaJ?Nd*
zTdCeUKyUXczykF<X=OTN)vKtQ<*fdP1pqy#UqiKFA^K(ts)Xuik;7s74fI0{*L%`d
zJVM_^b-j`Lb^-j2);Fs$!7=*7v!EBNe~H$xRDH`|u#~2^QtmWe|11SqGxXVoFmzcT
z`xL-3^-JcUF-vc?r!&hHy*Irov-RPWmA<MMQyJzp{oZF_DM$Z+>P4^XuUvtp8~T})
z)XUW$SOZHp^;LB8$<sfNME~r3eSQo?3iNf)K%`KAMFf;0y@X=r#rkJHhr%uWhihT4
zM4zpNNU1)+I)>IVz3;P7EY}B8CaFUI>|MBjTQ9x}XDapM|AMR1?|%U>)%x5Ba5ehe
zbs)9+J)uyj({GkwO!fLp{{pl@{|EIo>Qm@ZYtp|X2Wi&Z_=4QgkG~CjEqX_~n%k;h
zkWJ5Do8CgFjCOse9bh{2N9j{Ao%$;t;JWmC@_=?%Z#W08TmNM+VD9O)4uI*=yV8x<
zUj4o^;QI7JioD;~M>@gne!bNTm=E-}E%5N6UQQMC1N!6#;0E<JbfaTPKb=nd&tZM)
zX<$Fn@1sBSi2nN1KpWK$MZwaT{`>-P<N9){@0-xa9D*~C_1CCyYf4{2k%wvhr&eGe
zH9Vr!o{eE)9VXb;u)rIZ><q#zG};@4lzenB)V&J@N5jq?z&vJHg_YPk+sUvd9-YpH
zpDB}c+~5=qG#A6{4j6Pb+)GBEn<0{tT<(TmI{BP1jMDDG!%+J!M&W6grr^AnVWTTJ
zZ$rUb^i&vjQa;$%&^8}>eul>z;l)Wq6>YFj8&=VqBfub{0!C|~fk6cZXAB{M=sat%
zp?auuhAs59fFMJb1Tw(}HpQhw4E_WYYWR6I6v7O}6dgZrc!iE=7Yqt-3_IM=`vFLV
z!R8zkA`Sj@-9E~&nj#h#4IgPRCDDd&DSZ%Q$fSC}*cFD1NOZ;-HVEK;yg~IEG!hK!
z=-&G!!&y6UiH74@a3;y%^8$vQY~UAxOELKEfL^NMAMew}EUW4vz%mV0^gGHjq)b5Y
zioubh_}K=*O*CFL)X`!2n!)-i`f?2VB#`Td94ZRFVc78n+|4z-bqy#t4c%rK$TO5r
z!rgp>;R?6{!v_=-EHp&l16O32qF6|=VLSsOw+tax$`zFu+5})r4ciZ3fMtfz*D)34
zhNle}N`>LQnegJa;m04LUukGj!eEubiIVTt1{aEA)ENHw7>%`tH2Oo-89WXFrQXm=
zPfCNKu@icYhCk`u(q!0@4MWWaUkVYl8czND-&16mqCG&np|1i%>oA;mhkmEQtqiVp
z8UCPKT6Yb7R4d<YaF#&-o`FkOFnSC&pTb11VRaA``V4PQ!KeF%v-D@_Hw^be?|~to
zYVIByhGs#1z|fL_zCnYIYG8&8-Ia94A2ygT0PT_C&lxZ{Vkq4RFGdYHv^-82)+wO>
z*szV#9FvB3DOmNyaQ8SQrwo(yE}b^~6@+;@Y8>tYu`zz(4->XV|F@xMXWT@a6nmrV
z47lcCJUs}zj>dvR06S*fiQfT#wv%yj9Lzf#f1+s7apP@@1GpILeuj*z@tAjc$pY&f
z((^EO(^q&rjc?`y+RJ$O9XRN1T+s+MA7jugaK6TBZ}j;YUnqydN#n;9|2kzfQO?8P
z$X228v@we!&H=`kDN`G0JWb2e8KW&N|7VTMY(dT$L+GU$WK1{&F4)*$jRtmz@vmEG
z4K*&<1&uIc<|f!ZZ@jb^XcvrsQNB6cSmgzg2;(T#gGU;l%7ghR<E!}~7mZOrVqT+-
zC*B1YV|<35?^vU?1?q9eUuf$cZ=8&PNP=-k7}PHr-G(qPiAGT$B|?&nyI(<PvT-AY
z!BUK?Dd&-Dygml~G~;^|8c#QVPC1VZW7Y>yylk|c3r91JGp@s6mhprK`mPw?b4TMf
zqu<L=&oOSK%Gc}0kQbnS!}unZR^%E_)xywCV_OTRGSA2~&{ikkm{bJN0^=2mpA{Nw
z?Lmr+zovl{8(-N36Ss`>|Ak12amNyHrN$r@^vjGb@4!U4@ul}MhzcW*(pI;PpPYfE
zO5^3_kgPJQXroqbe6t;-#^^1_0Bem0DK=ea+@YsJxO(HS7HBjW#arNMqjAT-aKFj8
zJPDx9#s^fFcE`A$cHk|>`sbn8YFt6Zd2L3oJb2h{T>2HTJB*EVnCdjXPuC;5jO<$I
z-8DwgvAEmV7!QB%8JEUFy~o&~fI_cPNA>#FKI3NEINdjf(3fQTjoM^jKQIpMh5HYU
zK29J5#vZ!GHfUV@Az+4#9&dsS8?zR`(j#L-3iL*dbN_om8P{dP#F+7AO6`st!|1g!
zVYG~3NRN$<&Cr`P{zEyxCq|z>^i5ffHmd+LZLFGxrK6^P`up0LF4Hn)Yr2#S4Lj43
z5^(k=kqi8GFx@-?gHEPesuFcJ<<SM7<EA)DrMZ~YHkcAuQ)mM)-As$NgL5}sr#gfa
zrj%Uhd6@jD%FNSbeG3X+ChNO8w0fK7P*IbQ>20d;@HOqC(qKQ+W{L`&G<DnqIc4hZ
zfrh`yk5-1$rY~vj3NWqz8jXP_M_(8`V=_Mt?6aoBQuuVv^wfV9(Wb}r3ko*Xeg;D!
zrV^?`3^mz@Kt0TK$@&Y}^QJxY^SWRXW<xRDluAL*2-8eTHb$D>rJP5UX-OLTE}GUE
zffj8Fw1H1CrrL{`%UDy<5s1W@_O?PV-n8aLU?!Ln_oMHU$#fZ9qN!#KdP%00TKJo6
z>b!}*6w}s~R=}j1g6lEfG}GplXiYbb-ojuqOwWv=@3Lw5UG!y|KDiF}vrJB&=(}R7
zXaicd={XBTu9{{nf%$8uFSHQJF>&WZ;kv1+3L-a52iZ`_H3?Q?EH_R2`=O9$dgfz{
zCEv6snf@bqfvL?AGKHr5RBKRVniCC~V$-V{fR>ur|J6X7d}AR}ZW?<8_bW_0=R)MR
zX(hd4Dot;{3dt%{+}AK)ZOVNQgQzh*rY~XEnnd)@uQQz@$$HcBCU6a=cj-e=jV7lz
z=syxSnGDH5Yc|zT4*ZUZ{XJk>Oa<8xZ8goJC9TagK~G$}>1_&rc9>Q)0K3yv_#!NI
znVcM<e%ExFE)sT|1`^@SJ<|h9S@xKQec*4eY4bl&=rcV{g--WP+h+l~-!zA!kJbk!
z_ho2(Xj-R+{(#A!B07U6e~RV}nfz%f95xM7B=(VM&jq+PVmd-g;ize$3?gHu7H8;<
zo9b48n=t7cVd=4H#T=NQG<CfQg(s#A+6hdV3g`$qZEB=N=&0HK0Z?qL=6800wKZ=Y
zhlZUwy&lBg-0?FEI+)KWq3CE{{yw}oW=^8Fpp*IbNtkdp$E||MadRc5QC-X#%V6Hs
zyopM(+|04G&2=|tQ~B-*^OG&W^e}Hb0ODz`9)*IJc^UnEyv^2ol%5PQ+fy_m(0qCc
zES)hI^}*6v^J==jea@`-8I3{ajS`3in|<k{&mrcUl)wx%FFcOEF!LW3=sRzIh2o<T
z=7guA9%+7c5k#WQiN}F*(Y*W)B%{sT-#}u_A;XyFSo2})CU_cWUQz;?c(WsIB@)aV
z={#`BT(uaWiRMyjOfvI>0Ge#xOfR<-^F}%Wr<&cvVIs}EoPsy$<{uouWth|G#DCeG
zmJP{Fv-c#XB-?Ddi^i+wPsJGaHS<?mkQ{TrD<wj%n-eHXe8ar$0i4P;#|Qy)(`=@=
zQl9xK3d!V~yD4B_U~Za&zgD5yrU!aO=C9~bQ*0jm4t=-G7qVfZ#Jna3220I1&ZDo)
z+(c2La`RTI4XiNx{e!;S=JXXH)#jcC`i~qn<}Wuvrq-;bAWEG%o1!1}=D0%GZ7`cD
zJk@BfvVb(1myDvX*?fc&A$QDM)R?>$bBP9et>&8BAZ_N>9|6{G{%SEKJIvo71xlw`
zr~&CRM>Juacg^AcaHiYrgHlZE?0aU_T!{9VnN(8JYkr$<Y4n-*(fR+rIbH&dezWdH
z^gS@&v4M$)=JH9{9WY1GLNRDgJ^+y+v-U?c4x8Vk8iz;ba5~qHnBRL9&WxHpS(w-f
z^J}!*er*2P6J*j{TnR(gC+6GXV5iKxxR}yu^KV~+v$5pPfQGH5I17z-md8D?Yj2sR
zCC$N-)&#qb7At)u{+OkfkGXKNd`t0BXG>Ni>>jsNzJW#;i`M`|TrHJ!jCZqm(&Y|!
zi!HrjPgwK`Q1Gx?D(NNVX*o>MA}`BT+8KLWKBwKUkL6>^i1=E*zkx<S%hQix_oU?^
zT^BfIky50=-||0O=$*FAqx#GMOIi*<11<R@z&vAF(*#RrE$^{_a?Y~&Cb%GrmX7Md
zmMgRo3$a*7>GvFJ$)d+1%<?gvU(Q>WT0kyXR?Y@!xW(d#DUGmX(k9}frED{tiMISn
zQNS1rs{@Y4TAre`Oq^xiQRu~6#0*$Uu<YeS{gOrg3e*!Vv+4JgWbvf~TC&BRma-H}
zu(cK5q*@$fp_pdrUj+BlEl>Xe(QB5)L*Q~Of78lz-O_&uiZ?9FDeI7HDf<ToZ(4r#
zg?hf_)m0d8f#n~nFfO!gq!UDurRW$$iY+^TfJlkue>p%YweSw0ugubU6^-SV_Qh79
zRamOxVX4xx;21iqEHBdHS#3Gy4X(!G_+L=L;zqy6I?K*FDAZf-UxG-3MSTWCYqT6J
zg83#(oe_g*wur>Ad&e?23?po@%=#K4t(L<tL!`}ezYa6gZgHg`WQXN?IX!=!mR)op
z=(5b91m9iD@3hzJw!F9&<enu-3D6#k4OMUTS|Xo?VxL9#0{p#i*+{h&{TAB|XnbIC
z4F&hmvVRz4z~V{~>p=@+Da;R9A`9Wuu;sZ#NItS?DK;=-F<_Ttojqz%P<C^|5<~Z7
zA6q`9)90k+a2w1&u{5@#amsS(CAc<i`HIT+Z5G9|F$uPd)D+mUTjbFIV!vqfYv^-W
zw3%}6#}@6PS`ep2$t;+6UbKLco5vRow}W$8q^8V`+oI5Zpjh1(O<jWMiA7IQsLo^2
z!F!PLT=ezF0QFk*4JDqu7oDOVn9riA`5?ZFLMWc>x9HVZpm*~B99?%@m(};Tl+^57
zY16D<wk)m8Qa^j|y-h7E&C-UNWlI|$mAzc-C3`6#LqHH^sK`bT5M(a_6+s1*CBOHH
zf6nXNGw=O8&mHHS`@rZ(2TLF$myWqX3`e>;7|hs0oA40EQ45rXGB&rP+hL67R|6bp
z)KJ+*IAb<F@ey`L)VJV?WK7<LQ&EiULSWI14ZXl(7&){njAiT!g~2$+Z{+~-jB66G
zBrx7w0fUK*=o0ke1f!NxwI>;IF90MlRN?sTlNni*c}-!+zJQ0P7=up$OJ&TbQ+fvD
z{V;HzX4qFAhQpbReF%FxWHCN{7k+0m=2DdS3}XWYW^)-mUjaMIaQ*-wkCFZ)IL|Tu
zkE&J9GlCbvnF2;IUHdL%+zyA*B8HK!#9d$%okkBYGEz>1rI<0BB3G9gi>c(hgdyAs
zmQqHt{RIe?F^;!_wVdHbd9w<}b2Ot?GL}=lauwsne*mf({rBMh6-McHn5bdw`0vca
z2#<o?RmO#R&|SwUrS-3#G3y2z8yMUC(6eg{*6R>xWRy`Dt%>2X5iHjkRrDk@Gu(#g
z{cB--<PY7g3^#h%+8C=TMb^%c&=c6faH4cYCu7@gU|o!~0Jz`H(5FGZhrzuHM|&BX
zpD<207;8dcw~tXsAKva~%>Ec)fbrVLXuQoh(g{O@j3=pX=?)`u8UjNMuP5mJ8)n>D
z3ZA=+1yqQ7pRxXV2#zpbd=rhMjD)9wjWK5E0~`++rEw4(XY8W%*97A?2Y^Y&!nts5
ziqVq}mTAV%^ft{fo_Pmy`<bsEfZYSkRqp{i$W%l@+>tr=CwSq+^z@)Y9B1ZU$}_ky
zpL+`0T$!IzYQT;8OF72Eow;Wam<LmM6__V;?|<c9OeQ^#-b`PLaUWtj-N#rQX7)XY
z#v{zRw3Rr@Z2kZyjxl*ZL$wd{QZQ(~Oe<vu{FoaIX!K_;2!&7f0H%$;1|G<KehVam
znD2_<a4>VuUDyp_?*6YPpSk=;$cHhr=rnkox#(&9u;I*w>me7xw7vv2k<5GT@FI%&
z+yEM5nV0Xui#X<A>5z+OiW-3>Fk@FiJdqiF8eW`WPEcInq@5|3LL!;Dgsvc^Fzb`h
zdWyNQ0A8dr^JsBPW4`}38q=8<DL|UR{FP$2nas!5LLiH2p(AEC^Fyl2JHtFV2#~{c
zp;S{Y^8ydxEORNn(|OD`nnKSp!w&;H&$LikK|a&&-vEh1=5LqaR1s58pI5uUoS|ge
zMP@K1c`h-(xe61-%mzB|US|F<7haSy&#!^*GUkCGu#__w(d<*fT=guJRx-={V4{k-
zs~>XJ%vt1N4bw=!RxNY<6KJ{0)D%FVj(OSM4q`oXxB<il=DK7EUSr;*k1jPa*SZ2+
zXNJ<ZMVgr^n!;O{Efuia%A6=bV+XT$B@A{l3l2bA7qe_3My8u7`4OBw%v7r4=w(LI
zS@s5VJ)O$>nO;<$J-{5GW9Ln#cP5?xZZTip0ByIK3$MYMLFN!8MDH-0XfH6#oHZMb
zcbOq=@cSNf(Gm#UXTIbH`4Q%ydx4EIo86&%jG5~SEf1JMlr((E%-slVoSAS8K20!n
zKS5xMnYj#FrkN*v;qN1+teN63Gt7kTFtMLC_YrswutI3>bCBiF2CEZml^WWdS=Ads
zb72+l#*nzOdMO~_#=7_&bi1>{W1!80HM<iAy;vnL1M_CRI0}J7EL|Uz9cFzUhQ=eT
z3ljKylr`sX$Q@&K<59Oe__7wR2hoou+ye=J)+0JB1+apa0R*zDS3qe9%abY;Ls_e+
zL^q7poeJzYtGNqUILoyF-bb*O&BJg-vM$o$Ihyqi?FC|3rcGdpWqlfr#yFOl66Eo$
zdWym)unL>e340>z{9CYllI86No+MV?d9)_8KA><}3M-z%bEjB!&jL$jT|Ew38te4~
zFqqCNr44TeEBPU4r&;fq(X~ug<QiznX8rOQyg$R*PSK+rmUb38k;|Gx#Sv#&XXN;`
z@>ub7@#>tN)!GN1d{!!*!wOi31z;^?Ej|r3MXZKUsJXy$d<)n`R?WX)xy0%!2Dr>R
zbODVetaY@dFJ(PW&tn<O`X^}RtPI*GRIvP+V5wxyItWnBy5I}i6&8<n!8NQE6pg86
z*$)(=^(rfXQkV^_$LJJ$jn%&xzBRITjew_#<=P1O>nyi_(b&wYr;}m}>sKd$HkN-T
zKs#$5?K(PG;tu%R$r{wbd>1R5{=ZK*i_d|04=dp=Xg646^!oR)9B513&*Ix}<98Zh
z4Ua?jO;+`F7`(;$`8$Byth=`%ILK<F-RvEfmFmleSP>L@7-lV{rRpAwL9@tx*531A
z8DYu)h8LqOHw$!+u_`Ew^?)@)<**M~4bMPef_3&8^mCH+*bKawV*T_Zt$))jA1ib}
zV%0W+IK#TS0>8+9_M$%l4zh#kK;y`sM=?Vu_Di(ca%LZ=AJ&EKLo=}}TRI3iH}-~4
z!0Ex3ECJ1vow@|hc(DtqaLJp!Gz2V%*fkUI{wUkm25^kMW;O-Meb`%mfP^o*+5ryx
zu@BN`Cj8k`R4N$2cCCenLG0~0z=GLc5-1H}Z@z$Thq9kufW|QP6O@`b&Nkl!7S5hU
zpVEwE-&>5vD7O43VA1SNPr<bqw()y-5zGFYs=MRZ&mEyc@ObuYD~Ji~t^|NY_CA`n
zPOy)B0r`{c0xHc<W^*TDFooUN4#89GIdrW!l|4Xb_cV6%*BHEXc07duGT7X6Fp<eN
zl>%h3ms1gBHanZLGiTV7R%pp#tEa%3$BtVFIr}+w=^rq7o*ftfiG21mfdB>Uf9XhE
z$o>v4Iux;$2hn(u&7@kTOKk2xz>3*bsW5+;Euf0d5_aqsj8iH558CFGv1cgaS;4+(
zgNaJ^FI4hc#h(8=uxj=xAyi*s&wCt=HFowI+WgnDkE-FtRdya_=Ihuo6yL6AzeZ=$
z2KJ^gxZlWD(uJfZ_TuF*f1Ujq#S@#^Jh}wX!v2fuO<LJD9<VmH;TzC8*gc`(>}21+
z1JK2erwv>;`-|70x`%Bq0!ts;o?wBe{p{!vv<|RWUqokavU_Q#dyCDZK*nu0Ujddu
z_7KIzhuA3>feo|U-UhhK&TfY8d+Zl?K-+z``5&;1u-{NYe3b2w1)UGr8)(US$o{Mp
z%Es9%O402Jc2PJ6Z<2k&PSL9=_Tx3^_B6X~651ZIGbvv;!#>jh!Tp>$PeAtpPCW;L
zjvNiueK>Kxc@dVJIkA+sbKyvKLco=?naT;>ID;p^;?9{%fh|u?+$ykmagK*WnK#Fe
zHe!c3lFI;xId6V%2hTCi+p$1>I6kX@`Em+}pxck*M5hgZj)w`I3E))y51k3*<lKa%
zV9w9a!_g2<PY>imIXP4}AI4coll5^<e=UB4aL#e6;ECWYr}-v|^9F6iqB%VjbC2Of
z(Lx)`@qU{2pK%=3Qpm@1ys}{_f%7lz#S=MBwU9W$`8^P<CpiUAftJLnc^{og;f$w2
z;1s9oAxxxl_Nl>{#(A0cC+Qq^EX-$c$|%-<n)B6OD9hsfumwYs&2ec1IK$cTIRtVz
zM-S8aFPGCx)ATvc1Xa78=M2)soX`1&PBI0YWfV0l<n&R#yNJWt2BjA`PVb>l7db2G
z*n5eS7Kg^moO^U<sf3d+hKHq`g-79b87Jv|u#|H~)<Sh9r-UMSRh%7K(5gAd4@1sg
z!x@?ePc7$pCA|O~SBjt3aZ+hUt>-LW1<=3=pxpm8PG>Y+YvRnJea3apH`S19=D0ot
zt%W1H4sER*mr)3`ak9jqwR0ZQsjQRp(HyAm;+)tImTpdNG6Z@!+a3Y*+BqSOaOwtU
z_6oQ-z+qp7`!_lBgaEfVg)I=g%`v?Tp9VR{=*_vqdC~;VA<nC}p>3FxNn6FcoP+BC
z?sM+(plpN_TnG<GIXftnHO8r3fyM_M?>uN3=eRutHo<Au08Dc1Kix#@G-oAc?H_Rx
zV}Q+Yw$WEr_jA3efZ_o6{RF5v$o0Dk%#rI!2@7W~;{rHcxI!x0aphim0s?N_*b{Ku
zo%`q#lzDKQ+%X8A+&eUbdvm=d;5@`_js@*7cMGllN4QJvG-)5@w$BFf7+3WI)cA4#
z_YW|CZuTa0G=Q7%6R<$;_AwX?;@T<XAI!a(jK&adiV;{SSDy`9829sI5D({m<pM7v
zxXG^qi{#FxjY$;uDVmp~xmOA>>apDa%ZF=mT-VL?{>5|SaV5_ok?TM+@(J$CPeT4A
z_i=Cdoy28`0g|~66tzy_O4mUC6n85hO4GRWe}kHIt{c5S8QfE^faNrI6TPXKT;T$E
zn8p3zYcytagVOO_<Z$IrKs=WlMBlkQ%U#ewAL7pAzS9iWbKKiZw4UcK^ntcQ?w>rU
zDdM(PLH+{w(pq2_xi8b}bct)r0Vw7QDM)yk+m#QN67GsPu#|GSA3(f}JGc#?oV#fN
zv<mKuv*=PK_f9t&tGI_FFc#I^VSoA%)D`XuN+;BCXByx|Eq9Ram|W$)VunN=HzpFG
zo|{t$HI3ZVUFby<mzN3i*SSCa0M2G^6;;=^aKDX$`BrWZ9ah@7pU(o;&V8Dest)ch
z3Yv9t7qI}kxNppdcsF+;7iR4}+>k@i-OEj+VD1fWL@xT&$IYbzfqrh(4h+cv_nUJN
zyvYrxo6@(qRXWJu=62KTFvJxshZn=#-N%95<ql9X{T_Fk!sGY3kreVD;lBJXER1p&
zybqmY-1gs~^8vS<Hk=Rb+^_$J{5bbB%1cjh`_I9PN$xr-Et%pvWkB0BH%AB7N8I{f
zfz5E+cS6m6UgX<QdVr_zh1@~j<S;Nt-bFgZy6~*D+i~T6@jCo<<GG6<?#?^x0o5M7
z7y*DMZzFBjy?FKmWYC*8rxM^0@9U*7ahS)X$MXp9sc|$O<JFAA86VzU$`bqXo*sgr
zA8+alSn}tE(sCBSEAs#d<b6o7#vq;(?RJ8BUKINd;pO^+7Rt+_fX#7UG1ZlZ^J4p9
zA%a(IryX1*FC!CzQM_GL*%HnBvjUAVyqGZ9jpg0i0M<C(8OlAy^L}jtErDnI0^kJC
z`7?NNlJ^pAsFHa1E8to(?=2lHrSKAG0i5Ekp-^QiPfff2G~QE`9!}?F^`bF@w`++V
zt*3bh=<&+twbC4Vh8MUPJUP6St#Brn_kiB}vpgF;5P7^$=A!W&PqZD*oac?b4v^0q
zqhMbFPr`y+A@9)?I4|(l`~tTx^0MfwQkQt%l(;MAS-sHD%e<f-2$b;LU!ni_S<0*0
zjgFS_+^Md$oF}BBoeJJ#N#LpEUH$Lyz}tHtUAw}2?0YoU@ETr%Pqn-sOCfiax0nlq
zbv!G5Zl#{rdI|;`czY@Pd5w3u5jq=rPG5ngiT5>~XPS8#RRAr#_;$*_xAIu@1h(-k
zMG$P~rBEq%2k&3HAl}Klr2%Uf?@2mRck@<Kkg$jMHWh02@-|Rtwx4&u2z?shZKo~$
zP2SUV9J|FErNsMfp5QrvLEima@b?aH)=tO`@yrPj80PUPK&8IR`<W65_jrqG|2o3k
z@iKTudCgUDc#QWg4<;V)no^+jA<sq$@Nu3=4lu!Mb%LXlysGD*ZHgD^b8~o!{oGcx
z9pu|ygR~=mifW>q_?ugRIrA+c051H@N~m<@FQrNxH-0FMh&%tvM^NIyugU<67r$79
zMsI#s5v(5KuggK>Vg5S_5IDl0-UM)z{~5i~$M|xZdwlqr{~aLsi|n-Q`thfopv|9u
zloC2Y{I&F%uV8-vTy!ji{~0BML-{8tQxL`<qeR1Te$LZyJDl%A-&Kj=$0x!>B>xGT
zSfco0YcVd-{P+=Y#_~UJ0T#zUV+ChCUsM9Q1peEf!$KneV5%L0C-`v`B|FJ~^A4Oz
z;yX=3BAM^E2_S{v{UQWU@gL9<mB#O=0hZ2horZh{{|#EjPV=YyVK<Zi1yzh>@n0+k
zOEzEmILx2nJM+-(9R9sHsLth&e+rhf{O}I2oa6f_X*D^||0M~Q^7-dG0Sfr}wCyeA
zbLo46Mf|5W;1{{TkE?@;i~M0PfJ^-L9k5%>AE&qeGJg*fy36>-Xq#QmH`1m23V#0#
zJgnrW(|caUXEI>0njiNgoVmj9p{->NKOB`#c86NNlxmr;@*kt+zK&l<1<DQl-h+_8
z#;;usS|k4z`b<L;KbzK%>-?ghp|qKw7Yxo8{tl`!Z{>eN$JI9eiM<eL=kKJMyMzDS
zX|QzhSuFtFd~f<>OAp^t23jxQ?*!x)-r%Rx{-BRvFo@QE{zjjp_n)`#m;rK|f8{TL
zJN&HWus+29=M$(N=C7a+n%w30m%*2N{5U(neg3DLpk#!<DH~3V@`at?9OJV$LHq%~
z#SsDz`QK9<ZIYiyhmtA&E1hs@n%}q#ERXmT6jYnx^XO9%`vsNuFJbV2V1isaC@7_G
z={O21_CelBz@?fWXTj%IjG?RG5v2y)1fQOUpu0doM_3O*<iFtb6hyoQXS@W-l*jcJ
zOmBnELxN?iF$RYPZsDLE5iF^M>Z5`|nreLn0r_C@73?-rj@M7HCIf>0f;WoM8X$;M
z!9<{74&7b}61++Vg9Sb(As8Zfrwd9$1;5Z23Bm-zFpNdGAe;&rA_OyHV3C4E9<V4u
zKkXW$1zWGeLX6<$cvy%PT&4U`oS+l4n?t-nmPh5J34;4W7@<UgmKLKVf$$C3O%_P$
z0G}dQxfdNhB{<d#FH!}wsRlVskV41tbiqfBkjoG(py1ePK~@5=Ou<`MfMp53s(`>5
zLCj`|=Lnv<43H~0M03Dd!P5eW=Lw3jOyXlFf`uipdtSihgP1S)iNc2kg2$I&xC;gE
zQlzg);7X^Ni-Loc3%DeBJOCaR3)DXYTox#zV5vlqP78Xez%dWvWr9I}h?ffnHv?1%
zc5Ve{rJ(yIbg4?<atY?I2sHF%Z+nekhUyAx1qqaPxGHF)1Vf!*9v$H81zZt8gJ26?
z*}EpN9E9#h!3V*>ngqL>;LLTw=Q0Si3i3waVVj_z_L=R19p6KDmtfV;pmhuOzk%NO
z2x|TWxGj)+!``4Em5xn!?1G(i<!ML|N-^?bLA3$kt{{=7gnNSJ2{3VAP){{?BZ5Ea
zUkQu~wjV$*#su!a0ec{DSp=4c0uSoixL}4(>=S~MyC6O(xZ{b&DS;;yNKOmRzXgFu
zf<He8m=P3F;&;E${^a+NI3Q&10?$F=H<!>gN1<*v8l8ldi_l+Z;VYDHa}gF&{J>S{
zyBh}Ggdb7OsJn18J>(w3KuVu^3Qxa<ZhHx@QfA#-I7l5mBs@g*42OkvG@%_4{y@pu
zqr$8xG#(Sm>^?w!gs)pb^c6Cw#?Vg~MhAF*p_>JRA0Uj4hnhg)`;^BG5=v<84Ho{7
ze&!J2o>`C!74j&v7bd(*lh$$JdMa297cQnXJ3{yxo!BFVZ_tk(CEQg9ozcR2O5nr@
zRk%(y%OO^{I~ekD!aZMuHC|YKA3O=dgvA(=MBz)z0Zs_(C{%t@82J}il7uZs(BEWX
zNh3xkMfeUy>P`uHtH7Bmd~*pJ(}Yg%!eF{EhY8LM;jYhM;k2+n5I$uJODLm|CCn+I
z_b*$>PDSe(;UpCl<OrQ;2cIka@Eb^+6)xR@#`8k&wQw|FI6!Bj0-+ymqY8z?RGm;H
zyiE6)E(nD(&@Kw!pxTa0Lf(1MiiM_?@aeLULwmXsq2nM7l?ty>L0p;eD-;{p9m<6Z
zXnS2DT=6pGD}_6nVYf<{@gpRvg~hZ_y&|+w1z(M@lit5tp`44xt3p!@bk_+ZDfLn>
z^xFh48idb0f|hH-V|{3B6n>kC#wMXy41w#y_gbK(Sr|fD<QC!Ybce;>D&$z8v`y$n
z71ZrQ&Kk&f2-h~ki%y}b117qJ0~9Ij7XD44wjQBF8U%WUsq}c<5I&&ec%N_y)eiIv
zYrch+0inmsXuK&jUP4E22}`?R@V0QK8OjEQTj`TWcZ7%NZ5*--zg-1%SonT6c<u^Q
zXbXK$c;p_i`@)l-LSjUyy$F_3p>sX#jtN_Sfrk%-M{2?HP<Z_#7#tUVLp_`jE~3ry
zq%eLCx;-VlmIRh*;Zrm*J`(b&Xl+JV{XBH;7kwEHfdeA@7BBD|6lGB+)KS#F21F;3
z`%)-%7UfY?z(q8NYMfj}CI7%RH<9@nVD6$GDsc7?8TG(CMGKSwUZM=DitrYNc)-yk
zqR<YQI4Vk;MB_2hYl-Nuk0_psNPI;u|AT;^=wmyDWc)=vp5O@(Jxir2fuhI%D<2W<
zx&|y*6i;OhAtDCt>Ow_&D*O!-`O$lSTqL9XQ@H3*5ZsOswbTABQZ)D~dLJd))B#$w
zNUsNHjOeEnu*8a--T_OT=+Wl@@uE5N?05zeL?@}LB2o0*Hn5%$G5!blPl|+U(2_*Y
zP@ze(=yl33ril7;fSnR8H9$U9#2Nu-nrOv*=uQ_sOWVK<(E-W^pB6p#2E51=eL;ts
zERlk){AG)NBcINQ#%OlW5vhYH#+@tT&IR$T=yj@<$P@Wd82+5-Yg&cRi)tx;o-fLy
zS+7VG91f)yM7~29i;JS!DvZn}Q5cni7K@(V2HlrMVe#NB5iS24;-#Xjvk)&69j9*>
zl#6)vkgE{2P=KXUG!sN;j4ILSH4JIBXpSDOS41<EF|HAHErfiX=oT$N^`aQc4mF5u
z3^;mCG?(VUM$w%da5jnBDX4H=^p+ORG>fvSdb36Ju@tmc(Fj!+wTT>PQ`jz=g+GT5
z(foB_=@gAqaM|7^!Z!`^a)~z5{l^~Bd<rl1ic;tyzact6N9R6K`v!o1k!dAp1EOE4
zQu3xqG7oldiS}LtxGnlg3-LkGhFNg*j%f8d*c}oTc!4%7YUD!huBh)6X!k_t+QE5W
z#7O}dv5WRl+I&=$L|>E~6OBg$JP>_OA(e-sAP%r`Q9DH=CPX7W_<biuPtF0D5}oyg
z(rFPRA02%pT4n>wjHt*9uI(3x{|4O$#GT#XJSaZ87^CJWcA(vvlemahLuc{(^pv=W
z?G?{}=qlbs2^lx>vMn&^F6O_E{(6YF{0=WX#qaKbhhAc1G333)uOCC#4v8CRdvsX5
zhDx1|h__Io@=>wlIna)YcTg_QN9-emGGFnv$KaZuc-0Ef{KZ$@(HJ1UMxR6t6z{c@
znjrCp23QIff3Xv+A>td9A`2Ct-U=_m#O;)~J}$mW*L1?g8>w6^LcFpVAX5A#EwNGJ
z-Vfkmw0P(%h{uUn(PR)W_NGiog7_G{0Eyz^aOgZCerF9DPl|me;7pQuP8zKz$zp{V
zXo^^v51v!vp0j976|XY^OB2_;4yEbhQ7zPDh^2G_IW6Am1vQ!C(`CT2#Ay-0vc)rW
zZaX8cqj-Og_`>55$Q8@hL(5rl2j%ec#6DEFe@+}8kH+(2xBpR%Z@xH!1GGT=48<!8
z#h*E%qebF+Uw{kZi+iB^qWDq(v|SQ^L~l;9_=kNMlFQ;FpMq8*{&yT$skn3_Oq7Wq
z(s%XB#Vo4Fs}OI@239Ff9fayCu^$a{wYWSB%C3kHU{7p!s1cv0xM8h$6<w;jDt?I)
z)^*~N*I=n$e3drSjp9EpLcU2npDNR?i|wv(ty%2(4QMUm{%%-m6(352Gi~CU^I&Ng
zZ=nUZL%f{|(L2R^Da6+$Zu|o*-D0N=kn0h9(+X?v6>p^*aW}-jypPsCv6KtYFAf+7
z7!a$Ckhm!xn*er8T$u}Px5fJ@)IBKvh`x1nN9+<0@gZ^J70`yo7TQ7G7012=@9&9U
z&H~GQ@ebNpjEHYg&H1SKb4t#RiFxy2{()V5ges68iW{0Rh~wfWA4p7yRd0egDR!aM
zz?AqpC4i>Ino<Zp694-xw9SaOJ_c?3CBa<K4oCthopeybrX;$fM9~GBlVoBYlsQW}
z=yJV_<Sj};x=P&MfPkCCVKvOUOY9+kfX74f+hZ6ZPf6!8`0XWGx(wR9CDn_d=8)uL
z6$B4U6fI~xA}MKs7e^(_sT}Z_WSWkFK9W#+Abce~exUhDqzV9kiFGF|1xQjUVHGHO
z@jGY<l5m$mXRzcCn(aa)ckL9J36(@%ftoOhjjHU9OL$b_6)v$*)l7uMKL#E~N?yAG
zEJ_kjx#eg{`cYsplI{B-5G%?33g+V^e^b~$Uh>ot^yP$Ph+<?XC3PEsB}vAp&MaB7
zq8g1U5@!X>pOW;xP5aMO$@DxZO_T7xfqc4T0T&=c@?|sxPfM0lu~4RD(=322N#MV5
zEnDJ8(S<V-<u-VcBf0)9bmvO4_Cm{9i8DO{d6FOK2JJbC!#P+uFELQOFkg~Hagzec
zWD6`5N|^cdv7sW#C~aOYNH{OT#6?NkW+=TRSwKTlEZKYkmM%+LmIIVXY8hZDm26Fe
zK$%3TgEQrl&z8bqg(R4RL8z1jRl-D-<bB#fRZHISfKOK>yWfPe8p&r?&}t?Bdm7-X
z<iluM|LP<nHk8&&W^VycgXB|MjIT+y(qqyn>AwNiCdn4s1hhzAQlha{vifHzZIcXB
zNlUw=kdj&*lBnm=*eR)^%Yj{z$PqZxEje2P4|^o1{(zQV$$mOa-jKM{UaL=XYa<NV
z`z24g!P5cBrt461Q?jrgmTpN5%>cJ08{8l`D5+|PwmXttr(j}8qFV)lVTpPr{JkqV
zJqZ){B&}<q?Y_kGJ(wSn7^z}+RPq_^LB=GXQ_%H+<T`~&9!l2Jp<!IYJ`CD~T{8a{
zv`$Lq-9+n@B(w@HPD{R^^2tY%mquZCMzZKI4DOc(^#dG`)^7(mD7DeS+)=v!ZMf|u
z-Age=XX!0kWL%_wmB0&E={ujo3pc5A9hA9Clc<{4L;BAi==79kx<lZQ)ZRsz%)?UG
zU*W|O>ETn5KPsK<K;to~^Am8!N4hr&jlNQE`mlnZwD=ha`b!Plp*uiYxEHzurP1_|
z21(s(VIo+XM;#53en_iusFX*WtuX1st>|xr^nVnqh?G{+St&~DZKt$Dw6uXj)-lpI
zDOeFJ-E<sE<D|9w(HJic^aMzdJ{|>aiPCkne4miI(tU%I()HhiGfDasfn@2=zF<j_
znjO&lQ_^+Yp)6JUB?rTmCVl*W@FHEh?iI*oNI#nZc3PVIUydnL+W8NZW=Rub(6wx7
z;|v7PNatRFwjAkSUC^B?eWDYBXQkVogtk2CkF=#fC;gcP&hyfLYQd5(4Lbr*Al>u>
zSPG>ht^h^S=t#(2kd9Mk?xJ+}Bzk{I%9@0S#Zp@*eQfr!bSZ_FN~G&%07|6?euvUB
z=^_p!%B2iCPgO_{(0zkSsk8>PD(OEjz~5?VFI7I&NY9nPM6I;pae%8*i43$l>2@ky
zs+V$}2TOz0LxcWalir}5OQZBX>SvR5E+RF!V<vr{2Dn+;LhoOT^k0f}wn|?m!8Ykp
zs{3e{s^-G)4(W%KP41R{xeW3>()<(P?3Lbp8I3oj#f}i~ld_Sxa_E=xXwn^!HdUkX
zrZkxz%UjYvec{?|>HIYqyg{k$EwI?{NPX$1+>kVht^*HC7f|{0UFr6AsJSQg=!C?5
z>9)C0Ga`M3gT_(m<L^LlOnQj^ztscj1qyjQlrkm&#-&T&1#LpQ@>RG!DNQm%*_1TN
z9bj52tAL?L(rABpKO?O<2%Y=wGT#Zn1F|$a0UeZmL6K}n*{Vm7aFVI14&Pap{34XP
z$Yz}e%~dx4P3U%$4RwLVT~<N~0uNd7tKjsMwXA~)FPWKwNZztHs2=Z-OhWgQ4$G>W
zz;Z<P76tK-%D$oa)-jpA>;!t~Bddr4@Re;p58x-OrxSs{Y*sG%8z8$HjjjdC-rfWA
zL9!2~pe<NdOL@%@*+R;TgvzF9tq7Ctpc`DrWsy`|7%tmJ`P2y6wfA5!Qnr!8dQq~1
zI&enIoGDuoBWtkVhQV0bcDj@kCrecV#LEQqjlu+3>v~8e%4X4_|AZ`r4fjvV^6Au`
zB+Ckf(qx&_D0-11i^%|XN|qP_kScpR6}r=8Zn?0OE_0z6R)%a2y^W`3Y<k}_W!Gl`
z%aXZ$Kslyt*}?*VGqSWk5OZX!shluZ_FXG1ot3SjG)JE7XR2F1Cp)qpoabe4_(48j
zww6Nu1v2?Ta2CoMeuwu(vSswFUXnF?!<k~)Tm>30%Ni+eQz8r0L!eaV;|E%qY}XZv
z%9qPF9RRUH_WN}ZD`mD&5UXUn=}JVkEN~xsctsXK=eQc#O=noDm2IvDxGMXDKAl-7
z^SusGFDosCK!fbWU6{Wnb4!Lmqs;#f+-{ORM+H;YW$Pb+)-3yV6~tR){y428$0U2S
z0mL?07j2*0Wses@utVlSiJVTE>RBl5l6ld2s#~^jH8^`@JBHw4uWa%-2Ka`oj9!O6
z8D}}X=$8#mfn`9p_ZV1i$|fjCaZBbA4{%$y^uHHRcGwjxcVuQNSFsPt9$f?+mKo@4
zM|WjE!~oorZKXx#zHB}%^dqvt$DnOgc5w@^F`1sqaUaNJbU1q`Yobz`aoHc!@OMJS
z7>2S*Ss%sBr(_H1{5LIINn43WvZXIV=Zvh72f6)n6Xkpk*yXqAVLK>)iXKEq`4{wA
zKPUNt{lJ{%KiMGYB7bupFjx7Xe_{~a<ojvacbES`-_r7s=T)Q8Q=U!x6EAt_vk>=|
zZ>2=_A$d<LSPsj7TZhIY^4@P?_o#dYWr~l<{a*p_k=wUV!Bb!Pzl%Zimk-d}5g^ym
zjf_C~c6zyj<QLaKcd-1oJb(~+@iH`q%HIlr?lAe^bR+k;`~ofX;qtXqLlYr?fl@$`
z@`~30qU7`50!y@fl*+bZ<U2otg;@D8UDk+```D?FFJ4|l`_}|{m>i>*C|@K&w@=6i
zUIp!>ygUeMlH`9CfF)Ue=>o76dCOg}oRY790cuj^UX;E|lV7CSCtW_$4qApho&me3
z<)%MiFjJoQHLxuCaXQ;&%jeQ0e?~rQryax``Ir9(!Cd(ssuw#e_x~5HdGZl5aZY}g
z&SB@}bKV9^zMOLiSb=;Ab+k}^jw+^#<OK}?7vwE-pzNaj3)=2ql4~j8Q!M|GqVt#K
zJ~Sbh$kQllTqZv;2n*%%Z}!vquR?ye7p;|YVI3r@<PQyysFureVDO5(wFAFXjXXCG
zSgoA>8nCPK3-rU($*;VF-q*|P6X9rs+)R(&H93O~TBDpb4J}Rbi*!D}E-$51bF+N*
z?+|E_&kly6R{8T9djHzw&%Tasx69YY!HW+0a+>uz<>9lTtxLYH0fOD~4YL7y<kghb
z?UjE=XO<iCbV|zg$@P=a)-M+}z>5L-C)qG@Q$9>_wOeu{rJ!!h*H!@x%J)zt{EqxM
z{jNiD=4x2556izjgs$C{XMKPXx+jmNXZ^mMe;GcF$iqK{#HhTKzM?QDmqx<w1Npzx
z;Cv|G@E&O6^4BWSI3eFcoA*ii71}&Z$w$9}7t`|Jeg)?v`J(e+nUObBY;(UtLrc{G
zMfVN>C%dAB?%O&m)&;?!iy~kLfUBaIUP?Db_dCGc6>Sue_E0EN;IOBno$gn7DLxJa
zi??E!s&Wr0ex;z<VTC81vyUj6=nQaF(d-YFV~TA*V(@$v!L+OMRs1j?j`}G!(Q4+e
zuy67MPk`cu6c7Uyd31CNQW&ei6RdEf>e>)RSQ$X5Vjt~-!xW1)gLYi8fwn;53i~i<
z5sIHEyB4YNqn&D$!uC6qMJs-P7h@5l5IO+FD)!%iqj8GQX|{`3EM5We1jQozR``~v
zC=mjjP`pkh9w!w^9<Y?6@LmcvrxeX^Ln2l2=j&)pQ%Ff^x?(OJ3^Ek&Pl4sM;)Vil
zXDXif4dPjfT>6r8wt_)V*%`(8DEO44D5c3SSMka&$emRz`vf3Q@qMNpt>+YpRK;~(
z5jcs~d_}S|dRU<NbTJwW74h^M7Acfe27E!WA_*)P6%W%eYL^r}2^jTa#b!DUURL-~
zjYWyV>j1D)MZo8fD^u*EYcS=Ccj*nUQ26P<QmJsDhowq!bS<6#suhp@7vxvW`~qT)
zVyhQAQ>&<ng!@+&1F>kVQ@pqqO6wIBbmO`~@$?6vT~k!<gNa7PZd#n06pt=pWUeb#
zP?D@!v6-TLEs7OwU};rsB1hX4<K9r#u3))BphMA%EU(6)Q=!iRPnV+IjMi?&@DniK
zqxhXl{(2QJQckj8u{{$?2Nb7_7_OTNMl#ggQgBGyZN)b`00tG$2V^XK>`i-Z73A(K
zK6?x1M-)Gu0c})Kb_?dm6w9gD^?~9aDn)y!Q2q&><BBsBZJto%-vO9Z%wvHzrTFeJ
zv`j0Wp&#UtV(=);&M1ChKzzS)K^0gID0k1p7#>ts&@ekHb<bd6oRn2|`qvcB$`@$V
zU6k9Ybk$YKs)cShrIz+5?n(>Q<9R5zKaWOF<z63PUdjh-^x9i__A0PLN-k}b4=Xp*
z)+tcA(GPZml&{SO2v!zTnM;V0N$15-<u2NThbcdy{LFFX{SPUg9<EekW^;&8injra
zRMt}EUzGCdVX#IkH&7NaM%mB_iCAR}ZQ$aRmaU-0E0>%?FA|i;sHQkknKX{Z6Uvr)
zICD~&YX?YDDt1C3S-Fn_v?<Dy&%nb|%A218q$<PypgS9B%DnAB)0JGRrpi!Wqs_x<
zr6W}`WGc5%?OK*{<V~<-E17=*oKfDQSa6Q=)(7;CC>vd1;;b_0FihkrAJKYyPAUHq
z=Fcl9C@hz+^!7w!fpUT-=|bfbDG<1*^jt&ngiFeZK(rPsU#8vjW#x$<p|nKVvJ>*9
z%FTa+R;HX(Kux*w_pd;!P@bf{WtDOt-3hN&#!&R<iZYdM0n{kJC;_Nd?#qCQtIFCj
zV0B8>1N5a{=}1KY4azo(tz1(cS&P2d8<p2-rEF5(rS1N8<(HJVZ&rF_q1!FWUB7|W
zuKbba-VS9OC04tXz6Fr)Rz5>3bdU0d5wP?sTZRB`D3{vcZ=ce37Fzn1pHg^wKsim(
zg`3Jus&~1ibUF#wZY$^Qg7<@VrDF(q?kLYwY0Ho@un9_smEY^(+g;@rx+{54*+L1@
z`%3RufQ=|C=}yk5GUWomnDY5lfCoz649q`N2Gdz*T)CE_w-d@QdLS^Vv=%|<l(LjU
z9n;F!=*vKll+`?p+KkfvdMnTaDvwkU52_5u!Rn}DQLxWNWr+aIRpoyfy4_S?(q7tK
zwT%Kc9;$T|5cgDlvJ&8sYIPX|4y$UP2Fnpu<kw*FQEf-PfP=5<KGhQVsn$w>`KzMn
zCk#;a)qyimb>IF1hBQd^!!no%R((y6SBNT(N=8Ce0?HqRsW#4s{Bc!qHCVz`&rs|u
zLN(_Yut-%Oy)jX${iEQFRxNxF;xVeo9)MU?TLpR;r<xxETD<BFTA&kDr^HZ}sAByL
z+6h%)lpXM-%JaW0v5L7H+LBdcR6UcT3W<knr&RxY70#rpzM^M6O_fA%YPxE}AWUSa
zhPDAat=jW7uuRq60qD+B{SpnG*{WwM;piFF9Eu+0s3dv}P_D{{;_zoxQxv?-Q>8pX
z|2!&R^&v$U3sl{-aV%7csTQ+HmAD?@g3A3P=)S00l?v>VYIP2j7OOfV;pk;mcOyWF
zN|g_mQq_AWV5v;ChPD~yss(z03e^`a0F|oK^xqAtR4v)CTdfkl4}mKx=Ver7RHK@!
zLf2|lk5g3gswzAWO6ycl?8SK1tKN--V1ugjIIt#F0@XBLSM8=Uu4dI)+TOINGV=ji
zRl|=%yiN7yhhS+}O<sYC4%KsX>!4Hh!vl1%N7YGHjJ+yHy0UyjRq6>A`;hAR8_+$h
z+C$-xyQ<jPkRMSsegK|P)n_!>kEzmEgZ4l*uMw6Ws>~Eh9#=^h0-I9RQH*0+_26lM
zN2)sN+5z>_f6(oN>a)*7i=#S|QpZke-UxuRdJd(WUDUg4z<I>3-n$fPj;hBgmvT(4
zeHZ3^)C;oUx34<p94z^%ODLV~uWqCol>qhEFG4U--P#NjLF)V`!5OT6GYqs4wHKXi
zL)CxNaW_o8mSV`q)m$3N2z48kP(-S|FXK0eQkPNuB3f<VMdb=H>cC#0v1%`xZxYlA
zJ`hY)JDdaUgnADLw3F(^H{fWJI+w;NS^fKSu#}?SQ;a^HQpc2mB~@K>8UktRTM~$;
ztM7$_mZ5H02<)`FX9ZX?)nyb;%u<K{16sB^z}^9;&Zs|G4ZCO6Oc7YmtG}-UmaoqK
z44^<Qe1t(PRBxfrO%$o$q5$s&wa3pGgp2AIsQmwuI`Ts(Emqf#LHx41oI=SZ>e)x(
zXsOzbiY3a_D`;z5u72}Z3}uD7ZzBXM)!xn&PpDD{t%L4rbrMz7T~U8-0#>7LtplxA
zz2<w!*Q=8v0b13Qw83sur_4p~+tuqt(AJ@T;cs-UQ++ZI;$7-bx`FkmpZprMUiClM
z!FfY%ClCA7K}@LbSC_2-7*H<})B1N){T*#LZmA2MATg+Jq&&bKwZ<I|52+t{0~=O<
z6#?w7Ix8LK@2STr!*O3-Tn?op>hJ!6Yolu2Az)+bJ+$3^pw|3^kr`LNNOxH$)cfy4
z%cR=pPtc~+V^71wX|)cY^T5aZ)&Kkj-81U)eE|D4n`o1EK(mXY69+Z!2FN>VR{jA&
zCr#?VXmr+W?1vXFn!Euhb=92R1Ml55>**<T*L2cnk3BT`^8pTNidMmkBbvccs6MJW
zG!Gp-rYWW?sXm%Z`_X9k)tD&U?5BBwil+lL!_DYSkmeQzRf07yvY|Ufv-)k&LN#t@
zAsD7vCjvOGd4^(};Tp>|{Mr$k=y#wcO7nmsv(cKb2f-4f2@i&{SdC}{#N#xdy$$p6
z8uk?2PSEu3goQ-A=2i^UoY4I9E7Y9SB>x{Ik~BS!K~1uz$^>vqvy`&LshUb}U}+jB
z8`Pw0I_ZK?hGv?MLz$ZA+MzT{Q(prwvNZ{3pzMq$`V3fdH1jEBm#bOQ3+$|BX)NrW
z(?n7t>Ac3C-hyGv*L){NYk_9{$52zKnYR|c6=^oo&isPrUja;%XfDuNQL6EzJ2hpR
zg_QLy*BJEBU7=Y)lV6qQ4lVoDnom1HyQ1l&>&RC%IeduMY1W*Fc)jK|`rciG#`8yX
z>6#|rUJSt|O%sJWuWNqt1F>1-z<`=Ijr?`c+BFd-bf!bIcm{SmHNR7^u1ix@0D*3e
z+Y$)$Xzu+A&KsJ;{^0D>d_*boe$9h=&;~TDHh6JUlSG^LTbkTFfZG}+JrIK$zn|#+
zyQA@=Ow?V?OV^<Ep2nvFYVK<Slu$FGS^Oz<k7_tQpp9uf>5%hK6HeK!am_-iTA0x6
zdJ8O*nm;6HoYMTb8M<dQeHXyFUt7Hd;DA=R5RC`56+(FLsMXS(?W7&@rGFmmqU~P<
z9#`$N!2oVr_d8&9*Xk)`;h}wnYNoukPPgFbA#FMpS02_*i{arBt@<ojj%w|cr8=hl
zu@B-t+G<Lf`D)kHfh9m2dJ>I++A9<(3DQdGw-46xDF6|oRW79WFHC##FeHv^-zxwJ
z*M1QM5UIUR;h!jN8&z^gYa8A0bH!+1-30ToT1x}e#A%nl0a}9gd%97SsI7V&22W@s
z*P!vFwvB30leF`&#dS#5PSWgtN~?PlUZiTjBxPw@SK3tC)3u8)p@$jTXd169?W*rE
z>e<>aEl_htyZRjraE^8svE*uBrl8qb?GCb=r+qRU9-h+<p9VOu9Z!JU`C7jL&<eB%
z9>AGGEtewEMcT!*>$sr(h04S)YSYqT=#uu|Pe3dFRQs_FCN68AqhM;ORzruvGHo^e
zqUG9$AHdTJ?QIIdRca%>z*41M8U<Rl_6()ru4ubgLtBmZ<OH<TYB|X;e^t9R;K=Kb
zJ#R1WK;t#-OM4;LsJ$(P`6g|{Gr+EE|5^^YX6+R|?6qj~s2rqKJKhPFcI{=FAv&}}
zl*;VXZe0vomo}QRCf(X$T8(<Njy33Rua>z1v>V!5iWT%}`>4pNU;FF>s2<QhveW8t
zQ|m+thg;gr<B+(m9qU712DRm7XuPBSfiC$EY2#l97}i#<hnjoZtv!&tul;~ll@YCj
z4zvf_2Xwf4s5KP>jB7`e04B6mw5m*MU!nPUO6z+Js;9M|d<)tm?X|N3QA;0t&Yo;W
z>p`6<0z8g7DZN`xx|IhohR(X(^U>&{^Q58&SKW6>FzBXp^aRaaC;JNidgzp+=(eY>
zeFSn|x?&43Z=Ea;a))%8y-<Bv*FuM*Bf4EH;r&sal0xRkbYT>H_0cV`Q*_Q(_YU1t
z@YChr0OqfYtB1A#T{``|fx7Ldpe;z(hV-sOux`y2$cN~5mOvm>w^R);!gLR2LHBW8
z@;<PH>zZ#tAVL>+4<K6CB!u@dx(}8^b*wI)Zd1nTM!y0UuRF4gPN509*K^@wqHZPq
z=qGgB=ED3*-4cp>ChK}=)=JSmhyysK+w(Q#Gjt#O!0u_?tnc7VrY@fHlv%pL`|u)L
z=k*Q@p3$u<2Q5c;fzI{0I){Iu?5vKP1$%kAujzp}r>kI7!RC3L-$r<vuPgZ#!~)&J
zU=Ry+)iiq)>Gnx5P#1JPyJ7dDuI594OS;v?Fj1`gh6FC_Y92wLME5>DGo`v<cYrco
z*KKf?>q_XEtI*xf086EAT_psnbpMwE*Q#|l-dcbO=88^0b@(;9yW^0k)mb(IyQ*W{
zhfj67i?#5(UYAb0(FWZ;JHR!aA074^bw<htH0h!k&~{z-aS*U(-TEDnYthA-(Ct=T
zEIq(&I&4z#;^^uE;6;Z{w-&TcT`uJ??OnQ0>8f<MZgLVG?a}R^>sY<I!a3l%p~Ef|
zZ;r0qhQ@x~tTVs{bP-43=uO>LiW=S0ZG8irw{<i09t`TnebL`Lx?EZZhIEHsg~4In
zzk|T;>fWsYc2BpA7M1%tCM{7TcHN0?I6SKRcM-st?pZpVJ<z$*xp6|b-~zBo-54$Y
zQ@U_Es!i*z`NPB`T>;g^%;^4l8A|u-CtT5ZK;P5>r3dxrUxJ5@`Xnlpanf(08Od3{
za|q%t`p3V8+phY~{or)d+b@oz)m{HRJs2MPEJ{0i>OZT4gqMD{6uQ0jkJHm~NWXqN
zBo6CGH-P1cKBNjB9@T%a4|b2~`7}HG=*xeCL0^4XG<xW#_og(dzkUa;9|8I~^r#2w
z=TIG0kbWgqa|P?m?Jt8TO#dY97$fvYSZIyZvuXPprGF|Jx}){GY5IuKAKD0?V)b9T
z0>tTEXu6BntEjRjL2vJei9~$~C6G_(RXd^Oq`po9f0Ohs^!g_28xuiG(KpY5qo?$p
zo)Ayf?<#v9Cerj_<6uqKzqS@U8Tvy3qIWPotLDSgZ2f!}ICDmSkZKik^zn_bl&io0
z6&la#r`eFp)2B4Si*x$#qM-D={@kmO%h#_iM`MBBneJ&6>bssrW08KZ542p+U%m|5
zMg1pKjde-CnZnD(`g)qkFY9ZmwxmSA#!k0%OZE64yLg@SIRkL5T)*u@bge?~LABA9
z`ey?mQKkQpjy2W#cZC2~^n1*3tw!HQ`;uBczG05HN&lAyTI%!}FF{Ma9v5ZsHtFMO
z3x7@D%7a{^Uho)bP5Ryth+o%te?qC0W_`_O5IgiP^u3ZUJ(t2p-TF{R(0cR{^y2jD
z@6s9ThMqSICi?VN+UoV|uh9ok2lOA0gLYGYO#see{qsrCa!)U#NBzG3EsAxI=&w_X
z?14Va4PAPu&!xcbxW4{fN@Y&yca!-^z0eMxDgA*#VAJ{<U-apbK5{+4jNXlA>HUUQ
z8j=Hscskx6G*nRl!qJdV`vWJ#;%@ZG*)Wv`FI)_^D*&#BDk?Z}Gi;$Sq`RTxcd&RE
z6z{`rPs4p&>9#v~8FWf`<8Ansz94nT@Eet{95#GJWh6%oK~&j&)WB^4IA#c?2g1jY
zPDx&0!|W<F`WaGp!9#yTJY|pq4EIG44>Y*1f{7qQE8TnvHoQPR3o(qYhfkq~p_8x|
zW=Nfafc>~(@+vHa8;%S?Fv7qvL20C+`B#7_!=CTa7;QNB-$}xdr~(#i_%jhh8fTD|
zLO$N`#B4Ms7&h~vJJHbn5juLpu>MPclZNk~hoeb`j$HuBhIe0wGbx6>^fI3^>{|_=
zQtbw*59HGfUMta>ZfLKE(hP%lKFpssNRvRzG<>%lv@An2#j~>wYblX?#<0i)FLDes
zIlyua3|i{W8ou2IOXm&W3IXyB#$P}yFod(ArO@C{Mc74#*Im&23x?%X3476CFQSw2
zC4*`^c!~{^l*PMj2u%b}iQ)fVL}RJp-UwLA3~$jLkaEK|9lBOwI7qejm4^H*n5Z&j
zya<1*4O5FDe#LN`uo}bS`7l^(D568?Rm0q1V0DJ@S0GStSl9>9U`V&;LCrP8vO0i9
z!(kl^HW@lyK)h~vG7xH-4Y#PUyv6V~ZOd8>E58M;&7d%1EZPn31z_ngWGcbZX&AW%
zT9=`WQX1Wcpez{dF=W$P(PuENhHL!>`x3AW7y_RL?WUn=wjHBz%W#_xE4K~fk??fT
zAZvxvJBGV7z(a=ILX5?*A+!S6U4!=?VD}6rD>&~P{(T-wM+`Y8h>seU{|VZdL2&~E
z^uSOX11%2?HM7AvZipvGCk)#uygX@er1;d7VNnVlJ*Evmb-;^91}Pm~W(<GPMt8q)
zJC*w!Fg|%4jR%e2EC!3CQAQsVaWd{&0Bz1j;Vr0fF-Gr$7p}%_RF>;ztT+YWZhU(S
zEO{6MC=K9g{F6emUd9Fcp~c(iO;rkqjIGP4l=ZOjb@~p#5o3%aEFCpY?}hv^<9igF
z@iG2&7rK3oYwqHQ@iVUFL(t!tJOa)@<CByU2{NX>3zlHx1KPrb7~iUdPoc)HEPycM
zLRyoL8(lsJE!>zH2Z0FV03~80jn(C7v_}~SDDWR`+<5}6F-CI%#xmA;h!RP0#viE4
zA>Qa22Q>-CKc!$vG+qpank3`&D%edn&ZT@|it(#p_<PF8UkH{|<I)M}Ofw$Mg`?@l
zr>WvG!?@BHET@etNj%%Q><Hw}*p0417@-_vH(kcgGtPPymd+Vpp|3@pH&)C8E#H_u
z4_JZG`VFu`;|Y3Zii}o@w_Y%w%mMA9@%&?uyJVEJz*217L^ThWjRp_&rNo#^(|W0K
z=~8f(8Q-J8Zn^PbKR|`i{$U;LRvHIs6JKQvPX|_Q9Qy#QSB#Gyhte8jF0H1u##SRF
zt{T@-EVj;g@D8wgV=}#z4aU_pHC!`RQc$wdxbsISYcke<1MIr-`v|Z!8{c~upvCy|
zk8rKk_#{=Dv>8SAerRjQBY-}27++cmiB4k-AE3)9c7)Py<8Dej_833f2GDDi?S#M$
z<HpU9?=uchqOsqY%fU}EU<{;=-ZcKY6pgoxPf{7zZKL>WV1ve$^iQ_#7`HzHHe`I4
z4yeP%tpXa$yT+xXP<qd}`eStazLD`7SVxST_hT$ZjdLj?HD>&IJy;$Xoj1YmL*p?W
z<i?HfQ{->LIR7(rZPMsw1Z~P#N)PF@@g>S0J~D2k$m)#osu<4fH$B|}Wsati%aC(2
zO-IrC=WKe5!Z$9aZECQ(n&z>9xtW~W;f1@2cM{q>Oy6c=xIIntX*=j;T9ks0dYjfR
zgHMM{e#5{Ho0d{V>Jih_EoeDvn&k-2V<ra&(0oj@C|%-f+Wr!>_?ed92aCT+w~;;<
z9boFF$tcj&@dsFgOn-O)3pO>;R2X6k*oVeYQ}!GPhM9tBuXfyYlgh`!O)F@ri!jAe
z?ljW0b~9L_Oig3(DcbbScQ7AgN~D)6)|A%^opGjuQxK0gsc9#ZV9I;|0ehlpipr6b
zOiK?#BH5JpB}O*Ilur@7Qzma03}UM3o8@pg&9s27m!z9a$AD#+_7nm;ZTkHw7|b%g
z_y-!ZP5;{i*Up&gRzohwltlHdxuzS9u#ji^d<p{ROd0eIhV!OFMKGUlH?>$nEHK4T
zj=Ipak|IkNO-m>@c*#_d4yDB=Gvy*Ln+9Bfm6#H#nyb_#r2>pH(;pPtDL3tA!QTo~
z=vU}krKyJw!BwWz*I=;Pw1g(8D<%(m4{A)0jl)8%>0B4YubS*TDj-p3nnfA@dQ;Id
zur`>yUVv}cOjUfyH=25X2G(Rsdk7D&n`W;7OS7r)W6)YmJsHr}YHAaK)@EvW3wGO0
zmNDq;FmboSwN6tz)q8fE@b=?1GVS;apwDzL6yp6Ry`3tN224-nL;j|zd>I69nLhV|
zn%gD^E93`FlP>|gW180t!68%CBY<I33Y}N)nwB4d+xJX8P0%)K`jjT!F;g1dJ9uDf
zruX)tsdh2M$4x>Sgb7p3F8nZ)roRmsiz!pVi<AYKHhuXK1Rt54cfr#c(`9-&_nW_L
z12|~@bOAhcG#f5L!pW>11&g!!yB!d4G5`HLOt_ji{daZD+$Vsgqvi~%Y&&Lt=|`~m
zm^CM0(APXC8|MAY#%G~3(0rF>pCGfXn@V|t%?l{C5n^_}2V$t%Qv=p8^M_Nwj+;ME
zhSG5JKDxUVVSbI0iIL{rv=@jn_jLh_HkTK{ix{&c6iQ>wQ8&;SXI@LmmsInCA&94$
z{}{(mW|*5=(U;TacXmTrrdfx>v)v)fy!<6t$~Mn)061fgcoVvF%x^vgrMc#%H_(f-
z=0v*8muL3-6)fk>o>Urh-n^UvmVEQCh~POCm}3`$v(P-<0P{uWpa08Hn3;6wxM;S}
z5%H4wPuhwUn;mF7c-b6FA#Zz$IeZS#Qgdhmh-Kz?ogiOs-Wvg8g?Y)}uv=-qwg|eb
z%pX|6Qf=1J5&nu<N?DT{vyvRGH9Jp&<*HdglWv_kqzJTnvnOS>8q8C@V7X?VPZ9q{
za|xYwn#?_uz^>cPf87CVvpKN<@@?j3+TFFAldI9#VIKYxJe}q(ei+0q^9^^n)@^?8
ze*isZw=6XFnkW8(_czSaeQ4}6SN?;M={Hvufi_@HqKW3Fna={aWnSHd#@l8k)lCkX
zr)02q$82ZD!QhbjS-ONcY~Dcm%Dd(b&!MCD%t_DT>AY`VVn^eM*>Vl?qh^*7?vI(>
zDGTwyT=WxY56%6r!HaRT?MVnsnA^+I-%0at4iK0!`#Hn>v^n4rTzh2B`3jsf<||sr
z?YCI%RA+a<GW0We4qDFs3VBD%QmScjvb;|LZD&gz)sMJXd<F2()$*$^8a*uM%h3x@
z%iA6B!pq{n5pv!Z!*R$RviwC;|6z-2H&~8Xq;#+As3nf#rN=CZlp^=BeD^s7d@Z@}
z)B5LUd9M?K{+6dH@fKit^&yCXmS3rOA;@Afp)<jjYZ+(^v5YMN2(|n`zkQe`n|5Hw
zEtzkFGu(2Ia(fY$Ge@B%(lYQnyoj<mya|7!E!LBei?OKtAP{SbrMPsQMRkh)Gh)1D
zwhhCbVA)37-$ctd6cajOd3Q5-PFe;iqLyTtqCjA>Wp^YvQ!LSoVd9kK$q499wftBJ
z^J$hUiY}yEdg<57u$-d}!f8u0on<pEDQti&%kMNnWm{TbgX%Mue>>>?%dsqb1!%5C
zeH-#;Egglx@+|(}Vo1(e1g}EyyygGsN6)v|si3yN@~08b6k4Ly5Gb;&eGcX?Sb}N$
zd(jd{YvU!0kgh@%TgI#amo2gHLA=Cb)&ncG6o-Mc%u*f$W%hE*VY-W7VbRcat4fQS
zHq%!uw=V&^YH_5LSDj@sg^TMgXK0_$U^%)52CrGv;TWez%PW-7ZL;vTLd$i_nI2%x
zmiK>zi55!-otj%M?Q{vE&2s-XSlTT<G?#Q(N~y4*({5>?ilQ!yk26@iExweZ@3GvN
z1!Awo`7>y{VR568?Xv{D0x$Y4)0CeXu<ZE^0yixyVgPPgLZ`ra+j93PJRG#dM?=dU
z%U7B3V#vb!7Y2td1_lh>wd{ThEcYz#lfdp<?3ZZT8L^C3Lw?k<rx4hfWnMV22bRCC
zL-#{V8AYAPErJ(7o3K1J4Q-Q_Px8PrW!dp0OiWv<lR$f9vDHIh#_}AUQ1@Gt?tt@v
zb$=h+K4=ZrqD#)!`4lO2vHtNgfU9+rovyXHS+!Llx?6)Ny69njg${7u)`PSwJY+4P
zSmR-9;Z4wvS;Og(_px@;Rb*f5o1bAw{j8=qX!Ez87zZuDI+X-kuyreKe?zP@Q@}#4
z9Su+xW-X&=%5m%eQMEz1mHz^z(;}=gI$uOui#1RaWqq0^^l0nv??YRRwd*5vE!O(c
zhhT}bw$Uap-umWwU<p<Sis~m?Usizggmr-&-9Bmcx&oa^)}4#d`(*1UeGpHvw$s#o
z%DRfO38~gYt-#W(5sPU5nQoo?2b5-5r{f`b+UoT_K&I9Fe|XBWte?<tm~H)nmeDiT
zcW4lDtT)VH$+fQf3);?F<0(p>XKkT<;5qA15;}U`s(%)Z`POY+5Gb%(`v3~91wH^p
z)_Ed;3)Wc7C3c64Ryj>+m#iK~&{}MLvIM?ew!S`q#uDoanpjJ%1+<=&S(Oriax3${
z5P<dU5X@IvKc_0CD(lPiI#gR*%79(5D%$~StZ8)buGT7v1nsKT{|8v8vxZbbuHL%%
zG<s%luzCfe^_ulSA9xzAI~qW2va;!_-F55jCdfBi+pFPBi&abSeXI4ke=uAf)&bfT
zc3S-(gNI$#EuTQH+j{9)DC@DlNONGX^)_9Mx?z3#35-Rb_2vx-^jjB`>H+J?3TU}$
zw>nXE@h$6XJ0Wq~`ot^HHfUYH6WZ=rXGcKWkkyqU+QZh@D7tvpdQJ{!?pa^T1-Nf@
zS_0i8)*bXwtWj&%Zm^75XU~S*1M6@92f2sVZrX&8TP<Dy6V~sj>~qrk=WWPMS?yy@
zV4b#}qlfj8^;s7XXRH@!@3Y@l?Es$+*f>wX;e)n%N|`y@D(OJtWNV|baJIeB54$e5
ziuKUuYFkBLdUUh-CBTxq?W?yT;9*;k2AZeMNU<3&TU{j@y=`+ohM_~YayymQ9JUov
zs{4p7@e1r7wN-`!J7%-L1WP`)hZKwQwH>91n4fLd1RDKqQw87*u>DFkw}H0BU&5In
z+fF(y1lv-k077hC(+~)??VvR^%=Xz*7(8y9>;x8W>tVo|2-`cE6#tC0<wQYSl&vfP
zYNBn^7r+x|+d|Qec-tRzluxkzOuzO?+wZZUCE2dbKt9>Fk><cu+j&~r(`=to%plzs
zK#}1Ln~qMJr)>h7(K2o4F2k8Kw%D5(nH<|cMqs(NzWKEOJZpQF&H#Bf4JByK+0M`g
z@VxC;%JJpfn3Ul!u%*-dT4?)R3QI*cTw})zWPAA@)LgW+`~z^wwvP_F#kScLoV;w?
zM`7O*+v9(MR%#2l0o7%;<+%_qw;iJ=sKT~hNu}hKHW8&Us%)3OfEU%amn9%xv27bf
z?`v$Y)S)xAwk!vDan-i(JFwK*exVOA*8e|8*BzH-^~D|0uuL<vvSpf;m7`sjS!q_5
zsl~hZ-utD}te3q60hzKzw&DOmQ9uF3iGYgAMnHxjAfO=g_dUPA&gb5H&i9;q-{-mG
zoO7So`P3f#6gQmzAs5e0=NWW2{g(5rhp4P^?x5pIt@B;_=4YL=I~iK<99Iar2ItKb
zKyGwy)`2*hoM+^qvDulm4~?zPXA@z5n{zxZj(41=76G)~dGkh)4(FNSFu&9JOFA8O
zIse2&<z44avZ>qo4ut`GoafN2b<cT*2S~5;l2LTK&w1)+2=qIjya3bgI}1ahcfk1<
zH53gxoKwC7>yYzB3V1wl9;7=(51qy2z8!XsvH^6&`2_*wA2~;bfpgUPcq-b)oX;qM
zJ??zuK42!CPj3SDr1KR@z;a_8ZU(12V=nE*Js59(0BCQ<J1yv^598U@!1QHYNq~SK
z!y#A&Y=6dP3eoRmJWigi0LIk>zyvZBa`5b8Owb7^h*5GMmBEbNw19;$UZX6--Ha$B
ze&$fdUb-(4#&BN@P2r53DsV<HK5;{3BqP`g62)+$8GH|;!Wkr*VQhoGIL2R&O;8`t
z_{|@n35+B!Xi8*!O^39-jD6(lOky-WjgIbP{6(k1WJUoKEGdk!x51Licxf?un8tWS
z8Nlg`Ir%`zV0`^PDl-{>Ers}g#-iOI2N<!m4b5W2z6X|r3@?fi9Afn0`Ns>y*zpxi
zJi>@3-%d88U<#}`j61Y@KgyUQmR!b1X%Ng~jF2PZ7~=qaIrun3mw?KAhMBU9PcYu1
zpYSAuL7}e#hVu;QEo4-LgQbY^&n?({im{ABZKoO0<ZUiyFas$vTEh5<=8aN@ryMY6
z7`%RT^ep2^x&T+kaQgw8&N1c|pmd&bh9ch=7>0UaUt|>ig0^zTLh|WWGJY-sXcgmk
zx-52;A)*!F8si5E<gPRBt%HVY#?xk0-e5#rM+a{*vKG+(^A_VZS{!Q_-s{j<&&a1Y
zu7PorQi&QF%P5xG#5nvCDw`Rn#-RQ-qlF@?EezQ&U}<HzaDd&$ST&3v<_=>z-Cgcv
z#L{xq#mJ;x-Cai3uMoJ$5c#65m+?_B?CoP*pqa%nz-T4+{2-(CWso7p`L$pjW^AE5
zR3i+}*?@V(koCaAafWvp+9nva<VBifY}EqIjd_Cs7<Xp4H;nOME@}j)H*;APhSG-_
zPTLz_=51e;b}|o8wt4{5xfz^+Oyex*3wAJr>1JaHbIJ2ixSP540UE=ZjSIjU!So`B
zPbBj=&9>3ZiyE}WFrU2(v{>eko*)U#uH&doWLD6lvzOWY69kf(leE!JVeXv-bSiTd
zxlc2g&s>KwnaoiE$bP1Sl5Gz%9V2uR<`8oieUsuabJ!Q99OgYM1dlRbq?tUIS@RYo
zjx(d5KwCcZclxs63Fb0N&?#j8@c*MYb1{W<PBG8L!k7}~r5uz>AqNZ3FuiHZcaHfy
zdDqV~x5mPl3(Um-Uu|H<I4I@6n)$H{1aB~9G|S&)e&&j?xW#;t4zo4PN8~oHXBKUR
z-Uenfxw{&fBYqHQV!BhHq?x&P73{subfHw(7G@$jWm=hwXb;iGtj&e^9p;v8P~Xn{
z#RH`d=Hs72yo<T{0tKe-GMPrOb~9tXhTa~gn-!q<m|OhN?LOw8&!QLo%%3TP<397^
zDPRvUlbawg$V{QM#35!c9g>Eb^&*fFW?VloA2CZ^AwJH`$pPmCbC3^(lgwV4o?Th1
zXkX;UI{!B9Kiyep<dE=SZJ-Cyla=%hy6w$6LKlX7SZTD-`?5l)hkmSIj{?n~^)5Na
zcCtpv7Zt$zHxeX}#asgMU99z#@)*RrM|nQMEc=JBB7~Jsmk4*W+`a&2C@YQ)lrYxy
zr>Eil3un!1gl!S5KKh7YBx{EdB#Pxq(a$}srsvTX&D!V*`8ZYwJv8yG^s7*x!1ADA
zND}K+a=-3l4Lt+7WR~|57@Ed1d=E|OtVdxG&tTos0_*^*upez%tb0q*`-7}&9|6U2
zgtdMH?9OKGj|WT+YnVLgd8|V<5In}ZwH7ePS&b(lagrq`XI}wpSpozKS-UQQ<uogl
za+Zo&p_^b#32Pd;CC;*{$-P&`noqO)Io9L_aGqzCUx5`DSZ&Xu@*?Xby}p+mtnCJ%
zU1nXUSG=4R7XwXKSX<u*PX+6_?|@dxvi}Y%uCf*>&~}Zrh_WiLvpx$4S~Y9IlOQ)(
z+nm99leI_*xm&DKH*nUnJ|rvZSo5Yqyq@)gGpuM}O^btgBP)pfc}*-wH@!#AtWVZJ
z{cV=@8yM5Vx=&u%R#p<t6m6^v@u<ARdOrZ9leL*r(Ysjx{tgv)S*2Ui?R%^q@(1>^
z<g^LsV@;#`A^of}0if@*4!#94z?wxFNrS9c7K3Go6*&wm9<W>-8&La@6)+zX!>sk6
zfQ+!-Z~=M53Z#6wQP!U-l*U*LinEThW=()hus%(O`ID@f|A0)fO5TN`uIxrGI^o7{
ztOIdpr_luE!LE54ZJz8hI!So3kqD26n_Wz!=EKf<)&VqMwj2FGe(Y~~ApY#DYrwjb
zox2M#0qmbGup*HC(i(8?Vn0c%S`a%a0Byl+{zaG;!e-9~+08Di2WTk!samjvu{RVz
zAe>$C0Z0V9KNTpEY<CJYMzKGou*n|wq8BLjH=3QF0lhJ7$qvB8vKQJR5yu{*_*6XG
znd0vW>;-S2GLikt|353jevLL%N$eCGK=-lF($O}VU3mnh6m~W}vZ?Il^jW(!_P>iU
z&gtxEnzb_6jT`a1X0q2ap>IFC7WZ%*P6yaAHK@&EzquTJI>?ToOOuD#8cOp!%x<NH
z{s?>8O2A~ZCA5O%u$R%1>nMAV4`7b5cln`D$Jq;AK=RoyQ$GF)b}OBXPqM!_3F`~k
zm&njUHeOro1=!EiChZh^CcSrCPP0Eb4c20I;D0c<g#9F)cT3rQ>rpzxRy_uuvuyV~
zz?88KeULxLe*Y-cpJ)F<KA{Wj-zU&^k^T2V$X#NmM~Z($R>@0r*Sdlo%7vy%_GS)H
zs@T7~g5@gPn|`}%>`OnRFW1?jbnvQXCsm>H2D_9FxHsA5!)Uw3=Fx*t!*-^Dsb#;h
z6kv6113CBW*)Q5*O9MO94@NYz{q<nE&E`?qqlNveBMR2HvOgRJPaB)P2P*EclPFT(
z&Q5v=&<^%L<d^GY^PWUo7kiyMIPbDs=_8Td>`lv1*~6~=37q%Xo^)@amt8~tsXq3%
z6kzFRH>`ja_u0F>z&XHvll%dLY$b(4huBU>$gB8(y)Oi|J!DUJhr}>Dxd|qYu;1%K
z=@Gkxf~TWw&+kFT@UUPE$JwtlAveKp`~skp?9A6drr6JCg2j~+{sR=cafCsz$(@r!
z2V)P;^xq)h$?>2>TrW;CWi)tmGFxa@=flyI!zf?Q^W>rR<2)CHl0WAM`cBMF&cA0N
zAHbP*91?+?yijP`#c6B@Oc2Mq29?2_^&8RO5Kdbc1a@=2>;_9HXTe%@DU5R{3oPNB
z{^h`o-~_EkTO=oz4!BXA9S3IMsoulcO<6<HoEP~pF@_UMxdgGC3SX#*<E-TYJDw9s
z&YT1eV;eXVIa12d-piSy&uJxbKBBDeeVn&weoE#vOb1EfeCr1lshl~z088W8W&tIW
zbNWYU*w2ak7?lS&M*1F=;}B={6X^C~&X+4-@DYxZHiySKJ$u1(l9NXc&jQXeI#(2O
z-a8Fa#2KKo!zqsZ6_C@M*mnV1%n2s1aS7)j-6k#N_+0_!Sx(+1l*%{_7hvHzjywzE
z=Q(Ej_{0TH13B3*Iyi4_MDa2w{~=h*Ig<a-!z&zF8Pr#B`Wn$z$yt{M^Q$;giuPRP
z{6@iyYn(QBbo4qW)q=Ka&g}J2af9=v2Lx_%cF|*Xi*tSn6xML!=K`#jbCD87>p1CK
zp`o60;S8*A;5d3)QEcQCQ!-o=XFhEZnmH~>0KLswbqFT5aFmpF(8_s85%V_A=ULEn
zhm%2@rFKrJJ4zj#ltjpNa(?#%C;pq|H<Wrf%>%%^$N3}$oV}dl8z6n0Ims}spR@ER
z!0vOp9TO-Ha1M~Wd5|+}5)wn4B$`<sa5}G`@*yYk53me#^pC@)5l-}Slpb-WC=Y*>
zbAJT}VT>c9kJgNHKJG^41SdNHnkG42ULaE(HHo`&AO9RB53UbII6S#k3OqVq+=6c%
zknrYy@ieUQ;pR6(g)jFst=@jzSx#W}=bob^xSibTZ$nc6_t_ml3*`Pq5vW~UGkyIt
zh<nTm>|kzSKLkR!D_?;4Zf?*+$c1u+l*tsvO<fD<aIVe-mI&^>Z=g1kdrU%JjVP}4
zQ%LOLhLS@dn!D-$cZ0ZptpsQ+w~$UEaolU<q)+6Yi-6sGxq-A~Byn5r04;?(@h3<s
z_x{&Vk;Y9vgu%<?u1*8XelAl0xdU8&C!h~;f4`2(!`w9mC>`PE?jf(@QErwWByzcP
zGcnwG+^Ppqc%1v-324gavYvtb39g9lm7L_Rrh`ENSC)l76>)1{N82gx;C_If<_2-l
zi4yLw<Wwo;roRo$Gh7Y*yl1(~DJQ0k`@u?#;d$=Xt0-OIw#i{{q<YizxsE-Q<9CJI
z*#J_(b@>HImE0|ju<|NbL3d%Uac>yGeVv<L1BhyFegaB2xDP*oz)kK`-=VUWyNq&I
z>bTcv-mT}(q=QuhH<*+)a*ODk(!`b1v7?zgm5UDC=Dsu^y=vjka?mV(mwVs|NOW@z
z=RkV6VH7R6$L*jvOfMHH6?km9(M~Y!KDYB#lm@t;Wn(yoxD&w;ALf?rK-&n{N(=BK
zZZbKQN4ZVM&^E@^96{SSH<OO$6Wo2{C{1#=P(J7sxAqGP?Yi>5peM|YH*X#!+<CA6
zj*>TTGc8O$ykEaYr7urKkA@%5X8`j4ye(pwzmvC?VwC~BjlIwt$V(;9_%5D|^7})1
zwpT&IcwsMrGn{vu66GU!8Mh%2$@?5TET<@5<5~Jj<{sWcIzB}6TqtlF!&~_?U=n%J
z^h@vMO|1Y);=OPJdiU{0X|YY_&7<#jr|{O&+mgzAqYf(4cz!aFbe{D#x|YRjrU1%8
z-ZF|89pV*I1mZBSow7EL@IuLro6TDtNk{t}UQ!tZkMcH9DswLHi%EbU=dm9H$>+WI
zEXWC-dp6om@}6G>m;&B>O0_HGh5m@jA|B5JET?#_d!g_&&(sL8VqPRALzM7deFbf$
zJmwH8&-0Fv8~6fmC0(+;$lH|;(;Sz0eU#sPnKzTpSLM6_nvSmUZja#it>6hB2WTZP
z{{qmed3lsMaD%sjJV!Tq|Isn+7VnQ4=x+@#wgaHGyt;Z=SjU@o8RGT47t5fcfwz_-
zVl6xo9mraFf>Qu%<2CyL?2d!?%Q?_?-t~<j9lS-iU_~eIRX#`;ue=>9?(+I5p5Mo_
zP-Q>wT?$#==WUONrUBl!<b)gKt$hHqhj{B~Bm00S`5BxKc^!*EhIy`Z|6-J<djh2~
zUO*;n8s}xuS7;`9j<-Gn+9a>$P4G<diYTJy%1<K4q#M72womT-`_F>KgMWq#Y)}3m
z1(Ch@JCeZS&p$w4H`>XcMt8vi_zUSE8OYBf=ix5?e?3qb#1EhuFPPsP0DD9DqjeaI
z-F)jO&=<*PI`%^_itj;F)*k+|sX&Y7r$s{|hF|Oo^|AcfG+D&)|Dt_=Jl}(Et0wTD
z{~EnW=1b_&OW|kGqnFCxO^;q0|6|HMN#}2Gf_Mi1RXIo|Uw;EA`}s@QAP4xeCV(B`
zKax9OMmGN`@_*&<cXpxnDF34xVCVAh4MS5NKj<w;9OFCl0CSw5;tTA2ejvH)3;09n
z5HI9s+(oH~|1)i%Pw}_6LEtpMJ_h2&e1<o`O8EQedR;01;p-r0_}oHt_bmUjcPO>6
zj9);`v~&D-;A(cd%>Pplm~uX&8ZcM*p=B7L3jT+DXsYC|z6ecK{J9ilyvq0DLB%zG
z>@k4e;xF<BXbnHz3oNz#GV)f`@jWHrtmnV{BfuK?-S^Sf$oHZxSrh+jL_Qo&ZTz4x
zVBg_a+fdui?@6EskstRCNGJcB!vO8#KcH)Fclqy^K)##*`_CZ#e4m5(Dev=l(z8Cm
z|8f9ikpC2g5Qg|Wnb7-yKgS(bJmfE+jl(ei98DXe{BtyCkMXPC2XTz^`zBC3!4D(v
z-6Vg(evH=?|9Kv4@)3OG2^GGAhv|^_6DTM!;4cWZfb0~kzX|yO!FB~$0tGpgp0Z2u
zVGTHg1c8ab3>Ku&2M$66NtEriTd*z!(4m5r*)T0kFivlAxI<u%227;j8CqVW1W)`4
zm_33G-mp7bkVD7*7{N#XfW!&9D8V>h@F%6NB?x|X0_R>qD18+sNw7)^(0u|i`Dl{`
zm2|l`MNmh{`{{zEF9JG4P~3{POu;<bW$qWeq6Ovwfuo*2=9neOr2X1K!RswRJ0vL6
zLGZBPK271-f;qHJ%n?XzAV&qCP#!_9U>f;1@&w__K#mFC>_#W@1>r)loDl5PK>Vb@
z`)@!O2u{*1=0d^wuQ3Qkf;(Sfm`@2T=V8-n!G1?I8jA&!bkVFtQ0amvuvCymcMr}8
ziYOQBtl%0w&t-ycnzqgfJ}rabd4Z7psTTzM=s0^(&_k~HOM<#uuv`}GqiY7`g02r>
z{T0D0w8N<ojF2zAQt%G_OxFY*6q33w2+pQFglfTJav<Fh<k1s+Q?Q-FPqzfuXQ3Ch
z0;fE*)d}ov=xDuQ#xO{OVD(FoYZM6I0%;P&ssMUh(Cr5C7D3%ou(S&N8&J9<_%{$>
z?E)di-Z}&?$HJISL3T5sy9B`*<XXEch}?x<bPE=K2%dWa<4iR63L>tdGkt>PG;Q?@
z*3-OkA43Y3K|vYqj)w%r&w)G;RD^)#p&)-Q6b=iPdq8|dQ2!hTVNCGkLdcB^KA?Tt
zguweU$fO{TjxAGyR#!UOy9x!%QFIf|_k^YH!ha~*<{@mSD50nDLt62?gxW~7c?;hy
zMVpWC0DU3HSLl=tv;Bl#<TdmchLb;ar!at4+5jPMHAW^-xakh$b_w0cyAvd|QAjyh
zsHDWZ5TVm55XWv|y96+y!mU;q946dZ3l-tQdvxxP5DvrxG*WovB~(TU^Zp+}6#jV+
z*wMln`5-aEk{RHP6)qt^P@M4PFG1pkR)5GP2$xWbZKCk%hZvH*!cc!`ND{t7ak+iM
z#k49VJA}W`!<r)eZ9Oba6<!(xTAJ|STCipcGv`8nzwkLarX3Kn{s4BCux=-?4+?we
zbbCnnA_ZO!3z_TDnIpm$FQ8-#x6$q{M_4=pxue3SAHbO_+|r4*JmE2lgdY<MDPixp
z(9uI%zI<VX3d43n$Y=!GN#QG>La;!1>o#Btg)ePITanO({FA4I)99RZTKF%1Jf~t|
z_Xn`PM0k-BHA;oPl)-jJSV;bcv%)`jqf{o;?S|Yr;YPYQd|uc-A68rt#?$8RqR{4`
zsq~UiPq{jmg$v#RPr0yQ5!6=-kG>C5C2V~c=3f=AdI~JpgnqL@t_zQ?2WPc#%Sn(M
z!iR}KxhWi@-|m+1PYPtz2$LsaMXm6+XYt$D34f&ULcLJ-0t6a_hiS@h6wa%me4HlX
zHw)33X5sW0NZb}a{x#%VgdZCq(JH*5Mi1MB*%7e&j?m49%66gKG;nqZ59gxouJFfP
zl)8l}lqAz5Y<?3g_k`(x0<%~6xi?Jf7cQmk#(m+k5g0Qdd}%vMgF?eFIU$CGO|8Iw
zAiVrBV1|Y6-H;y<o*jk!BVq3y48o}Jl@73s37=8I?s1{z6|hVScLbtsN?1g0WLMFr
z{vht69pvut5Pka<N}i(kXe#p(eHj8yZ_#4%7W#_pCqeu~Zb#`Wnf{`k<Vx8oI!23X
zfXMV2NT6tICgg)eJPI%ei++6@3PVJ_vrxHPWT2fvsAxAmUSXnmHhLH#I!?Z#NYS2Y
zXp0i%aL|`n(MAfP$BAV036*$}|6Z7uAj(<+k|?U6TNREZQ6-&q_lf?h19q~g{w&Z^
zM9#FKN)`2AMrE34l5#%NMYqU%mnm98Yw~{4jy%8|5Q&B$o+V-qp%Vv1RnZVXEQ)vn
z;zvZ04<VN=5}~6`IifMj$37~O2+*Zm(MTfX@*E<UH4w}fMbpXoglO7tu=}JanH;eN
zqM#)ZEEE|i5^+lO#%grtwCL1)kYW*we%}(&F!?-7Ma|@GJR|Zvj<zz<T6$B@iT<Ux
z_`FDygVF`j0t(_@6lKnbzDpv$9OC7ow_547xFQOWqF5p7ph>7o6tEIJS4AGfu=JWp
z80pG`yKqxBdVfolP7&f7(X*`}wW54F@zseI(Qwy`exUTFMiKuKz?wwgs?pXg@})KP
zwrCB_y)B{-D3PpHlr#?LJEE^=L!e#s{UU&Mh$_kZ)-7Ux3Ar9ocOT^LiT2a}u~+nu
zV<sf}L~oN{=e{T{A7}%jKjxt{DEgTJG9+sF8!!(<$4w|b6s6K$ZCKPvmr)*x*1n0J
zjfxuHg=u4=l-EGUMf2#c#Ds`XS1zVRtd&scD*lQRvE9V^AHfQD@wpdK@(|Yq(z4(w
zzPk}7dWkpgMx(Fz-8iW56JOp99)GcooCrI`AFl)n5PQ%eI8dC|4VGQv7K#}JiG!X(
zCxXRWC^{b^K2ZVFc8izOR2V9Lo|0U`#LcDP3>Po{2c-z{6rErq#h>=jn;Ip4t_gbg
zh#Ox;ZM3+U@>pZUSuaCjta!#bl;Xrs>d~ioaqI%9NDwn9zMUxkhO#gAiXW%!`6Th^
zDyY~ezJ4AgS-h+q-A)m|O<S&1@dZj`NfUoD9~#od1$+o(h`X0e!<(8Zevbm<`^Dvy
zpmjhzLD?Hw;<>aXKPZl%&BGz_ItpGN7ALns@QB!TEd;W~3u#}IBYyRBa2^$Bk&o(_
zSQ!F=<6@7W!I>|f`v_JPh!;_Cq)_~n8S0C~)7w!h7JpNMv2c`#*_3=$D&95#yUWCH
z(6f3@ynzlK=f&+wkhmoFquU^t#f__>qFj80wz!qzjt^0)5}y@7{HplJgBY1=ab^lo
zZiru@RpqAGZ7sxW#mneCQYY5Z2W#rZm9!yg60;6MyxAf4ARo$Y@f-@+wuspjziAb7
z={iT7IF7b;cf|gbg3>NN^ai@tA@-sy%}%kNzA4ZpKAa7fZt<@a<meHnypPg7G4jmt
zbc^5N0jy8FkQRyi;wl;B2E<QK2lSx0c?K|t#10oa13VB<b-|j4;{9SY4vW|P1hf(H
zPwP?nNW7K&L8IcwjZioywp<42xVW31^$D>o2%wYVhnK-QCBCjfo2x`@fqFN|s~-c*
zUE+2FEMAh>U?}vKtfRxPk7PP+{Cp+l4$4>blYFE^(O;t0fpw=O{RmhCBo+(Mc1e!V
zwk$~EPMfV@Ni`dqLL{f?R^x7o8@<M%l8uxe7A84)9wb~cL@#`l<Y)`p_DJrV(3faQ
zZZ!nrBu~=%6EDf9jN$}INeZo$iIQ!hXxuCLlpd3PlJ$?EK3S4Z8S5#MW82Y|Dw+K`
z+R`NFeu5S0lFiX5Wk?>bKo2t|N63G?Uy?*~_5sPFRtV%u+G$?Sll;9MZO0@sHY$%x
z&QJ&-UlR2_P)<mG<<U;{q{Q$nG!;k=YEWA!xjGZ2BFU+6V4sp~WrLiSJVoh)#gYT$
zw<(e2Ou+0?$;ULko{>~N4bZcaKYgLTOtPE_mUEJo^B{L#@(gVWE=YcFgE1E+`4qUk
zB$3~PhRc$;etQ4PCBOcH+AETKly_7i@k|73rDP6$EVD{7lU~ZJ5+BO#tCsK=LemXN
zJxx$IC8Azb)=GBKWKt*j(FX$c5@8`K8zf&-c&<@0N_j_3l5gn(MvEkuQn6YkAJ4=1
zwn=7FYOdpsWWyj>+a>XPAm1U`L}Sq@vCIHym!#?p$X&^w%b~YhQc15<kL1}fsJ|zP
z{0M{4E8$aAvQM(Q0Vw^F>Yu=QU&6ZxG9Vcv%t6V_e^45dEItgD2a-coFy^78X+PSA
z9g@WqRveLJ(9Zsm#EBxyqY`-!$e3gyr3{QqzPCfggd~8%N0X8xZ=r`%lK&{Z#Z?+0
z28)~Yb_L9Km+Itb^N_aFka$Wr-hx6eX%W3@-qJTNL9dUr{zp{$O4I1w@{>BMC^gt$
z8deV#JEcDbqBcMpN_PMPrQgwxW|ve!r;QM)l^n;rrEK~nLa1~v-K7bWenIE@aH%_m
z$0MXK%7Gmz<=%r_l=Ko!JA0%*8$hC^FHb-&M*4I#?2VPCQeIb_^ee{~5R8|eO@#Uc
z=_i!0ktlr>4}<qgf1<!blJuD%sNW~;C<SM-bkQCtOp&T6?;%Zk#0xg1OS@^#&yY4>
z1WTs0n(o=`m;R>37-mVYOrh<dw4xXShosqbTF;iIQ(j4q^hhz8cvO0YF5>1&6RarZ
zNm~?9cucy5Vra*u7keO>FBK^OdP2&jY}k|1Hv|wUkbcDlXQ9-evaX7xqFLZPC7nZl
z_S4e(YN#)kUXDd&iS)B6=q;6QrFZj;^kNh`cvc!%NI~E-=}T^CJSY8%mi_b6H|XSb
zK^kxbtQVz!Xux_&I<XJNT$YCBfTdh|sT3-%NY{lxZ-w*{ovJFO0=hj`CDk-S;Hos6
zHrUss&y$1xy3|sGwrc6wAe3%N)5*nBBhCMo-1W86UNO2>C(SKHZN1d{5J-bGp4@DW
z(m6DtH%Ye$0op8mllCXKr3*(O&?2p-eNmg#F%v^_M|zq9+wIcaWVH24^NK+Fr2kQb
zs$V)m-jw^&p+b}fq<7{5Y*6}53RoON(iZZMJ&^9Bbe@OOnlC_xr7e%3_mT7r-DMk<
zUit%i$E54?P&qEWM<=HV>96EAnv_n`Ma?N`EA129WSwur7<bv$l|b>3Jwx}ry=5hL
zpvgz}72WXimHE}9<R=T8g_6HR_Tv`NoickJYzvUpypB?!ERCL)U9vR#DS~7#l0!U1
zX0bs1ZrQC^u!PDOmFPv7Y=9zT;j)8S&=esv9Ro_FZ1`QM*dyCcF~4Y;gdX4+*&Fqc
zi<MoVr6x|+Nv^B}nPV=cq9n>L(~&Dl=0Y2>eX=gvh$YLuE=OCM?Dm(CPnUI*e1^=2
zyc5~7cN3r~M|L#?az|zBXTyqISro05d9shDP<c%DI?bymWFJtd;G`^jEsQCU&7K9h
zLfIQNP+uf_%|Y>_Q?lcHV4s#fwGIl4WnSd8E|Hn&YD%e0wFweuWIJl1_pEIC90;6~
z6+Quh^RmTHg7boG1$nYB$~>3Bic7MhcyL~kU8VRzg^We3VWsROdElyKg<k^fs%#4-
zDqWK$aVcDOUDiOWM77Lq4Fqq<ipdjqQ}!*bjkjb6Xp34SbK3_}D;uZiWSwl*BFNXv
zPTYcp4YJVlkZY7heE`xVn?uKwX4#)HXuB<&Lx+tPS#T=)+ba8%wu)`C;AV*5k)4mC
z@7cD?Hqx24L$>HSV0X$EyaApr*`E|PzAGz#3Z`|-L^N;o$b3stx+i;Y8`^qhD_c<6
zCwu1*NWZMX3F`05dQJdkKo(36xj~t{1Db|p4U~WIKz8{qSRTsWE<xL{Y?U)z0v(af
z3qtXc?9)E*jLLGkKpT_U<oGGZWmdX=G9k<Jg5ab~PsfBQSqOb3$yL7b7~0(Bt>m}y
zl5bd#HgCCter6x}Lvp+N%Dd=8SAO!S9RTx}2hjDAo$~NX2n5JKy9Co5f$~eWP`^w5
z@ou06$>sEMnqaxwgvJp0=l?&N%A3R}h05*Za*UDxK|fQhe2Nl`<K!XVp)FqSbqL}K
za$7Je6Xk*HFbI3)8T3mg$^V_esO^(`-9RZ>o?QxKQsmQUvy<wOAE4JiO<qmm!F2fu
zrBP(a12%&vQ+|v-a<N~2m^Ru6<TY7n%aYgs3kwg*t0`~jkbEZH^FAz}pw;Dw{A3a|
zWy|07LtBn~$0z97QF-fjSePsKph+`NuD=WMWAZQmgudf)$Mknl%$Mif1<VQgX7W#;
zl%J-=p#r%=3z$Orv^bC=dBh`NpORmvWTw;dW^#oU%V*HHj7#KmC|*)3zeeYSGjb^x
zENA5_!(daHd}=v3&&$h^KkIZsE~BUGqWtz!sJ$fr+c6uOF3Vs43=-w?KfZ;;6}e$P
z&?@A=P-;e{{9}qtSIPZoPkdEwqM+V2c{ANNyDpza{)n4$HT|i}EqPHOEUb~wCtq%@
zy!1Ap>*OCsfTdoZ+YBoj<R_Lvu2C)`k4KYyegw^4&2lAqt#8ZEKR|7Zyt4}?w#pNC
zLa<F<G=b6`xzZb;?ea%<fOg1T={rH4^2c_7rAscJ2ea?W7y1FLTh9C#Z9VdZKY-km
z|3^;PUisf2LA+1?Dmj1q<q~pJ-<L0z(tmaj$e(P4-a&aQy)r}cximpOklW}k%tLv{
zmmtIPto0Bak)Nim+atMv92leWn;SvK<gaXnrg3=<U4xvEzc~j2lky=GN>lRhs?g@D
z`21;@=AoEH$s?YM+lfH&QuG<0nD(`kui{He>+w_EjfJ4U;`1303{)&}2HB-p<PY<M
z6hZ63608s*ZP6)2@!K32vs+<}JgkEU;YWHoA`~w*U<@M_``<w+O40cR^zKp2?*oZe
z#8Ge{Mlqje_gKaBT!6(X7SkR+Uh&o_G$bfKC$C_lqGURt_bPlTW}BqwrKxP6!h=@2
zWCdp$NQ&ZLieaWIjHl6wG{sd1IY-hJ92XS#E4F?HD-I~mlJ7c8(M0pyVa0uV$c`us
zv=7Wy)X|41auoj*p>$M{wF#iPirceMnWu2fhoQ$5*)O8<xFR+fmHCPUbld5KV)iOP
zpHyU@17?B3e;G=JiWOVP*IuL;r$g*1MG&35PAj}A-dL>QE1<VT(MeH(QiY-&*k=^V
zIGBG{@p38J$`oElQF%@=lROCL6|S%03AmsL`5Iss6&9M7FDW`)K`twH&{&i!7SP0W
zMX@&(YO55JbLbl5RmHD7)Lv5@y8`vs74xP+zFHAQc@sAj;X0_OQK%!(i&}+>Lcev2
z>$xa(Den5hio1%_zd(JrVkWsydla6ue%({Nl7m6$RXj^uu0BPP9hLnGr$dmtuSod~
z8U_@bVYb6*P?1L2IYWxO<g9z3cq0%h9xAH$f^}H2^*YQSQEVc+A1T7<bTq0M{Q}ry
zirsWMcwA9UNktQir74heRZgc|KsTi_1A5(+sdO>MLwP$4m7dCc9}q94g1#{4tz4=C
zi^E5`nLPi#$}h;1=BGUI4od#YpfdDnr*h;rBm$I*J75h|&Up=JyOclDfh0(IkepA!
z%0zl&LX^iT*=4sflpdB)<%@ivgegUIo(Wf8u0Sb5nN4p>r1A#c?TAwTND+!X4&{<b
zz(gwtoS`B{*+fYbvC6f9D8(sXD@G|^`R+~#CMf@=i7`>Rn*q?hN*~(QB`J5&1GP{2
z4V`S0l_$1h)KZj!FEJLWN;@rMY0BToJCLs2Mn{(n<%)Lb%~VEA2lRgBTP@Qde?Yl|
zcIH{iBJ#}~R94Y^aY$M57(fpz&qYd1cvBxIU*A#XI~ReSt9*)bTl17QN}4>Te4_$#
z$Cba4k1$^ucN$<Pl+*TroK(I=cQXo<FVL>8Q0cb@Ju6Zkq>mb&QYI!s;IwjH7%GdE
zt3C#1i8A#skW%Fb4IpQf&2)G@t1NVcL2sFI^hto8Q$9(P^?BvK7{FXm*3y3LqH^ua
zkhr8A%ths8rH%%;T-i?^>`G-IIsU7ZYKqTXRr=ll*fnLwbO>BmhEbrRS~>nc`f@{=
zLK%WLl@I;V-CIhV59Df;HUH9Wj#}k%3ZvI4Q?pQ8uY7+s&>EDLzhh(@mB+qE+im6N
z575@4JV}AkR^?-Jf!3y!QZVq2GIkEkZdb;Cf>M|Arv+fSt9;^Xh<7Vr@P-w=%Ae@;
z*r#kGUrxW$eJk1qm5&9}n>wVd$IT0;2g=`QdVZ)Bw87wE<zMf?(h=o?=TUm3jQ<bV
zqspERm^P;DrJeP-avr6VPAG%tz_dxFH3b4wN)x47xvD-`3%zctPrrm|?y3&jU3sX?
zS*Y|>*?zze<D)8UoQXHpSGE2q1pQQ-XbKKcmG;4kKvgn@G<T`GHb6c|6+y`Z!K(Wi
zFeXH`m{N##t8NrQQ>f~DI#7hEPCpN0!d0(vAs(T+OS`g2RWdy~QL0}Sp>2<fe+!t=
zs&(}!#i;f!g-woF)vWu#j#H(dLv5n!n?Impud0+L%_LQ(9M~x;FM8HfRaz&IG?nNn
zw56-&*<o6S>dnVd%2X9m#_E36Bl^I|0hQMlXv$KJxS~r3RiCz_?T~68xeN}ge)tV6
zM^u|vLs7Ov<r#z89F>%2pQEbR=rUKX>iz=Ql&5+z9VX_hL>JI@LUs2C^!KDHjm~H#
zs&(I^Yo)4Eas-@Fb?<`}XI0CbP+6v0L?Nqls-Y^#omZ7epzwk!W(DLfs-`c8F_%<z
zG_PJ(Iih;dSgxAs4RS@bUIbF1+WRjwRjQgkg8C}eW7)vIs!B}&xu()m4&x0~Cgu6w
zRNbuu%q>;g2~^go7E!pQR&|H6cIs3Ol_2%1Qp%}qQ00>MwNdpIrTgAiB~*g6s17)2
zC)BFi{~uV}RKrVP@Ez6b6gg{GZKiaC4%K5cK%J^RDJXTRa%X_EN41GAdfijKz6Bla
zRqdp>L!YX@0-E|&w_bz5eN`<Bl>@463Ya#i+ISHPhg2Wa7I9d$p8O^wD$|Fw*LtK1
zq1kIxb%^qe$5cO3dh@u-kq`L^Rn<w5N!7J&&^x6{*#b^?wW9)Z9_q5q(B!FZp)1us
zYM~NszG~@AaQdm2QSN1c`iX}yG*Eqzf{(k@Vh&0n>K|ND+O58MhqAIl)!Qk)8lm3y
z7#bthE9l!PQEJU@$j7L2=pYlT{%j6Ri&K9}DIdvdB_9GQ>hU&|Qq@^GD5a^(UBHsA
zzI6!pW~j5e0hXzD(ZHttNRNcV1M1gKqB2W;nU1mt)t#SFRP2y?(W~G&tS<csJV(^Q
z(dd1)TGI*jIci2J)E`x^Apdf%`uHah%u`QTP&%geTMmWC)wUB*pRX1NqwRz`od<!F
z>QM<W3)Isod{C$^cohOg>UqAf_mp}yk<;qgZ$rRQto|_`2A8T&??v&9`sNTM&Z^fw
z4lBykA3Y75&Z)nq>GHgKjyEbVs8<d`{-XL{gbJK4skgb|xwx$MAh%w*`W-KbUs3nH
z0@Etgk#C@~QoY<2&{gVBw?h1?+M$NPHTCKvK)LQv&!FS(O*O9ywYSvQ_JFlUZTt@g
z*Q+zvK}Cc5J#xe~s*j6Md0Q=|-E)h21*I&us&8CCsZAa5F-mvTd4WJ_SND^Lrc1qp
z;_i3Vd^(ADtB1)+(5wEMocew0rzq*aU+w6VqVc}^UKnf}P<Jha{Gj@YJ*a%BUPSZq
zu=@N$kP&qXxhluh>uKLQuJ(BooD=Hf<1o!tvyS@Yrg`)`+T1nM&Z0|Rnt;bp>8+W)
z8qhwP<rMJt)hwn-(@*nQ3RwI#ryaqdA(}S_(70RkDY<q+HM=f=Crnd88HnMUAbPAL
zG@sK>H&P>C4D+Kj@6!jY_h|m?2WPbANfL<B?3jbWi`Bfg52ZLwrw@#Y*ZlMu<PtQu
z$W5H6S@{Qy*{gY$62Fr)dkV;(uun6We*0w2@8s`E(R@Z}QK_1DK8K1l&A-)XOV_L?
z2V#b1<(p{B)Yx{yiv5~bYN6?XX4P~Unx%RBacDZI$vBS6Lz<4cfIh5Qv;;$WM3YX*
z-PxKf720w%u3;!0)qMLZ`TBA-i)O=`JWa)QfF9HQcM@pFHH(6Qmamzg3@c7(HpD>v
zNzH>}s4UQwmP5W!(|-ckMVc$K!E#EIIsv)Un*OsuDb}brqq0QvGxe-gbIOX+8BLA`
zrL&rMPJ*ROGvP_=-#N`j+Jl_etZV|$1<m)x;JK(dz7Ca_G;6-a4|7?=-wnIVHPUXd
zT+v9#*<GP&qwK0m%|r4yUehE{Naecb-a%kjYj&Lg$}P>0J5gDqd6)7cYBhUWV0MG%
z*>`}_s2Ny_E;*VsCJAa=G}~qYtyQDZKyRC7_9ZCn&@7~LZl~sP3OICW#_42xSL415
zEZv$!3PAU0qUqhfr#bgJSb8;lIw<yOMiv6QU&Ep&;l3vG1^g5Pn$PD!Zb<WK7t}w{
zRMC9#(4jg0EA$R)de=aHM00xy6h6{yTmp$vO)({MjA_=qgtl=_*Dt7?(6~{O@TA5+
z2%4rea`JDvYJbZ{o16C4UR1hk8#Y6ehjvCGh^JOj0V}+;E`ezC*7_s8!pTRQPv;<C
zt)q_8R{gYZb776Yb{hlOJGJ&=R0e2Y;6Qz#cFA;*UD|gAFfB;?Q5*z=wbj3ZGerBr
zUR3VZZd!>_sCIZUIK#Bj3sD)amDiyZp?!n=o{`!rigiV4?P)M(kM@Ztz!I$ub-V!+
zW3)T+pgvan)n4e0(+*vMrSV!eUCK((^670()GnsT^<J&W18qs#KYjw}KCSshkYsK9
zRbZ!RmwW^4RPE1sAZc1VnU=17mgcDp?ObvkW@=5e?C;k`(R^`0J4faK&C*Vt1@=Mh
zUo=x3(!M<kV-9P@loWkL8$kJP+1l=3fR>~EYziz#wO^0}KUcdY93)TsHu)NkY1?jM
z5RPl_oPwr&?f7?qKB1j)8<i)u8<SC4pv`;@r9$mD6gw@_e!A-a|8=7Mj5f8WwULvs
zyI8wF0H7t>G0I;l)goaFZ;o~YO`d19?o%+WOzWlqIj2>S^Z2}WJr|~3(5_wzfs5J>
zIvHQm{y^^h%i6Id$dzl4&}w!?yC4+M6<Ps(KKQCO6!+&HPS>>h_fWj9Ev*Mnwf5x>
z$luT=Qil9Z?ee!^_bqMkHelCi-=ieqT5ZrewAE=3?}XlZ?UDpo*r0uaG9enZ#ZN(?
zN&8F=ENs>WZh_ow?KL<soLaQGPeVhimdk;7oAwa7i5+*e|I+f?u1#=*V2AcQAxfQE
z#x_WFX@8~7^j+<98=#_Fd*p8j_GnX+py{5LvlcA9+84hCOCJd2`n9vj)qh|6?q*aD
zXuqQ?aD!SFEx1G4S7|YRpj}RT%ZFMi`QwHi+MZcx9MQf<CyGZ}uSUp^YF}~z>zKBm
z7K?H1Eea%0XdU!r*GX;DCbUgy8|#4Ws=LlarJL^lI&{rbH|dHtFWujKRC?>aZw2wu
z>6f6=S2soq{dAXEkn`7Fd=K{S)H$9Y2S|YKzbMoO>Q2$yyh~^K7-&JdV=br*)@>y3
zZHVq6J?p!5D=E)4ROd`ipfKIv7L0Sa&QOLvMd%*TsurnpW`QM2cbR-{dvu<kLPNBU
zJBm__ZiJToSlt@R--^@qJAQ;<ye`EEi3Ht@WT;5g{jeGe_v&0ID=SGCPxAY8K_A1k
zWSyCUt|_`dUPfE0F0~uKVVZ75HBi!Z8cHV1(0NyZGgG&34UE~Z>!Xh*9MFy7VROpT
z`LZBzQ0GZUo<q9&bq-i_SZ6y3o*dnibYJGE?f|)&b9HAMQOeT=k=@61oo=x3xNdPO
zVDfb?PeR~?uJcKhPU_zN3upzpx4(lxq3$R-uZnaonHZU3-L_R=Dba1AYdWPm&k5L6
zrfY77hI6`#!*n&}ysm&A`AfPtharDiS4U31a$Peex>f3)SEH>;S3|ixS9M!o0;$!>
z<*2OFJ(~=HdY#W9pf%_$bZ?|l=O9-{lP+-$y#Ts7zrfJjx|pv~YSC$ESJ<lCLuc?d
z-8iDk4yQXh137rxb&q5q9lF>P;OW$P(1ph?-CK0vysMj6gtl&-JAJmNN0(az`Fpxg
zDa)c)*F<sIJ{`Xo>ic!S(Gz%IS4Vvr&}}`B%0b=S*MTymyL=v;4|Fq{QTb4}K@Jqh
zux=@BamRG=G|P|cMvK5Rp-U#`)uiqbWgSfEVvj(=RX<}pK;86FMQC%^3qxR&w_Zuh
zk&piOrI7R0Py7Evu79Qyoc{U@nrL?FUz-N?0s22zLoQHn`3{vq`ky`l33lik@1ZtC
zFF%FfcelPh6)>Ut7-z_b>D9;37Owv#5}G3PRi$8w)USRWZBhE(Z$P5;H#xwL(Vt0!
zg|Yh3!vKxb-!Fkp@p|W43{axpV>ZP1>KD@KCP^Pj?!;uhYbtt{qIX<q1Wnb~^8u5t
zPxJyzhMwbzp~=)ck%M@@zQzwQ2lN*^P&%Z)M%#wN`qS+|JEDJyrpavmNd+o%^rxg?
zIjR@XtCFj~aR8Wk`c19iJf?rL52X|O$Li6+llteH!C9b>aLfT~p}y*CkRrVy1GT60
zLOOMy)*pT!y(rdSq;qSD-kDtIrTP;;pzVy_cpEmI)$jiu0%iJ>wBDc7Kl=&V&g-38
zA#g#TLV>f3`p>Bom-OeC1MG@^;W(_Q&_`r~RO-tYI8a-qpQnQSRs9F#9l568Lw>#M
z`nIE}tkzekAb&&u%5qqEQ$N2N<d!~R12}8+2lCKXryr)JxnBSBNstEpQ#O!BeI&&|
zoAe*-2TQYlTN6sR^<}i{Z_$_Eg!QfZl^&Gq(WZZu15J1I-gi;kuKzO^JRSO&WC(WZ
zt&2gr^pga7SI;HSW4HcCN-pWqkH@0zo_+(x{d)Co0kEl0zmi<$1Nz6Wfeh-mQzGw>
zesd7i59<Tz&_1FUTtg=w=~pbG_it2xFBiozea36x8P{K-4?;}omu?5Pt3mu3+T09Z
z%*2p-7zWm(($f%@h|%*h{7uGq8|?I4`4~nvqvUH)P$1aP(0&^z{)SI%5ZGy$L+en0
zA&@qQfrd>^zzjCLN#00Dh~XsVi|;n%ZUPB4{5u3I!VE9$MJe3SuLn$oVIxH-BMmD$
zpef4m8{PTaV~C;2B--!^&C)T3)ox&kH9WY6v4}HF(k1A4!>}{N6AVp5=ysx^<OvAu
zH5e)HCCR|1V8Xu0%O2C8bo_S_!s&+Rnjw{8NTMKVrs0+swCy(x7DM=eVLADCvJ54s
zQF+iHT?XMphU##T!-n57!E(f)I0d<E!=`3{<rrMNq3x()vKl1U5J8TaJcDIFSdJO~
zqNDF|LnhsR&o>wx4UjltsN4n>Ck+#m7^MP34!LIw4R?M=Tam#j9D=6|@y~*sHtatP
zg~f)0EOfoZkU(L&QiB(rV$K-;Q9$mjp_`5oWrn9Du=kwd3rbZuZ|MC13NIKE=|aOr
zgU2<HO9mIF1FV+~>*~Q;Zg_`WIadtfbV92zgyw@(8cxxyT4mTz6UtS?`aW=8Gx*S?
zeBDq=lTEeZ(ep6ohN1HeI(pNvpa7*?hSL;7s4@KW2}-pF9T{3@ctla)dP67eWE%{x
zETWg7(a>Cr+9t!Uf1#q;pdc6DZNoasN@_9u_7Ih=hTdjWwj17}15bzHvFFj&X;?*R
zTU~~2Y_QxlRKJS0Zo@kI(RvL2Z=t{U3=b%F(QDvbML+utW#2$izoEo{F5Nfe;D(yR
zX~3|P61)Zt4R|M<h71qp!{A|q-}7J{G0ba2+atpP@<)vt+UQ_7W>`w+(s4sGB~?rq
zPE%saq@j2zIHwGoC|2oeoJnyfH{%v^thgHw9R!Pq@xCWYp2ii&A?IVvcn6gZUt?_y
zB>areQ-A%9t-GLNr*Rh#JORdMeuou-#x1l{+GTw5E0lta)%4xKVB=$4*c4*?hf=?H
z8@2T0h8jB-042=$?{%<*8{d+GCBpd6W6%(3v@5|GW$d_uwmrtcHy{x0FxFANNQ^Q2
zStyJ({y;m#IHUO`3|qYMg*iamYb@W7wj|^F6%gEKTtH~a#(&Ddl4AUcK6{pGObCL7
zX~vnf^-edgVgNJ4*!TiiGL2D(A-><3%0uM=<6W9TvW$zk;5=w_gp!Zou(8FC;t?aC
z4wl)*M%vot7^4)xK5F!*%-3Aw-?U-MGxl5sIcEIM0?^||={Qv68`l=YrW3}-O(+!_
z7xlo<B4f^FRGu>a?1fT^v4{^+YTQPCtTV>XX~%KanCxhSiZbI_+UuV)uB88FIB#4P
z4syZxJ0Bx-(KzEQG+i>*QQYdXF^e1><;IqmfOf?=N)LI3@q2nMDvg2^2viy6l&gBx
zc<eW*zh+#z2GG}yOJ<|3+BlEShc}FtM1b8ie%VTk&@E%n0yNebr!T??)fz7>hKf34
z&{}k+-uTOWU^f`wqv%_s(R&^2Z8H8#;l*a-Gkei?+gLz;p%&v}+B&xy*EXT8%~<LN
za>uxIJJfd=L;rwWr!feA2d6IMD6K4ajazQhA*|cjDhE%GvGXo!?-_&70jAg3^E`~{
zGwyIfWxp|K9t7_jpQmmQ7)Qw`IB0Z5#)Q+5F_Fjv;{h$Kc!)~$W!T7~j~|X0nIkAY
zG79L>IcoI329z;lc^@#xjXD)MAt#K?Pz=<hQAp3_lrf44OI=Nkfv9vdJ>d;jcaw#F
z5f77+mS9iQQQGo*nWo*xka(LUm1y%ZZQlgqYYNMTCO^}2u_*bQRCB?y({!~RB)}9x
z*DnK2E69nl%e3)0SR6s7L-areoBpCGO^7LqK03AABqwKYsA)FE+rmt&WPpa7s{GN>
z2-CLhsEjm)9)v)Y$#f0adrY38=zX-wPA=mZlS?f65^IX5r7+I)0p*Uxn;xgoR)Wdu
z3C={*d~#Lqb(jvh;&)0ixzVkKeI~Xuc#=(5tRN|-N5degro}B_O)~}1y{2@N{3n2B
znAV#ClWCewyP^Fi)>Tv<Fh$ZbnPs~76)+E)4(LD*naYNMa@e%Z18ql4#wd(owkd&P
ztT`sfufxDTYI;ChtYfAOTFH-_{u~B&zA4uoZ6{3I$ggzLRCWgv1*YB?(3wJ0Nk2MT
zWV-$_Do>fp=}>dpluu59VpHi37*k>re1cM`X(nwm&zPR1o$OiDdz3g-W;z%H@pGmV
zj(355-W2SK;sukK0tFXMJ>;;sWNKOtn=YF&!a>SSB07*>F=db^x5D%#1?DSFV{|B~
zGEJjj>#Au^DHL8aRePZAx+#y=k!sU8B{$qKaVdH0rs=H<(09u;g!R{{#*`3Db4snL
zJO+bUXPW&Gwe_Z16g+P*ttBfOO*J<`noP-JSlDdZL$QS0Ce>CL+G2Wv?xwVw9@`Ai
zHq#jwl<t`F=$zJW8hQ(09j51e(AH_{T7y!T$%k@R?wS@J1WUK6aytb9dQ5L;qj=Ah
z83awerV{!SmOfMUMHt*~($SXSzA57>)DM_mn~mRR&@@PU*df#V-9UR_@}oHFL({Z2
zpbVRKvLG;GTKNK49+^TZ7&dD1ri&C~rn&797&qz3XFFjszE9!uNt2HcSf@;VmFSbJ
znVAGD+|1@*f#z<G-;Op9^Gezhc$!;j59?!2JpvYAvv4VhpV><Vd;QJX-mqe)IeQB%
z3@|^p0F^=J?<tom*gWrLw1t?z{2py#=CeP;rf@U!U0^yQ%>P!PHqxA;28lBNMR_WF
z%nG_G7HvMa0G)|33*Ut?vF7>nK;q1E2EZ9_ZrBEv1aqYvok=o#QFwo!dBhDY$!0+z
zRHT?&;!#R9FUf^5Y37_wV97Ka=@7Nw+`R-S2OQ>iKS$#sa|8{|VY8JE5J$}anSp)O
zJlO&HT=U|kK+7|qP6x{|^T<w&({XbFIeYWX34LHWVU8#7|4H)!O1mmBCy`5|(EJ!(
z=qobcqK|ByGSB=70ww0B$$?dBUU>%nJY$YryKDLjj_si+Tr!`bWAtTnu{-pXo8?X5
zzhZv-2Ba&@E^AR)X+A;IOqKZo9Y?R4xpXYNX0Fm>l&+f>a8X%pzF~mYn`XZa_^oc4
zf2Mt3jk$u>vRX3^vv|<W>Et7-H+Ky{uEBiEu>!?L^UWV1(PSQ{C}FcX(g~HV=G5<?
zzRi5*5_)vU{P<p2*lt$Q6W3vWiu?qf<{}YT?wU7H%%R)-Y8J$M%;weT(mnG`+E(<M
zk1J8xXRg@=)B4RDd@uy}%^!!LG+=&tDP=DWnn$m}nj!P-M3f$w{mkHbXs#u%(6Bl7
z1(Zh2O*udtHUI4l)5gq8@4()1a}TBJOqieEh000u%DFIY%AENN1Y9k97Q-eti~paf
zbhog#L)^o{4+HVE+@;;4m*u}F=_T~GsA=)_u{@-cg0E$m!mm3muIHgXz%q~0v;r;L
z{_m8s{7&)h5X=22=-qAEMaS<@%R0)V3A0pEs50E*r$;HuvS|t^dn~C9=xDShk=zt9
zmYe-BE!MIr4dQW@>2HuHGTt)u4<r&S4|I@7w0x2Qy?ZU2mY`2bmbnG6X`dzGbC6_<
z?-WRi<wLq!l4@D#1hh2Elk{bybj$j9bTq>v{s=uhU@2S*uq;b2oly>21}q?lEO8QG
z9=3GP0y$#&ybHu})UuU)Ou3ft$pw;U5rpCA%C}_DvUkF=p%ccOv<RPv!U9VaCASq?
zX0c#zk>wXXKu=jl--GyROF6|@iY>A%SW#kml5P{0TD}iK>5Sz%c^S`I)>F)_%#uKp
z>p9CaozQpQVYxRKDlS-dMnL|erHYL{U9$Z10F{?5-~R^ea*MMPXjd$4KLV}7vgIwH
zRazXa;H<LTq4UpGOXGEvu30L{fqKL83GKaaTK?%lUv62d$O%_t$+M%f*5c(0&N@r+
zE_ATo;>cYIi3ZDm<XmdBM4N!tWO1Y6Znkt?MCEPED>Qm7mcSbjY_<GMVc#~3g09ls
zu~gFB(QaA08k`*#CM9BaTH4Q{)MZI2M<?!DzM740cU#`-Mz?z`NMyvzVc8#yQm^Gd
zM-Eu~EH6F<Yx*spP^4(U!gfOApk+-hScfb-egw<|OKuLxL(7&D7&B~HM>j4;EK5Fy
zz#~gAy<=mR|4bm`7CY_xCM?SygTSQ4MzNJC3xmRBuGW{oM5UYc)a#J*u-0s+oH0-9
zoB}j@S)Dv#g}0Rz1ma^Iq!5q4_4`nic3NXB;0&-P(iSh!s!RsxE^9vzgAioBHVB2m
z)`>2(g;+;^MB8rbD7nN#tsAzXGR%7JO=t+W#$*CB!WwJ?W~8+xiVlHMRw?BY?y)X-
z34+nqfl72c#=84MNW@y-y8uh$tQ$VXFA{I9$pcBSPK7}}(c0w-oAz4Q@Bo@*l`n?)
zJ}b`yV9C~-KL91gx|A-jq*~uU3Y0YK#%z#utJ@e@GOUB|(MPH>t)Jz?#4PI%OM!OK
zy5>J%AF}36L+P+}YYa+9tnbh+J=^*h<&))F?{&b6JZo$VO2@3vkR#=|^?NJS=Ubif
zVay3@iyzdVw8qm;t-$*CSEwwsZmb4akv02YkW<#Lgs60!w%$&Mi6zz*lp|DX{fvCP
zXRP1m!qT%a29;&jZyjJgXC2xLa^CvV2T*^(8aWf>lJyS?EnT)+j)Sw@nnq5kE7k!%
z#4D`dH$$M(`WN-3%IaHy%BxoU>tMNN<&t;iy2E<&cND9wu0iO<4eR?|=*3N|n1Tkk
ztf6NxP&L-MKj5dRwQiaY`8uooFO=%7)<S?bSZB~tw$a+#4bo&?^$7iKwz9}KeA_xj
zX+SMj7bP^cS{;<~*>26EiM+$=On0a|t&VAQIsUHolaEpCw%($Y&mQX~4b<PWrsI_0
z)N8GxU#-tNdlMA)TNhHc|9xxFet-^GC%*>Eptbxnh!0u!`~mR?*3SPx9$ME@a@>e@
z)*u8PS#OqNU`MS>XMl6e`T+~Q9=G0btOn1dwfHK~rmVe`x94h`NxNP*+b9F3x!dw-
ze)Y6fH9+3WHV_9EZ`-T1;`!LvwAb;qZKCt7pKW^pIQ?x8{y}M{O-sI`09yn-tAVyv
zJ<z+$c9f>1AX_S(*Me=5ZzvKMVq?%7yW951SKtY?jg!MV%(k8`iiO*1XmN|Mv1!i{
zZTq7JB*r#EUbI+SLom#avq`<c5^r0-0pba^PYWTQX#1QT9(!$<!qJvwGmD{cpY8o(
zbScHQf?Q9jwy8fU>pso)$7xuRZrlGoSTk(f=_H(KyO0K${kF&GKHmY`jyHjpWn(%)
z{-AAr64W2IsU(m)VtaZnSh8(1UdA}**alaC^Qi6dF94Qni;M$Ho=vAg+cDeohfq3h
z6T1Q>-!=hvn#1XY?H5X^DzquS1W%D|^;wWpw!RXmKW*Dc7hH;M)!`5<v8|xvVySJJ
z74m0nn`uHnYpbOFVwtV*SLi)w%QK;C=WW%Wpmf2uN)G6Yw#45caLG1E32>Kf@6gt%
z+~!JOs&QPg`9DNsh3#wFAynEPrz3QgZH!JeS8aXekiTY&mx1-VZSzK8SKB&h9lK%s
zgswc?v|XhQ!Y!NTAF$Ne*7O3b)>gI*hSu2zmjkojwwn^p8*IH5fNr)uLsu4V+kX8I
zC@l`#yOjOZYRkKgQE#(-H-N@FHfM5Sw%Zo(z&Ll<4txXFPTL;`A>U<_z5>p>w!di8
z-EG@Kk4KN~%4Z<=Z0!H<xoqnwKda9sX$MNb?G9y?-nWI)2fGGrFHmS`(Ds-gz=mv&
zBhe6iVB1^|(1*6Mr@%98`-(a<Vhf}L;v-u#MOsH~m*^Jdn5~YE(BrllWnh`G9i|Av
zq^%$xl~cB2`udft{jcYM;$}bjA_Uy+t1-<wdDz3YqSDhYeGe>N_B#~E_qInk$g}Ea
z_oLXIzg<kr(oTC91C;^xYD#7bv>&Bsc9(tZ0SpeZ4-cX<!S?kzD23Shv|#SGKSP_#
zP`m08RD{_*E}=5q9ztQV2>bXmurSj8-XaWFls$6;D)-pm{}UwI-uDLWKV$6aB8+;h
zeU26+&i>Z7sEoJ&Nj}X4dm4qp678#&0ei3g4Edgt>|Yn4w9oG14bEiy%cU5L6#Jp+
zD5cszCM(kH&fmh&bo+d|2a#b<b^%J3{kR&XgZ9Q9KsjVTwuB;ahwc9y1nUvI?<#aO
z+y2b|vsLV$K8rpbwFlh;cCJ0;I!edvqh_c$ZV#wM5A*GRY=Ybg`%Ze}PTFm)z%H;K
z`Uw3kwD&BA!Xmqr6rQq+B0x^tZ;&sh*lwYWjuLz9zx1cXrS<}fAfB<mydI6`>>rjx
z@VxzpUt!Dz``r!Dd)Y3bcct9^!VYM<VjrNVyUM<+7@DryFTM+bYxb-iP;tY4m;-^E
z_Ai&9@|OKzI0S0!>ncEM?Ox@;tg~lyfu+g5gd&cPX8U;t&~Do|90h5yYsr_|YTqD6
zsm-pX&Ho+y0B!l&?eklqu)}`+Z;(#=if3R`m;LlXVBfW`c?T@r_P_EmvORXcyI{Fz
zZ=;NzUVE1vn)>Wzw1?=oJLsO*eLJ6WnFbtoAKFk2+MihpO+)sde+1eC`;a#TAKE$O
z?iscpq(k$FJ)gqzkL>OfAft9o0)FN(`#9~>$L(h*>tn*sDM96=-S>N-OxcfpkCLm)
z1jPj0Tqemy=<YI&_PZV~n<!Dq)5VdL0C^vm^`TJc>(cof1pQnd(w$6ymmmsx>~!J1
z2kZcsv=Iz&pi4N7#V(is+EE$g^2Y$sf?X!b%N*iT@-yUiyL?9R-cXk@S`@=vPLT5_
z+~peWIwD;9ogp6S@+~FKMY;GpXxG2TrHT%m(Jr2`D8;xKjo^uO*|P=;<6Ms9p)KBJ
z7A0FJ{EwyY0E_B+-uB+R3+%G6uzT;_T^6v!l46NQV>H&7#AqyOmYArC#;7sI7zHJX
zS*kRVBBBV0R8f&Gy{Uj8NR?s(M5-cIL`CI$=lA`e$H#Hz%)B$_>@DZanRB(<WPslj
zc8NEj5@Baby8w}PUuD8YlwH^tAklWqdf_R?Zlp7UiM2cMzfWA))#_k=+V1*Fw4JdN
zl|YHN%Xvea5NGX*_JU2YTi%DUNVFSs4lv1fpKXKt6uT$3fJwDmQ;yE0*=>k`$~n7j
z7vVS4u80H4vI|~-V6yF6nqZJ)$C-o6wd+{{%sjiSY6$b~a%rEpz;50{Ko{Dz(d}Pk
zmvDqCp^NRZ=|iX`cDss!cFAr9P0dT~9#Yn*%r4UvXqW9`qo7i5w_1;2D(qIqqZe1~
zc2iM9m0kR2Ak}s<dNS46ou_k1wRSU3L0D&JJOc67+npW;VS}A_9k@oj(mw&#WH$m=
zf<b!CF3TD0b-QJEG59y^j{XAGTXuF|z`oh;$$fyf*fsIsTJ02cSKYR&pNt6G?7pLI
z+dFozD-lzN-KSK;*lD+B2=R8=eL)o+-FDgUpc6fI&m^$BYgb97MfdF5Xo~v6?h6tc
zUfcD=L1)PBw-~s0wqK|PwwwLb`>^-0A6NwoZ~Jld>^^Ak`Ykk1*atSk#Tk3ID{!A=
zuR23NjJ<n4R5I<&Xg-!>zhDD8nr}ZP6PV}ibLf&Uw%`31gyr_*U4e4L{>}Gj>oM3n
zUqCcZ>}#pCV$i;%2tm2*38FQr`<`bf(dN6Sr3em#_q<OzzKA`tAqY?H84L%Pyyr2^
z=W_Nmzk=VQJxA0arF))Df{W@s^>j+Ee$O|*LdAD)z6Csl>|K5c;}o^`gXus?-fMWg
z71H#*kDAf#{JjrpT3EXG`%*Mk@Aae=#r3^^?}1AD-o^KT*1dOw7NI@bd;d4Mc)mA%
z66{{>{Y-{noE=tFprc+6ey$MuI2@-ZX@G+t)h8cz*i1E4Ar3(<FpqX9{0N$H4nYP9
zJjFZQYlmv0!+T_y;?VUU9G-IsqUTMzLr*&_G8~@KetxDy@F^JPIsBRkF5kh>j+hD^
z3{=W--l53_Z5JG7HiKMrnD{d~TI4Y2KZI87P^<$faTwJ~1LW`>9bqeTc-BLk5akYM
z|A9q?!_iM5z2Y!zJ7TJIaG?cUl|u&I@HGzG=_3ZU4z0*pNb4LTD35a0Vahs0*x;~|
zjtDn8d`G+0O%6ZxL*<&oVama_Ih0lcv%?|jFnx9!e=ah3^8<nz8HVuc4a}3{h^Ud7
zMpxQ3<`X({bAvfI7FM^IWHoeJm@G?hx0!qkMAE?&^APqipQoTh1I!9~CpfYj`anF{
zkL`dGz`93r|KFQ<Yzl&TYkLCN(GzyS)0oyI1UuG}W|`ws{-n;$;OT2tGhdHK^T$z>
zfj(>WX8b+7gAQxXxklTVb2lu;NX;vl2e|oDo&n;Mzq=t>@KZNzKmCGgxj&mm^Onzh
zEn&Oxavf~HFux9+MZcS)b@9?`u>Er61^jzS%0Udy(#PGj3A5~bn(8jErU~;`vxcKr
zU!SLiz&DyI{Qd3HbeMg&k&;U*Dn|lzWz<T5uDV9sNvree`SAVGS3p?vJ{3v);1CY|
zA3Zw|*4n2mG}l>DYJPpren@_b%Yc^+SLo@#aaR;Qe}2(e!eCRw0W|-*k*bI`uNjVi
zZ<$MbS^s`S<s5FztGlq+&%8yu=<ZAwU6LNm(`E=g8Sf1E^<q9h0cdY#?pQz^VE(4_
z6+X;g|N9aR(;Wo6Rwg0?kvw3^zl7aGCIF95R3b3n;o6W6GC4F+b7QxS2ieaC-y=`#
zgFFnT2OIhuTzIk`bY*(6lBa<2W~Z5uCw9ISg7IN5SHNK?%P&9_VeE=iASYR#o<ni0
zDb<vmVmH!D;55rG0oWPViVip!;@S7*Fg(jHi2-&3+nNf8iEM)xbduPR7GNi{M`((Z
z!k(gy<y7`=GyJBp?c>0uvnEtBk->KT1(i&;NdVY6ZY*WW(z*Y-sEw=M0nAJ;?J<JM
z;$%G#W^*U)pqXRfuF)bYmwShHaq_tLsT4JzQzgMg0q3v_FooPHDtS83JsAeW3tXWV
zFc&%7<uEAXqGy8?bDeawp@hqS8!DH$FJpjR%Kh(1c^MZp5nz|OVjl69bJm}LRB-+x
zFt2b1%SJe?<fhJrrz)<RHpZ$s`{l5&;TmYgUCS9pz@m;@L669*oP;)!>N)E&_-){J
zFNecMuJ;F!CT<dGUgNq7;qW?FPAA81aK%p0yvd!X&s5yv?tBgp&D;aZEVOW;21*3C
za`Qal={7go2lj2;UHWD2aDp*NJC{-qm<}$y7ZG-H_0{0IIQ$;~co=i~Z(!HMjiQ_O
zF87A+<9pnRpMcrRtzM6|`&`Ka*!6Lr--E#e&V))+9&!(9vG<5uJem?Kk2$@7fS+(D
ze~0ub=jMq>`?-}5VEBytXe8POxO22O@|?R74D1)&*R-$pl9N)=_#l^|28yGkcP)m}
zNfJnt&Lqj!e%K{TzS<4U6v>5faH*21^yW^JjJpk#bCQXTH2+VRjJXeKhGgbx_|23w
z2O`8O$@|BERxR0F2g4f4(;_&mm0YK6*iDI+3Keciyvm{3ArS*WIwkfh81zUwR?t{T
z-W~-zcj@pufcB8qQdO|0^aj-o9gx1e8UyPiedEpG{yQlBV;7?Fm3C0(I9$5zD_CSn
zU1<@NE!ABI$&rpZ0*hQ};zii!NvG4SFCYIg9b6Ph=Ouy^N>>)Z?|JE+T5uPo6UQOK
zBI#b5-xW)j(56+1RQDy!FG*b*(N-#5-3zydGW`Dt@OxQ0pYrw1MrWwoEk;%}r)o9Y
z9s+XPsQ7Kzw;7Ee0sA{f6KJ^Gjb75xh7O~P6Y1A7n*9_JJ~L{2gLsFGw$TF1(Rg+`
z%$<yH)*uRJ<KJl~%iGwWx^%$!TlyfHkHOewETTDRtXl~ee#Tl#2m2d;PX%KE#xo1S
z1sczw=iFiA9(o@K89$|5(GlaaC~zUhi?@M<8V^u5EzI~MdY?uaU#B{lG~-5k)}J$8
z_&Z3t@t5~8G8xA0sc@fVTug<UImQO*95m({XG}wEdB(=`5O==ucXWuUz_`>J+$CcL
z&BaQMAJdVuGGnDH3@#i0G84jb<7J(Ixnlg3e!@!Qx=%4Ojm9HX2)oI+ho-gHjK`EA
zrt8L|GvNNF@$z{vzh!)%rp3+1R)!w|(_)<C2khI%kMAP3Hsj4_A#683F&!`+#yjZ=
z(`7vU6fC-pJ&K`n*O;Rjf3NZ8FQ9qfct1@%`i$Gvh{D+<c^#rZYO?Dw?1D{7Dj_^(
z(&P*GAts9{H6Cj6H9alEOp1bO{e9fzr#Wa0H_2>+>IswY?V%H8!qx*j+GG?}UBsCD
zK)Lu>6O-34h%*WL1Hqg!Ng559(<YNTz@0G}q#gTslYL(R<($dG$%rD|B$SR1WSVr-
zJ1WcMULG*BP3qmDl4BByM<hnw#F1XW`6koi&{$yd+ZKQpnmp8Cpw645?S=57NeFGl
z6`3rj8B(#yFMk59#N^0Aw3V8SqPJ|BiPb}(TsGNC$K)$arl!Ef6_fLn`K>gG-T<!0
zgryTGcTI}UgX=XJeU!crdf#LgC6N0}@-BlsF!_*Pb&pKe7QyhbNq;F+pPH<shgiQ!
z4rP$unCzf;)R4(u+DCMh1+&m}l5NaIFwU}!vp{i?*_Z>xRmSZ_Xl}B2dg$(#t$%_x
zciBkFlzGS&Qstk)Pd2n3I{vbVd%!*<dvODXfwC4V;|Y>E{0qY)vQZ0Qm?)dH2cD8-
z@wCa3A{!~9EmhY0HPF&z4$k1t$+#OJ>9Ps*63>v$rC%gd7T1W8$&&q60L^UK`ui}?
zk&ULsQ?5bA=7HwPqUZo<zRZbMI0drY-(g=Ui+Tx*^D>rZ^%rFC=Fm?eOQMxzk*tmK
zXT`GHQ-EC}a|uD)CD~!h)t1VPm%^@0R<j<Omt|Y&dMuZfe+g0{8@>(hD`juhL8VG&
z5MQF()v|5Th_ps#Lp9*FvN-zKX`SqX3xro?K0H+GWtZs^Xpjxu25FM%zk}vASuU-S
zuggwS`M?d?+%}M#G8;d{drRhH1NY6cyl)U%i);*C39YiCRM_2?nbI<#O=fM_3+WwM
zo)LbFc3IM5kPcaRD;##pRL$_zC3B$(V7DxtCPY253(MicU;g_bLJN@hybXh6^1%{-
zhR8E$UKA?tr&GIO@`L>#;qqD20d_+E)@hhW%8#rAiIQ)Y!7f@pXhiwv7&*Te(v$Lw
zp93aN9zaLaPs!i<1?03``ZGY|<vY#LmLOlh322G(Ep(VRTRuP)C^_<_ZzHBWc^6$!
z`SMqrfLS6xRS(Q6`8k?MRm&ICg1ttb{J)fuywwzKb@F#?DF1v_{y{v@>g5^97?TG1
z`4V)yQSKcHzfJP-1yF61hg<`>BOgN(z;^kqdEh$aySKn$r`(_32VL@F%5Qed@7E&i
z9=W+IV!9_EO-C_$<y&a(b6-AkEFAU8zor-F1Nm~~9u3lm^4)YA?vZ>L9bb4X@25P+
z6L}e(yL&3Hr-Q5g@)h(>ACOOe4=~T=*J(oiLcW2fgD>T)&tpgi<(qy0c_kk~*^<}t
zZ{5JXkw4fBZb+WI8qkiW9DT#Z$@KfTL7Yuz&}_xvVtR1{SXa{x^f62~(}E}r)P7Tc
zn!&l7=7b}BFVhGAoA8>Zybs|4({fsM9W-6O8=SAH${eBjna&A@(BE_sE#?DE7d!;^
zA=8_Szy+Fqybtk)nMP9D;kaoqWqiX;Uxk32FqkUnX&Y%ewGC{P>2LJgN1L8q2JW`$
zd#wn6z;xaOpgAf$*Fn=s@%lI%Ix9||hR{V(-3Ap`#rX3G)J@Uy1?)T(Q)o5jrN~;1
z2)z~MYk+w`vCbKq2Nl~CK=D<WPeDKZ6^8Q)zyv59f}j(mFiF9$c0@7aLo^;$jNgLr
zgB4@wu@$2DZWXXY6@Sv~Jxno~vUtZqU~ob)A_xW%iit)bk&1%Zz>HF?dkXh4irVQA
z#wu+8hUQ7do*4j(Qz#~aq$pD6($hLsVRHfQ(-ik9!GBH>p8>;k#cC>D$xs9?gKDPY
zlLsK#ia+R1&rxim&BA=ez>(@ie9quIs^P9xc$lNDPBD=V0bW)37lW%;aDTzBL9yW@
z2pbg_=sDA>I7PGW+ltveXlqm0*+cV=;;Io)IuwrU(6b)Jq<WCMiU}bwxTm-j4}ZOi
za9^lAQ2ddG03Rw|P5{ay#aP1#4C!OVy^)CinPOlg$bjMjWfq<*?A`**3q{){49QEy
zwgh+@RQzrV&{v9~`*8nS5l<@#AG5nuRC>^iy9aY$vkzW^_?gY03!%SR#4V5jvy^Pu
z9Wt|`rB<NX8@de+n@v?4fE{G^dK}P>nAH`)@Tl2#x-NpvzF?qp%xpvwNQjy9m(UC~
zJ7b5?j+@Qxgl4$ew?hz~Fnd`KF2c-{7Il$k>n=bTWmZWqhiJ3HdXQMNg><Cvq}kte
zQ^c9=_y;Jb%t}Q1bm<wh9m~<tc(dPW3Ut=&Dm~E>%m(IwB$`zeK$v9qH<kG&oBc`!
zx+!Kg(}0$0R!HBvNi#c3r<T&qJfcB7%-=5n@iag74K%&XM^HUifcYwW_&sKRc?$K#
zyy`0mL(MI)ZZ=56%)g`W28EkXb4H{m%!_E-D#Dzpgo{Y?i(3E_Wv)H}_tECzW*}$H
zN6`%IocWSnAnE2!Ct#3azMh^CndTEm0j1phcgky4nEy5#C|Atq(rmKcd^Eib8_Z+r
zV<wH}BPdZ~XfnS_ldWs!wJPXbH+MV%?uPl(AcT0+yr&DGx6Dt{M>CquAJpK-YcV(b
z7*VvE$8U$`ZS%Zkh`!By`+AUe^HG$G>o8BCWl5*`Yf9pEnZHG8?{4$xAQ(J0A5B^J
zC+5D_(Du||e*FL<?KiI<1n4vKJBz^$m=933%5!sXy769^FS3I0rTO3)7!H~*dLP19
z=0#M0_S$?LZP>mscYFcPQMu_2+MJZuzk)a`-_TaHi*g5*H@YgT=>_ekJTw(i>{q_o
z4$fU^nD9GPJ(R0O*n28JYk-B9vT`ki-pb@f7~liS-6e4EqZ~~Yi3gRB_QB9sc`Fz~
zKjpVHr2fixo}ev2x%oJRhm><-F=~gE5&xSADWkSQ<%rUn%DRp!1$zAjE5}+ucuYCX
zKnt1><;(%Fp-QbB4#SlBRJMLx=|vl4CzMmJfQwMJt%6FV(#ReCjZ&5rp)Fc@Z6VrX
zlsS`O7pwe-wj56?<743Bl(KU!`f^%%jTWe9l(Rm?AjB)*rp=MFO3xUeBq$$lqDge3
zGLTjhNy@%(fF>(V0-=+l%%vr5s&X1Fpwg6FGy0USEO-FT4CT=l3__-I#$K3bDc_=6
z^lYW$IJnPI{<#rcu5vp)Uh|aIg$SlZIrs=*mz1xmGQCupK;Ne*QzoU*B)V34$qPDl
z%7a(Y!>h_K=mbi=a&#Kd8kAnNPu-|Ikq^I3%B%Dwy{61N2ZQU%m6VUWp*%_@MmLo~
zw5GhJ+<FYcX60m>wYMm@?gLn>(vgaaZY$LvLFJBe_BIIHmB$@u5!<1BPBk5!N|_5R
zx|ID2=yWTCl0kZuCw-uLSIN=g-FwPFx=MPLL9=0SUpZS3VV|<e2Eqr*ea<j=sH{RA
zg7k^<5M>0PD!-;rm-Z{;>6!3MdA<x}K$+$OmFLR4G(|MLP)?%a!<Wju2v|5-+}#7I
zv&E}G^w-6r>>&E<YSHpL`n2C-3e7g$EiA8r^RNgQ2Zx>(dug8FWg&4yo43XDqp&+*
z@$F~`eJtkDe&9ii)yeSdYZ2rCM}8LXp8)Z<&@G0eID=)VDSC0*GC~5-c*{StV3=Sj
zwMH;WmLYrKBE_;Z0~TqP^Qa6d-7;(<JY`!xqn+9Y%Zdz`w^{nlLfak7!Dw*pmWnmt
zIxHv9FVbn5H4^4smY>k>#3Rd8T0lLv+%g`T&nyj#XnW$hWiV~{zOclPjj^y4Eipoa
zmMdvN@yhZgr5;{ex}Jsbjb-aX_#LurJ_|HQ)g{_~by8K4LuXYU)l|5sycfdYfXd_$
zpnX)S^mWn@RUuV%hN^}Ipxeh)Z_%cAxT?=^2RbKI=`+DbsE&?>YLx1`=`;wc8<ns~
zRPBp`-z?Q&0!X$hla4FpsOC<BO0mkP7Jf@qHv{PERxN3Rd8z8=@31RV{qiBmWmO9u
zQ7czHNQGU6%Jgptuc%Ts!EL2#=W1H?SE=?tgtS`KNmJY!)c~b%Z>W@1ntoH|LP?}s
zs?Yv_r)E{RBMe$p?OxzoRcbnybz5cg8%UdKU<jSKqbhg=yLMIOOK=^ko_27Zs>`m3
zuuJtyfO)sdn|6A7RIY>cpUm7<J#2*iJ(W3CU-hakybqoGD(Q6C_o=phhM((!Dnbt7
zLzU<cv`4C`RNnGfHTwoad!mwcgL|racPUW%RZr+;`b@QbGa?*NZK;9EbJgTZw7pOT
zUWMjM)z6;b234`hd>f>%RPJVwzE-XMhkjADBc<A%)KdpAB+lxfXFzjNPocdqSG89)
zR1T|^rN9nSpZx;ZN7dd_fEKJ4euQ19y4)OgVd}bY2#>47zec>_>bQRp{R#DsN^lWs
zf2yL0R0l@Ez!0TgO(~CPwLjH~#HfcYz(B>Sr@jUIlj^Ujv@lLRq6flL>Tye<a$4<A
zB@$=UJE>wJUaixDoK?S|Uot_hr6Sctby^xUlhpe-KqsrOFhEIB=UE{7RP`T!fJ;-?
z(bVUhL4EBL^e|mrK?~gsbtO$4Gu0!~pqiyNqOTfctKTGn%TZsQ3NBauH5EhUsWo$8
zpRZ;dU{Ij$ybjPpb?+*)omcOr9h(d4Y)YM9R4Zs&Riyr$>Pd^$GwIAsiF)BmXkJnq
z9#MX~RQ(N2p~}=YlySMNmQYn*xq4avxC-??nq^&4Z@C7GO7#^gi>p$<M_a?yYCC$l
z)u_|t(5zK|JPj&!>Le<kxT>zd3HSBt-Q>4H-AQNJ8`Tpys5Gg4sBra~`aQ#+px4#E
zCBelFwHM8VZmL^`gS(}!-iJOltIZQ&(V`w%1g=&6E~RE~s{=)7wy7u30hK%I(;ZN0
zS0A=UXdUVh1=>2*)8@iqm)eq+Ox^0H3J81DL39fBu6lARx_eLU+-88ZSN(n*BE7F(
zz68=fHCv88Jy56AW4Irx-}wOKk$QYG+8(P*X}9i)dKwSzsd@(O>GZ4pXx9EroxL5w
z45%lNr|0T!I&ShpJ>CQ4rFu5yT?W-#HbC>0I_MjizgEA=p(4gN>g-eK?~uA64EB!v
zz+@07{=qT`o%s|h40GX+)4bW0f3*yp8{bO>#{2nC{sZUE%c=OogHNjis3+fFf|$Jc
zE<3b&^O`dt2l%B;h{=Z^`51Nwd3V}1_T~R}l;i&M<8y1_$)DeS5;_6=z8whh5dYE$
z0SEFA>B!$<{^lmQ2;w(UVb>9UCKat5<$v%33FiNF$8a6vRrC@M;n&fAQYf$Z2A;zB
zujrY5oG&^Am2iG6eJ=L|pIeE(MDS}DgBT)t&z*=SiZ2xqel+iQ3_3CVFLWL=mQVZ!
zh9`NSe?j8-VRU@;6rVyHeW&?lv^YD%x6p2RJfB7*dzODoKokl5&=_DQ@=G7XMH0XL
zX9$z|-g{6<;U`z2EtPkkfexk_c>Dj|hx|Hv<)rg(tD%#@2hoYNOx~LZ$>K-a!F@L0
zL<5w=Upj_BbNS(Wz~%8fXTcz!AEFFE0q?aDq>wjW3xo5#?*?dI;G5n@ycc<o_2^j<
z&%A)&Vt#!;xDwv5b{{M*@y=8~Tgu1iK+5=RN)le?+o`OkobL?7SXS_p>6E|~J}(ZS
zmAutHbghctd<tmQ{GyZKYIsY!?`!$bX-ZzlUmc6kuJV!3;J%(8Jq)CQ-})y=BY(9B
zU`@Q6!4dQt?^^&**ZGJEXuQGOzXr@rK8FfAZ}IN*ENbQxsiLHXe_RUE%9l%FaGM|b
zDY!OXLp4};_@#$n-p;pCuAzfpOtbz@ek)}<yZFOLfZ5GY%SKxd@A@9>?(&PD7$CjJ
zzqkgpUcQJ{-S_#U_h8t^Yj2?25BMFF+<(ZwyBpWlBYyl!bnP)ef-;s*_}1%ad&+yp
z0i~b+<tE58zLTnH2l%CyFnG=f&~oYpzlJWWmpn($ghBq?$IyJmul;ox?!VXkVLcqa
z;bZrM4DsQ#f#xXm%K_sgEaKqMSqM&t&_%dJb+E32HwR5OVfO*3>=&Ysq0L<=q)D`g
zP}mM^PvIh6)m}ouFqnG_UBl3`140jF5PXD6Dxx|lxTuEV{__>qP*H@Rp!g3`e_^Bo
zpaH`1F|ar!Y@?FbK;azaF%Apg(clLO%PBW=M0oot$WdY3A$STF{2O6+Ot8BM%@AQL
zt-3>n_uSDICj3p=kh8+rF$gq4m`<6NM4@XsR18Ui8)b%*g&!%4lOi0Wn<Q1JpyhU&
zaDNdTo)a?ZZI~{6YKK5GgfDUtTBdMvA5^jg&uI9~77kF+NsjPa5kPZ=pYmasC#-k`
zgM8t0N+%WwQWZ#{aK{M-=Y<jhm=_GfS5(G+QD`^>wn*@-0aq+6rj3#k;XRsDUlOFW
z6OZQuJ?zVbVk!;3EYysIi*n)VbD&iSu3y3Kig4q5pi~MiOW~<XNT++GT9`s_vl`)_
zbqK9iunhrMCzw*{=2gL9w+)`^g`Z~utwHdhGgXa(KP@Ahgt=64bWLzdfQ#$G?MP_e
z5dJ%lZr>D27--%SjBpxC+AM@I&}<PV%>ii@M!SLB7Mdtm*d}bD%j1q<ycVIg3kteA
zI|S<wq0%Y*V^|BeOE_MEu5}Abz5!Z~FpM5Fck#nOcu$!142HczjS>#;3xiZ5(I@=+
zC!%;D{G1MzheDez`t(SMJqqDtp(r2R6QR@-exC}()Zc#LJ(_<$6H3=YWk6U!1%J<l
z*hvPse<3WR@`#s0$S@4TpkO~A!dJp68|b_i(rNPlMtGmn#Y4iQ0|>@ZyznEs<|Nu=
zf^!xtX;$eXuG#}nu3`$!3f;uqaB%y@xD|kQ7q`&b-$VSU4IVtjLl<D+CAPh${EN4k
zmjdhq;zqiHeZ(2G3wcoVqnC`Ym`l5Xe&WGcp!ti(pMnbzchV1YNaSep5h$*H4&h<3
z#2+yQi7c&Pj)+q=;Esy7D2W>^eliiAI3_M#jNXTcKMX^Jp<?27Dq;u|?UUf}xHx??
zbi&0|R0w`TTt(@L2yrcaNGDQs@j<{*;&Mks5iNGo`Lr03qq@OZ(Vvo<C&j6|&=x07
z*aU-9VgW6nPK$r-2RS1$>ClW9C(^BQRxCIOumtfhH8?|}xcxdjC5Z)J!9H26#g`ML
zDWcUPSfq+Gtf7-8YUy@3C+5EcVY>JUU2_>?dLe|F;$a!W&Jx=XLNi-@L^VD+qCZVc
za>d8_aGxh0r%}%rPbI*hK-~Qb=7nNC<w4FH#7)ED_kt+WEpt)q2n1Io_E|u+So}`{
zVTow<AwVyQmky$9rQ$8ZE)ydoG3uAa*|aB8F3Q`{Rw3Teg1aK7KY_zaaR(LnSBa0x
zp;;{+evGyn@$G(awPMB;xUUlp?u$XMit~Pei+Zt`CXfxHH|47u#hV<0X%hF-4|7fA
zF<p^f7vG~5!3}ZPL}=a=H~$6mTVi<>JT;3-I!n_cwhW=IRh&2$G2Ir+Xve%wH0uM(
z9kF&dde$y>--L$_(a%8Zz)q3%gHD$?KwItIVk$kRd&C8<Aa})^R9tsYT;BqfUa^^$
z68FVp7vZ8$<SA$VKwNVl+(YqCUvQ7ah=ss>EMA~F$P;m!DGZ*9AJf6QesK~N0X!4s
zXA$;*7*kL4&*$Rzj$mJiiBuy0Qk=g8hJ#|maKOA0caMk4YmxqwH|ZPk8(O6diT9U5
z#ZmJUg9x28fhxFg*38y`bJ1wJ(dMdodk$g>)JVR8-@}>$syYtRoS%fYBbwP`U~p6u
z_X%yH1Z(P_LMKFH;|q&W&DIF$glVqR+T*z9M;o{g*O*tq?+J~|c5o4zKn?68H7Qim
z6Q!x&i?E|LG6Id!OqRheR?|rf-IE%{J0NkIR!Tmf(kLQfa9Xo<95l~p<VxB^iPuz9
z?(VE+#CW(*(2StsmLyI2N?0Uo#%u*i(ImA1G*$BfU0!LL%TGYgX}l?4o38n}3o&JA
zwu%_8OpPC%?ak7BPx+T@P2Ok-b2I_8bjj5$8wtO88vCti%hyCqLYtvL(?{iHg_>B}
z95}DZ>VVD#O)Lp7YJT#Diz3apW^hrg@uf1{5>1FT++WfhYl5dz&9Xg!Dbqao3!0ZT
zJA2WWa*a2Af22aQeJ?PtXw>uJzEZ=E0(6yTCFOFfH4_3rY781N9MW2i8I`QoX?~}}
zXje6!$3f~f)BlFw2F<u;xM<WY`V5*)8aK+ZT+>XVh52=jsvG2nW*_YW-qa{&Af{WI
zom6bytf@W-%ofdUI)Krt$v6Yd+nSk^5mTEcV;;yIjlp^{(AqVe0nv15-q0MgQ#0ZQ
zEV?ui$q;sHKBnYXkEZ!7(C%t>n!(dO&5~sh_G)&`1G%rsZva}KW-dLDA81A>VE#~Z
zN)7Tz)02w`A8Wn{Kxj`ilb2!eo@%bTVSxHI%MH;$d#0JT0ICC;omL3(xn_?XeqU%d
z(UkF}<|xg+2Q_naP<f^Kaum>BYewvZ<{M4T6POQa+$y2ssI5PS2%WUU-T~*Vji=Ry
zi*~*eoU8U0-Dz&xdz69Luburaf^pYw_>ZI>+N)Hv;i>I&2B??Toj|>{J7^>9fHtWS
zLLY7F9>jD|`#!zQeYHENg2PYycLh}ZwQd(+9-tlm6I2dq4Oh?>s9i?e0f)8kwZMIl
z_8dicL~B(Ka#Z{4bQlC{-KNs~^O*KvG6pe3d&?R<4At&^8zf9C*8}aiRz+7}xb`kp
z6rIqXtwJyn+8t(qiPUa82fHY(^+j;e+63AWiqRStf{WE2p<1nz+7vqWAE)iNMNFr(
zjhmoyTD$Wkz|Lrsk-WnFryZmh(OGRgO%fBdw;n<#QTyJzz)sRO{ET3dwYdsJk)kc6
z63|rb^dHfdrj^rE@0|AO_b^Y_s%Z-<L%Z1y!c6Utb>OnJcWIA0TRVX=o;lhn<*>`u
zUZm?dPkZ7o_%q~dS7RGQTA*Eh79kdDi=!YtuibDAo-Sw=CxBM0T~D9WD$zPoje4op
zWDXpbX-mFEXqUB?Ij}3&*3uUkE3_luL)#T?HC>jKS|6JERcQn5pi-?Zp~}-5ZQXy+
ztktH`?tPs>D|12PRqa=lB&pYKn~#7Sv~o(4G-|)2a>*v`i^mXN(>A2xx4*8XDpctW
z?Xy`>xutbm3SqO>V-TKNv>&`eyscVc5xCphO&Nf0(>A*S<&IWXicYj^59kp^hj!xI
z!0gl-JgNGwOS_kfkGi!C?N;?@7to~kuD0|&*x%Ed{{gO7`(X;meeKcJFznM7)13N&
zRxgFhL+#8<5I)u}q7xKPv?{8Wc&fen5Tsvwhc32f+C<9N4rpU45$|*D8v0>gXdf78
zeezOUMxU=8)E3bR^jF$_mEc}$$IvwCjrQ&95DsbC*U)s-l|Mu;oOJ2aK%8|pcR*Zp
zRzD&NSKS|%Vc@1aN|k{7bsx-vLw8+PE>t{p?es|U)b02HC|<f5J`j5AEW2p&eL$CV
z7#2RdA-eAm>awcQ=&Kv`zh#kbY8DLrb>r?s7@*6%1A{}lmG2?KK%E&)V-M?wH6X$u
zod*N=M|5)*z{OGB$P3_tbv&IdIi^cr3=*R2>4SNwE{3kPFx`&%EbhPKx?yw_C|noO
zk017gj;DH%2;I-0fs53AI~DGubj=IFMeCZVpfE;vpZXN53z0(er0(J{3~-#T>KOc<
z(p60ZcUt#uCCC|F9nE&)b=*Gm?5ysD6eK~nSc0}hT^p`IgEUFElBVs+I>#uG6y0rF
zOQ-5a&PMoYI{#_l&gmx21(&XyM;izkx;b=@Wa?t*TyB=m_&)@bt@HFp4|8-=(t(|;
zn@EQp@^o#K6Ux__TB3smx(N;t7V7e74u4)(S`28z1zklbM(?6dZh(s--HLr6#k!?w
zXe`kU{RMJKr=*!<sctTvSt`^06$8JQb&n4qigMjxHr!X}-d_Ulif)(#R4R3o6XB^!
zr=TTMwXRVQgBqPvD1xcgWm5rVoo+Km4~Ix~Q|K&ey)KM$G!42~N2oUH+&)8Nlg^6j
zq_62-_5<{~Zs%pF+|X6e1b0&x_a!uM>AGn@x>;99nbsDazaDn2y6N-5-PVZ{pxLI=
z-h=RtZqx(>+OA6<1@|4gfH4?^M>@m8Yy|aK_mq<SPjofY5zJHFqs<`wx)<~)eWts;
z0AxUSVFElo*9{iJ{)KK69qE3l<2%qcsB5PZ&sVxlsfhQr&X-nYZ*=JqKsjr5${3mn
zR);g8l4K=&2c1Z<DwU!w)hfUch%nNuQnMgEXSK{5(sZjFTKHvJHPS>Z+sctrcsW+O
z9Z<=$+PxQO`BveZAS|#lF`-}7%AH;^=dJ$P2CxfOOJ9RrwE8L%!Xm59bU7DWrBiD4
zl2rrEHcG9m&mx#It4x^zI^|YjAHkx+YH1ZzuUKV_fUweP(-c@#S-DXPz1nI9rA%t9
zzRpBjt(D3KFm+aIX{LMCY8Ylq(t4}Ui@`Nmy`u8qMyqt%FKM#Ug+qAFil-IZb*qml
z?R3Mcng;f!mAIYepSP?c|A1<<)w@)~*J3q&1-jO1#qo%#!)hY!baY!;(R{tf>R$_J
z-nAN=4fpq~y6Nm}uT|wFko#6al#}hVI(z^I53DR!L-Uc<z;J*)wlbsC&J(LyGeDkN
zMGipNZ<UZthq#|vJ${aW2du^zL;BomC!HU8Vf8Q7w7s;tkbo!#t!B}+{>rN95?s8t
z`br9eH&#DcLO5hKXEr=J>OZ2|G$(zd4sFhQYd3gu(d(7~%vEo`0WrDhxrb2MuMhbh
znC|+<`DinE=#y#7&QrgMM=!ken`+>~Td($q@PK|Y?XLOg?<@s5sQ;KIM85h`s&4et
zFWL#v0DU@@MIO@kEr&s%et@<b4(mUqTCE`cj9d8aj_BukLglF5j@~N4`ifdOI;MA8
z56lpQzWfKEh3ae8z%Wcdi&B5b^-Dg0FkC;Ma*ZeSU(!20LcdG~!$|$EYru}y*GFQw
zV)RqKL4RZQHne|tQor_V3`v|mpVE=1^&eC9K)k;EEIggn%V?V?QQx*6BuRgr_Op`p
zh7ZocZ;IZ8&{Fl$v=mR%->rd*bp2HtuM9o+3)(XEdlhKQ(l=1LIa^=zGeC3nFMSYU
zuD)gpQ1bL)hrs3QU(vl?p!c{6VWECd3*mWvA7v*l=>J{}u#5WkLkP4;Z!jEzv{=7W
zKrc%4m*~Q{qz|NunNt1dG+Qduzox`Xxn4@&46D$4dBfm}{(TmqRqD4=QFfL7Z^~U)
z>!(qvSdHGX4#JoE_85S<TgOta-qU(9r7FFwZ~TY0Bi2Q<`*O_spC+1rhFQPffX<w-
zepvv&QP$(i;VI7gBO10-)~z+*PFv5Q<;@xEa(Z>dTj$U-|E%>dpCgI{>rwRHO|*7j
zOCxKYm4_&jtwU%sn_|6xCNxv6H|>DmG;0mjmYuV{I3Ac8)-J2){>!vp`!S>!tcTOm
z=c08n6_Qk0=kEhrwe{Q^P_424c0K&oTCbQ7l{)LvwFu^_wP7*3R&Rad6}SfLcN>7x
zXdQJD=1taaKf>;s^{oN~bKUyMb#OPVcl-{_o7T)bu)Ae_p`G^snyuf9fV9Q>#&8(6
zT4#QW&fK<Ml?u={>rk37w_8V=0lUL`RW{IEY*utZ=xW2#B*4uk@^{$nx9Q#u&`_J`
zMX(FA`H^;Xj@zuIseHIi^fPFlu<@M+F2d%!|LyYHlypJ3D%!@9j;qGn{7?v(M4Jj7
zTqN0ye1!fc+pIN5TZ)a(KlqtaZL%pJk!JHQ9Y8o|)3gMErrTWbfu{nSNZQRWwDEOD
z+j*O{NB*owao0`SaICZ`qT1+c8^?MYLz{X9RO)ON&||XMCV_7B7Ml<9fYNHSopuav
z+f@As=sPyH-y@cG8x%$2sb#a2cGI8P{P+np2W%!cVGN$z`2L0;<b_Q$?R*W|JfVyG
zl}#6=6JFbVW1v!oH#XD%g}tM#KRrU7Y-6e5)7iFVA);`x{n!I-uC_N%K<H+>@D{qe
z-`4a8#Oq-ztVWxsZEz!qm+fu`^u^ougW(AKfUVUv82H#mErq9pwgVr7^R?}yX`H|9
z@gSH7*#4AGFPB5Msx9yvXnU>}hKFtO`2akbY?*hVdc?Mp@>@r3Z>~q%G23k-x)x#^
zz61tgwvQsvcHH(nrKw|Wd;dh+N!uQpk)N_v(-m;qHgGsdysfK<ekRyPQ6eDG_DVWb
zl59V}Oq*-Twtke5OR@D+05sKhVjy(VY+t7%#B;WP&PH3hZAvCchHdzIpk><TZNVU9
z*{-mJFvs>!`nqM2tp`1wi*3DWf3(DQK#%Az*}hB9>QdW4IuKT7yM-=<%eH+SgcY_U
z*3ir4ifw2p8Y^vQ7NW7ic2gN5ZL|$O4D1%$t5m_!YOA$DXt!-g(VC^rcF`@2#U0x}
zK7_+|+n-ut-eLQkYK1#(<vW1VWh<v!tlM_E3g$hw6TgJ;uC0!W7Vg<jYJz63?fAWj
z!r(XDe3l%p@MqkdUGVbu?sfS4-TXu7q6_0f_k%0*1s!;DW46@OkI(S*j&o;X{srg3
zv>$=3CsRu=887Coo$%q!Twfv?W)#A#qq+P!rr-o3O=oyo^k*=63lLi-<3$$@{zH@x
zkATf)a@+x$!|4BpPA+3p43fuG41-}lbDKT{Sim^Y1HF(Lp9h2U%+z<Ga)D8Jg1g9!
zr#-$R=D?3IC}&i^3>#+D#RSsh*_Cx~hPfNNVl*7?XU+Q|bY~~fZoG$qy-fA-p6q=p
zxbtGo=!M|T-g1EO0Gm1w7C!9GM5rEQFMbbfU-mCk^vRE1N+m`9tST5$1hD&%Q!)x?
zXJX&O=qkGj%Wb3mTm+4`H#ZllB_n?>_ESIyaqrWnL<o1l;(w!#>u-jCDZG3<;wsQ*
zANGOL9EPUP^KPa9dPN{r!TfON4#L~4qPj)<TDk}wJScbX!F*7RzIih<CxXjh%IR{u
zz=V%vp@={HJZm(+;Wmzj(;?1DhJYL;cSEQLlGA2%Le5|EhR#Pv7{5!$Xd;dMX@erl
z*kv04qm8AjVBf0L)j*|7=}%`x`jk18Lh4sOD}&}M<yRkrbFuhv6r%OAc$bRL{4K6g
z{_d#7aeHv#7H@BaW~@d0a-f{Fs2YhV;w(O-T64oGiwsJDpSJjoCbnlR(tknM<1K2-
zfOghm^?ukVSOj{3Bw8f-VsO$dzTW`N9E)<Q!M<Rz|8t;~S!|>%V6}zqH!#0uvHc}5
zuUlwO1LcN=y9KzL7QYOK`&$+{Ye4!eE>ZgYfx%);DcFY=t0|}W$YO&hxW^XG@o@OW
zBH$hL;;BV6ZMXMZ#E*c*GYc&Z{D8$U>e>qni(_#A(qfRFV1pL#K8Em>#dFG7zqaV0
zT=N?XRTm6~ESg6E+R^f3n#Vg?E<6oQXG_CIcd+i3Cer}pVd?4s&eJl>35H&lf&GB-
zwu~LZ594pShH7X6EUoE5c*xR%>RbXXkDi9#!<MPHfEI1};tY+f<xF~^pSI+yV32G%
zd=T!_EStBYgE^L~?n3jX<)0s*?UrSdfk0a<{|g0awcN1*<c{Tvo#=MEWrY<yy|5g0
z7uSxX%1Z@@2UH50&-<uw@&^+|m8A_lolrH*MA#=)N(qDssyTF;^PH+{J3Qs8Rxd|P
z7gb+4!~C+UkP6~zR5lZ#*`!K5Kx~U@C1n^pRST$y<-Y2zHSqgXwf%_yO}rpwwDIJn
z4yFu=x7w9bF$dHyn-G(a`j14!dr<uiy{~-LXV#&ke(G5@;QZBxW1teC?!FE8ht!Kc
zK%jx@BR9}?SiNX0?1I!kd=9W9>OU%AcT{a%24S>%B;DRIYS{%C#Hzy$SEy_1Wpro)
zRX&tIIHlgw3YgRCNt+Pw8Fich)p&JyEXY~)+n+%tLES?&KZ$B*$~Pvd9VvB`tiHJy
z4pY>wLm;W@rO)B;oLb=z&2;tVo3P7J|5pfuOmzpXrLxpl_tWlowz{+l4s+D@v>wk@
zo2-Xwp4xLBx|XkQrB!2r`qvFGEL1-q1I_d5M~C3zg8Et+gcsEo@4&7|?c|3csaDT9
zjxIH-fA|N`&Fa6MV9=r7G#nB3s$WvU)DyLS9fX7Gzdx6JkLy`|qz<aD)h&}@|3>Yf
zkH#T&JgtBo`E2?o#sNOT7%Dz|d?c_B^3_wJ;>-8P1JsX?9ga4CKBo=?bcok)L`;GF
z{UiT0GkQa93(O<<)l~Bn$$u9PE{eZRpO}c|AAJI04ByuPgIHb{3V$d0rXFx{eCBIt
zp5|AEf;+>HJOvN&{DluNB4_!oC^$;s|6PwUNaR)B&`jdr`~i~8S5S^Qo8K(QpylvR
zhE~|;^Yd*WE#O<MK`!&Vz5+}+A6X6eS9pt$VOYtJrh0@%-uXE?*u*anf#!8S=_LH#
z;Gfc6*v`MB1y~3Fh~{gZ{Ek~7UHqh8sC4s#0q9Z>Z%udhUH(0)7rw`5M$^yR%O9mT
z@_qiV-(k_mFOkC21HNP?qIk%Uhy?eD|Md?1KIXIb0p<x`M~UZte%%TfJmYs*VzdW%
z*=%sn`TgI3yx`?;p@%Q|C4C5VkoTyBqgVWEI;8QM|Meok-tdVh>HjJk;*Dsw>nM!>
z4u(!bY#4N$1y?GLcM;0zB6StE(7MA%Xrx8`L1E1sgyt*kpnYFI!E-0j0)$iR=;sys
zpCYtCA;A`b9u{J01sW-&{0oC9;R&fk3ywwLVuZ4L!|?uz6{-#c^rWzWs@38Ij(*Wo
zLgQ5!o)&&MjquM1SA5YHFKAAJoE65`A(#X~bqAp(3U#z=o+NyRcOGgK!j3~FRq&kz
z%rxP{4shp$L3)R#3pUi2Azc4o{#lqoc7`k=^%Nq_7QViN*m49(1%^9UXx2lRC;W08
zQREA5v?E_2WYRBMDC}Q=2+s>;6Ck`G<k6XyD#7e1+*b=lf1s^a$cTeoo$%)v2pfcF
zYN#{{6JCJ3FFX&&aP<j8bXsW8AT%4$_)55N6YgINjmzNTjqvs|2(gt;mxrTRrb47n
zVg=3hoyE3x_;nGtP@R{n_?tZ(x{13f?YCdt`7PSq#g1_R^AOX<0>x9jupj1LqFX4q
z17a=>o{#vp34{kl1Gfr>zT#WUf$b+2zl%nH@kkM{1H?rQXgegXG=?xxY_vz84vU*<
zJ{}}KqNmmoagq~2kBVNjh6@%y#jFo|=>2p&B1H70;)Xae_$Y*@#8f)vcUl}+1@4UK
z^Dlmpc+t(U71(D*vq`W|6u-=dU+i-~L7$SvZM3{h5jU12id69*e|Sn0ZE3x9VuJWB
zdYCf7`fmi2I^i$cKK7XCuo5nsCN&$w#qCLD`9OI+)teHNZ>IW2Ll`j4jn*wkr)ATF
zDR^4Ek`~t?)5gXFEp1xDZMZL*maTzK@wBid(5aZVpYHUoX+O^aTHN#}RaAbAKfl?~
zCAm$c;^5!AX(wcRART-ABdQC3+s~_o@tz3>0l&Aq3Z{+>I|Z;#%v-e1b!Pm+q2R?B
zVnzVQn^{i<g+5F;%`^`)3+4bLh*|zK`g)wP3j<0xGw&JoocWwXTO9KNW$;ch7F7Ry
zni;nqLv@CEH5H(#Oos<`hsmN#BbVVefXic|$AIKBI~rhDz+_Xht&9mX&<^xvM&1O_
za;D@4TvRaTg=lPGxOaip$ViPa08LEvez>^CD7_%O%_wP~rj6l02f4%K6~VlnnKB7I
z>|nf|fZ55^(l%TdbN&w6x|z^d@Y}=OibmTb#`Q5gJZ6p@rb+k{<}=FTJY_UVu<vJ%
zT7rAcq<svFH_YfSFhE00YaF6*WM9&TgA==i>Jgn;51NIzu$^B+)0N#!C~oZ20&x4;
zAzF93v#Ua(;=z7RuM1Ch$9{Csi@gy6;>|AkjGli7*cf^z_^_R{PkNAzngHU<Rs?|f
zv9`8|(4Xxc4=#XxNky!O*gi`H8ps-`<oGZ<MhcZ6_A4q0IKqBTRn14)<Zt03m~EX4
zzsJ}|R5KXDj`c@Op={V<jA0ndKd0i#<81N-7{;>xw4Z#E?Z`(kiEJ%BPm<Ul&cGs>
z&8Di%6m~P6TFhqe(9$-C-9y=lT=u~yz|Ld!zrb%kTTVIp64rYy+AgtE4?we&Eu`F4
z85_R~=9k%7OAuN)E87hNLj~J?7T7n~+`BNm$<Eymv|H@uH85;uH&BxOHoLb6hV86$
zHY_^WVp?%^vWq977hUY>ujuz>Z_PmTJ**SGVD7RT&Cqs_9aDogNA8h54BWZ3YN#CK
zs%+u!FgIczgrNqm=N0@$aX~-B#ToAMI7s8UV^JVyxhJC$MFRINl@KO!1GF2M#J#4&
zp1GWRGhF0x(<n2W&t;B4Xa(HmMyM2WKm0GB$BkCP{YCEOL>S;(7L<V~=29|2N;ny<
zuP<?io3yc0%6T-x{wjCn3Zl5deQXPuHg3Z~wDoWc|AO!#7hD310dAZWe&29YR>EMv
z<ZB;9?=IQ)25lY^#|7X#C8ecs;Uy`iGd|vue&n#E2PB_-4(_N#NyS;gl2!EFI3}?$
z^Z_PBlJPxAsDz`1S(wD-3+Nn|WNm=q2}vD2AtEI9H5iLX$)9v$FG{lY5lFOT#Xhvf
zNM@VU6(m_s1qLaSNlL_<B}t&Nn?lKkd5GzfBs&b|l@i%VVAe}6(=~omGJS{+_uP?K
z&_RHElC5&+^h#z?o%wx9cn`Qf$+fQm^FVTRC%XMmGGhpSA4&G@fWc$Qzf0lpjpW=?
zL@^{u9)PB!bb!|LPSSDoT6LCw_!mNRk?x3rfva@XufTMZ4v#_a-KAT9qx;W8`fCSN
zJ*8|o(7dFpY(TuF0zFL+NH@}i$4B}T<zEg;pV2AlBhohps2r7ED+L!UHKs!TW73rr
zZ;14yCk>_a<Q|YPsU=Nj!lf$|&^#d>u@xv0(jT4B!AR*&9H%izqwujsL=!E2PRE90
zr1rGGnjkf=g-)V$B29Rbq@T=2Te5T*9fnVl#!_-W75^y)T%<{-Ccy7G>5DMLn;{)L
z6@!o|T|-O8EUAIEj<Tii(<C=X8vhwaCRh5>9bkFV=${}o<m12N0?Z}pxfgI)D*Z7T
z7G+Wk6rSO;6*sBAs9buVa`hF`<utjtBK^GyDwWcN_4o~|qy-<qyhhsE0JK`^#8Gfj
zCw*9mu&+voKY*}a`dcoz2I*cpF4ZVCS%`R>q=DbT-!+4DXbZ4Au_^)SlD5%)ShsWw
zO|pBW6Eo16yVAK-`Ed^)AprJ$>5|W3-zR;35SkC9FJqzdQ2HrdUXP^5tDyN<8hjRh
zhj4TcLPw+BP6*V==u9EZosI5$0NTZ9$!@f{8W~1RhrOFofG<LHH!`JCA`hbzy}<S~
znlu-jm(j!;7<wBOzYov@Mmx8I^D){$tJ-5m|4IQ9VpNd@F4V{#GfHWg(L=foj~f-!
z&PupZ8>N{~80AnUe1uV<7b1)@I-d>bXrp%w!@$NE9r+XPV~xhpmuXHKZKVykIHSmJ
zjPog@#Rp+{+9)~;Di@68U*d<oX!L~k(JG9B@)3Qr(J#FawisQ-X))<*BYhqG#u;xr
z0k9(Du8jaIHa_eF;Z5W9mmzF1zU~e4yT*N5x{x0kKcgMl=f;DnKzm`li&9FSCSP2E
zg_lWdFM1eg@^L)ehnt9$b4xZUr6Ph{lbCGyEiyrI8n8_osuAcTldVU9=`IWW0d0Y@
zKWTyxDZ4F26iKo$%8s9ttyV*&Om=E4<v%aWR!xSXx4e#y79NyO-UZHA{u=|%Pwqxb
z)&M#49s)ij|AcCs56i#&31~s`)P970OkTMMnj!K|szwQwFYboQak+R15r)fGSi@nI
z{J9UfXnB+lb}{lpJ|J;&Cm9{CJ0nlnh{go@{AuW6vV5gC0#21Td<X0_`Ldm8OP5a%
zgo_OM5LFgr$`dGgoh5gtTfAJ}ZUu5h-bdMvYWXx%wAIPiroctLd?`&j8|4T7LloEK
zCJO;}Q~rQ1(%bT?UZ@zHO@ICf0lS(umw?@GI+4=r9;Ve)^Lx;g*#%WU)9OT!KvNlQ
z?*^G(dxRkgHf^Vuaj5Cc2Q(eTAHi}j{$BCvD}=i8Eh^AkHAD}#)&EY!zrR06nWZ(~
zyn*cx-V^cf9}l0PFSM_HCkv?SDv!d&`e|$7_NS&HMD+7Mn$vAa(&OJ7_l<+uFP4eu
z>85M6blq&a44QWL?9p5M|7hg)2>w9WTSM<}hvNCb{6`W4$NTCg;@|%jvcNH<okKuQ
zOvekDIWv*FXmiJf*=_|(A4Yo>jRzSwdi?t`it*t5nALQYA(&w&L**E==^LPjFtd?f
zl_oO3+9RqArlJ#QNN}7-r!FxW^xUpuA_9#6Z&)hE;veB`RUN`O!DbZ#FM_qCUCT)J
zvf(hCMX|M45osJ-xd75rtd=hM1orDj_)KK|a=<0AOQ}fm9Ba>lOJ^@G0LfsT+(0tf
zbSnSMWB;S0kom0UZMZ047dm77ir8t};l7ydPKJ32i(Pe^`>c0{+X{B2oStko>?3-O
z*0S#B5qcflL|5Qd_M8$r*VrfXz+Gn-`GLE^UVk54D;qroa-02>W*u#8E~QuQu)F^^
z3uZSL!EX<{U=*P5vR_ig<OB9V0fbN45B*@!&!*9S{WJFB9xCn{WL0m$uOoMXo@`HK
zFX)s^zkJ~%+6KX&H%ur!V~3bCG&+u~??>?M#4e(G9A`FxY+YE-G<b7m7sZ0Ov0us1
zwx7+Vsy=si^e&8t2fH!|=ALZWakP1{-%`TTn>9?Ka}@{Jk_B+;!wzhL!-MR~2XN@i
zenf{Jg4vr-5bZJcMGD$N*mttgc9Qk&hNn|(aozvY*tq(?qjm7g*p<*-l}<PB>J`l}
z|9&-<Ev>O9j3350B7`3`w}G%Whdx-e&Jaq~W9to6d-~HSf5YHs`*#r022a|N+E_)a
z@n4qE*8HaLied1p9i>_}e>NEqTNTc*`eWZbINOy#o6~!=^lIEY|82-!nc77#c4JDY
z6nj52VLA1Q*)s?J{FvrSsQWXI4d#d_fH^xH79q@ODrOF4T5n^B!kDsrgb>b5{R6^C
zW;(fvVJgf);uw26&3%UXm*(CH%xJ2ctYW^SM{YIqJ5^QGFkV;Ssh0VYYMSeq_$}a?
znCG)#ev4U8YpOP8{$ZM}-(?;%XzXY5sB+>Z6M6$WubGA8fi}dPn+a?u_S9Q|31@q~
zAxvkx|NFmXsL-WHkXcO4WY}ag7QZ2^9OmyAz{_Qp>Cl$PESL(C&-~1xR|U*?I)Glt
z9HBLK8DlU}BZAA!O8P8HIpabXM+I}9wz94;HYBWMt~i2JF{7xEq?(yTNr5{|3}vU<
znO~QH>tLq#0;P|cNjp0a7%Lj%=gfEXw12^jzXdR7_Ch+MaAA+pT;7%K+>I!F*x?2T
z(1Yy374YlJUZ$fVM_Ie0Ai-?%91QL;_T5I1D7L^4?xWccXekoI=24YaEc=Y^!$kH+
zdORkvy;O0Q#k#g2m~2*&0Z%z>ZUM}5*;%^~Ofmb(bqGt?_z)OeVxu<F`?r)mKn`oz
zVH<&6%chKkMI9SWkG!jF5-n_Qv0s#<t(moqMOzDNOIK<u`_&-YZnNC`7@)f>3Ib`-
z6E2{wm$jY<;eB@EHz0j%CoR1mun}*;{2}`r?QT6{!~UlG|1sMVgrJ_V8LQFwl)bVC
zTtC}TkAR=CyBrYO06VfBfj(#V{f4f+V6A92{gRzf32u<xLWQHR*jel0{xuszWnBlj
z%vKm2<3ebf6~Q@dM_=N&FDaO0&h{`!F*kr>RD2<pJ54!}`&>UgCY&T&{{U#1<Uaj)
ziITC?5lo?Eel<X=BwsE<gw2xo?1A<~(oZkPLCK#f|Mv)}##<Cd*QL))NKHD9rsu6v
z&31JCj<n+_kUH_rT&UcYKCgn$KB>+?^QgztiwB@OAU*N}f_^E@84Yeosx^kHtI_q3
zhM{Bl!|SPdV)YPR0c+f^q4CE66TqzVrg`;Gr_Z5v>(SrQ;orX2;P2gW^y}KqZ^Xat
zqt(FNv*aUKIWnnf=#CS!!O;}s@5wBq{VXr$C>>r1V4hQ{(II98<-kIi-WG77Oz)3q
zi)MN#`4Yo?YYMk#nLf%BCosF;hGrsDK;LP|V7wn7m`ui$-jrEP@FAFIGk?5-c@Fb}
zwjOhtOv<6;G0ZtCuFYqL?S)POQ~sKUn)#|2<UAvxS-}NnnKj5oCUYgQi<mFx!@ih#
zO3#@R=0n=6yu?ViK&6y%I0Vo#=0mD{z05oxg2QqqZ7%|?U@Yk(y2A9+PHiPKnG$(b
z%<l8BGgLF@n;@-WmYRXBW&UbFFxQzZKMdUsW{`??ZZeBB@N|n=L9^s$W^N~<Xkpez
zL8Xha9trGj=7)_?>0zS$VSbmXr0n25X2~`{_cCV%pxkE!4qPA8Ob>}9HtHvUr5o5K
z^dQM(U(>IY%`T(#dM@kf2h~D$3)OjDWS_1_pGw$kwBj#g-I0RByL%%gNUGRgnr_yy
z@f%=poi%cS${n_wPOmz0Pq$E61pWvUsIQ?&d4PnmOcqR!vzq~Az%%vxd}yCwk9-2x
z5$yJV5lAF^&kc4_?25~XE}Cs);4_Ae!P^c`oiU%m%Sra*Utt%=dQ-8~Db|V}#HZOV
znx~&(7s{a-&)!EZ1HS%w>ohbI*p2i_nnd=lIUFUic~qBVNM_S_p)rLGeuLODSWnt;
zEo2*y1Li!tj8eX3Y(G`>U1n!CA((QuvKcBB>}Q`~jO*Es?Qq|~eo3?MM)s>Da7}Cr
zZ4|e%JLaLIx7j>84$#JCQ8MQa`@{~UojpJ)`3?j7?{qYFvL%1Ou#0WGjG($%@6`yg
zhi(21Fn8HACQ!Y{K9d2hmmQ>s^nG>)rN8^w{0y``U_Xih8DK@4-acpNpF+GZ*tt}1
z`jWjvi@HHJ;xUA;*n|>jzGkE6fV^Q1dy)2%?&k_^F<$PR13ff-Ia_*o`Ee<$(8Hq~
zqk&2=_fIpp2yPbTb|Sg<jW9UPb%h|NGh80cn^U<4+IdOiqVGU6m%Bu@sCnGGlol-J
z9#TnM3CB@g(<N@r5olI(?gkxb4VOb1s#<Pq4T7rUn%6<~D%aY8wt7x618oglryu+_
za`yt@sfqg{9ON3u{s)!o-0Ou1<_7l}<qB_dt9w9haXua(&D?OBuC;J7da1W^6EgvJ
zn_F%NVLO+aXh3WoT;F2AbaLzkxbNaT=AgfKxf?V=y2s5y2{67l`jp;3_qoAn*!OW}
zJs^)blNBJ3xif2l{e%lT0nOK3gfqJBD0$Aoz)A8oot$x&e7Fw8Me@;KXmgcFDK+aR
z86QvY9}h{Y89aGP_AkQF9FW}ZK`=g&U@FW#DA`3<psyr`?i@df^<QW^CD}9!fu>5F
zvS5%aF{boFkz|NUPAVk#5+J-M>7@#aH_{!Qh{D5Y1C7i9BR#F04jLuoKqbg1>gF)q
zf5(iflOYW;s&a;>P^0s^5Mr3oCfd3`ZnVD>peKwPRR}oJ=&kt(G}=h50BEdHHyu|#
zWt8s*;c25RGk~5knn|m&c%wP3usdtyP=szL8Z{JxBpKBl0%o$2{NMkZS@Y9>qVZpS
zauBB9M;M`X%~Z<p{_y!4ME_&jSVX;c)Thu{r~Lwd|N7%Y0B!y-82{el^9TOD)vp6O
ze|`EP^mmQ22F~uW^h?=&7=*v=zoJ_7J^xY9{waP9eOD%%u4Xsp2~7cf7{iRUG$f3h
z0x-UeSrmvLbN@D?_h;;1;VKDcw$Xd^7_*b^@DOI83?!71&@~>$NIL<Y#MtG+TLx3+
z0<b*h2+g1`GJSu7lrhqAP^n^+?_rqg8AB>!#3!&9foo&FGqfX`d(5E@NS`tHqyTkf
z18F|v&&JX2Vg#Gw&H?~`_$X@#{Fn$Q;QBM~P)a<QiKXhlV@y09SPo&FCWC}BeIG(U
zn%OlKnla4dy&z|qkVA+(f%!ca28ql}nhz!!nANmBk;zP02sVpxrQ)q@roSD+i%b@6
zh!!y+_t3iv#+BX}R~Um8gbmEV2M{(gaWjC{!t|a7*UB8*0T;KKF-hn^8*^|OP|mRL
zQFUfKJGz@L3HHS&=y?J=tQ?w&tl=wKm?W{~lR%Q$Z8DG)cJaUHS~(kb8Wt@qHx>@V
zxq(?AC%9w3pe=&aR>DOjw}9@lD6aBd3|utVJ_~Iz+<RkS7t3v+EBPeX@F!H_xRuk<
z!BbqvzX;|ucae5ud?j6mv1s&@d`W9Ye~B5rX9FbP+M%O|Bo8T*`Tu&k^1rCAD?abc
zn}-4;qd_rRm6$}-$}kI{P|{SCML+~)5Cnw*M?{f9W|Vwl{LlpX0EV`SV6I!-8?B(0
zkJd3nkhsQ1t0r0%x8OpxaVg5?ntl)Qm;M3GeCB=5JLi7Sa_`K0@7{avebw^4I>fY6
zZstVYXL2e!4H_ZGxIwr|etkW-)$$8|L;D)poB+RT<)NLZTB*_=$F)}u7r^f>ML!7K
z9%VK^eD^6%-n_YAx&E{mwK$+O{}q@<<w887Xi`q{&FPS0?F(q9ViAB=x<&mN?rYtq
z4}kEvTZ0SS-`&O+A&T>E2g6?V0Pj-gAfWHlq&mdaMh*NlM^~0-CZ5nRo@OdjZ#~cb
z0DQguBYAVhgywB%lGr2t;XH2o8Tg)D$O|9i19PE0#a4qhN!aIrJn<WTxzg0nwn8~A
zJsw8Wdv~LBW)A20W>wz7dB&zKkZ0N_AOP#`1Zd6kAA|Gxn>e@ckdqO=bMr=EJ}5&U
zv{<v$$}7H0rG8k!g<;}Yems>)0h|ykm*(+st3pzepj9h1)x*$UX<ic`^-><Ez?!7V
zJk@ec+Or12lhPGWkng0V{RsV{bo*Vzdrf-T4DPnHR{?iVTJa7l+9BOM480e{(id73
zme8+9L$QLgGhcOCyzkCK>=Enwq9r2jJic7i!80mdl1Ble=$6j=!OS!1CT}BrE*-6f
z`cG0f@6P!>t%-uLgiiDWav9Yehov$~;1#OnbonYERkX7PhLOT*><xA&&9s7TptCKn
z`r4<dx(bquG=~>6U!s=lu-HuATC~Synv@EqD^#OLSu5=b1M**#H45Cn>C#EW^&_3*
zOZNd;dGP#@nqMM>CsZ1P8a$<Zo`YSke(x!dKmMpb<bv%L>VXBQWVO0s85CEl(?Va}
zr2A{RxAj<BzZjO<F-e8u4k>X7e0EBX6|mbSt>QVFZmB#N!V=PD_EbCgJ^Y}RG&2xp
z|3KB;%Uwx${V}d0isg}$p!N&JkZz!(oG{%;{qw+WqT$?7o9RD40=k33gW<l0)MjYZ
z(wwyjeJ}Yug{QyK_S@hZsEVH%jTG7iPsb>T7eE}R`-{;=r)dmlhR)C}Es)K$?F}F=
zli?DKT_NXO&VO8`(LBVzMi+RG#C6({1jQf7o3r076!SgY-yoU)`8TPNlYEb;i?e%=
z$>$(QJC$%Jq=UX)3%yPn#ksz2`e^}>Pf6li?=wod0j@-C;iW9g)T@UAvQd2isbI{%
zs$H#!=AiluUeJF*9oGqK*VSpQz}#2w<S|}{+L?f|7wS>p0$D0YZa^?XzVka6t&y9e
z!8OXmjstmG4!Mo6Z_4Fcfb5b-^@FjGHH-MBwNmq-72H})<)0AKX3c<TRJVA$roaj5
zI;9QS7(DPxdD?k{lF4)T8<o5#Xqmq#=Qtr&qtx*Fnp)*3PoC^jzTq1~owD?w;Pxqr
zDTu<Q+_6I8OJ#XEqWDS~;RA&O$~m6AZdBY_;jl@0%zJ{rR(A7W`EarFt`GE&D3LlS
z9#vX6n|VTMY=FioWgBl5{D+b~1HqhDjxL4%_sUo6U)}AZD!7v#ZQ-H$q#S<A#+;I&
z9{XepByp=M5X0mnd;!PXRzr1){UJ&drk;XUqInlgPfaO)ftHyT-;KH_rH+A9%Wp@+
zQ1X;=L^b{8S)8YYF9S67>RFhWv4#8hY29;RIz9ImN@oq>Ty#c+3^$oy@=_=3d>*=F
zg)RXy`(xg#HG3#88L>U$xaSm&h9u|n4LG0c8_W0q+%iu<=MCb;1M>~lD9(Fr9b#P2
zUIlr6ser`(C<1N@F5W;ZE$q00PzndM;oQ;a2YHd;^(srccmvUg(zc1HN4cbgz($jV
z>2Q^53sS#o6{ZtaBt7e+RY~|jEU83{Od|p&gr-kR!gsRSG+|MeZPLVu45Qv?&>R0p
zmR^vzC?_}HkuJ8&6!CUZZob*XIK4q{GMLPUAd}e`WC%`o+U<Fc^sL<c0KHyxDKykW
zugB@nU!m2|uwUAtkN81D@Bg2@{-Vw3s&}Jf4@C0%US4ANT~9ZS??{u$;@aOyhKFGj
zLIW%gTcIN$+gg}c6fn`|nD4X~1UT*f&bc=K1$KLWK#{$0zN5gJZ38CX-)VC=9l&KR
z$|>_|RpXFx;N6?83Jy0My<A?cy=U!tEqYo+M)LSLON6f}$k6k#xGGk=r%e;%uPK8?
zOoeu&>y7*FZ_f~SZmUPSBBMN#CyL^FPj?X(O<tl;j#d$8EaWae5%OS{U!}+6PSI4<
zOLiGcJnK)0Tld`G5mnpW`?{XTY0Y6Gxlr3j7-BsXQQb)+L|LfE0MRs7<L+8fq5a_f
z!9m6le`83Xag?vos5k44zW5)S3}cNZmCEHO_j%^-8xj~26l}1WgF}pg*>kMp#*MQX
z$C?dBW7h21V*_o$W#L|ZaCo`Gy>y+wc^%8IRLC)_mNV_8QbpmqAs>}0-<24v%jrd)
z14aEbT|9XY6z)m7_4KQOVn>p0F~toQ!!5da$tf0EbW@~i@ihpA4H5m4A<YxkWJsN&
zj!CVMri0uPi6G<|AU012rdG7|um%yH0taD6u>w>&B3e=az9)>S3=R|@rJ^)2P<+QU
zEJzHW0n}cxa0ZIsnj{YW%=S$KJEmD=rS+JuV>W4!p!6P-iRm!8Ol)G(F4{mS&LqNT
z_E`FKCZu_y1%$=~3)3w4@eC0kfuaUyXF)87iQySww~B=sU_HadA!ePTZzgoN3M-T6
zqK-+WkgUMG6(y!xVaYp2Y_{q~OWVXLtL{x{ooKV_{P4yEQss*wS-LkVQWoJ^x)IRJ
g&C>Zv2gIi!G)^PxS&F!r_4E?%*<hawW46xczZoj%tpET3

diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
index 6deee35b8c62e3e36b12f3de2c1167e806ff9cb9..137679006185c7928dcee6bc23aec347c74c4d55 100644
GIT binary patch
delta 127500
zcmY(r2V50L7dC$Pwyn2UqQ<VVcVllcYBaH%#Fl7`Em31hjK(CFrU-%xD2jrh0t!+T
zP{0C+*ua8<ic%GoE@H!q-*b51_xu09{Nm2ene#m7%-r26XJ*L{9Qk7R$nCA<Vf~J^
z>7jNk_$bI)EPbz%wO-B3B-#J_pMp`J>>|n(4CiI%WeT}!?e7XC?CPVOOrcZ-yyax7
zv~8?RKFMh&kP0PR+*2-7aH>~{P~h11d92K;R4rZcJC%t_sJE_RWQv~VZ=kOETPE|*
zQTHA_I7%T)Wi~^^Dd%=&WNA(Jl5+HWnJm5OUe8aSDm&YBYnB<@T@<nmCK&qqb}i*Y
z8JSFZz<&(eR@32zO4d&9g95wqzW-Xbb+1AhC+i@84T*wN)>kkxV=vsRI&KDtb5|;H
z-LssPG29oe<uW;^PV&FRHlMX;F-ux$(>R&BhhhhGO<dobNYtHU7+HS_j^jRek0|?G
z%q8<On?%K`AA%T}dVnIH5c;9b<^M$t|1YA|zy8BGt7F7*mF&wVkt9?77Rbuf;}j18
zF$Y8|WlDf#vYz<I1kJ%cll@kJum|1CeV57mzE#N7@+P$0_jj3;PeA!dm8=do{{x2o
z4_L?a{4bDskjFr0#NRRp5iMyVs%QQ$kuYHcC%efAO?3m&2>fG$1jT<nxXJYX57Ey}
zL^qjHq$u~DCy(G&vb_KCER(C=sARYPm;JrT%I*JUSIX?0KNtL`^5!K}t9YjS|7t}f
ziT_uv33dE`+23Wtrhc5vi!sr!M*n?=e@xKk|M}*{4Ehhx@64lTYABBXk8dkwLX`hC
z-pN76Rxu<0*Ak}_RmlDr0XDhsuZ(UokL+stA?3b5%l~px%GNLzvL*NZQzm>dkChGi
z|7@o>+3t@gr|Fj&!i@NDyEHY#u>U#zpN1ITlvRTWE#bdR==3?cQakLw5HWNQC##*g
z17v7PmKve%KdvuhsU4sGC-Xbo*Z+#}Src~a|AXE7|6sTO|FORR7n{&U^pVftC#qzM
z792g;GKIgKSDE{Mua+sAsZ>^vK)jPJg#Q$|Gs^$mL@=VNmG%X6+DHmsqY~onc=;u{
zN*%92XTWJy)<^ytZExmx{}Ea{bKHNXwxzVpPn0PYhZu{h<#>O0?Fz=z|GD;a=COYl
zT~CMhM@IG^a=dsdye_hb?^L)J>UdoLzNf~OFK2L_d72cynkmOMtU<u_%v;hAswAD`
z@2GUoHNyV9fl8;$C%NVzIvClRGa{~+PSaJfgs!djk^Tb5uawk3CQ<Y@x(^;ofDyM9
zxHcRjd7=l=xwK|+&A>mEY|$Vp-8z8G4|-1y{c)PEvSFnEXBaUoN+gsO?SmJ)jwEXr
z(tYzIbboFXVOv@q1XIi-*bhEr{$nnA{m%<B<8hl*JAWkAs9#7Dw3ako(Y>i;<_v0~
zjvmC|oKKpkFOyE=K$7$tPWMBy$fWHz(m!88{4+XHX{TViztT<VK;rQeDZSZC1&jKV
z`HU}#?&3=_JZ1ycJI{@-QMDu))rvH4{Z2adH^_+vm#Os9apJk%nIz|HskF^#x_`Td
zTEZ`mOqLfC|E$SWjnsL(%%PG6v>{ckj;;Ygq&l#v9_zj#y58NX9!n-s4Vq;W-Or&U
zFR3I~8gG*RjfEs<w~$+1&y)O88R>+yCNnR`(REz~Nz#9%`$9dj*)K!iA(Pw4qtZ$;
z^J7yR%)d%X;lZS28bfY<{DHu2JW0YVrMgCJB*~aW(o75^hOv{#i7(<v@@_P_wX~Wf
zEt{UOC41>Uy$3NIJwq;jXsU)|djuJ7--+n5I}_0%j!Y&sHE*xq=ss#0kp|Y0rsWTk
zjBRqX!A5khS~52CJk|c&D|FxS3c0wxsTzO3C7q?;lX<<CtUNeLJY_zldCw6?#kIGH
z^z<(BE9)9vzey%n{%m@YtPONOtR-o#xl8wl{YhuhRx<NKPljvv65YThRC>NUv3bN&
zX>}C+>WM?hWW_@=zqzU2$s+00PsX^TlHJ)#8O0BDZTl%HecVY`Ux}`R<4DIPg-ZLi
zr~4j@i8Qb2v7MkHolf(}aGWPOVV_IJnBPfq_ftZ7YDqFxqSA(Sg#By`wdfypP0#<N
z3d)?KiHmG@Inm{QM)xH$0v!8^h?d_Z`Bx7})2E!STbm3Is3aYqe@G%0kQuHw)w?66
zP<Uc45$bp`wVc6|O0(M$v-@e{+^vz(^B<@n@G5VrS=1#e=u<@CKbtzAkSBCMfF%mY
zI%?_*K4f6=ZMr|x)V(yjO4u$tNOSvay3cq*rH2oa$yWpDdc=*aeD(*)d$uDh@1NqC
zaL5WKlW3WduI*=&zr&pAdc>CiVLFnVPLuggN2uxE_aXE9Yp5Rjf9SF5Xd}tpZ%HEe
zBJ(eHlEfplsjgedyx(;)Igo2&PN34`Dk^pCI7bG`Cen50m!uTj<V0c`nY>p@N(;T{
zT3k%jJ9*OSA4rB@igZ6)OO7Tt^@f%^bUz}Ruu&XclU|YeF4=T#{Fh3%|4Qxj-9@_Z
z>o`kws{e*mk4`1OTsIPFQFBtdc7c?B{g-q;VAR7iF^p>P%Q7l03!$rUiJXi7Nb<oq
ziDCRh(oabxli6(u<+qlq_vK}hk8Dr+1|3-}bU4U>XG>CA+?uYdhEs9PmsHnY(+O6!
zfaI>72^_YPNPiqp65rW$4SY&O?E~ok)+$0-XEbT16L#ppCKq4R{nvfS*7ObJXlp;x
z?=YLE{=Zu@GCA^hYSKgh5?$+PBDyw+h}JqtQvW4^6ED;Kyn_T@yP8l5pOXCRBV=Gj
zKf0cmNJn{yu4~58bxAa7Zs<pBa|+4)DHCbVnxv-ZKl2F{M6IXmlcpgxeKOTD?HxH0
zGKZRUQ4PVgUC8j5G6I(c5~*u6N&bo^{jlRy*M2Efx-+@S315=0d`~<>%ZR`99iiMm
zCr)7@^c}LlR}tWsSp>K+i~tjk5}<`E-EXa;>x+-nHp}Oe6C*AXQRMf8^8Ja3OdpAq
zn@gxE%SaOKO(>_X)Hct@k$mh)x}LI=d~?&t68;bIIHUpO^$(}%`q7gNbUQ%>8@{Id
zX}?kZ{&Xhr;J-<J=m(-GTS(NVrhd%}^Ln+c(M*!S&*{FMR*9=(IaVsN+4#xSvM&#j
zTjATVOpv+62)JI=Vu>LOc1)&vciKTUxVeo0{d<uCM;;j-*Yq5CJ(fehIiK3#WG*?e
z^d*6NJ|WW3HKh5jobG36=-NU?n!y%gUc{4Tzr|FUerD1f^_uv7ZmJ<S7dr?rxQYxM
z>qn|#Gs(x#@ItC(Ge09w9fL@9ydSmDqjDAQTl6QL>p^r~_aprfnaO0pziGzT`4eib
z+33X7GUalT=l3D(PAgs4V^X7*EqFk#-2GB?AQN+qNY_swlfUjISRDFiwe0c@a%)s?
zs_}%T=OE)CQ8%AWHEYxK%pcuG&HgMxqym}B>5~Phdj~g6-c_BiFGZ_<v2{J}r-$!D
zMQ7Z7hSF~<sM6oP@Bs3A$IsK?|IFid_%>@IJ&Fqk{et_&(`k@d`CNm>`ZJlPn2z1e
zAaP^FQLygKu;-BkFyGUBV;AFD11EPg>oSlFWa?HU*~3gI2W&6XaR!VAGo!0vbsr=3
zLCr&$2?qfWW#&6Z!q|RBmj~4Y%&i~c>p|uTjTK=`TMoi-#+3zk1mosFa)`;KVec@r
zcRbi48KDQbqnNaj032aH`x6z8W_%ujJBC?Hy>=|q@f0}Y80V7^9%UL^Aa{((qX96U
z+2-K@K7k1oP?*Sc@d5X7MtL80PcW+u5GFCpsfSKx2Kj(3g^7(o?j-X(9p+ClR}TPw
zno%Bx@C-Ab`qxzEuU&8^jk*5@Ea}Vxtmsr{nW{t3%wXJuVE!DVjX`pQ=_oSj|86o5
z@I0w<nUI-i>^x?PKe%r(TTcUVn|Xf{p5A3Tehcn<Oz=4X3m8}G*9sZGE=cY(Pby)s
zj47qr)gva*1Aubo4;oA=nC`vNzBSCM1HjcXGhahk$IPz;*;7V%&7uFRXS53;ea1X~
zh2%NoR0_K<n1jiv?@MOVC<tFMGp7L2z$~so?llwI7LLAUw$;JlJLZSysOWp<hh&s}
zWG?lFc^7#pO`}}pMZWNGi`@6U0Q>mAgM~VgzCL3BS<x3=u0!?P*YU8l^7&YpUA5;I
z+^@bj9P2?+Z!_XEsP{Os0u}7}dN;1UD*8j-+tC8X`qa>~8_G<=N~cL(S<@P|RZpX7
zH~VjM5ONzLA>ngWSU3}5YYh!rpY8h!FQFUr_?;Z>@6N=ck5_MIHl?6ip3G3p+0<Ul
zNG<fYFf&@=<=n^A(*!nzDJ+Ca1M^`7-1@-8q=Iat+(1vQm;CA%@O`KJ&K2YW<%+$?
zg~-!=&;W7r!wY~*lb5&xmn|Rj9IIJ!NB5Is845m0S_ZAwE>l3)BWDu|hJM08bDB#p
zRB-vn6}WmcnR2)g!G!({-P26QI#lu+v-_ARQ@>#10{+_s!in!ds1L?4pzd-z2i5E<
zV0ch>tKNXlq`UWePA2a`u`hMcNtl<Z9lhq>N59j18;f@86I=+V`|d;ZN7ZlmbokM~
zMH>A0yjvuG%>iL&a2;4rGm}A8G=2G^$OWb2=LW#Bsope5%$?r`I!i8%1kb9!JD_yk
zWFzD*%qA~XZZos^H*otihF2ij#r)3FOMQT8PHXQNCPW3&6U_7P;C3?8<b4X$<o-#f
z$^TPKQw2^lO*J^fkk{%Arl}_97^+EAvkHf)kGH(e#novW`O+*X90prQ9EYdvL;ps5
zcHG_q?byxna5|D+>Apbr`GC$>HL!3goEh4ee#YTlXstea&@A}=m7dl}6RQ!tQ%wu{
z2XP+y1#PKUK-pqkSKPN1sh{uEW*x5m+`7Q{@PzY_f3=>Lp3}zBTj$K!Xe#Z(WNinJ
zE8{4egY0g`^CidwnJ{;_wui~5as2>uY#lfbGJa113}f2gf)}yOV*<u8C+cALDDz%`
zN-}fy0pKZ&JQA8Gna;Gh&twAE0&t!=5f9A^%&c%!C69SZZ}Kf>?hTl|&0KJF2L3T~
z!W)Qk#+xcr!Ay{#`ifbQ0el0qt~Ct4W^TAZxJjPU44NMD@Ha5HSw7DQVSv2E3CS*b
zD?gC!mJ2!XK0<zWAIJ{LFVW)huzcwZ;7-Ut{sEOF`O`J<B3WLZ?0|_2@=}UzT$Fc1
zcu93#et`locjP6lAS{yqMZa0Gd>i2($aft@<35(}e}P=Je2WIn^-BKTDpbZ<v2q#6
zHY%?10C+3*Zi1$d;ur=|)o#U*d~gOTs#`-dOfl$BXof4|$EorDA5-kggr#^z-C~fQ
zRYZRUe1>8#Chko?ajUMQ0cyLw8rgQ1uBdnWgMX<1Q#NWfrZlQA{@eyzqn%T5KlWNF
zu8YSr|9uueSu_Ln@8tR;NV|%+aqaQ21FpRfwFX5$hn<2M118dwH+a!fh=z50i1r>i
z{VO;;`pqv;{W^grG}Ac;<Z~9$+U)19&r!N;-3VNNd-N0xt9#u-9Zso-PDag6tEX>*
z(KG5X<585U&Y_BBsi!k2yQ%)e6}IlGop}&l@$c70=a|!o3i|R@!%?27eM<x8DXq&3
znDf;yn~K~HeM7>3ANW{iTn)S_U<Td<cM+qsBUg-&8qD8kij5$Bz|7i%pSO%*!;tKd
zU(JLwJLMM-gK(Gp0Zor~%kL&3*&`p)sK6MoSKhZJ*n;J)ULx5i|0xYLq4IBLAh%zh
zkOI|%@?oP<+c5dxTj1q!dB0dBC*-?nQGG)`$q!!Kl;@p?i9Gqat*GHGd1@YTcjO_o
zPS2O$8U(U?@(~m?D3DJz0aqm7dki&q6wB}2f@-P!``?hgFaL+aOl9&Ri$VHO-jia0
zkL4~eQJHdi+hGt^%0rietxEn&DXLZ@FF*iaRV!byAKcE0tbb7EqOjjX;-=V54dkxa
zIUU|_QbgCn84pDkO~DT<rqJ6P=}`PdKhRA@4<%G{6_3=QxusZK2!pp3AEKa>uUJK^
z#=DA<^WaQ@;#XQh7b+&rK~k)UTnKoHVs$o>2MY6SG(wr8Bm%idisPMud#qTV0<sE4
ziyO#QDn1zpL)D6o%RybEa0HV1Ckp)zWa|{F*HEojEHQ%Snd0j%P<^2oN6WvL3Xg5b
zH7I^~fvUY$?4zOJt)k04;NB@VQhh%tSP7bqipk4SLl@<>B-Gbc`PVWCH!AN_x4%jG
zWf<&jRtDsvo}S9Nj$crVElLEQ@ZKt)<K0qiRnB<_wr$F%w*mB3cG(S8KjqXvVSa})
zRD$MC<)1@Pwo4h<6UlDnGm0bZRX&b`N|3S{1>^Q9H{FI8A<8~fm;K6w0+bz4E=z<@
z;mRA^;6;RT-f^q}Rfm<Meur<7%Hf-UIHFVy1|nK1^hYjMIpI^V#VN;8<l~q!eHei8
z%1*-|OjL&7#3OKAS#bk^WM#AYa3)20xf{q%Dew0}a#~r~5-O=mQ3I7UB^QGVo>lr`
zzOTwq?#ZMWP^NN|8eW`Ns@oyCs2qG9G?$bk&O$XyS!jme*~)A5cwANfJs2w2l%He2
zOO>N69R`{k$`5{UCRaI?!l8M}Ejg&+ZRLRhV7a4gZUo@2@*4Hd_muGzdM#AiOOX^Q
z=eyG!utX_;hpLq-vuNR1rW~CGnukjC5qNf#+q%M1xw2<IOjIhLwS%xqX}^P{R+&PB
z;uB@WZ)lRIN{0lNdgYHB!2MkL`VG8)q0A~o*(>EbZvYyUBUgg#jk0tEG~X&mUIC}$
zy>k2#G}H&BTL^TVRnurS;iCGc96&eK=<h(|uF7u#*EXrfO+;IIs3w|W*HiUS0i2g=
z7p)Y$Rh!h%^ilovJxpv<wYdWm+f@r^0OzMVG!{aC)%QtI2~ahTfrVWv<9*l*bf^x~
zBzuplVK}&hRGzJ%8muby1wKUe>?|5MR29(|DhE^}{{rx!YWNL$gjCf507R&YVv&nf
ziDO_XO0|)enb9idAT(oC{-@w!oa*Oj)a9sZiwI$Y%KRAAiK;(nggl{gw7mhEBo$u(
zyD6%r6wW=V>Om{x)2d%`pmRnwYc23;ss%fNPgjki8P^?^4VyHoeAOIUg%qg#hXPlq
z%6tZAidDPEqpU=A@(6_YRrA6Df1rvT3PTT7Yh`GzN2*kc6P2shIB1})P`O-yr_Sop
zsYqPZEeAvBrp{UfpWM}*rofp^>iW-t@K8JEg2q!_cmbBY)Q7(Yw~zV^g}b(@YboI5
zt8Pw1nV))K1}yDVd#V8lP!FSU-EQ^rTWF_1b*r;b*{lAJbATpDz3B{qIqJB<$lXwL
z-$6A`EzrE?mU`(l_;g2IJP3$<^@@$i-BVAYIC6oyUpHtLsekQ+T(SDk0r0m}{g(o{
z`|4E`$SG4V(S!P-Ix7NIdaPbM9GvCq%kz<|ROiOf8lX!3?pFY7)U9SfwN`!N5-dGc
z_hZ0aua1ZX%?tI=%K*MqH;aSjYqfn5ym+IQYEbrGy<jnF_(5Gh2=I^UBNQBRW~V=e
z30HRc6_mNL1uu|`We1Zmjy?Vy7LKv~N6;QbJllOI*b><(@o3=VtWQUfCb84<kV|G)
zs$useo4W=yr`VM(AUwmiqaCGGw(As>rLz^6Kzf#)Nz>JH?4D^*$z&%|1pESf@)m>_
z*{c+wyv$~Y!fqD(H+862*bwZbs~lI^lAbVlofY5VH_Tzz)6j8~ZBHxxT=pk=5O1-~
z`XRZ^`qGp?pIu#v++DVp9KUY?JNh}iFJyO7(7u>0NJQ;R*iXKPYxmiRQLy`fEw6;Z
zM{Ke?a*x?pG*PW&H{}3c<zQ#bL|V%(`U=t~><}&R^=$7{c=3!KOk?Xyw%J_(U$LoQ
zK;;d4(*=OH>~addeqjHi*T0c%Jpx`hb5Hw2=)yTsFy4(5E8wU*_vR3s*~FEeMB>4%
zY7c-X_c|Mfyf_C#b@JxEqp*b!cQzHtHtuI^<*K%G0e=DS$1RKj!k=54hGZw#!3{nI
zaD$TIQwEnm1l2yrT_1+z0vEm#!i!uvg=n+5=@dT9=BA#7rK?<NJvgs%v(&Jc!(E>W
z;SFw;<4dsRa$RUCn8$_g0L>k)nFoORTyvWH-{T5@fUtne*$VT;+;<@WmT;xCmG*#(
z-UHGy?k#aY;`C)Gd(5qO1-ybgjg_>jlB=i5M>VI%hQ6wXdm8}{pKwPf08q#I_jEv~
zp1U^@$uq9*0SaGm#k8;RlG`*E!q?oVv@`jJv;P8v@3<2bAbih#-U)0Uxn8t(b>@?%
zK+}~ky?~q>A5M?uMm~}@PB-yvHj>SJLoh1g$p`%gXSVRopTdGS?|h%d`?r->&<boD
zUrMnpU*3fl!G8R-K+x>u2RcI-z%R;x-Q9fg5#$2-A++=e;y*nBwqX7uwu@Dvyo06-
z`}vc!x;e-{qy8q0e?v3X2!72VG|3^ps~^fD`G=**Me!Zm3wZyc`QK=k7Q+X!NaFav
z9>TYy{9Wob6Zj_s;YA|<!}s7m!RMDFN#eIJL}hOC&eW&e<yX;0%RT;W8sLR|aTJmw
z{>Q1XTfz(7;Akmd+lU{gjNjP}xQF~ViE#TdpRg7<M>*f{4M;2bbJ;*t@e77RTFX!F
z2AwB-VGMHheEu@vpYi`>0{?<<OIsB$`7^Z2XyE^(&B)h$k1?p)JAM<Hf6veO9+hb1
zy^e$PBOgFPa2Mgx7Ld6L-(CT=yWpcm*+z%(8Fkto!pqap*(`K90HBw!=q^;Z2#@Qb
z<0DA_KxM1YiT2R83u|b0=POkGi!y&9ejIQ+gz)cx3lJ{opt4J7w+DcDq03|l6NKT^
zT^$#kE}*$i2umqqk}O0offp%)V>P`pr-c176rL9TMASl+D*WvQnlzyY&0o(7op!=f
zhTyjtxlAEb2f%sZ%aPE$C_G6<*(G6oEquxn`u+^kY~lDc<gN)OTH0L~9)1D9O+iHl
zbA=h_A-pBbq&<+^Lad`3EaeMMR{REcg@0zjM1c@SvF$=($^+<>2+NuwS1KgCqZSW@
zxov<i6FyQ~JQ8dpk$Wt})0kc%eDWiNm4e<4EY*UT0AY==9}#TT6X7-Oo74$a6G2ul
z^a@AWGvPvj1HQcwE>^?ROF{MxlGnn5%}Cw|9ecsxJ3*)h>3d-dO%NJ|8ASkm6y6vh
zbP)}-G3hG)ZGiWCL?tax_KM#0Bm|4ymO^EpIQ1f&2^BvKfEWA4jxjKQQ2dvsm|>##
zzsi|-JH*~{WDkjYYRgDbYK>f!IEB^;(c%kQI>m@lS+Eo*o}~%GQSn<^%f^e>cvwmh
z8Cnz`7mt1pl@p@9HS8vfZT($(njJIuqSk5RmTo9Y7hlorH$&`3yA|ieYT5_7Aa003
zQ(P3wN%OMkHVFo@#7<a!tFDOQ^O3tMZry|2b<sqVlpN8%5$0}+S8BkSD^}5OeM?;J
z1Nd$670pcZ#X}TYxGTPQI00B7W-LNW7K;BoK~;*yitf-U5r4&@DAj%O$vwFHK=hac
z?uVjpAY6MSX3}PVx%h%2cNO9|+TN%V6|}8dEs95w`yh^w0NF-q-~uFm(uT2UGk>Xe
zGkn@1dC)<Iol@Hpaw9;R{tVJxQXEB*cS}_lfe4gF7{Iny@~3UKAnB4GUIa_C_rRxp
z(oI_QhDf>OOsKS=Cvf{Ed3)pzNXt&aQn(b|06>Jam!|iT(w{*fi;_ylLwH4+Q4f`?
zlKX6mFkh40>50EC3Dm9TNQyp4Zb<LnAh{`x`3p&|^f?U&c~XG|$t|fh*88g4k{8bA
zsP0GuDKc3qEnp$MFFh|q?H@|N9Y#_i-DTifrBp&&(^XRPdL-3S3dL<}q*K_da;R#h
zHmlUIf&W|0r>%rG3yXnio1KRiZs&RmlJ-egQHc&k^HKMX<6A@iSsU8L?=;sFe4S%X
z0^23$40O6qYXwQSbF|;zeP;>$>cRDglRa}k;M!~X7hvdJNZSd0rjQeT9l=8Z>o<HD
z0R1ylQG?H8D_~&2r0tLl?7aYVgUS&`RSh12BZsOXX|z2uv?GN=hu6{O>WDyk5=Txv
z0G&}AC|3W)>(5|#w3QAlOjtGq^6$UO!u{eL+GJeU=REjb8P6}_i;sgbTan$v#OR?H
z!YrK#$}lE#DTI-XKmCTWj3Ju^9RGW<9^O#f!k(di)0;h*1=Bw47Mee7WwBVmAjv-1
zg0k)GF$$0Pvegu*^<xuh`r*&+@P`LG*b<5?>}0#GrwCU7tFS_K7rV6@$!^xR8%FoC
zLnM#}vHBhmhOjM;BNxj4Mo~t@F`Ur|2iOE!w}-Qjs2_=7Z*PEWhuATZC_Bs!`5I-B
z>}A@YielHzgBM5G^7*hE&6a)w&KR~WBggL_%cj!)N*vpr_I{4CzAI69j2%E>zIfI&
z3&I4}RSpx0>`y$B<Lr*jXq^*m_^-evv0l$1OlH^9fRw^U-bZqhJ^ve=ImNc~huf!F
z(GxzMVUtdwES2?rg(QuwNQBUl!FHgAI>)-|;b|tDMbr56tlMx1FR-tN!^A~4Z8w~`
z#ICG`-OH?75P;ci|9&uWg&o`#$yN5%S+x2!w!Smq*VzX+<A|y9PZC&eur~%k<tFQV
z1uD1L9OAsqx>Nl5j)V2uj5ME384T6CY*s5I_gEQiRTQutDS}hT9#?|2h}}izi`nzp
zC@W#7;<TKql&$IsXYRAXEy41Do$rmZGWJq2SRS%nDbDwZ^`DNKJ!U_r=w>;4omM>+
z>`!F2l65FffV7HTLQA-6wt*VIhHcRgg|)0;L+%ONtpw)l*uguHJY~D2!eBkSibD0z
z*wmr$;yD{{f}=0kALtaxOSXcx1zxf1>F8Sn+ocUu-m>c+AbH33K8><QwsI#lKeB5b
zv~}*xU9X1Jg<C~q*GBH;8E|`W)3+np%oTq?nHT4?5cn<Jr*v$|o2w5&nGZLOHZHev
z)zl>0IPp4i+qum@gVUD_+k~7S*N#R<f9`oH;5#@wJwZFUyUUQ<#U1sg(RDZX1^E`p
z%}R$;`?*K+kR0IV`NHl&E_?_OVcgF9XrORz1$BoJTr7{4J;bel4wb{)A_**!Trh=3
zqc|A_!;WydN8nR5S3y&o7|v=3JeKRc8Y*#Itqj7WTwyqNcvZ)^(UT#K=e|e+FoCmE
zlO}RsF9GRs&W)B9C%CC}vMGr>M-h!=Zmt?tOW{nRaP%a{J%#2eE`0=qr@8EYfS=)%
zG!snawBaaA<MjJrKAr0rjoevo7WG3J+>nR#{+;8(-BFmy{n7zWUEsFR4*Ny!(NM5m
z;%={o`O91+9T&{vvZ?>f=EmjXt-8W}=nS^2Tpo=V*SPNF;dM?k2f`d~R5es?aMG8s
zbd$@W-Q-+uSSeKUICdO3Z*htBP;uPmf+s-d4!4Y!0r{LOovFFYJ*Pm>J#Gyh>?`1A
zO$KQpS4=-;5tl(nBZ|2_f5Xud?xqFiOF3~TxbJgg>1f3RZU6;o%DDM-0OKLIYBe+;
zadi?jA9G33$dz-eVxU>!-~w$>t>m_!g;Q1Bm1D3}&3U##VGZX-D}`F_`VH89!bMZd
z)^UEdz(3_W1cAGr8yW+^GcNgi2%mHQ>2U1@7w{7_Uvl+*QEgXVqO%mc_~GlJxrguc
z3{~38AEYg^Ae?Zyk2IK{Nd4SCK2QWcgm>Emd???UB2N2xr=Q{B0lqVBgB|4G(})<x
zGo6uy^R+)9iQr!>LUM>-@FU=d`F8X+M)FSUkwoz}dee{am+3rEEPrGR5=22~!kMG|
z6o)Ia$M~7_$j9^J+QM!EzatR2M84}*7(C8jngE&;d<bn6CGl<3Ax!3@(;-aZ-TOlG
zB)_%-9-iW7)01$T524A;8UEN3_>{^Yib9gcN8|#Y&Ts33<Sd^=Q~V76P}4N*9Pc*@
zh)jOUNjP(!KSg8p1wQE|xG(YrG>yN+f0hW~W!_bZCduM6;-Hevf6@g%%oYA5jow%J
ze~&=(8b6&*J6z`%XTs4OJ~|RCH~8uS_$6=hiPPaIJXr^_JpNiTjeocJSlW2K&EKJu
zLwEQaM4He0H-qY3KJjN*y2t;s5HtmRA|1Fa<Xde=or?IORMBGoEzLYi_*)s!Eal_J
zA$Ok-b%sw5`3;jn_K0_)ZsRfULP5uJzGNhD75tWXdjBf<ixZ$z#V@4ivYHQ|;71Lg
zQiNPB-;#Ddp70Yp0a(ZD0+2lAhrR`%p6{NDIz8jptcLJ8zlP2OzTmIXR@O^?J&mca
z_&yUMY~a6Y4$jxSOJC&P@Nx~>@Gald2rnG(_<0nRe$Ou(fHwKS&%X$KBOinVI9M0@
zeFyW-!kgAmbrE9sg49)5cNju9p}Y=k?!wp|(A+3gZUN~g!FLi^JcRQ7(A+G17=q^V
z6b2rIrkBw87>2e8v*>7wx3J|Wl=(P>c60)7t6--S7~6yayMf;>@JrBMzQTv20Qw2K
z@leG=lIG(9!rb|=v`d)(2g-H}ffVr#6jU@t+aqLu0cZ9K(}*)j_=uB6s$gNFH<EqA
z7gHb%5q8nhrBI<oSHSlR4(V594+sN-VFGSiK@%p_okwA~U>}TXM+i7ekC#hGq0`NW
zg}8CZMGAlT!^0@SpQiOkgs(q?+tI>_KFGxg?P-l0E3E$>!Z_h*Z{Us!Ua`m>6S~nE
zvUnjc8jdCiKRIZclPJu{NA|dIa1?SU1j`8ElZ1N|uuc{Z(qb<~FxSDulfsI{5S|k1
zCV=#`5Vs$~GeS`$gsDOuwPBhNUXHSK!JQUsXN4ED!I>e1(emz`@L(sr$P|`P`1!ox
zwSl6m7liOAICW9*Z$NTMcuG&%Wufn3<g$c$R+z{Z$}vgDin)-^PF@$>Dfpfvl+Q&w
z-4He<fb^!&*cY0)LYNtr@`Poy4{}SGl?Z2U3(LJ=@Q(0?-pza=`V9bgh3uiUyKzq_
zy@|pCp~FEqQz(2wOTi++=^`pqEL=JSe2K8*DQZzF{P7cj_l3J&D0?9MK}TcDguD2}
zNA*xRu?oUR!qNn2J{G=t0+w<iU=&m;gr&!zQYl<+j<PBtmLl@i!Vnxia$x=a<sYb1
ztuTwWi=PN1e?+cM$oT=uQ{fqoPGB`|+zy&&LV5%6&xH)?dtV4K5`-^>5ZY0GC7kO6
z^9_QDHi}*gGV=b7P_YiJ_EuOu3xIb*+BuZH7asl$;Rm55ZBjTIg;o@c|0vuWi9%<w
z)oYk=5u1CVp<Km)MhM-+6q-=EixcCK+bI4>Ve?I5)qdFZ5N}bGbh9}A8~~nTGVSVn
zi(?l6;3Gc#8o8~aI|ajh#db8i@)O_F8qi-{N?Q*B4l#Zabash86j|6U@;^YjR}7)!
z#zCTUAP~Xg%|DQYipKdcv0r?@2?h^{ISbH0;o|Bn<RZlLwZI(`f01A}N>oypazt#5
zg)my|O7p-NF`EKyvEtSTppFx}(GudQ=vYk0@{fsa=qHI6Kg@=w3F5#Is3wXZ_k-rR
zSU`s_Pl(@8bSFv7=?Z6(#iB3(QpC;CNKT3a>4iNdF0O~A)1tNk+-Jnc$B;`E?>vIr
zY2sgxp^`2(`x@<gR-A5yN`~0r|6+vMafh~qE{Ho0!RkfvbWgOzC9%jG8kfbg(J+@K
zE}_6&w%Dp4NUn$>)Q?{kEjPh+P3#i^r>~2j)7z6HDptdzTygl9$mNNvMkBc;4qFcD
z+u|_~7`h`ar;WdSF_QL-?~30z=(yxP@ii@A3dAE8=oE?}v>GZBXS+eCSR6%Pl$3~L
z3SqZYv~>a7ebHVCzymRS6Z|a`?^1B{q1dM<aF0X{g}EP#2lj%jTuh@4j|y=K9mlH_
zwY0rlC0?WzZne0Nr5(;1@$z1f){5UJLHa~&9sppSIEWS!PsMDC;?|4PXzKq=>_wyJ
zbFt0{gD=E+6zY5_vJ^LZCH9*Dc!M~>9c8b@(H-F78*$KY0K65a(t_!oxP~@_--~Vi
zQ1(IG6-#4qqxjP&XsC~(p7wd1r4R}~xkyhs1K}zyc#E=)()l+KZjzQ&!-R*lkA9}j
zQV|{M_mmFg!%;8E+5_BMq_h#hc}x50%$1MyEiJ*fO0FuXY?G$g;mmgFnm5e*O5^{K
zp%3tr_EB)jUy7Om#184Z=BVgS$%O`$0I9YDc6Ui#X?Jb6l+y!t1Eu2|K(j~cMLQ0A
zrBn&<AZY+?AqPtd)WG|sF*89HB7O9O_o32f0?hB13VMV3fYf~fR1QktZiCPfCQTg$
zop5Oq9Y2VW@+e4oNP0?pL5HOk__PlZ9OsF!6eUG}K<$r6ad!cTmK-@S7$bSF0!^&c
zA_6LLQt%iEk4hyXSdK{xH^5T7R6*T%f^?1o_=!?$2AoOKhGxhmJERQSp-GXhKLhDW
z$@L79Q&M&@>U3Hf`v+*wNa;Cfi&SZEEZEYdTNM9Dm&Vh{*|XB8!GLE-?Ofr-Iq8l!
z$}*+89x!oU@(2Uqg7m%@l8aJGR{$<aJ||FiSt_B~RF>rM>;S*BrO#-6d__7$+*hSv
zr$hCc^gZo-UzY~gKqW_N^nw>Rq@fzPc2hb{XU}t`3Dm%Ok_&a!x1<L8)atgBbP8p6
zq~B@0%a_IsfWf<x&uXaLlZq~Yvq1W6ERtd=+_4{imq;s%p;{^pn~S6ju`LunlqR)7
z*(0fY9Do&4+bH-{DgAyBWmVERT2ItU?yF(&iL@*kxH{?4Bvka7)b48-d@i+&gXRmV
zEp-MjrLs)0ypkG>$TdjDL-6pe)cz?&l-^05XM^Uwlul=4K1dH_u+%7Rq>0x@sagRq
zoHdnSgWE+j;S6%Fnx*t^yJ-d-hFy2fkWT^MsG0vS0Gl*!G+FS_9H8!Mv*wpvw3?@;
zum+r7n%`fcY>Q?l9VYYE+`7o&{qxb(Q-FG_W==EUw`tBz2HSQ`%mH}nt2uuQCj2zh
zN`Ua!tn3bz9hzA`BH5|w;0|1X#<&8cyEM*W$nDl#=z}CsbFB)s-=j&}1o&Rf0Xo4E
zq#0>P60BK#5W;<$BOPgnB}60bK{iygfYzz|HPSx-9?<Oi2f~AzK9i6O(_ElUr*O@*
zuHcT)Y@>MmAx#9Gj61C9T?R)ZHK%?CJW4b6AnJQW(}hleL~EW*03b&5vNy_NH8Ux!
z8K-f%1I~Djy$EHF1kFn7bQ3jK#=&5cW-e`NBx_F5=$E3g9tGP;O-FnWqdKJ-egc}O
zH4D#y`-~>D1<F!2Z)lGoP4ll2xOC0OH6T5!>D~xHhNfEwSURU!A;Ns7rkZ;2^P1OQ
zsLKV-$|zX4=+KPl3;ZRGAri@DO(JbwXKAV_7@e(I^&Y@0no2t?UDdpy?Vf8IEZ6W>
zXmY24Ek~m}0=65PDed6XP0h?cz~yQ>4MCEpiHk<rEzO(1p?O>5;fx>cjwY67TKSqD
z)RYAphnY5p3pIZ9Toq~FAA!MQ&2Bk_C7O0Kp<1e0a283KCjED~_E57Iky}-*=9_b1
zd!q4JgId&SCX?`~<{S-U^_poE0ehxNN(1L}O%|O)d7(L32bGr^+at8$D^1Jxs6>Ni
zn_~ssc&*uI1n`Y!JcV7}Y8J0S?wzKV7FF*xn&n77XukU#Nu%aK0m?pVLTEDStUVkK
zfQ$Bl1D0I14s4mL+_Wtyj_R%*MZMle?Q=S-wMpCf4H6G6OP$DOZJi9>dusa>(hjGW
z*1QT*Z|#|upz+a0^#bWu?UX#U-Zt&7MNrwU{e@n5U#(>X%KWrWD^MqYZ6zHb+o9D@
zgljvsFX==@fOa*VRo$gM-4h0PYv<7}RiO5hUm)D0{e?a<*{ijD0+t|c%~=KBzhLbz
zG}+&$UCV+rL|Zuveurwi(N`Y(wSUv8(gWHvhro7F`<A|{3e%3D*<85x%6I@Gv>_wl
zcBD3R3P_{0<Aaeqq8(iTpQ5$hnnNW<t1to(tNn+%*Ep@)F654CV=>EdsE%p<Q&6>d
z?ZZ#uMS@l~9=SxV^btD8wb$@jgX)BK3XOP4+W5}ECu=?1LYSiMLmOHrwZBuu;FNX(
z^;4&{t0MtFqy3l0)Ku+I3Vo$%mu*5Lq-&EXL~&MotUp}K(2glbnd6-H%_(FvwKqdy
z;=J~i5AYYXPPA;isCB=KX1k>Q@Bwx&YwN>M!z`_yMwe_YPqV-)+WwOuysDi@+j-Zt
z5<Y)dUDv+S1CXP=rG`&8wD*oc^QLyrS~!}k9WoNaJZ&!z2yZ#GC+EV%ZSBb{0Pkqa
zC~}ameMH9&?rEd`f)@qa$fIB@)V83l!XoWFeBGfc*7m0(HYM6`Izd>f{UrmM_q7|x
zq1q3$4YXu0(_W(C^PzUmbL1XrJ!$P*uJvfz9MR6SL0GAE6psL+O8e|NXsWfXB_L|F
zJ?NlMt=5}|r6*cj3vkzIQ$7R!srC?shwHVMsb!vN)7}I3QhR|0<5$|<)QL1`TT|I<
z?JgI%{YG0!hY8+lE9p?%J8kATxcy$s_6P2RHpbx%(njs^A5i;`+HQxDIO}|=+1zx`
z>5D*jT^E`_Zq#khg56EJmmdK1&~cui*{ll-K+aR=d>1$`-HzF)(-z&o0yMpK2~}Y6
z(H)G0%2r)T1zhvh4W~7vpDrR1aDScqN_zix=vo%S#7^A}8>$_ktGN#0F5UMz(Allq
zIT>CA>dqWMvPbvs1IqU5iYN*aq${GJM6j;eKQOpYH@Ol9Lv+8n02iv;`XlV_*PYKt
zTO81hpqc7H-F7<Z7N%Q74@<a?c|u>AMd(JfgU%t{!yo_;>tq|j7O5*41l1_rB7Y=D
zbXTc?qIDfd!)}c3b|6$@b+yz^aXP~*SURc;^oEIJy7V`2G+y_*JIWGt(r);hsEegu
z@3?L)%>z&9KG_aHlCA`gheMUD8|nx1DY~z}1?fp$!dUor>OVfE>K;&MlBQcg2j<ds
z-t@?y)g{bBE<^Y90|4iA9q2rHrtauQaG%$$rm)Ke-Bc4yT+(%z3$n{P-%ju%OSg&o
z&TL(qYUHly-W~#O)K%S&Uqbb|F6;|rb9D1JqY-ZC-q1$&O<jlzY`MCDf5MAAofjS0
zxuYAN0K56Roju^iU0s5I&xvM-ek9tbNGH-4)5W@=?np{>9cdS=ROdbip550)%V6Mv
zt}Yo|WxDxgKtI&YD+kvj-GedEe5`BO4&&vzw_9MmLg%v{nw7fB0+dzh;^;T4*2Pw#
z4mCPEJu0=jN%xRE(cN~eL|Uiwcnri-oi9bv>veOV!lzd{^+y03bSo)1_FA{B3c@$K
zw$vhTb^Drw?Vau$3MaqUDKA6wgYF82cN%qTdm;BxH-iAqdgWfY=Axh224$}LiZqnD
z>HjPM&RxHtj2>eTy+18hH|u{t4TPtD=0YT1`fQqoZqW~T4G+Eb%V`SXqc16kaI4;T
z29j<1Od5Rs^y9vQGyeL?vmxA}H{L{DcIqv(`xT(~u12y;A4Ml?cI(S&A2d+!pqFru
z{?kb`joYg?;LL|ANbg*MBv^mD45Xp@uV}krzkV$T;Q{@hhk!V!-|!f@FnvfOl5l;Q
z2ERdsK6Mr9bVy%A@ruKGHUtJE^=fL-DE+aQ5FXJdKSw2E^_TF6QdDvJzSogEs?QuF
z(lDYQO3}1<{WR*P67**pVJT6+JsmA{Tp#~696q5h*$cKL{g&QPN!E`)hPFu2htgTn
zlllR4z~+?xaWS}0>+NIVQ=0w;?bD^}*)+88S$#bP(=+sD+Q2!dKPiX#OuhdKn01`j
zhYkey1$|&F3NPwE!Rc{TmcAFQgR=D%-r&BXA55>-RsFmB5MI;A(&YKNescx@IeLC7
z+Tw<O#n-TVQ@?>$;JJE3HZ=3}yXqmlr9X;Ehbmv+b`Ah{^*K3Exu@rvp)Lguy{sGX
zg?e8K$QJ2a{e`4h|A_*K68#zu6)n~0(o*)m{%Z+#ALub`;XTmzpzkOj>r-feF4s3Z
z3tWZXkqSViepM@!Rq5Bpfx22>Nl!wJe#A}~tkq8qNA8I}s1=%|PVdmagY>C>!d#Hn
z>lcWid8Ti;2fv@|*ZvId7kcp=gbn%=7Wnj9f0qsgywO{~f~B|m%s8;U(^oSPzSlc4
zko%x_r@^~XA2b{$KI-!$k#jYu=vj3$H2et_cf-||DBEb5<e(vWlVO@Kq#lNaH0j@L
z*z*X5o`#v-k$4$y)6`{)!Jh)7-i9t$A@ni)CPQw!VckHG`Wi0N$8Uaynp}9{Z-}Hb
z1v?BPEqrzwdQJl%z;KB+*>@SbP;hv+q30RE0}X3d(K2d}!Aet~y@m_9(Aj4=-+-!x
z7(RIcV5s311zh$Uw$py*0YgW61P&U~Xc-n}Fw;sa+@Pg*B*Jin4j&vcG;ajwVMB2h
znk&*!O!JXwgN_a`#u$bbKp1PNrqLwMFmXGDGLIU{XoNgw=tFzx@rLnpz?NVbN(Z45
z4UwU!T9RQ0O*)bdUr-Py#qeknXiget6~VPrhJ*B1A5I%8Zy<NZaJ~lIsRru;0MZQI
zFM>MV(EcYRXAQj-P{}Z4H?6V_E5D%k?}B00C9qvI{6(v{ONJiZVeqoyw||gi8Qflj
zCfl&DAAna3e|-wqt{T>jgTZTtJD;FV*A4k}pgqShoX)Z28aC2L?s<lTk!XZlhJBCG
zB)1JSS|WGHkkt+<`G!6eFTZPOLqQnFJ;Py7uoW2k&Vf#$;n8>?iVR9`&=ebr=#>3^
zL$VIeJTUx8dw6Ar&uQKD&|vTd?vWvY&U-&LoYn(SZkR}2e}&-<4XKre&Tk>CF?>D&
zO;U^If`uoBjWj8%GvsuH%2S77=D*0+8#;{v%`=0qi26P^tn&uqg~38A)0c*`w59#Z
zFfJXgH5hJE4c{7mrAYZZgYIXv%zMK-7vMe^2CPF_qoHUlxIY@s(GHih@fy89F2=kH
z2wja%^t-wlnQ5q!yV2pqqj00qLX#CwW5ajAdl~gC%x^Kipm4OeaVb4lKE}bzf!}Ie
zNEP)p{zEH&KjRDv3;P=<cZA9gV?iyv*lGNkdbR+gH3Gt2#sz&qw%h3X6Ep*jimrg~
zF&>@{vwMx>9aqt$LB=ce<^&rz&`#GrV?K2TA;!*|kqb2j(|U8iaaj>a4;Zh|MD?KY
zGJ|#wGnQXPF5Fl_<4J@us~<EE8PA<Ua@aVP&LBk^Uz`Un$~f){IFA^6Q1m_8cv%Z!
zjPb=-2Y|80Z)qVPXRM-E^{DaaDEM~F*!o8#@kTcqF%yiXKLDR-)Y263xN)Ea{0ZZk
zVE`l<ca)+|$;O%vC`&O8^@H0djbmI;?NdhoB}h&iAFH8q#<+*pR;k7%ok5mn^jJ<u
znbM6_6ofr%4Ez?BGK}wrK<AusB5kQ<8mp;mIB#4jKzPCE_cgdL8khAz?vgQoIk+zy
z)vW-}GTQzCAloR*MA;RiC-o&)jl1`uzSoSQUxDSi@#R0TkYjv#2!I<#2>~gG>ZVao
ztD;=vhsh|+Gj@A{<d$*Z9ay?;GzJ2A$M~Ze!hGYu!2sShmM0*0&)DxU8o$7JmbStR
zjqe{ov&i@l4co=WSHx0cbPGhT)VS{&oVjoO;!CJJFy`h1S7uBe4Hd^j<McX^J~GyJ
zMB!uOR6>*+ErXG(G8RsUYPIoS`u3#8XuJ=fYK^ZKB6(ueP=8TpOs1pCPmQbSNJzbL
zloGgS#yd2%d~V#K1KA5>|9!CV(zqrC245KmzecXX_z#^ie(f;Mj6n8{vHxrU-x|+u
z1=~C0*)cHq-q>$HbUqjl{sHbr<LdXoe>7gHM17r23pDseT})0C#CJ8t4F%54bcRKl
zyUF-3a2rh>uufHNGCgR7GajZv6iwW0in<H$Jx$+I&*Wut_}&G6i|LCm;DxuTqyuPt
zOl|0F#a7eA-+<p{TJ{vG+fA}W<a|wk_k*K;rWpGB7yhQ#-5}gyDxqo0PSc!JzynOb
z5$7(GA5BVko7^b67HH~BtGGR;0~BN5Yg$czHYCXO+;I^2VAE>a^4Vu{qUl+PsS~XW
zLQQ+AquFoziOvcgFp0j%9W-T8I55og4b8H`P5d%cEy9!$jNBoU$Ct<*HeICvZKNr9
z0Fo%v0Qyw!h-oXmsnMp;1mt2&Pw9kJtZ9~u18i|7*S9D<Y8pume9Tln6`sbM2GGV}
zf@$s=v_+!navivjo0hjia>CT<3h+s$!@FT3+2rDcT#CsMh?YHRN~i(+lu1Yf^=Z>Y
z2`pz!k`B03(+T<<GtKl}K5*%#f$22=JZD-?k8Y;vGdh@e-n3{e3|=sur={UVQ-|Sj
z?UL!(1mrH8deF&~ER&f7cQ#rLcCVP0Q7rYUsb)R6ubKKZhZomPF=vs>F}<g=XE#hw
z>4Sxvrfalz&NU6A@K&D5gs01)x@9s_{QkD7UrRLN9n(vS$>f_FdO+u{sc0o~_e`(e
zB3EE~L*ITCnyN5xs)|glX&0;5q@_>$N=!dZK(5qOyBY@Xo3bY&_rR3-5%4n8TQlGf
zP2W;X<dLcTI~aOwdNLhlj&f7G_8_e=or^+JX)2<l%2g)$m+-0Dltib_YE1X(s6(x(
zC;+)9rY%p<2z90}W8lS8(?4CoU2oc?LnAyhebyN!o|}T`W0M!AE3~ip(!?G>^2*dP
z0m24TFda2|ZJN~@$s331JgvRon%1|4&O6gan$o{F{SXfKKbTsMhEAht<v!T`XqrSp
za%c16YcSzrX65k0)x07F05|i39Z+#Mw?6^gMsxpPpt8v<^MZ<pIi417o6R*e!S*!w
z?Fkky^BXz@vc>FRa$(-v+_4L2e9TF-`M1^l^*+#SGj|({WV^W^%>#YS^XV{$pLyhX
zsQ8;NZUEa3^QW}Ev(vnAF_HlD+$m_MU1pBv+q=zEmO?Yo?6MI}8DwsxJ}}rkqB+X;
znK#fA6k@*XpretY<^y!hZNK?u1f&PdarNLnXdX`wRG7KjI(QLo-o=4C!d&weyf|cz
zqh;h_^M+=y8)=@g2Dm75R2s^TnD^37Otg8W6)G|2!4z1EHFrCST%399eW)BY>#6p~
z%(^c0{>7WOFNTQ(b0|f06U|d-rh6Q10mKROZ*g!Y$vl}h6Ozq8dmu?MFYW@(ljdaF
z6gXuLyNDW|Ht$g)Ib;5nN0MrOk&h(JyoENg)6HHKkv(g6{{TZ7=1yi<IA<<$5%B(H
zn%~h$;`8RlC=^~W`}crv7tL8VATF6}_u==sZ2p!)=2_<QZ2)GQMGBu>F~1oE^H<F~
zX*c$o+5Q7quA5IR1xt?EIU30gvvC^Q_olfGg#mNTL3Ac6&)kxhC%4SD^ECgwZSH&#
zg?G#yN}-x>#!M40p7{<f*YBAvbP%DyTt^>g7n*z1VyDRLLr+<;IeHIVD>2v6%)ZpT
zoj!%UZ{GC?We?14Gm(^;OTyvkL$jt4xJTw>+8ugqUZ(}F+`Q-vemh5ndF?e6R+`;t
z^SsJzp$SU0dHpk})|g-8i)~e{xui1?Pt1Om(5y3`TmY4)=8o0it~ck=_jk|CE9sGc
zW$sEdzXtQPVSv9j2h$0FH)eYh%HEotX-n{(xg&i9_};v02<&}un6Gv~w$U6#N3}ni
zyLZR$>uj;*p)xL(!@nTsYPq!$G;WsWTak0Oq|w4}qot?{_)V61n*sN*)IWhUn=L+H
zquQR9@pPKP%VMEJ!&@vJ&ZErRvTrEN`&e$%9|YQJxm$qTHjASlosrmXi6L)%Eg`f`
z<7XL2^Im_;Y6_k0uqXmiw$rlo2FwRo+8#o(%ktp{aJwzvehW*1mSIz%xySO>8@auf
zzi7r8Wa(=MS+FIU2DN>bi}6qiu{7R6Jwq)cJW#gZveL01YzHjS^pYI3)X@kKW*JU>
zceuse2e}AKyKJZ)vb3V8(_u?%no~zwQk-BZ%JMf2IY%sKBcKv(c{KwpF_!kU?u@lK
zKSUB|iKbujsHHb;A|A68xWSot%VRmrCRm~;Iv`E7%#lI$xMdf`Xiix4G?z%SWM+UZ
z*^<{CDk+vtodG;)888z*owB6=36;~9l>-4dV=*oTJk`=b5#2P)w37g&TdLZ_wX>Gj
zD^ZqVQBa8goW*wwa+#Jg6Ijk$_}vsnykIGvfy!L8RMUromn>Bj2)}H}$BAiGmL+8$
zyvVlX(r)J!OX^;jxM~?j;q+@3Pg+)8w^V+EmdUZ;s|>txmfwd%c+>LqI8<^izb}F?
z&r)&(Dz_|7GL+?8)@+BNyOuJ9o*k-t78d~y7g(Cn=l+G3Up!&H$g+19gvAy)Ei6hb
z2kE&gwJ4VWc;Avv$J8EJZm)$;WtM7+2|cv<(dny4md?Fl>9OS#nnagd7G$EV!t#Kq
zD=lw7M_HAnh)z0HTNZDIilfFd>NtS47M~eldtwo3F<NICwg>J%wTz7bqTW(Qd*jb6
zjUPbs+!E9XFJ4&m-+<<&rP>MbSC-?)0B^7a?L*mXOV>ug-&i{0SfA>x<!4V=dS^L7
z!PobeVYIXV!7_oK>PClUG}YpxWf-j?oUJ}K<Xo%^hNHf&)=8^C<7Rzmgk5**{Ff-(
zXgziYb~jlks9?#%`U%xyvsLj3+@97>0$9APPrm_Ri**QnVB&2Jq*b?%HIEK7Y_+zh
zsN^>5?F~@bZgnhuh1A!Ybrx)XRt*g#{?-=jptHjoLxG5$R=*t(23UKQfP0rUIvM77
zTh~V*7ihK8dUubtWieFtS_`+qQjk^N9hQQv5iP;F&w6?zEQDB}JVP$jx-J3m{nkOW
zemh|8=xB=TS<7ETC(Js7&e(@r-RaNoL|EDGFmcG*<^xC%TYYF-H`3aMx}+%U96MBw
zSYM7pF53Fjr>JO*HDe`6W35x(fGp0M_Y(j|tp&8aKW4pl3M%o|Z>NJZ!TL=kgo)Pv
zpE{s=-0HUh6+L0?^$a>m)+rQwK52b53&|;~i30Gatv<I=cE(ynT~exbuYe@Y+KPU(
zbnCY?K|gE#o7U$UR-+TVIA>is4oRk!vBQh=Ry!R~zF<wDK+#2O0saWC>XOy7oW{S)
z)|{5eW?45nqiM3O)f9BQVm&bfxvSP~bY||FHI+`dT(_En(H1$@xL@Gf4Qs&fD7$I>
zo6h#;TFWgkpJ%<l24%ObL%u+A+uGtfaCfW=>5q5jTYscaiSJrp?gHSRwFc`jhpNE3
z#S?{vR=3met;pKRA0~>e#+Cq<SjS%gO{q0uF52t9HFQ3J53I32z;2nfxd6aJs|T$n
zA6cJnfXZX*E1DsfTOZM4vclS9CIFSz2}_ZyvcBC7m1^rA3f<LMPpOeOYOSkdfp}uw
za|5JxRts$iJ++R01~2NZHIIRKW_58w13kA6qP5`*YeNo5Ut0H|`%t~Ie%>CxPlHuW
z<H&1kufA~Rjn#S)2H#p|)0d;~tVeQS;k|W@3Dh5~>O!zIT8sRk^3h>k6Ny4++k(|7
zbg_*d0~%M`om!Z8v;Am7&fONKLD@#z5Sn0Yvdx$VfQRkb8CcqE`#BfpJ#ChG$a&d>
zWAJy2t*kW?Z`+F5!1>rJD89Vac7oPJ+iamX0N8Hxy9;Vxn?p$(LVmXSG<Ea0&80=@
z4qFV3)H`kQB@hPKa-Sf#%ht0iOzgIOH5m9n+tVbN2(m2?LM?)A5eDS;+1$DU5Mo<V
z1xG_|_vlUCZ#zqYgabB#j#V7Ad0-b_6=rKioqV`$y`u}#2-}BH&>XVOkOO$w*47!#
z9cjy$1hyz!2MzE?Y(=+VBHA`Yjn<2?^<R!8*4CN!gX3(|uYu*L?T`U1$83HJU?Sf3
zoVwWr+X7$sn`qm=5y^3z<`e)YY)N^5C)p}g4p>UIeZK~UDYi8<c{yqOiI(E0Y_n<8
z=CrMD8&uBNhBpUysx5~>F3q-@zPU=bnU^3rYr8%PmNINiG`u)x%UcIrrp=9dwDY!H
zii=;ceL4tsFWQpgP<F|7ZYy$^Z9XgL7+01pKNY}i+g>_hbHx@J4&YVWxFEQA&34HR
z+}Ca0zlYr%+c&fWe8YB%J{-Sk%W+0?<=Q^|6ejX)J7|aSmM!TD0Jm-V6jr}u^YevD
zzHRhL7`$uqq%RWh+1fsV7X>!+9GZU?+8XGO4iwq&aS>iT+vWW*Ut*g~A4ZhgSX%bp
zw|$_kkq5RnCt<0~wlx-jhqfQ7*Lq|N%SPE_+h_BUl-m+7qO8I;<13h`v}r_CqRJLu
z16;LjLKHY_Z0Tvh)!P2)21AY~w)WvDtg|g}LH4Pw@&VeS-WEwO&@<aU`s)bKZKr8w
z|H8KR9h&>4?YtbxE87745iV7O%{~$yzP6qG7Ixp*cF-|{x3<1LQTEQ(n!coLv~8P%
z+(+AW>PemLsV!i^#r`RMwBYKn`_ZvCH~WisFz9Z_U-`hRW>2AT*(Uo21xP*YkC#KZ
z+1`w{nLO>03jy%5H@^&(E%p;nVbI$?n?9TKu{X0qWviW|$kaA_K!2FnZcmyA6<_-w
z-@pq$d&WRi*WcbV8gB2fJ2bnI-Dy8ZE8GCPrwU%|vZv05!QJ-DG<yiNFQqR>_SkQ<
zK(+VUFH<)gWKZHj8f>3Hr`Pt`7uaDp#J;8gnxXc_(ZKDuS6&3m0sH3_uyoL#w-biK
z?2ctf!tKQ!pb}yK+7Sl)A^X&BNDkZG=xkY}z19Fklzqes_;kcRkh-mCyG((y7<)fj
zYsK1+QA8}xexHX=N9|+i0PQh*msP;U+l3Ga6YNV|&`ybVf&SRQar+87m2tw}hdQAo
zd-@#IGua;U2mJx26#G~2fj?<~HypWB_DcasPTNO}MRLZz?g0>~_EWT!NJD!;Gu_^{
zFOswN0kmSvum@a)hv)2H{|XbC_Eeg7pSP!Yp@tXi&5y$TMf)$bNp{J;rW05$+ckMG
zpJmV5!jHy_XHPALr7QOFp<uge-%s_uX3wUX)OCBxaR77dJAIJ5f!_yZH|^iQMRVoa
z&-{+EJo{DutG{+~WYc%I1@_Eqpf0o*9e`qyou2}GrS@ZoVc@<!hW--G1AFOTC@ZrE
zP?YPTy-zW4kL*_|X7<>=pE{;;`#L%fSYbbo5mHrYAIrd8mAzjPa@F?q`Eaww9<mI%
zTDy$S@jbD(ck}_i&hB3f?x*(q^a(<}J#QO?&+Ilj{QunEhT<15>`}Da`O@B+9*b9Y
zAqq)@JwXd+UfVm+N3Cz{Khj>}Tl;YOVEdhY0j-wb+q?K8`Cy;s4TFt#6aBS|kM<!n
z20J^Yub__9#pyfRJ9Tv$Nq=6$&FK%C=DRz^yajNh(>WR;H#yC_jH-D!dHch)%}$jI
zQReA1g7z!Coa*SM*y7|#(?4&g99qZtI8FNumbN+#SOd;&PTz~Lu-$3oA4q(ideJ#-
zKd1l0(RIgVS$%PHl$KhK#=H04i(F-<mZnygKW%Gj!^|?Xva(*;L)jprvSf>cAs`BZ
zfT#=sK|q%5B}0aQvVPywU*~i0J?DGQy}ZwT&OPVc2d@yi6Xwg9F#~9R49nlZ_Gf&u
z4Xxu0^SgivU_`b7^aR773A8{)3l%P%WK1>y^c3S~x;}oI5&aiff*AgE8VY7i!~;8o
zaZm(-P)6DaT49XgeHc5#@ckL;!x@<k&=A3BG}E1wNXA9V(nc}frL~A=#1sH6hH;p7
zq*zAc&md<Re^7N^9HV+KIL|S<b^-f5W1M`Y3k<<IsJO_O{y$hB&-f$;DiRpZU!gOR
zQ8WU~B*w~}u=f&UlN;7BnPFQC%oN67lzq3RGA7C~c$u-P5Y043Nj(OyFfP&;9<DN;
z=|*Qd!=7$<W-#7L1?V-#Iw}s#WVB0QQ#Qkk0r4EhhTAYZmm%5+mKzN9ZLs7qLfm1@
zO@<$(xNk9T=)rQEv6KRp`Hb&xg0sNNm~w)Ng^a6BSj!@YGi4v|Fq~>3QOu}W41-G;
ztLcVVDI=AVpLZF*<wI{7<G0x$<qSUxAlzdN+QGsK#`Df#sbtt>0=tT#d=GN>8Nbqz
zznZa{YEEkyd^gxz%V?#Ha~;Eanw*t-#;<h#dcg3y4Aut5<qJS-WH@cZ?3);kAEC3E
zarH4IS{M$iF|}64;YqaG7|xW^Z)f~Nm8czzM_LGUGX5xq*<FkxiuOKaWHp0yGd3><
z>0#Jj14}RC1xK{{7%yAt)%b`pGaaO#VfhrA1{eWDFlLaks}P_=44)BL_?VGKHI>5*
zI~$CRFv@R3{U~FC!iY~8b}}e@%8&$sbBwV~fEkW6HYzcR2}Y&~tx3kk`A|5;cy2v9
zk1!>4ptfbof2VqMJEqevEVn)L3p!9cFcawI?Z{No1sNyiolZzNGa2L<xG+VnFyECa
zrvtScGnFd;jxzVAg5?;qX*<T;nHix_=)vqN2AC(ah+Ya_%o{c^)SEenihO*S|9lA+
zUuNH5`0Da3Kjsw0#r&DCQHt(3GwUiAA%NLQp_LQNU6kqyWa{WOa+3M_G6<exZv7su
z)6AReK!TV96r>Ag?xrL}2-EQtTA|EC^co0b&Z9U_1oLxBvqUoYkqaNi{3ZmgXy#5|
za%5td?@?4EmN|z3+s-n%<O9SppQd3>=a}9s*mR!BC*SS@bBjA#7n$RKf+e1Lhdx7+
zz)Ys>eIhfG3{7IDP@3fu(~Djz$;|6bKuKZl_!gb1%#|`2bD8;EHAousB}%hcuP{d_
zXmypjb30(tnSPXK$zWby0Ksd_ku@Nh%xobn%wm>SVo9zu>nSFh%?zSN%wf(RLo1j0
zvoq#&gUNCMXCCu43IN<>n&?1%i}`IfTDO@$1^_yr`EUxx6fiw$*DAC!chgf@#8lnJ
z4DT=xMna;PnXLqN3DcRrbydnd{s?1tnKzlxRK~ou2r9~%Ybg|bkNFNgh80YG3FIo7
zQS?fzVm?QitNTnHMSH86nXiM?Ftv0@sAbA2l2ykHB$u?FY4xGZ)dOaxFIKjJ$)YSo
zBXj;)bT%==2cWl^S<nU2!d!G5np&AJ&~^Marc)D0JM$a5IMu<lQf|DHd5mhRx|k=#
znBhaFeE?K+Guy~F>tSx?qSecMi4N3#%r~jn=n->=^*O-wGk4Ovb%43?Ff<J^r(S_E
zL(DMB`95Y|qa5ZiGoB8ZBTPd%1V))(ZbIt`)94DAr%atI%pPOfP*h=@*=Prr3Ffx-
zn8YO0XbbgI%x~;Lj<C9EeQjAM(xK0e^~ojL^X*w<+hCLvYac}_omq#TV9<r-=?Mu}
z*4=7=y0LB?1lm!SfkG?CSgbc7=gu0Zlcfi1h@#A%tR+jp;>CJz4(#=2?WXgh4=a(5
z(7r4uI@bHK{y7e_{aKFmiLT?U^!b#?4PaU6H+zEh9G!InS)bA+r<1G&N*HsB_2LF7
zJk4_a11v$Te=masv(iJMB82t*MF@nlR;_?Q7;8RmV$C|ka@z`laMlU>a8CrQnTnhu
zStYcGMX_ek?h(zpmJWd!Ru$?$tg~WSya-rxmi6|B;E7{>NnXo2mi@P|`#ftGt@;Jl
zn!g};kyS_)GV!eVbWA3JHFF<SB(gZ!AW5u4bT97`E20^k$*ec%>sBc&M+!!!vOb|`
z;$_xDa{tm;9`qx<!b)rer}ZjJI|xnbtatj+o56ZQA)#xmxwNlmvdolG$zs)vqII41
z`zGkkW_?WCT@GvRQ<$C0x=RP@8>~MkfSt#>Mb6Sqmh*0)++wN7XS&U5djl-_tfN$b
zQNTJ(Pk13K<0qgLSy{8G6yXjli3P!8R*4G~maw+c0kxF19Hm~f?y}nVKvNlO4yE?W
zS-SaPxyPEb4KNj~{fEF($x2#=u_{*61GMh5Ue;jt)vQK3z|^p&glN^WR!}6Xjx{RB
zbn97@bm#Q}%Q`_7-3_dTMQAp%y2nA9SbkSPnprKYfY!nac?6hNmLeB|9jxsiqqCF6
zwSsi9-t9x@Ll&F7hHlnMIzjZX{-%4Py{rfdi}kVg&jiaO*0ztZ-2JRKzD8?+)q5TS
zgREX_DR_oht{=g~$E@fMm^jS(j_%%#u!iZ5{wQmuAJji#ZF>`APg$>Q2Fw`i`g*X8
zvvS}<&6;36ORoPUOG`nkDOR2>z>cs*tsu7S{pGO9jxDptl<e7ySHd(0_MK+|?a2OR
zk_ri(*zr_1=FI+(9zz#)&<zk*cJmr2bYst^m&{SNoDS5-*k8U4G<WtZB@pmnZ=?gY
zC%c&i7B6-J<xsrY@6^FGAGSMH9{RH1Ee4n$dmaPE__N<2_w_h?3kA6Y*#1>?kUzoR
zLfcj#do3mWPO`81z_wHD@10@VY4(nfp*M(~_XV(n+4^|QK7_5IV_zs6Paz&W_T)Im
z&al%cd>PK}jR1*YpOHW=lATWvRTR5;4xppiQMAFtum#&87t0>GMqivf%eF0m`Z)HI
z&meJ*opS`(=h>_1419sTi)s!pvZridQ#@Nwp~3{VJ?$xp>;-h7PGaW{gIr?UQZOZ%
zo$m)tDeQM%gr-#XynJw8W@{<WpT=&#1C%RlHdRnuWlJeMY)xlBN7=Xx_WP8Oy~a+U
z`DU`uzlp&tw*LxPah+XBbt~Cy78OY6u=Ss#Gnd`B3urgk^XMg!$DU0O*G=}}TG*S<
z=GCCHfX$^lNQLaRp6D!M@8d$?4!h$B#EaR^x6vxGvOlLvmr}Osb+F!LAN7S`8M`3^
z66NgNCRlNg{qmczu!8*u{wu<)N_IGvn^v(e)?!Zg*`JbES<Q}5!&nV_Ul0Up*<3oq
z*0Fo)prW4bycrrEu>YdSc?0`%I@mU{%bA!`6Wb~s16nitB$cMMu!qU{Z)MM3jlnkd
ziXUK1J9|t7><;#4<W6?7_t9<FE_Of`G(BYd%!fcXTS!UM9(Ex`R(sjcF2`6OJA}^c
zkJ#(8fYQ(YavI10dqoIP2HC@WXc%G_S{DHAF}r;aR1C92pNGT<`;)EU8D+mW8)#41
z%NxP+lwD08_85D{Q^1U~-_v2*6YOnNW-!SX-vyase`-MI5l)8#1Z+7mp%Ad+bdSP9
zd(Nj6fp*|LJqEpw9KRf}IB`aOtdMZ#G}E<h7tT1vw_G_deF);l=}JWBQBK?}U?1bG
z`v)y|&ZG!q9-M{q(do%~lm1LzoD51Pcyoen0qVnf?q3jJ&a1ni*N>AW!s7dLTu(v$
zan9a!hzD?*sY>Vsr?`dgg9LImwPU?ba$18Raf<VWD;D82r)><aAP#dQB!W3++7m)J
z3qAx1<^1{>0%4pfit3%=d>8}u;hfFqU||HO@i{C|B&YHW#-cc0TQL^R*~S5h;jAFf
zI+k;ojj?l_aulOjXPxJSQ|jpgr-MQ>7ddhYqQ-MZr(vNII7{=vn#i%CYM~^Kx*PJB
zIQUuMQRB3d^O3@N^#LZ6$~i!vG`q~%L;348&d(Jv<_d?i6D(IbxA~Y-I_KVxz|7z%
z7X#%Qr;fZ8YbIy+*AUF&{6Rj<b<QUbfSt`5r6)Fr^OFZ!xtuK(7`wp<`~s~!&Sz9~
zaFY}NJPf_Xaic3Xw>d-fYR~7SH-WQ&Q$-=2LXKl11d2FmSE1<+XW=bi7IQqSAXmZ>
z(5_W#<=AZky~|;iqqmIn@HrS$&S`lO<Q|8Y1;GkV4}A)ylH>n9^j2|v=>T`1Gej@?
zYR=0PI;i28mZ4S4Q5i8-$1zbIR6XaDHjoFL)Q><KIGuFKs*%H{2y_$YwHIJvGsimn
zcSy8w62E}LR?gd-U~n5}NhD^`&iP|H1Uoo?lMm9#`GX>>U7XHDXnM%;tp#T{$JPbn
zJ)B4M6!&sU)oAr`{3^imh_lFmRzF927SkT!Y+4V2LC#$IbjuJY@Kdln=Dc8~J!zO@
z?+#5Poaz64(3I1-59*(Aka5O?$N7~qBV(Lrn$a5P?4|nH3C>HIn8hS#A-y7}IOUO0
zafJKsJrG-N1v#vC+!Y64lRfu6f3P@k57IH)k(<fHw4J!$)0XedZF!H*e=gkGYM{At
zS5Wzj8+RdH7d*-hqZfe(m)C?@cyeb`v7Z-LeH1X>+}(1>`EaKwN$kt@rSO;^x62*^
z{@ii8X>gqT<ZGY=aJSNt>jc+<?z#tZ|Dmk?N$%NTjGf{ZeMA1|Y3^q=FfoXGU>H2X
z+&vWc4B@^O0h>a(4=JV@#=S>J@iW|iK0qs+`!oesL~x&71A$2HYKluoaqGy>h~_pn
zV=RU%p|Er;_Yz(BKg%7by)%xRwhLyT<8E>X%6V>k2fhC;aOW?C!56tgDpZT-zC)En
z3EcTt0Gh}Rr^hgf8yF7xOWY6-U?+1Q_+TuBo45h$Q@NjO0eYGH{(Z2dac@#V>=o{7
z^c-B}_R()Wo%^#NG-PnYD0^{@+rJKqGP!ScLEM_f?cRvq>)bs0Btka#`+ATZZa4)=
za=A(5y4~QKD6Wvl9ZkkM-{dAy)y^%hCvC{Lx$A9VVLms&2?7ONmtW8-<Sv!L&?4@V
zSI~Kf`+zD#i@C*>kSpPSL}8;+?mmBr-?ef_>DE#icQb`*%DJPn!E=v0pKPk&Hn5?-
zk{h=fELB`K1-R~Wx3^%v)!Z9&+rEY?ri5%QSLOz^I&L2&`s%r_e2Ufs?zDF>?FR1h
zA&56}du1@KiEB$|=w|M49mHF>R_mKk(aQbjEO^?u1qNWZbL$<jG#%W-q_C5V?=j=S
z;|2@B@{oJ|Q*?H7x6xa?hx?=oW<TOSh(%{V_v(M|I4+-7c946SKJPHZZJ_weV{UFR
z#D}^2KY+a>+=9hm8RagsQpEHLcOm(hPr1L5Z#%~Q{e37L=jvKOCb+y`pkk8y!yb?+
zZs!|dIl{Y2p+8&R@M6ruj^`5!V$a)L3={`mN<8Eoc~_r-fD_LF<vO#Rd0hvf*M;{P
z#hhJvQFRz|<Bf~y`8&${-$IaMyk~EMxbqJ7W6*<FMKN|y-eUUAdGW$21n13LOOB@x
z@3TeF<jc!j0W?2e!aor3=dGlT<~Z;0U1$p6oup*#37)?OV}ZO9$`_pEous?Ur+8cG
z(LT*vw}-yC9K>s8fhU-^iG1o1-f`N3LwVPhp%un!SdFnWygz78;k+>NGa`7eP$fhp
zFOOdIQM~2k`9<?sl*^CdRa3M&mN!7(Tsq5(`vexo@nm%7Ima8I4BvTP5`|_j@M7_U
zu+F;3J3v{4c;4V)NF?xLsgx&?w}i@Ol6W6e67mwSZ!WAz=KcE;^rrC620}iSw}L)5
zbeXqg6Rb$%RcK+w72f7W5V*>F<p4CL^PZUj=nUR$D!{+SJF*O8nLKAY(q{4a<c(Ud
z^B#QxP1(F<xscD{mF&Pob9tpFfqjEF_XK$Ic!Jd!yUDw{733CAK_wTrd0oRm%jcE6
z1MC7`WfjH>d0}VKD&l4S2o-mDN;Oc5d3V->+~tM;2D8g}$ups^oTsFspL<rGE&_rT
zJbOCRR`Q;HgTX3ZG83%#dD|Hv)x1-5R;%IFQvp>iPnHM0b-bH&owJ^Ih~lmfcyUxy
z-M~}70qYxi?<j%Y#QReL@n&At5{$L*dT48C<vDx~mNwoWDUfUDSzo6tdIxVE#oRl2
z8^}%S;#JcJz8>;E{Rd;+Ja6)JdwAtFK<njYoCJ0s&+cysJmQ_%2`l<})@xuH;AMP*
zu|b|M-Ju=gRnhO_G4Cg`ewcUVBY=(YZtno}DDM*0Mn2)qwf=$mKIOf?7T9CFa}-7$
z=e;b2!~~B=$)ZVK?+C~g@63-tJHmg1f>^fv{TD#&__<qvX3wvuJf#CaWj|Vu{ITt@
z!impY00C$IbQ#86_;U`xLRY>=EWq6OJzY?AlrK%ApxrUPhFp4gey0Eu9{f{rQ18j#
zOvi06ezPNpH^2Q`jQQ|ix&Z-S{vEm?<;S1?D;B|@zuE+2j`J^7g9Px0=-EEOe_;v6
z0{P`G5I@OZPvvf>_zN~;>@;8fK3YNiks}oU4Caq-18WH1fzHdJ{Qi2h!uYo5fp&&}
zf<n>Z{11#!7{Twn50*&&*4>y)6kkN1c{IP`zi<lQL{C*L|J!Fk&hj6f!6f4N@pJ?^
z$1kQ>{dxX!n#%=#-Wyn_i~J&lz^$|5`7hB)HG$tkVW&&{KT;r{%rBz4u@wHUN|03k
z#U8L+=394QERDaJp13Rgc@%=X%Aey2>~#K{7LW|SeLKiCe%E_2JCpAp5A|969pnsO
z=P#iEZ#LhPa%(w!F$ct&%b$A}bGpHAp92+neBSGjxXFKG9OM??W)aA3{@H&pme1cp
zADJoOn|=d!A^%g#auxAgDGqXnZ#@Xpius$kXqE7%y#&)r`B8K<z03Ee3Zyc=l!~y+
z`Q1-I?(y%v4)qmQ{y6>QEBXFEWA;`2H){ZTpZ_Mk9IN>*6q~8xYw2;S<wu+cspGTA
znXc#0ScQo`;QP~k)dv0^3Sczyb1AIf#8*@8Y%|~d3T$fOSLK4V@@KAsTpNGt7FgQ(
zPWu4e!MC<k`lOTZ+XJ31{`n-V&_h0(&OF`xUnp+W!{<<bvzK2p0@BC-g`UPo{N@!P
z{e06SfDZ6~e;f7=@^k3tJjDM?4!OsCcM=%p_s3vtgr6S;MWg(UmjL~Qzx6wir~FuJ
zAm|vsiUMTg{JF0~{RIC@2VhU~ZI)oZQ~b!=fH@-g%@3fq0{0@I*$Fn06K*f~W+CJp
z1b!4nbrft#0&x;Z=V30+0>2y(7eRI}7RXhQJp@cQf%;#xjtc6ukUJ*$^uIz1cY%H_
z&^!crbQ19tm?`h!B^V6^kGCLo57hezO74L83RK^~rsINVse~aw&`Epm3Beb1+apl$
zS}|0d6huD@uv3Dfvk*TmP?K*OB+%%gH&~z-V-g_(H%dl^3buDq{3T2fOv!~af_rU1
z3m1$~FeyUtN+Eb61qVz(ixM=GuNN)YNkO|9LCRrZ#|ploF!xzOUpvf>6I5;mIVULC
z31iL+TE7I!1;MxBScHoL1)c5U1u^8XCI~`l?@SbEQ|Uf(lHj{_5WFM^dI9Dq3)Bt(
zO%dGR28mR`v1oK&7Ua)DD^0La1nesUk0HQZ6_il=J6&*>!jTyQ4+?Hx6NFJ`reJa}
z<gx@8=<4xxK^D~kXAAx?!k8RE;XIg@D@dczo%M!ba~rVp1Vvw<c~cO)2Ryd~hb}<V
zZ2_CYKly@`&!MnD@B@Xy3I(xLr&=UvqpkmrVAU~<6$@Jago+ZuZ{(eo3LevrcvtY&
z&tNGNy!1LOEEhOX0RNsK=Q)g32&Ci?Raynd>9t=a_#Zh6_XT^Bpto93HV-Ol1Rqny
zWUXKx9jWUCtLc<dFBqlZ<O4w_MGzYVKRZHiqu`H&AWedh`v7egETyXa7Qy@x2($_m
zawu#Q<WY9IT_Ea0XNMs850FlQwTJ_lF2VZ0VB14M_7-4w3qIcgV|oOh*D=;Bh+PBu
zKEeKln9L)=x@55Q3x>W&=YSy57BGW?u0g0D5@hbiTpkNfkSj7OkdUA8L~!#i$Wy`J
zTy%~JnyGAMTyTq4Z9?$5^$3ib6g*4$@F~IYJ&+^9#(U6fD{Q6j<k<;#2SA0rP(-_}
zgK%*&T8_fIVPJ6*KBoE+XW{97*yJLt{_jx}UM0WPP3TVfyQ9L>JfIvC#x94ryKwa>
z2zUq$Ux39^n4CoM7cXIa1FY~Ce&qr4eS|+#;j^#sxEW)9!bLlv&|i4*6|{~Eg{iPG
zK-hE{peKae^Dq`D>>|(Lr0`t|kDn55H~^N@!gi`v3=-N=ty8eDkm`Fvgpy34gbFLE
zTrEuKQ$YW5;EeFE>1c)v-!=m@Lb%=ytw>=IZCg=7H;NrZ3j?WEDn{5$pErvYend%}
zvqHC9XvGP+v`?KAimsvays$I|6TKi@_yIIs6kZ`eAznD~CP;#?dmdITQTSODFq4EU
zSoHq8B;48vgOi0JdFV|MPW_I_qzeDH0P>fGfpi>86P8fI<cd)ABgU=@@4pYd=|bIO
zjAaO4Fo0YWzA*rSOyTDWEMAuI`y?p5F5I#K(Ah%Q64;a@%$tDvT%qng%;knKa0ZAq
zPiQtl?@gg49iX>_*VcmE7B2h^BwzS<96$?%8~%l0q3{cGQ;LKYR{(lP*q)14v2X_^
zI!lB$sX!|gZu}fzcZCO5L#|BNMp5H(;d8|hxF_tW0!xMPdAcW2DRemmo2sqCK@T)*
zgx&|iS}S~?j=gn4=MD_k3-4_Mc_6$}4bmXAr^z%5Tem=AlkgMT?wW<A(XgUL7(W**
ztwML&{Mv-0^xkb3HqwfA2s`Pst)0RPyV2Ptj6Ds3hr$y{SkZ2wb>m{d^Z*;S^$MR+
zVz5uR=Nqi^BjMkFf~Q~T@*?C1gsF7C7!+D)4;>N)dSmRdaP1_<hJ~sI*fb)XqJ4c-
zn7SUz^+XuC6qrwiLv*=xOn8Z6qvOK0=b>*x_{~}vGb#MhO0UBy;ggeqIU-7;K%lM2
zk8b1Hi5#fv)m|i_!es|hnE)`3qIaUvauTiT1#uRoQSi$}^e#nX@RgQ}U~v<bQlROm
z=!F+x=rPg0^=P?^@@d!d5UrwovZttN3if)5J{qO`gSY58a&vq{Y0>EQ6=gC({6uLK
zkM|c{JA|?0qOgUqFhKN#u2h^5xt9YiQ1lo5MNf)W)7^qoqFz6=PK&DOGZjH1;p=Dx
zi!^JYFhq3yHabH^Aw%d46D9Yebw(64I1SHVxTu8^r4gcw;m{i?nn5SNDA5To@I;Gt
zP^nCe$axn8V?}e+7&|Ls(WV(Enn~$|bD{{^tj~+KHbBz_(eCAFT@*>nz!ERA{)O2m
zh(t#)&qNVt5&}u0RhKZAOCs;TDgT!&I>-Z0iYVhfSdl9Ff=bvgi?-Q7Q<}&?r4;F+
z*}EW^A#$a7#x;@qCfJlIvPpnkmdJV+dasMx?|@{B^ptAP5xM^hdvirU(d+YuDD4oy
z@<jYgFzu!&jr_n{BIl1mthYt)#y~~BXr>7A1)`zb04)@a)Au}zMAZ}=xg$DF(ZOQT
z>vv#9iAdxE6{VsTF|hZp$iReLnFy{L9yL+PFa++2PS-+Vg(#2q)k@LkwUDb4+0v(P
z?~B5}g=y8I{;lAwv5H1)F<2`ass~J+Xj=>h>qT3sXzzh&nFn|pMA_syHi~|j27{YK
z%RYcH&7zoLkQULweyC^_JxAw@Hc@R3tY{b6Q8`J6sEkT1J4MZV!O|u2qpz+!6ltgq
zv0L<83N-YHtQ9{2v{y732EBcvs6tHpk!buI2=<FSs-a>)l;sZWLDA%A5F8Sv_@VV!
z^e)AshDE=R0%k<yL`SYsQS3_?dm?)5kJeKWF9Dciq8FplIW8)G24E8+&IF(*ML$z)
zbV^iheT*3%5&uiUQCo3M9@N{317@OSFCKpfEeG*}=V76vxR|oUPU7CVn2fV{=SHx&
zh#ycu+*KT$1r=^$FItkL;)gpScT8MM9)-L3mrf85@hy5Qd5V?vU1=}zQrZK(#n1jk
z7g>D7Z`?)GSG@UU!1#&h?gWg#Smp;!$Hj(OP!S;hxfydhA=dQ5-azqY+PzMSKO!&d
zlz1oIQVAAk#9`G##0x?o7b>33##oqm?MqO2Mx6f`W8vZ(RAUk$o}#kcNb%ZPRDTvF
z&NvR9XfZDhDq_T*n=u$G*8B}kXT?9|p%o`SJs*ai6YD2H&WrQNt-BzONQ1o>#fw_-
zr-&B^(fKbyyk!+o62*lSe@PPeP$1%xSWVfNWbsOh0H%od&}ltYyt0Izzsus^vS3@9
zc;%~*xFTkWfPGb*^$?oU#jbRq$q=ukGyFC21xgBLiXSb7rY!N-l-sy2meQ#^TRhDH
zdUM1P;}FjkAB=<C4e`eTV967^d<C$Z;%Ve_-4cKHU;IS;J^hZY`QqJXU>AtfC}&nE
zw#kM>k@!V2@s2oJ0KsDMP$@u5#O~K1Q7WEi2P^K1i|=5pOnlrH#*~Y@LNUX8;%$@>
zst^xOKvSjIy#p*&;wkzD=zX#8G+<VX*HBEhM(kgJR;^WBN>`%l#1rI`*Nd<10QLj%
zCv@s=5Vu|hTBCTB3~mzp?Se$JcmV}!Tf`9`LvO3tjcR(@!~=m)-!7g*2i*?wWGw_b
z#haR;zDw-#9t0kWf5dXn>K5;&+U6edDmn)Cimd^gF||JN=3FeoBeC~B^!AHK4uTAb
zQ>Q^<P`ok)<`0QCsG;Jqcp7B`hsA-nFg79{`0xIJSV}*(C*qeo(fL&DvIRDciBB&8
z%DC8c7i2;#r_|&T$@dhpu$A0=7pB=sUa)#Wy}jfkie5QL-21@lDEW;JqfU|`GxR!3
z=2ASuMKYhxC9V=DiV3+%KCFcmM<t9qF#DLKlP2RXnQ<Hf9un545cian!M&R0B?+OL
zHgAa{5S%`e<>W#6N?2?xiJ#;_8eQb{mz<?rSH~ruYXK7=IiiQ)3CRJ9lLbm%{0>t)
zDT#ao5~n0>6e>9_Ss4eIAc-&CPzshDp?aSXiEKG$A1dj28Dn7*{rliNBYBgak#Na=
zvM@sO%2Gf_O0K;H&M3*VJ{13qmhdRQ6eBT_=NK!gOu`J$O5P*~KTfilu5+K0JgkAH
z^AZbfTNfmsQBv`uq=;@Y#7nrFA(tSTNjD@CC83leOp+Y(0l6eu^fIhSmb}7*T#6(l
z44kQw0D6mFmOP7SmvvT}<oiQ_xgvRZ91>S0LJD`KOPqE=eTGD!LFYAz{T?i0reyy`
zz+_1r<1ltzg8zPl2T!u}9t3hE6X9s(N|Lhyc0)4H9ddb+FKA1-DVa;B?pqRb5m0VR
z1Yv09OLndSn6*HncnxTUl2=%mVUgq~ItJd6{FMR0V#!W5BuXT)Ay82&k(PtyuH?KF
zEM*cK%IuU&OfLiNp5$5b<0>S}=?7dXDan8_Rg$6^5V$XiD270_<nKIy)kt#0=&Y42
z5J0ZZDk*&kgX<+WmofN2;@b_qO_Fpv(>6=|$ZKhlcs+uAt0b7xrfrf6`pLFSc2mZ@
zLsI@P1Ue<twt{p?-n$7a9!loX$1}Pm#pE{kNd7FtSg+(mUnuO8d}Rd7BgyY{QK(;H
zZ6(KZK;lscD+VPy=3`DnlKo1M$C8avP&h34G!A4$^5ws<dsOo32IzevdG!GVo=QHc
z1k9LZcO+QGB@3yvZbGtXIV_x%yg*l>rX<c&XdRL2k|1C!{nQ@NcG6ewLBL+>Xng}s
z2PuyY9!KeGI!HK4|9%yq&Qkl=&~lO5(DB4o+E078n{?(3n1587eH1Lmr1?yYxl6;y
z>+q1em4L-ly2}jWCEZJBN^j{r3U~QP<=$8XUulOuF#V)uX(0a6PywC)j!V-H0W?6G
zMBD5MX)?J`fl?!FcPFJ^P&(n1G>guLr=@c#n;#_A6hdLJluhT05NU}IIzy#Pgs>@0
zI!2+eGt%qi3xrEKbn1?fZl`E>q*PB&c$D;95NwK;M&RGX;lY!-)6pqbx+ohe&PuDO
z5Gzi4W;#~roV2hQ<h<0$6=N5q+#`^`C=FSKR=hMSA7&>=zoNK$qO@Z(=9DCjq73CF
zsly%^lPo=(1eO$O8~J#t(sh4g?6P#pexRgDZ}n6D;fnN&UNo;tLtcl8=~7DrS{c%~
zIG|mVUZwDOrqq|xTUpYD<Ir?nI<^8Zxl*qanD!0n4!ZA<ClzLa+?2jZHMqB=6APj6
zwscMbF!QAw-v&y7bTuWw3#D}om{ufBpc-839jPsq4-`uiM366$7FT0wN~K>{L&aTb
zH2tp1q}Ry1E0^X_viY9W@D$h;(&Ar1Dy0g#8dxQr_5>{VrR6yQtCr?=0jx$^OCO=A
zl_tLgv+Jbuco?gfenr{52hxgvG1g#}rqM6BQTi5rtFB4<LNO-VEFI`Ut3|r~eUMh^
z%e14mNmqUc(k>k&ud+irSPIf99jpZDlJ2Cv^Px10+@o&kPhX?6N9z6&TD?-P0jBjy
zm&5|>k@V*CX!T2{+R+-2THT8QIw)O2B_~7Dt9~%?v2;-Z(1xYrWXxhjnobVUsPvl$
zAWx($+AW_--z2|xO!~Pa1jeN+G|)65oqQ9ZlhO-xUvNsg)c}?wvIA;B+sb~fLd#AT
zM$ezUEaGF#(?O=Pegf(!TS}*HCz*-L4xDB3-|<&-ku`6}n5%3hm884LPE)PrQQ4n#
z>OLm>iSp6zvhr0x^N`h(YwRhTM<+!unP)y)-m-lZLGY2aQtZrE_GS|>{ba@TlJJ);
zpts?1S$+ZK{{m#EkHN$fvKiI*lLX45uK@I<?7%iioRXa-=l`^<q8}_lG6W^@;K{mN
zK|*B4d(adrn@{d!n5>mT0B2+ldqKiwdz>*ACHv=BphU}50*J@RHc(O_R<^GUYR}5-
zSrmVXlN~w&o^!INl$<{=W6XlW3$h;rA#qXGvKJEZvW0ZaPmp=g89q_=Oa`WwB+JeR
zxg`6XT-;>Y+w`hSk^SZblvLROMJ_JOqA4txCaa?N{1w^cPZ+x@3!;*|blF;DHm$QV
zWCnT@T$4Q^UoTTOeG+=JWFOI;v+J^gy&&1L>^=zQ$R1G%Rj#Z!2UgsWIZ(lOo@_N;
zmbocgUWu_=G8a2&x-Bc@0W4p(`7q=PWU1tV70PzyL7+&cx`oyq*$BCc)?%6dFG!Tg
zzNWP-l^uHq3h&A~NTN*kelS|)vc@Q|-jn^<1w$)jOJ-rLQkI&GSyah1KA7lz{B)qH
zTDJcujMc~jKEqh8>?l1dbut?sQ0iqFbdY%<OY6jnHpo8cf<U8Hww)@+nq*~FfN7TX
zc!H-z7W6X|w#u66xX>osVT63UENuY{?T~%A9TV-8MN*ETOBO*c-$U8KIY8@{jnFBl
zNA~a-<a%WjAH$eFS#Ac#9?4RcK|{an@;4v@GABOBpv>w&4e~>>j24i`vQsaB49h;G
zM`lDe=R+*XsO-(Jfc8Z8b2(t1$|`(e+L$aW1@hyvSjwYM$i6!VO_Q?G<sehC?<o6n
zME=Sqv~1<>6A-tPKTrFzz5I2mt#**Jmx4ITtF3h9%|$+ZADUd{KT;mtP42};=TUj&
zE|6pL^ck3_JN^qDS|0MdbkWaK9!9@zFZp3HRCvpCFM-8Jz9$4NUpX@kV}A1D>9E3I
zK57Td<MO(Fus1+{cq_(E$VY#JK%hKZL+`(n@~7zlJtdFW4{}<5xgE0)l5YtITClw9
zdHj+><jX128Y+K=PLpBs+w_5pGjj7+5D1sQtwSq9o<rH~Nco~MU`EMzOF^RL;gujU
z^2Qs$jFoSrD#f$%=@XEPlkeU~AM!aTucr@^o|pd~4HXyU`>F2jqWslzwBqGnbSWu8
z{x!v$66MdF#IhyH{is6Vl6=ld{6&)G*C^JQB0sqrtyKAvNQhsS=RSo%n*82Ew64h0
zUPkMx{B82%(&Yyn(8`djz36`eUX%M#fGks9LNEF(dEWqduFLCRMQ65r;aSM%$VF6e
zlPiCN!V)*+$yA-3Ctq?4V>jiU7oh%@{9+5lZ_8tSft@ekPbKLE^7Wr#qJ{E;RTwLh
zzsQBa9XUS{;>GfxdZ5T!BJZMDR;fHK3=4HvzIGW@l*wmNu)SQqascx8<VWeHSRo%Y
zKvSjs+6@R+$=|huz<v3NXP~KCKClp-HS+oAz*#H*m|n4U^2Cj3)ytddHpBz@xlchF
z<j>MCzfnF(E<ux3KJ!zobF=*8MD(`Euh6}zR=Fw+>f7Y~6ohJ*yUhSvmwfMbusoFS
zJOP$&c})=X_Q;!C(dw1AR)M8Y-boqRM{<P%*!^;6a=ixRDRi_Pl*b>2_>er?9deK5
z>y2m)%dJ0`LvTc1Kwpp?mA^9+OY=nj)-p`{seFL^qA~e9bQfz}zLKs;OvsB~gTSPG
z8@;2Z<Z`-cenjy;#RY5?D=2|&r+AGXUwcIw`9%(jEwouXDqcJUW1JL8<QF+BLaZ2b
zQM_pVA3$9d%hN#I6m!`aJgV4s80H^S{6$$vcg1&4Fy^6H-i}##Djpi3!b|Z39ag**
z=5Hb3qxj_$SmCQMt$`*#1uq<9{t8_<#E&b&=R!O{A*R&g3B|o95C~M9PKSjj6<@oO
z8K)F)lh=P*@do*dK?=WnXay^tqY~f{Mc)|ELKVAd+X_=G^@bH^6q6(93|BNzlp#XV
zNN3VWg)g}|Q3`D^#-bG*x=|UUsHEsZtm1|<T4xo%)58&`V9}F$PLVT>p1<>oJrwu3
zpolsOy%!Y>y8jTbV0{Cg1jR4)z)n=uw?ciABJT&7e@XEdRbD15{-rvF6vfak2&5|H
z%Yl7a(MuINX^LN`L*R;H_Hz)ws%WK5aJph+4;C*&kxe)Dt|`_a^=qA#sd#r4V6qgi
zQyt26g%efVXDiM-z@{8Utq$0^iuH{^yP^2N8;h8yI7z3Yn~H9CaNbg+G(h~e!sk!4
z3KeVaqgABXLr=vW#S~@SixrI;s4r0@I6*_Hf<^zC=dObJ3k0lXihumTQ?A(ZU*u8|
zM)8*lh1U%5R4R%SVQH0OJqrr&EB+n=Ots=v2s&#N3#rnrR`Gp5K<gBHKg87P6@Stv
znI0%ib3qyu4uz0wRBZVeb7@jk9sp*uB8JXUEsDlG$hBG(U3AcGQ}|E?NW0>TcY)oZ
zuzm%>PQ{8*2zDugIzb*PF71GPw?c)o*;ze`JUW{8D&9*2TA!kJBg7vmrc>ylUy(z>
zf&qv_#h^k=yVj867F`y7tk_1su3^RRCdiE_tm03=Gpab$0_-P>dJ48bRV*N$F-6`n
z@Qf?eVK8Pw5hwxnq@tXjm?_1o?La%C9H*d;t+I=Pgmy|39T@GEEfnE(P)g~o<fv>V
zr^iY84%JmSD-Rup*)GbY1VFng1FZC3a8uS%`sAo`)~{$CQ$F|;^6pAKy^}qZhh~6y
zD)B!t@!%=na)Bmq<!?1m@1tBtCrw}F-2YN_%CJyy`YRnNLVH|!J{{@<lpf?wo>1m|
z4ic!0JBP88%FE<kol*{zQ~u$!^27%i3{w6X1uKG;CMxa>QO*%!EL54=h*p@gZ~`o6
zl>AtbaOGYeG({+@_Jc$!ODTyNrOcw2akR35JnR^yh)M%ul`|={b5{AiFXkJkoK}ri
zlJe#6KrSiU9jX30S^4t=Xi8H)(+BlelsoCSepTuF13)vChbhRBrJVC6#;z;J{(*`D
z<#h_P6)AuE3M_Y&8!4+$tZblPcZo8T{ywG3u?no=U1jlC5GYd`=qO#T93DgKo>D{s
zwMr%TWAZ<%l)*k&%lpb#>8)6;JY|J#HOc`Bs@5vsqYshPE2F)j>49>03g*<H<ekEj
zG%D??ps7ijLb2c$<+HT4v??<wM%kupa0Xbr(t!(s4rRzc5bsoeO^es1Tz&)s-OAT!
zU$*urulyGYRC@Viuupk`?&&{LCQ@b<|KOB1xB=zDbLbpYrqeHJNV)kk#vUuLP(W{3
zSxvE>5v83DhK?$aQI_h7@}-kl(WlB)Z=*G?ED`~FLisY~S0|O9G=p<WIqxA*j#yQW
zT)^0>KBGW{y=o&}W^_<R(wWv#<^C=7I;nR51mdhpZU?BV%J3#8>ZXbyfBUFv-H&J;
zQ{B!1aaV0v32_hAU*xrWs=lF^j<>3has)mquPadGs~V*Dt)J@7eRTS(tgkhI9#_qK
z2Sx>|!l-olq$-vU9j8<!^g}$Ys@#sTAk{P~Cks~XCzl{h_4q2Lc1E>E1(t9XgDUf)
zR4Zq~ifGkeMvTR%-tq*AQ|-!u!gDIqE~r1RDxx4%ylRxrxe2OS)&W?WsQNYsgUPD@
zQ5AWL>ijTxQdI?u(7K}f-)+q4sw$E$Q>CkV{svm6sxT3Hvs9Kfu>QJg+b~eFRml-h
zn4{9(!&t6r6BlORRIQ_mz+0;P^Jv{xd4*yuU-c&C2ntk}_gf)fsET|R))cD_(WRLZ
zRX(NjN>v9>Lg8K2aX!?SsklF4Wy)2;b!b(p*i`3GrMgFf+WV?c=_FFC61)bmI@KHs
zKG&<7se+?X<*^6~n^eIRENE6GQl`E|wK5eNT2(LZr2Jo->Q#EF_Nop<ptnyoa2Y(0
zRBut}p<nepZBzrQ*J!&NRDI9^v>{b;ECe2_rqR)7SheAQSgsM(>>!Abst&&iy-!rP
zD69Qc^?5Mt9aFVY+H+hr?Ka4SY7UjCO{$(>PyY{NO676{y+_oGeuN5JwWbY&cItiP
zZrH1z`2lDSYJa*X>8P$OfqEzPp|{cLtd^g{oLtmj4nnW1n!OccZtCwMG5e$Hwi9R_
zQy+W)_3rABqk#5M@7)XHsqUZ)tUl`EaEM!d)mvz{_EWo4=G$L=p8^WU)xl*L3{W48
z$Jhz=rq7`;P<{S2jGa_FkyjX`ev6J(!Rogt84{xYkvynSbwUcp!qh@aS)Wm7Uw{?i
z>OsoBM5vwVWgMw4r)MNeJx1RVingj>rGn%b^|Ny@-&pmp^i-ZzACAP5#;LE<+w{D8
z;UY*}P~Q&(xv0*iKw`XFSp@6^_5K8~B&uDz(V47XL{-8m>H;bsO;yK70OhiJ!;8?A
zrhcCM>?`W&VQ5`df4l@1rmL;?<alPN4~Ak*uBpZJ!^l+s{t{ra)F06O-RtTNOQ9lL
zt)+)LN4@71$PM+PZeZV1htX;Mwz`g9Zu#msFMt-PGr}NHs9sCoz$jA7sW$tLI`Af-
zi`9wrmDCco<t>m>^`MpBw0G52`H(MD&!Izfx%w|9$UXI^jvy84onK+u?yFynhcVS^
z-Wj0PsD~&<S*yO$2^Dqf#v0h$pkCI7R-<|z8PlYWe~gJXtCjRpY*GJ0HQ}x5>=!`V
z)Lxn3Y*(`mTCt=Z>J4;|>Qs9rf^?~W>q6&4b?+odw_1D;Fg@x}+FyIsTTRg0ulD7_
zm?3rlf4;oB<RIjR)fcW|Y(#x14+5j=u79vVPt-Xppy{c)dk4nG)F!&YHm+WG3Y`<`
z{oCmMH>nogLhqD%jD<gtoyPTR5PMCG8x%Td;;5p+Q8THAgp=k^O5Qqa4wpf_i>BWP
zpst#2ftaD2#)CGmqnao=%s!?${|;L2nrYb(_tG#wh6ZoVcR`Tz(fm%O8@?I=N)WBH
z{4`y3WzS!8lcFOhG^b`mZ=i-v@8px3Mc;s&(oBs4?X)J(1+5@W!a=AA)#Op=Axz`{
z3#>S!si2T>xMpt_6h>$UZ=e;andJ%0D9t6RIE&T{m>>|NS+E)cu^LMlz^rFAb1CEz
zr+GkWwIod;k|MJ%X{spPoUHkm;_)e(LU)X%YTEt<+GWjBD%METWMtCsS>vAtmaCfY
zIWRk2b7mt*hGymlkZYQM$O*{Q<hi1irTL)=oYyr`^h?OrEcgpxIaW;+rOt9S#mAuH
zhUTFIdh;~O#hC9+jg{h`w=_L#q3O29dKsqWYi7{)UZAmG2be-l=-1#Z(&SMM;2llU
z*O*$d=IHmpEYYm>##pIlEp4cGHP5evhBA$N4dlu-F{d&6dm5|j0!*|*GmFC9m6|zR
zU{`52XkqDnjfJB0)tbZfz}IMY({+Yg&5nH_b(-y8LatsjleWnR8tqf4Z_vC#fu=@H
zs}nReX&z-_tXZ>@!Z0lwcRCHWYF1MUsZG;<0s7iCuGTTo4$T3oU+dI_<)hW5SxxsJ
z9%{_=k=Jfb&JU32(R`tSO}&~wMQHVD>Zn}dk!F<_So$>^sh)X2v!WbiP_vBU%tM+6
z4g?-+@(0m5teHu1j1i55YQ#o0iE$uLG>%0Se|f4&p=!1XP45WEq{ciSlbO=Y`~ebn
z+B>vS*=z4pQJaIdstd$XYu5-CC+$_*{G7FU-viA>JHo;wT(uK3Fi|(H!+LNY)xP@*
zSdM8w+yDW0ZNMgI@X#)$1DL1wCn3H6ytMf;uzG8+e+J^CjjO-{`)V8J1IACA`W5CI
zpxsJo_!HW-_OK~Xd*mfd?WDH-EI3bT=SD%rY3;+mp*~3K_Y69NwK6L22+?jj2Fy_H
zMhbp~X<17Fc1F9E+~06*o-M^+BD6ZnW<+ZH6&Q@tUL%J$T6;nU(6d@GmAl7j2gzeS
zr(J#tHl5d+-oh*{Xr~6ja#0&&1HJLu=jnZtpxyi~)F*1w{sc>s_Td4LOWOE+h$m|^
zK0_--n<W5esy1N~oYu?Q--cmZns$L2%`4iow6a&VvKPRbt`$`PJ44H%il%GY-!@`0
zncB<rHqFw`Cr9kM_U28HZ0-BLFfB*hlLxt6ZQ%z{ctg91Ui5j|uP91>Q@fCf&Rg0G
zUjgN|*7G>5&$nv#eFFIc?R`pE7HZGYE&d{HJDuV0Xm#yiE!O@(E_sP|%pR>$tvA&}
z-qkuL0<BE@MGF*`Ydhvb;GVYPGFU3KOQ%6^rPh8SNR`%;LPPhppLqbKT08L@^wnrx
z%OF>)wK`1)TAkK|G9~rez6A6>(8kmNtwEbcZe64HJUQV_TImifLbLXlrC6>OZO3-7
zv}!#+#viRiJC81|cWO_BKt-3fkZQXhYDII=>efytucJqM<s!s;wf8A5-lq+uiswh#
zO;$=M_iIm)Lp7jHw}Zih+D0a@hqSl;gy3WC9je(H)|Ldo!V&FWTeL>Ct(59}qMdyc
z)<4xA+6lQa?IS8y9M|4{g4Tp~>JC^YwLdQf^py6*E|4R-$5H6C)ft>I2|L~GAS-(9
zbz4?Kp@YtaN-!LC&r`vwlWy5Lz&Pua6v21VMN!SMt8NyBL)>(>CjfI)xA+5)W4a~u
z{J86mE&-^A?g)KA#Zz~XPF`NRy;M)^t^3x1x%lWhd%)?d%Ri4!Ki!TmDgWoMlTe)N
zxbDwqAQ+&VN9B<xbUi^ZCQ!$xbizqpwh`)2>297v=V{%_cwh(Vp7((IU|n(sNQmye
z9Z(;t>&=9{VY<(L0y(1_qjYw-&XwX3QMy+mpdniK4jr>&be~6){~4>>xdF|yx^KDQ
ziPNp24B9!}k`-V*uUkSjNEdXYbg%TH?yVqj#_ML&J=z4_a@x=nbtO6IOwz5UT9Zq<
zmTXv&tb5l6E1IHf+=8)Got3_va#{B$l~twba%MvAif$$?to5ockb@bf>zX5>FhjSA
zE*f9c1ssCjOx?`On0A)VT?uksC-DGhwl0^_={dUn<X7eD>U+U?L-+Ajbmr-#6k)ol
za|i&+EnUKgP<UGx#lTp;PC<#10^KXqpr}x{^h1y$t1go^^gFtL7DJ*~_t$r5mFPN+
zfGO2&$wTX|Zu`5?Tc%4;Vix7PUJg3%=>}$lROrGfNKvVKngD?+T_oLOy{{YE4S{Oi
zzwID3y2VucRIBrHg@!uax@ADA*Uh>D@<3<Za2|`%pcB(>(5Pe6=L%YM=g1Lj)qQmo
zD%y12RNUFFo8N*~hfYnOeCX8eql|2qE|CI04|P>#Al<t0hggyx-JWf*saF?HC*wYy
zk%~1Q>6YWPF{@wq)d&n7&@G|d{Gje<D?LX;y2)^u_*fT0)r!NqCfXuKbQ4EFMs<8j
z1wGOEehTtbCwv1iW4btJw8nLZsnUBwcYQWcCUw&&ZaSrlBrofT{#zbY*y_(VL%p5;
zCRKde>*KaU&OyI*35cWK@mDKYo%Hn-Cv(;xcn>fx`Z0<uyXw!J#F(4@9d|6rQT>V-
zbRN@tuYh`Y{f=_Td+68fgn*}hdk*I7rI-B<72f)JNwCRBFS&?LU;Vq+!Q!Vco((X6
zeS`*zj_WV%1XzInh3EeJ{)B#pEd~SiA!{IbQoqLy2A|SDSO>Jz`U2XSg7hgRU<ua0
z{xU#A^b9H$JEQ-dKIIdx_aJ*C^iSxA7_EQxJ1C6NS5TR6tlozYd(Y{QtFXT3^?ROy
z+y#B&5eTH}fBWsf|Hr16P%br1zk4?nUeSMe8=9`_H$4Nibp4j+(3zp{pd-vR{d9U$
zX6k$HfMn^Ns4DZie*JUMl&$yQ0F)g4o(yQp)d$nYctfxL0Gjgj@6mDUrrwc0rgls3
zeGV+Q^?yGL7HhsfSO}N`J(ptVh59s-DAJ$V1ci6>7A<&+_4`KAS)zaKSqPTud6W*g
ztDoP7bt=;zxCUd&^{M}$bx)796rKwGS9CS8Qvcm%kShI0XCQE2?;ymKs`cu_z^u`~
zL}Rs9{of`?)ahp^K<f3w{vZ$ZN8W_O2K`Hv(rMJo>7?1Df0+&)&H5=@z_jQ&u7GLP
zf8vQ&n?9bdj<)LysQREoe~Vn}PJKB=w7T?1n=$Q&`e*3R)UEfi!E*KJH^b6dy?Sez
z7eM>;TOYv0NBT6XpXt}{r~2Rl{b#$tI;dYn{_Bu_GyRL!$NE?MK!)`}Gl4duKNAN{
zqk8LNw4UhqQn}w#{a*U_Ze#ktcY{po_g;jdQ~Hp90DZ(Th)s8vts%4m>uYDow0c96
zy<z`VSmR)LG6gh8!{={7!pSh>8-O|+BA0{J#V`?%F;@eh5=(A|8)t!b)DYbSg~ts3
zDHwA%#8A%5!*GEPLY{^|avr=4>sDbB-i82*)%zGM$I$XM^e?BU!Vq|v@(=!o^o0;S
zZuo(U%K{9Z<YAvQw9>2Nl;PEJV4pT@rFw%P!<SUK5^UgRz`_v2Qu=s6s3AoHmM{a0
z!qjIB5<&?#%%_NSgh3DrLn93*?}9`bW_e>S(S~<dgTxs2h0Od84~fC1254sueg6Y?
zoMDQdm2-wm%K&rU@B`HcUNC%2uI5F9MhNrc4P}cVkYEU<tX!huOMA4E3=Qcp=8{1@
z2h&bAT+T-;#qi-bkV`eV_@-sBth|0;r5lpzca&jR`~-~G3^^3k&om_FqBG0TlZ@7N
zL-b1+%QloGg5($u{|t~^L)k}|-wi|Ob)e)KHd&zHrs3Kcti5Hpoq^VE!(s{%<{Q>f
zmbAcdokAmp2A4Fj6dAs=(o5xz;Upi;V#BRJFuxMRbBnPQrH0Q8n95zl=oB=S879Am
ze7T`X35E9z&u_r|Dhwa6fL3X!U5Cyp!>{y*xNjKx6DZY&z4V~e7!I~VuGY|#hPl)k
zMrkXkH`r3dpwaOB-}JX`GPIEo&}{H1#nf61Vt2^58lEYIX>EprFEQ3`*i5DK9fnn6
z$afkds5Yd_AbStu4-E;y5a>26nuJX~hS%xO(rXB!lzyK<9f7e&hN9^Z?>D?nA;JMe
zRWHT{4Q^%R>kJueBY^hU@XItP95y6U3GImCFZz=|HL&H7A2WPGS&wl;6}egyhI2>3
zIcZqh0rgXcHKACiBgWlrAhyPNC!xa5IC}-;?2XsRNpUc0r@=Hw<7&zyIT^)tRn6Hb
z!0&)R%f)z*u0OaMf281%oAGrD3mi3W-vgdw#uVR2nTxGSbVc0DxN|>Hyp2}6!r@~q
zUI7DrjqAuS_A`o}LCfFxKT2C4H-_DTK!EWJ+N4exXHW_x(0E3U&XdLo3P7JS{z-}3
z)5aIiU@AdI8M&~*#wH>m#{Klt3^jiLH(FuF2x}a$&lsOCKySEl@CQgl7{8*-ZKP31
z4rY|`cS=7;8xy?15@S5}JjP;;YPw{3*0|yZNSx7q2iEnR@uQV!oi{ct0QLoA9~BT?
zH0G1*9dC??21|l*G6Ld>M&<z4CCMo4rW=%(j5YLZBpa7eR4m1~g;F4?#>1nKzibR4
z&oIp>p%lm!<LWgKylVWLYGBfhiYzG1F#hO;v1`UM4|HBP%I8Bo+xYCKXyq7}ldF<z
ze2FS8ZWxzQc|e}g{sETqrqNML3CUZ=wN%)4+xUq$2J?*rb|3}D7g9kAjmh-3EHZxk
z7g+8X<*%bvY~0I)e2Fn~B~+9eKU#xH+%=|?lTc<{76eV@#(ycDde2y$0G0~l>=uwp
z;|3WfSY@1~;K_aCcX~RIRvT+9kf<@*Qp%{-D55u8ol$=Yp!LRLDpPx4?59n=!5HL&
zwQMxLHXQ;@Mspr4Y&LdKJh;VJL}#g1W27@kn=!fqa_z=hbS&;LD(NuPX`Dep@h)Si
z5&{p6FHrfuwcB`#9H$=RvRaT{W7#EO_Zi)Pf%%V&d2}4;H}2;HX22M=1~7xh&euVP
zjG2p}>9O&x6vz!5yJmol7#prY#i(%uIlWJejr7`hYGgmgl*WvjI>?P1r&9`W!l-$O
zu}Q13Z#`h9j0-2A>4@nd{e5jsJldx0Ow%qw!rru)VqFfV4tg{lO?&@^CKuCc6*^r_
zHtWISW)j`Q*iq9v6yP{!`is7B;%;K>M9agpZ4=acn%=(wIWN-&DmwEvtyuv9AComw
zhhAS(G}SoynV3}Y;cq(dKFD#?4GIbbm~1;iPMB&RLL$&qMqc(wQ#|cmr%cngq4TsU
z#2*TSOr6t#9c)@BflVQ%UzY(T)D-p!1j0;5H$l-E(|#&S3^)B43h@Y&v-LYPBTc#V
z^NKR<&wyaGX(h!#V@#ROushb|M=6lACZ`mP#hDgUmEAeh3c3h+-V}BgYk9%MqnG_f
z)6;s$#hcpbm6Txm>JN-1n#w3+n`Bx%47p3D=X9_)*<_`fjucblDoTi?n(FSu(#xjy
zx6qqrDlEceu9zA|Fm~0nn_lSYrY6c%Wtb+sF?P-LVgt}JO>T5J$TFqcK>c-7sunES
zrpHuEl4JUnHtAf`VKxMAm`<<4T=GmW_d?*N>9=<<ms_TLmna~6+q9Z~v-zeo^fkN!
zQ*<173Qc!a04+8(s$g)5$>{=EN=@CAD!OYDyabjq)4_jWMY(BU0XXlO-rffF6{Zj0
z#w03DzOymyD$|Q0kh^cnC(dfqn{{Z_m}GrWRBKxFDmlb;raPB_R&V-;QsNIxm$w6^
z!Q_|;)<)9}dW@S)rS!x#n;J4PrxsK5ePFkmmc0N?ZKiiA{MT;UK^d41la^BWou(Hk
z7TIOmL;mGM)1luW&}~XgN2|wlfU?28rZ^6)u=bfgrfcVqOl%e8`%ORH#NdF5M;Ge{
zO`)_E4&i4F(8s2>NSHQk+Cp35h$)zY+oL8I7sx#^SyrO;)O5ERn#N4cv!Q<6lr<Lu
z6Q=(>fk{*N9JHoPezXZ4F~8df6kDtL_AWH-%%|!1VQ(I;1aUAg`3?#l%{yuFoy=EO
z!wP4!nBIae=6%PZ!qvQB9a!AV2Pv(3)ZDxj>W`V9qY5o|^K@^Fd6>U(gF;Vp_?N)+
zGEe*g;%)wsZms*6%b$asui2XO1gm$-e3pU{r_Ha?w=;sw4&BfcY(5+gi4b%1cjyc?
z*9*ZCX0{x_e9xG7(e31L^Yo(_i!jeD!C0i(!xLjMW|vtIk2U*Sz;f2y>H?HF^E>t6
zJZG-j3v%9^Fob2kV18iT21_rRzb*hzym<$?5((x9Z-6A4H5Py-nPaK*lKCZa1(MA+
z<h!PrFVSly)vSt!ip%DYDRz@)<~yQw#r${*t*hn_Gr^f|cBkUAO!L(ifMuC~6=2%e
z&5kONZ1eh~v|r_zU%3d@T=Uy~FzSZcMhKWZ^Dh)vx@ophTIQDd%zSj-HgB4P)yp@F
zC=pX&9-+$*h2|q)Vywu#J_9Q5m?!8SWwH57s=_KUZ=(2FskxC#1@D^QIE1k>^S^I{
zRG6J>=t4%NdEKYrsWP9lK;pjn4~l+No2za@Z;d&>6ri<cjR~aA%p1m7y?KQ4A`i?Q
zdPEz{-)bP&Xs*8t(qz7}6JX8eQVTd+%s&4DrPVw`4bo<Qs}A#QH?IkVF&*YNP!?pJ
z)rqNrwaff~Doh@ld30%`+dShl@bs8prpph#X8Bx<^_hdHxbTtr{2281o7bKL%YgaE
zKfy9+wxchd44JRrhoO(nOXyfTY-TQoF(YPQ78drYSwY_RnAyP-WZWED21V8h^V}#j
zC(S-|A!EwC@PBC8T5_jB!p`zzIy&tw<DJm!VELT>=#G~E)j_Y5CFTxV&X#Z<*22Xi
zrue9<Wh)hmxLHD8LFZ9RaW7boS<cci-rb_16OM;PM(JZu%ae-`@UmJ`=_TcDY5foq
zJ{B{1#=e%v6g}~?jL|#8-|{pUoyRTpPoX!!vWDW6CoD}_urScleFSnREhQRsp0a#&
z9iXQzZ#)KOkmXt}GzD8YETDu~qHmxTYAK+jdYENfB&Kx6VlAcLbGYS?AJL4kOsDfp
zq~$VIaYb21W&kwWvcLgL8e@5$oQOEfzhA<ba~2In0nb}LX@sE{EO8Vbx@dXP7IN{H
zrwnLHuzbXWc%o%9#buK$TKYX*vUG)@GubjT3Tjg<Z(18+O{%4XGPjp4KhTdR&64&b
zSg%_KsMIOjl0-XGj^%B7Mdn(TP}bpw#r!)I=2>R>L;RM7{VwKv+cKL{YWbFWIzbdz
zesuy%p`~I6SngO(X9A_z^6MWME3w#Rp|jKyv&0ItyOv=3Ta;VAcf{a5%LUpzD=am%
ziB($U{{<B+Ec!j(x76H+K(*zW1hCXt7N5e@YAtLk%&xO+Gh!0;mR=$BKCn22V}=cu
zZ^`Fxw7fhQEKL>#y=a>)-*O<{V%bqj&tI$M(f3%(Hj67I_}VScQ?#|i;_(4Ur)8rO
zpk0=B+8Q2OUVj#X-IfsA1$r!<*|4zJBHxP6K1*X5T8}LA2SNHRUzb8)!1DI%P(Ntt
zy9JwuENn9SvBi$ug<;E5csbTtBbHAo+4<D6gs#nwS!U7cbKJsgg8B(dKm$4_Ew1xn
z+LWb{%J^+<V%b;(JDbOJcCfeEP1n^OY#56%=4j(EA7IWlGAa#mv0*Tv-qj|O{xEJf
zha1s4YEvEy7I&L~KA>1VY&Ir<)zik2LUmp?)7!!0ZPQ2vDn2%Y4G{FTv5*JmXOplH
z#NUQX@#Nz+CG#K`V8clO%L$tUbj%I3X+Mw7lQx^l2|s1iLxonSZGvhs?I4><a-D*0
z=F>wNVv|8Hf>5i?)K2h(*#td;QD<yEqc?oG&C_PIB5bziLSdwh^JyrIvU#rnB-+OG
z7Fc3zs^w4^YxBx&%;Ky~0NoIXvk7?_<eW`;F#h)EZR+2Kzy+JA&tc(3o3UsA&(U?q
zWnFb~%UrKE)YQthm6h30<Jo)fX{J_MX=Q5LQY#-oQ2{|^h{zT}5K*QeC`*Ryy%Ygu
zh-{I)e7~o^&ga~FzUQ2KpWnFmoO6E<xEQ-4Cd|j%1qVPf!Oj*<JK{vUNfj(zvHRd%
z_?=`Yryy~%-7bpDrr6ojiX_#plfHI%&CdEiNM5(|eir7_?4~JFmtj|P8@NonuY;j9
z%kGvDeK+hDCSruycBkVYl4}>>jv?jQeMc4GH|^%_f=IsILEBOQ3+%!gAX;d*o$_Wy
zb_IK3sn~8ll`ogrWl}1!)NW(|?w8p``~VZ>cCr8MdF+^>z*X99o(<hqc1P*`S8X?^
z4UIK+ZJroet=%WD0Z?bxN@28myXPsad&}-Kx)N^N{nJnPUxS_U6m;LQ`+_dEM!W7I
zc+q6nM307MyRnA=-nDy{Hputv`sq_yEq08{z_;2}R>09VyT`jRPwjSnR3~=dZZCb8
zyTdN)BajDni65h}+inZhvG>?*q%x*nyT)+<`s_ZOP4{2F-Qm|E^U&^Ts!M%jw_q`V
zgLaqRK;w|zmrsKmwp+OjUX0j183y2(-HfNvH*WXSERYGic#3RJ+8v_OohiEzx|<%`
z_0h)7o^jU!b{!bctpw-D*b@x+K}PdW@Zu2TIu<6jSx$^7H?$sRM9hb_BaFLLL3ETM
zryQa)<Bx7|E{w$$;9MC4J29ol7)H7t-581)u;k8I{Sb3;obg~W8c#5GUBZ-{WPGw3
zCOjB&%2IkV8qc85i@~PMfHz~BLS?5ITPfge^I^n|K+S1J&sHFO8QnrSe1_3QOJqNW
z;lC1nM%Yf^0~j5&8w_NWE`S$7j6o}K!3@h%s0m^0zXMBW8HxAN7{=H#058HByW)U5
z&#0robp+#wj{uKkaOpjCfw5VR#wZ&@F9IT(5xO3tml*7eXuZrx&wv*(j87>;7R&hY
zEi}e40w_Kj&tOsLHj(k(rvO}G9H%X25~Cmqzd<rX*#mNwk$xVQQW%FhAgPQSX>jct
z<M%%>r0a~o-N2<WHdcX4XV})(0FlXfHXBou#ppZ(?gqn+l4;qD$0@Lz!{{rAiCjh<
z?RWDSqPg%QpW(0;x(gVu`a-0TQSchzMU1Rxp|qG0?g<kmj5$=KP|DzuhvkeX>DQ`Y
zys;KqDjBV508}xy+8WVW&G4v3XAQ#~1z;`X`yWB-84Kyi$t}hcNicDn;ZBe62F5HZ
z-MPc?$UtK=<KGWq@GfJgJ+$3p+*pX2X<?-9fMhE}=Z-<NF(PR%+s^oKF-QkPL7CnM
zj5OMIb~4^ir2StPBZ0O~-3<R~IMc&8L4`5B3{P4M^fMBlK;uKknMU|Mz({!sfJcl^
z4g){P7}yJLh>`3J-NTHnRD?Ogn4+ZNDC4t@;KmrQc*3V~#v61VWRj8e4zx@$)_cO=
zX+}{U#a|vXCbz?cJ=0|pG7d};MgAO_X)K5yVg@Oo&50Se0ey#=lAkaoN0@(8K;S4d
zbO&@hGk>6Lk_*$X83vCrw=M(c#&mrIfIHKfj!7J6O8wDzf+-Wj-;>Pze}MB~Mu=wM
z{_|q`uScgh^Z8$aIK{j{VN)OGS1UnIGuN$xQa@(G4XE*Fj)g%ofH`srTp;t*U2s9n
znd$I8nEBdVOjiigmp0F#%!fZi<Q((%CWwSF#i3{nXFghp#`8>j4>U$FRkTvIMKar8
zhutV<?@`EHWd3yxt<lV?a5P?G{z9+V%go8A!No9B{m~c8{4a|Y$9&~$*o|k-r`tDy
zdESVjB{K8ZK}!<zw<q9zGE+ehp{vZdXJ8O1%q^~vOl4-s@M~RTn)gHXbsO`~cF3eN
zU1%Sc!CWeUXeRT22~d;8)X+=n2GeN;xNPRH2OyHewB>^2G1ZiZy~*sMuu(qq3~hD_
zn8kmguaGIQ;zuiDrZFH=%+x!Alrpz^p|6Ztw;7V<%&csX3a0JVOte-q?Y3iTYM5Wr
zhl6UF_AkJ<I_7Lj#n&^xs002MbM3!qyv>}Tonix1;|S8ow2udAVt!1kj%Ma_cj50{
z<`){6zsKDAGgP-Qx3d9nW%^V7L_4#BZvXqtAX-v)F!{DFx*wReqtM;S{QedUb}^s%
z0i>JR-wj|7GvOu7S1<EfDmUw6ZlcgbKXZ^0I0H-`Jw+ZdZ(fJUAoJ_}@M4H*XMyfv
zW)@|!MwmZS71k(IN1L2+=9kZ4oD<B1Nq8~I)bFDA-xTu+D|AmYpRGaXV`lt&_(kkl
z-~9>V$a<4%xDT?9QOxiVtE(QwiFJT}*uyL%ErE`(>^p%w%DV9pBwbkIm(b_Rs(S&>
z9AmvirTuO!t}jH~Sy8lwILTUS1@U0rpFu%#Pgdd&KzOktXTf1_*2Z~o_!R2^oo4f4
zO;o@`U)EDs!JT1w3!&7H6?_B3_GiV=QY3)2a~*JjtX^8A1+nz>Wz7&)5hcOTvTp1K
z7s_&)2iMNAp85e^gt1;}Lt{8A&7J<)^*n0}rN$#z1>qo(tY!4ry1@G2OW>nejHfZ)
zXjbVM3|?aGYXtBzOB4@(V_2HcL1J0oev8SAWAP{i5YIBC!bBo#UoOZMR(=BfO=1}e
zp)8pdV1bsatjRG*USlOJ1kQGyC829Jjg{aHL^^BLDUb}-@3bY(WGy}p^I5EY_Grvz
z@u^fPhZXcUxLnr!%P^nEdM5<hZnD1q2J@89I!Vi%0#-XkJd0Sr(MzqE^*=hbSHjx%
zC%979YeJ|lW4X>iW4Vo$LW}<j)?!)!R<bryV!nzMK=JKrmW=kKHLMSZ;eH+K8r5yo
zv&L7#{4G|y7LB)AOMZd22G$_eo7`b#(^2V0R_C|qYi2F>gXCS-$K4?JSXXEP*TVYj
z6{v1yEu(neeU?pahNm5@7yQxsfK`);!E~}xXr<f5+DCzmZdS4kB0a2mR1eh0>dgk%
z&-(K%kcX_nI*1Ig;^`3VBbNQ&5E*10r<~CcE0)rPBdo>r${A%%QJv-(YvD}{dz`f_
z5R*5-GTSJ6HOUGp!?34V%PHhB&00wLy2q^aY5?uojdWQ$u(z`SJjlLxAKW4KvBj|D
z#Ga<C-C=e*y)cik6AnS?QT7iPAmYsSpum<Z+vy{S9Aj^!N^m#!9$JXGvnz8zj<f5(
zw?W2(y)P83CtLFoI4}0Mlv(#?GibMQialz?V0_qlPh&8r*`f|uI>TPP7>@d}|7`)z
zpKY2CKmhv|1!Du*>I(b@LF|oG!4u4$MbDeF>>7F>gt9Xz=6;U7x&|bSt$2pkpW*CZ
zUIG3*`^O|$ieNj@T0D~7Sqj7jcH$|BMzKp4pzk8v|9uSR65BThfXnQ}5txW!zpjL2
zEc+!|pTx1}g~5D0+mmAb3G7$)L)jJfY|8K@v0tSeS2BCiCIGIoe>zV4zZCY<OaQO5
zpP}eT8rzA&<mv1$X(yAxUQJQ6O!mr~AX)63ZBTlH{l9lGrfhauKD@|b@28hy9=mHM
zL~gP_6vD%N_I9d7Enr`H7b1o1q;*hT%+}Mvh!S>*3Vo$)6>k4owsQ7w^xCgrpOVuJ
zz|N-aTowB<JyEOKKYt8T!w#g}e=U0hZK><o;fFzPv1gY6cbokaolR?CKTi+FJ8S{%
z9U9r`0`xVpuhXvVF1vgtRNrH-rysk8{W8TGTG`8|K-z5V6_grpXSco!7ay=~<#4}~
z{TC0Ui~UstfZgnm-+@m(Y*)H-df730NcOR7JE5(gEup32L-teaK_0P}v!QH|y(SYL
z4zcwV${J>WPRY3u_PkVR8Dn#X!Hu&SRPQmtw#|Kj)+u)3CE%yo(`UgwX5ZL=PJ7P0
zU+}{?a0bJn#*yRI3GN`LpAr^MoVZL#9_F-Bi1i4kYbF3kIrFG`#F^ul17$88_EAiN
zE9aX^xb4R26+_aUvo{QV$2kk=?SF!E-9``XlbowF(dogtxCm;zIdT7hJH`2OGY0Cz
zk^KzrG-m^?5q&vNP*C*@#}Ez9kMl7FDf~J4^yPp64uevJL7bUR@FJMA@Fj2|94A_s
zoaMYu&*f0gbD5a+Fisjpjl(&Mw$M*<p3_PNqLG}%^hCbEsh$gb6vx92eqZEFV3js2
znsfafNM7P(t_A)wr;Q7xv7EPmhnhG}4BbERoV71PB!RP@?$kuii}T^(6;9GtG$wKQ
zakwt7a`>|WPvO|b1D?t`RYe6k*ErYdwSS%S6V~Xn(l}9+2F&E}cu<qYi7f{H2FJw?
zTsEg>AMiOGud5)r96kjJ^Em&|TK*;{E*v8HoSp9hUcf2a22#jb)`7kv&R#krUCcQ_
z^%EtWv_Q;7DaXZo9`3&~P7$RO$~it%Jzc@srv$0wI2wSc;>-;OspeQRpr(%FOdH2~
zjwfyGZ*dm<2+7-=`80VAoLiLby~FvLDjym-n`eM);`~Ohs%Fmj6g0cbsbzxP<E)tn
zcnfDS6J~9#9Jw2Gw{d=;U~W6-ixiCMKIi>4u++g>xC>MAfU_tKz)sGqw4?9hsI<U$
za~kM&=;MS^9c@3SEfCy8&OJ(|4{$bC!R{jtXD`Sgr|fN57~*8Eg3e*i#y!wE!U>}V
z=ctV{hc31;&b$BMY8mHjqt7x<aI92XGRfH!4{cK%juxWRoR9Z_d(27R4K?=MjVqwk
zfm=;g=8oJeec%pq1HMMzVXh;sc8+l0eHH#5<<1uZ?#yjD3e_&$%{&lSu9=qW$GEmB
zx+~qd-i09U+-<MJ#BpvdU7jbn9V2M;;O33N8BgwM3MqSWpX~+En_K-QES=*1La#F)
z?j9<6Kh5>u3QNA+Xj<)@;iggS+mE~58-4!V)pSZfkjpuZc?#kxXrCO+J!qp9TnN{g
z2;f=n_f**u%1tXk<2mlf0k9j!Euo@?aPH;|C_T@;Q;WU`?v2eL7r6U3!HXzvax1ut
z+_6Hq7R|k+hNVl~4;}+|nX9D#FpA;srynhryPHyNaok7u&=}8^zH9?NfxDb8uOx0P
zJwubZXI_NNRql`5;7kg)atOmt<z`dG$ThBL4jQj>1Gd4LH10pIfTVNdDcG06{gK`y
zncSpFNa7sEFEF3Y9imUr<ZvA*ahJ>Ocf~mKxa<}HZgQ<J(g)e{xjTQsKnu7hRsvDT
zT~0+iMcnNdAXChJ;~?;*+^qv}zl^*8do-4FYnH;N3hvB&;3~P!92l(Pj{go5)!dTH
z0Mu~bqU>iacSkLB)^Wew0+D)dEv<5Hb63&_Ivcp*O_YDX!@Wbb5RKetvH)!2&f5>t
z%-yjDz`I;u4Mgv857L&pg<D3&SgqV^^onfb_P+<8I=CmYFs29Gm!{x$CwJE{M7p?U
zO1yV-&prpz!#&mse|xzByMXKC_EOTQpF2STD%C?Sml6mA+{>j99puXC=;RQWR|1EJ
zxdj}U7~$@VhSE{)i^t&17<XC*GR|G)1V<;h4vV2}k}L9@cW=2(vJGvHy!Yt?{0Dhw
zDbRC>=TE^wC*DVXAcuLWMNoN!7euEGj`9`;K$kO5{t=Y8@P3bn$T6NPJ#yW6j+wCP
z&O1lvFpl$_!vQ$K+eH`NN!}uQ9DDE_qc8?f-n<<kUcBWtdhL4it{sB5Q@qbsLya%5
zf<A?GhL<%51M}lmi(uZL_XA}L0(gIX3KGc6dj@U?@iZ;~1oP%cz(fddCp}os@`l!6
zUP5{9k02SwYoSeZIPW_vB+v7f+ypLy7e}%ANM6|`DzCo4duA6%6fe6Q&Rpa%Xtf{B
z8`ubPiPx|cz{@;8dPT+ZthBj_<0VZ2AI}S*w^#zt_Y~|V^43ws$Q7O^9bio23F(`;
z$-G)NhJBTHCJd@mc)g!NB$f9Q?K-dXUX;_@B#kGz088mSc@szmZ+#v}CU0mzNER=S
zLiIOz{3@8p=AAkQlEYiO6LxcXf<pL|$NP#77Z>m<XqjEeJJtw55ijd8JS^r}Xya7E
zo1~XfDespb;Y=Ctz%LLf=XImf$u_Hkw}ncXD|z40>%NM2vj?IzymOAg*Ya+CjJ`Tv
zd=zxo^Q`p#xWzlt1d-dkPy9d{c(?SJ(mT9J+IKbba{mILiMQed478b-lmL-?yo(JW
zExh3>IMd3@&qrSy&+`Is3)^|?Xnk;>x334S9lYl~V_KiLJ@Xh$H!t#UkY1jiZks-y
z(??L<&)eaN!9V2L7r>VRp2i09h}TL700((piEv_wcee?W!@Nab06xO|*b#tH-pMtv
zH^Hl+Vx39e1NsT3c$Zc}WSZwmLAA%cll0{Xd;ZV1uVB!DA5Shh@_p&kItTeH{|5dL
zzxo95PW&g#n8PD{4y6W;@;xbs@63OJwy-Yz$pesd<$wMroH@q-v<*L`8$ang=yc~7
zeu6nT&i^qGeJA)HMNoZ`KSTi*PkwDWM7;R>bT*jq=D!*X;3@vsxoGv_M}G&0PxGf{
zfb->VB!g%8e?<Z4$IoqsQh)x`W+)BdH~3>Ng7~gf$PmnT5P=Kfmvh0L<vU#l7s{Vi
z0So8&GpM9JjQ>jv8pHX`c)HCx&;LAyJ~|Y^zuymok^EsVD80z9rHFSlzl}EVm-uZI
z@4w7n)e0|S_}|kaGM0aew&QX9&^qAa`OWk+PvG+-!6ou@Xz6{0-(LVgGGDkA@T>fD
zxgaTgA9@C)@)=Y{dW|21*CakV#2?Lt-88<GgU)omGldT`__;4)x-<C(iu7gif1=$?
zHs6nO0Xh8ZR8pVIpZP0D9^a43I&bp-r5AcWe?=<b1^jumV=v@;ZUHIcFZ~vh#eCOg
z7*YxUy&EuJ#@{#({@Tj<|59B+1^;78J5=(0hB41oeAy)^t>zE#L2CGO6i`#k-(?To
zb$sP%aP|D}>*35TzMm9;JN&;M!NW%WE?Q?c@ikN|caJ~sSM;^;)8D}8Tlq(6D!cis
z-C?hX-%n-2y*5585qA6dZ&8fApT9~A@{s@6-yj40l@T!Ui2v6{hz|1ai!s6>{u~F4
zVwm6aJGc?P*CL3F^4HMN#`qz$V;|?gy9@9MzAL>^C;8i{Kyr%jOu5Ht{{4+0kNN(T
z__Y_<vVQ==LD0M#GL8Z_`eflj!R%kqct|kxEXM032$N$>hXtSTFqk8P=YEC3qXJK=
z8Fd!SS_9%D*t`ZfS3xv=u=JQ9k}~UVf(RO@yC99~8IB9~(*x~<pkxmKCk4h3G<pbb
z*iM4=6jYee=_OdQ6L@by4sGC12|A6Kd>;Wn0%}eR)+x~FD_BkM-ZO&e6c9gwZU%7v
zg5YRq2@tr`Ln~0wQ-IM2396~wK3I_61IZ9Ub`~1X3dU#&94grTCUl+?M1MlhlrTZb
zY2d>JpKXQcdBGP0kcki&U&NF|3hdtnxgcnuP<fQ#`aXzU6pXrKywL*xTFlHPK_^A(
zE(_x5MHwRqr%NDK@V~cVFi!A~9VFugcj)7034$kl;ZvgE8_FnL5!}n6`!7lGehgZZ
z1%6aea8+=dR`4l;@Na-f6%6e_W13)qN_^7=UIzfo5a?+cl__|SsuQvV-(Q5t4M71F
zH)RV_!T`?^7_Xr(SCG3JKIIAiqBY%3fnyI0<qI@a5LY003dIJtS%rdny4Z>YSxbR0
z7Ce0mc1r|5{0Ky;V3gLWWr7c=#JpTEPWNAhU@ld4R|<MUp}R`3pHeT?g1vNPuSPIA
z2`#mP<@eE8CwMvnjrD@3gaF(UWZZ_9+k*9!MQ#whHvqG?JAw!^lr{=#se-ym&`PI^
zngxM1@ZzqZrwJzR3G9CY*CMz?p|)1RFilsRV37$wQ@h|hKKkwpexcfd4#9=((DFdA
zei<4&1w}a+XqTYuE(~@H{HeCPN6>?H>a1RYjPAxho8Vo_JoO74lOXd@u&fTi0l{An
z!95bJro8i@;Ezm*3<)+>!|t#k{8xB5BKV~oBBO$jDGD(rSV<!s7hFt7--JN^B!)dH
z_$3-5Qv$CDcrh)Qq)pUg!C%iqr@hcE000M}P2&a`N8#nyAahXo^*VGO5^i||N}YsE
z+J77trcsU45uu3wo#Cjk<r#3!LghJdF2WXCy1NPw%R!C_e;R;!H{qlU96cedzXKB|
zg{Q~S=ppo^Q!Adr<y1uCC47Ohl-|N%n*eG~36Hx##z$C8-;FyhO#82VL|99oVLKyS
zPM^Z_6ZX<Z&0lz(J{}YxWYc{gD2${6&miF{U$`AC+$4t55aE)SF#5B?!6x*D3a?SX
z{hV+C1u?>eFTV|uaAELfkn_U#XW4KKL<n{B;Ay1r*fxk>5K5nh`%ywaIr=UNvu9!w
zqJ<{PFJ2OEO9ppYn4kkbMyMEsWUR1gE_BBUM`#}qFMR(Oa0$ZqUWFHl!Zg~{ToHOv
zfl89_>1OzpEL=<B*{i}9ABu6O2uEk3GgX+g9wx2{85D-UF6@v)CQbNk7r1mGlb(86
z!gYaAdP8XF#av_yW0jbh9N}zwLgWggwnKNG(C<7XZwmjVl9YU5!BxNugvs<NgF@kR
zRlpSqk5GW6Soi`muUlr72tTRCl$HvQYtULI44DIM<wBq5fUgps6@XL=<%^)EMi{;h
zj@Al!RQgjVbfvg^z3|!hq5GDwoOUC(g{B;6X%NO!HtUYCz;j{m^ENLF+U^Q%R9k)z
zvjxExVcN$~(klFp!bxqyy>wBx3%RsazAyZ714xH3mC9%z2!E%_$WCF$EZFH1F0TRU
z7EWjY?-907!@pkPyX!H8KH+l8BJ~TOU;+0~I6+4X2ZZZwbRj$v22ogOP<SU4GDE@#
z^tJzCp`L<TBf{5d)jBFPvcQcA?^5((TsYB!-*ZAZ^C^%?p^r0^P6;d1FtBOiJTpWd
z3s<<oHG9$iJy7i+>bM6<N6{BAV3rPw+^DMVkjQ_U@|aGds-Hm)i=3Z9=Mm9|qd*)L
z?cV}}&Z108pty+U{sk{wMGf@mJ0=>SWrCY%l0Nk0F4{XE@Z+NXYcP01R7!=(Cq)(4
z(B~ntQtr)Dq?SOLm&oNYIB!uq{eQwK(aNK=^7j$B&>QZwXgR6z6&2OM(izd3ofw6m
z=r>A<`HKYKz>5IUKa{5q6m71Bnjq0;Do+a*&7{M;AtEKcQqPKVSHZ(jQN@>lhl`@<
z=07hgpv*^v=n-A;ks@m#bY2iOtf7^Elt?=cZ!U_8FT+H%=+A{PaY^JxCB>ITzo(!v
zMs!^dE><-5GL*)NzSTlayy!#PaU_V6T%bEq^ch8UuZU*Tvo=X|o%U(TqF-s}dR0{Z
zBmgO*vh~oCDzZ_|?wUwTb^5mJqM5WoOcQ<cG(^)yV@z-vqC^*PnW9e|FwiVftOv*q
z(F?ypcebd}2ikH(xAwucTv6*j_?sshu%hp#=<_jf`J$gchlv7F;$kQ(6a`j*D-xYg
z1XnCl_CR%sXkIO*xzr}Ax&m!wq8+pdE*Gt#3bqPS!D$SpQZz{a3RWf3z6?v%q6u0&
z*NL8`3}n5?76x)lwAl%`+oFZr(bph)`z|cq5f#!iq*1gZ4I)jVKzhM8iz?oS<Xur7
zh4k);KKK(NEh5{3jR3Za#B^P?iR#Y5sdmvHtI&8~w37qUAv!Sz@<0@&1EN#ZHx8~#
z^b7s9OSfnNg|>S{opi#aSM&_MP5MMX(NT|n(I>QGdMM)2yL&+N^A(6Z5-p&G#GvRi
zihT@;mf0v9J1i=g4f7+S0jf9}75!e1NgNY-c>ysl8hIUk6QVaM6)-6>P$*<d^jbb}
z)1t4xg|^2cHkCQsi??vm=OE5K1AwDAm9`uQ#aHg4?~vGkJ(M|#4?hLKVX-@<9FK?{
z-k{adQSr4;VAol^aW7<C#KJ#8T*bchQaL8>dkfm!#Nkwj;4XHP0eD<|upW&k#CZ+y
z;-oli9V9)($LRFEr+Ddp*!2=md85x;>?j90C0;}4jD5sTl%P5-{(U>N_=*?4On+>8
zM%+M;J3sL`ip2Pf_mo0SfcVY>7z`9Qw!q;av6ZT1g2f-v0xCrOayz)Q;scaR4i&HT
z0C!F-+z&vQ_`NMKA1-EeLCblut2=(}3*sn>iA9Me8^B!@uceo7v^WsqB>b_dxSc9m
zE{oM~gT#ne%!blfaUR|9abiCfNW3^J1i%FGytgn<iQ<KH{OXE0?;p69BzB=_LbAB{
zJ9u$bypPWGrig#}3tCde+vpOwCT`ge_;vB-Yp{?ezU2>+E?)RPh%G~0dK)G(#pTyQ
zvcxu8tlSXy(RaeL#jLNPG)LT2g1%gFKo%_Ji9P7)byMv8DMa$ce_aNkKx|aQnL@GU
zbr>uXzs$xY6pKG8hKUmKB3dz(ik~<NpUTAVz5!+B;vPDZUtts9r~AHA{9-69Rf$I!
zP+Bc^-vXH$@#5L=yH@<g8&Fy&wr_`Iy?E(U5NQzSDA0IE97B~Ijp7GX!qOx@NlC0`
z@odUR+!fCsfNS@}e-FZ$7V(#P@UT_v@)xwUi6dCB*Dm&4HuQ|G;3)iiAU;h+mYrh%
zO6czr*Vlt|i>IkLrANGz7Ms1|ozYO-CvN=+fPV24tKsECF=HHx2gEXZ0Y4J&qBQHE
zIEm_Vhs2Jw(ij%EQ)qQWd>|2Cj*3^&)?iFr>4v^>ag6OZv`&a`P{@B${A&pun-af6
zr(dVV56Sn(;^N~lXfFxA58@y>PK!QA$^3nA?V#kdx8e37NzHn=<|GNBVEJLmxg2<L
zL=sDHkE4=}RI=<WIlKq}7s<$P(CI2Uc?1A=iT5IU2OgJvxCdUGkZhv!$R{PIo6+bY
z@th53JSAUVM5CAFoeoTix1?_YfTtvR+o9V>vTHANpOze?OVd~KMg>fqk!+=b`bp-}
zyVqZ`k2cH!lG|Tnyup&OK<EsSNIr&zvl27wzdyH;%wK>pos(pjLnchZ4}j8eiG~7m
z=Osd_5{{6#hd^7T<RjX$UXYBm!KWz6Ge1D`qU6T+AkmU%ydZK((lisJzbtuwJCwyp
z8dy*rD@mFUFXAMtmID_ru^R)IAd%rh!=Kwo9R7vUE0PmuF|;Jf=4k+vB|((yzACY!
zdYu%>pUnWKN+u`^a!vAx9<|pcUwjJ5G>NGkBIy$4agYqj(jOs`DT$-YDogTv2yizf
zU(rJ*Te4#UqtB7-8HI<rk`+{5Xv>p)*#q{b#A6a9UlQ;Klom*Q*+3LZR!l)@k))nJ
z3s)>@D@9+4<n1N!w^Xuk945*o>*!x5DkRY}K`JHL67*F`2B<u#T9QL`fi;qDCB|DT
zv8T*Ro#Z(hXT2nn;xV^ul1gVx@NLQWTY+ehj8i=Gj^sQ68znnu!HXuzXLI0pv!s%u
z9W9d96~MPjCL<u(Cb_f>jqQ?O9Ra^Dsq})<4#`4#)IN|z)1#wP@-1DKU6LhUaIITX
zvJS)Uk$koSBE1sZMgiD9iSseY^h?@ahPH>2d5usrAX#}Ah)0qKv!G^B@-hRBLz1W7
z25?yNRRjPdlI;}O7?t$Whj+##Z>~h&xMc3jaC<^xHbU8?r11#Ilq9JLhNdMpFL?i0
z@{a>_+Dreoje$Byzo31NqcoG2BL}6sCxAF4T@-^xC+X#-P<mLZk3-)Psq#(eJ}Uj7
z86wWo-T#1dk*b$N(pBp68B83L{*OXMZc=qVMBJt8=@im&X=oipPDrPg0dP|K?n~(N
zkbZxG?mtiIj<X<M(x+$*>n&YK>;6;H;AD)~N4o1AhIU$-{VUA-O5dJ@wlmUk%3k_O
zU!d%VzjW(a^aV&ip>tY+QZ|(k21&y+fD4v#DIy*seMrH(v(nj>kPMZs><8|g^!IM6
zB?yzI(gE{usU7WX&P(Hcp(a9V+W<tQ^hMg*Uy!b1!u=@eZ?reRD7Bo1(r9TWJ!3CP
z=f#7&Ed4YXBu0Aa5_HE(Ym#9pPI`zURq@jMl-W#>PE#^5QR+4gEmx$Ch!ERmB}w(^
z7;m!Fz5|_CrE92YFh$x=B}}POUrJ_NlTK1~@^z`x21uq!Q$3+AUD`r5QyJ2i?ID>d
zeSZ(U&yudAYc)se;09-MrEXF*=1B)BI&)Jh*8`9*{n#6Q1=7bQ=(80{|D;%Jk+hSx
zv&GV8KXjHzn{!~PRJvv#Mp!0|qTO1#H1i-VRY-@iQ<_yNT}WP3N$n^TTP>ZP2|$hX
z>O+{XmHI~kP$xC@!0mdeH+@j;mefe!PP#2^S`B!E)I@voJ2q+mTF^#mFfE#!q^r^a
zY?d<RaOSS`wS`c6PwGIss21tjHBi$keX0*0wn?`HV1nDFMRYsdmx|tj7ah|4Nr*g<
z&hUUpr}P$uBD$n2C{WfdZTs)Wlj@H^q*q!`HS>K^TSyjYzjQv;=RTB{(3LbGeT7~!
zkEE~A>wQp~_XM;JNx#?%Zdh7P^+_Yr396VLm2RWzjxniz8vc$;n|h#ZLh5FQ<fL?$
z3w)ZAK1pk;X=&6F=zJ{Q%K^?__C95H9AsN<^c74;S!5TSIw;GELF*ye8}{IwWaDN4
z56iM?<9kGA+KWjzD%(ddduQ1grFUIqua=_GRkoW}CC6lcJ_op)>@`Y9yUQHt$jx!t
z+|ST>LdN<Qc2CNj{y?9H?DR_@p0aaeHhAhKJMaQJPsv`TyTeD;N~JlcWk1o)<ttnF
zDRiHaWv7Dp$$D3y(O;H9C07A5Hl4c-ly%XIK1fzfCzXO_*Uy0qkq!PA?T`giL@`v>
zOT}5|WZDm5Axw6FmfYd8`+w3N@VrbztJVnFm>9DcDGLx{*cW6Emcyqg*>>8ET$H_#
z0g-6g_AGFhWIp{6xhxx_ilP|V4nMdSEBlR}K5?>}jp&P)y-i=YNsuM%fx$%C_HV#l
zk*%g3U6Sk|J>-*R`%oE<Kev%>coo1DnU<=;Qe{>fM6by%lZopxAKHDT$)+fPn=V^=
z3|xjRo(7sJ3!u8FESaVn<c93#Ojyd6P0oaeIkJvu_?s(pq!@gjY&SiSZ_1YJg-C%c
zsv8yxW%KOOXe*L=P$Ifm)=&vViEI<?bV_9dS7ESB*3gXKsa*EMb#N6j&MV+5WnW0Z
zRmp;Ab5Jb{jDVvxvT?ffYGq72n6HyPKM5`MGJ863bW2u9d*$1*fIk3ekOlj~&>dNj
z61Ya2to=0%yGiCtakFMw;b-veuB?q}knYLeuK}<{_T5a7R@wJ-tfo!&4((LhWuugE
zzb{)k0c{<!#nsUEKqjYps7~1yDroAG?Vv<cx2(1Zq(>G?@$Oz(ApNd=va=t<-+q~G
zhz_7Xlr3M4$rz9+C}Q<U7EPZr8<aU(ff$m>Qh*qiO^3kli0t1fNRG<v-$vh<Yz1Xz
z$7M^GKx9JJO^b&~ncr9NVoGNG1CrA+a~eb*%cOPi$zERa5*&4qNACnVB-hyfE0vb7
z@rA*|@?Um=9FcSAraUUY`VKf}`KPpbbdgIg!eLi=KAoaCCJ(2Q1UI=>0M1>$ltN?2
z<tut%@Pz!=Vvv(^qYp$p<o9-B@;v4L(5lW${@PqP>Mft7x7jIqxi{?redLX_;5{wp
z97n6KytxQ6XXIbK1oM9K=L<mm<)5B_7Xk9`zCvH1d<HFng5=D8^aab?i$Fr;`!0f<
zl|TLi%0lIVZ(%OZ$r~x;8YZ7hL7#B>G}S7empi@(c!d1Sw@=~zi<I{Z;Nk`O8?S>z
z$xpe$(k1!(uR+aa`PXj(5hH)`H8jS`caqXLc{FVd;^i+)KqNuFUIw=l<zG{&$rX7q
zeZDzKUP)J3vfTYFe7Y*PE(JVAp0pddRJrRKkZbY`1oV;TlK*xdYSQFB6KGABKXC{n
z%#imkLu01=8@dg%<cSt2y&*py1(9s|`8dp4j{KGLnDt!wdfEf#$*)r-#ZCDR2XOiF
zH#Y%SAfH_cK%x9~y2Fd)Gj$LtmZ#AEu0;Mc?VN3;^0ohk^5uX3j?QxVJz8&9$bSlf
z`<3$QFf>-l57RTST7HsFTh_?`T7|w^`Cf{_)XBHg%c))-n2njaC6`hv?6!QAiUu3x
z(+v>0Blo6!M5BC@JCrrammC40S>8jr+`CG7LlR`}$*W9gZIMS)$hB2IN`-xG@=P!E
zb;#!=K=gs!WWXeL%2m-&(<S$#5MQ^vc^62JyvL{F$tT{l{agavBf0Mim>-m{N=Dz1
ze9i-yAC`Yd5!(^@Mk+WPm4EvubdJe$pN7b|Jg^sJLcWzw?@r2R9fy`F`7`u`Ov@uY
zVD_<m^{0T_D?$n(;-GkY4(8BNv4N)fphEU6CgzZ0r;RcnPKs#S2pv{DRSxcm;^_+L
zKB@@%0|;lu-kHF=D0WccrK@5+)vX*;7%A}OrZAO*b63=P0(V^T6)l}kEB1K8uCF5M
z36L`i!4Hu1Qw-34(O;q62G;@<3n&W{sQ79XMa_d074&2aRs?<vE<|BRsoArNmF_Sf
zs>l<AJE!>RE)ZdgyR?7{SA^54fb)ui%NRw3V%sqKA{9qR(Re|zuNuxoDK^nU^`c^8
zCjik30fl8RDXu;X4=*cz+W-=y*szCAX2dGQKY)!>3~+&uSH#ldAwg05Be+CGK2@k)
zQ4GHcktBu3-yq2fBOO1wsyO%o-6M+sIl)A#;=L0vaZT|K-Eh|xm0!Yqn&JQj<I)u!
z&S=a~y#53Rn5lT_A^_Qn_;pm7lcV_O6k2l?$+UXTQ*7G_r8gB$l*Y_gyhIfh1&YHm
zs3}yuumycZ3Of_H62&AHA(SfQt-zHj)RZAASCriZsZhAn8OTaS?g+Rl#aqJ|OSR%l
zO7+($ex!=4T1E1w7>lh=QTY~R>J>S(+`pv|Q+EEgqAmf$Zcr@w6MapJPwCm)tk|Id
zxu^Ib1Nat2^4D;tRWWY}B5jH?%DlHL{xQMd`-;#MXz5T~prG^v#dZ^vbt-tYK<-i;
zi-c?4idY(8k4;hM3z=TUuT;R&rwFQp(tbrP-S-a_(;bi*Q2a($@FT^iFM%6WeBuvn
zLyFc+kYUB%OCTeP#WP@VR8dcRoiRlfg_Xt?<1GM8C_J;Eb5e1ELLF0z*Xa8{(~3Ga
zX6>=U_9~?W9F&2V(CMh07X;CR%07zl9ai##(RV~SkEZmf@>5z%J1avULefP!*9=Rp
zN+0?fgu62PCIH8k6Z0W*Ldp6XBA!Yi70-DoUGpH~t=uC9cS<RxpU_A7Zv`YzD_w2R
zV@iFMAJI9SGs^39dHE^VeF4Ayl`_g21Sr?e13pmsOc_LilobN#4p#2-02iW^Qia-C
z<@bY-3{@_E7w~h+VETGxn9{xwBMet&`=Rf=@+7^WBb3jHp)6AQ^v~$Kpj;C|JBcXe
z`Tugk%7op}7OmV#H8Pi!+rr`6Wu>SO&crB3RzXdylA%IloN_}COvEe0w}VSiPJ9C{
zQR(~uy00h~oQ2LLC9?pICM)Y|AaYfCPJ;<bQQoKMd#cixLblhG=V#Bt{g<wEr;uWX
z@?TmwW-8fKahavu@Hxm0rRzt~ovmz&0hgmxBtdDeGCv58<|%j9fZS9*l@5`7<wIIl
z6)3-;Wk#X$c@0RB^6@Q@V&y&#;3dj^Nw8b06s-cFOu7AS$|#g89TgZ_g)-z@=&n?X
zQ=qg;*+h%?YNdY&fHlhUKydZS5UO0frM$TYBDa;+v%obdhtfgrC=bx%u2FfP%E6kH
zWo0nYtTaAG<6R|p1OseUZhH)8+LX0)Fu7g%{xOKy`jmgX3ElllHHAYSDidY`KdAJf
z6zh=k2YT2KE8kp)z7gfKwXig*ET-4sn6l(KaFfdYR2M&`^nDs+T3JIwb5L>Vh=QZ)
zm&MR>P_>H^#D`Q>k3gJMceX*<VU?^Lk|%7cg|yE;sZyljKJrjK_b$wPs%q)Lk(X-i
zHCXai$$vuMDb=7CO!%m_QFP(7%0@HmtGYc0l4n#VKlJ&jzNMY5ziKH3RRUDM(TU_h
z)${vcFj%#h3ME2R@8{t+IIG%2@rzKEt(H=b=Tw$fuwkmT^t_2sWuF8vQg!wk`Yxzu
zQdBug^?Dl|y{I}#^AxSRMKy<)RP(7E=dx;VK15<vKP3PVtJ)(1JWh2W2z~LY1J8j=
zQ2D<HkwlgBcZgh3N&iJ(l8R+(f>X(=k+ra!sv74*G);A<3S7Es`(}^~)$%D!Vy0^D
zUT|5e)HVQbsAm6$Nyt|HMMeHOs%5L8G*|WPAmDkbI0_)&R5hP~qxq_Rl;bZ@&7!4k
zp(^V)Ol6U3&qe@>RX;k}AXB1J&_<|KW!?aMnQER1T)9e6g}w?^3gtShRi{Hh?x-4R
zf!(O8dJ3a&Qe{)cK(i`iKZbT!m7W6lJyj0{09#cDx1z62HLDJi?W)wjVgA1AD+*_H
zsE)4!d7%1>Pw&4@RaggrT`KlLAbM0@6#eg2^&bVIPvuUl{eD#!&E-SYXLR~^K((F{
z+K*J<7Ge~GsvG~pwIS65H*mwMFKM|wq6*xNnHf{X(;YXi`eP7UCRDmV(Ko5uO=Wje
zs%uP&rcA5Wk#CPxj{8CE)pKZ(=Ae$sz~~*-^Yy?VRCoLV;32j10W><PC)(k~VRcL=
zlpay9{|(+BRewxZnX~%34<udGw<#~-u6Cg6(-Z3SA*ep7*37{GJ=799N8_pf(H@O9
zFZEj#ZuVB6Ooixab>D3a##jB9KRVB->lx7Pr(V1Qeg5iIR{;!A$MQe|)v*-Y3{r2b
z!LJ>x-uxD{oK^c!WHwYizY8Mg)XB(;&k9qY{S5GM_1i08{=9na6x@zbJJQNJ(x!F_
zg_;ZMMSGwoN`3iNATFv8KLIt-Y9pO0xU6=dCq<0<N1EVRb+;L6;?$qgXB^_yyJ$O<
zsLrK@)D?AP8N5hRcO*kuvih|oh+I{NM*^3kPG|v_s!kz$*VR@^AEl{ny|*!K>FQqv
zXw6W+yav8ys&{`1-?G$pv@*Y;?x8Qi-Bgdijk(BIugF1Pfx3h4^g?wRMKy}l$urPb
zqUNOnP^xZhL|>Wu03AB6RKH8`Ds>g5@~YKgbhM~OJ%<*-wdxKV9XYL6Yl~s`mRdtc
zif^m;*g;LB`n6Zl*Q6F3F_>oc3y)#<u6pTZsJW;9Cli1cbvOOZY^(a%?~rU)t9>AO
zU)@dB<{fHVCHfwyt0}0`spceOX1dg>RFH1<<3T9vQUCNa-G9Am1LdC{s$D6`I-vF~
zgqla{*>b2ERHs{^dq_R64SmDv6)ylks<u9c$e7xbY7@rQyf+~-q5e>W37%BX*$Ul{
z)ec#ZwAWbv+r4UDq_4#}YN~ng{-EX|#ib8vio7VJcUZG!Aw-X822O(<)x6OQQD;pX
zg)Ce&mN1CAX`b$aqwbo%IG8xD*(-wi6PimY5ILz?WCiiiyweW2r)C``%Dgn3N{IMq
zwqHQwX-y<WN_;idwB<RYnN4p>Kh3L)=>7}PtT_%upe7?7BuFz(k<t)N<#QPCS<N41
zn3+%w%Nak{In9AhFdwEFtb&?wP57(mi_oa(+)$(@?@1WEpjklg#wg8RI$m;7^D&mV
zv!XRu=;?l0^X3Y85u-^zipE%ti58W%IE^?9BaGMZXuhs!BEQ3|Cuvd)P?N0je+v_Q
zRr4N+q-aXs13pzVKz6TbY(enwy2gu=H))!msVFF2^9ltCGc-R8!<kG?RVYZ7W;d-m
zZfG7-F?hCSe=H2;XeK{FU#?9PZ-I$C%@GQw=4(1{!0!T0ApN3+n(+_dX^}=j`{ZKH
zhgnclqA>)cuT=A=Gw@{^H>&a~*Eo$sONE9J1@o1fDau<^X>M$X&T7pAT0hokzHNp`
zttM?BxH`>d+Sb%-Y^AgjyQNwCF4WxC)KleXgC>Y-LhfkJP>F1lCX*f*&6*ExVDxu2
zu1nE(PxBHbQCc)7>E+a_SzeCOw`pGb41MjIO%yt~uQ|2`@D9z$5L7?V?56stPR%=%
ze(2JO0s-jO4DGm&q4j8b3eeiC8G06^Pa}8@q+jzs<>&@9PqhH}NK;EMnL&-c27M!%
zO4@6UYVKx(jA_<HfsAXU^ctMdT%*VHq{jLc+@8`LrZDETrpqT|;S<l>mYZSEQQH{^
zk%L+l-D!ukTPddLq@6nljfb`MRQPa2`$-h+9n~f}qt98}{1yCl(aspcs9m+WR3?8+
zn`#E<rfp3D&Rv_(2Gz&4-_us<gtmSaoIj}@(!mK2?Vq%o^VIIPY2l2QHtReb_11pg
z2JVzLnvOU7XcOqiKCPWY*#KW{0cCj4Xd`IV?Wg_UO#uA07gg{gK)Y@lJ_Ty$(rP_O
z`)?-z!CK`*kWj6XUdiXQ3*Lq5Fs+K>o#9#)#emLh$KIwrX@vF?J&Pi>?evMV3)(Gn
zU_MIQcL!XwHi({Km$WC&gIw0mr=3K+wuGYN3EHL~;7p=cK%4a|+EWiP!X)j6w_q??
zd$SOISG9X-m!G1I`3K5UwRMTGcTL;b0?F&z<4h{jOw;b&08i7k;y=)tp{+WN&P;9M
za&TGN6xyZS(E9!iyV=^f4?uFXJF;OSSKCNSr#$T;I@NtstD{RMUwg;}q(J*xCnO8C
zyXlfE($>U6q*yyp1VD+l_!3+z)yBR_!P_$JMLnjiT>Ie&5Ea^6R8dl?jiTAB(w;7d
z-__b9v^K5L>g+*kwX13CU#I<uas&0+?-|f`OWW-W?zZ-WAAxJo&NX1zceEeVlDJXp
zHUlC}+8A$m(X5@h4t;mEuTe(Rc27G>H$aOvVFCkf)$XJtSZ&%rXF{f3d**)t-q(J$
z9*rINnZP~JUUP?|o!TObA$4gbuS2q1dy>{3J=(pV7;mrEOmBrg?ZAsL*so=EgL|mG
zo)2z7JCj~9kF;$W01Vo++Iw(#NE`kv$guWV+NzCcyJ;6WuFcB=H=%W<rNE?ilRwCm
z_H}QVnAUzybuo{%O-rEEUU&8|8Xa^IccIi#=eQIe9@J^+4SPs;f}T%Kx}SOhKdk$8
z8{9sk3wMCzQJw7{N;^91W?w<8i%vZT&Q+ID4#Y9t79n)I>0Ib)ao5?=#dcih^EpIL
z=+>6N!;`ub6c6{%)n>vOPhIeC81&NZ4#fz)brMRNp3*&Xhoq10+yPiPty@I3RKB{M
zRMB-t7h-!6G6A~ps4ga0r=aqQ5ZxA9%%0W#5(V9%x<&V)^qg)T)kKBqPEc$mTsM^m
z+<DzHT7pFAmUX~Hr0xq!CtuL{?}U~pog>BAFY4Z*+c#SG>jm^((tR}(j$YQKxdI-e
zOSnlH`dHn`afrt0{HS^=UZ<w*V}foUrF9c^ODHsYMfce}G$!d@p{qMtS4G7VS9O9q
z*iF$Hzl6W3x-2#T*K}Pq@aejac@`$pbm=bxm#+KbCK@wzn^&SSQ`i3-8nbkxC+Q&A
z4PAdWI<s|~s6Z=6H(CUxxw<KOtmo-m-hjh5bxYoZNWSjIyTBLdQaa#8q3-PuFwi31
z5(z|#br*21a#o3ME^T>Ab&-6KGF_=2u9fQ!QT=Cy?$9p)RO$|@p`}X4Uq->(YF#(o
z9W^?gGwjytwr~Ng(=ncaiF#e8FYvc?M?b-MZ|j6x(bue-Hw8=gbOs73wdj^OqOVma
zwgAwkbEf@QyKeClFmYdZmzIGYx@HMR_CU9iP84?PxO_<V>k=+Ni)}!+i>~}fx`sX=
z26cj1$c*TeM=+*QT|7m7$8?Fbq8QgTZGrg-UF!jeOzK|k0XL<4&J%spx|y`3eynq$
zXSTim2bvNG{WTdlM}0H}Cl2c0eH(y7`jBP}$w~iJ9K1Me)2}K8J)(D_YLuh;KH9W9
z>(9{k!bQLEeGJW2ub|}eG5t7|?6~PaqHjpK>kUKDc3jV+5|a~p38g?!>Yt@zBoF=A
z7l3=}*|$Nw^tDB3^wvK`8=zBq-BTE@kA9C3@Y8zR4<EsVul~SYkTd!e8k(QpX9Ill
z*9TsN!2tc*2_ORXWtFfLr2mn^FTwguJ(Py%5C0BwR)6mYG=}QG`)`+_U!?>WrdLK{
zM#J^(d4QkSM?8tf2z?G0sw4H`A7Y#r^i#GkK%?}<3*qTS{g=ByqV)r>z?n<>J9KYf
z);Fz%Pciyt58z|<J6EGIPVYb~zIgpgIs=@bZ;nD=qJHhW=)0o-I{|%3`eItPChO-I
z;l)+`wyWS$^e$gw5>oY96xdDEXL4zmlCFRMH*{v`-(W#arhYcIfwQvot%ouC8~RyP
z9Gk6=r(JW7KIuD%<m#{5Fp50A<^n`+>T{Q%F<<}05JU>}9&`$%P`^NfkrnB?sM@|*
z{}xqqm*_Q1;BTq^$cuoN=?^XWAMU?$eg8Zdtk5t03BFb8TYbS*>G!<^M72JWs<vwM
zGg6_ZR==wPq)xw(HaYeBBZtv<OP_cON^k4W)1iz8eNGcZ?&u4)p|4SI&|xl`^ed=%
zzFEIQ36Z<{W3}kJryoGN!#1l$-;oG|t$I6pb==pNtbuPG`i;vW^FaUev*_#8Kc0a}
z=+Z|%1CegMo>G!M`WGlQ(W`H#3GUNdvoII^`o)w;dZ=Ib2e<)!933Qhq@VXZbPnp@
zpwRV@zKjAF!}^0Qm>}DT-Y*ntM)ilEgy@)FM4pc8=Uj!~6ME%`5S`TDiH6cC{m317
zF|8jLLh`Y`hVsz%hI6A(<6zk0k48ts&7}}IXxMrRjfV`4^PtShuoh34S%(c@{|zsW
z7#7k&kD~_fOCZiR!<;R!<YI`Y9D%DLiQ=`#4E6s)jhkVLN*LS?-@XOzxZ%}K7(8JZ
zb%3RlhKRkudl-tTe8to7O+R#d8J>BFAI94dM(24>86=M&dD_r^9B^NQawSC07#I@t
z`58{p2GieQJCOt$U?}Q>wm`#{&FBm=1e^mR*zkzb=OG4pAsWvbe*OXGLk&wJ(Rj`f
zMB%Y8!zxNLg&Usv9OS&g8U`&91_u#DA`KVMK+8pg_s6gsZTROD3|%rz`oiDKhV9Ql
zB*yTfjmlwT4NqT%r*Q@^DuRqR6na7?!SFxACmF7s05I7Q>VpZoYWSl7lGhA}Xcu|i
zu;V&hOEYYmgT8cwJ6*>ahJkOuWg7O<9A+7AQ!Ms|VLTaq*#^-J;BpLeDU6Y8c=Er6
zcAjDQC<b%Wz@z7SzG3)vh!z+ED1};R*zf?P$dFtCyTyiYX+>XRXovw<YS6BRWSPO?
z2`DW$@aWxIVQ@79P-)meaoQ@wpMBt}4KHtkg&IR;JS@~2RG&h!&d~5974Os=wtfrt
zmZ3NhGPezn-Uewf6z_nGcMPvm8A_u;&;e~thV!(WYc`aA0Ki?tFbCwGVY362wiv3{
zVAfg<McYBz3>mutXg56m3h?`eKFWi27?^DQ6b}r`X`G#g_}A&5k-H3y#Zc32xbrn+
zdJKj1rHEd`chlhd3?84rV80=qj`ck>d_+%}0fX}=81^GW%gc})G$b6rTnrh~=mj!t
z7^6(mh+)-c*c~<Ws(>3axKUJa+_3j^jBLX2p&osc1{NP$Y*Pj!r52|R4{49}*zgsV
zPS_j6o1pEW(J2?eLq>B5h?CKS0uYCdca@MlV*J_;+)?8jP4L3m_<9tyxfmB-!F0PC
zL+Cko%os<<r`(K;ci@w|k<kb4xUrTNStpEBozQa9W{h%xsE6?!C7C^qKlwqamvQSd
zsPQ&FHvpMa#$H<T`505^S#;Vsxd)QIMym_BGseyIDD*SN??t1(G50Cp0*q6%atkyb
zr+YKVcu@e6U}Fa5RYQyqw?gEsv0@lLg&J+kzlZsAMibptVa5-rDl**o)+ON28{6Xn
zj4(!y0ugDf-jBYE#zHp$qKz-oEB2DnkD_~*jp>IlhcU*<cj0KPG2>Z`FwQvN6I{Hp
zFCAQh@z4Soyke~S3yn#}4tnDx8+~kR0K95^p4M|I#y9I=;+l~$0mOCVxp*MbjPKrn
z`E+Bs1$`ODc^3i9G?vh+GTRvX8ANi7Z^lDut}&5LaOWA%9|3pM7)X^~`NkLjyPJ#?
zFT(9YqwlBix5zl3Rx-s#m8T8(5@XEEFj#7ge+R%aV=vtY<;E=|Fi~M#eGh6Xjq_;h
zRAmgM?0>a!6G_$>otD70TB8%?DeH{Kegju;JU<E#ZyEjQyzy;g?I*C%U_2BDWp|7M
z5&9a9byT_7Wc*<G$pyHbjJaRKx4Xu>KB70UBd<LJZ5_tTbQJ%AF)$5?PUE_FV7|+E
z?HGXF#uFw0dW=)c!1WscxedF0#<0gA{l*=%Uwvqt<qk&&j6c^w*^u!`dddzPRdn`X
z#3-Z{#i+6BMZm|5wKSG-<Hp_iB_@omHZ4X!Y0RK<kSXJej{%%EZrTO+9~;+DEXm%~
zPU|X1)9MBA@Sy2X766A#8IK_1WK!$~;IL`KpD=O6bp5~MVy0)QI^v{hJ=M8+n1-pU
z+|y)^fI%<Q<|LT+Htl^HI!~KsU8K;1uc`YU@MlcUyP@09^kF|b{Y|sg5DhRjQ)V*I
z^iwpH2AN*gqcPZ&LaD_N(?W{SoHZS~2QJj~Z5FhgGyO^@3c^f+b~J{YY!uv!F>UPw
zJl6EpD7bi&>JG+|U~2lA5@3lY=LbMsF}XbtOG%~=p9D!Z?R*2eubL+53oj|AzIKcv
z)l`uQ$!jLVZxFd|Dx^Z0G?Tj>MAA(f#Peolm;$NZEYoy`qOVz|d9<LpVJf9vMz(2y
z&J^dEMm(T8*W|d9K24ox+D8%ao2DGfPUo9uoJVJYsr?}Eg{I9x=qob0?T6iBQ`sWu
zE-`sgLbuf9JdDONQybO3mYd#K0237^+ayFPO^c|Kw#vlGL|?V(>o?(Ajme9WC$%Q~
z1?a0Y1=8-uR&OdF2Ybu(3LS5~ZQ4MQ-A0oGt>>Cdh7vS3oBsY1B6m&uy)lXROb4Ce
zT8pV*0Z6Oq<P|iwnG*KF`*zdyeQ3OIay@{V=`gv_j{1Q~MVq8fQ#u2r%e3Ym8oNzj
z+n~C~X1XAQ!CupM=U}kURQM2<`b`d$y?kg|vIqkmFnzrUSLY*>?q4(xnpV~VKV*72
z9JpcAH<XhYG5z%u`bJIK<?v$6G;baN<EFm~G2RK&!C3%InygMRKV{O=Cz+;AOKBJR
z*kt=t4WPZb>rJ#en0NdN8AtQ8zXN~J>`z&yL*^XHa5$O&q-v7G=5{VTJYqiKfkqee
z)&h*e)$G*-FOHc<Hvs2m{+^1~-OcY%iSu#uD?dTxgn5-e44yQ9@EVAR*?tB9p5_AE
zMj*V*!uQbXZC-g7z*FYLJs6sgd6dcqPMe?n3O@OoXPPjWGv?<h1np-YehI|iynym&
z0cKAsQ3*7^O5xfd^D)Zw1)EoUKud_(YY)6QYfg9_{)U=QL;`otTuvd%F!RMqTG@x2
zS(jn=ym_Y?(;Z<>rBhjv=6Z?=T`-qzfk>1&pCW1(&8N4(i)eFI5F{^|{a=KM%Vt&}
zbjO(IX2N`|`F+Yx#hI5KKx4f5+btjo=04iJCYpa`f?P3+UV_df^MP0B{!2Ee(h--d
z=2+S%q?iXD0H11poyrETnO~+w+I91j%OR3xe#d}mOE-H`d2NPyl@ZQlnje$FEOW;q
zn7?6`(SkSItf9AIj+sfvp>oaJtRQ*j`wK9no91*KxO{Vj|NmyJoK;{RKMQSz=2AL;
zUt~W0-&d5(b7=WoW`2`mZ<S`A&%<}{uwJ|lCTh(s0Z>zCj-!Nby?M#Ez}+$%TfyBn
z-`fH64d#2aGrnWq+kshYG+*q7NR#;*Jw2MuWmH&j*F5kiwA?cfIzh6<Jgk9atGQ_g
z`r6EIY=W|Ob1MaE?we1%glX<D*V`yR^T0f@35ZVf(sLkPX1_^@cAI~pe{JnCPtw|@
z*SsJBUi6uN{09d6&8)Ss^w7L|K12r03&z1cGQUU9nL)E#Dd0oq%ye+WX0JeSBj(?3
zLG`FPoTAKQ=847V8#k-Q>0v!#KAH-dNpr(on3yuJrNzgz`Mqi&9-E_R7iw>L&;>~c
zi=hL4J6e`d%-YG4HXGUwTmD)Ga>Ua5IRHm3regFtTdZe5Tr6TLNprKvyCC9j@uuM7
zaZA<%^m$nRK0(=1Ps{Ig;MmKuY!jx`+Y)dNqNglhj$medEZ))RJ7ekn2Cn&8JSV{U
zTM}!aG{CZpA|`<rUj;~zW&0xN4z@f^TZj<LyR>3FYiXnE=}^n$yHIw{lKCM<7G}A>
z3L@baZzfeMoVUbY0~=vEZ-Sag%O4VmUa;(vVc1cY4@;r+qUDnpF#2dqWgGC9EDE}*
zE?ahIL3fPh(*|&{mh}r^FwU}h4@kTvEF8E5%PFcMO|(qEf{W~mr70eUk}TWly_sxz
zhbF;x)zW8xOp0aR-_Vw7ky2dznq`>Qde<#a(kn8}GUquordxL31tP<;sU0NK^0yaA
zmSwj9<c1}To*vnjujv_<W09RiW3I)R3)k{2U$mp~rp5gwj4a=>m0lnP7NZcP&}O+q
zPs<|9AAK-iY>A{Qr4maV-43OeH}k=jSvu~3lv`rxv|WXzAqahy7UPdFQDvDb2Cmw2
zFAhViu_!2pTx(fD`HDJAL^b;AErAp#zGZ2t2mH2WZZYgNSf&kVykoI_|2O<@w&<ur
z?XIPg@&NZN<@6P?7K@RB&#e~Mlep&EESV+1w_9RnVJ_}lT<NFiupA)W4=mh5Xz8?c
z(1$0wER(c^>9+j14CC#we7qaVdM#<eP}XPpmO|M5mQ@r$d}z_wq%b&OS(Oa($npV&
z><2CO^y#Z1%U8cbX4o=GX}A%~1ignwEv~fA9<xNdfQ(yer7$>QS<(&Mq-ClOl2aBX
z?Z&1p&WF(V*z)H%aQ4>5S@6lh`uuG8>u3#(g~&l`Y!rpE4_QyrQ_sn2ZiC&!R{aKO
zJ7Q(f_Z*K}dFNrt*}7~65H8k;81%VXZ@qxNW7Y@?jJa7`C<Nwi71Ed7j$5};ru&3d
zK!-q2T7UEh=V4v{0t|UtJt*AdW#v-P%iDT&jIyPttU+lI^|8(>#w4D$CVmNLe62yW
zBRFI28UyjOmQDiUZ_W4(A_3O7UxUFwt5-9)AnP}Fa3<LLdpsILtRcZrcGmj65440@
z-6_KtZe33SjPurCXtN$+t)^vul=Vg^-G3LYPSe0gTkp~{Fvj{jz06~+kAmTMoYj}2
zzwuTLZ6*_}$LNukXg!w;XOgXo2bh_w*0~hOOR;8BQCF%pnkp!+Syxj==DPJDt@zTc
zM#|}>TV4MvtF^|`<2BP-BZeVcmepSXhi_ObsmeCndgLFF9P83=Ad_o#y@kF!>+2NR
zy=jf6LW+DVs|~sftUFSGFSKr=muZpp9wo_&t#wqgTVl0PtzxP5tPqn|X5G|_(U)8M
zDE?Ss-T4%pskA=$9wJpXYkLJctF8VNG^?@tP!y-u8bt@v>#R2@IahBD{1}K^R%03Z
zZd-Y@o@%ga(tx{Tjim%~qjeqCRyJ7+>AGsR7KNg(#Tp$5?^~_K^fGL-UVI%o+pXm)
zko(p&Z@ArIwXLBY&;x71dbD<0H&7U~%i2nbzi#U_dTjMrGaW&Ctq!9YcAqs`{eO<G
zJ1)wj38(QH(-WgH(G*)^jHatGiN+XHOpGadz4zV^({mI>kS0Y@5J3e&njlSjZz3Rq
ziWE^%5D=sZBJF!7f6Z@aXP%ked&}<3?0Zlc*zsW%TpQeRIskTucEr+w+Tk5<eF@2t
z9eUdC-rMml^^NZMg09Z79WPR}>;8@s0o2ELtPY0cgB=SU(deAm5hDlo<PPp#z)bC^
z{1MpGJIqvo<;wW+8bsX~i5EfK8CmZD+k<iA8V0(DvF1~NdNT4Opy0(=`~k4{GUii;
z-kT9L1oJ+OhiN6_%h*6QT7Ha1+Vc1_X8OV0$M|-Z12O@OZ=QtRK*nk#e&!&C(@yvl
z%y@;?kNX*|wGchPNOXW1!g!yG)(<kCrbqZ8hVyoiP{!LGFc{8QwhiWwFphZwGlJpR
z4NH-XK|Mr{GQOao$}z@ovoX%&j7R8HOB5r8N%vng<IgzAoM4nK!U$s+{`GJsmf@WV
zn3Ig?6=23OT9-jTo)HrOlEBzS3(rKx-)}=CiLopmpr;tPMR5NxF0O-zDU5kW%*<(q
zX$q353^!V?r!h)hAd=2-L_;rwF$<3*oV{W!qK)4fMqxO(S&VKK^s^b|6hY5nlv1)Q
zm+|f+u$#wtCKw|5j58PEZvo>LZ3PM$v*|)EVt9IkS<H~rW21yIB?U?;W8Pg1w2ZMJ
z36kZEy<fpl1>;-}T9ph&8NeJ>45wCLpJkM9L1ztPgrdgh8J&3mt!KQn4h~;nG}0TO
zfl))JksBGmZGwr5j2<(Xml!KAV1$<$mbqXyF_zN1@e1SP&FE`o_%%YIjp0v~L{}N*
z6ai>woSqNnHAdJ2n7{5|1W?8E4MzVK$aF9kumN+E(M`wqZZX>S0Q)xMDf$$5H{(eU
zDE2UTKSH68@tFtu`WabN>T#FxD%B1RF%%SlA7*&J3^Ky--3ZAshMbO2-DmKg0m?W-
z-U|;W8RO;Xn_@T`C{Q%bNKygKmHEjIz_>9t?uIk&%(vPg>cKSCVJ`PDOaH+Hc{08B
zpykc<?uRoz%;oKn^kqIrALQD{)YHMn0A|_qFc`>uY6N}znb+n)@&NPG=KvkTG|<B~
zl<BHQUl{Y0<2KL^GYcsN6~X+S>hL3(KhU*vl)33!Xhbpf+t7+;?wADj3Fa&ck)C8G
zU4S!j%r+iKJaaP@+a@tD&^ee>%-`ul6v@mCPqb2*F=ptcF<+(!c{=mq#ZWlI{CpPr
zvY3_cIzY3TMRaH+kGVS^iuug?c%T(9PlmynVx}n#trBJwm3oyjm(!B3f_auA=#|WO
z55t)%=Ar+NHZYs1;{PJ^D!tq;F{SjBzsywAo~4O-kxpq{VIBwuvz58=7np5h_CG~u
zKdv&5dqSg~`2i(Et})|Q!Qt!7sf!>tn153krh_@Ihozg$FVdlZiy8GB%y%*e-O%b{
zCVvF=Ze~{{T0PA7jF9YQ3O|G0JIv+uamhYr${q~+F7qR*qZ(jl{(`v}WE%1)STMwV
zk#?HH%y+cljxbNtwrGs$CIq?9Ts;8Lac0}U(4S<o={t*4%zt?>IL!=u4Wn>jIn_eX
zl@+@TKDn{Pls0i^Rnk9K?_$l`fMI*ElBdAj!}^}y^Pa3p8lV?zkiZ;!S?!-e(VJCI
z(I+3)PzZ=Gt9>!_{aATa^61af`-1Fa{rxVy2w?rY8X|$LsZRhJ#0q2sCYV+8B$)eI
zovm=~0LwE0c0*XN2|*6B#$BO)h{b*ZeW9#pcSACql|a|b5eMs|dYF%3MNq=y7%RUY
zCXTZ_o`PZ&>#0TXG=^2X36^46Q9;l@$@)bDv;>y2AAO0eyUQ^8B-Y*!fRe&0{~B(e
zW_?Y|*Hl&r<<T-&?oH6kWUbo>lryYQdivzB9;0|(F3VAV1R8lP=~>7WvSv{vu86gc
zK7d)wy7CW(R>oQp2JCWHG2QnStP7QptYpo>fSsyXZO?#tmNj1uXR29C3;;XFx=6Qp
z4J#uImTFn^RzjqX<@zPS&a-B1hZh%EClu&wVCfz74S+^gI;E~IvKsyea*1W!0ny8>
z86^~(SkJpbw3+1*3NKn%cV=Lsm35xpAZ@JMl;OC_Dx(NqJIkH6YS&nYC_{OjHL@O(
zH&_9uV4;JxlO7Z|SxOr2EmoyB$Zgi-0=oaYS-n(4)Wg!yVd*|rH7%d}Su$D#+-0pF
z0&{>RrB&e|YYx4KhFC%>K^kVgx)>rOtncr^i+ikz&0vnQ-lYniG1jb)K<=}$Y#`$-
zC6&uPV9iycHNhIARO%$_<|L&rrdWrL!To8L>JN|^)}K_w<HB~~Vid0ITg@PD>^G>A
z)}6iO3H0q^=h0STH@oWzIO@UvcNY5guvO0h)RWDi-^Ytx%>miVey|>r-fXi!P<+^n
zE%3sZ9ZDH`KlTkAOK~{)vweKgxsScO0=@;XA3O;X$TqY9G>Col3dS4E?#O}0e)cCT
zK@PABPXH!_{RJfx53)a|)W{+Bt`{%~p=`HU*bQShP;~DwJD3W5!r2ian3*H&3<gL9
zyM*rBNOl?>>UJDuS8u^6j<Nr>0rWUKl(x1}?BSj0jAqxJK<fnitOh1x*pI#e6S3@A
z3dEmecYTK+HjZ7l0|w*Sx1R+wfxW&7%tUq;ouf%&Z_WesDfa6t0G-Tc(|bOJty>9{
z)9j7(0!ekSm9*tbV{i5VOeT8`C9=-I8IUY?<59q5vv>arlEY4;99u3siX6>jU;iJl
z^V#W7LA`*zn{K>9w!ILNMeGm%g}=q@^i*J$uz#klbSZoGV-P807o-8DoGlrEdIj4t
z_cXkzWN)M>P!;>#NpzlNPg3<yHQV8WzH{sabjG`e{oZMiT6WSoFzeXsIIw%3-9~xC
zdiE4Wh%T_r^h-9d*L{znHL_o$eb`0zALqfm#6Cy+-OKFqG4wUD-RZix!oK66iE3u|
zF9BK$``b~VwX*Xm_uIxcd%>q`?9F<JTxY-bAw+JlyJ=t3!Cp22k(=yK55mMP_AJWH
zce2Aq0oui0u?Uj4*;oIEzHav8?vU(Z&m07^m+iD1%scGwwm`Cv%^Y(;v7h}`Hm3V7
zdw~tD0rvKH;l&_({Vs?Ou~$%dV3^%P+0PMnCB4({v0Vb-+9*556$)eQ_^a^nKD(HT
zc*faWN|!!h&rn6{1lv`O8J%RiZO5!lvAJuZKFxl2A;=6nA&!D|E}WO>$8+Tr_`@kT
zj*)(JcaGo(Xzb#AGK1D`&g_qY?ZN44$0+u2o}|;Po}5a`ICyd5=^3_{QzM4DHz%(Q
z3O*b~CKP-*l0aDU<NS6DUifpy*Mqr_llmQo8^G!4ru2OvXQUf4K^%`SFs5M6i;0lg
z&v}DR${ygnz7BmMoVO^Bc#!jQ0vtWWVNsn>D96r$hhdy=Lm+aPvt$oUgmaRpc;N_V
z8)7?75u8aX4UOc?P`&n1PNNQ($2e&}p>>=SM~^E<6esW@&}hyyRiB>VoV^3I7|#2%
z0TahrNYT1@&bJ?enZS9`8?K$=R61eU$sGT8;cp7(^)Zk$oZ3i;<ZxK8041065N$K^
zII04We9m6lNfdCL7Jw9T7QYG1BF;RD8W%e_AJgH|63*#rfR=H#R-skS`LhZxR&d@+
zgnlI_aRPl+oK}jmpXHqW4y|(>{Rkv$IBz;I!dlK$Da_Y#R?_*9^PCvkRn>E9DEE4S
zlS;{q2F@px_HX2@H>2+&$Nwu>xWsYjT%mE9!>3$#6X(cM7`(!n`z+9!Ig?Z=+QMP}
z3KOlI+4RG<aq@1Wb(ND`3)0T<qUFLh&Xq`jUgs>Lpz{rmg6a%9I9Ze<zsYH&AMF<B
z8Cp7Za(<=FWEba^qtLs}Np(;ebT=oBwoZ3A6@xI*$BB!AXg`N@3FIzk>?m9t;H*0h
zv_a013ABbdT*`+Ha|$M*Fv5BEL;SG!IQ%*=M>)ekLu8EewiA51&vAMOt#OX26(f7V
zNnV9XnBaIm1?D6tx5okQ6o>5tOVb?x-5@iZQqp(fzWX%{x^rj$x02$f$zWnPcO|{W
zJ-E%Y(YJ@oZHEa@?l%<B_Tnbc18y((>(%hdn|pmJEctLNDT(6C4W|s0ANQj*(DUa8
zQu1^kS2aNIzX0wBbD<x|-FXj+LEMLE=M~JIOJ%S7xi3;A-~d-ZH%AC}JEhnUa`&!=
z!XfTf+NFeY{|*Ca7`OF3^d06NqJ2p?_YVrvM{*@p({_}*g1&xwjO(}suxRdYJ3&rx
zzyFNNM`O4KDkO>HCZB*zJa>`@#RTpx`bg&~ZchW4$y^^ghLFO2;vmM9#$|g#A)Q-5
z>*WmYu3;EF!wqwSr7Z6F6Hw3QUjGp$a=5LuO~~cy)&eD;oAxUD3b^cev<kT|QM~8P
zVs0bFSW39!WdJSZE~MYLj2l2@Fy-7{`nf8(T_JyOczA*17b@ke<>t~FvyR*G1N6^x
z3n}q;fy<%uFb&)t2FzL`_oF80UF5z>iQr4zB#QT5<`#YdW;6E@Dp6_SCeg#TmAi#D
zS8d!k&%@qT?(b%hcJ4Q{^|;1mX5g2&&aIw<vE1MmJ7{6j!`09tt(Tix26BhH^1pKr
zT+=Nm_H&(S4?e(+b%JYy-0KU`8sc6`#w3hzWBs8%#$7~bd+u}F=q)_XRa0R30oRy;
zz6mZj1$~p;v1m9t#XUTU)-?BjR0TT24OmOD3K!mdTIaj+yq<%G8_(ruv^;oU(d%dr
z@5rZMdh!m?1>wazFa-U*yaGy<d-L)sL+QgC?uA`n-s2P=_v2lO!6XFneq0C=%=>&k
zB=_@Ls5<@t?|aI`hVY)e49tVPe@p3mn1^_I*t9r>^4_C#X&5hnwuq6uNea>*<%PTp
za*S7>1-r+2i#LEo@#3n09nCAF1@8%7ZZk~8@a{`NVtF^NVQ7iG*~RcTiFbjrM5lPG
zsOBk|_r+S6PvKdOaOO0Rxu5>?FqQX3ITX`)SFZsyo%g{sK+o`$kAY<IK6wTto7Y7J
zkU6~ScL9^jYkvzcdAyNt!OZ8KbcaX*?*%I8E#y6Q6<|fY_bAa{%zJGC`bv23kAPXp
z6HzF*iWfqk@jA=fc>=CEs(DdV)qIW@Ap=?s?^AjR)$+ceI)gf1?_&Tx&uggy+C|<O
zst~xuGg0*DGVdK)@-^{RJc{vN;jQlkXfy9r3p{M$9ix0>D=)hQCfa!0DGzpoH;*b3
zI(Xp)0K3Wi(i32}9K1IwKs$Mx=*sWnow*DzZu8FYK)QKaN{;vN<Rd`4%X^v+<^XTX
zfYu<7Paj?w;=N9hxMAK$qi}nKmq6v$_jr9<AUVo=lQz#|ybbgge8Bs97FrWLdn|mK
z<gvbi!W7T3@;#tU^DK)XGs7Dx0h$Y6LcvK_{!U78y79dz9p}#fl?&`$e8Zn0yZQBz
z5ZTM$attkR{sH=kun&JRZ6<yB4+o;pk3a7Y4EpmYsibEg-`gAh2JqKj!CVCL2R?$m
z5dIEFJcfOcKTgl7L;Uz?poQ{xg+e2Y??Khrhxr~9b_(Y|!iD}3z7L&Pjo^R24x@<T
zPt&Cr&7Us=Il+JAI`m@r%c;gBmjC26sGsCF(Lud9{>4V1#Pd%vK@#|DuL3NEpDK62
zjnn+^s9ZLc|IKZ1)A-qRU^boq!ze6e@VOME$mBo52h171n<ucd_$yLiFqiLp66$&U
zZ+g(m=P#y3bOC=s2NVkVJ42yf#Q$Iyz>4`&I$~GCzw|0dDL*+E!!6@KwVYyw<^10$
zqE^8_P2uKq{GTW+QN!Qc0GL|7x*QW!$8X@l(s}-6T0_+HXH%x}0$<I6i3a}s41hNA
z%jr#bg|FHTk!F4bg)Cb58>NtJ<$Hb&ur_`fRRUh+r>}rsJHHs&4~NrD{`V9%zQvET
zfZNG$il7UTA3>koy3Id+3ZUJ5E-g2D_?478?&UX9DeVA1ECD~|Ab(Xg^oIB?^zEr(
ze&cJfG{RrUg57)kJFf6zl%Gn=g)zS9EKnZs|D{0B1V8av%#34_-%o*zDgFTp;Z5^h
zH((NG`02D$+#`^?!GxzEC>Hu&f?1Rt*eg(*K)eNY7XjlVcv%h+U%>}P*!2_CHbK%~
z@Ny(D_X##pd^tdHoT|D41+P=dW02q~?Ky%4(mLqvcL=KJ{TCuQ5e(3S0-YT&hXhMJ
z;CHBiPka9`K>}U!;etSV%pMVRu18;lVD@8>JSvDu2h1_S9h&Fkf-DNuMhRkQlM^j?
z*a;+7@Z*bsJ}HpiKwq4onqKhng1s7GCI}pizraltxX>akNx-AE_$k3x8Ym_Us_7Aa
zT98hQ!&Je91td)nz66Ttf^gdOX9%X3gJcS_yD^9?!Dj-9WD9O9p`Ih?p_q5BAXowD
zJi#i8Amj_4{v6X>Aed7Dp9%$C4mv(tBoNV(tyu7v9g|-okgo+=sbFyg^veWxx}M7g
z@6a}|LU4}`$5jd*qnK)yz?cH{vw{T_kFOToxB`)Lg0GSwQX|;53f|WWzM^$aogkIs
z>E{K}^e%4@{7z}9MnP0E<*F|V!k$OxB>~?98kYrguA#F@Ffa?FXch#gp|3^o{7nqB
zRnSVixi-P{Jm_5&tfDPmyI`&opw|Tfv~#*4*t`rP9fHMeXx$RjdjqUfaE%FOm*B(0
zaOSq))2o2)7PQ6Ccba+xc0Y`wSFn%1Uf3sye+ZrZf}IyIn7e|ey)Zu@I8V=wLBT`6
zLu6QxNo(Q}LEZBp_XL0LgUF~L=s6f16FlY$_4|Uyp2Z|g2pZ-?Z&Gl=8G2KKCFek<
z1)tD?)fvGCSK2GN2+LQZ=_*va!BaQk$Uo3<7xuNn{4QZPz43MnPwq#bhfr9AzCFSn
zbD`iVjHAi-5<W+f!@a_F6jSvUPCky7kMOm1m>FMTX9x8Bgq=&_n!m8=3t;XOwgkfM
z0O73nK^%d?0tsM(gm0SRaIkQs2`2UnP2a%80ih}apdrG)>GSFbg}({`b4Zxl1ME=Y
zyiAZVp`7AAhlP_Spo9y()`1)muJwjqgs|$r1*>rVdzg}=!hTO!I3{$b+}v^DHBUGb
z<q*cw#TqSi`U;+&5JpqDIYyYd9-?u=t<S<lyfA_`X9>cs+ku@ZjPwC^k}!t0w5Nop
z9*1PIFl;jhlOkNR3n-_BD_;aks&M)q^wNafuOXQ(?CwNghR}%)&SeV4RHk=E==iW4
z%`D-MN=#d}aI6(*Il`+H=gJj2Uk6N{@c2*Y%NO>mAz2`FrrlAYu!&Ax6$zR20pMcc
zk5sHtA~aFmTB$IUf(&KCMFD7)3wx;Kqe8g-3y4$-!{)$?Dq$ck?#>GDIp|SZEmTm2
z&N<<RrI4u+>RyNW^TPcrK<b5mQT^rxA=Gi_2;H6rX%rT2g5*Wv09B-45(Y&A<+AYb
z6<BH#E~TL672!A2@S<6`{2BacEyBAV=xY^vzW{|cp^hH;SB0II9dNN-xbYPX=9=&-
zy?3t*tLc-!H-rf~XmkiaqTlDHaFEhOw}gwVV0H@G4@0s`7@CT{9^sudw0ea_R4H>u
z82<)D`h<`E2F!lpD7}sbgbh?aHYl7JgEK?If<Mt37RHUxQM(c0?>B&bPx$%AfEg1m
z>4E-zVg3W?j|<<Sg8T=<GzvCM2+I}lds6uMD-f9$CQ*87M)>+y0Cf?yc!9WynkdHM
zE~@wptzDw)YoNDV#PElthp3IR7@nfE91t(jqE!0NwY{QQ6hQG7CDTjQNA&Sp5MNQn
zN$C5F)>4*vpXjA!Fc=`Jd;-is(T#f;XppFmF0WwGCN@TRK%}AwQHW^kG|V3q#d0u~
z!=g&sH-?K8>!5H%WQ{;yglIl(6Cy>g<^a=iOthJHxW`4$wg5Xy^hX)cqDAktVDu+M
zp69@f5j9YyXRPRRdO5|3Jn5YrFZwPGFbSgV_n@9AdVUy#ND>)Cp`I*?qOT>Uh@K)x
zPm5+KE}kl4eGi2+Q3(%2N*5Vux1Qm^L_sl2w2`*U*`mj{!S5VV7zJZ<MVW6vF;BFK
zvJnNM@O2nWq3C-$H&G-yy%Wr0QPk@&SR#6L2BR+(m7YOgx#(lMQ!7LsbQf2Oo=HWk
zO4LGCt7k<^=D=RH=!P8XH6q6yx-Du&FUruY6XnuFs9v<0o_ZHVBC4!w5dBM~DvhGI
zC}eR_ltWdOmqlU8AWb6Kbx2+jRS{_x1=IeoMKqTtzg1L7m8n-nA5;UnUDT#R-!)NL
zI~=_(YNnEc8zQ}fs>wP;|4zWtEm19{C^|*$uK}$~beTeMy`si-P`o2r-Ur1#kxBtC
z`bF>4!H~P6+)7O8plEXz(1t{R(~4$Tl=v&ih{*FdpxhI!rq9KUioQAvkui}!g(1g9
zD*CeE15x{ODs`R^#k>kKDO&I)xKpCdbkJf(^vb(1=pz2@GCXt@zxENla1)19&4;^~
zO^391i4`=$-Qs%6AbX0-s4T=wd@>Lsd&Mhho#8F^dJn`$Tt!=AU-9-{i1>-+8$kTU
zn;)n5-#&3#6gmUM@1BQmf#Ub*$rvPlg$iGS#s8E*bier8UuYc=A1j4xAz~|4;vN*A
zyb8OA#G76LGgQ347UK;QyT1a1hsB4>&<Yo~X)vTCV$NJxh!AH}rXf<?{TKR<iWj41
z-r;miY^L|_aj~TmBuf12Szt$tAEg!839&36qA}vbbQCLA9Ki+JN%74ka5PT*1f|O3
z#ZQz#GC_QtZvRAaAAN-^N&Go2B~FQFD4m@w{-y(ZDdM#opm17TW&>ub*k>&y9cg0T
zPe98Q_w9qm8L`i|5X}<*I0`Rv#jjJoBv0%?zhS=kp-!}l#Qzp!E{er-s2;0CynP66
zmy1VeQCcC+xCYQlacv|Ns>M$|3`^(4$3KIG8gal1m_IL0_z<mnu}T2-3l4F70;cAo
z_}gf}ToMP<OXjk;?Q`fii@Ruh(jvY`HB+r($p;W=7ys`R^sk9Gy$iJK;$n)e+z{`l
zj82ERZ4zGG6qkJlM{kM0cnl();{Mk$vMzC15m0W6-=eP!bc>IkhDfj2v5@i}cf>L8
zpxGyW?H8c+i)$zle^*>g?~Fn5pE4*8iSy~nHZ0!%FhEDd&8q==PdwZMXGX<-Lf9P>
zfBhZ6?u$n$Q$H@wh=a%j@p(NAPKZORfH^7dqf32C{MtTXPKz~;8i>w_z0~M*k-TDp
z30KL|_krdn@w^C`-I4+N!kLHU+AWNJkK{-Ph^Itx7ua5sqYAY4N*3!N=`Fc+3X(pO
zC(Qu!lN_T(n!jX{mR|cL?i?5jko@=v`T`~E=`IeEu%Dy*FIcj#5@f$*f^PVO688>t
z9+I4;6-}sQK?5}KUy}4XIwE;;Jq8mY@s0wCl<W^c-%-iObd?;Jym24qqa^bwcoi-A
z<q!0okgQ&dz8J|Cde6s7)S+mdl)SkT1B{bwSxm9|c*y~JgeOP@*PxLu*+h@&49Ob0
z<1!_)Szw-#@VhbIEXgaI0Fy0AqH^RM$>wKaDOd6;Z6)#~Cm%yAU&5h{Oo8NMCP<;A
zGzcg~lFbywDV9V|!tD}Cjuc*$O5#y7k1wl9KJ$Y4a!DNnG8GaQEnF)l6;z2>C2776
zXU<AK3C5LBEqS#MCeBF$2BA<R$=L#Ctz_YGcvvUVAA#g~34=bLSufd0b(9w*FVK~H
zQL=^#KrTuC2#2GWCE`9Xn<XF6v&7LN>D>*DR>_e(aN8sb%Gh0%Sf~`KU9$0ESh^u$
zQFT^_<TjN%+?1T?0=Xq|AAn@1WHJQmU6Q3V7q=xz^d9P#*o%SPBWa;6NUvn&dbI9H
z;)7tmPx8|Tn1p`GnklsIIwZd}Lt{W9*#gl)$#50Okc4v(pu>{vKhYYItVx2%J;{;_
zaAs8URUG=pB$E%L@4lq|8Mrnsxl#qt2a?z6#N33WkctQ<CApL-oRaLO6w<V0%Tf$*
zM)E(Jd>83*F+^OYj<4$Ax101u`r@Cv)Qje1mvqlX7~Czj(XHko4XlRUJyN%C!1R<d
zXeH$(&81@Dz0wa_VZvM5<O`;cbagG5zEW3O-}p)2e;JMjNVj<aGf=u#1Cb!<3<b7=
zrAuj-zhAo8K}&-J(hMoEL!`VrP&_F0asfFcebfLFDs9~j(J*Q3Avk<kTKpm;!=-Po
zhTajWG!o_`q?ag}7%AOG)ka69qrbq?F{!sN%paHTDTZW}bloAKL`&aU0QDHDr#pO#
zm3mfEuKJ|ZtqL-6($K%57%z3wU=kChu`}pPlHSjU#wn>EZQf5y&o6>xs&tT^Woc3!
z{i5kojuov8DNhcAnbK91M>`{(MZ1(N=>kf)XG<RxLN7;}$cI9%G>#3)Jn8TXiq+>!
zAEwBEfz(dH_CjfLBg_{`C+K`iv9y~?WJ;udbZ?eQXH(L*O!|HfnB~&We?cmwa(eAo
zO5-R%RV9t2%Am8-7!@R|r8URl%sJ^lDG;fV%1U6NR(fq8yr`4@h&>iQ^&tI}4vp1I
zA8CWe1?jW2-fob_Q;@z<nn;JQE=srhqtztMrHIQFsrkR4w=_<Ip|wb>a=>hrh9-iv
zN!L)&?W**7dY-pS&n^S=nl%3m3|^N$GY*9t(w~38blsG`_AsWzaZ6f2x$aKsifDB9
zOXUS1ccoh>OEn-pOu>~w=~sDZ4M{`k2-&bSl_W=`;S?>qC+)}w+NhNE3CNhVWgK?L
zrGL=@wg=K5x5Ms)^v4V^C#Apt4Ca)yn}SHwQXe{=IpdI?rNU2F*>kk@ag%k^gUVgz
zPx~nkSwJT&?U6Ms1JhGB)ryvv?CmGe+AHg(a~|HZ<Yu_$Bm46;w0vdf>0<GdeMnnk
zf7t;Fj|a&5EHED^3kruwkgT&7g9w%tQgUp+%&{#2mJZ1BGXN7J%Y7Rr4$1hG_zRU?
zqboQ}_GSwd56eDL!tZd|0g7xz$SNpA8Y$CfL;aX+U<*W!%glk8$|zY4RW8TKKK%sh
zv9cjjKPh8Utm3q6egq7q%Jlo7mnJhfo`4(avMG91X2{Z~z|EBT(t|Zy_9|r#a%7KD
zL@ZZ!^9d;C$%3xHe7>yQ2xkgpTt2W1WrbhDV3BMQ)d>~LjC4GuL}sFj%Tig^W!No~
z<xnL>g)9RFf=-pPNs0wm$$qY)1;$y~6K}zbYFXc5h}O#fx`S4oOh|9T^D>{4Xw}PB
zeG0S-vfK3DZIG?J1}_?A2WcC5QMUPW=v|T>pe4{{S?@paw@J3_Uku`k?AB3`X4zrN
zP`1dnyaDxASxOT;Y?I~w_kVa-Wq-T_{dU=|5$Io&`G=wNx@;}&J#NV6$G}pD>=&#R
zoo>pOUxWTFnT^uJow7Sq@Tp7I_AIb(%Qh^8NVjYe_4UZ!x`!$0m3>B!jXSc+5;)o?
zyGTp&epzNan0IAM6Dj^VAk$Hhe^B;m7GQ>CTPXKCESv0vr4gAYZIJKDX5WU$s7zLb
zzA@PaDp<QOyGvoCaoGTU4E}-a1vWq@WEE1_os{XGh1*lI+wRbtmOVll;2GHm6gzW~
z-_Jy!o7|hCIF8-&V_%}vL!L=1i#_scio$xz{VC?>CBO40(DusJbfUyt{^5CO_{eK1
zjOr_&MOVI`JT?$${_>6Vftr1CClmSt<j?=NQI-ECMk`2um;#Vt@_F<#9hNJo<TzYD
z^d<U^IOHEELq9_9?+0$AeDX_7!cqCZ^iv*_KR=0q9+$s$5v?fstBWBLEuXoG-{*u}
zMYn&9{4Yuo#>#W3lH#Pi|3~;6Cl}I=End!}aAJbIFCKk~^0>d?VUql}IcS}dJI+8d
zS?*|@hWQlvj^nU&TF%{r&Q$pwiUg#|L+SOKE?+=T%?$ZS7xXjb3_A>-k?&cGR+fA#
z1wOOozfiO~NB%yQ66MNY(Eue+{vM^w^5xs^1G+%ITn@=X`Ed%270JhTz(TRS-$AEG
zO61P8K`51%vLRC@j|zrQ<#GXq(kkWU_kmp{_omD1tX#DOcB|#mhoE;(e(_@{)X3+5
z358nuiaB7`$s?#d<GkF|0u%M}09q4YkpDy}z6N>z<4|vu2T*k4vV6lb%2hYXZ&L*D
ziahUWm}r&<D$v;?uiX#QDj%X#S8ej#x8cQA`O8WSrd>Wj7sNHWKV_n>%TJAfc|*SU
zHq<-h-%v%vP5GC!6}Tl|<^kwVc@*t=y5udi-n}jVJ{_c6&Uu0Ur=>?eN-Kn3`M)25
zdq*z%8l+D?Mlsob`Ros&e^>58S=Ryid0J`?%EQEH4auKvgWX~IVY*{R<PKVk-;@8d
z9Ck<L-D^O`<O{!o<bApG^BDcO{9ZL&dmxwn05T!>`i0`3lk$d1%-)ndy%R9g@&+?n
zGxB-$@WMs0o#xA3VM>6;F2$M%!0c8;QH_eHVh+WEy%f8`U}>)cFH_tViuxTOeu`>O
zc<--xeltY&DUch$U7>iAin{_87TU%IDYTo>as(?fs5pARqJxgi9Z)c6IT)gNZaG>9
z70<1M=pn^0)m4QmzDxy7n8KeP_J<WmsQx-!@fj`Yk0_oThrtL%<25iN6-jh?997Iv
zLid<Lb`KsNSG-Y-z9_}S48|F)@TLUk35TL5A7hG9ypRRZSVbZoX^dCAxEfw0C^jeo
zlc@NOo_fg&H5~{|Q7ooa;c3NR6#7e5jOC)0rg)EX^XZB|o&+;P@%xK#G*iKS3CuH!
zHU3~`DeemZmaRBXVTByU_Z7g*RXB9Z(acjcZUf0zWYV6tK(U4PVTFp<=u19DiY}_T
zDpu^JltGE&<1S#ADjeZ(zf6%@guZgc+v#9dD9+4+GnESFYZzgbV)QeBomI@CIApb=
z)CJ_6Vvrv4HHuU!%db^5JECB>Uhxzi-MOH+%>}nX@#8s|Z&bityj>KbR7r73Vb{aN
z6-5f|M4A=OloxJMEKWnKTd{u+yy#IZ{vPIg6=M$|c}I~-Z?itdnbVkre#QM{VBS@*
zZD0;4G>Om~RD8RQ-hV@i#~z2`u;M(`>x?K4Q6%r4!o?RRMiuKKAv&f=ZGijt6+Ptl
zxMB?xdJhzTe*)|Y#fP~V)1+b_y$Gfh&qqVgMQNjIL09Fr7}#}FeiZ^ecjZ(dn7fp{
zyFqp<w~o@MRy>q$a>(pa)>93Wr!s@WY+lMGZ=tnU`9>LB^H#2=u$7Op?*=4&mEDvW
z@>5RJ^U+@^qgd2F<t%!71Sr4kg`<JWC+K1cQbzND60Gd~4wCzonmV)&D1GS02~mDL
zPVtw6${{LZIHa7RI=xUOlcHB)$}?0^aag&)8?A69w-Bu(%Cfysj8HbyV=_{?j0w=A
z%GtEYJEnY-E~w+m!f(-vQZA+(d$e*l-9IOkTj-@0qg+D4f>`D2w2?Wf?504(syL<L
z5n#tFb030!f^uOIL=%<H6sk#5ZluS@DW!#~aFUgkAueJZ@7zJ5zci)cGq{$nJVBev
z4CR9_pq{Brro_@2<^L#vn5A4_0I+OjXb4D-@?ko?k*jQ84lnYQr$2>yzVZ>u4;3ig
zBA`&H><<95NLfS=y<+7Xzk!q}t7wl^s?^b5woG}+5sWdFD+B)r&<f>{FSwP;`-cEi
zrQFsG?6b<Q`Ov6VzE5S5=alm(KUAX>(@X8V@)ODm)GMDpjn)OF;1a+Zls`NSg+}ES
z%3@qpN>*Ylmy`>rX7IA|h!=+2q<oEvIj<;>{7c1Q%}Q4~h|{7pC4k$i45QUqn{wwb
znAxjJBP|E7D~Bi~d_yUqtZ9cb|5>2jR8G(f^Oo}6XW@3IlJOB*-AeNui1aAWehT$o
z<xUTH(XZ^O0rRf1f<ik3%H>o?Jgn4}(bu^~l#z4Myr*1659?9oy$(1$rrh*4JiV_R
zcmb_(<<Q^2exP)wqN53=AFZ<|m3~xjI;EWT3|yO5UOEni8Rhd&0L(?T;|thzRi)BS
z!cDc5A_(p(cRDS(OI5cCKg=E#0})4ulcy^1G!(s5J@g3nQDqLm3t!dabW+eyCI1Hc
z{;FWAEZC<~orE(1s?io03{>^x!cvf`jJ6lSD(4sA%zjlh7wQL8F0@DsQSs^0IjDN)
zb@Uxlm0bd6sH(LYtuWPZZ^9?XVb#lnzz$cfqYsfps_M7H#8K5h^w2z}@|6NRTE(Sn
z{e<cdCy*E%h(uqkD#i}iPO83r6s<Vb{_|+Xs}4R2g#=aKHdsnj9dyBvl2o7HLf<LX
zt9G=KRok{gBt>=UQy4n!P%R1rH&u0$4(g|==FNqPbk*=Y_>`gQih+w+s!0l_W~+YR
zjPd5E-a7%2VpZ)%46Q`vM{$8tRl`wuQKm|G6wGqfUzE?PPzBUOuTm8)g25`4_&w;I
zRUM*&+G<rD<*d%B9G~{0vqtsmE|6N)TLO?emDAs_bYAt-M=)Qn>OTeS3o5^GkOtMO
zRMvP&<v|aa%PJvl<C;|8p8@lVYCpXjn^non;Zuuh35BU!Ro~2lPi?Avip5@4Eu&lP
zx@u<~$PLvN#{tYjhiWP1NpGrLC>?%F)j&UGr)rSuZn{)QDGPF2^<@-V-KwJxL-LNQ
z#{j)PmCw%@Xus-xN=n>Sl~T}pK(+f-C=9CVSYQsRE=l3quu6Xx21it*pI~HTsyAqn
zbYIo{t^;&jwe=PhAE;u-fHtApMR)q7s`d=@r&MoHW!<!D?eDNVqk5mxhi>Y*HPCZc
ze@74bUFsA%bG=91Ek~cHdfOwA^ipd|VbDi?<sKaMRgaW`>8GA#qZOder|ndr`j4Ab
zvK6HEqvY!W_4dcm8KRcvfgDsXrC?u}IvM*Kr^D*a&%(8E^~f$5j8Z?vgF>|W5T(&i
zsEbn2icv4$36WU!@l){kr26Y#pv0+Hs^L?-`Z=n=Pf)vMgPEw_PCMHqbpxVK4yRM<
zs8=A9tX9((@KV&b4r27D)#fgkPgUP9g!weJkwP@->Q^aFoT1LNpp~iiUIl|^)O*gr
ze3rV4q8iz1C#w0)QSTN5Ggqy68Ld3EU?CLp)%APeZ-IK8NTJ&LCKMb+>a|DUaEW^B
zQ8Y`{dxxM=rXHbace(oRZ1_~6?%EBsO0|p<!d2?o!_Ysg-bsmrYITqU*Tp&Yb&4F;
zsHfeaUaKBl0N3i&QmS7$uf9M<-1X{^pP+t0y+a9w2KD7+pfozv?f=63W%X1YxJ_y^
z1;(zZSJG0VRn4Z@cbmGR1)^8gIV5>q-9l^W8|uX)=<86&RibrM{maK_-BLgA1C&nn
z5Cv?y)&EjbzDNCU6~KDc<rFjMSKpn0hj-P%JD@k9b{v$Vb5OmKik61d&(DYcu)6pV
zn4{{O6rLMX`@9TtU!9c%GNB$m4NH^iQ<QX?QU^}LH5bi%8k4Igh6?fBH0w*@=x)tB
zkAUf+Dg6Y{do*>eXnAVZ&_mNp(-;Mjy_#^xKF|P7$pAV7HFqd+9;C@EhfJ{MDwQYh
z*L<S@^MK|Gt#m^)J+H(4gPKs3raB$cq*5L&RPzBTglU-1V)71awjM<*T$AVtXO3vj
zu7-yZn$xeKFH#fm3!FKsk$Qj}(=5-S9r<z1;Yf5wY5Zst9IbhlYNk$TTvo$GjArgd
z^u=msQ#kRY#%VG7;xs>b!Hakeo5CRpn)e=tqlubICs<0-<Yj<)N+Wz0(8-!JRN9@Q
zaZtVYY0Xw8`cgH5V6@USQ7_Zy4bn9ipM*CV8pQ>GW@<jo0ooZ&o<GpCG`}B%7ulMe
zFqqHL1ZIMntNFAB`gxl7DKwj}@qP*-1)7K{=oM;$N`O+NIsYS=#hQyWvJ#DmPNkM=
ze%7E>ra4Pb%W}=}UG)B|(8y>FQmHvl`|K)Bb0K8TYNoydvs&}b2K+GRG{5hI-!+;?
zDVtuanWji-ohFP*ug+_N0?=yEoS+0tqoyYT*cUa!bl{;$^MMbTS2V{rgEVVq-+<d~
znk$t5zN(S`4LwJ@<~u4GxuJP?HqbgWcQvqkQ?sTL2D>y&+V<YobTi;Zx5oW*fc9uQ
z{2<b+Sx?X9JDShv-tN=fT>z1OO*QQs?`j4q{XU@apetcev*|_r6hoS?Ux40-=292T
z-_x)uMK|iuyz&F=j%mg|gZ_O@=293O*F3Tq8V@vFN)AkD6m!uxsj+_#=9FfZ0s7OL
zx9Ino(e%8D@w#YVN<p8iHmeUzH|-DfT5#9q=Ys6g`kjLpyR|R)qR&GcxC&r<w448X
zSZf`-dZ6#6E#|<Ry;`Ro!1mU@Q~;)r_BR&H`)ZqJFhW1=!veVGuYK__EbY^7{sEE!
z+Q~>T1GOtD@(`rGya)=xTJr)h_iOK7LF<4vlcJy@+GYM|9n>a9!<j?ctFs^ys@?B+
z9WI7xucyQOVeOI#*bUbP)WXvv+9&DMR)qEt-OZ8O0?K0_)xPGAzGK>2`lQBj?ZiBg
zD6OR)*wNa~&w+hHD@X&0(QZBpy;$ud^qe}WeU{>gaatL@_T#k%dR`=Ghs5;oOoRzw
zCu!eZ2bfdZg%99Nvi9~(m`~AuCxgam?eGskOVyTA2}PRr1q$b<Yx{yhGPJM10Fg}X
zkF>lxqdi&xOIcc{jeyS99;XWY9POGYFmtue3(?Bc7Ci)e`P!QIC}mclZK7C5p|)`X
zeiv!K^8skFb_p$GOSH3tpjfJ%OApU7t?LY2E7!hCL6r*a6ory2wd=TWtx79h4284W
zjY62H*6un0N6%?j&=pvtJwtD^T5W0|pzE|nb1||D+HD8u>#z;lAqto_YR^(=_o6oY
z7W6M^w^PylW$k-QVZKS5@EfqNXwOh^v02-@5q&LMUvJoL)gGj>sy6N9uV`J>*3E`O
zyVi0V9$wQP*ap4pS_UodZfL)M5*9kNnM|nP)NY}uvE!EZ;RTqCPHmqn6uY$N_-NhM
z*8L8RZf!p$GkUZIRNvdH)$N4h9qrCzu+*n*p}c>;ws`|Y?rJp@SRT+iq98e_t^E<q
zA?<Cd<Q>+|^MvGx)`eci_q6ZP+HzDIOwqY9ht`iyCg0cIq#eb$cKj;zA80RFAv&Rb
zEDti1+E_{}PiY(Un9^zOXH=6jqjeCri*5}AOjn)$D-3Oy?i?jicI%qCV0!3Uu7m8+
z4ZQ)Tr*4%ez`S&9D!$vRb9)>9dg~my4?)I9S8)JbU)|UAQ~2rbeh4&w9s4?%`*a7-
zfCT7VUjj2w*Gq|#Al(ebgo1V3Etu#1x=mDAdq7tf4M#(CkFX(fP`7$1hIB~x8HM#i
zbss-KD@?aP1>~@9DHV5x>x7Q)pm;>L%LI)GU04)MMCy)EtpBKvxdIL!(=kZ@xbDIG
za4kyr4y96~buZ0F-wEA!J@^e{bdO#HN~~_>$6%h+Ev$oNoNmqrI1{ha+0mDv%fQ9v
zl&I6ulQc<pfwnxSbi%JFWtObF{Up3e)h(nGG-<kr=<H^??vYlsGISd9J5!hF1`p5Z
za!vpyOXvPLK(lq@kE4~N+v^OpTwV7UP{`ATQSd5X*Gqe)BHi=vL!?-@b`YdQx1NIR
z<+?xGVWC3zaq^?M|0;EYPUu(bgd@;Dr+e~kxLBi;(YETm&WEB_^*Rd``drX;(<ix`
zb!}2GTXgG>L7`Pwnh3Nu-JAv}T-Duv6aKdA-r7JnfbO3k;OKSTVmeoLLpLIVdWUXJ
z8$@pEZX(I-aJr>4QM|WP=a7SR>E6kL%x&E|IuhBf3#K??kFGWkeZ9IKDi^w=`}GR+
z`*fEnU(&A&r8Mnb-Si!pAJ8qND{xRZpUSz0bi?If4(mE!1ImalwE~j&bWvBq9Mz@E
zfZ`a_Rnii7LbshR#7SLn9%QC;8+mYeTDK+{%o*M1$<T1oAO0PnuKM@$(dVXb2!Kx>
z`a62~v`7EMQs{Z=Kcu_LOTW4XWUv0|d4TrTk30nPKKd!z@%id&Hh}4`PyGO7pF_X1
z58MF#3x)W71NEn(0TZPEay#^c^)(sj+pm|0z|sM|t`s66`WIhC-$8xKdXP~4IVz6|
z)9X*b!^8T0NdOJkzf}aEj_7$;FhP;}fTy8;R6mDyH^=n*UIa>%z9tGIi`F}&l&CzR
zPv-+BR-f$-n3MYXw9SaqAD|kQczwxUz$EBZU1*)spIZj~WPJg}T~qYcv|K-}|BVu}
zsrq-N5J}Tl(yfxN&rSelhJI@YBs29z{b*(Do0>7e9DPzdBy;rzj;A1+r++{v0P^)u
zoCLQ(|0V6Z3-y1kz$l9J{<Lo`)-S&X#S(qVSLiF%J70rOW%^aWLZMv$HofmF^z%MI
zU!}g0N<OOe{7o3yS$!o9qFNuc5@5CZh6#94r&q>-oY(K2>j1Z2e^3Se3;Jh;&~MPE
zQ(Ui6e=!Zri~0>J=wH%%tbm7?^>MUDY|_VWhU69fmJIZ@=;u({qg5YES8kiW!2)ts
zzl>6%?fR-Xh+NZW(9L{Z{|f_sH}s8{;C+YQ-IYqVZt9~ruyjkmryJZ({gO1ubm>2d
zg5quc#3GPx{YfjBJ^C@)F8Au&7eVrl{?K9c_36K$G+@8JbuWCntFH<L8PdnrgAD8E
z3865eclCw&F};R1?f3P==P`(JecG#Z|2@!`{fSAK(7P{$%%nbrz8Ep1kN5-FE`~E7
zLDbdo?V}i>yTQI0%v}a~BxY~7VJ?M1Jq!lAuJ#z>e@4sGFhCn*FN5bbpzJjyS)t%<
z$e?$Hk71G)hrR~eBf#8enA!{C2r%rVV)8)4#;qVhhU`Ij5o{Qv5Z-=6nHDey4B1qO
z9Aa421xp7FBUm>(9WuO0Tg*_yTzX1}8D4UQ$YH}I6?%soPI$uL5kvE@P>(P;4`bMo
zhOhqzg`<X1s)9LY_#Xp9I_@y^tOkuS+@l(mSi|Y7P&{e)fwHD?hIJG?i#M1Gp`T!Q
zj6yt#hJOpeOftN+0(z$m-_x<*WJ6diL{bco=RxnZA+H@^sfIUb+nQ#$&<K)lc=<7q
z48x|A5Xm&O((d<+!GUWA4|GEtoqo(V`27hJIfl#An5bOC&-4+1Jd6T;`G)I(P%JQ1
zJPA^0xSa%pMTQ+rjK0|LH6`v!44*y)W~re^4!tsidl5{O8v-Qox5Dr^6)#j8QdhxV
zl|euU9?lx79QB~phR0bDJ!ja|3eg(F*-V(IHFVP^t<Lc58Ibb^UwW|C8&1<R<$__!
zT}U<<zRCw_G>jJl<)R_%1vqob;8ucxUN)@AMytu-OyT$|h7BK~)ogg49BnbYK&AVw
zh8TBx|Fsz=UW3e4!{ugh+YMX)g^6p1b##jGx?%DT{JvpWeGkkILvcHporWSRy67^r
z%t7C6gWKm|b{iJ3A<|=TTZq11LqP#B?-<;dV!V9@?&s+1Hw@NeoOccVbn<P$@P&@{
ze}jfVI>I(&P~C^dutD}320CI0nFEK%4Bm4fdfyO#1AXI$ZFD^5fx(r`PZ;tVfi`LI
zqbiFjLpYVHOdF0ah2)GOj}FPX7}ak<#MOB3eN2#>@y{fPxEr<ZXzen#;?Fi5PJ4`w
z<=}c6b3>uwWjsgY-D`C5g9&fr=X_xM82|hgUiccFC|l%be4i=;{f&Y2ZNYuUE*5+W
zFfyn#JkU6YuG}DF-b+9UHkMp~$bRE2F+>g+ryqfZ5aaVoNFFq<szIOQkZ}$k15TmF
zKdFKw%ozU+3?4RqON+#C;{>g_ju`JyJ=Rg<-wEhDW?ZrgipPzI2rbH(Qx1`6<L+CS
zt`o*#Uw9Z}+(fJISmT`Sz&vTx%!Npt@!J%r#~ZykU?v!|=^>KnFuJiJnq-{22IEaO
zuA!7!igEl9TBnU!w7N?*u9X8j&8VVU*mUE3x@IzrUKc<zjkhfTJ!2ew025ipD+TZ=
z+i3j}tvq89ZI|<nd#b@KFc#CS7aLdcKuU~P>AZZY(NRFP%4Npu*I}aESV7DE3S)3G
zIxCGe!5~$}QxwuVYrIEixT=lWl)5@++(WUB8e`&1VAdK>(M4WoY^OcxdE?i|p-^x9
z(i8q(FmC!0<{OMZt_O6ZaVyn`Tr}Q(1$~!{osLMLT{bq;O1H`Q^NZ-bVto5m%uuuO
z@g*?PVjS6k!L%Bu=K#CSc#c+ZSB=kYg1_y?dYZ0l#*>lgyKWRyO7n&>l2*?h#wL2R
z-!#7D0&>gf@+Zu98Q1*^z1zms^a$-Xx-X`=>@l+FZQ5(pC?IpkxVs0;KI8ccF#C-!
zJ`ZQ^8b>L3Jz&&OI$+Rvbsqd3GJZ<Mv%|*4J3vN^n~2;qdh6iDsIir*Psfam1Yq7b
z&K^Z;-1s5wJ0BPqQ$5s#G3G9nY)u+BD!`pGK1`n?m^Mb81NMw@0|TDAn7n+zbTyUl
zhIu#BGy9?FZsJe@$}W=^t@?MHvIa0E9;Wd+^zAXN+6Llj`ZxucUZ(IcwDy`dJP#3X
z(<WL?`j}?u^Ao-%f5b5yPJX6SnUL`}ZKVrppQ&#ZNPx-E2$?|B-EA-*WI9ACw_wxY
zF@Wwj<#=PD2Tbq(31*1t{Uj(HG}T`K_94@F5Jn$rD#=DG%+wJIM-Q7e(%UfHw2`XG
zj+lHYyA@$tyBm^@NK+9#ua24?b>Me8X8PP8*vC!1J0KHfI%x%oHdT*-oG=w!hh&T?
znjW69Cc`%XJ!x7(H$a@}MfwTjP2=amOfVgwH)WzJ>Qi7QnI58V&z&*}M}U%Ss&GeN
zis}0U_(e`TOb=6@HP!Uy7_ie!$+XJKH1X+We#WGw?~-Sk>~84GHtnR)QjSS<6AHPe
zeH5I`GyO%ApKtR15X=J8f>eyR(8Syig(6e?pKzww)cz4#C8ooz5Gge+qQz{P$?qs6
z%S{gNFz8p9Hc}X;(q!0$R+ULZxq`E%UW!>%n?hE?r*ozq!5}pzTQ2O@nx6a_XmzGH
zDK~%K6!a4M>P_DCYh5rUP;S1#w9O5Dji$Zy9=T}JX~Dc?>ZNk7%chEQ*lRN7IZmSU
zis^HDpf{U54`UKrOd}&;wwlWJq19&EKwexmC0zz-H~k}qhu2Iwluo#AGXDfeZ<xNN
zvnw4Y@m7G|Gzsl!-7@_Y1CdTs!V-XWnfi92@3!f)|6Wz5460`7G5wuHapqpr9s0KX
z9h2v2wE9d>?t`U%llePL{#}!@3JwpLzNRI?py^4v%7#p1PvQ3&Hg&mzIbu@Z2HHK-
zWlE)vnr3wXWz6(63w`%ZPV=BJZhE^4<{y~8ya8t>Oh0x&VbZj}oQ~{FnYOKfiD{FZ
zs_kb?0Tc;$F>g8sFI>&NRA1<3{_RinxtrZ-NwCXoq-E?Lb4UtAJk8=|AYNv<8vgDz
zGk3!aZ?obTc<5t(Vjh_O=GXn9zR%o7Ps;#vD19y}*u3alT7T|0uXzig2h4Nn{tYp2
zQiB{cZ%zmEka;1UBnvg0=3y{l=Fzv{%wcoH^C02om_bM$F@NwoL?X;48OC(X+)d{k
zkDD{xAQEMMC<nuiHit)`b;4Xhg$*(0#akf~Xa0`%QI2@?ilu-_F!#|>p;P7tnwn(u
zmp9Q$F<&qOJI(CW1^sk$>|&s0n8!~*B-6Z|*4t;yB8vBBnIroll5HOM1~bRZqdKfy
zvt<GL^2}e+fxmon4Sk5Kz-)XE%wltl9A--#=H3#_Ua7fbF*GX7wLgPYn%ypeRGHf;
z_*HFI($4yvdDsPZYs`0Ap<ip3(zjdd%%4#B=e+s7U?|j^{i#m<f_bC_tp@W(J!Y-Z
zoXZCDqIm^{Z!Vi({2ISqlld812VOBdR&s&XY%Zh&X)We$R5{XWE*XMin>lP1T35}|
z&CqB!2d}~iubG!o46MW4`6bNXG(T|`b9u`g837MF&FORnc9~VEMR2-p4iQ15$9#(x
z7QN>5M5x~}AN&+U>N8J14SW4&tAk3Q?wVK8vSGk{#{+XRXx>Ai(joH#x~_)JAq{Y5
z#5^8>);;r^W{8ZM#S|zSGw+;>)_t>k8qgk?U!z^~g!vk6C??Hb^t7BZulE6S+I)w~
zg=WlawnD+hQuI1}a<%l^Y5(VDnfVj??v{F*#9fxpsd#U<W#0cF<6+rHFXKIyKWOvd
zX{m_Cn7l1Z=<(rWd6DY4d@Zlg+k2noPfB?QSo{vcZlGli?Z|^Hd@8L8w){@n%l#H7
z16l_ycc+1J$nr%i?f*h8oBGfhW-$%Gx5Jj66VMO09HS!GBbJ~3hDL;?RtJqp%fcAg
zJ!+X;gfShnL}bIK<CX<$K%y+p(;(57TG}_Bu#7wguoz1Z6;Q@nVh_W^la^&4VSovi
zAj*6vTHZNHpLb2Nd}GFRpR$ykL}#+amqLyy7JDa1nq?k^ozg9Rxq!*A%%>93EX!BN
z;cvF3mOiPGV|ktyCb<^lGJxh;0$K1k-x5KuoB~V1J5VpQ=qc?|WT~L<Ru@~o4Mtyy
zrN|#GN2$f{Ip~*J7CE3_ZaG3v+X_oXCk$3v<~;)wRhF1w=%2M1D0^CMd6z=7=PU#C
zNtzl<tQ=^ymhImFt<I7~8RYYpm#BuJ-V#dtp$nFsjc7GkzNaniCCe3Bi(j_<-HWj_
zIV?UDn7d+m#RhJ(<sDCmwpbSWVuY=hciw|Wn`HsTo32{=4M1zROs$4%*DM}q!MtuU
znZUeZS#}9}9hUi&3BGB0dJn*ES)RTLw>vFG>mb=>$*n`{w#B^yt!~R_)fhyN#qq*3
z7<R8^NiT+d$Aa4zcZcN-3N7_p7NkP-uH_V6hy#{-dN2-Iluqaywxl#ea>UZK88G)O
z5mb^sYB@(6)iKNFJ`Cx;#q%R5j9b2^TWrGei3w!VQb+5+Da%g}Lt)yo#X<R&8Os=@
z&RndU)`073oqi39?p7N;Om<lla?rQi`nnsu@URZj%<QoSQ`Tp%wKV`OZ|iC^Bz>%t
zwB+-(u89JspH;-gB=}oz48!0)>+UY}1y~>Y4t;^v$DaT*$okN44se65b_#Orw|*QC
z&;wS51)w3;MO2=D(E1Wp8y>RWp|f(KR%Jbg9cEoZL7l_a;z~FgZrw5$B1f$1bo?+8
z)<Z#1kF+juz^9|ucKY_fG3%#GpnlwX$`z7P*4-3OkGAU0QvJ&b>%LUL#8^+IfW%q_
z4<K{W%3lE!an>st@G#N(;!>a`S@nMd`;>L_3`CNxy@$|Bv3k#e$Z2bnFUFK^jioC$
z!y0x2txW6aY4n}3F0jIUmi6l_IFoIS*$eYI)~~U0b2#N%M?VEO&w7WR^7+>5e}NQO
z+vr4Dq4nz+Ok%P162&u0teYw9TWXC?gQI2EjK9Gww@%X<qQdHX45ZR}eg(`|Szn>e
zS+&)NvQ6i#1sRa6v2K1H%v!4-AL@11E$vWnoVPmBVCt<`bHKe|y}uAL4c3QSpwVcR
z{({y;E8iERxMWScjZs{-mQo&}$-1-zdRMH06ccK;zC|Z!TC7)hqSb2k$bsE9Ytvg$
zxN41|Dz<j((gzs!HES@1i?3V%SqJks9M*n1=+R-lNkyTZ)?esJ-evuO4qe~2YN(X9
z#~MX-D7{w1A90UZm#bjD&-xE-8v3nkDA97)n)(9_4p`&qJiwrJ_#`lgtg|SmIBZ?N
z7V0C`Z+Afbo;8t5u12ll^s(goR!7JnG{&t#^cH?#oqPnM6V^;x-%MJY)<S05I*Vc?
zGgdwQOfI&EXcg>g`<nsR+-za=eYst>^KDSyZA&}?5f57qz47+gexbFGr|o^(?|Rvm
zc|&rq?Ri=gd)vOGSdx$JeFt5vzP4_fAwOF>J(K)xOFshHXVZR;z5rV?-LZkTlFuL#
zWb2?9cCf97;y(LrPf}d(fNi1}K84y^E`fyE8mY|hu#Hd8*Kk{~J4BAywtfTk2wQ0m
z)FW*o3V<B7bp_E)a?JL!7zU5qDhn~DXxkBrMV+w4IYTtYHk=PHVr{FxgyczEJME0)
zY=I}x7jOIR97dR6`*#u05^eV%gL;x}WhBfe+rAe;FU9uQa}YUgdt^SQIn{RWT}Y<c
zs@4E3-S)v@s(;C_6{ygeX-iFn#u?i~E`Z6h6;pgI+jfnrtnzFNKY>WTt(va60-F~V
zsutQd&=Hs-n<*H2#kMN}V3yd9TcBQQTSiaYGTR<nKbG6x`4M(2Z2l&UtkO31F<Mo&
zD>BOeowY6A290XlAu5VHXDgz$Q;jXJ39VY2d=!0kwhme#oVP{Lmb%`yg?2d?Z1>K=
zwFcXII&RfyV|@?oi?&jFja{<Mrb7{zZH=@*XtF&@<)c?@&6J&Pw*9*tj<(p&ybDZ6
ztIeBA(%Wnfx^%DEGU-&qb=xwkHMwC+SqzO1+qUbN^_#ZI0rcInt)-}Dr>*r5%yXA*
z;TMp+ZQGXs^={ke3n1BJTR@BOUYi@OeeT!-r~tXo_6vn}`fZslAa`w#-U7;i!?yKl
z&_UZbRF*PiOMDMw8n&_b0Byupa}bL6Y+Wq?9ksnQ3nF8-i}YH!Z&T5Raom<g$=3(A
zP>Q)v*gp5iSSD@nlt5(4=0!<`Y1_pkV9waGCqZ27k@QM;wWqxV1vk6n_}hSSw-0Os
zcb8qh0y4YpZWKrHu>VStRxkTnO6TphN6=fz+iqck>0>ugeUq>Kmm)~|*#k!4ufJVC
zgt6?iyQZKOU>~O!W}sc{gI19J75cl1VEck<F!$S!QReJ`y}|J`Tnw?_qe7vB_GRCI
zd&r))6C~6=_+M_`{*e%~e%M}4l~m#Ots7zfi2b<|v?A<psGt{V&!FAwQM=9xM~~Ut
zv(P$jzeK^~DEp>D%tf?4?_sn~*gHqj7h@M}fTOYY#AEdAK52j44wyu{RgG4X{rEqC
zIb|QE@K3UR0o@fT_Gwy*oVLd+fR<|Sp@mJF{ag=P>Gt;<(8{#$w7|p}`_g9UW!d>Z
zKrh?wOLtt3{m&bK&b7ZzPtrVl<|5e3w=Y!xmw&gv5`xY`d%O}FMfUrjLBH5Om)<TV
z_Gk*Im)aL^LSKdbw`wpe?G-=3nJT;aYuG(!KSH-kjonNu)mnQTUETHe>Oxq$VBh~1
z6dLThe}Hny{sP7NF54el3}%zPVn4-SuGr_-L9yAsxCWpt_D#1T({5iyCl9XKx9<Sj
zb^EiaAUEvaQ*5=vUQfTsP5WkA{NJ+kmO`)7zKe=my6lO+gWR^Ce*!*r+f$MN-D5vN
zImur8vTRK39s3JC5b3k?sEEhWZ+Ei6(p~$ej{!PhU-JP>4BD%yzG=w*Xc1b&b_*SK
zAF*eC3$%OodJia$+MlEF&zSvkIV|0`^T^=1z2E`J1N$#jD>-4Wrb9N9_BOi3rtFhc
zRWfZ)-UO5x`y47FaB(=tQj);cxszgsZq9E%4dU)x`V5%6oa@7(zsGq|5Da=cGk=1j
zm-A^MMzPm<^=_E=cK+;bc<AHoH--uJb)Kf>ub=Zvx4`swp1cdNea=-Bbq;Vge-FJt
z=ev_=1v%^Jr5Nn&czhQ?_d7pA3!4MZ)*a9faXv!DbO)VRQ!ez7Gp7wOq0Y)Mw8ETU
zGD76A^E3t2!=3-3?^Yaf{)p<YBb>ATf!#>wtyC{})cH%w3LJBO>I^I#cYbmUNR;yc
zWz3_UJ855W!g;CV97Yl2yoUY>B+fZ+2Rh@OtDgo;f^+sX`VyVz|AtnQvrjMP;*|3|
zI_;9;JfnsA)BmUGJ;0*6p7(L@y}Jv$l!d+bZean_EYWD9Q4^yvQDcntqlqT5#%Q8x
znivC!CRv&S(y`N<iYQHb2c;?~NEhi%6bn`q%m1BxfB)z4ahy3b@60)S%Q<uAT<r#J
z0h3}^a}k|MwF?M`N}63{5&UM_C9xn`cKZ1UCflyB5e7MSC(OX*+AUcH%se~)D|G+m
z+wG*i-vYb;-2--^U4#RK#dc-?C93S6m4GX?JADCYWp)=SH&brsTnU2;I|nzQU9|gz
z$_6gkt<)o!O1sB#=tPy>D5`U~VyCBrDb;pAl3k5m`f3Dv)h?7~b+vY(Z_)mHy`3`y
zX@lKRHNtPSbNK^kO?HduN@%uoa0PeGPCkIaZ?W6?12kLhdT6oJW_OsjyxZ*#^WZw{
z8tJC)w0kiHp1SOI&`xf*-OekBsn@Ra7>2UXZrUrv+i#akMIJZog2vPOZ@|u%&Sl@U
zbEa~mTXt_`!{JlAX&lgA*v&YFj=r*cKL+ky>=$W)z0ZF99T<4nuUZWQFMC&dbo<)(
zt%PQT{gg(yIAcGq67G}iAJaZ-s{MpqsASqJXF`}`-?9n)%(pM1PbwOU?0cxACHCe!
zA-!bp<N}x$d(UstIADMNzXY@W5iQzA?4O@UOs)>==-P32@QX#Dehz;Z!{Kp<D$4mq
zI^@5A@U+9RaB#^E6&&2>ID9_>zr_v(79iygX_Mih+Tn!&uHN7<aVvEEc5hO`Mey#y
zKnzs$?&KMON#1?xCkWGb-)lp+^LOw48Znjc-dm2g>fPVbisIUC!5%6-y9cQ*|Hkfh
zT7)*Vd+yJ0F}yqTUD!R}-EWLwTpVvv3hsbo8{Kd|jy?1w4Rkd8KsC#U9Ur}bMX=*K
zH`vEG4ort?tfQX<p3XXYcSAMN(UA<#IqLp_!!*Ya>3NgxnAr=13`dDM+A<xTDLs(q
z_)Q|Xe8<<j5mTY#YgFA)<e2D;w)2kXTR<*2UfhI!7CW{X{y}Udj@xx0rH;jIG(wK+
zX^~dpc=QGgFF9_bc}AsU(>w^P9J7BzOqU%4sLbh#qshMryT-9%5mc@^?jDV{T1WL^
z#8l_lv>p*QIR5V`G#edrVxigOxbPuVnjL?poNSllgv&Hr>UF$(PzDqHxxj?cB)^u4
z4?%qOj87;6YGeXe0l%3^rD;?P<3+2AR>q5mN;~7P0@umxQUbr12^S!|!*nO3KTntv
zdM7xs`a2+=?4v({63FsVw3&@RYVA~d|GjCQ2<9zzJ6w&aNkX(^qiC8rPDV@nna#9V
z`)JYxw9Yb~3iR1Uw14*T%)Mxx6GGdXpVWMTk^1zlPtmuz6CVR%p1vQF`O^nr``LOb
z?_Q9%8uHIeEn&NG^;Ot@;m|~%cU@#|hUUeqnqa(SaRL6lbOZedpv#_8(sB8NLj3!G
z2S0#(#egk(wQ|aA^yW*)%lP}Nm~`l@GNI(s>V($-`t`f3;rN?GszCg96Fnc+>>B~X
z+L=^0v2I!f^w)pehp;wuFwit?OrRRR@0{Er+LW6HH=8FOL&KJJbfVygC<_?;xRt(0
zuyrvN7H#`#H2(dQwFeyhZA}#(`<T!H80=@x(8jtu<3X3C2NOZ%te(uobof2M*o6Vv
zi+Ms-GTw~m5XQoXX^5fqcK}m-2!<WZoD4*Am-%Qh4DT_v^!$9r9K@v|9bp1#p0<xI
zdIw}bs~sRu>;kHk_h5Ja1Q(v{yzL0}0NeHeC|+zP<?FoJkE{@k4;x+yhaqejEn-4h
z-%}u`*t2*J8Kkjn1D$j^&1&f-5Xagq2HF``LPyNbvU4a=5zqFX0CobqfD#3X>=aL^
zB(cAA06Ur8OjDe5Y!q!Yr?C00@SDn>9uF>^b)l3~2J24cznSbc5nyTDbIQ4-b9$<$
zF=TMte+OtLH*^<4WpO8OK$^|5_E62?a%mBj%Uz;fojfl0E5PJ)EeUW@z<s$3FooO_
zN)!}vheyHgJm;nX$^~xRG8hzd@w5Og;m+?zUrM=g<DpW<eQ*NM<=pt+!BrTz<&%JR
zk;@kl@FlKu9!Mo;tp;cnx2GNsFLN=p#JIvu&qScrTn|k{YPi3b!qZi5_iHey<yO%n
zvX1LG3{Ul3KAkRX;2zV$s*&5X4y1`2Pnyk~Gi}jc;~vmqvKG$JZh-1_ZZs{&Te;6r
zXd-Rnoap{*=k8G+xP$wXYN|T9RJsVexH|e_y17{rkRHyx9x%P!x3p>A$Hi5H>*t;s
z!Ql<Ah!%7Mock1D-sCQL!Tc8Ya3e4WxtANzcAJy^_sOU`TsLib-sN2W1i8l@-3!$r
zuIo(<!hJ4<O5YxE`?o{*kn3|tppQ7^T{wKq-J^`k6E2eWN`|@jjsg2AH}C)spK(Rm
z5RP#3c%V2*7OclmI!jDw(wQWAi*}fjB~SjMWW+g1Oc>Y{$qagRr%DRj0h1;vrIcd2
z<gMEfW=OhX;WtyVm+sap5?{JSt0l9p!mdW*T@1~ul0WHlC)Xv}RE5zh8Al(*>XoDf
zfb>b;w}iofWcSxlxhd&*4R-EQ+iv>rRXn6oR4ME!tusQT-uO?OFtR?<7OHObMY<Nj
z_(|g^a~zKUdl$iENzc+EC|hcA4J1d((2t%gy?X)XdD87P>&usZ^(9;sNab{`7E15r
z!*7u^qXygssd6kLESB2fSOz{>BekYULaFr7V%V2S+w0I+E*-iFzZKHeYvA{y^yks&
zeVa^v9N6tL&-ox7vP;Bu%J#ku^DbF2y?nZ5nJSPTSx74kdSwqL(yt}EH-rcu%UWI{
z-dD2sXno~m<VD9#4bDb?)gU$(qe9x+@-p(EK6x8G^@7mH=*uw(#@ERFYq;<?@|}#a
z3@}pB3_8%Lu>jm5qmJu<Ic(%b@8cszA5pI8sL^mFxL~7Kbap+&D2$S6p+?Dc$SK<B
z4%Nk^8jYfLVVc3{`7fa9MzTQ+O@>i@3fyNIeM+B@$T2FPjka8)9n%n6o>Aqeh&$hC
z5uIx)Fe<VJS7tPd=3?bWTDl!7jOMz);G)snvmm@=)Yl7?Dx)v{g!yHo<#Y(3(WurE
zVK*7QO=TO+MuuO@5Y#oJ6v~}mH&T59`&OgkD`;#pDyQO;cB7-d!0t2}x{1)bjMNDb
z_87hK0bqKK_Rtfi->CXD3~m^0D1pjNqk;^OK_hVyG;bSipozyFqvLd_%f<M>Mnr$i
zSR8`gapP|cRgeZ5yZXX?uyKDWKtqg&XnQ}@xb-+-!i>++mT9>0%1&rT7}wfCCED1&
z9@sI)&#CC;gz<0%geQ%e7chu5Ua<qgoHpM3CQ#yxXY_zOW9+^NnrDr<g+NI&-ZT|a
zq#KW0Yyftqu?M}RvW$=C12o(CZMqV2j6b5}a-Ojj<(l%1^J39fVBEbGpoPY%YK&8n
z@j6EcFBmt{R$Q^MAI*?TjA!luSgG-XFVI$QY))_43gh}aK)GoAD;=b-G~P*NrB%kC
z%%b_nW#i#ZU<ZubX_<G^_|rmggT@~pLuYOqk4>S`GyaOcO?TJWgkE(+#-YXN(|zOp
zWzc+Rd}KcC9vLsC1ky|6I!cJXGM-ipb0>Kq3r%OaWgdcYk*A&kimN=$1SoFuZT2+(
z*e5rmhwgs4G2JBYa=)c8^pKlSHK4!zTdJlHkbgvX<3V}wH5eX}pZ^Nvh}`yX*d3Ms
zOAFaV`E6P?CCSIq8}FQagx2OM^0idAlqw%hpHNDJIY_$Pm0sc*@=ITUGi1vDZotrF
z$;TEzHCz6C5cWCpB$~$L%2(uo<jIfHnb3UsQpy_?$PfPp`$BohGZ+-fC(x|^yu2xg
zehRrj3rTzlok|@_<j1D~x>P<KjJ7hl1LbPV<#v<{tdLLM0L_aA`8>KHFUf0{fK<wT
zsY>9oeE2GKuE_5XqubT;&S;?3$nB{t{HolU{->N;`A@D8*2(<@Xx7VR4G=cSw{?Ov
z$z8vMX0!bDk1-_I<i3yKw?+PpN-M6*Gkg(mt9*#Qv)3j!pzav=m^_-2%N=qR)rEJ;
zt6d@Nl3&{mVYhsV6hB3e{Od&^z4EXQIP8<Vw8B%r{2EOFZ^)<9glIs%Y&l#6D1IG5
zXn~50<6sb^m{J1FU`4<~^ejZNh?eM~inl0X7Owcg@Bz>w6eh8-k5W8b2NJD#WCX()
zMWh6go={x2gYcAM>H@&TDt@y8_Gv}I7LYi_Uz-4WRx#NWZ3&9r9|4xAU|N8kt$5ji
z&~g;gafm5TQAF2MzM_2#FiRCvYJqu0Vc|({|7wL3t=MZ6cM8#`s|vXsjkSt+Iu}u=
z_#+Nz^@^=@?5#mDr4%ZSit$nK+oZTc>&h<0n~fmdigsF>^eARheRZ#b-v)<$3Tt}(
z_A7Q%dh>>2-&KS?pvZCo^ex4t<&=LORD4f!pW6zCzUpyDafjZRcNHd-e7vVvNeASH
z6r1Tp!+nMAEWkWaw9-+$hl&CpU_Vk+Rzl^8;xX-Y4l5j}_T{N!9Zd(HDTE@Rj3{oe
z19`3(q?`GLB61(Nmx`r7QvJg#1y9F}oJ?Bfh|Sp~e>{kb$xB*xxSD*o8JwHR9Qt_X
zK9e`2Fi!hT{-GJ1yUFS>4Bi2g3i@HaOj6&2(A#7uO>BHk;{F2XXEI=p(ELr-9)&Q#
z<j6^&1e$y>1n7e%bG`s)IAqd7=fFZu)>GOc%p{FczTqYlgFqro_S4fg%4BCdxM-8l
z=(mqC`Dz)sPLmW$3q3KBP6nEjsb(WIolS3t!J&)k*Jmht({DSV;$~V|fI#<|?pp{u
zPt#ksp>n`<E)_j{8BDjW1*o^_bSJ3#nwpsc#?Lf`_Gkl4vrPdLXsV{F=Od;yN%+-{
zn*KQrZO2TVwj%uFrkC%*F4*)LRf~m~I@07l)bz%CXbUqPcn<~<riW;f7HN8mN?xN(
z-R1x@+I0IvxIbZPm^cH{lcp8Bp>xVKf;K>7O&unJoHI?Or*(>H8r9LJnm$^LxYJAz
z(912|^i3`7GEDC+fo7)ZEvmZAHeF43dXDKd+APdB{r6+o6`Iy8f@YEF@4vurjp=GC
z^1f>N$`qQlrbi5POt8*$Vlmiy)4bmS(_orIF*TZg7z6tbQ&j`FPScV;v~`)jM!PcI
zrd2Y)^qSVKM@I)tvnc_5({ye#G;f)<#KHZb=~{oN+%^3!74hCPEus4NA=BE?7~lJ*
zMQ@-lk4>w$(E9s{=?zLW44bZg129ibSC=EwXQtEQ;c3M5a}z}I+%)zU+`lkQqlJZ!
zS=F~7zGmJxVeV%(_!Pw7Z1Kks2AIvKgQkIInrzq|G`o8V?hly-(_L}cY!VOXBWA8+
z0Cv>OqJTb`f6VMrJJ{o9H%CDy$Sf}rB-re|rBDqqOKyREm|0>kT!foV7zGkxHiKTc
zk!GfJvOLOc_&hYD&8&0L!x*!->p)JL{XvKRPMHaGkHnfy`WqcQZFWF}@Qhi_GW7GT
zS^s?6|A{yAwTJrzv#(}@B$}BPLN&>36jcEyn_Z&%-E(G#rok}9%<&2QrkZ_D#lY!i
ztx+Hz=4bOjJk2M41<eEIO>ZEkK=WOH!EccHx~bF`^R-kIA7WnbjX*=qO{T*j+&sYv
zff^#rGietq(tHAauO!NR6Kz^Vn~zWeImW!4szu|?pI$~xY38zBAnE4IB4LnWK9fER
zm1+L;HNadlzcUY>D$OU+jIql6C(0w#n=hqzV}rSI9l~xje>@hX$=sf%Ud`rzSwiKS
z!Q3hwY>RpLVT5?y+_@j1t>(YI4Hs?Z#WfiGcJmn@B8m=k=U<`OX+D}pugkn>14xf~
zA1ye0&1ZZGl|FOt450LzZ=x*t4f8pNVQ}C414_a_FyGRIwuj~p-U#%OxyMr&JT^D{
zxESmc^ByW*88)Bc2=df?h|*Ed%%7ft;fOi&E`-m`BdI*?h56vW2<@f$OuFWrlwZC;
zo3rxN4<Ihe&Gb@rRqmkbM>pl$Gchvzl)+OF#eU`1-@v&mpZo$%59MSH%srJ=26_=4
zP_9`Ish9GdMHpajr6o;6eUy1ru;{D&g*HO`lzWat=&#&MLmHq=A3|H8Qi61q^q?~J
z1V-(!((S)_k#hIXP&ukxM^#_PlnK{Bjw^l4APiCl(CQ{wnfM4?h%#PI`R7n&U_0E0
zDYwvmS%gwn2`*AuLPy1-l$R(o6RqTm(H5ip;d8W|P<}N9b|;n2v;%oc`7|0XPAlhq
zjK0JvcM4EBqjdfZgK$=vLVG3g%9kgAlAyHT3Spx1n~xDilCmwF?!RPZ3Kia-QwGxt
zH$`be>#0;_a4Y(hu6#ZS)ePlKIv0_tJhU73SxU?*@VHZIsT?myIr2TYT;&*=Y~?AJ
z79f~X<=y)LD^vdZ6%5LiOK5^#p%iIudR3|Sgi5XQy;}PIK%KH@1ElrJ{i#4}P|9iB
zx>1>$3%^aue{Q2s&B|vfu(+mNNZGj-<r1nmx~_bkmYA(dmmmn+lr?D>u6CvQKLG1c
z794^>r_zr~qq>#Xeu1z@>EMW-^(yPAz@tz3rZWr-{mLIrpmRg{9lc!!l*@dedQ<r)
zC82I9f1%4{P`PY2EN&}}tsuOkOt6LUu5!FH4DKm^YeFy&lo#mK+(Tt~Iocj6$LGV~
zvGU7ukSEGru230P`qPZ@sq(fn`uR-xO#}>_4HhL1kh)lC52C-W7AL&XUpI?&+tH`}
z7D}3YxLX)EgY&RhJQfZ;E$V-uOV*;39^GCR0=?S3Et+44(8r>kwg-JJ4kyB|pT(*@
z@Z@iCi;{i;7AF?NQLN<}1v(LDnJ59~SxW<-0mB5#NjgN6Wcj&0T%5BUn+c0l%TK5%
zDc$nHWO&N99Ib?AgQZnE?7J*8XQQp#^1EnoJ(h>og6p-+TnY0&%awFIsozphn-xQr
zMzox|Z~6X2Xg;=-(PqW4Wgu<;KDD$m{0NI@meo`PHexy4j3}O4KA=Rz3(MEzA$(~$
zdjb5uvOFCRG$+-UbUiz(zM%<~iz=N;EL>Hxg)s0|xd#B-M-?_5D8Z_|;Sh#Eh;E0e
z`sfKBuJY@GN`%UBCb&pd;hQx7j8>hUMuVX0tb#?N$|@RuvsA|tK(bZySHNM8D()Sq
zl&Ch-!k|>O@*rK^sykHIU9LJp6VD1&*L0AJs=w(F+a*=zIoMUID(E+;Qca{Pm&>Xb
zUxQpxZNCd)wd&0xy8mia+bE;kqB_3}kzQBLqU21gs%Qs1wW+?R3dMHS0xxhKs?&6G
zt5dayN?^KF(_Ww#-KuYfVArEE83xy@a_#}wr}Eo}2>Vr80?coyetd<P22>x@>9?Dz
z-SsfPrBW|saQ_XeBHxA1ZB;o{3EWW)QN_ev)kZml_f(<&KpRq}uY&!3mE|>r_CR%#
zGM5ik`xgV|k!tmF7(7-z*oFw7sAg9~Wmr{q32jeRQ|h4kO!culxDi!$20T1hy-j;?
zFH|%3A{c`czj`|c(V5pj#+bP9e?9`5E8l4gRX2X{3Um(hJ!QZ?!hg6B*vI(CR6u*2
zAEvsR5PpL>>_Yh*dSQm~Uw(;r!+Fy^h(3Zhx(qIopG}jyD1I_k??>|{D!7l~CsNhO
z2?L)n9|Lug&wdT|r}*uM;5U|kM2Y*;{Cl*A9>+_sgFD0jLIn(Gc|C1{#q)pu3l|A|
zK9#H{@~cvynZ%FgfSt^*8wHee{2@AZkix&Y9b77Z%n2xIy#HKuFrAN}Rc{7wI8O7(
zOui%qs#$#g>yT#i6-nT7_<!FAm&>P9X;dD6ohGjN{ErSWDB$0uP4`0HgAQ&L@vqSf
z^E`iq66qKCb@?za=G$o<R>J#I`lpn?MybCtK6e7l%lTBA5>)UB2HMEH$n#XBcZv7(
z2Up3jqFGiIKdKoPmwBFcs;=;kbZnrSUraBz8vbWFG_Udz)1gw!7g04u9lzlk+}HDF
z^xkaX_nJW1$QyA`Y2t6}g?Tf7>JN}>ye=7iY2oKiH$e3|-$Z)~t^CCxsJ8LD;z8Q^
z#YO002VYGKnoj-@)%bPswJX7O^YbXP)x&SnBeY(A1%1Dxj}M}QGX1<gEue1jKU1Oq
z0Drg-4sY@e=g_5Fyq=OsgS_@60=><Dvy|??JA6z9`gE7yUx(qo$KQ)X;}HLZeuMk`
zFLI3R1Kvag_mB_!1TG%&!!&Du%>Vuyf_cK{Uj*ndpH~V`PkA2?kY{`pz3N8z&P~vK
z&U<|c^B4S{Y-qmZe~v?UU-5Tv2*4n960+X|jI$8>KS*7K4OA!QD(s>i3pc@i8Mu9d
zUnyeRFWmkcoV(yewICjXx)z|G!t^r4bU+CF3vFIP2OVhe7MdF1$w#<I6#%}%0@_6O
z6UI=s%U^h}7LEdhq7zUt1PUYD5#m9iPKJOF2{ZmXF(xdbqnbyA$yDccRM<kf%432L
zo!~z%9N3593KF(@z&==5LfcCr!cYH$r%>VcS=faM8v~&dF4TPuPZ2`EW%MOdxU?7~
zN|;Yy4~iDT=wL#OL6A~%=7eBM6^<u`z!fk&C7h-zxmY1I7-**j2da*X6HZNs${AsP
zEXY}5()S?oLKBZD5`?4lDTqX2{e8Gd5{kZqFj?@q36*og2Q+(55#%4CgQ>!-|87G;
zOKH$_!O%;I@eHA!4y<JgpAuS@@bNCV&lbkedO1gk34;4vVV51aJmKO;Fvu6aUk9#0
zX!{<dP`J4k21UY8o1uAL2!0pibV2xR6M9xGJQ;@H65*@I;7WyL+BPf`La3UyT&Oar
zK`R75${Ai1Zc~-bCE;=~#<EiApnb_I!6z1=mj%0j(6uW<Yb?;Jg@vcU)d*SiZMv&M
z>{5W%3gKfATAk4T0PgFBb1xxm5Nv-3*C^~L0a%l;*cqf*csC!8t_d#h7|_@vtat&K
z>%wOP@YE{2lM2!%tfm5!cHuxdNQdwX2a8U@<uh<yLdiFP=@xztfO(J5L#c;e!JTIP
zeS(G(pZ&trqrki&3}vBhKp2<^yPLvWv^jT62yOz{piuje_8)Ew^>lvaju6p=Zr>G-
zjz;4>q5e-?S3`m?RchQ9F6RRDf#5<Dgonb|Sin3InCl>qg@Qj3?-QYzKKL^%?5E|_
zQ{hSw$TQ(5dM1nrAIyU0b7A&22ww<mtl;mZ(Bww<-z(v#L>M}Wl_r337GE-O=pv3!
zgV0s9$wl05qK<{dK5?ZtRQ8MekE6|9bfsCehq$2!*q-7)bXgw||9S=DCH9R%x4lKx
z2k4TIxOz5Fe8s=%J1KtRlLi?0i^()oH3W#mrT`5TBgVkupr}lR&LMFlC1VeZgJsY;
zA|_MT`ly(8ALN+Wbr3F&i&d0z3=*|P&<qw$Xw@Ae4!EN&RJ=^dk$AD~O$3@CwtkL4
z6UD33ppqo2DNmd%9;cknIfFQhZjuyn4=uM-MMs(>ripWCI+-r!|Ak01L`g0}%M^d3
zl~<OyCI)`9#SyAO$q^M70GcZf=fN&de0K;2`Qr5la8V#;TYwabh0ZW25-0G$JTKlp
z2bBxrxd3p*qG4<e*b>pd8fc|rgA)QS6GLfvQ!bvOhkb=OpDKkfiWYCc#U(L*7-*HE
zYz6G9#1Fp#%w=&d-2hia%YPAQwK$jFW;No*^$6{%_(3qZTCw*L4C=%?Kf_VIc!PeC
z2JxnWj$Ad0|I#wDNql1!ESklo32<>uTo4J>7Ew#-h3jGg1I<>kkLs=3#1*gLw_W^j
zHVit%Ij$g`qFo?dbcu`U^5_<SSPPXNv3DoHdPSr6q0%R=qK^pmi)9t)*$pva1-<_U
z#AWm-z9}Y9&f=DM_W=wC#VtxWye)Q7#l#&kDh6$LMY~jxdt#3*`ZOf!k0Z4EqEkM&
z2jVXJB+5gvjr#jYe3%UGvFNrDDo@14RR1?DK7SYPpNbq6OFR?pMp6CIh?qVX(&yr0
z8|b_cA7_BP6fG%x{7S4kfMA@|E7qfH&g#N6a4u>unpL{0&pE)8n|eRZ3iqjF!@=!W
zE9i!GSF?xFUk`OPRjzufD`->jfO<52;m1o|lLX?e4#x#-kou@AS3}2FokcGhKXoW=
z4*IM2oCI2cx@8Dlpn4VkFbCC5wEb~NefSZCht*psQF}yvA{{XuRbQtgV#m~d%b{{y
zeQgpt5u_ejjNS*U+g?H#qW*v$Frn&}MEDC+57D^@L%3SH3OW($iIkp*RGTaW7o}#s
z5pc9R&IwV(s4w_ofKI4?qcXyiYG=xEo>C|6LR+kQ;71soR`=5aDo*X~269FnmIlqU
z>X*^bj91U`0a${1kpM1HJ+~Q-lGKw{!aUiaUOp4ioKuH<0gDv1(gr%I>Wy?eq^ZZf
z4Pm<ajR_di47H>H!c6t^3K(Xoi+rJ(t!}20pB(jLnwaFO1M}cMPd%dxnE7h6co-C@
zSB${CP~A#-kRtUqs%ky2-c6s~x}Y|^JOs8_eMSk@67~BWq^0UV-v?-!`WruVtz13t
zQ(#x9Ya%e}7u9EJhvbsFnGVQRs=eq1RHa@{Ti%z|3&ta+D{3pcx~tW{-$z@G`p5g=
zuBr>(h5K5y{}&*2>d<fDp<X?~Faw4S>Qu^CHL7oN2&PH>={7iQRu}w>fx4zHqOFP+
z^^cRGd0jpG57@V=gK1>j)B!W$qFvoapM~mBKNyRcI@OyyV9=#DzYUab^^9HUS&w?m
zHF)S%e?^O&KK0kWQ0Z4UhtZ7ahWa|CeFxN5^zp!(>Z4R^cS}9o3Y|gqJX%WJR!_YE
z7kAX()0E(@`u-red+K5za6{^a^nAUqUQ2V32kP;(z<#JM{R}9N)H~=D%VTxi8HD{r
z{azioVfC(m!97*4l+yX<XX@M~FdR`Q(VFME`u&N}d7<7q2|6#;g9kxgsr{Bi#Yq$T
z5-QG`l{9H_(L@S}*HvTNk2W_=;vB?uNaIKA)x(<2*=ReWS@SO1j%tkGg26G(`*YED
zT;u-$Bv`W-*P}riqIoL{I-#0C%3OwN)?34UxF)Fzej_xEzk-X@tW?83O7l?{K%+JP
z+l^6=(bUlf>j_ONWnoWhV)g>%lqP08NUSE9lFz3#55r*)r<pbunrAdxC4Szs8c#~y
z#cTGxgLn-In!R?ACTX^R4U1$=`%fU}G;VDGP0_Sy;3-uTL(_&djf{4%(>2eix-~;H
ziITaQn(-QFW@$Vr|B|ioeiOnR%>-Jy<Z5)38_m-!*@m`!%@32&R-k!7wPuByMA|AS
zGHBNJK<B(BjieVei@o8ZSYvDo7bO}8D#|U@d_gC)%QQP0;i+76!wxVNn$v$m^P*<L
zAUbnNGcpsTQsZe4&??PebK(B7ri$EO(aZ@0O0`Dr4^pGq6AIx~O&Jxi)@lrrI;hrZ
z#4wP0jn{7YZP5JC0vC;%OsaEe(hSh9PqQYC7UtJ9XZk=|G$ynucwH0n0b**^R8sAA
zo5srzpzWG&I*-wzu|5OLPR+c@h^b3cI0vL#Gw>Vw(xa*Q8^QEy;th0AwNLZp8Z7!X
zUWt(2(8Mi<!vW2w2|&B4;Z5P`mL_#6goB!{IUu(+o9cmfM<dW`@UCXEDa`L_&hQ{Z
znjdoz;eE{me}wixld=pBA8L~6d(DqD|3(4qv1Y@3Xg<*_u|f%mbXarH2!5YxSei0E
z)1=budqnf84m!^@6JH0~3(W|f`+TV}r}x1t%{aO`owWYJh|pPUG!~qTb}daxUA0-J
z;M}xRs5Eh()`Kz-`?Zg#D&1Y1{x^gkS|6(5@YEi1q4(bbZSg&TdTF=NzL>Z6i$-|z
z(c;4;cq?gD^fLF;hEYL>zxH+|R06c;i(nt9{d)sc4r*gBqV142nzjQDYpba8<cRhg
zitwm5w-)4>w&4R99M>+UZ_Na0uP0&*gSG9}RR12L-7_8?4b|?@0xeAY+zWjQ*G5x;
zQG|8@9g2?B8qtn@lr}2`hSA#GB5*O<8T~Lgq4ih*?xePL2e?z(oX^3<YOmNJrqkMK
zTOf?n&OHUNGur)>ygI9`q4!X{cGNb+Ye>-UzXP2_?c?#lPSS4N44q`{a#KWcPP@4s
zXerv0YtfdfjiRSsns#6f?9;WTv;~!+oo5GOrgk=+6UfrWI)Y?t2VF4gIojP7u*=m>
z{R|{e`|uAq%-7mb9an+&w=;;a(4e)VVJp%;KL$_dwa3DNR-%2C2(DE7F1^0XwY%rQ
zVTE?uDui}XJ0=T;m$Y_NO<$>PoQSq6?I)kW#bs>>&HS!tC;tVNYV9m4M6J<A(zSk7
z>;DvvYPGYR(N?GRp&UuQ)=*6^w+8J-N|H2cJ5~XvN!u|5VYAkiP90p+hWVm1E!y~5
zP-)d#EQPR5>pTKa?b@l&5pRdqm5SRtwT@}P?$Una29$2?nNoD3N4rmtD0;P}<AB+x
z{gG<%`n5Y>!r+E>hM^X!1KQ`bv2;^=dIIckY5TW>8`QQWgWT4BM4z>}qg_X@!Mobi
z98~UU_mn|+UwekOjvr_*(**FLw)-B)Bkflo!tSxQ$sC@ZXdSB%@32-&Kg?5Y3@uNd
zY26JVBic8PQg-pV)|C>UFSM~VO?s&fXoB#SwvDC@PP*-PA#~P7P6ct%6?B5Q>I&B)
z3OC)n3SjTky~w~I?ANWI35V{wH91i6(0xMdRZrd6sX#fPJLCnSm#(89W8tk^b{Gae
zI=wM{f5%t1j=nhHrz`kxU8K903Bv$g#VrT}b?!9JIH<cb0TCY32{es8toxbv_>SmI
zM#242-J`j1aZHy}2=2J<DsA-z>84OMS+K74F3dx8S#+_5>V`hWFBzr_r9HNA-CnE+
z4AKalCuJZab={w#F-o_08r(<gHZ24fql>5d!V@|l>eESGoD`a;bU_RTI9B)8ariy0
z`(y^VI9()F_MOpL(Bk{7E^iOUB3@U@f+Xl(m!d6Emrqw<lJ3$mpd{-aMS~d5>HO$;
zQ;KfaEQFt``+5erG@bLu;L>$9RN<4MI~WO)saq&ROj)`ae<PS|-DiR5VUEr@4cNK5
z4dL*cr~8a@LixI03-qu+SLOg=q3$@%;fr(&N&$Ud_faqg?}9GvA9yG>=tfaasYEwK
z>&{Z$$z332x?N|XQ?85HkKR}4lqcZ#qV97qL~%(MoCWuly1>QYs&wldp>kQbAReBs
z=>CX+UA4}jhe3^QX9$A1s{4K~Fl%*hgdpBJT^a*_^|~QS(KP4`pF2UdQ8#J<8k=-E
zeXwuVJ$MArYdW?9IxV{4kHB5mO`t<Zt-ABHAKj+gOqtep-Bdm7I&@j|!*=Sllc3q9
z)7^xyTlXc^Z1?CA-+=pGo%T%(!jSGr7Gk=u3!ohT1KlzMZ4f=w#cl<8q+{vf`B-;z
zF31zzIGS+|>rNNJ{;BRoJ-BDO^lr3`=&GsW^SLf18S%c*MboP6rS4b+P~xpzji8xe
zwUVymB&&gO=)^gzB@(oySnUWz6scD4W<r=|_0*H*pXpXTwD8Nc`hzB7*;b3<Ak4Aa
zz8yMwRugvvE#GPa?Qj-Y9g)#5YV~#-qA0Rz`Uz;~twvFC%LS{Ow4+pPb)7Ef607ag
zVP0nSQ5gM_R`13mm<p>EMo_tARXQC8l~zSp=)a7qvTC=1^s<#T9euiD^&zFutF3ZA
z!U)w^4W*;)s#PmxT5GL1n(5YAEsKF>z18pM!8KU9Q?YQP)mOA%(q#2TD1^;cPricP
zHLLn!1k+;GOz)`cRvo{h6RlQDc0jYu>H_BJ25Gz1`L7`Du-aycpn9$R4j|GSR^K!O
zX25C&Z4BMC`YRLeZ&_WUl>eYrJ>6=zt$w4N>>aDe-Y~dpmHG`dhphJ60_?ukC&=wc
zA6UKm0OX;S=VJ&TSuIJ1%44hMCy4inRjd?3!?4v17y5mz#GB~TGphnR-aBIDe*oNb
zt1rsn;)T^BDJ))EiImTHWmPyEFi!gVK@eyCW*ypG^vmg(t*gF_(kO2FBlH&Cr*FLr
zmHm3{FTixyhs;Bphra3vG(Gh`mgvg?gTAa9F1+;b`a$ZgH>9DXKKd_dvgNC9Is$t?
z{p<!9`s+(}0yI$nRT+c_^@r$F9f$P$Xsh9{K5`vg9MRWY$8UF3|H=a@$MlmaRdQUv
zqXwRW^w%~3Gg$9PMV%pfhc&PZ)f?25`U}%rPJ=XDZ%Mhv2>n=kr$_4hWH5}<k2C-~
zMxPOh@j9WeTZ#Uj)T?O&@07mae;ATjeJ-UV<Mg$Cusf@Nm!2N+`ZK10PSmgb4kStc
z_3uzg)-Ozf-*ft#bgQK3<%T3!r0Sinz(u+~;T}{o^uC+Xn5qBL6m41hdz5a@)-T=!
z&>VfE4<gLfADRM~JpCRjnatO_(7j!tzf%KYp}s~3VUd0j?Ny)GOBVs`g8sum1X`>=
zb`-)A{c{1GDAgxCru(l<A4?T8<@)H&fT_^?QR3y2{`fPHO8qU`d8^W2Wf0nB{jXG_
zeMP^5lGoMx$pQwUM!&ii!e{#U7=XE3FQQz%r}ZG^I1gCQFre+I^(-pg2(p$nB8pIJ
zd&*r$Sl=2$_g}Pi&`hYtT8Es0^t5$GHB{rQUkHfljCB;fI?h_(q-TD-b>9L+kzoC}
z9G()b#SJvF*4y$CMY8o=DzZFh?LmjuQ>;5_xKpivq*Ajq>vit{GsD{aYuII4@0$hT
zdF#S%s{g!T9ZrQLSFAVw1GH-E&#ytX#`>M_;P<L^G0m%Lt#_<PFm=`~3(>WDYb_;u
z8?0Z^yRp$)cM9fB*5lU0uG!kF5W!rte%1`G#k%cRU|zR&9}Bxy>sOtyYqKtofUw=#
z>NVIII;`i<M^K&Czb2!x%X&^7!tb$8G6Qz6wKNB4t~O74A#}3|ngGy!HlO?k!~Hf<
zbet!|X7LxW3$^*|B)Bk}AezdD+ju>KW`xa`)4)aA{QV}(qiw4CAdIm&Nbix8HV+Db
zl4!6g(ZNNM&9!^zZ?erR+M7IQ)9HxcDaEFo@)4;vIp@Kp*=$*YK+|o)yx^(8<_p@*
zFSO})LR*o|1}l(DHZuwUR%w&I8l=kRFWP>*Y;%DMr>kw2e*x~Q%>ff=*4kVa5lown
z;UeAl?KTaxT<@^?oHh_TZPu=Xr*50dHGt`{`AZJ+(58tt*B{$tege%WHnk1t)3A*(
zr8A$}oTkU~h|Rxrtv|P6Xjl7%&3Og5mp0G;hPjjNWqP1G+g>k*ri<;5pCbxa+ffEj
zG`iV-8V>0`+a5}&@3%d;4gq`EUZ9DIr>$8N$N}4ljtJk&wvIka<8ABO2m>G6vrFK~
z*LDT%iTK&N(zGtXHsc7)18qm8q3xh;@>cjgWP7*<c86`TTE=tAcIyOa9<`0Jp(2K3
zw)?(AW036?$`A+JE?5GKP}`zNw1wH8od%ebwm<*3ys@>Ty5Q5cX>>uv+2&e<oVB$U
z(a{9k*|aiFwAIriG|9G+YA=#)mu`i_bGB1WfSF>uot^@zwkbzpkY+o54&8t0wwtn`
zlVR(!0ce@F@BD;8$g*8-31N;cpNW`?ZIkF}U1Dop1^ZIl8aicPX6sFl?sD5P#Sm85
zen!{DMcWbygq5}lYk*Q^I~0Vr%eJj~Xlt;YN%w7|t@#l^x7&K7p2HyRu)VHFY@N0N
zw6gB9U2z>_(QUiteK_o~ecA^5UfT^+N!(}a{u^NWZJkcS{SDhv3!n|y9{2*no3=Zt
zhT)d&j7De<+DhpdwEyT&?yzu$KjWHq!pV3m+Dx6W?jT}wWj@E<VUW5p&Zi*U$4Kkx
z$7kHA!q%M`{WmxdW)00%J(=I>opXSRpdZ1D`C^%5lq{GLX=<OwtO-Y?>C79H1IS=(
zX@e+}dD#fNET)z!H?x^zRJxVJ*zbW#F4Ih<>3NLdCBO{%jO!{yT)<rY4&5(gTykMi
z#LSogo%75&4{#S4|5IoyW`3t#woA<AA4ZLm^)o~Cw02{CTVcMBUH%pv?q`ecL+H+)
zq@xxdY-$QPPj)wz-yL9g(d)sBJ?a3VH@kZ-415f1Jtawf*^~4YO+R*=0)6slM^S}Q
z06XzGq6lO~q?lyk?Bg7CyN*S%`6$_b?kSD87uVRtjgkd$@68AH5$^Zb5pOWZVJqst
zVV^0fz&~c4zY6e=%e<g7CoBfgpH`g%^6Kv<()w#%SQp~kcJ@3}?bGNYbbOyu`5w%!
z67<cBx&IEh3}#XdM)5qe6d%j^4_xS^$?r?9{4F?r#f8cckdx#Sy5jsL+f0ERAo<b(
zT%^&n(=d%P3Zm_bXrpCR0~cd-3K=(Cf6ACE(CJt1qmv|eluJHD<0Iv<a;QF6cFY9l
zYVqM42={=+U3aJiSj12|@0i5`2XNsQCf`Hzq=h+^ft<2fJsMHOS`^W~^=XS5N{7c;
zhzG!(u^96Mx_;K;6eY0ZEo=zvXznFOZs_vC$fR2IY=T;jg}p1td5f<3K&r5?`5B$8
zwuo2>+h&VP!vMTyp^gJYi^a53XkNGY%oeU&Eo|0++_6}+2%2{-Zk2+&XOTkL#UYDy
zcX0PDro_YN1B(rm>v(9fjW*sNS*$U<28+iQ7u<pN#Nw1abe>ua9)<g77D?NnGh$);
z0K(@M%p$mdVX=+o#xE_ZdSUR&B7Zcnoh&mlK%6Zf)8@X5WyU^m?v}fz0>#6!iGBu8
z%QeohJ76h)2ox{NFJ9qC39x+9Z-6w=GJhjFdeHLEE07+tjEIHb!<OUPfEHtU@idL9
z<!pMl$5|#{hC#BW>>1prTK@10dYEIm<Q6oqTQcvXt<`eb4Ul$AeF#X0W!v{4-IjyD
zquV`}+pXZ}sb%&6E*mG+_dN4E?g!Pm1#sx2n%4kwTs6}Qo+4B}GZFVGRVZzLCaBtP
zz&=e?x&xkaRjEr6(*@NS7sPu}<z<Do8db+T&}>po_5#<g8llRfK9xC@QruRRtbyN$
zD#d}L$yE$*$TtV}0bWJP5-&cT(lXwBAZ{nA4{t&>z`nc(y{!EB85_`1f8ON^xB%XS
ziY){AKic8`AiwfG1bT@7@EY0<^XJCE?g&5d8NiP6^De>e7@t)RVGQ3uB`YWR)A-aK
z>V4k(ukz&-zpMkJ7t2S#g7h>mZwE{qZ~P+yKEqe5AUw-2JOL8Vr_eklfxkuNKZ*Ru
zlzL3!^C*p!%-hpK`y5~N93+JwHw=eqymJ6F)A?B~u*=}{3t^DSZ=;>)EdJnr`q8ub
zDfAxA;UCcMd@g^GI-1A#QXywPA3_Vr0$#ZphK2lvx1d?Xn+3wfd48k<!V7%;+psI<
zjr}ns)%?K_^stey-vj72{sBE(dihzeA;Lj^AJtAh;Qyjyh$DQ~=aMzJp809DP<_FF
zHWl_S`F5(He#LL0#jum`6MZeiTUcQP6(5126oju}_dZnogyypV^%uSxjkW+`13lgj
z3dI!YA>rWBpeu~t5ZM9qNMS0K|3nED;ozbLSNeKwjPT`r2u}!)>S1tF7@=y?Q$q6%
zaIu2lOK8RkmZ9Lz2>G$_fMSm+7?F6vISP&vgf})~3=)O@8_-M=T7L&g790YAk}cRN
zFlae~hoK$z`9g^v(gI-%k&D8WWq`RPd{hnhRYLtN7+w}UsWhQc*!Tn;Y!aqWFxP}-
zr{K3mcusd=kC3VXSg&B_53Wx*OIu0(Lgg)}+z^@q(WL<)*9qKBp}Yj-masa8e%?VL
zoZiN_g>k>a;*Ky@3Qu>1yHpf#PdFP1Zb*353BUJ+z<&VqKq#Xe^dmvC3I>mbcPud4
zPlU=@;D&{FR)RbgOy5Kgp9w~{5$K38hMon_g$z2q@j~b-0@zF8=m|=!y%HwV#Meo@
zN+11o7QYXJj*ECT2cWLv3A#w##J}^<<|9T~L+C4-Jx6GMVqyj~{l(Vbffguwucx0^
z9C(D#4vB7~5$Iv@jXx1Zl=vIvxuV4eQi&1YJP+=Km^U~IFP4+y@<RYUB^rMM!&ot&
z@;|4=vvn|x6W=<G@Xv@F{Lyw+3_k@DF9ud4m;^Dg3!x>7@6nnzNxV-_=VVbuS5S($
zgZ`(TR8iUoE=??@qSACRFbrIVm`2OiO!3HC*cq}!S9<AXiw`JenInc=LSwF&Y7JqY
z_)i$3$QL(K=}3Y2h<?#Rk->og6e^6Sde`&fQ5zUs5#wl6qFVfS2imTRX|b@Y6`S9J
zutBWmq0%TCJq34LTo#7mx+Aua0U0rfuC%xDT>PO0?q7)i(4m=^V#{&}Ux@*9c{r&j
zSs+qp^`5l|-$ngp5B$2SA5enXO+DTL4)>|0G>zS_-ue~V+|_1d0Oq0AjRT6OI?N5`
z2h^4!;Jnpu(DcSfy<7^RuiEhAY8d*dYyJmpfAz_?(HNkfask+Z>N?tnJgDxWJ)}eG
zskDuMSp6|=Js(kT4Fq>oUFQVQW9koSId@!rZYhL8>O?vz5v(3dbq=xWbH^Y&tya#3
zFivgw7Tg)NY%hM1v+9owKLI;lef3?~C#tVy!f%rL<bCuhS#3fq&2#F9l-^5Gvs9p)
zs!p#0iJ0`13c$`ydgO>;QYHnL1I1%<!&h+8^zNV$Ty(xGF96DmX?H2h@N(MT7zhKW
zo2>^qHa(0UOvk5xZ%&03!P86QfR;Mlr33DZr{`**Q!@R;Qs`7p|B3GO{^_MOwT}H@
z=4BH^ia)=^`{D0jGdh9(Tguz`d;1&4h+;=a5B|1~qDh#8vp3*(7f@lD6Ek5dV4ax>
zwB&VRoWh}SfH8!<1{g1fxrhjS7%l-ohZ)(&z&OI(+JwG_F&Be@63(a|Q_q<?25qrS
z-!t^}G;^*Qc5zJFMhw*%=C|npO<_K#!{@1t16>-qOy76l@|emuK=PR<wXiE-LRW#S
zV5S>rGx{R4upXe7n2q!WuSzB%AB_!6)&!t6G9HwYY+|<Thl^%r&=bN=W;JcubTO`<
zfpjx{MKJGSroD?E_A-lHfZ4~KdmUl-GcP;Pc7ypJ#XG>*pFrCXGj<3b?lbB`^zwPY
zjHZOnL&liu_8&1{T7rAQw0;PSm&{eF6MMy+K7}Zp*nj8+?93Kkh0uj9p;?G4JCBMA
z-PpN=vX4DVi>Upq@lt5Iv-^Xf;=$(7rjREqQW@?6b{joYz1Y}!^!)Q?SI|4bhc)yg
zU|)9gJ0O1SYXKns>;OIS0@yRO+aAa!(&XSE``i*}huF!Zfqj_m;-GSbb)@Qmqip3i
zv>jtVTLl-#*%O~4&>%KJ1(jg7&<`<%uqWt<SSUM!bfZBU##&E=;Yl_^2GvunArHYM
zvcDfgXOdWsuFPb1%RQ)^V<mK+F`M1j2VoBTFC{8+*^P67oySK00KfUHJyk=LvXeHT
zt&H_M0L^lC31tx~*s;4{evvI-iqI~x@*mM=sAPN30K0{C7=Yn*_RXKcwX*TwqOpx_
zrLFW%Rvds~4?F2&xaehn^@M#N8}TlB(a)~<AN{^;)JKSZfSpAzn49cJ=4iXcF29U6
zC$7>S2JYO~JXCzS)z<KEm~;LV!Vm-3Fap2PoRsFCXSjFALwc5L-w*fkoSv@P1TK{p
zi;3J4`o=&K_x^eGH<x?T3Kw~t^%FSE=dxczXa(GAs%I_aru>)M<4Voo{sPxL2?oX7
z3p(dh!i~xRDdqm9O}{eE;P^AJ%ef7Wu&?8OsX`PjoZbd7U7WEm+6K6yoe<vROv_;L
zgnLPuwwGM?*D%;Gc}``x?vi=0(B>gAnFr2OVorzU4@hRw`rAt~wF^;rOQJsqcTDp5
z0pdL_8K&n(kmRo6HeiA!pU}aG5Xra4;Wt$Bav^lWBrCs%VT7cTo)D1|Z8gRsO7fhF
zpQ9xV74yePto}vY3CUIy4CzUUoN5iuNe0XjZ<fS{l4^yL+j9_8nPgQ6%r8qa>5{FN
zc+xd~UGm;5N;`H-mOX*=mV_~e&Y;Ai0T#C<b8mpVBUwi)s=Jb%RG)TF^5HA^9g<Al
z0fYMzi)C>5QnF<^qIf0odIC)+>7k=gah5)z9I*>NNsiE5rD4%9aFa@Z0OmfaYczWA
zj{kv{?mrJ{1HI8arFr2%J0Kml2JyoB6Bgdm*)-wtk(yKP#aB9&iW!eebDf}aOuC{R
z+;QpM5V#1E4)+5)SZaKLhEmGz1__l`()=)7`i>biBk=zK0wq#v<b)1JNlma3Vvt5l
z?f*nHG1AxRJn;$X8QN-1kap1lg+%F7%9tfdfBgt;$<n7(+;<LmASqJif4Ng>-C6ie
zla3ETycyD1T3BUDZD`GyCB01BNZHb&cKFSan$abYD{a^ZusrFe?;$kgOQ-&ZNXw)l
z!*EzG9Y?#l71Cpk(77m0aRIp`UA!KoQYxp(MU^zR5h|CZ>_+^CSET*#!@NeiiZUrz
z@e+cITIrkugk2})=|FtFG&37qgS3oJPBls`7a-my>1f(cX*NjLZv}RrR889|{nDOE
zK)WIRnI_o-(o5;+%uT7;KWMupjW!1MZRzUIV1Gxt#t)izrAJRf<({-H7{Vdxv?^%c
zmwu4|zptd`|3c^_E2o#Nvuu7L%w1$>JOS-0`{_@#xycMsGhn|@X6cI%-DM_JRpcQH
z9|X3itnXuR2V|u*5BHKCm;z95nfZ2bKC(r$stuCqIlu(V*3rZvMD`12l+sYyUb+p#
zWV@Du3zxZ3#yLW^l{PXXWg#AjFk1F;7NBEfTMaMpJDreCrX}x5*}?z8?<v`$@o0>d
zO}v3|J}rCX4Z}FueR^)3mnAKN!3EhL^q8!ay`PWh+hmag5Vp(WX*Tjg=0}C|u}0rS
z0Ib+()@Fc}7>)6T@Ve2oix9ROrF+8srjeu8fY^qN7No;)*yvaa(4HE3Q##4hIHw90
z2aH{4gZq$icpTh^8~g8tO0sbo)f40zXJx`~v9Yfj!t2IyR}kos@mt4$=`R0hE!qyr
zRo7r1B|joT6iM<WlqgS=cdMXMA@>|Z9~QqTSH1^BFU3y^NPQI}JHh!Ww$QciuNX~B
z)<A{(cm#Y<QIm?c!-{aa^o}TgdxWrq6yEgxfnddA9aKUTI7N@aSKNCKF@-CZTf<?r
zBFqQz#wen-usfmXryb&0#kUG7EIXrEyakO3iicNWpR7psM8GMEORIpLs(5=R+R_#G
z55Yx-B9e*>G8N@?U1ce{XhM2P(PsrxrSQ4}ht-NIdWO|1f|B5(UUB+UU^XgN8W2UZ
z;^&0`yRO(r7ip(r{Vk{%TufSLAYeC>-%G&mH!-5rx`)Z4UohOhCOLmV)!(El9^{b8
zj!CdTVxqo_Avtd1OfTaQlUa9YI*31F=5GAGx{3CKz7C^Wy>EW+1=zR3Wc+)LoX$b4
z^`p|(b&DtA-|JUIQetg`ZzfPT#vOr+?_$=$?WU5Ki0JzW+M?V%%?f{S**F$vKd_1D
z>5u)ibltXRDKzbj?9f~LK3Z)%4EX|Kw;g@b)p6`RVD1g2$<{v~zKehVJD>K`4JZD<
zznz)+lpb?omi?)~@9)agXkh8X?4hCnUuF$G{{5KE?|}1Xrqij0<IMKSPzhqHRscPi
zd5YAkG?5uaC2kqaj$WV@Fn<@IQ)SEongw5B@~{a0zhMa&hkt~#+iKxDf_+>7yh!#t
z%DzXjc7{W67R@%-BGOp)<9U#tX0vYsFoA8ZgU>|vy=-tvtb*z#)7ZC1flFsAY41IQ
z4R!^|WdGO(^E`H~Hw^OG+vDM)fR#~kQ86n}8mfeykp%Nnc5OK{FR=<|xUFRWG%~=V
zhE1o}=v6i;AEDQ>@6)8Ij(x`*I?e3!IpD6b59!l0Eo>K+TXwMHUV?P8pVO?Pi*=p=
z^KLfuzgaLVDTdzxwt_O8H`%K+hq%kWT>#-j_KZIa9<l$>*8OAlm)*3nFv1qS4!=&^
zcl2a?AYbN*aeSm0HAH(L`16vPNzd3<j1`TJ6T4?Rd^@v7^yqM5|9JzpuI#RJ@aD!&
zi2>QielJJcem0*9{M^|Ww0iYm!)clA$$tCaTb8{~`z>Cqp{@~V-t0f~;M9k0pckYs
ztELTUKlZr}I>*_g_YrLn8=8W)V74?1ZKqgGA3U9Ak6-<NDQs~vt%JXwvKqSIoS~cd
z+dwK$T(go&nAT1qjCEmj7;b%P2M{*c4??oh@D^=>fA>Z<&^BG)4TJCh8H<QEFQ>0B
zZP``{&>#M#UHTvI(4utfKe71twj6r8{M=2y-j3U!!r87>v{CJ_ie8Po%jmlSZp=nH
zq_B^P_JeFclenDv#Dvd*KYzxEN+|-EM1vV33S{25fkiO$9o035F#R1EzEH-Y03n1k
z9=|~t#hfBHCzxm@NG!wMhwuz@>r<E~FyV3VbcK0FF;p|MNOYiv`K}6{t}<h&yt$T{
z`ZKsD=BJNg-pX{*nyQN#JV+bM_&NfM#z)MC3>ZFRnyx|T1v7pk&|WdK={vj5?9?{_
z6VBQmfH0l?9vc_`cXxH@@sBKK?o`-hGe7)<uyUAPPl1=qETlclJjQrBNItWcL$3;$
zickO*GXK&VyMi&yegyc7Olb-1FEMlI;;3W>XdA1F@gd=5Ce8`u3X>%JuXov$6zFCy
zQ+BF{DW~$DUgqvi^y3Z_ObNTY%sd+7VP+LQ?VmE2DYN0i{*i$wT-gzt%e%3g=*Wl<
zd)z=Z!oKW#tKrv={pA8wkFm<5AjjF)KE~h%u?OoxqS+Q-xQ}70DPw(tO}-1XldL1%
zhl%XR^mt5S8>fQHV!v%eFxl+Rba={P75OmFW&LUKP{LlLir-SU<v0w=*ri+OCMsvg
zlEWJI_szh*%Kk(3xV5bEUG%VywWEbiE8BY!ZEdVw4BFb+OuAA#*u~G$*2%7U4+C_Q
zb)^N|Ep{&L$PcoAQhMk%`{tJ*ci2s|^t#Lb_6E%Fv7eM+fQH!5_R{@-pZ%M*zaFsW
z^!Rzm#yWs|#C}iX{FwD~Kxj|c@!be?n4R`By7rV^M6>B<EJHPWBdmgINT0LA-@*M0
zwvH;iyt#sQ7zA+{G|h_S9#d&aEcYn|lgy1A0x98EZKMy&G;>oaCvuy+ybDri$@|*@
z8Y;O>KVG6F>H`E*DEXxdpjRZ>3lV;sq<0t49!L^*f{aLJCjY-jK(%xxZHrx#rWlc$
zG>ocZI`Ds=qU+sKmt#QclUn`-m7CJ4EAV+oYHy&@r2EncZ>T<z&RmC}pGgD8fP00R
zE>zuQ;WI~}WB4NoR7de`2rWj}s+!QaKEfC<8wVEvdehhGX#IKnFX-?ujspJvYpWCB
z?7HjmZ~LVSq3OVV04pb^>>Rq|%(VPVAC~lF+Ne7E05hI4I)O~&4&WbTvd=>p%y_ng
z3t@sbpe=@RpdF4A%=ab$i)R)uNAL;EJL904$V|&Y6dBB$cR@0lUG%2RVrCqKc{cOY
z3z+9HXCJ^ImpOa@{mWzSr&3{WKC{OGIt9$d7ceYjZWMzQF+bC+;5;+l8sq}AaW(uF
zGpFXjzJv*)sa+`(LYcfWCTbg0%9*dJ#-)NeNky<1nJc3}E-^|fyQ^d-(M43n{6f35
zml<#RXyg^fv<P;FYG!&fq&3VqGq6_~Wdnk_#{3n4p=)6_tiX6(XUx>_)XEI*px>1#
z>qZpq%y2YR`kBvcfqjE{MvK(}=F<R}-(==fcJLN6@i#yZGMfdU+-9)<NDqlm=n0U-
zKHmtibOUQg50XqaoC+1P*$I?h&t-K1P%UI1&>H0eTlF0}Q_3!CqaLzVRWPh%M^S?0
z3VVvCo3-puTVQaF?WSF(ZuX=rLUZCOw#p&JAF-qmK10}^T_B-sSSC!v*mwXL@Jv0P
z5A6tc`CPb;WIgvFkSI23KkTB}TV;qYhP^xrK2NZYc-!Hr^Wy?|ImJHu5q7ccB&wS_
z&GPghj$@Zlb<P<!!x)-p*$tGWh-dB3Kr?}@?FE;}hMU1r5*tJ%N`_>1$zNzZ#~!24
zSZA;kzX4as&I$!g5&L`%Kr7g@yU})$JztMtF0u8kP^o0M&%+qkv)RAGeFK|FW#NtN
zy##Pgtm6gPb+AL9prf7a>$KeNVy7*DT{ru;JxCAx`5qYbVq<$c8vEGb-(c9!uDOVy
zZm_q%Mu-D!-mieU$<|P=_!fIi4zxiwm>$x%S-(lpyu*G^N4@T{uSJ7AVZWm3?J%1W
zi+G>1&*&n0#&*-9ZiJnAAHwJC%3^4~U`NdcdC3|o{m{6d`^*O8<<4E9ho&Dlh8|x2
z+((ovKE^R>s2u0^w1JD{RFvC^;(p%@gE-DD7%`pU-l6@f6z)D%$)s}8-O$YC#=C>$
zaS}=kmT*5%bzCVIJQ2`koc&>FR&z@XTF@Hq2xX|Qa<48Us9G+Fo}_i$>^ij7a~?C%
z*1%oxhu=o-7y5Wa6L*$=pJr~_-%z>6d3=swS~v?E2(NQb`$1Z{>FywHoPwrn?c4%-
zsdsP(sRp`}`<2cv^l&Q@DZ$^%9il~LA9tbv?)$k<XxV#{J3<qrTb$KXaD!aHC1~E}
zcE-T|4tL@P$PgF28st9bwgK1=xLdTb@PfPRf^IuWf~fM<S)zD~HW!I<BZ#Xcm9}Ht
zB)zXebDyN;EWLj`Boj>G$y35C!q9k2Z2J+6kK{!J!uOTDPMZ#X5~si5$zPKG2ii_c
ze5r&xMN*UngIvjKN-q>k>`p<YQnD-&!dsG)4)ps<P5Tgqhinp!jJNFDJ23Z^-N}K<
z5t*iS6z;zuSx+LQ!LmcH@Dw8Z_%DPQD%%nV5+<|l189WI+Y$js$r3(6pfR#E6M&wS
z*}sDDwCra$2;*c+%m8{u))<Mlv$BSE*u~4zFQD6rGQJQbN%rP-kYrgmz9{j3FO-wt
z(fEHmi<WF_5@qnXcEA{*>!QCw^y>|DP<lhmeCTWpT8O{5iuZu9t(G1=KW*KCfB!tC
z2ReU-ybt|d7pTzUuM0F&u&X_czwJl&z>~v#>e=3HFQD(nWYg8Wk13}qfDdD6Uq?g2
z%rgOuAG0$O#Gl#MiRc5Er_XSe9A~=dJsQN+(;Xhn_|Ow6gyHBK4`u550G-6Ba^Wq5
z8F2<!9ur10=nKpRIxSwoT%`5a6{hTM3{ySRnSvNwm`}d|*Tvj6bRn8sOi&M`kC~@Z
zfI6`^X+9IcE~nkaNOq_D|6fS5O%H)TlVbpG0CQskOpi11R0tTvygwTu2Qz(BKth<5
z58yL~**gWACm3^j{lqg40f;<-k)DD<BGX5&>m&m+YZDqXnU;lMvlxrj7=Uc%Xg7ox
zm>sksTFiV%Td0*xE4?wQnE5&g8yF8tv^6qgX9BIA@r(o4!DzO_MJIC)Yg6>@C~X0p
zVe`zPa+b~Qr%Qr$n~R<&ut&<FnaCPUXkn7Xx=sd3X73n*oMXfGplg>{o~HHf?A5p6
zFr3St1rovCp?ppx=T`+6QCu$zztLRv1PojZ7ffeAPH_HXV0V&h+Xdk%Zp9x^iRJVk
zqJyWo=zkDQ9CwQ{+kTQ2hOub$m)y7j5+JD&;UZ9yu?rnNC|P*`_J<^CNr>sNWHvpL
zk4S2A!5x)UQC0FW$<#2Y9G8SqJ$#U)Zw37Rf4yCcUsT5x-kG~xkcTXaifvPgu^>Ox
zeP9+a#EJ{Jyj>6wH7?7#A`0xng4RbR)(4;|F$Nu9QKU6(6p2`Mtq(-48cPjmY9(T&
zzFIZfsF9b3q~EdjPiPh{=bkg?HN(Ag&&-**yG?nCqKwsYe*)EBo?i^R4RYo%V1JO$
zQiOh3*7`!=h`jlEIcjlSu4)8NlblUMq-OaZbxx<{xBS4`E$`R}*7w|NegpIM?%JUs
zo_CKt4D8SD56j@i6?eb4UPXZS`6=wSz{6oeBm8>8x6sqPiywF&4)yV?YH(LbQCB2b
z!>|9Rv9z(#;QT$BB(Y!!j3@Pd4%^B7l&?ss%!71l;U{R5sq2bCH|-b(chkIfLwM$q
zL@1pV*M-t|S}4ai`@&tEo2zz#o+Au!z;Yx7QuEbgaK7MYl-qZTO!!~AmbTh0n}ry(
z-0hd6A|SS!?HP*lHSF3M6jiW-D<D>~?NtC(YzrlG>e;fRP;`*_G=b$PJ3uM0X4Vjm
zvUBYH%^?1Txp@LyW^L3y?JQ#w{Jp`dz65rct#b$VkomujigvN3XCT*K&SrX}a3yaH
zhF}$soBb+e@o$<3-(!RQ&=PTfr3<l4>4AFpunGsf=w%awq2>ikp8%!bvQ2v+{yobS
z@abJ%HwDC%yk!tLSMlU?&{V;HyBLNl`LC{n<wG7<55+aSe5nV}eO$HxJ;7^ly^6J4
zc`8l0we$0|uK7!D>V(E?{ID0=qk|vGg3xuoZyd`0$$g{1`7b^v1lR+<5TO}@g(|vr
z|IH84;Q4F*PCs1e<6()Y!E>HKbFgcr&|VsUR7-v?=-wb5vZInUczi){qtt?W{Wo??
zrfBOM_LK$=&)9Mbdb^nKGT7{9J|94D58E{npqI&d5LfceIWMbyb0Pkr@A1>)q4w9@
zgQDDxeE4yQZ{j0p<RtjKcA6O6$%80iTFakNxVnokq=u^FV`)-%4?jTrcJ}gPT1eFM
z$y?z1LEhR6ONY3IBH<I<NLj%q?%e}R=XeM$fH==hWoV;TE`1NIjr&lB<{Gb{2X6;g
zwnN!<e#u7pkH7OqdgaIsK591#JGnj`g8$$LX=UY2UVj<pZ}DrilKeK0v7u^D`4-CV
zeZ#X(0zBh~C<y7|AzLBW%@6v6*vpsFd!e55*J!8d3!Zfg*h=X~QE+CJG=Uc9)=Dv$
zU&H*XR6^_1PD%@CZU0rNigqS-O1XEz^GM30F<zH6(uA^pss92vS1a{9;fzqKqM>xJ
z@-ri_Cgo|0>spn6y92jxE9cjNvq#yYg0gjP%MXEbqgyDY#<#fzRl}z`x9zmHxE$Ln
zoS<%(*C88&2mW%JcHSuuq`CWAIkyij^NE~l1aYsd4*;l_jnwxw$ZgayG|Hwczz)lC
z)8U0nUS)y6ALaN;cyUZ_q%9}M<ryJxtx2xE1B1<S5#=;b$tK#bdZt{yIt226k^@x`
zJS$gFHuHjPIR=S~@`Rs)__^#i6V9~C!)aIO7xG6Rz3T0zJlc*HH_oD=dHk5s;7OP%
zK|FC=Dkw>BR>6nlRJwsvjtYpT);~n))XgoBGJUrX{-&AA>0Q+6_1&oZv`%s}LkfkW
z%;#(1RaOb5xu=g<1=j3&ZBQ}8@F_TF=FNrbSrK<pIy;nd(fFb^n8~TW4~j)YLzmpl
z#o)B+Y1`JE>f6v@V>D+pS50w1-k@5X&l{ac{eS)lPq5BkJ09l?IyRuVpqQ?u!s-p6
z7il(uV%NsOjKe{13@EPdfGZ^pk8$p74hDTuLMqOeHqc(86-=6pdQ>uVICL~KtYcRw
zYS61miUyo=_F|xqg5d))Q;7U778Ie5b~p<1t(MY!dy!L}J}o&+XDG|H#mB^svp5`T
zgT1KKR#fU#$65>W9Zs9tQBanb4^Gk8%VGlyEmpfzKi;ezM?X4^E=&`t4b$p%dUdJY
zUf>j_ZZ_fvurW-;_pl}ZZ$q<se~<<n>YCBV-n}cN6xm-i+kJutn9auMBy*a<AS_$u
z!J;*Xj}qaXJXFMd<~dlL%$5d-z1h-8S8gXCyF{#h;4xAxJUu`qYP*$Qu6x-MbBeez
zUZX35E=o9*INV%87v-8@5&yNfS4GD&+12sPeNWerv}p!&R>rh6`eUAIcLt8uWQ0_F
z{J_KY@q+;iYDD{MvaeXb#!D$4-Qb=syspYGU3{zadE15Y`NeEk(HO5cV&l{qPFsmn
zZMBpX*q!PayS1$F<u#O+HO;7YIxJS3xzuJUR2!mG#u_XobIi&1Ib{VlbGm(Q=^{&s
zO&w#)Ez5JQFZTMPXOJ;H)|?rglo1;kp?UeqaOLKEZ@u7(4D)eDi34ZlVIujm=NNId
z#(k)Gd{vfR+~Kog$?!<6Zmd?X(S!tQwd2CZX#;V2>NMe6oomMfpGfaOtu@!8x6IL7
zG@9@Tt<ItuuM3Z`>a1^CwYfUIKD?r*+Xu%$S5LQZVN~=9x`Plql_R;r5e^K-!Esyv
zj^IFr;u1lXLV@M&3XazZh2Xy9Llg?^vQyxjOB9P;yTeo;dNPNIoTysFazx`qRVv?)
z9rZs~rSM)Z(g@ZnMIFJmLE<UF_90^OBvlGii4P{JQkhZQB;XL*XaJR1LBJs{0r1)Y
zF>*3kM~mXgpiUL12snhF0bsMR0PxzMhyw=j1PB%bYNap{2oSpntQSuRs6=!uSdTEV
zA@-%Zn}pu;7P>f~)5VH7p!<i5%Y+7q*QWq&`>`mQ0(8AN1(b{$L2VBdxkgauiAJEz
zL$LUlg(d*r9xCeMQRpF_5H&|cCxH5Rtk{qMYNfadl>I_z6IG#@{t&YhRU^@7tw>Y_
zyWRVaDSXAgMAaL-=f1d{s0w0Hq7Nl#pVyOA!F>N$A|Xi?#P571N&uO^*aC7udzebm
MLY?2M&;L&U1OB}~NB{r;

delta 127509
zcmY(r2V50L7dC$Pwyn2U6MKx^XzUt$Pc)XOu_kIXme^Zj)Z~hyfPe_7fTDsZh@zmN
zAYuUv3Kpsr0Z}O;O+`gPzUT11@Av<I`Nf@`Gv|5EnYp`D&dl=GfAE8V!8@DFxt^z5
zc2+xD*9)>HlWSG7J+~Q|B>R8=Q!wg(I*2j_!#V7{Od(f|S))M0&WYk=3Z=^ZBPUbE
zda*M3xJJ`}R4Cb)E^?WIQ@x0R0>?JVVr5pPYSFSaRHjfu{e3ATQ*<%^2zAXynanp$
z-F2AZm_l}uafOIe$~!W$OAYsuvgDIYcDdnR&yW8}me_D>mKmlyDP&2^e(394HIw&e
zWHRMC-x2Ir8e_Uj)=KV)0=sgX@1JaoZ?j~athM|DBnnQMT+GOf-{M}?#uXrLx>AX&
z&r(*#aE)5XWpXa(tnUrB@pPXBENR6~<Yem3ie1n(aosbJs7oUlSx*U$<344tDC;F=
zl6jd;qGDCEKt`tStvF2xegDSt{~`wd7xDBT-vOM}(eaE*HoQS3$y5shSebg1;yEDZ
zB@s%Q5+IqZ3;r>IGjY%C_$WZwneOG@OXR{wg-k7PK+C<?$fO4ZEFYwjRp91-z{CFo
zRxn-u3uNN580ZYzD02|e!Um!$=Km52LpN};3`S_E8;Azs9}_4j{_8;o)Ac_@^BRaU
zm?5Mn_ns~H;Z?G%|M4u5SA9^)vj3M|(_rP^|FSD&_FsDmzCZEig;cB4%s2n56_LdJ
zU$q9*ng3<i$b^4;aI)=;iGDTuuPy#Dfv*4aZ9CKVKRj!gC$H5|{NX>ot&j=heDCm$
z9As=IGx&ckaWqDS?5t3*$-Ngd9mn&?uA(1O?mbUFzL8S4nz4{Ax%Xc(;k((atl$4<
z`*MTro_KN^ewlvEp#Qc@LqiPspVR+oh=C1RHHgp>zDtC5y~vfa0sn=FUVAxN*|c3C
zLrb#M2o?WveF;nLSoxpK8dmVVCA4k8?)ZPOJN_T+&i_Bw`~PC2JBXh0$<;rqWQryn
zJ=ijZubfwzn@?5C6kn=T)=>d?Cz}ZWDRO3%|G5ceL{)S3Tj;cu6ud?yxZ3gZOLCPu
zOo7gT)2ggTeKp#y%n!bUw06ebcbc}DG}lLzDHUOiMb)giud{X;v)1>GwilD@+d<dG
zarak7_8)S*cq+Uuvb0YsT+?+tt_vTjam_1aaP6Ex3eBd;ab56U!1cF}r0-fnI>Dc)
zblV-mw%I_X{pXOp_7FN4S<D3y*Gma>RV<|IyZxl!$FZ1_;zAN__M-dU{Rv>br@*y5
zjO2g05Z&J`SX@uypGwxRFO}}-P3HBr<k08@y2=KS{`|wl&@P5huWY2*w}K>Ney4l!
zINe_vLfC4HgJ6o;1ncfe=1Vil>qT$L%*K19diOJ_?)ifxzJHQt8+30f*~>&~p}K9v
zu=W9I9=%CAS$#;-WFXxeQ^@3lWu(8anD{%iqtg07x<AxO=|J+!Z=`g09~J!6lg!5t
zC%ProWO%>^s`srebRAbl5_@yfyuF5WlGDkF88@l)z!~C6ZBLT;GAbQ7jP5V2rj}S3
zNhULMh=2Ncs>b8lyv%`SY)PtW9bKmdlIqtD^%(mj(KY>s>Y*7&HK<A<y1qdqcP=4U
z5;I7@{CAQ+*-mbCyhic^&q(LD7G$P+6kW#_ljQPZx_8nOTlo#>J7ncn^5|9xnd#Bc
z22*d7()|6TB#t1rvVSG;GrayPS<OPK>&C4l=^sOyL5GQ9-na(mB1w`yjNBSnN|Ne7
zsNMti(f#k8i6QC&xtQ5d4ade%GW@A6(Z#kWqJtcnjBIG$cFXDh*b*Y$TG7xFYe~|i
z!O=h)(M{EovCh}1_Kj}QeY0ES;);f9{PdA@woN7Tg&MMQC!TmhJxOz)Ba(^>vWYao
zkNirxL)SiW<VxR$7fJh`?w>U!%~=oW{-`hM{JMk8r0B_T)IOs7dLflw_=eaVC#f{?
z7}Y+gADO)PoXr2)Q12*_bgIT<+)>G{@1V@5U+7xXgp{&(({+JF*Y6@pXT>=x?eR6;
zs}>OHv4+RCMMIq|v&rx(H*!Mx3mGe0O_KDcgj%a5Nn43ZZ?7Y4+Y!{FqbnMo{}IKM
ziK2;%?AszTnc9}_&&UX{|2HBUnnChG1*GX*MAvx@hCdaPj`KexdH;ya$huO!Uw$U}
zhh##z=Tghnxl-wsR>Zs_fjIp&GJ5`JDhRyNgKD<t1{J)^A@H(>&gZvsx__c3iplG!
zsV{nxf&TaC-WT1kO7`V#!j}7z=FS;(?_W-(yF$ohL2tSq+Co-7uOWHkR%9ik63>J~
zc4|C{h8XGkX*$uFH_`QwHv!h`NS<|`%-1*kmT$X}`8}_w9)%m}v1(=`N&3$uk#8sS
zuXdB<&!C37x|8{T?~+L!N6aD7RC+>1rH((Ykb!e!={kHkDXpGCN^38X$-DWaG-*3s
zb90H>i6<Q?fDAts>AtC!9Nm#b66rqOGnkN}v*PF)@{Y{gQt4X#FO^PQOzku_neGKg
zB0Ua!ek9eSKapR{wi0P{V^X?yos<UuOFGpU_3%s#Am=(Qq0-QUbgfAy=UnSa-YtU|
znm;G~BNxeJY)e8d{FAEp<xP_J`I_|4YRO`z!$AhtHY25pE$F&vAQitFPIYA`5$xVv
zl22_<;GHXobo37-`DX@Qmsb*zVGrGBuWV@iNu;^{GGR@9$i@8kbg%11w%TtXM>RgA
zKXe99{r}frl1bYdYQTm65?zZ3B0Aich<Z6lQZ>B6(VKKXCWOGtRuSsYrX+89oD2->
zLDxSd(z%9-6h?|sbe$4GniF~uTh|;i?`<N@5#!YK{O>KNf=z$ZwY*_SjTle0oQIjd
zO6E6{nzY|5f_-f09~(a-a7F-;E{h;n=0}kJf-_WC@f?-@97l#Lcaq#vOFX7$#Gn0%
zP#b#@XZ}3sJ7hntB!F%@0ZtESXx=CS@SEv={Y$#0)Kl9GokLDolZnVNl~8WK5fN8U
zq}(rr`hE#X{5=SjgJqIR_GT2xN5<1N%ue#}8%CB5|1|Iv^dhfYB+xb6jSMKxQo)2V
zbU$!8)$gxO1U76Wx$mz;@$7e^uGi2#hCP{DmS`qPKrg!gs8QnjX$e*;vc~wy)Uy6z
z<kki+EE8nIP6)VO(_)Ds8{!z>@H_3I8YFrVpyjtjx;Tprk7{@hW*5pK|Mda2!Ol!_
zVoo)I+m;ilM?**Zriku;)X>!^Bh4WeV*ZsUO>qHLriGa}zrh?9v#AU<<WjDK0EU-j
zAiM{uuAfFe-X23<cWz6bF78XJ8Xsz*^dig@WN&(q&XGX6j-5q6#NIeE;Aoifwf}-z
z>sxeUYT2VDBtO}Wu#2s9ZHh^aS~jkLTzNQLbRZLeNuyfUbTpY9ypLe}&_AnX2h+(d
zdsnJ)uZHI!DTJt>G(0OGj*;OoFKYIZP>~8`sz$x$qVBD?VDheNpS%dII&{b1xSzED
z04h2;@-<3-&ZkOGDRlvIs-y2j&`fi;!?)?J=uw<|(E-?k(KN`c$fIBQuN^eSbj<h?
zk}XWsV6>|TbK@$KJ<K?oZ}>5@UcpI!W_c2F0Zid4Bzu__MS$&NhE0ai{Y<}7SUtde
z=!%*jWTX(lgP2~9!7v=myvT&=Atrkkd<|h<&{%PpsbL{J!c1ks9m-5|APHmk(y(`w
z@%;g8;Y^#(;6BD&8Vta3rukp+Jc60~0^BE<->KI=$+S5S&PZl(JcLoq=O)OVVlLAF
zc$)d$#Q}UYGeAIL48wSW`wa6aA9l|&HUosQ%uwo~<Cu1yU^~Y+hawlxlwOAU^GwJg
zz!R89VGv$mdQty+ky+^nXD%_ZHDI~SgiuG6$XpJCW)kBZ2=iAM?Fl65%q@XI|ChnU
z^@QC_#(f$ZJByj^3+`-YUIGyJnBsVN`jDxc4DLtF{wn}JX4+7{mc#VwfaEFjq67w?
zF=w@4dBJRT0icLkN`px;qwI?IeZ{Oi1Y8+2;RA#fOs^7<RWkMOIrM*3jQV#-Uo*My
zki20k@?iHZ;}eJaRx=}qK=_X7JOPOJ_?eOWz<7KGM?W&ZSHR#Wru!RIw3hif4rTRB
z4E?@N^0Q4*wpo6_8y>pLC)EnDkN;bjZU9mDxg!8sCZNl8sFr_s8kSb*N5Sk$pFeQF
z>d`=~2T8r9wJp>;A76$FcB$~k_1of}kazv735<11qGvaVF=D0Dpsq}6f!eCAH0@?r
zHwGa$ARH2YtqKcgB5YAJ9qzR~@I79_Elk2EIojWu2}K{Tc4bzbL$%zP9+<PKw=;va
z(06ABH^<9)fYD9^+d<|=4piPVnS<a~9TRX7WLxD1dTO`JuMLIoyXE(9Ar~Njja9Vj
zpxnt54G<~cH5a%`@-v%(OO+3JgVij#qZ{j3f`TvBErC{xr4vBcIc*yX`d1=;qnbG7
zTU2mq_A*>Om~(Qt5X#J%2i*kb+&Wb94&!x7l&Rk`tM>f234}vaK&ao1VL;vCUK*;|
zvHmma(<yNSI+Jgl|K?=!&J_Dncli$UGPUE|Zcowgbp4%0J9YEPfz#dhAo`=~F>n(6
z==tU%{OF|!$FJFY{RLe6B-6~K?^Bw-42^a|=?~rZz_Fh^Xps1&S4-$DygV2@D}QQ@
z(skpFkUKG}wxe>c%&g_$_GPlFLE^{!z|u>7h<U9*a)S9y1=6$3n<;QRj%o1z9Mj-_
zJk#L+d8VNP2~0x`E->V^I*Dnh$rXlb($K8JF6!eg&ogmt<U+oDIqL`vw%B+Eo__u3
zMzm*}9!=1Wog8kHkbHaD8^~^%=zLXuPA`Hp{kzl8IIsh))rYmFhvxf2S|g2phTxrQ
z;;MfT=b>NFw(Axsn~ds+`>&qT%hvA2U%2*I-T}r3Mqh*c`*F1NoY<7!x=l<1O{JZf
zb34JanQ<JRiL5^}s~Y41%z9_IwwFnxas3dpe;qhNn1z)99%c;L@ZuzsO~6RTqXKrL
zm|_7cag1L9;OCeJN1++dw5P@WRc7m-09<1{PDArLGvNrTlEqx7H#wW>mJYM`nA48-
zz!x%SJ%A`;exu41Gg=9%@0f8(z`ti!w1B}6%nc_9x5>|a2~8LIh8h@jm49V~aF6^@
zBP4!u$p>Wqa(NoO50(2J09ly)1}z?s$`?%r?yS6YEmUIV*H^=fIC*BA117G^A5d%~
zS>C7yg?HtrDFAa{e!n?{Pvqn2H_MfK5xzh^JqnFmC?D|_xl;KY4Vvqn+`bZ(*`%1c
z1Y}zkS9kzC6u)kRrl-OMgQ&`1(e?p20~9-3K=ZJo^<U6DqBt;0jraeQ!s{w5omNyV
z0BNG)=J&uSDO@mdZ}^Furw;|_s~)Auwkqv_dVlS;R{fu{A)_#*Q4Q_u1zW>@K8O2}
zhx2h=P$B#8v-rjQ$*6z3gR?-|@o6@$ogcQwwQE=lQ1oz=H-mq@ThWvE-TXxm4QTls
z?LBzV_i%Wabum=O9Hj}(BpHp%Guu6Zsd@G{C|xpd5U$J5SAt<xyKL0qyt>_Z)GR?g
zdK-*hP&fVoMOW2nRIwEGAO>X_>d~8F>!JE*9z?f%d$iO!x_(9lz4?0sQ68iHNCW11
z?VoR9&Rf6aC**eNZ%6<4fj`MKeFbkGGrA0LKVfQY$mKFlG-y3#VvHayV7lzZ&-;vd
z5`tux{OVOWvs-@lC<y)J1vEYKmp_a}vR7{WtiTwsPcBe1?3cfLi{ya(>r0>sl7BTB
zxnOzpIjDxn+Ydu+56c(2!^<=B7AKLMl`o@3b-Mg(A9#@=zj6&Gvg83fP{VBb#Vp|N
z%h&#f+ynXXz94%f?@d92$MUu&;GW25o<hwXx$^tjP|cS&T8`{fc}og2J(Evc0Mh63
z#*bjBP(Gy^l_`=B8USI5{Le*TdnuojkE*?rKSlswRVJSw4DL;epnp*2q$q!gWQ)QR
zyA&#Ch0`Q>zfG~Z49>VH+-VAaRMDT_-f)LvJ^er#idIUfW-6YjL6fcMp96#U6eY)?
z^FYy^R*er8oo2(C$BHSmg3eKVHxo&&BK&v2^AxL6krXJT8EAxOio8(dUMSq#16QaR
zdJbg8iu^R>N))|luq{=XmV)|~!Vy5`%N4c0$W|z--b1xYG1~~5*NVX%p!!zPl$L+h
zieJ2td#~tDKhp=r8X5{dDr^*Y_@tQe2*NtW6A_x96^5m#p_B4(Eb6;iIerO*Ta}03
z0kBOu{4ngfDtBa}o^HzT9e<z}?#hZ#81zu);oVa0P<H(UHZSG%djNVXzw(EwkFxDw
zFuzObFF|v+^2dHC^HVPGg2Z2WgW?GLlnIeg2~<{LRiZkeoOusk98`9ox&$lT9;57#
za!3q(I-*SXf)}C6F=wy_R2@~S*1)%LrED7z$CY(`frwB>_CW5WvPDy{MJfkT<l~g`
z@&Eu&E9?717^4i#z$0)*c|RS1IAzsrICD;UuoKA6D`US!lAt`;3@R6u3Jp{)Dc{nX
zF;UqI^L<s4a>Z4O0bNzDQp1aD%GWftN>&=~g64*@V<J>jl<8*povOS-kH>B0!tbDR
zN7)+tU8*$Y)&ZbNS7!RanM`F{3WsJX=cJ*A_mt~;gXO-GGXn5X8Be|QBc&?^o^zDt
zc}Sip$2-#;Fi-jMBdV6KJWC75XUZ=q(D_`ML$l*TrAtRxDpIN+z(k3%s1<}SmF4%4
zlqtR1!BV+0bUB)&Qu&tzmMUcrn&iDvR@T7#x5|_pl)Y1q^#I_#vd;>T)hHhfg62o1
z?G`v4waVrT(NJ~DX$PURN!5;46Hcnvg#d0*b(sPhXVujvaBZ7v)L68oi>j3wcHLC*
z3gEV@mU5u+P_0r!(^EBlDol8(zPJw)J5>`V1LvbUI1)l%)v#Eo>``TnfCWEQaX#z?
zI8?jhA>FHbKM>r3DyQa9-LHD!4g5h>bRrr!NafQVDu-0I^#F#bEa~(JsS5T05UPqk
ziCnnq{cu=1rdmnM%m~%}L(n{-`uRLOj8x5wKwY9#bLi!WR!N1Rj!})K5%R3c@kKgl
zVpX3X!R|TLWD4iTtFkEMoS+(%2AvD4>3;%$N!4dJ@RwC~nsMD%mH8s~K-HC2A&*s#
z{=ns^_P&NQxvFJ9pe#=ndK|*1s@X>XFHoKA4@1vYV`ONq7ph$pCn{1ccF;gutQvM5
zo^DdJ7m+xrZQnt-MV&MsJ~^xJ&@z3SI=L4RE^5awpm9^5z79*<)knvG+f)4;g}ZjB
zA5y@{Tiuw3G9R@r36^%N$EX3=qc;BoNBz~)ve8Zf>gI`1*{ANrIY1MrUUdP$H1*c+
zkV{v8Jq4;+>inn3Wvd5HgirU?xqX3np#F9%a*x#gDUSSD{Zl7sK2c9;hg`0Dd2jfe
zub!_!?y3403gkRfPtt?>xjHEnRVq}E83@iIb>bZ4O4Q*eXbtdE{bn(Muhi0HsFtbE
z-hib_b$bTfRcfD;pn0n{-2|{&Ekr`|gSz~8cu}MNP>Qlz_1p!hVVyd&FW~j+y%ZeU
z#Ez+iiOuZ1TPWMYX1+!4B-@RIk?iz0uyBf<IEeNjPP0|Jz!t-{IgJKB!~Wd{q_J$f
zEac+Y5o*|tXH!;#<~%#134|BeFKI{VA}gPOvde7#4Ui_X(`dSSg<UZbDp%PN6al}^
zp2~(WnGK-;<xMs<2zFE0HPoTrVt=C$k>fU-+64yhvQH^kpT_=8Lq`UiG8nl`mZjf5
zo4wo}$vt)fP5B?Nqe_r_$g*<$zK>b<4ZP1`w@}bNmraR5?eo~mDRAv6du0gh7O;6G
zF!+Mq;f!1%dkY<{s)U`H2KY+{+hH2gGPd9Mke0LEwZK=gT`$6m*X(yRwpO!M6#jX~
z?ivb}8uq9Y03X>d6nd>=$J6WonSDPHUToqjdqU{M<+viZg?m~AN1eI5VQ^*}cQzi0
z3pes>0Nl8uR2bUMIqq))sRuWf!WN!f+(jf_TwhnH?&PMd2i}MK?gS9N+?Y#9c5|(_
zz^6T&J{CSDaaa4H+E=*q1CU(jl2$;N%pIc;Z3;Jr!iTBc;6zxu&7G|R=N+z#8urq-
z<ewl+=T<s~gDsP@(NZvr^VkKN`<%%Izz5vx3aCEfZu|=2V=i<D%;$0=4g#3Rou#d`
z0&eqOkUrzmi2DVHJ2Wu2ax>t?Tmn|osuJ!AO+HGw!e^+<D=sY*9+q?4Mgvg6`F3$Y
zr;2+t7RhVwS^)~*a=|5Vzna@N62cGM+a1*ETscj8K5-rtAgtwb+Jdc~d%YORCO&oo
zG&l3X*OA-8Z=lC=EAODj-^SlaLE_3k+mA}P@vh6^j60uK0Sg}dx~DAOza6~78+b21
zcm`Cxd8cj2`S9%mK(m|wNFm@oe7_{v_2&;BM=pS`H{fRq<b|_f+t0gVyI2*(Pp0WY
zFu#*lHzE8D>TeG7cWI^?$}jGVCJE!qyipd;=j0=IjIV1Y;Qfo>=g}<f1iynt63O>}
z4&S2qhtz9E^H=-8ix|H9RB)f=PZlAG<v0G0%G~4EQJ?aVA9({RkNC7pfamZr$B;bX
zd;A2udHn5;a5SGUz%pF*jCbk;+;hH94BRf{-Tnm5QN-W=5u_!2Kq?R~`9A$2E#v!j
zf=)Sq`UG-Sd>X>3s@MFYtH8hIb+lDc&0nBZ#(TaoZAO0JvxcK;pZJ+%zLxJW6_xnR
z&prdrdVXsJ;7-DMcaUushTH<RvoKeSvaJrmOr5ri@H_!Ju0nY*fZK(B525NVBve7i
zQ~0nEDm#RF+SuGFbf?*!w{ZDil=%wBMgg}=*f0gSJwl)kDt>}~F94?nW;}$^LQm?h
z&IpF<Xs)xuB8r&A3H}S=#W}&@MX$_xAwY)01mQ14EmRkUpSFYMlAxmbYobuU3zm|E
zg$t0oDxA{+a7`FK7@En#)i{*h5So|4rxc<2Jdmae(<dT#M-XXgcUNGB0gxe7EkIeO
z@Z&WIvxU#J2Xaqvc65TJ2SSAfzrjOc;&hmJEbOE`yBwiS0d(?&sb3<OFGM<{76roO
zmcTy~vS~l@g`gXZT%mA`#`I#LlD29~gv`xgDHRma5WW)rLIhh?E<C4wlM3P9Sddi-
z?T(=AwGg<6W?65A{iU!}EgV7QS@l6^<%*<6c-aL8KMDCSL0T(pdW?4dEOdARK)rC+
z03jCTv@y9^{K)|C_lhlOd9qLZb_C%2Ma3eh91tzZa3)C1><ur1MbinG4-qHP6!Wn7
z+rP?bcsoQ+j%=7%7z>?nv7k9}$HZl{PKXdwXz6r93`l{cNYR-l2vK53ngE^_SM#tG
zE#9ZS<}>2aUQjtJmN$ppI8o>8)Wz%=z7Ms&ByQ=1qRV2z3FMN*PPAKbMZ8b@K-b09
zC(snhVkT+c6sL`YffUh#)wk-FxM2=*x5f2)k-ID2yM|nvSWd%8hM4#YoSC8*{npvy
zubzP46K~x|*#ps+LJJSYVn-tYAB#!z(ULjh#Bx+6S5$R|PM+8ihoV$Z#jB6tZh`pA
zOmIIJy#wId3vq8MREorWirf{8B5iNH6tB~^YN;qcj$EDCJQQSGCEZ*kKGKAdXft0a
z#}z*9l2+3}hTW1bkKEWJeg7I#Kj{EPk^QC1$v^~1Rs-1fNsA^S7bqRj!;Ae=<Gt|d
zfRsUt-h)ymITIw!=mK1@B>x(@L(-7*uyjP){2qW%$%Ur(;Zol~kR6lG`~cxCsY4Z1
zZcD>wP=xu8w2_|pyOKcNYMP|zh9q4Iu0fI^jaZK)Q_|3IkR_e6Ajy{ApGI;|+KjU~
zs{7K{6q(GI`mhi_m0mtW?Vn5Yk0L3S(iyl`BHg2{>6cRE-$+U&FN)i~lDv~C!doV3
zSE^wH|2OYNTL~?v=K}Lpa28s))ztHld>wKdm1uon4(i@!U<=6GenGqV?IyW_ul<R5
zU^^sSfKEqib4WUEqy7GGobupTXIW1;*(J3O*Kds!tLb_=3!L5BkQ3b<Zv6r4VHp5G
z&%GB>gI><XFwon$6Ouk%=Yp<pF2bm)?>g2(vtKN2kMwU$q0oW3H*g)am7c`G!w*4c
z$OMYj4}IPihKE_{z{2Py{UD$EeG2Xug!X{Rb^JB(Z)U!s?%318@K$8^GAs1ZJIKr#
z3(CXH(?t-5GmGdqJjw8>Ea3QmJNvH()ZAHL>Nh=DuN0W}WY^RDVFz1v201VGh&#%5
zvMv-J@n%aYQ0v16(e%TY{e#v7yVz8UEbL|*{Y??BJ?ujZRQ=d_rAYkQGCvsI$99)M
z8psxY1K~kdI)hvgJ0lx3!R!ZWghQ+wt=o^V=cykFWp8hQYhmnwaFiWojbl(2&K{)w
zsblQA+3?~xn>hz|BiOTFfb#@fBa`FzKgrIe{gp`ei*DeKVi&AH;VHHih51gi_0u4X
zW~a(wB8KhFBRRwV;fmHd%g(2{MJzk}4TN#*I2w@7u?|`j#Ix6y!<qA}$ro-XunIT$
zbb<9ekFtyGf_F$RvH39&I+EC0dcm%+Q}yulDjP)8_-pL6fe>D2_YZ`LWcIi}oVme{
zD1+Ub?1n%9Q`w$9VB!}0nI_4%*>j0#^*d~Gd%*9qaX90Msd8@#Ea_}|Z>VIjLvKMP
zn_Wws_t+H_f4=Wv|D=-_4_L47p!$#vYL4U)d#^cEAG0Qk;N-CGN{~Kbmy-Eh)-@Gn
zdF)R(EvL$73%bCWr>t8uuoSSZJW%$GJ&+5Q=j>M$=X=2}qAmAAHm5o47P04P)l<xl
zC9@^0;~@o5U$UABC@f`fQ{%s4`5q`NWAm-Zm9vUGn6F?ByO30}UtNU3Ds~Zt>R+=L
z`@@Sj>;V%Tearsf23$3J@e&NaV}GZkZ|~U-Eur#}ZBl^b6U!x_>@%Ca8=Cd(7zb^g
zZ{m)WLh8hgq_Jx&S9Ss1F5H-%NL;y;I+ShaJbwq?oqPKdDjr<PL6muNqiN%E2X~U1
z#EVnhMQ$he>pXCJbAj8C^Wi?y=;+J&=L5crE2lFaySax;kn`iVdC=(U&lNvKHh>#(
z8BPUr>9dg>;(B_+ZV0!b9}tJR#ZS>dN4RCw9foo%d9-X8H|`Boj&d_3u!M8_DKvVF
zyVnlF<J_L(@F{}Jqp8ga?mQiaI?1(P1(irHN(NyRmw5y`ysA^&u<?+d<{HHU7|q$K
zNn^N03qg8@n?_5Ev)lkW*%ZqKP(&k+o2*9F&T;hz;b=UUTLI1UT-+cC6S&kKfM4J$
zuK;k7dwv*Ym$-C_C|>63jw6@Ib)kMJi8DT@_wNcf-x-BhxlXO&)OGGJ+F?)Tp7aOX
z4K898%-`ge&~d>OZUyz9sa*d|yj8cj*X_Y}o6Dl{;tux(d3cv=KNG?<u2(5k(z$|R
zu#~|i({6Gm*FGOAS=^J6;LPU2tDxez$E_X>o%>v;RB%7w{-QHA54lnb1U=#w)4{&S
z++X8Cn#0AE;-`4R`P14um)o`xj^=S07MRcH-qXV9DaX;#iUO_+1!<mfKT<I5Irqyd
zXujYoBxn|LArZ(Gaa~V9v)I9T+n`#)%}<0=FS$dfV5yY*rX>nranop}P{tiehuv~6
zf?BqM`?n1EO3oMv?kdi70)W@t;i(Y5;eNgh*WPk_euHK;SJfTW-pm)!(Fi}@@;5a1
z@-1GYO8fY|v_%%kJKj@_ct78FI@k{I%SGT1@>})-AH=t(h*L0cm<JCL#i1jpA$$gn
zh==+6w7fgQU-=bDD4#MPNf_T}7T`yDJ-v<Lyy|Zx$9M(3>Bo5wIuCS`U*?V^l5avg
zmQlRfK{L@){BU~YPxGU`g579-Qvh-?yqwl`XZV=WpgGI0rH!IkzJ}iIINtv<gy;Ab
z-Ju!JFD{0M=lL1*BqZ?eG`YFJyDWrH7x{naB*G<rV<zC2`G{^v68Tt~;wSOGVKo1_
z!v8x2$yMGQ4`;6N(KJ?H=R>N&oy<R`Y5WcTb2NZA`Qb`5NeUky36)g7l6u=){7xFZ
zZ}a~ihvprAl8EFk-~TEcP2>H;!IIAJ?2TVCgO8X5M>F|*6e-T)<Kt-j%jTVF<MkeY
zg-#CL=fgUH^a1Zq=Z+ro5%XZ_5x?kn&^+cN=)h$T|IQ0_dcwD(istf#H1ohpE(x0X
z{DD!(J>}<af=|!+3FATbf^S6KMj`(<1s#j{)WN_N^K(wq`&Yv6r@7TjegZw0rTh{K
ze!Sw3JVCCEucp{?IX|KufE7Hu2T3Jw`UpT3UxD=<)_jXsLHLIMp3Vcl<>P59tD0|0
zW9mDe9}D4ozFA{%e&DBcN3MpyCZP>K@{Nt~!tsgkIR}NcyjyRyNge-VGVq`IT{wV)
zb>YG(FuzH7(E_SY!t#9}-7Jhf3gH&v7%kDAg@L=ExmCz_2kAE9<T$Xn2uFjV=_*wB
zLvy(awTGa&UC1hgA$Oq*9mnzzw)}=NPluqV6L>p>hv$Is614un?-cljXfLcFqX6^~
z*dL(kE3BsZ_#WYxIk4m>v|5WYe<6S(z5zmQ6q3Edm7#EEpD>U(1BGlY4DJ_Nc_29;
zbe;g=L18H!T?!K3bO1b9a1{K3>>;7eewYXmu2?{GSU64Vh$DjXJ5)PVIPx9rh6z!0
zy7{OuiB4C93u}Gh;W1$mP3w;fgWJOG2*INpawmjObk^deuxBcSk;3Y(z(onOPa=0p
z=tO78P7Ajp;Apfk)<M&p7~#hU$et0rh9GxVD5V%=tZ<zI)^Wl-TI`(@_zHL!FHBzm
z;d!BAG)NPK1Hlkp5N?J;cu|O=Q!JN+z#^1g7N*m}H&Mu+0nQ|0JuUC92ywgN#Z_Sd
z?Y&(SW^bVA>UH7BF*ubh^nQ=zhEPmT*-fGQQRGsDsaBXs6*4hN$BH?N&Q9JH+7+QJ
zO}Ow2+9_R_N$+Nc@UA;FGllhLSjrNX&^}1EFd+uc+!Kawhr#<o4ZWKWgv~VoJQRZa
z)9%J2;cNy9ALB8BGdY5hmV!@&M-(f{6)uGVpC@dpL@n|KpWgs{D(u~kvI1dAG0L6^
zk@&<%^<4OCC4?`8$<fd(6o!<8rAXK_1S-YCz*A5u5zaJ5*-OEhBJ!oew8<1*eI@i?
zi#nAFU1+<wT<9|kxeDRNuShC|GdMbd)i}QsG_Qq-_rSjq{M$qGt+0aLqiSIn?I^z!
z7IuUA_rkr^0DKS<$@>~1YaLqcqcCbZ0H1`-S5Q_fq|Jk{PN+7)3&&^S9mO^4g{Z+O
z+$2gLV8Tgkyd4d-S)4{I$}OT7b-K=?;WTnv#U2zk-zHuThFur&I7LZa#UHK!;3giX
zU40L+$y@+D#k4WV?GQ&A;i$LxF$Vx2G2;i=^%XnP*25l$cwjzs{KT$5!eM_gkABg8
z;x0OF94P)A0K|Ur=vpK}qHzvP1dAElVDON5V=fx#h&U<*xlqxy47f0HkOaHO#7DHx
zbzDq531Nh2r+MHBF*pO7C&euVppF#3-UN7*=;(h2-kcIYP#Ej9ST_TnMvJ<GP>m6@
zgF$mfJVl2u&x&7BbSGB4))CIciP47vI4AxZfh1n6y^6B);;brIN)XlW!F@r@IECCr
zapMcPeM#(J2$jnsI|l8WD2}m0B}shm`*x7oahJA)u8V(!!D_NNrwdx*hM4UEjhmuu
zILxJplPEBkD!!v0^p@yH{rGK>$pF_Kv3)3<zANUugPk<-;YxUvDGnTtT$Z?U7?Nz!
zycE>;#2^<Kx-Sl;jlT!t?rPNQq4=YNj!Qlg@6ZC~u^3{3PLAkKtDz_2w_Bithy;C6
zk|z$xf!%zujGn)zVtFwD1>*c|@b{S*Nx{wMVzVy5y%04N<}MVy_kpZPJWd-P#o{bF
zj#nby#V22gR&1vgZmGDPr5(;!;=z3&Efc?tg|u80_W)QS>S-ZSDSFTeq$+VVP5obs
z>^d~b8}XVE2H%QfDAZXkzM;|UohXh5{Jq%18D$^DFIvOH8ga^U06vO8(SqrdIEyxf
zYsDIGl+}q_PSP0sS^Vt_G*rD<n*g>=(pm~XIZ3D51F>1+KB8=^bgBlzZBpk_m~fGX
z($C~7-K0bPZqm93aCEyQ?+k8t>CzzJJfr|RbLA=hOiS<`(o_{xyrdC!II~ka>;d!M
z(hqB8=mUJD?G#+{l@3h?VwW_oF)F%ST1V^tJ<^q8*!7d-yOH=yYdgbkfaJabG<zkM
zb{zIe$0Wc5B`s|s@0ZrlZ2N#TU>e8{O7%YQK1lk^!+fxm*%j1>q>A655+Ze^iG<^@
z^b?)QIU<du;|HPAWeQS;NyW4mbX1y;Px}zT`FSiX9g~*Vq4vk6$cF$#NR!iG@Pzc+
zO3<8?-W-8Sq!d2_!YC<K1j{L@^#)ivE#*@;9xVk>06#`*#DFtaTJa@vaSmxK?a-W)
z*1QI3ytMfOlJin*F6xvZbz2LX3sP(v+Tx-#^CZ|VNhuWnxGXhafJRJ|o>FirN%~0J
zE?1=M9w@si6?KM*YtpF009==XzeSQPd36NfhP3r8%5F;cX*QK2IcCvOuvDou6*RY`
zK;phF4W0zmJJK-P`MxU|UO^>Is@@JS(xrA9xRxOurL*Um(r9YnENK{Z)!EWB`qb*4
z6mlMA_oW|byn7%G=naDprSYqv@<_UQ9h{FP^GGDQ(gsH`{LYg`<U%!Hn(+&gXVRY>
z3ZF|~w?x?ssfv2CVyPw^K9xwbLs0fo8b#}gGHLoM7%Z2D!~s_!ZKsXd*HYs#F!)9i
zBcb_L`ieS(YAKX@sdv(QBXaMh&!O<}qtv95f+?RQ*$mLsN_*&xOq~=bgQd^XN}71p
zONk12u}QOoqQ6d>78j7)teHyh_7;uyDC|0Gj7<UGs`>F>0Jdq?(PY6zv#tloTs3nt
z(Q0m*)33m}U9;#N%G@=b=`fjx=4vvB_s>&PLILU>no(Z@@1+SC54N3}6Nlibw`N~9
zO!#Qp<pJTVnfVP=c4<b;Lb6-a)ET%v8etho{WR+iBj>NV*bPa5CjKRAzgM$+8{qpi
z-eFJ))bz0<*{|sz0^tFTQybc0IjAY1ktRsf>HumOtocAoyF;3#v_li3X*LeI!x}f*
zbULCL-4WcOn%}MPFif+NPR1S8+^66|xMm}remtfb5Q6$1*D!PfBtla-8h{g;y<Jgu
zQu7&K)~X^kOYej8v_}5~WsYdgLh5v5G$o^8FjmuzHZ|fj-sICcjfSR{@tQUo0MBc_
zISb7M&39M8eL>^W1Z5XBcWIB{l4g<-xXYUNt3jHm$*cn)Nz<q`EM3u<M3}#-c}6|>
zHO=|$sLOTD2-=HDc4(~Kfxn?CI*R0`CWyAKQ#6Sbj84^ztOf9vCc+L&w>5WZoV=sK
zat&{VCUqj%(li;zz?QCQ(+WOiXgYTTE>lxa0i`U>stA;2YpOOv^PXn)Cj4mkHO?Vm
zd7x=SP5D^kFw@3xj%Fb}S5Gt-j>BNCW`-QXJk7_cP|er$NksBY6R`%aJ=d&6<W^Ot
z=|eGwa?LNRQHu&qYZ6v!0%#bk(zK%p*lUd^ZHd0oET?lQZ#6q<zp`2*y+9kj(=_`U
zm3XglaV&!yA2e%>0M=-lQ`qIBrvGZ>K51UiqN-M-T8gAjGp-ks&zg0QQC6=xNR!D;
z+JC9nbJE5+U}>{95L@P|Em{l3QJuAYsn^@8)l)2GoA%4GNL;j^DQfJheJq3bZrW}+
z4$y4ZiYp=Y(E2t5ji+|gw;<i2HD{sqytIDvp|Vr^2fgs#+R}k2^U*${T`phkB|1R1
zOUsRgYrC~i=|sgIZ4WxD>Zg6!1qS`KJ!zLJK>NiX5bo6uqK{1WX-gY{B~Y7`sKEQT
zU;8sn_77;kWI=jR`*b?|4$?NFuRMaaYv@$zA+0Z+5)aX)(N|T6wN{Fi9nr4*0f12L
z+CgwTT>Iw)kRH=E-;dmJZNJCxDMFj^B~(smKNtWwsa-|gYovCXA97LJP|R{1s#98D
z+E6&HO=}7-qP4Ogkc-h4e1^^$ZF~{DIIC?#BVMfbSbN~(v}?bD@SK*P1!v;5vngV5
zUfY8DsRZq+aKJBU|DZATqPBoSUzfC<>BQw_ttW*j61Cwy;aZZmF>L`mu4t>yBYRbQ
zGzccHY2SGQe_fkH%f@8whKFdj8`{@(uzORRd>A!M(Q-7pq-yi%LB6Gx#zA;nJA$_J
z?r3lOg7mJoTn|8+_P828rE8;(Lo-7=>Q6YDsWlFUFiXq2K$z{&#{U8n_p}>Q0KBg~
zN0EaE+Vgbm;E{IedU)|z>mLQS9BtpB@bHPYC%*1b<!U8-2d&D}4rvErzP3{mG@oi$
zjzYByv=y{uf2NJ0;q$q6(i`MnXlK#dw@CYM!{&%~f(^nFts`X+5HGbi-hif5tC4_s
zrTvl)`jlyZqmXyGwu}zbRcO810$-{9rv-9V+RM~3ueG~tfveUA(qQ~fyNt%D_gXuZ
zeb8=mg4;FPr*xR$qqc+&wSCg=9R;^*wXJ#rSEt?L@Bry&?VrD*_VwEGFeICF3#i$)
z=t}8}KxdteCXico6H{P!n=Z8uKo?!ED`;GG>*=_Wo9^d_z-`xg%s`#ob&~{Wdg$C<
zg2hw!cQ{mb=+4lD)mzt#){s8BjWK}x>YP{5`?pIc=D@^m-31$}y+`-zE`)x%Z_=RS
zuk#!aF9LKC^tJR}T@ZDw`*hJ11qsw0prFKlUG7F0JfLe`0)q#2!|5DKknZ>_*bUYt
zJV09<(siVnYKU$lopd{_`;{J+Bf9%#^p#ntPSFZFVY>K00FUafID;)*m)aMq$8<l@
z(Z}Pu9n?S(y1JpTdqNiw0F{%vE7VSrx}s`WiqdWMfQeJOGc|DZwC)b=okZ&-fA|}t
z3!z@`jBbno;aOd!7XY!kR6HIIRh+K756qv_wfq^R@w($9;oJHD_;gWsggTQ;x*0X#
zzO4I=7Cwo(gR_xK(nZsB@QTjZ0Uln}ZQBa&Yq~!u>~dW<(gYJXbWMK&*-f2yJ9v?z
zn@N3VsxJ8@a<_DaVZaT!t=mYeoV&W6Ly=9>^`aj(T~|dL*%>-N71%O$UH*a>S-P+x
z(7dmcN5k#|ol|Fc@lbcvx64?w<IEtm&l8=3zL?I{?fM2uo~{k;g5~R`&xB`Bb^bCK
zD9{zgf$N#>$7eu4*L_t4t{1w35zs8u-QEe~MY`ASFkY;4{u`Plx{}8zd#MYf->g*U
zOd<VOIwd_SWxDSkAt~1-IaVO8(EVEoM5WG~qUcq+Zk6!qo$m8z0N?9oQgG~pZpcdr
zYjj^xi+t3rX$-bcx;`}LsMXcdS*beREeh{^)-C%Mxq4j(0&LPhqJzs$`mrrhwppKl
z31wUKa~}ietmmH5W9*_|M2l5deUAhn-1J}kj%2$&m}a5w`Ys>fp@)7ZO(8t>XNn-)
zp+7kpiI;va4Zc45rr*OEU;WY<5bo0R8K}!{eJKOs9{q0={`S+4YX?q$eGct|2Iwcd
z!QNiIbsSCO_USXoZlM0>VkG<Z5%e))kY1wghG6}d9E6ATKZXGjqMuNR++qFf7$isZ
z=QQ{YLiJ}?qE2D@B#KuY)jv4^gW>wR7l0qryHrDXTp#rYl{l%tj6am3iqtp1i(Hic
z>IjjB5xr?K5U2I+sGEw`hku5p82!e}XrVLuyJO(+S^d3zV2jny=?axNeV<cki*x!v
zH=!(E--!;`oY&{(f;&N9J_0^n(%+<gy32a@652OWpG+SnCh5(zfpbM4Du?;2`bEoN
z)^SZA)Cb(x^#LbQn5?g?gEU3ogw{c+`ipeJ^p?IGy;`^RMNc8Tqj#ps^Ig4b5&&uX
zlM~Pu>H1+~U^hd*fL7p{`a0TU&C*Y=f-qYjhDnF&f&QzR06f$uq(SA8K9}}0A3O9%
zIs%`gccXyp6TN*sl3e|hhIy2JF^7ug>(|jz_Njg_?HCp4F>K*I(0{ocG==(;MhJ`a
zrbOV1^~){-P@?~(Im%w@dqsk}RDX%~L0{>uyJ4_Q-}VS{<@!~09HT<-DEtU%rGE4;
zAg$8R5JB@=AO8q`ztQ{71NU3K;tGWC^?y^C^MgK+)@?O<?f0<sQNK45Y@hUr41~4%
z$w|o7>D$?1_p^Q#O?m3|0pZAPHat#%p)H2ne?i6B5Yh}~TMZ)}G$d~`w4-&si{U$(
z^t&2Xyg;Fwq4PILwi_a7>f&yQqQIz!fw>K#r(vE9xt)fweL(7MxOoEJ`xqiK;f1fk
zL1zkf8KOqR?rwv6A^>{~2WXSs&rlu-6@P>J0^k9L#VctUwb$?}5H$M?ftk=bV2H;@
zY^sBXO4_FjG9*&KCD<^Z_A?I|O!NqZ7><Xbfe#yGw9-0ah^F~hsKJR2AA}jq)NLF!
zWWPjng&TrHU@*e)IU1ZN3_Tu0c+zm6Mw3WGtDO|ej537M2zkoD`@_U(gE$jx(FW7M
z@F~U+9)zmJ8vdY3N1UNi2MEs@UW@}xyrIhzxOU#~_e}^B442Z8yI?r=3fvbBuV{vO
z$xwA2)RzsP<{(Kla0;j-8Ll*}vJESS())MaFyRK+k`41|6?X%z4udxh%l|==Vwm;;
zG^vI)wE1_-(5xw3yKNXd3I^{O?tXzf-8KBv6T&ouydEYp4I?fgmu1*T8~WLXHHB!B
zdxjsIA$Q*p)CwvO4DaYcdT7v65XSMy@UI)#9veE&giek@J{pK8hHLJi$u(rtDf_2}
zI31iRF#Je+c+U)-Y2EeQP_z@c7ltKt-n-B+M-M=eVK{aD#fBF&q?Q<Dbolg@;j7VT
zk}|_jv~DXmtf5I+g(0C0R4N^Y3I8HnWvCwxn%9N}BI^6bFwX;sw+0QZOsfrkHk7?H
zG`$Sh-Wz<Wh93=sDN_E)@M11nrq+<|1YDh=<}Z|eHryNu?s`KU?Qm@}UZ?lR$#}UK
z!p+8te}LO!WG13Y&PIoUN8whZh9)a+#=t4SZ#ULb{KDN>Lg8o+<3M_@JdJIZ0>8s3
zP({6s6KUn|V;oFjVPE6$Hc;7RJXHoSb{qRr&$h?->Ij5>#&O+1=5Ji~8#DuqM>_z%
z*BCSjX7?F2j@xL`K%*DEIs1*PX{YOe@d0%P2aSzfkqa`eruAm9amW*p9x}$!L^Z_d
z!JwTF8#8Yscf@#+#*<KEQ4eT_83WEEIcjW6M<l|HDc68IW*l`3oX3r=Df%8^JV=`z
zCyXg09RQv*cH9d@r13Jns!_(HL*UyfW20F}P8&DSh#76n{}uQc<8%7N=!{V(0e{x$
zI{<)K;~)8`Q=BoWHOkHzJNm%wcw<*5RQtTqu@Fgu(OnId3&vPlTU|6RY!9+a#!*Y@
zDAQ%57j0oA8ohspr6i-hKXk4bThW%<RbwKpimn-d7a+WD+&%`}$ws%%$lWkrT?+1-
zMs;(*Q;cP607y07yMnS?##z*t+%|e0Kz;8R|NI^-ca3HLz(Sg_It+kx;|Ik59I6as
zZA;K(8mq^nFw6M$TO`@WZ|=j=J!7#yfcK44%n&{>{<|N*hsL~U<Q^GY97W?lHu}+4
zc#bin0GdyXgJ{^!HI@@go^gEua{0zJci_xZV<URT3yhZ@0QbxoH4G|_=f;|HkiIZp
zX@kN-<M)IpGM4s5?xpd@B&e1eCv`&0zA~~;;ZvEh@^>WV#+olsR$)Bc4@sqQ<XKd^
z%4k;t_u6=crj~DvQ*<DEYwURd7OIVl&%xk3V?MR^d*ehpWBkEkoEC~~jZvBb;78+$
z9bo%p^rKO{)+h!;r_T8IT5x|h{!t5jz41^9>buFrY4D3WnQ|yRw%N3gzEs#^@?}xx
zY%0dLl&Y<!rdX${wwdmHhBGdvyoT7X>EJ_n?`G;qJ=1oRW70$5-AzM>!V3>mYHQGV
znp)D?iXEmA%YpYY4XK3cPSXc!b#K#8J>aO1X$$@R3tv-ZCkS_$YH6CX+cfGT;CoD6
ziPO)tkS3-6rsWh}3oyxO6}Q)Ph+^#fOrz*XNua6J5d!>v)33DUbHJpf>DfV3eKnFG
z(@g4Uf=yr3Vc$chTRV{pF?mvb51YO^2>cOK^<q>l)a1V(xiHge`dZ|uDTxBK;imZB
zNRF90)2DLBP3!4RjWGE|BX`1dy(?ThX=>u+09&MK{YMl=nfg!zpE6ze37(!d)zIc@
zwCR`CXp0!rnF?^9F->cZ<gBSa75G@wzy2^0XPQD$iE}1d09rQQ<n{{i^QPMuL7iZF
zBZB3E=>wg8y=Xc_pJQG!b$S5YWmDVBH2=I}8cL7uRZ}wxv0O9F9|?okP5WqRm~1i*
zgljiUKht1-(}cqdc-2fVS#YPCM$sR>xn&wcvDDk92Y-Y6j;TXqcyZShkceEGshG~5
zrJIVfL7ic`PHX2(6GP#xEK^AkeJGf15-5Iu&m=ZOBi=WaQB3B6>2_!6JTzsmK<<(0
z+(+ado9@!LUpc0i7&ui=Oz&yj%{4{8g1>pD-lLJrH$7YhgHKJtW05N`CDa4{%#>yZ
z{JCie#YA41E=+-;LQ^4i!Hy!+%~l{SHaQ<dQet{SN0nciJ`RIVr6x~0b@s}1n~pk^
znWFa~S8ke9jz*|3^*aGCDoqnRg1gEzQ-?-)Z8Eoqi8rP|`q<>H$!iVDs!b`uNZy&+
zL__%Aw3@!V`(WzQ0!fX-bb;31A5G)Fg3c$?44Tr{nz|o>`*o&j+Nk(!8bMR~dee6l
zB;RD7cn2n&%(V=>*lhmx8~|I)edwH*v-#5*;I^7u{sEP3=6h~XaWRL}!p+tEiYC}@
zW}ypMwwqtjArN=7qb399J<N3!?ea9Qr;zy$bISvu@iHsu%+F4<Nb^8%bFUb%`Iv1#
zK*iUbya8;x%mQui>^6V50LdQn_Y=@ge&%}Wbp6e37C|$>ykaYwGSHkwec*nxqA|)2
zm?v;3J7`XG(9y^s^T-xx{9yC$P)HA%Cslzv#N3k}sKaK(I(Tu!yoCdIsG0u(UWA$V
z(K7O=dBT^l8*a9*2JV=76P?vRZg!!am<aPsD^yOHYbmgF(%dK>xk&T8r%;J9*V34L
z%KV}|y?>|8^B2HGwE0hp=*F0r(M<P@Ii%rpRP*vkI1_6&(Zn^*+{OjTIdlIG(2O_7
z(Wbz8voHO<o&>Xx63GSgTpr0qbIAiFm&|i$6Z^7x_B14k=IM1Xlw@vdhJ`EUASVIu
z-&J!Zog}_y&N_y|>t+XShb5bXY(U&Fzc_&3=cc(Mh0IgT7bpOcYQ9AWif@@~`ojEe
z^J3bKy<^t@3YNQOk40cfGyfccB;9PBi1y7ee^?J(rg>F5G_%YiEl;w|+G{lbyl0jr
zqwv1D2_0&BV8%=nFP`}XE!Q8J89IpY*u0BA&dxEnp~cP<^W3xG&NUz23)k|@*Jx&+
zZ+4|mA)lI;zCc-lx#kLzXXc<IaP+zP8O5Gnn0L_bP@#E+7PumFzYF;79L44_cTiYj
z-a?z_FU=B7P)g0?=##fs=I8XMmdecc+XGQ<URVOn3UfT2@2xb~(fYp1d`tw*Yx7Kc
z<lmX?H1m6JZZ`n%59VET0-(mMj78Z;^Ut&;_{rRiJ_4*Y`}KppI*0jMYh*v0H_=h;
zdb9Ey{JxtkQWh%XWLf+Na+@u;wt{AhCC?K%XUlO~_-(apreMrA%T!muT`bAvaK_a#
zcMPiSW@%2RDYjcmufkt<OVL%7d05u;hj~v+68%A-9hS()$az^DE$EEIPRj}M#@pgf
z+cZ9wZ)x7^Ynel#vt1Si9T?wj>6i}ldn|?Yj`&$h@Ha?R{+5nE!%~2y=LBf(wWN6<
zx6d-4p6)<Pb34fPTTalRcEED>G*k{+vhJgvL6(j#C=0f9b5PfG$g*@7Tnw=k(g<+a
z(t-N!BbNJJkqfoxQ=uAWktphP)MBMMb-2Z=5iA|EET$pnxa9=xibYuVO$N&e%O{!@
zp0xb@97&{QGyRfL7LGO%PgzcFfitHq338Z?wrn2jfHcO^RR+~F7C(y7oVC=_j3(By
zH3@8SmSf*Q<(y?hdjR7ty{Eya^OlIeppsx&(FcGFmg0qgU$nfUi0&mzyLbRDTME90
zYl)USD^QkXsW=9}70Uv5<gQvmO<=iZ$@8Ny;&sc}$*4@S<vx8Vc*F9N0^v6;X~Fmn
zQY`Baz>8E%IPG@cvh3Oi6SplrDV%=C;zY};yO!)9(K2b4+WjC+w=5Y5VTL8|3{)~L
zYvx0kWl22_m28WFK8JZ=nY9y!9$G>XdUmKDS*8eZ__4)ApZn)n{&0i&Czh4dA<VVB
zZw-TamcQw_%C}T50Pv}03msD{utfX`pPpF~DJJyX;zOseURbPMVX4s4s~>PhmR9uW
z6<Zz=b%~|07s_5*qUmd%QcHhVs5o9(hMWPg%rbW}*vc((T8vg$I_-t~m6mRyKvY={
z)86=N%ey+zys_;13@_eV3dew^+EUsG@OKvXQ-Hs>xE?^+2TP03fY(^s;8>sPqops6
zL!T^vQ}DIcGJtmW>nx+`ss8M+d_lFSx0q=SvB^5uhMbeN&p_07vvuT3&}^~h7-84h
z+KVCqTdgh^V0W9fmkO3#td%a{cC}uA4sJK=9r|=-yS4a70Nkx@=>roF>vCFkds?fO
zLvx4qYl=#GS?_Fs%1*0e&O4;u*0YIV^RcGUUbC;Y$vWulvL2#9#BS^4T@dcEvU%Y4
zvu=)qd4Fr)P~-xv8d~q}wH7>q%0BC9FIWn+Hv0ya_FH|Lf%AYhW-BZlv=+WbF337I
z8t`Ci9W4_MS?e63K!jNHK0xQNwFAYZj##JDpWg|!Ms$LSFsrr>Do3rJhu~AV^#cv6
z$E;oLP&sZ*9fDkhb!<~q^n~@?3Xq<(eqRH!NNd(_07O|&(enP3HU2zQPFp|GcQw)0
zufidWv3}Fk0o60s?Hf?hv(_fBp%ZKUo?_4O*7E5{&Rgqgg_~gg`yR?JSZ`66bkXW7
zAh~3HM@@3s+L0#ciPoQJeV$~^rcKW)))k|WT(vTGcyZ0Dqyx&=t<e-HO17TL1n!1)
zOc9NLH?3=%A)8{Iu?bC+YJEmQw_8?^$;jQddeND=J60z;;d0knLXrM7YuF!fE#2z5
z24xx6g><$z)0$&}`7G<h)hNrhb{~r5o;CjtaQCg>(Kl`ntW)Sy;)m9!egHhOKEOK6
zp?Ykc<A%Z<>y`xg_QYE60~5K{;-&!RS%+K)O}^Fb7qr(?tH&Gw3#=!9h23XX?C#*j
zv%1h~@`d&K2B;KTZ_y07$ohm9lf~9ArvXr69l8j)m)0~|OqN=GD0KJA8m&g+D6@__
z2}HToI~}AI*3$WKrqcSwYj{y*O)3Q9wY7C4G|(ICx3o5VYkigm(rW83v~%^&`qkI?
zecoGN)B50p_1o@nrpBsGhQW{4@$}{BC#zE$EYw=RH-Wm&T1PRk&(>@osMI^G--n}c
zldaDx6gt_ui~!AM+lexm-(nkWLeAN?UW2l&w(c~+*k)Tb5dat4>kF{tY8#&k^KLfF
zY~;4v@}uCdyX{;HBp$Y5Gl287U8MN(4qGOzhrDba=>Y7s{reEq-Zsah8Wj52dePL)
z*Vc^|rMqlfXr$h4bIpTrk1f0$IX_#MjxgbG>+v1%0k-S(Ra>C#_dwKQzip!dxdXO!
z9RWCKoBI-u2HB$MO%1mBQ6S-vEx$XOE5x=MyYQ;Rw&v8yAF=)I=zuiTRviSIFx!uE
z0FT<9JJ8(Ww!Cp*J7%k;<8jAr(b+H&VXLQoofEd6OOc$k$-Y2Yq;1k2uteDo8o+YO
z_U~MnIBmO0-E6dNoHzW9v3YJqa>n*79)Pp9lUabr+B{WcDb6-*H44w!X3^v&-qxFz
z;^%GaXwxRa7Ucz%3$|X3!F|!TmO<{4Z4`ZTb=mfk=B<ggBjaEx$;L#$iz~Kc>wvpz
zTTVUNHCs5v#jo4m_JQ4Gn`b1-ZrB2LAa~RD_cA)hm1289pJk`oT&~0KTejUt0K9D*
z7zh{d*bZy~_gz~i1;)~B!)XUN-8P&4hDL_%(k3)lrtNJLn8>nu&<<g?&GQxj_iX=A
z=XKxa<PDVvwlApK4{fvPi^NB^8u}*YvCTY_=ASvX+w?~Vp4jRlfX}s^35NMR+bH@l
zBH#9=96mj@WzyD2fh{2(mY&(>odn>yZ3^{TFKoZ3qO8zXG8;*eZF@4xifyaDhlvtf
znt)2Yw5@#wT&Zp7F>t=JMP34~%(kc#3^~ee#fMQ?VH@X!Y^7~S0otO<7ECYDYug(7
z>j-abF*LJ(Ya8<k&0THVCr9$m)~O!C_crBVc=*A#^JmztvHdX!fRDD0T~PMPcAYkF
zKHFSoB3Exa|2r&fvR`Zh3r_a8QSflH!|pQ(E^e{E`UHc{cKnqOylVDeDO|SAK0yIe
z7klAS2wm+}qmXm6hyM=1cKeeXP;s|=RKlQ#ePkZEJ?&K%sO+%64MWb$9!-12JMEry
zu+!VV^hbE%WB2ca>iXIn)6u_Oc1M~Yvb*h(w8GtEcT&L%Kl{ZQFz9dJPP2yq`>*un
z$X<I`6I6Sj{UUX<fp$+Gr2FkHX#6^0?_-DEgZ71wp&4Wk83tUiy(AedhwNV!!%~Rd
zZ#N7bwhvi?<cNJsYp8_UTRP}uK$yL4CnQJh8|Z9Vxc#94h-3DS%iz;-yN<f82>S<m
zH&57G(OT=I-Gw4zk@i>~K1JEP(gE62cH2tePTTWo^%`xTMStBY#xBqw8#rU1PNy=?
z+Q(BT6l;&0iF(G_{npYSU^-_XTnl`>{mnq+&f8=6AW5+I9*N|FeJmZmyJ$a6ONmSN
z#TsZ{w(GhhNwjNe#g=4WavL6AvG=B6&{g{}ns#5auiuUuUbi=ng85|oEZQWyVei=v
zEH~|{ESOKR2f6dZ@Z#B{b7AS0y?GGWZrlH&`rfg}(oE{E-Rlg1X?7=1<kIc4R4B`^
z5BrGb%C!5gL0OhP#P{~%c8*y3?)I@g;SQ*C?9qpy_{7dnfW3Ts&`}t8Y7b}y2Mg?H
z*Q4y2eaSnZpWB<|0{6nclVWCtc7N)aitG#MIAF0o7$c;r#NLE~xtI19Pmn9M@0kNP
zU)kN4AXjFW(K)_y`zJ?N;4AEla=~3`kEKr#s_cGV5WcqC=<xp=yO!b?Z|#fe3y5mF
zh8~M|_ILED$9wxxEu8saZ%QAv*4U@eUgAf42MSt!vQMSea;=^5Mp9>==mCSD?IQiP
zi+X!M8iO}Aa#}_msZ*m)w0F9>k&XVm#+F9CX`1icXv;?cw>FBTmDaXK<8GpAE{(?d
z!Zp`M>iH;hYt)hUE4DX!OfQ9dBR87<c{B>8{WH%-quavLjz-$m;Ph(rjR*@n8`;((
z@ov;)K5#ybTn^GVVZQ%|r0b5$y88Z(tjtll>e+kmMOHQ~bERgbHojR}soCD9_JF8>
z2*?Hj*;`ZuK?DS4qcUX6-cuB12nhV%r{7=ab?!aqea^klXWV<vxu1veXb#Z47?1t|
zwm0LC?cjVE&%6g1U&i__fci09m_YMq)KlToX+~uWKm!<`ZGzoEM)W@r31aN0-Ow3E
z?*(87Grku=A%u}Q1}>Cw^9S^WG4}lg^WhBd7FdX2q?+kWN+ctSvb0f*r)e&t88J72
z7Q@&|Po!9e<4+)QjQ0;iBc5?*KP1mG+I9mwfiX;LrE`o$XJO(zqxK_se}SQmfr&)M
zZ(pGCA|reZm`RM~l+{XRtU7@?yu{ev0L&D|uSHO|rZOrj(RrEi@=dU5jHo7bUSS-g
zFFd3(#{1Ej!LX+jo|z1FDnPF?7WBeW7NbD|pRO~$Wk5ZLv7rcV=Q5t%2$4L-y+VlO
zGyZUaGX;$AJ_RXc<mn+&#CVwkmBoyY3LtsI%E&$r7jH76+c1~67-}lJEMa`!0F6>c
z#WFZt#^|9iQ#r$hlApI38;W7Kg7MwcAe9VT3LsQ5`i{WEYDUX(h}1BIS-`Gkl&*tb
z9pgpX^50=FsOGeuG5X)Kkx@<==SGJ0S6ZwzF?Q1atC?}?GDKS#=g$GHmGSR(jJ}Q0
zx)qJ>jHD50bTB?$jiGfiexC-{#aK%z{ceVkDp7kFJz6OAGQKT`+kK4in{cL|;nNN>
zz>qBixyv|k6(WO-)}!F=F>0+82fWWHpaTL!49h35^nhVM3}+rP#5Vyt%-A~y4@VeZ
zP)+41<3}6xjWM!|VEz#!o7Be{|Hxo)f-xBg$w`JrfM4V><5?vJF~#sUftzL=TMUCU
zjHlM2(Uv($M?~zH%l@Q#^drpAcVoKknMT@BA7uv7n)Dd+g||VDGxK_(;lR8~`F2Mp
zs}t@!F{df>bb@)FD*v3ByHX)?l6hw*`dpZvAu#C5%q|6(8#9ew3a6L>HgMFPIr1_%
z59WvegNP@y{vUjGd7c+Do63s3nVHXm_%O56F$uoRUJ9-FF<+)smp@ZB7nV*l7rg?-
z0OqE>-~yRhYe9mTg%qSa!`wnih+yVt0pLQIKhtX<lsS*$JP}L-rCB1G-_R01iur0V
zxM=1lp0tpOVe%=e5z8ET5x&JSSI`<Do;j3;F`Z@F{8!J%9HlGx9CNt~JUq`FJ^+ym
z%n14nNg~skviBF62g%VS=1EGkBr^}uOXU*tavM-mm^R;{F_rm}49;9;&eVaVF`uS1
zi}ea~fPz-(%#}L<lfiVNJWD3?;PX(t${c$KB#Y@MgooM8@)}IZHD)ozM6WY{qe;wR
z&YA?5%Y2tM)OpM%3UuZ(pP&Fh0aHaA>O$t$>)?u*pZNm1m{~IeXKpav=&5zn%KVz{
z%3I9YMHpcT^ZQ6>lrsI4z%FAt(6_G2ncv?>-)&|RWv(iiXO_Z5C6h&=;40>;bQ@MP
z<z>*TVFu7Ev6lH1Wv=R&EQ<EtVaC4%QqO#XHVF;P>1vQhraLW3o0!&rDRb4#w54!w
z3v(%DAzGOebjGTUdEf!;wlhPiu&smH>kUht%+}4Y+r?bh2GY&^h7L~kFyCH*dFo~U
zO*K`0%pb)VVL$VrFH8(DyJ&58m$``xZjkwy3V!b~Z4BV<Gi|Jt5*cEyq<8BBrtlCf
zJ!D3#fHT9)HFU|3Fq0^UIm$fl3D7a-Fr|DSF-`A-8)qt=05ielI>GHpriP*lkC_oi
zATq^Vy$*wzW*Y5aeunvtJ%}x<gXY(c^<xI?9bqw&>6vfO>fR2gj<fWxP;_8zqP>+P
z%Z&;MomfS80D6Lz_&d;?SqciRoMdIMf}RWOA?++(S;Z7(c4LWGLgW<djrs7`o%LA*
z`aD>Uw1xI$9j9%*7wbbGxb4mQg+9^c!}@A5C31aPAJaAK$9i}a`u;3k87AR0t6KqQ
z0$5LNfWbi4XMaH?i1pEBkTWcg5SR#NeRLiQA*>fxK_Qe?PUmLASVy)&A)NIYMRp=s
z^}k@ek*p|shDEU^JHSP=yfUB=!#a#*wsl@CYe59OiDT{D0-1Q0iB>IVS)b5`I)U{v
z&H6dkDyr`}&-#TbWG=9xGccG$RspR^FS1&$fh4iMrfVjd71$2RORS~zS&|gi8VW|H
zva}RUyv(Yh<zE`ho-WcWthiQ4TGLriJcOkT)~iEk&17XX0qrX5RuUAmSkKU!G@F(9
z2;4Q+pYOx&b=G=%+~u$yjl=C+)@|BQ=dpg70(L$tnHEb0tp9xtltR`3RfrX_x?Y1w
zG0UC`FmAAZp*#F0EAvO7+_JKU>0m_(%ZXAVrK~7N7%XF{X@gqMdKIN!^KP>$_Q6sG
ztC`BYD_QdvL!^o|dplsNS$qD5NDXVpE9k3b)ir~wV;MCV{T)^vZD8tI!$NQkEHg#2
z8d)WB47Z8ZM`vD}S=I`w=x$+6-vryrs(lR7#<HcGq@C6A7SK9aUiSgh$(qT5Vh?L4
zr6zh=%dH@NEY3YN_Ol*PNzDMOgU+nqWgVn*qJyk|C@gl5wT8Z^aG$k#E2evhwe%}+
z4_LVgP<Y77wU$F>m=(1ZE{?D~sn%nZrM!sQ8)Mz1Gy0EMS}&L%XRUr6eG{z39{^^O
z<+~0dk6Hd$Ld~0Ejd(+3nx&<n)eI}p4q&$I@eU9>_L@rgbcDUs9z(KcFM9*79c4#6
z3Fu?&71LBmc%1#)T(ml{SJ7?g$acyDablOg1A`~nv*;z`%$`01zfZE~ybUxL_M$Q<
zxUz@L;M~~tEQp+9J5UbAojsp|iXQAkRC(yhHkAU*i#>+{XS~_7X!+{H-bg`iU$$K>
zZRGvfZ_;DSpS_9_ey7>)6v+x;?{$D{foz)(VK<0PfA%%+3|oEyqYq{?XxkUU#$AXT
zk6rl~ePQfs3SWk^b0a_^*ndl)7s>9Xn<|R!F(1&;?0xiriD3(NLNAuxb(Ow28OQ$N
z2F%B^7k>(kv+VP>z)oOy(H{65do$G>o@ZCtz^4oBCn;2z$o_<$DHl;s4!cS0)1x5C
zY&#03Tw-7If~6ET`&n2@Ww#eW@-lk^<@wXtnI%BE!d^xd6zOa(g@>&f?58Ljm&q2Z
zp>dV%K;z9~N4}2EZ1yYkoV&(Opt_ao?4?v7ox>jb6pgv;JSri|W4F@*l6>|oy15G2
zdmG?yF?-|=8gH;$e*xxAw!saJx7e$>P$*%?+CsgQ{l6k`WmfikROwRAp8XO;Z?nJh
zgklBzW+pT$*%@u{qKduzb$D3K{ucj=Ft3LFHQm&;>|=DovyQE!RplLaa2opR+1~^~
zp@F@e_OOlY9J(u-*uQ-M3(f3*D01Gy{){%Zt?W1^hSbKkKBii$cJ^s1P3vHf(&E39
z-Sjp(yVy&<gEQUihazD2u=TW@>}6{UpwP#5%Z8<Xw#Q;946qkd()2Dnha#(k?CDp~
zcaOb`o{#t0ylkKhu}!l;9<Y}L1LYz6CLb1t*}qty2igd`c^^!Svj2Pr8e?qjHpo0;
zFM1ki<Lu{KAu_=(rxo@jyKWpXkJ)>481@u<HI*4mv!A;SGQ<AUfJR$R>`^G#ae_mj
zaD?Oj2p-yV)=~ueD5vZs>>lHMoCA^LoDvT!G#ofll(KT<+@|=J6Q>KMn)6O@S}&r}
znd3VT*e5w}90upYsT85ll`~EIc{h%dex_3#PfCfnb9UMR)Pqxa7{rtF!fx30;+z#>
z^1V5K2f(}!=dBE=`*LcjO305B*+J(){5kJ-W4=yvI)k7Qz~MPz5&}8Sli-3l_cuV}
z42Mt8gka9pW{?oh{t+mIav~_I7sipsz<fAo?OAvj!AX4z6BNnu3qxNNCt(}<qB$Em
zATb;{t*m1?0yg^2a^g^oVx5=3382)|InGrI&79{<cY|Eul+40JC2}T;AbOD_q}*B(
z=fwf&Cv$LF;8x=_(&8h9v#=S1N#%S&pESG7`GWG-X`FAX;mj4z@?8)~=LGXHqzq2{
z_rT2LtXKw=tDH(&tyr@-TfTx~Hs@Pf!(8L+Xa@Fm&hq!+a1Q53S8%zUb=Bz0<M@9L
zE}x^P<NO7j<Ilj+Le7_T#HNTdKpTT%PGTD*Z*X!cq;r#V>>?CyaW168QVFMr64s@h
zZ)%}e#u=liT)CCA<9*QEock4Mt>Dx=1!pQbWzT|CaaLqQv6|ySuaz3k{=KkU%h`7V
z2J1Kj^rFAR>8B!?dX9=N`3BBxBl;RS^QjK1iNopwY38_W1!>`&rQ+aL&I8JVw{f0W
z01w+a)}}w8(ZM<MISh7k-hLkrcX4Eq7)3YdecBlGa6X_lNH6C{imdkGvV^66j%NcT
z2RPdup?;T>KM4;9Iniox_c$l3A#$J7s|Pp4c}$V|2b}lULE$0i5yfVPIqsi8WQ5ad
z<p6t>vxaiiW1OLLu=|Kp_XEf{2N`GFc%1!|8JXlnQH1j`XBXASPI0=fViePyo)oCh
zaN;O?Vaw%If!J|x(1P^{cj_1TWY6V$L*yveLfh<P+;}F2eVqFdJ@Os6W$S7G=g7TC
zk4q=+Dk^_D!R-lyzBAW_UIeb(kyebtjhjFxu1|6AQh3aryG0H?4{jADi9Na7C_LuH
zt+t1PH@AmQ8u)Nm>;j4}cN1;7{J5WffdTq+|Dde>X|C-V^aXHTzoGSKAXiUG^&qZg
z6f$SHZ&2Jbm^&B_pF+6(6w?gl-lDB|829jIaN*qa6nGKAZJ@1qB$qJ=v?y*8tuvyz
zsqN^C;c^n75X(KW9$<0Y+w|;==SJ>^+h@7&y8tDD+t5SrzjNG)=i%^qE;AV#7r1Mv
zk|>eekp|F<+yitQCUJiXhki2mOIKiD;$HGVUkcZe&R?f;-_rv0GFMy&ku+}58n}Ih
zyNK?CbZ#D9>lxh7ykH@d8%o)WtK8nTFqFle+Xr=PHg{knTCZ^f>5~Z8xvw{Y<Z#0&
zNRrEqp`}|MS4DA!eD1wVnCAkn6IJaLa*xvkxrocNgNMaj-{VlY!TsVFa5uS46sNt#
zUAY2{CEOaS3@znG)<Ca}yPm>E<=n5mp?=%S?WR*p6<isGYAU%UPeZ1PyO?~c=2o#`
zzJ?qA0YqxK4`zT}$KB9@@!sL)(P{g7E}Igv4P5RCpfz&yf}q~SUGWLHX70ed7<LO+
zKMeI&ZmtaKZQQqM58cikZG?IU*BbabOmuR;kAqAXH`M^_Zf@vNOid4WD@D|Lxo77=
zq>t+(fJi^r_Y*V@a9^ai_+4&kE!@7(y%dYaA+Gy>?>KHd1*jf!Bk1!E!`u{#zl?B`
z&Om*XyLU7E9pi>BgUBPU!b%a-aqetdV@`1YptbEJ*K-pLKIY<+GPu>aBR|8$H22MY
zAT!+F*C1lci>A<@9dC3QMsbAa5dvb*d$SZMM|meHMR1JgPRpa?yn`s$ndiW3`xSN_
zd3uUDJMj)RqVEK+M@;vhGw-b>ASZbbD3jyDTTd$*SKc{_vAglAXueMI!YKsj&Razb
zPY>SKrLg453tR;>FP_6;D0uUh$HA@-@AuoV<jeb+lC^%k{TlT7^E~}9-qSocI;$MO
zdz)_UKpuA=eQ`O6m&St38J>vN)WN(X^au{&dA$NIl$Wv^ePO)!X-wff7g}dT@a9k@
zL?q9FUi4ACS83%J&1<3^UkopwqSdjyUi#)z9M5hCJdEeDY0q<(*G(C|1YSIaX3z1g
zxFD?a&hyq%7U2S~?+`Q+c~&arxyYL=14-g3C<&R&%UcL9F7dv54t7&`VgArh<;f`q
zeVNxtA;UCYwH97n;mMXlA)UAQS6Is6)llXtlb67O$W`99SJ0Qmv(lC}n>Tt3eb#Hd
z{Lf+OI`5TS=;!e6eu;tR@-nFgA&=MQ3z>YLU^V&*c<I|f3VAahp|OaUJqom9-XCj#
zeS=q1i@uw@T~v;Ei<kO6OqB3esDV<-yRr`CHZR~0xLv_>eggI?d9$eKr^?FHML@Bd
z_Ydu9Yj|Z;t6$4Ypm1{?Z#x6z4$p!1YW2J(DxhlMO;KfdBQJ=Kb2jn*rnqY}&zEYd
zTX^fJ2)mWXRsy??_lpAR?Y!KT=<DF+(4(P~7fQ#Sx_E!3K(Cu;T}0u~9^L|qx%cv3
zp=DAZFW(#U+|Sb;M&AH$53O|X@^01xZII`A8rb)E2M$8vK5zFfcrnEL_$ovm@H}^*
z?;+2b&d?6?YU#Qd;eATpkMd4!1=twx(wBgK#5+N?k>k8l>z^3!1aHl|z@FrNKw;F!
zyxCG{Oz}o&M=;Gxq`1NiFYJ4u+49vC#Iob>q&MXe{)LZ#X3tNiJmpb-*w5gO@ymC@
zi{pIW^H6Z$*Gkdn$d~>K51sfQ!~*ODKZlCYocWJ0Q_$`te=r@a3%^$Y4OhNHJj}cC
zWmHLfiXU+d#GT*$E&4q8UAa*3<d@I^DKGx`ub2dH{;MW9<HL`=1LDgsrhD6uzhEW$
z{Q2IFP(RJ*QMp?Hzk3V%0{L?`feYfd+fw}V4FB<Vhz9dNrTuaUzo!XYDF5dKpoQ_>
zC=?ye-)w}z2!2)_L?ZdWeT~6H@yA<$9nC-cUpR%YqPr@V|HW*OIDSJI1`*FcPFs+(
z{9KCFC-5KB4SSA%@iolTd43u~;MRE;_%l@Vl*qqAVW(vNPbtv9#80ETu@wI18jw_e
z#9fG7=Ku92`qKELbjMxcm$hOp)A`M=z|P=*W&z3Mf6@(dmEX4>ZfEiLUx4{+zJM0P
z*Z7ST;Jwawqug2!U(5lq=JMMp1dzvXo(~iG{1Mt|7Vs61K??Z`mx2`W!w#dbnEz%X
z{Jz0g{sHWp{C8<3b&KCfagY-JU%$h(QvSPKaAo{z+J2Vv57E~2HvceHAXV^}P!V<|
zzn0=QRs5=#V7}VQ@25+?hQI$OjJ}qytOsZv-$F0PJN)0Nh^C(Z1l>*z{C^Ta8u>#!
zU^nskZ(*R#d^=B|weXKq0Hc+E`WP&=@mW+m+s;?7fKMI#vRsf({+&0W*Tt_Ygh)64
z*B=1g!?$Kq`lOfdd>1l({2wXo)X#sK_B;dpUnp*Lm%p6yn}htaF_3%w_vmiC&!0ti
z`VfEg9zY-P|9l(%KIHq;<vh&)M-IIa{t;3b<@dy(Z;T%j1w)VcE0X~|&VPFk$OPZp
z>JK`}KSu$w$NWSan4jXCjskm{zi=hSJHz)X0*tNT4=;e)369c#$sQ4iXc2BNcy$T%
zjtah`DC#l63rQfy1>8j#i-X`~4v3@R+#n{%N#HjO%oBna{{`nPNYX;@q+t39ihsHY
zo_rT*u7ZoS6LAxaP-Va=L5V+P+y&?N!Mukcs|3VTF#8+$<RciN1hB8bm7cwR0;4|~
z{RM+1FmYONn6iigg77$~2MX@V;ct+Dp@-cw0=*c62o{{6WMqh7Lm$OoLIpmQTnH1y
zcL6P2&_#LV2*HY*kckwmH32P3kVb30Xu&QD+QkS?9s+i(;2R2a#|i4Y;dZ<rXB)^_
zLFg_xlOSlM|FAtL_#zyWa9%J&%c={4f8PO0qQIA)ofienR638GB>0fd1|<tT7Qp>W
z0`*aVrU=e&heoPkS2P+g3qt0BOB3`6fqg~r!7yOb1%;IU&JYw)I5Jc44+S@`3jC=t
zOThXbdf9>x`vG=M@D0@gUl;sjgflsU+(mFLSKvmWJ8Pam)&=Z*LHOrj3j{v<AX6yV
zbPkq^1W!}=r&w_EGZ?%f*hQhRn*wjDQ@tgKrbmB?;E9vyD;0DcfQd4}23nn!3+~br
z@wQ<0PY|gPJogejtQ36e1D~n{=})1rTEL|RQH@pLLa+T=fr=Iib%HmNVE2w7YY|M;
z3sz9YWP_lc&V4ru7_>`i5_C{-vRU9w5yTe3Psd=lRq)sEAZ-F)O0BdDo~5e%4nYUq
z{+$AW90t1tS1CK)Eg0`bV~^nXzd(8g)^OT@^$B=XY27b4_YtrM1coo+%w54Z*U&d8
z2&F>>_XNwAU@-Ru=1UM65)AA`;{$=C9bg^`+#bUGupsMejAcaNM@x}M0uHS+#sw+2
zK_&zTxoDgeL`A~2#{y@XwJE`eR$DkVEqIdh;WL8KDiB*?Y8C9-2`lM4c}Ik=_`-y}
zu#29yM}>XK;EoAnLLqWo*h=*y4noHv_~a<e|L;~4y3@M#gzy06@0^8RJfNHuT3>~_
zi%=H;1y|vw&mrO_bWWo9%PC<@3%qa_e(VbOJ%su^4AfJYWJaHtu$SJZ-ol6#;CzI_
zRCwqsEWZp;KcOWbeg48WS{a-czDMEl0O5vTArdIej749NaK~PdGr};c?+F%8(mEkT
zn6n11g$hsHpnn_)6Mj1fY`E|hGe9GRmJ{G2g<ka7iW1sU>>yhB6V*z^2upk6eys3y
zs)~#g{#ghvUO4;`Oq>-ydliid(8EB_33XHjc3v1u>x2u!k=H>Ih1VBh)-DP^hyrGk
zP|l+FU$Str1rA>l`sAZEML6~+29qjWPhar3Ec}VKV`;(+N|;;`vc5-Ox-f4O>}Ck(
zji4`6*s2G)DqQ*i3R%Kg3QS(MaC;IAUK4(_0npcl8)-3{BfK~T^SQ!#>oJx*;ZJix
ztogz*3Vsy`1sMP>6vok>sYp2eJ4mtc1Nw;U4WZy)DBcuuDDrqqSbYVcCBm3oaHYZ>
zl;|uIE=&blxp3oW0J|-8qfcj42s0>ZTq%626be<stF;iR7Rq*@uSU4xZ}@b_DlDSc
zcfD}W?+|Seim!lc6t3?<XOl2~J4mze@EwpAp*;<zRoM6u47Lg1p~qdj(1Si<(IGs(
z5F(wz-SqJ55|+@7*Db828SN2fB>=Nmc=T&D_6ffWghIdYXcA_0KxkdL3@~?vpKO3{
zgTg49y?es1zQH`-7w$O#nIYlfXQBT<_)jNHJQOaVXXvo-m^=DLgsf@wjSBfK@M%mq
zL(la`LYH-zu5sbPmw`DUy!1CPCx!788+|M^B*5O3@YQ$W%(QTam0pK4!cxj-+lt~T
z5NId*j!xqp5gnzfS9{SU<?4=#{uTh{n1~$>?zrfMK@bO#8wI}{MVu@sIEnJ<gIy;?
zUKD6@7PV3^^`z(r%DB6TQs}AWD(YfF#7$H)1AkA6#>OcB;4W&U*QkdmCK|1tqEse`
zm&lFc@!le@ztQI-@>v28eMLibq{2^hpb}{QqAm1`o)$eB4NC!{TrY5eq5%3#MUdzb
zo$oj!y8R9e28)gsp)o}C$1oa0MSl;13lqKla2D>ra8Uy#N+U#P!eKX3RQEOp6D9hL
zK3Nwn+DN4`F{1zNhGML!S%tnh(GVLx#fu6kYIRn0iXPSpA~mf>&xy9Y3hun<@ok7)
z5dHZNMxQ7W*<zd*MJ?o7lIVqGj3rsL^&sW{E{R^^K_*3XX+6A16>Xpr_RAuT4J@UJ
z_*6=fA!^zM#Y~YC#WSvo4!jSavP7Ch=w*vOz74zAM42TZ*F{fKsy#=v`(OB*D|&}s
zpLrs;zX6snT9^#i3Ph2#4lES?_92M1NMsWO6UCxfA@pyE`ilU1Q#3^1^SC7{qToo0
z$dRIhrJ{*j@S;pK?f?_zB6AG<y)CMyBHs!TmTI`wM0ul7s1p6!0E5+{tMpv05y{?#
zUae^R5$M&44p3(Ej;MDVB<roBD|YB?5EVB8rctDcL1&XlO+|anB84ktT10+tL8Mi*
zZ5AAE6G=D2nRZdgC`gCs`yrU<6g5&XwoBBI124Ko?`A-uN908dsa{e2eu(smw$oQv
z`b8S5LmUuoNP&gBBJ1@Z0Xiru3WeQ!qC+<^?E9ij`jp0y=$|_<@j&F`0_=yP=})0J
zEIR20ZbbAt#iB+<8y^8?O!PUuBp!*Z&!KNzbi*6mglOafFegQwQD}TDN}mm|Dbd5n
zfSwk;Ye3(OsMI=w5!#CXrQoQYI58jQkBG79#*HUtya(>6cxpa8JSI-3Eb(!1*Fp@&
zLA+}tL>$F8C?M`6{yiHePKX_8N}R<{?}pw<@kLruxQO5D1#uM@(p$+*tfcQspAv7Q
zXP~>d;Ria%;vrso8?2{Twj3~C;zzU$^%nEIV97_!nFkZT;&<CICO@%o5dQj$U!$kj
zY4K0{p%)<DL?5C$BespltOtwd2SYDJJVnPzL&fht2ZLc^ml5=ZixU~pix5Zbz$8S9
zpPoncXHnuzAIL<DM=rxejMz+H#)uV54#HBLSeFkjUi|A~IC@t6<P=DPct0)c&WZm?
zgTLp+&vf9YxFGhX{a>P3`4&(vigPIbk|ge=Kt!^bMcJ22;^h<pOcB39Z{bw&@-n*r
zE{j)Y!?!f?oEM;RMa&WbJ6-J44@(*1owT9J6su?te^vb9d^nRO?s*xOvc>;WZsVGG
z3GKSCi>vKnH%GkgG1PO#>*Jx9Csz1EBwzf+7XT{|SN{o-Lb3j1^c9IeqU+dNEZ$-U
z_6_j`%9-61FT4(oTjI`4kP`7>0TfHc!{q=i6Cbz=jdF1b<#}$4BTLX%A$GNcGnL}H
z5R9-&yqYpX)#9QlSgH~4?tw_HxQf03S|@g#1<X5QCdFjy#rto7Yp{x==}1(gc$n7Y
zO=9bpz-|_Ard@Z7xI7(bt>O}LxJ{f$*Hyc?n_^KN;=m7Kw^MwCYI?fFt^P3IEiMj)
zdXKoW0SdihQ9I1{iN9D6g?{ndnC^K4V%Y*f-xa?=+rUAw)%ODo?Vk9xTuj1!@tz;h
zIwZbDXW}1-Kc5AShvGRYaDQ05S`8B;;zvS|QSqmR=o=F^QFY`aF^dh?#>M?TXq*t+
zegvN;#lJoel*i)v^dz1V^C>lHE7|!Q%-czV-h*pLBnzykVBTJ`m7-TiCA;rI^qAxa
z+Ke8T6jSNFgJdqnBOE1*X<y<b`J7@xCnWDSzzb)|yb_o{DaoS2xJdG;R@hat^b@GN
zNwToKns-VPOf_xplI8x8^pKcn1?4FjqKKoHBrJ^%a(YYrDFWdm`Q}}~_)5OlL(xyN
zmf~do67?Po?X=|JYtRUgbWx}zQ1VhdV1gw3oX~ehvW@C}f+aVp1|me#xg33=68$Df
zhDnyuJrXWiLmoy*=DZB(NXhOuAsHoUaHsfZv?TX!urZQRdX2_P5|S{&IEf7{@Z%**
zuAuL%<XSx}B}f*~W9yt`4J8%NOY-Ox!v)Fk7U(5P?w0}kqU7Wj^d(8Y_5ewiR4;=U
zmm~wU%TJN)3Wa2<<Oemza#<3;iSEBN$(Mfv=8B}o2O8;;PRfF0NdDao^O=%G8Z=&&
z*zdz6W=YnZ2TZo)_jvSOlboX~>AK``B@}Wb!{Oj^B?;F7mM0lM3B7!YF%6aqB##b*
zE0maT0i{T?C=^_=WaT>mv)+&hUIf}r$pU&_-IBaR+rSdZmP{y?N_MHCQ6~957$(Xk
zk1HT@TVgMTNQFd8nVm`rZ#mGaBoCHi^wpB*=>o2i6lB7gTFLdfP^gpqQwoJUl7smG
ztCw6Bqp?9UMQ`CotE7lZOq(P&m(kfQ**5^YZIUF~)3!^t)2gLI^6h=-cS=@M+O$hj
zO_yx9<ZH^9_ekRYg+i~Sno1Y@BsK-`qF>UU3xxqmBrTioN;X%ZZ&0$z69(@|)*B&m
zU$T*+I71R^IxRdONRBtci-(dOi!r8Q$zCPMh-6U|430{e@gQRo)4%Zhk>mwB*)%SB
zwiyZ&5>^dhCM6O&F#A|CJq?3XlBKW0!)ZzDM}VG@sAs_0N@esN1Uu<kdq5wN4p3E!
zz4Wm4HLypeJT_#GNe8viI4=F*1%Nt8KY0<HqqM#SeNNH>dUl_X-k$^aou$W|A#ze$
z%tW7y)Q46buF@~dAmS!{*$i?@x}Wxx?$U9}f_O-$Phk=~rC05N=_QR#1M!x63uyo6
zBaQqUpuW;1dd&JsooNZ>FWpR!yVKH-D4h@>O{KkIpfqs|B0*C2O&B~QeefATgQaC2
zXbh1q7Q&}c>5FvGC`{^0Yk_d-a@uuANG%lYj+8!0cX*W4F9<$GOaBR>gPbwa-L!Rz
zl|FMFCgP;Gs1Pe&`raJO&{=6%DM*6!uoL>uNrx%GbzU0$7Pt#ik7Br;DBVVJ^^4N0
zA7D&L(ml>lNS1!O56)bY`XoUlMOsB`yj1D@1L(UfT};ugH0hZk%0FC@8VA9qOaGv4
zWQKG>3%E?FT|CgPO5G_uo+Uj&>8)((Gml~Enlxk;U~;9W{4nf1=|(#5kS|@F4N@TO
z48&Lpr6WsVut?fm49sGwkm@;ZNEwCbyD3d#z_nXa2WJ?vmPof#`9P^ONCf>dY5E;Z
zO}X@?J1}uux|go23aJ-Gk1M7Alx(h&N+*C_EiL#Bq()luAw+7W1CJn5CymPi*d6JG
zK7iFr8|Whx4bp_?;C7>Q4i9}z(ruK@YnE33i@p}C^blRat<n|rt-3bpoKg(5U0O(A
z#OaV)Hi2|X7ts^7OZw6tkZx%*ttxw@Mdcv9(xMuWKB<Iu-Tl%_v^*M+>b^qbUFor{
z;0C3`dboB^x;PeK_oYF!QXP_3b%T2#wH_-4=tJpZDmfXJx_iOJ5ovWX&_<=tUBW2F
zq+ij3=#li*W{`2|QhHiWNNs4{J1I3BgTiB}Sp!Q`(#qEXIxUT&^MW(dO$LbA%GRm@
zZ717P3+{;Q6y1OJvIxrb9hIr9J3x=gB(&>3F5^+zfrD)N5BzG5vi6<mbCPvzfZY=^
zPpY+amc2r|?vt`_DIe`3yZIK-TxCtPG<K7<(@yb}?07LaciAqAAb7~qDR$;5Th<0l
zFIhSrqw|(c`Qcagk)_<A{GYGv*OPG3Pd4`seiDC~&lP~4maW|mjR2V~E&c;#XNMpX
zBtuXVH=eA|2_#sisDh;sSrVP{3YDc(2p~-M>3)!K*_RIJi;{i#8&INUvjtF(k-b7m
zg;?1q6)+noJIJE=OT288Eo9Eh9#C>VL3WScyXRzY`$OZrtYJSiF32kAQJ5(En)dJ)
zWi=TXT9V9<D)EzLpV1Qcl5E~`7)+7<a2zP9vO<bnT$V*sSTIc%K=1i0ve6&WmoEE_
z9)9?c6td~od6_bf0Nz}cmC{--OEySBl5ClrGI!Txq5DCu%dXsmVvg)Sl~Co%B6HwH
zp6q8T_|BKDro%D?vR7-+S18+X1eS_qVLX5p%hnx&-VK=xt-x-|Hs?d(mTYz*xDr`A
zEfuY$vWEwtQ6}3#b6GCiH5&$R%dV0}g-m<~T&3(*6hy0JJNn>gwQTV`^wr4zzJyWK
z%I11tpmj3Uv#@kWw&q9l)ys_iP-u{Cq+6v?wvY#uCRyw=P;Zu<>&1+=$lmLNLaSA_
zi7Ln1WU;k?X_wWxL8e3I^b_<uWu>%T=#tqOq2DcYdmfJV$hPdnKzn6glw;_V{nHB*
z{j%@p18qPyM!TH5vKo5(56UV&gfsVK8JXz2FROS37KUV1-+(-j9pr;Nlv!Vy1^r=}
zX9viL?9BxrqcSPoGGns&TQDV$WXdmqHZI#!3784lbx*i9Df3Bz{$rVy^5|2t*UrMy
zw5;S+kQv!)&!N#)KCls-o&3NQ)Q`w-Q00idykR-WQTer%AjjnS))=5U%J0^}l9PM~
z<-t$L53$kcEO*}xa#Ef=7Xx*XFV=!{mH$O$Fm7@`y1Gxvw~ArHU7nN-5fAwr!QedQ
z&!?f!OCC7~UU<tpjsVj~KJf$m^_3smhCV;}{Xd}KFK^b+`|q@TA_JfS@`#^70_Cn$
zffXcIh6C-4Jo_13Nx^a%MOs7THMFA$m0ubKXqepm1r);NS{=9u`DMy(N6LFAfEgwK
zggyZfEk95L5+hH|17@sz^Kyv9$)jnL6fgh$2l|lDS$UNQoJx@IiiU}E@;y}dc3wWW
z65Iv(hX*l=MEOgDuzOK{-5=AIB>#>o1d`>mPvaN4Bu}7NV~X5kHMmr{E)wdO<)<g0
zkS6zA0`7|3jSd*5%kh^ixbfs`kAlmT&pAc^33yfhF$Ku7<c0L2&z4_&0GVrY`xnr7
zT|Pe!`Z@9ry4G{$ODQaoCwHdm<b1iV5Pb#m+H){pD37Mv?jpI>6WGP_HB^#*L%!})
z4D_Zv=PmTzlHcY)p+r7P-yA5F8}7o8wM<@3v8-~rTPP;#ww(0}OjO9@o`=CodB+g+
ztK@&tOR-wsZ-Av5xm_L<Yvr6HP^gptI2)Gk$P1UCv0gqwx!VT0f?lzW@-rL3HOWiq
zG(@x9?-P&~`6RstTjh6YNzi7M-`|0GZkH=AqP0UFMdzkE<pUuw-z6`gAXK;f%eg@7
zlRNH&NWXlOA4CS^i9xV?S6<o)ZcrXm3z2*BtXAmVmkSiY9+Lky4ucQm3AD9*C_jD(
z>cetB7wC=1zcqpzm0OLpdLNVLEWivslCz({)QrpDd<DavkQdUrXj0C;j>gCGS)Rb2
zl83(tg=x8l_R=%*X{tH4Rfs7rV5e9`3G5?^K@}A26^XPiI;v38R{EG?@-H}ZT;W9P
zA_s-96@8A1Wa~!&by7UO401xz#zLpFV)G%me^T)+Wg%S@uZ^S6RblMLDBKkN2ADXd
z*hZTbcf~W`Lcv4v-VS)-so3%kEO{vwgrm<}!3u}Ek7DgYsQW64D7EOP@EeDMzv9;n
zcz9azi4(aIpm>p1{ecP#trde5-&KJ-qnLROT(F{k5@;a`J9=z|D)jE~B23XYhQ@G3
zN<3g96sfc)jZ`?(GAByGJcGVy#d11P8KcOd=t8U_(*azZ;s?4p;uX))oqAT0K8x<Z
z1jQQ^_c^CH<P5v#75C`i(gnrRZy=MXc&`cA7Zu5!FrTDw`VQ_VD}JTQ%S(#ys7@h8
zQM?-psS5e4z`m^Lqzauh#ojqkxT0vHWMsOckut#<ilG5aUZ&z4o!GmoU}95fotLFB
z(NW}V#UiRhxu!Ts)%MpF_DA7Uj^d&Y*trT`E70;3&$(j~^A+y2J1S7ryFju~5!M3r
zBE^XV;BG4Pb>MC(-k`gpL=o{E6iO9!8kjFr{C*r3$`wzsA#z)><QFJdD-^GLL8el%
z?!U;T;xCH7R4We6g-nei{USWARV-w|V4dQ(VZhu`I0U1yUeQA#^ah1$2%wFM{aY}!
zCdFnt+TN^~zYwHFaquSeS{2F<F_tz(&ac31SNu!+s18L$KJ+@RiZ<Hlb}3F!1xUAI
z?R&uPQCR6y4ZR9EEo%D|zx9IjD?+}6{(xdO%4X-?RpiswbWp*kI=y>}%8gLJub9{Y
zGNkaQV8H{$%ot2OR7|kJ4J(rAu;_?FLs!?R!qWu3F@<$vJ7gXyzNVtKaYZr(+b0y=
zm5`ZK1fGP<V}&Rb&P*xXCBU9m9QYX1HKWk%1e&e#HU)L;l+_d@Jfa+?<+{D{3PpI2
zDwoq+>6o&S7Cpz6uTx!xgYxe~aNAMoln7`i<quYRFPu;&QToJLS^q1zlgdj6pzor5
zlHSR#O3qvmH|10T^iL_(j<Dpe{Hh-2J(O!{r|GFw{Fkaz?xLrbxAHTJ(E2C?Ghp6V
zd6-s{e#-REK>U?<XVG_B=}N1s0Of;9%0C1uPi;nLkaATNyf~xeQE_Lma=s9KA<FPp
zaG}a;QxFMLJ{t=Xu6&LMOA$){pFtv(MU=#hQu@%#I9gdsE9@BMI7Odgl@DnW;*_s@
zV!ZLn5vl`AQZCv9lB~=;M)lX1ls`4YQkpWCvJzL6E9qKKS2}+O&@B8dA0|Ir+5F$l
zp)5ZP6E~Dc!eIB7^4l*UQlflz8hWM5aJst7l<(5-Q?4whV`jINkzYWeLirSJr7M*;
zC&5)IyDmYpMwzpf)}OV?6CRk$I^|v38sAZRQfWcGvX_FY4a!BO5N%QhpMs@k<ttQf
z+oD_$fGKHJ?x=;OHf0#af;*H`5m4w<#!`&3OPS&Tux{n2TqyJ?eGfyuSGk2IuTLqn
zg~EVxkQUL_yUJ7lMFN#pZ*<;MhA&6!eWfF1R)>^zRK)N=*+YxzhstESl7^KsiW840
zF9v}dRpwJg#h7x34vs!j8U*lZT>0E-%;<!&>n(7Pm3bmSPbn9fL8g_gc1X@B+xviG
zYgHZQ0>)0Yl>!m=D&ckbeN^R6d)i~FI67v1TxItoh=c0WZh$(e46kFLCsYx%-gZ{4
z{T|#&Rdx=Di%ReY)Lm6uXw~kf`i5dU?y5Y>5qPK^ufUL}s`(Q@d#NI*lF3_T9c%{m
zQMFTw#9!q@rOT&Pp|t4;P-W1C7^q6viM}A!EGj2Eqgws|Bvh3`C0k)Cy$T}XDh5^N
zMXBaI0WYFeJUS|iFSfdY#H%*vz~EVxYB$U$sBTdZ>VoPX?Q;`V^;X(eT~vLMgU(B;
z_o<3JMYVMlGO4PZrQoipR7Dt5x+;hcQ)Q^?4gxJpb@?LfW~&yw1Mjb?R*wSZy6Vpe
z7|c;ItI(IL649q<3RLr{BCt^9k^rtqbtnXV#VQ-h5!_I@{%nQ*P1W8f;Z3P(6ICsh
zsaz-yS+3emiLl$M@A)uap?Z}HIx1C<C~jM$T1IsawW?bbsI5~mX?5118hZg?jjCp<
zrfyQDQ3Xe<>Yt@B*rxKKU_rYojxzNfsyV5!(5ZTM7v=xDREz1QI;gTlp!J@r?=ocW
zt7g-)Y)I8Yg`W>pPtfD;q3YEhpbe|e#zJ94Rqc+xQPqZzF<oP-8-Y-Nq}uvA?2fCP
zO%Rz-8P34pNtH7TV2@STC}=&UnoT8Y)2cb^=>ITgRO@WfYO9{v4-<B3Nf$bgsK2J=
zhP}Fms&0>}w^5zYF?CKE%pX^8q70>j`h~L?lcSpd5O$r^Pj5rt3H57{7`?OlHf^v^
zs@FHeyo=h|8PKlk?PS4CeRU}mJk(dip>Fk5E9q(NrQS`MZ*TQ^3MlxfJuA@Zt6onj
zEI+k~;#~gfuouyHTKze#3WL-uGvVkN^-4;H1gkY^@GwN}kb=HY^$V1;4pW~y2QR|a
zZIpe9P^;->9I1|@dn8KzkiH`nZB;)@1<5h$qNg$5SoOMo=*OuKMPf?h)xPvLO;GnN
zfyO!Yd4G`e>I@1bUQn;N1?)uinnZ|PRND=p@sfHeRSBo4bEteYRed1>D3{f%pM|9~
z^(bxnuc(J8QIf9yc_lo|P+Jeu!ZTC-QV8bcs=Av}4O!}!p94&``c*o=drd8P878i)
zpP-vMNBu?sNS^vKrJxGcE)?-BQdiN-typb$3ZOUCo}o~<sb*aQcS}7T1CbK-=LLW+
zRXfsGQp?l}-UKOE7g_0Td|O>s4E+lAY}!Ous()32RH;8W22!mS(O*H-sVC3FnLFwc
zDtxI|7gLO~K^@Qw6OHQHdidL-ey$5#s~Ue-jZ0n~If8+<tNVkY-k~;AwSA}BZvjY`
z`r9l>cB_Yevtmkn)T?PD)vI>A2-2tC(1*r;b?!9CfSOSSn7isf>G?XSR-0gVNNwf9
znPGLoe`|Sl;qTBJRUf^IzA^Qld?-9p_Z`LrjjLN$!P12K`j_aNRIBI&+ha910F6`X
zHQVX^H?3Y$h}Ic(Hw!<|5zQZ8f!J&IpMb%m8at|}IHqCIiO%Di1C+dV(Cn>%c}Gow
z2SA-PFVd#)gyuLsyqq<M<Z%0>CUOlp7ftmwsGrg-`4AS|H6I2+&qK3|N;f<;i%^1S
zo#&-#^#Z83CW)dWewtsNhFyORo8HN%HA}w%3DAr^0$QLZ-w|Ap#^HCE2+;&m=pj_I
z{}*@>rpcp_aJc5JY#5BtwB><|)C{=-GfH!oD$b%cz9uNdXu98qLafFT3NUM&=8-GL
z8?U)U=O2<Zzifs~vZj>6&6hNPQanCI6Gn#<QZ={#1=?lJvsA2+rism>>sfO&8zSkN
z*Xe6U8JfR0f@Es$tOvQO`H&U?SsEuNaM_xjZIHaC*+*Bxb<NZPfaO><0c@b<Y9dd<
zM4qOG&OqmDgv&7A0?o%1|18why$ef4nm1{aRIIs2`_&toPu2qFrpE6pNZ!(1q#D2y
zjnh{cTB#;xFEGnAueqbIT=N<|P;YBm=)qW_*-{U^N=-~4Mqj0|ZhRgCt=802^+Jti
zgahna&1x+?t<x-^DE%GH?{vf0Yqn4zzd^I{2arb1&i_HLNi*36(yWnAz<i5lfR-Dr
zn)Kta)TZgqLSMUP<@?||G{<N+*r{Pq3aLvIa}M^pH9M`7pgo!wsD7<iv#S_fpXSR=
zaKB%pItl#&jsJJhxU2byLac+D%_4C3G)Yvha9^|X6hwwJLaJwepjlE0@=&9r4fe36
zmIH+mO~^wuj%o_%<0@ks3Dt-_(!|DtjB7r-WrgU3<|N(JQ<^(tAk!NDVhm<RbBA`S
zN3{L)pt9GVr=qr_+H-v%$Fx7TLgcvCogRJ;+WfshbJUKpFbF5@$XpEcgf?^?B%QUK
z6%aY8U9|xUF4`a7hXq%ygf?Jq+8>4V{yU}3l0np6+w>`jht{_m6YQz2T?`m6t;-h}
zudnt6O2hkUpSFij{@TBv!_ZD^E8-v-plyqUi9l`tL6{HH+RjGf87+^>JA$<$+CqeA
z7db;cR6Dd1U}4%#wEPX%2HH{lB|@vCY(}KEK!MIEtsO0RqqRTE02-%VO6BhH+7x;&
zpVgX@;ZuTk{+k%ZIc?QLh@98P*ud@u?HqcaBx+xK59Tjw-3~w`Nqdbp6v^7(ilKf<
z>-j0T6zyd?NRz4!nuetHvUbBLd`r_#(Msxy)`w;`T{}fl`V6h88rYfImf7&>s@7v8
z29u?YptotZHi=?0*R%x%AlJ2PJmFf7HYXo?x!SPJFqo%(mtOSw+HDjiFVOZ-P^M6O
z;|rh^X}|G-_r+H24?CcLL!0LU^Eb7Abc+9$wu1KXC0hJ{Gj1pCE?Sb8Y0K@wm23C-
zLh-hCEgcfC&>A~nuu@yO5DHb=vzH-Ktu@So-5Tw|B_OrhZzwcWr(Nd?lsnp~KVYw3
zyR!m%4O;8xbAZ;Ub)`&6lQxe+Q_WhhdZ4vvBWYRJs<o#mLz`CmB_^R=yW(X`SBJK8
zCqz26-+YK4tw%dfw|}qJAs8n5w3n&2yI;#%2yQ?-_#L>r+QjovAJm?wrTjhZPgL=I
zUn{awLU~B*K?|w}+T<f}_@VX|6WGJrWO_o4Xd|d*YgAk23lGP%Z`px+q)jh_PvhDq
z+9phBf8GVXNo{@;xX0RS<KU*WRV5Ia*8cP|pl7sxba=#8cY}&?>~s%~V-QDl*+Evc
z+UwqY0|t-ktajjz>Bh_9_i>%^EMOdTN{Zk+>h=v|5}kDQjWB;gx7`mg&bmIj?@#J9
zbpN>M^eX}Cs{5NhpyH-mPdl$uy50ML;;!3jz*szVS$84nsk@$lMlapr|55(WTQ@m`
zRv+Cjv!Up#YhMQwe!7kzIODH-k<tmLb$&*e571o=Kx3e8`2}DH=~}2T>5R@f6C_x-
z;7gbf(G6z7-%#DBKZ1nm$|;>4uG>lRh$!8>2v~^Lv44X?jPAo|T7SmsR&D?rr(4B^
zOuUXs8ML!H{VIqi=ssQp?wqcK&Xu0mtq6kT1zi(mSQ2&5zX64dx~Lp9Cg~Uy8BW$k
zUWXT#bS4|jXo@cNBlM-}_S2VBF6&<T27PHd|0ke#MfU_vtTkQd&cO&Xbhjg6FjMz3
z9W=hG`{8fc&C(UnLOolzTM2Sa$8m+^b=_%7r|0O_(3!VfUGg9#^K^=IH0JAWP=u*K
z_p>ih3U%AIz+jQ?5CTo}iggM~l-$rQo&`fUb%re<x2!sEdZ3r+_AP@(scy?2aAmq)
zBVfvP%6xFQb=%*A-3nch5~HZp<#Nzir7L_Iq*`}?f)q8ni9{&W>h@AaV4ZH@Ybe~&
z{n-studAU;r$Kkf2^Jc4=2w8yq#H^DY1UZ<bf}_5H{lJ^s(X102GgO7poLhc&g={m
zUAop5c-pP&Xb0D$n?s*`=+%8q8QDHv9Mzii>&hxX26VUkF(r3(izy#AsB@#8@jV@v
ziZ$-*OxSJA8`90C1oi{n;*SCLQ1`Bt?xSJdwQ#sNqVu6@#Zg@wJtD?*Q??+FbffEF
za9p?V6OaiV^EJRs>g*iAJ=PtfO7AJ1@6$k;);*$<tr?v=t+H(Ot9USBr}t@x`6K!a
zs`#|m+iip1QN4O4$T9sdzgZ!ATwg_TG6((I^?-5Imj^-7N$+|ZeJAv67fgw>en|`(
zPwJgk!Muy!h5}Tsdgd-Dxas*h81E@P?@yR;*Dp$fPagU%dc%9_IoBZKrB8nvVBY#Y
z8W{4?AKe8oU;WsV|9yW#e~*p>`s;(=f#PZX$5ekEps!gAv_SoJdNKv+!>G9BjJ{zR
zK!f!S^tqid{YLsIb-4a(@;5?XN*7|Z{w}S|WAwgM<{PU&!H2(R_1~*7zX^IZy+_XJ
z9c`hIs{iW$|Bp@2p<HU3{`0S4@QQv_5iF(a-<}P$4E@HZ(3q)jp)Jf+{TzBzX6ZXh
zK(h6}QdQ<P{os?ZbY1VV0Vp|obtWw3>VGf51m)@HY=)(L{d(F?73e>skEs>vKROGM
zBK-$XLd06EKOqFn4Lz4)=Qs6kq;X4s`h6HI(J#<Krc}TB5gN<%gY%$Rt{<Vq(rx`j
zC+4X_zwauXsnmy4iA|LrX(`+l`t`BkYV;p|08*=89tMRv{Q)6{bVonu5HRcYkEu?m
z!Ky!Kf<~i$t^%Y<Kk5zAtl#!J47TW>rj$;ro=-c?HvMecbhPWM>;TiDe@I`7>C|i8
zz;)>Z3xL+G4-Ep>qc5bTb+0~-@;rU|ujl}5zrH3A+<^Wi3dG;lucZXqpx&Bw3ZVD&
zjApoaUmsZjZb)yUNZbQGYd1t6>KD-ZbyzQ>zi1uN-=&{<RR7x(KpWGC#lzAg{m09|
zjqBf{a=!`vcKUm_N&TL$L8kR@orj|{dgsG{wl(zQp*zpc;9ZURJz_Xwb%!N;!=7|_
zbJTEV2583&hBu*c+)(#5KphN0uR_$(Fm(ZaPKHr>8=f#E#sSUQaJUTyPa3>a(C1?K
zmvUaNhA7$yxfy<<#ltDX-8V4^cY{5}>OBmjv=H+&6ue4zg~9z0<sZBa9<;&sF?>hG
zWxj@kw8B1ZNT*jvfFWZN*nx&kRBsSuSVxsBXAHv`@G#i$?4J+`F{DT!5^5Og0ce;(
zLMY*eCn+KwVOSIbM<Wf#=?fWAhT&5fOSIvQ)gUp3)xl5f!A)XVSP!%~L;c6VjyF`%
zy>ix&{0d+a4BveK>~n@UXsLPLfFm_{0U2VKK_SubRSLL^1`}0YCK*zw`XJdLn2%v!
zGPo9lOEIka270N6-#ybZS=QY9z{)U$(sh(+=z9dgtA=z6>Sr0w<f1X#(0K{mHACQY
z=(}!+qNG@kVed}>$u-1o#rX0Jz1M(}ZxC5vpuk`^32zGx!I|KS3~62HD>g8D!QC*V
zQE23*VM7{3ZW;Di>7`O)_?Zv3)R6TT##d&TS&FGBH_YfUl-q`m8Ca??RDK2hO2cI(
z3|1LhC>LLCc#j3N8pFl4Xsk8tq#vTr(0>3ZcMQAfMyWTf?}T21p^n}yjfQl36f_yO
zhe4s$Fy|os)@_C=S_8BjzAnemIt(lq=yw`sm&3I#L(c!u*KLr!1ehMf3u5T^8ctDd
zNS}eX9_syum@`lqF!WBrr@ICb{Van94@&9ZGl(bzeBTg02kJuxErkdl7;X)s@1fz#
z3R>$78-9oY+KAzoSui+iD5VnGF~b)6$tMiWGU!hl)>78vvEf`3V5SUbogq1GF!aFu
zjA32~=E>IhN*9Qoaois!ju@X_1wDJC7cEkb8lRX2*Nz!i-iO`e#)*Rfb1*K#b-<tJ
zX#A3nKR6k8Q1Ix4QAc3`XQO2wWKJ5-dEU=jW{tUrwo}HHKLf?x_$M9V@GwTMf`gt$
zGp&ogjN`Mwc^fxU+S<o>ssswY#*gSB<!8*Lu%W;4v>c76jbT(-8DRW{61RcIXTva*
zAmbE0{?8aM(@Hkjxc3nHLX58;1Q%-DV~q!Pm~p%qt>MOp-$5h7xc(E^jWia#1hgpQ
zMoK?N8$;+`iZTBE4Ekb?Vmf3QXEf)5#2e%26!%%<`ZvHO7*n1H_Bmr-Gt|!;Lul!J
z!T3)!L=ugCR91e`xa0xmCCT`xp9;*9jfvyvykwlBe0hrTO-g~J8n-@z{$-;ttqjwQ
z#awV#jJkKAm~K4y930Is3bJ7^)2KOxzN^LxS2SKTE?W%s>&7QP0hePm(NZPXc<C94
z<Qbo%@_>BfKh2oR0^?yVB_s=thGKvg8MPE&EjAV&0l8sprHYH2#sqp>-ZF0e2O=d#
z{!8FWjanx3%Z!n4z(l!G{tgCl+vq`ygbL#%y@@N0f4&aMD&w6*h*TRB+CgfJ0vQHa
zYpkT;NuBXE6l&q04UD!HXw(}IP|B#m_$<BI8jVjT1GLGQPGxG%#sYe%w-|r(z+AQ(
zGiO7g&G<|{JZv}iP&~N97*2bsPUAs3EzxE4tcG5<aq44W_80}U8R|9W)0?=@7@~wi
zzi}>=?^_3qztF<zuJO4BkU^tYGO+I%kNpDo?;Eeuc3{Z3mk*c+#;A7y^U&D)63DR8
zdl@W^7+0h~Z`7DQ7i7#Beg!5T8CTPyciec3UK<m}r$;cPNu#(CdXJ5@lmeVGGWyXs
zZ8hf6>7g0pGgGi+Yx<IYUpvza%b<V6G?oMnd(&KsbsaVJ(5-pQ^wz(y<Y;<Tg+?cn
z%{qvjFo~+r=WJqAfa9cT3&rGJOg6i~xtdnL5A$v&aUS$enO>rzGk4QFtDxXvvL4i-
z)zfsCYMi`G^%UFlHodS3#K#msK>=UW_FfP_lU+YF{7pA#m3`V2L(i@N)12*S3^e`W
z4TC|ZDykMeV_G1APr;@a|0|F-`R{;2sOhWsVJOVBhKdryO`nB8J;D@W-2*n#bb&6f
zDAS%yC`Oyi6a$Sh#XG?7Sd%TKK;le?Q_vT0T1ZuPXH84!AY_8+>p0BiInx4q*`GJv
zYl7YdQ$4+s5>0}?(09=kOBvfF)51~cC7Yho!QV@!x2dKh#gzIMB}7t9Np%?SWmD#x
zXiYPP-NIn5m{P{jmu{L*Nv#aiWy(}#nkwAUch&S%3(&GmU()6v+Z1jC^Vdu+R8D){
zbeaxs=9u=<Lps;AmCi2ZnH=B3Sn^H%ccD;V`eO~oQfP`#rhsgbi9y$FvB{ObhIhks
zI36-LO;=R_Ej6{O;BcAg^K%d>H@Q=)=(cI>S%_4azCR2vDosuFL76Jki`!wo+9Z7&
zgQzh%K8<15nmW%wug-LxB=4A(HG-=*ExiXr4W^kDbRf9V6p;+HCet635^pxS?gUJW
z>9Z_|wwf~OHf}ThN!79KrqV2osl$|32kcJMa|>Xp%fzAZU$;p_8JHdulT!G-rnwZ0
z>@)47^<}?l(;rY6FkQ?5ch|I*vcZEUUk<#m-ZOnj$IkDYnw8KWGQCrP&IhI!=wSUr
z(@A<14x5a$Zy7OVM8dUE6TY8<Tg~J{!R<#Tt0VNrO`12rO_*Ztz|y3t{%M$hZ1PzM
zg(=g2D}ia#f%)KOOyAK%$kxoc2NXN2Ie0hNBW5qUKJ3kdH6TaL;yo~U%)E;x|F}77
zHN0>zPjo`V(Y)FRCY;Pu??L2*c|Dc8IGgKVhWV4`r>H{9#XLx>Tvzj}Ct%Rc9PmG2
zo-&X81>$bj(W!M0bJ0`K^E6xi$1!^W<}eCI1e%{%2}?odPX}P>jQRI)Xat)}_n<Mv
zTumo2Le1)5G2Srq%XB(9+&oCTrwH@IQuIZdkGY{Q#;lnK^;q+M3q<0~jgCNxHyfKE
zdDfh}A0)x-FpOzFXTD+G4o}aUKe+*!3uYTyN+g;uy#{j8EU^GI$!w*@WOF$sHZGYL
z(%Ln}e3o7-spi?yFmc(ufnqml=Fy|zu9)x6fJ-+^vmlvaHcnwmvdkAc0G4guE5NX?
zng3CNTsQNa>3Nl79ykZlT=R=`9wg7aPzacO^FE3z6__=YmMJv<y%>!}X3>1iUa@(+
z2YNTm?X;=6Y2Nlf^xZPA%!G*&^Aw$<EH$sADy%Z|1Bw!rn^UP&@V5E2ztLA={`YN=
zYV-f<=|Dz}`R)$L)SCS)(5N%NPtlJ%=CT6Vtv9DpbgIEDF@ZFi+vr?XlX;BtBF*Oc
zbc?o_w`!o*YA(JF(q=xm3t;W$XbU7e%qRW@N~d{J1=3|+(TH(&o0<M_rpIhVS&(&J
zFNOxuK65iwnDm?5C^a@<uA}|`U30$#8iQu}LiF7;J5h1reRJd_><*b(XCd;y{5F+u
zJT(9KB^rm#DOB<>Viwc3cGR4;6wZv9_pvas6J`OewkOSp+&~_icUQoWb;|ri6xeCA
z10BeiF+cM$I6KSfS<pCQd7Fv`>@7XLuzS?<A^qsbEUHG>J#Gmp0q0=(mWR1;v~(u|
z&B^jM6^fj&?4ljJv!!4VA}1}Im%|Ge%Us&wxLSJX4eMsfI1hzWR!b$lq}(l?RQ%~-
zG1JP}({h)hCtj9vdS`fBCUVi}V@aNXU0;iy;*@@t%h~YI-_mXiz0;Nq4H^S1%dY`6
z(6V#{m_Zh=23R^{dB_Axuw`!^xDZPyZPi09t0OU_FpD*suIF&e?(e}ySO#ei8EJ{2
zDy}F?`&@uVTV@@_l*U+Q(;_0?^6&rP%vsA^iUKBBwzR_0bCxg)51qG6QmMrSOE3eL
z5-qRupnlP^j^eUO7Aaj%$(HJ1G+wgYp+{MYWtp`V-lSS8DRX<-@+Mt0X_mzAA$rYn
ziAtTWTjJ@-lw;A-D>B!zlClnY7S*3Hm~W}~f_kCl<@Ye&BFk_dM2aoNw1c=|`R+JG
zZd%TM36T<uR~Ar8Ej#~0Uzue`HX6$<F)OV=yKVW3ev3-WN5{}vWr?DPXSJok9bAoN
z*?&O=%Me|Ub(Z=%DBQ7((}zLpEpr1fv<AzABA9QqtTtj0O_oF<>^56I561{wEML%?
zzt!^0LWs0kW@<4r?UpY%Q17tVl+*p!Y02M<x$Ls+qy%5LrG?gdJ(jOGgY;TfDgoMO
z$)ra^zeV>X6bCGS&{N>9rRq979JKJaq4A#ORw%gpmM0&A3|U?(hr$EPD=)$PLrYg7
zd>XbaON8Wz<wsgBj9QxBr-Ga@%O*8^o3JdVnvhA$(2p?q*m9qKm?_JrEohv!Xcxn^
z8A~gb@!Q$NvM~uqY%bH@!QMtj$JLM8G%Q8mF`EO60p?)SHy50v&GQVHcd~J(T;~a!
zUs}OA+r-5}#KmUSJ)l@!ZB{2j)XnBI3e}ym8S8?KyG`mEfO^<8w?NU;W&y3hylfnn
zfOy*sQ<lZY#&Z$$d~N0@Ld4HzEguU0Hcbg=JZ-Zi2>u4xbZ!P%ppAC}h8<*6N=v6R
zHc!$`8Eg|vFM<%O&Dbu;gxdUeA5MkYtfM!4xJ_9*xCk3{E(}K6{4Wp&qipy$K%#9_
zZ$c!-=7JmsV{KLxVH9yTzH~w$-X?fC$XT1XGx+TjY?3MSdd|k<GkAF3ru<287i@A@
z!hDiVNDw6dkE833%ev~~YFgR0GSils+14z3_TGD&sg+vV&`dKMR&S4h$Wm0c2neF6
zED>ZQB1;5h4;cb7WC$WlWWV3jU*~h~J>PTAz0Ysld(OGP=Muwyns&sAj0%c+CNaw2
zf#1oDS1CxG!q`f2*)+!Iv?57oWYO0SGZ^nb0m;jZ9nZpiCgTA`>arNo4ZvMxYzc+Z
zY(^ZNkjr6AUBU=+87}b<$!GlPi6LEMSf~QLfKj{yBG(!3+Ft^&ka4ULqD71q6s{>|
zg#HOjHy9-$kSSptppxiP#*IO^U&c8115A`NT>jhhFqVe{SIICv3f)zVubtsqHDid1
z`)U}C-WXXeWAz&V++?It7_E-cL#3<r3@u#=4U9MM)BV@Tc-;@WZ!zAWi>--~JpwP9
z8HscSwlGR5TXCDwu?t))qme$9)y7zH0r+;t`3gAN!5H0%dAh@BpgOTm##R<Yx)`ym
zK)M-WAEU9CF_-Gt`xr~8jOiYuW*mTi#@t8g{=3iEvlKD|j5gZP3^5))58yB(@J%$1
zFw{?jd%$>g5xf{>jGqQ@jL}Q!uW`nPc_0%EH;QadGB#X<$P~km?xq<=18v;)GjBV<
zt^;#&1vp3M&QQRem|;J|iv!F=EKKb4oSET=(Rz^S^CYynFmF%=kt=gP<q+MNn|r~z
zGi%Dhc`yfeU`h`$SJ3r%n8~99ww}yo1DJ~=%quUT@hDS5ONnF5nh#;Ziz%Qir8o0Z
zAo_fmQ<NF-Wj>%#nIBU}0dKoM({&VT0+_LzfjG|W6~W;^W-Tp|PcV(U!38n@-T{0t
zvxRnpAxy8Q;KfPig0;YfGKDWeO&D|6Em%6m^yoz68Rln$@FIdKi3jd1GnN9^=a`#U
z0e+r2l?y|W%+(4sM%kG=#6ZL__pOC!Ec3Z&v|eCd$%5TD=7*FayT}wRM`JwmYl@F1
zFxeEkO=Qlj0U(L_H*GPKnW4$}4N{n|)BYlrnS2(O(wP5pLDHG=nQ$$GxoIzkbeXxG
z%6K!G@+xpwnD+TKKwM>3<X~#DnOTA0a+u#zGA)-`od&yk%!YE9$Y;jV<#CO9=P`J3
zow@H*=q_Xq2SB8V8Ttm`#mv}eq4WmR*Bd5Em_v7fD`mb%9+oplDI-zA97VurUM2Hv
zCID4ToxKU2)yyBNF$pzHaTH`~nVYtQ)G=q#k&}96Ep4zHn9lSFZ)8qghuvGuAF|Nc
z!u)Y14Blq0+z)N7%$x<7nKownkC1F<zU7HQbTAFHm%YQRq+MAT^Ha+7b~77j+u6gM
zl}P))yG(c5I`uMLtKm!^^B*dVxyQ6qEb~4yY&IGPn7f<c_aO7=5&(vnj~xVlm|5^A
zxDn<)H|T!AWKa?2D07&Sh7Xw^t_L^9e9ap^jWY#w9%Pbvcm=dfF<<tEzthaCH!1!y
z!|d7y6Z=`4Cn4j&VpHVLk>$gN=mFMACA2xSO4p(9AdCAmro@G{odN=`tneS9+l}=B
zWs}@lzqG*MAr@m1xWlY1LjZWP9O#(D5!Pc=EO(Uk3RSWlV_p9TI4{;Y@hsebKCC@!
z(do-t{R<F&tQ-oP`m?@%2PA;?#0OA%f)$+uH9@S5Gms2s^~Zt>VXeOn?j)-}6W)ii
zo_rkB6~@{{o9A#=_b!N>W?kF>ku$89!_gSQy1M|4XIWA&G@fG#Xr*dD&uXBfK~bz+
zSI9)OzRN&s3@b7Mjj^mx=@ol{HSjdJI96m3`Yy6I(QYuFHGd080_*kz^j%{8&xD~R
zvQE-nk<8jN8{Vg|KBb3HDr;f}eQB)EJRq6Q+9t=ZmBCs_6(X1ItZ(Qly~5f|`>-rl
zFJ(fmvRV?LCYz<DmsAdG<6GczS;~JQlE+$0N$_i|rId#)VC7KQ=sIgRZFUM-;eVj7
zh$Xb)M=NIeFd=e-wcHV;l*OR6S{W;LBP7dN0l6R*Ec-C6#41@Uw_$2(SZnFSLA9*U
z>CnYZR^t$4>R6xL1iqg2;2$(Lu!d--*vR5If;6#qC4e-u-lkPY3oEe&{@!MNsfGDg
z7K2_HZ7ePa@OGAX5Pf%8SLyceWSyiXbr<V>`(3&pSb-0ryNAWEhrzq7cFM~3vhsTY
z>|?E8g890~>YxR0KkMV?p!7Z~nG!gItoP_CGQ@Jb43S|L^DlTY!eUsV`vEI}vRI?6
z7pV&CA?q#L<czb{K7(;iu+C4yi%FK@Cwl))v1+Z*J<WQo2Awmklkedd+0VB84&umO
zR1Z-n_BRwWJiv~v194_=ryuqp`vqD8xv>B20nU}3z6z4=?3GK<=fS@5GMqWYUP7h)
zhuLe6L&THqKwF4o>|Q#l=EZKDML}|JcGwR<_^|Es;IJ=y`f)hy$F`A-KYOAA9v)}c
zr+^D&$BUr!1p819h8@H{NK27mws;M2A?#dQq@85T>C2j7>{FBkKgG`32`-%dzxi<O
zG<))UcyWgPVh0){*bbib&#q_L>nJsTj-46-a-Q9H7-}NfbG`yTiv9G{7;g+aeGCR;
z*}Iznyukj5P8r9snRJxsBAfj!CNG}-VHw~FY-Ku3B(i_W2T5X|q)*=@v)?X)vJ|$P
z6<Si+17ncPV7o5>&VHG_n6BAOcC;@LSJ-d)fn>2?UXMw*%C3Qn^Rn5$>_=lR8|Myi
z1F-%72A9tsjfMGZ?1f>_R>0o!4d&@O`+HjE6tXKQ;#tgA(M#<HyX6IFDPePd2Up6@
z6+(3xd&?{|mfP7!Y4Kmd?pDEzO7<!$)2U(yQ+&Ic&7nPM4SVhbxPO!FMdy?1*n{uD
zd_6luhsFkW%`RwbWDirl$u0JebX2;Do%JpHTG&sXfaGoVyS*T->_fDGYh!=@8dSHl
z`>sNylWk{M;At28<sh_nv-7TEFg@&}w9>uH{)GY=z3kI+i1e|WDK6g6uFnN`pZ(2p
zkO6k@O^6J#-Ka!ki2eEB5E*7~qnyzQ`y!<YN7*x!I(o?N&4=nSb`{m7j<X*L!Q@S_
z)&E7WCfUE0Vc1jb7bxU0&7M#Bx*2v<HGum$m*}!|;BeUhI&o4u!5!c@yZ}qioN3D1
z9pog_3)6)YdH_mYIf6)txN&}<z?KI`wF)AKIC824Kg`+k4n#aTS7@hrgmdA0J7l~#
z+rq(mbKYD9&WFRMl&df2Y1(c0aY{@Wj6dhv(-=$uhtUN~ft)8_fTJfkKehoE#8Es6
zKrknmg0Uf-r4{%MPI6wQ#a1Y1_z(c6I3@Hx2<N0w%>6WHaSg~B&TG%m`ZI#F?KR-f
zazx3nbdK{2t;NrCT1$b5<b?S_G>UWjDfC5iHc^l;ma{7kfD4>IM`0q4^Rfz(7diK7
z0T|CIq^kG?&gWDBe~B~yFDOgmG;YR}By)x-{*uCZVgmrFoK;6?|Ch#TqsR1R&Z86^
z$>eOzgUl7qSG1GK;w+}9*;UR91t8g+6I-D)hcjmd#+1v6plxp+hfgoXYn<9gAX30t
zDT0UBIp!m9yO0z0E<}nr7uG=a4UU2iMwD>U)aWbaJVp1Gy_}<>*M0@(Ck5RAoH*Lf
zRdKTDiCWEhk@A!^9QQlWUCa51w$yc;e-47wa~f{|*TC68XVV%vwKt*d7H1*t9hx|e
zLi9CrF4L~;Hs|akP~FOTnSSgx&f^qoXy-gO1=3;XyiBR_JDkRM;bJ%E_j0)3!})^`
za+kBF5x`!~tF(IW<9N`WbB}Y*0Lgw%U=Ot2=PahB;sB@K1~SBXfdgg3oX6?r8sRJm
zgUADpiIQ`poRKtW8RLBX0Ngld71eu8aO}ffXr1DO(eZ(4PR}WDGo18w=-kh3rUD8F
zZZe${a^!CB0q4Zcr-X$wH{>cL4|3Bf#Oi`S?ghY=JBzAE+_=BwL76-EIaf@A2ltyw
zxP6$LD}kgZ*Fe>iN4TZ?pz|o#+fEPdW85Q;pwo+cnm(i8%XR$+oF8}XMhw)S`^qkG
z0o;#hjd+|}y9R(j?%OfoPH-QkAVm;2k-i)d%w0h#!js(b1Mni0JAVndFz!ZLn4IFi
zOwZ+T?qn8b{S4QKqQ(*2uCM7QIm<1h0@3r_?&mPVNN&L6z(;Yt4#V$g?gUn8^J2K(
zD<B!mjrkP#3*2-blwRac?17qi?isp&61ejhL*x>7E#0Y!-2NxvVG{T7W;7;qXD;Hp
zNaeo&DBx+_rxE~9=Q>tVK~4tOn_l~uxiThNGr11OpzSJ`&xe|9?%o@~=WyK_;BvXy
z`+(2m?oS2D=e|fm!fRY1t>p{2@evTY&fWYT;Dy}2tsq6*`cCu}b9d1h=^NbdTG3d-
zO$xzWlyW!w&d2>%#yv&pgmUiA8hBB`HL5@=xsFC4s<<;JL8`egWkJnNu7);_bzFNQ
z%-3^Ue}rTMcQgu<*T}7>Z0{}ZMyh;h;%=M;u9>@?UR5pJ?<r_@n_J5QY3067U-)X{
ze$0YddpmbN6_IstZ4}JC!~G-;W9sCVu7;&9Zs!h6NjLZTOaObh3u#Axm;0Fx_+D-!
z-46ZSeec1G``nHYa0A>DN~RBT%~h~F#QpS7kYR4b+psXg{q6(ke864x8+49x|E2}!
zLp%2tWunKpOaH;uGR`&8XBj8B?~kK#lB=a<=oEK>4x-cCM}Gr1!`-(NYWDM1y#=KX
zyh5rncjWEs2j|55dJFmv^8TXLjtlSZYw*{VcUuU!8?V$As@-`?K8OcTK+E+*JbQOK
z*uy-BA`nj=XDLh^;l<G9d6d^OibgM9@EDx&<{hArvJY>f4?tg@-&e5Y$NRJZcKvxQ
zDtQm!?b!@V$9ZRHwG+roqS*Hd-n+i&!>8lvlzs@08-RH_$$O3V$)P-jomOyRycLN6
zp5lE^l`Y}C#6mQl<~<q=yJvWJsc0dBr^$lSv%IQW^qu47Yy^qqy|DpaMDZ@PgNx>M
z6v4F^-T@6P#q#FN0C#~WqEKZV?>qX@F7l+5YK!OHZAD`Oulp4{@RxW^SAa<7?WM(K
z3UBvf$fWYNZ-p~yyrK~dJDv9<T@V>O@ndMb%=6s}XEJ$vUjw<q`+Y9VXYoWV;I8rx
zPeL+>w_-QU=kki^6Eu0e6_mKk=jGFx-)p?pZ2%PT7A>X^vR&ticVnQ1Jm+_SDB?YF
z3`&c6Uq(Xa25<Dg%>z$22=~i)e|?X}a$fdJ@Tr1VR{&fkZzUH7t9awT!bCOi^aU8K
z;dTCwvDET}wa|H!_xdJ?)bVO*mD9j`hd$8R$or?6^6$5J33LTE@!F|$ubJ0OrQ9vN
zgP#C+n|E9b(N>-lZK>OM5&dXv=Xud9vV+(79(?NJeV2_fb@QH`g4;bj32n#j@-&}=
z>*WPL2hzv;vj_g(<Nf**aQ(boN*dkgby9#zJ;0lJ9l8g3A*B!<=DqqdWJY)|l)&K!
zyd*A6jPi^zQ2LO!_z;{K<4wy!#(A@y;phZ!-3!n*$y?+-zx5US;;m?N<d?n%v=cv&
z0zC)#dnh>Q%)cK9a*%(v7%E-(estQvmA@buy4?7$u7VPG{+a}c9O8S>Blj@>i>t8e
z$={ZO#v}aw5da+J|3nwwF@6`_(q8<Z>DlAWANg+s!Drd&wd>3GqCA)%|MQQa<~aY{
zF>rzWfX6Vf6a1@`2oB=g96*Bkn<?cK!Vi81ZlC09-2n*Y&p8JZVSF(?SWfZ#KEb?%
z^Zy!x<Qe`=+B8S-zq3K|EdMSgOV9CLH^9Pq{<T;tua4wD^AkuEKd=|hMDstS)qV`W
zXFW(PzwspiFYvvbA##y#qs>h`|1eb-CGg$oEp~~&%MW%F`E^t=lEn9>1B}W159yn^
zDf}1?hMmgaeFm!2_}-sGB%S}lZHQdv&r{IbB$NM1BrILwbDKf3__AvtSNVN^fn@U|
zDO8`sf3XTCa``_U0?FgQu>*GV`HUj?bdCQv9WE~9XVNmeh<~67fMR|C?ci_lHMDUm
z;ZM@bsFeTdb~sbU|9v+^%K0}@>13Z*!T;<};4Aqodfiv?clJTFhX0o%@U{HWkI{FN
ze=-WX>-g_)he$nt{cb32;IBRb$wq!0)tKMn+iBm`#1HxdfM$LHJ-J)>$(JC~%8zaY
zY2)`*0oTrVzmC2R{*RHsEx5yff|9PCd}AM4yZE!b<Jw=ew@-uV<!}ER<Q|_xw@p9)
z)GDaH&tFU5HyPl6UI<?X`ES}mhWKf80C1Qen+PXH_{q(Xe88{V2>2-fRYw3G^1r7z
z+5|tEHYJmMPx=X__*M#^PxJo^s?G5KM_-QEFW6}R8U`H%Zsd}qU;}+Y*GVw-7w`uJ
zQAdGy7L1uOhc1FoDK+3Kuu~4-O>mEHMR!5PzmW70tXu|X4hi1xzz=y?5dIx>dI~&O
zV-Ai8KB7qZQGvA>s*ec*DZt__$e{yMJ_0|z9VUDQPhSMkPoU37tG^)TJ2)I5=$-}c
zxIj(@0|l%o08a=mw?Ju-pmHOW1`FbYFc&8UTTa4@P{BGexG=$49=KD2jTgX$3mVE{
z;k2OtG%TDEDB{o<AxOg0ZQfadDUCilbWU)HiV@EXQhlH_T988#?-)TkZQx@C>3?FN
z7X*vi;YFO_Yg$BJ6gbm%JYEof6SxGy6g|x^2?XcCB??ZIfJ+iI76OnWc!@R_se-?#
zdOb~WiJk%Jf>l&TnjzSX*CakVBuLMP-Aut2E;_FWHc|L6OOUx3(|uL&Hbwff1*>T{
zlPmazashdQ^HfrwFX-P5a!ueuWt{~A5j`re3&zp_FBHtC9ea_$V-rZRV9vLYydl`K
z2tz6nyqp8`WrFqd;jg`1@FUd~R0!Utv_qv}=L5`hm0&e(;Hw2q0+1TPi~?$E1(N;H
zeN!L`09PmA*TI>3fk+0xEdgf;9ySRiw9af6XsKAPRZzGaeQg5YH!=El!PhjEy@JJ_
zu-7MOq%z@qcEP)eu-h+KOfmBNg12-a1A<+DgA59$&ceiy;9IJ>8y0j*Fv1bRt^F9q
z13~+*;6?@8pNGgp!Q(WvF~MQlv5yOu{sj1hU<<ubCk5PTkST$Va*xx3&h;QOf<3Rm
znf*e0+z&uF2$Oa~#!=`@pDc6|4pNor0bvgvopl!eP5HKi!WxPnxCrm;hCx@MJJpQ3
z2@B{VcNbbe0nS4hLmw<XBs5TI`eC6D4b)SZK=lkqgeH2R9Tn#N2EZ}liZC>K3DfMy
zz<LYMS<vYtT(|>xUtt<;;QfR(CQQD+@cna86CgAz(Rf^_p?7bf(20KL6T-J<0T(3n
zkAaq8;Z}NRg$Nr9G5V9jD0*jy3Vr(^8754~M&l`A2Q7iah3l6==V_tSYI>%e5#|K|
zA0hm8Gepk{ZG(_GCtR@@Q*vJT`MV&ILI(<!M+v?6K_psu-xK4F5pJr*%)|<NC{lMp
z=t?ijIN?8Z30xG;c^d}fg?ky0Oc36pkDFZ*)&{_*MB&@H5J?i&=h6L_ESwdG))e6{
zR8WvAyhbbdG-1RyK%@(w-;TyiVF8u+UJ<VQ7r-pxa#}`R6}}k(-PuBZG(>WQp;X+I
zD~zDzeV$O2fxdiU&`0p;ns67b=?a8j^uf?|p_U5b3Wa$nHn7ht5|-1&RxAv73HTer
zx%IGHBHX+kh*IHwTBnu?=TM1xxv-4xzY5_js_L#3=7d9cm5@uRmujK!26#~;yfO(b
zwZZ|aioGdpJB!9T;iM3NdZAwfv@{6CbagcfUmt{7`z_(W7AS2J22cfcvoMWL7qtj|
zYv9FgVNNqlv<mnC46aQWL7}#GVKGfthj5xMk2}Ke1nBD&eo3_hUBVsPpru>*@**_$
z2#fPD(7VD6s+8&#?xEW5K4Ayesq^j$U!l9P-!5EAnWy{0pOYaoAbjQ~fP=zs=_~$2
z!bd3YJS_a_Dnv$vA6LWf1L2Rqz{64Dm*o(7D6C!ugJZ%sL=YJl?xMx=gpfN2!=4m=
z83U0iq0c#ZF)i$(P1KA~{~~nm7dZz5;2^Ry4@1ULbb&IVP9i4lpbv=Vz6qtyqUE&z
zI4Fvw8YdSKi~gO#RaE*6I5&~-G&pxrDJ|VSM0*q<heWFfVg9hF!X1tt6_wwDiDROT
z<7o5}{Ya-)yhX225s8mz?$ZGHibCx|sPPk7+#%yHI!fP-3lRDIS3V*tq0g`die8~l
z;hhlW(yA^<^bHmM28*WXz7G-EDgSg*H2XN*4izaRP#PwBVhKinN>td4zHm_n1>8@I
zT4Nw`M)dgG5Qz{S+6Z!1v}~Ro*T6ZEd_FuqFFLdpqLHE{Ps9Bvk+%YU(W1CVFbOdt
zHRTs$MWz&R7et|Y;NwKE4MXyx=+xuT9WQF5eL#X})^2c@M6bUNFA_yQw5drFc~F5$
zvZ#%GN)f$r0a{W;ss0q>P7|fiLub0^GL`pah*nV;{<5e_0hvtEV|T$_5k2z@)MSgE
z2!YZZ(ew8(7rCN~D$GotsF6xR^F<EZp!=HW7kXwFh<>D!l<T7GRKN>Gp7be$B2guk
z6%~s#lwP?Zx_5l;tWEPuM32>CN=rrCv}i38{qY#Im5ZF71HMY+DFmq&37&_V8d1a=
zI9e-ufl7aFingRevQ9Mjedw+imD6sdLG)rCv^0v`D4TUlw99+Jy%+7<t!TR~T1&O%
zts>;da5IT~K8BKZ(bp7C>JV}1qP`=Vp@DUZMC(AhL<v+z+bvR4Wn_=&);!p`D;l75
zWG~DC-Y06BhJW`&H*6R}zi7Z6efLFU^wGxw(GVRi929+Er%4|Y{YGJ-VNpUjWJW~Q
z^tJy7A`S($Mny|$)%sAxV}lzLO;hw?T-4cy-*ZCLPr<`U(LpyTof4hT#K5LSD=ZM1
z5se*!Yx~8f-=Nw-T-6FmNAVjkW0su6j#O25K)h$#4urEfau>)!vF;gkx`^jK1j1GP
z-6j}x6Z=yF#a;aPAMnCMTt$z*L*m=COgJpQOdopk6dRrd{D?R|0|t+Z&ro6VF|l_B
z`n<$a%Ds7u8B!?o5!)%5>nrwnAANq}7hGxO?=Rj=Z@2*Q0IjNyi;HVuDNt<Ofl-_g
z@1c}fka*!Y@FG}j>4Qj!*i;KOC&jC&JS|jQM;|8&6R)9H>M3z1mCS{U`@aG_LhMgB
z|5<SoWj@Y{uhRv8UaSp)&PZ{=C$#d95-%HvH__sw7hobrtXlvRvEl<%QhY(oNJC?s
z__6`qMe)5?p)_91)<I2zSW7#OOX6^M=uQ-WNKxG+@gN20lf~z0pOzw4(#|zie0B~1
zY2vcA(2_3xgK~Bm;$;tE)_z$$eg>_XV%F0Ty&@iCfy)wmxP!YYUh05>W{X3;Kyt)$
z_ds{9_>w=g<%xs$!L@vG+CKPuP26NdUx9e#7`W@=@4tYFLh+w3Kv|L4uL4}LI3y9=
z4e{%JP+cOPUyErjwTmN@psh^&1)b|G7r(v+epiS?12C9MaiS|+tP(GK6_%>S<+OOd
zDelMtzD~UM3`o6LL&^3AaVKq{8^y2PhNWBLWO{})iG`UEX%_p@3${gE_&y|Wi!&*t
z*D8MbcZjr!?X6z`*e>SKb=4uhc^XdL5o<m`W2acm1?dw1GX~Nv_SXZ^BW@T6cUQcL
z{@SHi+<FQo`ouMXaQmM48G4)ai@&0y9{0toX~i@keu3WIgW`=z5E&A;rekEo;t38$
zHX`n`XG7ZqarUDyKPqmbilc{ObsZ*gOuXL*h;ecMQuIxTA8v-FNwJYaAyeX!0^p{_
z|9%T?Gvemi(6(Q)iHAN1NoF7bj*?@v<#3W5x{baA64$j*<}CSpE&vB52Px&~B5`<=
zR!6RqbE{$3O(OpjGVYQOe+Ti9?4p;-AxY<QXge&?Qbnex#90pD5y{_mXgn$jZiE-d
zB!91gq?g2)1mZ2}r3=DGQt696U&$8=5I@N$bk5jcvXK&00g@ftpyjwE=@t58(?Cf)
zJ?>6Oj#DHiNWv<GnqWynHw=bIE>T6-Ny+<^Bng$gLJO!c$zTV#Q<9yOOAePzQEmHa
z$?U%XI3t;%z<z{eoWlHPC61o>wId}_6cdY*NY{ajmV7`j-xx^<!b$jJQ%MF@v|NxZ
zeH$cB^2(!7dQlQgH+;P07dA+OBsC1cOOlbdFi(k+scCqTBnkcpt|d!WQ8Xb%5>5v?
zQzgG_h3+)T4}U;Qx@0R|0vVF}zW~21S)Bn3nUc65kSmf-ij&y0BwqBTi>neJI);@k
z`GXcKIg*AKVJTPg>=r1^lbk9+U%uq)Y*@M`Vbas9K=RvX5V<bdbpe1v$xaQNDUw*1
z!eFsvkc~;WA$jZuOq58b@5A3x$$c02R3@2T3T5Sz96FL;VV7K{`@T}re+rhWByCJ6
zt(I)v1eqF14ZVD8C11V?r8gy?-+?6l_GB(Z8YOv3G~SY&qsopZNjH_SG)pXJ;984h
zdI1`5OCA}7YpoLVFq~<Ve0mKYwo5ku0WBSpe`)i0N8-I`<QaRCEBx!0{7k1AdL*uu
z(0^BwR|nE7siNYPK8ctXoA)FeVxYKRQnm_!`;yuZ;pKqj>2W9?l*s7?JS5plY1Uy$
zGS%gdNdBOe#sf(Pg;qx;|0crAhmw0W;Kn5952J5f5@+9o)(OeMF0@WclqGO%O43ag
z9Mh6(<ok>y^#}~^mmcZ_aghE^i#|u`ZCa%|Nhg-W?E}&hI<n&|RZz&~pfo5CUbsjv
z(%ZvT`YNq0+@xPV4}iP$#vbVOknX3S!&AEBd3pyPk*@p=UL2Laasl{b(w|$<=q3G;
zY7f1ouScWNNBTVFoP4F7PXXvBy|xXy{iUn^gzf<8uI1=EE*&k0i9qRQ8t4gW(_U~v
z(rvV14wgRLg7Jn*OX+Aum~`>Suy9IhVgL8%Hque5VmmDjq>#iJ>Fi)AjgU$xFn3nU
zq$=Ta(yd|8c3wJ<wycrT8y)Z|O4|NCB%`IriNr|T>9eM>(%MHb`U_I!HYkge7O<iE
zqBQ(Tco8oxTLN5ybmbVhOVU?xq2bSMr0f0%rAbozDGV)Hx_TPG6zOl-(3UD4Yk}@G
zsjdaUbZIALK{BL6^r*co-S-(JGo>$5o!u4blSe?Zq;s}I<f=4;E~{+mnlRvUq-*FQ
zlPg_2fzjtlcRqxN`O*T4KiRKI*Y<%ekh)KTT$ld37fK7IyEs4;N$=3EsaRT0pM|?2
zO)o`XiFAT?3Z>F*<1kS!9k~V*6;jJ1AeGWUDf+6U1yr6?Exkx}fi=>bDvY;Q`X^;p
zZc1mupsY@6r+7@gU0Udd32u<`Hv`cqy+iTLTT*WVHc7?v;6=0a!^hxvi?m1ye4DiK
zE#TXwUFRU#A&pps#yiqAj(~Sc&-*}Wm$b7GfNtq-dUW(iAE(RmuJo=qT<evVtiiDR
zq#sg!&^@Vry%21_RC5S2_ocU9g|-1{^DU?uluprwI3&F?4{C;`Y$h5<r1i@Id?0<}
z8~~$IGX*vtO6%#vJ7dy^R4O(uZK4>)gj8dKvPo%;3&@l-xfq6~r9b<?`x&Xw0Xp}~
z1okmd2iY66&vBHcP`uhnwrv841F~vb6gkVBUxLzuGI>1uTx72=gKk&Z@)n4=$)uF^
zbeAoC1(F^z_s?PCkgSFB$%kbUs=D)(eL$y>j>x{FT=P*`<stx%$(AlbpO=guN%x<(
zOn3^!M^=9s#8=i?1H7N?_Y{oRU-rdm3@t#G{tL_>mo1otwm?}wWiL<2o~G<akZj#4
z^aaaS(>bjW*@{m5FehbRlr;^NJx@>iFxf2%-kp+7RX{RaHbps!(=v50)e@YMou#8U
z5wc~pvpFkEI1V-EWINUYabDI>uhK}_Y!=*)l6_Bm^Jv+70Z<wvOQmOQtgJa6+y&W_
zp&)Ux1F_J3QFbE*mf~d_&H<hvn@e}&CD}A36BA{Q)6kM6b3(nTeO|Kc*((@titOz!
zbf(H4r=r0$SqGIcrOTWtnUNu@pz7qyviIq$5t*`M-q3bM)<!i`S+XbhL-MNZrQhIv
zw(JSIR`X=*4#Syz**+N>ugMB2I#VE17y!5~d(;<wg|fRP=(88ebQEhXmi5qf_J%C!
z1UgG(VR^7rDtmt)Mpz~br`=k)EY1m*Dr6nlDb1^tb$S6;C3~t4q*`_@3xFEgkpY;m
zmH9*ga8veTAKb2!?Vt~;)ysIJ=xdPGegt@<>_ys>-?Gc{KLu@)9il~Zv+S)a0Jg|j
z3OI9Hmiru(w#rtl1!<H0`3cmt%j)mJ!w%W!!I<DXvQuwEX{U^_0$y~<PEJCkTUK)n
zB0aKv3Ps$NJxhVIURlR~H=b;{3q<b8N;=_1zs!C#8}z=c<Vk27kmb>pG$@--FPS0P
zLVCRq%YtV^+lb7z8QcR|)LIxEm330Z^g|hksyoJHLsRf~TvpWwWfL-I3nV9H6591m
z$@1taFfH?62%R&stz6*t%V$w$$3ec?PG7-vl-uvZDJOYA99j>^NB`TI$;&JN9+U^t
z#@9vu{GXTvSNT4A*}KV0DZT41AEuO-hx~b3l^l}mo&)@_d?Xbfddk<)k((p(rnP81
zDu4T1*gYoSxEFn1@}HN0c*}#v?C{h_zWrr%`pFkoV)Xv<Ix5Wxkbg@z*Kv8>8t4v`
zJEw!3khi^s#vr*Lm0ShOSJ1iJ5P1u|=ugVSsZu6X?tL0un7sSHXovjJGKhrB?@@8q
zY5B7&Vd0GYcUp2s$SZ%RJ>XgSn}0#uIr)GDvv*$ps|dr6lvlq3pQ7Yk+KoiZ?_GgN
zjGUVdE>^zbK143a2dJVbPX7K0xOP##hn_z1a*rnTCCC>rVE2+d>Nglnl$*Z+mn6TR
zioRs|E_%qP$oK7d68B%KeBJ8+rpceCpme%iWQS;md=HtpEI&xQuT1$A1#qv(=N$r<
zC3mBNUX{C1T~xN5Sq+jS_n^}ox$=QW;9;ITlfpXr@}DUNe@!lZ6@UWyQ-4CFQ10Ig
z3q|r~im}>@<!+RSz9EmV1foQ)pq);sd@vOT%jEGb_?^n-KU@Y^Az$zsxJvn#QgBsr
zf7%>W%eS0^qc!q=y7X%0YZ)+qQ~uN>wA9Hzr~1o!c^K`L8|1!w0ce!}ejJ8w$$wJ;
z*JPJ_yn$gi%a2mrtVN#uIefb<ucsQMR{5+N0NdoeM?l);RytPGfeR7jj=Y}|?w#_f
zacJw3*Hl4Uw_HH=P(AWZRM2!+E~G?LuRNw0q)#3|@$P$aclurX<$)i=-}`d=2pvEl
zkPm!_$rzNsMiHwa`Oo?AX;^;J2E>SbH5CCpkoSba?x@^41<8l<-`+;wnEYAF%#O?F
zEQH8}Jew8|lXCB`;l-4E1+BoQ<$_Fz%*eSn;nRM_=_PQ~L9v_8avV@-?f;cZD~1AK
z@StM#ParM|F5Q%_imz9Ib5p!Yn@4xWC(&@&Ly<zKC=Mwis3hUALM8;~sd$D$V@DKY
zy)bxGp`?}nF@?z=B3_CVItSpb5Ynp7NAcw2aMV{ZL~k=cMY%8S0sR$WbjUnF@yQXi
z9#<3>Lncu12rbr5D5@z}7^HafD7*+(SiVMIh@ys;KqnQ?+(%!i;%qTUn1T}xa!QfC
z7s|pF-per;rxleHay_G%YJ;N@ioUBLXBA((2lzR~?r-Pf{yVS87sACz#poL#Q3^*7
zSc+B5dIM@MDAq3nB2F>y4K!X<Y$m1g3MbkaBq$mvf_h1@Rt~ol70llNPf~<OgCr}?
z(^ZzDFrI=>sS43cfTt-A?*uMgvE>tx3`H~o`p9!BK06CFnTnkgXuYE7bHWI-6uFDg
zcvbN>-G<o;4=VP}QEZEXNUq{+JZ3FVvG6QrJzp_SZ-;9NZ>ppyP`vK|?z-aPdf*Bb
zjTHbCDVEY5UaY92*v$<^1nuui6m9h4v6m`7_%D>NF#n3qaz!1jw<{E~Ft}f-h&qGD
zD#Zt%L20$(7@fAPQRqKFU#)_>5BQskC&+xAVs9>Hre3jxQeh2>k|x+~R9tO@$SuWT
z%11OQKK6vNW<||G09q7JP+s}AN^vq7GOdbzX0)~`cGIq}T~R`XeI1GelzHq@+)99G
zw}NlPB=#uYh=H2BieC<c^eU2m0_ju4`d7@Ez058z0d7dK>n)fcR?JR8--u$S3+5jv
zzNU!ns6s^rXAc$Z-=T9%5kxWNamC(yAQOr&==AQSqJd69Oexx_plDj*;{~%binl)l
ze82K&5kwr63m(H9Ix0Wf00*6v@@FwI2b5wvWj>shPBiNWmGx!dT$F9)(Cw=9*b9W4
za`z*^yDNosFvLSCqq>ztN)rXX4l70F;5?PFv`{{xTtiEz0Od|^*gdWcpA8bI6#f9o
z6Us!|F9s=DTj5%;vXv_FLX@9>KvDCP%5(H&3sw4k3ocCg5v68NDPQn}`Ecbm3Aocr
z*=-=sDC=ke7oqf`Qvqj{g%>c2b4m_X4xd-<e~89NrLh{$L@7U}S8}v+Xa@i>N+E@1
zW0gmqg@+fEs&yc7O5<;IGUKB1<sZPtE1P)0Cn#NL@o-6*vmIQb@;X(hB`J%SK_prE
z!`~n&$`y3{C{?-ZL%K(lbLi}Hy7IlFFp;5rg>JaZ%JW~re5TSy!MH2ROgA)UDPNwA
z0bW%;9}PgR(ha8=?DO)JJN(d^uk@tV^EIVu2b2~lH|_-fy7GCds3=r^DTkUO<=jo^
zD^@;b23Ml2pdy4)<*V($l_@opAu3mv6@XMI57HUPO687Ga8=4zA7Cui%1^0Uy+$db
zimO_s=Vus;{id>VIb`aTuC&~*S3W}7`37a_B@DY!x$t-NH7g%(M_-Fls03+M&dCD4
zO?i3?oM~6a4nw3v`5R^4?<n`0;cusMYZ|n4Dg7uY-L2eahO!>zC$vDmt2}TXuJtNi
zXn=ioW$tmv+*5u>1uXqakDE|>Um2r^Zv)DzF31cjx6l<lq<nG-xMAhHLC`j$Y`6;Y
zK)EXxWK@|l1M?4+7ih0DrYxqg(zvp$4S)%yJsUbFm8U4wF{K=N52~k?BOJ`yjM6?#
zK{*GNUo1KuRU;t~by77@gzup0#ZdIQsOHm@x~i7bTG~x@VgQovswOimd8l@-1o2eG
z6##HVHS{Dzj;dB~frz(iHWknLsJ2{#h_7mi1e~AhWBLjGRX<fgGC;NEzrVUUu3AOs
zZ~|4{ba|anJ@F;{4pObAtU<79{(Rs=RL_(_<fN*Q5|E*)eO}<gR6MFsJEgJ?Lo!^|
z{SM%#Rlm1`oKbyVgb_xl;!dFNtja<!=yR$&VkkSWdVd%CB2|xv(M}>t^}qje!K&z;
z&=#ZGK{Yb5s&}X$_kwCsKb(nEwS53J7gbNI(HO7#s1GI*RR3%PcS%+L4Y)+rrf%p?
zQngY-JX!T|AskInouKGZs_Li~6O^W^r09FPYF8a}W~jU$ornAHifSu`6th%TS~y-+
zaj4=lTea>BkQ~*PRnVQQYK{Y!rxGSZX}&7uBpkh_+FS!tpsLS=$aU2vT2>XR%(ToX
zQmxj46sxN1L2jt_aRDz;8IxhRRJDi#)@6{Sj6%8UXC;PKp*sF8bXTfYr$K3zDwG!Q
z)vBN{0BclUA>is%VN|(TugdxaA`L3hDc~Aax37TQQvFVkyCzj9m4h{_BFbQ*MWvcS
z<89URqZnYjiZcUeI#fAyF!_#Z)**=4`&EmVLHB)C{~VA3)ul&(A67Y0igiRKpojef
z)ipX@Gpd@Xfu)D4a0(!gsnVVUH>uh~b@5ZGV^4!jtD<RW4(jLWh=QZ~%NL-<NiCt!
z+W~bX9W-)QhirwigX&l4A%E1ao}zWaF|{BQ_mP+Sxp!gSTb)k_j(pS)(qYM0t@s&z
ze(GKynDAF~D7p}!UQ083TwVDXBm>pz6X-jkw$RQtNZm`@-C*^0I*}ZruBNFBRU7EK
z2vg6xhTq_nnnm%8aJ4;#iV{w%Uup+?M*S&0Z_cSRjsbXH{bvUHBGq;O?c~)@b->YR
zHG{%NG3pAcIgC}`&cm24sJYhxk5kJo0dP^hQw(^#+IA9s3F_aU19wTi=RJrds+ar<
zktFq!|Di8g{j9wiPNk?vKZV_N^`HQvnd)0r;I62*Z3M|uzc7VKysCcuPjK1lV;unI
zs2hL5B;=~Ur6T`4b>D|jny-Fr81QTA5K6fhsKbuJ(d%j><@gKL4Zi|cq)w&pdK9a*
z>jAi-{=k_kQ%lrJ+6a}ZHS2&cQ_nYpD_1Y9LSKdYDCIh<)jx-U+)_`_0=r3FJQt&H
zR_9X1K#SVxFAVLrIynvSR&^X5*lSliZAM>*dYqDPchtxJhWSqQ*A&j^QXlyMq+7j9
zK<~dEbucYA?y6Ti0nw-Sq3HiTb-pVQ{c2BI?cY~lrMVnXe|Qn*2i1B?Xb-8`MHt1f
z`uP9g+KBqfVQ>%BI$Cazs@->DX2#TRbjOXW7t>2(LM{IteUoY_mEBFLx3DOhGOd1s
ze49~!@fXN`P2r#DbkO{ih0!}|ZtH<}(zNUa@PJ11FB+XS<#*u4LCxA8D0R{3_rQBs
z%>Z3xZklL+NV;n(DKFuv*-6!>M>W19P<>4E%wrg!mxfE{XuLI|{b;oNXgVuk&{y-n
zbchCM@)|Ih;~G6>9RfAwOz1wLnOTOuAkC6g0E0E>`5+-07m973)X3?k4Arb&4lSoN
zJ1H_7u9<ZgBBwQ;flziv<M}z@5t^=LFn?Baa}sW!(|kcI>+^Qa#&D>K)J*S%nkbF)
z>p(<nzMKs;F`5-7kPDi1^rVQ>h-iW@YI-eD6R&xbKI4#}`H8kei5iz?C{5D*R0c1S
zHB~84mZEtw86v5gf6fD!rU`8Wm##TV_AYDGls?MT*mD~&ZC5m&LbPUSUi}1Wu4<&8
z!MAM9=zjF&X!__&a0Qydw=oyjHDh$7u~1V>cY2W~f}$G5nz&i$E745TYrj-e*@V6_
zjg1Z+S8CoRc$FrSYJ#dYfpoN}MsthyShboKI~_T#)97x%ZoP&>M~WLXOBhhoq*?Sj
z`kFN>O&Cmz=H4{y-q!R|u&!0}&s6~0H0|^^v+bG#ze4hkhC$VIotg_&ZQiBXTZz7I
zO%w%HdNk9tXuqp@ik@h_n(ARF>(i{-Mfcx5jgs<D0~!xXvJPsTi=bvm^QZ!9hBe7H
z=pNC;wxjQXW{fsD4>h70h>U4|q}qgW&1cIXGND-_#sp7lZf%0@8I3F(lKZvq{kMD7
z_EVt8Q9H<o_fFbwic25R9`>P(-a+kW3n1#EO$-2W)sFT-)J>aCAq#h{_6$T1YukF@
zsHe6e9wv@xw~Ar@sP;e_M2=~@C^zM$?d|~FTl>WO;C!_2R6@jG`)(u}1GL*IQgU1y
zMO&Ug?RDC|ozUhip!+Xa`}h$cLbQHYKu&7QC{h}xt$YsSJ*EA&3^Nn1ebx;>*J<tc
z4KRO3TUZ4(5!#T~(RWV!8J!zCuT7W(gOS>~^lpsO8t8aQwDwUfap%Qo_tDe+g7zA{
z>Eg7$u4ufdeUUcw_INEP8zW56&Z7BB(w_egv!1MtH$qK{cF%H5aH{rA5=qnk`X2D<
z+8(l-p|zichnKZJl)TB*%Bd*miuQR55@u;_58%vIZB{r)wst+OI&!pKR1BW0<zIxM
zJZ;x%^yS;NZdRDMrgfoU>UC{a4*V|E`q3|1q%Hdpo)&9gqkZxX?UHP$DbXrJ(O0Vd
z#trx~?YEymTe)^41yw4vE23b&QaeI<iz;o-Ht4L@cGLQ?M$2x2NUb(=AGn*^jkK+)
z)7ndEBUZ1S|1Q)tXdh7JXrnfRYC>*lk5P$iv-Ud*RkmpRvN8JG+Wjw~uT|SXNt8CN
z8@-&`wF6}seTSC$Ir{EsjZ`nvsWpBAc$YS91gg8WJE=aZNBcabAMR=wg#gg2E&8z&
zL+jJl6{7W?_V%+N{n`&`NpN4gjB<2?+KE;GhqQt8k{Q<iq($GTwutsx54AUPLB_PN
zM}drMmwbc~PH4U8@jR)ueGRv#w0kIwIjwE;&ss41Mf-pm_8fItRDI;6`;6|i1G+CL
zrs=GkdK8TZb!Ale;G!F*E7w&Q<Ay#rUDDU^*IidLj8S{&;)j4cq}yx(cUYH}2ArqP
zozmP#bbQ(>9o3b80OybCM)YvPOUI;_gST$IT?c1;bOC4KsIN}e0nSf%yb9X<b?)?I
z2k36mDTL#?&~R{px^uMZKA~%&MN5#*Q4KGGbstW{rx0Be6<43sS$hBo)xACd60TFx
zEBUnUAw?R`=)@H7jL>~XF`%=$(zj_(dQSIC3S2y|%XkMQQm1_k=A(4+x4^~dJm?t~
ztNZ6H$OYXaw3A5Co%Vv=OS<MC;7p=!A#K)^bRGj3VX|(?au`g}6%?T_RkxLP`Dwae
z|ADe}U2G!kW$2nIlyq6=!lEM0Or0-%W#EeL<-O?4(&Yr8^Qz9{6>!<QO%hC0j_%kl
z*v-{Neh8AM+nfs%`MOKAbh@V7N2j_AbZok0uIqNYgB0o(^+2*n_c2{^#k#zU5V@f%
zC<dTJcOw?AmFo85^@oFCI!6Phtz5Ta6o?94+<I`8ItQA)D&0oPOjhf@qP1y_?ydbG
zwYo=W>wi=C3grgsbl)?ftzLKYIJgF#dOL89x?ux`eM|Q$Es2|Shi5^gS$EPGUbN`?
zKSked-3Xm1w72To=>}-ixldrA?K&|<OgePmJOY_Jy1*v@?9{EH0DPA&HU(U_?vf`Q
z?a`g07}8zcs-=+Z)iG%8(Wl$xjq%>oz56oU?$`A!hQa%~$-CeNbkWzr4eD}f%`&9x
z$O2&4u3Od$hevcLo&|ZJ>uAFWM|Ih>iyYSlQ+dmT?vLN#;iOIx1Tv*t<O>tix|LKH
zGo!0r2&Mb=#}A^>L9eHTtfT&~m*An3ei^-C59nR#`Q)tMa1Zc<dgWHQ?V^uxfTXM5
z{sW~Q-SmxgVYurVW8ggWDdj*M(ytRi_hG%At`<){gD$osdZ#ZSa#TOR1RfsKyHGsb
zOCNX@&UouD?}R}g{mO8R&{y9@DGfjUbx%n8>;L)}76SBLvoWOO`gK&%6{uI(7egjk
z|25Ucgz7(~@`*70I$F%0(tjTX-QoH!dU~AJe@Hb^XY{TVTZzzT($ns&{#jaroYVJp
z!o+#KiqgrEde<G$5~X*f7<;sSl5XD^{a2Cbi`B1r1dd+N+dTk}(?=ChhW?_SF%Hpq
zy~`TNB<Po3fs2>)`-Esr)GwsaXp;WJ`Djem&!?+9MPEh55~=!yH(@tTulfr9rt7mg
z0A%RfYT(ml{TSuVGxff&0(V7kD?nqGe%3o^ysFQC4vpFR{$q3yEJxp!i_TpA$2_#=
z=}U^CG+#eRkM(Q%&2Pft0{zqPLFBsrhj)Q5)JJr|iz5Ak4>8bU{apz}Zs_;pT;;qH
zeNzJFxm0f#fRyR48Q@yE{vWFUtkCb?4M3&-T@AEU>EB;O!P{zmFWntA`nTL*w^sid
z55SxHw`Rjcoj&e3@b!A_YK*r*|I%jkwdk8CVX0NGq>xgZ{wYWFwd+?}0qD?gqT>*E
z^eMAoqElZ-%fK#uk`yEB)=xb|UyuG>0VMD1-6NsJKB(V9SN@Pbz8{ET{lbfo8Pz}O
zf-ybRCs5RPOdm!oigA77CYYblr~M0&N&RpyxGDXl7y734{cAyH^qc9Kz26{^0`6e&
zl7n+JI8kuI$uLc8hXV$`77WSRpoxbU2knMMrJyc`jr*X~)zC?sb~l3;Z7<vnRqtVF
z9)?dTxqQelP9-~s4TH2y@ie?W0&PbOFHnieQNv=2L?1I$)Pr~#2EGK`+pwwu#K#a=
zj7DF>{hy%4&mftL;rbi2BESO-_77IU#BsxKw?P68M`>s$3{I4|4l;y9!(gys{sa&q
zhKNd7I%yD5_$AcfZ-CM;gZfvHQ-+iu&=_vm_}?zWFk1!gjA8zH%xHumg9?Yv8vdPw
z#&d>?Jg7cz2w917MjA%!UxG#%@)p3;Xv5l{Kw=DubbvJ0P(}Cl1w-Pe@F~ua<OTdi
z!^)4)7;jidE4~Cn4^>@VG9*QzFVXPe9rPs`%$LxYYzV&xT#6yu2rp6%oK$dWhTp%!
zB%~YCD6pGpNaazu_ljZG9&~0IMp;mE)euE>*x82mgBX2|Vb~QSxdu1dHRl-)e+Q9#
z!x=k9am}EOgh+uQXdxP}8)}CkQfTm^Qy@i#xmt{@*w9MV_BRaUiLg*&cyl5AEj9eQ
z81OQ~hJ{by{wp{5&WFJY!<?VtTczR5ad1@z;}RgM4R)&9sxgeFK~1gU+X|4IhE6RE
z))~G!h`xHmpMFr<VEErvm~S*>G(+T;A#^MHnhZbbF&E8-J9JjM#W1FX$Zf+nwdiX#
z6d>JUpVwwMp9q8PhL7mg(P>Eg1ip0{R=on5Zo`YuqOZp=It!C<*YMLb5a~5=C?(lv
zXrRisdj<~^MEVW3Y|O=dLsb#D0mGWT;06sLW=IYhMqYr<VZ)mgx*jo<QQ+c%;qNv~
zkbTtfbvV>KH0+rJ(J{kZD)S#V+@jd?gh90uqLYS@7$}`G^xlFO(}p`DNX{6d_hK;n
zjX@8g#=)o!LZhQG>m`Ud8NcvD;{oHP`B3I;ym=Q|4jT1;!wVN<)&J1wYWyM=#LaG8
zz6qAxjZu^%@Gu^xc<mu$`TwBiurZTL7(9&|mxDWE9PWm}qsDdzSUP6hL16(eV>p$s
zcpDA(q1(sUejh)KuTjGX&d<mlf@FZP`Uv31jceY4NT9Ki7BnY}ezd_1GTM(Og9aOq
z&?`E`xO5{rPZ|%M1|rnhMd|Y}<6|_Xr;Kt+3WOW)o<rklqaTIG&KPG?k}1O2z7FK9
zanTuQIcE$JL*%^iL?E<88y!A|-5BFPelQektT+yTFBmsG1Cco6JUf-cUNnxSz|(l+
zb}E8QFot<U=8|!Yp1sM&q@w_)7*F_Pf>Mo}3n7_d+(5g?%f|OF!?jGK<uUYKF@8$d
zah9>?8*o>RyJ-%yjTb2vn`2B*L0_(M(JbKdjI$_=k#8K|L<{X}#y(dJroi~Z6r8$l
zJh2p_g~nh?p%xh@yFiMKrz>FhhLKGx`VwP79Jo^B0LowHl^NH~hSGB53-oTSFnX8(
zs5E{=aoQ^5EB)ZAjjwKig&N~|N`uuJ-}nrYH;wVzsd%T($oLj)y)icgG7ZM0w?P_>
zc|XFnTgI2D45i7qunXFnjX|`VYcZao%EjBpVlGIlakT@Kwi%;7!K}3#Pi+I~F#7ET
z;Er+hYrs2=d6by!GA`%fr|32g(EF>$=(d#p8Tqa;>;}~I8WXlarq38gUy8VA<V}O?
zH@dHe!TZK!F35m!-UyTq8duVx@F8RBtB@QvhW?AW7%}?L3*>>Zlrl-9#<w=Y?nC1p
zHE?6beH0ZOH~#qrMmAwwVL;!cv578H`;<{dsl{pIE!tzv7}rqg#D3F1&Cup#`XwL0
z113Qjh_lIy0uTpHH&l>xF>PUhb2W`N!3#Ij?MP^IH!VoQbbFZopy%8nlPevcI&6BH
zYRWuKPxpg6V#=XK)=^V;540S!n|^kHsF&$DC7HcV+vqE1KBmo!pvKoUNr6j0Q#~#D
z{7swaSrlNZ_zjZBO$*(@1)5e<yyt|;?N2lYneyiX7i=1)m0O5u8{L~HO^!l{gqr*)
zuNr0=*bI?VrpyQMDcocq_zvbzo8CE(&NHStR23OvdL<V4v!)DM%A7M99s+UR<o6f)
zqD`KM0f;dzpjT|H$(^Em7fi_qFo$ubu6N<+MN{;%7-76=)C*jKso@H^OQsD^!C;ap
z>kl+0n=<K*lVUnz{{+BP(~Gp8OEW#B<0=`ZRTDs5HvN?VM5gK89GJgi`rV4YEK@V(
zudkX;Q`9NfwC{6><e8pHfYN+ZG@anSX7Y9cS74G-rPp;+CKYECn#vc$?IP2$&){#d
z>Gszc*$vYh-ge+iOhK>0V5#Zk3INMY9dsX*n?4(bi3-yrt-x2BnklqeW%8ozf3-<L
zk~Jphg>bFb^b6%FZ<-G60as`GAFZ<LO)hlaxWN>&8WtK&8{(ntmT4hndzwtKZ=tc-
zH0Qybr*J!&g0{f7+ooxM@tfF@=LAAqm&uvxlDbWMGlA$aJ+T7j@0z?00oZH$&I~}G
zsd5pxd!~OHV7K3-p^V#o(^}fE4w!}y!_h(0#+y(!Vwyuw*$1XKC{#FVdWlvP4^5Ga
z0UtBv&{)Pz=AHN@CQR*i9Y#NCil%aqDbrgY12}E^<0rU3V|t%rN&C$Ww61bAS3C(1
zoy>n{18~6XHv|!9vvMZ@2hAV-4iheB@BfaAnL7lqbj<t#)wy|@A5c}fw^?%z27S!R
zWSI9g?|vFO1I$xV^h7*v&Ta)h(CoGox=)zjx{uBv^Pn1{!RG2Qa3N+{43wTUKW;!{
zsQD<R7Q@VsQ-tP}c|$9>a5Fm_T27mPq!R^a%nR?JF~Yod0VXfb%;*RFqWR5-;1bMl
z+`?EcnTvK&0xZ$&&<#YA+4)6SN;a>U1CnB1`6hIyV%SicX7;&*QKXv-uR=1ztlR^U
z%jRS%l*u%2WkBSL`99)#^Rmn#RBv|Gyqlu0+2-c|@)hPYw9Cjf7o=lK^33<VpgQ0D
z*ADtL^))lE5>6GEFH?5<x_LALorUHMC*X_Bub)I;vDx`A*u7ycdmg$=%s!OREj2ql
zKx3IXy$MRo&7<UKg?TxJw=2!n^pveKFSv@nYV)JZ;98A&J2_Kp{`@KQ-84&ScVn+J
z`;3FFHxKnfw86ZNBD+oIeYBoyHoskh#ul^rD~Q}Sn|v{et>*P^aIMW8`V>gJ`THa^
zc9^60!TURA?|o?OH2?80W~R%$nRe9O<~JxW)MNH#g4{Jf-ipRvGro$6tJ-dkl*8aX
z^Vg?gu;1)C0897H`zU)kV7|Ek106K$pU2fXWS0LAjl<@t8sJCFuSNj(!2A~N??=tM
zen#Izv+NakF=ig2qM>oKz6j%;Ft48nz@+(oXPBQdv*?pd)8=Pr7dd0L|EvLUzom8=
zS{*FHUm)XXnb-rolV#5y01sF$Q-;IY@(op!9JFNc;Gv7f)eDX87DgdP;bGa{3@;8@
z+SdVh*uoD1&ePIO&-x=4&d(4zYFQElgU2k(-vIHlygds5Z%dMWJrF(?)_Z96wM<d<
znx7?+s_XqN_o-|kz;csH8ID`(Oc+d{WmY^IPgq))fCO1u>9-HII8up9h-LUKNS?HO
zLz%u%%ST?&5@uQV8@xDWiCzkS!!7@u2kx{bpF)&pECH3YvX8JldjWROT6S14-RCT4
zPeSIr<pRZoA}tx4AQELsd>4(;mY*rQ9%Csw3CUPX&|;XlU|Agk-Eo$tESSG&Sw`8Z
zc+0c@qA|g;aTCZTODFAK6D>coK$0vUErHHt%l6mk{!6hW&=HqZOEB#d(kz|bz^7ZD
zqOySu%iuP+cG)sc_0O4>B04;M#o|HbwON+gG$mIpqhv7KlKDK$=U5)6lg+u7H|cGd
zXIVZ5c)o>W1G#2td<sJ<u=wi1UAOEAdScc)^9n74r=YFKvX{=^7h8_dk*gb)p}%0h
z%(9qbZ<UtM{0COxVcq>HOw?LZgQ4c8#dQcK>MS+i09S8W(GIS`lJX<WH(F9?XMD@D
zwF|S>WO3|;NVDY<Jv~}18B|zs+fqOUMXi=XXGpeLS}8-{ZYi3Dz7EUidMLYNX{10+
zr{(ApOmml|z)ty@ZcF(FAbKpl6e7KA`DGHKy_WCkUt9YuU9@(&XDLm97yXuR{(-^!
zmd`(hr2)(RCm=FtX&nPMWLbI^+_2@_Qou(nDObQfuxt+jH)>JUL-j*T2t}F4ESYpL
zZrmasr-$`~<?D3FOj_a}hlwf6`?UC&w#-xkF=KI{UFd%6?Yoe4unu>^Z%6BFidj2b
zBOisfgVt{sfw)-H=qQ`3m45?$ZdOqsh`aS=DoHzR{hk(np4NB@E*`PQcB9YBy8S3+
zOTDd|=)kd$HDf)d)Ys~E8ruA<mQl=%zttfIeSy~8Z{XSqt9=4okkx~p7s1vqC}I*~
zbyk9$v~GAFx<jpHry&_;eUVm-r>ySu1P`|k)2Gx<TMw+n$j(?Ve*lpPs{@Ow70z1s
zW`I3s^)^GzdFxM7h(=l^atu4lI=2)`qpk0~jM2wf3p;?1wJPbRx?o+I4c&3p4;#T<
zw2BwNV7yiN8%Ton?+D;7Sv{zRG|^i18ZNRV>nZvPldWITdo#uQJWYZ<)%uhPGHKRA
zTAig^mlQxW!&*#hz01~{(HLl^_13d!ykcE{8;C5c;tt4F>-Rn&+1B+!kR0nVdV1tq
z*V8jB&${{;8uP8ne7JVaYP*BR0_(vg7}<3zgI*wo)}11dBD=Mko|eT{4MmS`SVO5w
zsl@6^w?nCQ@pW)z*5+Fv<<^5#*i&JRKZ(9dD{nhYR9P!;09S226OW<QSU;s0a;<f&
z10pxA|5l@~&bs$wOl7?_wGQwG>#Q5F*J!OWqVbm1Zv7j6w^(IVp?2F^M0tQ#>+hcc
z*k<KX@VVXUaSYd7ht<CX_&e5v^Dq~kR!90Nx~w+R-EDoh2wHlq&Gg}kyVgls!t`3d
zS%mTSSqFZCvU}FZP$=uST71!X-#VKDhyzxsT?T`L*0)kXhOBcaWIt^ElRkYlVqHTO
z2@kAYl!hC%4$*t)p>+$bv&XDX?jYmVS{V#ZSnu8iZqnL)6OvQb*J(F4ZQXwWeKXb_
z<G}5=HO+%h4z`|o@Ym6{<sw9!Y<r?8TYA9uJw5fDZJG|)J!o4_dtn#bTl76gSKA9`
zVad(bw+sk(+rM$>^RVT=jJ`v*9TXTlY>S`}n5RudUvfKQ<4~sisBI-30zGCE1%dOj
zjW2>BZ`)c5qxjfn_JH`>j*L;Z)X(Ob2~mIBKrtpUz~=E4oH=guryW6{t!)hCgw1Ob
zh#*@uy+wm<U9ZDnh;4rhxRW*m1I~onwkM!5%yu*s%1+t%{?HO``-?Js5w>v(V4Ssm
zNt^X^wqjc5N7*if)BP81`(+yV7+W$u1LJI)=w*J<c0Ck+$J=&M^f$rwCT%7!*_`N+
zmT3E)J_?g!d#xKYlWJ?ygG;mdQ&CsC&54%z88!`NWG>qjwBpOOsVJv+#rDSmkSv=E
zJzlTcvL!HN&$jsp;c$-4kE(2QZJK{T@@&1dm(92BuSefC+XJfHD6s9OYS-(wXX)xL
zw5?48zR0Gamuayrg_2}9Y_XKhF0s8wFZfbhpa_#!W}E55=*w++6o0I+t(yxkDs5N3
zhe(y(cBcZJ)wZuFXjWr8LQ$Mrn*$w4ziB%@g2p<V`^P}k+f-%fYp~6t^;Dxxn+e=4
zTQDV%n`}#|wzApgN!L}2tvDQgZML8gc;9ZzqnBZa&2cGo-m#rkgLK*=ec^VO&Hf4P
zfVyp=Yth<c`-sAzcWr4M@U++FMUSmMo4+H-J=?m67<RucMgzco+fV^q8?c2OgWW+}
zC>^LBvQ3E~Ic)oaw!0&?PpR*LZ4O<XqqZKZEq-Xr`Re~1U3XlRM-xs_(~Kq>jftjN
z(qoD-v80)3dQ9@g>%I4Wq?nikM2dh&6QoFyqBQAMItqw@Vxx+Hf`TGVL22JJ`D=bV
zJM+x!-dlEOX5WMQy&X>kLGu2N#g2G%PVT6Z1AA)6&$j_Hy~FSmuxECtsQ}A`vFZv$
zT^YMCfb3?(zXfb}M*I~F)Ppg96F@x~jwmR2F;>10?7fV(qv-Qyc#pum593}WP<$D)
zGKlPB{52oMk1;+7=6=SyM;wsxXMFYq>;^ENFydzpWK7X{i6F*2T0aIe&No2x03*%;
zW(eao3rHwqE<M5zG7P_ggfVV*!(b$1&32eS#MtKv%qYeedtfP=aYGN07{(F>pko>O
z$1u*rjOJgV5XWFL>HdpnSd$==zzBZ@BTQucdlt?dVf>K?n4^rp-vl#>k+}x?$&6ie
zs3(PCqlITGL;VIs(ioGJ2RO#SErR=pabY7o%wXK4@J%K|J`Kq%2Ah`a*^DY@h~zMI
z@zBd<Jc36O&R#LbN1&h2NQnfufN?_w{X#}2MbL{FVU+AT&Y1HM>=rZb2STKTk$wUG
zmNJTHD^SMhq=<4k!`U0m3I?AZ8<mV{DNw2yErS^73C1w(^iDDozk;D^Mr;vUHH<AM
z0OqJ=w6y{I6r<-mbk;LYQPlVh<9IPZ&oZ9f2#1>(=jjb_j&YbyBcErOzJ!SjjD9ni
z7a7Z&Fv3d=%@Q!18Bfu>v4!#BR`j(q<g|q8U?`}P=rSXMlBb;v&t+g<VFccX`7Q^;
zpDLca8CBmwriZbZ4VbHp(!2Qat}#w~0Q)*4gI-5B7+tii>u2zOg2FAvo9^fvWcX33
z$8E-AR68`n*t`)YMj4XlK*kupUqEu4!KWis6O0EI0OcOzmjQS<#khA8ebWrbISLfb
zFcMTib78KguNb&8AKn9Jb~6`uK-8V7Y{Xo8FvE6Xf;^ed9%y+pB~-2M!yKTKKEBM}
z$6#<jlSc;|{h7s2!(afjaTI;Q%-p4rJivVQDL{uXIrOj%W3trf3uh)ct^+NCnMWz8
zDCTA=>4|2(VuVHvbL}_Kh+}?9+2wfVcT>PlV5U5ZQ5<EuHNlxA=6xPWGIJ{x+omy(
zOu~y}OgVjsBAw~uiB=Xf$_%}1=I!M`$zk4o1q%7hMUSAbfO%*wrSA)wAylAK%(Rq1
zv4nXx8EB<UeK?${V4AYgs${BG!NV%%GqmKZX68}^y@q+4PCeB!5B_(wftgMf{}-4s
zHt1bsZlI_9C8n76EX~YvI;GXZ)CYmt&RqH{%yuxV=F{1a%S@#wG&-5@Q!?ZVGxi-g
z+{GNZ0MgCW?E~py7SbZ(Dsu^CL9Q|P{{i#8%xYJ(`k3zPpnii{T!U6WbI1V60VZ=Z
z?A~O)P9K-N#q{vNux~T(&c`5zn7&l9G0fx_Q?Ou!*?$=tqs#}j;EpkqmP2uzxl;%-
z!F*x}p!b+r|3ZI?`5b*`ahkb<2ZJ+A%ZnI=Gpns0dM>P>HSo!m^%12_cC!vqCdiF7
z`YDF(&T^jy(}T5<-t(TUF&dy3E0e$+ds%gxq3F%}ouW@ZtdS59Uslda=<j0{Q^}(r
zOXdr*pLK98yzpoJyB;C|taBRx8p!&X4VWNS{S#mYvyQgIwF4}B3haik9v6ayvW8rs
zevq|x5&FVd3->@Wl9fW&%pnKsrL!;}#R{Q>M=UF75GD?@tn;B5$C~pBJWXW9eF;lP
zSgJtiA7%Zj0a^-+H;BGe)`>M3eH!cc_kohZir5CXGg-@N`I^NtP#!Ip^>s7!@>mPM
z07^c~Oi!O8R%-_Oj<XyQhoDi+T5}3AWvoXi5?9W8pFV(D!3x`jp`BnY4F~o~Rt4Sn
z)vVweNY=0($AIV7vN{%kd5ZOv8qU<Q?&$$`npIA>cs<J}9F`hbOX<W+BkR>I06W9#
z_#eDzV*R5)-#ONo4qv!&o|QtWs|&0H^FS`L7Sk7VF0p2nP;6%Pxj?j)WetNDZLEq}
zm}qAu{10Aqur5)C<TC3xMesUV9NMZ~VeO#|Wf$wzr;zMssgA)y4{Kv56t1#9q2XR*
z9r6ab&T3jt_umaxIeliUpC$PP!@k9;qvi7;Ya=ZJZnM^pfH}n4K&!%G){WI5BdqVK
z1Zk8t`U*tGSfAg47k5~FTfw}`dUY`r##yr;fK0G5Y#{eouTi<&eb$pov?f{gluDgq
z6;4t5Vw$x-7Vgimgnxm|vVNf=9%r_mi&40+&$fcNvY(|&+THAz9!H-WJCL>#d)R%C
z!%=tkmPgR%!TxjsKt0*Z==bqr$8bRQvd?@9NpCja4=6tD9`eGMZKe$UK6d_tl)ms|
z|LKd){p?-U@Xen+@&rf#TiyoHK=vOk7;g}}pa>el>;-Rw9ALX7049X}5G4~s*^g6d
z<RJT>MVN#z_O>Ii8_uqy=w1X{O9eiWZ0``v%prCxrP!m`2kE|zW=GSZZbuBe?mLVk
zmi@U6poiIJ+S<mkJAX%KJUc!Ctps+o1||~OlN4w=!v2>6@kiNn=!KcYj^6=;$?TGa
zV5YDaH-nkVj;C`pY3!|ZX7U)jimLq5*=s4lo57a74U|mwQhI@8IoLwla%Hn0aR*Eu
z`yEPT<+Gh^AO-BQ7{C;=EmYuB#Eve2`^VV|a<rJ;H4oS&?9};CFJ<%S#w%ls%OF|K
ze)M1XTfzP_3z(JcS7|F<#qN9<A}83%*+4nTo;L*bYPMreCcLR(U!y2cE&J6ebe>{2
zQT0z9+vtqG)9mGR#=D;VZYD?rJMuJ`jqLY1uzQA`#RlkEb{R#8n%I2$CC{-JevhG@
zXOB_L-~wB52F#1>8?@iO#LgT?Uo)FS*F_7v*+CQ4%I;kSv^Mq&cY)T<E}`6S2m5_5
z_;iK+o*p7y?4@))ce6`rU(>@rMFlTc+0!8~agE)P4`wgh<1Rq^*ehRw<aKuTJoMdQ
zKe`)|{p|5jFbCLebaCHgzxW*_Z?WGVcR+EF{URmDZ?lIfr!vHTV=cTGW<THt(Gm7H
zKf~`)b{l0s$JpLuVBTSG@rP@7*}GhzFwPFS3=b#Rq1Vy6$NrkqrT5tbRM9%gHmEV9
zQ|z6;Vb-SE?|lsQ8TOnNAhYbyBns9!b8c;gK^IQ2ADnXKaOp?i&0+ii4L8o}S+w?W
zIw|Ae&gtyLC_Fe_bP&dqQ$`sFFOCa6!}f9xi=pn#IeG#LKAg>YQ1Iof4uGY79N9H^
z;m2wG6wLjctZy+~e@+3?(T=$RoV**53FN%>ImQ&k=}&=7FlPy!ls&+?vjKe}oW&GJ
z4CUNThNA~LEUFU<<LEi?Fr4!^{RR=7g&r^w$w{N)g+rW8i0#ac;!II#Xf)@-QRu~R
zhIPP<<?Q_#t;3uH^tf`wasGV(G@jG%1rrGz-<v>7<cvNFm?X|K6s=3<yzl{-DV%=#
zDAh4e*<1`eo%7*Z_?yAGLrcYcj(;>nia1|A50vAac*?94b6zh6DdGH1JBd=xF!hyj
zo_`gX<(vg{Ggmk`Z`0w@N={N8Ku>TsQ;FM2&M&oav6?fK0{t3J{3QBnIhhn?KgFr|
z7Om49$rvQ-Ij=e}!Uj%R70fqsR@3>AGn_-Tt2)a$LAlo^ju#~}&T&>#+W$P~Q~GT0
z1&-n?Sh&b>$XuXtiL--p-OZe@=vy)^oPh;EYvqhlrDz+6`9GLw=iH$$3wLm&RJMJY
zlimQ*$?>A)!WGV$Xn=Nc#?#<oH)nG{NDn82a^zPzNhz>&jdK;}aOU=MUZ>4uALscP
z=w0V{IlLfxgOg2Lr<<HCN|)Z^ILASBkn`?EklUQz7`QgXc|Q|q!<@iLv_?2w%7=||
zlBb|B#(Db#{IGX8{6;YEat3~Z$T;Wb9QZWBnWoQf-Q#R)$H?w;BHqCyOmdv(gE_?s
z=y!lS%~|UMOEVnB9*|kiang6@zPb$tcXK-_#o@+1D}#wW+_PUm!JXUm82UW8zjnfe
zCwB!^9e8nF=Rk5V_x<(o$(vih8kT&xWt2qm<pxs*Y9IHlkD%wrRnv{WpZn<$z5o2V
zk1T<H09Sekih<mlOpqY%lFxu0%<VS<^Z@rEx;a9)Z%|kwlq+5jg@fFcbm@h0?co3o
z=VnqlW(3!h_9c;A3kB(;xgS$aTMYLB`ub@smvIeX@!X$&2T9<5znRKM6S?nEAxRR~
zJpnSw+%X;$Q@BNaz&^$;I|pVu_opJXGPrl?J(kT~PV40yZYiyobGd(w!eBmk|6Euq
z;0`|y^+IkQoiZunX3{p{ICsm(Kq=v-ynwz^?pn$KmvL`#Fo;(xxV02xspNjN2B1~k
zr|I`S!S$jtn3LQ~^mEm4FNXZ{*@Md+ue}112CjqFn2p?mAE1ARdw>#uP28DLICGA>
zgYu2%xi3-H^aA%8N(5izx>3CM5;x^@Fk88mTqv}0-E8opo%;oCt~$6&&cNPfu9-F~
zo!rN0>v4tqWiEb+E^f?XjHR0!>Y!(LKlg1~qz!PBPJrCxKJ?$Y2d?}Y6bHFZv<DyJ
z{yP`04RgCzpf$oxNyj9Nadq@@pmFZ_Kj@p_UZA(|J+7Dn%lEnO=b~?t`(6h6rno)v
zaCDmMIfd2?H<_wHXSusRrdWkDZw{^VU3j9WpyA5X|ALk~?>fDXJb3m^V0!ZQ(FNhf
z(~m%ZFE3aG_q};Jl%e$DT_1p5U*6ca(A&p5mWW9R<gHo(62x1y43fb-XR3}rz}rHZ
z*brXBMPP>Vc2v>#Fc0!luxXha#(Ry@rQy6?v_*{OU8f*@3~%>ZkXT+~0qh>;P0%Yg
zj^|tp?08-{EqD`n0j)5R$ZL>-9O30(!O&894_3h6G+s4jiH`9eehdcFd7pm_^BFv=
z5zb`twg=OH9%k{DoP=UFFZ&8Wb9gVz05qTX$sCXZ-hu@ng}h=afGpz0tOd+*UhHdt
zDdwH}2FwzkV>d)fd5=>;ZyB$<17PL6<!`|43f|cB=&R(-8w0b3x1K`5wY(7ejMpii
zA_1;B>UjI9s`)g}Nd~lf-X?koHSm^Dok1h7XAVHm@TzNpc7eB#Dg-X_R1`hB#CwpI
ze9gSZhcMn2-iN&aZRJ_p;9(o@Ps%s8^Nv=+L<jE&%7b<D9-@kb9-dbzz^?M1rSl!v
z9K5?I51HG`TSixYA8+3!cyXP#j|Xyt_XQ=#`+1wjfOebLL(C!G^OUF@=DidNOC!8)
zN`H*<n(x5vF`nyNP`JaZ{0@?Lc~dJv#(8hjTkt+_`6Fme@?=Ng(-e>OH58_Kj_=+D
z+6+(d3S?$^1C>B?=Kn;&Nf-X_l;Cvb|4Zq(-Tc?Nz;@$*wG(6yzc?Bqd-*TLqUFu^
zZH1l>|8v?*`tom4kZ>RW<^T-(@nb&21nuW<_lCdz{C8V07XkeCb+8x0f76kSVTbY?
z={a?f?-CERF#fhMXoU0KsTw<i?@nQ-NPaUd{txkw(uvh5{)Zbeia7pxy7c1tgLLU7
z@SEw<OXSxxL5}bTJE4A*-z*17;-5Yblw|%fCP)hZeh0uZ_)&5P+{omANHMT1{$tm{
z&E_AY1G72&SMI`6F8>7zQsnU;;sYk1|CJ}O3-}LYz~FKIUq_){%wN%uRtdkyioR0*
zq8=!e@qY}1dO81PH-J^}x6={3N`A!)AXR+#;~4G<e#UDQD?G{HbQ^Z7`JNPRKFxoM
z!V>j-mvew=;D1J!M<c(K2TN!8skDYT%YTeAjZOSL9GE!ApOXvFW_|>{>00=o?tw@v
zUu*<Q8~+O_B-;TEunvCsF#0a@liq}0C%+Kc569fA{EsMXe2rgi0k@Z*7DX2#--%91
zU+4dI44^mo@6mFjpMR(v`UCtVDy1Fb2d3bs9Ogev3&#<D#t_ITKZMc<WBiRQ*uBF~
zrLR`p<$KX`VVuAI6j1K-wG`-?<i{_>%s8g_RTRjW=IbehH^XOrhDn&^$IwpEL%?^1
z2~UCM2=u)K9oJ!EuV9Y}#9L5w0Wdy-r{xgw6})eR-F<?%W=Q%8Zbt!gzhD`~m;D8P
zRMizASU@F@fr87l=LiyT8=)8M5afgcCPeU05I{o(QafM{3a(P1H%#z>0s7$rSGwdQ
z1s?R6JtXj^616D7>4za1BZ$fYOswE0&GTVF0R?K~1P5r76EC<o2jqz0%Vz+6RKV#*
zUy>k(Uhv5Ru?Cna0>_VkgPST?LyNRD!Edw{KPK3$fnvHKh92RWf>c@@W(h_uAlU*N
zRS)C{Y_#dm6`X$^Bu|iV1A{0KtP?<_P;f;F^&&yn?|?ooU?>1xEO?G02ql7^&6ws=
z!HtvfsZ3DppyRXUg7vgys}Ou<$K+QEe)$+^Rf6ZDpnpQ3qwD#k;91%RRtxIra9oXG
ziUmuxf_F2ZeoC<T5L$JDh8BpN7Ce^*k$S=Eci?@4;5k~?Gzxz20rVL`JiW`$3FP&#
za9$9RPPys}0?X6ryeRm9N{25AW;@Z@EV%v%M$sx@Wuvc6(AR^3whJ<8H`gJ!yA*nt
z1#4)F*C|+{1ZbB)MLVZ%!Sib%(j%B?N9&rP*c)KIf?Ot;eS$|L;LLTwyO#ldLr|MY
z-)ZU>tlx)G3<#9(LFSg=FqIV#3ZzXK%xyvVUYH*eoT2B&u;Ah!5E&KtQX$5eApU8P
zJAzO5L*%YN^Arq@3r6X;pAg(zfJvAX99RauDZxKZ(3=+AqeRw>V8JgSvw~+31ai!E
z7DiA6!bP~l6`r~Z2X;YYx3GmWg>J%9dgJX81_z_hUC1a$pNH_xB~b7b>S*%4guPsd
z>=kaLn5wt1=~1+NgiAMKW_*QBJ<!`HJWdfFKVjA9z}zp)2!PxE!j5-A905XS319++
zUzy=>kZ_<GCW3|AzJ`edLRAz%Lxi8x=hZ`nuL}WlP?+2g>@eYiJdkkVriUOIAuKil
zB~rL{Bgi4)$KKG35|;nBU=^-^7gG`=tn!3~SmEE4n>#E#?Fnb%9KvY2SmTAmU&7M_
z;olT)P86R16rxGOtqWlySr|f_vlQVl9b`)tM*9FeO&Ca9+GE1FM<JOmv~0y-GK4GL
zfRZVE=oz473Gd#4UbgV-ZIH|nUg$+%u5gO7;d#Q3s7x<k=y>BKngzmDRB>4-tZxTe
zk?`U=C>|I7&;^)c;a@+auS7VghGePGiFQY2!ZbQ{RW964JCO?Es{7EZ6n;Q;YgIxX
z1sP5VuhMmKQrJZ$AJsxLogJ<bdMt()wZe}lfpSV%=b%Svolrp)I;Vx}Rzs#<D0>O!
z&j@|r1UV~IQT=9<5bC&dgsxA5oELU{3CRn>lLa6bg_>xfToMMhz*4htH3c<Wgezv?
zMXPY;N&IMS!d`duwF{jWL7_v)qDTH^;n7PDxY#LNO3S1x!YF$0b_we~fqu6z1)mX{
z+ar97exIwtjv)AbO}NYoX0LGi0Z8@<y|U2PFHFrwYd{!6l`=Pl#+M;-OW5)|Fb9RF
z>2)+DJV)hY!@{%UaArhUx)ZHYVeA+kwHp)4yMcX2*tHHY<HG0rp+6x^x)1$(!c|m|
ze_t3)!G=j;rUHIX31^>!$c!+7(o?g-I}}QG7G-#WxQfnDjAOSbax+?PqWX`Zw@37o
zA0*vHwUov16h#+-c!|a{=|9)@iaI{RBzTL`>80u;`tV~AUs2>y==+J@r7ZJ)QR`|L
z^cNj^9LxYw{v8Z7P*hEqSCD8Kg{uyTL=+(k5p9`)`B2eMRQD1g%BFo|q{ww66b^|b
zQRs^jJw@AuXwfr8z;wilw$cvwu;^MVu;WBOp8#6C=)pFOK0zd;g2Y785LJ2}5v`+_
zQ<6wX@8o3B$Ju~M5lxIiJympm1cOKuZ4HBZx@hMkP|px`)50-RbO8gMn<e`Bdnja!
zj`1+09Fc)`>$wh06ch_YOKH1YC`zR?ZIQ@A!Pw)Xl$W7cELzrpR;kEqBL-6@`sf*u
za*-$fz7?XKFTr4?Xvr)_UnNS<N8d?N3*D*JqQi6-*N7T3(W(`-QPt`x(Y-~mS0~Ds
zL%m+)c#J}L4WfQ2nvJ3sdI+5rJx@=)CJ~D&>&}Uss8r>==rsyiTo4seRplj7KsrdX
z=+!PrwupR)w2HK}|7#N!Qu?A@l=3~Cxh#654$z&VEEW2$h>APmXqPCRp2XdvryW#H
z)+73T5|*xs3Moa=E6RBhXnmqe3c(GCk~Tu|rs(BcP`o8lDd5GRXvITNxGhSq!ITb*
zo-Y8}h{#SWno&{w|3Jn>Kl}ldJEC_CXx$Y(cM2loB0ma4-V^a(#5nJZa$cuW=Sk77
z7eJ;&8@7NuEm}thEoMcF*218(_$MmAb`g(#054p{UoJyyxA<o|r0pjDl}5NnoJbjD
zPjNVvg?Ndz0T9_Meu&l?-r}|Ig7}EbXiMxXeq#V4`^1|*1Mw5T_b9#p_KTC_(CIH;
zdj`G*i09IiF;F~@3SWZ6zg0psSbUm}sT>gdSHZOqv6d=vL&c8EuzOIv>3J~2#Owx)
zH(dPs^Dr187M(yVQhZ;7AsrI0SON=C;{BBIjuxl<jlLN1gq`lcSn=2N-aRb-rUoQV
z{QW6l$BV0I1(qOwwFIJx;vhPTbwqre3$&x+tE=E>lKAfH_zjZ9byTvIBL0hR|5S0B
z2U=<3MYNPSCcZ%F>~!&p9_VF=SA7PBOtB{=6SKtce+)@SwwU)b(DKBU`=OC9KKczr
z3&h)~X!p4I4t*r3So|;jh9%;QlszdIYb!7p72?_bAeG`bM&R~I@zZqWR*QYE0JKJ2
z91Vp!arXnTbXt6PGc44LcfASoXT&KVpmkRKn*i!f4smP>rsjh9g?PYR6bI2u=92ir
zC(v&d|5x|fChnq|sdn+l??a?hJntCvuZY*K1zMLlk76s`VqePW^oX<Q5XV(<I4$z7
ziQk$7kzR4tOBh+7IHMdW*Twy`5W6A%BNHM6Vn;_j9KI>u^%k19#7ln#+MxIZ1>$du
z3+SCOELO^(I3muXC)=pl<w1asiPP5u^o}^RAI{trCktVBT-^T+z$V0ZDN}z>?2`nM
z`{F=73{HvzYJoW=uB1zSTKqUo-i%n|sE6pR*hP&_XUQTHOt?t4yazN_iTwg(_DI_4
z3uo?<+-n%Uhr~|nKu^i$+rajc{GmW=uVjG^lHQWD#~|q=dDslFeUd+Ek>)39qNUe<
z$!-n|`AfDvguVdDr*szwO4dF__g|1iSpyO*>7yGyRPuTcIuA;`X+;wzS$qx}k&;{Y
zAaY33^$7+OCD~2|iO~{YfAqyj9;fT#uw>Z;%*ROvDJmH+`R*_DB}kt57=4M7m*_oz
zMDke}T1O?z-^KuwB<t~iD7b<pn`!f&B4J#CMvi0?J*IOdE9s8QlRQWZ?R?1xH!$7;
z$<P+S6iULV9JxqxV*xB3myD{xES7AagI0;;UE0W$N`7U6lu6P9fl@AckD@pg64?~o
zu9W!G!?sG|f>LyRSxvIp3+7KsiWrcomi)L7iZzlfszj`nG<Lz6Qvk)4P$wC^2@|I!
z9}PpHUQ+ZOm<^I=4#UGn3GWaj&q#ix&u5;MJV-ZXlVpZIm2g2ap9(-ON`8)nqn9K<
z-U72#@-jV39Bq>BJ<w>E>@5bjLn5Gz-DSxKwb1XBeDNSGbxYo%>Z~5gc`A3fDhcQV
zxhDC02$H>$(GaNjNor{>u1gZ=J#<4Ns{nStB!jjf1CrIBqIFZ^5(x9RBx~NsBn(RC
zPos6)Au+W=V@UGxcMu(x)YgKGNPY<g=%{4>PPE1(YttZdN3yC3&fJx3N<!bbr0GHQ
zO-N4CI{%&|q86a{CEfiXlad3j=$n!RP^NHNVxbh$jAZ?43~*M`P6aQ{(iy7Ic9A-s
zYlPpf(g)<|+%5f+=EP0vxB!EDq$0Z2+@%3^u<Ie+`8AlHQU<N0yreBuEWB6xNIOh;
zOPhVc^pQT%0H&|hK<k@*(ox!b_)9-^2WEiuV+}+Cr57l$6(qe+weP{w2?wRj4@lFb
zzz&gqa}$c8QYUASgVNiSBny*f?ty5y^xuPUI6_+Z3?w6^U#*AUA?b!_n2(ZHP%<%E
zx{0cdVx)I}g{4@jt1rwSmI^8$87EzM5Ge7|Rm-8CDE(tMd^#c()=;kcsFYm`nIvi0
zKTu4Twy80RsnUOE(U&G2DuKo^=`Py5XG%{{tx1-&gPvvC(k=9h=18|$(aM$b<S>{g
z9o&x@&6m#7JE}msoD%MZ(lceyE0XT!L*ckIi4DnOY3-X7t1pq>dlaIj((m8J2+O3l
z^Dtj79SsAsLVB4>WGbcZbZ=Hk?;OAgPe@-X0`sKw^1mR}Qa-)*YoyM!537}iQf1I7
zX`l*{b<%xw>i@J<p8=72>BdS}XprXahZl{~RoG+UQxDQf+Af@x4z@$1N%{z_x6esk
zC`f-^y1N;D7o;ow&}x=uQ^ci3%KtCuElrYOXl>H+A~4&f0jVGz()l+bd0E=`CZ@Yn
zTCoPqE7G8R80?Z}(V4Ms=_fy6x~@tWKZq%DT$2V<uDe(IW;{9vrSejc+tSBVVRuLx
zM8TC|>6~J;Mx^d^gltrrMUrDuF-6PnNE=Ilc31k<29R-SH9aQpNq<$L@4j@^Z?HQl
zU6l*wlyv(qU`|U*%fXzHy3z5>S%=h@3O`+Bb7|}2D!V`rs@*aL?Wf#jAN9hLhpcoB
zn4YrfcC@@?OCCpSuj~Sy^YE6rx570anes)nd}TFsvFwvQ$^)jK%$LIB{<2D{`3;ac
zA|VneYihtCf@JxW91E5?R;R$y0huEgFd?$zZ@|Ps*-Mo83zJ=<D>z)Xs11q{vIR=`
z9Vt6Nk*z3M7KKQoWnUITJyzEK9YhYxz7D`t#>on(aye19X#>=c$S#xmQQ3BiRb<Lq
z4#7~C?92Vo%a$n|kHd`|**SVu=E}UM!OfHT(u1{7HcF?vi)5{z!kObTug9TSEDLOb
z`4U+KrI1QxU-N-oCQI1@gXOYu3Sn2swst|UQuYij<*Q^FmtgmV%%3VLs%5b#5S&{h
zYob_it?ZLpihrJxJ@gv9sFPibfM|ovd=srk+4uA|JR|%2C|YM_O|-FZl9kYV_nhn#
zE?VbhZnTZOAp7JK=v|a$QC#klENvJ3ZI-S07lUY#wa0+8$^t1v*(Q7GWvI8yJeuKQ
zhb;TQ|HHd1v%CfUP8pYWD_3NSaCCOb-ln}rw`^G=#@i!%jm}qImCbZQ|C;P0N)PwS
zDyHE@pDcPIu&>M3t$@f4+0_H+>zBQB2U9X2dy^g;H)YwCaP*cel$PX!vXo9RZ_5^^
zQv7pBCZiz#u<ZQ;z>LUV8VBg8tf?24#$-Rx2KkQc!RrvYD_dQTzHwOz6|7Cj(kX0o
zPnLBHBKKvFvjI9O%aX$GluWk}Zcodu?1tWqY?!tQv$97hcIGUf$U~p2TtZPC#~yju
z7IeDHed%ZRkYA@Ltf$<AVt!uo=AA&>D`(M(5^wpVXQ1IDkE1ZEue_rL=J&~u1OUxX
z{w{r>X1~0R%3b~CeUE_z$bS`s1j_xN0cN;-0sTx7asibbN6Krqpzn}F{$V=wqvRg@
zz>StqZNVhO$iwNUjFnGMVxWiR)92BOlP_5bk$Cw9S`#P8-=y0=QEsLb;SqTjRZ<+4
zxBdiwljIEAu_eo2q;O)2{8}>lQsuFK!^1SWiAsr%$#waVOqV<Unt}NY`4@*_DO3JG
z4|Hb9{XfLevgKxa{pQGrD?oDPH~OHTCx6QhgZXmDYP1UE8z}HuD1VKj)kX4oR7!MQ
zzDNU<V)<*7GAog9ngDdE{24hU%jDq{7%P`YP&rnGJi|fhlS=syv_Ytnr?Vk*LLL_c
zpH9lxQ7ElOo;d;RTDdb_UZ>=uRj^wpU-JO;PRq+bghIW1*%l}?$ZstIvr+C%<r!z>
z+uC5_to);IL7L>7DaChAp8F`&&&yR5owy|LSxvd>W_bxk09)jlPr^j2T&+N7n>;QU
zq+Q<M0f#%}0dK&I%ksHO45m}wNf*Qwxd&yUy5!+wV0O#J6dv!9ukeQ6Rr#~D6}Tp!
z+ym%dxr+8YeHbrLuFGG}0l6XPETaEu>6c%l6~cgg$2xFt%GYlLxh1csnCzgulQtc<
z<$qAtbx58-QR`uOxEQSw`6R_CN99(!W5(nRT8rP2TVIFWyYhJ-gN(~pd<Dq~x#Ve#
z{+_(94zAsoZ~OsdQZ7Qtq+{-s{Ld-O-n87i7cevOb7r(=<u}j33una-G+(<F+ftz6
zrdSyTm_3RJs!{P&+_(dSUJ7nFEbUd`Ws18(adrpDKE*yyc<-m^`wAla703<Xu23{Q
z31<Qn-}C}HP@&z5mLo`!OU2Q_iUL}Y9Z>v4%fS#u?`vp<Dtb3S^q``a>Z-yNTe1KX
zuK1fC_7Ms@)n7*{o~9-JAw>g){-P8~SHO%`Sm^SIQCy&eZmeP>#fuIr?$V1dPH}b?
z<BV5G=0GpOp}1IrF(oQyC~|T{anOcVvSR*vc#)#`i~`%Kil45)nRLZxbRaZCv4B>E
znTlU2^p~aRIgVDgVlL(8b1+aaa}|F+14r`|?>!4<zGA)~m<5Un0l*3sH567TQoLLZ
z%;O4&>~%DY6{oj@lqe3<8KY9g7TSlEDaI%nS*|Fivo942aW!Bn6)p5mu2L`};r<E5
z@8#$_sdys?%xXp4BXFihG5G>USgYvX46sv*8}yW}Q|xgDIjyLshkU)li=I;riY7-K
z?4DJ0F9ceXqJ#_XImIWZVg9^gd=|_L3NuwwTvXWgFwvqoLOYRG#SfGhZc{v$jn)kX
z+XG(oD;9hY^8<<qN}S(RB-7jMmSSHfCSg#~mk!L^ieIR7aY!Lfh2F4Y-FABajVOl5
z?@>h!)$5EY{3()mN5S-kiMxvTq9Ho2@Hz+gClqDm_dUf*s^_?`_}>O#PbwZgjxkLs
zexnz`w4yH#dd^B6RSUW(KTU*PSLJgd(A%xN69A^0vS$y-9_7Nj^r;nh<xV+dJd}x4
z!{n)qr7)Y9^4_ax?N!b{0oS~h?@-vvN7>yCNnd3tC5HAX&(rhKPx&*&qV_ANC{63H
ze0Bhi1}LvQ0cQf0fAfG6q%8jylEKQ)8__zTlu{BUMEUqViob*^bEt^npmLn*^um<e
zDS8#I{EI&N5utqC8?8v?@-nmzDZ}?dF-nO_KV0O>Nd`b;l%4+rGgdiu60O6^1K*$(
zr(8)n_IM?4BjzGOsic=$qO#@&ewZW5XK5pIRGD%WX5UFtE_w*q$;yBSpr4`~p@n*?
zQbM7cH02lc_&BEghN^JVmDwTAVjS=MfkJ=TO2uZlmZSWKHkG-`GoM2}PZ>dprF>=k
zJHRebE-nRFq0$@zQlzYKgQ4Tf*4N=hu`+2B)Jv3ud!bOO+!h6eGG&K9nB~fl4}e*r
zyh}ATmC7jEV^t|x6oomVOmPHZOed8d^c}ux<z*^QtWjP)2$)*s_Eun@QWh_RMxAm6
zl|`Obw$S|6E9cTn?Tm7gvI1w74V1iTQm(rQuye{+9)!Yq<*}`3T~L1fHpX&MIZU4w
zxugvC!f>0FU37k+MS197Dh_K^8Ysu!ru-lU+;-&`n}F7#H2#X2y{zQYa<EI8Gm5@$
z<+>Yiv_~1V5NKDGee}Y-rhJ|@=Do@->(IKPR4j%_zp`Qz)CZJ5y2Fb>Wm!F#x0P2Z
zv@@i9nd*o~mC_URb*?dG=n^#VDBq!n^<8CM4;&s>&V2)(PAE?<LhGLL@;|`7ul#|E
zjwY3IT4zrwcT&CSw6fz#xHhA#KMaLg<zrM|<g9x0bJ%rJMbS>eRdtQlTDw&oI%eXg
zs{Rr`jECwiL>wJ+Jyl+rQ1nuj(IePL#UFwfzN%TuckWaD@-_7RR9dPm*suEZD4g+E
z6|})%fU5gAECs5<X?qc*k}QHV!Kykg)DNgkRHhfA`ha53p{i$JLf=8v@r%F=Q`NMh
z6|P$GDtvN8sBRAdJ5sfVK133&O8gBbVpLA_(2P|jNr4@&nx$(!LG{;MkVKVj9{P@`
z0_||^sOs~F(MnReoIxvD<@+!cQdGCL!&0is=!_wysb0T^zGJFUiXfz`bU#8QLzS`#
zhB6(haSHNhsS2rzEnBs82~6auYL~*NT-A|8xLBZSqF`#F%DffhEmFOk0Feq++!q*H
zrRrD8o>ZwSs0QzZ%JpF|PpW>Ud{(tebryOxstOSd)~dwsLhqDn&)aaOPGzT@)oGRE
zsR4A>t44Q&G^n-;KpIukf5Xxl)z}9xe^%9T4A@PoU6CN?REwyr@uKQqdca&#327VG
ztlF3lW{XNk@5WY@?REInrh1;j)a|MjkHDu6RU5@(FRPxWTdYeZZ3O97z2rE6S?EzM
zr#$IZ6>}9FzNRXrpR!j~O?5YYsy}FguB)DnL+gf0{vaf8s>%$|yQPx;f`JaIhAAm=
zTjfDP>me2I1t<)w>?|-xR1H$NHmYKug26G>;0BCrT(yuENfWB3wGPmGs)g5}cwZGn
zrN@&hGu`P^D!+W_Ppi5LL1t8I|AgIH)jUccx~k{YLvOeGMS94)shRWvArEz_9DSbZ
zryqi(mzqJ<m_F)bci^b6dVq@2_NklLX!)yiXgd|4{`o4EYz3;_DfxOp{l*-0hNw3b
zgM_M|qF`URItu%mxe@B;>75#>KII03aq2ldD8#ExSJ6sP7i6H7sGf0x$Pu;t82mk|
zUOoVnB=tjT_>`<ZHxC9=)a*hqQ`K+K&NfXwgs78a?lJYw=OL4>e(Qb6WT?-EV)U76
zejm(dsr$-cK3mPD5KWGH^g}4-st;Sx%2P|;fx&#WBOm4q)WsClC{$0=&Z$Vv69e<O
zTJRiN#p>@?K%qpP=mCFA)r~~T)Ze}e1xLAhA`%W)s#nIKS*3Q2K;wk^3Prn5sxu#h
zPu1!qdR*41e|7`2R^3TK`cvxPDREGz);MrooK`ne<gi|S%N6Pk>gwfitx>&(>Q~OF
zk2nB*R=xXYs5hxCN+_IDr=|ntyh9!RFU((3pKAoSS^YHy##+?NXerUIW>f6DLmk-$
z(aY+8NU}?vL2K!5bv4y9_NWatXkAtR`XO4^)P3GS=~dTI0RD!0$9o|CYHcmR2Gk`K
zGZ<7~orH(C)!H4<8&W&mr05)0FAIckBkFm}pg*ckI|$}obvuRU#?@}mflR0~(m*EF
zqnWTYrH-Sd)3jPW1=pN4>uF3bnnWtZch$^P!qGjNm+6B??wa%sfcDVDx1;5$SxXO1
zFHLY9MD}Wg4vMe&YYq;fGeA>8iSt0sv6GMq(qvP4Vz6d~0?Y%NW3<u@(R9BA_d_*d
zC{3MvP?Jn~v@p#Zq!6xodm$z-LbEjntw>F(C!9H?iCzy6qcon+qc2*s>sL4vquK5b
z5~~>~q#gNTjWrsbaT<9mOvG!>=s*%Q&g)?!Q8REJeMdBpQ8@9aCg~OQC22nMf)~k}
zUnm@sqM7?398J|6nhQ&5nw(rPk7+(!2<UW89F=xwXjadMUZ!TN5`9^k7lY8s)<ir<
zpEt<Sls^G)ay2`e0Gg+Hst9QLnm|9G6=+Pc@S;#t6b|!68g(9+$2F6up<k?7Q3UJ~
z&2~C8R;uxyhF+P*wGt@hnlnFvS)oa$kyUD#bSkw<^Qs1|6Pf~gTAtMW<woznYRyJk
zgVboMX`fxINiT!UDb2aBz^v2AKEn@lT4UZ1zw0&kZ$P9$bDkoljT#Rsy*i`O_@i}B
z6F>=;^O}|vU|-PG767GL^MVhUEgHYAAg!9tF1X#HiC6=a%bHF9K+n;sc}xOsx90iB
zfYzfqp@H42nzc1B*r$1$w!POi^C<stL&Nz5p#7SHeGnPYET-r3P0ed`Z{N~fT@H~!
zO$_ZDZ)=7r{XV4mm#&0i&9Z0kQ;cYqFM{5froIp6?`YOiitesMGw%o39oIbb3G^p4
z{M9gcPt*JgH12D@rsTk+hPwoPQ=0F;2Xk8UhynUDn(2M8G^^=;72|c*wx*-cMeBD9
zOjqqI^jg@h4LT0urgc9JFZO7!`=HNVd+Z&6d1#;i?_sTV{M8SAFKs9X-t5)R-2rTG
z?YvSjeY7$b%=>DqW--Ej+6q2g^V41mho$}6tv^80Ut1gvW`OqgJ7@)JD_?;^kao#(
zFoU&iEodFk9;PU0i1ukev_iG<@o?s#cK0I?3DfEvFTurdZC(z{M`#yC!EU5h)c{Wq
zX&<0dTTxnW6-1-8!Ia02(T=&IFIHPfpVT<4?OO^Grxlz9cD(j7#e@>HjBJoZ?c5mX
z9nmJzbLyz}+7%c|(mqPB{bcQ4dS0Yx7fR^inX2Vi0Xt3m{6@eW(~jJOGwIrnt1zFT
z{Z<BzOl{~7K+Dn|rxJ>6?e!UWk)y2)0?F0Bv<M=3+O4#_%Gdr;3QGmrm0tk5P#Z=S
z_(j_Jw2wNj-LL|!Vr>YeQcJW2?^4RFRGUVzjxz1(N%&o^eUW~r3hgpl##U-OslKU7
z`y@R)PiR@QaP6daR1Q+Dy+NVm8tr8&&#2Y1Rzl&F_6s3Q)M?EW+&`^dNmpRKHjdtA
z4O*`NKsRa&mSAK}+D!-O>#*mv{S+`gug#^<?geeeHRxZ|eoIC3m$Y+N!+f*W^$%dT
zXwxaU*sAUM0)1`T?cT84t_`KKst#?;|IoUujeiUZo!W0Q;o%i+)^_N1Y2Tv7UAOk5
zCt#sRdyEP7tJ;?+YV5eCy+p6yUTq}`$maHGWBF)Z*T(+|jT_qD$6&BuTlzIj3}|J)
zL-D5e<5*a_rOlwc|Dd+%Gl<;Qeom#9Ls~~1B!{&pe*$wv+ewwYquQJF!X4B8NiX9&
z+PSp0ysP!0=-jwND}NlF6WT)BQQXtsyA1vN+EZ4DPHLy<Wih4I&~dtHZ7F@;bw<06
zYI0_^zZ15zZY2Xu7ajX649!hfMM;!Bx|3Wm-F4MnARfB@m%;SZt?>kymyS)vcYAg0
zH{h?g&T-@c$oS|=4uI>c`;>l)eY&;}faa(BxeLtwI=_4nf1Tl3FavZ0lqd<*RZvVQ
zNcV;X^Bk;OMuoKpbncY@4$(cthDfOHiPad=LEUQ<)(g`;ejlxHoh}0;Lf1DA^+?@^
zj&GrONatpPMwHGY4kn^?hbYz`quWj;Td}$=q<>g9@*Z4^(>+V6)Og)OIu?+id$AwC
zVWO^uj<Fxnt^N?qqq-*=A(^Dh{}j$7>$cd@m!gZs#Wpup=gELVny!|%JjZk&enly>
zbX^JU@3VBz&<UDs-A#%*=jiUYp_QxqoczwyrMkkyd|hG!U<!1cM*&)>yY?trMLHMy
z9>Q^5*XK|u)(P(ctVCB%d!=&S^t%wL(5<3_JC(Y{6uvpBQ&3T6weIoshjIVa=yvo%
zzfQ*-gZ^pV18=~^dfi6aR-MuLP}J(I?wiE`ZPJx41!>iFNWpB=t&fF5yDmKyXdSv6
zbd=<>u7pAzow{i{Np?l|+YfNGOE*Dpj&9v45!8Eh^E)7NRd)_aX2;xXx@{Ei?bR{l
zAbq;Qe8^naU48?e-q2|&j@Yk@D@NaduAj<<Zt7ldf&MLBCFM&7b%FsX+}54H3G+j`
zXXpwX);&e#TqC;LlVFbOyk7*$nC|y#NZ!%yybR`Dowp1qj&WTcEpaDxpVNgnrDGLC
zW?HwD2Zv{LE7QT8)h$YghO<8CPk_4U=arz(Re#hUKDp~}>fw`z{>m!odFtP!yUI)d
zPCdw8{aiXE<E=mV0L=U7&(V(0SAXI&F#Yt&?}O}j=zqKguD^a!8GhdYy)_;%f%=WV
zK|e@;I2V1v`b{CQbU?4Gf=GydJ{{5t)gS#7BusCihhMn<%LI5Bp?9PKG*bU!Iea>#
z|E2{K6s=c13H2EL>|Kyp{eB83#_0><FtT{PV|xc^g8p}UxgF8(r)}U-{orm)O_E+u
z;o@ZdvAuvv(SO>9)-nC*HPBDj2UFZNLtjSA^-TRAN-(qZbEtGbTVF=EN{;^T6kz7+
zSN1?MPaiUfR-rz;6$32NyLCeHxIWJ@AEL$j5jp`-qQ7zk+)}-ecHL$A&)&o+%JqJ<
zZ>`V|bV9LGf8{ImRp}*H;L{2H!xXMMsh|BBCaU%8-bY`J{x2%|sMUY_B}R5ie~1QA
zr)Rzmum=6nNqEtye=P~*jQ*!34sg%vjVkCj>EEX4$T@u~#r4kXle59RpnpaM{fqj4
z--L&k^ap8;*sMRX6_PFbmvYh9rq8GIIPH2}0X*!`AFzO2*1te0(N29-5=5@()7sJM
z(!a()U$?&OBE0X>n_Q@5>#BYy2bQksZ8yN})%RvWrcb{h4vN?HXI}xiq1Ri%?AO=R
zc6mTw_X;F$>P->oyQP1N(tv~d%)RjGwmvEhWJLe(S&&ivO#u|f^ndxn{J361oAwEP
z_ZbZ0o<8LTy8rI$kMG1JOzQt$0huX%1AQ@KR`2u|u$>L*>mcf4_~v1ZaJS+6tzfzt
z)<k3W_811p8FvGRcFi6JmtWBGG@PUjvX?=41t@zBZdNFG8&dx}QDSJK#i6f3_Yg4m
z8*c6earhfHQVmmpVd;+`friXscoAeMq!3=Pp<4@>0|pW0D?<zq_rX%A;S|=*a}OG(
z=wT9Oc#@vd;f7{sh(s8!Q=xaHA<`2=I%F9CAJn4^hEWVV+OV9?`^Fdss0t?5Fpq&D
z9d;P{*MlY+a;Zk;h~emEC>}L@L0Quz!$Jz4B^!8U&`&W8QOqLMu%isjG{b9eLhqR2
zdph=;Ztyq)kqpE5ap+|l0y_bgW$1B(!E8e?)ga^;Zc}U~*YN&Ph~ybEY4@9NaNwH3
z1Kp5Cbw-7TojYNo$dF3QtK)`Oy+Mi%4q9217|sMhvD8rd1W1|Td>Rav8-8SB^c99p
zl(?%jygDDuDnpqZdM6B=a+o-2P*IIawV{?)4K;?WcVMs9@bVmt^OT{?aTc`BaG43w
z(}rd35Un>9<iSLP;R0>a8V!?qAZHAF=)ro{aEP8MO@@1vL^)@8t_0+~VW<o!7Yu=m
z;LJtCwn_~2l3`^bTFnN@qfl=#e6$X&R>M4Uw9Rmx(!%YAUAyW1*J0>;5i*x?nSk4A
z*zhk*Tro^hl&{OsL}g0dhF9)@*<;v4Pk~-T2o+uQ8JriR@4A6abzC<LkFX)qZ(y%L
z-+&>x6qq*+yH{hpw+vr@g1$jR^;wMbwxQ}X7#cEstfT$kupxksu#Ff*6VMnn@Lt3~
z#|(ap;qbUYvKXQhhLCRb-7~DF<1zOQEHXc72&Ap)lwluLSxg&*{%~f-;JX@<vxY!A
zB<F1Wj8ac7#{Bm%L9WKlX%N|Ml<Y>!&Dfs*0Pa5z<LcMJ^)x!dpy6eVrSa}HGHH9`
zZTy4}Y#-w<|AQC4#$kF#?K95XjFz8~@dRM@8|Sd$lfUt;1+Wxge3Y)-K%?|opadBU
zn;;TwTrGyk0pt0HU?IfVM=8lr<LY|!ISv}1z++%;n9)QPB;m&71uz(4e1R5;k;Xn+
za~(4JF9ceQ@t+j*#Tt9*QF_>DBD6ST;z@|a8+Tp9bR`%&ec@rEaV@RBj~L(k4VXub
zj3p3BGJcZ*^<-lL2h0@X-}Dekbr_A5e@HV9P?#XyxYCAJhOzM=TA4;aTHR$C-<1P9
z+xU6_G;)lC|DrF~C~5-9GhVj<G~d{LA0`Tn5vA~{&?x)~tzu(76`z+Fzpn$c)L1~X
zUSWKP2U2OwrchRu(Ge`eKu;K3x?tj@F_M=1)kbYPI%|xFgFtGHi5yJODdSB#!&PT2
zq}0`Eqkv)^^+q!trf4vR(?#BB%%PaU8RLhCp>WptkSF|YGA{cG=Fb^deG2IF#;sH%
za>3~PJo+vgdmYh0yJS2|E8S+}x6h!n#rWb2n4wnV<&`keX1wwl2GedlzZlpZ##max
zT{b@YCH(C)7SnWHF*>5r*JTt_O0(POL#yW=V->yGuNohA2DxTr?u7Y1<NN=E-gV;>
z^a#CS<gBFouiy9;y-f#<pDQ49)5z-w^Oo^=HJF3O$DW2Ww~eRmU=A5Sr*y!uF=i?J
z9WlO2#j~Tv1v@~-jBAP9F?#FZ#a-k1Uon<(<6HEB#0ldJ?Pc#7f2Mused9zEP$rGL
zZd1wDlu@7nciLFxkBOQwhMxxZtnniTJasnx=mVyUDPj-IyPB@jFS6UzLvLX>lZaOR
zdrW>qm=bqWV<Y-JOb>4d@iaZ20ZcEGEgY@Ark<xD;%!<+t4SZz1^WDiuStP8hGXtN
z)1ExY_?cGH1-0K)Nr@VN(^s^l4=|nB4)cK~6Q$gOOx3Xf4K^iuW1t62^LBz6Vw#r*
zg-}ys6R;1O?ge7>VJ0_<8i$)&!!VWz(^7gHMw&KIHQ6DPjIvu%rjPeP(h+S6q32bM
z>Gr?)onlR|`vLo~seA`y;!F-JNW3X#93;UM+y%)*)8BON>4<6X*8n|gT17WNlIa2Z
z36o8YXTVG`>FG_GYTCaEm}#b)8jxeA566I#Zi?KEz6{gG1DL~1hw0XL=*%)rQ5rGZ
zWV?d#=9xaAmwCQvA=Q`_n7*f&L!n7Qp`{|z4_BdZ+~i5Y$zs#5H2Ec_KRy7n)U+rI
z<1I729SntXQ_fB}Q(?+khgPM@vmGK;rtt$Xf5NmU29hUDjvvFJUv1hzVVoM%TFUCx
zn%pT@aLQCpwNG^>!`txbwCUL(kb0Aj_M{D_aSG-(nr_U3dB&u97UZl+Lcdm%$+ZFo
z&zZKl!o+#gPwik{Fm2I-dC_!<%DFC?a!<luv&q?U6rC-mMf5;#HQ6IDiEXC5F)-Ur
z8C2HXVS0wVxNLH}1k!2xObidNm=Y<S&}H)d8IE?FKBu!QJtp>#0KIBr+R?gZ+MEcH
zUXv?r4Ejv%Zs@yidiuXtl_@P8BK;<H8pW9hOcj3u=BCM>iPkMsmme$*n#|u~@^72|
zR||)SOv`CWFl_2N3-cqU`uX^MMoq;oV2+u@*MWA&)Ih1!yQa}@pp2V(nCP1@B`tx%
zJ=3yUn7?nD(+y`PP1|~)FlF*RNk?|3O`E8eea5uL1ERAg6-C0G&C6opg^T$T)fc*&
zH|#{;ZnKG&1a9W7w2bvI8!{l`Y5r&ph?iNehQE8wKT!p+w|Vog@X*Kn_);+a%vY$o
zYQH&}o|gV*^OxugGC%hXtv`d!D_;ZX0rNluxFP0cYLHO#dpTepG(Y+kNSJxsQVb^C
z-2EDyi7<OV4H9YIH4Mo^<`@2iNR(M6!<b^tSLmGMVRNi2MB>c13o-0?vsV;a3Fc}l
zY)CY({1GBa<}YX;<w!O^uo^Ha=38`B=$N^VrY7CoOM8e6bBPhy+2-M1=;xTDR{|~9
zJe&ZLJo6j0-p)5~r+9CH*=G<Uh2};|02G;dREKrktXYn}V)MIn;IG7NrIReBX63tJ
zR+x8D46D*%F0aJwRhfHMLZjN;@C!(d+4UkwtvM$UeRbwf&H?nadB7QV>&;#5&~Gqr
zpl`P}n%|@F&l&T(K~Okr_MkfTCi7S&TIbA5^_aEuW_&vcHvn4j;*z<4D}K9X^8#82
zwwN8Oxj<_*mpz7NoB3<19BDTn9D!noIq)5{E}J)yMyJ{N9gOgb`2~uB^_ac4!2DJ7
zgH$1Y&HQ^5JnS{6&=uHc{uH$cbFZ7(B8c>xTWMi2V2(+J`c1QO6NYrlJoO~(4Vr}x
zCAhcE&(X4B$Xwx$IT<$FC{#LP9;TP^sM&B1&WxEGqtLozo-#q?u9;1NqH*(&OVFAy
z@6HC=ee+V<HBXuk(}rToETX67w0XS`m^0>M3*g$UdH#=3aJJ;W1fN_i*X*?abG6Lw
zg#K>JS(-#Q%OWb?+hciR9%S4td+25CVfmRh51tm!BN&snWf46-d@TL1!zW+M)BnY(
zEWc37+utG&h1~$leA<x*T0WrCnjp(|%3cOr+Vp6JT29OW<)G!QcG~}iS(e>GXSikC
z5PXZUlqEnv(z1_=U=LZ=`~!_Biy!4gqAgD(!fuRZ>=leD)*>y0PlqkT>p|iy8)iV_
zEpfDOOt74q1F%F(Y6zG|EKv~{=TXa=br@iZWdmitQ!URPrO&&jSw1jhx{p~ZkD@c(
zvWG&B85VsnNVa7ug`ILN>Bj++YnekOq6L=c4#VF<OC^0$qsY>?2nLT^7Ow$lu|>^-
zza<vL&~dF>O5cKdnMF=%mvT!9eYd*8vMvaHm6m)zv>a6y`BTt8Vd<vq+DVI@p0?GN
zy}dA4V_C2OCTcBFLC`;C`HHfqb(U2Wnmuh9qEFJ)TY}_3Yq0$GHP9L@ew0BzW4YB0
z$+H%B+7C5ZemsxXIm^qmrM+m0ptblVi+TWKX?9rtq`+K@<!KwZt(FHpA=+jc@xch&
zEf2m6jSkCjGstBNb}zUOEazytuUPn}!0fW{Okj3fCNDs*$5KpR-@a;@;{mX1mbq8q
zcCRI5BP9DQ*^Ovjw{WV_x?y><4uj~oIP#vvum>#n=!-lzEx3JgcUbQ3M{CeBoC(p}
zmN>c)hb)QoU>vc0G8cWLmW)<Nj#<uZ1<W1Gz6_ANmVDZ%j$7Wlg&|E?gzKPi&+-x7
zVw0BDCXgvhJgoz#E#Eu{g&E7BV-?KLTIwlv=4{>c5x6ea^Djbiw^c_E6E~}C5&HI6
z@3_DVcWbpTh=<jgvOasQnf_>bTi-E5(#JYROFm!gIF-rovx>Nw1V3y3C=Bkm?(9RK
zzcv0F^aWTiQ<OZ=I`KQ@--E2*Q;;Lr`f@Tr4_I9-01dG|N#C*wwLVPMh6k<wbXG3R
zsyvHfhg<Kx2Zac0Xbl{Vw60$QkwezEa`3}MSxtdZkG3v$z^52%9esNs*4nue>W8i2
zE|83~?xA>kyj6ON>R%G9$}GSnTK8mt9I-O)L*}UUgEwI!$y$>O4^yr4R|750`sF{s
zK4$%779#1^@`Gq)Sa&amNTxN-7h}q?>gdYNwOYE-%Cla}L|?uYmlAFq>-z<8rqG(W
z7v_ts+puzT%sp=H-UM#3wSu1VCDy#ZK}xN)bfT=x`bi=tvBFwU@r+9A^Az^2vi_Y7
zM^9K&{{i!)wV&1y)z-gaL29fCZ^C@7b?8BmI;$IHn@(GEb0Jx8ef}jd8?16Z)Elkq
zJE7n>W1XJCV9r{zi@<HNHmrcmIqL*PY|dLZ{EF5E>kqyd#YOAh>lno)>v75>G+Upl
zgkFnPO);TX>+}OqZ?k6qj#j(%-y+!Uu<m*d3YV?B20%Kkwf8XWD^_O;7k61T8)3fN
zVI8D{9zE7VDhlnj{z^~sKI;f=ovvFyr&8K}>vwdPc)*JIBkmFF%PN?^WeuZE!=QD3
zCiHGwlYfB0A!`Vo2N<^Y9|h)!b@gV5j9R-tg8G>Cn;lTUV@;)!tGia)1o|ed4!>b&
z+_P%vEqvb^L*;9eR$p4*Oj++x+3SpT<_yqgt!(<4oNc$0Vcx~|KL%WLwFyHZ>1Ipl
zfchTW!9x&nx24k?&%^dBt$jRgKhb{I%XWP)B=_3-{zA*!_70T``Pk+;=wkJ?mC_9D
zv&GOe$<OxGI*|P~4@!yp+uZ4n4X~*<LnP3aKr!qfTQ|jhf^82|T<?IbzXCpm+0I-9
z3Aa^xgGAVVqvva+&1W}64%vpcK|RXmQ3Um9+j<Is#Mn9m=_ZM_%@xDoVcVfHj49q`
zr&v^i&EN#lL|bhMyf|WeXA2~c+Hz=ToMdAppfB0>$7zf(#kS)WprzUx=0H8owmcf<
z(`_md^fGL7o`OiGZSYx4bC#`cEhMvT<sSho$M#4B)xYH0l2z!;vw5XLBj0wB_M`>2
z3W~24+D=oIRk7_+Dq<+H<<T`)YWtB2Rm*HWv^^=eZ3}{4g)M@%kCnE+EKskqy+BXf
z6E+*IA5YpI{0VleZNHc>vKrgD57DZ%oxo8@$J|r4iJzcRXY;3`xYM?BT07O-a+=X<
zux+AkQKPMg76@l--n6AYYx{zBIZd{%({SyaZ9N^gI&Yi$4%ioL|NXuFMO!EB7B1P6
zsL;FFHc3y?7F#-Hr(111UWcP?w*0lgbhO+4ppx_sn~pBsE4H0~ptH-?y9;RDHjkCi
z=&`Nt!mMAll@6irnr#O~HG6I6|H3@?*~&kI<aOIWDNw&*TeKXK{kBE42p_QRq_xjY
zn->)z-?IHmp`AfnUK_}5Tgz3T3^{CDo&+7XZKkr65!*pZ7meDsdH`+Ab|MstcWlLN
z0KIEl_y|PCZS^#m3EQXRaP6LLCl}`L+dilD@}zAMZC$2pt12NfZNq=M<NmQF9|CjM
zmM{h4Y!9VZx{E#gStz*L9e=$6nBDg4+rf3SZ=#b<d+cnAqqy5&r%0=p{bNe!?X^46
zTglu04HHZs`&U%o<ZFMe9FqI&USsgr&;I2I#<JgT$Uw{A-bgRZ0Q-+VXa(9A(%)4C
z*@x-8MX-GzWzG)R|8&snH^iP#g+ihBr@sdGpgsC`kT84of4O=4V?xY&ggt^PsUqzw
zzkvBe_Hz|zMcH3gK`+{#M!VM-yUq$nW9<zEXdSkvQ1Cd;zNrjz5pNHC5Um7z+g<b}
z+ILb}#}WI%SbBCJwa?PxBh@Zcqm^bqybCbL?59`3({%eV)mmoQ&(l&Q(|%Y1v@H8Y
zTG(XUtNPK(v9CCXR-XMwIvSO4zuyAA0{dS-K(Ej)qdTt1uB1)jaeLJV7;dqB=PR&R
zVt-WqU;f=bF9e-s_8KKL%IyuCp<iL2Pj8n>yFUfgtL&eDiN0#Pu@1}{d*lyrrq<5i
z2D_*22k2I*w|`A5)dssWUEOExK4q}fWM{tyg>!b+E}&er&rm_dC3`iQZ?;DUQ~agH
zKG*=oR{O+hfVSD!UWZJleI=bdxMF`}2hh6gO_?Cw_KzsG+G9_oU*xL&d0PBmv%kL@
zdcAgTHw^aKjemk%x7Sb=>J7U`8ld~_|4>eHz`mvs6MNHs{RTvC*;mwqI0o%)R#>`i
zU-ltDhwLlghlyc(9o09D*l*K<YSjJ>9d#eG`+ftoJN5u~DBiXA{src^z40V0P1t`U
zgZJ!t_d)L4zo1&lNqZ$7vYE0s(JeM@AE2s|8N2(JK$*2aK}7`44ksPewz)W6pqQbn
z(<@Jc>~;!U0H&K$Z6x$PoVqFS>FM+~Wx2eZGKCn$UZ*Gaz`VE9Yj40qAE%w;m|$P0
z^R)ck=kzdrV8hR8_%^`yJME>Yv%i!1d*}r?otQ!^(CMj<L4uqdmnj+)?9@!Fjss5L
z?tp%XQ!o|Ng*r{ps{f$V_71>=IlV!JFX2wN3=oNM>ZgEuq?4Y$TXD$gEvmnca*E#t
zyU|W7sa`I|X#-^iVx7A4VBxS+7iHSxoK8~4Jl?67_7w?E_Z@W@MWWMM`X`Vir`8?l
zOm@n95-=%F`)AOX>NMvMw9=g11~3=LoNiK9F2iX+3-g&yH|fLTSxy0`Fqmv7uPBJ*
zIE9wOZoZR^>M#qOhQItjO>Y7hRr&pod+(hYm|<XG=H5FSkXf3!WL8>gR$6A7S$<N}
z+|4viElp6=9Cq0^QP~$k1(Z#YeG>seK@<es5KtCH#eE0;zfZsK|Ml|a@to(J_c_lq
zcX^)koac&Q3LF|*U{L6=!xCJP!>4nBS?sX0p6<UAhb5F(FLfAtAJ}CMep?}|aERUy
zuF|2q5?qx-+)1FFa)_gud9}laS{T$g{NN6>(+(r4Y~YN;93z6Mb*N22C+ZvqQJq7*
zgOLuVoO75&cIO=y%|oCK4xu!wYjpVMUD|(dau~)y+U#)a9KvsL*!VZlE;>x1E8&vE
zZ*Jf&JJjC9;9qh0XcaVD9Xe^TbIsvT+VXC5SfByd?hrwDRfj|4Sa`bb@D1(c-f-Ad
zkC?g~a>Fo`-42R3h_}a~h>ARJI(QDJ_1`TA<YsV_I5<*@_O^pn0UW+?ct)c);4tJc
zI{L=pX#(84I=-a?wufWgT^M*d&YA}UU&kHv=nimfm;=o?N3#~VIN~@!8zmWzxwOxk
z?Wm`1u{_676Cf;fY+R0hmN>fS0Mm5B@hWw+(owbv(ld_hT>*2&aoGYi-f~PUM=*~Z
z19WJ6<@l%^F}ZDBMAy#ltviy?7P$3)6>u27HK80Nerw7Agvnbs#)8Y-x{-tX!mXda
zg5Qd*+14P{TjM`~hjUvW^5B|GTkrf1oxp7iRB#cwtvmz+m9Q;(JYX`n#r^?d&bF#+
z=yu7rIr9-y^|m$DXgjw}LMx}s+mwz_>D*RMb@?~9Ez%*h2ir!kg^TCg0>;3ue_OFR
zf^l`aOer`Yr)+l!{hhARlQhK1^d8kL?{&I60E<YcMeeXqbm|xf)g-4K5_mf5<aPt9
z=}teA;V~zhf8p@B(}(oD$#GiJ1%q6t%e2Lx=kzzF2a26Wr-LhTdUhQ#l{smty5odX
zj0@VzopP^$oOFs?j(%1+Wt;v*Y?V%5>p`lVBB(N=+KKrNU8`{lxCz5EPRnSXQS0>Y
zR0!*w4$(RCvrcPh0ax$zjBfbzPA6tSrNL>{TWD)^689pe3r^=2Bf@5<Npy&~#p!So
zG%q@R{1_^ioJL(mudh1|I%@)Gm(!I!GMM1cNhXFS`HhTQ6yj@Qev3vxEsW1x;9p{n
zZU^EO=0jRlv@$C+P-$bvsljzH%T&PcVjOq~`<Q&H@_EKY(mTPKeQ+1Vo4vakC?V`E
z6dM2MOq6^?@4t6!)4{*{)&{s5dN>2o4hx`Z=6eq*`8VMbE!HLu8G+VG*Tw?<^Zl#w
z_vE2F(E3FvZEJpc{yU7+SJq#lZ&S2XW-(RW1IgEysWAMTxm4agZO=T&zm2ki?er-P
zu>Ef1Mf$w!44EaGXMS}N#@|mZ#lL3__Q&Y_(A5LU?3^<E`$ykTA^)k=9=)2=Obdbk
z{dg9C{~VM9ow*&9kC_)S7@+gV%!A`!<{HtuU_3n^7Jl~%2*1v!x`{=D<DkEIfG(OP
z2@Et%OWmo4Z<+IMh?Zv`hntl{!qD*BOgd4pD!>{BzpwU3>uO6XEL!vPTln`Mt&}U?
z*?I(jdoZC?mg>pG(Z>32W;CIDG5e{U)tg~*;Ma%Q5CddirtV!p_%X{KU@ZKZx<p!k
z2QyirFl=XdDz3f9Oq>bB`;0w3KVLE?TpH3>%%?O@^I%tx0`X)mZ;>a~NR{$lY``CI
z;mv-q0ipV^*^hwY%LY)s&X1jFKrsHSLoFOevHNHd6U}-a206?o;yGlJCb8k~!&5RV
zp_f1kJ8>q^j<ApD(8E!dSHLipJ%13`X{?bF1?jArH&ilMRXeaV*`YMWImRBKjpi)Y
zr4@d&+2rBia@Ylwa>`|QQTcBkn?Z-)j&t!;<C?=g=ti3<m;0JBnt9x<dk89@+j$ex
z0`4Le^A~cLXc1M!#nY}%F<106U`n`{G`J|`H2(mmjQf-l1t+*a2f?nK+o=W0N$#5;
zU{JxGrUh^%m+6VVRB;3ELFE)@c@WUm-0O|tYE0a_bh_#^SHdIUGhD}1kXp`M1ZW+%
zsR<6xax=b!r+UsJ4}qTJ3TPT~p4&1Do*KAqgJICfji5*51+IQCJT-Blbh@yatDOxO
zE!<CZZ0#a9oHQ?S-_REAWv+$}lU?CV$4yYZ$~}1o(#jc7Xd=DFt*861jk`*D;C5~u
z)l_wG*>n+J=T6euzZ=}g5|B=ANfThYxDRO4yqj}A2d;-ZX9kBixqMpC-Qt$eP20<z
z^o99tu6-#m?{H6-pzSVq#Pl@``?!4C^1R0_*bH)?+rI;<54f}MU=SX1-c<Vbi1XY4
z;bX37Hv)aab@jpSDOW`qm1o>m+ADd^*@gl81y}kA4qtNn3m|;OeV_q~vt-(045f>t
zwib37k{&wEl_`0)g_04+Bx_>8W=WLv>duxNrRu!nlBj0D<VarLfiPE+mju6gk~ws@
z)=NC-7Ck3<eI9n_B`YhS*&z9@2IQ*b7*%1kN(LxD*(LD~2I-bOwT8hh$!x0g=#}IQ
zhTU%I<LmU_t9VI&qe@|KX_*-!^^=<DweByC@`W$}>0tyDC{3ZvaV-8HVg!>fb)`j6
zfwcP)NTKvT-M&TAD<@%IEL}yjz7pyC|AUKCX>BS<nY5w=eosiZQ@kgoX2TF+h4j&`
z|2|nGZB2%!Dyj2K*q@TNTtH*Bw6zz0YozlQ!tZJ6Qp(p~lMM<7cAL!mYmjzXIdL7b
z!SBQTx-5fUJ~w2EYLHIZ=2jSV$!?CMUrW~Y01-ZwoqCOU-^f0s^_8=kD;+mAxtPs7
zkJwzzj?&haui4Ve(D5^?_l3~kZ01k|6JVA_)3zY9RUcq1gUxQf0vBSIS_&@ItmP_T
z_L{lT`*@$(SgNPlZ+1T(T%_4EI=dcaw)YBz(Pl|>$SJ|Bo9be+&7RYv{<z8P@jB2P
zvl^;m%r!fb1^4-8B7H)l(5&opv=y2C`UyfSHmm&#ahI6&&4>F^vlF)9PMIB~xmdNC
zHQf$1W)oataN6wsNf4efE9wGDo!KXwVSd(ZA{_!~F-x{V*cZ)&DsY#~Oe;?zsLN)K
zlsmm@ruY)}t!5ci>2%Gknu<@_%sc~t-C=f$Qq<SY#54#y&7O}3OqbbydcyRW6(z&q
zrrF1pQ0X<>OEdmEX2J|;-Zh&=6OTSK4?5K4YX1FFL?32;`#$W#&A&F)K^kHHZ2;Uy
znip3AG|K$u-!xw4S>b?*G57i$ZL#K)shBv<JlO#%3FeMXz)m!8prV(9=4WdlJY;^C
zG7L%PpKnAk$>v|Y1C$i=A)Vlkm@k<D&7<b`z6Hv0b1AKZbIb>3n1G#UzLZ{4`R3sz
z04*>V=t?Lwx2EKBv3V=KfJ@Aalh9UbeuK(k%gm387^f5Fi<}@lX`V`3aTVsD&<v^4
zeEvp&Rhduw4sF%u=Lf-{#yqSKD5uT6#-pv)d<m76)|ro-MDvfc=AFyI-ZGEd1N&a{
zQDxxnm}|n&nY-pf7LA_yRQl+|J@eu8s(WDWU4cG5G~av*nvcyV(KGCc`Dc_sdTpLU
z3DGy^iVB!J%XhKRbdlQ>BN$hC0_85<<S7<FahET3r1^)3{KmJi@RSeSN8@h!@3Ua&
zCFiIbFi5_Ds_BE}!{~0@Bj0oxhN1GdpF#G?AMb$Oez_wpWYguBXw{S<@2A4`WAgK~
zHqVlONOeou@+U6fj>8-zM?Rch;<@tp@4%Vz<X<*pX!7O#B~UGpH{5}Jp*(}8F-7v}
zg&@W9&*@BPiCi@VT&aBidf1oAy<WoLg#0a<)tAdJ7Sc~4SJFbVLOzd59V+F2jRka-
z{COnWPRS=yuC`kKJ>>#x<inOg^R!9M(FJ)%zU_OETKTGVaDP^QwgEcz^4{m@_BnZO
z0?^LO9jPq5K|b|wXg12faD(uI{C6IjP4cUB2{g+mcYs`!yZsNEm*kd{F(jAebDqHO
z6?rk0R$P_)2O!>7`7Hz7Uz3~u{28&e$pa@swOuZ!y6_J9IX4Ke%d56QctifR6hB3$
zeD(~GF8P*rIP8`$XoaU9c@<3nZ^}o|gy@$1o!M{^teEl&p@k^Q--AJfVt6GmBNb~N
zqi0cyaWrF(R@hR)ELJhm^eNEd6fbGva6oZq5lDjKt{Dsy75gNJ^q`{30m8$IkEQ`8
zNio$9*vX2$zk#GEW-bTlQN;tQL`zc?{tmEo#a%jITcGG|M`(qLE5i^|u_B+YrxHc~
zZ@{cl3~K~ty`tNT-u~wlTWQ69UXfmgJ~b#9IT{-kZblehP%KUXT9aZm9eZn5JgkID
zi{f=W{9aU)(7N)vLe~OvLve<dCY_40RA1etuvi0!-3oJh{q`s}P<r#GVo?LazNOgd
z3h3L4nX@VXd`Gc@=00~7cPYEnr>LMe<~>D6DLQjsp$>w>2a4HrqT!)JoCKIhiY7XW
z_gHbnAJ|V6{`5|Nrg%zwozE3NQ0>bL#Uh#xzEt#53iFlX<RXxM#TB}l2NYX9z`a&{
zga4D!Bz>cJGauN_7Flw{=3)^#9K_Y)H7z^bEXJ(_=Wa3nDO5Zx3<oeyo)$mT3~sl@
z$QTTsk3}r~u)Y>PA42G7v6dz_0T#|%zy(?aSRu3^i~sG1FxbNN5KuxauF~DK$6~~H
z;7p+wnRE^;+TuG(JH%L|Qpz{h;++VPIE%&fv^`+4whdf@g@JziM2qi#0M}uWL}{UC
z7E(%MJ1g%lfu@TxEd~x<mGh5K^vWOFq2jJQP>Mi3l>bhLowxD?t;T$m+J%VF*QA{M
zD?t5}?>a*@KzYLgFo8-(+M^9t7AOG|qP(*gD*Ke7bjEAHa`Pu>3sbINjqt;jC+Vpb
zseDM)Vo}O{G<lC!UZC$e#VAWZgh8Bg9Zk~Wm1$J+dO+#^1uzqoUq6QXgG$rL@sJ);
z`fY>GVPzO?fF>#b8VPbtd7hruSxVm%aG$M=n2ETLE0@#DEl1f+r7XG1o8Ln-PuWgY
zmjy~4-RXtOQM6fDqMSP!c4f-*GoX1w`PVx5J+GWXMcxg{CM7f*mHSL|Oz?uT?<CkJ
z<?+7&)2u9{m|B!piLh^1%A3J;C=0sLc3pX63p8&i^JRePQkE@7M{g+)Q3AME`Pn6C
z-c~lI!2KQNw?R<3ryNHKv-?UfD%yOYOnwXF`%t-h2>S9=8T=cqzn>{DP@>_va>@|E
zyim@oMx-y5&yK>=E2XUkqUcvf--i1EWdkiN{4IN_<}|=^WiQMFEz4hk1X-?`3}LXP
zo(`IZSl-Qt-5$%zGjJbjxry$Iy_TajfZk`hV<^D(Tb?hWPv(bN_O^iyw=5e3oe0Z4
z=^&AoAI^eml;!R#u#d6y=z@z_%lbDE##t)qX&Y~Ooz{2<ET5M{m|&?XLJt!y2VVd=
zWcddj`a5jdO9_M|OZ`rCFxk>ofbfWA@ek<dQOm}!Y5ynH($f*{(=5OL93<WHc_~yg
zET7wf%e0KA`rTueexJZF%koG1I8L_ZM^p@)V_9<m#LFtI7{uF(`x%-(R%t^JQ;5}!
zE$|y*HTEOwi`9oz6dz^P<cC0`t)9_zF4pRxGXgcmSuLS$(RiyN^u3Y;R^w^YBEhOR
z8txOV%BWg2)vD_(Vmfa1a5G4b)erG7$hA@_pqXb?G#D^vtSTtYS!*?vW{h=K%V~1i
zWHp7}jm=iq8WDDjRV0;tT(p|?0K!XF>usQN*<^K}o+4MQR_;ZJSFL{O0cfk$`uE}D
znpMPk41Sx{2cIE|cB_~_q1j<&L8EuwDs>4+r`0uDaCTXJ@IR<@Tm6^|lpd=Elm)+O
z#qWi|Ln}*4!auSab`folt$y%Bpiiv+eF1}~R;Eca!9KG(OvNkDtzOV=_`>QGrK4V2
z)gOW3E31|dAndnVNhyZ`t2?_8+G{HnU31PVVE}C|s()93xT=1om#UlU8>)VESG_+0
zBjcgU8;dABRjb#7+pQ{C2Td<kqX=_vRk?{?L_Vr9iy`$@>1JSn{Zu`baPO~5rh>%)
z)e71O2~_<Q4q=e$ZyM5IRoVlzg{Uq^L%2ufa}cApR~7%?yhycoEmZcarc>2dm@0za
zhT$q#O9&%W-n6=jRC&;c5~5V$a>_qPtLC-AeT?c|+AoV!)lj{1yy`j~6+56hLz$Tb
zRmDlPC8{QVi?)NRFUP{}kZJ?%Kps|gCBQ|pYT{({B}FxzhsqJvFW+Dgj;g$AuOwCV
z`XEr!RI^q?n6CP9GNQ;(#m3V8m#K0LfzB~iB&~3>R2jqJDO<Iv6@AK4J-!3gT-Aqk
zE+S90ZX4|LRn_4zC{RhL9IsGyeg(K9)hl}17OOs^y89|s=tF>=Qcd|82Gy#!X@Xv(
zx}6Ek29=pNR2o&XM*9B11y#WkNSjofvw_yE8bsUHEvlnM@Ox3U`7Zi&N!6VNi_0oI
z%FbO;y-lUiS5?pEz+tOuK?H=?RELjaxY|^mI|0_NIuZ(l4%P4Dp>ji&u@1sc)n`uV
zS(mDo3Ou@1FPvdu>QPOyfX+?T5PG}ZQoZ93)n3(RN<!UMsi=(pj%vc^u(+!_qld6h
z^|L*M_f)r?VQ^nHm5PHNsq*O5++&q@HQJu2_!1aAReezn@=P^@j#E8Xt)>~{3)LkT
z^z)@^bQ}y^OxBTGA$7I3-h=+SS%><ezwXv!H=s|R*5?9&w%hvJMQ~o$gJ~w^ZC$sD
zE?MgX^yv1rR?@58&-(n^5c*rU(Dq<}wM#nu23mi$9iD=$TPW!lY`tS993|P<D$t1(
z8xILEkJ^~nTo|U=4ACQ+3>&#4TpY7e=fNV|Mz{@~9GkEY;HkhytAb{;jZF^huiFHC
zj<y>%^Ao^z+N}E(T$fD%{UY5qlj(R;kImKJVE4f0kq3f#X!CRgG@shks6n3FgwXcy
z3!D2Ux^Z9H9HJVqS2kxaA&P#RHcCVc*gQK5;cJ^urorzUn{}x`b5;+h>)Ay;nkH1P
z>KrPua8o~|eOo{Eu3%vMs|&{gB~ra67Q!g?l3;W@MtzN*;IV4Y>rjbPZ<+uuUVZ!>
zntvv!6F;FrP}kMLB3*s|0Q}~wH&R`9fm;6)92Tk%jDkv~`ZHP>RH^6ep{rY6L3Q2L
zYFC<g)~L^p139h!Uoz~@sCUqoWv%)+{RVaFkyPb!Ry{Buq+Y%79)#!Aon>_YomVSA
zN7t^X!+t=dSJgI@oM~0>-w03F)C;IWu}y9C1=p?)qmx@5>dk9FuB%54pcgmPqaVPo
zQ_VdG*QNfY6I{1C&;t?nsCV)(zp0+|1~J`IYbbNktKQHA^V{meZyDTwchsxKK<BQy
zjH(3s)U8x8aZmlW9K!qRe}aJaK<zgd_7Bw;E+Mo>>Yb>>kv>-MnhBUE>M65f@Kjy1
z1`$3}zp01Hb9K%cw7pQ9U4Z6G^{Cz8Ua61e!b89MjS|8E^)o6dHaTlHZ@?hBXw05s
zOk6eVo&e2FbIBg6?way?=<L-LoC5Yfjn#BuhiUr804-c2{0h4$%?vBpMQc*%g&Ct6
z{y)SUtKqgI`Z!H%9k_VS8>*=|ppj7ZeuAch5+I2hCKTL3lP2wJ4AddbvB9uEtoc0@
zev>p2w;)W`{O~<=QZ&-5;ErhKQ+na3=7AO@RkL;%T%>72sbn=>Ga?I`8JZ_7uroD3
z4+6?D%>)}npQSNw0GF)^a|X(B&CV(4V2<WDTJ`2?OpA4Z$<ugdK{a0!`ZlBm8lMbs
zg_^k^gDcYbQE61M<|<8GOEinO!k|=Rq)qoS&C*}cc0%)12fyVS56Z-y)Yz85yh3y4
z3OrS6wp042N|QmUzf&3$-G<c~p9@f_(L|VNBlEQ8)<g8^jK(1dT&?B>&9dq=%@<*D
zR->Sus(Q_jv{8IcvxZ)7=QZ=>&}`5+j)O`gzP*Xx;DY9Vm*Kui^Md>~Yt~pm*rI7=
zp>k1EvIFLqH2?k$a#^F#goi7d(c?@|y{frLdkU?ZxCp3T)67T(Y12$SfgZMNs%b&f
zp>d`fzw4SabHLru=qR(*sd>kU(7H6A)Au{NHJ)@(rbjc27Em`e^Qh4OmgdiHIPBHz
zKZgF^)|gQe>5j(i5CXlc>HnVYzdp_O8uaO&X2t~!_kB%U3K}11^5{2ssQF5ck$t4e
z;K4oC_<RW$Pc+YI*8WtpW<7#=rb#&s(C3;xRq*se^P3mQOU*V)!@SaTEQe;l=EMKN
zd_c3h0Gh8gYg5qOH=1r70x(IP`C}gf#)Xgm5mHxvurH!;<7d#0g*(554i9<oyQ&bA
zC!ets+-`n8)q;5OcNzfd&A)vLG5PTGXkp;XC(wZgKfa<Fp8WaJd$0@O$I>QpAb)cg
z+Jg8G8{sIJPdx|~QwaZR147)xr^pa+C_nnY6Jz|_bX0R6|A3Ao@8=hlA;K`;gHG^=
z^UFOjToL^LykH;6ThaDX6u<mOc#7sv(la}T|0Dz|vHXSk@D#_dp#qP1K7J<10e%d9
zJt%?ynr2{$CSFR(nS(q>6^@7a^q*jOm^abMktF_~NT4P2Kir0D3V(PURF3cylR%F0
zqgQ~W@)a6Hk;c2xry$b#kLWti;8T}Dn8~~MLgg6$4$Ypk__hh?U^YMLzuS=Sqc=_t
zZ%VR(PA-3f4y@(zqX;dZ*Zc$b1-uQdmkasdBjCP>U*-U=m_I!c1||Fti@=rgr&oZK
z@n(x)aDsn-B{a+VJ!3FVC;4xdqh}R--E;V@<extQSH(xuw&5v$vnvd$`Erv8TEicu
zoZ)F+L7Q}E_~J;6Wi8)M`;vA1>?DAm<-h+IU90D_l7M!Ow>u2(JReB+eFGml3!shs
z%ApAD0^jlo?wj}&s_Sg##lOI{@Ea=uc9Eay0&<B*G7YyOzkQSmjaT?#1Aw{88>ld*
zmA^~RqHFv}Dllo|msf+d^UF9`bnpwl0e79R`~@&K_!Yr0@8k<8_0YweXx87&Ybo*B
z!<+91=1u-oKH6^ar6Xb2%fEaG;cb4?MS$JmlONOm!(G0P&ad?GdoQBf_jo_b_21{i
zHsiW_z;B<6UOeQ_76J4TzkntPkNN(?fO*2VP@TzB-gz_Pea1)72Y;UPBWXGHg0GJN
zdCAYEXTmGqauPKA`OnutIKa;_z~5{BoIBlrZ}^evFmx6+SpddG=w;y0Rk)oEp_}li
z5OKQ;HY_YW1hpSjJcSuF{oO6>pjot+@Np-wy@j=OS^Egf-+=fEMT5|7KSA*+y5uj6
z{2V9&!cO{5N}y2J41*wH_rDODf`w=$Ktlw_p|IE^sHgxoRQQ>8EcOcJr=YV>h@Os^
z_6w;GLBfQyd*C8mNN9##gkW|8nvp`s6^u-j(6k$E(Lw<wM^c6CcMxcr(DW?=O&9Kc
z0+kGbr95$_5KK9pV<zDvx=FHx?X=v^7Jj5j;&EX-O(%1N&@G5GSGZh=(DH=!wDQUq
z42ketAiSa)ltQ7s9H2$Q*<#og3(^NLC=o6^f{Rk&kTpn|;Nk*<6T%P;Fw2FLRMdV_
zhz|x=A(;BlfvpsFQ;ltv5KeRIQ-U`wZ>oh@df3+pW2jR2w9x%FT$~Zyo&&8`xcVdP
z>Vyw}0nAxpG~EF8LJ!>|=L9X4oSzqVEJkPzf@LJQMxpQt3@!+LYvHI#D4}1ZS!g!V
zk*gMA3N0fq3SZ8J#U;Tq4K6MVpT|S>ilC$P!d2l21I<>Uf$FWU3De%dZ<{cWN_5)=
z-VLNf_&x+Kt_zlQdE5{d{|c2(;SiO6cM0!)43%y{SOTs`D6K)yZVC}U(fjX~Fo7P$
zy}}{NS=<&nAHndB@S_S2?+RzBVxmuoNJQH`VM8{^eWAb}eR?1m!x7p;VLqkK9|_~V
z;P<hRP5pf$<Yt0<D!4C&$}?d+)&D&g;>W=K3*nv>{Jj*uA4K&>uY^TYAng~%+d*eQ
zxSk90T98xr_>EBHgJ7J+VT;i<7cu=fI9G8t%_`kQudVRpF3zA&I(Ue?V!?TePk#pX
zZt)^bue`)V9T;bCv8)URKBD#&Fnz_E3=luj0T-}I>MtIc2b};hlU_1`;$GSu3=)4j
z1hinW@d3CHaTEP8d&DQS{ShkqKY?(sIDrzi`^3;3#I#>LCV~qSIXaOSE>?|3CnCgG
zGtv7<G5a-yQQ|0iz(k9g>F^gLwyuVXDOQwHU3i?>*MeT)T<dgj2gDb?2slA>c19G5
zqC2g_4vJH$jPQ^+m2#YiMbCfGmL%T#9R|tbRa!u$h%4Pej)+^1L-VLungGpIahyNE
z(!@RuxO7oMljsbQn*;MqllU&ZmX3*=zk@}Vm~9K4Y;hjl4#&lT;SlDCRwFQ^x#Fu5
z2=l~-8W`q_t^v?25UVM3UnpLuiAj<8M={(Ni%L5FQX)!HVNfc5_X_4^;!DbdoDe5d
zRcpDpiaxt_QZ!u%1zRC*R6(^;e2as$N?i9bKu?Lk1fpxz;s;dMQX|&HVbo8HuCzmP
zM%>kjwpwuoy@2Y(cWKM}tk_GHIrXBNuI_W<G<w*d7neK)*C1XU1NV($>USU)#JvmP
zp-CKM8V|!}@hIi1TEsFA!CVwat%1W!qAN{TE{plJRdGd}^Z_)liVOdSeXF>bM)sPx
zW&&KaiP`j7sCMzuFvQd$&Tfanb@AmLpxh8gQ*CXhXm=SNy2S5kk<%?s4S-6I7!^bN
ze>cSol=i(P%3VQv#b0khcw6jjh0Yyu0xc!(ismQbqEGyRrUduI>O0`>iy8jl9*AGk
z^Yx+lEzLn5iMMIx^jM6dQ*%$mU+EOfQ_=Yd!hR;&UI6!8oUses3-LWEoqv8QCVdaX
zS7H*adHTh-MnY#mbQ=ww*JAk|kT>Fv*-&xT?tKjv7cEbd7FTUJk9gg*iXODNYdyX|
zOrhG}X}!8vJEs6``?S-jo_oLc4DE%6Y2{PU7Owr7st+QygE6NyNu#vZ2cQ$J{ev=>
zG1~8J;XYRDSqHyy+LM2Ri`ViZ><?(iTnA`^cIY;YdZKnefgaTQ(DywLX@hnE<*+tr
zI7pIqHzl8wwKrm6kfMD?6O$v_J}dmZN43i+b(gALGz#&W(zJ7^)Fnf^a6T+DwP*eS
zIi{U{4WL=tOf5WRYqwKP&vETTBy6QQ+HR_D&D9R2WNx1JwFu38?Jml{6lmSwfv`|J
z=n}Atv{&DP-(u|_YtUArUHk#sO0@%2YgVSMrLBS!CheR~=#*=Zlk}u^ydPXtXdhd^
zMWuE%73EfG?dgQ}DeYK#LR4$p9RO3K-Al>X)7n9I(3vyZxCtP&+GUOat<%n&0{3UN
zL6n-U*N%<>$~o=xK#=p=P0<iGXtSt*wNY!j+z8bR+S}0}P1>z=mbF>C_zGOKX!E{?
z>P2lk?fP8O#?!+5vUYzr$Q3O|n}S!hn?FTNt=a=rdwos2H4va}+I%{X(XM@%0?ZEW
zvJVi`b#3bxAUCw7>(Q4^ZOu*u)1^%{WuV*L+PcfI=+SOZhxDd4WhNZn(vC_4TCdhZ
z2~W4R*>r05j`sQ&Aa}Lnn}F7*9ZRdhds>MS=J&NO8juItIfaPup*AN7p*_-i)9H%G
z+RYvqpeI_#0|0xf{rGEWKGVK!pf7Vi*ZP{l?+fk4eNcU=^`Y7KE3K%9PQO<BHqZvN
z=l_Q0Ypsml2XC|kwNP=^?Tkc(F1r4q;9PaT(xlW)m!<^guCv<(I}hDb%0PJP&QMkQ
zZry>M5PIo;qZ(*$-8xr#|M}>O?gP|UXZ`^8emeUWc=Ff%PTQUVx+dB*4%F?Vf{q~F
z-CC#w>)cMjK18==2~_sz;!dM2R2N9w0ef``t#H3jH=6FB{ko7wkTBg2s<sZ-%^U~w
z2wh`3#xPQM+?ML!qjW#fDbi@&Y8}vGbT@s`r&yiSJy^u)jPy~1cwN5&Fb8xQSujk{
zg`5DFs2kY>gM+$*)4(0lHEjfUSa<PTa7nsTc8DoiH|jSCQ*`WMfF02-rsUO8og=Mf
zQ+0P}j%Z5L?dXF}x-Ne>urqX@tb|UcZlV%V9MgT)2DB{Qp<mIKt=mRVz2mxog|N@j
zJ(ofySEqA;Fi$tU0bIT=)Cr_OSMG{YFVy{21G^&KM^pn{tZV-p4oh@){uqQ(-Kryq
zu*{^B(XgG+HH5)axo%@D&?<FJ>ENn#W9ao=t+V?A4r_FZxd`pF&MqH@XLPHmn!Z-I
zb0pg8bYFf67iV>wY35h28@2^1=X8^(5cRw+oUZi-o!1LEYSew~g0>5~*_0z`(wU0r
z<<_j5NlB6xUHe?XT-4P*fbf#;+bsO{mvvhL(3vZ`@JUc<)pdUl;WgccSMb!PGw(;d
z?Yf0Cz;)<09S8Px-E4QD+|apHp%a}t4<n-J(j9vbnBBU$REyW6TSBEsH+7>;jZnR%
zYoLv#US0eM*x%MAZ2)&i7nKQeS2v74YtyIunO=kUbnzTi?(0^cg7BekKOLxeq)Vg;
z;A36>eUK-*=X9|>)t$3~r)Rp)>k#jAorHdv7rG!?p1jokV*+`l)9<J3V!!S$N_-CJ
zcF{EHwa)7zgl}}sG;MI!e|--^7k$Y`Ag=no9UyM{yk8N8yIxuYY!7{7E(XC<KX(Eg
z?$(bfgo>A5pt-oWUi}eJeDv#lA@tRI^k6Lf^zYDyuD@PmPT$`N(2uQ0W1xQTf9oQB
zRUQn3^|7}h4AGCGdBz_7<q?Q5R6mHOv3vE)X^(H8zT*v4_Uk*Qz(tsTR~do{*O$;%
zUxeO{s>vetuJ>RbrO%{`En0u-EBul%`hRGTEml7VD*}@=PVY?_h<JVeH)uSdpYsXa
zC+Npd2bZXKqx!;w`roKehx92@Xdc#o$zXt!^w#0<o2>5~2QEdwvJT{k-kcWSNA<_I
zV=PkjB`ipqzDk0&bbSt8ff@QUVL-{$KS=;F9n%NW@un>Oj7bPTTR(q1xa0a?CWFh-
z7gL2#uHF<6lBc(mA*Ou2awmc*(0>?$9v14S9tU=jeqJp67V8bP)mNe~v_=n0^`%=O
zEYo|@9R7rUS{0zn^<yJ3cqjGS{)LAMlm6rm&`SLST6b3I5B&pjO26(XbgK1^p6Gpz
zzAF)aPwPMOMHFZBoATklR=;Z|xH|n<C#am&PfmrWdi|O>*qzhQGs57!{-Y=a)1Y6m
z1DK6^t0=^KLGR1JUz5I-QZ&taldUsUTl9CRIPIeT7}cs@(ziVU=w*E$ZJ%7xpPdNq
zs(uh1I%?I2(SGzb{bwAwHod(OcJ2B=`e8fteWRdxT`%p0@P>Z+2n5=xPagvJU3%+x
zFbEIyzvLsPhx#=MFnFYY$3z=MkM+A&gFMl{MGw!Xdb6n@&-4SM;pw?P`2_4==o_2B
zz0~{NK-(+*A*%T7*QaD6-T{3it;$~O7sUZ3)v(YEnrVjj=sM0YG`)vT95cKvL0gt#
zNeH6IHW>3DJZ>oRruk=%;VLcs@(hb<B358fra)L|ShxW?#Rg^@&`J!0XrrXm5Fn#p
z)bNI0GA9h@{s3CJ;mJ#olZG<dQK~RprOUa}uy7pAPZ`F>&@X9_rXrXc!!$FfoH3M)
zgF&s~L_PhNF?EIuc95PmnA6dxdV>|E(9aoyCt`%o8&2h*t-%mSnbt<bt7&k5!7w2a
znoWi^<=~nP|4^}Ti{X9RFS%&=DjLE|2A)=Imkmu72<D36DZQhv8WR3QCt3|}Z-nMG
zLptW^CTW`?>}N>Z4a;m0RF~m*A4Gc7@Z%-G+%hOBP1kGqGY{@>8*VNH%pJp{Q6P5>
zHUfUiK0~b^4DK0xeu3r#!yJ2nJv4lZ+>Z2-;n}Akj}5b)Lioh+b|zGw8Y-V5-e-ng
zQV31Y4dY$u_cbuR=+jF>+EGOD%COT1T)#nn3N8i=<LFiQ+Q3jg<Beh8=YVlG9=QYJ
zVw|l<o2&6#I%ex;JVj{~cjJ0`i+UKd?m@-VXuS@YyNyv((dK2W+y_l>qpJ-%;bSsJ
zpMwiu<9mUS`WYRMqoe-D|IuVCz?eo8qCn&4%`glyMs5OVi1GbX5biPh(Wg2>jsMbC
z!(L-JRc`Gw9=?j-Zojd~3o2no38hNHjo+MyrwHTaCBTd{I#E$)l<}{Hu!}aD?({=7
z#%S{iq_M^Znkd8>`?mll-grd@!vn_q&A?7HZjZ-!9W<8BL4OY!McTkSY&`NKh9t=t
zLg~m9V{$j_jv9y2(<9aBLi;@F#`l(iWEe;N1(i(Wms#+8%$Q2IN|v$BL~HSE<6re~
zkz;hf57k`bs+DNWGY(gxE#Fv0>E;6COv<De8pHe%VUf{qEMSU_llFisF>a@OyVTfy
z9>OxCqaMN&#<ys%y4-l>JAj=uz8iu-D~ucWLs)6N$)gih#!XM@{ySxiql%eoW8_M}
z)EIYA;^mCd<0VL~@dWL>)ftl*gm%_Ag-W#RjZf&(J7@fW#~_?Hj%<YRrSb1XfbF*Z
zjB@qfw&j%L^s!Z%(6-<9y?+1}Vf&EM^3k@Al)H|zy*-rfzXaRd2~bV4-E#!eWZQ&u
zP))IY!Xu_5w$r8Xbkw$tp82V^Mbi*Pnr(hHJf+*-rld@U?V1uqk!h=S#c&<7JxGVv
zvutx|xU+31QK{K++v%f#nQPlQ4|aLBizY!>Zkv09>OW7~Iw)XRZ~F-y1v+Q@(PgNf
zx4pX*ej98nXkOK5yLvH#xnSEk9bId(wWdUGvuzW-8(VDe9fJ8qTg_tFU9$BpLok<Z
zyDx#eVw?RZFt6I0hQY4Y_E`t)uGz-KLD*({|1H>=+HLh;Bd8AB-!jp7-Il+A@H=fi
z=|EGLt+WtmZgzED5W3rWjsU2Kov<E;o^}y*oF~d|>UXe<w)^-HxEQ+-n##x8ZKbaT
z#@WsM1YEq`rgvbTV3*$wVWQnydXF5kt0@Iay2-9m4;LAB8TZlOOuHsJA9&2J&I!L$
zmR$_xBeLxdmxDWQH-Tn;Id=ZO@KkDNPrLbLcJ<C^J7G7&0CL7|d?~<c?Q-UU)Y;9X
zFB+Y-3#Y>Ab9V232d=@+k(QQ?b_MiJylZx*a=P!^>?&!w-fm|`8weeCA1;EY8+Nq|
z0n=%>MGo@VE{!(VpW0=73C(AA$<62!ij*jw`ND2JJ)U3L&7A?2e!CV*FAUg)DZst9
z>)#1;XZtF8pt{&MRzTC$e$Kau!p(k=$s3LC_MgT=>S14S6}|VgU%Lnad)c3)iHWzp
z<wX!5d&UXj``VY$XKDQGx3|E+-@b-6NCWJDqCJs7`-L>E3%2*CFMNgAH)o@5kA3oL
z_zkspIS;$N_E;_BIc5L(2x#uNpJ7Ku3}N=0mZ34i{uE`1Bkd=D4~uAf*LbwW*w=gl
zm_zm}{#)MIJ5XJ4vb`@|5GnSVwjf9CA5z6jn*DHE8K>K;=@FV?f08B-nf9|*!{IUe
z5f;GAvR_C~foyxn{V+IgKkf^<|8ne?=R+sgK6VMv^6c3^FbMhfvuz+Ov}f}WQ-%FO
zdRkZ7o7cg<%Koqs;h(Z!NssPodz%UfYwSO!>*BQiI-2X%+Pg0VN}YXc1lrEp*A}C#
z*}k7X-q2!iwGYs3_A61(VUo7nUoaxJ4*OtQSzovR{3^!chP@-@i#zSRaOgqWWj})|
ziM#Dh>jBeaKcDWnoAy!GK)Yq{`W=M5_G_tz;kNyd7HHnFuiA<zg5DDPSh&KU_s(sC
zli_OGOdT<H4`Op;zQEmKlDacahavP}uKc%BW~NoaayRp22Xwrcg)~?7W~R|Q$A<}{
zAHkQgM+LPkl3{3Sf1DW;i%4^r=N9<YbD76qBep!|bqnnBndE)o3Ydkvfmz7R+76W>
zCY?&ti<vF20cI*;{+f%3OPPjc=zbZqpa>Qx8084)lrvsl;7&5T52LMu@uMC8GtAjl
zg9gcZm|OI;c4xP@!rX(M{Vp7OvN;bS+|5SQQ423NAq$*0JDbYyeAqwf_2A0}ZiUc~
z-8KaV{wB7TlB5Cb$zOmS$Z8bmQxMy%Mt_4@CLB?Ou(y$7lEt#Mh3NJL_6k<tGEeRS
zjkhnCicNA^FgN^bVDICm(H=!4cgactaQvAdslnfq!WsZRxzrarUu>bt^j8VTfIM%=
zNLqg_T5%omtvOl_RmTRp2%VnphQy0mR*Am(GS#EN<ucrPjAA)61Ru-!51g-~$?t0}
z=3O{_!|jzJAZN))y5fQ)Ba}c6mV7~nr{m2E>4?n%vs~J)NHDXe8n{HWJ;=D>`cnnf
zL#IbIq7Sfrs<%Hw;}g}!YN+<BawdRtv$h(7aDA-r?S@LQ^_pS84zr%N6<n<K@D<QJ
zWc`xL0uNjN@D`#-vffYo*2&g~DIK0-ebF1-5$jjKq3cJj|D^<Ws<j<~?JqjR$W531
zF*4cK1<RpUXg$FVq}=-Q*FdVVmaj!8&sjUpf$b&h_~!t;Y<(vg5Lc|9RYLQs^@sLw
z-D)jg2-0W$)(mLgvu>#Zci-BZvWpL_59|i_(0Xhtd_J-sOu3H7*2`$){fYG$(_mOU
zwf3Yze`bBy5jroduk45Wm)1#CM*hnBB$c!ETiefo`vL38G&g>29n=MbH`Xa{0o&Oo
zAs58O<|%FNyV@jB)zfa9KR*JBmrVuz4Bj?lTwv#8)Ak4`zBcx6@S_CV)b*Gk4Y5gC
zijMBF`K}()P@AwM_}y#s-Zh{l+T<tGsM;)~cYBJ>?z1q+w5fRk_t`cR*P(}nHurm>
zdDW)nBeb>JymJ$z&E`QQNV`q;3XmH%cm6`RJ8c#k;OK=-&@Egx&T5&4`3v`hI)$e8
z{_2U%AmQo{4Db}EcA9{=53Bdm_Gg;9`6ld-tE)D`Q<3`UEW~tD-R**SPpfAe&~{#Z
zaTGK!s)y3{Nt?QaDvP?+_32Q#tIk{qzmL`J-upA_7>y}~Hlchpa!Qu?YSJhz<EQz9
zYEJw$9kiAR(3t3D6{t}zK}Ul$PW9k|H62tI9isWY4es}7HhzdeLp5VAqiwIoYbfmY
zX*#|E*nW-l4D7-*fz=QuYRai(<)Fq?27^Ny+y5$G4r|__;}l66CrTwGYX-FeCPh=T
z3IQL{RH`97s<Ar=lB)5hc}kk*gboJjn)fO7n4#H4X{1ceMp|ee)8zMqWN8MT!QpYu
zFTv2v(Y&VZv0P0`84U6?lW8Y9U$fSee)Iy(aC(mxY93Y6kZRUaM~gMBRLEJP*-Q(_
zQq8LsFf7w}z6;G08XP>s&7tY3f$*fJ>3!H$Xs!ifNX}_YQRrcd=E!zHU(@u`v!zSZ
z{uUy<qggZ^(2q1*=osQFP2jhZg}9zIibkjoXbd00{<Wr=DyZLRCeUKong4^nmf^<_
zGlPmhe>V=;0sLnlLnV-pI111p{{6Sm7R-N4kGDO1#!AE#%CFrYQO_7n-?qa%o;T+J
zeSoit1((1t9DrRSKb&3?2l<XB7#!kDBH-^ZUwIQ;6936-Xr}N3lr1>IhbF<pQGV!H
zj7Tc~%K<n_;|)tO2I;)tO=xEDt$%@J@)LuBQow(&z@QcKTTE@RFX1DNke2cjh@9q6
z{Q#IVy!AP_uj890!SF1<j7k$)`1#M!!HfLkaA;oU-#HAwSNO+t7k2V-T7Y%&I0A^v
znNOsxq#pjjZK&Mj!$Z)eTYQK!xL!VnN{4UrBNOT8y~F#`+xRa3)}OHG<NGD>bdT?$
zqJaCnYdp9I{Ou0-eaQd(FJK<=>nR8Qgzx_u22c5WDvb6szG4!%=lr{KKwj|I=~?`e
zKYa&*zT#ii!BIb-K&Lkb__HSf_L}!RNQt#K{5v%9brw$3M}J*}A7Y^6D%2DL)J@p&
z9ER?~mSVK|3%}b!7$C6y2rW>E%!Ou<Q1chiLWJbS^z#Y<RKOA{yieEDUg0?{Mh^(9
zD9@E3JR+4uL0t~+ps@1JAiP)(3DZIWdRQ?35{5}a3jLzVg6jnsrU*Sr2>*z%BnWLs
zh1kO&se;cr1d}FsTt{f>!f;yCW(d{vbj}pibOmJzW9k3+%@$I+z#SL7M}o@{LSn$>
z3cmlPqJ@B8VQ0!0zM+?1flxy!%R*uE84P!ku#h%bi-n(K5Jidb7L|^a3U}!jEfele
zMT94WiqR033mfcUP%k)B9m_dk-A1%E2);?MYZTJog|JyTq=8C{&`LvjSC|lk;p!94
z3<Y^*5*E_lM!ztT3Nr=-2RbzKTF9IY;TvHMT^`QjP-{f$B5wZ`;k$~%JK@(&teJ(8
zaTocmaOfdEpbVg=Xz?@Jc8ly#fO(1ch5^M}^mm83kJu9l&QCPZ^u}NORtjN&Xqqz*
zhJoVwAAubt#=MWlVDWJ|utUT$+J@XCUZp*xP|=*W@%M_?X=L_^pND|kFQzyHG)(-A
zmUH2v*DMGl#KUw_B2w(9jrSzcD-6P9(QFEYDdM~Z;Esp`+wqGW6+bfl0qj(<VGQik
z#ppcv%@9K#qEDG($4=NE6WePLMV5Fm2%fS<KdRM?8!gU3508z`aY8UzqxVz;#p{E!
zKf}evG391((J|&p2~Y+;>832h>rdt+LKrgc2CZ4b#x0`<Q~0<atf;Uea$Hmj(6Yx(
zYlr)aaUoQ>SvhXzEa=pZ8%d9yo^i)$YMu1yhi5GiDgLZW4aDDnrgZ>)z2p1%dxOCo
zQEa@}iN77U(Ijl^20y@WJ3@tJ&di{X0PDhtwB&VVro=+QhcU$r28=J$LbZkd%uAYO
z?qy!n@r-@UiRI{P43iTHlvw8G6Y4or%b+cZxkAajWX9_f>{1xtr5LIsj1A?Ovlv@C
ze4fqxMwdnr!z~9_%$yhkQo`J6gk339Fc(}6^R|gLqfawmHUabu^T`#ssAb$s(Adl@
z9Rai!W+|m4FESH6;o=gL>J4EBGmExtt}|}mfZSlNoq%~KqZor8b}{2zf!WQ(yp6DX
zn5XS%yUBb*@!n!q9z@#%rvE-XJY+0G>E-i?c|r-W$IP{K*gs*0+khKjnm&WYYo>wf
z#NIIL4<ia^_GfwlyRc;q5W2F(Gz)QKCsI+NJFBI%kO%8YizrWa=qzaNW_LwE#fuH5
zO(AdgHWjP+u#@ST>dVGWrRSd?tD$#-Kl^770uEqjj{*r~mBAoE>`{8+1+)7{f(v0I
zX>zcKZLk4aC_C&eVDDuQa!}dFZldad{p^7?XbWQvbKxSKJ@^#@jbJxXIeR3#FAy<B
zu`}t2STtLLbfZZc!}23xc!<TD6OTc5YB7RIXQzdsGa2lqWLRXf3+VXTG4^sigaz!P
zZU_t6b(E+mVwX+<b}_qk75tX46Q~-Ziq$Vc+bQ;UA81yypHdc~hV9=B^V4k1EQEH3
z9riogOttKVBf!4GPNZ^%tE_P?xK{S`0yJJ@Ybf8|!QQ56VkgT@hKnwCiZ|@L*=b|Y
ziyrp7AL;jH4@^Y#x7hdS1=Gv6S)%PW`|Vk@IdcabVX&K<Pp7&9xF2lcVK4W~R}e;-
zxbRo-o4{RJ4i`r_>2OGoa>qU4K9#ekYc`GZp=!c(?o;~4Kn6FW9Q`fg>RREVm@|I{
zhb3IlV1!o6O`*hD8P`l-0X@N$Si=2DE^0IkD!2hU=Tpf&qk{=m+%DSmJH?rPTnp@K
z?&B8NU*Nu?*W?w>%nmTuxoiGtyT$F_1mS&7c?uTKxCF|yz2<`G`*NO=QeQ;BThc?b
z5idyx6;60dq;y!`M`A<kZ(qrX>xjZn;`A-JFv;~th&NnvkDeP5l1kHEz(h&}Iv5cp
z`6e8Gqb0r5p%WvSu>yv1l3IE~#7p{U_v?V9fr_6KBrW$r5+#ORXgerbYJnj=Bzdw4
zcE=>8R){xW@`x&M$|NVhKuo73Bcfn_R+2%NY?H)+uJNl9+c%VUydjzP4AR?@r<C@;
zBWY}c#a)T^Cb&MySXxotlYB(=Y4;^oZ{YWVWW+`oJe2g$g2UI6-)19<H<A@JpLLe5
z+Yc2NX&%+1y5d{r2+d8pF98Pb(jlvW=^@>ofZp$xmaL)s&r5og-e}&^<XE8jAgc%B
zi_ap!!cRJ|6K(!dE6TkDNX@C3albUl87g5?8#+Z3F1;277ZK94J;08XUh}4*lwPE_
zRkSoO8k(^<PzlXA{6By|iN|qnbnt+*0~raEG(oyyGone9>ghc3LFob7YE6?KJO`b0
zq>#a7NPnA%woE+RfOZVQfn?!-OMr`PY06RfJuV#_g?MwNyFSJs<VgiuGv-SJX&b3P
zn%D-vh0+_-Ffv8bN)Lb)OP8;J&{QHdUk{j5(q+%#uv&VP>d9-Q{w>fsEj{20az;9J
zF-WcS$p-kXlkRGP%2{dO68whs(&CR{eqK74GARwxuZO@zqjX#;!oDEQy9Z&DG`#>^
zvowoNPPIrsn1*;SN}te|H!hi^b5{eqTWUqyDm~JI(LlQ?okx@GThjO(bf#A-{TFSw
zrB3F+zAN4Q4ea}*V*;UhPrBg{RPIZ&BO!bseWwnZ52fFw!S5Ss=f4m-%d+Vu>mt*a
z!Q550-y6_wvM)BH&0S{NHXimKGV=h0xLfwj2vskc!yRCI%Nizw^N~f-Jlt32GZvtJ
zvQA3t`pc9r5q^ZsngdLv%$_C=Q8E=~l+tL~oT=bqWdHmCE>`yUVmOSGy-ypN@iJd8
zM3^9ZKOfMEvZba0{7wgDAJCHbkZkRb@OxM`Za5l~WXw&BbFwVY4~8kSTe(mvmnF@B
z!AaR4^q8!b$x9IZHCgyA2-{>EX*Mz-3#7vNB(u?R0IM*2ZzaGg&4va*h%aZHhOo`-
zpf}8W&3^yyKahQ3Cd+~0bF+<EKzm`flF~`u=7n{z@G)ON8{DDh`%>UO)_gVP+cM3g
zsh*(7JTnh|E6i7k5MDLkKxb+mm|KUTzq{oh{ff3w`AwQ29FV(85JiUkdrFiam)EPI
zQX_X5N*@+KE$<owLtn*Q1*8Frl1<<O6+hCo9;DFHk~KtO8jgVXC_<^+d9T8EDbV&Q
zranQ~5sGc}{eeiuR6SIp6xH2OiBVL2h?rs(vu)upL9vCNq=||^9qbM&8fk|(NiiU&
z!m=ZZ!M~v~O_5A%#!SU-Zv>pB_<Js}vlVatMq7^JS}0uPDz;LQL7pOp64&{PJi5it
zD2faqb&3`BaClBpZjQD_g=Yp_G%4cgqZ2KPIVMDLN%7@$fL&E=p^LObG50o9Os*DL
zw72VSv8WQPr$zM&`1P`wu@1omSY-VT)gX(aRFF`MZ)m4?pM}*u3`w}fFLeGZ%Hq8~
znhxTRkhcwg&#R#Qp!q&jtM|(^I*z<x&<FVU!Y7nk`gJ#zwk{e!8vkDWc|0Z7maNJH
z>eBFiaIq|L5!^2KdX0!yIMNp7N`(P`|2BUZ%vN1YLr;G%rlsqe?X>mh(7FY^b?l~*
z+u9xggl+3R@NcJnsw~^#O_QyEt;XQryY#f5ZrVY^>B8tKJ?6?-Z&u*<cVlX_u=Hns
zqN0ER#<m%nfsENGa6!z|aFB53_Ya^F!PNZ(^ho9fQmfK*=J^&xmCJn71+-G;k5Y8%
z6f>D-!S&2>EQ0^vumrz{f5ftrse&zz%`F99JUgGV?+4h=Orda=z*aUQ(j<2BR7jKA
zpk4r`v1c#9XF4k@0GGkm$<cP4wI2j7hrKlgB$wUf29n1vUIX)Dc7`7eO4yL$a8b%$
zr7T(n%TpSvk{z7^^D6e+YG|He>zv`XmR)CNg2j0@hhC!%Y*GnAZ)D{(X}Z9&$j(YH
zvHCB;U1oCwz+GYAP`PD0J1_v!!P?TS<2vgy0_Hc^z5mUE*~=&4_ZEACGMv3^QUJPr
zk9|WAipQ)=5DcEMU(we6Q+C}p+E{qS=D!WU&fK^SP<<qy;Ei#7qG-lW(|-f_no-d+
z_6=j8(Q#(?)44?#_R%i%#Fcdz0$VqB<uQ13X9p*Oc(6an(dNm9Qi0!YwuDx%UhF<v
zW_z>W{P&h+duhMLmo=rd0L_nGI~7j-*=Bk{2C#RqAAl+FV?A`j*<T+b+6Xo}3vH2X
zR6g1cv&wFGN@f=~{9g)NkkC4Kz8P&D{_+#uybFA&JaOS<Dq;Hd@dL;g?cIeC7W=dV
zVaWtaOe{6MT!H3gHU&UieqkF7R%{-Ih*r*~uP^;JxfY<S9BG&S_so+pSnZI6f3FFq
zr_0&~`t>%3d<AF!%%Y9ztt05wxUH1F8{p1-LWdMQm{oz0c`_cesZWf<7w{Lvyg38)
zU}m$)5)p+kBkf=j$$U?B%~4EaJBBZs*;<MaVwo-LAw0m$A~y$_?^Ga3%qu$BeT2FF
z70lBZ2P&bgXC6`v=a{QhU~!%qR|iiG(1hPc#(XWfi;U%Dn71-{w5Gbwr0=1bNH5dO
zpz#UwaV`vBGHI8gGr$ZU3A8tidJ?c*So3!P6U&M|5aNSz*tqzAcUQX+|Hx;$$HJz7
z`RNaYRmd!R0lXq+I_+5&Gv?z!N|<js^s1DJrL*W|%sN_Q*DxkEttwA5yDMRTh8aN@
zM=f)Wwz2A%*(5y6{OJr*&m_tI>)jzr3fy3-C_B~3WK(%h7jvu^{pe#hQNr#XqoXl?
z&U{5r`xi_iWj0*dzjG0V8+)GS^6u<-Ix^zV{$-*X;Q-cl9{dKfU!8<%7~8cEB%B>Q
z8G{?a`ZR$gu#Ew5pU57frN}{cKFw?nu|HBNS~@$99*-I9<B!1Qv&L%(rhuKE15br4
zQv&lMb|)<!D%lLG_^o0a!(niW{p>dr{8qF5<nTN@Z6&Z9*srJ_w~;j)gC1UB9cW?G
z$`+nR+ckE5BHG&647yU=*?X_h*1^7}l~6D1Mhm#x>;&48zr$+jIP_h%dJae*JN_S-
z-($xNf%$z_sKfw0V87Wx_y0rof3*Geh?UXf=P|o$E4U}@4>ZnC+26M!v}Y`T1A#tg
z6>HJ87wi<8O}}I-YQeo?+iRiH&puxU_XBJ#Re1SvN7`Tz!THlPE1v74(vl>ui-O7I
zib6puxmio;!!nmR^TmkfE*JO@q%M-D>j4@qxkNu+x@6m@2&PQ3vJRm2l7i_7|C*%r
zAD}&w9Nq--O46V4e~*B3(xJ31c3J9ZMrzV!R29=MT}-9KH>3-~fYdD=_y;Pz(u8{W
z?2~RZQEAdc=?XunK9dezgrHwa#}5Vf2GeJ#y31lG3_{27hv%t|V!`HH!29)e3mO+Y
zngeEOInAq=&(A^YTAy|3@VbpW{@(IGXTUk+Qw_4?km=CedT%_eoSD*N=#C51u!}w{
z>CI$Qb+ivNoH9Bg%+`&--^2V%Ij~4(SsS=0CSnQN5}ChfhvOjgDQ#k=GE-+G_%w!n
z51Q$Wq7YH!GB5f-@|b_<O_|Rq_rSb>u^fPTArt=y21U$#AM~%7sm`Xt-V)}gt<WiD
z;s#(?#*|cmoM67BSwT7T+6Z!znLiJHE11|XU|-3E(A2Jq38hTlDQ4Rms8lmrs&T1d
zzNaGC)6AAZAZM7aZ3wiM;pif&W7g3w?OA4}BZT$Lb()Wx&N1UIL3*AUP=ak>x|$Ho
zWoCIWhVBY8<0p*QRYoepQ!8_4BmJ&S(G5h=#&jk?rH7ed5A2)FLt3ofV#HvW_cD6Q
z4&G))t_SoTW;PF$yUe@vLDfD+peH~E+rJcGIVN@kJxKCc2P#x3V24n8y@=HZL$!>p
zp^~qYY``*friy**8ugH^sDoiG+e``9dUjn8R2tboeuKefHqjL-H`ow2gyzh3ua-lK
zKSCt+HHt0x2PB%^k_XcmHW5H3JX1X=Q5eTgoC4SJ>@qr2dVtOFgk1uA`4pl{WP=C6
z=Rx*!yzTJRQA~rE!)(XzuuEb&s+&q?HS{1(VW(1c&Jot%9GXYjk10u!%C0;D%``T-
z3tT$uYY9gg>>?^rGG(%#Zb9QQb|ZbpI+xY{0<MhxC>k&)*#3n8tzliaq3txA+k{}w
zuqS9MyO#ZWD#o~pZTS=Ko7uxu7T&^ErGdN1I-P`FJA3L&bhLxj(Q^AbJ9rxGZm@qi
zf^@Q9Y==RYiESE(#%?xmJq&wT!)XL{lf5(_A>Lw({{&1gTSK|x+w4X<<9vtRL=Wk^
z>?f4|?qh$Vqh9w|RRYK}_IsM%K4<-t5bq1Nn=Yc4Y&{(ndBv(8LfFrKRRPTb_Bnkb
z>osf23q+$QXRyO~?dG=7Lo<-Gp@&xxXHB`{Fz&7Zm2mE-YvAI!T*~bn;HIsFK??UP
z?OYz=M$vv%7S~HvGTEHd4QLi|uc<7xn7d5L#Y%1!RmW9vyGH{06t{6NG|zEgn{=S(
zx%HHxYT)|LBB(|#f}W%oxKA#it%+MY0d38kdl3A#a4YEJ5f`}x`h6~Oqjo~&GPm?w
z1apOJq+H=u?tTwQD>rI4$TjXgny$5RMtZ5Yb8D#vx`UhY4}_iEuyjiBcX58SsO;uK
zOX0qU8%fLFUTz^xkZyD87vS!2YtBIPE;l_9_I=!rn;;LkP4hq=a?_Ro`w`bd8w&$m
zr7ODaEcu&*fs3S_iu+t8=Sam(;<FiT?vnF^q3I#Ha+KabIEb!<CvVB!?=Uoe60rxt
z_)8wgA^ZTz+qCHrD49>CenFD7ztNT~@uU*&EJ<oU42mSPD7{c2`Tj6eY9$lWA-pY#
z*-F2!^m-Sf@RHr9k@1uL)Ccnb+2um0?2~C*2jTvUkX=oOG*TAo22W8k%@%|hEt`-6
z5+i%u1<*LzHX8(dK<54>0!@_pS^)HrY~vdUlVzjaAxx2dY6;LIvQ$cu9+e$!gI%g@
z>q&GwU3P&M9T~D0S3ojli97ypX3g(hM&rNWJzBCY^pL^huTACvT@?8XqF+3f&Lb_^
z{xx)#{yiOkufBZ`2y2olH~YtX8}aY8!#km~IrL-b|C4S6&X#bRDL5qW#ovw<H_)f8
zUsKO^Odf!~J99{+v1ejv3gFL}S{BieFj5P^1Tufbg9I^)IuLy@Q~wfINjQ^0?@_G1
z=nju$cG43min(;1hKX_N26P5<vk=~LnMW=FD`xi44EiL~PN&6dnA5cWs%N6#$1pW9
zby<k<3L{dv<8|he={lmh&3JY~`jn}c0@Rre{16U<*>C3pEuNje`~NQ_S!RSFhzT|U
zH<-CF0;b_iI28g$F!Ik4awJnU79@(v`V>ABnXs|YJjir9f}}F5gAsWe^WYE+(wT00
zU1yk>1++bp$6T2XHlMMchXE*HHr#;lB(wTYIILi-XbZKLX{9$t9WzM}A$BJy(bmGK
zCjhODS(XB>ol$Loiw-6;9UZvNWYZSF5jNQhDo5Fn9=ashUnxhM#(GpkGo3Y^rG-fb
zyO2H}mC06^fgEFfwxerj*jvf4Xk$;m3x~1Xu}L6t+-1t=#B)E@!NmctkcHm_?$8Jf
zTq3ud&VC%^Ru6^UAujtL2oH0^{)S2tXZ#EuOy&arMKCE`J7u;5CBsa^&=@2sp*3T$
zq(*>?5J}oU=;$8Fdp@uam2AWOO1f7voF2*hB%wv%_Dd3|DmhGI9s`wd$zH05kB}7o
z1iz7zDw<_@$P83;cSN>s6a1#hzSn}wl10)CJxBJ~3I=(yjW12;#sAmKwSPr*UEw+V
z&RhsDM?e~_8lp?lD#Oe$pdgYMK;EDNS`|f*QBh#j88rAp1w|7z@qs6%qG*%W2PAbZ
z&9qUG_^b&^YIUjcl_F{-n6}DGLDO#=f9W64u;#9P&VHZ6+<W)g`<ywZu0I5xS~ZB5
zNOfv0Kb%ggJ$r(+U9G49>jsyVzlZs17Z*Pu&$$fx0==(YJ}-h7S6m*1zls1KQW^jD
z(Ie6yf?xlk&HOfRqdgzMp{G>CX{K_;`-%c<`1r1g;e(A)S^F?0iSP7+@uY@}u$}yn
z>lG=E*^o}P?#G;r+qVGt@ln5myA#|$h49orB|>RtWE-f{PI8TJ`d9bR&U$wb@G}bd
z<XHBV6iCh04M%%k7bjBe1ry=Fqj(p1mYETQmgtuE9SN~DVkLHOVVQXT6iDSF_X?2f
z#J2SS>#_F?Qq^L@mr!(AbaR2}OR=9zV0EI5Q!Qu3ijRP-7tc9~d`TSR`MD;Zy#;@7
zi=yl3-4jL^^jbu71P0nB#-D=R^AZv30b(ib4}jo$nmPSd$l`lr4t$UC>4}*bdw|!M
zMOs&kyF*Ol-$v;az5!6vB|5{Pv|Fq>0P&whvV>17DK-|!QrhDU&N3Q!7MjZG!(td(
zN5wb6vX#u$P`r&wB3;p~p~o}OJx(!=uVU>68pSEMYgEbmny*v99ccWHK6A%>+@L>C
zg3wJWHGp=Xx<-NX0fi4mubGnS;nxqeif`Q?X%8=+|3$%^FL_GAi5S5%3gaB?dy0Q2
zuRk^^mpJ>mMS0(bL2gqXtcGBPGC%y)L%P@FXpo<X+YV@I6^l6NZ4+HfVY6M_{SbOP
zL~SHMr+6F!WGNNScscA(7U3Vdfj+W8?M8CtD7S)o9)tLHYUGuZq&e3(F}Rz$*FwIE
zS~*<ZLpeNAdub3Sbq~;_P?$eRn@y0YCeseMewdDS!qO2M#F6lEvT#+fmKxh(=`3Ar
zg_d&^SA;ogpnY5!`j&KDq4|#N{NlYq=dME8O*(Jo`o}FQ4~O7w(tir#9STi@;P><%
zSHJ&3t1rQPBbE38+@(HN4DB(k;p*NKiaG(%N;MpWw2}YEkZY$ZUm!baJQpXP(UT&K
ztcwEqZBeT9iGVX@%HaNBsZzp_Uqk*?3E}-|CzN@-xBsfLiccopQBv-K=aG`dYrHmP
zz<AJ}D|P3=xklTu3(iRG{kNg?ptc|my;|)dj_Vq<)lG2wt~PKlI6Jhb^icM`F8v5N
zD|7?7H2ynX_eS`%SGSJ$7MJYPksa8bYBpz0cBykY?Yvv{;@o|eI`S!IX1_X$Ba?&b
zfY$-4)&BhK`%L{SKNt?FzFe*PLj7S9yl|>hvLWyn^^JA#;;355M^28Z6NbXIT6IGc
z4A!YrxTg7)8qeodPnD=Oy&!*DZSMiWGinJ}GtaBzjzZ#ss_zfvMYZQtIMbl&_*CfM
z)fttqo_4WKJ2B&NalAB-A3g*;326$%6U$S9NpfEgACgD$4V>}^3DML~T0kB5!8ec^
zf1(EdP8ePC95a))x*cOrzshcAD8ry=;_<ccYSKb3bN}}HQm{@={}w8y^!^;2Q%BE&
z>daeBpiUQDi_ZFu7G`DyKLjS*$V-=;;l<#b`E)7t<mTRm2CLwl(JURu0kgfU(4KQ4
zfuH|*zHVTh8)QLy-mWbm=g;BqQbFz(;0vEr0Aq6*3p4Y_@-GG~SaJidEG+vs+V<@M
zz%TYsMSJPTe3odH=;ECo*p)g0I_d=Wv1>G_+G`XIUfdcIU0$9Vfj^*yM&`AN!9h{s
znQ7_xBnO+LigK*+(J@&jgUM(x{SPj4etyyHyh3}XJk%j#1})Aj3^p^L!DuiW&B4YH
zbFeAI7@Fy@+4Aj~IeCRa27~nL6#d-|1~h;E$l>kcjbGH@KikFT|FgkgbOxQ*JH_^U
zGQ*<lAy+PP(YlVa+5Lx@%^C8Kx2eE6;SL2Zk(av_KUt`_sM2_c2FTTo)W>;rvO@NV
zsPLc+yLF*GXlC}p{KY}hR{K1MZGMo$7U-B`4J@$P3WFBg7S6NJ&z@-oPhp_LYIoSd
zms2#mys2KnrNyOlHr1;Y0n*Uy>Q`Resyd5XU5>QLlF7<|^5|w)XLR#xbGP}#rNv}T
z9Fvq0<8KZzzWmE@e!arYJ59zVx_L<BCKs*TaYl8QnKsWM&fb^YE=-o`zKXYOs8{@)
z_lLO;jFG#mJly1qGxVCQJg4)J{)2UcWae|7t8?c9_q83)kUWna=jF}6xs7&SG<(`3
z<jG{!SB5rv`pAAS6jxd2;o<Hqvw2o7`E`gXEYK8YF%9)MnGC@OlRv(;X5$ExS)*}=
zH+zP8_=j1-LPCw!;LtFWW#+8xkt0W1O(TMhCR0vs?g)!Dw0vv3CoV7N*7hC+5o3n%
z4TVsunIWQs6}Sj@xi@Y%^3rG`80s||Y!=s$w??y#VK0rQmf`CfO_Os>uzstXxGb-X
z)-M*PWpboGm3$SsD^j0AnTq_8p;jj&-vYGw$W06*{N!yw;gErE>r+LwT+ZOKyuiRA
z`;B?oD*zyEZ&^DAtQ(}~JHQ^6(->TqH4M7ta{$uzlPOW)Stcu^fNhbF7%Y>cqXAmw
zMg|Uf3xN8PG{n4Aw>$>jBu{yfyT@d|vFQ5tk%ePlDmu<xOJC^~i*Bo&77G<H3P2HW
z$`_2Sm&tL!=F3V3m*pb>iWn{<<3Y@q8{>gJEpGu(x<MKefNhb>6M(%bFC^%Pk>Vzw
zCFlo;T-h&CAD~P7NoZ6VpQs;5lbdB>qJFTbk`<s}evUJPZ;PkKBHxVA`^fG@y`JJ)
Xq*oHS-jyLqAV*mAns20t)cgDw`wBi|

diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
index 0d049966a7f9b8b2f98a4669a13c8233158ee940..8516ce77fd32e97ec1bc483bedb106485801bdca 100644
GIT binary patch
delta 127670
zcmZ6z2V51$_cng_a_`-Gd)35Pqp^2QG<Fk>C9x!G61&C{jj_ZemgHik2r3|gh@v7@
zKm;s+h!n8_Dn(F=f=W?AQ4kfC_c?rj-~ao2|9o_3=gfJYb7ppTcIM3N4NVx89zSYt
zJLZp5?Vq!DnM{<mNq)=8hOgsglI;KeQ!uKso}!GY+vFf~=x!T^QU$|>x8h|Axzc65
zgN$)G$;%wRXf=~c<m{o#j7*_W&TZmk%;>$W%;CFMYp6uQD*DT13Qk#d8YS&FDrFAK
zTkWEfu^bza$I6Tf<?>a3km73vG%{L?GKJ097aHOb92osaf=toLG?C8l*T6_0(=Sw*
zM1mNvJg)ut(fvi)b>=Dr3ier)D9da)=cMV=WLYhzk~C(TEW71Y$9mUsvKuYuCbnCS
zD7)EmZj+f?c@5*ObDXd9GMQ!iSKrHEi&I2DW@H@Ip6%kq$YgSFr2@yK-&h$VS9g@l
z<nmKn(LyrjTs!FWa99MT|LFHSLHb>;a5xUTho+P<ySz^Eme$5%6-1LO;lKRp0}d4J
zuP{Wh-K&gmW&iArQZ}R#Seeo<hn0QVQZMC#rMzr-1caP2RVBzql2lR-I;@b5rc<4A
zz;TsqES;K^eS3?tugSVidG?Sf8&A@YWsKsmgN&OXe@X@4ZAM!!vwSOu6$cc{TDg>o
zGXAlUq(P?j2T_y>W`*jbW-ljUgq^t0$h%UL%RT;Z@XThA9de{4yH3Vm{Z1u21SXkm
zJpMEOCNMe>=8(MS|Hd4Wk2uwWSu5k8JXOlJw_wJ$V8;I!v;F_Ivt2$k>DLy}Y8gLs
zgD6|r0$SVxa{n)Ap}hD1HndPaD!T=<tj$`bOg0GTXmS~|M(!Z{WXu=5jOi>l(&eN-
zNBn2}FB8?XL0%`tHe<~r7@18j5F`EB@SpK-+t(Gim(2f%`>aJQe7{E}tNg#xcK?y)
zc<Cgw^{bPt?DGG=tevmdms0DWcePf?PBG?|o66%anYQ7DQnshXB~uH<PTXe>DdR~v
z_<!mq({7odkp26=lurCt>EHjW)P9xMDam4AG2cO^WTgK>b;B03vb_J+*}ug^2egf<
zEqu)D`yaKHD!OWU<NlLdrlJd-_v3$>a=xBCzWrZ+b$**wGQa=wg|_ffTetA}^-Ago
ziQMBqgnncHH=*B*|4r!sU&0QTV*ggBILsLO9lD4%A`86C!AmYFO?PLhWDXy(N=u<1
z9+Nhz{}gR!l>a#iX4J}dKh#5~gT{f^Duq3*@jyxrN|m1iJrt)?TBPn?d-Q#o2(J{q
zjoI&YSKn4zz7PG3LkMG0w(a7jG^}E}di`M-%nb61F!ZsT=HuCKVMmX4=oR`E8LFm~
zt$nY=@tuyxkttH)c%_QLQFnn9HvBBdan5Uj<Zns;el_V#drzhDHwbIrOr<#sNNzsP
z;rMB?h-04%bj)5($G_|W1PEM7$MsbtYVASi3x^ZHtpFERb|;MFH=K!1JBf^KmXm?f
zp;S8TbCOs;v^aEujsr)MzCDN-_Maxy%T}Z*Jtv9l5;}i<g3i-N<ISLy)mjOby?|hu
zyUDy~9(kSFKxTFpkZSK{(kxy<lHGrkX5BDqkGHARLJ`iyV826}Mb}8j_9aQqj->O=
z*U99V)ucb^G4U_zPNj~A6?P==dy(kiB2p?t=c1G~3?lPRUlZNg1~TliiN&$)b~^gi
zkVNW0nn%}@PErmz(R`Ikzc@=gH@lO>t(HnnU(vaFJ+*}D6xr%tLj238i88xVc5eX{
z_vlEfwOTrQ9U|3PE%k{0wuP=Y)nnQeszD{*8cJEzQIgkIlPi~UNneI;8z$Yzt)-Vp
zZhS;K86By$x=o~GS~W>_{YK}_I<TSruM=RgjXZkwn9Pi8X@jzCQhIQhOcu7Z#9(^N
zW$Ro?(rG!>HD@PDUY{n-*+IlGdI~ww5KR*PYjSJxQ<BVUxx>Ekr}J<65W^EZsJLX~
zjuAy}2pK-qjn04SPDJ~7YKd(v&HMg$I^X_19gClnW?758cZ;JR*@$kHmW++MOqFSq
zMdxXm<l>u_Y7BixI<7yG`5G-*>2scVKG=7Y>Y7tj{PZ>%c<DoawZB2fhI8bKXUl{1
zStFe<Y)hJ|yL5ifi*%}YlbIL;8Gh_fYzfP#^yl8hRue^~(<11q4;fA-`&W?poR-Vy
zE7?h@Y6=lO*+b_y=F(Btj+6%Y&~cT9j*cfuXI%o7)_0=w-<J_-Rm*MrSxcS5=ab=U
zuH?joxnykXA0(OGmQd?;BpI%z(peh`J7>H|_y4=+l*z58Yqkx8Dy1yAicBu=O6TVo
z0`yx%MDe*K&w4<b`WF2aErxqNCLLcp$=er`nP+{e-s#OGUwD;Jf83{*`_z?67ko<0
zJ(5&({|Bq7HiH!e_I9K5VOPmmw^9QC*wXoUKcn+uEK#iANKM_prP=2e(zzdcVYE#a
zVZZh!O{bsfJpMVAJ~>V%XP8MIv4gC9@)yYucY+nWtg)`;j-5uLz9u@(nN4&nw$L%u
zivSDtB)^$N=J&Q-%Lo0be#>g89-aOrhOt(X1kEH#XIC=+*M5@hIZ6^=H*(_Bn^ZB2
zK+IemmD-P~sCe@wGVp#19jm?~rTi8r)})ZhJ7uJ^VHX_--Xm(ANIF(OGQ3(%=X15>
z=;1VyY%QeoUn2>7lB1*QHJP7~NylbKDm}51+M~dJg)&c4=?*CRmQ;PFkzeMWM4Hxy
zl)i1z$+VNs*ani%97#3U@f(%iKSD?TDmj<a^7cA`p(Lmuk$zz^nf#(7p`8Dw>b<*0
z@`9E-z@oL2$&xMPL}Oc0%5P7{K_iK-<}0e}#2Exzv6$qs-3feq4UyJPAc<i%9cR5D
zo@@K*T(Oo=J!g=nTPk5E4j~sS-_ZHtfn@9V%~XL5PZiz&<7QK%<$OdYm#wGs>=w8B
zVhjxVP$D|yNCrBOC-BDWbS}g21^wMRLfvgg@&S=#z<DqouSujcI+TuczM<pTNYb<q
zBDT;HGVf}Z)BP`-LPQf=9zt<bi?Nnh>WisV%WF;K#Ln5&q^D{KcBrL)9QKIJH2M)~
zw@6}0iX{EKGgQ|$iBvi*feerHB>DPx#B=Roi}`niS}_=$cG=V=1X#O{0N?*ifJq|>
zus50jeYes1@h5c5l9A??h2%uz6(YLx6QNEoB<G5niL`k(q5fD&l8f$y8rh55rXIs}
z+?WY;3~5dBjFvZxUDa}1wf=&rcPG)Y`z|uza+VClPNws`->H5F9SQ9JPmAGsL=m-=
zsGGHP?uxOxO4i;&lJSG-e4ti=<Bi`qlH-!8WG6z%t>=3kaDFOE!11wN!y<8-O7$M*
zO*N?4OMtw7L~6(<!?RlMgDq8Z$hY00`{R#%azc1T*ju$k+P<Zu^{=AywQ4#(l96VL
znV6^Zq&a>WRi@lbod00vrIfYHwX0C@u#^D(o{|CIfuvge6ZvSs1F4dY=t`byhLYwl
zUerQORd}Lh-h)Y}6=qs0S?B_~5Cap)fN3Ea_^dUxmNPmrmCU+|<e38qyVgp_<rvhc
zWFh4(_rC^rwMv$WL8D5xXcCz`;!m)d=%3M0x#ZT@{i((aTJD24fkfS5Hq}gMx#uH2
zsM+&EMJkXfTMb=|x_91&8H2Lh!C%p;W0E%D{Cjf%D*8j-OO(#&?}+o6_Bt0pXZ`yF
z{QuFj6@2??EZvHWeprF?rG-@}U44(P@L%3E#I!qo49PYoX*8_6G3gmd_A|mM2z?k`
zEu8daUZ){<fGPU}i61k%8nA=R_!%&Ih<Wq`Ru3}=`=gBl7?<PppdVp=9}QzinZ|sm
z9%C}+!Ph|M8NDlxGjDhZgBULk+`-I4M<gN4QF`r#GFvBrEsRn00e3i4KL&skO#NS|
za0D}{64a55EA`q@%)&%)o@9odhcKFX*9N&$%;qF&{}^VrGw`v@VF874%*@^3KFu_h
z!|oZzTMyw`rc)a1o@2h<4YqiuUnp`3%$^jOPh_G30YA?;he4Rc*sdeFz$`ofXOfu<
zO<=jmw4;tFg-Hs9W-612IhitznI0)a|8tA!A)+vc`RQ}m&1G)=gvQQeo_K*fpZOyR
zh}+EZM6}l(X825S-(?EZfG=WJQomNr9O{mwj9L2x1|Kj<I<P!qdN>16$;_sgNfpzf
zKic;x6M77|8s?KX5I$q7Xe4fb&Sbqto$8ozzd-teInjvZC1Was-Fn759%T*8pwSS%
zVpdNBqLJZhkbBLn_!N%5W$r$Q!6s&C11kECxq1#|&CE=?zFXw8Xc)Cs-pdOf?vjsv
zFTg(jb^en&kpUs&ssCN&O=F?ohsVOw>PO>YcFmF%IA2>d0@FfL@35vTG<wfpjSBX;
z?}uYwAI$TW{f@VRvHmK0KOJH0nCY~rD{?xZwyKRZ>}C(Q0U_rR4hf&H#B`bn+drgN
z^Jf9yp#4?bn6&pG*v@#Pk5@S}c?qbN3v=-kbVIJpcZiWFcQGR7&#J?W;U};KFfU4=
z(#SBQ;nsWRhh)@shn%Ck)>ZB~7QTDSd(&X(fL!!PE<mowY+rd&es?i&$@0nDfx9lR
ze2Hl%y?>P2eZQfgb<%IpYTsoV=z7=hgnZZ#IW(ucA*!bQtzk8eZcKy&TnJ`@e}V3K
zCTk-qnaxayMGsQXT=V&#CJ?G-flzl5uK`u}p107~^vJ>MLDjSDA9N<Y_HINZsyBt=
zRQ5hKU!ZDzKYoCIr{C`!+Nr;P37j6F@k8Sd9P~Z>7?gJrehhXG$JPA2`~r?&6wt_I
z$gfvne#}I4G|CCXec;%%Xh-PJxziCk%iKqUXH8@ml>R-}0QnZC)h<-dnQ{Fc++NJJ
zSAvoHjUDuCA7gqV-i9Z3uh*0gCVPv&2~3N_iA;;f=b09llNfSSmCCeup2m>tEtgd=
zyhW|entU8veNV<eiV23B?cL76wNLl|iw5ix*9HyOGy4Y|`!;$2*uUQ)s?f(PV0@Tc
zCL|+XEvIq$*!w@h*>9X_QuJ*h1G?!~|3&DCu9(#|3zTix9yssVOix$WVH<E9*uE!>
zj}S8;|E4Ayl+$m}W9G<wOk?LQOsNNWwldXokn?2{UV-}nvuP(h^JCu8d;A!aumKeI
zK&I6T0FN{0=p7ivyd~gC=G1f8jb_Rv=$vDuhrq`(JHw%wz;quCtLaSZzW}(z_{Tys
zgZVN9mne^6r$Z&5(d5GJZDw%~z$=)$ZU9s=v#2gr%(rT2zG7ab0^Vq6G#y~@HIuUq
z(w*|NA3@bg9`hCko#l&+5bl>}BY>;)kuUNBo3DKNO}HN{KNbMC5c&F5C<~R({{gr&
z^1gpT<*dBVdU$b8z9$|gGUPSw0k|wrq^ovA{yha;3gikBmdNe%>6(?wcM`r_e)$v{
zw?ghwkK7aa0xjC>m3-S;RL0SvZY9`uIGhv!aC1201Wk8`19)pHeI2IV0qFq;Z3k!`
zcSxj`333?q4U$t1{V%~%j6=mzaHcr)e*s*o!{bJ}y!2eQD;*0^N5?0~cXIEEdVkvK
zPlOh!d~_1VFv>BWdx05SM{oUct;%s+`W^E>_hRd*Gg1Gpf%D;1kAmAc_Evm`W4|Ts
zfgf1j9`1d<4X=6S&^gN?8UD#5H20{03GjEUWhIaMZ_+^qfbW}WiaL7^O~w{)sz>q4
z52JAWJ@o}B)?Uj;B@$H+XbgK^HPsnLlT`C3p(tH-nQC@T^+Jxa9M#cnFm^|^P5@CR
z+h!g#U$UFNgvu7ap9}yGe#1y;#%Ttgr}`&q#x}sRhi=g{=<L%iJN-ZReiSpN296am
z?el;tVLD-<Kv~L2``}3#bHxb$a^}fFT<HhQt{^1)<dZXC&0BsW41_-N`!qE2m7C5X
z@srPPhF=HeAKHQJko^5CB!}gH+Ao6Uh<xcxWRJ>g<DnWTkNOG~KQ7n0!Ohe1k|-o+
z<lAXNeM{cQ3tr^NGcsTzPyTrwaQSj`K5zx{Sem03%AZk4>aIMJX0Ao@Ou9i!<go)G
zES2}V4bA)V?G&RblmAv@NA`jI$7LXWC{LqsLxr4cL}e=F<`EE9%Wtj#@UgrWv2^8A
zxhqyNlr{3wqu_RQxM)Y&76)xHl5Gy>sDZXST>b&x?{sLag)>eLTmUSEIt-=<Im}@V
zU8)?1=F`aKI#j5zVx!D=s4s!R+YTcmAT4xoqZ#8Jht&CSrpVzA&7O-LZqoFt)Zxf4
zz~6JYb{$E%!~LJp2oD@AA;>*)IM^My3WrXKAggkCcni5|2k9I5^u*!ERiJ+Au$Ro&
zI!yOQ?wP}}Hws+;ItR58G%p;!?g7<$hYd9KYj9Y$7r91<p>&;IJ8Y-dz*~n=MF2KA
zY^M6Ycd)6U`N3hvD%5a`VnjUZyH%0!8-zO)evJU^RBS#DgU$*a7KM~9iqc<EiCqdV
z6!zQ{f8Z%o+IK6ypx5#q#pOZ(Jrq&CQ1w)7_#5W;DIC>M^;T>ehB6<;p}t6b71DG7
z4k|LEq2jMNLV>u$iaCYwB0y1S0N|)1su*R*6eYNql|c$_FT4m=M4f^6p^7;aAPiIN
zbpqgoU2$zF5D|(EgOH6<nCbRBsW|NpFHR{^h65O*7&8*WIK|g_xCKrtDsuohr&zNP
z&crKD_5xd?A~Xu{^9qL!P`RLZLT)E3qG`UEqS%bFzA{xYH3NWj#YhfbTvFVkQPpLI
zz2PRLR}@t#P`##jXNKR`6(^NQvJ~=R(8*SGJ_WX$iiIOUb4&4LADqcmd_tknJVn7R
z)bO?<_zSQUC^!=UcNF@4NbV|lia8f6g36GTC}!;d%RR;ACe-Y{qLk*04-|r(f}9T(
zt+yblP<+}GI+cnpcVVJhVdxCuW5vS)BsGe@-C?O#ap-q6$#aFj1e!X<#m(S;sSw`6
z`+7zD5|q7C{OArqqe8s~WN#FgM?&+hqH8ud-zk1sj^=u=SbPL3j>@|=G%MYrTv!R<
zHs#})pxLh6-4?#>RQ@vsZRw=!Zh>7FWs(9wSLJU4Xxx+x2TgZnuODGzk20|UCiW_Q
zW&r1@Tsa;>ys9XsxL+wB4+}m@bvX<kP)?!owV$%bXi)nr+qUQM{2fv*@&rCWc`^+R
zd_*~LAasr?k5PyqP`N9IZXx9WBkTq%zl}yNOu1<sEQKrkS)duA+;JS5k;=65@bIMa
zj|kKyTInxA7^^&80qQvA40>6fQKn;UQh8R%6~n`Lr5=%7yD~x9ie|;<m4j|UCrRn@
zC-BM2`u)IPRCc7%R)I3q8@WQ|Fq(lBDLV{@-D0J-9?q01w@pOZJ>|j(2+Nc{L4cPl
zAB=#dhssHExcx{uu>vZUO5b*Hrb;>fG8}bO%}PdM-=b0tg>;*0|57-$U1gjGXLhO@
zJ_o`{^((zTTvQ)lfhAW}z$9?Ht5PY{wOjQw1)DrnMtZGzs@kW+lDBFj3&4KWGz!)E
zs<z!mI~`E{oC1}DssR*_^H=q{0NhPgmtn}=va7nzf@+@XhX=^!tN!{PP8F!!hX7Hi
za@mR8T~$CLXo^(5dqJ~A#dk-pRQ2T-@b|uIfD*YfRUid%9;jaG!TnIxhXN24s#*%4
zRjO(hAXlwQJP8jUt1hnu?x`x{2WZx)?3$~v^jy_O4(>Wt^-0jwtNytLV1r7ChU#lo
z|E2KajcQ;G%HFAZEk_OCtNuisK-sKHrofOR+wdGFwz4%@DBH$vZa^-IEhgbfHs~cR
zoMJy41q(6kH~T>r$6ks>`<`aI+q;7FEUUha>^XKa2fGRErS+gmWVd_*VG`>`>qr;a
z#nVuBk=;&<A1Q37Um;9mPkj%SbT%#u!VI=c0fd*?SPD*FW#va<_Zr(w9cm_<ft7z{
z7W)syTW+w|C{BNqjSi;wUk+P9v;16k65WXTtm{A|x7in4!ClDqeS+K_mQ|qjirB98
zaKD%xK_k0THtRHMe~+E^BU~$EeaFCVIqUow1|PARJCLhjSDpY%HM=T@8lT-k>uEJ?
zp9v7wvL9>d`Kx1py8tg<u#fv7X<#jP0er=#j)l$}_R2OO-m<GH?E0RaLXZCkw)ZG_
z;m8gB0>Ula01Cu!<E~Z1(e2!iVQ^+AH}yOcC(hml02i(?6OOua3#m$OoJ0`|cdqM2
zS{K^G?RA0bUM_VL@Sfacx=p;exhY7zxe43g(|)eqIrx;yEggnxr*U&fAj#lT*Fbog
zldppLYur!@9bV_grovJd*Zn0pv$+*44Bq7SO^5InxArTL<#Kaq7MRC<<qZ~l0q5)l
zU?CS+2i3dWoOzHIaToT&d?`2Y2sJQQOUr2GT-ia8KH$D0?nfN+5M>oy`c}ZJxFpP?
zmDOBF>I0u}Hy)ubPr0lRcv#C-O#<K<H=5eFj=S|Ok{8_L2Pmtzb9uC;(7-v3gY-4$
zwwGF+8^00;n>fQc<lb?kyMnEm8%*<7M?PvQG`I4>SCHGrm(XpwgI`9Czmw0(MB>c*
z97ZKv`0UkiW*2X$g9SH!N;w?e%@3i;*dD%u!df1@J%}d2p1iXkXuSFHA3<k7-zFV)
zeR+<i?+5r1Gz;<PSDppiA>MWn!Xx|)8ZI2=SI|T!kXPAJnd5vJjZ}mApN4=Xg#U-a
z5n+5>8FJygx--0p;P=oVEt22JAvwvfwm*V2n%4!xi&%aMt+dAR>wg6I8Gc?hlC!*i
z2`Y1&uLuUs9sU$8vfSnGUj)9Gk3WH=gx~Nz?B3%C9S7Nc{xn5sAMl-e0r!yKOJltX
zKI1RoDtXO!;H>6PWC8G)FB)!#w1%(k1)W-c@=4_C_~QtrDqrxrOTgFjF|<t4z++7W
zFI9eLHImnSt8u7W6Tg7WzvCDE2)iHnwP!)v%&(0Ee2bvRP738#VSN^;w+j<>DBB_I
z?*K9<p)v_7&cbJb0-irtA?7YrcL`}Pq2n$D`~#ic!XLD#xmVagqdO1bz9Y)KgulK4
zaGwx63kLTKfqJO;2<d(R#0XzZg)mkKq3-Ima5@9cbw-#^(UNmQ>2i1xFYKWwCQ&#h
zL)m#D`=$)f-vuF*0@2BWnZ~avg4G9>QiaH6$fXMpbwFGaz8(dd%fjshlwA?{XYlEo
zu;dqzUKawsM=o19nGVt$!tJpD<OqYwV6IR{bH99Ht`;h{h0eWUs8Hx;#WlDi?D`oN
z>_x&}TCXb>bPu6(PZ-?>x%)!=PSm1Yn9u?E2f_qeOME1JprK5KFuf8<l`w5Sgw;a#
z?Vx!gEQ^Kkso;y~wX#-lnusQOCVV^vWOag15XxQ%A@nY<7k1XbP=oMzGLqMJA<hNq
z8(~9#7;F-LcnZ>Yf-8*>J_u7vfoK+P8zI~xI?$rzR?*!6_x;3I!%=on{FCm4L*mF^
zp>kMkbp_5G5v@bv#ZmFsD3}ivKfeXQaj|8r6)cW%KrTdl9S@Z-(LSsLvf<(wnkPhv
znqiPeiecAb>7<xXBZO$N0}TLU#9SVhV#Rl~&U{*2|2b67h<iK0?m6*#Eb1FC?kmD&
zN))^0AUQ9-IS660*uEDuFN%k08kZ_|nuD@5ajzG08Dg0|5>0bibn-{`s^~EV2Cs<^
z82FtjK3#}hmU!zRayP^-G-|mi_SgyYIign$NOQ$Jy7u`ZMkBbsVrn7E3dJFg$lVdE
zJ_4>tbYF&sEf)WHj+&K<<-MVDPy8$nxH54_F+G3fqW2tdKNPPVfNzh)y_wLd6g$)H
zRVA)41OHe&LQAYq#F_}?-i!T0!L~zM{tFUMX$p-oy(GpJKJAk%gJIrVT6z!3e#!b0
zLLVuO0?NKp&Q$;oNIeW7J19lYkmLFDmx2uN;*b<UJ=<YPO^Y`HlHiBri1elpfJdbi
zT8cg<bxeY#AgSav0Kt+I4fn&OKMsK{T<Sr+e5O=P;iN3dmHO9gsU1CrH>6(F%ife?
z`XRX`v2T&&Nb5J!^Oq}aoD4*sbj}KVzT_E)<hC??1Cj#i-c;1$zBH0Yu1xyt5o-TX
zni`IzO3IMKwQ6b6Luw!?Z4;6w(qoF@K9$y9MN%ULuKAxxO1t5-s?cHaJwQ78<fDN*
z{h9=c{nOjos6^)n3*l~;Upt`SvvYLAbp2@;__|e5V|0IZ0XjW4(&VaV2(A71x<jqo
z`xzE-lzqZJ;Mlh<g>m}j-Uey^t>najjw65?IC%v02gxs@0)xY<!T<TM9*}(TelggF
z*bgA2svMe4L8&hVM-UC`OkvRxwY1PWayo6m8P(@FbVk3#I*@YAlCCg3b~0^Vn0RzJ
z<g<=m!}-!YT5$aP%_SJv%B=euzPK|3tjPH>(R!!_FulG5<8h|!R|vzHbh?C5j6L!?
z3poC{vfFn<Zx?%=`cXGF^*T(uv;WX|VmCXTUVeMn_iiZL%U-8&i3eLwL0eCD3=K!T
z*iUJWu#de&kp^!zY6FD(*&Hi0eb^l}NPO8z2VnFd`>`6F{_LQ>6qgTRwP%n$!pd(0
zag?1%jc|;8N%Qz1_BHh@!ED(-a4m$52t!#Y+l6kJFgA<Us>0dd=fjH=Y^z1E8^NCZ
z7?vX0H#G5xV$*1;<s_R#%LLJ^(^?2mu^I268N<d?*wr4(&Qrid96Lfpa++P>g628H
zo>&RsSvH@hIOo_)^n!|K>nZk@z;0XvXA;@Z_rdM+?B6c%DTy7Ngt7~4Y9o?l_N&tn
zrm`ccozhq@JseGEh3hE0#2y+2VFtT#BrIIEvvNOpbA??|3%gg@m;L}=XSWQ7iA;7O
zt*K_QLK<2<n_b=m_#15eT>x*gpKCyKi~V>gRC3sHv=t_wokpa$S-(7R7O;n1kQB1H
z)T!QK_jN#Wm#t_I%_26G0y@R4-BSh964sN<m$Gh|D7?r1xfxA*pS{%w&Xlp!+k>W@
z-RzFC2W;|v&^%<9ZbaE5Hv9)vt%CizJ?vJp%rt0Lv44`?YPOm}tB=`fG^2aM)==X=
zWfKRXtcJZ~L#~$n+kPMBpRudGkvwPjUjS(xyN|;5FWBT^@Zu#q&kRrN*|oHzq=5}c
zfx%a75^aNPWFNPO%3Ic>97z*fO}*0xwucWio7ogvMR(+8)Ihj}TS>379o&4f;KUW|
zMdHl)Hq-pymD^5XtzBFzdbPN53yz@Bol856WH%Q>O|pjzxq;kX&i@yXdT@FgGkbEs
z)7#RElga?!$2HLW(wn=v5;-5vgQ5_=+-!2~0Jk9pJ{{$(3y~b-vOQrokZUvC0sZfB
z?t82(D1*2|=ns{_T!4Tp8p6pMpcBfCQ-daqE2MSBaIP-}$4+n#k?<*ko01I8NNxyi
zjEdrZTnm+x92SvquX7hD9)F4(It9WQ?ivlGW4Tt;qH)~v<={Nct-wsft~|p%x`Vbn
z%lT7;;~Y0vg{sAKGmgU31kQnW%_MRmBOyG`Z5#-E66cc+zy+=>2xZCKw-jN#$jKv-
zOX22HKa|S#ufX+9<4Sg*ES>ZC49;Y5UHgOcGM70FWLLP%KcHg2%H6?&8s;zmQ2%+I
z8<&TtDwAvM4z?_ATYnhL=2FPR8(gnB5Z>hYr%<`Y>Ar@g94?C%mUFqS_o0HF+Y>;V
z&qZPzwemLSJP9fVT)!+(7jj!@d(9m#nc_lsxeMFiMUkD`G!>-9TvxhVO1Ki*B~i*n
z{R2<$aW~B{f1it{nNk_2plufATy{I)A8<Sc*B)|#>!A6FdoMw=f_oc@TqVbygk}{t
z+y>2R?(Z}>^O%c?fuSc{B&`uV<p$8ip@y@6L|d(Dxu2<JpK*z`z(40QXgE^G*`k2J
zOzB4mUveQSaIKzmUkJ?xZVdGhTlwGqMGbxUB^#mX$6tGaIvwOY(sG$Uzr7sEA-<ma
zxx>7h1b6_S;0O2-e%>gQ9pxX{7sJJ4{7_mF3*;ZtEAcq5?SUkSZ$q06g85F%k%aJT
z<^vzf-!g$MjQ6ANJ)G}OPx=WygZ2hR@fq}XILWuC)yrsp<u>F_@w*m4C5C4^!fq^I
zK)qcY@3#l`PV+M-*+FxL-$83gXZgGIY@g%5r&we>-+_9H1b%5XJWS*Tx)aXxy=ZWg
z#FzaFpDyrwB9J8WYx4lV$h!<clEO#PkUy3GE)<$+eETs-()lfkaOM*4NU!P)UeyTd
z%Y5-D8J@o@yyi53SNU~Hw8=HTZ8UVQ^Pbe(X7X3)^_|7<J^|8feiH3`xWRuyq12oF
zvvAPd;(z)AmokTU`~i;U@?AE7ERX*)9(MEjk7*6|HgBg*L<Rgew7gTuTRw*79lmBU
zi|6kye{u<EiueuVAT8!Ko~Tm^pE(GKQodC(%I@)N(%{p5{{1(|mGOyN;L}4sb}HB&
z@#Cr6sNh={LZy;lH5#}oeq9_`s`+LblRf4`>9%~rOB4%v%HJqOu7<B}2NioQ|4~-}
zpYfiwi|si-stJfX{z)?G^n%~N7Q&bOBnAfS`G>U1)xiHtFV$E4sP7<b<bP@d(${?8
zK;+)=N)6iZEni}U7ft*bic!Dg=YD}EdCxmu0sI3WkF7YECPw@S^Nx05DNPBt2+jT=
z-73rvhjg1z@*Hg2g=@6dvqPwG2kB11Z3<|dgiiyZ=`5rULvy(Z-_e}cRoGDlOS^>8
zv`xiLn7IgL?!xD8Ft}UDPXu6((CPr-SV>!k=JF7F#sKFj*z+bp)l2xD2ITvN&lbUw
zkFfbq6#5F;6ahXUoQ*-^C&Y|_GY5sGMCvc-bTD{GIPZ?+u&|z9d;!9Z$!NSIf<sTh
zj|y#9B6my}c^DP~g^pIR92XpD8WALfQ1~ub_}%^`?1l&@Xs2_iaNrx{!h{Iga2hTw
zqhb9CVP#kN9U&wPKrT{{)0{U-@cR+MlY*RfxkU@V;JX>+DWMqqp)e61LUWo};W-U+
z;)GA{Aa`0Yjz#W_;64iQv%(J)zdk3_yVzkcUMPA77ZZeMOCe1ZI(-Y$^TOF<5GDyb
z!XdmMM4X3ave2~}Wfz5&G!ae_I?n-Vs&HWla%n=^et3~CJf(2-B_U`tEM*9%!{O6q
z;cz38E5bS-ICE84fzADxKr5{jf4eR$TMHA}!aTYIZwLn{7=Ke}n2UzGC9I4CX^yaO
zAe_k+)>&XFPxy`2Me+sd44k<w6zzh+0)eG2xKN0D3&0)W#&8Jl3VwM=iiE=&2#ba2
zo?s~v?osHdR0t2F_}e|9pboXTFYI3goid@D8w$&XH&oFF!c%;fq<kop(-QC_AtDZ%
z6@rPHt5Uc=7AjT3-597;3-(V?_E>035&9>>oEac{DlA)%D%A*mv~astm^lx*XF|nX
zB+mu4FDhuS6SSV7c_C=u0RK|BNquj<5KW8Z4T2*rHop@34S@MZp%<+jy%sXa{WrpL
z>Vn@2$7Tc2B;=-}?49t-FA%;L-kIUW2SJ>O+BXYTwC%}J{Fy9l5l6bBowkboX+pWp
zF0Q6dcf0s+EV4VqaTG@1DPBJYyG~*fMNOT>9ce(gh+ojMwwripF#zu3y2;4x7M&<K
z<{`GF;gzTO4fQu(;sIKU*e~{{`^iWA3)|b2zM^#=ga^f?wDZ_sT;K=5A<_QkPozgg
zegRAz6}LFU;4!g&5n3on{3#Q;U@@^4zz}hh8g|3QpQukcA@+)fFhX2S<G@HUmI7~4
zqB}l)LfqhQnnFa2g=gT*Dbb6fS}|hP95@;)wm%BZIB{DbSWb&y+G&;LjJS-VJ!i#h
zJ>kqbaab@A@#33EBnjf=43s5`XX{|;yqHV-mXgHXG00sIpFe`z$>Qots9Y46OhyBz
zh-)lRNfmn?Ls^<wIu3Tz#f`0yyCeqEicyBRISgK07QgCC&)*es0xkDl74yG>`D<ch
zPjFusM-KvNruaGa>sey=TySTL=1{QR5J%JFbW^mfgNM1|NQ&#`iEGCq$rlIw4({9H
zC1+SF5U2M8OQHBRttsCTZA$^aD~>G!u1K6>q35qy>@@%eOT?@6t|}FqXzBExXeoi+
z`{JiP!B!?NdJIIl_{s_XJ`kfR`1w#w?E~B+an|P`tq{X$4^pMLffhun#MZP`uUec$
zyFVX`<uv7eBF^Gb_EbD|2%I&d^Em;}U#-~32f$}y-}{h07jOLrM4foy0?fY<XVKgA
zr6@DOV7*vIcXxw0f#OQ9#4(dV+9<~FK-p{Yd>455Mx41CfVbiy8Xh%?F0^3$PF&@M
zviIVMlYoB^=eI^XHH+u4?NMoWlzyb})E3E13lv+WRc}$aLt5Ab;ZAAcQ<!j)y7Yxl
z&eGiFK)6T;XnE3Ait7XJT~a-*<+({qXg`*_w2P+XyQNtyRQ5<~TEUsU(pz_!_mDQM
z2eqd(oCbGZ(w{Q`*k_l1r)??TQh$mA?3ezaT|7Qg(taeq(vS27#R2K+X3+Ra1II#m
zQ2Is#yuZ|+mY5Gob=1IzCBsi(3y=oUo8yS|L4^6EQffc6;W25zVyFa4V?7`|E=?Z|
zl_05eGlapCT}6YB5Xqwss-aTIQY2xL4@HT?rFkDv`xBDtE)WsY#9J^JDQ#T`nkeaL
z2vkl=d&WT+EnQcG<&@;H8Kg0iyA{sFN*5@?A18HSz<E|W_%U+lq!3!biI<XJfHOf#
zvL_);l(ZC1IWKMa6EsQE0$QfLAoYs|Te6f#@sNws9NJZzB7Jli_*AKhmSxhUC+;Xq
zmu~lliA&O@AOJF?75$K0miqPr;EMG649c!b$7ytRO-i6$V%Mc-nPAD3f=g)AOO_P)
z15~pm11*i;kWy*JcvEU}gBQ1?E7aUM(y+xya;2@F@HbEL#|}8es`kBy=51--d6X4M
zKhXQHQ0n<P4BnAK*Foj3^zJe^izMIiNJ=I5K)8KRT5%7W_oaDrY5&awDR>FYKa_@b
zLg6E6F7<3x(zX*2R!e8;tA@wY40^fMNa^cfuvVHD5BxLf#uQZag(Oab!I#p)XlT|;
zov1TtkQy(6<&~r~BG)J-guuhMQU<LEHc6vqgXNtRjx98H<$Ebv4oe@Tm$W0lSxQmD
z3rBS>g@?DO`zIr}RlSCu?QLo?40gAxC$|NDhr0e>0CuV;(C1!G>U8R^oYi7JTFph>
zg?68~ss}fsY?rzZZ9H>R=i$RurMudb;@7*?;U58R-=n@e6>NLe52?HKP<z~l2~YKe
zG9bLv&Ap(rPhB(*iMM*qb^!OQOILx$NB#Uba=z-w{zwj}AJUd(KXtAX;0M*=w8g_;
zT|pDDL+bIzAv~=1_zWHfsB7rWb3}bK02MrHSGW5Yz+>tY|3Vt5{)Hmu$JOU)Q7TB?
zt_Qe-)ki2`AEGXxU38)9i4Wjtm^$Sb;KS8jgHYcS>fXbk5~0qY2tcHIaetIWsTaS2
z=1H|rAvj~yRn(!zs?8So6sNxM4eXs&+lSDi$2qk>ITf$ILcL~!dLVr&lc?@{7OLmf
zA727@lKM$olwDA-p+$sbb@DxUcv0Qq50Iv)`+oo+RsHrgSklz%M3_%kCz8QSY9r0c
zGSvDA;4Z7r4McK9y(S#VRkhqspGRF&ms525y1LH?05jDR?YGNP|4J{;Z1sF4xNoQv
zri1OKdPD@+ZmG9^3ZHV+i)mL=u6oRHBzfw46qd+WkNpRlx7Dq;;Gz|%H9=r0RKM#E
zVUhaYa!?nmH_~lYqV60?@4r&@AO}eAsb~KL)%)tBsYo8EU#y2~57pCJBDw1OX<(~W
zNBw~sK2x(Ke6H5gd#p~~jUr+%)B!0VeW{)_0=atis5+=LsJRNX;VX41#jhLHF{|Lk
zYxO34PON;RKIci_1-?~p`~%r0wF^zM-l_ZihUC3^_+TU-)V0MZYgVsnfO$tv59;-{
zXbQK$(pJqHT2kMpDgPEGwreWs!tT)MD7dmy^X6M5P8tPuBF-9j+8gJhaV>@yu9~ZB
zA#~F?wWs)tyC$k1NOx;&`Dnd8n%zsFvsd#sJ@6iyR-;hnsrl-6)X7Wpo;H~6(=<+o
zYu=hewBusGW|0bPKAJOqVbE9eHLYSD&^%fJp`YdqeSmUM)A=K?_-neQA$Lgghz0Jj
zW)lledw}LN?czG38AV@!9Mw#t4XDR7dqcq%s3~X-#Bt3~8r=nH&P)U%SQ9@QwGY#r
zod(iyO}_x-PH0TU@F_ww^<$_+YC0MLh|+APuKT2Bu`hDbnvZCdb4rs<o9tpV)7rv|
zSi6RqfNY%RQ8RQ-YaUj?i!&M*8mgYvjPDNoInDQ<A{VdW??5F%bCyB~iJJD*Po39<
zg#n(V`Gj7o7c>hf6qc-UazZ0q)O?_jMT*9E5bUOEl(a;grdfO*xpYnJQIK8I*uUEi
ze1^tC)5y!3y1Qt$E1F9mVE3wKeK2ZxP1Dp1i0hi=bR%bKCQpGdOY@kP`?582yg_<H
zb5IY!P0a}oKHbtxq=93O#_umUnyZ;H2Eshe9A^mgH9@qa<+jF=7OD$0es+o^6l%;g
zh`+13v<Y4mX%5nct746omJ&-e-n4JHRCAfa>-RL{x<Pnf^Dl*j%QU8MQ0;O}I!)mp
zXx`H6^P%SbOXMDD*3ewIQnS2eu|)Hy6~b!GZ=(Qstf{F7%M*=SgMH!3r<wu^Pt<6Z
zQwY3P^PV=_J=0w72K;l4JMD6>(+nzt-!C+m-vij7xkE4GSDM$<i!^F>Q>(q!?A{8u
z-)N#}v%y<UyS-@GCe49w;PyLB;~?PPYqsqM=Lb#VJk-8fvm%Va^XI5tO3k)S>q6g(
zZPz|hz^5JBnb%==r}q5^0G+gdx`M`8yMvZ6U9|g#K*d$N>1Whwmv)T^O*d`$Q?R&e
z{|tx9Zf!RjuzF}yy`kc%ZG8rCFYTt)@M)iRU<u&f+WxI*|I>c$7_0*;eYA!g==f@X
znhGxtXfFjK@zctvV?C%Xqo|0#w$~x}eMmd#Ul=^B9rpwV1GG13Q^yhQN!o&YRNIf*
z;+QstMyi3@T<il=9@olg88}G$j)LsL+NGVL5~3Y?7&v>V_9NP46sG;<OQ?ox!)Wi^
z32iR5P=q$%E7*<HCip=mN}ERQbW$rdf+kwq!yP70X}7(FqcPe~u$ZEZ)sFFnzj4|C
z>h(@*CrJ>V(KhV`;H*|p_v1P35PYVtjMx4&6PyWlt=~BKmiQm1E@*S9GfCF2e*^A|
z+NX5Or)UQ(KrU4qNW;N2ZF&#Tq-&j=z<o(On8Gj_+O;N_xT00h0ohgUl&<jNnl^{}
z&g)tOZEeof4hsV=OFQ*zXx`A8zC!M%)_%hUt#C_QK?~hE*l`QCTy1y!D1$OjyO}oh
z6li~sgWW=HCz@^C(dN>wz`I({j{zvscK;rl#aho%Xs#0N(GGx@YWwv@a!)&#7Rl~w
z<L1KAGVKytN-NjSOaS14Hs}G!9%^UUtHAw8``~M+R%m~rxO}B{sT;Vfw7#^WSgjpN
zo%UnxM7oAgv~QlEPEWNP={xEg?fKmh)@o;BnNj&nD^>yUT<b|u_B!pyFW}QFZE-VH
z8nrtqcJ^A^{V9ZRwB?^c<*jzpC$#?Cq+LMa=6Bj7SE2e|>#z@nAGCAm)7oaOi4cxD
zZ-2P9MW^n7vaP!57g4rN=UxolcHL$gkvQq<=>r#MUEd1;xaj6BLE@^5ph4*_-GtZh
z&`mdwMilP4yHybG*2T=A@#h|01ig(tb>0);jF)cBY!vR(#pa?i-nthK5boC%JVoN8
zJKYtezB;xeR1WBB=%Mt}J)nifgSu?8>#rN}7|9`B)+2Bp(N)O6a#Xj8w(K3#HH88Y
zs2fs++;QFPGYp=;Al(fOu0gP_Yz^uZqWgFbfT6mnM_@2a=UNGTxNdhNgeP>(FHwsq
z-ROL1p445wfn2oi&3LGs(oI<jK#Xny^;)sIzp$pMjMJT@WtY>s$jR{cj4lPgT%tUy
z+dlv*=X77jz-@cHE^Z476LhU;M^2*d%sp_Q*L5BbpOSUGXdUmOZgeslI7K&&R*O<~
z;!5PwbORMIpRNo39d<A2p3pj6hORUUWtVkBXtVh>ot36V*L7FjL7l1VKu=nhPX7SH
zY~2<bOW&~T(o%uAse4JQWVdviC&O-zPM{fiuC7leRP%J3>6?Lko##=QDAcu{4Zt1U
zqFYe8t1F=O&LZ84o`4tY;wWBQq8metbEUd-EyF6^d>$3OuPddQZJDm88g|QdnBn0$
z(AlHuo68E_9eQC`>dvMBSfyK&3`Di=UOSXM)~Qc{`-v`t)=8i0dilU$jV^{_B(=J%
z_Gpr4x|(+oKG%(&1JXL3qX?E4y4oVR{Zi-i3#jXLAvC&b)ZL*kH(%>+)1HAhx*|Jm
z=y|IfcnWMyx^y|D?{qVX^t~>WUgjTkM@Ayoth1azZmYiL0xWIQ3$#68yS}s?%6907
z(EM+w{;(&6PWlZr2XNN6uSA)P-nBOpSA8svWOnJ}engp@zC0U3cl}_7_HFIed(wUt
z550yio~J%G4_<ibcha7Nefow;u<NZKM>`$&>qpYZb3Xc?PeH|3Z@B>Y0sVfubN%!m
z4uj>O-jENK!+K}>+$}(Vl$P<1=+{#G<*2^sKFW^ihn3^H2I`lF(szN!^;_GcorCm7
zdPsuxf6?xQ5d8~UstDCDe2Vr8)7R7ZBtp;7hQ~<#iDC$&^u6d^aZ-QY1KiR2aC%{$
z(l4Vm_89#X`tm1M-`^2F#p&-KLCwzUFVYy~oPH|BbmH~(Qz`zLpsy?iK2g8xI;7|I
zfw{;f>1%7ieL>%CF%Zf628vo=)URBGBt<_)0hLt!DSEYE(g%G7XEOA6uOhjuze2OR
zEBe}=FnCq(^$(J3`ku}xyRJV*YlE5k!=J#lEWPIh*t2KrH-CgW-O!I44CzgMF@+^_
z^`q&7_&hxyjz-AWAE-o=+}3Ywi(G*|`ctSB>Ss_u{f<6x84TXl_uK`xBK=3Rp;D~B
zKM{Zu{SWS7Db;VK4-Crm8Cp0~uJ@!Rz6bhZGlUQA`es^hd8GfB_J>#K@9BW3)c;6b
zf0f>iUa{5s>Lv)E>bFiplho+DmBK`={x2G&J<|{W3@Xp{Qz(#7rynyOEHCt{)M&Mr
zfCEsk-$4`A2L0YvD0`*vl>*lq^?Rs-Z}s-+6iIK=FZ~5g^G@Go8-VZii#MR~gMQ_B
za5wAYXa&sC@GFftw-{^`@!V?A(uLh-cs&hu+HO$sDBEGUI|Z69hO$|JyBe-hIAfO~
zk)qXZhJkcjxf{;^2Ka7+Gu6|>kZY$<fT!U$MK`<*t3QLzK11hc@WR{h7xirW4b{OA
z`WTpjVDmLNEQ00%gQf@Yeuh2Y!|p+YJ{wKyZ}6fA=a69>ErcC5+@Q`Nz%bkexg&<Z
zX{+E-!`V`B9y9z*<JLgKQn?-NeB7`x8`&Vk3<~528)9gz7-9%Jk0jKvat10IW*C59
zQ&NT-j%0%Lgdvuq^AUz%9fXmFtF%xOWf*)AfRhG>wj@Lwd`82yQ-;A5bB{69CL@V8
z6wC!Y&cM)!@wCCBq4oDOhLjONoHa}@N1e_Ya=M@}-Z0e*ekT}y+KOr?8ZIqIa^CPn
z1(hVjKALM?Fm&k#wq%1lZBe{vXrP#EiotOPETtN1hCwCG5cnQ7OE=`wB<Yf2st93*
zVdi8|Up6f1!{hn8Vi0}@_f><U9q`u-fBy+*t{W=Sp_*yP&qEEf3>%N2zS)L^iJ-Y*
z82K+u+%)u{Rg_x>pOyfXp{NsBat#lspe)ajU5_N+@OdFD-8RS$0#{(zY=W@RaQYB%
zcMN0Wkh9-4l!U^?B0~hNl@}XcK7?wC;Un5bP-^gLfX+R`ii61AH<aFhGi8Q3<DgP*
zSaJur2Zn&LP<dz=`wXOy3{728R$&-IfJ#Ge+IjNWu=NLMJ~1rrg@%1<(3iuf8bkUL
zB(-+K&(vW&GmN9H&Cd-p&!XCO2Ac}N7l!pcQKy#%A06204Zj_Ri3USyJPf`veEk}^
zMnlX&`1IPaHyF7$h9xw3cxza)2V_l#8{=T`oxy$#D(?-~{si?0!{GOTHyfruL3JIC
z_GM~Zye-C_6y)D(98O<0Y%^waDBNxwL8G%BMlTu;?lgWULz$B?ttA$047&^WU5rzy
zXL2>px(oO&<Jd9q!p%6j3pCx0t!VGXZsQu-&9cY1v<{kkjdQ5gJ&gMY!%<ITpq+jz
z!^`-fC#3s~cWIpBZB!%!zu!2BNPUbl8kG7PEp`YG7!5S5^E1{^%>AJ8I{_a08y8Uz
zbIADeZ>StLenGp~0*sw#nsCH8i#nR4Mi<&jbj&#06S+WRDMbg58-0#Y4TFqBe?vP5
z8>Il`LX3@HBNu9{p@40eanBb>!j0!H0e`~So}SbQ<FwPrMH=gA2Ue7E{Z_D@H14CX
zaH5SWYT#2w<_9<$V{D+s*I1+5I<!TcQKF@`)5eY+keo5z&!YItS)<DVm^f$j#E*d~
z<BgyCp=A?{;kCdg8b6^A^v)ZnOQ1<IzSaSF!8o=FNwRSo1q3b{yQct<W?W2nZo2VP
z+P8PfxRmyjXBf8^0e9JWdIVg%VmwIi@~cKU^=Q|O^&G`NuN!kWz;327f?}&#M%gBC
zXB*GZ8vPApW-4+wjeBTs+AZUp0&wRTpU_-7*SLzpU3tbibbI9+OR3kpZH#P(T!FFp
zTc{KoOZq_Nj!{MfguBMDCgh5YHw)oKv9ayfAhVYkd0OQvHGX&shwm9TPe$&(an(8)
zEHgfuf?T=LPX_J>#sV|&4~;7+M)Jtm_D5K%Fy?;`?n-0tPeEE`6sDqT)y4t0K=#;p
z`77X_7^`Sg+Ee3d+6qx)H25M{Yuxz^n$PUU#wfV)+_;F=tm}+Ew5<KYm_gsTyfoHd
z0ZqNJlGYs?jEX=cuZ$~WA#5~ecZcR{<1X62`^FeSQ}MUPd7YrrWL!fd`gg{!L*V^;
zW5=(c^1+xucUQCV={w{cO*`>36v{0o`!hM**lIeQ0K_(vuQznIo7Cq3++kX_0y;ZQ
zWv)<hGPS0eo3p7e{Xmk7>GQszaW(nSCXrpHHMubFW>WV6i@T}vB$C~x0Y|{H$29I6
zBzsLuXdLKa8b^CQJWbzCgo>Bxm3<S~_L&mjqR`tEv<%69lLLJk?_+vQovyEG<*!gZ
zVDjFHw)8g*zX=ZynR>TD*<sTv9%TWh+q;oFV#;WbYjD(56$0TgQ$QW415I-`!o%aH
zjvL`ckjWr`I@nY>0bYcd^sVTj4mG)b47*{b)qemOZrV$G`%jp%X#a17DaQ(xNRt}{
znxahk3CNu^xs*dC+7w0a<Wr`G?!d*EF49JwSd(oKJd87~rIGGw(>z-9I%A5XRy%8Q
zq_u@}Cc86|c+<Te^!`gQWf)MHXbPn8{CSg;5=oM2qJZRr>E#_H$)<O-$bHe2N)g%=
z(}HGLN;Q3BhKV%OYkK_CO&4gV@g-A51j;f@efz?-%chW409-N63BdKaYI33o`Zd!P
zibq^G&Gx7HU#2N^2+U`hRA*6`ZF)EtG&f8YD?oG8v@8nAEmIfz^gqY+&1L{|O;tJ2
z%rm*u^d#TplYz#+ZF+tgWd)}2GUN(P18I75$JBwQt#?i1X2Y2x(>?mEyVx|1<~k*&
z^>mZjOHCgigm3puOKD_(-?Ul-^JS*pl_)GXi5W;9nA(J(@gJJZ6r+4(dQPiF6((;D
zaFwPu$#AX8H2Mb0s!buZxc=C5fW{|JOzAJ7`P4LyewC@l6wwWUT9f-@Xg)LT_ysD@
z?WT&S;I1=0qVM%yn2ymc|H_m&4pnP3T^|AbYm*=C5O`x+at>v0O)M=DHkrab!1m7M
z`y~v%HzjmN?t{t606??J)EigC(QL^_UACChRv@?4eA@{u+suRaAh+E-ay2aMFx#^p
z1HaRp<qW)&Ir=%AaW;p1i)y==ThVR{S91|<D&A#&kbyEc^D)|3;clKi63*;4FDXH8
zkNI!v*Y}#E$QciFuioJHG>6e!$;-TvB5C`~Luhlmx4BOa%<ngU5sJjeY_!v|wy$~h
zELb{Vc9;fLKXcV?<PMr`ba(rk_ajWFJY+7Ux7uNId@NJ~%oFaQqDRcRPAEHS{_Pmp
zj+x)nGZJWiN^gMU=DE~$2bq`97MWo4+3U~@F)s>*Fw|_IA$6G9`6D|lg`4-%E9ZoH
zc?fhO%=c%2CeqxM=ABVybp?`>=0>`d(dO`;NKTobZHF^4=41!hjWs{~4#GI|W(Jz4
z%`+%ObH*G%1DdnuE$JXTXP(ptD)DAV+SZt0?)Wo&N;Hr9o92J#&27H`BFQ}MSKu$0
z>$*WF*_@sT#6`1XXSkMP{(LRUQq3n$fHckA?1o&rxxxgROXkNEUe7SUor$_!Hhau~
z$`$ilii=-0k3WWMaLwEp057ha6`ui@X%6rQAj_QBjl=VoZH}U8)eZAU-=S%4nkxf9
zddvLt2nch`<+L|D*F0hwgn8x;kx<Dux0a!-&}{R7r90-vG&I6p^IQr37MbHHHdAcg
z?E>>9=G>nlEH!tadBr_*65Uq!%{yquR%R}uU2OJp^WeYX)B|%k1%)1(U6uj($b6+g
zELE5#8bw!{+tIC8W!`if+|_2^FHrW_oIpFFo|p%?K;@~~=`?UP=HoL!R%_lxlhJ49
zX$Rr`bF*s*0Cnc})Ce!kc{H(pX+HD;Uew#o<G%$>gSomD@UP5WV}Wlpe;I(n*XDX!
z2Y6#P%mCY4^H;90)MWOfVC*~dI$G&}Z{A9`^#^m%U%)k+-<QFJqvfy-xh<A|Mxnl2
zEg!7~%Qg#Rgx&3ys#hr6VR=SBZ?e;3&rrdVlcmxb+|HIa^f{P|r5Ek6bF~!EI?pbP
z{UF?TvxL*E+uc$}8yt39Hq)mrdo1lYLuId}7wt;%u&hl5nWyD5dXIQnCjAYSeU{Y}
zi14;VdPBJ1^87xieJpJfVBXhq)=oX!0ZV(D@A_FRw5WK{GJygL{+4&WVCj&>MBVIR
zOV^z+5nvfeA-E%!>Nwz!S_)~JaLjTd6o5cW1pVO8aZ4u(Nd;LJG$0AKtnCF0A(rG1
zPzkl9(<*P6Wf*ly;g;^L>G?ZhaTtqigvHhl6^*p~MayGR7Ry_(owQtE2t>4HKF#k>
zS!!s#GR89U2av{E2A+U0&hqmo&^&E%*^G*wu{gej%2~_j6pBu;l>CGw(Xx-?@#igp
z1t?3hJfbe?f@PCP`(KhR_vor!v`nQDdWvNsP0&*<pAAHkW(k@AXVNXrR(NsAa)v%%
z&9J=2FDfZ7Tio)2yJBgHAz!uBw?*!nC5C=a@VezX4-=V|+8M}YS<)wiCEHSq9WTlo
zmR~9If76olEA9WhWpVx!g*lcW+WVVpVXd&6XHonCzw<2}Y183t%flN07FeR`cUTH7
zo#@l!JC@H60C3l0r+HYB<*X~piY*t;!?hBN&pwzawY+W%+&xPLeT8%1@?ajCtIU$K
z5V&&7f%!1&b$gl4Uhxm)6_%?sEUvU<(hRc7vfw9ZRa;gqNA9tu$`2|}Ec0l$<Woy1
zi=@UfnYJC)T82`j_?hK1S`&J1x&9KC>nsnd0C-^uYK2C5Y3V@o!Fr1&2b>L-DC#j@
zS%N-=<BgVY?DX<@ZMokcp1-lgT!z87mPzz=X_MuzTQKp?GQ|w;_m*`fp!r~#?*)}+
z%h%y3bF}_Ro1nH><LI0Ct=75EV1Ao*q8YjE)-76;?XYt5K(^ER=l1|OS$kf9A!lo2
zF3h`FrTKPbU9B%-;P5W%t&T|CtiiJZbhkE9P<gjCl;%Ktto?I<*lP{F3vLgqz6oWX
z)^Rji^Rjx<JanIR0KJ^Ot&#U3+;9EqIdVSMXWe1J*IGz>J`Y$6>B~2NYl%N9amc#D
zNZ()`w*J!-hyd%rC-C%$bs{~UN3DZT0DsKdgSJ)#TH|Ra^>OP=>e+*=pA%`Y^|zy-
z39*iL04~%zVGEi&%$hU>WZ~Aq8o*Cj^9o=v!rGHX<3(DZtU?lH9ZE~WC#@0LGTejF
z)^t5+PFd3z!$gerCUvc`R?ZU+$5{u^Z$zH9rk@AmjJ4Bk;LloXl(2NpdWYsI@m4uS
zsuHZ8H2qGrPNsF6^VX3bP)V|Gq?MWr)_exJWb1bypmNbV_E#h+R(2{3*;B3h2vjD`
z+Oz?{bZd9&#x7aQC>EY!?JyK}FIx{qqwI>c?_T7tS~V25zGgL2VE(!_fi~G>TBim>
zm}TvD7#?O@>$ijZhSl~X?B28vphe(Y)^7AO8#&g?ThLs&Rs}sCd3LLHKMM1$jafk4
zwvM45tH2uU37tY~Qz8uBvHH<xi+8P`(5$J*+Dw}Xi>-sN08nCG5eayyb@?%vzh@mx
z-%8xKPIwNV%B<&UIi%d$m3Blvur{9r;GuN}^;D0nzh<GV!fNkDAD>lP>xr$(I&K0?
zR9kftOgy%R)&Tg#dWr&}PpvT*0j#k~v@NFAIy4w%&#bSuAotuVr&XXj>sMEx`NDea
zbNKtx8b*Wpdh7J}Xzm8<K?Ram=*nQB(ds-J9=^7|u+N0uH&$QTYVg*2jXwBmvUaAg
zEk9U)o`YPobqalh>}WgR1}3)H6!ay-R@-IT`L@j#{|*MX+b}P}qh`B65we}OSxRs^
z*-Czc(Al<(R+e0Bf6(qjS6lftsO+*0djWfHwt#yy2XeQ)wnAsOEt;ZHdu%%g!^B>j
znl^iS*oM#!3s2k4A*ipHZ5@q5_Sx!a|E#xd8qI3=+gz3K!pC;{XBhOg?W6(20oyYA
zn8eR^uq~>6&{k~$r@!rr0M0|U8?=?<ux(^(nga#c))qtch%Ndn0FT;6(Zu(dZE`g%
z1=^nNho$2-zu%Aq*{VB3CD?W|2>1}&Hu_QNP}_LgUKVD%V+0`Fma+;yov>M`*NU*!
z(6bq78$i>mD4P#O!A{!Fits7gcKJ_QgFa=OvlhS@+lwQR#@d$Ck732x;`_jh)3&X&
zGvkb{BXvS&Z6UK!(Q~#He}XOE_VYVfO0ZoViCm(s*ayjZn{qsoB-=XLe|N!lj%E+Z
zHbD!`i?$eASxT|Bqgh(2?RGXiw5QqrT?rHEwsx&ic*!QXp@tc@1<^2n**1|D#;(}>
zx`XDb%_$G&uh~wxL3rJkbPtv?ZT*gcEz9;V)i>L=f(B1FYyoGWa?|$NZscy+mar(x
zu{AWIxpHj}*P|@Yb~*^Se6JsW?_^)?1+^mEeEQ6)*w*DZv`cKZ>9Bd<79R#HWwyUN
z!^v`6(<YQXuz65;>!IzhQs5rh(kWI}Vbf6ORB3agZGly`@$_b_wk?&z=40E266BuP
zo-cyUr?z$!2d}XWru}@iwpR85z(2E<-UIh@TN8boP-lC#7s3~|@`WIMX-lTSMZIll
zG8(7BHkfXWSGLI~kTlwIwQ%OOEtS@Y-`INJL-N+voq|<Owrw;^erJ<Bk-WG4AC9g&
zF3akRSB|nwE6sfO-g}V^Tb4G=kqy(z%=OEbmJKa?*(y_p2#B%~6_g<$Lx$`jTR=ee
zP!Iu`g2L~6`s;kobI<vnb1(06$2sRd{OJaRGt2$xs~EG(VHNKc<L)n3fZ8$EQPR|&
z!F>u|I57UA?Y$!-X&Q=7jQRJ0=FHeug03B5ob`okM;XiapzRo=hQ3tg!Z1=@tSjRR
z?fcvqwRC=QXS^kcB@f0&RO95y&^`+b#~CmG3F5^_px4@)@oOl3ht7x5KL=>Oj1B()
z`vl|QW^jIt74HM)BqOs2p#F>mCeQ*H0l&euK*k3h06oPBrISMtqwWwyPBW6|7<7ga
z84v7W#&!`DLKvkJ;6fQTzo0FQacn=#hcnXJVIhJsZ9{cXk&Gjho{eJsY>Tlt%Xo|;
z{m~3tnw8Em?(YLR&v2zGy$g)UpCB2-ShN$^v5ZdIBVA+^Q#sTn#&e&;`#8p1=V2nA
z@zgdvOklV@0A?a%6V*>$W^8xG7$z|mQQj+=v8)8@))dAEb!fc8xK#!=mGN~O8q*lN
z^FY!WVR!K`gRz2ceqLqVP622p;|(ej%wjw#gHP8OKe3>m%Lp%q+j)$HwGhc?j1)tp
zfZ^^5X9^j4ROM5|I6$v;G2>N=P?j*J3n5u*Wo$SK7t0t`lpVg#*#9xOa>n5nXjCw4
zDOXj=*h5#xsu)F-^sHvQRtmc{jL#Q<)G`VvaBzb$>Ie_(7=ImwNIjz^3)l^erBt_d
zlVMLs{YJ(ctx#xUtaXLI&5Q&8)qXRqCuzsh!g$^cm{vyV6^OPm_QnCNo$=Eb=zRyH
zfpSfqjO$bi*TwLrJ$pCfFdd_M81EvNKd+auhbmHUGn%Mk>JH<NYPj9UaHM2wKjY(W
zkh_fUUIZCn+|7i@J;p(2aD$BZtaLwXh+)18GR#na2}}1GJ!5cYgrO)0=qSUTiW|om
za;mKyXYf~`ZGy3<1m-6h8d872ST2XbDaQOWkep^z2+_lbjNjDg#3RPb7H~6+?8PuR
z%Xs}GJhWx{&_UXcx#dr)gR*BP@4|39F#n*Fv?FtrR&XcgsZ}7(%uo8EafIopf%&7%
zyl%LEjJbeL(k{$@r~<;3S#t#<Zp_JTXme*iNpWEhW_1<7JejGqG8||2z6?jbn4YhJ
z^JXS}0}&tQoPY3r=6Sx%4OCuqg83Td=KPq`bmj9TvyWmb{>(gEcpAWD&xNHx=B3x5
zc#0|f9$XO9?E{e0OyyQQJj1M(Vn~9SX+hvZm@8>52xT6k_)Y}#?G*SM$u!b7K8m?I
z1l(EXwiA>Gj%JD|nsJUf#)NO@nU`rFaDn+<I{FmDOk%;OSmp-W;9X=!dVssceC%(C
z#4)?+b0zW2F{&<1V9vJ#m&ja6`IXDeYqYQ=G2iO~N;31x9z0B8s%3EI3bVcuB$auX
z(ks?9<~T*G(wTpJ3z!V159L>`GSgpxVkT3)1|*9aErN&HOnC!_B!}soj*ebq-k?Fu
zWiqG1<uPBUgLFRA<`^Ukm|N-OU&v(ALAr?PlnbtyY3mQ@5@zJ%;7Xa9G;5VvnM>%c
zyv|%wiXN6T8zZ4n!F*K>>`G=beG{vS`P+T8RWo0tj8zTOXDLk7G9?rOzQL5yYgoth
ztb|@YGm_TD2Id=-vAW6hqGF*&=DHOiP0SsqfZ5DE&;W9aX-oUk7N%9=iN;pua}>gA
zW1gYxLpw8>?p}2;ZAW3ZlX>kfNEdU|50<)_47#S@!~CZcq?Z{)xxm}ZFv^MFVLp5p
zUF%~OOEBF1%=xs|+-3IA25o@(HyxJmF~6aM^dM7W05`;Z%ZgmcykTa*-*D<a^PPWT
zX@n_y3C@f%7t&9Dj2TSH%W>x0CjdIZoUDbyB=f*Ja1WTl#{e_MT;&3{r<re4G~prh
zp#wx7F?%T2JH!0k4(4Z>#~eUxS)W8f!H%_@q9FFH7n5oIb6{z{gj3F}qZFb%!g88I
z<55<DCp3<+-lUob7uM?Ef#%A3v>%q-SS~A}=g#V)<D~~nLU|5PRw0e^ahB?7`0K^0
zqBEm6>k%EDeOT#qocCod@`u|eSRxhd`LS{qQ61t*)_nTS`m+L^pdY|`n=U^EvL=*p
z<`k>;BNz-~^-!?tG|Q3(a)xy}6efaM&&5F@gthezD1@>KC!r9=`uqzhgtI&-q7%WI
zPlY*=tWui8qF50$dz@uOWkMmEbqjSL)_Lbx-$lZk^Q;||!nwdw?goir`R#$<v8+)#
z&tGJD9)jW})(}<3#9{Q%nRpiOXP8J}8FE1qS$z7<TxNYsC&47vMkk;ov)-X7WD3iF
zKTxi)4p|_Q%5tY4X&TGE1DMuy*1=I&%3v+IkEd5zbrcH9WECetF^k2feQ7o;a0*-w
z>%w~2y~awX=`NQQNXfW7*0Xe~&S$w&!n=UAi*7~~vdVV>rHFN#O2dj-y(=M7!qQWr
zbSdj^dc(_DzwQIdbt~%_l^~R}@+cKj!TQVv1}j;6=#*N;+D9c`)hq_BaW$+qD)+8s
zO*{g3gLQ+(xsLVsA&Atogs-8kfwhIQ05@5SDT39=ilswL6N@JX*UWOe4@0+D`;_Qz
z3u|dBP+D15J30=uu?*#4+gV@EfON1r(m^^|47%vo#o9d#m~Phh`B1#g`tUP6yu;$z
zf%LJwhw!kUb*>dCcUi-9mwkX0NB2kXv3{d?*dXiU`4Aamz3~Z#dziKHJ8<_|Z(V}I
z2&>Lo1DR3Q`Au+fjMaY|E{?NK(w)2sR%|L{CRv+K!2APN52dK5SdS=5GtH{_5F!s*
zx3Gnp_lU)${r?P0y&U5_%WAX-m@S*z17gP()WIiv_G^ylk^}pLx8a&2yY)#xJF)+m
zp%{oWd)-_-J;Ju%44I?si~^8j>|fu5K^OLQT1Z^kpVFz?jlFmk(A?Q^RZ#F?r(3{z
zvUk(0b(|edxf3t;$`-ih&9<iCp$~g^CBS^y8YY}M!QM>US3h<iRs5c0%WqN~+@GCC
z(^ddGHWi?OYz6(~PqE#Oz_lQ@|EI8fnmzsvu+OmF<IwwHcE&q!ErgBuH(oq;(+t|e
z*oiur2xsR+f<&;HbS*5B-A^x76g&IBZ!55KXo87mFW&~ebL=}=6bC=g4xwth3+#Qg
zjK;7(r&Dz-do`VdFS5rgz+Ga`p;L7ndl`iY<JsjjrzEg@=fG|vJ9HA{GW#YXD)W-q
zg?{KnGTZnZETynNE`{V3wu18esqD~7pro<qP~}8Ad({gd)(rNGl!d#>Hd7)tlYNK!
zo5l8h1C812xirt^urDvd!)xq#F@`OdZSxf#=CQx$z_omKA6+CVV8_x{v5=kJjE5!c
zWw-FKl>G|bMJi+W(He7|{VxyZ%h`N;s8_JxC<Rw(WxG>_OBMU$6%egvA3OoY8urml
zXw<TOJK@C*_OdtNVIAA`I84;DzonPDfqniK`gD{1DeWp7*<opDYhvFz4TWYlkIu2T
z*oWw?Xkn**0t>C|c#4>}v7a`8w6o*c=u!vU+Win{o$Pa{Nt@TjUPqh%Zno{aXzXGC
z_#>R@WqVP#Z?m7L?c^P{sTc}<Y!g*1_OnA4LE$djk&>kY>`aQN-eV8Einc*^8lBsR
z*oJFB8D^WF0J+c34gtyt`)ArCj<N@>&jW3Yowye!#@Rm4Kx2aa%NLNDWWTlmXb;#^
zR30?NZlWFbG`npYFb~=9>e1~-?4CDacZQup0m51KCL<o&a`?_ru;aLdLBXCgF$oVH
zINK@o?8uRNz^)T#V?IQjIX8W*&^W@eP_F7IXD`LLj&WogL0mXNm+{b*BYhIsZk$b2
zG3CzD(bDe0IZcOpPfpKOkmDQ|N`-iF>gW&a%`wrM>cd&I19p8mu5^du1jj1~=KVOr
zOsJpabWnMaKL=X_yng|ld%YO1Kn|OBEvGntx?m83IK$K6PIKmc42?6KO*AJ2b5?Bx
z3E?aqhe9Z4?h~*S#u1%^`EZVj3JM}PDGM+_k(?JJ&=$ps{{n4iIe&6NqB&ODS)b#C
z&}ESr4mWfT-oIFm3#FVcavo58<`U=99gsNAjVCZr@toOGh$e9IUq?q1IiC$c|1t+L
zM7(O8Ph6mv%vsik&ZKZ2r%#_<;rx&C)~TFks@O>5y!{<S(m9s|=u!sf_D{gP%2~Dy
zD4Cqwv|F)eak{rdF`MH`dzc)~rB+~H<BZT7o69Nm0GG$vRFAfN&hf9n6>#37YJ);f
z&NFbdh*L*bZHhT3dSI!9limr*QqI%A!9*FSBmoN7IfARORL*HA0%is0y<O0&<jhcL
zuFA>@S`S*ysl9=xHJsfG;7l#&m*+ulaDsE7SjP#bWu=}I_dV=3aI)wCcaw9X3kDlG
z3n_Ha#9`7;zL^tlLfb9Q+f)G6!dce~(#px-1k%PiLRG=-oVgT+?%>QUgom9RE9*~a
zba6~y!(cb(m5<?Y59h5Y^rDxuVGa~;a~9Ih?+)in3a|EYRwu$zKc}x5l6N_=^bN}a
z&ZS52@E+#_Ex19BrXC_g99JW_Va@{z*Wc%?`v3|foM4L0jB;$hgvc0&ZKXMBoO8wl
zmL@n)RX}Ev6H6EU9&p~E3usduzuzD_&0%(ed&n82<Jcq4WHx#+!wI+o^;ynY%3#=X
zm(+pSaZ_l+YR~=OZ}7>1+vEokM{YjdV0Pl3V58g4+#@vQAK~iO()sTwx273r$GE-}
z{d3`tghStzYo>+3gS)pAz3}8Np(?-Q+`|+i^Wr|Cgq}C|L)tp|aMLJ6=F2_o2!#{e
zx4J<5xXc|uImu<wk;|X!y$u}<;O>>8FM(XwV6>g$*6gPJXApNWCDTuHRdfOS3^!{#
zxM1#MQSd2*+d+ZNP;Let#lyG<)`JV@rd)v+5!|KkK_Qa+2F0eMxM{S{ILi&`Mq4!3
zm15K9xWOL*>^wJ-=FSV;ehTx)aQC|dC6?Q8ht|J~-1H@I_!8Gj6>4$Z)0Jq9=Z>ZU
zG=XbNuVEsW6AAsx+#ye3CvmfV(3Z^2UJLUn+y^><Ug6GZf=DX2oho6|xG&Lrkj{;0
z#KR2k(i5<7mD@lWj7)CB`!JNnwdsetHJjVH7Eg1yLG-PJYus&ZAi3NK3X<e;YecY=
z&*f5Fp@4fn1>;=E9r+(Xi@3*WLN4b1VGj>WxarPNDCM5|6<itjT^Ss`&b3*FhvnP?
zDhaLNM%{#7CHEBy8&z@lo`ia}l{-kcmuk3gQmCeuyMQL48(fhSWa_w&(X>_1-S-JZ
z8n~}hfa@mr_ipsJky}8w?wh#3{0+%wu9)uo-QunehDZzd@vY!mxt^=h?KbYrDAe1z
zyA^P)gIi5!=uYm(El}^`TKB&R6Wv^=3y|sIes2PHFZY2HhUPXmhz#E0`p<_*AJ<Hm
zT>7~UTk!BM*OT`71Kc6HlRm`#>;fJRbG`ms<G9OcWJkEdDS(Y~f9git7`H4K>f_um
z*2CWkZZwsYO>);+DPsD7E2TZ=6!%-&+fH-$uZO{hTxB=NBkqfI@q30F_yfo+m-`k(
zY<U9|`m^JWE=4cwdBq_h4!jMOKyl;+#Y4}D=SABiXWraGC>-HEOK<T}ULXaYkMT~o
zqRoX@D5dw$mG|~i5I3Hr2*jPYk#;m5yszjMo+ob?{pODIHd6@Bi`PmUPjB8VRd)OE
z-gpCOzPz)PO+LYU;R5XX@$Oc`(n;P&H=yUwOV^<-fOk0n{SD-8AA;T~-W^-~VS;#n
z{XjXm)4W&?WX|xm(w;h)_dHF(A-uBJz=iUr-a}g$?`!H)IByP}=p%UP$3Y@_GfprO
z#q*(^-&x-CJy3||MN+i-9Pd}EL^#juq+-1bJSm-dVtA>P<%{KoP-yldPk<kUb>1aj
zxE39a<IVgFjd-4?4loJ4*(#7k-fl`nUgqU5f)`1=1uwvEGLIPu{S=;+K0|bcCtL?F
zQh6t|@FI<;rC5AAuj5x(%HX{~wF6gqYO1`?<W0VYwk+P-wP?%c)mNa+n!}s<8kVl{
ze$Rt`E^l}{I-18@8U*Zo-su3y6!3(r&{oJx_#C8&_ZHP!6!Tb<Kr7*;tpRo^PkR$>
zWxQ6pt#O^_`V&l)^NKV;so*g_0;%Q|{0_Hkcpmd$ua<Yo9bLL%<?W7uVjZua*2sF^
zi+j-6z^i6L^d|2g21p|>z6JVCymM4J)y&&N72&sd&Uav`g;z;&*H+%GpCQu5<Gum!
z+j*a=f!)Ddt$=zb?~hl}*2Q~_^2Ob}$gd#M!@Haey<VPm2c^$%^FE@O`yJjU+9vh!
ztbQ2hexCEcXuHdEqn+*mFQOS}_jr*(z#ineABMsZFM0>O80PKDg2;W|z!tQP@V=+J
zw4*#7t!869NAiB0cYhPWCU_sxZex-+Lq(Afcrxo>=<gKI@*c3Kd43c|eaLH*LE{l`
z9%YPXcxNfDFv|=05oosjjTFSP<FCC0V$a|E8PFW~Cn!bh$bWf1I48d9J9y#D*E|n}
zBYcw_ZAbai-{9dfe#Cizx$tAC_{^1mE6s{VH-6t$u<rb50W>`LEio|f$(K_J?Qy=D
z7EUjI%WkxJ^9$+Tst<obHaK7Y=m8AE3I0tJoblr)Hi4Yv_tU%W&;R^Yv<2`bE>I8T
zZ=o``Q+(AXv<2~3tp|6S|BOAwKhN-czl3Noe-oXTL-^mffeYn-eGzD3{0}J<9nPPj
zQ$qy5tqCHL{6BZ0Gg15w+L@o_XZ{yX;q&ROI>+DhILLXvDFU6iz+Xv6kQn};6biBY
z-)Lukk^dPTr7!WnLI@l=aQ+i?QjO;iQ`qS;zats?N&M%|K|h&)umL26|HnOuT;Yd*
zi?&q$YxKsY@#jzoE}h@!3G58M)CS}#|KHmnnS34<eq`|%B*1(&{|tS)Du=(70=(Dw
zwUl4W<qIjPYR%)1)}T-M{KBVUqJS@=lV%~mk>V&t{54BKius}cqOFAgkWwq9e951{
zF5};A0C$}qzZq@i{4lB;so+;~!Bz6_(($v3??6Y>YQB~(A=U7k1?WpH{}9D(Ztxvn
zhWR=xf9`2$)bpeFq4y2^+$MnD<iAFXV<Ue7RnIi>U#HipneTQ9<QD&N+Dy0b$KFOq
zTlo!i7paZ!LII3+zVQewb?`-0Guz4ExC}mZ@ekyKbn{<$2YNmH<PwPV@}Hzs>21C>
zj|IDT_~v_%>ErLEuv0((<a{*V<^M`?qXB-$n?SqAKQjq3$p4Yv#v%TVl_0}>#V|nc
z^Dj`OW`r-c1NJEY6*=_A_!~%JoL@s1p(pstXc(I0k6s4!1AhG;kSYEL)<Do{{&Fg_
zd&vKr?jk+n@2B9|41dF`=<h5)q69Fuf*87;X(xEL0%-PvgR}{E5d5(OdX9nv6h(Cs
zI9>*E7OZ*}eK{h~=Ybp*%%d~UF~QX_V7dt2`ftG#EYd^IP4LY;I;*)0qE`dWL$KyM
zIO8dpqVj;_f@7y3<0Wv|3-jKBiV6@P!PY(S$xrae7Tife4b8p&f)DAMM}VNK0ww|l
zj+8|_B{0W8JxH*L_NJ!=rBs%CMldKsCxQhR-9SPF;e8Z;2^HX9qu^B&_);ZaxZoLo
za1nx^%ODde=raQ?N-#`&y|aRsC}<Zgc<EnYpA!Vpf$_Y+L{X~?g2P{c#0aK$!kJh>
zJeBia6x4-d5H1N`rEOK5AelC-@q!C9cP0q_L0zkLUZP-}ibyUC{#^+7lLQ+a0h%lr
z+6;{p!M12Tydr3t4=z>km;~5qg5SmflP>6>9C(J{RSFwj6>uoHnJGx5hgkyFPteO2
zoS`eoIf6JU0KO*p#t3I}1u=`@TApC;FnVUq7c}$&yFf6H(g}rv9IAUN5_}s6OT~gq
z6#gj@<b4H$r2-x0Tgn7$s6O?&;4V%5<$|x=(N-Z?Lg|D`fgA14ssyfPNLCAe+y{{w
z!PZycVXa`-N%(X_5cd??>I5JB3Pbf)K`1Tz4FY%CDBKimOoH7;LDpiJXcGKPrIO8p
z&ZqG3mf%%7rL+iEQv|<N@H|Bj+XOyNu-h((Isnok_@xn`odO<}<97-A>GkgxWKnjk
zN8m@<>0SYovI(~Zz6U|>2&^q!!1M|B{SDvx1*4w<`>x=Z?Qmv5usRoQ_XI!FZGu68
z&kN|xkiah)BEy1gN<rNhL^}XxM9??_^P>Wn-RR4h;0xM{ObYrabpAk4Py;e0ILO7r
zX~6@kU3n<zq)~e$h_c$ksTsixMe=3^AJ>7{3a`||uAOk;3>58!p9H{!gOEY9t)uW^
zGB_vU=iv}>7QWJkzt0h2E9J<K3OWD1YQkjNx4H-)QU1<VXygOMO_=gJ)ZK-hr=Z{=
z{N!thcnVKleh>7x(6$|3cnP;2hx^__bs;+HBm9>N0eyw5Xf-_{tau5WpYRBs$WIDu
zQvvEPTvLR$0AZTX<Hwg;E2t>(v@n4xoX!Xr7Gns5h0kO|EkwBHefSb8)KZQ)OlY19
zE?n3^KavRH*RJ3qg;tuTqJ;M|K+X!QHb6aEDC>i}=Y$b;z&tPH6ob1UTtV|vjPRW-
z=*0?q&!J-%h0j{4_Un?+k2VHz!fP~V#tR=U!Z0NWUylZ8qR@pBSeJ#rv}2T$guEg=
zOco0Ngik5L-(P_G72)wVV5bUyrUXfvaP^O9OBeocJ@hh!3n$QaRk+Lqk||s<0);H$
zZUqJ_Te#)26$W#JpM3=EYr+k*d(9Qv&cb}2@Sl&+nS9|NR2x(vbf#ceq3~7)K#PPQ
z(;2B)=<_>BiSY9nfR+klXj@VyWKg8>y6|~Qh?WZ@sJ5p<D4}?CrSR+(fK>@!{u*G_
z!kzEZjrJPhvTg9KR`?C=ylx21jgYAms^~^Uy)c~qfnKAqmX_-#;gLTe*(@}tgS#a>
zd<ShU!p_Ygt-|;wkT#(s^`%`H{}~K+2xq9ix>LCL9K7ff20aUrZsAp$?0SSZ@S<7g
z^$NGsklq&NT?FVIVaskb_6d7WL!)2VbQwc>SNPyXzzhh}*TS`X!i7q-4GP0{VVsAA
zo`)bZER22*>i31Qbe<RyuA(_}RM_l|wlU$yvuGO^D%;`Hgiu5W`AK2ehZrvF10jd@
z_ftatA%IQ`qbL~qP&g0^gO7yPHE?D|xHJjetgw-;OxlV*y$!o|qP=wM&R$d;3p58&
zB<1EDMH2#`IEkWY*>o1U4T2mI;a`E_MHA_Apm0nS6bBI((JvHOa<z(PD0=E93i}AG
zyJ$I0Qy!vSltA_rou|^X<D#!A80sZjPTLx9QBE{^;Un5f7lD06!&`xULc}|SHa}6$
z5-6M$6)54MzbO0$zyd@CRQ(?)`jRdYoDzxrzy*n1>GKq)Mb^L-V9$tJsgf&LbhHFd
zLqvUJco-_WFbFP8<WAF6xM&Y0Mk7Qi5wII6;?M~%N|fjYk+Y)q-58)~(W#x#J12Tw
zi?;J3HBFKiL_A6##E6d5<Qyw{k#?UKMSZV>yCiC})<Pyu<nj-CA1_*C3rh*2O7bmH
zBuhePE{m@I1C1onDFH;1MG+suixkm5s#U)t+P?ypQbqb|a2cZYJE3<~bcEs;nIiT&
z_>?8OodCUTk-iovIU@f`kZYo&dtf$KlxDTU;XKjXv|i?mE*%0|foMk(d@B_FA_OTC
zrG5%hELwjKCQ3wd5%fz%2TB22CSp^u(sfZ41w+b39Et{3h-S*+MWx8=zfX0D!lL1C
zwdgY@^lC)dn&C|o`Ak6JhRCOdPSSNEKblDEMcY<Gu|YKG0N-wkk|~whD7yLuM4Ln}
zIH0Xrl-LHCTcVV6XloJidGNPYw9XSEZK6urDYlEmPr%;}Q5(%ZouagHkS@`S_hF%1
zw4BZpJ))QB(Aq0XK>3Ju-fd9;?VRq2=F_y*CrX#1YyF~0T9odJzP<tz1EQz)0rZ||
zWjO2(ihjM0ZV!o`*aN*`(GuGH-WO>-fjuI+^A+?)MQbR2I3{|K3~pSsX$mM4qU7x$
zlcKce(e^;pc@ms;N_0E{pwl9sXgqx=`e_c(9*LS~fITDXrC{i+==3;xXe+i-Fw{;Q
zN_Us+#V6;2a}eKK1I|%A@eDk462A}y;w*mVzs;oh%e4?WDt?M;#gB<Uy9Ns`;xHN#
zSMkD~&~sZLUb+P)+{GC_UVclhTWHer5;K0mGjH*N8gM@1@0LN&SL{yv%oF1Cz8EGy
zasPZ^o)qt<K(fDhlukMUVqcoA0>!`l2)$F{r>Vs1jCddhf0tmfT`=@Q#BvVWLdBb&
zgJ)r4hjFxpi{n|)ixA(jQuS@5*k(RPElND<2br_tC(~gfT6~Z`d2vo`_y?BGi_Jyg
zE{G342S;PX<{6M!aWd`OE{eCN!{1Bdlifgx6T8p>FJAofDxf5Y*HVBbQJhMVhRb3z
zrB{-~%P7Q`EMA{wg>Nb1p(<cs5g*HeZ>i$%mO~>=+$aQgy7-v^SjrGjP$AM)@n>{M
z&lD#vfI^nI{uNlt7TZ(uB1e3du1sAM*E_*(uK3(TsOO2BXnUP6HX{c)uRxr=4Pb@h
z@xLHaB;Nly-ES=xFWLab67dssSFu!_MoF<UF*_F;*TrL*Amw772#OWrkE#J$DYj7E
zR+acY2Y68}UR;T`8gaWFoT(Mx4@D1eh-WF~Qzx#Rg{69N!ySk;h)3vSpEt!@9|vZm
zn1!ILbzYNrdl}efaR>{dx5Q7;KC?xfw;kB6;-~3Y-6nRYMYvtOm=azc;w1VZb&7i_
z*wiI<-2}Vc;y<Zqr$;=Wrm0@>8am0|7Q41U;f~m!5}|$Ku(eR=7jvr7c2~TI3Ye_}
z;>lvj+!K3jMArtz`|>deL*lBR@o-qY`45o$;*7_jF(UpY1@4cE+tn~JCiWA7jElEX
zweW=4LR-5@@oM_9JrLLS;o+3{mrvo-v^e$!pga^0)POt^`%~`GR<h-Hn74aE@}^H{
zz*6hdVYE3(meKLjS+a}@>W@eqTOo2(Vx*JCF-hXT=!A=8{VkYvm8__MJvT`Rol@N;
z+>=o7kUT-z3QviEjnO(T@uMm=FUgOAko1;(Lz9h<q?=-hzLLdMkaj{6MAxVMBtF*F
zfH^5yY=EM_<RglF1xVEYLtg?VS#Lt)l%$G+A3>7H3xGK-IpBh}Gm>~p^94)%sH!1E
z@-&^JLnXU5Kr&1+mWH-)iHtmqkVL)$=t#+1Z$mOlGU@}&vy!S+;G!iToU_8<Im!D;
z=;3+E)3jy3AX$`w#u!OYGc3hQVrgEwD3MT_@RDRDjbWTb{R#BqB`2$Zogk^Eq+g;W
z-3R2d#AX@1NRo`uxjk7DL^tqKBqg*?UXcu~2Xv~$^)H~LNwoeH-bt4<QC=fM^2tt^
zzbeVn0wz;(=z9!emZUunFxisrF=)$?+@qh)HOXUjP{@_EMuN+eY|I5(zC_>wy#mR*
zG=~&Q_;ijglDJ(5O0i^T7`PHi<9h%rm6R_BSee9zO`ln~E{XaYPs=6WWkIn*B2Yu4
zQW8a9uCJ2Zuf-r#OC)lL)JUf3d{-;sy#%xyl0@36)k*%QUu?Z(MHZZCkR;88!c9pR
zy_$`ZngW0|NjfEX*eofeW%icj*SqkyMY8`2+N`Y-mwT|=AraFlwNtW{wk2JXCOUg|
zORiBOv`6x+7esp{zflhSwxq-s3U?&T%^-b}TT~|6FZs9t3U?)Xss<d8Y`=lFdlDat
zy$nhQj1U=;e8mU!u!Qq5B=1YUX@M6bR>@n7(Wg<#d=<!;#N{juj!PV3Kqe&nX_lOn
ztfg4h14%EP52qx&2Ea^9!lEGZP*O(UQ+g!1Mpt!bB&+CF)2zg87M!irjWU6D(hZJ)
zwwDf2or#0=!#BV=N;zzZI7zL?_0VvZZe9-1Bhqh~;Eqby(*fj|w1_5a7pZkF+;^4U
za)XGQw1|l|cj->rS9nO@t%iuFbdLq(xO4|qO?ydCQC`Dax{QA7KGLO5!1R^An+|e9
znoYMw{iLrR1m;QU(^i^S{iV-R#wb9#iRQOJX&EI5PD!uQX)j3n5^YIOOV!t5@QidV
z)tLlKpY*}Q5Ghv#pF*W<x<3>qt)|sJTslA_8zHrLKr&KlrZ+rFI(P;?os~L;LNZ!<
zl+H%yq&~Tnv_CIBbsyLlq-QBz9wR+Wi&CuA!4+*6rB(`AU6R(W0v9KJg>I|HOYJC9
zo*?B@$T(3tK{?0E(%`*tCQ14U1+bE(_h=WFB0WHR{VUSH_5&qVx?}_jY0}O?aOu+2
zS7=j~A-&cP_NtT}i^fc8F9p1_q{k^?l`XBOOB^}Uy(<BeCoS|xxAUd#6q_rMmSlqz
zN{3FPGey!cO1TtEhs)6I5^3Hlpp;4%6r-(7n#P1{*QGrAD1N#0Q>q83kn+S7UagdN
zH(_Y1r2J->sFrrq@2W;xLHoB_>EJQI+>kz)0(PDB)B%us>5|VN(jYxO1(BQ5v^=0S
zN}uY7GfmQGD9+I=t$q$}-;!$hXls#*C_mRKo%$DTZBkqM0k=!t=p%I24ryd1I@&2+
zNe7rN>B;pV-BRO=(C?A{wFjhEno8To+tLX7*Bp1GB{xC(q<_)5x?g%^5ZHI62fo9@
z0qG~3z}=Gyjc{#H>VF<!L(&E+1Q?cnNNe$Z>0P?XFd|(~OX{dq8gv3Kj!7F!fi^BJ
zqvO|vG>UdWlTvXz$OGvcG+j<fTZciWrN1~s;i0rz151yjf4l|I8R>6y^KVwVlBzas
zW#JlN+sWR%3C>>TPw$_D%#(6=j<RK2K%8VnRJ`RZvt~XAdPK&hjmc5jVY(4<Os4o4
zc3otSR6Xe`v!Qdfo9r{nFuThF-T|72te7^xo-%hj3m%s(E(7N!bEg=Aw`_!>VLmbo
zeRsoG_8rx}oRED=tD&Fl4kgx4%AWRsA%EExYa{+70kVK}fCkFk=z7H|*%jK}2g$ys
z3xlU+2s7fvlPz)q36=%d!BU89ax;7im3^KH^I@`+lmrWx?LLOKDA{kn1LdsjD<RaQ
zWim<=oRc}!!tQxlCJUXoAp6-KA~CXFsTFLj>^`l#7iEtEp>atT_aijoWE-MkB3_nB
zhx7zl?^SdyQRYFl^_OMe)1Ed-wu_d!WLbwZP*P;qDK>FMR(B9>sj?AUV5Z3g^pTfz
z**cp1GGu;~tGp`frG+3<wqHc$HCeI@ih^XzcFY0Ekv;Ph$TiuHAt>g`WPw1-lcnUt
zi+tIADaNuu_6c2oDU^BFqpe65P6wu9*}DP^LWwNsALy0Js%XnqCL1q+!gbk_5^&|R
zV5-`xkbU$w6e?xq7)o3-m7S(PdbR8c`oKtyEHW5et?bxYh~ALd_rudV*`g=WRxdk{
z0{0tai+s@0o3agyVX0BJdmq}GWG?jnHOn^At8z=Wh7Xh$SvVDuw90JzFrsa;p*|?I
z%QjLeSck0qCQz)MGQAgMx@271M0d+7=zP#4+i8M+uPpopczRp5hU)R|$Wke5&?no`
z4-@^e?F)c*S0?=pZ3D7dcj(=dz4SSp8I<WV(KaNDehnsuWxcyW?#rSCAR`!1sE^A2
z=>ZwD%0iw29hceBD>ETm{s~5QQnqg!&>qO{)B<Ko_O~xwo0dhTK>wl4nKI*#Wa}@&
z(v0kdH$Y}(o1Vu*Te*HcI6L{&4AkxATWMZ)kZ)ZE;wX201;j~ie-2<r<vW^S=$PEP
zc_~C)<Sn#wbd^hYg1E`g%|%Du<?&i@9`gPU^w3j&hJM}0<t|c~@RBDdLBw0WF%+DS
z+@3yx;wz7y120a<7disdPd@cC{5>h(vl(sv@;tg179h`{%GW@-<ti{w$xrzNN6fdr
zNflM6<*!Eq>x{f`A$~`}a%(G$hsf9VfeV!{p9Ex>T=fmq!sTsxa1nAB%2r3pSq}jj
zC3mFjE@$PxG=N0Q{R@G4PX3Up4$sS<d<4A<a{bTXV&qM}@F-T!r5k-0<w7gfv0aj%
zuLT<?zd)Ca;^i?k9Vf^?IfX$>l<yybYnSB*DX*O*kGl+*WVs#HX{5-RXQ6&YUNjAb
zRC&V^aA|Tsx-^(Bf0K4`8S*o<1-L2?^ny>B^6Z1a%#y!V1NCfq?Fj9GbL3A@>GU=E
z=mqHK%G>Cdo+p2j!VdZJ0;)DHkYAw_WuZKuBB(|34c*W$mbdr<yF?y34pJ(AYYRGB
zCQo=9ZP(>Cd?=L5eG{QxA>VlqhAQQc)nV|e<bh!rr)v4O*J%x|k;^G~UMtt#hyD$D
zC@qO~@?%C=s+U(6K(Rr-)d3ne<-gB?rAB!(KGHs~NxqTpJT}Yqw7}kycYO@5MJ}a}
zS+vSqwt%$BrS!XRm(M>Bunzh8FEPxW@>de^uuJ~hHd=$b<==<Fe2@H@SJ2;H`Hs0j
z>yx{E3z>fT69Le;E0<74dO$Ag0e4Rxa}y$i^5{<J4au_<z#f*rI1PjM<vEnT8Ik85
zhWe=d9#u4s$yb@cjmvFrKyN~Ro4y1&DgR;~M#lO;KKKf{JtZHYZPB#+Q7)c7lpps6
z_9OXu1~g{mAJYmoE9cSmaa+YF6b7(UO!J{<ulRsoUI#@p?TQ=~uhPlcNwNGOoN-o^
z)2`@<qK{_!qlyQ#bvUM&OapOI+-IZB)v8!`81B0%#^$4I?h5HN8a)(Qx6unvMIa@X
zk1JwN0?kXYp2`or6|P(0g^xl)*#Te0ca%y#p{NLlx}PF?A=FPQd?;1uuke_HLV#jZ
zCOiyOl+$&HQ;Jt;%O9k8mNwL<6;{`JuxAwaR)P&y9H#R15QPs-TA>OXA9xX_c;x{e
zhAY;@0wzMSh+=t>ia6TjL@D+MqwTCBwH#cu;&%!roKqN&f;+F+OfSa;MF&m5F^T}H
zJBU>rqA1Trg^CI+E-4<j(tU<FMei;&#w#*fft{eZ*#q;5iuNDi{$)ik`JJR-%YmJ&
z5Yv*FqWEnku&*dQt3gr~TjxL_P0>xs#dO6JFF_$g@%jJ;@2X-ig_tuH0y+|ADN^16
zO19!XDl5rRd^}8vfolpD#aVI{PZ)unr+BvmX!(i|Zwz9A;t4t%6)GO1=wFedtR4Er
z3co|($`o4~!ChCZrnjP8A*6EM3PqU)<|`FtM_{5#k*ot(t>~evAvKEf6A-CYy!2mS
zQgI}g5(9OL59a}<Uh!ulJZ(^{V8h@|1$zvNjf&So@UTgtrpmQu#mDyndQ0)$26U}O
zagM&N)T&sp2&7Fhw;X!yiXT2jUpf>E4gj-LkwK@ZE=6=9^tu(vbjs~f9DEPZy^8)d
z^#0ve?EMyscN8}tK(S9D?g!~t^lXRzUB&Mq=-Pn7i4Las6nd(=8&u@3h5nG@&SsEd
z#VraI+*gcE!o-N;9v9rGVyipc9#gENU)Q)|pBZ`+3ged$nN)aCjoJgnn}=Y?I;D7u
zWTq8o-68W(u_zqQJW@DIfIXwg{2b#otGI@lVxFxsmSQ+|%7`bSZ?D`>$3+L_1O;#%
zmCI>Oa#B7;TOMa+Jk?1YQ3m}3w~s0V5&(TnxsH|v7iBSJM_iTf9RTNMRWAD*`tHg>
zs!a4y9-af@sSGWG{&D4}$6(1zIYpsYZ{-KC0nJA_|G(6mvNaTvCzQ+l0OO|&z6$dv
zmA15(^jCU*1rnfqL~l%>vY7T(r<5PufO?Sf>kVi-t@Jz#FU}~fRSK90Ru)lpONjD%
z2e?qB?+j$ZlyaIi!<C*qSc*{2{S_oq$)<=~l(L+b;<L(n+FwU2%}Ze7oN}B7;k@z#
zU-b8aa+d145|!<HKrSnn96>*mlm%2moT{9loI{%OYb*WM)0N440h*<>Qivm4`O-IN
z%ux<oVWLzyOHsA!O2=;?Qmzc(0j)wgO~39+r3?Lis+4Q!+E}%6_FE{_C>PN|x>i|3
zHN-cRn<#!(uYBrLNH!=}(T(bx%2l)|HY&Ys>HTX`{?P-w&C2I1A=;u;dcjhwGCKu*
zYEynk#a`{oFB_rXp?q)|T$l286coCZyC@{tqg+S_wO-{39u#gX`wm0>j`DjNyguc6
zJ1E>$&d?TmK)IjdQumY*erOw1mM^3CZ%7$PnbKk9UW%IDR}RotdPLd!GhjxQucV=E
zOsPBrZd`efB0Cex|LNiAq%uwbpB^aJ&^CEWIr0v;hsqsdU_Vk`p#15Ka$OfBXO(jY
zfMTmU&jpH|ibr7x2bD|ioW~gR997a^&<iKk`8}}ftg`zB<cO-oCnlC<{U9IxbXVoR
zg${bC(td=4o~jTE-gv3XDBAC>noa|zk1AjbKzvpCO?Y@hwYUSsPsLgT>j5fzsyPl+
z{Z40#Q>ve-JUB?j-Hx`?s?Ag%ct-Utt^J{@1gf<PQ+22z60UmA`Z=CPsr2*U#aY!I
zBO0SsUdKT$sK#?)Fh=#o4w#QsNeUqur}Cx>$as|-ot_d@Pf(FblIrzWL6TKh#vziT
zy1fKkn(9Oex|FWk|22HdQ2qQ5z_L_}>93ouTE80J=cq;}DARgPH4+JfxvF<*?~<o7
z@!)r%%9(2Uid0h<!4<1&LeW;Dx)==XQq{#@p<kx*dlJr6sCH7hQKhPl@^V$GqZBHx
zRxJ|3e2wZgs>G;O1%3doUUiqwtPQF^C?0!LwJe1Spqo`g44~ao`B5Eoi>j1rFWOay
zUWCC8)m{n;bgJyB`mRg$%N3aDR?Yto9qmyqrPcGE>S!b$4ywLRg~*WVUy3jctA?mz
z^S&y8=Cu*kt~&r5Rh^{m-<Yc18*SsNcRqUzv-5-s|Hu!&HI?66u=_y8w1Lc&Dw6g?
z)2gQ_ME6itK+)(&s;3`^i5b=K`yjKbY&$%(Rr~%36L#uyx&dIX9;SVTgWB*Tz#P>X
zwh(brk5|FGv)cPzJUpVF8;dR-RlhR|v({tkbzh*-Mcp5T-n*(5bdYvaXSKn+yV~dm
zY!CI_A3!|SiA$m3t*(!NzK?njP0POO-zbHBLOtLN;-@}ci?);M?s&BMs}Fw-g8}O6
z473HRLso!0t-f#-j-FA=UI7WVsuk&QF+?431&yKVcPRNBrk)oEFT&N+lvasQpMMS_
zk?OT?12jr~o4x{cRz0&0`qAo%1?cZN^<H}Y&Z`q6@rSvf9;Rh8Rz0{B3K!LjPJvuf
z3ob(;PW?eSpySn>6CskIwkikkG)Y~w4=~B<+e~mN>fQ*zTv4l@gQZk8pR&Jc>ZilN
zrK|5a!<h_q2yHR1s`rOtNHW!*((fWmeeijpWUJ$;OgBfp>ou6Trv91U>0I?x5J<jy
z&Rswkskc&KvsnGUH3cvwYBw)*yHp(+4vjLkDjD2$b<BBal&ilj0(OPE>{GN=s@J~*
zQl;*rCAC_8pcLvgYAKzSYt?HgTYW=a-~>{q{@*q@dQ+Ve2WJ}9;o$&lQm>^@WV1TE
z4;F5z*WIEBVVm003$|VT7p<us>fb0y*s1;>Eq`6=Jygxztxj49(xd)^3QBs_+TSsx
zx7F!%V!ERqNC4?mXZPb_zk1PQFmYEcssqY^+L<QOd+IG_JRDX(&Vw_fYK|u)$J8SS
zp2Yh%uHKc6#tHS_LTF5?7f~GTfjVg=EKRB3`3`N<>SCI6AF35Wc=$*iy&3v5YGE-R
z&Z?_87)yIi`gb4>np{^HbksCaX@rwzQUe8N&AWTh&m)?}bO=1E+2#w(W18qdx&Z5<
z`JHAjR}EJQP&bY5YH;qF+quv`u4$!+o0sOvGf?!_u&Kt(M-xUL@$l93`T_KWW($SL
z{WTs7U^hVX8?C;9nx}VxoYLey09cTw?<ly_nmih{5RDT>7(z8SsOZlcrny0(-*C;Q
zYcLq0=`H{lsX6Zn&?t@XB5-Fl+vy)MMr&St7aHd@KZXMByk`Az^!I`$X)*K?HOU(w
za#?eOqRL5{Zz$}ZtV#1kTZ-nO6<}91Oscv_)ih^AFHLhK2O{ZK%{ngp&d|ht402WT
z0u|b2YKrUOX_ltl1zfh~`%Z}FXoBdMa82WV2xz&Q0uIpfG?5gC&e#0wgog#1HA~Uo
zLQM*VIg2!3uYsjv&Fgd=D$y`#b}!X<eE^g)P2P4$Ue{Qkrs}<N&4L~1T7@S1dw^DI
zifDgOrHQ)&Qmqlc4HGpQ$7U$jYFdNP`x_cJx}jgENv1M{dQBD&*bSO?EgZe6iAsa{
zM$Ju15HxAZ>2TAm@%|a)mgd84&}-2grD?KN^OkiA=G!zf3MjQ}_8x_$4$Wq&vg*|Q
zL*bS#O&p#3x;2+6Rn(*THx34SHSa$Hxvlw*Dmw0H_LPC^)4Z`B-uG(^9#Frlsrvy6
z1Dg93Nxi2T7K0nq1hqkONb`m_M20mx*3<fTUo%d(uSPUmD4sm3*};Xzm}cV`9*%2x
z6tS4lY@y4~lN#SxkO!KL<&d1xyh<<iBaJKV>t{4si_w=^4etji*lV+2frx{)ma5Sl
zwKe@9PTGQYh&XG*Y4SUw_1a4xU^%KCW1$zvv@>(iQ5WqWA41esyKFgR+_bG9LBm~p
zaUD!}Xxk|h@2S;L4*R&aPYy{hZO2v+Z*5LJ2G~dYXc16+wS(Kx-;>$}lwSAOe(MOI
z0<@Cn(X&9Uk}AAUX-Cge*;0^p6<wS-tz9<<PtRyaK8H-OR!fJ45bbFSa)oMrUIkj1
zR`@@(g==4$hqegqPD)xtYQI;ZElQh1JKM9`C<WX;uU$b^q!+XznwMj={xtQ+YF~aE
zow%rN9)rjw?H4xagf&h(F(0Dw+N5XEwFE8mZ^$HSRdjZ^to^eT`bpZ_t>BWip9>+G
zqUAmY$tzm(BwS0?UZP6|Y1(@<vgz6tlvv2n9;yTORc-nc@F`Qf?_>CzrTvH&(`@a`
zFxqmoJi6_5&8n^Pfp59mh$1NFX&X1dV7_)8E%XIi5k<obwSyFXDbiMK15B~@us_@{
z(eB&~{Zj1!<t59spVIaF>sn<9xN@!XHY6*w+o?>qQoGm*T$R>Jg^bnOB)Z*QqrF4d
za%#2K+C|W~q0LBzOr7@C$6&W!8}b53gZ3Z=fo^Jlrh{>#R{aMIHfdMUZ?#$b)m)(6
z(q5(bXp43S#h_ZXnau!e(|$e)u3fv74o4l@;q4fNPHh_nD7&;wI(2qy3qQpl?Y4HK
zm0tfl+K>>K=+k~onV){`oM*w^)jH6wV?g_3JoN8rFVm)dQ2YEEC=O}!DQ`TiJxm*_
z``RZR;O~ewg$?Xc?FTeLjcFMaGaJ`FNlB#%tv}t<n$!kUM(=@kh|U93+Mw?!ZZoaz
zZ3FvI>oEoHkv5g?NzZ80UIX^5cE>IdTirpbs<G4AA4M<hbr*v1&_UPu77RM-j!|ia
zlWqZ3nmX%3Vt{f)_az1DkLp~hSooN31I0aDbT3d2z*VQ(0OF?GET_|nyKZU)Ks|KJ
z4AA$~MSKfqj_W+A64*;OM!9=$UDrMI-bbguh=;y9yKlgq(D5mt<)_>I1oTeowosX)
zzpjE@3(&b!)*w)qY=Zeyy5Q4z7^IUW0Q$7<FRCy)qx&(73N?at8@9uIh)$6WheLH6
ze+CKDnZ5y9xNaLo9-?&INSHXQbEdZ<T9<Pc*ynT~uLXBrr{_cDf=)?^vKZZ?*C83J
zQ&KU}McqCs-@c?fc?ObkIu>1kjn{of^Lc{qNIo7~6LlVxxVo$hrEf(f>AGLWkS6OU
zKSN`R?m82_zoN75Mq8>bU_KPnbS4_vbX_I~US#O{qhRo=?#BY?W$H2y!fuw%oQiH|
z>wZ&#<mkLTAbCwUw+e=Gbv?AL%G2E(gk-)|SCfIK1-fMvODfbA`U9p&cWNUH7V8`+
zq*S6?K?#vk-QCAvsZ2LR$NTHLmnCQ`*L}YX3Kcr{|ADL2`5S>!rSmNWSFKyU26k(7
zc9egu)s^z_@P@A9X^=YIca$Kg*ID08fJTEZ+XJ57)M<7>qfy7Z4br5$PQRUIU4#ov
z+|t#*im_<X#ioI@>P(j~7Hzs0XfkNmt=x#tbm<n*ir1}kaf68-T|ZT6_UgXu26tPx
z+6Iz$bbBfB+NTTn5|aJ8PgYY7;;znN0An(s+eCS<d%6@l0}tvRi9v>R!Ve%atoxpB
zpx)Q*qa6H*PC@U{sBS48ea3X>efDK6wZ2M8p$EF$tsqmn1r%?b*6ELdd#HPjYO){c
zsuw_QMmIsVSF^hJXjf&cZ{Y*dPM_TcbM|`A$IulAeg0<XIqLVl3gV=ne*lus`fn%z
zc0~U*-6}n*e~*qx$Mo+|O|^?&X7zxgt3K!)p1SG(dL8E7_3u;ZvWGs9wiljyc0T%d
zTtD&$%zNoSNrX?{`V3mpee^TeAmXe4@M)l((5L8N$xnZ62f$A1ou9%(f4!d_NPs@%
zUFZes54*zOQ~C(1+6dCeUZAb?Y5fOOv~otj^+kXN>tCmuuQ2^Jik^h)8_s}4=tt?7
zcUE6XJEv&<(ld}er%&O--x&QrY7A(s{z+OmF6vwDppc?J`v)vt(J!PFX{ugNk<>JO
zCskvo>n%?JEJOeHQ}j*Qt9o}jvSjLCrlm1Ue}t0H+4?7`o-#+j?nzj>rvK+7z~t%=
zXTnmR-nkfF<m-2CfTaSx9i5*F_4)fS7Df7;ScnwsH$DZC68%CEP)hZ;_z)@650k=m
z{hoEOSFYcxr=`3?f93(6R_Z6`L$OLfNeQEBy|@?d*XSFw;7qN)^j~l{^cXF?2KrFC
zL|Cs6pl>uZ=+}os;if)9gg!Ouh5y2Cll~oQYt}1GP`IVPMwe?^^cp{qR{i9gu-B%a
zpc}T<cD)ZBEj#oMTzJ~4UqTs;E`1n%)1_Pg%5iW#`U<+_*{hE^1MaqdmbTJ&^p80M
zrcb||*2I4ONAzd9tACtA>;w9Blo-3G|H})QgL+dNJRH)mEdn>J-%T;L`}%KpLUP2a
z|Cjcwqk1F#Q`Is33qv5|`a^UtdP1LY0hT89Uo8XoK);si_NMe!`Uh;&`q*6{Gx|;O
zaCBC0{1@1^hA*Q5W@iYl#{k<K8ogo3!O)NaXB-VPQ~~2;_?^yz&W4wE1M`T%x|gQj
zqlS0l(Rj@811*0phMz6~&D9Xr34?Bi>SVOJ8)Bx>=3zKN2Om#^FYOkN8%o|rFT4yE
zio$yvoZZ3s7{*?wx5CgxY2Oou06I|n89t+$v6F@z+EE7@IJ8onG6<~?fgNO+pgMxn
zh7hVqIb)blWlzC|wRFut#PGWWBB6$`K7fW9o+FrW!x;S@BMdnd29GpoYCxh43~%)1
ztYP81Akl{55Gb58Xl?=Qyg@(#iwlNsdR1Z!v#$ds*06o!d%(VE@VkJ<ONNa?xF2T-
zTLz7I!`D~9B^b<9LYZjzHWSWVHaz<@x}9X0ECrWru-^^66ob;|tsIthF>TQ@3?e$M
zUNx|%Aed>`N#Xh|!+ZI7m~GfhXXPA2;qz#_W=N)dSFYhARrlr@`ZmGce1rHJPzntB
zHZV|V*#8jj78#z*0#|I%^rEfA;7R$<QbRPwLdpzR(jao(u*^!UNV&mQ0Jg$Va}XV@
zG{h{$P*fQ@4d_a>!S8W+QDb<4=BHZ25;Y9oFo-F~UT1KjDujAN;#P<>7?SA^anmsS
zH&7Z4pR7V#lOd}Idd-Ftw3gg5EX;zT7Q?&<ptKu4`<pgJ9fo_f=64#lRHJKM27xE^
zyA7MG;98I2<Tq&RH560L`)z|v0{uG%(`umg85VsA^?rj-2o&xbhGyZ@fZ-7RS?(Ej
zQl@Cou!w@YLx%Hnp+0PIN<`azL+~KlMhu_V(xzzCpoj$8m|_28FgR|gp<37p!?*M|
zpE9gcLVw!ufX+P+4Wc%{JTg?eLUP8?NNeY;!JeWQwnouy5If_BQ!rs~T=@p{9E>)!
zD{(Z=eFCmI8J`}8U1y`yVSpVmZo==tI`62FeG%r58C}bv=wf_GVE|WS@LtHc8KvPc
z;chJZ6lfmC;&mXN#zR98Id0rckx4J(Y#|<c8*i<IzdpuqXkYAWeE2xH6UI*{LG5P@
zser;sV<F91{>HZ{*AZY`L8(q_pz#uwP@Xa_rW9?EadjBFcG~zU?P1Rt7de0g8~0FJ
zF~sQb54cccZ49u(j0?)}Fx=R;7YY%^<CLO}G<wngGRk;_^2}$A`Cbr-HvUS*6X%RY
z6u~`jY{&<>V7#~;!yIEZzVas6SmV_tz`kg_*be<m#&>Az9cTPA8Zz<5x1*q+VBC8j
z<CJJTM;nOC#!h-wl8i4?R4m!JmvS8`#@D8xe#N+RCG4geKcHMknz8y_=%pKvQK?IY
z(Kj3Rt{Sg;p)J#By^6T`yd2}w=b(Sh_=rwAxyB0%pr2=akt!<kjq|AxpujlYhOsO(
zvUF%GGB%U|wAlCx#aBy=^BqA-jl)z}QDzLH)$_Ws_Yg$Njf-CfS7F@3f_kMf>P=Xv
zGJgIZI#F%>+xj>(YK(u;%3N#Q^#(+57<sf&t1}9^K<bSKIeOS&?4sbwP2&#+C^i~D
zw1GmC@ngyjH5*^1h3=LyA_;9R#+4{Xo7ZZ*NppOgaU}(d+KrqipwMBQDuBICV=Lmp
z^SX?0CsI(L+qi`8J@gn~t%qW-v5Jnxw~ftlaQKeVL_zUB<2EHU`i&ea#J_7?LM1u_
zMrZmW%su1rWMB^(<MzY*A*1OC$gpv~04Vp3O{;-2Vl>ko=}}|li!d~1j8B2yxUp~^
zl?_c8pUZ%WNuz+0x(|%UXc?I@{xFU{O&bGSp!m@E9A*0+8Ta?2ZN}L6Az)^W^^ai5
z)->lmJhU_A(X3@}N=Sl&gJ}tcx*Sal-Qc#9$=?ctM@=`WHuRY3hmRoQVmgEznsuJ5
zX^Sn!#Lc9mn7q5`)g9nGOvl#2yr;>d0E)*=byQsDWqR**pn01(20ZjJc~U8pujvP>
z>^NciiYkKrOf?h~IBEK;AH?5OM%DcRrUNul1e*S#sqB>L!RL4wWYV96J?m-H&bh!o
zWBNq~r-Dr#uL35-bd=Jep{Cq*uoPypq2j}E(}7UvN0=i12QJd|-rvxRGBspE@2u$!
zih)L(YL3F~bEX$51#;fBg1%pO!8EN0Sd7W&0H0z_RTnUn7flI=A#%xTde92RI8z}l
zQSqjOf1xqKluEhTL{ri@6fc_!Xh)r7@}cUDWYhF2z@(Uhn&9Xa)7aa1m}+vUKxfiS
zS0A7)-PA+tdxlAv2k)<%e(*tCrm3|JU|FUJIvix1R=*7MIVP))%4V;bmM?)uuIWMz
zWb#bz9BAa57Sg@O0@K1FXcU^xzmLuonN}x5q1Y6E6e1<2#WN5oHF?HDq|CHk4bTcx
zhzkBznx-y6q{=ig4zAkN`aDExOj(Cvq1F^kUxK+|I%K8rZk_3yRp>>%>A(VXyTRl`
zdw`p!7ypH5qp6f`05qBQ4#85hX?8itEmLwb&{|A8--Af2sq9;zw3%Mdfn>WWhTh^1
zQysl=ou=w+jBl5zr4i8GCe1<^>M?OC`qyhpu+UEawy7=w-rO;HP%N^~6mkL%_nU(M
zfW}?ZKnA!0lfxWf-!pBe=;NU2Q@SrcWLl+x`mjkt_Ydxy!YG(GVoIi|aMW~@BC%tp
z)o0<_xalvN3MWiv2}CAMPA<@UV48Z9cJfoE>rJpUZK`|<<{z3)FM`G+la_V{GbY<-
zz|EQt(IjMRo<9s2JM(k9z}cI(Pe8%J?AZX~XinV&gHC1v4ZgEk`5wGDV(#pP!cp_O
zldy2i9P&OyT+CajuEo_H{VIKx$IU$RH8kAKXKCB(VfJ!`K~J;G*8n|k=KlraWe%eI
z=HBL{r=aL#4w=U2oid-KU__8P`4w0?ZC-T`md=>((t;Ume(`%e3^5-NK_t}N_Z#{f
zX5K>Aio?yz+|U+bo>PT3YoyuL3yslc_j%AiXTJ0@WX_vEp*oQZ=C4{I8e@L?Cy-e4
zigAqdMYGdpIC{zah!P@k=9RRwh&O*h$AbiOt_7fpW@mbM*}RT+21({6w3kgbYv}--
zVqS6%7Ot36DRz@;HBUH$O*5C$i9g-!kqyxdvp1EQWtn5T@i5!$BSg1z%vLqXHM7zU
zB-ea|g2Z{|;vx8yZx)MzQed{Buu`EpjM6ei=5L?F!(#JWPh;>(%v?&ul$sTE#wjz$
zZA062v-P!1m?$^Da}fqB%pqsdSZU6n09uuKdL?A4%|HHywi>hb9gsTnzqB*1HygJ=
zq`~|l#ZYdVzozI%qxnD)>^7N;tAW{U&NYGDGB?nDsTT7!%8Rs`V^kQtHuGE^^xDm%
z|NVEQ4s-Snpmmx@=+;V?`4+u+-R4RaNRN4mKQwyH##69++dP*__3oHG7DKYne1=L%
z`ps;*n{n4{`U)ZgW_KAz=APMRA=(Db@eZ&wWX_rf%CK2;5hC}^;fEkHVxF^|UXoFB
zHWfFFnM>)MJ8oXN6wXYTBj`JwQ)cHRcrk5$@;Jyt^PXB*dSw1J3fzo20T(ak&6*#4
z3eL{b^*9vlEuT<zfP>|Qe%N)i+@KlF$+ET;cAYKnR)9NVDWQ9jM=hTwK8^S9n5C%+
zc3mvjUcysX%f3O#xLL~SSnqDxMRz(pEM2t3dRi3mFn`?AKx>qjW%Ls$cw1a)qwHg8
zrr?RM#Y72_6BbK89{O3*AHwcQOFrEa@V5j|;32>=U=O`O%QjSHTIZdz?7jxjAj^tz
zfS$G-Zh@sUmMQvbVX$RqA-E7rA|2gBErGNV3$t9L-*dR-9K9707Bd}ZA}ycWfJ9k-
zod-*2El)XNM58Skw1>E0`JLYI7)uw`j>TH!9dPubC7QxR)=L(VJrv_CTqZ2VTe9gO
zlwdJXTsF~CQV7w@78g3OC0TaTT$XIHbi$bwiz*I!S1fMyn@P1a{|Lz(OFh*zU9<c}
zGgGc5mv&%z78^=B<XfbF!C--9#1HC4mPPNQyTw+^DJm>3vHV0Qic-tIqmU`H%-;c-
za?6vnSFEs%{)x6q%U(*GRaw4R0kmpMc^oX&TBe=QcEfUt=FU2ctv9%O%a;FQ43>}R
z_juD{Y=lCi<(qhjG+Ed|=vlL+qXgz}S*&9w^rFS`q6BtZEj<zFVVgzuDP-C$;|n3v
zVR?*J+D?lr2l`!>_iF&!ZPC;DpvUq)CHQ(R_i3+p+Y-GI<c_6J1<XFn&%+Sux2%{C
zy}K4~ngs?d|4^mHJ<H<H@o>;$XAJ{8Wch3aWZ1&0fyRBylPh3;#PUlCd>XYJB)`Wj
zFH)>v+#;fF&V*$XB|E1qtLggdwB=<wj6SqH-v#rJEbi@iIAifx1j$)T8CC1s*_>r#
z5bSLv6z6fU*-H1$9c^BJk=8#an~23gJ7Tk(N<)s?WHMm>n9T}GcDmU7-2u+k=InWh
zxZ4~V1dNBxOadf5ZGtIscid*A7b0FZgH)j6ZSyjvM|^D5v;*_Cv0Vys!sZ(aC;Qpd
zEP~!ioBVi)_}gq2(EAr)6L1Mn18qEM6Mo7jfr73<Hb31$w@=$-8bHq2T)GDmY%};H
zIvQeAx&tDiHvYr#Da>Xqt?=PCV_o1PY~Cn<!AP6s6o-zo`9DY39hY_0#q}+-WtKKv
zm8C5kmgckf-n+D|X=aXWS*GQKsB8fR1ldDC1Z9JO%0>_oWXVuKhJpgJM5eyq6aSpg
zz2|(-Irl!laql_j{+L+-63ZA9LF6PO?>%@J$N0GngE+;=ah);4hkNyD`)lF&)lW0p
zrI0<tc;{<4m&kbbNwks}sVo>yWn2pZB#m*3w#Mm<mnr<2!C<}%hcg)$mIHp4QAVlp
zY=$qbMRFM5e*|)lvEo@so@eZ*vXu*rC<@u-G5l@-m(K_Yht2{<x7`e8A>+pkjID^_
zmI|2?#y&5M<|5-cD)KI6EZ+f<GDhsn0A6C`+<;^`BZCrVml-qZSz5t(k}8z1Fs@S$
zv68WG1m0IM!nVM~RYv-MyB)?}Dle^J@Mc4GE#o_9xK_t_^%jMI>ly8S7}_<)%GZHt
zV2n9Jrja3|0B;lHGr9(v8QTZIyUu8&h4T#tn=Z2!M*IVK(aNZ&he8`;WC*yMj9Iib
zZfE!%gZCYbx03+xWV~JrN4pqr{)~CL#aI;rv$q+u+4N<YZie||i1sk7tI*ra*xe3G
zeT<i>f~lVoH3`H$#^V&69ANO?gvcP{HL5)wW@Nnx+z4aSGIZW&bU%mIC_}jbUOZrI
zi3V<*(Mx%+3C6orX*kJnB`s5ottk+hW(46rvd?<N_=fgu4$N7Ou)CkR?;W%pnO)()
zA7DQF3%oeUTtQ2cL(Bz~VQ^x4&Ve>(W(AcFxiIHY^3atT(ubBCv#A;_cjoyWm{AYr
z%@8<xm^qhrnx4!F3PE@=CtgISH}gg!ro?`P8T=tk9A&PidKVw&PO2aAWe!tLz>nEQ
z1)9g0GlJlgKlAh$)C4exHvn*)*(ZX(fy|EvVK<1W_yw(CW*1eVgfKs&ePAfFdJen@
zW4`n`aN*4KSD+<=`F9HpMKY7R(HU)Lo}$xSG0Zkf?Zq;e)3*;!GOa6tk7JIPz|tvZ
z4MhavnIZ`gr<vKGL-GtWo(_5?GAHt2H;Kuh+*mTRow6k<%qWVKrZUGUh?~y*kO4pj
zlSzBaOlC?JeuJ}2;XRNnrv0sxu$0Z*!3D`-rsu-9bIj;n7}I&CmnT{mm^-O3CzrXR
z0f>C&vSQ3k0kb+7twQGc^&myeUnsj%%ygtvLM6-|+UZ_oDxQQFWy~$Bq52Zj8VHec
zX3|o?FEh`)0G$=gY`ZT^Tw!W&16axIqV(!j<|WEaR5RcD6l!XiV-z;4Wu9mOua5a`
zJ$UuZkLW1rHRkGVAdSo?=}buz^S84w(ad~~p551(5tm^12D2(3oo&p;AH(2Hrqg~X
zYiC}40W;IVblOJG;7%sj8>8rA`q1<J7Sl}ov2LbY7!W<o<}EOIhdD13B6pd+v}fvN
zuB?YMeay{N64TEtrd7ZI)A|@X2bu4*!R;ZY>k<HlnQ~{qN0{Av(7Mlj${nglnI10C
z@_^YILWKciOwTXT9B0~m;M4?D@G}ro%<gxfW}5knFC2czEN{dJA2I*k3=<Blqtg)C
z&w7_afR3yJ4kQn<YSkFaAy&;g@SIq4cLLzd+C!lL7givh!*yltI{{^GtXnr>&x6HZ
zK;Kh1%yJq5!jrY43);L`;t<Gqv%ZtT;UlcRe*iqniW7tQvQB*to*(Oz-vBtq`i*u;
z{;XHu0SRCwd;q0EEE5H~f?0E8AsNE5C88C|@@PjZj1`{?@55P*Phq+uSSH#w+oM=7
z{sNg3te&qR6U{22=x7Y<c}k7PvVwfjd6K1~HEJB|3EB(9v%YqNNCN98suVuWij76*
z8CEz2<`P*;=xv(BDhvTHne~JN45qL`H-MzFo}k+|jg@b~$kJIAYoI05&O$LT?gv&n
zrCqXE|N9?Ck<Aj(J|l;9N`as29BT(1wK~trz6Ft7){nFU%VT+pAeqnFM{%bDmLt8R
z3RxM;(JEs7=m3#o){mti7g;kY16#^sw*XMaYRCh*#47w7ymFR(#pn3dF0%^ggK!nB
za|b{wSq56BRk5C@_3u^I|0oVq&3d8`oi(hTKVW9+S#Jt4!fUK==v+ku%S<0YX=JT#
z0=$W3*oV$$RyXYtud^fvKw4P8rGd1vOf*4ltoLrh-<zx>c0J6uvp)Y7x;t1uae?n-
zc?^Mhi*<``|J$slBDA_$wqCj&Sl;8%eTS9W41;%BZ~O$(%lfMyxIR_`Eo1vxB}jPB
zy2n~D4>|`}S1FY<#In*uWSDg*7a}7pm%Z@fKI=oP9lA$Zm6XqVz-n0y<`|1j`<n^Y
zp64*oN!CBp@M4N3-ww%X)`HKV`yuOOJ$R2;Z>+#C;=sQBCx|2ajb=z5VE;zJ!h`Jg
zCXhqyUiw{~*j8HnIJ4il3!Dr4i;p4c#`a!B?>~3;*g|;Y!Jb9s`-j=N$06g%cA?$F
z5%$NQgB)d7(i_Bw&G-r0eA!O3;jbV2Tl$W~F?PUb5b<YQYT)5<b}!XA2eO^T00gmf
zi!kh9wi7KyLf9Q^fD2`J(ef;eopGLy?nSWUDE%GD-n|p%qu4(@4c|_%-`N5$qS+Bt
z&>h2W^ul0b*~`t~on%+Xg2b_B(NpUbdlMyw;@QidgUD(2H*|XE412H@xI}hOD*R1i
z57MqZnVq!>lb6Eg(dIvuot*;<_H_13w9m+3C(_qzGTC02q3tZY(grnI>@x`%(>ZqW
zJOIzL*>ufbU^9;akjp+pB#-?KZHDvNA9=%k0lUZnokeUL6)6?7@9agZgq@lQ^B374
zMZ#_=d)@cYS;mg0Rn8?ld(8ugUS_+}Tdjg!_af9>VHf{}RwX+^1l?8aO*7GXl|Atj
zI;+_qYT-o<TNwaS%Z{hWb{+c%+Ktw;zk2}h8`zmtvC+uB{SM4Gv0tM=Vl!L(E0kSl
z=Tf1`4fbk2S}kn*!%bkeu@3}6^d|diFGxF^Pb;_%w(V8u?qq*PVe;GTf2?q{n{5n6
zXAiry0E4;1{*~6aciBdYVDz%zrAoX$_Nx>TzsH_ag4O_A{5HrSyQmSWhu9_Cp=_A#
z`wv7$*qiKX;P12hDPj14{W-mI#@P3$LUWwmKozMI?95Qi-Xz;dajPk|b2WxN&2Afq
zwukI`DI_1U>*|4X;N;L{xu5ep2e<>A52@heASdBPSUSW}(>Wg}jyt_DojFR{xw&u(
z<0&@m%4ysLggYnT6UcaQf~f}lFsFkSVxFAMv`6&fjBJ6(QO?2>X!&qH`4}x<&bRlV
z+mACfA3h!9%(Y-F{+zlw7)t<WRSzr$az369M}s)|9l!;1R?)65g!42#tV21IHB=ZL
z#u3nBE1a{Co;Q)4@tr_KajGfWeu9%nZ`x?iEDGnuaJ*jwK9)0h7M4zOf@m!s$5B@S
zaEkM#KP2Nht#iOj;1qs<v7F)9lL1KN{5%E=Nu1d#NG5aMr}aq+M;Swfsi~Yoit?v%
zKG_Rx8JtDmV@fhPKed9K<&1v;L>4F48&^v<=LI%^=Q-ObEOLQUOwZ+9&Q~vCym=fc
zh0F3eiZYM_&a<1Lvyc=1HilHhIYt}aVvctVIxljf>6B6_XQKoj+RHdkd&BQboci}5
zQ_czf6uK)oofN#g!udu6UL|J}-TqfOd+4=a%}G*WE^0X2DR5fLIY&>_I?mX~AoZLy
zDgwC1$)vq>Bd6LKq={2aWsJ?7^K|_4I;Xi2%5HETj?xWa=Ol~3Y~|d<hHTbNPV6k`
zZs+{s0GSTXcZooBa$G3T+{Jm5a^$x-SKoz)J)EUAaQ_Y`K?rh}^H~dUy`0du;Zq;S
zm2RAVj=uqt_c#@Ip=^Nj`+A5Ba$Z{tGR$d10Cd&}$NozJT)fZGQWR^H(@!5Ue85T0
zftqo+h}HyWioOLm$<g(obDEQy1pGrzXcStHI9}_(bKt7!%Lx0qPoIPqNABWYv<`5$
zP^#h(_sarEI&oj1Y8_{8!{Y$BaPOXi+pgRL_KVQw#+~hoNpR<8(IfmYce4zlp4{~)
zoSfyweTUxu-rO{LXdmGon+4ucu6aJx_;FkRMe7(>_7w)|&t3NmS^-=yS|c9kE~aQ|
zAUE#}T0vY5g(rf!zh=Oh5U%zJ;9=ayooW3U&dpeaW&}5kRwj{LcX}{KaaR^#)}y&6
zC}14JUAi7##Bx385MCU2IX#e1aZ9KwKc0K{Fx*byPSGOmG&kxUNS@(-w+8S;?jt(d
zoXnN{0WB%qD!PACxzAIjV;XnkoEf<P(z&D0!o>{k!wu-o<W8pI!pP!|(UvWn`&v5i
zIo$W^VD}vNsq2tD&vjv=^8(j{5`g(!0Uve?xVx_aUdUxL&?@5I*#menw>=xAg!?Up
z2QPBHX(?aI?TLX%8TW@3wEw%r9sB`m%DHoTz`V?Dqf^ioTz9IZxWfI24x&_Yw;e;P
zihGd~30JutR5o4BEm4EiaF3V)sO8>?0IB2tm=7%t-1MCoL?ibm?dzMkuWy57GdGpW
zYOix&h=TbW-2YJtguR9P)eJOSx##I!)yDmS;$=6vP88^B=hi+Ad<XY2HtcqCH+VvK
z7xw{$ac^<wpTn4LbC1(uo^G!AXG}>CSAPMxJKV*zp}))Z)dSwkZKB)Z9(VEk@M3_w
zBn+)Vu6+XVAv?E*BICo{Zz<S6!p(RaChl`DzYnFOT;pF*`he?5E6y?Qr*yH6b6@`#
z7s~|qS^7lOBzGOvm`rhd(x7dc`<Vff54lJFMC%c^^Ji#r;0c#Q=YC#o2XKzOgaNb;
z@S?s4&xvOrqScNw&$tv0yYSwkQWsa=pRUmD#=FA@apyftli<ONK8My}-n*AUJb8X^
zz=Rj?JYAjMyom?sJj$z`fHOY4_bET@%VXUG&X3ppEi4`5G0R}rpXW`r?g6~Z-^0*x
z-eEhfb^>`%Q7uFe&*2!D!MufZ4nLIlTL301j3=RuayZY4R&WtK7VX0#d2dsROB7FV
z8J#D1dqQD1ns<+?7h-t&eCUkjX&S*h$vg86$SK~Yui!;Ik4NjN1m1!QxOSR%PHTsy
zGrU<dKoWV;N$?_x$E8(&GOwAkY$?3L4s@pSw$KToG~P<OyfS&aX>oa$7rzK1S-cIK
z;7m5J>pq5^!&^-k#5o>&HagGqe)<8<T;M%=6(pB;f}(tRyr1bklF$3|A-(?!d2jy;
zzl(U|^pTlj-mjFiE8*=rjDcR{UFZa&l=sCVkTTxBUop^2yrg#lDCe!D>Yd9xWde8=
zJg<X*SMm~vF|;b4{3mo?<+13DOf^qRhs0`lV_dja%X^PLuTsa8BtJf5-mH3_kn*0_
zcxxJ<w1KzLC#mzrS6APJvKzdo>5^;V6&Iq_%G*js+ij4z+4-Wqoa(MRc~kTf?BaP+
z*tMIty9iGA@Y-q3euwwt1Bl$^y|xyuUY_y=kUn139eC8wOQIsxd%Su|2o3PuC;~Oe
z+eo>AA>NrPNRIH9ErQ5>UVkN=9_5+%u<(FqI|H3#JpQX57{fU45tSoN@Q%~D<4K<B
zC1{)CElKb>(zVDQ^aDB_`G(hkKfrgTP|iXAR}}v{#CHe=apE`8b>Peo_Jmy*zA6OD
zT>0BSffhIZ$LSF9;Cs+h^)P=+0qlD6H)NyJi@)t80N(tybZs5skI_wgl)r)=FFt&?
z|Mm#{Id*!n`tf}z$90VV(uYuUoS)}|Rv<s@DGV)$FQ+7LF#jLQ0)+7AQ9db@-!K<$
zhw*pPr&7ZCeQ_`m!SA3`Gm(6EN-IV2Z;U`Pn%_>_;u!unHb}<uFH<J;B)^>k?{R#`
zBzm=+;x|$tES{g+2WJxa6XQUf=3n>{<P5**WdIZT!Ojp#=Eql~mBRO>N}^Q0oL*FE
z{44&jo6cuHgJEaz@6wmBGWipa!Tec%7Z=0M;_rxo>TG_)T8QNEooQovo_|t7TdNCv
zZ9FXH^5tzHd3;+bNIrjjFGvCZIK|-$`EGSEQN%Ae3{uQb+XlNO{9L-RFY*<1MEDYa
zuowo*`CqpJaG4)A6OtADYji7L;m6barjqZz4bD{YBPf_~mG2u(>78o6)8D|?@SCJS
z)bh_#@o_zW??H_48o%}v@EZ7|3DDih|B+r1P5hQth&1!J1c6-V4;nG0H~4<EwQAw_
z?FOKg|Ir5+Xd8bj4I=IQ$8Lah@Hf`OnNGe}Ie1<C3HnDJ_FH@dEdg%xS@+P}&0p&e
zOFew)R}j6!A3+7ith@Zq84&5^*Zl*Letz!?h}`4bKZd0N{&T)`SMc-7;o1;?w*$y9
z|HW?s7~wCb)4=!n*V`aD%3tse;1BqPjsT4D{Z_;Lq@91~0GLz!|4~49nxFL!WFGRb
zQ5@|N{}cKigo7aBI~d$A_>DYt6kIzAazNnn5AX*C8Akv=B<MC{N}UDQ`$1d;T-s5(
z3hvXr=_dHb0g~<l!7@1GA$a>1e%Hf-o*$vpQ(%AfQw-Eg@M9R5-hy>kp!<lRl^(7>
zf>Amh<tzBZ026+K=TiVYCUCfjPJh7(`X>Ydg3SM+bzCr$3<e4!5`YU5XxgDOSnv#e
zb|6Gh6pFbB6U>c(7vX{+DOwSNIzC#Ff*tl`G@}Gpt6}1V;7O`qj~1*;L1&C$2R+_m
z1%=rd(@DWKimk^9UZA&6g5WU4xK9gmXv=;^uw)Mgnkd-W2``caYB~s!EC{6yc#2@6
z0k~AbG(Eo41iRwUN*5fdL@PsZpq$dHX9czmz-I|MFM?zXT<MvRBbed>e@+lhZ^rY2
z+>5Y#LBQaFmn#UNfMK4XV<BA27g#xPv_S9<?O%!n9|WLPESPZ|9+n7@Z^S(!;6}hu
zso(^?!OH|sodf)mz{8Ku{FMvhzJr>}0@WsnRtUaah%sFeEG~liDuMYaIDA#Gm;+w5
zU?t@lY6PE;!KYe5AJyg63HA#?>IMCDSnry^VLx;?2+9M{Y7{JKhBHk9y&QlWg0Dy5
zVT(XbE6Y}a1ch<-S?zEU%nku_8AjhJ$o(6nS0MI+!9KxU+9~x5-p_#DdxB*Y6(0}`
z=s*SqKmP+VB#4iLiD5w;)z^&(mdG)}`+{jl3}RH!x(lrbg6R1W857K;k&O##XpcT2
z7@-5&_DR9>^bVa8NM^w9v><6Y5Dx{_bpJgP{QW9A9fYG)EU{l$zY~&<!uJX>v;#uc
zujo7|eCY*@_mD7^a%)b)aEcf>3r)Ylpo=h+%0*p;Yv~$y6G~PA=Puk%AKv#6R!|cC
zuw8hU2I?t1`vKH=31jF1=Pk_p3y34aPa@HIRG3F+n|*{&+raY`KD!NgKVcVb*^ddm
z&6s?D;r=*i2@t-mLg#VeJF7tgg+4hTLBbUjt_&7hD2W#$jG$*&sIa#jqYo3>J?O0+
zF3j$SXoN7M5WSH?4_fs`370L0(i6hBRs#_&%m@TNM)=nTNX7~ih9GiM`1)c@Nu1Dg
z1;{C3i4kLp7k2J}NP=*$7sh*9xUm5<b4K`_1Kds&Hqd)BNqB%Rfn;I0o$75;gc}(U
zO%;}Y2@`3;qk-@#UHB&@5i*4PO2Eq$hGHQy>#T4;6%S+y-^+w+*}`8p0gxk{w+)>a
zgj<<#G*_5N>$N=LoQH5GU+6`Z2n9mPX^0dG8>o({NH`q>c(E|&94#qJguN@_)J36^
zR&k}mr|!X0nJ|)`y_bafR9H|htfGtUvM}rw;46fCnql{f(0wZal|m_LsS-Z*1k7I*
zy3_qvExd=d-K-j6T{KkJ3LPlfQYSo4$MfoiiPO+>P1w{;OS=YP+e!2`3hxSmXc9hq
z18SOu&Xh8~F6<qG-5bJOE0nefeW`f5RoFl$iQ0tEG{B3S!p@s8(Jox`3tAn*aSE<=
z3b&>J&?P)em&Yw(kO;in!sn?>pj()<8CrUTyKx}GKI@KfIlZv&3U9T;V6V`J%2)b?
zwPL907yd(c<2~VgN;M4#tIk4XP<W6Q%|pWMA+&~tO3E>h2%j&2$bI39*I;*4nEx9*
zd?0kHhRB#Oi{cLB!skQ~nGojXfj24q=rN4iJ|#>&1DR=I`AK;3Q0V>vTzn){ybPrd
zqUjJI_KUvrgovZ)^y?5gAll0S@1W?w8&G;k)J9<dC(*zbh&YRM^l4icQRVY!xr$cA
zpyeidiAojSMWad(50P~k<`0XudcaX{yC|*&CXR^AljuDv8jizweMG-e#fY!y@wq_w
ziR#2qb4+x~9U}gsftS$=5bgS}R751ZhE|~HH!5KW64lZoFIe;e75RpUJm|g;6)mES
zQ<!LB5Zn$IU83b&glNrTj6PCi7gCxfN;F6z_7kEJI!P2Qx=qo*7*X}tAhDuXp1>t=
zQp9-*j>d`BZieJ3(Pz)W{dm!OC3p!UAr+OJ7F}?H$QjYIS!gASZqcxlL|5)ZGFcS)
zG*qXE6tpT#6)pV@tu&F^{yN-97k%IgnGBJFj`wAX){#$VMa>kE%@P#_KqOn#^8|P~
zqJ+<2;+)7varg70zmyQUAWEW$d9G+TJ@pDiFNFb6D3ag9Toj2?RG67!(TntiC=p%Q
z4AmD!uhTQTRP=BUz5mKYYv>hwNpzXMTTm{#Rtw-|Q6z;_DnxNX5WOOLvJq2SDGJe{
zvr6>WQ_yx*^yWOkYek=kK<Y#rDIHWV8e_oGYoc8g&}|U?o&(87(Nph3b(5%C3ul@|
zKa@brby0<kzQ}b$)K8T}Euz0^k=QDlfxlU8qDUKLZi;fLjHF$JmmzL05rd98c8XR}
zK&eaQLl^li(JI<3-xlp&2huGve*j*OXhth=cSL1R!0uhqZAwV?idO3Z?-SjA2!H!U
z^FF80;yuxnJD3Ba5;lN?q77#-iXl;W8$^di&r|++L^O{Q<@ZHL=$nzFqW(yb2cpU~
z@M%oc%0_EkR72s13DFB(_<biu=P7(RC5m^0&S_Cj9wy<TXoVFbk3>i4i;NE9!+%1x
zeZTl&2Sgpk_Jx?X1LA#DQFl=MH@yuHi7)*Mpp)2RE_lx3?<fP~BA)yX23^ImltOV6
zGyj4Y?&3%EDD)6_(yHOGSnq=w^%NWC0PZD@rLrb(aW)kt9}#<90Pm>y>kvr#*u{-f
zX!8|YX23T;@gV&dgk$1t7j*iI3#>30AReSu)^YJN`Uqm6*ti{%LE>*HCl)Mr+6XT~
z#J^LfI#m2+1C)k|w=aREaB(($f+#}#HN9aY#XeLm7bPD47VsGHVih`L#rEIQVCkfI
z1Kj{|Vn#TWo)T|cjm~)SGgELTK|GxV6Q{*230h~w_o<vXQ5=<n&Lr`W39V%DLJFCs
zhz)vZNfoP}hNU#I#vNMH#Y-rzn<0(~Ln~8!)e&~jiVyC<$g;%k_Q!z87U!&mnjG<2
zO52?iKQjSK=fz#I=)52n&V^{MSjI&wPkhrIt$gvjju>cxxY!4zP<;G1=q?iPJPu{W
z;`@8xT8X%6FQ(+8IN&qzO2um?(JB*vz77^HiO;?WW#!`MYUs^%S^PyNniXQ7e(1g;
zUQhE}DgKz^=T+igX-#}pTt$(>YH|E=45mgbcY}wu;#IH0Ql0n_Ev6g9#$v!5#jP<Q
zO=61^aLwYMHiLIveE%j4-4Oqt1ZP^rvAGaw7605p>(4gvmiHlgQ@k<<UbKr({|T86
z@v<)g>=ge%*HxEzZZv$lC61=UHMhk(c_7{54<|u-#2f<vcf=l3Xx$Zmp9N*T;?F6#
z-6#Gq7;g8A<@9p7C*DEFJO;$?(h6!&ya?}d`>Y}Hd0I;hi-%}YJR&Zp@W*}el_F>x
z6_-B&^AE(oQ_0bocxy8zaa?@O4}b~rk~hGc6f-CnFeP@Pl+U!d{t|Ex#g3bx?2%YV
zCC(0#^*r$QOBj?ta+K837UY0rR|k0ZgOV$sL)#(Ak93gUNwS=>j?NO%8$h^7w5wp(
zRr3Ac5OI?{nt=&&m)Pkg;~}}e9NG>`%BT>*Q({p7=OwW=q0?Jpqmt|+l8b8~c~o+a
zwt+s9Xa9j+Ux_DG2l+{ylpx3KlK1G0vA={zIjR7Oa5K~#m#m>cR-nX2kGmkr_J`;U
zmhh^eCPWf^7ranOBUN*SNq(R@nQ+N(w4jQRMBPR!QnKp+08tV@AGA(Lw(kWXTJpsP
zn2(Ws*b6PO5*Kfb<&?x8Nnx>g$wyzHnIL(LUdE>-_vxRuoRNI1g84*A!P_87lILeb
zX|m)wN<*bc;y56wk`qzDrAhvx>Y#MVz8N4HlIDNmTBhU=3O1aTytM^hWJyvsL3Os|
zkKNFcBl(Ihfpe06`#->+mo%S;i3^hD6e7%(xV{gPCn>oO6Zw*^3m^rO&9rzalmx#F
z6GalQ@1e9<5>p9YiR4Q<FMUxGLJzM}$pQvM$|SW^)^JIp)xw!_iFqjuUY0O;n1l++
zuUBB<isZ8)JEpBt@{%i@s**hSCbV6Zy!9EF)siB*?`tF>Ct#^o;>3c|I!PTx`0FK)
z&xYIAB#Y@PX^@oPhGe7U2rUAxOG=dJydn9AYCBpa52%QxRZ@vG)~q&3{5*8tlq3wn
zwRXw6QF{M%NS2kt#ZF1cZm8*!B+zd1mc)S;Tel^0T9S85T3q31k7R8#)ZCG*tc9h!
zlI=|(y^<BK!1YPKr)6lrM0o}#?nxX!0boFK`$PCUC=pJ=!jQzDUd_XjFDT_YA}K+2
zu6@>hNhGa7MkOO!h(3@Mro---Wat`N<B~K_@Fpa!zoBzdl10(~DapH4@Nio4Ih9I2
zlw28w-A9t=kHDaVG@~12zcinggN{-OZOjiyH@pS64@x8H+|D6s0>#apq$1i^*qx=p
z^dfPQE~Qn6t8^ok?z&0){(w?<X|xLvp3+TJBk3jmW*5BhmJTKXe?;olj?Saf6SLur
zkJR}zI(?;EyD=qx(n_k%JtjR$CEfl~=f9ykKsrbl>2c|f8dwOFM$<Th?9#>b8V;7e
zL5r;r>D2caZ@BbdI$#kY{b?0UL`rAUH#4K859VM@C#2pKtB96zL!mTAs@o3}u~NPV
z$Vq8KB$UNTpQX3=DQO0sEr^%C_Y))&q%D-3JuQ{`fp<pQ_83N=D7AmF8QPMh-*cfm
zS-R@K4{u0~ivdiPs>b0{n$$|yT)OlxJDkao21H?KnbM7qfIBN~rL=dJ^aHBh$(F8Z
z2QEi?^BE{RCtX3Yj`LC(1Cke{3#jHUSGv&~Bu}c^29bPeiJh*i0%>w2fQ8a}O2!pQ
zpP0tzi=~`#xL6|PQDo|(^dWs5s#Lmm8l+5Gv<pfvNnhXrP%f>f{nTaYPC8pqAx*9V
z?}~JUwh)!l*;BA^RXR}y3)Rw;$3SYNEpqT`r8CyjR<TZ+{1Rm9rF+#F?=@)@Wmy`e
z3uvH?(p?m)X_8jCV}hHdXEp$ET^dP&&l^%7!nH_Mlu~b%{zwI>ZPIKd;2qLE%K`6{
zo`{2Fm$dv9bl#GB902^bG|dk>yQQU<>7Rr2NdKUx$Q|j=bY0$+K6VVg^-BN!6vOV5
zIxmOPe(9G&wC+ip=p^uf^l7Se9+W=b3N=I0*Ql~{SX%Z3w2VlfWuf!Fbj{nqjY@;#
z0C*tvr;x{(bln8VxYYVCcoWht1UKxnCZ%i>v`tC1E+Es=xfQVVQ0n6c_a9099ih}g
z_UQ!3e%W8N19Fr_QDFOkY}FJ12W1i}xj!V!dj(3JWHZvhbC%^%FvmqU)dmq)S>V5D
zxye3W0!eq-{?B2-Lsmw0srJLNTV;^(l*J|j?<LzxiDz$F(?TGQ$mEN_J1R3KV1zz0
z^9c}NS#K_gpRBt9_+v7sER5G*mKcqp1<3xUgDl5o1#|@k$`;X+B}m4iOh~Xyass>%
z*#I5Z3YG1nYQiwPtT-RQa9J9~&Ld>86xWNC#nwVJO7`X;fG1>I`(ZFzww})4#K?*j
zAhEJL$D!t=EO{LOak5kNQavSOv*CTbY|StxFG1#V96C?Sz8}UQ&dBzpp_M4JM}Q>B
zd=sHMS!Nex!%~Xu$y30m%ATaVF->-w5{v1w&mKWdhD=Shr<t;6@<GnZ{JO!*lI7C=
zB3pKk%9(OxuT$RRoa|`}%%7L-TnEVuvS42*%at`*0mzfh-w(-rS^O?|Um%mywOTAY
zZTEyXC9)-Q^j?%L-U~#jjBfy<O!mVu@Gi-YR)SY9b8`UivP|3zUWM$X5b&<ZcGDuS
zQuf*37-5y{W!lDFm7P6^&T83xsw%9J4fz09EBl19vURe;0=QN$6Ai=sHQE0XX#LqB
zQ})B}Mp+_#R;@|aHwI?2Y}ZG?UzagxyM9A<?o04mWNEZ~Zj~L&1+GoTR=}B?GRX^2
z+AiCM{nV@u+38Oq*(oy)z{4(?I1KZ9OEyin!)@7yci=_0Eao9ZdSqH3I$n84Hb7B|
zyRyv`L+h3K{&(ZaYFr@GFT2zYFYd{F3PA>B&rz-Jpe%{5q#>D+UNXb7J@ld<k)3!9
z2Jg!p)}u8l>!nhq2QoL>oQ=ui={(rD%=!@iPRL^Vp=?t2hh;YIzbToX_J7l|GI|O;
zl=;5`rH^E@c>p@dXHyPnzuccbdg&++?}JYV<f~KAc~Jfe#W)YipQMedlRS{N#Ln`6
z>66zka%Xz&yUOPq(dj0ytU{-|d^fF6Jml7SfFG9E=fFd|r+jxSWW3~}wdnPhXK#ev
zBl26jz&t9CTMXhO|7ika@|CwO1n-zUmu?P!c`=pg1js$<<~lBqS_9pI^8M#Qg5=M=
zh0b9487jXDksIjrZK(X2rRWTkFQB5CaJhFhS`l{ni%UQw<)2fmF-kr~m0Bm{-+c@d
z(Q-SjzGLKD=y*x2TukfNlky8v%wC*4UW{R%k~5cp7cW=Pz9d0DqW~hO<=R5D&d3iB
zLL^cC@{7=tB+sU7Ub6frditcu2X0|xsq$9~nXsECkD-8Ty4-&wS{d?hXmgh-f8XDG
z=FAuEyQwBDN4~`YymRtsQhHt<Pdl#*@^ci-&6Te>j8>lfAyseY%b$4{J{8DY>OczR
zn;(bjB6;WI@Tpi{MG>A7`I{7vzbMzd20*EN=^lt&lGpaZLb;r=ADx%wFH`EOLSAIA
z1LBIjM-N1${KIS*tdjrK4)?Fhqt2sME!Vw<R*n1{DO$C1584>i$<yNCXuUk2F1Bm(
zcbPEXAb)!bS{mg{s=jQJU#ER?vpnw)0ItgoD*?YDKdlC?MgH_sjJj36H-=J#ZSv{0
z@a?8NWhS(>%V#zK*dhPxaga{=tPjBJlCPv)$}RbB%F5lAKRyk&yX8%F(AFc5qH3r+
za$hQEx-0*ea!$SSs0xric?gBR`{lih;o3bp>l0WQkbmF>X9ndyAJHv3B!88nSHtq(
zOX1XrJnAzb?#uh=lL@18aTM%6knewpX&aM=zYX5FTtZ3P33(wc*C*xk|3v4MJo#IA
zF)iP?3z84zzve>Zkvy5AnGTAy#c*`LqI5gRL50JAb<&ChffS-~QvA6CcAXW!(QW9W
zD0&+$SH%I^H@YcaKMjZ76=#z`JQO#m9^tU!1rb`Fiq#Y*^HTgw8*6VxGOhZLD4hKv
za#Zo=4osep;%{2V`6>dRf}?(lWO{!cQ#^SLBL0f!&VXkRP_XC(=5fXE6_5#3I4*+u
zAVm|U5rY-GY26#5xcx17p^8dc^n@uM41yP~@TYWIgd&R8rjd$8e?nW7;sV{9Cln<V
zevMX)cf!#a#Q;?*#wxtu2mGXBU=v)6Q;di}PT3W!-T;kPobrIBGm7VzLQSIL!J9xN
zDJqwuGg;wIN>db#RI{F{D4&E#n!-&9x6>5`RA`c+c>N4WrXnW@CeA7@N5Q8og@{fI
zXDcrK3|x-lu}?wHDW0Q=J+E+~Lahr5d(aema}~Y^F~U4W`2zIjE7s9%SfIFUgVI99
zjMES)QuL-^+KLqiVlnF_3L)+PE-Lb=j-pf%;fPk5;^VJ?yQHwx0#L4a?KJ={D;60b
zQla>fE|x2bm9%TFRP3WemQ{)z`yXIlRkYFyyIS#i6x^>-d=ZPzTE%^O>eVSsA3#mL
z;?RfST~qi_{G~x*q}NfS;$Sgmrb)4m(qhdDth;fmDem8Z$PLA03{12rO1+@0Rk7Ix
zfHuW#%In@#JeviPcEtsY0KFZGPzt|xD(0zSqDyhz56o^wUm8Sv6bDS0uRDq$n&7*N
zr$}3`V(HHyeTrfKFP@nBrhRP{aKnlh=;+6YqCE?|`-+o2Fh8o8P4%n~6g#NgY)s+y
z7j%v*u002l3B_A<dUjGVN-OIr#V{2UPb=op5AslP*9T@FDPCLyxPvnMGDP+(!=J<)
zIx2slX+EH|&c(zWR9fwn1v#V~r>&2ZvbP#7XXV8j=yp*qr4@;*@`uNPcT?`6vP*a6
zPe;-6PzG@@>cdJ?HCmp^5<lR)l<gEe4p5Hy!0vHn!c34r<<nas8Kmr{9b&L@-w$vt
zMA<`ic%jOX_wB%kDck7D7Ovd739Sg_0!q_HDziOdK1w+yL+gYxs~w1Fr6VobVwCTE
z4_>TtZW2auQt9^qyf|gx7&=cWf4K%{;+3ZTAPLIXwgYfl*-s(aGs;WP!^1?S>pGAm
z<+4BN6nV1J@h3D>l>4b*Dpl!8%Y`)MIx1yIS2j?6T88qS<q*kK4*vskR+&%1-z?=D
zA7L=r%D)c5M2>R3H%y#UD(HqguY7Dh%wJG$qCi}(vdj&gdCEEe!vOP@4haAhDKpp5
zr{#*3-u~z<QHIib`J(dJb|@`X?%fG|nesI%wz#D9RX|O-QnMbs%SsuoCa)-8W<jJ<
zDeeNUN_nUl=C3N>Ed!}m-le0DHOi|G(5h83MlqH;C5KAY>y>E~Ou42!$G}+Z4a%d-
zA=9Yzp!I!|ayw<}o0V=E81{9g>`(Aol_q-jwkiKofwU{P<^$iMyz@Pr=~Rx7K%`5V
zHvn==DYn4h+sgIlpru>+{(9K$QT}0tvO7v1Es5_chvMK`uQHYf*k@Pn4unj<^3w@0
z?<vz8p>#mmPxt+x^8Ovj3@Lx5D|lG>_!6{6l=DNO?Y?qTA;_q5MH0vZ<$@V7IHoi&
zhil`?ITWs)P!4thFsV!_gw83YKLt0Ym8SQh`l0d?7qj+AX^*FX+<w*Lv{ZCd>B1p;
zK(&vedrqo?2=JU$8%i-W7u5%}dUjRGC`99?5>W))T{V|J0^zAzTLyras`*)nc&onI
z01+RRf(itDRpq4+@l(AcMeCUAPx=Y{RsYmLGC=jMeI<I2tNP!Di9pqB|H5F9Y7-TS
z1gpO4glLHB`DcI+RsB!}kuX&j<s!pXNk`F&P(4reX_2ao`;d%M$=(C}gz7_DK}D-{
zmodT^)$9=PVpVJD1$|QGB89Rz)rw!hJEfW*X$Os0UHLCBtaA7n+D@w?seI;)Y7ZR(
zN>m+u70x87{62)5WR+Zl&J<NkKTM>m@;9TErZUr8DP2`d-)YKF^-*p-Q&oEjj-FM8
zQMf2ewOWS>%2w^6$a{{;o5Ho{R2!b8e?FM2dV<1<d8%(|shF=~y$bUMD#JRELe;sC
zp}R=6JQ=NGRZ1q5mZ+|V!_kYXtyI!ns>;cONSSK(DOkFs`iGVo<*K<lkjtuxW{?Wi
z9xmWlR2#Bjw^H>R1*@x6HE&Uw(N$FiWgMzi#T%i!M)he9l-8=A*@OA2Q`JNOSg)EJ
zj#i^;{aa`?slHtek!F=YEpM)?UZj2M4V9f9cP*+IsuXKgxmCkNo9gWuki4ndF@^zl
zs`xYDVV7#_K1{+bRls40*zc(V-h}P}m5~A<gDUJragnRurflnd)!+26A5|TpPa8i_
zz109qW2$@f8XQ+;&qHfUwSlVQr&SqqKpv`Qe+a;S^~QfNY)AF0FG0%zb=2Q5e^CAU
zeUL-yjvt`RN&SdC^tP)nz5z8y)QP#ckB+J<={T5=x{Qt+`KmXbhb2GtB%N(JrvA$h
zCj8aAD4r0Y-a|8cTwVGkBm>p?6hRMCe@T1UVD$sq;D)FrbPzdIEuyImSARj*MTB}@
z8GeIEwKqj9qSW>-N<W@ZtGm#QR)0^=o0DqgQ2^uAZWq8irG9}T%JFK(EjXH>K1TC&
zT5YF##4~CwRpunBg_j_br2aeufMoU8V!%_>rQzVEs)L?KD^2aV0wU>Z&Mt^#sDIrD
zUZ(m}dmEfOtBzR>yE*Ec0*GEve_DrDuKMe*K=RZdPGb`D)y&;!6{w$}kZz$`@jE7=
zNc{v=_!q1BE1|SRoiqaYMKxC2xGdG59EGE0>OLxuxTIb{OWShwUw>dKFRP=!0-!=2
z>12n@6}5o2K9y?rTHveHGt6jRRS(pGSFN7d3VfY<NfgKp^&?tfx2W@HVf3x)ajG6@
zQ#bF$&~B<%P~~~Mx`RS~ood7P;B~1Vr=y3r)Qic(+v+(KzvxyQ-UsPX^Zxsa${n?W
zmK%4~+(SV0sog2?->+Wc28ZvdZ+oIOpk714kwG;t1?Gp;izvB0tkzaQ>4<u{9j@J1
zU-Lq1RIQ`s_5=0nKVxRb)j@Q}O{h1~OJY*J@GtPD)L&3V-n9CCe5=Dg>!I5C4|G3L
zXYB=X(7Z{DwEdbb6pwJ!yk!FZfF^AhfCn{6G+l=@qqpIOlP3HQlsap6{|4_}G+)zI
z=Bl|G07*AZDdi+QHP2IJs<&of6snJCcu!)0M>TWl6pfF@pLTP0U(MYb81&Py&p|Xm
z^Un<o=C~$-!YF~7JSKDpY4$GzFIe+xHh>|TKLsG6ntv&p8K&8J4VPuOM*J4EL~0IG
zEH+A0eHS7pH0od|i`J;t0v@B$y#@2J8rC%2KB@7em35q5v-t$noYKhtgqnCw-s?al
zXuf_7YEEmmT0jyt_vlHHq*+H3oUEC&K~0LL^bnM$Y9eSql&(4N0D~EtU#`N7ObvtT
z_RnfAW<n%O;~5WJwq~pYtsG4d**mXULaCz*8vALgsLj=E6rndyQ~n8j%hz-<;9G&_
zXIhyTYTgvWM5*TXTbPS7&BhY&E@@inPA}Kop_28>nyeY%UC~U?Yrj%+qZPa=&8`OU
zYBb*n0I$_#Q+-gK<`^9;s@EuKk9AFR&|U;!qviy~Hk&lx(Rt!#O(z3tS~RlPz-!g~
zVa8zEG^`mw+|*1_c&=TOnGZmR=Ey<-IyH&EL-Lm9Z~!E4Ywl64dADX?EqFbe%M?Yq
zquEBQ_Pd(D>4ROp8Vy|#eVV{u=z{9kET-Jkpr)Pjt3#Tzm!W1@!&O1eh$hAc-S;(b
zc7ZplnXwS~G0hO=v&J>2>6q<=X2qKjnbe#YqjO5Lcms4l()blZ(m~5!46<K4N}(M`
z?L`5+KcH=(Nc2JNtH-F!$Vsc62N`E={c#W%?e=>Rb=7`M(HJ*vRy0HpYcKc0QBSQu
zl~a0YyCv|@Tl@Msh#b*sJ_9+bU2+?6A8i8V$b7ZtT8Q{-_r{|$KwC$VlH=M7^xFq&
zmrwvANGqO4_g{$iUvD5nwGZ<^!n7*`K_av_pT~G3wZC7*%tUEp-7xtlw9CJO`Dkrk
z9n{2V-+LXrliEx=H58}a|2Pbu(nhXAXT0`{qYz2Zeu^dTtkc>Adb%fS70cj7lJ-MV
zmaN@Qi%NTnwuS1GQnhB9uMF)UTQKXHTDu8q&T3D+jS0@u7L!P}w(&jSbF{n2?m2Bn
z7(6_$ZKQO~1#KnO2jyy?qo`n>HuC|T$=AL@vF8Hq3|e&*YWt~9yhwX01%`^XfvdqQ
zv1=<ngNcjUmL{kv(^eJ1?@L;D`bEpN?|%eOFKbWIKDk2cb{Ha8w7KEnRchVbfUnZ-
zr;4wu+V7{JrCK{b0p@G8ODXJHtIhrafI6+1mgM!?FDWf`P1{EwW^T}W)3&Bj>;K)0
zGiTcuz6T}E+HxL@U)SbQHOLL^Yg8=Tsx6_%MVq#VGMP8E@vnf_u5F{FNrzTN`L<5&
zkJT7^mzKL0yjxl=6^h)}wtNbBw>D`Ms(ZANR4H{wyN=QgceU<e0Q74A=>fb?`>dTV
z_<rrp7eMZ5?^EDlKs)*w)C_4|IsqKk4$&)SL|d){?}4_9c3NZFKZ-%dwN3FL6WXox
zikZ}A(!+U5tNj*kPitpy0`H;ra|%E|(*8qF5(i!32JrUlR#{=*QCA*Di_inQE#$>P
zT|7me59xYlqti*}P6ZIox(x|1@1lFt4Ln!fg7t9UO_w{0NpRP_M2lY!U9=Ug!@5g3
zz<KJpl<)S^?V^2?w{GVL7|Rh|uO4=f>LMu;>!X{ZC8@9OR2=16{dB=yXdcrQ)<K)U
zu8Y=D0lM}x&~{vBh(;?=_lTC@LAoJY!368ZHShvuPmkbJsO~4)8HVY0-vuCCCmjNb
z()~;C=M%a;6n2c(ZJrOw7~Lfb2*v7VzY8rVbuD-<*=NP+F24&;Pw5su1@rN`TP<jv
z*0s|E?ToJGBuJueC2cEGb&vVNZkn!s3!F*Uxzo-)L$`4VBh1w8dm9GN>Xu#xFH1K}
zTmEca`M*$>qsybSH|KQC6jwU0`;!G_7j(zh!BKmzj`b&)dAjc7VCL(h>A_N<+fG}S
zLfyHY5G~T#KL9D#^%TQIiLRE`Q5SVOIxAAD+g=V2%X9(mAeVG`cOY4=%cU#uvaU1*
zA{Dx(D*#;4%}a!9mAZ!I;8p1gjhMBocHQs;AgXnPR9aG_i=o-8)qPhDzw2~jibmAy
z&g=)drrS+%fCinMG6RjemzmJkq+1z;R<lmM4Y=z%e<Ox{L$`$1$1OVCw789QMaSSp
zo9^hR;N8^uQ$Dj@w}Q?|cj)ZDPh+5+x}9_yt4lZdIAm_=jy?_GZQZfY(b=u*Ig3`0
zPUr<k@93H+pmbN4ycCkXx?(-l^yzldv9W&LN_s`y)A=ug!2#XMKC}jP=Psc&q+8(t
zL&LhI^!6IjDLdfreO-zDdC*Z@ff(Tf-6q;nPU!X(p*5*HPwRpyT?p;srgg9S!^A_~
z8WhOPdZat}GL$;#!(7n0U!Q*yN*(oKFT=wF`c?G0J*b}%fz~0t|2@E+^bwokwzK}y
zen`6LZ;hkVRo|aUYZf<s1LYvy^{-b0;h|qHhVH}qy>zvB>OZ85%}ZbQ1w_2{zgNP;
zBl;i;jvv+EEr2sV`tv`-pszmu1V-qmH&Dv-m|j4y7Jq%911tpSmr+gCas7O%><ZKu
zFN8>l{(S`nVZ!zGO!P+Rb+odL)LTwNca(lkH<X^xFQ($CX#F$=T4MBt^ze(-KThkB
zllt#_U?NU`XA-WR(!aVLTH^HwDBzx;pGk{_)B3b{@XqL&kHgVK{ai}bCh0$=?~Ekt
zgC}O-{!7ub8IVcU&&-F5Y5F~s)lJuHC{CK8|M6*bX6iqotNX0}Z6-Ri^zMzYo2_5+
zE&R>V|H=X2oc`c7_;g<XXB13a&{w?*T&{ks6rFkc&2)kzUq5pmIt%posdT(h?@<h%
zy-5EpAHBtT76qb9^sg>}-xu}2ya|U(^}&?pFVkOn7x+v1svdYzu1}*4;${6Z8F&?X
zcRFEtML&>^d9KtKia@ILzDBrqRlki2L#y?(eg&XLze5WxwfYqcp`}jWOE*WoUH>;N
z_OI#x7690wAN(JfjrzJk;G6VKtKn(0{+I8;Ytz5*5SH5Y2^3%I(7${TyiWZebRTu;
z%V;xpOTS<yOx)JD)0(hb-zme$di0-8fOkh<AcW+A-YXtjhV&kE;ScNWK@=4q(I-**
z?16rx3&u32Po@y?xPBQOWS`K_CG(T|7aSlmrGM!jTGRS;AMhUP<30y@q|c#ewu9kM
znv(s7JOx^ghEMN-956860pOq^{3eEU$PkeVFPsdTDiCMGIXe}jxEKa#2k&awOnVJC
z1M33}&E3#T=es=&lT^EN*r1`WNqHJRcmQo)1_M=?cpI3XqVtI1393puYAF5&a32Hv
zI*6|!v;v)ehC@4`<(T24Ss1Us!Ak;ofMM?^uyEY)zYa>|1R8GJ;YE<4Y#p2mHgqJw
zV2FV`1w^R9tqzvL49Y<O!wr>2D2*^g`~eban70j`QHBqDVeo`Ou0bo>;B*Qz8e>SH
z0-{*MzQ@sd(x4SUb)4bIM;PZRL+95Z@rK{#(fyZTcy9;rrwt32!kIIMZo0P<4QtoH
zrzFD_U*MAs`&Obe#h|C<U#fwd3-f7)($nCj8@^ltUWQ>qI(V6e1p~mHH4K{IMV6s1
z8?9`^GxXxiF?dpx_kzKR50Y!(|4y|Ic?K>QYVr-cs6e~G@T4<FUualJRkB5fcTzC=
zV#Dn%5GgTKIA9bP4PTvtNU6c^6?B#vTt*>s$?)%2@S@x>tijMO8`e=7eucp=6XvfN
z-hCPVRvLa^40x4c1GTOi?mq>4_G*JaZC7gyYl6_MHGIAVh&sav?e*&oTj+c8*9>!N
zK^hG2(~hUnkm?LxlcCBVYMKq-7Q*~>1OFyOZWvmA0I$WMF<>rQ4a_`<v>C=!5V>h+
zXaKL>FiN?P4nuS%>~-1=tLfEo+pzsp_||P;yb75f!yj|OykqE{iAlI?NT5>RUPFI4
z9PKmAr94Hyp~?)Adj_up%*BAAu>!3@!^S_*8ZxZ2Kyuh{pGsjy3?DlHe&6tjq8OtF
zYbPe?fg$+>w2T?-GwF>tZupEmoiOxKAbQd;o60e!41Xj->9k?A1ztQfxY8cyk%37o
zVh7_-R0y=+_$U~ij>a9YK;(e2gT5?s(0KJ}C_7|ahDXdSC*!Vv;DxjC11jrrF%~C+
zxEkMG4?}K7hTRtkcjHP5-g+3T_Cd{IW70*~^)!wzN6X6?P5+M7+vx5HOGk`_e*=Hi
zIPot4KE~)l==L?<9l{UeXMB;;GRKT=!;lOxPIv=;+<5C<hy)sYXh9QX?5Evku(3Q7
zB*a+IOHPFvfA|{AFk^Hy5aGu8^g)LR<FhoSk;X*I5JVZf<Is7+I6Dt>8Eu?T8K)TI
zyHo%XYup+GEhmk?OCS<wObddR1mo&euzT8=N?F4*#!rIaZ=&(gT!<tYGpI;5*_fV1
zXDw5Vy+5LvYMkK*nKa{TgwHhgc>{RX_;vs$D9bpz9Ai3X+)7)@^TxO7(-9YpU(E(D
z*XTnRa-Q*J3S#CPchVdd7(b!FY@snT8@wXpqM5)I8}HGPo)Y5%Du=je9Co8xzfz-|
zp6g}CMRa!KlChTZspZDaJs_8j+8WrcFuKwL|BCToGFp|!%nu=1W&HAgP<qw)GQC@?
zjgBS&YK$%vw5>I6zK2$warW1ku6kn@<;1QTw=p2uV0?B5lr<V-H=$*3GA4#YrrEgY
zU6AX>fuG>p4dcOhkQQSJZBtr}0kpMiGp2tC#7*Ple2{kIPDd#1FzP8k*=cO0LkwNU
z89M>EWqj#7z;7Fer_kALyg-F?J;r4;&O65U-$dtKWAqhh>9rdNzelsrm`dM_=r=k&
zLhGLKUE0bH7!UG528|i?gc&l<qx0dz#?!Asa>S^lV-oj`_vr;PYJC0+h&(XP`wDi)
zjHw#n#*IrTL^xsG_$5X*X?)25-jwkqU8K{-3`#RTG}>b+2K&gkohm0BOoMIEcEGgY
zB7g@?LsXD($aImS5l*HLG>~*QC9u$PF)g6VPFItLayD)zLk6bX-L#LMY#ye=bgt^K
zY0EqC$<wrI04*=mW-3<oHqGyamLsMTM@SwudDtoA>|;`dK&h|k+gG5*&-C3eWR97Z
z(&;^aQ!YJ=0!+&&2YK8S?T%KUX%{^TgG^0-qchl4@;GoIrdC?Hg__RMy%}aI5kn;0
zR7*+L2vhfZh(wxpQXNs0iLnLdPnedUqWxdA>FzBkjWN|H0v~I-LQ9#GrnE62;!HFD
z0WZOH%M*yxrmn9svu8|+6zWSfJx!~^BvT+AzD+i1U%&`cOa@=HQceDOXr-C_=D=Wv
z>Beq!W|}7P%9(Z6v~Lw~S*Fbl`ixt)X}l38&Y9GcK%6%%NC)DAX=5SG=bCbC;N_Y2
zP%=B;lt!z{B2)HSh!mTCNQ2T6lm98WebJQTf>x=?g$ljOO#G!FmrM<d;C8v`TL%2S
zY~pUf$SO=tzJOmbJw%xd{wa*fOi!pPQx)9@S504z!9=yGw*&YZ(;&rJYfXMs3Q%Vn
zdk2#BrUNg*wQHsqDQVeY%Aq>kMpN22JZv(t--k%Esd*JlTsLh^g|Zu_ObK``rl;OQ
zXRGO{G3abF&7o5o_M4_Mss-&Z!C%}*rqAfRakou>1wnVWX+0Gw^_Z^b0)NLOp?&LJ
z(+W?h={1E~fbTOsw-Bv<Qw`Oi-7}qf1TtVspxx`BX`vU~9y0x}5z6kHg!IrIHMtf;
z*#pyAx^KtqrmjW6kDGSUButq8*@0hX(zMWsxtKD&`3iv3rs|adJ~aKc1CBm2mD0WG
zVD6$-mZN#qv+(eM`SBtE4w`dDAacko*a3i(dFx*=;cR~Yzf)!A`BXV^#B8FXx1;7h
zDmM2q+s~eaL0@y+S(x`TuX_$k1I*hfOMBeR>;yj0EZ7O%LFW4d;02q_T1bYNqbO+^
zYR)?YrD0}+5uM@YWXd{5nEhxi5NY1qiB^<3q7Yh6m~RF`XSA8ojm{YJZpzXmnQz+%
zfKN8RGLE@SH9y&k!K9gA_!ZjH%`0dxonc<}5-eq!7e5Aa)_imsbZ40x=Rj$;`N`WD
zMUMGr3X+{OFa8}O=goJhhUS9#2^K_h%|9d5H!IJaK*eYI<|7oCEil{uOJ$hnUZI6&
zk-6a<yeT%1_(FGy*{~gIE}BKP@Tt_CLW%1#bNfl~E}73C0>0e5E*!ke=7v46TVZaQ
z2i;f9QIzYgG#h9`UuAA<h0d$yhvaCr`QQ{pYRrxF(5*GUQ2<_@`Oupb1g$r>-h#|E
z^Y%GlHkjjRv(sokIEhx1c|ku!o6SdQ+uUN_qJ{2O^WsW$wwYbOg~(0wGgRl<Zhq1o
zu63Bhp9ASM_hq89%Y1eZyuW2m-HXoK<}fPl?>38Rf8AsL1Sun&wKO-f!MtnE?Lcp@
zd6xrp_nG76FxYRdKLLaH%t=GAG+=(U9IZj~g83Nekomb6adi%x1O7$li1{IvU)?ub
zV}KhqyHa%dfjRJJ@W#x8i{Zt%`QXz4Oqet2OKp>8-zNaDPnq9$hWTl87JaMfp}C#*
z5Rc5?&@$G+l0g-C`z_!74iQI-_wT?Tuw17E)Im!(B|i>XPEw(XlVyZniq4k#RDj`T
zdAl5gaJN`*!V3>e=sMsITP}nF=V=jBy|b5vvlAlTcFXDz7(8MrpvdY`%b^)S_*j1V
z5(r;Q{d?&2v!qdB+c8V$E)31z^7I4n0xYZ6!>8jGt_6b$w46&pXOKlk^<u%6*_2uf
zvBXmKN~q-nisXh_c2E*9+_LGv^tC1NPk0e&u{SP-!%-I2DF9Dc3MhaXZ7Hb5m|`ra
zlVCU2vd4z$K56-imcMb9T8a>zvixrYMB**X_t2SONmvgrPFpe}AbG|TxDbveTH->X
zI>|Cn0Q1R~dvq8l#qvE>5T#oFrUgQpMQ2X|O}DJ0kXVN0J9<K8T0VUpy3bnNThN(h
z387s>wk7Kh@HrMCRTP}F{6R~$^On~aL*#<xdD`scS{`Phm1o&#hBNt=BFdB%STgCH
zLZM|ntu%`)yXoCnY^j?7yu`BiGs>S`w3N=lm`W}62DHj7(IF7MWZ4=8ZRM8zbWH!U
zWd<F@s<14k#dMV=k|J?6mZ$!NiCW82s_3b+d`<bFddr6l7`$dF3Wd%F%k&5gHd+>M
zf|e#rP#0Rwmg%jqaNRQhBdT@3VL8{0No=uf>xWFMWgR_C+AO!I1mUJ-;clpDw|wsm
z*E%eRC~(?oIZjc6F3T5RLE9}$9L?-)i{~PE(QWCYL{5)o-q!%!u>?~1^sXgr8j`)1
z9Y^6|pCy>iO7>fL=@kFGXGy1jo;6@u{V6OBT0VXjGDDUZC(#<VJQIi3h^3+m`1_Xk
z^3fW#w1lDc!1B&@=pM72rHJ&n<+Yc<o3K1L31yR(C(lD<%2N3h20Cqdi54agEgkg$
zJhF^Zmc_y9)(c7de(NSG-gdOEr}*|EE1LqRPS(Z+AkNlFTGqK(f4KsltJOaU#LcRp
z4cuYtf(Ia;))b07dRZIpfOpjDMVGvf^*cJG>}#F*6=u}WDvyS;W7ef(;Q3n{&VUza
zT|>*?AiMRAX*7ea9`yJKv4+~v3bl5sK*Fqt=0kV5bs6n1BCMHesEM>bNe}cW>ruKl
zPgraJtID-jd;pOc>vAe>j<w!AkJd?RqXk;xtZW%1Pgy$^7<RmMf}WiTR>J~}{<PJ;
z_BN*GjP-N6#}ch8DAkZ;jl6+Yvh{!Sp)JLFor=Lyt-E6ZOtWUt?kL?_`Z}(%4C`F{
zhO;uQ<@6RkYvs`-WLfW+Ad+oeLo2r&>j#%0dCvMYE!WRmZS=ytU@d+Dow?Qn_I4oh
ztiRj_$+uqc11Yc$i$Dsk!;4_I$l7@nx{IwYN6}egt-1);E?TE=p|jMwnjWlWRt3FJ
zE?FgFkaBC$e<1+tYKkmXSihojrYlw-x*aO5kreu?vaW9hxoYLN(EV3!Js%Ecjn#1*
zOw?M>R03FMotK88)mz;H(Rt1K8s#<`toCc*HCkU@g}H391~dcSY&}r{XRccrbl=~w
zcJGDTZPt}k%68KlM>&Fat7tWF9abI%raP?#M{vn?S@%}a{dddiG#is~+d7wiif-#D
z1*m(hm9*o#V;%k*op-Inw4&*?&Ru}<_E{M}LtDRfW+b%Tv;IZ#?Ex$A1voQkT_uCT
zA?vZTAj8(l{|cw9H|PUd_pPD7L1fgLLHW7|)_qIpUzv<qzdePajaxn4K_;xvQs8sa
z`fNXZnzGJsg6Oo>i!RoORyQZ`9$5vGFz8^zE&(qm+u&^Y>u9@@0+9o@X4;S(w3X3Z
z9I_2}!LE~S%NJ1QY}4O>G8fzPCt=9dHoXi0yPM5B1x$Ba$s#a4Y&$7xcGxyb0Wwe9
zUy(53W#dpz+}kFgqoPM_mQb{g+WuYuOFp(3ibeU_)>1^w&$fFKoyTlPav|w&3!viM
z09)U;aOSw}&Ota6XiK8P`5>F)GyuVNo0wjzAvWC`Fc@lUXhSQ^HiHFc!fkJ*qcg%5
z7XfXNw%`D$iL$*>2$2|@oT3}CwmDOn(v!AK+5^Pfww(Yk!8Y^=@YA-jufR*Pwb7eB
z+14Bhw^MAVC^DRC+eRDBG@E^d0t)H2Z5QFqS)1ezrY6hwGDZ2aZJ|{Dm1FaxJ-|7e
zf$}xyZKr4fc)|8Pm8Rs{UZYZgJX<<FU-NAW87vjpHc+8+p{<O{af@t`|AG|TR&0bw
ziOsDUyo)v+MSV+crFJU0D6@Tf3%W1aGIM}0w|P*Z+GX1SWzZ^Y=~Uc%#dhF3cu{F{
z6=C+OY?^+I{;DmGf|J#@TeILrjcwsph}7En^fAUdTVEi4ihA23itt>sMbN4B2Ad-t
zFlw}Y_z3__w!|tsn9Vki7I<^r=5ztT8@9Dyf!Sh9-wM)do22Wi&Gy&{@H%YiVQ|0G
z#;12<m+j9tq4bvRt`_9~99?%@RY%iS6Ow4UF};~s5;ZX<nr2Ki#Uz@<M8oa9_kKzB
z%LSBPq$^TI5G#V9Qbj<D(os>WG(l+sB7(H<nfI^x&F;)Iv*(<<XLn}y+#ct-d*Svi
z=QXrDy6xP>LSwJ97x~oZtm}cJ{mz~=YYjN>+YK`4>@z`srFX|UWh*p>oX0Q0w_#^i
z2<(nH+m*0%*ZJ#jAv)?DOX-h$&i%pY8*|=4Pv?DSXBU8uJ7)`^KH<D10+J7$XAYrn
z(z#55D>~);7Ht})olk88^o(-=Rcg60zUzRbJ0tNLtv`1$SX5u<$++H*fqF64e*sW$
z##B5sd>FNBfbGjzO}TtOM&}63`!g)GunAy%N7Y<`j0V~P?P0{<L1Pf3kltUxjO9<j
zZV2N?6E18h<NlxUDU4CG1ct&He^o;=f|25eM#o;pO)Ka=hK;81NCy9Rko}A|yI?Se
z@fw{vie-H41JF3eSx;DsXDp&U+5yJz6mdyluoqyU2N}=&4uwQU6xDYpG1`to<Pc-e
z5)3q%5m*Oj4l~wf0_6xJ{XH}uWjMbB^<xgkNC@b0hCeMsPcV9EJ(t3ma~z;288cK7
zm&#bY0Uo9?m=xPN#rSjvlIaXBR_{(3j9ab{In8+I5cJM49;GSiEaNrW24*tEv1rU<
zWN4tC%@}86^f`=CN`&Py9)B2S^BCInFvy%^Y_EsI`HX1V8JuT)u7OMe<DMTH3mGSA
z-Y8;}$pLeL@dSNYqL^Vg3CR-1&hKEUl(8!hTp8n5F~BY|wzmNL5~E-%`YIW<6j82W
zRPB9s9S*K6kwNkbL--9auQJ-r@VB0^ib_JSF#?}Q<8{V*dKoq_KK>4U&5R#u(bB?j
zp(3MJMoJYtyTK@;O?MmP!~@uCXVg<-wSzIW6(XICd2FC`F%FO8PTXV+djt9w<6nCJ
z+-Cgkpmkg?W5+Mh7-0PBh0a07!@=<I4kMN3k`ac3!tr+*+*d(H8G)N1d7n{m5}@M@
z@l$}AVEjWtq$$SsQuIwTYAI?o!}v!HFgIqaGf>=_JWn{Yi}__MBt4n)YjN$onAiWK
zc#k*J(+8{{b0KYh{h3Z}5Dj2<KMsRIOxJM01T#CHg~1T!@F@DinZqwaGJ;u55uUxw
zMw(vtGov-=i(;<r1z0q*fbvms%)^;zjA#1MvvPo0OW#6CWbXPEToUuOY07sTVm?6u
z(<97(F2k9l%o#q&G3G<>U=%6LlXOJpB-5Y1Pm#*}!WUdR(`JEB8O)V5b)ROwwFC;8
z%!TvOm&F`h1Cq^rf)<r|%*1@?ony8i16V#YAR5jTGBYy36*0?E1m<wMz~s^zuawE5
zczPMr5d&u~GWY)P)B|(JGQeDAPSD$|o~fj1{Tef!_AJ+#xBr7)1GAjM#LZ0Z@37m#
zoTd0yEAyNW6mBrTrp!nibJJ@0+s>S-2kBr2Q52?=IctC+M;9~o4D@d@m;D9v-OSf_
zgX>`?u7mz<<~x_b^)h)Ti1slze*wGwOqLCx1I+)tG3-0cPpHIdh*`A*c88gwbHE;9
zUT%ZJU8YWl#!=<~?TYR*_X$D9nXbdYoL~;qt)Fr*pFa)JX{J9P24|Rx#TbPvE4Lbo
zZmbump2(eLS3qMIt7AR-cC!LDV%VOn8cYUGUaSrDX7^@=&<K54DFo)rGH!sLAFG~%
zPyVbG`#=I%l}n)>$nvIQ$UQ909*`iG<Bt#EMlkFBk0BGna#;`1P}WWkV8U2UkE1c1
z)zSjjB3R`oV0SO;HxbA_)`MNpk7RxG9QyXN)_OoPhNYutCYDuF3-fWTxA$Va39PI;
zuyBxNeF}Pstc17VXfo^j?_lUKE8h_Y{UfZ`bU-`KdjAeOPp}rhgVCq3Uj7I$X{@#%
z;P)xka$2yav;L2=YG+tm8=!ZVmG(7YGFjVcy2)Yno<d(PD<vKZd8`%X5IN5hQXsB?
zwfJW^Q^<0nI7Bh)5{2_hSXsX~&{@igya>@UR%jKxxX9{z3XPXoUG)1cXT59!S_Nx{
ze&Us^A7Wssigk4rM5<X2eFL-_)<$P|QOBB5qVF>6mq2)Ng>{PZSXWsW9tEjqu^EuO
z#u`&X?>ft|3zChj<x!OHXkuNQ3;kwRE4?yWSVK{;+sfKZ5xg6$D*7F@vEKX&=G$3M
zZGtl$tUps>qLcMIO%z?MZ8YAStX~2^Zm~+JNc}cz9vwRBW&K9yrUzJsv|Ju!4PFO#
zht)a)GQ`@CWuU`pnB}(|CPr8{=v3uh*0v>39A!N@1~2Zhd^e+UjP(=M>)dAzegrbk
zYPNw)utKPk?g49?65J%Kk`k*^tb!SkY1Y4q@P3A6{TF1GC8mlVSN16$2I0n@Yyxp-
zzvY2G$1e7U$I-c)ZKb_~2m1z<ns~BJkD=3xz3dsFd9z=m`{ToI;DY$FXTE}@A3Hq=
zF#haqR(KJ>&Y*mKAUppdjAaiyJ`jCD?6;`gAejB)6Cfe%#%5rKvIiO=62>migF?82
zty>Km!JbJ5%wG04PeW!O`!h<EM6y>rhl{YEz3&L@MzP=c7ckLmUn=*BVQ<`rD-+A+
zQ^Gxt9k3XU@$CClWp{vGu?2%jU>~&u^B~(oTiHbRN9o{_*uNhJcZl7hg@t6cBXTiJ
z9A;<Hv~`5tumv~vD7%FLgU8qt&!F)*8~-zcUj>`B8rUgpM;@?GvRBeM*;MxL^kz?E
z&wU>#r`V-;ppeeqKzpnVw#W-8XW46gF{Dhk*##tv{UTNBXS2^z^;-^`@5qMxx$GM9
zG>?tAG-hjd9bK<{b{zfi&a*?QsK0<MqR?m|`(_3}i`ZqfdA`8D;RKOlw(2xcO4!?n
zpkB&;G#$>Au~$+M=puX56#6c)8>kehoc)Iz`YPB9>AZI(+kT3Ee^u-gm1wPIFXq5*
z4f{zRKx^4Axk96ky_;_3W%kmaFtjUd1#P^pviH@Zv7UX7Hn`W=vI+EEXM53e(ZKel
z>(t0@S^}^p_EHM&H?s#Q5!}Kq@P$up>^}?;X=giqMBn!5V80QG!F00MOhTp$98BC~
z|3#VlZuV!Cpy^@%`WDb`vCln<zT52gc0sb2?H-B7K6W2H-Tmx^TOm2X_M!t0gX}#N
zpSr_dZ3j2R{+nKk!)&$(BuCiGC?0T^y>Raw{QgGSttT=1d+gc}_%_DA><*3l?1CF`
zah&~RFSrTz_=n&guub2BOtR-`a7m}wKR82gn!WQgfX=WNy$&+VzH<yBuAC3)-nnt!
z4~9?foHW`P@8Z1uGZc1n>gPb+gX2a84GvGv**1*Ai*t?6$ar)5Xff-<@ux}5m$QUE
zA>+qsE`h#3r#=%J0i2zouoTG2xe1s(9Lq*D261j}#dw1`T1rlbaC&<o63TgO6NVJV
z@koJ4IOmo3fEmGge?9v4a-Mq?nEM=@xhe28lJf{v4ejS_;=;u!j&vVnqB&>0U?PSS
z$pdyQr{yznahz5EKr)`wa}0V1IKz5?CUB~@gFDFioTjTp&YF23Nt}g#FmZ@;egI&}
zoVOML<tV3pGb|kAe6bdd$2pEo^fmpHoQqBvb}Hw=YB-$6X{EJdCa3%WWO6v~zXq6G
zjuY)G@;FQB69?xwn<x^U&uOB*^PJ4(04?B1(m)D1m+07O5ocQkFpD`qQN3FUM_LXK
zOF1PeP%q<H>AMscIT}Y7uGb|_+K*r>I3L`DXeDRs|9%ymXG>tdnlsgmz8a2CGTg7_
z$SB)W$5}<mjLV#IHw^R&XT*ZOtDGa7VWOUM#tjPBIKNZk`#NXd3UCdaxz7Nsk)!bi
z*Tnf{2d-f==iL$q+;8F3cY$r?^igTt4bFKymriY*oCJWjbHXX;+`;Lm8{5f={}lRN
zoLstTH#rVkI(2ha(Dt#1v;6?{ZgJl7gXC?_G1@Bib6%j_=>TWJAxI8#lCFW=;mjt$
zwINQ#Df;~lbCgqHM>ydWZNAHSkHQ0^ocU{UWAAa&tI;^d$=nW+`<z!EfluR{DEb)J
z1ZQ<CuH^&H#?`n8lN|MvXq@8w+mFU+&h7wMn&ISlg3NM!NZpnD{APH+i@W513n}hZ
zIeoU@gPZa-G(5Sb^U>+Wt!sk`Z*Hs#qwwLnKZ2q8ayzLc&X4=+GFbBGR!|Zpfa^;c
zs6g&3R79|cn?$M9AntcmdJ)Y1<^`ySaEr&F7s~yJwpwA_t(yQH&RsxT{|N4ljWFxj
z%T-areIGaQ6KF(oAE!reKes;$pix|BihV_MPtd+3hP#J?^zqzpsKV_4_e&l661ac#
z04<4Y_zUC^H~dSONan^+RmoBAGlwB^jN8eB-f?c?Z9t#oesUF!soX8}6@)Yg_b9!`
zGPpKcFrVgD(}MX7_lHp!%;fHT1eUV6FFX$YZ0_W*Fp<MOOxuK9ZYMo~=eP~@nU{R-
z#pB@4b5~P@r;vM@f+|Ja@0SDf0=J98W5wK0s3xX_`w!i%GH!PbxQkrJy9zjbi8~Yn
zyA|C3*x)L;pHj776*rw0p4Hr{p8;CKbx<;}j=P1<&s^rtrzGSRZpn3^UFFWkfve|+
zQPlSu_t#BmY~(&hRV+>10-A!Gxt%o-Y2hxbh22)}cNUNv+?5X6k+g9W&*BEPbN4@w
z5q5A7(}dp3<<iovkGr-Mq@VleJ-`fb#obUG<hsyKe2AMxIjdprjn}}9aC6geWk$J0
z^!cFsT=)ObH_o-ut9gR!LGk4W+}N||o8(qe8P^my?hqACOmjb<0XxHemMTSOxr=F@
zbLDx`!{)|wc@`S(yye@$dGfZ=JIaf9{0lUC^B#!?s1NV;QK<X!?oc+}kC#JPOMhNA
z6~P7Y_EL~MkoP&A2?*t_d;=tm_xLN24Cl2?)8A%9@T%IOv6ojz=M(qw<i!|8B=02c
zWcKqWtsqgn#XkZjp11KNuG0bD$7?_mc-}d%dyuz$BS<2zm-b3Yyw~Z6bBLGT3=_$`
zcNHLqc?UW$vJ<={N~NUmA}MurlDBvP<vUV&zMsQ<8c$=y&`$9h=xAL!@0~IzX7E;Y
z0Q5AkZx*1Lyg!{lvUppb2Fd2J)6tj1OZxzB=kgv|36wmZehV7U@m}<RNIuU!9$@Er
z548cTfLBR%5rw=DUPE6I@5wPVI?8yfX~BGvcL-nla=OI(FB!g-^WJpAcq@46a-dc6
zTxe#h;;pArglb;@!vL+}J-7t4tGwGwfmY9ZoPtQ#c=srvcAfXZLl|!Zub>B*jl4rt
z4%x(0QxdY7cl-h@wD8VRa;(F_OQOA6ColIr(7JdheSmh8cdZPhoA*9F`8~XcslN6W
zZ-@_an<t@+c`r|N4`_FIn+0eb;=MxI%V8deKGZP6`-tLkcX><3;Pxml`+X?f<E{S*
zl4HEsr6BitJA7g90nhRFe6W+eok!r*6p#HqG^TmW*8pvX_YTF!W_fl>uDSAu=m41;
zKZ&xQ?tCq!=yvhl`M}=Im+b`c;9ICb$Cv+MA~-+(L$u!Z=f6ff%mDr&3L^&cB?GXx
zhyNc<enI?04u3ct%zv~I7bAop_%RIb<>ws7u=nvfG<!wzLz98FpMRC=5u^A=sbD*r
zzg-UO82&RnsK@fXeujxS{@nE#L?ZtlJ$gy}AL-FM#4n&nFPXoP4RV+-ZG-v|ezhFr
zDF2&!sy98x-%r!dasFy-KAh6{H|b#hDgHnx98TwNxQ)gPeij|DJ<b3AJ}jN#yCHPp
zbe2EC1576WvJbGc_zTlvFqdC*6zX~WFZ;or<8Pytbv{3?3kv7?tSG1#@Za?SSRsG-
z1KR%;@xOZmmM-wuoWppF`7ctwzl3j~xLPUyJO!OA_zVhGRPt9{1xywHO?o`4`Az~@
zs^RC;%A%J4DCHaL_&!{ixXeF)2AJ3RBlP}j;D6->kw$(w#W9-rpGqOw%+LFQ;x8@y
zguCc$<)2&y#T)$1$bvX^@dF}&eUo2mMPoOgPshJ|_%-i>+~O}v1L$pj-KQYE{L~_-
z_wfg}f(-HJp1_?P=1<VGKEki3k5k>{PcDYrqx>~2*uBSJx(i;6@uO%B;keI_D+kO2
z{*x5`ndHB@3S^4^6r}^E`N<U5o8j--h>I}G@1gypm*Av3On3|aJqmpv!8}S4_zFDC
zAbtXAJ=FaLJLC`v5OmW^B2ZA=2+2JH*#Te%2|h=d*(q3%)d#Q;hhQz0MTQENq{Fu`
zK>_`Y!v&g1!0Z)xg#&b-K=21(A_aCY_`P4Sg8~9kf&_ZxV+0(UW@7~ms$z>1BtHzv
z1A>Ro03|`tN!R(H;9&~aCJJI{>ysoHbOJdnFgy?FBLYWvCpwP`eCf4+OpvVu=y8Gg
z|Im0skhm0$DS}nBKtCyXS_{Qg!C{)hPYI%F#h5O5!wQliIJOLWrv)DIAZG+mtO7YJ
zn7NHXWC`9DKqOm`p@Mpjp!qLA=L+^K0i7pEcYKMfa8B^-m$=UPf`(E!bzX3;9-Re(
zN;;fYD2Q;u#V-=vr9%l91P>p8ez9Pjp63$5R@xhu3UcU`Q6}hP!O}&66K!-a3H&H3
zUoIG@j9G=?jgt_m6qKxn_f>))Xt7f*IMU?+c8!2b_vy0W@hX_OBA81B^;ZQR3(;3E
z@TThGYXTM}qOJ>C9>XXa1s5pI+9Y_a8v|_?WYHe4Meyp2&}$XELL0vuf;JT}+XZ>F
zo$3(mcn2b#0%I$<n*zB%z`6ww*mT~hM^HpTom+y>ZvgwYz~eAFdj-XNFp56GnUA12
zAaI+DzCnTiWenzy;I1Fc4+(N;+87p${SA@3f>m_7c~sE05aga9JQyNl0`o!`yf2uf
zdp|B%`V20@q+sl2=uHWt|D=4!G=>fR8NrSnAhUuvcj&tcCsu=V6HZc<ue)%T=BZu6
zhbVfyTUbqRJP+Zv2=sXhTMN<WC0z0%6ugBhy7)fAHz=IwEBuclt$z4-J8=F&r_XU^
z0)#8Opcg0<E{AK5JwoBv01Xmup(4CsVPF(sLWIRqz=R6FwZP#pp`;Ne!i7FRqAx-i
z8wb$6!nl{vxKHRS0!*aPxewU;g>Gj-qJ--y7!)mhmm)+l!tu{RVud_E=*0<d{BIR2
zy!-(!$pMEj#|I`7gg;V_?x1kg2hJo4?ewrF3B$gHr-y{@6oXC{9{CEAM}?ZFVd9uD
zo_1`<g`YSB`-Jd<Kd@7Ty|mFiDGZtq$y8z7W(+A!cyTvSP6;PzahEQP8-rek@Y45?
zJS}v*--FIG!n2eWKP$An1dUALDO&Pn3DqiGwrt@@3(#_e#cQFME7W%aCQq358~V-(
zv$T-R7apfA(|O_Nbngm;{VU;pp^!l(8%4r*Cm?x2*his<V&R4ma3#VXs{AMwZvNkY
z>y!z9q^}cP6voi%?vn87pJ1X~D5J8S3ZZZrU@C<{Z^C?yP`VPNR`@b4W$J{V&WFfl
zVbGHxSA?g&h2&LXeKttF@L$TWUK7qo6xZpx@KwriGzedtgT_Xo(=)hfO~QU}dajy<
z$EdENMVLZ!eyi}rb+~v#xcyZOrcL-kH2iKCR?z2xJA{84pwKCtrDR~2Fd`go-xSu{
z(AX^$%!Oo+&_4rxy}~1B!1W1lQJHMNu<mV$3<%|a0dr7TNw1?J;g!v_{u~y*N2Qu0
z!a>^D-xdCJ4<j5E=5_%4p77W@z}y!m_d$PL$fNA?gmAJGA`gV)Hz6`999P2aDdDPD
zAu=O;)gOJc!o3t=b`?G92jVV@p~%NB(Z(;q?G~A7D)SIs-$UQF^As(nK%%$kaxRFE
z=+O)~>?>M9Q58Q?3cXbQMV+631c=@_2K_yvEtG2x5`Fa!3<ism=uhWDL@i^`3l*8^
z@d^|1xfo%D$e+SSIM_N1^ZP_0T#O}Jr2G_yVnnR<P;kVG{)tCtoG9fzka&?tE<h7R
zQMBznDB?8(J5eMl1zM7*jS74YiOMR`m@FEi^3TJf)%0>YDw;?|<1x|t(?B^c`t}~w
zPl(3uVh|}JW;E1OMW-KwdYb4_a`cqwW;#f^L-g8D(8v&d$H$mXixO!Me@1k50~E7F
zdfG&1i$=D=?;O!@P0-I3U3&|Pd7=qQQRIu3e1XB77k%;qNP*}%y1#`Y<6AITB)U6`
z(O(cP%tl{{=neX%mWuwOUvZhJJOkWCk;9h~x|c*xE`q^w(RvD@SBhFUL8eNim4mAm
zHP9qfD_TjjUY*D?21hT8`dTsUE21|jka1OXiApW6iGDc+a$UsffMkOxpGc!9nf8B8
zqFKsmG>aamvZhwitqMTj5Dhuh=xh^((<`=JR7jNt9ilg=#H>>kGzm*LMcGe5qgzz`
zCeV6B0~D9*6aD-J^!h~?2cS0~5-Q-ups4C0DBKa{T*MU}7QL4Pun`ge8E|(+*55%!
zMF;-^%01CsBe*fqstN~W?u*V*baF!E^(F@TK=jN?_%<oZd;?@k^yD{aoEH6@1dUmd
z6CGG`6>p;oZ8vemI(XqOE_eytE-@nzqu(t~{Rtj=h+hjupSSn~6^HnUAA~~0SKLSC
z27cm&Ye4+PvRbP54iIl0fJ~tHzfB-}#QF0viXd?W<?VyT9yM?+M7)V6#!&H^24IJY
z6~&MY7mrf$U4%HS7_RLVKi3P__K8Ptz;2|t=M^;W7xSwz-Y9YMD=-)>PNj%ejQD{T
zLy8see1X=VapI3C^BpgKnCdbPh`0QK&IEA;y>}0aIhQ~Z#e<iCog{Xq71$y1pZSnX
z7Jt1ECJu|w^Pq4<d~gXIJu3cd1-w5dE~Ub)<Kk*xK%WqQMGN#4v6_|=C&gzdshukR
zx(j-aG;zsS&^RS-vja3;Joza^GsHW71=?BhXOxW36#w@lM6<*T@575+@$qix=ZSaF
zJv=A&>H$|Ejw!;mC=@fPDyvAmW)yChh@Yh=w^ZyxTaYqw{Q)SHi*L?_p$c*07qC$2
z5YMiJ`5H0rBe1pNNFns=!~rR|_*carBm<^iETWgpHE{wR6KfPtx<aH$+)kxa&0_sp
zh};nWL@Dn!aV-T`+Qq&UQ0owXau@z~if>NCi!SlS4RG|PIGc91-D2fi7+H_l(NzeT
zTjJO0vjn%r&u2iUPt2ucNWb{{d*BAdofJG96lYL${*E}`8_o=ikISJqBKD-2?XGw&
zJ^7>J9ke63C+_TpGh^bDBG|nz{$LBh#>Mw3eLo?7hXO?p#C-<Xn-qWIpc^|So}p)b
zS}X|$=#03a5~8!><7)J|O1e!j;U;<GL!h}!V(TH|Aqn3DgPxLWJs7>0B>X0bw<ML0
z+WAOoRp5Lj&U#4tNdo9|{{E8HW`G4sUZ6$V9?1xnUQR)he>fCr4VG-1ht3emI{F!h
zN;J<xCQS0fC6I8*vu%LcCyDMvU!-KrjKS=e_+5rVj3jmvBC(Q}zrtYRBnOf};w3Lp
zeck~{0X-!LB_EB$e4^wUg({OI_P^10Nb>n-=u4K!w$l3Zuw)_%>=DW0_c6kwl3Chy
zACq{}6n<RtemgWyOCF_J`ix{N{o>9_hL~u~lq6GfAWO3DI}9dU;>?Am9LbiaVJTPg
z3+*KGBq<MrJ11FB8<~6wg9UP4@+g%R7DzfiaKi7eQ1bgU{4SC_OSA0-iT9HLEtZIU
zV7^2$mj%&M$)B`vEt4#u1;Ry1LkFC>B>6Z3PeQq*c@QQlByPh{sFV!-gvKg~KNTcZ
zOYCuwtdU$TM`NvIx(JeWl9^|La#ivi)qyzbC6YLJdQIXph}K5Q5}Hh!B>i5{XqM!i
zLt~3%F6HrBC7+f<|Au7KTv+Om?4TO0PD%Je47*FxOY69slBL6t?3Q#zLcK?_g096a
z$?iG8ye&}{f%Hm#{{VLTB*XM;>UT&Y!(o0v^6^Kw2!oR6X2IQ&{LloLAxX+shz?8E
z(hhY*^7Vdz-j#UUVRuv#odS`2l7H&p%$Q`^arE7nG*J3+Tr&JLL?$Hhmw@>|@_awY
zq@;fr`lckOD1A6Bd3zjJdq(0|v>YRxmGG$y##OpO0vR{yXbt>!mwr!yh+Wcu>5}Z0
zF0O|`59zb?Q}dMemcy=>RP#L=y`{{};C!TK*1@i?^xamN@RNQRh(>?u+-fuiNaJaF
z6Da-o6*w9!l~P1GM7r9cflR1$W)WJ$q=)0-MY!}aS{g)18>PVBE8RT+#eLEkH;_o_
z$3~F-(yd;QjFPtOhriL%8;c+rBYo-<=*3F6(!w)N`WTgU#7hTb;O_zHz;+l)kb3Wd
zp@ULG5hN3(m-bV=X_8d=D)f`3j@@wTu+&U*{t@YqmmqUgdX5g@9Fs2A;v$}qdd!8v
z6sas93MZurw0A!x9eNv*>C$It3eJ#n=!Tw_`q{vpkuF!l;92Q^lw8Y{9;SCxmUJPd
z;j^V}1yt{rBW)2vBUc(u=hE_|b17VQPCED)MDwNnYhdua^v|m>Um(>{SiVr2HVwN)
zQX%~|FGy4NVuZ!gw{y{0B5iSiluEy&*M6BalLAy1rPC)Nc}e=N8j|JG$CKbph17J4
z>P;)92QR=xm9#1ZcB`c-+GN#8{peg-t@QgAXw*rYXuW+|djAR}uSj<{qVKA7ZxFca
z(zhw%(jcAP2+2n20SSiIBwd$_#%AdpdPrNOZWMHDm3~9>`3>pWWoT@Z9?FIxN4xap
z321akqiA8&C4FQbuH{W>(G)bgrIIA{4NBwkLGDP~D0ej^y-LBAVd<QFa3j)XRD*O^
z+Dnq7(ol+)-ILCvXy%yo-sd3qrGL>hIU$XpLv9bGDhBLMN{`TilqrYQb30n6rL`1A
znvn+35zbj@FqMD0$=1-;$6e+{;pSbky|kb5lpXDcB`;Ylo&EBbIk$lGkv;tcIA7VT
z+d=$fre?V2FI%%1T!8EgdRPKwn`leCM;1!q@nG5ebZ8_*=BST_OsMQ{`ha+t>@4NX
z!euK?z*2<l-%P;lmHoQ{CL(1V$_DP2wa^nBCEL&py=a+Q4Yy-t0TkJalQBO8O1x}G
z4%8E5U(iDApe%<LVu><w1^SX@9_yigSoRo|{vMHi>!4u8DH$^!meOUv1Vb@H_RHh&
z;<U_2ugWvBycsl}l@-#&nk@^a%t4N9Aw|S;Ww#eVFHhFn0Q2W$xn?+%FY~9c;Cb1v
z-@ssj>|-h(DwIujK(9!~p{4u<*$yfMDVF{H46Q#)WoG)+N|~&IV!;<>CJJm{lEuFR
zFUn<t7>HKMz8L^lEwj_|w?-Cr6kM$=dOgtUWNWFS>9Wj?s{60Vn&>5QRkmsa^y+2l
z6qmaudxQc#*JYpALb5?tdJto2lx?@t`m;$^Kx>g^nX(Zsw#e8eP;8ZbzY64r%t2x9
zHrZkd(X`80wD;(c{hEyNcFO*urDB)N)(-WXvOvlicgqTA;YE+E?HQQ3B@@05k=wEj
z)YmKf@o~7;C;OGAjec3r1$zGt$cAW5J}5iWhSoc>IVm7RGCc+Phh+)bfEkfJHUZGP
zvL9~2(x~hpRVLh%9lZsSG1+2ztKFA9%mDVdY*P@p30e0bL>|am*#MiA{V2n&n3Dbd
zG~Aw+t=$d18QI)R=yS}<UZmiet9&heRmEM-r7(_%T=fk)J>|u;vhb4MqA0Al{Er`@
z=p#2!LA|ehCmk&DlfP021%LTd6>u#;UeW~ff$|$60NW#Xrf=8;$zL*~FIYbKI7o<m
z54~eT<+&7qjB?1QzW`{o{6Y;#j9mLII%DO3r$RqYz7RWPr+E2?-{B%0kVnz2OpwP-
zW1t7+cdvp=l-C!+nIySCt#%H{1@!Yzmh&lZcvzl5<w8f~|F;byN9E<TV>>4QgTjf&
z<-Z?C-wC<nz)rZBA`g2G>`D1MSrAQ?H_X6%ntX2}ES-{<dZ8~}&ifcc%aGUp3lC4r
zc{FLBk>9)p^|SJwE-;uWe|;IaEO`(GKC|WS6s^vYFQNLPT=|!DkUCEuM>F_2dFBM5
z^W{eza)_Rn`%+}AK;BMOT7~ktls+kvn`wh^L9XRMq*&e*2A@jgC*Ff(nOsH(mM+SV
z(c^VVKD`8X%jHc^z*2=={xK9P<u88?g(~^`^lGh^FV>*3M!uT9F;^@9m)68}^1Nk~
z|GO;zjo!Og<nt*!aZSEu89J}abN9f-2Du-Fb{pmPc3?NjAKD9%W_e*Nyl9aR&`z;c
z{*wxlH{=gfrD&UcRW<tB<umut*dh104G%lzR)6Sq$+yr};HG@a3z*&VeES0Y{(9sa
z=zBu9<n=otb6c)j2)}#f3%r5WCwE_mzJ9svdyoNnJH=!N<%`xq|BhT5kD(38=jg!=
z%au}aBl2Ywqr5BU(Jy9Hev;PW_vA4vV0TR3fOwVDefjpykQ|r4jpH;9rwRGT6wi1d
zkNO#8QXWr*lvDESbU<=iZodVX8TlnMxLJ8k9r|1qo94r{U5d67P}r@gkHa<eP?S>P
zinn6uJ`DOO6w$EctN4B%^a2!R&LDw`ZXbBRN3ja6PC*JR4DkC4Ry_4Iya`c^(>^X#
z5%)c~Fohe{NQW!#i(w){v8)N$dllX*!0l5kS`W!c#XnT7yI<i+iGwIb<5mniTH#4m
z*fEL<TG7WUE>P$%PEk(v?eU7A=K}M9qK^`~2?`;FVGcSJk6l1#qM~*#NRlF&GMtAL
zA^8|nvI3hm{Eif>?ck0nCfC7><BIuez?@JN(yW)NaHd0|X^QjnAaY6}q0nEtA}$YH
zhGGjP>`yDWPoVLP;*Uje^sHjV%V^A0ycmSWEQO;}1hi~L4#gF66uxBu%~i191(&DD
z*#>e>@qqTU`HJVwxa#K>T1rM1C{`<Aw@~q08DNSOwb9@%DC%S3eX*jn5L}7Ecp3&v
z6>I0inKH#cZ{SW|RP6i`V3!oPX_hWmOgY>@D-``S%U3E&s64+)u_+05YZb54KCDi$
zn2*NGil3=Q?24jzF7&S|j!}I@y+Wsli3UXq?L-<Co|G4EQd~I=?zSS;8(#D((ze2U
zpJE<`R{Ir8=xsKjh|j=97*zD8(PHh6;$ItDhZL`#gyOK`?_XhJMByO6?<(|E#WSin
zM3KCEia|Q-J*Idy0h0F>@~iNETro{<Pbk#1S9+j`SP$$;#Y=e@(v-rJUIf#M@I%mZ
zRi2{*!fs0DVVHGS{<V+(IAE93H59G8m26KC52e$6Xm~2ODInve?4!aaZ{-FGv-v1L
zTmjBknO+Rn{FF`<wenY<rO17NvV;;tfy$TZSG-3VOU3p<%3GAC4OY$>fTJPGF`A%4
zl~)Bo2~&QC-HpR3T)Dj#Y=lxnS(LrX4G*BPPx&O}FCvxCQmAvk@>PmnMJdlwMMbpo
z1AlNa$`=d4#VWV@LoZJ0O4DS#Qow@w1Ii_|$V*Tv>3KS+Y}^7aQTZXI*prk#^!qua
zRMJb$k*xfPq6LSQkI+u$i1G#nB91Dp^MHL!895L7$CdNwJlhH7!?eUrQM%CdaZ>ri
zBLGcR4%5CdO^G-JegMj(CqUAbk5C{mL;2ALIC@$cNIT3kO6%7EJFEPbvP_xE{?#y)
z<xnm;5A1B^zxzOPl%La)j$CEryMW14{`m#;&nd(Gppmb1#6#n}a$YDJ3zQW!2No({
zpyW@H@;q(1E+|<PlqpuKA~3=drHww^SE_u3Ch{`nzWqSCs7z`E^d;q)SD;X?bX?Cs
zYlZSdy4;n@YKnH(D1WCUL9Ox<<#Otj>#hUsG6FWxxT0*Kq{dZc!}}Oaz4B`+EWD<S
z^22zqD?g`-&jw}Te=yOgTuvGHCS}|SG&U<2d;zc)rC>WQbE|TivaRjPYmQNLb|~4D
zMD0}Wd=_Y3%8k9~ys3PJ_UYZquC?H9D}xq6q*s}?9{PRCF53SMD$i7*@s9EqMS6ym
zPgAk+U1eVhoEcT-(dmtQ%B3`Qk103NN!$BM%_{VbD=Qa)n^1cEAHDw`DA(PFZ<9(5
zExV_bpHNNewDRs#aBW7JnFNhl<qTD4xvJRo(E>Ns_VsYhUDZxYuU)FEbcS-bD(qX_
z7%x>k1t7gu-(^70M^#4?vcD>M2wnuJ9#Hl(P<7=8sP9ot9;fq$L8{WD&<IuyG{azs
zijfCPp{h#SZG@@bUIb^tRfSyWN2naMX4|X!hC<Q%RFQ9@FH-f<b%5?yNt(b#soa;t
zr)X9D2z-iBRg|DHUNxTq3kOtNXbMeGrN{uCq|)HQcQ_qV1v&vcS*3myorhHoF7WM$
zYTd)&j;b<h!5ve%J`9cHs<*ep(g{_dJI0iv+R=@^ld9+b0GF!T@(V=LRNFSd(ka#a
z7&NA<W<CeWP%U~M7EY@krXcPa)v_b-FiX`%+iXX+O7tDZo1;=5f=r>R`D+ZVNEJ$9
zf(xo9D%2}hc|4595>+#;6G~NoUxs3tszeNf7gcY50KH49Pgld4a#bTuvlXh3`_Wga
z`p^TUO7)`<q+0dcP8h0Dom&g@wW^j>K-W1`5wW0`Rc%ypR<GJe)xy_Qr<(zDU9}+#
zjSZ?GdQ~>6u2F?glPZr2xtdkWAA?UVs#FTiwyHkIMRaOch1Y;|sQ#l>Qm5(z%5HV3
zjI@HfsdA+|*{#Z>%7h-359LH|sT_-vz}{AEoCnc<)iiyHctCY<I|e$a8lW7-9hD!&
zu!mH?z6p(CRTdkKBdP=$T)V6CD~G{RRm*1>+I`hJimHsO%#_-kP<_)4y$7nzRGmDj
zdXH+Pr&NB~P@h({<buqozH$5myR)jVD4Xc6UQ`9eU1}-K`McF6bP(H1y+(;XZ*@O;
z=%e;7hCzSzg8OhZKy9Z)WuST;7hJG9-xXYl+I|y53RO=~DmFsB<`MMmRloKLp!ca&
zVNj1!`_m>TTFrQd;x94ka!(jcRNv)7BS{_94epTojZ@%~)joeh<gj{u8XP{N4(bQm
zQS}cR_;gG?m#XxStMBHZ@q{{-Ho7V5N(w@qRQtXPkyLf|T8N~nJ*c4Kl-lza%%`h+
z3t&D&9Z*Ogy+5rE{{)I>)VHnZJgd%K4TG8LkxZD+QhyYTzHD_Z2O2r*3JE}S)e9)O
zkf(m`4Je#bGkxH1zWP5R=heNGO(;;i#KGSpbwmQV3+i9)LZMh~dIVmSsM{96r&9Gi
z%$E4xlX{Hu!xz=v6tlmi{+RLz<?3WtjG{t)kphX8>U+DOU!|V+I$Wz(`%pPcje6D<
z*tO~}e}j6R+M<HOWp(~3pj=Tu;tKQE)E8^ecwL=DVX_AGCW_oQt2q=2Z&9CXfuy5V
z-Qj>}ySkW`)*b4Fqv-5ZTP}j@QqNfj?xuRgA28kOCG=Il+iLd@L3-6Ov`z0*r&9!B
zP<@s{{&&;~4CoE1FUin1tgfXJrV;grFGKyV+9?W+W9qpyFW*-mc^PEfp&q1!<)r#E
zTE<SPt0@IFtv1cTH&@LMG$uDqELH2fYaSHCQ4h^?524Xh^ZVz(_R?Hx0q3nbK=CFY
z&B8+v@zo3lg9K~N4Wlna^C-oALN&jaLL^M17=`!Y8VNns5gNxyTKDeNxGskK`!v;5
zz8a}<9)#$AO(jJFqBLut#np?}<Q@PQqp9_VGqIYkPoWp5+4CCu;x(V{fHMa)_dG!o
zH0)epAJlXoKwqNf7YYU?X`ZJFszaJ``ebFYMpBQy!<zRU6kR-`S@AYHk7{JT@Zy+e
z_!=x7*ZevUo}SReJ_<`Ins@2vbW*eR8DOVsb}hxVOw;V9n($K^4<-82H7ViXGBjK0
z={&9Z?MXOuMkBur?yP1w7hsv1W5EE+(r^>uMYd)nit-ORnt!s;nycxnf_|RnKZ?|z
z(*!;VnS2e0N*~W_Jg920K;!fq8VfaV(qmnuSwxBV3mTagT(KsXX3G*ywFkIT&1g9E
z$}~UTfXGG7OND5>q?t>LhjPtl8*yVQG?PJ8e_g5Z>Vr&`rk?_*)tZ&GG^o+Ig@U`R
z$)$YD6-~(rU|-e9>6d<8vpE2b4VveuhN4kZ)(N*;G;`hsN~?zZAM|c$wn@?0p*gYu
zV4a!|bg<i{sVl>E>d`z;o8ViT1;|D?oNj9-Y1`YY*&YO$KFu<knEN%uuLFBP^E7R+
z2Q`zljl83|L)rKt%@{oi!<r|b$E_IAFrS0osD^tR=I?0^(tI(dIr0<i-q+mT0QGTA
zAr(?hXl}g?g$J5gN)=3MJYGPbV@l)x6I!P=8Aj;OXr8AVG^=r?;FqiRhg0Zt)27}*
zqq|m0uZ3M&mvbPywJR&(g@<;|9`t!?{Z|9cOY2A5B5&<aeNgw&KA?HoS3AT2w4ZkV
zc{KWKUuVO7fcB5MAb}3;qeA$$NBe9H6oa&X{{qoq?fL{XhG;jg0T-&>{5C|xv|+EJ
zF<k532rfd)prGhp?IlWt?bAMY2+l-mJ0FF}e(j;f@Gwfd<1EZaYgfg?ZjAQt8aNuO
zt)epqaav{xB;&P?BuZ-^(B9jP&IIktTL5}c+w&4gqW0lBU?*uSDUx?co1FoYtaT^X
z4r@p5(ho-)O<~2OS|h#ok7<2rzBsOZP6~2Dd!iW7DcU@mC{AiuOv0H|ZNp8NPt$Ic
zLE)6P#ql%H(zV63&B)N+nFE>A+NKCNb4L3<1tQLBv#;SIWNO*;Iod4k{Y}8m*1k$5
z%Q@QYBsAt~<*$Rw)9#-OgXgrm58-{j_A*62&TAv5;C6xbjX+=)YQLpbY?1a)+A>|x
z&RgO@XR-Fc9Iz$Y50x-qsx70)a+!7s53XI*x-WsoCG9FPOq6R^P^`Z~yPuxGN^KRr
z&Z@Kr!hl_^Rlb0s)oFwGqVclU`(1EXv~3h8zN-DI2kQ0O7ig7pO)Fjod)Kv>|Dyau
zgEos|jg8vWuhH40ZS{xUW^FZ9S+!`pe+Sp9ZCe118`=&kd2Z7N{|cYlwI*8Kb!gW-
z2@{>#T`Z_~X;)GV`KGpqUccR19-TDo(KZUe-O?8S1BKh#CR$7PYR{wC*WuKs{q#>L
z_G>c^!qR~D-X_QlY74%C%pL8Y6lWgNo=Jo=!`joopm9XYpu*m}+9-PAj%t_Dbazj?
ziH;<XY3F)F<i1w^1p3Cc3ACY@(EfG<>JPNBHb_otO|-zC(soml*)gqkrVql-Xy;Ig
z&aAed%9UJo%?vcU>6*X8(01#JXq)b#bLFAYQ}<>Eh?ma$Ei`)T_LD&$-M3VW=c`k%
zgui||E`>w<br<%bF+kTuKjuJPz&e2K(KUCVF-SLuBD=v3o#AD)hUhvdZxX6|#TWWv
zI;9oYIb1hUiZMm#9wJZo>Lw`2zfbq=a*QcbcWE6=?AJXz1ujbWf9W96x|VUM$LQ8>
zfnKccUlSDKbggtKFkW|iJq#YuEm;YF6Lejqeo*HK`VhV)>Wq|<P13ESQv!!{-}d1i
zChPL*0drXQ9L0T(=w7XX<WZeFRhk~t9dkk7aoq$xY$tU7Oem!2cGI5cr0%cHa3)oE
z{Uk)vb$`=3E<@)=G3e8}x@K@^bl;QPXLYp>cet3Tn@I*tmM&~QG_rM33&7>*cG6c8
za&<Kup^>L^et@B!)BQvxPzAb^^cySG{WAhmq??+7PbIp%8!%C-OG<-CnXa84`EuRt
zDAX%-PAlPIrA|k?su~@OVpz4h4T~r(P^T+-5u{OfSdP{v-H8NfH0$&!Kx@(6pyMX3
zy0LfR@C{wuM*0Eh)IY<~cHRE3z;)=ppjBa~?)@7O>C*Mb;X2*a#Z&aRTX#(X(xc;L
zL*$n3J32LaTlYIf6?=6a`LzG*(@jwIP`_?V6Z8jk^Mx4Gpe~5Aws&+B128|NdybyK
zVO<v0rj6*bO3`>%x8O~{jOzX=gXBG3+zm92>24~3a$lECOWaA_FwOE)y2IxnGOhcI
z4}WKLtyGdQt9v_*-hZz8{J#L|rZ?uJ(_Q~{C>-|GN7C!aOFy&}ir)G-3W59RYw4Ba
zt3O2(jh}vE4$S-OU1-M_pby!I#y$EibUrLdUoeQqVEr%WaeG7b#fN|rs(<%)sE6sl
zqGNpF`g{9e$PuAGbOADZ^`F0v&VBlQUxMt{pWy;KO207~V~W=6>4aj8KDiJ+#p*3o
z(HpN%cnbOl^r@7{PS6KZbTLuyl7yip=?_ub@{m490F=Y}s@*_2qQB#TD|1wTfGSpw
z>96?#<+wvHybboG-ftQ7Q}y590$Q3rkk;#`^hV0lrt5`rh-B!6^iw&l|BSMbXY>tS
zkUXn*9RioFuWrH!bM#5=kj&M`JqgJ?eg1lobNUe~6wlX7Y1e&TpFkh8F3^8{4eEt@
zhf_Ngi}a_zL+1s(Upt&C*8kuPjS~GPdf%7opZN%VW%>cC0J*5|`vyb1q`yp~DA#AN
z23nOqWEx&n>l2TG)aXy3u*s=be_ajrI{g|7j$GD%MnS$S`YmVBcvWxIK)qi7nqw7Q
zyrw@wi^S{t{hJ}$p#LxvolW|eC=1f8zfO;Ci+<1w(yCwnC}3{r(~d)=P4C$Pu3ax;
zqOU{Wdkx-q>R)h&hh6#{E-c;D$MmAHTmSoMi1g?eAA;U3{p}?nxAhln^!w}8zqb!h
zM4vvKDo^_LZn5Yb&`&%DZcv}+2cPcfk4Axv=<RhNclFyuP#Dz@2EhD%{lBznAJ>o6
zVh|JhPu~D}ps(49i!iA_{2D~2^mX)6iCKO4zkqf%Y+DBrH^UEzKVm^;2>c$cyA25k
zaP>S4Tge$u!vfkidl@>ngY!1b&<5GZu&W&~zJ^3Q6#NWJ=so0bc#m?h0S56y01Yxc
zOTo!tgT4z2A%<<gfP@-&Bk&^3FiH`;a6^X<C=rGg$X+^}_8KzincHVr><LSe1_Mnd
z`wbl{pb=&G)g3-X8x~%{wTLks^o7A#!{qPKk2B=n#jxWI%N~Wo0mD5iib*g`JL9Gu
zG(>(3l5EJKij~8Lm2J>FVpvEy)T4%Eik%%ZyjTEr$8p0F3h|sUd|Zgu6hk*9n@<|t
z=rhTwhHsBRCe8354~nM@JKKSlZur6z1~UwiS3yo2MkqFO#;}z#vS$s>?_v;{hO`Ax
z&oV@}LLu9b@GmUn7&2&em20?4@!CAY1zK2~a~ST0LNVWv`~=8(L(oYWEHHdQ1xAI2
z<&?)OGBg~6YZnZ!&?3CpP(WLW5<`y^jirX~69H3Zu)Yt27Y*B-Fwjc|?PZX1!zMN)
zD-6{wkgPQ1X2L?1VJDsGtu~y^1gSANcGJXKYbc{RrOt4aaw?Y%5As2-82+aD=Bgoc
zA)Ki<L|ni?uNlI#!Cf~DQFOk+uxu^3M#G2`9Bncjq%3i>;Xj&aS_~Qr&$Sx-scQCy
zK}<(o+YD=3fYNTr8HC#%hTV=aw00We+R)l<I7uZKJ%*X*(0R)c^d%Z^8-C$Hq}TBC
z8|dpZsLlhl-|)>+jCa7$M%j!(!<Uya&^v~ajj%LicwCPm4I6yuJllxjZz=%0Yv`t5
z#i$|UIrw|u5WNVJ<AysO6#twsyix)89~ewze$p_X_NG&Yi&S(mZ5X7=l^Mg+%OE*x
zNL>J*T#apXo862*ti=U#H$IyRkzGce2e{qF7qg(}W%Q+EMBc{uC@A<C{b;<tMq>~x
z_!-yoA>wZg{+-@`0mg&0S_(9-qXNM_#&G)JV36@K4txqWe)J41g%}(A;eM#G{YAip
z8Rb_X5^j7~0+9&gwTED0uW_jglKYG&s?Zl{jCdUi`;Ag6Cy6p<Jq3f&MmDVxV~jnt
z<cc*u{S5v74jBE9qcg$y$p=t8XtWYqqOq|QGD*he-MC(djGlq;Fxl8cCms$P*Es|9
zh>`IkM2;H$)1ZFLc$ACA<Hm8CL{1prrEEls@q^DW-c;jR8@M!Mdla}+#tK^8r5nw1
zKsz#wnW4})ZG6fNoo9@eD<Ef$FIoYbY1};p6IsTA^YAI#n79pGo^f+O96e{;R)NNR
zV-a2TLgPyUkRl_KLRlA#&(o@-*qGJ<6D7uRTJDz`olc>z%s4Ls<f8FkE-ug|hw)l5
zER`G6D3euTlvAvu(pd8n(5j3pY4==htfW0@jq#U6Xw(`*eBf`L@waU-f7!VGD_~zS
zzDFe^SB+257O~#=`T>AlGYaW!(RJg!Md)iVZg~S2sL|+3=l`0F|7^lonvIUi=Yic~
zOqhjYtMUHVaQKFChaGm?jKNgM)ox6p&`^i*D_TBx8eeNgUzhQyE67b_`@b;XV_dug
zdbf-c3O(F5T9!hu*Jz-ZX`it`36Xx|&VDow81Iy!anQJKA)L8m>~~P`ddT=a<pYL|
zb7|NkMh+En-8DK>Ma8JmPUN1^T?a45j0bjLF!znQCjdHbtQZ3~VcfhB&O9(0sXS`Z
zxO*6wQ$~{#CZ>(A(bo!Qj7#aUoHZ_Ez)@FIVgMT5Ofg;#h`O7;rCYMg^pq7cyG@(Q
zfbC)WYXq0X)AZ{r!1gjJeuap)>6KFe^)b~&gYz{>o`r~?X)Y}%{Y||;K`+2Gy$2-F
zv^WbQdra%-c?vQ;M|qlH(>t`H4>3*u3iF|+?k$x63p3Rn1ZcRa+8+arFsZ1(VXx_>
zRA}roxnBWxq-jkUM!(<WN@3$DQ%*D-jW&HjZ^IZ<3>BBfnw%)T6=&jkKr-IsN7K~-
zQv^*g2_^>}aX4sN!h}eoDc1&)WSSbM{NEwdnNEl%n~Z$;cGx8P0iZ`ruUG(c)U=ZB
z;W1NjEgFxTUZ>B`pD?Zc0-z}-H!a9X(-Artoof2n1AS>G;a=R4Q>LJ;=u0;}Gy&)g
z(;-@9oi&BgyFAn6LLV~EGW|p$2S>JP2Zfe$Ob5H5k!w1!2!qKpt*48B&h!f9p7KqV
zw68gD`fe{Y3QUjegfoSviI2e*ncA8ma=~<pR<p$>GgTIqn3|)ZUTUhR&oY#ml03j&
zH1Q}^aLM#nCnU>F|Mxz8s&JT0;h>eK)?C=FGNn;4x7t)R2QW1z^GoQfHAT|xsxyUM
zfWgbAUw5PLiph;$Bv(yQdNkIX{-f%yYo@GH7`$$}d=z~Rrj<0GH=4?0a1EPGC+?xK
z+4LA?(_2jC6gX)$IXoIbZ<uyT;9{Gpk<tn6Cf#rFw8NA^-&^Z6E&BzaT_!g>xSOVs
z!w~5<h0w;J$JFJ4zFVd(|9e%LmPbRR*OY$}B7LUk{sBtAsXQIrfa&jG7#cKLe#FJU
zW16@Ke}_zOJ7`TXY|6b1^CPA!Pl3B@ntL4FsA>Lfpxrb1P%d@M^m-Ry?wj7>U`*qt
z6)!+!!t^fX!ycGE?SwOv5P`y!=|c+iPMdO9!o-Z}v^OMYO#+I9yP8W5!V5R^C%*v9
z-F)z0ihb`gzd&n(-R7ONjP)`<o(>srbMSHyA2Ux4hkeZ~DhT#7$LxTI{^rMCK;s^>
znToA~%yZ~GU9fo}9r+0}cmDvN!p({A05ihOs6pdiGeZNi&)iQ*m`L-nZ$b8(zj}%4
zucORiE8tDE+3z`!81u*oL}SgT{(?-LIaG$hB$&$&z{ElGrCkt7G>_!KM3T8J9^4`G
z6KCK|vYE9FB1g>z+D9ETCoBWXadY&i=sRh))0IgzbGyK$nSVC{I>Y=bqDO3})8?<1
z0PT!flnj}(=5@5*&NOeQcyE^Z;vJaCHaAiNAjce^3jJL3EedPonQw&y=A8K~9c;-r
zKfDGCh2|Uu>=v05_TF%x`>MlCLEv)pM^~U;VgAYu7AnnsEs(4-e|`;m)#f)T&{Jbp
z(gag$K1BuUb><IfPk7mEHsWSqF&|{3@v8Zl9`>%8-~JwV>AJb{J%}`z$LTfJXwIAu
zuF3o{Rg5&7<42*_V)k^r54P28-VBW!=8rzWSlZ0XDcaR(-uDg6cbR?5F_xQVw|IEi
zZC25<)?+qN4Z<yRj2I%l=1N*a^qI#~px$qe{sKc9FfX7L#h^J+g~mJP^8s*e$o!Hw
z20v_mF9_U-`RC=7-MVXbT!lBI=KrHJ%=gTnTOc!L9;2Ahee>@xf*UuNWdQAg*@-sD
zljeHbJ4~5fX<nQ*AEg6jGv+%~CNyg{{sIM8OZ#H@<YsC61C8#M)&D|$m*uf=klmK8
zRJ7+|x&H`7_dG4B^xpNdaA=$0ZE-q^G5J}Zr-{PfvY86F0xYrr3rSi2qvUq5W#@j_
z4YACpy?3Z3ooZ^rEI(16GTgG+2yUOHcn(A&ExTy$+i&@D5PeaW>|wYTZK*qqz8DJ|
z#jg&hSWD{vK_kv`MGw32mZemAa=<eGZHy_wQk?^z4qCqa6eQ8Ia26!Va)!2uhb*;}
zH%zuvQRU=ei!c4t_z}yMk1)dHmRQPhpRin}-ARh2)C_Xc!Vv>A)$$Jo7t<`y_kcJu
zEbA%2blNhP0w8BBJgN=NvMf!6!`YU6`j$qHrEL)m=34%yvbQ|T5jOliXIZQRXujpY
zRZu@~NumTxf#nE&x4O{MABMgn%ei217c4(7gnF^%M^~tqSXR;OUTVqffxR+^W$Y=K
zxM*1!4*g4(Bo4+@ZW*TNLWQMg8?Y-aD-=MhvUvXpv}#M~GN9F1q+O7#wJduIeRY<?
ztKcqMHqq|2-m;ul-PbH3{TR!2OZ8rm2Fnxld96kZ%LkH8mgxWtu-W3+{vkA4EDI^J
z)M_yqfp)|4CSC3}i?ITY?Uo^$3_2{9Yf$X8yiYmbF3SS?AmmL;3QZf`mZmQt*<*Q?
zN;Gd-bQi(hwydwfAbKq?K80cTS&sH&*!>pEqfj5P1crbcv^?ZE4beN6phw}&kfn>}
zz!A%zkD&9e<*_D+j#^?i1LmG37`5n5V-`E@N$*<>gBa7eWzNS?n6T`m-`J!@YX+IJ
ztl0_mY0HLrP?)h8D6=wasiYj4tM$=O(dcIVV=?r0StI_Y==yGJSROh(tZR3{3r}ku
zeOb!Ox|MRbzSg`DaDG-cozC&M7SQ4@z-mtdXrOf~9~WVdRdWvpgRFntLSL}8_eb=F
zSYLh|jiJ^G3SEa;zoKwPxb@HDz>KiETY<UPTC$hEuCUK~ffk36)@NRZ;(lvhEruOs
zT}|PeXzRR7@HEESwGMYA*1GQuNSyVbFzClymE`>a>$7}-CRl|_pnlN$4aHUxt)2*-
zJ0)5BX!1H_oqHN6$=1aboIh+eJ%Gp&tM<KlbGADjwU(cSizlpemjW%t>iU1cK55-N
z3z<}F#eQ&U)-|+1KV|)%7LKQ_vGnMkvA+Ai_?GonI{GrLKiFVC%Nn}(yf;3Yx^n}3
z%ClzDw0_QdkJdx^)~7{iJa2vH2z)BEUZzk*k(EIa-3!(i&cL-|Yr%hLEU_+hgJh|-
z<{(I!^~@^RyJ)>T52V~WLbZ1lR!b%%E3GRRqp`|bLLV8awu;)IP-A_>LEhI|g?VVL
zv$nntnafrq1!JyQ%{#zdwVDIrcD>cs3%9RXHIyQ_ZarHBy$0)X3imWxAEvW1P1Y-a
zforx7=fG}@weuY)v|5!^uXe-w!2?|8HtPn81h-osq8hjkYnGDAIy$Y46zF$bBWUXG
zvAX+0<CZm=j?MR4pQAdeK5Gw^fA(8PRWLtbJx&{fL2EMIraRXCKf&OT^{Z-N4_mJu
z1LlZz;tPn}wH~KKfTPy0oS}ZtT1!dVF>BHU`o^t2!}M59Shp7A%095peF&nH)?!+^
zOj*l5gUpQea2?QQts~^HtF8Gs%)8klSa8kV=7@ykZkyl+)IDrNaS-ve9i&&Bm+e<t
z)_B{t(^l5Uw#grozP8W)1?OiIQ<%u#_ADMwhf{#<FkPWQTRBZadu)ZYHw&`yzl3P8
z?OFPXhS)yZ0FhAJQ3_9o*=i}I6K?y9LUs|hfg<>{-`02yB+7QnA0*nwp$Rp{c4HSr
zVr`%N0QETAC?(V5Z8C~&9I$D_(C0|7{Um|GgSON{j48<`pg7YZTk#(dO|~`U!;8bV
z*Jv+!#P%EQdXL%;C!_C}t-1muJZ?MrHqcJksvd!Qif!Eim`}Co#L!E#Eqn$dr)=_<
zabwbL%hy0M!<PC9z)ss1#z5qZ!?uYI(wwygrhv_~jnURU%jUKcirKb>f55do+p*6e
za?U2a0FrNup_0_|wk>qlrNH)EIP?l_qakQ4vPIgUe!-S#$LNb~FMJ1u65BW1V7Jtk
zW5&qJY;!*WchUAZ9mu+5b8Pqx8s#=us&}ifO%(yO(iYGFuFCc`l~GpP7SfWS#@0!J
z@LJm>ZD8tbi>jc1*(RZbRab0Z{{-x-wmy1s)!W)=BXG^;v<l?9Z8;T+HrQ$@@!V*W
zuYjXXwm(+`v)T5pgNn~vYzyhpZL`(U@r8EV&$N{8u*K2dyVDlgfvetS8yQC5O&gm6
zmfg0te{h|9Y_S_5dCT_M38>$;z5F^Pdu^}L`nu0{hZZ~iw!c0G8L)}|x5%<RMb%h$
zY%^3>G-P}KDF^7V?J24_8L|CDnV`G2K3c+$+J1|K;yv5i7J!b~9)1iW_if{}s2sO_
zN1MS3TR!DgAK20<oIYtgN?HFYTWJwQrfqvDVK8HRFCLAvHr5P?tKIc!pt#vjy$A(&
zd)g{mwC}Q?{uQme?csF2JnUu)k$BqYQxMh1zM2hDU;B&n9`dt$v(V^o&!p0&0Q=`f
zkPNh6ABDer?5evMOOSoVDR9B|C#aAj#D14P4-#r`xep6rc3uS<!|mTuQY^xL{mK6Y
zjqR_!h3mD?9{vMbBkd!9g6y}?dkdDL>|cv;)uZk0R3sH+|Ltou#@d%s_%hDkN13m9
z`_HueJYe5XVWtFoZ8o@r_V2tQnP~r()<a45s(IiJ*^iJH$@X72!qLO_A)2!tN9+%1
zxpBgtr~#W|Fa1BjoU|Kh&yi{$qcX}g`_hj9bIRVOz?Dt6yU<D|!)~C@bey&qT?Tj7
ze#QzDnRas%^s?-%pP`p+KlcF|bL>H#fX=lCuEib6v$rmRy>s?$WG~-g7wiK)Z!c3p
zqrh(d68eSq#q@S5vggn@QZCpReT%+Q`~3<umf72XfioBFvzuYJ!fvFWN~OJ)mZnwq
zAbPrM?cRm3RA<j!0fozU$A3Vnw`a1UaLvAIDH^Za*?XbTV0YBjfHv9}R0Fih?s*F`
zH|)RA8G|;vgaNd6`^F5A4twTO^mW>A&>iWrzeTJ4n|94|=ylt_?SjD`d&A!#x9kH8
z;L~mUvQ$9#+A}EK*k>1K<HGjaYx^KFV1J?-WYGS$!wyS#?DCHRI%F@VLtn%8IbXrW
z5&JP(LEW|AUJgs6cK;uNcF+Dc?SaSaKTu@nzTHOq<8k|6WN^a1dlKY<okL}illDwn
zm`~X|sK#U3K1dZKGxm&cfii2qz6qSGOOYofZQNW2DIDnTGM`qsyIfMAM&oXmuj!*Z
zUM|)!81!~A{02oImm@-q!q-JY2@XG(BP)RI@6s}k3mo9`1YL_j7v4=Y?r|v^0$7lX
zm;%bdE|#s(3vo%I>~5$_BfS*ET>kK&pmDg%3$&7naPenCf3J%t)yeI1*+R?wNEdc1
zVD`IgrBeY>E>D^v67914D;SJ%G0_()VqM19gT%S~{2%PbyL?Nva0grp3V@RE|15n6
zSX9^Zw)fuMg<Z<R-g~#OfSRU>CdMSDsfj(Y#TZ*Ou|&;Jqlv}>iis{w6r`gf0#Zao
zkY1H8f*>LwRizhEP^?%{zIXEdpU1~>&Y5>+&e>benVEC7D>?_aPukVZ28pukqh$Cg
zJB16JiMCr`K|!n2b~iP^$J(_lL1&!ZQYF-!wYxEd5ysmE?E;rz_u*a4MWUStW!#eO
z#{UWPDR#ZKP?KsGcm;z=vtz;`l5RJ$2zImVe&9gP*-e-UXU^LVHUf}s_m2`>j@`q>
z(3xwONCl=p=GiGJWS(zV{}8$h?9S{)>qWbtgTNKr=_qtvV)uSAv|Y0MlGfs-c0vUJ
zWp+QfLEB|JXDSIOw_BixGgs`Y1O5E5s;i+0O|@P4Qn+@_&Oqz98at6Lq&hn{295Q0
zKUTxv2D`LvfH&H`Pe1*2yF;$vZrBao!EE2O+x0sno9%S70dKMMrSx^H-7x`No823_
zi`(s(PhqIT&Y9A(opz;_aH88zZJ;8>TXvQVNRJ&)B^$TxjOk*zW9Q9)>$RIf;nqI8
zzq4WRh21rpuGe-gry(+AH~SRKJKL|&LHB-pZ9f19?MEyH;E?_I^sM%__xuTx;r64i
zV-Di%A5+pJ$$kU{o6_v9b14y&WzT$#)@=JB+DzuzKg@*ELi>v}&|>@X*xpFX?Rgid
zxoID`9DR4}+l%1LWBXL9oOosb??w3Jvdcib&I7xyok5?^uJt7_7_=*$;&&0d#tfnH
z%r3_WaLK!_()ulX*B^tlS--fe)e`1Qcg+|F6IHuxs6?!8*Z2*P@!7ps2@}D)M;^um
zo!q_POQ=cSeR(4qGj{K7!?5#qyDx)JrMr)pp|5JU3+)+h?Eb<YB3-+CsK);G?&Vsz
z_Hg%wKVaec?mHg?H@G`jL7#$hcIc&enuo(YH?(>=tgpae{2j(n{qYfpr&J>q>|k&O
zKFT5Cb4bQG%$C8@SqF=5NG3Y;Pz*N3Vf|hhOm}#f9xxdW)!hJOI*3a2WjVN003g?)
zoE~#|4%S`pslXwMN;M3H4$;o&yx>sS1XASC@*4(v(V>=N<i!q?^dKb;`K>fT4zuV0
zTbYBt7r=6d&9tz%;@~kIjTH`e|AJ3f9U`e@snX#D-Qm>^-g6*w&Ecbw=&Ny<Pmz*Z
zhx}jRVZFm$TF*2X9M(}hq0!;!0A#K^tf2sFhr>;J=yp3C#-4we6n}~sq^F^S=?H~;
zb<CC%aHxS<wFLUFGefj)y2%`+ZA3G(QG`e<ld1yO&b+aJ`flc5H5&Vw@>GoH8RJSX
z0Y~=6efqEW+}Xk%P~*?8JjwlkYwC<o;mq5=C4zlt_!gLYcV-H_eQyG-D@PsJiod^l
z?SbB}M~y-6M8{8|eNrvu!X}@mgPPyCP>S+f*<8%jl-Q}zHnsE_G)xP-jh5*%?f^UE
z5{gR=(wVhO(J|{J5Ab)luL1mh*L4WZ9%BX-b2eQEcy4+={ylHEHzsGk@(x;lFru~X
zf<0fL{m0Z17}dgXTKWI<K^6X9^e7WDi(4q-vc!5MbS|}82A#`lC{^_HFZ6s^{^cMv
z7*>p#0p^!o5di$U?H2r6xsQeDst~HjTOD-(Eo(+)z|30yINH~(qtgNFz3I%$@A+Qn
z{U1j~LK_wi$G<oJMR}@!XT{_1{mjTd0Nj{ZN|GO7BIuGl$e2-Wsykzu39}xIp_|@a
zhnVJfp~I80c#OI5VzQzk<Hs}}0kDmE?;Je2&upEC#s`f2XONf7mlO_q#ROtyCf(1D
z{Sd^BmG_b*wm1)Sd64z~118+rom=3l2b(<rEr-}+6p`~}zoep4FLtTnDh!6O`)S(}
z%08iJ>}j@&o<lM0>oKr&hRtALDVEjFg|;~MaS}|NWfxE=BAy+68oCqMj5HWbWZ$?$
zB#CutgYIP3oz^rd>~HUYOJ&nrU^k83I2v3AyZawFlgUonLA%;4woeUh>6{S-!!kG(
z6~|<9j&y)Gi}QZ~XU=h<y=Xkot=k33Y_6GhO*vd3WoUA_(^P7j$C)I-L_W7~C$toB
zd#R$SklV}xcY%x0KuZz#)(-$&<ie;zwwS9wK>rm;2{+*b$Xw#GqoKQ$v)u-+jQi{(
zXuHhi2ynQZ>zD>|g)`PdX$99)4}({^_ol#7B^OOeuPW{ptvjl@b@O298fQNOfEuoy
zcD%LRlcSimI?k024%TxP3t^#wi(N_2zeeso61~nHp?vEN?in2vyU9IvglH2tiuT{l
zT+a6}(Zca`|Fv>QDAe1=wH|<_cFxQj@D8pd874Zp(Nd5uE^iB5>*h3+0l&qqzXqK>
zT$LPlZ*wuUgS*2GeFB|^Uasd5@O_-!YAC(Sb+1I{JuYhofc@MJ%3t2+cJBmvz?IPU
z?jaZdE+*j-w@-k-kGZ{nq45cqdJv8da91Ay_mr!r5Xv*|-6+_7&Q%?Q>KEK+12FiK
z+ns~PSKLP;v^W|hAFsk(I!SV_0+=L`Q@$u!@}3=(rbr^fz@<vQ{sf3LiKGo`(j}@!
zsL7DT^`kLUl70quvm}4e-C8NJr(3j2!qxy+ExA$*$!n4nigz_h8mOY8S)!!RU3E($
z0zhs_44<ojxFbng2AN(-$w&YXNaH9Bbx_(yRln|1Z#g{mlrEyzx|ejU7aF~#)3?JJ
zAL;T>;b<8CS5N@XNt0;Tb6#3}6C_(I(vO}aH7^D{S9*_@d3n;`7QsTk^s7XW0_j*o
z0qhn^_gw>9BpsxWR9uwKaYSRWbOjYwl}KCX0)I)mybgV((g}UATPB^i9Cj~D-6<m9
zB6~=~Zk6TD1Zk6{27|QA+};PgL$-%rKAo~C0i;V7*aASe?A}=VwPdM}X#Me2b_6dO
z>5yzO?Wi1$CT9TeWK?hsUN{>qqCM^*qsdJelc&+UUTE|(`j#B^HhNC0HeaK(|MI*>
z)l?7WZ<Jq%nLTVYzXe*37{$>0_^8oM3JwJtZHxpLZ1mP9kPsu2X8IIDs8J3*1x^|*
zr)XH3(dGh>bfe*$K{AX6sUk7cXm&bHuu(7-VrCm9PC{Rf(d*CPTCP#W6u6yd^eLTD
z$~Vfl26xHm!99>tBPrbuWk#OP09-a|{2GnrM&o;+rNXETKcPW-)hKT!M&Dp`jECQi
zM&Hvy_PSADDSWzN)Jf6NCZiXWFKRaGq=j&cQ9f0Yv>L_vKzF;*Zi+&882yrf#xA2t
zU(w}d^d~)GdW`ru0B#!zR8re(WKT={yGH8Ski2KKnARPJexq3eM&WGiyBh8vGq!jH
zV32Vyt(=b=pYVbCVB^YCC=D@=-VUEajkg3t%?aZIN`HnKA8ChVxN+Goh@3R8sDth(
z<Lgwwa>}@^9F5V&Cn%&4W9+;Y&YUrhd>2|`jpucPi!&J4&VlGzWB>1<Cf&I56L^tf
zJb{h}WEpRvm()4q+B_&dZ=6F1O|p&mlmU=y{1Lr?^NgRwpfBGzfp+)>#?@-fQ=zek
z0~(8r6DZks(ReDYkcy3$ZiTWE<5}OMuhjS~13;Ovq5MA7TsHoN4#{6J)+NJ4g>f;3
zdaoKg{08oh@yB$+q}TZNe?>^fS82a-&sdv=+3Pp{i9S1b-*_~=>K+>B(5?2!SXT<%
z6XWmc88%?tdKKIo<C*l18Zz#q2&SWao&=Ik@_GOL$0E*hUy4?`$d8&rjjMe5Zuque
zzMmetZt}W^=sO^fo)6$b`7CRU&{sa4D&zg+`+A`}Kz{TlaEIlci$RXc=k5hAP(FPs
zaEbD#v`tEqThkjaMczo8@l^S?MNpO|pX*`(n=bF6SVV@re=Ho%lxyi1$&ycRz|5SJ
zHy1$ky!>%L@Y(WUTE^tavvNRk<p=11XP$fq1q$-z!G8f>ApdF*fI|5kTGU^V^EvcW
z$j{Nv@uK`PJ%WqnhEJfnL_RKrN)a!~f1&7XsoayIe`WHQD<OJW{yklf<?`HlAXnsh
zl<~hRPpO4SrCjm?!>*D~Jq2ym@<OWdz9x^S@1EAk54)nVRvs=wvQFMimq5Mzy-tuu
zx&LBFUYDPyP4Nx+cTedk+D-WbDwJrFAM=63&GMsqm~WA<rQ=tv^7rXVXp>(|1+ZQI
zgto&S@=gadcFN~T@l$lkC(j1ymXGOx!CUgFt+3Q1ADsn}+w%8lL3Bs{%K}*NQ*0fC
zYyOJNQ2-oQB-4pqL$G4YQw%Lc(X<z13RP@=0urX!_$9Q3EBG_OM=A<_1v#mBY6M`E
z!kOysPAQJtqw%z2!*@^<qnJG$y3Z(T)`P?<qSiv^S;crd&6J>+yaCD*6>fA^_Pj#q
zfNR-`zESWg*PysX7Zf50ze8z>;^SH<tyDDAN~%gRtO)pOMcjWuBE=p00z{1>z#70>
zg*Fb_>J)J)n38%$*Ch<QL17UEyN!xMDxK_5ywwQOsj#F4V3*>}H{iMz^ESZVErl_?
zetQ&#DHPDWt*EYn-**(XF3{bl7)?hl?kZN(+UK5PD^=n3E1Kwyd0%m%5QBN3h@{hQ
z4;99AI^mI`lg^AkR*a#doF|GJZ|ELS1jIqvGetUOGoLGdr#hAw3M*O;zEqS`%<`3D
zx?v^gprVED=GO`(6^Xu4Xz9aGLyB|Dpxe>pJbl5%$>j47K%7n9qScCv$&Pj4TupwY
z?_%yZkw#&j+)S9$fFCgVJPh7@m_*a>ddMVeJQ_Vsex`Mew~2{8I3JUKb9nD-(i}+X
zE<clRXgBX~GU_382bffR5ALu@^*-Q3O}r`WaKhwEit&b-1Rn<pH~E*Iwvi@N+rXVP
z8A-o=l*!lg!L^&DP#ox)$wev-bu|5M4J4gR$ArV6v+4ih$a~Xe?GSM_O(~%L_kPnq
zzXQ<SH1<AZJWPM466QmuVZT7Br|DQHh<clLnn8_^=`hN|`k9uRLXE%a+(3vNHDyvT
z&w-{FKS$p&Q)UCa4>Ap=r&h3OJC%NgnC_&-d#LFyirSqptsD<Pxal4&(ol+M+9U-q
z(schfP<qnz31uEnnc9De#%R+n2Z)|F{rwAQi!n7D3zA|QMGxy#)5la3n`YWd5&d*i
zOM1Cwn9icIluXm~d63L9O`+o7^QPvw)1}#_BPku2XZn;5Fcg@|Xg^~pH2vQu*sV6*
zOeNdbO#93rT4P$i0G+j_-xh<bGj;zPYU)j8U!k$V^cX#M+Dr{}M5^61qX&H*rV}X*
z(`kBu>bJX1m#oA<@0iZ71?e?SxB<yN)2VSVf7dkB4<h$XYiLFBz+ifpirF8UhK|Gp
zKQirp3xj!TTE8CTnQ0^i8lIaLy#+NdOyf)8=u6Y}39$6a^ldYEF=)E=F3i6+O`?s3
zmsvm6k9wQUy$iUHS==iSU$aTypwZ9ln`RJyvxC{d1(-!w!2Dq|gFD?8N6aSj(0$ZQ
zN3~mlW)%eh9y5E=1}?~~fVMEl%}ynQ1e=YT2gwk#?G$`JVYa0Ql3`}!hJl2enbFfW
z!t5^X@gmJWErR4pGuK=UFv{#`9Z0m9X$2<XwAla!5Ms=x8umiX8MD(OTI0;t{D6U;
zHCsjtqIk0vyI?-SOgkAQ(QHg18k5XiY{4a)O@AMwNHP28GvHFqzNGKoq?vhi0G?sC
z_aw+c^Tl}}?&iNQhNOpi-rMlW-~2dzv*@__|30I!m~Z@%qPijGFFfICsQK{;K!lkm
zI>Xa&^CC)HMVObA!$hR{4$9-7H0Q!#KFU0XDnH}RwX_~fH~(@cNQSv96@X@%t4$%9
zWj^9<Xel>0rnu%6bAeWj73MV*N2oLZlirQ>=I81t{?TC0P~fD|d>bvjuABQ=Lgt3~
zD|(9DG(Ue79yXa@xecYw=3}T(y~TWA4Su{<^H*QOi#GEUe?qd|JYhb(?=YXX3Z%=N
zqtINpIsOxJJZ;T$vY@5M{9Our-!>n96o5zO?uioIe~-;SxQ@;z=JV;W-hlbsmq0u<
zH_QX~%-m@Reb3Do?g4pWUO?ffm*#7z4)m3I&p0#=nm?jA`)hLxO4z<JfBq7jqY_V1
zJa&}*zk@g{jp&`~q8y-_e^=$siI|!F$|Ik^3xk_-{1&hWl&U`=dQkb326%Vn6?zYO
zC^xJ`<00j)IhbHi<%>%&@1<lYz2~j8qs)hoa$_(WeU-s9rG84;BlP(z?}ni<Kq;KY
ztQ}FF`fpvNJhBNQfy!Z2&wNbzDZLGY49YF$Xg#hpq3unuGWIFB5M_V~42CMVw!!=f
z<sXzF3s+W9?Qw+i79IPFRNkk^%t>WIG5VsE+rLBKDdodYfQwd!SAd*WMnu8H8Kn`u
z_+pilM2N&G_s_&6oK+UC1{be1Oo)b>1m)HLUeU^LCc}#)rF8_9CM&N}6>W;rpLV#Z
zN;U1L(v-JaFs2M;=siegDw8RilcgMRfYNiyJI4Vyugn+?^V!O2>%iqGO=z)|t9+6V
zXG)Z<kD%<5(s?lerOHnYv_daax>0)mnliy1GBwIUI{j6vv|f$II%QcpwACwRl&5Y`
z4$p<%M&*otjOn^EG7W$m%IsulyQ#Dip{z+cj<%T1N<IXQEy~OcC~H+t+y`ZC%Joz}
z*RD*aYMf5xz0I`#>{6cGgQ0aRZ&4A)E#()^K=deoHigV>r4No(Nbe{eydl}EJWUVn
zKBYHZC3lrglK{A<d}f8le&sb=G~QQEcLv~ra@`F$^H`ZnN8p|)y)UD0Kv_l4gr~}G
zTA)8u&e=~{&F9J-S~9*+GA<bCOXZglKsZ@6?na}tMQ{Md>tb=v3*&XQ2;PD*xmm2C
z#m51Q+#BEyT6|0^DR+yA-|3RIFm^)UA&bC3;5;q1zJ*3F3oVsWd0R|Qf?XerjdV1`
z*Wx35H{T%jvv@QYmSQaDm|zsKmIYEMJ!^^G53UQ#`Brcy$?~^dFp*-p^BjO_mL;^~
z%dq@+94wu;9HLBZz2%imz&k8+CZn&@a_T8?U6ygbfa|s_`3dk_mPT&_-eWnEk`)gv
zkJEO_@W^t-hY)>gDW`13b4y=J_`a|VGy!>O=}l!`uPh(mfER<7@f3)7Z7EMg;~Pt6
z7VHjLPDz9|N7Wj-o}E<jzrvuiDvfF?TvYbo1K_E04S;GdmD}gg60FJ#M`MWUnm<N;
z!l0_4M|hZu?}ALYYRy;RB2;bfK=h<)+60;e)v!t+5>@Oe*gdCmq#Et>s)Y+-Fk3a{
zLx>cstZ8FVqB<BrSGVd8)o7QhN+~8@rgHoO<g#jg9B}2T+o`}^Q8m+VP@ytB{T+6%
zs%}$Mvr?7x0IgN3Hd^pjtLiDDdsFrD2YA|~8cDI4W)<@{EVZcCIswqCO7#TSri!VC
z7wxK98$mi$FJ5C1ovO%3z;&sro`dUFUFimQOO;BM;ytP+5%AlpX$DIC+))h<!cwnl
zS3U53s$o=abyt-(9y0e-i4%bDS2@nW&vjq5fIg$~Ky}*>xQD8$r5MvAl`$Q}d#nnj
zz~vLw+_}&)pz5NR=~LCGf55|MDy|wL&s8N?(Dy>6tB2%E)xv`me|e>PHwz{PRYT@z
zeXUyiFU&jg+bQtw#BX|rDRJgq2cXS`mko!cD<4`7kt2L?8FU}zXMGRd$9T_=p)82k
z{Q_JFKidMhP`>B{8c*;Zi{Nh<ulX0=hx6Z6f{WmnInbx@B6;OW`nCBg3V=lMrc@_#
zicg%5iHhcb90~ks{sEQ1#PE_{G@jwd%!5cQ|0|V9#PLQHUO3B-)q%wGI~-vmf$u#4
z6N&uSX^>3f2P9CP%>OzJT2lB-OL(8k&-#nv|7m=VBh;kx!>3_{8T<y?_Ga=qw2sW;
zozo$Dj*of^jpz9_Dd4jC?Nqsz!;hj`s9e68)~$K`-wpue^Er($QNS0_DXc>NK7DZN
z0v}6(^deqc0Qg1zZ7Luw=9P3l#!$kmNc0llITrX*{`Y#wl<`w3{&JZ={sdzx=RfiT
zcZFX*41E>+yc+;q<pZt&P|5eWLZph{KrgpyzDohgYrOUgh}7`wsC=T9|Me!!*YOL<
zZax2-85$e-E(t^$4g74X2e{7nYy-K$ucC83H~A`B2{rNclv8Nthk_y6!gtYlTlrgs
z7-1WqNgJAW{;3+09sK!);5vD)TM+5u7g)o!Zob?UeYf}#Q(&-%@24f(ZGNyEjdyr!
zS_|~@hJZATsgGYxQKY;4h|}=&9zS(H8vFT8mocXM{QNph_XGYCy~iH%-t-$h;-{Ek
zW*_t8L~u{|cPPa(z<)>|>Uhfg{|RTF@e9e)bAD$jEWO}gxr4mqc?!e4;?J&y<REWn
zSOolQ{;h0?zTq8WG2S75RS58oLd3@)PQu{@Xml2Kd&0bn@WEB6aTSixL7@GD(<S)p
zCK&GncR+|951$SSmujKYU07TSpFD(kJM<kAp3><APhoQd40#EDl=Al$mb)4t<0DLQ
zM5nKCpaz!wgg>Go<1Zv_g^K|~vN0S!EHu=BJ0ko;#{rKDGfo2#C=5}k@|f_FPU8m&
zC)_Yy$AuRM0S^}5yn;xG@ZpcJ6e`pu0Cz(8HUJ`FLith{3KwRbqpE@kA!9Da6e-wk
zhchRI3v|jLN|+Q3nNxzCN*beu)P(?^7OJQ$E=JfN3T<bE&+kDpR(SLUMB;>ZV?oXe
z&uM1kh5aJDND$VJg3d&tlk!SQ!n8GLOcpHfLL^04ipRP^nkqO=#0b-b)&JdwLOs25
zGKAX{7ta*-(5D}=gnJaDJSVK!3G?TL3Yws7VIUahbA%^$;Bp0#zG9OnbWlJbUs$~s
zq(CtF6@Wrv%Q{G25ZuOLo{EHtYcR5lg5)L48j6MKPr;T5pZp8NB_YWLh*II62Bb_l
zOEJUCLhE#pa-lv1b9qI0mktC}2<2y>^r}$54@0XICdWcsl~5i7u39)q_x&~D3tE!b
z2qmN7TCL#t1m^36)Hi6X7p86n*I*FN6hm91u*C`Fx*+Dm(hXt3SajYLJ{*FYCV`_$
zm}cP)J&RfdC#ooE6)sa4v`zR)0zkX)awfPAA!ix1bP9L<0PhlRQ|O^vm`AJrTY{DX
zpFP5eAn3d;#AKuIj$ruhLjZdPhO%>g!qMx{c2`*O6rJ}3dpe8KFN9sku<r|*6zhK=
zJlKKj>Y?!25{%-JAkT%;$HHD(AUqMw>CpFp@SF-uo(g?bKKo2aqL24H7yM{D^+J%*
zW%W|%{}$K9D`BBwGDHW3PdA|TwP0@rgKvbH`$2|;W0X&G6st|3#z_p}V9;6oIRlL@
zVrVYhb``ByNbVOSDJSA4ZldMy0dW&8q7RCTZ$Y)Ym`GQ(hp3_~;vrE+^<AD~1H}`(
z#EQwZ{`3|-R50%&_BR6IE4I*5)lYnF3Z?#H^?N`Bh>NM>^{_bR5r9X;u{8Nd#VHi2
z2^6J|L5_*<9)YDGF{%-`<D%jMB!fj6?Ycw6*9XxTDlVYlNW6HF&JiVu7iZC@fD*;?
z6Cjf$o}oZ-viJuDbyCE9O5Uc5+i1I;CYI0|F<q>sw_%2uW)DX*#q3<TmL>Y`gUC5C
z@D%Kx7eA&Nlx*=q5p?E=pXURYE1EtAAWwXof{Xd$1{Fww_}rPQ>I%h59!f8Wb!m_(
z5=;EST@=l0z!i(*DQ{9DK6HY^m&A#bmoF8)>0w_cmeKbBFN+7?hKX|VPuloh5l8$4
zT!kq48CtH2Rr6q}Qru2wLaM}4dYe^?hLv#bnpjHv14E5?;TaIM;<?SRR41;X;7q;v
zVH$Kdh~sG+*(gq@f}`tVCoMH^h@(zI@}{`x0*2irI&hF|78ldOrxsB=43e$l2a`eC
z#GhP2+QoH;VWC6(h%S##@#A0MT9;@^S7*0DWIlt;Epf#vus!0s%NW{iaq&WEyCV*q
z0_hd!P|TuFOnCy}U2%aW4BivR(;?=5aS|QbyDwf#gUADMU^vF~Q2Z$fjgQ1HD0Kc<
z^md2cC*syna0B8ywElc5{<8`q&qTwTPN;b<?*AC(Ux?mRE%8$PiNz$m5;smm<DfWf
zI7D8HGidSuMtt)gEDee6hv1B(+Hn<z=A=%^0OzbupjD-dny1~Mt9mc33iqqWMu2lu
zCoP8R1L{s%T^&^GJ7K|HJ=<^r2oH4^Jt7XNKS~DiRNK=P?4_1aPSRVwgx>c)Y7esO
ztA0Z<PCxa(bhh7LZAU*$fO>$^ABWYSKSkpa^+F2N9#scs!lyuWoEF?MbvuQ0gVejn
zVGzgFgL5$YV0Gq@0j(kG&*=#hs-Bk&gD2E)Z-h*kdXOUU;p#_?7)6BI^gD2o>LD-q
zds1!U3@@V80`0?2srOLbV6-|v4BTn;gPrJ$QMdgLz!|lX9u{KN;rl`2)NYxOJgc5W
zw@SQvq7UW&64ZYRU=!8GH()7AJ>w_flhq|(!<iIy#vCA0)t}lxBu)Li8s^j06ULx1
zL+wk~T&DWZ0yJi+Q_F!nr&jqw^1Qm8N`A7{|I)%FN4+}_=5y6fH0yclNxRXPuU`9#
z@_z;D1`31}s&|h7{({<wZkZyr&rxs})d?2RU93)!ps_@4{273k)ZRWATB*8}beE~8
zMqt)2tD7i8Qm%f~g}y8574!nCPzODM!K>;YN5iK|bw(K^tJL$Jps!jjdkoHSO?~cT
zn6FVg&jzVg|FIk<>eP|6fUH*!rv*lX`jrIEG^)4L4|838gMwx^)W!qw>884Q93-36
z%eMjEtiB!vOD*cSi7?TselrZXHg(E-@TpxLP5JW<^%won(y1P8hmmy|)B`tQqFenn
z?Q(9Z?|4I|M_nHV6Svh7^q9V*wxkaM_Nu*l(b%V+)B=&a>iM*lxToHJ5$5~Va*Cke
zS5NK-_dvajv^-RQGz&T(so$kF$YZsR_Sa9;wKJh*Kz(W$M4qY*`_IDfXX>I_u+P;8
z=z4si9z`c>UaF1e1Ncf^XA3oh>I-8a@>;#-BZ$0FR~!ZzQWq|Oh@)o55Ja3bi)qo~
zteGXkUl+}1x6$XS88rny9oB@>e)WiEaW?vnYMy<JzCg`5!+Ss+(@dR)&LEB56Odrd
zeIFn~G#gGrCRDSVB9|vLvDPpjrup|O?1pQ8{u5k;W~T=5NX=KBP<m1`a}V5((!8Ps
z>nY7)W8k7SS^q-IY0b0`Kw>m46ns9T84L#?R`bhf%6!LZ-nYQ-bXM~{#f#%LuW3n;
zplPC1MUp0L84$@D%S|9DntxiMG*uI;gQYZ$6RjH3HTD#*&Cq;v3qECP=1?p*OC!}n
z@|?zn;xFel4)npqY>ho_U2-&2-h$a&&Bl$Cf5_7;_z0c(8eC6!EoovYS5T;F>4wY&
zO*}OgX;yi`#6^vZ8B7#w3{-_%qEXqx{3Xo<dP0<HOsL|oOmlMwBrj|3(Au<Ivk9LY
zkzUax?Sjq<&E07*e^v8@%vWk=A(m^9R%vYfpsiZ-YZzLuX<lpwzDDz79Ykw2tHVI*
zG^P%)Td(=72__me_hv$}QBzJ?pX-_#v@yS-xlg0NsWGLbV3Q{HOZe2R`H&WeEt;#o
z(AlaH-lp3@<8>A~+clHM!6!q9CgoeuPL25|(AK3X-3w>BHIHbGc}sJ)35Xueo+LEh
z*0fUa>yE}H5!!k+ADhBbpXLsofW52HOa-~88Cwr!{hIN#8@#Xi)(r3mnj8V-p~fr+
z9zN2T`@^-znu-OOye9??djK;upy{W|h^Lz0W<d0rX0$b2e6De%qXaKB4~{|frRFBB
zzF%n;T0vw`6EqUqUTe&^L-LI#@gd+tn#UCoan#m?z(XhPs8QgYwF_xc>Y_bv2F_J`
zaUXE|wSQ9t!cA+qNp<K4w6iJuc~Co#s-E4o1ujtPq5Ykd9?~wNw3w&%FxB07X}_Yh
zr?>Vg<&1r_=H#}oc4h@c{IrH5!2Pw~uYyQ`b_PZ64{N7WI^c-5lqye-YTu^&Cs2E^
z7UY<Arr}E<g0wF_1OB+yI~kK0tbJgE5r$~v-UkWQ@;Yccp|zkZFigAlApqgp{dB@P
zLVMc;Y9h6p(}6pwjl2LZN;~Q{0H?HjW`T>=p4kfSv^M@ba535^Ht^|;cG!9}#%c{Q
z255`ZPN{{Zv)TcA55;SpXpxwpoqr!PiCUX6(4C}BTL+P3?bqh;B1OBh4cbz*e!rqG
zO?&SioJrT#tN=ViTVe!}OzjeTG-hdkssVRSo3jVxytc>{v!1Peei^tN?S@(O{>#<c
zZG*u)?Nl#JLcaDIrKt+E=OfWrsBI2{r3>1QaA+&mb|--=(SA&??^12gH!xVHox23C
zUDo=Z1Fl@Vfy(EvXgkKBuR^<%F3YRhw<)Ptsa?1eB30V$RES!wJ%&r&AibuIq-=hT
z*3Ai>wc0ra0M==jPJ_es+EyxaYS5N1g_=g~xW{O`u1%$51~;^xz8K6+?W9Q%Y1Z1(
zM~7Opwy$BSRr~pC_}iwPKL=d9wmu!IJG4K$K})B0+a(O5OY5SC7lv-_`uCyqme%0_
z{O-|?p;DyV+J;()-qB`LVyRba{{irQT7E0IyV_%^AosL?E{9~lHj>uV_qDMcL>_2^
zO40a8yO2&$Jl5`~1>h6yrbi$H+6#28J=JDWy!M%P%2oLL+@Kvxzsw8mG}@oM)CN0(
zd!<zb!Tg{$@+!F3TBjj6{6_ocIvR(x53p>II_fq)K%<i`_)`#P-T4j>7v1R<@WNFm
zzYN{`bz7(~&`mdzs{Rk?zRiKiL0vdKlH7IapFoR;&S2+>)<e319!!R(&iN=1UOHpS
z^n2?@(dPqvbQ%9`i*%>Y1L&u_co&WSx^P-&1n4}+!o$P54`>y8L|0!250C1)hQWNG
z&Xodc$8?p2;DU6wDARXb_b*kG1?wvA10JFqZa52vLv<$8@l&4AB~g+sO!qVG2*Py*
zv{j7Iy`BXwQfHU|^CxwCW`m2;xi)}1rQ1Pciq_>zA$eLC#$bYDbQgnQ_lz##b8xY`
zpDID(bjh^ZIjbxD2P2EurE(w%y7#0qbSCPm0_R@9!F{Jm@H9;){T$lTbw1yK%h0W-
zTtTMpQ@S0pbT-B?e@-`NFYKPz9SFc+vUT5NLQ9UWA`B*SbpsUs$<tj>VJ!K&-d$)c
z(8beoy-*ig0@W9Es!+^Rk*<ouMi+JZy&%Q9&kgD5EYa2N0J)@Fk^q@fo%ulwv`qIb
z8g?)1t{;LI<vOSHFn>iiaxS<EUCtheT-C+J!&0U0r%2$cbU)YtP_0W0g)`T5zW+dH
zjqZ2)C`PT$n}xwT-FAw`)axcWL$X2l_biG<HR`^l3hC=QUn-Zrp*vCrnVY)7iQt-a
zGw483vo6dGLu=7}DFxT6GqwS)O;<AwT)S@eN098$jq5{Wr*7UDINGJ#@)pc@>k{6^
zBs|nD%7#ymbPg2Gf2`X|sh}siq74)a9?(6Zr{+^#(=?E0x-eQ?KG$^>0{=ocy8+xw
zU2+%tUg;J`!P21acPh<!ts6$S_#54k2xyD9S|f*Kf|W5{vPo9UMq>~uR_{pBmulr4
z058(48nV!sZY3N-V}_L@ws;0<mQ^aPxz1ayrqYpYtNy<rlWVos0owAcwox)O-zrc>
zzo^wat?;7ID(VktyI@uN3Z%%YoN`AOt@sf5TWmEr0q{#!*5UL^S~(@anKG;K#t<pD
zI`laJSFE&EkgTv8vPGles#P2nNK{(=P0{iytGY>;p=zs!Omtqex<WzK8mr!!Fkfpm
zK)J;_D-$}xS8uh0>Vg}rCQ@po(JCtxjn}QTv^l$BWkCU^n^xsCu}xO5D9zezHT7>u
zwpbZa*tONFYB3ty3|6KpIMr?S`Vc(5Z8eHk=69@~SVFYds_7ie_gURt0X286+~}^l
zXXQ)b*M6(@-T>UUy1E>a53PP14sDODJX`^PY<24kkSA8to}qET>eEz+Jhjq%1oF(v
zNruMfRx6z8=e05{r)svBR>AS`;+56gbgd6snU}%DYb%c4YHzH<Ezvk+b>kc09raiG
zL7enI=+Wn_4|0Je7kwT@OkDMM>4mvpfBqpv-1J?Wp!0w}l**_N>VKr<oVz|=g|T?(
zcVB~rL;4hh4_ZC-<0+Bmr9VLHDsO!Wt$lp-0rdd->ZLoN)L%cb42=Q$f9S&-hxKlh
zRXC#mi;A?4>TM`L8>n~nfXFfZJ$iuz>A$`POUL!atD!Sk|2NfdhUix<2QF0q_zfga
z=nFoj1bUc$0fiOA^<UBJJ3@cS2*61F%LeF<(x*jYzE0_7i!k13y+EnD)B4|k#FWJ7
zr<{Rnv3gr76gaE5q^C!`-ib0giF&8sK$7%FDRq^sk4lBz6nzifDyjNCwCPUM8>*-l
zJwt!!5kxcfb(A~K(vLGo=Q+LP0K7P_7uP~*wtln^Jj~JmGahPk_2q}b<>|HWz{7m~
z{A*||&=2U)Sg4PsK*R+-KL^T+^v(Wo^rHU#AT$>1Z>uqg68#3cE-vZKvFP}pv{b)!
z9n_TR|DhO5xqj3j$QAu^FCZ%PF&tdGs^3c0*p>R76sE4ykEI&1YQ3@!jW6{@r=abC
z^+XEGyIc2AG}FU6&=Gxs)_+lz#&PSQz^SD;_vQID`eLm2#bZcktm~`M7i(=rTbDTN
z(^9BDYyE~E^6}QgzK7Wa>)bM^PPCr6nx@h^G7n~xt^cBhYKrx4I)R>QJ(6-LY1TD#
zkSN{y#fQ+DX>Gj>xGZb;Noc%aJ%e^NMb`fss7R#Jda(i8s;qy#3DIinPu9ThHR~6&
zW~#AX@++LFwGRItW2v)lehIGLx}M&94b~1ZfHzt%UkTiG>yiREbHmz#wA{2d-vXUY
z);6PnYqqZJ0ItP4DH4sX*8U@bYqMTBgSPPP)}<8h>9AJR!Tm1lLUZWuww{s=Z7w#C
zZlTfD=1Y3P@3;BsF96+aw$MqP5S#Je0~cyD?=-j*HWO)?9%gfc0%GAdUwsBH!Y1Uu
z46aRQ4;rIv;_1Z^Z8N?QS`uxFbX515WE1oV<4v}yqr-kFHf#6b@<_G0PO*kGn;(k6
zrQ2+q2S+n(QaoWP-)1Kz>I-b_ozPck6K4fdZnG^P{$8<(UjkBLlSZk<t2T2eMP6kS
zP){>zBc*L)jm>!toN2L{?@Q16R-01VinrO!qvSxl&BkA0sne!tIn;F7{7IkId17;m
z66a5C_R=BHXEtFCn3Cr<HJkAJys$Y&&*N7%o^){!+K7(mdu@|$0`85?i2o|tZBNh>
z)XDZ&s`PZWeKHGPxY)kq4%L>fwr@qCb-(S+7L4A__D*2?Wn7kP_rU!_wjLwksi*CO
zMu>RXo}LHY-nPM$!1>r_(HhOq_IvvFmcQ+-bo2$-_Wlo+4%^0E1MY||%D?a^vTYdy
z$w1puid`ME&0K@N<F-2mj3wB1>|6jsZHFS!cf$7Y1Zau2oiP8u&5G@sWw3O{Hi<5Q
zSlcEWkh8WgsD35E){*wPiMAC~q@QHFiPi_nw$uLygDJKPOrSK?RuzE8G~2a-h2<F1
z$yI=7+5Wl-<2+~kt0g3}ZBf;YXMt@MJ%NjD6Dt5Hu}!dnzn5$$)AP90HtQl9%WQw9
zpZ>D#WeFOu*tYxvEfuzY!RWhcTbYNxdfQ=iYc|-<JPOsVw%e&3qs>-h4PV-AOAJ%s
zXov0pnlbuL+eH-Z?XsQR3VgS1ClvzUvR(8S)b!Z4QMJ%*+Z0RS@7OMwjmBPEBPv1Y
zvz^xn$-B1W9pHuU@XsHxFoi#(UTuSw(G2B6KbU<4zPT_T(hcCs^qdCS&kP#=+vqZL
zN`XAUi2EROknueRusgGi-Xk8&pET=-nAJZ>hRK4NC|a4PGhc_p(+uWQ+QMftM=8IP
z#VlzA?i^!$4BUC<4pm-dGY$VhB!}@W0m)^)8-lVtCVdGU&S!FeqX<s{!{z}|$ZQw`
znF~ydJGdfdJDqmD$oNvizMLsuKWvz+hsmWUuqzwY0{ni~jLK!*Sl7pBJisQCvV&}N
z8aQ{>?MF<M2Yam=13knBQ&7{Bb(ji(7keNPlHTm4pDDuQ!$z85OulTTfbsgVImh9J
zKl@0d7$ys2<B`RX)v|rqJj>iTADZt&+}j8g$^1CYbm%_H^}GdtgSq=k1(f5@SHG6w
z?}^@2r!@I9Psn`ZMhoOAQ`4Y%i5pe4{BpPx?rrEXT!5&3JzazjKTst8Amd+xu^nO>
z>0@-6ObcCZ7Z^1@XY-$OA(IxgZ@4LR2zZF|FoHvllGfui0?8&bsP>c8&|&8Yqc7tC
zjWqJ4Y{N;Tjhmq_%IG=;%-WP+R6(RiX=k8Ax&6xJU!ikAxvC7JgUbG|!MRxcK>;BT
z3;rNP{4B~xL-#R@ox8w=S&Ur^$!LpEs^U0p(Kj4k#8^~P+WCw{H$}5!Ek35TYn;WB
z|6%B7Eml$dIo@I_)ukm^?4>&8M2iL92Fy;H#hA4a&9?A!1-W2xdIq$WSuCKKUX{i9
zMZjOTsCfaUH!M8kpysAUr8&4JixgX!Z?-5}4$^P2ZZ0J6TkN|8?tz6sXW<@N%%*(v
zBMbX@7<_Eu`T+*<#Nr3aoex;N{T5YNJ+){#2)oZL>g^%(!eUqu%)hj#p-S*q7Uqx9
zIB4;h;?J)woM_Ga#-ivJ07DjIM?klu<!V~1J6X!8dfC}>jvKfGmhw-b<)G#A-Qe6U
z7q|fDVJR7amP3}d3^+f_eiXzQr2du<R%4(6mTyzl%3({{8Q48yxvvG<qAah)(#%?p
zrB`^YWl$A>$(H#qVLr_=YBNTdZ8@<Il1-MT6VTUeIinY()si~_(q?JC9;DMUVjG6t
zWjWm%hF)0WI2+tnx$>}Q@KgoSlHE&nvmPW!wVW~%;VSE|;rD6P3Cdt5sMhrYpRUT?
z0!uk6hxzcSNVU=h_{*w2dh}JR$|)z@s2W2VkXF_A6fV4_I+YBOd#YzEVE2j2=MbEE
zrTXS1%@co%ZW4D?cu-QwgXbywafoM}p~jPMxegb-_{X$k@aB!_4duhnScPHx^465)
z@Z&c}L&TroN>#uC{M_+y`!Iis{;Pl^e8DK-j`CGApe&G=UjgnIA8{FtQT#%>*-!C4
zg#bkJhN3GpQ2s_c<}!x=mtq5Fc&9d~iRI1z2lwOn2Rua2@>bCx@qFP7h$QfXRL_&h
zJ5nq$iQiKI$z(o=w$mxR+iQ?iUh)zK)A{@Ukj&seX#y^jZ>B=wEZ&JS%jfub1Eny|
z^C#$4n$6Fp4R{V8K?BX@W2rJTk6%RF#C(40Isgm!-uEC`$ou*OcY(JmM`ICx_<i6m
z@{6eKs*3+K6hms@%m0Om7XFD70NwoR5%BOXA3()WkNMSftnd||``rrY9^|d-Ao`lm
z`4sp!{C9ci9OCzFfT*KzlD>E0DZD3#h?fu%0o~rhr3n!65tb!Dsjpx|)!}}^`}DvI
z5T25whlTvWku``~oNog>LQqPfI#L)G4(_C|d<eKG;qnYLo)SzN0EiY^gJJKqaGwq^
z#|VetKr&WXd;(mY5FHB(XN98in2~s4EmdSC2=Y~!gGAx!ZAc~wwOc`w1%HYkpBLOr
zFtBXlgrN=iJR!~+t@*-iBA123KR`{n;8qRu6+-<)0Iv!R<rNx)zn@`%je<zd+z=+5
zf!&+JTDm8@gm4{{bql^&p`l{o-<u#kLeV{l+!o%ajm8}zg~AoRLK4*i_X(4uX$5^(
zNT>JnJz>sfAo>N)2$t>(X<x#N2g1`xa1Vv)9kBaI$lC`skA+MMDh~*KivV~kjI+dS
zKNC_Xf_pCT3qf88li$GzUkb19!O>TO89f;Wg*)3|=(XT+0m|M8VbQc}8WMh>)vlv>
z?k519#HcXHIE!CX;k%3IOc$xE*prJsFVW8ijoxA%9eeQ+U(+!mUvbsn(B?13ucV(>
zygmTe4vR6v;ph=@Ep0g?#lI<Vby9prB2l7P1n!g=e|H$3Z_(o1qfmNUlz$6gjL6V0
zdPe+TJ%F*|*RgOvPCV?3zO!QeX^?pFVHKQ75Tm=`TB11k3$!JPId6eW7H5Y+Bvo{x
z{{|;bw7mr`UA#xH)C{rg1h`DG^uO4$xR!8+b7EmEJUuV=Qw%a&Y@$#1<cN*dXv`IB
z!{9}p=t0@`e6g5*(E@QB{SPCBqQ^&Qyddrz4nU=Nj0#h##H6k0yC!}W3tWxZ^Bx-O
z#dr}S4PqBf<vsD<2~1bNIR8D6R|YZ35uJnL>L!?fEv}yr6K_QRM>GzJ2b_R#R9~}z
zr%vi^E8xDf+VU3cx~Lg?nYyaS?}ows>SGk=b5sAg7<~uSAHD}=2i1O~p~YQ&WIx~@
z>RF-SJk?IL;PFyVl%dgEZ7^91ppUwg%EWxtJKjg9pL!;Jc*tM9p$>fk>TXI39aabI
z#+Z(%f1~yIQFUzqxIi`I45i1^I|={~QkTs~<8k#ryP!K*El}Y?jCwk)m(Hkbr=l@d
zeRMgvIJM<o{32)7D-HB5jCi%vIN%f2iu16Wq#mF^d9s?Jn<GVi;4-{ORnMo2+cfpl
zt03VYTK$9(rhGW^A2^fx;TMz|KKN1OVwh+g_u3dH+Q*G9fR@*vRZ}eC&1XZW(C9y5
z-Aa&S6H4QO3z~3OX@KtF2@!G7mNsE^JIr64P@#oP@dTgwkhwBp9^L6Z6XtyjZ82Y*
ztEAFm{MppygTFUV?1c6|Z%~%wueXii#TKV-{B6Ie2H;(S7u4@=sRY!K`RG%qbz-L6
z0O!o)g+l;eFbEj|HHVl>R4nMlq|?Il2y<@|bR1=de#2N#Fq=Z4C5)N=j7HAXG3bk7
z5?*1fXPEdKz{N7%YcN%D%*_c<n#%BWnmmnhq)Q`*G5QT$E_3&7kUZvTEpYiv-V$(#
zO&KV=e3@yhgVJ&)wh1P#Fo*NeS<hVj0NNUu-zf0d$b5YeCayD+523N0siPcB2a`1m
zq?2*J0C*Sk`^OkzH?z_OI&U!}-h$gb%++@E-DWi8?;Yk`H2NMgBOk%SBZfapOY+Ce
zAceV}F#l2^{s3dagL}<Heg(uEriKc?hM4>qc;Uz{r5CUhtD#y$XLeNsbi1%dR3+%j
z+EVamKkH80DmRv!4-*I2r^g|3kiAA(9(Q&s)zx~i$@EM;#Qrs%o`0U~W_l-hu|+*_
z*qePg7Q}}w_5<-{8|jJX$9_$X{_F>|I0#_PcxXG!E*cKqM_5M*M2@oGP`W>mHT?s9
z$Jl?Dz(f!mJq3;)XOnq|1hWyo@F|4#nTt6LWz!Hm!sk}mlraECv&Uo*J<SH>!I?yM
z<#7xqiLH+XBANZ*Aw*KxyC>0jo^|X&V>Wx3q7yl6z;x)&WncUbyLqf1#YRfl)vM5V
ziT(Q!Bum*ZD0EQ9TH67RRn8A^t(+~k1Hf>FEj$a|H`%{>0c>LLQ$)C#y}BI07IywD
z0NYv9J^;Je@!tT^%?5e^e~W#eihg?7FBZ`6%PyqD;dj`-=mpcueoH3=``F&A=yT*+
zcL8vKThBwpn`^X&g(KXHsb~x_aPEV!dy<>54kqHb)9<78EcbU5NIW-@uGs``>@0AJ
z+!adnC2^@m7;g@j(Fzl}+~(&nn8)>vglqZS?Rtn5a7+FR;BlR1Fki&o9S6Wg?t2PA
z6m!M&Yn5>6N8rpQ&fvKTx=Xpwt^;4o{Zt7rZgTE6P}9MEMwJYAxXc}Be88>01jI9r
zqom6lu6h{&ZW4_bygwlMZU}t`CA#V0+$G+0`rShkOgr*J61EdwcuMr&gF7afIRJly
zB>&QL<G94$a35-dB}?g~Lx|)#<$gjXvu8u*gv9PQ0K+BEXl5fMU6js>l#CC7nv;@w
zRGl9s`DP#bPDy5&VoIYW6L$cYA~|gVf6qzg{{>PYdG#%Px+Iwp3iwq?GhMQE677dD
z)FkP}^@sacqM{=IK1l}!_wPy?>Vdc?nREwSzr>FASNA2M+cE41lAoz2=AmTC762Ye
zru_i;8_9|v;Kh(+;|oYSO3P?_?<Ac-uT^J!dK#{|NX?@FaFxDC=XCc=e?NuMAHe@R
zO84JE=@ELPxl4ydK${1GG$4nt6$Qdmx{($<Ueej;V8UA}r`oPSX_XU1j!D&*!39a5
zg~G&f>Eqkb9W1p!L{lkU=KvBaRnlT6Ogi2SlHvGI{-7m7`j!(07%9Dr7==N4QaWZQ
zyor)B3aB|Hokv-~1nC(%agZpzO<}Sm>Bke%mn==?pe;qZoTB-u(ghTdPLn3a!*06t
zSP1;hlwP21R+dykJIHg=LzFB!FV(ieZnkv)cbJ(RX|EfU<w}?RhDJl4bo*aWb4j}7
z1q_x-^HP8)lLj_I=CU-_1*BZ6UI}tVI*}F^6;i`>h+LJrtio?tDee0V@M>vX1GHU}
zcE1f1HPUD*>Z+A;571aA9gzdBUTTv8c!QLi1%Df*A5zxjx<NX619acQJ`toxD$<wy
zZc7cc$i5>@&B9=MrILN<>ytVvp!=TmyP3fEOE39C^1jp%1Ca;P{17xglzw^@l8>Zb
z^fiYe>01UgI?8@=griO}CkmfB%kn*-+C{d12l`xPhMX^f-!C)wg^LGd%c)H0pzOVV
z=ysRceFM%zrn&~;A=y{sq1010atk;w8T$(EAD3|ws0o%GItMO9wgM|kX{gMdZo?C@
zP4mHp$ucO+94>RBbY+Ar$sHb^ly#qj>L}S5!yEigr(~Uf!+f+X_D9$~Ez6{gTa2vt
z4(9oc%)%SMSlJ57AYG6J&IX`JHi<GaS7iDEc;6zM){Dkg*>ySy_F8s}UQRJaH>q;*
zqEXITC@VJF=Z(fDqrP%9wi;db0KC`ecPqO89vZP(06sTzOoz4?MmE7TdSm`75FW;R
zDPw)u*y$|HhZ(!=g-Eh-ITZ-x7{5bB3m1)7YSGwaybVX*@fn8=LC|?XK5_;64$IAM
z0v;*1l);N6xf?~t)8&-{M9SpP-lgx-UX~Ah4B#Qf52k4KR;Z~&+DBnS*SfD_8f{tq
z6*lj~;Q$3g^~*;TBUVG(QN@^NaQnF8hyx^p75AyqBt-G52O=jFw*%l|m|~ta44zb6
z_68TFkW$S1lwyx3NQ`2of+~396sy*wGePmV2KZ!!zXu#nRirP0?li@u?dZ!;OgIV?
znTimq8pu*K(RFoBF`aJla>X+}NQGiYH721-kswE3jbd6dOw=j1(4w<JVP}9B*A?yb
z2yRli(nZ>?INJvigR{xd7jW3sge?K<W@1M1^n)hCpO|iMlLOlz>T7Z)0pzgBt&e~|
zYLa;$QxatIM-&W(n5@4~%R&4Rdv@dRCI6$W&(b^d@b|Kh=zQ_dDdX_(<slSkTCsQ#
z*k7*G<M-Eq|4z`Y9HKghRe6ChvD#-P%&u8G1do1m8;-x%TIuoky17)oy52qsBmMn3
zZCy7cQi9L!BYTY2{!2Q$zDw#04ZH2>qpS`mrbFjHZM4|hoAfdMz0aDm=7y|o__q@?
zmx5)^%*Gv*wRU0bwLp3?W9s0oH#4FEl0HnuSa80KTQEov!;OQ;ai-}fXb)x{AlNER
zWZt%eSDDNo6ll+9-YLMKF5z4q8Y`J8en$T{EkBOJKf>75T9^)JQwyOlg0-YHWhCos
zI09oQ+55HdG=|+i1FdJ+^gbv|U>oaTGm%wigG<8wj=psE;V^I+Y~D1GOg7OKB#Vut
z(#~9Vix&WS>~pFY&1ah_rgo7v*#h&$>}@KJDq$VUAX(17>kPA3*ww~#f~=aoL9fwk
ztUe#E*RTRDnrc}s;<eK2Z2!05Zm>#Ua5vc|s-J9Q#|?qBv%6^3(ZNpn0Ps%stN&KP
z?A>D6y~C~^0oA>%jW33MpS3JR;}cd#v7P}oo)Yv=*`VE&NqWUz9SOUR+;)1hJ(jo8
zG1dV^{v%3*;LjUoBt2t?m<2RDj_g`Gi0H)X9WfGTcGFwHy0E{e!kR1l)hUquEN6l~
zH}?Kpuy%lbe<$YSAR9v4Y<D&|9DN?_7z$q=Vh!Pq(B{dSPKQx1wt`-e-mDp|$9-6x
z6=Z_ge;>o!<7`JN`hwYnZ1kOGjeB6}47;Z0|AN}03GIWIe!CR1%Z|{^`}5i+z?Z`)
zu6s4<_$AB{+^=yR(6I7P3QVjr?4d;WY9Sli)(q_i;J46G@M!IJ%0aC=T>+)*%P1HB
zJ6jCE|2kvv?+xvrK*b+79D&-hbt;VQm`Lg9U1R9gxO*ji2f&qyqf-a_nI}}z?8cP+
zNMmA7ehYiP%*iVd_hV8F=J3d$$*=(;n7KiP$|20_cDNkMq~ybeFh>3t8Y7wa$;>Gx
zMhOzbEP8~-IA#Q`y%U(1aj;a$w3822Ob?Y&R5R*ISh~irRIgmaY~KW~k!hF=cr%kt
zd#Vn`=m@RWdl^d(odeADEC63JflZKk%?wc4))1363A&xw5${4x7<<SAjT!8p*f;%m
zafmH?{No&x^a(KMneL5nE1R)+1${ZpOda}inM^7V%wq&8MwQPbhe1&RQ$c&|GRCl3
z1rIJWE|-8WXPoHbxWdROqFKSrp~kCBhZ9I8lT4K(Rm^+}3Uo376rJi~mdyp%&2;xc
zOFzR?p65O@i{|(_lc7W33#N=B8_sN8CcJQAchFkim0e0_K)hHV!yZs?cI{Hw^<jU!
z2+?EggFuiVcFDJxTx^3HKu)r&sJ<bJy+rZrQ*6Y2Xp3f-{1@V5KcL5B5?lQ#aOc<s
zt#IZ%+mQ)N+3fawz;js3?Qo`;eeWh3OW3)zE4;++TTk!bQr74gfYodmMZ>SLQB+`C
z!=9o?UM>3$Ex()DiYw@AVV6atua&(?S85x(U=V%nYzOUxdfBB5(bvbW63};-ZKm+h
zJ=SayNI$!jwqEzyfOjDBfPG5Iu7~W7f9U>y#3l#AsmH8C9)M5S?A_o7*e6ue{glnv
z4cDHr-_U=h^PF9<2}66qo;wN2muzVTxL0gFm8}l4_gBN2*X)dN^m%f1Z2%nSYH67j
z!ClylvBYp6kTc2LyrUq++=$gw!FZiJNHLLn+)H{)I7xok0;QpnA=>vQO02$uGX)YE
zZR9E?_y7AstR#6Sv^|#mvmNA><d2m9djwQT(`b8q17FYrwgvYs6t>|%NW;)OrI|s{
zbPJ!#hDfjUKs9XkOQ#uVyZK1^&<mo^q?><*(=VkV?}8hWes2U(SJ@9=4a30jNBFA>
zdVda}&FG3#jp+O}Sq?R;*3-IrO+W@@{_xn00dEQt@%PR>v`w%}q@rT`69RPZ^8W%T
zN9G->A#q}w9I1lTow-Zp&K}Hais<+=fqz4P0CTknjlqm#JGc<WZzcMonB6RZr<m=g
zFdNS(7r^-hMl~9eiOdm-p=2^!9>AF_#+lxf=a_en0DhkN>owrn%+@CW<S@4=hLX$t
zFN3~dk;nY)0GWKI_YF-oGr9z%khwvtf(wk)7Nm%oxdgf|GJk#xd@<uhOS=;06-Dwc
zG3gs2Qp%h@45ekv=x;$TGquA&%9+3Sz|kwrV!DVbm<Y<-US;l4=BtvKa{)L*72|mw
zt<{V~3HBNzYlJg5m`s06-A#sDi1}(_KA;biH8T;kN^W7Yy5L1CGw~EedYJXYq5C#t
zyA~pMn2!Pg?`4uHI@rg&^(R!{Wt4Qv_8#*N2d<yVq=!Tj+p`ABG7Rk3^dQM%H&b=O
zd3F+o*K^n({UBPvGD|SCMQqI)45oxNZle*h^AUo>yStwPu9a-)ZHUyctJeW=gVno2
zq?0{QpEq{oZf%gG6@NsI#u~yt+X)iNx}68~1p6Tr8SqTa%7=6~+dLJfBiN*W;7BA}
z>jvCOwzm}CMX`S}uz8A|g0~%>I+|Iqa+)2r0k|0UMKu6tSW9{k$Fd*BLo$wyl|%9@
zYfV9lc=p^`NG7oUv>Z%iKcFv9C$W9r;0(#^UORNAuvtU!Et6gOGq?iQCJbr{*~iPF
zw2bX^K;LDykPg_FvwbZPxx#LnjybMl8&K>at!Ee0>brrhPXyP<rWFC##+ppSK-*c4
zw%Z+S6a{lIIlDl**g5|I&~0Ex(5H%Su~~ls*uxIL0;g`X0n6ax9X4$<)bz4>6f5py
zx0pcNUDk;n()ZYxA40O9T|{TM?z5w#K%TK$THZcqHFTWx1v@zamR_>sDVp*MS$H%K
zveSzp`I;@B1oDP8Z1Y8@8~1@N=Ia3W^*AW?;U?0<%a>b7vEpOgIt@gEIHNXj5!~k#
z+lk~d)&UU9{TT|M;y4ZEt5P{T%Dkj;A9q7ChdWBer@34^EoO?jY^s4P;l84}rc2z5
zBap1(HX5{`)!Z41P+jBRRKlqm&X1m?wOmFm`f!kf4*1q{f<Npwa2x1r5RIHS{XW+@
z!@m%@!5#e$&fMfC4Z&a&xAzYEnz>KhL0Y&+6EIz^oP=KLZJdN|>vk@U?)5J2%VY|1
zcXR*Hrt%gSSOD`q+||h#Z!hOb3#2}7><e&rIfn{J-s7rI0oczyxC8Q#t62*2i1Szl
z-H*9LVUT>yt#pMKj*`En060m?=wPF>L|hHxB6+d{eXf#4BO$q8G9sSdKL;ghGgxw$
z%$tL$@s#BEz!@(|D^=opOSF`9@R0=A!IH1!`rqg~BUwZ>*{Kp`HUK%2+-yi*l+?vQ
z<ch>M35|V{*xmH|O1azc;-GBtaEN%yUi1U*Ei=o7$Whsr=3%)1j?1Pdp*2{R<pN6~
zvb_|R43!<G<7_8nfAm0Uxa=z)4oAvzrl2uOcE}7$qh-5>(0E4Xx*v_PvM-cS8Yj!A
z5b0Uj$adi3Wjl&7>_k}=Z90-<9nB!gGUeX?TUiVBztQ~vT=ojk<poACykflqN`Kk<
zGra#bnod5i%$o_BRcW*F_y20?{KSSrip_5H-->_#kxnIX+dugX@;id4^kQcmtrYAE
z>C061Uv^<kyEf3s{+T=kc~{0-OLNZ{F2R}?V<`EBri7Vk3N=2=qLU!LOjQTG_hXnr
zTslEa482E>GkfR`4`w{+i4?;4cF{C3_b9=Y#JtRfwM=G~GnC~rd9;EqV%q5VcNybO
z`>#qS{sT-?9rI2)e7wp0FdJM4Gv3e%Z~B;|ZnQpS6f^~n?2hp;=*Lc23~dqYQw0A1
z|NA#mj|N|+(h++7m|bH44PuI@Ztpk~HyJJmGpi^?9Kx*q0+1-i?h{C!VkXe*C!RS(
zXLA#n?_&VK=8@KeNe1RuN>5}lP2Yh%$GlpK2{_OAccHO}@uP(3MP?kOP_Hnh^v0-Q
z*67e!&je7Qt${iFHMF%d+s=Y(V>+o8s+~DNbp;)aKcxWT*faDkkF%^1-81p5|1^v|
zfjv?N$wb!h;1Sp)_7D0RR5E+j7$k)q{tt#$&hDUPeJh*)4h)8I5tLpH=eDjxUj#R$
z5+)+KYzge1<e0ITxG3%eI?Qp3Gadz8G-pd!@@a0?c8J7qmuX7QaGCqyOe|;e4qWq*
ztTK#7r>~@{7{pJ~FT#Ys<cu8#8X(E1NakTlcQSlBBI%$+-BC#%77fxsNi@|SACtI;
zfeVtnMOE*|CAL4oZm{Gqtupq@p3kMx%YwGSZi4Lp^>!t0Q5;#kt9qsp5FPKq>=#jE
z1YH?s&;h&=QIPu<A>uHOiW!-KVZ?RAhelm6tGn@F%UjgVw;q@nHBJ(hpfTQn=x)q<
zMLdYaD560Dul+sN{S&ec{r&pAdRNug-BtCf8s=+39Z<$l=X*#Qu7SdrO4^HJ)Z&Oz
z^EqTH6$ed`s+6uyh#pt8Js|p2*(e~o!fiC|*sgHvq6PDmTm2zWXWiTi5yijU`i*`w
z0&L{XG(CF2Ki!YGn)x2;&0F|M%1pHJqm*VUkxRdq;SIk%&rGKMHDQN#p-G}f^?~!~
z?`q*YrjgbwV%=#n6L)DB+9ZBwKKKd8=?^C*PWS}M8AZ`Bn)y=;O5fW{Ykbq^HsCsI
z)pqb_Y@CPyOb6niHFw4^T)*#0Yx|DcG{j%9dMji;=#4RGvAW1J7;4K{NgtH|iJd=z
zq7tU2-7clfou*sMSsg9rRItD!Fm#Z;rUj<2nc*CqR<U;})pC;USP$lTc9)XK7uf<A
zLdR@xJmS5<es=}bUG}jXs9%`>I8?NS9X<iQm&L5X3x!MgWM3#Q=d-ik3|V?!%|Yzp
zJ$j%eCWX^CcTV)J=wsO_+NayfqWxgzIXh0D2)<xj_CWnL8@nDcE#fO8z+A$w(K6Li
z-s2Q3mGD6e;i!~1U5CgTzI-nXujR#7caVE|a5l)J{Ht4U#@e-fbs0E6@DVFv<KJ9U
z4~tj$CE6l+mG7Wg{WX4rlEn?YYz!oS;$=fX{miG=Ag=qoqGK-uH`3&}iCbPFgf>1r
z3N>iw(<ul0k^Hcg<{y8NYbg7<T0U(@CD+O$X&-!<JaW{Vmvpb!;V6E>98OsJm0hPn
zZwnh(1fNgY!&R{RjIE&@O)L9*5SUB&LsLh!U(n6Df{!%9>`I<RquesS^a#}d#v5qn
zB=|Q!P-1W^e^LVda(<tNtK0aqKfu#=UegHC-MoJg-0$Jr4A7|HsT&abK_1c$Phar<
zG!j0_zokB-l8<SHr<2^9Hb9)>VTEX;THfh3s0;joCnT@%79U7n<>%;|&ue`1EL#7#
z&i!bLe}kW=@AZG={ZpWLlkcXzmi7F-f5QDO{)+aC-{zZUp=yu$Ia=L&!sk~3kX|UF
zCgI&SLGLLq?+s=vKWu|!JD*sHnmy-tZi8APzcm`cER`SigGjj?hWr}xuksw)t@e%F
zm(m26<srYq+K=*r2FN^+18I)eB6}yG?4^9-EF_ny3d#|TQ1zSuqkB~QBSBTF4$`=;
zR#n}Auy3no?||ep)jbW2{aJm5URq`9^LIdPRJ;8ZF>O~5os8-h?^F+SfV)YtQr2XP
z5=?35t%{m*_vMPM9WAp<*$@fl9%VpZ0Qz=%_kF4ucSG-UMN6wyhm?SHMB!4_WkcaB
zrDi#zIIL{eLg9$=h?3Wp%AGrKSf$(u2lJSc+ZpQL7ApsPL;r;GvKth?Q*voF^Nf;o
z1RB-K9Lj;#D4jA8Os!J!0rW2^8@9Z8+fA<Bf)<a+r>S}5ed=YWWXe#Fs*VRI`s<Gn
zL(C|8fMcg&aaSD|^8lss+G=Pelzj%%i4Tikp=FZ(@eFlOb`F8ll;cBSD79B9qDnh+
z5!X}GmO(WA`30Dm=C==$8Db7hXC~Z5>GaXvVIiwk4L373H-ckIrm0JI(LzX?6X@%#
znK5@^!GZ-Q3}JfFIAC^UIj-k)@Awa3Ig%$t=e7-p(ECr<pxByD_tHGu8t`+Y1UR-4
zli|jG_%>Q8uX-ii=eITE+R^L_e&L7lxc=i9BSKuvPESBRO4;rZ*r;N-<0T0jMkQJL
z440fe@8Tsf9AGm^JZfd*f_0&GyEVsbD#)?rI&?|NF@c6KXSOABVz|G_Zr6p`atkcE
z1rA-f*_vZ_Saf!)b9N3S#kh7B?laG1wmFQ$v-JM-V+b$=288GX^+tnHS75VQ9iq97
z_4_~g=p!22nd!H7w5y%HJw7MbY<14GNWXo<^>)?2U_}k$Nr|ebke9085>-0cQv`ji
z_Hvcp=B6fLS9Mm2JUvD<iOFGEq0xykp+f)4-Mb{>l8jS@Q;k!>>4vkDE8>#-gMA`+
zpwd-bIO?WykGDB|d<}*aKUc(3kG@Hw(!En}u`0xCu<Mh{9;ee?WqQv^;gfVJ4okj6
zXEx<qZ4TW;o7p+9<DN)NOODVv>?X4%tH5HKrwa>>9TsNFpP3b7o9VP#vXX4G3JOj6
z7TrWkwsW@Y%6!kdXWb)`!n0CCqf^3tf&)5^6xZ(D&UI&9Uxs*nKT7mE;I0uj&ncdw
z=(2~eNX_)<A-dd9JY093UU3V(L-dAWdSgI<pO0SeALy_5!98aP2+|u|agV&X#z$|?
zHW^Jbji!KrpkTeh6foQn6l^w_N0{~52BR@(SzecAd0oHA)5znBE9sd)$Bq}J#JfmR
z4q-P*dQI3%lJHHN#QR9nAVP0RN+86dnw7AhByA!bAW1I5L6UTl&{vXvCLAhB*q1DE
ze@Visn#A>zR6&S0Jw7Ctcn}`SNA9kt<1`mN*bH%IiYAV&6W&ppI9}!Mnj57V%a}&&
ziUwON+6a6^WQ?YXjTa%Ypd!TbSWO|n=OuWYCYCJ_331>`VjF<((}>65@|$mq3Gu*t
z{l#h^Ow`9iYO2sD02YbG1U{nfzf}K3Qhi6{Cqgt>90Q5Sx+QgpngD#~V6i_5_V)P-
zo(v&hk&ukibz&QVuV@DF@@g?5rNh~(6p*LA#4RF&g+3Kzt5$rN3UZF9BeH6c7?9Rs
zDK8D=&B5Y0NM7zIx=#grkuXgK``+)xej*nLmJUZ+kwCCWYy<FnLE>>b3bi718n||`
zia-+e1nY!815hd!XK049v0`tAW+2+NE<-aIsVOe45ih~vJDbFSOwGIemnJa<2(`RS
g&0y4iJ;7RWjNl#72+-~vuaVASUiQC(-llZ?2g&tQ!~g&Q

delta 127683
zcmZ6z2V51$_cng_a_`-Gd)36)5@WBiCdM9(Jw{DT>?XFTi7hc2bHNS*BB-dS6afJ#
z(ky@=s90z!ML<LZQL2KX*nOYF_xJt3zxU5acXrO4=Q(F)cV}nL%-&1qMua4c@My;r
zMz?QZ?H4}?vNmzAIoYxtMkdMr-#-PT3hW`unCeXqGKX%qp(s@_oNp^$rjRS0);q|U
zc~QK~VQ{M-s6@^>USVVkh4TA1oQxUb!O9$_v|3Fi3ifSZxlF++Z^xsg)kdYvVOgu)
zR5F@lz4KU^QK4M6Y8@#yD4^loT9hel#y-#x{cvC&wH9QGPfZi(ys#cddYgWw!t*2u
z^~&Sgk5l#&Wf{yh2o&tYNKuyAa?VNLPm^V}oJ!KDX|n8=QyuHl$jNeA&P{ClTcYen
z%ehTv)_V=*t#jsP@G_a@`!UmHu*E4tY8V+uwP!!y$;f1KH>Co{_?4`Tkt;jOWpa7w
z7POFzIol38-5nM|=|B2?Pm;dnDu?42_t2CwW~)~;Z)q)-s37Y72>#3OS8$+ETxE#j
zAFum-D|@?FO4*P{z{-@Kw^-R%E%j3VyM&j09S$L<Jg5?6!$~SBdmdBBM$)NH**#Dt
z8%?JsWm8X4_6=FLDI<@HvT-E+SjN0P>LBCB%j>9M>_2GhrIyKZSaCqHtd-+^QO4H@
z=QYT*P8CI&U{<I;O7q$&46_sWX?YiFa{1nM4(qcSWQX{*WY^00)F~?2Q83A5<M5w3
zVgjQBVUEgs{BO)r`LO5~%o-VAQKyt`Yr%|e!HoMaX50U3XPf-X^UGU6f5`aBe~Yq(
zEuddoKyLp9EtL2A--Z^-M`X8PmbO`=l*tC*98E4`R?8h^pUfZ3%a~4bBVA7VbHsn<
z$Q7cJ26{z_ZAQQRnvvP$0x{B`4gZ-VZCMxKo-zL)u5*i6n7BtJd-Q*$?fxUZ?xmB=
z)}c|X?8^VYteuC~S5oVrx3*Tuq8W3`O||zgnYR9^QnshXB~uH<4%}xB=f;t6;Q!Q3
zru}=oLiX?fQabrxrGNjgQv1bT(UQf!Xug9?$w>c&>iYk}%JTkO=OZm9I-qS-R`{6L
z=RayIRCLwy#{MU_R7Dp$Z`OaBa=xBCF8Hs%I?sPpvcv!73u)n_wr=4&-1B^2NaTC}
zLwI=f|0X;<^M4Z_`7dFI^RXM$sSY#yO+gpYMr47PIe5t>rRmm>Dw)GatkRNr7>`LC
z)qje%G0Oj(1T$)7yGc#Z>7a4owMt=UYdnyWgHp9efgXy}DJ?l&z4qw)Fo9mFdK<IC
zt61Mwn!gYIjKc}WqHNpNOKDiewD($P7|8VW3ODq&H_yYf-@>j?&UJi&enp0=DP_yw
zDRFGn@i@LJR^fP|iouafCWX~M%W-V?Qo!-#Ytk>QCY|x`s5Cl<up|GW((4OIt_b9C
z{5VC#@$+OlW-p`T?{;4T_^hDgiYgKr_R{%JUlU;4ZCqH{jZl(%?jkzvL^8HcP6i6T
zq|%{-NTPjD4$VlWWB=i#zbc3rX2lb#wiRhI4J6sJn9d)ar1MK7?F4>kC0O<Xf?aYa
z^DcSh^`+-zX47p_HGCk=yx&N&eFJIc4W;(Dkwz^PxQiIp6_IA{b<)v&MUtrDbiOWw
zOm_N%^heha|Igj1bi*-)9m(^aB=TBBN=4{gl(PB(WZwP_(H(wHhMhODI9j*SadSOM
z6dg$O(0bDGx<yVjU!&4KXNc!=H<CC#rqVuR=)7<pwZ!{VWUJ#{;$JpRl-ZTCw+pEF
z(~hM2P)o;|M@e;ROFcp+6W!HbRFD2ssRrlq)=<iV{Yieanq1kHOZsilZR3);l3PnI
zlU%GM9p{eJT3sj5F|nE?yI0bAxejc0*~{w$m~A7E9@mhWVJ&S?m`zIQ$66Y>r6qdN
zV=kNNLXwY{QC+X^Ajy+>(wrVd4D+Uv6LqIZa&HW|HKdLtKeXIoZI94-_uj-%iw6~L
zJS>1HGER`;{axvNS~ntc<*6k$wKVVZ-|76H>2%C%AkCr{`R6T;zPA$HXe}8Ve1$4g
zmPzM{ndD+aOEvnvC7lzq$b6-itaMHyo>aR#sZNik;`;?;;F&l1)jo%g^=HYI87&V|
zyJk8c)0Q;f7t#4WFVea1PG-UkWH{movBfN<((ii_TV*7bjt{4+-uG)V+3g{jzut2B
zJS00QRZS(L;yrYJWiB0Gwk4(R-gI27p`&9I=`2j3(xy-8e92NGEo-@L+qKjwU_Kdk
zb0H^2&Lv|T*O6p;TSBeWk;J5?(y1E>J7=6o_kU9ZWv*A#HQRtel~Q)BicBu(Lg(%b
z0lF?CqUc<bU#cKYu0?-Qi{Zv<(%EAtd8-mK^QaHidnbl{=u55<YDF2fTpJfEo%I<p
ze|la;_kXaOYV+EG!24b4y#F;aR)4p})0WQX$0u~&jwOnf8>y+gwKV(8LOS<EFRYZU
z%_1znpEP&=Oy|)JR9X>8CcB$SetbJwvHV5y1E0c*U6$2IH%0w45_K`ramH+-TjWGX
zUoQguq$hdoc{0DN<yzk9NA;UiPxW}cnHavZlH}+QB<bWr=6^pxl7Ib4;^9h8w7EeQ
z(+I>Yi=$HeVHFjxyG#b2Po-no7*fh=abkKZnasXVI!kxcvHv}y=ERm3Iz)z-s_DGF
zmK<GoktBZ?()pwa!g_LaeBVswM`qITg(H=&T0!lRZNEyHiZr?dk|&euo@wNldIymn
zYC}q6T68YiN$0EQB%d;zYA|kPOOyK1@g>HdxQANaUdJ(%RLXKHN&iL)ne5Y%P>vg@
zdQI0!p3`y%ywcdoWS$c_@uV#&Wwobc&*4N@KZfc$Y9_%J{X+7S-3Xk$nn)jxCy6kd
zj#Hl!Puc-GSF9n_XERB2TN+{84<Q%ty`u94{mIsnf2ab<o+`Tkf0<2<cKstV`Sp4_
zk8W|R55~Zde@R4+j%1+II0Dbfp!1i<$=Hy!ggV-e<lQ64fa5?qMo6UdSqL46e@n-H
z5v2Lo0AlmIOXjzj<#hkQ#E=%XY<UPBHc|1>mRD-ccT~%WH{`^>v#Ci#>j}2MrGM;S
zNoF1%CejWO#1J1r`rfChuI5B4?Vmt~hk26x$G60j_MnCTEuj_-1gBm0`C<YrUrT_2
zKNDc|Z~}OoB0!g|bbh3kj>l!B`S(I{;>lGay7^N}T^EvbH$D*QhuMT$v4SLL-3aA?
z83L|4hU=(t0v&x@lRUKL&0>H5FA+5iBI@tX)3M`jGT?NE<R>T5dFJm_KOaW|@7vsB
zcpgziE+Oh>EuFhytgezhFq355KsxWCRp5AKC5NK|mrNx)euCVp@^HZUx<~=Xa=V5_
zviv)$clZ5NgM1GHWcDReA)gHY*m58IT_uNnRuSDFEAq(+`3u5cdrYLQS~}W&Rdl{w
zO~+yxX$G2!c>+(G!<SNJip|8i9y2ec%$93cp`fIc0A1_IfJc8)&HIUbd_IZ1Hg_RU
zRbP^3XD@1@XH`m^yA32A{V_WFEuah0BY_M^3&}v|*3?>#=)_bq?JAN7d_mZ8Ryt0^
zphhM0EpNI1HMpx)vP&2=s$}0xB$Ee^5NrziXO%28m)!cgAJuqP%YE?bI8iHSQ_bWp
z_k7@9YW9o}kqTtWRzLoNx_8=&8H2K`*K)M#sPlj0e7f2f6`c|G45c%>IpX{WdzCYw
zKmIub{?A(43cmgH72S%9;vE57l2e7!KW@_%{>zPqnD+4>L$a0e8wu;K%!za)2N)(A
zLT`q93?~mVPc9;Nh$&o$<S;X&8ZaN`*O@SSl(}0AtH&6xerO|KW<?-9=zh$YkudDf
zJjsV@0FyZnz8+^D(z_y%Y2+acVs>-j4rWRmk(^)-(Q7Y+**G3-p-lVU;0|M&Mgee=
zsrw6_hclxefjWZun|kd?W?>>YqnLI{5T0V*wm~kMS$Ce=KZfbM3;0;ZNkCy7GsPX;
z@yxSw*gef`&_j5J`S>F2o@Iu*gY6vCH3Yc?W@jqQCo<cP1D?b<hC+Cr(Pbb>W@a6N
zGbzmJH(<HII8aBF%6Nr9GmS~aoJ@I<`94C1{^us66;XJLnKlS^bD3*Dp|SIr3NLWy
zGvm(#QNSEYM0*u61AYK^F;jRE_&dxL>eosb$8JdOGs|jWu!4!#fu)l9bQb`RnCbK~
zsbXICMf=t<ApyYEGnQ8nK4HpeByMkD(q5uYjm)rLA$`gmZ$|QrsVRfqCT80?ls#v9
zj)d?9vve8|&5W!bxtGkM&*125=2im?zG3=3M@8Q<sb^94ftf<r*GWFL9m=-I^<MCB
zx14<^z&`$UT1B167rx`D|6S!qW1-)B#KO`a@^4{w_1xcZzUIy_Obbc9!?G^W=r#Wj
zRIvB$!#MWw#ynry_edKU>-V1ST|Z_dW;!kEijWSdt!ijTD6(E{K*&uGgM>e;#B`bn
z+h3tqb7$Xg(f+EfOyWBbY-8Ne$E$WRnF*+tGjsM6bVDx86vRlByBP<}pH;`0UO$1&
zm#Mi6m1gGE2)Ol*nUsRMZkKa(*Sg4EM#K00@?JC;IwXJXgPgCt$sP8h<hOnSE=4|O
z8*mx&d(SZK#QR64)Vi)jL2JL2&}!dy8t8g8?SOn}UpX|t-_{TQt*rk8M_0z*0WJhH
z&c8x8iMg~9mCR;F#G(gjV%)s{rwN3zA3>-)i`RgvTaTOQYr0>->p|6{XfryKp1U?8
z64i@BaVmT7%E72wA5#VToxWo@v{S#mcj5FGs>5j9{sX4Nj{%t%;K#u2VYr%uij#31
z96=+KAq%d-{HRgrXq4kk-f(Q%DSAoFx!DmqOSg{%&+4GhQMzHS0dglszZ;d?#ccT<
z++K{^3&BYJ#%6l91DMa0NFtc;y{2|B*<1WgU|JkbWLi8<Vp?22&ybs{G^WM#iwwEm
za#;o8HEL~E<>T0DA{qZ^eK6c?zwk6%`^^1cG~nmnZP0K%qG#aPr+F`c{kkGnrW|bg
z4aSGMW<oOT#WEU~k1qTP&VK7ilcLEt7|?y6`Y%F9bj7Umvq0H~?T+(~`Tby|i|lV4
z`?u-=<HN*s$iJ<mx#ss*=rMC-KB!>PiOJdvo-It~9OMo%F)zS<h*`S>o*ibI=sh05
z#QY5k`*BA96u>~{6uko@nQ8(?F*_Sz_Y_ksLFX)^cmVu4=HD=ACNSMb!s;c)@D~7=
znKiM{OlSI?z$MCKKG36^&!}=?w}6@59q@-tu`2+Nn4VOZDn_q{<_qR=8sN=#M%4iZ
zUozLWLb^kK<|C-?l!v{B!CmrBMhFkc_acC+^p^kZ1-66o1vlV+uzZ6r*iOjTuR>Xf
zeEtmJ5KsIIDre-K*Tajm@}1{kB3)kD9)K(ISh{LC@`)61xh;R&4#K-~`vAITrSctw
zFPFPSqj4X~*EJzmE1#uBd%ch^UW3XwI#jO!+jfUQ0RUHrzjs2@&0#Ozn#zL?<BLFg
z$l+;wXa+jOQp*H64E`2Lv_rScuoUC)a0xh59bPm7m*!B8fjV7byRu#CXn;B{szv_O
z?LAQM&p!SWp+zbm8ILiHa?}hDU`AKdTYs#+9LFVnng6*LTYvWh>fhzUd^puTq5#KU
zuRh1I@8b5r_b+Y__XcgkYhL-~oMn)FZLCCdkMJH3e@FLQ!Q=j$=)nLmy_u${v)h%z
z)GuqBP`u*B2poS;cnXR&Y5Ax`qUz36R4GX{ZWoN6SN%8<MVC}psAktyHFA{QQXSd~
zV@0ZO1rTMjZRSDq8N2B#s5tRmWdQ8uR}Y6~oTh&g)jv@)_&F@^)h(I^oqf9b@&9x0
zM>4JI;n*FfRUS}xnO3ckD`gb>;K_aFm=XNtOob1wbOp0D2+2PA=yX`yFHa5yp|`w@
zhDHbFrn5*6%cp;UUq12|?Lc-^{`>`!WAefF3!w3n&-(#cfBEBcP(3aW9)pSp%2`*q
z886R|L~>gG6HTaZ%2i(Q;+8x<9VYVRy&Hkcmz(o}yDdLSbM!*_BMM0s%Y$g<dPkl~
zH|SmY$^H<Q%6k?-vrN8(VpR9#Q|s->R>=Qc3epGiM2i1Cl*^h?nMd-z!yv4dU;Pch
z8hIsR>B>5}3sy0d_3{FLa63AjwWG|*fh|F@)ggi!Xq!XI40yl8;mKn-v(urLhTkC$
zz34#>by!W8>Xt)uJaV}Xr79NJKi{G5E({hp3<`&|&|wPA7>gVd=EIpg4mWA`T;gz*
zreCEFe!l{L&*6Fol5&T_pV0^v4we(hRXVKh2HZo3j}t*w<#6IAa@7u9=tW!W@ZBm<
z*Ex8Q`Ns|u_9OSi;qWU3u79J0(g>QT4qtYMY7=OHf9~+L2Xf60{pdQqbohy01Fszh
z-vRKA!#b+(I|rQ_n(rM3uR;x-6a&wpzFQPAD<Ryjn9~fv4#hu#Ft|&>VNpowtSDHH
zO6*oNpMX7A#R@!SO1rzF551Q6C{hXm+^Yya2vtwTlnpSyPq9G_)%}XKLs90f*xv`q
zL51Rb0DKeyr=W5~agYLW#}qRP;f1f_h5-P7#kLZZ1t{`yFDru-oCmxJRs^4h_aTaQ
z>)~3cVlAT7%9D0Q+Lu6tD`pQsHd3Lc+cQcL;RY|F6{%kX7^C=dID~PEp?SCk;uQtA
z0642ywh+#oQ*7@EwnWA5NWha6>FuGCtf(NjQxqXIUrbfZ!&qOLrua4;fJ=%&9K5)!
zxJIL@D++u44M?vl%2J_vUD0TU-x-QPC6X+~>#v}btuRM}?S^8^FwopoRP2K@xr(Nn
zP{~u|+(Zov6vqaG<+cI~MYweo{5~Yb3Wj3NC5of>k=#{`-42#}ij+5~S(&1M=8P4J
zGW&JVJWw<^B6+B2(*rt>6m5%PqFTXrg0M!Ba2rXzqDwbedaOA5JDQ|Hu}=a`qvGs8
z;C`l%zlQfsiuQL=_CnFi4S;5aay7_aDN=?*^R=RVHaOoZzFdapdZ!rT2Ng%<t$GS}
zI4Q?G0&uIc{0Go%Q|@RB-*zZBPeohqRCct$uCvlh0icWWR{=Dx%2zBj-ISeX!NeYA
z>}{CvQ0|!toTu`aaS(bbU!H-=0p;tlu;8t%xDSJel;dc8eOTFjB&d%lt?fBHe@B%+
zdjjvP^t^}$_EYxg51jzzVG0o(S8lyUw~(^C5q5)>-<(1&RJnF6EQKk%TA&%O+#Cqa
z2<46>co?NzN3+;d%6$@qvC4>tppH{^r<dhvWg^xlm1mUi?!d!yN*<A1yD~xfmcq?R
zN{O!Md8PB8z^5qd4gh~a`RV|Kx0QbTkt<XhX$Epf+4^hPEm5*faHdqbX#&dbDSrxw
z@V?SJ2=H=c#V}ZUpd2lS+m*^u525l%=|S(@Dy4V@jykG7N<m_GQoSDn=~k8d5;(O@
z^@678J5=?9fY_;8POlGVmFX%hxu|?6g4<0MM4>Ks)%O%^+N(0sYt2*D>JlvNR}EzW
zIH2nMFC0Cn+EjpcI;8qJ6)HZe?i7zZqUw|k+znORp~&5|tG@XWs(GqO70BkRCQXM^
zw^eRKfGAW=+<{!N$~zG>cT^L5Li4VQ>4sdX>Wjhfw@lStiQIja4+U{5RJD3=KTvh1
z0K`MpLkgcgQdKTMu38lv1rKXfDJy`hQzg%UX1&U;xduxODuW!{jjH=mplMRAzYgGY
z)vG9|zEtr`;KeIdk9w57RrOqk8opDlLYzSPK@~}XAxE~p0VcMv53*3Um0kB7xkxsT
zgi-9SXRr{>ju`<9F|2d|WO3~IShR0E+tJ<yq-R(>!st`jF&ykBuu1DdlgR%4354g_
zt+bAm%+8*MvJ31#wD^(Ae!3jOi)`q0s9a*hBOy#@Ke-Lz71o)8lh;_eKkQy-o2f(1
zWSz0{ugqfCQ@kaIO`|yd4fa$pz5i~p2{g;kWqZ-J&u3TmM^eDnYyo#6+ocw{BKCs=
zTJH{9_YCfrumfpiSIQ>EqxSdM@w4FCeKvj+?3S~RH85Do25d*}A^XcouvD{)Z&Bm3
zn`u3*p6xsy!pE#hOV3{;yD}MGJY{QoBYDo&QRwFdn=l$Wuh<J)fq2dKqp<5cb{swa
z?^)#tc;U!>IT%7GuGty6tz23)9Nor!7Yb)~aNi~&*~$I&IRMVw!%R5p!u>>5a^)N-
zV&TTMyFlwgd$?WBQ1#$~HUaO+jiKAbi<_B>WIs24D||Y@y*LA((ztm;QSFP|%wb5<
zxqGW2yuw|k@a%Q2AB7GxxPED{l*M&?2F`455etJiIM?qXyveN@1F~Fh2F(KVxS{*O
zV!zEf?gX%q^J#=?F*jo#q<6T}9xz|ZP4=S(<{r{AS~*wb1JVj^C~;SEFR;%*`H)N6
z0(cd79<yj=HTMzqfwkO~O4Ox}JAMKlKIY0M0`P<zN$uOn-JFc%DR-d)WleU@y9Vw*
z=XQ>T^d+~=gIb*%z5)i{aKc&S-g2LH0ow<zHO*Tc`N;2}xrKMWiriK{pKi<T{CsNs
z9sH?GB)j-M$507pKK&0kvzyOvfCX26Tsa(d=ZDZ_Y!82p!diQIdk{^4J$c8&pxMt4
z{|Gt<c=ILLJ;>LFL+21Lr&-7m{+BagJIcSoim}p<pG?CAe|`~7bdK{S)ZYa1MKn?k
z=BH7Qc7mTz;fPQ^{62DFe8p$*BAnkwgR}_#cMeGu-_KqN=_y_p3@>8&xwO(6$FH0P
z?$i7a)kx0p{9;t5fG-UOO%WeTi!8<b=?lP@@Ow@oxy!Gf4!igGSI0qC#)naawu1k-
zCvXq=T{PBv$S3~=+#_B!1)SCV@hkvp_}s7Ukk<1LdqU?iKPC#fM*avwsmiB3cNzF5
zK8%(rp7U4}!Aq52R*mE(|MnYH?F~PW%)jLa&w}0e{PHs({lG7X0NhF7v6Di%MOc{y
z>TSX(9m=)~?j1n3Qz$qOm0dz@fPm-EMF=Z~>TV(N8FbtP@6FJ07go@sriU<_Mt6IK
zLPwN&3BP{};6B0mM;JUH_~@bHEhHTVAV$!B2VtymjJm6MAtD{kby}ED(UP-5!7_Mp
zP6($bCQ&#nLs^oLeM5%lFIn)TKy->w+ZFg!LF)}mX~Nc}$XybObU<7dz8L|UD?)Yx
z%B~8`6ZmvpnENY8GlVVEk;@iNTmos1@N6^yw}f6~FjuIixnI68LJO4w;geo4R48<?
z;u;hQ3x0+L`yF8yt=E+Z+ym&`6Na=wu1q+!1GOj@Ms@(cLKsPFiIu_&8p=ErCOkq?
zC5)dBVYTphD`;wk`LPhz2_A@ED<2E?322fhf@vzq8ihSUD0?bwrpQT?@NYc~Jr}Yj
zA$e&Ryq%H0629sOgKvaMbs&8!*h|pP?}bjKKztCgjSxDCPbo;ZMci(H`-ep%O;3Ep
zSz`e|Dh^r>m1ANFz1sam?U(SvUtAao^T);BHvtF~D`~71EPm;L<b>F84l1Fdy?+N}
z!^HVCPY4%PLm`b24`#qplz5Ov2&crCG_8#hPxG)8E8e1Y=6G@CAgG)ccXfc>v*N{A
z)c2gY?+z|gqS*Bok|eRw2f`GwRZnPM5D(BaE=~M&4$3ZyyS$J~7mMr>Xqqdc{Rpzx
z#3fT<@Va=1f!~>8+Ct>A#A`mt<%l)u$lVa-J7E5nxT_wdx#AhR_W9yFH^2+TgM}z7
z6#F_NS0t8w1l%3bZ7CYIL|oB;nw5$ldO_u$D8>PIU+h~#&tJLt+Z=E|5U(DBZ<XTW
zOz1okKcU;JO6*BX9W~-2T4JpgAA}?KPV5>2w(Zh_Uy*o9<Hn&4y`%<b__R;b421dp
z(!6^}4oK272)(5k3Me0xu3rP-kR&&N%ts2EDaZ47L^^7K7e}Q%K5*)oq^89iUkOhM
zE~V7i8$f?4m6oCdq>s+SQjnDY5`bXIPQ(3BY2Z<?g-M@MFP|ypQ8+0}T1owDwq&En
zFh}Z1z3dGsrZ1A4Qq3zQx1{wO>G{i*)=UB-Pda4<K3{T)LsB3O_#4S>>GpT1MVT~+
zNAA9~suHz-AdL${QY9tJ;aauy(*tTCDPa?mTB)33xOLL<Ye?!PpVj{pNohBLRuwwT
zx(7(dmHBAkPZyqt#Qs@!HY(96eIeZad|n3>bUsBlOqcI=gRg59HAc5b$<XOOv;!nP
zmebmQ&zsb`y&ho^N7>u|J&t|k6vpYBQ2^3@8_9_;J{ks8|Bl0;Kj3u=DlpJq4gNtr
z_ChlF-7jDpV)sBuRrzH)1*N`{JA!EFM-&zvcJ~^N!za)NoDrV~LT6+x)`66x=5~SM
z(UWNN!UX@XA^*|;I?k75(t_iLoXaq<g_%j+vm4XJirisltsZK=Os6Se3}oIfhcJ{$
zqDvUb*n=`y!12$8-Q*6v-K;<Lqpoa1228uLD`-67&Q740-yZgYE6P0Bixe)|%a&8n
z)|35`h9h2V8=52RW6x8hVLu!EH-rb+>sDxbvzzOY9Arlyf>9sVqz2~^wr3xT%loqL
zX%y$jzRm~2pB+Vw5Wv>bJU)nRpnfHoE!+&(POyQYC<|fR(hU>JUZ%CGF!uNP@Zuz^
zUj)11?1_(IDS~aJiAN+GOiL|MY&<O!oMP>3AdF^{-$FBnji#`xJ(m4J0TXfTKoLni
zJJ1=;bDDKu0pJ-ni>5ed+4J;*I>**g>@9)axEjtRvY+pR+ez#n&hY6x+v_~alG%i2
zBq{9BcnH(jLDWtc+1+|LdWn^1pzJcce*}c-?404SaK+BPJ_K*BvLhbD?lrdd2!I)^
z(?FQWWIv-d)hsqE4XvKdF6a(?4jWwz;0?C71~fO>kH3V<Emp{aN<Q14NDElcJaFD-
z4>%(!WHYE!En;0eASq^(+C%dW>qh~d64vgb0_k0LDVZ;2r_hd?d+eY8ph?TvYrWyj
zeRe{7(3G>o+)!4*o+$&(19sj<lwp)T166y-eocYTN9-$_1y!-D$Zj>8avGd9Z2xH}
zt7R*x@$1;w0Vu0yZ`zQ1%>H37gZU@y()~ypSodU*HnOf1wtvc|422iZ*dNUBw256#
zJ4&9j-l;J7f{m|+u$irC50%&Kx^g6M*!$Ewy=Oo5hUN$M9Ic`|a+B*JbmB(Rt86>>
zBU#wV<#-_3#d&<7cajUYjlx>HxhJ*Iaph+Dq0o&>Jch)bTTe~0hx5%r&V$?cD@gZp
zJdK$>xh3?r^x~eB0ltr`r}^c6?#2q_ytyS5g*eC!Bi9abt5e~VKc`)YB!ElzgxTYq
z`D+LCzk%FDtSl&lxTEL~mBHLX0ax?{_p%8(A>3DL(1db@w5}M&b)n$cNiIDcK815*
zQ=l2awXp#n$<0~=l_+j91K}wyp5pP*+?P`!jN#H~ARWuKq85$gb}R#DJhuol4ZHF*
zcb9fKo#EC{gySqXQ-!LX<0kvV(*&-l0ji0d?{El{xQ+dRKhN#C1VA!(CJ1FITpwSU
zzrYoSBbUm}q<$!k>xM8UW-1r9qwEqly)&Fi=i2uJ=N0bKP>@~aF0F%#{Tg=!3u>6Z
z%%}b{gZnBEPgN#Y*9~l0+}3_Dn9ZFd4|BK)b0ECIy|0DJO^*8pmTqyEXkj^*+gJvb
zJg(Jvkmhqi*hZ}^;2bAH<u+%|0(BwxCvC4O;?7W9sF*vw6<*x2a|gczX$jY!?v}e;
zEbWpg<$^cE(|g<vGt8H9Av9CE&pkQ^nsP3^9q<(#L&3ENoX=WlR&wtoXg=hgMj-cy
ztEFgM6*s^J&1&wCi*Tlf+Z6*twVX!>l+|(FY2r}N*^RW->M{2-wd@lv_A&4cTrv$u
z8o9?2Ks@EjXF>RkTb>HnnmD(G(0tB~q8?%k|0`{)@aDhT2+hNM+EdiYhi^^GWk>i;
z<w%b5b=1!t;}=SR`|=4buXTRj2$cErckREx#Q?q^Es0?oL$Aa@p6!k#h&R(_gJAyS
zWk^o&W9I`O!e29iEtL19?mdj}NKg7n-kJ6WMe@$BNTT?!Y4!3H--`yO(frm0P>JE$
zj&M7c&pC`-9PhaY_Tu>|6YZcm&HqemNN4z4^lYEyCsHi(9N(IHiUfXkH9Sn@1-cWG
z_)avqInNg@hfm4;&Tu3t{J1>8FYv)%AW7vTX~>_(j}3w5MZVQ2B$xQniE!pJzky!W
z>HPZ_puWPFjF92^yUIU^1MnI@K#4ZF&Rb7GCxdsP-ZqmzMz8NI-u)y<v-yd%^C5?~
zP$=~V|0oPJH~FE1aVc-{8)m@KT>c$Jj`R3c=U_LVH_;kw0smJZa<};rw7gTuYd(f%
z5nuTWi|4PHKd~4zclgy~AuZumo~YAZ{?Y&-N_l+>%I@*YF2biW{`t4a-RJ*xf=>_l
zliz`@k{?Ii#zWpv2$e_t;*r2r@xR4^rJ8T1F<A}oN4I4yub@~+9e<@1xqAM7JE+(n
z^TsX!KH*(x7h3~A_ze(^e0B=z^ptmB1K~5i0|SFid<m^`J?9tDOZ5eBodRJqKdlW&
zU-EzVNA4AWl@|A2^Z7=2@rIA281-9z(_l2oJAT7ez~A%H8gPE#182d!qg|LsQ$i=9
z{0K<52tS5Fx>fL_Df>1djn;a$3wPZ>x<d$^3Ywh)cO06#goL4JE@#0I2u&AZa}_M@
z7KYF^6<1-(B9yray<K6@T{xQvz#ierLBO$+wiL~^S7?X^&Qq{wj)$t3FpUP}2ZYXx
zV98q;_9qGt3fU9^J|slOAUQ0Aje;{i!aO29B5*nwJSxPwAvq?joCcw<aAgu2&rc}o
z4!FNyU4dMH(CZj192Xv1z!E5=(=;MT@TKrwurSU373`i60%)gmi15$1$b|~wwBa;N
zm`}s{lfr^7@H<?H`2x8J;Wh2Mh!oDuf-p+B`~`5QgfH>kj51m%!G0)Ag!|H*CRV7T
zVNRUTrU<!sK^%?TX<_>az|RPiIG8^x+;*mYG3SIEPvByL@MsC7iNdFoL7F542S9jU
z*c=97valx!nkhoNYLs0NexZqQs_@AikfsTzhah)RI7G4HOTq&RM_(3>{sT+tLVOr}
zx*|9=Be^R4<_%}A3BO@;KPJ%cEEIps5azFeiEQBqx&w2Be<&D#L&%tmhPo+?q-XP%
z;MyO~<O;u8U@1>nN$Vo{g2QPzQy}E-hQZqcOI>iG;PM)PBH_x{5Ecubc}VUEUK$8X
zgpeL!xhtem=%`fi52g6qJt3zNwI~x}7eVK~pms%JxzIortq>mIvn1sM;W8}&R|<h~
z(0nNH)Lf5*jL}f35^lvnrCRvw6O`2mR*KNq3L9sFtWKD}9#yIrI@3b(V`0iX<emtn
zbCEO%H?WIBX>Sx%o}hUuu&;oBCS0Yyw@Fw_&(U*XJuNoB5X@h|e6!F<TgzVxq2&H6
zVF7i)uZ6?20eB-ExP-E|!kk|rd?z%S;l+EwVFGIZK}e=;PmbdEWWh-s?t*sOBEEPJ
z;a0o2lsesQ;)qyew~NCljJ`wk4}jgBVmw7ncZu6C0^uz7`3u~x;{IO%a1(!<gq*uL
zo`Pe0#pibc@DxW-f8!<2rlp7jVmG><yv3g;!{38qJzY>AarPTD-Vt%&VE~Sb_MAVF
z`icAknD7_>-UWjJV%;LNP>?t+6S-jV-^T!+5Z9_<H%y#HeacC(F$%(PaVd=hBgB&w
zc#9ObP)IUL{DY<tr^Fkl;Y_r+o1$7VV$~ct8Y{N)hi06(={Q*8#V_o%%5qx#nxZ{t
z#FQRz=B(I17>ILXV+4`}QAbZ~q8QZ(OG#n|?OQr8?ubDyS<J13+bLqdM^L#S&Ygq?
zP8F9~ppqu`3_#gMv2-l#UJ^I9LhiEYLn}t<;<`|HaYgLhhn~Ny;z(NVyCyyz1M}C#
zCq2NOA=(CjG*j$N{d$(zF&Es~q7(wQ9Pu-HoNkDkweT=k98PiFJaNrvB>7_Z-@#oV
z#_fWo+hP~ml2s^vO>4?UqHPJ_#o||YfV(4(YkB@k#7<wp;9W75-c_YyGA*6n6E$~X
zw@hr)18n!jpKE|97mH}ovO)}@;O7G|p*L`q;*Wzs`cOP{1O^|8t7$=`O4QR<y=t)+
zEkD<YK{Vy96{qqjs}n<yg0o(na8|(c_gHM}4d4^8OBtjMVjM+z8^zN!P=6}+{2NX3
zOnhmC!6vbY?(XN}NQx`H5L-<IX|ou;9c3@YxX<C?D{<W)0K68D((vew=tK*~Z^gx4
zD0?Rki~{_<IKMU8>4SI*+a8s6N9j8XPdQ12-GSI5efJuL+ohl0K)6HttPUo2N<ts_
zv`d<~3<zgwFD*~HNa4M~y<2LcwLDj8F73y1lXlaT++CW=LS>J%n1a0?(o;8>-z)vS
z9@L)F02<tRNvmc8u+J_np=~MqrLGhQI3TT{T|C}WJgvSRl)j=bC=N-!|A6MO)MGS+
zKGFyc@JA$`mY9!9dDOtiB;hBp`AP%m&EY4#5Mkb5O6ZF=43Mn9K;^jf)m{h#rSC^V
zB}n?@1B3|Syr(GB3CXz;sv(l^5+tG09*Po&Ngb$*I4P-$fe4q{)B0e9v~ewHBBeto
zpb{m8kA?7*bWshKXldO)AdQi>Tj5Nsw2vbEaZ+mroM$ADkC8hoEpGznIVs>NI1{Av
z_VY*+C6>Y|Nz&>+L33XEk(McwCG#n;rAXH(9&$mNLAz>GrBVturAg0dS>~ct?1r*S
zQg$zxxGaSP0gx_D?u+D#)TJi?SEYv2D7z*dq0!ZKDTa25Wk@lZV9Atx?$V~0EXijE
zRI??4md10W1e!74ke<52i<{B~YVKQ7f7+LxD{b+Fzj@L;>bvtL*LTn?kbX!)*=?yC
zz5fcO&j!I@k@VYIs1!?0SHO8k@)(DtRN8(VZr_te+=FJB^v_({e^VhHTMY9Lr2e0x
zuu^J&3cxC9(@6-cr6~HUp+=fXFSmLrX)O#smO7sU{)rSr3%5@thlw!wO#0~*G@GPP
zsWW&kC0qu}3rT52u33sX0S{kG$+RN)MjAXDEN>-8Y@x9$-$`fWu=HN4r5*Vnq;pDm
z;ix`M;bA9rw-n^IsOQtOy;Xfb1a`Nn$Fv20ySnaQ0CuQ{(dS+})rYCO+NGA~qt%?%
zZE5$3i@JL=%66+e)5bGb^+o!4z)kH!@oRT=z(;`F_o#1u2R0A&1L`jKs+SbNgr|Ds
zeIUHl&9sKGPn|mt$$s@R`Yh{!x?mM(ywz2K$Q@J%^+R$<T|!%y5356W0`8+e6atka
z>Qb739aVo42;njHlFsnZSACJ*JbvnJzNnzTU2XdpzyP%qt>7G2&!LEUpxRE0QbB54
zcW?)*4^qJXggS?I(S@jcR>09vbs+7G3{$rYLVZuFKOYK}aCO!M03y_5`=KmSJ(l8}
zQR+Q~;EYk1QHL6<R$JgxochkUuy;mn?@NmwXVq)SsdMTS>NOM8{pnMgM0L9}P)$;s
zE`$5LI<hUwlGV#-5g|pr<sLk|pl-bmq^WAldjQhZH(r9}qIxE6^u45xC4-mM1-qe{
zuI9smyP`hTAIVkqvM?mq)UWNdw0&J&Ows8Kb?5g0W~y^q!BUobA-y=W)$^6$&QZsF
z54Ia>c{tc^syBWHpKhsV)2^mm^_O2G$x{bJpe$eg)n;fGs0~iIXt&j>Ag~mwo4P@G
zM}2P@s7usq=(f76<|F9+SE_y`hxDF$`cF_TQy)r0QlYL{57!>3$G1ds)rA+q_E^1b
z9cuVQ{oyLiH>g>9k2R`0P(<vh+B+4b&(yt!A=jiH+z6HD>UXr??S;CO;@8dUuvPHl
zrFtzsCsw{vpYo*d0$;1wtV8yV+KDDvZ`GYwB6+7CFc8Um^}`aBeNZoc4)czhPpQ{)
z(%f)@r7aqFT2kMtDV_`y+cfv+!fw~}py0|5jb#dwotifkMc$>^PJ82=H7+Ia!bNjo
z4TP>5dwYt%xM_m>g4A7eCl9T+N8`R2Iv$!0^uX`c=trQ;Q`7l()X7WpoHm&4(>$33
z*Y<1n(~gS+nocUPd24d}z~Dj6$FvLUkf!oC2oGx_=>rrW%_kp$<%p)kMdXg+#SYvt
z&0H3oc3({d?c(y&45lwY{59ig18RU~F+J(WH94(;2-N5)cow8NGy#ZUP4r0AK2#Gm
z4Wwb3uD-~f)JP@pDO~f#$54sT*o*)~YF1O%9i<sUGp|z`BaL#RHQDD-vlz|zw(ug>
zu3^R_8>dP90G)VENfo>}t#P8E>KV=OZor?_O#BSFbDDdFP)X24Q3xSX(~A13Bu!{2
z;O8|KdZ{LBMpGy(MKgXU8sUN_k3try8jk_6o2GeJg|ds9*-6M<(m4Br?6Sr_#U1!`
zO%W}fUeQz)quH)%65hk^HO<Ok)bP6ISx+D`Gz;iP&eV*V3SpL}oR<5tHN*FVG)Lp5
z2jGV0I0v6@YDUq(@s`H(FF2a3nLG-@Jk5+<5aw%wXh%zdW)Uq^-`05ADUwjAQPUv4
zShH&rytt!rp$%6hn(nlecvs^_`-V$3DHLA6r}?TYgk_o$7omAyBYlf%mur$}3SXgl
zO0Ulcn&;1utJEx`x$q;+{FcQM%_=K|)tX;N08pd3*aVhZjZ%Ys;mSHq4uvP`H47*N
z{#cVso9&)xQn~`)pjkw_+#5AL?!fP-nxpRke6G1kFXI=Q2I@tcHQTAxUTQXPf!nV%
z!L-@nwWgg18upE5@3(OKt;RGExObXO?%;f{IW`Zq|Dc&1%Ha8P)Xt-3+p2Y<Z^gE0
z?<(Nac5Ukn*xjMceGlMH?J5`0?9%>BOPJ1D*C9}G(XRa&b=s{RD?-y%8&C%pH|@kQ
zsJLr8(13NXHeo+hJhg_?fO}~-{Q;l$X?xrSe809^E872bKsyTSz)Ekea0@yIwbQ<X
z7l*WQ$B`V?R=h)*kG6=SB1g3PqwxEv_SI$>Jf<C13xmGetF)=ZPn$_waQ(Gis4W7t
z=V+vQT$@2#mIJk~>1GMi-l8CTu(oR_sGQLDI|iIRL|eKYY@ymYwAn69>%R}lN$qKB
zp>VDD7}$-_Zaxf^NNpmuQ<S#+1!zubKXrqNXzhmAa5P41!D5OsRy*n-{EgG@dkA5?
zcC-ZHY3)r90M2N6x*yMK`|N}HbK2fNfHT3a^&AV|693~=vi1OVCMnvLufTml`+#ow
zRBiVK$fao)({S*jHmN&kE@|yM!F^fVi^4GJ+9f8KxT;mo0ogU})GqMiy7oHtof+Ea
zHOOUZ`-cLTrCs$6G;_4l802nf?N^-93OBW-w9tJ^yN$k*%++?lk1{Cpw1;Rz&uwkr
zIM^-JeoV8CBJEY$6<Dlw`51sZ+HTXKS)yG(0?l<-d#D58rP{8&klfSGrA4wbZTMU`
zdS5%2meR_#lM?`_&>pP-*#m7Wdlk4VwH4n$^`UkS#pNGq=edHrO1p<v6sxtvsnf2}
zj-sXfT5V%3>Qtv)L*G%?YvbG@e5{><Wk%%_t-K0=2CXMW*&DT{r|{{8Htz#enzjE@
z?ChnsV;zLAwB?<l@>;w06I%a$qn$<J=C|5|*P!}N>#z@n@3k}N)7lSOi4cxDw<B=P
zNvH0BvMss^7f`lUx4i_oZMu0hBH5{{qYqqm=}gH0IO|3(M&hE|LW9!Xx{)v8p{s5(
zjVRo7r>Y=y*X7Kl@#h|0Aia$}b#CL~jF--RHVXIY!g5iW{kj?l2oLCT>X3Nr4t4?Q
zLET$gCq1OAq=)jb?#>jD`skv`?h)O<8YD+`m+8AjKV7H{EdIK=9E1V7XCVL_*Y%~I
zI8Zn2G=t|aNEf8RH3-%ftwx<r=uC3}4AFh-2ZNzHr$@kt>2@?jcv9E=47G^V4atXQ
zlrAL)xl_7V<De3)8%NQ$7~L%DwPJO@V@*>Tr#nH*F7dkSli=@Z-C6u{iSmrj{R^m^
z)pd)3+xBxh7bg@Z=rkOXL|x=Pa3|^Bj)hMtx=yr?cR@EY1r4048&9i6X*zKQau;<y
z6fl2DckFlAy{xOHb+~k0X(Y<7==y$u@VZV*)1nNWuN$Z{b*<@1%hK@`5N7Ls2!$}m
zuDh59#0^~mt&-i;O`8O}w{&uvk>~0<XF@ekH|!~d`8sERm?+e>o(({e?&q6ODc0rC
zdgmS8<Q{;R=)x&pdsp`*EzXtdHaP%rPxm8_ik9h8X=Zz0*Fg=t<vPsp@EqvuA@t4V
zLtQq#upjB7QUR>e%})WMT6eo0%4&2CG!LuQCDS@-ovxEN4A$$yC`R&Fcey>9<cY5G
zErboak#j)WsM{cd<*6?E4%~jGi~AMSO*&s1T{Y{DP#E;3?hsAmUg>h}-@?*sU5{w6
zz0n<(L;6-Xg-GA&cGJuJz3$*}<UZ(Lg(0^^UzrR`TlI3<9<WVc&<<tW^?hmnw?lux
z6T+SPDKrPzrEm2JWzPC7y^y%*Ptr(cxBe!@O<ncH*$}$vyEArVJ@hWLUuCaeLl@6e
z|0fN^y!8Llo`Ze*!iliEUq6g?Iv&suqL1gi^`B7m_@KV-Jm81)?sVrK*1tFg79YKk
z50zv3&GfmOul~?;;QaK<DgNTG&n-h)fWCh@uIq9Aybu+hzd-%Q_GsrI{R<k91?wl#
z?t~Ni8d|Cd(a)+wdxh%HP?$Sh-w+4V2z@{agpvAA^sb1~$L$68Dg8=%VMgoc(;9n>
zz8`)06RYp$2%qBgWqzpH8U0xrgPhfWOEH~u`ljzF{+Xb^R|<TherpD#NqV1L<j(6K
z)`L4)-{BV^QuJr9fct`e<RT=g`Y#nwNz;eYtNpS*XbhZ5*WbK`<cj_R&FZe|ANPR4
zYkIHENUrNY-G#CY{b5=g%+x!50@t$iF5_X(o~>W^5$cqq?>Z3D8+u>b=aQ@cEETyt
zJrjmT$k+e=2u)I;U(*)3+xi`}lde$T$_mmVy$}5gL$Us|-C(<;H_nDiiT>RL0PgAs
zxq+orzmYyLxUWyw!kKdYQd;7x(C3*Ud|=l%(|Sv#{!iK;{!pK$1LBc>Ds}x;`fc=z
zt=8Xv17V$h<3uz`y}m;!Ogz>vra{^h{eaF;Y0!_OKtiMb%W+_Ns$Z-|t33l8fF}KB
zny5b4?`nmz7kWi1Tx-^^p$fj%+b2*Y{f&O!uV|XL`nFpEe5W7#HwxeDe;Ehv5BgAA
z0dq7gq(Ov}K}QkKEe4h@>{i3eX{ggS!+Q>8+YPs-LetrB=|{j_3~3b3*ljpP(P~$N
zNVk=nA#Nq$?uOr}o_h@$b_xY}8nP+6;br)>Gj#SDK6wH!_8Weup6!4kB^W|)!>cdA
zcF^!<Av6ye8oL31*syat?D`n;X!pSp!%TW`jv9v1LfA1w4s`~;h91ty`57jk1dG2R
zsuY|7hVN<Idfd=eZbv%@8rEbZ8)TSFf&5@Y&H$*MFxZojgcyFAiHe3Ay5rZBlwk(H
zOpu;5gi&-p+;EH*Lm~{Rv``XhQ2PK7Wq3tT>M6sXk#H^A(2HX3F@}dJNMa4Q=K>yQ
zxJ@4?#TzslT7N%nI5!N4GlmJ}sMA?P$mb|LXBh4UzY`48wxHUHhV#piBpI^l>$>xX
zXqsy!8$Ry}wiLr3v_<iPp^##-sfG<RVJXcZd<~V02A_AR*(E~;O_DAfz7ZizH%yrX
z>MMq=y?H!;R}J#t!F|o3Xb1dt!ykXbnG8eHC8%Z^vhq;FEW>I))HmA@GXXR?hC%<r
z#0^7tT1B~O*wYfAGUR>=mRv*0RFvfz(wmUv8+sJNQi0*+Vc>2X)|ntIG{heTuE_9J
z9CG$zLw*QcykiKYwek`}?E|RZHI&kOyVS7fIdtwB7WyDpW+=#kGxrTM#zLjsFt-S}
z3WN7(s5~%y{sg3zhG$(+_R!FW0FMlx)6SC`!^RoVtThawPgUv+s&e>LZ%A5<<gwlG
zJ#`pQ48v$^bAzGB8C1K`pi=?()UdJ#>h#R;lMZZ6hLy));<=&V91OlNba{zfvmwj}
zKD{(}1S9v#FqZ}ouMKnefb5MSh+g7v4Sxkd<(<LrPf))%^m+&Q2g8I~RM*jHpP<IY
zb22tixNM7Y0Dal8)tJtqaGP-;jn1|kchhiihjFY7Wjl?*EwNzZv0}LIZ2X*hCKuyJ
z#enZNjvfUsT#aKsho+mc745xnH!h>yEPISY8=>i8oI$O=*XTYFj(Qq>?DSh1UdB5;
zAl+wdrg6%C<6HVd;ehc~5lFp_FR6P!Xw=YB`5~h~v%15^dWyOG7{?0m@QCqe>S2x=
zYd1jUn6W2~&U}rpX`0|?{E|8vf8#{jN)%um=84>Kqd!$Q(74BsY8Yhfw-W6fY*hFn
zcf$DO8{|Ta<rJ_DHHHsH5@w9L4E#xBD|%AHjo-#27h$ZU9axdZL0iBUWpt&la84QD
zzlAf=##htfXpFIt7GGnHu4~a2aYh9#wZ$7h>VV|5u`r9`FK3MN4#C7(qYHivOnJ^|
zqE8wUi~)~<Pc+_70e6ydfCQTJ#s(dL$;PkVAW1QHE&}d?v2`i{7mc&&&b?&(m?AEh
zjZ0`hdAjkRJHTBrMht^%SB?MDyZoB5kT$MdH(uu`{+VIS_#1XJje!(f%`(2+2<~iS
zB(2fs7%!zEcf+`|0Qj56>9@gs%UD5k>0DzU3U}ohXVC4HZ!Dl*ufQ184!PULyva~0
zG{*LZN|Ev9AIKFOSG+;)j`3<CyeKiY{RU+AyGDjqxk`=q>)`M`<GM-6l^GYWg~9vA
zyHk-XH+sszU15wc1OLGI3&lt(jn-MP^w5|!9o&zMhR;A+W&Hd*RIS?h#Z8da7*oao
zS8FVzO=)$;rL+~I-Y6VI?y+(96KFoM8y`o)jRxc39^h^??xAJvr^aOZ#^sr@=_+WN
zjA8V}+H>QT03<JrD`FvRHl}xj=1b#N+Q0kC7)Vp`*T(*zLgkHdERE>j8oxdP@820e
z8UvO0#u&Q0J{TXoMb6RmFMftX>147$ki(5FrUeN=Y&Ci8ht4(=zTL%xXPW;Tbat4|
zxIks6Nl!DkU8X)!Fz;;Y-3K%-rac3ovfH#Q7v^0}6%_n(GlkLGpu4HNA6WL7hJA~~
z!!(!1fqPAD;z8zV`fLJJyi70bo4~fu6#E*5`%OoeA~|4s^Bo$>+jO5g-Gio)%b|M6
zv~364@`!1`4S0Ce^pt*{;+SbPk1}6VmOFBOrqK4d2L7g#Cm;+kZD|Dcannq?p8`!E
zZG;y=CP4sout`DVlM^QVG$XPhrfna?Zm6l>Isn5=i)nBFNz-LonF%*tw?ZYt^g9Kb
zB28Hd$VHjvl|$u}DY!pWqD>i8?HJQp+Ncw2(hY!zai%>q(v3I$Kx<y7O>xv}XH27L
zZQ-nG<Sr!VOt-t!`!B(iZa`t8$&<qKNhZ4z$$8T#0ZFo{st8GnsfiZ3FPIW2LYr!u
z^#PXBOkbN};-V>$9{)?GSlVfP*;E>ivUF3IK5*@d$+r~%S4}f~aec0t>=Z%2ZaPNs
zhz!%PBQ*cZG=&U-`7G0WTCUADmCOZAj;ZuF(A+T1k3@3Q)RsQ|zh!Fs4}iI*vRly1
zGi|5oNxsQF9gSaLO22}#+a~|}$Q7FU)AXju)S9NP#in7i;mjRV8hzGXVj4?xox7%$
zbd%XjO(q}scF#1AM)qZ<r5c#OZ`$z)h2<uPbR-of*$FiM15+)<qAE>Qv|9Ag<fZ}c
zk;$9_*Q!jm9F$d?PSE0djmd+?C$*-eXV9!O4SNam^`^kC06aD=s)6Pc)AnDX(qK20
z()_;BbeF!@dulpNxBLrJ>{wK-*>rIj@Gnh!X@|fo)7-Ntdu{qq4b3;EfW2UQYdZK9
z48AkPbVBaE$!-APgQ<qzw2o#mA9Zmu@AwV5E#|D9VA*PZ?T*|w^PoRqVY}IWih?sc
z%$IioztbGj0B3fYeJ7*Z&SpLBws0{=UxvfG&FSeVb2T5PjTLU@>BHfSyLs+i<o1~V
zpnl!M97)dXHFxR-Zcnp6y_LMo%P5kz&phN1%J!R|-GuoA=C|~Wc$-B#Eo&b%FZ~gg
z4w>Ij?Cr3*%pEx&vySfWBW8Dm>6Ay!S@c#rW)6vkim!QO5i06u&e(}Ee{*l@nF7pZ
z^o$%gSI`?E&^(j6?jUoQ{>TNJqcWg*!u)dxgdt{@hSZ^E$B*o=6lS*5E9azn!3pSu
zn=j4;O@z5U%{wE__$(DqocRe|%2Vcm9!R3im$$*081sGy*o`%pOo1@YypDlpym=;t
zXil5GX+U$v{L3Yfoi&f{4V81|_1%C=Fn9bJJ|&t5Z=m^KlDX|*AkLe|F9$x^{E#BN
zDdwa^ATF3Ubb@QC=H6>imS#SF5~LT+&92B@GKZQ#bJ=`>!t3egr$3-BSIo{cp>oyy
zn&RTu%)<k44X&Guec?rh`7Nz}W}4R@0U*nq*_Ffdmu(KFX;qHdI0a2}!(8eM(wpY*
zhe3GDeDgHS=bDEtg)q<DIsz*BW`hi6g=XDeSSm6nP$;_CJX3<dcg*1wn<+87JHz~4
zbH>jQmYS_JuefK9r`xK`yqRWf_sz#>7n{A@+-n1zsxSvoQ0Rf#c`1OE<_rB`>7lvH
zPyip99q87pGOsNFceUALFv@DoG4%CMtyyq}N}YLUJaF~qBQrtv*t~@%qfg8ueBgb9
zc?<pOV53<<jquc*NfYa5=Kb&CMU&k;d@^XBo2y#^|H9lp7WiiK7rrQbX|ASqfLCV2
zOt8H+e?;%0H|9AMjD2ffODp~F%v<QTes4bd7jPfU&+o&8qve1NIVa2d5vcDLi*XHD
zwpv~pV0W9P>;=lUTOQHRo9wXIlU1;^({g?nxOZ8SD#7h+(bEn)7fTMU^X#_#<pcL!
zEdey^cC%<!L(|>z4}I#g$I|K_sCZa9(XN!emgQ+6^R(2`(zBOk;s&Vfv;0bdi2as7
z_Ct8UQdI_OZ;Lqr<_}s9+o@+eWU<kF_pqg?6gobZku>5wVrkV2mX2B^>Sm8w+V6k~
zUrP@P!TDM4#{ute@uAJe0hZ$}aXm{Q{oqfa<zos-1zBd%FZBdlX7q%G6P7dY!5Lz?
zM60}^79({@VU~`q>G?ZpDH?@rxJB0v6^*d0qUEtji{>@hqAVE;fjDLPk>>Z&mdYfk
z#8^7c0BNkH$4Lm|EZ=_u&3KE`Kd9(w%Z6uAIb-Qfq38rl{!d5}Ev^)gPqO&jM%j5w
z9(75{mbD`7KTEOPrmJ?r@;QyrQ!RsNf}Um>(;vx2OVD^YbIJ0-3NJ2OBI)zhbjwTp
zqLT88Wm`UQS1ltchJ4L(yDf6pEn)O~f*F>JJWOO-9?nEA%W`QFSh6kA*zuywu`Hy>
z{|(Fa<+T6vrp5jz3U67C(%#=(%UcWV=2_mZh2Qy>k7(0jf#pOFfVV9n^gAqtmXGPv
z<04D%LjV+8{-Sx<9ZQr8%1SKBNpS71WzRmCD79p_1@4}ul)l0#v)q}7=DKgWz7V)_
z%c1!&>s7E+XD{6h`9q5@P4pjGF3}9K$};OGXjNMlFGH@zQbse#TFVdPVY$xY$0Dh>
zbc_Pvv869Xil128(V9?$<>E6~ZnWH~0^q4-S1UBiGfOL)4>nmex4`+_vYL8~7nY-+
z!SQCx2s^zzURuif!Sh#^uq!b5+A`t+OuVs7x(O3+E#u7KerH*J7c}oJKYBssgXQBe
zlsQ^g(IzM-YdC!qzr{N93CwS`jxr;+&HA?%W!tT?c_7<i^_mXAPHT^37}{lhk_+?B
zR%yN+Sr=<f3>@BVz19(ltM%Ay0Nt$5D5&giy-ahUJ=Siwfbg*T6@z=Pm8Uf!Piq?*
zt$A5pXdb%H+MV|A?6+<$gYbZLS_5+4)+gOy;h^;f?fE=py+L2T9kJ#gK_!k_7a8dr
ztYg+SJ%I4FcBQ@Te%4X+c=}s=odiC>DyOX#$F0${lRD7)1NH1d)<HxXZ2i?AG$*V>
z9Dob4_HaUThgyrLf-KD1O9S{xYvyej47WDW(oTf6b`_FHYd=~Nj<SYl%Ww~#vL@+4
z6KzfU1twywSE*}_waPr<aGbR}{YGTGH7N;*)7Fm)fInlsp@gNg)|)g>IcI%M<CO%f
z3r)Wht;=cMCdt}yFI3K3*L)1>Wb0W5xfJWz_fWZD{c1UqRO^SSFl0}&>cdf)i`JWe
z19-{Wk-D+V)-x0fPq()I5_Ydx*PcSzRcjXy<gQs&6t=!@HBw+c!x}@IY%;Ci21A%-
zZGQ|NW?SpFfjh_ghJs-?tleo5_@-4&KeKVmdfExim1`~j1Qzn_R_y^4=3Ad+0a0M>
zL_OAR>wZt@6k4Ap!eEirlRjH4wl>ic-W}@)+Duqt?R6D^yVgY!fR|bq1i<_~YcKj%
zqRcw70Y2Tg#?f*}xwVe=pI2C$qX2kdolHGdrFBvk${t$ndiwb6k+qK4s;s|^hly%y
zt_Tw~*5B#@thI(xAhgcve*wUHtAe)0Jhr|MLfI4RV<+Sqtd-?xi$?3vtI&LEJv<2h
zKC}AMV7|#Z;T@X$xz$U7<c0P52MC+3jw9jWOKXk&2iSdO^`NZ=udQkH!QUGzPhVTU
zw|+kdxewNH^bNA3EvXGmIN6G$;o%nB725f>)fP?j{cSePi}0w~{3$}V!!}h3&YiZq
zD<Rxvn@=lC&bD>5`_RR9`8rf~+xkC+Jy)CeJ(>f#*&3|Sakqs~G-{9SIIS0Z*p#%{
zbFZy0?Xd8)1rI@ey==eHC}f{4?jUmeZR2THd%(6u2`{{D@jt`hLEADKFdVYYp^r%p
z+q~MM+CH{Y>RFH2E(qW}YP&*PIgZ%|wWc|cuWd;QRQ+sTV*vEGji8BdfNe}QEFHJS
z9Dt=j+nkk1f^3<cpb~7m8U*|a+a~%^=@8p++FllFyJ-X<%yw=Sd^%~<P_GqktE6W$
z!q$<dSCO`rG&Ya2MTzj~lr7~?T7!<Z%~%6qjIG8G(pcMk`Z26H+qvHGBHp%<c4nNm
z4W~}%jLmm8Dtgwo=ufbnvwi;-mJ)1dha;D0%kV~$WP3->oVR^T`|px%Q8ar<vB|a2
zykHBXm8Ddhjb>?Sw(M+pXuoLta|KLXve{ar@UpFbH)@z}TW|{Iuh@pu!q`>YoNl1G
zX0zwP{B@g?D}))gn0v64Y3mvQwk+G9RNrjdA{sp9*w&wh$_-mPcjRu`=CUZeWvhRK
z=E}7ttVda%Eg}fGe6Lx*e`;Uq1+_c2AL%oz5?k9qXy3KjzK6{+TSzFZ+_(MF2~L*V
zo^3)|g>6YQC?42;F9ojBwvz&I4{g}@iYLjoiM9n+*@n}bvD!9I4x2T$)pwDrwN)*G
z%{rTn;^6hRfwZ6RvF(YyAMj6X1^2++V0%X2CN$b&JRp2(D_;oGXSOpGxM;GCPeJ26
zxAmf1<ArU^NhHm-t6Dho(w0DL#IJ0h-$U}+){%l$|A(XNj?1$8;#q1#Gb=UUz4u-;
zEG^4SO|xy&wAAX?P}3|eUs<v@BC?S!3aBgrK|!_(0)nzZHYiJwq44{j{yLv??>XOd
z?&W=+d+#~tK1?tFi%!W8m$&<XJX(Ih9R_EXd(u}iW|y0v0e6H^@w*kEwv2ZvX==w<
z_7uFZXRM&@y#vE-8j6mL8CoTeGB%ZAXikiu{o$H3!?Fu~E{t;eQk5%1Np-Pqj7-}1
zxihZP`Nf0riX4_a8E;dKlNUq!EG&34bO%6u7^mp5_GSDON#CLKW3)a2G=Ij6{{Z_K
zBVY@-0EV7|>&F?9T>uSaoMHm)1jG9exE92Cs~w=hj1zQn2w~J7gh(jk3>|~Q7@=o@
z9nSbd1ceAj!2@uS4DIjeJIS!!1M^V~?>1P7W{lcU9aIeCFr{Z>86O_OT*NURqey=|
z<1czEB{2GSgPdY)I}D9PM$E5}Jk6N@1F+998fcG{#JEi5P|1w0PvLzE<CRk|ahCDe
zRy3YtI7|ZbJYxgZPo*+8yI~H~81pIbmCjgH26bx&<E>hBW-@MG1$%+<X)8Lj7~ft2
z$z}u%pfQK>3f=s?$Y{*~Xf9(86$$1s9#TO<K4S+9>IICbQn-DEaq4}D6f)9FAyUL}
z^nx?Rj2x=+DPioR$GVj98bv6}7^B6IEVnXD&T#Q6qm;74*BGB{1b3aWzZn`8jK3&X
zRmoUSSI2HJE>Y66it&6o>{c^2JPlIA$fdx+O-8>1JgjBxc7{kDqc#uNw-^uBL+>_Y
z2Oah68B3`6w1M%C8~kl#{PJJzH^cfX?O2)_Pg9nsg;Aaf(N@N`6ri;+c6^S}w=-^0
zuIUb=kV@e?7(c#)p>;C$(=n=xAww>IUN>X?W{@66HC0UYGImtK?LNjolx*#1tmy<9
zV0^h0<SwHl7b5o<dyaw|WISc1^>K*tfG!RUGt^(e(g>q@49<))7G4MFea80_@NkT=
zfNCqp8OvWm-vh?hGMJxW3{m)SlCfA0gHw#gP)JTQiiH^ALxv3%c0Xe1EZ}Asna{!C
zEaUYJXgtDnql2_9^P>Y)2W7`h+JWh|XZ}VfX$R&2t>BJKzqdh-GS~G(!-=^|1M|+z
zoKCp!!fc_GlPhx{RY15g%Q7M2&K%l`J`d(>Bn)~o%WeS7i+Pq-25;uYm*J=n(`f}b
zU*?%_A>zlJK7{Wx&+})RsJ!SHlS{d|0OmAZ`8>|-qnJt{Gv^3AJ;7Wu7nXvUaVwx0
z%w+xqE`;f@4kVN*{0fa>%rYsaB%FCJ1Y88u@*esknR_X|6U}^y(kn4cC2iwlnd}H~
zam>$-Q64y+Ir%tzOJLq*!nae*)3gsrWPXv2F`Z@xvf$Gh=6kfkOJX{Ef=gyj9E3;;
zvxz=ea+Z0QsteCCXUNg>Obg{#Qkhw_u%t0x?*K|VGi4VVGnir-oXKQX)Pr1L?x*yM
zHH+C#(W-3bZ{GnXhv`iDm5a>7FF-Musa^|`$2=^8hnJZ0TbPo|%){9jXg>2AO=1D_
zg=uhCm@m*lx{x_Z5zZp!$8_>9X1+iN=@RC@1>j1VzXt-kj2SuyTsbqB-db0!%opjY
zyvAHmjuBpGR>eT0f@xF(yONns-^9AX{ND)rs+iAG#;Th6(-N4dVd5(_c<`8PdJJos
zPL<HBV+PT>c#FA`GFG>lE>tX3&wTe4kOt;g!N6=}{&EYXiTM}pOPiTiju$#xn4|uf
z*;Zx%Wgps@Np$zBo%z>&*uBHd8UX2FmIc64Cv$K!>~=9%-2v%lhEOiBhq;4t;=RoK
z?_g+s%*zr?cRzFHI7|#MyJ&-Um-z=BmhUk?ql5GylVbok#9U^jQ4BME4#BAr=4*#x
zX_Psi{^P=Z=Aas6jOkCw%W>wbREPM0nOy^g3Fa@Gz)doby8vd2X>^6#)67>Wn(&aB
zXAhA_%x22<&M-f-h51>gi#^B@*7{f|*s>N=6vU1-kw)vEJxlThoI1+d-~~k|*1uEe
zbY>NKLBoY*Lp2Ystd;wL=EfS^1556#U*CY92djaOm!2#R<vF}qc{I=7EdDd_*N0U?
zXGUMv7#*GcSlM)(_h-!ygxkkhEEVhpu%Z`H9pZ7;3?1GAS-y_YKf!vHE<Xjat|{S6
zFzf0D7z|-GQ?M$OrO5&bWBm~c6XC3<QlJpQ`gkQ2B3Z5zP&moj^f?rwSRYbECz>_0
z2jh)lMbbMgmK8#8k2qFXE)?QfmrxvKotMD+G6vq9VjcMqGKs9UJ3&sfJa@tGGpqqR
z&nK~*4ni@RRZW#KDXiymF_^QgcG{PoW8KdOInP>7znN6l+jJ64W62zWlFpJ)6f%S5
zy$2|nti2Y9TwvMJk2H&QupOAzY}TIpu$04kY6PtpStqEzJePGk4T^cJCA2TS#PXd2
zcbS#=0qo|p&e7|xfaOccxGSt@=~P|FvZsW15$hYe8BxrN-T{;nRymc1m9o0ufJhlj
zPKDCttljj4UuEsx4U}tEmMxVaTxaD_Dx`w7(G><OSzGCpdV{r_O1!FA&(j)L&ALV9
z-ZiYjN8oO<uF*W#vi2T?NF8h53iRD#eMnh=+bp#fqpxSh&>^OQwL}cAk>xM~Lrtt7
zl^AX_YhepeT3FV<={V5JQd|ey#`<suq@7it4RVLYpo@MTtgnUv)5+Ra2*n=O`cKi=
z%UWg&(#LWgLSsKGvIQsutQxw@ewUR(_ebxs{zvh!LDri25E)|Ge1z#9X06)}ZiMwp
zG89Hx*R9o%xz8&87%q;n?)1RLan_gTF?$bKF&7{+!CHL`<|kRrE73Q_8lx!9G%IF3
zL>{tkVhc6z5$kE%|Ie`0%Q4ThtQ0$d9bw<^1hHi^YT=U|+vI>D*|XQZ1=k$dbx#7?
zk^RLC#Xyd-pP!3XC-%WDka1?G7J<01e_jKFuIxfuNZi=()2Z5>J+c~T9_+XqQ1E1j
zS-^R*zooa9H#>rICqC@QD46KW{w)KIe(Y~60p`yZGU3cIHjB2e0ql0F_&v_%-=;Wt
zAUlU%TPN7j7XTW>7SK;VnC<Qa*FxCdpTKS?``)*}4r4o}VD#ba)YWh;f{pk$9z1sS
z4Ej#8D=BOl#XcSb63u>ru7$<0pZW+~EZhDWK*zBi=mitcUcME23G7>W6bC=W4y0<k
zMD~xgjGkt1qEq!5wt~*VN$h(S;F8(XFT<x4_5j6v&a#W>opO%d@&xRjXP=k=NoC(g
zL}gwYJ2wE9(%DZfhNTSlnsP{Hvfrir{ss1lN}y!1r)l4s&0axqVQUT>VRbxs>}NF4
z$Yr<Dc=OoqE75t0-TgYexXeDi2#xvd1Tm(qfX(<CjaS&)IB>0y-A)%tir6u<RV-#_
zHlneNy{HL|<?M%hfq9kPPHW6H_MbeMzs`Qb4(b(bn{sfKR<<KmxZGfiUV&&8d(SZ_
zR<n=fLZgQ5eg|IMWG`C@4{O;6y<wt`{Wd++x7bITFs9pVCG9Hf**;n5Yhd3Dg+e2H
z8J%OB*n8=zXl9@N2o_q{XDMRd%6`TG(#B3;V@U06YtuuZ-C-x7CT(5^dlPN`JK2A|
zgU&AY55K^fZng^zyNCTWZ6|x#%Sxfp$5v6rVm~`#5fld4|4_2@E<24Ps`uEPuc2>{
z{V%;AhuDgIpbWEBkAsY`Gb4a9%HBzP#QW?j>+?VxV<-L$6XWck7C_?xd)McXnPAU6
z1++=_NIOKP*j2Q{o@U>g2FyeDHq`LUd&F*D1-mosWC{?@vUeNNc!cxBQ7G7QY)?YL
zj#EDY5A8XdDfH~X;d;WZBgb3_k)xbsKdM7?;!Kz!>de_rF)kMl??Vt*j$bMo-8kGQ
zf$h#&PZd)h92qU`o}6QJsQ2PDUj*^yd`GDeAI=5(!}@ZT(VFVVS@b>Z`g82*4#hFf
zkr0><;4pKcew<TB<w1d*7rH10a)Q&<jrj`VuxZy4%z4cflMuqGnFbfic|_$wVVn*0
zP6+3$_z)z5vv3>=k(_P{?VaRI#>0FRM@a<*(VXO`F+nk$3A(Kx%enqJ`r<gha6#fZ
z2WV%Vz_Dke?=)u_Hp<p{XE=70a!TS1Q+y_w6Gv&z6wbBBF;QnZ?d1?X$GP}A26~>e
z@h<dJIfx<RQRA$4g<d*mK`RE6!I@kSkxb4vl()XXsiumJEY7RjA(G8;6ktd>oYr4~
zd6Bbd8BlULEwo#)=5d;~LGcpjAnjo;bCO$tozGdk2@V%<iao(y;k;LezCw=o*Wijc
z%hW(C=3H0+M@u-@>8edB$D<3D$~Y-^AX(0N{12G8$|*Ysg=?JU7h&l-C#eLO6`VJA
zK(CTBPNBIQR*wG%pjDi!H_=+n`SxizQ^VQyJjhK>z-1`ba_neXspA}_Z`j`AWY7Wb
zHpim_2J1O<DRj`ld4YcNjhtW;`kFW|Q2|sl=lO1s7EbWTAg!GBR2AIDc}VH+b`Gux
z;<@8kUpxSf4vy*@80_S{x)Ba{adfd5MK?$K1QdHXb7|+-%h^of)jrP3^RU#<>1%}K
z04K%;>UTMDkKo}w&Rbe=gB(d6M20x_MsUNN3JTYca5k-j!YJoB#b)kv{`vwUW1J;c
zdMAx@wo!8W0q3a-$V_lz=%U{wXC+-go8ov<Mr4}vh{Bu?IbC!dd&C*Kgi*|Jd@`Xv
z%lVfw7)Q9hH$iN<r)k4#$KCJ;e6r_O2SCJu8}9_pk?X<6u#a-B^vZYQ%HF5*pEI|-
z5oj)4e~SLOa!aG2@5WWrLg2~Weg~uQ;*O7_&zt+5J79dcQwr$$a#z#V$&dRlg~<H5
z`yHTgjQdIlNC5Zc?}2ih`yw5=0=YkK#Q;xmw@WdWAnvws^aXR%chdedg!?2V(?hxU
z#vv2N&DaJmoI61=vIuTF1vVqOsdN-S$=&w>xF~K=CcKE|_R&#1hPz}CXtCULw9km+
z26mz^o@-CB=>+ca4FEgEO{8~cBKHo3`A>8AcmU-L_gXKle@Wc)FT&wu?g6S$OW}rA
zqVp`bEDNCLxPQ@Oc%Hj72KuSoYA;}?aRdC&m(C4%ALcW-!#aRwa;NJda)EoBDq*v@
z3+Xw?=7vyX4tL=(Sh&c&MH!4-ZsmJ0l*gT<FpBjO_s;uhz0CEeZzbe&KW_yo;6_uB
z<O;V$1WSe7WfWH^;znj*o{PEtRIO9Ob)pw?Dfc%!cv!~GJ_?0$uHRm8SGh779KFW1
zS%${z+*~RNt>A{;hF&GtK+Eq9?zZDlud;HR>Go1J_hkyz)Ntp}OXwz-<p`Nt?idH=
z>$pFD1d&@@GX=PAbARo`c<Z@EbnCu>yXz1n8@VjHG~C2p84i(V?wqf{wQ!x@#jsns
zqxYfS#{E_S*V?&hbcVje-PjEE4zAU66-;z;_a#E6i@VJP>~3z3Bc`T@>rV!IxgPT&
z(#KWPC6|6~<(Ft2;O?b;{#|ZQJ=`ARZcIeuFxTb3HI93mW_FazoC4T=?v76Mjd8QX
zp+3(2-~;&kfP0uq$|ksPSSeyU$z4i&%qi}7w6~q+dVT<d54n%g2J#X2S-SW=!}a|i
z$SjxpCPa?#Iw|yL%e%h>qp;(ZMu6D!R#gJUfwz~^1dcox+8!O{O;eeU6K@_p#m+om
z3Ou{;j<ulAm6s=_=g*Dz>Jkul9;XDvgSU=$G@iUq=oX$A?>+j>dGoeV2+oIBOB+vL
z-UF)a_T$;C1e!lDoU+Nscs=x@3E*{9!P0Tw+mxgY<ek@{?*#9_35++0_t_Bif_ZI6
z@P`TE?fxI-;6iyZ9LR+6478^X=RHlY;0WHy72qOyBWuuil4qhZMe(L-pApSF?+p^e
zYjcE&Se_s4{Ni{ubmEKWg;KOSf%g+tBAntiP_bSjk40ym)4U|g@}1!YQfM}b$G{K5
zIxm?Qti?c6cw>j5ahA732bgobe5#i@&-<1Vk*U0ki{M2XZ_W#_o6dV72>Kbk1N0f9
zOy0ar@ZtjRm=<1S@uU=s&*s(dg{2(cGgLcpk@p-`-skd$R-iAB_s;w1yTq%gK%ez8
zujU(A%IEFB0{sHsqU{*y72d)SU>EX^oq$XcPxv<aih1Wg11aIXLbVp9ycZ{cR>lim
z3+!^9_BQ&i^70eGUE|sR3KQ3Pmoz}B;61+qq>7ijA8uFkewYV)HM}?v4C$tow=)`w
zwY+v(BkOqmRHT24SH^_sZQecxNIfs18Tt*p1ge~B<ZY#j@Fw2jURY}8RZ`rwg?IBe
zh_v!nQ1x{i?|n6}+j%ShyB^8=?KSju@FwWh(8<gH8X{f1)O6@|^Q>P{`n-p?h+^)&
zyw$W#>f;><z&!W!4j)F}0B<|(bno&)8sW@6UT6rg2YC+vLScyK_C359=B>zs$Oy0V
zOZ1KMw$WYM`#c@3W@Eg6$op|#-^T!Zz*|kbjS1d36-7?+`m6^q-YK4D4X~$qe^VIs
zA@7z98jpAlbRwAH{Y-I%S>B0XfOdrcCIzu<`74q^?D*S11)4qIgHp5(eBB;!j(pK}
zcyW}kc^(Q*e3cx1&iuFkfQK&pU8ex%%8#bvGdKRtEGs(Q`PVLj_29?TSM@ykwWnd;
zi_fPLT5tYKv~c?Hn|Gqmm!C)XR{i)-UjpaP@85?>IL5zWf-?d9_y&;U{5$k)2l79A
z4Sgs0Pq{)pi2o6lxdrn@AEPgXzv2UMq5LQ8DE=A7@BRX!;rtDBUXI{@*9tC@|9%qC
zPV(QPP;?Z3hE5I9{96qWiQ)V2z+hte^|UjO<EQ@@PT?=7rz(NJbq>fWzA74nNaS1S
z2y&X=L9zNX{Lg4-p2XisN9kn#CkTNf2hJa+TBo!8UJ5&<^6S%~pT>VG0s86uJ-0wI
z`2V{HkxYK@cj&vo=h73G#V=~dTxRnxc>z0z|F#XtMgAu}Ah~=V6@KLL=bVH2OMF|}
z3}5E2qyTR|zlQQ_1$-eTRjpU}1JxK)AwTaKm?+}2D1TebucA0g34hfRkW&7M!{{sH
z->1|{IiGz1*jM=-x4>QFCu~9Ab$-x3xK_b0;exB==hN}?2LBKpO{@4)x`b5CuMuD@
zHT=C4x4Fr8cp2tvt^85?$=C5Cc4PFn_}L8rz0Eh$;#kk0L)9}4d^0^xjeLh>kS2Z|
zAK1<O7gl4SE&NKli`2@GqX0%5U+Dx(?fe(0X7&z$-7@&p!T+TYq?6zC7WBIKNo5e}
z=Fd_du7_{UVZm-MUwscUef*6ScIxMQ%}3_|e=o(2?(*wb0qq{&ZvteHznY%LA^yl4
zAjABDA%KqX6Dd+N%4gdG`#%3wIrPT(Ye-?7Uq%<9AMl0oFf_p*NCosHzhW226#p&!
ze@;Aj{KZse_mKZB-9>uDU+W0$8UA~(VZ5_^zcRoa5uB#mnYMzt6+p8S?4eD#z2LVO
zq30l2Pf=7y!P-=iqk<LBVk}Mq`4tdn!J|P;kc+@?44AHhSN>b@1oQRKa~HfdkIrfy
zf{1s4<|$aU9nN?Ony5U$TVNXu86Ux+pJCotkXr%bC-`_5d<qZ@907M+kWTO3K*8!@
zG@cM-Rlr1$;2+8&1`E`up&lYwMtjpxL4g5Ygb4;k7(}=r$sHs@5Zp)cmq>v<B^OQ#
z+^G^TN-#yiq-eo!S0NK4Xg32bR!~fPy*R;36ts&MJa-t_34#zhFrE^qC~B1`*#9}m
zX~F0ZaOR94fy#N41lOZ53CRK@ZL3lQ?rVT@R&bKuo#zDmGV%XW=babadk>1Kf<G3*
z{WQU52Y{vvdbU6#Ltvq^Wu~BdKDY~l2{Ev<1U6%U$rjX84m?L-ps>+J!BPrt<_Z$2
zF;DQyuh6?Bu<ZxfWq}_R0Ot!nGs2kyLG&WHc17@zLU-0eL1j0viv*9p0b4A%Ky^<g
zf-NbqR4Rz0@K2c_=xZ1(7sx2za#gU3>Qk=?D(KaJUBL4|UxnaBN+(nb9B6lTLtt-)
zWR>89-4Ll3eDx|ktP!j@4xerc;-5lat>CS_FjQw11k$p9OW;Twh1-I4X|P)_$aoGW
z8UzL^m24C=JcY(4fssxr&4QH_!EX^fO%cRafuAGnwh3bQfwT*D)dTd7U`zzP4#6FI
z{5u61lpX65cv5z{Tkry96M6*he}nW2thHRg^a<WQ1mF4v1D^tWK(K2YoVhDlS%AKK
zf}M1mU{LVq3mD9hz%v~p!-7moL5&C^>;W?>xHt;)_XVyyF_tmG=d=}>5VTY1d{U5B
z4KgM8n~TP2K~5}OdnkydS$iZ1vmSv{GXfM?<53fAtOYqDOsRuiTVZ1u6zzoTPr!t|
zu#w)j4#NBC;2edUq9AfqXlTXX$4OW>0-v0PODVkIB6O#HtE+H~@^@}RB_Am6LXX#>
z?jdXlhJvT?_irHLCESy`2Gm>lR~x+W5q{(i_kD%W6=R@&!e9&f{DmuMH9aQ0@)EcJ
z;bA(F9~Tx}0BE3aRSEh|2+#S=@y36YqoTx6;VG(c3KPyP#T14M+h}7DAzbwye2ElF
zDaU+LsGbWhN?1uhl4#+lZs1~sf6{9zR@j>Z5+^L(4E1;+uMh4f2t#Utc}lpn6kMWE
zPw%DE!q@VkcSd+B0Ru}CDy>xel`M3mjX{bqi{6=Mg=32_P3MHBcz~W4+ED^4RrpaG
zW;so`tOSkeLgoSZlp*~21*m5Vom+u@LAa9=Bw50hzo0K$_}vH4%Ms3ffWC{uMJAA3
z;i6F}<O$a)Fj<#`>r$;Scv<-A24Lq4U!>h@f$*<cn7<<2w*iAG6#hoFK}EuKRG3{X
zyqN>g65$#;Bb5r>_JfoO)u#bkE{vva$yMP)+Ll}sK2HhJ>p~~0?WquQC>~uY49^7E
z4dKh*0IW)A`wrb`uNE%a3g2pk-_p+OrchlEnOfm{bR(ipxbtuLR4+V5%XNd$`X?kC
zh0kPzYZAWMi@s*zg)Ja0!hH=OtwIMHOPes^Qy6R)j#GX09pOkkyyy__eHJ2}!Zdo>
zbqTNGL9@>57H**_?GXkg0kl_GyAz##!m?0k^b4y~F{J~-;iZ7ND?I-`T)QV6q}dx3
z2JOH+4+)(PLS$GNx)|ys!rfgkF)C!xJM+G<#ut5KLeVVx#)Z5#`1C+1qJ#W|Flard
z%Q`7sO8fgM;S&b|IxP&PVCX|(=NTA$Bs{Pd&ddlGrh%IkrcnO+i0J(u*tHdHr(1V+
zqS7-!vloR@Zq7keF93?8D2$fPqauev5GT<i3U)b*WS61fBC@7H#8qUZz>=F)R725I
zchSiWU_C^O={4mkdXEywUZU{FV9;CiCIv%%M2l%#<10#u$0+<nU(-cke^D>R-;ar2
zI*7giQTmHeI4;Un!oxsO@J)c75am+!e~^eB4@1EsRsgsV(I)ylMX1Q?OBXr9MEO+7
z6)xIPhSmsC`xqJ{MZXP#J1N>tuc;`}Rw}}Y7R5%xZj5Lto$z8sfBHZqPIP-GCMaIy
z_XG42L}o4ePKm_yl1vn}Q<Uno$eCWwXGG7^?lVc${yMm1(JgBYWKu-7|6ufIMQe}1
z(m9bI`F39PC>4WA6-E35jWp4>0*IuGLe|5J4AEAqRnHXt^a?Cp5b>(O<%lFdK<}c+
ziQ*Tzq9vQ)Q=X{h9P}=U<TXIKEb^`d$rl~j1+xXBb5<)Hz9M>w*2_Xs+(DofiM~pM
zZ^fcrLXZ;C*-t=9MJp3vqD-_v1pRW+|H=V+RrEX+D_s*^qF~5%(Nc;AR){WNhZmJ1
zm;XN1Aqt9zzg41Fn9!>hVQYpbP2~Il3O7Y=&2*Bk6?xK&v`%Ds7mBw;-S+V9wkU~G
znf0Qy&mr0%x@m{LMp0rbV46h93FvDUE$6}C7SS7C5NQ>~u7*gPi2XSHZ5Q35x6d8X
zxp9yV(X%74&?#C>=ZP-SOLS=M7VW=CH~M-+|Ip5<S2XiK$n=R0OEI*5(F83@1ENne
zVdAdnvE2Z@C$dDr?x5(sYZ&&BsB<UuhD8f#^E)DvdI5V>)cZB`?u%AY{BTS(ln!oO
zv|$P;4@61ZKqf@zo=4xLsNpy`>y*g(96+Z<Zt-Y+DBAG^&>o3uW`I2-YN250tjKp9
zBRnFuQZUq3e1PsQ*@=(O1!pf_@E$k^@!$e@=qP?B7UZb-iT^f};xFEZh_m=Hsugz;
zZ_I}US8)(ciJMsQ1N7XV7BBn~COpKcem((9tOw|&=OcdpceMG6TdKhMiN9P1J%6zy
z?K6*wPx@n;0>pRb1M|4}TM8rxihJp#b3*J+Z>u1&`!CQ77C%lUR$<~4`UY6I`0sG&
zMTj{Z^hJt4UJTDpir=N+Wt2F91-)qTRqGcRb&Pm&9%e08d_Mp(apKu5n1~mDO`p6-
z5G($HrBmXUO28$G_bi5^r^V_SkTc>Fv~Noie@r#F$zsn=prnZH=zw=tyz_0KoD;uI
z0haUPvlMAa6^kgnk|th6A-;66B+m-pGQ>SMfSoCR|1x~LAeJnLMwYl<2<&X}6L(=L
zM?6S{NEgK$>5!f)4tN?0dE$y!Vd;`MoRSxp#o=^iDqmdT2)hMh_lHowBCe+Gb)onf
z<RIr2i8HqXtXO>SFNl<gfBKB>x0Z_MZ-!!-c#8Im<>IsUFn?7%k`Ik*;__UO>*AM0
zP^=Jdr~+uESVMJNH^g##cu^&OvJ!pO;@h@xrbgTri4oouKcJLPt+-?smg>Zny%4!2
zE;V9+x5b<10JC2FB7&~gc@5&1uYzq92eKgAB%Y;Bce6Nd8?al%bLd#zDt4qrxJ``z
zg@7kbTtz>mJK`1!Hg$;YKZe~-@$Xc$(<L4Yg86Q-l1{QcV*6$&^oqSH5!xpXdLIh?
z;-yvS8xSiO0@`|4JX8vqdt%QIF|<MPkA;|oA#v$%XdD)A{u5+G9R3(IM#aVqxPM=K
zTMZLqVowpsxOg>H3qKHRXlpkiUO_*$N%7S_G){?keFC4R#W61c<)OH<8sw4Kn{tmw
zBp>dFdE3V&FZ)HFSYll`j6O%nB063kl?+&5$Vqaj1tQK8Bb_u{B#9K|ah1G7-z;;J
z=qq5)T@pyAR1ZlTRRDWRrnW%cOTu7dw!9?)RHf!4`5_3BzLL*qkK`w5q8OsTq>2jC
zj!E1oq!1u+v%U+M<B}&0Pz;m^DDrhevhGKWB}kI73L3$Z8x;Hqk%T4!CRDQC6@6in
z1WNOTOa7*+h6u^ybdHXc?AQ#+lajkx=!=r@$irw!=&OK^k%-=cWUOSs514V1)VIOK
zOBN<rVK71RW*SC#O7b{u*%Kwh+2}ki$!Ub8Gm;p3FC|GhlqO7;SZEGYB#(aty|WUp
z8^As%DWjy{dC7S{kW|U!Qh1Rj>8Ephx@7A~NM=a#X`RfJRDS^I3ljUkfRZJV22yw@
zTN3sFGC7j<KfwG&Nro0MxsroFVG{Esw^IOfNwWDg`Yub((oZK}Qg9Or1(Mnra91Sj
z3V>E9VR%BXNb-6%EEP+Z(>c0C;(iS%rIN2tf-93$tpQlMq-Z(7u1ZvF`pm*LNf;gM
zu1mhmgJOk5poT`J<R|)a{S8S;4JM&V!jVIyS~5!KyBf($F9GeQB$0M%wUR&R7h5OM
z<-wU-l2db`a9h$yk7m83x(Hwml3NlqHcIknnQfB%JOF>2C3`Z_XKj(#-GkkB35!mt
zcO+cemUKv}hoRpoiJ?Sjm*iO=h;~c<pd5IQB>xB$dL=Jx0qK+6q%zTd$(kZ43`pcu
zWOrBc#ZC0xlekgrWl+*-gvgM@NO75A$<mFG9Fct13@=8ll2@L?nC?qvlptf0U*lkK
zT(a{t$OFk*dP`17-ltgAq@;z;hf|XFI>1az9AhE!P;!O7r}RjYPgiwkBrE7v)2!t8
zS#U?B4wMPBm9BCCw4Jn*>P+mVt5<?^kaE}%ag<t}_0Tvf)h-99lXMFcoU_zO2M`zO
zC3;!AN)OD1`)<+*cZj%4OPJ{MkbXh?3Qy_lRS@x#Znc1TOTVY8X&<Q{<u!bzi|DuR
zCtc_WOn>R?*&xTHX+jJsKx+IOn8&5hSn0hQD4j<cqZ88I^nMGHUZDg*ur!rUdm+*(
z`g}*IlywaT!=&#}ok_U#Nk243Nbd{bQ>64&x<7PMT1KmVl(ds(Hd?Cjgk+3VO;32N
zv^xww#Yw-S!mxPhw{$j2kh&I7(*Bgxdj!~tQrE{ZL#L(tX;C^OJ?MtMB<TSPStUzr
z-UgQ<HPCI<v(mpQQhrXloI=LurS+6^OqK5c8P23h*HZv1UD`yuxD4s%wAas+?%o5G
z3(^InP{@)t41&v+o_&=zWjWHUHn10^OU|G(SK2}W?>wm!C9Ez<E9er(W$DH@0CPoJ
z9Ef2TN^jFOh9YVHC6HoiQ78seA`POHOR2Q?Du!Jq&3PLr<<gcC^j(#DGvV4b=}Yuc
z{OeL>0vao%FNrC<S}AR6z|`E3E^ma1DrpJ*uBxTQw12CScDn%Pru5zvuxq7$`#|cX
z<DWp}mh{*ZL~cvHuK=xH`dB}lX^<|UI7g$jY%$z!k_!3gYnHMoKi49iI*h(n>D#y9
zOq<k!K0;@0mxfegpm(GeI>2;Dy*>cxlq#1(ze~D%7f81>gtm=6(h&OB9KF)~+aP_?
z6?Crdm;N&d>;dWL+tGMey8dHu_oPfCTpN^np90vBw2}$|hNY`%Egq3}&`pL>=~`M+
z?^~sNkHN(;X=pjn#-&&2`1L^QLOY-dDZ341Qffo5%PDEyFvzrY%~2>kl$L2=>5=re
zHvu{${U6=@o0VFqYV(LJSOaWZ*~_=V*~y&f`LmaKQSQz`w(Ls~N7*GR-a0C?rY{C{
zk}ac+iL-1!-H33JE!+sZuChZ^J?SQ6(7D=OwvjT-9x|WRK=YK9(&pDo=16BjZ`u5-
z;Cy6u6eI9OAI9P*({upSU-l){z8sUiPpe^otc?=u$7PRu!cd^>OKUy;BqwCf*#Hfa
zInecrV3{Xv??YstjzT6>hA<-@JlP^wkZ@T*Ei6UI8tC#?q-@g#m_I4=q9j<9>>C&K
z#mfG-A1HCMPlQm9mo1|-L4xd14eXwhrL!=IMA=R|h@6(SNUdPc$VzD4O_GfTK_gif
z{|huyWF|VupOvN4A^n`};zbPYyzB?6txuKxM0?sanS2=xrpxM&0wqHhMX`xYS?%BG
zyC6$H0?aHKgFf<-Eqj+<emSzgDOY(>)<O$GuIwifmDl9SQYi{@N%qwfAeUuN{0fpU
z`)UY^1u|I>(5}dm3*kkftWS!$ERuah*I$ZdzIEs;k?pjHrBd1J0!%`g%>N(gmCH(L
z%XL+DuLug)WDCl`U6&oFs;vsyqC-%qloetsam`eAjQ;3VvMJK2mW76ctC88pLG-5V
zU_U&qmCb(=eRZ<WGvNL$S%)tMdRzA1bFfq|`*t__8f13#{58tV^r$q+R`G$-EDK%;
z^%mLwKFnyVtfvnOZL&A16s%nqeH$p&J2JTsWIANaXcOHjE2i^7m+Wg3^t)w$zW`5r
zWNWD&uU8gNS%W^=SN$;2FZ<$Ypbf~Rf1vNK?12aL?#Z6}49*P7WVz@Yk`=CiiDB7X
zx(qWS3l@Nk%KoK2<$c+{E|4*+%zgprxa@CwWFE+te}tKxko~w7Xp^$G8o*4+{_uxu
z)3Sdup#M<zHD$&h$<`*p(v0kxl_0Y+#q(%9BA0&v&Q?A$19dz3N_sEb%U3P~aghJ^
zDu|=}U;@CL<zF_ykc-^9c?m>a<+ZePbdz&`0CAT`&c#4I<Oy1Ep7QHd*y1HWM!#-v
zxt$ayeB?1{5b>3-iv;H<|C>I6;x9k^1iUyVpX&h30QpP5!{6ibU0cu>D9`y53Mb^Z
zsq!^QZn+4|V0o}#c=UYh%T!SnDmTXfD@>lZ5Wk~v`GFP~kC4C92QE^+cmj|o<*IL?
z7A3!>2Nx~3QnorqK0FP`Soz;FkU068TOjdr?_yvk$nR6t;VF3^orx0V^54LnmRI@1
zqcielbfYgx&ahG)TeAFQ4cHX<Z~tHnXXVlKIzA`21Y^?9%YPb$YpL=*l-Ev^ho=H2
zUH<pm;4<XT$3Z<)erXyC7v#Y&g3FS7(xt&{`Qx;U%aI4r7T}`X*9Si3%A@`UW}f_&
zYN%h5A0MSX@MU=?)wJi!`xBvGATOX_`W5*s7j_Hfxm0ajBu}OjWwAV!BB&+u_d20p
zDzEhicA5OdI7qqt%`Y*~tMXHCq3@b}k_UzBa`*F4uaL{`!BC}qf<jd{<hxH|o~q=Z
zzfNm#wR`~u&uio_j6naU`~)qDwQ^e{EY-=66+!Wq++Yul+wxzZfTeo*xfjvcAYVs!
z9vkKJX@PB$H*N&iEa%e4EL!BXUxKvCS@gSalaJAcpk03Q3rzDJ`E%#d*daG<r8T%y
z{{Bgr?~*_9D#qI_e|0X<`s4}UL8f0m6$p(1IfpXRcjde;aQEcD(>JIF<q>zFHzdzc
z0DD;e>@*CH$TR6AIVunO7wY%rT~yIHCjZU^Zd^V|*8?8NTj@)X6Y>w{VP>q8^1)Xz
z>?wHxZHuPmV+Ck^DF1`5JUo&gVL)R>zJ^w)S@}zJef)@GJ%s^m71Mm^*(u(lhu2<F
zL%Sje#bP=+J1Q3c4QGxjqG?y;q-du%y|be6Q((F%8nQrK6(wx+xmgwO{tNfr6?f-j
zXdVjgG&(&M={*>Qmm-J~%ifBZ<3RIKNOnQPS7HApyzo=3rtE;f;!8>;A5#=ZK|Mg>
zwh-#a6@OByFi`Q~6ckP<Hsr#?AVm>fhX_^}Xv-g>z(3T(bEmM{*MSXFbiDyKT(O_Z
z*CP}uJAoak(D=cNlM2Hm8lx1e&HyG_F`r_2F^YKF<isj|3P)d@;_P*B@rqyR!$%1U
zr8BrwiVx`FNL19(3;49chw2W_DE3m6CrKfq0*hqDq?Ilrr6^i<p!2LEwFTJc6v<sM
ze_jzy-(yHsw2<FviY0Pjrz_aBBxWf7cmvp(ilbE^7ZjVHfI^m{iIR)iiYYpg<|ue~
zF?kmi+bP7Ht6<QPFi(-Z8Yq_(EGjFxtXMrviGh5@ixg)mP)yP1imxb`?LaG3*!yA<
zixiV|p`chX=n2UZ#g#Vbmnu9Dg1f5ts2<!k#Y%cAt}EtIxo(BxiU#H@6<$s-aYK=$
z16QSJrmG><inGTcQlnV-Utm)4O#vkaY89*J0j5sz`+0bJOEJxY!P|-@V^FMDm?F^F
zpb%5#TBBm|2tb<@+c#rq&5B6+wo;2?&LWUj#q>4kwJE;;1Y>De%-ILbI|^SqMRh3t
zR}8&QMG~EIyA*q<prc!HXDvN{J&K>{n+v^)8<SA%Q?UC%`W4OFpg*AaH3CDst8k=)
z={?1Ks=FIhWWNvnAw?Sn9)=Y+DO50`$fQb;QAHQMweBlE_JG@Cig)SPHLmb5L+^p&
zsV^Whp*Tu4YLkkW55kajO7R%UOe_BNfXqY1yeK&HNO4#K>={MmXPB>9MHb!^^NuKE
zD28LJ40#gzcFIraxM;5&qyVmi@=02g9F>pJmglH4f$Aijlp+7XZD-~0=K$@Ze3zC5
zS7kV5N8FTe>;va+RW3RNeGg?fRVI2Wzk342OL?LM`rgX-U0}&aIYOaVU*)<LK=V_I
z{!6_n^CKa7Ot~lkFab)>i!gs&`8(|;1C>r+gPc%~(GwG-yi9wmVCA}-P!Calx*2_;
z%8%mUMVQiBO2wMt$`Yz>iBJ}{gNszU%s}R(@}*NCQOdnMSc+D5?*WNXE}@89tg?uf
z;y7gy?XTmN>K9=mLD@-@a7xMZ$9NN!_v^u(SKi(QlB!(bgmI=Ri>QS7f-;M84p~Z*
zm455l%A}tGnx|Y%A&yJRyZ=2M%3do>lq=gQs&-BJ&$ke{uJqvntwNbgzwS!quk`o1
zp<G4R#;TMLzJo%way}iTYn0_wLwr-YjN)f?%Kncbc}uy1ZdBh^uAoJ+Ug>&-p1%g=
zuU)X)sH~}gXtPr214}K+%nXdFRrw_qd$lP)tcQNPayS)Shq5IW3Z2StC?wgXoJ$9_
zZlwng3O&m9f1%#1+(MJrr(A0bg#l#^ZK3Zff1<e5J*8g&`UaH+%jo$VQu<P+bXd8a
zqNXFt0@_NCD(ij&%zdSS!op)pVHmh^Wfw(u9w=Ap;pl|YPXM1Lm1}96Jf*B%4ep`x
zD>1MiDWfQVI-`8P1Cq1KhXX)4qB_Y1immD;3Paed><XTEj4{ta#r++la8wo3PVuNJ
zjCM{=sxyA4&#<g-7Gj(ps_Zv0Ku^`VU*MpZDuRMHKB_Ae?e|rUW&zVr<?|&#{8bkl
z(0EMsWIITJYM4?TCsYTh<~T_8E1fNZRXdd!Lx}4BcjyaMZK3+WFxA_%_D8CYQBw1y
zs$LC|DAi)?XK0O8jnWOAIMr1nI^$LQyg?FG_X=R}wCaQJVg8ItQVhuyl?zoso>e)}
z>FJzmih^TlD)Va~>8jvyh-9c*Uj&z>@+iZQvQ<CPEvOvT&VK-wr+Sk9x|dXI--Y*=
zRRa$w)0(fUje)@e)$6tByrO!V2fvF|KT$1TiRxk!xKdSlB>Ku!vEjfjSH<py{#Df%
zPr{iB)oWC4RH=%hyxa}d0m^7qspbn|zFM_~DluwQzU#o%sXFM)dQ0^i#ba-)Cex_^
zx>41`09upElj@+GRRvUg(WctF6b9Q>+bJk;M|F^@?>bb*Oql3Y&EJlJcBvN7>UmGK
zAqI_us!uOKWJtA*A`HW-BC6ONQTfn&ZB+G5FTn1rJZbwkrpllb&bVszr;p+7{6JL_
z3jGO{=bNxQscNG9^pq-;_CwREyDXqRR3%U}`jP7KIWRG!>U|GnRuyH7#v^L?Utq#k
zT|_qk?9@H9udr7uegT++I{XMk9M$)3!2D6Q>pN(4Qjb!!(^-vw_lCE#i~8Nq(dnwb
z6N}NisReY9c2{S#!n}uC=?-j9b;tieywomBpy8`7iiW<QdMmw_{nhKTF_>fO0*V_1
zsC{eDcU;{>AJz_3@Ban{PpI=5=nGN@z5*^(9d!|ohN*d!<OsK_7g9VpLhX}@&Pesk
zlzcv^ev}L^qSSqqR*6=7EQUyo`kl7`8mn%75{+@{@lDW=S7$wq@g}IZ--Y@q_4ye5
zVG`B7v}~SHcQ1iLl6rnHNV1xd3WXH)Th{@7R=xQ=M9!(L!n<fqQ<v-pOuD+22`)q3
z9SxXFwP-OcT~IHlEp?W9k}@FK>Z?cLOpZE`wwM>y=15FQuKFeVUF4}>e;z28)CtQm
zU6<A0tbmDp^-g-G3)CYaAcg8KN-dSBKc>KDsrpT824Kq6+kG(Xa&>4FG_I=W&?hXe
zsiRLp<GNZ@0_+O)75cDgrF!jZkQ?fDT2iajzm!A0TFs@ia*cWwWvg$ha~(ly)f=|L
z(c9|e6gX3_4vqp?gZdo`MK-Df`e30+y{3sGgstiY-C*0)yJ<~rSN}*!!aM2>wET6b
zmHjZ^sdifk(xrZ%uAp_RrTa0ZJ?isxV(L|Qo&)JqXZEA9Up@aZm>5tmuLa6o_1E+w
zy{G=jjK*R0Bp1%yS1<K~<e0jD-;;R$#?{|kLgxeZ7sb$+P%ol5+N8Sb4Op5|zqTEH
z)9TCg&V8t!4MyW5b;K6v&#0d-MdPfxl!Ljn)12Q9Vy`*s27?ZoYATIz)GVa~=~2x)
zyD&~C&69Kpbk=<C4@?)0TM%7<b=CYzZ!b5^G9^IWHSX_%^U$;wK;K(aM-ew4&1@(X
zeKkv{#>`I>M8$*tn&tq29@Bh8A@V@Y4^PAH3C$n0`UYv9*#Q!)$(aOLh^EgOT&O08
zW-UVVFGUz4HP@)<&w5gGg+jkknhp6d7_F%(0vDq>=>^bOjr$^Sahi9`(1_PO`wlb`
zG`~aw?UZJ%H^!T&IrAL!&TCF=hDfUBDn*skG@nt}JzaCo3w;@yJyw8aYKH#%XHS}%
zOVG>G{COE7*;b91K1P(IIl2+#qNZm9NUr8`9X!p`M7x5!r1|y^L@#T$(k~%j<9ZNi
z1)6LQX7-9El;Y5Znm_6Ca*<}$5{$Q4lT2aG63wS;VX0KZqvKGS=6QO%muq&d1IkrR
z&NfJ1(^wy;>b>ilIp1Sw6`I1I09vWJMEipqn)pnRDh>NBn5fpQZG>WtrX>WUzp43v
zZs^x)lBf)!PLsg{_ASkAEgZeA3Cn`{dd&?=5Hx6t=y21has3UXNwa<{^qMtRdQG-y
zUa?NWe5-~>0i`z0c4t^>*L*-#R(CY}DBRMaiKla4r{*-Jin=u0Qed!K^X4Ov9?cr6
z=;+m~zY4BT^VJ9NzF#A!&$13^uKy1TcQt(!Nxi4(6@wep__soGNMrGZ$S@RW{TtET
zquW=bnhz+Rd|&ew7aC)lbz^88*R)eO?SbY?y8Jw$aXSMtsgYfW<dnup5A`FBJ?-mf
zG#SrfEVG(1I+EIHn_h*8z4jDUqd903`avAExor?Rstu->pOe<-XZiq(vv!PyQMhQw
zpTIy}wSMa%>ZV<^95U|Ox((3q(8g|p2~X{9%EWtVHI&2l*0#tY>7$+f3dC1?p$-%5
zryW}a6n|~^R*d(!c7Tf60<|Is_;f<cc^)GR(h5&QGFUqhM`cSPT1F!DL$&Wdfz~i>
z|7Va1*UqKGLWK4R1-T-%Zm$9Dq?Y+3`l7T8=b<lJ`vWB{Vzk>-=!?}l(9Ska8>WEU
zr?j#_NG58#Xlr^}>rJozGg{qS7(|k`W(*?9+Rtq;2y2RVa6UxOYR^22p`Fvda0oKz
zwIVt@q-tL)hkly&>Q~^>wVUV)Oon#ZW01_$swd#u1#KK%GRV?)(adIR^^{o1(H^V?
z_C@XC$Kg}1)?*|5&C|Y3i|Hk8+c5erYk73rE8nUu^@DE(+K>_`UeTs(hQUJZyR^_3
zX;~BvFV+@P_@zWUuoW<++WmoWzfAkX7U-92J1H-DRr@|&zrUsxMu5AneXIwP71}ST
zOt(_o=>YDA_5c+!R%!pD+uhaLHoBHmqqSaL1dW?o-wTkb)fyjz-8yaH3m~_&A5akJ
zw)Pt@z|?Eif5Kpcb_M-b8?~Rz1zMB#BE?6WwO>&TszsaL2(VV|rU`Iu+J$sDYS#{L
z!zA3%7Epk)L;C`qIy<#_pWu(yqg`jE$G=zW6#)}{+BKB<>DNv#1UH~PM7xf=+V9Uo
z|DM*BHtmDjr`JMpNPCg;#>3iuw4oZ&&f3A>QEf6C*!Q(>(F<x!`#i<W#<fpUQt5%#
zo9<~%Xpd7yZ&KSs=Yc7$|8|PoOlw<O!9LU;odWkrdzS7=&uFt&0DD&Z{SJ^Lx;<1?
zW2@WYj8WL>PKKk=URU)d3_9qJP-%suZi0%Zj_LwW1I0=A1qJGzb(^SI*hTjq#XVeg
z&rlA)O()t6;;!2$r_+gtuIUwkdg>M#pzoy%`3}x_>yA<-u#fI8<?elTS@$q{Kb<@Y
zjsCi@Z^0eYjgNo?=)Qd%ddGDiQJG_)u83Sap>w3HL6FYf1oOeVfKW7s=y>$8!BE|9
zsxS)E{g6k68sR$AHkgmlDK5d`NZp6Oft=K-z6Dy8?sJMf#Oj`nfr&WXVR|a!br<4*
zouFIuKDbjlIUgd4y2mI{c3L;~Iwa5N)~*GYr2CP|x07{VVUSGGy+{{e&+0bP`}~~F
zT8KvLdEHS;T&3z9=vxtKx~7*grRln%Ptlp7D`aBynY!&e(RV@TGargsIup%owl19m
zFLHGCu`qa1_XFJ!&ei$<4ZC@|2eco%q+6!~xvX>bgk-+%A!W@Abj`G_x}r-Sgk+&r
zSDu5`BHiQwK#O&Gfq*H|9sUpoOLd1Rq*SJRg%Tp=x{k+S>8fs=j`!DeItlu&>$WX}
zLWR!pM{t$8KqF9Y=-i9JRq0l)h23i1pOk;C(G~E}cvDyW3`ni+OG*&b>8z{HLF1Or
z-V>hQ)=73iqh9w?4@iT~n|?cux)4{GXwp@@hPi0g#bklB=v2v=i&ot;^fGAEefc2<
z)1jL~D_*D0&K)MYbggZ$+pYVs6I_pOr41x|b=xTM+NbmR0+Ri@_3u&+VnBE3F6QK}
z&W7?{_jJj01|HOni9v>R%ykeM*1b=O>Ji<Kl!G7D3FtYxud9oOhhw@(zuowNw~<mj
zle+A$K&EtaDBd`&le>U>s9Qlb*^hK(PeW}+H%PTtv${9JFq9+uT0S6c^_d+oXQy{~
z3`4QkU)%yc2mOz)fjH`C{($6B{ioOAyp#S@x>f3|e}j%lF8bGk(dVjvWTh3uP4Az8
zR(JjG*J0j6|0b0#d+L2@d*P*@rQevhzW+~{_tAfJ9zOZ%!)ZnL(~svv#9zPq8K520
zAJoB8fIjPcfF0K#ehQ6&dQV%B6Z(jEpckayPleOL`jB-13(-d>(pEZD{}vUkgy~l<
z1!%Z__9Zl))MrujBuZZy1`@3=qhDT}zJzv8@%jf;pPQgh=EL99`j6C@&@=k7InYbe
z*V#fLLm&PpEM@BFQi}9~UQUtJEPVr2V`uA?j{_`6|LRlpP1%cjM>?|P>R+a%F;9P(
zlFyg)vtL8>vfl6{EamI>Z2(Mx{>@xix}rZ^3NH%vUvGw`BE2o0pNjPtcVjL}^bThr
zQmS9~6hzAOb45TY*EjJYa#i0;3fJ^oH^JU@{l|J*$}98%lW48fU!M=f8~W>%FsjnC
zyWxJd{ze|0snHi426t1B*}`L>KS7rW>-0YKjfPwL7ownWTYrMC-PY@whheut{~Gl*
z>XjxaH0kr{a!s>d69CepA6f-_t@=T_VQX#EyV23IU4Mv98F%!(c7W;72hlfOI`z+a
zgX_{4(<RSty<Hf%9{ntBrF-=g6s+pgFQzrIU;j4!nFjP7Hkhuv`ZbgoyQkmn1I$7F
zcndrn(!WyzZdk9N7~6>c?H?dHYSsTq`_=pUr)Zx&rthIY^SFL5-HU#pKbHtg6Z%h<
zft%C|scvsde}Mi0+q6Dr2gr<m!&x{wt5+Td_7TH}@c^?m_}5{A?F^y5uw-wjpz?eN
zLmO4VI2wMXv*1y~b31|QWUy|hSFf{S^;vYf7`~_F&(*La5om6PzwW@GyP+x_eIADB
zY4mv-Jm}!#W%!wP3*Lq^Z($TZ1`S2weGNZ(fb%oleVv{PLnEbqj~RUEKpkNClxoI~
z8!pg}I>@k;R*GQ5JS%14LJWgcM-XZVq>7X<!%Qw*3^%+(*Zd<4`y~*GGz9el^rT@i
z!9*GE((f_aaDl?$F$PIBNUY&0UyLQrF!vphctdXl6cP-QCV-tXFeqS=Xvn5V<+Ne;
zb)cLvZ2NExu#*g)iRer=n1ygZ#SpX%8fOh}W`a9sP*VxzdBc`mIFo94{22^8%`j9B
zF5Pf&C-gE5LccdJv#cXSz{)YOc<|+-VPq15xrVPPT%TunqY#ak44dh!eA$rmJo@qt
z?v(E;FvL=I?-fJ)$8fjMAkGI$k>R2Z3=|v858-Z!VU~=S8Wwk>ugu^?`Ok7g1jRzG
z8V+Sa<eFibl~$4KhR+0GD-30SV}O;0=p~qn8-^kShEiqloC7ba4bRZ~sm8EC4TCog
z?2Q;-t-+3}5b6wxUqR%SA&LGFw+-WmfKqQ*|2Fy>3>jU}YczP!TGC{wpjSb&;SrrC
z+6)^H(Wa=~&_rwg9fQ6KL+das_kw<>VapA;)@AVe7Jc1@%T)8;V|XNney>6GF3|c6
z^Qo}B-{2Yng#km)EPT3a*h_zwdxkG4Q#5FpN5S18!^yc&A2$4Z9(^MQe=2nuHK=Q7
zQ*_@ThymJ|Vb5bQIBpoCTG$5$8~U418RjdYKW!MMbI(Hqs}(Sh43%z>oH10<+Bs|3
zLD7pNMph4qt?|8Jn6NXxu@ZXrMlJ119E=a=z%@tX>=5i8HU9fAz?_U5@H?>1b2ctX
zf_WFC{dFk18t+pWz|DC4XUMo4xlu6TVZ8bY&^(Q$n?SsbzY~nNaWh3GeT?J9X!JFn
ze*^yd89$?avA?lu4!C2+b^hoJFnU!$;kYr6-dTZ0G37c=81<Cuv<4Y{sf04v_#~xh
zLyYg9#Lz;G@6#SO%sAg3B;2@_(uxtrL;rw_G#)<<?32ccax_L6`+kN(w9%PTv@yng
zw7-lsS}D&QXH4~hNWAf9DxOF%UZQJ)r;L?_Ac@BEZJ6fMR-<7R*fYko7lEB*jBSH{
zvhg+AdZ!pS#zW?;@zq%9pEGVB!91NeM$!f%)p%hFeQCxiN{pu)w^Obo!)Tg<dZzK~
zH(>XIQBApyEMwU_(91TuP^n9f(ftzaT{K4cpfA^GO+(y#-eu#$#n8_;KBALOfidc7
z=wC5TJOi0RV`CjG6&Xk9wr;WUMIHJ|jFn{oEj2zz@zpY8BW1M9jm1=0an<NgtLHUi
z%Rz`-H$M3?xC$eOGI5p0*j2D_!?<Y;22o|)ZJh&+YU5X7uvBCGW+g;#8hNx)t2NH;
z0I4%RDaQzJ8M7#Oa@+X50gClT4Xqdr#x;~1YBcI-p=&aRq@l0bXhAvJycXjPddIgK
zU!-7BoAI&7q0nxuEP}l|#umhb=XDrgJx@V_PU8X>kS?RK4vO8zQaTp*7^_p@aIbNk
zR^~qARwXq0jZ3Kzf55naN_6fT57Q-?d&WP~fjwx9-vjT5j4CIPVdD(lMjJ6UybF|3
zqnYkV-#3;lg`qKHLI(84jd}B^Z0LcpIvXY?j0{TZP8w}#8JRMEKaMd?8-1Fg_|Vw3
z1tO1(KlP(;##pr;Ftf&rN3e9nG);eBTT>3bwd_m@X;82?Jx-x62h&1#xb0~2w!)yZ
z>4pl8E~fu&fQYN<AaZEdd2S~C5zL9ZNk%bw57X!0gYz`mZi0C)(^0BM^)_9n;xZr8
zn%9BmYg%eRqo2u%N}2pko2atmm}wPN1P7SPDJXE<w7VZ9(3DIe*b}B-=tU7^+DEUl
zVAJGhXbdsQaT#KsHPrO=TwsTpj50VCZYq2YFcGFBln#wFWp9F|lct5G@F~jlJ%xp%
zO_zTJ7h`(k5cFbA6}ixhGnps`8gD9hhT93IXDJ18%A})obE0Wf53tiFr9FH)WAabL
zR3@2D{R@#~tLa_~6jMw&v_zdXz5W+E&zZa^H+$Z6W*myCrXt!=r<p#Z>Wy^M=-YtF
zF!?vY(M(hMTWGvsI#hwdWSP<?(U)y1rS(0>#JmFUFPgshLtn0`t`%T;rVu(DTr#bE
z8RjpWtTH`h@=eoJHBw-Ts)o!JlOqQjg{HZ5ud&E9cL*BArc>`>FeRpy=};&&B{)N*
z%=F|8M9NK0XCQLb^aUcq^D0acD)?Jz8cBx84O9I%xGGcK^AM>vW&8^ZHKyY)Lh`0*
zua&~PwI=i17)71wr>8OOTP8Q!1Kc(}dl;hirUJSF&|um=1WS#k2g^a4OiAfLYc_qo
z1|lt{E8hX7)nvX5$u?6oJ;m*&3-rX@F<rid`Ry>J)&siJ^u$6K>M|{(=wG*KzlC=4
zJ*MmD;7zaTD8(ZCOcBT6aKCB)pU@aE-OT}a*L3I!VBa%+LD9!S(<gLae8@Ck1NC7O
zhwdMYn1U#nH)=|vSK)or4T{8$nO4TZwQ<u|^eTK{QcEB*Vfx1vdXuJ+RkV|zGDS7O
z(zL1MDVTp~I<^QJk4y;A;88REwE*0#X*0cqj+keL0Ap+J`T?As`HKfous1v10&y^(
z-35b=W&ut9QL}Ijyl^r%bVI?}EItkkF6O}ZAmVD)Q(cRjIpQ_?Dv!H)<{M~un8Rt?
z>uGjzgF!E|-8TUBHZT7R#K*jq?wk9XPdx=iKXc$TW-r+6MZt&=bJDA@6lz{^50=8r
z9kgJEo1gs&jS=Qw=!Qk4x$O^(_oVqFx>g)zUgVCxX!A%V`m8Z#J0En$n|IHHeu6pf
zWyqW|uctbZMDr&t5It>v{8x}OX8kzkIm!I*7C4%09;1XvirGRti?ikr=y-6>oNWQ<
zdGldvOf?&5XOL!IKzrGAvy=|N8Ri8Eu#jm!OR<{^R`cLduvz8;I`L<lk6wakj(Pth
zOi7+OvJ;J$%+5j#`?7hT8YJKRm^(;;*_r~$E9T2X@Tt(u76YZotfjD0u{ns+G9~6M
zi_utWUiJ(ougrYE7kcGp0iAKKn&Y>k@0!`F%!P^T=G93sSYZx~LuaKqoC0V!%%g8W
zrpo-wU+AkgTUUeBn*XGoah-YTmk_ySUQIES+h!9*KkCiDl)!F-Ig_GOjpl3<NRv63
z?n^bB^C>UVVvbf}@><Ogwa{xb5B&Gvk=o5s-vjNAxzq-t9p;<#;B}fyR3KgE1yr@w
zZB_=uZjX7AwspPcAD)9`pE-<5N&3w#k>Cc*s;?n(*X$_6%-l2EEJWX+Il&&5hRhk$
zKp8emk{~i-4n7ExQS<b7^pM;)r%`dkn7M$?x#MR35;*g~975meoH8FygBR20Suc=>
zW+hd9Ju?3s3vR|7hl>~UX3fK&fU~tU&VhoRMNZWL_LgU;;MBo#joxUEmUmiU_o(Id
z3UE#q4*}-F+49o)XYl;FSgIRf*VW=kCwMo@kAskLx16P8y@%x+y3^rlDW)aX%QBDx
z^WK&*TBCd{_o>Fy*WyMSWj{*|1yB4fDoThPvsenz7+^X75O$ASF48T5K#LCr9!^*~
z?4TE9`5aZ5)_K7eMLs}7EQ`hg8fw|!3`=2_5&CLjxMeK`)gvs4baaoj_|it~q$QSq
z&rz00dMctVYC6uuST@;!#9Dry2TO652M(Cgc*}X(LnK=E(-VH$(nz&qXDs}7IGSV$
zr|^(9*}}4eVv1!B6PC_eGU*_6&Z2l0`sXeA#Sl%k*wKM4&GI$9%hD~HJ8&k$B1(Z?
zre!<*W-eH2eu3m=OAysG<y&^so2kH(O*^nF78^=B6k0fc!C;Z4KLF|_7S($gZmHGc
zM}@^@mK}7WD7Wl#hRjvV%y!6Jx6I}Nrou9C0DYB~?UXjVVfp+OpjBCX=uc5&8KrF0
zO^YABJ8La}`GTvneDq(8!SXi!9&cNW^-!p{e0CNh4VDEV7+Iqwvkc~&EY`awjH20c
zOANa$mgZ=Tu+<{^1Tt-w{)Lcfw@lPyX6{(*IneL0yjcy<PK%t*2VIsoDZ$rm>7%_~
zk0s(mkX}o>3YdMCox>36x9I0XZ@}^+y#?-C_EDw9J<F4yp>fdixAi30A<M>5kYUS<
z)zBER%)Sisqn4dz@aeu~5BWW2d6r@Y<Cgif&3RyXPXpJcENrR?nYQTYF#6E)bO+2o
zvTSZc<BVm`B1q0!u2QwWtxX&olVE4lLuUtj8!p{Dcd(gVLhGNS&57rL=48`Ar6JBX
z=?s{6vC&hq)755oJ2*F+e@{Wg!{+Bfz<An>or9#8&2fs{dE4}KL&V3Xa4kT6ZFH0#
z@v{-r4$R-?uO%SIY(ArKa)3?1BIq5rxp)>Lfi_wJJ%1-`ypz!yWV4qx;lVbiHUllh
zW=9i-9cq(q012~+y9W|()BOtu8evoLJwzgHejA2QCv8^H3Lj-t-T^M!#-<1cV{HD<
z(RIgVU3GCQO|vXZbK6i`mX>MH-h1!V)XLGY%q%N=GwWdqh$6^RKt!e>Q$RqFA*iSf
z5fB+NMFc@WRJQPbPyBN}=ic)@=iK}J#=Ym9`(q}>p`#hYB_O95eIkg&Fakb+hp~*G
z=}S(h8QBLWP4ea5m~NkQ62E!^qfQFhM8=yGLQ7&yo(3+N5yyhzRK~3kK++gtv^74<
zc$vbV>5K*M!{H1@`ZB;X85bxup2avsYmscmhLs@a8B1P*WDaB9Oc>5(1kZ#U`3%nn
z;4UzZorKN;My}nA&O*l5=@{EZ#$TzBxy-P6VKhaI=c&m13dRkQs|=4h0A6FHHbAnN
z5l9KM62|afuvE$@4uwb=Bb2J1uQT>MhWF)+(CsjBgOTvxZin$3m6ujBR!xQKD#kiD
zxOS8A`hR6m)r?wy4DA-<<2Qk*VU$rot(L)~0B;>bL)Sn(!$`4`+l(8uaBg6XHN#RP
zBVrI<G%?EPq0r2@MtO=B#?xQHwK6;d;QbxO>&bw(G3Hjm(YuTVKVzQS8OuZ9%ss{g
zi@prg!BBq!(N2c;Q?zz7Hnzgj1IF-q=<Z<zj{?!l7^AZTeT+3rAo7qghiXqBG0w~e
z?lEK2QZzncG`|dPfWeywF9sQ#qktP`w7rbJ5yo3oX*kMoq!8yALzDuMrwni0NA@Wb
zjL&J$=D?id1iOyRJ@0{YVm6!v-kI6E3tqS|m(Y@AKXWE!7+jgIGoa0ld5KDg+?nOq
zFc$}y{tv);FheT99c1S0#Ec$d)`q}QPv&IWX&z?wKEzyjG5cqu(VKZQ2~%P}!nCh|
z2_NQ%RPW-;{GRGZ{Fv#K6Yys?P=RIub0`Qt9c4NXLCrB{^%ejEnGZzpH;DP}L)Z;w
zDt-ZXoZ0Xb;2}&s?E_CR{b#_7Q0Av=fjh}em<ugo%%2-!D4glqfyO91Gn`IyMKfzC
zwReiSh`xOg!_<BZd@S?!Wmr1RET)J+9P>*F5DCnbwUA6?M$kd8B<4sy>?Si;P;TrD
zvyQSQDNI+2l%_I=D2RKO`3?hsbmqsjx6ELkK8N2RlgaD_Imfgwj)A2t=C@psY-VI0
zd^^t!`2%ChVg7p<TrTr_D$L1aE~x?H0<--hW~P97?KrqX=Go047n$2ByK{-Tmre;?
zX135yw}|<{G<b29xp_5IUt?;6AX3b9eGBjsX7sDjS;~yH`@uvRQ+f};>&ym9uijwh
zQEsAwxp)oKR5G*kfT&^~Z$#fs=9+5sRWlb;an&v6hdV%OnS=X5>X<)f!bClD3O&1T
zGXt-|ZUghm1vEA@XMF;LEljl|l(jN%yo#B*!*tz2&)_!ZYHy6<E^`k(-`kmMW`T4t
zokD@=WDaeI!TZeV84&4Ww$YxcoB3WfoO!_fib`U7m^rix=woW1L*ql{o6T^$pXs;=
zfJe-QZh${#Htz-ZgxT!@)dNfycW4=8R)<hwz!1}Q1K44v%@<CMFgN}T#2B;rJ*aug
zT<r&k$C>%H7~ur-kMCf@fwlc9L>yUfQ3%k9mBoRi3#&?vvFvB{tw*0LYw9il+*m(Q
zD8QW+MCWi1u*8%{@?bT#z}_L&ta<c31y9zd$3PrrEx8MAUaZMfCg;ssCxgRBSP%9A
z=);N?gZQx=)}qg!W!Mcs0Bbkxl8&+#zXx)R75NdA2D4NY=sM1-h=ybcOP2)h1k2b8
zE|e9K2k%d^ZoGi$3S+5g+iZ_uz4QxYB3XGGArr;QjYMlSYZ|4-PqDu8MPm$$Pixdz
z)+n8Uh-2A2AQI17PnE(6tbb0SF_E>6Uam>3SLtn<%t{GC-x=08Epby=0b4*)S+@t#
zm&Q70!N|_CE`0_q8Ftq0XW)J&D}mB3=U5}pU=&%bIkeBnW_c>`bDd{>LbV||tdw?$
z<gvb{9auigRRqZktUVNWDquO$JF1YCxD4Dy*4GXYxy1UK(%(g_;frXz!dle`z*Sax
zKFBpz_Fw2LX4#jo#jjSv%Aya#m9o;DL9VkDv`i~!O{4Yi4c5pdkP6l~Ex{^T-+zml
zsb(z@VuZI?tLa=t4NFZQK&fSYSO<6=>(zhJSkG#vJ>qTFDrb;J)|NDoCYGEgsG0Rr
z3;b<i9kJ_SzLjO5cg7vo7B28@tX=)+Y-io1+y5S`?jpDjmady_2bOghy6>~%>S3^p
zHU9^YZq}|I;2yBDX&KwY%0<F^N-t~XYtY%p@}pN(KTAswkw>iUc@TNb`s#0Z@r1R)
zYKQItRuSd123Z$YqjQM$3hi%3Si4`wKu1}>K7|)!Ecs86e9D^nIdqS+PFACDf;E3R
zeh~+D(;g5f_MCc1I<r+2EOcQ<)q(71x6$wF%AP}uA2;^=F5ukR=1(B$!FFFj@4tiW
z2lL_0A@&q1-}hu^1VZL8+hGjuA7Q`07Q}~rk=`J_?3F)2n;-k%sqojIEvD~C1hBn7
zhsaU3r4k+nvfHT6Ifxx81|XQ7aS_8l&i<E{A|dSh&wx9@ZlL8^C_5pCj_!rA!zle7
z&i>ynn2%t8IUT-5vftbeFQVATsGvKVecTI!ImKRNMqdp3!YPng_ERc5JI&riiJ>_5
zFjeCxus^5MJBjR$Cg76TEvfJ~ncYdd_A~4=-(d1m*dN{iJe8f24GZ?O>>0GrNN4Xq
z3x_k<ZY9u`$u6=%%{g{rJjQgMo%0%iIqX$*&E~Q{4gesJ9Ze*kEuziv1@=Souz-Eu
z0gV^gIx14S#BTi?++}uL63iE|7l*^{754hA(0P^pH?4B6+1V=wAzH$Aq_<irJC15!
z%h)-8g1gRk5kYr3oAV4BZ?OA+Kw|~_9WA`5WD6-JU&W52$o5V42HK5Qv)2v6`x>?<
z9YLyPH@ye*b?iA5NUUcsqq6_o>^v$oX<*OcgKK2l2fjgPGyCsgh_<k=c7wFCKcf}g
z9ky*Tbhokf6ehpN{@n^kJJ`nKXzXNX6kss-**}y*vWu;x2u3&iEvm$Oz<xv#@m}_n
z%i#Lh>~}#Pvd`B-bw4}zCn$Tw{&62f9<w*u)xbYt_fW!ckZqt>&Jeq?2-=3(!Bmkt
z!cIDY*&AgmC~h^zwpU=-PuVrY&^FF4lR|QWU0MyC11FU(OGl2H1DrGG9V+;6;e^eG
zrTrW=o%3<!IMWN$jU%L;n>!~vj$*?HI7t-KI>_0$3NnW{epCbQ$*HG>*kR6Bv`6&f
zT-y#2AI__h;Cwk#KLO{*S<?&M{+!3N;8Or+ss&>?%DFiMV>!louM?JnIPcGbqrseW
zcYr(2d5?B=A)HbQ!=B(gs-(j3P|h>7*g`~%o;Tr~hr57?;9R3<dn6~5-n3Dir?0?7
zG-v-Cz@OrDX2Mbo$CuXPu^e$Z0H-;YqmYc_+?s*Dc#i8w7)v7O^D_V>aaIk%LNaGU
z3CS~@rL;at;Vh4)!qilbE0w;daX$DP+R{0%ZN-#iaJDpoWO5#U0mL~@xHqnrEY1sT
z0CPCoC@hl8$)Wgo9%tk07;ip@OX0E$9KltP0#56<&{@bi_AZ8Wk@FL6crS6R^inM1
zgwQFaE1Yc-cxb=MdDa_#U*i;i0GVP=z#8Z-<=m#=T^Z+d4f?Kg-lLoA2FFCN{R&Qu
z3Ug7(`Gx|gRh&?IqTb}xe*#j?iKilfTbv}?OV@I)xq;MiVyKL<o^zItf8OStsD-iy
z&cFcO0CrB92%Sxw7Hr6-v~WVFKzA!=wF6}CaMn?McpJxo0?l_hb16sO&bj(NJnZD)
zUs&P>;KU0-x;Xkq;JP^h@4}}CoC9>@^l-ckknH7ncR^VnXUArUJmkz-2l9whg8=B1
z#~l0i0=W2u^Kv+31~~2X5yL@FY&O&ka~=(V8{s^rZ^4anWSwYy%85$`ew-5!0d9ih
zwjO;BTrqta!I4`^XMvo!v%0}Kb2n3}Vn5eX07+Nw3skM+#x0)=fIGMKG~7PG{o7sy
zZ64ePcTB=T?m2pddvd>$LG&<pJqjnMcyaIVg;H;BJUz6Ja1T#GpAT0(3u^qixBdYa
zz~ybkK#y`wzkoZ&b)z+6Aa@o;Q-ipfiQs~{5(-Zo=l+lmXF|9fN)Co{M_p<Cd6JvB
z0BjidD6LGwxz5?p7Qub50J9#&-Ae)EXzsw*@ZuELg%07xau?A9`84+cRprNVyFB4`
zJa>#1X$joF-h*T!cim@zCvgV_(0PVC?{{cP;a;NqCzabytA;f0wi%Of|DEObyaX51
zxm8=xn!#;M#f5Q>+ecfrEbg4Mz-M#cz6rbMxzF5&WDeJXjmBK=R!RU~;0pM#TfpU(
z0ba;uGr(Qsw(bS|61Of3<T7_Hg$IkcR$9tm;dVwt<SKW=a@zl0<GxIXB#XJ_9q26K
z-l9{`rQ9ud&{)QOHxzSmohuFiSI!NgM8XYjJ(W#YaC6llmE0p{0IIkxVIViT%P&An
z4fh!B8*90>w6Cw@&fNjYdTtz*)!yd58UgbS+!5NW*c-VUCxLC^p8Xq^nz`RnysU-m
zN`bCcZpn1u?{ME@!)_aQ8C8$n<@Qn-x1Iaqd5q~EcOM<*>EN<|#*}n&^|`>^=e|Z8
z`Y!GvJ>cEkI=UTtxwAfm7k%7Cq2L~J{~Q6l-_9+j$oM1fS_<|*<{o+%CZ2GUK7`T%
zuJTVP9pvt%73UE5Bf8jzxpV))#WKR3OrMAv<(jC*WQ^OA25nEddIKcKxd--uo8T7x
z3@r}4*Ox)3Bk$@R;GB57`oKB!T(_dnm1n<Cs~tDqYj43}civ(N@CSH5AAoKTUMnBu
zAa62F!XaMBd2pV*w@N?`^E}^%2``>6U7g;%{y{YQ@JdGDj4y8~<%j)vpY#If&&&M^
zmI8Pq^fo)nvwDCW<6Wd6V<2z8omM+Ryl1EuBA6!)K<9B@FGXxl@OB@=M1}I^(MI_s
zPfaVhFy1G$4-4nLOC>H5yw6I|7|Gjx0(PT#FVWT~n#ZG(`%^q|E&5`3iC==8<|#MA
zi#XnDT2ICEW|qRW1fGx94oiu=`UwD&cp=H~BANFFt@_XKDk;mB!ppvc##Ek`KH`(c
z>(2)ugU6-CWhO6T0YuL6wtNF;vUm+oFzjsJ9J(OR^Vn0-n8VxhEu6{a;lEzsUBUZ)
z3e4y8zN7cZ1>Vo&^!_X4Nq>d;i@b;Qk(o<88|CaS^LEm~-Xh-FHXyF>7A*j|%G>iR
z26~Mb^*#W_yf>(Nr-UbnM_(z=%?0r5yi<=bv~r&O2Q=Q`eL`nsDtKHvBv#3*=fbrr
z-Usw~m76@ynaPu0n^MhtmhzsrcrVsKX$?=|o7^^g@rNx?*1&s~F1bctP9eA^-c~Bw
zZss}owzSQ*hxI|cjrW*df_HhY6n5?4{c;gbck*u0n*BbHPaCc--kf#dx_QD^K_2j~
z+=oX!ycjA{?d6qGLa2}DL=mWmymu)#(9a7ghvZ}4!UYg{!fU?{rw4c{J}eCKmM22z
z5Rbq35XLafo1k)}5#A9xcRb2dy$)?-y#6@fBX<|reZNJc6Mxkkz&rCDDU{>Fw^ICX
zKY!bC5LbQ$T?cM_-@~x$&R2y%*#Z7HtDwb$KkF<+4)G7sQ`M6%D1hC=d|4J6z4%*W
z0PyCoqigF3zl?5LAN~@0y!i5+{@Ww)m)q&Z>d!w&Ij#Wy>norpke}%bE{K2h1q>~i
z&!;5sasKa=1qk6!r+m^0e)%hKJCwhRK9zEk-xdoKVf=bJH51NvrnFK7|K?*zM)7aa
zwm6#qr45p&_!lV?8pE&K1PihJzmn<Ia++UDfv`Bf{{uJ^&+i=uB7vX20VI)MHwVBZ
zzONfZ&hX<Zz@_jHQ6*6-pHDBUH2&qIuzQxj=tT@Wo!>=Y!ph+HKL_)f{A@0UeU2}U
zhUzSS_Bx1U^M9m`We)$Og0@z<d`=uJ<?%VqAo+ah6_5-3hkt_<@Q+X&zL4*96DBV5
zvphjA@#A;E?qz;D-PlF^ZFEHV8o%=r3>NckO#qbekJ28!lwU@-av494-Z$6zh8=LG
zoF7QRgd6-rsA{rLso-z=3;0TYg%pS?elQ(mujc>ef)U>0KU{^r8h%eabl38~rdLEA
z|K;6KTF>7e49VO4P9vtYfxqKr=x*c}{ttjA{;MBhpw0ZTG>EkFpKAcQ!{30<uuN&=
z?=D8)U4B3PqYisJUqMTNd;Cv&(b~Z`9)+b&zH}o*@ADs{0%J-S|Mnz^bn`R!L8OP@
zwj3h8{Nta%QXl_$`eeyNer7RT>*xRC0P=|c(pLaH<~OFprziZBW=Ib3M>hdJ$j^2H
zV2JOz8s<ms{CwJnjPdW%Px6$1{5{Bw^RH7JZG!(nAc%t?@M{=!6#PgYItj93K%4~*
z`+#>596AE{enGPtQ|czD>H%>Vtfn310l@>hH$4QOJ3#WFVD?ftb4akT9lxumpyhk$
zJS?y`uf{;V1j|Fw=`G-vLH7|s0X<xO1wC{+%1>~_02BU#i8BBO2>w@u#-oBr`X>a(
z1WC_=3lt2~GB-%z5)WLkK->zQ#|15$pff~p{siVCR4_FRUYr#8QgKF@pp*|TT=1>^
z4A=<4sS22g6bweeM3lgkg2rgUxAb^BCCJXgm|_H36kCrKRQW?`ykI}YxDy1av}I2e
z%-)NECJDZ8gBQsH5gmj$Bk-gRc#2@82Dntg0t$zv3I2!$cUJKIb#Uo|zl$mMlqt|{
z0sfreb`eOHAex>D*@DMh;Li)(>CKoUa4Le`T!EE`zC6Ki6fn#e)X#@&7X(_0?G*^_
z)5rBL3YHxMcS$fr)$^AHD|Ukv308-}&=tY=^aj5wXvzlsn!v@M&ioY%!oG%@5`pL&
zh?WX0^D(9}!SstTUoJ4e0Ece~W^vG0Ay`IvhDw292tHK_?owUeO~GG6kZM6Y9oD-g
zSnCMgHG;xp;A#c4>)}kD;1l{1Z-d~?$MCRG@a6)LCV>QnarP;#f_aFpO}QiZcqvBT
zCdi;{Nw<LQ1%nR+Q)#EvBUq3QyS;*W6cz6ibm%}H3clM1(l3aJg^5RkFsiS6ELbGR
z2%iX^IAIV2g6coO4GKbLL1aiUJP(b-f@0dEj|jSd0^B|-m`3l=F#%^1>^>FzMtR0@
zK?U7^6M|nCqtQXwL&Xw~!m?eEbP~Q@h@m+PKlv4nF2d=rV!Zo>2Pn7ZDs-lZftygZ
z8wTBl{!}h{K)7HHh=-8#DR2jcKhcNx4+)bgiSB6^-l2gW7AAZIHD1CK^nmjgX8Z}n
z5#iKuH2MfLe8Kq&pS7XSPx#Uf;QfVlv}F$vx|=ciM}>dILd!9sRE5Ssp^U!35+wYA
ze&%4|l4pTCE>u$zFGLtf&#)81`eKYeRA_ghxAsY)cMn9vgi(cP4HvppLTQ9>;W8+V
z6fRy3M3gWg2>58B-xf%o5=QnzBt|%QA*Li&=(-%_v@q6)F~te9_Ch3H_?s8Tn;?9*
z1~Zc=eAxkRCke~xy_qchf-ZqG!ejP#U@%3vkpa<E;gt<AktXyAf=_3K>`RbI7w)-?
zz6@ai79vwJh3lwz;GFR747iph{Pi0EvV|Y-Kx3|OD-(|933t<aEnhfg9L`)2x=|%U
zfpA^|L<)t8RL68t_#_(eOTyIiw4}T&Z2K5a6$yp3in}6wrWcm33d8BydrcTgg$2dJ
zD|E4y2>+N1e5vr)de|)!I{yg3bs?9ulnbAE9_DWdo$3Co5Z=SuZc3%FGzzM#gxe_D
za#NVT5nfaacRz)eTf&MCTH4hJ(__$DE4(8FqE0xu0cz@nc1juF7Pj=mZi6tx3Z;$0
zKdE@SNtj3{iJFDa*1(Gv;q4ZfXcd0;3%EPNhZJ0E6K+ib;I1&4E{}F$un2wkgwv=@
zphM{U9kg@`x$`Krcwe}TUf5m2##R{Y79OPXl?TESG1T-3f2X^#SNI~On)-xSG9mI%
z_%|(@`-Lg};2sHulw*D@oK^slC&HI*!R~<2Wj8z=6#iQQks;x6iaQJopBF)7MCeS*
z<5A(#=P+vfm@qC8GEarYG4Nts==>2}oDd4;K&gZ1NeB>*qIHKM;v`C-)TguPHwOA#
zMBlv)rTaxS6b5h=b!>--n@IXETyqx{%>;Kq^ma5j577(*xPzh|CCDMsoJTP4DcX7n
zj(XcgVT~|xL^OL8tv;fzSd7<Kw3{kM{6u4vnDiIj6hlpbXy-wQ92KR`0e4Ka^S@FN
z5%(6jAkl6rVF(tTrbXUy(JNHs8zM5&eSbpq8fBb9MXv_K?USMcTF!-umM_HU!$o#x
z3pyi24=KbRDe6vwOq8gJqJhz(Ynwn$iC&>YkujoAUx1^rqIKUv^0Y|*GTe_7tyiKi
zUc{uLk_1t@D?}1Slh1)m5;fAWlSP-GK=O<zXgXA<hy=7MOcl-B4K7V2u)hg6&We^D
zfK0lGPsjT*L?-enQ&dS2*>j?xV-U#_#Xpa}Y*FOrFmYa_qquvHXqOTqxuO_~nCFRp
zp{HJfsOtm(g`#P_n2U>|6cuLXlISIRLR=Q5e+Sh?qPg_Uz9JgfOYgs{q80Rty(S8$
z?-mq`f~bV3MD#5sR7yo*!4NGIO{&F|UKjnQLu0vU*9*{gL$u&Ez^g<bh(K<NHc~pM
zS~SFfqqjsmDWF>;+K~;(TG2Sd2vh1r6<Rn`FM9tnwA>b5lF=8r8bmj!lBiMi7cCN-
zM3eA0rCIbp8)RBU8B|8nD#FVUH<xH79d&FIEvJCeUC~;)$lFCvXrT8*hV>vFBK1e;
z>l6)9QRID5?(?wQCCZ_MWVh%;J>U;SP2=#lNA%=#3N7}EDh{HvPn63B@S*67M2w<e
zbgUVok3`cb|NK}qof73wL<i`bkprUkaF9XK_0Qnbkmwd0+_0#R!Ve>&7w+Qs9TlCW
z@Zp#!$OAf`ic<423F9KA6(SR&1N22k2l4(rP;GY<58Q#MlUOnz)8;Jx?Jf{5;$P`)
zxL;iGD}b(I<16TM6R)ETjJx>J*D!cM{12s2JjBdD;l)AmAUz5Xi7RQ<;3@vZ7c+WT
zte63~mpGKln!Lp+RFr%~ygL_tK4NVMBz^7T8&YWV6DuddH-B-}a&!iWQ{2&bRGejn
z!DHf1T4e=_m(oWNgTz1m1j%6Wmy{DbF5a{aUWABu^g`r>*jNLlq2g~A!O}@_3Vnho
zOl+e!Y`FL!Rm(+)XVS^tXz?r+8c&JsKc>M_jQ9(>0b<1~PD1Hv@wU}yj1xaM24~{M
z`N=SmAYLc|mniP0a^fWMciCu67WbRLoe{rGA+r>*LJuveV$pP1N)t;CLd#ikKh-9u
zi%*1t%Mf36g56B<zMUA^IdPr+IUusc+3TPtTbxX3yYu4bMqnvNeESp{bH&V8AetwZ
zalz$_YY&3EAfD@lffk6<d_fAuM|MN^Me+B6P<Bb2NwLVw;)=g9B}HQI&(U{9ykZpG
zRk2|`EL;=+JsZl3#m`sLo2x`@$^cs`KG*}@W#Y{=&)3E8Q~bPKyqV5)-Vk4*NMVK8
zF%W~P6u(a?>MHTH#jtc!JV=Y_8nKd6khS7l(I9nVu`6)(;w|5y@3#0s3k)@gcO=7^
zMsa8!M4H6k-J$hovv~7|5N#2^n+-2o#Zh}8b4R>z1AuMfFX_6vD}E&kKDCQOK0@O?
z@%KEC4)HsqAf4h*4FKF1yNrSB5}VIKS-03g!R-g)caFpD9<iKWF1_MSbj+hq{64Lq
z9*X<sP-?qhe3sS{kHlBbV`z`XF%<rIBEC%d*a30j^DsXs-a#ctL*lLVn8ac6b$<Xx
z#IxT<->7&c<pRdUu9Wh5DlWSQ+_*UO8z`F)FL@Tq93-20=yQ~;3<khSQc7D8XUWbx
z=(D>>F0X~Q{gO>|klt0Yh_a4u64Bd0xJ#s;!tMdd2KvCAhooQ<Cg`B#b9%`fl2k2&
zHcv@B6(Ss#XcWMCNwjrn^p@!8>2pL9@);z3Bz8J^?<<+S4|e?|u2dc5FZovq5@45n
zKxd4PO4d-0>X?N29n=I$<}HHKAc>A1cfpb^<7hlCnYa!$ArikX^qr6-Q8ibn<V&iP
zIVt&(7F1!9;CtZ0CEqv$5FzpO1s5qX{tZBs#JmOOqa}S5=szW~dt)r8CH8O%i^WM+
zegQUKGD<aN36dxDPg@ctYgI6xB*}UgBv~?TDwLj)w9yTpBC&HoQYFC=z@<rcQFYK+
z$(~6d>5?=5z_kp?Itn&qN)~U27w06Wzk%v3$xr`-mTbvJx&+Qk?%MYOpChTvfr(tn
zA_@`aNgO`}$(J0Uk6c`k#N>h$NWP-QOQFPX4oqB>xNU{fOOhXGN-j(Ibe6S9;y@3t
zE0UQEh+LJFP+7w@$#yNADVCVug258WN**SmRPsX^ER;#~{dP>-b;;xdaH?F=_BOQL
zkSzWjofVSvbl+D>{3BthO7brYN^eTyHbbOZQbaG~TatxzmDETI??JLwa)1^Aw<VXA
zXl#)DPPHA4l0hnBX_BNMjWwlN67d=uTO^VFaIIBh8ld;z9m#MJTx^s0{|{>JN+M}D
z*)DOQ#nwHEoR;JrlIjC+v{PcNhnoA6_vqU#U6OC=K)NMM4gmK+vVoSNJrYJDO!P|j
zt^%M>lCuK-K9syZ3Jd*`qx5QiBr#LU^|9nKs&nmAo=A?;8e~9nO$*UMN#R-89g>{A
z1#Vd4aTt9glBV5g9F^?rMB|v`E&3?HQ^|Zfcrz}!JOH~Bl4(a^&_SBm0pch<N6SGc
zDTg-Z&QjSsaN9*1MCW$)OT8#=?kZ)`zQXP%Jx(tYcj=u<XgeU?NTs_T(!0My=|QQV
zI}nGZo2W+8OZw#>@WNYKl??n5saq==eWb^y!Wm!bj|ph>lWy(6l=w@Fs5&=5>O&>n
zN2Qv-p!%4!lP=Og>9>`z5G0MFaR%F^v*<N^Tsof?TOrc<+c4gf(m&{cMVNHUr!WyN
zeTKf786oYRfiXo&zoS@1lysa*aH6GBN0>MzU2_N|Mp_;YWwFx9^!7e2O{B90ancFO
z%En96h$Kk4{^(1T);x#NCrRylD6f(%-N1$JGt%Y%eRxCq=|TWgrJ`Z@lqUUvuDP?)
zU3NH=E_I8*&@!ZKiiT%OZ&BL&oV2$EB3aTEt-xhVYhQ%2^U~!M>&TIAVL&ohT2KE6
zDo^^ZH%Puzv;!g+q`7vwt_q}n;Q$s&%P1LlQ94df@=MZBhvDL7>6=t)SR@^wk3(IN
z8lQq(l?MF*rPrh{@Bk>52GV}2MEX6QEhv?`m7}jr+D%)C>(U9Tb+{pIxC#puQvc^b
zDy7wO^i@f#*V0z;rZo0-$W%*zQ)9fhq`{PBsgX{lf!0d36soC{79GR{*GpZt0B~Cx
zM1ju+=|RFZN=1}XZ<2mZ1*y%_6v`jpk?vjwc$@TiEF|wr3+JM-U21d&{GQaqA38gv
z`6cwvK{};OdWzhan(4ail8*Yrw{Gb_YcT8wQu{I}?U8N}g6oy$&`IDv>9dQW?V+@;
z5o-FSbEvZOku>yqXn8FCfQ7~<(iQIlHz2jg0x&4`qL9as)HDJzEY-e`z7c5yf*bZJ
zqtaC-Xd9DC-9es8Unzy9ajBC(+@FwcaDq|?*&r44ILbJ*19FlDQDECywtNf#7ul3E
zXxuN$oC~F{vcXjJxydpqnBy*c+zgQeGM|6IdB~n$1j&Ok$F;C<NOpnhQth6y#;cGy
zEDKEn-b=QE63^bUiuphsk?|Lx&qt<=#|V98>PQejSz8{6zpS|i_yF0aa~SVY*{LWD
z?U?MB-(Wsamh}|Mf@H7IlO<TTf-)h;W$Z}wg~<Bou+|CL9;zk`waaoY0C-XsPqFhb
zSt!Nz!eu9_AQ~YXqVz?iY-<k;M#<LG`I~52jsoPA?0z8B#K>aT0}v|<r<dw!*(+>#
zA17P>2$L5ta|nda1lfj17(}9McN(}P*`Hw`$+91lp!$r={#h0*rN}0o20m5x4&9Au
zvII&jo|S1Ppe9}R5!Ie%$a?ZYGG+hkK;Jo8MiT&8vNkGb%9hQgyvKQ2GZiZ5$Smt2
znJe4v2W5G(Ix7JAvS%G3c|jKO2fQzk@#$K<B#W{ihBudGv*l<ll0Brr%@rBn0K`?<
zmjURzCiA$CzGB&C2lSQ5#P#SamCXo2UzzNCTI5}q>HoqA%VjUqHtvS(lnWXwWNlPc
zSSh>W3tW|KDrIGF%AyP4TD6Sz2<C6eM&fAwStFa?1HWr!r|7e4b+Wrd=&YCRTnYSb
z*)SbgXpp6CKwqOQo|ex|vcq}6HOtrvIMX6~=T#_el^NE8+>u4Cfn=LZ*#{5r%2=V8
z-*(v(x*hJx*1iWXI%FrtA<`+6`qJ^r`?3y-Qgq3_q8M7Y%<sP&PgYDP(0XKf9q^)8
z=2QsMC%f?yv^|uaqARIirlgn5BiU|x(La_Qe+~wp$o{t(+<>f&N|gp>PP922k~vbP
z$FPhs4u3~v!97qmD*MSY75CqmY$@&kp2`l<Q(#=?H5W=JWD{Hf9pn@AkzGgmQTphm
zll<5N_~b1AFa?b+@>eLvxnJIB1<qCOLtA1u`DXg$wY%JnUi$~+FB;M4AulRN<3agG
zTAv(}YhMH0Q(l%05ABELztG7WFF9)+TD|2d+hF&Iyzvio`pCl;g80g}j9^TD@|yYR
z3y`PN&2dzoMP)k2<j!<+1<GANgYF>tH#s1|^5@<`<8gU3m0yL(6?FRcgnZIlXbhFl
zq@tOV^6#R+h1umVP*GO6+(5C$2>BRQYDLPId;$|u@;_<y9WCEX$4gGh*|dI*k*7;B
zd$DpyF@}9w{_!I8#mN`Zz9e2gbO9m>^0y1YCCW_?A(AA2c{a2p%R`RCwKMV`=;@Op
z?`X%!Qss-YnXsEC521kTS-ICXaOv{5Xmgh#UwYL0nP+C(H&RVlwtTY#`p(O@lhPb{
z5beBj<>x7wn<t;|2`*ng(1@X3kU#f6d@7Jv-vlX?e=r%UFUo5t!>3E~D-_|mEMGwJ
z_#(OF4FIml=kA5bHF?PcSSXgSbVOr`d`3GOOXcV7H-RXVx9EYmE?<!agXQuqt#JQ_
zJR%2Ng<SRqxJvn#QgBsr7up!yl>ZqEN2}%Obg|u%%b74=BY$HIT59DVQ}tz?yo&b8
z_43T$0k|zUd<=Ml+*u7=qx=CKh-{MYj;0i0v;4_A_|_sn{S36V%7-b+cSpW!GDw^J
zDdlzV%HN}1O1pd)W##V4$Hw4xhdksav~|jZsT%6O+>gqcy5v@8IMXfvs}$sc+=oKn
zJ@U4NaIIJV$tqarlYis|XCBHAuB2PEU;a8puO7+QUV&4O<@uij@kD+%3y1+ZI|6nG
z<$sN1+J@x*@1k#5&Y`63h&-E?>!b2cS}u&qW50qIPvsl`faJLRhdhW($YUs)>7ejf
z2uB?i2k9V(i^Ac*I%&msK@_5KReZ4%cHI=a={9s%oO&1B0ma|6Z}d>SoB)RpDo!PX
z98xq;J%Xp=1rfNziVrDF=B4<KHrC#XSX%WTQMet2h>v2yPE4M!f_DN2{S-bgz)^oi
z486Ys6w?AAa#V4HR=D<KijV08W}sq6DP)2a-!6dpU_}n45sxc=p>=PFqUkI2olq3f
zq9;_*`w)F66?-Y27N&5ewQ0Db;SXqwP^8km8L7yA4kSv^(*{SQ6-`vBcuL{^A>c8J
zj&I;vtfE^4a@wv~{x)cwBAkweCMw$BgqkEp?-C%A6-95M@r=TOl%^<dP|bR(;_xU$
z(i9#_xP4ZUMTI8min)m(8H&_kn8;KlMZl+X3f4TpvlInC1DCBBrA)(l#q%_=ISOqI
zwB#!6zGG<3Qyg-^2=f(T^U!)hv5;=V0>woelol$6;vsTT(Vc>6yQKL06lVRhVhQd4
ziWKLlj^c{K#R=S1#q%41yQa`o0Z^=X;|%~x6t5W|QmXixE|xOI6xuakSL~rfmgS06
z`|s$yp{S-6c7?(a0rx8v=2K{_Qq<5>@20}^5!6&G{#k*(TZ*+5f2mP?O0T0@#fD3m
znL5QvN{iJixXrM8TanoSkp{)1XqaeJ<a<F`lS1tdK(k^prJP$7*E1o~stB_P(0WI)
zg?4;xis@>YxT^^DM`wqkFb$%eioZ>mulovLn&2+QGo-CsG4E%P2a4*WUp)WJ61%Y+
zxJQZ?=;+5|Mcp~{JyD$Og!uu*1VwKL6`QEsY)G;BPv{(0Tz?rNBZ|dzdUjONLo4es
zMHd}`c&eCAKghV^jxWqkC|>#ua0jJV2}B%~$EINpos?XfW@n}K6-<naQfsFy$bRKR
z+WNRE+bY1hDf23!+g&-2RwM_MUrq+zL%EyEE)Oc#Q`O2LWiSV$_EZWhz#UfR(#qIN
zSx3R+W6C~X*bP)hJ_8b@oc<#ugOzc#Lp-kB^DSHpQMOPW-U(&*hj!pYmFe_kJE`3I
z4Y)AnE0m@USEd|>`3U8h3|yr0Oe+vk%DuE?i&nn56@90auOwp>F-p%t^u;QDhR}Fg
zx&0QLiBqZ^LE@Ej=yYX*vWG&liOPbR@Gwc~xE>@~xo{7iB0r<t`vce%<zG}Vm8x{5
z<wBa$M5PR8l{HkKmacr0R{I&su6-bx%5xO_J*S+%5`)Q7?%EF%*~-n{FmYbVr5i3s
zIr=rs=PEfAh|5!kdZ001IptXl@PhJx@c>*@CVfVqmb;|1A4ThB<?pm!E>a$*gL+q#
zzwHA4s&Wn$TU=BAsDPScrDQYuN|XyM;L4OQvmkO^IrlDb<;wk+VE%^k{i`4q$~$!Q
zu~L~f2(C)GasXqwsr-~m)vJ~9CqQl~(-;_wy+-M?3^KJ!Bdzc2lt#+b*DD><G3?t)
z*&g&YDQD5Mw^^xIfwU^OUI6}%vUMw*X;a>Q43WFah(3^ZCEEgj?<u9{p`}B)bTjOB
zDu1^^*?r|IS`v3D@5jQmZe=J9@PS?V3!TpDQGPIj&R%6gEtK{t+v&c4sC;lAGX2WU
zbOk?Bjx7ZDSULR!v^`O7ECd-)zMTv*s2rVu`5~ox8C)AyPN8t^h_dr80Hey&h0r;s
z^rGO#Q>E%ds2*3|<6_n(l=cV;$T_OUD7f#WlAVO8vuY1T_gqz3Vd!&HZMg#7?y7~f
zdOo1yQHaJv#i9uKLDf|H2*hEP@hSjbs>+uj;;s683q*WXA5ejSpQ`W*MEq6LrQiZo
zKhsZmRJEfLlE+kH`^RVvRQ0?I6G5su|G;3dY7-TS99LP}AR3~Y_9E~nRNt0EBvf^V
za*-!h$v)u1RMV(FEnJoO1d<Ud-Uon3s@|a$RFrB-2}T&LnxH`IDHVra&@n0pDU`*k
zl)s?ww5l`A4jQM5{4X!8`rpscmY@o!@|i>xpUQEQRQndgnPipc3aB}wTBt!|imJK?
zCQ?;LzXO-1Qqx=Mtg3{*)0D0%q}+Ihs^l6R%~WlraM3x{hdNA9mTEUe-m_Ki6s|q5
z`eGXW^T9mTxDvp8)f!qVUQn?X!+e3tupXpPmG%jAUsNqS1MZUQbOw}OR^^|BqeZH(
zsigUeDm5P>S5?<&S#?eID=jmMRUhd<N>t_bAf>9kT)@jzUz~&8>#83qSY56veuv78
zZm2F%#-T!$vkkf{RZFv>v`W=O%k`V8$}j+{RsEshYE_%x0avG5yBZ?(Dlb~z+*Z9r
z`_u;2pY*tER7F#zSd+@B0w$VOZ%l$@i|X4U46sc#YZ5%XtJ?Z6CZS#B?FkWkuj=n5
z(A}r{lmZ|RRoIK-B3HdZ+14kjU+G~#p!%IYZ9J%2Tmwr(s!Q}599E^g25wCCg$j0`
zsuJmc(2lDnXlRaVHXTrKQosH>v^cASDOc>Gp8Eu3zxwjGQ0A&0BoDpq>b$q1=7>5v
z5BHIe`Z^s4^HpckaU(zVyE(AruO6kdEdlCX{xES=y_4bz$J8d8*+6yvG)M-i&rt+D
zSgoeL>~VD|ZE!=>910qrP%qsJgD2G=({&N1o_-a-LAcsV5sL`5y@Aq?k?NQ3f{jvd
zrRPnITId5{tlB9TeW%s;{@c5&SGL2^c=ca2PYLQjsU9&=Ev3qwB=xg&iZoemNC)7I
z+9n1(MV)^VeW_~Snc&jY>z701toqYGAd;^B;a~J+sHfYT;Z&wNdNu53t7`=i%~h|t
z2`*2)X(LF!`kkkk#0zTX|G*Wf$J+rcR11E?BwSRFQ()?n`m>Lr^s+kUG2lgNthRAk
zs%QJa(W~maR333nJ(HHU#p<7b$5fW6LpB0Xs^0HvhfJATKwF>d>Q(E2FIP`8gS(;b
zxQV_BbwA}fZ>ncUfHbHVt%bjh>T^>t`X==-RSz_)PyCIcwWya+<$0?*x)ofT+OQRU
zch$p`cxzYBA`kDWXHfj2Lv8pFq*J}-zptp=R|{yl(WU-$KM)Vp2PyF1qn_;nhkMoc
z4uk7cub|+_L-lJZFyF6!jgs4s)Y4KYeXL$&higyN*S)|EsJXP<9#qf$88b7i_N6;+
zM6INk#Hjk!KhZa){+KHAo~mEQw>s=o#?{Jw&^@6(^EZft=I&qUbkt}m9^s@}Yy#d{
z6aNQ*E*f8&uKk*ld+@?l<9r`V-88@KhWG9oAzft$H2KFM>7mJ|oWx<xG^$MX)^rR&
z^%2d)R1DBZGnG!!_-edpH)r?LBvO3YU$cq|q>pKSZ@^#zHIWoX3DRUTp*vXf*HZKy
z*SwSkV2I{t0muoBm7<xUn(uGnvOKAo`wp~(YxYwtHbPU>1(8UN_&AhBX+-M)kJh~M
z4$Pm@EPM*LV>F($vW~TDc#%+ZTEp7|HF28EH-U)P*q(!$1kF|pNRs9rJt>kkCYs<g
zno%3nq-gT@LuslejP^rkHH}SBnyy)W172ikR%St2rY0`~BIh)&almD1`tE?s*8EEL
zax||}>L^!ZkD`j&JdJ}0t@)bbRZw$5)4+gl1sXH0%nLP3gfMYM)ASDJ;;LrjW%OOs
zl+m4DtZAi^^%BjQN$4xnG|+4Rx~8HDedU^+HR!9<d?^6DO5;uSK{quA>0nW{Mo4?C
zTbh0LivZSYA}O|6r!mlZ;(ARH18N#Iyf@I-r1{B=!8B_=nFK_Orh>wAt(uGr0Nl|W
zm=8dk=G1SHY}f2R2FZJx6sk4v(EL_~zD~_WilW@ttUQOA>C*7dgLG>obU{4O{DZHU
z;ab<sqTJI%O)KSB`!&fWQ1eK`rLQ(U)|{|G_Y=*OyXYIxRMRGBNOPa^S;Lwr8FY_m
zmMnqDsOGE~jboZwTcCSFv%V0L4%$~1f;eh>D753GZ4<zIXKgt}qFuC;0;tT$Rr~g9
zka5!n27<V2zv+eO0qy$~jq%W)iGrx7_F^|2J*@Sj`b{rwvjiS`Yv-Pa$PumNa}XbG
zQ#;_k+DOWg`DxWv5IL$9#G&z+Hj^SHfm%QM?Sr&Uw0{fME_;pczYy&o-awqt4&;M`
zYTpY23DdUB#CXHCTW?@yBDA3%nEXiXqKz;gr46_VHPPC)-$Y-GHi=FR#cKbW41=e&
zL7$>APW!PBMB=p{VTn5>LA#5d?n&AYmcol<?K`CGjP_$%RN7Ot)l{F9s+~>qm9G7L
zJ7zsY`=<$NGPU9FVuH_Ub4Vmhd;SC9v$Z?P?s;u`C_K#3)>67AS6f8&L3!HeC@Pq*
zO&WwV7qqWX?72WY<N*&0wRfpb{GxVe3JhJ+`m9FZWxMv$=P*&EZKOJ(tJ>&`@cWw9
znSRk??b4O-v_yN7_Q|DM4^N1cX){iu@4D8>1Nd_7y4BEjL%V^3Dizvi<6*v1JCDMy
zRobj?0l29Z(~`VeYoWB%E$svPFmsL8o3=Hz+M{33erBq@_kAd-*LF}1>1}NTRf9BW
zU#DW(CT%P|E}FF^l*w$-o}7!mR&60AP3~w#<#4P``*j7zepkDG9s1g}A}SQQrwv;J
zc!&140jTcOhEt`~eXWVo4P9F2Pyo8Mzjp%uKs(t^7krPl_EnHx?E?xN^l5uOhnjw^
zy$!%e+OzbEd8{qep>I&zKs&7=?N66LhP4%OAS2qX^okkPdeXyrOsoA0Za>vdP}Fi<
zYoGx1gmxc2NgQ;AThQmITW*DUCtX-5Ekd1jo5>3oT?9p*_v;#`qS007L<JCTx@GY&
z@2*?mfxZK}nVaFhhc06PlW<TsgBHJsbnaGgp1PCSz#Z1DrhK=TPD}eHZ{7DFVJt^<
z-Fn#d(e0<Dov-dOElK@!;jxr!_1F2`1skBtz6otdbqy<kKc>q}gtkDPA_`oPZi1HJ
z!Mgjjf;p~xsDT$Dx@RZg(+S-c+8KuG3|#=6)Xnb)iO~H+@8?L}ZVEd_>Aso;$!J{x
z1%yuNCf<XV7+n~iOZF+Tx^TJ#PU~KM0p{a$v5nvobanJVOVky|fF$YOqisd1Zqyfc
z({$C_;mlc`Gws~db?f^v!VI1GT^P*Ny;Xv~bGk0t@@MG|{{v;&x=cEIb6!_YaitvH
z&nzg*)upe8qxL-ACwtJDue%k9&I`H_daxAejI?Db)TQl$=tbS1AAwxbHD7{>%eoR;
zM-}PBbXMew?wewGcva_p5agOJ^FAbtbxw2zmgq84AX2KUC<CBO_gWHMyRHjfhQ4xL
zwh^;-!>;QZ1foLMNu?!~x_vZzRk|e=@cX8YP0@&IU9=;}E!{5^2dL5UDKk*3o5O^*
zI^BE0;OceX?Evn!&dZ2lH|S>5`nXYtn-;f`E;RsNH0wOppsz*eMfuED-4Z${eMe{C
z@e~7X(|u2;vF_?RCqt%P=QAC^d%DAG(b%Eu%mmk|V|u~S`??AWD0S&#--2YfE=LbF
z4|G4#v9TWAl=*PGSLd|=2K#jV-QXVT;;w<~*UfN%p+~y6=<W4bxA+eHeWJ^@&jcO7
z6^IcI>Ne4qazwZ1BDhiASy~s2>HI@Lp6X^Fg^6+9i&X47q1!hHN*(k8?r3z>N47wz
zlm6%&c<8L3Mz32J{SZB@_UpZR0e960eh0VR^w%6A>8@`aM&ki}dj_ppJoM$1gFL98
zTLHu&{UR}Rd+L9otL3nM1zl`j`U_t`#9P1PIy^k0_o3jpk3O*g&iLx<euhCm{ozQA
z&|klbQl<fV2EAI2>U|tw;h26Q)l>!QU!=;eAbreyh=k~uDkunZQeVbIYnWa}E8B3r
zIsv*P^mpiC5~-g>#ZgiEClqLj)<@IB@05OwqUkaE4V^F%t8b-j@@f6+KS4{J-kAdK
z@%meI`zGk)<ItC=pD`JZCh7YR0iLY?kiIi=MsFXPg!?Z=zls5wRQ)jRCDZhKDXV){
zuc0_;y8i3wXw1-mKv#FB{#_;-&*`0OVK+-Z`z!dHt^bt+z<K??Tkt7I|3w5$<m#_1
z1};zEcLk04dNrNkxS$_?6^#Y@ZeM6A)Vo|lpZ%hKEg!9y^!OS$ZZ7?6^Wb-pUa<rY
zU(xTTH2+oonfHOeroYk&FN*c?v_UM<4@=Qks^3B<EX(vAXED#$_1Pkja{VDAT)Uy)
zMunjj`lr7DP^mX*p`}W{WInXq)OXX(QEk`%N{jtl`d<YA*62H*MQ5%4Vi53k`jFM|
zv|hh`EBc!C_nyL1t3HzAOLz1$T+r91|B3FSyZQ^X8Ee;%PJ)Sh`Z`(@cIa=*FtSel
zM<eLFug?-fvQPhQ9JKW79qGb<q__K0RQ$0%hSFz)`gh$irXl?q3IPx67t%rY5&cv$
zKdOJh0U~4i8NJ}1>Jxm?H?9v`3o@ZkrDwK-K_>&;(U7SC=VbV(7sT1HlAg9M2LBce
zX}=*b6<)X+B;_D(hBP}BqqrM7Xa|45@D=SfJPe~BVrT~qZQjs*$S_K^JD!FaJE8lq
zVc8(Gc^MQ`Vd8C=u?CGt3|H$xd<;2X0`6;Ac^kyfu%#4@{)T^cLQ8;Q=@g9jsKHGF
z_%VZE6)XfAhFd9-6J%(z!;4_Uh4paixZzGb42Bq99RuQo!RaO}g&Kqp0X%7lGD2yX
z;hWz<!VS}RpfSR*q#Fh!4SWr_D8mn@F{9B2rz?P;GVGa*#u$TC0M)UE11mAk(}vrd
zK;jHPzDD<7yy5Mgz$X}PzX@j&4NY`!CmD>N!KY-yWk2B07{ni=F~zWymVc>+aVoz`
zGvp_r@2p|*a`dGem}k+KVVKzmT&AJQ1TW4RO0&Ra8J?pTU$()OqP)3=fB7JJhR=SZ
zT8DhYYA)1VFs!En?E=FzH;lf}Fpa8YFB;yYlKD%9rtJ{9Y`ElrQ4|?Ao`%R3gXdf{
zUNtxjK;)X?pN;UM*wCfH&`JzOD#I@|cxJ$SnPL2O_<P;3V<F(>1}16@r`#~qya0Rl
z3WFDIS1S$kg27f942yucY3RNOQf>H}z9)anFu4k(#;}xjJhg^6H}usRe2+p+y<u%3
z%-=SwX@N+Cq550&H5$G*U@n>rBY6;MHuR|=(qbsDL0_w(hjJfx4DK1Q*Jd{?r&q^4
z!#8W-TZdugV#stF*1dwx`-Zk>FbQ3TT~zAZZD>CUM;{m}s06OZkZOiVufeMTbJ1rw
zUkdJ_VcYNE`VA%vBp(?bP$|q~!+Q>ZKQT;D6l1`kZNmf&8h($2mLY?E_&JCU8|LMM
z9WfMAAbQj=mC7;34C|7h^r@k%5nhZN9BGd;VfdI<#16(SR0!l~96XLjC*!wsA>wST
zr!R}R7*9=yvi-*A@raq?YTUUGUbq>1|3#y_(LD*|fKk2~hCGZb?S4QUG`>f{+e5}H
z|3ZzY(U-p8c-Z)G88|Ov2>m-&Z=<slEFCer{sp{`vHu?ce2pOwq1(@RryoCzzj2Tb
z`UDuA9zpV$vC|vyKx5<k5D7At(1Iq|*h9O`<Hq6)kPzekZmKmpVN`8GXQ<IH3W$@&
zY4kydFk^2C8pDmJC_@lo%#B53q;WhCa~WlPkupxv#<!>d;*@bkG_=GRy(JKdHAVzO
zOT6*JPhmH~m`Yj0MB@j+@Hff0_Z5gF8xyHW_KY#%9G$gHF}8gVHq|)f2bnbE48ms^
zA9w?pX?)`tCg_}Tf=*_iH;QOWnPYq*53c1Jty9sLXWT;<a=!6p3SwR`eou2)VEljr
zvxUZ>Ec9K(H|T)7WV}a5dM+DhZU!kb-uIwdzbnRt<8bP#@#$L-y=JVUd}^^#-3d}+
zlvcuSsnL-Z_+`d@^a;Z2#vm$wDK~!dER^0bc0UJFVRSM9P-%3aply{=-3#ufaq1>a
zSGCcLa$>iPVg@8@jFWdlS*`J(Z@}5>jL|0{Q*Uf|59GG7;|KWGVB8l6(rC=3ZAz2T
zleTuv#)B(>Xff9DKw6D*Cn&vRl&`_8wHa@H2Xfaq^fLhM#u;A&e$Uu7hQ<zKIu}1h
zr*W9xU-ykmm!PrBxV;Qoy6wi!tzaJ*<LH|aJ;r}0!1Ws6qOEM7aUT!lp)rx3F#X0S
zt1#?G#;7+S`Pe9=V-in{59kFlV4U^^L<Wu1H^T0aF-`;AuyM8qA|u9a8!)m_;|v4(
z#*7CkclgwpNNL7#qdk;juoFfJRZcjVI-8-**)+2VKo`?}DoEIGDxzqFt7(}Al5VDW
z7C3j)OsecWU|K;r8xNBq9n*c#WTPkBA=5TGSLJEi{2qKdY?{^w&dc-_6{~uiUhIaJ
zBc=mRkn}M*+9~7gYvPAMsh{bqxlrS8TK5Pt0j7ByK#rQi=~;BlG`t6rfhPBZ;DSs$
z=}{PLO8yIt$4!?f0~cbdrj^?XQySfyp{86hL{6GcQ<62z)Ug>N;im7Yjwr(P(sr1S
zG>yd4{x8aOryWY8O{Gb|pE6yhrA&<J=nxRGrZ%cnjyJ^~1|q@Kun9ApXgWcmz9iGL
zv?@$C`7DQ{XH3#pF~Ss+!Vg@k$txdRn#pqp45piI{tt~Arbl??OvyCu`4qTwrtcW^
z8MiFc!&;a)ZxW9Jkz<;97KmKawnCWCGo7%ZFW<B~0l*6;4+=qDG^MPA$R*R4X;6CE
zboeyfE;6OMgS%qdL4{sdO>g~oH<=RYOkJ^QEd&0Rm{xDW$VyEWet?&m22du0e+pw#
z(-W%PR7Cf|4bvw>Fi~M@y8|_qrcR2pR+(I=6yT<*?>$IXo19;VYqv}<QPQ%;ludQG
zwWj!Ccvxpz^&v#+O_iU*#BGx(70Mb+NfPumnx1(FjZLO!hM=?AbZ0AEv$vSqsTTB(
z3I5_fGJU=e<eq6)Fm!jA)>DyEr>QCr`1>Z#`v7*CmK=tfZqx4;;2)TtpAW9bR7o{x
zy(Uje#`T#ZY4`fjG|dZc_nSs)pzMiBNDtislj9{Q8#E=;eLG|~H7o#r*tC--VZ`+N
zPW&>Xrujz9#h7WqTmYY%Dn15q+~l_tj!u~J>E3iO*U>7=$^80D@X*;jN-04X^O468
z*>4u?1i;n2^-q{^GcWz`RGIljs+>4tewT{ge9RB1*xc7_PmX~>KXX_n%=?>7FGJ}u
z^ES%T2AV%^13t(s*ah9e=KFo<J8o8MAsJ#mMoG&P=FCJW4K*u_Xgq0-rL1F^`4FuI
z!p*<6fr~H)7D7v;xi$zoqs%Ki&=_qtP?jdy++^<q{*1Y92y>Zgp45cFq?up%723|4
zm(X51-MsvDSjsTZdJZJh{P|MoK4-o$14^^ZUF{e}w)r~>lASlt`VAsE=2ohq$u*BN
zA(Ce{Bh)t~-yBcHXBW%|C@@=K*3t5&&^)z_7M>T)iRa<XC3BY_bYC_reuA1J^K*3M
z>x%g_C9bcUYh%!N&3tx0@WtkZC(&18F5e5grRK)hpu5Z*LAl=RW(95N%gyOc(0Ri=
zK#o?JzaN80rTI8LbgRsR7tnXpynP7;L95NTD6w+OESZ7M8uKCA?9`f-qu}byJr5vS
zZ}y>WbEA2)7P_0v56jTlZ2tNyh_slWqdL!4^Q41t?T-1_%OGv$yBTP_Yfjz^@7v9B
zf1~l9`6!k4cbM6<zwR`DfRqu=TAFXrM{&B$8F$dyZPq$K_XBgB90q&LWsxx0YyPbt
zmio-E7lV6fu73>!?KeL^8&~Hev-dw}d~6=50sM*C8V%fl`6r4l51M^`M&FRRb0NGK
zHt(Abz=%1i1j8LQA9@}D`<QvD8_Yj7pP_FxjhpLe4>4i>oR+Z;mPD$+bF{4c4I)k!
z_uqhbwp399%Ei)5$&dY(lT>KpYPrUThi;Y^sQ|;nGDhF6I%v_hz>7ncfc3z6TGB&-
zJ8YTk3`sA`x?K?Qwp*5jz~B)}7DZNlEZZjm;cMBx0SG@!*#~I!x5QInTY#nQ4-5^T
zIvPaZG0XDJ@F~!;+JeCZS<+I_7;NEDz1VR}1O4_PmH?_=Ibm5wk=#&=l#+laE#Lf?
zzP9Y%124iY_8V`(;RwqorvZ$#WKaMz%92%uF-2RVl419hWv>m>9b>W5@;BCUnj%D}
zEhCgnkF$LI0UF~ik(=Q~f+Zmgl8Kg}`EWGJ5_STrlPw(uFn`8!j}GIcST;}vQL5!v
zS|FrZWcC!$vlbJD#L_Ka(-SJg^3j{nooR7yMB_P&KkXW_EQ$Al&$ckBqTsycCt9-Q
zSmrK-NUr6P5wn(O88`<n-?GsRXD(RIQ>LuIl0@ee3N1@%rFqfv3%wgJSxQF$zij#K
zbIP9;S#oAzOjj&r25?s`+e09F&9XHD+KMgT$f3K$GMI&-m0D)eV!GTCNRhZo%QJgm
zqRR3XRrK7nY@&QnwdEZK4BoN?oq*07%ag}2SZf*I1}$|K-@D-IEtNmQ!fnfoE2-AK
z!IIX2No=%i>w!#@#Y7L2W=kWLAhcL|sr0DTvcV0m-Ld>bfzvk25sDJrwU{?TTe~HU
zX7--t@B(<zVYy9-oKDO1O#s}t_)z$?%X0K7B)jq3!@~y_KRPSfW0^>!_-C&rf&O_`
zpT)EWmL6Ijy$G3p%l#2>k1Ws9S5zKbE|mlS#PZe!a08a=P;i5mH*Z7tkR_QS(!-XP
z+2|XwJU<F$qn1fI5E-*Xy?}u}wY)?NlW|LZH2@Qq9?G&fSe?2dX?L_Lsd(GTx}M_O
z`>m@eaO!HkF%QJe`iPcw?$+&P=sRHb3I_483TOl8X`ML;a@cyEB9C6y^84uXvHnY!
zysvfLE8zUBZ5uG7{#Jezlm%E{A41<zYk4C2f~+sn@;BISo&OZ<ajOeGK0>SkHgG4b
zw^bma*1fZ!`=qr!3Zh}wB+594Tf1I`(g>>u-J6ltqyJUqS|dJ!NVIhkl{TNUMpE)V
z#(Kj7EwR>BGDx1b-d14Pan|zd&>3%4%){sttaigaOiiM7E!|^D))|y)NVWzxfIDLy
zc@5f9tW{JDmTEPe0x-=QN4ul5*8Dedm8DxN@EcCauolu=G}F3<CgGfQDn3v#CCfT*
zACzTVmtBM8d22JR19Pl8dST{Tb6!Pbp7n2gD-ikC?e{<~SkwJM3aniskV0$M0@%H1
zz3l_tm#hvxXuNDKDuQc8)+g;~ykh;39;{cbiwdCon)PcjNU`<&e<1+thYw-C)M}w}
zrZVdfbUR$P22$v++`6s_<c9ULM!NqhtiC7FS!vz71174h(boaIX}y_>p;cR*g3x%&
z`nVk;HP%0Gp|95Z@~4=~I;(d*;PuwyrEuo9btT>R4c6wr;dZn2T`Fa3v4&BOpw+r`
zHE?&VYbY??W-T~^OYW}qw{p7w+O7Xi#bn&GK2JYIhqZ?S)ScF%VyL-qz5f>)yR46B
zMbmAaIuGN0V4eRnwDnkr!=SC#`dt7T`>bmyy7<t#Tn2;v*29?~kF1XtLG@$nP5MCA
z6KlY3hzwX0DPK2e-Lr`PmC2BG&1np6*!s;ukP+)kN*ElqPVND4%=%&-M4wu}rHggk
z>gbBT3G3=n7<8~<mw=a(t#c~;b+R2vfrzs$mo_9WwhJ^D`)yr!Vb|5R`3op>v&kEv
z%-z;b7t#S+<x&9b9ya$BbRM+jE<ooY+ou#Y^R%6#0NG*NpW!g!W&4zJ;@-9ubX4?+
zO>+XAk8RUDSn{>~Krt3S+X9M+`P+UOMPq=?ArF#AZQfLzd(3wCD>xHqYjuG$LADqw
zoDa6ip8{~)Ze!C+HN^JH+c0>-R^ALQ)HcL~Gbe3}&Z05Qb}S6q!fk%XpeDjLzYrqP
zw)ZKzamqGj3{x6oOQbzOoNZeq`r>W(Cjd{d^=(97vaN>R>}PD1;cz>}7EY1jRNFS%
zXr|fhUHJf>wXLL2$z<B*-N)3NvvnK5W!VC#{43k$Nqd0vwjGqO$+7LE1z@gi1C^%a
z+2&9wK)x-3p05{d0vRk7*uJ1b=R(^dD#yKO`}QA@OSUE3AadDeuSZ{zO-51QE4G7n
zs*Am9n@(5vHCs|P@WnP4dbgI?E>i}r)OL{a-etDGzlImrZH^+$Ub$^W4@Q5(7DmCz
z3R~k8cu{G4^+$+Q+4%G^#+$bCAp8{7w$~`abITS;r`Bt1d+C5tt?ivv0Myw|mD|x-
zZ*yscH@9uBxd1lUj2qF}XiNAJq{)^`*HyFa{~TR+T$a@rSIaCdD;rv-nWhcRvaBpk
zn^u~o>AUyd`?Y2HGGq!U8yO196a)kupn$RjMFkN>0g)j~*+ZuOzUTMX`J8*t_ndQ|
z=XvjQ?>Xl_?-Q};Yu*ui2=2G+_>|s__jVW;Luu=d=FK2&J4Qp`cKeQxXm`}HqmG5f
z&K(Z&>HZE`8ytPGV>iuOT|4&g0qNc$8l}I|>)DaI35ebuwHM)A-;Un`V7GsVo=)8k
z?D*n4hz{-uq4dYljutv@G`!;#dO9EO_+=-Qj_k-006w~7eh4JTb_~U%Z+yo+1+M7C
zj#p{ZFu5c6SEzop!;LDnoEhtyAnC%0yh-a%SH^EtU+2z<p!0ejjE~nssVAc$8VD~&
z<wwx%&FDLdzP*gvewg=RXlP;M%Xo*Xx%?PsX$Q2A5!Qpo{fr!XfB7>OJ`1}6jIT|&
zuz`&3KjBjlqjU)j1vAW7AsNDmb4H^hlu<`t&I)7bXbL~T*s&cXoYB+_gHen(=+x0c
z#s^+ddWaG34olIDXK9ZX!`Ms_m&1%LGcnL3j8@tW#xizOeRmwA<|sts86Hb8&;-VR
z*WgSdWBF-lNn#|gK;u!yFYf@J>|k^TfTl2Z(K7THqlwmYsf-(xBuHaCqKde5#v=L)
z%j1k+O}H`{j1`X{naPl1^*%j|(e4D16O1?Gfjh~VK~vHxM*jfdry1;nXv}70X#me*
z^ip*F4C4VM!p<_DcoJrF8QSC^$mB78z5$2x89}r&ILBC}fy{YE*IqOhFcN6qC}fn%
zp{9s&wFd(&W+>7iS;9E*JuF>d?8*gK%D7t$Wo3+?>!JH1<IX1ZU1pR~M7e@d68hq5
z99)?%gXDDv^IPbwW;B}N?+wQ5R1$iV;r<F5YZxEX%kUQC)9=w&$M~8SE%l7eRAh9A
z5q|}qH89T5ru!}<ZVdJs88;}g+QhiF2_nsmF&4D6Frr6rC+;!sdO~$OLrCwR4u-`+
z>$pzF?^}TAVyyQ-XE$SlQguCyM4C(b8GlkZet_}&e2_tg-`9|Q$jDBE(h<gYv!P~`
zVWl9_1Y_F;^i47<DQfhHVO2w!GxNp{XmMdKbcZvp%unw?(w#Y_64%aynYx?eJ)X?}
zyuj{d&ZNz+53{rZqQ1;KvtV#P(-aIf{><Ai!e9V1YY=_G%#OK`3}NO{geR1Fji%Rd
zrd5N!2<H2pP!`ENP5G!pOdXZzM>AdNS&3nm(YH`ynY(@i7sq^YlJXt#%$}z)iX`UN
zDmZhLIbQ&h%zT2%A5)nLlkg&qxo00tq%%M92A9dyS>RI^b1_ZbCz!7;0pK)q<}>Ka
zX10C=lEZwG7L~co$b8`Pn2pI$me1T831<qJSy|u;nSLk&b4)K{{!VMW3(Rd4PcLOk
zqu@*#GxYzb9+;b!LQOUEEWOQcFoiU&-()7!o~4G_xEr`z%)($a)-iwI4!iZthZNts
z!*uonpn>@fWk&8Y*Q|uUjm*9qAWcjMMPZtmO>|zy(ZWnT3H&|gg1=zCmHEmZaBa+g
zRs-L`eDfl>PUd<OMDH`dS_``mm@FHVb}@H&V%R;*(dTfTdzmG_!)_n**F5O%XI{Ds
zzyMRGL*pRx9_@-AGWQEXMwox~LFXv*0^Rxv2XiC~qLWN19|j*W1&c5WCsx)~0G(O0
zsh-G%rB?vq%DVj}`u4EgHelH9tWrz{(>++r>CNuR@}?1bvHVX!nKw(h4!FInYzjX4
zu-*#;@nsdi4Y(i6lZqktvBdj8_Ol#;AHofP)(4+LCV*x55=sMEA`a99v1(_bF_;xy
z57$Cig~wnwl=YJcB#hPP3j6`qyqC}y&icd+l2I%jJu?Scd6h7Ki1m6X#(S8xuLl;6
zu(Y#*i)Dqs1xFKD>%WJgM3##q2>2w{8#-u9VJ+@K=P}m2cQE=?){7rQ&2d)EkMKK#
zH4z0hnXK)URXfRg?iO&TSV`YN&1u%pG~JwGoy$PqSyp^B0J*FO7a?+vC8R*ydDgsN
z;7kFleK$r{%qpO8UI{CEivyh(So|`Gma@FBz>6~0{n==|$f~2??<LlYCTJ^X4bxBj
zGHXK=EL~w$FNergR_iy=R>Asw2fVn(8djpOinYWKUR-A-Q68(B<uL=~25T(?k~bj&
zTn+0_S4iGwEsUUiM=k68RN(7aS=-@7J*y!CcJHv(6#>}5Dxu%eUDn+7FyF{}>T5XD
z#M+V$6V0qw?*h=m+DPNQ$NIq+q@9&VMd}@_F{&u)Wc@_vrn^`Lv|R3Hwbp>^VcqBl
z>173A8R(ea$8uc;6aB24RG&1!+PDP3LDsZkcrnCs`2mf?tna8^=OL^0V~`QnbsNYi
zYo`Tc8e?r#f*WTQQ(|?3mHh~0l4XsB_m5bbT_BHHpHW4R6Z<F+gK%aK)PlIM=eeQJ
z;mV#f3!Qt|TG~6fu`&1I>1KcYG&()l3toUWPj*8oM7-E(To7;e@Ont@Whd{48Xxv5
z`ZAv{JB9M~e(Y0pVr3sY%nyD0*{@N#fj|5CXF&qkm37b=$i8<QB0=oJTmXU{Y}rcC
z5O!k%)P%C9KM$EO_D7T`IlzAFC0vAXHZKWwBiOI*f|^LS3zhpsu|E&Pl{v`XK?(Om
zY_~;djAr*xm0b+G{AUc}Fx%G-ok!Rj+RDbVU&#a)$KIR>E}mVjg@pvR!+#M>B(jgw
zw3Wmj{uwv+C_9q@gURf^7tol(o_!0A$JoEEgzi+fBNw{U*w4{9*>v`M6yQD19;K?T
z40e7G0GaI7w8zR~FZO_zQ|$M>F{IOM)lQIX_VZM!pTkb0>bEoO9gZBhf0ms|p60S|
zJq6u)?2B~0^4X#E!#l^`OGW+X*(?f;7O)euptO*EjyBIl?3>deQp^^efR+;W>R!Mv
zu!pJ2sg(U3WxUJSYbMZlk)1}RK$qAGXY`e`=g@iY%WQiF{r;}7Bk36SRrWj%>{hU+
z^PsenT}u(7YwUmNR#vg!*o>iFXRoD=S2cToB^qzAYiWaflg%4NUk%$q&&4ga3tgw%
z?5ZVDR?B{ag8OysE=mN~vtzyC(_OaF0Fg%a<SP2MPZRr9Is@O#erX&sE$qfHn7GF_
zQ>MO^{ShT-+Sot71#Ru@pc&}vV6Sk6WGDNd18BU@K2J~g1NO{KknCbR=zv2v+x-kK
zcMp4+9b7NlLNCQW_Ix);_Orj;3bzN?b3&)!_czGCoQBa4v9qX1ewcm91&D|2>;||v
z!k*p<Zj{}-3fvf5^&QAKdrXZ>I>Fws1Gq`{?`xp+5xesZkjLz{WQaI%-lKcx%vtIW
zpIkUehtcTDdHojv_HeFD0o;xAHx)EE+&O7?F$xdPF*+mT$!Vs=tQSX0lbAPWK7B%F
zFXws*@IIU?r-AV0YzTxUKThU7sM*KSY(V3FPWvW|*PkP$<a7Y%SSLgRIrleUNI{(c
zQXvw|d42_ShH#$v5`CeZS@WSY%)uEw22T%go}#LuaLyVoT#Vo>rF#&`N%eq<D9!;Y
zWjM&GUIXqBXZb&njOH{X0~f=YO-Yc$oRV$ej&N4dbQQ~acN$0>XXaj*i08O=L0JN)
z<r!!>%DMFeEF^PY`~;0D9LE~^ntmGR{B#UEom0OO4j<>-pta&@j$aI9&Ty8#0X1hi
z?X%FB%b9T=B#*O(BGLJrD(XAONnZw~=Q&%CgA{NI=-6o?XJa{Z7IVI&dbbh|_Yyq3
zz)4C4yp*G*?^2X;B#stbuZx_dpTL%L-X4PJWzMGm|0+1wi(&pMXRr=^6&$AoxL?WP
zQMTtAXUQ74UBxMM#z3!g`Yq_I=EVE}6E`@i&H&uxY^KC_4QK3KaJM)&pNF#B9Emr$
zTF#c=aSiJ@i%J}Dzn+ub0`?B4nM&gtIOp(OPQS~^I1HtY9A64LH*s3%#x`@pJ_o*q
zla&ff_c(vj(y5j67HuEfINM@?Yv;VS7m^*EWZEh{;LN7nX%}Z&JS4k0Q8z()INgWg
zS}(^hgMNQ~9Nq-jeoin&n+G^=Q+QyIv+NVx*db2lRWuHB(zik6A*X&id>Y{d(#N<)
zIm_<gT8?o(Ux|w_&JjO{#tDw?0U9Sc|N6qxBTl9}$YYK(!JW9z{Q&P>x%2<OkmB~s
z>9hTATz`6tyL0oOL8k||>@G}razj)Yg%|gqr!X{cZY`C>?dATs6qbCrMU+JG<+@M?
z%8xsTiU{^`qbQZSpSzAqFZ{V*z6y8%H+LAgK<@jr)e7Qn`WmW(xzlLtAHpr5ABQ89
zE24yZ7}xzXAP#V!phqv9+Y$k#5!_!W_7%yEq<u*g*Moxe(cF1d;TFUFRENI9Tw@!w
z#c>sXfy8rzzk-Pbu9&Jyj&h$)gh(>CmIqu4H?jk&)3__E(U{I%kqhp)gL|0XV_DqK
zXu*7fdzBW<C%NkeVemB9@)Rs(b7#*2K8HK-8%&(x?xt<RS#B*ofqC3Y`pio{_dFeL
zKF3`~5uO5WDFsyuxo<3k&LZwD3Xc_YS5i$(3D-(@tCU+^0j`Yecvk_3FLHaMV7HvR
zn+@(V_c^NeyTbj07M@qRCBHyv1@})%243T?pz||T+-E2Wd7YbA18vpZ;X~kVaJ3Zm
zy~+LYYc$^G-sb^O%gv@KxQ=_f0wVR?mn&iS4tJdeq=DPzhyda)H}Vv2P$M_s6^yWn
zyPGETPVNF)y4~l#e*xqH*E9q*U0g;hfZg1kv=i^;9;cjDAGhHRaQ)nX<G3<|TzC3>
z&_nJ&yU{no)qMcKDEB{#FOP90r_eXfEuk{532taS6-`WXS3Lszh&xE{^vB$JG|xHl
zcGJV=%-j4T5H7rh+rYW=R?$1kgXgjqjh?(m^ptq<UKs@3o7YC!^u4@{Ao%OUOM3vj
zzPx=DB=_U3qB8-3yu}Maf_P874#{9%;UxWSMhLIC5r|M;Fr7~f<9%6-Q5@hMq@7GS
zZ@>x?!JGFJ)I{?>Ps4SJ;eGHC$YGw-8Q49-Tetxvme)jkr8wRz^uvkgCD*}30&kH5
zB$0QZ2_rkki=tFYD$kEnM`^s_XDHv1&h!2P=8y9<Mhq>3S4l_fGI?*70+_{ns|iX^
z@R}b(>1m#6I!HF}o997tcv~~kcZTQjA>2O8D|-)Ga(VKf(U`}3-VGx8ynmvh>>O{r
z0m{zvim5K5fcMTD=quz+A4a32l(&o)%w@cIeCccYMV=u6zFp$YosRLA^OEJzcA2-6
zW~M8=7pN5BDzD{9D6Qc2Uxc=5UgO))c7yi>1(9y@x+tJl!<+L2#(Rr*x(zyS^E7qv
zu$H&}65w^bh$2|1=bfbFSd)VnMSHboUe-BiYvCn$LEAmv)l!gF-cow<+jtW-@S>g9
z&Ijq>aVTTn$@_E&+Io0j3DDTf`<$|ueY`gg!csqPh>{=!yr+iY_8>3g0|172A8&@_
zFfZh7kcYfY-mo{ubG-fx*m0gN2~JJ$*c*YE<bC%Mv_0azN%67AJY6xgIq}=+0GTsC
zj<TLEd=aJST>1a-p?eRX_b-SWUqb~t-u(As!R_UbVgESYhyMlbFn#$4DU9gH=XAl|
zKE8w|zx{lT!v_xg^B>>B#R%ZLe+q-4{LB;#JB+`LX0HSMy$R43&Oc4{h!OmwRInY%
z-zJCdD1IyL2oCaN>4fVc{wRH&G?w2*k6s-AYkKtJ`Pua7CGdwR5SPgR;V$4w{Ht=1
zqx>&!IG`q(A5POw3cv3Tv>oTy)4}`<{=GmroXLOOj>as0Djl#r!GGf+ES=<kzZ8H|
z{81j%oaUeOg6?eo%uE<O%P&0&crO3b2jKGft7v7N&ktz<;2i&h2*A(t=ej{z0l(uz
z+W!^u*DZvlBL2I17;iCujEbX6_#gGc?gf4b1)a<JYbaQ8nZLLiYOe6-(&KTJKgoxs
z3jQftSyb|8P`>dRKb{K{Rs7Q@p|ghHN$<Z~{Leffa+{w@ag192=Tb=4@pFHq_)9%M
zd;pzy__50YY~X)|EXed0z8eLP@9|r#Xl&*0pyS_d{L*(p+WF5OhtdxIMJlN1<R=ya
zexKjE38a@lnu0so$G=L?dOts<4`hI!w+L<z@;_q1?ht>5E4&!y2htkC@sJ;S32Mgp
z(<%Hj&Y!y+WP<+`r2{7UhbXT1h_Bdyi}0A=K>J4zL4pfRcnWMsf%g*BbijnS;IJ8F
zuYh|4a38@YIYfK~t@M)c6Xf28<URo}20Hf(Rw2wh-CuD0K9mJG1dFLGGElH26TSrr
zvgv0WERY<4noxlt7)rwgJN|&00|J%@{0<jvqJThzAe<igD8a8Z%^no2p(?gR0_~HK
zj1f$nfR@98X1dNt1W!`9Hdf$ETc0>V>vWJrf%FxqP7*lko6&hx;6ktcWI=`wN>c=^
z|Im0$;PEyZQw2+Cfu1Iqp#?Bq5KU8fh9HPmjG2O0tsq%~BTIohA^0yE<fP!q<shd7
z!yOnzw%~OEL~;ZvD!|VOs{VrNvx5JWP@OACcF;$;@&wO(h3lLzNV@>1&IwN5K<9Zu
zF&$1T5O8+l;ui|;)1ibS!FV+A#eyDso=XJZ(%$fbz@J_jrGjRPw3Z3lGXTFRaHXjH
zB|$G`%*q9WsSvp=$Xf~TuLw5KV&|$r-$Hx53IUhyQ<dO}D==|gFiOd}Y5{K!`fdoE
zsJi&3;5SM{)d;Ge#wczJJWimmRxqU%1FaJrr#)W1;HA01-4V>8jbDS{t_nIE1t(}b
z)g;*T4n&#-$~)lh3HUxx)+*>{(|M;h!5Iqbv<p@?KzE1WzeIF)3KI8W6!!(G9|PDW
z_<Jh)x&?cxFqj^}NjkCJD>y^bMxUVjZ-@*CmeA?uK|#$NkRbuvA0op7^&A*{DCnen
zKO%VT1zd!2LH29FO$dViq<qIDh7J59!KU9q9t%QUfOiu1QCPxRI6zgtF2Z4&r(A{O
zlrY>QjH5T6n{Z<Y`rL)p1?ck-&Yuf_r*IQR8N7spJcxJ;cT=Qwudo<z+UY*R$u+n#
zzQV;V!1)Q8%ix-0pOE<tl<pUPLq&N0LiY%$2@obqp(ao$w!q;aA^SE=1Ph&iLSKmR
z;2|gt6-wu!F-+(pf|>)uU+zP9xbW{&AQ8fkDHs$foJA3$C}HgvAP0rKy}%t3-u(Y6
zR(R<{T#^`v(BBIt4hz4g9NiJ&11~reE7a4&8YlGm4xYvf|DhOkg0O^6j2;zAo`;EK
zVHoY$QiQMVfbL_$A|L2Z6*kdEH%;jF3?$Qqp+8_q$A#zVqdXbH0b1N;3PXp1%MuoB
zgyadKV`&>YPYP2hD}G9-nFqvaVG=F*vW4qaxNJGX(t2n+Bh38-z_UVmGt}e?J+`7R
zPnfNRWWF$kwoK=QtLWaH7q+|)?+b*>$AK#p-XDQvk?;zI9*TvJ>A5Ho-l58m3qtAt
z|68Y2_%(f<piJmQtGkQB8Jl6^l2ArvJLSUdOQGhn(DO~0uMl$I2dNakNK2V(!q1<9
zNR@E^b0F7+SHFW~wJ;?I<c82j`PG}kDfAYu5zeO!$1UN@Q_y%@IQcwoTCK3zlb)+O
zVf0Ht)C=Qj&c7ox*TBUF;m`9in7hI`k?^}wSiTPUCgGn30GfplDH+%z^b3aD_k@>i
zXlxaJJr$B|!d+SD>lFH&1b1JUNA)rfgu#m;(k0~o1)bf(VtO6*3a|e_>(4&n+f=IA
zFYKm`{ebYhA&hWPnAHT`LqfmRQ1eiD@ILS(!tIn@9u*EWLu5?Ydk-Sx!d@lZo)C7w
z4v|N~mweFoSh$Y@%ub@m-XJcbV2XUWia!4e+#ZpdrZP8C#XkDBox5lr1rj|)m(GHC
ziRv@qu(#;(=eP)aMXB^s^$|6H2I4DvGa2}OqHieIyk9i+9T@Z%MLmng08!>JaDgH<
zJzhbg9bAksM6`#(Mxml-9>aW?XeX7wM2duzOpg-TzXZT>P^5`Q=OI!23Xo{gzh|NJ
zuqcAIy+=gb>!3SU#JK=%aiW?!j6Pm;?lKw^M9&$4PZTYsm(x*EUpg9-Mem(}mK4#l
zA;6D`vIj7TRMD@IfTxR&Jq`GAQ9UgjGel=-oS6>M%bS7760PH7OeaLKw1+<_N?r$G
zwn$E!=p0e?ukibf=qHNMo)wk91z@hIk5Ux*qWNnvm~*0)uY#Nx&7%8TAX2^sgN35|
z6o)Jl&CEexiD)YQQZI;t=~rATO3eaSCUSUFLieJm`6U><B>I>_=$A#~bOis3NGb<+
zRWwYKP^D-J&3e~FnqfFvC2G2ZVP6+5q(DZs=pvO`-V}YG0a7D+qY09?L@q>biw@EL
zuU6DVIgL8e6I9l8M|8IwsvAV@4mCROihSu6+bGJR%7P}*R4OrR7I}`t(mheeY#>@i
z5pP0Uo9G_J<?f5VUkls=(fKamx<o<+yyzB{(Akk5(a|zo(LT}JXP~TKwBrSE10wBq
zkU^31FK8JOjnWCDVbPLu2V@?K@+dkvD*E?L40KHN^!xB_T$H{LWJ2^louZf&t&IcX
zv1sxG7<3YEqzY|kvEOQV;UbQm2hLUe3mxj-BTn2558cEs2cpkY97n|=UgG*dh<J;e
zsoY?%c<4hAA2GL*>b-r%-*!R9PyEN%Ap69pp1~;gi+w3??=N<%fNKHbH8e2>ir>8j
z-9chOF(iY<5B>!gB6cl?YoX#<op3Eo{Gb7L4~QFHM`O77&8rx1gxLFa7>pF#O29>l
z=jt$|gW?UZ()#m|_<hQJM~g4~i_RGFn^aeSSnNmd-6P^{7eQjhtrwv?PW(Boz~aSU
z=0h?;{KXuYNEFxe07w!aSpr9oip`WTPZl4g!mSkX1^W3P6Td|Z^i;8!mJ(^=R7z^6
zi|4ig=Qu9TTMtBr_z0yKGsSm4hiI1g_uruHl=ve`#-A2P`~=Z#@yv(t;;cBf75H57
zCL_$}i5+d=&WnQ!aV-kOzfx6Jq4?cFxLqP%Nl)$tv4OTArQ+fk04|BoOogFxaqL=H
zxa<%=d>`g3#JrEeR*L<Fz+V&ZNyWvl7Qd4KH8;c}ddb`rhtn~!+u{Kyh}4R2QR!5j
zSpEq_8pN9^<$YINM!}Uvv4a9?P2!aU@V8lfhR%7kh|jNsqxZxaw6kp$3*W-X+Qg2!
z0;p*h-)(_Y9pdM*Aah^*6(vI+h$~ir>k`*e@T^;$Lecpi@ku&j+b52d1J^I!MKjxg
zcsV`!gW^rJBN!5wbi$coak&U~AByMv3}qwYhm^h_6~9S=qA_u*0rtklD;;!WC&a__
ztWSzL{!sczeEu>-AB$tv=yQ_XF~NkhWbG<wbCHDHfQXyKcOMM8ORlzI^d1u5dmx^Y
z#9rw3l9Z{yc}srLLvpXgEgh0Rl4WKn^OMY`McO_|Czf8*_e=iaP^8sgvT+(Z10<{I
zXB;SzP~ljRWWz;}V97Igp(ae?Xhz=w$t^Pm6E1PB0w78fG7gc0lAf<Hm_rgdl_f??
zUZDEC7)drgB}XLhkHCDa<SK<K<0SgO(HAdSwFZ3&65b|Se<n)$BETj|UikncJSure
zyY6I(hNkco$<jt3PDmba!bLbK`IdfhrzGu6G@h0mqU1ofWX1OwOpfFiE-amqtau)l
z&PsluokXt0|4DFpk{4(rlP|HdK+Z`X2SLku$?XrP<M&q}d36$g7fPO?*|tdH^c<8H
zOGI8UUm_W0LiB<}PYc&l$+Qq~Ws)mRaOR?9MF^gROOor|Fi|d%_W^KO(z_XrS0sC=
zAnB?^b_kLclJZMvtd!g>gyc2J@Qct=Ety4iAdVXn&LMbuQ{vo>*4vUfG?~;&nmvH1
zlbpyyW4&bb0<_(cynYGz2Fce`VW~;-F4br?OMK^G*e#MKTF2d!ywL~AR!Qvvz}qCx
z(zR%p{5u6YJ0y%kkWR_w4`KJdq=SA<4;&KzV3_Zc%=#D?p<6QRF}NPdhFYlUmBep?
zXrE*`?NIwAYr>&)Kq9om?w}+n6(U2Df3CrqVaXdQ=zA!sr1ay6r1g1-j7nsbfgY38
z+y@z#w78;gLUNSShm(@mM{u<tNgU5E!w4Tsc2F6NlXSHNGS1Qmbj-v>x}E|Nu2L;s
zl0DLSH(=0B`V9Tl+@+nDVAn$`*@#9@Df0(#UeYQm8TOVgx&sq?rK|kV=p(&(1&zMa
zFk0UDNk?e!;V<1r5#<2sN{0qAfztC-EF2__j)oV((mRw#50PGzLU*Y2-!1^dq`}T0
z2c#buLBgfqdO$KlS{)95Bc(TAhGdj<Ih~w2DE*ceo`<AUsH`Je+8PCaW29Z%VCb;a
zu@8ohNWUwDWURCxoa#;Eq{8{YCrFKZ;8dbiO>=&dbm2wF9F^wL0i0y%um%_LnDoD?
zFqkUk<pYo=^{2gihV<TINM=f(rYSf}x{Yq=38||M+)3#&B@CXDN+`K@S{hC7sBGyR
zO2g+!PoAfGw=>deArNP!!CZ*uN=K<4D^J?`G(_{IEg!+)Iq8?xFn?YuqkwCHG=36x
z3#Cl@Z5B!6Lovc)>5FI4SR$=<fLxHSqt||^)Q|RIWzwNENM4jKqQu=LX?HA~DVGY7
zCv{A}ER86Fi7V2Q0NA}M711WELTaRQWtGzP^*~&cR?&L9O4@TBlGmmG-bP=wbRU%|
z)kt4I2Hm%$4>v&awlqe9q18%PoJC`ubcFiqrGIxp@{aUNn$H`gX-m;~S9&l9h8&I3
z2|8ESBn_m6QHykZDz4={>6r;2TBVXW^mR)Q<%9G{3n_QiE4@s?l|E^69=Lw#0;)k8
zkam*fpp@Bx@eWDH@}X>4+Vus<L#dgj$x*3ZjlMCdhylCf(wI|doN!3_+t4~GEu$#X
zBdHr5;e0IJLFJ#$vZb{3agjMF-0Uhd(0<BY=GzKO9<q>k(C8`KQ4h{bHse`v-m;gr
zf$Wv3>foA>?A=A+d}W`|!{R4<l@Fc!WZo1W_m?fDLn8q)$CZPS36xpr1L8rlG|HI;
z%O0n|Qix1=8frpiyWWF|1F|<L8yGITPET-zY;_%QkutFwZb!*{DYA7)_UkHWiI%;4
z2JpkOPiP@_M3zYlu~-?q9DNBgw=V%tlue<Xe3ERfgMt+qvM-`xDO0w@AHXcx53}IK
z37L{!l_zC^kI;BZRzMSLj?9ZP2WMpM>*35<S@}%ha%G*jU_MWlWrj2PvONOmJ}3L}
zTNpeq`+$mv3S<LKz!l2Y(NexhwuuTsie;7;X#IIXrlwD=l*%e87F;G%QDFO`EbJY4
zaY@FAg6I|5=Uw2g%Jj7St&q7M1y?C^d<kvWWXq|dsY)iNe9LuN6}=>?WlPopcSBY|
zak-navfc2vMz*RFlDA}eM=+M#vY)K9{;ZW{(^{lXCcF(7>t$O@0K6kxzZ|4N#-QEG
zUD-Se(KO0_p}j|w?6(Arw^{ZpEfrg2x<<h7$+l6>xK)<(7+$o=j=TU9?Xv9)Akraw
zOlQ+OWna&NYxiaAY1()oYbc`kUzaSC*5uu?<hy9?k@Xw{>6OVT$loVBkOMXSvMHlb
zIw0H74oibFr4s-{vcv5V8J0akZ?%WA37YOkWJ~sg8<iz>Lu5>LgAHZlvae;h6%(?*
zpNHF%vgLb#dnD_nZGz*mtg8qvI>|pdjZPQ&?-a&ylZ(DZr@K6YZnKAcx(y<pawEn3
zyyOZhsP~rZ=wQiS`J8J2_{g6shiks_yjqy|lQ#rF**^Jq^bMQ+@)ykL^Ov{I0tt|N
z&^snjew+f35f1s#S}2W_pRE9il1sls=Rx`3>A)Y7&%_RSdbE7i_qYf#^3!xH56eR*
zG0-FOvTAU#@+$>!CQiPGRy*<XMfCGekZ+^BVWK>o%7v2TJAZ}9QF#IF*plU6P&hF~
zzM100$K;L!|H8#oxz9^r)8ubvLo{7}_7Th<m+y;(r3`t#2l_JQ>*+hjS@N=7@bH9u
zJ58D=<+s}bKPCTtCk&pJzp@luw%n5fpE>e>C|Z3+J~|Ty&&ofggVee5P@2K><msbO
zoiC4Z$RT=8?(zj%&&!LbN~=I#MCp@4`9|6x6v?F=h!o3fgWyw%JZ=RfOXWN|uv8|G
zrpN1|d}s;mUXmYw7M9B8{7(V6EPw4A0ItY;UxKo$@_8CGR>+st!$PH8NNeJ2@)Jub
z|5qjdiQc={<x?p<aZ|oxDLQN9S^MDPEx9X&c5ll+Z-nkz`FIFK>f||h;6=Us9_<wG
z$iGuTvOzvT55!&hlB?)zln)P~u}RLO@OZOa>jPYi{7u>l+>;M_KxeDm#Xb|izc%@5
z`kqj`{K~(O>5!}D!0%4^D6J6g%l}!8z6WyNMvyM~DT>K<%b#5he2<(%vEW|$2rV`H
z<Vq>He))nsusa~%PQREzc>=A)hvWh8!S1kp81bs<59Ql_faHk$^_S?p@2LEP%dk5p
z5BvpWTpmV+loRqZbU<=au5X8$NAiniaF6As*U;yrSn~{Ab5+zF17MHh${}1sH$}by
z!}e6PKZHRq#o9<%@>Xn|2Ar>=bO(r^BFPKh?^7&6>-7B!EDZ4b^H)^PhBpC<UfRb6
zDh_P~7o>2e8tGs~j~FIG6bovhJ5=HH9=I^YvtL5;fWk`Ey5S0UN*qKeu5H4wBNe-;
z3Oh<sL@WA(3Xf43JftY3`u1qW^HZTSMsc1Jx`!33DPDBMp_o#H&R9j+RFF7D5M?;y
z72f$6Q-Xp`k&{HlGCR0r#lUKKk)n7;4K>FUIW+5~E8eF=qQ@1dr$Hn`@i~S5G8Lh@
z;Ib6oP{RI%;<snfcvA7l%W(9R;;q-vcv{i54~^LhN3#gpauk{LA(S%;mr^J_tJwN3
zxLidhozTxy^wXX;U-6t7SN)tqN+0_<uXs`cy9J76^i`EYMNlNTBE^-1@V;2#T>!2`
zVLSnY7Zl4Wo=~a~EX18GQ`o<PvWtpFnx!u(8XV4`<%$BD<u5DpOwfHru_g|7D;2NM
zKJ1!e9v_WWinW(v{<<P}D)7~cBUE2;L!r~d#4SY}?L=-Xc2i!sR&j|=sdOl8p75em
zk+ccs?<?+&LGpoOKE2Jl6k%Do2;GWX$7!+Fqp;b~+N+q824J7U@*7O_EB++E2Nd#h
z^bINwQY3Fk(Mo5%hZS=UL-L`5Uk&d^6hq|ps6xyFZcO3#C3KG~y6Ft@gyLs<5lkw4
z<AHNho}>f9&dMJWVb(=y4x>K~a8>>lh}J#It?nRh%F<yV+?5*@knvD9Q(=>*ay5n7
zyp->~2hLlWTnyLtDkmEN@KL5w<la}AM~NXn<%{$y-lsf6#rFG^^^~UdSB_9oOn|bS
zCa6H=WdXDVDL=yQ#xXru`Ew=M5T%5&D51(ZV?cx{E2xO!fbtm%b%rZnqUcqGGKRhj
z5~*D111?HAb{^b8<+nb-9a8>9(`2-g!Gif1<$PM?9aakIc{-xJ_A|Ix<tj?C$0?oZ
z_Y<#lrPQJ$LHP<r3lf!&s5U1_dH5de9#t}?L3gs!e;V*9%9`^KJ*J$XNKLA8Cruw|
z$_-SSldkNbedBQ@;t==&DC3?5$y81rhe($4{dI8kgwmaMm?xFmZ=mdyaxG<<PAdym
z!cewDIhqgMIm&HeAZL_s(2<U_$^-90O|H_k7Wh1+FMX;xU->N^@;;~R3qa#}Wf9GR
z1<Ki!{3%qPrY%>I@;3^~6e~p`7-5N0Jp(!~C?ENuu~fM~99qhhakruRqB8Y$04^yV
z6<KI4R}RwUzO2lkXm^G3)c|mn%43wvxu#rE18r5x*Pa04y0V&*8r90m4=|V;$}gy}
z@TM|gFUDJ=oS;Jnx0D6DVdA!OA!XcamC|EqtW$Q;TCHBm*oMn|M>#~<)<$KxV-TH9
z%9Wk)v{`9?5!zampLe43o^lTD(_58wpMdL7y1fjMPG!=Uz~5Ka(f+Sn=|g+V9_4f~
zNUw4R6&nvIn@Zr!pz;Kr-WXE8O;h)<at)odeW+Zq9DO6o;+MgVD*yYB-hX4t6&>(x
zT)E*G)J!N>=Ady>SvDK4JyNE{0r6NlOx0OVs;%_V0%z6FU&1vPRS_+{TveCp4CNk`
z&v&>n9;z@3KzgdyW&!7=x=0hUkIK6jUihl|DEsNBD*qAieX4;JI&ZjNm46fne^q)N
z3<jvS<ib**>Im&Nf>f`+3}=E>1zg}mRK|-i5vrO;q3AG`|C{JLpn9(cO2bv0T5u66
z#WMI5sS4|dPf@C(5;R7urZQk5M)eI%p@&tMWKbQa`UMZZV|u&_j|V1um3Rg^6IGQv
z;aiew#gpKUs!}S!C98Hm2}Fu&@itgGrgC?|m{L`nTG5xLn)L^`bd_=oM2@RAu7jlv
z)zm07W~zq20LfCl{0c0bP)*ROk&~*Yli*>ts*bkVjvN*1dyMytN*NEC0#(L07+Rr<
z`8q5WsV-8XUa^YzBpORp*J+(_L1n1|uvFDdH@!^t=7+#tRDHM-&RkOEQU<GBHR}QT
zE~{p^fm~53gdkT{Km7|s6{?s|V7^jSo(|R594fbipjE1BsyMr$+E3NOH&rL<pr%H(
zJR6O-RJi$go>k%R!>3wR78P>UsV1ltw_bIbLbG>NtLQh@sPe4<X;S?Wii^;!T1MHe
z7L}4#Q1?`S(Vc8n1yW@~o64DTBJC<iXDrwb)wF34eV`hmFA;aCBDP_m-Kq-8QS_*O
zr5JXv>c=;M=u<_q(b%sFm%+6GmFp!K98^_PX7!<J39Xq%RBB3Xj;f}&0yn1mimH>x
zRc}*`^n}Wo1Nfxs+*y!EsxKV>!0uz!%al!YQ9p47Kvy-F=KMYCBsz%gp?*q<K2LQT
zdFZ8fDuzKH^|Xg@)K{&eM5Uj41s9yZ`lJ)M0QIJO7*e3Rk5aKA>UW<)U#R-!&!9R?
zEuzq0gnCyhxJdPu7byM`r7m=b!C3WuE)a2Q&sK2p>Q^(sC8(YMgh--#!Erd8r1pFO
zZAaA$C>oQjE}8*@DeC)Y(0EK8LL1#wbteU(($wPl5J^}6_X$LftN){diVXGcc9_pp
z-#QQTS!%Ze`sn=$weM#Do>Vtl(RoUpwGswTt2<A_e75?1fAr<3%Q!%sQ6H8-=~?wO
zN-pH8XDtLEPyMSG{LNSYLFAmeiLwdj)$Bv?w@~eO7+jJ1+W`QI)vBl9MTz>zO!#y`
zU5wch-+NMbQ+~KieTQQ97uBCq9^sPuKPQZ$Tz!rLiI>$auE1YWkG%ocuBv}ogvJW>
zLnr92RDZe^@M~&66#!N0QyI{5UESe;`J3uP6=<wcM^TvUmU<0E?(5VXiiFpzPu4@y
zaYtQDqK)bZT3R=$hX&ButX^FPu0=g%HMo1~QXi;kRnMod`gN%PSq0Lm4yJATeRVQL
z5W3YV6!Py;|HS~VS6v`OU!S^+N|^f9%U%O~Ks_0b#$oj+1?wKFV_pLpaj07<VL7f|
zL(A9+brGeYCe^A(@Xbjhr!hHe4sJ)Ei>AI9j=E`{egci|n$2H8w}&RW9-OD<0L7cU
zG(&L^@zzxOgZOKL`p_4ksi!o0pk^}#af391L3kgm`JA5W5RD^&*1e&czZSv$FwIpe
zUp=7tr5mE*nqrCsL}-@3h^rT=$%+9NrK$9UGY2(wp96PD<M9UiqBS4>4rgLCUG5-<
zHS^Cx_YuvV81%(zexP7boMuE160f;LpR7#KaBiS4QS*U=qKiqIXBVUMsOEQXc#*8>
zxCu)snjfdZ(_@;D8L*V9SwuglG|i$HpgUc&>up@i;~Ev6HO<icr$k?-#y=QbmgXCJ
zI!|bRdJfK<)NHQ;cS_T77RpX*j`%}awq{!_yvWh?M^OIZjK-Rc*0Y)`SAfse{6Uf0
zJk2&bSeCEZMx~GEG<K>QJg=F)6^#X&x%5~UYGzU5y-35;f-BY}(`;Fyx!?xwg62Um
zaHX0J4G<~QyikC~i<;5z(RfM2*nk^Tt{K=*_1Bj*yYEBhil&7Er&l$LX=zZQ`8yC?
zl_rbwE!Q<CC@NB|;nOd@M)Q>~8gFT4Q4Pgy&ADc{U9Tymbod?3@4JC((5#Z8u}Kp%
z6Uv%3@91E+MRTzf*QrhO9BqQzHSZuB;h5f`8K7-%r{?GVkh!l}Koj!=O~(T0?$SI-
z8|-e)0Bs|CG(D7!@6~kElhCJWei^r-U-Rorzzu4)b-?_PCW7XRVNJ|t*nOyZ>MOuU
zG;vf&HLA&548WKsgi;0LntxtJpJPJ9-i+2sO_mY(N1Es820hmN^$y1Cq@9_8K4)!W
z4;o#xTzW0IY7KcHd$fx$!wWa<h#&ggwMi?X%|k1pZIP$;>-&IvY5Qqj_SW_?pn9)%
zBp;1F+E>^x@2fRV1@UueI|cA<pY}TKp!RG3-U3m7?SjK-4A4%aKt!PStHlrv(*8Lg
zjltS~Zi5TaZlR!PsJ4I-VPV=?@o?sVwqyoG!nFq%!NUmcrc*E<seL^fcB8bG3OIUD
zTS#XN4r#wAfn>DSv5V5$G1{&@=sc`_@n<MKqHUN5604o4gzh+PF-7v?wHa9;30eiY
zmZ+_!c`8X8L}A6F+HLgOPu3>Te37F4ND6XHYc7WBRP70xDAKfVjl-FA?Uj2le_Xpk
z20(`PoZ}a0%hcx5HX}>hHU%;#v{fN+=A`xm3PhaJ9>0l;a9X?dJS=5vU;YNVbF_1)
zWciFXBMyycweKtdm#Z~Tg~2?nY!$rE*CtWq<DAxi0&btzzDl>LK)Z%kv4vU_ZJCO+
zV~ZW=EY=>F0=7i^o)YFSXwOk(xm5cUg)_^ve=Y&yqIS6$CN62;qF8^qHh`YM%i0op
zon6r$2!igbTH&i0+BL0LC>pD@PVa)duC1Xsakci-Ho$LaXVEI>rk1@F_G+|Ae^LJ7
zmi9Qs8gFY8zd>iM_Ph`5)@iRE!szR@W!u5s(bmiaqCtC`N}lg(Q-6a`jan70?wYjk
zJ_i%c+FdNbTeMRshI~((ORwKn?RGk8*rrVvfNR(0{sTaVwu;u$o!WCK_H|6Zul?{(
z03T>WkHAuww(D!ibZfKML#9W&Wdne{+LN(xrcZlp3mW^iztBOt0c{|?a0j&uXu2EH
zuA#-{uy&M!bq}@tXVEvJ4W|vosCH`u;A7el8zjfIDq3JqXv-+c?3mR4LLY>Eq#fCe
z&d1tjDpzvSU1y-tS$F+=3~i6@3~kfhbbs;C=&qaF1mdA{dJB!7x&TjT^U{4swRqmT
z_3y*qy}I8i9O9!p6NW}#T^0S9{d8`tp=_V7stJwzbq}*a{2e;QYiJG7HBsIqP*+bO
zq9C2nit8M#>$`w4h3H!2;c2LDl!E+Wy0yzNrUSZy)i4pRdu9S$gl=ahNTe=$1n?-`
z@}Ge_sM}=%;E?V{94tiZIw<lVqnrOe{5`CzBlr=W!*dmUi`6OVOD}P{74y&;uY2u2
z?qP!N#0{uP)Xk!}Pm*qC1tgE^6zkzkvhE0dYavC~M-SUET@n+3RNXGx^Q7s_KfsxE
zT}2v1GIbVO$7SjMrWo`I-Nia^Cw1$|?Nho+hYMUhts72&nrxlVGeG3%0%w9dqqEUh
z63*&MHvo~Vn>&V~<>|ho5~%aK1p18?=&b!9g}T8<@To+1q5&o@=%S88q*PZ!kNhRw
z!$H8ybz>9(ysZ0%c2yNR7R9hCb#q>JK<PDI<Xn*3x<olzYjtslfvD5TQ=zS1ccKc2
zJG$<7;c$a4bOZeWbmCv&XrnG*J-8;_i?k|i)-7#-NQ<ua5U$fbT^L1wTXk0zAZ@yZ
zIS^^ry+bD~I&_;Us@SRfFQ4{*_jRLGJ@i2LO)c<Ux~W2psav=G0T4a9t6ebPtD8kn
zV4v<d)u#39_FX{ZfUb)|T7$Z;N+CI<+u4A|VO_lfS{~|>Xo)+n>!4YFLZ{1v$fVB9
zhrf?>H>f1xv2G-t-hWQ|Q-49JvtF5xP8a<bfpFMee}G;`9{Q5E0rb>|(yz)(Uq-JS
zZ~al4X!h#srog<9-atD(U%mGRH15-X^D)SNeRek*{q<YU;r0gTJ>#JzP`_w9;6eJ&
zPNOea-xUT!ju3r(5oAL3s}`U$OuzptkZ}D0E_6reUrE52BK15vp%|q<SOA|6>NU4<
zfui-{vw@G%CsHE&u-=cNi?Mn`9EKLBKS*iIc>O_ow<YRh_drXMzRe9+=BWMvRjefI
zukMAG6o;PK0X9v)cPa4c`t|M5c3kgD>-7x1k@B>edZrvAS$Zb@R8HvUQx@{1zOn_9
zr}TgIg3Hkd)MA8Z^ihqFJgX0V4wAY0Q(uDQ={u=VJYVmiUH3V?Vg&|qUjM~Szzg(_
zQaVFjsK53-I*atKjc}@1zhMUuCHgh=zQ3UV;A8Za>MN)Mq)gxZErxbce~CtMN&nwU
zXuG2Ko`e@y^&ZI}6?!uYo2FOlE7X8r({B+0UZwwtf_&HY-<(8awO*+K{D%Hz$8xxM
zQy)f)#2WpnA0T>5|K4eI*6PP6VX#ggL62^|{<sz7j(*_`sA<qAr9kAaes?{%M*XKu
z^fl?5Zo>O!{cIO_*rLzm!qPo`a3>mD^{-OJben!&JaFy$#w8#fdJh}@{yOz<hvA91
zulJ?OlLz|052CY6-}f}QZhhch_|&6!iU8@?Z@LCDpx-D0U{K%c3-b^4Hrlk0=o>3B
zh*ABA3qi*87yiXX7}rO?0g(xP4<ES4df#18?PS=v8Y0ey9}$1Vg392&5v_X+ZZWue
zZia8k8F#}p+BSO_YPW&&G+d_*vX_C=2sPe@NIL*~4X@LC$j9(D<zRgc>?fdfzhMdm
zC;bf{QbALI;q5ITfrjn<@FK`?iXwQyhR0NY7Gii75i!T~P(unmb76*gbX4Mi;X9g4
z!VS0I10urku?u{PG|aq?YY}A#_lCiPhIu=HKV--nz_6nY<4*w)W9X!!n8SuiN;MoY
z9QYI@!Elf&RuT<w-32bmFry11M-7K4c9v{-{ygB06vKQ9@f<UJP=MA{Ln|el(+tk^
zndEfC+9b#vH+19zm|?ItLR+TcksAzV8TeF^aKcbZv6+*GFDN5>%J9p(7{qDA@tJ^U
z8-nftkYfnn1q){kDYUveYq(7D+FU~dEiCdJhL%78^9_fd1vzK%OoPGmhEJ%#sK79v
z@_2=Y%4E1!WSB#X@M1$YZ6!(!4N^2-FuX^#45bF^2QXM>cyT%gdeI=M0=Z;Z!-izJ
z;X*wmFB_6i!@?DVozC=LHKd&esW3SHrHQrDaE|7bYlg#=Q>ila=Yw1~m}$PLHl)vi
zGdB#JA`JAV!8Zq7jiH^Q^S2BOJ^^>z&^8^8)*2!xOI&C8gC?4KgM`9!cMN-|YPP|^
zrlYQR4FeS9Ycynb!|f)+zm8$FHXEcg3$z*%s05?U(D)KM+YL%8>*_H4z=24o;roT?
zyKfMkgVG0vZ{Nmvy9_my&FD6KT7`l37&<q=Qm^3&J%-e0@S^i<{RRsafDIV#(63_9
zkn$4zeP{@J8ImK0wkC>yjv9I?CN*YIk@<1MRN9+P7|Qa2pEOib<;o+&jHQr#Y;dP!
zrjxOTZnLv-CIweqjDu+qaWzWa!0j>4%?8fHXrRxAdKzUB0C*W)X}sP><$hS$Yy5-{
z5g()1c6$H$8Y5`6<Y!z#1%msG>}R27zi}xCKKUEpe*u;Pj8`AP{Xk>UT&M{$@~%T9
z*!Y74A|b|O^ug;;;~OeSh8bh8pznauZvg<|M%FZlL>RMY!(gOwE3FZuj19EpI%w=i
zb(Uj#jL|0rorjI1G?gAP{zTehjn^(fCeFC971t}?xZ4jNCKwy&#6zNS8~y&0j9cbH
z<fzf-IN-^~3tTj&7;9+~Ic8i$*@#r*J8LlBbYq$g+;QWr2yhw3B3j&K8r5>Bc4QeN
z0)aSTe99S}CykoxAg7FTtx$T}`0oTvWE<1Z!KWN!<gegzjq4u3(LCde<!H<|=Fn9y
zFwPTz6dHe}P*#!gIa+lT8<Uz~qQuxs%l!++$^Wm5jAOwNDKpx*xIh;j#+${kbjf&}
zGFjzD{)_0mYz&+SZC8woY4?29SWJ7;3gfz1AS#VJz2NUP<Fa32zRLLXdg#7xe0vu9
zs*OFbqwj`sK@61LG&1OHQH`<dW%S)Lu3v}?bldnBo&T#fTEE6v>Wq%!SD?Gz82%W*
zJI0=G;BbR+lO1;N8oj8HtI-%op`j+@XS957HoklZeJ#erP9XP;w|2pNn{nRnz_lAW
z6nf||YTgE})2N`A>3w6i5+V<b_6KO}GPaeXvD^6G95~ZsY;jQVy4Sd#@&SE#yx?%Z
zaT^tK4H$o6fD9V-M23tmI(RW`Jn%aP^U#=e3`$3g=jkgYqsFhO25`)%r1Ge7<G+2-
zIbrls!o;MpfpRI2jPvQSd~966fTK<(l`k5dO~D>i|Keg=8v>xKsfpggdrWIeq1(-5
z?#Cr@H~siJbbFWtzd^*))O#FCy-XJ)!Fij$e-R>kO`~lfKBlJ4!1<bn_JR1B=4C@<
zpJ@d>Py0=?C{N>WdXrZ40j8?oU_Q`v=V!|Q1(_0$Kxwe)f)557ViHk-L#XM6bRfb^
z|6GUe1E!CHF#2$ljKandri@4oCerjGy$z#G!Bkv!&@}lqaEDAhH%LaCTxq(BG5OI1
zbJ+AJ9dS5fn$LtttSQR|5@#A5q5NOGDYY4*2__{Uz9pLe{Siu&Os`v@=BQ~g-NR&4
zL?s$iOs~-A=Z~3|uZ7Z7)8AT<G*b*6j7~Rw;D)~ArY)hkh8ZT$P3X%sjZ;oB%cN<<
zcu$#p=v{u=#HNC?Y}0oXa&Y9BzM;_48B+wEN;+$bqv&L=>0`S1d8Rp(d&)Nz(Z1%K
zX<aA~=S_9H;7oz3?^AGvrkXm46q%0FYPQ&<qROHYQ+_1i7fe^^vkavsPd9L7roSjv
zaM5ILhU6vF_7C7wxx@5vFz98|jkB<O#gs(B+^Z({DNs{k+Bgq=l_nG2u4^WrA{eYP
zZQO&t>!$DP(O7K?)T8l+=?|*zx@k(h0E0EAkfZ3kWm-)0`E65S6s}>d$vlL{I@1)&
zrq`PaDR6Sf<oNFvXoE>9fs1!d*C?IPX!6_&Pn%3Bd*M^FX~7mKZ880A2Y1ipod}Uu
zlbSXLZKf(W^tGGb{Qs-Uv@jAPou*T15V>#appVf%FcoHk>oQsVVW`_=`3V=l$JAE_
ze|t@@J7`VNXUeLA`F>ORY;Xgn7Fxy*nx=L@+mOkL4pj`BUTJ}vho(0<7}JR9*;gSl
zYMM*=urbpZowOK-2mlkN_bAXiY07#ZCLWo>JR$km^a(}6oy>Vh;Dxh!<rXM&F}v@g
z*te^BHmwQvn182btcUrDOvreey_SJ^nR#kB>}~$l177Sk2mcNaeauh4ipG8B?Nn^F
z-&{zurN4P59r+0|-}w<f1)C$^fzA-~mI^e6nzv{`!ptp{ggIb7@*POH`LlUce;r}=
zc@N%1nq6N4i86QgL-e5e=wFaIWZo;oU=EuLVqoHkxxf`7vF64zFcD|2i3S&Me)c4s
zNieg1g~(B}g7#6#=J2J^l46eh9DQkKJzbe}^H(k4j+-}|pgPO^5~4@!=_kyeErGU^
zW>x}ZPMK%Ydi%8bYl`<~o6q;aM2<O~5&&n+(Nvao*4#j0ja>8HV5rG6htt89eDee)
zoeIpE3fL_)hle(}Or7sgQxN!)`RVI`mzzIxhK0-KyY-N~VqSF<xU1&56zHiiD`|qM
zG#{k`^=sx2X-`;XRvU4%ubU&-Xsk9L(Zk+N^T-dlOEu=pD<E>q+)J;q+vd~HfU7ls
zKoui(=CDEF>dm_yAAr4M-bjcB^ZOrSEO*TdDcaR+-t{fax0szTVJ!E|tY~=HY8KM7
z)@J^JY7pAZPGX33nhR(Rao^mV3itza&{_<s%RG}-6y4@X6&icYr+wjCulWT}48G6&
z_I_~v=I@tLc5A@=XEnSTH1DJ{%tPi?7RU^nyD290(7bsrxDj({7PO6-C+RgdZazSJ
zhY9mvG%rq?57U9NN9K&@;o4)fati=XmK%%Ule6XKA82&3tlR~-tL5onkUf?~RJ7-2
zdGHiP_uMUU^xpNbd`S69PfI%`U-w#`q=~}E@)Z?u`C5YiACj{CLCI}@i#;5611t^k
zzy(^8sir2#@>U$UV9QrVaAB6*DG)he*+p|-xaFm8^hH=Q`rulm<zgcGqAXic{OXu~
z(31Ec5Qi+MDE$#_d5J1dVk}b^V@!uF0cYUT5z9+-)-Bdj{Rkw^l1f{|cuN`O4HGQ>
zR8^U1ai)J7PqJM97$Z!vI8%=MnB@}fPEsxTW{@<?HZgRjTdWjZJZ^ce4aAXU`H})m
zCoDy|P;=6<ooYj~Eo1b;%duq9w=~XJYF>uHvlc#;z2#bB*zh;cGEWDk`Ig<w0Y7Jn
zq6Eu%OY|{#QDA8aLSLcfgg>|<%lC5tFSaaq0=&esgl6{(7N<7YD|J}9XTwC9WpOa@
z7cEg7jOmi4bpVa!mbPD^`?BRN1+-nUc>V-!S1tKVp{>HgZGmK^Wx;IpU9;p=gR8Qv
zq222ZOUK8MylL@%fU(qAE>HySmgNchyw+{YZ(fkBwN&|HfOQtf&#Qo_x6Gu-(jAM+
z2yG3Pq0ivkU5m0Djg6LenhcsOnwtPNTV9}?Z;NHB7qs28#M89VYN=Wa$u`SNRHE5#
zk(Gh#u)J4}L3CQip2M*3TMj?Kupd|~GXU?hxCemiwv0QnAlhSbn*ncnEp;>p_FGI(
zp>x3UbS*>&Ex|uP&5*?jwdm7_EqdCMKC~#hF{TmA$Z7yaEq3~ija#H<kO|AX{{lW~
zSv?JaN0zOWS$S+JrW~1*^)V%xovp@2z`0ue{-)^q9;;6-I^C?#xWWr}YoZ^BhxJ>^
z-FjOC1HkRIZl%*XKGtkn-1%BrltuKjZsOx2?6XRSU~s=xN0pxb*2_PkFTncZEHnmM
zizsv*Wc`f78NpUl3Ur284_Toz)S4GcUsnjTo~6a%0qej#0K=`hl^Aw}bs2?kBCTU(
z@HEPrvl@5gpp|zL<dAi15b)7fA$cETeTEOEhppc%0sM&dONy<;THO&kpB`szqRA`X
zI+_J73D$WOoKLi>#vqbpm9CgJW!v<l)|^vt@tAd#(zK~o=6}$gX8r0hWYVpN!@(W5
zzDo=A4C{JYIG(Ud=+QlCUG)F>mi1;P`c7Nlx50e2b#Lf7Pkc1hz79U+TK#BR&$C|o
z7bM?0Lxje2)`dy%sla-XLKTJ9Efmo$vd%sU*NUyDccZbyI@1}F7p$d6KuWDX%VDp~
zS~d;jlC_g+@5-&}(~!Juow5jxSFCyTk&&xb)?EN9tdAUz;C-c)nTytI)~p4Psj@04
z7<1ja@po|5R*@gvzG2mM!tI+@38e^XtZ9Y7-Ll3~xaYQYVjAGJ*7Co=)mb~vz;3;@
z<Q)L+ScP364c0kSw0GCKnj*oC)^RHOX|iT3sjQ>fx+N9(R%-}N-ECHdHxTXCAUZbR
zX&wFq+<j{sm4804K2X7Ym$i&G1l`s{benpt0h?j4*ZSF2=<c(YCqrky_0@F{8L;l7
zLx6+U^*aC`vQ|=(cG$XW6n!JshCX_%My=l#<I0X%Tc$yD+!{ekmkH~=HIR8^J#-D)
z9$P!9XwS)ZDFx=8ZGJ4c=3@Ky03`R=7!82C+1d|5#N8G~uQ(6eZ?vrOv>9nD>t%bw
z2a?{l*|gl<YhzQG$j8<eNI_#?TQprEKU*P9Li=nvv^U#t`<v38{<df6CmLXTWgSEU
zZ3YTY2ieLfq!Vm2Q^+pFR#yn0!fjV?f<)ME`hY~*w$g+eWxMGLk%P9^egyoG?Gz=`
zqisBjZN%85LFjWFwtXjo!6UZB0*oon#-KP;yv_3uh$h(5^5I3I?Pc0aCfR<<z~w$_
z(<PuU*><%YBTTU+EQYpYwvwj+Pqi(Hf%$ZsClwSOx6OG0A{jRRYq&9)wuK)-GRv0u
z8I+x{wMRnaq{Fs`4$_>m$y33ewsq6iJ=^B|K7cv4nSa2wT-%W~5XrMKi$L;iVk${J
zXIn7}k@L1?!N3*RPSMt|(B^LgyvP<|$LNb~v%d$R#P;Q{uzSIF(2S9l+D1PGS7v*H
z4rE=lIaY54;*#wzs&^~5O%y`uWt-bAa93<!(3a<_Z4NC7Dr~hB2(PsD(+1|6?b$29
zSJ^mpu<E+)?ak0#ZM#A*t{b)*+6dgVP11^>#<q|OMQ_>4DDiyT_T_tUwAS|LO6aV!
zEpm)OrrtJ_9^JdPU^>3gX#0?s(oMEd+Iu(K{F`vqTWlx#(09+ab34Y{YODDN*SXE+
zyaAH!wvUbh-eG%j0VF$ZFVXt?zO9WGI}dE;PeHnDqW>?lY_q8vtH*Yo>WX@8i)TAP
z`)p58#Yw;IJIVwN*qUhxKWO{u0Dwcb<@HcHY@3(?k%zWkT2zkM){VloQQKk4tB%=1
zD4afSJ4{*s30r<4L?&%kN*Fw{y&a9l$F|=dfjHU!dLCMw?HO|caIq&Xr$xJ~{n&44
z-DCG%4jDJQnnEP*_Nf#^^|G&IL)6>;JiUkZ+MQTv^s%Q?>5{K~RUst(>=lFXcc1;M
z0gPq8{jCge{`M!SkRrf--v?Zv{n|rV2(oW4M`N&k9VNv=>}T-4MbOyZKs7*NcHbY-
zdcfZKCrG$`Y!NI)*yoCH)g$evs7NZx{?j*TJZNt#1b4`OpE6(3_U~!=8DkHpFw<fC
zxg2mu?CU%s8Eaol>!CP%$uw~B_Jia_f?dA>jwagMY0h>e+52d@am*g60h?;S@E_Eq
z*_E{CNVk_$8Rc>N8y`bWhP_UKE1PLI&`KuDuDB2Gg#AnvxKs92D@>fWt80PFw%dOJ
zF2{cILo}YTdp1M$S-XX1(p-DY64=YLZzOy94m%?Z^ql>k3W)P|^;f_b*yqyQrO=*9
z-$*I4ulf#s7wp~TXe_ng+5%_F><@o{-EzB<ekzykWwbQCVpr1BU1`@9z|u9l<2?YX
z?0@ctmK*kTHUKy6-DJMTzBLqpTXx6A3eem3X;-1N*1o$PG7a``DZ_Zz{y78M8tv1v
zK$`67Z=<i-euC~ui~TiP?ccLYmI2plU)utMZT7Q&gS6Z4&4f=K_66xs-DyvubmM)y
zI0qN@fxYZLM7r!fRG-srA92`VsmK21r%>8!&!t0OefBBq;bOo22(6$7?2XG{Y0$ps
zCuke8Pp3WbuzdqXb{^Vwv_BrPo5|p){oiqrG5b$c203m|r-k{1{WjHjOxo+uq4AMD
z<vVD3Y_IqloYPKscS_ng@2sbApv%sww8C}W>Ha(#_w4+FKDy(vlMw`io;wv=0rc9L
zB*ZAZcXBAfv3F<8d(iE(vw8#<*mviXbS?aLZoh}deLGM0LfQVE-=zcYztge_xPYDU
zl-&*7nM*Ilpq)lH3K|FRd_b#?kez#&z=!VqkLu*Yc0Nma&I3EQ{EwyY0E^;${&#op
z4(>QOxZS<N0WoT-F&aw}ON=$fucnwpO{|HUXiPM*oI;966A`3ZX(CmmHz`sC5v8h#
zG*KynSWyr~MCJdP{D05G!|={K^O<?y+uMELnR%BRfC)BQQcX*UQTiuDLXH1Shrux8
zDtbf3QRAa2AmPS2yI}X2aVpiqMHq96ff8xV%Z1xf#_IVX(Z=F?Fcf1{xWSoN;|d%W
zF-eabYqijiHx4dFXM*ud6<`vLmxnOIBxAr%w33Z)+{av`7+opjmS%kCcbHE%-lg}7
zXBhvg!eBCu1K|)kY1Ea#ZjRB01IaaxnG0u58T%TckZ0VcLMz{R=R05)7>`qd>DPru
zGYXlXHeTofc9Ai{5!|!JuY=GkHQG?<`kZliDbUUv$I)86%&4q}Lb>rX51>^T|DuwB
zO5;}sI8$XjemEcytGY^x(9{^+mcX^k#vQbdt2J8Eg;Zz!l>xKf_<0TdZ7?QofqJ9y
zb^7R=jBf5|T{WJ$gV}C2F8djh*Nyu5P`_dPh0@n8#^nN9t;S;d8nqb*#=}s%@q0?k
z-ZYk7gcF@cD-#td-ZIJ=kS-%nB^$Sm!{}nUWAtUvx@(+F;nsV`4S6s)U_40E_0m{>
z93n$TWem)_?)XLz?A<#CA3(u#hi(ZJym!o?d$sQlcdF7mwqtk`<{)85c@@m3?%)#X
zlh|QVK#8E79S&2#&D+sWo5{i*nb`m>-jPoOE#2`Bwl~ts9TskYY2LBv2lU<9(NqFw
z9`8t?%89`p+s?u#x1A>1b?(_&aRPmQJ6D{8!JwT<6u*nuIdTZh6FVIv&`R5x#=(5v
z&QD*^X8r8WD>g7+wsYE8n7Fi4O(kM=JB9U-@pCk)U?Rj(e*hB{<v8zSz@#~z*#Ksi
zqp=mkE_7VI6h4(X29~4mlH)J5XSnJ(b_YZ{91Ez%{<h-}I=I&3c<NVJc;?tP4tg&f
zPb%nDP_9l*6i@SVn&SbkkJIvM3?|U2`vO1@I(1WxREU$w9s1Euv9#5SbDAlGr9>yQ
zPDrLWwNMN;-D$<YFnH3*o^CK%PMMuh$ab<+p)beDkpch(P9=1kD|G6;37?9bLa0>3
zRP1!n6`g0CvaW%YIMx4zfu42x?;RzjP7@87uX9cZTWEru-kFb~l{=~LLb1|mEiEjn
zoHoq{v)ZX+6MVYh6ig*c7o85#H@wEl<9`sj?DXdA=&N=5f+8hXoU&KI!+NI<TF*3?
zoR(8Oq0!0r31pg_MpA&a-Kq8>Ks%lGVb4EIik}h&>1kjvSHs|59W&=B9BN>eECzlP
z(@*QBX2yxO5!aa?MToR8htz1bF;A@l-^py(fZ5HIWMDk~%s=!HaAq$*q<_7)m(AS<
zm_T-M6!-tFX_6<vnUO!GpgC&VW|(^8lXQ6d<``O6zGeCYzbC)+Lhls2(deD(I05L>
zswfxsNje?Woc=eZC_j}gz)a1EoC&m<Mg2gSb?7!Yv){S{-8rXGTxycety+SP&q8=8
z&uhI5<<Fa&AT)oZB_RH{rU}Xml1}6Ag;RYoIbWFF0q4t#V*LHp){nsdI$=0QwaATD
z{@;wagx}xZ&4$c(nN;S!Sa=<nOKg_{b7>Y;6Mp{z-5-7!90Y=C+2>RQvHXt+D6IJI
z7W`T{lZEK215}T<I(iQ{Kfaa)GiwyV;II9LP6w>>pffK&pY}oTFX!mM+xkVX;qMJ!
zQ=aOdcardXH>0};1rH{ilH_|Bce*4!841;<?q#~NVAhK<U8iT4H<R%OF!nL#k1-cM
zOiC<d0+{m$q1ehe<ieAO%pVKEe8kAV2YJqnqj1n5^A}cT(%r0T42TE&>JC|A3korp
zo@~OeFtL~YeKTD3Vl$oq#hcws5xITr$5d46!+vSH0E40IzqD-$WA9Tm_BdNc_n|np
zXf!OHV3QeGif1P+09pduPA3==*?AO-NMeT{2X-=>OtF9z_R3y}q_V%X0y~XeNNbvO
z_9sdjXRwYpU^kQ9@HSdm?4N(bnQV5#HrmzZus1b8JIURpxJnkMpyHTp&XErA=5St*
z;7l%e@Gh9AxaB(`na4e+T~j`{i83?=+;J*3E#xkwz{F|pr|m!~;*3<$RLreqp?8K0
z(gLM~`}9jFoaORq$6Lyk?xBALa*iAGE@aMg8L_}F<1|~)D(4jM1FeF~7vOLu*FFmb
zYhoQhtGOHXFnEEJ&w!<i+)+w;UE&_ox}%0$z7Uo!b32AZp_Xf+9q$$H<{`{l9k+}Q
z4%Tz#i(sLFi(E<fzees&5^dtXr+n*G?%@<@G;`(75WU8|d<Jrz%lsTBZg3X#{cGWT
zDAe1^HSB?<HqO!)>h0XgG?=)_4VQv+a1oo~S|_KX4EQZ>#bsc2ab<GYz0Dn?9o!wR
ze>^ZvceyTa=-=Zutp@0Q?)pk}KHx&;K(U*<O!>=)+@IS)9&zVrd)LFoyn#vR<-Vgz
z<j35<o51Yj_Ikq6C)~M5(0j@yQV6A=vyX<|XI$A4Ko4;5QO@i+_h&wsgWQ`UP@GMY
zajP(wE|PFsW~NH2`k<I5dD95cbjiAKv@#^)>Cv4jdC>xxlM+QEV6r4p-C$-*yidSx
zj^ro$wqBHMqOa&BN$F+i)kw~kLh`aCz5?W$<RVp6T$h;9>#jN_LHj{&NlXJa(6}Rs
zTMC)GlF-+oxJMdAVJJ^&NhEyQEA^1W(|ytf^jP<is(irol}_CXXZ)l;On{@|_;;dE
z$d$&?uIH4rpcy1jDxnWOUn(nwdV#cqmU)HJkG_S4)6y5oAVtzqrXtuamd+%HOQd~o
zz{RuDS<YaVN<X2D)H!Lx0_dNYE~-OcnRLuO*e#bX`~h|=q`QV=^fzR;Y1l2Y!nq)=
zviJ~?HrcQ5K)qeIl^#AfWuXE{hiuagD0Ir&-=j}U7S~JbkEb#pJY=LpvhQd|<!m-F
z3;Hf*IhWyutJwnD<9eG-x`r|BGqd*r)5q*1a@5zXnO1H7W{LmhdCkhH9xTu-yBITj
zz--P9pd2(iM$h9zW|t{AblB|2NVG!CY&U|0nz7gERS02b8FUwjGFwE^uuQYHMIa~5
zw7-F5nVqJJ#B8&fCuxGs_ERBdp4stf=*u^IG7+v7m{re!+l6KtI-_*j?6e(P=gn$q
zEmmgsQi1`No4LC}p~9?j3Ye8<?{opB+N>BKp-FndENd=C-(cp?!|z738MKgXGHWk`
zPgl)iDLQ)1tcUVN*Ug$~A$-H^G*yzcm<9U*yUpxRibA)WEl&os!))SYy1dNx(jBJD
z%pw5_x6PDPQhV2IGcED&n`!1l@`2fGT6dVb&87<&g{%3t)o}la`K=x(2AQ|h$~oBl
zCqI}EF+X1h&`|TRt?((#{Fe~G95p{g>CbR;pEgJyGcVo=ktp-(I$%ee*H8gVjCo@v
zn6c)ED5MZ){?{LH=7jmrZvZ9Ud`>4?2`2NZ|3Ng-+-n|SPMW8WhZkAq7IZuy$9zsU
zoXIu6QV7sf=9zTRB+q;+g^vr&d*}gNXx<lxzSHK(w8JklFV|q6ip{;8z$`J3rDWS#
z^HH=yDmCBs2f)smfA%^0%FO>@pipjZ@_h)H3Ufy~BwuB2lLiyj<^>e$y<ooOC$#RE
z^K`=Gu6gT!MM&o7Xut8m+$<Bb*KIzN-Y4<Ud@eoeddxHFtJZ67QwF_0^U-t<dt%;j
z0j*c&pU^XE$owWnFrDRdB#?BGFZ}Nxi@3^76s>fVdn*CsF8|sQzU`L(OE+B)c|{NU
z_Q;QZ0Yy*wbUTdDUp|{E;{)V7?gD$i{P$+)A%IT%vP1IO|3dGud@5D8r^vf$o0KXS
z=!usuzeJny4Ee9$0xVNL+s%aLNqGy!BC_N)@4?}0xix(vIdWM8W+qo&R|L^h@_XIT
z&y$DHGA3W1k`GcK-$(~M3*{e<LhH1A*CwbJ$v=1jg<|=qw5UHL=kw{Kkf+hk@vQs|
z-GWQyi^l`{oP2C3l_H*(J5Y4COzuw6zjAr+N{Cj-N7MCKDL=Llq)MJe8UG9N_$v^(
zD1Y$`!@eY+90Rl(c`?;^UzYpRdrxcS``p32B0nNRvQAz{mq5MT;U-9<Jn%b6Hp#<j
zQ+!pfcuGgnn&lZ(C~-}`nGWY)m-`xE{)T)F9lvUkzfM;|t2{3Qif!^f+77qNo1MVC
zDW4<7N6{glG#{i>K9Xt+ZpkONz*3idcn(Bv%MEt{c1QlfSFjMESpNd91u9bBf<mw&
zj!x|2RrtR=#n3_(SN_GA!W3)!K*AM2ehjo@3ibr_BNaI-K%x}gW>Ab)?4-K87)9U?
zFpn$N&jU=HV&-eWKB1^w2NJIcT?5QSMITj_B`YSa2Uv<?7oC+orBJrRwLC@fTkxsC
zq_{yBRH4HDXMmnlym1Af7Zn+_lDeemr&_=oh3|hsB1M}VeYJ{T?Vxx?VVwZ9Iz>V{
zrlekR{yc`=pfHby-9|+!l}@%Rw2dG)6>?etb|{`sN2^mYXFcrQQVgTVZ<oR}i2|Cp
z73H<?`;OwU8?f&w=F(A%`-;`H_IaRKPgQu`iYxTQe5g1@M^YXscGGD$1X}5ILa(Bk
z&Wt}+jHIHRK1HQ3u%9TFBmk^magwr`&lD@Ej%7e$OUuFMiV})h4l1UaR)W4zRMWTl
zrNWGgL|-Ya>BUb&inOJ`cD6{TH@LW1y#FqUtHlUft+-kIwiYdSi_hu3n7b`rL}8vh
zECy%+x5q*m4)47zj?(AqZISu`nENcgrge?41-An&KZ_bGc<*mfcbL*$0Tv(9Za&aL
z(F5%L7Nwt~b-<#07xcp{JSgmN)M6aPc*8CB2ZJ25*iLubNQ=p>Xhm7*>9dcv82<%Y
zZ5GEV4%BaPb_~Frm7o3yNf)KnF&K1J{*pl6D;Ksw#9irGMEmdE%60RgxK|nZ5HeoM
zub06^Z{^|T0NtlFxIolb*=z|IKV=DJVFQ$9O27mvXCH>hA>~;VzDf@(&whx$Bg%na
z;C+zNpYB>A$|frP3RMQs;yq0H2Sx3UDq}u?!ZGF7Sfrs8Q5i0UVx)5Sbbv-F?^EV6
zM!Dl-Fk_X+ogjK#x$+~R#VMulfut*o>1Lgwyhk;$naVR1(Lbq_)59%GDc3_UTbZ;F
zk~zxbRQ!8NS@Q%ac}o2#I8&(XrUMK`N*V2EOvTDyHo|U=axIl?Use`dLbO&{`4u{^
zDA`i9>Xa^j0;XOmn+#@y(w}ZSt;!t@XtgO5y3p6Id}V~>O{IzIw>y<zti(X?DCb@Q
zxvPx13dwuQ$q6ujUwJS9A`g|7w4!)qQl?M^W{>jV>zLqPW!VS}=BYAw9Z0`2m;w#Y
zlzAfnGoVZ=gQL%tZ_(0iP-(D)7cZ3S?!){`Wi@Rqd@L;}iREiK`##kDETaZN{4IZ&
z4rYL*a2+Jj(m4-$`z?=F!~6kDlM8(<4q8s-fqlr*hHAGCTc#F4@rdP}R<wdFb7%__
zY#EjY5@Pw*LP&;MZlvJ*QOjStAQ^6{9tLvE5+MNudo0h;9xu{zLJ1_JEdMUR0HZB^
z>Of*GCDoXO<Cc{aK!~%PZ2A{4CoIE7a1$)Q{}KaDwET(|L`jz4?1cGbOY2WSQY=Rn
zgPCgiw*y*fmQ&xsDAFyrO@v;C<v4opO{S%5JJho*jZq+;RtpP3_FAp{4w7D02S&oD
zK&wBEup4Z(Y9furYWmj{)eW^8*auI;tO6%NBit(16`mfmilwwwgjHcBOhj7!MtS@w
ztKOq9A8mDvDnFB~tZ6-V(rVmxkSr^ADge#4vQk1a$Li(?pj287qqt_3m6BGB)mD`h
zN2s&<iJp!1R%vw<|7fu4pvsO$t9iZPHd*bpfy`B_8oG-#Tm5?o9$vFLdmEtFtwvL!
z`VFfcwfOK_tR8<1FIuhgeure6RqPk=zTIldDv%DVLE3P3T0N%Z{w*t04p6$R>?!Ph
z+v*8r;(D!IQY85PJ+^w#h|WH%xpY|XiPenf(0FRKb0J#&R&$2X_smN83uM45hr&_M
zt-hx^&_Sz$v0%Qis-rmjODk(i*uJuQ^c*c`RoP4Qxv0+m4C1O9vIVA_>cMU3xvREM
z#mwwhrH_XfCJ)sIo6+2(s{0M1o~lV&=<ih(({sp6^~p*wy;Xnw4->pk)pH)^eN+Qf
zfa9zBoiZPOsvkqZ^jG=Qlm@6?^`I|M)j=;G*{@O_$E+Pxo%s%Zhg9hsK@O{)Q3cl#
z)o6Me2ANcAt-uXdakRY&Q8_<FD^%re0fS+x@vSg_RJD*2WXDwgRC^qu;&6gi8mW3n
zk(nq}R4MwRRiDp8UySO`c<9Bdj#PsjR|Q4G#0k|9UBK}wwFr>})xUEw35lx1tI<kQ
znI^>oCRugvzelv{!%yHvs%nVt)@iDM{g6pl1=0>TLpAU=n3<{@H!!9w)xigl%vQxw
zG$%*(zzLwas>EO@oKhvf4fA;_-CDHrRc&;)El}M*4QI}&&h!H8yy~y-pirh7ZK4%=
zxoQ`s=P#>b_d=#tb-5NJyrL3TgIT94J_)pX)k}X^YEWqlV7E~<xf^3@QUzy1;i@Vl
z4QS06A;7Mwq_oAnuCfRP^M=ZY0!=Nd3A+H+s#-yl-=^9_#ZNa?oxjogvqR<a7lziU
zx<N%8w^Wv{(CAXVuY}BP)i?BXxue?R3(32x<8;%$r`keS$$iz8X;65eI%NxHx9TLF
z411`OxkBNQYWY<-^H`PsF2MR!TPo1^L{&!jgr}<Ov_S7y&Du>_&1b4iS~3o(23#@F
z=PIiRXt-Ekas<=WdOw{Ya<h)}!Fb)R_ix6SJgjHa;$x5X$*X92TFYo9wbwf6XS!sq
z?>VE-+uH9i^!8b=9|5M1wKbJe`C3m(g<U`EAL(d_zxA7uR4f)?eRlyY#o1U|U=;B-
zIZ}Wo+Vo{ZG1+F8Eu2ZU8MPB8(rtdvg<_^nA?^6GY*vqjrBgQjl&P(^DanR<yG`aN
z=(}n2aSU1=Hc`vb>a+>{2I{wLhDJcW%SJ-UiXNLl+D@5zZS2QD^r=l15Aw{$pAx<U
zHis=hp4)g(nb)9A`BixF!X}0S5if0+6fj@e3{Vl%kj=;xpgF5Qr0dy59kT)kUDcUX
zQ{krG{5cf%ssG*&XdiXdhd>EYXB`7GR9z8>Q6Dv_OX(IKu2ytF=9v2X$!JBW>qbE|
zN<C!~O@jIvW$;tf&uMX)t9GOs?NjQv7QtYi`r|PWDOC%!F*v98+)r1x`ZU#Om#K>=
zCSI;~{0O8%y&?g6mFk2H=vArf=rgERo1Xp*yBE~ADXMu<9rp;_OX?C@@YbkvDWcn~
z?)?&;UQ_o|OzFCM;15{3q5i=I3N7k{eQ33+57)qpHudxkAnod&ml(uNb#O2AI@D#)
z(CSp5?L_OAI)f_3yVT(#)NiY&m?-gcN8R@VmhP&5uZR9U_04%`-B<7Y05T8M$0tF*
zTkSXpAJ;>*nqH&vNZlF$y&iSh5{#)=U3nF*Jysv2z-6C$_5z?hQD38n=~MOSU*TcD
z`rIXmJX4>nLf?SerXG^d)iXRP{xYbx&w+^->V7M5U#jQ+1M|+j9|hiB_%;2Q5?B78
zCqQ%KUpYY1oj+Iuk%RpHa$q0g?LG(g5#D_qz=HS>mqRa<pJ@%fFg~3gm`8cnZ{cq^
zZ}ktnKgNH05v>T`)`?z)7s+=<(x=UrQ2->GZ^uSf8pEf|#ze*PpT7?M<NR$Zfr;b0
zC~$v*|9l}t;`tR+B9Xuky@VHu{3tz062H+ICX)H~Jus2NTW3Ntm46@sbQ=HNFrcLK
z!8Y(dgP*>M;{Ta^zB6D>^4eJ#VHW=`ZF{qM6Rjh2_@7TgG?)Kt1emAz+39HI@t;%W
zT0Z|8)j}2U*J<5a$gg*T!f8IU5hjZG96E(n%y-cXr_S&}6i6@O2Tw!&EN`IaS1E5s
z=VMIgcm;``=VRZ4ei^^A9x~<pWQxC3@PU08Qzidq09sZ2v|;G0=I306!Uf)|3JMqb
z7I%nT;@#=tR>NOYK=Lwg{SicJ`Q=nTafM&h4D)sTe6m~5|6mDb1Ak2dkwz0glj;GQ
z_?9goSNT<RuBVwVqm|G#zMgUl*ZKYsh~D6@(Rf?<8^su5E06z;gG-+8)<CkIPhW)A
zO@8++h;;C3JGj=#mnhM9i`UJ7!7lz5E!l4KeU)I|;RRX?+~rL>=ygB$_@xv@y3ebQ
z!_x=+s4u|m=4Vu3Ob>bMI!yN?K8%6}J^U8>40`#GEiki>d9{dEA8$t~o+tbmdQrzy
z-s^Wb)6dT*OV9Y<%V24Mf4mpuId4H>m_a^q4J2Ri-<!UL{!89A52CMlr+AEah+h&4
zeP<zP9Egi>;43g)g{f2+<|d4wgoV5C+m~qV7XCaBe?5fCf6>|_9Q^=3c?zfL^vGUe
zVHte#68@x(fwz!LrxW%GYa3w5NARGOzpt>!-2@pwfpbQuzp$qkmI8#IVj&YKr2YXH
z_X{V?;qU?BLM>Vcg>7^k@Q`43914epehO6{5qjw~evq);1Je~O^msx&L@1{8QmF98
z*RT{OR3}64s37i#NVrhB1cr_Y({rh+AVNr{Gc=LHrmb)$N{FFT2GPQ_5Xi&`!>FV&
zR=BhXipPamDvOH~{tW}#3E}+*kc=04KY~btU>6UPC_JN?O%nbU;YG5r>@8rX2+fpN
zN)@L32xgjKejg&~!j~86`IjL$O~nW^h1LIk4TTHz$jK5C)R4&*w$iH~a)eHbQRWKc
zw!{1>p_C>lPiPE*`F!EN5v>A2q_@}<3Rfv0a9UWp2Bb)Mdj%AVg+*&2c}CbZ7V}gh
zO#KlfJ1e{xfLT+i@a9uA&k67T1C8^72Nleg3GG^ta-p1Jh84mKDyyj!N<%T1Rl*x|
zAfQ@ErlRr-!i8NJ+C^bfJkTx)C2?rg2+s7qzbuTUC3&r|_bs?~MR4qc`8pxt6`1wH
z<Ui1AFbOA0fz~K&b^&P;?iIq)Rbk$H=xi3=7y`^SVUP+suM1UlFS;Q(QAJ6MaE8L5
zt-?GB6xxK|xoEWu`AdOvQ|JhQdWX<Tp@&Xk4z2oc2|5aVb_u#5VBQvv<)QD6VESPU
z6z>WHec;{`es2QWec_v@=zJh-rn4yB!ht3X`=O9XvHnLw#x`76J;Hm7F^XP6UI5U?
z!nd?Q=o4gg==+KAhzd)d3Kyt+wqNj|m-jpqw$pZMK#<X8^<231DXxn_VZP}Th`tae
ztOxg{u-O&{UkRV=1{o5Tr$W(L%(MWEi+F&8L08d00dY6+U;*5A7u75zcZ<6zC*mQF
zq2=!$aSbh^J;jB$0KHc{PFJ;;sGuyOxA=;|$o7dBDW2dXmVQF(PhZhX4fB5Dtww10
zi}kcr4G>$E01Xt&--O0~@jI$`Js=M6h2lYR6ixmi@neeA92Q^pf*cX;55iKA7}^NE
zU~!-rk|E-?YnYi(@rft;!o+#&A(<ow(>bDKG5<4q6;O)UFbOiLVgv<>)5M=BsFN;c
zQSvrJ+(O&!OtFyGh$qD=dKzYli96tEwwO@>*K$PvT@c9?|Dpo!Q{p(PLCF)(l>jqe
zeE&4`3Pj0cC=`kY3ND@&SF1sa#Aa8jsw)=H^8h^~R%b${L_8UY)>%<ji&m-lHswvu
ziJ2~N_`EoQ^73V(2i@$;#bPQAt`MC^!bGLGjy8T(qV5~$Rf{i{0_B2Owh)#siW})n
z$R)9eo@O;-=t{VDSuCRcfvHwJ)ens;V(xFSR40B<!I^sTjZ9!Sh<&t;Y!rW_z;=^(
zj+UBNMF)zuHH+V#!LYB1TR2Ew7Z=jOryHW>Fi5tD^Qb1bReakWq)l9Y02bQC9ttzx
z6yIJB*E+<$tpMvZi4GGXb4&bW6`Eb*@(K*?wzzN+(C&y2VnFVSvnXb9PdwfS#rxts
z8yI{bzC(wYyTxgAWbdI^kqMDU;)B;PrXKN|ATWEyu@pLgEH2s$yM5yNFtnbCUFm2&
z75`oZk$%ziJyrZY6E}>5`2o>`swJL_|D!7HL2<z>Fkgtz93b*ioJNcPSK`w*VQEOb
z<PB$>HIAz=G#5=o7Fw>FEwrk1(^$}M&|Nd58J2cyMn$0Ip^5tr(0eqwwD<Sa@Hb&$
zuV#kn3^cqn*XS1Et$8yIWS?d;UBNz@7j$sZSMvou@BK8cWY=Hw^f=H0G~0X83e*JB
z2eV(Jrp3nr&HGQmJgAvZf!aeF58A;T)<o&hI-+?+A>AO&pL854So4C4+(I-yLnd%T
zHKXYc6Q-Gy27^a6h7FJj*Sw$z{4vc*icUmml=IMv)I9Zpzfl^_6<$PZ`u*W(jAkp<
z4aRCB!_hjfxxF2Iahlejp>RU;f;Ld`njO1A5;VKAA(^OojlL>Ln(=;=|4Y_<C7_w2
zsceF!RL!(+pr58GoC0UkHOc>jMutXX50OmG!y1@BsTngG%q)#3U31x*wMAg&Xc8)+
zm#cZ=2gy^KOH}fcr`b*mlYGsWbXzabIMJ*ZY9>0O@3dywAm#sxG<_5ZDc1Zs9QtQ8
zLkj>}qS<o@t+Sdf*1#^+#7e+Crx`X8isv=Hei&Mrriif1HIpMS>lK<Slp(3q)ODb*
zO7jgpfT}eCeK2@IGl4<}7d6S{ki4XsL-+a`%`5r{O_w$G<6yp46Fwj0ismPJ=U<&B
zm==)r8Z9j_8Z?h3aHdhSkv^CvO&A5uu4;xofltkvy0MVFrrEIt>en^-(Xezw6Ezhk
zS~O3GL9bPl{w92C(;RJuLc3;cH&AYBUNd539VX3#t1!{28Be>MTbeds$aHCf!eQdJ
zCWvm+cQnJ?K<;Y3z6<6(&BPlJxv!Z+TZspnjb~xLTf<NU{h?-3H(HN0UlB@==FQK5
z*{iXqHOOPlHQG7#Y2xPs<%uS27(||GOv@ADcfTg@3YyO}E9rV1(7Z+`Yo2R{7D91Q
zQ%!rG7n)O}A@Wl5@B0vWrHMKKGNj4<3L?(h--aOKqSex(#Z^09guiau_im%lUHjS$
z_;f(KjrOYtwX^fkcS!qi9QqDxdrg!KJ)+glLT8ZnW2!y~(RTSkBUHOO3Nm5ZFDY_)
zR2yjr^WoZWF2L?F?bmcHFhcv07V44O_iq9;O8d!Qa64LCNSHC&jpopc)u#Rfl;hed
z?}Ef>>nZqrLVJ(iP8P3qc$+fc3EJ1K@i`@GXHdL2N&AGB1j*Vfl&VP89$pHKG_8Ci
zNV;}<3qUipk$PCl)H+d3&q?iOiq~doKfDE>vbD1)mYbt()<QB@>qzmJQ`#+b5+_f)
znYJ$ZT8?6)1=`&kDF0BXo%cREPit{K;jyGWPq~6(ZCxj1&S;Z}S)yIy0~2Spe_O&t
zsdh6};hxhf9AN&u_8INi%CsC+{FQ5Kw?VQ(+eT~CO6?a@K&rGJJAqlP?U)7g7qr=A
z{-SnLIQ=V-OIl?B&}y{bhJ$-q+w&XrYqg)(LG+4tX*fuoR^kM^_1gEY!9;`h!CXi-
zYR^Q2G-;>N#{8<bi$>q9l~7Xfn%4Pa_;g+S1}zS6XwUfrvqh^MNnZ!;?nGd=X@3|C
zpG@uAi=Tqt)Yi~$ze8K}FP!Pr_R<>jmNxntG`h6Erh<7}+d{#wJKDcffOc2=wi1@^
zY46Yp*!x=TOppg!wjN;J+Aryb{80OmCDb2jGX;<ytu!AV_G)Va;M!wt=~tM%K9jc7
z12gnQdy6U~o@#%X1JQo%a67p8OzUV4y93(WM<DuKn?|eeLG657h`i7SybiRNTG>`e
zzS17=f%=fPyc#0Ty2?;^=%TZG3oTdOB3hKX>HI9wa@XbWg5GZ328uv<=uBx;hrUNQ
zld_+lx;a$!yjPdw22d~EN&@xPeMo7seY$;AcjKe`fYP46x?Fmg`{`ulw!dy}HADh*
zYf7LVsGG40BKvjIC~|*5H<i)>2X#kp!2BWI0C{*=x9SSW5#8ISkD(Ey8<+_FVBPLC
zOk#-cwmn7|s*8FDBur<a2ij4cIbDI_x@A33IHvoTPB=&Cu3G>mQn%(L^rCc*XV8k)
z+1-XhjPCGfXvOLx{y^)vu7XbZ$La3d!>1FvXKTTX*R6>&0WCrI@fBD~)HTv`C`so;
zi^OEztcQ?E(Y3w{>{MOiT8O0S##_OQblrqjpk?R+R-i9a*ZBa>oYZA4gL;;(&<rBk
zx-WKsnWOt(En2y{%)dZR>GIq$>v_6|70}Dqt^bUke+9ZtTVSwIH`51`a9USEX{sV!
zdL)>|x{M%LI-|RK3}~ggJiI+idQLZv9^YlUis>*|uA99Wu2twfbD>wMTSDdYRl3sA
z=&ROkr_1t!&Ok}Mi@N#SA#zE#l?qX7bpE*1P14J{-~m{w)$MXY=M~+UA}H4BzMKVz
z>vauO=G368TmqOz-CK{rY|`z>#Akn1=kAZeH0vf#gUEGV-$F2N=rk{3sYUnxOZeNW
zoBKbs+H@CA0=ixIl?PC6>gJutAUbqz26$oW)U9|2ptp1z_Q3Bh-AF1$x~;o#1)_I!
z8I)MMtK0l8^zZ4OQc>G|-QO7?4|MB(fMmBWnAX$}b&(uI9_a$g!0gq{rxO&9b^p==
zuur$97vza9hOV`zx>SnS_UpI{@b{TXH;O))0o@eZpFG#?cSdVa#{|Lr3tcb;K40pV
z4#DA9x+hIw4(V=V*&ub+Pk#iai#}%ph^yYe9mGu^z6@Tt>#NFvy<7ha6$X0f^;2MQ
zk6z4&h^PJt-IDg|lg0zZOK)1R4_t43V;3f4pZ>2y(D2a@qfEcA{^dpV`RSAY+ZO4=
zPeCz2AABFoK)oBSGxqD<--Cw-^do2$dr)6p2M-VFPYr|l!}@<HpmszbNQF8<`Wuw#
z3)XL^YO)Z0>O-i9>b0gsI2@+uX5*tgs*j^2Te$vf+7TSn7tvNRLjUA5v?BF8C&7G_
ze(QX+qV@kYpcSK^Ph*PJpO!-MxZaiO_2cyUL9ly5AMhbs@%l*@K@#*Q9>Y+gKKE~o
zEJ>fhfh6nYQW-i^^ks(^oWa5UrPJVPre69X&`#=qo{m<Qeg)+Uvh}0s>yV=t&0#)Q
zKm1?VJ*7A8$6)gGuV(`#Utbyy69xJQ6#gmHpHgEir}gbS!7S2;(sI36A9fDVXY}$g
z%u|Ve|1MZKtH1FNNU8oq(@Aum)7NbSIj>)s44E>$%o77G*FTJf-3on;H@v9SFFghG
zReC)w6|41`e?jDeJ}L>8F6!q;Lhq9PGkYl1=mW#x%w@g*-@vTZucVh^T+y#%VX#iW
zk)kp6`iZWPY|wA`jABuZ`VXl>x=HUz<<eL6KIM>U*7r?C>zaNV9Voi4KWvGi-O!Jd
zqSc}wW)HnqedR2)+VnHuhh)3{t$SeJ)Xy9ZM?3VJN5FiiK6WG~p-2B=9(?N6Z;64z
zWBuHZ;7p%BXg$S(pXhDqKKWEXFbkw#f0!1R&-5L|&>zsxY(VR|eoqJb2K5W0Vd;f_
z1(oK!)IXyQ*em__5kO0_{ay}9{2N)iWK(UwdK-gCw|y=_Uxw|L{qQ2w_F@j0Cv6+N
zz|69B#1_va&9P0OHP<QI5mY*oXM1ZCWD0DTIRUNEb{-`&Puu#*=o7VlPS2BK+t6Qu
zcE+|~5TwL5f^tV^ZTV36TWZ@k3F_x<`D64++Bzk}nR44V%^^~0>-HfOs%&+aAX#nO
z=K!YZf^F0X(70&3fuiM?Y^$eXhH7k+ve9|j){la!wYKeZVg8Ek1IjJd*>ZG*uio}I
zstazgoj|FPM%&adFq>>A(dO)`tu+Ohnr&~><LH`g;qMs4b=%2*Lh^>~5G~1DY-7Iz
zv(;oPQNyWD+b7=e^tSD5v@*YAd*244cWrBPVg8=2oTB^pZ6AyQd0@MZ!mr)7D}15w
z(DvL9knFMj=ry4A+Pb<!{ju$hk3jltQHX<&*LHLUM4sBJ-UsQoT}p3pduF@Ll|Eiu
z(;}*7dv5EM1TO|{4Ro!)u<a>>iI=v6R0{FR_J|FbL$;TvL*LnOwj0F7@R<R9u7&_N
zSaLHIQpCjF&_NH(-G=lYh<F&TZ3N~XLl~7&dm28c<lJ6Eq#A?pGW>ZN7Q7AdCO>fZ
z8Q!KunvY=*t*d+ug|znZGwiR2qQBwgR)7W?CX|D@->{8dym7#=i?Rv_4L?(n)**vP
z`PsvUf4m@a#L!6(kRXHgWmpO}l&%J5h~ZDF-wZV@`2l)ihI_9ddDKueffDH9hVc|u
zJZAWS9^Vm$d^0FU8Xh(PJKC@_67v;fc=Zj&8*30KRd?L5@@q^<oZ;gWa4p`Tp+bQ~
zgE`$jk_=9i(Md5l{REO~@ck1aX@<}Y*iARY(^n<Ku$4C5nTE}ms1`lT;MNP#Y(oO&
zj&lreS)nu6aFrs<rwrm6faV!2Xos6`*!BTn3Jl2y&?+=okAjD%4RbGpS!8I`gIR2d
zq(H<O!=3p6D>2js!qKya*Mq<;HMD9lh;xQ_>AE;?kYUmBi?qzJo)$*shHVsMsWiOy
z0;I~Y$OjtLhGQIDyI@#99<7Upr4**VWO$Ei#A*y?bznX>c*Fp0kKMZzmfvevK+#Mu
zJ3nXi9k%<Ksx*S_0uIkC!?~{$Q_vS@XQY=~oUpr4gT8n>HEmrI?7XCaPPDs1H~A#H
zXY*h-+0L1ssVR1!tfr~7i!6lMG`pW^p_*=YkWQdy*y$;Ul4(~-2Z>JF^^5^#wq5TM
z=;heCOat?b-BjAul-O-IQIW_+yM-p8U9$VG8KO0I;*YR<*=~T=Otp4jtbj9D?2den
zvDDesJx8nF?gBmc8tk^jLA}v#(Msqw*_|tbGgs}*38mRiwi%e$?8LXAcirxMJM?bY
z#YKYIV(0Zb^jhuSnnPRoHoGE<_q5x!(qg#7F4qd!opv+wfaYdjb_+~*`*HMu-);ZD
zO;Gf(|AkKKgxbIJIrPHpryfV^sQm<5ria^KrhwQn`wu3f6=5InUk2B{xeLr_`xts~
z#M-}843rf65<S&@rrHPeV!Ubg)pXb|-G13$xI8lKYbe%`Y5!RXS|{!2(W)-XK4Kp%
zowom-67@y)n_bXXY#(I{Qfa^CH2kfyPg)F8ZJ$V~#S8YcC`EqB-kY*%m+fCtBC6It
zT?=P!*w6K+dwq+2Hf_aQ?Z;Abpv`{z3Rt>nU-AQBI_!U!gY?<wQ{w!oy^#)q_S+j9
zFeT6IYd7Na8L(eY_v1nPHUERi3;TN%Ie2OBZGqM+`{DmpvO652JE)7pw^Zrr>Tv%v
zc;V(SYA>K|+#U20;O=&)y@AntIJ6yZtH5Qs>@T?Q?ch2bp6+w#YJ`Z7!`X$v_H_uE
zhL)d0Dy`819A?nFw*npVPoi(XL;EkVbig6%GV~5Qp!^HBB8U3XkUZ>=K(VVM4k<sP
zFWBLC0b>bq7_|TjVGiw)=sW6=HVG)P4r9LfZ?od?<5E~U;ow1+K)geZJxHR%MXFy(
zc5tM9Zi>TMD$-ANSVQZBG>6&0z+k$=JPUwkI4Jgmndz|XaB(GuRJ01}IS$`##5i*u
zR@gu?&!H~|UYvC(r8{t`!|`e;oO6h^hrj0?Cei)4%pvtGnB@-h=%cT2NRohA<xsyI
zDAf*oL(q4@p|B8r^$sQUvV{hRxrYGV;_x|@W3)P`?BGkA!#UFoINI*8>N-Y$)8WsF
zFxcTRiH>q~Iy6%u@GXZ0n*h`0&`8xnw;eofpnu0<-h43cIt)?B?ViJ&Mo8Xw5S-wJ
z|7-6*VqpqDZ#~`uD{l|bSM}YQ2jQC=^9FqZ+?kf+AiJ49(|;RXW(+;X_Ar*aAmhpS
zAA#~-<|}%Rcroi}*1egfUrL6_LYPomnV)2=kHOO{W;AW#vl(B?@8mFx8=;rW3_F6>
zDW=L3n0d^_zaf&(c%B0(V5SWLtdL1s42MrM1wT=Qr-*q@`I2I0^=QbPVe0pyRl@vA
zr(Mr7N%TmsWJ=c!8z$>wPSPFNoejMK{oSl3mCJgtPLILd!^RPqCwnjxt-b6DdOfTc
zTTz37db9f}sJV}Inh6CTb{G9uFJHFfdy4S*vB4G?lRtZ2z<2}L%wTvC$d+jp!(`!X
z46+!qD{L_~&oU2g50!j)a|Q&8WC5INHn0zIEhFG>2v@37031J)SCr%T)OA#+^vQes
zATxazEs$qS&IIz}`Bc%eeCbWNx4z4C2BJG2(?#fHvllE+#_Jr$=FKG2%jmM1db-@s
zFjgb~?=uxrXhHjm`<M;^4{@$$aL8HG5KJSGjIjiCfTWTRJ4cuq=!8t9*$K)vM464I
z3btso8VZ=Ts>WV|NSEq+Q#b5)tHw@7=M&Y$a)`cAot=V~oApl=5c0C-Js}cc?fW*c
zk63TtiB`Dv{56n_wLVBy9LKG1z6LMitYawce8M`9qS^7*k7@0iVEx4}7<!`h5{f@3
zS<j@pv}EglsZKe?dY-Qdvy*Aftbu5r^>^+dXRO2L0Il459>w%7S*L#s{U+-Z^s1Gs
z*6s;_X|_H~WpUT6;~ilBx^><UAl=r>7eMl%^^WssJ+fBrgk+EPOv*R+TJK1L!N=C~
zC|uEJ{Tb!XpI944P=(b~>j+QS?YFMq0hs~oheu%kxpgH~f)85vP(|7cYwQ2P;7e;K
zTJyfL_CSTWbjW(ta9}&zETy%&i;aw`mtAdUd7!n&hM52qPn$)KXzjI`=LS75o2z|5
z@wU-0Xa(5ZLP3m48fbHSH3quh#z0jo2W(!&!R|quT{nOhZBraiGix)S9^vse0hged
zX5;!C<}+<Vf5Qm#Y#i=E@|ulg68f&&OuGxxVlzlN@KzhyI*^+-5nC|q4x6cVFf?HE
z@-8kNXZ3m>_DuWK0kmZIQP<Xk1gXC?z|t|bFa>@eS0ADbX0m$OUFe@w7i@;5eD#(u
z;8Tfuh8y%N)Snp8SEDYWoN%Lh1Z6;4)D~2UeM{|`29XEqhs$8MPrb(*&J3!jN6|d-
zx9Cf<7Zo0qRPy2#6#ek#2Pn+4kFRfni$454+A;X@L#62R<84=A*#10ES&jgHZ7f6r
z`E^tUyr19j0o*>ohc=_{AfNLV^bYZ5a{zXjud0OJ5k9B_%xHc-ec5C9pNpXo%bW75
zXrTP%Hq2!l{|&_kPVkPcfQjdOs1z-M@8ltx$Ulk!N#YOBfk-mnNA)}@yd%XDQ~8xe
zkWAwPXgi(G?|KQ6!M_-Q!IOMfASAQ+CzS8X=If|XIEQzl%yKRtW1<wsDgGcmO7r*y
zv;oiOchW!$_{ixPS|PuHwuz_t$!nol#3#K8$zt9!5PD~LbtRZ3{DF6%ca~p3WmlK@
z(P0=;17GqFOx)n_xj><lpEVpF-sgX%VyMUbYC2Xp$e*0I4A?Jtp$?)i`OFE>f5lHP
zMCTCy-Fk>R3sLmGi+zHF93nnKPz11j1+PgE@e`&b1Jqv-sX9DB7@}>&exaKjJs@Ns
ze!Uh^i?CLxM+jz8Kt~G0j-eGLEE<Adv~Xq)m@xv^0EJi~G6eRH3te=8IZoL53X<`{
z!lP&<2uI^#AyLTt05g&#d>jQs$pW(qbC4o5-G*eUaODq>G+}WdP)-TEEHJP<;gG2n
z`h|jv9k{23*N9XI`@RHBrLe08=BtJJsZhKi47`U{gRr3=18fu;DOrD27;^%4n}ua3
zV5vhmq6b)~;E5F)Di*dkgLDab4<K?|P|`-@ju21bin~JGd60X;q*z)(-xreT`TRhb
z^&2$0g+UoCp<>}<c=1T+jzp_RnA#4zy+Xt;z&sX$DX9EJxcMy<o(jE`X6qLcrlR#s
zuvi2#AWRyC5k41+9>CE-K}vUq7ed<>7<wtVo&ne^!8ew6O+&(LTJ1WEY2QH6MGOsx
zjH~zo6~4QPe?5nyyVz2IJ|FQrdoX>)3Oe@UCqAKLLjK~CKY<n~R;;9tSImC`*A9r@
zuffrS;<9b<B2wHyfvYG{pyyb$C@DcJM)bcw4EMKKan>P#9v9`GLNQJp2m|N|aaBDO
z<HeUJ;C_O5z#n~yV*PQDB=OEAIFl?M?SN}3V&8J0rHYv&&`J~MheISooHGuXnIdxw
zt&?IZJyNs8@}p>Fi$(v%mc?bHXUY|$<KgKk@hrt4^TaDvnC^Tr&koE2u__#16pEXu
z7UZ;8K%Z!l`0E^aSS)UOAIvl2@2^4OqUaw4^OwZ9KhSqs{2(5BwPMSgVAhK<B19U*
zYc!P)#LlCbu5NMen;?TGG0qvCFT_byY4K8A@dZr05-q+4b4WC~K*L#6VGU1RG+UOz
zeOHbA7VNrd8ot2HxNF{Vgu&e!e~R;YXeNAzzCD@|ZvxCyv-fSF?A5sMhPsz#dKg;!
zG)}bO@zG3>f$6I;aZ8}+rzxW{F@Mc(@1Qe4V}2IcftuBI=-aQkPD!By8gEC8>7Zr~
zt;Y{(s`jIGSTo=P&?A~{MNkjY6n_C`ux8s%V25awRJahQnM&)W6Pl`-V8&~Fe?Tii
zWBxBbkwnd66TJ%~N#imW`YD>~T-Z(3JfJ{%nr47jo9P-;1-!`6%%zIkOilL%kYi&$
z`UWFRA0zo2&SZ=kOQ~Vc_k+KKiN>){%weK!?C>I>yqs7@v4mF>`(wZioV0u;$dO42
zNze<L)S)r~J7m(%1fXS38qo&xXD5~FAX7SN>lcuznxvxJPS>P4p8_rJqtuI3T8y8K
z9e()z+xVM6|2>S(`foCr!;8&Mo%p?DK`oSbDt!R&Sbq_!&di$=0PDhhd=)KMCgK<b
z@CJj>;ehdG!Ybf_50gj>&x1_oG+-QJ`hUV$k1}gQffCM4?Wd75)eQRLn5aRF^#tQ~
z6?*Z^^&c@+2~6Q6fMzgv_Rw$`N4hlfnNdHXRlu~31Sw?hU4h<drkSE^<;*kFn~<qs
z8tVXB$wXd*i7IB}X>`^z$KM571M`s-6VS+v_k@WiX1F()ZA=yAVA`3S&p>W6f1QDP
z2eWb<M%c+Lb_3=uMmGX(cQNPM(07|rlD~JDv{>}@F#SES(90+e(USZz(??;hK4v==
z;y+=`d9+?K!IPo!im9c-uOY@Y4qiC3@6iL;h1F86p)0$j0oZQr&{vRjXEhZ3+08oA
zw#tJY{sm0zVY`DN;>lJ}mS-<Jnd)l2*b{V5^=5ybP4~Zj?ECag@L}`1;IJ=y=RFWV
zwjcn+pADfqUI06un1SpFS{&?Wr999MunS%T_Ca>G1R{sn4=LS$n3epBz9a1R#V`@X
z#?FAF!R&S_PY+>t`opJCcIyJnVHmp;!6UqGm5m<_#aQ-;45G)`C53P%g<Tws!KAW@
z@z6+PU+aNLI@=Ki<|%eb7nphMK8jA{v-@WQyMXQa8FmZV?<h8Mj$OJ6edpQFydhb}
zj-}8+IV%{UUco;50<KlE1x6^Cs@T*-U^lbls6OEu+eH!K>+HQBpm>9w`xzA5Sjjyo
zcChbEhejvs=LP*+tdfd;y4bN_(dWx9ngZ|dus_oS<}N#eP6*y(+b^KcnQPbyg+1Il
z9wNTnB|BI+$o0$wGt|T_d;z;r+?cg6k-&w&18yR>AsQr!8%Nh{GB@fov{JaUl;}(4
z;!7~zd@i{KCJMN<&tR~SyZJg?JI%G$L!^lN_`d)i*K7&%C0xo_D4gX!rvOAL=SiQ|
zIqu{^ICGvexo-q^8TVcj^sjLLy9h6uITw4tv~%xKCBq#qWgD1}xOL~D(a+tY@Y*Y`
zd?^$>Bv+}fc8}!UA@q4l9#SF1Ude7c{q7~%PdjpN$#aTf?UV4Iqjf~`$rJb+B-uvy
zjbO=U(?h_7NWP?#4xy4ql=}&j%$yIIqmoTOLGhTRpJp~fa_SQ1B2w}Wy+%GtGKZ@3
zqb1XKp)W=<U5P1;l}y+My>v;qHT=z$%-sZ1B&qonKAo3XghBm+q>e7xI*Iid7`i5D
z$MuKruS7vb{`Vve6x_cr39g661Bv<$THTUOw7+^Nao&nyKazY+H8DMsFE&G=S2E>G
zsK1gd`x0IZNq(gDth2P3w)ZYl9X(cE@y=?v<|dUzL&04-o6hO(mad4w==VsyHqiIa
zQ|d!cw7t@2$AIRAKn{pEUT^>nyf=atJU-I-xiH}?WvI66u(ZqtB1fbH<!A*-Z-v1`
zu(bR(utTJqy=f|?%bh^Nq-M0336~0%kUWNe@&}X%X(tsdM@r8iMq!dhNk?plH__4o
zN*l&VXHyn1S^9eoWKs}LMJrYM_Ehwx;rawxx^xlcs57MVC?K6F-JJxxC#C+O@Hbm}
zinduf(ic>$n=9Q+$)Z!z!4}xflm0soGm|fE@&H(Ybm>oEnhK>GHv#6nR5t*FWzvXr
zXp~F$HA1FB8sr92DYaS&QYD>0i;HUM&L)Ulkp8_2pW#L6&52O2ktQ?%?XvXxNSLUV
zhEY-173r;qVAe^s`DoQk#Vn{dNQZw0e;cJ7Wlfq)(&6iYeM_2Q1JWh691FDD(w(%(
zz9UV@!C>x6Ur<%YJ*lGt*bk)Z=0d+)dfFe752ZWfAo56hFci!l>4*!E?3Mb^+Z=|Z
z&vt?7Ec@0Oj=IR4D17QF%k~1an{4?u^tsDSnIA)cw+zRLaYe`$QJIjZ%%L0Ddu5xZ
zqva)2T!x~zZ1M*H-6zv;M$1Q5N_*U3*)t9>A+j%N;SehO1S?8um~8cIw2sO)et}lF
zESbX0$7FLTT^S(@-wO|;WY=>69W5JadWFv^Mt1X0n2(i3ehs_FWhs<#i<7nA!91Uk
z)%rj&UbcubNM~ez^Px~8n@Aa%Dj8n{?{CPa+y%2mmQM%4UdnFK!zs?JmMRy|nq{s5
zSgF}AUofwk-K+$&#Vpqg>UYgn+S2#0$E=f5u+PjKPXcYgObnsXoAVc-;bs0UWvmaF
zJ0`+>xcRPsA(CcZLInc(=5|!HaMpaW4$N!j6X}plkNN5#VD6FYm!a=~{3b0BBIR-!
zyhxRMP;~sH{Ja2>a{0qI=)JTR^2%{g^j3VP1lL#5v=uEsg-F-BzhVk)SpyZ~J8*cv
z;_ONE9aQL61MQGvWIx;vR`@tUGDOiul_sHz!Y+s$RkZGhhvABab}$&FIOB^}wBn^6
zdNGQv`#|CpGZa+8o1j>-4xP!0LE1B>DK>b);S9x*#lX%~Ox%jTEX9~ZFp;g;N>u|n
zigb!r=PIVsSG-d3&;U}c_^k$$a7hs*M_;XCN*YYmDSn|vXM@6Mf)`DSCb|V*Q*5J)
zv`rCx4<aU4i@J~Cu)D?cQZzj*9<700PYdC9IOA(!+5%C3izCS(2P|&95B)<HDGxCv
zK^8wn!(gbziiflu#E;nJh~JA>QPyWk8x`LzeUr`?e;+><fB$fR0!_;nzJTuX8oK?i
z@c!=v-O7Hdb6Ayh7$#Qxt%TVh-xz{NKdpETzt=pn#qYJVseE<a=2VRI=SQ@4U7tb;
zKBHs@M!Vx<I=jBJ&kqQWo9LyiPKRa#^Y2DlZ2cQI4u9{$Vhf{9-GaYenAa&-=E{uT
zMp<h&X0r~OKFr8Ec<amDq}#tAllmT7{>-l-AVJLF`w$6cu6+aa5atnrt<n_6V1!rM
z%%>D+Kh4+`VNmCp>9h*I$b1}N_J7mz^;`HOoK3g_)5q9D#lVYT%_&V8$$o1(2xC!f
z*A;jg$8Mbi?g`fW9srZs>N?m=Veg+pE0rx&pzkDmYZzKtY%^upv)SELBAvqqQ)y=b
zyV3^=g={m`i=JldD5iFnwb%^vrECioN1bE0ltZ$Tz3l?CRqRr8Izd*$UZuzAWtKk;
z*K66kbOl~vyR9J8#9GWi>neNM53Oc)fa)h(St-@Dw6TBCs-vBq@h;SFvLF1n3T8V>
zVfPNZbU2{zvZ6nR{g9OxgW1R0P^{+(`zIynpRz%Ylt~(7&%F-2&fG@2vptqK(lOR2
zitJuWgW%^Cqo;f95c3tyjx%ebgNQCH?~IYSvTH^_*Ny!y1J>Nxw_`wdvx5rsd9Yn0
zU~Lbp+>ZJ1WcSlHdoR2Hzo#ralERnXtZ7Fh(Dt#C*)ZzER?`F0mzC0b+>f=fg-j6p
z>0@{s%(iEsFNBTFL*H@s<t<n`!H%r`zo53r(LQ*INcqC0j`ZdIe%Ups{{Swo`=(y-
zmmhM53oD}9fv|Ec1twORwo;;dHJ1mpANw7l@KfMh@Mz6e%0aCSuZH@%V#>w;TuPhL
zUz#cWxxQ&UAbu@(hSuh9X2RIE36zfBIg%cYj*IC%0Pai_ojTafG*Fqf2UGktjfn~Q
z6!!d?kSd4=Fh-LVJPKrz?V%CET&6<hQ07S+Tn=N>Ps4?9hS>yWB%>rVF^sngB#v3o
z3uXc{oYvmSOm6}#U1XZbhf7QWl~L3%Ru^IEGV}Z~?A9_HH=@<ZocaXn*O>s?Q?)Y{
z2WYi^myvVme8T8+p!l5ey9Sw;%mXUh8e$Ts0o#Suy#bhT*3ApdEOssSP5)gS;td1-
z$Yu7Aht4VH`Ubd_$CwWSFQ1vKM_&PxP33`wj8ckGon}si1E`28r9E~zW16Xk2NldO
z^ahkl#)&SDD&`d>wyK#i#Js?ix`13{PEh5@C1x%K1#U9l6rJi|zFL4*ClhxMDBX+&
z<#`@5(`k;MG0AkdA7H{Mvf;`mWWx(L_BUF~yR%=?84w?KkBN$Yec5G8VAqd*^DIP<
zu;&hg1hI=h#pDLF{q-PG>=LSPh-Oby{5pnpr<F}C`^A4DK6V7%9#h$FswT^2)h%%5
z6nixrmh#wNPeVPQm2ZVJrL03UnCIBpv@1N%?pR09-!k?(8LVLsQ#AZCyPgVcYuT`|
z7~vIm6fM86v!zw&yTN`Li@p}Nmaf!RcKi$UwXvnN6S~VTS%kiO>=FTe_t_!}4?SQX
zeFM_Xeo0%ehwPG35P8IQQ?jdv-S#(q|9jaJhvC#?c1s}?``8Rew4Si{siylWyU!7>
z^|K##z|m*y8yhjS0X8iPlFwQ1YP1H~L@Ek>!9H9KXI`??j-hWKSKSJQU@o4PSrOc+
z-!PUq&hlG0lg5ob1X9ZBR#OFI6X#4Zkq6v$x=px9Y&HWlOmc?yy(tp)WH?hKd4&Qa
zyddu3e{YDDoY)Su$C7PZK?Wu7rT^b8;F2_vw#Qec>&>BiLpqO^=dJjcY8d)WX-W`~
zZs8T%5V<Qg)xc)Abc%_#o4wL2J`nAfu3Z7ApG!?|pfx0&VFpom*_V@tVPN<X)?EVb
z_ujM_T^81e&J`!*fLXPI*401m&w|Xa$A80sH~NbBy?rZf6O6m5sCb8q0L-0UA3@8R
zv7;Ii7pB&kDoFP-XQ<rSi&;$(oj}I#PvGxo0!qLPVI14g3S|OTqA!~HlZ9dovr!4N
zNsJlA9g>;bl(J1>d?<#J&HVBR&g3wz^rXyX><&Wx6!Y~<sOK^3`k;`{lv50)fLWDA
zZ?Gt2HaJ1%G}HcyrkWXk4y2g5Osj%3%u7ltmoT3!2KHHI-KWqmWt?bfcaC{Xk-YOv
z(gui>F<u7%TFzK}3R1yj4+E)WHv9!gtC)A`BC2L0C~td#>7>lpMP}9+=$S4t`<lS5
zVP06Fd6{|D0B5c;DS?=}W@eD8bFMKX=*48$nFv}X-(ZqD;6)2FAqFB{%nz>t`!=Il
z1Ccw-oBN@DmpMVv!F$Yz-vND}F{4wq513ILTHQ<v-6T@kt{(xGWn#zEjU<PiN!1Cb
z*ohQg&u705fM^lhKzo!DHtR<W<{Ue$l}5<UK?n}d?pqXay~zG}8zQyr>a|d~%D$qU
z(@i$r9j-ZZ+y*(g_z?$b?-9yA+zt}P?m7k4qwFXEnQ%`{Jq_t&Y~4(lj$l3LkZ2@(
z#RGa#Y*QJ$i)P0%uo=U0c-rBv^L#F>9A{r!54||{Vht2dur_ofj%P<DK{A1LmP0a;
z6(~rN#HJ-eGMV+F<zNasg5Erx%3knA%aq0%jp$5gQ-|PNHoN$Hw2D|E95BV~;~xN8
z&Ne%tuY%2@1NN2dO-gQ8vA@p79M`dZDE5%nvkPhU-M}WMpw-A`mO!tS<z``^ZS3=C
zfVH!s6wJZo>;&mxXZ;O@P7^!)V|3nP>o!5Li)E|e)NR&#DO|k6X8s14yKEN4itn+%
zSOD!lyOeIy57_HtAlc2%qO)5MSuLGu=x42IdHal2#lznLb`lksK4;&dXv!e_&touO
zu;WW1`I0S|2J(tE{pycS4{n$P=4%gUKNg^V+yuIL`E&CrR(yn8u7yYtH`Ibw1gEFi
zP9(RFO1$E^b(F_U;Ix#l%HTFp<|UJRyAzW6oG%rh7I00pm?`D*s0QvF_W{*4o#%QE
zLh=&#qe%x^!$nYp>N5A>BAlw_0_aY9g-gDIzB=yN6!g_|{Q<Dsz^$UUK{Rr^>GNsg
zcK!pAtK9GN;7l_&aR>&laog{p?>hI+UXUA{ik53F+>2(Yw{kCX0M^DO(s#Xs8<$4;
zpH6NYZ7OeZ9z`(U#hv>E<Gss$MGK^R+^7Mx?sHqJA^CtSkAY%0cl!=V4_CPaq?g;Y
z3fPZ1w{S?l<QBWb3unm&s&93X6w|>*SIILHag*HNhCX-6g4ZFrTQWR}o<E+F`$|~a
zE1B~@OwB$?b{CxSk<?QquCGK#Ne4fPw-J{7B{hGd?}TIl)nsQ#%<`a+FUib<<XK5|
z97L)lo~dBolSDew=PMoTf)}1L?Q0O(C+q2kx~~ku5A364o39VU_b*sBIThRxS&kbl
zh02T+mJE|Ey$YX>%6{qs=rP#`JRFXc1<n97TIOa6&{)|YLtvhe&D#xTylkurpb4^U
z3Xvwt^li{fk}WC4uv26iwCPBdUA+#HChNr;BL4pa<-$)i|KAr6LiL9nGZ<dBLIKd_
z>%WKhD}JSu&nvU$LS|LseEj~Uiq220&!yPx2IC+2``1J&iQD?_M96Oopwf%&QM6Jp
z<{rlH9fl5A+PR)a_V=VA$h$Lwj^>`(c^=k$7*pYLni9rb2^c@-e^DU*Oj$d;4`3Pw
zap?px-t-&|X13BdJcRk1?nt4GX9rCabBPjMsZ4JHtYtIPT>)0WWY7w_gn9V~NIA2Y
z_Foqnw|6m3b&TCf_}I*hnvYgH^N#5zyt&83b%OhpVQC7S*(D#qU;sPjJD^3d-3a{u
z|LF=gfZ@-?I0H9;`C~LxgP1(3+Y4r*K7q?2%o0iwhcatEf=V<KI3AKQj0HV@l9<2f
zY;H0$BMu5F%t%@frkWThN>Ai4*XE&_%M32T1e{_vbbwjH?4^Y0S>`QDp;j?v^u(xU
zzSo0U&v;Xyt$~T20<;$9*F>~hnP#emYGXE1T|qmOLMea*HiF*ek;o3+rb~j|Krz~6
z*1a5(DXb}jHYTa;r}Q?cG&b5CB%Rg%jiFVtztOV3h0PuXgW+5drB{z}>(`<$f*W}e
zCL-~F2Vpmg8yJm=i{?hqVGevl--2E&r=ctPI5&MOMB=y#nvxS-$}TvA+v6y><|kQV
zdK;bok}}#e21ss+FcBy@X2d}EOR_1Fc|a1E2A>W}u2Q1zkR%I>2I*nRKU8~sMB);T
zR**zbRqw$P%{Q<cBKd#4T=`#A*A>6_yqO0AgJVGB^3f0z4M-VghFwdj%BX}@7L|Y^
z=%9!!aUiq?ihhJ5R%|NLTN{JcrJuSc#$}R<NFrk0{ZO|kYLKPzLx>nfh+xw1HU5%6
zAf3;=&$;K^v)wyy-aGf4`(CAtGRoEAa^Kxvb@My0dqB+|3G9#>AaA}$)xMz+_*9J@
zEX645)QbnfQ?F*rB~pXhQ2^F2RJ|KmpQsxJSl2uF%N^VM9Mq8@o_6^1D6q2*XWxYv
zR~>q%yodnr)0Lr6*iHZV1b#iF9rAA8OGn;^L*G-iOfyv|tF9@qhOhhQGv)r8=?8XW
zN+SJUhViHm<U<?Lt+HMb!{uTo_S|mFN!+OwpwHeVUz`*_Z5M=73ZtMj^=>bE=kJs?
zz6BYbXs4}`Zx~-#9S#T5FULY^**qV#vs=f&y6yB__+PMkD|m`s5rdX$OO#-UmGk-7
z&xK{;u|{-N@Ml*+T+6v!ZdLL#vY4}vd)GnHVg9WwF#U^rorBQ^K2D}un)t@eAfD&9
zodBA7z8$V(wf7tNdxyK<1lGZA4#2+Q6T>jjUVf+%a?eWn9UVH?P?#qKE2%8)Mabgb
zp9SA7&Tg2A8KLr-yF%PsagXIE<UZYg9_|G-1ALc!L~xK-?S=S{JYX|?T19!YKwLvt
zWSOdr?l(bG1&v(^Lu;w?Hdv}@^?oScM5Vq%fbJ(_2GHZQ<sSR#x4A^?YCyR`K2^~1
zB{{Z2<4rmzw@BWi9mx=Cp=&Z(+(}iT;QTLDO#+5h&_(#wMLVDGWgvrGJU^f*Kfs0W
z$v+a>pHj5U!LC!<`sMm#gL3dw=-#L_<YSPV6tmn1U!#nj^5P;r{GN=q9`Wo#XnM@A
z%AmKGk12u8C%o~`(A&p94g=`tTY^AbL!If*hkc?5Kj?Zg2SRNXrO7C_hKlPT{ukOU
zS5AUX+>nXEt#n2fOt(>&3|Ie74}J$r+o|b3Soe@72<G=vkr@*E$nrP1ewa*8Vd)5s
zkdg3lIwtQK^%T$#OHDNR7+Ox#<RZ+`CF+v<R4!A8GdOQjw+A?H(FXZccnj5J%KFD`
zdQ~p*?@*(BUjHt=ngqeGXuGU_w^Gs-n7>D@a=&;RZOX*ZzN3?}y7!238vq_tzYIcp
z$#Dzhp3q-MfY?um^1%6&Mi*gZ1Ju$6Y>hJJ*Knpx`T7;GY*T`fUqk*?@s_*QPAH>g
zn&7%J{xP)ORq{K*)2(>RHD0eWYBu_wDHUhIS+1G84bBLS%QPt6tEq_qR<GG1<GM?l
zQ=M?TO*3f+IQukT>7ne8+Gcsts?j#K1N%UGdjovhu6=DLhFkhi?F1XBThwVXYf`Hk
zW!ibGs+GC>ZR(Pzn3>(`Mp+QstBxKGuutui$&&-BVGraEs<*BJJF2=R!wb9meg*_S
zQ=2N`#WA&JBn0ZzuVwPOUTtZI!3Oo31;o$QOc#isELGQyfPACcI}C!S)J$2;Jflvl
zgTw_jQszJ}s*Wje=90Rz81ny7=hwct+RbdL#f;BdCYR<BUGgsbR-yv&$Ww8kM18Uj
zK1BP;KX6Puio4oaOE-GshF*Zw?B9L_)$yIBKVW7OO8PMN#GFYmn)JmaD4KJl0$$BM
z(~S1K$>m^8esmcs-u_X>_bGo`3e~Cp9q3)){}ME$^=M&c;i~(fq$kRyOGd&<a4vF}
z@Ag@2>3{|+3QP!Ly1YPH60r^KrM;2z`k&S71lDCO{%B`^R*mlEaq?Wsu~dVe>ncFW
z^O*@V`G?vtOYfYjg83B>AEIr$?+JR*$~d&&3kZaZt9ipTjAJd|69OF#9A`XZyI@*j
zNGCGl1Fky8@d24L(bLbve5X%NO-RHy+Rr?_FvA)VZb>s4Oh$w0XSCG(<%LVKa&4(%
zV1QdD6lLZ5nI)gWXfPYie#QW^pDDl?m|BpRx7?PRk(KLfFo+Ka_&8^S0nMMjV&Nbk
z5$v0jzG!Jyu9f}2EsNTxJmVK0@5EnN|Ig;rj`^(a6y;Z3+#KWbY#yFwbCTV=jq)GN
zm_FGz$!1+)^Iep_VtJ8oxYd?jkeBaUkmpmd)asLymzV2Xl(!<=mY=@J3Z7h_0;{dS
z2EL5KB`iL1dfL>e_~@zP;<F*6M1<YNxuU08!J)yS#i8PGz~N}`X&!R#W4Boemb5uj
zqmnEh<^bdKPm=xHHBO@w#2?<!=tapn)mgk*sPnX2t~>oZS?n6Ayd?HFD<kYWlk*IV
z_^47lO7xu9s-kC##?#*Vu5)Fdy(HJ=@>$_{-6>S?6B;-B!VulbDMC$9-GxINO|)kg
z>Xxq@6JQGQF@^Y>ygW=MgP+0Vfz#1!3^JJ+vv)nvk=`T3KO`W~X!Q#WG5IgbOb-qY
zwwi+cj3!gY;>AJ!*1&R|Yq@Ud5uIKMEA^895*+VI=*k#Yp^SzxhKeJj;f$de%jjjs
z5L7W5#TYJCj8JB~F5xSTIUs_d@r;d^Z~|l4-p$C9$=9nh@@DL?ga*cXB{VUHxQ7w0
z{UH(t;cuGaWZxL3Z+7C1!upmzmJf;}0Q9<(U5(Vg$$5dWM1fo^Y9uHV9Z~uRe5be?
z4Q!v75Th@mC|6M%qmSV&qB{oE#UeBo8r+A84YB$d3V%i1kuYk!FvNkYOq9fdt4>^y
zpk0ie4NxX>Bxo1M0myxVaE%A+7BN2_)JCyif_Cu?fLuI9Oak<|dx=^=zFu@Epm$J&
zCIYM%RRE;9DDEUaH|CQB^jEIp_eswcUXW<&C^2ph(DNc^4$#*pih7Bz7rMDX!#%}<
zxiFxaBn|*dyOJE`BVy(OZ4n>NgP~&4EkU~oO_rU(VnZ@Ii^XlA{EF~-8(^_0kzi0<
zkl-6JHbw8vcZ-M={cD)loD}^V$XgLxCpLpZPCcSNML&_^dPFB6#B{0PX#7sc{Kdlv
ey_<+i)$4h`m=7{vE6QcB%Tzr(CuYa!-TnuriBtdp

diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
index 86860ed81e1cce6971da195b98266169dbf453d5..3ff655798a8f7224c3fc47b7c33b6182528f7c52 100644
GIT binary patch
delta 127937
zcmY)W2V51$_XdpLy>095Rb$tf*n5ky_ZBs3G_fYe*o_)vOf+8Xh^QbapdyM20#XE}
z2}n^?1QA7wpopLp6)RSh_c`SEegE&@PqMRf<~+|iGk15&nOW-Mh8&I?;?{y$bEah_
z>)6SNvZj-#F*4^rc$p;o|Np0A)XL7HO!4j?g-qVTJ^-aEhVyI0%T#ie+Zu&Tkr2+y
z<oy~=rxH24GM$mBl&Vc1Ihmr!jg`qKHd;j`O17w*T&Chw73Vl4?Bv_5%&b%`Ua{sY
zDm<Zr{=g<MWH)t#zTk<AV)z$=Owq<Xj_!*+!nwAi7xWNi*O){Il<XJbqAauFo)f2h
zFUxAUmBeA+%dR)v>e<8>oGiQH-pp>lDavj%+}mZ=^Bzrk+wAk#c$v&LWyDk&eCCv=
zs~8za6;yxqI|BooluBG@tzc!0@?J~1Os>q^g!;-9H(EfaqhcJC{?qU7LHZM~aJc%E
zh@ew6^>F8{jjM~)5Vfk1fx=wQf#NmV2NcIWQh2)~=B-M`e$zY~Xc;s97As@FZQf8f
zCS)NmV+S@riUN+QPzy44a6^g2-0)S(*r5#>J@fRqTE-4<$e5X_T|^l>vN`!;XUcq$
z8QoCQM5gHGtB|o{<+&)5%v`5Ka@d>mw}X{&U8FOxA!8<PLZ*8|M%iGH>(!9q7*!6M
zrEfz<Vq%^m)4w63mnq7}s%6|j#bnS)O}JsA0z?_>Asf-4A!9r<c^NmlA){o*98$@+
zaSa)+!QNQzyM~;^eD$p;<0dy`^vqNpC*!6zWXw!W52cKoF45y)mnkmjq4%RA5C-jD
z8#o#BQ_~T+Z#2lGrD$nCL4&4mszQ^?WUf@H!<zcxg3P4S6P*6F!2ir)!xfKtVxzD8
z4ya`Bl_HhN-T#tl+J>lQRZ7E2<msOs|AS$x$5FA1!H~qtvXuS*r^}D?xG&lrsh3o;
zU}f+Bq`%7x+lt5z|1Y~juIVI4_WS>`%hkSvRkG9nuQ~P3MoL+z(n3#~+<mQ#|4uE+
zoRyTNe?9R(bJ&3gP)??u|7ZI52As=(I5oM=&+_<JvOB18+bjFfk12OwCa0gXy>i@t
z*+mVYj{h?TO!+Q_O#S~F8{S|{qXLv@)XLufUmCS??EjaB`~T52ah9RMa}{XtZ)GyK
z2A1!Mg&x>kMXUd@&_k1}=>A_rEL9sm$z*wohTm82zDCycj>ja8)j>)ziZB0D`m3P=
zF^X^hqgW|x_NlW{#!P1#e%p}^mcq%>+DE)>I`d7#J-D>=2sR)50=i8Y)BhT?xIw?>
zfBH?B5&!8gYiO5d4E+d>hG)R|yG|vm_#f_c1Fkh}>SiWFKA3LNx_bKUs{Ze%`%9*!
z*U7jAPwmnFA@4UJ|NbBH=z#x2>Z-axYYG*}-4`|R`2WYFbpK1A8MR3JkD^J)L>2lE
zfdz+5;UO1Q<~}pjGQ}5am35cLXG7x__SeX^(kOVXN;upIy@@1OsS}mFOu^|?)-D}9
z`Wm~9*gHodQz`}-8)%gOk@+(wRpYCNpxD*?pZxy{PU$TF<yG7CYdl2&0~xETc~6fp
z;|k`1M^jTD=Do)>Q&&gOTn0Tad8SlN8uA8-49%*Nm48&>`a+LkK~``_jqAk<bgHtf
zL{gaa6S{ucqxS-?%RZ3)@hZ|$eWKEZ*9qHk1C=iMndBQ!V2qF*x**~jkVMzY#dI||
z{0K08DP1pBlIY=Hx{n-4fWPt-xT=ClzQLL3?qcXr$&7L`@aY>W-PD&PZ9b7h;}Yrm
z^WX*pCyC+dSwhLsrYc#_=Ol4oK=(hNru*oj4gz1W60GuPf_d#G^D}eF>zS{~Ojtgt
z#(pNv@ykeZY8`2g89?pPDUDia(GFq=EF{gHS4rpDHzbh{q5HcTWHJ)Zl1f%pMf^S6
zQ)%NPN(Yktok-;W3n^tErh-Ym$$b7uqMKPuhQHas;(C26T?alT$=w#DS@kFByuV3K
zY{{U~-=c{pwF61c)=;T_1l{Map_WLDAY1ag#J}ZxQRYy|+WkVsCtH*1LOor__>!u+
zp&r>2i0*zDs>im8RD;GC0#vf1qa@!~MXpS{Mfzhg!l`6yc9C04E|I*xjC5MIq1I|P
zj;`UABssa9?w$2ubI5A05}?pZ9-XKnGrbzxV0tzw9q=WSUymZU8qXzg`<*1Yw3zDp
zb{k3BM3biFBr&*7A}3m&A&GJ%x%KxGl9(EvunmXl{z4aGsKL0bk~!8KYw+<D8BS<N
z_gU?UXs|#guQfF9h?R7oJC&|~JtNI_Yw5megQEv*L>HwaV_njzGNGAtKPrn{{Jo(X
ztv`}Z?vG^tgO;ppOdy^R#~xB09zn(Ch6nAl7x~pDo32T*<jSCi7wPdEy1(0uG_woo
zzS@IyHt!`fTMT6Q=wV{}ei4=CqGM9Ywue(Gf0};v^#jRd^M_=<zTxK^u5pl3^dush
z>PGj?=h9WvoRpRwpzC@KU8jVT&Y^fJ9rq>OH(N-g&l(=vUJZ2`I*$zh<w8!x&mm)t
z*O26Pb3%PUPYg#jR66W$!cHD7((~{0oHDJe={F0&G!u_i1(|%%j_#i`1jzV>h{|u0
zylFXU{#-@Zbq$6cRixwNAW8NeGIOOn)q4Ua!YWzX6+*2np_X%Tq0&2F5_4^Wnx6kK
z4b>)DMXDPy%b+KpjP1Njq}zf>e)~Dyr>lvg+uzjG5B89OrTKIp*wDSK%_3}_CuvTb
zN%!f`sI=cnGI`<~y2flHwmW~4{Hr#w;*d!%>7mHPlnd{riLM)FlD}?FbdB;LKo331
zk0+4%Q4POkLQgX9_LS<eVk0pG*ho@4og_LJGOza{$-84Dk?$t+HQ7|L);uu>pQTdA
zcPtezxkv_bC(?D;2vU08;KcA`GRZt3od>(<DwGiQ8lH5<9wfuHBHf2#BBzq&H1vk|
z3h3VbG-3O4blv}k%)iT^tFVbmmoKAsn&7xfnNz9s1Zck_)s<7oFTZU>`lcx<UA#g%
zUK>e=ttI)|K~#fL%c=ChQMz`!O3o$KlYBPj-Ei?C>2FFRlc}u;HT*BCUR(yrC$%Mg
zKdpmIRyKI#)SQ&&w503y!Bl*H1l6_GG=eF9CHc7a1RlAXNXKBVtde=or0d`p#Ix}L
z-OE-Js(31C{*yvj|8K~}*YD^)r59Dkb3HjaaG#o<fA?9`jN_V+$;dzH{<{XZ`eC|)
zdVfPiO`XU<<Ix13kU{rx$H|z>AB5`FlH{#UlYzOt={iLsoiTxQbsJ6B&`{DG-iz2g
zipl&;vz(s)*%OJV@);GpX?QP78-~<hF!RI1^^u&IJDZx+_X)xD9Y}v{IhmPvh)7?Z
zCW#nE`W>RFu3|iuei=uG&+H?4qdMYQSWZ^1)it=%7n}~6={Ev&UQK|ip9rvfFahRA
z5a7TTy8phKuBwKf!1-r#;_MY7iujRGd*+jKpX-S<YZjqQ%SqCHPXiAYyLbXdlYCk{
zT{|`=`QHsAi{r(=M6{|OIgyh<*GVp9U~LS^Z;q$?WxrGXwmK1b#|Dy*nMV{?783Q=
zhJMWjQ%1FHy^SQUedvCrR*CD>6&$XwuQIp}KSgeR?S`qkj0+QR9q-VwNa80^y#w}B
z4JNu1pu9U7C~BC7%xicK_Eg9rcPpglqw{TY;_(~8Mm{6bxIf6nf2-&|S3_5hA<eNC
zVt&Yz=EQ|mndxTIl-?14)lG*Q1qVt9Fz7KESk;?UKmJHQj+j7RuWm=4F8+ozzwn?I
z3aUUKDLdPnbVgz!s+RpakA8?>;>f`1h8f@B#?)G&=)}~rX3I(5x))(j+UTmmq(&`U
z@}S}Qm*c5c%l^Tn5w2hju9jsTB3O$=GMRLf+>&*t8tWRKgT^O_I%X!->|F>Mj&-MI
zm!YesMAc~9uc&+5Em&-++P7GWRvi}iH}0o~`JtlIs$QY=hhit(Pj}Sq1a!u<si67s
zQX}~GlZ+n4`L?CFU-)$uN>^S9f~mj!X^QD++zgT}jC?3Wu8h|uBnOz@G~e)ILZ8A(
zZ)U|s<b0TqYmgjdCRPG=h}ri8jQTR^Phj;3qwRqo!H;n}PA~dVCUhu_9b=TYq3X{Z
zoC{x%GaqQIIKgCa5T0ZlEVu)haI7FzflL?;d#9M0<G>cgyy*h&V5Y@z0795=*P+6v
znbD6x9m>3-UOS9ga2}lDjQ%`?5sbMRa%Y$kiPZj)On@`+QOs8Y3ePfocZ2&J!##lA
zXr`F~!WgEMdgxdtW)Ilnn9M-r;u%va%%5jUj{}~-v<iYSk-1I%YZ9~E2hLnzu6+PY
zGV>L6L@CVkQ_xIhiVwql8q+pZhW;mqIY)MHGJp4h-CN9%nRqgDnXR7SzRd(C0+Gio
zKach*WS&j~_Z_Av4frC)kNUM@rdtOjrA+E$7%XElbYOYNMDGBgg6TzrNhLF_2io@u
zbJZWXr%cg%2%j<AszK&>&eXm`onA2FZ;-xZ7QI9AifLI2yRVtVIF!{gx?vE$VVX|{
z;w@A46uEcI$2M^E1C#y?20t>RU!$UR%+ffN)iW90VSbZ*0ZpSe%S+wi;VyaBX94!{
zU)!Il6Y05e6!pI=oT$(JT^R*SE9Z`Z*;S9}kzJiN2#YdOZ^eHNjV}MJL<PG(K8S0#
zqTY~quWSlqJ?_%8dz8t;N~b|xscMbds&BW3B8#vXB4P4iNccG_#3G2WrJe?@ua}QO
z`>VGwH|jvJm05v4UhT}ZI*)4YWcp#wrgmYbYoWi3iD-$J^9VERC$RZ3M~k8ImPsEB
zw>~k=E`V&CJZ}y(UE~jj!}tC2?lc+lk*_(7oS!^@HyR*ZK6U|c7vy%ln5t{?E3dKa
z#P}mq>69x_(D?i1&}zALGU&S8-46MHwhT0<%<m5WmY?|@S63!m0T%+8{tKX+z+C?a
zmAuZZjY1FdnsM^_za|i7{0Kt*Tnq#14)PrIH63d)Jg7VQZa`<!x!@lJ?z$jSDN{ST
ze(Hy+b+bP}zti25Lp$}jco$Ch3_OU&?WLRwKYF_-!;e1kLHITMj!43_pU@1N-`uC!
z%P{L^l#X5H1;@Vkp+REyqgK#abayCtR*h_n(sjQXA>YItcR}TxnRY9|?ZJHUPQd%;
z#jK)t+n;HK@Fd>Y5*DP<Of2HB>R6`1`#7e-{dlIq|MN^k1rnHs8YD90wK|n)s7M+^
zHEH;jg=5smTM};J+UNxN@<qD<c-`_sG(7$C`+w1%UpcxoMMHLKi(s*;n|vRTJ?0*!
z3f@=@X9n!egk+F@2|OA;;3xP#CXm)h-))tHZc5F+2+q(CXiLumWz#twao_rfo-op`
zdL6F4x^;r_LE3c4$DE+0=agmi);TdJX)3*m8RggqqRq_4*~oe`0kt6aVft)?YX_Oz
zG_LzI?f(JCaV8TnAasYDZo`W(W<KG<ne^wd8^NrTpc2cxdjNPG(;^s}@l4a9uzHb+
zTnoS@COZn6>CB=)R3(>*rZ@REBfClcZyvLzBk+%yG*=)h7*DE9CF84w>Ko=lD)4Wa
z9j##S9dmaJgxlrWUqEw*{K$J4be7*WLwG<w647pzmpsb@WZrTq2i^zBZ~K8PP`-Bs
z%1+5UPXjJme(W!(#K_D4p!I*Od`28hq|3Xt0^+iK?0Xbu%hM?UlP@3L62iN35BkmS
z$)^(jfxOunH0~pLuh+;umUq{px!%ZMu0ma$6g!uJY@6by0D!Av{tjsFRs>)WRe399
z1>p2ixU_`k3B{DZX#I0iad<QkXB07)U@1~@b|FYp6fedCpQ`v96ZeLnxJB#X0JU!O
z7}++bJEGoSCj5zUnTm(j?nQpsAUD_=-Yg#Xqg181E-aA!-?P|w>2%b;-P3s>?P$u!
zwafdjaP96$Yzcy1Q54MR8-Zb8)xX1HNCu94i1r?$8wZDn&szr7@kunHnL5e|@>vPA
zHv3h0h0<kXhT{5r_6snq-jIhnoL3K?gc>ENXF0=YqPovG6kSyBr;25$dm!Yfx~Wdz
z3|ob2#@l0FTeCw^kIK38xr0!4R@*lLn&-94YGKM<-|c(kJoWp}{@=qM#>{vMPl}k%
zx4?UsX+&Em_n4D3V3jf&Gdz31$PeKGD`UPqiNsT$mJUbu%lig{&`bV~rbgcKiWnpZ
z<)c3<@GBgWXEz6%uUvS8<cK`(0%(rP2mXNEF?mWHRFBKwk3daN$bELf%X9L8FeK6P
ztF)lbk<a&l7dPcK=`fKiAMqTx+w$sM;PU11v_>zGr}u~Oj(ipc42tBB=!v{5cj*bC
z<DOiR2i5!XR}`cwl^dQSS0+Ec2&Cn5SBn2VlAnKr%2db=gCMMuyDkB+T0ZarXr9Pl
zbOYe2{4alSJ1I77MA;@qlOiNr6rt2WTNQnNfcM)KWl!PE4u$Rr44qPBi4X=k6ocr;
zxv7{CjqEMOIu<my74COoFi)}PG=v3;?`XwXsQ76foGDWLLaXOu#rLz2+*7Pr0C<Ta
z>l%^=imtQJ2xW>sfyg~nT<-wfBSmRE$SM_Ua*(T1Y^Q<tvEnKXJWmvkIb^;@k+>h(
zXNqa>q549x-2|GKioPA8`dVRV4`Hq1kQ;Ju6{BlWwRegbTA+SVJSzn5qhcr3_mg6Z
z1kKNi$26R6QZ9={eK#vtEQ4^HvNeTFw<~>V3hS&)%|$(TD%U!epccE7t4_h7t5TvK
zYmagy4a<9#zZL-Kt{mk9)qTpebujO#?5Kt2e&yhAQRbzb-W7?rvW#K~hm`dZP&ur0
zra;^g<-~k=;isHTbvdRyUyL$;rEm^Dom83-;a3GH>!L9Vt4=AK{|VoMl%uu-5u$AT
zEfA-b&w3#jrhL>4Y~jjZDe7@X88r~VNM++e5S~@~=i(7Kr_|j7AXeGpXE+n5e9#$W
z=auV20Z&lQX$6%e<$7}ag7WWBR4_#uj=8=nRjEy<UhtwakA)YPls|uo<gzmS257D*
z&!j*#L;1o2zpp88s*q$UhYf(rb>))?u-#Aw4g^h(@|FjjxuyJxLZP`zc@Aorr(D_>
zEcwdaCIAYR>phX&Q64`6VX<;(DU!QN-)$V;zY^uvI#lhxax^U(%ajAKlc*|J{<;at
zBju4!uvDS!SqKwVO13S8)yftHNS-PuwTGn|rO)qZlIP0L5?Ed+L)L@)l``u+ynn5H
zQ;f1VO4r>0yj4zH1+w?bqeGziLD@SCoQ^u>SBueJpOjulq2r|bi&hewRDCJ{+@cya
z9W+~2J(|O{?W$Fi(3U$?eJ!xNQ&p=3&P6ql2aT(0ff|~-RU3bViM^`j1u)^JVy6SQ
zPn9qlLJ!r|7^oajT^<PwUaH0qV9&>)YD5$4gQ^)r!F^ce-4d$4s=9r^`>8gkqJfX9
z+<HRAU$y%m0FSGpsew<bR7ThhP^}L~E=ZL=3YLOZfwaUtt!jP(nxQH+t*XOS8)y|9
zp>h@>j8Yw_0QFhbP8uDfRgM<7U^hn9wHS8eR2e6Lk5`SSRdIr9bq;hARom7Ae?cW4
z06tmu1I@PbReyLQSD;!+E07}9zXO0PR(*U4XYQ%Gk40IDssjZlN>#BZ0e_&<(cVD0
zswo4vAF3)TMpU6HcC>&um8ybtc<Q7+l!RoHx}-mZThxyh!l$k3k(1%fc6EFoAa<y?
z&IQd*^}m;4$wj?<Jh*qO$5E(jkGh<KP44Q_MG)>&>(XFpzxpZ%zybAP3e|b5yWK`R
z`KaflK;@8n2=4&RVf9<AcU3pkBfmv1NBzePsOGAN(46MBdi7NJl&{YD28aT6@9oIl
zQ9q@rdXc(iXK3D4H|l`gJ+*5;_<LWSp+v4!ZK5DfnR<~P)aB}{fvD0WwPr9lE7a+~
zAXlXh3X|jgt5%O+4&W1Y>uFGZsy1AOrRVCwa&W&;_lW?_YxTXW0M@E+ghTV4y7o7C
z@m_u7G0N)HqZgxwpWq?j_3E!FFyzGMy?}|$?ELE}+rrL9z(N&<O?)Kb?3h=uaE5I&
zgva|A$=2@&+gUa;3JrXYt^69KG3;dubi}ehv9KG@mi!5t^Q@yOgo&)2c9W9WEt64}
z%yP8(k-`q7scITKZwgc{vJ)u!oz8B_hww7{h=P+>+1AHkH-q)24mFdl>Vz^!7Q34Q
zF4=4(1?q3GIRVhQ$u^-?{w>x)4<e2?P*<48CT;?E0o$n>xk9!;j^DS4{ihb*7qcAA
z<nFPV=TQ3+cGV2HR?2z~gWU)0;>R%fkhN|{?h$Ja0ZSFTJ_qn>2Rn;4)Ud7`18EJr
zA6t*A7wpO;c=3{*Ok-;;+xiZGZ`d8fpz@yGx*32EY&C^lKd~+8_5aK+9|A9&xH<hG
z+{BgcL~aY0UI|CHa@$YAneE)h^GJ4ZliC8XlWU#@LoS@76V=I;YfB-E-JD-ClD*tH
zXQ;YyL)QbpkLw=>ga<c18OeUG#}@c>fSVEvpHjKhZ&B?uE^Z)_bWU0g;brb3g=aH3
zGldSXam!L+DT}kwyLp|Pu7<rET=^6TbGX5d5n#K;Wi7{Vkjo`{f+nBq;|yQ{_XExQ
z?{Fn^AS~hn_QL!<?#fXBOSlWPjrM@k(!8;Z>qguUxpp{~p?bvqu?6r-E*z_9RTbw!
zlaI&TwQ|(u2`8gCL=DGMbnh7#)YSo<7o6XBNM3Sp%TV~5`?4DD*K*TFLHLfFPP>xt
zIptCq{K(Z)aIlWc`x<QZT;?()PW*<+(A>=beHpned>uWO+xTCp@wf9wuOV^fCmlg0
zcJc#P!I@qB_b*|=m6w;Xc>nhBBiw=C%dejWRd;?5Er9p&=X^l3pTF+};Q{_m8ti)W
zT`02d!^hFG<1il|12$j&nh%6W`B(W+ImXYviQI91k^^-)!Pn4CHGuCyJz5~&bsx%t
z_}?BN7t9ZCE8zV*&2ObyS}5<!AqnSG%HdlC-;LgbD1IC5w4UYL%m8;ZUss7Fh7VeR
z%H;75>Qf4NBXtdTcvA}C#r%^HBzO5qQ((7*e{vjT_xS>f(3bIDoq#Ln@129&kNB*$
zz&R@T#0em+;(aoKsOCQmfb=Q<xifTX_<zEXd%?FuC{^{6FT4o+YhFX!6t#RJtuWs5
z?P(+O9Y1~~s`iohB=dFroF8HLGe0jHob`MW1;956V_ZSDS!kUJ>a9W(9m=*jgyz&~
z?+|oJ&~X;-`2*-8_!dHSmvG}Hbao3}|AopPVO}|eZi03NEV&DZ9Vqh<E{_4uQwW;@
z+yNm%4;3%r--7@|3Oy%77$r2N?&_S-?=qSzTIftMzF6VACGa9na1^eB!{>#b3<?v3
zoEs=i60#@|eL)ya^Vbxiem^Xw3coKx?xIkr2jG&>cL+2u3m4;1c13vc6h37Lc@$>3
zCcK@3+;yP`E$gy{o5KOPDFiM?*)8GEbO>(?6<Vm|2_qbxVW~j)+KS(xP}n{bCW-`$
z9;(HHR0f?A;c^q??h6;UqZSW@J+xFU6MEBL;zJ>yrZSI&o|Q-{g<f+ZtP%>gfaS3u
zoQ3d-a1zmLRgLhG_Dr4$u9HCaLg*TRvX{agFM3K}3!9(7QmxQ*0+M&aQfDOZg~K=>
zrurxhc?{AzA(AEtpM}}?0H_zrj1X=TJJ6=&W^tDR-X9cS4n)}@F^HZ7Uvbo8s2mZ4
zF2k9lVog7IaZHR2gZbm)OPXSy5Mwtgf5h7%c9A0+C_ajXPLTLTOXPyZ(a!)pEk2~B
zQ>d784VJ=1J1x#4#5uH%jTC3`uoNX4Xi<1hywn#e(V}ll*o_rEJ<jwrJ0cIE))&Ns
zol%r5E~Ir^s`!$2D$+#G1G#kZpD;AVWpVIf<gSXYlVBi2{F{NFnPS*4$YqJm4<nZ?
zE}==v4RI|EBR9qKPr-Rh>^K!Z+!pul20TyvOf%C0@fw2rszPzO;|l<b#K1*p$zpNS
zGgRfCm`gF^67gdsfTiM>MR50l=r$YN<>D<Lxb{%Yq>cUx@c=zemEt8U;MHO~+ERTi
zHVQ@ZNo)}avTf3rzarTuSw^AFJftNq@X1qJ)f?vbO9M;DjRVr4SCD#19rq&fmXfak
z;Uldw!r&okD{ZkImLd)C!dIGm5I!A|?$e^zPqG|Da#R}A4Y*^H{Y&KhrTYo6bW*zd
z7JvXrGQ-0lsl6}Af~9feAk38ZzJyAa)O;3$-u1e4f}Z$n$wuAk4XIHNBso&Zdn7ld
zRsSHlCAAw5M6Ptn3jA&9LKKobX~a4t`O>!(mAo%a;E*eoE<Z%=%cXyVkyJ{n6>zOe
zilS}lYU$#7B#))d6tjIIb-AiU@A_2gze)`o_^-t{+D2&QS^`Y#Tes1|ZDu4u^5xbn
zRHE&=Ur_h2=C*?T>u$7z-)_M!@U=f54{Qf-99mL!yiJR#PP1vRzjH(h{OWQAn>MPh
z)9P{U_UkY(biYqq2|XH<6FnWj4g###u0a6wUT^_5=#x|h1AT4oko2=H0Npp25JFY;
zA6y5`Z=+~yWWaY61|4M0z;$pHJ&8kRoq*0zBgN^56@CrF!)MT8g>hK}A)j#~1NRGk
zXoGQG$8_*-W=@YrvfIJ5vmrgmv^PP|kJ&g8lqZ-DOCbzmBIq{^W4dLsfa5<GcJCgj
z?PAlZ-*jbHX2A4r_9V?8_OQoju-nT9yQ0jE^{4QNI~zek+I{R1ntph&&pqIQCp(j3
zg8SK#f72ev0rt2Rs$T5ACrG^6S$oh(huA9`kRE0=T_N;iwb95OWv@|$@fiD>8o{3p
zq;>mAwx0Tt0QSMZa4nD>5sb1^Y~DDO1+hD5Zz`A_Fb`gYusi3&?rGNP3vh<A8CYmI
zFy|dldmQ0xSK9Z9V27<j;Tg6sh4>;_D+N}g*kuZsI15cA=h%>)Xq{+wFwHGu*pycg
z#<CGKAjPrwDYzETdai;q=h<VPa65th$^||pvcD#vEQt+!gX98RaSlR9Dr=*LN@Lyi
z@bn_PGy{c~*foP8OlL0)f{DxQnuBoW3hPt@yH{CPUjVPMC;GrdCcCXOk}P&YDq8(I
z>)ZkGY&N72xEn050ZR@$s6SM0viWrM<u>a@oO$eMiaqB$ScMDH0yg+ts1~vdaP(Gn
zhi%jfszq#jir^HpekzdOWdq6lJ+=wal(2I*ph@qu!QJ3YDf_MkSRSzLcB8C}%`5>+
zIjdifvWM)CwB7!Q&1(U>73?Zn^;EJ&JCRhejwUf6t!B5;67De@M2-K1z1ACrPuXA_
zay9I)B{2VtJ>`kyIotRGNMEo$C`|v7Ju?7aykc`raP&2sPj#tfXQja48`g=Ay}f0J
zw1Ub9_O}N}KC%IcDErJF@q%VO8|ruhQYY@!6G%64f795tjVs3?P|U+ux+8JsI@hDj
zh5LR1@VmIqbY#hu`*0LxySZ7kX}O0RN=>qt8+!veH}3ea;B@DbcObWqn@OXi2UmI@
za8FK7Ptbl$OOf;9F7Bq$)tl=^zWH#ilHt@bZpSZ3{5c<Y*gejDOVh0r+$3xrs7`V|
z)Ex$JH6nh|KrZSvR8DbAG++thifA7(n7i5z!VvDK)9~pumrhfgQ0^QZgbL%P(fNmP
z&a8kif~yXsGd^cHp3WFWaxt+0MsXrF=~*snF-XsGKhn}7nhPsLTgGs?6w!#~o~u!{
zIPSzTI2zB{UqJIb=R`A&1TLu;;ECKknh7Rx<^Ysk;HFVTF`4TXid+iUn);zsZtz2T
z|I#?mtth<6o&6e4rE~pyfb=qVav<2QaL#|g{8g^&IoQqMQmOyE#{Hg)w<?pX>HxMZ
z?lO%R*EtvRFq>O98^Rl0H!LKudbvFumTqzdw2^#^`|&<ha=CY-!Fik8*b0dwkLyD{
zMLws>1a|=!R0?1r$F4?lhg(jE`ii(qlR;X{S?FQ8%lXmT`W|Q62uDk}N(;>2=YHJ}
z?ouv47Az0AQ52*p<8D%XqntCXf#yR_rGe%nZZyqsD!3wwzEwK77&}y}xZhIYO*Qv0
z5|$owU$;Wx6Rs_-6rOS;Z^CX3=SMC3jQim!@Xt91O-EjE<H7)V$^G;bgs-^jWVrU4
zoB0bgYq{U3huF-|pkowXe8fM{JjjQ<LX{5jKD0e{n0MqpK<dj+rhe`SpCbY9#}_q>
z>-?@EC_BdYS^y9I`LAdT>^OguM#K~ReOlg~<O}B_3E=N9L=wm^n+NzQek8q(L45bW
zkp%N@^rnaK8|W-h82^VWl5l=0?N&zcjT|%+J;Q(e89I^toYwF=iZ8OF+GqI%dtmS!
ze{CFSqWM_bB#Pm^=-rOxn^NpCj_*z#MLfT^3Lc*4zoRE1f!|4!n?&AsF?>qm|D{t1
z7x=JTz?1p)J&~mF8)%B3%5$e^{*%UU7>eW~Ul0#xF7X3stWM|m*Mj>pf1RfBSNI|4
z0KCel;^4R{gHMTo$~FEB^|qP3dN6QVe0T^nuk%ysq(e4ebP0~$;0J_&C5OM!7gf5+
z-<SqRZ}F@C23amYD2~Rz+k6FWQs(h}DYTZ)FX{-=0)B53s21{P7QoUSzWGAX6!BN-
zuw^m-#tn74%YQ``y~n50%%g;_O@rore)(ABO8G^b;8Qt&a}vlN^24dyc*JK?(6NHQ
zIs~{%{^uxq|El<A<DpZ{zX=8KF@KhJ=$`QZ-bL;yAKx67YIsLG0H5(4=+xSCzS9Q)
zUhqjtsMAZn*B=nR;<wTXpx699+QzEoSsGK{@ZU~^@GU>12{_;JA9^A8o}a2i8-C!w
zH^K|YM}EQ2D6Hdu>W4P@#CN_7{Ad0PoV~%iaLWvscM_hrgz6?C@(@Tj3*QAnxJ776
zOZ2V6{Qc0}CcM}U((OXtB(UrdI{HJ?SuoN`<(-1+1T<ZQR<t(WC3K~uSgu0ge3b2W
z2>z}xxJNh@55!(!ybthh!gbnna2K|o0dSwtW*k&KgrQMTIUo$34@+Lcz_lpz7E&qV
z>m!s!A~`7R8V+X;2|2`hSkUTV&{x>uisXp!kOn?Kp@v%fsL;C;;Ku|<+oj0*3qeO<
z;<)gy9W*C|k+hCDDaiYy+5y7D{;(S;T%wcBr-aPW$OQ>89`G<&=tR@{5MfR`xP4k!
zgYP#~p@NRqxM4#1j}V3nU(%_z2*Dd)4yn!vE$IAMq;M+~jz$T;IB1%4R>&_z_M9+h
zIC9a#>A}Fq2yqm!juk>^u@@&Op2Nd<VaGxU&kOeNK$;-5I1XW=FfbUxB*AeWniqt>
zt5B9K{6q`i6yd;ZaHb0TX?d3>yg2|bE(+Tz{Cr8sSnq(PbRjPoPF)s;zD06Hki6l{
zRl)TXav8!#8%$giWUFD~y72A*%CdzO6nwuSJfDMh$`Sm|g7l_P-V2(ygy9xg$`$6)
zKFDpMFC9S669QadFkjF~5EckeJ^)ZCcn+Z5jXT2BToe`wDOyO2g?6+QyemXftmvMQ
z7X*BXu=+V_abLJUA1b9nsSC;;2xF>IRwlf{hgqs}Ve)DS9||ANLi3UE?K7}c2yf}!
zPo=;{LZwP*(+p+R!gz|vKNbRU?8t%jH@g;fdMYrqRa_%<orl~r;lf-b&xJG`o4{(k
z@jlSJ6pp+F{*`d712kU?^;!sPh2ylF{6;v{1Loff&({F(PVgb`-wO<N!5@S<GXeN0
zSTCZiPWbdIgr5YSHYpsRh4?Y3eZA0j7z&-lYBI4&Z0CZ8+AJpEn-kR*u@iN=TgBUv
zP}wH-qOkdP@v}ed?hrF5O6n{+rvb22%%S};S8@D&0CtNN<B{7VG8VA7iydipwNG3$
z4t71n;`1Oo;1I9<1|2Ukm?8__qH!*yheQ`TYJ6DqJP3rZIP5PZN5y=a#2*s}?0`Xk
zG3!?}&`ELhHRJ-sj}!|C6r&~B4HkLoQbNRS;Sin{d(b>ER7|EoTbOvR4AkLb%T0hs
zhz?aWyg4H#Qy42!l+S^uQKIfBRL_b{kAvo%_!aG{M2qbyx)UQNbb>Rn;*yg9#EES~
zk;IE`mr!<I{O1KMC5UcxPAO5G9*JC%c<CYBz96PNf=aTOHv#RNBHpq>B~_g0(Po6%
z@rt&D(#0jGVD++izAIYdiuisvG_Hy{^npNzxP$_8*F>M*AjuS~sUOc03v<AAT^w=>
zPG^gc@PP<|4^3CYqg$eO1ai6J;NeJai_e#XI#2Ap6Nd7|?cKprAik$P<3h2!gN{nx
z5xd+0ut>aWg-)?}j8;Q;Mb9nJxhHO=t<e(k%3avKFTSDYuT-2^1;7I_l=dXc#0j()
zS}ykL3fx0+eP3`s5>37!s}OZ6I9e%=q@#FMV*OzNs>Qvu!hI~(aJ0kuMD#lh(x+lc
z45T%pj~9T?#DTPscrO079Eca<P@4L`6#Z%Rd?kK1!r*K1ZwhtRirzG<dLs@T5BOVg
z>sFM#6N}oy!}sE`l>mGYlW98iQS5UEnss8pK9qeDxo{eTKa1-cqoL}>O|;MBB$;x6
z-z4>=4T#N>@dL`XNtTZgZkOgig^3-KFa1o;(i=L^zf%e*grhFf#jfDqCAAm^oU0T~
z=dE^2F|-8VBehdQWv}#GBRJzGb*Gbj?$V!s%FqYwlipGo%0o*30SHg&Go23FFU_TO
z{{hKR4ZB`a?tUcRQZ{`d;Uk&;1<gU}!%zqhNl6mmho!-^h3qSxpyRVgq+fmlnV&R-
zMv9|SwgB_Tq(eQ>hW^sk`A|77b)<=e<AgL~D0EIrOX>JQfVB2Em=BazzeMhov~&@Y
zAZg@xuoNs+)}!_zQc)oQr==aV{}(C^Tn(Bqsed3;!lhlKAdHY^YQS<vGHigQNJ&l8
z+$iZ91@O;GXDOH(Be^v}F4iHvqaB(!Y5q%)#!Jcc^~ZVX(LK~DL8@8{nnWoPUzDnn
zB%CY4%OurN{3BWVl}^p3NI4W-N|j=0+a*n!x(8(!rSPsWaY@QN0YJJ`+6~ENX;LQu
zu1E)CP<B;%O|z*C$uWhFfnAdvnV`v(t`m2blsXlv*QHam^PMftrA^-(lA2~2Inn?P
zT)QdVo{!{~w407*<x1aESAAO=^$D7J($@(n%a@#Kyep8@{a~<ATJi@}?nuGu;4G5L
zMkBc=t#|mt?-FTU2~_V(L35ClNudj1zFg9_M%hE@9Q9<CQbaI>RTB1g@d8P6XfS&!
zty>L)HPW^?;GRix+7Ejvm5+zPS5ia-G+#?EsTZh~zM)>~jifOl_g4BN5FUPz0$(_w
z`cZoR6KLwBXC~-;k}?@s`YdgriC4X}PYExaG-~RjH)&cXA-7p`=P=r7i)LUD>~7VJ
zYX<l>&9;pIY}c%&$-)lJ7kxnHtXX&)t+rERqSGZVnz?ULwoCJ5D_C4LbyqmNf4en*
zP=I=mrpFh+@73&_1U5H~>Nq@g*JS0v#6HdR`#^YTR(FPqr{<5jNcL-5Yy<9qX8!LW
z_0sG-iJZ4)dru@jntj!%{XtDrXTT3>OhHgNteM*giLYk;2?&p9E`CirEPk36_)brC
zRC9{fsmD+Y0R1(!8zDTdxlIxA6B-R|I-S%+bp&^S<_N{(12t)MD(;k~MHw6o()>Ut
zAA>d1PNKdcn%DiIa#|BcKSikKPIr`rX*ddNhHFOTgELZd@E*z>QJOu}>7LaX=wMfj
zW)y8|#A>o>^o!HHrd~5%Gk{i)=QTgZKr=y8coE!*nvpF~mZWi`J%S6GW+m`2S(CB`
zq$!$&PXMH9oWFvlG))~%$S-P^lfg@x<XzBA*9;5+?y^IZ-xKK-&5<A^S2dFofXL81
zqhRzkjr|jVnVR3efTb*r7mbtGHS;JMn62@c3bq@X10i6`(adWDpKfaU)2XFfn#Kc=
z<Z60{qU^Tj>A%p-(}XzTN6XjrKLM5k&0cECB8}tyVsIC07SVHcS2N)>4BpdRP(oOu
zS^pzc?`xE)NXj(7P-jrC(Ore5r<$NNu+?bZtwB3I(_Fj);d9Lgio?CoG@%ICOU>?N
zaK6&G(>avantRWoQmg6u2yOUA)9XuA;;m+~<9E36PUCC>@V#aWg<U>qHvNIzM~&tp
z%IY-P%aMH2*!m**tSO|3e7&YyEzCP<(*pq5r1f-yrOn#q*fLjb(e9wt!B*`&n!Ik)
z{zS2q?b=}zk?hdwTv0P;?R6ZTSMAi!Ev6k#7j4;UNL{rvT7YJ^c2PHw?$HM3f@ZIF
z)^AX8(>l=$@2<T!2xa@UXK9zqL#vz*XFRnxzJqJ~wZBos;ea-h&Z&B7Pj!PqZ|&b5
zz~ZB=Ukc$t?J@em<dC*aW3U|7?oL(U{qxn1p~?Oct&#<)pH?*sejn8a&=(%Zw4WK|
z{IzMcGkaWH-U#>;+R-$dJE^T23qXL@Z3x^B(*8CXq`}%2N01BArWeDf)7s20pc1OJ
zn*a#Yo}lhET<hhHT!c0QvmA%&jP_U@surm&Y6dT&wAncQjI(}CW$^o)c3%a&h}PO^
zP>j*0bO1h9TTUmu<Fwz+g){Nmc88EVuYIY2-2`n$5a5a0d>T`ew8a$qx}fbzr!AAU
z$rPeU(XQ$P*HX0%Z2>#dwCY4;FKQnhgHxBZefI#LuFa&a(aYKiMQFAw+RD$cdsVBW
zUpqs4qYD7nv<K)x&eYb?*qEhVLECxPwR%sGW^2tx0B&eEu<$8IyY4hJZ)$~gaP*e8
z(@+R=wVQW9c-x`9Ku1>cv{Ps&I$t|I9c%^K96EMzN4t7GyeQKCd<JaAT9LL2?`l)&
z9PmBuJvw4jqV3ln!u#433IUgDf2Sj(546+U!<jPelD}ZETzl^|au2n0Y3*B~-QTb|
zqAjpNSfzDb84N_VR$dF5$68++x1VU;C>rrpyOsi$HQKIpruv!IyB+Y)waFA7excn*
zE%Q=a{|UHS?R^@I-)O(2G3u?h`VPw8X$v;P?f2TxbeQ0SwgVk%`>35W8gAEVU-bs=
zlXj_NH%LEgC(T9e>$R&-A#u|6rDofrlhe0gTXpN{#LPBbMF#9{*Y&CgaEETlPS7~(
zV!e>tsr&s7a4x#3vrwm9x&RTHuDY1VVA-t;3Wmxaos}l6?z)+@hTNxPqXGBO{k4+b
zKTlm*5lrmYowA|Y2XrH8o7YR1N%KH&UGQXh;iKzJUrHa;?WB(NkS>d&Acu9O6qNAQ
zmHi8YM|4xGVbD)^XcKTpb?@m+?J?aRY72kek2F&~t{dP9Lnn0G>0vpkGd$z*{srh#
z+d?N$ciR`hQ@ShLz!s$2{Vi03btXFc7@}K54Rl(UG#qwAbt?}-B~0f@?G&z?{1%oX
zbkVLbaYh&N0gguMYP+B;O81>N{5`9?OugPYT~iUlXkBM_0Ah5T@OU^>vAPkSFdwIz
zHXWq#x<5w4xAXt`l%#7#=c6v@`o0HuvaS&=d{T6o^N>r`b)*Ginl85^JiMqIwjJD;
zbUOyXQo3%T878ji9?b^XRb5~^c#)w?q`vc-F1i}IOx>;^;2c@H2_vDJt(!Xn*&Dip
z&S-=jUHjGm-o%ptwp+Rpf5TF)ZXF%i$=9Vv!O;SpR~L9usJqe@!aKUWCIA%aMj!&G
zD%Rx>MswZOHEs>~JzWTG*p=uO)27&c-OAZ;v{Y9|TW1d(x~zC0%5;m$z*epctN`~z
z-I<Y4eWdG3<3WYaO3SfIozHq`R_QEsYOq?DO~2t|-NS0s>51-{74WCJkUL0fbk9~I
zd8V6L3BYsRRtl=W&?#TQr#Cuh8Ju~m>q)V)cRI&ck0E`p>qjm0LFe2QY#(*$|Dv!?
z*M`ncebQ+?QTAEan?9Yb*Xar1q(4munK$WwZH2PU`ut>+ZPE9q=Xk4rGR;VK=u7AW
z7H7Q@M=?}8^{;7u;-W91N$D=V<{dnA)$ef7lw!C3StX=<^mRWV*{eTDgYiE7*)ed&
zLw}w=gY?wva#5N6`g%Ep2lQ!=k$CCHv;(QPzK-@qee|*PQXbUzm;}y4`eS7Gu)cp4
z5?}ot`Y!RP{&zW8j_H*gg#P;dr|7e(<NDqe$ez%5Ifvw=-mJrK5TJKjjXDMD3n+eZ
zO25$$27~l>Du55xA9@2}h(7fdY7wS?jWb}XaJ^eLauNEcqoHy}Kb?YWk^1h`Yenfb
z*uzwv)z6?^mUH^I6X0*O{;4nRfyC&S_kd2UULFa*<Mf|5p)g+mEr;a1e$jn!C+J&_
zhEEstH)!83SwG?e8aPG2kVfcKJxd!pX?h<y%wN=pu7KT3dM*CYiYi@yCJbel^=)yO
zT$P~@m0<pwzHT?DGxZ-w(fF68zfcP4b^TeIOlRxUQ-QdlZ~HykB1iw%1emy~|Cd(e
zxAgZipqZ=BdIjNaebO<QD9~5V1fWpgF$XGl^rvWlvq)dx5%6OD6pGK@)j#<M$vyoL
z6#ylAi9Vsfuis27TSuvWk_L7k=qJ)wd1d<1^iAa>{dF3!EA;(S0j$*fTmYg<zo-Su
zs`dA29rjp%i}ppI=&c7}@TtCpx`rBkNDKU+&-5QYLik*-pAF6z`UfIdUg{?l!R=T2
z(gmP?t?xjytG5n)4+?v})4S3-?!CUlSXla?|0M!!AN6%|2<!AM(vbV4Z*7O&&-w*4
z1*+E%2u5zRp(qiSwipa_9AK-VxH-zU8FaM%+iu8nhj51>Z3hfG8<HNOY^R}BXCy9$
zWSYtBGB`d{pw!jicOBB*hMySZ+zgAq0jay8G!*XdGYq4j*~8#LXAC?IUyp~~{f0N+
z18~4Fmp0wK43QB~@ivS}0^G;Yi=Nzrh9|yYIb;}+3zZ{=2>P7O&oH$XxTA(I-y%6?
zxa=rFp}*nref+S;4J}TgflnAjT6vu`9H#kLfFX(wBLo_b(9XmuL*x@QSCAo?!rG?|
zGCI&0YGCg|7-sOM(Iwol!wuXKhHtJx<&0s!H!MUN9@6o(D8sXj@ae39p|h4ThKD;S
z1{-T=)e+J-gZ6vS#2dEW1OB|>?+geN46|<`muT4e1l&o6ZZzY(VAw|Ic9IR9=Oalm
zbWuPh)v&8!)osWb0hV;bqzojN4U=h6cf~NGGYnoeZ1@*RhM})B%B~p}_M#YUrlC<Y
z_?Bf@JO&1@8*0Bmow5yyy&=3|SU~4mZW%1e$mJURX@mc^A*=#Tl4nS2j$FQ>>`Qo2
zV2GdxsnF1$f--ju78j5e8D7(rpxDrUJOFnMU$}zhp5dbj7D^4*buzqv4-8XjPp`}{
zjn-l1h6;B89~ySi`R_-DMS37A3_nrVUum$?Ii4y*&Ibse7+#J?lRPyP)3U0@Fn}g$
z&kSe2g35D)w*$EshQ_17^3t$gLaV(pyx9%FYeO?ysMZ>Owxi7P#_)3re0yv7g=+Z0
zFoYuK9}U)D(WG^T@tXnsWGG*Uvd@OgqrhEnD5f1RCu0r0K%0z3l@M+=UZWp&i!q%(
zirH%P#)rkKZN~OAciCxNI|FbR<2(-LcNxnlI_+v)MUT~PhjHq1;P)5}R8e>1=9#d&
z&$xoZ#2&^4Uqi>!Xsm%3`;8l^XFFhQ5(uG}(a;NQ-o`_}K-0(Q-vRK0#zoU$_mJ^e
z7FzVMu{FIozD6(F_&Q?rrOv?57)Wu*qs9<A3V6)uIDQwT{>EsUxE?n?r_JdT#$nfy
zJ85i5f%^bsG|d$Qjl~H_P8o;MnWP}&{&e7ijmI-V8e&vXH2$<PN(W)6aSv^bgc+C6
zx<1?(L1&I5j4Ox1wKGONh1esFt7*WDGM;qI0sgG9ElnBE8Cz?Bk2Y=}2t<r=Vkznr
zYg8djpo%lbd%*8_<Au$r_IYEkB}fvCYt&FlG;XK0R+4dJdyri)wxY#ZveAcjG*XN|
zPKTvbW7Pntq#2jd4%<az3N4Z@8P|w(1|Z!SI04+3jWfC;cg6V6@8G^_Y|;Yw4CDMi
zfw*RDbO~jdM*Mjvyeh_kqp0t7qx)FUWE-nC!o&^Z1llyoF-i>qD&taGB;7J5PDWX-
zF}xPZZR5NG7|JtN`T&=2yl18pt_8+CUjPe@kIq8pj`09>LPf@zv^8FAl+n0-*LZ@)
z?R&;`Z=h0QTzd$)`$kJPoGCT-90`>N#xAr8UuIl40xIRk${KJ!G-iH{vPZ@d1gJ2o
z>7Yrqv1BSV9~-^!DGK&LjQt+Ksi#IW9q6wymN!P>Go$~vNS+&A=!nP*V-*FVUK+P`
zLY-b24MwoNHtsnB6SYRCco=+RtfuCEYb-ekpWYeI1R(d`*lHGVAB^|*fb63&V-$YL
zI^*eMQ2Asu)6Rn9v+?yO;OmXgDbng>dLiM*+hkfv;j+ypANq1(iz%K(*;do98v)#A
z8cNf_?WUB^aAt?8A4M0PO*wbq{Z7+w)HAu5DhdJLW$HZ)Ubvc`xj=KbsbV5>drbP3
zfbTVJcmYi}hpC=g-QBdjH$2^EnoEBR!^5<;GlZU|Hs3*KzbPvTUK}u8B2q8YHR|5I
zO@S0`^D)V2Rd>*&r=#VEOtW}+c-T~T0&ri`u60m3V(Lt@Ge6T}S|%Jdb)bIcnCUbf
z9r8ChbneI=H?^eto-kdcS=LEY$Z|LwVCr`Sxj@s<QOKP#J)nSXkZD&xB*CW6^yyrP
zsX7ZLPMbEKLoU=5)*Y^enObcIS-5HX2b4va(x`pUm<p!A(MZ!3+G~w6IsbvSIBN=Y
z(4Xx&XS&i7Nwmo~3-}mQf)7l@n%o*87iZdY5G@;Tig^nBdDG7qz@1<!7D1C}`d1HJ
zlIa$Gnt8!Aw-C5w)07kd(oCz$0Jv!CO6T-0nR?NA@pRK!S}9&O=?B5JE2it?9LQcZ
z^`et18Ky=&xUZR#*1>M3X&%K^vrG%tgZsLvOH+_$oBm8e?uKbb9`HG)IQoF$rfGs5
zHN0iIbQ<tnlM6jww@sZXoS$ckZ;o8P>D)x96qxkgpi*e^TZP;mQ}<8wopF&VmA(Zl
zHjNtzw!5acH16Ir`9FcfC8jCkk-KkF{{e%gri6*eJur==piG%bu!61J)R<x<4^0E<
ztA<CWFzSLUOlfVvS!tR&88xdi@i`!?HrYl3_t=z6htQswuHobZ&On;RdLdh5I`j;x
z&rGeu;l*>)fllClVcJjI*e^|a^bN}^)7vYcd2I^%6J@ogcz+~sOoO5zd~5oxJv85$
z7Pmz5-n5Oz-4CXHZJ_ee6s<*4XX+UM??0I;he74Dse+y^N4?3f4p}F2&+9O;$!t`>
zi_PZRI3Tu|Z+JpytNCLzfZNOkOQEveY~BTx9cDLLxH+4Z^aqf3nqPJSi;Fps4u$M8
zx6XxmSM%VGVA*XRND=fs=2m`S*=ue_M}XYSpF08I?lAvz4s83(W5+?q!~AkR*gVZE
zKA>>FdFnzW2h8*6kg1p1O7m@RbLS<{^fBMrj<!5({*(GZUvp|RlpQg9&=cfmF5QFN
zQS%V`p7)q}ZXksI=3y^DecYTzpG}`Im#l*qC(Vwv9Jm9_-NwO-K=XErK%6qWd;z;b
z=I(0%3^u1Fqb$TcfOck1n@7<~Gt@kY0!?A&Bk{<En-4sIN`yIy#^f{Ruc_LR<_(Kr
zBFfyS7d$*`PN0eIIrG=y07RR2P^-n5^BvSQvF47>NaD<&J3uwweBFq`^X6;#Gn=Xe
za}PC=MDtr(H6)q8pnmRxxgBk4C!0$tLYrb<@fns<%>ykkk!C(gum45!BRW`o$($R4
zvUKy1ZgB0g`K%p)E9N(T_<gRL|EQ(;XNLKs8-Ul$Itr&`nxA|F^I7H|v^#s<+;c8y
zvd#WWKy$<VLnx9Q^Gk}c+%$V^0PdFAbQ7AnW-BdEZksii(fE1h)>lxLZ~jn<T!9&<
z&hX-ywX|%#V~&{xXNt^QUgNJ3s*25{Xt8tGJU<59_sr)G!M76gcADAWH_LP|Uur(|
z2xSk<?=K=LGq(wVqvhra6pMOj)=h)vBlBA=a24h|NpP*wyfGVPRc1HZORqLp(Xoif
z=7^Wjd}7Xf1M^SKgF4Xqug2_O4b^96zXi~FZhk=P`xoXGw443XY+MG_H)bo%{N9?Y
z2Lk`jd~zQ&-<!|IqU?kDL=`kYnuqO!`8u=9w=nq0{JAZ1pUs|ha=YF<stbM*C(FRw
zsLLkHwx!5zwv_Gwi(`wWd=Ii)Ed{jj+h$os!I|xr4LgC~Vex(jXPhk?C!pFpE!Acu
zE*5P%{M}`VzJxMY%fbOLzuOWx7|!gmDDEP+*J65(oSWq+Ipc0QM!PoqEJJDD>tQLQ
zb0eOX5k4r}@3182!2AJA1id6)mK567_O^_g4og0kDc?i&pykGH<PKTBrl<R`MYMy>
z*OEn}+7XK*3Mzh<UInP=QOoQdC_83pO+AypC4%0O<CeEH0-Uh0)ODY<?4%<x0T!og
z&<wOV&d^_&J7xKX=F~x!9~;9`u;o1sIU$x-fzUZ^`SS<Rgj#B7Rv2aprf(C&EoJmm
zMp&+PL~_Q`ZyTJ6w7gZoZj?na5yG>UMKWlfvxHKJCff3WCNwdYsc9gKwJhxdl{m|4
z2c2V#w+xsGr_Ngn|AJ0}Wqv;(5-rSP;FBz66yd#Kc@YmpvgLhSxRzphvJz#fmNg*&
zq**d{A$QR-k3I#sWNAvnXSyZl2h`=VrG~y6ykhwx7@SuvrT+L0GAy5Iuj`t{w=KnA
zGA%a`1CeE!K;iZ4mY1}w%C_v9h?cowG0{{r$I^2!gf}e$#fxrPeq01$u4QE?RBl^N
z%TQKeadU&ELd!R4XoNeKr6T+-viz2ZvSQ0$J7NB=<>gNh-m}<fT~T83oIqbV-nTSe
z1YoJfnU1YJu(bLMK9yMlC?-^HnNFW;KC~3j$<Rj@j%LvnmRA>1R%z*!5AG_<seUM{
zwp^x@Pme7dcS7Zf<)?GNJ+(}k2C^CpLyOU8mh<%W<8w<vAOJ5cU!xHms+SfgT3Nrc
zbg73IuPqBFfTq^M(3yZY7HbsnZ!NV)Q1;GZs|WtQrQ;7^`(Rn;0!tq)lPDNlXYr$*
z{!f<O^jLqkxUB`Q-tzuF9CflDwjsC4I(0C9k<HfmbiQ<pb-oE^9b2u3=qScE>-R~p
zyWQGe1xq`u-KZAM*0B%4z0(>)pR%}EBWRyzmo<wvJY1~@Xw|*j+J6-^_gE(v!R}sb
z#s;XkSs%Ye;%@Dq3bK9HYTA1Cu#R2_6;G=-1tRua=kJH`fW!Kv1l(TMv2if(ZB3${
z&Bxk`*1HF-f8K-6A*+REoQJJ7ongt>>f0QoN2~?gVZzV)?j>?Zt=6-EAG7{U>o<Sv
zh*JO@w=Vtwl@r!ldZ|uYSG-0NU{!a9g+S}-&rmsKbv*QkQ$f~x8dQU=b+jf9u?`uI
z+-YkfeOMi8b*J62FzYR13%C0G0ziayG_CK?So_oY$4IL;eP<J8Z5<5ZS*u?&Xr8m?
zY(Pb$t-6;`iLn~yKp1b0o{8kVwIjvj6ReXRc_>V@en-*$B<oiak_*-%`qh%HztIdm
z#k!x?=c(4cU%-nrtIt>@7p*osytrgd?+$pn^%@0=E?YO|0(ZrFqXOPvwf^25xeRN*
z6I$k)^)DJeGp(8*kjt{hP5{ew>xftfRI{zhBWR2p)<2fQw;ZegS`^;24t@&mTh=-&
z%;#E<uR+;uYaOj(^Q>#Kfy=iZE(2SEbq#%5TxbpU0pN~xG_Avmti?M~R%}g4fNOWH
zzj(mHJ!^*+z?E2+(8q4~t$uUp{VTN&rB5RsSfl2_Zke@-07SX9BoN6%tN#Wx=_6|$
z&5$dsCuucVY0aS%$5mF{66C6_H)u8a*cwiuyC>GE9FnJ2r*HsjtX{Xk`OMmd_J^KZ
zH@<=wFRafi0C;I_(TLu^SJqCnIDBorcmt%h))%R8@r||fm#D>CYdNhC-dWr9gfs80
zy|2LF2kRR8lJuiBDhDR&th3GF{$$Oj7}#g)dk?78TmPnAA1B+tt5LSeR!=LK&9;v<
zFu%oi!;IWk+a4{-9NTO&Xo9ibmOK@R9k#AXu;gq@z6J9;ZFlIbu#4^f892Pl=HCj5
ztL@TE0C(Hu%aH7`o#+SLURxc7U)^j!6oT8`_US#!_SycSnVX000<B3sZ8<bh@3+O@
zhwy;y?K9-O9JY}iVZz(iqd)LIw)9w-IBZ+%i(2^FzNN4DkJx_i1caY$_G37D)V7Y^
z)MK_1iX`~kw$Q1t<F<D6-M|UkI@<j_Y1`WYNq|jFoqeFKMgiO@TZR*!#~>R^D}rF#
zY7O8aHb-e5Oq{lD;Lv)ZHr4M)!fgF$e>mJ0ejPLswzfvloU!$!@694@cd46=vN^fK
z-?O%)ZAi}9Hqm!q(Ke?%z+-G{Rj?FmTSaS@INNNRyTseRqow$H+ZfuzNwB@z3zbA$
zl7qHwl5BGrWG~oeeS%K1O|}?GimmM=SW2}uIt?$<Y$N^w@S^Q?3fL~$iYYFhZmZ}A
zyO(V@B2ae4R<{SatG0j@P|2`aDM)|KwulbgWZHxP2(xTI9D#?|ZH=~qI@=aHgVujH
zY??msBFA==J|w?sGtj=}EnA=FFp+DEpdG{8wi#JK<k|8&K_%a&qhL^hE%rPN7TUJc
z7m9amJ!k<{WNS1BCW>v|mjSqIQ-%S4&(_Kx=1XjP`cC4$?O_dkDz(K{(Km1pY|H34
zWSOmFI1uHwBh+m@v<=9FrAM~3pOIA9rd>f<rS0HYn5eSN)xboxEvN>#$F{K{Abn!H
zlMLKbo1+sf)z~6WqU@P%$0p>S+wvcvEne8J();t$wy+QUePx@5iM>Ph+BUBa&0T9-
zMjPmFY^`N5@z!>0C|rDJGfaow_qN%Cf%sr++zlo^+QMn~=CdtiHgfg0O6p3T?72;0
zVw1fOeZ;WY{%R;Z++tr#YyYkG8w!+dvyY-^*>?K^B{+B33ztLaaJKKDZKj>}Jqv+w
zv7fsNon7|lFJREszP1G1yX`6)RQA{xQ)FtdeRCg}aI+`OgNnP|<vVz>&;C_^)YrqF
zLNgLid!RRR`|Y7v;i?YUo6sjKUiK}tQQ~d?k>;&Fb~pNv<e<a8tQo3($bOHy*~9j;
zJV<@*i|I7m5&MKju<K_(SPa#p_S)e99<vXpMX<m9BdxlR+fN>Vr4#m9%aNS4|JxQS
z0rn;I=Y<08U(gcsl--+-ng!YC&>uSqw*N>^XNbKu^;)Ox4j&~7L+!I@trcd^KuAm#
zZg&>oQ-pmk9jHBH&sq&&r2RfEU!&}6wxFHP+FNvk7w7C1bV?)I-kdt27`xMKR5aEe
zwH9P?_GWc}$J_NokUMW5;f*B0K5aCTM7tB6#Y?iMIcO<y!S0}#VY2-LeFTwW*V2+L
z)!yeiTuigq&=TaLeLqdRFWFP*_;b3wX9Ub&wy&T~vMct)4q&-z?{^#KGwk<VA-raP
zSOQC#_7=xLmSx{X_5FW1y6(6vt1qsWwoJ>kc=z6WH5}Q}wx*V5J2Tr^nWa{~fFKC6
z5tS_<Lxv(tKm<jGfP#SRJ!HwAg23;4et(_Mx%Zs!Irs8D_qq3+b02Qmh(mx<YEzyH
zkusZ$Zj>FkZL@C)I?HXMXE0wCHrl_?S!omQGrLz|?e>O5z0E^qfNrq)FdTx7HpXqR
z*J2|)2Met>k4oWSn+^XT^tIbmQJAa4W>XXNI&DOC7|~suA8BFgvKe=SLbuJ+^oH!Q
z*|reodTl;v1lMO1w+nvWv$^y$xPF`0sIG6o<~OSu`hzw_O~4+qDgPKU!#08RL9G#+
z2fF||YV!xhFUD+EU%|wT+jP>;V!|eXu6|6~6fTD|Q#Kp(;r)G^)@G1tn+wa)H)C^v
zPRkE$)_a4@+I)2!2Ip*a^!1B*o3-=~wq<;}m)0jc#-|j7wP&avffq*@BUDoD!04ZW
zq9fxB9kq@!oQg0sC&uT#aLt*q>pS!vV|-2}0WJ(%s*iPLB-8%yIO8<s&)gUea#(U_
zY^7Q!55_!I26!??_k(yb-l4i|Z$|JL%8&XmmOTtKU&bs|qnu#mehki!F}o2kCmB9>
z0eXtDk_EKWjHG>V&7WbRi;w|~r$2z*Kt}l?hy*dt&~Yf3@oOTmLl|c%!5_+Sp9FV?
z(fbSf!WbKVgZXeqK`SgoFv=}-N98OdDF~pEi~*VpeA2lDXwi%fv?9eYBKLxvW89%?
zy;w%}FOZC5bnOOqJmc~kAPEd_DvLVLcw#%ezrfJOz(gX$<qI@kWc)b=%p}GqyWnp!
zqsSF=n8JvqGi)lupR(`PG=}*OIxjK4z6my+G2M*L42Fnm@G==k`q6lqv6XIoW-$`e
z0D6Vt(F04_j0aShaE)<@3H4k?<PEreogsY>B6*A>Hz1PF*zXQ!3K+JO;x1&=>mhQ3
z@hC+qix}4nAX#i>JmLfwOBmKR%;il+1Z5v@F<cs<QOdZ#3J#Ys+9=L+n~_h+&vM4E
z#jsn!IQSSyCF6N|dhami9pGUV<8>#9R5PNofnCFRlj^r>8B#j(*D>Cu8q|8m?=JAS
zfzd@7=SGG#f_5uS41pOi&5Ynn5N%=jT>x4uW8=pdeH$Z^a!&0GPb!J)V3g6`y_2zg
z9^75VbClBWV)$<c>1JG@%Bdbka5>!WWxPr`*FHvX2gp6fS1UpK8NX#iWPtI8Be+3E
zpp{mnA;#bIt)gMZ^vAF?!q`6sXGR$h=nXl>D4&9d<BVXcv7BJ&Uqs&|Ltg~*Qw#@E
zzt8ZJ!{9XIrC><TFd76H;RA-B8iSZ+Y&V0OV_aDVgYyjiyJ)m!enAInJ7&?}RG)6o
z{9`w!`v~)WI#D|?J!ntr$h`YH$WdlkA2ghpHncHtW}dwZ_m45x(t+BAS+W^+U72sE
zL*zK~Hl?22m}ZI(yEB{10OrAbncfPX%$Hw;qh8FkHQ>CNm7hbzhxz@#_zv@8U*<zp
zG=GA5eL099b1oB;aFW?Tv6WLy4?4l0W){+G#GiR<H53DwQ9pnSWH!7F62yG_6Ep@h
zKb2xiLYQ3v;6j;h^d30FR8X8Jg863}{5{LGr!9OW^I#~rDCUnR=>HHzGe4!MMhx>1
z6TY2eK1_RnSY}No#uUfY|G&PExs*0{3Cy3|;Nf}ZTmL}h0@Ig1OOnXkPTBj5%-iH>
z60?rdEXhnGWf)SJCpv(V%KUB*8q=7+$>7W-=COK^bf%ipEY=Jrw+d*P%>TXw%w=XK
z#UHbnmX%Pv!sNdRlFh6a!NVNpY&E9jDsyut26~M-Mw6J!Y@{s2b>>lLj46-VPJzyR
zW(-9D3Yeqs!$cuddkx$TW)Hm~i<oN`f-7cb(5h8pWgeoZ@+Na(5k`26xi1nLrOcfa
zC@o`Nq;Fr{X4(#;ubdf7nX3wB%}SW4WWGb8;5#6&Tg5cqhF&%ECcP7Dm|s%ns+PHg
zqP=y@m={3mnV$Z@Y+!y_4bsTmNn6q;ru96fu9}&-_-8|lTbR#L7NV88m+oA(G2KRC
zx1Cwq2hzcmorI-M=E^OwdzV??2GYgMqMTqi^8w|?dzf!hja4r*ii&mnm?5WN;vVxZ
zZO;0c*>q?gV8&4a@E~)}0B(r+t@TmB3^PLy!Ko4E932KnnQ?SSbBr0P1{r5wdjfVR
zm`kZ1agym&356-9=zVbanVVbyGtG>1f!j08*C?v+fEjZHBD2g_-^L*3nCtCeexCWq
z5fEEeAI+~FYeN?7*|WNnY0W>v3fc*$j<PHsP;_GbPKPUJ)@=`H9AgDE0Mv!m^e50<
zSsN&}a-7w+7J6>1rvlOE&U$(R3LY%sixBZ-ZF(I3da*Q3=<{av&=J~)b)Js(zAVW}
zxP5|UqI8EJ>z!q^KR?L|r{C-;mYB{ur&*im(vv?+se&^BEb)6V7|6O!L8~CvNIFO`
ztLzL+gs^HU)*i|-u7koE)(6v22xCR=fI>K{xdU7T>nxRuoMk<A9}1ByM_N6iSiV_M
zh-U4<Hru*5hIN5T{?D=E>EIU2`g0FR94lxK{Ela3)44u@_2NHJJkR=xDr7FO+^=9T
ziL6%IlU`)~NeAjAR&5NNNoGkqA(_Gopnzp6YZXN!(^&6OH1QJaju|59tQ7i@X0Xid
zkhEs9zNK#*TxP8qL2DMv(hRgKtiWU_X0slrJ!uZh{yw;?tdPyHdyQqF<t~@CbQ*47
zXFWv+>O9ucIbi3rY-VApfaUouPzqU@R3dhRRl5!%MXZ=-VWF56PEU9V>-cX#xoKqy
zs1)HA>l&p*N?A`IgTXS^w{$?g&Du?+UgfM~lozUCl~dVwCF_R=;O?*_9|NX}_3t5w
zRI^U4Mqdppm9hb~tc4WGs$<R40j8d{QVgzvwV5JWjVuoZhTFutMt5MFSymRE1X@_l
zC16`w#f06)($hoI&e}j1{5n|f!+_~z6<vp7H*5DtXzXDr?Lc~2hX>Kv$J$7{hI_2%
z=>*ZwilBR=1FScwRBMp+$zq5Mv7Xz8=^kc%{57}{)?@+{Mp^CFa>$Ia#<s!5aaKY%
zT%2GH&|SPq){pdKn_^u)0rU4+ufB}FX;u|QXl7VN??B`MD;Zm;#j~s<Cm}M&dV_*i
z^DOZZfZ4KDcR}pf&)k7e_Uupx4Cx4a|EqA#fnB@=(2nf+S*njc%C4ruF(>xO$B=Pm
zf13w#jD7PB7<6HC=q2OIK6nIvA7_8~8qnO>OUt3)&Nk42+JoK9hKMISg>oof?7&92
z=FN_xNU{%mWhuaX*+M3qIl*2=+gCsKHx%SP$sVqu`&p;h%W2s<%@$F@&!0W!4c`LT
z`<>ugAUkav>;|zfeh%zlwk{E)4`Dw?=e|%jUSoLh*xj?}3uB+v!9+NF>?}wG`z0y#
z&ay3A!9}u{F9mcI`&U|EqS<%9fL;vyX&k7ni_ft)6~lZi+k;-CaqKQzV8^pd=?t8}
z&MpOao?ZAne7eAXn?i+&><n5{F0wBzg54x`!X!vCyMcl!DeQ7TSW0F8{S+*vu@j0Q
zd5OJ`>Jih~pOyh7gWW*;)=c(U3cFY@vpJNF%VK{=3E3;`M?Zu{Hv5<L=*(dsqIK>n
z`zqC~Tw^Qg->2lVi$6u<b@m7wuH~^O=|V|9TS^aC0sCYF8jIMX1~eA4XZ`?Y3450Z
z8gH`y<-+_ewuc?mOW89;;L5D*S^6^7ZFU50P|Dd~`$DmTz2yotD%l%5;Kd#Gqc6k5
zD)yKsOjNT?^ibEZ(;6|RTK3nptE^)eWuUK~{Z}v)8rVuY!#1*?qo<;Yt=I+&&Fsq*
zId5VAP6yjo_7xU})W){noB>)pJ9i5-I@nui^WVu1c^#d1+47&@Oc(oc8g@7P)=i-G
zu$L4<p_iR@6_)zg(aWH4k9~g?{OxDgP-Jz0oxcWsgY184eH>!*t^#G4{qRDN5%wpc
zKpAEKLwm$A_5thDKpSVj_!CS_uxqGHXp+s{4w)&o%i}=1&z@+7$Ta&d?XYLq{nLPX
zz<!=ed1l$Ku7}+@wrx4cJbQx?jkcU>2PoKaQp2EN&k2}<hetR?lofN}eBlPWjvO&1
zIF53b`ci$66X#>fSvhko9<Y0iQ?(hyg;SV}Mpur@VqhQVd}syd#(9!n?e3fv%h2e-
zIZrnlJvsA~Tl3;<um`9&C+RSV52u0R=)N451e1S)GaU%?ew^kksGsCKUJLFNXGtgB
z4>`>#?Z$lhbJo$WC4eJ#0a_sE#0<C~PBN7V1#=!;2TTYjX$wdwXPnA}&T!lo!crJ#
zdkh8<&iOI{9!7ASAH@Wn<*>ui7s;8~fxalt&s>mb4wH7)F&q{feQ}(3L+K05@tkic
z^_0Nrq|nTH&U+L^y})T(h>1$%lovttB8N}OwIt3^AM}$sKQ4l6DV&9_&`agK+=9WR
zaXzC@oL%C0($La5FV?`B3=Z=fh-7lw1Q^m~&LBl}vp4~(fO3V?L%S7gHs`;up_s!N
zqdm-3jzcrBuW{B<Wlk>Vf;+hDoPVm(m&f_yGjREweUyGL;KV-;M+-Su>B`Lw&R<=y
zRK#g-hh#D5&_0+b;RIcT!cES}ELgh5dEy2zOF3iTK(CDR1g%=Pt(<+EK+8GqchFkF
zDS8CXRB}3&gWTb)x(3B6PRHw*glf(oKfrDcr-Ke~wVc1`MPJ8ZQ0SnZGrAgF1Lv9%
zeT|&8Z$h$(6GGRLn>jh#Kw3CY(IVf<8KEqA8^?DkJZ$G!g?~Y#gOl<Z40duJc^?kn
z<-|l{6kQx=Iv8|ws%a0>!*Qh0YA>fd36}ae*$t4q$0>J)dOzpn19&*V`CbEVkkd?g
zyCKdw1Gr(1Iu^qo;jrI^!YJo^ip`91c76hpaSqc;YtjVgUCL2Ua-JxK%oNAC7v}GC
zUZ#s^(;N$BMrJsJ6ykiqSx@z`vz)ux7{wgtD1Fvuo>NEJ3tR5yDiAwv9c@_cxz%)M
z{|I;F1VkLT{~iVB$YruI?4w)@E%{E|koV~P=ge)X2ih_2Ns9craHVv8(3P7<F9LV&
z_BM>dgPTS-usykESHO62vlY<u<~~nbCm(Jjg~xokk2pZ#1oxp15I^qjZ-8==`x70x
zPI2A7!~joo6Qmf6Kle%q`U1G$@1gx?AUCc7E(US`oq|j-_g9L0hHwWW;8Q5~0tGeC
za8J-tJdFF=W^mzLmo#`0!Ck%q3TL_7C@vkzEueiy6gRK~ebHPo#ie7oo8AG~Iqq+C
z6p!V8`Yqg!<9^}>lz8rfUV8r}aP=$T@OiEv1sWH)p>#VYkt@pt=tZs@J%&l#v<T=Y
zbHnNLT`AmAAM~YiGv9;xH11=1fL`K;)<Gnldx<JyGq~&NImqO`N{yGf$9-WTi+i84
z7gxB6Z^KYF*Qpok)*No)duYAN{e?b}aE<$OGe|D?4+@f8=N5`!DUUm<g+@NNDh=~o
zzzw6SokDH^Eyy>x0e0}Ph#PSf3dP*8-@%n|YbZ{8le_6zG~VKdP*Saw`+6<(%D5}&
z^?RGU|0LAQt=yN6z|#t@j6yY)-0?>tbB9~*2$?GGI0xpdxj9=QQp1%~fUA}(>cDvG
zxW07nww`N43E2j&?l{mIxh<6FYvQs#1=q~&-GE`YaHZo=Z{<45;aVH_6rG{lxxyx>
zcW|x0tcQtC?m#SL?s5;BfZfH7bi~wjbDhax4>xlOM0&aLLWuNnopz$}9(T?bF#X(F
zx|=@4ojr%fVeYQ~zvH;y(aer=6Q=++#(kU$8pgSnP^eFE^&i0BNpAfrh)i+QtQ0Z5
z&-I`^<}~*Z?QLhcnVVto0r!PYkXi2S-(g~oyB(|U;(6{nuRz3>_c?|B?08G*14;J0
z-cXPuyaQ!Gap09ELeG)6i?&Bcd55T6$B7rW4|bh-Gn8gI#yi)9J{R5&DLsF#ynG6h
z9OqR~D#wlY1?_0uc@q?5_u#4MH|NRwgF<j#yfw7(^yVE{2}?e_&({IXm-o$KD4gJJ
zpoPYd7hC~LCwc2AS$m4-twrBy-jAm-UVq-PA?OA04$-3>$TR;)`OzTWVK!ufdE04E
z9m3mBOK>Ppgc$AOGrZexpf8N)Nn;A<9iZZ@2%d>5A<ptr=tUpN^P`<#6mM526ry<+
zidM()x^KYIbG$`6;bAOq6P<bDc&(J-i|2JvXf}cO3VsmQ#piizD2;G|H-8u!iM(r6
z%X5+EL1i;ZykCBTelpMRNqCXMJNy*vrt*^fp`XUPc@CB?@jiMVUZnHxY2if%Zw<xa
zGkMB=uymO>N13ZEUK9r+S9s5@L0>j6kdCxDJl|6ES+DZ$e-2C6cn7XSKbN;=7Y2Hr
zw<{3XdA#IPkjdw*q&n9Ep6zy!Lf+tqXuQFDWD;may#9^AF6KQ{i@p-xl2~vzc~AWc
z6SsIZ8laT&j=c*~&inQ+xLv_ZS`2%YypzW<q&rrgQv?*Ncwf_*wwhN>wfZ$YGYg`%
zye0-n9q&sztJU*zser11SC|jGjXe8qSZd-`P~5ed_x@gpwD6cO!~0gAL<Q_N-Z=%-
z+j&P<qpySa2<3`9d4r!p<Sx%C6?$Dft23q1yLox5fZfBpOxvVhp2-jM+{cUk4}JG|
zr)j6#&)ePzv;m$^0I&yn?*Bnyh_~(=crna7l?{;*-u0d68|AH91e7tJk=|zGJR^BO
z!F!qxGLyWvuK+#8Q&A!AeO{&YZ;W@Ew`?P@XLvU#jQW80n+zJWyca21G{@6ZTw$Jf
z;%A`Q@-rxiWyfD}9>kts@FCES@V8QW)`4G2*U}vMU0=bAqkPNLP;laxNYUra|7{;U
zJjP#j4qz_)XevT;<@;w)(C#=t>oQn3{=5Jh?tC@n*gW{JP${h^zt0iGiyyZKecpVB
zd?@(vm*#-;<uBWhNjSk*nBj~czrG&iB!7yY?Nj`NtI>Cw-{1^&fBwcNpclYjv=x1U
z{1J*C1@V8gr}$?uf8i$(4dILFyd28UYXNtLpPvA<F#cZ@iVo+0YlOiFet#WA&hoE*
zi@`+ln`mbq#gF@cIEBBPo~juBefs>wIlf&41`*4zYl5XXeuoqa@q8tXC4ql|s=m+j
zOA!LMF22B5(n&Ru-$-GnWWGZh^i%j>(Cx)kzKrhjr}2XaAaaTS@7L%{=l@DiTn2v^
zh2S#z94c<S%vU}SlEwGw2D!q2h6+Hk`4fpSpTj>(pRBsd@1OwhHGUN3)^ho)DWPh;
z&R<C1uF2!?djcl%`Q3EVEa1CQ9Ho%I;Tez{{GP+;E8^!-YNeRJ{%>HH@Kb8Q-Q+La
ziN0I>SNFrUQvTaKaAkbM({SxJ-;<7}<^0wOpj7bf1Q<&t|K5F&JN&{IV7|)A|0M_-
z)%^2&G5Q+5e?35J`5WowSjRs@v6*`Qlk_+>@DC+`H1f@~nQr0_zlwo2^Itmwv=)9P
z1u$CqvlP~E<9~k?nC<+eXW>%^e<}~8lmEeM(7VguN9WEie#kF??&e!>Ghw%fziJRN
zz5I0)cIxBLJdDnJ{M{5c>gO9@0onjRe+p!fe~_NWA^z=kAjAA0MgTg(uck=ND1VTC
z&SQK}IrPT)2S{OpKYtE=ll&b~Ff_%_N(S_O{@(9ErumDk{-87b5(<z#;1AQCq*;C@
z1<&UAvX?O4d45R|U~C0xbW77taHJGy_JUyAgdY+7xdM6)g3}a5brjUo#nq#Nvrl3y
zPJ-m?AkKnNss%VEC?5x=i{R}4UwDE@E%c5Hx*n$Zr<<T)1JK+B&2$p+5Zt7^ho>Oa
zA2MEoN9kzlEto6?@ew??2R``;HrRnXDOmC*Bu@#9{%AZc;FrOKzrc&KhyjAWSf~dI
z{-V8Ukf5H*bAtsN#TZ10;N)?TP{E#Fiocu@ys#K(VFFL8$O{+zNh?f*;CDKTpA|et
z>61voJ=*I<2@Djpixw>U57;q+EIKfr6HIi$?N~wGc91wh+Ba|}Ua;^>pd<+PMqm=o
z3#4?myC6uU4Qrwxj@HhLf+EznS{Ek?w!8(!WWkxGa6d)xk^?|f1tB}2ktXntM&l(x
z!D4Xfg4-fsX9%uO047uL%`EgT3ocMNGD~oPf}2+ae?0)n7JT~)^l}8R^#Sav;KMPH
zYl0U{a3)u<b~#+TE*PTFoi$IezYEy;0x_i%3Iw~T=BZGy={zjm5FDWJPmv(|GZ-uu
zSSb`%BG^H7sy798wDjK+Jm!YJQo(XcCzJ`+(C+NEpq^I5azXuGh*Ss;)8&my!6^#h
z-w}NF82YLN-4q$FwhF@NwO=EMqw4-z!TMy_trKis4iohPmL0Gg1j%#{yixEbol=?v
zz7(8n78Fthu|@E&BkZ;c!u|wl69_1^(k|FaW%(U~DSG@n1urUK@UGyk7W8!qWRy+l
z7JNYU={*8#0|zj@f{cIQTc2R}c3|HV{Ph)_=@&edi@pKDl?~7z6tGudFhhclREP`<
zHvEXj5y5VIz>EqGkHY+zAYu>3GA>A<t;m#MHSII*3kE7crUhPHG|mWqi-c<r1fDc&
zvx1MTc5rG=u!QpA^8#TNh^_FWYS^_CZV!Q?y>Rs@m^dOlK&!2Tur~#qqi`q;B1eT!
zwczjLBs??>pPYr4{{N^6b7|k|B7Ex&G`b37`9L`?T(%DCZo<F-D7Xs)KZl5i@K!R#
zUp$4zHhAGB+~W!Ny@m5sK;k2`x1i5gI8SfW6T<7yf%6m2UWLd>;e&L5o)TIL(05w+
zGwlrgg}+gFJV5x@9~eZSFzX!pf`q?Pty8e@7pm_G5x$%Qlu)5JeI4kG@L~zw&k7S3
zJp?vfD7OGKLRjDm?yNADmaRzP_Y^yb5)N&KezdTcK6e%)OuPfobHclY;9`Z#X`PA_
z_ED*1yzt`~3^YNw;{#YaFZ_)52^WMbXbDXezPJptc2W3!G%%Bd&!9NNx;R<*Mk^dn
z5uPYSYpU?--xy4q@W&O<za$Kz<5;@zunO22!p@)3mnm%61iP1oj0yB*3HuEoSA_46
zLLpl?Eyv{L2(#V>cU35Q7tq&)EoJa2SNQBa%wHD<yo0gi36D^jkTqWzL&2{CVdQ0i
z77C;3%ydJj+7D7BJQfF-V&UJ1p;#ikN86N}!j+UDy(Rpc{!FF9{gmh|6IP}H?Y3~s
z=Kw1genp?ss1TM@)VNakHEqQ12zj*-sS@triN0##2M6I(omKb<y}s*(ukVLwgYY{#
z_BIM{b)&OM*z_?-v+yap*xVxAN`q+?F5C`-ZNg7!xoa0b8x1cygso3Pq*Hj17Qef~
zHhS>7gw-^o-NMNPVD<?8zeQuO&_56geL_VFX7rxW`s+%-^b70Wg>M7GP`YnFDBQCL
z^E@ORI|P|wVbD|19}&*c`C?S~GOeLw!i_%Y8y7mxqi;gEwG}>13YXHseoDCIZA{mF
z;o8-}oEC;21m=t|hhn1-gsJhcH!Iw}5zfpB8?E#@oEJVx`D|N}r3ZHHL~9nK(_R!9
z540nqN2zexLG*_JFpi=MdW{|x9iS_tPNE?SemRRcIZ!wz+It=%E~2T2VaZkW`cgQ0
zT;xX?cQ?@<TD9CoElh}bh;A-`Jx|fXDat>1iJqlxj<-k|gHia18tH<tujr{yfqg>s
z_(AmfiBg||#!1mm+^JZ6O0=aCXs1PqbSuDLR7Ua70MVx>zy*p{E`Y%xQThwuf<@vD
zFc>1TDS}9-sA>$2XGDEN;KD?PQMw-zE?PiEIT0fMS=c=*8hagsi4=Y11(_((K`NDr
z7KMES#Td~u8uXnLDQVG+6_rrbDo(_w#X4T}H0?$cL@OFW&WrpjA#y?F`Y)VG6zOd-
z&Woa*<XV#GlN5|4S+wq7%KxQ^CIo0r75(=vyhsz(QVshh(OWOTQo874Dy6tAdU`i3
zWr;#4o^eIw`96Hg7OkXD$mNKH6)<>JWLpYyP4oh#+H*zChvDya(Vz7C%oF`|5McSD
zMEcDYh*k<g3Pp;KK&&@JmuS|DMBzf{7mIp}0a_w@dKDCJidYmJxg`pr=wPYH{T93^
z6MgpoPk4yd#K7NjQ5mXy7gva|Rl}nu%AAD49Z_f_3|5KWqII=e^vOo()rd0e;aaUI
zi!z&aq9;FwWW80CZI8|d(fMY;G>ST+(b*&#=0Lw$l;#1M7SXcTA<`<!pu~NfXx(Nw
z(=PgN0;EGUF#;2vqKD~xaaY8oLu{95oXSbMML*L<sz-E|R;^x96McoHPqc#S5bufJ
zO@oDgk@diD038th7zVq8qJ*0m_K@i09w-irdh1|fM0DQ`*rTF{XlWS}eL?ZWagl^#
zQ4^xC?gM60^as5prbL&XLf?H+u^+f;QC1=_XG9t*mVY2hSO~CL(e+tC&xw{$pmtuA
zXPv+ZZN=|XaMVs*Spf6)VkD{Y;E8+R1m_@jdjcLhioc2kIV%3;|C>v(jDlv);_!QD
zJSJXo4JKT~-_n%0ins5E-f^*sLJw}@=pGPv@hH8OJj5LO&a|gEg4RGUG5=S(pXDvy
zPyyCQ{M9PJ_=+XF0CPh8`Uy;%pV)2*Oq>+&qd4;^F?$gHo))(yqtRcS{xkFf#1(W)
zC0P7M9A-U4%nXHIsF=e+-x=|zPr+cAxN;JG;o|36(2Ecs-ib*#D|UQ@>dzv@^L~(t
z5|5|DM6@_=3p!)O2mghobK*w|z{QG>E{CIWV*V^hy!aE^)+LB-s66+)xT_O?iVNaf
zbpA^eZ+HzT7sb~o{*okqnF0~X;-GMl6me1w6jH_ZbXrdn*ObxocS&551K-lcml@E=
z5F13m&J<7f!O~^%H9F8_i65df{1x$9x~GvXzCgkD9B~QdHm-`-)2aKK*vA2ObH(pJ
zfckZ@cO3Nc#NW}Eu=2&>UjVE?eDQCH6pHyDq3?$HC;A;*i^MCQ2X?VIk8)-u;?23x
zxG9#Ci?_sTArwo+{BnSniRUOQcUzoHd7g6d#!~cEh&}D$Or`kKFpThyxR5eJRpQ1u
zSgICZ?}kW?SZcxmYsH5b0<%thiNc`u;-C_64Oa2*Oo%p$AERw(lX&OXz-|^lPp9q{
z@pgJAw~DWj!)@Yu`dzh)FHtP2L%jP#*zFW&QccfY@m^ZBy2P94pxZ5$)2X{h>_B<a
zUh%<qq0lE@ej9!F#Hm!<+%HbK0g(Z*^|LJ)+Mt+0`K2MT<1c6(7Qen9WJJ7S0W?O%
z`KfS!O#F!kCdS3f#UK-6Bh?X4ipz$eHzi&}KeqegvK}-}i{JVPKFx?@p9abUaa0A!
ztk^)QNn6RE6tb|BeDM}svzNSY^@RB&lEXD14wA$nh&oCp2OxS>^2_tE>m+GuhK93*
zMdy-Zk{XH$xk&zQgcq)oyEkF}xa4y>)4EA2{h;73sox2856L-fuNHescJG9qm!!!b
zlHQV8T8n%nsT6VamF&r&`ynSJ*HeM!C;4~-U`|Tx^-w$|`HkXarzL-VkD>WX{9cAe
zfTV9HoC%b?90!;nNfg~s3YK_KQZPiabPYxyD*2gC-De~_KY(PI<YET;!X+Iv-4T)n
zF9G_j#PJnKMoJpIDgGHHdG>X%(UOd47>tqZPsRw(Nj!dlPqC8L4D`iGMjK!$UQ$9S
zodijW7=t-4sS1Ln3liB@=p{<Nq8kzyC9iEoUy?-P3z97Hd=6fuNET4GH&wDV43cS*
zGxQd{BoS?<=PzBNJP4Q!N$4qPWJ-45hs<S3*lw85l9X!Ect!Ho517Pk$+8Q8$&nPr
zq3^0>-7;WblX%>LLayYANO0FBcX9!iCvkO$UcSVb0ZRoEM>=&EN<3}?<%Z;97`P(I
z{Wkz+Etb5=09uJe#l{G4O7cEK>n+I#SD;ubIiQ9{ndGxjn7A#`-hoKD<P8}_DkSex
zW~WjT@hs5pNaVDStCHyG2V5;lp#RKJBdK{93bhgz>f;yJNviSzRxhcMps_*nGrffy
zt&(m1aJWhG#wBz%OHTH~ZkxoP&a~~4J}M*akQ59-zf-b~jX%X*iH#Q|yCiOuG4GZf
zwL+msGEAk5y^_cRc+n?G$b-T?$qa3q`z60tqHjPlOMj6;$yY{*3`sorfF71u*S-hQ
z5y?|jx;!dLr=#(h#Hs=rmv}|O;DqEH#dIennRHf~lDtBZt^1PGbef!&Bvb=tMiO%t
zA`c|H7Qn=;WXT$MI49Xf_h#oMtLDMkO0~&Qu#@^b0NP&KOjRjIr2ba=io1i<!iJ2a
z^t=ulN2RVd0Ckf7!T{$i71QzLnDkp(wp^s`i{QSi)a5utj!RqU7N48+IPE&zrE|9-
z;vrR=K|H0n1&aqys-$q2w{*@6li(wL$pM(Y(%&;cPDoRPG$uc3`2m2Qls4an#wqD#
z+CrU{2GMfoFFj1@gaBzFoecw}ne-KkAnAuUVK7+wD4j1tq$_;T7%JT&f=_3pd+4H3
zn6!-c0^!mSn%D>_#|@HarT5=JW2AIl2z-i?UOGeHhl`d5(a|YJ`q*`tI48}eLabP+
zei3FUPWmlgQj6oI?yl%dkiKIJ{qxcV6z;kpT|{?W6Qz8Lt6!9^--<CMNfRhTnJoSK
zM>vxrWzqgVRl4IGFw>-CbQHKGRa3MpT{=HZ`G*Xt?I74psppGu@v`*GR&ZI;x8s0z
zMY@#YT-nk9N^j*zeP?0ms`T1gz+9J>pTe;7qz8Y6iF~O~4oHDiL^ZgDQWhm>Zb+Mp
zfmtMNe+?+b(zTQTFOl{$;o41UuPY2$Z%Lh~e4tbsErNcT)Ta(pb6fgBJxr8K@6qq7
zLYhgtyGrRwiq+qdvS)x@C2ju`q+0sZhY+ceelQJ@T511vfYnKhdjVE2eT1SS4N~*d
zaJx||<fE@ix{tDX&C>S6=xeb`m)F3XR_WjMz;2T+yp4gjOBHmy>5!&w0_l|cu7dtu
z>Duo>x}?WxSJ^G~D+lS3UakS@mG;ou*(W_u+oOBZ$9AEyUmCUz+<>$}57!2zc`*PR
zl3srt+_3a{dNq$otsZpoVN^Otuh=nZ=?S<vF8#3>XcN*CDHz41w3aqRQ&N5l$bD(!
z0VqsMb7<c?BTYXFg$L4iwXifRJ+U63bJE<Gz|BjaHA2KzwnhzTJK1n8ID1(eJ%2}J
zF&|-^4l=!!Lhp_;5uLh^%1p~aoMd%>;jiW_`+@FH9Fu+a9_+fvJOUu;DtnAh-N$8G
z%167&dR_yXyR7{)^m)jJvS8j*=2!yGOJ+|I1aH{@#m;<WueAfySEiy$nG>>ndK>!5
zP8QR`d{TDjI4qr#>FV$&IW4=I2~dC8H*^^zKsNCj^aEv2jY1?yhM*)KJlW(ikPz7n
zUHb@?xqS?u&d82jg8496Fs01GWxpRoU!+X;Cs3kfs|8SxmU&WAAx37XfZ21hMQn<{
z#LAR*kcpG2Xe$#hdk(><#R;;N6n;G~v-|>$3$h(iFp(%bL}&PmGUgQwElGB@7$jNt
zJ8f}OWZCqpOO<&!0VPegARc{}WaS6Zmo5vn1!jgUXD|9PWv|fUcUe}A^ptgRmh3pa
z39iTv(_SxIwv~b;IkL@*K(5NNe*(ECdt(@ixiX_a(5}nQUWXTXvVW-HJ74xQU6v`3
zeMiO7g|ZKhz|sxb7Cyj=WE=j2Ua>5ic3>s4?0hKPlr6jg?w0I(+D%$ZWmAWsQ6^JX
z1Ln5u82!=9WwoSHAzL2;u2S||6h!aH^u2JjO4dx_foj>CsTf6#>{TBOv{rU;IV{!5
zgnQ9fFMGca3Jo$bJt~c|4LqPU$zGz8lV(|TFJ`nwcDoM>tybAVsvK*R)z<>1UFPov
znGRX%Ug&qqKBVKqT^W}?JJTiWUI9nDWvjl#Kzn3!lw;_Xec1~WeX`NVfObzNq|eUu
z%YLA@|A1`ZLpU=iOS*!-Az8#4SQwTW=<3XfEI<G<Dzl0fKz~ejpc7<Vrg#EmLdKv+
zW>RL{iYb|rwR{P*`?7#LfSHz!`oOgrS#28hAIQ=vk3K6~7Y|EwvYxdd^RiQveX*54
zvI(4>{O4Jy+sjwbx_m_5u?oaNzVIawNBJ5nRqZ;<v+H5$n7onl;4bp-*l2W>U-<^)
zxcnoE&b!IQT5#_294dqHkjK!k+f)9j1SY)XDJc-~mah*5=Odq@I!a%8%R}(ug#330
zVEW15*b9G8%I!Wz-zoXhzoBqio}i`opTGRYEPw{cPyPlHC~xS-=!4|S2%rVaE1$qG
zDMY@#8RkRfFVbo9j67-rpkea+pF<&BKBNa1A-_o3?X&W24}cjdKPUr<lE>D7M9V)a
z0A`GQKUFE7lgH8_DOR5HD}5h4PJY)HPQ}Zs=~tE@-$Zq9=jHn<!CjDl{4Yk4C_hCD
z@<loRnH?TH`C+OMNS3b%z+WUq{zWoCQ{|sfT}PUHV-(ac$&;s{kS^c43S5Rf{8@0B
z^6?OWU6$w4CLl}xttb7Dz$@}s=&hJ7AE6h0j$AShnXB^u=*z;_<or13=gO1lw|-q-
zLt%+L`E@1+lP}j6p|3#hdLHHr<p!$lz9E0s7uZE|w{ehS`La(i&=R@pYv{Wv_u@n0
zmfS80>ZS6CK^U@@$rCCud$;8`!!S|h^5@sUM1?$&>JlsE6~oZKBi~Ff#VUEN5tgdu
ztMZ{(BR_it3bk_kMX*#S7tpPQdU*)tZX4v^&?~l4{^2HYP4YkK8yL;<O`n3a$XWEu
zZ<X(*EkT=A{>V<ubG!WKB(!$Ov%Ub=DgW&Z%-@x_Q4p$29`G>GdgWDLL8MQfc?u%;
z<XeMbw_o1d32s2XrWPWD@`yI*4ar|r0()2<L0hj8`L+Kr>{0o$!%!cSOWmP2F1MJ#
zO~|czbe~{S{?1a&(3Jf3hcPwx<)+mb_OyJ_7-VMT8I*>2Ab*{%NX*I`8Bmy$KSpQi
zdAYg^#8&Y##RcpXTPcBUuV__4;fUfN+7~$}exb$MQQ>?L&Ky;E(!R(^;bV(FXN9}<
zBY+-L6sLo@C?p(ox+?tsgZsx7I~QYUZi;2o=yO*r@4+ZM6bmU4?Wy3=VZ}@F^mkD3
zR_xjdFMJe&4Y1^^xDbK96AI^WsQW1lOQC*J@z@I>rxedUfWm3TQ&-@jzv4d^E8GZB
zY@}U(pdy?0ib0A~Rp5dZ1uugOQ4G!iEmYCC2iRv6ulm4?Fh$`c8p9QH6lI7|m?+qH
zR<VM%IgyI&|8Fi8>q@~zD;z1h5Tj^y26s;3Ko3W(;&FOX;}jbf(eoFtIIs#Z35sW^
zBICSb8Qp)lpm<>qWD*t8O~AgW7`O}bNs4f6suw3K{OH<8ilUb46jBu}yP=S#2w4a0
zONu_K&`DPueh3N~iV;diW-4|+2ZhUumV21IEQN_;&{q^%q<*c7vlWZzqE(LK6{<tI
zs@PA}_SY159pF>0qE-*=>xwOHK+98X^TH(ND-O`<s6g?92P6v>hv?gyHxx~Wz?CQ-
ztp#^ev5lUJTZ&lv>S3wkOR66$Qyg@Hh1-h1I1njUX#aqMwL)R%3z<sA`u|5R6&VzN
zsZz8&44G=hD@pLQMp4Xx!CJ-aIAH1&V<Bj)S3LA4Tx(DSj{>w&q5l9wYf^km-(+f5
z)GY;RQ5?Djy;cQt8^+S6IQS<p+Z9V}VWC6uVgd9zt%@bz!i~F%tyBThrP%l;u)7rw
zUqP`)ar{0MdlgrELHZQicR~N2B8*B$`V|dyG#yZUlL53rMd15TA5vV~2{NomreMK{
z;xJW?j4HBe)f!WD(q++c#i#V^no#UALvK=H)$D}KlwxfMu<t9B6l|YXtRk5iMV%XD
z9w=6a!<kt{kp$Rtif!95UGs`hz66@BGK7LUcFNU{K;2$>fDVjDlyel}bx=M>ZzV@%
z6m5ErDz{Nxg_F|pU%2h8EV&5iW6CG2^j>gLE?WjKT$T6flWfP8oI}ueQ}$6Mqq}m+
zLm(bX$qndxD$|d_l9%!})hT!@*U(ARM>$1<@m1aph2#mP<^)julm%HZe^MDuyUA0^
z=FdP*E0g2V=dVnm-Bo~+dx!E5fy#LLqH&ON3FQ%jmF`sB8KUF~(HE-xrxn~8Wg2}V
zK1}IFt7f?JaULv1DEIvia#mSPNz6!P2)&G>lq=RjAzEpq(tsG{I8DMi<-fl0Fjgt6
z2bZKYd=HYWeDNsNU#BPonqetj`NA;FXDEN9-+HEU$4>ywR^Fm;S&niA{Wq+u%J{=D
zQLJ1N4!bv%pMMFFTgnxb;Ve}~)33Ws$)mr|ZKaW}nUyOuzl1`Cl0`@9N@dFfaCemF
zD4<rYT(gbhFEz?cZ_H(_@_TwK)+y_3fmW}~zYDt!$}^=9ZBpiX!BVp_J`H1PQC^_p
zuvX=}wXoEte3P;Y9m<uov~()9*#Nt%G&lpSOX<UfLbuZAFw}dL<urM{%49nz+*2B8
zUAFcswG=!XP(FDQorB8UXVE&Obf(Peuu?z^+=!A-o9R*IVfrPFDP<HV9#`g4KyO01
z%@$~r$^bnaol>eOOLbqll{U)L$`@Y)_dwY|A;Vea3?=2~l=1D5oL4@54=A=))c_YT
zcB;J;h&ZC^zXrb@R9EOs>!=!|z2Z?-G3}k4R3TjeJ*M)01p{?amC=6NRi*hA+;LTQ
z9*CQ&jSgV$s$Xf>?xEU8F&!^eE#(NjRY93B<fEFP_pPt0oGO`4sI2T(P(RhPZ^Eh5
zs<TwO?5~>s8O{W#R7wmjP}TAk`hrxSQkh|}>fsTPGb+c+7+RQWL=BN}Rntdkj8s{d
zz>6r=mvmJ&TJ?qpNUSP57Y5^0`rR-euaXx)@`7rB&bf)I^;SAoT~r;tj?NU-sx=^~
zs?R1MlcsuSCAbXL#0`uoQ+4%o_;gwI^uIvMR(+lfyE!W926%r}6*UQzYpUr87|d0T
z(1zx^Y7Y-?7pUUTp|Mc4B>~(GmEixeH`SYzBPdq=_&Y_fN>rVX!kbc63|*QjQ*EKM
z^ljB}01TF^SOS=@P&xjBnW<EzQ{1*%6<i1X8r6<LkXltw3QRPpuG#>sQDtg`Gfk>=
zs^Dl<&98(rZK{hDENEAmDO2B}%1?uZPF3aCl>fV{;?YZWKs6tM)<M;LI%I}ajud(r
zR*7h#8d1GPH$z5M&vXNAOqCl8g>e-=2Z&#w>M5H1NmXVLM5a`~tcTtEs&&spWLi~D
zyQCSFBMV>;RHrFuJ*x^_2n%znqPOY%H?Pv!q19Hc{uwiCr#|0>PJ8vMwB0zO?x(6-
z2lZN8h&ZYv%3%Je`UlETI;nq&$C#YeKD1#yroOTReJ*OpNQ~Z99Y6={<LcOEn0HfO
zb_KM%+TkY<5A_sn6}{E3P`cCVqyCjvYhQIFWxh|SUvL8PQ|DEp^Q3wOrLaz^U-}FN
zPphvn(C4rIn|6gkYTXq$8mwMG$&e8B1KL4_s-4o%cSijJrL4o$+b+P1aP{s8fJLZH
z^fErH{^=E9Myh=uMPrmzUA-Cl(dvy)V7xKvzv-zwr>;DUDUDUf)7vy&{oomBB&gT;
zgPd3AQXuhyda?xAiRz6PA#zdu1cmHV)NQ{3B~|?n3tXD|Q9`+-j(7@|($%-<(4V2+
zM~RY5b*LkpxvaJ>qK#*kT6P9=az!0WKa6bk=nBB(sHJp&_o{mBYM8jD7ScnVtA08V
zBu^bhDX2pAFrC(KsC((<R;14M!mx|gK4DNOQGbyN?xuR<If&d+57GO+R2@#ANi9=L
zUj@0Xp0v`Nwp=|`4E+kV^Ky_%b)6FAj(Y!5kSg`;7x1)JZF>RE)T!5n1Fc>?Lovz*
z^_^arXjGqTgugB7ce=o}s+r_Wn>v6}i|y*Y^iu3lU+RVVPW3b;<?pIvav<5Iw)|<u
zly<8>q=QtC+9L_1R~^@j#y<7*9LPQOyH$YcSEtkZI-p)@g56=Y3m49esXzMvUS93J
zA9@pNVGjBx)!qeAm{L#vhY7l`PNX`$Y4z||=$lc$CPCi=^=DLWFsm-uLGQmg^*cAv
zI<MYN`!ait>Kl+Fn%`Vu&_Q#ODk>Z`y&7m7)qFw8TPICT1<X5Zls*7Grup<VM(Cp1
zM2nZJW}O0VAJ_cyCO9`u)itPlYIGmMf|n*I2zuU{gH*cVqgjm-MC)Q-&4?dBPiRCG
zJ3pmKqI=z^HE+>7*<Vw$8zewuHx0BvO@%YKAWiX~FcGS;qtL?{&9UF%MVMxmLc-yi
zSFgfggyu<_gtHo<2QVWwVhXEAX{t?7h}P7-289@n+Zlja&uP*<G2U3s(PdCf()1uH
zvN&1OLgD5VO*JW|YQo&nm!^5#3bad__X98&=^Dpu`aNsTUxi4f#*Y4p%VkaM`yg4G
zC*K3PqDiiTquCmF7jQWmuXadY)%4RZ;hIKy2w=HZO(vzzu4~*VK%J*~)Df-uniyL8
z3p7;}|18u*zX?k>G|TA`FVYmy@?NYt{x)DrG(o!{c~f(<3wpOSm%hf(N;M-t0JBW<
zwKw{1YqrvYTCSO)g|R}@PQ^5pngu}^{T+>U30?HB(gaiWLbYZ$57;%DPjv9KR#TA<
z^L3hk=z*`-d_IM~2F)U>^lsGbrhlu`q^ao!Y1TY64f8D;2?d&3HBu*7YSY}JTCH}?
zHVVUZXg1Snuv61|9+-DETh7B?mqu@W0NSltLiKAsn$^YNdNt0Q;eMZHtvmGZX&Qfo
zM!)7K3b77oo)Uu_)SRMng(1z`-Vhnqtk?v*Bbp0$Kt?s2Db75mY2ZR(T=Vca8YeU*
z^l_C*%_gc5o6_XOgWT7+-J<x*w5Bo)GP9bOX}dqCF)zbl<~6N!QnlA!ehDH+w5?Rs
z=AiBF198*_wL;{m){7QDCvEJHKy%hUNlBDrTF-|uP#5hD`jnKbw(D7l9M^7p7Yc6L
z&)<gyckMa)WQvE@K}hdEPwiGpKYD4^pFzW0ySEAx?4$jX)*@eR`4<@PNo_+u#(PTp
zqyv09tqpz}3jW#yagYqqwnf53p!Tm=s0V2~7NId%`}z)uglNB}BSfh7LkfPK(O!HB
zU}4%nX!{$kUA>t8M{0!D^L4m?R_m-pXQcKi%IZaF|CR&voc0VAqsD3v(YhR`U7Z4-
z;<XRfV-yM6o-v4=*9JU~VPDXOKLW`_?b5el{-SpAA&4Yto9RH2tbK&y=_%SHpMXo%
zmI@)6ruC%nds{DQ*^}@sU7M`|o1x94na$LSpMdCP?dB?AXKCM{il!^tjQ25^Z0#L-
zo91Z4C^mCdE2K+f*R((S!nIuO*M-o#uD$aC4CZND=tZBe-A7UK0<DmR#zHNF!YDVi
z-=2i`MOLlxW9S!acX+^jiS|kQ^21H-flzR_wCkyuyi^-QTk<mPPDgOJwcnkBV!3uH
z6&qJ*k9NXfrFQo+DBRHwrbDDkTe1LltF?=s0jbemc?OcT+G;v3*J<T{!Ct*~mg<ul
zv{ubSKx@>dQ{c2o`#};~o3%gJ1Fc2-*c7-{Z82@a+q6&6=aAa9+h4+Tb!c6_hDfLO
zF5PPA)~=+B>pj}X&cH;kwi65M;y&&9C&As*vS`=QuRWCr^#N@cRrC#N^&6o#r0uX$
zLU~vlLmR3QZR!y?JgQyG2KJb?^&k|-wTmf~HlbZX*``Tt7G3w6((WvWPxrM=bWE7m
z?*9gQGup9ca1XTa&VZZM?kj`HoVIZdpy##!(d7|a-7{2-W2bw`34^fLRfo{6+9Nv2
zt1#%G^Q96DN1cHRR*&jliU*97?jwreJL?)IFp0->YbhM!qEnm(jH|AWp8Mmv_vILq
zo9?$40qU;XV}QDc?yE21jHgaV^~7Gf?+qA>x9<J`Bz<%@642<YEB=D=e<yU7QMCH$
zRy+j7le&ZNz{DxtObDDgty@d!1b<x*m2d>;ii6M?s9Ti?>>%Ci?l2#$Q)GjL=sLfG
z`B0rY2mYSXz5gpnm~QLm01MaYpM*lB&WW~sQM%Rppb)M5B%1c0F}erufIX*M$b(F*
z?sLkZ#p&K(2hn()^i6OHIu8?I&g%@pki4K1(mmQlo%$6hT-3dhhsGq`AxdZ^>;BAz
z7b&{&7cir#x+uCTl&0Ix#ON>SR#I72y6(rt(96*2Xkx9Ix<zyVyR7>#3I?-utMZ_D
zMfWIu4KQ2hdI`hM(M762uIgU(faEpZ8cL_<>fC8xbzL_w2+2I%g3D;k*JV(IsX+JA
zX`mG9ZhZiQH*}r|G%YUDZKXs>vF_AD7%I_i+5&RZs@qNr`YqkSDrl7Ie7^%%rkkfI
z-)-G^KDcrn?=9G^(8W+<wo+HaMdKY^!($*-x-TekP_0{W5ehZBU)<qnt#0^RDAef|
z^nldsxRYpX(5<Gr-bS5qHRhs8_g4l;v(73=z+|-Oru{%#bx!mRkPcleZNxft=Urjq
zuI`yO*zMA7=m6KP<IpD`dUX3KBipO{;}b~s=^m!s#62CqA5+q=>)rvM26SvX84v2*
z#2`bu8Jsp259^+!1onu|gL3nux^^q2%*S*^bo3e5#ZtB6gziaNA|`c@+ks5!o~BgL
zeO(o0o2GSb>i{#OyGO6s2Rd)6^q$pSc@!vfy7d${o!8CLF3VQm$Abww{jcpXZ?C_&
z03$o158MGg2mPBbfjH`e_tB2#sJ@coWKQ~}^h0#k{}BwuWBM6?^ttFiafhO-{zfz!
zkL$OPc{lw>Q~>R+e|r}cJoJO~oAcDK`5WfF^pYg_<gNFhH@uHN^BP2a^$Cvx?1a8f
z2Sa}P8@m8@Qs2Ae|KFd`%k0p3TL0@CQ1sV#(cdXRKlV1z0`;}DG6m^ZP;pDJzGEdo
zL-c+OG=}NpDaI16Urhc+=pP$`qfz=xw2_L|7X(5wMnA)czj6BWYRqrE-t!^oCFmcf
zH7rg4+~5EI|7`ls9gs=a+fpDfLmzhomNNApF9O<SeLtO&vh+*ng?mN+4ZSI|_3dRK
zIr?K%m3dWPy#$u7=|6f8D7pHaELgg(|FaNY<mr!WhNXOc7#)NP^auB1E(-NF@esM8
z7d`?JYmxqh5HQ7hGsVtJ^iO>Njhp(kO)z*%Z`47iRPQo{#xgzU5h&i)>nR;jt}pMz
zJXPpF$bmDJdc76g9lg^NK&jFX($&Oj{bSoeYV?c4p-`(oEy9rM^iBT)vtECZ>Vz76
zj%Gh=eU73gE&8(8F@je8b9An3(=VkXM!WuV%5rq*U5-JiQ~xs+Yv0xXR{-5EeRD9l
zZaqH?Hhc6EN1*iTQ#vrnKK+3paQF0oKaa`j*YBis*?@k?6PSZ~?`HTjq+dnl^TYZ`
z>k!xx{rEQ!9o6$`w>qZ()*sm8dKvvuC-hEqw|Y`v5erLG`X5$-yRWxWao@DQ<3Bhv
zqvz}anbW^|0gle=bN>UjtziU9>|#4ZK{aO6-r(sCLq`movfzw^!D${~j)wPMwL;^l
zf%`2$oeUXkA?j>cm59z`h8^_ob1^(03p7{5`F0pQZaABYJ~zXuY4o`pex+lNharZx
z3Z91LuVN5hh7lQ@@ix479Gs6KV+}n61~*CupD;wyY1+@QcPG3!X)x@iJ9z$vwe+G0
zFyzkwJJ3)=)dfL@fndM{8^*HWVTfTHeJUW-P$GfI8N>QsfQA{A1QTw!MZdlX!=X?(
zde$&OS^h|ay*I`ZW%%q3kZ6NzC=_B0s~Z4z&frDiidch<=J5qv7RMP>>i`pP&}{*B
zf}tZ8o#zcD6wJF|*tZHAi3WWdxQm9NBjAz@xmj=~*`TM7J*60S7K2MQjL_d8&5+~M
zbCqRH8Uog3Lmd5%vJ4+iL-2}W!vy@yHZ03SV~$}u72H+B<)_hi&Co+Buv`Q8cYs_s
zoZbp|^9-_UK*=|BSYV*QFg=UEV4>m1E8uPz7EwU3$nX#4M2ih}6bLCX^ibXSO~Zdy
zdWGCFB++fTQbXlIjIYcfS%s;%ZP;nRP|6L}^RQH5V9;t*X^2(A;2pyZEw@#MTP&be
z8~%C=jWvdcLm*jeSU~G@ok2yJ&U!;^C-fQ&U(lPR(Xjan3^f@-C_d0?nEQt^OKpZ7
z^d*OOgI_s@)?rY4K)=(VxeeFu8oItfUzeeq3gx>EpGctJV{qR9v|dBkJ5cX4WQRiG
zo?&(lKJ^<4>CZA?INl4rLBnb)xEnI0Jp}b(Lq!t$Mhpdm=o>Y7SJKXA%+MAAv~k1l
z3t(`<!1)+nOd5P>F`PE+Q9^&l5J!ie2ZrSoshTyUyFzl#kV$XOdBd?#%#*E=M;FuV
zjKKjgVQ>85W#}C-eneXm2jiUuaLv(Z9ERPa#^3%0n3FLVzXSeaXJaQNnvNM?x(P)W
z<9ieYa5ZlF0W!yp**^U1E3IL4A>7lr@^_$k8TZqL4R53QWjN?#TuQrOU!!>uxD&?D
zDM{^TEG&h>N#nb;NS!jiMG247#zX}g{f%Q3ZVoVhNom?Z<9D<y1sM<0VjpZY*@J`_
z&(kY1)ENB_xHCqTH4fNeMnef&!;N=;ghqsM!Kbi$*7yi*CnJrHlx&VNYUx>uHa<!<
z6fws4=t|`|<7fFGvBs&dF|TpP6|aDcHx{h`c7pL-3)IgWzow1$1>?DBh$I?4BB6fK
zs2Rb$BpEmMTY;TyWX+&6#n?|(j;Tf)N_eChMfah9$(T(0z;xqvF1QS%<_#!j8oj9E
z<+9P{Dhy^BfAd7&72_%oG+s5HrrQwLjKy@U$u;hH9O~DN!H+{E&-fY@1LPZbv|=g?
zjJ`TbKNcF#6an;x@n>&z78yTq04X+#FM*U8_fwtGO{4V?L~a?oUjSEXEN4T%%y?=&
zOx!lIsHU#m7);g86-HGMEL9p`UJuDT#t~XZtBe!vAl1g*atyG>_#6eMYmE|=Wmy;3
z8FMVqs5b^tf~dh5co^<C8og2g+GNb9qO@jX0WIn+#$6N|YBfeKghHE9QvieQ#(0YU
zb{MsEa_TfTIf2|YK2#08E~9`B!QIA3>FCpAbfNcduQ62#g+5~oeNNMQ&&cQF57ck`
zoo><$7{8%V_Mma|A8>!j*hZWGVWU+5m=R;?M!<|3chJS^G2^Y3urzLLN`>BpvGQS%
zN#nLmn3yu&q%H1!<5qfYOdF@iFr*pdL=*HL7@weo->lKxhrT(h@fh6|nm78+!IG`%
z3;O%onby%VWp8RqfyNQj8j5T=n8xYRbTnlhh9zgyRy7)rnZA4%A}*%QchKi*im=6$
z95<CT0MpIn@C`V3(|syJ@GuSLLC@3lE|r*hnO;~61#gpetsbpDrvIp-$=AfC@{SWG
zk4+$crU(iFoHRN1f}Aq_)(4H#rjKZ4@Hdsv+7)0b*p9|P)0=)U7-TA>+R$K=w+udo
zm_A+&lu*;xloCB-YI`4s!c0F<31YaZkq)X6rUC2sV9%Nw>E{(`+C){mQKmf<@r*XT
zNSVeMQ~W>ZJ7?N`34O7qN(0d1OapfCDc&TH#at$sUZ<D+d6S?8dKXN+^h!!JNe`g!
zqUl}+xFnO`B=nL^93A{kF;(TEFV$538om0{OeJ;j^peR$m2T;#SLnM88K$Bs^kte<
z^g_REI+6?bvrNx>qwk8zs}*S3rhn)tkYhUYJj`D;ZKC4YYo;@FO*7Z@c_l=yn_SsY
z$TRJr6nnmjF$jeMQ}A0DOQC6B3WZ;9nEs{TY>~<C0c46z|HVP3#8jyQXsKyZ1&7N_
ziRU45+Y~SXuH1CtDTq{<zCR2Tm8O*|AbH1hdI!u`nF3$OAgWC#AH%R~Od5LU*P5=7
zWS!~zCUEtp#e*=^U~;gb?Qf$gA_ZtorgfA6Z#GqY378hseTpTwnjGmdZZmzk2xDqD
zP3K^OJ4}6b!0t5tu@si>n(B^1y~}jRf-!ZQLN3CY9+QkBkG-bY6Y#gs)bke<?wN)z
zgX=f#T?FU>(-I0bS_e%V*P(UDv_}K|VN)B$Z$?Zkx<)^0+D%L0nCVA4rHq^QMZ&cS
z(<m*4lcsnIWlxzrU7&a0^v)~brcHJAury=Z^%%@QFr9l63bUpYv=f*!xjhbU-V{%Z
zkga)O5GZz5bNOzt_Ga!BG>({Gtp#x~Z}|=e9nA-5@{gMLZ-5t0=H|Q5a5me~E#hP5
z87dTTF}qO`)zv(;8s?9iOQ;^p&CK&cpSwBL1qMCL-+Tc~PjmJG5HIs6g^j$;HIG8i
z$83$C#_R={U#HMRpgI2~SPC+)?}w#evttA_Ld=dopfS|kFM`M!^TU5)ykX|==q_@&
z+4ea4BFw7W=sRon^Fm*=`Ps!#k1-#89wO(=3#nEl*8F%AB;(A7egTO$_fb$Z!Q5uu
z0Z-4H?MfhX!Tb(wB@)ely$o{E{LJ$JO)~pXW3u_9P=KbG`LuaWHMh{OJI%Z>8YV88
zw^F1g-JIkIF2npcEq<Bi;cQ4=HnV0iCE4c6PBiA2orM_oRrBv^kZb18k5l+H*PKi-
z;p^r-LvSk3JT3%GzIl{F{srbOl!PfX8<wN-hWXpaF?&U36Qx~>&8O)IQ)2%43-sMI
ze{%&UZkbmlz+kC)APRkDW+O$*Zkx;3LZsaM{Q>k<n16o_q{{5tK-Vv-%>_FlQ)B*w
zLMF9lPl|QanWqY2x86Kl4$ubkGiH!RvtkN;P38v5f;5|X^oX{YSL&eGY7Q$0X)}LB
zr<iv0J1;=8!+ex>ft}`W)F5}we>Y;BU1p{~oar{JQ3PaN++(g-4$)roIMtK%nae2=
zcF#Qc31s@saZ+dum|tFszCrV|4lprfwx5CBVKXZpA|vK=2O%<Q4)_X<W9Dx9(9O8n
zmkzNL=KN>i%%nMtzU?_}meX!~#vJMi^1wV<0YlbV^Ak~E=gd)b{bJr+{t-AkOW6Ww
z*jpU4(0Ig>(*wH>7AN|nJ6d)&!R}E@S1C9ri$sXIaJIx=1llpnMJfw%v9K9vbhT_5
zg2-{pj#co&&Eh~eJKQa4^oI4Y*j|8wr`00d4HI6LWfU9owtPi9V;@Tj?S6eNTPgi<
z!t!Ds8vQJVGq8Ko@;OB%Pg%B8T;a53${u?DmU0am11vFD0UBs|e*&06mV<N?G}!V8
z8z>=`7xKY{TF%hH{EVfWHez8GYbO1k!!3+o!A4jj==^flvWIH6A}v)90W`|;z9XhI
z+R}XimSQch(<2^dIYR|x@s>KeV3}Y^qF~T@i?coSE?7=8U@6h^HV^6-EsYd~O|opF
z-&3;XbvmG>SiEQ{OSQaaZG$&ymV=b1y<};p3s32me|~}JRf~KK+%=1ZR;FCbr}T=v
zZrQ|w`8>-j2VgMYQhx&Kg_g(P!gz03c2jwAk)@DM5XF{%oFP(Tx%M?gZdqJ&fKqBX
z{x|x{EFV*n?6xJ~MJv$CEfV@$R9YM<_jJdip~bVxGDVA6wWWxju^P)GpF*S7@<<&N
z>MRQ`LZsf}7>J=YSXNOPcB5sn8Inzw-z2cxY<VUEBW$t!Lwo*K3*$+Mv{^=KF*EI!
zQV!HREFYEA^Vex<{vLCA*YXCX^Sb`W(RIgVU3GD1%d)gAN5f2QSZNy1-g{5f(n?FS
zX_{JAj)x)3g#t2VZ)M1kA<9%ikRc!<q5>j<0s?}7toM7~zs~2}d%owKd!OI9_ndQo
zk6jb3_1f)hCXf!hXUm}Uq1}vLh&-|@eGb4*yG(itblJ(Nu%g?peGM8P+i@bm_1MjQ
z0@7=Do#NAdc57KM|HSS-Rf_i8Eg-iC>|$uS@YHS%RynrmgLZOCZ9cOT(;?XryV&h8
zIBNIqJ(wS}>uf^fxZPVb;o5{<8x`$4GV&<T<HXoYdk1I6xdxB}4Bt1==fVhh70TQg
zKT#owJA*kN<~<mbDYJQy5lL~xLyU$~5IMqF_83}hM;V`_LDZA+HwEU7F&4B#<~ZXa
zm7{nuW>PZ5o57|Pm=DAJI>-seY>FQHG8VlCoFC(83Pk)FhiID{z_^r*#z2OI7U4mR
zDP|};$$0M$h8@iCTL}`vIQAGMl(B(c1YtJDg3XW#XC(H*sR+g{dc#LDrckmgit*_s
z7>s752E$+sBljvuEJG!RNF3wI$1oVr_>(^Wbczv0=K)SL&dvczU}!_}+b1$&B>*Hb
z;@88&WX8~Q;Lb1(vtd4sF%%5RbcXFL?TF7Zx-_tq!6^F>erGb~w*ZmF_>H2l=NLh>
zBFSMmeg<-$G4c{5FEB2@2J^X$w`akbe8#0l;0hSoVNhDgxMxOR5#wwIMtG57N`uH{
zMv5nfRLm%jgX$7S+wTy$!dPK@6Tni&FO3i_V{D}?*;U31^h7OZ<c30~g5g00(3OlY
z`r&>RW9!c_agFic|MxtMD^bAJFg837-L;Gbv=X|`D5FxoI!4zCjO+$O`5plE3<-tN
zZZa0oW4(c~kFJDUjMsYT{%d6P(DL~<!=Em;I}Goq@Zv7x9z7bG7%x(8qM1>!9b5}T
z?F;wsF*=ihZ)Ip|;OKou!5^5XHiknm>^@-pKwsf*XIxwk(!toY5{;b<eG3eAF*<Uf
zx|^|a6oAK!>(9~s*TZOjA2Pj+x97l%CydWu2e6;<;s<CPV0`-uxTg%>TzE0am>dJ(
zFk>$zyPh#}p92|TtfM&QC?l8(b;cM+=x&-|w9&@Rf!R$VY)57<#jc&0`@;cuX71Sr
zFAgwodQkeqg;{(Qt**?)uRxm{(?WRwcV=)Y=E8%?>I8R?`D-<}L(CgnF{Ou@d+2&R
z!dyuk&ZEpleV7YR=FsbCJjQ&9mJ-LAD?Wn>FXmm!NqRF~gV5*0lu;hw1T&XPHGP@c
zf$+)Z$Lt$|8h@ty_do<N?~34XAoB_>k%O3${}<#l1E}&Om^sZIz!2v9ufmH^=7u%E
zg)u*Q6KcYl;dfvuf_bSOjnPcsK6nwsET=tbEb~?RN<tj-qZNS1Gp}BPp;OF0iVK{!
zF?kXo5}CiOhG-JAo=$xwGsp7b#TllU@?j~=$xG0f%4BT@FpX*a7=34%eP05Q!R(=Y
zWhOH$3%@}YQ`ZfW&CI2!=Q*Z=2a?0Qod?&>Gw1w`Azfe&9R-)me20n%@|ZT}4Im1b
zTP|X13Yqyq;EI_4QtIp?GdKr!FEO>%FmajrfcCq^%*yBC#TBObOXx0TIs`zZjCpS%
z;8&TeW<hB=^MeyGQNf%^B?*<x5c2REvy1W%)y%sqp{0h&%>$s8xyN<~o!6Oxb?B^P
z`q8=48_cZVKyEVibiky68JY<bx0na$5#GpLLWMfFnX3xW*u-460tTCzs~n-Ng?V!p
zX67C<>^DfZGC%OdAnr3S(_XfX*+9Fpc4j@r@j94Gs6OH$b5aKF{~j@Cd<AWt%%SUW
zri=NAvY*{dyPrUMm_C!y*vq_l7k>9K*DV0x3DeUJ_<m;8zu*R#`5w^yl$qiNErZM%
zAuvD0O#B+$Fmr=9e0s)o{{w(grsGm*8DlQ>fxqL-CpRhnGQpg)1tuI=rDKqBWKGs$
zgib6sHbf7wO4QKi!g}Xx^trNpwqZ)#SP>KuaA*De3v_$1zNFmIK~{AW3?61}p9}5?
zD~L+>kFsX8L769O@FW_Ku^3YLdz@9b7dS6gka!aAKOa`~8g!mu?b!i@FY6|4mi$<|
zJ_PY+l`VtPAXY7vC!S=v#y~Qd^)wk=2<uTZxKP%vJa`|*+V&!*E1dNTZJr}pY1<(Z
z#cEv-k!aS&C^W{fcFaa&EX(YT#yHk?TB+LNStE2D;xy|+56C32j$c4)BC8=5jY+IQ
z+TSO$X3<Oa4C~Vn^rf);Xg8S3Vtfyh#?sR5o6hn#V`yhtUUXMvvUW^{_gO3fJ%qAZ
zuTI7w&arkLhGY)wwj96KdDeWY2f1Kl?Q4Tf9%~ov!}3{)LWmZyexvA9AuEzzQbjDE
z55QeyeLxq>CDv+6c^9*CFQT!8wV0OlS6JM9kW!ZIAM};6WNYxFU1hm3AyUqAa{{Sk
zF=(w;#ad3Q;A^Z+6pg87+4^ZER>NAg1yfVU+9AXUZ?KNh5sP{jpFWmylT~#S_y*R<
zJ~ZB9`Or?Wk#*P^<PK|LI>=p?oF=G=HQoe&n^`V;m~UatrdP&2*5@3+TUjgm(AUN?
zdIIo(b^9W?cGeWzBf1}0^G2ZiAuFT-1|P9L`Wd8?^+q><T`cQ-%vU$dnUdU(SskxI
zX%A}!y{h_Hlj$k)g!NS}MEY6Pd*H<YYs3QGPgyyXvl?XCQ_a;7Yd>vrp0OHdVw@wa
z&@p&1$`b!h@4qotu@$<<S?g|~bAsjbF@6yTw(V~aC$^d@ww>A0R9<y}EvChm3;Qqn
zVO`k~^dxp;Pw52CogKddk_XxI=A-WryNhZi53}Ff2$3V~uL2=*lzoD>5XafiuLkjA
z_f4iCxi`DwXCQpo-p|3|6YK{sz+qqZHaffJ$NsPe9tN-*sN^}2?JS1UAokBi81_l_
z+8JmJW>2BiL<qZ&7HOgEPjg`~oSi`_?+CWnHgJ*bSu@~T6#LQ7@FJSs+lIy%wyWn$
zxc_3=yJ(db$L7X?#Iw7o)a(@7nbJY0**{ZVej<CphnS!ww!R6#WOgbYia5hId<Bxi
z{&^GnQrVj+1dzu5<~&TCWd{_4WUyQ4LpPc19?H&Sv4!-(nQZohXOKM4E}8|L?E-sX
zHw@;ot9*gTV=MhY^4Wc~B`#p!f{W7&**hK4c#%DY3X?9ez3Gd)m)U!hVZNB{7XfW0
z?4>_op02PTJHcQn`{Dp3ud-S6QY&ZAr!#sL>@$CZt7Nwcp}LBFaxxmP+1T;4_^)P9
zqXl3Md$}J-Ejx|k+t=CaXir+l);@*%_3W#(61vG=_7TiCu=x~Eyv07V9oib%H>tYh
zHrvMy&fH;7-;BN{_S+{R+00Ju0%>9QJb|Hm?BCyk>Q;6Z)tNtF+d3&j+Rom760IHV
zo<iUsvOh0}=p**XBygSVol1ywv45ht_+xg)MQ}arYfC_S*?%`ccOSd_H)wmpzOxr1
z{p^n^XEeYrpfuqiJBnU8L+rOoplq1^a|wq1jJ-VslQ+U%XQSxVDBFjQ{EV@KDdaKE
zUP}483AXcf03A3bbXhubN;v>JbLLT%#{o|G8?fZU`HQl4uAJAXT-}Xx?EsXzb9zoe
z#Dfz=fvrQFoG&19nDa0k%8qc>d<c=FoaMAr^yFmxY=ev!r#cd>H)rz-a6X)!kD>bn
zr+hYi^5x{3Fc?41?N=}uf6lrNSPJBLQDIXM=fFMSPI6Yi3_vjFdwN)haJs7Ti-dAK
zsa_|H<3!7i2#!C!4<b1yo&pfX@u&ld=G4uk^=Ayn<z3)oId|w=;&B``t;ORxomD`b
z;>`4e=xNUUSJ0QhY5Np|N#dlY0FcZX9EOQAoF)|{Q#c>f`XrTOh=%zz&U`9&Pv`jV
zfwBzF``=?qGC8a7fMjv1*8z~t+2Kk1zjK^AdQ4y7yh72DT+Y(Vkjdlhq@7GYr}sAS
z1)Tn3kU~zyk5F2~nfD>abdhtV6kc57JWnshVh(pYL`pcG5_oup<3x3*rJRzFAyUTK
zZ3ormoNpHcSHa0rqpy-Pi|#GkHBKtM_NzH=O1c3!b`(FY<#^H)^*ZN|6(Dt-AKIY%
z2B$R=uHEDex`H%tW>x}si=!JvUnA$&o6vTf(>4IW9ZsSMeRnyfv@2`o{4))zTR87H
zK;#}LF&ThX&NGTO-?wozlp1g2%=s8Dc5wFA!2O4udLhUo&JVW%?Bsk%tM@KWINdqj
zob5(PKIXjp2-<o$%W0|D%Nd|2>J!ciE|m3iYG`#fz?n>68+pq4iIQ`Jod0s5Wtg*c
z5Zp74j;cFGIJQ?i&^pEmPX>ORvz9Kz3C>;mG?fE)jLIb(xsI_=<HXH+1kRc3MhOcS
z?gxdCbmcM*fpg;?m=1tD_bsXw@!<Y>8OjcF%^sM9L)@eE1V6%ckwWq)*Fd$Bp4{61
zpz|2Fz(x=4<J?Hf-gt3KUx%6#+-dv3`EuX+1_SluZrBFSpPNMC^#E?49RPvcu0(J_
z-1kl3PI5UJa3+|WejM;n?yIQ5m>$Mmz5rY}_itL5L~uW&=W-;sJ|D9l&AmZU;~4IO
zjdcITa#vHDG@iSNp2(-Tb7la4np;cXl1t!rW0f{Nkz4m6B$K$??0`?^*72b<g?o4x
z)TDAR(fyOgmClDqI`=oaQ_pgzz6=jDxcT3sF_T-7it8eqd-Qq0&v9Q)2Rw({S4-tL
z=ehm#+P}cvz(Q*-H;>YQ1>6;Us43*WPyu`qcOL`XMXr%<r%T)wIUtw08VV8?b89H^
zUBZ1S79v-;Yd-<Jl*^^#l4acQ+R=BFyCw%iD(CuB{X_+~I23bH$qn(P^3y7AEu|B#
zaVw}+x|(}m1yaL3Z3d#2`(^~lb?&KrsHx{Jrj6rG?($5SZ{RNd6_U5Od#RSTk-IVy
z=5KS$XtQ#MyM7Y5yWB1Gs%qlyqo7$cx0D6a!u|Cn!0&M<STJjA<<6v%vHRR#DVW>F
zt;)fe9&le>2}|wVvEMNz9b8i`fDgG#X-EHvJB{*bo!maU9UgNzpTLVAE<Y4pFL&iL
z!27r^R1WrpJ4PY@es0H7SQy}LTn3#_xikKT&OxpxEjWj4+^_cnKg|7!^3u<^*Xe^#
zBU~AkmW*=i(xGjP`>7tH<J`S}ft%o3|9~0?-j2mk>c|_t2b>eHla8)A^H@Ki&y{zG
zRy%IIQw!m*J8x73xCd{N2UH*A$@w6McoDQ*Kg_fJK?aZTddonL@^&tS2~S=RU7p8y
z7Y5Pj#mgUtGv2)ZE8u*1HC+In;BEg7mV9}|^g8q7@ehLd^V})c7{FuGYA2AFO0n-C
z9>W)XCwbq^0tw;mqbkx+-dfrxhw-l4XayI}Tbco21aBWzwnXyMuc9%E7aI(_(LDB7
z5RKveRRE>2yqKHli{q7i3v!A#ybfNR<{hR5RRZsF8C*-`Wolt5iN~J=lFU=4z>70H
z2U_)~@M0*{mdg996^&`Udkbu6P3P^P%PW)jJS{G>c=7Wflg(RBClAi?;wVj=!;7bi
zk@Gz9^Ju)l%l;A0<nsP`7bK7Ogo1tfyj3jV3V7eq2j+@++y8{y7kRn#NvTV`Ih44&
z%=`8*##zjpc^`lh-n9kv`L!!Nm+cs6DKGjXAj)|DRA_LOw=)4U<-B#yz*q7FeHdC5
zZ^JKWyv9p>6Fyb*qUc~)4et*w4A%0N(6?5u^OmOoP{-@sjj`O|{aFv4^}L}C5V^@)
z9t@FNJV*K*XCtqwiSqBadCTbvyu))U0`M+x^?x8uyw$4!Z07x}g=h=!XWCNV<26w+
zRx9sYdPUyng-~d=owub3W9r~dABWoyc?p9MdBppJ67QY7d<xHX@w^|x-)>$em90MJ
zU8JN@4{wYDRO(({E`5Emk5^X((SF{Fd5{_4)m6aZr@Z5Qm>A@_B|+&BZ|Pw;Gt4WO
zgFNGHc7dZKy!YRLwo#tZo87j+rrC@(C;pXpfOh8pK!KhE{6iERbm6ZG0&(TLUxi9H
zek`3WaOeL*GvdLQu7Hw*{HgTy>%;v0^vFHJ4=RM!qx>(k(dfzdiv!>o|4+K`j`Nq%
z<JgP;<TS?M&0q8jh!6io8@+Z<@QsuQ^X32k8Po*u<GjEH@)KUbz=HV4C=q;;-%Oc;
zVE!UXIfd}+X2R`I{#OS92;<K?1ry=?DfD28;NMz>d5Prz{sfZI{Fi7q6vJO;56M`*
z2Ypm5jvqp?`FMWP87ihe#eYIkveW$9E;y6GUqq|@ME=b6AW8hbHvvrM$I>e*h3`-e
zE|nin)kSIine-M*=RfBMyJz`@R56ml@1}2NW%7?rh50N#kB4Dr^TT4G`W$~NmAU5d
zziEcZ1^!e8y-jlY>8D{SkH57EB%i;Rmc0dh@m`QZ{*JZyMT+=mYhmId|Jh-XOMKmL
zuzQ(rR}P<w`5HUuF69T(GP{gFvk8E!{Deu6Ea!jt03sFq$MiC)<m-QfGgW-ipAfmm
z*GJP~qH2ECzrfe<hb2JN^1tbVXdRzPHETEcm%l(?Jztgx-8cDv(EFo-pLQ1_xA-1G
zAdUPmswltBZ=ikG9X^wk-Q^e3le>vunGTT_etjdzJ$_ytoN49%P>R0${FKwc&1&N>
zp`_~r{=#mww)3xeH?_ZEJ39fUlfQZ|NH>3!4wXLU|G5IHd-$&27<@1PecGY*@q=w3
zPxw`I+^?U%BLhwh@H?6y`IMjd4d8=(y%PXKd?UrtM)+USreu_VgMNZBzMjJ8<NPEF
zs!i}8(sv>p1hZ@#VbD>qj$CpQ+=&Ho7VO*u`~gA7ao}A91s2Sqo8SVa2HXYHXn*M;
zm_l3FgMyE!M(L2?&kx|tVS%9yKjaa?*FQt&QGw`7%z>xi9g3766D%u->f?gh3J`BW
zXdXm-1i1#v@tzRWr2yzF`1~?j{RBJc-wgZ(dOE8TASk6pZ=j&$G=M>Zz!oSyDR}N%
zC=C{*24gNl1@U3<B22JD0xnz-$O9K4Sbqjwq~MhrScnq*Nu_qt0!0cMV+1cXLnK!4
zV-9^{C{D14iV@=l#V4RNL9lWW>?R5h(*{0C@WH<rXtH2sE4(-(_=^^iDT3!|JDw`2
ztOqVlprqhfy1+Lc+*v_6Exj`YI(lhl3D$1}JX;_y2015ip=UsjKu2Yy=LH<RCh>_O
zfw35Na|J7T=*$y5pzvY7Kt3PST_BiCk-kE~8QRTU6iEHRT@vh|0{Y8>=p7)%f_};x
zmIx;3g?>fAI}doNU<vKm%LGmvL9Pn2Hbb&puxu`dR3VUFg!w7~qK34`5G>=Mvs$p0
z(hfBO0Ufxh6=Wnq>2*P)0HjV(tc02yf>KB5t`}?$0C!W6-2i7A1YR-#ZVM9Wpz9sM
zURr0~6$q$Uu0;?<NAT|nWQ#ERR>9?eKsp7dJz=j)aDlc>-8R7|biV1aKua<59)U;?
z(ksZIM?#-K9uE^w1oNoou3w;%V}t{OY)6dZsbKgoaD#%#*$^2LRKJDBVS&^hlFtPH
zZUuZqFmwowqXOdu$e3UT<sQcco$Em+1g@0$br9ON{0fAl(CZJ#I0+N!1BK4QII1!|
zAbe>S#_J+XQesT5!XX|8<0hQ;Ck(m^L;r;u58;1wkslN;SOwf6VG(_v^ssOZ6`~&z
zuBNktM}?=Tp21UihaPChgblj^I4;~AfkrQ3navxlxA0>tI(>vM{0969VFPX8eT7{n
zOunD6G9GIDg^MVU8z7uV@7_S+<s6V8A(Nt)Cx!cyp(R)tM-QzK;Tu%27%EiLJ3CBR
z*$v5X;hiEhMhI8eKxd?|gc3MWLfJ}srbG)10)dYa7JLuUSmCxl$ixYI=3z?Wg&RHw
zIVBu6U`(flpHmnwLHNcoj5kr(cLOt%BpjqjU9vElUX*8q8FUGx2<I(@!BioS3CT2J
z3w_EgT^Jt#pUw)iDWi}foKj5pU#9R7ElaY5=~PgVE!<5j_;bQTn}Ns?e)Ag|bA=uZ
zIGQK?hW14H!humZQy~0^suK!@e<ebsNcg4<eHVq=Simm{zrBFI%fh11;Zw12_#U_t
zVGKnruLyTjL0qZO2gL@q>1D#Xw7kA5tbPmla$y~P?WsceDShFgQrJoB)GFbd(_#La
zFoN#CYGDZnjWxm|`UX?2a1Nzjt_$z2hZl81)&#WN5Y|0FW4-Y8cr@M=UZmpB2H_xm
z#_pDIkg~{)!Z)74tnIe&4-1su5&lFK)OUq5z68EW_!Ip_UbC>b2_{;E#_izl3F9c#
z)+$_^3c!8g95a5VHes;{eGi0JLcz5Q<y)YoLs(5U77v9V(hK^L(1$9eI)!0W+}$Ni
zr0*Sd3!Uk1d~6f8F9+Krd^a01y}~A1LiY(*_kw#Oe0MDn{X(BYhztlT>R|V&(0K<u
z929<e4I)Fr<rIY&7CxX6J`+x*#qx;IJQc$p6;7sT!kDl#4ql84$Ctsw3E^9FpwmI*
z8v=l%$adu@WSm5o-h+&@$U-~l1ETSTQ0gLzr>KCdXyY#saTDqH!!>u2{cGSnL~CNe
z9Td6He(R7(OyBH3EQ+G4h$AAqLvZw%X#HK7I4)`!MWdH!VLZm`EmBeuiI2#KvXm!8
zlWi1|@fEE-1Q|b(W-d5?(aQgqkBGwPqica8C6zS<iJqrb-APdd6Rrh|lIgw=5h*GE
z6e^k=2)DyTb7W8&F8X8vMjs(s)`Y%D(R~WIM~PaJAQCOwy%ZubBFVQPv7(~qY`6yE
zL|3V*B3|_87Kok_9iw>GY0()a`VvHuQ!xpNqOEQaNfKSp0+%dWV+8(;$Z-IYDWaV(
zLU*d@I_(3}M2*|QrHcgb!Hct^LE6-0h<2nvb*4y0K4pobC_I}j8uX_a_c;;k1$5?!
zT&Py!yeNah@E1hY3drP&j#K<RPxL80^$JC*P$(@Dx%6NzE{Ysfn3+qW`&0^gS#;?~
z=q?sz$3e10<Vz(fS420?0bVM4lU{0NqQ^lnbX8=e^h&uXKXBTl4bv+`&u(B!D@Fb~
zv{s2!FF@Nhk>6{;*NP4cL9UA~QFf?Kw15fx4UrFpck4yppM&I0(Fg?<8bo2V8@VNl
zqw38@Q50pfZi{w%i~HWN1>2*oS+tM7JJKS;(-Ak5Xf+*fY!x|CIO)D<HC@zgq8+qV
zejwWU6-c|N^i%Y8h=Qpy@}a2nIoNq5`rrmgr^uoMyi4@&1pMn3#jeH>9*dS!7O6+{
zCI`4)(X%8t-6uM1y9?1LB7PD`zvy%{S_eey=<|_JMX?begQC}I)jA~Nu)z(BD%nu;
zOq6#Izvqa^O2NZX(Hn=LbW9YVhk=cYc3B}ZA^PSBTyqfn`~}sH;)E7RI*D)2$1FLE
zW2ma`fY^0{Qd2HsSGp`*#m~(`r<+(y2^e>=_XZgB5I0Z)<)C=gZg_D>97d16!{V1O
z0e?h1$qPd}Dt_-}z&*vAskG^s_!l+Eaq$lq(B~z-6bwmk@t0C4^AZ0w39g+GyL^H^
zU$M-cR{nnCX8HiCzqpWARRQ9mI#>!62mB7vAn|TWiJcUyHo=Qvu|qdRLc~t>P#P-!
zbpb4eiFX%+go`iJ+95)`luG6z#rzF`$B4Jk%^xe~($`eu#GkrDGG6>c7<8Tz-&sj3
z|I^|p&)`jh*q(}+62<$dZZ}E%8<i9%i{JkR+RljEOyE+)Gbvz}Djw59O`3Q<?KslK
zwFja5tk_6V-3;*tde&x&8P2eqB|bzu*KBdc6adbNudjuc9PwVt*_{_Z8G<3(1@SD}
zAm)m7Ga;HM{)r1NU;G@!Ckw<ooG{Qr@#j7uMdB}ZK=(zlt3R||5=Z<8e=m!D|HG6N
ziwEq{S0a{Bbm)qBIn_>=idRx?QJFZu2HaJ#OD4E-v8@ZLE5vs68JtR+_#KL#SBV>F
z5qwSDL~+7u@tpt+rbayK4i{_1KfVJ?*TolU@mw!Ha}oHP;+JDU8pM9Cz}*th{SkeQ
z;@B2gx-I6>Cok@ZU&@2XUGYK+nly=<mqD^w9GwF%TEz0dA#zV_tNseWR`GLmUELS2
zh=x;bV*WBTJ`jJ&1!)&IQEaS3oTLZhp;$Ny?veN){gF$j*qK7xUE)0_;dZxp3%yMq
zi%-x|j~?-2S~2yC_4MxU6VJ$k$P@7rT1fPZxfJ^t5FfHpHukCb+vj0^P&_~tM?>P>
z4Vc7XvDg=gXX1_Tqi;mar&PeGIF=GVV`A@8;Ks#QsR(gGTrwHj93&PV`Wz*dK>#>O
z5@^feEcvqqeFr3hwNU0FIf$e4(_JOIDCOuT@q3?ENA8l`FJRY0QvEMv4ocjoV1^D!
zQYrd(Sh8>lv>lOHs3P;IBtik8r)2sqG#-=m(id}%OWtKb(o6DsCWyDBgf0jlNi@|4
zosei1Aik0%bgI}-GEAjd{u0kE&=Mdyvw;4_G*GgW9(O?!Pm08xlw7TZnqZ0lLl_K^
zw6((FP{}5$k_nUK$H2pIiRb~i2uYqZ0Fjc7Uf`l6o&Nz4Et#_s=3^xLDa;=$@jiyJ
zoRVy(nAmBF>T7TblCxA-mM9rQI0=7aD%q!m`D95mRjZtloTt*86iF4`@TrnXT#z(L
zRV0Avl1Ym(PiG}P<M1LwvSdG8%apvh7Iw2FwOimtw&d?0q5GWV{6El=BUwwAz<J4I
zI(~IQ^1=mJ$d#BWKA0zoqd18zU$UeTCJH1UQ8c<xB1EKadXZ$-99X(25zuEbE=d?P
zC6^_i(Q(yc$rtqWDv|88gUA)h-)8_Qm7LJRnKH>Q3t{l8<P|O^p<Gg34igoUo*wvH
zDcSD<pQ<F{MNoE4BC|(dwM}x3?)w@ElS&<GCCyAIy)N<F2$?#Gm0rF#Bs<=R(t1f|
z8zgT^2I!^VDDhFE@wR00b|}3gnV=GuyOKIeVl_z?Q$C_ua^wkIYmxjo0B7z=)|9}*
zR!P)uXt^)>lQxfS5^v@3Oq=u|{OgdoH30ljGDO>eM-saRkWPuw9pYV*ZB5Y8Ejg0}
z#g8RkUjWb}ng2Pw?3L^uf#N>NIR>14A_@KwM*AgA7H|U+KU!%#l{}`<>Y&8;EW8|&
zIMUW&Sn}W~`kqN{*><3HMDkJxT1O@KsSspLl1N38<C0tC`-J4b<1pwT-TVN=QThcf
z`kbU{+I~Ar2NuKa1Jb@VaLq+3qL7QL^x|cB;U>+Xw}-p*43#W<NVikX?m=n%PUt)&
zok>5(QK{YQ^bYite*G7`I3~TA4E%BF$!0WqNsm1TXS}6J325|@e%6jDIU(IJ6F^^S
z!cWlcC;jqY==PWXN0(-R)V~@g0;T`ZK!c=<=-qo#`j9rv!BWL0j5kdB7DXh&rJ^rj
zAwnu=|NpOSq;6Ej7A3t}4Vh?ZZ!na`NY^^TM66UrRl;%7=@HNtFP%qQ)>G0{I#qC5
z`sim!CP>4GBue-AKqN`JV;V-EERCdG${FcFE>x#TeP_UnRB7pa;L@ZshQXyv4Y<(o
zS2ogB`=K;LIynkM%ajI90GK5e6+v6J^bpnSoRfah3}B9Q_Y7z|FV#{+<APMhfMl*T
z?ixh$q^}(V$(LsR29W~kGP<k^rCH&?6-fsu|8`NDO^@$O(!pVPcv(7&$_s79(!1SY
zOQdg%gItl${2NM3r7O5Vlu0+xuIZ{Y&knAYOS`JjS0TMbJB3Q=zt3RenzXzGCaR^}
zsUS7dvoiG6N=McJcU{Vu1CcsuoeJZ<A(i|K3-waRNGQ80O`&*9gH3wt5GMGRbUWp|
z8l}HcJoC16E&=aIS3d_Y?n<rC!|x`kH|31)NuN+gwpIFVJS6W+KbwojHYwW~@CVWd
z^eOOmsS7=7JEYU-(eY3^g)YlS(nmgUty5a?C5GK4{qX~cbW3eIA=t;#Fgo<xBQ;Qw
zbFXyPU8w1kE~9GBC(`ccpr&8?0_C0tq^~al@ToL14uC=F^Ay+^l0Fy$8J2b~Mc*@N
zAH^_6q_fRXHY$DQ4l*X4T@FLz(ow3jn~=(!pwmHi!A3<qj<UtH&vBAf(sIOE_IMPC
z1F`^G6uHQ9--J?E*{A8~bCZ=Xf^K(NQZqz6WO<YZI4IlnHY5+pjB8-xuq=gYQIE)e
zErrNY*>`jb$x}9550PWC2Xg^9E{mlomY0lwn(jYunJ^N>N7j%FazfTX>waHZb~eWA
zCmV~#(EMfIJ7GRR_SYD+1<GEfM@x|GGs=FPl>HHfzF?V>&S{0n#8g5UD*J=7reU(0
zk6|!erla6pgly_{NJh$-y}(7uc6U)NLA0!%PMF8Y7ShfpRyGg-HF2`{zXl>+RzR=P
zQ?g@hxPMyqE$z({WM}=MG*Kq)$0(9yv1#CvWeH&*XJp06(48VnKL<;xvIvS)rO7OG
zH>S&aDVcay_Rj>gWXNuRN^yov*_}L$H%rEDM`yO|8!8$+Cwr?AGC8u1l*~9Un{I*m
z3$khS&GcMZr4O{_$>OX4<jdAOLb5<6{R`d~%D$j$^^)xV5jb;Mwp)hAV%d)rohgyc
zFaU5x7JLGIrLy&v=(Cl{Y8}vdRrcmBbe78`C(&6UyFg33O4&HwGF7rH+O6SFm0i$S
zEqkW|q(-)cyr`84C=+{K=34;Q>SRy)VE%?IC;@<ancHKyeN*O2pHFL$g$<$amaO}8
zz#C<5v?sr9lX-uQ&O5Ssv}nF7o1YJ0lk9l~oN1Poy#}Q%vPo+|?#T|Uf@G_V`xqYH
zmu(Hj1h>g<(e3a+w&p{4(Jo6HgGh(W*$W~MWg!%bcqB`wKv}1({{J_g%+n1b-Lk%R
zc=1?f%P9iwk$p=aFzS^x(v{RF%cDs36WQDJdheH|Oo6rm+1KBLdnyZ}`lLbGeX5uq
zl5M5xj$v8j82o)EtLTQZ5t-f!$x)fZA^0>V`<k8t<FdEkg3bxq4_x3J<Zn=B$5EbT
zqrIn-Jh2l_Im<Vup!I;f#sQp*d@5~EUFE;g#@9_g_75h(UG7OQdk^_TO79+&XI7%|
zko;v@l^m9DoCWw1xi_VwkIG%>$c?9b!x}UmlUp{y?s56GUFh?Y$Ib`wmM<NlFqV&e
z^;~rN$`{bx;U{mW(j0%eGu>PP@_Ba99VoXy4-zDwx&)0U<-SyM6)aDqbGIS#Nej^!
zDxXG`GGX$fXmH{37pV>_LO${VL?Y$W$n7Y((+XIKmd~OkcZ__}ZrTIJ%ExHc8YiDA
z!|cV&JH#0FDS7?^_;gzSFYQJW<lXrYNtEv|0+%E&?}JFP{GT_V=8SwRCFxS+OnUmH
z%8#^RXle2q%95qa^LNAGS^4u6=+2O*p93ya-cNh%EctiHdEu{Y<Xh=aF3-syY=@d0
zdAS2b&&%(Vi3{>KX!n&Xe|<4T^5ot}z~##y-o`)+<ol^Es!$$#9i&M9cseXyls`|4
z{7dp&3hP{!-=Y|Nv3%`20F=nz{|_Ri@@-U~UM64ffJWO@`4&n<m&>o!0#PCVmUcRo
z@=51luuA@13kGvd9&-U)wOsQKxElFg`eAD2Rf{qD>+&V>aI{X|L6_bQ`C=ye>g63H
z&~j7WPrLF4c?0d0Z^<|O1wf<x??4#3Ess+JcgH4oc@M+BE03kPS(AM0SMaS_{@oO4
zYmtZC0PvoC(^QaF`J7MDcV8Y#JC!zhHznL3$Y+g0Tf6+1>(JIAms35|LwP<$&mPH(
zo#9NU{BAi&m)w)$-QDuP=y!cAcmDzwdgL~yCx+H5PyGy&(I@YwYyF8_Q4F8@<z1_R
z7?5Y21LCRNGZJ<O<y*%fIV3-^6n(?;9!lRole6YPWJLZgEgnYY2RFcrG5N2%AUQ6d
zp9_%*`6~_Z$wBd80UUKy9Hg@x2Nb((|1XtRFaluERWV~Lh?^pd^8W6Mua<&%D6Uc5
z`Jlo*5e^?x>^}o?SkX=;2}cy)i@+UKoS@K{r(zxLu8%2ZSAZN>c=<uZOHub5CeK^3
zJOl=P6ywjs(G!X?dYkzwUiYOvpr7JLI%MvzkRC^CfPz;JnLx$ZJeUtsB$k4lRJ714
zI9Tz^cjyaIgwYZxRB^WlePIe4<<P<vrL<CwP&EDpWs!<Bx>KVR9aBM~74K8fCq^-s
zo_4W{?>_-NP7%6k8t%V%MYa$wo>Ht>2y$BS#t~RbQb-p<O|oM92SA)r>{^J%6omsR
zO;wCj)q0x3eheb%iv3EseO8f3r6w7Qx<rsnMLb<)S&Etn_>`@<L=V4nifdbe%TX*^
z1#({T4JH<OF2xu0Ov+Wbji5D8@$LbPFkdlFCFunUf4U6|6?>@Iw@C3>0z@t<@=`Ht
zmlSWuVb(7zYU%AztZ-#Pq(t$W6SymiW$S?}RqU$)piIG_JN&BRiVh;>ipDo!p+ezm
z2N7GP;=})k@)g^5qVt;KA+5Ko6|xApU!!;ugT`9LZ}beju85`6mUW6XpQ7)ELPRl`
zdPOUR_--mPFJWdH6cLmPyQNr8p}j_h{cVWcR`|ri(K`z7qfmBN@s1k+O^Tb8%WYOE
zHf2GkMbT?U>pex+^Dy74=%B*B`wFiU=xbLjJPXkd#S;@I@u9+!1T~KowG`s(RMh?s
z(xq_soAUhRMYheAz&%l{SPb+1iqLHI4JbSw!u(T3J4I{<6?If_Hl(QC4V}Y^*)t*X
zOi}n4WJIB$)4QXJTXYIyOfgOcMdOOqJ}^6>=%RW=2W1H*ksOuN=sI>%Zlq~;R<3^)
z6LUZ*wo&H8MY)(}-BmeE1*&dJ#~SE%S7z-3!b3T0I`9XT|4`xOA!RkytsGY7axm&6
z%75tG>``SBEtEZ#dui$9uRQJpy8%kU6p%pW;$I;dq-4{6@uaf*N4OTOd`gvgA<C_v
zQq(+Dd5fNGVajux!G$Yjl$woD%8tT(r1B%m6-Ften}LW{ZlVQTj53c-1;i>_k}--n
zrQ=id#VfxZLgOjrzB)K_TKO`)k`t5{eg_~?xst-NNy?H};bF3pwHD-z^0&X~WJZee
z3o1@dRW|Z~Pg4fb;vrqx^DDTs%08-4%TP|I#eb&q&K{5~Wp@%pvXx(aPWOm%sVhw6
zD1SQ!6X%s&y5TM;^S*=mT%{ic<MNcF2ho_X%%+EQfpT6V02h^ezog2XOUhwCv|d(T
zqt$b<^0}>0TB2nB0sIx^mObbzReCC*rc8NmBl@l?g|xP;P<BxfLZ#AhAGj)|I~||B
zrd)Ofq*{3-6((wwf6-^iYL&wS7|V5~l2ZM3%4UkF+)z5&VJx<KWe2?}Zz>nugwh73
zH)ZE<DKj!K>_(;NZ}i<&&ZcK?lX8a&q(xbt5Bxplx=nDVRT<n5k^9QclzDGc9=E{X
z2g+4B(9*6fqM&q#@~9Qc9x69eRm&sgp;K_JQ@M!-*kx0G5eS)X<u_Eo@>sd49!h(Z
z!Fu@CtDHi0n|;avx`Ll5ug?e9uN2bBn*n7*5y(^Jnlm7S%J2!8A5wnz0bCnaUZb$m
zGv#<I03*uvh0r;wyhWjoF=hM5P(7}^%*CutC~YcA2{@{PlhNs<3Jim&v#OUOe6Ff*
z!qMlZ+FSzN?yA2JzzYx65(?8CRBfOr_#xHj%R!E+7E;xmr^@XWh#XTfet?L#>ejcI
z1RvF>B@j8G`dtFfSJg&8p`R+M29o}&Aln>FX@E*j=Wqg5FYblGAl1Te;rB_^i}xTJ
zta|4q;6qeDS3x9H<wfbaFjbBhxNz0RAE72fCGUr1q^j{lz@t>9_d%jnwyPLnjB0f-
z`eId|&<i?F6)S<Vc-5}$=sTrSMA$%2tLD;fBSAHt&K)JHil{~=N!1$z*OFDM--a`1
zRMDS7O^QmSL1U_F52atzRL)z#rK=`w0(VxGPakN?P%VsvvP{)iWpFf0^*Ke4vQ@EK
zOwc*iv_l{{s^A9bJg*vjo<53|r&>ZG#eCIqS~wP{Oz*&aq3Z3gK#ElA<<NamHFyTx
zC6#>^lwMYG!r^GK%8QDcOH}{lL*$C;A6izGs{W*9Mw#ks9mrMH^Nk?os^7VQSE!6x
zuv@8mi2~MDs&AH1M&X)@ug1`-RUw<9yGHd*4wTla4*iSyx~}RE2e3}{W+=Fus!Xa}
zY)~bwg2*k^eOlf$sxD9k%x%>ydfeSnjZrz+U6rgFCYn^$bhe;b_4ObI*sA(#5<I-G
z8li*9ZK_R&A!2*1dVLXe_o(Wpfb^=;rvl%v3ZNA0fGYhJ$UId&|0VhcRW)=nV@Rc-
z0P?U(I2+ukilc_zG1XjJ(2T1>X=sk>#Jw1{liKTbXmM7bq6F~)^^ATH7xh0sLYb>N
zn>;*bQ~yrKLXWGL<l{c_QZM}o=DpP=bl}KG9djO*PN?T>N1w0yHL67MQ}3kcg1_4B
z7EA=FcfAP7K=rzl=nGOu(a!dy`V$JO1graRqcKFCPg5DDK1_uY;p#~x_zfb|e2QO0
zs%;rmln|v3Yy}&w{*InEaq1>70OQsFTtMF`_0JsiomRKD!qEivdlWWGR1Z<jVUjw5
ziWHO8l~*8gMlCxFK#JN<0(h!=AQXLR>ao|rrK`_=0+F-orxZ@iQ2XvfU#41YYl2f*
z>W8afH%EO=2+>^ii&RyRr~YI;NWMC043k)(UiA;SLUrGL0E^VmD2sYg{k<A}m(*{3
z4yBjX#|Ho}Rv+tyqb2IrV{r6}x`9d}O4aYt(zZ-}d>5wjs(SA_0Ls;0yVxL8p?;Y*
zLY3;-UjbjGt}ubSrf#W4U$r{v7vQg}Ga^84tJQ1Z?;Z8l=P>%a>Lp@mYf`)K!O)u3
zS91VwQA=9DwW@#q0e$z?pWcLIo4W5a7<`~MQ#hkt9lZ>sLw#6C@4tuY4{5paNUd-I
zqD%cXMgP0iVh=d{SY34#T#x#PFmS!<ZK*Kdr~Xw5rBBrCt5Djnesw=w8&KyR1@}}v
zo0i*y>ddW}nPIgD-Eq&<FVIV3ME(74^o^=RsO)Y`9nPX?%D8&h9_XG>=l=)dpsAz?
zt)qrZ(FrHbr~!Cq&FEhM9?-0y>2lG`XonZB8refAb<@1H6W+UP8tE$Y&~O4Ec~G<K
z1(2f}XR1CurfD32>f@S2FJgdR8lT_L=dC&KfJU2-W)Fp%PiUr4iL}3F9wli4G&d=z
z5~vAaL3fbmr4P_|QX@YHV6f)003<|{O|i{T%{z2chG}*!ftCo3nj*82nrDw75~bM~
z1ZB~h=rw@HXkw{sDOS@s3b*4lCuwCJZ_@-sLCq;m`rlA<T9f-O5DA*kra(=iMogy)
zk~Qb(NpVIaq6tpX%vlXJsTvD?#vx5}g0@3vHPh+F%g{`s$Zn?Qz&R+((j3c#NVaD0
zDd5g&a_)i4(NvJV3mPG%k8(A(+l`pEJk16XTJtq4SHiaf%`~dfDb(C{L|>7{K*vN%
zG|QG^F0N=UUP51~=3^(|%QOWP)wrtBPDWparkq~;m73{P6k4Tmx`DnLjfVj6T1^+F
z@~&%gJJ46B8KFJa4b2O-O90-~#8RlUK~q9|_gk8E45+!Iaeo(mcQvhM45mr5cmj5t
zHOtRHO^fDS0RZ<jFU<#_Rb$u%$u`Y|KO`S$1h2thyC$X<eI1&c6jXVrDWpaFBhC37
zkWLMQE{HD8i`(gf>eg(c{8O(claj1`nk}?LeWF>ef|`DfZ8dZcXa-x+_f)fL9`Hk&
zRTB^y)*PVPglC#R7C~f0GgpiW9@Q+`2;CE!`a(!LXn$V-;;5ZE8;wrdA_2U2)}~Ng
z`hd2|hcbGu+GDdJ<EA|v0OGFwsvDvn+P5h-b5LuEf#?x!$s;&=RJ$<^COoyPq%eO>
ztIL7NaqTbmAYR(7ZGd}g%P3Liqn)URh@ZCe6dL`tGAiE-(Du@AAE-SNhsGdn=`6bc
zg0*Kofe6ulpAQnM{U!h;T-)&)#v7pxx`vsF)b8-W&lRP0TnF>f+R^J!6QhlI4}Ec3
z5uF=~*S<9k22W}GR-*B=_AnhUNze|j0xnTIMo;%-Z2`UM&S-}yub-m*oEDX~RP7H`
zsh6hpq4~<t9{m}!o~f-gK~0u+&k{^<wpL9d=d@ct20lmIO?J;~Z-m0b3)%!q-sEaW
z<KT9lmO(+ne68XsoGH-$NRjA5?Lo@<7iov782qAkaw-g6(w<s{zRNakls!xoYtyJU
z=!$kKZ3;`ZmGq02X^TFEr&qP!v`;SA?mPmK3hh_n=&RH&JOq4|HhmSeUDIx(Bd68c
zy$LX1qrE~w*jlaoj{scP%4kVmr~QeNR5!F8^gZT!?RgoTxv90?r;S*HR`)T~+|m~F
zV7^iNl0C?6?H?_WxvMo&sIp0Wp7NQ^+OW6K*P>0MB+5PQ;&BYERqJ&Pqrb0pS&P0l
z?M@0EJkU<I1H4^3c?haIv=#KOc&II*laP<JSs?&)YUlmZfuVJ2&y}LJTf1cz$YX6F
zg${bO3d+&-Y3o}7e4-7dmrTEwt4H6UHjegMLt6eNkYR1)X^>}HF}(&yv{xU%i&5>o
z@8I^BHk87c<Juv=o;j1>ur-@u&q+5P3K3`Bn{=lg(Ahg+x?FTGzko(pT_zPixaqP^
z!=AhD+ClVr=tjPSzXx@(0~qxoT@;ncAJ)}dz#Y+z<p6h7S5IL?Pu+IfDjn0ce+uW1
z>(1%ngqLm+y&SxC+if~H<D>JBgQF*O8}5Vi)%{ruZGO6a^ke($=1?{uK-W$g-auU~
zoh}Q~HPNEwq;9STUIgnhCg4+u&Ym`dp}HfFAQGngst+Vm7f(feQMxXQG)C)6UWa6i
zPDe4ISY7>6N}j~&?6Tovyl&znkW;$k7hwLhPJRbmqRu`5T$1j6ihw8UUibm{G#%F)
zcGGoHKVvXwbs3bk%+MX`!w55VT{|(fEZqlJ(U+}TOS}AYx_|aTS&l9#1NP4ArqcCr
zL1$!Bk!G&$9v!vG)AjE{XTHuHh|U6CH9boTbt$w<DblUq4!ak1vp)m5q}y;AW4f$6
zMu1}7HagW^qMJ{b%oW{~!yu))@JEm=)3s1B-BsPuREU)89+U%6p}YV8Pj%^5;q`}u
zV7eU!OxrcxnIRymbzxtFtI_4q?A7WX)BEeXZiLpRb-I5YKyK(Z)7HOU_oNDzZtB)C
zG0+Cxz94Y7bly}{+Nhgh#ISGc!s+_Gqr-iQ`$qQ}?W>z~)4xPtvo3=&nzj~QAm!ig
z>DE)>X{&BMMNIDNR!@aYn=bGr03Ybiu0~_K?tB)w4qd$`9DS%eO);cLI?h5!cIxb?
zTCq##a027)*8M<lg~z(r7QkSSZbdh^UR`S`xIWz}dc{1^eLyd)ew)tz9vmLf<-7*+
zRL7>R+Mv#vc9G9?Tq<uF(S5cXx<_@7XyZ1f`^XO_#&thaUCe}T>`f?j(4TTgqodxp
z8A_e>liz}e&iWte4SPTzK+h)^{mO2@UG?Ao2)EtzX^xO|*W3Q0w4;Z<kuHpb`k#iu
z9nxQ`2I8=Oml(Q_=p$P}j_OB#0>V?zUI&q5`cwapkm^rTJlsqFIX$br_0MmEK_7i;
zBu02b-$E%3U;W?oHu2N1p-bIg|0>l|1?U^;y%nez+2%neSigtrV#4%aQ29i-eux50
z5&Hd!&>g8?M2ov9eLt;*qxA_CTZz&8($g+hucGRjIK81ACgSzqP&)aP{_Jnia$0{_
z3V##yU()THsGpL6z9jv&X>c@I-zES#qd!$jM`u#>qGu3I)vFnhNz>=j_Ay=mJEe8c
z>ID=U&Cpw4L}RA@eHXZvrB^f2n63Z29(K>^fBz1RIr_640M6?f_3-I}eqRJU%+*)C
z4P2gn?-exW>z`3Px<Ehi8X61rlYHnPSdsp<%jmqQ|A2?qOZtFvD7~zoJr{l#>mwJz
z(-OVnV~AYQ|L_s;rTYEtaI{SS;inkrRsHu=9bK-^^#!0pe<vODT&WKff>h~Sjd1On
zUPkqw)%xJ=0MzKiG|*D3Po7J`+w1yHx;yIhA+)}~p*QgXtk=6ufr*=XK@ji_`mt3Q
z?=AhO-=nWduO5e`7QKN&O84~dA3$HLzLjpH`}$AlI7FL1d=gAN(C?yUV7oqEijj5b
z7Y?KEp?<0el0Evu)6in;(>v0Y|3vRhf$)C)ZOWew>R)rmn1=LMDC#?`PoNdWGkw`c
zm><zIY!DgMFX{$2rvJ<vedGG)Xh}Vxx6(7)!H`Z<;%IP@gL5)mqu_+I;rXQi959qL
zV@NKB$7%4w)n*u~0Ch7IQ8kLY!D$K{_An&T_Tr#n{ihh(A;V@$E*~~rp^}{=hL^WO
z_fZ4;DYSVSIL|@%F~iX>(RkeO<1G*`!yLLGyba$|0@%m!c{v(S7~Y``kgvf!9mDlA
zY!L(QZ?J`Y0TTfR%RP`l!^<?ZAOo8c*C!1b2{0IJ*f|PBh(UH8mO>5oJphIoN{vt&
zZrHR7B*IYf3mPL0t2<#Z%J8-tT(sdxJZ3b;aJK~TSc7pY8siLy1yCJt*g~b@rwkWt
z--4btJemz)f+2|xS0oyCErc^kh7P*7lMR1=37^gwGQ5FLF@!HiW2(V}R(xrO{Zw_8
z4oA^<*0Apr^ko=)DAt{6nD!XBEW=_GyvR08IS1~X;mEg`gdD>i3hd?@>i87y%`?b$
zpflevn*%ikhDS^w3Jtxk7=4k!=^#Wd8s137=r0)}e}c$m!%9btqS&za6hul4Ti!(D
z6$AGvL`n^Q>)}P2;i?uRyJ|?MYWs3SVFoNz7}mcDe=7|`^8v3i_`LZN?!Rk>{V&2`
zwPE=m@U6zs9ssV^uxSAh*9}cnwN+=ha~^7L7=Eb*sW(iaP0me2y({_}46c4qddsk&
z2<96N0nHG(ZMeS~eRm8#2F%4>!+&`YX);_;LZsPHbOU`Yh8(0jY}4-<{>gyBR)c_E
z9S;n9zl3k?2I<?7=`f7VMBhV$KgEe38J1FoZ>J%aQj%SUKdADp+c4D(k;ewFLd->v
zA>k^xUc-i6;Q9<_=^()q!+%r@({IpF=z72~LV=5?hUxb)LAF7|Pf<`aWcYCkM28Lj
z<mofRLi&8}h~c}>Av$VMCPC?#;oZCNV%*Rwg5-o@5iNopj7y(EjiWK^BpRKJZEr!u
z*|?WJCvw2}^d%^BF&0097FT1#UU=bVytyBZ?#8#1K|E~69UEckps|v21c!_~iq{@C
z&ZX<(h|&2n>>f4lSOU(|D0u{f$Bf>zd_8X5{x67^@jZ&$cpF7jqvvBB>ctOp!uUHM
zIA5dw34HQ5ZlZKafHCqThy)rxm!dDo*h?GClSW%eCTOs+s0-RcjL+7iGt@XU28b}@
zboz`#xbbco8Y7I~QBok%xZo5Tqm26~JQi)7Oi88~<HT1WvBu_TXo)j!lRzZi_|8da
zNia%R!fv85*B6G8jNb*q-(=%|uR`RE@fX_&l%^Q>XT#G}W6&0GX-0hP2X~dxjh?-k
z#-U>XW*PJRF+thJs!~XvHwM!#@`7=gs<d;BU6hQ^GrmpNalY~KCU6DD%>95D8k>HA
z&LZQ%Z1i0;S|$T`$yh>1cP<-yH&WuP*f@R=gDElYqv!e+<B5e3Ej11V!fu)Ir4Ep*
z#y4tUx7@gqR`eA{eG0frqxLgMRvEpfK<PE3f!?jvMiWJ=YK(IzPFrhy=`pzL#`nL0
zg*szrIxO5U7E-{n-dOS*74O_M{<0ZtgYi}vWNsPxAAvL)kN*nSZX4gBGL$>UO|&h!
zYs{zJT$8c=GXR>6>-iup#%w1jy=VNLQj)F4wjV+68`HM}&}Qu30Qdvr-4Qgl8{4Rq
zuEV&V#`)05dY}FW`H|7C0%|&qLsTK$Wele;MRXf?jDve@{D*e0J;qudNU!l1dcyP>
z-M_%FpBVSQ1Id14{eH~FfN_*wAWw~Xlt~&iK3WgEL&m9E;D(L6DJuBPxNjXsHe&2H
zpl{STNdPUjF{6=Ei{nNeg<U6%r>Jzo!F2mBv^kraF9UeMbUGZw#gsz<2v^fd4J6%6
zl`L@XrX@}A!o&0@rD+bD-p{~vA2OxTbMCMypN>x*F_qCxb=0Kn0q1Edphea(Q^7-M
zIc_uUbb_dtDVdVY-liSFQ0im)`z@$BVd|#9rLXB2E&2RRs#jsc-?Wv|jsd1`4uT6b
z>F7}yWLo?m8c&)oPXjL4G$RRGLQKtjVK>wiEP_aw>0SDn!c7?)ArfI)M3qF5Cfm?Y
zFdt=FOLtYY>A`&{jWJE398Rq1JS}D7OkWKF5pQzbgT4fl_fY^6O?Ka6W|K^FDY}<z
z%67pVo-wWc1dgVd@?XUWQ%zYu;L=PR^TDN?s$Pb{43nNpA2Ll-cEYtR(^}gq0JBXV
zRQ!6*^r#*t&YNDQ(u)hG>1Tn+HEk(^`8?C>_UOwu#Zvyd!1RDtl^0FFtbxcSQ(8Kd
zUN#lc3GQOkLJx2yrgy#q;EE~hJ&;n<47y><Oi7fUy=ofVfRUA(qP^*mZH3A0Z5XUH
z&7>z(m1&gjgKMVHA(*H(wYLCYW4cSB)mqbqLg25P&VC5VI#bXbxOT&|jq;TBrc5ft
zy=e*?f`<(z^)iUuGM)GW78*^#X;60CR3}E?9n%9!UfwmmIXLBI+)k#-AK+WFsod|+
zCD@U#2!ghDlZxt+I!wYmARd}t{}ARMnFbC6*l7x&d}EjC<+<RxO>tCq_Sm$FGHyMl
zcWJ-cYjX00qkX2bdMFz(&8Da9Q`18_doXCaL3iqq>E1lRhfOPK)Xz){{=hFWVtU19
z#OOy&epC)JW@4`ZaNJa|74A=%=2D);!Tic?5GQla40z~l{_i3H2h3Id5OFbcwgTX4
z{_}5`a5FzW2ouN5^#YLN=5MLa&CA?DRps7hb36?Cm<O|9{)D-GCUp9nrzO%8F~I!6
zJ>Ub)Uu}c#AoDxD=samI&_XoWTt=D65cBRNC=E5|(s`{gb1tP8!_D{U?H^%wzXvYT
zJgo>?qRju%iGpae^Z^=U%!QPSIb%LRU%gH-hdskorkSVR!C2DGj(<`D?5ueP?VdBt
zr{};@rnz`3NS3+l1L)2+x4jId=gha;Fp3;=Um+yVn>X!*$OW@E70TqAmoOocXC6d6
zZ+gBtoeH-K%pnwgEi{X0K~rSjPP>eY<{7j_ykws6f$GcVn&0Wu)Wzm1ih!4xzazU>
z%roQBS!(|G0PtnznPKR=YIfWMyXEG#+0b2KzCa1xO7n~%G*+3rsP^@mdB!U+QEmQ+
z!rL|GU+5`YYql>$-*xjOiu~1?%P4tr!<_O8`s&Sm+TGZ0nqL_M+hG2Tj<?=2pP-HM
z9kW;m-FMAvE790wKJXnxn$3%RF^Mha9uK&7&-~{rAg$(xOf=p%Puc_T+sxbkL*oPU
zGzZK~yLp@zX&vVGC@=KTe1-+`$o$PcG<KTv9H6?(X8u<WgWcwB(J=VfJh>m1dd%Tv
z;CjtoZ(yK(X6M<sI-i)u`_b5M4yp%!z`QF4xToe9X@5UxW^Y5^koniQ;l;4I{RIG?
znde@`ct^|*(*YPYKcEjrjG32>!L@PoO4>9`m~9MNxH?!Ai_z+6S+D~#PL_{$0`F`&
zwgbQe7B|XpxLD>=Al%iWrOm9HCBYkw2Q6QhVHAff#wK`i*fO#fxFeRYLV-JK>85AB
zr{%ylh#a$=q_bVeE!>45UY41Y0Pwby+r9?E$71{httTvIs$TQ8H2sC4`B}=JqR-#b
zO{EM0mUU(fCeY%NipC&I`FxO*mNzJW7HoOV3-A!j*kVYATEZgG7-re_{~WdD&%fbC
zgyo(0;cuj+Hy*es%R>rDMO(Jl*f6FT%jPq%8*A~g$8^V8-k=3<yrqL;LZ>V{zK6(Z
z%c+mhm|#iU051|PE#Z(%vZT&~qsbOYD0H8(+$n(h6pN6uQ>m62bZe(sEE_@6E#0(x
zJ!|=b4U%D5Ne`$@%guM`{>!rP@1ix^vS<M;owGDQ1U|>oUI6aA<pWxzU9dPVfJm-I
zYQ(hVS;DBiHs9i8f-?n{H&g%=THIfU`6A0JHjMY8C79lZmn`md9O|;=6MK+i%cEB?
zq!Nn@l{Z|mtPg%^(udPaEmNbQt;}+n&fj0P{7px$$}JAGe6F(0rPy1I#q9U~GCZuO
z*}=pO%U}r9)LS~9z{E|<nN7eoSln8{-LmBU3iFMY)3h_bZL!fIh&z^_x*&4b(nwE_
zCW{Xh7BpKn{R1s6md{)vdCxMeg=DK`IRyglTmD%GWo?#W3e-HX#LUNZwOiKMs1&`!
zQm_t)hn6p+K^|ESjY723@(=w-YnNp;9fRz)c&EdQ$CmH*!C;SN$(OLyYq7lokv@xV
z1l$t~lb$pEmT6Uh4_HDAz&*9h2n9E2xp)hzhb((2$~<iO=S}oIvy}b6_I1Q!cOEjM
zmi`xEV$33@u+g|BxDJR3OA94W9IU_5#{eCzZ#x0+WUbO+OfJ^o=fJsI4R3+CSx<ch
zfV=hGa`bsv?^8JOpmhcdjYq6ywD3D>9i`x+r`5FseO}g~<CHD+wmzN-*2n6*4pVx<
zIvxdWzE;%`X2#FDG#Pz?)<HTB6=d}u0e8~+F+DGWtut4H3$fZ$wLz%$zt^EV%o<2r
zh;Zv{S}{ggkJA%8(mI1~#whFH3XCk;I*C@lF;*Lksug0bi!XqUv#KeMA8+-LLG+Y$
zssh74ZDmwJX@d34T#P=^8v6kFB<ps%sgkW@h0uM*I({2migoua7)-V9`U@n@dO8-k
zbZZ=KfX-S2-o-_hVckMMVWxF6y*IP04=Dy^%eH=LhRiwZSz4XtSm$4X=y|I>t@ZFy
zpjTwB)%P_t=2^dJ1|r}3E`8Om!1|FdNTF3A1}U=crKiV5>ppshU9$Fhq4Ba+Q3BVB
zt#=-vvBa7{!PG0(f9VBM3LHq8%^LjwZN7B@MUTp@Zd9dIVZBVZL#1_Y8MrFz`MV(3
ztPPaNt+w`rp|8f;_Zv*qT74^kyKem@4MVH5js~LfhIJL?E9$L()}imF)$R*SWrNj@
zuE1N?k1F6yqjfdi=(nvlhduDS$-15@)S9iUsk)=Znn7O?yJsz+;B%|B{5bBF`&PRu
z;M=TgpTk@{ux_BAqTM=&baz<&%b?|<wf|o<KC(WhB}}K)eJ+%BS<ALUS+~^~0cDS^
zO}=RCv2rMY*lV3(lf#=nD=Qo1iS_CN=<c`L=+jpNRtr@mJhkd54L4{Vr1#K}^*F7w
zhph#NK%QAAQEYR>I<E`3QENdxB*&~~+Kr7{Pq?CQ!utIPa1Qo&ro$&k`|;=Cuao@}
z%9uIZPf4Ix-2wY{nhY2F+BVpAwHMM}*v)?A7PPtBOXFb4!+ynLAP(B^PeI=ydo9IZ
z4%<&$MdK0sc`IS*sJ(v#OnBPQpiK8M`z@8Qd)!_W49?5G|1B8uw(p>DlaKv83VNNe
z-}sEOrM~vrc@Xup|DI}Y{q0|-#87~J0PP3@?YEAA1liA^Lr5p>Z_)|eVEfqjVKBr#
zxd~jT{c9{Z6J~Edi^g#K*%43{VPES9Es^#Q3n3C?-$4P4So?h1tjF2kqh<bS`^C7?
zZPOF%|Hsjl$5mB5@wCWF%hEKn%u37Dep$AwshMVJrsmuCec#_}ReRtDC?E&|f}kjf
zq9D7hf`A~3A|Qweh%AaAf~+Fj?>qf9pL5Q9zcc5)%f08!%(*B=fsbWG(=#xh@f*F&
z6Bxx2@H>%llA^y!3^r{hlNmaCq@^&13gJu|gWZNJlg@aJ0(lvX(^S-z$=FHD{47Q=
zWn{7$E^`4m&uF58lN`p$|H^6^5%hSy!0=lQL(V)#!b&)t&v>y1GzE-}+aWG8K9fPG
zkdb&BV?_)rMRqSSey3{JV#fFPz<rtFk_G$~#xRwil`z^VNp_XdIs@VwV+Fn7OBu57
zaq+G*9(7>$WehpRAIll*o`W+Lj7kkuZa5iJ=rfCzjH47Zt70Tk6z3*GNC(oZ8M=OS
z-eMg66o?weZ)F&}&9IZBwG7Ymz|}F5DS=$i*g&<FcNo9Xebs;~i?JrgJ4fMtGo$J_
za4n3r?}76kBX1qVea5CBxZTQd{zN;V2aHS>dfOO3P#CnG@xpz0`jEk<$5sb}u@mAE
z<H8`O-O1Rt4uCGkm14N|m{IBnyWNZe6)g2IW~_o{FXI*3?)EVhG}h1fodUE2j2EcF
z`3b{A2>2jl;z4LWWh`(;V{nKuMFs9*#?M`#8DX?+0QV@P^JVz$#@u`tsymnoRS-Lw
zYO0#s!~FU#ChE={qf?w7%x8}R;K}^vGjQ)^9-$2VKIVyTnD=77L@OC@<}LaXi4RjY
z31UCftqYyL%nv6xq2tFap9H%Hm>W&_nf;ls{RN)_n7_|~rGw13u0u7DneK+pAm*42
zBA7Xe9^r?WUos#<nEy7xU>LJ)1I&jrb3DL#glXChOGlYWMyNzEc@$JR#@zZ6=6Res
zaSH&E%um_$_ZP+d`!sY;FeUF}hSAK_ayWC6IeZQ@r<l7IqBDkR{}A}o%moJ^&M^CE
z;Tg*m&WB1I^Yb$xJ<G(O2>yPUzbu1?3Cx#FxH5@M-Y7Jam>gQJCo{`jp_0OEhypH^
zIRTF(oV{XxMjO90=9}T@O=n)y0-wRuPy{`b8BfWsEar@7VK<w(FaRp&na|#Yzd1}U
zCD(G9eH2l?z>M@lXC6~TkBxk0qXH}i%wOo65f_<r&qA}1`PXU~Dq^n8M(YwYfim6B
zV&<}1a9?IlT#v!4%zBC%UuR~W2Wc7erElSIIdeL#dn=gbbQ<{v^XngAqLNu>L1z_n
z3)OwzWOhwMXEn361#aJBKD!!YwaoFfgsEemq)MWCX699J-eF#tfzAe|<tfbHbuv#;
z#d9NbU>$Utn728gX=eHk;KyrW^5}?cEAuhEjvg>q)3UCO`7Zs;9n7Uv;P!~Q%oqN4
zGMDTITQ`$M0r(!~!kG}gOxKlA8DPre!TE&w;AOB3GCyjEhr>)p5ynQC&Ic4I8f9MA
zz>*tlDFZY+STF2>Gdo%BwNTx|QkLOby0hM=%2E%OpC?-TSZ6!oj2BCB2b$ijb1%W5
zFY5uVCjD5er@-I=)~bGt9b|P*hh`va$*Z6aV*Nr7+YpvWi?LAFPG=j~4zo%q1$Bfq
zb`HHqSu5z?iC}%a7KljJ;$P8<Vyzef_X*a)7ch%ctkeoP6T|vR2yvRlqhi}QRu-Lu
zIm_y&4^hOk20YM8Vr5!^OJ;pU5Aqb&^f>^ev6?1eES+_65#=;9SWi0W_F`@LZ}ZJ^
zP~}w)>xaW|CXeNw4DNi^habYj0u~;-xP@5B6hXhlT6`GJ6tm9$ceH_JoeP#qRwljN
zs#w3#Q~oAPKzo*I)~~cHy2W~yj{ViLKKl)3>sU)(rn4XQEWIZXcUUq?hBUC!>1^Iz
z)?6xuZDb8n7^aC8K#PcGR$U74Ev)Q6Vg4R#)lRhTvxdF^`~l0O7_BzeWfL^pS??@^
z-G{6#c5rsEE_q<uovhuHF^MkLb}HF;%yK_Z!Gdm9=^Y??ShIEL?PY!THh=>xs~F-5
z%g_bVLDo{*Sr4;Xlb|`mau>khDC?`)n1w6*?^590*hfBqPdnIKDQ&Woo&GJxcCoLm
zz_j<Uv*^5#J6l2Tc@Or)MG&5Bw`7nx_p*zZ0=SPYrs$Iw`-@-*Z+7?`;C<M~sN``!
z+p!<Qm#tX@FZ|fnFQIaP9q=tk{n@W^K@-46`VBW5ds!V^3uM0;2fIP+Tros2+lB6~
zLu~h{7z<&)y&IZg>^!<>!kz5>WiWq)ok<CgW9)04Fmaqco^}M0?6=;Br_pTX53qES
z{d)lLr`TWV!FGnt?8I0sd-Ma$K92468CVk7=YE9SiEJ({Uz6DJlt)Wt->L@g9Q*o8
zu%xkHp{GwKdltp>ve?eUM}Wv?r(cFnF8gze#9d$yQm7=4z58EG?IL?8#q$c;?(}zG
z#GYRa%}eYTOW{Q^yXO^jUS?~xaOMiT(g?B=_96NczseRJhNWxlkLkorDf_4IL3W)j
z+5#`i*|AEDRj^&1^bLR;>}*P1RkEkP2vNn3r%35dc7Y1OYWBJvP_1F#34s^4*;UT~
zU(3ElZ;(1Rmog;v?92k-?yxgxtJc7lEQk5K?3U$lrjZ>J4+~A~M0!v(vzO6yTi9QE
zLA0`i-lo652keC3V4{sZpAJiRu+JM|_YwQ(Ewnn>IXw_v>~tZxAG2dVfaqrbNhL@<
z?2q3Eu9y8~KfLH;x2#5IKRb3R00Zoz&mo?$w^AYDAbXq@Q+mptqDE_o9Zsp#VfM8V
zN?(kyqa)$|DBHdjVvOxiMLe#Y_XU`R8|PFF#178KR7ty&W1WbxU7X3ZmDtU>PsJsB
zIOplAxpVqo0jUS)%q6IJa&GV-_Hy#SgXTWYEI+V#ak9w^Z_Yl-(ED&oa4f~?vY+!3
zJ+FK@QJ3JGALs8$5C=G4(XP&)Q+*5b4dA3_0dbJC>VFV{9G7U&1abVRDl(Wemr^5#
zILD^qB7|^WJO#U<oFa<u9p?N<1wLV%CqcL};hc0P#1W2&{%((Q*3h>^oDrOmpD~ML
zoCOY$9_PG5TiZyEOCnlPoQ`O;PH>vFFcHm}@*Yf_<n&S?{uJlqb@*XpIMqxTJk1%H
zjLtKhHMh_i%Ta#<?l{g4Ix~5ebACR^;yD_6&nIyH`5#ykISP7#Bsn>)WAHSYGszt^
z=QzvvVoqtCy}v`GbCgt%pTU_&58X`82N`fbi?fLw&F0*F9^B_SU(g~ghw}&h;pK9c
z<wElUXV<^*H;=O{8Jzi?`)klD;KV-%m5ZEDQ@~Ql>7%q(5yyEo5#C(l2q_9w%z1Vg
zgO@pzW&(JHlS?mx5>CT!P`%1on+S1@Q+XAgrJO-7>|W<I)5+;F&P9q4m2)2Xz<dR#
z;%7|l24^1a!zwvHQk7E`CxiC8H#yS>F;>m_h3<=6oDe5ns2a{}I!Ah&^VtB{YB>)m
z_glyL%M(5|aPAqQa+g!T7%Gh%79D$U;@qHumuAk5V3=s(M5Uwi9;bZ(r1v@g6qjq|
zG)=(R1J1Oa&}`$p6@t!o&O7tb`H<826Er(G_5mk=k2o%r9Pi|ONja4+&Zb51;xWf%
zH&nYh=1uUshchb(G`*b2vzUD!XO|yb>*qXi17Lt-u7`(DID=HgGst;?(xp#18C20a
z#0k;hiVkyv7{HBiD!u{dC}-^~h%wH0XDC?b%6)-;JU8x>{cvgrcZ@d5JGr)BfY`--
zV+^g`+@n;(u!pO?i&?mHr(T6m9^Ac@aq#5k&@*f=w_F1FKJM;|0C;hqO#{H2yVxI=
ze7OI%z>ED{-{t7^<<_plbp5y!kdAh`9N;c(gN{FU!wSqPfSVW#orBy-AA>ZIyK4!?
zg1Eu7-woz=Qkldd?mDUy3gP<l;9)3t2K@$yxhvgaB8;0v#S7uwZxGvYIl`Uy4>XT*
zE2&;Pg1eNGAjh~-o6tJW4WP%BGm>k41~Q6!avw~b;9j6ovuLhmB4}c`pHZ~#G}rVw
zI?r&G^iis_T>kTzc0AYT6Zo6JEu^Jl8rLlXDw*6w3V3F5eJHb%%^k>rIL~dNokR{-
z@-{>+_p^E6yuh880Fme9{y>LI^SR|EAic=7Uq-8tyXi7qEaD!D1^yCu(Fn$hxz9J_
z0$=9t{TZziF1rt!SGk`%F~e(I#zmMf<;KzZkn7wO+EtZtlPLFE&Rs{zj0&#64fDLg
zokTmBO0Mf_Sg7JUl{<jA$ql7kcQyAr`j*Ts?vJm6t%f^eAI5HT-=e?2T5eeZ+^^%F
zrn2pN?w&_z-QixL+p>Xs{}@Q`a(|(qb0gQ2>I|B=e}4mbGdCs{mRh)HXz6s1+p+_#
z`&?TDaIM^jPEV*l;Qsw9nh&{AlrHVyejNqXM_k`3h)%BNI9%)Eev<^Y$6U{0w7R((
z3ODy~!-oOr<qj>z58KC0Ek$QP_l4h}GQibNfKN}juYZizAa_9>X7-eu_&;2PA@1vx
ztQzM2*-r775pI?jERAv-c0-JDZ*9h)EAJ77hIaCvQi@|2Z?+O9cJq2x0<ee2eF<ak
zyie}Jga>Z}1++bRTU?;Im)Ao@aQk@Gb79Gg_c|p}ym?<e2jPP;;P&&*P`QpTZ}Ve%
z|M~G&P6Pe`kI@I9Kkpa^B7pbDN^l?K6`DaB$eT-l96>x2rPzacTfPL~5U+>A10lTK
z|D6=#*+0eDVcv8PSPJ85C`f;l_dC_JMetVZFm{Z$^B%~ec=P{+IKjK{9hHwp^Lpd(
zYsc`ui-yi=UX}pBGrXg%;6BTf-auzO@9iwK5_s}p%qf}oF0GeScwMw!PUV?<VK9w%
z<at<1=lwMi@C;u0uP~9xYo={N7H|AFU^&m5MaK_vc>Sl*%H`Ejo$9<i-VnuD@_B!M
z2+{)H1p0k1^3GBjOd+p>ey&TrSIUB7SB;zL)V&X#YrHA6$Smb;Uk`%oyseb^E9Z6e
zz?%x*97;Ie;O(ylu#&fsGQm~6qK^T%$%|Qm&Kh1A)u`O&U81LLEpG+wuIhLj%3!db
z=S91fJG_Qa02+ARIGycsm#2RnlWFALcGAkEjd$t=AliASiXa~H<h`Kj;Cb8w@DcBK
z+JtxUq9{N0m^bh?THU<P1YCt)o`t>+G{7@%$Ji6zLwXGl^6pb)`6;h26=OrZOe)eE
z=5bEI(GlLm5wu2mQB(#x#@qTe1uI<nlWC#v#?N>Sh#mZ$o6y?B@22;WJO9~b==9(p
zp*zBpf4v9zz5LS>xWA8INGVD$e&a*f_2zf~1e_0FMMeJp{I6$01n_HTK=UA9OXcx_
z{CB8WK8P=+^M=9vpo{cD%tQQ}*tNKX@PD9uX()dy?Gcaiy(vl`!C&(!#4-MwOxQin
zZ>M)`B!B&7a7Xb=XvKSipL-i7qWR5oh?D%VyO>%me||pvjpJXSG|^f9nwMZOo*(-y
z%qQ@bCODJGx8bOq(<O;Ntq8zm{<OOwP2szZfi#UTe-0v@KS;5^4F2v!jAinh7l9^=
zKYsyevibXdLg#sY<4$Pi@ZXAn!Cd~UcL2D+ucNAmJpTXQ!dO0kW*<5)@y93@T+Gk?
z4e-nS`_XXCd4<1|%9=~~8FH{)<^M!ap=*366&jTC|8)WBb^gg>uvPMls6?QOzrPfn
zH~EDWN~`9ljmLa%@n35NX${|n>d$WTLn+}{%fC?o6LowECBho{&rnH16JMDFvS$82
zbikv<$q%>$d5>Sa4&pw)lgi*)`I7|@5BMg^j<@k0ePHY4E2y)Jub@ojWB%lDSnB38
zDHPYkFY1Haz5IP21JK9kQVD)P|MVP)0sgtYF!+?e=moTf_${a4(=h+T9|0KQJ7;_f
zwo!h``_LKVw_OCAt3XcCNjE{n@6g#H@TPp+PQh|MxOWL=Z-v+`SU}}Bdj+$PqqR>U
zt_99Z@CxlFy#?<az?hF<!$TO{FUY5w9$&#0FZk;xNUy=QI3NiB683@wHs={kJ6N!X
z9#n?}ZYRJNBJc<SB2?f{<=BS>dIh+{1QYqdhYQN+$m$Wn<|UX#q+on408xVH6c8r_
z*>vkg3!>Q&Ck0<O0DejkrhteMgja#(v>=%SaYo=>53&RSQ{{vki2|iR98MB=x1u*$
zaF@aaDS~|iu#_sOr2}c_1VwbtF-@@71KjC?XA)sBOYqKVz_SJG+R-{M$fiREIfBk+
z0CEL;Ljk`aFj8@Jo<Koo?D7RyXF(JQ{IfCLi-ObhC|Fo1h^3HPksy=e%_V|118A-a
z+$%wIO;B5e3sfrjT?k9p1+lb<C=<+{31`X$6+D=z5O~tZy{ZLo>;dU5!Ba}0*9exF
z!E#&RB7<hFAYm=Y>I7%IF;*{#SP0x5!Fi-VoG#6RTFN@L2wt<J_nx5tDBXwx%{+)!
z!T0eXeIR&DXWiNa;d#Kf3ocSEZI>V<7C+@<!N(=Qbqm_*<5N8X7UdCo1*3FWvrpi^
z177qCJZZf!Ab5tp?Eh4tp-9h=;J^Y1=dj=@MKVSNQ53@)6<l3`i!df&(^k=4DB1}V
z9zyLY;5~(JP<CLiu+##vPq?rOcrW2}B~-kH&sbpBM_7Ifn)`*mN5SbU{E-68enK^s
zbsZ2M_Qg-(FYKpHM}Sa4LEwW<;roX`6C}(y2-0BTpMQYnkZ|E1_#GmA#RPn)P(-(U
zn9z+Lv*E&6Dx^Fj{PcNfMhH)&g65bofv)p$;inX-jTE-hE+<MD@;t;zp==tcPYJ)G
z`yxhYqs8TE;U7A1o)J2w+tC{<oK35=IAL7_*v<+AbO6Q+Q|J+%DEysPhe^V08$_~j
z8<h{F2<^1%PZie9hd3v^@BouY7Y<S7a)$6Ziacft`zh$1C0wKeb+)kgJ6weG!m6dX
z%sIkIQ~;eTjCWRI@PaUy)@*q~&hNPR`NChn23vvf(+J=%3V&*WC=~Y4W2;E`h|Ydp
z5*AQUwOCl40QhC$Tnflv5uUgOl@j6RvrxGzZ22F&zb2eS3!75m3(cUuE_Belyh3<`
z@=`a1#}g=&S1G(a1%p+>Sh|C63O}J7RJG9aMa-f`_*M$WZVRWiV4}6cLfX#N3Aeui
zT)j{<2jY(KsT!nrg^jdzY81}-5GqYVZXH@J!bkf+c28KwM(2H@FbvML3Z+!E`#`w-
zBz>r<P574&X3;M6{tP-D!v9fS@gw09Ivdz2JW5BfyM&eW+;}WZ{0k~Q!Wjvm=@r($
z2GJ*6<p-61;r7>Ha6q_b2jEYHZ@!9)FeKdc7I4Et&L6;y2)EHi7!}UnjMkV?=SG_)
zSJ8C}LAZ%_|CfgsJ>v?*PEkTF%<mG7{}hPbqVa*4#U2qOA7k#K-e~}Mh?Y=5!Bg}m
zg%0<MHd9b_pXhaZ(|U>Osf5E@)X@Z-k7zrEc=n4<QC`_s^twOX_7h!P1mQd&;>kec
zFY>m+;Q&!~4NM#qN!G$dpeW}ENP|R!Z=y3;WE6qskm$>Y;0_VZNrMO#O{BojVNs9;
zEMX$kw-Di?)%$=uB1-#j#VVTfDK1HbX#8GSI3^0F<lJ!)m)=T|PEmmx%_vdlDtLNA
zw4dV5(W0p3P>m5?nG6%BMT=>7c1Gm01>CWsSTAtLiN2vg##vF)i_nZ0DOO`L38F2#
zz>+8`q19cI$aMg?WYM&>&`c3^-NRU_sEN|y=S1c=07w%#Kcakkx@dtKmn}myRtL6B
zQTP`CW{Li81WmT+%qEPT7ggw>nIk$!+oN33bNKOGE{K#1;eDRSo2oVPMF~%#Ss*$_
zQHG16@pM$7P}F?@xFXT_E1_~plsy$*6pOwe!q{ceJtsX%uZXr%iB5@V%LmZ8D!MTn
z=C6zT7C@AVs^-J}a?y$xp;93Vei`D1DDDSnR*GJvQ+-t;EoD}3ij=ousao{l7pUA4
zb&SG`8qt)=_|a~Q20SoUD>^zAfI86#J@V^C%c?2Ja!0grCMMG$YNYq>UD0{^=5M3O
z58n}UX%cOu-=|r$?jZbb5p~fQp6-e6Jp;}Aq9w@~YZGltL91P~m`Y_HivC9>c^#sS
ze}eOo$a4=|>k=KK`mx8N8B~YaEo!4Ze2?hkemZN{D{?l1yHE7q7oZss4YULQMD)rq
z@Pne*W?Y1)qD+c542d*q_&qE-{x(!bMVGxWHYQ4?ShB15<Gm0&#2pmm*eMn*Lu;4#
z%2&Yc7F&IxxktR$7jO^pd)W}4;w8!SPuKQ}T`7XHPh3bZRWI?puOYm}j2Phei!W1}
z*;g!`2ZMg%#EIxUAby`#2L9sBbbAGeKc{$Ap!hn4h=RmlkHLJfcpeqL92WoaH7tdR
zw=4l5T--#-+auz6v`siF9-;`5^O!iCwz$W|Ki&p+q<CW?*rLSSYccy1;`vw687*F7
z0{*1<Cwe)>h(Dxv@@et6DWEwczTXRYtaxo7CJ`rI9SV57IAQ|e3F5c=flCz6z(ie=
z#0Dz7P8JvPF{KpoMcS^XI>jG<2VlB5lJ?6P;tzg>-<jf$8sM|UCGP>4Elw>(D@VM3
zDJGLE&ZL7A7sR7~pfgXr;$0Zb7aw^B+y!Du2F41-o9QpLNbI1$;!EOiN^um6A5+=t
zW$|yX!`>C~0|nq$#m*Y~v$!UHQ;ue-c#aLNGO>`>`Q_p-`r&DXcrDec+z>z941A@y
znaV0}ivLc8s1~PD()gD6okoZnaUAXcZi@pbe^D#mN)=7@;;0f(-w_X}G1eenOX04&
z;&|FuG>YX;Dkp0aZyAE67V)}QfVd}qG8=67#i0~~YZvR60QgWG^9aBW@yAMd@kl&*
zJOG{IreaL{v3O<%*t*4)ucFl>&f5afE8g@MSo*|!Olb9s-@F2q0dWS!AqU0VW@DaD
z#V7y!heAW*)LC$GSp4ED^p1#AqJS6^2Y&*Cu9B5hf9)no`5a#CkSv>l)=r6pPHFFw
zy!&6xmV`kmWDiLw)rELUVh=!NucU$^3Hu}-iy*utIkYAAmarc}#Ye(i0kK~)=LLHI
z`AYImV9-zEaUH%LkSwPsqras7CT1TX*-`-2gA(p`v;rkr7vWlvq_+*O1xp(0VfT<k
z@)kNnBoC>WHB|EcOc*>Y>7nRVm}IpcQwo<<y#WhHB%3MaeN>XL4Py}!|3B#O@0i3$
z@7?2)wZ#yT65ADUM@c5q3haa=gQ{DiB^gs-;-usy0oYDSp3Z@zF_QL=@Ee?#gwT=i
zGm>5^=!li{(PzlwB;K@?I4iLiU@q~JUz>qTki54XfJDhL2RM@?)~})IOqRU65p3rq
z7C#`;B>(&b)pSWI{cUGSe!d5Mw&W)LhUX=7@1u1=@?##ZMV=&=3bOJg-}S)lLJ6N<
zpG6WYZ9y(cR#3&v70Imeuv8)mTnY<UB{o{{UYF!8MypKnq8RXUrzD-u1yo9Aod8Xh
z<ZpV(+>~^G2Yii0;s%}D64exlTFDQKp>jv^&RO6aB&$CG+g(X41y>p+Z}h_7CdsT(
zc+o8Jp+#Pc<elfBa!+D^7c;vr@xB0-R!QMLc=$jvJ{c<Q5~uV8nhzzGg=lt2KBqX_
zBZ)T;Y@L$J^v-xJd7C~*)-5?jPqrS3V;o3(C05!I^hw;?;7q?{Pz<{R64_56dm_0=
zsro?)gMva&C9y_agds`BWpEBlhUr!xkzAqd&8Vcnc@?T-k_}o6x=KH>z=WIh)z84T
zL;6c4baqQ$-VcL&q|Ns*dw1!vW(W`IVLC|XDfL#NwO3kTfaX3aD;}C&(yJDb`ADx)
z<Z{0>j+S1&(x136<R@(ykFf*N@$^^hFIB%vXAJ_R&(Wvv4@z_B4?b9GZNlIosghPS
zA=2+|01+nLJOq_+sbx7Pb3{5L3gW0V;Q+=Wq$0XYj!XLnU_Me>L1D=#>8yV+c0xM(
z6~>~aOXxj+Qu=BrTBoE_{)Y+1NF(P^u>Q1k0d3yTNbk_2DMiYr$8@Un>^3-aPFl=H
zXPVUi0p^=7o%jQ2GNcJqkDMtje+8DZq%YD|B3t_Pb7-BH8fhbwBR#@~$dy_Tg5`p=
zdl5vQw00D3=Sy>C@S;F^a1tfUE=qs$g!w|Ll?|ODseu-*m!u9_Arwo;HNlz7(v^X@
z6Rt=LI$)wi`oUuWu1cHNqw|{d11iidmDU}B=5^_M`hI4a^m-mN%cVQ1+^<slE>(b3
zNjHYW(VNn_9q6o)uBT^-^R{%r9f(?~ieAcf(%qD@tCzlX8TdQWmE&NkQ7WeLtS0G8
zuVLEF(%AbDEmD_mXx@`{9s>NnG?A`FtMt=xAblY9$%kl@+CG8ZcIo%a(RwI#3xN3!
zsb(=Q!XxRsqiA(HrGvLY(<Qz7GgKc-11Pf9E&U|~q&?Dd2kiDrzdQ?-KIz7CIMXlP
zd<J6!(tAiXx;&BIn+%mf>8F%zekxV9Lkvk@+ljGZsfkjBBhpIBA&p8SKfnaXq!a1l
zyUKo$K*dewtSyD#J7lT!H?~uDoUX|(S$P!<?w0*Ve`<SV9amu2UAAg1Iz41_X(i<;
zJNX6d?v;I62NU~bGkwtMCHt-vo!+uXSs?R~#nRrxPj<x}oCjpX^j!ph*$OK83XrX$
zUH(DYQYYoi17%5aa0kg|KLjvXHhu@hAz73OB1ATgYGguXFVP{r!?N$GC?`xd<tyOA
zW#7=k^N8#($|fF_MTf!P2w5h*sE^6~slwp6>}WnTBV~6Ffh9^7^A_OIvf^Fv>7-0l
z>;(RlZ0lv{#K@wz0eD*0sKrH$l^u8n2IFM+bAUK2o9G8bqO9e8XeP<h=~<R6`<{N$
z6xom+tyI}c6%3w}eMX72G?`~RaOtuJ`b*D{O{EIiOxYnJ09mrLbm%NwR=$ve_2*@-
zFG4j(Hj$$3xw7XgVg7>bISRPu$!<`MOup>ZMzjiKGRpd1l&#A`XQAu^SBN56Hof*Q
z$&x5QRV+I~r9qcvxoT)$kxhw&GbOSw6QOcd_8gt{xh6~XgBPW;<=A84TMx2TbZV?j
zHmeSZa@j&!Z&%3Przrgm*&nwsRw*l`?*&xLGAZJ6OUC;z=q)o#F}2&Wsw{NY$_~Xr
z)X9t#bgP%uEWqWyBOCevoei>pbQruV%cetPjk1XwaJiag^T*?oI9p_ADcOBbwj&CI
zk7UPkAUb79l&0#E9irgMV_5|qsqB`8&>6BG*+e?i(JO1FXjz}^^m(xL%UqT~49FJJ
zV{%Z&(O~SUY&ipVhh%~0&^at~+l<Z;Sq=q}MrE^K0QHzt_FfTs-Q*w8)@O%2h{DY~
z<)yTr+9P+~gC%$QC-czhA)jA|mZv;wB3gUp`!+-DlOMSa*SzGFv(fUF=g`gKBVS5e
z;{Eb)3Xl8A?^4n40r}h`Q1O?qD#auM<YSZ_J1BPwVqqyz{_8o=1j)<i!^9!^WXk-7
z$Xn?S4wbjn0C-qFR}H_z<a{<%j>wBCM0!-dn>Jv_<fqp|<+!|u7Gja|`6U>OmY-Y#
z_(^#x75$!)yHl(pQ7$|JLrHR1Kj4z(gU*R?BSjucugX+;AHBZM$y4dUnj!y}G6$LR
zO%xH!lG|PaFk7B;3+B(u|DqgHj(k`M?p%4y_b_-tzKjZm^5nsdz~#%mHULl{e~xNC
zF3Q(U2B1j({EGlwlHa3PaIt(=u@lY9@;5(%7gyx{VNks$*L9#(Du18ehS%jIF=&;^
zrz`<mxqNmPfEDuTlyA8qUl0V9O8Il&0aqm-p}5>ldD6e|w_5%g#W8NldyYfY$n}(>
zye+@>F5tEDXK8y;C$BA}{a?NO)<WR#$O9<M-5~#(YHaSxf1$lcqudgW`8LV(uvT<w
zmWvyJZ;`L2{O~=wKkabu%Xw44-74QQ3n~xf-E{K2O<w;JTx*x7`NI2$a^HNkI^<!r
zB!48YZ$M|KTpLI6&o24sb1?r{J|hz}-SRGq&-KVZzYj~j@=dNl^vU-<fJ(o-=K{tC
z<PIj-p2&MBY&0nUunQ_r<)3gtIwWt9;injuyG@4MBl5;wz>Ui1Qwn%YzK&vNu8QZ=
zFt$Una5{bw=WfNhRT$i(c$R)<cg13g!g?q+Qq0d&;j$HMdlfAKP}!%LR|bTa!c1XQ
zZ$*C%%=;+X4uEaHBAX6<`YL9dG3KWjdI{oyB2WV1uSlQ(WT>KQ88{Cs7H@=Rn8I@v
z#=@P7U*ds3qBy-DgGUv@)wl=|iWd4Qk11Xo#zc=R7FD4YsW_4cXQCAIX|;1g5l4Ui
z(F!N!2u~`uQfbgB#p4Z7iBZg>9ouQeHxy1hqj-1*W3h?{+h8|N(NDERXBAy((2Q3&
zWuq{kplFGNr9{Oa9vDnglu;xgSyBBDTuf19<wK+@UVZ@lIYr^`FqozY`~a<V#TE*D
zW+=vQg-WJku>tTbMLn%1vlZXa6a2hl?GsSvD85%fGgl#Bg3b$yZ|U>Kd5XDCN}uE_
zw$lcoKvBej&PBz&0Qgj>SouGwUQ$ediuo2Rj?(RQS@FkQ*uA27mrm!ED01ktIad`E
zzX#x&B6=FgN)>5TpK)Cws)dO%MI5b(%N0LTimyV^Mu*OBC_bX-#7#xrTuN3~D?X&S
z#4Uw@Lc2AJiUx4sRxAyKPOZXm2VT@EcFzZ}UXe)wkUI(^RfRSvPAvocuEM()osEi+
z2k@{-5ws7uW`)}bS}lsSJ>a~jaHBoXeZ>S<u(T?M=yE+!n5WP`YH3s0DZkvVSVrF=
zd#Lzm4Md0HLn`fiq-dv2N2kK)D5ln>$fBj@V}&c#5OymnC`Q?%_~8k>=vC-xE#9Zt
zPv>L$6_sB@3@Em*f#wrM5Utz>6@ewN`&5y!9%4wb5jB%emtn;=It)3Yu-pgDsG`t<
z)|g^%IlORHKBOS<PUXu~L9$D^{|IPyD^*ma;-MVrhe1ze@L^cmtNd|1aNf#52855&
zpYqxJmE+ey#aC&fN=84WkgB^5C=b#$&R^;OBU;V?WhhlgA5@OgnYlpaO<E2HDWg9^
zD_D8!8>k*qzR?8{qU0ulCRDkO9`=Wo4l2M7Q#OTQEL^!^2nLTRtEsa6sIqcAI3tvw
zQe69((%ugbk1PA>#TThO_6$Un(t{G5C!9)t4(1fCjHAfONo66OX*{jG@g=-Cqnx7w
zO{_AGo_g`hLv+t2D96#NFi{zh0n#L;CL66}<-3%ePf>24gw9l@&+BmXobu@#=uA_t
z^F?R6azqTW45jZPP-iOJi@=$sbRPZ)&1_}BMu_uDg+IK=Q3`1vmaAk|L+66Bi;AxD
zlshS9kgs$<j8=it5)St-DqqS&t5ErU3Jex0gC@Y4OUk}k_$7;#+24WevND67(pQvv
zH;5ADIJy>Bl~<`Q|C;iaGYWRglyA}5opR+0K6)#Z4yp&cq2!MPzEXLLN-3(8Y6DE%
zQl`^Rq(-^x6?EQKK10FW2TGv_yl7KSS_kv($`h10f2ho&w^@hMCkYqfkup93oSn*<
zRJ+)vTzeL{$I1sA>HXKOY$CsVlwBnl>{Yf=B(G1I?hO<D%C*O!I-q3TfcsCB&(ZUB
zP+3iTrKd{cx8NR9uFuAthLwe#@M1){=mc=CD)m;dxT$hZ!tM@LJe{4{sd_U2ox4;M
z+#z<WSWoC%D|=MoO6a(&@~DW(L#3cFo2P30M`-O;ZMz89_NmS_0O6(DL7{tZRRtx6
zd{oQn&v?IT6~&@_RTE!<7k;YYb~t)KwUllaf0dsAECDJu?QRaLMAy*@RQ*9olpvMk
zDaBucRT)&oa7cAv1T-NkJw>lVRa*q0IjjoyLMu$wmWx)nYVke*kErVCF?m$AjRn#O
z)zdBLJf<q58|t_!;U}~rRqKDlRf|&nN{2a4sNyNC7p<y#fFI_h>dudt%PG~TEin7P
z7}d}?aGzG47zg|r)t9tTk5!2&R1>F)pvT8q)eI`biC1|A#Vc^Wb1{Yfl2tpF!L=0C
zHriCCs{B?0eoi&%8gOZ<*%UxbSFv(ImZ6FZhR9TP?Si2!RTq7|H(OP-6!7z^*_0p3
zQGIz7fLxW{ADtIe$3F*Wo~ry$h<w#m+G7={YH2TfQT4C$Am&u43Y-AaB9(<IO)sf7
zQz>t;>Yo~LUsk!l3B(muL^3){RP}Uyud3G2OYOSq#RF)Sslq6EQ?4qz39<@R_c#D<
zsE$z<qf+(cW6Y&WHG_%<Z>mo0!*r`v_viq@E!F9NsXDAi748S_+p7LE=&e<`((0^E
z_0?~<vh^wsEeG$aKBB_{jVdE$O`B93UIkmTYJ3~UT2x0~h1>U3?9b79pxXU9RN7Q~
zmjd3dI!hbAN2=~?=<HN2mOyl=S~p>=M<p$y&vW&vW=}`6PxUT6tov0TH^bopmDfUe
z`b1ST6|F(l^zGn&s``|wj)qi+X`MZ+8cRp#i0YfkaBWo890kCb%9l#7T-CEyz^<EG
zN;`=i>ST%_>{NTjp>vnI`3L+k?rJYY9Gxy6YD+SJp6XnB1beC1cfkv9_3MA5(?>n~
zC*b$16REPmSKWIG&iJW+sfED<>Va%n@>jbI!<hhe&=fdxQ0>bDJWw4?i?ks1?{w<~
ztKXlEu|sN~YH)_AzqyT8sCxQ`@X2{ty`>x6Vd{hQC6c4+j~Fl!q4uMP<}vjXIk=<L
zFH>Obgc@Jgz@4vt{RNDjRR8=3Tsx(1pvtirwd^`tr`5-w1K^B$`es;)Rj+fyl;YIS
zv|#M4x|AXa@oN7KP)Sf5m%>n@Q$0XI{v>rJm9ZtOKb{5?DeCcWz^7F8$0y-py1JZ#
zsTt~T)?mJwYIoYP<*8?`!qoEB6DfOApk93(UR+dXKZnjjbu_IEiqw0`fxD!BRSJW}
z>OU3%cUirbDr&E&|D~K&iQ2jDAqKCix9*0xramBoC{+(`gQe^0FFuF)GWGFzaF?sc
z!XYZuFHl`$m6}hLz&F)<Ye7@3R-~izmO6^w2Q})aRMK->{U(K}Yt`#tfKPSm1wUh~
zUVYpL=I^S1D1~TLr#fj})TI8@3Dsux3R*L@sQc)ryr=G>x|{pzKj{Lss@F!L^+0{;
zS!g~~KS!^e4)t%FFwsZqTuMrGs^2Pwr7rcmRLk>N{VRQ*q+8uBhig6RZ!g1OuR4`d
zsRQc2DU9+&-KcRw4yyg>>Gf3o<O$e@)P3}qKCBj{13#jU&x9CN|L_m&j;X(;^x+Q8
zvTMNY)O<@1`CS@aD=vb&rdx?I56$n-LDN(78I@ytY5M!%sJEuA2%SEfEnKwxG?!^R
zbwK0RLM2=Nnovr<25P=@!C;WaKwnS^)|3SRAFAoYzQ*OSX3J!_7N&8hdXPv>2_Jwc
zO&F!oPiS%z(TdhMD2H=W^Kv}=J*C;!4zd`{ixhr2t=U8+_-8clW}-7zQ$;)5I86?s
zPEMDzn(Vir6R)YGPv9kJmQx8uqUMYHFrTEEk_Yq2ny)BClcGuf62MdqmqIk>G>rej
zV45Z%9p=+DI$w-sXx^iu-%O2<6r5R_oiowO)}+k>;JjuEojA(TEFqDrd2t>9&I_7t
z;cz%#lOKU*f#&xfATDYuDB4}9Su_bg6=}}W<MNWml@h|mnjQ+$U)Fe0;^2zru`BM2
z63q>Y9A4F|pjgy3%`<PqwNg#<yXd^Gnd=JbGEK-vz{@q6Y5*!Uu?b+g;neJ*Rr^hi
zOBs5rHRXq(dP@`K3WsYo^C<RRr@2CfN%a~TY2MYmL~H3rO)AwhHfhEcqt&cg{RLVr
znh(6ea!-><0r&@+WuHQ{Y1UK0S-WO{Vg`>iH5B9T)PymC>(V%vC@}a~^RqvE>(+eu
zCh$F)EurY_*T^Y6H=vm~6XJ;`jRKcLnu)Y-9o7_3(rHAqZ3M2lYW-+VZd$_@jP1}~
zEr6rDwO>7p&OO?=Z$Ry?y;+BrhxP}0XnJbjjDpHuZG_Vo(ob9Q7=s72#gsVr*WN6G
zPJnhsFWf(<oufi$pw^XEx<T5(cj11pb_lhpE{C*Vc0w~myO{u?+Lf>3;vLp9kD(Q&
z&G3LT;o8ivfIFf+{1(QJY6CXInFy_O55zHTXeOnsk87vWZy%}MPT`*@Z4A{+ozOm_
zPf$i{f2qXSN$qqBC!W$qzK5|GZOLAEaaw!48kWvzmyUy@v0C%<uoS1gd=8ywwfkQM
zb-Z@!TwKZo?aOqoG*SDr8e>UXX#iTu+Ps<ceS;Kj<wSUss`aV>={ap&7TD6X{=Q&K
z*Y1gg7a7{AhhaWbt4Tv=mbT(5@Y&iD3eBF^*1ZCi9Bt<)aJkyp0<c`r4sJwep7s}-
zS-$oY%Cr|~by~D8YMbe4S*Y#ZMen~N?L=CGT+&9;KD$`E^#XJ*YYTrs=N0W2s1$H1
z(FXXz@2lFI?NGU<y+M)EQtfUky}GW|9zd%?tD^+V4ecU&UQ}xRGQd);J?o9mTUybN
z5H;F@Mz~$4o%0b`>b29i1LwS>ZIYt5QTy_XU~AGgX<@fn%PNM!``R_M?QPXEDF5(4
zJM%k`wrSs{a|rF)sq|cas12mQ?GEj8w4;8cJxBY-PVI!ZaJjm)`{_=2to>~oeu{1_
zV+wG++L#A0->1Dz&x?MicGh~>9niKc1OADYH5Ud4wQtP<;;B|j$$=s5KhrTbtlhpI
zog><7*Z{hWYDf0N(wKH|9_H(+3s1n9n=bniI(O(^qu0Vt-Qx2QyL53^;l*xUt2f5>
z=>Gi#WbV2R|2?dAPJ27>p1L=A@Mf>>B^J2%=|0Ovr<d*@Hq3kL&W&M)KDxs~xVB$c
zL|Z0bopA#+{dC_)p!0xEMjx*5*Ij!LfB@a(x6pY|x4s6gK%J7Jph3D-l=%wQojCz#
z4(SXNpc0~sbk2s0p*m+O%pcYT9EII5-JVi-8m{Z7H|-JK{EJXMs;j0vc7!frC&rHH
zJbwo1ah+iXM5OL&8Mvc#Cn$7xLMKRph}L<MYbSMq^qe}S`<CK}F}f-A+CQzkLC=db
zI-$%78LR6m0C${j#<!q3tDE)|&cy4+QN?tE?qxX;iMm&R0b7!eJqnd%-S8N^NYUjV
zgh<tWIRz@`bkk{hm8P3^0hZErJu5+-q5G3c@H2IcD0F7&2Hrs{TUR~~_Rj0Jenu&?
z99=8LI&yWa5%_&U_dNYhdAe_C8Jn+LMVq7o-H-I}yr}aYgKLGlZ<G*4Iu3=BFX_^F
zaIIMP=Nteo>()qM;)<@0imXa>pVJ+9Rkw}aX4iC{{-7?^-I<P=mFu1jrq9Dx=*G=Q
z^M=lcLc5hZpZma9>6TN~{7v2RxiDX?oAo!iZ|T;%fUQRN3<dda>kd-#wN}?fWmR>$
zH>pgbURUxW0C#kgli*>4?)FCD?&^M|#a*MWa1tyu=_=TOH|vBHHFmb>X1<M!aZmT*
z4gl}#DurmZ>fHVY;(^Xci|IC<57qa!>zscA_)wR543;`{C6xDnqzhRAl}=p>MI5_y
zHzT3>Sm*OAI=giVwU|qfj!iGzUR^l7jQe!U>AZ2jE}o)u15VwS6EXNiXQv&-pzeb^
zz(3X9vqN=AxA+T?4(mE7tvsT8Xuu^M)or4hoH5-`#O<p8md?z%>F2G%)OP77x?*g%
zzK(~^J^KE;5bpYM@1xU0|Fb6ydg_H#e79F0x&YMs^v=*{pyQ=44MwlGo<Xr|AAQ&t
zVB4?%xCx!U`ad!t{Pf*)uOHCIQ=-IQUqmsX0KL(Q>wHk3T7)?T>R%#9gY-od)eqLc
z{sE?RNdEza^+NRT451aO*C#?8)~l$vD@^~yxfZ~1{hwwaj_5z8BY#Krla|6@gg$iv
z96qLBLHOhPhR@(yq`sPRuu=NJ85ldE=d|NDjMo2I1(uWghhL!cl>Ue7(2UX7d<SPv
z>jUY#3TO0s+-xqf`YILxar$`L@|@LgTumvnc>Vsf&`Hw2MMr3o^>5PQ%@qBvI<!*t
zTgdNo`ivd$Firo<NzkP0U0(noL;o4Y#WVGRe}XMbe`+NF+4?#PUY*zfMKw<s^f{kF
zB~L%?F+{$;c?3Qc>I3e;LXo~a{#pF}UDAKn3j7s)Lm%)Z`T>ghUDY3_tj%@3m7-Q<
zdN(TcDc29a0a2sRQ=s#<{>S40)at*C16!T`ts4N;>x<^W-#hyAbd;<?{|21_xvNj7
zH%Fs>L;`q|en~x4n)OUP?VK(x`fuhz=bnC#0^+_tF&#Rs`f558`9Qys;)refRXG@I
z*H2}@?n6DR2KWyB-y+QEk>0NZfKL4@k6^w_&!-jrV|_?JT<g|9EJA0Ge)l_I>D9k<
z37UQSGk4J0ua8iG#W|pFya2?IelgvM!}|7Y=#1!t_;7esA5BFFV|r!+5UvKz-yn4}
zl%2=e4#T7a@M(`BiC#zUhB+Sq=VADj{;E6;%xe&P4GZa%%s#`8XJFpT5I{RVZ$sk>
zbnZ7CS`6XqG{knG*Uzvi7r*ZT!?F{g@i&ZP03Tq`pTpQe!=zwX3N)N5fJ%^I`z(wF
z8?4JALJaHa;TLMKMZ?3xhQ)OJFw8J3A3lW}W>X38QA6F!fJYeQw7WTGI6>jWNW&*l
zm|2v;xt$V~Ck&hD<#y6AgSLUE45xSD(!?14qHytP!}ngGIb+bbqIK5L_yO?oh9-);
zCKys_xt?fPrb1_uVWu1^$%Z)kQ%NyQj0I<^;g4o$o-=4V(aJD<avKxOG$b}aGs}?U
zq#a|nVe)_R8$-h>^yV1O(5^ezaFISveZde#`_?>zf&%IJh6MUXMS<bl2KaQ*@D7Em
z3JskbVWP+|o{pJaGUQRoN3r3@RhZdjLkvygilOckkX<wUGYl_E4Oe0yt{W!IpnYeV
z!Ceh}x#1r%@D+wKe_YuchObi5S!r0H0lvy`a3SV&(@;ih#A-v}8fe}!%sz*)+lB}_
zk5g+{lmQRx4DmLIdPCX-u-q{mISrKt!#DM4-8Jx77;7{HSHb%xL$n)}Y&9EnbkeHD
zu>Jvh?-^o}p>yBxN)&*thK%<i9vJr6(b;BDP~@@Quw)K29~#VI80#?Xe*vvWhOT|^
zsnbvw3ejzdFNf$csOg(Dy@oI!hylZL+O$70%q+(w1`YA=(BI!vL)kW5gdxMjx1lp^
zcv}eIm|^oj;C3~Je*slD<JxC2!<|Ou8g%Y5o;r%Fx7)aboY`Z{ru)j>IDRu)9>zi1
zAbT2p?}BBoQDO&RpV3M03NK?TEe^enlPF^1Yy5|zkxoD375X~M0prgbApDKXdf-KX
zF@{2T2aO*aKoe*@LWRgd#?7s;6l`3x8<q|k7tt0o#P~Zsr9+M9-Jo*Vm`jD;VaB+<
zFc@xJ!vOq<(b<D(A2qI{1HTc*SxvBe%y@-z3&)+tx-TK4jXsxwKWW_40N^R(63Uv!
z7;O|hJ8f*p1^$e&jA9nC#%@~Q#2LR^0Nh!lS0F^Zarh)u5{&Pk2QJb0R|CkBjIFz2
zFxmJK)gYu87q~#A8j~mmd(LR5-EW%FiKiVN=*HkWATo>-w!uWE@d7QcvW(djq0Kf9
z{D!gfMiJ!=bBtSFhR8K?&%)pZ<LgvWlxO^z5_kE=C6mxuV60LCchNXE4<-tYfl~Ne
zWZZBZESHSM|AW0^V;CKHxNIzRRzO}cirG*tF&gTidezvR1{2qe&%1-I)aXjdz3avj
zda#xm|Db0|xp8e5G%Jkf=(&8u*qH~GO5;q*238qw<zu2ZjbCS?Rc&Ov0QfEA=;vtF
z7^jh=w~dqOPo>tlWEZ{v>Wtm*K&Rd~pXy}q7%x&BzrnblqI`Fa$+S6ZG*0b9XOnUC
z4m$4{gQ)1@zR`Uu=G1DuPgSoEjM-eMv>9j3!dScUQ~J>!8V}9Id^?QqEyvg+qoy45
z>@=QR4nti=Ujyy`9vgSl5w>pQvL`_F7{#+O(O%>9*WvJhF=Q%KpBNJxF*a!2Py+X#
z8rfui$Y`Ry(y+0Fsw_r~5mc%&Y7CwW%`syomF~Nm#^`5uGwCR{vcuFI2bG<sKX#+F
z%hZO{vD3xf^v*}<^)RtQf$%iBcc8V`#G>uZKGQe>xV=m(e}g4&Q!~Azd`yE&(AsZm
zrjHBynttQLCqL7Q$*^?5G@kBUf0N)1umqTLZ$Ras$wm>tK+|N34hESPs-PKcnp27~
z=ONQ%JO*4sOuMOqB-C`_6&O5hV$mWo%w%{Imo3~BJQ-{erU0seKW5@C0`Ryg=2@^s
znmh`j5@nijAD8Qd=~W+i7;Orr)%Qu$zx4Na%2YEQDlsN;0^p}jy>!s&jA@J>BC$@>
zZpuHznV$a|^Nlxcw4;?^Dh)v^(NsaJyCl;WRJf9C(o-#Lis>@lGpVM3D<IC9rrJQ7
zX6k<m6X~W;bKz5l>Gh3hWt$E@grnz8^;giDW4cCHJ<qgQ2$664okCd!CMRkt@V8=;
zH^D@qsfw2SMW)3G7`$X!auA}}bcI4%mrXSnVd;t~mQq(GCM(4{u9_Ci1lu)}58dRY
zrWA@9TsNgg0#Ii9*#rKTo7Vpd^A)D)-+}sushVm;DoyS)F;-<-?u-E2O;a4LbgNCK
zX&Ag^TK*2MP>so(PW;_AU0jLD)SALy2X~#xP6@br)Ad#G_l~KJE?0xeNtIi7O@C2n
zsL}K*t)81qJ@jU8HZ669Xfc)i1M~MygOpTgHSIy@!R3Kz)f~E(ZKk*AZQ5?K&=Jsw
zCeL<sc9_D7(D}$Te+r!GG@bk%on59aln!`o;?o(DZqs-wp6xLePzgn^shLEd>0dp(
z=r=v4>eB&}Jr<l#Ouh68l0j3(t8nJ2=}-k&hD?54RI)W}N>{<eh^d^CDWj&4Yv3L;
zjWXe>t9i3GI^E3NJutt+yp?{Do#v0I0A-hXqzK%*&63BsBzw%3>lkx4@A?(O!@MC8
zoSx>fP_*`%+g^prKJ&;u2ru&?I-comzT`tGYajCl`V_)`^Y?T^`I_54f$%fmt%S}2
z^OKD*?{9XYlv{w=B@(0u&EHZ~CD3f5iiRNb^Jf7FHajZ7eaO5t0J9G<Z=tAhsQLb3
zIC|Lp6TJ<?%qysxEZjVIC2&W~t9L`wdDJYR=T(Gxo)eemnE3%!4;(kIVnQd<oNt4O
zGPe#uoG|A%LNnStix1aMn)z!%ddfWA3Yr*m^&Q|&o5#^>|BN|<-juOspC#aoGry^W
zIBPygC!yob&+Nijg1IONzeu9f-2O8LlgzI^0e7<5<u2xX&YZLfs%hposm3hbJb_{k
z8RpDbATrIWW&pCxlPNfvZGN9F{&}<aVsz%12WelEYyLP8fD7hL+u%%|`T7@V<(tpd
zLZ!f590c<h&4-Uev(W6^9}0Ytc_W2!E|~?C)hjl$sc!qSd0G=xubAWi2cJsJ9~^|Z
zYIe<r-D~DoHi50w{0rsgubYq0z*w0%fPSrV^NxHNtT6L-VeE#vf!-sPX0{%kRpzx+
z&UMp#w+QyC&8wX;7`$bkLJ#yB^PAzgh_}t7lxwRs+o&eI&a9!xNxk{~TM&25Gbmct
zVD_MN!d-L9COFz?mebjlCiCwbK-z46_jj~f%nh_vyJx;Q7i9O%^Y>t^)qM27SCu)3
zs#)61FUQlXuH7vB2Q&}OZziMFVP5SEOOMPee!|7?H0Kq=;V$zcS`s`q$Cbl;xB2eN
z_<efJADu?4*WC61Y<=bwN~QLjuQY;Xz&y$Z;E6eL8dL_&n<yXl)Ew9dXNJtBbPi|O
zoKi$3TO;O03t(c@Y@llUG4rA8aK_alISwz}EGMYGaEE2iR*dbm9HqGJF3X>^jCHp>
zNrZ}r#ry$;r)9nd{_eHNr~-JOC5x7WUY2*KqjSGy&VImsEj)T!`dL1sGd=;9uYRKS
z=RwOG^FSJC@hU}ckVT+@2)3lqXJ`&tp8o+N#4`B}OeWN_c|M#uY<YDmM3|-iF*L(1
z>;8hu5sN{AIUTbM&^gEBmPNau5^0%9wVhFxPa@DdVYx$v4bhhMzd|L(l0f??=V{A@
zxu7{?X`rJ*XD!SY^u}8jHKUbaX*Yp8*;0HD_!P^zIbch*Jc)+NIg6Us+i8}+Dc+lI
zQ9Oc5hUH~S0AyP1REL#i>7l4bw&gG#w>oe6g-){MSQwuIkY~wLz-+$LBEE>LS6~@@
zABZB0|0ak_mbfa2V$0G1j9syqXlGqw>2QPHtCp$tz+ba0q>s0jTAt80@VdoHkDW3L
zpX$`hEsJTVSYi3th^uzPvW<(*O3M!vzPV|c^&@_}YRg<&2i~$cf8v9!#)8~B?tIHD
zR5?;>iR}Tf&hq9bXw_TvYk;_8S+xi=Y_OzJfnAfO?t7STwmegU8MauGkHW)y7Js?}
z?^~i#i{R2~SuBA{o282u7VVZF&jS9?BBixUhh+*aGagx9cWThvX<6qD-?}W{x#OBV
zwnS2>wA-?P?yDY)*9|z+Yk4CAtv<_23sm|oW(pJySR~WYdSVGp2HR6h{T8@3Wcjig
z{tjEb>1jD);d-NU)S`V2u8mo|e*wVNTJ<h`a<e}DgZ6(rtP8dRztcMPAjB?f1RV?5
zZJjv*I(w{9^fGq0{!5z&59_2;nA1M%cl7x1vetbBpS-P)8o}ag{ee>6epbaH*garf
zMmutU>jo;V39$Z4*~^30K?7RB*1$2a9J2CiY5x~u{f$Bwq1F>!@a?cQHyZdb>&R?e
znQ&|9HXx2zwUiS%YV|$|yAjq6?_*BKtWz@K({XFS*AS7`&}ZO9lr@s}jVG-2luV4a
z?xNz#lh#!F58|h+jqxBmV_i&{?^vtXDf+%^oK<YW<vwd&ECp%2brOXf6RiETo=djQ
zp|Dembu~prQmrv`jv(F2rq^JG^*#lNGpz|zVKB@3@&_QzwsP1oao(Cnubdof<wC%7
zty(q6E?6t+!_|3KMF7U~t;K$5ISZ__UIYH3^%7;*3ayvuX<KA{<vt8vvI-}|M6osh
zAn=#11su%jiuFwj&6ZeGeg*ec>jeeau35MJ1h!IZFlCUhTYqhWW|=jF_Cw{?4l2K{
zuntp9waWT4t;KIzSGHp=)lTd86qvhZ{gA$>Rb$=e0oB{qPkk`MTI)xj0#Rq3P4T9B
z>jZij+_C;am%G6#xPs2RRu3~e8?AyW;F_%CDHGgmo#qL$7VCa`mfW)@E`jEK>-p<w
zwOYBC(0X8%m0%KWR_D=|G3|Ei+J~6-Ln{JI`0KE8{m^=3eVhc<PHPg~h+WopdN6id
z<t`ZOvDQ&>O0TtJ4QTqTY${3bw|;j4&J0*z=)jboSZ99$z@YV^8m%E~jRj)Z`qoy!
zN35;m0T{KmI_JRrm^GYIXRbE(*XVV#?VJtZPTLB4nC!Cc$imoe+xDICVvo&bKZLuj
zld?X0ZCwY@+GiWEK-0_i+7`gQZCfM3>0?s}a1r*~-tL1zUt4%9#{6uve!|!Ro6Ae+
z^tZkK7i}s7Y?CR-anN@03`hfQB{q--+5VyO{9xO+RBd?3wvW!rh1d?1VcMZK7Ygbe
zw#kd(Xqav3m-t1(ZJj9)M{KbHfFHF@c7;z7Ha7t{kJ)a$5BPCgg&W8sZ48R1N7<w$
zRR40q_DM2mqHP-zAx_#BKZVXI+tP(F5o7B)2M=RyYvzJ2&USe_xX;>djzJ~fHWq?b
zg6-7nP)W4ChUKJ7imme=yhycOq_xXATU-*x(rl?Vm`}IerMkcjTk>9*&$L;va&x+5
z*&>&rH`~@rPx<q<6=WjE<`knd*S6&pE@Gaop5ht#w(nm6X@TvB6gYa(miI3@3vGY8
zL9@vAP9(%7+k=HLUu;`Qo3ksneUxn~v4y2U^QukwE;_H-S_FWX+Fqs=qw~5gm?l$Z
z+n0sja@%X~K&QfXnIbkfZ2I5Os<hqm!7Qq5<_DO?O<N=75vpyj`M}+>?WCAcjqNo$
zL37*Y`zKnpHvcTxt+V|(4}f}`>><P*Tg4!z-C%Qx1MaSEAyvjTI&Bqn(4)z=gNj1$
z*|hW|zi<226NpxuoetBt**rf-tKD{=ib5aSR%>9s!`4rmhDWv=^rLm!?7zTZmu*5R
zxF6fbodIXJt#2t*dTj514S26@5(Dr)TLzU}_1o&`=*$zFGv+Z6gSH9u7Jh2mJ07Y-
zwp?1@4BHC6fzGJyIf{{t*=Ewu<Z53-t6(>~kp<Uw*uOjk&0Y4V^?>iTFFy*EJ@!I+
z<GI__wD$3^hthu6)84TUntSa#wxYGq{tA@~dD&Mx>1Oq|N75DYvHwlar2Y1C+Q9kR
zIp1N-&pu2$w*&T*OQGU#UqUhL0DBC@eGb~^QCu(3K8@BOA@=dr5TW+X-VlfF3VObV
z*?o3FCETw45%44Sud@I@YX67=AQARw4>~b;%$_NQ!Q=Mu3z$=solCK(6ZQmp`$yX+
zVQJuU(%$zyTBq#WX=fZ`pB)XF)AsTb%<zoe`#rG5+K;#Z9%m1WfcbcPiUha>`^;CN
zl4!s61}<}w{ro4;OtyP|4YCybnlP$=Nwrt2F?h~?Ar6Q%d!j37((Tn0U(2xXpen0u
z`}5yG<-C1f0Yr|y;R4L(+B;}_a>2fn4$0-&V`%%BZ)e&7FR-6?VD=a7R$4z6+8_S{
zyG8Z|bPDj2z3>aPitSr*Ov~wV**<k65LfJ6`nqO`eJmfOSM4im(7I;-bpT_f_E%_u
zaNV9kTk10VycBSk+w)4`T7`Xy9GW-mj&<O!wCi0Vs_ffow{X)QHXoweUP@2WTlRX&
zPS@Cj=EKq3_G_Pj(^+f3JqVpT`|WGsZm>J)RKs0+$-kg!v|Hu?(PZC!7gxR6zPJZt
zE%swuFyDLjkGA4E-?uj{hi0pNTrA)Z>>s`j%{KcyT7<XT!)fjF(7yRAhz`5@zcrV=
z={D?k+9%!vOPABW=@rPw_Rpv+rQ6P@bWxA}cMARW+8-POu+RQZElB(A@h?DSz#c)9
zd1Bv88^%F9gAemh?H&|!AF}^Wr2)hC^#xEFvCpNX!l=FQ2s+2?FO5RDItJ;L?&i4s
z1^_!8&K(Otv(w?S3B9`<|D%&myB!>gqwH}MQl!<>F-+;ay^gu`R@&$InuSg;M<mrZ
zc{}FiLDR<(+6#a8JGS*;F20WL1ho7dQ>ohGfMdHCTK*0f`hOJxj;t%_Jm{!-5%Uam
zNS*Zh4RZYX9<EogqhT$24>@FiL4-J-c^8&K9m~YH>W3Z2sgf$pF>NI}!yRghaUOBF
zXn{NGxJbL#2uC2rqK-KRGtfHjnCuSCNXP56Jc@E;j6>^$qig_U(T??0)^XCYJd*Z*
zryQ^U0h(CH>pHaJ9P!&hbJpQa`;vIaeEO?Ma17B>B++qFg)5unXrqNqvg6l>Xr(y3
zD$qLT(9zMTGzY&1xO7LvFTiCuSo9Z{=~zyi!Ys#g^d!x8d^;ER&O6R)|I5ESN@)p{
z>zJYe;(}xUGT`$Z@6p>O-=U>|dV%BBA23$rFkVIHB}dvXaHiP7TLZf#j(6!#<*Fl#
zR;t$=`E+-eIrtY~soZgAJ^&St=6}Ib<(NjXzMGCcWWL&A4y5?YEr-{20Bam?Tm$KC
z$Iq?Mx#L(tS;z*5fC;v{j=&^{M#uLQTWxaG&@a;L_=Fb!EsiB00C&%^q6r4?JGg&C
zv^qA@XYL+2YALbW=J-EL-vJiI^}X%P7TBdM?99&Yvap(FOJa$dm|~(a#i%jOUZcj?
zP0>a9nYc6+lp@$bdQm_T>C!=zW}}FJAXSi}h+sic;CoNL|MT#0IQO3Oo^$Wa+`0GM
zbBF!3C;4F4lniw2!(BJJAkw|-=?xI$qg~r}!BWqzOqxVI-ZgzPO!V%0?{m1=w`&(o
zsGjUHrK9docm4D&(4OtOa{!9ZcP*gsPyep|B3OE{tCptCFL%v)4KlDRKNy$!)vnhx
zPk+6uj~=nXT>@=14()RI5-7vF#?AugXf*tJ0Ct@WOHPAzHuzhDxEP)(Q0Qu?4Tk<f
z!#hV|(9K{=yIk&u-K)`xLxuyi3v$?CI}RRt7`FAJgFOxPH2w85=-W`}ZFuk)U`Gs7
zE<oMK@Wou{`5I0Pf;(#XkzR_&48~a$4LWZ4m1Z3$4C@y`|D?f(lIi>m9yIIsH#pLQ
z^ORvkAh-ZS$qtAF8VV?&9%R^&g1TVC9NNDNG1OC*aH!!&%9jf>d_=nf;ReTaScov3
zo&yqT81WE>P8*)ky5fwXz(|Kkq6`b^UxA!8jHTW2bB1dcfQdB}4x#S6Ve)QpaR$q7
z^u-0kZrYVgFobP``9uRd5->@IE!WVPWW%XYh@==!((Y%Pp;`=*ZZQ7}&SV(QRzo4v
zFy9hfmSMp{U}hUumD2N<WB8Hc>bVB@USQ`Lv<@h|V)%o0T?-6F1>gz|Aq7AyGKgqq
zUTmnp4uukfd_T~x8p=*X<eFil4$fRRh-1-+8wLsGIg}dyp@S)9hG2^6lpCfkhNBgR
zb2O{FWtjR7?Z4kPC>WGh8Q2QAUu}5%Z=lr}(&<jPV|Yw~j9SBwo#^~JgZTzX)*CFo
zgMNeIbT=$D8k7RKCc`p%s+tX%lVPdFaNQMk_YBuc;ZvJoHl;P*H|R%zv>Q4aP}pJE
zJC@deod%qI!$V@&Mj_e<hMY_od}&xA0otJ9WE2`YY|yO%akgKo0rr0TtZpc{+5fp1
z3Wx3e=m?sZedkXQ3ALYAgDyE|Kk)|4$J>8P0jgyCud*SMW<U5b3N!6%XrY;7Kj$Kv
zWV~dbI2Vcq_GN#e^qPH;Gq^f?-({%mv_JG;fZ1N9Mcpg=zANy_W%nk!cMk3zbrz0#
z@BX;}2K{$OP|PoEchDdTV|MQd1(&dUi3sL1cZX4i_?6w2)*!{ZFHV4kvfWBbD!Xmm
zUHCg>y!SLJU?O18vZLssh&^kj114e5Ryuo@y2qvo&Cc25x&%HI@0nAKy0Se(w4$ip
zQ)Lg4);+H&FTZ2YUmCd9yJz`kn0T?rej@Z<@9~ns8D|IOHFUxu2lajwdOFn7Nb2ig
z%%l%(9CvV|ys7|)O|H<7bQt;&qR|eG5?G3L__Yn97aS7lNlkRH*aw3t4i{;>Np(2W
z28D|bKU$(L&7qIN1KAGFw9L<O7}pA)@*JL0LenLO$IhtBcj&wea@nEnSG4nr!x7^?
z_*URxVFOa=aGf$EiX9wikyhfcwF`>Z9FqPAjq47jU!w4a!%8|we$&B=(ws^iChmjV
z<qi#VAyVORYZU5kIV`0xN~MF}DtK7s5HbMCY6n{c8zeOj?>vRb9fw?s$+kFLzDbMz
zHV1P=1V%{kbD0UIN&YQH5d{BkGhxASsG5me1pGTpG@Zh!W5&~}qMkAE5NTvSQ-W(|
zb}E41#<;6c_=rhQM0@%fM|vkXviXld+*#Q!p!l+f!f7)bKSJRYdjGvO^#Yi;H}8O{
zcRrwy=I9|>+Kd@VOZ$)S(_-xt?YpS`G~@%Ie^y8PXET1L)105Lq?Dg82IiutW<HyR
zw$0kx4}>p!D5Yk02ZaN^+Dz%)U%M<q`8V-O=zg0}0o^$>Yw7#0-+5Y~dakAh%JV+X
z!{77Y@j~x>pG`Sy3+B>P_lIAmqx?tLk!aOV0-Y25Sy_tTzsyX7%tC7lE-gAe3ZRRp
zE`i}C3v{Sm`X`MK%PtK9VfmP^@b`*>Fvzd`=04n7WkTblakVSu@U8JYh@xLhQekGD
z{uC<KUk^ub{l+Pwup!zLwZD5%V$sIUG~{l2oA$Q;*&d7E`<cHeE%g9X(E^Qwj6L0w
zZp>y%XLV=3x(K_6n0+BYKFnB+280K5xetBe$+VuK^|uc*>jV^=7(NZ2^f2q^L-8^5
z7LA_+O#D%_>J>AJ=4t!cy!Sv3u#>yU5<8X>aopIN%`oB4w$hz>h%J5!l*4Q`#p^uS
zA8p`_C(GT0!9aF3?V1I#p3xvtYz)RBqa>Og^&Tw6u>Hf(Kg+J02efl+dOS?TvY%3*
z;yh~~g}ONQ9%c1iV85nspT)CFn}D6b#?llgkxiqG<|LMHfZb#^cPzM6cIyA&%tdzb
zPKczjohpE(hyp0bHB~f{@@b40MF;-?XqsqeFPusjo$W+vhG>C3L^DNWXyZ0ZbgLXB
zTXbm=U~)w3F2F>tXtg^e^F-aN;o2q9XLRT&UnHWuw9BGx3!rdC6hKL}1)?w9(3V1x
zbR0yAM2qN1Td}D24{#+$(Z&ftyDF;W;qWz4<(DAWMV@Ma-Vn{MhQXVntzW?5Qqe8i
zCo2=3rD;gH=(F!(sY2v63JSMG`x;SLDOz<BmTrqK(&@q~Q9CWHsztxkv9%h}=OlSY
zRFeyPwW6$#p-?9>&TxY0UC|m^j@OIokZ2-l5Z$HcuTf-i1f)siMLAW?qUUrIwun6F
z?B6|6r39o^^r{LlZ6dB49^Mz}E5Nmj!c1YXL*zsYx=xXv9@;KZ*<q+Z5cRJH=0j1=
zYSeX$292|!_(;@FTb@0lsXIX)i}Go;*DIRw4mzPvbeU4$o`@W_qwuL{&<&106Q%Y*
z@3~0!2I~4nxwKdELgelT?3bcZPhoICG>!7eUx|`<pg4->u0~fni6d#!882Q=J4^}U
zHw{LBCW@DYfK3uVodk_!aa|)|QpAH4QcM-kd4$4?;*J>DO%wk_Piv{zi5}51v2O+R
z%Ej*&K(a#2(dSO?ia(|-jC%1P#V6au?!F-R#qk^zI>n`nA<`v&Np2sM%xR_nui_?Y
z4}(+glDBD1<ROWm*Se>qkFs065DSGf-jbjxa5Mz}>ln_YOANFK%8;z91Id)^qsKQ(
za*>YZXG_-8tS?8h@)wxMl^lr!$&+~J!tN!BCHZ?<GIKOMydwF-_}?dMBu<o!RVevk
zKJ<$uW>u&xmb~bK-4clned*__WFN)r8>FwP*^Sb!uR)rmIRPNeQk!v5Z;_6C1M2sr
z<EXn^rI8I#Xp=U+M^{T)*9Q-uOW(z?FBz83p!Job$!0okYIHJrP!8XmP3mcD>##{J
zwaLR|l?MtvO<dlAGhQa1G;KR#a(E*8(#Is7a>#s5&gX$UW)jl?nByjLT5y~&`G{gg
zCrud2j0`ZjyagoCWMe%FgG{n%vmwId73IYwoAl67pJFu0+X|X$GDumB7fn7)p$;}F
zrsT~`6So<t%Q9Iy6|QBQ<j#cOIVQzRU_RHR+7?`q$uXLX6`Lf`<4|JqsS6aYn%I7d
z!fPgW_knW5WbNNjziA?)Ljct#o0V|8#^gCoYwwsC*OtJkT9Z#wVg9a31tk;LoA^+s
zQ-g^oC7(2!@JE2%Y@(tNb&JV_I25*;aMJ<PX0nM!n0Ax3=b+GGQeFs=E|V!V<9}$<
zItP;7Cc!lEcw~}Ehq|0i-&q6i{Y>BKgPy->lJN#gPnpj1hWP-~>>_{$n&#2=evs+@
zQ-BFJRnvA%i0QUwNQRp3w}(iCY4~kmN1EQJq?gmCH?N}bjOkAlVTd;E`vcCzm=3-J
zl(VJ-_rRSqeL_3<v8LVM042rr>kr^Xs_CS8Zvs2bG>l$S>88~=0L?J{hVFz+)4F14
zWSjnVvNss#RHvxXGnY&cI6&mGX((;JT`@gCbD{#%&_AGFXv$N2i%qAAV7J87jJ^YW
z)pQ9Roxg6{5)aH9rri`nylHB^7F?(4JzCdwnI`0cduZB5>y2*H28tLzGW{QYjIPJ@
zZ+f@&nr<*&fnuL&OA$n$ntIZx^~^MyLPkTTf74rO*fg3#n2xd*5hR^tKV-uhXW7eG
zz_`fL%>m;o+qnm>?UzN;D0@IQ*o(S@vPBddbCVsS^uHsrRg^yOBb!B!-%(ja9rTXL
z-d|({Jt6z^A1I!b9i^q~1=;VkPKuY+(6&mVtc_OVNwQHt11(whr!%+|Sp~%+Qf1Ec
z+P*0Jh^|4JtfC4%lP)`z2gwZC2nvd2%2H_Fk|mpv4U#Q;mkxpE$Zpb-CRa9TJAGO?
zPxkN?G%m@$pm}`0Ovs{3A^U)qj#p%<H0Tz{5<dWTq3p*%)D_9BDLPv$`}BM0mB{9<
zhU8UQ{c1RKP4;*m$aUHOw!-{P*|tiEl*)=;pxI@z9gzSlm$iNZ^A$4NzZlFDZpqSJ
zP+BPq<{^4pR!X-(mF&$HkQ!O+LWtgxb<nD~R_50ayLGZ3nnCW$uF;lBy-Z;X^9`~|
zbVjRD_7mL+O|r*H&}){}yP&W|_RIfJcu&?K!KG-G33EZ(WW~*}XS^?)(Ev;BGJBfx
zb;uUb6sS|Sm@*!G<SSmmHDCFwG0-?AA5#R-0Quf$Xj-6rJ1xqC<P#`F79xNDBcO%K
z|A~QmxZG+LNQB(Y6nc^J(-Js(THa!h!YKKQZ-EjmU#tgoj8R^@9`vmI*R=qRl{;FZ
zGEV+*1JEwWSJ8>u40(PNT+5W}$HJ#<`FPr2&ymmF0MJ7D(n^4q%HO7`Q<>bJmgwd3
zeg6fC<j3WxyCpBQg<hq+{4Bt3%l9RsORD4-3(@Loxp62Qc5CFFw32L*&!tHBJ-HK2
z`C8=*D5JVfZnX&p@5?>u4bU!MPXWyi`RfX}-6?l+0rms=-*g`1p?o(@cDm&+D4g_2
zeuZ9<J#r&O8z0LT(TTWT`35?|&?ler8Bm_c?;7dw-BbAtZ(u)@Z=kn$zuf#iz`T%u
zPuVUn<$uuxa6s;s513c-z7-&^<@L$XAC%Y9qHjpP>349$a)HhjIhqyGcU_#!7L5aO
zHZ!C7iHq6))`4?1<LGOd`^_dtqMr_!1)MQL|Df6C5V(KHEQv1cVY9z!y5M0pnWi#c
zX3uwl^ETUU3D=I8+54f;$E^PhV0_K4(c^T~Z0sCx$ILwG;8&2@&|hdvuvt09ctgyl
z27rW`O{d{C-0VpcxCpZebnPR}xCN9a(ri{sfuMdf9R;o(%|&Y<>SX>w2n;%#A3R6y
zn;V-U;%eSTn+E&Mzn%jacXMA_e;qP6Sq2Xeo98SCsE2vLW+-@>Cz}Js+x)F5XsC~Q
znK=r5&0S7F<b?TBI@ER2y!}I3C;6HC{|@*4%`eli6=0sR7}$a4IW%1lGVhv%x?ppb
z9{*7D^R&?wX8x`TK*P;<e-6+H^C;SgJZ<hj9ffDieH<VXWu8Jip3&w9-UCTA52e96
z$$W7>%qN>GX@p2IA4-FsG1WZO28tKWC6wfoW?tJ3l3~7vp7c!f4YWO&W3Kufih1S(
z^B{T2eBBn<EjQOvT6cx{Buhx%GS8)RftBXYbmHo^dHJ6}sWKn;F$$~A3uxGBGOwdq
zce8mzJL+1@2Mv(CXEe8?Eblh+>Xm3{r@2rG(q%5MgXjbE+H)}f(A<O)mU_(dXb$n%
zTtR7?z2-Ycp@aL(f2DB6bMvjgf%KbCmqPM|`TRG5^3puM7>*8@XP$?pSLTz<;l*q7
zlMi8j(0qVa5}p>u>9mXGW%2C;=zCin9RN9EG5vEC`dG}X2l2H?$$;Wfi}g2P{+PvI
z^i&+Tn9TwEgoW>Dpq;b`&4r$yg)QAB{uVy8W;tbXG#(_t;@Lb%23oZ2hHJqVTkb<L
z#3F4Ng`pP1|9#p#%);6fE{0otNP9F976bIMh_vXt4RXff$PIKtl*L$jMxrgw{0o>E
z3z>kza~74~qoJ`D;a{WhyhZqKn2)pAGy~*<MP)7u<1Jq6!6jI%8;eFHS}dFfy(EiK
z^fjDhi|<>E&`-7aFapHQ(k=(Y-O}|Jh#s=+eG5MMTDH=sj80k3m_m)QTu*86ftD>E
za5TvB8BO3qEHj+pXsG2z+6N7@oJ$`l3Ag+oZR<x^ZVQ3=NXv!hAm=R$Z^EY(%jjJo
zsg|e1=+izIE#ESOXqx5Tw*Yg^vT-&nUAOH13@|q=m(X<bw&hxSH&$7mqYs=^TOJ<`
zQe%05CR=wbpIAer)^b89xH`)}Pr$>wmTB$4thaO?2cH@&r{BW0YqXsAF}!H9?AQj$
zX3ICxc}7W#<&{-vMXTioT4J_Y&ZEu#`<7f9VA?HPUZJqV^5+xK=(C(jVfQDN={2Z(
zYB`M#^gXlOIRJ&{mW$_s>$j9MXv7Q4A$km7TKZ7@X~0rV$)c|;Z6=}cwPg(DqYYZV
z+y~c;LzYc1!8$6uhEeIHh~EI>tZ>u;)J5Uj0Yz8ENjkW-UvcmQcyT~6ZwI)8ips5!
zbW_|tMi))-l-@&!6zf)@@UWtNE;`sl(OwAio{AdEQ1nvR)6R#t;>S}cJfb*4J?djr
zl=Py~S5b=qmE@>m)){o$aYfHURGv^YZUH%|NTxh5KZTs$hW-j4iu#{YWZy>51Soo*
zg9}uQGlRh(#mz>T4^|AVM3X`ltLWcEhbbm4fk?QbhC(qBilbLh7pd6(E$U7yjLZ}$
zo>45IJ;x};@<^D7Q7ri!jXA4uQbFdNV(wSygjhw^8gS<oi_ZWiPVw*WD7>Ihe-1C=
z6>o(CG(q8d6e5WVFIv(jDb9{XVX~s49!*MB?0W>siwX-m2$7~}+5`1;MTqefG%^%B
z$HIK3LcAVamf~|7ZL<~Gxp1aX;nD}RBE{ripi!)NgQnyqiljt<Rw$;sL*$lXI;A*N
zDn4C}!rKaUD!{4~*0fJut+<p8yETe!kI<w$imk~|s8vKK0IW{&fTKL+yNdC&sH|6v
z4?t;yqAL|>jf!9Y1zM9rL!IBOFr5yOdy1!9P}r(?>wjokn<9o%I_@i+oT1RJ2r`FA
zhvI%bNT(vf6Ovtu0E#+2P{=56{-NTd&!Et)_`?>3j}+hQY5v)xc<cm?$BIAiz?mnC
z3*&+IRI#=M8qXB|G$uS(#1(_|E2MOQ>V=}2W{fWtzq_EJ1B$I-P;jzp+>JtKtEtD(
zUKgu3DYe4Y>WA%U(g7=uCLaf_me+!Fvsym}_S~&{H&CABAuBgWR35gPM6Y%atByCJ
z=xKGAHUzz_q_n>9wz{zwmX28c6At2IWjzm;qOJYS(TcOyv0{M6TECwLy*TSHZQxA2
zwdHP@NVLvRheERTdRpS8TK7$Wp$zLiR*<Z+esK}%#ujU*&ro^Kdi!axt=7wzgKM+C
z^fUDDTgSc${dVhAdb{*mzfB9MKI?zqhvai>7Zu10>uB2WeQ6zH1~Op1hLXNsS&yLg
z#cS)?6nPl5?mv&hA?u&Mf!$$iE)HOh$`y1wI~kQLX+q_!yiQ3KF3L-Dpy8qPJ_>A4
z<)IG&6QDGw=w_f&?u%vzE6>mn9->^|3XxFd$De=;Q{H|Xk`YSZY19eIxEoNopnMzw
zyXndu7eF$U^Xbc$nacF{AyS~Mq7kuBX*_zA?r!CC%H%FqPN#`yiSo!tAXk+?pM~Nz
z<rlO`d0qMCKPbGRw4%J0n@V;WNU3sO4+_haNi^XtSI(ypZk<v~sp@x?3n>~?uT0qi
zOAX5HPEcr6?mG;wNm*77FPfDnjFj}!qD&n^EAA=1DD$;d>G={|n=-8x+<j%>et6if
z{7?=34&@IcP}r$#eFaNh%8)9kKTuBj7TiN+^<;>2E8RYX`Xgl>rAYKBgUwL*SUJiE
zdcDf1MQBo=a$_xAd!jtsLC@b)WxzbZJX0=R0FCF$7CJT8uRK}?nHS1O*HQOUIr=sv
z2b38Ua(tyMN`r~l$}$TS4k}yr!n`AwMUi$V?j@b*apt~#1~3<H?np?wa{J35a-3UQ
z0_YRmtT}-8<L*wPb2|Rq`V~+N<ZddU7{t9tZ_HpW=4Ut@!fF12`=Q*vo8ZDYF}+s8
zxi2H=YI9)}@`&WVpgfV&T-t2((;2Sh4X8(P?vz>>%|&;jForYChsarO@?CJ}xQsz~
z5zCFou9s1Ap4;aL6LFk^l2k8n+mj(0&lQS*oxnXB0hmN?rZwD8;@Y-@OXf~H0w#s~
z-z>B+m3vOh-iw@|14<gVC>fIJTr~wCGPo%T;4--qI&YoDEu>tiY_62%tvTFZ4p1=W
zay#w-G>>bfqgt1^JT2_zbKD8E;xhLj2l`jI0ebTka8VTSDdZ-TWDzH&$FP`NLjN45
zgp*Ui<tq36Q#9=wcZMRY*SQv&W!>ODx&wuqoQ$@nO1VTAh?H>&^lmFRa&u%5t>8ZT
z5Hh#8m-NI|a;|kSf14XiFU~5i-yDV2T(1ZsHQZFn2e`up{0UOaO{T*?b=<qtAbFR2
zG!k4r_a2?jXyB~lKpMF%`DkDhcZAk6&D>TMBwM(nbYSHkXLM+TOe@!72jAMbiF7FJ
zKDTxz47PI?w1Vp33a+8BlS^-h!7lFiB((Pd_aTLi9&+wcaI~A-H6MkKxS*?OQxA8y
z65ain8=%)%FSnMiK_6!=N5?+l(s*!Bxj$%6=Nb2g@kiKw&P}EZ+t1mMr5D`fVpw{~
z6}o{8a5E_k^NK562g%o5^v}>A<Q`-|a)>*17VRD8`U9cv$p3FLh!el=2NXK<@6i9!
za^c%)+U&|7SpaT7A43Vo2l$kK!5!rPokY){8=rm)pzb_d1g8%1f6&U{Fu#$GFnI7&
zt6|BLPk#(WFFuF1jlKD9BkGRuD{sM)5C7(Wt3m$iAMo%fpJM`lkMUC~!5!y6qO+MN
z_{=j<ILW(Qf`@*53?13`=Q|Eip4KVe#SJC`_=B{e6v+SkBP<2+mub)r=Kns5E)C)R
z7sFC0kJvOGLw*Atv<c_iXh%DOpC`ckNPblSL{9TOr8J)52Y-TI6mLUEMWXqgfdGr)
zKX?eqv%HFyYUlW$&eHlXmRGI^d!8TQ;6)tYHyWT9_!CcHBA&0M4eA7b?L&wp@?x4k
zC-I@5poPi&oc|s}K8jvBsr)(~A{Y4yC!vtWuOqN@K9X`kGWY}3L79B?DVWdVJq+No
z`B^idV9eovTLCtg@2A*Z9=~WMG%oR?^$^YHS4=`jUFK!KqG?z7$1h;FfNy^Wu8_aI
z7YarE0OijX^DSzS68<@b46pKalvZ<%{~`!od7Xbj8<98oifCZo<S+e;mX-2bVgOcV
z<TpfvE$5ffb6>%qn-9=ieCHVWR>`k@2J^T1uZK}s#W(!{u9}Z609p;d#0lgMKPMNK
zYWbG;P*=x)G6a;n{4gbS*7I337B%o^D5Ip2f42mri8qL$(9CPU2G_#l|BwUb9>3og
z`mKC8g&x{?*=un3`TO6ZuAMja184`oArp0-yyJUN?BXqHJMIA=aR+D*d5h<$>*kkq
zLGKY?bO+7u;bSSd|CmqQiQB4|_gRQW^zr5tzkI?Uszu#X{<Se0Fwb~NJ;-x@`A#_8
z&p)$*#tVKLt*2h{W9Ysb;3v|U@QNS%86;ox%tjOr@-;RvIK)5Q4>HX6T!5aVYPlIu
zoK*D;3_7bWq@d76bu|layQ*SYNbXl{@_@(z)u>bS93526rdhO`YHb^^-Bly$GgyaI
zztFznVO8G<G|fXbW;)vBsd`9BR9-4yCCq!PUR6Wkh)T2%g+8hS<^c6oU3doyM^$4e
z<Mo*87uupYuJWXy^9fbJxA5tts<;otPvw1__No0<C#s=%O7%fLL<3YDt-1qM>)c^J
zNYzfkk@Kp4I&BoE3i=j~UQp#sgGjvUZ;BHqsC3OJOjIf88A(!oF&}o5Rc&)&Fh%t}
z%_dV-e;VNEMb(~cxR$1Jpp{p;DmaqjpBbvRDeELt_0|=DW~uyhpqQ=F_CX^@b^i%W
z<f`skf#j(+I>XURsyRGB^HrBAjs3D};!$u{RJsaq1uD-9fEB8OX-ZwBnn$afV%0_(
z>`PR=^wGeps^f3M!Zp=GTK5^RtNMS0;tkcprGUAq`idTaQq_!o@U%>|mtJS(s*+W3
ztwPmE>w{aW(&td9RNdMNOSe@<`UFLlYHu>It5q4puv??@Tm*$Xs#Kb4)~bGqfMlI&
zaXy-TSEZmpdcCS>91JxWRiBQ4XrpTM43H*OpesnTYTi+pXi>FNocW&0aRpp!RXI|!
zcbn?T6o}kc^-vOIyQ=*vn%1F8_z`HGsyO=kLYL|$g)APZYM(;yp{mjf2D?>xPeC53
zrqj8;9@VZCh&)yqpXkx1Uezjpl=i8f=7M{o`qUkEpQ;W7f_tXgn+Wc?>bunt=~r1&
z#@`FotBElGQYE7Fhym3a2A%Lqb$%8KU#m{*Au_1)rOE%0>Pre953A;Sz!^v3vsGxB
zlTe!q&RH-u(yY=&7}^a>uEJfK7VZ}cL%|&oEa-_nC<wIncN0unV8UI<&4<DvA&f?d
z!$MgCh=;I=ZeUO0E!u_j67JAT##^{ayMadpzbJtD2&<le^A&RG!W<R8pvlKELETSz
z%EyI|DN=hv$h`=sP7431!TAaA(iuE|!EGX1aZ0#47p)HvdWKOLD6FOtCP;9IhrwXs
z=q8AS2v;crA1XLebRtZsrLzFxg4_%KMhI1o@FG$u@`j_Qg?W@Wct$7;ruAQx5V;eT
z(L&q?Xv7GwX$5sw=-Ll*PS}+S(O6+No)yV?;TvzD#R<<ia2JG=cVH=Ac=99E6NI*p
z;Y_07`5hFJgg9G>Bnu1aaYzxQ<58F@h{mHwFA6PrC`=RnyhiiSbfLftq8Y+m3f*T4
zMKm+X63*qoe73NidOb&Q-GjPZ;hk5|&l5^04suDb9|^np!rpl(yeynK4(^IDRtf9^
zK`BCEp|Er+^oj(3Z?vpf;JyTOiBKDcPQNPn(GH36no!h=%Im_r^a8pe?0*7-H-%Qp
z#VHj&p}V_GSoQ>U<w84M!wTWtB$&S?-2M)vQb=D06Ssv+G=HoTA}Cx{Ewqc^OpVY&
z7v_#|kVe^B;o4L9R42Ti0Li;T#9vUaHwsM=u+$(pe*zPYLf0@Vn*`Yy_|z=?+XRgk
zq2eK6?g?KS(6m+|stzXF1ddiY_l2Ea5NQ`YLSUjp=%ui4r?A2Wq)TX^<hlm}*8q`+
z!U9@JbPKmG!@?sWpQZ#of^l3o*vCS%C)i%WgvQrCA%*53PlQdhz<w%}(mA<jLJ`d@
zo(pNQ@Vj5|s08;yC^v$8DZG%t`vGA$9jbgKXlc#!TA21OL<WVQCqQIK7(uI)VPW!*
z5OGwG903oV)HjVBOgO7^>43P4y5&A9UDe-w0iTYk{b<2@T>Vcb>Q1OlD1-Z?`p{@7
z_^FLwqRwAk_zWaKJ;oaff$Ee9hy<z6QQ$IIJ;fI0L)2+EVK-F$cq_Ot^-T@b!_{l)
zTNx2*#)0Oak?O?+dRm=MQP?wTI|{KzsfWjbM62ge@Hs}kAq*O4)%(Um@|=2%0@pWI
zJ&D4_=he3F!+e~&$biClwPGn064XwV^qi=!rM#IW^<E7OC9Az?){vsUMDf~GHFKZN
z$z4>(s?c9)>ggJYrmGDUf5}j1zlFj~^;%lHWT^w*gxzd)BBe6tsNbH5x?J@jWtZit
zpVC&rCG~{+5Xo1kP~l~Du_sJiQJYdib%DBrPVN_~@7cn9k@`wC3>B--+EboTiFzJI
zW3Q^)XmWZ@-SjcYb@jk*fZkA>eF^h7)jv>Zwp4wAmZoLu13n<-YB$6@Bo*q-+n|0+
zy|)sQm1>V*klX6WJ+ND)zJC{vR;#t&K(a>NPrE*M)FHGmuT>}B2Qk*EgK1aruA2E6
zPSvY5G&^iiPxk?6qq^@6a82rra{z5tPnZawTGVl0fZS70{s3sLYO8&4rcGTCk7nOj
ze|HxO?dqBFDC|(*nh%jqb@>H=b*X*LVd#Ono{q^rRL`CT(rr|4ssh?0^<Em0d({6k
zhyG)A1_#osuF8aqed<gfxb{RHxd6TQRGq#b9rR3nkWwL@t4Gg<WWRcv4j#TxzbAv;
zm+G36kQ`9IV*utW^$%KzyjH*Y2EYc@s=pvPq(0II^<lMfBHf;jnm2;rqLapU3^-@a
zNSc(oXtFK9xoQ^egW`V8zZ8Kups}P6j2+a}{)0j{%~Z;IcGt8y1N4yQ8v;G7>8EWm
z4~?-Jg`OHGd-&v~iKTbBw<anaB1bfHZa~CG^RqD@`o0>!)sQ)=DZYlvW183Dz&@_I
zO}Qo~G;7GilbS0O<Mh*Hegp-7&5UW#Kc&e?Kqm%h9@(OWftuN4L4q_MT7U&>{zrFU
zh-U6%D1>UVO5seH#*8-X!!;*UpckRJolnC@q~?bXXq?vAe*^A}<_8L7L}_Ba1sAQE
zu7^)Cnje3I$XU&SD4?Cw3{dncR<n;5v*$J1jqo>4W9Wg%1<lNNfgP_|zYZb^nyVJ@
zB2lxY31CT@b1PAothw_L&ZKBIEvNTis%E7LWG-q}8c>?18BqZ)UGoNo95XaV7xa3j
zX2&%sW@#>z!kKK11tkyVXvTZO(Ok{eSQO@Ic2cih(pa5>rF@Md6kr7!O#-+=&Cqv{
zEY^HMXIe@$1HZtvtC|lo==r;*@y>(a*ERO<qVk3&l<v!$nkt(4m1-XE0(P0^UrIeK
z*EIbL$qLPem#}n8GtC)wl^Q$Rd%CR&qnBHiW;ex1sx@tkfl{N%=|$lkjXW9GzE-o#
z8*Qo6oct6b^&0K>C^R-`%3s4$qvp-maJWfh_Z_%q&7M?Xw`kTM0L(p2WD#1?stM4+
zi#E+0G%()Rv>b#p?V3x&Q0UN1q0OpJO$2Q$b!lYpLj8fpc?Y<MnyrZ--I}}0p!Z0#
zfnI|>n$N@#d2G~tON;(KO&skVKhb=d2ehXeJ4&Q{rkOq+iqAEZDPY^LDZ2rOUub+N
znc$_yg_b7+nh{PQuQV#k?0>EK@dmg-O*+kzhBV7-Q8=tgqFIBZ_TR@Sbkcg#^wn8g
z)B@t7H9D?<8?IXa5@7Gw22d*C0qtL(z~Djc-&v4x(;lWF$z4141Hc^8Mth*}u=Z*@
z`ocq-aU2Ss+GKj}y|nA;69eAb%l|Elw7+FQ&qsUbAqsu92AXCZ)ds!?507bUnn8|h
zKQLCo#S>av2Ify{8)w0UpH_JZoWFM7KFFNXKAZ;<p#7@{`hnUsy4ixXEwgYbgS8iF
zlPyHMfmQ^e+GbiQhG{Fm1{bdVYAVb}Xn&dmE>inOHMrB-Gt{IrTBMlc5z~%kjOgHK
z?Z5PG<QVPSAA&op{p2RdIj!$gSc=uk{z22uYuAWD;<OjUsJoy&N_Swq)`Dj33EJ-?
zK@znKmx3f|Yd(Yb$=dHe1ec;+l?@M5weQpZ!A0%EFpxCuBRZCwu08fI#a}YCy+_f)
zOs#b)u(Pzkhr({Qww+=^IoeWd=;vzP_n<IOE6^nVk~Xvu*!kMegV1@Gwg2ve!7JM0
ze?SVfvJ})6YRh+m6ltB}AX2QoLm#{<(YBq2-K*O5hvCIFZE^;EC;GbfpSfUfXrmk;
zb5r|O94wV;_k}~TOgoa^nC04afpDfm>#-N0x3oz#SXXKbSs1*nmH!I$D(wqLNLFhz
zzd>D%)|>LA?`UUJ(sZqMbqPf3w3j{scUP;UQ%3dLSlW*^HfUvHu#H+zTPQYZ&(ei$
z);7Nf(H3oeCkpRrKc_71R&BwXFyE#f^ENu6S35cbKJ{rgMnd6<w(ui3^HjTkBgixD
zV;V`HYiqs)>DT7ajPr%I{Swq)YNu9#8_?#oqVAPZ`-pNpUu%6RVP{YqPRp_(?YuC+
zoVVF-3eh;50?K=fx4Ak7tw^+4LZRp+n+LS)O|}V5Lt%=|r9)6iwGrQhdYTPGXLd7e
z$|!=DX>(vZM6zu*?}1*9%@o?;%(WS3LKoD=IJpsST(TLr1!(y;4_<*>wi%)wr7Jd5
zDch;QW(mbsi)`kE(xtSS9tUSiY!;eA<eE+0hfug~qbq~t4V$NW6yCJaPliINjW<Qm
z%WPslMF*AJ$kR|)VY5aLlv_5Jzk&Hmn>ZtFINrALz6`d?<^`n(SKExE4U-z1pMp_%
z$7UTZ*=lV#3Om)=6j9IKwaMOwR@B=J(xIUSn+BSvH`-iVh{7hD{Yv=MW>b6!j&|7G
zp;Kg?HU(CY?6Ube1Lhytd`J=hhc-L@J15X>qot3TJhGYS35_0`(@P=RYjbQQ(E4mX
zrr6FCo80LjPi?NfK;bi+HxeQ8+@|9_kbavpQWU<hne9y1*T$Ao+y-pKaq!}m&G|#%
zUfVPm!NQ=8zZ4A|vQbeuW7sBP27RZ<QFo^sFiyH#HmG#g&2fb#7o7*iQCxKa^cvl-
zD|!r(1G>#y0eVp9P1)3Ly3Ui3bk~I|(U?QJE#)wASU2wo3O#hIXm`z1x0fbcUb;A%
z5P9o1RYC8FF8wcH`s&6N)4!HGs$2L2G>+*s49Ia^_DYyIp);jj+mpJPlnm~tyG^eZ
zf1P~=ES=Idt^sI(?(>yE3)FqI9C|^z5fu6h)`_R0FhsYQVvV7?ne<8z({<682Eui3
z)&M$Ew<R3iby{ct3z};@qkE4w@S=42KcG*db+r_ZJgbva`arC11`QwQbwATS&jsC#
zUqRw^bN_%yg6^AS*iF<0(W8>2i=w4?vM#C&CQ@~Ny^y@9J4yS=X}ZrWP?xS-a1dT(
z=q6GiJyZ9{6CP$6bqhZLOtx;{QLs5WA9}WPb;A`X%+vj;Md2mgaoViT*ICX5+GX7$
zUpRV2H`5P=1-k9@4YESrW4bSjbWxNrQ>@Ef50nz!2y4_`)A<j8T-Uwr0fien2Ntf~
z)QzL#RHZuOAl-Upy00j6tXx-8iP8bxC#QjS&~`lq>)maiQjGJE?K;ZUI%!)^tA$gx
z>nJQAWV?c5*P*t|XsAcnx_tu4Xxp>rQ5a+EN@u~(+WteUn{&34Brp_fJ7*t6&f8Xh
z125uizc<o*_ku06ntImubPiw=Y<+1qn`pa>j;SZv-lpzOwhg9KvlLs|1b|+&RWE^F
zn(cy5QJ8Ogj7}0=wsogGl2Ti%eE=)7mDfVD+_q>9>{i&m^Cd)X*-oItJC(MN=b&Y`
zZBM<T_)C@TPI@_3+n$MnevNI(Dk$EuEy;s3wYE8Tz}4Aa-3HLRwkO6wvEJ6{9`qV)
zgTqkRXd5yLdQG<8U%{tl+bxNxYq9<2HoR}OeQg2gHrv^m0CTZ3X-A=}-5i<(?6+IC
zjn2s(uuI(u&_Fx+cTfznONjy(Y-dYz`4GF!w3`@er<?{Z%+BX+=ttQ3&^kHN&Xryy
zXY7vU!TbfgIxS4Z+d1{3y$N<_=s;ki-GBowQ<7Z)#UqmK)R)1f*ln8+M^o)|I8Ses
z<l6buZhoGfi4!U>*-f<pxn{R37iib*_AUasVfTQ>{F`>|4**kUx1YA$D(p6!LGqT}
z7c^)#*xje+zR~V6t=60Dn%6<3*>3$xSh{EDvkWM$cG!%-7-rW@d+X2bZp?(FvEQz)
z8f|)E*S!T7=%wAeG(NwwJ4pBXYr8d$s2j8!FatMaC;KnKUH>BmK%Ddyg^+aC|L_gG
zaM4@11KU-<APj~3^&J#XKcM%cy>&Oe8%<2y^&i)O9MW%gKwA#$Cys*K9!CBAJJ9gd
z_s)kUFMZKx;Jo#ZX<Fx_Uvm=rzIrVsWE|DUZG_!p`eo%%Jg&!T8RL|Ga6BYW>Sx=b
zy?**JYf*Pf-%SDH0KH^B6oT~9aMT6s{iXrsj6UNJ)J5t4w*-b_^u_`@u6|ZuZU+*p
ze@{R|<Mgv>X?#Kdk}~<@^;2l}kf68z9R?Hi31$FI(jTHxAX)!I8azzVkEJcuRQ-;0
zkc;~6)c{M=Yc``3()GVtqcBtdemd-4(HGEQU7+7X+ogs2OrtH_FVat>vAbCBbOog)
z`b#v+x~l($=6culr<McehJJ1U>Tc@$b5K{MKT-@wtMxyg0CuDPG$nL2=~vjowPt<a
zOt{^m=kKB~?&-gt3WKeBz7gte`nSJ8;eCD0cA&KDEuwH#Lein{w}yVFKIA);cIlT;
z62k-iKovwE>J#?Biz6dv_pmU9pE0NYhLy3k^dOI)d<?$1Fj9ItTp7n`ko}CTiY`85
zN3XntO!+_H+?W7A=(;ms<DG+JTfKA<4l|bDV@#6<Flw6Gr!d<?;c6<ggJJ*|nUt^K
zTN*Q-?wWLF=1FiFOz1&?W-|HzgGd(hJ)H~4X0{9iEr)q$F&xfis@J0VdCWwb_+Da$
z=}QUujL01vP65WC?g~>&um5Yz(ch5&CT(XdXl?7t{#+0J{p@d)Z+n1^eS*S+Y$6@5
zaAOxHgL7w{endwdVqNL=aG1SEQBe<e>ntdEvPl;p>BU+v1GYCSm7_^V*ia7b^<i)M
z!wX;b9YmO<A?y}xgGeh`{bkI5r3XZf)Zd3imWVV-eMFCE1N(&N=^Jo3Kr|IwQU7)O
z$7@RP$ER0s0e!|j56FDJi)Pa^CnN)UQ4DRyuXxe|_cnIrL(+cK8b~_4azlw5^C_Lm
zILw&QnXHRU8QpF9O#2&n|NjThe`bgJA<>$5V02jYp(z}46#Jc`CWzB50qrB+x*J@W
z$r?IT6OI!kK#wpPPdRXrCf`xWtw}MW3?l6c?IYNKq==`0(ldom2_#=DzWx-Pi`BPp
z!rMbuuMa}R$Li78&w=e{_2+J|Ay)S5AbQ5in$kd`tbQ8>FQTok(#Ca+)x-m+J8M->
z^W1Y*)*I0DSS#Jh=2D!Y81h1QBwKZ_MO~)V=dK|6R{dW=y~HY)!hmH~K0ia@j+NN}
zP-?BFo`V;4R)-5AdDrSwJ?zz6jamls$m)~1knFMgmQF-Gwi>3GVz1S$gW&qCzB>;;
zpIAkWhu2T7#?W^AGpnb@QP6m9b(p%k->SkMGB2$*`@{Tz)k(@7e`S?OIc%@3zL^X2
zgH}svMm%K2--p7mRmw<UJ6eyWiM*5b7|M5cwyxX{?x6LuDL`?v?xntWw>EQz-XUx4
zGoT!{?it3F@UedNUk;70^{>C8p+~LFDADDZbw~{C9=HCb0cerdpPr+xv>r<@^t0Ay
zN&%B#J?AydCtEMwf)-|4H+DhtuJyessH?aBsS~8px;GG{$@=O#kbBmdf1%l}*2Ov)
zdTHI;iF?ISX~8i&@DM2frU|{L(z6=GU%5aBOQFi$AH(k`<s=ab<CIBV&`(jO?|`K&
zWy$yO>9X?lYlvJ`T2TH)xpMXUkgQRD=n1Y-xs@V}_mz9%(WGwW#uc#pRJr?PQ#r1A
zjwSRCae4}n9OmLF6yw2_)W9cCu9?;kUfe!<L3wjutVTPJaC^$Z`EY)xA>zxOY=ZTp
z+>FWa^BBk6Mcr}EXEgLqa4}y4>?G%Z4SIf@cL@q3xfDuMInCu?g2EZj!$=49qqyC4
zh9a6v9s$u9uD%H{XSoPEOn;7R;~*N#eSZezJa=e3ypQ7skn@8ipPPZ;;<@iBbd<nN
zr^R(5H+u*qiL-tQgDG5w4<u7LpE^Ka<PPLPA&p!58S2ux$(Lx}l)(+uz+fh~fR^J~
zTp%?xn;W3y%^c2(q93_j!g?s?aTc_pe~BA+6ngnwaR~~M-7^k)SGdDR&?RNu!$35t
znmf1`CK|Y5Cn&UWwIku-L(Xdspr3FKt5NuhbN)vBD{g0QTqQ&Yxw;RaKg4C{pmLa-
zNh@GS-k!dR;lcNtK*W<@PH_h>zH1spy!r9x0eXagG!k__{017*j`F|%2A_`c{f7Z|
zoX<R2ehXLGy9p>^ysa38;rtt+;3D|(Lr{<8J7=TtG@pJOdT03K0WcfI2X%mp=Iw?c
zd6o|k26v7>76U`EJof=Q<~)C#lDFdcmeuHr3;d}LNXGMJe}E+Lb9{l4!T(LCb2It*
z#zyGp@C~*o&E@|ga+Pmg0GMlhLK)28;EO+n;!S=OWhGSeQ~J@)8vYt(wbt@)QF1{Y
z|B9Z)R{k9=z}on6KH%>26DTs@&X+xeNC$t{7ftHqcQ}FT;)4r89`Ns;rrnW;{Q7Dr
zcJmLmLgNu{C55FPUi>k<c+9^Q4z8EKHwSI%<3HaAm?!*-UikEkzp@Yt&-obIk?ZF@
zJ_GlHfA|x~OJ4UDS~$QDJ%XdJcpDlKUh~T+pJtH%B_E9#;!UF{J8qbtO><sHmG3W5
zbW-(&K*m`WpAAqKl{ek1uBxp$sPk04Jradpsuy%Z##=RywttVPp3`Y}UsXSCp&wQK
z`wXrfQ@usE)p3>ZH@pZ}rR{}6glZN|n<7;+E`vL*`sv|_5u+q$REtjlG)nb~W?0dx
zALxq4s7BH8+_S24Cz&eTB@yK?AE!#X2WKv*=F<W;Uge3m8<G>Ygg`Gz6-oa{Ct3BR
z4P1)KY67@aRaY>$i>lK9;?AnX70^ppb;Q864Am=&PiCrSTu1+AseYl|)NIv`5SYzT
zy`+u!T-9#6gn6ng<5%$Ml1e`TrTHo+Jv2&Hj+C@grW*Ap>MB&XVxV|SmG%w_t5g~E
zg@I~SFLhqG>P#>?=#i@G9gtV5+cYD4t=e`M<_A?X7Qn=i>VqFpIINoO2n9!Bo;4hG
z624dt@0|sUHY4o12(Kxe>?(xqfx-R4T8j4_5TbuU-9h2a(Li$(;>Q5SU8vm;{X@de
zKyV(y6q?I;3hh!9dI_5rLC;$_@dL1rVA~jVK7!k2K>G@lZlms~uv?14W5T}OXwq@v
zt}VszPY5BtU{4C8odD`5*ylmtU)VDrg{OqebS@%5cul+P(ZX_?3&jX;e~H4g!q-c|
zofDM*;)=uy<!0c{3mp@oenD894!iM!Yag1FAY{|=qD0}xtMDR8*iZSS$--{T%Z!rH
z_ka5tElhkrjPkOR-p?$7i*6J87Q#f$#7+}{Hcu?i0nFgkK?*4hP4z#GLf>i1l^}l8
zdSapHKW#0&R05_|o&#9&w45fGzcTHb8X^VL^5;Y3`ZSitnf7U(G>?w{Xkr=Cj*T=e
z-qPcZ-&+sg1Nyc>+5*|0VhS&Ith<lj_Fq>(dv~x0@b`F77MUZ{K@k8a=1~neXQm(o
z0*9F7Q9wD&3|xf=o=h`MDUUOSGXQadk*-CPgPFHzoDN|oJ_i@dY-H&SRWwun3T=&H
zGHRiCmI+&fzB<SJG!39h%qlutp3FR^TO*74X)U;Hrui+997cZ|dby10VsItQk<k#j
z%J^2n;5FuW9ZXzjigHm`#Vj2UuxjRj1RYSrJU;*ncbKQ{l*7}^%%lC87AE!^kb8`j
z!g;OC-jhIUWAZ6Y{XP@(2K;Vk99vM=!F)pgb}}YWsOx1u?1PCuMo-WB6GleSo2Sg?
z1a#0drkV2V2AMt@@P?Q$It)9^Op1mVj;t5Gc#Tf%!wQr-vsN|0c43!L2B9naF2U?)
z6KKVBfc^e^m^jFK2SCJ)by^5)clP%KXyGBYAq)iHc9;!G5B3du33##x+TpJk``ddU
z-s}t?kR$9?8sdD|^R%_@%X-nI;HZ%`Qv&T6dy@9ukFzo<WKOVNlnZc@&7^E*KQ>??
zO!%{YGvVkd_FWZ30@%tU@F|eZpNpOiVrRUB-C*|J_n>!%4V6MNiml2<AwCV^kG90K
zGP*Mp*q`aBS|VFZXBRVA<8g{=WU^mUR3eMboek`4Hu^W%&0#;M+=oK8bT#UV*oecB
zEM~JPXjQ`2?1cVRcI5YP?HU`u3kuiS@#leE$L3J(!d-S3#f9rx&2s29uzue_ubI_$
zL9dm4{uvb7*eoNht?siSlo8a<TK!1Zmp%Ro-0x)T|AIyrTWo>42kZ{ozH=1aw}-+(
z(KZeuUZS7uVB)w)GYf@*BIOY5Mu>XX!o)dI;aC*Lih?3Q&Wk3|EgL7AN2!AsM8DA{
zV7zGD6<VQXi4q%NB3m@@90qelC8OY5t|*}jGI^ph4eBn5zP5z<%OVB63$BQEQK+Fn
z)Q|>JD9SqyXNp8eHv_v^R9*x1O3|8|@S;wnv;#_uXqy-6Iz>DGM&V=8#v&;6i##MW
z{tby77enKK_zET69u$|+{KHMWWHvZ=v6#-n9}*YS*`CAVWQtvRh(GxjoS(Sz3H<dJ
zU#D^7l$h%QN`P3h93)Vj;19b&;`Hwz5-eV@4tk;D78)VK#G}g57vbX7$aFSJBE-{s
zffgwqvk#T0#eL@J(lg?7JE52;-lKrS>0%j0(DK9|&xB7!;!Q!&zbSrW6hLo_57SM4
zSL}$@pyZyo^aTnZh$S+JJQV*<`Q_c>pE|)k63?fFRFBx4UV)FrUs1Y@u~+<b2Q>P`
zi3^}VBp$l}UJQ#3FCgkDVf-NDB>9ZqtIiVfUvSMu5)}yrSIM7rh<Crlht7T+l&CkO
z&Q0Re21$3xf-ry`lKi3vIV|~*22&47$G@oal-N?B#Y^(43fxJfWSTQ%{3M;lVErY(
z1_S1l#FQKkkj$cOfI!KDJs?4nRWyAG!2wH1hT?w*0wzpS>WCJGOGeVJM}*|-U2rB+
za-I$kpO!?^zG|H0<8p{xknE-CSiHpXQ`9Bk<NW|jlo)%Yph*(Ze}Pg-%Xz@0NG1ot
z;foUgspy0>N&O^n>5|p7XOto7ZiL-TN#r-^nJmdf+Q`k8yt5XCIg-)a;AoMgVE_h;
zB|ZsID3Rn+<ov4SsSC(8$?vN`uH&oxFndGtm$3#iHzktQxQ3;Y(^H^dE^({|T7{(V
zO_;bPvAqPpD<x4qD7-B>kp-?wvNaX@)so?_;cty(EN!0Lk?h$B?E8|bw1?6zIsZPu
zIwbGYth!SYb`fpqlFZ+Sx(5<Z8KAo*v%fY%|B=Mk8=^gu?NN|<Ea?kGVXtJxO^EhM
zevO0OVaYa<bd)|c!ciw_YaaBSrHc*&+eKQs6LqfAqaQ(izf^k!9v+mo=pgAPz1$6G
zcWK!SaEGKb%At2y8af%69@4SfDTeDQJxr_FQ_|65zywHJ(!d2uhaNyCNLoaXVX$=i
z_uxXLqiHA%l}?~t%P^_-5Il^K#-#&0QrbaFu+!4PKVkliblDHE8zmh-7Io3m`yJ@!
z7-_aA^v+7l(jk&B{c|qm5L}jCqH*%NRF(_(8>DYN08FEF8O=rprJ0l^A8ld?1KJgn
zh3kM;V6xE*g?CM&k%Na%VN5v;^)8bxS|aqC+@_7#7bZKB0rt{l>M3fysc;hthfIBG
zH~X0B`B<0_G5wN)YsLiAi<CT&Wm=dHyH`vns8M>?l%WGOy{32k0eVn2K-)COWHxos
z50@Fl@FHI3PGRvB*+L#7B{D~vf?k!4oeaIh@>V)h=q0cD8=SX1i3N8=-n<(qzVZ{}
z;O|lSQp#;UZj^`9t#?AsJ%`_?<Pu5{2#{~GflQ!$emi7><)e<m!w~szwlEkWXK5&n
zl>biyz0-0rO^c%C_hnE&C*QChb#ZcCCDaq-1&82olH6hu>XPNN|3Y1=+@==XMR@{c
z6r{<GqbW+AE}uY;_%-=68;~1v$1-$6nY^3^v0HMp1emxj&zS|#YWZp-ytpGDF$ZXO
z<*{^=Hp~Bb01;=i#na)htJ$>za0kr7DUR-DHenmO+smw!2CpM#8G*2H%uF%?>L<+n
zjE~VL{$@+)v{#_na5qf{@uRx82fr89(C*LTW#8lXlJRu-cxgUmlr9_X1_R5j2cf%S
z{`>fQWpg;nSG|`G)YW7BU};UvDwzHC!3g|bn@-!2>%Q0F_j>Qq(E9EDc(}2lRZjat
z8zUA#$gsyAt+ikAA^zUI;|L)3I32{_4%uG<bngV3Z2en05r6MnNSo)z+&}TR6XWs{
zYR=4f%9M9udNfe<Wb7*8tQT{EhJSBn?R(&kFdv@+@n`;-2$56F^Pd48U}SQBLrX6(
z`3AUkk=aKf^<1Vq7mX@nYG~jtW$s|v`~SNoY7G7eVH<A2bSQfu4}f9p4BD;?XTLcP
zV-al7EjSv@27iUZ820J|;Ki{cs$la1`&}lucy=!3My9YlLpcPgYzFPLUu0jpf~2v^
z&Ct(gtFgg?DUioln8;=QDSCE=HQ5341uUNk{X%w3F(j|C6;7~woi(F0l5+Mky+te7
zkX(3vi~W}7OqJ{^1w`(!U0;B!WwX4&)v-4zx6;_eZX5<}W*5<{qlG;=9{Ts#?0o3A
zvb9%Wx09`*aAp^~h*Bkc*kKwdp0ce+pzw?pp99)+_Bh=zuUO@q&~wCxp&<E0w#6OY
z_)H$vOZy%88DbPP#11oisdpUN-#?^L)roa<L`$66I8t_D-%WxwS2p}K$bQyej=BTv
z4a(*_$olO>f4H$xG}(4%J3~=-i0z@xmBZ}a8i0AQ8^456Pqu{Kk6x?|Z9aRmdu<@%
z&)#?nXHT&yNvI2812O-kdFrHgSc+jESNvbRTBV_N@ZwJvLwHH|LRehN*F%3<*f5+}
zzL7vyoOOf?E7O_*ziK;$B36&1?d~<7WdiKiXa~rz^&JC`)~%qer}d^cfce`V+L7Pz
zHGS#e_kR#uF-kV3O$Nl~H=UriBY7r_?c`~=+igd$#ywT^kpNfbDjiAK&qPrU_5mjJ
z2Wk|v>2nx7!i=Gec^`(cf<wN{L_HJ&n9nJRIgmNmgdPfFQgY!!2otsqh2hK&vT~Z4
ztf2KzG$Zt(^c*vv=H7A47|NF{WirTzGR7txEhuMh(YN9%7zO1r-(ud_46cTmI0G>C
zOcO1tTA1u(AYIHLgSuyoJ!MP`Fhz9`8D!kv1=uii>r+5GvAu5rC4~LtFba*S>~_q7
z|GPU>&vp1Cof-WBlrorqH^Hq;=JEglvzS%1Lz&IIqAmIy=Byaa%4I@=ft1Irq(ycK
z6R(5^SDD3yP`}2M(!Ft=8KOO_8;l(l-ei7q0x4x?QvyjDBiyDO+I!5s>FBanrj^2e
zZOn%c0P~3XfVOaY7&GeQ7tFgf+P`F~D74|s?z;#{7uJ_1^RBFt4v2WN^Bh3D*b3Uo
z@n&7FK+=zW%MZk#b@~E*dx~9I4HCijd&7JrTZurmQF5C7nr1d<*a>S;dV$?R<6}H~
zc?uNM*|-Kclff!3!cr#NkqiASHilLY1*~-~3JclRQ&1>kA5jdlnEiwdma{9?!<h<p
z_)RF>VxQ5FSIKUobxl2+Nnb&0U|r6j&e+Jh(yiLWK6!=8W_IZ$^iUV;LMyljY#xug
zhwNVz9_nUi{tWVnRqld*5BunC=s#wYXdkPW{bMf_`q<7B@aYLVNI|uyZ2oR=&)96r
z_ePqT16=E8AGW~J7p(ObwCtsk{h4Od1ME^t(8Ksa38Sys>@`3eWa}xN%R}VS2#r%B
zJsn636Mef4jfobmB4-jr!^c1hM1QV9;T_RO6cXtc{cjfvoy1l<fEgsdLf7ts_~Yqt
zCQp3mCNN9I_vqkGgV^|T7Zjg}FaHhlN}QMQe?vf-L_?ckwHU-mPVx~=&zmHFZ%5Pb
zNm^-Ha9=Wh7eu-wv&v!g5&mg8Ao?U1Js{aHsapx32PBi;0XHm(l|a%}>ih8sv<pA{
zc*>br8rnrs(&am9P`fh76fmn@XkPv6@2RNXT)7nu-r}Xg?_G^fz%x9cgk$?LJV1AM
ze+Vr{rZ5TZabntOIC5uZ)5g^yW(x&$e3@VV0Q^zLnqpu9jAs+LKxWM<)I~CK+SoX4
zWLEzdwqn-&0Po|Nug6040`n~eQ7$sed*DnO6G*ShbjJJ`^fQ>v6qn0nPCkV~787&`
zTsHGdDxA+@-rEC_T&8M}x|(q>0J+4N(5xVzQQCoAX7q~zeTB*T0_p{faXIBs7Bc54
zl2^oJZG=oQvz!uIN|^1G@_Ln7H3H-svx0K$t~0@V&;>V`SlW}l$<)}Ru#`D}33_GB
z+B+yLXRIy3RWMvNoT+8rIEtRDV}7MmMt2zx0fy?COqwM(Fipl*xY5YCpN333vuq@=
zJD7f2t#&d3#r(RMe<(WmfYEOQ_Cv;%2TV8fwg}uKriuoMc$T4U+f?=tjU#Dn6eT5O
zu*3AZqAYfW4<z&0*R({r%x?M>Z7F2MjnqK)aw)C<ud`JYa4lsY(RA|``~G@p)Up-M
zkh#Z>+z;0rMU#-d|NlqH->I#E?9fh-Aa++eRD;=wQUHapYbj0`%1)mJ(_!quUN{oY
zW*>lN1gk88caiKf7LupgGQ8|C=onXi4J%RX$&FBqW~Ws^BZeJE1MyjQ8Rg=fV@qWa
zjb$|yq&Ux-oQGr_>qXPS3v7r5EXA`4l#rCbb{kNa$VLvqwTtWx+F8wGzY77%CHB%X
zV3x35dr)_k?W76OHP+uq`_|Xl55Gho-)7&~4)ay)4J|6GSy?=|8usF4C^oSzGttmy
zb|NjeTi70o=G<e)Q&_N-_1z1FHg-0hjlIvZJD}Ij_FaWf9qi-9@UWAO-wKp2c8dul
zAFyB0f#!#7@)eqYbhBRXL-Y~5Hx-pVtWP9JKYRN%?t&NWS21w-B^yO|(Eyua3$$14
zpM5BN&2BA#<RGh>0W!pPdZX@uXq6t_bx?GZ#!PQfX9M)GNkySzKT(YeBL1StMsQ)G
z1P#Ss!bN-5L*uMyIqg`U6HTU#sw9ym?X@I}ZnQ!)OSJYNNVez^&1MQjM<^GrQ1spV
zz%CN`o`7VT=&A;!Tog|MstVC)N+!D{T0;YArD)S_)ZG@1q{F{eqM{>kty=UqJ``cZ
zM@Td10^Jdf{TDK|BA;*JOr6MgBnt0}Zghgwi)OfkG>D#48cL&RD!tX4M3d8i)+`F8
zhrLxaIv%dIi56l}iLZ|4=D~csXdEqjyF{KeKYAeQc>(UBXybKAc8i80p=W#~y4wNT
zE9zSW(kB|Z8rV-nUxh$)P&C#B&2|*eqBK`0aRQxsbQYf_5f^bZZNRvS?~a1xe({r7
zG}KMJ!UC4u#aVOFGalm54mjf}Hj9AwUgG<72YQQ7?Si2r;yr(%F2*R1pnUBl@v2N{
zWQnIxc;SkejfTv1aYH-`ABg+*(DjvAwZjWH=>_T;4{2==^u44>G+Q_!om~&?Q__3!
zC=8H>xqu6lZlb7UkksiMNU(I#ePD)4<E-ItxO9L*S&>rXN^^jok;+DpH`2-bQF>Nd
zWC^?Hq~|F{8Y{JEg5r7UH&@W?3(|-@ka(%@F@PpWz5n^YsWtEWD}<MRN-MTyu~Jkn
zFE)jx6}d~{{K^vALtS<JE6A)qOj+H(XFUeaMq>;GXE!l_fY~g$523%Er$S+;p0X--
z`O{Rv5OV^*?JZi-sNFwO)Am{pLEe?|5vcE(&x&BqlL=W#J;EHb0E#zbq)tD=WHrNi
zALirNxO4oOz4RJA#XO-0Jb+0qrd_%~=6$-ygP8pLfR1N6vS95Z^UN7&*-R2mp)WJz
z{{$&vnrQu1$~28fH{E9bPJxeg%y-{`Yhj+Yz?lck>Q)p!XP!%d>Bx4{bjF9ZTm-N%
z_W$*EC2mn1S-k6Y(};kXsPRbj3(){-A_JowB6vi{3*-hxNN^lSqauS0;Kn1feu}7T
zG%BPt9)O7_Xw+557*XPxLn3RUQNwzpo2+3y053HAd#wLL7U=KwyI<AxbiJxq-RvoR
zu@R{Kt=B;KSaf#IgWVP4w_ea)BWCcnzfZ+?5r}!Mn9H@{bz*ZUe10w_n;^MKIC=Ql
zAsSYq1v|wjTcPlUXyV~|m)OkJi34K$aA04GS9q7!K~ZuO#AD)q7huOl1lLSYi|gZo
zRg0sYxfXt2Oyz~PpT$q%uy#dclmoje-p_)IYhv6kwBWj^<q|+S1sEVwK@V>8B|$as
zpyfNMlJD$a&|sdI?4or>fZg<<6~G>H%|gq*r_$|ExI(Hg{FSJ)xSm?7x?4H_EmM2&
zru~iTQWbtbQ`huD&wZ{I@RJ^!RDVAxZdT7aK-{9z42W!1+k~No+te<o9^t;Fyou13
zYes+YKGqKNlyQX?$K&iu?N}Zfx=LHZ3z<b)1kx+FVr?Mbl0VVPkux~mr1m{;L0+wO
z=K|##Er)l%f2u{s!|z({5N8<$`a8VCu3Rsk0lz!-X`O)mT~Fu1cR#*RP&l9u<hQyU
z(#v*3<gh-9XGm3gY91ty>b`9u*`#llkX-8C_!-<+xWCpBMCU2@?fZd#=e{=|QJizn
zk9d&*{z|hjKf>U!b`RpZM_F7RZzSUi1oW8h212?}b(~Y-4u9=Sc~j~TZ994-%Bus;
zqeTsTkIv#9jxlAEp&XmJ9eomaKL_;qNPekOg4MYR%4yZnFq-~N6WH%w<Qm_5QMYlP
z@nj?D<Hrv{0G4O`n#QS*-op8`0bI>@)Tf{Uxlj4Ix;Zs9pwGP-2CV{dup`(DMZ<A$
z3We)Dh>OI5B>;=XU9RO+h`ankg1y4uc?2>C#a1qXRS7dMwVV`QpMrQ=tndUlD+ap|
z`vuWu5CXm|>MjDS6P?|G-4SjB(9%ZH<v8@7i8L?p=2KM<=q;w*880%H_P$dQx_Nb5
z^u(|no?hl@t<da;Vs<vK|2z_1d%(<75f%=k&BDC``hSR#{8-Lk>Bw*p=hG!FQ!Suj
zr(mj(DnEdyMHF=zBCF_UPDzUBtJc7F(AEjSDrwpE7rFKsYAy!l0x7(S`678;g~3Y{
z?1ldL#YvT^(5j{U05EUS`ACS~rrx~s?l+oNjkx|zQJD~}ryqFs{2yBX93ea=ib4~f
z(5b};c8S{IF~Bml%mv#k)iZW9vPk`PKJ<#!U1-+-Qn#U;Y&{U3c`(!<mLunNqW2cf
zh0iAO#!A?ID3%WdcqI0Qf;gYnk8f%Awwd@umr`ml?0!UjIn6C5ze<?@gz|ajB&p~E
zh$R%s_0m$h&Dm-hE$4pPNMHO0$?YUV;J%!GGC`q&j_{}K+)Lj)f~S2nk~85-^5?SP
zVe0u1o=#F_1I(PFcW0uH&d>_34AsyYuFzbf4|(AIg~nZgwOaap5{Un#5j@4eOa+_3
zyF&ewp?8%garOHe#r_EQ*Qu}rzzvGBp=I}-)IS66AJFSZ02*i;Cn1d#xekg=<jb|b
zM`Y)>Ks}*l{8;Hzns)=(eAPPw!7NaVUx!GkI*m)g<?5Gp2nMf#=T(BARnJBkyQ2El
zLF9LJHc#;y)!T94JyVmugJgl`oXxdssa+fdqvcxN2w;b`TF&dvXqV~`_YJM<XApg;
zjd~f@{^oXyXFA1hJL-U~bqimPm^QjC<c-8z@t?9lT&I_CF=m7Q11~$5=s!loVX2<>
z7(KI1Z_SxWxxR&0%PaI@PQLf;)X(spVYj~J9I*ZRiLr>nrI%Qs@uj|G5u*4?@74(#
zhx94E5ZYmV%S||}(tC0m{Iy=g*YYv_b_b{**IT~~y%YLyE@pnK&prf&YQ34C5d1+u
zKMuj1(Ie+T{YO1+11hX7m*()N8_?q;d~U$r$ai{xII5l}h*6R8phRz6j2K2&@i#c8
z-D>E@2GoNax2zgk@$c`1?S!)D=$OPi57G9ddX6%=^INc!a<mXpjoH9e?y+qaKr;0>
z@3kD4&gs1~EpakTr~B1`{a*OXFp;s$4Q|E{{uLBUB+p$YoSFqu>+?A<G;!ojn6L?6
zGnzDl^MJ`yOL6|bISTYC-8~^W)!rB9(<)Yhn_0k@()5k1K+h5q6#El1yku{=j$WD(
zzHceq=hWQ=;#lkt#>}!<oX=hzj2P#MPFz-BB&z$tNR_~*bwx=;m#NAgT`qboLc@%M
zv$Hd&SS`6z>{$+DV$$e7rXhI~Y$J!711#Cu#v%5sTw7MI!)Uf<PRVxIjM<ralczvZ
zUTYR+pXnB>-4W6^BPf7>O@XF9f&GH|1cjJFjJbAurbEtqB3}PL_~<A<cq(T7*^ZVr
z3%@_x2Rf{SYsoV)?UwWn@oX<Y%=h+lwY^F6>g5|I&mM&}XH^^;4mTV+4tE@_Ts3Ds
z?0e*+Zu(2|>S1@yBhK#d>0vS@_jDx`w0@Ex$A^1Ix|UyPy)xA`(&V|pJj|Hvu;n<6
zR!dH%-C-PRx8_Z6`JfZVB#kgSvMp9yMy|~=-8f`$Oz$C<oQWBu?Gy7dZ5fI7Nx3sE
zIX2@^+l0Ky@>(#xy8kbp#)oZ3B$_i)21h5GeZm4;ev(}Qb}!TSuJz&G)&1qd#bl5f
zr*%*H?Z5PPvUG)eD@I$%J{}&OWZY%l!&Q~<y>QlR{en!rgF*rWd-?<g1@s9B^1)?g
z3JeW0DT*uOp7+U@e1fbKEFqSOA(p_v(6AtrC9tn4G|XzU23vzBm_kBA3(cYpj+b0!
zVJIBn{2Et1Ze>a;svv|hy@sKeq9kJwC#+*FWB96~VA)=wu8MMxp^u_q-AbYEih==6
zAwNZ##IUELpuDQk+lq34p;1w=hf*O#hf;|`!HUuuUob+3iBg_I{S{Z#AVYj>Q6$%o
zGQ`qp4_QCT5JNXT<bWtcjA$=EiZYalzOr|;Ay!1lxeSKNY6j7+uA>bDg-DX`#u#P-
zoQr{l+BVWJ7MkfYFBU>x@&tnj`AS@irj5ZIxetK$c9VKMoYi)dDS#kvif0SmWfP-b
z(wqR{B3TSThy3NO1Qzy}A&KB>vLF#$FL{o^0_mFsp@s;Vp9JOtd4kdAYS|&V#jq_I
zLT}1_42q;%3P6%f2B70_%FQW|=^`7Mx<H!807S@Q0BY_jZ;fH6Z_ALe5E?2A#)ABl
zQJ!ZsSNf&`tqqp>sV&?SKtX+F9H^)J$w}itO_%!^Z3vfo8ux6ZOi45J5@Y1NG(&fh
zDL17V{4tu6azp+D6gqfUHl-Q-gd)498~o|cKshWOXq=o56!8@UsGtAgEsvxdeBJI0
NGAIk>y;wuL{{p0sYV`mB

delta 127949
zcmY)W2V51$_XdpLy>095RgE>4*fo}@v6pC~i9Ob+(U_=FV~Hh+@q&sX0#XE}D2gIQ
z1UrI=3Mg1W5d;(zL8S>I#opfMkl*+Hzkff;&Yd&odCr;H-6>~g363B3K7N>2D<<c7
z>vGmHjuB<edrxI#6Ehi^B>VsWr()D;T}7GV`QHkeyt91}N>vQEs|hbt$yKg@Dr5?u
zSY9UY-((t<$l1wP7@10`TKkTZDYCs-nS6Ycl~kf+vwO;ADo&MqnnS{Vdxw>om8!+d
z|Lj18!7Au8pTUsb)D!x`E?g8%n+Y;STk}}@o#PwJwIB0EFHv@#IS+x7HO7jv8;!p?
zaq=WtM&nOO95G3j+4xh>o~Y$yHyeMO*?(_~vRjS6?K100-{!pSC-3XLOlF%rYKja#
zbIL;%jEtiSsyqC_z`$QhC9YGJvoc1R+gdJ@D>I!@Uzy@oE9i7ljD^yF`d|8z{@`>D
zSFa)wbP9{FH*alPQlN%NRVD)k|Cj?s9@+;KLB5xGyCe3MO2!Uoc@t<EGcuc%u>)H+
z){RO3jhC^5Tkb~z$DCISGInTViNvJuRm#}mjTt@j<e*x{j%>`B8C!Qz#(vY1e6ch4
z_98Q;vE(zEqT^nLjQviYgCfbybq$ik-j9DdSQ*z{Iu08$X0$UhUp8ixjRv_sjTw&l
za0|`SuQ4MrvDL_Y-I&qK6oucZW!zxJM9@i}aU(<ph?4(-Y*eF$j9GGnmvLhnGfHMy
zkV?jlZOm|u_P*nOXv|4Whk>Guo7kAqGvjoejGNM!F*BvTlrnCbM2~}Arr4y1-V8-J
z4BB^Y;AG6q=A-bt$!y=&qNS5wgQjn;LX*p6?o_E@&7F~g%%sv2oc^`K|4gu9pYJ@e
zNr&D3D%l&QNM&;GbuvwhBWhWN(h!C`{j=kLFl_MMFLpQZNvteG`St&F`4PSkMY|*6
zvPu@E?E9be4|#BV5!sRdWtYoUUFFD5`Y*do?Ke~<i~fJjshyiBWk;13deY?HYh}Da
zEy`S#l%;>Y@jnynzyl~J)2{zB{YN9t?LVBF+~&XZ{a3O(sBt?fzoMHd_g*Te+u2Du
z_P^|+Mo^dk83U$pheD?Qe~pc7G^SAjN;GO^-~TU-TKV1omxlZQ(R?;mh6c}3puq>q
zWL}LdlZb^L*c?Th|FO_RlcV_ZzlQi--SA!}%T+YqU%B_6vgUhzCupn=Qi@Zw`%h_I
zV+G<A1OKB~A#3rXn^MM1V;b-6H;tBJ$<nw|UN(&x(D)l%T6zRq_N#^NXN>88jak^J
z|LlMIpE0BU(_h-yE-e_k3692R!1$X^B`f<MF1iu-Ic(}CpND)X{Y2~P>E2cR->q9G
z)6(l?{0C3%{{JB#HX{G}A9DYo|3m7EyF+U-70A68HS&c1$D{OKr;k0kNc*?qvxDPR
zGDUNN1&2)GD;HJf?$gyWMKiU^y4?4pp=m391F~&23SO%cb~Qn7BFR<i6G~pD;B+c$
zT_@ju#-5|L%~8mdiXp~E8s&dvp^Qn@G$aU$J<R{f|F0lIXZbI$a?$_3O9U{Sv8q~j
z@r^MqXYTnnH+{v_`c5_VaJbK9(DRaKO4Wq6FOkU5tSVXII~A^_dJGG)TldtsCYGU7
zm0dnh3S(xX>z75o5pW&<mh^)vNaw?QDxI52*qVQ+bpFpIUv>y%gv{rHi0j@Yx|T1d
zEAI#)!1&+knpjSv`#b4()L;Vqk*mP<eI&_;xDwrc3>_+&ASVMa22iPUKaza*fgBof
zo~}O+CH=fGVmNk+P_ONz+3`6^wlAdL6Qb$&nc)rs$5{zh{xiXLdXV|aIpp=^1~PLn
zk5q#`lIF;zBneqhnq3A_dni(<h30J|hTyxT>3o%R$_9|+?NIuC=Ng&x!?UE46;}{{
zmrhh_+^2LP@#spT!1<(<7EA?W`jYvZ-w@s47i9R$4J@u#w$Qb8HA(KYBF*A8q;vB&
zIq}amDxGtNc;Y&fB=Q-Rb{$2(1OKF!IDL$4y)7jE&67l#LnZrWJ{9l%oK)xP=_>6d
z)sN}qd)oIzm*1U!FB(rZc#c6<CClDV@--FYiane3f5Ql;k}cgqZY{Y?@>h>Y=ke#%
zS}n%XHN2c8Vaw?E?|QH~WTjULkYy#0f-A^O*Ty#Z;U+2lwU<n`8cl8)=Mq@6oh0WM
zQ(bFZNYd;KX==iVA#wsaVLwiid!xv$@l_-d8=tUA!Sp+{J25=NxU7;nmL4FACJ|)#
zR7d)Kxf2of6UbyrWAhGLLBDTIq3a(tq}h5c{kAkZ`j?I9w(H1PhbvT>6*uVjkPLG1
z*T!lzdq+C8Gst|MmaMEzB%b9C&qmlWD&`v>w2!;VueLYodgd&-BHutdk6zO6i!Deq
z?JoVU^d+6YcaoWZ3}kpgFlm0bh)QpuV^YaB#!@L0O?Q3uU@~cYLgrsJ-oAkv2PvJI
zKtv<F=(lYyT~#ef=@);xuGY|XaxCe%B~a<ucJ$l&8<CbZKDJ#O>oi~<86Mz9PMnxS
z#*BZGB%>vv>d+IbWHU5W`t@Igoj69M=imD|WtvvfJqyA#6K2ZD<h_pc`wByV<oQHY
zc$?(r$D}#Eg03qX4G*s%9WMt-((aL&i(gW`^_U2&WarWewWx?%Zj&38-fl<C)ro3)
z{$n&$o6Rax-H2HRJ^5s8+<hY5(AfFxc}~A0)kM+pFKX(0o@8J_9{mnMmyJ7`LD&ns
zNOS5e`khomr9H#QWbgpG#<-A`+iOVPvMsDQWF@uqP^4nYh4<1(*FR?wovRaFqkIX_
zSx@q<iDZ6A<Gno9o6NgZQ$0p*B!+!9l2lJ4iO!A8bGu1Wc7P;r-N}6EO{!Qko|r>V
zQK{n_mWt=6l7SoJ>H763QmSfnqQgZp`LdXFvUbo_C?e{mJn6IwB*WDr{a%5I9NzE7
z-tbO7{r)qWu+2ESdb}j_&#%#yai-E9OR1ekI<8V?e=<D*wcnHKqRHgfZWkiG(VUdd
zrIXIijimDlBPCv&Ayfll8I{i1PuEsg$+<J1NIn(wZn*e_^#4jClL>7IHE<nO@Ax&6
zk7-Z(o3suxS=8v!`j({hV{5u@97@IKMp0dxP9@m81tcHQiNJ$b5$Q0@l~pqLS#<4J
zOFV1+>9=eZp>n2>=Bi7CT|a<ata?qqxAdXPxc@_r_VrQI^B*&tnsLNuWYTpF{qEW5
zR)0)aQ11amBy%DIO~*7g-8K4s{2&?Iw3<+_TamnJG#QxIm#%#!(&-XT*VSX_8hn&A
z2lgSh9ff3mvRO{g|J3nB^st5so;ALg#f?MiOw9c7j=m!&ru{@s>Q_ZDt~2Qme@te^
z2NCJhXp$&mNdMVss;eS_O1XG49O*;y_l-PrACr}f?;Bm|2Tq5qVj%(AuOh&WnFMed
zN`M8&$gt;T`u$xcT?=HS>GU%>5uHv%5i<z2bpbh7|A|O5W)n(WMv^w3glgZ7+9r7n
z$)_gJwQW<9&u$!992Nf((dhm}y(^KfW8BEV@;H)T8%Mu?`Ge}W#fiX<4J02nk0{cA
zBkB!}{hAx5jB43n8%f;1qTh?ON?gY+=Wxxt%HTRMg4}B5g{ivi`cVPbkq#Y;WbXv3
zx1S%?V6Zm<3cn-+*^SeXd5zD()-pNdzuu+iqx~In;?YaOM%57M@zvzwnhN@TLqpdO
zGScj7A?Eu$X^#GlDl^_pn#$M2Uwqr4MuBG$0ls=l1{U`v)%qFa;}>`#)v_@i$<v<)
zkmds)YM}#VSX0QN`;yLJEJW3^+4JZ|%#0@khZ<*mLz_}-g`pEu%dE>t{-!r!|FO~a
zc>}f3{F27!Uyi3*En9_2qgwVC*5GQ{<sgFD&y&eBx5=&7J*mcQ<8#pT5K#xtqMAKF
zLWX0#so7seh*Tg`H3|I%b#K2Ji!D_r`|oJg5%GWF_msmSsOZ!S^(g%@#|giuIqJ6q
zI{o`8pqUZW1isCDy%N6{d~gEnx0W=>tT+-0Q|kh0is`uD9Fon<lVK3KGk;%3;?H!Y
z`NnQ0tQt=4VHTz$7r@m0i6oF2T@F|f6Z<2K?q!myV09m(?uDBW!mK_>FZzCF^KckG
zz`W0aYA6#p7rq{3YH6%E#3XYNhB50{a35yEv4T{EGlyx|i(n>?1zRLz>H+R3rqxIQ
zjxfE~!}DlnXep?VG9}b&$1n@efisq=Pk`_kV{U=mac0nYYX1|=23O!uGJ=4@Q_MCG
zaGz#mC9r#jVGIz)F?XqlKFb{T1Y10l8jf57BPPTAIVSEP;E7DrNC?j}8PvZfF~0=B
znF~zHTd-VY1nP(`F;^m>namUh!+Z+U{-_N7PZqO>?A~Tpeg(VPO#fMUGIN*>yTE;i
z`S&~!xo{utb(eWE72Nljf)wBjm`&8L6*A_|NQ#;Gr!e@4N!Eeo2@|sofHI~l4JPGG
z=U!;vD&}e^aMeuq8whKde=9-ec+OP5MxAOI#jlXoG4oy{sb^k2gxv-vIv!;&7<L4N
zFB#iJAYL)W)yTbO>f6H6w@gwE48CKAHlU*KnFaAE`@|%F3G>eKpJ*DjNuKHr4|mAD
zJ_@jp|Ju)>PNetR(bWGgUr&ARAN40-X~l+bVRq#sdSq8+48fv|)Y~v$K%@KLD^S56
zC4sp1Ea(gQmk*o6Sg$+u?Cxg*u+nK%R~EEEZPj~d+ReH)2O)Pk5)yux3b6<xY|YW2
z^~JJp(f;bqO!|8eY+-&yAFp<0nw~?owlh63XH&Z|)3ngv!9=vi%ejyFYbMx2m_3D1
zdBr3Rg<BsO>jjXx$aCjF(@lPFBz*Uie@T;}0QrJo<U-^L9%z7A`S69nU6AYXVydpo
zFE(J=iSb9K(!F1Xf~I|zL96wKiJ<F#e=FpJS}@R@JnKvNw=D7xT-}*e1zb4Hv{(q;
zMCS6}sAMLy>?C@S24=+W|7!wa!VD1Vr(qaSca~?Nujx{W;X&QiZv#4$ZnyqM;I2C&
zl`^%X$BX``T2Flm`kgPAaA>Dq@%Q0$?~p(=ZXe|o_|bR!Mfma6iAdbdeuI*5?f;Nw
zCIj+l_A)}d38mkS-VMhl1<)Yz(}On9S#)POcvcQ>kJ9zO8X<RPg4|F!SEls}aQiY3
zUI}>rb~B6V-41082v6dT4P`-khB=G)tNJX{=zToX=zapz=>IvUu>y%qV-3zT<h44P
zX{<;JLp5o<%R&J4@s?BBxHbtUUz$~g!Ryw3XW(hO@BT%5c5oP*qanNU2o|e)%6)+B
zH7%Gbn7$a!4BB}Ek|Fvf@MvV8nehGF5LzSsut5&G$)*1yI72tk7Muaf=5xB>_vc-x
zpYM2dJ+6H^c7^dF+AENM8%#^j$-mHB=ft?uRN9&8>+k{5Cg$g#kln-VdjawQrn?JV
z3uH2ATn}a1{0)wSOe$hP=nnt7121BjNra1Kf}g|gF=mAXm9xzA62RjbdlWPinC8P_
zHI<243&3S2>?Aa=FmuCEl^iC9-sC&X>n!SjbD5=GfG=fI+<_=#mQZENnR!~MzGUK(
zfq%s~+Q8szCTBB*Tje*KL35kj{|yYf%J-Wg^q2F9cB^*FFZ+UQk6f7r?+?q5gn%qu
zzH>RsBIMns0(V9punsD5^1{`${y!_95Dybq<Q>}pktQGh28B1}Nfdy|lMihT;eGjH
zx@QmMQwU!oFFuCGEtT6bimIN<J898eFXeYuqApGf=cOQXQKSg~xGUOkgQkaK9|lp?
z9>wcCa0V!rwT9*)#n^SU{s~j;8Uw^}MeJo*I-xlA8%QrHv}1u!R;<Ltz3~>eQjY}a
zbM`5+Z4Y%pz1y8ygQyo353k;d{0O-hY>l)g;P>bc4{`nNob3Oe#iqYcL;X7nKZCSO
zMJ}%0pLM|XOUL=vAn0?1f*JiHFzl<o?z|Y1!CyZ?dk<sB!r_tsE`{p2lMJp?hS0b?
z+d*ryU*z>DT{>(yu79M}f??I4xv0ZAb-xLyQKEXXD~z63cOQ$QRJ9*f?3%hWLXN82
z>ZDDubyv+S_np_??0EMPmGkCr3_;l`ZNEflp40yP0;at6JtrZzOYd>&{~q=jrdu^U
zDPY=XgZDn8rLB_(%w8I>ikU|ycvix^4a5WXh-n^%WS2bQ3LNp1cZdSvZux7P8tsvn
z#UTll5B;dXT?mq=wFKK<x%?%Peew+#K(k-o_ebOo$S=i1^`N|V6l!`%?!5zEo|f;6
zL2^bOLJR6Fd4FGcaa(@>3QXk42R#Swj=VAlxIFm@TBGO7lfH)Vo_q=g3<~6>^hDm5
zZ|V)9<AGd}3)P46TnbVZ%NweYdnCWO2&9kYTPXflDnI!Wl_`^V8v<d4e9IC5E9HGk
zKvN~J?Fm4&{Etv@J1PF$h%#q|xd6##MJP4U7De|T;r&)cK{cG&rl_OocZA}y2w|i{
zF@$c;ZN;cF$Yv{6u%Nl4*nS@da}`^oA<S18XvKI}F=-y0DNxL$)pMcZyV*z{D3&h-
zyhxF89Z8Aei`i&|M~bh)k$a*z)ET%^#oYvul`Fo=Last_kOtbPic8BuU8Qi$A@k1^
zr~QzvQGEXfs<n!ZCeYL=x^{tTgM#k_;S0q|FXUb+hQ2`6UMoCk7<j8Fy9?Yqg)`On
zgJP@%&5w#q8qS=Rznn#VHz|Kz3ZaX#^fdrmm3wIl>#9u1K|QxCmphiA7CV&lB4E&6
zsiYpuQ#qK1<(<me`2cz=hXg>?M;Wjl=65OEYN6?;>^Bf)yOra6AlaiVpcq1s^3E}+
z1S_2=5Vub`IuBliD8Hq;98h`}qAXM?KMkM4lqN*@Rfm-gXD|w@B9tY6!na6er>#I7
zQ5pvV5v{!42e}yKgBD<mRnDfU$8qJ!!2q668izo5N*R!YN8q&b<81)WD(yeRnRw;d
zZXi3SoO2ZLL}lwXP)Sm*CbusrR~|(LFDZR6*H<Mg)mNw&OjTyG@Zz#^Mmr>F%J5sD
zNmoW*g6cJ8sRe#tSEi|uVAp04R5FzX$G~<=={6WNS<36aa3)*XgF>M>%D1;r!(8Qp
zeqhN{x|jgCt6aSc$vtJzJ_rky1B#K{SGv1!c>ju&8{VU850yh{(fCMdq9EsE<p5_S
zrAq&<uvDh(au+5ll<(U?SgCxOhoo9LrV}hZQwIEjCV8%WDS@R{dGH@_*DEi-f%gr{
zmxU;MshsZtz$@kVD?#=~xn~$O-zvLhfYb3_`C$>->w|LHe&{%<{-BkFv#MzsfSXlA
zrh#UQs&h-YwpF!q0@`w$s)q%3x1&*jb5r%@LF2CaNexX8)!G>_u~W4$A11t1pXkN&
zQJoqCp|9#v98~;O7rudo-KyusuovJ^8EAqXsG2?;+`%fZ)==H6YVZL*M71y(4ZL6F
z+8ZjNDwn?jJgADvqDM&e!2r95RjXr>i&Q0zhNUP~2rV(ARklOWJgT~S4j#s;HbkQ?
z$5c)tgeO&=WuQK#noFbO8I{A94ZCrwc7?DTuSz}ye1fVwt%?&>W3r%gUgfeD_zNn9
zKkye-U1+wIr}}*ta`~!nXa!QBS~Cc^LREbooOz(?^c~8IRG(9DqF8k{4Db?_j`ju~
zt1JxMexiCvF`_b6j-wU4DOUwufu~ODIY~&I)p=h-xLN(+H~6$g-EktE*{VMA6%gCh
zTjqjhyLwF;EV-$djRUubx*LVMJk^C1Z1PqYFM`lV&8EPTpW2-Rz+b(JLUnu89q*u>
z0@QOZK_y7tpLc*JSY3nluIiS0@Id6U)Lzq}nxpPdbDBHqF;n1Eo;qs)5c%piF38<e
zKcT65fqHN^Xx>*FIwSW$y`?|=eW*@WB3G;yDTwn(Jx>qn$LdSrs8Xp~H58m>>ZJL|
zRj3cd$npMFsz)vZuu9!*Dpaf0hO4mjT-`?w?pk&CW1wkJ=UxTyh5AA)G+(Q){|YbO
zsMDXK?7e!-V$|@1`YPfCs!wVg1%{m1%vzY(#Lmn_*=BYs0v4(m_B07&*)H|4aGV`B
zjK}+Tf=%`V+bK5cBpUcM`|t~p#<3SD&~cWX#KLX@o4W=y=h$`4Aw18%p?#zz_MeF;
zyU5CD^Wzdbn5L>J?DWY{No7Y-^!p0?cOHakY$63Gud<&XfZc1X7j>vN*l3)EP&qPK
z7YexCWTPlhe~ZmJ44vETCtBrav-9aeyu&`~jU<;n?F{aGwp}H1ciCHV+}{Fr&<l89
z$jWFY_kcZj8nrKC7f*+4#q9ABuv^0Z{1gVCuvIR|m9o+iuvD<CvjDGjuv2J5t(tv3
z2GVD&2euwnwd{%{cu~hrq_On{`-Vb4FImS3sJvk}Yy#jddz8YiAJ``J`hR3c41*U=
z+?@UpI&+7%Be$7LDu<(6xQ!8TW-GV$9FlF^nDzi{=d>9x<i<JLQJvhm<`lB<;QTKl
z*~uMsg{l|V?jPWNxLz?p_;MpJBJtyTZH7<&T*tHUDVa+ch-#;B#|I<1!gX8)VH&rM
z!n4;n3Cl{=b#7KNEM;&ydN(t<@oLz+#T8D5FpC@N7zMU$?lLU{bGXyHK$FLHcLgw?
z`+?^D_qe<{5EgLzcEbDvE^a@7MO++hqm^)Knm0b;IuiF2t_6-|s7krtHv?YI#bOn$
zs^E4|ANZ6@d5pSLak=5}@EP}MEC4lJWDf^)YPpafkkoM*k5JgamD8TW3vTLY2w!vK
zX;<<M_nsy_@3>bK9DL8ke*v~nT<lULPW*<6(A>n&PD5@p-$0M03qPA0e=EQFIuciY
z%sy0NJKuLDoY}!!>R`d0e_O)h{qy8Uc>}+bpEDb(-n=I*fPMI*0if~YQ=B05=WnOL
z?jGJqk@Wz611&p(`4e$q+snrUK)9cOng^8w{M6gX9pu|PP?tk|Da}+5^PQ<j3+GKf
zD2wFhlpq(yTiXkG|DyT7XqI-A_u-Jl@>?Fmw_|)ydJj(W|I$wDDgLwR;6B4Qlp~4b
z4=hAwa`|=Cr`+WQ>Kg9x6&C?7<dcsexzCT847){q>_Lz{<TEHj`-tD!6}ZQI?rFGP
z%3od!oTH3C{XIx4c<&oPRPuF$Ag$(Kc7x6{epL)|wR~%YQdM<)Rx0ofyo$CdUhwB>
zh4G5l&_?8IzWX<*+B<#;nSamso&mcb`RQlC`H8<q0dQwwm^;We3C(VRdW&Gzq0Gf0
z*r?OqCVV^(9arH%D1dH)-(9Hg5Yp?Q;~{+UFH}5*>5n1w5^8C7=Pm4Vpv+ge@GWq=
zge}v7^A{rYP}wc42?XGTAWVetq+q7a@6$rhG&I*4p&P~c&I;cwffw<D<K;>?d`{@X
zpfFL$x`o0d;W7oHF9<DY{(4Dx<p)d2!YG<2qzajO04@vthCwq;NQ_5Wx=>LKpRNg+
z6lS?D+?$MCrqG#|bvK2YkpSElLKdSeTUd4l!aKq>EmU%aL5^;)lrOZh;vU=;X3v6&
z0zspPYN4Qf1f3$`!e_`m6wYl$ElPx~v{Zd0bfdk*C&Epd%9ILS%8`@{UFSkrAp~s(
z%Tqyq3c@O3FQV6~XF@&gnbZhdCV;F~_~J0i>V#vv=_zdx{;q;0^rPP+c`f|lisX$j
z7w5xN?}YwOLHb?@rwPJGq1OWdJ_!Xz2%W{Iv?;ks+-!jNfufF<Cqbe+JqdfoA&a51
zPh6S?XZDMw{o%y{@mLJZ9~3KTig`#pwoy3)Z->}Hj%>L2;4E|^MN@0!qC~L<z-aM4
zEuD^v7q7!otXM!3gkxfFngE^<hw!j;QY@o==F{T&eo#3h`n87Lv!c82@!n=fR1j)?
zLG<Z{qKo2OTDK*Ob+d8nQbd_Aa#zGvF=&c3v0pH9SH<}gVBng#l7XK$#4YoY%MfkB
z$lVmX(j?`UIBqM<-4>5kgEL#yO@R-0#BCmc=ZZP`D9aa95ZqVY6&E_10azf0FG5Qe
zihtFhDi6fk?$9X`ADjTNSZrPZcT2=ye**VoF*^XRJrP51K&4Fdq{pdTbhQFrDOSml
zJQejvk$e#C;UII7n*V~tN79T&oB2vJ+~CtLX>nhe_mlb-ksJO}?|MjgOU-s7*(04z
z2O>ZkZG^!fX#;Js1xrx|c(GR+9tfZINe^k!8zNZ(k?fa-^#tyKWN(LDsFa@wOJUNb
zR{$KAlxBDsDOJ<%ca$`Odi5L9wmPU}Nb=bXde=-Tn4b8Xl8w66TT+u=NU|i)H%M+v
zEB{84Ewvs8M2>Xc3j7@@?j(|2Y0!Ekc~WnRN<NfEamW=*Nl#Gw$I_osNXn%p3b<Aw
zMbWl&rF8BeBu}NkDP~(Gb-1cT?^-SOTB(K&{MTv(Z6maCE&}HB$UA7^wi6N|X}2K*
zm1sX}KI-0KN*l<(=tw*G9cS+VU#D{kz;^b+p(Rz9J+zqW+KOu1Eusj1b-##B8&!|*
zKjGSQ^awC~nSTeIy^Q2UZ^!H*fc5!#2mpP5x_}ydwW|UK`rV^|O@G@$&<#jL2vzlU
zzxU7_c!ah_292OF=n#zHGS$#xdJ>0CJ_McN0>$Y^WPJg{Bd70%TVpc@Lq7e`HT?d~
zn>HBN%ddcc6LWP85)TK{!iF@EsWw6{gjqWtl!urxze5<wM9@8qVLIMm0mpxC>{d^x
z?O=nc-*jge(WbEnyNl)zo@@XOc01W+?kMwO11UV>%^ss5tq<!@(+^*^+!r3~Vkc8f
z(2pJb7wvKQvq4s<?q=PpknCZHc%qSl*ozvF2D7Rj5QeZHXx6r$O`!<m0k(=7A(RcF
zb$b~5iu#em?A?FiS~xo>3S|*&=2(<PvW_p2M6rYB!HXlT^8(n7X4f|Z=TSBp3k?V6
zyxnP!BbNPw_I-}AU#~>rakdAA_)f4|3ap-Fe^J21DR!iQ<TUHN9j$YQ{ha0&acq1&
zglE|Z8j#}I{9+^t?5>q?<{ay_3vMT}E#2VLd3JUp%97Z_FOghei%vu6NM?1^P$}$o
zJv>ci7hFT(Wp?RM2(PfALtr9}T^a~y(%B!M!R}Rd%U%GlvxmNdi5u*gZb&j%eKJ}-
zlXdD0_)YfUUEpr9j0P-O?2xaaa+?jLqc3;Zzlk%K9ZIq1JO}%3JJNhMbRbmkvOnSI
zt?C|I(;BJ;Y#WN;6tcTjAidB2OXeT2Mb}YQ#LnG-CVj|;_JlLV?DJM&DPgPV-alef
zi@@@j<^Dn06LunPx0kZ<tzfr|T}-Q<ayFaHR<Mpb3Z7Q7i)ab=ls!O=U&W^MMPW4?
zYD4ZBJG%(xYuNp}kUVFN7eHFecBU|W9eW%{h*kCM4HFz~U~jqs_kx{r2?k%X>*?6r
zD|T2LsJvyrEkW{*-A8BSKC=G1q4|job5w!UiF;ZFsWUg8#x57G5Qji94`1Ys#FcCR
z31x2Fq=mrm;FL6!xN~*;QRcx-p-oFqPDL%dlN){uIWI2g7jSxWXSX5e!%e2q(U(ho
z2>34UEsvZZcVj7XySYFQ8eR8rX7Vk7YkCn*9pD`Ek%V&I-mrU+>rK<GL);i_9jL;%
z0O}48bH_#8(Qxia15_foxf-xUas{-H7{y)c2;mW~c{F^A=FZd9<|wy^4noCnQ|bIe
zESD#T@EBJdPG@|Mb3C0fI>E)B1@I&%Qj?zIZY>7sX>KAdEzWR<@1iZ^xG0KfoaM^Z
zs9HQ1d;pFnaL*{ve~w#EGmS(psSn`ix#=_$OyVlTP<Daqw-4qoa^g|sE^*DMA4=x>
zJ)!q6g<H1;g{j=SFW}S_u4gZhrg3`*gDstNS`G78xq57%p|=a8{_{HbOAg+u8{C7=
zV9VgrXuQbeHj#%nIlrGEyv4Pzf=U*bF%p(;b2n)tIh&jK5Gpy`^D*GO!>w(D#F5K&
zr=B8@E2m{ZKDUp~)7<4gQ6T6Zw~!9?6>udJL0ZUZ=wZ3ft)aE`15VrsM~k>}3(P;{
zX8VD=m`gYdmJ)6V1!*2}*C@X6m=phm<`YguhnY&bp)|uO<B}-)R_@?p?NF`Y<|M<L
zO77eVSbEBdZBSUnwV;(kH8=P+>^|c{sAX%oAF6?W&aI>ANG;bo27o$l(o6{JxuX~1
zS_3z0J~Ur&zfupeiJw5nD0cH(|AuBDf3O}^3gW$Jdn}lDTrWYom;aXfxqW=N1bhfz
z&^WI1JBFd`0N-^XJPhSq(iYf3{u+&lhxmM2-i7g5bCDe8^M6AU&JUjlcmzL~-o{A2
z(_cuUcvpJUkMKk2EKm&JmwJd;-j#MMkMV_$O~@YS>wkvM34YG!@cSg6WJR@4@jrRO
z;AuW(ENIT~p0r66$M2+f`z&vv*ke53i8_h|eoF;BJjee)PeLN^Op}}Qyx(H@l*F&0
zQwSIMEjfT+<oEPOa*5wSQ~YFJ7D4l$6#mcQNK*Nr1UPe<??Yqt72e|oxYPJdn#QN|
zw$lJ!<y~-aTy>3)KL(ZSd?fX@H~2yty)*dOBhbv`r_f1<n|$_VIC_ika|A3|{K<Z(
z(rrF{Djdz`NB;$~9R90#8vpL_MYKto%lDwrS{^@-HgNL!ZJ$B)E+4rNmhSPk-#}Bq
zU!ud7h5R!w)agFok}CRuPoSAc5nr7G&4>KL?~p6zJ3GUt$NaSkAbY}(q;8{>Po<z^
z8GmUQaOM1rll1;o@YZqAspOv>1@I{!O*?c|{F?j7Rr4oW!qPK-T}J?G_|NIo+H=0$
zTL5bL14*b;9p7~|g!TMPIt$pqyX6D-g0G~B_e<V59>Q1rgwMeFn!nWtxi`E`hc<l6
ze`kajj(7Y|KcnzHzpg*p<OAP64fv0|Ne9wT{6EuS-bpBL4OM5sF9@WYgl{4t+$=n-
z1=|*3mLD`-gmMp%ZWZb$fMuJY3x%euAkazW?Ls=OaovQbv^L%$d_hOC+=Y+@DD!X#
zf$lKqDeR!r7dwSE0l<3+nY8ENEsQ=6ppWp`Sg866?M_0)Ul_gsmUauwT9oY(k}2XF
zAly5FBv9Bq63zq(SBW!NQ0riDui$V;vQM~A17C<xO0B(Lkh%hXKybA99obM}&pwzq
zC=9iO=8(YCIwDMXOYyqHLi*RR8!jZ$$>s<lb_{ZnLYyx=j1t<>wEl=Nxg*?;7M9}s
z4b@SBr8RDhz|cDuE0p&J?wGI~Uk<5`3$5t<*a_kKQ8;>1nCYNt&MD#MU1U!SKaNE1
zjBscu@NvR%3Rs^NJZZ5PFTAdShY5n?Hwe!O_8&l+DCiDCcwXom1!0mf{~R<g2rDX3
zc2Sr_3*SqE=TG2F7CdNqmm=KohZm{BMhZV)7LxyQz|s{VHwsRr3GH4XNf(rR;LKIQ
zJp#FF!de?lTo+zrl8zPgbAOcG6ed#e{g!ZL4%#V8SaS-bw}rw!(99MFT3{(hm`nR0
zcZBYA06ACK=LUm$f=+@kUr2rnz+J(85bbW<6UODBus}GYg|tv;O-sT1f*-|-9tatc
zz!wQio}(5Ig%1m$QY@spp{zt0T8Xkp!c%;hrFty%UIpP3q3#qkONE})TxG&5I`>m9
zd^!%53gNRBD614kQbhi#koqG<SF40iYfz_Z;SEjJo(W&fL#{@Mn~UVRuocH9uo^e`
zfTm9He+7KK5YQQ#4MMUO!WY6G+D(2b?C1sauY{AdQS@5aK;FL*-mFKfy%m0(1;9Ju
zZVJlY3om|w@Pok6CWYgpaN=9k{*&;2I0~J_5;EZ|c638SZNl^bCN_)hsMFmd?l}P!
z7qKga&9{m<p|HD6Or|KQtLT~nz;^K}?T@*OBNqVRAr_58&QnaKV3@Zkr`eT{IBzWM
z`idd6_2BOiQ+|ccZqb7x3wy+Jx}!m&gN_;pi%SB5*ef<!hh)E)N0ayiVxMg=7%E==
z1q~D?4!w@tVKIqf0pVhd1iMipLtV-daZD_P(PC$s2ObsAW<xVZjCus>Sh0yS;KxMA
z2ik5sE}o4+azd2Pfu|=$c0W{4iI#()IW4xNT@^e=6y1pvk9UPLXT|wp0K|(ejv`4A
zCtpU{IdN4jEG3GrbWZ8KIQ|53Nn*qkxP3v~QVNxeV&?Z~-%H|kD^!xj@xE<GnH^7Q
zOX!L?KLS?M#C<)`66s>C2Q;pV&ql%AHE})#=B|r>^aaTcv4r~Z3^6MUT$y6O2snLH
zyowJ*5PYz#f=Ah+b`)|s;?R*u?ug~fK%FZ#-ws20;_NTMk}uZMp7CArO9vg5yeD?J
z2VjAC$qJo9F@RP>_eJ;3(0L$^rmsng#EbV~_o4WVp1)#obOit<q8IH+J`zXKUg%@7
zYY*U_i2w8hXQ?RP3$ikiRl(76aS$EFs}M_q0jLxwd4uz*Sjy23XO*}+7^Kx=XdI-^
zMAzK_)`)#+A@N-Nb{P=0;sBcZ*NN+C^sE<O8ey<OTuGtM7or!<s$Pobae%)PH*7)K
zYcab$JbWW2tpMPyc#)<<@5Ju+p!r_h=Yz5jqAZri;E&?^rf8^7;$O7S<0Oe$z&lIt
zx&X0BdO@KG7fJID!mU#KYM9t2Inix$m7XmEV7s*ME*y1}5_^Dqhtz5WaPCqJowxFk
z;%Eu(DYaHZWv4W&37qkgI?+i!Z)wdM8TtSpsfNN(zEaYUK<tuU(&->S=|@`k`%8Q!
z?CzFs_#xRNouDry0;Gx!pb3=fhC>)6osj?!maMdeyjR*r`}g~#nKMBaA`PRFV!xCo
z!2AKpw-?$lREk~zm4i}Snn*YfNu!2CCrnyE#}5um%YTLWaA`>$auL#kMMxs0!9T!K
zlyu}1YJWs3xC=nE^b_s>9hLg70!@t6i;f<~N)e+WJSI)nfaSQ<@DD7VkUmm3eo{I>
z0sK=^GzC-RB$v;SJL{0n(GE?#^i3T|6Qqmu^~X8s!2{GOQ7T>wn)A}B+h~g<sXPX3
z7o=K>e_WJi)2Z1@(yqOLCrh!k?UEvm@I+av6y5_SE=#e80JtKh_C%5<jp+(Ny5tjw
zva3=R&8DtNj<IwM?7B4k254?bDa4&2B}{>8rnH}SzHds?Xw&zW^uZloWJ!HAaP78~
zLFdl1B@a59l_OcGtG*)*`2fvasZ}D%@}xO5-sMXl`@!H{sq1Q}+>=7DfU`g<7=z@2
zwAv90zl)?FilF*Xx-tjJBPnbl%s-aYpQG%Fw4Qphaw#GT!V2lbApk3-IW(A6ODk5v
z;4^7fJa9GA6Z#IQPAVJ+gY{CxF=#eOb<_*IkUpe><)x%CA@@r9Jscjsl|pJAP<<zr
z&jihT=`x*>`5>h-u=G*-lO|rDBsV3zaMDza1GlrLNfL6KG*^SsPMbC6NZ8$?8PNi8
z7tOyL0obbf?K#S}X=<sva@EYagI3$F5$SY^n`X)@l<m+w-U1eP&C_%a@1KX}cM4E@
zYC1Oqey7HH0@%DXs)O*<TXQfMCVVvG9|Ga4S<($EyEMPgMdGKiy8!2}ne_)qcWa!(
zklUl#*c(ZJ#;p>y57g9e13XA0kAzCFW?B;@do>deLAXy7_yz5-glJyUNV8wFgVw1B
zPzwM<HP<&ncu<o;5%EKsTeRsEra96D+=n&(6ps(roO^*fMQ9X{;Ao_#Kb?Gx(u@m3
zeUE6WzJ^M)<}lrgqnh(yqAW)9^ffeNHG}fNc|zm!0A-Gonyu97p3-#t4hG{iLugau
ztR{?niq|})UNb>6h*pp1G-KkRnW)K11^0Ok-wI_(8rN>{;)1650X)2@iT@L%moy<C
z07%w2b%3Q5O%VmTQZ)<7;APF`9nid@>3amYG>7J9Z=~rO|41ZPHDeNixTYziVDxp3
z{sVwFG##74Qif(Hjgy(0c@z!2so60FY_~Ksj({yoGrcW*x~=I&r<Src#z9DOG;g9&
zc1QE%UufoP4m#nc<!O2y0!zMT8#QHt#_?t`xC=G&=()PD=@AWs4>X&U5Ef}x&w%Pf
z&HGD89%*J$XYg3VB66#$)*MIy+cQn(pJ=BVO=3EP&oy-vhpW|?DFRlfak&W2dd;77
z4y8ep`y47SH0?^!hA%aJ+MyD!G~YV@fE%whP9^}~X#SzF%UjJ~tC4%BK|~I3g(eNB
zRaGA}I(m&iYO*LI|4GyF1<X5XlMVymtaW#SrA=BlY?-SzYrmt_!4~aw>h)Z->nN78
zRXcAyl5JWwbt0}fcnSD+?c74z;dIm9TLr1Rc0w!AcxdPK1gWQXNe*asYG?ln6)&w5
zz3|@J+#x9Q(e7T3I{9kf(*d$w+VmgbnxA$KMI8LKYv`QnZtdlsFt|rMo_47Mw4Z*5
zFi;ynAD9GbKWhq>V698C0`K2m?J%0`@6(p4K^mg{FbjU~*Y2Y)JPv4IGRTE$10uk7
zP+Qmp_(R$jG@A?4-uMoH!&=v2a63{vXCg?WwDx_-9nmIX(_Iy<jco>%qgss#fEaB6
zb+577WqXi2rcK5y$Dul|JwO`@C$!lu;KfPpO`LwlS-<*E&^fJjD}xtjw0as8<FxUe
zfj_G)q!Zrp+HdB<nFMX?Amq+zD;2PtsJ#{m_<8M38dH<B7bx^~LHlYe8sVbWpF$Lu
zw2QxjYsuO-Whir`Xg?+*o2pGb0E3sc{XBucqTNZ$#x(870yJB?_WnoMy{cvDZeP=;
zcL(6Q){`FO8`=gM8#A=O(so{^wjO^JKy_0q83DMZ{gZ`HS=trR(7dgcuZN@A+IGVs
z%+db64Z=GP?FBlrlB?}YA*ej<_$y$`*IuP#2lupn=u_PS?S$iCE7X2LTZQ+v33Lwl
zfi{<p*c55Ib%OArb_<1oi?zSek<k+E_)c)<k#_z%7<{bFZ9wjcb{egH%e3x|n<Ls=
zHV7-Uj*CNqsMO{+faa;zkH+mPtt&+%s<q20<o!&mZUOEZtyf3jpKJZwAXls1PAyZX
zz4HOM7utLpj9+S-(-`$iTYL{?ueE8L;PxBsOFB&OR@<2lwY}5+I0kON*Xq9l?t^xL
z!vmxrwY}z|_Mfy<Bak@hdQh`%*1e^#0k`N@(}@`uUDP$$-KrDmx!9)bza2ELI?vt6
zZP)#F4>&j7xY?-F4&4S3n(n&Tr(p5WIijHAsngPg)mt~2){s8BPp1L*)va4W@82$6
zK><wo>Gs=DZGYW2w9UI)mrC=%J-X0|@FGChoW7I})GeisHAr`vq9DP#)F9a1t2_KJ
z4DQp7tAxQ2ov$-+`*qfzVfTQ}h1w!iH<4zl2X%dR!O$VyMtWGnbY;(YynlyvF72Tc
zuFKd9V1#Z59U_X<xeSDAluo3hk4JQ4sez((XGX&AQC+V<sKn^pshwhV9bUoGF<p#1
zOdQwke+x%X=&HM;?4<68J@EIGE|Ge@(>jX?;TfIM8-O_7UwAwms<XO*yI?+E*LfO9
z6Li0ifp6#j^C?O9ggTQ8x*l)9eNktih0i5j>OAC<bu}~{Owrxw0uNJlUvCBXWu0RX
zEM3vfHp4`^?g1S#xvC5A2rsVbPE+4`T^CS^+zs94NZ=e9x+UL0^`>sxC}eNxd|c58
zS-Li#19%%x0@$*31OI{-IXXW&u#>0TeiC-`bvwJmi@Un>?IFCU%lr(00^KM?;8caW
zgrR7z`#R(2fIrY3?2e>Jx0p7?9_kkT1V@W?4YYMu;?Sig0P#pS?-AG@>z0&(`-$%O
zH&89reL>?vnNCZ~v2vZ)KhUhuS?JVYr7n%`;ZxoHO4O-JS7rsgT6gdsl4rWI6-a7y
zlga^juG>OE^;+Hg=kV#J&PfJmUg^3}tn9VU(ef#zZ*={sh2H9%nuG0~F6mzszSn(5
zXQw{sw7XFDQP+(=o&BWa2;ihY6a?3t^}n=1*(UwXizwTy??un?7JYA;k!;iF(FZK9
z`ZD@Fb-O-~<|l6Y(=;jFp~o>Xyd(Ox4w_PU=r5N;>Zxxs4arWu4-LjX`si=rjITa_
zHiWzM>Ks(YPyb2|p}+pzQzX0fT{?nvkG_`nMFaH5=%ozQcb)*wApI5`0Z|3(dsQIW
ztG`X(CGOXMNxKgR^kpoBp?Z%9`fTc;z8iJLhxA5#-J}ZBS88z&4(r#iLY>0(w<vxQ
zp<f#UgOU2IGT@{1zAqs>qEDztEn@Ulcc2-ocfE<+F@5zIs2tair{LNNeJAR*PU_Jv
zcn|awXqV-*-uwgnJ)?iTm-ay7^b31I=d8Y#y4iSrjx!1q^gZdo%{l$Nhu}`szZwmn
zF6h%~-|nJ*)CDx~C4DCvp_BD2ZRn)vz2z{Ust;QZyO;G^{Gk=q75(uTl%?rg;4r!B
znm$Z|`Rn@I9-zLVuOCh0Uxq%e7}89=8%?Hf>aQdNaZArnLR)0%zyBU4ZtK_3iacAN
zOM9+4dars2@90k-fQfv4`78kL>f2^P<(_^&?Qa(7OS%AFs2@x5+57s(e<OLISE>Lg
z(klhj^Pzs>Ti_hU`cWF#Ezyssuks%0htfBdrTP>au*>wlk^wB&yIugILO-t+$}06K
zvEY8HzfSw2ReG&I3|8y&sB3tpKiCR4v_@a|4#MYp{ZHVm)!!4rQm5A!!0med$AzG7
z(0@*|t5**FOB<YetshV8xHtOGzk{W>`kBYT_D+9W4&i&fJq5WBdbJ&PKk9#?DbOc<
zt0?3)8M4pA(q;os#{sq&a$2Iy#lX_~Z>u5G8^Udd09pgM8qSoWY`dXpHzaO`vow?0
zVQ@5?i9&b7?o3EM4C5K(ybM1N0I9d37$3r^d<<&3&Ax^mbjDzpL8OI{pW)dg0Q?Qp
zXw!YSVa+k9>@l=V0zAObm7d%{!{fbR2{QD_fyzEZ7=6wbVi@-Vxc!FauaF!tTyPYj
zFx2qqA#UtJgFONbe8`}nl~<U-K`+T+!*)815N`0NorwrTWEGk#(y;6h3`QGjPJ#5O
z;bS3$F$OOhU1ALmFK{0-e4qjIxWQu&ESxZ;)A6;FhO&+D>6C$?vzBp&``ai6d)Cmj
z3#9P|?Ih477&bfr{+wauH3$<8Q?rpfZ*Z;xcaovw0st-;#?ZN)iw5NaB$o^w6i`Vv
zY;Ih28?r`$<%(hSH6&?<Z)s7NZWz@K2Co`6{EOt8p}Q-}t{dj|p&0B9!~5p&EyM8h
zw=kG#sBVTj-8Ag)3*jxp7YtOh4X-aCmtzQ|4gNcZEoEquT*H}`$mJR0+rf)`!)l73
z-!=52pv*mk#tmczhANs86dFd41K_^l;|{PqFx1nb`(i_;PKNid#L($i;2#;jr*+t4
zLy<RtPYjzgkdzw6>VYUTOr);A+@Pg%JQaqkZy~HQRE|TFR2y<=S@q1&g?f(~Lu3c2
zJU4hbkgGKqM}wu#uv$W^)f=990MKBt(n9rxVTK)Lj+ch7F2T1~hEW$m`qt2&BIoZ6
z+F#J5?+qh20r<g?wjO044Hrg(`;#GycD$U7rSt+h8?(zH++<9l8@t(fg+7YeV)Vj?
z#VQwL8=AXpH_n(2xSMf02lG3O`4pXYH;$&q%EMtCw+whsV}lMl-p0RY!LE<-R|*sR
z8fSh1on1!Z8NBc_uBD#M-&l7T!rex`57_n?edj|n!06H$@Id3dsjwSl{3Qb|8f+}h
zMzYtqlQzEg8TV3W5MuPFIOKk#GaUsyU~~lC2WhA=h9<5DjVBdo=R?M?Gm#53Hle`%
zVPke*sD>L)BqE70eobeRB8?tbfQvF7yaCc9#<#TX5N$l7gYc+vD{YL#7>DBT@2Fyp
z5p?GGm~qhvxOUvgQHcG7aS08WCyil_Il!MXz8B!>X=5`D@Mnx02Llmj99@h$oi!G8
zKv}#o(ieUw7~?jf+UJa2mmo<rPNOB$dE-G^Yb6;sb^_T2qly-17mXWeN8^%l;xt%F
zHmV0hCB^s)?Xaa9<7ts}*|=DwGXPhNA>V^L&A6rqa_PoZe}Ma{@v~OIUo*~H1H^S>
zO)AQ67++_@!wloz{ituIar<|mxoIrk2otxA-_xc^mQmRlpfWC?MN+o$^hA{97{gy6
zxnrD~4@0@ehXKIl8FS5a!ZqKRyBEN_#s{aMbI<5Wolt>sGHs0)8eczx>V4yHG;TjI
zu6PNRBIB|k<Q^I|H{ndNvCB75DKU1SP54K~6{Dc?*m(UJIG-3(zd%{3aUcQ8j32*7
zuF{w{1)5Kd%kU`*_CSo?O5jwrQTh$ZGh<;>6xJ962O@cHoEL{`*BXl{2vukNw=3#Y
zZ_F`(t-<KI4<=q1*C)W>OJfE#_bX#wAbfglJboCtH^!#3fqQGr^#s{F<9-^%-y07d
zfXWAB<yufXJ{qe&0RPEYPLWn8Q;vk2=WOalLH$i8Z~Ag!v*`qjvMr|B8v%4N4WQ}Z
zR#W^(IJ3?48ATUeO;_&0`|YNI)HAu6qV58|!_;>Kyl^*_xk1yzR5l(tPZPHS@SUbf
zwb1l(m|jt<dz%*ag{MBIY4o=+d`-){LAc8_jOHnRrprn2!r$adq`OTi)V=R9g;2CD
z!1VeE0D&ew9W4(sP2u5Tu&Ln?;CoG*X$NSZ>2sQ$g_wrWGGV_-Oa06N(;swnDAeSr
z^FsEZ=`n=|51A5amKA0?xC{;-Huc<xT)1h#XyhVHc@(gXG)44B5@l*fpUxdIm1Mv~
zv}w(0<c^vS(}}AX(-Yc%jx~*ci?U;;bJV`aO}8e)(G#X4wAXsl<hmMdamp0pr~&tB
z)5X?E&Y1i%fR8iz1i-{ulWP;?;!XbsqGc0IvDLtzGqt?{?nKiC5j5vbYiMGZWV%kD
zW?nG$xeMGy)9_0Gq?i`dlbdSlK<D%>oBGgs@hhfiS}CTPxFK*Y-E@4c1KF!4k-D^N
zrWy|1*G*^E!|n~!bc(HJn11>P+?l2h%|Uw8wCoacw@edqfzL7>%LDgq(<nP?m~C>U
za956L6FpvcOzkP0pKChN61hCn(eY5pH<k8)%3ag$mB`&Qy?9UG85fum=v%Nt)7Wpo
zcHdM(<L(2KOBEb0GL0RF+(XmHRWMj=IyD}-64PJ`$~-bXw1Dlg$w)DhC#JsiRYR%i
zFm=IYro(N)S#DZ65jCqY@mV0NH0izp?y2bp9YU)zrQqZP&On-m??(2SX=M#mYfMdJ
z;l*>)(yrjHHF?lBcAY7czG101y-Ej7gK6m+l)W(h8;azmX~;<kUzz4~g63<}&#jTX
zG5t&9?pxEMworLza;F*ndsCOg@cx78;RvXFG!@a)<@jXU{T^8-bC*n*a5l3Fc(KWR
zHXex0=JZ|A*<!9g1E7of*6&c+YOZvH$~N;hTDZBImGlRYwwo)vgT>7pLWe?jn49Im
zyt~=j1uPzBh9c;m=B6QF*=e@Y5g;$~%dP-;JIoX4aEFh%)mZ5Gn(O`n+b;93Z&B!H
z9`_p(fAjQ-X#Cw~4b8Xrn3YSQ8DPG;6>S-8UPgW3Ub9OJl<hMw=1~@6&i6!azqu`a
z&wIe!CLF?0bNgCQA2gq%&!!KV^VY+QFtcMh2kyh>AI8FqaPvlrKtz}~HG|zq^NZC0
zMwtWX?EVpRAKICTHV>hd=23H-UEq!}`zIh5YhGFcm1E{JG$tQ6f25e-3G<(eVB(~?
zdmngs%6xYQR8E^)#R71~yp38d&K&5Vra5b_*@h(E{IWAt6U>=L6rM9D;LmKT63v~}
zNY0yUXw{Hp)>A)s!QA=;G%tb_$tClzA7Lrk+{*$JDdt6+K$dDQsE6id^9|~tu9*Ax
zgllQ$XgdJu=4T<eKUdAazo7Z&HFK61fY;4+fvD3BbJYNt&oFmBgR)F>m${(1X%1Wh
znp@@{jv~o2S5l1Swt4Xe;Ihpkosr5hYiW6M$E-|4<L8>+q@gU&Tw9D>zPS&rZtj}Z
zv~0a+j-3r>3e3MY;I9#?3e5v)v2))%D-PTb%twRZTakGq&FmkVUu$8$*z8-1vJ!J`
zDw0QL_AnfMZ2p{LQBTb5RA`o(YqY?XnQte-wQ}>6n<%R=d(mEcrTHPvPoA11>Y!O=
z&U^{;)#k4{)B5k3d3_~RYs?{Z-uJor9<A?d&34+&t}_cuq59ISrJ3I=bID-fUz>w{
zp!voeeHLYJ&A}DWd}sdJ2j<_K-3G$o2lLDJ$bB@s)5+~m=H}gTN1QCZ?w~HtmNCC0
zx5<*f4J?k$mT*sGw^(k`!q3Grg@Q9%Eq`tYew)Rs2F|!z)_#v_Z?}|~k+@kNUxvRs
zECH8M=5Cog2<AO3Aw%Jer{!HCayu>JbL6}%`^gz^O91WK_*e$eyw}%qo6e2wvWyBq
znV-Y5ISc0fEvxAz*=>oZZS6glA=6+fz%q6cR0A#P9>@h*TG7)TY*E<3w%3wOquM^p
z@{>>rv2@KxMfY2#ZbR7tOX&fSg<5>+9XV)uMkBx>%O_g<hgrtaA9^}$S$`dx;TA_E
z{e`&*OLv-6M_MK}g{3G<ISn~SEKS3q6K$FPBWR9VN@-RYV+o~i6Jsp}bSsZpE_Fe2
z+@f=VGbbz=3fMhqdG`Z^r!4bi&^&E9N+FsvmO7fy#96*d0ohs0g6>d>xBTXybBqa=
zL9^i0IZM_$=p<Se^atX+<;^1ClPviZ;k{s~NC4uZrM5j>yJUI10%ggTrAGiru_W(6
zF4gimeF|{dQcvOaE0(K2qAqEcQu=N%-O?-yoL4P(LvatTS&C_|>$=6SJ;h&cSR#Uf
z$gqr}@Oq}Dl9p9BEt|)qWo}snnrdcQx(tQzw&l$ksAOAaEP^n{vgjyO?pO}VP?m3T
z^@63lmJi8jgnO0+BK$3|%*jPrp=I56n7?nSoC)Cri$v>+B8&U?^o8R?i)9gj#g?%&
zZ78ucT?d~YS@uy(=&@xQeXjY$a*IxemRi~k0<g@In~Jh>OS?R9S6KG<M_Hxi0-bz%
zYMHVfDpi)5r-7@sjGYRyXO`Dj;cty4ioSk)Zn+f>K&?eYBREubmi4r<uD5jf1TPva
zbH4}83kySM0$y6QCxL%usosaO*B0p$@NX<#egxZF%MUaTy|b7o82jE5LOcB*EFSb&
zf3&!+1@4oj_8}Z~vhK1W=WHD}6nA8kb=E4dY_`ra!K`D8)t8Q9xLChSg59mwHY!-!
zW@V`su2#(xaBsH;(uq1ZYXt4{?66*@4G(v#C#||YtkYLQ)6+V!0Csm;lQ%%c%lhaQ
z5^rm-WRUq-kJ32eYaO#5D!Z&66o~M%w)cb3-(h`R1n%9|;qfrP$9jNzwg77rTJHv0
z`_ZOikX1u7&S0z99hUZ5{aS)_pY_&Om<X{xuS0IXReK8X1J<^*ehak@iU8oC_2;)x
zIb^M-mnzKqYXg$Q){3sM5N=)a5h@W@$CFSv6=}UggKCtuf!4%FthSNJMO#nPht)@|
zuCzNAW4%snvDSe3035RprS<)BYcD$gc*6P*eP?sh+AIpfQ`X%rpn2MQbptAT#>&<~
zCC<vvfiS@uGYiQ%Yg>xPCtAOC<f8Drbr41OldLTzBp0mNbk{Cg2ht4vlJ$35pC?-<
zHG>x^)`0Jjq*`rucyZa9L|>;~v0kS@QJQsa4shvK-!gcA)jFvqa@VXkozODZt$)z)
zdBdvu5xETO+3&%UY30s3pnB8#o+AIZtiS&b-?FR$Yf*UH+OHbi+16Ss%;#8x{zTaw
zYXhxfbFE+91TN3I>k-)UtxM_C;=9(+008b;htfK%z?!oiWrfyDiE!<{b*3*YJg_pY
zfGe`jr;ptpT6fQ(_pjJGfIf{Vv7Vd<yN|4&2|zry7KI~uVh!AYCM~tzrWtaXbuX<Z
z%dJ=G#Bqg{U4mStHJw(IPp#n;x~sB|<B(Kae~bm-nbng%Ag{4@p#7oe*0uHUqSjho
z20)!v(S+W=dTU!+95z@JZ-MlM^%Qj<FRks{p%$;Kg|t3+ZEf2d&b+a9ONYU?*2VNC
z={xK8ESPw2ooWX62kVvlVEJgR^@YkO>-Z>?IoZ~%LYcGe6|G=4+3KIc{AOFa8M!UC
zty+{hTx=6)g0a<he+m%WY(0`-$<=l?8|Js$?$KFcH(UO3IK0Ca*anHa?ffhNJ#23&
z!0c(eMC+lQwgw8ndf9%s3vO@Qi#I6qu}z?vo3Aa7)}*^^S81U3vw1y)(BD>5gWPV1
z?VBzzvB%c=Yv2QHNoQdq*tUExYO&YW+lbsg+b?wNEW|eHDIDEzTS0H?0b3qL5<+b=
z=$OSpTWk7m;E-)S?S6*Yc6LT`*!J-NSi)_k3g9AaN1gCIM%voaiXh6iL<9H{o8xXS
zOhns;aA>`wHq{?UVr)HWe>m0_n+cj@wiZUv9Jh6$@6Arw?oc;-(zf0k{+_a(aY1t0
z_7{Ekb;h<X7w|aS3>7S$wJlzavUuB6n!6;}zM-Y~Ioq$ahm&Z_-3gWRwlfaewn?%L
zW01XIoALoV7j3U;;(E!}Vgf8B+nPkfixgY4zX43ORb2wxW!njgi(j!7^@rUw+u>s<
zOSd(6B6rocZ#h)1*{l?#ziyjH2X1cI<cA^5uzkM|9%kAMTR?r&<~5zxf46L^ui!<N
zZ8QB%joUUE?OSHsG%aBw#}+|5hIeceGJwdnB~b5`XZz>_m3-T=b1-<<wvoP2yl3NS
z0aajYG6yCKZC+^r+_$|y3itzC(@>Z%vT^jC#6#QtXYi@mcC3QFfh)0fr{j>1Y;9wK
zcx>~hZtIDy)eTrGwH^K$Ntx~Ybd;6b;=Y543R@cuOjO#IJ_GKlZTJz8R@tsz1g_e)
zt}84(v#kk3S&hx%jNEfuLJ8WU)^>^BpE}#zui$UJ?R!k@9jXS~^!I4)7q(w$1N|jB
zHkf#2yH0<-=e3QW2D@);Q-=ca)@JMp6Yp$39DMp{JNOfFpKK4QD|NExG=~XiyM{hu
z*krFC4i7imm($vRi~W`YWiIwk6fN6o|49kXZT7p%AauCe9kk7~-R}7t5N`H8SD~}R
zUS11>?)K$H;P$Y8utLSt{xe0UcG^R}f(bACsd-TGwr~0YUijEQ3_yK-?eR1t*=1j{
z2RT1`7*@C{f4iAJS=nvhOdBP8>;q}u8en&!4@m+Y_Fr0{+Clbg>SlxO(L6}^+JC0g
zZ2Rn^n!s*|eP<z5_uKPF0(ihak`}?C_Ig@%AG9y>howXImdlWY+2^%~%3=F_`tw5J
zb`vczBkW#u)GX5eBmJ?HDEmZuI*-_!QLhzkcX%sNc+@_Y)><+4{RoMvV(m@>d^%>I
zMh9w-+b^#I@Ps{|maix6zi&o6owB#;2`^6Di|CZb8T&x$gyQV$e?mpi+K;RSS-jo)
z9`FP^Hw?LR_TGDtB-+0pgXFyZM>>m_WKVF=QsRPr9mNbU+RrDz{3W}ZmTbxP?wN2g
z#a>EFkW{+|O}j7K57F`GEB4;UU_Q;hfHuj}?M|J+a@F4R4$NP(pK||yIJ)k*EUPbW
z!z?W=&EnmA@0FRU{j{tsH8rzs)25o*H1%Z)D992}lp!D>OArA85d;(&%HDg*QbA;c
z{Jy8Z&ga~F&i9;qd7t~-d(OEJXe_d+Z-J#^8=JELyJh1*<GpRe4hBkzO;id*N^PRu
zDLYVR^UG7{EVl`n!hBWOJV}AMN}JO@GkX-)R&Pi&*i4lGy3ywSFbFo;7`MV+tIZ41
zu+U~RM+yhqZEXHUUx!UBg}FLy)-^+~%ch%RX5BVl)53Jerqdk?JvPtK8?x8ty~kj#
z&*q&baQ!yn-@wlSn}lD%-L+Xmb$$12)>+Nazi*S%4D3Oh!jB;{WV3_rXFjl*{sy4K
zHa}DR;-L-aDkf&crip$Qqc%Qt^<&H?a}k^ww^?-q-cQ)nwSY|8L@h$!l+7+WEl=Al
z^#+--`N|CjAKA$0>ld>&uhTo&ma%FNtxtB0t&}{qXNcy(3kOE>QrLB5<W51+iE)aK
zT1Oav7Gh}54E_nY=EAW4fIe5oHYy1?%J`e=V~;T|(f-ek;YIl~cg8_EEFEX8r&=cu
z#u!xwcryC`0P$k1p}K5uhVNO*kNPm4coJwQ7}->f;>&3L7@QwtWF27q8Gm*I^d#e1
z7SK*HqW8nK0EVUwpr;wnd;q&=807~b63943$Dts`&O~4bGXg2WAHp~?2JS4QeHZ#d
z87qH-`7lOc8!Ut~3N3U;<s2hA5TFr^|Go(q$#|j|Xi<!nv?85n1nmKdX2ejnUJN5^
z7bIgDE#Cn<j&bQtka)&XDvP?nXxj$w6BtsuK$6I?{}PQC8NZHWev=qmsE+CqBkdUG
zFqsk71k4nMH)Y?gsSI@$IxjOmxdk?j@t_5r=?oUt;AJrWy^F>xj4gX%H<NKb6`)rc
zTc}tti!nrn2|0{?OsMBFA`0Mk9)tTnM6NT|6+q+$W7lywlh62@QrtHg4SI+aFrKDJ
zWg+8AJ|v5*jJ_jqv6%5!JLd8h!<n*=w;A?L&?sRHErr9SjO!F<Dq~!w<YzhK%_7*X
zVC;Sdq>`bfr?-kR>Ie_387rJ2Qo{(&0(LD!N%dQGjA!V`U(XP<K%s&0(^2@_$Y`OA
za}&dQfOad*42BsnEsUVc5N&0+CjhODvFc-tzMT<4Ij0VW3zfumG9qa2-o=<V3$B|n
zc?l-&Fb-`3>0v}s<y0@jy&P`$F_u%#wV%=62{OR=_(hPrj32Wga*y%46S(_~9adVA
z1{tqi0U2UUehf<w7`q<AnPEl?y&)emqQ>Fj2*ZwQEJqpgSJ5}dkQc)IIOA<npJ2Gk
zVQ`YMC<u~Mj7kAUIL-Kk3cP0+8_nPzF;W)7;4DM`9vW?#AJKu@j+yfp)u-DtfBp{B
z?ZAACPSlP}XWElGF`L(d9ATd7hlVqAN)7Wa%)oBA@5)?E2kN8DyiKrsjQK_yMBJDK
zlzMV!swqBvoLN%}Fc0P{^j7d>zW6E}^<rLF0nVFQ`~^gOm|q>lcbMm%V0KfPkuNin
zQgnXIM;Vv|e`X`aR!%aV=>&g@nN6>e0OpO?pm>@Y{1dn{%*uB`0-67#Lw68!s}xfb
z%xpOgE`;es?}4*S0mXU3nd>Rda*la`w(t?mO(EbSnP2<T{~?HC8Yrr9p1F?+-=dk*
zddS2uOENH~Smu)d>id{a(&jFnxzQaSUSPiQFGLcUZuD7_MCL}y-d|)EkfTY=a!RvY
zVk#-akj!-J1WF2X$4)e+GJll8nafPO29PwSn9?lPbmo$3pk*-s*a4U;%mj)*W-`Z@
zK=CS*|29Y#Gf@N&vzaqBn38MEw=*!%9OeK`VlK0avJiR9&s{L4>&yrjNZw$cr3gSi
zvws6j++<2~z!flS=?z)PG*Mwt5i^}utzs+l06mqrm=gsU;cezG5zr`MZl*wKDf1$I
z`>Krj_YnHZnSPYHs$j;y2ose|K81p-n5*eAtY#|9pjX4pp?6{}a|dOv>X?rxlv~d{
zy9}g(=|ZQ3M&|Y!kS6A4+LAUit&x<vYGFoDU12M85oICTm_N{+t9GW-Fzj|P^ZP+M
znKOQ{)Wz)k0Cu~XLG2)Sn3<Fl>|th6ZoHSdnrf{2n88%6+t2hr2@?a%ZrYsPWv0@h
z`5rTz3V`o3M-AWxnJcW65*cEiJOHO2Fh}VyIL!2*JDLxf4)l{BVWuvC-BIR~RF62u
zTwe)=aVBd6xC!REqkx%Yo<0h<r<ltrsxZy`)d3<i%;oQ55RaIv?O=YExz7Q_meoP?
zYsXrd348XeqD%Dtb71*?0;i6!#wk+i%=(EAS1znF4`{fuys7r#D69H+pdDkaq}YlZ
z>-y`^b7##vgTCXeXGWpm!D7A&5l`0I`S90^C2mHaH>-_~&_1jSbgVzY;`qaDUzUo}
z9eym$LfW7Evrf}*_9Tl<XPr~5b#&<|fHjAL?5A1m_hIl1tAK)5fvmnXkRVpXS(pfB
zl~Jrcgr!^wg|n<BlTZj{1#O2y7%Q|BTsSL`N=44Gx@irIU>%~>Ba-Eo356)uyVz!1
z=bmRpor5>gtU@}t#jw0~g2b|Xcf#*DRw|wA<5~KDp?HC{kt$>oSWZ_lm_$}M?MW}P
zmeGMaiB)zU&Rk+~yC9j&+Die;6xMhS6jE7lQZ(^0>y{ZJX{>1ak*2fM9gwtUu)Y|E
zr7JA`1GHwc#wjFpm1U)MJ&W}??Mbs)2PVK>V+C)5-5i#jmb+Zmlap{ekM%qqsIRl0
zd<5(ptmkK7DWA3Td!XE81yPAu0jq8$L<(7FUxI}q)=7H8i&<{J0p*sJ#h_Az+pKg-
ziIlLOafQKB))#a@En|I0rC#MMJIV`HunMW{yOQ<wG`K1j=VQQBv-Tf=NDb@X*U(qX
zilb~m9gC~Q=<8V{bbx7KJtGF!$a<S1Sxqcw1%}(qN~b%pEiCI2ItjG0YKp<Ov2qE!
zoh7G-q=WSqUGVE<ISc`&i<OfH#U9po+tAp{64-(CvHrY|#(vf++BFQY7<7WT%L=D^
zqxV>^Q>oT{)|R;t8DuTmis>F=eegB72dw+?P#9)4Sj!>vko5uuCq`HiJ#cZ9l}LB-
z##rCbk8PY4;|uc>tmUiFH_5t95t=Dh$a;uOvtqG@nmfbV=MRxbtT!oWHOrc`2beAU
zv2GAM_JS(-WY0e7h#@(!|M(wVb7bc}1!yOB`wZ2`9$^Pi;g~bK?_<cgu)nwt;>y1M
zCJY{BFQu2vG4@^u`0d7CwgzbK>?g{haGd=j9jHCnHEf7@vg0U+;>F(41lPRTepGqr
z!+y2|U?<owGvSOcyUYiDe(cXE$nDSWt)=@}C)x98**e8$Qo=8QJ>U)BPP6}ThHGco
z7q-G~AUpaCU<a{fi5Pt_dl8-cLfCkX;lX3K&Y&-pokQWvFm~ZNkZ`s^3cYjeEnC1v
zu*(+!I+AVhfcYqP_m|K+&z^$=wRLVZdtDLC$FQC0H5$uqu?2P<`y!oz<JqYt;4ZMU
zUx7~vY#xOQ6WJGOO}WTUcpP?<*b!qOm)MOIOi5-J_`y;Nd&Bdvl**1Mgydzm=LYDd
zvA322C7oSK`_>G0AcbA5SJ)iN#$~csQbP7Bd(MZ@$YOuL8lBnfFKC^+#!jQUl^nK^
z3Z`?}@t>hFkKM<HYuDNL=|ag3HkTf*e6~j;8VlL1Ml=?&ukHh8G5b>wG~QzW&V~8g
z?0t4nFJTWCf-AMMM}ETS%h(5KgHq1^<OCEe*zaD2MkRYyC%mX)KfMYbR<k=iVWNip
z5<S$lZ1*ONsgAvjc9r$)v~=_}uy+SRp^+`1Gi(!k5j_>nY{6DoXklNW$ayP!FCA>#
z*eNUwshw@TJ_WQ6cJ5|qbh0<o=D&;WzZRX{Z2m8B<_`OD8g>u+#x0=rvU~HP(8s=T
z4VL=ZQ466kz#du(fA6wOD6)EweRT!;?z30Z`Z&mb`5I7$*wb@B9<aBB0A-lHpZ16k
z*`HZo0NMy!{|iivvf~#(V~qXMN01q3Z<r6X3HH4<h)lAZXoo$;?wSP5G<z$R^31T8
zuZG=6?7z!FX4&5u(P+y_cZ7l+CoU8U_MF4x@X&#iMp-dO&PVRB>%^Hy363M2b|0z_
za^|ooXXV1tc)+eJ=k_L$qnxZuXgtQTp9^d^&U;pH?wq;wYCq1IzYvWcoJhLS=*h{U
z+?p3hZVymzj^AMrA5J61(NA!eNHF=noZd4q@5iahgt|Xxwiet;&ZADcA99M5--G!I
z;H;!w%W2LXSD>BY{5=IOkP}N~LP4B|d4LJ##B2r$;oPM%p|hOd9)qP&j`}<X5ytr_
z9v+5sY@fyio#V{XE&T|N4IL&UIbU-@qBx6bXMLXYh&Gk6oV6kJ1?D);XOw!1=QL4h
z<^tzUilQcP>L0^IC32DrA$pNx^Ew8a#OdjW{v{4l#dy>>6SVnA;h0)6m{iV(^og^}
z9H%;PX&hZGoJr>_{uUw`oXY|X=?dr0ufWXY_$&p=RZc7IR;*c^KfZ=yHm8I3FxNPa
zEx^v<d`gu$xtxUK;PN=X)u8V>=gZH*-Qc`SRR{T;bMxWoO->qJxhdf6z5`2zoZ1dZ
z7IF6NhlyfN;6*6h;vCO}rQ4jgo4_pL415c{QqB{!YL!_zzib38=Nzd*YXv7~9-OJ<
zG%f<E;yjxJ#cEDIeHx{P^UhDOTgz#r16&<vH@)cVIWJJ?pn=o>8n{MIx)FU%oW*ZL
zvYGP@T}y7^_-zGg<y1Tgur^K~Wx?AyZqLHQ4vv-iCp0=aai7Cr7iZoEINZ%S8G%vU
z;e1I4gC0%^?Lm4u2Pw4L$7xN1rG8FUBP0hnh4ih;yBv>cczBQVl?L2>P7USl205Vy
za6_EOV=(Lo9QM0V80LIMv6+XQ&7VSKgtOR6YtkrZA?^IeI15T3GtN=cg}({TD!Pa^
z$<a_|WQtQxA<k*eD^wpl!)eaKC?0VR(`RjFISG`#u;ogsLF~9Cv|+X9rqi8$2X3D)
zL>#$0=$P%qUChR?k8m}#<U4cy->37R3%9lbXs%p;iu@hrPKQDN7&nt%1jo4>+c63c
zZUEiD_T;`y6{cR?R0Z_Bxmwyf`EWxhJa&RR>i`8`?iAfL@Z;Kj3lx9uw{+w>$^CW*
z26&1aA;nk%xF>?qcbfa&PTGH-;f7OEJ&?P495O-NofP*B=5~j}rx0!e1vSrd-RUSE
z%3ZSwTo`v(D!d5icF|G%99Kbc=?E^q(Thiod!iG4QCxOB6wY(ktp`{%_eVO4$8fiP
z54U5vpSlAjjyr;!IKGj^l`n?F7r2aMXe4k$=ypsZcP1U67r9RK7$$KqghT%l_XvHy
zE16s1gT555*ZVM^%6&`^(97JD^$<zpCQwCeI@e6kK?Zj@HD2L5o`8i+?gV8ou5!=6
z3qx7l^?gvcW^)tYN9#52_Y0wz!~L!WB$vC7f+Ts|Oc5+y=k`;%+zsxnRLpZeH-M^k
zZgRb8K`!9>*uld>Zuk)>6mbLgf-B}`P@MJ_cjHTFyv_Beq*@7gMIH1?x%27uTgLs>
zAL`{+uG|5hR&aR~s;T7OeHt=V+(IYFRCD_{Fki#Hyagh)Ts{T3>bR^<jJKY9g6`cm
zaG$4yY$I1n_x_r=wLuVR=CVEm*TQXo3&U>ZvPPiZ#yup5Ywg^B=?vY$6*fb?lWRS?
z8Ya59O)-$^=I%8C`wsUfCrnKb*Om<Sauc3{NFVo{5F-6t>nCU&;I`QU<}P=n4sH)}
zN21X<#QpR!a1Xdjn%QCQ`Eh_f<UURX4I^A}2-HWp@(<we7&nnh%f`78R*INTa1YZS
zbCP?2_O?^p+D$Mx&3&#5WQJR?7od;08?oxno#n2710uG(Z4~;m<2_3sNV4bkg@8El
zekcWsBkx=y^qhE~()Q>GZ!eYWIP=2y!>$W&n9?k+ywGO!9p!D3((`wWca?%9ZoDE&
z<+$@cq8-g~-aQJkd+-+0Z_bmqk3w)>JR@y9y?MXA2unV^Z7YFxg7?{BDERVNw9xqR
z{3>9{pJ$<D?MdEIE&5LJG^a4$0N&w2=$+>6qeuG;PyI9HM+13(vLO@1Q`4S0n750T
z;1J%#3UFt61#hA+l(&<{6vq3FPW0hC6;(o<<DH}zeFV>sc7BmO3FY#mcp8dUpXaqu
zMM5-hl8W|Xcx&m*6U(cn3|}0tkwUZayjSsqu+F`}Gf^5Lfj4>>8i~A<RLgUbw}r}P
zl6c=!67mx7_;c_gnfK@Ou$#h*34neo?|L*WUFN;I0bZo>2DI=ZooAvrd<IXrAC|80
zMk#ZZ$va8~_*Z$0R-iA7cY=<z**v!r^jWX*O1^-l9Nyn~(9h+4{0#=0$NTgQu&?uC
zPeSGf??tL}&F9&E1agyi=R-6W@Mh`MUC1k42kau=6Lsh-=JnF84gBB1-7s;RSE>O@
z3D535kaFG^f5Pnwp6guLtK@mOVMtY0o^v=9t9c*OnYM-(N45I3JT--z>v+`+kb2&B
zI;%DCa;bo-k(Ye~cAIzydSI!US3z;t7T#NXAkxZPwhG?2@i;1AxAQ_3Q19R!ehqz{
zyjfZrx_Hli0g-N=a|-nC@T|6!M(^RdECqHiFNU^BeLR&P=DD92b_jg~ygjtjz02F!
z1hjj+W2b?ApXYQ43WGd8eQRNew>t|W4|rETLEkX%xyOO>kY}W~*$7Wb-jDL0p@YmA
zul_4QkMl%Sh&#daxBi9kPV$~w2ka?cEQL|0c|XdaF~eI($)ZQR;R%pgp6{<fv*n+s
zAeJ5fu?ryf{Hzaw=D=T1=~+j9K3z+5;<tPSFOKjnFF?VWpC?713*UV|JapyPo(I@b
zeh3wz9pihaQ_#+hA94k(JAYOHjpKYV<=8y<uTm+kC;zq+h!;P0C;Ghk2X8>ZhyQFg
zxD))je_#@P`2sVX@#B{^fcWzV>DfNX|K~OIo#JP?Ks|uJY60|4^Cvf>?+m|>qDO)J
zAMGjr8N`3=Q-}uh*>qkG;a_P5cb1<V542GJE(%45@xM31U^u_49wO)X&EI1%5&UY}
znMd-&{|l$^Kc}baJb&mhkZArt;TS{=zq}ciV)=DaD8%ufqp`&Eqp0fp0zV%iaO>Oz
zK7&rGiTo-GJ6+-*Ooe_j|0BA+n8N4LUH(+Q&pn7-=KuaR`qKED>4{6{ODF`F!5{Vj
z_7(oyuYhFof9e6b%3neSAX)r-i7=ndccIPjHGVz?cysuXlv~T?zeWjFYaV}sLIBtK
zzbt@>8~j!}Y3B2tD2{TIzj6sk0l)1q`U?4(lv*j`zw#Hbi}`W2;BN6JC=PO)zx)rl
zR>J=u4_qmK-V1Q8jPF86({g^@C{QZ+|4<QjCBJh5q>6uY8O&E(`JV?uqlO>32cxg$
zdp7{Ij=z##j`jRg6q{+_&!xwyk-sk<q=`SDHq*`gg=;X-7XE9#Kx^d>Z3WlHAEB^*
zJAeBTV0Q3hUV=}Z{K4xWU3}>p=ymgdp>yXQzW**j_wcO+OxW$^KX)H8eSAKJo%;F1
zPoi^x{~g7R?(&sy0PP+>V;tl@e-k~8gZz6dL5BG12LOG*uc1iIF#ityoFDQ%<<J}9
z?;?d!{%AD%#`v2eVQ8G6d<oDK{2zV*ndDDePk~PH^C&<z&99_8Ni%#e3Z6aU^Oj@0
zv;2%gz}N~>>6WIQ;6Mq`>;-<b33m|ux)^$nf;|*PbrJ+6fgBM8K8LY53u5y?Tm&bn
z7Qj^yH3H0|g24Y?c!D4;^xOo6Pg4BTU6Az_(2fgg=p^DHNT9rjr{H7&WV{4(=xFLK
z=q>^A5iHsXpZo-7J8=GjURrxk3X}n8JS7+{fr$V_`~h}a&=CXmGlJ!`Hw_e2P<d{U
zV4WC)2p0IefrJRY?4$V0S%GdY&_V?+RFM}Z_?A|faKT<Wik}laM(L9XK@RQpA_WEt
z+C>Q_4+8tVAd?P^(Smz-;C76l{3DQ9!G&+(Oq^iiOQ6IHeh9}TTo7>SY?mN#ehVmx
zf-qV;FA8!{-)fzkBzX57C|(laV>o#51j`)(nj-Mu4vkd7k5Op6EXbM*E=^D%0(QE<
zc@!`ig3o54cSR6M;mAzEZxr0TD%d>@k|nU;1-)#6q#t0{1j`<R<Op;oIFl<dFM?}%
zf*uOpS+5Ir-2wIu0h`hZ`GQY>hRjXDx(l#WAoz{KKZOF{&tb4g@E3)`iUpgfPW6`H
zJ6ig03yR&)S0Y$M>4Z{&iFRjYf(lv@%LP~WK%_!&m@aQr3U>R$rz*jR&!Deb&`Ocv
z8mr(Gz4mJb;j~ex6D+#~yY+&%7r{h>pxGAKje=OZ2i_!DO{bJ*fg1%UTLjq@L2MNq
zbb{SBLFn%w?E(g+RyqW7G4whGgY@`!3G@mW>=wMyioQDn9%U1H1n*FNdauA*$pK8C
z!1G`D)-U+{BVZ2*c7FwD?h2-I(05Oe@)q>(3uY-)GAL+Ffyj_x<<Dq*Ao$!KFvEhc
zhhhGqAbcmrG9rklt;o2*Nc)TlK~n|Dq`-@d#wmd*0<KL9wz`AN2sT*l;M60*Q<M*%
z6$q<AY=s+YVAoFgRxlLpg~pRG;UHW=tF5E3JsF&nuqPBEM}$we;_u@u+&2WDT!ab#
zJ!-;Jv~N8seB(_t9utP~f#N3YM9O`xyYR$mC>$52(I&t{7=DT3FP=hWJG}4`e&GrC
zy@l;mK;k0|wxI8XaE#ujzQVMZ!TAXvUW16gus;o;Cxx1P^qmrZM>~T6;cpZkKP~)o
z9|mzom`t^bfx?|XfdmP^r}~~?;fvWo2@xKpuLGSGMi<lltWaUj6JW!Hd<#Isg;~eI
zofC%AvK1lRL9v5KVb3P$M+w{Mb7$v;=c@o3Eo{CCE=D+y)~Q%wM<(>*ge-c)#|wY|
z0G2KY-=lp(f^a@9p@~BMLd@Dl;f^R^CJ7gyIKw*kl2FzLhm(bFH_@6RO#2IiNfqu`
z4E@VOUpkJZ3I9|9J6+iHEBZ2ol^bFAitvR|^koXW3?Ns9qG2dx37h1Yyli3pyWp+~
zMehMRM;KNLpK^r@XJI~1=(8SUxi0*d%7m;pguhboD_<CN1)w*DA#`Rc5Q_c)DHQIA
z1x%4}&tWJQ3rlF5a!dFkB}i`zKczoYiEtMsI!lGcsX!|eZvFyb<-$YsDUAwYAw`WV
zg<sP~tV;ND9Ym^y-gHr-M!4i3_*8EdHqq<5LAc@%h&BpWW`JuFdi9{QS$OGVkQQM@
zJxHr?3k{}CII#@|+l5<cx$6*4M8b<sVd`@b=@Rax#jjgfPY>Q5;cc4H9^tKcVD<{V
zzei)A@X#43^a};an9%{Db?1wKxhpJx55C<KI?#Rl`@%1GVx9+u0|y{8B=mkB`VWNH
z=zK9Oe391Bhr(4p=o=A!HjBPd;oEKSX-xPm9qh-2@4k!anh=^_1LmaA;U8d52~#OH
zIxUQkgS{Ey#&vM!k+8~2ufthk2VJGK6=`~5*G^=bi%xsdnK+<1h~`k?vZH9505DFX
zB6^J;5&d=##97os!7mrl(rhTWind&U$Wc)S1)7eD7|+5{H<90a;M_%D(yDb_l*@#O
zhbU(b?0Jeh$0+~cC0a<^9B&chJVxOos-g?RCqz$w25eu^<Nu(~PZYBR8vdfqxKlCr
zr0CsBpq&z(r&|F5A|Hx>o)&HO1$RbNGYc+Ilt}kGf<*J)g27->Ljf8?M7JNJ@vJC*
z5L~F}#bLT15+)j_L}|Ea(K*;XCmL9b!9<8eUXY0t?WIzgC{e(-P&_YMpg~`>NJxuj
zjL3tcR<R-*TCC$l&(Ll(UNpZ6<bue%5+VsA`-2#LqDXIxab6U$=YUHR>60;*OCtV3
z%Ks&c(gbKt5&iKVyhs(@q#E|iqBoYoQkv*(Dy6t0y7Mh8Wr~6+o^e&=vH?D2i54V5
zFI&W{fWd2`ze_-JL^?{f=Zb0$!{0p7dU}0c7k&E=z;1}n({C<c^sEr%rbw_2#9APV
zq**T%9T7smNYqvY&|=Y3OQCp6G@pVaw?+OG9V`)Tz6~!*MIZk62@jF!Jp3&eB{85^
zA;MM-kD4f93<_1ElT9#KEqa62)f$n09rS8N7wzF%ohX?yoAsi(v~O*&itO#t*(i!^
z0ZfyqF$$f{qFxU4TSO5akZBcl($29>bdeJG?IO!2IMX5eV-%!QbngL7bcv=Z7~3sk
z(joSa=rWa)^oTamMygj7NUK(#=q!DOrC+p|>JSG+Yg1w2uE_e^Zved~`X&^1?~5F7
zVc3JB13RHOBx<jRi3g$~cVG{To}i`Wq39!uCyt2N6pI=aeLMk}G11TTk{A~yJdeH!
zQLZ1jNl|hlFsDQkDwdxXMLY(u8PSy)KtB>aqS)xHDBU`W5!#A3P;k^v98Gtc?8Qh@
z<G~Zpdk37O*l7VgbP|6Y0dhqA{ePQFv5bOdF5=SzXml0Nrx*26@fS2D$He=;gPxmM
z^$AS4i$i)rj*Exst>hu*(08Ui#n)&J^b*_bru$jmVpauMAMwXa0dqpk`35k);uXG_
zHb3z{Pr-!0_!o*ZpA^4vAO4;a*Iz<ofVlcs=$#f9(JhrA@w`~fda!tL2=qe4i#g~!
zEB@?x7z`ErkD)J2tYtwjT>SMXn1plUcji(3S%i4j4>FPByJ;{HCHB~i&hz5E2Vp5%
z+;;<9jQH>(I2tRqnE{CtucU2Vy!d%4&%GdS?!uoUL41SGe~IFiYk+c5oJR4NB=IX0
zh`1zn3j;|O$J9b0Mf@?H)>Fl$rS$w=7JFpFw=}Vp0gZIAK?Lj!@%?^Sx*|@e15KuQ
zsu6x)74ztxMwU2=g6-Mj-tB<7CSFFT?i}$kN7&63>!+cfCq5brz3bwYCn0h}eELg(
z<%^^Lg2+v=%{KHEh`*)Zv9(Y<{}o^tiLX%3tXM3`g~l!MqpKjd#bO~8OT_$gfR>6!
zDJxed_P2)@<>FN(=&KOB*u$Ah@%m7Vuu7aw8KG)%)gxG{5nt(nNUeC9z6n|<-v1ad
z>%|Ea25k`UF9z3W75~J9Xp?vjZ9|*IuYV2f7O{p--L2w{^iFOQr;x+#Vm6(+JH!bT
zi|Q1A{vqskiIb?Nr(66bty*`)20G~Wi1~Et?iC-TJZYbJ?|V?_7tbq0-+=fZs%^e2
zjw^u3J+bxk%^2E!@e7n+8WbPeh1MbQia$Ueh~;yjF)VgXf%^}|TQo2+BAzD(85J+3
zI^r?$%|Ymmi}mzln-JgZMdPISjcxF0N*wkAP^QJf6(BQW1*Il!CBIO}!cOwhJ8;cj
zvcc*J^A3{3wIGg?^Mep|lH9)s(Ib+zRC@0$scC_Ri-bkz5?4tn#e|MZer<vm$0W_S
zVBSr#jn1_05`U@{J}#;F1nM4=P;9T}dP=_g1bSYQ>HtW3OGaod@{z<-#PNhgkxutR
zd?iUKK=YG)@D^bFB?t6SJSka6ak5hqpC2)_0Lk%H&^RsW{{+sQk-QQMm_W%Px}g*#
zai*kTu;f0~K!ixXqf_@;$tNE`GE@?sj=nHSBTaX>WSmN5&PjfJ1CkMvN^gpPMoK2u
zfQ^zIih{xOl3kZD!f1)}Pw**5l9!IYSV=)6EX7IkXxWOF#ECJO3zFM`u#_N~*$llz
z$;V~Dz9@N(K82km;hX@uB-#2hyhxUe(<whivNRNusghIl7QHNaY7;$wX%gW-fJv8}
zJPC~qiHyQsS0n-7!F;A9UyH`8l6QW>BxXsTN&rl@BrO(w*CcZm0y{^tr3wnUlE)*!
z<w<Vk0_?iP;W+eeNR;WYlrK3%r|z2)k6S<~kVJ=qE0heq2{3DsWHo&>vRJ}rV}!RP
znV+New&b0wP%M%Bt%gRagckx6Ws)bWAW|-QT?UZ~$y&<nR7%dg1hgs%pZ0Op5*ht~
zYb59BKQq)yZc$-von#5><LA~(s&4?SL2^ri#zx6^^cHTiO5VE*hnppDUPfn&#N#gP
zwoAO|Oxq!er(H{@Bx?}*UGNZpif)OG7bNdU+$m$;BROn^La(HkN*DViLHY2aUlMU0
z3Imd1+BV;n?5srJJ;@0DMea*JHbP`j@;x8WLlUd`eTY7gJWZv`!;(Zg8b6f$r2-j|
z{2l>=qZ0QRkTHoDot4HVZ%|}wLgGcI$w|rH8o*3R+|EH{TJq@}n3$0~wE`YKl6*?{
zW@jbikHFbVrI(;!Cv|lMw7s;3s!|-J-quxM9i<jFWSpdtI%ph`er*F#XX*D0a4yn$
zbUbmDenHFDQE9{DaQ~Qe1D(3vq^(T!xl8S6*Ku4rS_Tmhsn`tSDa9>VJa|$eg}c0^
zqh6Q<AF06+m?xw^rGxlNqlGjkKWX9L0QHx)ltJU9^b&2MPD#`0H5wrOlhO&NrCD?~
zJR=RFuTTU^*WQA`An6=BUj$1R`=BvIDigt{vr-4D<q4JEq`g3x)So6cT)Na9lINsD
zZ=x|mY6*r<k<#O5>HBa|(*1OFIxn4*2NTiK%T$OJBVF=1W++zr1zu8f<D^c<&=)UV
zV+;KY(m53FN{~)c5p1H=hT`fMrOUQpOi5BN%1~aCF8dkIBukgj{ys&zE*hAr(i%Dn
zT$YL{+Lb098>0L}y7ce+U^ApHufoME((P^FGNu2E1=>~VlN9I5l6q5mD_iO|154MW
z=UxX)p0xZVhJ9VScQ;JjkRHnh$(K$9Vk|eMODI88Agw6^W}&oU4N!`tiwn?KEX`%Y
zwOi75s=>A1mVQCy10~WB5%f!?$LcXPWzu&VV4_@FLcgmDX%a<`E2Ym;tiDS6!W6Kp
zr47G>)JQje2$5RpJChKplji0DtX`Vi2e1a|Jc^1mO4TpG?I!8VeDpO-f1zw%i?rh~
z`dY2ha{2|gN%u4WyIne7ih*`W1$4aWl*Vra>5{rFg?_ix{3FO6=^olu_DGMHgY-%-
z)q?a%V`=T|mxj~!Xh1qZZ_&HbfUV%}Nh|em?Y=bgJirE}S7@g?B-PTZ`GM5xTnf-(
z=_tKoA4<>p!o?A(rU+=GQukzxVoZ94Hbmo6n^uqsY1Q9Qn8dFHWJ>CB1PasAwOUx3
zk-D!2=p$(c-4~pdE;K^KR%TKI+D_J62hLtrM$eyv?EE&2(^00kQs~`D#-daA5t(Wc
zh_kHxPyE$fWM9+$30K+b_hI*_?8s?I9+M4F<%*k3O8IDaS=$<*9hY@{jy?}rPbSQJ
z$_^HT^OF5V5d?2p9>valWUqAq^Mp)9l`_7vtMoSXlX(=;!t5`*<pxV9Wx9I&NlwWU
zG5{JN`;0DQoR$^S=KqZB>0yWj$`F*qgC`qv1qqftplcr?vft?YM`vaKUWWNlnIEOh
z!el?XqAx-w`yD8eGNS<MQ8Ftf70$~P6)+nun`BY^B}OK+gG{VUL|d6S*<E_?#><|i
z@aqMcW*0OPWUtXNKT)=i&hQsygP9mwlFYvd<dSSJZE=%j_VlVtk-0hpB~?~Uk&DZ+
z@_*2mCi|8GdFistd(f95dzBWyE3y)#r>t``WsdYFxGMXT_Ig>e^%Nw@mc9Kr$TeB&
zFCaOx*N32(D>DWFEl(Dh2QRM6_EW+44cV`BSteih0~JT#lr3?9r2^Tze1H|oRvv<0
zkt~FEV8yc38&J3<o45(?w(Kj~O<GH283&+IDihQIrc7o>fAn%$8EI6=mIZ^W#ONVf
zC6o8T(P~)@g$HV6$`p*ER`#+F23jYJUIa_^GUguiHOSuTheD%l9z7~evXwlbG|LQB
za?&CT?8A(<$_o0S&}NnWNR?ylvcx*TbjZBDAk!&}-vj+F+52={=$5@ipPjiQySf;T
z_Q;m*z(9LtcPYovC)?f!6aBLOXMi>!6VhjA?#jNVxBop^_lI!izAWY{`UYj!R=~oL
zY$IKrc_8x?fDFs5PtAe;L)mX#AS1G87l4e)UZ6*2OlI7IDH)g5?f}|^%%=)4ld^sv
zxHcubKo#}VG7rk5&&Vusu=GgQ_BzO{Y&T_JY~`~Xz}d;an}NE$eB>yg9pw2-K^*0s
zuYx$qO;)Pfb&;nuz>=%Hit^w`<vZADJSI>17Q{`yVJ-&hE@x}O9hZku8H|TKgnr$g
z@~sk>@REloL&RIYECig7{C+z6PRLW9fET{<pB#bdC;xg6{PmaHeT=@7@+bd-!YO%?
zmfn8>@>eqfdRp%P8^{@XWe-LlC>MqUEl6Ix0KcSQ`NkHQ50UHXG<jAYJPOcI`NS7c
z2$T0v1xUC&lCs<9<ceuvM#y)|KqBRKwIEUQ4f()4FW*H~iqZ1pbV!Pk$L*%?gU8C7
z=mVv3@)G)$#mnEKy0;7RUn;>R$XN$5ibT05Eyx$;J*O~jN%B9bLg12o{%QP0lI0sN
z0W?Lvh3Yy|<trnhepwzn357KI(xu?i<)>c)mm$9#46rNm4B7-_%D?cW{}FgqE~2+$
zmb{N%^x5*Bhmg4@|BAjWoFjiZ7W%nzKl-ib$xA6Lab13eiNV~EOA67KFF$Yr=5NXs
zRNGx3Uw8u8g>t76kRtiQPchJ9xx*Ut-I9OEhr(_7KS@w8k^gWXhODLX2#RHu$-_c1
zQRQ;&3Ye&npP*oSr95Q_`c?9`>7`gLFEheYjlA|c6l>-GIzXXLe&BIfs+W%~L1Tm5
zpK`a2^5yi3ZIZvg5nQwUSNaA<i+tT@Ag%J}>6hOo|B|)@?N<5h$C&31`I;oOcFL2#
z1lJ|sdKTup<@FSVx+CBFB+&Zg!(Tz9U!HUlA_MaEL9lyQ-rfc7p8QcQMDEMav_o%D
zu2%wkNPdR4UJvAHl<papcOHWJLpk?2^hV@cOyEZ4Ru{TYFeYE~EM{n2zT!zt&4k?a
z8iqY7uN{WWl>A~Y8mHw_x*{<nPhvpfk^C__OV7&1cR*|vuTWgTPO*g&*!GG#6%-s4
z`)Oa~s8~x!X(xs4KXB%VVkhm3oE67x(dVMrYuyG=S4Dgp$Wg@<8=c1##}C1MH^t_;
z7@E7{sY&!5S3K2=QFtgGqeQf);$=Flcq#7ego3x?(@)@qk7CtZuyjHZ6^=e%g>4wr
z{S+@g3w3|R0HqdBD(a`8a7yv?Rd^Vn_~WP*Zk$%EqFw(PMJnwT0~Mat;DQuctH1>-
z?o0tKL@~J&*k={5`oN1&MfMmP!xW<wWe8WODA;#SF`u?M5sK9RHkS%Z3AiZ5A&M@X
zSJb(Hi&p$g4@Zn*mX_dH#mdL&`HNHhwiGb&iUm}WaY6A^8AyUcw-YjnijZbtUsU9E
z!+errCpOh{FDZ^w<z=#>jOr9p6t&+$AypB)64;j&?Np(Yrr7@k6w(!al#I+!eEu>N
zt|)Q`FnO5@6~&;hDx^3RTIXgdCf5KaTk#Urp<Gk^Ox5-|ie^Xnl&dJy13OP4YX{nO
z#VcNz#2bn|bUMmceCz?qn~Hs{P%lta9{^XZm{SMtmf}5nDsC%|KM#cx#dfM6D^<Mi
z3=3t7-5iLNE2R6NV69MmcLFk%3iE%FONA%JU#b<gPeP_f@oEx0tyLW7z+jzXWCSqv
zih*D>HYlbjgx;w5dKjQh3jGHdTC?H{y4v2ND1R2DRk8Or^x71Qw_+^qioL%BvqRBH
zYi_4v>IU?>tcpi;(Ct>NrwWieidAm|yGP;p6%>0FjuTMqQ>68Q^eZ-g1N{L-0F{p1
zRW#Dk^qyil)#=?=oY(;MK}9-+9)=XL6fAh4_}?T<3@cJ;)q1FCqRXNqimmkP8dX@$
z&>K@&pZEka;|g;puqPBk3bs!wo+FtlMS?qIrWJ-TI5VTjkpTOV;+2muU9*ZUJAh`Z
z^rxVXozgfD>h{Xd=)mZp9Hj`aqw*<wD>*5HY14B=`5x6(I4hkF!fh92=tV%gDxa{@
zd*P_ElhP;0ltc7MHaF$c1JHL@c2Fhbab+(Zgglg-0_b}x6J24+OIgqW^WMr8bkg)u
zF0}ydgt8z6lD<lbFHroHDVZ?uuk@$g<Vj`C=OCw)v2o}NP{z^j>a>zuMfry_%5xu}
zGf-I&0WX4-N2s_nSjiKjFGRV&4cu8}EPWzARB21AW|;CW7nZ`6AMFJ>r_7}!W`xq8
zUdEBi`75CirBqUBz<FgSO+vJC%L#ZGqhvRLOHwL+1i7TtAEEl|Waa4=SV~h)QdS~e
z`3C*gGnAWt0ce)ei^65u%AWro4&}MSFj1uJ4TarX%56I!a$7l{GMpvKU+C9es(hUO
zK4nTJT{A0JChdSig>nfUr7M-S)8ML<yC|SmqvUR-_)D!a$s2Q7r~HcEiuKBJTc9;4
zGrM88QTZKxh@@GW;RQ=A%5$k0Q>!wHio@EJYwKXCUAdaF3Z2RYw6t_7rC9*$Rw`To
zc1L-P3xyu#vBOaBRbHdX>r=+sL192SkJe@DU8R(QXZMuTe(1cfy!;Yc2bH#zSshX`
zXn}j69Hq_lu<}p(B|TK~C{8@0%%FhYsPa8qpp7Z_>fz|Pa-je|O(?g}MtM@nS_5uc
zSt$nejB=Qg@{g3ibwF}f`OE-NY^|zpE@13bKTsgTLDiK5za3R6bf$Guy+E<IBdQ+S
zJ2|WD?*P<Q<^2W*dQ??P`|V>Y&2DgRs+8*>?y7n^fE`!uq+Pp*YCpwvyi{eBBk)%F
zX26h->fR@SKA|e4N+w^G^~E+&Kh?lGICV-DK&8t8st3QqnbRtf5<@$qO8E+XfvV4_
z%rHoGhqeS~RX<+A&_Y#xYKVlXnzx}bLbc{8coC^uLsw;^R5A~c7*%R6492SD-@$yG
zN}dnN1XWiVBokH3taPlps5+d7&ScedD?n0It4AS|s#^0RxOCOM0*om`mG%XEx}tjK
zAkeZ@+b+Rwwu<`}yuYRj9s^2_swo@>b5(t`p~+Ld&V$?eDo?5iys3II9$bNn5sJP-
z)oRKS6sf-1OVO)hRn*h)rbK0Z9x|n>7wIfrrfNM6gXO9v0+_E*g;GIBr7Dr)wlylh
zdg#}xHr)rQQxzw}M58Lr24GDpRTG?PRwYseN1JNwMHp;XMN_b#L#3uneW%Jb6&AWw
zm0wf-uUqvJy;Se1a>CJiUp1BnnL*W$6nYp^O;F+I0~MEUh779~^Z@OlDm?}YBdR`c
z^o^>Xr^z2v9S(%Zxa#}Wusfle^9n>JRfV)mno|8pHy)-{2PtShqdGw)YL8So@6!2i
zR<+m;t+s0Mub5dob>tm%+N)os?S_N8i>huN)jV5>IH}K+!u%2S*OZ}jR(~FcF}bKe
z8i8F`b;@@19aSHS!03;uedvJgrVeX?d3W`tV}L%cKKKiWhx#^MVD(n(DBWrGQSYSH
z`h@x*WxjpY&pCtmsnaXb>93woDXf!f!{;z~N}b9;Ux0cK?Fs|cva4`3NIkwBBv{=-
zJE#z~H5Gkl)oMyvhpOL8fEQuvt>FL*SHDCr<8$h7-vDNW+U;pHMq1S+o1h=1er5s2
zdtSYVp2}!-<vC1gjQSkCP2<!Lmp~(4Z3+Onpw6H`VuJd9F|ZTWt1d$1qWTF6*(a;p
ze*;R2dJPL)s`_a{xvW0(JS?TDZ_uGXUHuIuN;1?APH^Um+B&%aqM7PGitt`l@1`F{
zmO5oIV6xTRmoZ=0)aKV<B1g@nhdNjN%o&jD>Z6o`x~cA^(|UoronCH*YF{r5yGVU3
z6bi*^a|*ay>Q&JYxvfsh2Xu-0G<_zuRL%V#NSXS+mEN@F>cJxDSEy|lfmEu?l^|8>
zT}MEw)vaH`(>nFv32>%fZ3zQfgL;@^l#S|`KA31ypKXG_t!n-qaBb?v<V?HTlTwQv
z>MitA>{S0tHQ`<AQcB8qtF76Pyrb6qZpD=LsNbi9RIl1O38YUQ-iOA1^@B$s1L`-b
z0drUFLF?;1^|L0}9a7tK;mkwzhX3~R>Z5-^Z&Zy->Ua*+cKJ{kSC1XS1Wl-KuY{#Z
zb?;Z`n^M0fLEp66cm|C#>a6Yb{(GceUVzqF^+wv4*=t1fwJHaV=@<+;YCNc-!bvla
zZgd{ed`Zb$XH97Z%)4lWJ^*#qtU84e9@VU)#p{^HqJZ0On(yBR=dQV(19eZ0>_b@a
z(p(ONp0{Q%m2UWGj3`00&OM>&^#iD{hDEXSlN#4&VE2^f9eO7RXllO$Ij#9;5@=^M
z6)xZcHMzgTM2O}e3O$_F*zJWEp_%~-35RKxUxUGL&GZd$=QK<YU`A-z6jqPaq?@1+
zr72$nh4UKsvjDS3YZ5&%-Wbhcy8n=*DMnIc?j=nPg`1N#C8U_5382dfshY>FK)b9F
zQL#pv=1>;>o;5+&Ad;ck&V}1oG<F+6GBq9Vfn3$ZR>RRO&E})vvNcCKAbCxbK)-|>
zjqm`#a;=&K4$$&6P86WNu9@S6)*G6$wDjj|Zd3g8rY7WVSSrvwxD3|{HCeR07iqqE
z7cj*d-)|s!OLP4W^lobszQ)i>G>d))W~t^AZ}gRE*3*Jot{J9<u|gBk0KH1hoIs4e
zN@K;xdGRCH_>};=M)Nrj*tME1I(S;ADN2L+dd+@%;2SjC#?jZPncNN1r1_5itxmJ1
zqz9x$Gc^J8tr`vmn%Xp6XIN_2T&G&C4$XTT!F6ihrqf`TrtShTyEWzuuy;ozw@!oh
zXnG&On_dm42wb1$+$Ol+uQ45m{(z?HXK38jd`ltLdzz=k;O=WYsa#=D^M*G>hBWgx
z!tMi2R29gu=1qz-Kh#ump)jJEeu&0VjR$>PWlXb?YQ)Ahsc|3^ns0B@SzuCA9158k
z%`3Fsf22__#9(GMsdQ4c*VZkEh=VqjirO5tSNlPnw7zW+Iihu?#m`wA^E1#~w9ioz
z#Z~L_BnEm^+r1u=$FwakLBvh_-g{7R*KXSY3&*vg^vM(tt)r0Mf1cX^rNC1!?Yo~t
z!(019H73|cyPeje6WYQrF<yUd7Ny}&YD+1)cuMQ{0u%zYzr{lGw6;D1CeCQzkAZri
zw()T^25DDphe)t?866=)w96<daaJ3>9AKf^pK1FWrq#`*|B)K5^;`@0&uMLy=#0=-
z(1tfsyGIVtXsss|qsC}g(z+b0H73KSIPJsL7)89c?IA=iXivX_VJB!$)4!5Q)IRwx
z%wN>b&_O0iTSEtmOWMLhs3&Xx{S;h^HeU$IRILkr-`jdw`{EdUOVg%mz@}?6X=XFD
z>;(|LqTN&t>`d)Es%W~Zt=WLVWNB~F+caD2L>sYdS|ME;%h7&w0<Pt1Ke-9LJZ;Pe
zFnC>COE3Bx+FvM2p06FJpv+C}D-=d4(0<_$?+dM3<Hyi1(r)sA`C{!{`trjq?QbFA
zZflqJK(s`AmbT=jTAdTPGVKnkhb-5YTm)K$_HY*rR%$<A2!$%`^)!f7YxCy7ZjE+w
zF-WcU1cip`v^VIuT(6b?340CN5vosW)LJD^0If-zMuF32?K??mZP9+$0JK)^W8>i3
zw7IkiZ`UsP29waCUA`RC)v2}r8X{fVX1dkTqkWbxuJ>xkLtvs$+k}O6ZofA2IdB8o
zCA90ftMy2P`aNwXZRPK4<?Em~sBN@TLU~9VLK~_F+IR;zJghadf&EZh_YV|Dv@=w*
zHL6`q*`_gVGF|r?*KRI{PZQc|IwnkNcYO=JDeXWDxM}U$DR48|UrHhJNZYgm(6ib@
zba}*9w}6Uq>~w5r48mS_JD6_OI_Nn6gF#2#F)G1u(($Qa^@z?82N-AFHj3c8=z>Qv
ziLN>`g+q?&1g8LVOjl0Ny_;^09Ak3VZKas*aov{&sC(!>-T`Mkbuy|a_R@W2z*xL>
zCHEldqq`Q5#uK`pFDd`$t6M;EE<fG;C!pxB+q)hnPU;>6!<kb$Go=#(bXg{tKds9N
zMB^FVbBVwX)U7xU^Fca67D%w}=2tKuqElzX-?O?6yFo&A>%Rb4m`?s26e4tg(v~k$
zXWS2kDBYGQ+JBzcJzNhqS~tOkOpMM%8MIj4TPq<Nr(63rxOknj2{0FQiXccP=$Lem
zHc=;j0}2;)uU|)Fl5QU*v@Yqk=faC*-Q8uF(G*?qhv-YyZKN-!T-J?!kG?eBH*=wv
zuG7)PS~GN$9E|XaZfztCX6l}!j}KhcHU9&<S-OpvG3;#JK^4d~-Et2|=IBh6PS4dH
zp?y`JF7G}huj|G$(0D@^ND-!do#7NvZt4<0fWZQt3j$4Z3w2v4QBtJyd<=$)b?Y{R
z+_LI6(t>_l*S!=PB|5hsz?JG|Dau!-yL$s%x$fn6V7EdS^Z*)_x>7D0t8|smfK=-~
zqQpUsZt+DZ)avw95m=||{T>SSy73;623;HdbQ*O=s_SjiDPO}}H0yS!gS6<Z47ya&
zs(auE(xwaFjKOs3!e}GbrHecU6WzL}+hO;PZe=I99^Fz4BztwgQbx8<_w%Qa?AJ|K
zf(+<v?qW*r>Wa3*r+c~=>12Fg=OhLh)D7dbF?UEeNN2kTI%mqw59=DNlrn#)bEl)v
zh%S_>6-RZ?(GoGHn{Nj)u6u@3K@+;$lx>>S)vpB1l&+IrvC}$ls`Q@Gr92IkN4jMc
zH=Wgu(k{zZ-@$_kJN?cMn77wQ&cVnW^e47M&r!d6If#?qZ$Is5j_8XhPUftCl75IT
z`k#ZK=&BzMK;Kcl{x}qm>90kh(M|s@nRnN3paSUQ`u}|c1rL2W{pLLNCQ52}=_N_<
z$y>jV-ta#9q#THx&__HCFkgM34u<^n*S-OmzrOvc|Gqz==h>n2lz#V{Pz=zw(BJ8_
ze&Ai8oza)l$`q)dPsJ@k`urCG8m#|>O2tC;=P1S!rk@D}3D>vK4>3}oKpUwjee@Yf
zp4Sia;cu+oNsal9({FtOdhz;cTPURJ7yb3$|7X)TZHG*n{_pQ$FkK&B081JA4UYru
zioT0ZNtyabbcDI8|CZjAS^9cPQfKS!s4DZCKK&_J%F%ClA1JwchfG+?)Bj32zU%sb
zH^I^keJCA-^7VW7U@mUz8>mjNK+l{95o@8|T?m*Wy_sU?#rmf|fW|HTg^e(HTd&kX
zrbKT)j>b~`@KaDM(?3P&fO36d7v`x#|8_Q<snpA@;Hvb_3xHCsze86OYxIw81*z5F
zq_Uqn{c#b7RIjf-2+Rh3G}Q?;`W(r6$-0Q5CawCLYcYa0{USP7w(FmyBSwebL|Kkb
zy*+&wrc1xZ6I{3ck9_Ff(I*Fi>(TQ=VY64yaRN%8KCTmk?AQNBf0P0JrxbR-tN(z~
zW%u+wp1{1X-_`<u2KCQT`TUUnC+i^C2l`sN&oQjGq2203{fYo!kLYLUk2<Qi(%tGY
zeMJl`jqAT&3T{Hbjf(pw^^J$%%#?oVPLN0X<q2?fR-bVQ*tUi~EU|O#3|DF}oA!pS
z-Z11~cq<dmI2wMQ1(=iJ&Hq`Uam4V__W*S^Tznm(E{3Iv=yWw~qBPP`gEj_e#|%y#
zFz9ADmx4ZbgXbjrjvIE;vB$$;rLBUe;lUdigqNXD24}ntIyZ1WhKnoc88A2<f~2n@
zh)&afhCNhC=5J8!p*wg11~a`VP8-fo0sD-hl&T8?4c$S22{H_1!oy(0dw)VC#851O
z$XUa(K7fWAlmruIxIw?ZaKpY3IC{=-kFxv`hP~bxOQhk$H$kEd4k1uDZ!k6jEZX2o
z;fff;Jv<nj=f)aTD*+Q{&}{~GyrD4$ofixjD43UE_+=?H5)DgI!Cf@;IDktsWMsmb
zO9sh&3_IDdxd>c}p^yFssfNowz1LV)zd>MKF@)3aDAS;vgy2=f%2D{4Wq9g38nX=#
zQovm^B))*Y977hRz;X>Q?FC4l!D|cLy>5`@0Of|E(E<bchRhlK1#cR@xeBhp&_&-y
zEHvz=oM@5ZAF2v1HpEih_$|XBE4@N)8(itOT#2FRAB?Zmz*&l^C^Ninz);E!C9|+p
zVR(U7qe?@V5(cXb!?fI18*Z?GR%6)x4jO9>)AWa^GmQNUlzM}RGMx>EurBB|8a|>o
zNt0pmRTyeE_)~nK%`o~eWtQ3v>mp#V!|-c4hSq5ic|gC*peciE-G-Jg(RattN`>-0
z2E7FOy@n%i0j<x_vL5RFhLjK}3>Zcp!Kb^1Z2Gg@GuTn~=)S=~1$Tpn3r|3O$WWAo
zz6XXY_t7_O__309HV+N;;XoTP?41LHqlVW$h8JUopJ*|hG$@qNpE88gp=a7Kk0Mnw
zhO}dld}K)Kh51>-uOXNxTjR@gG0o2CcN!+_jX$k|o`Z1%ZAl!Bx8}e#C!>tAMn{Z4
z(#14qV+MW){JAd1CQ3B98V$Fgc+~hN1p$s3*Zl+;H)E;~Kkr4WKV1m-G(Ni*C|<^2
z>B5G$asDbe=wp16cEKl%^B)K2Yy6Os)PBa)5-9i^*U}<&(x{?@$0_4^1sVg4H56_>
zZQO1IcgFYwElYvMy|iHsGOFxBf{l^%iVQJ^{0r`^@t!pX*r7&#F<Qfn-9JMk+&KOz
z?4C3BEdyGF@en1OBaIw-mZFSvsD|Ra@lCo?8EyRV21tx?={K0ySmXRRz{MGJ76Uup
z7}^T;3&u}qqn%*1je<y`(K!O@7mbn!n3p8us=HQTUosBSvyp5}pcq(+@p(#kq#9Wh
z(7$YqrF~$UF_ID<=|;($P|PrTQN_y@<MY>GFw?lz6Ma{WOFhtd&FDq9A##jGbgaoW
zZkiAEJfq!wh+H??P%*#_<Hj~jWxml(N9o6###2<rR$yF1(bPht)Dfh}I7#&t#l~G!
zXLQT>*8zy!HnuJUS7P*KL%-B`ay3kp8JAE^UAfVRs+%i}3j<-P()h}1NLCpi&@x(W
ztm^=&F}^0p0BenRDO6Ht<e)6eI=9{!W`Rb7(U%fLjm8s);eM0RH5s7I#;a76)?&<}
zMZMMdDussHjINJCq22gIJ`8pk<0$&uX_V5*smoaH4AO0!s)pVjBZCgXJ;vDt_}gpT
z5C`=>V~P?A{l?l6h*$@VHhlbn?izohn>6=~>nN0c-}v@ExIbvDr_KM6@h<^j9vDm3
z0cO~^{WXw>#v3of(ulD-1$v{#;wM4Ij4x%t#JKS~ZE+`z>*=*IX?*YyLz*()ZHC^o
zv5oFD%^21F=zC-}+R<I1S)<z{Sh6*JM1Nm9lZBQkds9_1G#pGyiflQWM(ELWG9@2|
zB^T3rH5y$_JKlrHQPZX>^c^!Du*H<PnerNe>25mvEx6;RAu2-fFx|NhJx|kGDlzji
zEqfgb-X^PAk5(VkA5_tF!t_`GM(=Cdw-Ln8bcR9z{-#5HASX>*`=N2lw1HNJ08<{V
zU8ha?AEEJ#X|*2=2AZ;|HZ;hzO$MKWO)LH@hc<ok2^7wn>NmhpsA)BoAcmQW&q6)i
zw7~ik*mI^T`gui|-lD4ANYiH&@r*L*Dbsk~bnajDMVmgmjJ_CCu>okYrfxg<6ldy>
z#$3jmR?y4-g6XAJ=p~q1=#`Xc>ir9S7fm^opG`6yAA{Z{6GsPslTD|nf+NLLxQ1T+
zsiwSojQ6tX8LD(kGrdaRWk@&WjH55ZwD5oEyJGq`7w%`8wBG2uYI1D@T9#=)9R;#Y
zr(S{iYo>KnJey;3TnvR=(>6L0<e41UP`GZ|MBg&KVS3>{6!J|$?_ex9O}`{l__e_F
zJN;%0P5(?orpWY1EM$sJ#VUZ7n8s9axYTt10z}G8hw1Q8Zi;#yA{C~u4#PyH>Dk4Q
ztTK6RhxuyLzO@)cjmhm947=7Op?7|rDTO5KO<y&GYcS2+gP}&#K^xlsHkr;O1FhL)
zp#*q~sb~jaT1`U~OKvkAqQ|)1w1!f^9j4xFOmL^^T0OA4Oz%7kOWmgOBT&C%I%&a}
zdQAQo;Y_cIN0G-qQ;aYC?Kfrp355aE;1zIpO+P#i=zFF|TzFx<Z(6q!t%D|o2Kqy$
z`kUx{U|K@g=!Z?8(^B}*^bMU-Mohm%z_n3RH7$i>rgId^9yd83h2Df|%^Tn*O$iOK
zG-dkq8JM3og+2#`8Iv#V1Rj~3=7XCxInW|xYwo@e6g#Uq>N~LZ=9k8y;b2}~2jXac
z_XiksGXG7Jf5g1&EqLK<uIYw`i+Q_0Ot_kdsZijk`CCe&9y1TV2J>#_Vyee-H^1zK
zzT@WjqcG@U{_IO&dYV(IZq&=1k_3C+=37rg&&O;%H;LIhZC*j4hco7@%V8<dyzDM4
z1(^?pLnGLH=qEIWn7c#}IcuKUkMV|@chFtrF!SGT=nFS9%g}eu?CyoWDD%XVP(N=z
z{0c;(%@eLbi7`Lk49QsYzFi=3=8h3ebG*6Ux*eWgF#l5wnFRA1+Dasvcdr7uXkPFN
zK$FbJsPU5d)ewLtn{8<Gnqsb{Uw5i`A`&Jpo7YpMCe0k<1TNjYhZesKb8i+Tub3ZA
zV@k5j1zl*&HXjmV*w@TE)gU=$lN*I!bIq|76V5Y#IS8k&o9_w%bHm(EA^&{yyOe~v
zX;v&kV}W_ae9T^<`I$cG6`8&02vcnS?o0IDGH<yG6SvJv<6*GG+#QL&Qu9)ZmX(<c
zUx!G!`NzM}S7F|}2Bg~T&`8%WYRu7}K&IBbg+eBE=A9Jls5cMZgxv;nYdJt0%?r#R
zP3D0y^fj9sDGSnKewiN8R`atu=(U*x%0b%AuhJ=|!^~d>$xicO+68u*KU0HroA)$f
zoOjHN1K>=LS%7jq>)c-R`9%=zGmlU`Nx#|mEVu#lolhZi*BmZ|#y#_@XVG`xywDLQ
z2F(YiV0Xy8Bn~1E%%T54WZ3NU6&fF!o9II~BW5=`#EzQJFM%^-<^cM(=cJiWyX`6S
zNl%bzb9w~~S!c{oM1p-}K10_pX3d4$z}Z=D&Vh!#<uj_Yb+BCSg<VIBmHy~Xmd(wu
zd&JUG0?ygeLzgFAEW0Th>S~FmvXG;e78^7kv%EV95jV?gOW}pP<sjYcIBp4`H>`(c
zZ2}ZLt(MhP<?m%#NU<Sr%U85B_OZm#?)QXcJ*7W<Ew5fjqn{;v3U>W1+bAk|(z21_
z3a2dh?V%T7Db%3xwB^@p06k+7jRG^!vX^dx23clVKnb=mDS{qiIYkHavzAuch=p3L
zN%VUTv%Ek_jd05uI=`H=d`UH15tiFe05sC_x)Y`}%F;rch#1RSdc<Qbr>KA|&QeYn
zEaNTF6b!mxv9*U@g5@9smJ%)h<3atRrHZ1kNtSi=d%9#<K?k&Ciz_W<DVEo)?eHem
zvX}C-mn~_p!2LAK{#_8gX6YXWmt)b;%9Lx_O0UQ~%SIN=U$-p#8wPJ!Dtw`S(;|BZ
z<1Mg!PUXdgmTWpf6j}DUK&04`{xw8yTO6{1QetuZ3w@=Q4=71iW;y+;6=>y_o(r&4
zX*oo>rz(qt7SC$SAT44wmK=J<YAv($d#tm}tA|3pWjqlg4VK@}U}%k&{z8~<vdowu
z*=#XMV7JAxARHrXwd|)of173Da}a5_^wnWzIxP7VaqP5gD5vMI%Tn_r=Ca%JI;HdO
zSZZmn*JJtX1CU<J0~J93&(U?qWnFb~%hc-4GA(no)lAFE%xCYtCz@ruEK5zxQD*hv
z1OY*1FWJbDCCF4+G6h6I1QprHk|{%myx-Gb=X38l-*e8r&u`p&&bhy*YyHdth;*;d
zn+;&k`V;gNc(9&Ng%!Q)8#kh}Z~e!iX!Wn3Hv}@UzMSIIgX@hfm>*hyw-i1-T#x@5
z#m%w)3@sN%*0Zt7vCSG?&shWC#@D|>6(AGqgLc8-<obmzFh8|Ep%I;r*N@MIYt!r7
zsc8QoBb)L(hZsT%;~ZxEa~tFc<Fkd}9c8$_0A&u0)l>-L$oOyx%pYewq94YI;X`pm
zXGUTSL{2cC?}HYbE90$Xh`KR;rNG=t#=H*5oMPlCq4YFkHYG#c8Ea_;=D|=e0P$oz
zOVML5M%xR(c{7eBLBxmgEp2ms85a}K>Bm?>i*SF&xCzPv7_Z#Jumc%xAA_7>IQD@A
zF+QaiL9mUn;0MTrFb)sEsZhrE^o9>()V87(&RAXmgAt6FKp2c<q?Uo4Wr)NOiDHzj
zg28CUZ}j=67)Cgq2Z&`{cp2mzLmGtNK8_J20U(|cvKbyGF#2bsmB={4hWTX17^NRm
z7`Ah?Bfh|B)4)<HBYq|PPGih(1|psDJw;(N8Sb<q$ztrMZyR1@3_T0UON@YdFn^ix
z(u;5=hjHmHaJh_(U?|OFWYBrId`4U<MtFrGOom7y!@&(hDq>_uL3J@BdOJi)7z=C*
z0W4*FOUFyEGE9^uD`U){Cu%w4AQdZDFmzM^eT}h-(ukFe9a~}II^*~M_B@Q-aNw#K
zc5|S+nz4XZLN^)tRLWPwX!XR%ZZVW^08q<VL}9c##sa#HZZm$TE8z}fsE_WyyNnK6
zKG!og)5Ug=;XDE_8W?xz(a^|f7zD71k+BP{W`@`c?zb@RBmm#akW|6ZHb%y;n5TBe
zpMkJ@pYb^zG3;Pm{1Bv*vH4?k_AowbhM@<HvMi|XWo()RppQ{Lo9@4UM%`PG8DPBh
zGQ1dKyt4qnhm0qdp>vqAVJ=!DjJ1p4#VF%Z1b~kidnnm8&PbgNGQqG=9CMPf`#eOZ
z7>DR?nr7Uijhj8QmqOSFnVl57KE&J?0{CI(S3BXw5$1I)Ol-4`GP7OLdyM(&TxfG(
zYA6rj$oz&fhR2y7^`Pa%Tyq00XXdRPm{J$!Zn_>%Fjvxs)0O$kAm+l2*}njtCz(&u
zQsNYI!5Wx2&Adf9Nq6SI{@{5q=g`~RlbK4TnqJH#Klo(xW)_b@jSq9%w?OzZ8$@u}
zkD1#CyZ%hce+Bu>Q&f2p$eg6z;2CD?^Y9{w`S(WPf|+kGgqjeh*F9JYW%^STFoNki
z2rnX;1+*tU%bY`BNr+;;`4QmJ%!C3MieYw9Tp-rQ{7eEw9P`@^5RGS6(y6Zm=2Q;6
zNMy1oAC|;?L>ZFv%%wj7n9MY;0`CH|>k|M{nH`j`Ok?__<2OiW%6dUEn5h)?%w!69
zAX&_^Y`AujId>n1bcuQ26|Kw6m#K&#n`!&-77)42RaY=IdCYWwwDOt1QR?gp)00v<
z1xzUg6APIQwBIdao}U9RN|@|Vpu3d$r!PdVGBe%;yo~wYi%?q5obL$}70lUGl5mab
zMIK&fHdFrL2J_a(&{D;GOu@2h=5E_PFmEz<)qq*UJVxhAZ!r_;i%WG(9vv{b&Gb%#
zi95^#^a#Jpe2ofq>Y4B5qO*~?>?0U#Vvg8DTQjrnMa)bKGk6;$TbWDUFo-s0H0@>E
znU`o+*1@a{0-%#Ap>1aubL;}`|GJqoH$htuv;QWXdBAL;>}M}?%}*fxOqVCnIl#Qw
z0KW&BmZbm;F}FAX|BxB5AFW|#*m39{VMaSZ%P8~7GcZ5KjQ9+#N6fG3XyQ0C;#UAB
znfu>?mMLbZJN$jj?5Lyo%QSQDk1%1+3Z8<@LDnN$`y67~*bqI!Dpo_=Q5NSj@Q$%u
zc4A5#Sf?l;;K<tgGjtzkjfO#+6RWfl23=SRI=gv-_1i-LTv;>Qq0Ehy8Gz1{tPiB{
z_Y|w<Z{SX|{KYeH|9P+uYy{Jj<?}lbUaUIWEP1o`tOW64<-Z4|{;V=8PYhtGsXjN5
z)ti9U8CHA~T0yMs+3-G?_0uz$t`OEN+B}D`Vs}9#oRzs5A`z@j;pmKH{W2e&XIU@N
z=%ZL$Xr*e4X7$r?h*;Je$02i$Wq%31aje9%=!|D&Qg|+bHJe_liL9k(z)NDe(QfcO
z>w|AWl38!j?VG|nX~xhlu$<_wNMrr}1iVjYG3X(b!J6{~29e29yFfCFl_STmb&*y7
z7gS%evG%q@CY!Z=9QYhogb<>+tnVrMl*bCAmsCE>Wf@vmSWD?*DPZY~K#EwYSI}9^
zdX<*+C9HKhAf>E7{siwTOSTa|S{cj6gh)Bdb_nDe>jPS=RkBvnD)>5UGeu)=uxvfF
z602gp_ammJhV_dOBfQ1>k&al@ver}Ly^d8}2mEc;<$ut5hvh;$#k;Hnhe7VKUPu9H
zU~y=I8d*(^@VAL|R1fpbtY_(!(ZYI%19&TI!610;EP)#U_gVE<(CT1~+vr4DC+jX1
zs&}!xZo^<V>&>koJ*?+?0erw>EWv#BvJOy^yN}g04@&!4LzKZ8WIdviz9AO(GDIG-
zq7J}|Vb+8Nx<^>al(QOTF{$QijAcigoN-q5^BCs@%VP>&OtQq=>HRmw%C<uHW0vI>
znA0qmRrp2h*?;T<Im8xF#r9$L0g4$OVLwHSt)uK6^ur!wZ=ofS1ADw1I7fEKN04-4
zzqkZEXLj>qIOD>8g9`aiuuXmtab=&NEyOAIG@VO3&A$Hx1<Bpng<FB}U^~x-!=CKY
zr{S;{`zMm|X0NP*hra9^RPyY{4i-bHKl__}3_E~r{2w|4+2fx8cZS_Xi?ks2vdb_S
z!j7kucPRVxPPD?<&-@Rrg|l0>!ixxYM>{$r*=o0EasQoVZ>L0f6nk|PNHn{RO3h-}
z2PhpB%N9J3@y4+iti%Mxvt^9{Ca`1ZP(&hIK?jGD*x!5)-g&l_LIBBZyNfV!fqkk7
zB$b_h0sf}3J19Go&Sq|a+ZpV;<B+__&Uz6z+a>mcKVa}OyVwheY_`xFB!_*Iw#2#Y
zGjMTM9(&tCbY5YP-vqvZ?Mz?XEoARWfcYZ!u~29$X20_t=Bb2Ta0muV*%yZ)S;qc|
zUTWp+eyVq^U`Opk>l(X62-TJB-=9F|bsIZ`7XLTclWKTT#a`(RQq4}L`1Vb<k@loD
zZ0QKxuVsf)l|~(V*}E`*o4uamiFerUyP)kZyN;?$>e+`K;LJVt)c4>uvR?{-WD`5)
z0Z22uV+e*?*xO%&>Q;6l)tTRC+gd3@+QHrxfZk4aLmu#5?03o`+RYxCfmRQDn-U@q
z*nEnM_p#%zpw-VVSphP@{`EF=53&okLE8{J<!^{QWWPl@qhWR~r3pvb0rbilW6v&z
zvPbOqiZSeQ_SQ3)ya~41M$xNDwhJBknPPiV$m22lb;{RGvk%a8+jDa0vOLHM<^Xt@
z^CDGw9N~Dq1WQLbdns#ojPo>=t2=N?jzFm+ry~X;$2q@IV9S~F?^=ksaGFD)>;%WK
z5+bggm9!yo<G5_KLFP24Gz?954(B7ZJUHq;==S6k%!f~2oKzDA<ISm`i^2GCjGeIL
z$8lN!NBuc}w*VKw(L4u0AZIx}tj}=TZr~RQ;#jEYBAD|VEjL0rC+U3<#yK$pKse`M
z4M+s1;(1zsMsogo9r&}H8v2%a6h};J@n}wKB@i*3+1?P1<;<T8-Z@V6`xs0-$1w?j
z1WqP>sUne6tAb<_=Pg>Foad~Kfca!jJ;nM{IIahvES0nPTTDqBM}H3_om2Wb02!PO
zZnXc)<W$gO`VwarMMo}kUN3}9HfJ~OWO6v2^}y$HdWt~uIN@8MG@tY0N{s0WCy2Ja
z1)S0dbQW>e&4NfV$4vqcOE`Z~-DxT3(kh5t<?LJ!)#aQG%Ym!lB&xx?#;K-K729==
zBfa)-aBNDt0XS<Yep=1>ot~&SIp&W*YB-;_L-#Gt-7vUT$LTu;a+}jy0o)yqY!tk^
zoHcdOR?oRN48T23sR+CVPATomnmD_jg6d{YBmLMdoQMPfS~-IhZEmx1gp?X@=geIN
z7dtt-tKfbYr&b8k&H20@z#h&Uw0eKQ386cum$TIf$v#d~7qs<rR?<>&fb(Dj$PnjU
zE|fjwT&307Fy~4LL`FDYQ*v&U^LrMwJmM@JMQfZRqw0<cj%`jSdZ#$P3BW(*80kWs
z=G>xBQ`vKesa)b9S9TU^4sjE^(K^hvQNrRVcWE9Zk8wY6M$3Ww_bdP$xzAIr$Z_t^
zg;3_iU3nan;LLTUC-@2OKT=4#aurl7>BjY@xBp3QhK(NDr?~!<y*bUzTL3kl+{wSu
z^5VYy1qSNP{d6Z<KHNwOulsVl)&t<jZHq(8pS#$ERsi?oR5%mJ4Lb#R5O+3eFlGgF
zS1v^>g!?NkOhUOU=(!xmt<1r!M{wgPY8=TO_?mu_vs^u;Nu#+-=!qP|t$h~wSZ+0a
zOYR)E7pt^caolq&AsNs8X+7`>+zLLFCUL*p12yNlnRNdoa~CgxND6lw-KiJ26aRyU
zsa&sb(V50gI*;ojgL`Za;F;W~QUK55c2!gP%|&hxz4kA0KV_l!GS`#RfVtd{_)wF_
zy;=@@KKCC6T35JAx}6HR?`DA%awQZbEaH06TE3Y3>{*DEaCNHzFXe8c<C0goZ*_oI
z#?@zGNafsLseYn@n;nF?xW?V%MdhcJ+!#tHT;~>2t@I6Uy$Ym?8*2ulnmacX<R*7V
z4%F0g=g`Knj=M4q=5KRf{{@nFxO=FU_AdA1Fqp6B=F?{79(VH$v>Lcy(W|PF`ws=p
znz*GbkY?_8&jQ}UeU%NfwpQ--6VTnp{f>gU?cCxljOjjikO~AkxWn5qC7oQ;WdOUl
zuhEXan>(oozK1(Vw?iNI<JIt@pUV$IYk<3Y9PmNzKR01_h&xOn|A*Y{cVJ<dD}4_-
zN4PWhLFXvfffk%&Hm;d2wnyBrDK9<FEvFAYO>lWsS~AJ4NP)H~?s7duA9MHYMQfVN
z_!VmGd8*}5dXP8J0^A{9!T?%_c}u?o?-=het#%xEJKlu9j=YB=z>o9B9HH8Y$LE7M
z^ZaPJ?!vSENCr>vI<JDb^0vJR6K=dhx;#(vE{vk{G%x)ToN?#%P)ON>cl7~)o;>SU
zu;j&aqSu)>Z-x_y56_-rjlR6KwA%6G#Zc_qpZCZUya3)ObSD1{?;oln4dSh#eR43*
z$3`o-5Z>#l0EY7Zp~{vpUThgU!+Al0up7bKxCx?>ydQF*^eiv14!kH{@s}Vmyt|*n
zi&)-aT2P(iUA_v};&>;tuoTZ*FasokC!|niBJX=z^(XPpP^#@bZ$~RSlX-<p>GQuS
zy!CW>rSVGX8Jf-uSqzyB-iLJZAd?qNY2qxN3tbQwdEz<fyu?e|0%tDscD)Xg%}b?V
zUk>j*7I3+|jr4)JeBO!Q;Pw?>Dt%I_fHyV_Tp@3R3&vT*o7DzDG0$TueSWQk_s=d2
zw3O%fE)Z9F4peAR#{1<QWXgG#!@ytTF$OWTO5WE$qw_j1Vj+CG!3&^+VO2ac7Y3_&
zE9hG*H+d_Q0I1<5Q1<f{Pgx6{wY)oDL!^%PVIV~A@D9@FIPda`8!7)@&s#}X;62`7
z`2aTX^nZag@_t_jU=wev7NX6(t+b_X;idMYvz51jUXg7)FAB|e@V?5&m^yjmw50Fi
z9U6s5H}6MEy!Y_ZDLnUp=iCK<dwB^|w%W(L7zIE-Z<qp9>H*$CN+1mK3MwJ`koWFl
z$PDu;D&X)4?>HYOMtNVxL+Kdr9TzzBh*vHL8Rva*6pl{t7QX~-le`t~?DnNL$q(o|
z#6R~M(1-b-Q=sPv|1bpykMbA#gB;`AmqDci{|uciaOD3?Gjg2I{Rm2&`0dFMapC_<
zkK7ad-|}G9mH$cxI^FoLQ2?Ce|3(+yDgG1mI6lqqj>Q<<`AdEV@!-E>qt~t{UrBi|
zFaGv5P~*!FK8=<iKm2J7%%AT_iQoW!9c2mv`AaC}bcSE?JlqcAZ*l@4m_IKDCPMh*
zbdDyJU$qYN62|{w2$B)}Y1%YL^53(A<XQef`lwhG-)l20MDrsOshB#3KSWWoSbod{
zICGBw3a$3z__H^I#PbIi0+_%*L$9bLzWoif&hve#x+s}Ho8Dq6{KsCfdx0N86(gzq
zUixNM8sBjy%%}6`^DyiT{=P`4&g7e@%r%QIY=X!o{)C*~CYSkPv9OfQ|E>`vhrf-M
zy}5k$-ynJXUp~bzlFyH;hKVcuK^Kq$zHA%p7V_UOhfhWPpXexYDgQJrv#;`JHv&+`
z51#?aa{lZ0AyUEbqnFV&{=98)rjpP44I<b1@(4Oibb}vBh09g^0SOS*eBlF#*6=^1
znzdW}mbKv3@_BL4UB~~C-XFL5@BR*@clgKsA$gbYLlx!q{6yM!-Q&+CWexlYdU7}N
zucbhwnO}Psq=lba16(U#UJ70tKROn;7u)%-QPTB3e^D=bJNUWojU6x9;-=B);j{h*
z>E%D9L#2Iu*N>pOpZ~8r20y@GOgpqezNZajh+j;{{T}kyr^1P0es&`yNBAed0DP1$
zKLo%SUrBMa3I4ORDVgMF(oZnO|A@lpkNJ@lRGa2E(|0251<%;Nfx&|U3%PVikb4&7
zuwdH(;ExEhPXT{akYT|bItVUMYQRx2No&yKf^oVPodj=EjgqrKxeU&@2&C=!Ax{X*
zTcOicF!K}4ft#T540tC6&zD2>DZwy3YTX6i*%0v%+%Zs&*HciC1fZATokH|_3x59*
z4*Lk?bXLVzkVgjn1hKII`U_4qLur8E?iWxRD2NHfTm%V1g5gE5;1>y6A%fF9v_b{e
zM6|*LEjM5xT<{H*+C>NiN$89eJlO=1vw|<P=o3Rxg0H9;F<Rh6FQapU)o;UYoZtv;
z;Nt~L_hX<5g4M0?B2loN7LiGU5h{m2FSu3<T(aN?3XY`+yrR*%APBpLR;oZoFU@p;
z^&7x51pFe9OhG6;1F{4%9^e-Rui-U`PYem>7s2jjfsqGhw%`(l4|4?kC7AA9!90re
z<q3AvZsv-B>y1`{;1?>OFBAm+4pJoOp{!xCAdg<?C4%`E0WTH2MmzSag1^22DHA0A
z0LgN}vPBqDh2Y~WFkdP7>>2oLyDnJ90rQ4HM`?#D0b>;NTrG%?htivZY5_=%AX^DF
zw*<ilp}SV_g)drlf~4DU=C)w341jvUE;{IXPhg>SW`jUL#d6I82Ree^BH+D^(YFdN
z{|V9~2y=tI2Z9T<ZR)iN7Ss8rK7oj0<oyDc9%MiePmhE_0Y4fhh6FEehUi0qN{$f@
z3z80E6eEKEy=aXJ{O3btOi=m?Iv)wRc90ww{I&z|2|>RzIwu9nX^<&F#c}{13wkz#
zObh;f70%cTZD0KY#6h9cuaG$;jGzw`9u@{umFW@TG#!*ZDm<dZn2rhW@Guw$;p8qD
zbQF3~&FFC<pDuDI;evI*IScdY^Q109HWi|u5bEjdpsO&5>KWXGHS|C`DZKs%0H=hU
zP;{Oa=GolQbQiv51=B<L^fur<h1X~U?<H(AVe-9&MbS{>BNS2|*H_4(cdwr?fDQ!v
z3qPdjWq@#R0<;7QgXy7lMmUoS7K4OhdS?d<BYGhjA}r5GXQ)tL1)X8S97^DX3wa;Y
zGbKWp?gxCN@ZPr&JuCca5HeB1j>VXgXyK=;Kw^Y<4H#3b@F@!8ofAHH661{%Ubuys
zi5LF&q38tRS$a_>3SH<DND{vI4h)_be!_%gvap#xWtJig@r6$pgnv^;AyqhDNcUfw
z@Gvb)(uGb`P>><qNh|nFq4N(wWC{0gL+54TK?WSn7QR7yq8#CaNjQ@$e3PmZ@`Tzr
zh~x`<sJQ8hP<j^d0^x>B;1vq9K7da}!hsgFiiKw=YFQ%u<0huLRQLyq4Q#Wn3g^-C
zx=a}L3h?E^@;k6wAzZ!<h-<=DTBlYDpPvQu*M)v`|J@MgaL`#L%%X2FRSU<csN<$^
z#uxCSMmX^pT5bs|?xV9-*cpY+I^jhs{=6;hy8|tEgng7nzAJoY2xe{d!XGVAdQYgK
z3hD-7(>mZAg<sXeizZ=bBTO_4jl0ll5e8GJtyO3|4?vr6t{Fd5yRb+E-hE+i5Lz9=
zcYlPIPNC;wban|>(hIs<=t7lJJwhKU?tUPQpzj^^3J=iT*k=<qeu!qjaA5{y286e0
z2|Xy(51=(9T=*#v4}~sy5E&L0*1+zFQ1LrF92LHQ9U^1G`4okCBy6A&jtdL3!J7~&
zW@6Zr!bkBCnG*Iy!HdVjk@w)?wD5(Oq0?UEdIo@lB3rI2WDbc6C=+^Eq@f-35mD2d
zP<m7pLQ#QZqD?<T#6cwc7p^&qbo0<UF49M$<s|yYfR?j}P2cQy5&cA;hdLoz;|xbn
zimVMVaY__8iO$oaMbQ|qyGThzBpxCc%2IlYp0H6!#!Ixs88Y6Yxm23sBU=4m`H0Ay
zKDy>7Qc_uizo?!zY5}67RQMYx`kn6kGa@17pMpe>eBpMmXs!%OLqu;Z#ppvt%NoH8
z6SYymJzR7<9wHH<o$o*-QpEWZ<g6%bwhh-nl;{doRYZ$^`w^lsB1ej6#fqYo;GGls
z&%`9eiMCLFF<w-jj#h%mU<5u<w0{_qNuq7fK=*l3Iqd_IMb*2|N)fGl172JZ_0gs#
zRrGTbRHun}<WssRfWosGqH-UKac7Dq=75<c`iE*IE{ftQ41Y;fs({R8(eWO%vPH{(
zgPJ_i>p@VOFH+H=j4L906=tSDR8OU#g`!Japu0$v6a~p*kt>y?l!&fn0$wWWIR@NS
zQM*43m5JulaociHy5CbXzMfSf8oY%my(aoqhu%t&=xJ!XE^?a(e6{F^5ag!l5@m;K
zL`#{#-x9e{c(+#cStcawMEw+0xGf5%-N+r$HmcsdD+-`&R=wzRck$p$w%vB<YZCoK
z-yLZd;pvE*Nu;O4jjf`;D4f(LT0|FhyJ$UamG6txREFCj%6lKYPLU^7Ms|ssX2VXm
z=n<tOdqf%?;15K<O~b!lk<$hYp-(i6vPk`+=Q+R)hz8@~^q}a7tpTD#qV@404@F^=
zCLb1AE&w<p3JL`o6)m7u>zL?cHd>EFJ#45M7p1k}_nZ)EDR?+3n&}LsQ=*V;4D7M!
zlocY=BD)iC&0g%X7pf16!<!*_NF1;PvvgSOPgQkC#Q#oHYU-%?U%D)giA&~z=^&O;
z0>)A7{51?77bj8z#Yw#G4|w4$_Mu0gi+F;T2`9uYr!X{E@hi^(?k4_%N}EoKzoo+D
zQ)2lg@J@?U0wL)xeqRb@9^zkSz%@_t*45y7iFuB+^7j_k(Fag{#F@0J@)eKOz>=Rh
zbvs1;#eYyrEI|DF_wXW6{AVvj&WQi0h0-ALcS~U@SiG|cBt(3f)()ZK*QsPKO#J!R
zfJchIqMQG$cpZIBHA=kP5t7m3&w`;dMqKkTt^8xf-Q)1)ocI+gEQ=F=Lv_3H;_s-W
zI6=JlXJ|_lx0}#P63?W7*?IA>7HX2kOxkgzh|8Ry`+|4{MRilfpVG57P5i-O*i9E7
zrk!hsxbR5;GQ~GPg_bPw9?IEW6nBroknNKAY1$xO7R#Q8Xtww#E?PO_$4+SFioZRC
zf#!){^8m>gulgOjuZaKkfwlti779fcie3N0loW{{*nw9p=1_E~M7)w}r%T1dFGJZ?
zae5V6W#Yfn&?*=I@c^nT#OvuZIM;0AmnnK)DK4Q!@O5!5#R+eSQ+zR)Dscn-2UxY3
z`x-3W6knvpbFDb)3h;H}ry@aai;o=x?v8lg7Vz$hgQ%>nUi=At^5UNO$!v%;h!;`N
zq)}Y=9weK@0a@^(S<K%DkruJ7bQ6HB;>UE_woUv|1e|IYuYV7n_r>pXK{~{>6dUUl
zN9uv-5;G^!>K5;(KXU02AE40o1M%(vxZNxMk=`bK;v;m_qhGw7R!jrpW%TYI6wgeD
z$dGt~*1!+NuT$(}SbW$<+1L^BhB+`lDt<r}M`Plhw=s#2#B47h#>Jc70&haRo>Bpm
z;<J?SnG!pf0{2+lNkxd$;@Bsk&0b>Rfp<_+<PX3hNjPme4oiM+2JeW3@hOxYmDq4}
ze%3L`c1k%qNW9;oJf@>0buH{3mz3^@jFUwBBxcB2;z%zQ7s;X(&~`$yo+>h3C4LG3
z-6T`D(RotRNngx4C3(0WlBXp#wC!`3<j@7-Aqk|~AWw-@0pcZDL8pqnB?DB7<s)(U
z5n6mD?n~)!O#LL==yB&SIr1320TQ=sP!lLQ*#(1VBp0coD@d}Ls$_yC>5=d-M8dj{
zR;VQYFaTkaO{dWcmt6Y`fC$OlZ(u%BBJPHkvl6G17)y*~7sbS4C92QRIwy&vy0SRQ
z7{W>T8&k<%CCn#C>Q;axN>b)PX_6$8Zus+(8V*RZq$mu)6v@~!%+m!)$76VrDw+5P
zuBAzO=(}0zlCmG+MTX?pEzq4QN%<36vLv6<C2&#FPRC;}NoHJvh078(#Rsz`!4!bC
z<w!d2z(lU3`w~c=go#MqtbEBcFT>Im34=b1Q6PC#0bZeGUOp@pNnWC-SFvQ<dWe)r
zeoX|RRB~PmXRb<qeiH`EB(u1fgmOt~IZRYYI{M-7HOY?S@TpSr%G*$OUBa^i?}klM
zLic@@<U=ZTsFu_*q4cI?$2X9vkt}=~e&3S({uY$hN)p;3StofwFa5g`4<$P5C6B1G
z<DO)iN>~~s8I;6ol)Os$h$hL=A-L8o`EnS}v`F4BhKH?^fIpz6P4Y8s9@{1E%16)J
zxK8k|Q)0UfaF?W?wgKIeHMc=}BuYn!Kal*?2pzqWpm-?mlQ^vfpkLCz23`(G^b=4#
zD9L2N*&&JNN*H}8X|$j<EODWg#)zbVLaU<^uM6;UOd_ML!6V5fSMbIqcWl3-cS2H5
zA^%B9Jr#mXNp?|@<YP${`93ZA{S*w^OTV}ea!|U87JY}LV%mNmmewwZ+ef5b8{yhf
z=`sqr9FtxwgclCdRC;?jN_SU5*>UMss@ZjthU|t;XX%t90It$C3+Nr_CjD$Lyf`U6
zn*jVNsYeq!PfHzV!x?w!sdMP`kgn*!lz2)%eI7tB>A9bv+gm#NCv^Kre_sxsuk_>%
znDCSSNdxtlE}?gCfV7!5%z@JHzsGokr7uuKB1Fns3k#uAIs3oAvXR=TiY;6kN+F2|
zX-XiJMoJ9_VdAV*NL9j7(y0(=i<Z7P4PcBkhE5g4N^`eD@|<)ZkvQpY4~WD|e|ZX{
zPmtzNE+tWVhzr$8QrG{%i}TXBCBP+1XVQmPQl!gqq2aG=r0@L;rK!^XFbpkC`r9;s
z=~7lcv}H&QP0*bwUDX6&mUQR;pzWemOA(Dr(k%=~UY2gV4v}nW6{Y=iq>0-gk}F+C
zmsOtBKLogZ=>y8YU6Cfy<GVoG_Xr*qN*_}E$yOx2)r)4a^ts0%CDPWtP+BT|mkY#I
z>D$v#S|&|f57)}2`IX>RNH5V&;hOZfahSL+O)Q3q8`9Tjf>cT4WZ+dxuTy!_P3Z?O
zL!?Gpp~84?Njdvrp;o$!##twIpm@w}oAib=Cisq2K{>Cx((fsrSudSOz<W~tY<STi
z)y{$6jZ$aI8MjEgDI?n|-4G4QHtC8*=xmox9s>Nn^pYo(c1ZuBM{TFHh#nnX(l&Z#
zbW2-2;98F~_Y(~Jf%MB|5b2fLbV4-yq=)IyZ@*MQMa~1#`}d$`P`Zq&IftZIW<$+G
z=?WG)ho%2p0pN)ASQG%G(rGG17?U>8XLcS*Ti*e1T-rr3j0x$pW+<DK4myHNN#~ct
z&|_&g)!9u;=a9elGJD$u=t0?i%EcU#71DC#u<ZUM5JzNR(4y$5EOjB29+NFg0nb5J
zKrtIfS!5GLj?2<04d5hWzY0lbnQ<dbxX7ZZ7WIVeyHbd_$~Mv|BsbZ`T8NyKH7o+)
zlq`s%Sf^#{W9j~LmodXYJY+X6gLukr(7NAC=9Yo+ddr3*Ff<>T({7memF<{<Hb2=@
z^l0&yy-nGV0NIvs@B(E@I;V9;#-<X&AlZ+UH4T<srHFWlOh&=GP}z7jB*SEL2Y?Hg
z?R-GB1QD`II$<6uTSPmXv$A1dsELv-{tSp{Sq8mIV`M+F;eM>lLVNRbvN#_ojgxU7
zVifVRpk%ZXWZ}UeiL$^1=uVQwX2Q~WnIA=}l4U#TZcLF4P%`m?Y{xXTq{?#Mr#M5J
zEH@kDO_#me0cM8Gj*12|WzXG(OqOgDB{MF{?wDczlI;Gcki0C5@PM{#S(Fuk9GT`I
zBy(llz3@Iywu-LR0$KeDI8!LwNk;>VWL%2Q6wCf+0H8$X=?Pw`%z6zx+f`YNJ(y*(
zg?GR#mvI8XtdO0frQJ2z2;DN3vP9agU6&0ULFWzGa}^*}vI%$Ks%0-xCibRme=c0B
zk#!Hk{4JULIRI*9nm)K)C;OK^pLSd3GX~xrS^Eco-<4@-PhM}6Ie!M`J=u%2Xl{_r
z&jGMeHb((xnq=|wptM=mLc6FI+289R*(zJt2M^n1KLlZd+htXBJKUFPSHg=9S?m-<
zI%Nk=L!?XQMWKjp**OZ7^~h@fyYXZW4iM>;-S2=GeKK22K4`z}O{&iwkX6x@G$>1>
zNcE8HC3?L-ltn)YZNoD2w`h&X+^IfkR8~(F(_=CzRd+m+WlzE1aan#ZlugLwR!C0D
zHaf$nDcP&Erg|)U=@salmVM3z&R+f;Wp)nA(`~f(JS30kfm4U&o9N4ZN90%S(K;%x
zvjTWb{ylAc9psIFViFwXZuGK0E^nsvu9H0B8akcjeXBrR<eOdu{Dj;&3m&@4|Dhu{
zZt_nzqVuF&^F8dIl9%iO@3cH<35dJ=^$7}NdC2vP!1R*OzlqU%%j>B$$4CAr-CVx%
z$xoo$PtLpu;x8Xtj?MtNE0tUY%47e<n9j(D>23^?Pu9ayu-rEStq}R+|Dql8p=A&W
zlRrgnhs)(3!9s-m8Cr5j%E$K69`LMum{zS(^4T)XUbH-0jA6&f)0e`hSh<mQBj@Dp
zIS`4H+vTGbFF!d5kp%g!m!Kw5ZlWYzlAK9TpY!sg?HF3J{3>P1QsilWz~BY>^!I3`
z%Kyj&E=}G;d+c=iSIBwcuWaNy=ua*)<)u^=mL)H+hv-Fl6q&drpGmu~%kl-wA(AaW
zbONm$c{2?(SH6$xqVnWHH$n2{=V!sv75U^-@UTFhN@1Nsc@@Rri{!@F04SC(`U@hZ
z@}H<a{i@t*k4{^e{7Xtim&;44fvAvgpq<V&`HV~$tdu{dgv51u<R!Fj$R)3#RVA;c
zAEsJfyd0yyDes7aqc!q-bm`rai<#in%9|#jrB2>MyYk!e8?;xxBmZ<S0C(lT`oU1W
z{9pPM+&!Co>l+w$gZvD|%^KxfHo><h`Nk)qty%7M3&0ln=9wU^^11JW*CzL-ol3jB
zjS}wn<<Cq)TZjDpo6y!N=TkjYmpq4}XWjC^!*HfYexV%Xf&2)?yL;t3=y&at+pmR%
zez}e5hM^6}W7c3Y2IcK^tq;jp6~U*6@@F>!F)WYI1Y$()5C*%W@-0)49Fse}1KuNf
z2c_@F<sZEakqP;_edwH&ANm?zOv%671Ifqo`IjLwEr04Ze6m+uS_(%GD)e-g<A`F9
z?Y~lK#bRF=Jf`T~4&tEjr(~3)g8L50aYYHmot+ea#KB=_#g0S}7exn^B%DxuCPK?q
zae_i)ZVC(Su1_kStpGWtIPDFQ(~631m^^pIAg$^=6eDxssHY;2-ez8k1zxlV^j5q}
zg=anr4jskxReVwo89zniVwm?=oGb+iP~4_faG>JbufRK_@S!D8km6Q9c)^PAD2EoJ
zh@+Kis3K@Dl!YmxR$wl|758R>L?{+g&?izchn{w46`!pJJWApH{ZqLAq7_L(xEP~&
z_f3#k#d9ZMDPFPoO{hswY+VLKqGJ1-=uA@VC8g&TBUH7XtaxP#A}NZ0m2mrlB7#ay
zQWX_(AZdyay2{cOsiE*GLve{7ewm7r9l&KNmaGH0sIbGtBG08*MbD(m3flyFvlR=e
zATdW#O(p5Mip_Kz<|%elv2VU&#W{#vQDmRTtQ9C;io&cHD$-~VSfu!u1(9OK&_T3H
z6i;jhu2iwN3V^E$2HoLhid-E;$`#cw!9s=N3)(r`t|{L5FO;wNX*ZbH6-~6>zM<fS
z!u={mcO*Ki6^8XtdQ)+hPFvO}4DW+?OEHsTFtv&zdO6i8P848fZY%zzRM;KGN($}W
zRlHIUk$Q#8SvY!6;p_@!4T>2K05mE_D3{x$QoNH6nPx?`8NDrvL<+gKDw?RUuT8PR
z6TA+^ND4$d72PIGVwXY_4>jG2G79naD9W~jJWy=&esazeZ`;1O2HcS1T{`^nP~n{c
z-mv0e7tD_+8YyBsswkj>voS@?AJF+o@$B;u8CPWXflMd_bb5DEQAMX9rW7MoQ1n=#
z_kh`HMH|&4+AGs2iF8moIU93$NXejSKCImQ0w(5&l5L~R$5G|0H0#Hd15}{upxj>t
z-Hyt{JwO~+K0{S^PRd<Wc<HRnrMeXt<z)^=eM0#Yott%4M$$srO}U4bPCm-x9<b}H
zWIPGtr(FIEB>k0>v|kKRwr_!Jfy!R0#5<$h@;*h)gOo}1WD8cF{{gKKC6`jOp-P@B
z%!eu8rCedSGO!7V2<2v4z(p$4=v2U2Wpe^X5vANe0$#Lo!x%balzVI7Osw)LdL^Gz
zUf2#mobqD|%f>5nUVw)Q%8xz;NmPEnk4|PJDOXW(@_A)75BOxIJ1rhklpVjIbwN2u
z6>6!<skb4LrmQ&tlCEs00C0wK)dzHsC|^GY6Ise_Ct>2E@*}$8E-BN#g89qJ9j{?z
z*~%ME=*&?j(L*{{`C=RZSCo4`p~{>BWrsI<3zcVS^<1QUyd6r5l^^~Je2Ma_1K^b^
zw<w_Is`C6d;FT#~wxCs^Y@;HCYs%$qz*Q<8>G<q*<$EO{H<U-u!$g&G(<oZi%7I~w
z<)%_d)#^3Mx<HUy%Khsx7F(^dlirkd%6qijzpdOy+4(!lxKs@Lu2QrQyawe>s=;Vf
zs#GA&%7Pr=Ta*@hL$@mJA3~%}sie$%yYjdN{@zzE%z~B<WfldcJC&|hDC<&wb_cv}
z<>45()}!1^1AJgpuJVISuhL8fEPcw&wNTox^wh(*0p)lnWCoRvbOjG7%a@?_P|2W^
zH^a*7`5+@oeIm%H^2jvIk101UgKLkJB@|W~SB|s-Frl>OLFc5hib5Sz%Enbt{aD$;
z#jH&$Z6Znu98`HGfO$xDIvApdRh<;!JEpP=0nb78Loswas<zNt`nc*f3ez~LKBXwQ
zv+A7>L0nafsA|qlWt$6;ld2ECgNVE8@|Tzd57qKwh<K`u612Qj_vk0|R=HO}(ns~1
z?PW}<uS&iWCj3-S{0)QtszqPI?*P>kEf5V<z5FcjXH;7&Arho=qV!y_D(f^_A*xMO
zp%$v*)2BzmRMjg14_D>2fkdb_lwpLCDt#b$XH|3Q1s$adl0aFs>eMdqVpOk&+CXDf
zy?=q6Q%(H}ZE>o6s*#CTr9{HD1eN|(IFqOfTmv;ps)ZVKo>%Rr^lP%}vmen)QH_0v
z)&*61Cv>N(MkpbkrZUkHu5{Hv4MZ|jL0U{urfQO+?^!C(+t7JY)i;Meij}Q;jY5h!
zs-I}#n5#0q2J?BUS2uy=tHd8d_Z8J>B3cD1T{@H&s#b--(IS-t6*U*DcI7~%M8%DU
zrBc<8w9L4w+NT34Q`O%ADOYXh0$!m~()qb-swXL6U8%BLK^cYXs`Y9N?S{(h2k5R+
zX|tfTTJ`IG%-2oT!w>*#RFBS}Ri{d$%EjBN$aN68qpGLn&0W<6s(`6iJwuPXd#Wia
z2WwFAZoovNs+7(aG^xy^7+|YPI|ClJsfOraa=U7?3q)*vs*$&#yI+;{B*=g&WhU?s
zRi`M$I;=W37cwKNu65vzs;<_+(wOR12Gl%KG3TQ-srpzAyHl!pw4iyc@}{93R3H8u
z!#<>TS^zDF)uEIiKBAua5ag(O^A;#OrcNRcPukQ!(6P`{>Q{4cADvde^DfN0tJCPf
zk%#){i?HOWet8#oUh1c*62)7+jiL)a>Mv<#ebw8afux_>5&)jR+MRZ`0qPkPR0&k~
z)T8r^I*g_=Sp6Mc7a{5~I#?B|o<VuqFtsh7iW0)rU$&wdq5g`VH&N=^(*Q=RcU=N6
zMlGPIa;*ApD;zziev-mQaq51mIgD3_7h+5a>eD3<NmTPL0Fb0!BLV!p`auwQ$?D;G
zXr-u~S3~52x|hO<scP4Mz)MrVVrzs`>FTa^u$!emFNEl2^)pmekgZ<586-y?IfY5g
zRj>OKtvq#C8-V%hLCT_DQGcceuR#6W2T)q5K0XY1k=k(pjuxwnPQuX=^$jYCC{@2g
zOWUhz$32+JGWDL%0Vr4Vj@lqop?;1wLf6#KZUVkiU137&y83oCcsJCMKLdYL9Ulr(
zul|u1*!R?1W@GdX>J?&WYgB6wU}#P1D_MXyt7kQ%)vDh59e8c(x9T9-uI^d`gZI^D
z3TJevBi;k)R38!2`>#v=1}!(b)%>GCJWzi|(f?jG`#2o#Q&+m8)vx|M7_9-d{5;GL
zs=uRz_K<pQ8I(R$&-oXw4Xe{!(Hc=dLCft?b;1tJ%p>(dy5q*x-9ykaq5kX-@FvxJ
zsO)Y^eS}5Pl*j7r2cUaeo&Fbyz2@|OFb`^8r|85X%|iq5hcyrP0(eBTfTruHrs+Ps
zIHp<I1*Hy}7k0yYM@=?eWydwEd?D$i+5R+$tL6YzpPtlI4@31Sjo}##@U+Hd8+h)T
z6nk{qJTw9dH+yQvvmolDd6AMdzMAV4RPocCVnMgR=1IzA1ZY0V1Tau@SpafI<3_Q~
zAkE8kQwD1^E1)G*Bc{k~n5M5ABH@}%{!kX73ET*Hq~@0uFn?B)Jqfp?G#<3Fj<#ub
zhC@w^=G;E0iPfaO4#YXliYK8aPQ#{C1qqt-^rT4CuxNslG%s&}n)4bBea0bK<4N10
z3!3BxC{5MmSHg=l&EJ_&macJ3gGh#EPYiIGn&cL=vNYjj?~>*dN*`U;*lym%v}J4l
z7NIvs^YO<}ldG9r58v`MIkYm**BI!SNU>(wJD7_S&BX%nN;Qip*LhWwK~aq|jr0ld
zDm01o+P|h5Zvd}S^Vco#sx-$1fLCkssV3;ACb<*58qE;xv2JN**a`rw)10MH=WR_I
z?cMKa_zbAIr?Gz>yavr(GX~SBd373gn>4c$p{7}rnF~OR=E)@hv}zQ4Ala@N^?~Gl
z%@gxrutVct4PK|_It5j_G)HOC-mS4^f%IrTpbO%Gre`NzP`#SXlz$q~q*0P}Q1cb-
zP=_=hs-Whf=8p}~J*>Ii3f_q3nZ>}5Y2KTL$Ro|)RGToa`SERtOlanbF~O6XCEq~z
zw8lRVlJ;83Qjmk%2@3Qa(l!d<{b6l1#ifsElRYS-cTD@^e8@OxjlLj`T2n7Xk859|
zQ%p`;O(aB5Xmh&ZsH=8UGEBH>-;=`pNv$jkBB!+9+JT(be$)=QyEdN^Wggnm8xZl<
zCd8oAN4t{B_k6WQ^xOMsO%#Ce*T%g__g|nk&JBn&+Rt)8g0yzNAR*e$c^Ge~*6BKC
zCQSRwar|82+Wnuye1!JKO{j^~`n>^Ol$J&3hN87EJOzU>+OCh$8LR#7G(^s62i5@>
zr_G_KdxAFnZFrHW?Weqcl6HU=mA3QR&#6)`S^Fu?SE|-^D`q`STV#TobnWgHnBWYp
zm_#zQCJLHmY1_%}MeVI1cz8*Bj*>T*wGX4<cDD9C3KHgM1tV}KSNkPJqVu$eXw{Lg
z?Wbb!E7~hbFjSxoT?byFO&eeb6Ghr&stqd9)?I<$rP?C;MXzeJ-iN1UT4&lPmuq*Q
zfJlYb6awBg?ILI3E45Bk<#k>A6CF9dq1|>4=Bu>16ojqTI&J~rrdCEv@*3^el%%?)
z?WFH9*J>}y;7py?)<zq#+uFBRLCqa)D-Y)HYFFBU)N8jiL#9FdF@-7{wLz56Y|?tZ
z0$#J$i;^fU+E*WAXs!5}F#0xa=%?VdYqwJ9;J)_CCxCZouZ%)<r?!IL6<yjKN<VaK
z6VCw9qkZw`P7LjV_IxRNd$nJ^2-2rLO`(H+t$=cLgW7AY01j!tqnFG>?K(YpquOBF
zYmI5w7l1s{`p1HdYuWS~oY02S<9SlM_$#<QrS+yT=3{NYcmK;zykx60!`>lXbr3`j
z>z=1O?TAiikLfz9d*W$y9@E8B;e&(jKrHMz>PnozJFXl03jR9jf`&0_XI%i5$-C&X
zENGq3Rb>I^s;i_hqMJ@ZTcwk_#`od;DP5)>PMp@wqL+iaZmUfPXFPN#qu{8g?$b83
zymUX)M-sesd+Epa(RI@)1YcbvWqAE`F?71jUsqcUK!9$Z23`c};-}%$8J&(cgF(9Q
zyCD*+`(O|xOczZ>eBrt_iZn*(auz@`QYWJr&{<vOJCr<$(v8uxC|Y;(U62^v*{5MX
zR`>KhwBmF+U$o+Nizx!0pqud>@X5M$?y#Gp3*U;tT+qc+)-qLRKZp^g=_+?)Xz99T
zW#DD#j1;ZP)N%iTvMgOB9k{uu8*7E+C7qH@MVgm&Gd_c-*}9%RVCLvVeqiS6O6ggW
zr}Lm)O1{pz3wE#Qo?Qb{pxao8F%{|@2~ec_fsTL_>*muXQ=%KE+n`kEONX<s>LTcp
zE7SdR9wOzshH?NZbZ!5As!KProPxKNx?c>Kw(Gj6F(7W}d_F^~N_UE8uUdDWGLtuT
zL$o%n(fwu*a!dCGZT)L?-IcIZr~90Vf!@~b^+)TDE|H2#@9Jh6G3<JsFI~U)bhuA(
z-{@YYeRZR5Y8`k@x_HWH+M0Ezsj#?3XQjf^R-Kh1CT%+XOvtqB{GJ8yzAkP9Iy-b1
z)6weGRl32^E?pSKkh*mrzX{16-5RP^e4zWo6XWgGvFNSPr+a!S4EF1W9-uX#t13ln
zP<Mh}F+;j#^ul^*)2(iS!^677c_1UYwX{_m)g7Q+<hX7fmA6djR{R0ole!k#xJ~Ka
z@P>)UIsw(iOzVahLaDtz#1Wkb_4_Fydr1FiAv`>+=h7SYi2f8kpN{HR_X2)QzhMj9
zcF-pugruY1wu91+$Mw~8VL0i(euS2@zT^fFF8b|a=suzMp{vDJKk*X~Zu+(KmDH2^
z(ElQ&dUuM4pVklL!Wnn{@|`f~q4x~K2tD-$lr;6y|4MHYZ@qyobszm4s-^PPSJQjT
zPruBz7&3wS-BcG7tY1at6CwJ33NVH0_r^hYn0}0&9^v{PS_?<$!zs2BsozgeyR&)`
zRo6u66&)}Ut+%6ea*RH18??mgU8L~$oc>u#=Edp9W5J8p%b$Xy3HplykVJh*DIJ|j
z(k~l_=y|=E0hwfdDs3NA^xK8#yr36QXf#!?eFmLr`gup;TDo4%L}!Nn*IL-k)c^1m
zI<xc_H~?JKe^3jbF6qAsg@>2*g|7mat>06E&K!L`#iMieqw~<2ryq5vgJAjkrwhTn
zqF>5GZ-M?)Ig}Ra=PZKXMf&}3!_#8DU=>74^zwIsFV*ksfTLISZ@iCzmg$)?h?MI+
zya1@s*Q8*cujx+<K`Qlkjd1O{p0^S38+y-O095G@YoMiCe|8ZCZ*S^*=<cY|d(ry-
zmR`jNuvTw-5+>^OYy5$~t<PD9@!rud{}#MP{Tq*Asada}kW!0&(Gl=k^>^tuYSX_>
z$06GFM`pmpef@S?26pH}q!?MJe$gZFy7Uu5NcQV}Vxh%0sNY9d{*e9v1;QWdZ&Lnj
zRA1$QF^%a<DC+x2A5JTZaee+bFh8OHzy^^?{gPg^rt~Y^!F#NKya8lducc?Uy}^m5
z<e=dnIa-GdB@~=EY?!9C!x6)!CJgDQ;eIl_IA$~SSAaSgvZxxx(eT%kaQL_(lC~F4
zhS%T6(3}llP;%MDP@;r0Ck)pp@8D`!I|6NPhL2}M_esMKpP=)U;oUnRrww!If^au%
zqy(^sVW141o`#oc1LS2;%))TJ4PS`?_c7SMT?-Sw26YRFpW!JQn!jN!C9VSuspnuY
z(4d|K;*5cJ6PAJux_$tI4Z%hz4Kcj42PD)`_%k}g44NJo3^%-_Mk~UwD;hHzX}C}f
z_*sK;COV@GM+8tEZTN~x!($8=Y+r)L8d~N9c+L<>hb!U?%s1goyrGfq?F7TGpTMU?
zL%ciiNroRjMCW<K*R<kGHi$37e2O9d9C#NDqSfG~8h*I|UYcQ&maXZAIVO0KVHnRq
zE7NfFOH4wRp@ssxmkkws3ioCkc)x?0V|bPWHMxcgCJ=dsfnykbzTr0~h+Hu|cOIiJ
zF!=ujkwU}jgBV4T;qMrT6dS%;h|Utjx)F$!8oW2di>rn!T8ymB5KGne<%Y~uSg0_p
zT?l`#8Tyw1UTOGc;j_5^t{c961_o~!R{jd#sti|s(W*9VUJArbLoHQp)fjGGgqmB1
zZ>ad7)-bMv!8$|bG4O61)ZS2f$FLwD=I<I#HbJD`Q2zsX_Y6q}%teENPsQ_%h6_rF
zG#RpPf!AzEM!Lf`tHrQ66$V=k>*>{T->~Ns_|{?IQUOS(q49a}x(p{NPTXziq>W6E
zA&63v4-9MXLTRs|ohG=?a5@ij(Qj}oLu<hB^&Yea4RLgkV94-0)xtb9Xee|&Y?z?H
z#fV|56%%9|HLMPYnlZzdPeSyOVKaF;ZWy81^Mv864<I^eSRD_gQ-%e!jeBgkD}v;-
zVF@jQ?TxRGL(M^BVgNc18SlLUk;BG4^f{3u#<FLj?5HuO8(NMTZ~P4}9E<_~qSMjX
z5D#+PW_0@omYj@5lp}C9enRnD7vns-E>0MKEQDQG<1Z`Fax-$eVeq7J;~0RajO+G;
zoHo8faT|9di)!>djQs=nVLXjSK5$+}`4D{aF<K~H;%oGO7b1Sf7p36&8wY5E8DO-X
zNdpZu9-~+E8DsrsFoTR!5kLeR$0<u2V$8dW&QRk<N(zJ-2cpp#ZrnrRu?XX%5EzU!
zj&1@uYYeAvLPQx|BoK)<J{JHj=ZxHsVK>fr*$al^jT`;oZ-Q~>3lK>(erub6(j?=)
z40w9p=>8*G$;OX7Ad_O;N6+3g<Jd_6(~W69n4k<}aVaD(8h6t!@{;i`RcT)~wox)Z
z+c^C+S~<r1-=mdlO!yb@JYy}zV)KnVGQhiHeD?|93XC~)bf?hR`3)t`ij2cf7)-Iz
zO3(EY<DYLrwA4842fJ5|52&W4%=lat?3Noh(TcvpC{IG`n(+hr+*+k^>yuD=-MF0I
ztv8G&idIz_=Te-u+W4Rst((TTzJP@qV;-f!ZW(<jU|DO-*+#`Xbw=S2Xx=v72!_lZ
z<BWGf?i!E(0@vz|FH;%HJ>zEDmNXbI&~C2Lc$q2}n~ZDuAk9X%Lr~gc{DD%Et;TzF
zR-w&!ZU+GE#`doPzi+%XfzA%&Ju0Q^G_Iv_b{Ri<i~a|>+c;JZH9f}uZz1!*=u2OU
z=r#WG7_C0zF512J8_Reg1IBOZ2{UNiwid%4GVXf~k`IlQ|6(qNjSuMsGGa`lOwy>a
zWi#xK87DNrJu>d3sNlHqpU*L}31hnfyh&pVU8J@tqmojKkBu@4yG|SJsdU2Lbh824
z4x8!<0X$*~3jsN5%Ax?oF_VV|k`AV8EVLX=uQkGp<0d;w(>R&lO2u?Ln;hsl=VJ1r
z<5MS0`E*mcnqKQi%gvNQi>#BTj4o(7Wiv4jLG-jKoRZA$rk?|$)Wfvz6{ztvwNv2I
z%j8H)K5x@|FTjM4NlIx)Uz5-YEkBct;ywPR@%`uwFcm%pT%hU6cxX9es-x1fAd{yE
zBEhDIlvfQgrG5jEP}35sBnmUxDt?0baMPL?Fe6M2ZBQC%dPIlb&YDtaDHCPljsX#E
z`r!b0=S&-20f;lL`4Tf5Z<<5Vy#!OzQOseY$+#MhCYjP-zzENq5<SpLHf_p5E5%g&
z91NzK<W%~QW*VnAPP)lxTL)l<={Oa?W|~@RVdA3cDJs3VWSU9=;<D+-e3;KRjab3U
zF$GcnI@ffGR+U#w-)@9RfhjfxN()VyG0;+ET67$(V$+OG0F;>g-vB8!H7$YLS51+W
zo-H%=eT|Won*!bGkZpy@_9_fsGtH(aRHbQ%?t|;5y<;$O!_?Ree3j`Ig;uLg=kkER
zX^LA3$r_XY%W&<M=_krl)|%3&5Vy|cGX@WDo5b%y<c{gYT3EPi+MNt#^`;6jc=t>V
zRJqt-dVciD=WsijBEExfO{OmI-&SBp{;of?b(lm{m(*!uW&_b>`rk^J?>0Sf0kFrk
zlk$xZOiwLBtJf4oWoLb+h0`GYriHX$9Weby9~>Jr<<~;luxUO$Wk*cSboOA>bdB!R
zG1HyJfIl*=rcsZZ7W|4|V!|}nX2j?xO>R^UGG$_a1mI)Sy&Z6W+BA>yEcWIn>p>2g
z&-@P_9yb4W1%M;w$cGR)YUb<!;F$U6eK6r*?sbBRljceR$SLzWs&hMS?xd=6ce6Sg
z20hGu=`inUZhRg(eaw^R=!xiSUfKe@pLx?x==L|y9{@AJoS}tipgD&!lV{93<DoRj
zoJ!}lg3YOvS`0DYrMG{m*}es>F!N*{w1k^~rxOJcX6}7-Mw)#n6_aTGo4$ITWd42}
zQ<-d@tjAbV%=>?%1lR@hOxiuCn!{d(r8IN)OptVQ;xg#YFyDI)N;Azl?HEOtxhoHn
z7tNb@L*$a#nF?htn_pu>B-?x&@w{0%<`gR2$~AjY^fk}Sq6JO9c`NNQu9%xH!kGf|
zhzC>`ny+rBPg56}-6;ZIY~DzAOU$#P!7MfZb_DpV=IcS=m6`V+fZcL)`+VrGFkhmC
z?ltqwF?3d%^BbV_x_RbYn7Cp7ABDH8%<oqKS8ZOM2i{F{3+1?K%=wf&xn*{k3tp}H
zP1@ZcB2-Do`fi(N_CoZI*^@TP_snb^bT^pSTtjE0`SY(J(qvxZg-L8ScN~XnE#{x+
zg0z}%q@lCTJoXp7Z#Vz+7dr2oCvBLS4)X{t(mKtrP+q9Z9K{0ZHrutJv&Zad57iHB
z=KXRQ>^1)s0fT+!D?_l<Z}z>4)_{4#OBm>&`M`W!okM2!zvz5ucCQ6~*t{naxDj*D
zzZk`+dF@W{#?0Tn3NId+8=nSX+&r%g<DD@7ISYVEbHh=XpE56-f@_b>t7+3PZMJ<t
z3s-xKU^#jZS{D2cnM0O0cLRUe;`lp&M=UnVa2&PFqd@pE%UiUWb+ClHqtnUq;Z=;n
z*`jQO7cQ2ePk}pOF$DqVYDuDJy_+RuCqzzKoat=WDa*PyK~7r+==OED6xcok!o#9m
zjb2ZSx*0$(OXFTJy)6YJ;Q3hEsg%LjVliVdewKgEqto9~ummK)(nY_0pk<oYTxTr9
z%OM$L*%yk=V9U<`a@3Yj_Q8u#%gb-U-!Mxj6=8>48rlGeuxzcO-zn1aMI!8;wRqTJ
zx}z-5(SkSHl1(w87|So;LL}A_`Yt-pSz^D27jc%l5J<*b&M$_e2^LNebSGMBa$!En
z!ldlfdCN??wUaHHZ$MHk?X-KnU|GcmNws`T52!TD_1EeCOSi0VKyQX+$x>L#wA6F~
zpJi#xMeCwvDJ{}2S@ti5$YskrM$B`z#fQpkb1Z+E;7qRNITZkT7W)M-pKqz81@9G$
zC%p{|EcSF9s?hSb9Y~R-aV~~bZ25=E8%iv%2R=Jv<*ZW6L>RPPwM5hT`!dT8I&xKR
z`IDB<m6jJM_Eu$4d%yJ_9@dkez{D*}`5CCGwKNUEM4iR`d*E(cY^`YBv3ULh^LH&_
zv@@=^{6U8x?peNm0FeeuH9b8VEiP18&}3o%2`$Z*6~`diVi}+eeXC_91p?YEyFQ1q
zcFO<-YVKPimteX&EOHx_qIX&{J_n-9@_qzJx8?98M0@aS!_fy8JspGWwQNj*7k!qE
z|G;3sMe+$O4Ok>|Au?!rdjhQ?%LnwFd1#ru2KcbWD;KR1%gi9OMlBcbK=qhqH$|Br
zS-1<q8@J^DSNl3)S#uFGla|tFU}DO`qOj3pi)RfG)0W$`3$?d?Pagw3XnpAr@Q19$
zI*jS4)srfqj#(A2fH+t~Hv!;iU04p@acez=6P>IxS?D}r&8LN*t99{qIO=Bow-db6
z*88U@Tk3AT|2&!=*8QJjN<FP3;n3z~<&R-zysfV%fahl|r{hrmR_6({0<3S*^CHkX
zdjnc$tU9VT2(s>60NugXFKG)AVttlYjG@*&^aKyH&ZL_$+?x3jMiybMc^@K?)<0NO
zt#H<QpK|h1Rx!o#qpb&J5RI`;$T93#>vNS*dd?cP2&0d)p1BWvymc4dR0-C`Jm^le
z4%efVWZn5944$`c-wTp#J$M$l6l)-T$L@ml)a$s&Qmw1#Crq<`LGR6UYcs{5Y#COw
z88VqxA6lJdS?8BP^rCe&Ey*ugXVNS3vek7SI<u{-nt;f$E~Ky8<yznL0?D&7#31?B
zJ@oXrV%<y6umWq>X>=A^`NeRp$XatBoyFF03Z|A=jr0O3wQd%JT(wy}|J&wU7f|%5
z-1;w7DOFel=ytefec>uvmDc12kn7ePl*qkdEer;)%G$LJCaSHj6~NuJzMqVt)mR_;
zq4SpY8Hza8T7Rwqug<z=EvE9ebq!sCcdTz#z?r*NJ>BT_R@<Kk;CG|dLKSLFRy|dB
zG+TW?2C&7NLBZ!%YxybMD{a;_mB6=Kjk7Tq_pKZ0r|7WGCEcCYlUJdo%i2vJp6Isr
z(GsS|YQG4|9$4ddKv}O<846{6)@xqq?6-bQ0mK38Oq(3u3|c?R02#7gSqj|`t$)y`
zuZFD}sz?~I$|wytYVD)<(3tfnT4z79dOL%RTW3&gbHe)K1K=jD8MTm{vaY1v*kh~9
zG4Q6X8z+FXx4SnBJ{`0hnGJsr*>zCH?66&1EQPX<*fr8*9JMQJhuvd#Oxg=O*bUu*
zHb=X~QLuE}ZuW8@ob2``f#+-|rTB}BT^<F-PT1Y05SXi-Pbf^d+0CR(_er}AbO`j6
z9V-y6({{IBfgyLhbC&_|u)Dh(#M5rmIAu${?4q(E>TUNK)!h2nJw=HjU%OMZBk;4^
zG6CXmSMeB#0K4mS0yog^m$zW>jNRErw1VuOX2F?YJJkhrhS)t33T2^oW!}&dX4jkt
zkx08T3SgYIOQ+3xl-+Gw=EvH-iW}WF>zv&ekAaV~3!-P>|2ewuxGbwL-ZC4SE3=<j
zT3TkMmRgpTmT78QX1#mwz2CQK_JV?dAhJ<G1rz}X8wUc)l8uOh$WYlb1wlas`F&4+
zozK1Ze9t-eKF@o{Ip;oaBI5^I%##?|<QGV0M3DD4g|U?mlc@|TO=)S2tjjRw9Aj}O
zM&>-D{U?;t8AmCp>jGmtZSyl2X&kg=G74$Om&K@~gp-Smi2u@R83$;3&1QJ5gCb`R
zBaZTya~Y+SWt+#CPH~=m#v&PbE;C~4&{n|El4rM&@%i6qD`L!QgY06)*ahHA7=!<1
z5HhkUNLI$kdL5*kv62?}D-7PZ7`zI`)gJWzDuYk{$4bW9=U~h=MwtdI*PV>%^qIvf
z#x8Q2RWnYK7v~0pNf**<7_x_`yvf-AF%Y$kAFiUUj)5=v;|Ij>$^x!|af$-Sw;1aw
zxAHb)W-{9DFcus`TQg&F1gvjil+$9^%2@L@WVSKVe*kG`Yz&3<cNxx&bOP#Nq_9xi
z$@r4opk0io+F@xoV=GNtJ&Y~8KzbRWkI?OVjDLOrppOw>1k?H%1^&=`pOK-0rUAy(
zwcs3NJWt2n2MhtVJ!E`NZ|4x>DF<W@GdzWWKVm!^49*e8+s+s?K4vVXyFsIj)qM~%
z#wh#|vY#;8C&O-6=B7rl?qtSQgY068DQj*wbL0*>>cJeMTb!QEwj%&|F+cwVviC4$
z6ruNK9=;FtKFnumC$pECK_7wlWv-tDvXA*!A1eKrZ%uT9$Ddg|33>yV8%%i2fy@{F
zgiS$A<9uieX3nSpYX~#Z6_ugPhxE~_{mkcR3O~SH%m6va{I(ei4>3D`g!;qGv!0N7
zgt^Tfnj)AdjbMpn{z6WbD5m8l^z$gQk&b`Im^0Y)`-^5;PlD$-lk*OG7{iRNgfX$q
z!Ltw($Nc9*RGwh!-vj<6^PK>YQ_L3Hc%Ei57l9?7`Qj-EO<>|Dg5M8w%U7^4iTR8P
zBa_VB`UIRQ%%5qyp31!H0+uvpO*C+4m=iH2;qDc4A|3qBF{d3y?RjRo7Wj0gggodM
zn6VV>%3w}?7J4(8^Mk;W#e7^1doMD#QE=@Nvxhv&+01YsROT>QG;QQEn-q|e$DGoS
zj^;DxB!KfWGk6^o6)-=~M5&M&N0Dx45pzX7WEV5v-;BmGW;J<@E10QS5PFsQ(ibqe
zlKC3#d#^Ez={E9p=F;z=qKesIL1i^_E#-aQVBVdH${OaKR+xR0`RqEh)iX!v7uUf2
zmokZNF;ggbdYgIvbyVJAYDS>G(aDUXjOQk1*$?1pW?th!ObgR<2oJB7xruHp-(_B>
z<*0-C6>aM}ne*r|_b|Vt1h-!13P0F;kGaep((W^VA_x2cbN+0QL8i+$U>Rca6Crb$
zSvna~9x>;2!NO4{qX2DVOlJo<ik>iYG|=SAT25av*vTq!hcUZY&Glg2%@SP2SbDIA
z|HS}#vOK*|@@B={gE2m=g}1@EmzD4m6#B7hXgBH4`f5592CybPL|ZVc{WWlgu$E1Q
z=up-=nrsiUR%p={#`@dY32EW1Tna%QVdb1fZ3Js2y*rVt1si}k#`@qVl%iQH#vuDR
z>rZl##<6^^!I%>)r4ZyKi$}?}@vKz32a~|+r4LagvhI1Jl)_4}0+-5~M-zD(>*e_X
zoMY8ZMB8~*=2D7jrnCBb==EZ)|L^e4l2gj#Mb`7-FeZoPkqX(ltPV=`%46kFkgR}p
ziah9rteN33rihjB-_-_|b^)YRvHqoqPBrTXn&oe>7<6W-VSP`hqMNM8<QT4JE&2s&
z8(7OG)7_6-tR-GR+-Aur7;=Y|v;^uKS^uL{*e2Fpa>F#U{-8}n3#%#(_*PchA5h=M
zTD1$McGlGufOoK5icsogoi>59i}l)9(A&-W)ef0Gtizt@_C40dDd<EW>o-c-=x6<&
zMb3iztb*G>46tVDP&>$4GzY*TmR1Zh%u@70=p)uNI$4jhN>ac%#u5sk@Cj?lT=c?)
zZM_1VD?9XE*tC;vr?AN`cG4GUb7NnoNa1dFD%}_IVE;<%yeIqFr668xMJj|j_pr0S
z1kjtkmX5DJ>=pY#_Oe6f1Mka@qLjydZ2dkEKeqc)SmDpMehQWVw$B$38ps|bFI^BD
z;WxZ&?D2Y-7Q&tu551x6b7GMF?9p9-A7Be-pzR=gjypIHv2*C1IqYP6T!s20>=X)k
zM6r+EgNmc<k;woaW6yX8md3D!-$7F>`|}{+<Jh0+A?+0VhkIx{&3^bUdLPer`vg*w
z*a_dm>}2**+P<c+cT*hg3_H9AxU=lSZy@Cy`+1suF0coZ(U!q>1|0z+ll@OIcrLM*
zlP4~l-A}HP9JYoW5&7)x<j=dz_MqQ=0lT{poQ3SCuE2^S_P{HsEM`l!Fs6iEW`wX(
zwm<#E%h;@NXewuaL^o!xus{43!YbITUtvWhJ6eghYiyR&7iL^%r&8#uie3EzNHsf<
z0oEJrJQaX7?6o_=TFbt15LVQ&%bx<io}KV3tY~0wqzK6^b~1VJZnKl=sCI|VSq=4#
z?1t4arity62o25b-)N#}VXvU>wz3!dfZS#8n?t|94tCrxP|?YLn=VWDu(OQN+sod6
z6Qz6XvjZS~>?9#%_p_tk1-Z{QQwq`md%-)v4YEIY2rC}28`h!nAv<~o07LAH%Rz?O
zc1k3C#BQ;mOC#);)F?e>hfpYWlzn-O!WU!g!^dF$6Si(U$T(X|Njxr`*#h*!l@nPD
zvXe8PGHG{lHoS~BH_k*lO1N{{DY;}f$Mr?Dd2o7PflyD5nVydq=L8RA59h+y;PmFq
z^oJB5PJ|U!?B(pD2)!>S57$zh6ZUbQq4~;>bEpuu`E#t3Kms_6=~NfUskn*$262)y
zfC%QSS_~4xxqBR9LOBcyChq6Vq0q<y&cPWNgoB*YSm+JoTqN&aIA^s3fJ2<VP>jrB
zP7;OKk8oJ@yN%#{P2Uo6Msf~rLNB5?lN}Ixl=D0tZI5y8CZQC~X^lbYIHz6<6)~Kb
z-iC@;PB%H?<2ajsz=J)(iDyFLNzT0~s654a<0dLkbHqy^JD#(X?o1|dA}Px+k+YiC
z`6P~QF{C7O1hjypI5~I5VQDJo%5I1`%lUK<`gD%t`Wwi3j*#;4(>Zf#(!IcWGacq<
zaF&yynViPwAv=rn5pB{ga!mBYyTn;>37pxSfBuENIh^qn$js&3rlWKoC-yn8<a6Fn
zgOtmhntOm3aGV*G*i^{*hP*&UoX3yRSj=gn?4J@&0xblkoIAgOwT!bN8Kj((SBA<f
zoPI9!R&eU+=JZvLrxSomPMa^(U*nW)Lf5Wy#>i(-#aT^RPSu<nbl$zedF2t>YB=lY
zy|~E<aMD24a%Ryz(mKwfAxNv|bWrTKfy4KLO?NoAj9_WxR4)Td6Xz$o_TJ1nO9?M6
zoY4JH(aJeQvH3Pm^ALo#bG*qfcb9X1BHB7QGk1ZrlQZKWD!Vv?^m2D|YBz$jhoc{I
z0@%wLB?r|#&SE=CeVmO;VMRZu&<(8jIX*wb?g7r5p%6332~0rmA8^$EFzq3y&lP|n
zj`|iX9Om>>63-*fQxq;8;UrT=>tjxU1|vGk*~b8Gj1%`cWIo}%`6kFX=hIW<taIT$
zMGw!F+qVx!?c@&8L3tNfw*?3{?v!zq+`0QHhhaBY+K66wa63w2lP7m4MI5}i!8C{M
z;TB5(_vY@%2f&B>_$&Z>xeo%M$(Q?kE3DYZ^<0fgKW_aG=&nC^ypzKB0o*4Y;0fe@
zyas&=;+{ASo?!0NA3<mcm$wRSp<F*Y@9yWepMs$WxIa*y&_S*z4;F@T>nM95ocp;4
zR2<@_Q1ZfI?#J-$OgO?__%}EsxMh^D9m(ZT5G0C=@EU$;TpyaQoX5D@r$D2*5#CU7
zoa@#LX))a8FGI`;?jrKmo#d`tj>=P9A$>GIf&1(8=yoF4x&-znakFTvc#gX+5-b<E
zC*FXR46c<TE1BHdiy&Ft20BSx<Z|YKT;eWT2$|X3*OEYToZK(za%nENxD-P3xw2xE
zE^{{)!^8saKc|5&<SraTTM_pOdD)A(J2#<J%H8q+oMqhQPV}&xJ1ZaRuW*mk{g4Xo
zDLPeM<({P2YbAFr1v9R38LsH(b?ziO!BlboTn7!+T&Hj+5I4Ai6zi_x&ZBS1+~m%g
z3Td_6sorR-<Gw+^zj|&_9?Wmx`cm5VE$+X)DBb3k&}(^zdn*b;8@cPq>D<J1r96XX
zuJv=kTewlDp{bR7jJ8f~+=iVfwR3Hez}@AxIK9By!Tswe6uY^HC|ugZT^bG6Uan^~
z$UQFmC`{|)ew+en{oH>?QM%97kh^(+8!`&OAoum<c(4z+XRe^~A@`|Yz%s=BXd-MH
z=1%$urAOR%C_Xg8J+T;r@R&P^f>onjbC(mfW8739XnMk}aR(XaUfqU97hW5=hIaAp
zQ;5Tj_mvVV+<DdC0I-|4?IpB%@ZN2N3Qyj8a%g+;HctTO9$ptE!Fls47C@5^Z_;)M
z+sj+>9EdO4fZNAAM!{1*-ll$9|NMEM&jdbzx8(tVfxLqpkRaag-#~USFUt&}A-sw7
z;|S%cD8#;>xA{{54)D6jJ#dh><G-6iJpIRL3+GMngr-A02|4K_c$+DwEt2<@4sB7q
z?QIYi&3pR~kmJ1UuPJ>rhIcj|Px}P#(-`oa<fRG#JjL687qSz0-0P@J<c-rcgd`q+
zKl+r)YxV>njn_x}<ug3RAQYbC1w9W<=XsWw0Z-=@{{$5mc<FRZ$l#688<@qLN!Jf9
z@_J9Abct6*d8!L@czxt!$>nW*4?^>JqvS5j=fzMO%w=9HJ+4CDSVidRwNKA>e)A4^
z%6V0^$-Kh*Z8HQ^@a(r>TP3f8F2r2p&8L9lb)H8JfK|MAC=y)FJ46oO8@#ABsI29=
zP>xC+?-I?n^}NsMbk)H7>M9i8;<?dj<u>nV7yx&8ow%Jnp^+zl6`g6~B{^yG?&KM0
zm)6CLC;;i^@dqKMhqt2*z+T>ObO`U`9isSDKW}IbO80sBNf?De-f};{hj_{zXdC9W
z&@%jpcbh!RBfN8G(Ds;@LP=Vqyq}N5&@o=i7)nogo|FbU&a<y1XN3!YB5m|t`F_)Y
z*va4iGfKPpRkR*?@Na&JN>6?$y%Apg!U5p-@Q+GhzBfOULX<xI8{N>mm*2S&IA6Yq
zlKcbtOWy<u;$MFqoWcAplpY_#pGnE`q5K6mAag(8m`@+XJixz<Q_F;d{4Xh98pgNN
z88L$IPG0&*{?{LaMDf4A0KG@~&9ufI<9}BS+0pzw+VLLepR0q47=FDRB$glCh_0RH
zznu$v<N0SOOq9TX<0U9e<e&Zm>XZ0N6O2jb>q6*H4^#M)3jj>zPi}<JH2z=X5PFW!
ze-7k4zn^@6>HHnZXuH5qUkWi9{O&~%lgZz;5tUi|+Fjth$e$4jg_rm*+y)?<Uqx9D
zIsA9uKwB<<`U6xJ@`uP5T*SZh3*g24>KK^jEa7jbwB}NNvK-RN_#0^!D(5pP(clXI
z_X!YM!H+0{v?~6^`H)u4_qc+}8~iMCrPc7mo<V<a@?W?Mp|$)%N_MQ{TPfgJ&(F<+
ziUvN10%1-3VLFvH^Mw~7tc7o*3m&abzE2@&8~^$bAnpA28?fRof1&`SgRi3Kcqjjd
z2atA;FQCdkzAHs4`}viKi%q!Cf1O-$1N;*YVD=z?*GB+6;BTW8{D=Ib^FfCA345S$
zgun0wlpgc1$HAsi{(Ij8FvfR&`Z1(E;pe>ro^gI-KBTz__~e~*6-539o}Gf76pz~_
z_>2$PZh~3cLEHuJQ2Nat!K|Ywc?($e!1)M1q|@YH!D|6%^A)V`hQfV<<Et@1euCG0
zV6VR*sTN}qAPD&s`a%Ud=P7i1zu;e*s16AJIu2<E1^R<Pgb4yE9Xnj0C%@AnK_l({
z4-0y?K*bTkrd8<0F~JDEdeMSWdi9PA(&*KT5$s`u#0qBL0X$A{NC9#}5L^u@Ck3e-
zkW+%6Z$Vg+;764cW+V%QlrNhi`1vksQw7!JCP))VhoI?<;0Sps&I$_Xp5r-z(G#-I
z3x>&OpCNedB;c8XwOuG>2_oo{!9_t^3jmh{k}$xt1p-Qr&JhUcj$N)G|4ooQfp;dl
zn=kNPNY28`0t>m+3IzV-Z!Q&-86c)i@NX5wlnbsGV1TX&j6!It5Jb}^;;LZoY#381
z=;J}fHGwOA+^a?~g)%R13hq+?y;kt18B*#56J+457bI<fum(ZQeYD*YgnS6xZNV9Y
zKb#X<1lK9*)GAnFM{S#+H-cV7fn*`bUBMTL5ZWQ=_za{|5RwCYmmrgJY5N2Lr|~HJ
z1<%mV@xCCNK0Y-d_#ed)1_e*(vgQN9?>k||LxC&p7ls7GG;NFsB;@INEZFk_h;vkM
zpFA03f<xrPdm=cx27@pz*h)u54<Tz8RCo%dalm^Cdpe+EkFeVU;w_wC4ZM%=6(v~q
z3ZJq-udlH9COG#AJtH8~Pq>;K%>F_#rF8`ez5Vbg0)-Fh&=DjQkP|rADV%)(VnT&}
z!4SG%X!;#u4hUb_4Z9BtpEm&?CS=hoe@OT{O|yrEew3qjL^v=3oRPxAXCNj@m_*}z
zRQNG@YL5wT&?zTc81OtutdKnuqT_^%>Ag51)Y0bhq|l^;%u_-qX9sFe3!kA~TD-98
z4x}XreRKdO3QyA%o-8!d?l47|W&=qTIw*Z0O{hNtaz<FS2;{8rd<QylUN}IR%jv>V
zHQ*P7J>>Mx5KdP?bf&QTYYak`u>4C5^F?7(0c^S?jCEF_F<a<Id$t_m8^2-jbA{ip
zgtR>2!bsrrg=<<tE(^P8+A0v{<pWqK%pj*~k?;bYX^Vw($RS@MJbV)@rNV^?U?~$e
zEQa;v!slpXb46G}4)qG5gVyqE!cvM$T^EKWkt?rC7%?4<)xv0cgKr4mqZm|;(Dg<1
zqE>i|BCK`7$*t&Uy)cW8a}C1ZW&w9g$eIswTR5VI&_-b`9i5tlZ@dSVX5qF5lv;&t
z-VoL%EMlXwUC2BHW9|xBl(gF+{4AC})YK{D`=S?JLibO=(<6MB@``(f%jj<4J)xYg
zVD|~DXx``-p7;|i1H!3E5Hl#Oo(A$jIKdw*4~4%?gTf)<ik*ND3tyRvL3k{j@dj|C
z!k>Q!ZcMnQ1)NWWZ*N0sTqtv;!;*`rkX#V1q8<Om;YCAq{bH9Wt{&>$L^ZVHxr;`E
z(Tm-p&ADjv5OvQ4z*F=l{gIWI=pG*|dqmsFsp>82q=3JVsG3qZ_KI4Yf%6spMlPOx
zqDYD>`-vt6!fbz0=28%6faq%(!~}{?SYdFGD76+Uf<>GSP!S@!cmzU2MH&A?<$jS;
z1ThChi@PEFpy-WrAYr0s$?+2|`kTB#heX@H068pL=MCHuQR06)R?!<DV@M)JHFQlZ
zO5{huxuc?Ov??8QiZbYBjTW`9g{8+u9^`M15#_7~>j_cr6sR~U`hZSnr$koDHasml
z?E~5IqL0auksykF5uAx4!8&v%NwnDwQj$e^w7W|Y{W%0&s%Y{CaHfgwwxR8esFuRv
zXGQ8+0Gty!=TbcVyyz)Pxl9*TH9*=0QOF7aGep)Vh{+V~{26UoqH8*EUKE|B<IyG2
zC|$eC776JKz&Rp0WozV$93$Y&6S<R@Az$<iT~)X&>Y$vD0+Hw&uoQ~YX26Of(SpZl
zD;C{y(o|X^+D<7trJ{}Rf~QPWIv46IL_HsXTosisg87xAH7|nYnrQ!Ikn5t7@4#6l
zx}6SEEs|1X^@d1L2Te7ijxAuhDQbNJD{4hAO~FH}6ZLwctzHy71Aqq61Df)0iN<e`
zljXK(!)$csjwqkj-9}Lsee<_T<ZlF`S+s$kPm5?Ry@9QwcKX6oo2ck1aJGvUrJ}7<
zBu+!AOZ38@kliindj~8%q78pQX0OO~H%#jjMN$4(zi2AuVcr*Y(iwh0wBRA#wHp-u
z(FEBKM9-~&m?2Sb7x2TP=SP8mB#Net{1H(Kc^e*!Bx=|_DpJh>%M($K58B2>@#IT(
z5ii&SvQykjPL5q-)>kOGiE}>#&Rwka1Ltn>PCvjs#sA9$@e)r>r9WNUBW95Y#an!t
z7F8ed!j&L<#am7QzfYV)VP-$^f`w4%FFrwkBo`naeu$0+iZ{{g6(s(U{8b_1LUIv>
zia#2M`u*aUDDfp+Y+4CThs2gu02~%qQt<YOcrG0iBE<JIAk!HoK1@g4qvF+dkbO+N
z;WDH}i+`&}?~jY$E<<IEm~8?+R=kE5rxW70XiYvTem@OjPKk>L0Y5E%=>a+sFa9bF
z@I>)}iGU}G@6*OHS=^ffk|I`Y1|U_O#YdOY#QAhwKjRcX^EH6y#o=^bP8YxM6YRbq
zZmk7AL!A9KfSKa>D=1wQfA=Lib4i>+7bmjC4}V8xj(FufD9jayJ_Xr%Voo~RE{j*t
zFSS7IPru?qu`7i*ip2etwpuKH|5fNK5jQFTFB3b5=x0$bo+d}}iufBFN>|0pY1XS0
ze?+Nu*TkzSSLM36dmHdo;ucD)ydkzEgVcz(H-ht~xRFS$_&A;a>coF=p|D<Tr;Mgs
z;zOkneOr7_jkY`DHRSGU6vxuJqDlO{lhVnW#hb}V*(zT93J`7L^0|=KE)FCgT$fnB
z3czl0R4;%%;*XTDqE|fe8368yD~r(We)05lNV_jCn~KtaIQ>_ULGg?~A?1PiUlU3X
z#nVc_G9*qXKjb5^buRijB93^Ua-AQG<KF}s6~DI@wPWIAbkky7?6(98T_m4V{<W**
z^m16SQ!@8;ly*tjbW7V!^7?-{TaqmlLiUsdQeKFc#4i9Wdn6^~N${5FmxB06&d`x~
zuViaCSbQZvt^wI6dE*6I|NJE9=_7gm63+_Q79jbIX2w8C^$qksNU}K(tih6PJ5UOd
zoXm%5p_1-Sn6_V1a|?P8NH}kx@}MMvl3Bwf6J|qUxa16ZuMSD1dUWZq<iIRwI3n3Z
zA@2x@;~%s|O0>Vz?=MQCq;>bGWK9vsF^R4OvZE!v6l*^&*+JPYF_PrzP!TIxD1fv$
z$;f;ddP36tKAyoz$qu^meM-_z2_2^;HS`&>c!@i0B@!fhif1QE7PJ7DB>CTJ0Fot2
z2V|y57%Rc)OqI;r3TbC08h;?pNkTV*^}M8je%l$6Z`**+lw6@_m?fFhj#9Q{bq>ZN
zM{<r5vT`M#4#4col0RwrERbmF2vR6nLK!n9l7Xk8sZ<j3B{Y;tbhP2EkmM{w>8j*u
zG2oR>Ng~|~sFKV)4l&h|zi5%UA?f@Y_*x0a6+Cqk(R7e{$(PH(a$E9N0`PYvUoC;O
zMoAPo&zdAt24QcrWMB+dv`BW-Ca+cU+H+uOlj!H6XYCUAY)H8)iSveq9g>k0uyjeB
z>nQNiEzx|4VvpoQ^0W0y+<B08Pm)b*M!)1$`W)GP$zht=1|){3A#_lpr4zveiLMjI
zJe0g9f!-m>`i&4aEXk)({Uga1ate(|EJh5%V@Yx`WR6M(=~W+-<WltJi6qZi2G()O
zdMz4Vr0-dv!d1HX6G+=BT~`Gjcj<(EP`F!K--h0MNDsDvcuIrrLAICFU4_yfX$E}`
z%v<_XA~=1d`4$NCmFAP@a-Z}#ZN2=Y8@W*AFRgh7Z2{6}=vN#l6;Gw#UyyXP2qai~
zmVWU2rHp1Y9*}ON9nC@Mr`LfvB;E8FEQh7vuSRE%Nb8P)L`dTT&=x6W(OYs<+A{?8
z$D}3XmW-Cp{2Oh@r4K(tTa0uWt@E+c7s61AlTKWW4xW&P&nIX7N$F%dyq}WZps6WM
zx|OEsGt!uUV9Z%*HXD`aq~0Cq?|JF7-$6{eG>-C-FG$l~fu;=U({z-`l+Jz*r7Y=p
zbdb3y&7iLwT#{;oAthVdxfCQvdgKYr&Xt~%!HPWT-boZJ%a?BSg8Iu+EgL)qQYmd*
z3#A6yArwg;Ho=%;>B<ni2_@2u9;hglzR(XqnY3jyD$AvB9)pEfq@_o|Ss`6Z-_N`%
zP00agrF1)``&CI_rwov4>4w8F^oDd!4=QV=t7tB9)=7IkfT)*>Xi;vE?x2v}Eol$s
zBHfmL^E5OyNk66ZtY+ym)6ne}X>>bCt8}a%oNdy!1Aw<ngJ~@8O5cAPLOY~8azQ$!
zx+T!tCH-PGO5M`Gf}p-fx_TJ~p;!9)6O`^brTujf(<jZ}1lE434;@kOOTRk^p##!b
z2lNg~7bk$_fplvnjCm;CcnWPp(pv~MP8gQfO##az=|B;Ljz|}EfjpMJxC?EgQWb>?
z$E0NxLwX_&e-|Abmp)5_?;`tB0v1=9^ZFIoy;BxXzp-7i02&iFSuthfxXXT^pW1F&
zPYLvT$X0DYrKfBG?WDY9`75Azk8E)RRCvo~`=ZiEHscB^_sZHbAk0^0p|gj-EZqY#
z17xH0U4%f{OiK9*lC7dsez0tslePvSvXgSi4wcR725`S@gr=PXvO^}2gR;q#BNHZj
zhA!!a%f6tboI|pup8<DR_AzZdkH{<(O^lEoIRtwnWfy3nj*{)641=Sx-*drvOm_1C
zq(sZ2-T*vCcFqkp#mZPkPT=EY+ls++LKgE6fG1_=v>3$GvOP~hVZ7}2MIaJnBXoFA
zmesxk&J<Y^&1I>wFX)M;$p-8wosoT`g2J=1S1FKoPUhML+<Dm@`lYAKI<kSgAoCXj
zkReN;OJ|v~;t$DLpC$YAMX+9!Jxkv9OR}QtP@gRu4MSy)tcY@Ca%C?xp_C`%QPekI
z_C*FNFU#I^0V$BB(XwAC^P+QDkt~!_gNkM6)Zi?UJva(uN@WX@!BQq0&4q??S-d~2
zxFY)uXDoc{LG~`)8oMf+*#JbPY(DL`ugPYUm;SoUbQ5h=vI6>EK#eSgJT5n7zx?O)
zmYJpKTAi#s1C{kM|9FrFnUb7tw`7$cV7PC~2Hr*G9huL0C~TBP(50~^*|R@lxLRay
zJ%b@}w#s5C*xe@E8I8tXS=2?4d$JG;Q}xOG$+^-mJCljheOUnAAsdjrOm{j4WijL}
zdmuZS1!)guV_$#_$>!5E`AD`zgSHXbXAJ0lEb~2!%26468!E?SXUU25L^kUMh#q&!
zS}vp3RX&@JK0D?6$lbh49!=+|-EvtQG<nG1TZl?e`Jx7tyyS;oMrn_H*ESGud1xI>
z^O2X$MQN}6EWIqg@@bS!vrisO?s0$lO-lL=kk2^+mO%NcE9gX!e2AiB!E)!a)6f(m
z|Ku#hgvu)yLB#=iWd!gC<+te#4wE-gzCyTsjv96!lJnVMIU>&{7iol?e*y3)`O(c_
zIV$g>jo2~y+ofoWk;kqAJXRi0NxyM&C;2Lp<=-5Eq7*sHAGlO`zw>37ktPqMrSgot
z<Oyoe%FocmnlAsHA_o`b?~z9=L(Y5&z)bnYn^2!6w@?h}qI^&Y*_Y%|-$G%wd<7*6
z<;eY-fXkJee*_>;K3W64`SP_>04R_@c>#bz`7QDV7s+Q9IZ-T@PkSF$l*oGzfwf#N
z?m_8_d^W9y74q&AC|#95po4v-d{!TT*W{1rcynF;PAFKa<fC5!S1q4STc8{A-~WZZ
zHS+ge(21M!&Z8i;av6mv>*SZ`0bVbEd=nNn$gltRhj_Q-S3d;)wp>T2l{@mKlw;E<
z|CY`kO>#>N`r9nukG<lA7CHM4@U8NR6r*pGd(#QGUH;~D$i6Gz_$F97<Y^Q;?vz)*
z1k<|YF*I#-%RO^Z>XA!mOWrHLb_bRB<eYf&fA+~AJ_q&v@+lV}=Dz$c`R4}YAGSl&
zpnQf45D(<LI>7Q!UY(7$A-RDGX~XhravMF8ciaQZi2OY+gg%zn$nYpe<*rj;_L#iZ
z4Y()r*C_-%E}uufGZ)44=g_uOG5<9@5vRK%VJ#YWD{j)x!b7pu4jxa%2J-oNDaQVW
zv^|RJL16J#%)JVPk3wAn)AlNQYoXp((HQ_~`xK|>(x;zdmKkmSih-9v0u;UykU+(8
zazKVD%IPtMD?Zo?&O-{<wP-u+RBTBE{)pn}J~T!sgzGQ}k&0*NQAR0V97RWuDkfB;
zbW9PN17o5UZ_{q)xWY<5{}_dXVuY~@JEaE2DLQ@x%L&C>bYeTHcuX7ZQ;L>TXgjTF
z{0DmD6}^;8l%TkK4xEV!=lUm5pQLCw22IHdlP4Ne6shD1NL5t)4HMH8sWfYzQ9RQD
z{8>f#Z%}wn;rlL1=M|gD@tLj|A<hem4-9~3D5_~UnW^}gLS|WtHNy~nQSpTWoR<{*
zRjABX%%RU4=P25pbbTaO@hcq=@)Q?2;K^6C1;M7viq98=wNUZO2>M&32&UJoSYcWK
zy(Nl=lhCzN#n}}Alqp{R7JzbvZYG3XQ6y4+Mumb^4;5Dx{<J5qRIH{D-!(-OT{^q2
zm`C1;8;VN{C|F&ic#HfJHx&$W?ba$nC=t3&u{;Dk^$NpnSka)^u?WChiWG8y+*SxE
zEA)=S=PSS)74CzmY*JXrJ>IO?=M7wof=x$(Rz>1&$ZS)rqes!M7^nU2UB$q5uyiQQ
z)9H^|Iu$aCFLx<c(09nX74z1E^e9HjC)=xNrbEX)g*!!E`xL3P)$CWe$WXekC?Ox^
zfa1$xSTU%O(_Z|6!fg@sK2+Ra2{NSEu^ybmihZ<md!+C!h29ZG@@A07iVet_bWRvm
zi0Lxqm_pMIF;5hiDF=95v9l6ZxF}o53A{@=fig(klpaSQ#$73*Bo$BPgNIP)r8I>@
z(;nsb&j7bq8NvYZRkFNb{XXT$I<WXDO_a&#ubfBOT>;9ybc_pB27Zr{Ge{Xm+0ntu
zhjeEyM0tg_gQ3bJ@1wL|dG&L!9#Br{139SVra(-XaxG2v;YtG~U>{P}9Yot<<<!Se
zctlx2ne7qE{m(#Vr1E(h!zksZhp_OdvX>UVW6Fb1fkZ1^D8PB#sr>aK`V^x)PM(uk
zWft9OJgF@G6jq#4&euT9Y2|U6^%9k4x)GYBd_>7D$x0o${!)~ZOq5cUuTyY7O=+8i
z$}>veS7GQ`<^5TxJg1!JhsyKHF)@UtD?OJ&^aW*e0c2(<ok8!Tn5p#H3X-K11j34o
zN+zAdE-8PcPx)jkFDsxoN69UOm|W!#;V9)PHHTq-zOpPErOV21)1a_Gxo;wjDOA?H
zi6>d4O#2$bij~PUOP45ras??>-k?doOqox4`Q^&1&S>bps+>W0cPf=D`KZ07lv6&~
zb>**517D?#q*RJ(rP=@$H<gKW5~)@G^9m~KltXDKbtva~!irAib3Z_Rm(q&@=iSOw
zTFrWtyHhX-y~-n$n{!V&opKlZl&cef>sK~zrS<Q=vX1N?P~I&?<DjyMJb4e4NqeE<
zp>lN;ScjB9U5EL@%2BfWk+Oo$N+U|;7m)o}`F1AyG^+HXg<wp%@HlWTD)DwmaaF~~
zLhnvhY$$NMRMUb`>82Xr4dSl)-!Oe^Ww$Cs2_6qsIwdiAss!X_^HPm0L}`!8kq^_n
zRS6Ur@=^UwuKT^J5(*6Ysy?Hi@jlfm@<sWno_YmV_^SrHU}%798oexmDlY+~1gW;t
z=_Xjksz513WuhQTsOpCi^1tj??Vu!v1FAjb>O82DllLl2^_c)-!c`tVC>>IjT|()w
z>H}{8kEp6>nv766SP&Yiy8kOGqf{5^g*vK=+lbOJ)#hI?YSF6izkt2RRb}MXi&35L
zz=MfZ-S{4TiBk<wFl6xw)vc!?`=sjd)4-ony-ZixPOI4Ds)<)c()5v_no4Oni7L0y
zL<R15E+W@os_O5rU|O2WL5IpSDz9$<KdXAK9Jq6;2TLIPyy~M%5SFfT+YfR<b<GWm
zGE{x^_1;X?#V-NRQq7|H&_&ho5dbc!c!8+QR)sBx%p6tmA0WA^d^%(0sjkymHedC-
zGZ=lktn!`+p#>_<KGYVfHc={Xk?QYS$Szhn{|7{g>Od+gOI49HzGbTSX;G_Cl~T0m
zs>+3eH<hZQ8xVF))%i34*H!ojAiVLazK_tCYSmOq8oZ%8<c;pusN!}5cT;upU&;=v
zRfYINcAe_{Db&`h<f|a9LAB%;jO;Dd&$JzERCSR{xJmUL-KlC;t)B{MEvgY(Fk4lj
zQ(<<SYU^^8I#hqZ3YJdQ&MyJ)QpM1LuUA!Aj>>zgt>oJ2Q{DL)Z38M!0ezlpP&Ml{
z6d$PO(PaHlwSaEb4ym?&2up`ml`~L!q<UosWRIxcr>vvLDjV&yM^!`gQI|2*D^p<F
z6IER_0OKl8O1*MX&s+n&u4?Won6^_LN*;t=YPWb)x~c2G!-MfqyTRk=oZzWervm7u
zK1Wlqk9tWTtk|o5nXU@@s%LEkexLdTWfu6UyW?Ptzj_Mg7X_&AWkOS+x{i()LF#?e
zVN9^vj|X^&I)pZ9q3X@#d)}{}Jr`{U)b2Hqc~Jdv9ZF&9NAJQWXSjOveaJqf-b-I1
ziBQjDKt-h5izdw|^-Kk1N2~kjT|ch=YXV4&deRGMi&cO7J4}mH*HGrz2{o?*rIYIY
z&jD~s{n|EYI;~#oiY~>ghg;B=pe`T}LZUkHN3bNRm0v<pvQvGJoct;3GD>4hRev-S
zD$>*=bSLDDdP*!zJg+V$XKK3o<Mrt81+@pA*mBf;-=b@|>T>c6<f)e*g%$bgz~@kT
zS$%}!Sq18UD}gIiFP1`Kk^1+gz!j_4P)2QuT1qjiQnhnlHyX>-+uT9Q)d?byE9(A#
zps7MVYdO?kRR<(OcBQ)aFvvCa7^Ra{tA8EEaNSVvsfU;v^{?kqc~iZe*2Y?O<_EB;
zPCb>})b;AOUw};w>J6LFc1s=R3-yiaFRy?!spFlrFKSjVq&R7ddL`|dTGc)DDBIMR
zDetCTZKeUbt9~;Yr4F_Cv*7Gjj~apNQUCBWI@+r~N<oQx>RaTr?o+=`xjg;qPw3*q
zeRZcCrVXe+DTcy9bv%VqhtwK!qYSHSHBQh+YE~<NBkI0kNPDdAp<nu_`rGrskEsJG
zweE>})!)!NuAV~S!=0KB%Yoaa`Gh8UH_eaq1tAYjp%QJLn$MpDr<Z0CrDOVNdLO{h
zy_&`XRQhT*b5ZiwWYcjfK*MgOl&wHbAO&ATG@njDW2i<!Ur^bvDGCBUOw)pM&4h3b
zJ~oS&RO6(4kYk!WJ^<00U<#uj*PKg6DMn+U7*4FFF9G((X&hY;c0zNT&h95QGbjcB
zl;-sds64GHr;}~GrXF4==Y#}J;2Ypc)I`uH@RBs2Q3^$}=A(9~PtiP`1NEtzCFG(>
z)13Mgz%!a{<f1vN*|Hc4&uM(lL;ZP;%nxnpn*UMK?*)xQ3Yi(2?XywJ)Fi$MK$hku
zx^Z+-vy8|k&C?43aAs@7hhcE8=0YTjc^cgS5c!%C@^)X=+<zH16=-ZUT^4Hoq=0ad
zri+~P#Tp+99F%AZT<~6$YD&m+Sf*J*zNm7|@Eb7giY8_rDl0T|Tp;?YCSWVzm6{qg
z0M|6pNsw~gsnOD|{f4Hl0<|@o;sap4sX62VgX=X5$@kr$$*l+LEzNr3Y}DMLePEO3
z0Od0_Yw`+FYSFA)fl{mHu@9uQX;R1m-=SIYF-WK8J4!g~(%d7TL9gZt`S|Z?>`dVL
zG|puTH1=!04TNp?HE;Y6_yNu4FjPL&@X0+lq<MBW$gn1n9G8zZFVnttRCAt!PGcI!
z7)*1~##5hMwT55Owo{v!2SeSpAJP|(c59D+4$&Uk(+wzjYQLmO(@Q&g3@m%JZcaZ?
ze{Ebp8UwUPC~zLAy;1<4Annvam>;ZtM6Y#-_D|aBhHCrg!TkN&$H+~ca6r5G9ykwb
zHxVFA`}tH1UbyzhD3lIq(>-C#VQtE1z#Y*By@9p}t<N?X6RG`UH%OFLbb&(FN3}20
zvp=T&jod%c+P#!BbzIv^pP-D<uB$>@toAi>C&p<#-bULA?S(zC;-of=+##p5%b$j!
zr?u+mp($RQa~72eTIE!TPSn1<07IFi?W2V6WbL<fza>SxE(oPmZTf8bzCoI{>}6PU
zM!WqQgr3zN&w#XZT5mr{JFnew3|6FTXM{uj1+C;9Dl@ca%7D+*=8<bQOB?YDST1VY
zp8$7B8=eO#+1f{2QJJG%M?K5czDtqzJgrQNQoi;Y&6bz7-EOr06=<KOJxHN8jLz9b
zT6;ElinUqap|V7~4VeNHO0_=zu)9oK-UXI&Z7F$5uV{Br>Q#kS8i3L@t&9RJ*R^la
zd{L$KN{5shZOmR&-qf<b2dUL&G{Ni!Z5zeEZ)soI0i5%;_OcYUP1*@BLRz!7P7A#)
z+MkM`uwDB#9eeL;trUOg&`$pvLOZpu(mjMO?aMSTcWZs=x80+CGzTob+5|c`-qTKe
z1H;v)^`JMQU;F+{Jc|3;Ez^M;)JAqd{R8banlBzYwKF$E?~wMHuYn)dez5=wA8Gq3
zk$6PQrQpD0t@$;yjcR}0jLI=>ISzmmo@gKJgQjt9|3dWFMJG){o2xFZ7nM78FVeEG
zOZPz*h@0+s8LV*E-Pwz_-MX+P5aywq|KDV-b85PP_tH({!J0j~mspVPt($iVl|DKf
z8|wG!62{R(U!7A3)As51(2>bcXZ#VI{<;N`s0`4(OP+^7-Q~9d2-4lBsA;h7yIPb&
zbVBlihU!*P<ZHj~*l`$hK(}=wSPtsKopWJgnC_1=P#><_6#>16bpKv~rH6H0bc5iC
zZc;v2BXsc;$Bxv+?Lu3W&XvBYaa5;x9psoU|0-lh>kfYn*~fK^G>{mbflQ0l{YCRs
zobD6yBc9MbpySj@T|dnir*wbIoS>(5DS40`ubcV>#3bk@kHDBj-NRO>Ptr}61Cgv7
z*bHeYx~)&ZlBydVhZSkM3&9{~be~QK%URuI+FqU0P0og<^SY_uLUg*$L@D?ebX%fP
znW0O63#Ck5EQM0DboNguWOh-PMZS(px}U~iced_{4}|9E7SlF1SGS4|NqM@}G<oLh
z+{a<sW!=Y0kOJM$<Vr5og^~ZVNN1p{tHrwY5~wKARfWLNQr(C22A1g@w3?OcTmvEc
zitfg1=vk%iF&v)G3D<Ow$YFY2x0_tMRXX=};H!1ZX`6FH_t^rduh9)qHq1@kcM~A3
zRyX`D+Uj(FQt-82*GFkp4Z6`^P`ahddl7)!x``>U@Q!YHD{zgv)wH>5(q&D8hGty}
z8}Jt0a`GBGTXlW3{I==d+6iF0?xYZ<ySl&r0-{5wq|J1v&X@9gyL5m20bsZ8a1=E4
z=<+D;->VB)1D1O_Z*na6>24eYXTNUuPpG`Fi=|B70o_(wa0hiEv=~3oeMWoBhq_qu
z&J8(ri(f|Luue}WibuM4Zv#J~yJZLKW8DiYAaqn$L1E=FU5f!j`b4*pa&pFXYe=?>
z{u8=0=c=E(9$j<OKkI@vcYPHPmAm!5jUXQSM{lFjQ~#|O6ng1}lzg{GZ~XwGz4gvO
za)9{gFYia~Ui}t&6u$c46_B=1Kff83etKg%h`+v*-t_=|A_YnU^?S%C6r@*LG0wsI
z_yY7PMBft)Lqqii<kjD=pY$%ebU^<mx%Cd}Uwe#Fm|mU?60ToF$z6x^ea;O49@hV1
z2I7c*0bTiv&`<gj3M2LLAHd)!{Yt_g)z^Fi(~jvYC<Ys?_kA60$Ms9P@C;-0=4wcZ
z)wirbWt@Il1vpRWGrxv0C-uJcU4>J6`F`L|>jzi>#Oq_|$djPou#Q4ziF%I&@TBNx
z&=s0g{WQ9~nWq1z0i`qg&1CmkefmyVcuv1A7Glop|9k;}bp0aoi(k<1{R7f6^pW2H
zkg1O#=T(;8LOD;_`m>*aB}YHGA0$^_KL(pF>wRuRLxH|H@mc)-3ia>b1-?XI^8ol#
zeK-01%JhHHv8qCEC9l<0J^NJ%t<+zc1yZZeQJ}I;zxpTu_4>u}kk+8@zXrf9{Y7$h
z+}59=t7LcdQ|JyzqdtjNjwbyz3E<88Ww*f6qF;yE&N-n~|M5cbwCVp<fVAs>I}e__
z`U{I-X@`CT`4Kzyt1hCgOFx4Fz1{ksYJu<3TSe$oub$BZz&(9S57hVRf2AFLzdqn0
zOuMhoDM00bUh@{D4C>1Y!1+MG^EN6U>JKO&#W|$EnhnHb{Ri|Sj_Ttx!84}c$A`gB
z^hYQOVO;-V5)dv1$zKraYADJ=+fKuC0kCPeA%&JB55uDcz<C<Jr(czq;m2~2J%;&o
zOUB!vd<yD)3_f(?+iR#@gUWpd|79S4PD6ALYW)pAU&8YZFpNh-OrYV>ufPWx<Y&<q
zY<O-zG=&)A^1u>m`0Y)!?KfywgB&z0p~)}IurUS}h8y0d>xYL7ujaz0!-iRu!W&_z
znhbcPflsHKD8q4bCmu7r7mc1p8=SvUpz^q3IW2CnhF&*_i8CB^!_b^CSeAjDG<@L$
zF{cdjyC@|Xn%)II(NITz*CfM9+O8)XzEYtw#V}nCmQ=%W`l+NDdQU;-8H1?>oM#P^
zdnlzF`fJg_3x*SSz?oqPcG8J4(=hQr|Baz04z(8zMRHVLGI-L*sk05ybZ*TtEF?#I
zuAzJ#+VTva+<{H`hS$hlb=lCq6)Fl0bC;p5&=5^2A4P`MYtge}LlkwQ#1OFr!paS{
zQCM-s5Pt%s!caVm&Yf2cPBrkAhEOr^*9=907}@KFC1+4sWq3yee6?Zkhv?G{!zJ1y
z))-ROgY%|g)>*XG8QkbTPQBqiy}1nryA9-)A#oz4+%|-s1j`-6$G1>wG<?iLTa&@B
z8rC-(j<{0FR*OMKH?3L?-*uq2&0tIgPrKpyXaMgTlHUR8Fl@4;veO_S&tsQi*?e$z
z8`Ou;)?@IXFkr9YvNvqHXGjSHxo_BA2{K?1(>G}b4Z*%3Lx#`j&^~N<u@aqlWQcu>
zet#o|!hbLbj}0wzz%y$2LI~ivVbkA`?P3gB0ajPzhG)^kT}I)0RJs{`A~1UH#=ps!
z-NrO}uRM$+KcnPnyg~<LFQcjvQuY`*b^yGMztdXbW4uF~!@b7m$YbJX)RH&S>2LI<
zWby#x+#f*#jVlIVMUc@Lfl{y$f3}4;-?)?Fm7&H>ccE#&@oTyUc)&P;j+h6HMw+F=
zjFGNj2{)djMDIh!=si$)*eGKFe#H340J<GvoHr4GNaOTo=#4U#P;B9-)7bDSXpGTX
z41BC{#~lFUj7uqMdcvq9=h;bP%_ZPZ8H>ngaoX5P`<r;<*B=0vVDzD{9w!<HW5JSS
zoR$S#ve9w}!cvSU-Jvkm*mWHw&G^&=kTb@p6JR-O)YIwroY9GQ1{1o`uK|d3<M?){
zxL`a_+p7#?8hL0ljkUD1$TI#&al?zo&67bc8Mh@sVYYD+WfbKYS5x3F*SKsFD)Wrx
zO5pO1b8?{Kve8!xdkc&oQ}RNgv1l>$6&WSZqo2jbOy@Pw5+j=p)>5OQ0jy=lYv-V%
z-1vkJX;+MYQgE-rm`4-qRilaKluF~8K5$+$CeXZm-Po1`DOJYlGhj@$F+3L?y<uE>
z0i_z_mKOlOX?(aGrCQ@lWN4kSl71@n#$|4_{xujo-vZAq<J*)cdmBbU#U0}><mGEL
zo}$B9lkw#TsBAW7-$rGdaUUgJv>SCZ(5Jh`Ov-xgFs5<A(rKLeCfd4;@6$u;HXc}j
z{`MIEw;FA|MoA_5dC!=z8jAXio(4Mq^&8#k3fq0-ieVrIjO@AS=%DeHS7GpwF<=H*
zhm9wi(DukUzZB+=7`Kx8$3_*Ml}3%Flw~nybfZ+2Cq};o;2bxeq)T!xrXhOFuBOH0
zTiIzUhzH9qlhGX|H&Z7<$Ib~Jrl;RWt*7aKVL*79oRpTe$Mh2&Z@f)U3n1Ia^!YE)
zwAWNmYm~34e-%pmOfmFvK|hn33!D5+D=9TRz%<ki>jO<|W<g4j>Fjl|1e^Ae2Qb9c
z`Ybern&zv(x!*MV3fi0pOcOB;OgL!zn=(kkOxdqMVYulh+9Vz_DgK9HJ8arM1=1o-
zL6id@Wty`Tz@sJ?l6K7Gav3bqrtvlm*KyMezOXRH6iB=8SW_7N{^CrPuYu)+Nt^`u
zNz*hwDo>f3Xc9T?H0_}HL%it;xd{?Y8|)}0nF<b~lx!-Y-Cc_5BPC>~ntq~O*fdiP
zy)$P_zh476Ynow$&~v8V5vVwC8n_6X(oK`LqLgX!>4u?MrpOXhUNq&?sOOlL2|;pA
zMsj84nVcDvtDJA*H$%l`Q#oz-3rrs*p|Q}kEEuH7luItHVpDBCG?kc6Q|PMHq$OWR
znW={^Q<R%_(@TEEbeeny6{hH809-YF<OzE#O>h4M_18?Vd=1gpO%;?QQf1Q75wY5|
z+8GIHH%!sA)2%V7W}@+?Y57|ip<0vse5j~1WqyOs)SE(Hh3p2Co&s>UOoeM<?`=~P
z4c8shAC$S(X!?^}LrtddY4_Z0>Y|ms#kAZ7q}7!7H`KSA`YEVz*Yq!34-+~}tLD>K
zcA93;YT9Me&=t^blWP|$drZLvsO&YpH66y>Ge!J{%0AO(3J3I?-lA^bH;s^6aKMy7
zDHMaIdLj=@|LS4ILsJK3pAMPyry+CL)Ipyhd1OkS3S&l0{?{PovB|5CQnp4-)hehM
zGX)1=pq`lg%OQK*^pFWlUCgiUMWw5G+is}eX|~f7*=2s|I;6Ro9~3~gyP4CEA=z!#
zRG`hn{LfDyp62<<km+R}3PWj+xoj#}yv+~VKzz*pbUkyg`I0Y%tbNVv&w*#3`3riX
z{LD>DK>W=&tH2XrF5e3Ef#xx~of>4WI|`w}=1<705@J?So<gYkNjw1i&4z1`eZc%>
z5PE;m{26(T!_2qB(U)-ZTeKP;GOwg;vcu*%-vD>Syv`k*&ImJu=Br5aTqlMm%G^lV
z14qrPnBX~PzF-51Hs2WnIc~nt1kM=qOg>DDHUGH*LgUP@Ss~_xx#Bi(C(SpmqVkkE
znO4fv=H06xGu}LnK0cRV-b**36V1cB(3WIA6N)iRcAA?vp)tk$!Z2i~nhR-{b=G{6
z7V~rF(ILn_Zyw)?wsiA}(?DD>i&_B4Fi#}sWTtsG4Str{eHkh*n)~QnbIH6Q1b}Sw
zd;h?g9CP6clyc1p^<c>}XNN+4zB%wHI4_%>wlLre%p1s!Q)pg8QN1FwgYveE&6AtK
zT4LV47&euf?*@UCng7g$-g5KvKSSCT^Aw8BSD62L9c@?5I(k}_=D%~H@S1s>8``d$
zkJ36)W!|bsWwm(?rE}ddR}?^Bjd`N;1R8IeU!n=U);#Sn2C>eZO&{i}H|r=TyumCX
z&&e(GY)W&wZGJ3)g?G#@6i#R~SN;q`o6LN=yV7hn{s^Hh=GT8isnuLVN3}L{7#$4S
z&9Co9+g<bT|1DMKvy{!!X`YZsOI??F`QH%JZJw5jQjhs7KWOSTui1#fzh_P_g28>}
zg|sE;Hy^Kr`upaalkt28%rBorY0%u%0cj7+rzn*A(45-@DMRLmYygJM!85_~$h?N)
zVIyX46O4ImE}(ljqvq2EbY*AEypVF)pP08&w*9!-OrCHT3+E`TaJ3w!{KB1<=eMJ6
zmt{X~3EV6{(l*w^(w7VtPmB6p5HHIj4eZ@x;Zg>$w<UEOEcCI=dkvNQEYI%)+|Tmn
zY_$1X7JY}dAj^`CwEqmYOj!t_Ar`kQs13C+G$8ver|B~^2P{u$6MxV$aTYogX4yoy
zr@}2S%m6uLsqP2oVawV-!E(f+P@qpymR`E&c+|4c4J^kjFH&x2wB@}>l#W|&Q({Am
zW%Ey9Ibn&TbCmO><@^GOIc2#+SA`NRKenPa(K5XSr6fzU39?fy*=@k5SrX<$+8Ik<
z3|P)uzNY>5Ig5t;z2_~0Ua+KFnkfKq!D6R8tPD#hc{MUEL3G_J%d(V<LAYqy@-YB8
zmUIQw<~l9xe2iY6<<UDp6j%a(1}U_}SA!H;mItA&#Io)>gqB)bU7@$k^1?0P%PsTi
z<E>XLeRK@0uvlr@xoY{9^3*FW%jl$d&9cCVQM+z&a8X%h`I6i>H!K6|@$70W3uqsB
z)8hPw4{5a)#MbfVTb`%Pk$Ow?0DujaX-iPLW%-s6w=JudqK9`ZiIia1Y`OF;)VElM
zO3=er%bo~W*k;*7Z(zG+2XYZ6+_lW4pGv2tl{OY#memP>cU!o$cj>WAr)@^BWs*~a
z+IyC@dtqCj<x>xgNxvnWT&4Fd@6dZSU~#(+V+Ji#B2ju^`P>4QhZZ$CiiRwl*H9X^
zgr!2-h^6{hnD*E*Ob3cli#yGhW0q}uQTfF3(KMJgZgJlNfQz+c9&B>8_Ww@jzn#_(
zwgbP*IwKgw&H4u=@3~v2Oa#wv>p@zKJ**5mJa}5~QAF0;`VmbZKGv%DVbfk~YZIjS
zS-+%^x4%_z0D1$g)9FMWXkAaKH9=MeMK6P`{RWiwTYbkN<$(2<dOH6dw7%bq#xU#Q
zKG+s+Jr@J~A?t&=7@5P?z<+=^V%<V9kqGNQvCtc7UH=aH6lJYShfPPVx|JZutfHr2
zMYJ`X&W*>d)f7yOv2LK`%2?}Z`UmkiYi%NgowCk+55i7c-Qwu`uJKm31;d?S{Xhz#
ziPq=H<(OpcZ3juU&L_81nsp+1Mb22G=pMm&>*8auH{DuKpVYWujhg|58P-1X+-F*U
zW<y1mHIbH_i`J?S0l#FGQrIQiT1p?T&an!D(3Wex<d2dw&pLA&@cGvNKDB$<dWmM+
z0_)W_C@i!xr$9xK^+GW4#nucC`cz_lg<P|x*0i4>yUcoC0cqvde>Ote6{{abkSna;
zH-q!4HGs}TmDW~DzrJQ2B%f-vbrS8xZ&*L?LSJf})-T90chmYNeNn5{>hJ_>o%MNN
z^swGK?_(euth319bjvz!gtXh%Ei~MBtc(&=Hd<ZGsBE$_s)1{^wzk8j7V9K02y3-^
z&|K1HJ+TU$?bb6DDBZPgD@3Wox~&wQ=(IX_O~$ZwS=V%<+uc?;nDFbcZu3W}*V>T+
z)_c}idJ+4q%``FIxAG^TZNS<<$ti=@*7Xqc!1_I<q(8KNnhj%ytWWizOT*S#D*$+8
zZBe82*ji};8MV&X4)~b$&NBc!v6eXJL;bilghFR7wyi5s>uTFR7r<S%l{A^S+5XNz
zo4f7TU9e)et&T><!`4nwpFOtA0VsLf?peU;V|(#e!1vlj6kGJQDFhgVeYRI0K%t*4
z@Gjc?ZBK1PTYznhyyStlNq^FzGRQWOoE*Wn%u^5=V(YL$XsFFb>G}I@pHQ~p0h@{L
z${n-?Tt&CTY-67Q5N_ia!O%mtX`kYW9JVE=fgG{z3IaUBHqiw(McV!nKxULJ;~l_{
z+Dcp@?3j%~{`6=Yr<C$vj@#Z#g_s!I`ecw;+Xo}yiL)*L5GqdCn$E())3&b{Kw7*l
zVh3a=*shF&CDB%O5Tztr<f~vww!Mh$<b*U^GQGKHY?-uoIcqzVg0^$E12(8XZ@Wo(
zf$6r?Jy3taX2H(QIU&Oq{uOF7ZN)UpXW3?wii@^C#HhSv`ymd4m}9FVe@3qD3v&DB
z*}hDJq4~D+|Dy7;&Fl)!0^4iHKniUaKZN=s+tYM7E3xgOXj7>z=o~o9Y|H1NvfS1{
zpB}kln?O58XNAp=I&;;wD+9Hac(CBPX3Hjz&2`(izo1lQEA&M#s%`2H^x}rCmf{FC
zwm)-$yJ_1_KA~FMi*$pg&gMy3R`oXT4CrmJ@fHGb%f{;lxotc12;IJ88#@hLqisHA
z#x*%@*XW{0v+eKGz_;17G?Ta6=6C^d*QTe-^qn@ta+JDk?UWSSZTm_C^*y#3YK&8_
zt&|?xJ)3?D6!zK1%OShpHhdB?@7tz-1(pHZgq45~+9ojoe_%_el&gof6uLSyY;#8S
z1M$c<o`;bgu^FEM>tkC8?QceHjh}<(iS2PEq>V!w40f@vpk1)5UCDxJJMF_Xzq;A)
z-vZp-{#gWAcH1w|isxZh)85C^evXHdmp#!NoO|q??I?NMpQm&oANy=4y{vof;WR?N
zb}P+E`|QPZfb+BeMj=su`yid%0_@&jf+f&CMn3EydldP7g6(t3uNPu}j`ko2?L#*}
z!tCGd1qrwFX?{Iq-|YsL!}cxT1AfFlasluN`#f@hMA{z*InfwpPmx05QF}->`V?*7
zM!u-y_BdMoW9&^AVMVOH=UbHG?7z{;_=LUbIK-T^SC*oOr|j-;L)vM3=mfyy?LLuE
zpJ=a?0GDK+Jryj;_N%in%qjLWOTd|GcU=i#Y4$e`QU1#rdxaW}XYHZ!K%BFmaDkZf
z_8Ri9rQ83eEUQfWla*k}vd_%}xoAI{4fU7o6?6qA+s+LJF2`=9<72M<M;qXI_B022
zpKsTG2f$@}#}?=<uurC2fQ9y~6(|+i?YO4poKS3kc`Fbl_HFca%~Jb#E`*lZSJt9b
zZvTD=ZCC8C&<3Hxo=ivTtM<1jQMJ;ZUJBE$*_X+|dEL(b0kW&?Ke>QZ+kd0e!VP=y
zB9Iz;0nMa0?bQ^WuC*H%!O%K;`4Y%<*4wW=0#Aee8oj!A>}&r-W1~IcUx;b4Yvu#d
zY~Rs{QE#z7xR170`^8_;-!}Wa?HK2F`{mW(yla1S3h)m5TXVqKX@840;a&C++WU0d
zH+=@uV^{yT=dw4~LGL|#V=JWeIqmCT0qwWHM`<bd?Y~mEXuxjtfV4q-;{gC4*k7xM
z(1-Te7r-)PKR}%swr`>X<0Jb@KGcuc_2hGZY&TMBz^MJZJg|(}CsI)1i9PEGD#z{5
zJOOcW^wW~=>L{KCz)pwr?++kmmt&0XF}OM2rJGLfj-SbovfGhGo>ni%D24O(IOfo*
z<n36>LZy!*obsFYI_Bnp)7KF=2z&QAei=Yt{2ZN0DET{HrfiD<$8SC;1v*BCpdrYS
zT7t@8N9Bv?XNY5+la}95$Evq6Ui%$28&G?|!TS^BpksJ0G=({)i!tiqj=$(4+abr~
zZ%}#I@j)(1M;sHhz(qJR>GT@u2q9lol;dtXN=F?NJ-~U)F^RTE(T?P&Q9ACpOjg7=
zG;3gJtmCs|bpDHTyiDH$IPI9ELn+>oxC3Gm9PV^3Npy@;u4R&AfVLvZjtCV-HpS6I
z8=F+e_uVL^Ioz(Hbk-rGt5N41zt#eG-jTHhxOB%)^ozUT_>2yP8IJa4=x(NCbUyTD
zInHSRi@!SxXbW`7u~Y*@w!`Bq;By?W)9RAzkdi|^&$0MBv=ulMWvDE4ByNE*MUG$A
zLvN|$b^584IZ|n-TJAVNZ}(Nl>TGDLbVMxz;F_cUUr4ETOeSC74acShsH}0QL&*Pf
z)8SSDV69_HIfT|ZzP$^c+m00!g}mcfMrl%w4laGEw8`-W`Bs}9iS$HT9PiQQztyqq
zUEtarE1RLP-SO35Aa@-bUWQE_j_VXy?R4y*m}Hk@c{&ER+mYW1mLA6qO5$<$I@UU%
z>7K)%HW7V}k3WHme#ie=`VO$DuIFv<-2%HTEbP5^3kz#WtkGx^%}--Yj2dItB$imC
zCNWVHlc=i@jZ5zx6)92_lwtv-2~w<xpfmwRX-W|+D0UI~-pTiW9v{a!XXc$bXKy)Y
zX3ll=7jUs>`|q@%db)i89d&=UefBp%d%pdQ2NYjypGo1Lm)pCGVd>TODq1$b-ahFq
z$eZnH(fFBrw?CtG`rGXtbc^+Emr$bd-S)qy0i}QYps&C=nT(%MZJV=kW&&6jW3Uy7
ztFcsxMmJ+sH1s`<=Akg?W#lQ#<!#)#2BYvX?x8G*uaO@K5B-ckzr+Ol8*6C!8(>to
zp)t_d{1{+CMm1Fg1{=Se1HBMqKp(hJ<0te|+-o#Vas%i-<EOOh*l%391o~k{FDj-x
zU|dM6{&1s_Hk=X0^Aw+sG@ji8ktkz61=J53SJQVZqK#82e-~q{p(^26<1DI|i!**m
zS%E`Fhtsfd*m!UjNW8I@GUf@!r?js)V$3(uA(ErUdGud_Bpbh`?0Aatyd_|c84KQ_
z@3?W~PH-oT(ubIflg2+OE0<;r{~hMjjqE_coHEWY#b7dwA+Zq2GzOf9-5g_t80553
zJOj?;8V}V$A<sC&3fvjv%*DXWH!dls`>((_i{k2qM&~EME;8CUqVa+ewY+$P7z;0g
zyJXyd5opE6UW(0JHrA9up~T3#1MQ0Oasot3jlWXSQ<<?o1%tS1lu(^Rxp6lgOsO#L
zC%sCeb}1aKG9IE;UA1xaP|Cm87<&ewwbuBCa&>h^yRAUGVN9bd;imB(1v2W5Tqh>~
zma+S1NH!QPXG6cyxQkNWO~x8Jsnl$=qr0lbc<Liqx??;<ncTa^(sKCJW}HlAjqOJD
z0FVyjy+$<NGj1C}`@c>jPQKwLF|MN!?R{fb9t^%V8YDpLGX@^TK>Ll{k035P7HNU)
zz9Z%#6ufr)wiF7!JA&xZ9k8S2TZqK&7;^(tlCnc`73NcSjG_Ql#*R<&A(FGh_A@l*
z?WmxQX2A}NYz)bCc1JQD^tia=^51AJ-LcOF+^rqIEk|eP4j1}5!_ys>I`sAK=)3@*
zTzCFP*N*2-Z8G`-ch0#8gW)?PDdrcqb6+1ClXh;11(&w-GZD<^?cDhmb}#HKu>rZf
z^W=xHP_fgDippwCJCim*CeWcy2@{bH--cp_4m&KH2$(d7pEjZ~%R$wQVHY^8SO%Xi
zJ50Tdz6ysH+ELUyT-yPWR);F8%fILFw-&BFarkZ{OuTZ~G8TGo9Xw=k#>J5-#U%JR
zD&5iO?^sDs(hx_}9;#X1=jcRrRgsRrxj{eP@x`YQO?0f2z|t|tWo-~W>6lD+YPzFj
z4-95Ho}}kZmZNtY6tW#>S)nh-v4z3|`Huh4How5J|1Nwga=cFkO=lgOT+nyUvGF#@
zdB=ve80Q5?FVi0QcF|E{3v$Wv5LHH8c3ef9v=YblT~I7_O!)^IWsd37(0J8x@fP@W
z&C!E4aOIA}_rUE+$J#j%sd6kGguZIWA1I7+-7#o2JgjvLdjrWjM;^fj$qh&QXArsR
z=t42sJC1qRsHC>dQH+Sd015t_XQFA5U(J{ugnu>6&S*GP#~fJ#{F_WHox-`rSkkVd
zf%$`nNE0(q1+InJtOR}=<1C=@5tBw$J}(&udM7xsxsO1+S!O#>LRgnWl+4B-b-^d}
z{(EoyNigqwY=NnvqbQ^~>;-LYhHGeRKdGHIYoA$tfZoYr9|QgKYRaEYnX?PMUo57Q
zpD*9c!Awnk_!Y+X)wY*FnAT1uHPcI}Fnq>3D)0V!*AlePOjJSlo1`k}&iY?HecyGq
zyCu5kSl@v1+>eUz?|Jtq=P^H%YStE5(o%Qf+=*ykw0j^%_3dlg2z)0m$KT&i%z@0}
z4vNPtIXDQQOUEyR;bkA`(fh+pdOj?7>jT1y8B{m1GM@sWt46lNt<_gVkTk8?O*MQ!
z`g@{j?b$4tSuaGO<EOksn5~~JR8aUO(I34V7E)o+uN&!+`<of%wstR~3J-VYH!4f@
zV2bZR!;@J~m!uc7mdaVZ8QW~w^<j3z0NIym9|{ORCa(u`;m_PULi_JvX54-#HZzJG
zc+$=MG!Kf8nfK`V`G!dh#i)825v|kQ*~6njJlJ7fWQiR_g*aa9^Nld!&EBRf(}yj3
z1{7a5l;U-M>>^t@<Ih@LgTW|vDP_$LvhIl>N7*<$hfI=0_U;F;l*D%TLqC}{%>`Nt
zn@EQqj<KJ}p?I9#auj_h*jrT9caqinKqQr&+zjkA_D@>kq_a7cXg<Z(HNb8LTQ~w-
z7CZVMIFrrJr}Ez%wnYF~rf3gE%CbZns;4n!i%fLNH%GMj37k4DI@F2QT+z%O5X}?K
zpv3JNQ4(c!@<nHt0H#1R^dw9aik5mqvPjgn2CkhIji*CL=S004pqv+ZFMz@YQ4Vc@
zFN!|&!dNbe-i?4rv1mRWX}c_{`V(A<Ni>B{S6vZZ=izXv==wB}GLgFmpjSno)xqF3
z(Sk4GaJi_I@?;gFL$nO36pfz`OI4zPK~Sg`?Px;db<w;qSgH~E)9J!mQ4?*f>O^bk
z*xC)z7bJO86iF%CdQrwCDBKd6IA@677EPe-c!Q|=8<=PmU8no6NhApZX%=}<O;wBN
z1zm)9M7!wh-(69e1f*5;v=%UJB8!LcuwA6C0@oo5H;2J{B1hWLb&Aw<({_m}e4&0{
z)V&6n4@6mO(DzW(Y?=<mN1`T5d3K9NZv%NOI!C*`C!z^MF$q1Qa2^gn6*>Na#%H2x
zFF5*KbfO!2FGNigQF$rKrd-J@k@EpyzZPkq!QdOw7^)-h6{YY%aT3p2gQ;{Dd(xsa
zRcucgrZn*oBLySU#kMhEPl+FlgGPq9x(P6u;^!1n%o0z1gvM-fK@#ldh-cH?S}t~=
zTeL#FqzZbK;-MEIStYih&z;;Be?(On4dUk%pKKF5hk&$;w{cMD6c;arNSC;LF!Ven
zQ(Ni(SMicup-N$Ii5=~U{P4fdU}pU#HB{XifUqf?36vcC1dhhw|44>2rzL;TCMZ|3
z;uc7r<PW-i&qz+vvHX0=3R?9QNIw1^CJH6rp8zS6coxF$SxIFjxbu>U!{Ffs$*-pW
zK3OCAnToM4Nxqo}{bGrz7M+(RkGo*EL}E){`ne+6M)CSa=~EhZleFt=kY;ISBuI<2
zZv@ouNHv3@epfn}rn^=8Pa_oCq}NB&uO+SMfrl@o@8Pj8>6cES{gsp1+AOG>oXzf5
z!Z#PQ8cJ>XnpM%5{LGg4q0!%L*HAbUVD=X++k(to$6_vn&C;lbEW|9K2;5$?*hawY
zGh=DPvES^&YH(p@uMdHXG|Srr5@oig0gVUEGAP+_*z76Q#blUu(4#)nWR|lTG|Q~$
zA*LqV?88i&V6!4B-pn&|nu5MFW{bwdwS2R}sqnkNEM*zY7n;@Cfh#uKNo%poW=V8A
zl$d?u3WY0Xc9YRqY9_P;<*M28tx&&a#?T>vI<s{uxP8Oy5iM(Pnwfqmfm8KneH1&r
zZFYr<i5twksnV&@%%6%+n#@E&z-}?Kq!9HTvky<8vDM6CB4FCg-02C^VYWO43ir%P
zE<vQr>;qcyKQL>h1m;6Ce_D7vGCM_wx?If7e}wl3%zK|eFWfxEbQP@;=2n3)A8DRh
z4A3a^?5#9k=Kn?jCffYr6!gWI|4hZivF88ofXHF<Lp8vTH*ch(mjv@mSI~IGd^SZG
z63vlU#q->}XedyU&3o>GOEJGc8<NM&+hzhK(|iQ&gR{(~bLpHxj`>b{Nu4&YD*$M&
z`4@C0<e67rhDN^m_^>C@IH&pnJy_40dpJVmy!io2zFjciNNb{t=J|g@{gOFP<GqYT
zI_#F1UwaJbE9Tq(hrTlN`cz<EHE*LB;x%*GI&hulmuO$tWu8<7?tys&?Kd8pU!{og
zBlC^)F}iN^Kzg@5F<))E0L32j`eKMaGyjX8TF=d6DP;7{d=tHu`psi0k?16=7eUfl
zwlE*gxXA7u1B|QegaR;bvP}+f&0Q8nPgxIH&lB`{%H~sS%uD7%<$po4)l@zoESp5P
zU#QIS7WDSY<}5LR?w9?x8;W5vU)s8!l&ztCQmU+i(kkh)2HK6El4-vKT88X57jT)f
zD-?^!lKn!j?QGdt`VDeq`)V;Wr)42Ukj$06dI<GASthMp&d7%5gXGJs=n!auESR=5
zg);6B`m}P9thE;!XJzAQ9e+-yK0`l+Y!q!BFUU^NL-(T0>tkSFk}ZltU$N{uMQ1O|
zKA8`_64|shkh~%*S_5ZFWz};*%4AzN!~8Yb&(|SRE-QS6VOPjD!~?8S*7_ODSIPPj
zHN-gqS(+<augmuH5Ur6F(<M+Vv%LdyLw0O2L~qKPX;)k?Tlo@pZ^=|GAh%_4f$+CM
zW@ZQTjk0lcMyp9So34arS;r~pwa6M=(RfET_a8LgmDNh{Q?$yg=76-xidtaL)GnLQ
z2umHZEwtpjC!0=7pibFns(1*Nf8Pt&LgY_}LnA_NC<bVxeA{yjElU0iZORYIhf#<u
zMn3d^K#P@cPJ;R&x%q04!*VBc=*7z;BycoAUcUp4N98NO0ZO8LfdSA-CVACQpvm$d
z)&caGe7Y4nPsm$;0oqCV5;{?vE6;6)YkBf#!{JlDd<f;&3*^840?<qH`Bbt~E`Q?<
zu0s9?ZP6>`>;4N8$^GT%tCmOELGQY}BpF~e@;&L8l3IDhC5*aGZhCPDc5ldU&`$D>
z{L334cjb<><ZG4Bq>Ab`x%qD}*e-XcH$aE{2MTE3lRvA1+nw?muE4%852W)L59B*(
zvGY*=n8Hbq<Y(v=*)88m(Z<K}iF6|FiF`F3Vd#;6@HtSP%CDQ~@ZB@{gg{_Fm(QZN
z_)EEBG+<uIzou%J*Ydw<0r*DlbPh1R@~)L2Z{=kf(C?F1(WdX6eC-Bs{c@{iz;?1I
zr0=>oTg)E`;$mSz>l0Utt?R+LSy;S)h`Yszc+8WBMd%R|^gS)UjDh<;7Af?@`dVzF
z<$|BZNLtDSSUlPeF3@6y6<iCl*m3}k!4};|025+yf^Mf!i$Sx%?X_^HgI@<NUi^)*
zL|c?lj5o$&bR<Zu#W;Gr9<sRK4DPVSF#7G|Ei4vLok)vCIR%1VTIeZo?WE{k15sy%
z5CelQ3eOaBU$MOfB5sPjA~@=<m@*46-U=VufB7i-e}IR+imVj?^;1M{ghGJgm;xw)
ziuR8&&|pP{0*xVxUHc)jU!kW%U15rjPidcYKoPtF?uRRK=&=>4NM8!<D8(&Wt{+s~
z8Hc`T#f^`k5vy>eWm%l!5f!-}QtbQ!pobMPl!#1Fgil1{5yfIhh#XZM{~y2-6?;a5
zq$~32VSP%m;2g|nD4tV9KU47{2YRL~#ZR_S%vSWxgJ_PT{2@rLVhG*od5YDP9xPB;
zegVZI#hba1JgZp033e+LHdNMKrI1=dvRY9{=K`-QzNQmbHHwnIfKsa%ISGw*ihO$P
zG%KoT)!m|~?m*uiMUfGbcTEa`s=V72<*P8zPKDKVkS+yt3!?WGRVgt4K+zuzk#0o}
ztsx#Os;J`qiDJVbOmL54I)y7<C>Brv>7`<v6q2tLGll@=wIcO09DSqMa~zg>6(bbz
z;;q8(0nGO)G<3)KTbh<o7AwH=%lps|wDf%g5@fmL3p55>4sHMmu{@p&#Zb$YS7Cmy
z<wm+I_E}EnfW6<+XBg1JEL{tscfityu99#|Z`!j&So)@dL|Q(d3&|+U`kins+H!q6
zBx5Wi`_UL{`SQO{o5xvp(5~)~<)@URIc)iaUKa6|oi!jwEWNH`5{_EFqmV(OW%R#*
zNwQ?rXiTvzn~#AWvyAu}jmIq`cEbD#%e7NLPFj`~qA}I-nE_my<%$s)M7rg?3D7%b
zsim*sWLSQE#{~T>%MTBOcv%SrAl_EHzlW%gRq=c9Da0z5K4lbPHQ^H)jMXG6gO9Sh
z;|E6%T0Nu%T#Qwk3mlELnnQWeIIC&&fs#X3TPdx7*lJ}A%*R{JQ-B<|D!2xpGOc2_
zgJfAH#L=gHvaR$M5Y4grf};1OR&~>1sm!YFbHH4+T1d;u8mp!BZmhLBOdmL@vvL>)
za>Hs>4;pV;-M4{Ay_Gl?+%2n5_QS*5R;eApY_M_}37;CR##Q6DYqFX?30^c?N&bLj
zi<K=V&m_5Hb!Ih2(Q37tjy|<nO{ZjkyHzbk@j9&Pd(n8$YQ%nM^jJ-#u=`W1-8azp
z%xVlBynJr;+Z!mnuv#z|+)JygRIT#L>MY%cudTc({`AI5NyVbQR*%P`@vW5~)uZ)U
zz1{=YOz*62yawx}{I(yR&PtD8KwOj#dVsnreW>2iO&LZ9x7?NSAHxd|<=idcJe6Ua
zA?c;OzL$P9WhcFde3TPcqtRE{GzSyxr);_e^Zv>Ts!$A2{y~|KK;^6mGzKZ%X-0!h
z%Ck?<8KSI0fJzdooOA@!woj>8g3kTQx0^u1l*g#f>wuD_w_&)_gQETs%FG(fOr-K6
z9dwCO4z_^7gUaA0n2%Pr(05s4m4nK_#VO}6gUBJ}4GP5^R_?ffzIf&IZ_t;ZG`;>9
zibs?)Dd%`p`CU9rBq<kufx#pzmkE$bQBIqINjRnq`4QZ4<<cX7IiWOeK;ucJ@(Xy8
zs+7h8G)?(UC`8hg0kow(rSzu_REF|O1BR5P-0=vK*-9}Tgve3eaDe)0<$6;DG;)=j
zN5FiZvVJ|dGfJKoTlvb&LO63txuFMW#mbT2L*ueiM@#Y&WlB0gtCZusAyTchq7sMe
z%1_pyu|}!P0$8omobuFl%G3F<dqcVI5r%YA`BMfI>Xor+0K28U%Tb;3ZRG&kR5mDw
zM547(S(F8|Cgl(R0<BqTO_SfEZ2TWY?kXQ_LSw5^`VWTIri`PKj&|iT7btWnx6$Xm
z?kST}K{}O5{*dfaMpD%2zVd+@3J;WHKZn9Y<;Qkte54#_p!H|B@{}_)9xH#l31^-v
z<3|DQnQ}%6G@dJi>6!3CdE_$4OXWLPh`dtXq!r_9<r-HE^o{bXI4C$<*X=~3i}h&w
zdXTHN4V6~7S%32fhU8)Wg6bqat-q@W=Vd*K7E<2Uoxf0>q>uGxCv^H+kDyn(pLO#P
zDEeDpr-WdD^}Ca>8)$uz&W{9HZ$AVQY%QA$ONlnC6c|OaO}rSO$87BAaK{Oo|JlNs
zRGZ2jFp+MPdm0KEHY;h1mt|A)Aq?f({ACTvTAS`{sGIKCIDU@KyEZ>3fNiz;ZUwkD
zo3QVo-)<8>1o|B|;q-QSVq-@es2-cCV<7p$W+tU4UfCp4!uPdJj0MOWn`Kn=)oW8*
z4=>)@Os2>~pH261G`_Q$Jrj2OZC)G)n3L)wx}2R&s>QURa#590QH87O^ekxjsXRh~
z?XNoeDPSU1Vv24?sn`$<J6aV@kMJ1PidKlksy_M*T%794`;a`W@|i%BpgM9D3MW<f
z4#Vzg)rONGxvC-G!eE{%Z45*%s;<!!@si3E8cJ8Us*EbRFRRAU!m~u>^*@j+syWF}
zELE|mpjf8*Y&ROOs;sH5<(i6J4pOd~-i^iz)qYy=R;tE+4suInL#67sRih{x)1W%O
z1(q6BKRZLANwvclT(hdM5?-{Z0!&o&az}OI9Y%3i<w2FNtt$7|;M!EFt>D^KQSR`t
zL-kq>{d=l!2B5K1b-Ndqx>S2>p?+Vb{s!CwRm4XSd8l&w6zY#u)l?$Uty*V+#>Xmc
zF!Y|NVwPY?J*rW3TJNdq&^@~Uo~c6T0_M4D(E@0^P}S3^xtFS?6_9zQYA8eBYn7n}
zl5bQ=6mslU73RRiTh(PtH1?@3?t*zI?j}Xrow+A;qQ`~%@;Sg<xoHC->BjwA0g-*&
zq7p#w=QOhbeSo_@j?U?Xb53+}B#OJFgyKO?PjAd<F77)x9K$Jh!~Ixp$2D+qTrpKq
z9OATx>DT7MDdZ8)2~;PNz~xNGJRRZA4u<+s&Y4OJ6FFb{!cP(xG7loj+();;rEuwe
z@ZuOZL`!+<<DAh6CQfi>o-lEeo1OvDRIWe->@==@0ASL&_iW()DX!rUa2Z^J6JRpA
ztzTh;S=?#b_GWW8X&ITrP0WDgY3?`$AaXf%8n`?zW<0nv+&rp<%IC^y-CDr?<_HB-
zA-CZsK#RCKI;wS+%hAE^IgZ_rQJm+l6+r(2*F$ffi(Cu^d@gY#NwSzL84dl*+(P=#
zVM;ib0xnm$ub*LPrCc;cSj)JJw92~5jlBtlYuo@zO_g)Wt`Mo<uF<=#(!@=bL9~h+
z`zd6qxhHhTUgsQd!F&xjh+dqvT(<&^bzG+iA~(3vR1a{I3;heEp8JRn|J>r<n*hn%
z+@pcu8o2lAbVeg5I|0(ftv`nWHgjIIpK0NK5+Hep^Q8kTc>e$02ANha!5+S~al`3Q
zSUb0TDhzgT652uC<MK<<*vX}Jz+e|Q`xM4|pZk!)Mh`fLqj2;gw`?97A935RU`*Xy
z3?0mS%vI29><Kr6euExPCdb4+<sx}-&$wSHr}LZ}Y+3}nFSwEP!@lHHWa$+*@-i&F
z<_f$(-f$Bs4AaY9S`W#$@EiJl+}&JAzT+a2G2VWzI|}Mf{ML^^ocZ+&(dfe8qrxy(
zzKNF2Zv2J?;N1BGRAB7EJNygIlQ)i|`_GF{s|Khy|AvlS`S2gp&cK%+MMoI?_|bK+
z<j<dY48;IGi_*q{e5wh3LHw#}SPJHC|Jx1nSN?>Dp?sDZ{N2lsx(;q1KbFpB?&tSV
zVOJQx>nuDxz{h!mg!2U+RHqfe@A86)NPbQqWTJTEB3L@e=g~tunx7SlDUIR7m%>sk
z-&c;o#PO@?pv@t^fil{M`48#c8qcqegh&E!K_!hxc-!xwca(ojWpRo8<|u$A@uMC<
zGMN`>tCqsgN~ZnaF<$i(*yDT;2QN<WUBdu+k`H(a6RCU^C8*Q*A09v?oqtQu^;7(T
z&oIIae%61tAs<7poGgAQ50PwsSQr#?_!R_pn*WDtKyop9aCy9M1k9h|-HhP!`LCux
z!BoJnS_!t0@21#Y5x;d6G|uwv>mhoM|9%`M>O3!7i=kcM@4bTEi~N=6;4bl3cR`_;
zuW*IJWxh@WQo?h8fn4EVO$RCEKRk%3EaP8MBJwJqnF!2l{ONx&vT}ZX62K}<{OUxo
zmHfAK-&gU6=K-{uKQ<h`UFVlShxr<QN<SKFc^qrOZO9+H2(%mgGG~yRyrB@5>iPQ7
z=)1*#{0=C$`Il7C*}%upv#61erizj#{=E{AW`2_x3N5_N*Wm8(_<zU&bC>@&1p2Lf
z1ce^jc;+p*cE0@^^mXt94gmBXzd8?noxH<nD0cBuO2^&j9d82d0WW!hzK8t6F6cet
z&)meYyZJZ@?my;@+i+Pu;k_4Q5Iwwt;+IePwX{HZ#y>M90_Hj2N0lWn_$k}q@Jqhb
z8XB*7E$ydX^TX-7dczN=XF@MO=yOQE<(Xg6*vD7c!r(jpfjdY)pH2xhCt->OP@IJt
z1_oV(trP)w70#W3+ipTU3rTljt{+4^guCH%A9)IsX%+1yEN=t0x1gcVVEG7hDR1a2
zbPd4J{DgrMF(!YZm5QhWgb)?X2MSN?pb#YV(n>X0*r)(#h;Vc$6hejJRPnl3m_;dy
zeS$j$o%ai&-@vCZp{NJsfZ(~0^3>r%Kphk#gu&+^8Yy(%#?(X!E4*R;pwL9Yk>kQu
zI&E}9*!K+_Jt^Fp0FhK-6UB+s1g-^*>4KE*kyFB#^I$haXqW?onZnn!n#>Y@Gs4kq
z;jetSmLoXQ&g-<`98dAjT;YAHI>{4Wp9km}A-DjF`GQRkGzx^qr!Y|{T(<@(66UzT
z(X+x-9-!xhJSt;9FBn3>T@bh`a2EwPDyqFCtfM7$u`vA;4C1ozBR%X(giiWs;1$7t
z2rQHe^Jw2^DigXFLGh|E?+3tK6F#RKpj?=+2cA|4+vs&xDYUPKYgIxW?GLJj;ulc3
zE>v%Zr5a)96rj}#+cJP%C;ZzFyElYn+P~ct!cV|Ny)fr6ByR~z&tcfN1v3hyHwc9z
zVW`n0j2i&aCSf`i<u(gj-9TD|>7g)jM>rY|w7Y`CO1Rc4{InHlZG!c9h_nk;R0P=}
zG+n{a?g>eYfYvD-p|3A=3705jabGBZ2E7MDnKcYP6mp({JQ60NI$Y8%{GJJs$Aam;
z0b_b1tPV$OkMN)n+*9G57wkS0_C$euE_{&=?u9UW4MbiFQmXiSB{YtO`PV|P6%4)+
zmNA%wULoi!G`<xM8X(dq_|W42o$wh2kNbs5esIP~J$^Mt=BzHs0_UPGHPNclRsCWo
zEV-#;Xj$m4E{Fx^p_b4c>#2S~%PTK+Kh>&wtFz8Q!ABiVPY7T2<unjK^;)`s{ndKP
zLI$WS=_M1WzC_u;Aa&4DfCa0UJOvk`zD++&sCpGGKK81WFR4y>pZX(;)b3ZG$c9s4
z>g^hE2h_9Z3|_d}X)Hz&p}sN)qmNWy>_=mi`g?l998~|E3WL#V-`^k-qrO5B_*nG}
zicZ9->**}OAvF^Ke-Ep#Il+r~bu#V464cYFZt#dYDVp|wN7Yf=(3z+{@e4GP)K6#!
zm8>pu2T4)?o(0ik>S4H7B*)cL0)ciyeS-scQoZ6PETyXNFM@iSx?vKWNmskihQcXz
zupLA))N|=}$W*@@iN-8-FI{ul>YGJq%u(ZGc)0&gs}lntnya2fq5C{_A+1c#sGSR7
zK41OI9e@_7cRQf3P;K7}{UUWc#X-)hw@@AHIrX-=Xgsfu-Usf2`o0aYFRJAtG+t6K
z8V|i<b$B2~c3EvP4bUa(syIyg6?G70NKB>b<W_W+so$d)&{g%nPhs$yx|nKl%GDp!
z)m@?f_9^-*)lKvpR;e$KgZXN8&uozE>a^uBQKLRh>&IGkB!#Q$)J-Bdb3<KEKg><_
z9D2&utIt1!Pq)<1K7{0Lb<y8YZ!oFPABLqy^*^7%M3eeXKRTP$vf=QlMQv<`#vS#Q
z2Y|V&o@B((TGcVPV4_WJLA#uG_2vMGbf_1`z{EXuCxv}G)pJ}yy3}!0Tz6k>(Fl<T
z>aS@h@laiQ9u^*{b7@J?tu_sQ2==l1ra#yx>i(Gk?NJ}6HON!-2eiR{rcR)9a?jO;
zw6b`i4mbwCU#i`%gL|buN(r>r>c<jz|3>}ieCYM6ZD`N)Rz2nei1exd{177V)U|s-
z`qd*BLBvU;82}HRHNhsz-@9nC>43ParoJ7WZkjK?gim`lTWG_&PqR4>efu^2<IoqT
znLi8)2Q*8jp)XwH{Tw7xGcXVeQJUk2A#zaTOo7X2%?EZcAEODl2D`DEdz-<<X@a#-
zKcrbo-^w_wdF?>!&v=cFKoc~9=1@GM5h%oZRP%BqNTOzH2uPA<aU3*~HD8T@WQt~>
z62I>;%?Jt?AJ_0>VE%-r(1^xVjoA-SNYgk{(Q~@yU?VV3X|`!$C`02xtA<R?X^Pio
zX<oO{Ik{|2yny-2(O79AdRnuI;xD<H%=gfkr&&&Wmou6*Ltr;wQ%<GK1sc1t=quFp
zQFU37#)dX`XEj6HA#zTWNsZ?<MgA~xK{J2~sxNBl=;Zz-%`H2aFV=Y0!O&&Rp&e8w
zRHB(q(by}R23nk!YR*prDbrN!1n5<bXd294)2JvkTds+wt!ahE7z|RWF(Kw5snV?b
z9qQGZZPy`rUE>xFQlp7-fZbY6<83%vr_s%X<PFUu%KF^Ygwe*lUX$DoV!EZ-Pg%j+
zn!1T_szGB-tHVakI12eUX}Si3Yu2Qv0JKFjcPxCmqbdCo<gVr!?e<$W=6m2wo91FF
zhTX3D>NXTQG-FfIcu!M34<enKl9K@I()cJ~=)R_50U94@rhf(U(4_gI7HE$&2k431
zt=X!8{$ou#2l7O7Ee|gCX!ZodwWpe>1(>~Onkf2Dzn*JMhk^D&W0(%fmzptpc=$^5
zK79%PwWcBrl5aG<wEFJVe4~TNTaE2tfc0rC|Ayo{jaLuU`!y!yXmLMibqC?1v({!f
zI2Y|eT9mqK(=EZdY3J{OqPx~e5eN@$E7hTUYO8jm(Mvm;s-C^I4K4un(SAXozS??9
zi}`7H)}hf~>$n3x1!(`IcX^;ThAKFMw6m^4Bv?DabPoC<+MqR%3Dp*rqI0kI*&$%>
z)21}S{C@2O@-R#raUJA<Hk#_I!?jZ;KtDp8mWD};)VAAUgi+ebBR~#n-E;tp)^4RM
zFh)D=F%)988Rc*$PCGyWltbEpOz0ifrktb4N4$2%J!m9oLuZ0JqFqRVjHB91-+)Wh
zjx)fgB<-x9A(E`!cob+U+8&Bt9n-F(&Fpcl&9CtHgmzOmL{4f&RQ8stUAZ12Y1(s^
z@FHD1wHaWiv?;65m!YkE0B16_b63#&FH5`F3^Li;#YVK|XkS%=JFV4G$T3&DlOmpZ
z+Fwecct(4)9M0rxB~(0ApdIB8M+>z-9YbT0b~DY|S#5hbES=Mu#RBZ2_E9RhOWJp{
zA$eIlgwC{-XnVegYge?Ra_Rmn)$S>R-(}k6AE5K9HkPi-YuanH@+;Tg+Yams?Y~rd
zTB*J9FC?q9t6#%XwRVgP`mSpSQ0}Ql8%{5`TJ4_{BdOE2Ed|OAZPpVs-qc>D2wuJR
z_dty0mNsxQL>jc+^U!E&)Rw%3r6#TITR7aT6=s8L(f*YM>^s^O9)P*4{ihhCXw^pQ
z;YFKPM-Rq!ZKWri>Cm3;hr&JWs2WIiY9lGJ)TL!UfckyyFI&Jp&@M;^d8oa<9D0wm
ztLZh^tsO6h$YYcC%VM<lXpd0t_^I|YDxP?z6{wK%xmG_BiZ8SyDPa3j8+sKEztVbB
zF~Mu?F4~^F(Y|s5>D4Nzvi~hEYjAzqKw2fe(|%iz#(r%Its0zk-#<p9vo84)5EtFS
zJ0Pw)lfz25;ig+v0&I6(D3t<w=r(=^gPyusXCULHbEQX;w{FnKfbr4o@k67p?sy00
z!cUjJ4+{ReV|3pK=q6R5FHo2F-?m7%Di?aex|0vk7^3@umKmYCy`$mbUR^~C$Ufaj
zQ!QNFuj?5A^I^KWuVCVUuBHfFxNiC$$VBK`=YmA)7I#BGN|#C(+d*CZSNJKTbtfsw
z7Nc8DJAznU3+)u+bY)+IJEZ%3Jj@@~&7K7=UZ<-Am!R8CLpq{Ei8*dDodsjU1Sjf@
z^ljuMo!O`0l6CgiKvHx*&tU18j@gZ&9oH=rgPhQXh|zaa=Sx>$s?L&D?P<FC@gV8C
z#Xo?Y(w+Dm-e>4$e+n*Bw<I4PX6c4f{vcb|8V8c2Yo}wmr*)hDrT9y(t}_%P%+o!i
z|DpAaZcQxg=Ifd$CRCs+wt;@3&e;KtMLG#B;?L@0F9G|UZo)xK-g(_r`oDZG=zMpB
zT-3=j(RWE#xecUP=Wqfdmvxo&!K)HoLjvqx(XI4_7o|F%T>4IQnQl83>R;8xI6~%{
z?(-9{RIW1~f?|bELvPGV-PciYrb_3x3!v4y6na=+*F~`~SfgXtLcLb^*a?z#x>GaJ
zcSGkvb<#I=lc{LBUbnOaBDZv>KLdAL$I&UH23<VmqfL!EMhvz|=WYkZX5AtBVOw-J
zM?>_EuBH=>cXgjom3FJ{;t-f`(+zwdlkh|*%Y{!px*y}A@KhH?`JrdJmA`^K*IClD
z^M&sDG?16NELw5C(si7L`fJ_jT5xZ4dt1@hYtpq-jptjP7ZvRE=^|)b_D*LN2bklw
zznDYxgl#_6y`|co8;((=+b*O~^eNkV+V*DH9>_ssrmdR~6tZmJ(#9{x_BAcUa&1E?
zf|qBz=MRYF+pcqfUV*KQ5}bv$gU#p%wKbVF!Hu)FgEs-~oNaS2$a&lAlu^21JD#eY
zF4``n*lMxum$CFy+KxK`XG&~mn?t13w)#^jl-cSlAbHic(}2cnw(5_dP;To<5%db%
z_{o@{O55ga^i|moF#x67Hjfs%*KLoODB)OR>v<k*t?gqf53aKvObL@4wzH$rc+=KI
zTef;zj>1m2Y+LCab=%hIcZ{OJ_BkCIYP7ATb$XL+++s8~+y1M9Pi?kEK5+D&ZDl=B
zI&Jf<A=za+I~V5f+kQ_G{|B~BW9a?&&=&C=JQ;0=`$MDK_TUc?ePX+5AkcbjKcd*q
zQ`_u`AkS<AUZL^1tu7rRFKnAfgS@oeEk)xi+vzU!``YqU;`YY&DV^u-wN3B=_ty48
zF)Z}i21_x(cea)k&gi#InnK?xa?)2m1dOx3)E1pC`l)WP<f`|hIEtG-lwPCm`ohN$
z@zAf^3{X#fAXQU)>081e>8%e_VGut0^_4K;tDhc(MnC;x%C7nAchO=iK!1c5M1lI>
zYM~dTPoo2UA^O3W>A#i>)z4c9jlFtn24tT;a}`YN*AHmGj~Aw&NX6g>^jGP%60V<D
z1xpe7rXK+sssCaX(4zEXS3vKe{#73&qxItPXpGTMqF7_Bej>fn<Md5t&^x5p+yHdE
ze#{|ESAu@a_ZY6}h<-FB@Q&(p7h+Bl^;Hy(OxCkhK5$Gwo*o~^^>ZlCb5cKHEl8?<
z+Mf_f(|?fxyXpG1bgP`w$Iw<hL%+WQCbINFPav7C|Klh0<><#-qVKf+eNT9is~<~&
z^gMl~KRi5R($D)CF!}m*p<oO2-gIvl>R(o&u}J^D4vlB^{*<gfr*EANwDbD;A#n79
ze&PW%Uey0W-yplBKSkF?u|9?hW-jZqe*#L0{uKpYO7+2SK+5!Xeo(lo|C@zt*Ytzw
zI90jc)J)&esnE}$%CSoQ+3RS1qwk9cny1}&6s-5QyFxKeAG;MM^o7~g&~72ZZUu$q
z58ADy*mbNOGYsm7?GiqNWTIW%aWp2`?XG}ivfXyt-K5xY5*RvWXV?Rg<96jU;l&9%
zYZJY9Pujhvs7$I|LIGgX?0jf7n{F3O$J9^RU8U*Hu-i|iW|?-(hXBpCd$<&OId(HA
zqw$=bFP$VhZ|6*PB;|JIdjM8p$JRr#(k}T&*sZb~It?P#cEjlK&UL$cvoNw6yO3Ur
zztq}ork7)#UG!1t->^Ho8j3gVN{Zl2y<OH#aJTHv{SMIEb^*ho*kI>)7kZ6$`{U5q
zWEVCFdd+sf%z#fVcI(s8cgN1I2Hv;YJ+lOKo89z0fVtW?w4>3@ekv^j-0i>pozBU5
z*q_)2&?tL$HWUxq#~%e3ZO_wMKE{3>WfNoV<rBcg*?at#=C${xeR910ZhDa%vG*&2
z`IGjybTE->@Aw4cO|y@t1A*!GJ&yR9PTA*EJR-whc^+J*{WMznW!cMdp57!Wv=63i
zevy5@6FSe@kG2IVwclO{v@-i$OF*vL-=$~%HT$OffT^(mmr`z3_UkMlS#AG6dT2J<
zH`0CIWZy))^=A7Els{;(pR@{=?%D@02TH3wwnKP^*=JL3{e}I-sgN|iv`?$UoV>Ds
zxCuYdYx_r(2<x?9JqI#x?I$>)ug|{10^B=$*?$G@hFKH<aW<4(f~1S#o0;&!)nMrj
zY&XN#acFcmG&f-M9)=*wt$P`~Xkp@Qm~;cg$FR;3WAQZ%9|X7kOor(<q2X_^nh#3>
zhT_k`1sd+rvM$)LEDZV~hVD%Cg&L0h3cGs^-_rhIp8>mNJf{rLM?o^oFw7p~JzyBP
z4t)`ZHVP0&8v5o!;h>>24t>#v%n3j_Vo3iJeMb%dEQ6sWgDH}(h-AYhdyr!WR*iw4
zFifVc@kztuEXbr9KA_b@n!#oR45k~BEC71S;6hJ<48u1$@G#Rbf>NqkhApQ-vJLVd
z0hVL1-iS#!ZTQ&+jd=#U)3AHNkV_Bii-x}_U3$rI%47%kiw(o+*?rmIcmb^?hE!T*
zT`_!0YrQf<$O^z*HB5^{-!(&f0s3kU-(QBKb%sUzf!$=-MFkzrhVSj*T8p7)D%`$f
zP~65`+%>Ep4}+}+MHAH940d0lvE5Md2T(c;lA|~(A-QL`Y6JaFL)dJzb{Q5@5yO2$
zPc1|r81_2Ai=cs%yIGjRpWz`}VP!-W-N>Ux?uBoz%)9Ym+!%*M5O;>Dr5~ReK(9Pc
zrerrbFDCK;biJ7=c<12QRww-kzKnD}o@vrZMoCNiOlEp4T+L!OPz)fOIX(lv<uIe@
zsyWR}3<H<TxOxIKkIDT9B4?Pd>0CfQ^J72I3K;vPaJZ1ETZiEnF~e!$dzN`gUrIQ~
z^m>6i&+JP=-v#C+z5Yv?(4SHNChcG(w6}F*=QKdyo&A~WZ9Ukyr)czKljv}T7dt%z
zoHx5{5hluq-A%6tU-lM7Mg7>#UqQj2O+E?90QSS>zz$^J$uOiK_5g?R2D7E%@FIlm
z)yM}(W7zdbgGjHl&(2}}EA<f7(R}-gq=+<0gGKkI1AD*d!C*KXDUu@<_20Bl`mqH6
zm>gRT^eMOeAoIoVw3?neECbL>ey5t4m05S--mhKfAh}}-U4)JW6v_8uKA}??zD&y)
zaM{ddy4ub$O@s0N{|}rWZ;$?WqGdy2v|se0IUI5l2Sv~j#JjBk9W4H7C%8DXX>_RO
zkXZtyD-N4I+yuaQv#%)R)~tM04v`M!TRJ-ONa-;Neb1G@mO%2YQa>4-tM!*d;H{7K
zTTh4tTc?fq0@w$v|Jn&Q#yWI8M2}d@s0`$&^{PSeBGEdQ64y!AI9GuC)H;^dxhdAN
zUoiAz)?8RiInGeLps$r=Sf5{qzC3Hj4dk44_YA0)SZ7lhu)^B=J1E?=Zg~xqdh5|C
z@Zy&Bf=iIRZT*P>_8P3U%RwGle>?}0-PT{yiHOJ6FDa(@#JbcIT#xna<M8vT^`=qq
z`kD1WO1D3^eqb5|jThDnXsTaYSM7kzYwI7vVg8MEAk~idTJNJ8wzt+l&4Kwo>qWF8
zerH|R28Dj>;{$>1WHX2s^3FEHsovSerpz6jr_HyY0L9Culjh#rM&trLADixHK=HNd
z=*KS+Z1eQL8k!KBAJ$@^p*A8ablGbYmIS-|Y`$*<TD;Au6q-t#ujz%JY!h7$m^2%U
zw=kb!vuG1Wm}hgY3zD~OZheBj2AkQPAWb%%Q6SAW=hlPVwaNP%!)~=H(!<beo6b&L
zD^9A%DrO6A0@Ws3(EF?0>p;R))Ag_vtNL>i{64B0AwuH`RdN^fGgYUzz|tAj+4=D4
zyz1avh+I)s*rBgdwR8+5Z>YxjgKJWKNX6Ujs+Fl2(nHmcD`EGU>d&y|O8n+olz8&t
z1PYM&a)}g*@#D_kfKUG1P1-*Ma7KDT1#-d~j5CP)vl3h|7nA^z5YDd|)<d}!AHmPP
z+$$<~-p6?lgWi5F?rVUBajQz9cYyOOL1R33obKlY?!Z|n9O2wdbWr~&_a~j9NaTDd
ze2~OlZw5><=kW{tP2uV}h#uqKI|6c?a~TEiPjEe``9YD-r6_Qz+&BsyrE%kEbDhpj
zeg|@jlf8z)OfEebl3Cp1TY%2y_7p)Ohg<YH`c88r&(gXnmwR#p2J^TDv>iXgZKZ+c
zb3IhNS-_c7^rMhV`U#3fT*WX*p5+FILhl?`RD#Cy-2IWzyTG{yVM;2v)+h|Ajx+6o
ziAL^)GZfmm{DJWB0r&GPKtJUi*PyYN`)8(jEiPwn@O6mxan&C~{~ec6fX;qSO*>#G
zeg}OM!;kMagNQ%>9mO32_~R2G63AOp1zr%}J`jDu{A7Bhh4O2DhEIF>ZeM`y<D<hW
ztMMyuZ3apl&x_G`h#wpa?l3>(9n|Cbmg#6r;L~cLcZC0ez9Mmy-**pOB0u0AB$N4w
zXmBaKUlI%*<1IeM#2n{0Q}NabzJ3j+;w1m?JxHeV6@P-H@fIOK$>lfE>D)YihN%hq
z1$>4bS_}E_h+N@sF91v_pHu<!SNY46p?HngQdL47|G`U)^9CP4Rju{Bo{9@@@lWYq
zY~}5B0Bhq12ZL+phf!p{gTMR$BKP>h5Dcl4-{1_ci{F0<<Uapi0%b=Y@GI+}_>jN5
z85)mxb15u!^KU1@i^shF5V$A&0Lq2+@PqdN<|+Th6ZrI;KeHGLFZkb8nDm#t+vnh3
z@vYy2yym(0Fv2(d*++1+msimf;Vu6y)zkFxbI)NA@A#KTs5-8npGa$7C&A}?C^`#W
zF_3W)j^+c@Rq&*1)lK-R0Db;K2kq?xgokuOCQz78>E9sX5uJ7q5%@LqD+_C%!?nGF
zlrF1%g4I@daY#tr1%<=H8WM>YMxO_lAdG)7V89^B5n=v*fF2ckX@!+2d_%uzlAxvI
zxyizoFs2q)Nn|C=pAb^+!kLr84BEh^3hsEjp*Uev4D?P3ztVrClOfc$fy)%C>1~-M
zbVY;97K;CiI}6Dxp?6v+O@eE=LM6o~^MnaynBOzPr<6_27dFJeY=Ll_67hw?pY#(J
z2^ppt@ae3;e2CU_f};T%<$?nhtyBowztC3&P$*UlsYB6NE2PsG2I_=Pn!JZXbTlUD
zk#KD&NUv~}R%CC5X;g&KCrnrX6Yqpk3(?pwOm>2TlX|)h9CcQIxdPt1s3mPC*mYG`
z&BssarVe+2L3j0XiuZY_eZNPar&==%XkO~X;ehd0m$*aUN4+@;oS*swTFdyWo1|zA
zP_JDAy+HN;g}@F%+8BMo>bd6u9ikplgT7GppHejLRqxn|A?;Ha+EEODzd9@gY?#{M
z4A2AW9YxR&SN}B+jS=cRIu{YCenwgLMD=&H7D`gvO+#a{ddd&rQq;14@rxW&mso&1
zuD&-G>L=CjpN8F3_3j=FDNUXEFVxf3v#!94Q|f=Io-{+f0qZi8BzBDRcNk&%7&ofR
zJ~if430(C0uxl|)+!)(p2GEwVB?W-#8~=<#3h%}TC!jH8f_xRofeBT|pcg)2IlWXO
zCnTo;EMtOmGt6I@a9#tEixU#&L8NTLMY^>+Cb-i&I`MzQDo}Q8qGj=>?m+y#+2t<K
ze=njG$REee;l-8}?f84glqzWN-0uf`2RAx|;lwmk1i+bTzX8sLNsNJj50fznD85X^
z6?ov!+@K}pKBiy_Aoerw)?&!fjGms;G0gB6;9{8{Svo_N$XuexT@n*Sbxp}k_>Y*Y
z6lVMcfSzJLp|j-~%ssj^&M;fnfy-xV-vcRNxEkmcGDDYwD`C8bLF5YKQwxKojQ=f|
zC}R#5qOX>jJPKfS%qj^c;0E)^0~T&Fb>39N)51)n{LCHZ*i4YS%)4{YZ)Nc1Hazi|
zTvw2GCXVuN9gM>r^xb2|lE0ly{}J>(VH7<u(ZdLIuRmoNirze9)}>*Bo-;S8zOIky
zngoS+OdK7C?Ps1Ig%?ij&-CIoIkOL{(CWgP-vG8NyO1gf-PrdC#+{9&9g_#Ui8h#?
ztY;)dyjaJ@!1iX>cwmG+Y;7EfFPk|Xl74I}r5pX(Jst2jfL%2jB#@mD3=+hCI1nBN
zvk8=14`DrMQ4nfkMJk}}WdkYizK<=FKxRMdLA3y3>?x{dKEQ@9hKX?Yz*IOI!9Jp5
z!ALea2tGxz33MRrAUohS>_)TijfUP4HdYGBqilFS8c(uQ!ZDUqwka73Y3w(2R4tvY
zqO*&+tZ8!xTJzY?C@OJ=Eu0SQd^YxH*ezfgs(rY`7Oz2HG3)3H$;)g81+7Zhifz!p
z!fNKjwNf^5I~2-T9mOqgvCf^)yUqSiap4Ab!V2g$vOzPU*TUL#L9dm4^f?sT*bI|5
z^xIh%stD>}%@@({%kKLO?su{^e?y~-O|eAZeRcz-@0>)9JD}hx`kjMFfM~WoOzaa`
ze}%><Q4JM=9u{@3gNYPT!3Z=S6YV<;a$Gc&F4+^J=~Oy+QnZSafT^NE7ifoeMwHwL
z6ZxW^7cf{LIy(ry6^fE-AyXterA6Oa(G)9~KQF2p3xx}!?G$RbD5}W;xg;vu2WN^!
zz8iskSyXZZ>eoffuEC32BDp<K?udR4Kwqb5^HwxI7X4Zbg_oi~CG`AzCvsQ{4G*!W
zAKdp8pQ81Lmw3!{aNgqH%P`?1E~2wNzT#sPyYdr%{0+DR;<BgkH(Y$4o*VeGR5wr}
z#eK^`qQptzuzOIPHX9<*;+gBA7c0I)Pl!123rckz5-&xivq^GTJnjk5;>E-Fpff?-
zrNERP5g*<L#dPssN;rI4%uocaNUWR+pNhp_9EAQgv2GARYs9W}k>3_OU^ghaD=vP8
z#{1$o6ykp%9!d4(55>bf!95bspp8_wxchI+=wtEcR4!wBB7U$18a?9V1<-#d9<cyk
z^o##^1yLu-YudRxO9s+=)dk;AhHI{pn0P3-;lE-BsJq0A&VG1GlpE3KCGl>9q_<>d
z9Kd`ea}6NAk`L)&>L)4v7k&N`I|{S}NS@Y$3o}W^xIpHBr0g=-aLK}Gz(hzI?*Thf
zGKtavQIeSsAO|H&X!#O@gPo9!#s3`$m^ev@6GnJQ@|?mChb5nHhcodwuMCs~Netyx
zPe|TYK;)$43tHi%N*pGmFHQ252w>?FQ->7v6#nA@n8=Xi90yFMWaL3OoGl3+k4eap
z)KDSsX~|cVGs=}zG{J73Bx)vR=8VKZiQIh2&~<1mkQjakO0gvF4GdnEY)^wii6ny}
z=T{_mT|r7EYgU7lNe=%BvsWb>O*bHOP0~ll=*sa$4d_=&oa%s9CFvRh6V(##Ed0JM
z@##imjl};9xLV0iS<tVO*v*8$Hze=q4Af1@U%vvoT{4<-C>@f7F#x+K8A_|_PDyw+
z#?mF3u?Kzkao!)$4<&2ArX0#6iBBLzyCuIIh0J5g<tQ{hk<7UU(H_ZK`nE&AWEx32
zNn1^D)LDAF2>LG4`M$t*l_qRMpPSV8e^7UqS_i>HPieg#l3vohhk*8$UY-KZM>?Sr
zdcM-wkAUeX9rOpqaQ&qVXg3=n)r$cWDNV=$7bR`E51E6~gLE54ODE0;7b7*$qcB$b
zgi7G!q~<>G@UZmAX<)}on`sM{Anp4L=8s6fT?o5Jr9(!bFHzcf57V3^b@GQ^vb6X#
zM9xWnn?p4O=cT9VIawxU3gLdERDT~ZP14V4HPR=|qbm7Cvp?d1cEN1kdZ1l2`!xWK
zx6NWvgNILH4Dp3}m)RZKB0Mq6$%5W1vke&ldu=v4f<|wyz6J#!^WP|&z1KYc7|h3*
ze@4MIQ=0inDjqmvUT_+AFPIP0p!K%-g>rcM#Jn;bpq{cGO4IC>J*EZ1A=w{dc#$ge
zrm%RXY#tAh5}5-nL9fW(jf0-A{5Bma43I}|1s5n!VZjB-Z|($2h&*5<{0)`sskV8a
zNglBViu>gjFW`5Cyw4G$k@B^+kcpBjJ0KG+*M`Ew82Qh3FnC!0#vfd~e5)3E3G%m;
z4^EVq$e^AgU;PvMPRI?PVuWe(NFVrnO8$5;`ZDB`|3+VyTvZP)Tkc5}1vzrlTe_}J
z%ZJe|UMhcR3vyNNP=QIPkYAFauUaljgNYh>)>rVUPQJzjFK)_T(Ifb_Jd!Tb7WuFD
zA>v{&n(Cn3EY4p9=V9Saada<>4}XU<0T#u7Lo&!BJqi}~TJ(*9`hJTb(__p@xWz&`
z?G<J5@*yn;@khApfWMbiQ1)l(xAXD$vLST%_=jAoC|z#wf`JvXKIpETF$Vu$b@LF~
zSHFK6sB6>*VCl!C)i8^j2Y;^%q;%x^_w@MtC(mKf`gv$7-1z0Tobp1y9;QT}alsCZ
zcE?JZx}B?o0O8=^iGMq0P6Oz!Vf3}Be~ZWB-+M+;^4ygD7yj+cET^!T3-geEYFDO1
z3q^lMxDICnn632q4`gPH1{cKGMSz4e+s8sAf_d>Bz#~me!Os}!Nha3_x3ZbV?LaGJ
z+6pnKVy1!~+~rIqw!Qy<T8<9KKVsP0YM72?Hx>afjvY_w%0sMdAB-Jl_f^BuL^gT`
z8k5-A`@lQFKBtxHNp@f!xK!4XY9ljQ8ACM$S!^9;+OyemH;^1wz7hKQ>?I^vumt*Z
z1WXjN!4y5az?yA=`HQSYI`l8G1203el-)<=;$^Ie%1A2N^Yj+2V#5mIc{OWKYo_b$
zCrXIiWX-06t7lDt;BK+^skYM8%ueYCZDHrrs^bnDHVXQ8+06e|!EDt9*zII1D4f~F
z&ZknzZuTWTD4wymgP`!7Ev7{M3w9q}FukmN2<$qE{{91!Pi5=9F^$jVF;6Jpfj{pU
zGkV1KGrMSZoLJXS>FRf89h@){7xoA#yRx>YV9kvUP5^OdgXQS+U@uZNpC`L(8|K4{
zji$x6H`@}6J|DJ&k}JM!`VD~ju|H0OQGd3C-j4ySijvQP>^577gtI}<;A{k&c?x}z
z>|U%tX`MQ>1D2B5Q&s;LuNJInAH39hDTJ3*(B1okq5=BL!~5aHictizGR_GutV(SG
z{OWNOidZw4(%nCPkO#1}v5t^m=Q$i6tzSv0r=JE~1?JCxQAYk3^9zvQupO}#ljPUb
zj{vdJ#u;i`!luI5HU&NIb_(=rbht(z32<Z1(UAmq#)oRKJ(vRvX;94CFJLf;8Ayc_
z!OR6E913BE8=w%$d`d;kQOx0H%+Nt5vk)%CFyX(W@euPZSxI1cCGCF_8LJ+&rZDqp
z?R|n7NcEECOgi~c!91pFib|&R8Z1>YW>m{u&FD6QyTPcY0H%S-qD|Eu#%V7|7xSD!
z-*aYO4)oqIg|{Hm$2ffeuzsd=GN7H=&i8;4!+z|GMpG91GuFWWT^+&;J^pc;k$nuM
zT*mkt+{$C}-T?3nvzjuL`AjdR=nI%bVhpR038RDOMa*K_WS1}=DtK^(nRE&2rA#qh
z8)eK>%2{1y22kTQX1p^<IWw6GNGces8mgha%iN-PR4da;VZS!!br)bBF{3Dj)6Ixz
zj$bkF(bN7lbBsb8F6^FcNV>8<w3v5e<#a&ApPlXq62M-eOim!X`~oBou&={F!dd4p
zF}D%y_jMqL+3rA?k7vses5VIw*b%g{Il>P65v?cL4fK3WWt%^N;%WA8Dgn-A&9Y%B
zk8LW1{uwrob`KX>eAb8_1GgifP|UVd4DvE-eE@ou?Ds#xnJV_&5GYi$59yJ2o&AmW
zH4W@3`U+Yj`_B>dnVQ($bg4G8wY}(UVJDBn40W-tw1d0P=J4oyz%Hin&_njU??4{0
z^6k*?X4Bq>{$n<U@>oyUKX*Z)hi%yppPsVMDX8|0&D{y^Ih#rK-Y?i%2e|f<ZM_3W
zU$Gq<F|yYtb`Gtk->`Zr(CcOIU4_hBHvdPU^|3Wn&gCcC)dY<Q(KA|R#fiTB9fL^}
zO(kd2M0fUrTonEGBN}gt#!^V+p=kAXG&+l`{{ZGe@frH<PKrO82xp4KF4urrF1||#
zcN)c}C)=U;RGhaJq*v^k_J5Cn3W>EGTJ`u)6Uj+zX?fl(+4Kj7ephn)0HE3>L$*Vt
zOERevMjzpSI|oFMB*G7pFD2Eh;PV>^HxyhymgJChlZH$hfN|juKZ<H5emKxYQPLF~
zZlHJ7K6AjV*+uK>wHva~z46Ir40w~PfWNobIRnplmI{t{$a#S7Z2J^iPE5fmjK`U2
zq{oprqoc%?53`8^Iw8#5KLH=gTtA1#NXESxTom);YV^f3EG0G)Ow7{%!dA?(h4B6a
zqaOj$lgyVCM9F5p>xMHqOccE;Pc!1Z(9dP&QCu#M@p}e^GmMiDxO`@A7Mw3&-gkgV
zA#<&drkZiS2y&L`&jC5d$n8PSGwP*)zQAOB3H6JN={u^Syu>6>B(Ips_!TmjnJHAz
zQo<~vlGiKD)Bzx+%=eBkQO0bitLQ3ojB>Kqn2H@}EN2qVLa%~ZcN2}3jLZsL6=P8c
zXX+VUC}!>!^8=kSy3M$$VW@%0qg8SvQ)6m{8%>OJ0%SUv1p|S7kLjk}YA0hwF~2Tm
zJ4FZYGlt)R{eaoc1Lh&~z6jhS<{CXDQdx%5wppwTJx6lbf2k-Tmwic}D>}oj42EP8
zTSfI<=h?YyF_ug0TiWoKu({>5|1V>&QNXpFO{3*zH9O`fXw<WrbYSc*t8s^GPNMn0
z$<T^F!WtTD6#HTu$U*k^(@>3OBgz33!!9p?a4b8HYC+@Jid}Hz5S#A-wZkk^0`KD4
z92SxZY$#rKc<7kE{2Eq{vVp%sF_E>Xf<_WMk{-m#>>{egNnsOY5Ix3Plh4Q5{$r3l
z!Fteg@FW{%2}`N$UMfgRW7~}AOJ}3r!L@AmB4t*K*r_o<Im@114$KnvjsyCxu#L5F
zrj!jfQQo?Y{csxQxQ6}W516lIFH#YB9ouvg+zmGSJQSPR`l%Rb3p<Rq+jrOwissy9
zhfr9smG#*Lg*J9NosDg02X2902U~LmKHX#QEro}jZ0cs9bg}ErAbFqtA023Z!1`RE
z^~Xc@?=cX4#BQR4UEQoxJjhG->RVg|uh`F%;P7iUhOVMFY`PuLdfDH4(D;^JaS@Vz
ztmPDtcWg@_`aDFR7%*L)qBMGD28vo5p%)~2wG0D1AgT}`5-y5r0v9LRtEKqMA<+UV
z^-30fM;Xf$(MOc1Iwg`)t|dcsu@$0cM9V!v@<r{mnz<+nqFT61qOZmPyIAD2ACeU!
z)Q#if7bQ}Fs!AkKF<G_fM|zN67p<*9UyVpZhkt8D$w6?fPP7ppiZJ0Lq-pd6-4qS_
z7c%vtU%!Dfw?s<@qVcxqLMKRrXuLN_qlo(y)72yzO>gyP(MY<lTSN!wW^WZ4QsG*g
zXdX6|`0D71BAD+G4W?~xmuL~KkM4^)UV(cc`mqd>4@EEHp=Wv|x_%GziKuG{NRNnJ
z1MH`w&to9kCmQ66VLOQ@QJJf=IEhX@x`_Qr#8n(i2^cr=^+Awy7e76QfqIEQvV<jX
zamF0XjGy?xJviepW)H*r0C78Afq~+X?JyK1{_Ah_C7HyLRIhzXyd)1AXT+l@yl_GM
z<|t&!#I>ntyf5x@px;+w-T^PXq+4lb{G?Ug&<~LAxDSK-rPCXL9U;AyipEH3oGZ8}
z=~{|P9+Wy##y(m)za5yd(jzwT_mH%LLRs-r(_#fck4TvT<c;(h<^PkVg;ubeB2Aze
z=`ks$8aJMF<OK}-q|~DbBvtCO7ocg<t-JqkY0dkrh42rb(2i|+ycC@)ip*hYW%dtn
zew7~`ieBwM12St|sj7QJ#$(|8YKo)a>~F1Gz-)X=rEpvS84rbRYO1Q(9!yIGW88lH
zz2os+3~J{h8rm-DJIK2+-fEhAW_&Ts`7>dwXhxW2mOu$)cF?2;F&QmzKA2Iy#g!Az
ztfALv1aqHm@JQzHWy;b;F+=GZKgcAs13HyyJ_Bpn%tIHT<ui%2gg(!F^A|`7(@guX
zawcmOrm2S6lnEbiF#~6VyTd%V1843tOIy+Sf_WqXrW0F6%b8$Sx&&ZxY_jM76$0^%
zdNc$v-6kp$3uf+&f^Imok;?uem~)@Q=Sap#x#1}0$p2t7o^ksak_pTbdi@+{?uK9l
zCzyalD4b+o(Ca#tIZxS%947f2aHkpJ|Mhm||217({OonkJs~k%O&UXu9}=m`aBp%&
zLJWzZ5|YSZN@d_u5lOg-ym~ZMiO^~*h>dCzF%${H!}UBdl~4pVSIrTMPd!v(uJ>K^
zm;M2L`P}naXRW=~cdfne$vJE9wNJvkw2;Q$gzyKkjW-D#5Pn=UJtl4>f~yugTXHS@
zoJi({w)5gxAkeOgVP)X1iNrLxxGsV!(1RP|8J7Uc$lVB)a=Le$F9})`jGk|#a=x=~
zB8}%I6*R>gWHbHP0AveonueYor6ucOaFt$kg1=&Q3fEIh)Yr+J|E^G-j>AQ%nybR^
zO0}R1MsAflgWvR6t+sQA;TrXb4Z`o$=NV90t2XJ59<EbeP(8wZtB#kpztK8(M%#RC
zJ5L!4w1NDbU7+pELPr;BpYuZIBJFhrVk*@9`Ifv`TZx<@#~`&8yajoQ_8u1~mueGu
z_xm!<5(U5CYMVLB$kP+Tx%YbEWcb~vC$<3hFFl4IzT5T5&0w%Y_vgRrvP)mF87jN=
zV4flE)xEQzxnFPd4m9ia?<6$mIsCQ~?#msVn?sm$$f0yQ*dq?vQxU~khwz?%W`K9-
zBg~KRa9FqnaXqAQTpq8Zw*3CuGpgcsrhIkcSrzW^aaqzI4ntn9!-#}wt~d`re*(S-
zkK-MVLza$*am3j57?a4RoW@4AZw~OGV{%r*c+|mgfX45wNApJ~xyCm-<TlO|?vz5F
zI6MRaB(;i!S;~VCa6Zw6tNFHDap*wiU4E}_`r(t1&$!ebR(WDRwrXLPSaSd^`C`*K
z2<M23FF@vsU%8f3E`H@dNU&A7=InvaPEpJyu)QLPms+aC3*P^8Ow4rxIVA$@i2Z_i
z-5UX45tn}kS1VrPj)iRKRS<ewCtMD|?v;pcgtl3<!vl76>3G7Q8H-DB3PKN^{|-i?
ze+o}8v$O{2_7h>t;Ps!U;$08Gyb$jN0`#S*=N&(<MIU}G=QAoD0O2e;#bv5oYJCV$
z`Lyj5c$!1OSD><xPHX`3BKp)3+y*L123JXwZzylSniKT65Rwb@^h-eeOxiU7UL?;(
z7>{3asB#3XE>W5n8gJ3@AgJCZH{N-7m&Q~hu6q=c3f22m#k1%ClI;(K@Qf%7@Xu-c
zTm<`t>huicYc<yn>;>wfbaZl&dVLn`3e|<^*4xyrGbdZW3pEQsk3~Lm-W-hHXEWfl
zUOXuP?h{eo8|0}d_lIy66(+vvc4{`h(RmbQ0q$4i$7yaMwXFpFVhZ4ylcYr#AS@<l
zu9ue3ZO&F#P(F`SDSdwzn(JvAzoSz|>&-AIr;W=Ha?V!T`xKtGQ7_JfE2$lq1$R@2
zC-787C657fh+?uaMkgqfD?=x#fGac?X(~T>f1x%PfOd&$$3b|R`tTJ03e8xJwyV@5
z7IxQYG*`c`(}2@(e}ht7L24+(ik>~nA>RbJ|DBre0eMU-I0>mEzvVEjr#4*cdrITE
zIPsjuW}|B_=#v_7v(&~t5lpW7RXeDZAi;tAGIcs{OWUK4=2e38s#*uIt7_X?sQjkd
zc#2o2-i}1uE4BF%Xy$1-qq%l1wV(O`v`jlZ5ZrF<DCc!2v{SW+yGFZK3e_iCa5JEN
zY1qRvokGLvT5#VQjNc%pQp2abk$5fs#TJCi^(<aADblM5ev9?f;c!@@M?b^Jtka1z
zlQO-SSIf)w);WCd+o&JnJHuu@<t(`E`r6@$!mi6CSo~Z6d=8@ckKU>UEOzNhT@c!C
zz4#^^?$tYR8oW<G%-8Y{dZjDO59rhkb_ey|T+IAYPuT^7YW*s|A$VLrHxj{|&@Izp
zep+`fLWT9sr8(eH5k`DqiyGj480-Pzpj$ja46{T*625FMVi>%Ge}jiOErD%>`+c-V
z=2gQgDr_ULhc5jC0~5Xf3Hly$i=&Kf`2ld^^70YYup+K<4}Uldnj?0d1j0yj1vGO;
zg^dSve8XBak2W_0M8a$X+$46o14&X4&s~zgn+DY}`=$eEY~P!JunJx?8rPQdfbl6M
zIRDrq4DtyroS>O9)DPzq(-)#Obvj>4lm4*~^0WhsAxVD}3NIPOH!w<*12@cr`ze<n
zfU(W&jE3x`5jg+nd<$ZnDU4iJpChUR0J2wL)4HPU#*nE>8wWY(neg`x35<`9!Dq0q
zIV3CD`eDD&1e2G^$IJ8=S$sxn*7yl&ws?8{g$Q-ao{;8iW<4(-FSC!?*T-V^HCcSR
z#b>6cr`qC^C!~3MdCC4SMO!B?FPy&p$oS`?-T&2Lix;BcZ+7VZH{<_h1nmu9iJ7-#
zw|-7d<-J_TCh};p-r9bxhOGB{h6H-Y+N@J--eZ!cq-J~fv)U$Rre}C(rh8_7Z1tR!
zo}T8NojzrvEhA}+6*_62nO0k-4SLC0<MUHbsW>zo1{^vL2OJITsizudY;hhK9hwl=
zH#|19z1iaP<|o$vG}rO@P&wd?!CAgOsyC3WrZ)DldtY!|Fhc4DdNUb!N^Nf6XL2eE
zm944`?c~Y1j&3rI^al1v*-kI(?IOLA>8N~k-Z98-4s2ZAL$29DF0!bG+~t5Wa+MD*
z>$-jP)W)-?wX~Q5JWT<9ruW;MOkTcTruMkx%s&1mv;Fmh##K$*2lxe8y7^dry9Jp1
z#*9nq-o3lk<nQZaG9`~4>+fgnmRH*(ueRy7T4R2%oUW*Z;I^h5V2bBEipdH!QWQ-0
z6vCPo9)k+CQk1r6qc(~X&$PXwAk9{&qoQCBh(hj)@)Ohd6~zI+Ow?6TIx_WElwM5D
zih`wgg)EAK`H(`$HkUK)q1f;BHbyy$$1-S;F@m}}%C83*hfqI9c?DEtO3yH3u~;Ol
z!;BGPxoi^-vPw>3Qf{vdH})1{t9&)sm<^IO1PDEw%Bmr-+$G<QfKsZoGFdLSF<B)I
zksz03EC{)Dlxrg4tY=4A4+?Q;6eDz!i=)7%%3839%rX?x)*f>9P*(Pk=Rn0+=@yOF
zRGG!(raTBjF+tKb28}nRH3n?_ak-t@OVSVvrCb@y<gr}MWUH(Lp-yhHe;jnC%fh%f
zK($PkOUp0@=pttiW2c_-94O*<8xFCbkDNLj>=}8G*`D2`>xeh4))BBhBe#K2*FdR{
zgmjmT9SJrD*ArOk*GtxqG<FgDWrtD5j^daM9cAon2*z~$qMQr~wSFiUk21Q8L|KUz
m3hyItF<T)U#~VANXBH4uQ<}(xc%z#kysuH2Eej%y&i@1IIA*W_

diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
index 4fbeb5e0ca08e3a285a09119ecec0691cf0dc821..8b538dd3b3e8d5ec467f841bbaddefbf7f995dd1 100644
GIT binary patch
delta 126355
zcmXtg2V7J~_cnLga?AF<8e3vw?6D@XM3WdxEQzt##FnVBL=$66vVfw3h#)FOP!s`?
zCN_|c2nvWarAbjyiU<mVs33mN;r)O4nL9gY&hwlzvv=ptoH>{HM-$5)PIT+djEm}1
z%l!P^JKm;;v73#})GeIN|NoC+q`CbC8-`)SOq>lPl5G3S7KJP#lC@#PlEZJPkS!f1
zvSC=s@XM&NvW*2Y8(Xnt-KM{&&B>O8;>R9qMGJcjoh7lc?O`h;dRq^XSfU@bP-<h_
zT_Q0K_x30kS$eg-MEyg~mg6P-42!Letz3{uLq(j8Ei0E8+dT}n!@K>t+}1{HJ3-w=
zBmN)R8Ac=Nmf^9&wwK(=O+a%nqnGqb_i(Y@#O(HHxBZ+c_81}l%o?<uvH2fFEVhx@
z;NPGQ39g+=4%bbkQd~Q#8C++_lft1zB3xZsd0bQ8lD=yl>4dja>+w5;_1H<RKdm77
z$}=pknQ;QH_hRYVw1%#tlcfKP^>->VACu_pVfy^VcmjM>Xp5^jh~!m{L^r>W4A)rv
zFR^hOL#>a#AoEu{$f2@$x{eq}`nLm!Vb?`MT`-g8)JBqQTSK3}J5QfY-x7A9(MqtU
zWdxglh|D(?kk?yV$c*znQvLKjsphUHNz`AY`NMb`kC<c{p{e_cVNVfh#$=Gr!7(J+
zIDtOT$|RGKn@B&QmiV*#Q>)-dpOXfQttj@bB&8v~)bQJAGQaFQqHAj<!*#o;-`n@l
zwX}gGJA0Gn_P<ESJC~fOy+y5xtHhJvpCq@QQERtv>2v?BG!j2YlF5=X;&1FEdC||D
zjTNFkr0SxitE&&Gj_T^i_L)StX$bXW)DP5y)C__}_>+9_Q*uR{NBXZ<ll;?z<kspm
zlDAip&iP(6TAxm#YiKP=BG%F8QZ=zfWI*3)!<xvWxH>XpcY-K3Ws%Z&zb>V&k?6z?
zj-flyC0R>-&2uEloQtFxbe0&nS>(iz;UwwtExDz6N|Fz{?y!G+==15J#88_+E>1a3
z3|9LfGHmTnmD>Y|=wp^fVo}%d7Hp!=i|2HW&2!R>?vk(Va`csn=x)i$SaKS<zCM#a
zhh>qA`?|XE>s!*9y@1TSD9K7iEb(YvNb{IAlA2%KB?F8X`PDOrt`lO&m7uO4QsyiA
zJiZrct|_6<4IZS!xssVIH5q>5O>|?{QtPlG#3qlR*6j22t-lyYCc8f&^Z8w0-)Mn!
zG_$Ql^o1)`0+-P>p(iO#J5E=Hg071qNhcwOTAe<o&x3v=(t@tr_GXvPfM3XP#eQ<)
zt7T-2{fi_Y^dwZXk|bU{wHkI3cF83Anl?V~y8l0|rpjeZowxyO$mE1i>GQ|$Y0xgN
zB%&YlN&evj(){%aUHPuToKZuhXLggMvy{vv45NN?n7k!6BX1GvNCl0Y$cb8&eTn(+
zc;XCH*wFpIn<4O37wVbsEozu@pTK(qNq*@WeI6|%iliMh)awqBfp>-Uc>!i*iOnC`
zgk5}uG%qZn&kLVZt9JmI9R4L;lkJIZ?KYCD`;wKj&(S@r4L6%aJG6A|yM*Y*+tKyb
zVFK({k-R02%nPA3bWtP7{MmZyN8f*Fgx(lQvU@&BrZ|&%mt!O;J4KRh2g&^295Q)@
zCFajAQR@f^wOZR#$$;hux-R~Xlzh9KIF>{v%PUDK-HEQlD~URuBc1QP$nXbp`aD@q
zjxJ3hN#kAm{3w*L=UBRiy(07dvgoS&ms*q7(KxM6qtAn^Db%OLnWVbrC-Uo*BauqG
zlhXYgq~!e{=~TCnoSQ&B@Lu25>POefH_5r{?@7KVj~KprO!`+6$z<q<gv$S$x;H+9
z<l$X+fJ#LcoBp+ufpxt|X-Xfu$|n%r#L3jxpXU;+eig~L4IpslA4K}g_ar&8gsyvD
z5Yf!z^x3kNP`Y`fDWnkA^>cD@-)s8pJB)12*-ehlIYRo%#T?E5e{>_0YyYGH{OLcU
zn-E4sDPxGJkCh~SyM8dsGwAbA0R%R0B~;=EM0zQd4787;YpR@de1qsZaVlNiLrHVf
zC}NvXM&@toNOQ>#Qo8@+8>!(|*YEP1FUfHAkJQW5cKSSbDGjOjGlHoGlHsx{0#EWL
z(!at;@_QKR$6TVm`d*{fzhlU7s~gETbr8>}DzZ}YmQY`QPMm92LEmb#ZwmoLiwPj=
zdT6e@Kmer!f!95y>w>Q5)rJ-1#1}V-s9_<Y=B^|nc_)#6x{Oerzmvqzg-}BW(AZ3w
zMsjN`UHe){-n;9`Qt&VFSeK0^ueZk1b$~M&czcB!cFmyAi#JpM;_L{#?jMq8FDHt;
zRYd(y*SzK|vaylca5|DSd`_QxD#f@4ZeVeh;472bWCoF2&kx(;^UhEnS9_%l*Y(yP
zso%~X)PoU+39xk-8Q5}{4FB47AM~yfLH=10-5(bV$cfw*0(&+PY4D$<xw3{na|*f|
z-xHg!ftb5-q&f08>dZbpX@35i_^tU;$aj}p36S@c4E#EZR09@~kF7JvYllzBQ@b&w
zy3>tDD7gkdO`9pBNyp+x*Z805i{P%2fumh3zMWVyW8^T2Vdc7!<f`F>P1Msh1dAG}
z&AdnCihPn_MI{7_Mybu@>16WC34)!*{4BNkIiK7bHJp0<N!NWKJ4@7;yY3aIu6sWF
z5DokLvjR2PNGu~(Vw67FCC29gTh?J5zRll>&vOTyL`Ub@H=%X@LF)7ZZXb{ftw-j-
z|3wu>__lZ<-HNN$t;Ofx2Gc|4kEQetZy)&%a%+GEl08iE*BDn9=J5>_$C)*>-tc7X
zpTS8l#xWT+Z$`WYg%9%(-<#wFqnZn&eoW|7SUt%oMxf`Xn5r{?`!jp26JYE#6L=S@
zXBh1-@HK$3bpZY>qhKKnWd4zXJBW$0q6lUt(qr!&^W*nm3t^-~z<r)+o&Z27lleC~
z9LB7F0`738h-U2w=I1zYMlvg6A-ur!`vjU%OgcRPFERo9tiWGlJb5%;X67FP_Z7zH
zA?#jd{?I@e&8(prI)*vn0=8?6TM%lo%#LK3k7I&Q10K&*2Sb>^ETZ`}k?}kR6G_an
zw_r(TcF{zX!rTag=5;2+7tW+IgThhdF&_&I=D&PK{yFRxFlmc0*moHl4{+aOhQ|R>
z$TY^n(-Nldd~laC_fi48&-_61S{burAc}{~%^Dc2Vs@#(@`Sm%AAlNW06k1<nKhqb
ze4jB_&j8oJB)38MoLN){vKNeP8;kj`iOE|HX)`nP6^fTkN(Jn;FqP5hZ!07I2Etd&
z{MkUXF?Z@wd(Cit;pkiD`g0g;XG&k9qa93DG}_)X8N*@TUS#NnHV4rGcX)VE^ygb1
z_VMqNZ)p-488;b_O+R7EwMsT0h=Qd*>L<hOmT~LxdFzmgHvd!qaKxujAG&7)I{2Bv
z6W3wmFvCcO&+P$YBf8P^$)8z;olY0K*w7ojl`f}cx6Hpg2-!b_A>r;wnEz??QPM-}
z(`L+x(ml+|4iUzGFS81Byz~I$a1GsZV(fZg8ggc4DFHdiB=*LS^CVM33)oXkP8n3%
zm`4-g);s1@BFG#?!+wUQvuN$N@co!*5G{thMGJjUJ0<%45C$MpbY~TCNunYL;Ic&F
z&Df*TaHtMgH=v>04;!G>$6+?;h8p&xVf+9FnseS`A1&F)ZN}AwNnqeY5c9=q=*BZe
zf1{Ikn7~NEM%uzu9R0r`;L8?(Q2qS|^l0FKJaluAEglcj!2|!nWHMyPPS!>=ly>6M
z&klZpo>_;Dd5C#u_&o{6X@viMI6d+sZw&6JpXb7l(S{`W@%i=;e4AffO~CcbZnQEP
z(?-jeZ|~Wo_4_Ty;Mh;OcF<oI_aSuFuKF50TQ+}!)*Z{VklQl>&gk3$hTjZs59ZBF
zka#kiWD2O9VS3QsJDhR$$kXYqUH-;0T@J@FT^`3XT`ngu<fimG)8%?9L#}s?BY&GF
zbwhmtu9g90y!+7rSm<MS8LoZ&0DYJAJKO^UH#ll8uEQip030#JmpW9k4#vkj-G*d>
z<yXwel1XD1!`W%;X;U<7oek*bocP!Ff2K^oW`VMY?;un^`eqo6^q>7VuA`C$!uSL>
z9r9_DX|FkFBK^$l7z3@H?U{jY;BjDfFGbCZInxSmZzgRoJo8~r&~y9@b7lu9tO1Pk
z3johDrhD)rf|)|VNM?B>>|S8j2+)aPS{?y^jd^?ynz77(-@xh(#{X{s(ipcWXr?p2
z1>h^X%QVnW_Z}n5gWW<#L|#@i?JfY+Fe9liwajQ9ny;97*8y*{GI70O@HJCSYr}ma
z_5-Ny7bU)d!2_b{Y6y>uo|;g2iZn;S<|X<m2kr-nPWXW>Smd=HZRbQz^MJc5`uK0C
zM2i~!gcmWQ657_Ki>^>C<ECia8?@z!loW6&5?$^MVY$dUm%g(KQ6%9Xi4I3#aH~am
zEvVItb}2AkuSBvf=!~81mJMKYv`uCKaIwwY3(Z5eQ}EQ3c-amu2C290(>~BVYy0(f
zXa?F|nu;RI_JbR+bkTOuT5zV=o}CK#bz3(q)ahojN_xNf7NC!k>rwB!c@X;j@%e4i
zu13i>@mRx1z70AATa(i0sXry*0j|GIW&ZD8?Dp3j^uPa!<zO9j=`OBArJvwByuA-7
zM*Tp+i!Z$Jn3s%=rHSLK&#ExoU+<a*e<$@`Pb=aXVYGsod;C9Km+qp?*y=tn(Y)dE
zL|iwoXadDnue<0(ob;<7(WQ9ly1g)(ApPrmG~JLYsArkd-3;3DrTz{uRw7N8f#|ku
z;u2`Sl-(Hz6?<-SC%Wp+)lY!tW##aA>VKSa*GpJ-SG)WKoule;m;dkHk6>O<NZ~${
zLt|Xde1Z_5q=M-~53GmGhZ^udVt(?$H(kZl1)w-8D!mSC$3!2T1EHsASa%S5i8L`N
zd_*%k;nxY#@4Z0gC-QAYaZ>cRH32mKqTTaQJuRxg2Gs!3>PhJMS&{caxOqj?F9O9?
zQ3Y+N^F*uM;YGekody$kMMbppyeHD$1FlGPlJ@AuqLpJIEEQGJ&h@_NIo+V;qEALb
zSRoo%2+aqg7Zjs<C<<?|qFN<d^(#mpi$0|IU$tmwD>_pn>OLOAI?>~G06rCcTLGG9
zqM^e9Xb`>h2e+Lq{~y}yZ6iui?6Hld0orRDHy7UTv#o4^Gy82<((?P9Z7dIAh;8(5
zfalwWUq-FK)>|sW_kYj!=Q0>9v~4^OX|b(8?HEgJzxf5u+_#-hyXP|7AD5!2u&rJL
ze5LKpEEJDyuP(+QRN3|oM(v4h#izhk+pf6=vRd0=IjGgyYNx=bdfS;BLH*3OkjyvQ
zGDlH+Zu_o{p2$tMp&HOM+fE$-)fU^awDoJXJ>iO4n{8<ey7t=kW;d|Cwe3kUhj!cU
z_aS^|%gCYGX<JK=GkdWv2K{vqZ{Gl+qd21lfPG?TTEZR>SL9>3oW#r5qZ0?k^MYW{
zMf?`OGKtkyT-*+}!{XXP0Nur@o=`m^-uXAo9~JkML-m+={W!FFid{ZK;U(@p8-Nqy
z<OrzvipNnP?xc8rA-p&x{+s%8TD+tbZD+($xR)h?Vxt?p2of*70`Jd>w@`pEMEukd
zfKaR0e+&>|;=EC)Mu;7Hf-O>9?*cEP#QF&UUKDSnZRBO~#a!G1SHyku0EiKrSHPKT
z;^u*1ixb}t13X?_(*r7rVkdGtN&J@fiz(utvDTMd7azF+zzuPz6keo>H`A)>rr0_n
z2hv;O;VDqf6nE<2ca}KW7Dcu=W-N5>i2p>iU6Lyf{|YpD;+`Jxut5Aa2P${Pn{we=
zq4?MrU?~ziY5^z_C(%S*Dn3eK*D|sC0g7_*^F3gx6t8=Wo;?u9(VnqN{LFd_G>^sI
zXk}b2ZXXDp8gY6tOw@_>eIa}*PQHhtL9819OO4{En=vFW#3SUOX%hExhubg3VQ)~h
zh<lc!?UmT&AOLORs?8vKBR)0}ns3ELx53#V-uWwr>z#PnNvPOKraz-)zP;ph4S;(j
z-z@;mUdh)z;oCmR?im=%{gPTe>^eyXhyZk!Jko&1MG`KB<{^oAAxs>WI2FQ#o8;g;
z;EqVXnF67Q<ojr-9G6s0h6PVaY$XhOOMGa3?IRiR6{vkBw|lYp{rO3DxC4JmQjmfH
z_Ll^Ygw7es&)8N;0wf>i!F-^ErDcAQ<ikkRLL|c`!_s+4A#E|kBvogi87>LF1`i`8
z4q@oa1&N~o;U&rLC!oG8`GFpmS0$h2fF)WYFNKHKBufy<wMt?o9TaYkmuTr5O^}@Y
z8~7y2l4HOpOXkyRt4N|cidwN`H0?m{OOB3*-7-mAGn}cA9Qz(^m6EVf2p>uU0|9>|
zc{mo99!q|)!Eim1T%{OMjbti4b898XZopAH>B4vvR(t8)F_7+&Zuk{W?UlZwE&4v`
z<IjQEFFiz$4<~73IxIO$J7$3UkTi}$U9Qq>3O2b*7p;Tvh}8c&EFF{nB?jQQ^d}0{
zc}ah{hjH?jE=+;S326bv<9ww%5`fE<mW)L$&nkT}52|;i<7tU=PkL}RoGOwI9}7gW
z)Nc=JrP7%cL%uH^HVB&K(%}B6RY<j8z~2Ybt+uE=lzLJSr%HNF4erO%A1DA(E%m4H
zS&h_X1!{HDF%j_asnqXx;GRkQ%!6iw)GB1a(hKPj8*n#CJtIKVBK;u)z*gyk2&lf6
zPFW2v-bice(bgfIy#_seC#@X={ClaK0z-DPxaTn8AlsFRwmq_M5U`L$$j*>3QugE}
zEJVqMOn`-pvSl71yDaN@5#xJBmSOD&(rDTAyQs#<o=IUhR#r<p>Nwe|9uOwThQ*<l
zC>uB%ZOO8Yboh}XoAN7!sWQ(wP`M#12!}9T=1~CQP1zO-PG-o|r(ri!ruRbIZP^u^
z<4Lk*-6`IZBWrz&uP|4Z7(~y%d|C6?s20eE(szGP_Gl!ELfJpG+%J}`sY9(q)?I|r
zyDwYV1oz8iPPDSCkeM!{_mwisLb&!&cJgc3eI%Pz2ZK*!xA&k{Eh`QIOP%b4JQ{qN
zH=U<7$W~2*uu&GPpx<AUY<(iUXqFuwhN4xLN}-=uvVd=)^G2q10OGA|A%$Jv$yQU4
zpi{Q>D|lhYemM$4dv+=X;`gwfHE?t<`|UY6vyc5a4#j@9?qdL)*pXRq)R}!|2Tm7u
z=pVoxV(-KY`28Jb4<CT48#{Ry@JHC&;Xrt><w+=xu@|D@%yCwK6~%S7WE{Gk%I1EB
zBAvax8N!>a@pqWdWH|~QX0fixu$0Z}=(l-?ohyaGTz36W5azLI-=TvA>}=Wv-eqqc
z1<RTuHgO+-#jKvT0i|sDa!Bv9O|CFs!G@ir0cIBtK<yFx$_J!X>|o-4!s;HOt(yJ7
z0q|N@JrUe>tcm8pdbXhoeR;;-4TOh{Y^29$ee_n(hp4o$&2)y)%9c)n{%h8Fm`0gh
zx*i7F**#ZL>tK8I2l_pm@jD7Tu4pzi9XRK7)b?;^={9uad}*-vaZ#Bl4sg9r!f7Y&
z`eqnE$bHrb3ocyE132c&O?3zSFt@|H1gh>_`aV>TaDLvPImSJvaPM($`E}U!;_O0E
z^XB@|uEUq>b`@-X+*WT0{kiS5JUGp*rj1PiC;b<FIm;a`fZIXbr!<2Fb43(>2;rua
z-Sga!AHj<-&Yc!z;oLzfJ>eob*GG_E;CcqZi%XoDPF62-OBRCrDwkV>BARnwgU%Fk
z5}HFwxIMR^Qp%l71iXxk2|-cL9r_7&E4khS;phXd`W?QAD(?7T;2v{d(b}$>yZAS7
zHC)R~aMp2)Zd2^xDR*c*qz#<QVCXb*eIih6;&yESzM0#61NauMFC9y?atXA-XyelA
zP`u_kzC+jAxnIb92e*AbI?>5BU4a+xxg-jB+w*D{kU8)_-3Ikuezg*9jyy|q^nQL=
zJjH$v@E`dD=*&+mf$BkiWixaR@w$JZ<H|36451q@Y=k9uegGX6d+;--g8L|ca~^QV
z`Crsf@#JUt0C16?ISax|{0y3&uJ9+*FkDx8C)(u1@cC=u#WmiWej#!EJR7uG<N2&y
zG$!)F6nIYJ7t(q)h5!B-EM4bQ)}VHSuT}z)#(RGa&71r@3a{VdM>fExOn&idkY@1?
zb5Og(d!>RjhcEjEfP8)+87$ySX|H#WUqI&_g*-b1hKhNe5#K?Hl|Qu*ChqeJ6;#Xk
zA&;O_$=~aa+5<kDf{>5+;U5BD#Sf>m!zcXhiKtccmTDBWyya&I>-Y)wV5#TbE<*T>
z|D2+pjr<!rBYDoNe*jq%fAuWdn)y<CcDL}c^)S@RTeA^mmb~Vb2T;7>w-1HEc7A+4
zNIQ5}S`l>e@9qQfp7+o~XfMp9Lr4eVZw=h{5jw`9?S!ysGT?r~pmk6=Dg2rSXZ!`{
zFX6>$!5j|r0m9$3q&zFc(m_&?FhYbPSlDijfli3<zBj7pg=w@e2ovmSs}wF&XTVaV
zaF1357lcmQ#$FU|bFg$t2%$~j6=C}4P`N5>?E||pg5eVSdrfe^kFP0C=$DToUa&s_
zVUo}`2%5=4Z8&Pzg_(3vkt+1?u%enS*wB;erl9ggEkg*L34@tJAMC^>w*{MDP|Fsq
zKB(mg{b-evD-7BT^Z7zfJxB|LX!`E&35O2>UMQR_L|d`&FHx5WYq|k<U%0Ru16wBO
zXlGa<JRS^{N@2!DioHG*@=D?UBOzolxE~9J-tg^-uptvVH9|MKy=sLyTHv1wPdcDd
zFPKA6dnZH%fz46=?<y2W<in<53_awt4#20Q@&lB_a7=EfL~&d`vk5{^x%v<aFS*?<
z0KDb<R6KrvC*&y<!t|A|)W8crxzq=pIVtDqu;!H9?1REzo--7{)AIQrqjpBVIu4cs
z<!NmI1j)rZco-tz>;u=%%PYQz@HPxWC0qUhO|N(49Q_P)<Ui0Xn=4;10!5zO<}C_q
zzT9~i$^!Z5=>Xo9Z!@B}C;#;libDBUEPzGwF%*@2Ag`1`_)vcPA$tE<{!b8!TKNJ7
zuGPt7=vexxJbOEedU+VdY@f+5-9*tK@4rO~6ZqG=yaQeRaBVptAN^T?0k-z7i-YLn
zOWEkeC)-xQ-F_Q-qv2E6!BFbImrg1NJfXoDcsl_)gO>M%g~4%j)<0xFjqcC{9NI`e
z8}km=VPhz4GkohkaE_QnPK+!W57a2PanK)Kn1~L1KEDS1U;O6^$(Nt^UIDr>EeN4X
z#vY&`)VP&&G%|hwg+V6_yoKvTce)e5Ug8g(Zvt`dBl))2W8<eLYbqTl?kGwHodYwU
zCgVfQXaj0KjF%G1rx@`p;LkGkYat9_!srW&V2)?X{x=-XvSZFrJ1DE9Nz+AkDid}N
z$!^kO!Bxi4lkTug<BT>pStZ3n++_kq#E!_W&|1UlA#?G72S;U7DIj=EHgYH3Y%-M*
zs-CjG&ro>DR(Qea30bTFQeT<tPzX=S7SR&TU$%mxi>GA))Z;U<3$#fOls%?NBuG}j
z6Rrizvd*FHob1aPXbX|W(?QgE*_B`5MW|J#SP8pfvJbk0G+d@&P(;Y$=^!OiHk1x|
zF33*&0b!KPt{s{eW%|VsUXpc+VB)f@f<tjdc5XjL=c;TxEi9sC2`?dxku9aC(KT7w
zLlm(xzm0GvPUd(7ZpX_a4#1}bnN^5KW1{T*D-=nxjh7+4E}KgOl`8v34Nq^#%4p4=
zCc8HQ!gN{M1emxfyWj<9ZpqBgU^hd?`U00FvyOm?+p^gMP-M&aWQ_V9+4O;c=g8_A
z2y<n#<zUH^b^9E(eA!WJCUow}{D`zrww(gcMY7!oP!!81kArH7jOl}-RMx*2H1Eqk
zrEpD|Y?uV3<+2H6zCu=#fwoH7@qaL+4`io4gEJ3h(%xWsBy*$hzDl;d5-g8pUsHVV
ziOg*-dR8qP-E}BlBWtBSPOWSX*{ze6Q{eQeY}9P{R4-$;0QgL{XcXESWRp#(HOfAy
zg!$(($D=4-$Sx$nV3SNwG5Kbh_A7YtQf5nA*cRCjlrGXLdqDC3SF+zJ$E{6f{SYc|
zWw#&MVD4;}4Twi$r>yiCRNu=&=#1Qsy;%>TJ!>h0Gmh*oGO?e1b{NG0w(uR=oY~AZ
zpgG8<*FnXF{reQ!4zb04C|ue1G$e;vw>zl0vHMqp)193{3*sZ}0(vxhuu~q|VD3E1
z9;I987~5kb*gV-A6l3sWJs+Xw&CXATPp4U71&TB5LU-5=U~|R+aF*Tr5Cas*UZlA%
zi1n6XWP{l)FQIadJs^N3guO?HhUeLr{UHoxvqIog7~4wgnsC-&2HYCKZrTc+NH(Vv
zjThKDind3wtAB*>B0Dx3z)S3g@u*#9|NIT4SJ<btkGRTCq7<fRmZR`R46Bi%Yu8w@
zKOBu^FHn#_j@?GfjCi)!XuuQLSE&Fbvb6zdOJdJa_%PYZGNGuZurp~My3Xc526rm^
z<6bo0V7K*!GwJM2+S=V@ea3_B7W-f;R5I8EoR(p8;zg5X7CSv3zpC5poBklnW<MPX
zgLl~8<Y5lmx){P-_PeK0$zz))!B9T?#1Yg5to5@8(7DTwnhMf;?B^e%C}e%6L#K!}
zW`Vnyb*u!iggy2Lic;1{8GQHIZ+-x28LOe2rJQY|9Eb|`;6HG*lC3nr`~!BxF;G8b
zKcyUsN9^uifLF0|D023g_1p^0Cv1mR4%KS*To|e~?4WR{*0N<rsMfJ<lzQ@%4Y~kJ
z_3VKU(e{iTOxuJ8_F^9FHnKJ}vd`I#4S>I3XVKcDi8X}*(9BjWgzzOBoCw!i*n*YN
zY-PWu8Nz`ZLrD{!+^;)m@8H9^HK9)@xC?X`=F62(K-iD_f#$iBTqOtmDejgJ@c!Jg
z@n}2E#jS#eXSji4&;)R+;^F97ZYS;K0=Z#7qX^=@_zguc=eP{;bKEu^$U?Z@G`pYY
zSo)!daw&d1et!{MsS|V}x!MJA<^pGDhguY8{RKJ~Ip2?9_Y&vmjoM|duPY2*;WDO!
z<|?<74v3<;?#U3wa3_-?yv8Mugk~(avj!f<agnr6i0AxiC6mClu7yvDoRU%wlDJv<
zlsB2o#SRBe3fDpl{Og=|FjP}Hk8e=i;MT;znKbUhcNm~_F02*YH@Ts7Om&MBT>>tH
z+bF`2WO7p?p_0Y@MYHW~P8bhdHs>1(%{$z5N^8jBex^8SF6S2lmOL)z3w)E-d~W_+
zcv`^q+YYw7Tr$NU?r}kM!dl2>P>N6yH;@i*in+pW&@AD$(>Zr37qA92_qiV?Ls-Ur
z?S?*;b6-(ME4Wv*%&6oRUx(%cu6QbH54oKG;L~Gn*N-53!Y!j|quR>VQi!pJd+;@Y
zwOsQ>(A071w2*qr&8OS4p4&l@j%VD_a?~2Q`Msdh$l3M>?l~7sDQYjcnQsAT;#7&~
zQ!{7W3gJtxuoGQs;Zll$Yvs1nGxZfWZw9<*<Hmge&exo^nsQ3sa1A^L@hxYsg%|DI
zGKxTVaH~HD{vEgMCh(oykI1yarZ9N{%-iuLeV}R2FFFBI2fp$ggnRh*29WLLE9oG|
zk#BPX=RSVUEU@h7t*4=RfcF}Q;d0`Korb0}|H@hoO9%NBx+7fp!7I^th&LRBL0A6G
zH6RZ2GdzKJ<0sQulsn%V0pJn-{4{8K@E#YTa-5(3Gc0-XZhxZ9i@#0bU2k4X>oFhR
z?pru>f}cd3zWf`c6iNK}$u1~P^6O?JZ%cBDKRyGa=g&_b0Q_lQ_#L$~{2^bM2;c=h
zXwLGsv}p+BEo0H`AU=C6><069D2@3X{|}{6gz&MHO?sZ6Mr-&`ep5fV9ma=@KrNh4
zqNIuleg*x+B6%B1VY|Su4yRMPDBhkDurKn9!r<v8{yZ&nF7xq4s9oVRzCrCOKVc&9
z(L5uA`51l{?ewnkCQLw*Sbp<w5XSKzeh<=kUVIwD1U@GO!bCnd7Me-?e^1bs%-7RS
zErsv46r9)jVc6SQC8_+Yqj2g5|2>_wrSVR?VJV$YJrAF5@~LeoZt(|>!<h_z=Q-3e
z`2Yh<Wbutyl4HC47u|t5d@)7Zb9rtl#wm~g<svxq`Sl~AS-@Y=!|q)^nN|k(_}?ho
zxR77t413lhUP@DNF~8$A5G8!#ct}h6;(QeM`9A{SOc}qAHh$%NDg}xv_<MoCSMp9T
z(2EDW>k8l=@_U`p_K2TVjkYSj_%Gld^S^F^@Cm>85;Uv%9~;0@!)Hu{N-ZA|1(iB0
zKfDJTpYks$Vp7ldoeQ>SeC=Q8Qv*MZj)@!jSIbd*&O1`^g70$-J#6BKx`L*eztRTy
zOMc8iXtwZP^fPMZ-RUIx74JL(=G*vh=ve4Af1bR5!$04FQG3f@T?{}wZ!JhcV+a3a
zHKgzOYjh;h$@ieZ`+L5FlA7!U!)utZ7gji9oE(H5w0+zoMA3q3uQ2%nYK}rW#mM&w
zH~e9DzwkSSL=OlKl;q<iB++TUi!f;w0EdJpGf;CCHd7?bUAS$fxWEyiopyX4!oPIT
za9p_bD|9@C#WUfsmoSjN(G!9f<rVu1M=4{~Pk8ee3V-2;6)<sH=&>IL&j=o?FhGF<
zn}u4CP*M+Eu&`PVyXOUlrj$_ORTzX}LQh%;h6^hStWb>*+#iBFQplw}#04Sj3Y>`&
zexq;Xq981Wr<a7Sr=WRRcz7B#SA;i|WqDQjheA8i!tH@@CPwHN2*5QVI}AmvFf$cx
zal)b|Sc(_6QBqQZP#lF?qA;);ZYK$@kLmfBEPOo!1Dqm!Vua3hVcZ!srV3@>!tM>h
z$%0y%u#?V%(uMY5cyUwk`wSy<OR%G}ybR&~w=kb6tfMGhmf$!7c5e$(`uS!HY(A*(
z2oukOEJyf_eoeW8Xe&G{5IhjHwMy;^X_FwmCrsT4?m|JkAC`)Q<3mAHES#nj;}T&k
z<w=$b_i00OUue`rrA+Xr-BGzPXAe{=gaPy_Nu>~eA9f!Ihv|NNC`_*d;F0j-KKNTD
z<WZ#au`u#8;GPKcM}pH@EwuT7twxBZ<BnQk8zth^2|>O<JQZHi2De^Fm7(pK(0Kx+
z4Z?;i5H<?`9s};VkXr%a3t<(V)iw#mv`%jp7ShA?rBJ7Z!4_c!#XVbv*Yq@dB`lZ*
zc$@I;UbMZo3MW5-i*JM#n}B#LoS^klyYMR=2X_b?kD%?H;6&&2okCPMjMIBTM5jD<
za!-my*~`Ur`rsh{?Je3I<q2;f+$XoIgNgleD}7A|<Q0_7?<D`C1dck(e;NwvgYsrN
zsB@89$5FP`A-U5SR9)p8B+xl5|I-9#+~jXuVBTHsx((b%<mnWI@{rG%2f$Hzf66&I
zCU>QW%yIdXTG;iJ_obsXFL~5Z*!7lY>;j9A+(^d_C*)7$fcwfHltAbwpH8dqlk!?C
z-B+jNljzamFE{Zpe_HM~9D{g9p1u+~0rKsKAv`M&qD4=jyqR(jg5+;0q!cV)@B+1S
z@?pQB2$BCg3zp8yUE9(7P`Pa>0Accebodu8KTg}Y2>JU!s6@(-eFxzM`BXVQ|DxoE
z-LP~~K9JVEm*l@wIRCQz9>rFp<$m2zi;)-7@ys>(`(}{F%3~8y#K{vX(5HC$#%*9p
zkZ0e)SR~5lM}RCzUQEG{Wcf5onN5)!PXK;h{vDmUq{_c=LE8=a*`buBkS6bS7Kn6t
z>M#^H<+{N@+>&dr!hD8&7cH+c<^NC)SeASoZI^G$&l7jHeEnQ#-jV-H=iWK;5znBK
zE0@!%BTv3s0oU^736ykRAa^?gfA7jKAiWKNsps^LRiQj2j!sF7<Ok^aS1fP;90p6|
z@qa+4R9=z}();pRQ&3dMD^A1jO1Zflnh)fkEJaZzk7UvISbmfCEKlU0gacPA-*_HA
z)ydb;D+^EM^XS>uAh+KNgN^dZ(ZD^IU!+snW_ihU*t5Qrt0SS>BHxbLK+-C2yAGOH
z2*{z<CKuCU_^sT9&imTs{g!~HLoTKSnRoK#3@mlZ*U&=jz5Jdnys%STrBJZF;$i}7
z4vIwjY41^JgJE~CVrWmm9TjW;17M$GA1xmCTNSdAU^}4Lo`+#`Qm81m#96Vi6^#cK
zyC|*9MWLZr0}d$`QncDtF|IrChZV^`g3V3QOtYoCV&h$yIHIVl1i(YFWe8M`Dwh0=
z;+P_Xc5KHLmp6jNQz4-cwwGe}2o&B5YX~JI`zQ(=fj^;W3xbZXVy_8>pW^E?5S~=r
z{TLpeQuOvl&0o<@zns&GceK?zqX?zr-~h!U3Xh*vl+p=Qpn@F)?jVH|MdyPRNt7aY
zPO+~Fj)o}aP}<{p#oW{AZm6QCmGVEr6an;Ige&5QqcK9^^aiSt3Nx+QE-I{LXuG7i
zM3e4i#f>R27_BI2LPuj1IrKEVruZlVY_W=w3gF@tyRSeqUa>3{)Cr25?r2L?%%Ky5
zB!#mUxMandKf#%z7}QCpq}LURuRxQk*dW0C4aHAnFip{qc4g^`@9AXbregg_;BP6G
zgrLY!T%dF7Oocs#qO%lBI)J;aXfeW4w&E*#Zr)KKe-pn7#eq2>%T>riK$fSN)E7SG
zD~d({SD?5$j?RwmDuU0W@t(r>AE*{8mf7K3D^k3srB|`y@jwXgD@1fET&8$K_f@&#
zWGD<)D0bOESgH7E5i}ntwxyt`QdIv1*B&c8y27@K2^4c^R77k=C!Q;&lJJEhh#q52
zijRsJ{QjC1J(EHDQsGHiC@qSM&!N+*==K<c_)78T$LK|yV)!O_@mleP4!}2xZzv4&
zR`KhfsI@D$(k81z5xW7!JB6Hn#hnVr`)GTwP`ARoozj_RJ$vPcb};0i+)n4^dz3LV
zVZpjr>1aUdsO(0;m3_+O87THE4F}M*14<(UypwW&8N6^-KHCJLi?W3_V26}`!$9h)
zT$7K%JFL9>D^%Q++vx}Iu4E^o?T9jJBf8|FtflO+qsp|IaP63~hSDjHE0@`V%+soj
z84815N+&wA@>a5IA@xztq`aULO12wle3hLvvVKZ;N=-Sb{EPBHPbm*BhTHzip7eUh
zX=T-WaGz0nQhIoR@~8!Xv&vdp+yyGVzXu>l*)$PuhbaAKgY&%7>W5mW(i&O{V3=~y
z2ha&ueyjl^LTN|yYoyZiIBFM^vuT+VrOcufx{JyiJ>kVA<=pR4yR6*&4k}laAvN&g
zs`6V}sYWY%4gfqx+58b|*ObHQbSqZ5h9U@Y%26~=#Veyj08dZ`S?Qsgs2oSJuq5S)
zy%>aKrFJ=r6y>j@VfVW7OF9rvRsI);+6`scDHu#sj&%h-U8$jM<W1$WB8=KC<*N?Z
z%}^GcMGrHTX+r?WQqDOG^S6~Fet<ArS&$0h9c8o!ICGR=s;xleDwCveDo@#qR*v~f
z2TC<9P`Z8%;a%m@{Se+$-dX|^h04{L02V3lQzW5S*`F5irOJ{W@Z!Gm31w52DGhXP
zSgt(p3tWYA2<6vQDyMx4;REG=6cT=@+(-GNkCb8k>G@ZsY^3MsV`XYHe0!pNL3`mE
z<<YLA5#>M=gmucwi9kG6`ZR;4Ug<0c;F+=y(tIQhN|uMEM&-or;C`+gMlZ&`Q07v&
zxJh}2My6Rgu^qTpWg0z<Unw8aB+{mQTS!?7uazI$!|ylBy_8DuRyl-H+S--7ro!(I
z<?vAezEj?D0codl=5qA@y)rErg`H|QjoKd7XgXfmtNMu6kB+Ldw_tal>hBKV_N#21
zz;ZwpL+6!Fs%0g>Ijg2EL6;7yZm`g_x~QhrgXWOx-*eD$RcUF(>aHp}3Y{aWKQ9CC
zp}O@4d^)Pqmchg^RgnqZKCYTbXTF}QA9JDNrTXkgc;T(m(reN_syFY@c0$!aQ4wF&
z0SZ$1slMM0gC|whb+C6zwV0An{H>~BO0YexI*GxMoKbyEOVt3CJ>|KbRn^no5~vEH
zD0`4<`iD>nR;Bv_cuqBxGKfM{-6@mqylR05icr-W8lW)M>`Aa2uDat1l?YW4jZ>uR
zS_@b%sII!eLX_&-YdCsQW&N8DQ!c4y(>tq|RZ%qST~V!}b>LOiki$Skt0Z(k#;6v%
z!TdGVrnw-ERjr)@*W&)?Q=%%HCX*zU=?%D(RfTlRr>HLfg4%UeJ}n1RRVxRA<%TNH
z5!7ia1%+YKRexEvFmX$De<|29R8RWDi%iuznmn^qKT+cHZB>0RfZ3`Alc1TS%KR3!
zT-Blj7=%349Xi#{SM{KGAPZEpw!w?LDhJBeDN=nN1-r$n<3r&^iRvDu{FSP{`2c|X
zs#!lmvrJV!k+L+(RkQj4U!h`$pr}-B@Pyq5s#{Cp=|k078yI|~>bMF-m1<5E*dD9?
zdIIhzs?n5cQmuOK24`wieh0x_t2#r+hjps)G-p3mjiht?dey_H=+ZM)Pr7v)R9}~(
zXjGN|A;s_Sx$2k4K)g^rp(uNkYRU`v^h&j{6TmjrDhi&xR{i`G!Z)hzG(c}vU-ST5
zyXq@igLJ5zC~@kYN^=x#ovMMuP<yYMN&q``2W2tatIvFhHV5^_B(&{OufGr6UUf89
zBv#3Obrfx852)wG1L34@q6Lbxx{?;92i4Eo;Hir`gq9SC)cdO;bXD)1i{h|)U?K+S
zh<eI2IOC!If}-q4)xC1jmt$&oIvqQ%PNI_zPqiDR-FT_FK2Y&iZ>JxnkNVmya9U5O
zo5`-P`p;Sve(DW$0N}44NT(5})qk-No>4Cf1|mScuo|_qYP-uQ0@eNHPzh46*n&O<
zt3O);+&T5^Q!p5!uB?I==hcH>K^Uq&{SuvsP^<4kGgAFY4r&+FZIhr9WmS)(Xxl|~
z)~8Utq`uM#OPAFybnJ3P{nvCjd{zC-8>-Q2j#e!(>U|gB_cirp3Z2KQ2S`!Gsb^Mz
zJ6=8JJNT5Oo_`s&Wc7q3jCzW?7o{s)S1;UvTB`b?2<C67k8Fb3G_|#k4&u_)(Gh68
zsUAS7<e6$8It$HGcN_%wZS{-EV9Qn)K7{a&`T#AabJWS#0mxMs(ji%%+U<MT%~$_J
zJMsdxA`6;#)uGQJyr)j^gN0)Cw@U#iQD4u6N~wAh9e3VWKeP@4zDzxm0=DJq)SW0Q
z)E!;xDs__#9etoKqOI*i^(Fy!AE}Xair;~HG`&z+t-eps>l(FxGH|u(xC8*|)U$h|
z?WuZLB&h4vYi!Y_XX+J{4AY?Yr5H)0`Y`2cJXgE4Q~c$H`uAlZZBm;A&@`)s68Qa6
zeRvhPThwl}ylPXY=+KMT>O9I2c%zP@?47r2?gH4_)x&Hc>`=R3N9~<@4?W8})rTj*
z#C!E0A*eZMHqgRxkLJ~OsO;4w_d=VaM%=ak+o$n!hjhPYC+z_aXpTHVqmyRF5ERau
zKWHg)P_vr?r!Jb0vLQUAS^FO5-87OhAa&Q&&|7dvG&Zyl^U!=uxu8ci#nWN;m}W4g
zF&@`6(}}yM<|7Iodui^*fy`TD#GPxE_-LlnQs{&xqyRc6HHojleM+Nk0nlHQP4So0
z8Y`W5p3#Wt76{Np(XQ;QriI2iP$Q?`NRVa@r6L4t_RvYiIZbpehATu<Nb8d@&Gbv)
z4A+=SAdJwI(ZeNDGnr;B>jh04Ju#y+|I!)zMa`onV7sLG_dob_S<~o`u0?B-Xblph
ziKC#-HH~=|Xks-#l>;BA`7#s2c+JB+)DkrQ&%m9iF{}b0N%Kt_sFO8zzo1CbjIf2u
zb&cInc$lUM_!=zfR?TneC~s;O)2{B8X3r29%+Or=7e%JV_cds;H12dZcw4ixCtS<c
z1kq959Zfen49U@)8VzBtrq4T=DA4?xgxX!rry($LPc!)mhNMt4pciUInwK9!rC9S7
z#nVePA5l=IRAbF>0^5B}9jyt<G{Mt=DAz<D1Wkpew-zQIYSL72=8-0d&iJY{yJ#Qw
zSTo!mxF?!H*(j<tv1$NnG^=RpuhkeSiKkAZr&QEunq|{5Bn_Gr+Eq1bQfQI(Tyvox
zR9<LmtpB3gq**W-G|d`?9Q}Q%S?2;oi^eAah*r%zI`V#{c}979ZJJBe!?&7zilnz|
z<f}0<9hy%ZfP1H@-Hx_SO~n*&zt^PG37DOB4y_^Vwdu7GI%pTs_qs>hXAZiwSDVdJ
z#M4oG;RmQXX%8;|-dQ_}qHPDYZ4|C{(Q4?vI;0)95qMYaD(a}ab{9ngj%epo)YwD2
z^%JNZ)hZj|#WC$Fn%RzPUz~-|Q+sLz$h@?BRzlNTTQ?AJAMLWaFndC~Jd5I=zS;+Q
z7+F7UkGU{-Qu~@FgHzgr6o>TJZl~?%Y3-77ke<<I)50}C8~PrAv)Ynu)B?2+=y?*P
zZ5;{CV69UuigQ{!N=ORPN-4klyw>kFI7788Md!n`t7u~#u0216-V%w>uBVNCq_&2B
zsu#3tzJYI1+CmDpU(~Yn#Jr@np|iou+PSo3yrR8AU(;3Xg|7gJ)^2%#KE-Ga6eYN(
zJ?Rd&W3`{#quX)XYim)&YadIYlAt|KTdhQG`~Z+8X?xM;%$lt2_8Qd`?X3B*bY1&$
zEOb(}pV5)q4Q=0(=tY`#B?n=;cJK^v-_))hg4!)@=SFa6Xjk?IJX1Sr8vt3_v)9pf
zTf2egl5B0DFZz2&duJM0a<pFm!a}Zg3>~86X-9MgsI1zZv`Z?`Ui=Y_ceO`fqPV9W
zR|rdm+7aFW7HNm+AuQIW`T<y?-EaxDQf<F;82tO%L^>)j(;lgUX1VrfdTdu{m$g8p
zQtR&t^AEK4ci_xJ?UwJL@<^Lj3|y6V<0Pm&)>`*I2k8^-8hZRzYc~_3Mtf!~YEQN0
zbD>(V4W<`So@osa;8TOvXAO!*Z9_M-J=b2NyyX|#=~vM0ChZ_GaLroXAav=a)~Wzm
zi+1-(SZLM0j)B2f+TUrk+q5@*;L~gENox?QZ*V^Y_*Prt3buA_)g&0~&{|JJ=bbk5
zFK~BiOWJ{duf0)+{@UqQDDdUk>jqPh-$8eQUR&6si<Y5nuTJwHaE`hRS`O~haqr>G
zeqDD8E*{W@7sGoeUFTzPI_m<9tiT`Cd43BoTy#mFfaZ|y8_K<K)iqJf;jm8s9I9?Q
zM;di^9XA?|9?><>AHwj^g%5`CsO~f^Q;z9oB?5k2x2Fi4o;qim-o11Y^l<Ukxznc3
zM^{fV_Y=BCdPe!`b_CG=&ri3Lj)YF?#!}AODP3L*3V+={G|`;a?VwzuGrFs8s0HXM
zC^~pn=Si!qK;6&{=vt6YeiF4{UHEsXozp$1cx{O8*ykwD>%OD+=0bIL^h*uXg-4+l
zuB)O9tO%VGI&YOk>PEjs;|1M08sI3MVGcaKsI$<);U(SaKQR`Ub&1cxeMMK;8^u*!
zpWDDk>*76OB1ZR@1+{CstzH<}SlzS+z~gj16X0mPZiXBz3A$}6;1YG66f;lKy{F{L
zWZkwT0IaDxTe@{`=*I7dZ)v(%TGFTM&d^rzrmo)vxOPkTA3e-7bR11-nYzVNaA)b<
zcEIj!-8zb`X6wp#g8Po{@9rSY(S@X-maA)|+_XGhMggevb^f%KF3^ppXxClcGP=9&
zS#_6b)+^Ml?}ciS?))t16zh5qfli6e?hn*Tb;YkyyRXZj7s1MOJ-z{3xh|TXyA`^x
z8sKlG&TTqs4|FYCVep~u%`DU&=?1<Byh`_x4)DjiVH6{IqN`p2L)E$fnu2R|R{mp<
z*6Q-;ki1Se3~yRXp6dK2!KZp%E+wTs(><b8hz4ChPt+Q9BO0LjT=!Ebym+At8UXGl
zot+AU(5zcM0484Qnr?xmMb}Q}j;*@)r%=4oeRm1MHl5o5Xuj6X?1SQsZkLswyKi-8
z`aq{$mnER+(0K;J{dYR?B<OVNV(IpJubV<ab36Si{E-QXz21g_7Y=%dXaM%;!;eB`
zuioV<aE|(=>!GqwuXlpVeti;c+z#k@`s+td`hK5*#aTaU6jToCr{&Z0&qe=Zf6yG#
zN7CV-tKN|&-NX7NQ&70+Kc#h`yM8PsdmPcPnhF&Uy+E06NA*TJ?m4Dk`5TJk`sK4R
zPM&%Lt+&1OcE3T>Td#7&Q2Od0(j4fgpWY2^C-o_G2c6Q_IMZ9&{`%8>@Ex4iXP$-h
zjJ~o7+yVNrbVHrhZ`=Vd0`-Y3xP$bMr^1V1{T13qp3`sY4!a@xy<31gub)K=giw77
zoy>&k|29G;TwhIrrU-qnSkxl*qaQ%!f_?_2$VBPCK(DQmi~75isdGu6NfF-5`Y&mv
zdqp48^=_*E5Di<jekvU<#OOU7QC!of41{K^K23|ZIQ@fk^e|p;7Nbbe*Rd!P^=(Bc
zlJvQB$epZrq6lq@-lh|VuIs1kU?Ej6r#v6)4Sfsc6{qRf&<vHX&lw8eZt7Q?fw-mL
zdJ^AHhJG`J&@=Vzt^j7~uTpmLZT(DolPX(ZdIfEF^s&pplB0jS4lKF)nlKc3`Y4LA
z<m;#H0<J)B&4cD${rg@Ri+lRMsrV`it@`{lG#2UKm!n#&A4J=m5<O4*)>8f0C2;1x
zzE>-RW%{|a*(ukz&|OxcALawsD)pAnq4_|sRKWa0{orb}J<>bhKvAXN9tcMt>s=`p
z^+X>{r$yEJK}z6i^ve_ATCLvNGaHR{`df6k{#4&cc@p*dFnSN>nZDr_%s1$d4gjK2
zKc*I%&-Ldh+4qIMTRpg&^mpiGyk`Azy5(Q#2h+;0P5<v#fWOwqx<d1fULTFNxB4A)
zMA)uRasye1zJ46+z0;queu8SJev$@=_xc5c@RisZx)q=^_J*Rhs5uy(?g7mn!*mza
z_8QV@<L78lP;6$O!IrXE_Z#jv!kGhxxEbiSlVLt(TR0o8QBLtegKZkxTnz4%S8>Ro
zrN0d1YRJ2f+F`?h7j*vTW?;sH&E4Qn$2La{iL~zZFx;d>lB0&Hl*)e0@NW*xA2)Ol
zMB!<8kq4ZYVefoc@-~!E?9Io}{Say=3|DEz>1!Bc2AQ9slpbm)4Yn7da?0?q2>tXo
zEZdK^(}uODX#IJ{u;3_M3^2T-C%{?5Sem;74XY_fCdgpSf@-iqLqVu>hQ73>4l%S^
zVClS}oE|x$hD$+E2{WY5153EUO#99V!;Z%&A`O-FO<pj#3_=lQc<umaE*b_g=)@&M
z=qy|O{w^Cf*g*A)p`KziR}C6kOGFz2uY)bdFk~oz*9;E*0gN?FUI3rs3^%t!CEjr3
zO8^oKs&#-T8eUR_H_6}?3qZ1A{>N}F#nAc(+O8W~&jXNZa5{+E4Z|G`SkeqV=<#Vy
zHz;WkZyKJ>gU&4jdmf}2hGnPm9b_72pM)1#hIBgpylwFE0V3OQzCXC{7?$^fN{&G_
z3nP<j(9%*f&(MDYg!zU+6fY_;tXvJ@T|;gtRPGtF-@`(&!OaatiJ^@`(WO?yJBl9P
zH#pn{u*?wY1oPzvpT!VX82Zx2qSBB@_tgV~WG#RX4bLf!?UAA7Z}?PYsGyk8V?z#Q
zXFW0eIvkd&4O&`6*BB<=KwGV0+C5O$8AgABwx@>e^r}z2VfTKhJTt8S<qCie2IqNT
zYc!Z?Gy2?cir#&EVfZ2lh$h2sI`L~Ztf8ItOT&+y@S??_nhBa#!)puRuM7@RfVUZ3
zPonL$;p2CJzcGyZ31n{#I}X57yCK5EZGqmplDvLz=uUeEJL7&6YWBt}6VN{gV-qEq
z?lE4~!p>gfBHH;o8dDQsXP<Ga1kC%5L&)m`MpG4rz{%K;2aB^Ykj`}u8VA$cB`!uE
z+GQUywo^WXt8pj2$8y-Xb2n7njJeiUl<vm(6tEpJj-v;MhjGOY=o~c$QQ+a2G35w^
z$BoKLaC;h?Vqo6Os0l*N+c=Q+w?4)ZWl%X`yn7gye2txhV9C$8kEYd=#-ANw;gqqc
z88v@n!X>~@8$Y1^+8HAkYy~2~IO{cZ&Kljjq1%B*n-&y7#@fL!5p3-C4l3u2`E;xs
zVw_D=(0QYm87iSh)7Pkl8MEju>TshEorXmiV~8x$s96QT1!D(o=cA07aZtHv{D}TY
z$|d9F5C|_Dg`TwBy<+UW8y&rB{G=H=(MIVq;A4%Ui&4ZG^%Q@PH`*1VEx|aPqWOtN
z3y&hn_>P7o+1S~L{-zjvC!x4*>|ufzsm6fGC~g>)W_XcioJ$GI>Bc+?4Ba$3765n4
z==X#kw;9HqUZ`do_u64-vW)BKd3oD-WgcqT#_Q8SbH|uZ87?`-R*LlJ8keqzYk9`d
zt!T?PE}&fB0wYK7XxugK{S$5Xj7_v@Ei?|x2Cm5HRRywQ<6C;Msl-_A2|%f_g7#g5
z?;Ec=p|Q*u7Z2acjeR^|qQW?~2Y{8v9D2v*fw65F#_ORm-DAe$?$*!#L8aQ5OKaa6
zqYrHpYmM_3fwRu|dM#>CjooRRSZ^FfIg!tdUrJFl7-xh7&}a<Kf!EKCdOG=eVI0>C
zb4^Bv8UUJ&b{34pOXC9C^tBjY=7O`;7(w&GE2HUSxZ7rIx6;c0wb79>y5AU2q{HA_
z<8pdIwB0x-2PQg<3O%^r87nEe)oI*z1S;>1GtZ&T&a`qX+U!m1>9uwTQ%(cS?=jud
zp|;o5TZuMDQw6OY_L;{21i*gN0D5EhfN6dK%sZKW`h^b2olRS!;P64y5=ymjF>PD|
z;2~2DMUGuf5wz1eY&wz$gqz8+1l;bX9(3|^#DrvH{K8DZwA(yt3ZzHyG1KA-2#=ex
z8d38!?HvRQUZ(HI0`6^EKye*kQ}YRQ!q4=th7QP2nydqXIAz*W2T%P?y{>`nv?+i>
z1ZPZ}Dc>u=6i(^VXH9G9Tr<#=JrG5Z$-y5q!KMNRxO1jERt$HDX)i7H&zpKH01q|&
zSqOt+rhZ}!Ubsp5JBkQX4?6daG=<!;!5w?Sv_u1%C{xTTn7C*<L=)&G(=m5AeA$%f
zh~kO~e<%XKDU(}1@X@Af2`t5!e*P0}*GzxWswCDFM0@Nw(;PaTi8uKihDw5I0G-Dq
zn(i>DC7BvKpptA_xE4i<>CO)@WW8?c6^72Fn%cJmc*C@f=B_kTD@DB1O`0*Vd(-3|
zfwo(wI9Jp%O#L>4Ez_i?@OzfYlQL;;n@$7*mu;Ho0}t<*UhV;RjwziYUb!X_o%H6J
z9Oy4)<eQe;VYmuRQ$B!&yH?X6$}hcV^0^H}q3Ie;Q$?niZqO+<jf;iB5|cB%iCAjN
zqI0_YrVlA&u*}5W1fbmH90quWDeg4PSDGaBM#KYCM<aZCXnH|s9*;~4N_(s_6+{5=
z*wnBK)K5&avd~s-vL^q6vc{B7Y_+DDQ(>ac^qPf<r>69$0M?swDct$Y)R72agXzD)
zu+(Vk5rDSmCOdo7UYN$?tVhyh8gdhw%_evH8wf8=V`$0VVrp*3aJQNwMJQgGhT+d_
zN!m<beGLy^o32^s!|of?PD&_vYx1Xe_}Wdq=mpA7)3Bwey*K63oM~rP^n?j}^Xo`>
z=wMEx{I)&jCA6vEYlidqshOiG4z|zSMn?ks%>y<;c);9^&X1hTo~r<GHmBc$%0Y9)
z3)pip&#bh9`;hsH5jw8sx520#HmA^`u$%evFVJx}t0|A-h*|dq`s-ot69&JJnvs-^
zpPKmwZC#I>$4lUar@3MY40@S^Xj$NG-axO6_?X$A==KS7y&jyt<|q!Fe&)eJC{CK+
znQig=J7xa66srE_tVsZ#Hh)Fi+cRcuEi46?Z7HYgtT|#mia_&?PoNTH9&#4=VDoo_
zQJgdPoD6t~dA=5a^X9KN!KYAjfeu{?Gyf+-Tex`(ZK5K~r4;IlH0N^g>4JGCGH0!l
zDD&(s0A4hIdkWG^=B~eWdfB{u7`(V*{+aSGu9^qZBouAlM(3z8=C8Mb?V9;rJ1oVT
zk551?&fNbvig@#Vawfst`yl{{=3?3-B$<OK7?^DCI}$~T`P6wBx^CW?4G*oU=B>ZO
z#0~QeT2QB%S39GJ>E<yPVE(3gDII^^GCTDHO@?`10nBHbE1V(BGN+Wo(rxn|f3Rhn
z$I>i)$DBY*q#U!yWvJwuFCIcI&n%(84v}yE@hyg{!2I}6wB0pJ&jNSPqx6@))^|ss
zcHcbh4(Q9w{Q{s}ZXWvsY(6kc&%w$=v+-j%`N&+k3vE^Ad99#$Z2q_cxF_a^6cMX7
z@1n`6#$0j`fLe1fJrC>53mDjZYVKE#TD@7k5;mWi{WqZ2VE&G>_8QGgt;2wSZg!{u
z_Y1RXA#|F|wyqF1n<bR`|I*xzq7yCVg9#X%R&xi1T3(sk=|zt=^F0Ned2J4*li)Yz
z^l}t$&F7S8Yd1U6Ubw?N!41VbvzH4DcA7&yq4M60i5<Ty%fd}GZ`)fMC{E>INuaUX
zWBG*^@p~;h-vH=niJ@HdeHPza=-PfuoI6}QU{S9@o0DZ39r!z29?%ctpe36YdoGq#
z+NB(_eEKOYxmrH|6P$-FQv_IWv)FG#;cgjDS=dJ`ets0B@UV1H#O0`E^-gdfvrL?i
z+Hs2oA#{nS<qhRCds*zdfz8_zzZtIiSQ;LH^n~RY?GJn{^}C?rX9=Xe&PmJj3*bIw
znf4I?{+5k&$b8!JawFQ#So}7_e1PS*N?15+*))n?5(u=!(-~}#rTIUMMX=>v7TC^N
zR?w^zVu{?0;=JV`<>G}}Zmol6m?eA_xWg?`-=c`H=)zzk($aShyuV;cItLR`mIKQn
zyl9DT1Lq~nSCl1n*%IM|F}z~gSq9FlmiKhFZjH7)xQoUZOL`Wn*DSXx&=_k8ra$fw
zXIWbhVZ3Dtz2BK&86FMNM9Wf21x&JVAH%2XmI2)WPqp}G!0j8BzB8bbW|?>sD(RMF
z+P2=b6jLtGEsKSI))|&V6o$;SEWQcNEUV@GKDc<>a{Lj-GTSnjk}U67J}3tw$I_Dy
zq;f6a(EDL|mh*J9nQ!Tl0lNj3-()E6T4E_YaL>Zp!^1+0Xg^enET1NUyV%k;4Y(4^
z`aLjMYN;;+;J#(LGyE;HRMUBKxy3q(RxA~kNZMUhT5iQa^?@ZV3~UcAV;7+Jk1PzG
zC{<ZDQ^MP0OAxKppIAQYM6KGgmJaM|EZ<Y!X{{x22mp1KOSy3SsU?kKx%HNqDiqHw
z)AcACEYd`%G+JyOQG0IbZ>5*8URcbrD4Hzu7Qs@p#ia$#ytF88gS5pm`xQKFwb)St
z<tt0#XtcFi(lcQGwM9elH<rdvVDPQw{RwEcTcY})haHxcpQ01*EOjGL>$HR@Veq|W
z%oGUiy7i##vVFH%e^Zdcp<CuE4ELUH&h&2X-fls(E_LiSn_iFE*DbgPi2dE((rNnt
z<LJ8MvaG(iBebQJTG_kz-U~;=%!ZluQ?t^BX~Txu-sKCj_i_OuQ>GxYHwXv<%9cG9
z5EKQJp~(1sPk)`yx%Yg}IrqNLbH};oKCdgoy$|lYF`lRGvO8lt<vDmT{z!+2C*$}Y
z)Oj(MQuNoGVOI-fJ`4-Z489D78IJlfUR?*ypYhMf5D8%P{AIHYFCHVFl8BBno_R80
z;g>6|ezcPcWF*q;5yaTL4x+(~d;7tiWbAtbB!n?WLAO(kO?0Rb%BTqj7sgomI_kn1
z$u96BieaW>lhcfcY2hBtc<B_l7>3mkj>a;47r>b~#!t_|nRtdfP5cRrrCF#u!|=5-
z;Y=dqb6V0RG3GtNon@TDM>%bh8CCSnk#mf4I*m_ZG?1gIj3hcXNn>QtRFcjJ>VcXJ
z#>ZcxFq5%L3TLty2U|h18L4z^lEav$7*sA}?;dE$V;rYrlYB<x6TlTP6tB=H9Sa#Z
zd2q3aA#T9~ah_32G0tMfN$R!|Mjjn1lrkKg(WVQGH=Q9_#(0D_^yQ4fw_xHTV_z}2
z3dUuc7b_Xp=HW~gqk+b$ON=ZX$YsX)3N)~qaX$)x8U~Bvp0$js-{{(K9b*OM;MOx@
z7_ij9xb+lFG%`FWw0niIhF-iT#ve5RHZ$UACTwB6MJG|M3^PS<+ZaW*AnlAlf}pg6
z@fby>IvH=%O0<h{mJXu28Q)O!wukWv9V+xP7El!DDua8MM#O83y*FXLk0Ct@OZ^P>
z+ps%;o&~wih^I5YL54e>bq_I8C}-*h!$X7?-efRob{S^iKozeVL&*VmoAEepm`50Q
zb>K!B(KgUB#@PE8e7eK%q#fX0#@sV-W}I=Do^k60Bbm-5CmFG{ft+HzO34rR7`wNE
zyU(~nVZmvJuPgk1z}P}jgBiw?_7It6e6Sg<m}C5A5A*Ykcp7%>m_MEdz@9lwm*EdH
z*V1_5z~p}bpPZQ|De&mR^t+EbS7xIR0B%-hLJO3-GcWxDZ63@93Y~Z|2cHMfi}~CM
z)Oj<P(eZ^3bL|?4_%fe=82<V(UuZ*}KeL~<$N|i3+O{8I{(1~<A7!4G!{9My&T?ou
z&itJo*%M3=ZEymaBlM;QG1tl9Ofb_L|0WEcWJdlDnGoi0Ss<sF$0#>6l)3vX5Mj*f
z=Ya@kPSU-Y2&U>i03w-Zu7ZnVI#bfpX{Ha2TG7mJXuODFit_=8Wj0YhM;!CXC^!?(
zRJ;R`1g79~kTcA~U&8G~=7(15^(5wX%GWu|tfGvUWM+O28gq_m{1zrsn0nerr!v2x
zdw6Ng$F4y#ow>~cYBHE#QgAVoxs#%US<GQt^<^{t=poHvKGzG$T;|@pu$0H#Jc`16
z=CV#GD`4JA1+I|!-6=}jDPmr@2lhNO4%b_4ikY9%09V3%cN%_|G9RUV^aZAR7P`xr
zMYKFBXI|Y0H5ZwW(<-Tgx$Z@XR5Gh+{;FbH=@q}kJbD0HE;ApY%z|oWG!wWQ=9nw&
z)iO8JwzQ6UkUlqVQ_oyRvswdlpat3*ndfG}U126rKQ}R*euJ83rrkQ!wJ>ujxZlcr
ziXv5QOb6Pwv@`hva2-qyMXEZP+vR9)7qgY_xOOwUDPg;ZxtzY}(aT&p3v!j|OG)q7
zn9t(=p4Fz088HGi{mk{H01h(0+XfRuOyj>GH<*8opztPh6|ED7nUB-H;TALLE!5p+
z_E6YsggN{WL`Ip9Z%22JF`wTH?hZ3I5rDf)$9jm2Gk@F$4=0#`gYa;YxreUWO)+oN
zm3-?xW>^5s-)DaCA}XhuRTP(bz`XW4WM-KE!=lM%mbw2ZMCO?5DJV71Y_o$lJ66>-
z5PKG*5k4Jet#&}099XZv0M{H@7neY{6YKjq0GwI=3sLC8`VE=<Hm<C|3m|T+zD=;_
zZe>N%MB>5PLHlS=mSQ8cd9j4mKzOrO(mvXUC81%<m-RZGiTJU0x5G7mRs}_d16Z%r
zK-&?Pb~T(i$~r&`)?=(95$cY!Txex}g7p`TT7j(Xbbc4aO7(|p!K_3VxOS3d-LnIB
zLs*Yer0Nta{VZA^%F@toFN}q_HeNi|U$dx-V5O^JB9e765+sT>BL?m?D}~;wXjaZr
z=#F7sp%EsQ^)e-S#IcODjgDviTLtq8EZf}xoM8ppL3JYQCEEBVv36Q1hwv=xjs;F7
zvl=PNbB>ikV@e9^!9v(gWo?)ONn<r3hGLV>y6z8487$9bu$0N-Rzfn1HTouS*{tqr
zXvtyK(MmO!)keXVJk}~YT+3(uPUouytYm6#A#2}@s4HUad!BX#=UF?Jp|qIwi4YE#
zurBUKVJU0)GibZOa=QcbWvngqa+R|VcEI0CR(d-Mt5{p<iqR$3J|7fbW_`*5pqdq6
z2Y3z3S^=(>WlxDKbu3?6k<_!!1OV5-s?P_Yk)^y!anviUuj&15Vzqd~L^I2g(l}dK
z@3*5(t*nJ~Q>l$LoQ1k})}52^yMtw<X}govPl;n)ti)|F(akEP^PL{nSz7n@vJNuQ
zq^qnaA3)hP*5$1L^s%;3_D(;`@Cxb%Sa#pg{CA!8A~k!EwVf7_L#$`Zfw;k9Q6}O|
zR_JmdhFLN?1ii)TrO4@RR_;2~jj*a|r#{L`E<&5eSg$Vtxx?awLd#v&|7cY>&Z>M0
z$|hKDU&F#AYv5r3rdT`QgUCIWc?pzR@3U6Z*EgnFBX(dPu&mQiGsAjKgJ#dNK6nXs
z=UC6wgUquWbttrB2RH&?&rUxDz+pD)K0I__C($97BU|hRyH4yMOCaLRe%v1b7q(Fk
zNmuqb1-0DR%l-%A&Yns}p@)@SZv)+)?2rEj>%|@uqSBkab~y@t*gE>1eA#t$Sm4Lr
zY!9XW?96{b0@&|<2D?YtauGWJD7z~N=8v&I%LDv4d!Py23HG9XI1|WDqw7{dY{e-6
zg4rG}=!BE(8xO#Ru&vL&1;i<~js}HLwk>_XC5+uhX+PoYSqkPwuoW>dAIbhC9v()q
ztCpgJPP4y{KwUKZkDaKCVgJbjiDm0)Egi@Hn}xbFY)%-=C$c}FlcXf}RSL+QW%DR>
zn#}%XA?nVtuURV~n!>iF?4MNj(qZ7!*my4Rs<B<&0L)-By3m+R_RsYFvMlxiI*-m~
zztIS1a@ale-OOC}9S+)*$8J0TrTOfDRnStvzC){(LiQJXfh%IS&=Tf6`%E`f7qfFH
z(WZo*>P=DMQug~-P<er!O_{Z2YzImrC}+n%3QsSx-!4acE7%|Q!%`)?uose5>^TbL
zTw+J20C1UImJLhQ?3^+vtzo;g09VTnp%7>tJ9#TeJ$pqX3LDrf==8slZGIBu3R_h`
z^IsD?hdzDM%r5;Bc3ap5v}J2$e@GL38#{r51?}v?wct9~P6pI<vUgHmQy2R{A4oU5
z^?x8e>?%t3?PWV;0&taW{}?>H#$Ngx0DbJ#k6^H$eQYcI9bkJ!p%K^F`Pdj(Z3fvt
z(;8%m?MMOD8|;HAuym7sy#u1d>@)P?$y@9;dW~<hm1=M!><4rXH_HA_4{nUTAP&vG
z!w%mJz+Ltnjrrs3w|7Bgf<4EE>PdEr2Rxi&+tfhh9^2tNn7_|P<_6xsY4$U8^6`MZ
z^BUM0_9n`Aon`-Ch*r$8AEh~Ro}ENz7IvJG1`vDBMOv^P<_!M`pBy+Fk3z(e!=;V2
z6Gz5Gvz<Ag)0pqVd2|biE9WN~E!{YN6z+5942J{m!TFsg0&gp4`&G2UhqH!mRQqz8
zDJbU036lZn&oR*2DS#74L9rv8rH()x<=m#51IIWk_Cn2Z&KT{{PH>{>ZhIhSJDtJ@
zaU4TX7tHzM3n)9u+1?HhLpZy~A##fIB?UV}Iol{G7RIqYM$cS0$DKCc5uCbrz(sP}
zGXRX@$Tk9Tnsf8NTO*uZHgG0}Q*aG+v7C5{M#pi^(FOl_&Nz*o37l>U?4RNIdqGPg
z=LVf|Cvo<yfWK!sF{uC~bAsry%Q;SC7CcPhaIN$nrgHv{1U`-PrZ;q_bME?~GK15&
z8Rj!N$2Cxz#d)n2BH5e?N^s5LFzG$W<y@y{J&$wz2u$R22I$P9fD`=&EERIz9R$3H
zvw@zu^PKc$z!h`mx<E=eQxp{`<y_%Y?)?SMAf>;Rad0gkFCHhEvT!bPqG&*_;JjfE
z4=Xtx&OlUgTz&+1iNlq`(aW4ypFv?Y=Lj8|)o{w2fve>#rRleh;~oHbJ;&J|jy7<9
zqS#C$=gz|rxx(4^7I00RMJ)PkMl<KNZIEf<s3@e>%30Tk_O@}JqieM7obtb*t%GBB
zg|<#kT?j<FIHLE#b#oTJhGzG0Om_kA<-8$-YgaicFSvG%^JW*|eVpH4Km+?Z^>Gjx
z;4G!M%XQ8&2lUJ!#}oFfHbb1ahahu<)60X*O-{ism>A|PqFMYF$A|8kk8;k(p>T|I
z`oB4jW1^nD%juv?a^sv9invU0o;wBjBuD%X{GH;AuYkxsPB4W??{j{pCFV58ftI!p
zIBT}T-VCStDu{KKBmWU5<~T`TgUoYS&qKzJ+e^Vdd+uWT0McP@a~OyN*Q*+89J#)9
zFyO>JP0J%^t{<h}xNyCGf?Zec3lwU0<33M6vpe?-isgE63n(h$$z4<q;>8`M-L^M3
zha&4fR&F8nmoN8k3cC4mx6{JYpBq96+X38B`aaeX?%2OT9OXVo1I;mRX&o#b=We3I
z*c0598q@`HFVZnV5I5vDaKT&^z1t_bp46leE`tSfiu*k+sYAK>OHmibePS)RaIV#`
z36&AtZPcbnZVat6qPRxNY&gyRktX_Rt}m_pVz^p5tB>WrLT!rU&eJEB;<@o3z{3Qt
zg7!RTxD!JliCk9-#wKwW(*tpq`vsjHBy%683H}_no-%V%xNlJwOe%M~m5v_MxLuFK
zi*#-c%?lY^Z6NTOTs1|Vv$!@};YBuAp@kPY+?y)_$mM4J2upd~MT?<3pSzS2>I=B>
z6g?{B3bvrGh`X9rqvyFRK7^%W?oXwFmvD#npq-`MVoEW%z<uZh1$D}}zrKRXa&G&3
zAQ!n3N};IWE}nw6N^Zz&&|Sq<wxaG5cWpel%iO&OV4|A)r3z|lxZ|5a>bbA|3bz}$
z4;H~-BX^4@nskNxOB8TTTwmJKHgn~lqppP;M)BoVuKqb%f3|UdqrF-?_Yx&Ub#T{G
zrgtYdhi+?jaW7M(wVPW<Inq5`(erS>ms_BK?yFpl9BQs{SFJ@|A9t9BhJNmW-4Gez
zp3MO6I(Hu(k`Ho?PeJt%H;h(EH@J(Ap_^}VKlqo@c80lYX{CFMyS^RTZgabWpnHUS
z{7)c8x$E}9i!rV+A0l_S3wNRJE_Zq!lH*(zO=lC_&E)+gH+wrQO>rwfh3<RYIm&gs
z&t3m3+B?l%{3-wsxPMaIbcTCK0>CWy4LTyS&T*S4t}xFXH~?*Syi*j!vgZXRf*j^u
zco*6ncujOV>B!6f0h|->rBC67Gf(vt04}@<O6hUs>3)QVZan80D0Aoa+<+wy9w!@h
zp1kF>qW9vxKzT{tJkJD}_u*+MG1k}0^L7ID<B9g8(x3P61t0==ONzi9;XV5!I^ihq
ztO3p(<7Kvj9Ot>yyM2Q9t_5|0JgY0<LA+NeeJz;x(l*qc<jLO#7s4B~gQZivN8f{F
zD6fdN%VE6A4shYT_%l!z!Ly#G;BzD|(g1@|JZl?dPV>J142_BAEufWo4DW^i!YRCm
z>8*<6F&2Wv^LitoJAoHVTaYunF%bZXya9S)lX&GXpr6k2swwE5%zKMAs^@sK6n0AE
z&7=dK&MTlaungXN)@IO5Udk|JvUnRmMP)XRLvLITk53`ETprsSy7PEnn?Uk;$^no9
z9-Hzz3VHjIVZMlWFC2jLJPX~aDCQ;7iCPKoXEsPFFM>h<7kFPh0t;ol6}AAB^UO0K
z7kRps^!`=w*8GdgO5SVqQJE^<8$Uz$CEgZVNnPf-ypOtSp5Pa_R>SjUgRAAewj8e2
z@dUIrt>?K>hEW60hmxurc_xb6T;a*rz<d*LTQC64yd&SE^({PIJ9M`4KBT#^jpz0`
zU0ZDDMbqol!FwzTq?5Oa7Smn42QQ(a-8^TykJ`iAMiGo&ULFPVukvynq4XMW$usb&
zkM}X1hxPNea$s<PH+2yr*Lg1A!O|elo&mc<yy;<x+~9dr*y$$k725I)^DZD+&}wsw
zm-QmF-R3n;f{gH<qqlLC*S;QPjQ9F&ICF;=w*d~{<&9Byjq|Eyur$GQCcq?bE*f=H
zyj3x<bdUF98g$?1y}uu1npYPH@_=`R;$t(s2D)N2%lpv*s^@qmYtUTlJg@g6)Y$QJ
z=+>n@Kd1`Y4)gz@MYsch&k6t?`E3+Nb>hEu4#b(?_Ba~j!hfy=#Fd|U8y)1v|K=`~
zy7SqGz<Ka%HNbiD->38mFaGXVq0F0KPCF4Fei!8f`0_^sA>wD{@1nh_KmT!>TLbvt
ze*veC@sC)+9p`7z*n5KiFQw%K@{2CRL=a!N6xxFMXXAlC$=^t8(-8jGI@mqMcNC!!
zq5K*;ehlMpy8(mYeAZ$pi{M`zfU-#b2Q<J$@xP_5_-VfNq!HSp`8IE&X)*kD6ts)w
z_x%Iiar}7NF~;+IuR~1&zvVrUGyEs$^dyn*@-fsT@oz?;6VCF5w7E;>SJHy@96z1L
z&J@0a@>Ns$U%dfb8sFzpc%RPy(GfZ`_)YHvkjekj8jaE{eyI)EY`(h?x^wsucc3Ph
z?>GZs9>1Hyk@<Wd3T_tgcT!;?U;Hg_Mf@(xUOmqr9S14qs|;|ag#RX`@Rst2DRg&%
zzj*+v%lMZ*0$0x8@-;**^1JC#ui!7Qp{#^Te#<Txtm50yTK*EhpYl#G^AFL`U(Nr)
z9d$K)8679o@_(Y$Ssj0`5t8-%mV*#!;O{cS!$$rI3gBPizq}N6P5cUq3^(%={z6>~
z|6N)qwDN0HVYiL{{Bl@m=N~>qX{#OlsU;}w<hRn`*To;F=wvtFlOl*c{4^)n?d9kG
z0&<nVq!mi9@%QoJQy<@*UjKgnQ7H@#@YP+YyUx$Pfx<z4*Y6-h{36<b-QfT5CtSP9
zAAA?8hxxldg)_JKF6U|ed7Hm!6YwMagDcROQU0cM$c*uieTBk1{5$qgbC=Jc4j$(x
z?n7fH_`@1-_xME=I=|1atOJ?mH`D9?fZtBpDl_~k>a|(^oE1LJ@n<QJH_v~w3B*p&
zdIdh&3)Y1IXFV)%It~*K0$Unw9R+`<gL4w3g+s<!aJ?J9kBh)>3_iIEYW{oG1fN|)
zW84L)bYkZr=;lC;r(l}ab6$dPg8}dsJoh0)d;~rzAijcUd*Fqi;BQZO?=N`n0@@iM
zIB!JV5v$;RnoW-i>YfIBOt3o>E*=+fDBN{IP*#SzK*2Uz83YObqVRaIz~?83oD{qr
zkGc>+8KpR#5_C~kPpF`R)(K&PS;|ri7d%Uc%n^d07J-WtB+)YyC0OSU?zAADMy+Up
z^*F^2Vgx5BMJiTsg+6B%CwQ9<apDF4Tm+XONT7l0jDTB!!bCwuG#Z*DXrx8_S-~}0
zCnO6_&=7h~Ft7~0mLk|61)Zq^78CF^K|H=rYm+WGQ;Nb2LBwzHDO2$KlYnOlwAOCu
z&K5kbfbJYY?YF4R6|}t#V4fgh0(JQUH$6y!pnnvILcz;&^j?u5iqf#p3u3oGcd;O(
z8a|Z>3T9!xRG@hiZMh(Ln&RSR0!Ipdl?$YK(0Nf%_$o++;JIHxDg`^^Y5!Lx`125e
zmjo}+I_0upc`lSz3rb7D)d(I?noF(V?@VZ`6YSmvZS{h0HUifmP*BvkQSc!x#I6Xc
zS|HLSxI-BY&4SF|;8UAmDb3#Pg1TQI*&$e!4X#rVJb=0`!PHKA|GEX$Ens^D&D5A)
zfy=uvcvY~AhP!KmujvyNeS*nHA<{3XqqLF%!7udUT^HP@E*%t<oPp9I!JW@hcth~=
zNdRsN+)~k_!-9}i&~i&~cne&+Ex1mdHzH7dfo>iZ9QYG|`)V^Lh+hu;9YGcCFYXH7
zr!jO~;O+<fgrIB&b&~>3H+-5BY@&_*Jwe)Lbk}`B%~~j(7DW94r4IxZ6dRop*e1f@
ztRR5y=*<Z}q1kX=u#66{?Szc$uxl?o^bqO}3nLPt%<3TgGaqUkh4p->aT5B{H0mt;
z<u-_mFt!84RhUH47&l>25=7jEsT64P5N>+}j(Q5iUI*tTETd7&TeyMFlYNBkbMV(!
zc=#Sn_z4%Tgunj6<uND>5H4bX91&(wJpQOv*zpG{j|oejf{Vw6NpwZxgwU=L+5&|i
z(=Qq%Tu*lef`x02f;%b9q0dl+2;Z^=cS<<D2?j%jSISWsCafPvVYskj7+i$#@?DsZ
z6#hf!q*20$B4PKmaOW#%OSG`u8zM16>t0HZi4{7324I}fUWLkd;c^-^6NE-OPB<f6
zMx%A2(AWb@Ny4!8;LZv;4G>8d9{B^UKPTL82TLi!d2%gP$V^3B(u6Pn4M4ik%7#dW
z@TWK7MW!&HGSahzeHIwX7Jg@?<cU1tXL|w67apT{MuE_KD|{*xzH%18BB8t<YR(J&
zszHi{YC38!5qchizoo)AX!^V$y#EKZl?k6pgKOnN0UzX|FmVS+h43WxdZlo&5b!GD
z!i&&(Nyu3V+-2cc_O#BZ7KTuGutvD$61=DtGF@S!PIx{B4%Z8H3;-L1SgYYx6IM(B
za7Ae7guy1Eng-Tp;m@xC*CPCrK6TqFjG&{<HetYfkZc!9>`>Pstm}f7PGNW~>bitp
zY{0vP!Cv&|Iz7U^mmt$C+_wM@Ulp!@2hLm*el!WvCu|>uiGJZi+FuL^SJ5u^y6_k!
zkPHg{rIpl>(3eK78^TZlns!sjr1ZmKVMhi`+!D?lgwET-7b0MHMEG_UnmsB!LUFk<
zp<Nqg<=qixc|rGG;o~&4j0=;FfSVA$n+k4Hc;_C}ObILZfZP*CK8d>f!e@?wn-+e4
z4oV*g$D&a<Bb;0ae`keDXQ6veSV6JTd11piI>Am<Pq9&ZkptaOI!vEF#)Kyte-)h7
zQS{fNaM4LrM90L=qKN+%m!b@cP`Qe7C?M`8I#vV|?xIc9B{=-w2cV~@ot6|{qNpJd
zZ_(p)ztTr^$PD5u;=d0OKatHr)cK40YrzGGwmc0jM?}l^LCaB5VE}sVm{s(i4NM#t
z;lBm(;)!&(;BcU5BaL1`qCdX@Fj(|1eQ4^GC_N6n9x6I^3cxUtf{D6t(e@`{FhZ1a
z7j=;$4Fk9+(eV$^38zK6#puIm(IWZ`ON_`l8x~?kAJK;{;zTun!BD)&y1EQ(g2?g&
zJUt`YFbk3>nxti2lISFDU(bq$d!Z&-^b_s>&WWO5hME*nE5%<@MLraWNE6wIgQSaW
zDFT=wT1K;Qrf8@Js<T9H1#m4}^ybq5<cPi(LUpd_?oAlV6WLp7Lz6FJ&>p@(bcRj^
z3q_~b!cviFGo5Xm7pZC2T`b}|!fuHuVg~q9(R&HNT@dX*29Yw6%O}uQF4{nAu8X4g
zccQLB^ff)lm7*{cR9A_r>B#JosI3Tq%c9ggkZRFFffc|S(Hr$pS}U>^08uB(vWFM-
zqLgaXHHg;Q!<k0WOJQi?713ro5o!{BKL<<AqM|{Fw1_M^w6Im=IS-LG(eo6OZ5O>z
z2@@TnWwh(=6s@3TXqV`{PocV7^aX9YdqmB-wEycBO_0M^MTzuWT@x*!NNt~J*ACe2
z7ww^(o&nJg8n&*B!fB&BD4L|4x*?Gros-@WWxNT%P0=&8s2di&^9Xd`60N0e;B8Un
zHneO+w6zqSFe>u?4uxZ)r+)>xBT8RDpKZG<+K~qL$3>Y+n3xc~A^@2by+Y~3Q=;pX
z4|z}Y20d)|MGp_5a9Z>NU3q;VI`$OQ%!rirAhV)GI-0Z-|4ShYd-2%oaP6@8f4(s9
zAdaTQB1f^)2qc}v9kdyB7Vn~bd#j7Mza0oy@ebOUxQU$*6tZy_?`Ve?9^$8~Vct{R
zOO5do8z@8ATU`4A@IK;HT3-2z3wHtMCuRgf(qBACV^M&3JB1vNi0{&^)}!KqG$=bJ
z{^eC@IWD%>0e3>2wFq^AR<Y$vG%ZMMcoB$T@%T<Sb5dLy4>cj;7`kzEO8hhB`-F<e
zDF-4<T=+EV!o{Dx1<44ph2D`!@mJ(wl=#`T(0y9$u>q3NVyQoL#)yYEf{PU^Y2g?r
zW~HHl@#3ES@F_uTHRPc3j5weTmJ-E2G;Ae_ON405S@Cx2(q!?5cK|#mo~(uL6mc0H
z5vGd2_6JE5b5_EOba66m^E1T9>4tEo_z5-aW{Df#hU#qbV}C$Pj=19(0J-8vDcY4M
zmVE~E`QneQYLpg;%fCh^7K+o)LQRo4DIS&Q#ZB}i6^pkv08t`-Gy+_ycwI5HT@cTC
z0#_z3p)sXgJo_)Wi(<FS&{82@5e}|W?70cbs>BDLg|bWHH4HTHviLjN23CuEDWp^*
z&QQ_$U#&Pi1Saal)%B367cZ4Ura@dsyTL~B$)}<1iuiq6$Tf-A&=cG&?#zWVE#k68
z0JMr-Y5-^x*Ooz9ySQJ7!Vd9YGz)i%*W84^UE+gTsOuKXZ^7<WaYZ`d*Tk{qk3No9
zO<Xbxe7`s(pw?@Zb(Iw&Lt@Q)AUDL%Q{L!JG4}!_hQ+hAPQE36q7iks#V-fI!iac}
z0V1Q~P`dduChnt^<{j}w2h83TchOdOT-+fCnGpA##t$+nen2tYDe;g0!q0o+Hz|^J
zUwnvmkJI7<)+<o+Ks*x#nHlk;^DsCo-oGB+&xs$UyG`?Ar+IL8k~BIfw3l2z4Bdw%
z1C)m1AmP0L&QWrZ1raC7Pg($+B~ed9r;CLB95`2rJMBl@BttY-yGxXd;k}1s%nc%*
zlINK8gLp}TXqn+HIa~`FAIW<r5MRkYN~89Z?7WX=`%5<ap%VfmD;=Tqh-7sR$Wci#
zT@pPeDf$CSk4u))uzEt0LQAGV$rc*kf+SINd=M<@q|M+-$@8>A4Uv3Z1$(C?pMFHw
zbV4Oh2cR@evX=*^!X?)z_7x$?rO7{1;z()VQ4%`}Z=aStP49HHBqRhr#Yhf?LNZoj
z9s`M!@QPp}UQ$PyR|%4^Md+Y2lHX`jN|YRNL0yvM5j()oO6p$%mn=C^`QJ4G$wCUG
zr%0}ELz_}1+dP0slces4GwG6(sc2e;WPL1@W=ihS+CNKTrubI2<iQvKIg)p8gUgku
zXxo@4QTKq$my9N$u0S$C@$f=PI2~sdN&ciu9p@z%pNE!G$(0jmwe^BzFWqY>ldLKN
zDVGcdqcImH8|Xx)LK0d9rInK3HbPC6<YpP_E=iWGhHIB4ag=6TE%}hr1!^RILcnV!
z#ck-BI?0P|Fi|ggiJrg)Nfxc<8YQ<~q2-E1aUZIiBtQNP(rlGX?tn~-<la5Vv`YRc
zhPF0I28FWPB|Hj)bV$B_5`K3|v>eoRN$&p-z-|eH9-SV^WqN>nB|`f2+*Qfy%V_8|
ziI}!CeUeY!2I-evUj_JpWYK<*>yi*!MGi_r>Oh7h){<t>8<O2LTHchD(0XWCvScp`
zZ%Jg^!QGZTrH5-HlEZP(HYzz!c>-e+1I@*EBv<Ha!(EA)a!kf0H39H&LL#kzvPsD^
z>1f21#En)!_aqy;LGDWmeg|M$a+=n;4<z4P9f6pU#HwIvRw8=|O6Me-*MOUsJf???
zo%9P8blXdtn!z2GY8_DLAWhkZhB`{uQmoxcx{kKl&eGjafVfD%`VBvttMog%A>k%{
z{4LmZmuAytJrC)7w9EFC3hDgWOZxrGv?1`84u613AL(A&8v064(x$;r>O(ODf9cZQ
zXiR{#@hX%ak)Eg9az~|$X!<)QEu(Yy<I*FZuyjKDej9#~K<Tw?=nRsEy$?XJ^b#%h
zPfDxDAQB=)6cR6<R7<z!L#2;3{P!INX*AvD3YRLfU_L_X@GVHB^pF$0h?eI63^g%Q
z4j=ef=`VDQ5GVb#0e0i12bpL^f;7txB4?yEbQqr~-Ln`5lcb+hy!EWq`C9;zrSZ|Q
za86qPIV4l0r*qM=ROvSr^gkkL(ywSun=ai-b6bXVwKLRYN-xDjCQEwrPt;{gmmY%B
z9BKGL)a6QFr@=2zI_d?IFAbuRzd*V}0JjUJ(-agblI~apa$b7zTaaR@d<3`>sW}MB
zN~M-kcyU4cIVE^o%cQ^3eVB5oPctenN;7E#RUv(81Avv%@xKAAlJ?V*>ymV584#DH
z=P!b*mJZR{utvJ)4*+VV>l&b?PU=NJdcE|SEf8st>P~@clr}^|@{08J8*sEqDzHIa
zv-Ctdyl=5eU-m;oTcy{R!%~~{uY;&;muh#TvO{X7ccoJ*=R!@FRPq?`-O{{4bZL(?
zV+ep=X)uM(u1f!IhL&s6E+2^WNu$1p!G7smv^^M*?l1s;T{`;&937PYum|lNk{apz
z8aJfY<Fv-RDV03}ZNt*_w5_=%?V#!Ywp95poEedB&PUy-G-)kNj7hsc2e~7S<$~Om
z1}p%4TpH8|G9e9o3}jOJ3cWE?(&yhsm)w(n{t1-bmu5CV%d~VZ0Iofd2BiZ&BmK!r
z1M{r3`V1`1Nu8btnU^Ngaf_X7(^hcyvb0&?56jXiRm4GNp=@eL+0YsgC)uS~Xmgd-
zG((G<><S%xyUTuHq0mDX{TYa-Y#oK;y<|cSIB%Kc8XD*$%b<tbS2ix9+22pLfL4tD
zvWQS{0WxVODv!vXUI;Ia%7zX@=`q<u-@)PIGWT~;cS08QD*%DA0!oYxk{R-$G*~wH
z1IS5P@^!R6MCKI<Wv66cK8D9KRHmlLYM9JKyT@=@0ezq%LiX+_ln@^&JER30B`c%j
z?9;Lf_n|ae=1ezWVq{yIKw@RB7oapw7PJZ?@v;T8u#_NM@*TJ{vIq2m(L~u-F))!N
z`<D{k&dMHX1eYu;q-#g#WJhQ~PLZ7nM6adFo}?VdG?{lGeMc`{Hci3B4B0!B$dM^~
zH4^wNS>rSi*|MT1!R5$y&^^Lj**aRd<;g;55s)tv`NF3H*(RD43uUY80WXp*9)rkv
zS?9ATES7O&0WXm~L<u&fvR^0;aX}VK>BwcWSIbamEtjoGg87TGXDFGwLUuO*x+`UF
z6ChQxuXm%Nmt=M?qwcbd!2+UMcIzDQHL}AuVX0QuNwKRsSwI;2sa{sU4kj98iz&F?
zDEs~n;8$daXi{vF?a{+fv#h=ZxE9%m_5ie6Wvdp!Qk%>|*AUue^K@F<A^Yc9aGkQ2
zx4?DD8tM8&x2%2_NRLcLPkyg#2Q3M%%4~L_pRdW(=TO)u%l!mgzpNw-<_BblY~jpx
zSuH(CH)M{VK;)*({RBjYWnwz9z9q9>=?8mTcE1TSBeJqy07qp<Wzan)tD&XW9a+_%
zX!c!M>EFPQ%WhH1<Am%NJ-A7k1Kl5(l35=^2i=ps{t$ZRzU;_4G<#YWMC+mlvKNa{
zI3v5^57o1>$!7qVlO3lyYF<`gr6glJ`6m<zu$TMt0X!^!jNV@d`A4)aa+Ker(b`GA
z;14+CEWb+YA{Y5aI%#l~cf1RwZgN&Oh`Zd(K%IxY|8IEjDG#S(M=$xd`>6Aluj)r5
zeB>_~V8K`ZA?;55<ez<R1;Sq*`T@KMkSkw-r6ckuBT;!&&W{BCm^}P(;E&61(qZBW
zdHxgtf$}4ico`&r$PHcu%Ugy4KPiu*rDBL&(FE?4Jnsc?p>kVFZx54u(5MwIf6oVA
zM9A+>p)gWjobV9dzbJVRZ9-4WU#DeGw48eil`-;&%iv<=E9r|zaq_QRz{SfQ=;cU|
zbLdSyBUdZ{NtAy^fu1CJxd-f?m7k>x56SZU&rx?y{%IFfr^ucAU_Mno@fEyJle5X~
zba@UE6Rb8F@-;LoX3BqD3*A}r2b7YNEkCdjh#a}&Qs8stnRN7<C;#UbdM{s|Mwjvm
z<XyDDFO+}xGCVAj@1k|WdAS>9*B8rAJHn?D`EDIlm&(Vwq3nWunm$HWCXb=*P`P}o
z7bLA0<$gWDSIA9&g1scSZ3TB(-cN~Y)$&<7Vy}@OqlB?qd5<GZ)X5!L5UH2v{Qy9N
zTy_K^jq<JkMJna5o`<C-x$9zxG|SJYz|j`@yU)R3tNiL+Xlavsg`%)szJW5^I;`@4
zMxeA)?(sh~txKLy-&E?B3mymQk^5Bw*el<*1C6;VpZy6+ugUXhBh@FLC<U%x?nyh_
z0r~5c@^M}M@$1k%DEImZxFNZT*0eX|M~6Ue%G*8#d|3W#C|Y()&QQbNZMpSH%FG*)
z`@IGHs63Nm4P)~EQFP#rTr>$2cjX__ur)64r~9B2@>^HHP0GU!z)i_tdk-S_<U1&d
z?Y?}5g6q@r7!r9PZ}Wi2jC^e<oSBs$6hrl#Je<CEGcVt`2g>Xe(N>D$*ejk`0{me`
z6|L7D6xS%E>!{e5il#X!Txrqctf-<)3KvD*Kk(aC;gt;CZVDfo7TguW$KZvBV$sjw
zJQZDk0`8?)Msu>a;<v>hJ_`48z<m{ZR~YhB?5D&8f5pl5w1^K-*#37or&vqF)=|a3
z6p}rr7|MnD<BCdJPM%PF@gYc{;*T?^3sPj$@+w&I+7-Z0Dva--E=2KT6uda4_@0tE
zLlqxW`b(I?zZYD%;sSl*Jwov-4VsaPZ@4fNrEvX${)6|l;ukyk7Ohw#Mz_T%4$=xc
zR>7uRfH=hlnwsMk|4?dof?{zixKu^vmmq1170zgAx}u~Tma-L3--7uZ#iKot%vEfl
zkAD;@_ES)!NTH;xtn-TXhhU*fu`2@RFDrzf(EL}e(9EE+M)8CbNUh>K`hn^cT}{wk
zuUJWu=mtgAYH*E;pJu>aQP@%htyyt%J0x2awf^YKR>ek|6x$SXTG6*Fs;<IrhvF0Z
zut=BUC0{txt<YznNj-`ugV80uitR0cTdyi&DEQl_SV==mzv3(fB?lCb(O&Jk;&-}Z
zFsRu0FYrT(4C=ib3Y8rI!-_l_mv1Rj{)_x6#*UzFL{UrE@kbTUQ5N->qMwo$?kI+7
zEqzz9haRMHMOGH-CKNA)fSWv^sG<~#DMf-Bp59Y<@Zr>b#ZFo&Pb-#FC~HRXq!7Ai
z74~$ZI;S|$3(0v!<V~otQ|{(KjlFV$zDw?){G=FeJ1Wo6mexs`_66)ZD?MoG<f43J
zFhCQ^ur{4XJH3>@(pJk``8zGpeUu>-ukllUdmlRel~3nDXMl2?rq(0M&*_~0s4}Ss
z<d{;s3DyIZ0hE*+q})Q=i(uvBbOG(8((noDLX<lxf$)?vj3)nZWm7KN5TUeFLL^eT
z)=Eit(MrW4coCy~*?`Je<xOvp1m(^W7(An#+z0cCN<ld!la=@vC=BGvS=vCQC~s0c
zEM58NI*<%y=Ojcjl_4v^<tX=8ph>yP*Xf#6o^t$eC@WOvr@(HJ^0Q6w{=D*?NlK|H
zR&J$uPl=L$1(l`B-{^}O<;tEo6kb#oCxEL^+J~X8QdvUb|0-qi55Qki`qJk{YLo?Z
z9i~=UOb2y!$}52|Sg#!A!F+@ARZ7)pRKE2FxMrn83*arv=Wl_uD%Yjc3)i9icr~<j
zDi=~*xl8%xS#Z6|sg*EzRk?xU0@sw!(II@Faz{E$^ef-mhlUO)O*DPpR(=zK!V%@~
zSr8djwoqHflzo)ac}Mvi4QzLnia{tFR~E+rFri#Udz?w-w>uZ$g_}|?2nPP1vYJNO
z`^wb@$V@9w(}L)MvY$>gXO!_2kDgWLFMx?TW#Jnj^Gc%~3hh*@4#0%H>PSBd5363I
zg@uFa)o-B8QT5-4>77&!wJ`6js@#Y|7uB`|G|5%<BP~s>ZmNy%q0(Ko`7~PZp=v$>
z&QtYSH_Usf@;sp1TXo=D5FgbtO6&Dki6VgyQ0<^$`G{%<9cmv{-EssurV6h|-Embm
zeNp>_%8xGg2C8bFMO~0;C9VHLR2TB#=qc628jw({YAY?4!c?m>Q5mk<M5oaas?;QS
z5vh730@|WfPBiVFR?X2n60Q1k2?}FWm)-_GRy9WVXyR0l(3&S+b^bJdm;{v#r9~vF
z&QP{$l1dl^a#poD6@X-wgf8QqQ#GH1NQ%ljN)gg@)y)G?lcCC>)X+@TL=@CysVbJk
zQnqTAw)Z)z_vs8ISGC0!9_FcRX^EMyI&cbIQlMHx&qbkX?{a7<QthOhx#v|aYhj{T
zrKESdM71{<<bvvzVW_^S3Y-I1q1tE7fSO8Gp%0W+sV2jLxTNCJS1m599*u)cwJPxf
zbl0eQwxh0A<+1^!PUS|cx_Z^em4G*>@@co+sM0DxuBc`lL7G(4AEVb=RST2hOq*(9
z1eCR_#wZ%uq55tR7CKcqt#mHbqq<7#v0jxw&8b&aapP#{HC1sa@O>&LO84$pJxnPG
z11b~UQM;~U{DLkWRMle3WHY3CnqsjxRIxWucvCeu2QsXZHbToSRRs;Cw^f^susf#u
znFD9WRV;6aOsIbTg)(p_RnY~goKmG-0OFoXa|k_jUzNKamZnuhpQ7%8>Ngs5XH*|i
zD#5Jk`}cvLQ|&27;k@c|T7Vr^pWO@Mpl)`BK}Yon<w`iIr<DLWtM`9~cDkq!Ho&~A
zddMF--PDV){j=J*t6!nf%R{|D4yB&zeXoJ@QtvMY-dCMYF*iT8PY8hi>fb3VBS0<q
z4&;b>X#kWSRcBKe<b=9+3G4={f1uenNd3PrK!Vj@-h;A}>c`x`g{YIM*TU4<6k`Zi
z`~L_ptP$!JmtZ1NU0(!)QEDx9!fCa@2TG&W28y7^sI!eg#HuGZ0uiVFD;(P5)wAAc
zZ-Tm-4$M;3ft1~wrk<d{a=Lnka2e`bUZ~4d=N*EwEcMnv^hLHhyO17dbzLDua;<7V
zCj8D*m%a&-ua;~EDNuh((|w_O!UbHB`a8OAabBH6PeQSJ^<U6dqQ1z4wo>(|Crn&W
zKkS6UGW84%{pIRI6zROEUP*~a73xp3;98}6l6Iz5>eH`5%O&+^dm(vQZOyt4V6{4V
zFPc`PPT3Eowdzh<Ak?WVGePRrAH4(<4eIb#02|e}PNMZ!)W1A|hBm3sQeHx{`X>%_
zx2QAKaI{tZS2oPIsTa}<->!D0iwYfTXUgI3RDbs&a9!%oK9FwpRqK72?@>QOA*EjR
z5*Jvys-De9<u$c01zh^nI@<U3t6k}IXh0p21cTSrKR*B&R7X&b$B=qUCAb@E8_J5h
zsov-g_^`V88vt&pFH$V^wz@$GZbY3!nFyomPrM;Arr!KE&3|{)rbdvv>W?U*Jgyc}
zmhFVP_$~@3)kX?gOsPMh^sjsB!Z?uoYV{>ZPODFZLu6JxFa<KF{%|?kGOsq$uIjL+
zjK(PkjXkBSIcn^NK%6wc^g_g0BS=BZTr_E4Qoz$y^BSF(xM|KUMnl~-|IoLgJTyC=
zfsChS+ZG_aG)K0=gttaXTP+_=F)e0&HNz4}`f1{Jf%t1qHKBt8G)HJGI-<$=1noVp
zSwIKuCp5p<!>2$^$rET<kftRblEIpvqv;0bNsX4)@F5z{g(y9xsn`jbP|aT2Ere;N
zD9jbEd37zcMQHBPLN`()Ta3CW%|1G}IIY>DKwY#Zj+VADnkQv&J6_{Nd8P@Pr8F*|
z(G<~>kf@PR6f;TlH+?DatY*dnv({vds|`fYX?}kl=2JAye?lfzGx!ronx^z3@adYI
z-QY4bi}{eu)U?b&GE1{(60T)ywyMD8Xiiek=4$wKwvea!y$QPWHS_a;7ies^z~4g6
z6`D+oG%wOZ?7W6W_rZ#-ngM_KR-)-I1F%$cdn*tZGz%%syi9X{0}PgH*3${cMNRp~
zP*b5vJ_h$IHC`V8U!|$^g856DQ*=N7vZjSL>(!d(en{46?i~WWR`Y}dxH?VBap3AT
z|0Y9OgXY~n*lW~Sw=DzWisqY-Ak(C|H4in-n!)?f-J)rD5~8h|Tra3;)4co}3fndI
z4FGm%epm!;otk=zkalVEC<fK732uk79?iK)aJ?Fz1dywmRiEI8xu$t>ExM~uvz)e_
z{TlBb_|XP6^HzHOhcvfN!Nd*CWg1v-YQi4_H>_DqtBzZm@<iZoYf@>|KB6h1Z01o-
z3>_7ZX<}(Xbw{)3FuLom=1nGak85iF1a3mJkYZ+&ny2YpX-e}AUF5o_>8yoM_cf<z
zLolsbzmMWJ4>Zo*U}rSC``~6ZQ`L}}(`4B~_q@iL?uFQCn<>x6Ufbb}Rvgwg1*6bG
z>-!Q6I%-2`7Io6TMyaUI+QI~AanT;6P`#@*hq8&?wBwyH@2>sx1hjZ)pLz$xQ@dM2
zH^98K+bMeMtsT|^@1xE71kU(sSAPvPe%k$dG{#@+N4M|-wC^OM@QC&e`n8T~FOPy8
z(@s&`<+%3oH(}z0cA8uZ)Rs6wGDv%$k~4y}je#gUsf|vC>JaTB<N(>6(kA9p25zYK
z>K>R6(@KiqaJcr=L68XTG#yn(YX6|fL$vl=TJptcU!fg!thOf_y5qEawt$P*hHxN~
zpdF-8#~E$IdPpW}b(CI|q!mzp_gSqV1d_?xrF28~oYsrR^AzpH5)@ifwZGBPRhsrM
zK1$QI4i<E2hPLZnRAy?cX~mhPeTq`1vbBj1K_o}}2K8*N_8=Qx<Z0KOhQWO8X1YRL
zpe^_vb_=zuGk`17X2?L!YcG01vRE5K2jwN&?X;{a)jHpT<OQoXCKsh;+V?1yRIdH?
zIMiI!9{L{)R%ka+VnL<$Lpl<v(*8>qZ!T#YX?uTJ`<w`M)!Kno0Muyz+z+l+`+^Z#
z>a<^$fveZ9dL4iUZ6+PTHfmitD7>OQ_y|ao){epv&06c~6d+o(jUMo{Rh#)a5N+E2
z0g!g>3_Uv?T6;H`=+tgrhbN&+JCzO6txZWpU-W2SrNN+A`_MaROrKUy3$cE!n+Hq`
zXh*tX_qz7wK5&EDY!f7hw13mt>kaMxU68z~<-OJbI;<VPi9WfdT}UTix3x!T4?Lm`
zraX*M?I`Uw#<bp3aP*GWmQLaCYWLH7G_IWthldl|w1Bb1Ro1uZSm?gCc^AmEw)uI$
z9%wJolscoWrKIgyZSKQ>&1t<UBs#CXOsgt8T`(6a?R8GqVD7N4h>|xQbgl0J=cv0z
z$H-1P&z~Xbth-48Fc;nTbnVnt_bP3X+;o*esB_otwtAuuJao>nDD~96M&`YAla#FB
zt$TSN5I(x+OVB=FT?HLi`013X@X24-Lo<4S?xph(Iij1SJJLsWIZ9YMrc2xhWyf`f
zr6@e1Yo&{Qfx5e!fD6*?c89;gy1(9lvXi=&7#ajZbg`7Da!O};8cIWTB1-#;(Cuo5
znn+zs2uPGJoSwWG-730h8ml`<8M|@1{XF=4Mpr0DhbHQ_(8Q6XJ7)(#rY`tbSjy71
zy$6wO-4Y6==IAz7z)-I4wFOX?r>kE=$&C3rCC#t}Ix|g;g}UiWAVoSCO0YbydwnS^
z73<#I0yQPNe{*4?RA-{oy9+wyJFrxy^P&Ayx$f}yaP6YbEgm8jx-XVMq*8ZC04-Iz
zpC~APNtZ={%eoh~!d|s5755-Nu&L2G-$QAw?vsZAtkZo#k^Xw!P(R#n&{^}~OrtKA
zvSqI54m}1nO}cmJmSMBbi$3DeqI)w8fL2{JA8l&W9ry=!+jW+JUCH=T&Wq68qr0#X
z&iCpPX%Bf-H^GKW*K{lGA>XHa(GBwbx&xGRJ)k>7_dT!cPM-ufs9P2Rb3?j$ib~zk
zInbrmo4PIZdkpJ#Q7rwI?n^oZyR94bh0YP(H}t8RQC&hgxG|lhm2!IT=<e);=w00j
zT9}UOzM#KNozNB1?>VV^j&4X#>539y>7MSnr@`IVSt&(tTKCaEaOQz7{Bw{wT|Gq@
z=5^8kLbsj%j~FPk*GFDKPaf9a_JJV>{lD38#!){t4`ojJ#0^#;ob`*ofKnIz1{z~s
z^~`gqbkpykdCpy*84qn9`geL^&{Kao19e{dEIPLG)_+Dj93TD51E}-WKm9Tq;iqpv
zyxqoM-$Mx=0s6l6^!V$a{|Ays_3zQn`I!C>$_G2HPyfya4_A=BkLHA6J#z-SPwMk2
zXCOrXHYJ~&(mPR3Q>cCo-S`jFKPrJpxPB#tnj`c^QWL2!p$9KYzcLJtp4NNTgGB4U
z^hH}@^j9~6#OmJ(1t3m;iLT7Y>z}5`M1o$Xcyz%wn=|^^HBghNcc-MjB>g5@M4r{F
z1aLoD-@OWmb9#F^SxeC$asZdAH|4{bG(Cqt*_5uYtOS>#|LqIlGWCf8=Tn&0cgCPA
zPk)rQrTO}vDF_zm74-dyLVZ*z3XAkV(WdykzTyeg73<^aV5>wQ@jaB3>T9>d-3xkt
zF|?HFe>cNGxjyVZe!+|Sb~0X}|LQvGD)qn9NoSS*x3y4qNq>?u^DgUit#tfTtuNt#
zt<iV>iuTp&-&~2VsMD|4qbc=z?gDtxpr73fe53w~0tT<>*U))-lYSi~95n0w-#}rD
z{&V^vTJ?`mPI#N1N5_}#`j~#;I`rK%X>{rz&x4^Z{bv*l=+!6wMXR5y`t?yTcujAi
zJl#IM!2|ey{mweLHlY8GE?QmJ|4r%cgZgg-zz^w9Q+~${eaB|NZ|Vz90x+!inS)Qa
z^fLNcZtKGafg91UrL?(G{pQ7hkLisR{JW!XzlFNHdP6;}e#Z4bM?u?!{>KF{IH?b!
zwAU$pB#nd9`cw49i3j?3>EvQYU)}|7RzKze$vJ)4b(o*mcTkwZ&hYX8h`nKsGC>X-
z)~|zI2g4x29Sy4&z%?hsYa_7hY}iiM%Ulev<2kU}xEj7pgn2i^R}>a<H`LR9-^1|H
z*O2ivtdD>RFT=?Hpv~J*{w9czA%kvt`x*{V2-45sNw+Zk4ZQX6H^8u-7QjagU(cfv
zM-4yGN%S#8=Vbtn8+vKXI$;Q=LybVgav2J(L550-DF+++bzn~#-lbtG#2}%?>M6sr
z!yuuCIhrlQ4Ez5E7j8Hi2TKu#*D6sMX|VkkfGC3_oyDFu4B0|iwBc(yQI0XJpjRu_
zF!3nr;tc2L!eG4Nd?`qRA$kuyJYzL1eF<!$;jb0Yon*Mw4g6WdIIXdh4Tqv3bIvdl
z1$>I(@jK|JR0Crey3-6X_fVH^Fi`j_!=R;8jZDLr_W;i_tfSy}wn4-Nmt)vOUwX<l
zxKdV2o*}6a_VNwS`l7DDU|sEl((?wt<-ivkB)h<s7#!&6ywtFqvL`MWu3mwqGQ&rm
z=*x1$m>Rk-8f=lPW>aA};ETFS!;-@wRfc{_qPS%EhLVXc8@{73MYW;R0<OmJ+iJjT
z4fkJyg*t=nCN!enu-!^0Qw@fCnt~e*#up)a#c=N&WSR^g^?@`Sei5UEEe0vYq+1QU
zbpW;*BFq4^8-yRinGVA$n$bE9v#F@-GMuH%vu?u&wAAh~T=z#;_8Oj91i)28ODR0O
zW_b8LsO~caoul1<zafM^q&Z*+Yy$AQA%^z9g9cmL^$Zyv&=h>bFs=aNrlF8Ni#cql
zr3KS11DmeL+%}}8LHCG3M>qaP4PR5f(3l~W3oUmHts9}`uE9XJrN<4~t6*rt;FJN}
zq~Xhl79Yf`W*E<ciF<|=THW3^G|)6MZFp(|ZF*o>(hlH^K}5%Tvj*->)Xf=&H$%<5
z;m;WW?2NzC?`v<|N2AtZ<FXV09E|^~0_SK{d%|re<2Q$3(A9W0U_;g_>+VD715e{m
z^jQ)wqhT*NZ{xpPVa~_+=>-V-8h@h1F+byp=YjS&&TCN^U|ddVN=J+r5VW&7YJBN!
zkYmOdXt#gd`0Ndk6UN6Wwi;+$M*~BUaXSrN!A8ORC_HIAeiZgXj89q@L-#4;4k7#u
zHE#GXsoD762S9`y-M7M0gmHB_e2O%l4+TETnDiyM)5a=#oT82Y<^mUE+(^OASYxsa
z+>SE_)7eJ6F@QcGl3=XRLD?DOKXi97(HIzuu1hjXXs$nNob9v%m~3pJDe0Wi>sM5!
z7z63hHP!g{1b}JA59w12>Ba!c%g8VqDQ2H(%xOh?vy5vfeJ$HqdKrz$F@AIpb-6}8
z&F6W>aXM_uH%|DWuE6+PH<T3`pEX0I$e3k;`SZr7wDckBV&h%P2PrZBMuT*z@p~2!
z7mUR(qcLU1gxf%r8)G-2F&B-DbSSMbuBS(|(pW*+169W5XCQLP*r0^c8lzbSe`}39
zk|0uNWYIRE-gxf`h%^|VrIWfw<0~s5dBylL!nRhMCgV>V(28cG(^53M#W+S;VXemR
zNVLsp=>*qqWYM>rI*k833({#cr$bwp(Lkr#-Nwv4@Ttf6Zy_XmjepTwd(~J&Z`d^>
zs}N1<GkUZ@b-&T>5f~aUe&r1Kbz?H!1+)$tc`5K_$QVgM#v8_@qj319G4vN8hK)D!
zz}+(bya>8)8&^?Sal{yd>qj=DMuQyqG2@rzsJmm_M^U=F#=mLk8#l77&^ck$MZ>j8
z;|?17ri{H5w7zEyaR%<bvGzr9(^lhOt+4dKc>H0QpD{ka42W4{1FZz+jNC`T%^UM+
z(6KY=N1(>uBtq)3&0*8xNdO#7A2)+In%3@zK_^p&5;$j5&nxi4#k7znL06OgQCM&@
zt)Q#V?xxjr+rz_jXf4cpnyk`KfbcSvQ5v?l$=4kQeM}#G45hxNu-`%aOn1kD@Hdq$
z0SPd@G>zU1HpvzOf70~s8dwT39UKPylxblk0HLNwzCvM`iBFd&!cEJ5Kzk!h_vxTA
z(sb7yby21bHK;pnO0asNGS=j51ALrGV1Z1$$<-BV5={Iqh@LUceG8IkiW^5iCz*QQ
zM=Q>n2I!<C+0?NJ{+=^ELc4(!Q=kb-Q%z!8UZj~~X(f<us-?Ls!!$#)NT$g@1{ShR
zEfkc=Hofdb3+WuwM>N>wn)Ve!G|%Kg`D2Bqf@{!LWI9S&+~-a93Xo#c$L=5{rVr0T
zvedM01U_9bB?+LV%+x~B{c=+aowr;x{ka^46{dit__ZocRo8*5GO=l6bIDZtG3qXx
zobqUwR&8P?!C;N)?Pyfiniv!rt1}&>Y`=Pw{U4}nFx77aX)>`pP}pqh`2Zp<ra{WS
zX*GpWSfkDKaXIX^o0d@6slya#0O>R>rSCj-nfmF#qua!xSG30zp$4wkR98<+o~x$q
z`=ITb$zp<NpUHd(YWhuCN{|7Qwi6A#Zu%k+b_Y!xD6?nCH263qZ<vgfBy!XAY$&*4
z)9bq-a?A9+1c2Kn^W&%+F?myZ;HYWu1K1riouPr^j_F&<z_@F2_!NcKaZ@RMu4cld
zpbhM#Y4s{NGi7pSqGzW~Nonxnfl2BEGGj`sgQZ!M-)V4jrZl=lF>flT`#1LH#svTz
zHeV<P+`-&D1iOyrNcz#8%r`q>*V(MD2Ipc<qAQTDW)=lL-K^#}DA~i^9KQ;s9%jpJ
z$atFLXus}dR?!Z}+x&1kI3M#^A`rgjTAHK$%+FF3$lvTr3*!KDJS~2Yn5SvVIBGUr
zK;bd-?gy}Y+`NSXkSEM-Mes1typRF|LFPI&3WLqoFAJgcq`Chtl!lmtJ7DRQIg`Fu
z7;4^j0bH1QFYU?0&2OAWn<C8L(q1gm9C83$lvzgGm(%8P6G*g~^AMEAm_r@Vqp{{^
zY0Z#eKJ_u2Ib#+hyl0bWE~HzMN#<;d`<yi|u-XHdY`*^-ES)nOxWK2FYbfBFYECVK
zXqver6ou*Lw`nZPFgNzXnM`vloycaHYv|fiw)x8gkUVc*G77HP%%G8}#JriN$WpTl
z6Xq|NH~#{IWoF4yz%QCty@uvin5Qq$I9X}#rX56;+0_v;m&}a4kf}EFX>C|z{_A(t
z)tZNjP*`W4Sp#kL=413zG@700nCXgnAB~+&=4Jlin$2(j7d$ZUq35yHtZf6J&Fq{E
zk#_UfL1<Zrx%48;cbWqXw2|#H-{-+@x4AYFE$lHb+yR+hv+ZM$xoTcQGwn6=dWtUg
znJ4R@wBLN|EA-`n`5!vDyKerG)^>yDymvr`%&rRb%nfrl4GlNVH*J6$HuuvgaLe3Y
z3=eOcJ9naR#M}^0H!McYQ?!&GGw-Sc;*Pn~0`qsxGnD^1ZVo5EC(LfNUYIm5p=HjL
zc_*D>PMderP1grzC2c-u%*j__e%74Og~B<r%W_E0n@1=S-`;YMg-$qZxkY;g2g@HV
zAdVK%3e;JhEYZuL&Bd~Uaz0!wAFYOYH_LH4#dNn=d%$^El42p^Whozl8gI+4vyk+$
zq*6%E*J3jO5kJe~SE1D3(%%DIfTd~(bw@1uD?pA~m=q^IX32dFxZ{>5=)*E6EWxzP
z4YXRu6Hppt8KOmZu*H?4sV6NDb)eZH7EiikaLV#4<!6LiuF*sgW(nU1k#NhaBk(E0
za;yMcq$T1ixF}0LtqM<DzCH<q(Uy%>ATgHemmm^rSuBOYILo&cXhgiFgU(<RECGeZ
zORbzx{P2mE5;{*!vc!A{|IS(_mVisP*i&9Ys--^!;%Syj+6|{$6cpObu&j{5=S)i&
zo#ka&#?C=9$6}@BNUmj*8YIv1%A=6Xx3n*V?E=fo6pkyhq_zWh-Vz-KoyC?J>)WU-
zu{@oQ=9O9+&q1cla?T44Dz|(<Dclz=YrcU<h2`)w09IN~bU?Do@+5_7E?Fx6fThcp
z#gu(qZ5gHW!5YiR9e7`B>Hi8Q>MY0p+u&H_k-#-rw%R~-qb1G>u3fQQ?V}ITH(3_>
zqiM|+FD?)*mV0)PX|;Sn!P_>=E_w{wEoVki*J0Uk47xilKhTrbWoep#7u}X$>GA8a
zgwq*BujM(~4PUjaJ_hfvS$?J*<~~bCJsj<~M0|&S8nE<Gp4WBDpKIva=b)uT3(+CV
zm=2}Gmei}Tbjz}ivXgFGUY!PF#Il+KkE50m9z@10ODV7PuI1yEz>Qm;6`*j!;<yal
zq-FCn@M6m15(V6S%hz<KHEjv70eN5vAuThOPm&=rYYD-tWVM;M)X+A~&Q^RFcI|CP
zCEyO*PKN^TVEe~Gc;RUKDXmJJY~QBS183W(9)~s;+czoR?`pf74hG$9-x&tyZY!+?
z=V9CPHG0(3)<6%Vm+gjmbb`07j-vlQw%1mo(AV}{61v3dXS+fT6aKcPboLlv+Z2S#
zBenv%#(dN^m69)y*}76(`?&3olkoe5t<$Ff1ln$R8U6;@_R#V;*f!t?a3^gez6CtQ
z)`PZwr)+Z`g%_c=9Xo&vv)%O!w1nIK+W|unwjU3m@U+#|{|?-Uwq2V7V2o`pg{Na}
z*;?S^Y(GB-FXC;TUPEDm?Q0u=NVE;x3CSc|>lqZDwVf)0-DKN0X=XcTTS_M(DYoX%
z;9;t*mmGEJwk$IM8MgMcoy@e=Q<7blZPzW3Y+LIl3VG((u3rz5YdfD0-|}n&e?gn_
zZ96={71+Mj2(Hk!q6vuqb9CKtSyx?LD>W-iE8D}gG_|+PRGz)}o|bJjv$C?Grj|W`
zY#Fjd5o8Y;%1{uMDTp#ek)>=Ak)eR>{eDmUb3XT;bH3-?`~1ee=bZZ^-)>m}d@8Ve
z`Z!vb>~2totk6zEnVTZJRyqT8*{+f{x5ak+C*j3ayA7WJy2S2>V-P8|8=%vPWp=9<
z0<+w1p3NU7uGx*<gJOl<N95uSy9vrWRNB4x31Dv8jZ&nn%FfgTUbP*o3X@P{_cxsk
zt+ku~6UZ&QFei}PcCt*EsJA;#kM9OMkE^iTXcwJ_&KA3@4`Hy?F8E)7-LbpA2s6`W
zcXB&T+g-a~y)lY*yFK)Xzi0Qs3n2IH7?i;6v}>nLXP2EX?R&cI(y?!v(_`md4QC$M
zjZv2Kp<Na&1p4e6=-_|9onI5&eq=ZN8WaZXq|Q(uv|GCmts%Ru?tmV)JLC$K5xb{?
zDd|6IXWfM6nB5kCI5lpk_!%0Lb_vS?GiB%G3x}ueD(GvsGj>zkV8Wj9^aMm47{j#i
zab%=2A?d`ZlwvH-jNpynxiH#)fr2X|lXm}ZjE)}x?aug?azq{sj~3YTWVkPWYS#KW
zUW`v3LBpHT*9J5n1}7LYhZ#Y%+4W^CH~>XI#w1<q0gN0oc!3PI|8G}bw0W-v%5esh
zf>|Mq{wT0Q8ULI@>jWdA8LcqJP!8M;XGosJ{6sK(X{#K?2-pdcXvWlM5Q$;D8->nT
zM%*HF#xYJGMrS-jL(9^Wj3;UNpUAl929YF2`UP|*Gfu^z^AzI;8@*6ZGv1;%XbNLt
z2$-o1C9P@F7;kL`NoSM{fp>;cZNN~@GA^zIOeW)x*%-<>#tM4qWHBOUVG!pTf6~_C
z0>ev+pXVaOVK1Pw89&fPnah|v4)r{SfDg%hMlFSw3K)k&ZGgGN*t-nPLPqMpkSSu^
zy9`py5K%hy3ZsF7LRT3{w6iH;EZ7TPDMM?*uT;iJwS!1GL*@ul!Eguw?>eLQ3rOBz
zR270$GMw|#d6O|ldB_^ZC>H~)Wt@BouGKM^gA_fu#jw;t|2AXG-{`Gp?4x~Q1LKwh
zNE72?8b~w4L=)7)_^uWHwlaK_Fn@>f(@tQwF+O8K{Vt=7${_ABKJkJ=2cxzSt^15u
zyXo?0<PHP6i=ny=pSl?fegNrV+(+aQA8cc!zlQmG$e2e(W4(-z7Xq}8@g%*Q9x>L?
zQ)7T}G8-a;47YvoVu-QP4D4Y>J>{lG7#paTYLwwmTbgmkBC1xIU?fk#i%Evx&ybvA
zOq&5c&Dc{7-VDQkC4Lcm<}Z6dY>v$LsOI`0^DLE3IWcEyL7bUi(+}&yWYdDjmD$k=
zMK|V0A3@TCsdx>%L(K7);fyEqeX7OxVpbi6h&OWuZ5Vu+5(|hQvxVLm{>+RYpb)@(
zZ!Y`|#Q#x-zeku!W{3pYnEIP=@fdSQ7Mj6KFFrtzGea(6*dfd?T6=^t1J^<E1k;Iv
zVqwfL&ck2?^Lt8VM>3D^Kr4#*_<UH3W~Oe37ctD?JLrsMKJdg?;+W&KB8z9f9Sd@j
z$)KlH0(13OP)}sq4p3=*GV|qe7(B%^H9+w+^OJNqoWj(629nDBb}MEtjk&J^`svK7
z^DuFiIb8&j!Hi0WznRR<r9eB!ykrJS7ISD6k{6k$7C|qYdGIe7%wcK*p^(eGL?n;-
z^d?L~K2v1#g82gG8&n}*$o!Zpj*6HfI+b{tIdux=i<y6i1MLd)#1_ocRb~t=Yf6~)
z6wWMT?xeR^IrAf`D!9gU+=EsHvxg7t>&!KDvhxNrlUDkbOra93o6P-3K&qGt6uhox
zZhy@Nv>K*-81C0GzoP?1x0n?xVE#6<U4zbgX3<WdH8Af`)kq`LmxERlvvVtWEzG0A
zkZffJb%Weto}v|78#CrjVBck~r087-^EVS5z0dqA1f8AC=kqa^E@m1nYrB~((^M|m
z!)%g5<^l6fihB1ly9&|jV>Z7F($D;&4%m;FX*+;6zzo<AkwK=E5=2AHPRa?6FrT1T
z%qWw28Q5dY_by{D#+i1{LvMn)okCTU%=NVEnPNIpd}ErKM7g;cW?D5x5A0c=({<^<
z%CLjtLDpib-f&`_dLEXXS#mnG<HFiZZ%9|x4JZ5}Zmi@4h`6&JY=*)i*75&A#FM3>
zdTuY4bp=GcSw%%4KCCCdhln3*M-*EAtX=;@D}eR%13(9|#I&`r9bpX_Fqj}#)dCFW
zC`-}-OTnyma{oAMXB!klSmLLk5z4Bh(CZ1-ARVm^WBo$K6ydDzX?YRJ+DGq$DAulF
zC`7Z~t^tW*y+sk6SeD-#P>*A6$%LVJ)?QkBpJc7AfI@<e)p!J=iL5KnfSJTfdmn>2
z#rpF!G)}WZhhQRwRV{~TD(gjBkfgC9s2)6>b%@H?&#<1|53~%{97^Y9vKCN6>l~|?
ziZQZSulhjpJZlyMdf6<0iiG5_f+!@O%lc_ChMUK-JxL+5eAconAO)-?TLF5BwdXyI
zsgSjoHn~NtKj@`c%xZfaB3D?O=^rRwWjRtkX$h-t1w=|&Kd%FJIm?&gb=O!GO7JRJ
zd+GMS!5SEcNF}RKhPk-O%Ambl6|03FsMRckZ4GD*Yu`O!*RmpL|9p#e!v*9v>r@#O
z>sedrFj)iZeR?o9vR2Y&p^25r1FxC&7#*~3WnFk2*mqb?2O!eMT0oJ7yDZTZNIPpe
zrNQs9vfhV>oh;7^c;CfJV1snC1{)}P*TY&!tMv!0+jQqVWNp(yw3pR=A836nS6UnP
zv({Qc23Q#s^c-YK^5NkSOGbgKVOHS^bdInl&I4tPwQdNlaaN@qWP&w*ADvUIwUnWs
zX7xp)HN)CQA3?Qe&;5<g$2qWj=wOc{+p`P5(?Pas4X~Zr(fJT{VK1c88&~#^k3++a
z{SuX@xw9XmH?#*^=ZZ-<#Ll26xEK2sF(kd&sWIUBu-WwXKg>4MGuxNF{t58>*u9H@
z639;d2dyLQ=f9xyIYDg6PBf3QH`1c;7~6Y2G=kXy$!HyCe@!8Y5cUN+>L1EJ>I3~S
z_A3YBML65?Dq0cjbXu51vSaAE9L0VnAG03A-a;|rSoXTF;6)s}hN?VIvKP<;If0!w
z7wU=ZS}(Y5OJeIOFqzE0_bx<Fv8O(P{%Q6fT!5ysHGcpmja^AMP&)g|mmzY7y@l@7
zv+Tg9;b8{*`ESsf$$mQx*F_e4>s+XxXNS^<DKD_y=#cJ3b~wHEv)L1LTp)*?OF6!L
zwl5bb1vYk3DfBO~n>L_X$S&Ro{UY|^ERf4=9fbso*@tQEeuX^}3z4hr?e9asgx$Fn
zq?En-9(ZMJXFAhd&Sp@t#5J~<4wY1}PXwTKoxO{42RGRJsRX)`y;lKplYLeTg(|jf
zG5y<(YWDUVz|^tdp^f4#whwLOZ?m8N38MAvsYHyTf&F$A%r~+(SEAL#{$dtd&FsbW
zs%l|pP>8IRy_yMfhyCe%sJF47rh?tO?A=re*3SNsBDeS0mh%`=2fLq&0q(P{wx2O4
zoorPO6ua1LUpUjv-l>6p4|_Fz0<)JrMP=-L>{VfC^|NnN=KK*mg37!G*i97QA7qa$
zgNY$_+-iUhvybft<_P;8T5*oD=hDSC#?GLe^Ei7WeK&D}{oOb^C)uKON?1;@f7C#9
znyuT7)(qS53t;Ryj_&}}fm7ECMMqA_1GElu)^7&Sg){FM?7DJ3c?15salR5j-JLVb
z9oQb6FS#IxIDgS{-ILRM0WB|%Ybl5~=hG#y;KTWwuFk`pkP(U;_;Fgs;Eg}WgW|^l
zoUR8@4CMSmryY)Poal8H#EGWD^`o4YZ(->eXEm*Mf;pQh(0!Z};16C1=TACSe}ZFA
z<)LAm-gcM>=ln_wxCl-r?Ykm57v2Leic@+8oza~Ap_ILf;bd4L8p{cyOj8^uqZ-V3
z&W%kV37qHYLj{Q(Us_NlafV9aS~BOl0+vp3e5Rmxnp1unUZils=|@ZDY@@_l8t3yn
z=uGE`-+=lV&PQ~0Wpaw>5qgf}^(sWNIC0;>8QXb|E9HPMa1PNGagl>y748)dpK8K#
zIJs|t<Z@0>WG|2N6}?FEIT4ePyu?|v6Xpv!x9O8HMV!=O=w0S4^29)kIWN#R&aQC2
zc^Tv?=cnH=za^Zs<xnW){6kd)Wt>0a!7EpAUOfo?3Xb&=+`rEGVH<jHa2j5MPnDd-
zSD|>5vylyhRU96DEv1@s{4^A5IA%(9)^Zlr0JM%X<o|Kai?$QZU^Q|Y{)So;XKn#n
z&72kcL0UKgA49N}^FR%dJDlIQ!%iD#??ZIn<y@n8Vms#p3cTLuj1*uDotzgY;b#|T
zHEqATIfIl%@8PsR2l9aPZx{S~$O)nP(_W4>9twS&NgG9=`Z;n+4?N;@UxVl%r-hC-
z4skllF@|BzTn<c(aLh>n9p!xO31`MQCK<>$XPGk`o#1%A0JKTY>j@B<;w0Y!Z<@1p
zGl)Gmo(i8FxPtE>>BwD4-^oA7{glExPTYO<HZ+~Nw}U}kxS3_J<jPH^vjcA2jiJzY
z=N5hhY!9v_9U`9GX4(&XahK=8k~i0xPF47Dk3>V^Fn2#)f4*EcJ(c~qyXX<*&wc7g
zkO1xr^zselHaY?92seR}ILEjHzVxx7U@q@TjQ2Qqf|9=>+)b1n2<4`%2RXsbe-?g+
zaSzj5JDmGUEKEdji|F|h$=yuprYP>g0Z7Jh@6p~lmg{1HWE^+F73jrthbbU`lG~UB
zy#($g1;-M(KX=2KB<>ol`E7HOxdEG?c#7Nk5)@B!Q|L{V%8jo?D~<aJRTQOjeduL&
zhTC=ocF%IxQdLL>_db2?DwE5gkK3N(zR$$4v$(sWfqkCqvJoN|xCONN%;vr(gL)44
z=t&sL<tm#%^0>aV__gJ8gXlYe1>EgaS$T>3P8CcPa`Qbwin!}`K=CqHa}_=nbKU7o
za0&Mst+q?K1C3B9<ML)fvYh)t8$_;g4R$bC!43NX&Rpld^BY8NaGRomQpt6py5yT&
zPZ1QVxT6msStH^WIbwvh+&OE&tm8%}0{a%%Os|pK-1=t7)N}V72WjBe>M*5^++Ny#
zHE|#8fkHEP{s;aJw_dPSRKomS?w?mN>~`*MI^=qfn@{V44(`?m=)BLJa|F<x-0wey
zWEZ!e&M9|uN2kH-;cogH<RRB%B}96;4j%%#kJ~{d82wzo68Q3ntFnO%aNqwDn1kGz
zbT~1@b#H>?FgL;W1@uR_T1RM%a-G(~`~<hl0nAA*m%_SJ+yMHADbrkMil)tQv*?o#
z_PoHaVbFmWN*+4$KBh0-9^^^?hPo54(+BF#ybL4e(3KZS=>RvLa~kyAd1<f084unn
zdKVqyIV`ck8&4kNE`CWbUgP%w_2#|41_SlsZ3zMIFppCPY+qgh1zP-hH|hLS0FSMK
zi9p`xDbPE@`|2_}gLqxv!{4L4p;>4h<EhDDFz?kw=pE;UH32h(_cnc4Ae6T#6mt>A
z`z4IlgyFoKLNp_Ig&a5)$?KuzV-zp>I!r|KtW;kY!>dg}XDqLd9(r-S#w?5}p7(M;
z44&k@NAIL0p5PtWP3Be6KK>N%F2(sz^WMA*FH(5BXf2t_>!xz|G~P%Z^wN3re*5p6
zLA-+}(LBrhr5pw`cy~&magN9T7W!GdjLRVBc|P<MxWKDqLH{Dpj$W79yl0AFH;2bz
zftSk*rLbWh@93*=EuSZ%2wwqjBW-F5dH$3GDB_)>`uNMdmA``&^Sr2(({_dDMlbfO
zyv{7>m+&G2pkK;Ud;?O(<7|a!Ij{I-jOiM0TLH{p=Nab1-y6IvDkiApeL~rWn>>eM
z_*BKSqkVieZ-56<!@DR0N-fWxcHVWomLRll@xHkQXKwR;kU*i)#ydnOS(|u)wBBsy
z`TPXzJG`vlz-;5ax)h_o%X6i<?BTuT4TBGOJyaX~khl8`?Dq0jP;9)9cUcY6&znOl
zpGUm;@h~yK3#G!kLEdXZ3~-1icfcTqd5`^p)(Fr0d5DbiY`@ab#(2fFbsy)I?126R
zFNr>XG0AJCXV?@kfD(?=ydk>(W_TOkfHU^|E~=Vv;CKB35l8;>1sK{v{s+II(~1A`
za~Q8PzgU7Hx$vhcjNr;&@H-5;@#CpZ)SYjoYutms5Jh~r5%{y;#jrj3@sv*Y;vb`d
zdh^e(0*ntohMs7L`E7qf!<WA*9G!mr79X_y`8Q191@JdfAz>iDgZA-9_}vCfeh~ko
zc%U5Re;`BWG5%-tN)G1#Nx$-O{#APRh47OTDViP1_oAoP3I0kdOAO<eQ!#xwe|rx^
zBlxrEM~~!p(^5E!UqhLjX#TvlP>A7oAAx!-e<#%=#_@HJAQI2_d=*o2l0Qn-T?zb?
z6d_OK-`xw5B>r)43^$pdQjM88#sAQrz8Q3yzh(_YQ}`8h38eD1@4{dj|6{8COXqjf
zSIN%s$Bx3Mv-~}jO32`Er+`!@e}q;i=lFd3ct94vmKO5o`2pWT;R64SAJLh^e`5n2
z&E;SE2YPvY2Cb&@`KPEPp@1(;r2Fp@zlSQC3i*jK&@bXwUjXwmU-BV*D&{w}qIHG8
z{{bvr<%iL;w}jtLMSG?E?R2q~@w;DydO81IE$m+7FQ#ubRPc|}a`ietp7w$__>buR
ztK?@h(Rq`<JQ~nd{O2j<VyotVy9u7w@SDZ~Q_Fw01HE<pj#zZw;%D)paho4i514xX
z-;_IU;4kfm-9~<l37}2<b5u3m%zyo3sJHO{s)84-{DUnpafkmI9gJ?{8!6&;mwzb*
z3hn$CjQE-E@sDx9>#*^+P{F``zGxd@I{Du&MsFAY9eP7|^AlTPu!p~v>R2A|Bk9XU
z5BU<h8+-YUAEMRA|2GpN{ro;!Nk8KM+>h1({|ibs5Aw(IATq=^Rm1Kuzj`M;9N}-h
z0g+MuA__)~@ofz>!f}3HHkcE9{%j0;lD|0_GE@9p@$h1rKSjH#8U8`461NvT9|{Er
z0mlm>j)JF`K;)p{;X3e~1Yf@cP-np^+K0FZ?rw*Ot6<}PxaKC%JcpLMz#55`hhV-I
ztwVw&n+()b;7GL)UV=dnczReMpap`jz<v~+euBn$jMrbVlS)Sd1P%+J5Gc6G1<Vma
zjvGXR1a<Vex1)lL|7u1ADfIcYV8KqRWjHQ)nO1cn0w=2O4HbCMeSbpmFawxj0?jds
ziG&O6MF5Qu*u9F;M+(}S!Hg30Qs6yW@aHLr#0Z?<gGj94@)sa+g7_zJ3B(I#&xfNY
z1^c%^GC{yw0Phn88)V=m3A!K0BqR$4ogs2cu<;yPrv<lZ*eL=&RcECNE<8!g$TUF@
z?FZ5Y>wbf!GXnLS@Zzi>gEluAf(R;0$rMbIPv->hod!&nVB`oy&I{Te2k(MlKNUz^
z6m%~D$rg0}w`3FS=|U@4u%4cJ1%hWop>RpCwFh%iD43(f%oGX!#S_9d=dvJS8?cK7
z2jU=lMc_n*C|3n~dc~Fq%ABBBDtNaNie-Wf3bd397E;FbnqYP<rnEwkszm2?!J&EZ
z{)XWGLa0{>qWB=yf^kX`)d+^y!qHj*hw6Rm1dk~EeoOH5N<iCg3*OVfn|i^vOMqz*
z%n^gxD7Z=`MNNXYXjRxOn1#PNErJXqL|O&^P<{Cw!KEkB*(P{}4l~{rJV{}uc0n9n
z<o5&y+Cg^+Jgp%21uIsA*D2UR)sbC-+fTr5x8M?`C3|dwaW(WG2!f~K@I%3n1$KJ{
zA5nIxPY}X@V!yyX8KZb4kkD^1Ah=7>qCr7sBt(V;_4JwkVS#{xT_b{B6j>P+7@25|
z32sqPVq8$uhM#vr@ct7ZlY&t<U``2GxftiPz}Anq`J5TS>t689Ubt^JupNY#?m*O0
zxcwze+d<*sHfT5rUzvf1v#@C=h>LL7GvK)j<)ct=6aM`T47v-uD6irn)cgf64hh}q
zQRpfB5EC`WOBm;ik$DTZKMi#s;r)xScUV|vqjF?lVfsZd{e&lvL)2fW76UCnc#x91
zfx@y?;2jZ4+|U^$bf-7oQQ=brb4<9T7M6mAn|{I|jtlK6Qx+l&{uW+@3ZH)nkrTqN
zYk(3a)KQ6AxNw3#G87?X(i=8X`1fiXT#OQSe+m6q;SG8i#0f7_MkHR?O*g<v;pPy4
zCI}nXqBBvrVI0mR35$|pB3Y<i1QVx(!Bkg#TIhNXohiaT4O*$f*C~#cCj3?dlyu=H
z+JT%AR(SyBtZ=#*tqkGl35tni3Qy6-?VRv8+TmsiD<6Z#d0~?oFc*ZPZSe4-a06B6
zXA2k7hA~Ijv;dO1LXjO>dBPSCwDN_y_84e^@OeLwOTxGRfTcoVO%T9}g!Adfxh#Bl
zKm08g4p_juBCHyt`|qmo-Opg6L>RsZXr;n?H_$2*o=HcmT=@3`U|$n{Me|%CjK~1m
zbzu&ziEjvhT?e--g-t;i%uQjK8$7HM?tTrHs)Y|}EnO#khZ2*wgjZugZVNk|pjR(^
zb{lvNLeCZ$vNZ~`>6y|b{5uCS&B8epOlcAFRzb8?Sd|Gc?g&5G1Cci2{7q22EA0Id
zBJILA>A2fH;r7+&>=1s<2DvYE8w2SSCTXG2CF~eSt6P|q39ugFMv8bp5Y`97?T11$
zy<B>2!UQ_t(I?zZOQ?R~_w+J<B;1h!nE_$tc?@k(xQt>VL&E1MNjoh3cP`A22nVR}
zXjC}=Hl}n;=o|orabejK@Fs-sP=;Vq7(j`jDdEdkp*JnuzXf13LdIhNvlpdvz;h7U
z)Rb0o6fL0S`9YC?E0|8A0xQs*MSJO}yo+f3LwM*as(uF=ZldguVb@)x+6xg6(f4~m
z4v7jVDCj9Fd>3F|qG&2d@D{x<g`SV7i?T|GMY#>|!dLXvCy?|Lg`WZO7j3lB6%imB
z3IsDyv|R>rM6`!a5eJD5Q0D5WXz@0{91|^k1E9g84fMD>E()c9O^C?795A7x>r`5I
zLgaD>{)UNkFF-F`w1n1E5uz9Gp%p25#t{lpqPP9fiWc?lgF=kxmv89(7b{YC0wzur
z?}=YKL3E#jWr-pq#b1&{!Bkw9EP6!$sO6Msp&aH<i=y8HNfAZN0cfgdDJ7@UL_KyO
z>7t4-=$#RDF2g*X6)|SuMTV&UZ@88zT1wG{bE1;(;YF5+^Bv{n&WoP^3osW%@pK7X
z6phjutZdQgi!hNRdKZDiIk}=8t3dKZZMR?|U(|j9q(HPz0M{;w1dCy*P_$t)K#N2J
zW#C;F{Y#~-#iG6R@VX-MSPzk_qRCTGC=n@?aHdp*q2T^26P;vX63Rs{mczs~(L7p0
zRfx8@!l&yZ<J&;HA?h)MS1H>1EXYmKL?kR#iAL=JS}p3NxPOgknqJ1Wq7=GH>O|@H
zAbCr~r4rKy(W?q{Hi}HY0<%dpOr<Q%qLndl&DJ7PQlg?&^hZB@yCWJIgfnfTIhWz$
zU6K1=fN2*Ur`_Z|Q4>|0b%=hTCHZ~P1vfa_DcVgXmt7+7o3PX^D!m2LBf>}XaI1-C
z(=zm-C?E+IdPPg9TC7jBYBl`r7d<`(3y*A~KzcV1h=i1g9Tauy&>9j&(;8%0^d!C7
zM?@iKVRux-r(MICsKXPyanax(=$sJMQchq}^y4*nI3;?EPTWk3ei?$@8BvZ84BCtT
z?f`KRpQYuXqxh+PaP6R&^B&xG65IAttkGHQO5t=D@k-iQxQcV>MdBv@<p$8)#Y?D$
z*F!v;a?FRsk6fVOEsmg!rjPiK-SFbDc=2hd`-(qoMW>(GYc8De7tc`WAwc{JWu*ee
zzdQrIBjU4L0Uabhz6a1p#anIff_Y5*L?uiFi~ps89v9D}w{VDf2koUp#e?5syy4<{
zI%yFh&ZoUnq&Swc4^iS>&tOc^;-4v25hLDk9H6n{Zx6skoLEOi!|~#}2!NdwC(>Rv
zL0r`ipAyB~?;)8aezc9^FUjK10w8lr?Eg4Me_Cw(4rnRjS6IMK6*oN%FVe)TUWa13
zxN8)xGve)Z&7BqJ9{^~ExIF?x%M|abg~B;;Y5~Bq#Hwb9oEMv0pm#z19i3ylC}vQo
zBU|jc4i<96+bZavDCLU(@`7ldnDY~4^2JefT@{F*j)3AN@j1%S6^b`cVDv@eh7ovp
zS^O78ri#UdJ!oAKk4=DF6&L;q&=T<_78FXwb0&aUCYI76gL1LgHSn&9KVA%fE5!NZ
zuy8}%R7{@`suU+a4of%1FG;|x62EAHVzv0g7a>z4exSg3YsJg<!bF{T8x8c9*hrC@
z+u~MNOmMxp;A<!}h<hl~*(hE}dQIYvIq;%cY?uePTf}aZRBjWmSO)dG;)n5&Y!}<V
zj85A<akxG7JH#FS0KG4sPY>NraXvjoy2MJlEW5=U0^nMYc<Fi!`+-=w3?dK3$$YeW
z#p^sF(kDLu2GIJ&sSQARB+jM_aX|dh6F?ahzqkRNL*kKlp*JiZreNKO_z*=rMs4Ef
z$3Vx#i&ua-E{>$=#)NpD0cewA2Un0O@iXPHG%aqS%DWkHB3(1~lC2{k4w6H(19FsH
zqlL*qN!2(MoFq@3LZ`Fj<V(PGk$jN?o~tC1f;nyy|7M7|OMa$Qm50Rk=c^DsBuUr^
z6P}Vm$~b#TDy~4rTe6f+CHY7)Yanu167&i*d?n));PR7POTY;IC6SRJ0g@d#Ac2zB
z8mJ$U?9aq_gCt)?V`N7qAv<CInB>h#fCWq5peM_532Qk>h~yVrIGCXlXF9fZLh?Ze
zewi>yWF8d5B}XV&9wGUh;(C#i7j8f@N>V{tjA+SxDu#@a)X{nKScx6&dEz9a$AA(q
ziTM-?Cnbw$)1M&uX9K)Xl<c5Qdy*vdC@_;H??1vIPDym>6q`LQv4w-ANZgWvohoU|
zfTc9a_Y}lRm&~HO@r=YoH~d+N%M@TTB)K18pqY}7azV~Xs_uiAC0Rvfgy$s#RO56(
zQq6`J7bS1$VLn^(CVd<tM^fPjuw2RG6zb2DB-rRgOTOge-EhA^@*!QUMUo^hICELz
zEkS3o<n?{fxFQMGLF1}qe;{}zlKyMpl}bGR1+PrPs|T-KvML0;YZ8wlSgMdz(;ahN
zvWB*CHzfLl@TpR=whZK^<UR7DO43wI@t0~zM;<h4B&q!{Un_Zs4*S$ewsphrTarsA
z%=2xDf<BT|FHzG0(gw*k+O0QAu73tzlf;)+&&`sQ9O$)3JSo4^DtU7eFz-loR**Ky
zl20IcS7O%-58EX_AIJROljOb!Ok0O!>wEC#zC=0&nNEqy4>Dbna*9%POJ1ZHT91VJ
z-;F2PNuR@bC~3F{FM1`7`5=9g;rT%8m(<gR^hhG6m&|}9l3w(K67gdI8<M>JEn35p
zN-AI)kxVi$d83kCIv6%)lW3;l@VMko56~tgA`?U>CHC&{X-e`EEw82}FTMoO8Oc62
z6z!$4^8o4~jiJw4I!gIH@adp*UMf1Bq?_&0a+bb98&wzSDcTadN@wrIB)Cak=(X=I
zU7<y%hxE!dbRLr0%(Ou9lrCHZeJ|<Dl(F`fzT5;EAL+b}=sYZCZG~N5Y1A(8{G^9o
z1M!zWJqAYuq)xAZcSO3HZjK=7+^6C8QR!j2xsFLE)&V+L8gl{UxOCw%bcRS<sVFN{
zx|)vNo{%oEy@lQ|=|wuY6fO;lLMuZ0(rX}*()r6E6D6IX`mJc`mJeVeM!J?(-?7q%
zv?GX<9-`%Iyfi?B$vY{1$iuJ`q*q@DFHyRW_9aPDTOLG`rStRAIwehf2$9p$(ieb|
zB7N~VMWIrqe)RN7lQuMfnJ(SD0d~(wul@;xXQhX>pp_vN(&jExy4!!zz>Bs?suQ~)
zl~OJKMd>BN%$AP&!igNIkwUq-(!UO&l_!m)f#pjNP^DCXlv@pQNt!Sl$c56O$KX<t
zR8Ik(%hFvGjxUzZdlL#*q^tHoq(th{0}G|nC+*Q$Cf#udo#oO$Y*o;>CjEjoITg}X
z=V9==w5kQa%MEFGHd>X^58p)VrZh#2R+V%Y?F*`<M`Gb<jdY4GwOZ-c^)O#2y)prm
zThhIB;OMqAhqlS}Qo$}LG)VK0!BC?#Uk1G<Y5Ut4b+a@!l7hx9(*BL`tyL<X1++WT
zr8Q7&lWu<;<gPS|vb*ilmuZu7PdbOPa2?Vps+YVkU2zj=ozhY&k?NBAQHfKx^Z=!t
zdZe~ekO$H*ihMtm{!2e(uk_h9u+S%E`Cu&l(%t`~Le@vpkDmnEfb>)PM%keBCo?pL
zq;^ymG%W3nfZY+P*A%90R2um%cw^GHDM>pn-M$zi6VexUp>tAd_!?eJN%iz`ziFv1
z2O=}lH*4UNy=>$aIO-s4_z}cO_V0hi(z3>*v}kaVJ^3^2y2|Y7E_9QHEl0~;_HhRE
zJ!C&8!r?=*Ij2E9W!+Sy;3ezeq2(<rp(vS;Y$NTf56djH=J%Ba20_G6*1Q9g=P%nu
z%eVlU>`6EpD668^*AdxEM<5a;tDyz1?WpWCFZ3RhRhB^}SoRfF)gG7SP!cgjw)`->
z2$gOB8oU#-XK2k6CR^GEUbyTqWz!;LuP1>-%0B!PXi>5}x;3L^wG@1fkv&b}o>&=+
z9&d57@s&`Imj!KwYbRxGe2@g2?8POZi89wiuyjgheiJaKWzp|IBSq%;Hab&fUIdyZ
zt8>K&(`DnM5IG}r6T|JZG8+}2WXOV(Kr&^6bd{ZxEsumxS+Z<;*qxVU`~tlTva@SJ
zF3K)aY(HD}Qw&gYWVW~o^ybRma>5AnWG}yj-h9~}x(y3tX;lAvNmi8zkwRHf8m6sC
z78#3Kzbre*fQe#R3e{Fzk-g}E)>WD0Gw7AbI%x@BD*J~Damr+~v=AwmJxv$OHQ66)
zAyOf$IRKRFvc0xH!Mq{sqXl-QEG`1>-;`y>ptDM*T@TP|S^Ecosgd=r2Cr5Y_ZRf*
zWNYbdbW0|>gqgW5`;4+;^|B5sBW#d8Uk{N+*=yuzlg#7|ux44F3lv&pos`yXmGzy4
z$Q@aPk%!(k*-_f?-IXnu!$iBR&kxM|veq<+cFO+JW4^j%FC_z}Tjo!}y&hTP&ma$E
z&i=PYmfGf2Ky5%aung7*Wy{WiH6;7>KCBPR$|-g`B0EnNXrnTZ-GCgE<t>27xa`P7
zkO^5Ct*a+x%YA?{C3}m0k7?O4KUkfS-Jt?SdwC;elN{uld6+^+`97NEgL2bzm=`B`
zv@HsX&ho=F=`QkMDp_@v&#45qn>=<GG~DIGk3ru<zLhF556LsAlEqVgYy$@ECHK0H
zmbZM&A9_A=gv0ULkuUIv-DC1^=<|EQ^8bAg$>Z|59k3fB|KmHj7Akk6e9Q@X$toN4
z!{meXU<;QEwxSgw7gLfpQZDg^`6&6g0Ig_wL@P96<O*7_#meL8m_VHT{%MRNUVdO0
zypwVc?THfP&(Ud@M0qfUG?L`;JD`v(_osmDDS7&H@bI*J=cgbk^08gC?n;&Oe?T)$
zKEQ!~y8M5%SU4lE`w6YH@=2;$%aC_2g-E76?{AQE@<2L(lqJvo0E0O%Pj-Td3-VtN
z!^B0og6_9$`O9C!e2zSh!f?6rNjG%n$xqNTI$s_}ORGY8>^iE&FOoL~qW7}gk5<dY
za*rJVy(0IagyvQG#eLwF$m7L;DV6iS0k2H{8LcI+$=x?Vq(c6XqCMB;j&yqVhWx#&
zAeHhLQeonze0T({DtX-y#!@XGp`?F}{7fiFtvqo(#$v0Jub=|0Tk>19y1y;IOGn!4
z<?U%0c7uG=9`Ksw-_fJDMSh4*E8daw@}S=)Z`urJ?#h`%5NVgsq8$7^`O8N5+aY&4
z50v}zL<&cD%7gR(>yis-LEJ50bP}%h$S=?UAK2uxf+6!z{u9-&_sae10NN+7qT9Y-
z9zX{oAIVSA6+9sS{WY`(<-A~^4axg+L5AhdNgyNgMYCXVRQ?IwMq~0II(acJKYSMo
z6LOydU{1<yE6_P5f1bYnGcCW)#H`K8Z7)$Wz(KK$7K)CFaVqORsOY2Eo{M5hIC!p#
zudiTeZi-73IdfM$Me!LA#XJ)%9a8jv2;!~CxB>+q#lEK@a#%4*>r8(|-IwqwKoMFD
zkwAq=gw_$oPxKQ8DeP}R@~9%k_B^KanBw3Hm<U#M)8%zsv6o6jLKI6VUl6J|Js<if
z6kD!CBuwE-dAe{#jvrbPihFd&L@K@<gk+Rr?)y-WRvf(x5~Fy(1S5=9oTU?kaSArQ
zpW_uQ5x`C=*8K`zg5sHQdiEtMuKkx4R&1n`N6Cs5s+KvW_%a%<omTX}4rfvnpU}0Q
zs@Nn)XPQF)04CBE)mzazqZr+S)>*~HPGDy!?onnuQ;~fYj-FHWR6!(55u?TgomV_@
z2;_p|quao|s3@CDCy8?v=VVaKQ~1(CF<;^SCd?No{`w5$lH%WwfL*AVN<phgQI-MF
z%Zj(c;ApYp*J_X}ib*=ea#hhutEv*kzqHCIRn$;yuS^kl3#438&W8FmMN1~^Rw&l3
zhQf7)^gTLBd_xg0$IvPj-)#l<O~t=i0IgE^&|<w>(Ha588pV$%(7L4<qFd#*VjY!j
z)hnct&}&fi=YljU*3#pyNx`OX^ffE4T!)DkMdma*TNTz34Dha^cnZ$6E1Kw7@;${;
zPl(uh6@M-TcAr8)(T{!wUYEGY6-O!8I;7Y_5Bp(7CmpvLQ9MS0ol(VF3LTFr>=vOl
zsrX0%6H^K;t!JhcS7~St%B}lh$x)gA0#FVrcTlF-NjYy2#96ufJAk<;xi=tr*rwdS
z1Telz%SGHre#-COhk1YH3+WhPfKq-QmI9S;{S4j_r6-l71S!9!Xu?tD3Yytt%1!ei
z8LX_K@cD6NKRwSwl&dI)5~{pakIoayLYm5OrHQVK2xVR|euGG5G{q~Tlr}xBYoe9g
z@1Pl@{EMD9@yaiKp?Fd`KO4LRrG?_jiOPw)a5PEjL-UlZd~+czol?F@bvdV%p2ZMJ
zQC6RULaK5VCCJm1SHi$cSFT-%)){5d3W%IlI#Kj6Ln%H0UZ%3u)(EH0Db?#>_k!{?
z5288BkE_wjRXTqGlBcYg#3be`HG9!2P(Eyj;w9zde_#>{m3x)o6)7hkhijLWdj_Ch
ztc;_`@fGEv!*KMfQbyVS66F)LvMp5x|Awh7Q)X>~7v;*u&Q!j5O}Tv|uq%}FK85~u
z<w_%3H<X<>!K+keQkJt?xjzD=QF)ox*G)<j<(-?ABUC%kqU_y^p|vU{RE>T|IlBd|
zyUO3c2CrTDWGy7`DbG`RXooV50qFb6w$&h=%IA6X{_9dcL(7eBrQQJ=50p13?Eg^t
zx;r#_l{dZ7>Qk-{N2_1CCI#jnDf=j+F`yhP#V7`q{RiOMkn$;Sw1$<(=-BdzGVB-3
z%$V{uI<q>ij2;BagtB)xc$3O>D!`jk)_g>9hiT;}<lBtWVLynyY6Gp&98{ip7`>y4
zse}GOmB%h9I;qzEi%w@%6xA8Ks9L%J>Z%(39p1aCTIecsSG^SkNe|Vgxgg#uN2*Re
ztg0IVw6AKz91PG;)&3)R{;D7C(P;}%F(|qms5*E7qDNI7^%%@CRXzn#f>qvjz&@@T
zSPEW<YWq1ThN?7lpznlg6U8#aRGJ$6+Tkjvr9g>P)lwujO7(0PM50wGlpv2$MQwz7
ztZL0WFdwJ-cnWUEs~l)yebT1-CK50SD#mWWB&s6cf<}_+x7mP6R{d)LIj!19Pl^=P
zAuqI2Rc{#qlcqA!R~*t+VYD4OtFq9Im!ZnO1}`#Ich3RroN7@fM6y&1C`5N&72Af^
z1yumq%T{SAag?L7mDXe0a#cT4VOyT+x3%ysUlp_-z7?oi?ZLaGT0#d$uBa;B!(3cd
ztuF$vM74*qoTaL1s$wrw{X7f2YpS;>#89DXZ3OSS>cv{{ZmPauLA^?~m#TxRRq-9*
z)u^7JHE^x!7aN^Hy`_qv$mVTT66H+mRh$igX;KZo30|}62LlGvqI!P@c3V|_6q~!F
zI+G8DHq}S3K;f?Hqdy^ePsI*`WQVGj>d)`194o==RPCS`N|#EXftl%6eU$~$qgqQB
z!~@mbopk>_RQ2zHXuqnNva63&fmCrmpkhh@GpO2S0rrsUt9I~)RT|pkjH>>gfykJu
zow9}Fs^^zNWJ2|k5EDG9n)@xVXH<cCkhE9-^9qQAI-TM=j_Ps_yg#Upl|#Wv{Z|0}
z>kJol%yW=&Rd*c$aZ_6!LeyPd)d=FDu8W4KmwHw=9Q9VWron`d`h*bX532{xL&R6T
z$O7W0X5EFlzuKEJWC7|AZ$czU{Z%|VkE%EQ2K8g=eYE2VR!`IR?YR04e89>!Csh59
z4>V4wD|11@)RJQ$5$YC-_C%^vDljuq>W|&=b49CdpTm5NI^-r`V%42*f)}q|Ne78e
zs&gNM!36c*kI|W^_B;%cB=s^ZapxqfOX%r-TK&#4c#)#cbVFyV+MX7bwlsBdK1P_X
zHqv}$sDr-4tY@mNdcd4hzexYSCrf>bM9!<vtc3mr_4>EKyQnUt!x`D?w6h>N>MW`b
z%2h9+m|&jzt6?~kuP%xLDNuV*w*QiPhRVVV)qk9Zp&~V7EqIr0>Q*yM6szm0O6aQE
zy8wQdsQ;v2v{e1z19)1d-bUNxa`ln|z+6*Tg@IS0-tG?l>*~TaK)a!yO)-^9^|uKy
ze^VV!LDwqvEGmSpR`X~{UZWmsfk>_TvHfV(sl91ib4wl6GH3QY+n37$Qm?*26{HPn
zS0hNH`cEpAZC2;f<Dx}9{}RUDs!m=E-W_!zQYLfS)Y2(<bXPrn9b<1-KV}8*p86|_
z8+51}sKV*Kx_JQ5o$7F^lj>4yDA~}hK6C;KJ?aM?7}o=Jr>z9N57l2U1nE`BzYWr-
zF0%mUk-D)3iUaDo`v5bjj#Yy<qIRX7)~NbsA;_5e-9(Uab;18Iz6ter^l+Y3@A?{U
zPpMrgW;w0?jl$0}>izU2vDeJs0-l5B6%))mY6?SX5qeM~rQ6O)^Ej1)IBUk|pwmTj
zkIElhH7ifTyqo4TcktXb&0oWP4^7t~CgG6g0#(m@YTQg{d1(@|py#bgY6rHD#+~*}
zhc!|v{PEQ&DR}OuSx#>Xf6cENxE7#U8BfJmff`jinnyI@RX_{U#L+K*RMSdl7LI9>
zqR<M~OwtnkxF-Ax1{$JCRKkl;&G9MtbV9S7mhNGi_d1~vuIcLqiPHQ{@8@Vu4@Dhg
zG_O;zGghObcu<_?_vJu|*A(EnWSetR^Bi3Q2^yz)FrTP-oFbsfn#1%!JEd`m139g^
zM%#*X%`5(}dq(rdk8tL!W-0C5Gc?EgFv3jDmZdOwPV;6Ncv+e-+VY>*H17x41r0v~
z1}|zJ+<|1aM#2DCj^^8qaMYHoaoh!Fo@V_~F!MG0E&#MZ<4RkWOBxOx^DNYC{{W;&
zv!?(iE^FQ*g<{Qt2`F6ADCr8is@d%UQlfF`gk-5Eo36kz&GV@cDc87_L*bgH`xIQO
z&|F*s-gV7M9cJx@O%q5TKdRK!QenwWjkym_RcVqc;CHpgMhn#%4Z|L!R`V^z0qQhM
zDKBtKbHNU1w>6E&(5ly%e}rCxX1*T7Zqyv3%ehJ8H47rmnnkq9ZqYok4!l;)KFVg^
z(Y$4bNSnrXVgdubtNEKwXtirXABW66jqg)X?9hB=Mdy9Zy>n=FYQFJ?qg@)w2N+DZ
zX4w)*_Gt2HA@V>I=!-Eu)cj4ah+fV5S7ESEqwPYgUo&<Etw)+uw164Vyh(4bLCs(b
z{2kI<u{{eqteHpqwh@i&BN!al<QAYcp-H86!K6kV0y3rH`oqMu#(}D1W;9C|1Jqud
z>4Z)P?PM!J9krI1;Nd~-^YprP(k>21%UP>@2z3|j+3(=CtG3Gll5X1YQFOX%f61Uo
ziHFvY5|D?qPu_rrr*@nVY%i@BT`k_)KYxIRk2d==h#c0wbPXQ*YGWui?x*d}g){!z
z;-6tKKszT2BMj88q=e}aEtg&`LE5|j!opGQ3y)z)$FyHjU01L+{8fmAYG+Gn5gM*l
zP!&alw()TojMN@D3G68Cd3u;cYddLS9HYg@4sio%<LKcRr|qF&dc0P3A0|#}qbZl1
zpbgytltgU}#oLp#vuLr9tlg3T-YNWlEI4{v`{N;~r)cvp!$PVyaC{c-zcg*_I>@AJ
zMY(YCjJBL|x@WZt3X^7N4fD~NseP8N?sM9AKS5`fc4-~#p4UG568>J$zC;_$i&|3+
ze9G2dr<{3?Hth}Q<!W1t(V3?eu0UtLwre3e3$%+51Lcx-cOiJTLammA-Xd*%89*;<
z-+l>x7i-hshQn91DU{^Dsy#{HO)Aj_-iH^Z+T|Z$pk-P+A$aB5oB$|X)9$4GPla}Z
z2XbBelMb%k&@!nkv{HNMHz?fH8dN~3(#E|Elxl4c-5fPG?Os~!*J^t>P^{B_G#kuY
z+NH;!e_LDk5j?HeI(-XXi`HWTmhNb)QUKbfU1bm6UF{EaAGK?b(`M|RcF}B@=+Fkz
zn()51NQ{wnY6WB9b!qqVAlaw&J_(dZT5r1W2eh`!z0ercI#Kd$MEjRB#x$yZj;dV7
zw1Kp|7}qW%^Ap;(e<3odJ@WvqDXqvKylL$dw7#Cv9-wEoz0QNC#6cG!MaxkaLy?Mu
zx^P-ZIO(FBF(hZ5J`G;D=vGvKxayp2REpxJi=rL8yN*M94G-Ol_c63Xy6-5n?5Wc!
z;Eb2<Yx<&;x2}}xT6}bNR9|vfxBp{w`s$WZO_HDPI9(9_I__<d09|(pIs<icXg733
z$A28-4bl}0png>M@Bd)onC{bN%Hss<vS?_>b=jZ7sSw@8Bp3|UwU0sLgzm~sSPIkK
z>xE*tu1y2b2;JG=K_Yd_e?(`L?#KVO9J);kv|@BE@tDzAoi~*a#p(PWLub5hHW$z*
zbzgjlaVF@}z643sEnGzRUy^QS2OLh;O}!3hPU#-ey?t6Ye;s^E(aom#ZmP~<H9FID
zD{1+cu47+>`7=6s5_o5I%H`l?=&b4BW$I@2LhqceN)IoxbSJaWI<GtQ6(-?=?mLQE
z<><cTfaK~{{y_&q^K_?}fXUaDQ+alQZlx<me@XW})yNj=>}d;Kq?`C2BA0auHjJWJ
z_hSM?uIMT$t#Va2HVBatT{xW$Db?kxFtjpVAr;}5>wcsn?`yhUFTmdlUEixvzphKB
z)(zdm`LJiJ)V=&Ge7mXhIfiDH?uFN(QLSsB;;kCp0{V=6t#03SkUAZoc09LqX)fU1
z*4+&NOua5FALbi$CmJErsJr?dcul%R8q7tr&Mq4wExKEBh_vc<)`E9O*G{RAHr>^;
zuy^+>ota)89lEDJfp7P917yBa_ser&cIggK(70O{@C-zHbOK6GKG1z|8=wz$=>~}O
z>O2cD7k#?yQndPYdv~GrNS99M3kGz51g%*(`$bz9)pL&M{3D<@s!M(hyfK}XTpQPw
zQ{;I<7eb+{N!`(8piJq;8(?-?Hz9!JjBaoj{I%CVJqi>Dy=w?M9raJY1d)UKQTn`y
zlm6W&0p_gVif76k7rp6k48>J1paUOndM{fNsJnj2*RbTFS5t=IkbV(GYd!Vb4*<qX
zA4dfX-ul>OX!+=0q7MTc)-QI1C0~8*9;o~2%cxkzU;k+zumkiS{rDvU^?z`ocSQfe
z03?s<<&-QrrgvHakzoB3V(^aZyUT5GDnx%J6C_mM(h0N^`jOAU4AVb~f=0N0@d~&W
zq3<g}XQcjTN(n^id*jd<txuxhSd9KV$}q+1IaKcur`JRQC0@Tz0FjgW*}*_b(%)DE
zyUF_eBQSJIFAIjhr}eH2=p*eZ`bAU*o2s8V2T#-VzEu2}u3sDgnKSww^svp;PaKBg
zIXycF6O^U@p3b0M)F;y(GFz|8hHE+cXXk;JtM{ZUH&1_d3tIX5xip6b`Z|ilUeec}
z1FujYJq_22^w}Hen+KQmncqOPSpPJYOI^|D(1ZM{erO3qOZ0are_E=K=>#d$Cse|2
zxxSTF^w;#)QqZc<|L=d0ysj^vf!+=ML3){1>Jtr6xT#lBl(tGA+lyAUe${8NP@_+#
z99XUX6oo5ob^0YcfOboNVKbVy^|wPHQ?H+12GXG4|07&$)JG+NH0kZ`1Fcz~Kzq3s
z{pczvwCd$7kURRF_5f|u&#c9)-PM<F18LW1{{n@3`ZJV7?$FOnp!2?d7uC&m>O*Lp
zT{iuKchK9de^d&X9(}`Rv>xc!#=@tE`aRQV_3EeBz+j*Lb2do7e#H<#AL)OhGvWjK
z*WQHWpx)zO%*BvCo8B11`eDi=jp$oGhuu-VyApb1dT)vej_X}EVq_EgHZ6FQdfQw|
z7EbA_W6+$|e@;Qy8U1N0l(07hHUsUT;jhb3bTUXHK%5Ol6n=0q%u_<r)sV0bEjL4E
zGrVv&L{pN+!=TK-bRRO5(4)-L;E7{YbG!_zmcu7+L-PZ)d<=E8syb|_vvmQ+*KnI^
z#{3MSlwtNa{Cy0d0ft{*227w~&LfB%F}%15B*<`%9zI76%P8r1%rN7QR<OaHo_)s+
zxBo(Chyj%fxSI@5B>?4w!JF>QFvBz-BH@NA+S5fCKHLnENJGhg|DrU?pxOrW(T3IW
zV8$5cQw?OS;bY3+#2K`-c8NFK8imG5gY$myk__XAppb01@C9b}lwtA+$Z5kCC(L1r
zfk9_&Qw@t2VuWdiNk6pG4XwFooiY6T3??DNQ1ll%GYuVoP^rQ>gN6?IWf{JsO4sv-
zM|5oEqM>^n8rg>5)1i@L`1TUa=Ne9!!OJt~k}#%xLp&`b3k~5LAyQ;`AswKX4Fz<P
zyV!8l6|F0V4OG{4)$q!Hcaz~=x?xKV>(;~HGK2mbs_!p12>qdd&2ab)7_2b#E{EcE
z!vx(2Hw<qL!$hUwsXKtVX$ULBTvQpF^PpdCI6{&&2EWB{t=8Z|S;{)Ybt=2PWyl+a
zhqn#2G#B-Tl8<4b!SHn|z#0ud3c+hKlrBT3t=SMi4A2(CJKw^$R>L#vA=74nzqpSK
zyZ-^{Fw9Uc?!I9Y)g*NqQgWc*Wk{lpYPaExCt!LEX?mzXFpRv6)<eVfdg%2UqGmw)
z44>0>wcqePeU0pqVRIe8h72rv<__BoU(gYR5yMZPfQ%Z7Uxogd;RSk3j~nLxf*)qW
z@Uj|nF=@C=$^I$BUu&Q^ZE)BDM`sKtD6V90?4)ItqjB{!@bI9~HxCL<#vdL*#MyZ0
z7bv(GH|~K2SL50L&X5@&qe=;1qiw1dGJZzZ&yevq*2ckLfbr8zm=81#KLgOCMh{BM
z9y7k(2K`{;<{iL3Zv40xyb$9DDoBPJZ;hgL!pKerXqZu?Lua_rKxxJZV;8;rBaN@M
zp%rD^T>zA5<M1(H#u%$@_s|<_+)H_x6ys;T&`&kWhB24v#^sF|%o*dH-+*@3*hj(m
z4CD0|U@6m>G#licanIYp&NA+O2B7DSV)}O|7mS}$RP3U$|96OF8;hxCCdYVg14MF-
zO2qc&<QWsG)-2z+rj~Bp0waeOG?$ENw96<oo;wd`ii|JP+T*hEU0VMY8@(tRe#Iyz
zyH|}1V!$gg&U1o#snHw?UYT)Cko_xIQS=SL{B@%jWl(MyL&>#D<AF&SylGrcWwTYr
z=3MZqjo(s+tHxMNsgqjc<)^@_Gdj_B=9V#i6s_CFqHajm8-4Pj-elaM26VG=qzs)c
z#?UVy(rWx85R-Pt80`*U+KgGYXF%^7zs^8!yK&<__<PSdwGW*g#()0BT--N0(iXbY
zm_kpME~AD4(rsLI2c12}-TwmnfpJ<2gAa|}Q83tRZ0?1nKI7aHwEB&+7Gm&^jA_r~
zavU)B{e#Xy<J+}RA2M!^r4_}naRF`UM~tui3g)QM=QVgSW?VBL8skRyQjB-Pcwi1R
zCXKtDVSdW^Cw-x5+IWt32{Xpkv{1D-S*XI!!Sv_v5OFlU^e5C0nvPM5$;tG?9}sai
zg-|7li^+}+4_!^~`_YLB57U!ZF^WT`-<#our)lg{D0-QcRH5!|vf4w`$0Yd$B8N@(
z$6?Udw3A||ex`qCLBZctx(Nyarlj}L8EAUD6?#WZW4kf3AXCyXct=e#s$)22dd!Hi
z1e@kk{Q0=4<~7QkhM3OKZy#zJq&3$G(~)-}8fN;Q@_gZ@KmN;5n=btcFCtCuOE8Kk
zljBL~N1LkJpb%pUyNNNyn&zH{-8fUI0n;6CN)Cg_Ns|M`fD%l@-#{eMbn<<4CYgf1
zffvc9)=)^=PMJ==3Qtd)azcTfV%nJx^QopH%1x!2&L2Q$y6F{K^PDm5N(DJ<T24W)
z3{%2u0L?UYya{s7w6qbOS*F*h^So*3KGZLm-k_R+i>6m;jh1bC@ESyNOapX=I@k0H
z1vB$(rd0-blWz)^L8HJlNCy!vnRd~Fx6q`bw_%ZK4IP8JY}#xADK^c224lKnx~N6#
zswq4ek|icvB+yDtA#@DC%oIZht;$WK`(ggN=_87@-841Rj<m}3Hr4D@n?9$EPmReI
zz77U!P1zv;tuwU`z~C)Y@)p3{HXXc+R=sJ_4=~YSs-}%`qv@ynn8YU2ksgRNn}qcA
zXfY*HkwL5J)jdGDW9o5+WSeP34avKv+F9VWo0fbIuzMyOO>Bp$`89ZP-^BXw`>&m*
z(a)jLWg4XjX}2kH5~4jOFZ$1{4@?hfCG*g<Bn@8lnikLv)Mxr`EiCn$UZHZ`N2a<_
zv<6HY=s7cJ`mF-$L#AulXbqd1PM|en`sp^HM@^qo%z4Z-_j&NfO(|m(CY~@gP^5Cw
zv~(U!Oqm1}HJUcPQw@z7Qxhdp?9GO5NIICK?!#|KGn*pV&gS;HKyxu4cp1di-1-?5
z+|1f?@Z8PPU=R=UdfK9SnHk*>@it$i*rJa)v=cl(bAu0Un*GfU3(yQOpWcKi4K({i
zL-dGw<1i*F$n25~Ua(n7>)qq#`U$i`%*j-q8EW>UfXNASt{f!H?79fp;pRECp@=ZA
zr1fK@xs58Pqs%|hy%}w;{Qx72F)yUGaIE<VgYLgLbJ2M;<IUwpz??KcCx&Q(`G^$5
zPBhn)12oC}_$wHFvN@>@`lrnM=pH+5))fFd#r*7Tv{KEni(oL#yk$2?y4e;3y)))>
zv>iHYUjG&@vJCS;Dhy?syXduf&ODnY!IouC)j{UGIg8e67tFUQEPm1a6fMxR%@s))
zXpXt*IdtZl6|K<7Gq1k~l5hSw0HnZtk`Hpp?2L!WoI>*$<@}4x8+_4u+5A-@Tq`zT
zYDec4^9_onUNt|F2j~*Bf)7$^GyDCw%Qt^b!J~3>230IwGkenQP+|V47_IB({CbcZ
z=J*CUQ)$jP0p3mXo}XZ%${be?y=wFA6b!A#%%Bi*t-16rMC#0YtHHZv9;GnxZFBuC
zsMnjl%HT|cc}kDYMzihLzu|X_`E#mPYc;c|(&LW#=vpYYnX@SNeAj&47uQ_7IqMqq
z@0o+=U@kh$-_cKT-&{x7o#qcqfzoB3qR&xun+3l@p~sv|8|w$=D?bD5q4{(;z<SMv
z0qE>Azen-Ie)BAw1O^|OQ!+sY%s)_-&Y*b?h2@6KU;GZ4Ve=rR<VMWA*P%FS-bSnL
zF>}5<$hi3_3T;l96MLXHY3`%4t0{97U8~dP6OQ1`n0Jmr&)!l!2R=Di4$p<Zj+P^*
zA#%`SPNdAKljSfy1D!2dcVXAX^3SJ0bG59ZuRXe1UXFz&cZ=X1Xn0tjO9k(cMNHur
zPs>G$i+NebC<NwhagKxuAB&E%-iIxJ(@9WYOIQe6eiq9sFywEErD#)tWe3H)0xeNv
zlsP?Osn3RJkY$9*Z;x8ed<AEYSwyry2)3BUK#p5d$Dt8oDgFZ@p_Vmo!r%#uOAA_I
zmJ=J`Ot{596`c{5;V^(jT2h065@oTcY+tO!nZg-ymLF*A9&fori~dB**(kdIk}OHn
z&`-8B(K9f`5=^i5RLchxB}lV)Qt&t3@&#=z&sdJpBkio^Tp^q}XX)+0%w$<sQ5^5Q
zh5HmlE?C60=)Y)LOc|MMi#M(Kax70!hA-C=|6hfzC7&Lz`Ibo$4A}}S_)a%&AWH`o
z+!k6g_Jb5z7H@&fWsCPM@QN*J3hZ97G*D5+RZD9duuCl4&O^V{Vo&eZGRqSZ@X9T-
zDQ$7h67&_ksIYu0z~o)Gcs#`DZ&*4g{8(x6djihfwEXV}h*a4uEcymxwM9-bvl`1s
z6w|4-oZSg#oh5k)owqDuYoKx4a+JRNS#L4Y@~XjdFb8^#mbA~oYqG4TI?HCuCAzL!
zEQ_MSYqLCd0^Z-XnCRWuZfRQr%zKs@B}j+mbRgWmZ?W-dKh$X%wW7Dna-5v%wlq-Q
zug5Y#yY&Z_JB}a^E!q(byVo*X4TU~S!xgyJZ@KFWyN@iYZLl<8*(ZeLpv8|897C3U
z#2dC)>FOM@ETY)gsHN>IsE=7T20(J$veFg>=7c40E3hXmUp)lOlqFCL>}kupRE*_d
zZEJz3qg6}=sRyk?tAXue9d5!vU9Brw0Clr&41<EZb<fAZ_OLFbZ2cjt^COt|w7Sr`
z#>-l>6(Zi&O4{=HSigUW&coJU=h-0RYb|^VcKxjDe#Ou1Z+(saT}XiS;8Iu$v~Ioz
z(IeJ^1LzF0K1ucKN3DMJ2tQ_BWd;eha$8|A)Vfax^CzsiZomw)u5yN@aO;VmArfKb
zQHUkd`s0%rXO#6_0~DgI%8j!nv*yHDXHG&U*81vFj4;kxdL7QhTMuLc=A`vas<}?E
zZdeZeL~Fk<NRssyEkl#7U#^76DeFv7-n-aIyzndLBF*~4BzWo8PFk*?u|7#js<YPL
zV<4Gfou*hrruAw+yf|mQABxT_Ywb1+>AbavBIXyYPi}+WMQZ|;?`B&!1VALm`gS!O
z%(XVsP9V>!-42m_>*_=3EU?a_=fovzx9wZN6k1n3z|e}U_i1l;+3F~QrDAL01+=bM
z<wZcdYQ0|%>=J8^0=#moH-%}hTeUd=y<y!!2g53@uhO#jrnO`<^s1~Mh+v}H`r+^B
ztg#++fI_WRycnHz)|qy=eaq@5p`Ap7)ujp=jn;EiN7Q8flCq`E)}&X^*<#g?!+fjt
zG?hEwu`X0Vq|JJrl45tQH;3_SwOe^~PWis|CcS?;t&h7vugiK`3xx;PtIps(v_5_q
z=6kIyDja%beMABG0c-KAl>Q#HwhACRV(mNy&{6BAX8|*2<#)ryNvp0HyeVr7#fhe^
zhV4Le*vO=h7dUR*c@WMV-1t}{BwaTCQ;w;0-B|YzCdh5$31_qpZ9GV&>Yf`pjga)(
zI5YqM99?-_R#g+$l5Ew?vcAl$)YP&pEzK;=va-cWGv0mQ_Z`Ku7XcMTKtL8jR@oF3
z5M&Vq0TGZL6=X+H5Ks|BMHcy<>96_CIrGfSx$nK_o-;G&zOZ}9v62ok`Z_w#qS&OL
z<2ys>3~+3s+QL9bPm1XTIUc6zHN-JRj=oSwk8Wr?>Ufn>P7#g=sR%#PaTDD-QI6mJ
z2tbUZ>Njw)j+@7zJI>L8BBaM19c$st3CChKNTOpfRob3%{B0awBs;3;`xEvQ#|96u
zX^uY`0Zey%k*4l5jtkxeBFpi8I=z+c_``CLvyQ`bVC0<R?*De%jsuC%mhTvK1kMyX
zdZmLaa!jT=uM3X9(HgJBv77?vrH+lEaHh=h!GFgZ96wtKEms|1G6Pp{cQn(y-r)Gc
zzjR|bUfcy>qhkjJhFcu<TVS`<@fJn2+8pcl0@3dHJ0(9l9OuwEyz7oru7Y$rwo=@s
z%h8us4L2O!&j5bYF>yQ0cRRl22Cm1k=TpFY9Uqs1>vJs8L9*Y`K6@?f-geYlp!AMo
z@m>sj!0~OWqPpjpz6Ev%9gpWi_mJaY8xZ#$m#EP=>=-r|xJQnwDeOApsJsWIj~xeh
z0Y2`yCJmAkj*%=FeBxL~%Sac-L?v*$86Jz^lPg0&X%aWaUv|0^-5KAl!?5=<&QG9q
zA7d}Q**zFa8sUCM9ceqj=vWJ&C!?CeO$QmPgF(C)j0J#uGZLxZ(TB0q6XXzM$4BtO
zmr?gQMEn?w*FdK~;{ztN9A;qEi+hbR+631E8O}+RPYPme<bwn=X3*_*gmLs`bcQgt
z?SW_*V+vKphBFq`!h8f{bs)wY&5+-LiDQg`7lDgm{QeFcjc1HdeRTrkvM=Dr8S52L
zmc&rqLElM6=OT>$6vOjVXh~%Ze-F1$Gv*(q+&~(`M2WKuMo>L~nGDG{P?N>*quD2i
z(UyX~T*hQL5a$?9r4TvK;85tTfN_^XC54RryD+q3#@0~izQ~wE^LYuQ`ywPu8Sj+C
zi!w&v3^ZP1oTbONobizk$|@Ksc)}5zWSk0xr7DJc8Dy#%zioiF8pbn!!ize_F&X+U
zGh7bBiz|#e3Kv~v<V^#qXRO@@$p*$(3gE6Wo^yp{6XR3}yl7@9rvTo<7@}83E8}ZQ
zkhC%CC}h{p$e_Jh2jePz8q|KBv3ni7>11e5!9*A10L>IP7!fqyn~YvhkXwwEZ-MkO
zZc))tALDI07=4E^QxCg$860}+4=`c|(Rhy`qGjM9L$?TIh#{Z~r2CAQ--F07<GW#a
z@qjVD5seQSQ>Y^6k)4rCf#DGb*8=jGF^7ufMj6*+;Kmr&DR(-~5Ke$hFybQN{u9PO
z+d(E7#}>g+7iJtAqu9;7)&%0p{Cqe1+?YPkqR*XqhV~A7n0V>q=4PrK(6^7dZU&Tj
zFje&X>}T5VFhCD5?|cnWPo{{zmT-_+M_za_7k>>=ZziAKYCg<eUg$f-e7*#(`7%$v
z0OH5|p%F^`neL4cIn4Yy7k~g}$}*5ZCNmCNf|wsr@-UdWkuoDkm?g7t5ki<d<6t(F
z>15vtHAk6OEI@=YOM-A|!kL+WfkZGz>A{U;#?le)DCYd1F^XvB#}+6(#`L4TYz)&e
z6<jPcH4a=HvrGjO@ys9Q!$blznr5xz%=RDgyPjYUZiT@_X6H;aCNXc;qwys3!7_UO
zPBH&E2i?g`hYz4Fg*k;nx~a?tD%?8F{DR&fY0SzAIGWD1xI;}Q^OwCCQx?<T1d`1x
zj)Io6%tR`1%VEZ4!~0z3HgfbF6M<-~1(>QA0ncZq(SvuMX*>_f0_LaxQf{D-Sw=hD
zBIZuoJYQhme;P8y%+z$Kxybar2Yd;03l%bzGGC&kb{VsC41JfFi(Ut=ocR)!!&WfY
z{t3xS=H}BNRm{F}G*&b3GGVud`7R4OYnjV-0Z_*j(Jy(Kx$0*+19XMyOgpcuOj`|F
z>zNm5hugr+dxT+MV>;1&(a2o#5&D{#MGK&<nOQ{9{1)a@6s&7y&ZYcJ2UD$u$aUuB
zPa)FDTuEo#yO>MIAaaAbA`ljCGJmC9d^gkoA$0aICn+pvzr|eWfX-g#uWk_SV+IAI
zwV(O%`)It)^rqDK9j1ZKFx+K+mW9hbz<kpJ?jE!DV|X#h)Ve})h<ST6+`i9zCkR@G
znIBRi_ygvLzHsd!vyRq2kC=Pg;Nb}K0Tt~$W(Ix&Zq&|PL>rnhrmGT`#+mc}1aN|x
z|2dRCVKUwXnPi5YfQSq0d;0Nqvod|)zAH;WKe`)h<YxffS%OJ$dsr)}W??Vuw{{F-
zA1jSc!FaGVlwsJ<%BMN(0PB(va8FitF#rcy_7j;vc(D#0f+cU3>L$GKVJ%pP#zU;`
zA242DR&y^9eynG2LByZ+=X#9kFpG5(A_1(o=#*?A%eWeSL99cx!3}1)B*D=mti&&I
zEkamxSnx2E<rDysqpWZC!9o}-mx>j_S-;y6&2fleeX|pykt{h?Ye%uh)KD7D>iiwt
zF;*hYS23*YDIl?|f&DNM$7<_?ws_Xu=}>cmmAMfn5?TL#g2p7)dQZ5P%=*Ux!%krt
zKZd`ltmhtqWU(%WLnMcF{!M7fWj%R;cJk*~oAN>OSodk~kk8W31v$_1UIe8DEEYwL
z3t8LgU}+I+bvcw4vph<{U1Ys{2_BZP`jP-IWxe{}H$YfdD9C<^Wv8<#6)f3(NLI4c
zw9u_$%_@TVYL-784yj?KAESR#s%5RA{7xOKmC_fNS%2-uK(DY~(_?5?S=YaViF($I
z-9R+3`u>6BHCEpeaE&a^OVHNDir5dXndP(<CR$hy^uxBYW>L*{8!L>8-`ZJKbX#_?
zy2GLKI_vH!c-YC}q0GSU(8bcP2L1+X?MYa=$@-JlPTedEZ6AAZmjQT-l}I(vy{u<{
z2X~v5ONTt}u!dtGd6)H7J;(s-*C@DlkCm4SWrM7sQE)>nKT3ezXLXMQFwFY$Q~a(E
zSSi(Le8}?t10wcEtXH3gQzI<X2Vftwer>_E9A%|`go`l7dWN!7<E-R9G)}PG4#LtC
z*4aHElPm$@UD#a|3vy!zQij8wT`7i%J?zKd0I-+s{T%xCu~)Xjf(QFM3TW?V2Tp_J
z0ru|C;ghGGU9b?A4zktG(B{RSO9wu^*|$Ci(1-1d0v(4#?5=x2__9BI4R}Ac<^h2I
z?DuKsb(p=0%3K53Z`0O4ko^HY96{`@lwl8M@A@2oBkWbQO9^354Ta87_9}{f9c3@x
z3qxUS`^OZdk7V1Zh%Jh}RE^GP_G^?ei)CjzfyA->*T6(PTSjFhC)lHL5J_aGa)3)>
zU+aPHWOn6cG^Vh1Ip9*+D}phkboRcz0GwgB(t0_Ay=w>tv)EqKU?`h?@_E3|vS-@q
zj7bjLo%RX2?10r!lgHja51sk!Fgm_`p8YCCcnaAK6jUi<?_U6=7uc`S?_12iLRFX-
z*|+J}DrGOI23N-ZMFf8@v7dy&ZUsAP8@NjLPO9gtV%N~Zvzp!U3v|}7!&>S2t7Gq{
zBQlrS%P8%5g}n&xEQhP?4=6ia&u&->L<75EJsO+XxQw{h*(YfVZecspmaCO5CcACy
zH)#jc&R$0wk`DIP4E#RV*$uNXz)p5QtycQj+i2z1&puxSa+@vq@BgUou+29Byvx=;
z4KMDoqaEPeAp4Vf;D*>K$+$AZ><0Qg&?ENmblhiz{nIi49<#rs`0^;*H649p?8T|*
z8)x^%!qEx#;c;+J*thAGKFRi5jYb#F2;FPDIn^@&aOLd&gCc2rIX}`%Y9D9d3$%K0
z=F)AlpW{6Q`~l9>Lb&hAX+8vp4{{z-otqcuIf{~da~34vBKUK9-U2zy+3^M>12~Nn
zP!`BpKn3(cocULwGnn%poqagMc}yFb5Kb*6O+z_;v~RRWa_&&9K8kbsV~}W0SvKq*
z<Gi*GB!-h)2HmloLRtmKake(YL_Fs!2}lAbzXL-%$?>LK$|=rO${i(hER>8$;dp!w
z^QoK+TB4rj+@-^FX`Hx=z@>94JD~FnXDPxO4q0}NVj5^RXT=PVvz%q8(V4>;UIsO}
zoW4a+bB^=&CN$=8qTC>o&k2fvw)33mHfSs0Xej$%$eA@4eMOw4VKkO<LMb9##wnu@
zd0pa^$HKL8PC1n}S8&25P*%w?)67)Gu|Ii$OH<8>m<FXaoQ5)JyUIzVvVnTea3vZW
zIAU4{UgIoz8slx`%((%jO`IaCcx>kUOi9QV&ci~OXyshX0-%%gI+ZDOagO9e*$vJb
zI`VOo^F|3sH)lQF`8}M_26%CclWFIG_Hw55z(gPC#rx1Uz<H62#(SKFI&g!WZS*OI
zA<pL%kh{;3JcQrFoQ1T+eZaZ>6C@vUT&S4r5obBQ8%H?>^l_FkPFXyB8s{X^$7m)v
zOFo9OC!D5tAu`FCO35`BuJ{v*r0wROrInN`H}M6?xN!s7(CyAWN#8Zu!!3%0$N{cv
zG&oPL;TnJkxo^`J(~G;(4}IR;pKimT54ViUd=7EX?uWm=-0*9-7Jl4iR9hUxU6qJo
z2XnuRhvX6NjaVoP;VuuMNOmaq5{0{ta;-w>4&yFl0w2!(?Pr*X;5K}LQN(Z$)2$cF
z<<hMe$8D!uFP?ke5hQ^t=m7jU_ca;F3GS&nXi4OrqiH9J`%4RyrE(kT=>2K#PO6zr
z<FdQan9e<i(1G3I4EK4u1v0oY3SDG!-{V3}7WX3$=+5T)Qsh3D`|ok!&v9G&z~yo4
z%;?MK4tD@>o_pX3;04@#H#l0zmC&iXB5uY!kPF;t=P=%4?hutfU*vjHl&yq&<vWlH
zZjT0y_DXJ0E!0$Tg%@#!s=1FjuvEj<(aNHh%cO*39rq6=OkCzZp8=)UxP$cmYvg+D
zfk+c~wH|7kxx46GNeegUJ1A@AZWuye8#i?+aP3?NN`l<ruBG7dO>V6bjosX{5p*Nk
zxqgd5Z*gxWLuoJ9oz@_I+~tM9_j8}3sPjGUJ4yH{2f0`2ULWGR(fN-1-1fI%X_(7m
z!0rQX5PiquA@@yMLp<V|E<wvE*G}P|F|O|iAmiL86x^8L9-^?`6K>sCxCoP6do%4H
z_wlB?!h{EJGy(YiykyD|9N_urK|FZ{SAjpsYoRmBUcBeDu<Ol}HbT;eCy9j8L%eHO
z!TIw3rAjY9o{Kle>(3jfoycL{2?_-V@CNCn7{oj451qk07c;aR;Z@lw-W$S`Q$!$?
zcbjhcFkS#nv*ElnDz1#+)l+yNinr_x)I{@^N}%)@@2M|<kKuhzTc22-osOg?@C>t|
z`#5hc-4`c#XXv$`$g5I8XA)2CjK-5Z`$9CH;uW?*Su*dY(hgt>Pc{#uIL%Yjk}-`J
zZURZ?y+$PkXL$ADAQ?QTr68HSq+X07n|F`um(TJJ$N|scO;YGPm$ys?-RF2JiYw&t
zrhEmr^LaVN@aa4+^9uS3cnn&{74l9{?5&6=TTS17y}(-@27EDZ^L3Dmyv4LREa4rY
zcSb2Mn<A}cyrs0!y~K;8uzWf1Y9mA{c=Jv|q>`8L5xlSBt)kUVHLrxi>NUJw^e(^5
zQ&+;@E4-zYo4d+upNYPD-oCv6H1Hfc=>2z%r=N~dH1QHnqqCV8e**(;;V~b9wDM}`
zL`NI%Dcbn8^PZMM>2+Q%?Wa0<xr-pu#hcX%?k4Z9CoFaIW>6Zghxh7HICG2lbt_c&
z@~Y#}*T<XhjY0JDW_${fJG@t>pwE7nr>etX26)qH+PcSUqj_VH_stH-+~>JddB!lW
zY!=7^-f?e;Jmh^e3kDzY{OGqI;k`ct7h#OoHV3$IUbhXn30^kkv!3webcS`3w{$n)
zF8p;Lf!odBLuI|L{OA4wz|GF@poF12|CNuRdk?=h0G)gJ8v4M)KE99&ygm4ybn*A|
zS5Q3h0G~mTR!{!7^rk(?zx)NRj2Hh}7jWMEZz%5L!+-S~=sd)~><7EP{L$qgetd=q
zTKxH&4e<9czp@?{0{Hf@A7CPopA-S5LHvEMp*5Jlg%34H_;2<>cL+Z;10<CH8wG=o
z@{<fu6UKL30}{^v#}l{+{=fgNV)@5E#wCg3Kji@v(fqe5MR$x}>j7tC_&?LV8q0s?
zJ2)E0f0ts=@%&^v9SS|cpE46B68V49mMw|@zdxb-B>(0?=sv{{rj2egKWaK8Q}`|$
zF_={TpYBj|n*YVCP?N@&JpeA9@A5q)&+wbO(U-x0g^tf<^4V0am&IRy0bDl!A1SWd
zS$;$_l;!aKSK0y0<-gDgHRt%no6(uaZ;?YZpMRG2Oy~JUboQ!%U$_+R7xMo{XA+9|
zjE9iC!2g~?55@dHe864gPxk??g#XJrh?Meg&xRLe{6JdVUE(jGnY5g5rmCF^zHk9V
zD*4~cr%I+8{?8x4i&}o>61ZQ-U-cYhF7tg}0=dG^+5pk3{ERG+dVWPD)HLvI4X|{L
zzk^a7jr>oZz>6k+%nbZ!&HQPUcxd6DoCQEDpG$Lo8-JA6f$jX2Z(=MR{QV&ST<6dK
zdJ3MuPJW0Ah%WwB$_C!x|Bvp#oBYR=GVA6${&${*Uw;~Xef-LF0Q>p3s4(_6KjUqP
z+~L2w9ZK)=U*8MY?(rAXa$}JHD%EBV@t^)1+<pG6VGMAXukM8E2mGf$gO*49@gBhK
zBm9g};2-n-Iw3R4kE00082`2mevk8id;>C1_**DxHOc?!J1BJ#JaYiVRbcrAKDh}7
z*Mf5wbglw!k6^?bl6wVJl-uwSq~w6?7mTIC-va_I1ywu+lk`qKDDYSf;$;`iIsv?o
zpnn|rLxT4fz@V>S;|pl?6C4-@&|k2MZm+`vBNHPG6nynAxFEsz6EGhv_=d_~jtZtx
zHa$$h`vQP)K?$XBBLwag!HX1pkPV&Df?(SA9uo{TL3NCvqZrC!1@;Ba7=4^TQ-Ria
z!6+4cCJ46B+v$X$lHSRQ0{1kiNfNj{0RE(4(I7@~O5hU$e2O4^I^d~-bXqu`7Btd8
z(*#3QjGZpHz`>Bt2u{-$K11-vm%wEUG_;34E4WI@+8lwuokFy^g2wp(o)dgo1ukFE
zxCVncFGzb8q(D&PgvLTa^L!XA61Y>X#|6RpEc9IzOr<BaMDQ;?#ifFQ)8NVk%PFCI
zNuZbogXMyDDd3fY8}w9E31&&aRSUXk5~>yGmQhW1onSWA+g%ngsAA=c;71B%Tov5;
z9bAJT;S|U<!S;4YHVRsaGzt7^|JN)yNlA?sK{pkswh5M&LwCENMS;E!!LoKZdR<_o
znYdH1hDyx31S=?Tc~h|ZB>=hw&(5Q7zxD`DQ(&%N@PslYw*@}80lXuKq2=UV0plqk
z1_UD|xTJ%E#B69A5{%9OcVDn+E6A`Q(*~a&2pY8D9ts+1<@QK$nGT{n7VMvgfsP95
zmcX?!LC8Fial!0w&^RGDg2Na1CwW2jM=<Cj{E=$1cMCVIgcq*Dqg49gCX~~;ZFiw3
zjc|`}t{?h5gri4cV!v>kA4Coa=g>OCQ>b1Ja!^=LTVgL^Z$Cu5g&FHWe1w{3F^EIL
zf@t*l3SDd9nxAkfO^kMb;Y(Eia#(ny2%-VP+P}dC3fqb>m>^-}Ew~me3~qznBf>rZ
zLt}{WI2E{t3SHlX!K1<y3TcH2r>QWeaG`WIOhgD@rNnon@Qt15ixU21MPIb=?kBKt
zOgOy^Bu3a!2Gy~4;VD{y#R<1ljZ3_+{biU)5bk3Eaa{PtLU?*Y*tZ1kCklJ0aw|z#
zMP(f)g~9v4of0Z&Es-pIL`m)x;oa-Nr3$}T2f%6Jun9WTgnzDvWV$e!f>)Ws)s&3S
z61x8Y$!wuLou2Jn;p>z|IVW7AgZVt+2yq3%orSm-g~Dl6mQ^IIrZx3N;as|PON9O%
zP+BTn5D7rJaO)%*D};~M!bGLeL<`;;;gpr&YK2}r!0UurbX4G~(1o@>^+H#A$216c
z*uMh4NqCL&0L?=FERYsqJ1tP!g$t8`?+||XF|=J5=1|0?Q#ej}o-QGuPIlZ7X03&z
zH-++P5a||fdIv-65f&6c%Prwr`tU%nP=6XC{lfHE_<LIz@*%i8!fcA2-4(jB=>0b!
zY;cD+gThD&fJ4Gen%V9PbEiV-uy7jf2p$L*^uw8l!gwC+J`%pN3ED=4KYx$L$HFn1
zLPv#@Y8V_7&Zi%CT-ZVP`h;-iA?SP}%&Uatq;QoIeJ-M0JuK`Ny|bM1f3BjxuR>;z
z=p`Q*+$(aT;MYFUXS5FV5CsoF_kPh$8Mp(YO&UmgiW-t3c~EqU4rhCd475n|5q(9`
zvO}U{ELidtO??V|exjZ96#I*|QsLNPkw+;=fT*6H_h3;&7rp<Eh<4J7CPXBu10qcH
z_%UR{MO-R2ju5#;gG7ox@<m^iXc^rX$3#~i!F-J90fj1KMZ-JL7bjY>8h!Di?VI35
zf=Czw?zrf^4{^Cph)z>rIZ<?xX7D7@1)7=8h+1iuwr7YI(-W5|%5y|(mdK|U<INUn
zzlEB!qGT#k&Jle(6P9vCBHBuv6U9#hmnYKEP9|UU)?Xm!MQ8k>r9k9DQJg}N>nPkV
z5@m_u#Rbvg7ooFQ<gy>;FNz-g1(6bwGp$=o?V>CyNGubzcEFoUqQCrbCzOk(-+_q=
zQNbV(m7=>pqOnR86%7xoMFnAytPzPz(O4^bmmbPG(cdpa%T-a$o3K<biVcOM4WhMo
z(AXr>(Ol9jnnE{OizwtA8e2tu7on_8WS?6Ge7oqIsj$>3n(Ts8U7|I!Fzg$m;2w~h
zqP_u$c8mTO2z-y|J-QaRM6XSvu~(E*0Ns6}&p(FUeo+ZMO}9lA{xE+>v|~9g!d=m6
z%3cnL+8P14ClXS`WKiUA31mp*WGAKfMcF&S4vTV5Lgs;JdmWs4DEcD-eUC&tDE&Ah
zy8jYfdn~$B0;Qv(m2`}5Ow{j+zH!kwr4J`WyC|{rM09!~MmQ;Ynl8SJc(D*7yTx~^
z;I^yyOA17|iHqryxQp*zq33UpID{Uxz2cs7*xe^y{R0|3#K-C3+Ar>*n&AWDk`|co
z6wmWU<3VvNoeuC4@1pgMw|MRAaMV}aLZvQ#Vk><d!C%}x3yp`x&(JnMKs-)q^gyw*
z7^;KBt8N1qEZ*tjunP0Kc&QF-i1^ALh=z)Xj=<rg;=`{(G)%nZGXTTIp^-2jAs(j`
zW2D$AXv0saUHY&9eKF!sj{p}do--GKc<~%Jc#$A}n`Zgr;txt8azfljXKWJ1pDA$F
zPKp;!frV4zU3mZ`iw9`8ep)>A4kXjWcWClT7aydb@Qm1Q2A3iJNsO^%imx5QHOvz0
zdx6UqGwt+=k+b6Pd;oLAgIpkT#aWIJJtx*s0al*)%(D>97gsHZ!Smt^bueEbb_qda
zp}3POWs1ZP=xMwl{*+R`#bWJQG+q>2{{<-#chY;lR9rz3sWS1RWJq2TCnz9UE|wjm
z*mZ?CI|VY8Vp|bRREekh!fv(rZ`xJWh;P#VpjJHG0z{oSl@{2S#oiRFzarjs4SiR|
zfj;1_i8oM)rBQ79FUl?M5n*J_;@@)6*dm@!cV(+sMNzgk@idyj+r<%!Xz$P=UPLRB
z>*95ff#?)F{etUtL;U&_T#}pOYD#%`iw&{pyDL7L4>BO0b`o~)i3L(99TYF5bCpBl
zf|>B}zIcQrhsCKBAA2Bf&x5juV*f8d9*Hm0y!cprf{w9`ivRwT&UKB6-^@VkxH#lD
zv`&csD1<Xl#NSMZ?n!YQ6@2cNtf0+~t7Oq~sBx2UXaluZa<dzj_DQ~?<6Rz-Ev?}8
zOZ=V(cR(`p4-ij@R})-2DCv3|oR{P;x>>v>+h`B$BT1upxZPLMN5#H=68A93_)D%;
zVHAfYzwN?x4v;KKgrz`9L<ZCZNnZW{CXPt9QT{JPGC`Fxp_2bK19w#Nj~s4?Niryu
z6(K35y3I(*ifq86C39%ybxd-WR$eiZe5zQEm$<D0Ji#uxN%-TE4=FlvT9OhDOKB1p
z9{|%O{m;RRGm>v9iIO2%HIBwi$$6Sd&r15}P<M{xFN%TXN;;nh?wq8j5$5wGHF`Lc
zFLB{Q^?6Cb1{f@myhG(eg%UZPQYn&rMT_?f68k$1uv;wgql$_WN%M3dN+mm<g=m@N
zSBhj`k~qB&FUlq6qmZnU{M!$%TC#@Te>IZp3E*laqqLK+lgy<OrppqS4tQ}zvY+;i
zS0#_v0#`3NM}fEo$(#Sc-)oXDDRR*$8L~%!Hc70MsBD%Tdk6Ry$?<D&u~o967{E5k
z#~*^UOP100q(icgB5BtpEZS^zN_g?G)Fs(Li^Cg|*E;~eDTxk%iEc^#1bpg|l)ePj
zw<N;35b2ftL4AFa^5@`MzvQSl#m;U^E);>iBbnxe&byMcZD<^jY)%5XCz(%C{Xxl(
znNTw%SxG72`;z57urw^mq*{ar5@QcU9!fSApzo1ngzDBtBq0<idMufC8zQ5UbOw}-
zNlL}|DaIu`X2R_WiKiPqe@`UqC=)y>xmpMpU8JATmr`7%K@_*yBmH^<`u0knrJs49
zbco`v9@32z<l8U3zZ2RHNXz^n;wdey0pOstgWgJB(i@F1?=8LK2W39eDEg|~A?Y*&
z`h2Bc&x80$cM9p#0shiF3OR;K%jtJIDm_^Z5+;4?TgZe<x26CeAzeXR;z;T8Z*UQ!
zq_Ol<MoU?gkv%4@z6>r#Iz(IASm`7B2uqywZ+iUWr8>$KCP<A`A9P$guo?cIkgldJ
zTB7s-1rY5?Qgb3YPfEY|8!n!b{zN53$x>4mL{p@7PhdV(`u#CjIxU^pi@r2z8twhl
zrAO#}dq(;ZO_~|fN8NyDO8>FIV3zdK0&v;Vbrk75E8R%p=^UvORTSk)OKAOgPMS_L
zc%EHq9)a$B=~5{~&r6wW&{`n9uni^(rPC;1QY4+%38fdL#Y~74OM4H)r;E~K&p=zL
zG;ajD%cLji_PQiJ@gD4!OE*42Uxl=uK9*A{)ouWwO8OeTOsl1lRHRWO{k0huYNd8Q
zt%B>M%NL>bvh=HGfxjZnp?E}tbm1cOU6Tqa=GQ1~r_)bOQePSRnx$_9g0x6kt?;*1
zn!FTVv`N>?F_w1e7OD;HkiJSm>+8~(VKjD1S5Q2>OKPIRh8xl&G<n^W{$Sq=-QCj5
zw9Dy{?)n>QZb@H11JWy%zXHGeq*Ljk?3bEWqVcwL<M$wUq-&|Z@2+&;3cv@XUX*6N
zCw)~7Zcw_PDhY?AUX(ezFWpN|%&@eG7T*t~5sTr)L#Yo9>5=sJ4R*+kNH5Y_?XfiZ
z9T*&yihqH@G3j2aoE(?d(uv3kX(**#o=9J(O5jQ9j9T=$$Z9F->n2N20>E9iBmyFP
zWIyUKY!8_a75MCz?S2;IfDG?aJQcFRZ6MyV(Y^5AM|Mm_|J!*;CVK&`zOsiez!^W8
zsvElfWntffJ1mPqr$d0OlTOYB%5rG|7$j3K0T(QLdJQCx$oi?eDnuqogO*U)nV)dE
zkIEd*z;2jqC9UDZW%nu87a>z$M`NVy5ZxY8vhNYewmU@2UZ4okG1)$P@x{n)PU3pS
z%Jxu7Gfvi$hcU&=W@JNYf-Id*HYUo-K7$uYvSm`Zc2Xv%SuaI)>Uk(lmHkA^z|*n~
z6zfZq_2z<0m+>}3^%<Gwc{FCo_Ph#5Gi8CVqtTuv``H_<*|KN2&~{d~=VR#3k#S3)
zG*|Y`5^(2a`+oz;lO@n5Hec3HJFoMysq_J#0@=4>*e#T;pf9Bq$vk?X`+`gq2Jeey
zCHd&PDEsjY8cSsD)8S01?60>mz%tniN-<or%O+@=E|(cxKq_QMXqK;(ou+#HDw!Y#
zc57wN(9Ww)*26~QW!ZkJ3cEs20p2dM!&FdFFUz8H$&Ioq+Ilp}43r3NmMuRGu2*(p
z54`A;E%+Jc`(<OJki0GXg5G9#WcK-KxC(b=pV10zKsH8)MeoU+5&;~P>3)NWA=!r%
z`M59pi^_I}WqO+D9>{ih!Nfz^4^$2FNXEMi??+_4<o073*Aci;*>h{4dQ3J#$Arga
zG4w|u6SDg;z`4lhP|e_O`7wJO?7GUmf&g@r2l%1YUGBXHWRLu_VIcO(7fK<rPd-VN
zOdj$fimUCHhb{(pK>kWGT=SG4rBu*C`Mv9q^pd+#CdgYpLGz=J{J>KXIV4|7vxl$z
zvwk@0C;x+P7Jqp!#||}z<$aVK50Fn*gA0^DOKFoJ`IHeLg5~d0!s3WLjbfW2^1&@I
z5i0+K12sqG{~Q1pCSQ9VT)4dZ0B{lVW|}4=<qI95GfKW1i#&&D`4@CQ9h2Yv5nPP?
zFPa)+<vZ5U|5nGzjr3NFmz(<V%OuFJe2>8#mrqdW;e=fC6m%!bznBVqlKeca(@)Bs
zC^mCSZrK1e$#M=A<D|%s(M~Z{{^VI`IW3QQ5hP76qR3ym{Mof|^o+bc43Zi0h2KC~
zraT&XCA&kGd^r^gWXrFggYL8PQ-L5k@+5cI&6R(=6l%`NH-8Cyo_s##hw|k+!vHuh
z|J@gj1@iSPp|nsg+zwJC7qo(0kYAy_Y_YuRFn;Zea(DU|Ux~cS3yr1ncc{F#Odj0?
z)%HvB1^)x0T>c)_N><3fr^{U_Urg_~8o7e90=4qHl)R~v|5Xodm*t;N1>lN2ZzH&?
z@|<NDOuhUFRT4JHllEb}*W{b2#IsS}`7cZ~$<utHx>>F`fyNfO@=GXdm4CPem$}U@
zH_+<vy8M|Tbau)eZo$(odB99)yCJ_r@6Vg^pqcQyTkg0LT(8{k6^Qi7?Oy`lFW2vd
z7kA};w3!@`cTi~Op1k#U^xc>5pc0v3x%oA459B5zoOvi;as&Q8k~0^hZ$xfCFdOV+
z`Qv|}dsMEZQlv4tl9t`$au=#Xose&S5w1OvcSQj)DKDmaEEmO(^j(78iUHbKxGEed
zg5ak3gU+6~E7afOhuNptND)U5MMMg4`xRSgLO!VIp;}Zg#XLGM=&d;L-~Z<ND4eLY
z;E*EqI1s*y=c&NRPhrS~C4Yr4?KTc8F1`Y10u=ph-~$!8v}6lX?4esHSn<Mq^c_)z
zUxCsPMO72HPzCRO_;ge;YY?i#6d%&ZNg@?Bf5JkPV!i?JXhodJ4&AYe1iJI%6h;S-
zc*SD}bS5Y&tr*&IMe$SMPAGh9z$Getp8_CB@y=#gI;ptkf-#*^ynYjX$qJqoT#Dl5
zUm%jIm_loa(~55?jFP4>QE6McV!>;$a7J-w4t&Z`*yE{oB3t1{`|Pudk2YewISOkW
zWC|7Y*JEf!iX#*kxS&`P1uu#fLsQXsQ6Z;%R*7P99dM<JJU$GTDbkk%cS&(|8JsCs
zT&A2=g`%?;eU*w&-9V}oGr1tuiiE#ms75hoC4E1&R`EeHbk`}mj)GiP%%Nh(dc~JC
z-!v#rw?NG`#okObHY&cRH)WIJ;`{KaS@8*lsaq5WsrI&2kwL-OHpLuz#;z;O)gYY;
ze_ADVDc1ZA$s3B11@QN#Vj*SKx)n#L6v5u3D5NaNEydhpV0#sAlhAfs(Mw+!zN6Ux
z2L^gqF)Ix}<$&T^1^VtOa_0dss8BG_IHcGihHLi~%1baftVpC(>LbM|3ZslDe)t&V
zu|n7d+^8b*5tNN7oajLxS0rZvK4Di(rFy$3ieH`J;-q3Lr4L<|TPgr_Q##R{@2+&{
z#YNbs+$cexhw_stkle47U4X%Z$|3p^ua|P_1vGjq$C%)Jm6vIE<)?g?B4Pf@*_rSu
zP+2_<eL>2h&!9S3`5MLgLY4ML+T|QouA2$p!j!M=fx#GM0UL-|<?@^0;*>w6f{R!F
z-~^EbB|jPd9#`(@hqe<+jvPKED#xb5V3M-rEE-QL!)T*>O8JDMPRYv3Hz1Ot%vuhS
zROL%YF#6NVUwU9ZP5GJqJj|yn)fBNgqx|u605g=WCUBX`e?Nl3Eai(?FrTgb^bq>a
zD&v^|<S0A%P@1bucmv!y<;AxE$WspOgTML8H|a3ad1VFV4+@mkVeq#|85jlbg3@ge
zfMVrb2Y7K&*)*NjpC!sUG+mY|T__=3rrdKM_)E%53vkuTmGS>#6cx%R0g$Xz9&`o1
zN_k^0T&q^<-a=!IvepjWwaVb%0k2d3Ed$`PavfFuTu~nQ7v>w3u~lfiraVh=u}0-Q
z3e~qLlQz=&vsKBXxLli3PNLV9^J!__soXjY^Igiki{Nf3V?P6TQ@O|!YPyv-DSp$d
zG<^cnr`$=~^nPV1MG)>PZ&8eYK$)=>xO>VxG5Q9Td|EvZDObJ@_<d#C5i~wjW*|Ce
zcX*`a{|~?s<+@WKW6D{yj2&0jQqpNcIfDY9E~@o3rroNNKhfu^dh-Gt-J@DK6^(mU
z#a}@8KGk+ghkK}Ua-e0uN*e=_1FB6FZSz%W2GHlHnoDsXf7MqMwmqz>r|Lv|fXYU<
zb)c$<*1bWhkLch-u&R>kRgb9NyaUk?RR%=@LRI%>;_4k$)kcB~Qw@2*nQ#?j6+Dbk
z{W=$Ykt)9}a3)G+-wP70`YIc$kEyyN(HEoAP%tP~6;Cx&ajG)<3}w7sHF5==398K$
zT|BOu_8vM<s8T%OMWQOd9+r|+>!-rgld97WuyjiGEtN7Pt72Y)?iAI#3vew{Rl8mU
z?zC#A9DQl3XAgr*SM|`{c}6w<0-VWEDQm%Hs#fGcS(d8J2g<Tl_C1ks<E(1RQJBwB
zJ<ddHuIfew@aI&^C^Va=a(W&j`Kq7^0MDzc3!$b!_4Kc3EL6>>+qy`#nlkMdRKKgh
z6|0`fg2+Wxl{>f+6^GU!rK;n!>n>B>K99yrs?P7wSgu-U{~Etch3e%)@Vipg(gT?)
z)%?ToqFQy7O0Q~E=@gE<tU5vomMf~+G+$g*eL+w9HPw3u(b%Xe+X&L6>b?%QTU9qG
z|J|mF`3JamRfiCbovOc{gR(BwZ58a^Q0348oF3K6W{Q8_Qq^vQ7rm;JUqNY~s@WSd
z{VG1q%ePfA^laZz&7uwVU0h%^4yeAFi_3LS^+FWX45}2b;HMZ;t$zi$VO8=?n17&(
zrupKbYVI$v`$#qLCEz2fu!XSqSoPsM0F0`B?V;MGG1b0T(K)UP+=SK%Rf8J%C#p^K
z15K(NDfs20o|%lk-Rj@(qR~~oiCznC>Wo|vclGQFc(F&l(hGfi)!xgXY@a%UwnZN5
zeZ7G1R~NA0%mMZ6tx)Z${xc7a2h}?mwEpx`Ptv&yZ}k!SyAvPviy;6WQg8nWqQ2_G
zk!bW&f4dBvzdG|>4Cb)fFc*yh>g$c*0@e2^T@$4K)(2d$dPOXpIihZv4v`SG$9#Ag
zs(wEM=8vj(gu`x_dT})z4OdU2qg?g~wG%zfk?LD-!ETg#y&F2C)x-2<jbm!*>mV^|
zNiB58szbkm?l^U48c4jlg<MNeub_GAxOzH;6;G%Y^x98UAEx;tN&SKl<fQs!Ayl7I
zFJA*K$?DHX;Y^CUzYFG5?dm;L40l?6{ugLVQ}3Yj`sr%#NqBKaJtF`lL%oaw5t-`u
zX?c~UK9Ubh+3E=@1~{w!hwAck)NjzXDp&3DCb)Cz>67ToQ$P0!yw6v=P~_vhdhHn8
zE>NouLT91+ds@X7sqItgqhc4-eea>OSnWFr-!7`(qTOYQT27JWQgtnrXOyYk-v#25
z`ZwAqm#dQk;b?_AndYKOwLiVis?=Bfpu1W<jVjvf)awJ$cv;O~4DO2h9L0IBs{OkF
zuUG#{mGlkj_v{N{{+jx-6LdGKwG?Y?Qt$l+oz3bmJYly*-AZLut?II^;M&w>&jHY`
z&Y&9S4mEQ#aM#tHt6{fOo%RAubg5a6fZtH_D29Af{lWim@w?SGseY_SeU}aHmU^Z$
z0KMwy=O}m7r=I;IO!TW?asu$SdPX!X-BEwE9x`{;KI<Sdpgv0h$b0Gw^nHOrwcBPi
z4yg;MlJ~xPHN9|$)kQSjJy0*D#pOfw>U|J-q~7&B`bN|_GeI7!H@5>ms<xUTIi}v9
zOYzTf^*40LZbE%Ui%a@MUH>yWC)G^S?V?#t=je88{Jz7`+%@cf(YHs_%tqs0P33iv
zeVWhTL8FJJh79i4$f@}5fF^M<{PomyO@YWk&5gro^wOl#!|bj3a3z%aXg+O!0ngtd
zO>71_eKmb_uls41P!X)Z=Hq?9AJ%L&;W`IszNEt1Kn;%);6a-Am=FopoLq=89npM6
zQN9pO$|$%{%{aaGk7{0|fKQm_)lI;KYf23OL}(7iz(S;^ha&$`nir^I%O0(9B>XXr
z{1f;Vqj`%`sj-^g*U=fLxkuZvc+D7{ZBNi#Ux~)!8fFzFPiQ*6hBJv8r4@Zins~a|
zPHO(7ne>#Vo%TG*nw0P0Op4}X+U=)lqG%nLu9->)I?rfS&EPWZnw#Wzre@F;E@o+x
z;-Ds5v+G$XJ*#<}!sI!c2n)33YQon8aZcm*2-@;ApHsrVK(m>iu|mzVL69QNVhZM5
z)M(maqD14I0+CY9svCfpYl`m!UZI)31Rhpumea1PMq}SeL9AL$AQk%5X<m5^q)AgQ
zL}Rn2kf!$*O~y%RYt`h?`I0t`kRl)Lnk{s^tV6T&7dU!d^Xu2(IyJx3s<2B_L3{8U
znl&`t-PDLF`rEDfM+(xTS)U1!TblWFrlMD4vUh{_X)c~aXTRpHKVbK^=2j!{cQg}R
zjOniC6s2hgG;#efe@}CQ5<`O;J5{3%X+n$9cwcjqLR!O`l43|c(EQqp#)q265@>m(
znMNzzG0jf85yv$NIS`r9tmnYrCz>TGcC=1v<|G5*qFql_0K2u{=AqM7TkZ>=_G)wK
zb+k{r@;v}Ov{xwvzF&KmUO5M}f6zqZsU4aE^9QwyX~*ZKRjxy$k9Pj2AcwTa>AbzK
z_UH5XdHuBU$DqYu`*17ZhqbR{(%H=bEjI|30=363Kqg4r`xZKbweqh)LbOtv{6e)q
z#KOa)+U%218m9d$A3lX^e`~}Aiqv|(1bCG81=`+3Yr`nI7^BUP!N_8@+gd^5w43SO
zmY}V2g_h&mHSV}FC$z63cx-n_)TSSRnk4N+4_cG8@4OFuiZ+v?u&LS$v|c~0O{X+%
zn$|3aNV@hjdQ{G6xk*r(q21U8$xLnHU2tc$x36J@IogdKkj&M7{URjKX#>`P<Y`UE
z(U`Agi{Qn1tuK9`+FqdTqJ3+j_Nz7ki?li4qVt0Gj}G`$tmSM4;-dC_df%65H++J=
zQtgr(0F-HY-(qN&v_D`J4&~b8A3$4`_S_h}sMbC?4pO5Hph~7%ZGZysI_(k)j$GDm
zrXb%HZFD*suiCY)3gGLtLrdXegZ3mX60d0^zk_I_HYEdn&DvR%1!>Xd(yiO7eaZ;Z
zrfqx%YTC7*BtoP^JFf-Yb*<%3^mS@W>fwEtHgY#SyrGR^!O~5wxEGDx+SR8a(xWxS
z0C!7kx4Z}1tGz}_`?MP<4%x5WM71WjwN*#acSkFwq~Klcz5VcMK-+o*WJvo*4aj}%
zYkUBPwF|vq{*iVbZQ4h)%WE)*$J$44fsAUKcHkn6X_<6ejcbq4XCx-I?eqe2(Ji#E
zgv@T;v^cPCy6BA{?z-^^T)jOy0Xef*C!_mnpYFsT;5>A%P?mVV?vr+?IiSlj1K_Fi
zp?AeW-8Zy2^wJGZh0a4dJ_RRzbqA=H+)pR|8N^@r?jXE4tQ(*RUV!elisCPUx_y+s
z4AL#?fu&&G{5`OAM7NtJlMvmdr9g!03SA&_R5w6{-eJ0&y)YQAE8GHjgpPk7!;aK>
zP6HrH_qYRgqjm59g&*yhZrv)7cwGdQs3hn-TYx*R`;Bs_Cv>0grTAx}PIMmlB;6DW
z@to8-orf2vbbnK_Ia%jJUqVjNc_lz3Rktx0z|*>rc4$k}{q6>X>ALPZkTW{LQy>|-
zpah6y>Q*hrAhL8R&jX&VJ4<CoXLa_Su#ltslU7%`I+G_of9G`Zw6e(4eM@P?eBJji
zfSlJgor1vv-E&k?RH$1`dAuT>=tVSM(0xp~oMK%-0Zd%fd5hq0i7t{>4W+v2AH!go
zZqrj3=p|i!HAuN`Is=jwx-VNGS*d%5f;m;XXZAsvy;?VwQhhbLx%6tU)y2}BQm30c
z0MX03wRs>{bkERyb5*B%1<us#0t+zE23>MCxNEwj6rFF>-CqH&N%u54+N>L<EOCpj
zloqqCy5_eb(x$6!LSwt`>wjUPL${fNeAn%|?%VLYQ}@9Gw07z0ThZFB>pTQtkFIex
z`flkie~HFk-3BH^`gGZEp|4+;nh&M7bqxzK-aEQL%4XcvU8%)D2Xxoz<l8;nbv1@G
zsH>+FY(u)aBLLjj#mz(GuuesJ&PO`?p4ku`(S>!Q^RezB#iT}c(PVy17fD;waot5K
zx|q;yqJ!X1bh{Tqa#Hs+B{N<0h4eG;)_+gI6<7V|ry$~{x9<k$u75QfxP5xr5;S_~
z(}Mxnug{?29?(a5!-A)tYv)4dpnm&Sc;TgAHWj+P^$XU5^U?33PYfQ?S3ANdUw!Qi
zSn|`)p<CBqpZhx09M;#=KqNr_jsPNo`i&GF4AQ?Whh(t+%X0J`(L2&C5TdtGIZ3EK
zYX<Bc)o-9RVwhg~1_eUG^?g*26{QbJLT9vo&4&OU)3;B7witcpMTo@eZ{NW6iqpUB
z4G-h>YFd3K=*Q^!JFc&L4I(G>vQ)qm^(H17lk{67q4T8Pjj|D^^wAV0NYQ_70hg+O
zleU(p^;sr*|E1|i=~Pg<{uQc)J)>vZ(V3y2e;FiGzswA!S^9NjFp;gla}GY8)dz0|
zcTOL23y$XLL(9;ZuWz8MUZ`Ko0x8lzOQEa_`dkSHTCCr69TqO?&(dnYMBn(|x=8<e
z0OjAy^jlcCLYMScieaf-|AaDG75aBy2EJ0CMTaS>^!0R;SL>(HeNm$ii3Xrnf19dT
z>-5rJVE(fHo3Ek!ivALnj9k_CP+@Jo{=+CJYtW}*rR#7_?>`%Tjrw2S!Uby5i|N3h
zy;=XsdJLvT|2!RoXw_%X3a(9Gya5ik>#x!E>d<#aqVKx?UkVL%>RVO-(51gbul5`I
zJG6wksSn=?^F8{zTY$Tz7gFe<S3gECmp=UpdYSg?<uZue*3a!n;~jlP2^#O(^{ZZn
zHv{@rHniT;KTYX?L4EJ5aCk_+st_{w^_#YV4C|Fd9_Xtz@ZzC<`xXr5k$yFOCvimo
z)B|vj^(@+Vj_Mt#JZen8;2w02>lIQoPUt^5gzNM~pLz+ZC-wKY!BH23J?j8kcN=;r
z@abw`;wN!%Gki+rDDH;cwCdkuICc-0WUry68h!f=%YFm#Fw97S(*1^>P;dtfU(JGu
zr(r&=CJ!3M@lgr~FT*~HV|W{eGa=$*=&XZ<Lk11yX?zVbTG9I%X4xs;>u(6A1l(am
zc@&fe7?M0O&_Kg-O5g<<f=&SuZ1}qlx{nyv9meQG3^8ZHg&OV!!_lLLTW!FF8Hy=_
z7jDR04_t)dpFNO_G>p)66=i7r7e7<9;UoGu$}vOVHi*O+63i62j5XYN1QKWXs}rK}
zhJAGIDZwE79!ifJ6qIp4VHju!FwqcIjm9K{H@zuO8e+eM(o=@1^a;9TgYPi3q!{wu
z(3fgR48SjP+VB)*UDFKFlv7MMT%bi(rh!B6@+?Eh2*p3M4FRs`JZp$Z1R}?<<pvPB
z1~H<O4(ALqy7+m9gDcROZ&;Fw@t!wqr?^0Y;hCLqrqH1M3|x`Hy9FW_4F99WY_TCU
z0+JUEt3m-UF(fU5>QciS?%>J{B1#opGISwiVRtAuoc{n$RT$j-Kq?I*6u_)9yoiI<
z4%LQdpP;eEkW2fLTEod-LFx>%i(v4wLE-`vR}A6wBDrcvrs9WsLu)y34Th&L!r(Q-
znRxUy8hG^FHW{3c;u<y^T87ZrV#qiI&faQR1vebp3~>!0?S|KcaIwRXN$G^^h84fT
z(@sO*0r=Eq82bfEZy2Up!QC``6AzJY!_{}8t;g`UJNj-J4*vJ5GOP`SNS{G>3L^c6
z**l=+w!!%{xI2cY55dq~!-Y-wT?gz2W*Hp5XDE0A7Y7YzYGHoJV0j5Y(0v2v1h`>C
zHPtsgFx;SA>O(_kC)7MLtYrW&Vwg4uB99F+%7={_{_21;V}|rj0LBe(QlNLj@G+IL
zKQYXt>1xujh9coE#)Z-FVz<#g>sM%VH7?$XPB&vD#ckb<hiDnQ&nQiWjEC{hMIif)
zQA#*`z^HM97oJAx7I=8j`1%|)`WP>H1AfSOi)Kq-;{~c+I&94S0X_v7=PZWKK;uXi
z8iR}*lpw*zRcFw6#5m7RN6A8rf6u{SLX9iv^wd$~v#)@J8Jh+n8gBez2Sg%_E9fN=
zZG1@Q9FG~}T_F-<{EA9FV~ySs;Npxosm>wZ_}9-6IbobfUqDDSx-W#5B;$rJ(3fod
zvI~tV#sJzvq#7IbBIr&xc60-O#@PQZv}G9oje|_4Q9<kNEMq9ed$Wyy--XCo<4cqP
z$T2!oSyrww{Y~_pGivC#Ri07C#6`$AHc`^4&=@C$-6CUGkkC4HuDyZ6T;;|Yb%0kG
z16^RD(m2oz$tvRt`dDkV@eXbHYK&HzU}}vkoWa!@m(iZ^ve8|O>vP3uVxsY?@k0vK
zG#FQXhhOQMQT!1^8jV%-7HcwQJ_oMZ_%v0Fv>4Y@Dy7x<hy5e4ZASNRfoM0@e1x%d
z7#p8PW0x^)1I*trzD~8^H;p^P;bFJ2knXh}<4USQxMf@}fJmRQjn)wT#<-J!-!^)F
zi6PxFK1VBxyT)KS8V8I&d%?AP#@F{@@Poz}iir*xXDqTq^uF<<EAVF6*c<`wfpL)$
zG7pUv6cc)6e0dJI5o1(3w2c}s(*}9WI81woapQcN7blDzo@jhxY<Ll_O&UM{6#y4g
z*W2)Ex9MpLk+_<^`x|gK)0_Yhcas;@|L-w9>p({o_L@%9dv~8HpSB4eCP4zm<Y^KV
z!~8+hbSmKTGTo<7E*vuH)`RmkB?rT<pXp`Vd;6Q#QBBQZ(^kq;2AH1GfeSV@K7p1a
zrcY_^3o-Rkj3U$&eGjf3HEoFpJk0dMeELLLxM|lvKt!12l>Ue`nc`qK%2fL<#uRNz
z%YskGOfH{+#F!Z4AhD+DvB1Zfj1JHiZ|bDV$pq7x5O{dp<h&9iOforBj{Br(-f@^e
zW!h{6Nj8lLpfkm^ffDtprskU<_H+}Q0!(L2Qz-zFVS0{gL$giuqT%paQ|%2nlVh4U
z8wPVt+o<gAoXLj)fAdU{^m55J&0YrhdDC(^v=x}H(1)rEO@_nhD>AitfxBRmy$pD<
zse;mI7fpdQt(KUYZ@^xu-E{aRm?$%?KMedOla}(N<)+0Hg{?4c{2jV0O~<9sR%P0|
z5!$LvpHg(M#`JR+Bx_9twDYMmv1mnp*>r$*ul1&-wCZj!G5Rr<Yo=Wkfon7^H=(h~
z<mds(X45AJF~Am+{rGYqT1}}GS!y#4=%B6LB&N&VVS1|^jn_?11~hh>o~;M4%cQ*p
zpKh4mqm!67O;(yVx=p`*3CSMQG%C@&W%^$!xL(utOBh6->E#(1cE4$EKZbqVWSkE8
z9n%{WL%M5nwWmRJz!c>GZ|<3DXbv1Q2_4XR-{jB?(P5KiBh)-FHB%wfLsK4YNgtW!
z-@%whOs7`@@YrOeXKc*GH-L<r?$C;F!c;j0fG4I+lv$ZHU8fwGi@Ei4H10O9oDZCv
zd5$xMncdB^bJ4lSymB|Z*lTw10@-Jtp#07O^SwjhJk8e(kUVG(qQ#w;x#}2{dYg4j
zTm&C;(|s5`WcKJrpRc*{NA&rbpL!mR{^n>3T^}}=z6%Qh=0%Cn8E8Iegw7!IPeGLC
z2{tQdVN6HN{civmVm@1oVTYQdJ_X{a`AR7~4KpuZfnOxt{7)K4g!!Z&@R8=cf8kS<
z*?|M4(dIP^06%7~px8=`x$y^Ri8b$_$t%u$H4R$g&BLi63FcX&5IJtX^1)M6wm6(H
zzm@?PPnvrdK-(#^%iqwQY#w<6nH2M6Ft}86)hiG=ZLaacn9i7U>DJ9K`*(uNG_N>~
zzASUO3FfoS8-h0M#Oa9@YvI#5^I@9S^UM!uJ(O>Lnvcfw=B=^tsnFa{p^75&I*RCC
zF!!aywPJJmPBdOL57;4DV*WQ8q}2R)3G9`bg|zP~H_xI(QiZu99g>x1-8?i_nZ4+%
zBGu-Fv>2>0XWPm9TJwrrwAPv5oeP=E<|YcpTrs=<4(_V?+(EcqZ;rnOw;RmU>Ga<<
z^PD2!8qMb^+|y(}Mzvkd=C`+lYcan->#tUG-eLgS%pv_C?dBy^wAW$YOOfE~=4`5g
z>om8B?Xc8kUV0MvZnJ@=?jCcC2N1W+*Ox(CpIL(%6Ni2?LW_7R%$MXaf5#j{8-ly$
zzbS_@U{?MDgZIo~RQNw=o{|8aL*~gf5V>!jwi@tZvtk?I56pvhkcVa!eGYlVynm2x
ztH)-~B3#)~^XO9$9Wyu5(q-ISgA>>ePt31U{A1Fb@Fg5}u`Hzp?rzJ8zu=my#Xk^|
z?v~P4!1q|f!y&TQl1{I<eHK0~YdkD(&{lT8WgC4~;DF@|XK<dDuPID)(6SLXC$fi@
z7P>;-mP0fN`B;RM+BjqpuZ5_urHUR=Kg*%D5b?J>qVV)#O9X{<0xYKvf&^Mt)AAz3
z(smUj)bhC}$We<kO{ig()ou_8xBTx1z#}ZzD48B<*-EjED2v@6efDU}dLaxRvn(&b
zm|`t|Q=BQz(rAHbyd~%yyhyP0eFM?smWA|GoUj~-L0_V!q5>mKvY6h5wv(35X@H-y
z?2dr>6pMrpT&iW(%MdwjdG-zbFlm-sA44+T^6x4rJ7akv6e1aR%XtMlGc8_8V6!aW
zxIj&|WzL5Hp0zw<gKOt3^S*#cp5+|fbNQAqDoH(W(bHL%0*jkJaD|p<X=_+yIcWm?
zf~CZW(HC1hXlZ!SvSc&tmRQysFtSq1z0bgvStcb=eaT|~<2NA6Ex-K%rz$Lui=ed9
zvhW(XDoe*h^i^9H(~_XZ;!C^bT8krXVCpP`6~JG%OrfJxS1b#EhVHAD|Ncz7-ZGU=
zKQvfMXhm?%5=ZN>MvL(-lr>r6--n~kmKP~x-C}XGQ}KDL#YDGmho#$w&g+(%UC`EP
zS-Jp-F3axgxav17FAt#are!__Ou8-qI^#O`SbEn%@|MLl3GiM^JylTjSw5llb-!g1
z-5$3sKYR{y$HM<_k!5*-s<8$viBwl~&!T^kqNjtF^;B^(Wa(XwG2OS=D6BVZkp%<z
zz;dY>N*`JRo`J|C%MKdMh^31*gO4p+*f2k8xr-x|4r7+jd@z=AOG+U`CM@q#!r+M|
zGaQYRmeb=PF4nhaK+A4x!Rr9HTIYU1UtV^zdj5u1cPrxq$n3EmqqO~A>(3NK-EU=3
zrtX0C%G>b5)2eqw<3VdAl`eT%v*?!fw(cB;zdqJi2QijIR!b^4U+W0HA^oho4ubQy
z&VC3Bhpiu#qcOl*@+`&~XsvyTs@H<7Q|94%1zUgl0j)=@O->*o)*JI-Db)HG7gznL
z^#K)0g;_&rlM!xRNa4!}>kKL^kF>t`K6FP}lPSy;ZJnD9?wGZTiYjBQCHc4(vDUn)
z;Nq<96yk`t{zVlV3D$6$v+c*N^UP3l(i*G;d&=6g3u=<Bf6$&I#rhx-qN&z@K7rlS
zR=o_`(yX&y!kE&nE9tu&XRPmC2A65Im|!ByI=u<FZ0p<f*`%{p7kc7ytbfsdFW1_=
z0>8*PYvFv@%d>t<_VVr47lJ^~Tk9z9Qeb_L3OEX_AJE&S$QoRSz6;hjH=wV?>RyJ%
zQtN|X;7pm-^gZlWSRLq5skDaE(zMEYneOgdYtngGs<TEe0^qWhy9-+Ct+OeP*I=Fb
z4jQjn^8)~AwAx>;25qutRYGaA^|M=$X}A7PXAC;5wyn^1-8wxLq|^EVg-yGx_vsh8
zVQqU2j^4ChrZrx-Rn!TCJyzZhkXu&w=iyVY_1{xa-DiD!F+}>UytBBlx2+C+5V>P@
zs06udU1m4K(ttIdRt@*8t3QQ_LF*GLT^h1JpcT}8YxyEr8n)_wgtiCPfA#|S&^nVM
zJCCef+8>WtXOh9k*7rw2My+vF203Ppq=JNT>*R~DFk$^7AB|6}0pCK)r1jK#a4xn6
zH#_X^wyiw|*3}kIxh^-`^Hi7QZgUI+exI#^VwxVdKYs^szpajsQ5>)dDZ$}so4XVq
z9<;eV!UguSInlN7wmo+fjXt)?yHIw>=1u`+U)zPBf%CI9j)U{Jt)Q3UVcQgU%3cK6
z=Fmze&=$E3_#j&j)yW0hexham5gWG!YC>%MBj7@9@9H6P)b{1qFc@abPD5X~t!fQO
zgzfw;*p0Mx(l@%IY`^6}OSElT7Ti8&E1)cTj4ikqhGK0WxWSn?+w=;Gp2pjp=Kz1g
z7W*eU6Kz9ucPH5{J;4Z1+U9Qucgl93?)79_7iHX1ZHqK8f7-TbKGdYy{=S64q}%31
zK;(?=R6gux+5Dz}WZQJ#!I`tR#s&a#Y=>V0muvfV8+4wt9i#$Nd!8+r^1Au9AMZi;
zd7JNcv|g~~{}+R@J*3ZQUbJNtKwF8ekm4?-HcJHnWwu~<XuD+lgh~R+ZIN@~OogrH
zI0jK^n?WTE)wbX01WJvKN4Q#>+h1_B&US)Ub(d|A=n21Sx7nwnwcfU-2JSc55{%Gx
z%~nEpLZeOT2Cm6AuLl>u+4h_ilC8GazX!g}_BHJk+ifm%CaJ^LNe}gP+r3X=snh04
zS=ugJaW#CpY5R~$7Q1aJlr!qFy-Wohw`@C?U=Y1FJHjq_NNhW)l&IhK_E{KwY@0I`
z+9qsE;vq9>`!E{jU7fyr1G@J(G4BH4;q-7D0G>{7)70(l)UySWkxnHIFp=m~eF^4M
zoOV*|Dcwn)1CcDJ>0h8R$0=NhappN)rLQFxIEn4FsVjC$#cs!;+$qczYMPxA9nsnA
zlvfC6?mH>pK;M|tbMzayZI7T$=)UbP3F!0L-gN;6k8J;p!g*2KZ%&}``1aZeaH-o%
z=u3S$+h>o$?uG5wXM&V&&-fS?YPQd(da<k9i)2*2=Ck9~nJ^K$W0gNH)Uh3RRzXeb
zj%{?xEMv#5HViv&N7y#_RJvn(Df()5@M#Otv?J37ksCV>Q;o;19m+T0+Tf0FRWLEK
zBXK!!<2&l<^pdOd;xdf$fOEY&8oitcX(sh^-cdnc9tm(hJ^@6ibEG@)G0yI^^Ga||
zp9V`w&a&$eO?EaB@U(O8KQMU4`8I9LGn`-S1|ZY<31#oIoa^I&JLkMG8C;%o*>(7I
z-uW>VD-}3@y&HXn&c#h2Mb2eHjPru?+y7Gbu-N(d|KQ?9XDt;ylsYfngrSu=8@mB4
zcYco685Pd4-=eY7xkC$|s+>Kkf~ordG<^qHRM+!%?zy`QyOf39d++YDuu-G2#FC;h
z#THA9iHV6ujlD%pj45_aG)t8tAfh5oKn0~JARr=0u_8qg5D=9rsDPp(qS*M}$^Z8~
zkB{S-GxN@zv$vcxGv~TRLjmd1Ek93zNZFPK1S#a@Tjo*V<k}X$`S7rE%Vat(T(#v`
zEF`aQ8Py4q>Mh$S+}gP18a;x|&0BN`0pKJM9OEKrkzdX|3#VIyTNw_As<`2FrB!pY
z>AcNNZVl}!YPfy^MCv$y4O$Ics2cdq+^6(TXy?98!FZl=2kD*Q%)r2dlkHmzlt8xN
zApd{Hq#r2<@{aklB((buTn$tGB9h_lyL)Jv+24lt@}HV^p!c(Z1JV2W(hq??DvwfQ
zqsRS&-Z4K=HP2WXo#q|4cpTuqc&7^p<2$KbW`Y~ld{1nkTGL6HGr|9Iu?D)6CznC@
ztM4lzGv%z=8r@${z7FMYO6YL&RA2fJKfk?p7o6`bXsJ8xtC8S;-|KCR>W4S95t#nY
z75qITDjhOEHd6p*rhhMh&Kf-fptBQ==>5r(o)2?Yb^~GV2UHR<uU{18=O3kuX2IDW
z@E4Zsp-kDL3!Y#t{^A78Ed4475X+LIFk3%c(T7NuC-|Xv#fMZgv@(evxxeI79C&L^
z0{-^kHd4jub}o@}=APWGW(at3Tc}jko0Fe_T_5fRy~%cPz1{(YFX!?YbK%F`J_wOr
zO0M4?DAsc^`^I@=JDjx}<9NvhU}+}zU<U_-Y-h%Mgv~;-F@0VvcqKr+*)PAtIUhE+
z6C>Ec-cU%+mw7wDydT?F3=`pO2BpCEGwl(OBkWIl^2D<HbZjM#jisl4JQJq?EP;)q
z0}MymCuWL89AlL+z)oa76bwjWle{34%yR01eVqMHi<%VHMOouiR(2D1)7a|)Xr;5W
z6jeIO7X1m440eqUww>S`DXx;vAIA<>ev)5J2Y561pB}=QQ~anFFf;jH8zGs+S1hFE
z_-TF}rD(GG!XE&W!<Qe0iCmto156&jW&vC~gRCbM&+@aV$m|^7@(mQu^D&=+T;RXo
zj=@~yBL_evpEtw+`x5`*pJ)~Eo8ALhAzviG-y(j*1dw9hLjvYyenvTci24e@W-Kg~
z@PB8()2n;~Ej&v352nIW8DHBA8s+>{dMIAwzt{^)75oZ1IatZ}ody$Ce9k<O>%2Qj
zR`Yu)-+F_;LkBHy@=yMS<So9f3#5ksV=^q%@@wgatK)3~sF=2%7pV%cf$yfvu93H+
zXx4516c5tGn=1g*%#WuO_#OV>RkZH%O%^bCkKagJxE8+Q1Aw;jmcCGL<DV`B_I*Be
z0s0>B<rARS&Tpao<wM?=N>3i~H)(tKnE$3PCc)gnU#B{@Cw$@W;CAvaw!_n>d^bHr
zx_E;Leb0C|%6vTMe+mY6H}6PEvlslSOfX;a30lB7%Vx~QZ|5RAQ4GCg*(a1QIxhQs
z129u$;o)ed$_CQAI!%^Bm3Aj&aTGL6H_IF!fO}GQ`Uvc1$inx)#S&Qp-IP~l)2>3X
zR2Fd_qGdAo0+3rWUn;4nk!4c|vRQVGO1<yMOll~!$TrP_NUKcwHuOB@5|vqb$v-;)
zpS<PW7I4&8K5!-`)=$2D2blhHbHN&Tvs3<tg2R#cFL$AFO1^6xNT%HK21u5CDc!KA
z<!$GnpDq8J)_FPd4d25=uAHN5HBbIlF6^F>7nPuOPTtfH9-fywQl|2PJdFygF3L0M
ziwgPj{@2iVNq)N(W((vS%yVG3P`-mg^0kV0_W`?3arz68dc{3zH7J%0gnpx9NH6H$
zR`jOnZc<FV1%+nC!$I_GDOw)E!!AYn8~EF!SWi1DXNzDuO6p=UyA)oyTGUXQYKMh0
z4awJ{uP>N>7XABCl+)khCN0zgEUYQwyUXI$OSA$l#^j;3$Kuot!0fdcODp~$i^&un
z+Gnxt09s)dM}Gwgx7bt-=6;KdbY$s}#kx!|(=0q_CwRgFW!CtaEgV`gGbb$$ro#Lw
z3lA#9%(B=vii&AZTl_g3zGYkVqC@9777eptKG(v|39WpK_i6QY$s&kuhXRWx7oZhd
zZ2KI{A`8PEz+ASNwifDFEY?rN%v4##+r#ba7X2=wRc*2P0(`n*kx$XlTNe3L7+hnK
zM+@Ovi+d;}G0W>Lp8Em2!J?%VzBO75PXu<8Mbb#XG+V5tC(K=oGjY(kXEE~vL|QFQ
zo&>pX@#_>wKCozWhI+e2D;>6Twd}JH-UnM|KZIV0<&?`{hFYfh!hD$JwtQfQTNY5N
ze!pc!2vE!smi*`FjI^B40MRH*?MBEPvMj6scC=*>9UqCY^e+VSuw^&J6k;tm{sCv=
zEVuUtOuVIi6IuzD+owSCsHJQ&P)=C(r=4%Q<rF#|kYTx$-b$w|OLKskY565x30am?
zDSVu5wj4^Y+#E|5ht6EfQmSpuv)nFWqRv=GZUOV0<q^uZowuA%YoZI5i+=~&MavLM
z#$K{~MA_y7%a;2fg_c1h&{u4^EEy&)TmD0#-Yb^fi_vPa^w|ydR?83b(7JCqA{b+N
zU};`TG2(X1o%Er(hn64GtM0L7$ayGsSZ>aTXs6{edWb!>977?aH<ku^NA*|^J`a6o
zr4NIoi*iafoN-mw!~?}mSw)A&-IZI{V=NxZk@V2ruC$_i#8c@z6?$IEE+YmQpj=_5
z()eA<!E`(BR!*pf;vQxEbdVsW(^e?%QyRuWF-ciV`=n&$3VP$EDECtCEmb+2ijdNj
zU(@%HPALDSSVX$=XL^aBR2F`PR)#X*8fNB{(v%CyOl9B$sAnm2Xx(yJx!@FqgR_<S
zbiy-7Ih!H{xym7{p`WMR^8y-Ylv8OPe^zOCntlr9Y}z`WSEkS-_=586FkoL)jt)m(
zzVc6s&R$ZkrRZOQ^6Gp@7AkKn09cVS>Kl+^Wf^7suP7gtL8L@^_&J4xuPWb*23n~y
zmx{d0lpp*B(Q@T(H!!a$y#<I?C@bj_s8mj*<1*KkC#dMSTDgFB#W$22pTO=-rEML^
zEoBkqNNSYBDbHK0+(E~$>Xda9O|DnIoeaGOrAX`kMrF}v%JSV-_RtZ6CZ*LBkY;62
zJq+GaE~<g0yUI#h^4(K@LJOi6<)2ewVwdWlmvAjm71<vOp{g<G02-#Ud5WQhtG=gA
z`F@oRg~%dRvqu6fO11b1)DNnH=7Ahi#aTcvTD6;pqvjaZUmL(ZqFO!yFtI8H#ogjm
zIm<xeRT+x`dQ@dlp)XO@xEyFnswZ?<Hd9qy57)9(L;Jy}Y*i4|isq=EF9qmD)$lT4
zmZ<vDLh7o@kGANgs**emsZ8Z*iN11GB^`3OW>zhY2U>;7Jq2@8sk(UqGF7T22VwWR
z%IY*k8&&UCg4|ZgX#v=zx;7fEW>qDn74N7#=zVZkwT1$k_f)@>!R;2+J!fFIsUA*+
z`TMFrXzlYr)j;8-c9l91&<|BSMH?Tf%&&IB;A7P?I-by>I`tV~o~V{mRZgcW*$>!H
zRU7G@{!H~Xr8A$af~k<DTa`r1!51p)Gk|%iYMlr2N;QDuBd=8<9%#K$wf~G(k4nIq
zA-S{F9QuNbi<N#Lh^y5E+Gn^~Ei^Ah)7`4$DP%mX-jBjWZMRxPD>zT9Vf*2}kJTjl
zVRu*^c^^z)t9NN(<8O6oJz6`h?%Kk&0IQB5Fn3vb9R^CE)yl`f-fcDZE421l8Mi@w
zzm+S+86vE{r5JCdRdNVOl-0!zv>iBTb-fnNLsqr)6@q9hOFAjiV3kgRpl4Qdh62sm
zdfq}vx>$Qez@V%3`UG;{dR`qw+^zr0fukPQpG}6Iw{^t>i1=8Kp%UgD)+^=$)7Sc(
z8Iu0iudINw)0!WKaqhCtx29sEK<mXpkO{IbNW`zU&-(0#=nS@YSpoM$tV<t4G0Zw?
zCa}Y;1F2eTzje#|=!>w{(Cr^(olS|Z1J;#Pzk1O6`WU!&$a;Av%*R--9}ebW>*pIG
za>V-cj{z2IeR~i{igg_x)@FICbv_lvrdgk*kp2m4S9-anTMw0>c+z?Y)$e3jx3__0
zT92kXJ<D3z7tZ8Z$I=OgJZsrkkUV3Zx(aqnt>34T?K100R*)>WF8Bt0*R02$MXSPk
z5gj3~w3dwkv&!0)o;v1w>$Y+<8>}xiqqEU^8s%YbTX!e`(`;Qa9|LW%K1w0qR%?eU
zNVZuoj)(dC*56Pu(nIUP6e4?MeUpmWA6u(>VS+oX^ZH;cUDm%W19@g`BZuU3>k)l`
z(rq1o368$79-II}FU{6xt>DHh>x5RAe{H>qZW%wD6SG15ZOjxq-Dy+V4H958eiWFy
zY}#&s1lr8cgx+qOyG1a+$L2KM6?<(y(*irl=3!re?X!8D1HE9I=e1~s*j#%HBB3^Y
zlR?64+^0e^+{PSt6Z#Q0zReJgv>EUgNR*9&p0)>Urpw{tL7Vr_LG+N#z)XxV+J=>Z
z9JYB%pY}Ln(@r6SSR2z;j4;k-z6fT5P1&~?=usORS`Zzxd4D6!C)%`s4w7VJiN&fs
z*=7Qj^d7hAXC8o2q}WUu4#iZPWzS$Y&E^xT>`k{RISArq8<7p-Z98}dBz<f-s@)2-
z4W*A3h1ynsNQ1H6N+p5ewhpv|*>7t-0t%6~=l+GGQMQhh%{gG3R0s<PZ5L6N;*jn4
z`(ZxX_DdDr7RPL#UV&35YzMCcNw*E83ec0bC+LBZVJo9RUy<!N3TzhJHhvD6%eD_F
za!_IW2fZ6BZBxqOc9rcds_eLKYkCA`we0|Vh}^L4q=(2&+bg@_;Vs*=yTGim%^L^{
zwYH~ADI8p9TRIY6)Z50cf@p(nFPgnZ+p`Nmnrt&@!`W<GO4<E8woxYlbJsS%8_avQ
z)AvB3!&XLN_b0ZSD$&<z8%&4wp4z%RheDU_?yu2$W_yv!Q=Z!{-vrWaJH!FZ7q&MO
zsF?4i?VusxzOtQ4L5A11@0;P<8{2p2nsZhUe~CU9HCqPas*W)L)J?sDN*UeNYe!;c
zJk%H8hZoz`KdwT{Q~mC*kn~ay(Lvo?eU;urKI(twg1JLIeG2B+SH1Zn%=@X6r~t?8
zuQvY;#hvP~5O4$3`)Nvdsbe3bGf+Jm0V?@!^_v(>+g|nR|JFt7$X_6`Pwhq}T*2xn
zdK-qQldQoERaci|X2R67JJAYPODY)LuRdG@^AYNo^WamI+My7w1L|XR?CYReZRdsY
z9#YqzLua&l`$TlcsCRw<#lz}tlyf|yZaV}Maq5~;7)-o6NCS}s^@@p@grn*T%8ndU
zPdE&eMD@BAU?!=pN5hL`^~OkG9#=O~sx(DiM;qK!_2U6xrm1~uFr;*~dD(r4o>Xh-
zltYF(Wi#|osbBAdMyC45{xF}Vp0yaQ)9UZ&X`8JcLq+r#)o(umTE6<18Bn;SZlKRm
z6sYG?dcI8ki8n;b)z?cg!fWc=3&5;UZ%PALrTSgUQ&*`!Jq@$h)z0So7*n<SekwF>
zs0E70-Biz}qM}>s3ADwmQU4tZX019Q4QO?0n{7a=SKmbpQQn~Lq;j0w>grWsHmUn>
z!O)u3UR1<!M?KOR3U}2BN{HN3&!(44i+ZykBwN)n^vrHk|Ei;K@O|}nqoDCXt<{6u
zu0Cc0^PzgS85)n&tQyWdQRfZ-TBmyLCG<U2JLEv2OFi)t$TRgGH;6n}XVHqWTV3md
zfxb|G5D5hryYrjCbhS$k#CYB86uua)yWLN}V@TWWGI!F)JUs2*sz%exZe3p(^tRhX
z%LX4iUvh1S-BEhA``S5DouQxIK}rbv+j%Cz?oPW&bT%Zw?p74YF1zTjVJX&rq9q0q
zZyzTE=281;>Cj8GpQeX1$@Ux8!$OLEpA0CZ*^flsky)N@e{Co%W!mqjRBfewf2tm7
zv`-iX{oD4d51`d#ziTd9&Gt8@LH~|@W^d@<wNItD%VYb#w4ds*pE3}VUG|UdK%U!2
zQo^^}9$^g3h5ZpK^Ll9?bsb*3ve#Qe{k6T<F)+<<?5n7XsmK23V?cA(tf%YQMe`#q
zs9ZJYsHnnCGk7vId^OQKf$gU$7!H^)&FV-n!!@P5Fzg6T7(KxwHNVtDBuX>%Q?w3f
z8v8)<kVZe8CP7nk845|78HZr^l%|Jjv@^|`<#akJOCt@2%mvL{+8JEb1ns7)TN6|V
z{Y#qD6a_EPm?%w9sJTr?(uy?6$<Qm-WYTYNSz}lVyH_+;GeJr;OCN%HRU<otA(d)|
zj{>==IrA+Xy`}k?LP|B7oIhZwR%70{4H|Wt(L2zr*EE;Fiw2G3N{~iP*ei_Uw#Mf%
z6q___pP|*PNozvuj^-Mbir>|o*FgQArlAKuwP^ZN<f2vc&o!vGX>L;y$bHSpArN_>
z*){^|?V1iMk$9+?VgcqO&0TW<&>m}=C==MB=|?B=o@hqhL#tEM`)j~F)y(=18eN)4
zE8*cY&G%Oz@?66gp|4w$e+`l^G!Yble5o0G5++`0^ptgbt+_+>!Oq&Pt1*WzTDvYx
ziL3TqTIjlI(@l_c*9Mi)MZQ;iD<9ZF+PRZ}9jskC3}_+Rda9%e*Iu-R;(o0iy)h%S
zKTL<ek=ovy;eM31^)gxqw7=2n?x5E40R7rpod)KkwPUGHBu2|7VxA6bU%w6YBU;3B
zaF1vww1OF@?U+JUp7Gi_R3nj~T}t7Fqgs*DUdObaTVWzm+p--dlC(opfR?OP^1wc>
zRlfz86m1|KAxPC;U5!?n_LehHPH1<1ff1%_(`eg!QX5Un$PDe_R7jrE-le!)rq(?f
ztt{<{59niZr?oGS!bG<A{jt!`(f+*w8o64ZDuCu`J!hlujCQ^OcF$^`?Zzn1X-Cnz
z>b$n}CM;dh?xpb0MQt^O{_?eD1E79MyYL!B3bav_xh&LLQ5jy5_Ammj@?!0DT4Y_;
z-lmVinXhPjQEsY4yN1pHT-C0jms_beKnc+@ZQ%&Wlxy$M9eYi?xEkgwv^`|EQrlz&
zW|h{BhsbrUMD+mG+UUPPZfHjy$5?J^$J0vamUehAv}&{h9lWU3W>D={owg(o1FSb|
zJ!nJIpbZrv+NkxS!zj148=4{0r2WkR*P6APtk8EyTR8>>?`p5olI@;$9#!qPX#MEW
zX{+{R3dYo?wV@!=eeLftaP)z;?^H0`wNo!)NDsB4WtjX&TGjg?kF_cE8+2&RbCj6b
zCt8(=W~cVXSeSUKeQzr4c4-~yhkd3^E(GXv?Fl+s(yjII0(qgmORu_@+LDEke5L(q
zI@DilS7$=<jn*?B<L%L|ql$iK;m`L$T!fVC5OEcJsW8k<_>B@4?n0dT8#FzHA}T4~
zE;#;!mZ$KB;*efKUKupJg%9%KlaFv_E&6r{*XekIuTWSCOMb#-%K7^XA5+?Rr|{!8
z^aTj+<uJcXNR5F=piurBJlrjOZvlVz2otWNwO80l#{q+cccbYYw@<i7vC3fKeJ_v@
zA;KN=6)L!SK|f3wLJ6gCfu9CT`-LCrp&cQt-35_Ip>q~2MG4+lFqi|vrLRE_3cu2)
zfDQ@!>6AgV@O2nOVuapQ(s)?-dm8kP2v?~rE><WDqjI1)VHMTG#S4!<f=q(&{b7)!
zf^iYZF=3zpFA{~f-UVoq@M8x|BnxL3fq7h5aStLX!bh}vP8B}-3?obv%>Uhn!b5uH
zqzhLmE`CyYO^44igk4&YQ^L<w1ClA|uw6FGvxI4(Fn?P3djmSN1ufNr<OoaWp_MDt
zEdj|B%H}}hjPTY{NS+nGABK54C%7!e(9R2X-LQK>aO*<rqL4v}!h9jw1qzphhayOU
zkWL}PLZSH!kRsuoFid5!@P-nR<1Y*SVgY(ZIJ6BzD-rs~0qv?V@CaI^!c#p)Q6|Jq
z1!%bt{|;QcCVcq><|~91RLNN>oY}WH8hNzx)4;wVj2w)<n?f;t1L&48vIWpJf=wDo
zt>8>GBy~dgC6Iby8G}NDaC9PCjY2bh1o^hW?SgufP(`tZW}%&y`FDihDAIXXn6VF-
z_k@;H=xY%s42E8-5Jjg2+Jp(_DxlpLifGsUKp1roitWOoDh%|YaEgNaj|ABoTu6_F
zoj=0u4naW?%O}DhS`u^$ezAagD(t%j(k1-47XCgHRJKrfE~Hc4U$-F8h4ey*riZ{w
z;r!>2d?jpI3Fd3zJqL>8zY+d%2k8+OAA_Q^SZD<p7qK6ML0559DwuBK8Y+Bs7cX;=
z^blWB7G%5lFRgby#ZPG2>?J;F0=Bn!h^}KFF{}q<huHNNM&>IXqX>eZXr`(uf6<%1
za<WtOtD@^TKuo5!=`OL$8lZvV?takNEe@d?*FEAA3cv0Z-{eCiNKBzH^*-@P2S~73
zz8fY&#Ql}f3l)FNgJhVPO55yk@rEb*_KPJH4LK%S^ns&^V&Io>G)a8@5k!(jO9Y0^
z^5f!Lb>OCm0^Jp<;uYFpr-_?sRd_;l=>^bq@y&V+?WFiB3$A5|$^Sy+l=%1%>}HBX
zsmvrxOgsZn9G=R7UbdL<7z#P!g(ondD_Yru<cYtzK;ew|y9StN#UH6q-F!~e?n3jt
zc)AqL3*!DOK)Wc)=>d~3R?~jwk~p89?ggTmih&EoRefNhNZj`vXvO02@1b{DyfF(X
zSH$sj#g~X<|AnJh#ZT$|RVsct53ZGo!@|%i7ne}6<~8xwN*Jmzi<;3us}yh2iK!}a
zG3^_#iz+HHsunF0Vd923Jrbff#qZBz*tf)!93*SRi&RooD^7U>yLICGRE1kFPIm=q
z5Q8XI*eH&t%j34Fm<y36aW9o~H;W&B2$4JDeX4rAE1IVkU}*Qmr0;>&B95hJZ>#uG
zF_>-Qy$&ee7mL*}_&}_pqKI~}e>D0YiZ4<@9*I>ZjOnqsI0UYBh?{fJdLka&4!fP=
zv<tBGRJ@;rR+kt}1!2#`epKT3T&x)e^WEYgGZjR<5FfvVNq8x`eF5$(G1Un&uf>j&
zAaBGw@4`}#IMfHuI7@rxV`whYt2DG+r65{Hx=B|z!LGX$O3OeG$%hWzY?rL)hV_)B
zJ@CRy;u~SXTdJfippUej3gC7~vy$ol^OgRjE7(senh6<yX$-yLcS>u?Zh$oZFwk~M
z;~%3HD2<{YX1CNs`Hnr(t4=WYO74`)43Zj7z^8qZUWZn&6#FeiLL_M@1`#Sv`v#*A
zlfHNjX1MejJz(}ry^`rraD=2=37JT#AC-PbNn<G<aX?x`AIdo>+4;cXL(*Pnco8lA
zK~dirsp(yqI4l_`sCh&>whn!<(z`355GN@OFcB|Bxq&1|$o1o;Bn8o}a!i`K17L~L
zWC5)tX=W9z<C3L8KS2MuwE0tvK1C}03L2@BtrKL@q~GXvI3Yz21T$S?gD|BhCHrhJ
zGo;P}=$(>Q`$IBQ8cMPHEa}5>7|UttV|uJ-OTW^r=SU6-P{@^JFQJ|%S$=@NGtyit
zTs5DSwtNHbIjL(8n&+h;8;D+z=JH@(lxjZ&XucG_6GOWs{Y%&d(yS=VdZF})aw0|2
z5Gv#-mh$P1b6IkE0)tni_b6CUB1K+;<W;Gy1AV1ZG5v&PQr1wIFPFR~gIqI9V}F8)
z3hBp>p;#$>N-K&gsf~v-*QFKo!&FP{Tk(tBkm5Vx(@iONC?s!5%l?FZjr0-CY^`LX
z<1%$pdk^~RrOEx_Q-kzlJro+Hmis`tEq${FBWsd;t6`y8vZQUz9m%}TA2N5P(r}o#
zCvBp~bc+;ARZy)`0+rLXNv$;yxi8J8y~6`(;yIXTmu6rQAb%+Jdw|v>slgAe$I`1w
z0PT>@^@G7Dl9qPVozlJWKzS+!?Sn{{<Q@;VpGkeLq4iwyG;c$*Tl$>N(!7uwzk%XQ
z$%A$|ucYDcLFTozbTCBTNN>@;q(?gO9YmaUvNsTM(T$>IimR@PPJ6rQy6>RRT~|E@
zKJC#Rrw!^}UBoH$1?lz<L*G7~wht77bu-7JFGLspm>#oXx^{nPgzLnEklC-x>IG(m
zZj>X;N9ukmhTSOL_21Aspqnp1|DbMk13(Yyc5a5-(YiXysK)4CP}udbZtp)pIijl{
z01~V7rD$`UZb~E+;&o&DLNY<8QRC-5s$17hag1ZSI$9GX>OwYvo2=VC3mV6D@?Swx
zbiua(nyS;$<&~!E)d_M!H<%){>AL$=z<N^GBVaBvbU)C+-BUUb3b<tImeARoES*g?
zpik@inqW6uw{`{ka&(5F=*!jNa>D(Wr&~j%J!f<uHA3dB?kKqObGpxcVdA`Qm^DmX
z&=u1${EIp>9k9;VxmLi^CEbn<fGN<Gtc7HuPPmT?u}F7`zAsX&OWpv?%esg!VE&5k
zI+-ug?WVoxRo$wcAf-CbFfh$!x(BPEU#`1b4$*76MG+tsy1>n_Td6C$0TWfaHY#km
zuIr*SPqi+cw&FK*`|p6<)a6nZ@Rshu2>4W^dqLZ&THV&2z^v0%(vgdL-I4@gHt5C-
zflrOPjL{&sb@oF6)@0T#+6r%)bwzZ{^p5T!)j8bN<tKu9PgnC5WLk6|Bm%8fmv042
zZMwT(gLz*kjs|(4v%ChhcHQT+{d=ezU=8(0x)?3UW8Lg5c-W!qvlFg8(KURF$?Me3
z_rL@_)$s=b)}=F#p8(Nkx@HHs_*`di0lVG0cWBA@LU)ta+b?yW86fgXXVn{MuXQiz
zEaw~DhDXrv(UlZI#98kW1`l2I1N))ns{fl7rEdD0R%p5FKcVVF551`ZnA`QH{&2=q
zpS=}KFa0Jn)j50Xb6o-IqkoS;cj$LhBFtC+UKN;rdNt)a{q-t(neWuULlqnW`tg?`
zvP*x6A~k_}(*lU>)(@dr{T}^ZivRD`Z@2~XLHZu@aG(C?GLT^Xek!OA(MODcdZ@nT
zm>H88rZ02E2*dTi4*=P(Kdu8>g#N(}j44v@_YfLU`T_Jwf&=<)C14KfFCK^9A^qY!
zw4(K&-ho1l-gzQghxO(^&^n?|orG4bKH3RB#px@Tf*G%`J`At~{l65gI;y`a{CEH9
zxs`A@QSbc#GD&)Cs(VY;&sz$a<NA}<@FGR8ss&oAKJ6#;rRgi~!<iF$mpMR7*MC4c
zr<3|GHh`I-A4W$3PU%CofMn`zD8!ki_sECdY5nr?Aldqtf5Bdkeksx(W_hmuG3BN5
z^wu<OXY_W#uyj`67zwls`szfqF6!N=D*cjv(ij*l(0}kFTr1SaXF#t=e>?|n7wfa%
zL*HfnTDmN+==adduS8$E4kB0e&U>L=svky|dYOJ=Hw=~QYn{<&zNY_!q9PS~>o4GN
zrG7a@MXL1e(*bi`U-1~sYW+SsSa3t1>yN?Q)F*xpksAGnUxQhz-|`Zc>h$AZ!QXnl
z^Axli^l#FD-Kbyf3Y6RWBUD$>q`zi_7tMM`55_zCCmwL-u37&p6(8NxPbh_Gi~bH}
zl3Mi(2SLA0Z~h&v`})(zK_2KA{{+Q${X}{VKGZMZA@WGSk#_kV`lFOAexkof3&2kO
z%|{?l^$wpvuS-9R0<_Qcens&2xn4;>Ot-#>wkI$2=FMi%m-?|(%l}Gmrcmc=y%jB!
z-so3Vg4v@Fq-BG%L2L)p#ZXME2Uo+&dJs3mhPm*<-7qU3*dB)QR0+7<@az*9^fbJk
z2@x;D@3cYnHuV1xC_aW*A24?qhTp?n_!{<^_d>(Z5JLC8zk#O@2JAG<tin78817|2
zahG9DE0}?Xn@!NzZ5Z?(Jltb=*Z{KEFrJcnL54rxKxChxi$Z9@hLRjO6Jj_=xxG-s
z?5{z>3^r6M5^fli0Dt!zCVT-45r*(zsMIXd@QhOBQHCqDRXkv@pM=&y!ym(8{*b|c
zGFs7w7%C`?G0dPb9X1@0L-L3rn8O6e8m7{Rj^hl9kI{-Zd~+Ej!LX?VmW~=0{f&_w
zGfZS4iH5i3=u0xJr7JMmU>EY%zKT>%V?O^WJWeyje+<+UhB7K_N;jONDxQ-Dj{_hX
zh7S~Q<CNiRI)RaC7!im;Wf_*90NiOqV+2fP8`>%ElVdR3V@$b*Rhz)fGraJI;WLKN
zi-10Bm>h!nI%jC2c+q*ou)jer7}Vwy=)7oXT?dkHaE^z}B}4Fb47kAXRSfJF8kX&V
z7e$6888BaL*!?wHmknFCK;(*{@F*;m7`8<~@2Vlo2!&FEG91p78DjncX1PI2pToFj
zc-aH>3PT5lVJZ#VogrCecy|(Ag4Ydus2IB1(DoFdHw>MWBDra3`wXpHhM(vtQH^1Y
zHHKDem`c&qIzyNddi4e?`Yjs_Rzo1!Xy~Lo`fbB^REgbW;NOAyX2ZNbn1siMO{d^f
zhoO)H`A-ZflmqHCRQ*h~^-m2i=;_&IXdDOf%-}+c%;$!NGtlog)K{SO!mzLreJ>3u
zRMq*)ke391UmFI{t^URk5CODf4m}huOLUk*mu|8{L4OP)#bFmiU#de1ZFJKddS`%n
z!eM|HnCT9`VylP$nZRKQt-UfGzK8`k%i)jTA(QPeXfx1q96XkSnd|Vif__nlQhKkP
zarpZepq+K-?glyMaGtV8=N)=eMbia`KPY~h?=U%>eo2Q{N8wC?!*~TmiX4`VfI_i@
zcomYD9XKa2%~u?pK7dAv!$=B~Uv>D3q9mmbMJLc%=5UXqspSqCw79+IFg6;J6%L(e
z(5iHJB*E<}hfGR}Tz9w}4raAO-E`>PaIm=m6E_`7X<~0Vs8?YSH4ZcBU{I~Y30j)h
zIW+wMX1&=V-VRPRJ9zrQ(|Zm%bX2Ux!G=O{tqv~fFyH2oN@4x`4raQ$9yt6)ao2W-
zc3&twbZDFn$;S@SjzH^hXr!~OPaM)lf^<5p=>+qsL&|Z8bU9pk27jM9wDVv-clevm
zh;$<e)CzB2INVEs7cU)-`Jna6q2nS<ymt75iXh%Ntgr*K$Kl)2fN?hd_5j4iSY$w-
ztMRcbEV&tt-vZ6uxSL*_9>zJ3AhO+<`71CzjgQ8o&&#-+vU1+WBs+}7$GGMyEbK6r
znf<}_HTtGvpngUVT3`7ayMv&=(-=?*#Q@{kH2@7XwooPHZsQdC<i;N3r*DDmHBO-N
ztRQ3FE&O)-jJ>=e5^U5{bR@(mU4^Ak<Gp#n3^Rtz2Uxgq@EqvvHwIF$FT%KdIAzWw
zjd4ey5oPR0uki!M>vAX_G`^_-cC;}m67v;feDMRud)W96CFzbB^QK`+VvP|La*Q`B
zs6^nXaTGm0ju}I(ft_UBy9gxNIO9)<95)uHz;24Mk#3b#<9EqWNHd<kVu|}N-8hIM
zMkkFelr+vTUZFevlu_mZFEWjvECgtl(bW$go;FVT05I9cepDBkW4u83cCPW`QZVz3
zR}EmEF|MS1^jTy7$pAZNTonjM&l>~wfqB8WoIW9T(HKP6MZR$e79VE$CF3MoAQc#&
zQ>>-P*zf|R*m#?=YnP3uIk<MkxRC0wON`SfKz-HtIaP<18ow<E^Mx_yAkaJ=Jt!XU
z?YM`cnm&#{o6)z=aS4@YggQQ_(EEPJpD8{a<v8|Ts2_3+`~;HbSjV_HaN`_PuR=85
zv4nOs364?pwm9nehMxJy9EC68MWUmMUbRV%a~9CdI!5LI=D6c(TEC_^I@3|~RL5GH
z?li{*R8Drnao=EIo^*WwN9biZZvGt1vyLGRuy@YUNJTs)X2*zaK)dSr=?#dMI-Xw$
zyJe2gXem|h_|AMdbIoz%WDKps(M+-3O2=pPI;?VBb_Dv@9lxCqy=upEd2r^2<AZ9n
zZaVg%56Rqee9{kkHI6G9pjYe29RRb=aeXi7)jKZ#0zNf3nja;jv(fPmt&y7?<86T5
z>^M3LXl_oCO<=k^RSp8EhtrtVP~7e`aV<c@oqDKpY`;@T3|bLR9If6Xot&RSGRnzf
zI9dmsBK}L|I>pk~INIq9y+;l^;dlh*(5cJ-3&~FB&5tnN<4*0Ae@t<@w*|jbs#5`l
zAkv(Uoki<}lgAWzn(ov?L9kq>b(FEsb2{aWzB5kC96*Yk{>TMdu~X$tkjqZ9uR!FA
zQx+9RUv=`Ov|5?daVtocJB_4=X06lGo$#>ENs~#%JoQesOCZzWv~><F-FCV^2QW=e
zzbQdFonBA^y~}CFSV%r|`lkX@^4zIw1%97yr!;yzzjTVCYyFjz_%HfiJ6Tfo!W*Y?
z|CO|xMo`Sd#nf^ZlCGu|U&0GF(<E;|yPLk<Plq`?On=v4^xI7V^Wd<T={B9F_BJiK
z4&q}Pv;~9NVH*85{Ps1?uK<jn>5s2r$=?+630gZ%muVrl%ajxZ^+3~&RP^mOtzQAV
zdrV%X(A#Um1{u#OQ{Es*?lT>t09UXnVG$LxhMF`K!U!|H_!=7fO>+*QGs0B$5nv9R
ztp3~4nB1uNH_o(xE{J$jtr6s?X_6KLO*9Rq&2W-w06jvJO$D@gIBxP@0fQ-~J1StN
znj+~bkY*}RhleLj-eb_0ZVEmHVm@gKn-8=M(_g<}5>A=s*@K&9nsyRCoi~-y)B1wR
z_A>M@ntpSH`}wAi>DhhBq&p90fhmTri$c>m8JNYUjyXWNY%+wQ?~2KgjlN3Lw-@1P
zm1#y0pzBO0sAi+yluzZ<4QA8%QSiIbG~pH|>bA-KLl|r_wbequ*%U(6!govqR|Dp*
zsqiq&-!oaOq2FTa_Z66}rkamH+DrqhAbH<(ViUXwc)OyV!4&@V|7Q)X3@D-dc+l3}
z@Xd{T`4JlKoZ<+GhnWleZ*$BIrB|LOw`eP5yts&9DC2C_CA56F@$@6?;3lC;S`o%c
zw3<J`eG~yt(>X`l_MhawqMT3$H=Qn;Q=HR2v@*E~RGyW^?fDxbr@2xpKhNeizXn(i
z7e}A@%jL}V3o!gVuJSZA&Ts<<LFO!1<Av5aZhs8=&U3RVlUBr8Er07R#a(VUJ+0l@
zuQkxe=`X6O-Oe%}gXzh#=s1NJdz6BfHw&c_J0F&H6$9PDKHUVSFDs@K6Mn3b!lM4n
z-%Ovq+{wOEVN3zcnyQF)v3Ek?MIal4sFEU*wP#`2*H|1j+=}h|aw-hj!Dk{9uGqyl
zj|X-TU(g%=hVfHuQ~<}HPv;ci@6T6JHPh%-J0LTrDjLw^LQ{Y|a|6}A%uA_<d*+o*
zlv>z$g)YJ^ODTHq#r=5!W81+Q-$UypS4EfGSuU#g|9(^9Ye#gy;rsN1(H`EYfJ4r*
zm7z2O*>n}4cgg0^k>~>!fpm`MphX~MC=OX{{RMc@7MCf=R<8~!fyiC6`UIU8X;+7T
zjLxU(arqE^rT*X(wA}38>jQUv?1odl*)F>zir@v?d2d21(ys4fNFKIRQ>n)hyI>Q%
zh_$;-x#>8&W{QBv+fAf(Zi3yfKV#@e?II~=eavnt9VAS&i=b-eBs;SQeN#BiZtNn6
zX4%EKfSk44HUVe_b`vNLc-8L8574i++eaT{xncJ_4lp<EzB&)dTXua-FkfS5ngh~q
zw`mF_AKKMiMC*}VDFqcD+m(Bw)nPa77z{qKTlX#o(P`)SKFmI~3o!SBMweZO2hg6`
zwQYn<x81k<VE%>Of|ZbYY4;tKt-Z4Arl9p}yH1KWzp-n$4TT=Nh_`|5Y#(<L#Km5q
z5@%QYYaVEM+Sh#m6fgTa`YF8aLtLQeV}HB@C_C&w?7<JS%iixE6;lV=H_^9zcH29a
zfV;=OUo7nIwg0CUXwmj>$I;B%52yEgy#3@7C>*zMe+Khu_Dfb_gjx3gv_bNgz4;^b
z)!5&@2U2JMeK<(HeV?Tux9!jWj$t?1S31B@xBY__TsqF0MOq31`D#|u^4?DqR{;{D
znMYZSD2@N8@cW472L@)MCgTqDPiRzs!qREYw5jmvoaU+v{4LZ3>CsoJ*-Lrk>zYyC
zXw_-Hp%~*GO+gYw9%$O;z;37JJs&vpQZw}s&6D;vZW6QHTia|4OFr8E6fxPMo#O%+
zU+o4eHSyD~O@fBMb}zlYc4~i`hhYb3cV0$omv$zVSO#j>QLXT9?YG0=_8zVMb@c7k
z4x%(okTzl>!1ifp6+kaoJFNiBXzgn%REg1kn+pZ=VQrsc8mM+sJ?1i2tDty7oVM{6
zVB)n=beujx+hGspQEl&NkYm~kTDl}^o2lprWj+*tOx8wFDCxM?KwIw=?EosnO4S~E
z4udDOTXsP*T|2EBdMCA+c~HpEcG5=clv$g$9W+y`qBm=n_AA<~pVpqBfo5x+M`LI?
z+C8+T%+-!q3dKC_l|GO>qm9`G6R7Vg0P~!7;2`Lo*G{L}tgG6ra15zREB*uMTCL^3
zP-xbE)(alq*B+sYsV7?3xnRE3nj^jh_A6~+IYeJ;ZC#-FMth&?rhBx3KSR`6h@!7z
z_zIuV5lTPdNfbo<g$o}*WT)`YQGf;rK5wIMmw*#7_$h=|a&(W7vjfiT6^2teRgiFN
zF~~k4&H^M@cv=r~Ku9!GDbPW|HVVx{!tbwv7A<U@0A`GEuL3ZKg(t!A;)sxT53N|i
z?+qm51-2ip1fgFX>>d?D-p4#06XqR&`9z_L%7c=G5iO8R7JB~$a$Gn}k?2g}PZfrn
zB`m9hdXCU;pd?7H;A;RW6jpr;m?FXHD$HLN29AQ_72)=KXjKWCXBhT%VIVnkLr6OU
zyEg?Fx>K73Cq2-bg&11Y-4V1DxW6kby$_Llf?FVl)FQlcMypjAb`hja@TZr-eIc+)
zj{EO{aBUSd+J%F1Sb8Y<jD#1DgsuZ<Jr*7}z;1^yej8w(2+t@y{Zu$L0}5S&&KAGH
zGr@%lyq^mV--C1uJ@m|eAsE}>=u08%3M{=6YW{+UuZ3%8=;sygN5evo@IBVYW)wYm
zPKTn4IGw&t<to;l0;rqVyBmt`BA1OmKk=9YnEs;TB@}mx36vcU5S#u4TA;Xo9{uQ|
zp$o3<5#8Q~qkF}-*TRc~qAi8M4v9G=5-lz|gI0|A;65Y|i@yZ|(|kmnPep98ViLuP
z;>74{P>dHHkHGx|@n8V@j*3l3K#qwwO5jYQIO#TAOA^Z{x1KBx#Cs8y46`F4k}A3n
z256c%=MGvY#9Q>DO&6;o&^jrm(e^e&{DkyQiAH)iW}3w?ie{pQp$MI)#Z*Udv&BUb
z@FGXFrK*x#aX$T`d1C(w@bHZI7S+C<6+fU;PbFdz<twg=(SM+?Oxza>y>jt~eqdIL
ztLOs+RiYbB<pXhS1g5K9%<TvAQgo&8<15i@O*I>@#SiHK%^UH?ci{GjrSw{Gmi|)1
zQx_?8F5GvOhBd*in<UaJ)?G4ef<X`I8AS@WOCQZZpQkjeFTlK{b^U?jEe&>ux{ow3
z94%jI6)l7Oq+%JE{?dw>(Az0JHcta~fHZF)I(JEv&Hy`5x=0zy-BPd|%stZgl;Phi
zjiN<+khCxmt$k9tGeCo-zw)3SA|*`)GgSIvBe27y$y5RnE5!$c87IZlS-^N{>rZGU
zNX9MrMUF~$>D78ndiTG|{UoV99d?tYunvsrxbzL}NK>Rc1@IzOno7mGX;KK)ZAJ}g
zplYy`Au(IvOzMzclw|fAx_JgnTpxDF0wx-U;fOJ2boeWZM!XrmAR5fT5vuth!6U}e
z<0@o?7rk-9MnuI?F=yI{pjwzeKO$WRnF}M<PK8YIh{bfL-yOlIcqn${m&H~XDgLbL
zpoI8u0d+uMT|oJg-zzQP#UGQK@b|{4rBL1!;S2oDSy!Oy%sG7sSQpNTw#KfUJ`w^x
zoUAucc5rcKDm3)t?2ZCxFPAk67(ra?VvIF{>!3|UB==qyjhyr1&=<?qQP3}rn|mF4
z@mx0@u}a`R8UfH$ZY~`}Pvd@}OXD=xvk<LpuDv%%4)>xAdbykj6;Tv$5tODb<Pxt@
z5k?XB1%1D(n46xB&PpzF5YVc)D-^oC&bib3shZp84Q2zkl(IRET>5yB+uUzwpx(sw
zABGV&bDy~a^bQx;8*bm_me-^29`_ab+rq7kLEmHU%0pP_;69>T{|OiNh>D;(xr!v{
zKjjA6!_sSRGo=vTaPLmR4E1maV&H`{tEaSt3lpeL(UlFZ1hyNi`3{oqESth@9<2N{
zTH9G6?M*$IRVYNfSO(>byxBM^$@O8!>6yBNO&AYJUuMQD0pHeRYwp5ff3|Ee$WAtW
z7f1l>q$l1kc9atFfvl3247*vEJ<#?r{%v6IW#>7F1TldM2llaomFNp*6Mlq=5Y{~o
zj)t-jDs2yA*ZkpAI9p4{#rCt?6n=_eUW1@#KFszhAbN!D&H^`y1q5R-$*d+88pqj+
zhmc8Oqv>p8CL7WWW)_=60gcma*H~a@vxuKzH;2V+h5AJ{V*&c|*&%O8USeq!?<!y`
z)<M0H<xhocMa*?Q6pEQGMLchs*^awVyu~h1Ou2^brBhtBjGqL>2A0qQ#U|EkG&Gu7
zkT>-2FqdH%#a$+!M!zrX`V8K;uqE_@X=R_-qOXmWUq+uZU$hYlp8PT`MEv<+BP{IY
z6UKoV&S!MP>>=JfWeH3q@ZMCRdz61dLBC`CXu4(-`C8gkCh^nPVDgjsad{Z;Y5rOb
zOl0%+&tNczKh_Jb<?@p$z?R3q|6d4@|Jw%U&+!l6gTi_KONvrl;B8KTT;$JDJ}{r(
z{41a@@iWa;(7(pNMX$-5{7b5PXyiYlnur#@XbqT;_$B$!c*eh?h};|g<SZy`m%Zl$
z_dR9fdeG-38!`?pZ<&!!&ilwbXrI1A7SaGOd}WuvL@QX<_5}Wh$V%zC5h}a;04QOy
zQFAFw7%p=Tf!+PGzF$EmLMAMMVw9{GJt7Xs@+dKOQ1&HNLLZV1r^5bd*}{L(7b9y@
zVM-6nhEW+piY(6-{+^O8`3)pbHfA(@%9jldgZdSjA6>E)G9S9eZ^;Jq!0c^VS{Hpx
zpiTCK(gXKpeXl{|fvn{YTJ17#+I2mY^`_FbN3ySaVE3`C;&;Gw$UgoS2H(g|eg`jb
z6q#1J&hlE?^t;G+Qf;a$zIqSW+~n^Zf`Yr;v<#RY@_+*vy{G(_mFV-5r{aZ%^}jqZ
z5@<g1B~Bna<g@8%>MOs$6)=ACFDXdlFK1LGwoiV{86v^*7x`#~$R~yaCR83p{$dgC
zLsKd5wHai;Je$^sk@7({kc^T~SOt^=@{j+;01wKWDROa0{@q`2#vG0B2mmHVo<UjI
zM0pn-R!EY|==M*RD?UTtaXh$ymV)n7fTYT;|BJE86B7V)LVk=&wol4O496s7$jgSI
zbxNK@>84D%SP#2d@{x22oR<GgY2R%5{v}}M$cL?lqxojJdlw8|k~bzpqd*>337JCq
z7p@>h^7|CtFP0CZ#l>a$<|>F>k@E}j8<xm#d<6Ycd2AKX%H;WdV4__9O*Y)VCZ9kV
z&kFg4474icMRbg+O0Jv;f3M5Gpu9`9{LOMe-;tZ=Q2OPryoyq2_v904k=-Ky@FWJ)
zDi5Qid7J!gC9ogJznuX6cKHuGA^A}L<}gGa$umO1d@TQ~7?K_G74#v99(kW_U^*)z
z%y862F*6V9u8MGPK)We+u0fx>V%SKidnksQec_^~qRj|VFU7w5!1h+$9gUWcB97MK
zI~27a0Mu7u^E+C8iVvQ{{ZNI#028M8lNJu)icnfn?pN%m+b}|rPsx}_MLb2OqZE57
z;dwyu+7ligQVcr<=xD`d+MmTJ6u+Bc{;(oo8tfiX3><*YScT~x<~dH$cLx;X6+QIa
zIICDrNA1rkG?ddRR)prj{aS@(3z&6^1+*G@t+-7ur&x<mqX2f^V$@QAU9ec?59Te4
z!G&PfS?DMw+iKBB8-~Xg@21oK`?*C=D$u$u+$rqjZE1G}8a|eTDEGa`@@Oo~M_OK`
zt=w_Ts#lnV)0ShX{NcQ1p#<hF%bd$_^s%KF3{X$yL(1^%QD)Kt;h-{G1}~D8ZWK^I
zp`5CPNP+TKT7niTKN(8zza6Sl6}bMYL4N^er)nNu>jA2>8vzrjdeR>b?^ZRZpl`1#
ziY~n%)vTu&Z>Vb9W=Mvq{PYkBR~eci5~2Fz1NaoF+V2R1hg1cA@Hbi&r-xpQN=D0~
zSk){Q)Du)wmZ8s_sCrfk{o|?&UT`>775pPQ(^Lc2pfg={dk;*UR867!gACOzx~@*C
z-lAK)NLB3sa#_{;Dhys#<yxSxT;-b#6BVk7wCJo-?KQ)TYSr$^0K26+Ll<d->bo|G
zxLS>;swsD~)shQnZnui05WJVw$X_ts{#FbAf@pwM*HMr?R+olAKgeoZJEkPWDwAHu
z;Z{;REeG*Oe6<;W&+PRQuFg77Wqh-zHUsRZ?}y^wbKdm={@kt?(4F_q5d3@o7bqc+
zFDR#iiG^mXAedN`G6!ZCA9)3rmK0DbbLj#-{$BRcyHNYNgigyYZ=kK~%43uw+%R-K
zM!WIj5Ap9!)BS<4*~bn4-tzr;fd1o8i>+;e!|?Bay(#Z*j{Xb(cHz_%LUZM|(l71C
z2|7z!|8RZjEU-WKJ3an)auWul6~NVpfP`?>LjWGi^?V2PFz(~!7-<rBXg$0-$w^H>
z%jN#a#h~)JZhCH)a5DpFgHO}a+#i2OvahMQEs9m;0`CA@O;P%TEIJUj4zc2LGdzuD
ze~kk-jxB8gU?RI!4x34=D+8@$_S6D>Cs>~zFw@!jabTWgNv<FnEQpFkvsu;-^yRQ}
zsyxkQ{ax|<oM%7%0rMBwghZ%cWV0?ovWR_3`~70}h+?Lt?8U$IF@Z8RA_uOQv&pn*
zy2jR8L#CQ_jz;SSd&dv0o2-^9G3#0EE06~EDXlshSp@}MZnHlBt%BKa=V7;nS-%bJ
zR_3@9!+yvDa>49mhXSDRlx?6Ce-}%n3+5#Y>P`7aXMQ0)*`6p@d1D@*s#+g$=*6Em
zTogTHd$@0DcAQxZondrg&;P|pT-o$K@Y#(e9fvh{w*3%@2ivYh-*$GKYX3ahG1|R)
zvD38J_GVN5d&{yDl$Y7TwpIenm;GxV52Jp}fnJdQ?C3)n+{vyOAQQq89>LpCmX(UW
zFg7F;eMgu>Gc3iiV^>xG=cRbb3Et0|F$1!*H`C4gQ#Wmw=S-pErn!>{V_xc3xG?|g
z1|Tf(X$5CtZ_1P}T6l``UyIF~p|B*fA6!}*NNKBOUl#-P=ict%FK1_=u!2#jW#y;z
zboq4+Y5kEo4#w6g>2bHIFTEN!f7B0rcWwclU-00*+X>!wuI4)$6BjrJ1_L->`Ub!*
zF4PJR1#%l52`P-*P9@Lb+}V0e-+nGB7cN9{-mAep$gL+cG28()NG$jCF_;OQiPqkU
zTvI$Om2gSq!&R=H3NcE#*_UCdj5|P;&*j{(U(veGjTjB}8g2j;A2f1Cy8K%?j?rQI
zr`*VND8ArM+<?q$u4WL>dbkyz1KWkgzXO;^cE%gbbhZ%*j{m#6hS3A|6leJ%bTYZ+
zzrd|5?ze6jJI(z_$<1tT{s@p9ZaR-q<#LS9rRQ<$XpddMU7#dVA@`U00`!ZxVRUg6
zb5<1Ryv&Ux<`r(HGe`;dv*N$e9i^baZSGf!PBn1_U!&E`@hyO9=Pppd?jbjV=J+``
zm!9_B+(wFQxU$%j@WPGtn*<Se7DcB?{8;s75PvpnCf)x#neADK2D5j9KtkAz&oQ~7
zY;`%vA@(m-NJO(0v=xbA4G)2KnBAiLFo|jC@tDjQCCyH;)wkeGCQDC;r7Wg94fWG(
zA8j5kuxu&@zQ`7bKp~&4T?Vt4*k?hs|1V{!OMzX+yr@*Soc%KtBfQ26Xk$~u{wYFV
zEpt7HzB)FKuGD(=)hqNhu+QGd1huliX#>~Bw3NBO&t_0~=mC5514uiIqOI3Mwy77?
zAF+`aFhP%*7ga`eu!}+TZQCboH^taG*^y0f@hO`@^W4SKH)2fB7=Ig{K4;5TVrbp$
z%0WoJU}6zkFIftem%d^n76a`yn-hsXUp}-B3ZZ;0Ewc{r!K*NqSl(tjoH@=P-UD)h
z@1l~`YJM1nM9dHPf7gNQB3t?!K=;d@(2tiSD;^1F@?;O`G)jr=0iE-ym3gj%;uF~q
zYd~JgK1llCBjBohF{RIL$Rp$=CjW|-=k@qcGcokr^5S41-I43pL!?!Hp#(<T<$Bs}
zcF4c^@5K5u`J#Dn`h|Q`KPdLdJLM2{S3LRjEes5Qgx*wd@zaN`z?&<(j?Vd^mVj9(
z(YkuEe>!@9-SaC3yedqKzt_)p2Hb`nRGz$XivY|`vXRho=B82=iVOFM9!K8XFr>W9
zh{gO)5uHFT;Sb>N=C0&n9>Tb{>(L75G8dpPntPA3ATiuLE0{gTHB+28k(=2Ml1bdM
zYv?=4&3XuDGPoFeQ=Z~x?}mCNx8gO_v$&WJD4gcT`M{TKE;kJ*Ib7x@h?sM^8?R}q
zxfka_&TxseEI7-Zbp$!bX=eiaJU4y}^e=GJ=Aw0xYobVAK6hXxL@se0)xs2T>&Ac-
za+lu%DdL7ud0sL1BV9z7xg^TwUg6?5f?2|u&Oq-f=UokEshK-ugJu~QQweWwaLadL
z>TYrizsG#t;_5_Ls^QMBrr(t-Y=jqeT+1Pd+~rm{0s9`8O`FvgZpkjFw{o9Tbg+&4
zb2YH<bEyJQ9&mkmwA#5}X*ZwDRFv>dXLj@)$zbNmRM3#gYP%qMnl0P~(L5$j$IPB%
z%NJoV7umbDG(vWx2#Uq5Hw8#aSQafe%UR4aDBNKFt`ND+_PN0|Xa3Q0CAjz_R^`EF
zIJ><LWIw|*0!vhuNkEZoZw`dbQEb{5Fnxd}Z-FBR+0*UNJH-0u!@X#h{03HHm>=GD
zc<OvO3096U;|eIovWgNYV9{cPLOlD4s(2FEYXu~avd<_;ag41@fMg;|ZbmDKU9^Fr
zWHyOPnU1qH>(Q5DX0dPJ+e!ArY&7%OS7CrT!yGB(Tfh=Fqpy%%pu_n^EV%|E#ccX`
z%y9*4SOxQytOJWUc@-->hSqg<{2cV^*@STzXagHc+wDd+mx4LB*};t<P3+zlC^Rz@
zedXv5GoMA738FcCA)LC$+GoMV7RJ%<*UF~JA=<_~l|Z}C#?nLj0sCtRB-`13ItBKS
zZ8!+>jAhdD_BrF?;BPl;ql@STJ4ex!muz(hn6H@MIY_={VV{G%VJ$n+x1ImpY{Yzd
z^2zkj#EOX?UIF|_iWLX*77}Da__eiY9pLRLwsVj#TnvSHex(BpCh(ul#VAsFAIiL>
z@nN?id7AI#36jk_Q&{i<pHYdiT;!{$csQT8-3!U9yptZJl;69NqVQ$>=U3oVIbXF1
zqStu$a&%VkDRd~SlK&$BcB^<#`jEtR{uKQ_)qK@I5V^s}PlPi!d7}}`TYOnFNDcqB
z2S_bHf|hG_d>?wL*Ynp;0<3`#TnlCsf0DAA&HR)p6o0wHH&7Y-U49&Gdt3Q<S|GLY
zSDvGFpYLA`(Fc51H1yl~>-Rt&^Pw|AI(Wwgz<$ElP-5XVf7cbmc9ywQg{+ILlZpUc
zWk*QFO?I5pG48Spy&&l!>pqHcdddD$(euw+)_)47##iQX2V?S+sUqRNzw8UT0(Z*H
z>tQKCHs>$&#mNSK3P)3A*{7gzTDFwJ3+H9IR0viq8<PZPo9wGi^!v&W-hmfhice@}
zd=<G5pzg0|&4Ngf;<p+=hbn$e0@EC(sCGj$T=5x&CHE^P#e+mBez*hBC`FAu96qS%
zp;%V5BH9X|hZTc*z>HG_yV8}QNV5TGg2Ik=Wk(ek>Y#T_vHKi`ouufbO-Higty>_+
z6}$iW-^yBOT?FBu+)(Lfmd}Y(z~Wpxitx^xG#lQ}_n|}63%VviXyGNQ0bkMc5C|(f
z>CyAco8R&8Usa8eS!?+b<kt<Rf{gWZXr-{BlfG)TaUE5xZ}Os%{qw_X$h&iSbTxZ$
zd9(!Z<Mzy>8R3SQm4MmF{Y#S`z-2VR`&|gR12u&6rT1tkr>FgO7*}u+B%FKMNYlg(
zxC`iHZp&#{JIO`304<x#qZRZyu9c3C7jUKl5Gmmv^~W?-aAm3R@g}$QOSBrfx<)wD
z#%*Y#^;Z}7L=I4ARz&NWU5x(`Xa`uJ=l?G_nQjClfGhbIxVyNPLC_81qNrdnlv^+g
zE{AdBJ_HHpEIxtFXznn5UnzzgL9d@<-1Pu>p2&3_hC&i&qV-@h_v0e;WpL(UbW;2j
zXQBeHOm1u=xaT<IZ!mbCyV8cy6?1L#(RY~>X;)IoDJalZ#V!35Xm#A9c(m%dQ>$U3
zflElj02;YD-vA|ny-Nk1N7=)>bV;zoV=?kXRz?r@B=$D#OOn}9^I*{9Y&bo(Q&<d^
za(K`#pk;j>JJJ^hBl$l+2Z`bzQatAX|LJ9zILMbU*geFb8-$6A=EFZnUku+$6*-6b
zo9n<l!q5E+BC-6RG$nETo^5a@p10`(*LKP-y^Fp8*|hVN=-VYbMDN)^S@9YSbhm7Z
z5A^rQjwQmUy|U5tNDh)UXQH)Frj>yN%Y+Dsgvd5g-F&F5`Fq$6lNHh`!$Xlfg+{MP
zTm!p_ip>&QsfvfRLQhvX(h<)Lh3g9p;<Vz(aoYdpC_HJ4l&4UygXmdB1sx*jQe^Fh
zsISHLLok2TqDTTW-{QS=v<fYZ>)}O(#nMmzw*qWo#X3koU>3*W*JJiACCi^OEuD5l
z@)L0;JmcT4;NcPe2sL!dV#3d{m=W_gn?*FH9=HtK->#tQ$nU&YLVH>VZTP-V`3w9X
z_Uqv9^zUP!Ja5J~0G)rV6TJ(rQ;u)p`_1_GqS`3%7jLCAWlR447Fw(N4935I`_2IC
z>w;#%|MhkIA+z;IT7zz@rW$e7zm*H<-_A+&dh+DTX)));jiv3DHy2FFoTJ?OOemyr
zQ?enF$>mZCERVbX1^O;>kM@CC%(*E+%DA&MKi9cF<KS;C_fIui&78LdTKBmFqcPB@
zoZmU<z2;o4(dWj@P84ACW{Vd5Z^<GwuY~WD0_-spUm6l1yWu58RGx9}^qrLFTzY@N
zyySX)2GCbr8&wDOaO?KMCujEOWH8;>1q~$K+2iv-@?;5HV9ATky8)5iY~)b@?_nzx
zXdPpN%}dbCW}S`yTWgoFaTId9&T^^#xta~F1L6&~$_n#wlU<w%ty?T=DEjWOZ$?4#
zE}K0NtyX4z8Gf~~kLlKJXX&(ge#mNH!i8?;`3*+!f+cvuSs%XdGZ25iBOTD@KtAnH
z3~~=2=nBQXd@#oKe`_}fT5Ubyx@qIk$z7yHFXE0{VY7?t9RS>CTnNQzo^#_r2Gfo0
zUHsp$?Ka>C^=0>m1J;ktr)BP57Lf(@AodaMoc6KP*TIZrpKYi8UljY~cQg;MZ8T8_
z*`9k4jb~fvNKXQ58U~G{>`*X#PGe7=!_o=%5v_!?*`M^z$YK4S!O}%G=P6L~k!-^p
zl`xJnLs!`j%Fx_kE9u31lj$n~c8jf}*n17TiLZ~CvA2|B&{@YO{s6^#)=3qZ4Qy5!
z%r~-XsyM&RzF3Z-b+Ft8F#m+j$OY+SKW(KcVP6JAuZuZRuJ1Y9{Qr8p9-k(zINs~E
z&jP)1Ld47oLjeJ?TwAfAlSBrcAkZpM>yO3rdOaCh+DhrzCJc=~aGA1cVBcg45`Qch
ztY$Ip<}c8>k+B4wnq`SY7e$S8YFsw9po8uE$o>V_=I--8@B8y!?s|9c-RsdmiF&3j
zqLWacYn}9Lv6b~N#ALRyhmugGi(O3n*Lv6;^bxk^KDI9hg+H=S>7=Ef+5CH`^O%jI
z_jn`h>&s9!#!mhgRk!OdcVaT28(D--dvxu^$a;0-^uW2I^WDR=hjpGV)ci}=%%igp
z^`)m!vt7S;7}-Akg58+YL45~(2DuyGk%yK0n~6euO*+ZjwA=Xr@zB2eF0yG9oAf9N
z(*dy_a)5T1A0w@_^W->j9Yw>>iE<s;7vz>3vrx%a2@Ot@^*b?(vt-&-G&o24GcdJY
zviB|qyg=IM%;AefZ$$G;L_-hzuSxS69u2=C3!PXyKswH##UL3k#=I{R%W6#K3Q2B6
z`|G5A-+#Y$i=TapEnb{UZ_P_K)3fZ7SUMxG^r91M%9ekCIh21%4`9a~9Ng7A;~$}P
z>5&1nT6Q{u`Bs#SVSvgFBXs|(D$T^8E_W6>TAsNb({lG;!}5ynwxa6FRo|nFRf)&3
zl~(txL)UNax`)y=X>=@Flyw+p?a(h+BZcX$i>K)w)RYxEzstK}7(FOBVuF`2E9iAV
zwYv+;Z;jA_=$gq<QJQu7^~-XQY>3{2VqYuWmue60K^K0p4Qm1k^!c#hp*z@08#n)i
zsnp$misjJBbgXYEabkJX2|DL!3)5ME+p&}Bo`*gzFk0*t(VWK>t5FH8eaJ-ego0qu
zS0hXHH35G}sH`fVYb^|Wl#(KQwiFBsg#mxP;;#=0cG*`G3@Jj;7p|^BO<4FVV^6M?
z<Uq)lBU-ZQ*J`%THP5%qwb-mSp*|4sh2YgEOwytnzw8Tp70nBd)%u8;`l7c7V<bS+
zV<zhV2&Arg!Z5>dO5_$mi^UiV5gc-Z6S?|S==_~TL;qFn47kR}B!It^&49hn^>OOx
zRjv3gbPpM3s-Kjy*&zre#$>cGeJn0IT=2@YkK9Rb8NE-`(fgB5j7+JhDiqzWstURi
zmj*(~8D>{z%fOI99T<w5)CLW4Tr7OtZO|o52(4CErpCUaszfX+ao9ym9_(2X6|b@z
zqpK^RDTT{dBbTE4SE~CGV;uH31XoC@3kkAR=L>{{qJSK(o!Ff!+*QRwC@9H_Sg%O6
zLScc!R4CPX#qxkR>{G<bz`FVdsZJ4!6i>Jsq!jHm=!nzt@X=|*D}Zl#GN|+9nAShz
ziYx8n@`5s#Jvq-j@o}kNtu&q;P|u`r&tHSjPEO*X>r%7<rZgIpXo&;ZVT=bpP9Lor
z*K%9lGt9SGO%|Kk4DB~KxBBn~S7b=G$R5cid2N!}oSSE{O6DAEZk}wF=gAh2)n?0W
zaSU^~yrepYV-prJI#5#h24)-FOyQl(E-<Ac<UkVzFAP%fL1G&3)E*uOe;V)54vj-E
zB3g2@cqe=K9}dJ>d^z$6a<m;o(4J$!k&fDTS?EMW>Em>i&Vl@l38mc#+GA7URt5^E
zgDI2Jqwszv(o`6v^zZ{nnvJv!YG+fA522URM&PoLKGMLNETlycq4XFF<CJ=#d=3Uk
zg$@cBm4XlQO{nvC478e1XFuFTib7NNgs_Riei%g1{xJoT1k~9EwF1^ohw~JSz?u0h
x?L`6$%=}FK%fB(22OydG6o!HAW<H&<Lxe&j{6N76V+c60j@KN4+c&uQe*uv|Ksx{c

delta 126351
zcmXtg2V7J~_cnLg-P^YJ)!1WivBlV8Z;2&p)I_7P#1f;%mc%5Q1w>H+6%YXh6={Nq
zN)ZKY6h*L5Eua(;5D*l>is1Jg-v5`MxwGfYd7g7-_U_!7Gjn-VIwtAKm;)Ud|8t$5
zF+X$7f?YdP8#}u(w;8+t{~yE1y?Tmv48sMQc{@fT`*w>x3O3*jXU9lo&hM#U2M&<f
zF`TSZEF_Lyk;~fIOJ%>V-$Hec_N0_1c&(QF(5~$anVo$*dzR?!y(ChZq0<j?JNvdW
znW@3o>#@Yz;Y9=F&b&P@$b`;TdpmoDD3c$T@OJi`LT0+`WwamIX6j;lJE{F>O)HJ`
ze`F^Zt*p&4uch`K6b=VOREIGJSqFbFH~aO>Dz7H{p-h(7An6yjRf`$B|3RcuJDDB+
zSw6~eZBX&JE+~-Wnp45x+C7O3mj5Whb>?dU*Oed0{+}wc@oS=5r#pn5_czsky_EE`
zPH?zhOB8Xvl|a|}6?A<NK=xnSexu^rQ&Ro2pFV#viU9BP?Qv}iA${mhqMOl)rO)^u
zj)zn2lds6V+eZp0I*G1>Mv{GE5HXC3Ce$tqS&phB&9^J)^WX^jY#vWo#$+Q{{UU<(
zaVPhWb1CY@jpW9bPo}q9$TVpUX-;k-%f^w^AN#IS54Cq8hOPI>GWaIhEFDgoA4k*Y
z&ojv7hV^9c^^Ev~dQxqvKYjM@E488cX&D(w{i$Nkm*jr#M56P5O^!?dp?3eigRZt(
z(#-5gmcMTyo8Pl2h>~=wEsG<b8$C&L={eO79Z#R1Z={|Wa)w-{JtF?p7ScEV%-h*y
zcG;cC)LBK>S%=BAQ)@e>Pbazs{iq!UGpGfAHwor^ob)+W6iR*;*&A1ozGW|k^-CJ*
zv&+b4T?gu|9+T<n_>44BztU%$hS;2M!ro@rXrhS1s>sc}BSf(xlZ;yY$tbk7C-QKE
zqr-Q%YF1NQ!*-J9n`pB13?_zdGbo73r%BT=j>4*}BF(Ec)b81b>GP!i#PIAAh1f2T
z7;Ni8$?@EtBwXl4MD4iNo@njf%=Pqn_8hwY^MWkTwCcZZ4fKea=#DDL*`YKFy>AA6
z4$h<yx3@N9<Oi}@KcCz$Q<0a91mekeCChoXGgMukM-CWYimUxyy7s<6q5RtVLrQ)_
zpP#fR%UKWUbFCNIF#E_&poScu^dq`%tEskUKVp+cQEgBJwf@maa#{bB+@Eay`ud4v
zqn%|VqVD@h2v|f{ul8ir;SgQR6m<RZ4B13ppxQlM>9b@Nk%qV4wgF1AF)bm-fi4t8
zuSMjnaWiQQ?Fm(+BF%b%YHPL<cHsp2n#R9qz5hE@kPwcc6Sq$#(GBfEpPO3m(xc0W
zs9O%{ttDi+sGP1Pt&Y`|MC$i1X{rmzP22!#_pOhl7t#r}x`=wNZa3A+KPTp8NyHhV
zw4?j~Ylgt*-Kb@|)2TuzB=EnjgU_GO>2sl+D7?2)S1)xZ2f6oJzi*7l_<i3dY&%b~
zJiCxS_j^ILJA=q&`(bpAcO)-g|3UhXUC7HnFK|!T?25l5)eIe7KP(_Ry#rmZ>?go1
zHR<CL$$e?-cNsp2-22r~J3jnNw^hA~G@Iv<X7XNg@9a&Q%wwck>Pqf6+$EQ;95MHZ
zq1xUus<maOkb}w@be%Mjj5aMKqj^`zWlk{}#qFW%z+$34$&*b-UvkVT=rgaNKnGqU
zO?e)D4mw5H=^R~s-;jHKCS8T?RO|FB_0z&M`Yf?squXKmbTVBuo8ofaNu-b3kWo%5
z8U6kr*%URBzW8ej?x!_Wdo+NqLvB!TzMn|{Z#FSlo|1jwWpe4$nNTPHq~_^wl0KyM
z4v1Be$7kDZ<X~<GG8)v0uF}y&H)ayGb;$PwyT6?D-}WN#`3*!m?Hkhkw~($sz9gby
zhv>6)6QQcUC(F{Sg#BeGh4|Au`uy_%^40TS3Ust5+4o++)A+x-4Y~Y!Gj*W;KcX8Q
zNkl%wiRekI=JVDcOoy9P`*je3HJb?K_!*JzIYkb#htPGkf@~Ir(zSdtT^&x5<%A)`
zW_(2M1N3A$d8VB1f6qFqIQlnT#|<OLIp0w$S2xk;X+Key{{Ea`O|9c&bQysM`4Q=o
zND5_sB-#HPLv7u3k!putAjhQ#NU#4$JYpH~-}ykO0Yiy%#B$i%?0(uvfUqA4Q1>+f
zemzTo503PCZZ%!|wvGhjmQoO^8$^`y1EHoZBO<1SNP8?I)SKT(v&W54uP{+VE2om)
zmOxjHmGq^pPnPiQ#A6%uW$R6pKv%oH<RB}KD!!XWpC|oJ?MrkZ@aS!%zqptvvX>L}
z>eg`$k3BoN-7OtyYKPM2Mx_+jfVCX1*V7qXlS3)2wEgz@Jo1!)>)$FCSGDasYWLq>
z)Pm0Y39xtoIariOj#swc2X87Q(97@B{jocjf=F*9@cvpN^=chx7gV<Pgp#h}Ct@3G
zBxW5?mclA(%q9bIc6mqqzvY0@Zu4Us0m7=u!Qvrg`uC3%<Kbx(^$*=B(zV0MbmRf*
zp~y-Mp?2-QB%2rhboKn1zKG%r<iMeI#`ia-%$UYu5R=<ITub`$0faqhpz91wYUFlf
zpHL`@38D>xHztj8yP9vvrRx!bxnq2m+YQN~u*8AXVqNQfzy=fb9}B2uKeyiVsqWP6
zZ-Patu#;K8TZUfh_Ky^wd;R(=`eA&|-}wA}=c8!o-1+sWowtJ;J>PB@kU!W~&q4e@
z#+ne@f_`)>E}v!tY}M!Vkl8SWzTv-wX6S7zt<daXwvUB(Hzp(%#UbV=ns4|p^PeL~
zUuN4?NPbMy1{8;x_)5TzFnzv<(*P!@8eWew?+2pg$C%&~fFEamw2g-2K<3{(n4VyC
zOAu=i^MRff!AuzoWe78y1$QXpVnY$em}m}hl9}=i*ut4E{lFc;yc!L_DJJ<(L>|eE
zDF^py<~ohqQOwVY;5@^0PJr?(Q{5Go=a^`E07f%^@3H|O!;BPA8O!u>2X`E^p%i}4
zGe#|x@yrMsp)W9d-N1H{Ss4l`f!S~s?h~2qfq*A5Nnuc4V*1ngdYReh4Hs9KK_9?!
zl^H<;(KY69C@hnioBjwUh3Rt|MK+TmFc|-Gm?yZOWVy__AJN%)%sWqT=QCU)5cimZ
z1Vs9f`7jsU1x$VlfQ3vWjcbpXcD+%QGM6jiu#EXm4VH4|gbM(bOlNwSJYz<Df&P8Y
zoIe3vEpy>5lrNb6RUmuGynDl8{Htef{sQeQX5t$Z4UA6_{5CRo;?dsM%*U}%zG3>z
z0^%)my#~@d=5-eY`hoF%0f$Y@*#<Q9BU2cUx=&0TeZP*98k$BqNv3)rLRZO`9|ZWv
zziw6<L<W0I0%Uy;47oPh?|+?xrw!a>xZOB-4L)z`H^%ON=AHQ-Fz>%(EgJZR!Uxv@
zBQe6r22N`SXM<kSy?dPLhLuh$yR@bQS}X5F({9$gEeN?U!=T|e%dmna|D8T8KzKb~
zVN8_oV7~e&LH|253o*vacQflRqFH;Gt?e)j?PX@DVDHLAbi|MIDD#FUu*aChM=*KI
zTo{9}ni<#2AloS!@G~s;N|uaA?B0?-G#T=fOg;?hn52(8I^c{XVL5PDB&VH#%anw?
z!WxyrQE#!WMMWFUT3B^jKMQpIjV`Ddg_W|MY)(Gb(Xw^L>v45sq8Wq`%Di6=+a%`B
zpJ?PA#{Z0HCvRi|5B^^l2<h`ds2R5wE$ZDX8_n$Vt{Ls=%WT77(y!a!oSmdUt;FSD
z{Ph)DW*eX>#ke!@lnnhe$h#0h4{qy+&K>ge_lV=mn#+h|==5-Wn_szI!gbh7nwbo*
zqv^}|Q;w+pX0kT|o1NtV`$Zm|VY7PSSnzC|*bTK?7wMpPWcKex<90KW-@)z0BsGA<
zhnc|QNrB&egFTAV%yh48y}{NRZvxXAa3a$haT3!S@+F4ClqWN-p{FnudTT!l7ids7
z-p|F=+L@fUogV}bo#w?Nw65pTc3Jnq?a*<3=Y5as0GTI%gW6#Pmkm4fE1Zwoa|@c$
z)|D8MWfQv7T{3kHEsAC=wFBLpjoa=2=gK@X6O`@z`#|hsp@F@p;ZIzLoazndqq*zQ
zPyLM6nsZF_Gjm`PXzuLDv^fACCuZbNkbIe~ufgrd9C1cuhZ!$=j-O!mZ3Trbh*|Oy
zz+lEcA5laxUlQ;PGq?_Z&oZ+_*j!*To&bN5NjM411m?eS@S4iF{Ru!Cv+^7)uQQ8-
z@D=4TDfH9LXC7z4?>(lj7vL34lN$h)j6iL9#=PfY`Gy&r4ES3c6Vnk6-!YGAZn#Ur
zeFjq($-(z<xLcyqKzT@V+Kj?S((C~?U&%Lj5q_v-V*uE~B))4<cT%!vE^y~1+CO0u
zFG<;qC@x6SXjyk%a+-1(HzZ5nqwcQcLlcVolE{uwK9<;e(RWrPIYam-lG#z{+zQE`
zjgV?2-zm{wZzSm(&=?2%MQg#f(>{&^z|G#>8J6z$?eNr;`P#RA08&5u{heSLY~S}U
zSccdin}Xt;y&)BzqV4;v2In>VYf}JEw%>+{I^9e*S;wQ}0qU}%2J+_<`=H%j5B(u;
zt(1-P#2iL8{#SSSnsDSIK2P>4!F5%w-T&Q-ZMMuo`+Htk4Awq-@^J0n)D_o(O`Sk7
zq$?#azFLpRylg}Q4IE#0Ekk#YT{#u;P8hX@X2jD1X$JHCzW;FjX%sESeo;1{dhPKs
zxc)x09u%7n<e?FX@?PJeNlEf0&Tx83{>?Y2N|h_AWf}5S4C->^e>%b0L%BZ-qFd~k
zg|KX3?~H_rBmY?on(D#d9}UY`)xacbf1>L526*<+xXp&mL5(i<|L*-L=6W?+Qpki*
zA3tW=A_XWbVys?>q?CE50sj-G$6<WaWz3Zz6bB{Q$?)ba5l@29M>3!-2z@2m3n&gt
zI=3LMBa*QlKo%g`^cuxc$uQd`&>WY{nhP;dQgaceL6Yw#py9!iovsKoPNI)Oab6Nj
z3+imiFb_nLBl(mH7kQG?wDQcC=<<QPFWEwC^aql!MnG90DWsKaq2vYKppPXV2SHgR
z>3t8DC6aTLqbilmuC+ldlQ^sd=~IcS0G=u&Ghd@Im6ESUL0Kh9_!Yov$?zi3JeTwz
z2tci*<~X<=>`S(z&e7hv0L2dbGt@!O_F>;6`d#*MwFt(=zDoc+owN@XpbWQ<Uj=xM
zy<aS(Tzd~Wi|;?*e#j#@yk}n!0qq0(<+NgaXy0!Mf+@5g`Z<b6_9K5nQDk4S0{CM4
z8<{Ac*heiuCzRQL9tNr0KDGyN74{=8g6x@n;~hv<_WkKWTVp?L9jKq%-y`>R_O)J+
zUf5T?r6+Q|eUKJ3uk1(lf@!0@mX?06?Kkd&^w$1tBbxTkK7bwrAM6FnIW*bVQ+u23
z?~AZ(u@9%mnWMBS9_@9KPG1Y<PN`cX0K24nX$rerdM^jvwMY8R8Z^RHIw2JP+@uxw
zmC0=Tq)|;^+b_L*4?quTq7O_xr8ED8`-4)G0;b;5F(XmuBVG0d3Sa3P${`$)9*TmA
zzf|W6>8P~NJw$O#x}Mq+C>>CMx)V|t+{>~Msp$Zs2$fEWL-Z%5gEt|xaOtU?0GzT(
zeTM@PDgAQ@#3<<x?ZI|NTIPl*&PffU0gRT8r)6ZUG&~EpK%7*c4ZsCy-4X<IQJUTx
zY>86$NWhb%5$#}dS?Wk(Uy)YOdhwc6`Yq~`rK?i`NR|4?5k;DG;pZrBNNxOGXw#+b
zufa4!+Mq|=nbJ6W6t|_pBVcn!x(wNNS(bG6*PzLkHhLn$Txr%_nB++(WFfSB(%-%U
z%YEra9RLrdr#w*<NY_x(`H{4u7{z00(GIW_OP78?%SxnSv}P=mCfm|M^HlosKNJ<x
zhTgELl=?q_iz+GqIh57XL-{CbrB(ENtdmy%jxKpA?X3V!y;Sr-*bUO)_b3{r?H{A=
zjdYnS0B@y*zk}?()O`#rKS)pC0_R8R%$4Y_X6c}#FmaG|dQQ`PN7<xG0C&g+%m<CL
ztZ#e7woCT!H1ws5?6LuV_aJ!!;9l7UEoj_iesWm4%RbJBi~TakdvI|;_SanCJY~Zt
zL+K^^G9D&}WEUsFgOBV$F&z5IcG3L$u&meDp!S!gcHr>)3y^K_0REWl;5Bscahca(
z*qo3J!LmvgBzs3493uO45QtFOyC_KEvUZc;DMFS^OUy{w#S^eREn9OD5uTAbMWQWd
zWee%Y5hL4N4(eE0S9(~Umvz4jmUtOcfCw+jCL@z;lO@OkXTooi?AaaIT#_CA6Zk8#
z0p7r0mGz<7)_qyI7o-O=1+72|We%g@_mS-OD+E&{`|TUl70Y~2L0Kvb2?6|xtaJoC
zJ(YcFhwdtuxlxX&QZ|O3xzA)jq#{rUdD|ouHb?ob;n41o|FRN6Im?gG5`C9EVJHwT
za(8-s?2)Hlho`;rkJG^IE?+{au6^>0lx*^l|M)AEp7KAF;mKP*R0_Z$d5>)f)K@+&
zAN}Mf|KS=;j>y9)ALlRs<q~jN@-rhKW!vP+c`(hB>uHLUFJC$fLEV=R909}w`H~%w
z3gp8mhg>M1(Fc}~u_FbkNG^PZcuVAq?ID%QcTf_iOdg^E_fz>~N<dV|{~Qg@O1bk=
zNL6x86e6sad;bR9bGdRZENkU9@g_XIly|WMcfEW^6lfadU2g*TT0SWXrtjqKenAxP
z<+(Me`zW8a0xfKo=M4w`lf20nCJt=O3%GD%H)f!22Rj@I3t1F<n3QMOy$$eij{SBt
zJVdh{y+9VrHl9QO#<6j>?jVh4JLN&Vz$VM#H-RnQ2%1E8SUV^$u{{zYU1phCsJqIp
zpv{kK?BtbDrm*Ygz$BH;JPqY_c5g0}H`vLPoV>|u0^v7<RrsRr7Q2<wL$_I$@-27S
zOv=+|v6n;X`Ip1`jD?uX=FyFq&$<joagUu%)BOkRh$=`A*?I=OSID-lNBED}KWJuG
z#L8pQ`eOFQe1ulYCXR*QC+wsuI4oyR?0{6kMumf=ihY$uozMPG`)Rf8u&GeivC&HU
z{nfK;E+dLp?EV2LUbB9b`gz0tJsvji*=LSGd|=yB+O?S-&OvHnr+kel9JpaapmgL!
zO2qHr@+uLiGiN=CV0Lj$2`F5+D_sHD!*$6-pnJJw2XMM^-6&(>&ZQ-Z`2FqYR_uo9
z0gn9#cu(%cX&}6~m@6o}xn1!H<`7pMha#Cv8;NG8a7kaIxXxAm4&@E*A*E+CIEGS(
zncViP@N}E2st4yCu9qARv$$omq0HveCZd74+$dTF=5etH!Ls5$cYYUu54h?VFfHJ2
zE{3*{yRi@Mi?}04se`$Gy&yf|ZXE_`8D~$w`*MzZg1QRM-~{+HPBRAFRh&JIfi+x8
z8QSukiwHr4b=*#`FFF})>q;Rsa&feW@R}=_4EuN7^L^CI+`u(((8T?C9@0lHxd+gn
zxV^ujaNzIHf~6Dx?R7{y_<!g&+{tgE&fdju%0RK37mp(7J$%&faPG=C)WU-sUtEH~
z_VH6Z0N>9Kvn_<F2Y-DRL{EORA85S!5F3<-_`%8W>&uU&Ou8Rmt;W~m&&$t)Er1{7
z2jy{oI!zA(`Qh1+g7`-?z6A3tauIeY-;qYJFy5Ea58?cH@*BZ->w+jE`CT+AJIy=D
zDfe@RpY;UVvwZtdL=nT+4MP;M{D2?8eVz}kL=n$#UxCKl<C{Z3^N{~B9VP|*mdk)Y
z;`fE4c+4-K4Zp>FSuX@y!WUx6Ei2=l`U3Zq??rRF3V!#Wz*X`Y)4^HA_rFEChiZQL
zC}?Z>t$krr$G<%dsh;12)T!(hzc3Z}MqWeP60iA7w7_`Fuc<=ujt`uOrZw?jlKYSR
z^m%AR3x6XHQGDW~DB<lWRJel7N%;B}sGWu3D%9;18Y#=~B6Lim+|O>I;uwH?g$@s4
z>MDHo3O4S-r){v=Ck&+hvID{`n$39#cC=OOB}|+G?t?<WT;L7~Uut0DBYbrjfM}u1
z3@BrS@iaWe35U|qUFU^8w8*(2TwaYRE(+)A7m_GUw?myRNyyAX<z-<zC7!Pc{b;^=
zP3Y(iPsxJM3P`C!p$dpJ!EY=qZwS39y`C-zwTLN0nDh%sGllMRAl(rTq=59U@O~Ts
zIf9uS<_bBq*2@<@(tgK1p{Oq$JrJsl_zoW0gg<_Oi$dW&WjP-S(kHMf7Ou60R3fB0
zp%qVrUY&t26S#5!%Z1c2kSYXi1&U|Fi^Wh@2@*%J)Cjwyp?oeVDeGA$l+zx`3*qAo
zkkt!O!KiyBoTX=Xqi~=Gj$RA4P18`m6Yjd8crOg^4~I>Hz6PWpg&i~_Xc2M?f%qi+
zs)N!|97&syPU18z!apopX*qI4Y@s_LK$QFnlcQqKGz4>8Trvz%1d7tra33U2qbX&u
zcz`yNLPcJJB21iay8xSTF~1|k2yrE?3nIn&v{X7R=HG;;Gomle2+oRmw2X}wH}dcl
zBid*Y7$=S&3X}8Vluqz_L1bdk-ix9~A-<+Wv3m}RByrslD6fbw`oQw4n0FddvN)YK
zDpEw=%Lehf_%0G%b3<$*)0^VI)8Q~fRAMDAyCvTH8PaX>x5JR`iq$EQvP6k9+~<g?
zH6YCuf1>X`U;Nh{@O$Exd#HOL{z}vj#aV5DD-_TEf{uM8R@I?pMIzG=CdHyMnsTqD
zVpsvfe<IozfcvR<&kwPci{mn2Qz^>n_If6oXltWdJV{%sHKIBkQnTn13bvh!Im=Oa
zD%i>BLodas-H7R+V#}9s@2y~pQ5;f?tB2A@@yQK^uVP+00Dg*})c8TkjwpO+i_Ks0
zl@?J1C~nZmhW&KftU0Ez97b_maic$gfr@!uA)QbRPlTrs#gVrFgeqRr^gdiM@GwG)
zP{e)%<t;^*dYIf+JYE2@I|_z=hIbV+X_U=U%pZgzTM_aeg)K+1_aBtG3dOeo<|)24
zp~zQ^j6rcv@g)b~eML9QN|q?%SSU*sDWz!rQ^n>`6weeh8H84)I78dg)r!==P}C@#
zC};azvF8SgT7_}r|7A`(#(YFmJ1=?+NSCR(=wRFDR}!J>dh9kD(e2Bn2)Fyvj;QFd
zt1patZlj&bUggvoy)RsXO`lHf;i2z;wAbHnGxcu&IBeR;z8Khy>ww~MU>G<hADn~Q
zP!NODMgcWs<w)3n8F?8E7}}>2{9ldT2hFgd9hZV`cnwmhvJqS8)X&HTv^6rS1EoPn
zw@Jr!%yzmH$Id<un{oeAo_>6)*Sa2No8J&P*m^nzbWTju1bB95dK)1fW)`Yoe2n=x
z9r$2|`xVM?#)-bLC}v*<i{{|pUe;|d%v{+x8Z_Nl*9`b^XV24QVINyd3)B5<-X7E)
zVB;tk;=ziP5%XjNX|7@OVwceh;2=Ag5`x}r$G_=jW6O;&^<h8Mpzvjf`oifEHd+L!
zKl@96D37sIXo_~6ot_UsAbW&be1hFYi}VmSfd-LK_Q~G}EsRY$iMo@ldK&7&Sx?%C
zieTfGAc|8q_We@$jbvZ70qJSB%nn5qyOcIk&aiC<f%`1GaRZd+*tL}3!{E38${03J
z0vEAtERQ0N{m%uxbDnKk16(}o)d1xMb|5{CF0#?3C=%F!bqFSr-QtO`li1MRi0Kk*
zD@{b@W!B*hiYx4jSZI^kUer-3>}(ApO=Y8L&Ys4e8V%)jcFkzGxWW4SBA9fxt_FT@
zvUdK!WwN$GaB+(@(9`=id;1D{{SMoyH{f^KC<e+bwz~o>*=(DkkaF1hwhY+hv*U>L
z9=n_p&-d9?bj0ET``JjCK4kBAL{Y$gY7fgo)<Ef+M=UD?>0{RT9PW!)|C^{QW)E#c
zmzJ<TUm%!L_EiV4JYnbTMO_&?xEL%?*{>+SSI(}az4Z#Vup`ZqD%nz6<2++Wliw;f
zh7zaMYyqv;YS{bK`On#jLr_=CerASL$G$3p`xorOgD76ICojQaJ*%Lc{3}-XHKJ%>
zU+58NBRc{MY)rk+UxC9n?0h=o_LjAEhRFwZ;}biKolUG=5-MBR>)tT^#M+*N)PW1A
zfzpwCK@YB-+$M72!ad!OVmFuEjJmyC#tP85a{hEa$&Fio40Y~YRsf29TrzdZes1?2
zNC&t@zkt(&8%+~pPp&UL8ojvZC3YA)4{~eh7V_rWtpl46cbIYvzTC(sko>rDR}oVn
z_jU=26I?$J_zmJhMgkDbO({hOg>ca{_JwjkvFO<_ZgK-mPIB8tu!M8@v}qW@-RueF
zDQ;glVv6LR)4b+1mq4eUY*F0$O|Ut`dA6YPELTF=_H*1X-$5D8Y2yKm;nt3V6w4i0
z1=2X~Dy<{Vb6?OArg*NH0qz3F%h9xp+{<GKG=bYy2g^im9ZfTmxDH<eeu;aM0>EYN
zauDjSaKBRe@T!fw9|7?i*M-KRWbWisaHnuuXH=$gUww{Xu5&T8w7bE1jsjaccYYI0
zZgLKEE--@|MLF(FZcGk-Rkygho*=u;^%x9?cQ^$_c$d>Hgffd8UJa9M?#2W-%HbaE
z1a&TF`>X^ud7L-}r1_k(Gm3lMhHqhWpSw?MfCt<^#Q;9!+&7>o;8b*iuaNtBCP*J~
zmGo6U=58!UFh$&7+Yo3mS8Rm)60U<cs7tx3c(6R-Hg^ELj2lgvv!~pSO|UHIKH3y8
zt>6wuLagL!DcAOl%QL~Wio1Oc!BlhG&cag-*S9n3o^$rJOsM5{XTxtDXGcBzg8Q)+
z@R!_he{k1xwWk1h#bx{eWdpb7GD2(Qa+ksKH8++<2q#`chbDaZky~l)aG2j+k2W3Q
z!)P<ipU<L%Z~#Ao#<`<>91r|4KE3rJ&Mz8;x<Ec=IU+p4Gg8n5@xzi3XfQvM)^Z^{
z`!kAAUbPBE7{724;3xT|^lJ>~6*Rg>@Qp4A?G*1EAmH~G#Ru$x%^6<y1A;lrk9UA{
zj{l8r`Dot13*wI9H~K+}<v-Bb&Nx2qThN^6XVL~yJYP@0?F;<gt59C#BL~AWfnQ&V
z2ow1;G*3w4-DoCriO*b(m@e~ABT!u7KhL3alUMos13`0*Z=?x+GQTqnrYXE_9Ew!F
z#{~qF#<yuk2VLiVUxWJw-=DUr()kC`z}@7(kf2L4_|a!zlF5HVqwOuel%CbMdH++e
zyu*JhqPWWsp*(38zb70l+5Dof@J-rs_!-|L(p<io^1^w1B;_CS`E9hrdXJBzBSQCi
zhBj{=@ORq4@*)2_?Q<9K`&WRbke@sW%16BU0NV7J??nwQ;-AnoqnMwa49gNebqb_X
z-t#}i^pyYZJCK$0i)h%Wu<<37VyxtEjRo)-pB@dGD&GHF*i`f5=(eokXHcf&Iq&co
zQZ3)715E1prXIk(;E&M}wU>OC4*=BjSy<d*!Kc~;Wdk4Cf+jWcr)dl8HUAksQ{V8t
zry+{ByzVn_zT<6410lZW&kE?o5BxeEqG;j=Ek)%=-f<}K&HU6Gz_;*IaMA{g!b9`n
z-a$yC^`E2A<_Jiggt(JX?hr21`rKK#Pa8Qqg}Oc9+$C(70TvfwOdu?G3kOD`yY>i;
z$6>iwxMiz=Cs)CT4xzXSU6-NKU0__{aG#KH5s3XlXCL4X2$N_p%0svi1)!&JVk#`X
zgzuwaa!C00XL#}v=4?ituW*afyM6*s^RdIi*6|4Di0}n*`U`he@E0I_=7!>^Fn1Qt
zZOM)aYp0?2jtigl0zObET?6Tau+1MXf`mJI&;$$DY0(fO$VQ;qp~9vS@Eazi(J|(e
zLZ>N^!i5AnO&TF|pgH_0VR?6i9VyrbK{_pX)1ite;lKG%o)J>M0Pd_X{50*-of91C
z0Cu!6i&ii(!XcXG#0s(ZA;k%C;~<?EjAMY07iuXxeL+y~hQo`30t1jNL0Gs7%0!{_
zHy}+C8jeGGNk|Nb^0MHO0Lv@FALXdKDqN$L+BHG`6F8Fv7Hd13EJe6=5J9C19cia6
zP5Aj=c)Bj6L?EUc!s@pu(glY@2<E2n_en?@!Vx1}WC{hCl4H5NmhQm2!gk8EX9>j%
z(NEdJm-O4r5ta>xWv;Nx0Ka*{Rhk*(3ybNr@jYS0Uih=!7vwYqKM-cT1LC1@a1^u!
zLR1clLSa%6f_WtTM+?8lf-@zGiiBGsz!wXDyhJNXgi}j_D-|a0Mcor&BAtOP6QZ^N
z_f+V<5z2C5QVc9Bgo(9asT6LGfypz$`5a8DY(o2XsH_%lQvSV082dfgo(m;g(570U
z18o!633ZDhy%4rj@ltq-GZI*eciRV=S3=-hz#9ZjZ&)@83+ZR{TG&N9$!~=IgW&$H
zAfs)ecfxNJ{d=KsD|+pN;I;sOCc$>-8Y({u*}p*BEbON(i58)OvY4NQoYAOr5Se#y
z;V3TMi+*wvN6_+dhv-6suCs_AE`DmFKjp}GiHDEFuZuV~8`5ski4OVf5l_)>zMI%)
zIRNfr_B2TQ#DTQ`?jfGA(e%nw%%&BempFzt8V-raR>H<d{6uL5Uy=C<$|IsXoh$Yi
z*U*X80P*e?6vxGxOW`6=Y}f^dCq&of=%5g>C<9Wc=wAa|m^fSkzY*en+SEEFUW|k?
zQWR(&cv>8qYlCT&xT_T0XT)?`L!1?z==}XTaTI+c(W1Bjk;aHqj=?fkj1L4&oOqW`
zS)LbXQ)(w(yw)4RTo9Xs0k|jzMWRR$HS~i`6lc}L6EX;NDCv@zdJfWMF{>P5UlC_L
zrRU#OvF|i=@HMf$2{y^%$P=hc5g(0*-&Apr6;hhG@dreBUCa(c6gR|iU!Z5w#jUiL
zcT;>f9_};5xs;{L6c-MH-&<k}4ePhX#%xgE5r+nY?5?PwUsIO&U?U>T6}=|X{4-BX
zn*eRT*nS<j?}>~HJlz-9_6N-a(fu_V`cND}=OhcnbF`o-6e|occ_g~g>gci9a|cX{
z#9G=HEfzxx;kQIwLHA>+*r^JDC!%&2;w=-yDAV~=?Dz$6<>I`-;IvhU6^FrADF)GY
z$1`y)9mJ~=SJBzdYVjg1aBIXfEb5+%c}GB6EB23rvQAv<4crScv<S+V;^%7ts28(n
zp8iVg_ZPaPLA;`a!$xsB<vm}EPw8p)M(jHk@VBDX8FlY$;+Ad*@xA!pdLTZCM`(W3
zB+jPo;E&>XPt-Mwf6zXCi+HXL`stHcmjuZ{v5s<4j*1&S0B}+$KA>)=BK$p+yA<QA
z;KD`mIeksL6&ZAze~&`-5P|MheBB?^u8LQ*QRk+x4W`pp?utFbA?{O*lfh=cVzn8;
z98lbKgL@CfzCXb2sfeb`l9yt_TmTL#jCAJ2Td|WKGKUn2&*0Zb@!=o}<Ywsg2tUQK
zf538B@q8SVM-<r#!2K2HA3_<RP|)oAsG`J1_ti1Q1bTEFSJd)wAE?+p5S@5J;j#=i
zL5k`7p$t}p(xfLuQB7wLLKPL1QVLVdd<p5KqUS0U;fgsk;3+~es|l??rLZpmAX3qM
z2M$jw)@}q#lp;R_CTA4U6QMk-7_6Y@-#NuS+MtM5bfI}~jAAUM^J5jaDYqK0@N5I=
zg2IosXD%v&Ux741k#Gq`q9VKqZAw!7_y<@nDN^sCFD@(0Q6RgbxJ}8AtBMYEWcHfk
zA!U}56>XgmMT(+3<*-r}{{88cLYkr^2#D*7)dNu6P*l-mD_tR+hx?m~O*FmAP|T(?
zV3~?fH$ihtag4ZcE5>{e%R7o+Y2W*<f`1N^EQLMII<ghtDG^$ZB78ZDT*U!T#G9ws
zOhb3RqLALPx~K3?q+QbcipBK&d!T3-3WpCBwhgc;P^4W4X`y2HWE4e;*g(Wxtf+eg
z%M!)-pHP%3j&P`ZstBMpOSz(oMz&{)@ezorN---4b=8Ww^lYnD%-;lub&Aj8fqS8t
zPn%({6xrXxpRGahv2|xq@fSt|*=t2YGHBi?q<Tni6)!^({s)CK?e{e)niqiPqoRNg
z$TTYkGw{@+m_-w@Pl{9ah{8d+kj89B<?c(6oRp{Or@ce@j1G-DD`o8g->LlmKLB<q
z|E0-;i%t2M#;e`R_1WmQJ<9UuAl<86_8OJ0%J1k{nVZt?1|)aoca*K(r|i)d`2EU5
z-+}Fb@)eDi9?J1~aN()EQVf8Xa#25+98^yJ8HKm<8m-t4DI?c`#Yfp31j$#qnO?u}
zQ`)?%(NTw$;X8ppqO1sojlXi68AX87d;-d&%80Ir@R;%qJ$a5RljxTdsH~!;-U+26
zZPx@TC(eWvtPG$XD7=o+2i&2`pG}A`OzBNW<W4Gkmm$z_rQsLABb46;qPeG(jkXc6
ziBuk;@8Yy_=|EIQDf>}Y^Ng~NjtEC9|9XVF809G%bYqpJli@I4d4|qTT~LNlOc#}H
zqQI7*9ION`QMo1#mPyJ%DWJZj^lXc|%gUbpKz2pBL<ihe<>AfXyr#@<rd`rx<-s?g
zNl|J=xKCAnLk`oF)w|J{>&lL_Gjl^ZW-##S$^qdhZYuq0-#SA%pAIQyDhGT7?v^s%
z1W&h>26}GZQR4h2eicfGIUvhYW}F0BwzAFVh$%;TnvN{xD&0oX-cg=%O#~|Ql?S)M
z^qz961HQHU$~!dmdZ2vN8_GhZgm#4=DeuyK^;r2cZKo9}N7+GHtbG3iEK8K%UPDo)
z%-Mp_o+^KBP1`DaQ_i7I>AVSzc%f`h%9qM*^cbsGzQ51l_xDQKcm<>l%8_&mrBS(?
zb}L^i)lbohZ<L$6q7`qIz1Aa&cS@BW!1qcErC~lOM{b7Hq+CObtdGj*wJ4gEQu-CQ
zC>Iu@?vs*x4fhVJB{b?es@~CT!%20J_RDvu&Qf00=B(OoM7dKnl#(mERF9{ja8W6C
zqiMTU5(fA^DwjuyVy~)fJ(O;$j1Hi2S8W~u(tWBPIq1Cos=SpjIiUKBe()ZuqS2`H
zRBc*^CV8nY)9JB;s!P)mnzt&Kj#C^`b+iYWk4=@|9}az0KhvI-pNd-z?O|0HIu~?A
zRb&N?zbcP<HbAwVCjUoORu-hkR67<R?BgoI3Eds2D*OcQ6RLIeOAk`5u>ugRx=fS1
z5Y^Y;01&FWF$Q6Wt2WO9XM}2Q0HjkYTTlUjk*e&rusN-2qXi;L^#_fwXH@GBK{~6N
zO4FQks?3XMTD0nHdqfeV`u-b8v8sv9Fo{!nS0ak@s{S-njaQj^0e(SM)CJN-756iO
zNl?wA3__wxq;V=q6(0`xC6%X*9;%mBrIZW1qFPKxFR!YeQO@F;YVnuwo2*jPhH#4N
z&qPS6DyL&`n5G)B5BTe<JX%KHP<?+Ny_T-3`3S!^RpG&CVTS5bKL9dSJ!w{WOU2KG
z^0q271<E_BtzO`~s~Vu8cNDTz-f{$$t$KY5ra7whbksCg^~+c&^Hc*}pv+gLFNBMG
zs;-ohy01D%nS=+bPd~z>K;^#`Q5353=rq+M)j--ee5`VyL%~HVDNPBARbTgjvP3oZ
zDlAJ?o9O)L6IF0edj6HE3h4RyRF(J&v6ZW?(^|Mv<=VP6qUvIXvPzXX28e3ahF74e
zQT?d^;JHePV?MH4RT1Sc>r|$;;C`WEdjkGa71{w(y~>Yz=9S9S1l()Y5qcQEQC*-x
z<gKdy9-UHnr!qJq?)R!~bd=zOsvjL`Yf^nT1#y2=%^U(?vntpPq%A7dVzmB~YF8Kv
z2lXuKwH@kyw7uf2R@3}(r+QU7{O(du`v{zi`rdA^>{joi{mMP+K@Wl3s~)=$O>$Kq
z=3r@aQ+KEVjk|izN!aXDKYNDQJk)m&!p2iQH5Pa;b@~RxbWq(=2p8V!6f>HANIi!3
ze0|j2vS8w??(rR>@KZDNn)G4y(Pq>gQKwK=#9uv?k`w`I<-c%vRGm}>f5+5c&>@uL
zHg)P^_zhHhqcdbD)O~5H8l+xF=iGwTWpuZMsBM&G4^^u=!z4`Y?+@Tf^(!Z^g{#>S
zu#8ZTr-P5D)ZM6qBGug|!0&0bhYw7m)TgPR&Zze{g5|9Ggd04ZQ%Ai+pwVjEG}=sw
zQO}}xR%6wnH0s5vM+i`!S4;N;5wEVN+v9?I)&aP`sGjgWNE6gcCL^@O|HX7!eSij&
zD{A$7a9>qN(k*{YeS8U|WVJU<2UFBDdV?iZ9kvtHX=)jzVXmuxwdvp@U7h<A*lw!J
zdm@Sq^=KMAGu3aaA>C5n4+HSFddmb@-c_F;4=GFCpT5{^^>y0S&QTlb9mrhu#6J*4
zp86P_*150#KugmHYN!5);-NZ&j{Fs<hkph@p?b!5uzaL;8bkXJkJXbp0biuH>xZIP
zz19bQOVmeyLZqeY1K8%0JyAED2ck?px(sYj)kDj{U9SF;j+#`c(+(h*O0~BuxSy&0
zX#22AJ&MNcYIPslx35vhSEEVK)dJl*wd%eFDC*QVH^}k(d!e5H6o{AVa>}yTtJ}Rq
zOmEaHS^#{jo=M5Gcj_V4P`+3HMIH1(t!f9hCUq~GgM3swro*yXtv!gk7Il{akUpu~
z6Tm@}L#LP>H77cw&PlW43hH)f=FxrZtoaEu5}V9L<3fws-5OI85PLMyG(p*`iK9uW
ztLEujMCzvTr74BGW>E!{`!t8XN3mbSTt)|ZYT8XjFkYIu3!prxF=e4G-kMdkJ9bFp
zP3dtT&5)kp^wqS`rl_B0`X2Z@tT{IWoVFvH81n0{nfeSxfMy(R036rUHKT(AHC7JF
z6Po^EKm=*}RX_^XjEzMRqWL7kBvkX`MzkqRBVP#INlo`-a2T$+SB5AeH1=<xJf-n#
zKqI0wTpldXXms=n?ODy+2{1Wl)98K!B3cvJ1Ew*Wz!rFl)oi70mpF~bw+Q&Wrpynf
z@tWd+Fu9=l<1FI7sM$-Y^8`%?If_Kh#3FDfX*3fN(-qB(SV&hjqpzUXuW4RWvOQVz
z!&*own%fe%Pt~km54UL=TNQ1@UDw1%q4I{tt_9i*%`Vyt&D7+$g8P={*(9*t)+Cog
zc}KH249dHjtH}UlY5tvszR1?B{04q=G^=Svo~wCJd$4($^)H~z*Te?E!voFup8$BM
ziOPaWfu>Dcw53q9%hm_@N18sAuzjpa{2N7)=1S|lN>jz6p(UDaw6rbNEEnPTi3W#G
z@jK9TrWYzJG+Fe#uGIKm1@4(9;t~K=no%85SFL$P>#!Ql2zxZ?xn`(09M)<!g+Qv)
zte~?RFEq=VXh!r>^V=ej)@#%vXkKaVJV4wHn#kqgZq)3i>D60}Go?Y_X%5ml?!6|Q
zPVaos6rTZG6aHQXlpi&#k|8x~dRXAMMYDpYK%X=N!XY_n$I--bhxXQAFmcu%>VUeP
z+K>I{`L|2E*#lY^?Mzw&?AER>N97)E=YA;mYA4ZD##QS}iBmW2`&&@DYZuXb4F|M^
zNMOo5w3YN0oToM=8&P;^o9KYSLGAW$;n!PhKL>zA+H~4+_t93IhKa8>A`xVMS{3eG
zo9wW*6HSGVXl=Q$IjW7p+ibF9+Gn(ncU*gs@-Knfxy7hEp{*;y7aODvpe>4EZ3*>r
zi1r-K$3nF|=_o>&_FvkmIH`?#hVBa2`US#aq;_}=I8SR;521|GrqjdajP^4cwQOg#
z3G~D~r=3H4?9tkwg<y-(&iM~9#cJ!0qiOM4Z<>Q#(0Wi(=c3j!12hTR9*==f)T$}l
zmZXi(hIC2m_8i=owKX*3yrM-q7rz7Tyd@~EX?c5?Bx|?!M}%qGps`@NZqqKlj`D_f
z60PdewLAL3;Z1GKb`%-fP47UHsa-{TgSWKp+at8w+HJH|cSozE&5*m=3132)rF}|S
z$y{ysE0FTE9mC-wU;9}(y5yd=a|cNGwKqG%<bjqkz~4iynvyaFTHCQbU@O#?(wyLt
zHgzfxkF^_IK~to)=-{GMo2EuEPqf=;kFQL-iPm9HwVVfV<yy&Y6cyT^H2_p<7tqlE
zOe>*7JXPB2_fS69PW={LQmeg4tExKfS(>E1(E4|W$xCgqZ9BwzZQn_td8I8A(cT8_
zTsI&ZwVt$6eXY%<E$=tlWICt!R=b5-_(6M;GU-j)CzMqEsQu^&T(dU(FVwYYGbV%k
zlQyvu)DF6DX%6A2i+%>BldeB~uRC;|=AcQ=x-^b5o;!6XXTo%kZt#5I_v$)Pw#`-d
zoYK{9y2>2*b=UP+2mC%AM-BDReYX&PJ$2(KYwV?4)eR;Gbx-NN5O3Wu8rcr%t_MTu
zqjMbuGGE>A%V6oJ+t(ZL!@9ZO!|f4Wr%cL!`s;$|mlL2feh-I7b?;~}IHvoD@{q@M
z(`oq`s2lJYq$hM2Y2q5BTmK1wU|rg6NFloO^gIdG>1e7Lru#Vo#Yx>fI*=5udz1!T
zgf8F~I8W(5(KbY+ZWwKboYpx^rnf|*bYuL0IHS8nKh?9kMdJ|LIo%yfwnyvi=!qGl
zv!lJiSY0ogGREm#6~Ld@?fM#kc-`a@wCRGb=5y3t)VX^g>;zpGdh0z=7qS{fl5US2
zCYN+EwA8w+OX>x(E4mWOSlX`Yu253;nr_lOcuLl3M#3gVC#Nm9RNV&}8q#$0c_^>z
zx=sW44c*RukkWP4>%e_ex2z-J89MO~05Wy|B%|(@ZXAszw{`yhXzv|e@Kmte)g9Ol
z4_Uh5w26|f>(H8@vguaPDk)bN@f|AjbZ!kO@^u65!P7k*?+4(0T~7m)4|FL306x_H
z5(B9~r$33#FVr2Rt@1~@)n%}Jtm{mN2#R!b8(~tc^YMZE65aee2&Pmwc_K`n=*~R=
zu1vRL0!*IjY&~Cqv|KlW9={d3m4v9&Z5;urT6gn%nAYgF(~Bt2bwUYZs?~X}KvAcA
z*amekbRi>Aywr7yL$m935-D)6bf0Ld*`OPz1X-i*-=pyGTKDn-9KO+M-a&e+3!nqX
z?{r6PbX@j5?q>i$=rZ<!tx0!r0vvwS%?*T2v+np7aJT5Pn}GkMJ6whKI_Tv}e0h%g
zmy|7Y()-hE3p@1gEb5%~mD_>aslP_k!Cm^-EeOU%f3-CitUvJp(eKgcJq71p{p$NR
z;9d1T;}M0M{!};6xa-G#2Wg+aigFJ7_0@GSJ)qxCz3!ne9)dtU^(pj+Fue33eW5(4
zzf98<Z~gGgfFIINx(`kt{Sq49ef7?C2l?q&(W36KzJ_w{NA#&2BJ|g92%_g-fPMvS
z2_4mcLDREi`Y>829M_McfhJHtg3c11(EoJ+Qjk87+8eB2N3*ODecQEYTB!a>0HiRz
z-$Y0!^-n2Z8?KKYiXuWklHQv;rC&?G)JT2sIY_7V7wH66lzti-Z<C$T_xpg#v-;!I
z!RPcfvk_^uzJNAgWAuTW(HF7$2>P2nar)$rD9-EOW&$6t_w<2_3;J&;NpVrX)E7OQ
zpzlx%c%r^E34tc*>qW3!(l1p5cUfOeIrA&}{CmJ%)&Ft@09%Uw;S(TI^@CjyTbe$B
zru5hKTWP6yL$4o=(9-o?=wW_SUrZ-gGW1`_!JVmJNq+(7mVPwlR&VQX{tfOs`t@x=
zdROm#4N{iAfX=36>#yd5I!EtIOX*zw`*6VX^n>W`%D3qwY1F%?AJYNief^0Uuz8?=
z(-$@m^;<VUD$pN!2dPkhj9vtLq;EG4Y>)Ns^xQ4dmpw<k#rl=sLMqXhY=Xm5{oNUm
zp6I)L0=!KBUI+M7eLKpLl<Sk|m4*ua5gLLk^|mvggY=ocZU&lGr5}Jdt!34E?+J*h
zMjuLt(w^(@&{2q5ee)qmb$Y%QmM`>EPa%qz`fapjU9X>~Mkl<|f7c5x8uaz)U}@A}
zrhUiP`s8CM-smUBK>1d`l3v1lr|;4U#e4lG8$EYF=(l!)O_M&5rt}~6>p~EIv%X+F
zY+CdOj>7LJ{UA!3I~Zo(feS~&Ydb{YWSAHazz)NXgD`P6EISX}PQ#QnFxh3O-VGBM
z!+Bb`?KTMX*N^rXn)`!guc6Zrn7A6o=Fs!c&CsnUXxt5(D22Yyu<$5o_8SIFMsdK<
z(iaF1gEj_io`zvlVB%#E>7?61gM_wwybWKiLUG9O%`Ehjk3m86ZC}H@Rj~9kv^b+H
z{SEOn1_l^ZZBTdA;6r!NF+<T_dQ1DbVNxf22Z09nU}#Smoa@0IWav&eRIp+ERzwkE
zh~U5-YG7!75@rabW#mc2gtqV-ZkW6gxCq1NG(k9JI88e<k%na^n4C6*QKBizASOUM
zV^Ea9<gDQ<IwEt<phBx{vS>pDoz#gj9H$I#tYIF_bmI)(wC8o+;7;8ZZxCtXdciPn
zCyI*(pWd)cFr?{FmuR?q9W6{UXrw4E8A>@6mkrPFqqt%SrA_XuhM#{#am{eA8IF<-
zWAyNlVz^6VpDoo;Mdyms3?pcSx^76M?Xeq%;T9m$4Qr0#`?+bDNGbFTL-sxZGYx+o
zMw@OKrqi2Lw+(0GP<O`=y$CFK4Ozc}CChLr5=FMbg>o!8h7SJ#mur}t4a+=3O$W3r
z-_SM%U&TF};ba;r?;GAchWNnHhn6=F4JEW(FEDgph+qm0sr1tJBg0f$>^wGP&|Ow!
z=y@2S6&qgA%)Z1RSHgX%!M*}@PYg>^QIr|J3PGSx4Zlz>s@&jCyG0d-&sD%x8U|lN
zXwM9`##^YYGNjYydbOdPCMY!qCwdR&x#1yR<(AbN+<E~~XV5%@<qN|}I_&$>@RHW|
z^@d;(G_MR!bj!anSZU_>)-dO5z~33p?StiegIzr8J{V@u7GaYi{s7268fr$uU$fz`
ztsBG^LmMp+pA3Eb;45)3s&mm8N8{nukerOAJ3zC;sB(kkY>cLb-%evR<z{vnn_K{Q
zF`lbKFuRQ&)6nca#y)h~Vy|(33gUG&rlz9K&A5urRk#~l=r059GlmsH+HW+yr2W4G
zMrIV)JdAF%ZR2S?PxD?c<M}{DanLx$4|U$gF?Zqqkg<q<BR<AQw5{!HTrdxw{EXR@
zdpm5brzGJK;|ZE^`Ww4hKo(%UOAoc9##iTHa?BWiAMHGDoa%zQKx6M?H2*wdv>Zf;
zLB>XU0t6eo)7Twi>`s5?Dby&*glU+uITXs1Mk~#!!;P6%c#1IIqDRgt<1yMKi!`pD
z3zpNyI+_(m8D~62amE-&-{e{2GTKu-XH0WKFwsT{gGR&{9cS3%_ZMp%X9v?bV-4kK
z&KsL)MiXybnGCiIMrnTlFB<>q31EV8(tN~}XpH#_CP~KBVE|k*mahi<vhi6Dm|QWg
zPXOSmaYk2!cFmZ%0d>j7(g*-jj6b_VN;P_D!IEZdpzONsy74I;HojqeFc&uIMlJ%R
zH;r=x@f~Csbw?3JrqQ2vKW`b=9|q#K@kCE>-!abX0F%4Mrs?RJEF(`-&1_?*(NN|X
z+fu$L*SPE#DD#X-r(lwAO#1{64~*Lmpm=CZpj32$&6q17;6md+c>q2#p4kKUkBu7^
zKv`t8(!!$H7)JM1iLrhafThN0I>z?InDHlKDl^7XPUxxeE}hOQH_jdiPZh@gBY>+k
zGIZ-bGmgy%b(OL6SE#EtPN!FWYK*g7VDj9!W=R}?wZ<iL!B%Hf(_-|6aUcCrte3{m
z=}WISj-(yGSH?xOvTiU=X+ac?#`0;Pd2M`W1^kWihjW0xHU4uHb?=OAngM@r95NeZ
zAB;2TIn-p_=yhPe!S)qJ{mEEg3`z&nA~PgMlj~@-&&gCp2TXUEqIB@%Z0b)d|D7hk
zOYpPHv{(ja7n78t-fb#)f-cx&x<&7?>@@|@zK*NON^h6AnKsZW+udaO9hUn{f75#`
z`%N4Fg~<U^y6rVe57WtOVDmJ6qOE2x)6%W5IcPdUi3e|!vnP~?Oizoz?PI!e0q%WG
zIW&^_nL5+@_OR(qAxw^#BKE_Rzo~6scnUCWqG9!@Y5q=lIA*&03es_tR}A2Rreaza
zoG=xK+JFc$O?n5LVACo(avx&4*MK6_<lYx9!c6jJn4C1_(6(;4sXGlp5vKJPn4B`z
zj)4?uil?`zPn$ewH!R9@mdMVSw95fFYs#VJ{5jM4M3_XI(&?p|7}MTxC}U0b?P<Cj
zXR`c@hMqU+Ucn~b)IzD}1XIug6p1D~%D*R>*4{(iB~vHL=3h2x1r%3Ix%8!7HRaKS
z{F><vJ#LdtB_>3XVhWmsBGsg_Ac{287&@?g-IPs<p&O=!xxl5HmLO+rlif6J=>Rdq
zw7>yflWAH?&&yjT*SU~xo06x3=8nmmPPp7PWm2X;%k=#kgqCeOu?clKrtx&vH`ml+
zfcretw#}%^H&xN1^`5Em7I61X>*=p{J}|wa7n>fMa(n<NFlErXt8bynZ4W9RnG%x_
z+hfyPPq-*DY1;u<Y`Q`3*p!%VFG7Ennxeg?Eof_#Z-Y=_3Z><IrOA_)iO)=9e*|Zh
z>E&uj)uwu1nADj1(wWHTrU7ykwWiLe0jM(_y^E+{n5tL8>r3=G+|`?Ys084ZsjC$|
z(O{ZEi@ruvaTYjVn>Nz8@Wy1{72&=$RoZCg|IW0NPISLFd0mIY52iWvf@qVe=Uuq?
zXe!f#yV-P)vRf^tb)GQ!Wa@Gfbq?mQHlfbZJZ}<MoXjD$aKFPGtB2%lexpR)PV+sQ
zIqWhom<@o7xfi{$yW2c27w-3%XD^`*^1bHC=Mb=~c>o=?a5Ilz2%x+95@n9}nKNmn
zv)}w*HV_BQ8y|w(!`$#5b)M$JOQ`cQZ>QDfLG!=#2=+FAQ3T~7b6_1LAG32Gc<?oU
zIRbD$b6?8q_?xSbpb-J)Ia=BvKWg668;E1(l~suJxcN2xCIiiXQ;Oh(c_N*k2r~OE
zf!|>B3fk8UG2iZuBGmlPanOXBGa2Acn)ln#-Qngyn(9ZGamE9`Df85Oa2RQ>rVX6a
zX4P*fqRb7nq&i~`zhj3x_AJ5x%{g=Ma=3^#FQ)-C#_Z^UfMd-OJ5j`$3lo4iZ+6K6
zKHlsqgQpATZ#SdvqIn6;N)pW5XpNm{-axxEN#=$7VRFgbnf7BYn>RC%u9#Cl!sM#C
z-)a=s%)v9^$d+vG5Q)a5n6v)^Fx9-2#;!DTCS|;@n=6OG?+x>+DAc8!J@!GmX@0gI
zY#C<cvGEHt@1T=3x6Cdfz}+@aJB$eLm~ZX?_g(XEl<~?ke;9%&vd!J;FJ<JIr#qm#
za?R~NgNHnu`Exp7ns4543y6E>#WYOaH$OQ5n+IkcHT$7?3B8F}U=E~xx<YejIx+aj
zTugsj;IY{$67V8(SRmXNo15wRSYm!whnPyu*J;n=i8+f7nU|TvqX2knF8>GA<z{sz
z>MG1O$0aB$&Hgt~`OLg#3S3l~6FIo3Ht(qhu*RHD>CWfon#%yzn%DG&r#f@V3DmtX
zuXTj<(){EJ`l8<4?FKAgnOD)@Kxi-zq$zu&IlT$p{o1@!g5r(28~qi=x8`1B5#c-B
zGxOm0y?N#sAU>FV=^ef%b1H4iw3vJT1nHAGiN;I^i?TgjI9l$UL4;10G&<k5!!m~!
z_0ARqkDr?5C(48EvfQRE0T)ZJ^-%7%yqp4QkHu#>0DCPi=`eA%IKPBHH_NbM8@Syq
zt|r**vs8pZ+HWbMOy2>^UOLk0Vd3Z;g{P&8{zRvjMHz{>4_eZ_A$eQQ($e*iWrz$>
z_*jY-!lAEa6-^8LEKBK?k;9gvc4+nyO9_pq{uUP=oB<a5P!vZkxfXl;{*GCGD}d>7
z%Z3R623o$R<?RVe3$3SvEZ4o@DcG`c4T=!Uuiao0YLU_rfG|s2T05S!nCJ{yxMiFU
zfCx+9^@!<|C7edBNXwrR)Sb30p+!`b<t(MT&R9Zu#B|m&3@2x8vU8SE8v%^ASdT#)
zW7$G~&nnikcmSe^vwTbEFV0)0&>$3VSw|1E3zlJjfbF8?brU=#SoV#ElxVRWLXl+2
zrC=^u-q2F;vgIzV5w2J~DH(XxqM<(!a?SEb1RNz>X5L1GwiL_a-{2zEa+W64X_l^g
z(ZcJN;b-CghGiCQf2CWdbqCE&%k*5h&#=Vqg)-A}{xLk=vix`)Y_~011K93Z!fA?h
z*YayDOtLIT-63UL3h8aK9LvZL=&oE#!e-RvSsn!em+w`u<a1k<C(H^hWAA|ek)`<r
ztRGuO%!JPp%j+<BDYZztBFHC}xPMSrX6gMJ6i+SMBH+p`!ITlJuxzBksnU|}3cxdq
z7d;QFEPWaHthVSML#nY9EQQbK7PqyKYAqA#)Lxxspltx~FDyUMOJ^@F<?~@vZ@KOc
z<tvMfj{Y}T<dmIgv`nM-A6{FY(XH{uQb{j*ytQN~5zISF5bXrNw_JXV;)CU&3Uy7E
ze`qcI(PBJ+qS@l>28S({ARm}~vS47x@5*XjPvf?uHHA{FPF64aOBy?@U1$>TY@PWY
zz@64$I*Y!`>PoMAx>*17Kxn(IeOI7vk98_-`0useq92B<^)^lR+^l}IJLYcfNH1~h
zvnn@(bHBBn2oDFW^Z!8MVQs$>I8W=r07_DLS?d|F9kh1;8{FR3Me`sXvcAA}pv=d5
zv;w5Q)~#*8=4Xxh9ibhzrj&s6h}Cfh{Q6sK{((t=^<P@+9JLmn1@|%Q*e(DZx2~W~
z=0NMsb*MXG-TXV;2U$lI!$Yuj0ur7!S%@`;_FzM;G5?`2!mQ1iU^{6YN~2P^b?5IW
zBCJcd0ddNj{wpjats%?7ecBp69z~S(6CHXwWBo82(Vw+?pM;BZ)-8*njJCSJ1!s)a
zKzmlP)_^_e!#L~AN8mhfeM@`mws`CLJXBt=Ue1Jg(R#E9l?m4E$tV)7OKPA@vM!|e
zJ1<$=$Ak2;wF4amykc#kV+YAryEcHQSdZUC*r`^{G?=7W?Qg*3y7iDdg1KRhq67Kq
zRxACiZ(7|c4Vht`bOV-|HtTP@5aKPX(-ZXNZR>kVN8Yi%dIZE>tBE$GvaFSqM9Q{0
z(AH*-wILmTbFDwIDDteKlpe^pesVyB_pA?g!Q{Txa0T2Cto~DhduUy=0}czU*B${-
zXzjEY@jkNV(0=k`tE~;qSc<GiXmwR=O}_xs5^GW<*h;N~=A-pbtPJfam04HOfw!mD
zZDY~2a%+zkNEOzev|(RqeK7;YGiyLU0IIAfvJiH)^$6{#)>!wIp?GfXWI$1CZMg)K
zI_pDcNH46<ZItDEX)UC;1M01Fe}t!3)~$^QronoL9+QpM?r#v`Yin0JK>5ZR@g?fs
zTBC2m{X1(O!QWdey20TGYyJ^fHd$Rdp@ko<U3;Jr&DJY}AhlR+DmeUP9X=UKhc*rL
zf{0_A;eS$+!l}*i<>>AmZI;k-*}07;%}aN-8AY$h>}qqg5(t+z$7nZwcN?dt2!GH2
z<LJ8MvaG(iR+eRI!?fPL_g>^EN10{WRMVDaWxHR)$})XHHnMRr1Y{#y*@Ci%3_*r~
zfPjDsGDL<f;rBiLbw2mr^F8O>`##Sd=bZbzjA!V$?8ewic@9Sz|4RppJHu-a+B_KT
zr=if3v9lJ!ychyn8N3+_%rMl4p<jcNFXR1B!Q#iL`ezZoB5;iH10@k1XXGsRTe$C8
z>o;_g3SdOh>JiAWSp(J}#@%mFI>q>ig5$xAGIF|wFmx1D2xUYCp>&$DWDDBD7_sEH
ziDWFHut^kS0d3r)8PA2F6vOz_2ZqKn_AP)hXBeNo0Au19M`+=XXUt`yErDUS{+F)D
zSVLR7Bu2hFOiN~*z(+Y3r7*(in<Hl#!4!=@$2dcVrZOBTY?8(Zr==vF;nN8*84Tk-
zRAw@sl){)S#=aJiY(_kVP0llh$p@9gu-OACxeRv-n_OV*TMpbshT;`k0`nLJJeZiz
z5I5t2C}8B0kF${R8x30#BaMOz#f;rf=u-(}sS`L$8RJn<U&iQs3o6PPZx^C;iIGd|
zVg;jS9>!EM>S>;;Vr1z+su?FQp@WwhBar~qFzzWJx|UJ-CtVx9!nl1Gjdct^1~k<(
zik^mw2F4fU+HGX0>BYOs_@xHGCPoOYgw2e%C=%7e;FI_E8Y965q?PeDoekO;T~|Tc
z8Lv^!;dMq31)@3_O7h-zGIml>p^Gs<SE_C>#_!RL*v+uH1NA+O2gjhPm+>%NzrV@&
zv=ihOBaUKxw;9_g*4@Vlp`59H#up;=@DAfyT3rSh?X)EuWC%GZ4KXGup?8>ZM~Bi~
z#=naoWrSfvi|IYaUOEAeG9p&Om@$Two^k6qBZ^{@6O6-t5PF}nxDJR(hHe{5Q;cdC
zh?!<sU10YNV-tA|W*POiV0plJ^$ql5j`61*)Xy{GXxg!5eisFR9kVbO3Xd?SQ=!71
zxpWt7a$@cw$D=dz8#+<BFdMu8aJ4eSn<3PVnYAC%jxsCBb>hzSSO=g7^C^F{c{01n
zYwX1ozX%p@rhYN(^<kQ>q0N_>Lq}vkW;Pw$k1^jo0ke-Y6Xj5Ng1KiIq?}}Kqes@C
z`4k;+0+=QArUo*flEIiDrZs#k6rN)K{TFzGnQvu*gfM@k+|W?wYso;IW=5_9B8-_m
z4n#Opv=e{`=KsiZ6UjVGNlQ`8uW8nbX6~i=B8EAW3qUOMAZ@PCFlQrROdNB|J79@t
zuKx-ofw_y0(TPmGl}0^@*+Ka_$;@9U<0XZeb{?HM%bcK{=sD(C9!M&4Cp|Q2%!j+d
zna-5jLrex!O3uYhrjopaS<GhI^<^`i=pjANe7XyqIZT^TXv$^2d>54$n6+&Xc9EGx
zKTIC;l@LnX$!7*lqFBH@gX^t}3Yj0$1Xsk|Fb%tlnNQF;x`Ziy0NJI?1lk^zF|+nU
zOgXcfGQKV`*Srjt3T7#-UzN=L^omz8kN*fM)y#3aH*uNyFGV<Nm}M@|SIguwP`bkW
znLanZsE#@H9W>Q5bDJTpff+oDQX?~h#`!Aq-#;Oyi78%#wr1uza_+Y<H7fM}8uK6>
zTUwbb1t_&KCFH4UXUgR0?{#Jg-Er+;rc=UpCv&<Ar7q??iN3-7m)?<X=Bf>pw%Wry
zISetq%%_V1yv_XSJ*enoDh`44Gv6IX<sD`}rN|60&(a<BL1xlhXd7Z?klSmRS@;N8
z?lK>FAHzMueC7+3?lFB50T^X|R0ozZrssRGaGdE#sT&ha0p&B^XBN|yeCs6B%Ma?O
zn6JK!#%X2|`DJF9*;~Lf%amZ#wCDkI=W(#iG1rn)YMz;53u(5jux=1L)?IQ+9br9U
zk3QM6w!8$>99SWbLbfAo#T)=mtR3{l2xrz_Wb!X^VL6t7xUy<rg+4bcD~J}7qbxa{
zqup6G8zIeu#kdTFCo79Sv*yL((6r^vVpB}Shs7qRp)V_oJi~r0Z4IOyV~L)JF~?b2
z+OVErWr@&slJz_7%>7yWXx0i~y+QH2K$a^xs)AUF&M@s1%WD1rdV^V=pFnm9D=`_p
z4`ngvw0D|y@^SElvEHR<Q#h-R+>;Tk5Q^PKvg*XZMX_q=t%_zHdJM8-SpGD_#IiP0
zlE)dAfR52|tnVtJKAyGoBLEUuj<yh;$m*eYGl{j)N;!ndta1yCN@2y3EATAKo#vEt
ztSbwlH<h*WK1dqtDtsu5(plGip(%s4cPTVwvc@lgGmEv9;`Z6B^vjTPo^^?KsyVDW
za<=5MR#0&50&ANBfQu|A>TVwEqnFW^&w6Yfod^n8a&ll5vUUn#a1qP(BUBc%3MnP1
zgtZ5&#G+ExEA(=eu|8^py%nsZt*ESIJw<-sD%RUxsH|pLH~?H`ZMOxyhPC4oO0}$?
zC~@TqYai`M>R3nofU9R+r0*Lxu!J|rkJ`xkj^5v^tTIoiXku-qm%5pyZbhG3SWUE#
zyvAzHLR%}V{}k+QV<~9aZfE7tTXCHg@E%lju<|Ir)5%JveQy`*RVKQ0gLQKn!n#@2
z+W_ccy;+5}Ue@AQ&~}rx^LtwVZm}%X?b|FFZ6Nzt&80x}vsO?h;vH7#G9U(6D<}v$
z$Z96f=@2V*4cdlTJ~ThxWjW=ePa`b$0+4&Gu@FcZWl3mPIL7+l(-1b!vilAiCRn+P
z0l3dn?gYyuYjP2US*KV-o#2^f-K0JB3~R?U#LTk3)S%lBSg)>!-Z|Dobs+PsFdZsw
z+1nieuwy5L0C0p|FbNCo*})X#a$wK6L$4#-Py`ky_6;8ZoY@mPaJsN7$f@PZ?tTZv
zjXjit%A;2H#YK?q&fb0yMGtnF5RIN}@iJ6;v03yxd9!0ESm48c!VW@x*#{1R__4Qt
z3BAYI&xtVj$Jy0^P=A8GIv4Ph?AEI&`LmmQU`zlzfv#HxvK1i!1hL<C#vq(xd(EH}
z%(f0v+D{0ZMUz4(TS(t;InA!4w4X3`I63pe*$ZNzK7zd?4i-kT!ydx`MX`0^Xp3ea
z-+{Im_RlPkST>vX(r4H_7TOZnW0YKy$bOeRWl8KTa>yjJCvJhHu(vKm+gWy`^%7Xm
zv4s>XOJ$GV0X~h5=K`-9+twAp4EFNt=u9Si4}HHZi~R+~qqEuT8(_?Nb~Al9GlyNy
zL7#HjaX&)n1-5ksq+De8(QYM={oWVA<+ICZ3sb;O=z!=#b`!m@MeI~h@(LHT-)cl-
z2|N1}luFsVDT$zrZTkc)EoY0$(BDh!4|<`gf}Pd{&PsMaIdZDl5$6D?W?#sLrps*a
zQV6YKf7%ROE&KOb;I6Qpwt>{KZ`Y%;o;~*%jA>x=p8{!Q3op|8ca^<|mX#)U;6CVW
zW*?&?TMPRGTIjE_?Z{cs%I;i^QXBhY1KQfzO3G`x&eryTbg+}(1?gmaE`SwX?A@6F
z++hE-1QvF)+y4NdhaLI}6!x-DY=gZw+5bkO6SvrYI2c$L-DbZ*dyqc%L2{_}v-h2Y
zraSCgZD1W>A8`SGkexCE3y0VX)hG?KM=1_>m;H(!r4ja3a?synhrI#7D7&BL{4w@x
zyTLNfZeT<71pAMpu<$;6Q4Lro*$01u`YARtH}L*VvzJliV}?CVj?G#2TFQ5Qz}}XJ
zUd*vOGk~9GJ5bERmQzv>V#m2a8`dM7M7oo2&w2hhSR6Q=jwm^DRxr_RC(gSx=R0#I
zwt~2DUZ>g8mE%M1J~vKb7~n@aU(!P0Y30anpch`8_6an4bNtCE=EHH90qDzFOnWCk
z&X432JH{Ec2jV#A8r>W?!O?yJF()~FbVl>%{QC)d7{J*|QTRa4NAxY-Adci~2s_1*
zQH(s8!=`)HA)IyO><r~dBVp5Nj&%t=b77n#bodVETzLnj2+pYt03$hbboh?q6#RE<
zgrg<jS`6n{H`-!3;pB}z!*SjUX>ptinmgk;m0!Z_1dgu<q$F}WZo#x9&YRD`-egWF
z<(;K)0&CHBmJ^o+3(s-JtqUMDmGfQ%@M)YSo{*i+xkS@e1}E+fsL$lsYald>!)gIb
zHm8yjT+ef!qW2(&bAg`qT#o%QsJOtnNimCyoRHU{DUY-2HsJZ34fM<vaE>kou8`Ak
z9i)hJpS&W)oC-eW-j{GXDgCXKGn<NWF5@^+7EU=Qh$iGq9F83<tl+dc0a3~M^jDOs
zIK||ht>$cAiOS0ycM6)-aDtnFtL4m7=?cfr5AZt9A9gUbp7T2SW*Ru<i^0;!+4~l7
zS2_2Y^x2Fi&dcwCr<wB*xwKk1k{<N;8s`PNM%&8C`v=n6I4T!NYv;rSgXKC$^dU+e
zoWafLb|*(Z3V0WXBZFx-ID>SC?&fU04tNje7=044ms4;CEH^o$6i&RwsXc;`xy{)N
zebz;NoRCMr)6Z$)f#(kA*lws8;1to$V36~53+%qjIe7+^Bb<Z(t#O?D<dPcYl+z`-
zF-{VBT*f(zLja%Pu-}2b_c;~MfMt^7MlRAR&R*JLPIK&OYdgc)u?_lWIf*wwtPeQz
zzd*$t$KgAWc@AqGcx<`V<m|KKK1?4#I>K!_4Pwvz_cFvdaQ9JQz>#~9wnt7}7fQcz
z<~sfcy)N8m$<^%2eTIH!H|~4n%RS1CBd>@%cZlLQ9^6v8@#@L-CeON;m22yPj(T$s
zlGDwH`vz@1eYwXeVcU;eO5evi#w|Mp#BuI0O*ALCxmTd+B$q+^UVm<%8f^jGqbJbc
zK(6l)a6#PX>D@lX-Ai2x=H6w3gm5?0mO7MshNj@t+};;a3gcQAzlz3iu9W%|!S$nk
zMkJR@nGI1~11<E?TyNU>#c=P@i7%F`r9PeEPL#mVIIit3SQyXc(wQfL+usM0$h9SB
zY!bIcine6#T8bT{aOeL4;4C**1u5sa%P9*cl`FGS=rN6(_9U!G=jPD5kinG(0H4Wy
zfxOOH+_<-3MK)KVg%#(y1<wMI!%g`WnsT|#6tB9#O<;rNBG;C@M|oVvn`q1D4ppPA
zfP0%hBw5J)tr+kk?xUZhpT*pyK!`5kUOP!nol@=}ub{Dv+qx5^oIAT6m6y0J6OdNH
z-Siq{S8|mtXshB*(=Ci@?(QF<;xhMr6~xqVJKq4Q<G%a{%&zBNc?b#{xO__DY2@yY
z1nw%=nU1tg+<8j9Z|3@wf4PM#e}VR&*SLG>tk%k{qJ*e6?(+Y_ZCr1<t$CeWO`g^c
z?gh$`?&NM<2lKnQ#}tr#gDa6kOgDGIYP9um3u$WT<+^?ZmYdw<4B&2YU!)-UZSKTV
z5Z%Z1qFquycj!2V`3_feh|+cjxXWp$JIFP*LfQ~FEfBJYxt@OmahE&u1*{n1PUV8-
z9=B;1+D5te=D|6}Rnc-b&NY+u6I`$Nq3J$1<8#QK<Tg;Q;}mypKl(e(op}|287_zJ
z>(6q(mjLj9%b^gFb&eZAeua7N%^xAnmghlEEIXb{BFGWm+3k>K&r6`_qyz8FFDN<k
zp8FhDIPp|Z1K`Z7l%UOpx9wM0=*oK|2EyEU8I)9Zls88140m2l4oV)pmjnQK@(#p9
zy%+BhN{sck^4_6^(}ySe293VF>%~C$@gB`b=@@U>uNZ{mych$FIl)V40XfP0oZfAJ
z-gXPx0(cu-01xE7K<R5iyyxCS+bP~Wd5?m54Ytq}!h2#TI74|S=(v2ESI~x17%w0J
z!oqphQ{;S(;6)gqFp{_98hE03?q8xa(Y&jjkR8K&_5vznc?;;RI>UQrAxIprIvld&
zd57r;lEAx3-uXmc485>PywsO4PRYFU<n&JAt)+wNSzbN4ozi$?>42y6;$i^L;BB%t
zfoAez2EdcWTk|;@vw21I#+~Q&bYLuVc%vSWoy&7Ffn4A%ya{rV$EN&_Jl=~bP@m7s
z4g;Wo*SZ{}ke5giwIbf{Y>;B!0dfJ9@IHMU8cKP$>7ZH0<IjSW^B#Sc-oHyc-61qq
z@C@`(nM&UJ-yyq-XG1%wYM%8&v|Z*g_QSLqo(mhLS{`c|OuNFHoPg{)-XD}<RL?s|
zN!1NJ9{Ft=dGZ&b{wi-n5CBcQ@BfG1H}hDnklDg}pVr1}yg$C8Ym2SCf9Z8<<8>v1
zwDTCWnZC|@egit%!TXKwqjvIsCJ#mz&({%}Zt%`HKxj8_?m5`h!`o2|(#zY%fx?@-
z>T<B$;{E;;G~MQX$bjBH-n{{^^z+^!x6>V-mX16Fyb>e}S{DuSQeK9%A>O44kYV2N
zHE6oan_LSr!h2!}#@yqb*#Lt_d1W+QW4y~UXd34oB)|l3JQ{8HdHvDQG|5w>LG~2y
zm2W_%c^3jeW_a=BADiVJpesfXcw6itdX5+HBD!mx=hc=&j4l5>-MX~n`&2^O5&qk>
z3Ag8)p8?Q;pF(a_NB;7&AWr<cC(#*a{?kPuF8qig43H~-!zhHh@gF~o(ouf21~_;8
z%24RR*KLL{Pkt($M7;Q+6zK5gmj-~v$I5??&ZfTnnQ9O}{^qY?)Cs=56{VB>k7@4p
z=YK%AHv;%4s-Yr~KSgoFAiiT9@Td5TXm1+K-=Txv5Wa&5oe1UEQ26mQ|D}E?4CAkO
z7{bE&AvYl`g1?0(m`MH)bQF)`TYob`S~S0v_Ife=HRQC5<)8l-vd{42=)@Suuf7E_
z@%-YQAPM~5y)Y(`Z~YWvlK9=>7=&d06z!{0_@_5P%2|E_&7J4?D=A+!mA{>?`lRt4
zo`Ch~{9hd)GlQS-Apn{Db=GLqX7K|Tp_tA8TnO3c`Cs3Im>mAUvjFDuuaZ0R0{<X6
zH!t$HQDq)~(+|Mq^X>0IS^@t!<@FZwMFtpC#NV_OrWNxG$#qx4=iY?qQhxX+D3$SF
z`3@}Q{PZL!y2PKpOj!vP{G{DbSjm4tuCOZp70NrU=C9w2@w&`6x}mLxFQafmE&p}e
zon7JYHiEN`A3*sj_59stSlGb-`8aH9<gb1VZCCjP<QZ<_htsm(%vaDpp@kov3cc6(
zvSrZF%HMpL(pKB})sLdKou5pT-*tW`c_%ygd&z^?$xm~H-Y$O5evljdxn>CM=D)~?
zO+Eb2$urf<_mD#2O}_X#+HUc^`cZkCpY|6>AO8d$!20>G{SDLZ@Ef*6^Z;M?IgA<P
ze_BBM&msQ0SAieqKl=<ibC<762hRxK^IKHj<Coh(%qTx^6za$LiF?tRasGe?rAdAk
zxz4Bf*;hcO`Azit&+tPcVA?GIJdN4|{)81a&GGSV2P|>?tye*81<8%D$xa{-2F`j!
z@bO8guoq0zZ0jI+FC8UEfm;}OoCNh9_<fuOhelwNiy-H}S52_G8=Y|zgi^%rsGx}h
zG46ue)qr~lJ`4iDQ(*ZREM9`I&w+RgmUqGmAHi?#u-;d2tr-3E6I?f<?U+@drq%Sg
zp!7KuPY6EBgo!5wOUd2kFE~|-wgAB!v@-}4{6p^XAc5C!U^yia#i1=&aEel#LIi1)
z)e|ZRr8KeAf<DSp3ll7-Aal6jvxiWM5Jb~66Dg3mp%f(uqgg9jVD%*5L5$#MN|A~c
z6!gLTGlDgg^%y7kwj8B+fgMd$34$dTQJE-kk48t61S7PGPZreCJ|RWmO;hMuLGDtF
z+Bv~zk&u}xSj+@GP4G?^>`fO$6r(aj5cnr-$`t(g6yRBcMb-|;&K68kz~sE3{0B7V
z2uj}uFjrtVj<ySeJ$jIff}FcR<Oy!dFnaj{zjIJnAc%bvvI_;DUxrOZg184zUo3cJ
zEBaC*xbrYbsbGs9ddmdQ=0aw<AfAp)mjsLc0I3it<LLZXDR}2FfK`Gy+NV?tmgPX`
zWq~98PBns2N^_|dyq5`SR|FsJhO|0?^CsZx1q(ifX$^vpX(QGs2x|t*Rl)KP(bgpR
zhyDcbnxLIl?^Z#~esH!4`svu)F8J&w+O7+#chLLSA@HGl%AJBH>P(lwO80nf2sYDn
z*DX-cCn|abRZoDWR}e#!-%Y_*dhu=vdTB^+3jz`#v`<j}6)O7$51j(wj^K|}jOc*C
zbp@mh3U<8-(}o1@a<mN#L|<c=?+SMPjla8HG$IIH2K+sNXE#)g3e+@*jtTzs0e)O?
zY8Gu10$~Six-WQ@4)&7*w>L0cQ-Y|~5IQaR`T&H^2=d7{Ix7$+Lg53!cbj3%oM0=h
zhVz1Mx)^CIeC8JP+6lKmg0>^V@I(l++6&*g05J~2zxWX2DBKr=l9O=j5Qwwza2tq=
z(1E-$u0p#cu(%2TBuCRxq4aSW>MlIJ1tkyRIhwURg}n^0cnNFgV6V4OO1@DaVH2&Q
zzQPC5sPq#~zW{Pf=t=(g<5uCh186)U%z7Foo)kvY6$yXgj}4F(AT-i18YrBjy8=PN
zWyeuEB|Jo*p$HZVY)}djhQ11gp+f&MRGt>bj-fJ4=sti_xbQccwIYQ3DNY(G91Vxw
zD53Hd^d(y8<_VS<p>-Q2$HWRh`4Yf0!Vgtwj1%^-U{kzsg4|XK!l|V&CQ<k}?M9P?
z?rTv>7LL_{B}I7j0D6B`_>C<zof8(4X{o{yns(BJ4;=&`UAT!2mJH$dTVX|}Fo81C
zvxMg@P?RnF#7fB%xx&?70C+)og8Ug5h5u}WO?kpK$pGdH=dVCaf$*ElAcew*Db!vh
z+<O@I77IDFe3l4n4nSI|@Buw@Wx{2AkaA(b2OyV(M`NI&LKrImyizz>2ANgDXDM5$
zTKJ(I?K3V5UCBLIBV1MmD{6%!&QNhhm>mOy>x7Mz+gmThUJb9B@ZvZCjl#w4P<T}+
zriryl_{J;1H4EQ40$hvm0EITM36JgsXR8n&#>9&!jG-*_cHv*KXuB@_k_~u=(9MJX
zT&Gibem!`)gl{i^!8e4`cVJAnaQg&EkFfqORP+j)$QgT6xPnfxw}iXT18`gTGVP@L
zgf28|^$Yh3(6u{4CZ!(^2+w6e#h~!^&yYDJd^Q|<hlQd_bo;Jw2l?ejgg;)Rth{?d
zPY=i*6+TH*%b3vN7)s;9H^~<@AuOMSnES%hdq5_Ie?Nt`DdE6zl%|Di&O+#nuq+yt
zv%(t-VebQB`z&P72}8*@Ixj3A!ywp->fV6acB0*ML+OYJVE`<6qNiU&$?725_XJFI
z6eUE0IEe!P+gyq=$V25KiXK3vtLVpksBjalqaise;_n5}U38YV6ds~~`anEIPyP;o
zm*}t=#9Q<-&4E6m)}PSkE6S-w$xp<84pNSZrf3^_T$JgDQ9EH3ZCV5sCq=E~XZ9C~
z2Vro4NJCFjpy<T+00xORP|j6|=)f6_dZ@^gu5z6gahYff6TSZw6o!lb7)4uzh`|6Z
zQnYRt1|do``Vhu2TJ#Woh9ySyNj5aZiWbs`F3yO`C^<GxWNj%yF<$iKa#)%mTKNDZ
zQ4~bmx+KwW*)TX+)ZGO!DWdP`{C8IL??#9@C#og?ORC7391&@vU&27rMN7#8m?7$>
z(|V>TuLh#CL~mV$Y1yKs&jD~=^gkg)=ZG%dfudZ|hgLe!To64<XZVYv_Z|l#PZUhf
z_I%Mkift5#UZ7KVq3FIn^cIP>%mQC5QpE#TB6{frSV~2oeg<h}qLsAgDi^7DpzV@q
z2R+9XB6kx+SBgp~WL70g$p@fX<VqG^7B%s$0M>|JuY=H9(GM4axFY)74p!8OTrQ)n
zUZl5!F%2TkY4osBWTuGFRng`-XlfFjxDA$O(UUs#utj7y50-19XUHepDtfj8D%wQd
zbi=7#^f+xpuZvcF4$&Q=Pw3FyDJsgL^Iw;!k_^5fs-WkpTXdCtQ9YvfK7ig{(T9}N
zb5pd5rmb6|y>!sMEvjk*pii{38|wQ-?pp!4BO0LL9uPhAIAjlsmeVnCNR;^=dNwRt
zU5r7vEBfjuRE~)5><76g`e*@twry0jG7aXBiISC2F)msw0GSXyQVwbNMfH>qIVpOH
z9=0jb_1mbN7MbbF>x}5fry*umw2)@v2cjqnP1=h0lgq+RT($+K9TC6l4fXco=w=WH
z@yEm9bQCwxVbn>irF?s<v$(Al2p91ObTDxhe+;M4A~*5tt+3*#c;RKJcNb?;XFSB?
zlp*XXF5d;bmpGKRSKi`0%3|{oKN<i|UvVeRMSfx#3qx{DoIwd|$Hk3l5OzYmbu*-#
z6#t|H&R^_FZn6NY_=A1uTA+CG%RmH)$9BM&Q{vn>hzS-SazR^&_zlYU2^9xW4#a73
zCY`#&#9zJz&T#RQ^o~S`UnUD9#SgEB>?pBr1306_4}2gqM(nc*rC9M$6cnBj-%CXY
z<HXJ1z@~Vybu=4|3F7bQ)SW2)nx?HJak3DdNfvLVAx#mld<Vd@;v2P)eNKFiLWHT}
z9ljuG;;v_4MY`CDj`<nlk3zwjDek3JG)sKoZHUemKYRdE&Wp=W0FWcDrYK0RnD-^r
zUl6}xRipNzxa>O&VxIVDGQ{MIgX7RxAP%4>sZjh>JrG6Wh2ba_iw%X4RwC|q2d-2c
zKyyl&xbF~3<zm-rNVz1QJB?C>c<-waRw@2!6@*oZ)eLm7TKozf122m+$)!{y&QMYO
zuU7n3FjQO-N75HE>cs65@YIVhQDmn<?D8C>HHu%Mjoel7GJ1lW#0@zxrdgcx5CARW
zPip|UCax`ouvYOkAu8L%`)Czz7whi8-s|F@v(VNdo*#hT8{+(Qz`Mmils)kzUNv#R
zUEq7goBV1$R#^KFgQZXW$WD-cv8)Vg?}*1KH)TLvPy6ISac@1^hQw+=Xc!j1X#mSz
z@gH>aXGDCScAEFZgKbbdD!xib;W2T89AsP^6@?#U0uL9+eesq<uyazpl{{Hf;y>y1
zI4#y%8zE*!d?6A%v*L+4D10FPW-Y9r6L-?Z*LksG9wl2z0tE`~Bv+3>_7O>L0|54t
z=U+m}LGm*TERK@bwE#Ft{&@~Eoh75sqvRsd(s{&Hl1Fp3n`G6)u>Pnd%@r)}k{6it
zgLp{1Xq(|F*;NZ3FNw+o;w{-rY1BTFjZ^5huY^kvx1XfX9zu^vhO$A9OEP)r(+Nq!
z0SG-Qd5or2e~AlinF1u=()1Q6IYr@vAV~uq22V-4=$jqEl3kV17b3BILf3RcCC~Yx
z_O!%?2cyCy3+O^oxWtDR{|L#yl=dAd+361TQIb2aqB2_I8Vs9aB-<%(ELO5)1muil
zRX$Y2NlGd6DqgbrAq-H0<Sm*d6D3ET(Uv6XAct16q;5S*DH4Z@|E>v0rpVWKPIBQr
z^eI*H%uyiHB(C4Um~@FtD!P^-QN%)MrX-v8{#lYG<loAcTp0o2yhJgCQjX*yIyUA?
z9_~cxf}}JaZ5JiE<PXo2_)|D5U-Bzm>L`%>v<^~=C5`^*wY5aDjqWv+N*3gUlu7b}
z(3x_{ixiQ$B>AHfLMtS1ZGxCeNkJ*vsw8czU|O}rO1DxkOZ1d3P$M}c1iV&~bPXeO
zMY7@=RMbfp&=XjXFP?+5K~n4jDUA~D6hvQ@eD^y@lT{M*0eG4vJ(J*Rk-S|9Y1bs-
z<jQK5@W>6)Ci&ti*xfD>anN>MGV(5f9TEmTI-L@4dVsqmQ`aE-hGcm)I@&Fn8APc^
zVtN~-SJJTp@SBq9eIU0apV2Pzw&Zu(X7@>~0ZpL&5;h&P??|#}KQtgI`y7>n65jhL
z4M}e4VA`-`*BMB=D>+G9(-FyHT8r;Vs_AOOsALJ{n2brH{9xg@q`w@(CL|A~qZ9Wf
z8rlI(N}lfknUZAu1;Df<nD)6dlFe2JAZ8_}RnYW6GWRls&Pg`Dh|;{|VLf<krE67?
zZ703lgwhcy#~y9=(sLBsbC9kkU%R7JLdR?;>1)eDoTV@Si66~H`U>5UaFw2Y6MEgG
zDJQ{sRJw{z+3r#%#h*Q--)y7<fv0p}7aF~!Hgq)fmim>W<Rf(;pMkHmot$NU(zqKC
zdQ6%~x8;sYhy3v~pOBuTxcf=z_wLZ-Fa7WuevtraT{dI}O8@*2fFNl&ZT3$|BS*jz
zEQJ>mFP>EE1`;ZLsQ$n2C`jL=+gxGN1zAuZF5UeDNQCqcM_3Up_4^%SVx(g{;A5p<
zQW)Wk^sRd6jg#(Uq8IT}Pg}4gNXsY~pC~my424P3HRNwimLC2AfE4Ku(a>;K8cS#P
zbJBx3=vk_C!zKD3ku>SIw5Ls%KJ_dVW=NlMf|yKccpP}Lq<8*CTeh^~5QLtW2K<b+
z94VV7zg+2A3T0l9I?>F3Q7RX}>^$jBa*E_j<rJwakcRvKQYhsQ16L$92SQk}^vPma
zQ6hbp61=UY(m&`vOqtZH3615_e<<7blJvO^09Hr`4gy#y&7mz<m2_h%5Y^I?<tSa2
zHqzd(Mk+V}K&@0?4=GoqU(%0WCmkR_z4TGaj%twRMT4_ZYV3!hSEZBW4``C^PKWi)
zR_Q7qbhJg<u?(87N#Fe$jjdAA9U$7I6BXcTm(Ft_=DPG5$}#DXp1qAB?UW|<0njCN
zBiGpt>3dC((k-p<0!xq7`+tD<N?)Yo!A+^$0QfCw{c;$3Tl&i$^s`SYa0ISjYW=AX
zD(*;mk3-skbS)ig2Bqb++z&|?(zl?7r5ov1!Ch(PYN!~I&VB`QPa4bx8I``c0Pr#C
zFFhdR(wCQjOh{j#H|D-{-P;(FN$I<vLD-ZuxgJucrTu;|ZASV_I^eU?@2oU2KafTy
zK+~M`<8>hOQhN%w*vc5&P_mPqegOOt*`JguVlQib4#Yv``67s;EGrh$Tx6w9km4#U
zpuo4A>=PC$kIH<%1aX%c$Q|z?TdqOLQ&vf7FJ7`ldbqu16(TEC_{fG+!Q(4C5Q>tY
zjFXARW3oHQ*I9I2)_4R$PssQ`!QhiJx9w>2m-+qyK!B{35@Q2ph6@lHB)k0!$SIi<
zrCbHezKnpd5ZSsVcq~I@FOX;TwCo8wJ%-8R=mQnuvhANyLVSemdo7BQvK$I$N6CWd
zYErc9pco`Z#=i;@D@!hc&@(b$N=uBBMbW7!UN%Rku>{#YZ`hP5+a3cINwWQv=$0%S
zuSY3GcI0n#;;ig@@-Ll}{S<&vOO@RmfoW+nC&az2i_&F%<Xp^<ZJ|8MOxd~!;Im|L
z(?Dd)>?x9aUM8n|ggLSYrywm?_PYa07i80PkNu)-5iN>&vZv|*&zF_n1xtbK$SPD8
z%2vh#UL-4_XT4aqmHZGTvcr^)Tq;{viZ*MRY+(}Am&=w>GWR9fB|pfnknN!y^h()x
zAEBdFvI85@RxN910&!VZbQbs;+2%XYR4cngzN;&;?@nW!>SVENprT$D`!p0b$X46~
zyixW&Es9rVAL^l~Np`#lxMrE&4uBS`te;ZjuF0OHYY45fI~1*Llf6$%Y`d)ZEtIay
z@}ogIWEXdXbjsND<afz7(U#zbY-AV4xm)(|SycAOV(4a6ugu{z)ZdhCw}COYWYG&D
ztX~%P8CdSf{`3dSfNUlhY6oT3f?gDdWVu(tGb}sR1>jwohYYeuWI43;x+g27_|B*-
z@F4JGvLX)v$7McxlqO`a(fxt@vcHyKfF@<^M=&x|vSVw|?P=LBv@e>Gttdq0tSsIa
zq94erRst|5`-#@5dD$^5B^lewO%EW{PVUVI@QA!i3530TJ0%!6$S>1u?I<7k3&uFf
zvuI!BEMG&B1{b;Ab_jKqw`YO4$(JzDc2wSe5Z1fPJt*wxA(u{}%~QUl7oG5uuQx!0
zw|onoPJHC6zan>)ul$c)u)<IN`YX_MOg<Zq#^ds(5x}32zxE{XC*|H0O!SxA-UlE+
z{(UYi43y8hz=|Mw5^eKO$xqQ%F<8FfDoP>pw3ko{l?y2c{j@xmX00&!HZNEaF7LRH
z$_TlC{3Ce(BIOx}(EBL)dfMhh%a??pF-9I(jZ&<9p8N@C<exjE6es_OUXFPAv-GAW
z$OQ{P66LGO(UT+(J_^0ba!0!GkRnh23T<cQmg^9GPX0*`)Thd`zJ>K^^5<M3EL|Rr
z#02Z24EZuz6*J|(u7>O^`8`U>$(Dby5Qy{gj~)X)N1nVAh+H{;5TkcNemVgob5Wl5
z0^0KAyEnqZe7TkqPYUFRDZ9Q<e$W9n70Govh%T0wbwF5&Jcm9;Rw@sn<4~D=od-Cr
z<?=(Fz+aN9{zkD%E^I-mTAo91#btRoeYUVh?nwz_wekoDsJJ5kg$0&6dD<@k)XV$)
zz|tV!^q;3v&MbhYtMdI1gQZEHcn*d(%U8Vsg)Q=HqmXh<{&y%UTjeV$v#rf4Uq1|?
z?ee4VqHEXXe)LVH4*4YAsO*%xQ~=l|mwtfG+>rPE2BF<@Uph$j$g_%p>y<mu$@Zpv
z{btC%C4XZJWZ#y1d;(mboJV`we)$i5Aa~@Yp94N1f0NQ=2jvVk^bN_aH!~q^Snm23
z@OS0O<ZBp_OUOHLPkxJ1MMmX%nzqK|SLi<IxV)$lr3v{(1911{tes$)l&_~GwkdfX
zIoGG<hlpiHo^li{vvOT1jCmm6Cx+-b`D;5cT=R0x9tg8l{A;a6(M~Z#Ucn;@ciOMp
zE3(O@>!5g#RwYM;Ep2+76h)Lt;jGC07k0ZSzD$8^SH;(~EVwDAC|q(>(fk`q?uxX(
z0ryaJQ|6+lg849rm*Pkn;NA+h3l#Y%KA^+|U&X1lw2AjqZ2vDfr<e`}>v6>g<dQw1
zXwHH9lZtHGPWmf8{TL)b@pb~*0u^4gy$Vvi)(H41h4LM=1uIMxHwaODOv#*~iccy1
z<+S2(7fNA@^Yn@LaK%?NX+|iPbD=0w@y0LoAG}eDA8lb<v|^bU!xp3Xly=y$icxYm
zol$7XnG>gY-xvLjS4>jkSE?d;A4r<wwj(;4t|;n&rffwsMIp{BI_X)@QM^bW|HxA)
z$f=R9Soks83KUP%VZTzr2#5M=1@kjn|1K*=D2z~}sH3O5R`Cq|KvxuLbg!&V(f1h;
z^@=b$OE)N9pGB!rF`Wv|CWZI=;A~dp`eH0w6wlM5cum2l9et~!@CNj@DfrdkysohE
zhA|zA$0)tFQ!yKeA?Z@cngO@oQ23Gaw@2{=O)b5OAaY9HRCGB*+AYO4+WFm9tT_aH
zpCXDzuV3-JEdT=wUz(Q(6)yjI{uG_Z&^D|nq3if}6~h!s9Z}>^(!xDOA?>9{6(7=r
zG^X&(Lfg2)CK#oO9~GIDLUCVVr-r4I3LS-|rW8A9r#!7l-H6hxVzCgiA1MB&i0Yg|
z+Xc>f#ou&|&Q|$82V(4$gY;c;d!?xmW;-bT=}7CSyh0bLos_Y(b#hiF-SX3fGOX1F
z=%<JB&Gq2)RBodUx|cGT{53wxjZ={6t6X{>GX0dDyCLP6at+1lk1HKIK~5+ay$bCC
zN*78>4phEE$BQ84Bt3Gcl#4$@Td;BmB@l)vH`C%DraVbe&T!?AO0YyIS6eCRE?POb
z5LUz}Z|cz)t4#0&iC1ncg2Dvl&|audR0_(#nWCJfBkfsbJsqIVDZ9xZmacqg4M>La
z$OKq2mB*h&>Ado#OXyOLay?y>%2jqAgs?p2nRC#auU!2qtS?ZmogfcHp>i4ddy14x
z8_`&-e2c!AQKk%|WWREyV?0Wilt2CFR#WDX`@d4@Pg$c?$`2laF*V9#bRDKv=}0cd
zE6U;kD6CVK@}Rz6xtCHk8kB<9QEE~iqzr~;rD+hPMLCm3FI=0__&lVwE1M`&`nr;r
zj8d1f`&k%sL-`{41-g|_QxLvKxiTFpdX;bOMMrNcm9%^gDb?Yq99I4>3oLh)0o0cf
z<#|f!yr*156WgeA<!uNXQ)b5iFs|(PM%#q)haC&>!rfOE1p+^*jHFq1O4&*g>uKe|
z5Ewk8bYnu=tnvr)M?X-eFMx_UW#;Q3^U5(w(zR7B_z^1XRPJ;|;E3ua+F01DnBPN~
zgK8nMII8k$q25V#dJ`(0RU6{bB^Q-x1Zu6WD$Pzbx~aHP=>1Vu5gn!7RjWIo-a{38
z6tX>4yM6%iQgzd&&{y?r1n_<;IZeyQRPt<e=D4beJO?LKC+g64QstF`Hh<MOA46e)
zs(2OJ0#$t$l!8?ka$#tQYVbvnP^)SgxqwfrhBD9?rdmzW=x|kN60C?&*-+3lQl+3}
zH%iq&??|-j*GEwqqbhzI_*hliqv-D$RR_I(ajJqS{4nvVR$4X_RYxdWHAyuU0FtcQ
zm<m9O>X~YYKC4PR3zl;#>uvIormOD!2r(I|BuWj<RE<YMOqQx(88l_9`sjFnUiBKq
zKyp;y+Q7nGm6o=c7gX9149P{+3<VMLRH9{&lCRoGH**VANvolvP_>ZW=^~X)5J-vY
zHU*c;RgUD^yrlZbngKBts^eY|TB)iE1ENYbo{CbnsxuZmmsP)%Kz5BP<9)Q%sy^KS
zaz(X=c6D{C9TkArtJ3MT+@O*wKpItJ4j@-mIiF(GT2zC{Fy@-7iBeixRb}LjY*W2*
z8yebGXIm&P)Tzp%{aBaEjn>o~s*o{sv|D9Q%U_S`bxNe~Rb8ie`%TpobVu!$>hA9t
z(%Y(XN)_%?EhS%Uzv^&5D(|Qo=0FBitOiIKRE5$+I;7$np?5^JhXZ5ARQLYdw5xvD
zPZ_uqs(&w{@xCge1c*tM<}gNRO4Ym;nx<8GpQCL?^)t=6vnoR%Dj%pee+U(Gs<+Ef
zIj?$`Heg58L0^E_s{>u2&_P{7xe|`*RdghEQh!5XS!eY}bP9A)=lMdWtGdXaB0z5H
zwKRJjRbQ1ssJr^3*HH3Mzf=gkw>pu0Za(UR!2tTIzuXDpr(Q<cg~!x$bQ$lsI*QyN
z{_4y}p*KMN3$4C^>UX~e2~vMH31O$yOI%S3Ry*y7hSO><@-c*|zx@?fSi{u|tDqu6
z9h(n@k!lVNLX>)$7lcNu734vWQGaFxB350s35YZ5f5IRwPTl8;{>G~#mjaine)%1+
zq^SqUv7D|RBV2~M$OCPe>e#~&mZcU_9!9o0Dvus#b$%XLa;)lan6Nun9k><bf_nCK
zkc(;yE%$lqEN7JR)qCl>MS=PdJqd;CNB)7dBJ~9(q!p`6$rD|o9&<otsd|j2{xbD;
z@^qG~=Ql&sB{iRpLlx>9bTX|}AAAi`s?;BU0nTc*HS!jKm(@;Rpldbinr|SqR^3P&
zge&U8OprRYVLepTtG{Xiut7a|3cYVs+bl;%uc{p>FQG~O83(eP)yZlY+M<4!-0|1c
zQ}kH2s`t}Hg*NqXl*8Sw{^?`juB#h*KswadtW!|msqUbSMVGqG37T%G$1b3;TfL7Q
zE<I`)o%?##pHXz^ruxeyD7>Y9V+Q25dJE-v^r@dD$5g*sKv_|D)T`Y9A5i;$55S;0
zpM0r9>N7%=hSlDbiEvlF!xJncYVO;#{@qhQ(Eu{4evdrLV`?U4*^aCIM^QPUo*;+X
zef2I%|C&^1oB^3qKU@XQY4y+aQa@1F-3OUdZ&`-E%&Q;&7Jws~Zkng;H6K#CnuBI%
zABdyo^DeMBX(nm%bJnEoBZsGp<~53!xN6QkjE=f#0$vB}QH^{hc-%EFy$OVe=KF0>
z;i*|gM=dW+A#G;8HC+;L`e;gbgZOIPu3~`wH10GP9n-jfhW?(^6i|TOUt?njn*uaB
z%h9tyO>rDJgEVhM(+$j18ZGVNgEa>hqBcZRume1y8XGz-oYrKKn=4GiTn%aAn!B{o
zjnJ?kMq8w2FU2jQG<*fxqBTF#);30SQwp==H2W#fG+t9d^KybFi>CfW&Fp$~B1!Y!
z7+8`uvlgherf6&zf%UBB%PmlUPLudIcv3YN>FkiEaV`fwUE}=`N*S6N9yl{K#dF}y
z(wHY;TDE4j3Z?TJ7aG|d&3$sm=W71C3fUJlh4X-4)NFqf_U35{Xfe&#bdR8|K*OT@
zV1-uAbzj(4q{%4-uvk;P4Tuu_a~mp4H6t6KuuSvx^QbJ>^n402mo!c%V19+hV;At1
znhX!9uhO{D{rqZ8F&)+~YZ80GS);jo81Pz6?-7))Xk1PLSEt#K0%7$UMGy2fXsj<S
z1)@>o{0VrjYI^4(rb**51=-D-Gf#oFMH5FS<7=9Yf1<Kg^I<)JZJO5}g0yx`9eGHv
zYkbKE)uC~2g|JRd@B~U-ny=$QZfI6~h99O|)BPfbt4A}v2Q0msuRg$!c3X4DO0R#P
zrY!_2`Zd`!vEI=HEJ0~NGyFYDgPMzpzz=C$Y1cli37~A|yP883Djv~<(uV4u=EEZx
zu2GGJ3E5+soWFq^*ECT!)`aFciYwjMY@mx=lbY08*fgctPuD7^HO9T<x0%s=(t+Zv
zMmB}g15Nd1@XTqlY#@7H<MaiHtu`?lm3G=-C-mZowmJxv_S%2fL!pEA7_Fj?S~I1h
zI%zZGA;nqyGr8(rw1+60*i~E64)t!@cl;scsP@*|Anw|CBy<DJLwnx_LOr!TTHw93
zo^;0Y);>kK!amv$^yrMQ_L~9p-cP$F5tYZZU(>I3TpMv0<b-yZ{4OW8H{O5>f9(jF
z7NE^>1ZSYOhLSUaw3Pv<Jf;0N1)_ts&6IK!qP4$38MvX^h&@n$S}Vzi!C~5vpFzU4
zwG^t3(7yd75YgI?Xv-I)ec^WiW3|oEkbOpLeiNlQ?e840#A`2-t0O^MxfYy>+HIRr
zO43f!jnQQ7<SB5bXxk~2a#s5#&FAN|Aw{UPrfT1!&{dlDT|R2lwg0nVNHer)+tHY*
zjiifYS=zd<U}3h_o<arZwXf62=4kh^VMVT18U=+HwB{1vE^3ec1-*INR@$fMYu#la
z1=@TMa29G0QJ}m?E2G<N#oA8>!C7L}9?C&&sdi=nLd&#YoP?Nit?*qayrf-8i3Jtf
zkKe)QRcimBi#Ju;Dmva*Ylmq<zpSlW0YHuRoo`U8)xKnelq=eGr6|>DpWFgKy*7bD
zunpSJIH+vYzWO-GRqaj+5j1J7&z}RLS$mR_{aUoiUjcDV+kO+IRhvi8PMh{8SEy*$
zn%Ce-xUTKa2I<hcBw{Q&wM?1}y0rXv(3u{soL0PE?Vh7haZ}sV0ll}ht9nqnt@Sd2
zvrqdQ#a{chdv=5Kj`sQ2>Olvz6?ZTugWBkwFltC^OK0F=tuy6e+|}Nu)5eI_NU`dB
z+NC=nZB+Xby+>o(>@Zk3u8sE_NnBwSQIuy&o46ZfT3fRYuo-Q*GfK1CT1wh}p!Hb{
z*qqjhT%z;ZY}!@X>VD-yq@C{9Zm2t=OQ+;bdtLHQ;2d<>6h?N`9rzubPP!Z90CU!D
z-U=x$Iwl>FTy+_NXmiu)tnL_tqq<LGQR}XInbdpesv3az)UDbJgqQ9?A^PX7E1+<N
zk4~8in|yU)w4(dzo+|*$G2M;Dkak>mNC{0RboP58?4*wK7%KgBCAJ^|y3tpG3)H<v
zsnkKb-(H8XQ@WZMngoJ%$0$!FMAy0kLPK@8=*v0bI&BlgMCg*p$sMWti=Mm~T|aHb
zV|7}}*gd1$!-KsEy5n*TXrgWzEgVTYXIlU=b<Tf4Q<ko7Cs?v|b6-N?d7b7G6y@mF
zE`YFHUB#o6%y>a3q!sp}&P+>Vo^GTHBwzPCC0G{d1|Ef`Lfxh}A*M*TAqOgobx%<A
zu0*%+9cU`mdC~c)Ot*`^gjTM5D-JA|bZZ|4ONH)x0i;ywej}%NmClm@)jIPw=)0_Q
z)jYId*P<HTCzGhH)tMdv@QQ9NdHU;gjlD3xUiW7%jA_svqimT*-Qgt=b5*yNZW%V|
z{(cXnS-12w04=&8KKgV`x9MN#ZPf|<cBe3{wl70+r|!Zg7~iFfqBG<TT^AcBb?f?U
z!QZ1>;R^m<-6l_zZtDEYAo7;(;3<@D>z0N?U7xOzyi)zT-E?X7j*d^i$AE6mjBy#%
zeM&*FAzhm{WDe`p?J(u8?qnHCBf2eC@}}L>rS1jmsLq=<renIb^tY+wy5sbFPUwao
zfwcR&{CH@Z)D5pdX-c<)QuL;Eum1~UW^^83fz0V*$-^+O^F0LFw)$UUAk0qh--wYs
zqCe{eMfUpr*)YaIe`+4W9QF1atUx&Fo4<lkXZ?#b$GYg5XVK`Yms4!WO&<{lX-D<q
zE+}-@S7)HjL+?ppD^LB$bi(n{ueymgZ~gfV=!B0xk1hiG>cc3(!%u&HEj|8v)4$+6
zu2<2?`Go!e<%6BnhyAn&4_Bc6Jgo^q`h5C$!zq0_<qQPt*HH3Fi2h^BX$sXZ`x7ju
z^-oB^5~lCF4WZ$BBZ-O7=g@-}sh=l@ca;7>9Z0l(hd25XqrbKZBvvmD1>lT6oUY8r
z=@*h`B3?g-cjCQ83Hk>wLQJCGjgtD3^g7x^ChM<|hb~2*z5<A|`b`-qozripY{^vp
z6Bl4in*Q0v=ytmPbOlNo`n_KRm#Gi%D>%orj@^Z<T)iC~OE2g%?t}57UN8nb^Yq@u
zsLa=YPlw_H{l(>IE7aRkV5>;)`9BCL)<?e&b4&F6LP#mqZ!<$dnf}Wu{DS5Bv!wiz
ze(5c=Rp_@-q_a~0^J)mI((j?nylQ=pmBK%l^#OF}tw!JQ2l`j5-}Eeo;)=dghpyDY
z83Zfp_4Qu>-=L3IKw+bP*_-I!RlR`{4x04ezK+Uf{k!x-wCER5PWUzb^Ax^p)gS5w
zu1#M_i$=S?hTi$>`qkk8bm^o1q2137y@Ec-(5-*67G3Mn%Z~!ztKV@2rrp$kO&6_h
z>EEMt_uKjn0^s}fK9t|luWxt*@H_hSQveL;zn+6lgZdTpvkd8v-v(}2ucNfNyL#@!
zfRE_8<ovs*uN_3&sD5!B?S97edm<riT>t9=D4ft|Qrhc%{ogbXPV4v6{$WPHfg%^P
z`rzv*J<yLF1?QaJ{}$BG>x0QnVQW}L_si@I{Q*#M#ISY^^x7LP65PQsG><k%!`fl!
zbu!5Qg)nD>5zm2jk&EH|M5uQ)Y$vyno1ucv`$r9i@4(}3For{ghhg|#Nb@w5Z3Xc%
z#M3QrZ^I^XLHZc%=@y2sVPXyJ^)pCm1ANS|ejc4TZupKO(I*U5)c~9{w9uU8Z}^0Q
z8Ucn!WvH|U8veHl#UMkw4#iW3?KDjV8)j+V4>5Gpo;B1kL969y!%GKI3N!3E15M!u
za|J3R3^qRi5NY^@VzE&MPufUE8`e`qImWP%UaeR|*Ar+vV>m+>2ICCb#USy9qCK!M
z!D^U)8O21yyU##&k|DeU_+&!`?Xgn~+oQpA*3cRW{5iuT_b^VWhP$*=NHZLoL|eLH
zoKhDv3`~k@WE$2@0-j|skn=m+aEXJ`d4rC=^ps<8p{$l%Lv$YWT`)9zq3xo<`n(rv
z3k-*r0bgj4>_(}`aIg+M#fH=;z*Az#YJ{dz!w2mc%Q8cs8nVj`!U_nzWY|QG)CxnJ
z9Z01ihmt6&40|b=sM@fb+!U7$jTV$@46C09yw)(a9vZF~mQvnaok3=$$W*<-kCxyD
zgObLg(J)EV>Q%$S9*`!(Rxx_mY<NIkk`{xGa<8r#w$O^vYG8g0W7-T0Xhmx`)Tg5D
zx*>=%&pHem+G=+iF8E?7y9_xC0k~mEDu#vKhQ&J}y2tR#Svvjq8h)o64>t{tR{^|b
z2&MDyZG(nRJ$;6Yv;_AX#uPx@F=WzbF$WCMv|$=FjJARd8U9Fv>|uk9Zv5Rfd_nm_
zBZhb`q}(&KY=V?ggMn^Kj~TpHK+(A2;|$;?4C@|w_-DLohRiIem^8%E?sm$MN6W~x
z;lUXCG-G&h4ZvB$^bW8*Ff6%)wmCx~T>zRl{5lJOt?>)`eeH}N(X4gE_{cc`?2YRy
zQF1V<-C?$)al>IKbTP*GZOB?-)g8tdxEo(5XS;{-oi9-GG=8@Y>b#7W5-@rjKcmDk
zAEW;|pnZ*vT2%TOdx|ii$Ba&tvvJ(mvkl~g@mU!vPZ|gNK>Uqo?*I^BG|<ElXxvIu
zSCCQgAu3N9e>x6*!NytZLy#R}Tq%T|p~l|T5Odo2_AVg8jGu3Vrf}mB<rPL4Q$m4{
zG*<3IDax2hk5ja9e-3alMjLW&#u`sK!|XFgXNqma8Qs#*7H=%jL0E$EeY(4tX#6A=
zLziTHhSvII<Gpq(fGNgmT9VEh-~9uP=ZycOdts@@-^T$=Gk#2;T1YqUq`Zs_<KyJB
z&op|sz|bt?vh}FUHU?IsGv|$lNwnn{uhM#+YpkGP(*<Lt585sof9`;=JmVnk`tyyE
z7N{>U-qO&As0)q$blI}V_ybMS#m3DnAWDo$8_}6kqume?WyaW7(V24N-82ZjWPF+)
z(F$WaWe-#ud*Z=TWz17TXpPaVg1xmyc@kKz7z-v)sxw|*4wic3a*EV77`4xUv(dN;
zZd>c3tH#$ipchTXe;z}(n~h~50Ja#vCe~}lC)-hKH7*{8rZ(fZt3cX~OVT0jx=}$<
z?GB^I9@x}r{2&jUUB=(&t-WE~{}8&=ZCsLvF7+6{Xol!s<IcyS=%(>ya_ikP{!Wn<
z>uuwc=U`2rF^HUu{l=u@F!+w~kNrRl82fWk8Z^E^0o@_v0&*)38)I<&XwhBcxD5Ca
z<GM1m-7|hfUb<1^H#GH)85dh2bKLl7G)$W?PSVtO-`GM<>q+A=C*Y=x<u9W&Z8g5z
z0!=eUuf<S5YkX!Y5D$#?v=f*!j?>|A-sne@j;-mjVTiFaO@D#X5z`Dk9`>dkO&|^?
z@i$QDXv$Cm=VYpS1y(qlntB0nF@1O(8eC0tTfpLG8lu4HQPZERq2AqOm3{_<hsik(
zte&QQZcylDdiPTZ^)~tc1>$46GzNsPDd$lTKhty57`-49Zz1rfOdDQ=reM>n1AvE^
zrf7i-HI09R%G0J7=<-CE>5*U1-*8h61u7#<9d2lgG-+$l7G(;zdZ01Zq+A628PlX0
zJaHylN?eIIExiub1XKSHAc-dH7{)otRP`Zxk!-q7k&YD8xrboySyRVLAm>azCJ0S6
z%}`~U={wp9q?@8?Ez2;C(JGQ@`Zfj{vP`w)l*u-&a-@y)dDC{9>~c&m=7BZWq<erN
z$up&PLt4JcjfZX*nEq6N6q<}~AVns9GB}G(PthHY5|e`fQc6v=<lQeb)l$5r-1N>e
zR9-TD_ZWVy3RBoE;3`dz)4`_76!<CHs!jWI>6CWa#7u(18q*p|q^dRLk!S3R=~c@1
zt25ahKwG`3ZWG8=(<tqPn@o<oz|w4LFaywH`jgxm*GxOgptsdDUJJ9^Og;vXc2mVD
z+OC^=Dd5pzdV*fjPLrn^xGvL$I@<EwFg;7Bm~PXPCb0IH)Q2Ia*Oa0JxoKL|j*i|k
ztqp+Q+a@z*_Vk%9J_*i#laZ1{?wGDo%xl2J{s=6Crp*!nhD_!s(Kc-QhtdP@ns(1X
z?}+J00$A>uHc|%0sOf*7qtZHN%BHM^annjVz)qMhJPTv)n?7M;WT#EhX|Q6(#PtH1
zHT`u3njV;3qfnYNouNw<^QOG*DA}3g765R>>{JN2y}76ldL7I`^rJhP3)-RA$t=E%
zlC$|&x&rB9?ns6(SF71X$sTUzpXg|Q)T|i-kGuKp=OD(z{1BaRJk6JAN%b<PB?94X
z9;7wO$GnQXK)z-d+8Fzp!)fz-%v?)L#&NTu1eGVux*6y_X|^E;q`x^O9~K6fCvntW
z6llJnMrDxMD$j$^Q|6pe2n{y>+6GM_W)J#aVW{~T@|K@A+t8Uj%xsE6pTf->=`0pu
zcKs2hNb?FhzC@WjO(4<cCmw;&7_+B6Ml{yEjP?xi=8#WeOoDlalEM<rnVm2+$(%xd
zpJelZm9iyL%pos8(^)fz3;a2A897{2&GDsRO*5C%0WIAuqPZ-?9M=V7GR-9vk<Btk
z8DV|4`LiFvSzx|I$x4OhXC_c8GMj0MEH*ncp}xetVLud>nrDvzUT)UEhVEW6-z=ed
zvcg<RCx}Y3)d4(J=DVMR=d$?)+8frG_x**oT611LDzBJlUxc(e^KSYn8qB{sqOH;V
z5zU=f%~SN>Ax-8r|2YrLW_li5%-U-JTr(d|0ZXfS7kzW5%^X+`_3dV>fey0Q&AB}2
z?J!42pog92DcbXQnN>@`bHm)$jFIU!8_B!aW3IXap}pp!Z!wlP&F@p>?v{BA?d@)x
zecu7;Gw)YmWctnNG&S5YcP|2Nz??&~z@WLT5Ec%Z8+V{`*qj$eH!SX&hiNN4V%A;(
z;-0zD0`;TjQOf@uGY62}<K{nTzc68rr)|!C^HwEHn>OoSfzTQADmr}5nw@Sy{R8vQ
z*HJlVRxJbPym^=s@$D>=6wx_iNujfXy=84Ph=b+U(`d6gT7s5BnzN;maz0!v+n<Me
zSBpJGG2JZtJ5f4nafk(rhvmm%i1D<%n+#4biz~V0ye-qcVDYiEQ09rR<w_@TewHxW
zfgQ8>Jp*#wGD6Xl6PCkEfIDfKNdb$$<ySi823Re3;!zuDiK9(-kj0j~si!QnlwT2S
zaiBW}A(o#gKO@vqLkq!aOTb>RgjtxwuqoW)coC%t%YhpxMOyrdp)ks_o*c~4mgg%$
zVl1WW!4hj}kwD=Y%MX{(i8xCe#bDztetCtDS;xq8m}m*0cxsZx?_=1PY^i({r4-BG
zl$Vfd=?w;Znx%kF!|9d<<l4-zWJ+OkrsYp^{bpJE&Vuv2We06Xax4rrNUr6DC%}2Z
za&{?nU$m?ycU->3wH3GmOY~{TEVR^F-$rARWnntHS8ORd3!YMovj;j<W_guTxXUdw
z-+|?lMY<Be3X4M<I4dnzC>T~{2|WN!)s|AqKE7;8rIh9xOUXT0Uu)_87Ame-e*Eu%
zV|gwDxO&T`MG)O!u{y%EM$6?MD{8M=rhL$~CW{9bh-S-W@}ad@G~~R!W_g<)gI3FX
z<Q{3WtULkP?G__FY1b_Y<FKN`@+LigotD2S2GM01{vS#=ERURk_1%`el*8O(aj%1+
zy_UeAFitluRY6dD%kuS$bnWxDC0PsBK1;g}wF8!2H=t?IGIJiXhb%8m12JqFS_GkY
zEv-DTj9A*~^fGFB<5}RwEDsA%Id1u7DM}NTmsi4y`xa{?a8s5Y6w{ivSQmlJSbit>
z<*db&0+t6BU%X1zMe~*%I;Pp$h>t+8olTnrr6V@?LV>rpS^YDtaIo1$yAns6*C=}6
zWb<GNq&eGI$lvc`!=}KXtIgU0l-z9kYfw6B)A=1n)ZJz=J&YbU=6MW)r;Ye7h?h<F
zv#9j8aZbXJSbc0VRZ!t;lS{EjKbwR=G#<0*C4c{Mn|MmTJYln+{MsjNwoJfof1B4n
z2Oz*^!$#N}Xj4Vo;~*QqUr;(_bKnQSgKg~T=oeyh=m}U6YBTi#aHnlHuY{B^o8Q`?
zDBQ+)6O~a`n{V&IjA)zX=Kzec@getgtj%*;;Lq4d&%%m0n~z^ZWxUOo8-Pf(`I9c`
zCfV#rKxMMc{e0+6vDrv2@3S_6B2=EUnV?-os*Q&nZRs}mOaNrq{6xpeOq<6j$u7$#
zZ4e~e#=4GNp66|hYe8~shAzOi-2ZcQ-Emo0-(NG!%)U)4O@EoA)XbK}v-jT9vZbXq
zEX`4xRzB>ZATksIktK*AD4-xJG6dNuvX@L{2@1+yzxRoM&g<NJ&ikBupU=4WoO3_e
zx%`1KrP~#Gg1c_Vr~sE?7g`04EW7(z@G0A_B?#ONyEBv_%duNXnVVd@5;_BP(=LWC
zk373}`Zx9kc56QcbfF!ON`H#%3g~oVvE3Ul0kgzz$mR<ZrFQr3L-Cf~TjXMy-6P67
z+_CHa1Tf`xSFb^%!j5+reU)}ERbUdT?6%R#&}zGx+dyjVj?ibQ>g*P!!bH8DFFn2+
z>>LYVx6$rECK{XVqSnG-i`};e0oH1F`(?~bo88%;XxiHCBu6lcdv<T>;P8FBGTM@L
z+AXI9ZkOFtR0q**_Y>`Vdh9%~Z<_tU?m#7+>9xB@S<XJYC|U?Svdf=|#(uk>@51c?
zyW)jVcx?BU3)G+3&Djrb&~CX0poi?fry5G68iOe5KVtX(2C$=cKls6^F}tn5L1V(s
z{$0RK+R1(3@RVH+eeHJIu4^ky*fUzjAmYI2qlJ$n!;J|^XT}{V#^S<AU5`FjM&ouU
zxG|z>_wUZ=_yy1&jAfJ~I>gx2411o8jq~Tu_-wWp<GBH79AR{}0nM8+9SE7DjP119
z^<lj5FBE+l6LhWnGyKiyJI46ZZ)g5%wk_`iC7AIs1+z{vE=Hm&gz-lLxKoVnP2fTq
zE!W|07~`Wkn4fUQPqbBzWO)7#k<*OwFCh}e7^47aG$Zt7G@fDXK8nT|hLDz}XBm@k
z!?8HVHFt=dV?<m<V?4t-3XKVj_igk-J<oWR-k=v4)4}LWWPC<znk2^D??I9oVT0(q
z$cQswD3=(%bQ`2HcF)96E;C-GhfW$}-wX`m3PVX-i>r)Jr1*KRF(iKhI-Oymi!y`J
zFbefd#_N1YW-;O^w3N*_8e#*?4Tf$R*c^u2LCEAXuH6L5W4uY})O<!#12hU4j<mBW
zWVF#Y0g4z}6Mm&)hMOHkN*IeAL2fa=pq1HeM*P>1EMvsxfZSnxorT77MnB~ts~C^C
z7+^KSMu#M77%x7d=s_)Gbq)0E7%TopYdvEZ?F$<i`3@j=8F5J<O$<3rP&4DX7Wmu3
z@K(ZnD?>o<h&IMr7S!7ryQm)ZK4YmD6gn8yIp8`OvwP_BXE+W4x|^|tPEqzS+9<dB
zfN}i+rK@`xU(!cj`WTJKUeA8Wc=jcLK4KJ6x@Lf}h@Kjc8QbXpCp}?&w;x^%GS-`c
zJ;X?)+|)3m{uA_#Fn*ye%^2f3s#Y0iM2y3W35M@)kep;xm;pV-*inhTX@+eTei3`-
zhP@y*N9Mv>h&nM3Q$Wy}nOzOy!c@@@>&l#>N3R>RsSAqk%=bQo<RRv|h3GrXeE0^O
z@no)~T6`~N@d=0=VNQ<0dmrXP3y3eXlHM48%!r?%;LjYN4S$a@C+5K4<4i|0L;`F~
zeK}kVWD3*31~Fs#01alk-@vd>GXJEtM+o!Rbx=IT{HhyVDARNW2E&;gN@YhdgMS4V
z$sC^pOQ)G<e}WfL%wDR_j%Hr)#8}QS2WUkW!~9<~$XVw9=qVM;ocS%(<Cr${^N@*W
z&KiTk1g5e9iszYcC&S?jOa`6(No0P$8MBwf{P`C2lbOX=VB!*UC>JD!xt}T<Q<-)}
zK)cL5Zw5*lvwH-R*O<;PLoc1VfiBtWOvy1QWH7H1$z)!j{cjd?w#^IXvzf2iqcw-Q
zm@1BPnXJFT-DGwpz<eHaTNu#tnWuihJQXnire#ebGj9-*#Y`!^#Y&j7sj8rq`Q=`4
zx0pVBVBcmwLnk}Sm|nEfzr%b(39g)Jp!9kLGnRtamCSDz+JIKYTs#E#YnUuLP*lsz
zdk^O8m{&DutY^CZ4zvblD^-m&GC${lyUWbjjJ{^((I7~+Fui*~TA9wYVryeYEe3Ww
zb2<wm9n5b`aI};8?MXCtF=u9BEZt0ZTGsY3Yo@4N@&U6@3YlK!V~Tn|WLD*Xd&DeS
z4${vw*8qEf=}wgvkD1#JK;#MYElLm#GP@`zILv%Rd7=^K%A3F*Wp+|^=@|3FSD-h}
z{Ek9Z6U^sn*E7jHK=F+!=4r~!O*2nbQuM%{_0coHc3^qhLD7lT(*e$z75NG*xv=DP
zXvdYcf!>gAtaNAmBJM1wScrJAZcrHOFzdSyAmYjToa(u~Si<)pa)gzb3*ybXyA>k7
ztS=(L`LR?Vfb(ayQ0dDt)&kmE*p9P`3>ZuRtKtO=<^+q`0ZT!wMsh!x^>rH*PqG+u
zp%KD5MxobJtim$<2BEBvXmJ(BveNP*g0+j@2a&AbhM;ho^?Vgb6zj<gFcHmiTLkqp
zEJi8}#jv)}+WRbP^(`pG+E@k0AsWXzH4mNVSbtJTFoC5!4~_GzO@lCTfmI@hXd<hd
zR(wgUAE+KYnWdvL_KU2s{Xk1$)o;R-q_Wy5*m9YbLB$wpthytRyuzxYr*t~&FhxSH
zv$j)6JcG4uK8BmgvOQ^peirM+e2{F`5I#yU`vz;r3XCa-rK3%5F6%RTDdw?m&4Nfi
z>w6wNEMV=RdeTBx$$JnfVr^Lm>=Kp-#p_C0SC#0y#bVR#U&bn+*Zdt;kPLHC&WcDx
zUj-|i9;lV9LEDF*RjjS|fnCkoNBiem))`ljI+k-W6zf@fI!xBU>Zt-+BWwBz6z;Mr
zc<5_lJw*qtTUb7`fZfWH{|k{e)@VEw+F5HSLGH2MqBQt@R^m!{*u`?X1@F6Av22hY
zR$&80?;fxwR=}xVRvq0reXMVF5Pir>=mgp$*0;1a>}Soff;?s=P|))UYa!iSgRJL5
zAu`0e_8uCCSshn^GRj&t2yTp3C<hs5-S0%>Bx}xjs86vPBEU_vzNL?#+Or#er}J?R
z?DMAq<H-J@8^4nid&x(@c3~gQf~YI|KE+er*x%2BhCBNODo^uZ*W?225PP{BCgCtU
zg`VJE>^>1BkFedM(C5vb+6T;|>{ay4_F+Fyr3Ak0j+cRQjP3RhxZ~`(U(@-V0QSP)
z!Jc5Rp+#XJdkaNSgV@{R!3DF|QApw>`wSiR4`I7`LqC-Lq7%FbV`~<G3uk-K!X$zn
zLeJ$$_DCjXJ&Mh^2G^q5bH9ZbXV}?P<$0Ff_7Vmd%XWGO>T&F9FSu<x$JSF|GM;^H
zIYblKU7te#JX^s9Xd-**Zonk5^XLXjW`FVqL@u&_pgZ*v``72;VG6tRJ2a-Un-g(e
zq_OqSK>Z4PPcqc6vj3=n-D~W<^x98nm(g+2>+EBc<I7_EaDkF-W4jkY{|5W+=U{W#
z$#gsAvj0f~xyfEmA;CPhnbz+4?BQsL6tKTp3H?I$Gh0B4*nRiVSIqv0&NP>>|JQ=X
zQa1Y(=HeFn4}WmC*(%B%l(7v|0)2<Aqk|*m>`PiGRIqLHPJvdkS6>HA4ZC$aMp4WD
zn>O-w?3Q03TF>r^!zdcqZ%4v>BU^h1++Ft9Gr%>mU!Yf2GdqPsWG(FXnINrf@pDjb
zW3Qxw-F7yED#7lttrWSv&t826L+W53r-M12?DuWIVNSZ(s_RhfW`9CE_#XDxbS(D)
z`+fQZ=0kS*DtPgTy*d<JKl>(S&Ij0mROa=VT}AQzC+u6xU}BK1c^{xd?BD+c<}iDh
zR-7a3hQFac%1-zj7t0u1MBhyuXS2r8IKh51nG%+hY`zAfQ|#q`f}3W)Op{>G`SKlr
zI&ex_py<f)>ILV-8QO$CSI#u8cHB5aZ^2)8&Zh#XdvG4O1N#t1!38<Y*-XoIPfq<+
za9*4}MIc8wA1r|dZ;p|!&Z8XvVTv61a#BX&jUQ((#gF|tRlQI=##u|J9gcJ4H(@t`
z^Ai=WpWviyf~7#tvghDa5N87gx`R1i_@VD4M@gsZPjT$2JT#P(dk-eUI3H8QDxBj*
z`>qJi)fMQA<Yecg@ifN}LfNY*PPrAL(HvLGG@aqZSE4h9Q?>ylmXo>xUc_<SX+d?4
z(^3T2;yKX@SW4h*orK<bPVRYlae?DWKUyM(O^LN6j;R%m$(&9)?Q@YckPd}ZjytU_
zFLO38fJhqW%oaFfyTY+i4)`kPBf284aTw2{HJxKe$7`>1QWt?_aK3*E<}*2;GN72n
z**5{n8yxNLFrUM@K%ari<*cVP-Azu%VGJ~nGq(i_`JAP1fD~{9J2Ah7oHOr2p@{P<
zRS^_(eu+U}iGuU+zs&<jH~{x=bAH~6)-q21>+tCgrzanZ<(zT)Qd9+pM_)^+<m@^R
zgH@c@Db-oc>8J!~4JXC#<Eqzee>9=1k&{H1++9us72q{-CaD0snUhEdx?4ECYJjwI
zcKrl9Z5&-68rwOi>796w^CkseJ2@rU7(*9l&IJ7I=FFt+R}bd_WzipS8eatI<!tMQ
ze|?<Y^dDLta^8=D!Xr+njUrI}oVk=97~s^ELi7nIg^o53a?(pMh9S-X8zzQ1tIh#*
zg!3Jxvqw258ORuC)ESPBb2h&Uv<XiCS%^$>;%m`2#o7Elh&?xk3ZERfuWx~*Be!%h
zFrB!13hy{`_4PKeF5KWC5La$wF)X=pPalGYJ9m8u^gXyi9|HRjcYZQNJh@G@ANJx-
zWWdr9uIw@zy}4eep>ULYfUZ9u?#uL4_T_G(N01+P=)a8w_al1w9^)oE1ME0AmXbJu
z+yWo^*iaDnwK*7XFt>w}zbCm;2api%$<IJeaRdGbzeBl4>8%~ceK8s)!nwipe2L(0
zpmb9t_xHz;jN;bQ-Z`4<YJub#ZX0DtW4Of>kUz_<I0wC0?gRzL;<%z7ICGA>0&9NT
z?0Bx{1}G+QyIzOldF~l{Qzdd^?tn|;K1UTr$=tu`Wp<I9b{uvuajU5+B!$~aU%N`>
zE`JK<FLS3D7<L+0bsE@LxbIUH>s9VgwE0ZuJ|lzrb*|f47|P)C?t)};?P>9A%i?;|
zcL1}w8>zDL26wm|CUUp|o*=p0CBH)PCRbblpYpiTp8~s(dxcipMckf7C=_#Fn*qrZ
z?y@$BlyVJrFnEjm!_RQ$Hg~~Jh?H>)PXpx+_ZzB9F6aJ0FZ~K`NG~L-MBHFUjIf%!
z^dofEaF50TyOz6Z8)WLZAMXHYJ$G*~L>svAR59Mj&86+vUG9y&P-x;Nyzl2w`>O5c
z9Z0rw*A-yc_qgg<NZ#iL(7K?5%j`vCC%69?pu4y~egVmDZa<w<?%|eBq3;2A;ol&A
z+`X$H@{oIKEubH9%c%sTpZjwmd>P;_v4K41PSJ6`C*160I5EiGco&jG++S^9Lw}gd
zbcDtT_bZB@jdL?;b27ngrQcwZ%cQvZ6n7Uz)26vm^vMT%p2K%A=)l`U9y;;{=#w~3
zytn>_x-&1s8|p5+1S96qjTc1e0C(Ol%G-PJ+!w%^L%bREE;`KnVu=mjc=A4I$1mx{
zEBFzhM|gKX#6Z1yD=0*Mls8!fY#-iF6ln3|WzhL2f8LiGm^j8$UVz?lp7JId19;s(
z!rv3TmKopzd3Izlh*w9c@?hTayTClj8{7cQ5MIYg%ta_q97=1#Fy2`q*l=DD2Tn!s
zvT6Ak$#c356Q_9+s;`UU#Z%TOnwLNiy)(SZG>j>Rca0+KXL+5z06oWB^A7CB^I~Zq
zpTN69asKnX=i1@L1>Uc;mQ3W;QMr2(Z@30}$-Lz||NCYT&*?1KOFVH245si(3!!nD
zH-8iK(|DdYL9X!5(No|muaE`(YrK(fFs5|gtsL0B&fCC3Uj}avg$*-#M;E}gEZ&<G
z;mhVNpiNB<?-$Ae<nn^3KK>?e{w|O_-u^HcvgPyCi{M)UFCz{5g}gw2=oj$>8$pVB
zD>p;5gctG###G9)WW)Szp5Zz8TgHo`VuCxom6UBL=Y25*pDK9EXdhq6YvO@a@h-}M
zQq5aWJMS7^O#rxB-e<LNrjGZ51PYBdo~|D*-sSyD>&+&f_cma+@(%1oXB+R~I~aXC
z?^~M72fVp-X0Df4L$$$uye$`D_aSc)#l|1;uB$=%d6V==7~nOXfr-aF4=SvC!docB
z00()C9WaO?-smoH!@Mo8KxBkxlhDvcdC9bOALC{J3jJ}OBfVKCc&YRZo5WQLjVazB
z-G9@(d5hqTJ-_N_C^+ylw?o8{KQ|jgbK<|b6OGRNc`stTF8mM)hUChRq%eXTzilTB
zy7NP+PSk_{=0_lh_;YNZK=Ckt=5h?%ldpXZqF#I#8t4)Jc`9P?=KoDkw4?mGJ<#ys
z&j>@KFTdIwoFD&;34Q+j4OB>YjNd@}_~ZO)113L!|5gl8PVkkKyba|4Nw4G}zLI|B
zV16h)`%dyt$Ng9L&fiQ=tyBCrsVp&+A4%`>Fg};I?&1806vl|)SJP5BlAlePo74P8
zI>8ggZ#@n#qWPX1A$f)`8-Pd*|Az&blC%6$s_u&A>nK7V$G`FyM9%U3j$pX){5_SJ
znFRh?d-`V3dHypWLG%JYiY|dfzH~VZCh=EM?O!s#hrUX7k$>w1e7eMEW<w-}zmWn`
zsr(XJom}S6ry7|w{ta5lU*Y?2g2Gik^A|K;=MPX>ZwBA>ALwQB|3|B-EPgbVBxLj7
zh@<=O20xoBnsWF7QP9ujms~~XP5#2Q@F|a9)dDV`Z|H@k0)8kxdkgu|RAErW-$={s
zVt&?ZP%q&(R>N*7|AlQ(xW)IQ<?3zzLD~zJ@$>2ayTiXk1;pk2iAX?K@XIOXVyoo;
zy8)h7@x#XeQ_XLuQrH@PdNdkq`H6gJ)baP%1E!w;6XlK@_;2*XZX^G16F~3s_fyq$
z6ThF%3N`b0RKSZC{)T3lXyt$T8@M*Uk|J*H{J;xPxW}KS%i}&jkb}Ms8(&8S1D*U?
zTLII>Up61D-TZgx4c)^Jp!%o>{5cIk>*WX0my7!N3+Zlr$gf-r?h$`mDn$DE9kh}j
z;D6Z<?lJ#kN;W^?_h&+6kiW7Lc8B;Ueusy{e0>>2M))Zdj2PwHDrkgbd?#8pkMq~f
z#IPs$T8b)6@@r$@#T37bc2m>*4X**zUNAQV3J!vmUJ!8<Jii1YPJ*0u=yMj#qIz-{
z!RxdSaTVOA!X`I?_5fUS7cgD~=ONHUfIB1@q!s*O!3moT)KegR1oK{k!b9-%sDMEW
z1RsHT1dYCeWIB`LC-|L8NBjlbUx30fK{*#N#{~}V5D5?j)92n!2t5C*84;YJ&!+_m
zey3W7U_meK*G>vnQFU*KKuh=iDM1cZafS+(22xBUOz@ispy7fw3o!Z!L0S_!BLxpB
z@P1mLOn^v~VAl$WL<^F>200@Ldm5KOj9`>XDb5NG`~b;V!D}zT`#8Z`8T!r%s%K#m
z;sp;}Ad(;uT?Thva8nEQ3xfGiAekuenM2FSBtZ@B2a*MIcf!&|fnYJbxFqnT%}t8n
z1eK+v3ht0kmjy4M2TYov<TymG2%=}9@2X%o6-ZnYw7me5E~xx($tKv*4K73Q{4Stm
z3))XY;fCPd2bhZ-!E7aFCRbp=6T&w8roetHu=50FdT8ehc2Xfqfj~~L*g`>sGZc#i
z9aKwHEZ9$JmJ-4JKuDGfs;e-iw*+oVG~O0`|17*O6I8qe^$LMEAEZ(+KuMx1!O$mg
zv|8{A)%(;4@+tgYE10ng(6&0k3Jtue7p%Mim<B;TWw9CsJE)}SuHgS@RoEn$fxp?!
z0#74ES_CGlFK-pxn1jYPK_7*X+66Nx%ydt%jV|*0f>&t=-68nF3eqWf`+f9v34~M~
z*)6#BH0<^W0x2!|z$Un@hJLTWcM1;o34$!J`%o~OvP+Ky{tPJg3;v47C<X)z={I;R
zxI)pQCjzeshztty=rjF8f;ANE8W#LPk(ChvmkDlEFhoI#F+p}4e%^7xYfpnr2s+$>
zIVpH41LK?$*#2jP%(S526TaCC^?w4}L3q9uqK?AVuVdPrgf4B+a2EE_+t5XL@plkc
zq1`<6xd|7KK*3%3(?%Hd5N1+d<&aRb4_+J=I?$ugQ@9utHQP)0vkyjgM96&}>fXZZ
zRNr(|7-6GwWFO%l*U;%JJV7}*KcSr%X#T>#D5-l)xN9}~jtf7ch(myIBfarX2%Bk@
z6)0R%4NF17z1uK|V4*!_%1#P*Zh{vf!cNLppAwp@fD$TPP9<t#!ZP~EP`Gdfy<sDS
zd)~Lf#Yo{CI-DCVOs9vz8DR`%L}G+lbOW3fet8n0vBH8+&=@D2HwI_U3EksiB3`)c
zWtd11`cPf*d7<hu8ZQVRX}~24U!pi#lJIj4P?CjvX$Nvqn0W{&mxL90;8KL`rzj?p
zDh#5H+hw7QcDQN6n5Up|MR?Z?n5#n8R(N<#IBx`Y(}mB{hVi=a;tP<>5Q^-;WeQU$
zY?&oYu*X2Ng)=EXena^DZdl3@o(lk2uCRC?T)Qb8+Yf*9giRLo<qKmGG_uVu5H9)>
zCJKd{slup8c()8(u`n(fT#3-w3+z(iw=~bUg!@u}c3T)vYvMBDSL@*R9pS|Q45nPT
z$sHb62-OQ=sZy9jYv~%{@C~Tf3PYnn>V!4U(5n}=(~i19=-doLwnpJudZyeJ8m~j9
zNjOO_+-BkDt0CGVEJ}qJt-`nWLZnUD^d%JAg&n^@<eqRb9e2Ag<i3x_4&gdBNT=|R
zQIIa-2`v=5h2>-5dW6BL0DB-@LlN&@VIF<5s8497m&-$&Fpv&-JQDs%OQ?P!hhF9b
z!Y@)F^H>;j1w(rx%%_;hpzvNc(1wJ2pMm*dVG|V|jR>1+F{PuzUH(uQ6Xq;I-?(si
z6D&;#{V5SNDeTRM-jp!l2Y^ir8|gHGy(pQ3J_nIaOlc)YQ5$VRoJ7C0pwn5DU<I0s
zXgeL1cNGn+g@<mU%6FjQE;>tRiakW1{{@jlBGX=w!=e-PlJOK>TMjTUk&>!1kBF8?
zq311XtwG~a(Xj@2;UjAP1d_g@%@;xZL~CpZVAo$%bPS!xL|hrjanW8nMI0b9Q|9V~
z=!LC-2^3wT@K%s$9<BU>MZOfUIVsYV0478fO{I0GMBh+ZSEy(?<xavx^JqO4F6zDq
zE<!Z!0EI}=pbxmyqQw1Bh!Tl6()%x3^uI2^oDqe3;@6H9byBb_PGqF`%Q=y61Kf`n
z4bVSoNf6zq!j|)*11mr-hyrH=G*L7{H++&P+YTgIbTbrs7e$rJFi)36%ctQ*iYW1K
zxRxr)v%>CWQP_|0B2Bbz3+3dli01AC%vDhgT>{rc59th6y2#}kOk5X@odn4c30H$;
zilS>_B1;r=6(n1<MgZ4th}O)9r5w?`?*W=CN-0L)O%XpEmhwc4>EV?x+WQ$q3Pev5
zpin5<s)RE|BKfQtxc`bpHWntKMATgj6Q!cZkKphvk<kr4-4?y~HqgpM*=F?J5i$P<
zQZ6csfTapiyB$C)MHv+LuM%a^%eY!}fv%Dok;i>V){0h9iD`pqfdY+<BGnFH-W3f|
zDNB>6n{r#WW|5E*6)mD|{qU_-RPqGQw2A6-;bOaJ<37OL6YZki<bBaysy6Eo{Y*>p
zPSF{6INBvr*8-+nbf6rTdPJ$UAP+>-RIbu1s%`>UpUCMPEIbs=qiV57q8abQ-+oc;
z2rLZPM91je{8+@KMC=n$mk!*ZD3I15L!!GBd>s~@yac-=qNixrFe*y-MBkX`$!;``
zi-PW>aYDo|g@==(7Ao<W5{U<4cUlzd4TJXLpE^Js#No6YbQCw!^3_S)vK($Zi)}k8
z*61Q$L*aB+@jJA!a1&?Hi^N_05v@8r#6zz@<B+&|H$V@ITU?=VM7)nOn%?5wf5MBS
z;;ICw`-q=zL8GsDGZiEHi8JHS=r4YnvQo#yTjxRVxcJg$KnIAw+Y9IuV!drSIs?UZ
zWiSyWK1c%%7B~I@?xgq&+DnIsU;ZBB4HGBQNsDlC0PU3`#L<*}h!k&{hcTTNizrqR
zB_5@3QALZt_!lP5h^16C93xH$2iRG$1HHXt#j*F`Q=ItKA0c^8oWGUgFY)5F{*Xx!
zAD)HLpBL|-Y|91l(=1>oiVL5I7fIq<3!#`SZXE%4QOu=l?vgm*Ux22FE5b3fRPm;2
zC|nl1Wdkft{6Z5%u83DPL+`5CK<C)5i5V2?NEe@82MgE5D{s+1QOXdrydat>Ubzi2
zSz>RxuCm3&VNkpwK0?c@9I<vBqt6vr48y~l;zg~1$rE3D04`tLKMqnL4%!3ILUAAq
z3Ps|4+D;XVxpc^&M7+5aeWl`O=fmGy;&>{6C=-X~(I<rNhz;~r!E*5fF*+;6-Bhtu
zDPH&*WU9oq3XHc}{MKJEQ6sj{Kx@VCQKY6$T;qlbt{0!6q*#Nvh9aGf;)z$GcUPP~
z8(uVt-+dNtH;e5lsoW-hdl}T*#dR@|yeIza4K&*Bi#OXtzeAkv2hdJ&Qz10E#Ln~-
z=@$3V<D*AB&mXQm5HI}<!|nwPMEb<>d~grNgNGsVNSw3?X#HZh2A~Xx{pdn`ES~)|
zP@afC{v3^i;*#ai8xp6Ufx@tOA4NPyY~raA&{1&@6_1UH|Dx!|xOiF*v<dNkH;_s3
zyb@TN65sNJ`_tkbbj{dH-W>*UkmzU!<S5Cdg^81-cnk{8k`h`TxkzlU1JhMvx_~}6
z$zMwW?Jhao1Q8F3=pS&0BsS#&h#r>2u7?RvNg<V|dP(x~A#+4B5)XZE$pOknAC+u>
z6B<5}0Sa*WN>0aOgnp90B0&5l!s{T%B&oC`I4&`yV!Qzo<!OxUgv9T6m=BaZHvzC9
z$;<R)36^|F`H_>7Ew(UphDcoK*w!h@n;rONLM2BiuNo%#je_Oj5*fwyA|!LmAQ>r%
zqAbQ~Nz(%ujFRLWg+jDs8SQz_NJavI5+m{X0t#m(9rR9(m6$$<_i>U<v}r#l*>eJz
z@scG27({|(c{0Uj&r7UfAQvRx#REH0QkMctNfJ&B^phov>2ACzG0_cwN%Hq3U{WMo
zr~)-r^5{CqWy$_d^rcB=P#NJBNhj4fU6o`}_T!r536(3SOS0EP^139-7hoBZSrqEe
zlmy!7L`#-r@t<%%Tk<qrtho|LFF12kazKK{JV`$VZt^8TI%pI~49Cz{C}}K3Uy)?f
zLG%?%c=hNjk<6esWvN7+3rn{oC3MH!maL?0T$zOD1fT9m-YEttmyG*BuR?OMn&K~&
zl9)_rR7u?WVZK_jfDZfANLKd1?^;Qq3G-YhSvQQndWo10kTytG(r&#`68$Cm?n?fp
z)pL_1<~sD6C7v=k(;~^Hug<kf9@BQJO)~TeB-<q~JcNh$B%6aVzxO4_Rshr1A^CCz
zyy=v@H3^w6$r4}4bW74GO3@>kK{2!k66Sw5o<vHY!|0Qg-G>(sCB<1Fk0fc&0j*zh
zhc2W6$%pikc`ON{7yT2-f~NpBD0yQOxFJc56$XbToeWIgh~yZRe~j8B{gZHbOj7*-
zXyX!=38E8{^&aqPQc_D#fhoz1*8w^$*~*5Zz4V`F0qP))qR(17O6Svs=p=2tfJSGj
zojo`g>3{)xu2N^(61z#W_hAy;rLOea_mECf{`ZjdR4Ez{OKl^oKs}}RUxL1uv^Nbd
z9+CDoLdIL#Xhq{u>ARa@*GIbl5A^v;zh4OAC!IA4NByNc-$dVW=~B8m0;J<qyK_S7
zLN`~SG;AH9gQP!R1qqhUUWUe#(o`zS3X#4+$8JwapR)ZQT0^D2R7(>k-5v=pT>AV%
zkO=7@#Tp}}<5a(OTDoElOhidn)9O1~T1PvAGt%#A`5Ghjq#~!Y(i|R!9V@-`7W(3(
zdfJzqlUg$&5-)Aa1eYM)(Fc+9(i^V=<$|;_h|cLJN`2|+lOzpoKxeX4`#J1hlxFUM
z!AsJ8KY&Y-K24juRO$DAFF$_GmQHnISEV0QE&esBD`BQfJAB~8b*Yg;xf#+Q4};5;
z{zU`JlKw)KQrXf~l^{2y+h+nfN80@qT*{TMpa9QJ=_U%t=Sdss0h}*=XD>twrMn-%
zLXq??Jtm5!KeVE;M5?e=K%-PDr%lc+>FO&mcv~9VjNhe98kP?3j`Zop;L4>J#NaBV
zztO&+Qo11;j#fzr=u)ee+J6S~HPXy+pwvorRFPRH^`~uey_E3>6dI%ffiTo44Uj?a
zuJq8`7<H30B!Ys*&C<s8@U2D4o&mI0=?De++N9iBAnj6b%I@Bi&Z14qedz?{;5(%I
z>3~(IwEGUwx}-O#M5<frOC?S{QZuET9!RZ4AiYw5ihTD;x6u#zQ2NYAu<%IA^2S*D
zrRoo;kaa-%>>QvymcDrtPCb#jnV~T#T}EX=L(=+i*d3N`p2W0`NCTFmZ&dm`C27Z`
z=J^mAmv+%=VM40-4qi-3SI~-UO3Jzpk!k5`Rq)APR`Mnsb&!Sr0^%$?_+PQK?9>Tb
zG`PwNeuZ5(nLXWw?lQ@{;5=lDQ=orH_H`T_J}i4e2Pr&dJyfLNC2Qh=J0i=bD4Dlx
z4ehIs%2t<v_{fe0K*U#e=~qmipUf^82K{B9%z>lFWJUD)Ixc(tI79+ufpnzYc0#82
zLTjMxdNE{B?L~{TV401Qh$m&Q9EBGlGV^!nJ0)v<4f7N#8+nMnFqyF!BwW@&OVbEh
z|8Af~$}Z8Zd0JLX!Ph9+3<~!|%U03j?Tqa9DyYZEwo_f`Sy>t%B-SSDej7ASw&yS`
zCCFAS2F!Wc$#<Y}LAK*<G$zU%2{cKTKs$kCS^5Y>F3Q}+aQl+X`X|&=WINA+q{<5E
zD!VM}2!~H;va|HCyCU=44!x_g!=Hd$lf_VMKV9}g6i}|qZ2yj<HA6Pn86(V;_0C6Y
zmW)ZaVYbYj>VI#@V&fo^Bg;*~wB^czqA}|?Wh)slktcJd+KPNxr9HR;*}^ZOS18N4
z1BD{lKU9cQEUTihO^Ixn{&iESOhKFGTe8xBfpS}>v+Y4=nXH2r*mq?AhQs}GnO77V
zD`W%o(5sZ)TLYLXS?>GjtCnq}@Jo%Xn%+jWvNvyFX6j^XDJxblOQ-K*G{`FJAkrv%
zg&e&rTX_UvO)>{pC^XBS`4EyVvgAt;X_d*0JhZmSzNQUdyKI7L{qD(<ebLz|OHG1k
zmu#~h^VKbTKoi^}`^5|7fh_qqkY1V0uWop$t-cg$k7WhRVEu_~l*%OsWj}Vp`j9M_
zVz<Mxvs8gLBHQ#QAV+1#DY`r+`>hXTT$V%Y>IvDz5ui-Uo=}O=l+48!R;OikRG?@t
zFQ#mggPid!rqEHYr&)HAn_k4cILi;%C<o#q|B)u$Rlbu-R^8<FWx#fq`~Cq94|(5H
z&_5(+($SE^@+hig@stOCjzN3L|G5qBi2Rlx^t|P-(@N=te6}C#2Fkyf2@)j#;73RX
z%L{0KcvAk|7PuB7|Bmu8r{vkIZO{*u7t(_*OwQO0E?mx{ByEKJqa!dMDIXJnJ1yVW
z0*xrSfEH}gaz8pIa7NyF9;1knn}^VMR=$q*M6vRFm2f6bzLP>4=j36(LLpx6M*-Oc
zxyOs}@Vs351;_<?{~xsON|ew48Elfgi39y)`7By2T$JZ*19wS2K{abB@{FYrNtGY}
z8|1S5S2}={CXZW#!Ca9?Im5(N`HrJ7aZS#p`z>AG`z_30m;Xy)xD5FncQj_okJB?c
zOCCT=s~q`1IM!gBohvUshSr<%pJ}z6C*S)kK=b8WDWO>)zqlWLh4O=9z!b?>Z$w|Q
ze61c_seI$-5V<AKp=i%-xg(vPEt9V(0J$T7J`pC$<-x<?D&)5ZF_ubs2_^lj<cCm$
zHM?5w@EOKptC7D)1zNT8leD_8lSfgWzFyvtgkd+xH|#}Ull(n;^ft@Cmx8p)U(1Ak
zo4oLQIMXh_`vfBQ<WZD^zb}8$2!A`|(knpelm}2ax=S9Q2UxfKGg=V$$e%k4*B;1y
zXn?&o`GY{n^vO3;{rW@s!5V-*lE-S{Tfcl89f%x|htL)LST0`(?uq=fAfOG(J2OCr
z<o}!l8J4F^!~BT+Il7HT<=%AiVod&HI~2y{e`f=8LcWh88<X<RRe+w7_cAeS)A%G6
zh2tC)Z_z^0QE{J64ml|rD7NRS7z#z7o8r5CV7n`l9N~qB;wg&H98xqIVd=0UZ!O3X
zMMORnycN5ihsaUI6Iy5bDFUfHz+bT^4<g4D9YS!&73=9I3{d=D2FVi&SKBL?(m;jN
zdoU5C$fC<DSfTp{exFp#qkKV#!sR*WpHlpA8zP|!8|CT36xV&hg)8pT9TTBYJb`4S
zqTxNLpH}Q>2Z>Tl6<~zXitu3col#8Cb|6Oak_cdD6~-Oti&eCS(z7p4ar(ckutG;C
zkKz><f`Of&c>6S5JFm!l3(j0nyiM17qT)k28j}<&dSN125w{uKMMdck;4UeAyMUdd
zxJH@rRK=wNIC@!ez5*g?3LiBl=!)VI#oezeX4e7pn&R>^bdoqjafE`2nTnrip_rxc
zSPb*oihW;#+)!9P1a^*M@&dSAMNSGpZz^60g`;_j&6ObeiaXaKQlL0TtExi99$IA-
zDIQa7uUPSKEl7!?gbnplMM^5{-crn^Q1xxa$Ebj|%`Q{;%Q3V&if=XpyIiq74WJbY
z!(W)MN<~XJ6sr`gPl2md4AQMqr&vQ}TlI>MBcRuyXv_d<RIH}Q-CYHnzR}mDICUE)
znic1#(Ac7Qe;5O7SA<N$nR|*tI+lE2F>)9pwug#0mje5dqW39~eg$5axX2aGlxrPS
zFz8`Fq&V^^`i2#KRj@RonDZ$HI;vRqGPnuFdkUDCR7hz(Go=Wnp*bj-2Vluj8BfPN
zos>cfwK*#rAA`6kKi>i{SLLhpkUwfu{<s7%K1%g9+(*93Eh}N(Px(|bM(D4cdj*z`
zDgW;`^c`0^Q%OpIavenzPADg9U?Nayd=`>H%2EoS2P>QDd45tkgJLKl%CdSio>IEd
zRE8;6(sdE8Jf4T&AVT>Q#VaC}wiUFlIjvmX3N}i)kDfO%N{bH^&nla)p)Xdsn&QcE
z%8qt8dQQ2HqD1k^`7gmzg7R@L#&lk(&x6PXW!yz5Br2B*p`N5X6^g!O<?5HfT~r3Y
z2a!w4ujqtIigLlf=u1_m+8W{1Wu<x@>|Rx#;X(Ae^5aTy8A_M0K{Azj6PUy-rRFbi
z*~*-IP`sh6-GxcWQEs8C|6FCqEVy=4x#Ka^^OS!5;PRE4qj0o9xrnm;h03};&?{2<
z?8H<SE4??sixOp(GnFrvDt}rJ>|4rds-U~ATxA4Trpzcu-yNkFWjQOAhH#KZWgD%p
z?<!T4cWzP+Q|&;rGU+c2twqVX0`*p94h8($mAk$}-#z6drQPl;k5YMPhcbx)=uTzZ
z`ygG)xjcIRbt|8y<wlQE<^YXeWf_J2`;`6e(0HgUKLYNN^7$}u{mN%9!2E!+lQJ5Q
zmA8s8iYLmvf8pAove^sVkkXx2+r!Gk+c7hv%13m^jVYD%k{DNZ{E5B^r3V$@O)4K_
zIc1wYrF@Qjn^t~t0K{H3N)cHHl{OQjcT~NogT9l>@ee3Es|No?ql;?)J$T`&a_I)B
zo9fXnc<-(Xr>o3E^+Et752=jLfE-cnpz744s)Rv6`=~~r#sGa)jlZDJPsO)Kqs?D6
zej5glseZo-(G#lldJHB|6+l6hAeE~fu!B`iOVM{ywf-^`LsSwv(05ApA;mI7RSdc*
z!&F}_1xkb}o+7c4s#)C-IjwRH0$7yFdp*>nRgagz{25i%1l*2MeL)NBvo_Ud5rBzR
zE&mfRajL)m4;trGvYCL1S6K`o=T&-7G+t1BPZOM|`adIJl2kkwfF`R#X*+aDRo?{A
z6qS7`yhv5uz6`L-s>u|Hq^a7@Lhp*ow+-A?)i$!1t`bq==(@@lUXN+ZP`OfJTc&E~
zCxFRPZT}3uWve1+VSYokgbt46tMXQ0E(%o7(;Zi++Dci@B2@)NF^W}NW}vTB)kLrT
zTdJx?^xal<SD~+5^)(CX6)GK72UV&<I?z|8s-rDdwQ8%4&Y;$+!YQ&@rwXQ=X}zlD
zGr-(cJy?vsCQJeb)2y1Bg54I?O^VI6sxD?hp-uJPn^0(1y|)LF_f_vvU0sJNi0aQf
zRr~IsuS+Go3op7=ucTmRdQ?l&Kpv>(&;`+}%G*KrU!SULFGTxQO_W_7P&pI<=CO(?
z0n8KCZx&z=s-C)sz9H4p*P%b6`e_;>qpGV^q%fwMyA&ehs<(ug;0aa3Mqp2?zRZNA
zz1s99h=bbWWi&dfyE*XQNqvgq(9UXxKmF?rSM}d7LdH!Ue;mYJy}A#g9_m<%SR7K{
zJ`GVXbyYVUJ)$m2f(dW+AtB5kRTo@=h>yC1l2X3v$u_9_skcyu%wN5*93lbgB{66`
zp<YOJe1U2`?RbLJS+so%R%g9TTj&tA$r~D{)G-+#q3VT!AmQrfmoVN4btoM`j8s4C
zfuHNN`q!^uK1#j295B)9mc{6cQO|!Djc3(yPr+cUdgsSzj8p$`6e8!;qn|=AUhPFs
z_w(wT^rpL@_HsvKqFPLgN?VdTBMT!;R=-B`m7)&Vf>}>hYxRJ+tnOZp2~JZ-lgJhI
z28xkgRe$h*=)0!Q35AF0>ZD5`*VW!s9h9M-PcgwvwQ>l~WT_J)L9*3*Y1MH<Jw#>U
zIqJ{O!%(hz`6uYRX;Y_~VIogmPgOz%>MhyuyHNcr{h~$c8*AWcv6@ZW<P!C~Y`~PN
zi$l?OOKtXm{%v*8M?fo6SC0YZj#?iJ^X2Lj6m+dn&!9rsN;Qv`<W=fh%@C<pKXm|H
zjrs^}YiiX2&9i4dYy0F~fYht|sDiXXeVR%^8r9pVRJKXIh2oOU>O#t6wx}cKqpwx%
zf|SYZHZ^w=9<{40Ze#5C)NfnScVBIyxIu?Hlq#G$)e(;Y-K7qrI;n0ogOUwB>hI~(
z9S_tuIxwzYb)~Hkt$k|MOCS%`{%?akQs-CzGoY?$hT>y&0li|LsD0Jw8&=zBr!}I^
z$N?EuzZ3^Dratij#y75J(ZhK{{Re#^Yf`<3VwO|tpDFx2tv*0c5_`>abga}t(`STv
zM@>)&Ekd0%AJc8;tQkKDQ5Vg_*=TgtG*bD4o8|#s#_k$}2l_lTm%fAhhcuZ_FbRh>
zXQ+DKQ}cldoR`Kv4SGj3j+E{8)@-DG(@_nV3V(bwN(!F)YC0$m>!<lj1K0dD(`Tso
z>X_#9dti@iJS%_}p!t`6`4gH{I<pX{af}2Pq?w>4c(7(~J_dSH<Di5WAsW9)_;gA$
zaR4Hrn(<C3glTR*1c}uAP4DN^ni`5aMrmH9U}v=EbBYI@(a7HgN{q$@&n4UJvzmJ=
z;AyO8=d&;$r@2`VE?)BwJ<t*~+s}ZU*W9FSMY5*P7j`dd7X1QeE@?(6W0|5k@(3eL
z)vQ<wgO@dni_w>+IZRvrE1HM{0K2N0p8|u|G_9?WOxMt%m)X}f|I#-HY#Ev_|3GJ^
zX88$pW@+?S0h+B@Bf>=8(5$0lo;jM0Yd~@}+p}TfrsfH)qw+Mn$Dxp~`HZfh0?qe_
zKngVnyC7Mlv8OArSTi#bA|;ydN}y1x=}CZVw=_0-7v9#`s3O12rtunr#vM)k2C(It
zRgd6Qh35BL@VioDrG;vh=707e)tb*K4p5`{ALRvVHCOF`R;MWl1Xr)w`3v+KG=n+}
zyHVppm-AhX*9?d>X=czSyIJ$-Q}nfH^pwqP)yy?Rq)lV{V;lo**BB{$a!=zi3o`dL
zK69biq4|`8@12_am%(*uzBmF$yEO~fU@$$J7neZtf#yeAi1cbaeK4jzjgejv4>cbw
zfWb$am%73AYdZ764QPHp2t$uGi|Ot4L{r!de+M<`w*P?+X&T!w!ePy#4`FajbBwB7
z#x)_dE|}2RodlWGtn-73Da{vD9W$+2I3J+)+5~4bI%vaN0P3jKybceYw4GEk<E(ul
z44jMhvp%T1Y7cLL+iu!!2S~bWJt^bpp%tf4q~wtH;3(L`+8Jfg@YD|Qf$gPrq^sqK
zcF)hy@YbIF5+X;n5B`gmYEM#Z+*g~B0cZTQ?Z3gGzxHMXMtDqHN(s~B+E?k-5}>_u
z5Ef2oyJliYfm$Wibp>gq3m_7r9hJ}`G)%jWswl#>m9t<lLi@*AU`J|?(!=Dmw&e@>
z6s3KiYAB<%KhwkSjJBPE=`q?RoiK4$dz5m?v09H`ffA>!qIml`Z57?V@mgIh`VzDU
zX2Q|)+SQb(y`a5(6BZJ+tg#um|B|#f)<Gs&`(_4Qyr?aqobDy9g2JRJ+IOErW2$zH
zp7@uw%Rfb9ns%fbcCTo=zk$D3wXf3#^O{yw1)tKjJ`_T|u617oy$o$_9vU;X_bE1=
zrOkW^joI3HM}cxfyFCYewjAv;4q9`yiBx-XQ~TQM@H<cI@irXJ*Sb=Yzd);73H?H?
zLnpi_(!R0=11;9RAVgn@)}KyYmTIN6|GA|t<AL1P{-A?vW!jIaEcA|c-%co$YX_A;
zsnGhp0hCJZ1G+h?Y+9WM>{e^DIZ&+8zBLn_wc3{hp<kyB{t%wlYroorzGm&Faad~A
z7Sk8D+O+T3qpw|Sq5J5bb{8FzxUWr_0TUfsFIp3JYJ<fXS(o;8I&avm-NJ+9Bkh*6
zKpD_F(S`q5Ydc9n@h94^5+O6JWw~HXBia|=hHs-<2U=c?X-7B0{J1vlAVem#hkC(H
zYS;RqZ%X^f3No!V(=*#%w~402LAOr|&QbR_MJk+hdsjfgSr^!ZA-U+-N$|o|_v$SW
zH{DmZ{Qz~>1=9}RL${9h8i#b<?_p?%bq2~Td+KxwIOC;zXB)7O=)$S4#as6R)t4OA
z89qj%kM4dAh_B9%E(kx}Cv_nHx`aYB9@F*z29)Evb+a(u09}Xx>L+x<4`3lsr)#1-
zPLR%<h8C<lOIhoax@+fPFhqBC6dI>=r^;a|RCnzm6vK3B8i0oD{@Mi+p_}*_jgh+V
z{@ZfsK2(5<(uK!hMx%9GZbJQx?&qh_7^Cau0Q#)XycXk()x~}T5~rK<GTndYbi=>G
z;dou<TW}^p*G2dCd0o?|@aclC+86qXI?4NJOwvu?0cf&rii)o;>K30v-zD9=chQ%k
zdp{X{sk$m!!(P_y*Tai6oh=RA72UpXF$q_7-%!lzy3WD@$<R&jq649sI%g(evUIzt
zJUd&r$_=Bxp|etrY>sX{ZJ~2@Wj{jXrtY{6qsY_!5(|-hT@00y6zFbIC3T@LjLwD>
z>C#jfTCwgb72%iY_*CRws#CoRe{bm;7C`;B&WX4(o!@h?XS<`DwFADD>kNTlD|B58
zp;4(zqT;P8-P80L`D)$H+aNW%`LyGy)w#Q(uTFQyA29X0KeJ%IL3gYXB8|GxE$F+e
zTdTobH0j3ZBz3dyyc{AeIw?IiT6I?`_0gs~bP4v_ztySe)zP6FqBUu!uHY@mbm?As
z5uM$-KPhP3qx)hWL>}nYP<pag_mB$U`gC6!Ao5V>nT@%4q&rvyu3z`pAK(Ubp+-nP
z)_oW7(MvO5v$eKjN``go!=X2#3w#QFqq;ZK!Hwx6De^q7J4vCd3EhTxpiJr>Ho)wZ
zu0sIHX<Z>Do$d9rMu6g=-*Xa;j`~@zL&Qn{h(0gktRH(8U@rPOc&5yD)${(wP~7yh
z=)i}&-e5Zi>Y?X;2TO<aV#*L4)^|`Pil=_#zku=5|4b3eBl=Uzz<KK*biv?J{Y*z#
z^3ezFg}Sdkf{IoA^x{Xr_SbLf$1ibA{{|O&$Mwq}L-K_Fb8n~z>UX{eks$q9TEPVC
zdrE9@>ZCqD6(mF-*#)#y`paLTGgRLa35_uQT>7d*xIVEEjS+egr351Nxo6OLS|3Tl
zu_!%@GEC9>SE%0MjQ+()pv35p3m|e<|A-!z=k)0x!EU@h>o^Q0=obaS-}Cx^UZ9V(
zU(iodQEZ~V=Q2D^(*H!okIDKTKge9ve?|JK`thSsysZB;027p^Hx)win%;@_km>s8
z)8X26{WH&^FGK$^UAdY1_#eP!>8JjIdbU1+BC$90CoiKfM}J@nuI1`4eNNvzxT!zC
z5u$ner>I;iU++&3@&bL(5{MS+TPc59q*rx;6zh-Qf!z{)Dy`^C^;a%{yQRNFwJx{y
zA=A(+({G@c=^cHX0Se{%B^0Ht(5oMUtJJUl5*DiTPLu<y);m+U(pIA%+6J^*z0dbx
z>-1$OAyco<S_aaf-~9_*Yt#qFg51@=&<V6AeJJhan)Ritq0pjV%mQiEOYH&Lrmv)Y
zWV=3mE66>)-*zb6*Po*#a)-Wh9F3j&O;k76rQc2C?6&FKmY}sqf2jyC5A;djgX`7L
ziH1*odd(ELhx(z9VDORN#0KftPtqf0K>s405r3?Iv<Q+<^m`9tE(Y~}^u`#{7gHW-
zSYPuM?2hOil+YX1AE21vnBH|gMmDam*P?GiZ;PX=bW&du1$Ig=qoC`w-h~P!><zy*
z0nN#<`6d*d4IhPrxEOLN{NQSMtbnAOA$A=&cY_xda(WoHQj+G7L79T-K5Pi1N13PL
z2OOiC?PZuj1!PAImwLf@8**q>b<~h!>jsREA%tqid=0*oVfHiZ4g{#bVf!0^IcDgm
zu;p>Xj13?GhHvTNbHXtC2P6XxnI7PR3>)d$7i_q&4~-`cs8qn+WSAKXlv9Q+bZ>?l
zD)<lyGsM!KF5Iy8dx%6BQvUlFrICguTVejRVP*_EqYO>$0F5@Rqzuj(!!laC#25~a
zK;x`Ib^v|n4C#lV5N}BS8Z(<<=s6B@-td((=J0}HIi0mlG)%sT5hfWreZeIgN;1G*
zG+5?g5>gC_`_PzbNZ(DR3YQHMI^>sT*g}=AR}A^pFmcV$HU^D!gFG1;*A1I)z<h>5
zY(`(EVfi_XDa&w>Voo`Rz3U;8YnZ0R!%agPo#f6lIJ<$%H`G&ISAij&N;3)#V{gFi
zBEy=`;BT>E1(q(h*(HWI{GeZI_-7Fe-ZIp`3&q=p0lE*$3{M7O;*O!2>dwmze->jd
zDh#EW(62N&l4O;^cRpOJHteP>WsTuBmEG1Fj*q~@I>QZ`i+V%Y$FR^~SeFQ}Mgw1n
zzPpC-WoWcD84eBswAnDc5x%t;R(%GUHUsW{+((8#{{iVR^aKIB)9@kHBy|~FuS35Z
z=AqYPIOGYK2L^Y_J@y((-T>EUxLpsuhX%zo$RmS{wyXUHs~6lJFlcK4HfUhcGk3^l
z_&5h>!v+DZC`Jq+3!p!0n5LnP8K!>24>N9fLyftZFeFiB$fRN4M^KzHoca}xP8*I>
zT*=;emzGtI#@o-sLnotqCKQ~Fya9-~7!PlUf~#@OURZE59{%qPnX!fkLq0}Zc{OBw
zjjZ1w<7d2e1_u3&;#8PFX6%~>&=W>SO3MZs2V0>ZWc>bDU<VuDeTcr3#y3@v3^A6D
zfIDS;IUb;)#<e;$h8f?bG-J52g<k#<#z(E-B8}>7pqw`L1p+h57-zeW)@Y-S@-i2U
zYac>C(fHgD<}%qh(SX5RH1_`vv`fZL3dW}x^XXp!q#94p1i5Tvz76a&qi!BRuNXV;
zV-Q!3dWwo&Gj{EQNV+kZYG$q*k9-c13}YW+d$Ti*aa3!TWqhWZZrp6+E3}}wVRWZm
zMvn0aZ4q;g&(qrDrg0Ii|MH9ms<qBHvdM0N@#!e^6&f3zpk8ErJp_Hl#+3o~Z(>E!
zISBK&jhiWhQfAykuH7*%rQmkCv5TIv6~;>$=&Ll&UJ7Tbj3JadsWzURi@qA;D%#G}
z8uyNXt1|}oK(gNGodxx~#<gldHyKNc(b#O<^EE_TjEZBJv{vH*5BSn%^tR0dZ8xr?
zqcHc3y8ZC?zOj5i8as?XAH-aA8o#71beGYUo-EzQr3{cB<BV1`J}{~e0=w5ZC56F0
zV_PH)J~T!=gr!HuDN0@T8*jXb!4DWuy@Jc}v9a?XG(Is7RzZEx_<c03D29xsl#v)V
zzOn<IBSyD{@M6@s=s9SN88;STyyHgmY-mgv)h;kUY1~L(Xqqx!pk2bWaTzUC?M;GZ
zXml_scR|F_^wb`xJDGmp4LxVmrri*6F}YJEiL2=aHav7QE%Buj6NgN9^D&CUCV3OQ
z@HE}~0*YRyw@*Rwi0MtLXZALIza1h+O}_`jppWS%ik<qJmd${IpDA?%6#Px6SEBKl
zX^<+{j+;jR#K;0nr-#sY!nEi+_!MZWF<>k~rUCkrRj?_0A!SZanhw!#A7W~wHP<QA
zZxpNzHE}4<7iQZ1UxwP`x(8lFm>ia16p^MKXQ6-ERL};6DAQqzQAe8^5@7d?Da3&3
zjxhy>LgcLJ3yJ~7np!tPB+hhfB^u9}wo_<5-c%C;Nn3*H>;iat-joso><cDo7R)D_
z(kVBUWJ;nMp=8rbwC1^J`YjRUlIi~_=#^qRz7U|Prt-xgmrV;B(U@j>h8nM!x;vqM
z)ij4{2CkVNZiQ><rh5w^a@}-7hgr)oy+pyxOq*#2%}JKYR|bu2Qz0EhxM8xR1#gaN
z3B3(-O^ay7chh8N0m(B>J&!Tvn|!t43QU`WAX#YI7Xh>)lTZTeV$(@FXjNirKLGQ$
zP47~yt=v>iJJJf%+f=htY5IyXK2;{$-gPioZStcdoi(Pbk72OZwBrZB)R{K4gR3`n
z`~(vXra0OdH=5RWViNC~etQ6sCKHpM9?hlzDl%v>J^T|Wt)^@jNVb{UC|lodx-kQN
z_e?_@0CwNBk0!Rm)U*&@bedM#s0zKyRQeS(x=p1NA?-0aOhEL3$(jB$Yp<z}Rx*92
zwnTXG&@`KFphqT$PhhFvR6hqI1Ez!#aF0zN&~xUANp=hBgQnbca6_hxr@#%H1a*KO
zF_|dlJZdU<8GU1>m{A+h#!X2SshmI`OiY^WC~7oi8m@rGwCN&kLha3p9!NTv6`k<g
z(fl4ouwBe$&j8KU{L334Zst@v(B^JtmY~nW{BaP-A@lRJMe{Om90WOHuBF(bx7ni$
zeZJ-*Z`w5bne*usvcK7~0aJR+{P$^~9XG3oFf#$>-SOxPGQUmh-C%RxIJlE$CwhE@
zm=99G<div14iakq=Vf4rne!tc8E&3W>&FPQJ3YZ8&70`nJZ%nIgONp<@2`SLwAqnC
z_um<_JLTtN%xOlzoHaiyhG?w$Hz|f4XFgW~&~xT-I^7U&j%<T|f_XpPW9Q8;W&`_z
zd3GJRM6>V9FqmZ4{Rxt6wnjnkqB)+nLzm3Y{~s>06mtswgsJ9MdTm}d_fiPTmS!&1
zLFS720Ik)onlDgT{F=F$R(|Q`sB;+Tb@Rm+(U@Ug*8+`9^E>xJvdmxlgJheJ@j-5w
zci~|&JICBlIsaVqQXe$lG+T1uTAumpJv8Q<3l?Bx1?D<>ofMk4@<EDh=0pGO^3Cfg
zcvNDJr;4Rg^AB`8+%mtL2ky4{ay>|y`5+bf+%bEeLSMQ0hix!XVg9!SdX?so3m96J
zc{zoUtIgr<5UDZiD$!SKE~PMWojI`<>h)%qVmQ-aF4v>6(QNzbZ}{D8Hd3`(i}@3(
z^k_A6>BFdP<|v9ix0`SK;F`N<_AZ6~ee=%Qn2Qec*Ys0#niB}S%e=4%DBb2K^f`(i
zvtS1l9+;zOW8G`^_zhrv=HM`ZJv1l#qw$e>oJ!dG%{Vavg9GN6RFKDJ9#!c)F;CKW
zu?Ec_Q+2|SxtUUO!{*Q5g5rpoO{?xvbASiPn0c-k2FJ|~51=<;ZlJQON%MZXR;SFz
z9MLyz-ZBb3drReP_~c;u@frB*XxTv7GbhVyag;fAw){xXKo?75JM6kzOkV)a&GI^Z
z?a|%ROIMPI<@I-<amaG-0{RYHKBVxAr^QBbF)zzC3V|K5xJ1B&w`DnHy^mV9mB6l#
z<<FDgd@ZAIz>uHi7mA|zTh>y{>zHN#C}mEMTME-58enOo^4k-ZL*K%gKnsiZ2SFAU
zRmKNf{uqPCNlP-F!ws=KUIc@uEW4Y*g<1}M4rjtF`x4O@Zn;NQMG+Ra0H8!#exqz(
zv}HAgGtO8nW0=txOD!$><1FEkbpM^RoS1@syyYT2120%y>D8WSd5WS0NtPcd_?v9`
zn6{P|El25*cFFR04xG7c$?d?*q*-QA9Pf(d)wvM4YFR*w{%e*`C?k_@G17|fx@Cfj
zPckh2|5eyp0_gFYW$6^bkS*KtA;su#SYoN*HpjC607$N-hjz9%El#!Q%d@;gf!%yd
zC>6dISW?@7U1%|0fqs$YH+r`gTk0rBR${59>fKVycB)&vWzh>TdABVe_F?p8mUId~
z-mx5f8qSnkW>LVg!e(L7HyA4|b0}t3WqFTcI@OlLbS%Bb;xvfHTFc>&piyTzdJBE^
zme*)`)nIX=5AQWvPJM;GyOwvT&a%nkO4n7h<>k}pYqRu+!25QKir$U)ENM%CdEZj0
z1nIB@AA{SS78{@TLtU0qD_XlPyU3{?OVT}f`oL1K7+kOAvLi^JW!W%>{m?Q~4TVRR
zkbJn-Z@KLQy8{-{R#<v$(F-B@#Bz`l9D|mv)Hh^#ldjHTOUE8yj#%2hh5D#vjXxyE
zEK6*W=p45+ZU***#ncCwNefF0>?zA4D#miKrZq#<(Yk=@Ae^i%?*rS_nsyfhb+b-0
z0qSmjBNPfA*1aDC`;fK#4EhdR{~dsNPwPQi*LYb2Hbdlyb>BP?Z|iq`Xgq5D>RB6P
ze5}{z!mh7%?hgFSe%6=i--Y;Fe_skq$E+JlA$r`J_AeR(tkd)<tP|El^au~ME;WM$
zS!cAsV2E|U4(3l;<J^H6YVC1`r7-Jp+LVP`U!xF9g!Q{Q7-yt)Ob><A);{Y@$&A@i
z*5R{|iMBp`2O~UVy>c7Q#8`hx1<YCN<JD-4wa$AN`f=7gACPm_d|HOaTNSGyl3=Y2
z$Xt${L>Gl`lC0lOpfA~)LCf`v);W}<x@7$}3X&<-DT+0uT0{Hc#bs+n2pZF@)mt&7
zE7lr{m|wNtrR3H%tNl|jlx|(>50UHEH!9&^hBcXX0-4rjKS3nRy6i9-v#rxkAUCW%
zwoQP^vGzW|&~mNUX>WJa8Y+UNJZsQZaQW6xbAeW1y<QLOLTkMOeI?c{6sEmxU3MLy
zW!7KmVAvh&0$TQ#Tf^uOa)oud2qr46Yj>fs%DTY;3e{Hjd^FZrd+x#QTC2N+b`lNN
zZ)nldXgxx8M0c&9P`0$m>i8xao2~LOm~XM3r*h|3>wP&y+N}AM6l=Gh9m215&-wwK
zQ|`3>Mem<3Yb~wgx~=E6Q0TQ@c0pgCwU&}`53TP~;n09Jp91cWtsx62{r$w+B7o?y
zwIu<dBi5-G05fWRzXvW(Sao^mo3u7loM_6b_z7qZ>sQdn3mn&f;sj@$*7wmP-*x?-
z5=^Dr`h<TlLGJ61xqv&oegl=Nd#;~ufTY*@%I9GB==y84eDqoW{~TR+T-H?=Z}B>_
z%uF-emR63;GRv~m%9fU9&)$3QN5#e?f{4fxWC$WdK$aqiECrOkK^zDO3NjQ$K|oa2
z`#t@2KIh(ZzUSQg{KmcKocnvsGbuLd&$!u-&OpY=S0Eb1*#080gBiQ%@fyl-SD-J9
z;phU|VMZ0DoFW*%Q4xM5;|&88q8Q6IKp}?l%_eZMjCCWxj$<TF#vl?Hi!Z>LL`FLY
zB#9A1m9{4s3r68Z3gb`u{)FQs<G2UdQ;fAHD5f*oUjxi(#@x4|k;NGOANsNx^Ou3-
zFe-X6iMb5@f4gnQ{Uo5}Gh~P0Oaa3?9b6&9@-{pyVth$!yi!Ic1<=bFp<!^QoH6v@
zu?EJ}1wgsXsH3;p6$j%-dagGxo~6=<tBf={lhw$`pu@n|7~gG%-4;e3MYLKOf$q?_
z&iIXzA2%2?mcZXO#?U2@c19J&U2ZbA(5j(>!8r}}PDb!{nD1gd*bT0mk-Hq~w;8o%
z;CdJydPv@3IHs+J-Mb8(6`;M0Fn0|5KBH|aM$yOcq#})eM#x!UKVX!$LSuk2u14b^
zBk(oo4KtQe*!2-(O&>rXGfMw~`Y7W`8YIUU+t@HT&WNXF<SypLYUsHzZSTRS-OSG@
zP2$S@$U#@48*|wj4BMR<G=|o_Ogp{VJ(waI;XY=-DWG{Wt5!pCKhs9xCNJjaAt2t&
zCGSGrhnYn6j=oIueh@!q;1YOofLZ?;MEsd!tAH86tYre_AQP)zTx-nSCb$;FlqXX@
zDVX`O03?LzM3>hgrsYL+hBCMAfoM4MDXNM+!kl>l<|CNPf-v4_=2yKiag^CS9eOd$
z4R68GW6YX$uoTY>Iso+q<~K@!B{K!R=sV8LdJm&N!Q8$aD5=bf@8NbDb0~~*1E-i9
zC~=m-<XnMbCi9DL0h7g4(bMM)Go7j~&oVC`fkrO#i!z9uV{$3<cAnWqp^^gT&lHC!
zX08bXb_w$pdY+du6G|Xi#+*|LFUpxcGtgMUOrzVklKHG2U{%b+xWf^fWV(gHQVmnH
z7&5iYfp39U$Go-$Ueq(4<><S}WO%`gOU!Z#7hPt$JO^@xd4mF_4a~2U(7VdK?gGgs
zW@sq9XlAZ?3hLLGWxvCV7Utqm*llH&Q^@W*(~I_IH<;%sBk5>kGS|SHcIMg>FmaQ)
zu>~3(OgoLYlbKH+fxE?=LIL>O%sl$qRuA))-!bf7<_iYcy~kWmZ~gns!~JONV}4G{
zz<%cX_dp&nf1wJb0cO|R5E*2y8iW@^%v;}~@geikOHdegFw-e8{D`^L3i6oQV8oc7
zFze*tMwpqDI~`@N90M6+hDXBvai(=U$OO}wigtFf{5cqf3#+IJWH)OumC?Gg<df0o
z#@bJNhdnI3^l@>s7CWJDFYDzQ0P|oirr&2D%TdS#^<))(4blCqjlO{K!asGu3vbrg
zR}l4KeM)aNUzXY%eSWNGO5xf8R@^iYf7aKH01aSq8X<C!_10M^1hU*0g9Nc&jRQ(B
zt9KeiLRj-CGjfQPKNFJ>%KADEX2Vzp$4<Z;W+hTZPdMvTFs9}R>nP>aBUp8G<3_R$
z&=Kw^)|)?L6w$2v7JwdQsc0`7!<v%{E|#@74qO~7LJbqgSZm&diFnoydTJ%GMmOMh
zO=OjBfx#qJ7VTh?S!b@G@i?n(G2MSBSbx)j$rM)N2S7W?x<W7dR8}n&Zl$qi&>Q3w
zt9T5Krn6SM0Vb2R&K+aQVtJZDvRSE7K*?bRZvi>O^3R6%XIZnY0Lx_|5RJ6}OFSLw
z`K*0(<DFyi&O!1#Ytp}z8z^9Tr2@2&^*e2zi&*8)LZ+A%o(`B2*2+HUm$JU4LZ&iS
z8byK1SxqD8t6+^#wNE8$)PcS#*6KeXS<Tv*22#UntVClitBVD@b*y1Z8(v`DrvOns
zYa{)V7g^JPrZYg7SijNE>oQARht?~sHrnAfuo8zc?5nI_>AGlSy}Sf{O{_ET0<D>K
zh@$z|SkF+fu7!2Y13ukgF?0}VV^uDPNIPo^opHa(szHT|QwM7(5EeRF?@%tji{*F-
z%x=~&h2<Q#SWoB!1-Dthx<a&v<r{+5JFMs4N8?@APD+jUvc9J?4EI<cWnsGSv-&LH
z`dG)7!i#>^vfYq;z?wqwfC1K9!9W>g&7(r_A=X_ggMY}1r?t;8%hC!DAF(Q_Xy-9&
zH)TtoI9M}jLo>oMs9<T7HTw@Jj<Eti1L!zw$vlt=);_A?*~Na1emobpw=dk^&Hjac
zbXRuY&ron<|1tq?4|~d|z;<W<a2<o#%idQ3pFG%7J-B`BKzfFGvLi)M-_MRMhJqK{
zu`3fA-t0g8V9AI5XD7VyWk3EJjehK|A28kn>{Loe`?D*%ArioTL?{0avX>o)NFaMA
zostb=|3JqSg4uu51~-JwNQR?_*hybvE<)Ke*zhon{RRC7huMqw!a_LvEEOvpVXt-|
zn&T9~{&pusBiUaiLNSUxm(m{5?5y9w9c2g8^D2fN`xHnlyLlf>#Id7#fOd@C`ai%V
zvQxf;i6r*ckI|USp1mKgrLb*I81_l_?4|HGm3^I-idpP^M<8;BojeaHXW2)m(M~>>
zJtZF`kA0o?4*6`(Yar*??(YHgJbN=mjSJXDI#^oBURDXvV)phja3$=na(GzEPD+M)
z8GHJF-vD7JQjooZy`9dcRIxb&kgR5FXrWufzElA7we0<LIHZo91pBxx*vl!uQ_ns{
z>5Gf(wJsRwCH8FEvs`9pu7`;$?Ekqyqk-K{sqU-n_C??t*~^~?S`#~XAGl`rwk<Gm
zjon`a?_1az9pGBo`>6QsI=hB0%Ny*LBfxB97oC8I?d%mjbpPFCD?W#Q2YcpmSn6bd
zKx?Ni_D{5Z>}Ct2pm>YzvJV=!*^_?*cb6Sc+0tHiMGPeGv0u6Za-Y3A3a<6BGg1N8
z&-Qu(?g87M5?}-D`cWthvYE^AyAH8W)}rwt+x>TlIEL8`&%miiZ1sm=AG6<~gwPXq
z_!3OQ2zz`Q8b{fCr~-V9&Gv$&akk$ckO?-E^mlQZzk@+nj*c=MZk!$oOzhztp_jNj
z$9)R=_HsUKfdvoFt5kHbkE44IlAav>XYgsigL8ZVEO~Jx&Or0#%%TIIKAan$LD83^
zq&wY@lidf61DvO4L*Jjn9D-s1=Ox;C9pwD@6|e(2g9eBMacb%22<9xJI7A5NkI$fR
zh%=ooy-?2MP+*2}rc><eFy|F_7z*b&-lrgaB<B|@VvFKT&>JM0bEgw%u^jJhAaR_4
zFJR&rXAzZ=By#HFAd<vM;6g8%bD|sADV(Dh(Rh-x^bELE&Kn^ZQaa~ncPO0Zw9tAv
zgJXFBgIS#2&%sbOCw3~-b2y!jjWBVB!=Zh`S&sH|z~pgUUPos>$4bYS&vAO#7)1f6
zih?SI9O1hFE#ge2-?x}kMOBz3oU8O}m2qCG1y|1bMGSu{IOE~4Tg8dm3a*;-JJs{m
zZ~|!IS<A`z1(<alYYW|f^_-=2MCKxAF{K?Zac1J3<#d_zHf4veaE?>hw}Er~8#Fd?
zxKy{&%yG5CwQHP>wB>5yY$m&{oR??^bDi@vZAfl#)@0!KY2zH9g#os6&eLk8hcky(
zZg)7Dg&=o1pZ)iLRJ|N!2NdsdbkD+zKF$s&_}0()_;qj(IPNK!nL$n{eI96-^Bx`d
zdBj<}7z&R$pUlNPJ>h&$-!U8Ej8Uc5DCcr493A8A8U;7bIY70b6P$lPN8>JT2VH9}
z+}IgV*v-}dPLVWs?p=CG?d2A)LaPUNRv19{ab*vn@5ybX(!c%Oda9W8;@+V;H*fCH
zkAU&vK0by?2;k<<2RX>yG#8SA+<(Ua7Q~%L1@yt(b~=F=!hJ-Q{fD@>Xd@HKEvKYu
z824Y=H##D@jTEbo;^r>}iRMOR!|qY;9eVG^aQ(}H9m@@&Rd5`4Q8P>&<Gv&XiRT91
zz|f9!-6@xHf?GkkqZIB>lVI>9*W)voPvvIN5;cw6MTh53asMuXUOM;a4Pc(;&PG_n
zDa*nA`Z>^S?&KLDIoxN`(0PViu^2FCxyRoFOfGkD0~+(V+g%}&&-IM}+BxoyR-m2d
zGAa9C!0n!gzC!NqK{S?e%@h$X=a$olyehakv2d-Dn@Oe3Ra~1CVAWg;J(+5_j!RU0
zP|FQ|4xn}1!g8Qp=DJYXz!mP@YBV-*SJ67~D!2L>jJJ{dd<Q_Axb9Sh*35mY9O~D&
zodqz_!mZ1KLOb_aDpR=0-IEWn4(<zd<fD^&uLPuvJDaZjZmzijUfkk(JGh{?xmPGf
z-otIDWd40F5O5)K*HZSfpF1ZEmL6~)Q5Ix?JNY5}9^^iuL;XYCf}bGykjtQ>zr)<u
z=-v2)8$1cz2si5(d>Z8@(Z^`UxZf`Y*f_W3ZHP>8ADsu-F5ae(DU#;G%b}IjZeAqi
z=v;X^4zS&Lt~){Y@KPcn;>lx0gWJzjT!o?+Z#8W(y?Jl?qtA!;=3N-{<r(PV=g0eJ
zAN)PQ3%ZKA@aN5?+Tvi|^dt;Bg!d|4vWIv%u>cF@^&O%}b{MaM!d-`XHW9GHc~59Z
zaD=D*873llwW~0S7@meMy;$BSbm_(MPSd4#j3=kUlX%{`8&FT+&6a~C@?z_OlEllU
z$4)YD1_fSHdBrk#k;YR{&Fm@O>s@F}=cQeyzYsXhyD<n$8N5Xly2#|c!vjnf@7`Wu
zXY-V)FnE@yNq~MXFRce$9xs6Q0QtN-H=uBiCprZ6^Sl$TaI}E;8=bl<<VC*@Qp9UI
zi}4oof)_%egtw^|c1wAQ6m+iQ#cR>%sOI@x089;UC0!r2yiP7G)$!I>z|sXCYaX1b
z=jmB6agq1%G(fNNO6mRA$P?^=NE7c71u~j>|IoRTYrHd*+Gyd;d4RrFUfc)JyUrV<
z)O-hTAq9^+dG}0c?Be;+0q<@HPeli(Z}IX{0D7Cpp*2Vk&#3_VcX(HS1nJ|=O~y~z
z&r70f{Q-|n=Q{>?(UeUX<guBsJH%tTz>9~xK3e$=^EOlf<q1zq;hz!SKOcgO@-9(u
zV~nSuu--T?{wqwv1kX`Q`^UZf30mKH@ay8CzmLC%as;0IWCO^4{_)Gu_u^lYLd2Ut
zMF+b+{4X0J>C68j5}<zk6ZGAK1AGltdinE>J{WHRf0TA22l>$y3J&DA&`U9x?-u~f
z5dL-xP!92Z9edz+DE}*p2!!zq=#mfTd(va}2%kk|YZ3fp3J*l_7n}x6H2(uBK#%gD
zSq1$V{sKA)7|Y*IM^fYYvRS}R;D18bMIwJcz4nv%F=}8Y^Tp0+JkDRR0F5X3IjsOo
z;kT%0>vWR8`gM#VjW3}k<0*cS86=&5=UphC<|iKk$>9I`0Z1l4<Tgf;&A&zU%Q^hr
z3aFpqKcvw2S$?k!*tz^aDXx&mzp@%`=kpH~!>4n6?@Q=A&tF38xB|Z3g2^xBZ~mOV
z{aVC-KOFkS{O{U8O8B#Ab6CnZ(s{Wuekw&;%lSPgp<lrdp|E@<|9m4vs`vxR5UJ+>
zy9D0X@Tb#ir<U(YVf8xxKlCoY$Y)f;-%I?rsbu~#|MUy!yTa$YL!p7+f1TccSNV!b
z7)29bn}*J2{y$VvbdA4s7^H<?MkhL2`A^;fxz2x92GBOXKkcX5`Tp-g<R-uS8n{k=
z(|%a$;&(96*v;>uAMF<ZlNLbV=ASu+z8?M!Zw%rNzk@zs*vp?vwZ)Em{6Fh4nEU(+
z518-cx6*T?pa04Z$PDl~DS#Q|N6Z8n;_G}M@{s@ROc)&IyU=g{i2vFQOu`61>J{jX
z^3U3#H^%p+eAYPsD>}nE!JnYxJG%rgF9GKwFjHCYZoyN3L&4P{sJaI8Zh~9%#@i#v
z4MeBAKtdmQ*eh5`1>PQlUn$D4PcWI{iJk%`MOya@=F*$iOHjEAGvh5Nx(PiW!7CK^
z@fAGvEinBA3I4EqKv1^~#9uI143q$Y#t4583W~14LZHB5{Q)L|1j!Kq4Ho=78?7ON
zg#y4F61>y{>`*~K21uA-0R@8&3-lBr3Kxv50y!f1dq4Cd1l#^w#R{U9VoIU}SNFn1
zwBQv=(H#}!dcc_&!8*EDV+9Y^!O=Lu@Cd+;391})C^S*<Xa-Cq34Wn1Te2W;3$Tw1
zI=z5>Lf}Rl-4sF4BuJhVFuucJQU%|*0VYi_<7L2{67YwhmoCtK56RPl(k}F62&T~S
zxlF;wRIQgKSXl%vTd+ljS<4aFn*nx4uz!UEif09FZGg!Ygl$A;p5U4SqWOXx+B2OK
z9HJlZyddWTxL+W+Pc<8bf_YTERwVczm4+4zX8D3E5sXviN2x%y1|nsGtFz!mxnT7O
zP$~qE=}B5Cuu#=bmEg~JAyO?^^(Iv^)d|*p2rn)OjxK`x^@5dCAahaR`#i`c!R56O
zy)5v`0=XiHjs#4DK-U0ER|PvL#nCAE-#ENz66~CTAFWw1;)cF!g6Nr0Xc7EK&-_+F
z?qzs*T`+}KNjC&PheDxE@aES~;r?qEgsP!&Q&3IWzz%^EU4fl~KKkTSmtf>6h;|E#
z)6mx=@JR=EN03JaGj|2fZ$PA1FuV<*_XNH4I_eWFq~%7xpobzR4+PKt1#UnvWe@`#
z6foKWJtT-<0hD3EKsVGKj|9<_UVbd_Y=_Jffj>ncMg&*o@OxA+buMJa1wT>JYC`bl
zdVuZ{UfTz<Td4g7KDi1@SA%mC)~tly9$}vkB;AEMl-uwS9zFxIPk12}{(1`6QBY;S
zaDv{cUP6!0LA)Kp?gZ%j3U5-f*-zN{4h$X;&YOltf1!w01_8pQba@>V{y;&jAmOKP
zg9{dZIR^6~!cG<jb6D6%yUB3j&Q(x2BFs2~z6jyp6v2xWzMT!sXkiF#dyfjsngAUm
z%qRv}tkChe38Rk_uB}4rG2t8?^y7s;(%UIfc$D7BNkZ!>z$6P74MG37@Kzs2aY85$
zh5kvQZ4%T|g`NY@OB1HhKu-yKs2Dq4c#?}Doff9i7Cu9G?+fT<3)j*fI!Cy3BiueC
zR68g{dsbNUCKPjpFV=v|7Z!hk!JHFDybN+)7)QTvfiU$=7%UY2O|>3H!sIOUl?dbL
zPAwIN(Oq07JedZrT)2!9x)s8&XTo5m@U#r-)xxJKtXCuKmVm1jK1FMg3&Qn_sV2K#
zIF0J<E($kM#mXh&1`1?c7WUGYa~gyZCqS+Wzq}5~Mqwn8CZU@4f6c-zH2K$r^;DqR
zDx9FtmR=X8DbaUBxZpY*Z4>@LPvUlA>v~Au6n;p7%TD3D&qJY0*gBuS{n{-&LV>wE
z!b@L3@vd<1T`2YnV`w>fPq_XWXxtZemtso$g)Z4Zdmwx;1Kfb{+btl2!ku>bG$gFm
zfqN)Sp_SXP@FE>Vc`W?*bqw^0Fn$qS8xfjb2N@N9Ovfh1gdRA2fq#-0mM($8U82_;
z;G&D@jTP`>w`lELaIPXgo!fR3ZKo0L5%p6d*+W!!7$)|KX8S|LQ*@Wg4fcy(SO(%H
zs-`Wmw<!M(M0`YEYe0NO%*hyppC~IDeFsFl>)@KdXyO$(;|LHvZUFW{QBEO514X%i
zfeR8<7h*8Mq6@d+T8PNd3cH6y|GbLEP?4?*;|&unoCkx4Mb<)a;i9+I7}F8a!dWm8
zA?l&`P^75Y8GTWrH>r?5T2w^u-J_zGGLRTiEft!^Iz&cVfyIfwJPXldqJ|e?B3=~3
zhDL&D)dF~$D7vx;?k9=jsd6h>6hpWFaS@vq=qE&9(^?`$R82|llcJ(F=%tDltbszB
zDANqgQ=&&JA(<{pq2N`f=y{sMEK$@Ckjxf2lIh+)E9#~12IY$0(!+e7sD^SX=S7MF
z%te8y&kv+f6iaLB645Gpf0l~WHvn2DdMOeLm7+xxXsi+quZD?g5uX;kb)u(MfV&`a
z=0m++ltM=ZE{hnkK)E8?P4Acnk;(BD^qWLQlm}=Q{X7%on&|X$$XpjKNP+$h(XypL
zYZINMh)cU@kn%h?MW52ijt-FzE%G`=Tb_eRm*|bRFtl#b@$*2rB^sxN*lp2wX%M+1
zvd6;TyCTy^;Ce-=6g#^o+R3K(-+fUHy)*hnUQ#GN5GB)-Z9o+NG(ZPMO`idDNL1DX
zXC8`*_^>-H%G?07N1~s<N8@ABg+z!v5fx})a6~kRe%Mh_23_l8q7lmIjEnNBAvqyh
zszTo`ak>E(T*O~5qx|1)vGOux_J|+*z@WSMSK15j6;GvgpoiFSAK3fEXXM~K#h+>+
zxnEqE0!c4%939T~5r0pMG+*&c6fN@;A7#VR0rBIf(dRGTNq2F8co7{uJt!8Gfdq;R
z=zb3o|9z9*e}}}YX+;w%=GH?aT-^B>GDpOpP_c1@_=jkaNb!3I&=)0shOUdF;;Lbo
zj}cc=s4`Z3cL)07#N#W`cTBvIUi9(em7(Ag#B)BvbR~+9P+&PptfeP-viK}LnNEu@
z(^J}!A)ZBdT&6gKfz~Xs{5Hm$Enc?{FgfBdDpEcp?w$clXT_h>Rw7sY>vQ1p#OrA%
zlP~__Pmpusr~sgx7wagBQy~8S3EVCe`_R+2NIXVwvtseCeK21lZu=7=rD6lETgx2c
z7%E6C7uVl_Hx=Sv{c$B!id*i&M3q?44~=T^y$xur5g&?%hqdC9;gGBov&+zULEL^G
zlJ#Qci$J+7j-$haSHypX!O;fs!d^5siFx!aX%-K=LgAX&Jr|8F;`S1NwTd0rs3PgQ
z_}iypsa<@TinMNu-<yeHcZl7(K|00l_aWLPelZC8-QrT3i(BI7C(w9X9C04lJ>qFg
zVfT(WpYEo+;^+XF?-g%ahDo?5_Mq(Leesn>DD;U}{shT>adSDy1F_ygpaWvxonQyW
zr;bBrNW8rs&O8)vh)3VBcoU@`ABk^057!=xPnH7oiTL3ykP-3u-RK(?*Hij%Ossy0
z=^hs!S%48vh#RR4W|w4)>b6}Zg*9+{x8!{aM7T=QX-eEAU6<(o+aqzOTg_e4T?xB;
zCCh$5qlYAcZmxZj=T^Y3rzHFuOzfAu?t?}z$*C$ddP~%_zVVTa)86BNq>@Tq{3SN}
zI6{CVVI~?6O0H2se4wPB(&#}Fvjot=l6USxFGQl)<+Kvdb;)c!*icF09*BlX$_~Nd
z!xFETAsQ|*d<w-Q5_2TXM@Vi_iZN0m310gXYL}iqkG>emq(jh)mCSez3dbZ)uJ9sW
zGDuJP1j$oWq@O5hr8723lBr6}+HuK~3G|(i*z=%}B59@FdYYvBEl8e{G}6N>T_T~M
z@U%p00hb~9NrJItN)AyvElZ-f4ZUm$%b@^hj>MJ^#WRvp9yHEMvKSD}m8_-sSf1qg
zWQgWVVwPb@=OlaUVg9^i2L<8_Bn?z4Qz+@ByRk^}I;DP#CEOe|mPmB}f|N>{=sjO1
ziDp5sT=F^<m{v#*Dj``ZdH*QIuB#;RCm~ZU`K1shY9tMQuv;tHOuMQ&NgVADE=X=%
zgGRk1ffm>oB{GWDUy}TB6@8Z_I$v;CC0|g8rBTBFFUl?H7Gq@1k{`~X@tR}~U6n18
zZz#&vDrx!<vwd9>{2uKcZb(M5V5v=Vla7wHOC-NwzB(k+pTd-MN@7Q#(Iqj)qVJyM
za6ZU=Niij>`Xo#lK>H<~XTd#?9H)b11CmE1IViDFd~8TknFp|k62~f#VM#tc7avP@
z(J{6slFfh6xvmjO-)XdtN=%#3IwpCa!bangRg-`{A&H`bPZ#Mz+U)F>&Rhl<SLt#(
z)a@?y?1H7e(nWLz%0s%j1>8RAzf-|^N=N9p$9}1_39flbYu^CpE!{{Li;wg}+5`Ja
z6Dc0<I3PVo#lHShQ#fP-q(wCt#X;#0|6ra2rQ?aP6eJa8047-a;)gJCNIHk|f1%RB
z{m>7SIyFP@uyl(8Zih=VD3lc;O{coeNa^Hks7Fhmp_SKBsh>ZlGDez270bt@t}CG)
z?~q;~{RHW|l$K7DnvcNJDJjDjis{muQ{csE>0C;pWJsrvqA^o?j-I4B(sPt5I3xXt
zVqj;bd#6G#SK8eO^Lf%Z$|U7Wbv!_ylOA6SgXg6WDQI0F{i+Rmh0?ZPp-?1s%x!?(
zVyTKMDoUlLlb}&1-831Z<<eCY$*zzZ-iH^JQq5sV)<~^)z|~6MqxWB(v@Rap1!=?=
zK&zMb(~I_^^b(cxUy|Bs-*{QtzZ!a1q)ilvYmm151%Izfms8}TQF_}E0oo+hQlhe1
z>P(A|Yf{HmxY#27q8N&;()T|Cxh{Q%wkJ2Fd<x36NjK4Eqg~2BhVkB%Zlc9uhqRZ@
zfp$velqK$xCXd03Zt4E#0ewsQ=W7tTEuBSuJ<`l6aP5wCzYoRE?n+M<g6)--(jxqx
zG^G`d_oZJYgY-$~P*lHPx`qyxJdjQq2Izp)sT-CCr91zD!jM$e4UvaZCwh$yOFO7;
z?U9u01Mac3^bSOxNR#PrwML}r68sdS(j70r?J=pVE8TzN(j}A$o{%O{hGm!RWBO9c
zZke9qHhW~Btwo=^to6ThOR^Wt5b=<GMM1uOvg<p6<|)hahsb`}kvb@N$ucNz>MhG@
zgn1uXuRp+iWq$NkH$PbumAM{}NvDGN%YGNprvn0Hr)B{(Ojbz0(_vXG)f$J(9;}7T
z5!sfL(2tOPNL%7a*|Kjj2~n~F`YEGj-&02Rs4Vs(xENUvZE0g=)wBqXldYlK|Cmfd
znZkIPit2+BWX&7lZ=!4|ZPAis8!3S3NS0}m(0N?;@n3N9glz3Ba49l=7DP|VwvWSn
zs%-gDSW1%(xufrtjP)somM$~W`}VZ#S$b$@$nJJQJyW*D3WHg)f_K4X%RZz?XO3(h
zg{RNRex-_{v$A|zKjzAk=?R|akO>|EJ6|?i2GMh}-@icXd6{}EOccmUDPK}38=xIQ
zkt~%3kz(2HgYc<D=KMdPmB|tx0lQolO_x`NEczYTt&~j~M_-k!;8Q46%XDj@P$Rqg
zBEV{8UR0z}Cwr$E7B0vf&;AHnFMI7hv|f~bIvM(xWCti7(I6|QK<`!AN{ab4$}UZZ
zi6)s+j=pBuy+Dv_vdt~<w?($+19;IY`$&PYT$g=IwV^j;(<x}(Ci5FaW4mlJ#lvsP
zHtdI9hs=*2UY)Y}4tHR8$%1H?(=GesFTmWA^`?W|mMLC>-#xO1H=%JywqXSt@5<(V
z57H}}`63kV$@rf@{l3hN(yV>59$H)W%l1(v;RBgBWzGg<Ji22BWrt|-JtRB05MDf#
z$!SQ#vftJ^AoEC;Mr*alvXr-A@QG~IFEBVF<5A`0sB9aZh#ZscrL@bqYz|cdPslpz
z(6>uoPElW1xo0vI+~hAuKxB{n8$E{YA(vBu&ptVGGKi-f?^4_q^8T$LKJr|5c<(De
zs;2+#^pm3u8n=Z!dm5bamw(d*>;QTAI&cT&G3ay(lxNWjEJ&VC3&3Fcw~N4q$QxHd
z@{s&IRab?|g{OcLCXf0F(|uUpOjX$7@+q{2KO)bdSYL$vTZ$1z%KxCtBTD`nBH0e7
zXn7kw*^bKj^x}(=pP9gX#mc$QK`~BVmWMGNlRu$QNxVFgPBtdV&wmOplI4pjl6_qM
z)eSgvQtmbtpsDiDXc?F$pF^>}Q}WAa!KKSrYy|Xaxo9dHGvs?-hNGEs-5fMJvgB|1
zpfy|mKOWF><o_%M_8Ivnr2suEU$qEauH0o4NS^#4oh{0j-=v+_Ie7!6AJ5C@N?^A@
zKAFChQYc^24eTQM=i%_aSnipRz7qL{(`YP}S5AU6W%4JlV}RxIHz>tW;gDaX$8@Fq
z<6R(CawE+}wcLXqR5fyD4D4QzUwZ*)_3~T}8ZXLsRMI^nzdwP-%W@4BR9ul~(YfSC
zc`<E0n&jV8BDh)pej2#j^1XZDMUVW2pJD!vJd!fycjX_`+pJga7)rw|+>^gcE3o_W
z0Sj9D<oYBi_RHCu;Nk=M9EyAl$Tw2i&Y)aD&$%J_CU2N{DF2$OVTR=^F2egq@_cgp
zvHV8{^q$DCuLAUlyoQbmkII$wA{djG$3SnFVg}U=x+we|aj?5vAq|G2tHRqKt!@hU
zJs^7&!voN8SIn0|WUt~fRWf-fS}Cr!PhnmN&Qmd71lRT}4pJ(}OVQZ|NpA(4GC@9y
zi}ZZ-Rcxc+lb_-ZdU_mCOuYj~{T1)i#S);%=Q;p$P;u@@hz2Sy*MbXDw9=guthhp_
zK0*{7RJCwOku(aJP{r-dFcGGh$py?|h1L^XxMGw_pN=TbdO|NkQA&@=NX3&sff=QE
z9*aDuXvGY=o{lPtHh_y!{7H|7SjDC<=zpu@6y6lcJEnMr!UOS&s_!wF1jV^_*iBTt
zNE!1a#f+z+pR5R?b^39Igkm!%6xOwXNl`4PVw{r-U)m|AD#j-RB~1}C9psdPMUlUB
z#Z#-{=xN32a7bn-o_qtaOob2fN)D$ig%hPsvK5)Rz|K*)1%aGV=-puVtYYa0fXP*S
z|0VSE6w@d_l&|<Y917<YYYw3CykhnWfEFlLZU-q;eAWU|q&P==*<wY^LHyb!3TG!^
zmMUt!(O9OKPUXGjis&XlJ1P{9=R%`WF@tI)s}z$dKUA%#qWE^5;zP;`Tu`J?@}^$#
z(G{RwR7`ss3YQcIzXNw!abPh9b46jKO2P)k(Y+Y&RmF=`;@PNZ{}(2j6cGmi-K_X9
z5slXr&wmN97R9@pG0m+G1(#NbZHn@Kbhay+|9eX)v@ZayL(xd@&rXHw3-G&3v2F#p
z+lsv}VK6<4?O#Iwj^aCacyUjmqRr%e#TbQl`f#nHZ$M$B5}84TW;VDXh1mpW9xBFf
z!rx)VYYWl$NZ}C80{d9e`8TkiDAshtw-LpfB*2U+bX0{prg(QcTpL$3ML}aikxTVh
zyOghg1G_HDX4+WnR+iAx%T@V4ojq|=O4i|r*{hsK5l0VY&`Id+Q!YG>A$cjis20^*
z`7)gs^igj6?|*ZBmA_JHfuC}30yGXNs~cg^U#UC`O94tH?KTc7)94s`pz;m}`a#Mh
zTCxQzxpe7-D2Lxb-yvn-C4h!1bDF?~DW9S5l^s@g_W?RwIfp(@5~+;)0~Vr`bBs`r
zRu+mKz>ZaJq$@v8X>tNNrtEh@XS_1ohM^@WbDsg1sQjl6T$0lL87L$x-`WUE$CW2`
zVN55K&(cYl6y*vVxRc5yzd$5adF4x3N>k3IFv=<A26`5yE8m?B3#XNZ6t>M!etV2+
zC$g2Qa&+b>-}?^ZJ)^Y6L8d@Cv<5>fRPyG)Qju~_6uc-_mOYKe66IHv&ni`pU4UMh
zvRMFw<;wJB(5q0MUkqm|l{+YBRi(_jjlOE-Bv+6c<zgO4tupd27^+jA`GmfodO`VW
z3b5;y^@l+&DyLDg;}zv6^t@?Mrd<QfRi!->jg87#luKz+?t33TH7gfVnEIMh;sl>s
zlou%&+p2tq?y)wdpcbTEsSd&<+*E%27bH8BHIxnSRK7@AwJxQRN)a60$`Hze+*0;O
zgT1Z%VFGA(mHB!o_9}(HW1#nx^^}yjuMDH0b)VAzbtv>Jr!&#`KxvY|wE^YU3K$$z
z9;H<3uri#&D36qDmV!K1zIzjTPn2F%jy$52(2YK-G-W}3%%LpE0UcMa-v$>al#3{R
zxLfsY6%<`nztS_`O_fMTulK6vNzvz_8Xyn%sWwxMrkAR02#$KI9?`Alqq@KXcR*D^
zyDNXya65(+pqiEmpMq4e&!I0^)$=K!LsU;wtS?OED5G7@Vb#m@iVauYaf87aRW=72
zu_~udaB-?Nso;*O=5K>Yyz0#q_?w{GbO&gOs^tnelcdUf4hEA|;W=nLuCmfb_k`-T
z6)>NoIyx63CslvZXYf*0kEw(rP4#&<%%4)d>o^DV=_&?AY)-3Qr#Nwjs@x1NQ?+#o
z3}&gG%YylA)g(Xk<)|W9P&lK?5CHV7DsnEkTvgh9DCDWi_QKzMRUeUas%SbmcV6We
z4u1<(x+ri(svZ4MC{|5!f)^#K@JY1(ELAnS0<BD?ql9p|iaP-P3RT6snDt84KlGuC
zD%DURB&$__?S_7hD(5x0R;&7WJ{s#(#~i@EpmO^S>h-D+ITS9cUZ$#_OR8V~h4}{6
zUo~jFs`8__SfgqRh3c=VlE0(%XNzhD#pPO63rVz1HH2lMQ@d(-0OoJ1TuQ)osA4|_
z*Qpxu1WcFe3`O8?t2TTL(xXz)HvNt&fFcO@R4o+azpwJz0=+&}q6B^Ys-J1~{6Mv6
z4%7!!5r@$DP;~;)Ifv7*it#EGAE{QJ02xuuq-E@=s)UkGW2%l(xVB5pqcORtOaDOM
zZgq1Z9NnXS^=UM^t5a72d#`#UrNcecrzqaEPrW1tBA)6g6m2`8UV9&X{_1{8oCl~s
zrLgTmbuv{aIs(<d&}AK@K1A!@VD)=%!u=3+HPx#gQoqy-(NOgXiUfqIOJ2b29afh|
zf(uta@PIQ%)Js;v!wB^|uc0qe{qJTt6Q$O=gG8$*vH*QleKrz(G3vDx42o5&sAeio
zT~42&Jmyf>Tta8OdLu;_6VwTBqcc$*;Q=p_)R|XcDOo-HX?S{E?coGVC)8h3DMN~S
z=kvfmseb-l%w?+jo$1g^Q%_Q$@07Yc09?BII$fQo)wia>nG7}a0=P`|<TC)vQm6X@
zEL-jPI}&c>sGm9v^JmnxnP@$$j;(@zu6izoX7kiv&`Gj<wd)uZ&#ChY0CQgb?5}7n
zP!G}23e`&~(_W;0PYteEJw#8-5_OClxKj0UT7#6SBWc%Nt}Zx-#tL=TdNfw5xsI>#
z%T%c+`@!#O^~G+;)ToC7;6<(4gG#UJ)Sd^xT~zO(1j{A$GxWT;te!!4`c?G|FElo)
zPk#r}q(0jQw_DW5-UUjldgtHJyRMEBp|M@Pb_&35steSx+o3*12XMO8Q<^FMc}sn7
zE4;X^cKr&VJ?c~+$lOtXO3&rHYCpQSd)5D=4fZ{CCv79|tG|5>)77VbHVQEP>aSnI
zPw_xK`z7cNs^dCgen`E8o)-_*lYW8SVfFOYP=BOeM?31r>Zjj=!V~qXZmL}xQUCoi
zI!D#IAJICdZqPt~T>S?9Kojas6#UwysXu`}7tMS3(70Rk2E7(sHC|^y+%(gw;Kd%z
z6mRsoYmycNY_G;n+aeFm-?yQ@PZP|BGoG4RTL8UZvn~&fUK$yb)}P**J9O^CN5kR4
zH(yQdAt?H3w*Lgt1DZc0(de&nqCiA|=IGlP%t6h|uc0weQ{4zINOPUiHNl#tzTiSM
zAI8F&LmHP!5DC=?-h_u?n$goRe^{eD0=wawu^KpfMDv(lw2lbP=S2{W)a1>F-6+j$
zS9C^eZqS!Cj%t3N0}`Y8?E<i4H344%J5JMd3gnn3oLr07G|+P@LDO;rmJ&77>9wDv
zNu}pSvSyJ8<haIE0O%8%*S-Ksie}mqICD~S<0j0fIy8Hz7%ojC{{?8LG$#5Yce+MK
z(f!k!j)Nc>n#B}|$ke<}%d0GnF&~z)HS@j!c8<nMb@^vB_l~0RtY-Z@aJib6arEVB
zhA3Q|uVK)d_MB$L2;4re`Nj*F1)48u6<errG*Eq0k*56}bQWur6Y#A>^MFoPmTI<8
zWVuYUjl!Ab8t1p6QK8vH`{YVZNDv&Y(j22_QMJZFud^CWqCc=}HKQ+MX!V+pg3x$T
z!&nIJk|u%Tyq7heH=%w-vz9998#Ip`R3&^>lduigjT#xn8k;o#ev8g#&0|m4y{2iQ
zvZ@x1VGFocO~e!^T-SI}jq?qSeIxYRG+Cd+Zo4L88cf{OY-T{cL$iWn$eo&}Ud7~h
zY0kJnuUmtvd)#oE&K*#=tqGk%xuYJ<tPL=6N8_{&igz`&QLxmjdG;H~+|%q`1Cje0
zKZ-N=X^QCk0{xo5Hlp!?CW|V02Q<%nKypxXh8}lAnhDyGKh!MS3z1>XA5+oyNORx?
zkjI*h*P;GIqq9JAMB{Rn;-90Mr|FR0nC2XP<aJzA^D{apG`|t{F73O2qR~bB?|KZ)
zO}ph^^zG4>a?t3m&29tPt6lOI8a=dSWN@EWLB)5TT9<|JcfYolPW*Ujn-8MVTbn>P
zvyXPp3V``)7hRu*`_E5%I0Kyrv{&d__t!3>BG>?JKZS@6Y8RO?&w<((sjxOk`vxVz
zgSGFlAQGZ=U4Sti(k`MXU#Qmo3AiwAJ-zl1Yioy~9<J@7kCq<MmKmWCq1_P!3z6Dx
ziu^}upQVZ|N3?bw=^xb!K89~G+R2nkjn%fzL1&z{<Q9IzW7-RJwmn|kxB`s{+6^_3
zOw{iA8qOqX*VxdPtPP-x?YP!NPtp_GE41fH(YmjPGbgpr(Qf~g_7JV((zU%5gFdYl
zH-pP?XwQ(}ncDu{a4}085(k)U?H`i?nxmacVe&KDAS=+$YJ<LkMy~dUVW8z{r%}TG
zy!MNaAyS~7OUHQ%wPU03sYJ^}Ri;y^_P3J|Dbp_LfO@4icL3^D+EI!CR%@MTS5>EV
z?4%&p1+8u-K<l-)=)>Gi+DZ``o3%Ogc)zBNJ`S`N?STu>Xw|Ny$j5c<!ZmaQXn+3&
zj<#vvp~GhF+V^NxcvBlqd+-kJB6{3)YFAP8w@bT42GXs4CKDpJv_*7G^0sz^qYJc0
zdpH-JceL|=huyo{JgN)s)!yb|O!u^A`r7Gz?caA`zE2xXiJ^Y&_CdJzKx-~W<AB!l
z4WJBaJ&PeZq<yCajSsc8QlJcL2lAmXqE*m^II7j2fykJ4HW&VmYhOO;K<k9|?g?n@
z(tS=<04}<@dFb4&i#h<G+;wN^b+lJE<sB$`=&C6MzE77%uN+U^k92fqzb^PGnD^3+
z(T>ksCt8C>U)`MLAbvUrowq-r`}rJxUVokDC{O})_qIU&pzc-%o!t!7eG&{yLAs+w
zkO|hc%|~a5PVhBIsBQ{9{K9neW8vXpUHox?hU-4chfhazUp8WbB6Z^Dp&q3hrp$G;
zE}Wu^F}kD}j4W37Z3{@8ZU(*E;&m~*fs&wmfp!^*x}N2f|4Y(EdIBa{cd;9-DZ01b
zhyF>OH$`Dnb=kCDPtzfSgDY6~qXZ)9y2W&>oYuWgS;!3Cyql2B)VbUPm!nI$iV>dC
z&AS1~v%1fwLo!$A{RK##ZbJeZ^L5+B@Zy|q>mm%oab9<m_N@iFi54gp>aMOsXOZr!
z8}O-Ew|omUN_3;Y!9=M}@G<(zbk(T&a4OgRv<^e7(9Ne1c%@GFA<$}c0VD9DR+pau
zQm124CDR3+Rtfcb-S-q6xv2Y|f_#^BJJQj3*`Z@8p?^i!^8s9J&>f~l;#FPldWbga
z+%wSEtjnPDIM;Lzx^!D~#YT`;-G%=F=DO~GNf5cAn|%#jo9?GS(ATazbp_tv)OoqU
z!w%hcHY|1OHr+;Jm+na_M7nhwVxV_R=lJOz(A&B&6Iy$8b0`jZNB1e!n%vdJ97bQS
z?srNG-qV%rgHQK$rw)NU(7j&=GN8M|hr*z4zBkMd>t@rY{gLjCIt=2m?*4p`C%Owe
zFbN~N-|4a%)n(9UBqnsHodLZ|Ki{zeGA{b2Sg@}89p8bt>2o76dwcYsku&c4&9rUa
ztKaoII1l|T+92=K|L;0rJoP>nDD2m})4Re;{|e<`z4f=B2Bx2WBLyc9=r>XclfQn|
z&maN%SNq|`L46uU@B;NyG!%ac(l7o327~n@bj^k6hiKh=NYA8)NvOWy189WlU3Wp`
zu)et-a}lmjbBDnr`s<sa9-(IpVAzp*@pDj!(%+*hm}vd`f8s|ws$a7b<d|Mm4)u8b
z?rYFX(66T)YNCFUJH<bf^c&AXKUsg5Viw2szn+5^C-i?&vN=WX8w7Gv?;H=2RQ-yx
zP)yUCt^@6q{w3PBrt1@^B;mCFvu8ju^zQKx$<$9@h(ToOPfmq;w%+d=6ms<1ov?65
z{{gM8&gwVpr~5Bg|0}I5^7P9ojhL_hdK$<%eaQ(JJg<M6DvAp9iz$y+sNXmpjYazB
zXc1nl*Pe%o61_|ee@pe^XrPqoCoP4+a{aVtFwhEpbuCDxzJ&qFD*cP}8L?{pPzEg2
z=pWD?%~7lG%>=E}&!SiR1^oefrqt{EDW`H#KQj;Hl71`?Fqif6m*C75J^MTc+Mqv{
z4eqMmgQD||`a7S1Ytlb@7LGRSE5e|6O@D+Ivn~2k3eUCbW2sE`y8eTIVc~}UMLI>;
z=Fp$L3%}d-uMDB}rv4B;1-kTERD#j1|92MpZs`-gMB{D!5*9>y^uF`acSj$d574{%
z1}ZP?)$gWk#yx%F1q}4QK64E$_30Zm7*fCf3Y}nkpr7>!3IqBhucL8LFQz=_u-?I)
z1<^<PeeLLctgoV&)D!&<GC!i<MqATSeF+s^jOnKwfHUKI{Q^i%=o_hYf0rSIer6ZL
zWD2hAHat8I5m&=D7jSNdm$RX_*D!Sv8a)i#L!hwF;6=mrG;H^Qh5ZJeg9jNe!^SP}
z!rL(SX<+*p9)AhW*YNEW!1x*NGT_qz!?78#<ZqZpmu`STJO?lb4W)Gu2{e2ygh-HK
z9z_R(4PBI>3^6RPMBgF9CVC2l8dOwH5@yJn0egoHb0`2AZuosJ1wxJ(d|v=slp!=3
zozaF-dXyeDoPG*uF@~ch5Q#N(bYQ;X45Qxg@R)%?tM7Qj+${i2FyzgKNTNZW3iTv|
z4-1XShFOuoJZ>;jHsXX~2So`^8a}XsOEvTz0+(j+G1L3+l;HuL3Q9LzqzOK4SV}pO
z48u@8NTy-21)y1m4@Y1k+i)@$KIItPHiFAF9JmEX^9+J=H0B#>Xx0l1tJxrhhE_U7
zUu5u?VxYx_Z`)v@#Nf98T&W@DzjcwJ_aNop%MCxVF+&xGOU1BMX&9$WR+V9xVjb0n
zzvwVUjiG=p@>;_c+LP89_C-VCg5fw-uhtvB`~~JO8eaJt*q00iR5Ehe;583@R}3FT
z0j$B0h?TC>Rm1*S=xa25J0BC&WLWhsEI67C^S{Aht{HC30(OhRi_&qehTOGq_`0Ep
z=Ie$bD-wNehJPtE)NUyI1PV6|8T4xJFf`H<rqf{C3G>~CuFcT9Wmrj%(A$O!^m6Gj
zyg@J1JBF|15V>pU??Gd)A*&RP_Z)_gUW7OI4b$yt?K3pK1jT+s^2>1ef#ID3$P5@h
z-3l^j*h*x`P^*O(4-Ll67|gKYdHPP`Bf~I#m*lZw8|^!v7@F&WGGcgqADE*CHyIko
z3<H!)88^gN0D8i3XDb}tWpw=IiB=b5?jDHlHZBc>qN}ls-okE1CawDS7@hktCGN(w
zTJ-HTKC=nL!`P7m(0#_-FmRs6wih9?-#F9>;$^JIM=6}VjeLq@_!uiPA>wPyqU*`e
zxR&xX2aKy}MelFycKizS0Y(EQ;0_w2q5v9b4B3x?1{s}pqA}R0KLL#p<K}u`A2O~v
zh|z}{<rFmzGj@kyFo%tKt<VcM=28Ujh|!zUTM@>;_dqhzSVNDiC}Z)z_?e=OulfS|
zsPWuZh{PEGwNT_T)|fL45@-CV9iqpK{KN1q-njdFfF>A~lyOfqHeZKgl5u-28k3E(
zZipN=9{3WVCya>B;8kT*4g%$*G0+u#sm9Pi%wd}G-cRT|W!y0g=yc=WRtz`OxSZbQ
zS;lW3QT#L8sNIdu9HUPXG|m{m?tsQwBL~q*r(EM|n*2QDj!)2-Z+tTq<2`5G7zl;)
z#%s=Srog!FQ*edGo!1~zWV{~)^TkI02uPL~heM%WYK(ag&}GI(S8(OVe<@W^Va#r$
zZx>V=gFb{)RmLCuL8^^?6u_)8KB8c5t+8?pjde!<*&r8;uJmiw8*dlD;6)>67ff6-
zis?mi*|<l8#w*5hs_tqqJ}8F4tHvG2(AQ{OLC^Chqx>-Du-O>#0FBp-(SG0@Eyn3^
z!>QHycLT_E;}s!XykR^_>4Y}pZ=2w0yRqF9KHW49`~uJp<6|qhPUGTZ5a}`|y$!T(
zqs9$=w~UhiURA~wVG!vtvQI$dj`8+(pxiae)4=r_8+~Eup0Vgh{I2&M#_!7EaGx=F
z94_`7_g{ed2gaYC#}71MoSz78&{#_KO+&_J%B4Ou*0cj=*f^63g-6DO*${bb+)DYd
zC&sxq;LM0Ixg83l#+NA2J7%0mrR?LzI(JA;7+;`B_%73vD0tywa*R>6;cn9{XLP!n
zyl73}W>U~HcCYEnRLFRkK6npgpD9WOhdoUaS9r1C^yOxF=w+Jo3L1S)`>EK<&y++@
z%LAs+b?7^2O8)^q1)82&2+SZ;O${1@O><NrA*Oduqw$bwieo)!sA=;n7)+Sy4LUt_
z*fdBb^x>wH{SZB3TCf8m5vC96B@u1vrE`u)O#!<h5@Y&^N<CvuJ0rlwnL4S?;h5>q
zpCOWHnoVCoNHTF2043S9b`|<kOrP9D<4Mz(9pF+;#Rf63(@j-f&_8Xu`8LopOxxlh
zlWF>z*4tSoPm1?uo0Rt;l4H6_34k*uXDZ7&Yf7GnzFZTNj$7rKrqW54d{aFooeE5U
zQw*!nlpQRxJ^h;FcmU?G($qnF=qi)XE?B5Gbu>e=#x$8e)>>=oqzzx4$wm*D3#Jd9
z!PT1<)1L66iKD~(Tr#OyXuNEiLxGwG)AaTDm9Cm3OCZu{DxtSnlPPlwxMtG`1&FSh
zW>YGq#q^_N3D{N>XB{-Io6au5SZ<guJd4JgCe~V*?=a1vTJTQO??>QamnoaBwQkdt
zN8oOm`UDW^F<qoJ#2u6Waj4%liD{M6YnnnUihCwE1sd<0R?_;Q&(upNI{Hn16cc@5
z>R8}_=z!_jOYmmUlo|nU$TVVv%tKQV#e{}UU9-VGGDW2W?TM+9HpnBUOxin)nue%s
zXUue!PLPe8LZ`#E3DdM+p|Hz*^$qysVt!&l<8Jf%zo71FekBmZ%`By&y*=i!=je!n
zyZIQsclVkDX`A3-ek&eh+Hc-O4+<}H3mxw9Hutmw#?QR|8*m5AdqQB>-`o`gy#Vve
z;b=T)UUU>(p!uo}T!=Yk94Lp(uhX+H)O?O&6k+BaeQ@otdEqgrhnt5{{OWKzV*cZA
zXhfJ7Qu-s(EQ*8OD0BJS7*n))+kc4?GviaZ7Gs__3KDB>p)F#Z`3EPU9W%#L<z&1$
zITRiyn4MQ(gvsVND93%=JS73<Pnf?jfuxxGgupy${(=(qspgBFAdYl1hXPEe%|$tY
z$uJL5m@C^nKrg%;a|wMs<BWOWB^W$weoR67T(g`BfAh><8i3}TXDx>MIrBmV(9WAH
z=|j~8X6`}s6`C)5gDWzxei7=$W^YQPm6&z(SS>Xl>43d5huQ0Sm?$@Yeh~T<=5>@O
ztu)W4C~TGayWfCaZ4Q(Ht;X#B9nfmclNJE2&iodYD_k%ir=3r|dD$g!7tJEty<Rcj
zT?)wt^ZGj&%T=?QB5;l7_vw3DP3FZOkZd;p&kF;*W_CE1L8HaImm*88=4L(6uA5iU
zbl)&Ps6b<zSz<(EySeo;6mObmQqH%-{OTT{b((eb*yu7Z_!5%c=Fu8(x6JoT!QD11
zDlmv1^Xca?>^tWE9t``g*)$32z2<v<;O?1Oj#Ci5Zw_*TH+|+fdIml)uXIA^fZ3@T
zqJw7bcYql(S5P6;Lvtc+Nr%nTdNHO)W)C_~_Snp$du+t~vk_#}Tu3XvF>~=#P#8D&
zz6<jc=1eCT+GV-?85&(IQ{IH0t7V2Wg_+$fx6hz+k7bGryl}TP)70#>+@}1Fr=`RX
z+<r@)5t3dOUs~LGTYQfK)W@P{VG?{TCkJ5A&+<<f`VLqubbQF)a+TuY0hUk-T_3a@
zc^ei2Ei;pV8DvQ?0W;Y0Sumw}LM&TnVoZlDesn4>)RJ=n!w$1-M-a;CuqCk!o`ze-
zmg5&WV)^D2NQA}JANrA&jDO)%l%=1(G7xQPeFy4CEm;&>iLo^P0F+pZkse-gmZVca
zIcBLy1&Oyzc><9HOX7#mJhj;=(efN^dyiY%-UZqT3*#?fr&#*NA#>7lIRsp)rQ{`u
zq*>yqw(PXUL6>fZMcocA)ADv2`m!uuW|+^mED2t_6Q?KMSPh?YEt-0$=UFOug5+E7
z(_yi5mY-tbQ-P(OLKTIUmnouKWI2}(*NQC#JJDETX{PO0sYMeFQf8@L1bgL{m9+1w
zv`nEyQkA7J9g@|S^{=C`#v<iGz1H#~Ee7i>sSfh~f@ShqwANdO=RxM8<pKp`E?GFg
zfxB!;_JZ42EdShs+YOcpN)cSOJW~k0MoSQddzviHRNK{T8Qcc$n&nwqf3;Yo3!%_z
zF;TtRbxZYQO!Ezkg(AUimRPERYqwmJIAH0fWrE5-yDUa}baz|AJ)m*RlDQaYJ(d@#
zj_QsDp+(#kmI4LL_gc==hTxuMGv!e3TSULWV4r0l75?{IhK~XBfo1-e5E-x}(6PTk
zi*hT}hb;XLkcXCUs4(u4#igGvtH%~`A!hc8C4vgoMl30`bQ!hu;smzSxMdo}KPD^(
zzl6iPtaE9B>tfyYCtTZYWduRe&3dE->U*r7M<C*EO`uoYUaNqXH6GT_Xe+zVI)}c7
z;%S{h%iaCf52zBz%Q_DiC$fjuG@2nF>)-Sc^0od-sSQ7?gVLP`tTA+p`ddF+4UqtA
z4uz)=T7xO16KIX|0tvFdPs@u?>qUIW#3{_WU_Z!VtBD?{;nroY5IJJa`yT2M*05}-
zM_LzAY$M9LJpg@<XzNEJ7(8lqI*&2MS~pXiDb9M>3ejU$eJ;F+x3+%^(FE%g+Vv({
zH^!hZ$y!x~5hhzVybZMD)~x5Ce!^;sfccZwT>|K(T4%lpku>Yz9Q-h+ta(cznQq;-
z5@4sTZJ`j!a9ES+AWf!KnhZ9}`pPcAWLsbP2#Pt@2R68tYn?*%33=88y5{n&A}UEe
zXPreC)OjmA0D1-1O4=G0T3yXhFS6#DF#2Mvjh2Qb*709qx77L+9q=o&mV64X+<Hd}
z=nAXj{Y}uQwEjR})2y;SE(B<`b^cXwHP(!W=&Q9Zq$NR}^&i?TU$AbZ4NSeYr3(5N
zt&hZzyksr^3D}pdA5${?inW0@0u9!1D(SvzJwofSM(Ypv0M=yv=Y2TZY@JRa>uXk{
zgNn~vtbDq3Z&(xP_(GfYz(0U#w@%RB`=*uIhFR~hUc86CPU}|`u<WvKbH+S(TYc6*
z@|M+*4E5XAWU8R(u`Z<b^&RW$ba~vhuK5h4*DCmLk!77m)mZnfE;oVFXO&K;=xM+8
zQ>r+5V7*M))&Z+{FVF_9{17M(StFYP`q1kAKZp!lO*EKC)@<4gKDNHZf%zxa01Bs%
zSf|pqWYij80Fg0kI~ACYTfOPz*@X4TD9A3`D>H!NVmm(v3cGFnAJCVVU2U$L(CTJe
zLT8%x*qkXu;%<A3f~fm!Ov==G+7jP@7yE7BG0^B`+eW2J-Zme)WPNOwLHO%y>*>Q-
z{A|Kha0hHP^oI1eslC7j*d{-Og@d+dE72HeJ2e^O46<#*`_|zUY%8Q1pb*>VKcMxH
ztz;WWs4eGBSPHX!#KWu~wpA)X!fhtnWE`<|p92?Rn?Z%;k+ym713Su=LSd$8+th4u
zM{P0gP>-?Y=VLBnZ3mwQ7iYUPguY`o3sr2y+dS!+?MSe_ObgHBHa8X66SnSu0Fz>S
zpY|LlZIx6;nQGheG3=(<6mp=QvW?M7Cf)W?54h8|85hB2+J2%lP+7K?M(AbRR{spW
z92<k~xHGo3wBI{x+y4oEkzCuJH(@W&wv_DUJ8Z+W=s9P*PjQ#?wnwX>UtoKi-Y$hU
zH;R=P**;&3zEay?<!CIkRsI5J%5D7bVYkXQMyHReZ8ln(*4Ps0>b_vppM#}(oAf;>
zT(tf84^XbyCQvNl)L^S8^H*(wflz3)Il5{<n`}PS0ByFtbqg}rZQoIb@rLb}EkJ9t
zRUicJ)NXr)!lpNE<@Aem*wSgW-)T#rHC~tP^L7~Qw!N_f<d*I4sqpExZR-g@_t*yC
zhsYfpKL-<g*VcR+BE7Z}s?WJ+d&XgbrTeyjJ^^T-?cL=t(Qg~4(xnHsHd;Xq*rMnZ
z`=D(-C4z@+U(+7=p{>&yjl;IBv_F1in?wd5+unEr^28QMWsoDb5GqI*wGB>(g)!Sg
zN+OQiwCjK}VT=0)+%9{ls{?jj>>nNlyW1W?xh_}xjp=A~vu_HA{$9JcKMZ=<KcEEG
zK6||Yqwut^+ynFb?UO!$hhBE$FecdB{wvLek9~-uFTVD{djRvZe}4k%2kb>ZL(kuy
zLfPE_djq``58AJ|QuZRyewS7qLH2E1p&x8dqdK_|`*g~49<pz~2AEL$+f>sMW*^o=
z<goqyuVFCU9)AjbN9-kEfJE4n|AE~|dsZ_<qU_&Oz(3mFlnJ+w+Jk=tiLo1Q!%(dK
zLsvKxXK%sXi2rc0n_q!`qP^e`bSBwbp9f5`J#ri)JZ_)19oz}~9lF+2?AerYOSR9`
z!hD+j$2S3U%KlXa29s`|5do3Y_Sk&b&9eXb6iBvxJ*Cfc?8OaGIAhm55ALje)mC8U
z+ILX0#*t@tqr7gu{q;UzpR@n79j!(7z+iC2_ICO{YKi^$d7zcrLuf5tW*1gLq1<k8
z16qZBK9vMi+9O|sGgbDu1Pr3uK7&daYVDio1WKKK1?gR|FZvUX*4v|KRd>-|O?UWZ
zhke1*XuV=zUI+IZ><3LiyK2v;E1}W8)fHTm{YDoizu8_Pg=C9;&iBx7wa=oR;&uCa
zI^cW59!qyso4sT?EVbKNl%>6CFRq18o%W}xWU<TcPC27)`-@b-am%h)ghAZ4I}mok
zO=34v^!1K?Y7PuOwl~u3joDv52AK)_y(pO9z3tVxz}~ZMtQQI%+wN_J!v1Zq(4*UD
z+r`b0jNBI9024{uVk=<&<hIomdrIH-=NX7(ZCkJkjc2w6i7?K*Z6WEvJim?OpiN!z
zwgl{UoGQ2N+YOlJZ7vLS-rkm20A~iaiRPkjWZP5p8@O(dpiSuB?YemM`EJiHg26-E
zrxt=lZND&v#)R$1BEY3?*F6jKXSUy_GKHe;S6%=q+aA3X7V5UYO!Z=yx4X&dh3&gz
z`U@}-wqtq#ChF*p#+86c-SI1(GRxSJ*NS21?XYfzPh~r#W$3Hh@ht6?ns%hvA=0r!
zLp2_^cBtmUwf-GT)iCjBhs!ePjqXUM(@VRZUn$2pJ)M)?(CF=ai=L$Z&a12F%Oio#
zQDe{ubB=U_evI?qwDXF0j(iT5lAU>N5KVF3K#FP3>3_rEY3B~wm}fYrc0wW3`4VOC
zvz&|LpqK0Xgr0hN&Jk_!>6~*P6)T;0UhIOt0_U72kV5AO5yn~MJopb~4~v~0ufoL=
z=XF%{Q081iyRvd;Wfv4Hou8(4MwRo=>(E&3T&06gHO^w%vDG?{(+z*YnfDV!>Yc0K
zMBhbc?*D1}4zQ@M=WXw~TiB&6>@B;?!fJ}qXe@~ulh{jQOrl1Oi8UHc)EHZ=F^Mi<
zp^AVNK`DZwC{;m0ii#o#f&~yonqn6e5ky43ck=&z&*S4b=ghn_=iIyZo-;G&N`aH>
z>o(7Xho$TK(Q)Cjb-^)^ys@r(6GY0_4X1Ex?Ybj{z_j8)iV#32s+&K@?WaZlHLfs}
zej416P&ib^eMEO!IX8jM+uY)0+Ev`<+60JHasBk*YPc;r;MZ|FdMDI#U6L@K7Va;4
zC%Ca&PeHudwiQ4LV*Mid|1%~JryR(8)-U40zyH-@nCiMJ0p5P#M$61@txNIu=N4b|
zeqs3#y@Njc1n7fz&BxzEKKci}L&x@mOT!dnFjK?78xFV;x@I7Zd`#ssqq;wY?&xx=
zHT^PR3fjN=lu{#O`dx+Y*JDZ{Gd9g?hwg9s-GK79xpcVsy9vISopISzjy66&6aStt
zd?4DtZ?<4m6A#cvU{Whh-DJNM$o!BV3FoH#-36dO4w($lpC+5pJGJr=+Nbqs1;X_4
zR1z`6DID@MC*Ffwvo=!+`p?ljC{s53yeFFGe0~CE<__Bhh<Rb*n5|!19HH=A>{j&7
ze@W-x7R1vdccGUj4E$@2#owE`B~)>`g*!kwb5G8lZb>h0IhCq<bGMGet`FBpZ!%x5
znF?V1xSyV5F1B(vBOwx~;lv$KtmgjNJ=`1H;X~Uojy7%pmS)P$Y|KX>TbSbm!e+}d
zFnwO^!~%eNvmchgIUm-y2_x`j*C{0D$Gn|kek)s20286?TS|fLW44Dt4zUIF<cVSN
z-C*}H>q$@jBkYs00E=aP=m5h}=3v!A@fbTB4eU5Jhk^m|%<Ki31U9c4*omw!Eozcj
z^ZVeE+0I+Adz`g*2baS3P*f?E{kRMwC)p7yqdUQSQZOuq_rwlXnaYo(nB__S`vy33
ziq}6xV;bMQ8j|UJ<Il7lKh2M&6io)7KM^pQ{H~)gk;R`|0hnxl7KH}R@KZWL@hm@{
zip<XOs_&qX!=I%s?|FXM77XSBzq&g_a`}cRU|-~ImVwLT$MpnQK7UDsznAy{qd*Gy
zKV@JR^50ye4^dy{<zcW?#D9Mho)+_|wD7pXfA}3NUF9pgK;s(!E<F^l^L=;1QVBnp
zP7apxuW2h)#_yN`a)aMQlI8qV%D3L+Pk#=DTYTOINLKJ?nn7;!qsPEPCI2)1;Hvmm
zgnF&YYTllz0BiVGy6tND4!SaT_(UG$E<dFNFm=3<QsDRazly=#=hM_M_<&zZTeydO
z>c;?m#M}5m{V`wjGq9iVv9r+kl>ciK^y>KukD<`O&s_oXjK4+OyXXAC_c009Mm~<}
z*k17YOVHZH7jJ>5FZrT+C^qvA6hmp@r$xf<D}MAIV7Ky(FJSOBzby@oZTxNlFm8&;
z({b(G6>DgjnV@KU4!uOhpw+-kQp^qom#paM3x(r~{ZwgpLSd!vXQx;djZe^;st7s+
zyC)SZcEH6VMI`+wixv7}C|*&l%7N%r#dP|3Nrhq)l~mkTY`+A_I>nJdkb8<62PiyL
zjH9ZJM~W&7^gNYMC=BJLYzv1^-pV>P9Q9MaGX)d7RXN5Njs8mOi9g}ZHsxCi4u|2t
zABM&$<$~cLY0AoSkaXol`oW%7mYsushVoBZ=VdCt{T?Q=lsT~=*~(I?e><b}F9LT?
zS<w|9<|rFCpz*wNH5FD}P#&Z&D&#6VUq|0XWzi#;%~P(nPJ`Wir5lChD^;$$fnB9K
zJp!a!RYhElO7$W1YgMK$(7&Uyr|G_{a;|_vo$786x>~BrXYjCDmGu_>cBod-j>=8F
zjgFGKt9xC67ar<7N>ll&f4m71KlN*0G;URQ?n+Tkf3+Je)B@DCy)l=8>Z@(wg4AL*
zxE<<*n}FG=9!M+xUFx9}9ons49RV&x9rZg%sCsER8uzI)=*ZFm^&e?yJg#0(JHZp`
zh(#bN>f2P2n5zCO8Rk!^XHX$#x_b3sDyBWHp3xt^WvIK*q4P}jmLFk0OYP_iE>~Sb
ztFMb{fBHG(sVm%pmakqv2#uH24RwGiR1aDK^~>rxqcJmOYBwjieM9YZ0bIFy*?IVM
zQ|&|1(F%1I6$al{AEkwGrTPI1Nvz5$_5H2Du2E-E7`j&7KMvS;)td(brcS+$o-p^-
z#|}f|fx72;h&)nnr8WK&_3vXL`BZ(=4eIskQaWtsVRL5|yx(K9y#ac`HUkRLxYuU2
zAIyi?Os42}s7>}#nl78zV4zs{+muuOGt8z>4Mf9j9#T=k0h|01U`N?3rjm+in_ns1
ze$b|lVhS-fbC<%I!!~2z0n8Db_B-HWZDx*z<WZYvUjgNWO~J?TBE_aN9S=BZ^VtbF
zbIRsQCNR@%KA}4y-R4~iA7@x?p3^Hg(}o>JXO_(ss%_1-*&t)0&e(*lL*qG{^^|SP
zvEgV<blzq?eV_S)O)w>6FWMx(g?gUN(I+7JHpv6fS70+C0VWD<7Eq}7vQ6C_a1U+1
zr4uHPY%JN}p4iy#!C0Q!SSM19xZY+1eQ2)1W&*wHp4)8BfnuZ0uelIyvaz9u*h`xp
z6f$~i(?B864jYyOeK*Y-21$3#*bF%1p(!{5l#QAKEl@UTR<6QWHf!wZp^K*){YE@B
zb163FrKvY#fB~BMRw|7T)EMdKxLso^hvE)R?j(?1niu~-aks{4I27YG`Ls_;&<v(G
zUXtby8GXr`UQ~p1T+@ZVhjc>o!%dJBjfP(0shaSw!JX7hzK)qWrD@89WSVB-Q>dqF
zGHKm%TJysxD`<vhF`e+t)Hrtmm!+xy1Nzw-x7W}(qZvW#__G?v({w2`6KLz0qw%7;
zh4Y#{eSm#IGb9v!xtdQXI(t#`^*HF|X)ex$WWFYZ?#D}-FTVvT(8N&2|FY)7RfrU6
z_P?TVaIuDq0@@W#78QA4)ihGr@S5iLjcB~CnJq%JM01pGfl`e#9hbSGIYC9o<(jdy
zE551u`~~dZ(p;$osnA4hg}=8oA5osSQsX-ru2pF+Q8c+)BPT$wMkCR>zgCm_7iIbG
zXj<q9!CehM7NkzIm`-Kf(+s!`OZPQrY039M(~A~F4>ezY2NQwXiEVH#NV~fm6!vNd
zoC9cx_71I!LbZcwjlNH-q!3w{w%0&_g=;4qf_kLZe+I|_ZG;+nQCcsmyR$}X7p_L@
zA?<IY028CFpp)o_wL9j49MSsE0q9X}1(lV>X-`r$P`tK^4$G!#&sW2>bgiN*e9F-J
zQ>|#GR+<OU3)&B_0<%c_+7n!{b`x#UuV@3ZF{G<ns}1_DX^+w&hwE1D_#;3o(QZn@
zoRn%q&qJn6J1`P<Z)jiBPO?^OE(N)xeNLN^yV`;w;OexODXn-<`zO5*?rY~$K=Xli
z=vBD=P#fz8?8jO=I%@GmyOh>GPql><PO8_|(F?OdTb_lnJkwe;w!z?Y?F2fW(5OxP
z0x&PM)2S+_NgKKq*e|sM>7Cx9{f5$+ue3|4kfl`{Ps_pA+FA-)wrR6xfV|NfC_d7z
zUA7tATkSpi3ILYf6b5s%?L%L1aks7S4&q@uiuM^BZTnm2g56~M=p|$}+ja}bL~XGh
z5Dk4#Tjf5u?_+Cz34^}2>uL4iXKSH_jlb>wRp7SS`Z>V00NY2q&=_dD>L5^pZ0(){
zd%JDVufgrGeNJb(_Sr6_IKzJ1FDb?wW*ZX>5^fv1nzjRxw#AiT57-{3YaeCXi3$N~
zY-1@9)M7iWH_+VdKK>b!?si}8hd~d!Rk7s0-S<@x*<|-sCLG;t_sJOOdE3R({>#Ts
zoCXhl?FLT=rk`Ds6_WmTS8ai^&F%taVFT@Q?WmY2$nMi!klAJDM+dfc+nxOcoqOz-
z%!m8Ib{86;7-Dy53a~@%7E<m1KD!e7R?~jF2fd*XZnvElX%Tk8RKFT&cVj4AJ771c
z3Ff2iR`o~YLA&%d5IJPm?^A%q*xl*@l4SP=4{NJ3*=`>d#U8g?@C~p}*iEIETZ-Lt
zs!K_=+er00C++S$21&E)M8EWOJMMirlWDhM2=ub;6kkK~j9u~~*u7%sLM7W*?aa22
zyk?j8E&8t8v9sVx?0#AXlu|pz05q1_O{J%fwc4)s8rT}Uj5>7I+UY3|bH}by1(-U!
zGcz&Jhjx1?<on3ZsSJ{j?WP`q`6qS*10d31$0$Vh%x*tbU_Q62?u-d;wEOK{jHTJ`
z!+9VrcC8dycxCs_yFh8RJ8}_@zP4*P0z++9yFIpW<BeVTBbaZu+d&(Pt@c-c0`a$>
z@(B9d?2opB1lZ3WjK)CwGdDqk>_16^-gf(pOEAB~K8Su5JMF&^fW6E9{`&yiZJ(40
zy*>6%E5QZZAL#^<z4ou;K|<^|eFw=<d#m*p^!MA(r82xQ`@#;ihTB)rXUik(yVEi8
zNc+C$(0IVUOBzNPW#4)Q<e>di`n1O(`y2`x#Mo>9#Rw1E{~)0;);@C_271)Kbrc$p
z*>_(9^Ktg~27$!eH)WwQ!F~{x^d{Q3S*aK|$$mtCC??x~P9MHGZvQ@2_NLgUM}l}c
z_+)^1JFv-+^l>Qb0-u5$mal}}y$<o8&|n-UQH6V`gEQ@5_Bp(w<y@FU+6Fip?$B5b
zy$FXx`LGb_Fo3cY2ONg&gZU_jp?Da=MTeTpaO#AEaV1EKLl9MfraJi21LLGat_3ic
z9ApY?7C77-1eijHI*J^WILxDWW2uAJHMm{o;7*ktHyoO1=~eE~#R(!e9rEcRa?2rb
zJ3Op#@VO7n+YZ?u!a}7(&=m>?S2^SjgcsEg=NCb=#=(weuht=M7RX(P1ln-cIpk4x
z|DMCV6M(tzkkyLD2M*nLK%vp$<}qBt7Y<*PqOZweDIL~(>9FP%6q+4={{~!(gEy6@
zymIKi7NpgIcShrDheUkA0Uwid=+q0XZyf9?$k6W4*9za>I<&q5=ca3UjXrnXjkzEm
zx_u^qZqyB?QpQcX6$3Fdn{{{k!iz1s9~Oc0)ID4XNiW@18S37;^Yk9_(M_C=Mqk~~
zv6x>!-S`VIzf~7P1vplJ-I~9lxJ~zGFj@n2K{Ta-y71@d4AKb*P${?Tu190qcIv$U
zTNmk0FNDZ$-7+fS+N1NMw_&g@ilY8|byu!oW<qqmn!ttXm=*^2>3+Wr^ZRwDDM1#l
zyG^yn5xV>zAQEZSIeKBd2XqnV&>5whIU1eOx_>@~;z8Z-lyf|!D?0!ahjk@`F_<H|
z#d?Uu>IRR-BplVnQg-B+Zqz}b#OcP)M`OHBF$7*D=mv%XGf@{E0FfkJ6>V^nb-Spx
z{J3t;Z44<zXPxl`qNzF!opLy-^ZE<=r*zr7p^>H=-VNr{bsx<EcUt#8Ew(arJ*bHO
zf-a{KXt}zflc8`?mr9?b$kX+uwdqye``!?_ri-J>wd=Z5v(Q+gn|B;wr8-y2Q<v#J
zJ`J-sbgQjTFs5?djbv!t)IEv^+AUo#s%x&$nP`i7Tlf85G*;@|DYR6jyYny5s&&^8
zLsZu2@~Ir>jxK%?8t>{JP&TMe=SD>w_jLAdP`Iyi*FfZf&Y4~=4|U_WLh_L=nx5H@
zbq)p!2S3q$F&G+8b)^Qh*6Su&(Ac1Jrc}){-HjV?=7sKfcc3-t`dvidOPwkc3eCE{
z7eQKdi|EY4D_tP17+ZDu?ilE6ojME(?v8ucqS3=KCJ5u*==hS7^_v`fFTs$uIR3MZ
zKIY-+Sb77jm*d#?VbI%g87&)p9LJGszK&7!YWH&#sm^e#<6cS#`a7<Shuv+CAO8(Y
z0ge|b%ophR_cyQ<<D|C1AdWa$6~H{|G&BWzaZaO+a3;a&vsJK=<m7M?3df!7AJgwI
z#c5q{SW0u+NvYaWCks`N)H=BjhW;I=c@g05IxUzEuFff80`%`W9efA+_nlVJ+vT~F
zBkiXeo$Nk@WV6$8N03)eVU+M~bwU^ebK$g}%Dmc~*4%&>Z=4i1P;Yno`4}3lZ=H&$
zimAh?>oK6Y>A#`-*<Ig*7E~Vkb5vBZQEwar4L^OzHehen-|G*U5dG9JG=}OA1!CCy
z_1ozQ9;TmN4UusD2cLtB(3ian$pd=F{xk{tyh13%>pwgIyQlOeaUf|{{h;wMn67vD
z2r}pOeQ9TKLBDG|-QD`dRnWhvkD-NUo?iPYNWT6Q9Z9>SUzq^C0{ua{28DXlT-d#=
zx19n~q#xga#$x^XYz*m&zMMk1xAeQm!O;r+7ZjVht>3W}hAQ>eCF`M4r5Aj`R_m`9
z!HXKbxB#S9zx@qHaYsMrITY{e7qx(^)BD^7cTazPGd#Sn_tZoEfj+eZK0Va8zlNnp
z`sLT5{#ftz6}Tt*zk5OCsebhUsMqT&sYIedZ>L7%Gku0N0BFzkX_N_U)ITVLZ!h%v
z2jH6Yrf&fAQa^G$G@A7n=tNwLUbqaASNg_$^tI~uU5Dgr{Z<M<w&@3^!o(YWy&W3c
z^@sk3c{d@LBJJ+N8#=7xAy{akyHSX<Kys6?xQK4@okCJBuy+Z4zXbLkVR|2+1q<y|
zNfRn0IY4or&=HEp{X(}%@Hb2_{ss5Lh3rCb5khZT-9-wO;dHfyrxXB*5+te<i5A#s
z%+o>PWoM`#656Q*CPsKbk@~}e?i;G|JR(e^8i`n8JcSpI3XcsS$Ak_4!bF^qMP;e+
zf+7iM2|^VEcA}u}1ehdYpcA}L7A`IZcU-7&1Ih_u{RoUOMOaJQ-c(_M43v|?f@DaZ
z5;8iYF-`a~0bIJ^i^?^t^0aV;ilH)uzQdrODg3z_8d-uz89=jzSwErgjPMC%Y|aYz
zwqq3Mg!T;R=Li|MVClTzPT`*mLOg~3a)q7Up?*>5Pb;WA!H+VR`9e)2hIB~?3IJCi
zw9q1}P&jo13f9YlfpSwt!WcROP%QY<%k7HruLh!5h42B8xh7ntU+i^ZN;%Az2#?8b
zsZeZ-#xh|V50M+flYgLIF8sY5<fbr?&h^|9dJlkPh0wnXxZA>`y^yRF{EvZD3Ax!A
zV6|0PPaB#VVT%OOTEUGDqudd`rO4J@p|=UH)d}<HYaI84vqNF<zHpFsP!EJLRJH$5
zm`4Wy9|?aYVZ4up)@n395oSii(WgQlZTjnlcQ0Z{4Z^IenEYo#HND233oGdwGz!)}
z8qDkqAzlRABwQE<6EB6H-@$IPAku|x5km6;`bzMnqb04v3@?z^LI%C++JvH?A^ApV
zp9uAKVQLyA-wK{bFy0Q~531;Q6BqOaaTmRAK*U3wK!sr&#SxUS*d$u5--6vNrcp`p
z7P0DYaGv6Isyy`)cU^^sx9FM+pM1nkE70dFhS2c@KQW~gmbQv#Dd+DmzDsH2ZK7d4
z`U1pF*I+(S42y<Hka+D6c(`5sKn;I)h+h<g+bRA=#{qYV4-e2gZns!XvC2JScQ24&
zan&Zw*Isd%7xY8KXRja<Dz;JHcc0jU9@_iGuLB_xCN}*DOX1?|%NR_Axc?iFNO1~%
z3h011l2%|*;x{1>i587i(s)qZJpp=$#Di287bC`mP&v?Hark419uc4QgG{VA<{-#X
z(L5XEm?(+xB2IkL6`=8A54w>P#JJgLOcZB5fJl<qnO4uqqUH;X@VIFG?`J5Ur&msj
zxLpU4RPiAlK07I{7eG#lUr-H5n#g0jY*nU<j&$JUv^ak?Ix|FpYC$r^@iV|>iI=F_
zKU-{=28}b~nO`7zR{XjT=INa1J_kd~5%0Z%-ScAiW^fn8C`uIOid(2)_M&)K0?8Av
zQOGb~WR#V=B<e#jl?CEkN<@w<6z?4Z=w)%;dJL^dY>xq2vDk4C+!gVX5u>;&?)(m*
z*Tg07!L{q+&=)XYBK}O3oTVa83q&E0cK9@~Z;E|BLf<VhvK@LAqCM5V+!im>)2CAW
zk!nb)#1$7os>P`c3N@m~XmGV+9eo7(j@TLi^}FIRiZ#@U_h^}aPyB--o%h8LcLVc*
zm~{$$4@DDw!|su|hE5AS7ERVNpgj>IXxIHz?Ee6Y_2Ql~475Rvqu~BCF?Ts`r03#4
zKfvuqQAH8U7h)$`5;TePVgU0}Tv7qjEcT_$SBqF}4~19a466HU6-By{UW)<r5NH$k
z4ua$xaoqwmwu|pMQyl-TxN;LnhxpzxD7s0@YysmgIWZXYkUEmkxKSEIg|C~W^Bg2M
zOBucp*&>ag^{%JXmzK?5Qr=x)drRBsKK7A3J3xG;f=(EjpA=0Igssw)!9eksy!9}@
zO`2Cm_i=!<Wj$I0r4T!S21&nng~oQN*Kx?~kbb1_>rUx<E<|=o`^Uhi-BMU1$Q~(c
zJ4^&iD@&obR~nTK$q>n#w%MW51yA(tlhP>~a!k5SCx_xBpReF(yyQ#^p#-T3L3XP$
zQF=vDoFvJXeig~mW!hjLm&Vho@PxFk3qVt(>#H!dROxCuTstWx(6<IpNl6D_H%;nI
zWhUv;rZWINEmdbgFGF&F4uwo9;|0uTNiB{b+0sYuP&gy~rU&L(sRtFRThB=>5NwVV
zbOr2rX~$)tU63wrfWx`cdD_ohlzyP6d!F<M6$9r>!{3F8OVSeB=@m%Y@1a*HUHuU#
zm!;lx#}`S`1~^(Q>8OnSiZpKqT)QeML%>~=22!!+b*W+j43$`=2XskFrCd5ORVKaH
z2D>+;Zd77aE?uOx<xOd97({PL-=D>>E2IM)ByUSeR8mzb4Sfr{Rnj=B!mXCNdw|qP
zi-TaIR#MXKaYuSP4I+1?AE}(XPMYuuMD9t)=ralTCF|%s4DEpw@;%TVN<Hb>`$+0p
zfX2tt?M5g*kxuGh@Tqi;iX!Tz&Qa)VkQ$Rgo=L|n7}IlUPB2_+l*UuA{Dt(}7T9f)
zx}Jxnmr{H@xMnGe3c^|>Co1uKC3*CL`Bq7`QbELPDYp|Qp-t*O0<CYPFjvU5OO>f0
zZ>7o)V5viL^?@^P@}ij-n!Eh?I5-b^8Z9F?$_LlN?k0H_eUM?ZJckb5Y>`_g1KLx5
zLhC6nxtxkqz2!p60{X}sr~uAa9-lzJKR@|Px`VgM5mO-JFMmpJ_-*ncvKt_OLQk|n
z`HSb^g5+s*VYbUIwA$DqH#MPgr#ziPv%BQt6Yy!bTu-%^d*t&J#0{2NZwz9uJmFi6
zK14ROqcK$OLl2mJa&tT#3f?dC3m_9Fcl`k};WDFmM1(w>K9mzFt9{_`0r?L%co8M{
zp{Q@PoJN&`2j!dlz#Wn|u0&sq{K0%E9G2hGmg$JRW+O<feCq@xkIFyMPvw|A$`@d9
z@)H4Eyllj(*{V#CJ57XsqCEa{j6O*Y{~8*}a<U6#j>~iD=Ws$^{UI7t<a)a2Qe~SA
zG@g|6^PqQ1?&S~3G})D6_35%@IL2~Xwxh>-hCHkmn3=LuEEKZjH?+acmb-q8zB6)P
zDqOXmm4BnpW}TA@c7V;1r`bdFy!;i9#tU-kCjiZrL$_gQ7v)8SohOeE$E@ee7bquk
zNxpg)eFgG9dgBzzKT(eRvRq8XH%0R9i;ygq&orX%ikw52@Tz>HH_Ts?qsM?;x5@*j
z!bFMO<5MV>${*8;qD(%+!<ifMB)Tx=a^k<ZA~)s8Cirwq-q{<H6|&nh=--x`B4Mdg
zZu%T1s^pvw^i|7ay1}O!c{r`=YUPqAK)EB2{1YR)D{m@?g*v$tZENny*4h4$xi9Ys
zg^369GI~ruly_4V)FXN6eKbCnOK(Hui9DY64o_w0b1+da55por*&w$)0ryNU+zRfw
z-1H?t8|8Rfbi9yDX|L2IXO0BQOW9*LM4IL4N8omg>~J02D|wc6J=j*+iO$lzmM?z`
z#Ws08?Q-78U3x;MUABG%k+*Vb5J-m{F&-jrhBxgHaW`~0z=VgPf=+vHG}PTg-zG!+
zQ24aN;7J?QorbNa(6`Ir-UofV4W*R)++*lD41K|d1<z?67h=fqheoJ@i-gQRLm-7J
z_Zzyqz<ijYcLD5%8*=^t7h&iuLO;^*New^`7=HT;Zbum+2{hVJOkvl92KRq}a>!87
z9VEu^7e$*78$Jtz!Vv>|ACj?#2M)NrM-5|JDUNZ>aDvtZafW47+>&6h{s@gk!}En8
zNro8}08KVLHNetwLo+QKP8f`ovQ9DFsDn?bh87WXanjI@4(^^Z{7nIuG{ZDHdy{Us
zLz|V;hWoCtn_<{CAAOkyr{3txGT?T??=RcnPo+I)3_WTgbJlPat;%zTZhkP4V=&vn
z#CbzH9mBt1m_i4va}8gXz|uv-#?^qyGo-J8WWM1MEk-XHmeBV_3JhCT1GCVuY6Q$*
zHiS?tw#eW?(c5Cfv~3_)3>!kwXuWDEUj+SYhKy?vy>1w=AEd;vfli{98qVE>i890E
z5fHs$cuHxWazi9-#cvwC?}6Mhq*4~J!f<W?e7bEYrt<1a!@_OAtTG&>BNx?%fw91>
zG0f-%pK1*yLqP5ruG9AZuGR3<zwoBcaEXqY-ZPx1I*0p)lsGg#Fx>tcG7k-|aX@=y
z$g+i{$A<ggpz(=88UpgvP<ah#^@geRKyEO+wT1dK!#@JZbHk`~c-UyD^M`9M45{NV
zc})h_&6uE<hBm5%Xf{}lqafO1NOy*duM8SB?6w+OcR}>EA(7VGZ3agZMBW%$x&W=+
zP`n(HZw*VHLBGQgeF-9N#w8)}(A{Y13eLm$H!Vsx8jEegZ8E;U0eYK_O%!t2Vr-(q
zb5G;pf6?e=9A~9EXK&+9N<{k@-y=|8<7boz^D}Z~XxwU4Q=Ze`Shx#{+l*%NJHR-y
z5F&xbU(Y~2$SBW($aZ5_iq-Ehx>Njrr}5hgnBQeAArE&Ozqksr$2f8z6oQTW2S9zV
zvHBS0u|te8E*N2`aTJ{l-Df;(0NQ?Ixi7{PW}Mdmjd0`J%Wx*bSg!$0q%k8AdIyZ3
zW`m0|_Pz&&Xyd-o;0_wsE(LeUSo|fp7-Og_d^&8rJQs~ejC&6PEY|n~MXQb)SBwAs
z{)|s)kr-#(@Dwuf#-a~^onZWUE@Tpo2khWQlCk<W(2|YE>3H68V=O)OP8dI!2DB8T
zE9IP0jfT}|JZUu3QGip%&FetYjCVXR>*>aSbD?+I_}fU34CDRfu$O6^i?oMTnPq%P
zd8usUs|d87G2Yt^OJ|KI!+>_)7*C(ex?tQ$Rp}RvkA}cto>Bb+T+25`o`l{dV|XUq
zE-=pRiM~SP3c4*X8yC^augI9U5+cP$x1CVGV(dn@`c>oLRv5ZwEOkSl^}4YSWt&Qj
zuju7gYMe+>kuqcbB*5G-o_UVOa^v(wT>G2Go&FfiE#uxn5V>u%q0bCe8h>kpr7ENG
z4g9S({x}v~jj{PSuxpL;Jb-e?7)o^&ca7K0@S@IG-wl}ejJ2EL%zdkI%3EkWFn&Sl
zsfWhXlu3GI{ILi09~*}+0r$kXJ`v=p@w=%|tTzs(*I<Kj3J;NI#<{s@Y&7nnWbq4Q
zC@lb+jET=cUK+FLW@|Q%cYvi9<M)@~?<?a=R1YXyjj6Ofd2O`*Y6WdGe!3Ip-x&X(
zP-nZb<_#QvYy71YjU7gxHekD%9zR8+yXhgV9z0A#szElImQ05in@px$U~e`VsS<FD
zso^si^fbLZ1raaPDB7TUn}kn*;$zz2gGOId`F+fVpJ|D8Cp5O20_k_}Zz?ZD=QdMM
zstyk@WuAm$plQq_GzOX6Xq~a$B=>}eJ50A~Kz5owzX}g`nMS{b$Zk_Dh0ykxf->Pu
zuqmE$dwWfzsD3QOl+*zAP}8Te@OPidGy)d(n^r8e!hD#ikW%I0rpvTdj4<6F4KC6&
zx<AYxF#S3PT$Je_DkzLLeV7JI2Tc)FhJ460gu?{Km_7@J-NUBX0pO09><U3*P0Jc#
z>8R<azcI37rojv(&Xl7-U%Y7%-GK=v$KX!8OOiRgb?@i!__*oFr$9YnilMXQDW-U;
z;z>3ANk5B|CbbG~oHBKxv!rRJcY-jebkln$0C(DSb3aUFm~trYlWCgbgfV5A=B`C!
zw&|fa44*OWy#VO5rlG-@uXCnD|G+|ysc{|1d6Uk10-YC3k5+=@n${kH%th1EEf{c~
z$r25_`KAfJ@Zyqb;7OP-Fj>C=S7@5B4kDLLXOF^Ck!jU_=oOm+%}}^v$`64vS549X
z0P~uugPzaVO;<XgUSg`GFifdwrW+*7O!_bB7QA8drDEuEQ`t*^-ZWKHisY8*%opG)
zOugwS(QT7xhoM!P-sQnnnLN$Vt2WgP2UlaN`3RD=rfSNg-!YA%O6<EP{ymtlGfjRM
zlknX1*(vzcXbPu5{tJ^A<$#(@$9|>S`j;jHJujP09m7FdOh3^g^OdRQ4D?$~DJ9@u
zoBG$Hug&B|Rh@54sqyf)-PDDC>TgYx_XF*ia|wmZ;+#9vt()L{q8kR0<h+2PFWEVh
zHoC{1?N6fdg!5xhG^RNJf~_9@X9DMOwDwAKR>Yt+-Ff;F$YeNo`U_~8&NC>BndLlE
zMOW1M5WQE<IIma;w6o6jtsv)|_fpm<$N3$qXgcpao#Lmt&O<}#N;+RX3TN`12dW@)
z$$8oUC=@tL#gHs?ZgxSV^|G^u4m1@x+f$gl*x5o+k}J*;C(wD-IhLZS*PIh*aeLjl
zXA~q$oS&QlSL$3r6~SfB0hAQE;e0+6jpfd7CPD9}v;BFPxaC|=ucZp-tG{Cqx1D<~
zg=D331TD?0oYN+vvD)e!=?JIloM-vK(+AEeHvsd{`Hl{vkDUKXf%(VI#T3?m;@r>^
z<f*fxgiBfPoZ|<D2IrGMLGrot-!4FFbiPSvSzkCG9SG9o+`kEpFP*&-A=2!e)&hT9
zoO5_IzH<JX&WN-+TVFhcH?N(`V&O%bbFdG%H_piyV4~f5x)K_1ohMNUqr>^VA%Jl+
zkDziicXO%<eIDkA9<a30Y#s-+P3GU}#ktws=NUw{n3H}7rl<MYNc4G`XHizp+Z^SH
zLHL-*6vKkAIp6A!RzLH`WDInxc{8oA{LMwQ2HIv0D1~BxdC#8!4Kim@CFFMVi1AR^
zVg9%i$WHShD$m+w-c^BXx7*z81(7}GdU}xro1YZH(q8j}8NduN2hRjpsQLYA(A#HT
zNWs4S=HL2L<~+>2h~kOi=C)OUi7*!`p%`g?Q3C8J^NKLcSG4)wM2z>K`8`U~9Wo!C
zfGLSFuQ~+Rj+iU%LGP%!A3Z&enU_;8C*J(WY>))=hsz+6XwFH3-6V4~{Zx|8@6#dS
z<L21QHu(Lem^)F#DAk-rN#m2|DEg(JGT)?-a+>)wik7FFM{R|Nr_Cci226(eUJ$rU
za|Zpkv&_A(pfTIL+Jwe4<{^}iK5K6O3Sj5VKL)|k9P|9$XgqJ8NS_e9V4g<zMXtFk
z79UpSMe`6^Amy3wQmo~Yx$reef%z0=*9y%+99+9>?*B2kB6Abndd22JR2_E3{N6P*
zzBVt61e&MIDvHN@yDXxprjN@PR`l(58As(AdtL5Q=zX8duN0pScNz8p)DO7Ce+Efw
zj7#`ov>tW|D~9M1mt5M>#JYT`gr%b{*Xfym%;nLS@FLEo@B%EwyY!hwGwTvYwW*0N
zBWeAb<g$;Bq9?l?r|CZK(vQl?PPlCR2$-oZsvn?t(q;T0G@f+{sDZt6F3+h}q{!;B
zYCX`3UAo?c=oOdEKf~@-mlj$|U2`$dgfrJ&mX5*DN?g`bY`4^<kY0ynE}tKQ{tcJU
zXF{*s<y<zLx#?0~4(^uAt3QBQ;qtgE^lrQSTm!vIm$Gm)R=IrB1$xykgGRuo8W-z>
z1a#KAoTfGMT^BcdVAr_}Ne9|S*VT8?xXJZw4}flV6&FKsi|gPO01b6*p~|s+u3pjL
z_Pe&yQHe0u#gs7&ckSp0F2Z&DyHG#ix`VdHQLek`J#x_XRu)j=U9Xy8A;ER8l|DR`
z=$d1X&Lr3C>u{ZtUBf5@aojcdEVvV{GseQx6xVtRf@QgmrHp;HYqT5s&bUr+2D#+A
zGz(}2uBB5z3SE2Adi}C%AQeX!yUwMw+Ev$mwvfE$`W`(rD_y5=gNIeFTpAVgRJ(@#
z0+|}uNz-8Ij_Z?YfVu1XhX$m{wU`p<&92`LgJg^A#1f3@m22~ST%T6gwe)yyb6qnA
zB5zzDQ$V5JwbBOMTi4<Lm9$%WQOv{LQhgSZ9+pX8!HbQSFTDZ1$ufE$9p>0<`TjOW
zzr`|t1|0UX+@aId-j-i(fcRKC(IHk}%ZHuex1VKl31GHbe7}Jue@pOZ;I>%~&_XWI
zvY9@~6=X?BM&EYJ;`y+<!?NlM^mbaF&<Vm_mR&s{x!dx!D~7wrvU@fav+lKMDTEPX
zY5WEn`z+28=-h8<>IayE7XH5-jb$Sh{~osVqZ{Ig<(e7fsKqQ`pm7#w+6>2AI@2RG
z!E%BY4~Z7<`7oGdsnh~9+2Tu2f#a6LDe&-w#hc3gQY?E;fml;5Cuaifq~)uHn1oZ7
z8BS<Tw+u~%PdS!cdRm{iye@$L1<ME*xSwmWqi6R;3!j6=Jj)KcFY+x5X?a&*xi}3d
zg%)K9`Yu~+GSF9QairgEnPu`WKv!9Osb-_vl11gzHC9W`VEA2Y=~ID;x?_p>1P1R~
z$||8>XW2~E!uKriEC$SdOZY*Ue_*L~fc`^^>(^*}WGU$f^4KDkLGp=Z&02U7&^flA
z!4&><TlpufbkC*VagRyc;oC;;1^qfUac>WTY_@WLme9rL8mNlalN&&#pI+SlJy6Ek
zEPChoa9_|x@a4?o6rEHd9HZ6z2~M*go~Ce(wCzvjER+*E$xWi0<`nmWsx#9#g(oo6
zxkZ0N<TQ7P%Fi>nCG7yq<aYi5hqE|q^(+iOn>%_M8fUl;`W(VpF4+s*Ic`TZ`f|8c
zlu5h9+5Xn4lj=U_OHb=fY|3ruZ)TBHQ@e%5KS!e{OQPcxUaTq!oHtueC3Ze6xflcW
zWgo9aqaQ1v6BAomIfX_2S*-O(U~gkzXfdV$R;$N&16k`HcoD=zM3q!wEGHeqzRs-J
zaI3cPv#2n{mk&U2NfpT79trGSeAqkiH-ztu?9+eK{`s^#{A18?s%9E8*B3HFk3|7`
z`0^wmPx*}MUS_PWhI`fpcPX{7<}uxb>$+}1lNUGRJjUkBJ*O|$rE<sUc00?hdFOxE
zRQ%Kh-Ea9<@55*ZFR0)U4ioLA5hx@rpaT_O(vj#0^<+9n6RD1;48;NUFsgHlQlFwA
zTeZ%k2qO2by6N?>U$0y7DLP;3<Xnip(WyTJx6zS%7w-Bv_NRKYK*tpn!Q12Ly%t=U
z<A^zsJm}a)rGJMU11#_&#_<&8rVl%&Qw02oquL8xtmCj>G4!L3t0`uE%yF(K)Z-lY
zQ#EtEqjf!fQ~0=}G#jGnjtkvE&N{9h1++ZJKEK1$V#lb7&@Xpf(gM(%j+YMu=9Z&v
z4kRla9W5|_+fh3Wq~3AdSV%TF=3M~y%<&Kf6`wn1d4g+noNx>VUpRhBA&w?Tu`kTN
zbewPP0*z+J6Ptn7;`n$CWLg~u?}qu;j#Cyurp@sMm94#Tl)r}gcE^1BIMZ9ls5?;T
zaP;X6Y&WN!sUYr7B9%CMIAw1J=jl}TF;KjmF43j%c3S2RJs&5}MxgjQ*>vE-1Uk)o
zK*iKSPQ^cCpxd1qFQavblWPp@?sWR65@=CQ4u@%GohH)z{fLum5fl=g5?f&YxYNKz
z7-70om&cH-aGKH&eYc%XJpie4`XCgf+UeCVAa|T{mSEU-oz6PLP^;6qhq!gz^a_E3
zKz{n!w7lP{k0=2N)_-q;rEvY<pTqA%`mqd+ar*ds&_AKqE`z1h`Z3?Zr*ry1clevH
zpJqhg75!GqBj3>X^9EO?cc6OhdwQREh&<JoO@rMgJ?8^w+VtNYpm`GR;74LrdJ9(^
zV97_YP{hPnnCK1|KjB-7-fk7XrqW-3!H-^F+l1aTFzf(fOCh*Gp(mAC1_=wPR(QLx
zs1MxUA=unN-%g<urD=8vyG8?Sw_wVH-X5WA9vY*Bhg7H%ExeZn1?xe<fgbLM1amd!
zGDfIqN9$psoQfNd2*3Oa_hW_oPG~$Tv>X6ACdAUxB~C~;LLpvoru}V#Fq=Y2iGmYt
zy_1A4RECu-ta}B6Cxi)skW3Nu<<LtN4rW8)q>xV=ty5OPXA5YWz|osEUHF<d>!$@@
z8fb>_*ANUXQ&>b>$}HiXxlqg&0^fz?8DU=_Oq|6eqVb&YVGro#2;HeRt5`S`iXoK=
zkN*aArO>e+3UxwNXL$HTSWgvGF9eV2XlxU#tG)vE8zKA}MB9bew5)k6+@ZSZ4q@T1
z5Oov7>8luiqN5rjTg9qyi1>?MA46oDIQS?)1H?I0LmnvJD#iqD7fZ>}9pVl;F}G9f
zPvum*#ELl}yT!w5kUiqwYLEzVla)$=B1MOAum{9Z?LdnXCyhd5w0OM)FbBnyJ@Dd?
z82$iUjQGi0NFEXEL&3$0Z85NWR1EBkc{(P390BujV$m$jOuTsW0VET|cb0=Biob6I
zN}Bkk7Q;;!CsaW_Q_L|@5+qBUYXZp^=Z*u+CGiD)0=7{6a4-}vi>G>mD-*RX81@bE
z3FUQfiav*6_m;SheyMjwjS*;d;yzl`-4ksoaDQL?><L63h@)w%@=(0$2JVrlya4i8
z{FPn?Ps9ynO8owwiUo_HQ7`_bgrx@2V<5bECKg11doJFtf!#)tUk{iUVkm{DUy6y7
zq0lVeq=a3IxQ+_EUy0@4gS3hz^vr%ORz8BGZDQbMSb8JoEr*BgV)hxjyyC4WSm+SH
z#QNBZq6h0FD7s5S>DyEuQt2sxZj@T+*4-qvo<`qRX}L2R{iQZKGP6zEP1)f9sdyRC
zf~3G1bkU{EmvC)|)Sd3KozhF%v_?uQ3V|JvZjnfoH2w^@XesCkBo9h+gMev0B+VQK
zHbx4eD|%S^`#KblNL2^neykK3fWD*B-9sS9q^m`6CQdTnfot(n{&b)vNFDS9Pn3QN
zgGjP8hW-nk<I>wYa3`cNdeNpxW&6RUN<RNZsinT8cS@>=fum_w=}(GgqK4rTru(!s
zm2$5c(t!Q&B2y}&ynUAR16|Q<Nua|4XQb#}Xgn*aEl?<uBB;crSPEE*zN^xb80cM-
zx^+cksWe=KNSQRP72H#)=YC9Ay%gIOq)nPi;m0?UwYD7Q+oc|Kfaa}~FdnTP(jj^+
zxXBB3@YG%2OaB?6hpfB{yBp=l6nowzE7!u{X88_93b)8NCZW$$e*b-ddC6nD0mWN3
zZ-Tmy{BbBaKY1=KgSN^!3N-r5lcqp#oBZ550oVcZ<PXsqDBGL?c95Jz8OrT)fD(;6
z<PRvrzf-QEnb{@x4+6JaKI{h2J@WEws0YiNzeD3*dF&cshsdr$@IFR%qgB*lIg-u-
z9+4+a1s5yp*WrpBm8<C0dQAS{zsmi1IWYxx6J*auj44rmhjye%^3^<eku1MU#k$Ak
zWmLBr-s>$@gC+HvzYfkM_cBtF*{k>R$uM!F&uKMG)bx3t36%E!FDM%Ewtv4UGzJZ*
zroGLc0USN9f(NXkH%`caHHWE~^Z0;il`x+(z>lgp&krzs2bqEa@6luD{(yQ~g2xOT
zQecab;?JT+N{IjASq1dPe%<i*lFMp%v2@s7{JrMgD^OnR;|Kh|4qb+-8~1`@2kxAP
zw#FV@`F;raaEf<;;>%gB7cri#ocbt$c5=ysfw7Cro`bRO=PGFv5yo-NG;+?3LthMc
zoq~RcxxP1`cZ4gVBUZ88js5^l=K9h>^yAzQbZeaETxNsI;O@KwlF2n(g<cjHNktTS
zoDZd`^SOi9sR-i|XQ1zQ6>!}%&{@ij?g6wiE{Z~zH@NBaek$jtdZV$1n?~83S}tWI
z$Q^Fp8K~do+IwS!b=(IY0KLa;cn5CZ=Vn!-?*TW2{C&txjz-^eE~)_*8o3_y(|^JJ
z`HYI7nz&f1;eW|>Q2kvyx13T4Z@CY~Vum`nU!&oL8%v?rvO5#0PSJzCUkdDvtYkbS
zH?i#$ZrjYxo(8vt-KV{&C*$`*#Ebb;zQ~)&RFdn%Jn5P0%La{vq#qlJR|3AR$7bD!
z!~Sf-M<CnS&_Iv?mP${&K(>bx@j>h?Eg8160w<vDU~QD7-^n~Vi0oo^R5-Akg)Kne
z9%lLhCW2Y(a5%b`&7{)y5O%~LK7}#^9T(fj4pR7OKXdB=J?lZXTLsZW?8kJp#<Tf*
zFqj0E90QF+HlqPDNlc)#jcJUpLt{Gok^&m1S>P~WXRuYj!fqy8NQDv?*sxjX%Vq1l
zA$gI7Q@ksW4PFWLe75g9xORz6T?K^#)_w%gx2$YDRXS9#42mh=W=TImv63}Vmc53#
zKZN34)=Y){b!@RW^zX3`sD9`^Yo|cu1J?Wnyno2X(F^7gyKRrY$Lvxe`rP=4HBj*6
z=Lrz;=L5{Ju#<Nmj>b^_pH`SXz*{@h`ZSiGO%=LF`Mk|Ae~kZx?%6p0IBhE9`Jwc^
zfdqbFHpY9JKXMx;GWhmp7|i51c7bbId_M}XW%DIQ^qt{X*u(reKB*@Za`>+(N^zc7
zoB+ANpQC(WE<gTvKwsp0TFan+oi8nf7q|HPRQFKJYy8pqkdOEijnDXBa-q?}M^HrW
zEx+|gC~Q&GQ%$a?qK;N0UJ8CVIB$iXPR{!%X3##}R}okPFZ>h-z5=&LQT77<1}iSo
zb7QX}<0()=6#D5DCJa?94u;)*3dgS@vtMEN3lzf@UFZ=Jq1Z)V(vDQPgaGD%LQ94H
zQHq~8pf6fcp~aLQRG6s@AxW{z0sfv+45Z*&wn7{NpK=w75U5{PZ0-!q62%(2$14<K
z2h8449BrnL2|QLjp!C2K#r<p0c&f;{2d-W*n|56dirVEE_A`a019qP)3YP$;QSt6L
z7<{Wp9S<)$6t`O->83os8zSz?@9Dkjfv@GmwT(*i0Vr%z4x%%@o0Xms7`>-*&I0s#
zDZTMR!}?#jHw<V#%5knBzRC&oH1$&+`xh`<m0wYi#$S1(1l(?Aup317DARMn1uOee
zeg9tN8uB+pS?WzwscfdV)js9neUJ=O7TG~ETsdkHP$HDARO}q7OsB}j0p*v=;fys(
zxtk6bM=Rqg3md0AMTZsQkqZNtpnUr|`V#RiA)qCJ2T8{NjQ|tJm78J#b3z$SCEKY=
z+y0n@lgj));7%!*Q@SZl`Kk(b)0Osg3!GL?rnGN{a^Ej#%v35D10~n09McSg7nKJR
zppmBxD1}VEvabioCFNZT?-wY|w74i#jxU4AWn}}MvMW+1^n?BtWlR~+t}6Gv3lrCr
zBQxOkb>#!fc$O$np9EK`Or>K~Wy%jm!`~Z91La-H@t>Ll`kvA{k<u^smB)Gk?SZl{
zEwUdfZBj9qN6PJ#G=Gfm2mt%3a?vR0*DJeigJgs9`ay_1Q~K{k<8$Tg0!TJ0=hKHE
zI+U;eMWdU_#|lT?RXwwz?xFJX2J}YNZ-1h1lS(-d>YG(vt$uLPQ&nb$sF!NV6JUF*
zt_=a_qp}u5(N|UZF+lxPcPRY3Rn<g0-@Pgg15AkO6IwWgs)o^ua-V7?{S5c3aw!=T
zrrI?V2E$cTDd8ERdg2KW52(zi03D?|Py4fIm1>C<<`1goPk`M+Dycg<V^mG|G0%rp
z_kEyvMAb~sjkBs*bkzQwN=rGN0@d<NxQ`g!Lo`;YEVLSFSKXnPQ;b>{4zL_`_qhN&
zuU_Pj#tJpdM`M**MJd@w>dUlYc&@&Gg7)99)FsJ4YgJDVhK#q3<7H?ds7Sf*9X1DI
zU_Q*|;6D&av^n+$lW^MRQ!0PRu|dHiux;E6;plT4ZVx~`HTNmQvqKX=3xr6`VFkQM
z&}^iD`U%Zv0z~pOQ)mgAuW{&2?>}E{1|2!{*FIeam~GlIbgu_!)7AhcNc*@O9Nw;t
zp-SkTTECy6xJ&!dON@7~_ID~L2+?jfLL^jMaTg-{wWB|VPhr}9E--jN8@3hxMrn5%
zp%<-vMw#RoZJP$_vD(h_&}WU)w$e^AQ5)g~hm*BKen97O?OQ7KNzoSVfQeLX=X&&=
z)Fx4Y`;@kne&Uz3@y;NH+7^n46l;&G(RWSzR{~6wXb01xvrN0w3NOmFzmEY}g*Jh1
z(i-hok0Ih=Yow~FO;+1+=fQ5VokJmbFWZ3&;f%lSl;sc&u&p}^vcq<NFX->GU0shU
z3APQOmvN{qtEc54{zz~B!rxQu+TiMs2~@`S)4O#5n>x5R{yj}kXCkK8zlQFNfxYnW
znY~a#pqzD>3MPKGzTOEFvy-O5?3_h!;L<N)l**jj&xpV0_51*8zedMlq`#%o)^))#
zN)fJBtiov5eEJFgy>^5@5dL!Ch<~s9U?f2Q`I{D7>lgOHzc<Y8fTZ<rnof7Fj=rhn
z!40Fb`i-2O!G_j9+-oWx@aOtoN9#830Tt5(a1p^E!Q7Qz0N=}Xj0buM_vvpKX*?IQ
z3SOmhPwoIMi<_Q>LFIDK>A79RjSHX+K21wqH~byOx=?XjINOs2ya+arqV$n$K@e;m
zU?;Cx;b{z8J{+xw*=G*{7{{($gUxtWa1vYsJE=zB31;X(V+yOG9DOR=>;ZC;c~FsP
z20KDWBs1AxbWAmiwNs=mhfQ4y^XJ(YaZta&MqY&ECH7_m>=v*G6f?cTUT>g}30!5p
zGU56)=1PmE>+EYg$doguq2O+^d-NTeTda*LF{{~zHy|}kN2`unRzg9SJIwjNRWKWo
z1G^8IqBF1`u|`@$G_d(uXl!EZ0-*4ceHH_-W)?>`OdIomhw_hZeE%g7eWCf$8}s;5
zoBfPKFaEsc*3dJygBwS)<HpWX>ApL=y8$EdVBgS}LpQShiLkbbt)`EIZe}Yq=-a|P
zsrJv4EnR{6@M6id*!E@v{(H-^W0aTiWs^z)=EoLUN5be<=1eb0f9BBugWK2z6J&zf
z(r55?FH28GUkKyV(07RG>R{<GTVAaFKQE>IuJHcH4<|$RCs+FMPJK?><!J+`xM{i#
zVazx}2jgaTsR6>QaTJ*Nx#bu1&K`G)@?Ue-{so0!c65bHbAu>tHLptnKz}uDLi=y$
zX;V7?^&$LwfsURozt179rL%{_*h-EbcWYl$75QI1yP|y)*N@IGZ02-Su)T##9#3Q9
z77m5M0B#d~10ax_WebObxTP+H6vC~blIKt^t{T&~kBiTO3t`;q#b}J=Ok^gS`$`8A
z!#$-#-m#p8*4}Yk+7VbP;tr7y#av1l25^PzRR~L0xwVb3dyP~64(<kbb1>9zb8l%+
zRm)Wdf;{5NI66%KlCw{N;%m<LCS=;Vk{&?o;06x@wmWls4=`culs6hv*b*c-{_oe-
zhaRw}xMLqfCykr95N@S&KefWxY3>I~Zf0;Z2Y_U9LwSrUi@UK8K-t`E+GFQ&Av$=F
z&wXsAw9h5ZOgBdX*NNhsh1{zgG+yRpH;^K3rs}`Z?V+H+9qt#3PTl2BP#I7ici{nG
z>bVdK*fnsrG{>*Fujpyt%6&(tQ9M{oD!kap+Gs7miLIg2BwJZLRS)~KkyGgRzm45J
z1JOOKbtgzLn>+}UyO+(o26BL{p$ds8Hkh^|(QFH?Y!0#{`W?nIEj=C+SZ7L_onn0|
z;7l6xOM#_y=5QM7r`bl@Je+6S%h7m&O$~-ZF8g^N%wA-UyJ-J^g?Y~f_Eq*RmFiw&
zD|=&v*I6EIY;LoOm(W+q)<vSPicO|FwVFL`LthQ6qMgtq_BU<d9y43Y+&^KjC_MC(
z?VJcw&(_e^tATyd1?tb3{dr8#bLRCA6dGA5vSe1}3+9^v#U{3%j(xvm!)TtHnco_W
zsf9Jv!qZpm^92}ME4vU0$=B>gKDajKMdhV$*nl}eYiAR~(C5c*se-~@{x~hOBKUws
z7)uPFM9w7g3wD5<=j&&ov7A@VgfsY$Lx-(ItGlA>9{}B_sG^G(uZSE7XR;Od=`>1_
z;whc;sZ>~3Lh*%S?4KZQil(^#JpziA-%<MPrt%jhi77R-Jg-)UFUHXCC?od(>7G)t
z3L=k`Aw@7+uXLo{W~0*1&kE5N<+n57^lPO{S8yFrh3F>Li_be@VE7}xL-iI@Z5{z{
z`m-{0&RlK-n4h0~3FtZgDd_z@@plY(QGkHISB-K5-0EMh<KJs6A~4rJ`xIJk+-Ryo
zap&&S<H(y+BIRX8EM^Hsbb>hdrNH0L1!iL&Lb#Vz;6k~yS?G)6-lHr?H1{zjJCAX<
zDNY>6_3R4Ccy7jZ^rdniHNcsZTr|BYPjS7rLp_bNZHIa~x3>`rr#a3CzGQGaj{_x>
z3s?&gYZjN#PE*Yl=YX8yHqo-+EVqYJ&F47VDZtL*z8DJq^W2!};4W|#6v@lw)-Hg^
zMeZyGnDaQ}P>_6XMJJF;98cwW1zZohi3+)R%I03?+}5D6h-;$tcroW)j>aoiZk;{Y
ztK2`O@a85rF%VOCi~EMoBvo)_5-i>3au(Bd<+5twMHN?a03!Ff8Lq&7z@4DY>O*c|
zAk-gmP81z{%q?3C>?d592$ZKB@|5(D7)DQk1g52gZwj-a=g3KBb)|xaG*;RS(bMeb
zK!|3u$FxT|$3B>i!CYW(Xvd$&u3Um*0c+U}OGRu$9Yn6N=y_1M$tHL}<PO`o5w5xM
z_VYDp#UJSyjWv{=S_!g`-8u=?{Vb7y!k9b739aF5&<L20U|ZI~kx2G(3-k^!IT!9l
zv6XLOC7OMYw;i53Wusx`5L3^GVhoF=`l`cht{DnP*aWKLiDlPRkUYv9$>n2gax5g{
z*cMt2#<L`Q7)oF&DrHJ!vsR%m$;vjog>R{B$WLIi*{~46oMA2$^37xJf1xj*rP1O1
zODyy@L<(5<k(lEW_I44>m$FA##3{>I_%U!dSmHV8RWs9Y477%IrR{bt`|3;R-C_P~
zK<={Ybx^2dmj39w$E;N-GeI;bCl5|NU^jn+iw_w`*Y6P<qlD;VHcJDvCrmmE$)`-B
z=UYAVqf=lF?AJ(;7M4WI+gGeC2L86PGP;Rgvv`W8w6T$mXne!|JqO8lwtW!DTUN3S
zeOvfZRx{?ylb=H0li0>Tsf1zxZ%?t}J^Twg-yO_<T?sCNPodaOBp*Hp3P<?a&M+9u
ze?eKSWZr`^FUR>m??Cc2-%RDJ8T^kF7Cg_NEX7z5_o3q9Twb*klEu7a1i8Zhv4*1X
zSNR^7;nX$0Y&Jx%^Z#B$X9@2`hq6lfJ^`>>#&4hxN!;KQ==zlNMgKtLChs;H&fMZF
zDOOm)=hcDS=0|J>spKcoa;=JgRSxxPJ}wntHT=RAXuQjBrL1NhKVmG!U+(e6RK|Xv
z|A@A|kN73DKzhtycm?hW-%jtJr+i=(^y~S!2O!V+<x@Z!`P(yr{esV<#6mlt;elbh
zDW+3}th*wgj!1ea7S00MsPJ5YzD<h6E|A=;Xg!K?dMUor((}(-A&kY;_$k)k!<e=z
zxG=cyuNXmh;5Nk+DhUiwOk9q>!-{t(9FnX!d<qJu71JoZkfYdn2qFcF9`R^=tQfwQ
zuCMa1d+@?b)kZVpr%HVab$?Z9Iz)D<{<sb3y{cd0(P#}(m2U(as&b^T<UW=82*`d_
zw|f8$SLHdu;Yd{p#j>JQf7=4|pz7TYG#*yX@Sr<E6>bmESk=7<^c_`&R6*~U>IeEX
zPQ2;_Z8{QErMEy5RX_amzm>I^JsZMPm!Z<ns+?w3!Q%8cHUOP5<R^GPa~vI-o>edk
zLO<^xgTLpOGyq{iKE-AiW-Y<Lf9Gl;v!WAK->fuJLB^^+bfs43(^sw57^z}?trv~#
zpKk4t-^3l2Y3{jQv;^47`OTmi;htG-0JDu-O_LtL`PabvKyKw0payf}=smiZbEN%s
z2zT-VNGNxumZpg-ya(t6Zo+9;OXYUC11*C)K`ZEUoO&rp9%tzeks|IwH%wCrmzfM7
zZ*iY}1+JF6R10SwbHCiB^;a{Orv#`QTizE216dno7bDn0&;MU=@{Jh{0bKM3;09uS
z3f*ANj|v9&a{UIw<q%H(1SFJGe+HXT+&TKbQZ#2vub*RFZU8)w<7y8=A)d3)dN6_e
zld=;hIcpy}DSnExP=Qw(C)J|$94Gt%gE?H(V~nnVdpr|;g`7R@N=mtkerPP?#(xg9
zD(=D&aMfJmVwkAm7RO@%wcMI-ffCE~RM2^poxe}F1p9XwMjpq`(1Sgm)i!`jU>??w
zKogmk9@|MQ5KB2cX#3H!zKVst4})R+f<YkR{4I*-MDVY%O2%U-n!)Y?KDY-aE{gXW
zguZA#yDRh#@`)?ac!=-293nCNGMbXZyxV#>bA)H_!nJLR{U4w&K+!eF3L2;gq4#W%
z;@qDY=ypYCAL#E;EXVpvxl{2WJ(71RV$#6vRy?HY<vof=^uNRfE0$8-{9Z-+_plqH
z$f8xoW>v*l8oes+PuPu9Es?<`tIpF3Jw;Vz2ZfWWsr1p8)2c&>wExXi&7v(*wyKUE
zPG?oIbcmo?m9!nAe(DtmVE(8&LPle*+K>V+UtPHpUX-Xm`}}_^z=v!beFy0&yPW{P
zp0h70S^knSI_=iVN_#=tlYe=ghe!A$CQ~`<sPAJiBi3)nOJKfROUFOPO`__^@v9d=
zd%`2it$$y%9PJZF8sP7w@1vnS<J)fmIy1Tny|aoa$M<vhI{bTfVL007OrkSozw90d
ztwpbT;@^L~Pr3b-i+_awt1j<@%)dQo4Z8jc)rh11?XZacEgZht3MaWsw3zea2GVxR
zn_EiBoTJ<~X;3)MeU<@{G%kfwVA)*U2=raxs&=EXfcr-Sa+Qmt`MJU64uijy+=6m&
zbzE;XxF_7&AsFaOZr(ZQwR21D(6^CUB?_>4vwvs(Z^<IEh4B5$f1NNBUp3H;xVnuZ
zDlOdf<?!Ma=hqD|ZQS|K0s4l!N!39e+@hWE$&HC)(72I>=png@<>mm%lkHvyOI~c!
zO^9q~?;Qp34)&o6+%aaf{sK0G1=s#>tzE=EqLAASwv+0g%bB7Ih&S0>Tg=BTc3}#%
zD%cvz_uXRy2Sf5c>-8bHN36C0em!Qr>8D%IB5Cv7z>c@Ug;wVIEk^K~?e&DSKD?;~
z#Gg-20kk!U_gRKP?%;hqptzGC^2Pri(oz<!wq9^`v~g(SGHKEKl6&$GY&LT(+ko4`
zr3?Xi#r6IajT_k?bN(ClwN<#Feh8NUb}O4n%iNu8S31;pv1Zyi?PjNMpfQX&ZlV2O
zIQwh~*a-GJO;jZFdjQcR%<?JB$Fj6O&^XG1_Q2=ktm+jkonYN*C7i)#P*yOLwKc=i
z1@^WHD7kFbO3YCaJ4l(KVz!YoG&k8~dhy<3x9Id}1^a_y@3&bZzCL2b-jYS5vx<$L
z2*qlaPZgLo>>~=w)v^sT$Q@?*4MS^Wv9n<Q1sj$H(!{?1m!^ab*#o_1rlDNlD>j~z
z6R(-`YRpU<`+vP%drVVT80S8ES{}u_bSX<5qOw8}d)wPm6dwyvy5XR92#Cy1q)-rn
z7AXv6$YVf|fm0LaxA<UeaZyw@{bRdvbHxR9F#{c&(S%`K0L`3WW~Oe7I`<v6f0q62
zntSs*-}!#u<J{cmIrrS^=+&Z?^U_yY+PGcwkkZGkp#5vdxK;EOwx&UDFaecUxu58y
zrR!YW4dl#l41LDC&!uLe?lE`yYoxaGyXe?8@ZTh((_{Rybd&=83_Wlz@u@d3?MYtO
zhs@vjIsu(^DHeQ+%y$)UPolJ6A?(DQK2&tlcaV?Z-|1oHfhMw?_L}q(H|=(QpSWq?
zeILpC12<_uDWn5p$4D3LE<a9+>ACM?;^;@ilSEHPt3D&Gd6<Pv@(a=66iKEtAif|Z
z0u4@+fF4r|kj5ztc!o67G0m^YW4bF3kt-TBKTDc+3ut(bBsj750_px7Ek?-Ybj<rA
zk=A1}mq=Ix+J8^h?f>U&_wwC+xW&_>C(+-kW_p!<MM-DmWehm6CUbEo=HNI)58%}o
zad21R44p>ps|PNiRaX4~=DWuF7z1Rd+^73rjx7#@=H|ttqqWm*m{#8T@36eCs}-sF
zFMW$HUi+2a->+{eLDw$n25L7v6wpP1lgBU{TW(=ZVJ&@hac6HuW|5wL7N|I75<Pf+
zr+Jr%^gf_8uMf+c_R)dpG7=mdRHE4Yz=A^g$Zk|uw9|d5a_b&+;a%8+HNI&(hN;>%
zfm>-y#SfTDwfqZ~{hhH`Ul--X@|*kVoTC<IZwj_!2Xn-VKF%;K_KF1Q@zliyEmXqB
zpP2!pZJ8@O2N#FMY^!y9R;AesBvCSn(!c6lRTZ_RWnRAvPERv-U0s>iVx~ONB$`cT
zi^*!XNLEv#tH$T6@Vne)UZW_&(c4VSQ}#bER1`7P-wQ05VYH^8r`w|cM2z~sn;3EU
z-V8GdR|dm0&|DP~0^%rJE?*sGw`_y#O0^a~8D;gbXLGOy=G@{{a(f1+@vpEgGv@j|
z)qZ19VRc2FG0o#IuklqGYkY>9O&&v~&*wGP`KrtPRfR<!<aiA=9)FD=dG6ZMj==zj
zE03!}9t@DlSirxR(gJ>^Fudc$O(LJTsr=wR9KXwkK~4sz?I;~r$))4Lq(_sUZ7*1x
zl9_9tZ?>9df4OpJRY=Dg$ZKZ>Xf9Bzz<-%&_eu&CmDI9hDCB%TC>zN$&>!F;WKCq~
zYCDXaQbd6eMMB`mdgWYb1Z>zncj!A0RBLRu0*B3MhS77u&&ntB!+I}(Fch*<c1Eio
zE{77oDjZCa90AoR8v}2=$7&%eMM>oT0`*(<Dyx)akdhK4u#Bnm<nA$bs%m~xLXtJn
z<gp|sNeM+Ig-e$%^+-!BCP{J^7cWWhBzD}HP~#dd-<g=BO=gNg5iQg)Q?NZ+a5B>{
zLZJsDUqCnul@x~IO9YmG0^vGgHM`;oY(PZI0iEE)i7nyqL?<{<cErru9z<ZDXW>o^
zveS5YF?N={GZwYoaE(F_81zUAdkz})sBD0dS@9^$i$k#uD&uItTM(e)aZoR!9&f{j
zMJSHL02MPC_>+o<z!6Vf@z5KO;#rtM5nZfYj8F_aDGb9k1lAP>q5(ONV7p;fIYMC=
zB1MEpP>I0iXdxgXXA0CttZjhTDOA9KQHW<3D`CtiEL61JWrD5)V-lj7BG8$HSmrP|
YD2zibg<&{|ptv_z2>J+G#?+d>00}}nfB*mh

diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
index 69ca3aad03371763c737c156be567f4c7be98e1f..48bb89dce917742539cdaf10e9830c3746e591d0 100644
GIT binary patch
delta 126697
zcmY(r2Uu0d_XT>-ZKvK|)x@r`_ZE9Mw%ALIHL=7VyCx<V#DWM)v7iFdL}`MGAYDPR
zH$X%{1w<4DJ7V{(O@9CPzL(FOIkRW4wfD?9XUd+r_=OEfIXu9#p}ex!@x~)KM`;o(
zo4SUVNwWX{e+ow3zO5)zjo7G=$y?j|pj5$d|J37U3b{(XRv}YuJkHDHKh~K-C304M
zl9MTvD#sU2rfTWU%H(6}te_Glo7qt=Q*f%22~glz{thd%Dpd=Yt){Ye-?PxS*Arz5
zyQw4eRY$)QWQwNdk#z6u!}0y=Bu6S_Y0PN|IA%i|MwVWCFENvS=J2*2pEfCE8O${*
zZK0L>Gcp;o7**2C2_R!yci?4)+IuClda@uh*4}fBhfgfuL^Cl-F0<B3?2O5$m~U%#
zaTR5C<SjtMHEkf5%R%wCPa~m;=I?Bktf@Q|oOb4!&p4q`>u(B9)?A)Ss;(2|-U^va
zIcU6W^8XA!|Cy6b`JdrLAAiACCt@`(n^r5)GsV9$vR`ZO&CGG1Yl5xMtI3RPX04<l
zlige;n^k+?l=0~*%4XNvZNa!y%VcwE<sF!M9Tl?QYVW%+9eo;!Hb;D}S~jm%(x17y
zgptj!y&udR0mFh?hMyQFmY4leD<8|;jF-z6*4|HK9^f%7s=c4e9Ebj5c@%0oo$2y{
zmo2H4&t`6E6tbnY_j8$K=q#({{Dava!^oD)Px~Z@21n<5tZYTCd_ChdUM*W$tM9}N
zc&Cu9s=ePV<JUT=WUJ+k(YAVetyGDp(01y-ukkXOZNiX=G6wI7vR?)BU$Od!Vk)+)
zmAIxaXJw2!x{+KaSD!nrl;Jfz-w^UPiWDf>eTGR^hwWcR)|uQ_3Y!|MW!>nO6Mp)t
zmi<V#k}zzAO4gfh^)glUNM6SFl~)2?>kK=10@>-k8Q!T|HIu^`m1~qJV~5Fmp+Njj
z&&WP88h~Y1{LlDpfmFVEG6!kfKuF|1MN++<B&cLs)C#=T%8Z8|s$`cL6V-(N8;k!L
zzqbS(6eyykQ|-Oi68UDIj+!RTKO9!bjx%af?NY1SNA*9|<IE5LpXy(l`a?=v$Ylrq
zQ|(l%>imDI2bkvnsjjZ|?*P*+5DIdymGTq#Ru3>gQ%&VwD`dtjpL?1*4)SCj)9(MJ
zM-|pFegDHOk~Yj?WE&X6f0%VLF=v7xYyO|z_w>>E^@O{%wQ0^Y`;TL8t=;BKS88jy
z*KDb5t0-&1NdIM5OM;q}wfw*ApK|G}&pK^=+t=}U#G$oy?}6rG{8Djm9^@0Ht@k|<
zg#90$CH#^9<(9B#PnKy<%SY`Wqmn7U=UJGPDSYID%G`XKTBfL{R#_+R$D8%N>c67R
zjPk#mFh*209QY18jU@%IQ3;dlDr5=?o!mj6Cx%{iRkIZ`rJ|pqR{MXLV8*Db8|2f+
z*gzBMBck{SV^K9IRroA4E@gP1JI3xz6Ca(agQMRpM)n^DUE>KeCsWGscvLdaFDhJb
z7<pW;6sd8Y@)&QLOq)guji<?RZTLaJ^~OiizxIrD#($yG7dHqy`yVR(<#&=N9Y!ZA
zdzgmqTJ}7Zu3Hz<HQ#ZF0G*cBT75#Ixn6W1+n)e+^YQt}x`dNFc01AiI*N?Vl9Pe`
zy{L4550YemA%`xf()D0J(r<c%7|ij6N~%MeJzkT9T|oE#(R6=(po73WtpwXThhWxS
zWd7$o^7>jenOS?6RC|9T&1Z{A^8I?!T-S%%qv{;B&_q{a@Gm4y!xhrG(~~53`qO>I
z6*AdyIq8pjO8kvmQE5ql(t*UeJ&EjdNvWSd6_j@;^S6H@y1VF7RWhG{SX>)zrE6Rj
zNunB(=Am_@vn!XJ=yR1yXC@HO!L}qh{gO&EhSL4JHPjM+94A}d9uU7~yeM<1WP5(6
z;)TsfwVjc!E&-&v^D_C)k0HAJ_H@5^4Ar0j-JnXA7ew-kirV(eCH?q6NZ!Sr+?slx
z<iU?f=Tl>9Ezc2j9siUhgO<{L4LT~7L$>rX0UUPn$oh=T9QLcN*>zHyh4E4)Yd)OZ
z^2B=%I#-gkSWI;lwvlAXDbnn6gc#nBtF25dNtO&Fx7g<-dA@||Ju!gpi`o-I5k^Yb
zT^>vnSx3n5+*Wiys|^w5ie%Ecws}9Tp!;%kH>mMT(tJ=W_o#K$WG6bCfs7r?BG=2W
z(LHm6Tui8~M$t#o>HjO4KcOQlO;U)*?(ihl01Qy@D4z_R-ba2JZ_xEx61lRf_CvCK
zp!;bJNHe35?n8Y@=cXr_>1`mx1^&b~U=fx2b|khQ$Eh?fifTWtFPY3JC-Wa`A78%K
zK}uc55s`-%-FKWr*9#3uX~jOecGl8$NDS#LNTJgH&FKE?A4EE@_O-35)#>;f87|vF
zPRyQ3#=5K}NmL_34b_w6v6f0R{vvGVFp=K>&o3!6vx1&kD9z4fT`S0BSZlhUsvtn(
zTp}8lOY*4?Nz<>kx9CvYn8i;?N9!Q@>>@J5b)kCu%SdwL5}_0isO9>(QE9*r#H>tL
z)BAr6W2H)_SCQ&8ce;OZnT%!JC(@Z$sbPn`r27#pQKW1jNr&2IzkP@9=b%5v+jEVu
zgZGkV@UL_~_9d0x4<(a+J?T1R3t5@BmgFJLV8tOj@P=NBxN#&(HqteII?<hSrt4F0
z0#xcq&Zdz0*R{{`b62Y0?iW;#zD~qot3wiY8cCjQC-XCXNzx^RBtGtB{>?3_*e#xz
zr^i#Nqm-lKigRQjWei>K4ke{_Gf3%ZI+?6_NILaA=-T`NQFjnYr?DRyUa6t`Y#ll3
zb)F;*^69=jvbME2y0(2!=AEw6)z^tiJ(f~C?QvYBOhpF00dGf>YWhU-D{mW-PHR9)
zQmu~FiF7*FklfgxoLjJrN^b_y_2p%9ZW2Q}mfOT|>k-|5Oed3ln-c2AI;!5s%Op3q
zApIsf2bo;!Oina!L`r-Ux^5mw#oD1%S78#tUe6<W_cjE6f$14s8ATG88Fc;dl6W@w
z(!FdYp&m{q%@1b@o8F6D4E{j(FS^vW4c06w*_z#IdjG%7phjz4pG<CANB04kAgW}o
zF%5x%-bA#p)=~Fi1U`C+N{bJZvHoiarE5rX?<g`btQ%eLNTib%MpxgT=vr}%G&^)B
zwr=;yd@Hk@-v2h^h-hT(N4VziTCZz|)Uo5KmbX5U6USy!lMa7Qu;AMMF|Lfv`1uj3
zJcbxzqe*{!0@c+G%ND#`r^)a@Z<25NOg!hxi2u@8LT&yLoDNy%1q4W3Nr1J}2(Y9-
z0Vc%~V5AG(pQ{}gmdZ)<>u=;l^+h7u^b4Wx%_ZkPGt_deXAo-bGLj^F5Oyc65oP^{
zlYCVYU6<7*`M}zdW$>R4BHG!LsD(7T{;`7$JWC+C^fTRWT|xDm?L=Vpza)P#izwzV
zAnKbspB3L(9cOh)nOY|N$>BN%Pe?6098O-e^-|!zeT;x>s-DF)a4glbbT2i6t2gNv
zbt1a!wUdtVwNL&1V>#r_3#m@aZ<9&)_k`{Iia2xDkV9Xe()|z}UDXZ+sU}*8da_8W
z=l>wzPgqFx^anCfg!PwNW-B4UrDtT|cz4q5`YXBE8lRt9me-0L{nm>#f8R~*QLh5@
zva#JsXFvd5SInknpO!@Y2W#hdy1KO!sciIFYT52(RIscYf%!Ug-GMm_<YnZ_YP`d0
znfxY^ZX8J_@A(m`J$hrcta}c*RnwVj>|FcQuZ2*v55{s7kEZqwf8j~Z-ub9V1u|8g
zSMyMHM{^e}7F4b7EkUymO5A|^iMk-vbke$N6i@ED3HMVvZwGX0pNa7QmzMS5+Oz<A
z@qX{V1osPmry=FfSRLAG-Po^?JKlZ=i3`(VAgsGHpUxrK%lu2Ti+zm#Ih^!m;xm!k
z&p7^Ejr0JM_yo9v%-1O}>dy>&4yyr7U>DT<5TgnKK9G4h2*!e#e{MrFn0Y@7u7)tK
zG%|!TE*yl1nT**GhB57&Vd4lgp9Z<3jNd4bg)<QyK^?(N8w5Zk^Lhj78^shl9)UZW
zX+xd#F=j$C@G;DyBnV>}zCLotnTcp&)d^;;8}KKYNC9PW%<i4wKE<poh240@!vJ9d
z(>N1$Pctuffh>_(cNDoK=2|AqCo_qM0Z(DBg+rLiSg#;SV?upt>`iAjd;-lG#*g})
zv&_W^sAe#`{9rzlu}34h#r!CuESs@l>7>eG9#2DK=Q7!Qz<rxpkPbi|vk?m_)m`T8
z6mS<XmokAXWR6fTR>T}@jiiM6@)Y(SGMn{adBjw0r;hY7vzf+@C(OAnXy8g_V=#bK
z%*Ia;zF?lv#QP=l<|FF#ikY?m!q*J{5y=}Sp%ixCGTW0;R?SQt4B<PbIaZRY8fMW8
z<lZxVn!(YJ%*t0V_=(AWi+X-$eojW&H)c8>uS4Z5Z_p5ho8%E*aB+v6{VKpd{xvWD
z2TWb&4+Cb|H=6k@uZV-CKYd2P?24eJxL^6GAC`lp-MG3XG}_z$L<KuEK7eb-H{Brb
z^m_vs>wKQx-9YBcssE8H7dAy@)iDm5WwS#YfRSq%2@zka!m5`T8-1IO_H6MCU7*^9
z`IlBoo0(Mf=xSHyLK3RAozY{4rgmedXraD?dEE#fX8?1NrmKgTj`yKb!<-lhx4tm!
zS#WKUccHh|O<p_{zVDGYye32Y@0Z8=BYQ~h;eiH-kyp$GFkQZHGk{m*3*TXVO77@F
zmO@^44lTDD{W1Y`?Gv{`-X~QK#R(%j!M~*q|HRduiB`ddFy_=;5T-DL{sQDWlXe0<
z$Xn*3@Bf-W_&OD1jY^+^USHk1{w-9q%^Qpc>b5QZL2uG-@<vW3Z%^?&b%*L7QMHbd
zCFplLaRQpDbJ7F&+@<;;8n^4FiSVOa_8IumJvsspvj>}w>yOK59@4YLC72(y2mOp{
z#PI!aZ2TH0=+6jj0-cV36b=T_icT$1ynenB1<p)?J8I|3xUT@Y593h-mVFGzLnD}p
z^@(a+&r$1V5>xAFGE?hm3RCN9DntIMGniVJGa2%^w*7?BAJKl6(YJA}6HG?yjW`14
zMvl|)so6c$S@lEI_h_-Uk0;{VF~tkO&ddF&CXtI_yw5*ZA?bH)Ax*yrx1qOV_!wII
z{H#@iZbEAZ!W#6bY}0Rm^7{#GaNi`TD~z<P{}--ZTegMqexJ`nK70%<DJR^Z&&!Ev
zNmFEJ#>odfn;7#9<b0VvHQ?UQ+}Z-q4lqsUp*4b;oDHCGgfMkp0~pGzz5_3gF@6M$
zVJ5zY-B>13g3f8?U>Wd<%#{deCNW(H!s<CDdp!W>nO&!#nZ+Co!?Vd{Qt6w$&1|^^
zyLrr#Hh`Bihui^p%(SAqJYh04(0s=nJqLJ=gBjTr2H!J_T_D{m52y##ZSt<4V9-^5
z#{}VCc|!z$Rr};KeZb}`FUyAeVe;r8upN=NU52uw@~BC`#mh&mgGz$@z#4dQTD~9|
zCbHyFO#rwce@9R4hI}Q(Rqn_$8$)<c?wCN&?7lpk@TKx0C(yX%^2oQyJ(EAvpuOJ7
z*RMcjoD}Pqfo+Q-Rsz6XvCkEn9*PDSE>*q?ue%`KuV5QPGgPr^12hjSHjhAZT(RN;
zES*r4E&%6Q#f(vaXDAGqkJA%&s2YwN3{aB;&ya6Au`TM|EN>m+SyVpoqbKr%qP$>h
zur(R?!;Y5Xx?no<zjv{2^<>n)<uAX1wM}?FuI-~*;@as%BjCGkq8LSwGZ^1hy?$8;
zN#7BV(cA;dM!?^}_m}c`|3>-I%w=MlGYY0x)0%7U#<wV5Qhy+>%YS(dij`gRQHf-=
z4gp(LiaK~3jHap^j6~5nbtcv9vigM_W!dUV7Z|&%mLw2eWzWup<{NfPZ>Tu)DPK`l
zFMiPgXvS%qr%?TqwTo(C*-IZY9y+`A9u(@O${%CODRO{;huZiaQ&ShY`^*~}sY;j?
z7VwucMn631hs@2xNOsG`ELhtkUmXd;eew%+!Qv}dA<VBjAb;=;ejSttGys{ueD^yf
z0rJ<5GoT5SH=m4bko-X+R72#~hoIu2@|zxT^OXElERuM6TOBlS$-C`=7uoWpi!hNZ
zzd;Mk+j8}7;O@vf&{8~KeykUS1@Z`5pccwE(+he}zOoC1_vH=ppjj-RL!qb=`L-&W
zwLO$KS_INExr4%d<#MhDm3b`B><?juJYo@mPvsj*KvO9%?+8GZJU;~7P72n6GH1os
zLL@GV9oTtMZC2cy1n;*hcD;Zz+Z3B=mVH#Ar4Kn=v6LQFw&L|E<Z=|ZITp|Vw&M9c
z7|c_2j)F8_v5XdmcNN1amQbj;PmAOt#ekVe?koJ}0slaed<99VV&F_P!b64r2y%}U
zo!SCdu4tVMvL}k@Y~(5wNi@PfQ~a?E)RhW%GXGrh^B&}0D1tvI@%&#YW>`S;T487h
z)whZ-t%0vrEb~ULMv+~Os=Zg#qyGP+!l@9zPl`8G-!F<#4K%+hep!kdIxFWUqQ0Ay
zO_xEqMLFX=09%z~Lt)TW`BxsAYrAsZ5>#S`GCCag+?CC#|8ne9zWofgUCN+*0KJrZ
z4nWmg>GK!N?^d4CL3NL^O<$DlQ~uluiLdesg$fQT(@#LfPx%wY+X9ridGO+pvIW&8
zNIC94%7T^hc=&W!d2JWG2vY{d!~3JkzH8xHxYE8AfJleZ-WP}{<+rZL9#fvG54ITP
ziCysGxbjM008c38{UD4}KFq-@a7uY67l6~sC%?g&MCG^+U`tlsi~>AG*`pCu(v+?B
zP)S$1(z5WZat|i?sto0rEC9|an{e>ryfTEQQx}wump383s63Df)yv8oHu!x-8OtKM
zrfiHo1=V%sl@nmQsl446G`Ez4cEgz*<;xtX<SOT7qlS6PDLuh*M|sx-z+I)Z8%cq3
z5rvkEl!r=?+*8`Nf#rd+*;mx8Sb3M0h7Xlr99Kb8rtIQ^q+I!1d+0n?2Hb^-3T4s{
z5I$AL-$hcTd{5)!bLIZ!Xp)!8<yz3ZQnsRr-5X`iCwTu>X}pKBcgk720H{%lt3dWa
z`Dh?CKPqFcf%CI+*djF77v=I`s5q$#s%Y`)teWx|Ko?cFUqG{2wWa}l+p2mv25q@b
z_1Xfv+f_5v0J^DaXnEkSYQ#a)L*@A^OzcuMD}V`4RrF-wyjAx`K<J~&PlU=|)ybb=
zVV^4YAq?(UwV;Xh0hRXvQ2VK-H{tO8`Kw0k2L6z${45$cP}Q>=bb?jVMgT)pb#mwx
zQl(LNF-)~87P)ZM!C|lzp^{sn8Kt@$3e9L$zf^b_qgqDG*H~2x`Z!LiY!#r6Q_Z2l
zGF~+&8+H>^&F{m*L{&u?&6<-`ooG3nqT=X@rmD8A1wLI>Zy)eyRPAV*bw_n$4|4gc
zpJ?e(s513~-6GYIw{YgZYThW6Jy7*L24RV6@nOJARl{iupiGq~gWHc(L&~A@ST%*l
z+$So-ML6oD&P_++a8@_%1F4Jp{X#gkS>0wFoY|@l`w@t3YV9o0Y*%l;2up72XQROF
zp}s*8t)1%G6jSn2>u6Z>R`1M&r9EmH2f$wS5{k(Asx$J?PW#oP&O+s&`UQpE{M3#V
z*uAMP?Ty?mhx)-UP|a1BJw*1l`spMT-ceWd1R`I(Xd7|`YVTyw6skYAhvq%Cp*3>%
z)o#7uZ?W2@Las#3P^{*m`jG)Xm8n}%;GtYyLQ%5EY72!&D%5pi;NerXd^vEH>i3hO
zS*3P-y9i4!)%BI&ex)vo0nJ<W)5`!>t7DEs^}X8i2fX;89$1C4&+76&P{S|k1-*g)
zrk+djA18Lo8<^O{MqWdi3;VSOxnpc!62`FUZ(!j#n>P>^PO!uFfh>;wAr9?(itX%Z
z3DN|X%R}}w%W<%q#7<lTnq*ep0K!yu1Z^6nv8m%xc81Nk0@AZ=(Lx9_*#(oJa*q8L
z3t<*}E)T*BY}k2Ny2R!M!tQ0ZoI2F2teK)f*Vru-Xt}{I{)9((lieIf<6kyAf|mC=
z>^yoAZ?k&p3iH_BG|$gx&tR8Vb(i(RM!Twzt$Yjji&z`Y?C!I^38?)8Hu4v^R>BS)
z0=uQ`(@Ge8#FlSEuAEJe1WN_`_7*ih+m5!)s@TpWA$-nGH_-R@ik+DTFJ7}lX>6@#
z6Dj8Nj$JhbIv-e_3lJaKGK#K#VGHQ<|H_68gcnX+P!9;5ISa+xUASMKz|qazhHyBu
zm0O#FWE<C}IRM+a``6*98yB?+obFuyD&Rc0$LX~Fvx~d99jcz3$6vsEbCJh@@ZqkU
zL9&O_xxlBroGA%DWpGpbqS~3<nEptzxTmWiyug)F6!tRrJ4Fbua6Qh!(lsvg4LGlJ
z&si9}$yH5)@D}GY1Y|kf5?cP{a&Py7#c_vo+YVqp7xD_K1>E)7kQQ=QPnf^YDTAqj
zxoFxgE9L6bJn|uTkGLOkZOc(s&Sh-|{0Vmf%V$*u_apUz&$yXos7oc69}W+na|1>L
z@PZ5I0F_tV_hXQ}<~$yu?5%^_`V8(@b2-Bxeb422Qmb=~7sKEuZZ-DrRiC*DEy4DU
z8;TPPDkuKqIB0I-bF+|h;k!)$_ZGf}_C~kzpDrVD<<|wG65IKEf5Mp^{JB@K;Lf|0
z!O@-kH&4KK@rLQp^x_?hXyxn8pFaSaJ$xG{NcZyf&cUuPzc~`Q{rpK<h4}Ha62Ruq
z@5UCfDv<9$(}f_ulomQ6d_!kcCX`>03%A4g^}S)~2>-zgW#RnehsZ_np+CTjDE>E^
zq($?83rJ%4#*T7GWBD@bHBa)5XhSuQZ#@m%@%*d`BniCl0#qiCFFp#IyL^4>8VdNF
z4B(6SbJ0ld@jWKM?gQS@4vrS{d02X@9`Y^Q16Rho&|I&aAG990$Naf5;H=;~(rEaU
z-`f`pO;r{Dt{rrq^DASJd&NJX9_lrpkp=u)K7@87s`*q}aMbY56-eIm6NjQ|pZFzY
z{xkpYG*sd%Ul0${Z@euAaA)CX50GsVBCmmZvv6CBvMs_v3hr+c3e%zDD%e8>e1C32
z|3awl5T?C>j)ySY0iB(Kg0{&#g^e`3^Adh=LYa^7WF&yQh3mh-;9g;o0V?~1P(J`p
z2!7)sJSohh?&_5A<|3LaUT~){$!Vc#A-qTw66lLb7PiV!mLjCzl;QhJ6CP2#IbDcq
z1N>QG`CeGc5Oys@?wpW7`|sz4u>(MJLFh|S^@~D86@0oZteFSWE5hjs$XyqzvOs!6
z*i3u9*}_mVm?N|&FK!Eqbx_F@s@lO&z7TK2Gq@{+O@{?Xp)iNG<%)zurO<gG@ZTd>
zEKG<1uvFliB6%p>rM7q^d^ZTWa^Vz>=}&~n*$`F;(iYG>6H-n=SSjcz`uSYAOj{!_
zgulju?3Lhk1ZA&<6Ev2;6@I9Mp=v=f8p(Ty(AyR12jOxjG}|Yk3ddYjpM|3|L-;DZ
zc>u&W!QTX-vsgpXxlLjn6Wl)_hSKunpm?0#1b;Dg5mW-iQX1L=#k?QkMUXh-7|e%=
zoo@jUDt4#+qcAZ`f#irdI}s}3q9da*vJv7dS|>z_*J$Y!EqY#qr5JG>EzV-ax3sK1
zAr|wnbW%J-i^5Z4W>2WZi&GlI?rAaP6zZEOZYjiLN*3#7BS{hO`a_s5&g=lqGvZoW
z#$||OX@4S9?1!m>DobqRppol>xF7)8OXAycFnC$aV&L~x@%rz`T@$Y!MDB(dasj!U
z;!szZ&lb~PfHX&}qGx|w%-RKbp18XJW%=SKXXNgRG4+5e6o=4wT_lRMQoJv^QtbGF
zIOzm%CE~>*`u<AA*qPui6aDtXw@2b{*P-)R>`JfK6EWQa{8MoQ?W8^vf5Jf{)fdt8
z2-vnrgXSXfmYCsaLmw$*2YlKsu{~gZkF>G`$zG{XHH7=5d7emorGA$H*e~5S!QMe>
z$t3w~^lZ`+BfRjJS{#5=0n%4m1Rs*_lQV%*x6S|tNt$NJ1xt-mVd=0m`vU-B(o{1%
z4438xfGtA$a}<PEr6LL^U6Z0{zu>ww(}(G1c4+B@O18A(FC;nAMN-U_95y7krGz*n
zdD3439>g8VK;g(@=@U&vN+kIs)V55D3P<up`b@F03h6oRK0lRy{2R$LX;~|ntCaq{
zgrrKEwCaD6lZGEC%G!8S2_Q`z3-6#so8C!*sF_4(W17F71NVL~Hif)JHN7A${oKIU
z>TVKTY;8z~PMa87Otp=rE&X<7)SB(N9&ob5I~nvldJh6arxAJJ?5rjyx(w<ERM)fp
zq2KL?GpIoKQP05NV{>nBh<-dZ7j!)}CvojnNkORI(k9UL8BFodez&jS+P@o}s~NB>
z1UdtcVZ%o?XtB?j?l#Ak?l7>v@&f2KF~^3$vIoP~K@QP8Ba{y@+r|MO%7ib0Fq|1i
z59k>4>>7*e;GY|t<pH%FY&)FEQn|D5ufUE6yMiVQJK3Q$vh8ARJ5lDzx=}2|i)}{{
zF>kgD%{3f8>?m3R>}LHaj<AQF|2Mr{>`E(C_p#qqA@OCm?}yQY>~tMS{n(rBAw0wu
z&=f6@O{3^y5IdS`9L&z3MfzcO&0+w;*eU<OwIggzB+8Dm{Ld&0XaDVjB!WFS8(u^@
z*cQLTZWKGF9!R5E7Y4~O_9pG1#IPB(xf9Eltbp)1TlN{6Cs-8)RZp^Yl`s*<eiV?L
zV*lQO)`@4676X^SF0F>}G&_MtpG4M$763_XrxkD}nJw4@w^P_PJK$3)`_uGP6sEC5
z-Xlq8_a{J_!G5EC=}fkP5uTo7*Ihx`d3Jh#2(#F#elT%?{jwj<Tx7K`VfPYS5a84L
z$GX!yw1MUgw!>Yh++;H(0B*6HdctlttG|wCaGO0(@I3ZzF5q|A)7z2cv);X-d6(^i
zqm8Np_MaxuEM)6YV5W#2tp?{kwyRIjk7mcyPVldU?TK9k%!l{VV|~bWD+a8LUAPft
zkJ#C?J6_ICXaqZt*;%xDdBS><oeH*yLZVOE#k3N8#tx(Xxk@&(8_KHK4L0PSvup{>
zy<nsFAbH8wI}6TN>|Tnpzh*Bv`rw(pVcXNj=UdjD4t!Lz{%2wE9UDQX)N0snjiK_9
z-BgO?6Z@EYm9Oj%`=I%a{pC4Gow&(W5IS?ZVmPyfdvpfe+qg6w8&<h;e}6-n8|O3+
z@Eu%A6;#~0UxQKR!KDT|knZIErZYghxJS2;^W^Hx2dNilqPea&$5tWd!+j|Rem56O
zFUKD4>JsGkar-EG;LD9B*Y<NUXW>&2*Zemm!JOR(c0;)QJ^+Mr4@=NMhq?XKtA%mR
zM0$%kSv4IgJIei}15G%0iS_{_xKk9=isYQ5;Zqc+#l&9~&2^%4OUJlLbX*~Zn=6Mf
zmizt)lH=UAu@Ii%m_*=Ca!sg3<G7BC!Fh_iL@R`NE~pSqnZWg?z{F{8G>4ica^r$%
zCnkvtqxgL?cYYwGDO_Gx;8VHbG^0!7DvzKnox4nt!84pD2D!7Gj(V63F5(fmGr4~^
zqwE~_;0HL9#dYkA+F#(F_5;~P&a@gTm$)f(u<tVWlDfewT=zVDFITyYwjgs{;~sQ|
z!Ry>V<l+skY$l{PxvtNlbBjAW6qd3%9qk0?aLsA+Etf0)38c5V(Kzy}%HtM|hRPjo
z_7!mFbBE~k%Uv#&;yDG}nJw_5kn1=BoJHJOdXo3J^aXI{K9}+j9DU&65-c!Z%+1;d
z^CetIIt5Y6iA{ii$dyo>qKr#f1=UBKiq0ODb5+sEJ?1(@L-Pr@vo16%xJMaq<|%hL
z4wjyAhbgvS$wktHzlsabf!*g^0yXRl?&5R6UvgnIi+II3L>!^U3P&~#(l=a_4EXkz
z+x{C=tGVEAsP-oQ4xM7y$2)C=<^jG<HR^PbFS&>^KVDag#Gmg^Jy-zWRSWnbe&+$e
z1Nrm)Q5M7xTL2G(`7{++Lilm1a5R*^POG%Te0h^uNW=KA3y>V)-RA&*ln*k4Eu0@u
z9d`sj#OG!ov*Ql!FUIntH$&q%e_#&WJ;6_C0z)VH>;uTf@nv)x^AvwzG+^=kdfMwr
z;PdHQKFzBsW|+vgqMjj%_jv}FlKJ`c<Wu+tGzm%NlNZ8=G`=blNjg6`5AZX5`))|i
z@&%)5Zl1ya5CPRp-Z&V^IsRoboH@_mr!h8*Z(9TI3w$|Ezc2Dk0)UtJ4|G!OGQa8s
z8tn@I3-zW~`QARUea(*VD8_k{FO2}~7GK;0&nlZQodT{Le!$;A=kh-%!_IAfK5dHT
z@ly~3Q{Cb9Z9$UH&#w>7yS$9{rVIGA`CuvJFVNY?B7VLX>Tr)w?GC_wz8B399`G^e
zp;^oir0tXv-p{cK&X@5Lg-RargQ;UE=QmSy@G(DY5P(nkTPHzN!A~6xm8bkcdhed`
zvnWVW$!i}VSH*9qEsE#-$5z0-;5X1AvX}h1PXN5)8>gX4uX*3q5We9n=|Ij~zDWUa
z)%*^D&M3X(L&ri|!$0^Qr0;oKcjP|s8?<P&k9@QVUVP%){*JQGywnR#@`aDT2>e&x
zT@TW4{NkxF?<Dl4oqcEF?}OmnB&3By=pyW*rSxXu_+Dsk5n9lkVyiH4JXp2~K|u_9
zK373cCx^ES%@0G>P1y1TmUak%ba2F7NSuc<523R=4DJ-<bUI>}(DWeip2BC^9Pkn%
zX$#I<7&01~K7t=jl=lk7zroTzVa7U?`3haeBDY^?jcsVv0paElICD_=4V(^@pWvs5
zL4QHL6G?!OLnGTEp~cUrOrUV69q>Vd-xB14g-3^AB1Bkc0}WQ9G`~MA_)=UgOsMV!
zyGMkcbkO*ykV{7&!i5z+@GwHCL(}a@!O$9RM+u9&A{Q-OqULfO6UNdv6(dZbQ)aQk
zRQv!&bzJB{=ebS@TVmkpNkL1Kzc^uPA#$gL&V!MQ7n}wFpCGKE!18HfBQ44j1s0u%
zDoI$o5W-}^Z8SJjgz2FWrV2BnAWRb;QX8fVaZgZo#v$a=vg)kRdj?1|gnwuqmML8K
zg%{_9j<iX3Uij`GSjrM&BH+^n;cyL-i^8=1aORRQ?<jJYg-LZ_;)+mrHB4L=hSD2&
zL)b|{@|%KwHrnZyFe@IM*+OY|Xyyne3k>B7j&-zQaa(Yr1HpMhGj|xgBj_Xu^M#3@
zfw(I;^@FfL*prK-P&lNAut=zC51M;|<^n2nU%<MMmcnJPP>Et;)I6w^2w`q0D-||Z
zpzNWrkbYiNCfr#8;UnQt95l;?{*G6mc`S4s44o&!w-eB*5a!oM;ZtESh0dP|rm0}7
z6c(*RovMT++TndJIOZVtLeNt3QV{o}hOdNiUSN4Gbo&7K8(~*#XucJi(q~jHI7?u8
zC!FsL^EHBwc68ngZ?ow8`ye!;KK7$9@>d`}31iNq@Uu`kAHpv}ChaDC6{;uz`Ayg{
z9WCP|?j;k>qRI`qO`=3AJr{8qb+Vhq&nE%jBF0g8d#jii3cK6HLD|T;ifc0g*e<@J
zjVyQ3Jdb7`9%B5@$nF$BQPj#y%%CN_x9CA@E+5fCdjxyMq(7jtPxPb^fUnqzp6Ef*
zl}`TpiA(5AslRC2fFw{<&4Gy^v85{v28-X#M*|%eFI+(`OkDZ`xFaH~g`*MTE$l}*
zRFPs-ETmE544UXgi$79C?3ft&2;4E^Uo`!X6~EB7*m3bRg_}-@?la)%NzoAq%{cL5
z2-r@EVRQ~MUK~MDm;`YTMcz+~Gr|B!6zd;Dk|bWrLRqpH`UZwl#Eu_9?MM~p$03_0
zmOO&r>0;w2&^aSUjz$BY6$jg)lOf83QI;tV#yL3EIdM)M<j#w#>F_X1EI0};E{ORZ
z&@varVYCf*Npu+o^OwcX?Ld7+jHeFusu)b&`ZaM;4ydn-t7+PHgBOR>=X6u_@##Or
z?3lF-WO?EOH&EXZt2+aiFAl9i&F+df=L1k6X4B%MPz<y~rAX}D6&CJ^rY%spFQ(BR
z<^yr~0~jh6%jg9x5nn$Apj7;KD;#_%x=|FeOuWz$xJP1IcW{=AV*)_-Se)*lt%)b%
zPC6}DAzt(Y;;HzV)}qhEUOdVwMV&uLt3-7ogwMs>z5u=uk3N9#rI<_M)>q<F`t`+Y
zaV3qOZ$x)9489frpqON}*oOi<@5HdtfY*qMttfjhy8HkSKZp%hI)L~nD#)o%;zioJ
z{VYcMpzw=mI}ZF;aadin);H0U&c!)N6DdyQEdAaFfKAexk0{$B{q_mMt&+J4CbmgQ
z^jut}M|8k`yQD9Gqi#}42T<>jrVRwnU5cX<Q6AE(K6JKbr&Owf&Ms+iJviejb>9i|
zUecO1;P#g4(|pZG%AX3vZYhG!hwPD#(5SLkT204k_DN-Xk@!lL^oxc4(!+njazH8{
z4B<hkmlkk8DeoSH{?byKP6tS<={-6mee#y!YY3EF1(*+#3cKJL21|o}hfav(N5S<_
zX~sZ!aac<9L|K?*q1na}=?!h#9F-y$A_<p9kA<ZOsqr_|K2oZ=3qX|gJ#ExQOP6S2
zc1$Wi0+kr4&u|E1B|i;Vj!V=3h9SoZ=^l0DC#5+QYmbxE3Xmp9gX$x9T3S>M(nRU*
zYmg>M$5N3bOLZyEks^7o1x>2-^%mM9O`3KLZ0XW#3RIkt3jRPFo|VKyfM-YpX@4YB
z^4Nv4bJB~Buy9@)5DGw+L;Bhg=>_RM&8{v=eG^f5NqSB5smoG7I;V9-I!(*8tI|2*
zz9xO11kLMGH4F1MqzqaD-jw>d!;4!|5;b?WbdJt}=SaiQzz8B8z!@|Ik#>K9W}ehN
z4P|$v*)-neOOBB}VeqcBeKm9nq)s%;DU?qCgyg>TEEs-2khCRGEtV{^kvx=|&`*=f
zq<gdqc_bB4PxeF#iG;91ilAQ+Je6kBU{)oyTMdKHr6I|{y^x-aK|Nnf&3=ZxH`1h7
zXug$(IEFyAT3SW@)H_LILas*g4u^{$r55y<KS?#yLGxLfK!;hrNPo#;>8tbu1<Aij
zBbD&NNmDrr+|HW7G~_mEtn_WWXsnU2yIGS>J9Jw#r<?%Ts##03g>9N1JwWEFIhyN0
zvu)R;({kEPGvfmacWAcK5ioa6GM(1<(7dHc@=nd&?||Q>@f;5}Pt9rS9=$Zb=fi}z
z=4>$lJ{n~QsO;AKHV4Tb%_{mC)Lu=U6=2z?c^ZbCuO_Q2lKmQGC2D^_Q?;GW79G@#
ziGYrurdvHE{+bD4APvy8XayG!Y2MRN6R7z<05uHKwEGvpV9j~jx((4}Qs_EVvy66!
z4r{u$19zCFjU65y(M+S`Y)3V{AHvaa&CR)hM`&C_QQb&QaUZBeX<m$G@%=?>YC56t
zm}c<@sK#jW@<Dn+Q?D3oCpGh^(~Z+C83}_4np<?v>9pnu`IM;XeH?5_nm)8VOx83@
zgl3AS?s;&hY8o~`S(>Itdw7wqxn>0JjHc;YaGurl{|Z2cCg%qja%5_pM3_IPc}`vU
zc}-gnR3=N)EegO3npItqT-10)Ai1Qerak7%nhg{tzM{GH8Mv#O{&ivLnr0Ubl-D)0
zDUx?XQ#uJ`H#MnIAiJeuo5QDUO_MIb<!I!6kmPD+97EY{hi0e)s(G5iO?YZ|G~Et^
zCSPNqwk*`_TL|tV&0~76?rDM}Ver02r-bl<=F~K37HhIHkUZ3g)ESg%#@2>dHQwhz
z_FQvuE!ydYMn%Gx8h;wbUTK2z!SY%o(T^_PXdLNuV&tu60PQSRYq~r^BfitLYKB_W
zXyX2a7w<I#%>aJT$SJV$QB$)Txlfu4w5s~7>9icl7tIv<nZj4i#(OCHrunr7=AE=F
zsMmAWHgJZeP1**7;Eap57sWs~Yr9jYw?&)ppi@;_wJ~FnY|{?ifvUM`-RP9scJ1Fq
z@WM^IXC;L0+8-K%#zQ-+Ge~!8i*KX#c4^(_L&a0;L?67D_VNIfd21UlLzR5Af6+;=
z-CDy~xVA^T<`_8lYAe(r+ozr08TNd&_u4o>vtR4K7}5jU!SsudgWAY?pz+g=$wbay
ztD@O{fYz1HY#!3uX2S14?XUEUiy-YG1#-dKgArg0(FV{joI<ttX*PFQdt(FuVcPWr
z;C8rn=>%{_Xgvdvi_{Lg51*p6!@r}|ShV(?8Hi)r1Ju99XqO*AE>>%&dChTcdLpWJ
zLhIZRUYyj99)Vn(b_)ZyPid7E@FHG&j;5vw+AVDXKdo)v47o(@x!G_gNqd4q1j*V+
z1?;A1L&5=1)qbT-mo)7!h;2Dk>DoVB!FEPlOhJgV+T#>I&(Q9s&Du<DMH+JFv}qym
z>Acpw6ZkBxnwE_hv^xvXY8SQTGL&7?CWWDfm$iBtU9M=o=smuwRg8o1nzjWUue`3k
z>jTak+Cmc?y{YZW!Y9Wq?Vr(5&DNe=2TyafmVuDwYWKK8cw0Ms7EI)6kI|O#9jz}#
z4)V2WbU>g$8@3T%6l(jN1Y40dl@1o%(`NevcVGLQBH<6T#x@WZYd>Z}vqU?E&U%(=
zLt4X`hguWaD|2WaIC8Ceq`g6l-^bc>w5)le9bN~*3hm5+Ks?oYz5~rO?R^@zE448c
zj;PW$6=CVQc6S4CztC=N3HVEGQ#xn<N}EG1^IE&$8*tUy$qS+RPHU$zsz%$I%HC^7
zZ-(0+v<{YjF!@pYh>o9q(vBDbzdvht^#JgTw!j0VU$x~kQTuP&$48Jj>0YTJbkSw~
z0NiHXMJ0UNqHA~+cDL&MWk|N^&bWcaRp&{2iQ9G8DTeK)3z>l`?a<ZLK*e1*pb{(|
zI%h`|bav_zX~ycM3*QGFZ{5at;C*!K{)A7vb*t~e#2($xbx`fSx-Qs|RqfMhvZ3Ou
zJ2?Sf?AI+ijO2h$Lmlfu-Q3S0^V3C8RKj0pqfabAm-Z9}59#XCfssJnJUR;-q`PsK
z#=l_QPc&5x(Ovg}rBGdedRq?b4pBfpOn0goRF3HU0suU!`@9uw;kqrop&6kIr9*6y
zy06qgQ9AD-up6y=aS$rUbff9@iqXZq2TQE3Y9}ll*M)zEqbGEyY2V|dZkR8f$dA)q
zp<eHlE|2Dc@jAu_hy-0LdOuF<Hu}JPqHfJpkS6KkhQqbw|9nc*{lcOwUH983aG%jh
zwDLKtOQtiK8M^u30Lau`Z3C8bx_eteeO|Yv9}H#bhFD?YqOR*K8vico{92;fF6(Af
z=Xpifh7K8D)pZC5@S5%$Eo*M*x(q??rmhY>*ju{8wBwwuyUKwrN0&tLk6c|V`T*|e
zs^VZbU)PdW8+Ubow}7xfH?BSag}NIPpjo6-4M20<)7@_hc=P+Z<sFee&^4i-)E4Vz
z%z&pQy5Y3RRjRWj0r61h?K6A4*%9Ln>yLGFcY^GRPD^`x6}pbpNk7$Xr)Ty|=URz6
zRO<HFVZBNhP=w^Uj>m?d>V<CaV*p<2{3uTTN|*W)PQ25#l*4$9?)+Vtd#_7+3gHJ`
zJ8F=Rx`FjU_DQ$=AC!I8-FMKbrZ2jS6yW))TiY4AZ@LgdIO$X9h_SQ&m&PdDq|eAe
znT!4^{m6B*ekn~sw&`cmYSmT$2mL;DyMEa`ByRcynuYGrcmD_v-Srb_3gMyu=P86c
z^?yu7vP)kl9S!2GcO607z&`pPC{DgxKQ;%I*`tqEK)6@Gyb8%aeHNX8@zuxBj^%!R
z_Z={JK;L^jNDu1qGa!5v`s;K6$zMO1LimCDbOtOzdRGp@V155^07CSa%8?7zZ;wNA
zSifG6=NYDdxQdPeAJLzufW=Y$hCmn$*ITGbBlN>-AdJ*kR-+cj^ig+E`xyP6Tgb)g
zXZ-|~<N9k9PCKD*NZr&){WNSis^avIXyfFR{`WEPH(p=YADRjJNu8l`TK|~3)kOVu
z7nCLG>k2$x)nt7|3Aj`A+lRxcbp0mUV>_eooQ?)Qs}H0hIYZCV7EPvpk`m_6>6`os
zyXW=edVxDjA94(37xbxg%=@zbxdii9^fz|F#8rK7`n0a;$3BGcy55~8&o}gO835eW
zOXJZNj$8T%Kf^?}UPnvt9R2*OP|el%djsKZ{i{Hj$k%tJaLrwP#~i2>=-1I+WTF1M
zw!jzZ<0&G0Pd|jV*Y4}RYUfe<KoJ!!)<2@9Y>B>|4t7iRIDv!rUjN$)u$1egED%0+
z=&LgUe4?Ls7KjSHwlNBy>bu5(`<dREHZd#pTj^v<l|GyLg6I12ba3K@{wSSZeyLwJ
z1EjC?6Et9Xt>0P%x8LYTF97#j{Ue%A)#%$&ob$ati+1Zj=tqr$p^y4$$3gZ<@0hEE
z^s~OG5lFx212KB5zUs%(oadX~I~=)9hG{fYbTMq(0K{g)@1(iKFouTYt%gEx2)7x0
zw!@&Sq0wWMZ8vB;AaOJNMN^j@hD8(@bvG1WhtR_?Re_wRVO&pedKq#Y^wTtN!$x|{
zK868wP;<9IODmr}hA$I=*lYMi+u{2RcaKBG*TA0ve!szY70e$nOsA>OK||nes00{}
z(J#yn8G@>T3pA{xcuSCB5$#w88#b2WxrP|}(Vj!7A)cD~u%RJGfx9rna5^S%#L$lc
z{-~kq8QLq{aD^r$QHHDW5JnpY7D0H-(2@p+7=xO6tyse<8X=Dx4%7bk3B%uXvh1Yc
zF9&>zGsFd=W(kJ(H0L;N(6@mw(cn7{EJ=ov`+z4K-d~pE`%5td<RF`B_*4b%G{X^^
zVx}9?=tRvK!_RY(oHb-Ap^{;^QoGDHh(kb=W$?X(<bt7wR&f^%J=?+HCBxKzkX$zW
zyA5Sm3=?Q~@2X*MeYkebFm5=!xNf-mJ*srWaIG6n)ovP2QQR@dupu2fxrT{RXxZC_
z-W6z)Jj0KTkh^0TMrYXa4H5Jv-8HnLC`^Ijwj0<A4TI?XVUc0)XaMdRZtVceeM2@K
zhc7W)*TI=m!)n^4duV7w>#j1x6mQ@j8I;$NILZxo^gui|-1rOJPYk2!L`{Xk?IVPh
zh6|(6BvpnPv~GKDs6*Yy3&Wt6P<d(4IV1PVARh*r*M^oFwAvfPHV**a8XUATtu}P9
zqwJlbQ6^lgF=SB%KN^xLQvS(se;!)qv%|2`1;8(c_Ulpj)etir+}{kvw5R1{Jema>
zXQPTjnwyN1>A|`f2TwqqHXC^nWm}A$X|l52sF(`4n=zWs*zYhtrf{^ok)_wl!#HR;
z;5&^@R8KGCh#9c!ZJa@2VIQNz-U>RqjcG67#UA6^<w*7#-yVf<pONnhHeaLLT&V6h
zHfRI<0b{~s*ga@0xQ-_EGft-u$KM!EJ6!?BPt+M4G8R+ZG0^A|4VEC|&<EfQHU`i{
zH3YxkM>B^S+uTI%urbg<<4KrtJk1S{82!?a95uG4^9|v~pbG#-7`?87G}73Y;_p$$
zrL^4<ZTyS2LXH^+`U4PSOqhgRtnt)fxOUt)i=yc#j5BD!JZV(WW?!7~fCNWR84Kw#
z#T!@l2Oz;%T1?;HY2(6{C`>fI*$uywjH@@H+R4V;g-BA2@6}LAHTI;%Rhn^CE3l;-
zJ(ogw#`u|nu4j!$r@~T(@nAowWEyR>r*_WR@enF;-Z)+ZVU{s=45%*{rB29QG}c)T
z>PtpLLz=2xHkPgh;)?NZ77DK#f2Ypmnla}P>U-U|VFYMy7zaAR#7$#!+9tVW++G`z
zGDbHAO^#8TfU;cU*cv3ajgt#tDbG0d0C0DVW2_M78@Kxdch~3}k6eNA6m>#{#+}&g
zcBqPsi|7aa_l$38+`ezD^By`6jL`>>D>kmb31>=--wlOIsj+b(fDes{L!nY;ocRKz
zkBmoKpsd`ukpPd4&wC;F)EGyn%%2%$9ni3q#`b0Ksmj=#PTD^=x>0}e!q}rP630v9
zh(uKTl@UK$!FOc*r!DIA#wZ%V_SQHc04A!9zo)?9JLBm0$kiBM9E4BrjdR10`(V^f
z2kxWM;sv%(#!fVde>NTohRPRX*?LfaHSYNa_&4K(XJ}?8(;5w)owF&NqGOvJruOuk
z0vFRX9)+7tK{O%SV)CTv;8xR88OpYqCQ~%g)pVf<?r%4}eF9Q9Q^P{wcbI-21TWl8
z<6A(}!!(ahPwX_US^@Yjlkf(bo~Gl}>RzTv-QcLV>FGKoKBo8WA>3_pc+xy&k175P
z@Ow>P3qZQhG=jQ!U(+25ukAPeNvpU6rU`WD`=Ch>;Gv&s2K6xhrpUjb5@0H60+vIj
z3-6Hxns!k~6J)wWC*Olj`JTvyn5I#ELrv*4$vSKru@uc5X6oWNgzOQMjegg0)U<~J
zwBe>cy^uth)}9AG(v))pCZbGPamYoR4tIfT$4rx5z!qb2{*1C%(_Cuc<EAro8u)~%
zG3^YVG`X%qTf~{_&}P~xlh7DRyy^Zmz!OZn55mG}ldYZu*+kRjgJ{_#(}3r|Cz}qO
z0e6aNwgj3~(<MECX(q=fB<ZGVI_Y@E)F2apOjF@Q0M3~f&<VQprjvA%JIiD$0Pcb*
ztUp}4Xo?$&+$EESdbG<X5B#uJb;Z<&eu{n7WL-@gSJzD1zrlUoq;3Gx8zy-sayLyQ
z^MSu*`ba-5$Tp?X+BwHm84Y}{X$!qxw@v*iexGMr-4MAurgs#R$u~JVLFKMVP7{Oz
z(~{4~6`F?Kffq%lEi`W4Gp(g<totT=l?>nC15>Y2$QGL#u7SZ4Qz-o@mQvGWT0=ZE
zEwce%W^#W5pB|ak{{l<prZ3b5KQ{Gm2GS>{Gqej{VQO{@wSQ`|`~=)H(_%U>R%x0;
zXB(<aV|<Z&Zff}onlDU?kHL$Vrf;+-Exs}}F`zMCo36L^nK!GEV?6zxllLZl6C@u@
zxwO9iXnNNSs-H}CY1;nT6dDE(znF4|K;^5cl-{6krpnLAIhj-FkfXEtCH<;olUYM&
zDqPIB_dsQ{c})UvTg>YgLuIS^u{%_@ne!9jjH~$_O`^A(D;ym`<7PfYM>}?y3va``
zyE(KiXgtjGVv+1LdsD}{%dDn@JD%pJ?E&yI_oNdV-sTgdpyFeGPrsGiZBG7(vOVT5
z3z6(Kcb$N?*k>M2Q)*xH&x@hC-`w35&E;p#r*6*Q?Dst_-2=?5h{8i=`%dHn&1rO2
zEy(P26vAM0;wyL>VqWqWJPb82+5j&On>z{M4m10Yg54wLHWXDjYBtb0h;Z|`HNZuf
zUFhI^q`8O=*G8GEY*2|dbGt!(%p9G9T#UI*8Q%h*lR2Ko-Q#9=s`d%<fj?m4q&bJ8
zwsGbbG@CtT?(WliPCZ9h8_1H(*Nt!~+3ZHK^%Qd|izL;&Lqd{fHc+RPZf<lEnrF=Q
zenoQD{M|QDW|+UTfh*H|m%in5<}y04d)_>ldYdfsj~(H|1@p2x09-Ur3BrT8WELp?
zec6278@Maxe8&NJf7Pt)1@qU;trJjq-8^&-Xl|I#ECS6<b5=BxTjmuMA;~uX{x5(z
z=CyQ&Dc79R2(`X#o<zT$%`-o|gt9y4t|iFjn{l=QUy(V9mfi*C8PnlRq4@*-I=aZ*
zj8-o9%=Z##K6Kx#@P}^?%#C|Mwb&d>zd$T8<7ce+ip=ZJBY9}ve;AIInNLw9>5+N(
zWN4O~|Ih>X*jz6iu01iEZ-KPJyo9#GpPHM}WaF86I{nbB(!7lRhEbJyPa6Q9n>$oO
z^M$$3Jlf}bY2Nk>+^@_lG@yBHK29(9J9E@es9KGAYd_%Mn~S`__QCwiX_S35v$VnY
z$?W9=w$J9^-Z1#ZyrBhhU(G)o0r+N)r(x5{qP~N=I9m=cL2i@f2bxj4SjKrGx7qR<
zt2l>hi{<fC;I~>Xy8*w=GVTSOakb1JjcRYVB$|=9S*~Az!#gZ>&!f!UGJ%dkcvv>}
zhci1Zv+p6d%d&+!X-~^(a>mQjnf6?~Eg>|-_*fcH9Bj9x?|zi+v3$se`Ms7~^f5U0
zS;o^Yw6CT86j<7CnLZJ!2Q1&yD&wG~A-%?amgDp__*<MPfDmArdkQLtEctg)(Ll@Y
z?I;Vf%m@Knuw?^%4I!3x6fh69?9KrEuqA;Gw1im}UW4Wl%jBaF9<}tP`Ej_z(xNWx
zMp(M~AscBK5DuLv%ZEvziMABb9PgNgEk_b#*+q{s*0Q24lH(SB8=N^|nWci=la@YX
zA&j$pW1xA;5=`-yc#9`ZPZBJrGeCCQV(I{uM9WAzW|(BTFbzH>TO1!YKqtlW_m4oN
zT1plHpJqvE1D$kBMKTa)EU7Kv+F48RN|a?-T%rNUv<&w^?wn;Bov=S|sixR?mL-vn
zKVPt9PJzlr%Ug<SU$P7g#WT2USrq^;u2{Cy*5y@8L;wKSECvS!$FEzK(i-W8Wy2UW
z%}q;xnm69EY#0Dxwk7X0RB|je3n0w3SfZhF+wzq`S-$0hH!R(?tU8BAD6rI#;BTR&
zem=^IEEBfF{5?yX=@8zxTy6=24=fw$wJNqqwEQZuq->%fXsIP=J)C-I`H^DlWtJ^}
z0QksqvokD}Tax+$_}DV#9Lk<p9uaqiCGba-J+(N~k7%A*e%=9<O3SEIz*SkMO##_+
z%Wzs*zOdBLbA4&~=Li6=EdI37{o2xqR>^NH&N8+=rihjxI$>39xmgGJca|L|fv>TA
z7X%mITP*a0qz{((NnrbE8R@flem#ed-2G;8F9w;DwN)MDoUOh4qh_0|bykDg#hPn|
zpPQ{u-l1%Z)tn9kTdn14P;Rp_<gTkVvK)2aZtW$2#m)L^3;;W<e;tIM?$)*{;5@8#
zRzY*8bt(NcWS6zczfkeCx;s7~^|CfS2R3gjPh*3R^{4gF*=^lR@q<0q$h{EmwK^Vv
zd!Kb+63qKrJBJ~+-@1=hsRyjb9zf-wb+;ER`B{TIz>>dp5cQ`4*4D1DaLC%20%w6%
z?J2;6tjFn)Z?N^{QJQdtScT8f3ALW1&*!l9{aYkq)+X&>;)pf<D^!kJeQ7r~+}eOT
zp9t#}TFFLQ=MO<H%KEJVDjIDaM4MR0tgDGE#(Lp50Aj7&4rm^?>QbR{!ukvS9g>q)
zp9l!!taTf*Bk_q@fBF{{jkh|#flh*THbTa#B&&+%8p+mr6gE$>mfk^Gs@07;pEPT-
z21&Yg89lT!*0--w-?P?9K0p6a&yhwy?98&JQXuDoRgnvgi`I@6@bi+jvH^0Jt)HFI
z23M>ijfhvR!=@m2&Dx3%wOzN)pc5!JtXC)!f76<`1U}rd+SZ~h+j@dd*XCFY>@b&W
zRj)<aZR-F!^_ORjz6snNYrkQSz?N@aNk7WHYwf%rhyrUbS|=4+U$~*H$QqLZ*X~(M
zcEiMd>#jxsKCm{u1e#)N)J!x?iM8Z6pY{vuI@<n&T)8!uCaaIF<>R69#JX-8I4i6x
z7bEx7+Mm{S&#X5oidJcT!Xv4&_NUW+&#n2{aQlVzFrAZlX}$6W_Fh@1Jptgg)xQp!
z;*E7Kt<v6FM`eSv+S-af{dd-g=5V*hI@v*^z<X<N{9Rww2kT4n@S}A-{o3-Ab$AX;
ze74#w;QnG2?t$j3b=V%Le6x;=LYb58%_@{R+j40wvB@^`1<bqHzOx{=*)~*%vMshn
zG&$I6Ycm;uZMOPpFyv}Gc^l@p+j`7)AnRrudjbycu&to85bm~b)B}0g)-Oe}(>9q_
zCcA7*E)br!#|7Z_vhDtaGH+W?nqc|ZZqVv*x2+3}vU_Y}OCj8AoAwg9eYRe0V8PdR
zsW;&JZT%?_<7Yb;fJ*q=stptj3$Xpv9*9G>IaTm9(Do;NeL*%iTGI#H0_g-+i0vXB
zSPr#~qb~ZeZF6fRVYUS!pgCe&uLAC<&FX~a4!5nMxp{;wlTNBd+D6`i!6@5F7L6Be
z3t5KbnC%R0%*NRKuhU{6*0#?Cn&Y;dxiE3UwvYPAlePpOI2>oI-iG9qEh7bpc-z_A
zz$e%~s$l7~Z3nF$5^X~$ew1YEMT_EO+o!=WpJGed1(j6WkF;TuW-DcoOScJMp>oDn
ze<6~yw%Oxg$dO?aqfnVln`I+_=WO@rp!Ip%;4!FnmMy0j>|U^Wo<P|}+uxqZU9$Nu
z2is+vlEURzY%eds?W?wyM}fO$bD`k-bz7S);J#t&Ng=A6w$VM{#VuPb{nk3$w$%mA
zm18^D5EgPBwy(5TciT4iIuLobw-n*NWBZB1GWoU-$uM}=_B}-+3v6d;BdyRDLTC7j
zY@rtcxMz!x0sOvgcqq(2uuY=hAQaoCyo66BwviPeE43X?fu)DGrm+B&*(}r%J+k>;
zL0P#?_sbllk8N`<q40@K?Q?61+3}g;k(IWv3}{x_4DCVv+?EptmKU}J7vx^r-jt&9
zuWT-tq50Z2f&PNP8~ptP0N&cPU(mkQwq~?f{m#}%4zFu$M+d^C_qLH!VdsNw_&@+Y
z+Stwje6n?>UmJe4rOra`o9&K+x<e;>$oDYeY_B;9{3d%_I&tP=x6!hDvmI*}d|UP_
z6sX#2H>p6n&3<<&gs%2qM<BP|-iF41H@p54RCd_=yoNz{dqfGSJ?!Z=sO+@6Qc!4@
zz5b7|;A!8CLzOBoyU$n$-0-#!?v48T*yq#yVYj{c0p#}B2hrkkuYCgxFZS7Q{tAP>
z_EZ|`_uHq^&oU0!d(}s^586|x2lca06hZ25Hy=e3U}q^jf5`56ADV&oCPRP=vUj4t
zN)T*cN{0YK>{a{dce<hWjmu#0u>E6m=!DrVv?+hY&eF>7sC_S;>I%0<n1G0||MVw(
zinQOO(;ZRvCTf&L+w0N7=$L((8{jea0RnuAwL9qW>T&zpmB5{_j}3(Iq+L#b3@XlU
z=?E`Q+5K=J!l8<{=k$d83HBQlXg+OUxE^eY_FpM3pJdk#LXvEE-j5{3K4AosRJ)aq
zy`|Yd(!4+2{+Xh6XY2`Gk({;v8wpDp_CYt`VW!<<3Cy3f_o|Ds^Y*ReVV1plEX-f9
zkHY?xYRX0XlUAU)WPg<h^Ox<%cS3r_URVN4SM8obV7q1?Lf!Ip`$(Gh+^~C}hRRKQ
z1%<M2*&DGa%eGg4LUZNVzpg`BuHEF5u)L+C!5(N7+5>KZxyU{y6pHukDdS<T*gi87
z21@KBn!~|T`^t?dduZ?b0q8ROrefe8*{4$otlS<+9noWZJ35K?#IB^VufqOR4s%cK
zn;#(e%zpVdxLIjGvJAN@`)4oI@3}qM(G~a?_NB$(erZpl<NvShJe?DLZ9hN<@88(d
zDXj3;9zYw7)%Gd$TD-IOk3>>q4>Q1-_jcJuc>lrv+yBGSb;osCeSgy|)6z6EKYQ=J
zuu^kmmYS<FGs_&=*79r1(mo(d_7spMQ$RtKB?>A-5CsuXw(Kc_f-(j4_ddVB&g<NJ
z&ikBu`8@Zz_ndPdT0ovIoS1{Y@r9q$(RO0tJb#eMg-hIF@Y%v6!4P@A5Wi(SQj8n>
zDfny0D4_7?QARCIlRcw%KI}R$woF3Nk@3c3pgA#CmtbhljM(FF?HHr<2lTlx{3-kH
z%8*bgsv9GXws7tYN6K7zFrF)5$&*n;Wkp_$%vrGD&G_$65Ff@nKS0lyQ653(M?XgI
zbfEb&3`c-{oT2*?Tma+#M}P@rBzFQdh~dQs+6l(qgK#aFQPT?05XN)b?uRle=&nZ?
z<87MmaK@2TV4r00B~XZ9WR8K0WJLUmz9>f8Z!jOt___@iVi=b!^a<ElMo%a}Pch!5
zxrk#7(D#+%83tOB5*S|{06EQwrNX!~jIZ}WGLd2P9k7!aFHj8lEF<zPOe8Z@TjBjV
zMtA~DoM#-`iN+L$W)zsIjIurOH;pmP19O<pm_ezh48~_AP~UrjQC)@3Oa|*V*o%y<
z&FH+u`1Tq|7URW7Xv}8x)AtZBGjc8h^a`WD2bQiflI8Fzk6~s(J)hx!18!eq4AEtw
z0!H>th!iq9JmJiB#y-EC|IN21-9T3{qs9p?l`sY<AA5`8N_oCg#$W>kZ!^l?f`es@
zZ|J&JIb%Jg87mmtTd;G7v2_;6T}CCH?kgD{4)Caok#`It)eP@kK-Vxfu7zGL;|QI{
z>liJ~P^f3PxWT`Bj6+s>_8S=Q(r%=Y!7u}+iIJTN(Pl<tGSFHW$G2g$tqd_`ciI@2
zsM@TZF+}_A4#uu2=<8%0NP~$khV4d>ZbrWzjrSSv=YsSwj#7H_0pr6CkY2{aH$nOs
z+o|s%Bj3rd;vm!d+Az#MVQejd`XJ-or|@NnkwtZi!wmV`=o?`$N?>-B5lV5pF~$}p
zX5=YjZUiL98396!WrC5bg1eK9$7XQP7$3h5L(dseYtd-SY@mA=cFcoRWpb41{VnFz
zo@t?TtpoFg|KD9YGPB-CrxUZG2O7>y3%%lxF{Ryb)P*^p4z{k$N-C#wWBO!5#GT3C
zjXn>ij$*E!%rEGBDqc)iTJF7>+uwnsKFs9B;Cz|0zk!G!bM9eq{>&08)j7^IQQ9kj
z*_%bX%RuHJg*bwkv+dyN3FasCf(T~*v>1vZOoyMrg)%4CfrK&bx1%wfSuMkqoMeuK
zf{S3Dr3F5c`4@#-Vwh%1UBoh@X)}I`xj71495d1%ZpSn8DY2cv%x1!w)64-QeevZC
zlb?moL}n5TP9-tNsPN$|Q{VwEnOS%kFz1*d^bwBp%-z>uFon5^98F~|rQAgtvz%TR
z>C7^^iJrmK{eZ>`%m)-Z%4E)L0J+Hghf)`pn4J_m%3?m*36yN+c|-xN(=Ri1Z$R-1
z(|0w<Rpv4Z>*g>SHJFlI<_`KqR31}HlbFwZc@o?;=I5>$QvvfWS4b8zH_$=+I@3(Y
z-6Ccd1<G$QCBd+ClX>g~aK+3^v>uf(f7OHBV%pxs085#7<Dg)@&3u94m1WEn`qEQ5
zbLL}oRxnplI_M5_$pV<T%e+Dn`bwsp9=Iyz%sWu5X6Dn&u7){}vO%@XL@LCoV=j9K
zq@Ec;`~7>&sT5FZV4k4eWh1lG8+}bocdE^6W<KOXy~WD(q?=2v%(v*c+s5413)0Sf
z9t2Ar%)_6+ZYNXQ4${R8pgdbQ^Q%?h?laj`sMN#UAjNb)VD_DWiC$(W?YjDy@AAPt
zWNyxe$Rp-^CUE`C+E<`Az<m5Ke0t1up;O%xrj_*;ycuL(rabBpGlCL>!^|I!19XI$
zQwfbxrg9^=F=nV6V4gBN+~D^(^8%guCzuTm5Se5u)?pCOm@GS(f6m-s4`R#uI35ai
ztfg0A@F;5~trPaF_qV|(Csq^%44qjstmEiB#&V;gJQr3~JwRPqqkjU;jWvD{mfTsd
zFNLB9>%$QAd9vau+Uv#2q<Qvcsb7V^KCB<;<mbzBr(>@lOF+-PKg$vXw~w<_Di{o4
zmCgoAAnPUi$p*2u)1l=A>v}mwYlB&yYIqaE`T+leXnH7X(;>)&v6fr{31`Je!^BBe
z_jzbUu$W7s5Xo{KgF+N5a~l+*S<5Nz62qE7MK7_eziACS#d?WWk2uyFSD+Bj>Y>7;
z1lE>VICGlC_!J^%Sk2#4Rd^!n4LTbqu~;<gXIVanp_t6-UI>kItg6cx%z4%ezrsWc
zD~akWQ(2>D;7l4Tt`m~!te+`vn87+kLBR{GsT9=9WLa$>a*=h0ex#RJ>FtorV$B_b
zp={PWgJ`_WI@UZB&)*f+a4Hn9vi_kIMh<K77`R;4T>9Qy9_tV-cloSLN_1UgJ-duQ
zQvqwob6^*;_D;gmb=JA>;8PKcN4udLtbwHvxyiDns)l0L2|VJ{OIS*JTi#;5PU-zp
z)*4Dd+-6O>z@D{?)k|m1a#q!ckf~tF>1}q0wUtUK@3P)}2CkB|=u5y<u?7x7q?#4~
zF8XR%1I^%SS#@+Yu4B#F36Xl%bqTn8tV4sa)WBM##CRK7pVCdzCRQO;NjI~;F9p}a
z`ir1jt*pu{&^DI!eW10oe4hZOgH=@k#ctNa&(L_Em1zso!%_~Q@c}Ek2{65^Z&$&K
zKGp)deff~}29-ZOV$FC7BK@rIKEremuu6A>d(4VThQbrpS9c&X$lAFD9uBc;df?$O
z%lal&5st9Z=xX~YYcv4n$5_>r{(Z`ld<vLxmXY#D6Rc2dj;2qtt_DHm8S9OOnCIuL
zK?k7OvU9sY?ASpRXgbQ?;(#I9vy+#@H3#<Y8Gv?V+f&J?6I(VNjn3?#FCcP^{n%Ov
z>cZZ$8U|h2@6k)fjqUCLzunnKR|3t0{aHCQJlQMgZ0yC(pk>RO&7)L?54(~+km}1m
zNacKf?9eiR`LiooaOODsbJ~~&uw@i$4rI62!9ozbeHBDbuz#imTQK{eKSlmR*qfc<
zTPS<rGuRDdpZprw;p`T=(R`AfL^p*a*m&LJ!D9zdfFO#!%>Wb8?2<T;7<P*kda>+C
zda6#bSI+`=9J`)Yn0WRos<cR8H{`;L)9flLWIMyYL2uDS_FMM!o$e&|r*yhK%f40)
zOUdlCx8c({_A68$bDsS*ttlz&15;r)mHpKyNE-Vl;v&=2*{=k^QU<$zE-YPOUn+)V
zCc9|^^e$p9fO3g_fIh>K#a=+c+iW(6a$=X+Wt8N+!d|&$8lJza?3Cr`%wfAOffu>#
zL$d*s$9^b<!};tlwxjVHJBSO{3fOi}fL6$!q)p*<c5x#bZ?Zk^p|P0Fq<cLj>=RUS
zaEm>S5A&t$TwAE$W-loQSH=#d;*oN8F6~b$*yaAvv)*C9n*)uz?CTxyqLR&j4=z@*
zHNG%W%?_j*&KmZ5DzvX<kI??HjvbJVzIt}`NhsW7XCB2QG_ZfCr=pSl)~7Jh#CD{-
zOf&mCI<mH~|7K%It!$@pfVHvLQzE9Fy^JboI;`x2tI*lWUi~w?>0+1Cu)EoFXybUF
zz3VzOde{f38t?%-el|3E*(WJW*~eZ_;n0WdSxeFPh#g9Y@qTtV-L)8CU!DT;m@S9|
z$`iJQ_K1V*uDJjkVh{ZS3&ZRsRGmG-wo1N$%qTne6`+l=U0NXXl>IyHrN`MJ<A9l9
z_t1}Rl3h)?`)6!N3iCZ@kD1VD%gJ?sf*t36BovNvo{hpod(KM~A9mpE@q}GR&ar%m
zIB}XN{p-weqRi1TP8tQOTsRHZ&7iKF*VEAI###L`u-!Q~{sZU1Nt2+@ljAi9jb5B9
zS3$fvF%;_e;rwL>P+!ioBOrd9nR{T@pYyc@lYg9J6AtqM9R3xk2Xdy=gA3v$U~4e_
z1ZPtZrYo4!Po*~@9A`JmmV|Of$H9hix=?#FJ)Gl0Yr;uR<YtfvPQWNMA~|!X!cr7R
zdj{sCIe#U=!x+wr8JM70j!zW&PI129hQ2rsj}H>hai<7Z0w;)#zC_OINSIIJ#IFF@
zS&k#cT#`A-_o>w39LIYqI?r=7HzAtB$ykbkrgC=oK|hUyj4d8D&PI1AW^l}{7|aFE
zD*B*TCdY|}c9C<a8qQqe{P-<IvN)?n7*aN8?|xuj=5$e{_X=mnzYw{~`DG9EayS}y
z=;d-Enx^3S%i|<awM#z7-4m9sao(>*X8|YsD{zIJYD#xs=d6Df4i|C0rE4oUI3x6G
zzsafXfMhX8bPy&=I9@4GxW#G8hNV(Y@l9af=49`MUK!`&B<87{vwZ_d1?P4p8t-tN
zUV$^#yPREfK`S|5=R&cHGml;?)g0fSV7G=dK}WS(&IrBe>p1ol6sYICy#(An&JGj$
z8aOc@L9&rEr5mJ)^Y#{yX3kEkxNYJ5k_m-YPUWlcu#FS+7Zln#F*{(dgX6d!{&re9
z9dQ^%7pI?22HhMJ?LqEyQYc8;!wF7@r3ak)dl2pAbhtpjkF#k49zNu}t_Amq6Ict8
ze$HwmxB<?KNf`EHPVgEiJmGAosLLQHemg{lIFUR+4|6iTU}%IhMoZ`@$J+fH%#U&2
zquX3hIYECwbeuD*4cr9hAF4T><m}DCD4uc3GNJ#RlR|k2TW&`+h#fbRHmpavU;ht2
z*>k4`Ld1c)o(|NG+^^UewiEX<t@+N}-#-R9#$8LRr3=@QLVB*;XVzHgyK#q(!c$M~
zSQ|#+#br_joi}%k0$)DdnMx@7a$5({=f|BvCry9udrnX|&ee2+1aQl~1xg^-osL{V
z+@zft;R&vSPC&ujfJpR(a9j5RER_2SrMAPk4@V#p&b8T1@4u7W9kFmKf;&mk%1CZI
z9lE2qIUB)6bK5hZ7{mQ*H8f(mE&qR2gZl^VGvc_qcJ#$_t0=;pz_t4rV5hm~Y3)42
zeM-UlM6QhoP?ESW_QJKZT(>viZ!-4|6@Q)MdX`bC-+69VHe5{ME~dvYmAg9@`f1!>
zJb|6gEu>{DgDctq^B1@;=mDC^ZK#9DMQ#LDnO@>r=sC#Z{zr}3+<f|w=4EaL<sq(c
zAFqX_tK4q7xR}G$(Qhu7E1eC!JZ@DJMSJqO{Zt}#jr%Wc-3quSiXaqnxfd|c*SSZj
zOs0sdpauB`H|Hokyven7f<iHOA*FUoxLag!^cI)10F9;Gb}F~L&9$wCUKw{Q<;BXm
ziS(kb;GU(MKzF!-6oa|TJw6j6)=I9#88TJecpl7Gb8mbGnHuiZ7tmSDJ>G%w)^WR5
z0lS`i;0Pq|aldl|S_3!kBt#myv6Oai;@W<QVK;NdBT#SQY7}s-mAiq?&~4oJ8lm3K
z<*k5)4z4l@BAwg=CO~&txphvMnr<$SVrBQaCuTsVhkJl-j6C3aZbxG;cP+ie`?%lN
z!S8-<{24S3a9J;ad(17OnSH|j`YF%`x!-r7Z-{#!66(X;1DoOR2zMEkYmIXIJ<&ME
zEv7BzQ|^nDejevqWt(Aef_tkIWRm;q{{Z@o`#V<M>Cd?i%OGRRTek_=cD(xe7{yUu
zSOkbYZ&3wc9C%(7`*-BAXnW+u%cH6pXWkroijVPLrf9MYZ$AFa(_MKdC}!)%n>QcC
zowvOR#DmvurQ^0IFOs6?Uc45XFK^!K2LR*4v!{)xFK^=lSn}hIEd`oC@8N$?IL_nH
zLKDFIyb_iId3krB7sT75Mc)bDeaZv`^E~JRa0u@-J=&qXPiRPCy!C95aNd=55IM;+
zyrMv71aJ9Lu#vortI!$6+eBlE=5gsnAH(~J3KC*@C;fhNns5D!29dziQzgJ@-jXlj
z(iz?=I^-nsIw(1p#QR1Gm(KFK<>*W1$tWLij`usg(a-Y?2G~jA6;ZiLDzEJqh@|m0
zz6Pu5ym5LBWbj@Hh57~F|LB`NnY_j8F|dog7A@xd5^rezd}w6xntz9-Y~FE7I$h?8
zsf_&!FLg2cuJSI^88(Mkc^iGXJjOS$l*jw-8uasdaeFYZYrHw3z%Jlj^V{S+-#Yv`
z1aI)dsWk5<Z)i2Jig~<R$d~Z8p9Xh}SNJO+OL=7)sNLr6SO-$UEBXt5-r;FqhJm}h
ztsWRdCGXuB=vDC&=*(Kp8=(UC8eTF5ifeh>SRi%0{zj<R^LFip$UWX&E0t3>@ZO}$
zI*q(s3Yj+XdiO)7nO8!k%PqV&RKRZKNmS5p<Nfz8`r3I%=-Kb!ZQlWrPTrvm=ymZz
zD7D?qyE-4(_j#lA-(Pxo+91s9177!k=<DU_XeZmpt8N6?L*BGdI{!c7O*;aOe%^)M
z@M3`XMJ{9>^8&V^?+Gts8ej%_{M#@w#LFl5hk5Jhq%y)Q-wo_ho-_j77;nZQjQ1&T
z<A=Z==Ot4>bb^;9gTf>)Qir~0yq_p;@SJ!27l7IFhfh%a&5l2C4knKBL#aI3p6^GQ
zR0sb3|ABMlPu~SEocNZx&~WBw%F%a>zx)q)=)zxe257GQ#Z>I&#&4&1g*#tBTXqlr
zpa2S<{PIMY_u`+V<Fq$F+Y!WvUq^R&efb52RBG+Ve@bamf4=?in1thenGKu?;FmXm
z1oC&&!yClUeg}Og_({j0AI$Hh-B1X>XEXXj`C}9w3gb(tKs}uAwhfXe`A?{bBZ5DL
z&ghZ+sWiYS{uK%;NAtfl!d?u2Ydu7)v3$+<7|bdD0or=U@m2pHFX1;)t|EcIj=s@w
zny-xk_8I=7CRj@32U3_li9eqPbC$oF&dSOBT@=hd#~-HBqVxRUDXf&nmtTZ>I)7RM
z)HC>*H6R!GQT-6f<QG!}_o9{m89ic`_~~t!%PfAs53sZOg^NHg^94O1SNM(}!|$v7
zpHpByhtH(lZZ7{*3gPDQPf%JcpZ^M_La*`vp)-B~|K-<UqL6==PLkL8brdHl;@_DM
za)ZCq7JWDQcPS}S%(te|F{XqcPsih1{5Q6vvy>l0RUNnad;z#J{_%Nmt(^ZJojoh~
zTDrk=ho3LNVD9pRC@@pWZ(aoRRs00n`B(EL2Qc~?zDENvYxzg$<yXh|rr=9Ge_RQa
zd;FfWAPxK=s}R_Y{OI>F&?f#Jy2#VaUrr&47XD#pSZd|BIs>$gFJ1_r+W9HhK|1(O
z??bPXpLP=>U3|}9f!)n_W5Moyen3A&dia49R(im{@DloZ`G+Yk)W_Ga1lU9VH7Y84
z#Gljj5-j!e?fqKZ=3DnuRC$o^D2L<_|4$Mb=4(&G`w{-yctDTxOELg9#^3QH$Wy)|
z6l9!#lp<ae{1+C%-X!168IaHTbKb!KpYz>HfMP2+;15hYL2)U-jtVkpS8XqtN`DXs
z!D|%Ubrejsrh_^O7R-V7&Vv1gAjbsr=oI53*f|1FSHT7=I5&Z>9*XXQpQpp1hahA%
z&^!gDbhhvk$SINGEjSkf5g$RpFEH;b$S4Q#6Ii~3PXU7Lqu>Gsvp<AnkRXa`XHG!G
z3KPMCWix;lA_z!?eyAW)35UZ3cc|_)T(DS-QJfSUq{Lx_z`GX)BL%sXEr=3`sM0N3
zaE?;GF@kUCa2+d%H3RIF;4|91#R+cz3b1&A-G6{i5d21Q>(c^0#i7m!lE0u(NTQ%}
z54=edys--~X9Z=kn1p0OA?=jT2^b#&=Da{ai)D)7S1KG$6}+<+`e_2|Y<Qn8c+&x(
z8G=*Wpm0I((`htj3U<5<?xG+<1n5fwn_-}23DTcIFIzB5@x{vmA)=KCMGBm#^{Sw4
zKNNEWnRG!nS8$UmZ1V(vnc+;np!apSc1;jU!MFlJ4PCA)6ztdm?z*6W%8`l$SLlBW
z+z=e0c+O2h)7LOqEQp}kR*7IE)qma+jMGwID)`eAeYXX3C_i8=6Rf2DR=J>-mcR<Z
z8mc0>BgmyI4tE8=oq$i3g8rH4s}ijH9hRyEZ_#_bM$kzm@U?>EG}x^ZcvH5wUa*lq
ze|Jx??`1SL2+q@L*C=?0Lh?<5gA@{M7JT6dyDfsK-$7cff~b1{Z4+cr2BckZik|ll
z!35>IIt4dc(AOpKd4R@lLH*w#_XT@+fawvq9)W8Q1T#MecCVm!7o6!6tjb5<LqYb3
zP=6$Fn}@OV3tTcFG9VDr&+@V0(NUm05ez<o`9Xnk<#!m&kRX~i8>52lw2>GSWK@DY
z6*zIxI4<ysgKHClNt(7vLA+mt*L>?DiWb@leIp=vRCqcFnD)YAT238=UuJ-F6oy2@
z7boGWR{TMng}s!&J|<ND|Dz?`)&=KXg&YbDx(R<30>xdZdJpOz!u&8OcnW8H0}(Hw
zX9kG3FtrUc;Uf(5g15fHJ=Ow@%ui@TE4IIoL$Ax@!YBr~0O1F8rVbPqWdSrun06g~
zCxm_U?hh8WZa`m%@X!BYV4*_I8T5q--Kp>>TzH6TZB7cG(MBLb`29z4EmHVPDfFU*
zZ@maES}0uv%oyQcZnPxC3hNSpc1n1TPXBR2B^55k3+K}lnjrL}zxiq5?VI4v2uI$A
ziA3SISJ9Xxw4TO5&kFNt7oIF!d>)|Zgs;;gd0yx;2eXzU42c6~s_-IZq|$^tTi|cH
zu;DryGlb$pbXoa=@FV)JMW*oOW?)|w{z)m1OTv%#!{IF9nN3j47Df-F@3OGc0CGiG
zKL~}Z!oL)lyc{9EpNa=f7`YDEc|rzlPxFO)p2Pe#Va_^?r9fz)3Z6n?HHELP3)8Ov
zvq<<J4n4S6FZ|#yus4Of&H}VpIBbPtiEtBbL~aSEW&yNRSbq)NZD9bVD$9f=nLsNS
z)_(=G3gNuf(7PkNN^#%2!i}`ksubqcL8MC9LbV6gLWh6gQ=PDmUeEQy(mx=1Pbj+#
z&e|Z<^`Ns+_-q?UlW@&FkY-^S4W>o-#uqTyD%5`g58H%paqyyD_`w{AbO-}!vFj9i
z(}UI}<k9y=yM-6d0rb8wb1xcugnL4v@IY9ah8gV@-gpxzeZu+c;o3tXM~S{iR$==0
znCE_B*gudN5dJ$4`j3U*biu?E;VC+{4+^V&(KjUQn*wfF_)!~t8WDEWIzB3NScmBv
z6V|*7(5J!&e*<(}XrXPvgs>nP1}BB@(M`8!!d`m&Jr{P+{X$z&28HtMMApF<(Rozl
znFKU@(akG>aS%Nc0LD>NNUu#Nk+>hkS>)FUa!eGO0|gh+wX+a$6@5gZA~#VS#Y5di
zGuDCg5Y3{Wtf%N}$_RUjim5=%Tl6hOH+@7g^xE_leRmpz@Drt3>E5irXf2gQ9v8X%
zgU$ev|C`VV6eX+SVvwk{5@;txpV415STsOY`XQp70pLPK8=iv;6K$c365*mxK7hfK
zqRqu<j1cV`Mq{Mt>wa)iqBvTnqD331UM5EL)hU>b72SKEcJQY}w|pTJC;EZPSmH$s
z_d+p2RHa7WY0-Hud^#g~hY|vbqFuB)Cy8R3Vd<=B=2CFUqWZfKIVYNO7^6Qgdes(|
zQbc~_TB?Y70b@xM9s3sw>7p_|L^4EIK86<;L~n-C4n9+)Uj$1RMQ`1OQ`sWJUMOA`
z?Wc&u711{v;nP*oS1C};5ye#iCRa4)Hb|c6`S-A!FJjxm-)o|e>3vxs8m8+zg`&^X
z;o5c4=R%Mo5pN5~4bdRY`b`mE1odK(v6%j6N{Q$Zedgkp$eZFDr6NxX@ZA<&zYQ<S
zMD;E(Q7*c58V*;8)-$1ahrXbUM@@8b3<{N^nT;@5CAvWiYqcnkUh_4gcO0NsD>D56
z*Xl$(%D~l&p4g-Bo@iwgP#Q$l3FxynigGy6ZxZ!;L#A1@it^JfqL-(_;a1VBo8e5G
zC~g#_UG&!=Omv81=m60vnnB0XE|K;M6uL#%sowFvXa=oXJ)&2nn63w+bM#K?6&27e
ztv=CPzX9{1Xm2#^J`%0EjZyboMRUJ{;((~(9!xwI{p|(pCn678S_Vb?1HcW5_GN$@
z7R`PNm=Te6C&;L1^*r>Ai53Tfdn!t&?_-XOYU0s2A^K?=z$QgUCIS6S6h+a^=c4>k
z4A53wOwmm{u|M4nIx4mz=7<MR9J&UqgSd1STyzxUzf<AC6F1JrV4TIVA4BAr_)RL^
zb`gJ?2NSMhFPaiJao%3&xr_HvEWty(?g5CW_zAt0yu=pzpt864b-G^VBMzW@(7xjO
zyWsr94;KK%Up(LXEntp|eF9)9KwSC~OazJ>C{i3G=F^qy6Jlpty@JJyXjc^?Zl&uU
z;o_f@FzYA9|3*SDLR`j0U!-{Z>o6E4UQOZ2Xz|}H=*5U<ZNntQinCwB9G((i41h?S
z`1eb&5HI%K`~x}@#3M&w>9lxvA-FSQ0jfWzCyFmT14$B>(Kha^cy|^YP8JJ00CP^f
zhQcK0#hR6XNfFPafJ&-(kRlCf;@TLHba8(T6f(ps=`DOg{Jr0+K`d)@A0V^EE9hu)
zS?o`z@hjpS%HLfT4=n~{j`(d#L*$CL(fK(~tZ{^ad~wDEe7GiFngqQ9@v>lu6p9%;
z0d`%ylr~dEVj11?xFLR*ey}&iGwHHlvG`MaI94K_Qviiq;%;jWXsNhU2*umtB^3ZI
z6L(Pptz6tmDVYj!0*(ESxXm8U+!Y5#V<?s4YD(TziQS&VQnmQ|9*ES4kDD>ewc^9m
zfLSLVqKIX^*i;Jco_IN(pBu#g(O$bz{Aeejo5cSm(@nr;@m_lSwulSJ;a2g_-$A2I
ze1O78?c&reu-hTFq4RU6_)I9wcZu^Oq2Dcbq%ybrVi~10d&IleLE(YezYKl7;`&zs
z-6tNt0g;E|y3H8bBk`#MOhUhS@vmqc5a<0#>6*vl8&jb1MBH})?hlH&I+z#|-;sa}
zi#>|aHzHn1Tf9;6L;6*XiTB(`<5O|q=kRG<{LULdn-F)?_Z=q1R>~sUO72te!A@da
z1J{m9UiOB0dr5E&h=XMQ03;nHf8$tbo$e%YT?D(%5>^v5j!8zS*2G2frWJ~=l6_6^
z!cDUOHq5(A!s&GCAz{;35j`bJN<(-_HgPa{-jeg%pywm`J{Xd|lAW~Z_(>coI_NL?
zk1EZMOS~zT5FlCgAy5J(^NrB621y>ggw7L^!5=ZSV99^)K_f)+2Sq(XCH+Z&36uQe
zj=pe-4VC7cl&}|L^bwMVx6l_UDW<xLD9Ho`Yoa9*@-Rjc@Gh`pC8^6Hc}nuJA28!2
ztKJ6}FKJ1Dy#&d=bPVvcRr1TvaO#X?@g;O7N?aOYDM|7JtxsnqBVr6DSt6z>Jty&^
ze{OMJviA<KQzZIN(3dL7@B>McxGsPf>5@xyV9$`aM?><0<Xa8wW=dY6z|}>G$3H;1
zBvAxGAxjcI3XyDyHSIf?zbv_~Me7yGpFd&}uS#Az511UuOJ~uSE7|=Tu=6BERnW+n
zycY}Zn#8LBXay3sC-e#>=V|e{F45B7xkz&47Eo?TzKH^NQ*!GAfE7!)EP$0r8aWu?
zEy?q*(O4?EZKdeYZOJ}0G|D6akuXs%xmE?43Q4aFGIu1ud<@0AlKuritCZN&j;%`4
zu^;nXEg7c&hEyZTpr}Kw<iBz#)Jd)t0<2!*CPU*r$ys{cHc0M1gujiF-I?fXk_aBc
zY^$U-lb*jeiI}!0?UI9!q2D37#KwGeN-F3#+a-BU^&s7nxwg=_FR7(6!ybtj6?#69
zTq=Y@ujC(FIMXNTx{JPt5>JY`Jd!*%L8M>ugf8L?NdBZ9=3|LZGrV{rv7L({4NBhE
z&}L&u^3o|79F{z%=<JBZ%?^H#N>V6BH6~%ULgT5Vs|GOR5^gL+CM3!95u!;6cQHJC
zCJCjRrq3lOo`bWMHm5_uPCCa4CXPzKt%QQTG-x?E2kDD!h&W2O>Y?ByeZ-)0A!n(K
z3HF$DIUPh?q*1hNxk^vI2>0EjBOb8pE=^{l&qL};+Y3+WvI>ZJNf+9HcuRk#LT4Xo
z6(uZurTcv`34YR#9f9dD{V@yVxbz3Ql^Gy?{0}e#rQ_vL2$DKbU7_`a^c7m}f~7VT
z`45pkr&D04luKLFFzFk&VK7`e^c6r)N=tmv7$Hp;!>34T1qHRDq&w)PA1&q6aXLoo
zPI2p4X~$|bo|5*2!>2f@cQhp9rK%y21nK5{SU4@srJAWTR%zN)%uu3qkoIp$(gIg>
zo|WF9$W^lR-S@$rlRhYc-{+<F6d_NM9{LnxN|hdTgF>3r4#S_GE>+S_K11qv2A~(D
z%MPJ0Q`$<E%@?I-o<QM}wCxeNEa~5LT+Ehcw}87WwXR4)=N0KUe?$MOw1P5GIZ_K<
zxyY6FF9FOoX>kyST_F8|E*%s~59fhgmyVyrV2Y%V=?gSBq<@tF^rrN}`v5DJPEfA8
zM7o&`*KSFFq-&t1(r+lye_JZ1e|TFa72m_mluMJXbudvO-9^8vJJRj1LG-RvMq&3#
zDRUCoRnilGf>cY@pFyNX8uk<-wbG<Qpw&r-=s;XAeVO7N_oT7&;C6$wQh>fj>0wH|
zHA%1jhrVX%N40RKMarZvwY5sulwq80(#l7)%C}4VH-dCXr_+ksDLwonNSCyWwvXLX
z7VWR^OIOr@^hjT)<Mjh+D(!=MrS`kf*e5-+1>8gF9V1+OB+Wbxuzu;cv?U#o*4_vA
zSo(bhFrP@Le}Tq9X<Q&Y9Fj(t(8Z5oY0L$TVnlj%Gtfq*sk9d!lP;&_@~LzMZE(k>
zF2|rTA)TX#rAcYbJK&y4a~FeqF8!R!F>PfsEwJrm|EmXgRJN6#KYN*pvT_cxOY}N%
zlwDj6Lr$`DuY)+t_Wnib(qpnI)1c@gTS;}|uChY9JLe|bN5^Y-*%3+|d&s(00nJmk
zkM_V`vJ^TJddqI%urS?6wv$2yzOvanFf)F##5VjA{AGG7YB?_3NN>Xc8SfTIpzJeG
z7z&cDtHWR9gv{eIFs;F|bzeXuM5d-)eyHqgy3ZFTL%0zSp6reb$Vu6fDp-n;F~5LM
zk+Od;!hDo${yvasS^P2doswPp9Vl_K79rH*WhKeLPLSo@h27J#BODCkj4a&_B8jq7
zltxdI`MwN$XRR_Z1y++~5B5XjoUDYF!t=5qI;^M2>aJpFsWQ7;AZfA#w3khnU8GlC
zhOGS<U@pjNC`6Gdt2l(di?X|R0KFs=(U(!OWCc_`mo1w|iSNs@QhE_wk-aT~+gD{L
zDHxI?vv$(t=gNZjf#k^w9z!u-Hcr(}*JR=Xcu^o5kzp<iWy5r1<+{wi8hu4F2M1WX
zA)6%t+D%#bf6yzIdD9N8L>6BJg<CS)8{kT1n`t+BTc$n?g)-UCG?nEtKAEkM<yuMO
zj_jofuy<v<5+GVBi+TW0t7Jjb(N`^tOo#h5viZj`&{~;jE-cl_e11h=z3i_(DBP1-
z=}~Erl~9dXqwF854r!7l_F_hxWuNpxp+)uq)p)ha4%7psO{VgJNV}};fED^3vH&_4
zbjsc|L%&P*@qBpNEjvhscK2o5>Dv`Ovd6ULdm#IE7SMWSLi*}TpX{jz^d8EpK7%ul
zWNA6*>z94L6eb2_VLyO8mTeG$Jdwpsf%>3qRtLzCENK?Vuxz@P_MaoNY$_ldl{tL_
zv@zMI)qr^_QwG4baoLHB(4UZTDCIpVOG<*JXR`7oAkSqJlt;0ZKUxpYPQLIt)Q`%m
zsmQ}#{^<e`2l?E0Kpf>?Qhn_)`4lQgc9ARQL(*0L8kd4yZt^7h<hHxK=_L%*L!O}n
z=PAEOx9z;-&GhT`mM@aPgpb_r0z`b}$r0fE<jXIi&tLx0ba-)GE_DECfIROv_!}sn
z^#%HZ<avKX;e>p*9*x0r>1AMs$OC@^36(FqkJ+|{$%A8n7A`;fDt<{P<*syHE<#>U
zCyGe<vQdCW$+zx+Mzp+J4=zTYL3!y|dDbLAPs!B^kU05@I*@pIz;%Eo$Uj~Pk<;?|
zlh8XO|M@p?iE@rVd`glJ(~s<|JRlWZvQ_?F71(ofce)vLUcQO~ODXcw6PUJC`3x#g
zOq1`V6n47&UkWN_$WKxU#s&GIQ_#<pubY6vMfu0`!CjJnO}G5A<T~2NWy`B*6L4AH
z?gO8$$lWLqc2$0w-t#%~z(I)Q%B@eSTs=>|@eK6y<*!j~%r$u&#UBdf>)22%l>bR*
z$?Ni;D3)3zPw9gG4LR#Luy4x6R6SlS-~J^AS|TrdAAPsvKl7kaDj!aT`fd4wN3c{T
zUsi?5E0@Q{V4f=EsExsMC+Ax!jDA<X<}vgu<<0ewsghTlVX0ca;W`v+<bOCqqgJk;
z21|8v$2ZYfFJF}e$$RqaEN~6-l^eh{${F<8h$i{qmmtmZQX%wO<Y#D0&?+DP64Tr!
zSEr+~U7olTT!*|Pf-XdL%5PG%sY^bMP9i<>mAfJHK%Nl{nO^z&ld#(-pWhAcq5Stc
zh&+-nYK30Ed_o260r@7%89tUTqO;`_c_ZbW2IVR*=ncv5o52mspH)I{M4m+-P#l%l
zO~=fP$=AJ0<w8&8-n20qmyhS8bwd6sU1yk-ub`nlll$W(HT}6ffXahy6_peKuv2_U
zx#**cTN)_XD;jBE<e<>dQQA>qI0R>$6z6DP<gDnmL*FsQye+_VQAjR=xGG$@=yOxN
zhFhQ3>F$a*sYud8aeWM(o{F{I7=@Q&m?}-Z74d;U^HCUnfQGMPEoJci6n9p`lE32X
z81x-iB*#KMK#~3`)B_a^N*V?!HjhK$gkm$5Oa?28>83-7qO1?<p^D|SRSZ*1tp;Ze
zSG>9$>`6t)B+w!hYiQYuRQ&A=FQOE`kD)PIk&pzK7{zb2TZvWJ(>CXn;+K=?i&Ko0
zfs0ohq3}Y2LgxzZwBiCi9A^}>=}ApgbWQ_FQoQsQP|hmuxWjI;!kMlZowLFqI?pTC
zH3K_Eakv}iQx*C2J%ltxJNcci5X*s`p?LN!G%hG=mjF9cp{@YAsQ79+6fP+uD9f0o
zsHB{3w&L?XOx|V1N(we#QFPP({;HySB~Wq{J87Sgt2jh;@p%gCUMDz}uL#ux`<kMw
z4QK@lwhtz;P?1Bqyz7c63Ii4?X0<~9hT^Nk;7SxH>cHJnyg*Myse(zRxVIH8I+!n0
zBpri^az!QwA{B~uy7h5KvDP0VcNI(jKSHVahvF|)3eErj6OU@e#&mdEqljh0V67s2
z1Tb|9RumfR6%Qy@eoyf_eXF!Vads1i)~K+j&lNQ({9XlVR^;7+UW-Do1!HMd2!Ds&
zHboVkquLb*ilEn_Sol4>=v4SoEk~C^y9UtRirG8q{C8hbI|jubh4=x;1H}+syzf<n
zMPO)sigG%dK2(UPr0$WTVFUF06>}-{FrWyfV8LTWCKZ7^QFzj-HK<^F0eeVMPz7#S
zvA_m;BZ~E3LS$5Nmdek@6bTemf2y!n(Z>MB6-i!@nNaMDf-{qf4`jf8rl_Vz=DA|c
zE}+>e#pU4al+G_h|ERK$w(IuF-zk*qplqXc*-<%@Ha$+tkxUS0<*vhU`<T)_4bU#i
zkLk7Gs{9|NN!*mlzk_pE{`xPKt9vN_qoPAkrRy{hFJ;qB=zA;oyTFo<@*0&K_$oi8
zlct|Ckp|<h+#UhR<I1HJiVaZuU4{8T<?pne3{np406C%j<}CVxl^;_@Q;722N~nh_
zGw6H1VM-b03&NGP3Rtk7RL&QoGeY?)-Ik10rcZ&1DCI3$HKUczJXnfRj{OD_tK?D$
z?v(OhdKt$l189dGugsz7Q-U&=Ud^YKp9MhujFQs;E>-#dPatW^b<UWlbmaw<2T#AK
zOrY$;CFPWMNM>1;mwo~0Rpk>3m*pspR9}^=e4COG#max9VE2|XaVJDdm3fptxUIZL
zzwR<+H2r<bm6bKXu22?z1BE-vN(Q*QO3z7fmCAAos8uTkpF*-m`Pd&*S*!e)UW#?f
z%~Uf`ue83<3A^`{b!8B3RL=E-r6#2?6Ju&tejSP_X;GHZ(Wh0}n+C33`5`SW9m==p
zK4_<Ml?%|iluX+Bbt`+VP`|I7oe1n6<&Sny=v5BTCc01gD@CRrD%S*|?~yW+?#lNo
zU$z#((*b1(RVO@Fj?!lOiL&K4zzixQFQRWqDUJX)tel|O&WLiR5sr>3;|1_(Ovwty
zls;8{w-VfhGC~UMN#&Rg$TQ`X4oE&%hV%l(R`nwvD0ZrS6o{}_CFjF!2UY5C^DzoX
z)&D5==A>G40K{2!)o;#Omi6TVjMGDvu^f_~sx`Df_fq*#_{K-&OksatmF;C<`l&j$
z1H@mogc9<{RZcA+0jmE#g7p(BdnzXmR-L2MMTqK8s{9RAP1%jUFx48WSPobHL+}1b
z)%`4tAxhPwhDfwZW&Iqjr&Jl!;YFP4uo0c{s@J?g&Zy$)e?%mztb1WTNwwfQB+sdA
zsJQXG%AL+nDXQgEZIZ6~atTO=>gq5=E~v8J1b0a_wHQOnQr-CmK4q&`{0FeBs;TtX
z%~8$%0N&@S21h96ny30T1_tw0_Oy4orn<?8-`7=BDNa<R`a2oi4OM9*`fjS?DePaY
znnCrRB`Wp|ICER|8f}ovRDV;%v0SAIgTV?_B^_DrsHXjjnYpX-pa5;Pibs_SHL4nf
zWT)4v-cP6hu5eG~y%1;(DsQTBZd57GfooB%dlLp*RX<QzpiPxd$@g|uUnWd+sHX15
zKs!~R)7$f*ihl}?k5sK$5b0MvrLhdC+Nc=wu`2sj^gU5I-UryA>M<1s4XL{P(KoE}
z+%g3V(}-#)95SP-Ez4kcO!cz`GEY^vXg@Trno2>s3DqElrzcepr^3WD)vR?O&sG20
zqS02(qVE9MsrC2KcvO9u_7(Q(Sw92JL4AxiUXE&Y1<X6CH@}ZYXLSO_JCCXH574kM
zxv0P0icVLxJ`SUIQ;X>+?XKR?0`nf~Cmz7|R3F?2;-&tIZk76~51)d*pSt~fi1@3&
zyNto$Yi=$e0cwvb^aZMCQc@~NEv10g3H9zq_!O-EhPHoUYJCnI4Of4#804f?{W)!x
zBGfNrqBBzcCS{?c)T7DpB3d0m7gA!>QB<-Pt6sJOpr_RGnP`ktFQg*jc=eH)z)n!V
zKzp9kYUfz|Va}+F>9v`p&Y-f>v+8vrAj#@K{=ax!Z7l`#d38n#L{il6xIY3+y4sd*
z`empK*x)Xxvtj^~ss4E$EL~K8Luuek>SRiZWT~IL3lFo^2mS7yXIV=YVq$XD;&%a-
zr=I);Q<$$7gn<;OIlTZWQolz*%o}P?D(Sna_Vt5yv3goG6iU=w`nJR^^}uN;l&Tds
zFuk|cZl9vBOg(!ANV$3!ZQm-?DYu}0M?LmB$X&Ib^3#>-BC9iKmD-Q~yFsnmD+SKf
zsk@_rR<F*dxZ^$bo?e(}P<PzJ_?p!<wC`$BU!j+0tNO$!M%1QmKMD1AHKP~iJJdU7
zgLJBY%!6c?`ph4gyKZ$99gXg*S5VNkN4>EZjStj5Q|RgKRliXKm_D_fmduChSr#-7
zsP%j}GpPRZ|F`GrAu0?UR`1C{--vq04JeGN?;ODdjj8u6gQchHi@VV`u6{{|z6rHC
z9F3Fe7pOq#nfjGtG(J}c(N62A=H_k?drgBog|!?s=~NBjsL9ts!$~vo9R}*GDXxV1
zW10kifVybJbk1|t_|Y=urs+@s)LnD-BXAy?E%{LQ*1Y{WO!#QJPD0ODv*8O6KaJv7
z5Pyv#0GP)$uTnHTNF$qtah}k8i`T4mda&lDy%<G^MmPbqP)+hNaABGif5JqBW_}Os
zMrxKFgcnhoY>M(mYjSd7Fh)~b1TI#y%?F^TG<RPI7pECCK_OmKxC#mhn&puIJFQvk
zjq#q*ESn9zRLyNlbEIkB@`g{=bWJ$L*fTWqywG_;^R6AxGBuJg%*92`yj&<=()^nb
zkt|II4}NEB-q;9oS@XwwkSm(4^j^QJ8FvGhqj9Di5xJTT^h?OotUU~{e9e9yz^-W~
zJYb<fv&<Qdg&O7p4EOpb&Fh<>U!*zmAuQd{{Fn*fZfd@ub-Y+JxE3%an%+GSy`>qs
z55-cA?H&y6w&u5=0a~U>rj0<k#zISHg{Ezp-->j6xQk-c)tXa0pwwu%2KZE~DZT_l
zbs7yl#Pyn2o}%xbCUQSWgXZB5%tfQ-4O;q|G@1z*YStvuUZF)Z?-<-})hwWjsy5By
z4dB`}DRh+U(A1s-W~b&96_j*o?vI0XYYtnfUgN&z_)V}qn!!zQ^nvD}2lRV2pHk_2
zpGHUV(TAE$F}Oz>RTCupHMTww8PG5`!R}+t09}@PqM1sk<3UX-9|}X7%|mD$)=Z%w
z#E2$`D!E2AHHjc&8c`V}pK2Pi7C~lG<3@Y+XPWbKFqr3>7wDjLRJ)(P*k!N%i%QQN
zw14)2IBHYdAmXHb!OuHmzO{8aM&_!ue2gwPZN>r&*Ig@I4+#(Lw;KWJsl7;F8S&B{
zqW!41mYWIBe6&GdL%~-&g-VV6v}Lr+_-jAfiSY$$*HUskNV~!jKAh0*eFF-?S`HOx
zhiE^EgN0D-2D;V|rZrfnp*38)WgBEpYR$CakI*vQpdYE-@Gj7zv<|dcjn*!F8GSL@
zn=3K+Sgl@#zEfHYrQqVUpUMGxTH9~}l4rD$^v+Gx_R?QIN!z^wgE*@_I0TVoZK@3h
zaZbC4zT9?R+wu`@-cqy<|3W5Jdz|+FY1-u_&`;O8eg!T=>nDcj1?`e4n1oDi<uF{k
zsJ%c}1TJaoX(qF@*C?c(t^K(Q*q62b)8Nw;t#l*&y{dhczEhK<T}Yd$T<z<08!Jzn
zc^t0gYom%N&Ua0_^b;5?&>E+qwNQJ2V%pcWPL!o6(mL(}%nfa2Al$#HwSEEpVr@5N
z7fZD2L}1_2N+Q6OYH!_#<ZUgVHqd2Sg)_KvZFLazDzv6FfZfry(XE-g+Su7psMIEB
z(SP8m(sF5&P^~>UAEZVrq(Dxs_H`e?)M@2^!eG7jJ^FFp({|GBmj>-cigGq;3n-4%
zq@ARcNwfCzQE)BVKPe>8s!iC1Nodo4_YS73U8|szV~3WHd%)AXweL|S?tSeCQLtd`
z(cYys^MUsLIbeIWGim40r)@q5{fFACwDEqVeepvm_G@h^`#Yemp-s_a?JJJ(_lfpD
zHn0b^FVNaEqz$D?s$p$OAUqt=w$e4KQEf2g<;JvM)1LmR_8MKE9M|q>1~*~V_R=~$
zsZA?`%rh;2F|eO&S$jcjbyuiH#!ffW8KXF=d+{V1?R8I=!=QssNCgv)y0N=(+e!D}
zEKr<vTPWOqOt*nbe_eD<O)&4OdnXtuZn_qF&fRrWlo*nS&h~9!dg`p7nxOBc+ehal
zZ=LVYfbr2ir4+oc&bc3=e!73pq0wKrXeYSiy8J<q0A1*d&<oUsQ_*6OPEM|!(0Nhp
zKUnvL1?EF^Q^U|0s&hOK=rCO#l?#RIe!2>BQupspn2*pgtvPTwQn!9TNR-Zf2hgH*
z_bGaCN|#UDwm4lsJr(h~tOQ^u=ydDBoz|6cA#z5?p>$WGZrw6SCh2NE0(VxYqGIf1
z-Do%@&*_3F9dcebe>oIVbdCjROx1BHjGLyb$)oLNx~^{#rZhu$_H%Sz&`q!~`b?eY
zUi4kmi748CNvETk&C(s=!HaC2cRUPU)<qRU?~1PGU)a5>i@u0q=jdi?Kyr0n-jK}G
zg;VZ3U-u5(CA+3OJOIf8-Dox%3w8QFit}C9<x%RtNSC$=25;!rQmw#E-91Wc6zkrh
z7*&aG>!%>MbkAr3FV(%f01CHtGk*kErW-WEwQ}7HMc^uQJJ-PO9bMcY6z=MLd1$QE
zxy}Ts(hX2Vp<4H13KVK|bzYQbuGKC79vXEzyB?5woj3h<?&+?$!bF3vXffuZQRkQq
z(xmgD%M8uBpJ*{?(LMPDgK5`&O?#{k-F0`E=+wQ^4!d2t?hbI>y6N;Oh5NchN}u-V
zaw$6VK$l$w(yO!Y!<1P2bboAxQxA0ov=lzl-KNrte%%r}F%0N_qYI*sbvG!J{zNCH
z=V(y(AQm1D>G+2MI;?w*R)`T@r!B~+Zfq?Kj_H2+66C2)whSoax*B?=PUxJe-g;8E
zV<u3Z=`#L<qtC56Nd$&wtB>Wwgq^;*9p;bf&rQY9?DY;?q3EF3(G>?redZsKbkeiw
zZiBOa*~fr6rr$@$9v8ik3aDN68gJ;i>9Z5i=&lcV59U4erIk?k)X)7E3SRn8^D$g+
z{lMQa@1wWAl?tbP_3iXZ_tQ^M#hSnVr<p)IuK!R6O9A?2-vTXAe`*FAgY;YNK~Cs%
zS3xgWALs^uL-cP_Ek>w*21V<`^lwomO1S>hH-ULl|Jy<|M(H=z0wr2Mh5U`t2htBQ
zPTy&zO?SNBo2qXU^nVKBaH4*p789JLZ=MRpvw8(BVi)u|f5K9x-b{(li+W!Q+g;Kh
zFNUQoz0He2%hub`LFcmm7M((_=)>quc~!5XlyZ*#Z>p8d)o*_phVt|Q>w%K5AG>0O
zrEB^pv@#axFVo(vP``!FMA!8?%F-9<mz{;k4SoGf5V@(JD+WxlUO|EG68+lEP`IVf
z*#v{7`XMbuZtDe4(O9PUnE}0WeGp}VD)g(m;Qbwa&{a5dS6}-dxJteAtSNFl7J7fW
z16Zvep~{^a{jwNn)apN$U`%!TACCaEULWDN_$teqx(v|G`Zp=l(xP8T=fYNf3J)%|
z={1y&XxFcGg?xv8nJ>6b{q!4v?9yL|0N1U*L)+u~`nR2c(xab8FT)4=gW=$M_0Be!
zm_EJtF*x{8FY^QDBYj6RT<O<8qka5<exa2jWRLZ~?t$nN{mn}-Kd4_y|2cF>pH6?!
zVZG%gppEDg&%n~CUbFz*n0_l&;XT!R9Dy_A`s}?R&-CXhYVchDgffk`h6u{Q*%`cQ
zF_T9PHGVK;ZwSanql01A6xee#m{(Bn&B@^Z9YCE8neRdLnBnE~u;gNRNbfyY!v{$~
zb2EI<0fX*_zzp<x7<811@-(E<VaCg_s0V%ChNUY2>SI_+A#`8ERCjQGhEq%F=Wpnw
ztnG2bPC5+-7{(}N7icKkKOKu@u;EX7M}!y@RA(4!*hXalVTKSYC<!+lq^hNph8uMM
zKEjYIfk>nwst2G^hBShSHq4<waf~67V%V{U`;?A9WytcwSmF#{t_F!Wd=d$T1VhX{
zfSoohqG-bzgB_j;>-0p!-X(xZG9*#m-dTgo8FVHa)(GMLIm5~~p>f{eO3AVmgR29$
zRD<IcIFn|W{VIl?ZrED_F2msS9rP|3UZ5J*Oatl#@JtyxJ_EUAm`0b=vkZy>kZi*z
zbS%AW$R3Bf^@^dBLhx4&BZX+qF@)2xIM)#T20HT$36#UiH(aLL-D`%3&oGJt!<%`4
zDKyyH!0vT}c@lrvB7^!WxEls;7y51*xKs*TY$&AoMu|a|1(92Z|ItgO)bN%F+-<{}
zLl||L)iALDGgNN)(|{3H82ny<7k3O^d!T>U5U7U1N<$lE&Z`V-sJ5WmuzM{UYYgY<
z?^A2|gT4+?XZVetpL)ZFF6iAe?4x%}gW=d!SZXw^je$aoVJqDLZ#DSE!Csp|eHSBZ
zH(2+0LchbXrX0R?8pd{_v&-N>746-ID^lp+H;8dlVtS83PG#c{48623={1~r4xjoA
z`{=Lr(BMr8_(z6)R4~_X*!v>X2Mm9wqVKVxcmRD*405V;8#KHS2e2W-fhn*zY;dts
z!Rv@&gkJDZ4L%C!j~mA5+%sWFX$H)s;kX+_pBa`sfcfW!XB4QgHKufe*csP_z{F8w
z^it^A8wX5Ka4>pKfoqONn<udAWPEf4V9v(f^z%4o9889J7h^63fLx7RK1W_|x|>n^
zGi2P2{8*UqF#h%#&^(PgI+}SIPtjFuZ)3^<fch9O)7=$c<K|`X*UuP6`(%G(=rnN0
zjsAY<3otsDLm|-kF)d|5#><qyIAQ#Q(wD(TA=O2O7(b@0Yp9VKMVpl{V>rDI!j0SP
zK~5T_<Wq$4>0xk@#!r%f9cAplg~n)O=TDf67~?5QyT%&dq7COM<ExZAjx&BwPh7ll
z4V6SB7+<;$^QVmqia^d7zukjrPBd;^0WQht@CKmI8kaWHzY9w?T4*bN&Uln6_|F^7
zr=Xu=+&YMfN;M|Xjv~!yKY_k<qbv%}WEc}DJ$Au(ZxrS;jVZKKyl7m(19!=o{{i%}
zj6PJrl5L!p4}+JD?|7r{im{bK;km{Ry2X%ZT(}J))_miGS<t^`6jGr?fw86*mI{r&
zboutW@e4Zm7a3itD(!}G8O2O*8u?Bj#m06jmnbn_qqpZR<0U#Qlp5vlfV*u>WI?^m
zcy1X?lp9~B61fValG0RnjDz%IzH78!4#`TZvHd(`s*Lm6L8^^K3XHJE_%DT@YmICw
zv#K+eS)fsGOs0I#J>v)TrfV?1l!3lR<4OtaHW?Suj=b4eH4}O*M&(o}v>N-0;9;9l
z=83*`V>F$uI*eb_orX^1a1Hdjj5ADhOzt*r^4nB6-#T*?jlIS?+Bo$Y=Qn~pG+s^v
z*dt@gLHOHmw77r_7~dB`?XhviYK-%VG58&jLE~2o06k=^x&Xal<I(9LBgRu!^o<(#
z)24UKxQpH<PmR9A7{j>HKtb6Fqlz+ilg1s^K6E}aX49pf=SIsEXxN$t=?`jWn*SEK
zqb6xOH0(`JOTjsq%IVQ`G(EM#(lOHlEgD@+<!d40YWkTHVQ!}1k75qoO$v&udzkva
z1?Oq%+5q!jrg5q%^)?kzjhK&V;}R=0d`<0owECGQu3^^vO<feWJ8t@814w|$R*uF%
z)1w}cAXDc9D4Z}=(JnjK)JSVrh-v;-G=`eC2Et&N$$@G+!%df^@ad%K2m1P2gz4Ou
zP>3|KsT42Dq$q|@(I!STRj9_8e)$P(tZCs9D4sF}P}OamNlW3)cvIgo_?=+troPjr
zMEcCf8Pj~KiAyvcq6>*hrj3c1%d@6~v<FBwz10f6bEYDCQ=K<`c?f+erbNoGrkWOw
zK`+fTPX~X~O><CzflniwF43ie3nmp6D`uL0d><MYO?J02m`kR=$IzE$+D7mBY?IeD
zxPRG{?uWiBrg?2ZyK34)r-K~RqPJl_*EFnyNS^8SH=vMjdXo+b*G%)cP$)2|-^W-A
zP0^2_aNYF!M;ME>$n<jtG;Wy2k3r_9N%IUc#iqVQ$ds7A(*X3gsaFMu%S>OLgGjmQ
z*)X^Y(~qx1<c=wqvT}D#zrF#<O4FS$09IwnrE<G!(;u@i>>ATx1oUc6Z`ne!&Q#C{
zuHN)lKMdWonijkQw!t(%189w=|2~9FlWEN^z%-lQ%|%~}=_Wn5t)@15#M(@Sd6?jK
zlifXFcbKYPgQZT>@6J%~GEJi_O1J538l1Ur`h&uZJ*K_K;qL>}#lNA@Yii5}*JpZ(
za<>mn){iLM_{g*aSB$3jn|##JA25k-p!2cmF@^7*n1*QW8#Dz|kafuPT^w8+HvL9x
z--zh|#jQt8*Il4DX8LF)xTmJy8enPMbY~{aPndSo7t$t8uCx_+W?DQ8+;h`hCET_(
z$5|f%#?JhBFW95ztMvP@H;>hUIGC6J2!oF1eKh$_=CvQd3up8H=q-56yzK-`xR~44
zK*ZI&o{Cf4%)?7y-rcOEdMXd|=d}CvG?%);pqDx28(?~yg;e+HV`iqqp07D$CRNk;
znYWK)_Cn0JC>jxJzVZ$%g_+xXVJY0)NpHxLX7P_`j4+?4dlQl74El_6l)0RelF{b5
z?&ym#_f()S)_jXX)bZxv=}=EF@3(=-Y4b)mpqw#>G(j@a%-9E#WPW>?B4=mK<=fzC
zvUzbSWX_pKr@`U#=6Q5VNHNcS8=$G?6|}!dGvB1GK)Sh(-ewu*Ao_J*FdvAAiA?j0
z^jV>c=JihCE}0k7;+JJk&4FaL`6QK!T{YKqp)tq2Sd3BUn%8P6a+YV-dxFh3CsJ7W
zn)yaQ{`LjtYeK*jn*AxRbln_78J8k+&ulc_FxOHl;HEkE0rZN^&UD}@F(2B2zFTHp
z4osAqUp@<ix6OWW=qod?qySpE`4ScORhWPH8+~`oE-OK-RpueuAy=C}+Xk5$^CuKU
zsWlI(VWQ5QLgfne=8F`bx@Vqi1JYm)89`s8`JeAG&rRm@YD`|U`BfeCTFj=qAg$)x
zy8+f_{{C%9wws&i!Rs)0Xh1s6%qEPp%j_Bqv)!+l^;E@k-@M4Lxn#ce9-a96%%901
z^3eR=tMKrVx!4|<{pQ3;7#c9UB|+q|dEy_4JTbfOM&qEl@g6{i%tz=TJ8ZVhhxHM&
zf`gfSYOcEgv*YH6J|GijeI;C)H2)G0?wR>Zx^eT|EZ7Rp&hou=Dm0E-KA@bwy~X$d
zb{#Cs=&$T($!~;RC(F@taL$(Jbg%K4r6Lt*E|%B^*mboGzlBCOOT_?0+%1K4aQCoW
zp}QEKmbvNRyex6_A85TTo_k@z#}Y)*Az#a3+6ntvhS$+j=5KMQm&9?4v;eIEmOm$8
zH_&qAUziB81X5_>gvIG76oW0_>d+WsY0U#@sHJ`cpkbC*8(=BilFJ6lNlQopxCjfM
zs%0ZB9<<Ynviw13vS>>tJq9tB_i3LRYuRB#N3&BF-{}C2vs`z=l*U{16hb{?iToPQ
zBwAXpz<iQrJAEJZtfhwnLdlk;N1=btvVaLo=Pi%usFPwjK!Mm)%MAJfrCENWgIc=9
zf!3}JOJXaWxnSX*gI=a(3jIhfS{nD$eWhGWFjXSuS*mC$%D4PWd#q~~4h!ZBEa`v2
zV4-DQ0Q8G2*=sP~8<zD{4}8<IgN_WvmRy7brk7ZncR{4o@@F1UZd(!$p|8wRO)0Q)
zOX}MItFU}be~P=7Y|1QETEc0uv{qSk{$Q&ung1U}unf}gvDPA@n(jJFN-AXPExDBG
zzh|i|f%yi@Bz>5w(XvMjyG@qau^3^q#e>p%EtZkl5NWmiRg0Nvv#jMoz1>n;0n84|
z)t@kxotA2<{Oz)AqRm{l)$;u&(EFChDuDJ__S03a2Nu~3DE3-ZufpLzi?#qBKC~?Q
z0*#L>yJEogTUHK%3|JQ2fx=_UmUm(PiA8f0J`GxKk=sL-D%u|mTb9taX2im!yya6%
z0^MF6x2&eq=7eR=u{M~Wv@B~y>oZG;-{CTa^{=^*bhZhnT8(2iv)O=lvFV{nceOb|
zaY8qnlthSl*hD_UG<n+mF9nibHajTn=5534fryXICu;!dYa^yyho4O}?WX)~_-}w5
zw<)67aDdH+bD$S!6P5~*Ae%=*D4ei)?Z;%a2HVUEgWDlCvnYZZY7^0fA%)pg(>^HN
zW-dK&CvBenf<Z*sXug9;q|M?d@F~h>IlZl;ZGt+%#n_xFfWcUsWfW9CW%IlQB+h2_
z`w)q@+3M#}&a$qKz#lNl#*b2=XKjMMhA+uBUNgX*vnhWUc2aH5gkhLzHobI=O}D9}
zSmpn5blveeUtJt6rQ=m}q19R~ZFS4D_uf;rTBWU)4jmLN>d7FIAVQ`j$c{urmMj?(
z8Dxp<A$tijL<UL7`#sG+=X38l-*e8r&u`p&&bhxN+bLJUzZAPeD*#WmdxN5>>2~vI
z8FATeHGTUp!!GGrNM_o-OJyTjb{!O7yJENE7H~OszXm~PuARna0rRTehGYyS&u;A{
z$Q0NeJOSqm?Yg7k%r(1Nzd_`>-Pu<FEV3JKf@HDXCzR|evD-jT#ZtS6K@cgk%cO+g
z4Z8!w@V?wGU>i)_wEOYDor&FUD(|ec<IREUD!WVc(yF%ObyN7Z#%_f-hE{9GeG`Z}
zyZICotGDZ;^3Vpmo%EA8+Bpw`cgt>?A9Od_-ED)VW;^XDylAo0(N)xH=Sw+;HoK2#
z8{2Lt^@H~vcE$04ciLU3f}>q_EB?Sdb=$2u4YNIV4_Wk8mD_foe+<!HyRSY$?>)Pp
z+F_~BPDd3){dUuz05M?aPJzThyXDIua^EhRb|DY!Tweli*iN$?og;P)|3hokZqXum
zF=qE&Byf-HGAU^_ZucBj`c2p^cm`S~?KUPs<gwk4xFu{er|iC?{gpkV$N_d87*4Cu
za%8lG0Pn=;{S96mWV}Pmi9?K+DLdfI_~8X;JIpvkr8_Q+nqtg_D<irOEjLDJC0a)q
zyS8ISk1}S{g?Ehc(Ni$!&UlNW`^Op1FQe0gF@xU!wi6898kjiA*h$GnPlit*m|l!z
zisySXrYP>^!)OhJPri%|<51(rSVHG?PBF%W@YkQgp??4sz!3je2G96wJK(1o>uC#j
zh9UnSyg17!UJqOlqny4B8_e)+g`p6Jg(7<4Himc@ZbUG|NdQJN5-8q$j<M}y;G-BH
z(aR*7Q9!%*^NfB85EmGK(7D=JMmZg|y2!YD1zyB4ZqN%Vo)NVYoe7KtighM3q^rTZ
z#AvnyAek|j_Jt{oMN|iu%BblFNn_aFjE1Fj#t|OKWkysEe9K^D?ZTKc86Q)rY!)My
z3S+Vv!L>l-FwW*<W^x%H1)_D8;Y=B@Jcc)=X7U-vDwrr>?4rw~kYSk(FRn8j)<Sg=
z!^0mU#S8^KW=a^gdC*zP_}b<J6J-o0RSn!=WKwGMCgU#U5h@rppFvF}<F6|~R532L
zf>+J>s1CduM&$+IY8k(62dQTi9tLS(_@=@{Bcp^W>~AqzN?^B%F_MGMR>ty=V6cs`
z)e*|t8TIopGaU^6FP?AK%(Qt@RYeyghMv^j3>9sqZZi&@1)!G^N_)jSj6Z0*a+e{a
zLX~@ryS4D8kFkadRr(oK^gbVC7@tDtea6yOcs;~ey%>N8j7?N8HO%;MFIppv6RuD_
z%E)tpmN5pCGJOvjJ+=*KK4L8Ngiqs)S$_aA$=JRMY92Fw^M=1q7`=@c;1uKOZ7^Za
z{A3Cu4oopc>l~RoIgmWaWUHX<5Yu%7c+O1qp8y<YeoM6|E=(Uf2<ysR7Y=1^%w6rU
zca&MR5Upd()uXg0aAzLvfwtq!kEu${gSkWkhfgpQsP6V8Gf@QM#mrw1o;UN$zX0%I
zmeB^sm-*8>Ab!l9??Y(-)14{>1DTPLkUY&i7mwB%Ccgu%v&@ZD<Qc?_n}g{JX6k9f
z8_IlT2Yn(YjQR9N$b>VW3rBARvtt2(k<3$G=sd^#kye{g%-H3yd!8BL29X%%#%y$6
zU?xPNGnTo8VrUnc123W#$J}-nym)3I?cfraE58RxWF|fWFNtYy!pJT$5714K!rU=^
z8lFL^%yi0-q%kw6V-)F3IqeWGGrMH?xiXk~I_s3ljJyqzZ00iBJ6&Nq2qBrnY`p|E
zxy;Y$6?K)#S&3F2GnPXB`OK<9kV58E9y+fv3n|odo%#3*ND=edf50ndmaW5&W-DRt
zWI?8sIqM+E4Q7NlnB~l$XeE1-`8$PBDwsQS(OJoK+=`j0Vg4b)2y2<ci{M%vvv&j{
z^~@I<0B>M^Na>+Q=8~BZxy77*2&9?$MlwhXb2%+8TA7R5;BOmqObhevHm1WL(A~jY
z#09>S88HNAH`9gg{vKv=9$L4Vf8C?ofoU0s?mJA;Ef~DZJVU9}d(1uk!1Xc9X+hf0
z%%fcO05gQb1%pf{dQ%NCPtr5w0W%{LBE!s(f8oUl^B)UTk1}oMai|$%{z+9)51H*R
z0x{0iy@-KMFi%gxi%F*FSBO5wd_ngU=KOl_rkHQPhhM~=b@p!%N0xx9q@7rED6V&q
zwYL%E5bHkuuFkANdJrFGIrRbO!t(h9l5VVQ%2*#^1=$wEo1?6#O^`XpiU@#=J4-^_
zfD^0%It+G_RZcGuPgds7KzOl4&%j@A)-QA5uMcZIiTJW4mGJNs>&tYs{8?-1SslO{
z$-}S%SuZ|^&eN<jYk@n%`uZ+fXIXz`!d@`zkHr*P3t@fqJDQ=a@aN%M80)>C;YB#>
z{cdzdupW3|Fp;c(X)$(=wI>QBinWoRTG6ab%IutHmCS|61=cgGF+s5`mlohIvU2Dk
zLL7@nr*-04AN>Gc0&96C;E60j7A#z1S+3Llm&^)Dfx{`RNy@aOvevGH-)XF_Nr+~!
zObY<aWZC}>gITO4egI~(yop?4*=QS^!&07r`CL|kBRca~p0$AIv+hwkqJVWI9_9;K
zm7!2}jb;4~^K_k+eGvAFSYMCPzY8m23FxI($~r)$r)8`U|3>Qu>m?y{m$ROx*!xYE
zD=pwFSoc)$qLOvi7o>`nNI~do)(f<+tYNj&`KdbAh7q*tSrMyYzJawzkIqJx9aY`m
zV(p<CktS9e7p-R2z8}D|wX%Lb4be8%r&J}{&f?Jmu7kyS1G+m|dnu&d!)mZ#Ot)Ff
z1JT*b%E-fD?y!C@h2&jU;0(0xv6NIE*T-T|@OpqHDL`wGwcu@#`>e4>s2*ZTsIKAx
zEA{|HhFLFDo@d0yN~DzE7|TSjoQJFqs+)Yo3Z^>Iah5M-+9y~iDB?89dVw}Gk6C;Q
zQ#@g<pw!zG>m{0Qd-iU+EFIWA9N?VT8NFy7WZPbWr9<qClz?+)7ts6iFnc!b!Cct4
z&qKtOZM#g-s3YuE$XU)j%J!ua>|^ZPv<`D;zjh7eIJ@R2h@50U3P;P6UHLIuUhL_V
zJ@sZg&xcPw?0ho@<I8S(0b}uFe{&a>{Mk>v3`Yalv0cCgvOlH$*=e>51yIkhchFhr
zv+U_MT5AQdFCPaYggx;m5TWdBij#-2_t$}hvyW3CCW6g;3;0O(sx(+S$8MmdcoaL2
z4ns$?=bVD%dG;^=122X>j{<wK>>X5|eUbe!9chVUFI7V_o}EJLzXbMGs^Cs!i!RdR
zGKnqN2W`o0-|sLdDeQ+7G)ZMI{ThfgHis(Z)7iQ7l+I*lQ-C9j{YfE2vf1L7G2Sa|
zM~Zaiu=i8yI+xx5BXnM6H?6{u^4PAlbIoV3qL*SJ+hrz1uCcF+;Nf+4+6h{N7qR!f
z2bp4aiXC*9vX{OMU>Q3|gE8G;AE4X+CVLUR_AA)GD=-(8Y$?S&tJn|diCWD*@)1Z4
zyNVL_wd|HKxK_`8mev^!?67j+8rhw6`tlY#v;oSR*k?xoXl8E`(;B>m9YIH<+t?pJ
z4c+Z*lLKTr*k&rv?qo+$h`5VApR(NDY>#*0VJ|zg0`A{o&liB)WtTJocaI(V4t(lk
z|3NoSKRezC$pN<Q9+VBTxwKNe&u&@=@__vT56Xtw-nsD5Hp1qFLS~fx9;ML6*shsS
z^N79T5nAKy?HZ5?HtQ}rAG7Dh0sn-3fG)%-_I>*9lRYPqiXI#|A#@bSk+b+7T27qh
zA4B&c&hvSYbmr)((B?4bf6oBm!jV%knk#3p0Lt8KoTW!FLq|B#^awx3`BDl|cTQFW
zn8!J@>Fw{qd5<32Cpad`xSZq!(}xPYIiDXu%ZKypMhw)KQ~d{8ew^DB5<kUhpfJ5Z
zrz;k%0L~nWGX!!}sc_~rr|%@-XE{5Z;YASVlUZ+|8O-^HRwf~w7wN$q%K0G|vmVaz
zrBH7Khx0AGh~#Xc+-4Lf&NHWVv5ifMtXR(0wGh0>$>ISW&-r>c<P$i5)18vYiChek
zB+f5%PhR50KM!A$Ij!HJGljD%0arj8r;)a1>74yZfM4cx(fQd7jxW96GdT(-I<q(@
zDJhr3QSzWAmm|6X_*IVgD|Tq+aUSjkKA%&a4pP8ro9_8%+XCB1?*mc9iQEcO%*pNr
zqJ(pXP8gSRKA<v(GR`VG;&Fqs+YhaB&d(IxzsdQt4t6UzX)2IP&RP=yRUB0?NHwP;
z2U_YlCuv7m&#9svdjlu%7f3d8j!?1dElyVmTx#NE{g3t`%^Z{jV9mqH_MF%LlI{Gn
z0CaE?*)Y_}*@r5wnO&So3Z`~*=4IfD>EXOj=VESi7H`L>dpZ0ppzm-t(mCV1oO&JL
z_c%FpX%BGP--X#h&fpoe?sIJP6^S7ZuNEVEz}ZY8_hF816)cQ!n%;xXQI3yoH<XTX
zc(i(a$T|Nn@Q*mnR82L`>7)-PO>i0~&^gJ`(30{o=OrB^pKvC2qcz3J*$y@K+?th8
z>cAbM0&Yj{H}}zU;wI33)R|jP3zx&(gKxrL7jCBza91wl2voaq8~GHBI>POswf9l(
zzhv+jx1kioox5lmOdRLN(Us=G?RkXGlic;>j3>9L7%eZZYydcK?kqZi;KQ9(1iQZ6
zXsRan<3>>E?-aL`7B2qW=N#Zg0QZ0|c!AtpioKlS?)IZB_*rgOFH8h+$7wYd%=Mu?
zRS0(n6`X`}CsEHaGmIN@26n@_;a@^Bf-AZTrIFm8I`GbM%^N|Yxy~El#d&UF7g{k~
zeJNbKz<pB(OR?PW=^z)mj}qWT9QRpDLdJ7fA|Gp;nZO<GLT@5>^XtGTanIBBl)@F#
zLNS&5(PB(O8h7IsIFrt;7{jnHa|@_qBZG^SI_?H;@m4sK#WhftD4YB4ESSH-eUlAb
z4)@i^ki5#(?}XcV+-UkHQ$E*|5@!Y6H>jlER>)O#0&$Idei6uZ?!=!MXc6~|cY!G8
z-lWWa2{(jF(Mq}X|Lp^~aSz~rIrs54bl&7zUV~2++_)m(D!B*fvrSdpmGrHWYHnCO
z4AyYpqU>WW_n8LhtmC?Gf=E5LomMQ3Htz2?KyPu^(5G6OxDIp$Hgm7iDd`q&6_rxA
za_6iCu#MZTfn+;()-SNz!ToIrot@mD=ylh{^`S`VZEhDGr|9KAH4VHw+-GTPb(d>T
ziSB#c!wW$AxS99hZ$Ed<Z@>+3Klv;Qh(YdgiZ$Km`cXW8i0fSe(P8eLg^(HH{!j*o
zN4bCSU}B7`@GS3o$<{$9dMCJp6uF$_z7q>WkGaA1aPSFt;kO|6yw&tM5(nP=A0g?;
zlhgO+op_-XxjD$Y(}>m~-lRW>Gw(&J2|3JbrYe6I-s`6Ucje9c2&&z98xtXNl;=ZR
z-DAA3@?glF=We5;4##;#kwAFxCcXwa!8=a3_DS9hdgyra=KTWV#k(v5!kgE72-<vj
z->!k0Q@qza(emeQn1k^J@P43tY#`5v;`gU{izxGRhPUNKxP6xQnHvB>JY^It1oNWl
z`4YmbUu(nsgz}n)AsWt`MmwAcUKCY4Me>R$X?c!!<SUqn;*C<+Hkx;W;$G)@-wnW-
z7~Wg7e!swbYa>W3FXt8DF7o>5trO1+tUxP)XP5#!k@p6@n38zU`N8fbo}3Cbl6kiZ
z=(bJaH9ZCMsk|?F7<L-(?{m<d&Kv(6GM9OO(@rvzcZ#wBS-im*Sjy&o-wtwx$0-8I
z;bs2|lFQ4X0QyzlYc(*D$D29^lF#F82d;qkZwY)V<UO&2>LT7dv~n)y9dDxyMG0>M
zZOTh|-_c&EjQ0!!25<1T{|aZyd7(R?^d|4uNT{jc1yM<HC9hNhKozf|50W*!TqlgM
zmbdp)@alNIG0<Jl>!kNa1Mdb-_sneMaRWeZ@gk|#yNSoA4QMm(8B%6z;R)WyKwEh^
zNswvh4c`Lk;7y|spLFsvuY=dc`#J`|Zr%%au++n=??dNpp4k_cdU-t?AbE$^MYR%l
zdB078cMpz&^z(-41m^&6<tMN-$jkJ`Anx<l&=zcn*I*Cwz{bn`8cK(Gr|9(U2+!6I
z(NUh{Yv9Lt2M+@AkSC`=*#z%t+ILLy9?&oHm{;@;M4s^4DQq^y>!Qyu*z;31!Jq?w
zK|gqod`l#V6Mtww;0O5`o`4_Xzi7pb9_I5Y#_z(nEubx=D?eiqym8}4+C%gRzj_6n
zIm$QR#t(ap|8Ogmy7Pbg6aziZUr(`c5598=bf4fal7o2i-=`x=Ui^2BFyYO=oCur`
zKe-T{zWgBi+`k{+e+F8o`1Q1`_2<8F9=HI0wXF?G1Nm>$G5^#2WoIxKXZe3nsbLU*
z1JzLk^PTx<h471MVHnB}t%8X#{)I@G2<InLnkRz4m7aN#d}SuabdG<YLg`Wbx%7&P
z;r~S;?F)PvZP8=-yY^z77x`az!;3h6ShNl1<M|TWaVPNa)&ZEvUrF(=B>wMFXkFre
ze-o`_{#tsMrt)u61|p4bqN?(AJ_D=knV0!$D*DXemv6+FGWjmoU^k23$pbH&pF#n`
zEBq^q;aU#=X^Q3L^6xx^NFLwfNBQ!6{sdLJ7x48vKnnSbLt*I}zn<Rn*ZGr~z!&j%
z`T}1J^B^Vs^;;lW${&9fV=Cj%Er9uQKHjLfRrt%<;8pN-lvb$Zk5LApik}|`oz?su
zLXaB%Y$}GY<@-C)-k^@3;E!fKfAqiT690-6h$jA<BXF^q-%1P27CxVf*4p{+{s~?O
z|H(3pzLWnN&E-8l_c#pp@ny6#>gSKr$@T%hh=SmQe3b#@K7S3ZgNFEnQ5gLLe)a}P
z4)YzQ7@%#0FLlHyM)|+(LUWA&@k@|-$PcEWJ>s*h5FO`#_&e|u{M4i9oa8^IN7`fl
zljQ(B;qU$mWQs3*1J2kBX8sI-gJAma5OEZ2&Bw@`1g1aHc~EeBKBn@J;1v~y<Sclb
zhp`;C3DS4Kpo`!os^xSQoTH1}P4Lxc03H#fF2}Hs3i2uceN50z19cZTeE>Db1s(K&
z^AH#)g?d834MXQi!3?S&^b~w=1<y+``xn5y1*x<}_YvfpG5NlNzoMYUPf(>o=P7}$
z^fOR@fiwNg0fH`i6b1?kVxi`=V9Bp&oe@-)V)SPPZuBY-5^NlVWUwGQADtlrWi^zB
z3Z7j7rD1|rI*Jo6cz6o%2*H}~AsHz+H4Kq+g6xHuk|=?0HAu9eg<|371y5}IArm9`
z?gYkrLGWHZrY2TUNmX1I1v}`)87EjoN1oyZP4B>9f?z)rl8J&}>8Y0_Nb`qJmjpwU
zGe{O>P^DsuU|Iq?Qw4uf);~?~dJ0@i7p&d_z-2+hujtGYtYpB^Y=MV8?ai+UVkhBE
zj=+_Q2yz9wi;%f0;K;zs6AVTGpDz$*gI6GM{s2A|3ii@U@0wuF04!Y>c+#`CNYI}I
zEyaT4bg`8P>?r(QDtMJjxXT2`e+A%%Kt`+AazP&L@@@(e{=5Gw1TRnxcBSCcaOkcQ
z9H-<;wZO0uUepM7Jb{{8!B0KttP|XgMrXZXju?OjfqxU!Gzxqu*?UVce*|`$1iP&8
zsacSd3_y!u?^?iH1?OtvMVsKOHdtsE^ie3VLok70nr&vMpoHeDOK^v-k8Z(qA(%aa
z!C<s*3$lNJnqEN+omRLbc$vNxc~`Kq0|xI2o~2EBpI}G=XZi)z|G=36!K#nZ8Wdbj
zg~)xu(t6;A1cgIrJrK-V55TZMp9hf<!Q5JywT%iwcf!RnL4E~f9tyM+Xm})epGG(?
z;L;j;Lh#{C40}=#5et#Wg8Xyv;)%dx4LqC@biV|p_QJ8V05}LYxI@HIm`<5aCn1~m
z$Onb{mO|$tVJdC=orP1|AaYok`!8H`u?d4-MAKF1N_EF>!kx6DKO%fZ3362U3Vn9z
zm@w%mJoOOXYK4gt!j~q|c~ZC_8sqg8eowU?Uc&1C0pKm<P|(Fkn0FK+zCtP0kN639
z{#WB6Y@=7YzwmpiJqQr~LTkK0p)G;Fz;jyIMECs}p@1?>XN7<I!|x#B9a_%?3!7fY
z=tG2MZQz9p*Xtk|CNy7!NVqVKqJI&>+h2o33fIrZC2&s2dk&693FrO@$!K94MXb&X
zV^!eA2sh2dBwP?)ae+vzu+x@~=0%~@0DPRVYy_h5!uRJucY;tstHMN~hVs2h!uz!2
zza-p^z0S;JVLFwOqzHS+r&M7gMPSo}H~b-zF8uu&@Gc9hs0b%R_zuO{Glkof5XlnG
z??)?J*iH|<T;W^6lpDG#92>x7<O!cBF*W(Z9IDVP5OTIcccE|#J+!Y0Z&KmNbzyo2
z@I}II7vPG8ZwJ6qiO`8cD5b*k07#YzZMB%u8^URNbe0RJ&xW#_!k6X)UL{;60;v|-
z(V@l~;d;C0@cye6mQe(^PS{GJ^?G3y#TFWbOSEvNQP@@hHMfLEDPPqj?4}x^W??mj
zCR&8k@Hewn`10ovX%p(H0=!*VG8>&8!uu2*>J)lW0I5s3i>~o*Vdo%7kI?f=klR9c
z6ua7H_6o<F0lXtDnhm>mg=v(4yeB-W1HMmKJPn@q3*TD@y92@*ls6g_zQl#n`@)zw
z@P>pR(r@rUxb`B*u<&`xi;oC@qK`C=3d_Pk#)R*YzYm4wY_uK;9XQZ3F8sI)Kd)^<
z7)0^HNulm2ls*=&x`Kf|5w=<(GbL<vhimqtXX)sMgJ?-7BppSG3o+|XqUas~4vIdT
z2Hqjj$REHti>AE@-eFPuBXqim9KVG@R}r65CT^ln_rQxIqNldQ!=s`)S~VQAiLRf(
z(A-6Jv_3j63eSQ;4^bf151$YfWPo>4G@a6Io}wZtw0Vhk&VXy)q8SwU@Dc5EL#MB3
zF}?BpMEgj~DbY){u;ed#^*2Zch^BuIp8`eOw!n+iqGtynaz^xb19YAh+3vp%OF^Pk
z`s7crXg$4RLqzAOvMp2;wHf#b5r-ZIks@_6ES(dbryC$jbo?xoMvMOV44vmiG2?J1
zMzoJgkS>VMi_nS{B~sz<MbZ2WbjFFkFrpPN%6Sty6GR{Bp(RmNW}_WRlIXc(P;*H%
zmjb!TB4>K`rikv+J}y->oi?~>q92|HB3-m;J=9zl6;qlnLli^x^O+(kZ6C8lPtS#9
zwkVp7))mnbib&>&dYmxOT+vo<kgFoiUr?PV@;L=%`J$SA^!_UlE!~GXDHIib4(2t{
z;5b^>MF%#(M3LzIm!Yj#^mjE{C8E+~v`R(q4M2C9$VBseLv)fpz*8=Ig^pj|6xC6@
zutJm^fU#7HN?qV#mFW5s7^)V<(OSArl#vg3y=W@pDcpYzqIoU=Hi}wlgMCZ1ii**i
zM4ALR(<~~<hG>f@m|nQ8qVP44Y!mgR!;5xNp&GmnQT+zsIz>OxE4EA25eA>SMXT4K
zvq$t6on5*uS~CICEBe;}op(e>C(*hq`W*ik#WwSv=m15t`$Ve(;dj4CKyQ};k(G{M
z42o9J66(Gv{x!HiB#NW8!~;=R7KSz~(ol$GL{vig*HKaWY?vPtby9`VLs44;=J1iI
z!W)2bQR6c3CPax8`=1nTpn%C^QB@IewkIOykI*(H(o!|Dz4&J?m=5AMC}HF%_M$C_
zllbX&@D7SQKZmwM;%#*1-C6uCWf>2Pk1hqkMQr>Oc3s8$=zDT*;=1XWpd;c}=p}Ph
z9Pl=j9TVqJ;eoq2ND16=vGXl-df3EzditCYa~KdkDQ2gFc#17_L3oKTQ3brWn4tvm
z5wE1<z`kNO<)r+?!P}tblz0sVyZps-Y2_CnK1T7HK=I6*&~jS*9(}jsjCeoQYMm9|
zr<HY(_y<}~1&c#_&<YXTKBM$;sJMkn(8I)xy+DMEmu-gm2yqKV_9Mkb$1#{_@fix8
zoflWoiLn^59leY%h`TB16e~6<Vg91n^=*(iv2hM`#)}8(hEEW`!39YaKNSjGl6e10
z%+n=t;53kA@raFHKq=y56l_Qp2X2EGY2y4Jp*vm7-U~IC#p~%3$PjPY4}7M0S{6)X
ziM13)%oZEp1GysprU@o;#NTFv<cbf{+U2VF*H>U7Pdw{;=*$=YUJhP?_(U!Y6^diu
z1-T}k!=SL~b@3_+Cl-mP>)=eW_?x$2utYq<#w3)Ao6BILO#B@!p>Bv%+~8BWID9#@
z-4q|7qw^JFSGw;j#qD9RR3+ZSg3fAj%C``y5xddLxK_NCu97<OhTD*=7st~g;Ffs4
zlHxB-;uI?8XckXV(MpS06As^6#S<@~vrYWJ5xCYa9vFc$9pYDt;9;kD5v}#Q#2aZh
z*)2Xsi>)4U@0YN2Tl~-!j`oVXsYddS_%7`a?uu940=Xyt&K0;maeXV4^^5Oar2B6`
z?DjDbgJP!-;qZNN%Op$;iAUE$+XL}ylw%zh|4fCoBVzSZ@J7Y!DHb~>cDV$*55?(q
zXgw0Adw@4CZrp*+3Gpv?&^al7yBr=q7FSXA#uM=mqp&+Ae(nV9*-L6}gV-D-<+L7j
zlmyUj(n+#oCHy`pd746vha{Qwl5v(CppC_0iI83-E|T6VXmgdk`w{?dlF$Bv(jyWD
z{V?v5rzwtjT=L~Ec;O*gcoFaul3DHOJSlmHst!FRPsO0qOS1kBro`JOnfoGuJ`(j-
z==POt+Y8-(l2N)!Pe~>!VZvYXGYvFA;<p>EK*=N8OP`h`Y{7VgB+YadB3QEOW0(k$
zY-B+)RC0|9*uo^=QLG|d^4?kKjF5EM!$PFQb_C>{WLhYcMM-Rhw3&^T$mkfrdC7A>
zLo`Nmg|e|1B=+8riIwEd#ON<d=5B+wIEf<%y5l9Eegu&OiDEHuiITMw@F_|18(njk
zBv}WbGg-n5$H?%J?dj-Dl{}pXWoeS;cC^wZd9A=*mf(x>(3T-tL9vcZNhbp)vLtO4
zkja+(djjN&Wc@D?$&s|ub(Jew6Aa*0$q8Cs<w<5e#_01UeiQJpK(dA^3kxNi2hqAF
zxikfGUDCV<I*TMF8~}<Xr)WD>BFSXHwNi;w1>OE-60eux@D0hzNtn1PS#=F2DkRxY
zfmBLPOTnv>EdBz(YKh~^5UG)5sWIMKNjRlq>Li(A&{i)|P^6|oGM^^6QQ|>auv?P7
z6!>hCY$05;<S9y_w@B{LmC!1wQc-P0ha`ovv7M6r=ONl9IkON-yCvHX0^cLa_Jz{h
zk^(Ai?UnH8DRM_*qs#KH<STEuc283O8HU{_d7g@c`XyTgXbng{KMIjS$@L{rc3%?N
z3N1qtZ@Lg4NWPm5EyI!w)|_dQnIn?)w*efLymk(VG06zkAv~0Lj)Ods)U5(<ToOak
zjR}dx3~iGVr5ng&$+S{fdLm(ZKAK!?n{f`Kc9MEfIp;y?6<P=#l4@TA+FANnB6x?T
zhnGW%i}XV}X5=cJN4ZTmY2h1?JR%MJ9J-E5f2MHJG3kmDh`3AV!~uR>`Uz!}J*2@4
z0XQLD_Bwbcr5Da)D4x=bp&(w;FKyYN-qKC9_V<zga~Z?+m4<|441QACPMAL>&82I_
zUz$t%m;h<(YLGx_FufH{OSyD{>WuUkDib^_ouFu9kaQmf$%Cct6u=9SN~<6lD$S>C
zMVNFtl{bb<=hB&&2x+o{p5u|ytW!{PPFnZ{5K+>b^!ALFUSPxh^U|+qdmbarKLw>1
zq<QpMjg_8FLhGV5G8iOIdN>}s<E4{nu#_OxMFXBF&7vG<l5`H;*_Widr=yiD9jBOa
zid38pk}7q(P0#T(X<7>q>CzXPVd=6|KxvK)>2|6>&Xk^@?>S^iBYl9+mcC6P{wvZ7
zM@Z&KH|~M=xzcNNRpv|YxWkzO=?nDr^+M^|e*w5Ab=3oKT^iy8UXgV3P4J4PVUFOH
zNIz+uhUa*x)O;GuGHF#lEZvZ<--i*FO9N=bc2l~?8I~%fw{Cz`O22i0WR<k45%_B9
z_!R(Zq{0U<Un|wc0#GM?)DO4orN3D)&kfSPhu}3z6Fvg`mh{mB@S3E~b|B5tGFm3v
zTBI{`0c@3Ski*k9DSIB2wo4Dv#;HU4>!(oDDeW1A-7cyB8BB1u)bSlC?UBx*E8({E
z+b0m|mAZIB<c{>iN+`W6{gQ%Z_oRdW-C@#wE)eOLj#35ufb=j$zy_s`FF@ISn{;j%
z=#caqdYe3umc_%FVd<u)plw8Y?mM(br6E*=G$!3g+pveyV^qWONV@q6{2iB83_{z4
zG?1d>lTynu`1DwMl5Y1W(rvFo=alpz7dU%a?ri9Eko`g*lXR3Z`rwn3%=QI+D(|4|
z8wWHG$@Z-S&{?*EHou2u%D*uQF0$kFes`5sP~z83Ca2G19g(@xO5~_)(R{#<$;N0~
z;Vv7XvoXhIr`Ds>LnitGc2CHRlqo(b`+zn~p0dJ8NP5X87J}y^``Su(hp(*QfAHH+
zW=BcKQ?k`-q1#`UdKn}@mi#t417)-5+e4>iU(*rTGqOZ_qo0*UQaMbJEFcoCU|Gf+
zAR#iI@8;>#@qbZiVI3iR>mOK(l)2E#^qlN@Ii@R0_ND~mjF$cQ26*RXCfahu$hPM|
z<bsT!k5;TqFa(i{vR*0_ij&y|z?XR0L3-RI$kw-lmnbV{z?UT1S_-9Jl0|%vR<f+*
zGI%Mnr)=~9PnAvn3TB$@yCndo%eGUo*JYWbJw!8P>&Zl>Oh;R+EZOW85XqL6xTAGN
zc8o@rBYSZ*wB*YCsj&B|Oh9KZ@?>4J;9<V(0}AC7$YxO7y-+r92>{n*KL0?ZNY>V8
zgNb69J>4-SvS7+dm&(-DK$OYer|rxQ*^+b^ESG)XjvwZx%qtVE3faviXjRHi(l1dZ
z)6fo}TBePLqcyTVy4GrCSD4_{$re0;mU`J*DywXeeftJTqbzqf0Jmh_{`Ae=CfSP`
z0Gnkq-omh3WDOK6Yn3ga$6T8%nktLhWsMZh>yVApHnmgs!u#NL$&|Dm>6Y11`mINn
zO*N0VWg#_C)+-yMGN(JTaSEB;mH8fmmV2^YH$eJi+bG7}FI$Y?6)Qy9u213cpzOXo
zhIU`J;RDRYkSvle?gz5q0{Ap6`*J-HBeMJq3}#fu4Taq?+0#>yd?-_{0`HORZ_4D4
z%RFgaJ|SE4H##R}^_$_vV_EAiNIsEyW<z93rmu%j_Hqrqn`{p9=<T2f<=u3^^^knZ
z4+fp(hkgY)ESJ-5=pwIv8!cD)ZrUKa$@602?-BXN1dyZhHb00QlW!8E<u0E^@v!6a
zS+s-pkT1Cbazd{4g~&<yn@7;{l>bBvHZOVl960JdL;kPtA5Y^x*y{oFr{pVdpx0l%
zcM%K*$Y;~%<pSk9X-Rup{>5hS&d7hK<;+>R-ynEF@`e(SVELOdAR+RJ-OwE>|M4A+
zK1^Onfz@#NN($vf$UCX%Fj8)K7w~iPtyIn#B@Y*YM9WibOF_@e!;ivJtUPil)LfK*
zwi1XqdGcH6jF*2(N)zPsXqBHRcc(aMl6+7Ow=c=x-vfBE+#wbuMZPcqCQ{|f5crfP
zpZ6Nz>2k&Iz+IMSeF~BxpH5SmDSs;pTC(Iz9^25HEnnx15nhphw+OvC@@MJB%auD)
z)$UdK$_o(5lgB4uF7xI8Mq!={<X_Ovu28;%$|$bM#SUm)mutQTu1MZm1wgU<J-Vk$
z<mD8SDU~zm@+gys(#z$B+}<8q%H=C}QKsyseCbgPrb3<+0{1KBXCi^9lJBF(T(vy#
zeW<CCOWy~tR{qyM;Opeu=>1bK-&2U0X^`(g#%pGyyrLC$Z^@4}L!?PQat<b%<?}tD
ztVQ1M3_z>=7^Q66<onVf(k`zxO`pb{*&$y+o4HQ;O{&oAk~jE(d0XC^4AEYBn-TMM
zNB)>5_^#YS-}SmDcl!;bPrk%AW7hO#wx%1vJ&@O}fcas0FI72?$e+Cj^P}>gC@?!F
zpG$Qj59MM1K<6X*_j4gKE?+qaG9j1J(b-A4#sgX&%e^O|<%zu86K1F6YZ!prD-M@I
z#6fXoHs;V#VNcWSr1)wsCgz|b-WCSnA;n>ub!Wv6sx&>U$fXl*E{clXK)5ObW&!V}
zm_-LXjwqh<LhGnvI>ob&DHwEU)m^cK7QM$6@6hVVPtoEHyQdT$Pl5O=a({wkfWn_P
ze}Rf)KftxqiZDvHoKbxI0o6L3RY>Sj7NjWo5v^dwPAb$3QS9@8`B24oloAY6C_8`%
zS9H=EEkY6dJ$R9ds*4!KImK%a!HZHH9!F=iqNfJVoLBhTgTyG_`VD{!3N=MrV-=sz
zgNGLtf-gbh6iff6Zv(_D=KYLjf?@|B_(X+@)(1(7mS54jq}WgOXvvD06%a{LZ2T7_
zRndJBB58`%A7C))ihmBn#AU@w517bM^wTRfQ&I8_%x5VkD8`npxN#JnR}_+`F~A%}
zF)gR^6x(nd!8S8rvGx>t3lt}4fn2Bv{}oEFDI$IY{<@-bKX^roF*-t6tk}F6yb?tu
zEg#Di)l_<LL(xg0oN~o(I?8%evG6)bg+h=76P1d(F|?`_%O7Ga)r#qh;dYJU7R5<w
z726pY%WHLtW_mZ)E3CAlZ&2Kh#<kw4c;fr#96a9|C@<QsIGzJUhvLz9FyE<IFakiA
zqJdKC-3oszJnT_)M8n{1MFK^adlj!)Fl%=d8>o2Yu7Vc>-aSPH4XID@MIc1_6&t8d
zWk4}p51oUGFaw;qulV&2M1~Y!&?Wmo5oTM2=CI;dIy5t)Saua;RB?u?Ud9wFr@_&O
zir47Id8BxY7D?lZZCwCNC~jYc(n-bV6sUNtsCo~&pD6z3VV<TG;S^hQP#S14=%`c#
zLDEU-M3FjY<?;~l4lB*qFfteA-9vPBx+)`vA?l_)Wr3w5%9;;B+?8{vNbb0D@mz>_
zC=Y!P5l`ixl<oIYGOt6#Tj?)G%SU;Xel%a@uho$BQ%=2t89k+B(+L`Xr3+n80m>IP
z!tFriK8od^Ru(@C_!;Hr<+Ou1tE?44caU<|Ng#riJGMeih%#jaqM^!btAP(wzS9j7
zu3S=v5k@FyoCYsad5B)Z=al;-&=#c}`V+ip<r2zCpI6@gFU708{0Ed>Q0}Hum{{ff
zb8zjVa>eU#CQf;J&CF?=X2vVe(Y=|VZ0?7NL}ln!w33w9wxD%M`Tbq!PF6l7r76n!
zrEoM=xs_r+Y0BL?Oi;R#Ls9h0%4Zs(G(#z!4cD@jj}*XNQU2uH`W!AY;m1&xr|gY`
z7x~JEY0y%j+#Lef3Y8n`L9Qv&u0Z6v@+_^Dij*s8?NF@Dr_fx9@^lkOsq!EP@G|A~
zR2aIU9DN^va%J7yuzpiHUj?%j%Dx|<x>C6+6FRGuHM9b+Rz})_0jyCTIfG`sGKMM>
z8<a6?A=9WlNo$r{N;Pdho0Q+v6RlY}M0H**%0m?}(W=}z1CnjZL3##tDw`;<(xrUQ
z9(KEx?Z+T8p!8S<)q~2fDR^;TiR~pWYUO*BDjiYIoNI&3sB*<;V2&xb)WOn2<@Xf%
zeWW}xAFWB{KB{4VtaP0V@<e%rqUa8)f9W`ZqpI&EsBuzFQuObjDrE%ZkZNcPlsT)$
z$wLoS>{4hsq1v8}`{tx-@hX`2RC&?aATL!*=Chk|t*R0!{p_RqhDu6&RnsX(;HP?n
zX7-e7Hhsy*Uv-Yc-vO$Hl)DI2&7c^_Y1OV4be>T?_YVvPskYFC5Ul#|ll&p7Xv(;T
zs=|D4zJOo(120HMsm3z#`$Ve_alkvT`n(&i#i&AQW-h3*sfaLEl}c5I7ge*1Arhxb
zx&%PHYOe(F1l3>=c!{dt=A)IQTKGOhE~y+S+?T9MrEo`zs<sVIq^f4n{_wJDN(jj;
z)k<46n%Sy7Ux8dvO`F23<)}WTuQcSUynCSZsw!?LMxCcpX~4@@)vkfk0@WvDz!$1!
zP+8_R)ddeYdR=9p?0k{Rn--|WD#>54TcXl$0H9PQIRue1)t9uJxuN>@OTf!jT9XaU
zo2so<U{<JHDJ@y8`ZpA$Np*>q$<3<ivoZP>)h5dIx2iJsV`y!vi&VbUuJZ0ct5Y@W
zJMg+x%jjfax9Spk*rWQ1j@sW=`M(F!t8$}5Vs}*M=(AdPRaFN8=u;iuLXVPumDLRn
z52#{j%|58wND+?vst=Q3en_>Aa?uY|H%p*&SmjPv<%sIT<7kbl?$d$dF;&Fxn3+ea
zr|2~4xaz<#v`na8{Rg~B)r=S6;bT=i69asrD%cOzQ>yty?A1?U-DR8UpgwyAOh<L6
z9(X5p!X5w*s_hS;^N{*fFT8M8r{96n!|J_%!F?C?J9JsOs(1TC(oH@4SrB*i%T!J3
zq25X7eom-!XJdpX)oMEA;;C+<Et!`(iK4;Y>UmW1?5Ez{gt6F8se36F;;(LIL3e=K
zc?Fn(>UkLeo>u1xLC&ZR74YJ$I<^+Sc96P`K9m-suA<OssQO7CM8ed61VUT5dhZv2
zN2vW*z<i`y_84xTQ_rW>a+Lbd2xy5`Z`=(n=hd>e0En@vyQf3V1@&sG_`j%TxuZ8u
z9p{c#y!xyaY7*40bVesp{R|!JyrkYwk)UKXiz2Tn>ecDcma0CR29Y%Ny=dUl)m>d^
zT~<es!Av!eGCf&p?k&t(wtAiztt;wxK7ngFYFm&Ue9KkOrPcOTwF@66uBjv5!CYKd
zm(y{>BJ~-%wTsnJ6pScQpPm6;nfhaj6x>ixw1HQyzE=xgrTQul@GA9%Y?!E4=hC^K
z8g=}345?O~OUFU$)!r0|Y*0_9!@iB`pKW$f)2x2#EihZu6($U(RegCH5N+xKim|n;
z&*cEop>A6YM5j7_7bLsYE`E^gQGY)d25+l>s{yZ9Eop%lchn8E62Ge+$pE>hE*-@n
z`qX=VhoOG;LP`|fS65OtbV%J_LR<C+>R<)b46DmNhwc&ef-W#e)xNZGd8lro^wT5t
zuT)hquI^n9kqLFI7@d=9zi**?N<A+RlJ=VN*FhXKnG~OK)a(+%dne5h70?~jobrNs
zXU*^eh#b~D7Xad-d3unNs;-)B3Ou-J5+fmcOmm#3#$EF}Ra+j{%$C4I4~;YfA}2JV
z>p)Iw%6fqJ)a;~`mY2q(3L?Im1u^LK(-cv><CNw){r3KvB-)b&Xjt>nd0Lb10l*o}
za$2{Y)%@yD|0X9`)B7UE8=~1z3A>@1`)-*0FwGxd!+f~rWG&Q0X#QCW-Z@PM9qNhF
zY<U_6qcww{q4T_ElNUr{G+k?fyP)}|8wM|G_{(81PP2!U#cTAmD^Jk8o{s@0YD%x7
zm8^Mx8z$YBqNy`OO{!-7N=$H?<|&d%*W6hR{AEo(+0D?norQ;)nlqGK$<ho&!ToFv
zn__!cG|gjhCP(uu1(0(!IY;5)Rn154(4D7Ql?Y4unvhSyE6^OZ!a||u237T3*IX@t
z+ePa&>J>0pthx9BJT1}8r@e2f#&8TWWty}Q@NQ_r+<-6FET;mko0>N$G*Y2Sy#Vu-
znq?F_t<og_06?|o6Iy21Xl}OoUVLf#B3s<MKs0Lp;ltD|&F*y|O`51S_|~GSq-R5`
z=B=w3Xq)E1Lh#x(|D$|Hhh{guhdMPQ6&Prj=KdGpb!+y}&c8?V;b(x~*6bXE>R!!k
z3d!8jBwOI&T}|Ry0Pbn__hJxz8nLYez5SYmc_0ItTeR~Z)O_&;)C_4BbOQK5Q%UcW
zVa<y=@WwP1v{ibjdAktgktX2+$hhX|4=~;d%?5fBPippj1GgV*+$qrbMAJwi<0(x$
zJvQvM+24ZapuKH@c}H!{e-%Sc+B4+ELG1;qr#qy*GY4v%wNq4_a9G<y*Q|^7&7<JC
zYX95}_uaIcM=%LTw6D-w_NX??jMg!2W+rg%S`Ou+k8A5_<Kv-?`2b@%p=DCU`=oX|
zt=v4d0zF*w($0>ec$l}=wFgZf?Ti{|^VR-DKeL~<Iu6=SX+6Wy^4AWQ10SH>bR7c?
z)Xvhti__Zm)1mu}wsJp2&T1F;0T86^egG1x?GV8GFs+Ruh2dHj#VaGU9E#{fYLniE
zmUCKNI=$SYwBOSu5Uri074CWMfflqbXq)Ki6{{^c2Xaxno^}a|TA>&0CTT0S!I?|i
zg|zif*18VEixh3iN*GMl&MN^gO}l`iP3hX015kEZyD9|+Gqlgp<&mlNVnbP$)<9?f
zZP{AeE-<fXj|G64qb;JRNUpYpb|6=^S${$_PwVvoNWL~QA0`U4iwRJu-981tHEl>S
zJiM+=I090nT}Ef7i?uJ(6<DI(nFNti?dCE7%CxnyaP5ZnZF=#QYyUA~)^6Igrg0!D
zw2@z-S*cYG!>KCms!I4>t>scUp+@`A0i;&@3~l7=v<IoQuwJ`^0c{Q1cj<$ljoNwJ
zfxD$`Fk;wE+CI9Ro3*$@aT{rW@`D$xTHm$cwQ0?iYi!qgP%UtW*7njQ2HL3|q617_
z+Ice})2;P?7Qi0uz~|_^t!+p}t5^H>2{?L3dx|1LceSlcA$d<5K&y^EZHgDh)UPd|
z_rZX+=XDqy)VB4Zbzd8b8nT%~+EH4qJkZXgSJklgPAB{w(VntV74fLnrwbz-)4ul+
z432B}=b<&Bt)W%Gq}Go%WskL+d|={<w&XP^ozhml2Br48!Ncfu&?U4%siSVkYw*xX
zx02qi2X*80WICh^8vxu{x9<nIeOPzg0g^7drIZhJ)qS2~L$8}|!33H|bpBO99M$cR
zK=(0SWH*SrZZ%zO$8{}VLc~MYdIKJw(9PQmyC-#9=`ro8JM;$(dg<N?#R$E1oBk{1
z((R)ciLb7WEcodnp2Cn$>F&}S%U_qd5R#{L|0pSn5~M3+qBmIQ_zVn&=zL<JJ5(1(
z50fyRgzA>UbyE~6iO}6I1Ta!}l>*@BboYB<B1$)#61~y7u<g)tUKb{TzcIRDx_vL`
zBF}>ttE-&}M=$D*905E|H*_5q;&q|p({TSK=tOpqNz_fzPBBS$kTR~9ba52uOx8Vk
z7M&?N4PD)-x<hv8Ow%oFfZcT6fz9yuvaXa3K!&cr9zJF2hA5+*rCUb<`)r+EF*>j4
z_R#5y9Nn?`=*-nIJfY>PuBZ?^Tb^z%AHDgyaH<R`&<)a4zEJnf3OIaCmqW*Auj^V?
z0bisW?1dM_x-{DVmFS$QqPbM(;|D;QPEVVi8#+e;NV%@h1lMlrJl6wWp-b5TK&7sq
zHi}ic`xKw8*4?9<qsFF-r<HxJj!6eX>vUB!z^vEp4FtYH_ui-Qv{9%27Q9wn{1hy;
z>!u|^X@~Bj6L_7v2D*>Bbar%vp<B0dI!yHF3TOd%Tjwpq$a-}t<KW%VwF@9QsPn%7
zEkn9Zbm2eH*|-$e9@bS;!fQ+?b;Xz->ar+?`$)Hn4waAVdN;%Tgl?xjL?(4H{b)Vb
zZSe;0iLP-y$dpb%&un{rJxz&&{!ay3j{482p4&;^L92#?`m7EN>5$$l5ned!?aM(9
z>tD9*gHjiL746Sm^;>9T;ih+f4?{bm4>$?kNA(INoH?d{pFZs5uD?oEC&%?SpMh=<
zeLcPJPw3Cw0y(LFhb{<D{d&sSdg-^8q0?LcJZ*h^^dCNh@%rlZBEbFh&(Y!eQ~G1=
zHc)@PiiQ@TZ}|dF1?tbmz~E_p<6|Js=nqxH(pi1;Ab>&oPfSo6tasc65~9EN6FNin
zU-rXbnEq)MTH*Q`QJB#P{aGsRiPX=23Z3Wlzwn_tN+0nN#u=@DeiO)feeO$i|HbIH
z(1C~xdi|SlCRYCq-P;%S^Vh<sIQ`pRz{l(V_aQnH^l#EyFHxUDrBO-xw=aNqNq=rN
zc*%Ne3V12{ILgYV>Yp{ji!}XsI$G)a{hKfem-T}brp?k<2|%*-={sq0c|||Yf|?xt
z1Otd%eW^1>e^r0^2xRi~uC!my*XL}7NP)h`9-}DKuZxDrHT~LG(0N_&G76C*{Zcx)
zQLKMKhoP0|N2o-;RG*##^JV(%SK;psJ$o_W<@$%zx~ZS>EbQ4T^h^GLZ<YG^Q)pJ{
z-*_E}YP}PcR@La=&VZU)eRL&Ao&Js%2J7{A4};gBFY|+%M*Y`UVg8oBsudzl`mcTj
zuUS9Mh`DIdCtiU_t3FBvkv9F0_29MZBPn^&p|7|Ed!07@E_!wJ=>Pf*zTMV8CiA^|
zhq++h(J!N@?_K>{REB#`Uq+wl>(fV4d0M}|mnL{XZ=Z{~7}P&QX`%c2O@E;^q<6DG
z@`1j9%2bB+8C0t}qMx9U#i-u78xu69cL|4<hkE3JAo@sulRO>Qw^Af|LT~v1qLcc-
z3sCx4{}OHBp6K_|hGt41Oo?NAL*WF}I2c;apwrQixey{wh9dgP$3er-&qLWE0}qdw
zna&2M{qW+j;RSnix)>yJAg+eyZ(+#I@WxL*KpZiQF2}Hs8jjmT%`wA$syT2s*u8_+
zaYOiB81yh`55m$3L)c#6Pa6KDdJ|7W!hPuWGB^(5hw(P}(;*xm!=4dH`WXUG0)EQS
zzX~G$hOd2Je{1?;+u^Sua@L@Z1TV;tO8L}a1G^ZVAqGAL^Fs{}&Z9HTkWWFcaKoRJ
z9EvdXd;t<^m=Ou<=L}1w5Q#E;c^X<`44hA3;ez3B9}G9v@LK>pyJ+}g9z@~{$yBNu
zZ#Z@tE+rVg|L<QxBpP_$kV!IJrKfC)A;AN{RKpAYn2Iz*S_wom4AUuFnQ7RV3D>d=
z>N((L8-nJbb;ZD^Xk?Dz1DdT|!#RqmUNv;4f|qAVp8;IHVK#*-3Jk*UKne|O-7uDG
zhOQ|aoVsq9zZ9ZHhI5qcEH-@G3sPcurW$rj4a;dMUuO6^5v?1BZEGM|ZWw<GN^csH
z=`C7eC^G_3X?UK3uT=*70ko<O=jryVF~m^%s@Bj#QOG(&_b*UZZ*ctqtp>yFAS%#r
zG;DhZqPGmgzreR9!;K3d&4vQnkhB=`XvfxSFj4hjo8fOhNV~!HAe43(W`BlR>ok15
z6{O4X^X~w38+hLW-ecJP7@fBb%~a0TYq&~psyl|ErRcnC`0WO?+%x?4Jw0yv4D%x4
zRKH;kMGyuIKhO?!&``k#xo=3OXUUKu{9_FJfkF2MB!>;N9WWOo20gthMhyj&0U9%~
zH^S~i!wMa6j|`hA@;7dHW&=hxVffGp-lX9JKD0bG#8F1@iNT#>skSLYs~Fzc8|~Ym
z&B<6qA51xDte|RvL&i0flXf=#sfOrb<9sGsF2>`n@WRztK<O1X<AP*N_YvdEv<y6I
z^rOQ~$BcdNz$bTO^?kIC8`o3GsE6^>d(d*i80iGblg49|8}_srqXMDS%P4ylYP^k`
zDLCn4w4*b0zQz)I>i8LXlrB7FT;qn8zwtAQ=>!;u_n|Y;SnxD(r;W=mK+759r*s#d
zH69W|B*@rL`Osiv=Vpk67=NcCpHSm#Kf!#M@xvJK!i~1QT~HcfR8uA<()d0tTFx0S
zKLjGmSVHB(F~(^gKwK~?HeqICjaG`_T{J#V>%TZ-2pxfqH}d9Tgb7BK7g~u%RW4dd
z#-;y*!DQp;-{?#+{{0tROEvm_23(pkpXyK3jepqcU?Rh4_ZWyw<K9a^WErhjVLsbf
zWdZMs@hs(?bBvJ`S;{m1@dZTkjb9`|X@PMl3Tg_C)h=jVGe%Pp)^+3Bw?K-Fzf)+Z
z*cd};)e_^=n=!Id<8*Jp%ZzK5z}^kxm#Zk2RBl`y1T{B}&y2%Fg>hdy@Ri0rr9e~}
zT`6l{ZJb6=ts3LcFT=H3<4npg))`Z%8n)iZp!HOPQS=@}8jVLkg^63njhCRT$rvpL
zui5Cn5}hr^yfNr(H4c0a*V>FfG3Vg^>oCG!+(*Vm`$2k)>rX@XZDTE+rpG(w3h;M~
z1GGcEYy8U{YVH~5S%L2}`Y%MQ-<XF2v6%zLlqrxwV<hcU?;9_B!0jPpRs)oc7(Yq@
zZ`3$S2Lr~8JL$fCX#9CGB`qHr|D~ag8xQ=BUuME+(_=0sjl5R@d~E#SBLJTm1;1l3
zQ^r>)m11vtss+T+BzPVkI+=1Qmv_+g%_u|;nb_L_a5nYOk(R@zUH={JGUW;3=n2z<
zMu?m=^-{&Rr|GHluxIl!1*XEhx5@8CDD^WXQ$qEWsh|^hf79r1&>dh}`T)E@laB_H
zr%l%<(K=&Vb`eU?nquf|Rgh^Fr3-^iZ&9Eo#5B}_R;a1qDzt=|t_4D8xamR<IwMRc
zDccff>Y=QAyv@|`2y>Ze@@>Lkl1y*?32m25M=5KcY;t@RmQqZnnINgA!e!8%X7YLg
zO4Ch`x-p8&rWiVHmtk7C3nH1O=dS>sWy)bdB-`{OMeweelBh5&$27YR=5tLQ|79pl
z`)PNPXR;O3VTXK^9W6QvOs>B{O`&N{HGH~ex=pK%>n0H;LyAlb4gp_mQU-%pVrtkA
zyQQY?`OsZvQc#lihAHL|I?GK?ls36(N+U-rOeZEGQfUgIhi;YWr9AMeP5)9JtH$)3
zjl8Kfy*wApI#W7rYwAskNwgYFmj@u)XmX+ra<j>i)^RPSzH)T7n!+|gq|Nk+FD9|w
z6z2xlI!y1r0McnPq@uISbYMTc?>3F^MQ4xc0^Mo1O#<3U_nMB=bLNi8@4tU-eb<!M
zf!=$j<5ck2XDX4wV85w60tN?6J0HN(py{hpwC<aZF2F#COw9{$bv`ip+t4{|s;dKh
z#Pm)CaHFO#X<t8P3j71ShbGYyc=5;-_ACJ7rWK_a?u6-8+AK_(9GofK^w?BOUr2gl
zlG1Kr%CtudpuO3J&fGefue+k<Xcq4R-pMTg3&4ZsJAa|`ka?B~BF^S*0(f}XJnn@~
zH}k?$4C08ny#-zzHQ)IXxMSuwgMf24FQcO4<K`KELd3&dcZLe|Pnf4DV0zMgavBhx
z=8Ug^@G>uWAD!OjSgJbnF}Lo*(0t8fl>GNIPf$U^DYKUugYh?eC80CGyz_OCKyx(x
z_NUD%Dl|D`E?EJ|v*y3U&>3W2{a@bM?6C)4gqZ!7!Czab`NbFj!_55@iwZYSuf~`n
z%ya3BB$4JNR!sLfGlv$sQRY1q3yL<+`xYYS&G>{0-VWx~6i>fkemNMDv1W&baP*=%
zGzhxm%o}rIKHkiud{lyY3l;k$nuBS9kYo-@0=Z-}@222ave`&as1)<!H=#S#oYjiX
zH1ihPAEcYR?g4+<yo*W!GR$|k!nI8E<m(X0GOspZ*0Rk`6x6(8&M?859P@lN0J-M%
zbXwr5SwsunJoCW6;N_dE#{n-efBZQ}q1kqQF2;1teAIyEb+h*wh!&Z*ghN}gd6>@1
zmzcBCF|<<iYFajzn>SO;t<wC=-!M^SUPZ+>)#hAUC)AkleFlTI<{LrKS!ebhfx&w7
zyWc}ggZbTVv>MGVzreyRvoGzBo6J!*I;PNUexANL(PH+Yhe@k>Ru?R_nLphNHSOk@
z!w~H-U(-Rd)4ZSJ0bS;Vub{2lJVu9&dd#~P!He5wkL@tuYrgh10C&tS6ezuGUiJi%
z_skbhz{5WC{xE3iH>Y2M7X#*$19Sron(OJqG55`3&qHR&oJ2=N9+-co$Ih^M>rLQC
z%sp4o8a2-fLTk)C{T6gTG>22{`H^`Conad{|N0opCd_LxAu?&+_8d$+Hvd7vqbKI(
z8UUuu?z9)Rx7_Q8q=V(l{|c)eE#X>>>5%11Dr<7K48I0)*b-02&Ri@JW#GA5P6mLu
zS;koCJZ5=q48+~Cmtu^^Ef4R2chd4PUGkomkLIG~Wm&!fGwN-5BNEDdEb?*id@aSX
z;Q3o#rR8scMevwDUKnWkkscqXEl;ll^NeLR6&RegeDN}L2U#vhKs4AgP6rY~EYs+L
z9%{Mq9<+s7wtR%4g<F3503s2Vm)Q`Bv~0{m>zsu_!Tl)9VL2qDEwyqC`@E&(CUnMF
zmM+5RFId{U0k_3k#_8F8(eiCBbjMj(O=!hiD(FCMg2jCgNTS6l3cw`GS5yjm$+B$;
ze&%G$G5QTtEU(aOG}ZDoO+uO_$PAHm%d~w^cG+@@qT?Bs6|`K>v?Rx3oLLsbi|EX@
z<hBEF#b)uKZ_edd(!4=(Eek{-S1rrvVUlMlrbk-7#pxtE3oP!1aIMg?sTZBsEKYA=
zXxA+)dY=?o1}Q^XY-y%vXNje10Om_AH!cBCW;sK*!wt*kBDBgaW6dBpEexvNsj%3t
zg@9RUIq?fjR9RNiqNm#8k%XbuSPuE4v(}Px8zOa<(Q5GOEjKA#++f+!2z;ZZ{RRx)
zvK*)TzR7a=U%1_BaiglUHp?hw1KKT>p8(fkd4UQrIxUA!;8y9f>@Ekq+w!7q7AB*|
z;!nTDZA(1q?zK3SLd_k^PgEm(*D^pWntPT_i=eH~!rBgP{g%mKXdAG+PLb?E%QdP+
zyKm9T;mnX_@nw()mVm`jJ#6{-zt72AW>ZDNsO1!;;l?aw^j3Ok`6-6>e~&C)$3Vs{
zJ1E3CVF~R6aMEIKfaqh(pLDT4u`G86Z_2XiF@W~g=9%!x!5Z@n{B^WyDP`tlU4I^~
z9kec^*TNy|y4&!=+4>IclMh>uHbI$-b#XKdxmvwe0^nxtkEe&p5$iGE(;s3ho<~`2
z59`XCFmb{fcN(pe)<0i^QcvqL3P*TZnH1*owk{k;r;qhe4kUf8YATuav&uKY?kVd%
zXV~?({*N980an=)00ONK=v?e+tHWCu#2IUTJ6dP0vzf3SWIdIH&S0zF77A@4)_VGe
zQK+>t4>A$fO%$?-w7xKj**j;QPe1H=t0V%v80(9a<-K5yrN>>I^$ESi<E<<T4<uMW
zq;PMdwSNlAlB@~z@VaFE>>8X&wRYXbB&1pYF`|`j{qi}8T(&MQrMP&8^=V4NWLjHj
zt(Rq8OG&+KYs-ISu~sHMN^`6~N?|G2dXWl_uUhv}k!+sT=>SN+H4=N;nFZE!P2d$;
z4^k-inl*}wRj*rXd!V|=8hsh?V(U`6SW2uGC3vM)?IQX&>1EdU>D7M28Yu>|+`6S7
zqrYhlqljaLb=E96Q)zv$4I)+659n)$)z+UVN>*c?PGOr`YY80_ud^<vb3XOfPd)*l
z!TN3`c#YOBa`cvUPZn@Z)=<h7H(R;Cg0xuw!4+hi*=nr~1+&AtAsFs=S{d{j?6SVH
z6iU0T(Q1$$>!c6dzioY$HbTAD(9h9%$NDYBJ?~n7>4Bs7tZ&l;s?XZu1k!I^J%M2l
zSjW`>3|im54%hBmXL-TykhO+RxjwK?6GPHAY)zt^#)vh*6U<R-J3U{=tXaFD^r5wT
zBk+%``@A7KZrvCG-h}nQR_LCz>V}}^v9(wS-A}BWskq8v-Q_k&I<8wxWe!g3HlYS?
zrt><tc1*(Ib$2<?>9X$cvjDiRTk|ngyV=$ioCovBy7FO|Kf3N0TEiS$XQ2Wt_jTR0
z**U&$#t=F^{?E~M$8}kK|F4#rS+*?8GPBZ3D=k}^t6Xg}`|#O&@7=Z!h_VD_$wmP|
z1RS7<3_*q<Lz#lemZgA#ECEsYz0dEj^E&sQ^FHT3&-1y@z2}_!d>HNYs`6tf=E1H%
zqmXJv0vK*|z#))v{%u$~#7L`xWDsM!3mStNDHf0r#$hV03}x(PfP^usI$<x8p`uji
zVTR+r7eJ3NSX6Zs#dw*vW6_LCieJVs*iU1iM;WfP@rz}oQq^@FV+BQOjxkogg%QRx
z{<{Wejx*+F0wsZAS%Jnx#%u3FJ&CcBj@_JKe0&5VCm92@ay!MCdkUDR8F;Ai`(d~_
zzJiM>j9d!ioMEu20Oc&Bm=@}(jFZlgImei$w`m#!pPa;-hjDQfBI%4xQE1Fy=+scp
zWXz*mn8hfk?A8TF(POZi&5#5^B!`hz4}UK*!e|eW%XpEV<2=TY4;u3sDQ>hBDPTCu
z0CS0va}NV8WK_@|uZXdH8!TOBxMYJXW`t3yyM)o&4D3?IA3vh+DkFsAw3UpnE&{ZQ
z@fIEDs%BKuWM9JwlS1zr<KHc?P|IjGp|Otf8WnL~XNVV|v7W)XMgQh<gW<FVolT6*
zv|MRsJpC@bXkmOx>C#rlj)iD!V}w0~`J0SzDp+o32!Dh~2V*&9#X1?^jp4?0F#^1R
zeVZ|lzKGq!D4+#gFXQk}P`Jw&^gv%f<7+?oJHRlz18j(~0f&(tvxXTD=qo-WjF3$b
z9b>#i=a$DA`gwqvV1!Zl=po~q%jkQ=NT+zw6r)K4G#97moB*@OX`MTqadr9^uZLM~
zPA4mIDczlhoN<9XoQgfb?RR>Cw!Pj?=i4CZ<79dY_I#a|1_Q<6=X8#~+wSj_I*QIi
zPP<=$Xpqx+itPkDjZXtK%;`T3`of)ZdVm(;#MujS#OZt5_C`64(xVgYl>aRhVx87d
zJ~_^5{WP$TIlW4e(gdd;YvD|yQ>p+Y$!Q0b&Yp78Jc1Xe*E+e==OL1vIy}LibuwF_
znCf(T5n#?amAnIubf<{f=*w{OSP7Ep6gxnVms3%&{PP)aIdUoUb=m3rZ(zRIX_Ag2
zl{m%z|LFs#SC>Mv)~SKsUv*AB6r8;7bdEM8^-g2|LGOmslXUp5$?4T!0p0AhpMqB{
zPDi|;(CYLRB{<rgcCUg<H=XX(gS0z+;s?^<G?P{YoldomH0XCZHPb<=ZYRcGaJQVc
z(K&}6r@&Hhy-r^mAlm07T@Sl=oOW3Ode<q$3nLqFN}PvFdCzGt6=DoJ?aBrAkduUV
zk;6_8sK{`{>BJ)FjXC9tK*pV383N{n(_Gp#KXm%$tOKHtoZ|T~IOQ~JF-GCc%&dT-
z3-h&i;nN=Gpd1>m%xFsQ>}8(Zh+(@ichM`-ow<tM<sQrm8lfk%k-nzr#T2fG-hO5W
zMV7po{lOqUO#RzXKfv5X1&jxoNmRAt%Y6OgIqNYaGCe<oj6ZYLT7U*H53>Lh$n2Pl
z#zRbd3tS6g=A4AxV5UL{62c6itYs*(FZk;(QCS*T1A|AHb3!q~7$%Rxr$?Ea=Rq=-
z+4?qIi)XIc0_fw+>_Y%cU|!Qe{REReh`y7|xOXw!Q_MG310{udWE&hk!~B?*pJ$mS
z%7&#eUub~dd1ma_KuKrrpcy5L*_?{L3(Th-QP9X{4pF&kE^`OP)$*8Ye}*&p%*x#u
zOCd9nqH{&eSu|%~W=cvSS<Kv74lhcW!}HKs%G{=fGiA&z27p~*&b<rouQCmhuvE@m
z@&QCDn7@Awuu5jgZ}6g;X;-4JhPlg^R)g1=BNPj&Wq$u8NFCGs8$_=&hZIn(XO_4^
zw1N2qdC|z+I|KSn%$*E)(aby)3A-)K$1Xvym8qbuRvUBU2AIFeyt)C-v@<nlV4;IK
z>n0RBnJ12*v5PtC4RV{Qc%7mlJ<N3a!c{L*Lx+*?GIMD4+t2K!vh)GwCOWfmk2x#=
z_8{}uWgtUL1=SS|Gi%<4$Ov=wIJ_8T{<95@_nB`{oy{0?_GcjD%oaPy1k;_$-5xN1
zRe_siGASYYkooTvO@WV?4M*Yr6!SJEJ*Syt@557PRxuZ&aAB=&0@=gLq*=$6)kRsY
zy{sQ;C$Nuo>nS+u#u}xo=FU1j51<~bt`dlNvPQTdUaZp_A-SJ*$`>f!tj%V4;lr|0
zp8WvpZ+cTX4zj`zpwpKnEQN1=tlnop{8{EEfCjMsX@pE5>&t9t9AeG-5G088_c6c(
zv(l)lF@%-%5F(+hzh1&c2xF~Egxzq~o4bJ$!K$L#=1A6XD6Y(5)&VBS5!Q$FLycnf
zQYl=tgY^onl44j#tN=aA`hj+)u`FQ<xHwkGad5|294$=5v+CZ0iQ}xTG*2b4+<(B0
zO=OKb!C(?=AMHm@uo@fCc#<Xj2-v4sCOWxzn)TIkfF-l;)5|-BwP7Vt&af^IK;bOQ
z;YnMjRMsXBz?^5<Ju#+q*0c>IgY^Ox&}Xt<qFFYJ_2~t;e}Uzb3AAk1%_o4J!-|`S
zfnH<@=!cifD#?Rn9xKlQfAd+=bHFTMWzkmn5=%{ADlcShJP(v2mi8XhFSE`#s645d
zwV7f%C9Dsp&{@hdy#~cH)@QEhyTTIeg6LJ&nlm8ftUx;OT*3O53%ix9G&Vr1SQ8ZQ
zsb)FoPS&uV_z^?9#@bHXs9IKe6&mYUy3H8<b(VAjef6v_>AASU^8d(z&IVT4QlK@m
zS}9iF#Ok38ZZqpUPx#cv+NX!eP1YNqLZqF=rPJmetS=@Z(#hHt1`}PZNXoExv%VY$
z=q=VfDn7l<V$MNd4{LA_Bzsxva5VO@_AE!^9o8Yrci&|_H9?i7{j8s|aJdIqNt7?S
z$9j?8bc3ulZV(+}HSUDp!>sF+*&JcHreO4=te^bg+I`j=u22|b{jUukj<X_q!A-FK
zN2$;Utb<gMI?3|Xz|uojf)n%}vF@z_<`gUG4UlP8dlE%MoZ0ub!k`QL4?noShkYUj
zimvQ{pP{jrT|hgoee88qiQvZWZO16w*$H%1#e;p9)~lXue_wE3>@W$`_p@K1Z-jcY
zC+WLuKJ32(Vd((-_${CuWPh*`jlS%kzsGR>*cwVIJN(%ZeUJ%Y|FaQe3S=jqg3KXy
z*M|TNVn=_4zF>C4LV$*_g(u-?C|g3+K4I(_9y|<Zi$Wn1!T!S&CL-DEDF=F(T~7J8
zBkXtohGZ0bD}CA^nw?<)W(?cs7jQ?}%W1lbox}ccCTJY{gW#$Scpa^z@LCeP`BQ+N
zVDF|cKAmQ#&&EKL*-0P4!xXlIR($E~tQd%7u}3Iid4c@`Z5FcG+>0PN>~|@We32dV
zI!G>i^gUqav3r()<g;hf3C{wycR4T%*`H8lS`oXV6h2*M_rHDu`o-)@`shOmTiS^$
zRLU-+6C_vIj9}-D<Y6ngO7?Bq4pp(ED0f=T?xyrZ4cprlW4Xr8F{7`Rt)dTY)UnfD
zp>Uo30;Q_!*_rRa!VPxf^YFfbt)P<5Mt110xK2%MK@t3IW?$|E*TNpBs<l@3K3W5`
zu@}Yw^Co-Dkqn>O*>~vXb+B_N$KA<ZcnX%f*s-)8>Smj07kG=kG#ZMx+1mY(>|u}5
z>+=qK0cAVyvX>u&WIua#J;(q%HWsekWA{>gc#!Qr1#XD#M&aRM_V={OA7P*V6!&hF
z9b4f*>wWg~zd>e<9rXm98fVvk2yTL%O{Mb>*jrZOB22Q6)8Vd%?5FzB_=uh714~ov
zVK<OzcKa^$IdfKShe20P`<L){FK533CiZcb(2LrQQ#u!Y?i_U+EO>BUQehCDoTq2e
z3)73!N9Ah!IlnD~C2x*Dr9FH&xs)?Hz*+qz6c2LVq93y_r*RP2ew^}`q3_SRb02yE
zoNrkmft+NjPd&u>jCSxroL}kr59V~zC#^y_8|i#sDCY!i>%%xTk-!Y+B;vjze9772
z2}_Zj^AuK(;`~I_XVIKYdP&4^?sfw$j+6Qa$T803I+%#(yhartiJVo(A(F(ID}de!
z&g$F1KFzsQi^gP*Go2Jj;RwPoq*Tstv<N=ODWOGh8b^O0_R=}KpM)Vt2B+s~=x1^=
ze};)H&fm1YzrZ>CC17$mA&b#>k<)(yTrQ`Ri&5lr1}QdDz-gwv)g{g>y1#`SH>y`D
z;yCDT6?3jugDc^*(O$5Wb14#buW;U?FH>FRl)nwVa?TI5n5=Mcl79kdC1+j>9Ioa_
z=^#rDCy&yG*Eo9`fL6<49RXLzSw(T$>zqwrqp^Xroa#;*IUDS7t%>7KTcu{s(>1W$
z!uf`F9<7|!kx*#k1k*|Bo1C@tF~D}tMw+vGIc>9{(8qBM7J=U3JbNE7cRAj-q1ev>
zCZ1r<y4i4TkW=(JxFOEzv$!%NoMu1hk8$q&hrV%6GQEB$I4p_?Kj6Hcj=o9Gs<Y^O
z$ob<q9DT%DGX-vn^VSOZJI#5XrZQ*letOnixNkUKgvK83ufKwI<1*+y<j#F_JsLf@
zcj+<l<SrV4z880JKRu+}M*;BHo7+tVYChZs3Tq$WvZ**ffIGMdB#@i*3I=+JdzWh6
zgSc!;s0MSx>VX-;Wzs?GQ0`IMorG~GY!1+HuJk*=L~%bk4HMDa^{YT)xCgUf_bB%|
zy<20s%raodaRX_kdyKoh2`1vXGi4yhxvOqsXeYTHl>9iwEu>`6X>JCk50bg}sN^Dr
zD>uNIGu+%@h@9mHUWQ&OH@%%+nCH0V(*RB9K9~iP!L5B3B$K=QEDUCGcYO?)3*6t{
z2TV3s_#GN^xZ-^fxyb!D257n5zgvNp$E~GGhJ0@7>*y=s#*U(~m|IRU+!F5h^nI*S
z?%N4)t&F>oYLc&TS7A4W@3L?eG&PlTZ%yFRRB#)g0B9w5RT<D~xdux6*Kxn2SkQIu
zA&QIDbJsnF@!sJ6cnhEn+zrj}u#wB9v|$rBst6{Uxtl4S)y@r~{Z|Kfh_=_A+zC&B
zb#ZHpLAtrm(u41~#r3Bmw%gqA_#i#pddhM4a%YYKZGd~28t-x2P2dK(-yMOaA#Of}
z)rPrS@5Aj8?q5_rJ<8qw10?Tr<#YshjH~m4!3W%C`V`6}cS#a_ddU528x$UKuY3%!
zDegRqa!ot9pHMo?nKw!&xm<YBl&9Ro(^68+mA8Tm?7h6ie?a!}c2Y@=7w_OvaQk^~
zltJ?5<*$OI5063NzyrLAyD)f=H%N6lzPwx?`0K}8+k|W3&kOnt27`HvPC_q)_ZLlG
zp*+XnF`$L<c7{PCoM)tB>ImK(nl~bOD|pa9%v=96OdR3uScg%>@^tj*#qr*vNADQ#
z7kc#Kd7o0@$Z_7THmE1?%48skyw+NvB=I)<{|E7SMXdl!;f>It_cOc*Dt0}~>v!~^
zHI<h@M_bSFdd6WXjaTsw6wmYK^8l01<9Yx)gJ(JegBN%OiO|pHUF!pv!`n>D{ENKh
zolwZ-Ng|=1$GhbQuzcSARWMP&vn~d?#AD=OyoJ2?C_!JuTRaG}mw9i0OTnirJedxy
zS9!(P08`FeM9)VB?=?OwRq{S4gQY57Kjmesc^i2!QNs&K2WUNSxjR5_@B-Z+(!e_&
zT)BP5eBPR2a4o#QY01^fJ4A_!PM!w^eY<#-uYh#(vZG<)7Vo$BL2mQbqyVLd=R=E*
zUf!YtsQ2+sQt9hG-jAno?*@5%3QZ32{tDjoE!HfBE^zlgZ-UluW4x!YK<@!>il*gB
z-a8+FJmmRNP~s79HAUQ}c#nOJVNUZN(I(KHpRyO29{d{#Q1|4=Q83?&f6@Z7pZ`WZ
z)V=v~1w?%KhmE)(2l(q6AbF6#KN^_6{A5QRSU>)aKA`#YYbl5mz`srVi9r6kYA7D!
ze-{pzV7`AaKtuR<?0^a7Kcu*97=Jfy>%;jy^iW6g_t8XpnBPc+jz{>;vmhDGXQcxr
zhTkdy=25<e;;ONHKJ8!P_#Zt<bLMgWrUk%G;F}Q}nU%<2L956lexL@RC-`;$qVXg@
zf);0|_ySsHpXTq>K`)tad;_C6!%w4C;935gHjq^Q5AQ(l9KVD1^J)CD_d(9{`}#15
z4F2~*h-C6#ra)m9U;8JO{9WKD$bp^BuUU_aki*YkkL!Gqf29OI<?=tHL|Yzz0WH<?
z`G5S5i(kO+{1RxF_|ho2R>*gyC$@<1Ogp^G{8RK+DCWONG0+nJC$w8F<?o~Lc^UtU
zMu=SDKc51Tt9&1PTgEY~oIn0Kuq*i7E?`&kU!eO`!_THX(ltJV5@xmhkLIJVj-N}<
z=ykq?QbzUsMRPHV2L3l`=xgLVsOG1MZyN_`=J&q>y%zqBcR*VCAxdE0<UdK9qIUlD
zQiyc$AGUyVbn%xS09rRcgNfE#{9X#p+~zZH0=tLLPeflY|LX%7MIYZzAO5?`FMkYu
z{rs{T3}%4;3{6b;_(GZ)2Knp%g2*u6hbksU__`NCM){}xA#$Jp#S1Vv#?PdCKh7U}
z9v5NK!C$@*iVyi6zeDj6-|s5O6#scTOghc)*#muNK>!68Tm%=W#&(au?tp@;;F}hh
z-zzZFJ8hrfQ84=41QGe@a~Bl61O*R4AYFV<!5WGJdI>hC;tAX@@Su08x8UusaAkZ1
zjs@LNJRn#~(VK&U|0v_@D+maLT|dEvk3swe*TjGc5NNG%I8ZP}-|IOf_;x!?1PLrh
z02(Z)c?FFjf({{2LIr7efgL8eoB<LpxHJ=z5rRb&=ZO^jw+7^};LZKeJ0h6vkU%C%
z@Z2Z3Ceec0{V)+D2%==#QNcWV@x%)1)ZpR-`?kQ*V}kV*9*!3<H$gH{u<m)NCkYPH
zF6@M0$1Y%>6nJ_A`;?%IcB`iaesdw2Ecj&`#*!lNas$d4K{&17&I*=HY=vT~pm!TY
z&j}XxpfgRdf{wPG7d)bfce=ntiS7)+_bObrOu?a6pk)bKD1>!E(9sT<Y{C5C=YGOe
z=1O-fPw+l%Ir0UgR5(!}=%b3VO9CrJ3<?EK0pN-R@B0JuvS9dYh!hK6c?o7q1hKSW
zD;1Q}WLYNop62K)f+yaE$W_6PC9qd1_~8SPD!~$3om2}p&VfjcAmka4YXXsDD@1Dr
zB^N;I1UI4qb6s$(0ha0oN=i4}5FDF=7Y%~aXK|Yv1?wpZ&?NZpB`7ot5@=R$5!i3Q
z!&X7vYZyzLAc<b3HwAU;px!Q6Nq<PwArR9I=@e|GN3Kf{V?|@PKr_Pu(OZHq($Lu}
zs7nRcCzwf9D|ZC5DS>)dQ2r-C`vq^i!?k;YQL5}36r7%bGed%2+K&$lu8v`ZBZ7oZ
zV2=tm(3zMq!6$uC9~W>b?>iy*s2d^=1YHz3m=w%b!tIBG-LKJ9HYIrF06M1yUKAI0
z7H-)OvPXEI0v4{q2kXG?6^d!{+9$k72gclluTlKZLpXW?#8dd-9Q^eXMp7_jzwppP
z_~b3z_yvfMaC;Ke4+>wWEU>T8dl`K46N;WjqrcD@FMG$V0O8O$Km&!ZQS2#5_ydJ|
zf`y;W0BDFXm5sqf2n}DrQlxO!Iy4>@E{=g~M}&PJfkX*6UjS%~(7OT#j|zL5fE_C=
zF9KMcuz}V{$Aq6zsbIV?ooX<T3$y8Mlqh_I-nxz?;jHt3IU(eaLjR;NV+5l(B}@&6
zezNfEInYlLCemW?jIf>tdRFK|1=6X)b9{{HobXTDmZu57+W@@`VFK-oGlg@1hTB=f
z<rG-GAauM9y=>tar4lX*H-Ck(<O*lM43g&%?xy>jFP!%#3>FAC%>?!(;jBz_774$g
z-{xiEGWy*X3&+oZD-m{6L20Ql?Ijp26Q(GjepTpA)g$G?n^ZVoA)H|YS0%i%3L@1)
z!8jbP5&BTs$TgvcViUDO1J%r27drA%K<kBbJ0N;PXeQDie24aQjlv~#@tcIdP;pU<
zu$#W{*(%hl(bpy{rg!R1;kPvPwhR5J&Z|SX`w=X43HMXFp<BpX0<c@c4=9}0C!GBi
z^zH~(+=Jd-Ax91``h{hV$DlDFj48vg2Zf=TKpPT9yZ~-kSjGSu5$^p9Fr&hCCUEzK
zA+#DB6J}COaYDFq2?qK=7`Pm+O$yg926-sVqR`|c;ovbSObZvTf<b3d;dOZEBHBrX
zyL&_#RFmN<3ihGb!d}tn4{&jxh)p?O57FGiFySfs-5)YuB5w*A>=(tY1o0Nlu7ZM(
z=;j@W91yMF2y#%=ItPRB6^+KB&rkGwC0z3tU7?vUKxDiD=s;2RB}g6;&D;$xNaS%D
zt_6$icj)t~AtKi{*bNnZu?VeUqNSA>Z@B2lLKut?eQ+6Eq$pp9F&!3Fz6=vbL=*Jl
zi4t|~Mqji@`X~BgL=1Y-9u*apfW(SExQb!NiJEB1bxbsT5t8vDm-(=8T=Y913JIct
zxBrLVU!rI?C9{)6Q&c{6LNuFx{wGC6?%+;|qG<7OT9ir&=VVc57Zg)O=Ql#(j400z
z(6b_!FCdvJI=lnJJ}<KSLm^%C!S|5N5Sgf)_JZgb<vy}SK6DFnMDDl1<%wzva4j79
zqMcM5RUo=dtL7rn8hT+~7Clbeiek|}N1;(B+V>bNT@ju73MQ_K9;X#<rRe-8;HpHY
z1yHXRRZ;nVt;mOVGj*Z`l+?N|y0;PP4WgG^Akrv0L-k8dq7|P&q*e4BWuMy|qB;tg
z+!Q5I6s27hG75(~MEj=UMW^U*TGe%l8vg$Xt?0ug7}_n-Lh}2zsDf5rJ)%ESA<`$R
zi-W&+M7$5d-4(5)a9Y2piGu0_qUY$9F(}HCL2pPDPZQg)Xcay9BO=E$wCEodJ?e!w
z_eF9sI>$tsZ-F*0dW9zY3DJ)f{COa{YJkB>k?jgVABtS*S$`zr`2loFbml4~r$xyc
z^f`+=%`opGzVr#e_K2J7AhJ)q#SaGE#6Q#a)?NHGE&M#h-#P|??I})Dfb|kfbr9Vz
zmY;#Bw|JEWXa~f9(z5KJcnw9se8q>@u;eHH<Z<-*i&xRlI6yr5JVXM;TT4L>iGQIV
ze2Cbm1AU?5J|o5wCLXPYLZtZcBt#C2eW>8~h<MF02WXUdIsl!~;w*Yhj*1sQfcaRl
zg6hfR#J~T8zGLFvFVPn-ev4l8$Hi|(fJ+efeS{Gvio0niog_X^Gx!Oyr~?Y;#DCH(
zohD{c&FOjZD{M5Ti$Cwfa5Kci-vA|39L1%-p3M?FJqt@0#P8DHAzPgFIJg|~R@%B;
z6whUY<ceofabKRecO^)^_~j|MT_E<L+4hon^D_V~6u;vM^F`tXOo&_-fBypXip8^N
zflwkI>x46<;y(`INhlNVrdri2;_yNG{aqD1{eaeTu^ZJ2Rfu1WhG?ZYpbU*w;!o*E
zSuL)39x%1yhSy-JPJEFjsO#dOel#|S7tmzVC|>Ulg(h)p4jP-q8!7wNB9>FFP^);;
z47k=V9=!#hI>d6SjO-L&r-hrNOYAlb(QfgwQ0U(he@@rpwz!JkLp@?nAxN)y;Y!%;
z6K~uE?v8jc5a#cSudl{M=ognG>o{vb{C6`@?unznhvc9*stjaE>`Iu!;+WrIcSL+E
z86u-%Z8e;^FLq8s-<U%jNNK}y@g-W>Pl(l&IDR0$d<SGwoGt?PL-7Qq{T_+m8pq|H
z5_d1f2&ct0RFdK>$q+-`MWU^M+j}Go3NE-xjC4u%O1$b}aGzuz{nXqfjb*UwE^+-9
zjUJLe=(pu5aqvEeT`$RzW|-J7x$lEkZ%Iuh8hs@Bw7xkYai`6OpX70h68lS*t058~
ziGKi*K*=21$RCnSQu;ecGE)xhV2K|ktV1N{Y1#>uY%zd@Ndny=87^5E4u2ygXI_S6
zq{QD5i_XK6<FxQRA~8^AFiKK>1P(__*3g?eMp8=k0Y@dGLYRn^42A(FPO@|n^y4KP
zDAI9U(oA!Hg5;|!5J{A{{tLY%$xJP-;YrD+88CQCQk@5d(~>RzP&gwAp<0l$l5GW)
zuS=Dr&>cM|iM4`DleEZT@Vw-KFD_}i<SE*hWJu;w_B>NkQvk&*i5njZ7bI&qkj$3k
zt^k)K8GH(o7bRy`!C<arV;#)rNq(gmYQChJYFG*+e)QYCB;iv6w@~tO4jtAll0>+m
z^Ri?wz4nVGH57Czk?f?>ol?nZHAKrK?sO3UiezCbM6ODnqf<ELl4bs|TOnCSyQ)gb
zi*&fFO0u&R3e}SJwBD|f?4xM>HOV9$lB$(l^95Hg(Nj$2hUDHR`gm)DBvOo_HA*sa
z(Ap&Vfu7Q4$*cVkZIKkwr_)*`zrTydHpx6%pWKwZIRS-sNgJ(;Iwi9o$0g~KY@>>p
zZpmkH=<ApGUIZDCJb4m!?@4Y`G-XioMK-u0$pR_|8kXdcq+>*~wHM<ZmApeC%KMT>
zYe2>%f6_cTA^B5{z6X+JzrpULWNtbdA4+<DMdKsM28t6+N&cmCl+zLpRc5+K>zBcq
zJ<@{|L3WjXLFcXAq~YDL<SzZ|T{L<~w>E?Gly=Vr=jD+8MMp69OQ#y(o40hqo8Ww;
ziS)D_kaB4gd{A0TA#XovFcskXOREk;BtW{o3Zn>={!VGIL()%A!%~p+cp6ZGrI+7_
ziBRcxl+p{6E<OnLaOpoy(2J0MqlDX$(&J2s9FZdY379D9)@<m<NS$dRc2qh}3$a+~
z3+3pGm-elJ{&DGcD!@&U&ZOM(8EN%lSUM}+6#%_dsn0X;;+!;q-jr!l{{LY2y!1Vq
zS2Lx<bly5k>b41u7o_)}f?l??@dnK2NN+ie@aCd4hC+S0(oLITFi(1hs(kXLqwP>E
zkXooF@{;sI1MC(`AA1%Gm!-SrK%rO~I0up?(zsG^rPAj2;YFEr%MnPHOAQ0yDx_yy
z(N`&5a{^qI^sTi3tCp70Yqv&vltcT!YtlM;OVmog+W^HnX(L7AuERGtTra&yOVk_E
zWmMGBAYDXNkd0CgT8cDDH#NY+W@%6{^jf6c4?$X`Z_#F@O}d?8GB>5uZ-Hx<eix7N
zc1Zncsn{u<*$(wCsdp%q%yvtEq#f=p>2J>i`?mCn#gOTdt__9xUg=_bO!}mQ6y&=j
zT~r9}uC$7l<o(iX?Pwg3#+?SaC*@Myeo!jP1j>*!f#Pw)(mFbHJ|f-g0)<iO(|r)R
zFJ<PTZ%q2}CJJSZOD|BMXhIq?0GS8UO<bT&N-Jcz6%VB@&%*CV($CzWI3>MJ+k|Q9
zQxq+8mc2tCG1((~KyjOWvU6L|=O$Z2x7l4b(+&|2nJ)$TJY}191I$bI27O~{zbvW>
z3f{7RC~WHRkum7WKOl?s2iif|1Rc)wl^rsn(@&N#7sOxoG$j!OWCtnY7%qE_Zc~J8
zV+}~8jK3Luhh-a*p?*X*;fuy7S@33DglJg--N_hP_9I-iqq4&5;9_MSm*7mC%#9X1
z#~iX}>E|CW<5M#5xGamxA`)b|J0O!NOQ0Zkl8i|K#1pc^r_gs&Ci)K^o{}kF0(V+A
zO~tCovhFFEPm!?&P&gy2{Tz*FWvu<sOO-AE7apFI6<-2LlRe)D_4BfzKVUCi=HR>w
zHbb_XLY<ki-$*n|c1REG3$m}ZAlWiEn!<Br!xI?AMcFC^By(lQDHN6`dqA~S`7%Gs
zh!n_P>;~v1SsDi-g|etX_*5jz{|J)BGU)@1w?wv!o~}~a+GQ|XCfn<n2N$o%)a3A0
z+1p=3qg)m}A7~Y_cnumWW!a4|Q6)>GHF32ppYnD!vJ^TFc1?C^9sIp6<19sAz3e<y
zKi-h7pjd8$Y#9|QH_A2zL!?PI+6FJ0W#$#oYmsp%0MaT;2%=DOn@mmFrJJ&)_tDxe
zdyfL*9kSEjQ0$cTOo8i?{YvqdZdnxVd2Y$v=<_|dWk2nPNRQ0;0^IJEouCCmpKSGK
z=({7Eza8YR%!`7s{jwU`bPUL{D3N+k)<7%GLD?G;ioXoWWE7PgmOZ4O%!tgB*5aeG
zZ&twWeVKU;$e8T>7ATI(hG^+FA&a>RyANa|KY~okoT%XOp{(m6ym%ygjQ)smN>*e7
zH!UlxMxV3XnWDa~@>!>#uveZI4U~QI64aYGW_ieys7%LGZaNH0Uh-`-q39!@&j2|f
zzf6higYw=j5b>2GDU4r*d=FJ>`OC*?9~U5>wGCXLd<|7EAClW>Jr*Qq(Q+_YzT<sx
zA@ahtkPMaoO_j4@@*mCuC0xFk=6Xkjyz?BeBjv;4=sYZUe*l9=<lj(`FiO63CP1U*
zfs~|;k<Xy)&{4UaUVO1~?*BmI<cptx-ZA->Jd7z`zKa4U$K`Ew*f2>x{|k6=LY_yF
z?341HH0veHAJHS1BG0Bel`{_cZxs4FEC1sn*i`wGl!QMg=gvc8n*6|gczRx5vH*?g
z@<sk=%#gbaftD$+q_{$se5@Ft7vu|;gUgoJ{sNLCAEhnrMfr;sT=iV}IOP}f<j*N!
zH($QF6etDq4YvS&N$&XK2;47}Z!SP*k$m+zv|g6)qJToN-0}u)Wr;juJ<v+!R+^>D
z<dM!GSL6q2mcJ_BO!HK^d~H1JR>>1+A66~@i-*P<`RWRoza~FE1M0Q%FBYJ$POj9!
z!VUR7+KDvCUvNB!)<*fa=fL*J{XF4CuY81#{`bk}P;B*%{3&{!-IY(B#YO0sd!Gg9
zfPA+djrZgSPeE@`etic_49Sm>+r#q2a`cVJ<rK&pm4A5<7VgXcrqhjM^2Qo?KQ8~9
z+@6sC$E5Y=13820X(#1#FJep&<zLc^;E}xH7!;iqx&H#jMKPHGyL%Mp=xmFtLU{;{
zdleiHkbR2cF(|kxl9do~S0qwBl81svVKz@i%e&yb6!Ob(ZNK76iduOqp6Z6AkHY5-
zN`D_v_|mL*P%%aO1YboDrC$9M(NyT-uQ)<aOMv1(9$*3$D`<OjNO8RqT#(`&N}B{L
zn&@~&h~iyJScED%spc+BVWZ$xxT1%OBq9`5KHwr1Kj(rwtQgu4y(5Y%m?j;wq7-RN
zfJQ6YccC>#Q9}>ZQAOyt;9?cEJ8{|K6l=f2wK%3YKykfz#fKCuIIeh;b}|VHKl=7y
zqQWr~*hz}tW<vdhVwBeDCl#X<sX3)+q}k)NqUv#ACM%|B-<YD9O_6ZN8O6z`LC-4w
zra)k-!g&KcJ*T)sTg)_t{A-|{SBz3#DP3`Z;)xlGm-B(0sc;Je$x<}zh20B^F8Y#g
zwxV!7)N>S0K2W%*Fh)ZmR}mYC#yrLT)xgYG@c#rUP<+t>a>=21kD@Y#iUUCyVUfZ%
z2cVY~GiW9+R{R+Om=Z-$1F%aKPOn0vOp%<1#w&^+=yG3GNGRG}snAo7ph_`D$(w4$
zyn2AuD3WGC;hN&WHgL6ys1GrgIz{70XuPgy_QG)M6^?~esCh%-{vS*<C~E24Orv7a
zDKs`Id}*=Ptk|~;*SST}{|)+XD#Aw5*RGiS|CfZ~iRXaUsrcXy`nnW-&%y0(MbD?;
zdKA)^F_vCM#X6|>DL(Rm7ySwk+FA}M4pX4#p5lE6)d&wO5~v7fMBz(EDMl4<(%gMt
zQPBm5#}wz6qi<XhI3L`EVw(fl4-^G7%TFq7wCsMUm`A0gj}#Hl!L=#H0*XUUD`rqx
zk+X8n*RboNWUqy5dz7zGJi%4@#c4F|Rkm-X_n*6RWgD<Pl<8-o=&4+lhB0|7^X|b5
zAEoD?Xgr`C*$(}KN<I}2_$qHDLcveDk18+xl?@kRDL|>G-A15t=tVelNZHJRdXQ2<
z1$n{BPI`1gl*MnNFH~7UpE3$lu4tzCOSm#%8JvnxMhyWwQu$voWTKQ3224aNx6>RN
zqm;>k9jBDhlYdP4*DR2D<?%V_JFXnE!?gsZ<_U0#%3i8ZO;Wl%0fiGvk6&Qvq_Wlp
zLpr6j&=;0ZD>-&>$;xSzH8^IaDCf{3;*3%mf!4Fi>@Pu5m6J5}pHuq20-w^9(edyw
zL%FjQeVNL?wqd+k%C*NJlCS(_Glo{6?4l^aC8cvLyeL#IeFBX|%4L+@x~!b8hF-Dq
zUkQ9FQEFF0uT;75BRJzIQ{JR$_KLFpE;_F&e{csWS565*DwMze2TPU8ovUHKO1b9@
zu&b3{MS;{PpBMwFQ)+3xxvo6c1eAK^sw_0#P_CvoWrK1lJvxm_G1X=@DKAn5ZL?B9
zq1hJYrw3sErbAg)3EHmAqGeKtGVVW!b}Hx55~@r2%Y0yWE0d|R=9cmn<wR~P7srF^
zQNHpRB=0EyrjuKDmF!<J(0=8@vv71k`5T3>?<ofsL19qY$VB6i@^J-R8&>9(!QO~+
zaxF$SrgYTNVV-g2$&W!Mlp{2kJy33?s^UrI<5b)HP???%{YT3AR8cpjO#cgZr<Kt=
zA-P92N$)sU)e@TX_o}jP<081LUQnXXLsdu~da810&*H7}8H1xfs!u30c|hgE0q3V;
zIh?`zs}|hCm;zKAGvQQ_s&5uLgH@U@fgPff1VTSt^>H$|2-Qt`VMeN!xWQno>NP$T
z;#9M{!5vdssNgbQHT(xej;kc6;ctTKy}JNQRK2f(Pf03wDy~1FdgTHdPpTRN9H6IE
zRtiF$RxMcsnPk=6)sRV1$*F|mjOy5Jm_Ms(DS-J@RY5+ubE;oHhhCa$CIxKHt2V8K
z!F1IhSumfWGWww}Q?;7Pd9zffB*46&;=B$nTlHWO6mnEk9`N^~YMCdMU*@V(-i1b<
zYA_NG7pQV#z+F;VN1;)uI`{;<C{iir!l%os4tJmxtIktGxJ0#k1Tdv47vvFUm8tUf
zU=UYSb1CL`Rh7CA>g6i;MR2V`m9rR)l`7>AfUZ)hcS5~dwMI?9zZ%t|Gl03Ks{Rk=
zudBkV0aLGP4}<6p)z8jwxJmUl9V%;9eMV8b7FCQ0jW<;WT3WZOJ{Un?hiYvpxK0)C
zQ*d3X@dH5VR>f01zDKqC6Odk24Q<o=R2GUL^sDMA;_nzxWjjIfp6Z4aor5Z8s!JMD
zJ^mW>hgJUzN8^3fHHy}asoY)z8CPjiKqgg>&cM<`)gMbB`AD^#!l2ITM=EeG>Rzg`
z-=qHc5{9%-J%1J&-PBvw0@_`zZw2R}UPhCqr$c=p7BXIH4Mp4h)Z$@u`m1{=aUP)d
zD}hX)T22Lsht!+tu?|wNp>=PtI{PiSAEN$@K0Y0)PP+%mF!fwg2v<LN4i_&%opuyl
zq&mn0&Ky=B{TzBn)K0IXFG{W61!tnwjx-O@81=Oaz&@&;NB2Hf-9%gBIQ2VJ6?IJg
z@fR==uO6sF-*NTOKR`=RFL?`niRxM2@FGdgrQpa3b@fa*dQ$z~6R>njZJ<(y)9T^p
z0iCR7Pz`sA+K&pm&!|0B=sT-k?g#{%st%>c^PKwEXW&el`nOte=hXujfR?U)%nxW8
z>I@2iWU7n8VLnUUo{q)~>W{8MJzH(2Ky8kC<~)d8RIj6I#$5GZML@|@Yj>bAU%j11
zR-kU9_{k-8n+9B=IysBpe?{uqRK|Q+{Ti)7iq)-@C@oR1&qrga`pi}|mZ`fb2YW@`
z?hn7Os$b}XNV$5;A$U=tevMWJmFgQ5j;v8nQoiMyT1!!pTD4~uQ0mp2e9(A9y_#w!
z8q~~oxZSM&`CZ!owWy<aL$OtTYZRUB>XN5`)}hYP!fvPfxiT2MrH-Xd@NIQ23tsf7
z)7AsDR~_yPkv_F6&C7Sx_4M1mt3Lk*MEcdW3N#L=>nIz4PkoP`gh6%M%eWOo>UOHI
z8BurLrt;@ebsJ3>_tkfPgxxW9@CN9Qt83nY!3nj4KHB*}y`ORglWNv0=zFN{qN2G+
zY8|$Nv!>K~Us#$}XH)RYSyOlheJ+~q18Cf%d4*mJt{Q6&$X<=A0$%LXunwTlP4fvA
zE;`&bdfFFxX#ThheNW9UE}Zew1TuiVU-KvrjounH8|Hm9z7%vjp!tLk*A8lC9EP5+
zru9ci`f1Xl(CDwJSP3pb^Vi!@2-JALhQ>ph4Nc&JG<*t*25bJJL|BOCnd5LK)S<aI
z8!};<6-(e^xaN=ZFdw0*q$EtFX1W5N9@dP|oA!vthkngbnst=cj@JCJ7kx1r0e$S^
zs3x82`eHTJHNcM3^ihQ9m}cI2ka*1$xprLhG|f{9njnfQCTi^T)=$zne#Im>>x8C6
z3UX5Oei5)wX-?5haawa?63!%RW>HOaismaRG|p)5{{XbJnuKYHq-qlX2a$7{)j@D3
zP4gKABF<}=w7g2!IOV}oh9>SCKxb;sQ00A=W;zay7c^Ciz-4RJIw-T6qp^Mr_b+OG
zr$ue9W^4+6=V|Od0L|CDOv~5;O&*muUDD)Haaf_|of+VYG^Z3We_3;sBFn{^tsJ;k
zqFKHa3Z<F~+9#K3>O<h@6-^*Lfmb#C^foKkOauVBLX-9i{r;*o-oa?C(G)HRcTKan
z8C<QVq#OEmnsrnxe_hi>b-?wSyHp!<Lvx&BjSZTq&FE{?aQ4G)ljbOuRW)m-e+Ac~
z(anWIt7dj8JZ#f!-wC~&nvZC4*RGlU3@mhLy4aL|=+vyDAaa-HKYIOkYvSmD;4RIl
z0NicO(|<#wN7FJF275I(se-pp^BMik!yV147+AWiNu?@)eogBphzw}@C;)j+;}r|Z
zK~2RDG!AL*G-52nn$4b&9MRZmwj0%4!H(Q9>%L~n6Eb6({-@A6uK9p=6cd`STcQ6z
z6Jdwwq-KO(77sNNIw|)^(`djYozj@8LT6gzN!ZTXc}z6AXdiCD(DrKgP)cQ=_6iS;
zZrZ1*GRR$9_%<3nw835g^VHsALeJr)on8Tl_iLFH5AoJM5rS49?JIOE4rmX33bcb-
zWjh*uwK*9ee%eo8MWesAh0-Pg+DR{{2WmSkxXy>PW0!I9g0v1whX-rtvmg?p?V#0U
zsJ7xWSP0WznFJTEZKSt;ghLxO0sTmA=XX#%to_3XjU(EsIGBji?pO<h(b}h}f-6Sb
zL;6RxS69QeSgraHMB=ow7ozW&w)+llVZ1iI4k*X9AAF9+1ntafNG58Z+yG~iv@iXR
zz7yIJde%;AzoD7*l-4m$d!EzUFSfv&WbN8y$eh()rG;Fo_DMRHc}_d46<nHj#zTml
z*9Or6v~=xYJYX`kZ_>w<Gqskdz-4LY{sFKH+WxPhkgZ)XiIL@KwMn=#dD`>z6U*1S
z4}lbDBOk%1B5kqbCQMw`mZm_aSgX4Q{W7f!)pK3ZR#F7;s&+1It17k6s?b-Z?V_@u
zYAyd&kOr+thQ>y1d@K~2v|Ew^)~rpbg+hz=C`CS6wH!Jm)~5abCpdaj%h&*}UAu@@
zg&o@176)WHwSF|+b!p$Ba^!C9&kB%R+R{wO+}1Mav}2F9y&I%g>v|D=ecH%fuzN?F
zOLf6_wTr0)qhI?CeH?s18!-U$_q5fN7#h@mMa5l1+7l&c9M;ZU43rV=<`PJbYQMQj
zU+=rGy(k0BnD!JcaVNF?GcbyW+IOgA<&n0E2ZyJ$X;hLht$pb%V4QV%e*@G-7jO}M
zdvyB);FFtfC%ul`b?(cc=b?+HAC;%>*-8*E-Ap<hvtReb44C)Ut)dN|kFM=&`g+(w
zo!h7A^wqKHD7>F;LoV*Gzm6Xdm;l``4Cn{yr0M88q<cLSmV$J_mmm_X8-D|RA-c4U
zAYr<CDwYb@eV+giBXrNF05ei2&xcQkb;%95KvBAno`rg}E_oazMt6*Mn2uQ8Pw^O9
zoGzsm<e09T2bkl!+irkK&~4p^E0d@beFBoCdolzXCv>&9!JXD!UkWZ+x9v92Qgo@b
zTtB1JP@49v?n@~|Qgz|<Q#q#-(J8nzT}>w>&+C>9fXmb=n=rtvH*~Mxgy;ob>$4Ee
z);;t8@f+PQiD<m2dnMTTJ3eb8-3Dha=}K>66otAcC{9(RyT21?mvw2Y(O0Z%p<<5`
zT@xkHN_GC^Z<+4Nk1+aj-D>(CeTDALM373|j0I?{(kazYuhw;opkAX}O!2&Hx}-ET
z*6O~c?^@L9*dM~B>$*?}EeGp$-)@KK4PEGYbT;aiQo^H2w>=A^Xx3F)L0WV#%>hiS
z?%5L%Y13uU@AjtdZzlTMb??{1`wrc8S9sW|Gjn07OPAe?#%^8JIf&fS{TBzl+d9v;
zKzej>HZ=C?)FHG->(l*9MJ9K2t&!-wt801^T)(cs2R;qx&P9R@>9$=18P>%Mp)jKB
zI|%b*x}Rx(KCZh_gF#H_+}{LwpxZ|E>61DoJwXq39s=l1>ze3Q<E)SP93n3I?T=xA
zuKJ(0(jINE{ta40?9;nb{L@YU6m5{*_3M5G=b;x<LfBKktOGD!`aUaQ_Ukk0wcxFP
zg3_%%`XD+?=c_+UaY#S?8&tdGuTS|IBtV}%0xtsfofND)q)*fXB}jjI4eSN$Q}J{;
zW`*ckv_cNm@1S`jOkcJF8sYkT&X9@F@4SX<5vlK@v(AV0DGcZz(I<>z*irhNC!r9n
zf3XX8WAxuqQsJn6^fQoneGe6<9M|WyLN7tTVE`hD`ayS$EJ<II5A_pzHU)DWC-tlI
z(Rxb%$#N*3)^DT3yUF_3k|2|!@4pDeGy1u0Ks&2{opz|HdNEZWoYVV10g|R4NP@_D
z{cG=G5b64ir=XspU(pPOOnve{Fp;G<(n9Kjem9-u&(=578X`v@d<c3M9r|1IKy&q~
z6d26YOIa9wzW!ax*cIr{)1Kv$enbw%LVY)F8jAD+Do(kq&!+`Ku|DTR7%b6Wqq7aA
z`q?!gW%^JSB(La8njv{rpPUH`<@)uW0ISd+%mk^_Z>E=cmEJMC5iVBi6YoK^Mn6td
z@HPDxG_};~_s@qjb@~?yG0^M!h1uZh_0Q23;)Z_1XW$z2!?WRNqrQ|9!cF>Xv~F$I
zhfpN0MX#U&*;c)Q;_z+yVv6V8)bsAb?RI?<rNcV(I~_OC+O41M55-&h`!AyNw*GOd
z;Ofy!*^ueg-+3K<efn4FuHDfecn9OXtN-5y^!4k@YB10N{n1UZbWgv{fH4i~_t9~*
zA-&=O6o&PmFG1so-u)%`JEni{B}k6zn`qH8p}%w00rwy1FVi+~QXfpa(1-d=s;_vY
z*U-W3DgAs(3Qp_4dm27D8{+9UyBI<~!3El5SaS*@u7=0=f!k|%G6Q<<hVb{$=wV2R
zfP$yt0~)WFq39qi>^J<(gNV0b`)}~V#}GA>Vw49AUF*OeG|Ztt)AlvwaNv`lVT@|R
z{S8mhqZ?qju>dfEh8c8-=#Zg>f_*`TKW4#1upwFr$q<9K9DSjN?!{0DGf1g&B;1fU
z4+bL)os^)7G@PQ<)nUWqbS5s^;CAAF{|lb}XU0>G7YHcU@LVyv;|w0RajA|Ow)<k>
z@rEE;V;?v4(oZkJuxtTD5)C_3fRJPm@z8j}V59ltq`}64<S9cx#R8HIYCE_T!$#Ub
zo-ur9g^y<qt_nb>8a}1+*K-DjGy2jDV~!fo^M)5K08KZ<JcNl1gE|jBWg2Eu`X}2^
zNt@yv!-A`5ylCLj1<yBJ;DHnvo~MA-C4;vdV=OducEUuFVfQj{mkrC$ps(1lF$ko@
z&`fcwQbTbe43!y9Qo8DjVa4+_312ll{wmPQ4d2uAU13;Ck3^+mC=MD`hJ_w*xY}@b
z2h7(PW^M%bHG}RM^wk<3r;T8pVK544*9|?ioUJ!(U4XtDhQY<SKn;fNba1cH5Vi?p
zX)@^N1G?Gp0p;9U3@>e=Lfuxw<G;ghn_+;ewQd?Tl*ep0Y@;=DhvD5e^mQ7vdqBDj
zKl}^xw+!F@hJoHTgzf`&kKy^Zq1S6TLGRH%!<R~k+%ddJrNnm)OH0t$Z<swF&I}k<
z|Bl9chG!_|KWO+22SpsSh71R(@^sjsVStPnyoih%{?o#X`-TTpayn*sgT7EWZWy9Z
zh)ft3(B|@i;o&vFOd4Jr1n5J<QVLN$GAs<lb(%7?U&XbUHvGhdqt3>h188(H4pVe<
zkI|X#h^w)|3=zj(;|4kwx6k<MAg+m<v8D>0?#7%QARfkNr~uB>_-rINFC+VTi0n7|
z(wfoRc!j<n;bYuR(TW4ctr-wGXw0PN$=7(2vN3+fw`kq&Zxm5bH^6v<4w(iTo8y3a
z$XM!)aRxbzx&NRQ3zE~&2r*7n13T0>8i3J<8P8{e3pc(I0Z${0E$vW@G!9an?yzxu
z6ZDQ4-`oeuDB}u>Nk<!*F1SrG#=m`mebo4`6GUQ-YiuBKMh6|PIA;8?1CsGZ{$aRw
z+~|1bJAft_Up50K(Ws_-m}CsDLE{PIq8`YcG`_PApr?#a>Of8#f4mQvWTRsr`cjOK
zh2oB!G1gFO^{g>x9N4Kw7L_QRH{RU|$#mnt<ABaE`n#ep(>Qht3R$>@P`F@pc2Ed1
z+t_#y1I;lmrVP_X<JYMeZ>}+dcK><CH~)h(`Ns55!4(+$S|D=Ccq0Vn3yl>qkSsE?
z!l8cI_#(w>ijCX$f-5o3p@cxG(b56QGUKZ&;nNkPJ_zKhQA!)na%1yON;_2;BW3`m
z(l~n|I;)Hie*vjB&bS1FHOAYn=(}cowFQl}M!Ob`b;eax!gbwvvIGX}joKvi-7xN<
z-))1jC=%DO(P+Al#wO!qlrwKO7E*Ym#VEW1(rP><f`@I!=dRGV#cmpx{0dLojVV5G
zs>Ar-4uEzVU4IAHW!!fh`rXF&Y59N4c+?$zw~g5w!1WlPISi3r<C)VC=`()#FHr6n
zbIyXhYb@}CrG8^J{UyqPF{upx-ZM5&!^1)2YI?|qjG^<WP-)n>n^v$RMr|L^Mvads
zVS3-Vz7sHG#%?Aw#*Ir}hRB5RS;~4nF!pr7{G{=hZYVr78YwvY$e6bRCZ>$*-61(`
zTuI?>XVctRc;RCD=O=*eF&X|wpR4IQ#b)=Kf@uNka5w4CLdL`N^1C3OCZ-AwdzlK|
z;KhE^eOd{6n+9G&<3ZCMs;KfceM+;XpJ^7I>j^Y{`aOI)WJ-7sph2dAN;C$Ws_8UG
zi0Kk#T0%_`TR_50EiYp%;iic9;Y@^y_aaE7!{jv#(ZeRq-;g<C%A!)&7}Ih}>mN0B
zx<V$_)SV3zai+#7aK}tlRLl@>%Kix=iKY)0Lm|neUJ8^Grg1tRblOx$S0>r?LnpWt
zQyYE8CDrs5#fZ+C{#gpJG!r`kBIiwxwY1buH*KY;ZicCD05X}THVX4+ndDS_b-}cp
zVi(z_U^-)!W4b|~&bny&`V%PRo4%w-Re>q05Et)~ssAk~TsA$w6QtNwS_e{M3O<Cs
zGSlOAz`SDG<O;i2O>^3yUT#Wu(2>px(|QW>RGL-<LZix*O10_LrZ;InSY!HLkIQz=
zRK`JLt?3gA(p)#~+m4%8Z+exMfHzDWKF}IWxs-ZuH0_{jktWj@ltyVbg|7tHVyf8&
zg;vwrl^9@~=_Lwub(rRULxqB!rf<tI!Y-3{3|#CsHPRD!%k=C+aJNmxLWuO5%4t#2
zXX-lz{X3?gXxVbt^a3q0`b}r4>}kN{auBZFGyUR$OEPF`q<H9%sfu34!=_oaaAw5R
z5)E$DlxBv=ebegY6et@rEnEP0+~kuAv<IdSX>UAf@}SMcL(>>l>^w5XA3)=jN%|aI
zn>Jnk2@1|;&$r-{i`n=)8uyr&QwG7+e3h=@UULpDB=?!eX*KO;X1xjGZXTj-gNNDW
zIEJ*}JO{IfW0tqMgpT?6nBS+@x378S*Wmoj*Fs^}-#nl8-2vwLN6;8(cA^~RA@gYi
zxDfM>X~2Y<573MlW^SYSM7a6aA-EP{UUeMmk>-tW;>sL0FZ>S*N6Z~sC`6e{5^%So
z&BbqHNRAluhX2ozm{Y!lZ?WdSX^=Sc{A18RX7+vpXz}L9!q9l!+z|;66U?htV}vKn
zrzyRC(ws!wl~d-wEFh=NE_8-7*}R+LiYewldO%Xm(=JdrXWpFylr*zb5PZrouRI2S
zGacqW3Ik`EonM5(3uZ4WdCN8n*>E_=98a&Di{{c5(9bm|P;w>De3w2Poo@~gLSKRT
ze}3RDnd>OLSZJP4&r^|kDb4wp&Bog>SZx0Mc~~ehKOYSBQu7oWLn<>bp!n+*vt#uR
zU|%&SD}YvR?%xiy3bXPZpjDa&J0V(SUN8@R)#hL7z}1-DX**kI{+E{F*Ue|{U@-OO
zQi{IaFo)aF*kC^B3CTwDW4;(+leupt6q?PR6jW+4-!}rR)f_-qyUpC_C`0Q_bBr0S
z?dIw0Q0y?jMfu)NGnWq7beW&K1;4w^VQV3I%N$e<?zXwU7+jBeNjXN*Ykp@QhTUgQ
zyn|uiG5<9i>UYic{^0t};#5cunEmF!nR{k2Wr&8%51v5Zuz8}v0nrh2-*&)^n%AX*
z+&3>PfHPy}zxy$!adXzE(3mjqr{CD5`7aa5Lvt9d10R_!k3(U~ET^Q(w3$iyF=q>7
z4H{i6>)(W)t0jcylD(E0+34G6`Dq`#aI@6Ym2tOx{06=MyetKQVE0=%7KnOV7BZmk
zW4TAA@dqsZTwH{M7WF6$`dVUo(dTDb`YrnWEpZeJ53rQ}g~mWj%MzG4WYL^}he4K(
zMHpGI#ZD#pA(lWYFbuUk`6~3nET^i_7jC)xF@0Dr!eT6ir;(PTmmzc5^747ynIo2c
zLGUTcqH=*x(Uy040FALYy$$`NmdEx&GS(7LQS&%U0!?1WEX&RTCEl|2EXZ*S?;%7I
zEbp&?Pl=X`8SwC=C6_X^rz~N#^E+*Me+D>5vgLXN*c6NN%aA!^@jZw!owNKxk8Yaf
zt^bd0Spv?XFWs`v0`nObH!23qwD@|#e3r#TE4K@lh;?Ypws_GjpJREJOkA`q6{0cM
z;&vP!=38E(+Moi<%{j1e$?{bi94&NMzM#^GBFhIZ5WQ?EI|@>4`RPNLFR=tX4pL^h
zLuGhZEM4azdDW6fiK24LVgd9kEQi~mP-*G?A4IAwuGwg;w%8X#q{cF<2@2ON9lOBQ
zT3+zQAnGhLdoYOWmJCW3)LR_tLR_dD7VTDCs0Pc$nb2>vy!I!!Cd=<R0ByF6ybFyM
z%j`QKt(MOpV7zUX`4kksX?dH<;o2=`1uS(~{-#3EZVQ(t@>`at=$!R!%ja}rzSnY$
zicR_~x2O*Ej>Sm>^LH&02kjdAEm!ES4Omitg28*1r>lTHXjzp6&>>6wdWZ~LKKTOr
zBNngUpg(E}q94wE%T}t98@F5=hQfs9TY3vWu*`c5l9QG;THidh{J9n)Q<kmO0GqbF
zK)1=+>O!kv7c0Yw0@Zu0sWiXtwK7|wzt7rt1Tt>cSbF2RTR(ppmOQMpdEh*)9Qwk5
zm-W}(;PzXCD30W9eVv|FAM1B?feu*vXi7S0Ev5aNul1>o=<~DwLqAx5Yx-9Z39woz
zP#tKUVA1~Xkkw8hy&&t&LO2y>ExiE}ZuL3<5@8MZh2N3ZoBJSg*lOMe{UcUWHuR&c
z^C|WbZQU7!z8EV<41-6li}Ep~IO`qy%GNRKu|FUgZ@rQSFOFN+ZiZxn)lNI(MC+#G
z^lj-RYwi_{@Pzf#w}E!j%9;iJQ`Q?XFrRE)Lg9uK>%!+Ca>nX-71#N!HE|UrQ>`Um
z0_~i2(GiHGSud;6ci!rf3@+Weo+_g<tXC<rmT6t_J6y}QMy!EIj`g`Bkc-w=3*ed~
z*ZK<`d&#qMgQ1vj9ioc60&ANE`j@QJR6$*6oxK$rMb`13VfV5%*@&SPThDwBuEe^K
z&SsTbC#k}=%o;|8Z&$2$3xIjmn%fAj-1=|~eHGSuv_Pn|_ESW>%4(!dPPN1OeL3`N
zte!H6UbFuDJ+N!7=jlCGXU(MT!gZ@BRd?50-=mVz8&=f-&>F0h%i(CFwcsOwHd)`J
zGW2F^TP3jDtY_&U!%ge!RC>~G-AMcM4(odzxaytO*dg?FS?5turQ5pV*uS{Wx2(@^
zgy?PSbEl!-V{M~iie9T1EyDY(cWCW%$LbgC=YuaBL{m-CJ?lr$fecz#QnksDbr)rU
zhOH+k&NpKHA{+{%*1Tq*+_!Fd3L<0H2lOHsw@%X*al(3&a;guku@qmQw2sgo`k{4J
z5kwwYGbvXvW%Z$2_-QM13dGr#OD}O3Tc~3JH1^m`%K_tRoA)bP_u5{i<4pT(#gwvl
zv(2Wcs;BKc%F=n+S{B2L{k9D(G<w^9p|T|(+cA1b57-Lt!{39pr$#XrU)zjSaDFyV
zdPVx%QV)O&usue95D{oArc)J%Y_B~<5yc=|*E4W2*tYXcT%Zu!x$S5Swaxt#B+TZ%
z1eU^WJQ1#QgsngW5^0<94H^&IqAr0uVmnGnuPB=*?N_61K@@z7u@znbchq)(3Myl5
zuNUB2#MyQ}2JV=xVgh~fwnv*Nvvl0nN3(Q-&C?E;leV*JaHnkEy8(0B_8IL&l5OLZ
zI!LkQtinLg*aoSf<g86eE16VV#a&>ZvpH(PowvPdg^6_AR3r2<Y|o&2a8{=68~TZ5
z*^)Z|eZjVb=FV)}i*HlFCdbAngBNYA5RhD(FGXYWY%8dEBi|OZ8$K1-9@L=kk}ZD=
z`YzkfT|r~9E$T-&Q)0Wf4R){CqUpzR)%F#wP0MZXQo6Rvb}<*0s%=lvXSr%@KK}uw
z&h|J(_paMSFh9#tZ*v4g<A&{OB}jwKw;Z62Hft|rT5UtiVX)2iuM^O2+OktY+HKiO
z(br*nKzF3mcKc;G+GU%w6nfpZYN}beWsCh2<hCuBic5QJ?#Y1ewTUU!*k{|Bi3@wj
zChCRAU59N4UCVyky5C`Gz*he`K=0W~KY@usn_@j&9J29g1vP9-UIt4ew)NiuZPb?N
z2EF^XD2n%t*-~iNJZ}4e3{KeEAAvluO&!5)p0xcz#Rv~=mGl#PWNXhy<CIOl1t`-t
z$1*AoaJI)%Lcqlya17iY`*+WQxZ2rNleE|VRTT8y?fn$$^sv8887)tHtpKC&vWHT}
zW54~>a(L)%e|!QL*vEc?*1HGn-~RviH|+yM0Q0qbP=wjfp8Y-a{Ovm^vm0O+Ip{SQ
zXwRka&msFNT4w~=e_%jA*j`K<)ew6jt@A_ezta{o%)ToUT)6#9BSa$Xu@pRyw68sn
zzQguyl$JYUf5sWkMA<W&AQEkN<N+ndUYY?5N9}&!gT&eo+=Zbyd&M4l?;f*PUBxKk
z?JMZ7HxliEOmrsMzkL=kC+z(HLF1%-=U?DX*$?*PTAa4up%h$-eUlF6&)CP_0Loc=
zVJXIvYM+dT$T@o}WggP)?>-KaVISEHXEN<y-GD-tebzj17wm64QPe!!-bKZwIrgWi
zw&0?@ZV=eH_I&#JU$Q$w!4=wfTn1NUzjX;{m+gCKEnaLdDu+UeJ$4_^O6_*41}L+C
z{u-RQVsAQ$L0q*Tr1FIdd)iizO8X+xtFmV>;ApkI0qZza7TTNWCthn0ptNtDy^IcQ
zUAJE~1Fhb!rYGTsJ#H_!275{`E`FokO$NzkyW?Acw%AwGPO;Vg^h@B{?5pWlb<=)k
zH7vE;BPc=JVb7?5PhIw1RIS);|38}E11zfJdms1SySuPUS=f8;78X`xtci&&Mq^1#
zEV0H!qsCriqR|*DVxmhE0Rg2bQWO+aK)Qf*5Jja47McQrfQTqoY>58e^Z9@O&%?uE
zX3l%gnYm?V&N*`_?FG`dLvk0D#s@nr=-z4H0cQ*zk{uh!C)=@OO%@cs-Eo#iuV+VE
zG*~|FP^<!R-g#dK+52{m=mfxhr}J+B9N2l{7Z9JFxs<RMzB8-_LvnU!;WemF+!;z9
zsg#{o6aq`%nJ^BOSvv==K|gbiJ2%tE5HIYM(1cL9bL2MEmh8MmOY%EAlNY0{eW&IU
zjCrxsjglz3caEiN;9@_SG932X7e=G)p#AkiC=9aiOHRHM_R~M2GTOc&9Hk`tJG6ky
zvX_5=-b?n$Jjhl1>BFF*!ru5)gJPxq#C6~~xa((Ys0i7$JOCpUv1{QNh)LRYZ38OP
zcG)+g+qt_Ue}hd|cU2Ujtzy@|w1v36>ziF*Y1!pT`5g~-P1M4)XS=5V1r=|0Z5j^T
z`&~cEVT`lGb@I7+IvjCBrME+0BRRJH9A1_~=wXN3lr9zGFxeIONQd{7*&F3BL<UW<
z4k0bzOmG-Zz+{JYMkq{m7)0-zG>3v#0M0v{pvZl?!<R9@<v4tigi@|UUMp<McNj`Z
z8y6gYcST!)!`%juiw;XxQ^4YqgPzu{g${Lebm6kY>LwZ?2PfK<6*-)42e8CpI4vwn
z9eRF1Wtl_wCfIb%;Y-@Fl{>7U2mZRl$5~*x;UIp3wwn&B!?5X=L)&s#Smp4D7Btlk
z<H);E;}A$WgtZQD>gi<XJ%_p1AhgwC5?lbir1-hW;9Lh}Fujk%yh_F)90pZ0`3oVx
zmSOfl;vMD;Z6oTLp(0rBGG|pNH8D@EAitHFL~}wXGx!|(^P1tC(dNkh+X>>q=IwwK
zKXzXPMXq~6zdCm$tod|60?Pf`HbYhaGs&=aKpX9427W_(`ELqncQ*F<5VVdPHxkmv
z|MDk(Pw=KQo8N{~2=lv*GcZyUi@%4o@2|dwgdaY8fSO6)wF5iZA`?7QJQt#V>INRz
zA3J`dlQq+vYQZ%9gC&}0MAQ3eX1@abJ<IPP?upq$+fnnAO9B3#<Nponf1cMHz4~Rq
zc=TrO2^zV1t>?k>Ydd*h=FjX4gBIj2fXsy@6i@o?LnrDNb-#y%#kEuL_mZtAz`u0$
zeVAojwvYqs@|Tn&x?=r)RIS{U4mGRi2cdqADIFA8yMj)?{O(Gh9awky9R&Tcyf^;-
zvx~gL{}r6Y?|n?{Ljc^Et1Uq6XZ+}vbY~JMOVxvsWI(ScbC+ha1I+e;5aGpGy`ZSQ
zH={WX9$#ipAb^dGPdY4l!c@*g<x?h(-k<N7w!`REHxo(gw0&&-5D+(Z)FaZwKFq~n
zy0Z)Zf(j4T<!_kk$<FP9lmqN=I!xfj_NM$&Z}!(~82nH+g0?Nk*iLfU{&0qULq4u3
zcIM~M6wRKayq*~L+AK&r%N|XJidgmz-RE(v{tRTtvv*RUFoD&2fhCdM9(esI)7O|s
zex&oP={877XYDCUn#yU({guXfP%6xMu7{43rE@QzLth3bJVa$CS7r~+EY6=cM%mnY
ziqzzAGbyh$m-9%3^?BU3ZIF`B`BVPV1+J?Xa0T3U9i&|3YUTiNiJNVteAq&6mj~><
z%)J~0o-16hGmw3ioBj_<MO+1iOp3X%FaS%qM?YXlO1WB!!j^HaRZw`13!-g9Iafl#
zuL>@SRvOp2JwE|(gLCNvz)kKBZEA0EK}VselC!5{f>m7k9D0FNbMuyh)Nmt-wU)D{
zxa(~$icW>y;VfLhTE|^^2U5=^OoNIBu8<zFyWC_ykVdY~1Dcw+8+4!D<Nl;Ge9hc)
z6Oa~ed^M!Ba_O`wzR#_=fl?c{*cAF6a0PQ|<J-<<j)2gIT<ihhJGlERA@mVvu@XWb
zbDvKJu#?+Dam*)N-Zqe@Tmfz2o^i(h7=-8CKsD@r!8vR~<x8&26NYwin<)?J6}PD`
z+Fo-TC;;+?a}9>*w_Ir#^u6PDX48G#&3zOg#!+%>8OG8{^05@aL`f+f#7dI%-2tJ=
z65nu?&Ph5(Kun56c@JVzCE+y?lO{RaiOTbm{Ik%TF1bJtWVs}rp27-A$xYy{OTM`b
z&Kr{6B_MT@7)q+BmmDqyr?FM?mNFmiOJY<&v`gfaxbaZ3>{9^uOHYyG$z8hi1Z?t<
zZjr-KFKH^x+}_eC%1iaZ1`oy@l%|q5I1K+85`YZpD%$5{O2h7eWJxpW3C)&HE(APB
zdX^S;x%dxN(2!@8o=*VHm;RCuy%(fElED|HS@cDUOVU_JR2E9BqM_-swBIb?uShRe
zqwT7+?_=mKlK!y>dW)sQ$p_yc8yO7QcV+!(+0-cOqEeGAa4_KaWUFX?X_oDv(Qc8A
zZ3LiIW=#K*E|;wKB}{xJ+l5!V^rK8idniYfq*UOYOn$lvE1XRP+SMK~(bS<&UM8!(
zQR!{+VE~NrF|l3%6^BfIA|J1>$yQ1U^D`N80i^(wmU>7zZ1OKnxkpTPkpn2uWHse9
zhL{X6ZUhZAIY}<EV<sbvAQ2`Fl;@ISa+_Y~sV1Lp0!cH8r~Je7CTCM=fKBo#?J~=x
z>|3;Do3LNQv>cP_i7-3YWImlp$}>4_i_#Sn1ueI(nvA2zp~%F?6@X%sug0OW#3aA%
ze~AYs|858Vnn}YH^uF4puL^e8nCzvcYpqH2RoHafWEJ^C>r6D1{8?|JBac&qNe3m9
z+%=i)3)xL3yU6c+&!kU0DqBptM?*@hi4DDA+Dv3;0eE1dx&oGmCVOa6|Hx$ZbecyW
zoA9)_=rmE&c`RqstmQEOsOh;E00x<cmZLJ*H2o0NhnS8he|M<q)~z&LriViy=D6us
z6k`c9b#4Y{xT%#rSRzbwD`7>XX*it~Ib}MV{OhMpkCPK2%G7r=jEOdV+K<-JF{T?^
zQ9NtfGy|-$rY_SUCe?KH2w0J3dXx?Wq?@jyc__oQFc(5IP4`gbGRw5B2!I^Z7@A{q
zO*^B|mS?)|Pnec(8mYxNT`+ZXK;=c#{#6im$uxx)L4~G<Ef99u)Q@7afo;bbE8~kX
zs3|plmJGRNrmf^0ghzi3O6{hx{s28R4K6_Gk!crgD;}F(Bu{Xs={F@HPfVX~0Q{Nh
zb9%m>o0b%T^QCFlB;dMC<H!~C!E^)7Js(Zm$u;RHA1VQ-lYBxBEO3^OGLjq8MILAg
zF|P6l_UOSr`7V0Xy2-m=pl!c=DfztI<x&H>bx7Vu$?v}Mzvx`3zx<ne-~!}93qX#@
z3-$mPDEFoPX@Xqo08NSVH8jg5%fl$bc1}K!l8;j4M_f=!mG7vdn=nltMziyIxfxxC
zbh%j#Mm0lzCm*bta?eiSv*h2=te!33nGKR7KS4)0bLAIk=aMIn*$8;P{G0axT#(z*
zYP~=%$)@p_%V~pnNuErOutNDKUqSR`ITwnyEAm6Zw3xgq|6vY*Me?O9!CEZeMmJ%J
zylN&$sr)E~`>)C4Zh@s-{_GvPT_In83Wi>n52P&a8}gI%Ez_IwQdd;ok`GaXvr_&m
zUH2+^Y7<C}{Oe!ASu4Lnd*9n~#cNn`M}87X5=LpA{J1X+u9x4pgZc(}{5;rpS3aHY
zghu%o%HnR4XSks9p8P!xX|sHs2`)v8eBn%xR(XF)EVwVPpsc?(xjr2%59D)cq0=tU
zr9=i_#q;+t%}=p&FaW`d&6goFL?L~Jo*6?G$0!5hnBq6`goP<|-#}WpBAqq_Cl!5H
zfJ7)-<p4%1Tqxh}l;Y?vRGv|kO@){!g%x?%q7^^?4icl-y9z>M6{jehEMAd9nLr7O
zpX(tyQ!(!zOv_R@4~9)Sic@qy<r)=f>mc;9qE8ismMdN#K&e8JOFQxFihKF!(+$O7
zbF|%5d}aXfmf~qFq*W^ZNyd;=Df(XqOSR(f2<WX*q|$!zo?_x{kY+_6TG+KHW+5F~
z+N$_@Jrv$o)Y2r-rdUO8%LfYMid(R|U6JYv*&T|8pP~Md!d`&v$BOL(ps7>wl|N)Z
zQRH7hXPznybe`>*;#WF=@LVzcTZnm~@S%*Hmx^mXklm%or+NIff*ArSZxlI{#PU|L
zj&cXzDT>H7*{#T22J&7JZA=5cN3m!>iXRla|3vAdLb?dD9nE%_!89kcp1~l_W^J^c
za4~zj1|?Us32(r%&unc3#>vfW>KVZIn|*%*)_a;wpbLAzY(1?Qyv!U|z%(DT9XnAv
zXx42B(+-(k3PPo?nL3)Ty`S0l&mi01%xVTo0cP60z#lU^L+*s*X1&Rk8)oJl3KDL1
zaVOeNnr**_QiRz91B{6@`<2duG?`V9yXUo;75Sqb&8=2|)5-kIaVT^)UwM|SH{a0=
z7FY9A1u%4<x!ZJFgn5|Hq-~a`xh178A25Hj1VX*cJDkDlW4_58Vh)-w7=e!Znpc=Z
zjGwuCAXtu=8|g?^p!ug?qwT1<`=78r$ovAmwL;A0zrm(Z^Ur2O(=qe^$T@f1e9K4x
z!p*H|Wp=`RwTvc#ljaA%h0qA|mlR+;WnMQL(oUNf?gq~p^K;)oT9o;WFF}&c$I~}U
z&Y5d3LVb$)8}ihrnopw{EzNv4<)oZ9x1`*ibn^zvoXj-8PANcH=8Y8g%Qa8>7Px%#
zjkHg>V7__-)EcjwAD~q28|DE@u--HuPN({AnP*YjYo+=Atq@aXzHtmHtIhN2wbN*B
zTa8ka`Mq|u-7~kP_)4?+2FlxRHNU(Z9c?$4SAje<pLrXc9p+wfQ2)sMs4rNan2#by
z*i-Ydl*9haXg;A22Kc#oeP49um3iwLkk{t>$bs<2{OYF=^Va<MRapAY{2qNgpxeB`
z99FzH59x&Z9`kkd#CTgoE&=hexJ@3?gBG*ifgG}U_`k@LMN<RX{4C<Kfb+MAEQ9(0
ziza$14qF%}@sNGQV!<Ft3$&2r0eI9xMYl<i#S8{K!4_N+NQlL@S>Oz{IA9Ocj$8D!
zf-}rwd@qo23s*{FIbpGn_HHLF`cdp9!s3S<^f1z5WF^RHiy7q@gfkYs=oyK!n6n2`
zqAhkCHK;vn5itiHjkU0+RZyJ8Zw^o&Z?Wz>kOYfW7f_jKakCFfNfruv8j~#o=pfEH
zi`v)Fn_^*48NF#1%T9r~Tgvi5JS=m61*fOw{Qj`X&oadxdV?+dkEFg>mQX%msAaAf
zIWv!0hS4G}%yODDEDg6Trf}2=OUX5;IBEHGJ;X#<MukItq~!xj`;4>viQJE=mcMKV
zNwfUz1OVqPuhaV?-Ew|kNGY+rLhj2_%Mr9pEVKN97L=8i-_hJyWjX8?%&xXn4P@~A
z)mREIQCn-dmIu#mOW8@3?pUS=!o)huCG8MeZ)r~-K5MXaxQUB**K+zeSkY*??r(55
zSw8y-*59){w*sWavWj+@t(L!14FA66=g3KywpqH6cl&|mXGZ~eZrPClDK9La*V6p=
z(lU~c<8@hXc@M-Z%Wr3*^xAT9FZAM#<%oZQe`~qY29@tD3*rFmw)7Z|%J-JL$(7J!
zS-BUceXtCAi;|=A>IbwrDJ#~2I4c*@oa&<NqN60P%G)$w?^BNZ3Rbu&+c%+P+^>AO
z5v=aY85-a{l-V>7c`BWkqw;_<dj<yBOS$d})O#z<@1lo3%8oq%9#rNBqw<jQZyHix
z<qHY``zdFHq0(RZ)ftT1Vdawlt&5b)Hi9KknLz1VN0mKwAVJE_<l7H6DtFMHCPX>=
z4T_=44Q5byO!-L@)E`#{P#i2=d4v*=Pbfow1ItNe3VB>2l&>$MEmB!I4Q;2CZ$|)k
zT3J;Faz^QJ8Y-fd^CzM&G0Iljq@GoNJr#oxtE{6KNSsoB8dBnw$|--MHbJ@cJ6MsZ
zJQ}zq8WFyMv~5aJ?zoFyq$xi>LECxdG&;_Zu3WJjfDGl54zOe@a|c0Tma^Yk2+dZ;
z(fc(=dHMp>Usk?-4i#6FW99>JRT*B4kttH1r8xTy<>mumxv9KXi7wqz?pT4!N@aE`
zgjFf087bmit&Gfr-WugUPtl87<?b{fZY%AQA?=PblZUiA<w@E})+@(`qOw65lMZQj
zmC1V{tx?I-a5pLYe*>0g<%W%@Y*GI00JB?_Hz_&ezVa7W0NRv{C0HIPEoeGvSEl*U
zqV%ECg3jM|DBbA3c%&?w0K{YEbUi9NmBj{BK2i2_0ph9hb}fu~p>!u#-%DloRkU>}
zo#`#`N*P!T@>&`03YIs@m$XKFtJG6g;XCD|2mqX{<~yL$*~<Aay6a-K<RGP_xmrm#
zqfc&Dbq67Bzg6IEl-#YZ41z)rD~{F)o>sRgMts0(FHPoNR<Zq1>1}08IZ{4WB5f!R
zTJ5AmAcw35)7S5Pt-hx3YDHOBn4uFf){`g&DAxLI25|A#UG!mqMC%`RDSG`PO}73c
z1Bevs%e1jevsMm;rcCSaRA8;Lo_HSkd)Ax2MO(9VcqB?K)~lAH)N1_=U6K3NoqYjs
zvmQoahiBGH0&kpU`Wm&?7=&)?BX!X9-nwB34DGT0BOa9>tmjOF=#SQa#sT1{`j>7}
zCsjXMB{{1?C;`Gnbz~Z3dZ{k^L7%s3z!*pgQDuaqGE}AXN6(I{?$c{IOm(~&Ea9rX
z<4`)GavuQB2-P9uXzHly>vA9xR4XH)H$&Bs0FtRnp_4{gsy#!&QmE3<YX7oowm;p#
zDla;IbX8SN4(uY8`)H72RRJ9&D^aaW0j^ZlLBm|8ivJyYuc^F#11VSKJVj-NN^=2S
zx~^I}p03s%)jY~8uT!Pd8l+zJ*FVtIpz5Ztb=+0;c%js&I!H&Vnp9Dgp>j{Puop<P
zYU~T(T2x<lqff1>CHGOfui8bq-)*X4YQP_;dU~O<U3IJ*iXN)|r~$4+HSR~09;qe|
zrz81~RaZv?->KR%1-Hi&Riy&Jr>g#b06tUUe^}%7tO~ya(_W~Ac9dSKvS&j~mule8
zbUUjG=ycm_Rq1uGyivtrt15k~3abR?JJk#FBzCK|kk|UX%EJPcJ*qGMg?dMR>_7BL
z3@6_AHO9o5-|`yLT=>F1V0Gn%3h*4}gNh*g2p>HivXAmbBOon^FQ=@RP~OH0xMTdE
zGz%W*o9DsaFy8xLSRc-(l%sTlA44m)le`Tj*GKS+$&(SuYbdAV6kjn3<77O|dw&Z2
z8NQnGRigNh<YkZMn`n&~!_Tfm=`3$Tj)GV|T?Z1!o707f=lfDdX#)R68aNYqBL~?@
z{6rQ~lKBKW6L5~7wi%@q-pLVCQhBRM=wKQ@l(w?x`KPotOgHig=fIl5kL!opOx`;Y
zr7T{c_;EHri!zsT_%>RM=JNM<0g=ZKpa^+BucM5`3;aO}wiNJl$ftIZpOXvtCH_lF
z{w(A#kRRtV{}=i2uJFT$0DhIPqj|oFe?dXVV%`}15`8M+>&bOm%CDoPQyG8zHW1hN
zUnoFd&JU-kZUsM-W~}SH#0;D__?usY<t9It&H~@!ch^IGCBKyPR`FvjP+84~Nx)LW
zpW6d?E&t0_klXyHN$ATRKGq){tmB)F6ac8_$A^NoftM$M+~xaSLJu4HyR=Jb;;l6h
zdXK+HAEs*NZQH=o!e`sUv{t^u9Budci4&o)jZdX@*aJSk43+J?Eluzb`TS&bse_+I
z?x06}VH6B~%rBmW%1(Y+DMhNE@M0CLdCIRRPrx%ii>|?QzL+9yFZh8XN-z1z6p!iR
z{b?!wiVyf3#=Pb^()5PkdKH@9@>4uP-tl9|x6;k8T@B9nyw6;~d-!+R;QYXEi$Qlk
z@>7lj?kHrApuLWh&`8;)&VnChak&VCD7@e*yqSa2K4C`@40aRR_oB34m`I5m?!vb>
zA=E?gyb7B<1)rU0J0SSbc>^zDU@bIx3pvk$^AWaD#P^`^i4)om3A=7Wk+1N56j=O(
zKR44}$6wfJ3WEcL?Q~S{urQy#rEx^4I|D?ZFo6<IjtZ~o6n&78?vCLK7BW474-qa<
zEGSfPn+r|Hgpu^lJ}yi-43;qA{sL$U7p77+#tGr*ERd6e&sG={A!O3Afk?qB1T4l=
z!c00!d0JRM55P0RL&{-`5}HFHEn29i6-A8j8|}Z&3Xahru|gt^Y@9G(gcb3^gn<y6
zAT%QiBux~GD7Ks=gm!=>S@5FQ`Z;0zICL;Y==Z<JP*_PbPMWZk2g`Y*FgOT^bRmbl
zjTyrBolu`CoT3rR61D_GeYSAg9;F=N-|;}?3iFnslqcLLe_XzBVHp4yggvXlSs;WA
z$2eUS{#c2wT@v=cgWf{n_g5%g7NmOtxFQr&vg=hLUk6eo7`K!6uUPP=h+2v8?{SP}
zsqm13h-Jc$lo5VSm}o@T%7tYykX9jBMWb|G7(~zg4PiH}vu_H*K$vz*U|&Ohr4ZN)
zq)M2y1*BRCE`+ceVI-wn*9xYTb9Y-<`z6}$2oH?(C7(LMuN|7|1$7EYgOEYlAa{k)
z#UPEsJQ)y8!s96@-4m+mQ^w80O@H89gdp-Kv<fk_l)o>mB^PF!u<IyfJ`fVJ(AF*t
z`U1Fz!cofm?-0JZ17VMZ#jnuzSg7eR0@x|!+(EaW2rI~I|5UiX9rx8UVci0B?YZ!d
ze0DE{KD0o1DQt{}m@Z*+J;*DeaVzY7Ei6(2@J2XFd!)C*?O>31f+f8Zx&^E8;CwF(
z{R5Rf!aQ5(`yl+dALOH;P9k5Qqu5{uF-~F-2ZhdJRT`wZhy^*Y+g1F)fpwo~@B)jQ
z7#4!I{h~XqjNQeOR><}cuhMPpDSqq)_yN&_Mc2H<{$tT4Z_%CdpL|3=71SRTf2Vwg
zL*hhQO!|rngdvSmKXJi8ApAug<);RSzfkDmuozSXo+F~mbO;R;pT7h-D)u=HO+li*
z8pZ^RA1;D3M2x1bbf~EDK-)2~iaZ{1;u1O;6fZVRgP{rH*3n=|6qk_mH%Sa7M@_Og
zgPsxNIWdR!&?%yV)`6*_HLV!a#O@ui^t_mn1JlyQ`LvzN5cx>x%@mJJ129W$E`-o*
zaY-I<Iby_f0CGjES5T2Bj#h!>i$P8RTo8Lx5_5q#l5);3ihl;6bV&@jfl{GSymlSZ
zE{ivuVel1k5(Uw(ifQz+FB047JATFDoKK;mM6{sYT&Z~XX8_B@b&Db9n#j`wP%dWE
zGg2X5rP=JdIBEq<yCFWIEx=824<%aO61V&XMU|qS94=L2pA?9$7L6}yZ&)L~rCnLA
zXci9@w?(&;V7((wE<m^I#HAcq>%~Q%LsNtJ4GYe@Vhsf{8pVxnAWdQxxdZQsYv}f9
z7X6mNv=&iDcW0}3W)xWNi~E+L)Fz%NMb93HZgU~5T`V)w_YfY6?&OH*5Nlom_(<$y
z4TX=z-{?qkr#OaExu1vw&V%KtxVsPf^h~_59YUXrqsSlrLflNBC3z_xIfhb~c=8-d
zuf#LUfqN~kp-A)_Q9BIk--?b_D7_OcD5JVtyz@P+Ki`XO259OLN7MTLgP1c2nm&py
zbbQ`XJ$M<q=A=HIj*_#QrB$VidXED%xvIrFXxgXtrt>py>U;Acd%wDqmRIiTm}aQ(
zP@5D0;Hm!M17sdhJD&sbQa>g~xVIWf19<*?)c!Qd98^yyy@%A3q9Dyz-9QKR{nVc?
zgfxG34u$0d)ah?fc~~9o2b+$l56~_pP(4$F(ouCFef1_t?MP>dg4NSzqW2-{g$yhV
zRsTvam}BZK^yQJ`>Jfi}B}_dHN!x)-(iv;x_ueovLOtIZnj_VRXnS=^J&^MJPOHa}
zv+|63@eZ^_sq21+*l2ZvEp)}GGxvj>Rd=R=Ggh4*0nRw}9v=vcSFaUNN>Eqah5?D{
zcXI(xQag=>0m<qe(*ZcA{@e~MDe6!oJp!rfmxEE8ranyf*?IM6`KU}+CzSx0q4x0s
zYo^+bT<}@yP+E*+tN+S}`W&?t9Z1PlkBkQ(Pd%px@O<?ia%fyo_t5Q9pq?=sl^4}%
zM^L(??rROsLiIHXDle-Sd~Jl#E9!X%(Y34U2PC^lJuU(xU93){P)CWnxdm;d>UUa{
z%GARtV0}%!Y7lHHSHCO)XN9`?1=_Bw|Lj8PhI+*asK2QmHWTEQx?~A7RH~Pa2Cho&
zLw=`f^<F8AsZl%qNyj~E)me@hsN3o;dV$<gM-ByRo!V&|@b&8XG_noq4P&9=uG)zK
zuu=VC0BmYf`&0D$o_ca8%x+enr?WOK>Ou8T(W;(D8=L#;m_uM`Q(va2`2+P6a^JSA
zD=5nNQ2kv8Ih;DwKQ@Brk@_NSA0DgkUV{2gbrUTEo~SE3QF^M@l9*@eY4lEguI@$a
zju+}M+Bd&ckEWAvUFrf_OuSMbiig>+)y686-l$JFq4ZXrB!%_w)U##-*R2kqZO(i3
zl_6j;_NeXX`-dOYHAleuQQiAz@HlGn8JOs#xvGK+XU!1}N-mmTAE3=ubMHIY6rkxf
z4|)%4rsbgRi00!kv;}JR^atRmCUp|pf;3|&bs$7D<PZR%n$?sfd`zPx59D!8tsT^c
z88tsuKySF_?j{sZXs&92KdD*R3ZW4iF9+BishLhfPiekT0C-w+`9Fv`qnYs;NR+0Q
zyvWg-6O^4Fqlu=)$XQLQ6)sb(rk&o}ahglC42aiEr972HP3l4bk~DobfFx^-d?SRO
z)6AgTD@CL20!h^zA;)W)=JN-z>Ac2HgYin&gzCVVq4|m2Dw&!w<U`NWNbW#(wr0mC
z(3_(fM&Zv~&DvpT%hTX#z~i7<N&C4An)R(<DbS=+<weaRZ)mur*=MwXib734%9_2b
zNw$UhE1DkKrd`!o?1Gpg&C6|IE!KEGLT5@ePrm^v)f78GXqo2j4^V$iGq^8gmuos`
zJ6fU1^8>lANj;9r8yZu}Fukd1s08ON&HgZuO3fuYTw101qk$Gd)tY%zz*?jEj9e$R
zno+bFzpbgG-rv!5)5*v>jbSWos@DWka&&{H=n#b7)dbNAiAGIwEQB^`?hS)Y_cSZN
z2Wi$Q{zhL~H2diZZ`GWqlcV=Fr|SS{)AUY8<pa%>S>yz0*X&Gyw1*nb5}G<RbAEyq
zk2HHGf;`rIsD`vo&0Bg2Khcy}0RL1oO$2$SY0ZI!&ozT+L-#`C^%E4n)Oha00Ci~|
zP+G$)jcN)wUu&M|Vc{E1z5;sRYNpXD@tvj%3vOh+XzFdi^IlWd7t(q(2eyLsgT|WX
zfRCEOa_Du`UJHeVPTKN8C^>64(n8cl8=^$XRlCm-xP97J<aKb<Zl$#G{aOV@vfQ<g
zDgVMlYes%HPwkZ#ka<A6iNaf6+P<}@G<s`CQ~c6L`#DYE2eqbT_aW`qW#IAErjfJ8
zPaCrmEdE;OGPDI~KPA8ZVeMa(H*!SVMHU8X7gvEC)s~C~AV@oZ6yU*HHVI=GqTOLY
z2Sc?(=~(A6?HWCV9oL%C9T;ZRa!-K>*Y>8*44lxmTR_Z7?Oi$x5}`eO38hHwyoW%X
z(hi!2(rN7<<h(eeT|(#dqqOIG!=`BM>UCg=(RQDPu(R56<gkj>KBjpnPHVaz_Qq=+
zo`EGn``2d>ov8hMEm)GYMl(y8k*w`?57N$QM=eETigq8p^-{H6i-1qlMw@`;y!OUU
zRHkcvDUm-zTf7@2Q>!3HW|lUs7`SY08QsS@+JTe^l&h6d7FM3tE*=)<Yl9<Ec|rRi
z1d0l@iW3l4sI4(3qj*{S-wd!`)o%J03X8PN0@zlp6|(^>(JrBM_fqYP&(T(<y-l~}
zHSMQeU@6zm+X<Em?dZdRU)L_Ad;Ny?U^g_~)VjN%?UvSw{34awoj<_dDy=X1MXI%%
z7eGplcGwF#y-}+jPTxhkt!+7o&fL*{F#$aFS||EyP=nUc15J0e89gw#QTy{ul$x}k
zr9<{T?X!Il)2v-vgif?*H&EVot9IjH$h@!Bll!YpYe{)T5478FfwNt^^bL%8s9iz6
z&JOL<O%!l>q%BNB?PIO;BCvL957IRFMC&63&r@wVZS<dOk5LTxh1P`@eJ`~eo`ZC0
zr;P#bmG%uKKEKw=%VF;u?O3`nZ?!{d?e|Wb>WEUeb`~Y#zt`4WL#apm39XDiXhUkr
z3Gh){j~AuXQD^oXy>QZfPit0Z-Le)C7hU;MSmCO>Q4GXBoj;}Zx#>2Khr<235xHP-
z*C}ZI?V-yY2`Qese|=DSK=-f>W8tOCI|6{WZW{et1|Qwq>u5Wu`{I9FAzgeXa7JI<
zADyW6)A`am!(SIL1SSUP*3&tY!@6x0tUID}WuZP$w}ZTBM|Cp`Pzut$q?lc>?!ruv
z5MA37z(aK#=w>^nEB+o=^0@Ac4NxDZ<7pQVt_vWq!wFsX6qHWthJ6k75eszROhYkJ
zx0<p8PwCcCpHAyyq+mUxi)AptQMyQ)p`&$QeT`C#?l2wqIIA1^3Yubd`}d%0ak_RX
zNW5;O6m1E*oWS@3d{3-v0t`*jt@;|mQgz%!l+tu+iU6F~@$@*P>(0;-*$mxUaz<t9
zoc+<4EZtwJkdm#tLdOttbQ{UzldJPkp)Yy5M-HgW*Uh07`URcOWr!}&?Fhv%UDPER
zq2ZG5{T`4)U3cKLi;RUaC=P8`b-%fze?_|abd0-L7wiq~CA#g|P+O{7I}4>U-GG0=
za!vOt0UFA6N%X~o3SFljfa|)?Lt(@Xo!7t6cT=~LzG!hv_oW1iDs^wk@lvI8aRO(x
z?ht+YwMJJ=+2XajL&nz-dRzBn33%@4;>M#?r{n0{PrYuj1-jIrD<J>rU0t~?fQ>po
zx^zvtvM<4TPdBFnmCZWM7cjI%m)RHUTXh}%(fMaO#|+r?Tvtt=`xm<AF)-$(?$n<k
zUAmL>u6(8QoJ<4zTDOkYly7vE7l41OtEN-c?{vT3M_acph%z$Y>uQr>aF6a++G~B#
z?K=rEaW;B6IOA=UbgL%XEFFwaB->n)q3xVazr(O1#U>#Wm8mvgdZ9ASCYN?|={E7S
z)XKDZeU`ioSvEU1gD1x(iy}L@HuESLnP=l>N>|e63QZ#yY-AfDt-z+e2jrqn6@`K>
z*|gCeTWIt6YrwDA><FVPY114JV~T7>D8N!;Q#%HLQX6>%ILmC#^g-n{o5T?Sl-m@+
zFK(1p*aVEj2wk@+rqs0?Hs9Dm%uO2!tz~c7lu>N3(q?)gN>w(KwXnO|CWxXSH8uhz
zuGiXJqYd(H8-|=ocWfMJWb16|H=z^tHXApCv%%&it;FxzOj>}-Mw?jzY-+Xnk-`_o
z2R4iAAiLdWuN7Dy+5~4neTU6Sa^yd<DWZqzv5h-<T03pxeSmmk<NX^rpV_?W18L7~
zyxahPVIvs}^3nzwG`PMtzR6&DWi#h3?0s$Xi76`I*z|U$%WE_B5sZ0fGcf^HbQ^72
zyij~^GyV!x^w`{|RE7^We%7e`XcII6VjT5rIzgQDq8@F|`jCCl<f2#1hBR0G8k#8g
z>3?|!7B~GDKcaHK{>%>`?)uRbYV*)L3h0Zc{z(Ni9MA{(qS8x$Dh>Vg)*Bzs2KCV!
zXw7p_?^*@mA^qlU5bCFoq9jIt{bBk(Mu2_;1rQGF%a_CMBl@!qxLE@ALp;H9RPRF*
zN08q97BmIx*HhMAh`vRIwotv>65x*M<H?_QTyOgoG=%9(&HxauPczc2eL{bgPWzwK
zYbg^dQXd(C@j9hnI}iOmt?yO?aYpa^3x*_0zmJ@ZG5WX%z{Tq4)7v9XZ${CZ1pSPa
zAc^{3TfmZ}f0GKm$@*$~RL<$cXoH=iUv~o<()4|wgY&%p{91Y?rR!hPlb)eBc)*HG
zec37q&C*AD!^CWTz(|P6(f{a=Qm%gf0O0fVS8t&*U;kK#$_sj7Hxw4=cg}>ci+ZmB
z7<x(na}X*E^%-h(;<ElTx-YKi7g27@RsHqfA*Dz^%bGTrCHg7v!BeV_@CKqxKZ1pA
z*YtfxqExQmNG|CL{bT`ya9yvcMCCjElGBj3-*zZ@;5}?T$#dyx+vJG0KwCG;vIw@F
zPtNvZwr|NJ9d7%oKj0CzW5<It%C;aDmC?55H*h>e8e{ud4WrK5rqJXNYpZnxPn>Pu
zR9F#j>qawcf^8?cS`uyjb0H?lHr)lom25kRPKuwiJwU^qVrxf9VX3yvmr#G+cJyz+
zrQ433fXV{fayr^`(RQ>saOJikl(AJ|8*&Gn#_P7rRzU9!+ZEq~=cetR<uK-!t@TWF
zt<rWJxo@j%6KVFVwhf8`zQ%U*G5~9B&*#IK+qQE^%pKbY8zHpLcJW}~>TTIp;2LZ#
zPona!?IQX&ZH=}mQ(#k*t!)b0?%CGSinzsSJDbiFwb~BPf;1Pq!w*pFYB!Ol`F(cf
zn*emP+ejyBLhWYG0PvXIGYZrkw>w6w^)NezLWJRVbH7IEgx%!-1#j&*+6hP6ZKQeR
zwB3RWkdj~*ql1P-yRr1$t|Yq^mS{`1Gur%z>vYa;DY+a{?0OZVlxlZtHY`oE`_%`U
z^6X-1dysE8+68SF>~8BpO6*qWL0YNZ+xZ}6c0W~s<(l0LihozwDJZ|_hFyQ!Jl?cB
zpn)+Bc3=6y!n=0av>$J@TS8HRCOa47GH7bHYghy^Ep~9-;U#9bh@#@J>`HzB>ub9$
zwHT5&b_X`#`n<K1((Ad~?g`!N@9l;<qpinoxdloe>{|Z=+|h8IUZ_q68%o@CHnjc-
zD_jii?r3v0IEABfpJ8qTdhcdfxr`QP?uJS_`s`ttUjyQ4$l8t0958I@1G~Kp-ZemY
z8<zb9O+E&OA{_?}U9@oXHEgD@YWW#z&!f%X(D^6y1{faVww4|?U_Xral;PCp;0!e6
zlSAvM;qpqf1sg7r+c(58b+*YOTv5ZnC(wA@Fl#i#oHqQk1&wD6l7-L|ZJ0+lM2x|;
zH%P4EkOm!%H*BK4Z-U`_dWR+&Y-#b3WcY3!6eb(`TEL2Ph6{mqrC4JvS_xdb;p_G2
zZ-!y5HCVC?Z!@9ck|BcL%Y}wjlsJCbu)_|9UNNN5Tl%VD!(~(!8Q#%4s@PC1L1n37
z|6)ifGi*7Awrhrq`Dm*$6cxdwYJ=hkMBg>YDP6VEP-O=rnhZmXv>mx;I8~2sHyhs4
z+PTFrtqJ&61NR*&?;CtJLrj~Y7d=}K3`=<6+YR~j_&qetryPV1!+{!bJ~F(whZTo<
zmpx&j3O@sTwn59F!7K3lvl9WZ&4rmt&w(q`6b-VE*=DSw>&)z;wAcO2(mg1-GXX~d
z_Fyj2?BdCsq2WHjh{$S|g)q^yOiyK|oP?!mOdjp$&odqr;7Mnu((RGKOgV~DCbNa|
zsj`^w{{u@l<8v7#hxwBME|)2p4}<fV9jlD!em*lW7l;c?$LHWFVAP%{U1Z9l&~}NL
zN>Q>B=EB-uy<}}nZ`!B2vds;^?_(GBgF-hprVEw(*?}a?o&6;ZB@ecpa^gJM*)$Ox
zU{~!%r5Ee+JpkTpH~Bk#*gcEon{czT1!m~eA$Bt*0r|4c!LY)Q^?<ub7RH`M7(;f8
zZNN@i=El|2cpu=B5agEma-*g|_7N_=FYFEBj#?`q96#U8F2e6|D=T66gyBBm`L^X0
zL{E$e#A!K=(Ti?5hoR(ncW16%Mo(}cZ753Tnfcc-W(7>zC;xW^g}ruYMj&YbRD9%$
z<xuY^$qOZWB@Gtng|Fm*14<`MQs`*QNt3bPL3o7849Y@_G<ibKvPPx!23XpZ2k8Ju
zr&d`;zMwAUFC}1ouUtJIB^RsCPXp(aGd9M1YfyXIs*zF{&sYuW3yo1$BPj7Z+Ug@Y
ztz)ca&|3AZ)zIJ3saUI}<Ytbul2IO6ywwkM^eMq=)**B|#mZt0IJ2y_?gJ^X>Y55+
zMOMqnbys2KFc<Jzt8LwodE4slSxC8Kb;)=ItaVmRy`jF|O1T82)2i<bus*RGM&}Wp
zTJ0rA;4>=)g_56Jjf;cA7gjgufd5OYKSn@rm(|5S0KBrw^MJ6|RyTHn<*n7JV5om*
zRZWT8-ByEMpz^)d334;{SWToQ?gy(K|NCd6AFY;r0@;q%qiJpKWZjFhjh(H{+)>(Z
zy>Jx7xLaG33(mv(h%<nm)@NQp%mM4DkGKfF*1xx-5=%sSnfY4>m!mSk`j@lNd)Rt&
z1B69d+sD$tTGxF;BWm5d0)QlI=Wbf>r&y2Nh#qEH&+h<hops4bG}c>Zk<h!=tB!#*
zT0d9~(rmqG3%cE6t)RWnTkC)h+$N5y|9B|$Ql0w|3cXcRYC(cjj2$$Et1QOB>@zB7
z2`b}NopiJ|Rh98K6lJS!%%SgxT~vK=0=`()M#*W{RgGVQwMMnc3#GfN<HJGjt8OHK
z<*~|Q3G}{HjXnTlx>c$O8YjM*ZhsGc9L0+~`B?IC9N;-uNb%w~;>nSE^S>kl;KN@o
zMB71r#R^=eLwr8{`z50<f8aED{CMws7$JZD8HED^_#f_|@i4z>0DwpMhf^UfkiSt1
z;8EU^aseaxE%X?l;+-!7aGKviSt@7vTTK|sDBhMl0MWd*5mI7!yWe5`S^lC3&RD*G
z6i6K3Zz@>gjl8=J5DEOhq3Bv7pG5ATBtC?;&B=VrN04)T-diY4<-hR<XBuBjp{(;f
zUjRTlKarxw8GQbJkW79YO^#Xoc-m)Y^V!tV9RAHj^emTOoC$ay|MME)^7%0Xz<Gf;
z+6O>I0snIeYA^DQg8{t6AM(YJRPcNl`c%!U{)6lW-rEU?R(@e0Sony4MR`sycy2i=
zyZOJTLH2w8<SlUa@b)7C|G-Og(e{yFNn2b;A%MO@;Uy%RfW=#IihyVzL2DcZo`Zrh
z7D5jRIdsz3SLmi~gTEkM3!4Ij_g;{8SYRguk8F==00s)lCMX>h&NhOa5Q-&WIVs!<
zLn%UN?t!pKA!jlwPYE-sA?392AQV=d5tI*6iV{wI0B4La=Qugk&I%Grhl>?@eT9LF
z6E;x}R=hBLB}OJec=iCSi9*F@kR-w85`<<7Ds%KVOQ>%IJXiR^0NHs$qa8@G@c3s)
zDG`Jl;4Bjw#{qXuxH<%-YGK)1SYIO;$e7!Le-wR0{EiSuk7|qXhYr$O1$$bU-4_xl
zFw`b2ehkwd2&eqer*`2jIV~Ovc9hZEA%xIt{*myKrsK!LPn!Vf6mn(I^h99C!HTDX
zAp)gm!Z1qlelB?Ifs_}*b@C{83H$>3N29NV2nw>j7OqbK{*5qh9>`mvpdWhpPDtp4
zrQL#mIW)Z&Sjr#h5yoGFv=72$TKIkxUiHUtIf_lc0_P-#g@MIce3K2CF5-lDz`2SW
z^U>xlexS9YkNAoXuN)Mgri0UXNVM7tX@26G6?D<X?k?CCAcpsbrH92*+IXH6zb3C$
zgcwIGk)pg1rBmXSN8mgydLM?+Ga~;TN>So_a`i-utEzyD5pTr6`m^GqLuiW?E6#w#
zi5qXin0V2y1*Rn!#pSerO%#`64n)R*9o<6bMC)M?nj$Liqm(L+`vRpj@z`;c&Wls*
zF{J6@rDecnh!bcY%oKge|Cl9CFGE|lSYeCG9C1`QtjHCO6kX2~-_Qlk7kwwg!VBWK
zFHu<_8prhpqFj7R`|S!bZ!;Qih<jrIyeS6sM`e|`olg8$i(xdDkHxZZ3|FT(cOXc&
zsB%Kvdy%EgiXL(A9H{spZu}XQAH{2q063~uJPdVGdo70b&g$?M=yg%ArJOBS^$g=K
zDBP!>L0&#L_4;{e+^?=22x;!>-v&X9hx%9gW~-;#<rqp{>i0By-s*o%QR$<eun@R|
zYT;+dKBS)eIof>H7cN1zpZe2kwE3%V(Q&T;b<Zwz>9Bect-Ft?4FM=29`0;}(4*?L
zv~>$o8-GG=u-btRFodW#Ql>(bdIPPGqSbvTqcTQ4YcWb^)%*X$6^T`^q7PNXsq2RV
zo}hNfgx*B;s~6}}l6o5LDwEaUl){R0YEM5XN>Q(&WXtd`Dky_1`HM#m<j_9%#SV%K
zyMHNJ2o*I$J>*c)G<11B#Pob6(%S9ASCdbp(r?u5WgtgKO{UjX(5MC_WQUB3jf1q5
zQP%gM{?e#LlzLe>Dry#3N=MD7C%tXdMp|1(jkYg0gQfV{5KSTMzb@aSHRQ%YpX2u?
zl>%1$-Q0%XJBw*yW?$(8`MZP)U>%vewEuTvjJHv8X2ynr!IO#Z12G4f%u-n3%?wU}
zoWqRScMx%e`END)dYqYY974jF%de^DOa>(hMKR^%w~J<et}_A{!^G2Rr?bqeQ4o5L
z`GO9Dr!YZuYh*Jyt5M2f0_Z8vW$sr2n8$3VT!$j&&H%6!Gc#%+w1gQ`4;7`%{tIZU
zVk$p_uxf@e!2r}ShiHDPWePn|*~Iu${N)~Fm`VY?W+wj<@GVUHF!ZpMv3G&c`^>MO
z!tOSPX+hfqW(*nJ&cvQZ+cW0U3#fR`%%?~H1>;Y?u9r*$eg31138tjE9_A^%|2{Ci
zr(=LVG7F<&g(LflA_-2cDJ2&=vsbZFF-l$7m6R6f%BGT-ee53EM!B&Ww7=ZX)`vp9
zJL^s%9uL-GKYHlN)}918z-CPWrx&}A;)&jDVms{hVPAa#a**Bb4|0f|Vt|Fd>~~b@
z$IhS?gFhR@Ls$T-`UIklhuK9^@El>iDA*s!hO9^9QMPhER0Oe!6JcpE+g|`n2z$m4
zHifcLbaLw$Yfmnu<Lr|!fIH3Nt$^1ctIR`X0-G9yz9h0uu>d5o3toUFnVmtW3^UnJ
z+fkXtrnJ%JHL`Difb1OhpLNii%Wic9{xZ9RKD}^--RTY1tE?$`42sw_+kr1;7ySg&
zO4y-00VrkH#Y6TTwl|U!q;>3EHwdd|U6%mYz;2ofTodc^5V#ih9wpqjvgNehy3b})
zPJSC}{N)$AzHHoBnBUI2Z2{sTJIfM{9qgd%XmjM2?gC;zw~+^n4>zbc6dvXteUHje
zZdMQUMsP}6o}T6YrnK5v?r0=P9M{|rR>X6?r=pa=?WHJRBDdutEX?MnG(bZR=VyEa
zg}K~6ePLT37g+<Id~Wvt+<07?66!B<{|yD=5*I%Xq>vks4sw~>O(DE1ocu4yzRFqF
z0)C6DxdtolaOnm}xyNleh_-g_!&X#2<>p@j;5BC@gWeC^e)^i5n`F2T`5X63e*K6>
zcgcT~QSy+?qJ!(6k}Nufb3ihRTvuKa%V{Vbl}zn|y+INaIwBA(+4%%wLL}x(K|&=p
z6!$qM@tF>m<C0@*fD4yY(;MQ1B<%*q;-utn%3h9;v^)oilyH0L82c%Sn<d>sl3%w0
zm@FBtguxk-f#g8Tmu&tXHeHcS3<Lg}B$V#iN{QW<&{QWW!@Eq{EcxdhDmx_2<l%oL
z39AO+vE=SUlsY9}(XQ)>#BU3_{Zw+N7YuzSS@;hC&n4kMk-zbS<n&K4@uTEZTID)Q
zWkImbNt#3%rOx<FC`@yanw|#2761DeLib58QR2aV{Kqb|xl8-Cg409V9S&nW;phQ5
zfWzGYcu7ang2!7rHUk=bq>hx#6)1h^1eT-H$#l}i7$gl1gP36H5i&SLnty=C5?}lQ
zIVM%mY9>tjE%G0w;rJJQ5OYGxIirUsrLV~+5rHoQ!k9?u_jJnll(d}!r}5IQH^7o0
zolgs%MCslMXiLJ@9m0~O<0(FU4j;>gh7_YTGXY{!rAA7$J}-6p3WJa?wWEDyhBTc*
zMwwE1BlKoTcm0Tw$(DM#Lt2h>-YQh);y;H#%oVBj9TZ-bb|eB&Buyp1d9if;K9CaW
zt`#7q(iyb2D3iXTl+0_=mn(1y%W;Bw6!6!jq1BLfLmEr@i#Mff^I`WbsohglR!SSP
zP^ywzr2$_pP5Ke`)=0zWLt!ocLndV3#|{9bO&T;5!X8M&+QHc_)u*E`52Y6=%-ta!
zr-10k(ypn1cS@~&!TCg5Z#)B@r_$o%sC_22sQ~M9>D+ke{U{ypgi1%5turijlAR{6
zsk5xs6S7@oVLQ;~D*Jad;QM4hAB2VbW$t$1be9e2glrGly6;f(l!ene{DAE6aLDwM
z9se68Z&_hCtPhq+WHkSU$lhh37%JONE6QWCNAwsTm!(laB}`UI-sN!FYI;&n$mSk^
zg%PrxEXa<OdGtc*lq}>Qs6Q=R`3v-(k!4fZElTF_0OK4j`|KcaF)}TMkqTr<GjUxn
z%Jx$9tW@TnN9+FvS>z+s-jzi<0MR3>rr9aVWc*1;yJRwHEu<BiO!7fxok=@6Kkk}r
z^aB2&$q*Zu_RM5x8gOq+8d5M8Z%roCw<SDGCD#D(H0?vt>HyQavrr#qT1Gp$B-5Wh
zU=XrRqqAuKyJXs<Ms1zxSUMH+%ye}SgzlG5r$~B$Jh2Y=lk(v*Sdl2VC#QI-Je&@p
z7s=lbKxMH!a0GA%6#dOn>7&>-1E!(Rbgv&$Os0LTpJMUnsPtDDDPQ@p!gnQbM--)9
zFxwcch<5;Mh~hh2@PsPj9)Rb#qJIEP3{#A>g~AAh3B5`q6@6>~Jf#>%%c3a71_khE
z6?fL6End-F33!s?s2A)#r?~bj+ENr5ThW%L7<L32&MUs7jDd8;E4r;R6mj%~mlzfQ
z*@BiS-jYkCLXlvG#+wS8b5K#K$eskD)rzr3SW&CEMX%sG#b0!jHYtK0gT>iw8y(Pd
zHA}gIlAD<=xzXLtN-2TY$86s=a2_)IDG?;VEbdFdkC^G6V@QI`uFzy0YG&N>gw})j
z5u116_k351{Ve#BQtuY#(3|bI%%S*u(K2#BEl#H7)Fln{`d#Wnr{b3N%Y@YBYl5I+
z#mHq)yK-DF{9a}E3G7;(WQ*Tx6oY_TTa$>6{_aXU*FQu`n%XgK7k!R%XXBSB*q`x*
zh+Pj)!w3i8Nf7$)O<HX2u^)!N_hxetWE@4~>BMx<Cykt$>6HEM!d$ii(3?4V6UO>5
z59sxOkl8x~r9%u$#}a~=iNnDX%s9@4q7dd0e5=v~roTO`GM;D5$)ldfR9!%)t}vr$
z6<p2?^rsCze#Fp$_#MW6PYG$^?87_=Ji+cGPy0#M=LnQVuwPcf&?vTM5-OwF-yTC=
zJbSeoIulrV4oZov6D2>UvMLUxG<M@;kn?Pj8}&b(O`<H@9M<X}5V@>;FjVBR{akQ?
zF0m$mLwzB;lv1NEvk67uEMa9X&|AueQGVEUHf%3gZm^ygVEIkfhSp5C*b7!*sbxdI
zN9i^@*cYWctTUy&HL~TsP-<e|e?p&8y2pBb27EJX|G!l*yQmO)+u2a^gg#^!Q!eBa
zc5gl^U$SfbaPhj>&trjq#U7>`rknNt6nY)GC-i1}AwO{d!`P)*iKx>5#_t33zgO%>
zCY46Vk!9)Np%XjU5gl=62OIkV?7~{5LYphwa2jMEds~4<H+DOv>+NR^+b|yPYy&N}
zJ=i1RX!B%;l2`KpyY)7td9gi|>Eg{6(fsJcMm~kH2iaG8umrK+y@avB?3r_D3t{zH
zXgkAx)ec3`?BH8?tNwqN`Gx`JFIc<~%nRe`>HY0+1MrJFKf;K`wJ%V=WQ-$BSlag<
zL@YCqV`BNUHE3O7ngeMonSa5*YRX_(w0bms2WgFP4Kml3P(c3oy@lXk_a%8+{s<oq
z3G0KLfinJmZz7a!TSGx<`;#;`?g}1+23O|EOrZBM|4@##8{<BQI>r1t5eg46P1nHg
z%M4J$AU{Ud2Y?Xfodly0%8b8<5jw_1<iUh6=Fs1$JjsNTmQzfs5+sV5NQWfOGHyT6
z{wJR4O$m|ZjGSJ%70h!=rnt@s<<NA438G}>n+)?8N;S-~3BcDgOK4MdkHJe6_Xra}
z-`MS9zRm>h9W&q#Sb7-67ZCQ5**qSio!I<OAtj7;_d;bFdvEXmZ9~OEqaIdfFq1|A
zl*w$|0K2jnt8NI)W`<CJGKb+uf#fo;>C-!TjFOIs=QG!6lU>9J0xT$IG7AAOVg93g
zqm-$mI93_sM3vW=BNVGGXTm9cq=J!?Q=pk?8jBHYVS;BFQEX)bA3+TM!6e0Xo-nV!
z1L6&HU5B=}%tmr;IJ2SWVTB93ju!K->@hm@;muZ2!mkgzYXS5gWG7t)=TWvh2qcKj
z`WDwFm_1en62VTPEQd(;TiS}8VzVgw>NLA&C7o(ZVA}_xF_E<&1z-l-b{EEEvL@-!
zl*JCq13sI*NV|tZHihzcFS8?PS9pc>CI{tJRuv4~b=F}GWZz(GKLOw-dyiguw^&Eo
z*VMCPOVQTArkz6DUABHV;En9k_r37^H?cd0VW1we2<OtKXE;UQAF)2<A9~CVm<!U$
z9;2<-6SnD7;GeQDDY*5F-TW^A&)LpE*z|(^Kt8sY>=;Vg>0%Qpq5BnEu^XnnW|z0X
z&^PSxztFR{?736me8>7;L&@09Mo~uSdse>^(t6l$PomL_6Pkbs<~nJab%N{Jgw8~9
zlgOAP?rH!?A?Lgbm9^YQa)~_V3h6E3BpJ3DLXSx{&`g~msT>1i@+FfiAhTRDe>$vh
zkR<E`?uEo*J4p9pNn7&&y#gwvw`hNSTl$%t_@sW60n><oNQkaCOJCBq;J$S7POv<b
zI$wv<PW-!B$apT@<OR;xQm3V``JFVbKT02^e+C|GXVgYT2jGiW-3Dyw1O-sb7t%6%
z<!@=|?)tf#(7z2EHTb<ffVKrYoNDm*&LfnHYVR@zC`V=&C5|{TJLv7>!K|ccmM7DX
z95{YV!Dfi}XJ(MgD};I7h*Bt%vkYyK%u)%huTC)^Xv&Ra{`>{T#xv0rkxgJeRzv7{
zM)nNGq%#9(X3Svz3jjWo+1&$t7IXL&0NKowSE$TkuBJgsE^~etN_ottk2JE(;maTw
zn2#AC1xzW0j4v{q7DDtTCX+rKWGrN&>9um1*-4SfE6j-X;JM0t>W>Z<F(H(}TFf-{
z0x4l`?}my}=5M-b%9v9}VZ}9OAvx~Knau^jRWN&MQF)yyvP9_yv!@!y+-8#fFmiX8
zp>$HHj_J`rQ9ZMW7R3!lrsY1&xXXNb3OsF$`6rP5fSI}$Jnf8|AMg*EZVGI4Foung
z{fN0srzIaV{Wz35nHYK}B(euqLRuQ@PVbF$b^@g!WU_<Fo1V>zzTnJfXKzL2MfSrA
z^yM-eNE`ej)@W7^U@1G593tiHoOTTUO?Jr|Aa1kS&fsZgZ@I!WM=pN79JTln2T@-`
z+3h<(@Y&1^K##K>*B~g2y`2Z<aQ4~{P<?_e-UFQ{*&sK-BG~K2ur89F!h-V@E58L@
z#?!3l6lgiae*Fi4QEbUgAfnkfHbBI%9L+>$*-2(#jb+c)gENkejRj{s`^kNj5?EVu
zGA6QrQ1($0dt?XNlG$;zkv`AjpAAsYcOHkr3oO1mLR}tD=@P|k5*?r~F|wcC1y3p4
zcQO!_Y}nsWU&TgJQg=05l!Q_Zd+H*9jcoBm7}LbArrq^D_7XX7n%SH7AT6xb9spWd
zH#**WpLN^}TpK&P7&bj%3-MW3tXLBNf|Q5s2l5Peuy5oL_J}oZr<d|$_Usp6?PPzX
zvsq8rvQr?h*`2hSeZ!89fx&OtG5*l>j$KLKlWx}bB`V*uqpyIohvmNm`M~z^Lz^3S
zp*MzWKi5I8$b;POM&J%{Cgd4D%I(#FC5U4hQ98kWX(U(9N$%)cAY!=UP#SJ7i`L2K
zxTO?mN#Q<g1#33fNExR&+%ED07ILvw=*(sA`!68-3fCA2&I)dv4ajwF0QsYCaIM#2
z(@idC1vqbUedu|v<g&)1t%^Hz2x_ajXg~7r)^KfffoeIYz2Ldcy`2VQ?r<9osI22m
zDJELa`BuR01}=tjPVRF4w}Efu2Geuh#Eqthy@fkMQOs8EFzq4la|a5bzKzTK7PyDp
zx3nDU;B?(6J>ovnbn}=C`;R{N-N_jr0{@H~vJm7sm%0qHUvPh&0Ba9-#ueRml)U4B
zaFT3zi#BJ;#N{9^lI7dc<|^6W7o7Vft+D8+yClyNnmi=FGcYn<l20DO7;nk9C(#KX
z$w;~b4@#^kiSLl)&Q^N=MN3Xl{`ENtn*~I+<X`e8T#|G}fu~gBl8DL<$v?a4`bu}V
z!3uYo2aSxEY{@go_K^+E0m~8Dih9TnmK{z;Wr%E#3re9feAJtE>_cKfj?3P(L1ws2
z&coi5vSB~KP-CP_G>6dBvLy_F(X!v&P#YsNRYK@lnOy|hVr7X<0LIB;=%X|VGLw9e
zMA?=)kR;h{d;;QsuLU7&C76F}>jrYsBvWWy?5cpKCD#|j_@yr?pt@|&WbiECMoHT1
zc08q1vw!G<QTTK7-;lO`Vk?-oI(`knww07?v0Y1-YKJZmzjqF9fhPMQ)U|)F^nl-$
z8Lg$UXZBoyI&Y?P8I1^&VGbz=nPeLDL(Gb181KuR=)s*6#8lC&8O#*Z10I5e8+s*$
zGM+6oPE5mnh)!hw$bq)=%rsX>%VE~hiuocFwFRVzsif^zIWu_(hN+U#q{7BKOwtUL
z;ID6mF&#`rD=J?x-X@Ug$jXL8p)b1(!9=_ekGuc>sU)lHP;tn}v^zttFZ16JV1pR8
z4%lF3-2~Vi!ssYa9LnU5hR#Sv{}nh-F>`48iDSN?!?*FwxF`S;m<KdnCo(F^7D;CY
z(edpJCTsx)Ad?w&AC(uGQawtSn9GmQxl(2$O&Dd2aRTi^s+hT7p|+YS9Sdo9newwJ
zH8O^OprVOMq2z*l%(OWWbC%t01(sO$NITsUtc-j?@$7#k;7nl8(KaNJH5(3+#QvcG
zNoJo@#$E~Qe-?nd?A`&;7slmH014+_8OeQff^#W@ij&+FddecWeM2yEk(_=4+D>uh
z0{}eDxznwDh6~>UmMCt(81yijE8GiXVz_e@d^spF8;G_;k_og!^p#wodDc%dW(PXz
zFOhoz9w1qR)s*zGM4(sl5lNr(lus8ZnMw)AM<ox#PzsX7QLcNi#C|UHhDb7Lm9bA2
zKbv|lJG=#Y<7LxrP&y|YMw4%vEXoRiblIDC=tQ>6KM5?kvJtc)%9jnc2WNrot_qy5
zWc5eD>186EhWc2ON)4Twy<(D)j$*ON1AACeY2rWO{}z1h><8KoJ!Y-W!LDcQQJT)X
z*gySX&|7u|xs~>F>S_+^@FTcW2I{2fXpG3rJ0kv`6?h%GXJ=A$;-^FF0iI)s#hCnj
zZaeCK$<#o&ajyClz)Sd7Xjr<Q4&^R;MoGfUOCR9x6<<d}*~(dT>}%EfUjW<C@&*3>
z>m<eUw+;FYz1lwd1bF_lrX}Z|!Iaj$k1^2UJ~t-+GFtXCn<@U~&d6wY<-vTm0H9cA
zcsBS`jLZv)CuK5EDdd&U=*Y8jnVA-X%2KAk1;`EN=M30h!_1fngBzHdJ1Dg>$4pRq
z#5|sWo^~;V3W4ikYAA)%g?0T5I1kot)&H$ngowXj`ji$GMq=s)+D-0|n4;US8RPJ+
zFyjsLmTsMHX4+T?ea}pa1O6l9NXKj(*(*Py(uMs~0H-S}D}pElzW#+Kch;>QEdK0&
zagZFqKBtv=9Q)&HlycaZ|JU2KI7L;3@q5qRdqr_|ePF4mG%4vI>;u?^(k7JU4azIE
z7cR?+)WQP0i>0YKnv`WTKGx4kCm-XZl6;i5(};>wzNS$opCu?2h||MLLPVkL_hJ7+
z!JPTs?>pb?oPFGLzVmVUQF{2&G>X*$aK05wxnlV{v84qDuZmr$d|ZmGN9r7CHH%_C
z-fI_!rb6_l7#RiXXVG>Ras49p_SG(kBfMGuU8tNNxhLMpgn1l#bINs<GQ0=yp3=j~
z&b5lY3WHp)OnDPi9#9%EtcOdtYF=#piQEzlb;`3ZE=B(x*}ND&yX4Mw7}{MqiE}dD
za-9v#<-%3mH|%S#!sol<PCV?c7BhL78xZ}EL4AYR$2%nw`@aQqi_ouv`c`q1SF78^
zKAxxT!o(@ukHu~)++#f#2ZcJ(vxy&ubx`>3!_y&=%`4#}qLptNM@2(7Je?G=T<>s7
zoUg$gH3~eM0SgTg%?C19#dyB)Hi>oL!CJF;FdxioqU|Z@T^BocqpwArD1hGg;x<=O
z{va-%hx;Ez*9btX7*@*pr4I1}ALjij>KXu@LiA0E@NI%(m#7*6X1AEYhY|P1ORr&Q
zJ>q&RsO8FpDF|kTa%CJuwkollPuru6x`|+pDK%WSe?_U|k5!AZu^l3}6f<w>?kKKY
z^!=r*{u+|_H@km)fM`f}Vj7I@(cMY|byW8uuj?9h$?b@{RX1w~MDOYj4~4aN)G0wo
z2Gkfn3E!mZ*C3|tYB<;Ze5e}zU~bkHaE{~yZ8T?@w`jSXso$z~+{es(q_yz**B<RB
zuBNG5svYNC$zE+4e={7=zP}9Wb1iQ+q6lhXPH23g)x3=;4r>*ULZe=bo{Z3rYTvZO
zVT1NJ|84JaEol(cztl1xh5A?8S3{t8LVJtPF3)JGN1<?5JC}j5&uNc8k6;?L@+DBe
zpv_se<==0+)QP+ZOk2xa@pRin2xUB@LO(Mq7o4o(Rfr*b;4ob040<2BGxq(C-kF#A
z$ws+HK0&;Bzx@pl`33hd_JU8z(T(EH?&av1bA}5pp9}vK9nV*l!q5xTZot7yr-wqJ
zs7Zy<xf_21$1#$3D#i3VB%Kz1Qcp>9D=fHV&Irw`ivp)~%vM~_kIDqUOx8p4<#*$7
z{YvM0^t$W$jZ^LqfM1cGxe+W+dn(*iX0%~as;*r_DAj8^aP9R^0)IghSEDS7v4Ou#
z9>HhkZ^?#47-^8P-<PD3aIHvtHJWx$wj~&oDl6S(PKU3|Q{gq{7i7m;ru&Os>B;sO
zM`fjPx~IbDs_=P@cBi|n((5u-y8WePkfi1w*&b2uaC*GfxFT~5|5{9zSW}`o)@-#{
zjXsaZ?WLH%<Pk|mh|Mpna7q7zGqUu^i~j3TrS!^?|FMrCX3lw&HY9`&r~Nhh$l%^K
zarj(t*Jp}4j)HNa6E|E?9;tnBUP05Lsc0HnKeUkGgY*4;2Wd^47!$0m9gvYv$Mf`I
zwB$2oQZTG(!1g)8mblP>J;hk)bya(fPDi!d<25FGoc{8@7dvlOL7LH9>2SJ=d@e`1
zae7it^mIpcNl~_^#P4<$<$LD&7C5S1#$;EqzmyKtslzF;Q5{Hg7x$Y$gH$af*sw4(
zt7~XlzP;$#q^v@FM1raBr?57(YG5$5O20;>m8bg|=*6>IDE)eMz(lgOXyL(*8vWpf
zqZ7@RXtUL1niOF+$Hc~%Bk<0$m~3W?Bn3y^)^7`qFguGKR!51|VKUhg%oc|!&SFb&
zTAcAtbFsy0wbeHD>d^)Tn|cS2oSJw9Z+zV5r2e>p3*4zuOerC2AXPBxB`Lr-Sdxx0
z4w0k|M$|tH4n{v|xYA!9PinGZfjpTO14M5KbtM~e<Ycnj4Kw5w6kv#>8w@2Bp8{~x
zn*gyRoGzyrazt}DMW#YUNB&f1kD-$f$*{CORTn_ikE74iAl&vCY3Y5!h3V*>OgkCk
z=ng>C#ZyWKI>RZD!Q?4wXL3BnXR=|9R%U|CqDxHHhfrh|$k)lA1@hOibdt$r3d?5Q
z$7o(Q$PzjPk_VXs&`}|Sn|1<3?<DHVfy`#I&*<w6Fu3Uk!)A(~37O7VS~(LkE9eqP
zL^dH8Fp&JYhA4RqZOb)0F0ZE(xrQgySvnz&rQ6K$Q&^ti2~qzCJ)LKW6c-a|9#9UU
a)nLn0=n(hz_Rw{3)q*Dt5>b`iFzg@O%16!s

delta 126706
zcmY(r30#iZ`v?5o&vviRzGBACU>N(pk9F+E490Hk>)090JZYg4sgNZ~r9_Jotz-*j
z7m1<;k%+P+h4*_kzyJGw-uamO+~>Nk@AtaSxwmt!bDmNU_YVl`zoVgiM6cM!!#Ia6
zg_V_DXJnG>|NozYQMYX)%2bYx3Yq*zdv9nJ3>Q<6mnr0`o@*2`m3J&JlXtH(fi!Zq
z!wF8NP^x0Ta5B|2Usfg`U1vFIl<cSWa+!it<tM;^WBc4^WmctX!O~TvoAo^ldwV@m
zrm&mZ!(Ns0ogh;*H4mrrQ+^!Zug=?J3fUPZ5dw~x(wdQ_)t*aCcfXmuty?=6h3q_Y
zowO~q@&k-a#snp^GQFGtGRCbPFEiAhE150h1(~t-oMX=W9p{^9Jd))yYpul2H1{ju
z+nCq8i?TZM7NFspHjvBZpg8W=NNA!ten%y1DnAWQJ9EQttkCGkPD)PJTz;BN-G7t&
zDr7R{fL~?f|L3^LXihfae~!!i4hXh7%GJDVQmsVKT$s$rCfA;unPR`|g01)6@r-O*
zt)wBt{-BaguRU+d_;nU#Giv>|VCH_1$!6Bd+c9I>D`bDxo_AvA`ZW@5j?%ko*_>KQ
zKPF}|Bb!@$K9C6q!@OFCp^W)BFPmR0AH%2;<gx{|=f5##j*~5{J)g+L!hVrF5-pv=
z45{K}i)-aG7`0X*TT**In@NGq(pt{>Oi~OZ`%9kammnG(^Xsv)<+bv4%*kKXvK6)V
zPRyE*3faoqb5|LE%t<9%C2x$r)zfXIN;-+YQ*Xb{%Vf53gMO1SxKEU;N|^uD>K_V7
zJyNa2@%>+{j8PXglFQ`kszjv>w_$oi$XhE?VPy9kB3T`u|6ybuDSV}n&{!?&LZ_VY
z&sVjqJDp0x#^owmFFMuBRHH}mGPaNW70|W8umi`DpXIKIPCdPu9Kom@k)n(pBJT->
z_)W*isu>NyGAsUP0^A^#CynPIZ4(5E+%He6*MkJFm=?7HpEWY$-6twpCS#(O(0^m_
zKNIktpgn>_XgbuM`z)3x`L)+HY5r4~LKe%Y$+T0gX>Zm4Ok<fJ{y)?8n)-umE#<O(
z|Cx5EHQn@oru&%Y|Cz3;jc*^*B?ty`pB3`Qcvkl@qo}2FpXD-RwcjI69S23Smig)b
zrAHIiGJXETER?3qWMqFchW{{YWn%F-LDu{~zn|!#3+RDxYg^NtY4#t->{`Fgna<SL
za-SJe?q*Tef|35Ku9EtySy{{ft1gpEAN|&9>)Sex!zB)_ZF@I#7ZY$A=jI-Mk=lCS
z6G7Pj;aS3m|F5=~{dnT3Hc>v}#%PsH@jcJNrA*-`7gXlSlhiUrJ+;c(buaF$?^XY)
zTp8tmCt-}JYPj|zY#K`nUZWDW)>X(9l3b;}?)Spbvu=+W3Yk*T*HCNyKTI%VRMn05
z>uqeH3HB4A4reT?1~#SN0^<^<kKcV`S7xH0&eYD)cse8d52I8$o|`$DQijW;lBIu9
z;mDYHsy<TV==B_Tnry%sGMF$)j$^|r0mrz{WG{b3He0@sw&^Xx&iIG4+h>uy_%L3g
zvWI8zx|TgVO~=g(=%{f75n$dDI#xa>(Ow@qf7XuxqjT{1$bO6<`Ed`Tn>>P??Ua*)
z8$C(8w;M^=uN2U?({$Y5m+Z%c6NC8_q2AOX%Y_vr={1keGotAH#?KA{U$7Ev^Gt#b
z_a^r)*%Y<>Be^;9fJ_^FBg=-1Nn&0{mXmr@f5_6QhdkVg;btyb4!%k@Qcsdd{pq~^
zHFBx=i|jYOB>oAlNNWvLI#8TyOQMmp$!OI9Qq=24?uB27E)}m-mF&ttERN$h)6xGm
zNeUa1<=wSp6MUC~SaFTCehI{Ly$wlTz9sE<L+JeDYU+stvE*w}KJjaQ6=e=|&MZ<N
zY(}QDjC6E4NTwGuDfT|2iB8jw&PR==7QDu5P$d(CNq((_LfL+o?DY#szQBvZnwU=V
z`_IUxx-s?Ej$w4%@{%M2meBb_J=h$w;7kI<+bN>qrR3&e07-V=Afuo0y~I_o?TK{U
z=PKD_calt9L~ZT6g(S01lI4PMV)*q}3S!1_k~oG?Sar)t(xmndn|F}T)7lb49=?>Y
z39W5MbvQZR+luIRwk9H8qMkTa+r8~p(0RQHbgW-amgaSIe!e!)k2a!fWguryE>Y;k
z*Xg{=O$sr(wi$+Mve`G8+&|Zmmx-ywV|VNz(=#!o*4Ex=iT)Iq@g^PRDHO`e+6QS^
z6`l8PK$excbROzQHYy)-v)n+AA08mKH4905y*-7vB$l)#k#yC)`;g1ZVshWMw%Hn;
zgN!<jC88uBI-fg}jx`O)D9oRZ^YK+x$p*!cjbAEh`!%EUjthu%U+rz%xVBAm|0Ksx
zw^9(hrjfG+Ye-Vqh)^5!B>Ai*ZRL8xUKk?M{olTvD!-S|HOr>anQUPRxy=2M&KD^N
zP&S*0Hr^%q=qF_9_kxadY8@B6Bpa23B)js+P47<B?gKKCC^HGwEuVUBl_zPlejw)V
zX==Lvqw%f8-K!$gNnUi`^eQ<!|CmVqu2IJhc}wSQSfVKZn<R5~kOLuy&UfQ|tdh;X
zPS}CF$uf8{ox8myt?4kiyxoJ2z1+ylzBMGzX$CJ2S=2kaDN4qY=&g~CrBjIR<t927
z`Vyd#p5#BIlKUT`sJGg8A@`TwP&>vt5yOZ&B<VGYB&8nY-fs^{W`vOBiWj+WafceF
z7KqvB6loncp49cz$wB#OI%<cI(X6RtbR~^kwtPx9L$=Yec|K9k5y_@=067lV(D@x5
z1sYoWHnir@dB!oq26A-#^Aov0d5w<VPNdzog!;+LafK@NFHoEAk0jIgzfoMGJCQDF
zKt_sMo8eAmGq;lDL;6v0^OlnK)*(86ca?(kWXNXNJz`K7(|Oyo<Z@+GLMhi#^V(h|
z`7bTVUafPG%O#sAh{=t}s816*CjCrm?O<wa-`{IHe=f-vw<d7Y6+}9B1W6L7(($Kq
z;)&iv=du-qvQHq(pUxBZPEQK)eifa+=|sNj{X-2nx>HT}|AcAOjT7pV%Ux^feAB-~
z_alZOaL|j0M$`uCHH5%dGDvF)BWJ5u6H3>R<d-AK!Nx9hOqR&zP#7II46U_~A<H>k
ziEYtiazEWHr~7~ASR!(IONyf#=vY<zNp<^`S{YwWK|Gm8UHWes!S2_-A4{H+n=1iC
z+BJq4o<))UuL;!FG)!A??GwrIT3?dSsUe=Kr^H|Vl~76D!Re3<o=1SP6$JQWQf<`z
z2=M!H0yw$Qc~$Lq!AVY*9cNJxtulxx;SWL?=TLAz$*JdloJy!;OG)x}8)3K898uQq
z7m}|`rejE5k~gdUvJ5=zAfiJ(h*~&9#{*l*K|_q)RkHr0=saaPwQq(KfqVW-@}@J0
zV(vVmR_Xnge`j@k)G1|ZS>I(Gj(_0_sbvo%D2hLQ6gY1iBj8w}XK{2HL#@>MQzyjx
zlD(lL(JAhen_p|MdYcz=$h+rKn?moA%X6OyJHMPbx!Tui$5J|9ucKo(hk{H4EJVFk
zB-79HDfZ_UB7I#&4h;9ykdG)Nz}Hf8P~4R)7fz-SwRrs0vXWL5Xs2FeIcq2N$Cwg4
zC^EOMWV7ZV9m8f&w|gfO|E=2bovv=}K#FxHb;eRsZ0bVb@9NNTDaJ66Kc!Gs;T~4Y
zx?+f^mQ5c{E{z8WH5+eZwQO+~h1I$fwfI!+RlgoW-TninqqsD+cX;s*>h@MgL{i99
zb%xJH(;dxSFj-KwGA=>44oLbN=f4d+gqHs9`2p(j3!QO3p_K=q6Ic9(`2Xlt51~!U
zq8o2ktTRyaCebHl*)tvbYONa$C>`&=gT#d~{S5D3OucjzyP4HAy6|TPl_AJIOw<L`
z_A-unt5EJ^%5dRS`<aOo;q(Bru?$`hGWR;6<$=tLVBmw8j|1TN5EFL~mch)Y=?FE1
zanP3`lu6_uJj|S*0bv+3YZF|AGyCZycZ9h;0%Q@4vID4(GLr@XaE$q3JtB`}^p0Y1
zM==xWB^}L-O94KH@l1yBIK$UREtc^>53AxB4^QAvFxv&_;+c%?;6BNO7s2l-W|;xP
z1ZD!gj}w{ic7QC2i9CW@G9$kT_bJS^!+@tU@}m%*W`@(-^bE6q4}E*nnCNQIoMjyJ
z-Z{tQ9);<7#ybG+FEI8f6t|i0MCk4?!!UJHWij7PMrYq;*xlg1$E;5SAe)KBgi7^*
zX*m(x51EV$z~wTY^cKrwe11ex$h?0Ee@~bsJy@PGjXmi_`kYCkZ^sMfekXMBD`sOb
zfUlX@Y6#yj-<N{zEz_(TZ7OHH=RsJ(^!be99g|rEzweooDbRgjJO)Dek(rE{q^gn$
ze1qC2W<@gu`k4tYhr?=y{eX7XFfK?<slG8jxV#S4Ci!m-p>&pS^FfGP<?L4h{_(H5
zh29yR_74GOX(xKa{$)7{Ps?5pgWKiVbjPlE))&)3vTod}6)f7?m!W~}>g>a@{ktxZ
zci7Va&N_akdpC&ra`J!V%8gCYSapnpM%nDT24Lh`9)pNaS7FvmjEy?cH>yP`UV&;C
z=EN5exH1)ZqpRJSnq)M~gBgSon%a|@poRHX=7+|3I1e(7r+_Swnfn+fmCW;>5!M%`
z*Ew*x$ve?q>nXPkLF~Ka4X?}4|9j<m2T%=^FWZI=h>_Qy17Mo`nk#@;<p)1veoEo!
za+W||cP34@8f_m3y0%H1A@5xwhv7J<4v25b@5^xXV)9i8A&l8G8-%G$kM)4uU{1#2
z4f3A3vgdzYAawi#0~wXR5^sI=kM(b(nXQ}QYoKm3^&h-Ve%iW`lgZmsK2P1Q6^3Ez
z_63D_?{ugqpqo0r%16wdS_PnUJ3Ie|IJ&Us5J%UdqqvyedZppmeG`pCdNjy@`vIAF
z&!~n?*^9t_UF`(>srQ<|ru}^VAP_B|*8=KwbB$1JVszWkI(O#Wa*+Em+bY50&-CVD
z5zIXEi)>uaQ5$D6QyXXsQyXb2Qyc1OhT>D7XKF*fz);M!{U<noM*mry@8MYI{y;db
zH!K{?jeHXkQ#0eg=(!)fzekU?$@~q+_NhJqb_~T^R@J>=5uEq_=Ncq^qZiQdd*I9|
z2=W(Kn){3zfQ+GP+zbcO8g!{_f87M-_v2dQyh(g#IB8jbJ&v8HwSn`#HR+K5;!0D>
zaY}l;oEV9Q$eWl*Kkzs+l~YjL!>p(T_g+T58IkQ{{-DowFvG0}g(HL+RRLfq6G0!p
zXyyt5W0-jr@OzvolVFp`+<FRp5+geX%VehW&+vMYVgCjooe4e(%S()J7_QA-rh=Z?
zdrb0e_|0YxwFbPH3G@QsIn$fk@`5?9f#pZ$(M7;39gI^`IQ+!?=>q9y`N4WH-6CID
z4TtXX`z8o?%Nrv3tMZro`GIYZyiOLv50jrg1h#N_o2Aelkw^Xx+$p(ZEld*RH&-Ky
zM0o(s-Y&@tn*eZG{$n+CH|61!SGh0$)EL4?a>rb{W{>4}2wx;06o<|&mT!NLTB*FD
z7X9^6K6yDB<D`gM3N|-IkpzI3!rvX1+Z4aybE(>+xby&|dlfGm!7@~FgnH(%B54?k
zSVh=nc#2aL%>(B-MFO&ks`HA$7?0BxcBmS58VFF6e@anr>d^-6ZYHinK8y4}x5d~+
zH6YRlz6K6Y!TFF!ML5pu%lz+Ntova++TZfTpI~jBnuBB8$1QQ}5Z4I!&Iy#G==LE1
zn4W(ufTYjH=jiVKb%rC}f!&t!xc^4nppnaO?>0d(<pa&RX2-sVdhxiQar|q01t?Z5
z$U!4g)B};QRi&!;Zh_O&>feS#by0nRT9&D9s(|i}x{)iKJy180Ky-~gHw~8WShrp<
z*~FKBMN@tF!2Ym|*EUb3_NQnAD&g5jAM-10cIwYls+Src%~Vn5AeYIbK7Pcs#KMB=
zG1G#+RE3PI1^h+KkN{liCyXi##ZI~W61?q_2OR^Uzx;Atu<VhmkmgtIlbb2AwqKsr
z0AvT`86Qy`lvg;;f+k2lc|59z<oQW34UsDbqv4@))pmq=QvUKdic|7_I#}M8|FR2F
z+>sYwfs4CxWjS#7<m!9C-Ivdysd$e331yxh%JXT0nk#pu8}yMpyc2|v<qfi7Ss))s
zsi;Ev!q+rvdm`Vk5TsA#@p<r6Ebm>3NT18U?+;;#Jbxj8FXhV$LGwyp+#Z0}a!n|>
zofN$s&}~wr<f3p<oTd(PRT#%3`pt@qZxGBD#XK5iA5jdT2RTBqgf7(`#Sf=Y%TfqD
zi|c<+(d024W-I1LLYkvkN)y8eihn7WkgG5?N0FykGY!RKMZg^3^A#yqQ4}fGPD3X=
zQRu@_d!`uF2DoCyj1-W)P(<B9twdoSj+jan2bO~RmBNeMmnmF!q4q{`ze<VgU#{@A
zfTlt*;3t^AS9G8m-Ur1dU(_lUEM2Ehil6BH|5<S|7r<&oi#!OwC?05F`Bl+t30k;G
zxi<;zbyohd6hb%U)K36xR*ngULw99NHoD70xo<HVu~qpX0{*;|lkt?P9NU#G>3i(0
z%+3MON13?~roPIs^>Dva`9TNMUCNn#pz~L{bU?93Df<<G{mMIWFbPopL;1FYO8!2g
z2vkm`wj5H<ehgi(vg;|tbXa-a8&QNQv#HmQDEq8IXc5Y4Hvo<~lq3595veTdjB2#<
zWqq*4D4%;Hidf~<J^;okyY_`JUimN!x4=oI;vN8r%I{|(m?Y)wc3?|Uo`?iIRoSf(
zOwK50=wXtkJWbQWbINrX<g3mrT`vJ}Q8|%A6zR$w8ctnSI-1>v^osK41(;?k89U;>
zsw`qrTvtxOnu6+vvN8^Ax0H!}KyzEUZYP4tQYt9pc~`mb4qBM4^y&eY`%0}DfCtL{
zJ5fAT1_nZyr@UK;;*oN|7O><iCw)cB3Y6OIFnOZXJ1Cd=R5`>2MX}PqEo`1EvmU@j
ziSpGC5WZAqJV5bU+2%)hDpT(L3tjS78L9<MxpMkH;C`oUU4!V~D~*q!`>0&u4M3%`
z-%5~GDeDe^<!9y7>)@<WPFjfW`l56WhKZ9(S4NZ1O{yNx0d!F<`U5nss-q1M+h*01
z(df%9svoTI>!Dhv2GCR0ng@-SYCH$aZL0LiaN(_*^bjs~sEX*p^Hmv#L+Gc{B*SF4
z>cvoa@K;@U0*8B5Q)ytmPvzSm)B!4=CLEr>11iT(-~&|{YT#X@`l}0Uf>r%D0vMti
zl|{FZ>K&yQ!&FC(qZXmMH3XiHs=8WX8L9df3d<-}-_wXNMzxftug6tW>ESq`8c_o3
zc-1QUSe{Z%yaT@ps)>&gVUnso61EOivdTi!;Z#+<EZCe@xvc>{O*O_J__M11G|alM
zQtn1AM>UzI9=WQaec?AxmG>UOJXY-+0bRc8uV@GhRf`S-UZnbkmH?irL<V6$Q>~{|
z&~ud+eRE%^3|A1SllpEN3dbh(AH5-UQMXx$pj_3uu?S|fI=4FzTh!X=pz%<jxdKm~
z>e3P5-lmSDjMjGbF3KtSsCD#N^HpEC08hKrG7f;<Y6oTH_NXhf(NBBTBhJBOzq%=<
z-2&8(RQSE6w)IBswnN>05=`%^>(CJAp8Cu0P~KOU^Z+79y>JU^57n1bK$ENf4GYDp
zN9w^pqV`yw))Vm-s7I(!D^z!(T+I`8T_a+8s-8}Xhhnw0KRBPOhs{Q<L_I175x!J+
z{R_BP>NXQ#`C9Gxb_Jf^s>dk7U9L792hDqRgR203Q0K<N^pm>9d_+;DUi%ul8g=n}
zwD5~M00{!sH}ww6|2VN;@8H6j4ZaSY3)>Ny3RN__l7umA@H=>jW!nvahd6eKKgi<Q
zDe>svlk9v)OOPh8y|YnGWP5Y)o6HVh4Vo0TX9EaNv;Aq&=nPx&D|Bbs%Bvtf$L1}7
z@B$m~J4`OJohZqDiA~9d@G_f3Imiq)I|zO=*?Rk-yT+O+3v``L?f`!`*&s^C-(p?E
z==*nvZ9~)hEOsc}i1*lcols=6%W0gS!+yXjuj&DN2@CD2T=vy_grCQbppo5U_F@8B
zpU)QjfzS%sph56k#5Q;hhtJrmEvOZ<?`h0h!nV9aozKpqWwY1p{NWImu|5WR{>s^D
zXAngNJD9$$AJ}V@^ZCdg83daucAyIopV_CBUH!u9=<)x`p86S4IB|!%LAZ&tP`=%T
z+x`N9x^mGG2xc>P46DtmE!@oJ0C;f1O$6%66*_~{i@UiJxNY3yG+O@g=Dv8qbO*O=
zJ@CF<K{OB;gr7sPi_^IvrrligWW;oy+tvrozQDQmLve{4xC+9{+*8WJW^#KdLwJ>&
zeG#6nbD!RU^9I+1gTq@~V=UCFZgYNvK$gWFqUqmVuBAU%9QV024*+wx99jf;$SGz*
zn#&E}0r!u&cEQxaToJ976>;Ne9QlMZ(sTcen_diEF<0#h_zUiGUvQUjOX(e0%K1G-
zTV8Rc5s0viTQd@XH{8K?Fe&H0AC01d3wj3Kdk43<6ybm1vW7tVi4%RO*SQIc;INvD
zpd4Tg*QF)czHu$FV?pJ_e;x}<Xa4;q)Li&Q<G}64x2DeD%-6e$!kv!{LL)qQBUbTM
zTltIS@ZiNKK1HD0`ENS__vYVIKFf!9EToyQFaLQTXm;^BCrEemV=lt)9)8|2)b{cx
zXciK{?@R#O0e&r(h*d%S92zbh;%#?O3*kF%LSsVtfV&7gjF0LCPvLwXr6D5t@5t{_
zKH&#M5y|hQL0S|aC7_7m8#{_2J<dO+x8@0cJT0ik^D`!a`xL*k1VsXWeI6Q<&0FZ5
z@_-+g36qC>@p<6$`1?^P9`Q@Y!EZkA_z8g)@EoSzswe!kw!l5*6Hg-SVt(B^;GXkU
zqrq9i&!w;7Oa5vfOf*%m`5)WDri>4dL9LuOBZaD};43cy|DMkojN$`-nkF2T{Ol4G
zpZKnW(X?vbLGEjKpGj!MS6+wRBC2ovfEd6x2`<|}<}4Ik2eqpp=%8~GZZ!ef7J)qr
z6L-NLD&YC^6jtZLbgSU~4mR6_T@Ki67rN0h*$!bkjqZGeDNfM&3Ez(ZaHmlC2ORDe
z0u3<n7ajxv5GTa^3gHQ13capQ3N13wU8e-E>4-N`XuJ?nBnbw3Vp4<@IdrK)+ASHL
zzcWHzFVLh3X{~`jCxq^Xr}IMa0@N-FB}O39g)#j>b6HqPS@kPI{%gdPDIBHr%2i?i
zIMi+kjcJ;9Q+PZWfIGs51<+*)v#&sSPZ*_xNw(0qEga<tr8ZoH2SU;mcyQzjyJ=Z2
zPq<qIn|z_q_ox*J?nePE68bbn@kG!*2k@CNmWDFL!pjmAFNA^_5S9p%8)!;}@{<t0
z5(ZNCvrPC#OCxWDm@yzL7cPZES0SX+xBR^@<rN%#5Q;~j_~Z~8xTCBRGCQE#s)fd{
zL0Tg`q!GebL0tgEH{p&6!cAfmT6=UBN0|`*KJjZm==O^{=}tHxRxE_cL9vKF?Lng0
z15q3jeWT$%M4V4U%usPLtsjMn)e02h;;tl^M2L>c#;6_@htoVEQk3_CG)hdp4o@-S
zSel$27g-tr#)%hrcse1*(WLOC_^Ag>PKjQP;WtstIf?criEg>LOetc$J19~`?Li3B
zM89^hJS!ffY20~n46RRG5LaQSpt>Z^bR0+5Towb!G(%+R7RnT>8N_`}ES!bfb&&}`
z?WP!V8MRyDAMS8}M=XB>(k$^7UHf}twKw3|V)#Soa>RDds67y$)&nkA97NyiJh2}w
zMLrgb+QTGYTpb5oq4*__p1&gT!ZdI{6$ADnwrAq%8?bpUE~MM*g_vdm{-yXgt)!NU
zeX-F<^+ik%2b-I;ZZ-;Esmm|uLqF-}R>ZVZ>eUVIcS+%eD0WMKeSpwk@}W%f9%)qu
z0DGkuCivSg9r|5918+9zkP%TFki>lm>Y((MCc%NyV+tlnTGSE1Lz1Q$YQfU@)9`dy
z+EoQWn6!<C`w`OYgJ3%<9UcMUHOcS}Cf6lzdcWR~{QQ_MW=DAy(08Qe>rrG$U&!#T
z6mLUuPkI%PB3p_Pa3StXgDD+ZAhqKmER?FAqP0(@kO&knr1mO=QX)O0)#sN|yA3Ex
zr4UNizLE~pa@1?dbLIasCk=n1<%7oYg@811Y`l*iZ7Q9Hs9FD;2)g;bnF#NPflVQA
z(TW!8Tl#r|uhj!up!#ue8f;p}&}6F3aaz*<sZJ5%YTLUTf^7FA1N-)?2Y{i2BO9C@
zdr}ac*7XId^WA>1?=s~q8qjrmDfqj&_VR_O`^nj$>!Cb>W6wrkVcM%dEs6AAL;26X
z%rzYQEuwuj{Wpie=I19^@KFs2@*CaN=18Vh!*$;-gU*@p83fPUnC^8@+s8CD!Z?sg
z9SeLYqgVoA1hbJYP&Cu<28-t4pC@~I8_c${{jn!Y<;AwS20z=_12kCJ&TgPDn>TCQ
z4&4qmjdCGA>`#;t^JN#%Si|ARZrX(icCxoAkFbl~zkzNpHrxtRe|GF^6noe+d*O6H
z>!Sl{0IO;TVIZqcL@kJYN7=<gtTVMZnDwPe`eF9yA^^hJQU4&caJF?MbVt}eqo9jm
zPtXd~QFi|fL~+c)PMrn6k*sSykVdhIG_8ncPtXcV3|mQyJI7h;3J7D_I+WjwV|z@2
z@B}+r2^aBfTM@-ccKcTJ&MEf5BH$9(;13WcvhMWtNn#V9ph#vrEJrXYta>-XPGyg7
zMNFsJp+2XfJj1U4gd&Z-kpSs=wi9*K1@<>1BE85)(wIG+_2~!UCH7WdxVX%A*oR=Q
zu#MirZw9Li^!u@U-6?Zg!}2CO=K)M^v6T`4w^`>N@Oy{V-@rAv#~vYgHmju+^L_TU
z2Z|i_GQAuhunQWYc*yQ(0?S->6eVWzSZ6gjAF)II4s|y>8gxW_h3sFA04rj5(`9|a
zE-C=*DSL1ubkEpb;}LW*+l3OA&)J<cdwId8lb;gy4W&e1vZH7wR?2RqZhggm>H^(s
zHrj?-8QZH6?%uFPyHLDk$D9LaIeV3|>=kT=qc^VEJ9f4Ok-cZn(T0x?>>bMKe`NDZ
zA*^J(G=|A%c1{tBYWBM`(0yg6_`~uWyPX!fow%*9A>70@rcaO?SC?FD;of1}u*#h~
z{tY@$&S?(dTe+LBVdBN@2!?JOR}thuxt-fUdw{&Tx_409!Ht>=QXg(8jdgvwUi6jo
z;|dCZ-^o3rdEqYZ+G5oFxucXl*u%A>(Drgq&mpEm+~hw|1al+(;5UTR^Z_80v(p#*
zFt?Z9YGGV6k?vxy^9R~ec7$8615E^%LF<4=xtBizc#PW=g_t5ae3Wn(a~3=B(cJH}
zT_J{>Er;+pXAVaZ%WWA0VI0>b3Ahtn6Y9};ZtEg&p5(sL4B-@)O?!|MxY3lDNaUP3
zv@D6+e27+JlDQ<x-=}b&e}*)b%kB*PY3^Sd(VgMGg+rIdMNww(EY~mwwR7A+dc&OO
z@}GhG0yonYx{F-?4+!QGH<wn&FLMq0f$R!5bQMf8xCykeFO$on*WgudK{lS3Yux)b
zAah*j@;k!e4K9vCyvg;M4(Tm!UKwm|a~}u8(;ZIj0q!hrGA+K{<t)E|^d9Hj7)3T0
zI1(oJIVT#;=Ww^5z~li}LHV4A+y^&Ak;`oz2hKe1BVEZy+?{y{<}p|P4+711a0wQ;
zFW`3445yGAOS>S7xPDE5f5KTQDfW~rUkTG^oQn1y6?2Vgr1G3IMZxj~ccCsUOSrm}
zQh3QF#=}!7=iV5)S6snu6tB6*l$I&u5~yR}a9_#*f6L|4D59Km)W;TT%y2qSg7h8N
z<UC?~&w2a_(+^y57c|?MmniY%&--nJ<vxDq2efHFpK}Ge0A5{$;sC#z-e3p$p<2KL
z`R)4v58~7NL3fDXI1dp9^Y2t(3E?->hb@#>{D|T(U$4mwlwo|w`6$Bqz?r}w;j_(P
zi{Q7=i~A_Q-tSg#v!gw&FCOPdy22uszc~}(#_{8tz|jew-H%#4UuOqAoaAqg1nd;Q
zmDYL^c+GhT6ZxK$Gfd*A)0-igPcKDCDg0cz@~Ql9GzdA(zg>VB&hU+C+dvvWAsg_s
zyhj%l=lF*sX>5L;pK=tY7x*CqQC#HTrXZMf-bCNnOZ=ae;J(Zk)A0KWZ%zO(gRi2U
zVwwDrICR=oemlKQukoY(j`uM;#!`;+7H>NS*lqqoH(aYbylo=5viRRN0DYHtNr9hx
z{C-*#&E~zrP`l3$Y6FrSet&&fKHxjk+Vn&I-CVHb@-?*gF^}KxgEl<kE4l*km|sRC
zgna&KIxGwLwZl*=<O3Ye2>vPGpHd~y_<{6dDCUzWJNTU6IRL;HygD8<CH%ILFnP(}
ziUP2d-$_Y|SNwo{)L!#vXo;eXZ~G%~Z}{jvDBki_)c}<9Kc7L9D){TGAbiJvlf&P8
ze&R#mKJZHg+N1Q5PZ$GfC2y_|(ocM=uBcV<e{0ccpZOvaqNwKoq~vi8Kes2k<O^SV
z1^BQ0Ic$!>{4HoA+&c*?X=Q(tFl|3LorQN15V{E7G?jK0ifIkTO=v)4ip@g6uVC3C
zxE^Bg=5rSY(avEHq4{B$dJ4%e;AyLHkM003p==Ix+l2XEaJXG)OuHkzg|7R7-yzh@
zLwETI$KrtV71oc0rJs;W1LfU9!JqKtFHBtv-5#OS7}WL(jj;@^+9#+6BbfbyKR6w#
z0O7VC4i5-Dx1%^HaO2=9P?$>Fh=PQ;pMXCk++K`YuwV#+ix6S04K$dE()j+caGmmM
zVM0z%_zf4@(?;VXLc&ngB826Bi14T|iiX?AgaJPy>_{P~Gip)7SL!ZDv~YAXq%p!c
z+GTcJScD(IsA7d~w4W<ZNRC0ICxihsLWvi)<)U^{m_HD;Q^HBg6($HrDY2X=Os7d%
zlF+>Z5he@A7C@LHc#Z^Ts^A_9;c3A)62dcrA_bOd!m$_7oplI2%}~z?%cp|$yb#wN
zwF^Sw9z=0bn0pwJrVC^Lfu~DC%u&R2S#YmJaYgXni(oQ@IY&^-6g=y|#Z_VSD!8~I
zY@j>vrm*}ubhm^iGtf`Bg%zj3c}K8ygJqU5)B;C$1;<)iu(&6zr47N^!Xz&^yf5e^
z2y=vaH9$NNPWFZHp^$kOMJ}!ugn2?^nxj1u+FV9s9t$-`0M8fdRG<+BLf9Ob6bc@m
z&=m<AN}zip99)A&JQb3cL-<U%8xPB3VTGd{G|z?h17Y(*=yU=$CBpvtP`(uYrqp?<
zuw)|GUI~F~(WckJ8x7(v6XIv0_C^>$#alt#ix!p(Lw&$fAuOVuTknL6^m2VKG^NMr
zgK&Ztfj<gII>LRWpraL?PlEX}J%3fgczVZv7MvynQ7w#4hq6X!L|L3K!Y2!&_$oA}
zocT9l>lE~ilX#U}Y!X$Ts5y%g&GcNv5E?MKiZv$ycN0tKTeMj$35DM+;yTJ^x{GTr
z0N^1ur{!iZ@s~L?^4KPpjzV?2SWQ_gAMsv35WeDhnsfPy7Fr|NExwr#6Mu2#NW{BG
z97I=iznDxre*;8E000L-iXuo<&4i0X;xu<S3>L@EMF$-gYp$XeCN6mcT)5avi$ITx
zYP?b$s$*j0aY!RYUmEB|iAyOX7A-z{2JRR!hKB#g#SRGwCRTh+>83c*YbpXgA;t&6
zGG6==0=AQ4F747eB~GO*OoDj1ErLlDeZv4q630cONES0LL6;&vcn3$R;#}HD<Tx$v
zk4N>4c<~wHP7@oyfX!L4U?e*DocOmLHs?ioFmxBhf!GJ9x+u=9gIc=SV+ta?B<kor
zcUeqnhn~42Zlq<n4DrzrxX%>ZQ$p>km_aYpYvO%+tzQ=dvp{`ATtvgRo4nYX9;aL4
z6~BIi%#NK)L6$B0d4l@B$kC>#9C1S>TJ}J^H5Y(~BAbV{<cjy~Fv%0=cZP>Y;!ro3
zJQmN;8fL!uZ$2Cqh;>?ntWf-+6o4Xe=4J%=L`<VB<WsSxJ#f#&GhM-1EN(amvge|Y
zgO(;<h;Fo7u0%W*0K`kNhUTKB;xZn(SK`0}Abl;WlOQY;nY{qM5g+A4_*P7ybZfcz
z-9rc~L^t|+z7x-x;qbk9fbQlG;tCozeH4>M0$wS0+YH?&G4TgPSS9|w!U4o*Q9(gf
zi(hEzwni-QgYt_wA{O|s;*h%Nt#4vF?Td4gJSb1JNt)Ff0B339XXxA{|7r*~OXk;b
zu|+yS*Tr3`y9fXeY0yIi>M51C1NByE($BzoNhO03?>4EtH|?$2F4@$u@s`%qLohp}
z#kASZM_Roa+`iH{8n5|Dnm>TpDdm3#%`WL6eN}c#5ijA_U#jDeVvlr_ezCAu`uHzc
z_DS_<X<)y!Obd8`RPqSI1JW28P9Kya=spURs(od68iJ(L0^A>x^qp}HgQe!PU=t$U
zrsR64H1%ghaaby&eF9<9FdA)yOD*1`c0?*zfFeS29s^HDrN-aT`eRb%0{|kWcC=6z
zC4HrdS+rE|2uxxm|6d?HF5T9EC06RY0gfDTl95KTC!|%BYmb+DDnObbt*(z+qO|Y>
zNRy=03XmpC(Wg<QNTVrhlqy|b1Dey)hui3jGg9wpu%$^&3qW>O(k(zAo|D8tz|Tu-
zX?^5^l;jQFMX6~Acu1F;h5~TOAr-bqd0A@n6A)LVl}S)$NIwjNX{NNQ1>(LcCDJtQ
zn)H#9AlIe#<6(J2YDH_*H>FCN0^X83c_E71(i`gTJ5tpg6j{;`bTE=g`>+QMNu&(=
z*;BT(_zZOSrIqx(%aI&TJ>c+x<gp4i52blD%E^^p4@L1<Y8ZmJ^QA_GFfEY&nt|ep
zG?9Lq^i(o7f$o`<M{lwhQqD05OQifz;9g48=wtR;nzafJ%cO}Zz`c>Kjz&8xq)DUT
z@15jXyND+Zatwm$2Wcg}r#?y=6Ka*x<p_lMS(-{~bJbGosi3Km=F(=CFH(#gp1w*`
zC`tZJa#A7+C(TXD({9q-JA<0D=4X1gT{JC^!LO@^Z3wuV=A{z=n>9yhw6H}pyc@{e
zHGy{>=r#|{`!bMvYP_qU+^R`&1C5vFc_wPxG%a5uitQTh_rQB=(ticp4oxDx9(^=x
za^S*O^RWN`KTY>`Fxjc`r`4fdnj`cxsNI@T%faHWX+Y`aJ(_B|$M<Twzd}Fl)5tt&
zZ_$3uhNG|v&@8Hl;(%su7)TFldbUD{fg14uYC#&=LA3CYX4by|25WMhAPmubqSSS$
zW+|->9o8)T3EW|tnRY}NuJNYrY)3Q=o*>W&&57B7AJsTQ(cEJi3vJbi)HKDVaHyg*
z4?92^tr<lL$QX@C+qB{|V+z1_LbH!vy78Jz!{IPNqo&n|L`^b%{*p8uW5JfJ=}pta
z6wTNqSf*-5r-S>nreOo<&S;iUHa|@xHvxB6^T!%+p3^k>3cz^{*8+|l7c{d(xWA}r
zLJre4ZMLB?mo$qa0lcg^(iz1S&84F#GBmB|=SZ2FXi5`b)u_J!cTLl;E<9b=T%-@>
z4b2S7<lWTR#)IsZ=5!>;ZfklqM@)A#6FUKyrRmxm#a+$RXz1=aG#e-tlC9CZ;Hur%
zEIJID9L-?r%Uq5B0&wSPzDon*k;aXdx*ltEN(l2cFDJpWKvR7l#S=|GdKo;`xYedu
zHJ8&tR;I~agMNCW=|RG`nmd$3E7xS_fTcpypVltlX&k|{W8}SN4XrGG(9C^-PW-58
z)eNnu)RZhk6rVI}%>Y(ux>920v!?ZG)T%W#G^?u7%=-()7mXMFOyR30_7Qa7G&?Hc
z-bou44!|buZ=2xBS^GDwZM$ffQ4Z8qySNStH*E(8rAszz`LQUrXnSu()7-Uba^O9*
z8}bl^r`Br)gkIVy4MDR_yR#!mw`&XTq4&JCo^xTcL+eBjypQ%<f9QO*s-<X>pEibe
zdhOH>9)r+!X^%#ObGNoc4Kjc2sgCfsNBg$512lWJ2NprPPy09h;$y$IpdM%fw5}IW
zJD}}Bqy2;0MYLx#P&;B8;tta8pkG`Z(%w~|7Oah?E!-j6Ec%60sJ5I&bBDEY!vF}=
zM)gP75!&E!;5@2LKZx2f?Z(H5DN@_|JDQC}X<Jx;h}K@C_iK#Sc^_)WwIgX<6RS;2
zLet{3ry3%P6WWo(P>a{@VG#C7ZTAvHaY|c7L(>FpavQ)CwUe8nmZYtkfnbug&ndZ?
zqAgIsZ>lyV0`Sw?j`U4EqwR&<mP3`Mo$n5|v)Xr*ggB=yru_MNZN_tie?eP64YiBf
z+aZW4U2EPB{3WfLrj3`iZV%CGSG0Bpx(w}`FtjjJJE%PXSGAYuKE9^yHWtF`+Nree
zc0-%$2hN*XJ$^u|x}{ynA|}Ue?cpex-qF5Ti%7Gy!+wVJt~S#h!h70Zro%<H_C_Xv
z_qEq4bC9EbHwh*WwP70(MXq+i39#j9ZM3HMNXz247plkFCbSnOUpufhgaz8q7hqYa
z^`gC=McN#ivp>-eC4WyH+W3#CKGQ0rK>A#pQoD?y{kIN;C0f6qfq1D6`3Ra)tw{^S
zEA3NCN4(blLFwu;ZFmE4ztN_&1pKYGEA2Bc*Je`BRA|?K1MY)%D}9VVYDdyHs#4pS
zbf2_;yCUo=t)mw$`+wFxqwQzaTE{TNU861O2H+R1ZaYZ7YBQ#x_20Ca;V7JR&8gd5
zbk#oq=c@anL`-hFhS%VCv+lSI#TMNMPq4V_LTD|~L#KEMoTn~lDw?!a*G2;qFWs6~
zVA-bI>4=2Qc3s&^#O9-W><=4XUF<2~{d8-WA*P+Wh(~a-OXpGt&EBo+gauiZzwYNd
zFxjJfF%D7e)$KlvVxR8q7wGou_SS$bK(~#u5(jiPdc+Ru-o1pwK;38;;DU5%v={b}
z?$QJL{srs)p`mJsPC<LpLUpU@ZaJ)rqlA2z?qoBVgzIh}1n`KiW;56#bjiJ7c~tj+
z0LOHN)IpKD%Y)!IO7~_zOrmwp)K4+G^Pj+ST-TUZ|6+ByH3&3L_qr`~Cv-#h(2o3g
z-4}Z6oz#gUq^ERdKOhox)9L<5)UEV``y`$FM35%yN`66TDgVWEM)wB`U7F6n8r)}f
z{b}ZNPWSdt)XwYXegoiwj%fpyi#p>LP^asX`@+#B-C8R=T+uC@PT#)_T|i58Tc&Oo
zy*#h#bhOF%nr==6fY)_@429`U-GV`=-O`Ps3wvAlkXD@U=otD{VwNtJ@*j6~uC%k}
zzV3BA{O0JU(QM;^E~*8D4|SXC1CXn`IS!V2x)=S>U5|98W`H+;tP5?AGGEt(eo|YY
z^PP%F3w8g}B3F@4N(SPI?y}#EU(JrEzVQBBw|6_pUg%V`wpXHSPcP}0x-)dmN_D4S
zp$)HenRa-8t;@<oQKsvI1wYjr-L~fdywwFzp1fRF@fJaR)J>Dad8O_%ee^%+-n@jc
zO7|0W$Y<T!`XH;;h5iFwjn3qtUv7WVU7-ZeSKTpMKl!H1A%v5@oVFNm(*MyII%j?5
zdFWj94Bfb{`Y|*F*`oKO*{ZwVoqiwcp&vU3g{MA~Mxk5vi$5bmFTI0?5Zm-SUP8EC
ze|{ngZ~Z9x`1<Nk52IyZKm8{99pX;?kSsK2m%c~=;ck8CYZU(a2-*X)M_))QmV5P!
zx5D8*{qkQyx?kT6n=@1adIjy2I-viXQusmoGzKh(^ouwMgY~N;00_~4Ek-R=9}$n@
zuzsr^*E39SUq#!1!}XsjVR1ws9R!CFdWpL9sQ%wd2#@I-eMBpw^@aD*`WSuYZPbqI
zrw@fmtX{qZfH?i{^qM-M_r`*wDqdgrJc^V0)1wjZDZSwUEEDve9buBFH^n3DBz>U^
zbjkV=*b0Mf;QIPS;7-*C{DPp;^a-@ac2?gp4IO+=A4H$z^Lmz+XfEhIm2iJiKXDoS
zrt8P{1otI<NHlbp^%dVB%+xobdC*mTkvCji(=Vq->$=|U34}NFfi!r&sgFMoz%Bh7
zTIO=x)>n*zi#z&(GzHJn@4p7qyZXNGAiSr45d;@G`p%TDd7z)01(S#RNLq``)qiUZ
ze4f6PGO~~K>uGuIvEHY49HqY}qM-%)D>RiY)X&htZ;>85aB$!2{g;EKSpS&5&(9tD
zRu=($q4zllM2UVtV<=zhe~$ross0o#V!qO+?1sbFdNv%jGW{0XIPpgRs0PBf`lVAr
zTCR83fTcpeIS*mK(}&Lk_j`TaOAuD-+fbhKll~H|)>r8_(N3Drdhb|}RqGvVm5|ox
z4Mh4y?}D$l>Z^V;jd{M|-a*aT;7v0S7engbK)4$AG=k2};7Xt5%?3S9>$e!fJmApX
zF#b7o9)<z!P<R?*Xy~%laB(tpUIxoe2)7wL6{zhnY^IGOK87p@{WQ(ju#qmapJ5HH
z{_ixD4~O4fh7PpHaJQiy{a(%A@E{f@dko*51%9vL`bxOpXYiq+&wj(bdoVd@DEN$~
z1sbwH02gEkr+mvHLm;hK1{-3Fa9u+Tt7y$3)KE&@eAuAiC~+5Nm_pkG!VRlv?cs>w
zX({?E!f=%aB$0+sryz_nbkBn@+Axhi4l#zF^wv6VSV>>VSi?hF|Bf?Equ<<|FvK_z
zQ@kNQ2rWx6wDEv0(J+XTI7x;*W5JSau;v4vVrX+!j^{7ckd=k%X+t|&Ogdx8qakLR
z;SBAlIcu0X8^t+8wGt-h4YJy4wm}>Ono9=n3>23Qt!Wl_#n9s?ILt6i{0Bv*Vf7a1
zt{U8Fb?=(t@A?Ssx?%G#h~kEUq1BF?hT~mmsCLV6lJbsOhP`R9xohyC)%bgc(Ix1T
zY{Sw<sNFYAqCIRmhNE;RJupmP2!{_1!d9^58rISN!#u;=kpMh0#BT-5V*_i2i$cQ<
z9fBz`Y@t=UCx)3c?|N$R@&)dhq5BOKj$%Wy9*F0LOY6b?!r)Bb)DlD5X9!;zYDS<-
zUK@OA8dYW(M5D4dhIK7r^42hL6Kds#u0udmVVI^tue~#*ZUf-GAwCR%4~98*=sp@c
zT|j7+hGJ^qXTw|CfK+WT%|*}DI1J$~0DdtT*FpK!@bnjOe=`_gf!oRWh#sI##vYW?
zbT)3K3+rMWI1X)cHTDsqb2HAT!HS2mcmm*_#v;mJY&F)Q3AvZCF5On!jO+dae7kWL
zwbRGwpqam~(RVI{en!WzR<PM=eD?-X>@v2bH`{I_OWP;?jeR<UZI3Z+Hca;#<@CPU
zXM9Do!2QODH_)X4#wqmR956nnzmRdzSWPd3K%+$afr5;?qrh^=xFH{$!Nx2asD>E(
zDbUTK#+kQJJ8Zn?pzleTF_OlH;l`LVD2^Cs(C_XejM<j~JZkj02GV23&Xj+TGzRM-
zj55a1Qb@G%cbdq@7+=wodffPOAVP~Z?xbvboY9v)m?w-1TI`EAMo9?tq*1R0{FE`g
z9{>qPTOmDviN=jBp-eJ1*oC;0jS<dhc8Zawt$V4)Ts2Hi8+X#=>Wpz^E3l;*SJLLd
zv&MW%x}GyWng~zljUW2L<brVot*Ko!&J9E((v7Yf2rn6*jRy5)<J=CYT``XO3)C4#
zLqi&>Wg2a3fw*dXbqUIA#y#{hxo*r1M0;--qlba!rg5zkT--7?r)84c#xu1UDPvJn
z&}13=kAv>6(XA52J)=9NO|y;L_5pX_=xT*9$LMhYxCh4Tr%-!nd`T~%T;l~Sb~{vg
z#z6W(|0Cmj`ffiqj`{?fd}HW7)C!DIw-8LBaqM826d5Pv0{FyOHW(&Pjs4$%^qKKd
z3+RfCD+%!2*o5|qyfl`Khh?eJ)D9i{$~f~WVtQ?yyZ}X+G3`6(-WZqkLE(67oSKAY
zmmBX>)~Ui6M`O!(M$rJa_s0GQ;o^gFPbwUKG`9PMTBWfm?FRm2oE?T*m2uz{;659N
z`GBq3IEX&tHO9PPn0zr-t^@T~W9B!&zZu<2(alb#i5gtHO{NISjyXF_v*|YlE+%gt
zN>@`h4T#)K=`<YNYzme^x5d<*vWf1dsyu}6VPfgc<Y{V{3;b5or~!z=%e18hEVr5F
z(C&%trX#c=#oP4#J6P^86;rSKm^`~6P+wC6`dbu!rZ(*$+-Y*Wq;bkFQ|VdYcbmRG
z1gXEtL9h2cCTSCddrgOF33H!m9BumEZ|X~%MgmN}^oBWLDp(JbgC-M=&H_yjKcNUR
z#n6l9km)|{d=ECI>_9EVG>O_9YI;wDtivY95_EHzX@MgU)o{}Y`d!Bn(`8D~MwtA2
zqBv?=k`DYa6Gx9~r0H}#YEh<#v^^@?G~NYlF{V>B&>c7Jr4EiYeHe#8<4ix(>goxT
z`%3ghylE8u*_@N6zKv0wGMR1wo?r^!4-bi^5%p*{LXzp@e)MdzX-ygMDW-jA!JTRv
zAc5wz>8l>VGp6`z6lo?d7r?Wo;THh7VA9i_d(kwFcF?7pP7Hy=OQxYTHN0%f?T65=
znEdHmo?&Wu1h`C75Pn#zx@uZMe}v|mY4|EyxVml{umRjROg$Tb^rorn1=MbtoN|D_
zZ7Qdq7Thttqq%dI=~Wc)cTLH3d)+gwo(Mp;DWV~2_f0>Jg-MRdw*yQbn7Yyc;h|}9
z4Qjcjjr1d}Jd+!JHy@df(K6O!Q}rtup1*w4vJt2jn0{XkhlQpGqfsj|eMecCC#Fp{
z;Gde#y+BOQOi_QpQ?aST1aLn$HE9OY7pA)7(6ka$v)gF>OVhBSz?GVUXv5em({9?^
z@Y>|M2emR&uX0$vG5r~hDBhZkZ9y%Tn<g6285Jf)Yri?u8#%VLM(vYnP!kkYCZ4{n
zpG|yom{yzG(6GJ6^dJloelhWbVe-{vqZ{g*sSzc@oy_I5$#Ijpu?n7?%^KQM;bInc
z!^G8mGyym_bL1kJY&L)Pg2@*1%_IclZvIGvXb*FJM+eY&n(xxqj;&^WHr#ue6WV}g
zn|aQ06x+?0>BZ`8?l~024s!z<>-m^R(hdz@bNUFF_?gAssO>br{S4hM^MVB^cAFQD
zLtprt`_Yhkk9p=ISnf5?az}Rsm^HT%;Q@2N_cV1sXs#<l8EDpRM=i*Fi1w--GCLiC
zFxVVWjz~kyht?y)P;=nlh~lt$o&fGJbL9y54L8rEtiloV;P2r#!aR00a7WF%Y2*Ac
zvw>DyBF&9yG8ttqrQ}hxxhNI27<1pJd<#5I=2H6Z#+n1E*>UEZw4LUJnd^cO<IT=A
znmuV=?Dyl$dXC)IkR_XM7!gv6`4r{WQ_U4Diqqz^5{fhC0rb*JGmobw>9giBlTn;A
zkNpP9^X5@Da9uDzplA7_+4>Qd>E^%bZF9-Iv^`?DY!0adz!kICAzX+Ib6?7TXPOIr
zfxBu>aqL6%*UZYEaDUxAgBDkBm^aJ>%}w)%g`l}*uBHssZF3l9NbZ=|{0m@~`B)Y#
z@0!aSq1E@yBj~rY+2)TK(A_t;E<`QIjJ*wbip+0l>iy8{I|aeyn)B$_(Rt<xG;?`m
zHYU<|=&`xm0mPPXo<PI&0`oIH+!vaAJcq8x9F>mZiFxB;1p3r`g)&Lc%>U9_PqF!c
z9=PY`F=+_xh53iuAT2R3rls(g=6W>PC^h@g4^Cd0L+Ec9y*6jI2B6G5;1w+2n0wEm
zb-uUe)KYMlo5M7qsW2DQ&Hd3_I228*G^g|h{*yV&2W(a5?TOHRHus_hzH0L&Kd{x9
zgL}c@7jtwA)V`WsXhZZja|V4joh;q%qb-{(hZm#fY^hHpY8T7c9jLilepo@jp>wlj
zz65@=<(nt)TP&O3AQ*Sc{*h?5ho#Jn!qZYnyLY!*dZa_=WpSr%5Zf%V{SeG{%dSVL
zd0Ud{CB4IvNWu76=F^&suO){*F@Bceln2{s>9ZHQU6!glaKGDfn;r&-zhw)pLhrH6
zo&ZmKEk3`&bf4vWnq};_{7$!VfTft8h69#3`a~VH>^KRNK#S%f8X9ED@PO`+Woii6
zf-O^aBEk?$GfJ3;S~6%Nf7p^h8(P9F2d~32+_LoughwpPXwO%K!!orl{2sN;3_$gm
zWlaQZA}x8pgC@$Nqe*16rB^YE7|TVvl*cV$ZBWEozT1Le;w&pv@O#3tVhn`wmQHe5
zp0os0zU7o9orWg~mYnk-OSBAa2a_brKeWv-*>ZUjVoI?%exk2$s%1lWAWmDXi-134
zDQgXzG)w(dAkJDUS|GG@misH9J8wyh0^ow>-)*Q}v`nHM_URUmK8BYpWwfjJvgOkR
zm|U^Er>u5{Wo;;~L8fK=K}2!Ya)y>JuUSqX1mL=5u!EB0H!Q(4N4jZ=9*wTKW$8-e
z#@m+Y{t(`=$SM1iWvQG8;a$tHD45){bd*DvW2y0lrw5jm7tsk1Eu$pFn`;@D16`hF
zoCn-Lvdo+U;bTipOE}E8#L{h5VChfOuR=?zGbKTbEZOT2)Dz26%B?@OxXlOfnMKtJ
zo{BAI8WKOZti1@`3rpPx;4ZP;>ki#Z%PIO1O{rz(R+zl9j5rD0Ym4^;kd;~b(aiFV
zr3w92k++sO`Wt=a7AIQhuCR=!S@Ju}DH+=qLqtpVDA0Vc+^PfoN6Xn0z*kzv9zuwp
zEJG-ZUu8M<JJ>#3rui+JThB3&!u@7BR{%06>-0LPZL%)!hn6{8N38<2i<P$^PFL&q
zG=X=s{*nd<o2~U&P;RlBDO`8!v0}8{!&+Yei>I|YEyrxN#?aP9FYBKw;I>&;u7u@w
z>k|5Dh_`j(zcAThJ?E%G>0|xlBG`PbJbfGdtV7qqW~cQE<qvjQkL`wVw>3T=-2T?J
z$#B2NY7IkeuXQ`kQukS-^I@{zn&AUa0oIy!@N~esj^3vStux%=A<#PE18PCm0Ve@J
zWR0awzQNXJ5j5ZmvG%QjO{les9-qV3HuN`b!mR3_;3C}m{wqw5SohFsY=pG~y?l;Z
z@rQ@;gjxR{gj%GvQ$sW~%G!e#v7)UJL>6Pc{3ig%t-Wbh9%~(V8YXepUi5cJPFSxT
zg)rVax*<CpkC^qJf6>rW)>H3blVIJ2l(8z=+JkcWDb_KRHcz$Ma-chHJw-2{GuF2n
z6lvBFx@c#uERCzrS?BwWnqSZHj(*sA$$FX+IhU>7?!w}VwS5WV%&^{UfLf-ty)*jY
zs<j_|5wBS{PC)ItwH0k@yJ4M5J5X*~Wr1k)EvvW$G2FIl*Fbm2`kWFXSyqXD?{L@J
za}9L&tZN3L$hJn^0`9(b)sSak%dv*jk8&Sa=kEpLp>-L}lX9(1w?da^jY&mlkF3^R
zaPin0+z7yY>mM1QDX<n!L&p?at+V{vE~xAH^B>fTt<Pz&`rKNN=5;Tuk(0n#Vhvw}
z+Dq$dn%9+DRkTa-mGyf8#cS)hSOChbH}4?qH`a&q;r6Xn_8$Jqt==yHsIWTKL07!9
zPNrGfd+Vk<;QU~1MUVbRYkqTtTWQ_ups&CuYcKp=UsaX0StcBQwjQNlTUJ}AWWhy^
zb%X`nU#!d{(0sLS+y#?w*4dHJIoVpQf^L(I9|{&{o8KF_cd?DNpyq1Zpo7lM7D$7G
z&9=?s0oY=zPd|Tkx4pOr_a3%xGaRUT+T7w0@K#$G?a21Bb(#v`Hd_>>dbit-_XN<}
z*5xh`J8a+4)*c^Q2JKMwwT+|!mY+>Yv%{UX1@x8OWt&w5;clDvTh#n*JzK-W9^2Pm
zfbX@frbJADt?D2ealqEfNXf8+w)Jg+2(<aVMx;Tu!}RnWvZc|SKG=4Gc3_3rzR-r{
zP}^8~MIW}g{)i&X77zlOa9flLxFfbIN-RX!uG0?Hqqa}9Q|*||={_7r+D@?OyeM19
zQWVj)5412FV>@tzCIiQ9*G!;^wQ=+ttT@{>dPknHz4AlA@wQg(C{EfcQ-L^TOS}hs
zg6)wCo)T?mY4(t0TTl6;WZN>D6sOpJr{$AWTc9^gPTQ8&2lW|SI{t)<D$UmSD@@MX
z#w|c`&bDhT968S0#7H#eg000y0595%^p;AuO&E=4U$Sw%;P<jEBo4YOw&Occ%dl<u
z3v8J-C8f)++L~QK*w<{+jsSPvww{vjH*7QAz<ty9{X|&avN_XI>}{JL{n?2-wm27b
zSC%chAw1l5*gEck@}6z)4Ir{@_uIhczHQY`*yPxLqGms^{Ysh0hqk-4kd|u;p*?(g
zwg>b({YSP^+UNS%_HQWM=i5AgMy<f+^%gM|+MH;SqR4hQ6`r2h{x}Z6Q`<0l5k0dd
zUWKmMrt3vN&U$X!odM+w+YG<ki?LTd3M{W|ch1A|wQVqM#VfOAg@NUb?G^2Bcx%fp
zLgUMAiS)o!*xcza2)wh^=Ky$b8}J4F`@uGe)~Y|+#>o+NrR~wr2<el}X(Ieo+5Y_*
zfX}vG9RaAeS$V|p)mAYbwQn}bF&{3R>>=O7#U{HzKM8QQx1k+pF7^>L?RK>zMT2L{
z9!-g=&Gw-xkZ!R*SOTHDeaA4=JnXIM`|oLQmjRQl_7xRy=w;6@1obxidmBu)+fP$c
z$lJcIJ3Q>LC;bT%AN!Rt4us)rpU?~K^|SA%@xxAg^L?o8vah4b<!*a4izxi<w<g2k
z9{VHu)bF)>W&^j+zN|i)z29DD2Wf!aLj>so`!BR{?4Z3DrRM|f=O4o|$gUm)+#!1h
z`l|%N_F&os5MqDrPruU*wQpPshllNtn!_f{J}eCQaC@(|D2~{#(k}T3d%g*XqxOH6
zA*N$?BfX{~?Gx3|McIeY#3<T6))Vj;`x*f;9k<7?gJrD!*b3m{>~292p0HOrqo3mK
zmiCC^r2RHFL^xEZ>}}|+lVDfUcPi0-a2?o^>|0KuNVX3cfFi{nwHHOI-F+B})Ap9M
z?d^=coW}iW_Vzk>I%|K`8O1sKiDU3|-oEZ8BD`QfzZmW>+LzUZF5SL>BD`d8ejM&E
z+yBM-lxo5i`-@hf$*?!4C9q8U#qE$@wQGvt>6$(L5ZJEU*He3M*qvzDbJKn}5hl0n
z^>?6l+diI!?vA}x4Z17KZlILdUHeeKguhxke%l3$Tzl4SFz4A_Lt*&Hp86}?71%wG
z!9k(j(HsF5*~2$N_ryN73h1ZygaY86*{4tntk@n*FQVu6NwgF1g}pm{`%3H$6ma*_
zo|KPTsr}oZ2=kRaZz*c8?KM7VUzz=eqciYt?7;=#ertb2+yBe$Jna*$u<!d5r0?wS
zDeCw3Gqlk7!R|%3#s9<6b;o60b#coqQ`=@fd+)tySgB>2ncA|_%1pDjv|(w()&nvH
zWXqC`BFK~tqHINmY>+7k$PyLVAo_k!f1S^{_nhxJ_ddUI?>XoGp2?NJ(kY9nl~<pE
zGt(<AW$=DxWk5H`>`DWLi{@6k(AM_eN{JuH{K{9|VetOS)L@7_Scz*Hw-h7cM|wuv
zF=i=<bcFFFeS*TCadSEBIxxPShoU3nZK?!!V*FBxp*b^79fxZ!4EcBHJIc81fx);k
zc2Fs*8zY^TaPEv;+H@Ran3b^P!I-Bvq9<cyDJ*y~(tZQ+X8cHZv=5^!g7%NT4DO>q
z^J5tP0rqjmQTix|KZ8r*?Er?)4S)tRO4vXPVtjrOt_3rmp!0$!7-p(d3t`mJS&vZ0
z543j)W2B}5JDjmi0)+_1$PBnhM&nQDi((8Ofca>~fgV^m$+&HyPr#mHbcX;mhQXn^
zIL#QP?<>VJzM&^l9K-u(kTZ;IDvXO~eDMP$6Bzry0d^w8hGM`;j3%l;N@l$N3A|5X
z)W^ZZSw_+>G^R3kPXjZJv54|X=?vX5%wY!OwN7AWGLBN-dv6wFSu;Ab8Shnt&0)BA
zp);2eL|;KT$9VZR8uJ);=zECg8521Gy}-CL1WWmhZmIz&VtmJfdNITAGTbg<D7QeQ
zl#y2sk&6tbC!D#&i1ID?Wx4hGWpq_A&N;!QN`|x-b63UqfhruYFch5-tY$2t>`)Ek
z4LWXB%Q!-5#yZB@D%h!K99;_1z*s_eYa_$K0Uk9mrd%M>%qT4c^i_uO9q6?%cF}&k
zl`-B0g*L{8|5kvEBrDzf9gNMi8tG(gq0P}XMqV~VyBLkhK<j3dZ^vk_GsKkL>0#Wa
zYO`L(;`JCxAH#nE`ff11DSO_}*s~R6fFUuUaggyxA;=ITivp{|jKBLpZZbqGKt>o|
z)OU+9?c`f`kZFBm5@yF3zgI$ioUwTpzDzK}s7`T`@x@E%n__IKgxP6E2*vGY7_Lgp
z$Sgw~0m(T=g%ERnk5Q<CyYmd01>Ajx-P17ifD!c$8f}@+(!SP?8B0|rN0_BwV_xl<
z`)FV5z_j^qb?L~w^Cmi-m<>bFaAvNgSG)`JvjI4IlqsW)tt)d0RTsE1U9utK&fK;e
zeaDzzQ_R(ad8`&_p3HoD+<P&9d>M{<GkaHo^I^XEB}9Cg>;DGl$4sVDo#V_El=kvx
z-aJRE%K+v$g*XD4Z`#4rAf_|DAcC3UtDty-nX?~U2-Em3NGLO#Vr5~>WpYeOI8z-8
zE`r%Z5BNxC0)<;nGB;4_;uP~LDa61-aHpApesDXM*+hx$IOZr5&YWRNP4vZ=c;*Y|
z(3!yWV!^3Irk0jzNz6x%flFr2{SBBDW(|FW<190v1O`)?j^t<>^B2lpq%$9-uzd#e
z5}icPWPbfE8nc*u1)RxduI>QIVJ1`RBA2=HD!|S$<zE3MkJ*DLpmouCrtUc?USRsH
z2gzrCAc2boOvY7ANg>mhJ`q*K+(VOC%zSkoTnY0#SB$BY`GPAXFEZ_EBYuhb-By?=
zW8R@a`DNz&!LU@$JpT~53T7@nk1Clz=|QTP8RZz@73SlyP_R}rZ75z@!%U?wJ=HQ-
z-$iE~^Dw1@>X}<tz(fPHmLl|x%pG*YH8EG$L$R4T(G3$<na@%-sD;^0vC~%Op_f70
zn2jfZ+0J~i1*C&{g;tlHOcrH>t}%b2@M;%RM1lQoE3=qRE?sB7I}W=&Oplu&z07BW
zV5yJk`2p<SU}}3o`kDTeXB%Mtv<}=L^L;8*8e-Z@G2O#VA-zRzGH=kTYlQg|AKWdb
z6IIdPW*#(wyTiQsIP^xDGJ0v=WnQ3N-5Aq)e+9f5XGTySb%I$(iNQ%`DD4WTm<5f{
zm}Y*t72FK7)(tST%xB!;_Z%~c_Wbvl9S#tgXYSmDLELAu>|p)@bBjHQEz6E3*pBtf
z1sFWS+D*?1d)6P@;gb_9iUNkttk<k_=yYMZQBmGeR#h87U0Isnf#$~2Q{cm$HTEhL
zkFj1qfj$pb#}pJiStB&hUaXzV;IB99OWOJQunKA0>&p_*eecKG7YMhHvv#Rq(4Teo
zNuUI<R?#IJ$ntWAdJyYgEk$dCS&?dZbAt8f78nd+IUa^gDC_53kTBM{XqX6RaZ;fX
z!P@#76e3x!Gf;?PjckWPG;0mTT~4xIqoS8nEH`?F#jsY<)8jPj?F&$dWmQq(Q5?(l
z6r4H3I!M`(c-AZ5QdM{Y>uuT_C$iq7Sx;hJ{2PkNtcsP;NMTi-$6(H~9{LF;Qdx;q
zUzx_z&^43JYQF)=4A#FCH_T)OQBW|8^&$oJvRUc$-LxE52VJDOtf5{=o@1?_fT29r
z{&6&(XSsAO!TooEwSs<`d{#20FbY@)X22D)o}ur(6|oM`<F1%BG6%m)SohE4XDVg+
zJ^=PbRxo8(F0qQgflp<u)wCMA%o=?SBIT?MdT&**Dk#uj$x_nWvWoQ<rT4F}{-qQ|
zHOuG<d)6A3fDN{m)wBUJb*wKaR$b3>r_TX2u->6BLo~9!-vO8=*1%ziG_%}ZLElx@
zKo__cmYL#At*mvsAkxN~k$`JwC5^*U2kUz!#@oqqp_8Q7SaVb*-Ng#I0<N2tK+xB%
ztR-}l^suaN0<D)-G6tAF*3yem9AMr02#tfRWLuCS)|aDb9A;g;2AG?y4eQ{=2x|qM
zzP!bHo64VVvtD}?B6nCPKEia5vKH<EcbC<i423b4cRfVLS-IQb;RNdmDxa8SS)ZpW
z!YS4u9c`axi34DMhP8~+gtM$26l<Ady+!$>d#qY4juy?ch65pTpY_~I%<}`*V~#+x
zWjFML*s-f9&~$|D>VP5Hvy<1rH3xRUVn92xzoA-uC$?-68lBlypF+fiEwf$%J<1MT
z4}-4kgPVZu#x8V#-|p<aZvgEWds8hmJlJB|8+)>csZ7R;{Sl=yyxEQPfm9!MI0bZl
z*|jwQ^J728hBL?6AJf9rpZz(-ngiGjT7d_$8T8Z&V(+E|TQED;k0O63*zY^Tw-B~;
z8|;R%8@>Q`7<)w;Mjy_;PA7#U*m&LJ#$#7dfFO#UW`K!k_O;U>C)q1x&^yJRqq{1G
zy?!aMPqW+T2@}g+N0k<F?8j-Re1^TW3g+Y4_vtN~z<$@BzSEt^wxQi^5_^W~_>$R!
zFTtl2Hk;~W&a!>znUczmc^G!n*xu71>FjdEMHXeS7x=?cCi~Viu$0BVT>;5#_REwz
z&%s;(C6^uZGZfCTH!a6l^4J{8iJfQnXrXX{{X2$>s&IDy8gv%0f1u}FAv=kRL5kQS
zsyZ%aulfv)CG09LTq|W~jsfi=+ekOpCH4Z^#+0**+R<3SX41KyO7<0c$yBjlqO&kp
z*e7kFUd{fw0$dHd_B)Kemfb+>lREaJ$DwDfXa7_HjRy9;K6uf{=D!XXo7mfZV4|6w
zMKzpP*}JY`OfBpsbUdh)U6hBuHukazD73SaX?NPej-$Jxll|_8Fma9TNO_qq_BXU;
z?Pe#kF{JD4b8`UeVQ;2HOfP$NCHnfT?AUeayuto!KfLK@FQj1)u-DPTagc3y2^vG}
zm||EOX2(7WjhpO-7vS#*dmV*CZ?V_BhQ8bE5Za92Vb{}Hi&6I71t53XA4dXZjJ=Q6
zh~w<?X8<<AR{j7BlkBZeKw*k)-SH`8rrCv$18s(Vp&K%@?ESQso@3X{0p=cioe{&H
zXD?d|yZ70-6y|%t{?Lp@Th2)bDA;kjBB5}E(>)Cj?Kwt@4?A!IJz&?76I%=sC(hmD
zP;llrQRc{nGf07|qnu~0AAq`Y9!p278|N<y=eu(X{sni8Gblly2d9K~>Ykjjd=M{A
z7KQq~IXmnC>ci>&2gH}NWDo56aeO40{NtS6VKDE{*>(Zy0UTo+xIj)PmIjN0IF3V@
zu3*j`D!n<uadx9@NeHKH4s0lgy#*R!oC_BL6V7RRA0&cPF%6AK&Nv0=qBv{gVLqDk
zV<J2}$@y(DCg>FBP!#%NIECBMcbfA)A0(DjND;0$&R=ZwC2;<Vg!x2H2PJ@#IJp#a
zN#^tpQmI1<r}SZTp5<&VhiEEi_%#ePjT0~e{dCU0hv8ZV$H5(nnVfGZz>vi`{4PYY
zIoUL{9L|AeIFri>`x+wWINL=SQXVJxM_``kuvY-(0%zM_5Xt96?txwbXFDxn3ONzi
z7U2FX;w*d*4i|IWJz%MX^J@z_OF4O;gS*HXqICBq&XHwsxQr7-$5t+L)Pt~8&RI%9
z=nBrK2VtU;<CzMDDo#@#EM4JrmIJezGrAXgHJn=%Z>!~aZ2_s{Jko^5dd|7W;f%F`
z<Npk3Bj=++C^m5>=nEpvoKyQ?_bSKW4udTmbw3QYa<VBX(8l@URdDSbUlaN|I9YE)
zvXir50OT5H(>9PU&MvCB?dC*gL*Y7S$rJFfhg0=C6nZ%=J7KSn<G30A-mr3>iNz@T
zISVQ4IKcUq)*yqNxKQX1ajG+5X_(X24$+$&rYrPEIF9$=;VsTvT5z{Hm6Sfa!}-ey
zZj|#vB8GjJ6TA@$V;nDf=8tnaK7+^vr-=vXNlvyW3{7!n=n*>2v2y6t+zjV+I?Xl9
zsrnV7bDUcgyS&HwnQBhwIl%=O#eEJw?~5CcQ%ZRVTkdo-h#hx`7OY3OYkq-G_S_c(
zAmYH)(}voS>&?cnow#?Yc-fg7M^%$9Tq`{-k8&L;r02?g#u@{CH?ERmrXE~vFGk_X
zou5Rf7q^`PU*6o+N+|kpU!b*<FLyERH2t^-ouF`>yZZ)+KUcXIC;{9;+HwVQ3wB|I
zLEN2kj3t;G7m2<T+|s=O3*o*_sqIkittp6varf`0_g^^I_Y|Cp;LcODGLp;K0mUe8
z!B%k5+()vYc#`W%o9<KGaf&d<aL>>><23i{Ui8Ism!?1=j+;rx=+AI((6ck1tJ@2=
z6Sy|VfRf0yxe3>jxCPI_-(>D$Dko3jdel&<-&yW#9zavM2k16T;|839emZxn2e31^
zE%eyR<l1b3`7ExD9-!IWXWJl>!)>H0(_HTV`hb0oo7RfPJnpnVOq}P|Q6Ay~SGEb3
z^0@<aaIt`^qie2^``MGwE8;HgqG(Ss_YRdvm2eYj=~l}9mTJ&0a-Yw_JYV8wQJG8`
zmroDm%iM`0@UWa~>jZ@g?&gEwD!DJo;Aj<>vjUA*xD3jKRdX|1pjX3nC$5$oO)u&?
zZY!Mxs^?aEz<dL@d<jIXjocm1kZIz!@?gH1d;cTIT;+~Ggw7Ujc^}5x%I#kV>^5%9
zKagzae&GhR4sLrmL^`>rDD8fYo3R1I?&5wt1@&(3ZUtPs&Na{;x`+FEC)9hnhu6YF
zANS)#h}_`Dm;l{x<+eIuY6iF;QLJo`Td^22L);iKWQMuLpP}(4S3_^{5pGB;{Jz8O
zh)3fn_q~U}-Q||i%#Lw=W`Q=&4e3MQ1UEDi>XY0UD*l?{en90~(_A)%LT9*B{vfm5
zM=1R~$F<tM4}<r(T{l4HxhH=C=zVS+p1O-3a2-}d#+GMGK|MQO+j5NJ2ro1O#GbdO
z4loY9s5Iy~^4_E6krOY6s%D&d>*y|a;k`=H<fFWe*U;z6yFxKrH{OQjAnrUb%E=t#
zajdkW@!&O4^xTtILi6Rtd-`X<c=P_Gg{KeCVFfJt^0co5&5tLd9ouo9o*p#*Jhw(z
z3gAuELobl$szqNAZ;&zp!Myyt&^y7qb_7362+x^@6v{io1_|TUZh}ZS@0-UJ=#1cf
z_!`(q-mP`$jN<K~F-7w}q#gZ9UN{vboZ=nvJ>az5nm~hy<H@KJ;0*8Q9dIe0_Zw|;
z5_m7r2b~gmeiUU*;&JE-NalS``G6GOetM&y<*hToPAadA%2m>MD=B@L&U1JIRx^0|
zXJIFkXA=VTEZ*reFqF;XZpOfJc->mec`i@6`FUuZ<30Z?EamaaDd}{c_ZXG2U*HX_
zLSH`bF706pcuQ#cS;$j=2}?!1Z%UwF%zNl-46KB=E(F-6ycys3oR?cwRNHWwS3eEy
za^BVTz^dT!S|DG^d;JW!D&E{rfV{$6q=i~F&vz3@9dG`3_*u_e`xp!~@Z67K42`^3
zPC~DV7eRa0X5Nx-(RY>COM&7Ro(Bu0l_#OSSR3!Fy%1^VJ#PIkN5*?+0G2v=g%mQq
z#uHE_au-j!2JUwA-c|woI&X&x`aQg~SJ2nXOQn0ikC(9%A~$%4GojbdtDzUv055+z
zum^c!S_TdA_5@;HhjFE$?<VgJTFH*^mR$qbE#6BZbT!@P&HfFIJG|iC@M4s=zYsEa
zc@^8yH^v*Ln#XY-zZxbcc+;IQKgqNG2xwEhM`=AV&HF3@+zfB=VT^Z{=dc0Tb37jk
zh~DGfkwIaemriw!_j&s$Zt#G2{Cj}e@`b?^f3xFr&cehIel3+J+w;pPrRc!t9t7ve
zf8{H9;l#H*0}W^Xh#Y+`{NP{V;Zgpp@j!FsAE06{H$LMW`rP?zX~}+!KQ4fR2mjGT
znD^v2(01C3AMOa^&2Oc%ygvNdi&Sdu%b%q*sUQE(Lzsl){LgLRj6Z)NWxxXX0d(^Q
z^7CFsUl8AmKExBuXHi+%2|n)w^o8)X?|}>D@1O$pFuvP%NQU#}v>%S(PhA5S$=9X;
zEQ+5&LFH)v4kPTH<h!>)#CnSF{67pPh95&q@6-HU|HVuA%jqtP<J;0V8qV<doCJ0}
z|NCpOl)%4CVfIA+6fM1z_<ya&JSFq}DVUwY7t&7jEI*FIO6mMBa-g2Ue~C``W%5U;
zdLxV9a0epU`~`c^mt*C>NVixnKcfe8d5*u(2iSRh{!1X|`Q{;z3w+0S;deeiA{FKf
z`16raDCFBv2)BqIL}{^N{^OJiE#W8A9>0|T>Ju<=k^lJ1P`Jc@ifUKN_=}$hxy(Oq
zi@tLH<Md^g3cfX-wlS6bj#jW${I@?t=M{bnRdrPJw+X=2@ME8aYqk7?wD+vz@1X*q
zdj7NkgK6MbQDCN#-}NHQH}M<kl5ghk_!*<W$}j2wW()riz5H7Fr4)Q=<Ll{eYUlHk
zK|1*HRw1xE`SWjLpx5||j{~iXA50;NZvI(kSh~)C(gmPB{Ov2@Q!l^&5=b9E=uPO|
z;18BVq@Q0*hdBoL1uWPd<X7B*$Phm(4HGoXzxgQoZu0-8xX=iH?;8NS#h;|2qT77o
zHOe#H;dl6UyDhgyQ&f4J?<j}l1V5HUCi#*x@P3MKjRo{H|Dh~^&G3D{1DWOT3;~(r
zXHmrK9={hScNWd_!<+$mpTF*94DbOzs}d--f}j0>X(uSU0<a^3VM>753tptJw>Sv+
z6x?+bJZ#MXbrNiP3f?;lqA!BD2sY3z=BVJ{6hK`C_EvCif=hZRx(l{Yk;5@T&3d4D
z2o`<~XFLUOQzFAl(02kN-h$chVcth@y%xk*u<slA<S!UF0xm!>O3&IrK{M6P1PLzJ
zT45qsaELN~Cj=D<&<_zrD&cUbU@?^wg$Y)PF^X`(K}sA(2ug3lU?h$r0xe4LDOI{f
z3)+LgofLdYo9k18Rx`k21plMO+i5}dPXLP*Wc~~2IKcsmTb~hZ8v;tap!ZV>g(L`;
zP<kX$@b*`LNfO|5q`0>PbF@-Q5vVr+=B!}lKY&RUoXmz#X@Vc$fquH+?33_5L-4!<
zKr;nx+o6yp_~#57vjx77fy)sziU6G}u$ctPIl<6<=;aA+Q+)Bf;1fhE5sDO?qt<-E
zYd=A;KyZQ%=oShRslv8MkYI*0#R9=IaIHj8OToBO!4m_(z9{hB3GR|$mdcUJ1Y>k@
zUlycNJf~c6_X`-T5HwP3t5V=V^`BLOPI}Z|5&Y(XzG}f!lpnCx2!5yaR;}R47a>|F
zP*W92y`YeeI5Y_CDJ0)0kSs-Clfd>6EHw+Br1$z&0gDy_ErQ;3*liV*J_QqPg01xV
zyLLg;V`%IU+@Pmjr{G75HeM6NQb@2%@Tnv0b_=2ofn2u=n%e=|Be+Z%kX}I>-S2$@
zg9-+32<~^IuU~L+7>xshrw@Y+3Ich684`s41J{NHt3L+zO@UxHoEZ@uE=J!i!RQ94
z-xmD%EXHz2a3K>Sqk>Q9vb-x0+XH1x&^!k7;{xLw-(WBkf@oT7ObfhdAu%Jk-Uu=)
zaN?qIPT+kSuH6&N)3nVCI(#EMms`K5XrZ0(LIebl2(JYK(_UCXk5dPsXC^pDVNEoA
zaS|TBjvvHXC>VniF2XPWyS0Sh_rrNt;Rox`=q5ZV1d6-x_1B?(OgJ411rOowFCpS7
zjLZb_5)SlWCcK4yp77R3Xm2gW$b5xfFQU^=_yN5xj|&?Z;QWQJ(w;g%IDQVGfx^K{
z=nE1G>D?bJyuJl}CxpNKf`NqycgLeIR9HxbM`6Mws<jChK2rpg2w@1-jztP1uRt#f
z-zozaE&PnGk(0s%H+m$T64u56Ek<~ncK@e^UsB;xtZ*aUp>e`8`pwS>AE^KrFI3Zm
zDM1*NkH$oy^$Z4@B;<SmOUc6j(Lx|a_!d1R&k8R*g;`4#`kV%4n(!87q|$|NcEjHc
zVZ$XfW(v0-ro+lv!atWoKU?@}7qD}L@s#q&75?)h96l%PdJl?u!mE?$J1<;f1i2u*
zH4cS*;SL2RuRv&^vXMez<R)Mj2^q9JEfxkofcX;P#3qcTRQL^5@LUu&Q~2tVaOeUs
z%Y+B9>A|^r;h&VSDHk3}0%(O$Wedeh;Q?BRR0$tG2hc0Rxe{>I!U{@N)(9WU0a~rF
z?Q@{j3BO+ty?Ws|#eExuTWO`$D4c4ANRx0C9W7`UI{XQrT7@It;M#->sc4~H_{w>3
z)()X=2%Vk6XLf*G6K-q==@Qn^V7i5Ge+q-wg?m4Rhdsg{Ps58|;ipeQq)%A62QW8;
zrF5h93s;oEnE_#W3P1;iBYV*}BwQZ?g<;{s49w_F;r-`<G9ui#8Lr(DE>NQHwpBRv
zKg{zTVcnmQ85Jfz3;nyoFZ*F)OqfI4_Hp4dU-V4~7tq&4CWU|Yz^5tU06oX2g*lrr
zT{FTbX#GAbyz&P?=Y(on7TgogCd1&o@F1OZyDt>b+wTGH3Rtie4O1x3PK5s~LFW;X
zM<USdMGq+3<{+vQ0LD=?N3TsM(e^ta&Z063U%7~C3!rdR)SCnmSJB%PDsmI$QasdM
zw0IM^W1=;5$$E&^P)68OH2*LRdWkkrbkkeZLa$99k<S?n!dEnC<$(H$te*q>xah*4
z==2v|d>$GBqFy?j5GZ<~31~s0qx6dgi$<wR|Ago`oxceYZFvALROCtrCBj6Ow_q?_
z^nL{zBScY?Xp9tnaR*$K$dw*b(IR`wbe<Hs#K7z+(KG941s@}-@`220Q7DzM#ELfW
zg<_m&sRn&#L^rtbDPHt4B?J;g{`7QC6t#50Qj%!(Yv7VaPd7p&MKncW!n2}fwy=~c
z@+H^OM4Bv&C0(@tFDPV)YWNVz6pg(LFS0~yLumz{E!z7cEaiyaY=BdFqIG+rcwY1)
zMI<hW{I<fUe9?!gP%IF&*8!$bw5}SYNM!yNc8f*t+rr-x(U<hTEETE#1lUE98(njk
zL~cTmGSNrdKrV~;@vu-XS}1~gg-B6B|Cv%L61)J#Dp4NAH?D|^DZp1Px>OA>YDD-x
z0B$wW!|`yqPNZi-v7Wx5j9X1KJOhPB(Q2wSX%gM12WzvakzVsxML#+~uSN9jw{Wdh
z^buv?+C*da=xZ1KehnxcqGe~$XYCYCaG-xp#P)_vm*^A9Pj}<UB^<skTKhhn=@GS0
zgY=3L#$lpQ)I#CZ8=}RuE$tU+FF;{H)KB$}gQC~ysWl{eT#D%$7NyWT>85CwPHByZ
z-aP=!TcY4-*u5?Kq#C2XV-=0>h2p5_Sz7Mi6(xECdrWkU9xdadX!<<Ogy`!`aFe1p
zX8|)MO5X)CE&A(O^v#G41b~|r4W$BfPV__^8t;k17XoZvlsXUS`=VxwZaxrAOk;qy
z;tGmx+KEro*`On0D`Jkg@x+rG!8(W+E`y7X;#XoooW#%lx0n>4dKV%t;&-TY`>5EZ
z2qs*`B{U^&V)i%Ca~DU^65^QHb{ND%JVtLNPqBqQsO%-)N6$cSam7#Q^AX=_0Ou<f
zy#N$H@kT4HJCBPm`eWMs#S0&Ui2(7leHc@q_=8b693;+5M`N(q`$s6A5WhgxQDNf!
ziJ0|paY`igBE%2#&=)EG>}eQ`60fK5WVASu1-+BvTc2VQPKom##T>?nbNnH4S{#=P
z3$fx~-~Se!aboqquyjUz<RZ9u@yDqCT$CWbc^@QEoJPyIByj-kPm{%rKER}i|D_Gy
zS@G^S0Fx?yhyp5UV#NWVq>J$xaolQR3B~X-#oK5*o+S?PT^7i)UL65sp7=M~nw%G3
zrrr1jaWv)c^2JJuix-G}C=F34_V@+EEE4Z_gn?pl&^`E2BK{>2dZpqI=)+GJ#ang(
z?2`DGKOj;j{`|j4i1;VEV9Uj;Z2(;%e#ah;Rf>hBP^c2mSqng~h*=^iR*PS)189wy
zO|@3F;>&jMqE6gNW3LylbbvDr;^JrwrBS?$a%@fFf(NkFEDjlh$W?Ky8ME9XPFe`e
zR<V-8r)}c(SHQK4e`P|lL;NePwL8Uiy8wMn{A)6u1nd$A)7!UOJWCE=7njln)FY0e
zFjB90U>ofAiT6|a%?)vL2+a43V`$4dAkOWC!l3wbN@)&>{Wn2jSbVt#eK*Bz%K$wh
zR?&v;mbmqOjO@0!trU}RM||KXG>(d=exr2FU2(z!XpD(Rvf%!>_(L5`Oo$gtK_<nC
zW$2p{|4t=}(_%hdRWstiK{U>aD?f%$bK)PL1KK??rvYSMoF0xwTS*rMAM7Om+X&Z=
zNFMWod3#ClRS*Zs#!*N*N)oZHv@UXzguV#7&XQ*-wBRC{qFR%qlK;LL<0=Wi1~1$s
z(bX{TE~%%%9Fwr=tB4+wFDVV-DRJar^1LKxw?ofc5)uqaAIWig==e%<DLUvU`Ijoq
zj!W{g0p>3`ya6Zyl8r{_Spy~aA4O-7WXnDbEm)HFIy6p5ex;~Kh(wYEm{7?vcl3ox
z_ETw2xa0wqD?~`1rTufHq=M=yq9g{o8KNaS$itJ8idTSrO5(o;k}(oHUtpe=$S4yO
zE9s7dy*No!24?1rRT8-$PQ^<;%SC5`B%~9T5+$MZd`gn2DgT!&*-lfMB8j3uw>T>a
zt_OCiWbX&)OOp)KLL^<{x&mHgNN&@HJyYTy4aqD?5WOz5B{#PKI!99UCs1-FI|HF`
zP7*c^kvxfY@Ee#vFS$ptzzdS!zQZKuOIDo)Oo7ChguX(_?k9j<Bq?ixMzO?l3S5b#
zq!ehSlJ`BJcTsYK9v+t@duZ)kCi$ldD3>LEQQ*oY57TzKLh>OCV3m@mxfo!T#7z6U
zE0Ra7`B1Eu{Gf(Ljl@3^CTb<kO^~UR2;`8dmqfk`#RiGw1)w!bvT4QEBw^AO+$<Tn
z0B5dB1}N&#B1x--LaU_YBEZ@t=VfSYm-Nu<wnOqbm3ekbc4wpSn&jhKFne9nl1=wt
zk3>w%lU_;eUFi2oLfM$F8<IM@X8R=%s2*fMvfdUNgOVpd0U45%T!t6JlG_)da8r^@
z>*Em#yAgf2B*lI(cv~VfL*$O+QHsZmO5$mSc~^3=3to&#GHA;?F8M=4i;W4%;3*iK
zlw7Ci?35(T4t`HdQYl6?BiVW#8ncrAtALr4JVcWBB)#+zqIn5-6+FBzsil*q4<vs-
z0B0+GJ`)Od(p63{aYP!_2nBm-)f#XP(nr`3ag@62q2MHam`UYA&eG4BU|pml+K3#L
zHq%4eRod_f+;@{s9fMtWX)+Ui$E10*yzr17s)LB9bh8bJmvlcBI(ti(QsBx*8tsEg
z@Riy*0@F_#b`IpYG?-3h`b%Yh0W&~4R||zeX$~!wtU=N}^tcO_?x)EA3F##50z;$^
z(b6<jy1E($!=y^uNQ6r(eb5*oEfd41NU55R_e4p3>7^en-A3E#lhQ(pTc46L=@yTX
z^1|WMX=!vcBx9woPk_Wp-!6uQGtx1tnToec10Kc<B}f(Y)J&A-xuP>kdY>X!$<kNe
z1eYS^)2Yz2(rk*5r%IDP#F)~gAG<*zUFwJ7FUpX9nF*0hX+EvyvZTVp=*yPAKyj=b
zY1bGOa-}QpfIBBmd<h=rNk_ZEotIjFOGM`dsox*a&zD}NOjLn%-vd}Gl-9orm=bA4
zAckEk4W&Z|7o}&5KrTt2ME%U7GO3JmDVL=Ql>jZ5-h2~a71F0F&{rw_nhn>gq+wJp
zdqw&SCHkwS+a*x1k#29t%+yMIt*tOoCtXL^RlU@U;=m2k&nfKQD1Dc{nB643@*7CA
z^r?>^a#dP43y~IS!9}38N|hr(Ym+`k@s4(B>$7mXL;9EyeVx*?lz6))&HopDUDCH(
z;7qr4D}AZ$x^ztq#@QoXa)*NWy;8}0AbrwTUV#1$>Dli<`lXLi;B7$q9<8qjrN3PT
z8InFt+v{OzAFYFKO27FEjU&>oZQyQ67n|VPZRrRtV(&<UXh}LMeUe_yccme9z#Nml
zLd7BD(%b-eI3bO$q=O%m(iYl=O-ZBZQ(4o}0a^>sNPnfr<*f8KTHww}LtLP7Pr6PI
zOY_qEFN3=;om>U(fz*x4F>Pg^Yk_SiJ5ArcKO(cI`_EoxqO6>QESFv<j<Q?pVaQ3=
z_cVyJEckaym%5<F8Hz_`l6PU(Rd$}v&bi5s(e~P1mP+;7$7JlcfaW3lf!4sDvVPhU
zddW(#Sy<#P^Py0Ik4&%=Gvh1k?!lGdC)-O!EyraJ^fvUDeMD7K0kWeWFcc`;)QVpu
zNS1RRnATvK?WfQ<AzMwW{1BPX7-T|am9(D-lhq#u3746gU@1a2PoMvZl%>#KKT5Xo
z2asr4xC{DXWVa6i<+N;t2<ox2>11HX$)*}$_lzu+gF(d0hU_4cAZw#EdZO&qW3ZQG
zm2IcMYO;(^IjIy`atutIl~vJZJykZ6kD;Z>{Hj3GWk1teHba&}uewYb<0xRVWWyAq
z$d=U|MqiGs!49CgvQK|T-#OVVRnO(gCMXGcUbavKXD-Nopru~Etbu|d1u`p(a&CpP
z>K{OgWV3gnSS*_h0$Pb|dnvpqm8q#V`=V@;POMy#**BxFOy=MKOP6J91VAg7)zi7#
z3Rx+wz$#@OWl*S+Wn2b#Mdn0H#cG-QZz$BrcGFbW%C^yOUMHKhl19C3RRq`unSUHa
z8)ePI@U%%*wFrI9vce3we^n+sj)AtwK79t3T4fi1LSLIKf$qO{Svc*qI%E$CfYK>T
zrX9;QS?5j6XqU{H{x7s!_A}LZU6(nu0i{Q_%NruSvPHjGq2DK~pnbs&**j+F_shOq
z4o?SU2dU6*Q07e8f+3k~2quPQK}&&lQzoRZu8hcZ^!C3cTe=O-+?EX%pzn?><u#ZX
zl}&vMa#v<60vVIJE`a*DY)v1?gv@Ix$fWEQEv-MNWO-CTHZ42%CD3MMF3o_Mm3>KN
z2XnH79O&PZ=_%zsFT0)yOZR1uz6SC@_SAD|w3UmufU}ctegO3&@?2M7+skdJ4BA0H
z{t}3z+%q0vF7l~X7&<E7Nhxbr`5RmccDc!~(<isx<;&@d7RThnI&dEHe5zRSlsD7W
z?Ir(S0u$cy#4L#T$a^Ee`O06+MW3JiGb*$>F8_>bH2vl5pW$zSeCem?3zSd&0fiuW
z9+k8P%cbXmc|sm=03<|yXb`h)4V71)1X`Fpi%!Oe%k#ToK0^L9Z5t!yho%7<CI4h6
zG@|7k1Gtm&ff0b7l3$qzXpDTP0_3#(qgIeudBr7w#>wqgLgb8miZ)5{@(9|6CCHci
z!KXyIijLqV$&aOhOSZ~SG=WW#yVJ>_v+~1tU^i8MHVD&}CV!2R`RVfGl)}!CpQfN<
zro4elFtX$aVxXTbx4j329QnJ;!R5+*=#<|%xsKLxdGe)B;Lgh#KJe*+{Kr3lnJ>Ra
z@A(3Gz&Jz-<<^cD&{`y49}oRvxh4}_iM*ZS52bQjDkQ!r|AF?Bm*oCuVZKb>-w*xE
z^7oDdyIj7Vs>dtjpY6avE9HyUp|485p9h62a#cFitK}<h!%~g>5XG!&<=H1OPj&JS
zSHVKPe4&-X=nZo9UFbK;pQpEClYE&4mYU^TE<y3C+=VJ~TjYBe!cwa|@Od=0$q!Q+
zwq4%J0@oq`eG9lw`IcCaYjVYBAYJkWbme!;n`udKU9S2J)7&Fpoq@()dG{`Gee$vh
zIuLb3{@_J;(=T5^JCPxI$Zp6C%ZGy@b5njK9Ck<K8wbGMk{@b?$Zh%e*P(YuZcqbz
zRPIPiue)+B?JdXTqgJSo%XfJ~Z$kd21>B_kek1gz<ag);iqrC^9>vVe$Tz)0<wCRa
zXj&M}$@O#~>Yn_z53uLuAJNe6%P-?4wdjGoq94RovE%_j?Gzg*7kxzWFun2Y70>+v
zPzS{t+DbbrzBvqMoD{{hE^<}~j-by)F+q!mql&k3KwK3eT=cmq-oU9(>mql>J5(fj
zOmS}pogRv{0~m#;Vv;INy%Ze*K=W3tqsjvxg_Sb+z6#9-Sn^Z&P!jpLqW2Wk{S|@B
zpdO&OM@hp##rtzm2vRs*fQP|~1ypQ!La~Te{UM59X{i{hc(ECrHB7N~4cKr+%{<T|
z6w&n9id6jM123W!aWiO)R&-L7;iTdetyWGcvT2zUqlo-(aj8((f{Rt8Qg|Uw@wF?s
zGm0d-IpP&-=uS;gupR+PRIH)^Pm*FWEm4ydd33}m#j5!CTXddP*meOsRpB`R^J$7=
z`W`~Mf<b;~D7MRiovAR<OEF8)@+z>i6{0$j9EHasDC8;{Da&|Hv4jDIJjKf+n7s3f
z-znI9LBXL-VZLG+9f>MX9HezZp(38@;)@j4U?(_Ltf-~GGb~Ze_5iI^@xTj{cu|o>
zxx7n?D_#&SQ>?iT{mTmPzrj^1uC#)yQrOU4aYZptx$|np3M%!gQ6##+M6F_k1Ccrf
z;}8_;6&gQ?G$?-hFG8s}M)8*>#qR(9#G_f^kO5DxDo(LsutiZn1(;UFdr@d?Q}8#y
zwRXkR^sUkkMbdj1TBjnLK38;2QML@EOOaCry>7+F+c1{vicb!~ZjWM+_EEixpUa@v
zr`Y^IcyU8fMztLMiai?vJ)n4U7w!KB6;INlc1W>(7-U$X+ztJkin<64ZA4K^Thm(#
z8!D;0t$3CWCEZc1r_jTwqLzXMcNN)G1Tv;5rl;1p;(bqGPbg-az)dO+*g$Vev5Qg}
z(~2G{Kbui>Qc!(Xk={ff1DI13ctYl$;_E0lGq3nl2JHKa+-;bz2a12c0-CLIdo4IS
zWgbNXk0@(sxo)qFqfoAc@+o>NIVxAvqQ^<8rV<Hf<yU{hZ5L&DI-rj#?dY}Os&u3@
ziJP+b5IA?`$-k&v{g^VX7ib>J9~OdmDwkJ4-%A;N6qdY|GZcgMQGQ4}O<(1sF9OX^
z`FaE-k1KznP^`Z)KOg1;lo7O?3{*<L1PN05C7~}^X-BK86UtW_p&p_frW1FeN*Uz~
z!jw-^8KyN{xm<|O2<6%yu#w9C1uzk%oS~;?v~nL0mQE_$4}hFferONZVw5TLGCr*=
zq7`<ma)P2yamo>zgfq(j`9nQkxwQjan(~i*An8h5XUtQEG7IIwi*l54lzqrmKGzG$
zb5`Z;?*W>x9HVeqf$}Y?uPRjjKuL%S<<2PBtx|UHg2)wR5v32RmF;wO*C?In_o-Db
zp%Y<s%K0y$P_JA<Tj>U6@jSRjWi18Nnw5`y2+6BT*>Ox|i!z0F#;r;xsu^fgTBj*`
z+OBM^foP|4y)P_XQ+|?-F?A_@LNF!W%0(^EzpfNe`k+_&Iz3wYl<!iE@`m#8QK0oJ
zxALJdpcL3beNg#I0<edaVRlfsseFW<%OlE@{{;e-zXqc3wz7UD8t*7ywU)utQRPGQ
zfV-<)nvB*l<qEoz#+6Mu=$lY(j{rBRG}r=dO35+8(P^a{rK4t)tYA#(ta9TU;O;3K
zrNEw7YAKU?U%8+Uk`I(MbO6p)6~+gOohpg~5%#LyVz}*~8aS{Vqi|GJeh0fws%Tm}
zIjf?4pGsm`@0Vbl$5g{>AnBp{m)7T=DsKwkc&qX#?C+z>I1fx;74vg|_^E!Tg#2;U
zxo!}DmG|4Q9;C{ka^hfB-;XeRLKRP!T!`wq-RKKdZKR6jFx40I?vGSGPT9>U6;A_^
zXqC$PF<N6(nTz1XY1NlTbjGUgPzi0ks)PO`B0-hD7v>XHD=tAYMWvzQ#<QwI+CQbL
zex+)Y43#HEurpOrlMu;L-FY5duIj}K4C$O|@h<q3r~2(*faR-ROo!b9)thg@`$Cms
z+6tH=)dweGuvnE%YnKvL2YtWdlBzEbjb*AolEGb8E&MOars|-ue}(Ebs`so^u@}Rc
zY89UfjcQbXP{grTwLKID>r_jGFki3wf=V(PR7Dh^ZB~6ml?qo?PmF@JsP<&gzbmw>
zN>>7{Lsd#O&Yh~ADd4(Qw$H<v>#9%+3-qXlI-$|48p(!<KGnm!G0+>T&Gh!XrQ*k+
z@wV!PJc!&;b<kKwRg+YVc~@1v41Hs&Tsmt%t{SAGpb6EiANnR$9@`e+!8E0s2!qVD
z%5^pD&ZzcVATz6am>$b>sy@nO-cv2V3^K10Erf~tsx_NH9;kNOqS03U-jA4BJM~^F
z?mwbFNb3rFHU5JbSDt!5Exa7nU)909liKM`G&-vrDc<R##vh>J!E{s|^a(m$)q784
z^ls|yw3T*O+jqnKF}2(S*dFTGA3!|SKhddDA9ZXD^nKL~dMx{?4^uMxxSDws#9y7?
zguVdvYD!84sz3W227}bwJK<BX+K-lhq3XQ_a5PN)=PHnJtNJ%uEJdhove6l--auLC
zD77X9UPP-aDWP&w?MScPQ|d!&0UD$JVhI{gt2e(7{aE!sOMo4xwi$u?8MX5%{4nwA
z1yl}^s2*Mpg(S7@36Ny<8HyODsMD_i`mB056(XtXmkTLinxVF(lYW`%SvI&V^|_OP
z$yP@^3rjg_zeZ@}s@o_fa!$Q@6+FyS$NILPWmz9$U}6f@+g|}#k=jUiZ?XF0P>@pf
zf|~#-Qy-)t=4Ev;y|2pEr+lGZp?)bE3YBU@Hn=Lalq#dIs1=tnz18Z157Aenese8I
zt=gZKZ*}VaDyY}1wa<VwsQ0Qt8rAbwXV50~Z}jg5E$Wg~IMb@;oCI2%dYa;n?dsod
z!bFF<y&dE0QV-L*t6M#m4ZZ8?ifN3fM|~+A>b+{lO_=Xf|NJD#4fWqtL(;GA`W16G
zpl%L<!l3%M43HtU!%Z{}t1m8~yZ5I0t*d|;QLmy$<}LLa3mQk&d--r?T<!Va@?5Q?
znBt^5umF8iYS+t9m{!;Sg9(~ZpI;42v+7&B(Kn}FMF*+wsW;H!^?9|;c38Tvwp5_;
zfx3!TT1PYwXyIb7>2Rm8mV;)9sv#UT9NK(3Y3_Z4fjVmz(00#7)9DA$qngKpFhW;N
z*{krvO~X_I)Lql_Hn?LN*J7x9X@2+^CcHK52<Z7}?5XU+SF`gc5I+syADG8AYbhEY
zsCi{6#u=pf8n0RFqF~LVdohX=nosTlEku*-0xneZ+ix%tq1i~$gh<VygYY6sGeA+^
zXw5_+44%~B&vzFrI;HXO255}taSD~6)-;=-5UZJ62ZcDznn-}1(OA7O-gwQSC!v?7
zN!<#Obj_1q@X4B?sVBuu%?3|&W@&!116sD`C91T@(QGJ$Vy@<NF+|R3rg`u?Pb1w5
za$e)I8RUY-{VE*I*UY(rE70W7iHJhY7P=COG}gZXR;-EO0jxx0@PLI<%^_zrUes(|
zf#F_yPxBUqG|M!p8(`_O=4dv2E7u&O=XizYu}y%f)ClN&Q<X+d1$$RC8GA6aYEAim
zfYxYwX(3Rn*>?`4PP1~2@7fG}xQl8Gnl)`apj_2_Xn;>Gng!=zs8zF@ZsIo0>$B)<
z*EIbI(xJJv6LZn2SwfG#Ynt8nV5m#eO>2d2%?1~^eO>beRaEt84p0oGSJO|IW1r?p
z%KzNZ9HoMiehv2?$bjZcE7fZZYBI{f4r#W~IfG%%zGKk8sd4!p8Y7yoDL#5jGa?3e
zTeIsLB=2Z`_lC%*W($=S-_=Ozu+*5wOhMvt%>W+?6B?%pG)`(3P!M8DQ$Uqm)0*l8
zkQt3l4J2nZ&*r@dnR!jY49I=Wji)e}2b$%yQ97b6qi2u3)|E=n9JEJAKpeFLJrHry
z+W2~9F1Nn$C`RV0^?VmyZrb4$7_Phalg*GgrVZK(NDu8T%A<Q~57T<oOZ!eXJoDDx
z{Q?R;S__pL`)U`_W5!SW&n}EFK)a8U<AK_>j_@H!8~hv;g0&wcK=Opv`7|tqXuqOk
z4WZg^tP9Z^rghy8nQ-j}TJT3`?@_2KQfvPT(4w?Cv{;SSzVjIRPHM~Fz~E15_o~nr
zqqR^9?zGlL4$w2&$AcjmuZ^U4Zh}^j1)mbNoHsCtByH>jM3S{>HW);T_WQ>nc~-k(
zqZQ^;wK;!5CQVyT>;H7^no8(rX!Ab@m#HnI6DnESpBG>fvb9U5;98FMCas2YwNLk=
z@tk&sLh5<i{Y}6=uk~99pDt)^x5D3i?OJ*v7HH>2(O0N_noeUCX-AI3wPI~^8O8ZZ
zwC{ZYgQeR4(aZXxHf9|RUeX3pmZD61?JK}s)-DNz`{i2er_is^ay((aQu`I1j<3@0
zhyZs*+cgNuYV9^!K-Xwrbp}_fT^0nrI;|-kVD;LSH{fW4w)IIUG-`{^(LZoBX+L}z
zcAK@a%R#PcEfmOU(Z1>pm{zU)HyCWw9;C9Nb}efm&^oj^6y@yH&ZeR9n%39>v@WgN
zG`MbUJgu0oYvaDcB=l%EzKrSW)$aTXB7NFz+wh|eXb;kjJ*fRT3KpzG+Q%t>GpzmN
zDX=%St7+vhqHRur{w-}CMX_&dU)})4JK7A&{*G#^X;E}n`?@3i9n+?<fjzFZp=Zy8
zww5ZXCbgCH&ofin7wo}JYpW?QH>35THT|r1h8{0-THh{k_pDmMJlJ{dU=3vMYx%2y
z{Xomw3u3Dqi$$ZIZo~<rIHH>iL!-S;w-yE+bPOt(aMVetY}84|PX>y!ZX1Q$U36Qh
z^!KQ4c^AyP>V6Ccikoi5`ylQ*qY^_prrSdSSPz}m#RPp%T@>w;ymXiL1IAmYGhr}3
zy5Kty_0^@MpwUm~y$jrNUDG&-zpj>ICjq+pO)wFt<AuYSAYF+IB!hMPEiivVHxq)!
z5MAzBK!@t4JYhae7oHCiuG_f_<|A}WYXKaN)NTF|BuZCE+2?2-_X%jk=x)=p?X*tv
zD>PztcjAB@r~7&{xHGy%Jcz{W^px&O(AlnrWTMWv5nPgP7ZqbC>onnzOwm<QI^?Ww
z;~FTW>T*lbn5O%HvQO!{=^|QgX6S@3VM;S~Js+bpOJ`tX^x3+f_o6RH_vs=i=IV4b
zv*&cFJb00(%cHZL=XK3=fcJuK_%GPa*G1=G*abR{2Bc6|;swbfT|MQ#i*-NJim62B
zISR>Ao#s3mFY2Bfp*Y_q-4vz%%X9(n!Qf?`mBK>hx^_xyROo(O2uqbZ_YXm;bS4S<
zuIPSR0flPa>hHkS=*Eq3tyX7K2Chzbd?W1E>sly{+Mv6{Lt~>Ze+fvFPD)|^X5AyH
zP`IjV^`ty=i|*I|L8DcdNo9_0Ixo6*+I3^DFwvo#Uxm5o)aB-ZT+>}l!d!Ie!UI6M
zb(=rLV0v{vw8rYw-J=t<H*~9dVYgq$xdCoK_lgCQgSu!+pAP9JDLON(8*Ku)smmV0
zlvqb}pHlYfmTs0Fg|~H&P-(>--OsdR7}b49f3a{^cb_upW4i5hAC2pVPr<_p-3xyM
zbW-;OJt3xaH*7(sby~{X%;+L_fXwPXUk#Kw-4jQ_-P1W!z4g4#cL`AL>xQY2>VZ|a
zgBDP>`c^(n*y*3AK+qBW^@lMudwtF)P;}6LO_jus`jKBD>7;*-&Nevf54{T*7kw0k
zfsg7xp#o}G{TeUmx#>sa(CDtOcpc`C=@(MO$wR;XYbbc?4;Ev%UV7<anD^FOUr2*f
zKKe(J(dw%=6hp>OAHD==$MqX@u;i~l^fk}|^lgjL7^ru*2MN*_u7h5%zS0f;p3uKT
zwHP7#2lQkL)xS%XC}Db==YbinKd=&wQF=!Th(zlx<nKxS8M+Wp>seMh_8F@`7y{8a
zeY_A3C+JmLOmL#U>tQG+>37mu&@BDLZ?KfD|Be!$Ir>W!w#(I*Q>pbi{kM+*El;0G
z8=dp|hv|iTK_5zQ%6z?$QpyGTM5>i6)W7~13>E1sHUp(tKXbtfOC@?aW#mfrcWG^Q
zQNNA$M3?km)Az^9^sAE~a#{cMV-P9VuNMQRLa(4ecctF?J`}3-6Ys&`6}?gik!t<N
zvuLc*pIi*RT75iaf$H>!`{8}P-ZLN0H0YnCYpqf5ymWyaw}t*PodImtt3L#}s$YE)
z8ZG*NB^XnyKI|WWw&@#vSLL&;1FHeurGJMqE#3Ofv@g7_@8`j#9{n0hNA&8gu8{B3
ze?Z5ZZs=dR49I?cc?7rteLXFY2lYQt`ejJJfsT+4>tn;f-PG@+`1pw4*#!>X(tqv?
z%-i}td^l#&9lfa>+^Bw~l_F$!^&jkk=$QUNF3gYX-wOfuguaY^&`JHiM}an_Pl$)5
zY5k`wz|H9QQ5D{-zUUt~Gp8Tj3vyq7gQ5lx^m1EZ+ZqDeVAsx2*n*inVz}xHL-vMa
zd1!Pn+@b;&N5gk(t<Z2XT>b{2&W4fKA?jjy>?}Hu8bp-uaW(vz2sAgtr+qN!ZV1Rk
z-!a42l#22&4A5rA)9}s^`n(MMwHSoA;TH;_`xyGDXv5dg_8MLO29_0)#|_76H|%ei
zp_E;KVbM>E@URRv#M3+Cgkc$_&_WCzR0a@gs0jm1m?4(Vw1pe))A{=dL!ksBk%s0W
zfJPb82`1XGZVMDn8k#7EeagUX1c@>9`(iAo4W8>kVhzrbP>3_M&;j-{hVLob5O46q
zJz-sxVA%UAU=j_9?*lu@a3LO@$p*C$?xz@je;yiV4QD7>mTJg%0GDRSrJ{gz!<uCn
zc7`Fi5?rR?;y2LCGT1By$u^)~0QZ!k?<0_0!$LZoe$KFrR&03&XFfbUZ>XMwy7hvA
zH4XRk4eCp1Eily6wz$wx`5Zcn40)8pDmL7u+T9XE<3|`psp0t|z+5zB*ud^3gLxi5
zY?<M!d~lZy5A~z3-0<NrxC+A@#WyMqGOEd|GW<d>l`96N2wb&c&0&nX#%eIUfElVa
zY^T3OsWX&41TX3hC3~RXV5n5XV54E>yBKzp;a{pPXf_1AgT||d8}$3M7`~^n?^eSp
zx_{aX_WjUnH$>69rNiKo4@;c}D+L3(4etLy<hmjMH0<>lRySZ|y$0(J59s$9HrB$o
z8wM?%o$5E_P(}NIp;ik0LBn>Olvp%m_~KpY4;y-DU2@aV^#DGN7^3Lcx@9P$1pIBo
z*Qd~T#}NDo)JF}8Y3RFam>)&om|+!Fx{VubP6KSh@bd!Ln>6%Tso-_Wu!J6uvj%Sk
z^yds(%2C`i^mhSf-f-LvqW29y55xQeLpKE~Y>oXlK<tdRCt%`;G5R&=*&C&_N^vk2
zFMw-~#&5@9*U2dU7hulD0J=O}jEWSPKWdz$0FbNE^<(7a7P%Ss?1zlIaoZ`FIA%QX
z5zsu0I@+3f8n4n(Y%gO!eGJFjm`-O`e2ibOhQGeXI!dDY8Iu=+J8pFIMW4ShtriLa
zMmu_x1sWqLe-UInqe5e_anYOLP8jXX;6jYdC|az98tdtG5N7nCrER$JGx90IsQU+8
zr11kPb&fK!ub?s7cw-;t;-s-{2kf3Q&b|n=7~@*X9iKM((j6CT{Fh21;*6^<!TcHH
zrZSLt<Apt#<^-erT5yTRoaX?YWc;Oz{w^%pxQ~|NDaPYxAamCE9aVp)8r{b+QEA3b
zT2Z7M{qLbK!zhb_GnvND>k!E@J~IRJ*~WfaDdrf(JaD<j>9?SF&ge}AEP2M4ied1)
zk?n=P3&s~pV5rc@d>ZOS#+BP4Vl6iEmqEY8xQGfRN{z!UuyoOQv<q{2$#{%5{$<Ae
zN`PKAen2tPa-+!!q{28w<r0;~8G3tG8E?~O;fnE#m%&vV6If8MF{Z4BiCW{U>oJHr
z<CnB(s5ds#i@Cv=y#|tvR%7p3$TS%zdO(_uZ3>L=s?meO&n?FHjZkbgrdgoTX6)Sw
zXWET_{tNdzjH@!y*J=D+0=w6Y-_we`%Q#5qF}saVJPd{F#s!z*VUO{1ikkEquhQPC
z&**a$<c3kz0=<6Y;%{l2JYd}5``*Rn*40#2f7AFBRoaXgH+F*DGIpc`?6$H0ApE^!
z+()%QqsBi(P`hhfyB^~lGX}p5GH&!<0q6<i(roBW8nYIGOc_Hd?>B9XrbX|J(VyNX
zv&Ku47{i=VPC?mw#@8uhH*fT{j-d0tadZ=49vJs6fQGF}L4{m)rj7KNI%48vK*Qc7
zr7)I*sg`a{N0ZJLmRwAmv}inPs(l9{uBQEz2y-(zAHf{Bn|4xM{g~;Uz2H1d?5!~G
zY0_VUo|kE!YQ(%vTVJ(8!^gxhpw-u8D8;P#naU|_cii+T754g@GAJq#U=k051ez`n
zLm|ktl%5R1rswF{b;7j#6EudH+yh`R)RaTDonfZ)Quq{Z+Vo#Jv#D<f6e3OUZ-t>K
z)2mcM7;SnhnkrOJnlA1Gd&;!=A1KC{j$MG_Y11wWZ^oL0lqrleaVU>*#uQDT`G_}d
zq?)({Q_>OmlxW(TfVoUE#Zt9VvT5UW=%tuu=}mRkwBs=PQcd}kUrjT8KLfpV)3ZAG
zn_+qi6&Uz5vgtM*D#$YJqGH8t)8B7GBgd3kjltxa5@*nN&h#q1=krV@bT^$h4f&$)
zf@wn!(DF@zv^yv;eg6{77n)Rhh!mN|sPd!O^bTzjN=zHLP$)HhMLF_|rmMH1aLM%a
z+Zc<r%oLFcjmsuIU8Lov-S;6=VG<@nrqXmm1JG*IO%)ujF?pvzq}J3u39il*_B2H5
zO_Q|DXfU084w8+g#T2=1GBr@SU9;)*QVjd5NkL127Sp@7kZd*0c7kg&CES6bcB^UA
z<6t{X8#95{X-eAwnQNwhzXD8`>8C>Ub(<d0eS6(>k#4ab)7>IWaIeX)9oT)Q!6#tp
zhAGY&>iwpLltmdZ^`yg@LDLxuGY*;d9*4ifrpiB{aMRS82X4f)>JdQSGFktjaN}*$
zPCD;>$K<Vs{;28G%jmpok_ljG%%r5;?YOC$f~*s!6Q|+Yr0GL?_Dz{$C~iG%x^NVF
zGp2vu05@y0?|`K_)8eHtf6o*^Ur3ubxzbYLzUjbHa1TskCET_(w_9%m#?HLx8?Z;r
z<8*!4o3(8q4(4CKgF#304>b8sX6sw<!r6S9-hwXX?}K3CsCnf(5OFo{q9mxBS@jys
zyPK6%Pj$@fMyp>B^FrEDdYb#c1g4ky6RP|4HZwC|&&NElgsN$L&0ceuy%Xk#7ePP7
zJoYjyg_;>7uoPxy(V^;a^Y-u17-7C4fk>n|kv^jwWqy<vchTnc?&v#dUQv&}Q|1y1
zQOBD9Sp@YsbF>Xa&X^tCfD&)6xdzDu^Ohe#63stMQsgYj{OAsNnruFB1u`jS4J{?k
znm5ocA=SM8C4i=xf1}29b0RGTGR#lWnl{s1MOSy0IVKh+vdu43@FvH6#0gxkc{4ry
z&Y1@aAem=AGLI?AH!m4LV}bbxD%dVG|E;CSS&{io53t4N?i7fYnD0{|bE$bo2$+lJ
z%M{<gWNx91OPQJX6dEs^Z&E6t+}tn>y$W+49aX3_C+$REmHD#*n7CqoEC~jy&1I+2
zS7Vk?0Ik-1`&Ee4nZNx5ef8#}Z-7{v%*qb5Hk)7E4w<WF=NF;TVt$OmAFby8a@cJ%
z_cZ{t-Mrogq{Dn-3VogCKmUh$zGl9m#^iOG*Xp3xZT^;OQm>m+cLS`){O3!M>@_d9
z14^HnsRg-V-g*t=>^J8J!|cH0=G|1qGiZLtx2tlw^_kDmIAT63gUBuO>&xKbZSw-E
z{kvoCo`<1Pa{)aW?wSoKuUIr@&fks3ar4tukuYISrH$;QdF66gpEB>{U?ykHPto#v
z&Mfi)xo6fl!lik0WGuM*W_LO-@xc7?C*bTX_`C@;j#xg;N2|T%f5WirU^zs;vZH0X
z6Ly^}S+(GtEf45iql=|34QNL#tyIV1YMFcijc%65sLa*f5=R^NW0tWm;HZbikO9uq
za+>~u*2^+LFC}kFAVr6KEPvBV*w><ZmmXz)mO^?-9JfeI(duuBzX!VkmQ<?l542Pk
z!NVZSKS!V#Yzfk#@r31i5kNyMx26CZYFXO>OJSBt`ifw<<y<Ma2+KCwn@3uTXr&cp
zIYZZPv}J^DgOip&Xq|e>;%h@&vlz>zMF2f*8FRvv##&?)LXEdXegS6^EH6;pFVW)F
z3rCYI-4qZ?w)}Dg`YDzf1}vSmhy_qjwZu>$HqG)HT|nuUaN4M4SaRsum1*g|4rj6~
zAErPr+wvS;BsrGnexmbAg_dBdL@Kf@orPktC56^lB^C|~=1VOJzr)}~i>*KO%PcG2
z!FVrQj!->txy6^Z3>B7agaZ~;TAtqxkt>$?BA`@Tx(}nT#<HvkjkT7vmjG60d6#~Q
z2Fs{3`Wh|uOCV`&vV83aw%Ia5H`P^(g09CFi->BvTP^)*kZH4wP^Q1#GEfQg9TuY*
zlAV@4V%WWAdGi!T*kviAv|hJG@f1X^TM}9@Gd&h759+;^h4sMfvyAV<RNk;Gqg-9T
z#gP_s16E7Od!U0BnHr!&mS{T4HEj8OF%)lFUS9@>M=X1&KH`?;`%lq$+v0x`+#SpB
z6Ck6OP4!T?YjJ%A=Ep4Ja`-fEc{m-C6PBeEBbc=CXjwC5c~1w|W-WPidUek77wtCh
zS)MxI1M~Bi)z{H_-}0~T-!%$r+%u4Lwh5zJ4Hug?*?>N3!=t36t4#&P3EgZ;6CiTT
z#^E-m$;0NmR7iT-_)^%-%jW$dh<MxV-3Uk@o9&b}^0m1-gg!r;ZO?%mx0$DmiNDQ;
zr=S;LQ<nyjK%0kY&l+U&$al$T4Ys*OOXw3eYd!>8h)v@)3@OxRnHeO^X8kBgxQ&S}
z=LnnK-#{eNX3H3Sin95h-qz7J@i)MowCSQ1-YJ_yVK5kDW3B=@ZS&Wg5Q(+f=X<P{
zW&JAxKVYIw8Kpv#Y^uJ1FUd9~i@~MXJW6}(G@JNP3^U!Phqkd9HcKd0nQ5bv!@n$>
z|8sQRaamShTq{%SS6XV$mStIvZ1L{B_f*TW(rjm?sqJ1A1VmI2kR{5HDGJCGWP{4y
z8<im-f`EV^OMc%I|D4ag_k7Pe_rA|_$2sRdq`eM!s-2m<scCj{+D4??eMaB@yJFY#
z6gV^Nc$7AhX}4?<v}W6V+yY#V-H$<#nQQl%&4R`}yA#RiO1|BWB=B6d^YMW3*X&kO
zn)P+NCw~G<q1~Yu04%b5=O#Fd?Us=1rNr*UpU_ll_b>=7Wp)`9@GG}V7=iT_b^+f)
zMWtQ9e<u^W^OW9MZTIthh_11_ON&;m-QF&8snyx7^hVd}?YJ)k(O|cRd}57utH~SN
zWEVz1d9&SjgJ^59`_LD%Z`k#=LDNmUgQKwGmfazGidyZWDaO!d_Z1yu+wK1Fh4meF
zWAT9Bwrj6}p`CUg|AKMqvfCL5wcU0b*z{GEJ9bCk1#6F;`+KPEv(vUi(>=T0>5$!T
zXZHw*0lT~>A#~90qt#%!Z+DAMA;Wf=l<zcRXa5>1AJ{FR80M&*b_J{$v-61nZrpB&
zf>slDLdx`;v{RBha?0+PM6gWT`QnwZ&6%<Dq4SkJqv#;?9%Q7hMd=V@aVYQ(jFO*V
zg(Krr+D;s1s3|(&#PELx(wrI9l)B@>s4K=;9AVtLhmtEJv>K(OjQzVYqHYWxJ$T0$
zJ0FL_;|w!-_fIg=m!Q&}!Jzfu=E2ys0V+;1A}P4&$tXUJMlVJ(`SZOQ9~hwU6k|ys
zZ1Q33o`4u%#%#K$<Hr~i!d`#IFZ2(f0vO`|(%>0Uy8#bmxX}^r3`71btT@Y9^AT`C
zj5*67C74mz3PmA|ugRkqW@G#|0yDxHza;_~!RRJ`b0j11UEre_Mp{gw8IuZBo@Xef
zKwMyi(Y@M>j5!xk8O!L+h81y)tF%DHGj39(;}XN0e4Pml>04+^Vl1Lib239p=fV_*
zf%4!|8Bf!p;4;HzjfSQ)Mm7&5ol%<u+paK%_oGi4jO~;vo5|>)#F#8bT|E#vjI#w8
znOw$Kr%}pdq<;>Q&nUVAy#<WJHBfPt5lxTBHHO_hSW(DG{t%*z7zO@dDQ0Y24R{G7
z@j1vWWw_W*K}8v3cMpK&j3Ek*Rx)0spR0=T^oI~r&DfU>L=EG1E81!qk_NQZF=j3R
zSI-FD4bsRMb_Qu;l+dZTnUPnBv1nl|rd*mEjJI=9*~<866BM>FzBvS8?Tp6fFftts
z{tuon*WpZb0-fk&oS>Pyi?MzY$Q?%7Spa$%({xt6%Lt?6N-yJ2I_~r_UTJ_W_ZT}V
zQKg?T{~M4&#$mdXf1k0X6;=;1K3fUEFk|l#z(*Ln{zT~kW8V>o9%YQXK*|{7oj}<6
zkg>}435w&4<({x<g7L*KKuj@0)<VoQ<0o&}`-ri!1s$AWu)c)~d!}p#EC-ptk+<#;
zGm-;NM<!bZX@{8|+tB93wCw@FnR$#3@h;3$bP@Ilb2Ej2T$$1B(C5bNUXIc+CU=z1
z1jm^<-H>*I`7ULtxic*i80^8kM0vL-nF%5gFJ{A5w0ScV_5pB;Sw;sOALe&&g7`8c
z*F$IkGmkO_PctJTz!}KA5s%UtCcguvv&@q@us(>{IUmCn%yggwZzxl<mp&15j=6L@
zc*2;%Fw}-Kmr+zZg6Zdl%1EX!^*)N(`Wp0}XEwWnC5Cw<3zZj`1yQKH$b5->XtB&!
zY3+<-dYwgEJadXpaF>|dz642NUL8kUA~VT^o+U98>>wqDxp(#~%t5Kl0g8}ZW)96p
zFVdJF(+MG+d0mE|>k3m(cbzhrEqB0@#oS6~r)*}j5S%&8CCLzz%iKasR37t}H7MmX
zJILi<z?@H!>ubypD0q6EIYq9XLgsrpAVo~UA80FPmTkt5W-DPvvcOZy<T!$qGn>89
zSiw9)JK0L+xvL;m%t+cyRWnn*!N}Ax!$jy|J##KyYiMA;GzykRrnm|4CgwX79%^P<
z=ycb@+;AA=CR3FRa*Mf{2B?)e-3oi#m}6R~Z?`d%e}U`{rhyCmZRU|7G<Go)>Fw`k
z7SmTS?l7bJ=yhOPCLsGR^FRv}_A;v}l-kFP=?Cr}GhqdWtDiYed)5JFJ-G`8nGUp4
z4Kc6L95T#o$pFg;GwB~#@qqb<1)@ipHfM@GjWMm174?w$U?C6_%tH&&(Me|c46K-9
zihcy^H1qK-ko}0MXhho#^OJS>MeJEMzk?iN?V&S?18Wue^&DA$HiH~yy+Lb>6YCmH
z#LleLd%(G{ir)jLD{EvW+K#fSY%5`n8!PH_@El_`2Y}}|>vuW^c(7jI404k77=`LQ
zSwr6g;l(;I7xsFy^z&iwDVCcREIuqrH7xXF9Zy5apLIe4KmhCQ0(AQ{OZGG>16kD{
z0(XYx(Tmbq)(;ub7t9J<X+v!YYtzpthO(N-ReFx~#rLoxjP+U<D#KaB?&wSe>k@6o
zB3YqPAW^K7G;2k(hA6Ugo^@*hST3-*Z()EgvTV12i)D=_!QMF5UOI2bv%dNYZI@UE
zI<_aU_GLmt63eBK-oIp4QVI-CVZB=lX{oI5H^c7BtfkXny~1)@1Yia$>31m1WLbOx
z%wiQ0$!6`OV{8sf=>he*tVy~clh3+d4|oCV)qhdC%F2$1`fIG2PzbxuvhKt<6|$-v
zp|6PLF-HF`tc10X7PV5A2c@2tv3C8AQaNi(0NE9+rR00BWM$F@zKZp#8dg-ZYJ5Oy
zSPA5Wu4M`6Tv^9j`ViJPuy)f8phi~nTTtJ`iqWI8nYEm<?ps*DQI5zB)@d$EH(7CC
zq0QFHIvWVqHrBTTAnmNZw1MkjabAS%+pJj1?(SwSu%b_QSg)N%We@94K00%kb&htl
zy{yW|Q0im-qX5f2mYST`1FYY#qBO`-z5#NdwY~+ShgiQ;Ud1pg=U=dlu+$Xid0=BD
zP{?nL<wQ%)L)L;KNE>GbQ=aGqt0V}cH_37#kJA)OT!n5=vwkHv#Us|o6ndLssc5+E
z+2`r8JjkBl0O!EI--D7PJN^Y|I?Rrx0GtzhlGaOSHjmC=F6<X$z;c9bEBgwFqwKZs
zg2#<r5)5g_*e|{Xp5tsCo%T+!d%gq9N%qEYlsws8@1o?zUVI<2z1iu{!=_X02{St5
z!@lth`r^xW?}a9RHggFK4PbY40(YAI)w2KuvR%l5dWIcQh2P*Td$x`CT0!jY6F`Kp
zH|+%?ls)ngh;!_CT4}@B`OiW{IQ#oofRA8rzYI;0>;<$Hk7AEk0T9jR`+@U3JLp-o
z#ju|v$KFNu;RFC;+3(VomN@nnH8|theYF3(#15wn?gX|dmZr-@_P)O$Ety@i6JwIX
z-p~q?%HHxR5SQ66od9bZdyHo34E6}6sAaOhxdxUjws;Bpo6SxkPgf2*o<i5T?AhNy
zW*+<bx6q}0_Gvn~7O>aSqIiv+F$XNy*@YrlSjg`8pgnjI`@%Z#6tny6AiI>k<qZJK
z*tHt;shs^Uz5bQ#4Ycf6vCk<m7S-%O$mdzZUX%&bYS}++0;yxqzXRFz?8S5{Ze$B+
zpV7olp_IdB_Hw%Y)xr*?J9jtOH4gx|$-XS6J@_qlI9-iyV}JbwWVf?Tbn&=@?Hmil
zZFV!ch&$O*igI_c3*Lr>J?z9Pn17f3ya1$^J)4|0ee8xeVbeYKFZAN{v%8Go9AMk}
zAZ(Dmhjxnh+0SnQ8D@XUgRl{H5pB+F57?Yg@Qkv*pb**^J2L}f#@SoOQJP?fXh0^}
zKlP$=nk|n5{t-JN45b<N8}va^d(It7dN{}lp{qEDIL1Dd95^3Qkl`>#ln+iPjsv+x
zojH=Z0Jv~?l=5+ev*sFvx!O1%9K{G7<wVmIevETm3fAMC;czsb;LM}d-<|UXP1+tD
zr#Wal$*EfcG2Wb`|Dtq?6TBTA_2E3V2PI$5i?m1d<18RYs6S^#EJ^_!KKU6=bN)?*
zF@c=ro`9d_eCGr!f;jJSUPLjN<4HS{5RQx{=1`7*E=E0!6HTt(aE^Wltcc+F#R4D2
z>GaHLU1`%%AnPLM^oL-K<qY$Hj_3S*0Q{FY(e$PyaMEahkjVLg-pM3R*Z*KkGG}-v
zDpNShOLzh<a~946JdG1iABRlmtf+^AE1VKq-!nLWGf|nz38SD~4oAs@lw6Le9Pm7j
z_X~C?=5sdCdsD!9Djno1=Y_{S_p~jt?OYE;5ob1CKP={C^#D=A@unNbr5sTwD$6+A
z>54}==ZG&#6`X&_yI;u(Z-Cw^PQMDIn)9IvfEtc47^Ifdkpn3Woc(knY~;*OfxaeA
z<qzO&=44Z{YYV3{1SZ|!3_nZfkeeK&1Ypm@8S#9seX*_eDF8Y+&v2mVHs>#7an0%E
zyi4(pE{^;Po|taVg7+Z$4#&6~z3$=gGl9O#vC=)`Ue2?6!238k^k@%omac=^LC)YA
zl<sp9DVROP*;|hu4RgH7<vzmsVl6a0;AF3Z%u!CU?Er+1arV;g@gb*`BERFDMK=8K
z6P)E)uws(4a0-=E9Q!0lo93u=;C#f{^czYuoO8P&#-7`=20{;VU+)6$5cjkDC^>Mw
z={)MhefBi;I&&RghP^J_<#ey$2=~XM5bercD4<}~QSLGt1UK%bOq7ms7nFe<=NeW+
z#R+a6J!$UTRTHQ@$#t8AF`nG#DJ<*7{c`{~Z*I?aXgbB6RRq00+-S-s_vJS4fF?ig
zW6!`Qf3A>x&jH+jeb9EATT8x|Gu#8d6a_!aeb@sPLEH)2jRkXy=}Z;E-Af54q1<8Q
zbIdu%tv>_3VceOI!5Plood=;2+?x$(i{zTOgG6(`+XgGnb2B?pis3qx!n6zA_jJ&7
zk()XjB$m68Jcn^y0sUz4+-(ST+2&m0uIoZ=0#~vM_(bk`dY)3aLfR;%a=%)MLAcD_
zz6-{rap%(Nlg^EzjEyT?gw*jiaA(oo)=aJ=C3$CY-+mJ6v$<9_a5-EpeTglP8~H2D
z&gb5u54IF=4^ZIjD%X4r{j^=<3U32(oqK)-NFjIAUUamG>-shj#oTF{5lXmz=h0Tm
zefBW$<=oC;m|wx2{uY&$T$g3AsfycK1Y9+D2L}pkxNGQJCAHkfcmV3SuTb={p1Yz6
zG8?#iJ_k!9x1Dw@%{K1O^x?`D?#?!_-ry$F6L^#RkW%Mvap(UH(#rkvLjc>jT^ew<
zbD#VHdONrWhfsN&dxn;~PHyo!*mQ@xA|HL~;eI#^ZFjjZ($T7yn?!-`KJJx8AosXK
zeXzHmyYnaD2DtBi7X`#1H=le>_qo30&mZFERDpGb`|=9#JmC75!QfGD7!NAOxZ6A{
zIv3lPIm5C^?wZ9wPjT57p=g>L+z107ahLA^vFE)-pCdWQQ+y51L%g@>d-D#w2Fh4+
z<h@MpzQep*{vb{~8RdjH^J<R);KExK2>1~mXA?xb^8QHxiyQA09d(cKe#(cU<GhPD
zy6SL(mlFYmJ8$w+5D#7mz1k;v44QO2dGa4Xym(8nlFsqwy+oe9Q@kA;AjXfU^F+y?
zcVa&J7r^tUc<gCjG5PNUc?Jf^8J^!ln0=P_fhzz(JV6vR1oLju-IWmDvvxE=gz^?W
z0BacUJv!lp^P(u@DS|gcLCZ*9Ho45Bc=yO{8_n||zt?%*{s9;h!!u6-aDlgZJIF;|
z&I`cB@@~_r6VE$ch0-OS;|$;lJTom!i9De%^d|A%qC|~kUJI`N;1%IL{{+;h@_yu@
z+n0GqBOyDDcVi29(s`e>K}-g(jG_UVyjA3u$>MppgJko*p^a<~Z{#14T;3=-(DQh@
zI;hC!eQ+G4fcML8;I8uamB6NJypQNcZV~TO+Bp~V^4lmvQNlYxhw@V1$8;7d<IQD2
zVL5O2k1(c!*Fd|)N?vdT#8mMTD5bcX_ZThUHN2#I;H=|~IiQF2yqfpX*1&t|0%SMx
zmj4KrCSKDX$ZY0u1HjqBYcXO(Z}3cX0KLguLBedec&pc=qpiH0MDVopMp{5Rcw@By
z-sat)3wxbBj~D>Ecw$=eyLr#{qw)^V*$0|>c-`B;d6(Boxe~p+&>6J#@f_%Do&CJG
z=w%w<+1`VuLEexzI&q)3vjnCM@fI8e8Mg6;K84T`o*&)5eZV`}4%SiL8=nF{#=GnY
z#6#X+A3*&iZz-KSrg(Mqi%jz_(ElBI#9P`1mKolP01$hA-{(+xkgp^Q5Ap5jbF&Wo
zH~#_Lkzei!_+h@xiV=0@|4Kf77rsqNN5~`m`}Bso@>}e|dX#_Xbr|Eucck#@G5&^c
zA@n%^r}xp(6a1~@3wP&-mq4}$f0|q<p8OqjMahfrXoL!Hes=<Jr}(|sQ0c=DqR;*N
z^2;AX$&ddm>GS8$IuBd`zr@xCp{MyQy5=9q-+BgPah4xO`2|7z6JnHt`RRO=Lin>N
zq7%wbu7Qek{6<QF3*+}vWjOyd&3O_0e=^XgNPZ2u(xdnbXo-s9N0CeW0{>4sqF>}k
z|A~Ia@;$m>MI1jM+6MLU{GaK>eTm=O0AK>&M*govRHBr`KTwHMGXMKhAX52H((&Ok
z--)uy)A$}VC#3Ujl=OLppFpc;2H)j6^k(w;e6(fpi^xHk&3~{GrseQi<jc$D-+c&{
ze7=h>#mfu$oBUwnRldVskZXKnC^TK?H_|#^$X}2Nd=Wp=2l!&B2PxsZ?E+^h|D9#%
zQyHIg73wSaSW)q+@IPXst%`4>utGI|J>86{;ZIP`TrEFB2vW!AQ8Iiz|AGUZ4I22}
z{wOx`*EPeoCVr?Ch#UNuAHc+${9)Q)-s1BqX|0|A%pSCL@ZWz8y}!-Z(OCBJ_nd&j
zd;CA?WYo`JO&5^{_`i}9e31XI0pvb^CuNln@z+E{!!Un@Qr|}ShotDB?E(LfL+HgQ
z|Ev8dj`6=<44#Mlx}~Tb=l?{9@(KQ~pMjs`-*ZFd6#u<h&^yh4^cnz<_y;}#nc?q$
z5ta4=_V)lB6xjU?&O?IJ1?ZWBz-bRE9R({EVJHs^-cq4UPJ;P7^u^gG7}yJiE`p~i
zm-C1qk{)tbfjb4ljtWv=L$}=okre+vCRphXF~<c-8zJU|U>Qwt?gBZ5P(1{ObErHi
z7(a=Ur@+^WHZQ@v9{~3j+@&M>DZ!W-gYP4Vih>kh!A3PI{RFl*X-W1M_+@|u2v$4>
z;Aug|MTiL$SZESEBbX^g@6QUdXekd8{4xm6U_o60DnkVS)Iw;eK=3+*o)av2AAm5y
zfFI!D0_QKm86hYe0ZXJ{WI2W;N`UX6U>y<U>d~e1g6C}Hsf!W#c%Z)*1nU|xG#3Tc
zl*JV*h@gctPOyQlJjDy1Ukino1o2F8CJ26{Suau0?+=@j1Va=vNEY0uOvMzzhnG;9
zDsaw%=*t2VZRFDgZ|wpgUGTwfRAvgcF<@wxz}=qC=GlUdDOi&u$fP8KT)`Ky;K>u{
zWoXM6tcd`=K(IdxZC3^98)4HmL2M^V*9H6mXetzV(%f4lc$QKEiUs-fu$2f@<o+%d
zJWDCuWrBSAZbG@>Pujg!2*&A@S1IWJ@BOP1h`Fe(7JM59*)@W_6kMqlL~Vx^b%MQ*
zAf{e$rW=(Ff=AJ)Y!vXt05l28Z$M15pqPTaEduES=)EC`w!)^Hf;LKbz9l&JA>gfo
zv-Pl|P2k=J4ef$^<O=K%Y;vIW@3vs}e_4fsmo506x&*U@XzUiOp$PvSLC9AS(<6wX
z+X{CDOXypXy@G9&z|<!YP@>5_!JG6Mp?<+r^fnF%wo_zjQ1CDnEcXS=8i5-UObwwl
zEZ}SfU_{`M50(c4X*~?JjS514g^6Q=i7N0s6ud)@hH=3T>fwZdOMB=^!HzlT_LQLc
zB3Pyc1(C4gk)VLiRx^T?l-_MGTpt9$LE(wxU^ygAqe!QN@MlV8a}<8|Dr6oO-lJo`
zlkkJ@z~U^t{0~fXu?cGzqIg7TPkG0#!bsZD9~EkpAa24J=(9`5ggtJs)Lr--_6u`7
zgo~$8c~Yp1Mt?npUsA4zm++|t0C)>I<a9YD%y$Eek5EeaBfi4O|8hKp4fHKDf8m#u
zdk`S}m-cw4g*I<Wzzr1Mp!fcaa34jO&I-dRmnKN~vJ^stg$rIp??Z%-x1%joxK#(v
zb3*4>u!ITw$@>>Bd~rKSgwSms9)U>VUP=^;5-#`}oYBG;7Qp)R!VVSMVuW6EFbEff
z4_v@<QMlZej$*9v4+HRV!pBF!8ZX>2AF?kA{~keQg3x{sN{PbPUWFA&!t*%m%t;o;
zQyNK%a245<D!fA;*vrCpf3Tzpf1ZoBbm4s3k6jUdN`CeXVW1K$nL<TBN?F3Czd}l`
z@cm$l4dn^P1~3@;!beIBO@VNfGBmFWfB6QouL=F4z<OQy<Uha{3J0zLUnCrN0j^m1
zVgNLi2p!0UQYxH7q17^BVm(H*T)0S&$_k;~JP4~4s-6eDMz~c3QY-v{!asGwt#(gi
z{i_!~P6;{<!X@coZ4^Ga0kWHfFKJ;+v#{+d#Iy)=C|-3#SV%cQH-)w2nz$vLg}*ti
z!nIq#(k67E4Dfbg$vjkc2;ZPviMNG?^x^PM;eL9?yM(s~LAr(EAA{Tx<{{bDHm67U
z&Mg4%3a92lZ?CX~0+4;e93AlYgtKPD(thEyo1u3=xP;<HgF+P-LhlRP;?OoE+|>ro
zVd3}W2pSQJC@%g$c!oaGI4XRc+*o76b!6{D;T#T1<HBZgQA`NG?!?b)n-tcPzi>+U
zhZ}@W3%6&ZqmP8_&ET04E<6F#>_q~)x^Ylsxed-kqJ-rbbq7&PHvo>J?`SnVEP9)s
z5+~8Dg=ljYEuBE6izsCW6dn<oC}iR)djB_Aaa6?I4GY~wPh121m`xPpfvz1FJwx9n
zIw5MxghF>wCFKu$h`O$z?WAY}h1)zuGg3(N5`{em)4WBUZ=>y$D9#m?J|ZKnc)p@I
z+GY8P7S}_Qzi7`-;0zGW-U6FWi~iaLD*{D=0kE7AMK?j_S&{7xN-7Hy-J?(b1dH5g
zFA*ZTu>mHAiXNw1w&9{*XflWp+32ICk)l?50ir}sXCX9N6!rls&x_h7U`&kYFG@kW
zAUZBW>7po_5`SYw&tE}hoaiGXO7WuMmm%|#=qo*>B#749=tPnz5*~w?B++Ve<R**K
zgHcKmz2X49sUkZ%;9eH_Q-W!l=<}@*lP;R|EiAkuYI_Jx86plHA2UU)1>npQMYB=L
z7Fpa-$`LJcL`QQ)p57pNBKv(1oi8f(gRlZo-Cwl+T@`Kl3uAIkG_wVb*F|f{hg2v^
z*aj6vqV-E4typxS7NrtVelkj>qAvy@yG&%FaV{5KqYv;@h{TalQ7L-H4rW)03IouW
zYEhgEEUXc=yaYwHqE6aNH;C>R0NyD2AmVYne@!Bu3xLg{CEuX2MYNrg(Qb(B=`$2J
zMYFTPdP`JC3vR2ZX#+UhM7PsmMZ0K9jkXTav!4KWTXcq&*iKOgeRQKs^w|bfc8fOi
zK<<ckPJ;A^E*T*6t|(^;rC!k?{9hE?oIX*)If%I@+D_jO>K6%Ubr}%ZS3=XE=ylpc
z-52FAgZV?EPTEThiyqRRcto_3TqF-fvnl>MDjJvv^<$#tbffN}=!IsC;kan-DF7x!
z3tvOqr0C90D4G&&BZtYfXnrwpwnw6qUqjlA=pD*NwikcTMdLxSnF2<K#D#POaS*fG
z(dH;#z7^6Ai~Z@&yOa17MH!vNZm$C1B0l^+^d1q%{Q(wNal>p3&{6SQw8*%LE8c*x
zW8!m^cyL@?s|4<ZIK2gx?l!T*O_<>!)-%9*Qp`>T@f5qz1K}mU>w`9L@sCQ7Q{pvr
z9oR?wGsUEQ#dY68jGuVnDhTx#OKG|b5NDCU=CpWDC8Pw3zo1;WGvX7Jt94fV28Bg}
z#Qx#1Fj(BsjZ%o%_63EHL&b}|P&_AI@h1>r;;mmmeYp4*dG;g3IVaGWXz>|xot+m~
z(T%Yf@ei#q|AM%SoK6?TPD-ec6=%Ky5+^=9A2Q>`k5ky`l6VsrBtbk80$idvehtPc
zNnAM#Bw0MqW)Is^#J`ZUAyr)YEv&dKp7<KF)5Jgj2{Gy7t@H?75r6VG@EPI{God0=
ze30CTS>nUwr_C0Bb^|JM#5=M;a>bWv?~*4DegP`-#hfo8vq1cF1=_BP<8z_tn%ILT
zuj^tygWRTt;_a7!C=!37gE7V8&t8GT67ky{3__`RQ8`qUiG64bRW9yug-sRW)Yl-b
zQk+0n=c~k-^xjvCmxe)8jW~t{nYH4g9bl;wyV7D@FaCy}k_PdKJK$^-chM%GMf|*y
z{4Y1eeU!{`Q#?aSE4RcO!(dyhcoT&n+QgCvFs)tu`Y4R)5WiIf3vY`Je?Uy9_#~Ys
zyTr$6v(+u``52n+h&Q;x&>r#1CP=v}euX}u(ktHH0@5e;IRe~0@w2oI?H4bLqxWw>
zoJAk%92B2=2L|64579lLA@S&kkTxvVQH*s&{5>VsJ`n#+dyrA__vDKm6T2iq??Z7~
z14`rKQg^gXh@1DKa#H-mT~tnqKdFF))8ZP+-gqSTr%ud>g&xpnFL}BL#CA|JhxUVq
zBo(xOb&zac1G^n1EOIp-mIRS^-AR&g9acC?gtU;jNP21@?TF;_#Q?ZUzN1h19+mt`
zKg@9ni!vZjNIu>VE8Hb4x<Bk8;k2Xjq~ue|I`ouuk?X-r;&vB9;%$>i7Xo-nqW%W5
zeI(!h3E94qb#I{2PqL{7D*PqiQ%3_Nr3X+tE!jw$tw72DzCwS4B#X#b5iHsME>wg_
zwzI$)Dw%!;T{<V(PriyU$-1+U87^tDhlU8rfukUik`F^6EJ|XVBL7^p<WIT=a9;A#
z_h5~YR8utef+WcsJQpS7bI|)($#)cNiIb#oAUj?n-vpLRlDAg^mmv9m5;i4D4$?E1
zBpLn}GLt3Wg`sCDk{4#9GF8ILhp@|%o9!s2Nyb}&OPAcUJq>ABB(IaNBSXSxLPe&e
ztqMF@l7BovvL$XmfF(z=gr2Kh$--a&^CVX(_?9o>Or!S&lF~_7cvZ5HG7GOsya!Rb
zF1b4cQYg9q8)OzqW^(~3miW<eszfqGA6+YzoT{SzXPKms&Jg92ZBtNDDN$aBiYiIS
z;~>?NDk<7(BpW{huvU_?1T1xuVKw?&FKMDsOoOE79Hcc$wvnf%Niv@XxLFcPQLq+C
zEIB@JNc;$QQ^KSW`Yp-J^I>+YWWJhmBRV8~6pg(ti9Zk4PD%B02<?*Wb_Bj#Qso1o
zcO;V~K=ep>G>hDo?4-xCSK{ss)A}ThAE4X!B%(E7>6h#hpfn(1xq)R+^5`W9yDv#=
zg_I#l5j}{*lKt}_Wkm7<d;ToRoClJDHvk-!Op>>5O!79lJRVA}Pk@X|o_Pyx6OuOa
zZcIvC%#b!E`NtJxS~9B?njT4Zd5%x5w2jji#6eo{2u+UCY}yDNmL6ONw3GCQ1hhFz
zuaMiuMY^j4EJvhrify_|n_dLxQR(R|kmV*lO9`jPq#u`n<+zj|2lxr;dlXT2m)0!@
zz(cxq71~Zp+s~sbp3>W)AYRhr|NUnKZ>bmU{ZC2V($QTXX?+;_;49_+3iW={F?v?~
zr6aGPEkOGG+aRZ<zM*IflycvJ`ZLlXN)tRQ-INPlkTi~*<iXNBa^QtXIW^!6l{Qec
z;+)j3A9};2QcnQFrM(K8$0MYfeh?EWo%#rfDCv`wOB*fCX2bmR(qnWykC9IJLFfhP
zI8Cb;r8S8t#Y$U(LE@zT@sJ%a9li`rm!yZtTa_SPMz39>bUwY=Nz%yKC?!j8kk2?p
zx-$zTRl55Q&EuD){dAB>lL~G^Q@V5?g*mQB?I{B}L%MG(STm(*r-09rzCkYjZ0Vyz
z;LMSp{0-LUN~dXlDv-W>0>)gGis{ncHK~#uG}om^^Z*n}>rbJrNa|gQwqj|@A+(i9
z-)o+QdAwBW9Eip;=|}-Il}p|JLJupX6?9;$l!iJ%Q<ZdH1xU5@6#1TOq}|QH*GgC9
z08l60KMeKt(nA*kXpoNg!|X<Bs0HKPBwam@wq|MfCcs;y<HKmXA@#EZxhZ{|w#l|z
zQg$wYt<r6BSlT9i@i_=>mwrPBrw(cG`w(+my6Qgkc1k_YV1T=%DQ`k(x0Lf1thggR
z^$09I(hN_q+?DRChR|N=adMXRNeBOX!=!O8VCk2xrPPxFX##n`2Bn9dfw22F>67O`
zhoqk5tR9v=PAmF|)a!9bdmz2B6QxmUJtZNHN#ocUy@%2ux}!BNl{|vI6VfN{L)xUY
zlDy+n(yx!frfKO(dfgvM1D8VPjC2DJID6UHJjgsK`++_tc}Vu-J=o+RvmLvHT1T1Z
zK@<<mj&BCgN%k=vew}6Oe#aoV$WGAuend7`k4jhBU*)JgD*KUkB5pFn^MD_dt*2wf
zaoOv)z;Z%XwiT7`vIAd1uZQgL0a$-h_T?%NPubKIIK5<>R-o;a%wnat!$<b;S=j9>
z`<7lVKiU62glvCVLpn%+?9LmgJT2qUH;V#g9{-|GXJnnUqMwzu&>f;6*~JKyf@S^x
zIXq;0eZH7I8~+!THrC;?&2;A@LY6^0(@2>}j^T=uy(d9Gqh$dvqV2qF7acibWFa|V
zxgawYpmb3t7y?VI?4=hVB~G?H0Jg--9BI0_B-`4GwglNMCTvNRttVG%lC1ell#*p7
z>1a!lF>N$~r^=>&MB`=I&X)j8lNl-5D_xdi57sNPt)wDD_6HrYGG+5#2TPXh;c=9*
zWx3R|9GQ%=opNR6l>U$>6VTm@eA!ak$QQ`IBv;N=8H4=p*JSdS0JttY_6JysWH0pF
zprTloL~l%q%$H))r7~MB5M{C*bet)dy_5!p6*Av;{4kX=uMCu`WKX_~Qnf6feu)~H
zJ)Hn*W!h*MS|@v%p0#?}3KrTLWXea7(kT0$(kh!|r(OhUmW>?%phdPafWEnVL-rbd
zgYBlQ^JR4VmaLL|WvwzLO>=Fs7RoGYmo01nutWCF9FW^GF<p4+l>I};kuKQ=3cq#B
zMkwd;jx3}O!g^%uQ=#InY=T^7y|U=TkkTh}DF?YH^Cus7zs!i=6+1*(^!qS)P<H<~
zx^`c7Vk5?4NY+9R_pmJIDr_2&C2R%afoy_4TQDly6AHa!GS&<@AIkn*i?(su1&ZWP
z$gb1Ad{QR-9hFnEXLrDgY1tCmTRoCp&jQPgOx6gS?B$=)+GIN@kKPUHDDR>Ru7~CA
zzEJ2S|Mo`^XStkSLl=4K8z>!-pQi(&t9<Yx>^&+!atXvu-sTIIV{$JsO2_3K@`s&}
zbLa%^F1OI`-b1eS0n16b^(ac7^6zNF<|QAP4@12llkfBS<q5n8d)%SkPrj`jwf^$$
zE1)nyzP1SDv^<iww1M(tU!d)b{2Xm(&dN&%(H111ph#J;{IM925c%W*$PShJzKPzS
zlaG^QHB7#hTsh(Lg*2l@$Q|DXJW_u8EBumC@+J{Tw7k#uD(HE66Wz_cC{KG8Vq)dr
ztpOrV-untF<K<tG&`WYT?eY`k$H`BcC?Ax=>?HXP$}>rpC)1aXQ{?&ps7RHs3xQ3S
z<?>~Kr^)~R8Mt)$Fa;5=$n9t-Gvu#CK}x3FGHpX`mfY0|J<OKxUxC^j`BU`b<;qhw
zLuj6S+Xb-X%i}L$EDPk9qA<=^<s3TMU6V&p8pU<_nu916%0K%QxFY$IS^$dW>*$>>
zk<T%JrBwbSJsxH9WLjLx<w^FCQX${ApCV<I@?~!5OqIMR1m;)Et0RD@k$*<hT&?`{
zdWfl$|FIrz_40jx0pB3k(E8ITcfE#@X_6mC#A{Bod@gzHTI9!Wg5`$%Z8G$xT;UF3
zx8#*h0JO@xDP-Fw|LZbX+U04c*|WHFI^?g@VeYp4NhMTt%9~E1@s4~r8LU0>7fcwh
zyYly9A*NUELXNvWdDc%L_vEvEt~@z=we9%|;D+VTtbzIw`AcbNdmtC|LH(%w3^``U
z<Q&Qqc_>f$12V_uz6-!IA>TF#GAaLquFg)$?cE_|T3$riM33Yvy`XkRzLNpCy&|Cu
zEC&@2=3xvEDLiSI9TcA|z`!^vx@_kFJgm4vhZ-kE1ZA2!E5@oJ+eI;#wjf6o6;A^1
zs^GkU%A*Q~7fNo5+2qeUrudRBtsYlcXw!Q_@hR<&d=-mNL9d^p;BgRtMecXt3{d#f
z;qSB}_bZqdsA!~M%NfPj8!6Y}tYQmIWkHJB-=Gw%_?{B=LKJcCP#>z;Ng=^=ihnwQ
z2vaN{h0t(C$Cqe}P}Ibt7m*4br2t1Mu22?Jv|?2~j5)6;u?LA!Z2k#=3ko%PTQ4e(
zJ_ie975hF0iBoL(oxTkauaJL_;w41{ANT~tzqCI{R4k?}g(St_l#iCIXnP$jDT<T-
zfTSu`(lw&XiqAHpGii#8&QOuASmO>AR}`<%3zwmoO{tHWif3O&&$1NlZm7&w{Qd+w
zn4_3Qx0v%4fp(OlRG`@5huW)(bF@LerfB*RLa!^De*(Txv7GWKiWE;NA*NX2{RP@e
z6lt`5EK@wi086=Ij9fVtiUV|&wNkOX5Tr`6FA*xL73pIr)hIrCh`!V+?C5)Gb&BWC
zg48QQ80gEg2E|QU8ygi?+R-;DilgzYH!B|a?3s`G?H<KN+ZFjaKy)ZJ(kgsgF**W3
zry_$w>RpO*D=h3*EISW{cNE>^UG7mVvtZQjD%>b}rB|^x25o(cxj)0+dx~SH!P2jA
zqdb)X#am5~IjCr)7yZ5>nC>hNDIDpM9ac2jR-ibd_>wNoJWwpp0~u9#Q`XCvV%{tm
z`cR>J9j1*dHq#Y}2}NKh0F#Or^C5Ifag-bt(~9})A^VY{iidHUQ8bZn?V!?;uBjYS
z{v8BP2W2XG>YS7xg`mw@X}*r0xhR)9(bIWE**pSPS7n(6nvN=;-UM=7$u9=tgwnVG
zEbhv*FTvuev{JO+OS!ucEZ)k0#3-Fo=FpGkqx7u>r?2w)r5I5^C7W*0_$xE$c?wX9
zx5Mny$~f}n2P$Vh4fq-5mI^vSoK^mhTvtKL{U?D4Rz}b}5~A#*?4VHPG#v%cDL?H3
z2~)mXh8~718G&evP=?VW9I1?xKw6YiyBBTI%6BOyeO@{FH%N?f@D~WXpgcgSFc+22
zN5ZsN<;SaFOq{Z6!<<>4&xu#2)4O>|xo7|?5|qi5<eaFS-i1<<(zh3~la)`0L0XDZ
zL6@&mmEVx>=d$v=4g-{?{Dr*e=}K-hgkDkpF%PC?DL0a9FkAVzPwUfo$o9VrVfo6Q
zI9O4j+>iz-SCt_lFzuSstr6t9vOgOvh03$ES1M9&p}j+~@?||pi8Ag6NU74119+M8
zQ7RObE7y^$xkC92B_~%Z6)LE$Qm!T+Vzttm0hu+*%d`WpRYur?0jyL0bOyynWejB|
zHYwXa1W&W_8tqwHlr~CbxuNu>8SSQWi1NH{DbuQ;qE#9B7&zOMYsS%~+sZ+5taK{B
zu!r6*<<jF|8BqSZ8lnf40&-s5SK@eyhg$i?2CzI(vKQFEGpd~X0UF1Yehtv{P<enn
zzvIg6=TVwc#!(LYv@&x6$RlMob?u<aovsrcQmtMBF%GJC$y4U2>U#ikSXH|V!kkp^
z&^+$0>Ub4WJXE`~@ZOwMty~NBo~mrR8|0<BmGRUUcve*j6n;LX@}!g!AC(>X2z*tW
zXk`6Vyr;qHuew3*?*Ns|0j1NbCFBDMR7KMz;WMg!8p|NnZ}fBps}ir{HwaNhQ^Yk?
z)#y|C41VP=y}%izTAzuwXq7JqZRb@-yI@+3%85qif@*}42rsJcQPyFsYF;r|;#56J
z0K}_eC4gU2tqDe3f-3ZRloD0z*MlWVl}zrwWL0b=`jDc!+Xf?2Rgcm6FkSV52%MR!
zHMUw5vsAx*0+Oxza0a86qk5md(vYhv>W0ufRVM{N^Hu+9&{m-O-$n?%s`_RO_-iT#
zrDa}Mxx2&ALX{(BGZd+c_5)X}V()|A5|zU?07_MF90p67>SH?1l&emC40we~YqFtO
zsXASQ#wt}Ng(YiMmqI~qs1|$#gKw(r=ArkuRG(9<zg2bRZ*;9qb(_+c+Ev~iDBV^)
zxf5-jDr+-1yHs~KKw-D)JGyFrN9Df`q(_xSm&ER>ZuA1zt15N`;GW8P7fmJosw1v2
zct90Hd-g%qNgB)hDsdvz52*qv7Co$bvJ^r`RC)ANK2YsCfzqhzMcOovshWSr$c(F)
zbenWSwS$&{NtN~wv`wj&EQE#ADlaBF_((PRH$=~<6h!RRk7M6un{!Z|m5s(j>g5LD
z9n{^w0qCgy@?TUQR>x49u#-CQE`&O(WB0*)7xhzrpzVk{#2=ilYTi>I$JJ`eCUsXw
zjzPAEI(Hs=cv5ZKjW$p93x`nYrA{Pou(w*C2~J=2`5Wkq%}@Oj#RvS=i`bAIpiZaT
zf2Y;FD*y(n$Autg)H|zS#aVSnJ$~&VbuWD=Ekr%v275!*oBF|WP8~)O?J#xhM}UW`
z{a=Ur2=&@&m>sEB&~7<O?HCRz(dv^2AmzOJ&sPA5v8h)+1~C`ZpP4{n)j!eH5U1`u
zj#9k(tQBG|sWY7+G(kO=u5~7<%WpwwvYJJn*A(?<X^@txuDJ}B%j#Fj)t07SK{;#b
z>dT}sL;W*FdNS2}S}<x^>L0`?WvkzO4^nc}wpu&bma87JM`NDag%1_i)y;2WEDF_g
z=#48<7tyO-tiGv(>=Jd=V`wW=o5)j8uHMj&whHyD4QQ)Y=kWlqQD<jCMXh>-oG*3i
zuHEQTy?X2_aE)qj@<cYNH_&C@X0^^{2QfF*%vaEOOFh?&&a|orX93Zse(Vy&w5ua?
zfap-aunLIV>aP9Z>{4g=g0oxw<pL<YqYkP=TaWs8@`c=0H_=YKSN-4$NT2#KdLZtp
zxBU!7{c1f0itekcDH=MYeyx;_?8E9{1;mV~AKwbu57eW#(KxD(ri05v_2StW%W-uu
zWfe@QUwR!Zlj;sJDyP(?J0N>T{aijc?KK^%Kn`k#$Uk#PQ!a${4w^S<l6KVm?FIEt
znz@U?;;eZ(0K`SZ8l<4=5zPoW9$YndC?DXMCY^@nxaJ&XKc3L=B(Tt3^T!picxW0n
zgPhcqbp!9IiKLL0m!_ZwEIyh=F{t#_Tp)jkpQeR=dw)$Loyh_;tDZ+?pk}}wfHRtp
zXy0~L6YNj_CMQ_avk?6a(KuB@Z>Z*tqZs^iny^oyK1>r<4>94Ii?5<BQgffy%_xoE
z6HpkfSwoBAdCgugu*7IqVB0$9g66X>D2&y-`Wh6*X<}Sa8L!dPsr-`0L^*Z|n$kR!
zk~Qlom)(}4dBy@UsT#L67~snqCh??cO5XxLT{A&?uV`G)!om#A849jsYF?*wo-ECe
zchQ!uS@aOb<Y)xsK+e^Sy1~Lc&6~#|J72Rl0h$Ul_3xwYswT$@4c9c~l+{zHsk;iZ
zi?(WP^otg2Zf}I8B^m{teM>clW8f*%^oO9WT+>MLj0%k%C1_P@%;XxW(%h!}=4#DW
z@}1UblD`6=R`VWhv+FcZw)?~`p1s1B_cjpCnrh1LY|&IuqQ(tPP#bK!rAel_p;aTy
zLr2>*am&%xuGvWOj1J9tT8D0H-mXSRJ2e`lYtHG?MA6B=Tl3BbfZx&lItI}_nt9}s
zxvS~5z`|b59ooY8Y2tg(iF=ygY$d4e*K|JzGN5^m*84%tv5z2TNb}Tf0Eaczw4RJ;
zWID8sY35RF=%MD5YarvA?h7Cj8Wyd1lbYQ$6HjS=`wV7JYx2m^_(-#m)}a|qJ53w*
z+N>RDJE(n;(%KGbd;ZH9a?n<j6^`2WgJ3<ZUG)^iIB7>IIl)<bi=J5*t<?=}N3`Kz
zz<gJ&_X7;VQLTpdvToX7GfKy_6&b)C*ZxAW=o8vr1#s@#wvFhEhn7hm?~__1?KV8M
z`}8o)OUsKQf0(y6vm3=zT1FkD`DoA3&+Mzc69;L2+UpdC_16wo03V?Bq7U_))^aqk
zB2eo#8?w)6=h0UDtajr)0D`pR!yuvB4gst`r%fbJVVL%(C9pnR`wMw=BD6hkKuV-m
zmqv?Ql=c8U0@2!c=R^H@?Z3BBx}bfYvUo3QCnG^(wQh7uNYL*0g5E@J)weJvNvo%$
zcd|Bp1XiSIOV&VPs`j}Ov|ZLJ$=j5sjrkYC(zV-Dpzw;8MUO{@wvd*wOl=h1{kLUl
z6ZfMrTYEVGjXByGnniN8xpV@_(+=+eYreK{BS?YvOaW9})fx$KO?!3*fa}`&Vpv$H
z?LG=pq}@t)ri--;=?N^+o=pTxsn)v;fHH0UMVMBueS;Rh3hhNBMy=AOb(#R8O4~wd
zAJy7VM_^Qqc5OB6uGQ|LZD^f#!y%A*Etd}R4cg0;TG*)F%Yd{d?dJg~HEVy^4P1+M
zfeGEdp<PY8-<w*zp?Hn7-oCJ+Ra^2Q+S;_v6l-kP7EoZULu*q_p`*98Z%(1MQ!A%X
zdY9J!DFC~*uan38j<zWkr5^1kl+}7yTSgwCUhR_A;Ox`>OS_JH+KXQ3Q@^&6)`J1<
zsu!VfP}_D7rTf})<dDr7(l*j=Wmx+hEmb4h>D#dPfwtK8Jm{#lxD!1b(|$oG#0hPD
zK1!3?r+<TqQ`%BGluc{5oPvr++FQ#YbVfUWIfUBlx}8yZQ0LtSp@(!4%V42{j!A2)
zqwbwhln(0}2LN}{#eD^{opmP;g40E}h2nunbVpNYgW{@FPNH~JS6%~zn=V2E*~fH^
zT_DGGZ_&ecLbrGuSlo3>Dqx|9Zr-2Jds6oeP1BybTfab|m+q-h^w3);rf}vdT^ubW
zKDrm|p}|+z{5ZPgr+XzCqvo#*S`L;#-9;sNQG#?+Ow<PJQszQoi0)VnWQXeVXfipc
z`+Xa13e$by0uru!jwZhd-9vJKN9x|V3l&j19tC=%b&b0r<-G2k1op=0=2G<Sg0AH}
z+Aiwu&Viw^x}S~$9;fRmgob#X)5I*if0uLzD8(s3_dyO!Ow>72#5GA5M~=>9-P)&7
znWD3&r#n@5*bbGKb^0dgP17ZO0ejPRrECDM=w54rO&PjcifCu*Twek%OZP)DDzkOl
z=ypYpF86s<=IS<jLQ0-)<{H{;`8p|OQ5EQ#${_TrZuJV-eNDH5?o3?QjnehmLS61!
z;EQx??!t;<T|b@wN_2jd(OjyF@&%ww=Rk*@a$Sl5q(Zma4AUxg*J-y>rR&=ZK((%t
z4vICpH<m+6t*(z=jyjvJi+1+)y4`dkv_UujaWppS!cPO=q+9nsEN#}=cA%|Qmp=nd
z?Ya*WA+$pm?tr%2x&@m7=+ymi9a6e<^JYUuw{DU)fOm97GW4uR*EfN-ySk-9a1QD&
zT!54zod-Sm!#dj@a%+$1o=O1Em`-{GeR`<NBp>d$Zu?r;J)wJv)KBUn?ZGmoYwJg8
zTIc7Dwnw^!w3(jK?V~x{Uf)MUa!?<xK<SYFJ90cY=$FxK>!=^>K$i~d3lm_4lRl{e
z#96Pl(TD0>^z)y9!AJCdbg*#MJFP?4j_NB;LbjV;p@cEV^y}%vPRI2RDeL5f{z;0i
zy6gLBz4y?cX#qK@|CAmGPyG>!*m~)|DMO{VUPMQqQ~Diq(O)0Eg9vb6{nK=L-cRq?
zZUgn#|4Us9&@cWNMxEA2#z0}9zJD5sGy1ezXgaH3bRWPVz03rm!TLk{K|=Jeevisf
z{n7u<7kZWor7(SGBt|q`f2j!Y2tDs{R7UE9_z)eXZ{CD{M(ahNgPhloEvEM`M(;-#
zA};9lFT<FN`pxui$LbXy!lpR=CtkqE>z{oGm6!DI(Oxe>pOOXjiTY12pe;!s`4-xe
z_1~nREk)ls2wbZEo&i=|*1waEQkp*ga|}Ydehs;xGWGN6$dsiY_?0%7+4^_b5R;?7
z$p9i(U+RS3=jpqTf+t^}N$2GP{pdGfxvF1v5WTpj-y98=>-z6sKxLsmV-ze!`d8`Z
zMzLP3L)S|5eUu_!svk&!`Z9eLxz5V<Kd%J5LjN>Pp_Teh`XGm`N^kiEwpHuB{7|gX
zn^yr*t53ZHQm23M3dGdwgR4Or^e@x#rcwWj3)-6WWxf#8toO)+`WAh0D_Cym-RZ;a
zH}%_$7>ir_glw?1>TjyR(xwk+L|ePQg@P9y`k^G~yKU3|NJ~ezKI#M5c1QmnrDpW#
zcP&8UUHw+_`u6Hyp)}k+{o@o;yr++#^t66`i4iOVdiz|A#i0I83JcxWf4&c;A$^tw
zoWuIbC6GCyze2gH5A>7dvKZB;cVU3W^e$nL@=$Nv@&s7N^_67lgnpPj$&-4^MzBul
zZ5JSPS}$*d6_50>bfB5h*ByZQ_J%1+(m7~Yd={053`4XWIT&VqQR!&-=YJ4(*zgLb
zm^n^{)W2bcv*8(gRJs@>aUe$w%$-o=YA}CC9{;0;b>xe6GvwPt%rV1r<bOPF_~A{I
zP8gbcq0rrMkZ!Me7|#6({7FMN<(qgKy6;1_mmy^cKa98GAG(Bd$`JDaoW6$ZCjs{}
zy!IAY{0#!1Rj<rmY5V>Yu$(m<h(KGA;V#8fgALn?Q5j<Rm7MvZh9_fCdCqW!oL*su
za0(8E8&-V`5@C3ZKFSbj_)7|wD8u1ENQp80@*Xr?F#LWB-MwfC4S;2_2G{4n5@+b8
zRMmJxE+yt)GWgmkB{9LU*Bd;Eh5?#oQw*2f0ZcU@6BKWZp`Y$hUokAEXk~`spA49m
zX|T;lTb99r9@%WeuV0~*WB8IrE7x#?JgRwyCoZEc-%$D(a0Lb)3oKU+`*(s|Gpu(-
zU#=S-&e&j7q2a+RU@bC4Qn0hwAngGuF>q_4x76?vZRN`h9tkLw8#MH_vkJpAPe5p;
zp^#S5DnpqOfNFz?oUb*8F9%SnHJqo{ug;J~;j4PX5P2aR3@d+xutvk_uTW|-%$%hJ
z{bs|rZ-TYO@Yav8?S|nA$`H9}n4|;AEyF0C*jf#{D0{HYaFh?yZaD1-p&bU^2N<>6
z29Iw*It^!k2B6EZmm<F1hV#>?ykl6z#ZS>=sH2tYuHntqsO&ZTR1PV9hR`o*y18eN
zN5H6l1D`wy0|x&Opm5MIR{(O~&`Wd4kiq3$bbHuv=tXdj7<dOU77q*#v{Z~5CMg0m
zX83tK^gc9vtOIV`;6<Ll3B%lN=-H%Uml17KhUfT@GHvLLMCp+skIq)M8N;v`*4P`9
z+91urI71&yaWu|72XffBfnw55#&9)QosG{kQF1Znx5A1e#wZG}xEdEFW4MnR*U}v3
zW;{=qn~oV*uZ2y=jd$*&bi(LHDWmSjZ~Gv{!x-TJ&XdM0iVb_(j6tU%)XOMa3NhYB
zZ*oqaGX6lDJ0D{#%{snDBZUk7j0;^+@;81*lU{&vF8TdW8?QbAT%d8q1xPt#{FdIr
zv&J+bSb~hR>1PTy-u?nCA;xnLVN<Aa-FHxb&M2mrD$Hn$?S#;9qlh9g5yl;~X^AwR
zc?d+5G4@Zi#TaL~198Fl_vaYdi$;6$;Kdq6&KSfvWBuDOG~T%PIrQ+7@n4EoCK&(C
zMJds^<yk09Hm;*2g%sn3eK0N6Sn>gImyHFKf0||tvo%1)72^-nKx7zW>DvjJMr$6_
zXBks0Xv;R%P~17km`3}@d}G*0U@0&jON7v?#-1pMxn_Lo2ujzD$0!M_(75csx5;>j
zTsy_aHVUhj7+GJSXQf6vZ@|lpJ70pna^vx}<V&hBz7hm6mBtklP*G)!YloO>V@xR!
zHO8cT;A@Q^t_5eE@%tq(t=`C{_+o=Gg|cBAjX%<Us>yg@9ax%;IqyS7i}9Bv2)kjt
zB}Us#W8NB6-ZGAlL1wG*v0X5&&6vlWkN2;`2z&7!8CU!b(rt7LgzP)U|CPgv9;010
z@OO=`zX@QkG3q$P^ci2b0)Nj~z8s}~V?GkZ<_sA9XFvvxE#zgpZ|ru5*+a(RCJ1|A
z+?0a0QR6!L7TK6FlHS{g#<MFaXgO}YL|vOOCj5+FX3}WWV=ShOdzS(@ZQQsCz(+>E
zpV65aqlUak_NEVSfgCce{vRxKFkPlto}+2cC|C}g*t-F6GOhX@Dx6Kx|6T1ejSFF@
zhv`ZBO2|o54`qCNnwS)3w0W5-Q=#75RJssCeNDYI`}mnAZv*dd8vO~f15B1-w4F8;
zYrq+3nw&!EjA?5ugq}6E(cP*b({>6M2Ah_Wqb9`k=53ThO_O<$a?Uh;8ZyI7?cJyh
zH-%BOCC;?!KH%{-Q`0!cGQm`G1D#1UZQcWENv51WAd*cf^hx~`lhYiKRMWN9kbT)y
z_zZ-mnOeHgi*!?4J~*$K^!ve*VG?Bno@p9ofF;YMA`f1+DUlMxa!fq(x8|Cb(MBfE
z6i=s%e3R`aU3MriZJ<rZRa53q5Od8mzZN!KH@!%D3r$Q4h7_5Uhk-9PDTC2gVp{MI
z^p={so`>u*lY)Y@<)*fAR92WyQP`x?)K7+1nf6VArP>rilWvXa&3v@gn!cboR-Gx-
zM)8t*)7k}SY%m4Vv8K_am_n(^R5k$CW|IRQkZ+n&XdidWG^-Mot)`UE!O~{>#s`Dg
zZt8S}X&t7|p8>gTa!f^KrzzoYSl?xOhce2#P3`oi-7)Q>lXQ<MpXQmnrcx#ycY96!
z9jNUyg;2udJyVGc3j0lS$hA6P`jxT~2Tkr2k-TqmTZE1dnHDX^(>ZJ^x1n;x^h_h*
z4@_@{12<~o(z$-jRQU_q9-0ok1S`f(jZXnEVfwff-JLXP=K?TgN_HZ5)3oV-GqCNE
z=?^+B%$Q=d0NR@~UPt9Y^P?ju9Wwv6A9x4zU;6-bG`~y^?Zak{2`o<LzXY(*+5C<-
zDqYR%OVNp==B2H$!p;2hHsFq#twF#YH?MXC=Lz$td%)sue&Q@8=zEwySPi`=&HHBo
z;c34A2@qap<$6?ln>#4$?3B56Kf2~)UO$dDU-PEVF=~G1LNhw!Z!SzkWq>(y7079G
z2L1Md=KY?4pE1uS2klw&(Q~K_GQag-+}Z5@8>|R1m#&7rwotPy2EcRXSMC52X11$E
zpTf=3c<7BVzhuR5N1A^L0ZWwGm3%?bX88`VoHy@z8<jEU&&Z#C!Ti5qa9%VYTn<BH
z%?&}29cMn73-$5ly%dkSWcH(Ep9FIqZ4eU8wRCDtvYF4bL6gl!nxRt6#+M;G)jZsa
z%FAXyIv=E&m)-+D-5i~V(iQV7v}MaMzxyIsGR^;^V@;MhmGWS-&G$_(CdaH$1CVQW
zquT;`W)W?4^Ubf*+E`$IiZ*~(&0lW;xn{OaE<m5In{x~(7Mi`!fVIf%7Y1p?=6bp-
zUt&&5L)S{ppV79t!n~DyZq;V)?@&==UQ5Y0wdP#fC)Al={SXT4&Fw*u*<dbu0ELa_
zXTF4#CiCZAC^eghet?D+a|xY~Z<ue|=$gV!v*;dpZkdZ|GHEq)I-#k}EdLW?+Rbgw
zVC^tZ>%e*29RC>FI?dgmKw6i1J&kO)dH)JnamQS+8|r(^)1Lxx*St6!q}ROl5jgwI
z;U2K?o;jZOHT~waBv>(E?)#Tsph5HdcF=U+eC~hX88Tm^D<Z?@9W?EXm`_&%|G<1R
z8>LY*CkUl6vt0{hKQuQ{n$Ea+FWq6AFb7XV*ra)923V%de?1Kq)8=o;dGyG<s2+eB
za~_>V?Jcj;hx!g$xc?<qAF?!Q(Wk?f<CNCqWO-{jh_j_@8xSs*<}$P$v0NjsqN`;+
z9o3FmbYmdLEj8q0JYm_;i?)-N?exfdTE1F<l9%PlZ5UB+i#Y<qPFa4RK%0+cRxH~5
zEpOBIH^8!Qnm%55+7i$JX@M3NIZn=4K2w35wYV;U>>x{eI9P)%@6dKK#L_`o&!Ltl
z=-oVL*|iB>3$y&a5iH>rH5)7umhG7+MOuC&=YEvs3gyv8TmGj&x6fN{(cBqh*|Gw?
zzhG&k52DyES|(`jj<p=jh3q)XrW+{5Tjnl;v`dye%G*k?oQeW4(Q=GZL6a<jFX3lS
zwj871FvX&wWi-{|L9VFFmI*Uh(kvacb4$0Bk$3!xg+cqk3`_4t^fS}qxDb_Dma%pK
zvTc@vZqOV{zc)y(MJWQwvuvfwB;PWNrnCY}>Pb{ywH&?%)2>;(dQf@Yl1e_+LW`Ex
zlOl^+0#a;Q^xt9MGM{`%rIxEn0F+tc>2)Z#Y%M~m!qR^eq|)*u<?d8jY|SBPthQYJ
z0V--N+sXi}wYVpuYju`1e^l06YVLrg!LqInZH<;E-@{loSt6Q&Z?-J0fH5tWe0uM1
zSO))r*{zm?(NNK5Sx4y{?Uv;Cfa|b`$pwAe;_QJ}rPFf00`M-2%=RP(qub&^zr`I(
z7rCN)EXk!1bJy|(<p}p$253jqXYpDAY4<Fvc0*df<=qfS8?Y$JlRapeeh$*^TMo)$
z%#g*H4l-=1SP9W1mapksRu3#Z%19Wslu;ON%<}llz&*759Yg28aZAK8kO|9Pa&b;t
z8twr&WpQo->$Js@9@a;e6;5cIv3N`aXm7=*6Y&CB+vdXFLsl(?%p9!j^DxcPx|NoN
z!&cWj(CcLV^dks!w&vV`Fc<5_Xec^jjaUPKtM#=@G?^T==K2J_gQNKPY_PgpO_fmL
zVeJe=>7>=V3_?AvtH~YVWo43^%iF4-K;<cGd=5B$tTsxS^|k)>IrREjU!{YAzg0q$
zL4Z~E2!PYpwX}Q&S`WU0PMon$w4-#^%40%%kkvgAmBH3Ok%^9X%=#?d;0U$OD*#Wp
zRZK362&;GsqZetNPe1H=>+j)ci?Pb+lHmnw2TgZz*7s=<kGK9r?tx3zUF7afu)aoT
z%0z1vO<qaX53a+QRO`cD48morn-Qfn>v2laO1BzIX)AKY`WXdbGOV{~ua{~4o`QN=
z*2T^s+1A}OmF8Fjq|lUWy)A~ldDg!uNjBf=@GnS#wFPI|IajSsH_&#?dYN3g*R4^M
ztXgQj+YQl0)?4X-7hAW`!%|}Xn$iJFt)H);f0JHj-SHW$D7UtV(O6+s^rQEc)<*I;
zR#`bu!is9^+V8+pW8Fw!JFK;8$xBvewIjDpy>&KS6K}A7G>Xbb>o@NK&}99*8g0$i
zPBOH``dcP&H>?d5E52#n^CQSD>mPW6Y;#(z^`U6&usQ|9{M*(aX&LOaYF>rVF6%8d
zNVoM}ADDl~x|9w=J=TUTsJv@EMK<+XgDBG1XZ?gGsC(AMjv)P3?j*WBV4Y9{Fld$2
zCztM9IbP5^WPSQOC>pkYC<do(#M(pt)(6%KPc)8N+i89svkvcv(1+Hp?ZA&)<GjH-
zVYP;%ZPMEC4P;MQZ9@<<ZM~?2>_=8_O0GJ%d9V$fhc+82hty%S7jod{IBj;N`*F^j
zU*STg%jQqc0&wL299?-_Rn-&MTrw@Q(rk4})3nkSD>W<4)HbuM$J_UP-`nkh3!Cg9
zAjl%Ji3+kQvhRY3fC>t-hzN=(Ac&wK{J!)1Yd&+%%y;J8d*8X|%*?ru@&1Q^_H;1H
zkD+rvV;Y64ycp56hVf>6N(ERxj7r+<_%c2lK%*aHK4tU#8R4^GH-Pb&YDEGWyXb&J
z5aaF=SUSMyse@!N<4YGbhA<K>Afb#)NoYLCIKu!5W7OS*y$FViQlXIy$GiIh8pZgW
zs*a)=KhSpUFk>18S7I3ZpT$6rFoJ307t08ts_Qt0=mbRK8M3!9!URUrWjK?_*q9BJ
zql|=i(U`>ec{$XNF=T-t#~FOAIH#RpEPWRu$&3Zbz)WG_p~mlr;p+GtE~YYuD2$WF
z@T3BibjA}}sAn)vI723ru_h6Urx;Ju>~orNaR?$=40|*h&oFdqsAn@a(=E(lOi@5D
zmoYj8cJmk^!4S!3^k0R)1&kWn0~9j8RY9bPvD^oZ#f&ajT8fk~oMnJ1W#so`pk<7y
zCm~wS*t->$&N5ErfvaHDP^!C<F}D@i=NNTAqOY1!O=03%hN%Fcb&R*@IM+o+Elu{9
z7&TJpU1p?y0}J(x784p97~AS`Ev_(v=cDl|!}k{bn@c0Z=^J!5GyZIVMhj!%a(L0o
zP*b|Jjj{JNG+t-ajKO?6Bb*ABZ!j!BLZpKs<N)R-<G*3tm`+B4C$Mib?$ev6n=wKQ
zxI2u<?NGSKc+&%Yy^P=e;cp)!o@SN-h7}Qa$FxDl>i<{CGD0^(beQoyopKss{5%^l
zj~F!+J{n_ueHMLB7+DlA8fUzq1)7V~7AL^$cG}<uXZARy;`K1i)hV_Xm(tB?nhP$F
zyHkNXxcyGssMy@g>GX9-dOO9<#K`=dehC4J!{6!7OE4JVlre<P15RnLKs4CtF2#02
zoZhF|Hq6OigT8R5%x<6^a{6U2NR*R<w!P6#D@{;1>@@r>Bx9WnKZA>NGEM+H-f3(G
z265C$SPy5CoMsC_jydh1(%EFEs3-6uWxZ3bFJMkOy+XUmbf<VL6f>M|z6qF2r_rU*
z$a1QC8hvM+@>YXnJ2m#v<K;9OBL8&qTaF>hAfI(|d=2vzPOWqlsnRL-|ECX}exjoM
zdZ#9Oe>FHQpo#p7(;eE7Ty=Vnwx*3vU(n&ZW~ZNa0=mVikb+mOPEnpvXmk3U5**i^
z(&&I(yVC-yWWC`e@CWH|>eRu|O{bX-N^NvHz4$lGcR6|P1$WDdP3IiCohr|PyW{k_
z0ir!lp<lr6U8i5I0KMmQ%o8K)b4r?xOWE&q=2zIgk1Go70jH2QC=5ES)}ir%Q#);W
zhMk5)AR|uO2Y~s=X#s7T$DAbT4v0Q+%I3r1xYPQD7=<&luLg=P%%7LTr`^nDlndFz
zY*>fBz04b5Vc4!r_X#w*F?sYZcV|xh5X6HyN?%j-WCnc!z5UE`iY$3CdqY6HnK4VC
z?!(+j1&qGT7#|Qn=I<Xq^95!^rpG6c31G_C12mB7!U9YXvtt$-4>0Yma4ncQcmj4q
znBhW@P^KqkEe|rsLpH5NWohLl7>r_mc@QIvVH)paXh)cT&W2<xbM8{OmcTT81L#C%
z-T{CeWnR`m{Wx>~ee|7RHZ8|+lbOGM43t#n<*jfujrk2NKhv3eC>wT)`C=3FPBR-f
z0VRvMmu8e4W`73ya+#YP(a^|a4p6yjA#(@C)ry$LpWsX}Gkq7vQpRkf=v+B-8qL{f
znUZsmtYCh70bW!x2WO-49P=OgO;$1gG63v6bK^aDU(Gxc0ZSK{i{FDt4U@eIV71KZ
z-{8eXW|9(pmzWAaS`A)i_E0RSp85R@kOt;&zd`g0b3g&btIY8|5N%?9PF`GNo|z2&
zW~Ph*FIt#Il>KOBKBjnF8#A1?TGyF2$}_ezpZW^U++gma^1Ke_w00=mWVT14v6H#d
z8{{@K{0)kRbTjW!DbO8e)J_ch9y6a-zrD<b^k(m4+K15C&wPiLdiR-b%RmO0;Z#>N
z$eghhA`h7I5qL4gJh>H(51GHtgTgR#!zUmk%$I%#dBoIEx!Yr=n+n`0(~A<KW6acX
zngX9N>yE(vab_DOJtvqmsT9YV^@NL2xUh`PAiG(qH0$hPjZju=FUy5?0{d9EX2MZd
z)(~AaH`dMB0Ci_|Rzk#s^)wH}lXdeeNbYBK_yNU>wag4Jyjh8qXZK;H(3{HP%c}K3
zryncm9DMU<Eu0M!z*02>G>~=j8f1c4`aEbHV6A^2B$&mI2TTa-6je2bvihlP<sd70
z9xg%{>w_fN4QDZS0p$>Dx*ZA;tark2Wg=N6Opqv+gnp>etcCyoY=?vO3ayf2Si7wN
zJ;HLPooOt~kqR!3Rh<Yfp5?2Bi3HZHB`}f5`kUsdqpbEHaAT8LvzRb=jFnCMk>jl1
zCN!R41+Bu6l36A?xtPLQuo7S=S<g_oHkD;v4U{z2SRWM9S&sb4U^7@7-2ro&rSrg;
zvRDsoAZJ+HjsPZ`^*zn9IV^Q9+|Om5$Oc*-t9?4K^I1)Fxe8c;^usG;jTb?(i1p9`
ze~VetOkkF<`nQ5BWkpVfNEyp^8YtzgpZcMGmeuN@@}vsZGK%R`vLxf^JjdGeIuxr|
z;yvg)&l3C!(Q4MZG>{9d!WuNzuy%1_x0cmIIl(&CBZ~K2WM$Buyu|waM-1&Ui$mL}
zde)SSXl!7W({}X=EA$ciuCny>Tr{%IuA&z~6RYNJpj~6l9RXT1tD7>oEv)xE;L~+h
zwjLtwtY0aMaf9VYdzB8>Yoidk$@(=6COTOcv(eba(vJZ27HjhoNZw{?o<UzX>;7&?
z-eE<Cqp^o|fFAC<taFs_zQ_9N5mlD<vcAc|<?dr$r+i62>sxx$-Dj<Hh3Ek56WZPn
zvaV2O^8qU*6{8<wec%t*9<qMj1BGGMC)eTO2&;}taUQWgp;YK&R_SJtQC7YNmd04E
zPSAV8nzA04<E;DzAQP<l$0-`(%zm40o(uc9KiuEVZl`_j9(Kh~(Adi!p*6rhwwWps
zT-ggdFbX$zE*({IXTL@9Ru6WZA2?5TjRflZ+1uzFp<e6{&OpJN{dW*7`LJ7V0mYXs
z{tAtL?4Q2JaQ)d)lvH*Eun+Y>CXg-o3S$alw<Sa70DJx_fCjTOK1W{&`+15AhO&cB
zz|n(j303=qv9IvpVK`fK5F&@z$30*og8c>MKqJ{xC^QqrUj8>EquGB`z4c-COO(=x
zVHf`l?g(2*(^c#<Y{^rgacpr&-IsVB$>>`?$JqUA0D7FAMqhkNVc&Zi13k(1Sp^SM
z*%`Fr%VOumKqQB~;tjZ#%O0AA#ys{v1t9rs9z~K1*jK2pkiBvRFpJm=DCk?v-ascj
zOV~vhfLX>CP-R*<dukPYI?Jwm<2dvy*wZG^S;-E)i7RxDJ?RH<=h<!{&R>y-ZQyFz
zZL}S#W7kve^dkH9wQ%$jyJ!!_a+#e^AIYs}M|=a&2KK!@P`JY0Mycwn?1-hX(8$hv
z0p2&U!@baVjeT$@u2VBRupIuju#>2=x|RKYKe#sbK3W4@XTJ~w%y#yB4hj?BU@yK4
z(!n029QRH3j$~NsWH+9I7hUYQJ>YJ!-#!e*+w5qnRPJUE)9dpt`$x)l-eU{nA=%4T
zT?Of5*T%xNe)hslfZb=G83#AOcBSy}Aloqxg$L|sKEb^kV#n4v(E5<Q^*6{2v!kcO
zsS);btH3>C4^Zj+WA<OGaS=w@EzhHIjQv#)8lSKqdc)E<`yDrs3HE$acjm~p!QdXw
z{Qs|xIGqZZ*vFYlFKSoL#4Pl=aYWZ)!JYFxMW8)6o2JnV)04C4GdQ)M<FO2uyf|km
z?cvQCqTG!SN3|A;z8og~nEg0&s4T*tGi5&X12~I^p%=*6#R3W9oTU2H100PBBEg(b
z==l%fyh`DOP>$_0C>-Rp)3!d0Gb0k1;hZGgSA;J)|Imgaf^(O`>d_n#Ri7Q^^wCQq
zhVvGsyy7_Be}KeuMmNAj0_SzA_(<Z&6CrYpvrz!O;~dp(V5e{%)uZtwCz?(Qq;dl3
zRh7Z{%@YcloJv{*pW;M4guN_I$_yBCoZ&2Z4*J=gzMo(shvQA_`&`Z?dIIw~)eF&A
zz*%wvTp{OG3e*&HmQXcT38$a-R;8TJ=>C>*a;RRVoRdL!tAg|BBDhM<b=nJ_<CI3g
z?s?8z^ku4QPWuw*UEusci^&=Xr*k_%YdM=+;qXPyRyxRXiBm*r!^@o0O+c&X?1%!_
zz}ZZ3+AAFUCNws2o};>xYaFW`t~GQ1qpea4XYD1}ZRPwyJC8Qb#}QDt&N+V?_otm>
zoQnb8;OwM1`wr*&(@^N)IBu7N-sODr5HR;R`IJNH<p2{;Fvt8fT)WRHe*@eAr#Kx~
z<^iY0ANs?b#dIiVgwsi{-$xv8iU>dEype^zQI0$vePf*CwAp^bF^q#7=S+JS{!VbV
zQYnEmw~(GS7w(6Sm!Pqm>$VfDD|aouhupXye}P7K?pySjcyM<<fW9YpnHN2z+y{a1
z*Ngi~AMAQ_pQo_457*}?ybt6qTL2Qoz5WUYdVpI?weG>(pDCdl!VS9$%uuf8ECz9q
zTSL2(Fzzb512mi)`W;}Rxk`$zALd#<0Eyw2=D_X|?z5Eojpce(0XvRcNh{rWuCN&<
z61bnqKoYs~b`0$V_mwjEo6H@)3(OSmc}gFg<n~j^MJiWrfHP^_p%93qb1Tn6FN1sU
z2E8ydDHDPRlDm33u+MO3&H>5hrcwQ34p;FZU~;*?tpH3OH|RSw=5vGhL8O428UwUK
zZb}=_inuc=dtc1$egl0a+{Pg^R&b}#0m@45_w;?NbKD(A;aU~fMm5RjxpFy`uT*mt
zG&Nn|K7NEtQ^TD@Z--j0yb5Ub+#{6sZ{Yq%v7js5a}*c5%3U}G<89<_z6H=G?w2j_
z@EX@ZX~Smj`Er<O;r>bKtQ*`a+JAL$m(xP(CU+Gb%;@CKtOV)eenStw;}-WU6|vps
z{>KOD=00~DChl<O4Fj!@dx;wRxf>|oc%S=S6f6yJiz%!&$bIJ_+<w4Krt0Y-?!P}k
z@*y{j%D#rVhdp8NG55u1z>RXZAA?V0+`qO$;R$!yM*th=Zl);LgoC?+(qYcLl@w}p
z;T@(t<!)XCCDr!uL|kC+<+V`;cpuM|s^vU+rANT+=jAlReJ|b{A41Zb=Skr}AKt27
z81&^`raB!zUZFSq_2(IzaV-LPRiD6M2yf>J=!No<Y4SSAb1X{$S{QFl7&O9pMk=O0
z#CwM3jR@YCwCa!Kh0xj3DBj);7)31aFg<#4JSIJQ@w|QX=q2#xQ{hM=@6+p0Kgz3;
zfh6%7>Va~M_vQaTh{r2$16V3=g#uor@#+r1-*jHDqZ_RmylWH?$mETUz|tvR%~B|y
z=FQ~+CX4r_JFw62;?iI+mp76G{XE_?cfsZJmeDf5fVcQ26bgCv2&fnFUUCCiG4I_E
zVWNbWxDce2=b4Z3mhom$g1(%$@IK6*<$d}s1)t9IwowG4npbccFc)|`D{zHsct7)D
zsg@_EwL~4Sm-4a~c?Wqgafw%*1<<QJA-(?^d6ljZY2xh<sogetF3&Isu9bKEeMq+P
z&QbdOCND1-V4b{auYz>(2I!+`w|E{aKyLF4sX*!G6;sW_9p26osQ2)0Q0Z$w&m{%-
z?mo}sGEfG1ULhO5#hNA21@1oNt)gYZFmDrmFaI&`V~X00^4RZzjPc4TDDi}+qKMl#
z@8wMx<^=B}9<00ZyY>Rpoj*GX>K^<o3g&zApSFVR=l^;Y>R$XX1w_30kw#n)AHKN>
zlD_=H!@%_8cRCut`txT~I4yubnTiqv`L}655yUrNgyI4If8l@$;m3slG?d?A2h2f!
z8^vYA_-O{Hhw~Tw3lhOU-3#?dem)gCM)94eLGm!)I}0c={5A<NkMK1VSB>R+(EcTk
zFP%YiW+LA*AJ|9vD#S*nCGkbHiaf@z)ByB2zxrP^p5QxZahA*vyaBWnzN-#;C;727
zNvH99=!jZ6pJ4;Z;5#pcUMByQXpmF<Nh?84^B3L4AkOd|LWpGZf6zcZhcEe)O8#>B
zUUFdP@n=wUAfG?{1+H@ezpWBJ74kLp=quv?NK3V1{vY&3lM?=`^x`SybE4r|8UJs3
zV$1oNG%=m!7tvdxg8wbWKr8t>X}5ZgpH1QOD!%R-M9%Y<rb48eU%ZOu%nSVYX+cxN
z=XL_Smj5E%r%U_+$|GIods4!zp1)}>`WpB{^o(BNhfvDsDu3rJjG~GE^(pjS<7ZIK
zPc#20ZPZ%$OJ0RuD}Ofa-rD$~N?^A0zo1Rg4gQ*C5b5B5*aptg$>;b0t&88wMC&d7
z!bmuCoA1#M>~4NQ68i4&m-=87J^Up4@ZUZD6sr5}<xjed!SwN;qlu}XFQl2_KHu^e
zL<afAv=n~8Kl~EN5I-dVA`khx7h!Oi-$nO+gumiNT!c{vf8}dX9OJ)2tFkBj@@kNA
z{#H6nI>BE+0Ul>T1qBye1ox@NcDF$1fWjWZ9~9T!E7(i#w0(k)Leb|c2rNdQn_y%f
z6x;<Fbn!g|KT;IXQ?NM$PvCw*IK4}~1gy_-WxNHBAG@IFBj8Z<##fL|8DBp^MG)-z
z3+{gi5+FD&227x!jDA%?f+6}|&jG=%Z7>lmutWhgL~!X9G=>UZ5dr0(pywX2!vtez
zK*9x&o`U2d!6b_FL<q#|Kq3W;_Cqg9u)!gLOtfIjN4O@31-JLZM2w({l4(Z-o9V?9
zE0{$OYn&ka8#o#-uuyn7L6Eu;l1T#d3s65MD5dx8aluDaBX~mK;RWnu!D|$vND-9G
zg5*iTzO5Kbs-VCXC~1OPTEC?WoE~j~VuoPhHi%{lc66ijl;ABo+ICv-5f#*B36zxR
zJ|p0(aM`j2iETj35xn#%^l}BSbO0t#usmeWc1&eibP%dYAb21C77J$30f7=h4^@<v
z3Y;inP$qB+1XnItM1LJ{R<QkRh*Su+&x6@Yfg3H@&IzV`56mjT_cTYJ7pz?lk!r!-
z#jsZ^aDES@PT;f>?p_pp^$bKV2|}L(xh%+bY=LOKpg9+$K`@(ApH~DCO|W!Tprmv|
zqu|;&yl4_kJdfLSO|XWN0L_Av^PtcoXr)=bRbX#~hi!scwDP$w@S#^}yP#nM)Ncq@
z(;w1w2!hoZ;7!5bA#l4>aL|gzF2VN64v5|oNKc{jj^JSixE{egs#>`#c$yNZ_XJb^
z0%)&*<p$UK1w&NXbzgAv5u6zi+@byWpx~(yjPQY=^(L@~1dHiR%&=fZ57b8leq&I7
zB#=^x{A0muw;?hr*r0^lV}f0;(^NJt*zSYQ2|)qHg`I_e?FZQ{e0K+Y+9O>31-QM!
z;I&ZPCwxE$#$1IzQ~b|exH1pKL--sONP7xTuERyxFFf!XeDV^0^%;n_@ZV!l_Z9v^
zSzte**E0CzFFf!p8UuuZc-cFq1qzox0%(x%XNo-q3!N$46CzYj256`-gpI)*5+0!q
zVuVn*0gaKuA7bEIlyDI({iB8Ja{(G7^s0fuBf<qOz>XD8p#^T7@c9;uK3=GyQo#h_
zi*%?fQJ6t*qa@+4^wxD86MlFaFvo=(hoFB#c;*2{ku2;EhyF?7@6SL#RhUPM!8Bn{
zCP=!lm<psbgm?HDQ>O4w+LoUZ^1g)L8DT5!i?fBjlt;}G3MsIfD@<Jiy*%N2wcrYb
ze}0a!6bd)I3{vC}ru~W5V&UdRFjykAKLzYk;reWJmJ45_-{x7NGyQHWgs-H7s}y!o
zLFqYR<vbXy5_Tz|UM=jRU&RIC%W`lvLaq&5ov`f#h+M>VhNG8+d#P;XvQR^@iF%=d
zYG$qo9a*WMSB0}WAlfK26KN8%X-{`eIF&AbvvA*!aHduGdNr`ygfVLLT^Bx~cWS$E
z7fro4gf^=4>JX+qfu&AiA*CC-gvP}HyCoD;IITyx;dAKS6^i<ycTdQX!;4<wB*#=}
z^a(FiVc7SD7qWpiAgp^4+@Nq01=$`5_x=T#A)%Q*&+<@MO{=kCVK&7S9|^^aG0?}t
z%9U_!RA^ZUGA5k&4H};a-=qT(6T%%Iz@W3}@fCRJB66j|-QA)?RFkns<l{}Rg}tJc
zG{Su%AIkB%i#A5WgolV702xnF5rqu)i`-X(c!|boo9iul`5r`kL>9^k_=@Jv#31}c
zcjM6KFZ#U}t_6rD(@YpBifsgRkm%_$NFES<whLUaDB~<#3lSyVrO&H|in6Z5?m>}`
z>Vd*UZ`WeH;iBEI!Qdg$duPE#h~A(=tw>Sr%P<ioT17eOXi?`b^c@!c{wMlkM4t4b
zJt7*ViltbQxEjNb6BW>sD_%5M0LcW=skyL_D5~W{;i#x@$t3*#l0<1M;r=nv0y>j@
zT(p6H{wG97-M}S_>S^(iBI>4u^GVTgClpgfcfW!{nyAPQ&~%aPGe~BLB6ncer$tEt
zP{<Oweh<krqB#0#=Zda%K|N1YOt&y!luMbABGHUeTnk6B$dziNN<?F{YAzQA(hKvf
zXdP`UDntoKpiw0XodQeeMaiGTM73xgt#E5ar#}K$C%P$s`bAL%mG9S!isOOOAev7}
ztt+CpH$uHh^t}s2u8D3@{Zg|?^bthbL~|(neBB|M^#Rb@MJ*IXxgn~i^h}2+bOK)7
z6s6Fru2b~<bcl3`B#SY$TcRB$fVnNIp_Ny+=y(Q1dPHa9;O||L|NG$XiOdua>lMAg
z16ZHvX?kVc7xl}aHy~=HiEU6Mp90JWBFERX=pPbYzXNX`iVDQ&92RZ=7HA`)S7@?-
zByu?pk;kHHI;}S<I(i<UW1=j2)}M&{{Q){IN~?zCgs4-4K4<Z(7MOPtFZdW>yTvbF
zfyh4bU;Z%YD&BJoqjwW;qJ^Kkc$ecousy`r6<|HZp*o1}7l)-m)JrV40L@2yf|g~z
zVgs$U{KN;?u;edRPDNjU_yhVG2Z~qHDbOJC-{(LMi1*PCK2&V#K;J>}1tZ21CSKV9
zg$VJbQHVr}qp9FGO1v)K0U9k{6NJvg;(mHej);GI4D+$#aH=Pd6Ce8reevRj>(G}V
zX40-GQOr05?x^_9)fi!t_;m^o9~1AV8T`2T00q@E#V2T%J|*`47k#J2+u3N$5^H-f
z+%w{LHUlMFT+gMyp3M=jdmff@#XQ<O<cTAvg3A}PXzNlSmeXel3dNsMabJ;mAw_12
z#V?P;?GkaG3|^Fq|9lRhW#XkCFkdeIkqMEr;(uwSS|MIf3xrDXicUClPHZ@UC!tE5
zMzyNv#sA%>-(R)Z=?Ao45a-0f#TxOJ!w{_%dsd;bPW&6yG+q=>rAN13{5+LtG>9M2
z1a(DR)r-a^@n)J#u8G&UL7`bZw*ZYTVjE@OTE+XQR;W$9aWY)HA)Y~HfF0tn7jb=W
zil4m$;^-9T3_`R^{N_RE-x9w{*W$K#`V@e6i(Sh=?ud7+hTR^qjebsd#mf%B{5|oV
zk8u%t#ZxB0^@&qjfYL8+_#Tq?#r0Jn1LD64b5NZ5JM2CXzmW=&A+h!%oOvkz;~4se
z9pXw#8;*z{z5tm=Vl^d>AB)f41sN6J69Icnyvh#pM9ido(75>ZWf<Xvcm`d3X9*m@
zvo49Qf!n(!p7ce%J(6&`Bzq+VR4ublvYCEru99n2u<Itt`WB7ul0WFT<sosLqQYHI
z$>kQ9*e`kLjaDy7S1lU7CBwNu^O3mGX2W0d0Y!-eBrDYr36x|%hDea)OWMdEkj$o)
zL9paAIj}<{<&>}vmE5Ii=b+>-14x*p(hZW~k{#jj_mJe)%aDwaoOQ&aGg8uW80MoS
zM<_EGEtx{~K!+vk=uI6XDWdv-BNA&FOvFl-g##u|!l6Qj1c}BKJ|#+CJO}lolAq2)
zBuTR8U+5i^%+ul;o{-ol!(g)H>0&6PNKCX@Pm`RZT99<fKP8l}%aC-@iP%g@qZQmK
zNvj+NPfJ?-a7nWyU(vqgjAS-t&$A_6B~Z+f<nW=8D_O^ZWS(T`U2yr5WfbBsklg+N
z1`8!$HNbq4#4Q4i#mHqruS8N#zs*ufz(EYKO!9R;9o8+E)VaW^vywCP+OLpwQP8PU
z;!34E=Oj1P5UrAE=pg=i$<_>rR7<v$!Ndg#Hvo2PBwX56)k+@HZlO-%+6IM-5(}-j
zFG;c~8h=^xK_mL=CC^aF&{atc#Z($4ZzGQFnARkT5MyZ9B)$1)ZI(En1Zk1{M1izc
z$>@8y+-;I$%h7mUvYFN=?UE^vpm0MnZ#yp6P06~c7+R;~pC?f0l6(?}zFvu60Z5;u
zhw@MTk~fu5zb|3tfg6zgNaa9-l6;bMJdkX;gYgbY*o8oQDEVkT$gt!D&6AHL`{}6J
zV+r>+*d3K@%tGUsWNarIpGd3}CmNTe(mBcr35O~(U8FN<>$6*0O7qkn>G!mqa+Utq
z1xs$y<mG5|mu_hR=OKOlS#X{XX)+zb*f0I~8hrDT{<sL7x3sMYpgvLqZGwHJ=PBgv
zFFj8MxB=4XQ4k4~{#%Dp1WAuM<2oOZZcBlsU}?oEpoB=zu7HVy((fpx7bbn#7wX~C
zlg-dOB>h7Pw<Dy9Oo&8D9exz{jFz(UpdTa6`~fmYr0)meTE<GZ(ckkXNPE^nKT-NG
z72qC~en!!WG-+leETu~ofzZp47C#3sGNl#traUDzO@iIi(syWH&6d7H$$%W`!HsCl
zl{U_VUY_(?Bh2SZ-*8Z}s6cv!LVbl&`(_v{lHNjGdRnn`Wd{^XqzqcimrCz9!ETv!
z?ekDLD|M$Yn^Z_EDZX1NZ8`_;ob<(&@S;lkR}>^KNTVr3P$RwFhQ3;<{5ZHe>9q9#
zyC|JRl}DGPt{mF`U6#%YflR&hzb~QKApL}vKv$%<=-qf#dWx2)jnX%%sG~_bm#QGI
zN%Lqa(k!(%!NV45RR#1~rGD>&v`Igq&B}G@zY*wbmwrflj~mkO5-{ElX&fyTZ%RMA
z0rgI)*Fh?o?UK6C4)>Pyw-<nYTe@~3WV)s655oK%>2I^(T95Qinm6uBcb0*>C#|C;
zd9QSO2O9gNbtxeIQordie_zVX2Fif6mEv)O(plZG^gz1T1qwsbO+65KDE*@deZx}4
zMhaz(NTVoF^hg@o2bsrGI~Qo9(y3GuGbVL;9)3TOYFwc>E}cu+-3jTN6fJX>Ev1i`
z?3S&jGxPgocfLWNtL#U*&2BQD9U|_sG79o}$n3iS<|+F=7$W;+^>tA2lAWZmsl!|5
z*#z@Gve*Ei`O4m=Z^rn^&Y95ZFKe9z5+K_o0SS~9QN%G^_A}k4Loyo`1xLsNHlr_6
z_T@>aN6A*v202<5vKbfQu<T8`lQFV^C%9@yWLK|%i<RY-!kIW(4lQ=#9kS=?=bs?+
zrDR~Dte?svj>?91Kqg7n+5=CI$(R&CJTAMGjJ^}H1OLIpWZ5CA3rdl#$${iaS>-s)
zr^<W;P)L)_{0xohGS+_RWypm8!oy72lTwgVvdukEKP@}@2kd3Z9KOrJo{^>XKqFh`
zL83Xbb9!Ls%6`{^<jHbq3eT6l^BAKjkjWL0ER?lSD6B}<LbX-JGJnd5l*pEK0kl-s
z!+}VdEIJ52mCJ@#L9#*?`WWM_l<lLZ>zvHE3}&ljA&%K_@w_bZQ)pDnmTZE?1=-=b
zK&z28YtUFL8=#q~PIi#i#2015%g}g9))fu3%d$rs;O`aL7jL8Qs_ZURKQ_ul6w7Ur
zEu%u^YchKXM4DwQ+u=ovEdE{SwaR=c0MaI_52jG^by;K`I@@KOhiJVa`<w#e9kQEV
zP`oJ{8wb}Zb8`b|mn@q0Jhx;yE`Yf$+r0}S-7@2gaQlwzDlHItWU5clcUSh^HjsO=
z2nxdX%4X2_{rhBTlt}HDJ+B3KU$#I(@s|PFL5fNa%03*yC?3f2X)Qh^v%L$u4`o&B
zK!#<fzk%Y2Y&jijc_h114ZDwJE4G7-%J%;XOJlN%F?jJrwwC^gaa>kz0yiO>bP0XV
z@=S{Q?vbxghQeNX&tahKlaHf5+A+;tetj4QJ>+{LVaZdz^(iQN%jYsceB@^-aqTN#
zxCJ79awLWEtB~)eO059-`?rA|D4(_!T#$SnRWBcqAEotJu-u!LgCX+0E5L=yAFqex
zL3v6)NSOSGbfARGf1|nHaY+8^DPTv)-=QUaq}=T>3`WWSxPiuK`P)wc^sqdElC&}M
zxs)9`B2S_hU##435=fl<x9QM}m;Y6SF(t^|DR7b~pZ7bsWAg7lgBQo;MHI<CA$O%&
z@1%SVozzT~4?G2tG>2SCp}%zb@dB_J@-HX}pDFjAjmA@QpSke#w0wL%8nfgd1fcPZ
z+)W6yZ27bgft@3NuM(iS@*h`%%ahOi1ted-G7w%A$iJn1SfTv=CWsWtmndMjSnhNV
zC?)d6w*Xx#cj%(vewlo82|CN=A7`TVtla$>I8z~KEWoX-l-GR$v~%)Anx(7c&dwm`
z<uNqNSIhsTdFq1Pm;k$V^41psc2S<pL*pg6um<KY%UdQxy<V=Pl8FYnQU?o-@>{eM
zX_9YqP_Fly{Hsi`-Ew~qcyUL*;zyY8k>7m`(Yx}m=yi5a{&5B_La#h49iV;kG&>sm
z<*v!lyDxwCXP6j}UnaK)<!w}o^FSU(fxIEP-WL`g%FT4Taaca*GQ1y=r;yu^<mpUW
ze?FFbQpL!qd_e)mG$vn5FM=oX=M$jltQh(iFfNMaNwB+HaVHdtdlZKbpmDFl*BxY^
zqGA{du8K}2MBEf@RFCAY@TV}FhvKDoz<DadsN#LULQhdEFU5u~NO~)Z7f|}!M^Q$z
zp0DC#ibeS;UY`Rm{1pvU=n|kvqX{Zdk<J55kU~V;n*)kx=?xOBU{l&8MA1jbGeQ;1
zDPeI?@#+Ln!W2gtFcGdePel@k6i>XtMJNn~;35^vy`UGRn2d9(j%m?~9wtB!E9TQ8
zFGewg9;hRV3*Ul^Rn-52%ND0FevWGqueeQdy#&P^3Kk?P7_^f)s_>_84<;!jPXYUw
z!s98ZA6LvMh2#mv%8hU)S#gbKj}*o9X}~<G__z;OCROn?MZz6viWAR*rYp=82+UAq
zehE)A6^o-FdP)(t323JkD{BFhr8rFS#50N&#lX&191H`=QRMA~-CRW{eMvV@@%Rg<
z=PUMmL!m%nJPd_GMQsooixh=42No*={sbve=vqNa9SS~eZOarT!5Cq=BK{eGo>hEG
zGkJyL#38^`DuSDUeNM6eRcKTxI!~eTyy6GC+|`OL6z#56=qX1~r<k7x?xJGzRe)Vm
zT%Qbu%Zie%;OZ6i?_(?tiaAscctvs96T`i#aJ)u^nvDv#|6rm?F_W_B*A#Ciqp?|G
zrNvr{BKucd=T^lMS{$}3!iLayLoxd<9PLniJ_l$w6=KR1b}AOV0Jpmo3qAqYtvK*9
zMD8f2egX9!h14Bh^eVz>YuTq5p+HZ+Lg1hp;Xy?-6~R1El+jU&A;lt^yB{j1cERCc
z#p#vk8&Oow1@}ntj|13`6(cmuk1E_~**&J%Or@kx6e)Ay+PGpi#UUpYpFRsPXXTfh
zVAn<IL;H%|%C!_v*rU{?pmDEq{#JVbxhZAWf$gqLNr$3`Qce@Hmol~=UU(~=|3ssY
za>cjM_f-Z^@qnN5jbl*oSMH<AivZ>Gg|HN;bf(=#kaGE4ICDVR!hw3QGJuwBA<AKT
zbV8L+7NPH;vYb9;6s8olQ2Zra`TH_Bbx2u10PF~5dIe;nl_3n6IIR4a=Fk{rz8u(b
z%5C)I$1DGu29ls`c?Nxn%H_YqwWG?Y>EM!-3on8@rc9p>h2u*1pJC~Qa^`LfDOs7&
zg}xM}FU1p1D%m?I|B$Nuk`@tZ%0q|HnywsJ3zDH6rKvwtS@sHiI;Gs301wY7U1^`4
ztxVpE@#ZMk$3vu8Dcy{rl_)zYN>HjiPPKPs%C*zcSgzz!cI&Ki%_ZnnC>td3sZyz3
z4ZU+p+bTHYs8W_v3hTVG=N>w%l>#@A3rdy<q(<rXA1u`>*L)1~b;{&4U|&=!qd_hy
z*A9a;D5I&y_lh#U87Nnkyc{$(D!0;`vPt<iJv!HvEDBmTD=$(7ZHqFCLbI((wGYg<
zJCu{^KyN7fX_?faJoFz#Zz?y_5~@?Vk8Wj`vV<yYZYkfO3v^rgQ3AMb<ttMlc~_Z2
zC%5h?eRg7?y~_2JqUclpMj`Be<<bRExUbA-qH#dEP65{jl@F<|=YjGAT0age9Z%7s
zX+(L0PE9;gKA^emvGVUnKpR!AquS;%<<%_cKT)p90U1}O`~|xc%8Xwixm&fo7J7SB
zPBiE5RYl&$MQ~HStwf)@s*F7JPz}<a#Y<H@3`f0HD=0JRqblZr^H=R~ID-vPt-OUX
z1*&Y>a4J}}XgWGWR8jQZlTcMi5cI=U{FC4gsa~d6Y=p|m6$WEfKl7mwr`pg3E?$+8
z0WLxH&YuuTRP9cIzeiR4djLyPZP37{V=6Z)u0O8Yo{Pp4syRUp&}3CL1))+@Yu<#+
zN!6^6A(N^KqY{cV)wSC&pRSr&3iBDNkz#O}s(qhA@098@3fP=h*;m70mg;y8%%4%k
zQjjBCrJ{1)995A7n7Jz7H^AkoRxf};zUpHS_*<ajdQkagp{k402}P>Q5pcLfH5db~
zR24S_jWSg!#lFi`idpdKtg6EeXcelvu4t@Or9A-5Ih70Y2-B)mmv>_j=T%Qp%&%H?
zeIL{>sB+(gYc;C;g=nl*9r^*#b*ji;png#msHWfFCDl$U?76JU{14`@sFE)N=BjEw
z#mO2~dz|5Lv+8d;RMw)>P?WA!bwz~6c9jb)t#7EFe}KLY)%tVbZmM`|z;&u-`2wX&
z)lBjDZk6gIkUOdw^yu}d5-5VutC~3h4;_7~S|=#>t7cPp{=O=c>XHUjpS}+LLDeVW
zXnd%8hUVpARnF@mBdVxWkWtl>G*}u_9bF8`Co17MTys`4F{WuQ>N`|pzgzuFDTcI9
zy>%KIUDbcB2eg~oxec7Vnp*%A4~N<u3mH%Kc8a$7t8Ihm3{a0z;yh4YUJ02Xbr=;O
z9#A{cV;!tE(7HE7J@6LX4^@9cAD=#`?xD0=n0g~AgsWG-fQxrX-E#z7ggV$A&P1xO
zehR%P_5L@|7p;!`70w)1J9^wfW7L;(fqg`c{}jYyt$u;FTyg5BsVXX7{o!XYk)U3B
z1$~L?fq#H@R6X@A^d+f3^nw@1)P58kIj(+s3LHJ5=1+&EWc3j$Wk^v^e-Y3p)t(fj
zPgUEVg<hIEUxmJO^>dCOuo>zL^mt~f-JXLpr_|1Lu<*2cX&%tB)NB2Lc1C@Y0wCGy
z@^F~XQO`ev#$5GJ)lkn<$5Ws-U;Wf<h!m*J6VNME$CU%6NUhz0#$xrqG_n%)6^fsf
zs^@9Jm8qL^=>1o&-rx%MtomnKgH)&+C{bFewiKiBoch)lG*+oMZo-W@ubv+WzpK^H
z^g!f-`Y(!v*QkH~8gAFBX9t42r2c^NEtl0H6cwpg=jQ<Bs@m?2#zwVjD@c>t>jvCz
zQUA1@_J6JFhFwr>Q@`>5?WcNtCeS+6gId_VsoqirgSXU;bVqKhU!!b9x4MUt@^{p=
zeh}$VXHl;DuKGFpZQoOOFMvp|dM1V0`qT}Sjqg{#9SfBE>dKdKD+bi_=R)s+y7@Mh
zKM$$rQOfS2dhvGH9ai7}68a<RQ%hm+kvd>0G#;x9smNng?fDA&#?&KJH1|ZU!*+1m
zxH`rUmL}8#D==PXO<5ZHTr~gop>elnJG~b6XcF^5_G%((;Ke?Tw-5SUHC`V8%;BbS
zrhSpS=IA}>duZIbaK=*;!~phw&5B|)dTAorFz>A?qoA9QW*#4|`D!LdLeEdr_9G<y
zH3y^77@(<H4K7fVyaWnC8sqC|JfN{QgA3LKP*5~PlT3-QP|eqgaOR*xbLnZwglR;J
z;bOSv_-U9wq#2_mOoV1lEj*3XETaQiQJNF<YmV0JptSa3jq_gg#b^TQV;4s>_g(>s
z)jWL}*m0UgUjaK_v-vbgf~K8ZOVsoY(ho;dbpwWyG%R}SAJaIF(}ZzcvqT1RLbIYA
z*vXm>nkiB=?W1t!q~<fKiB8pgE`>&#rtt@$rE6Mgn~|Yun*@<ejVc(<oYH(kfr!(Z
zpJ;iNrP*HuOJ_6_R2q=2IZBoHIhr-`Xw22ry$LQ)v)w_N)qG9jhj70@<3W*+Ld|;<
z@ViKp<PFeb&9}6SEzvxr@}^SF!=>me)37IlE7x==VE(M;Dn*tnH1BZWTBU~fHWbcj
zYG|KarFo8G{pU56G#6ECmUKh%f@W0^pldWeuh8%BqNa%ApO-X`DSmoc^BV<v>otX4
z&~MNfs964r=Cx%ocvUm$A7D3XTBZZ7N%Jwq{H|%f*blqSnj=(J)uOqv6I`q2@GK~_
zX*OiQ!|R&Ezd)~DBc;XN4b6t<V4*|v8i(=^H#M6nh}^01r`K<nritpuZfRx+!QIwu
z`WqVEnwMxXeMi$y6}&wf&0ny4SMyQ~EZx&|Qx!n3X6`14^l8Q^0NJncjD_TV&D5XK
zIH2jchOrE4{-pQr15Famc0-!USX(-#J=A>c37KKdl3C~+(THhB@kq0&4f>BYb#{o3
zYF5w+drY&1PRc#e%rWAUj%(uSNYRAGnXsL;o0({I(SEoEL))u8O(~Uq+R0R-;;P+5
zl|gRW$4k)Yu02ooJhZo%&~tcdUwjV^@7H=!Jj6@;Bm}MA+U;~Je6;7*0L@n`xPeAL
zZRQyef32EoSOc`Jlr{;}j#7juNc#%Dd^+ub_B|?{4c1C19Uh{c%YsO#_La9Wq=VY2
z6yyujP96gnuAP$(a>${Legypp?W^BIF;e@75gJk2>G3cTt=+L61`lgDy$6S5v<pc8
zi1w*9a4l9FNg3HV?S|LT7q5Lp+pz@gJvw!ss1<*T#-rL*7a^IX?fC-E9MgXPJNk}m
zSA;_Eg!T{%3dveWAMJTkw7PHL%}K5CBxKUHPh~<sL;D5Apfk1W+rXXDeoB6y)&}o}
zhgsTXiGVqyWz2*^wl-lVxE$?Me*i33yX0#q<Z0)RVr2Q+Xxb|kY46fctXP{n08*m8
z_yj(cYo9pUVdAWIA{8<fTInt5S7}cTL;t+?srTSwwRQn*t7^5+tI$`c9ig(Hi(1pG
zAWd4442{>c%{09?YyUb4uoi7;Jrr8CSC_-zHm&bh^aId3w!_hOt>>5EZfHNCRbhv=
zvDE>Yo7y~@?mD$>Do5_p?ooi;(w@tP%x&#jI_=o4olhIiJKC%Q^z~>Xeudq;+99e7
zzNh_-N-%o0U(?6I`?M*2FyF6znx4S>S`*c#4QLB0(Kx8>q=?o7?dD2I4rv+f^!2`n
z+6OYg3~QT8pfRdlLJ#7Yc4+}*o@l4@;qbV&he{GAwC|(?###69Z-Bb!DhklITUQte
zpImjn(Cf%e7q$#~?z#pKh<NC}sRi-WefBD#_v^YR!MvAFP8&XN-Mp{q>tVjS9D1Pq
zbUt(x-e31+A?|O0j-LRSK;1qD^n-MvS?D{U`{f`k1?xgeArhi{e<Aupbv-oMhv{;t
zSSnn{KMD^I>As+Yg%LVlF?@>DbvEGwMeC%`L;bL>a|9$t7f(A(N33pl0)`f+>uLju
z*H!WWlc*bY1<X<1-}`W7l5_{CWaXG{Mkq9n>t=R?OVM3<8{A3VKNN*c)pgNwJx!;f
zG;O+0FNH{kuJ&UzX6iOm7V?yCMkgds>zw+)W$Tp97+}r<-7oZ!k6hi{IS|d$ef|IV
zjc#8O8Vhum5aaLotWDllI8&;dXvZkZbf5o<zH;5W^lCq=o3jRe6}loS_Ndgo@C^oW
zPIs34t<ud{h0$Nospxz3HM%KDAho*5^U+wRJEVsCMcqb<gIv=6M)ADMy6dOVSg+ef
z-?eDa`MeL8uIS1fv>d#ui`fRzM%{(e=)9(zK?#p$-L@QzqD5D01!>iNPr1-G-8aV}
za$VO;zuR`5H=XFcp%Yw%_Z_-t_rk-Qx_B-ub?OH0ps`C=mkE(uy7V~c-PYy51=6jH
zv!U^hE;5w%Xg#`AI<9e7H#ZWU_jE7NQlwYc;0>SpbQKXG13LC)kU?Fu5DE`;i~L}I
zSht7v=OemlmobP(y4*z|k9A*Aefp^G&;p2z>23(1H=%ohPI)-%>pq2ui+<Y_3~-Nr
z_ZHft?bT0?#?{-W&!zaMtNtt6AiL?!JHff@Z9CzqhkjiLU_AAUY=GIXPo>v_m;Q5F
z2YTzPrUBGX-$rprfBgcgT?){b{sa=JA9w&Sg7h~jSa(1_)c}-WeZV@{3(<Gu>2gd9
z)qB$l`Ji4x^G29{5>3eA`b*A`Iiz=`n(hdFGo5vg)X#E)ew4m-2*Zxn*Uf;!Vf~g)
z*p1PDM@fYv`k_xi67<iUgL<Mqs||Wb^(IP}Ch3<^nCzH-ycp`o^*$7waGcPqiqV>^
z|7ax?Q}kQu@a{?d&&ME>s(-BzifQ_d*MXL<e}i_Y8G12QA7tv|rh}Z)zfQ^5)B2y^
z!635qXJ$hEj9%0Ng=~H2KQNJ_kEMlFu0D-Ivw8YLT0`XPOAbJ<z@dNRdC)?AL@Epx
z=|fo<eX*WR8M_kwUD~sh>Q^YBSf+oy1Tf|LKq>q^tB<1vLWMs6eHg6NU#7DS=k((j
zL8|l@SdcugA8&zVwZ1tU7B1*59ssM+mu7?1>i?uEv`+8Xa1AbA)VERk<dXjVLXgY)
zRW!BK>kH??nFjrfWf<rc{f<0vSM^(H3(=^zegdvZ|28>#O+P^i;b#3aG^MoYt0@xK
zst<2QW1Id6#o@2(D=41VuJ@<<q#OF{v>)lv|KeyzYnOgQ02FWO8(%`_ZT<YO(AcdH
zWkcqUe({^=>(T#2ckQm;XDP;ePyfl6=<C%_x{QJL>91~trGEWC28`*xejgo28_<V8
zhQgp;yBLiR^ttok@35Xf50WGL7dp}RNIy~Sfcua2W3&w%)t_$w+L%6@>MNe;x6{Gx
zas79c6r9lWo`p}&hGx3WE{4#LaDjFk-bjYX9>eHfaC;3i&Op!2@E@H5ayJ}31O*R+
zn8xdA81;pP{f3`-5b-kn`y0IQHq<{wF-jl9YhQr%H9SLqrtN2Vg$tkj4e!l?r2xZP
zdUOK~x$^-NWEi;wkpqUcQiuc_Jg31#h@n9V$xwsj0{RXbUZ+_g%y57zN5Tz7^wEn$
zhF7s1oEBl|pw(5RVJe-8J8W=0K50_O#6Oc~I^HIrSi_bIbjKO;ZsStL8~*jfz!MBr
zbdVv@@D2U+jvBc0A(CYHB^3zA4B2#G>9~PO^T!FpQ4S=N4NE@5P)`~n?ch=kHrha@
z8UCXsT)H7k0q6|Fd@6s<G<Z6r@08&^$7RsdhL<b=%`#jWgNZW+brF2ZHhi`NT%O@9
zZHn^^^Q+NVVEA<(xMD*t52VDfl>%0!h9as@E;GE^2@~apG+NW2H3-wtS7ERPgH#$`
z<m1|$GgOqpP?g~XrK`>xL@&@JTy2>8D$p(%9Q1tG7&!Du)EXAVL!-{{#0?H#G?edv
z`Ade+z5@1T!{O)9S8urW8u}Ux_oIP!#c-XLvsVp&)3<3G4NDf`0yP=_rGtCd3^f}u
zmS#iDTtK%N#FTSuHGKaK73#Jb)=^sVx?yPyI@=8z%46Oz{6lNx4g>Ex`feJccY|~q
zod1RSTZUb~VW77S7xn?W+pu*B^zIni={?$G&?_Nw*YGVJWV>hJRHCuhux>7#=`*N)
zM`OR?Yl`{bH++JFB93VThEl3L9W+ESKpq$hhzuG2)542~hSdxVX4vp6eW7r~u=EkQ
zM+P%(E*~2{q#~$M!_W5tI%aUF(D=mgS`e<&xS_Ec*J8r3n+Zpqjrl%kbTPg|$?o08
zOu8d`jL$a!%(2&KtpN5u<4^Z-O<avLE~3-TIJg7E-MA<NpdQ9=BEWeXH@pCm{l>B`
z5HI6oT6%gL|D|Y!kMVE%l7X+Wk3!;p#v7|Z{EbXnw+9%l6x0ng&ZaC|kg-1wm<Nm#
zUKnSv!#MO0T0@M-QlJrPTy+W92aQ947=4)WN;bG~<Ge!{%pv3b8&HfeE~5&vNaOpI
z!-_I4+6T#Kqljjz!$vO`+@=^~iXX6#7*m}f5^FTrK;n!UbhskkDCvM?f-!*3HYFMz
z%I^Sr)cCR)FiFNpx`)S%Nte)g+_<wFGAE4e4FF9xexU<NF}gei%t>R$KJ=v;S0BVh
zOf$}))M~nMkTQoEMi!MQoHo8iukkFSa0Jk2jA!?tFWb0;;zv2ShET{gW;&=~FwZ!L
zE`Gl8w>4-jFs{wOcnghnwEHhIe*7PtDK_3)1Fpolh}M&(#@V!FEi;zKK(gHUc{tS1
z8o#AjO@(pAUT~F0DJ2BX855}7sml1?YWQ^Cs1F9IHij0!>;>bCI~_o)F&>%>m|Ej&
zuc5Qf_&nXNi^fk&Vepc%Z4de`8(*bk<@LrSDsgBq%Bh6wim|a02Co{m$I#bkJWapb
zCgW%XuHiMK=^+}MjcWtIwHO~$c%;=B)CkgM^cTUy>&7kT>DyxM#(#Fg(;LPvZ#dOq
zOy2>}o5rl)!F3w5X+zd!+(66!TgDnU^xZbr(y5GY<JXZ8xnsPQ0+Al$#(#lw*EpCC
z?w)bPAC`KJdGwbkea7om@V6fY9k?U+jjD?<KVZBtn+lZ%jUrmXJ}^d871NOM0VPZy
z8Z9>gGi-dFg)xm7r@jo4N5;=7>-E^!-2wBX#(iB-7&FFFaQ2Du;kz&~Zd^pu)r9eD
z3U@o3HpapW7t={9Dco)P<!|)uF+EGGfxV_ATEIHoOfgi*=5G37If#dese;3vrd(He
zvETIWuW;DQ)He@}zNQ+gsPZ$dq1n>kw4ToO1ew&|!>0qL)^`9JY+71}#t_rf8jw)a
zBg(WKG}Y1aJ<RkH)jNcn>Q=y+Lni;1Kq4Hbf<cHznxg)OOq8jgN?l`2iz%&t#PsT3
z$i$jn%!i3M)11TL;!Sl_%#dKp+YXT=lbCi($4rrL1Le4BgpLQLm}cEV<4M!1o8VGS
z^UQ$GFqtUhk!d>lHo#7qe2zlow8^oZmfBe+GevdJm}d1uCfhXVgT@?_oQkh<O^ZWe
zDbI911TgugT>5lYf$8^;pipemQ>3cIR9}XRS8D2g3kqjVFZ=>hVLI0UQfWGW0DV=a
z`3=B4Z?f-!-D=b4*P(vF)ajrjoi!%QMzq$N-VK6AovHgDa2HLBXg_$#<j~`?T{cbP
zqOsnjG{B21rqFG;c~?!Z(h{)I<V!ENCQ~7$-mjVPCkc4+O}YorYcbWX2G?rp+6sj>
zlW{c$c-{0p1-d#+y_={|@TTdjDvYqx6cqy(yG$493A|-`YYg0N(=j1L?wBS~vZ2Sc
zh@SPkrrjGbrhBFrX^GKmx=m$IeWp{saIN38&mEWKzG+SXxB=62daMRb>+9jn1Jg?}
z;D$^+W{5mAsa8^;Y}mA8KG+eHcLvZNn<TV19yPhsW@60r9!-}|OwDwbY}_QB1J@=@
zV^pE!Y|eQLKDn3`zoT)tc_n2K_L!^b8tygM(L!>cdF3+@aW#9=%h=64jZ&5FW?3SJ
zwBP&*W)H_SFY`DZ^YJz>qSv>dSw@L%fAce8up3}rPW$da^LJEE6J%CXj`D!{rU6{2
zdG7>Z4w_3^G0-scAjK!b&29s5?T}fX2=xfFjp|+_%{%^sLX^2&3x#O&&{5p2!{#Sc
z$l{1GfBF9$iMezwe2X>rOn}6hzl(={yt!yP&=Sm3!qAv#Zi;}1N6jC6j1e9;2T*$Z
zg!wvcSCY-i7LXM4DG5MNn$u>1q?(U+gJhT|T%eF?-jxrOQ|A4_@ac^C>v;H^?J&RD
z4R3PHnJ>X$u31kdZ+Ye*HXP13H`6Ppz<lmq=ogw>DY;T)zDXaBE;iQ&qp!p~><6yY
zJnIFhmzjqt*;a1m(42qPY`hJF6=v-Vuuy5<8Upom=8q{wT4nx@;;-k;j*oW$yV~5T
z0NMp}?>3;-m=7%lTCI6mCq(PaKh8$qMf1J}aF@)v6gh1$|4Ym8E9P5wF_^3735xVK
zngi&ASWV_q4@h1!zwCz*Hk%iH0EHHFJ_VIp&F`83)@F{Ut9{)($8jF5?dB^qMcgp2
zxeCP&^EAr$-ZbxY2U@3j3r!|n=9=}8yk)Ms2=2D|xk_-|=Is|SiaX|~XJgns<~I7;
z&Rz3gPec8l`8kRo^_qh-AlYXwp$D<w9844AfO+-P=o>UYYH~pIfq4;q&S=Q2$^dz2
z=9a*jVRK3^#x!E?UjvOt=0f_7jhd59AY<klS_eKcCrpLHxcOU3s!W)@C_m<G@mz;S
z7mH;P^!8Y)X)f7o`7{rG`z)e;@WR#7Ls!PlqF6xhKTk_T5ZL_|UkgONEIVk)=WV$}
zrSU$NUM?<zuO)H_2K_9T@1W1$GJ}dH11wDx3lFqR{DsCK%S#mBIADo74iAGZ9dBY}
zA(kWx(}!9rUj#X5>7ny+VV2}N^o3jALO2KC$+5(qgQpRe(U&0;X?giH?o5;=G#EZb
zTOwTG(_ssb2hbSHx+Ty*Vp&VUmRL&yMa|<Z(KLC*Tez7(NwEB#4w7i`AA`tIi{M@O
zlw|2S0}oGFhA2auY&k(YzZ8pLGC0Rc%bi1DQ!SY<Lnh5q=8G|9T7ITS_mqWs6WnP_
zK_>dLEDJ3#f5wtS#emrsKTnv?v6yJ(mTRfofW|ya1kLjKmbb`6frTSPW1(eNB0Ma%
zJWI7fC6<>dwp(g3or0rf4$CSkjVQN>T_AeaGAS0M!XkPf<|{4nQ$eaMiz%mc-qL&;
zlGT>Wi_v(&@|ytqHI_@)p-^jCNQ0@fWaXjpqQ!k7L@rszC{}aX^6*!1^_DOFFo*`r
zXWbaY6-zHA3$9umk!840jh5&wxKK@&2Twu&n&sy|!8Kcs<pZ?Ea%DL*S}hyyg0xv)
zrSiS&mhUJi+-_k}Iou74SpiEOmJ})k?XqxbBEMz1=MIJ27VY~0yJPX7Vv`=rEvf^(
zYuT@X`Fob!|L+=lEt4~#*k|e94uk!cO?AM&Z&`i}paYi4lsO!<%%k&w4=kR)L4U{+
zOh25578cdWjaZ&}0EI`EUGx@yY`OmwBu6cSw7wa$TwD*4amxk@k4#v$(QR_Jo=Apy
z7ptce1*&&jGiZL@YxQb_{yyuXXvnx)8)zHtX8rVKSaP?DX}{}X<<J)fJgxFw;PzXq
zD30W1T}{ubxAi}|Kt9$*_t5BTouK`jpH=o1`uwdY=?5EN4gVY>fmSO8s)MYn*tGvU
zU`_JHu!F77(HbPoI@SmhZaw7#a>yD$^J|3lWmkwqT7TOL{V1y`5Bky8?<n?h*y<XL
zz8I^o7zU46cNSwvan{8YhKjew{{hJaYg-Y#NVFO^L-MFKiFU?G){TkuZRumy!t)s6
zajSX>&`wyrr$Im2I_(I|pS1oXfnuulwK)(;vu3=C>zr<F`v8&|*73DK%d~zF1(8$M
zF*W*5TZ2x5%d%QrfO5uKO_8;1tLS&QmS?S72a$a1mU55+>#J0o>L|2+Ovhe|tcDOM
z7F!3X;;zIx&kFrg>l&JE%d8u=K%?CH{tnnZYYjAFXcg95pMtBj?x3?-=d2&>fI^kE
zW+xQRTkn+sv)Vdz4crCmhqNuKvCgIiLalWP?WpUl3fkmcbXXl1pnu7lFN5f1tMGeZ
z*IUDAUDROhqwT^KYd%$XU$ye7WVF#5(Fe39>+E;o=rwD}Du6ay`BaA9Vx31%?saQA
z9b{;?PV5584Xcgz=N(pl2d?@}YwQ5}I;|=OhTCO*_u9X>&bO=&zJ%y)>y{MgcU$MZ
z3DG-N7g~h(SQpddao1WN;_r<w8)Q&TQNL9*2jsq0Oy^4ntnQQr8nm|4%Km{>7Y>CX
z>%$hHJhc8b6C%Ub)#Uw%b<HC<^T=9CIn~EjH;S*1T366!Wz4$193oGw5tJ(!w-!?^
z{DjqO9K_i+L@#j{+d;>CXzaGdtpv;-+vc5U-D~@ajx+7EJ)xAnt8D{CRXuFqQI^ir
z_7c5^_S>v1G<w<gQQ4BW?HWC#KDNgX;jgdl%^{4%&-Q5sIDcC{y&?l_-9F#~ZJ*E|
zL<HHM(5Z?8wx4HGL^0S_@f=(XvHh|L7bw(rXB!$1+BW_P5@yT&f6Cov6yZ7_vNceF
zRD|u*uVFsY7F`N1%65d3UeUJv6~I1h3#Q;xjO~6dxFfa_iWJA%eksAVh_ks)0T*wZ
zOkO0|n42iGlxSN-v-DA$vmG!eY`4|ml5JkQ0Fz?V&`#u}ZG=(>skT8{e5BcyU4Xyo
zwnMa%$*@iB1$L$_qaNI88^a0{S+<Xxp?Ainq>mzH+y0=RSdOi;1JJp)sWf-y*<M;g
z0h@eV02wT>c~i=<&~`@+jUt=q3+NZyym!H;65DDDo|oF**n+;Zw&Ul~SYfOG5zbWF
z-rfeg=WPx2<EXZoXl;7Iww@m6I$K*IEM2tCq|b6)vK9Xalm^>6itb&piC})3<Ekwq
z1R9ODr|LkOY-JY!dd-%22QqE8rF6XDy3N-KXzjMV43HbPfw$4uVS7#t?xyWcTJ3k*
zzI+>cUACt?VDOgB?N5-~wjs)gciVDL0{V_Em{N^BwqLSwVei@w+=0kFhs{XEIlZ<W
zzr#|Wt>;sK_S+^tf{FV!#TRgKz!pF&s6kujGFW<GvwR1%A)B`=^d8#kDc&<|>!Mxr
zh|QS{KC;ap2YGB;8I9XKYCBHF2xGRV=<Mhd+ic1oj@!b%0m_8U!QBkj*&a&?0T+7#
z1qpZC|D!b59=q-ZH14&VqM`3*ucJ_>yPfq56g}+q0*u1bet|L``|TYo;h~p(-6LFJ
zZ+knfcYW-;{{Q_=`{F@>`PsD;VfMG@eGk0=`(DcI2HH0}=rtH*AENNj0kCi}*zU}L
zeu%w*HmafaGFs;!v?tOQGtB;L1h{a!-UyLH_C^YxN7xngaf(R$Ka`e>vVZLiXQJ(W
z%@8?k|Gfw(G4_cwuyDj)P6_l_`(Y|0jkDM6ruS~VefkBABEc@Azuri)_cGCW%)aY+
zz#O*+OoGM<yX#-zlI^ARtf$x)pGIS<-L8ZAH2d%ZprqS7DN~bS{~!h;nf3<CJY?CI
zPX#$+U-1o`$+nvsp^#%=KO0=Go#jMP^E~@&^xn<4Z=#fLfqm8hunX<O^z$#ZXB-4q
zX5V`jT)Dlq6liDdrvuPfVIRE!g-UxP<tonElj0y!W&iYbICI|KcLIZ`w)--nP-8!}
z1*F!#ll1EBhZu15qP-65I8+weU!doz-v0Y!v^Ll$U55Kt>`z&McGVt9PeP-;i6R$G
z_S8GL_}A>}|IzdvU{PG(+s@4H!Y*ZDXJ!ivtBIy)VvOBHqb6!%OJX$kk{FF?#u`*K
zx>PA5O%N0mDIy&N=|wD{2m&HS6c7*uELgE2`hQQp-}gK|9`C*9eb2dfW@qj__uO$U
zG@I;=GeO#H|23@?Z`zxSD7Dy+re9U7edlOcYO_zF4cc4wIhF9K!`|aC4BfV87>G`L
z$xT!myX?QBd#BqT!5I8V?87LF=&pT89t^&;PoUB3x4#<)mACd&Rzo;%)7yaCZJXEw
zfXBA1B>?Q(R`&yh&$cI&uy<@*%{2^3!nSJ_FrT{3ND--1+a{fcO7=GSBvj^YTd@ZH
zEHrN0NFPHyv+Xl_Arx=>eJg6qw#nT<b7NcaGPHGXn|mJ4JlU2<NfdqCM$$EK**={z
z9Nf3RibI?4c3BAw9@@T`f_xF%_q;`A+;*PME1%q6$iaNxcH1|wdwzR64{>q(o=;(+
zYP<1WN*1f#K6o8;e0R86!$jzg1A!Q!s2$!DKyz{jM+eL@cO<r;+l4!_mcXZrJEU}&
zvTDaFT0&gkv0(>P+IJkG{En_2Q?+pI(T+WT!NiLlkt2b7z2jdwoN;#Or<j|UL)l(b
z?sw1`DX<;j@U#-7K@Q3RWZq%AEAY_{BWdLo>#$k|ONkBv?a)kdSVzD#hfpIlGaOdZ
z^Cr{bcn1Jk4t2D1pY5<L9=HOBUrwS_=uq7OpNbsbr=*QD4*sraJL_P56XKkM-!HUb
zao%Ab&0C8dtZg7l9PC?ZgdEn=s;t!ENH>6G4(n)QQSQ+46)G<~e7XTXRXD7n6<ei4
zApPL4IE?ugD%B3N-$C0|2UQS!s&TOW2_DutyhA62>m4>xbm5vqc`sBN99}fh$<8(h
zcY2+5IP5?OV1N{V&N0}&1_$%wQMgyjcprm9^-S+#@Ha5yc7yQ-<3-DeCT6V&m79!@
z3Z+)&J!|lHFgw(!>|s`=qd(7?ne<L@WK(+}JlUuAU<qJzqiE-P0PL%ujD|OZ-%mk#
z$d{X7>b=G^c>BIBO)NjyKx_HW&eH1a^C830I&srzuut0iJO2LSES=e$e1*0!r>vii
zk(&DUOR#;}{~Qcoz0-x7Y43IeJN>I%=*&3181-L=^T2*HXephnnYp6@O0z~Q(LB4E
zo=<a@p2ffC2KeHh_;zhKYQA$hi+_KA@iWxV^B9O;{UD!&-psF~ky~Js4V@ofQv_zA
z<GXNZQQ;zRE>5Pz!X?)9d|2A|8Vt)uQ;x*)6A{o~G2=GeGOk?AL3Pzo3eNxZhdZi%
zj?9LcU*;Y{{hBe+7_GH|Dgb_UrOytmD|rQ?-&PI8zkk0*(cyoOC*W^4Ch86Vdzn}5
zK)5sZbW3_LF_fk1$!Kz5*NYJ%z`T!f{{R%;%#0_rYrmhdjDe0n6Bi6%3v(_To;+Y`
z=b-W-lSI$YSBx!1hx!<Iny0z3MIS@#Wq-Rzme_%(F_<1~>R&M7$!61?>BYMDf@L2&
zog#GJ>_Eyd-OqYfVDQ7(YqV@R!VZpy`04~ZoE}86?3|BaDUR)8U@4yc@LRAYu;<fY
zB9XN+2QZ19cLLnWtQCa@QrM5Yp_0lj4!#n?ylZ?)ailEv?G~_Pvxyo2GPpj9q-1i1
zUDU>nqA+DPH}nbY<#4m^pfZ<ZcR(|byH5+FeC}V`sVU&*P+n;v=a~xcPjid5f~APN
zNcl@=xM6f$=qwkf1IsyX)I0#rb0>_nsx9WCJ>hQ&H*_d;E^uQ{fcql1XA?@L+%4KN
zxy03k16ao0`wBx+&RJ?fdYRi*2ZI&dzf)kTk{gf<N2|EoG}E}krF{oLHRm!2fUBGp
zJq2sH;t&|B<-F*aU>zs<?*UTJd8~k?Yusp3ZQ!hF-}O4zM5n@TaD!Z++Q?m}FH$sd
z?K5GbnR`Xyf}5NJ1$SFGYfAZR<*MmEYvTgx4Bsv8fC)r9x49lH9o&6d6yN3ot5NFY
zd`)4mi+etw7QWrwgHa&8!zJzm{w}Adx79uFtDix7pR=3}U=J5V`<M^7r?eh?$epDn
z+#~MPdl-br+~;ce`-F4&8<kJF7B4v3%SBTj(lgHSU9>&t!f6BK1($Oe)Gs-P_Rd~$
z3Hfv%_i<xH&^StJR$?rjBm-$)nJOu#gIFge@7jYjP2ztHrF6+4dOM$zOm72ChNPCl
zgqf0-9#m#Yt|q{4w&dA=N!yYX`W045%B});MY5p;n$?mY%ODyhHz}#2Npgu|j>Znj
zCkG&JOX5{PbW0{v;>I1xrojNZORrPl$wN9N0zP?4W8`qu8{enL$nKZ!qr6lf>9Bv`
zjIT6<qQT+#4-5gwkshRVPOh}(21K6pHvK~Lr4Ge_7f2&%VpoX&DGC-&8>Lw(kVVqH
zMX-BD`VBdJPWtczxOiUL>WIo>X-*t0l}MM)1^$BcMLpUsN*CXU-BRgqOJVntbPdJe
zn`OfegZrjz2u+(>WcR4lD%&{}@HW{&dcWL~#S0MavTs`e=#Uxjd_tE?X4VTApUIN&
zXqUc~>1Yk*XcC(NypxH`Re0fSGK*HV`%LCGqEFr?!TV9U-()m7>SOYhW@dgSE+a6M
z{w60VB`m;X^%;}`O>Q)SCCDU|UbzQNHc|j6*d&;88beK%8`ndInH*|F?GclqMu;dA
zo&sK{Oq8_t%P?6&$JH}Uk}3Z%%cLcP2H2#R(k}B%*ePhsHyJ+;t`(TnPlelsCKKpH
z(rJ?zTa+%C+`kWT(PR_-97;{jxdL#>WXwcVmYMW+{+D=Ql1kUG!i1;%{d$wdD)@cP
zB%P+N4JOAf!l&ydt0^AZXfpRp;G0aoqnU5B$z4h&xoP6y5AIfzB#Jw?nG8xsWxL6z
z6Ts48@((>=I!z`f0MKRf%>}63F-fCI{XLUkX3=}}zR47tT=baC5#WWh>CshiKg6`;
z34n)8uT-M)uxYj*%!it8z6jDV(?95GdBpTmC}@tFenWdK;ig%)pn1%6#&)PgnHJW<
zi)hnY%3(Qf>Rg7(7}Kj1M2Iyl*$8LiOdk%Rd33yKL<foqrs_FRO*GA(37QPk8KdAu
zrfC8l2FN!3hu%Xurp1LI%{5J<Qzdz(wiGZfFpZ~oY@umSEZR<+uKOLX6`3|@F-~Vp
z_d1~RoawSUkexRTrb$q->5k1HD=`hAJ=x&Sql}gD+s{x_Zu)*YcrTmU(23{@)3Iw%
z>NfQ~0MH%N%CjilGaYsqJ-BcBfFi*?roYmM<sO*MrdQY_(+^63du%%35;UKh9-RhU
zuW4HqN^eZVDYE(2)KCJrqkOFdnojaB3gCgWe6^9nkS_94OVGH=Z*E5q+~i60q}?kY
z{uFKQa{uoD^pJmUK)3wlos|6UFF!`-LJ!F2HUSqXf3gVTp#1r6;DY5Pv_4IdPj`T&
zRCx%!<<jIewB}Biub||kQ}QwwlrrS;jdT-c%AM)$oF$(+8>MWy*)@!6j@*i}{Bz}}
zdw|cAPocMZzWncehyuAQ9pNmLpP`k@Y5D&3fEUR(yawQm{Ck?MpOs7UY5e7rX@PiN
z9z@$h#qu#@KwTo|!q9d>?su3blNaUNDXLd0_x~BHm*k7+CM=WZ%z-GEU#9K;3VB-%
zR4V1~_o3TW@}tM$=oR?~l*L^wccX8aUX?R$sH~B%RztH^?n&3ZPJX8q;+lNikI-z8
zzoxbCb-Cg>ytpBcM3RJ2+9*Hi4~LuNdIQWi%aa$tx0~`k6eezwkDx5>R(XyKD%<2E
zccSu^e3J<-MZ4U44n&81SsM)AmP?yqsZ&0WCU#wNSDNT_%dgCXC4a>S{ctTnkuVg1
z!-{n!;0#rK{tP`chAFBk1LBBcKSjdA72kaZwquHRS`b7k7XJhhrLa)|7_G=KfuqM2
zmv^A@gyQnopovw?7zpk-h1;(X@rv}-AWc*pr);uhMfYzYOHsHrfjU>=(FWJ@6hTAb
zQ-R_--A{!^h1G8$Em6#;T%1aUf@VlniVRwbUs14U(5Gs}Ds!}5ReWIputxD-64+`L
zo6;~Ob&44!P^ni$MZxYhMJufr+Z0=_L)=m<q={X-!s$ztIuveyz~F6#CB1Sx6$dD6
z*`+WB*1+#>MTRT5?<ywHX^MM_?E<*(E8^aVr5?o}^p<>}=%xGdp@O0FY>yP4E70~>
zv2HSGo+!@I$+@Qr&KKOhik5PyJXbIugXM+dG0l@-D%Mf%;48%&3QhJY9;}3Tt*A9-
z0^hIjaYyluBIS3K-YP!FEMMwq7H<aEoXkcIgK#$Mq~(N**?VhIay8pRpT2Z6TONgR
z+H1D!1mNywKSscNFS9LlVfUFG9feA7vkY2I`IyCTL&?{y*%Ge#nY}!ON`JFCadhni
z%!WJy_W`pRvr!5(`*siTN6Z>Gqcca%exy)txLH;h#4)oM+t3zi7T1PSl$jk}`)D)I
z?@?+sV_V_<b2BT7M?0F&_z9X$=3Yl((AoUw1oGbe#4V_}nrEMdqi*JTvuG0LY3@kN
zEHCqE%i-ca^WiH%>TRxZfvS&rq&aAO%@>VANBzyK%s~@iUJwkGgXTs$k`-(|cpTb7
z%nN>p_lL}%Q0ywyeDV_b6lU&9lky|xCn-30)ZBG60LRRS(9A5t{1+L$1R~9SCxbM~
zeCRWnKW^SQ9&9n@#XF&M!o2Ih1+}^H6Og8vAEbwMy7{-13wz4^21V*K%y-ipEz^7_
z<)mbpPovzOY;&uJ5V_`8C<Q3bTzntS6q?_rGYUoK>uH^G#{8E*Vb*xXyoge@tIba+
zp?cMPB%SK3G0&s4*IM)ZEug70Uq1nr_2#|w*l986>rrYo7w({~&D@suS8kbyn}Vgo
zyl)jc+HF3$4&sjaSJ$C=*ZfQp%-=J=><^U(=6`0w--qU(Qx5whqxqIW7~sd|Mem|B
z&&)5bfp~77O96xz=KX^~^V0n2MR@wkyp28{&}YtDz>C-BmwRBo-@J%c6Z<XRP~NDI
zh4L=oz7|feAp9(*PerA_#nWbp0E@Of;0{<cT!#5T3w1Ee23Z)V@!&pavF}5$1zQX`
z4Pc1Hbh=FrSr}>Ea@b<RNr+I3t#hFnW>K^qt{t@)bsL)D76S)B9J9!wB$fz^5L&xM
zS`4ARmne(R3edx7i($18F&4&348jQuo_-^-7OuO&5@(TO)Sx!O;@bD<Xre{p4AdrB
z?010qWQ))#5GfW1&!95Z!jw{ZPg+c&55J^Yl#T-~-NNz(?4GhnYzI8kBH%cLhvmc~
z2v5r=KSI;X^7r@PQ-I|K`Yh35%VndfFP6=eU>0Us=uN@QBbGHZi3_)!;tWrZStikT
zRD|Vc6)+KL`5tXXL|N8QU^v>+&JrTY(xnPMWmxY02O`sQNdy2{mNIi_W?L?N7c6C#
zucyIMx#e$@!E)JhJH-cTEjQD<vCi^W`dCT5W$*h8et*|2KX{7T2FpV{bgo<KB2l_w
znH>xl8!i31LE2=woj!clY?*u&7w@L!o{8|H#j<DvG+Qm-r@?Ep?D`3!-O`LgZXK4M
z3!!q`@+0J=OFJ#I`%&3t`9%l-k1YpLaQ%tp;|6;FJ+*A0<9NN6QLlk`X1R3^O3y8q
z4L~nmSdQ8S{7cIq3NyX3e4YegpJmucRKB)cNuh*(%i29~?Tux{OOzay7vG@GNqK7>
zgtOAy4xBE^VU)(`s=Q9`Yd2-k7<jQ)+5I<4Mt9}Y^-%Rt4yPn%Ph}6ihrE<Qt5CU5
z`Diu<*jpKT0p|BBzr2Ya`Y79W1L&*lJ&Z~}<uMvkf8~cy(H5XIhNJR;@{bc3wIF52
zfAb<`)_SM}E88i3D?~Yp-iC*i5wv}F*r<%BHBG4U=NBl3DZ|ZR@QCuAR+vAk+)n#o
z$CL*t@i;>Hj81k%Do;_wB}%C|kG5!K*G#k>SAIePsTidhZ6%&iCda@;oYHG5`Vy~v
zL5tJ`<zHW85E7LSXjdvpDUSh5vQoM8chsgR{b@Cks@xU4ISxB~3R*UuQpVpzFEW*5
z9-=KvIfafhWGe%A0+6HhqhETi^2vuVn5P`S7Nq&gB6_|SC~usB`4VO0W0<(0{Cgn)
z7nQa2iHTBW3uQ-CE2H;8<*KrkPIT2M<9|YBt@2R@$m*0+jI`riuWUFCyVsPF^eAmm
zrep$fT{)lPY&Vn-c(64pGiW8*q}&*W%4TIjHrQ?|JNJOCMLCm(yHz>iGpO8BhOb9u
zyYdGIxZR;N?MK^f<yuz&I+cPYRJxQF^g8KQ-t{p;^^Vel&fnfu{z3P}JtaFCi2KS}
zdQ|o(lMJYQpd8`?#6zX>I-Gf;%>5W_PnC@q(blWXqNl(!WjRgBpDSx!q4GjGl;(&p
zmGfNC(O1evQ2;nuc{!lc*(xgt-F2~Y_ob9HSF6uAqECCRPWyt*-KzXLN*-3%KZHR~
zs|hqu@UqIHJ>q><>GU%9wrU-M%KcV9P>z(3)$BCb^|eZ%Lm+-ut0E!%t^S$|OR?5f
zX6Qt`^$r<06RqFN1uoh816w$gYW>v?#eg5AY1UymK%BDfqlI0j_2W-qDcAZR6;$i2
z$7ccGW*s>hZMUq0qfu(NKDYv<4(qveMQ&RUrb9)Y);w)HJhJu+u1;XyHGWGeT7A}W
zjj;6Enja2F`>n&0QTfK&l@gHNTF*%Wz)|HxH>s0qDb13cRiTss;i4*=2~KZSK>+OS
zS2<1qOQ@=cQYFGv(+{9$M^*aq;0#v<-Ga(7Rr*AfB2>BWLo-TMY#dJ=RsB^7M2adX
z8g_G3d@4k)>cV^&%u}U}fJ(7yF3t8!RNo$;8(0-i$B!<m%xN}Rswx-{aY^-@4w99r
z)|~>bTs7!lR9;pk{|dVmD(@u_m8!>-%2}lvPm|ayswtD`YTZzIP+obXs*L6!O{!y?
zV5wR4n7-C=Q#EQoN-e6qtMH;#)$}Jso636t#4XjvC&0C<*7TuI9V)-uDBV`=pxp0H
z)u(E}yHulSm!?})-3LQ=REMqscUNWj2Bmwd=_Bb#{(V(HjZlv&W(IDL2dY{HfDcv6
z0swrZI!~K;k5$KRz_ll;S#%ojsp=7h=zCQw=F#n}dj1DIe6A|L0+ko4h6=R3RMpf%
z^Ob6#7fOAq7>ZiIRux*HvR`Gj3+5g9Km^H+QYXITImX19k9iI@7yi{CsJimAs-P3Z
zSCoSLAfG=A+#&p%QD8g74_%4D597bL0`3SONN>TTyp~?A;k@fEcz=xVM)*-0!B3zW
zTO>dHI9+Ytmm(R_{4mPtIL=p1!#EjZ__Kq7Kf#*^!)`3!Mp5=Se&Tn~iRZs<L@9xv
zM1g`t{=N<(iRb9TB=d_Yqcnw|nhDKR{uBr9le|3(mNY(q&IF|MyEmeAig$7ZO9nq<
z8akNCkD#S&7XOguhS^5GG99Wp{C7i8o69GqqLjyfK>Nq}yc1<E74V%j87<_Sb^vjj
zUrsyZMf`V5(RPMEPv40;%kQF?+Btq>A>ilvHI)2W%s-<zP6>aEVt5z$kskwok+-I4
zQ7Qi+1yU~Y#>%JYQyH&1fMPj6i>6MOdF2ftD)^bSL0`$Qqg~x9-jm)~SNPA&pjpkE
zj)%%sexm}{poULug85qBpX}E0f76NcdcH;im1}(0ZonJ(y;~rz^Mg;KFE{wa1L$BQ
zf6GW408RYnFsL^3lT#pW@=MR7hb_E7A=g&^YYj--cnzH{xyAp`36*v}-xjWQ@Pp_)
z+HKx`Dhzh=cW55g#oxM&%5MILE*QMSx1^y<cX=lY2i@Zz#lq41{1<ak*~4!tr=98t
zyjTZs9`gTEB;XN$gRa42{w?jaJ>eB1N>6zQ+K=hw571Qn8DF{q&OGNQkfj&=2|6qC
zlHchC@rwVOVk>?8+Fzjgn%_Jh@P2+o0W{z6TjSB)xBSkdfIA8gM$uZwNob*LQ)eN7
zvbbD?m9)L!DwxqS-A#xng~NM=?mZ~E3-*+_;UR3j3Q|wu^hNmOCHQPZ+djdE&Kr0O
zD;i*FzwiK&AE}QJOFO>4!aGiA^AmPlg&}`oTP#!pgx@#PTIYZeVG4%>g}?qg$|ZQw
z*}j89;|U;wg)J0x3=uxw2XRO!^T2Q&79My3A1a)oy`V55Z$2y?5q_s<_EBL;5LCj2
z+lyf7n6Rq~eTfh*&xME-&e3LclyHQO4MYo8p-?d%7rvsSlrh4&1puB9`YDGkR?r>+
zTby8i532FP5?X&H2;1Wz5`|P6*(AYBgcr%emJdLhB53J8P8HrzwEm=U;4W0sgfsM5
zPZu^%L<dg^L;m|23PJS7$rM)bP{}e1s}2E?Ej*@ZV~*gy4d!!&>oh`n!jFexK3}-8
z9i;+c*CZec1&@^|ofh<KA&Lb3Dge$1KmP*FvqIHKjMF*cx1Z6q^FsbB*ew=jK0~QQ
z_<Rol7lbA^04@rTbr7Y3v4Wz1mxRt45M{!NqZrF_;SOygUKWPMg0w=gH==8mLO?v&
zs)QMFC|wa&((k@nNcj$=R|Vk%xK<;Ke-87tLiqrQI$_6Vh<f30G03h7qbc3GLC{mq
z-F4y6CuqAN*csn~rct;+>6cByxKj|#LJwtw+!WSdf@l%kWI(hE?|zL^n^3<PG`9rP
zK;YYj3W_Im2sddee_L2fA<Rx8DFmEdLVF(Cx`ma)fx9DIro8{V!rU7myC?Y4y86Cg
zanA@~kMQ6Iy8S@#r>Oly;mSX_uO11Zi_o>l!Yhi|JrPFJ1mUR=5eJ%HA-W0T8Ez=}
z`&?MB0^o(Pi`Galh3khQUJ29anb0T9m;}w&!ie8c*)Mq5!rmL<Uw4SNg8C%I`W(eG
zW}tBrD>xW*7V9#><{~~XfZwj-XbDu^M8+E`d&Tfjw7H7~G&A-P2iyj?r`S)owU;=C
zw*2;qg)F+}EiU^UUD_`ed;u08F+c_LzT#oZXYdp4X)@_A-Zy9P`wI~FeE`G(QAhcy
zfuajVScAlhQs^8MvuA-cSp0wv7>9@pgJ9{9IIkYg92SS2hi0glPfO`AajqxYj)-P|
zKr>0)KqrHeMSd0>O%cn-LnT%8qu}pJ@d^cM(!?+6H)2c|3up~}N}NLTzzp$gnlWaI
zpHfUGOYA9tYuVyLT2AGN&!S*AS3Ecqz&!C;F-Y@8ztg}Kh}RwiP$<rL1{0^n^(u%W
z@n0tZ&WJx!67yN{cgi_GCk6(hbY3j2Myc2+7GD8diCFCnhcAdbXw7m_yt@D{mWl?-
z<Gm!h4u**`@he)*m5ag;0A3bDmw~22oJl``O7Ri>MykYqdJ0?-eSd;$)#8vNC|woP
zo&!)LZvG2~YQ=dJaH$g)o&t5fXnaa*!)xLKN)~DmduXb8UECcB)f?jUv*>oC=+8m5
zN%Z*$mYT)CSZLl9M@@lf5siBxTE&MH4r~+G(Cu+cyg&zE+Qsh8AnOpBaZtG}{=O2W
zPO+{WJ?j$l=7X$TWR3Koxg!=(AmXm5cn;t_aiKK~-WT`Nk>nn60;O_45SM2`<)N4|
z2z`1aerylY$KszwC_NE3(q~DYie=Q_UNJHqrDx)aRlq$LL+G}AA@+@c`Ilmb6-uwf
zuPCFsPb~cJq|Iy5b|5VEi|c8A|3-ZLAuPQWQ|S1-qk7d!bj?X!osE*Snx$E#i#p8#
zmR!|hBP_Y8&qkoMSFNERth<^CfomS>o3~)XQ~idv_q^2G-+*(UIx8K*Tm3HG!28t!
zi~sv1srn+lWPH_o$gZDyM=aR<)qF2X0ctn8FbC8cntTMR@4rB0kh(blJ{?qN<-n(4
zwIiM23Q<3zIPD>I#t3xcuzKbk^gdMmCj$?|)O+axb3`3OUmiKC{_S_DgsW#FX*+m%
zHe+p^updrFslA+GIa<AymRHBsD=5z|Ms1*A<q5T~J=$W`jlY66PTfiiqj>dYcZdY_
z;4Ek+szd4Lk)-~|2V}|WZv>Q5)K%BvK&pDg0>DqIGe3s|Y3le{0Hmue?Vxf>eZWXR
zfeiIf%3jS>U!wagOZ`p}DznwM%K*$#Z}x#|t~!lE@OkPhG#SZP?<s=$0`-h`kQS<k
zB?E9;?MlnoB6U3lG|s3;QQGNQweee2o>SjFh|+oWyVlSwR&!ERmZ<lQGlKMjdVw#x
zc2RBj6}U^)o1!q%m(+J@tD{U^(vG%r^$2?DTvo5^g~1B-^bg@vrFtmc(N$_KJ>ajX
zkI-eSR_Ba@`KxNLIS@7K0V`mkRvkcd#ya&miaXV-)1`3cnmY4$I_}Y+&U3^-T~`mI
zRlp5(!w9H0s&8xszDYfSMz&cU{y9wCRA({(wy58{51(4q7issqP3_PFw{NMF>8wq=
zdSw$#bf`VXL)=#1^n*&Lx`cMkyVOJI$=t1eO}mVD)Kl(K!0E2~-xlcHQ|Hq1;l5fZ
zhWQ?~niAF?s1*-TdZ_-EXdbC|&jjgX^;nvBJW+?!y7{SkHl2LyRX?Z6#4~kNGTeTy
zK2?X(3-u`{lwPWDQwsYlwG*9s>{FN0GUv7W^~X>#_N(X9_YdFT0zvhy`p0?Dan$rO
zaM4L~Q3VsunlcSaE*j4+w7F_DQ{hvfhF<`?L7IOG&~{KWW+d8zHM`#fAVhO<8rlwN
zCQ#}?sAjbv0AZToD5xCKyh{<tqZ&&C%!V5^tE*u5m`2!uVua?R2KY#gCw<2vN^`~m
zen)F&5$SQwR0V)Bnm$_Gp3oSFLBwh-10dowmm>j)*Tm6eBtdh>3YRHSW1zTilIA5%
z1Clknwxcptb7wICCp8QIgh<mE`4*6-Ym8c0I;HuRl5R3IWfXYL)co89pRzRbH5jjK
zO^ObhIT}X_tK@3_rlT`?n$KvtlCQCU2X+fIUVoykP;=;0w4K)A*MOgcCYNIVXEZ-|
zK;^6^gDTHyeD=e_c}=d7RuRRTd6YF<qUp4S`3stUTBcppe6<5KrJA7>RlTG+P4m$*
z%~kqdNV%rT0i>5T!Zet#&<v#*Yo$gL0hTJw-2jLyn#7~1tk!%%8Kze?d>u4vH2L8W
zwVIc7xU^0a)=ZP2dd-3vP`##khe9U}nm=hVeqCeT4RJ&BDedkxYDRtzpPDq~lpNix
zdE*Dto0<wbA<?4gOay7GX3|Lb)TYV(65^I-$_DhMU6W70@D5EDogBTbxj`ulotimm
zsO-|rm`g!`ZcRc8*zRa1Si;g>&G+BIi+h^gQz7natgnHsN3(z)!Vfe9EP;Qh*)2jm
z(%2Nj!^fHrX+ifybLKl3e5(1|4FlAxu{#d3XPR$jK=Zj~h%G#Pq3Kn??n}*XnkBx{
zm~N*aK%YjXht6vaOS=pGnxZXGeWUsMDe!MK*D7JxQOnU0Y9}o-6eVZvdYXv3XfG>K
za@FQK0_Udvs1BriwQiI)?yj9eJ6RsucPUBPQ#;iaoL<`3Pr$iPJCC-vytRuPP-)z+
zT~GU$KH87y1@5c;g3>YkwBs&A$6s4V!I}W=&7YxiK$~?LZGqY)6xR>Z?xDPqgIZJi
z{RC_Ou7e2CCXWZ;kapo%zz=I*reX|3webdYFig9aj&&Z<hUh_dR6CXKz;L5>!b2dA
zX@8`1$`M*U?Yu{7>*y><ls5J}O3_-kJ3t)QI?qHYM*ABDFHUGPW}y_T?HUN5;<Ul*
zpc1cbjsaPMb`u4x617$I9!k=FLG!|7ZNej{q-g&d2I^Gp&ugJ_Qfr)Q2{+QTd>h!(
zwPRPH@su{V2hL<@uPp^WQ`>9;l`O5vc2s6-ORl1nqkT(z&$-$u6v)ieCS3w9UwfJE
z;{xr9tuR=ql~ESfY3=-Ecvz&Zj7H@dZC@x1oz+f>09mp2t}zY8679dUp?Xm}Z!!#)
zYR4^tZ<n;Q^8qZ=y3@B2%e8eMq3yEvI^C8P+9kbEsnmMVnfNO0_#nWqXuauPuhyQY
zUHPlp0vEK^Xd@^tQmaj%cUzsdgyJIg+Kr3Aa!vc|6FR-opdCryMY^ul`Jpp6w7+}-
zohEG{eKn|AyPzMIZfbjI&%8zJHV36v?N8a@Zqs(Tf##NWdnr26uKknpwmY;DL&14l
z`wb=1b!w+k9#NO}uNr7}YyD}1=#Dn<W5Dlful`LNF88z@CsBJ}o3#|GJ=*g$kA9#%
zCxy;Kt)vu{kG0jb2mC~vO_RQ-+VIB^z1oi^0QXEgTm?(dwem{%`$D^sF3d~qTAKU4
z(%x}IsZTqN67gSaEof2PuN^}(qc_@s1_}ba)vDe=)lp}7j9xhDLdQZl>o&DRxacG+
z;f1TN`VtUsx{Em&guS}xNigWHn^6cA58V`+e|zd4j0TIB&c_Fp`*fE(F&5ssrw0Mp
zuiH)kErXBFoW23ztNZ1@rI7AcE^tPF-Oe7=2I&5wdBy=<>Bn#}P<QkeM3C-J+N?XM
z3ua+HSQk%Gv=H5#vnU<X4W+Xnhjq{9K!oZpJpepR7fv_Z5#8G_aV3xHexc2>aNSH=
z1su}_Qq&<r_h<%6k-A^U!F<#r-G-ScM(ctpJMg&9f%+7qi<d(6gwB`20LSVY=nWmG
z(~LtYUY9{>c?r7TpTSb1E`K+=mZUStAd+=zDcVwWkAsuX;(KDIli}zo-Rf~5%h0K(
zqLitdLpuOjx|#HI$ksK|5!oEwb_z!2>aq@?FL}Cs8DPoRy{25(0$l_}d<u1iD)i;F
z?wy^eEYj_w8TuKWPYI~c>eh#0n9k`=8e!qQ?)7enVqIVG%yW!|(Ju*Y7j^qR(7#fh
zR}Ac3(pBz<^)j7%KFpTu4$VdBvTpe<s8r}aN`-|=U2Ft!Rl33SO1z@841*KZI`3Vu
zcU2cekK-EMml7DN)qU~{;B~reCur8|iYayMn(ho`i#O<sjn6@PUH5MpbZ+R{CZW`*
zn?UD&nsmOjb=<6bPVv*5I*A>CExHSI=~{K{2xzwHT<@atmTnfMO}FcE--Y=O-Jti;
z`A52AIq>PR&ipt4Pjt^Fz?rAI?B5}Jb+74J`ApY7od))~E|lh!FLbqMfPbkor*z3z
zy5DZ2txs1$8JVwjRcUazU*}0{tv5QiNYEtN%#%Yi*=9Q3s;M^qL(z#en|c}A(rxAi
z!HZKi?YXGTu=&Irm6<kAXf>B@bBm^0xi-%eD9Vs$6TcBU1vU?9XQ$9+9c@OQw#hT4
zD`|6`UL$90CawqDSsOj&p`5enrmdj!Hl1|G7Tdf#9`Fk`>%-|v+GtbYOsUOU1yssx
zEGZ+Q+(upn&C50ogHTyv(?R(Sl{Rk{(Dyv5Y)U6$gs#{$<)E?J<}*9cT($X(=CU<5
zEPa)))@DyJN_934l+0UiQ;`C|HJe$KxZYs%A+5u%+b|SNx?yvbMz+zW>2GwR$tHqM
z@if~Er4Z{)n?;LI*<#})z^4wIf4$+TvCGD{5!~H2=~hs^W8<F#^LK4tuK>+Go8A!+
z_ig^7NNbPHEgv8r*qmJg%||w7?||*G%^5mr`o!k5&mo@LAcF?i*QO*5D$i_OU&7z#
zHe*at`NC$PGhJSrU6hRW%4R)%Sf<ZtqoaHMwatnPFwt+Lr<d6qn+ufY|JJ7B3(z>~
zLwX>b^t1J7bJkb6!IFz!@h#X~^&#}4bkpyB1eLw|;oqRrU4P;$2oL>w+G_LErwQnU
zmww0<SlFkp@JFS$J}eXc+^;v@{}$3mzkudEzIxX>0R8mQTR|G2Z=xi|1NuwzfC$uw
z(*{D2Uh)(CKB#YL#?2C}U+o2z5dArNaU9YQtbwJ&`adY^E>y3hUC%Im-g4lM=x@=N
zxsU2?$G}3kKKTRy$MkoN+dvbce<cSnQa}4TxTE#aQ5dh|`a=uQ-xz(L8i*76k{>W6
zvHDyJGREuMx`0d6&!wkFl71@f-lXV_KSQMI$8LtoN&WCl*iF;d(@!N`UqcJ*Q~H2v
zSjf~brkGHc{?b}{BxUP|TB0#WKhhIk<mxZ425Fw&eLq~x*O!h4O@V&c0h9{$Ui8~O
zt?#cvWs$y0hsrbhS+vP~R_{3nWaso}0^#U+z1tyF7VCS|=tPNr7~K~a^gfi^a#1g%
z=}@WO$(k0JW%`}3p;NBEM*C@(^}n(3twO(WG)k5F?<pi*rJqhYURU%}YEk)0zdQzP
z?zYP*0`F;igd&$-wrVG|1>5G)df>3F7X{mo*uJEQ^fB9K?*SfV8#oD?v9>vhsEo7y
zvKq%jr17@z(gG&IHke)xiMAg(LMO@g>DTZg*>*3zSyOBWucDE)Jx~amleYI=FkET2
z&U8{d-L{B^`;_f`N(#%c9rp>$XW7nP0$jH3#xGEL*0zL>_MEd_Zw_3gZ53r~RoPbE
zfTr<^?bM%Ox7zlnFQIeQHf<H0sj>Zf4!TxryNSZLb+#S!_N%w8hz0(dZS+b28*H<R
z;LLSfSE9LLYxg%u8*P1u0@q|az5}>s+i8)gylLz64sb2D7iPexR@)y=p{>pK0nLcp
zjkeB8aCg{_%mbT?U2GR>UG41YHScC8*#O{Py9j%bhS@pJ2JncTT^veB?W$?E9&R^|
zwg`{exl@Ksgx$9PHgD}F&`LPkE`r`8F?RdTfF;E)UIz=Qb{ij|yC>}eEzy={XZ-$O
zT&Hw9e+oIAvKw2BQifgUx9~L6&d~>!PTRH8@}S6Wy$jmT*ePux%ItnQ4YqQ-mkS{-
z+qqOhrNYig``=Y|Q)nZt+HM&w9<SOJY2Zw=-5&w)@TOfCt;bvJCeyA!tKC84N?5vO
z*Sr)o?RNjr2XUU-t*2e_XLbXoLG`(vYXgSlh26eCaeZFeN$K(2XU9^y@oT%UoYB^A
zx7h-vH+CKW0`6##QHaCIU`>ge&IX&A@WRE=?SVE|!;WL9bTha&qxX9aK`Uu;=3%I%
zqtBj(h1Vdw3=emrGy4oNgW$Kf!Sxyt`wdy&!IF=Gp`8w2!!Syz^EX6?03KktmxZ<i
zhQX9F8E6<tD}W#a*28#C8Loc>&0s?m1++p8eLth^u;C?zeM1eqzBO5jD{5F3fySeT
znDL;AF&y8F#uEm~VpxhZtfLzu-jF#EBGC|~K}VAfk+kwpF-)LmXsY1{nmn8|Oj!qm
zX@<oX@FLytEZD9bbFB2Afy*}h^#}T!V_0hql{~|Hd9ZNaP)pC{V#7h&?<_II+riNb
zhHlzjzGw)iqgkbf_vsF}WXP4EvfPlr3@n!oF-Oo=VR%r4wmL&;DO{>IC=P=9roood
zRa*>Z1~}1b_}ECxkv7BiCUpCjVFAT^+YP&0f$uO(n1agNhI1Q1(`gt>zpXCA1|Ils
zLofaO?ijo%2jQ-v=o&Qd8E$Te7k&fThb&Ct&j+Laft3$e{e-`V)dj*g7iJgz4qO>^
zJcJt)Yy5B3%Y;zct2^Vr8#*3LU<kmT%u9N^crlGM-20f>-%AF_LYZcore`oqBH?K!
z^V9;@H;XBp0pGHjuj%&4VRnX~l*{}``BZt#wtu0L&zz%t@dD;B0~}UVi{S8S#(uRC
z-7jKR6asOE8T2u9&N6enP&&t)k44*g<{0hRmoaD74j3ToWPYRvvn#8;3A`J-bO;RY
zWgB}@>CPI6%!A!cIk2AWYs!i9Vx8$lu#Y{s6P4bq%a;J`XCG6%(}%5JCjT2ZEBo9G
zeez?Y>2>JOYD3{g02_vIku02TDL}Vt*hg4N%l2}r382}>-M-EZkoj|e&H(p8?$*2T
zH<U}TR)8FTKKr&5e^1;>$w*(U^MTG}9Zj33UJH(>U^K?tbjvx6puoEa(@&}PIFLq1
zqp}z;ngX0<?!NQCD=4JXr1lLr>3x`Z%e|Guyrbl482Kw{wm>iZB}EP>MVJKB(UwS)
zK-yf0GMP<TXwfD^mH^(O{Ja_}oyskAUbaW8Y@t|CuX1e}R9`FYC!yqGHF!wy_mzx|
zanf4U##o8-06Af`@?BVrwVFXY%5hdI546Qw&8E3(g4Nnz(Wyi$e+n}vS;;7mEZOQS
zI{K7i<>ZHMpRyXX2AX+RTihVdS`GUKWTjRID0Ek4l{_Et2CKb&;Jj`nB!cCJ)p_Fu
zs5V-u2f=)k)%4{MJywfnL-m2xucatGv`VKy;3KOkw3YnWYGM)$KC!B%1O88~!bZVv
zuhok|06eog?Fq8yR@K{}^3v+cVVHkqW&S5r`mD^Jpz^g<ABCCwt?X%v`^L)tzyD11
zt(D(9;C8fLPjho8>j9K)>});N10{EB@3Elqu>P7taGus>&H#E@=RO0?KI^8pxCs8%
zhr3Z3U_Fr@W(TY*D^VF}y*B}NgRD0;gDl!QDv<`(dK|r?<E?+J0^p>zb05w3Pg(!I
z9zD#no^Thcjn)Ikps~sNA(7s+K6nJ8#oBHS#4YQko6+rd>nXOd^wPTYE^ZS?)lWPO
zdaJs=fx-Q%oedC&RHN-+>6q%PiE#UbDvS0elT{sbv^GPPvjK+kRVMT3`(fu)txmvS
zQgu>t+7*>J0;<<kYrRprsX96m;<oB>3RLc^zFH2uPgU#p!I?glDvHL5uczDJlix)9
zMP7Uq#W?oy6I{XK%}3yuBi+yMO$ES*FDOQvFTdp{TqZw0s|qEfKVK9BodEuH8%F2=
zKW8-j4&*<(fyN*{@_hgg@&l=B!F+W&fFb;}OQ?+IW9VmmoDVt&Knx#GN8?ZM@-_@*
zEI)!G0CBvs1uXIWfM4N#0^ch_Gm)PV3z5W+{~9XEM!vuXh!j3G3|&j*uTc2sBwytK
zgK4~ulBd%7r!QeJgWqrfnwk71+RDn}XPyNho42Q3;~c)%9U_+>MK8xZeiE&-^Z82Z
zXaPU`ORyC3zO*Vl&AY7uu85!TJ~Yqp#>7BaI?KD2q4pf#G8Dk`e6c@<q>7&zjy~1%
z-~0>iX5Q5ahz|bqLGbV%FP{zWCp@<bm3@5FOmM&E>uaFd&nJ!s{0;w_GML};TWN{w
zC<M}1D7=LZ6R7MLGNVB4BWR6dq2nw3k_b{i;W3@`^%pGZQFcK1d@Xzm6h`g`Tads`
z2mYX7Jqy5KA<YD(5W%MfB0_je`8$z9O*l$Xg7yu_qJ_uPQF&Z2)`KNR=n8`uCxq#D
zP>K~?-#{~7a6L)^wFKd_c-T!8#*V>2B?*qlVLn+{M@c;?LQNM`Q-!LH5GRH2&x15q
z_{JRl%@b6ufENl24d6a4Jh6kgB)t0rSjvQ1)zG{wv`hr9Lg@b(rFtRYCA_~T7|5CH
z!o^tni1-bmjee@_LYNM09YP{a%x(+qG;8V<eDA}xF2N%Jed-oIp`ZU9VLoN_-W94S
zlyFZN+5p^r!R2oNdW0u3Sb89gp9n7=3Jao8dL;ZxDc+BT^}E6HL^wqe<z8XtBKnU;
zp9xX4$@W~3O$PpjuxSCrOX2wt^zfCC(gRQXgo~B1^ja8C`2+pJ=JQ~CBW$7!rMJR|
zG{<!m)eC`h5^KVt;w(PM2d9g;<rQ$QVnh+z_KR<5uIM9v_!c-{@x2^q8vVo>Tfi0|
z7W_mPU2N`!Z^$he2v37V<{x+wDgH%Kt0>Wg-el3@*kY89i}ClM86&y|f%JsPPeCbG
z9C;L^apJ)`;Nr#VczB;6F7-oOqF8kTB1w$63TKkV`R#Bm#V8(F1-4YtAMZe99N5t<
zlrCC-3er>J;|`QE#EHXE$`p?rMJY?%`CnjJe7O?19B~l62Xn<}ia+LwdoE+R^Tl*q
zR2GPT9)lN!;xCl@aatVS47){Q$#i&lMl?`P>RHjaX&?}l;(Lc+zDj($5slSidOUzv
z#nSgsStrKPiT`@BhQ{)~$VOnedPMgRAo|2_oY3}K6e+W!UrhfVCf<k<^HBL#<S4@B
zsQ!kBqfTn?W$@lvUE2=3F6!;yV`N;_M&k|`bW<BC%C}cNcL5sR)g~W;%|pHaL(q7t
z9qF5`Uh3>4D0!<#(gbI}I@J`FKI$!tf%8=h^T6$=cK--%{^~R5!5yGpQjfL+YB|M?
z0@b5vA3jJuiRRr0)e8bq!hX0j<(Gu0*V5AMkopvz)jO<CrUMM2>IlkIh*gIlMrE9O
z@pM$itDTmil%U@8FRn<U`XIeqlhjQk08ddn<ic*M`lF}l(n<AhT2-d0H<ZJRboJ=~
z7&@g6sf0K-eAtiZVA}9X2MTDX505VcjmIaSEry9}BMRj((K_Nl5or3ynA6<t%@~Im
zR0fPyu7U^|`vE<!4vppMl@mJlbQ0K3jkRur`SW9aDD|><?7q2BDIdF#e(9ZKBc^~X
zcKn7)GkA(Wf5y=k_Fn~UG>2UO;YaxU?{5_FVuQ8|e{XwB6SM6KU-0jkRRydgBa8vB
z6Lac1O3sX3I262?xIv)V$6PLl2m6^pDc}iWrc%z&LFVKy=<89&coZbzOy6_rIn%?T
zEtX*@ZWqU_X{2~#JadaqJ0&pF$AUDSnMw!2PcapAYvePUH7FG@CGSBLGTM3oPcs!1
zV=HB>XlMBnW4s2^GUo3lm?&ospFvw4lRXS%^^9PG0l3B#)BCA`iS<NfE8|7`FKvwB
zYueDe#q^#BzMV0QL=QWdL>G|WW;_SO?@nf1JKDOKKl@>~n`w<f+asp_2~0d@=F(69
z33HKRT~8UFa_f7UN^6w*nfEB@|ArYj3j_3)SsVv199cQNmYrBrN-lI}`!Q27N?q8X
z`A~Ib?+}d}8%N8iy)6GdOt`bEBQWp57SI-tC!6e!9(u8s^ibW$KAZtfZ`O_W6Zf+n
z-SF3k{pb@2Up9`iRQ=c)26*Vt{xck<0M<w|h68K`53)e^n|DBM3}Tl`p>vQuLy^&7
zw(1WwhOml7FmZ@YoeED6v+oH|31xEw;8Pg8k4|nKVYgEV=_oto6X0UlW3*9xf>oYI
zWeR(T9w({n(?kGHvK~*MlExaNP?^h)>qccB+ucc**T}y73fu+k@pZ6U$ZnzBh7vZO
zKD}^(_1q8Di|iK^F(_q2{sI0H>+>C4D`VGg1E8D@NCx)}b|8`yq>b#Xy&!91o0kLE
z%tlgdy_L<r16(_+nF2ruE7=G5Z8n^;d^%a<-XG}tvPqxA{cbjoPVL=cM_8iqF1zvy
z+8jCm9YDBq>v^d7a4QGGU=a7tSEvl*=JvyG6gT}Bm`LEFD6KY;yBrOX#EEpvCUZYh
zI$#QyPP=@m-0$b$VLrFB85Rn-3&s~PSjZiJ7rve58m>X7i2L-vFdlbT3G?T;e@6gu
zo=ctxQOwz8LzHkkX$$WHH~BAcU*x7W0A9mc&|C5bcb`%f+PD~Bv~_c%x1#bPx9|c0
z&$%ZQRC~ka)7RYgN=EunywP1U{w*3kB)-#8@{~-YgX><Bhja>OpX5&pU3p8U%|t0g
zva1*V9+JFigUVq^!UNERO1`AS3t<uqTBjY6oSOxeqmt@1z#Ws+(-R^>Qc8PSk&-CN
zUXGIJC>uXo!tJ4B?8hZ}mUIhAJhuXvCRwM1!#R=_>miCH&R@c(3z7xlz*k7F&^=o#
znNK%)ql9GuxFtFM3YB*yq8U`~Ny6&^xG#Bp2c;g#AGGRvAhF+!Za<V*Q9jHgiT5S|
z9!qM!qj=*RNz8X}@vUSD&2k;36A!^RCutyMlse;^mT=8Q`b7*7uF`RI+SW~)M~MgS
z(xHE$%|p7h1Dc-FPb1)r7lI=Y`*1880B@<9COrG4pXb1Wk2IqWrC{kmXQ+fo*V0KB
z<00wAaL^o<#*xFJ(%yYEmQr>n#1ZKfn$3hu-?4z|G5i;Opox%j&gfyJR6&~_QPQ5R
za3)&1jZXO<m$uNxX|i-nHB?fh3u(fWDoy_aZ71;!5|E`yH&aMI9iM%Mg;Pf9<rL6l
zNKYMw!&%ZyT6|?o=hM0}M|zF6jB=&-Zo+P!H0c|ROujVR18fD-1*=h6D7D@InhR3x
zD;T^eH9HAFskD>g=9i>FZV+YCB#O}EQ|&ajxGeqX8dNHzLx094tVFzZEbv#PVfA3E
zmbMOtiL27(Mew^uI^ZEHYo)b$DAh@4WCC9=HJb^4uSwGv!e9gbTSsu;mVQcGD4o)Z
z5g_Z5)^tO&TRJZreYqojVMN<q=_UoJ?@Pb`2Jjx~*Z$CaAXOP-q4QAMbQHCZq+eG-
z^|5q*GVH#Ue(!`zN7)a~@YG3mgQBL+GRuA7c9Esoqs>*8Iv#L0**CuM&|Oww2Tc#z
z@*Z$|%0j20<Rz=6dH6nA&`5B4%dS!ccfYK-58fY^jg!&)FI4s_2gNYiVwzDNk-ep#
z;Za#8ZK#CH7<v>Qll?-!)Ck$0eef_!_BapR(Xv8XpB<NlZi4w3S<nx#dqVbzw%uZ7
z$z2%dIN2~?;NoRU+D1AnyFCZj^_(o7cF)RX1*d8L-z;mmhuWJmcLyN)W%cxSiZ$6B
z3AXblJJy1&*kqayDjQ7<<*2-A65<W~9h22IaP5)F_nE-GFyS*W7B5X4D4yhLDyaa#
z%XBpDRtK71O@R4uQ<eg5Crw@6U=Z?6oAc=XciwaqWhFM6eom)i9+?Io0;#)v&kFby
zC_mQ-e58Dx3|^$lw^L9&LtZODrBptWrl6PP@uPs-r&wl=N*_h+Y`EsD7)$rMpTdFG
zu>lI-k5G9)VWfQJAVmq?dIuHEGq`O$thnU>)lkJhw$KSvBy~aOsA5?lTntx?wuQkc
z#Uy%^Mk^ND0C-%n$p<1<@vQ>*1clYFXiHX{NJi<TBEcK}rYlbVh|(!V&la?0Dt<i(
z3t5W!lrfO4kW-90N6|(T(lVpsq%GuS#V1!V2vv$!dWc<Be4h>zwTed+@vc{VZiE*N
z3i&LsH7bJXCT&$z+=q&@*<L!J=W5n{0j0fWZ&$;vhgmr#@cNkLZiS|w+0ImmK(n?_
z06%E<-D3>NA+y)?G7d8{#yp_;ApVHAcHr-YIkfk)Xbq*_Eq+W-wj~cn;NMFFDEzdn
z^9{hu`4RZ{igS^uU%50FtgCzv!NgCaSHkSi69?e$)t}OC<S*xK@%Nf39|E=3;v_oy
zYYweke-kNb%6|C{`W)xBmQPUFe$^ioJMP5535SwtAl+qp0tR*`eu{tZspLRp{FBDh
ziFrexG;(HUQTDqF(`N(Vey08^ob_S4=<)B%to|4!Kc?dl#39ChBvcMFj`LwCl(~o4
zsx*aJwjEv>vzUQhU^~s2(RV^FFn`i4xRP0MfEM`pBZhr|zr)#WwJ?2*RTP0Rg8i2w
z?UAg{K^Ti-*VMw%SbXLRm2vD}_raIUzM`3G3Ts<{QY!02$&VTAbPlCVwq!a)7TdU&
z`k&3-rYze6c9Jg;h3q{_7Cp@_b-@KX&zfw2`C@j#N#IM^c1mw4V`VO|Th7){e%KW@
zd=FHr+0$p>`Bio}&6#T08Y`$Yu+P3k={h^qAEg^?<EJRKux$fSYGp@a(qWXgvEIXg
zzr`m0Hw$Kciea~#y+V=DJFG9|LOx*Ai%|KL4GF-->t#Pm1pXNtL^n(ydv-AFI&woc
zLi35dZXbrRR}u7xwmb0W4Rh)Quy2_R8XZS=1syzeVpln$BhKt9;}C#d*hv|%=E^Eg
zK)A6=Gc@jH<0xIvon^LSJUrN1nrwTrWyjFw#jd5jm3^$+b+CD}qo%{?ezug}k3MVz
zHUuyQ{)kR69Ac+Dg|mm*6X|FRW#{Fg?F7578;0W8p*47_{=ds?LhIl~e=mmeVt@Me
zF1bYO<)wqsEM3;{1og{DIKqV$i`zi4(m;WURqxYo_fKOA!1nXFUC>{>eJDKoWjuWc
zY0az(aIPIdM<{;XQw;reYbet4TkS|N{88)-lyO7xR2bVDLYvat>nYoNN9BiTaAk(j
zF#|Vd0p(clWeUEhPBETSVbG6JS3=#Nd0z>K0+@+|00?D9P?mBSv$+i(A7P?S!-a6B
zcmpaU86#Oa&V(o-Vj26Vs7zq?ensn_WadXoh^%BL(<8Tvkw&8jSD0CquvE=dJb~S-
z%(%Z$y2ecX0{A9o11+lB7(7IAk1(b5jon^mRxWU_nB_O1($7p84zjmQ^dwL_vAu)A
z63!NQqcW3i*z><-s90>&!^<4z{ZRnrG7*2muRLZ(9|-fAk7<LlfZ@kN6fz%6(XG?W
zbUGql#Bj98E@eIt;K3#4dNJT-%t^X8${9<Fb6#d5sIr17qrKWnrk270Rm@}x3fyAU
z6rE~kD(6z(V+Rv_4>Uc@MB3MRz<f+&{DP6u)BYu6q|k;l8<qtxT-Z>W%)7GH_V8jq
zYqk@@hfSjG9ba})2{c1k%fk?d*u2TOHiy~3I*2HCCuKQAvs-B?a-2O%*;g@a+Rt>V
zErm7E^D&jZG8Vubw(};O$z>;H!%`mm!D-<0*%!2WC}z7Uf47AFEewDQ>{$v>US!`R
zgICz(HQ=sh8{PrnDytcV9@emqw61AlH<qKVnN2#5wwtVq?$j1`%Ig96{kO79KE*)Y
zVX>V{i=K6AG~Q!3Q+((?E1wV1!&cMM>jB$382E?m&<hx#N9@L306b;~hrp*N>}Y!Y
zJZ1l;q@7;2gA%%*vA1@@wdd@Cb~yTio&Fbk_LA*74$W7re+5d$J~posI<Hy%&tU6k
zw??ATo0~<E&BGkC4Q&zJs14{$EcZS+bCOF4gec~+R->|k8$%(H`&=wNC7dLmZUpHO
zNjP1*6p7+9I8!8Xr~+rDWZ^7$-z;h02HX=#@;?xL%Oss?|9b>fN#*81U6&4%lb$q<
zGGJQpU*n<cx1>W4gX*@_VH;HLNVBfMXpgjkRsfHs^Sq(?T$;H8KEIOsy@%3U>5*XH
zZbogKau@Jr2d@LRVv7Q(Ro*m>{&`6zy8B1s-{{|;M>Y8SpHe5l?E@)+c$)*IqHfQg
z0F)z>lmYjhnDzAZ@np8rZk87_gaSAL%=3+)KfuhUkXI=4aVtt;Ou<UDMKk^qnqM7f
zM$@ik5_5#&!pTfN?Z~DuV<={l#Y}tzXR?|1>CKqKoD2j$ms!~ld>(V*836gr5K0Fu
zVEQw`QpnuffzoLv@-2-lbEyR43^Rr%0cRP;0CA3qTny^-%mWJh8;hA{daRT%2^6@y
z!2I?HbS^To1L$BWvu85ICFcA9h%!b=8Fl516WuhInd2ewqJr_J?=@C3(Px3HVs<y6
z@(T0D5~XS;tsc%?XF4gV{syy_P6{<LqqH#8#4M#rakG(8cfyUE%$noS>0~Cq1MV(n
z*IMXwGkF2P-(fzbXy9GOupZp^7(or1`^*pyr5@%cJrh#deLsUOlP&lhWZCRIN<qkF
zS5Y)QpB4R~S;U^$g35DjE2WQ=u;sMCFJ+BvC4lAZE((ZLvfp=O@UODV*8p*y4R?ml
zEmrOZ*Bm+1Kjo;!A8{r1HH?k3hrnkua{)cdwpD;AoK+S<`54PhgXsviX*X;}vWNBp
z7RB~of_KsE3>KQlS$Pd?8DrSLXTZt{_OIUnjAfgz0ujf)umK{Toj`A*1a^@bR1?{j
zCTJ$Ht%=Y~W*5;nVp7;2l(3Y_&Zg|6lWdti+S1rf12AG)Y%J}!7O{UHg~2l{zB)o(
z-n<iTUt(`vgEM7D_NSZBDQ6c?2cnjJxdG<u*ak}Ku4fxhqI8Wteh$DE_U%+S)5<QT
z)pZ;Dl7ct4SW}7uwzD&K1JJ?lrQ@x)+3OpD>tz4F1fROtS4-ewH@-&-mOJcd+BCk)
z4p)He9&2=`hw^>aXE;=Q*sa-Ue89du4)L5#pxNvTc6~e?e#!n#*`%-7Ac~&!u|GUT
z<!g4$1!(rOGp9hjVHXCVZ7)|d5X0rpRnQ~SmrH2@&X1c!k>L<7T?3Uv+_)B$A~<U!
zg>oXfgtb7#b8o|FxVb!<C#Q4%w9#^k`>6w}`JCtpQNSfp6tI{}tV3r?xNXD1eSs50
zpjpLjvVpk5E#CpxsyS;)9lOdE`~=M!ZecyzYPpA>qpgnH>Ibv++_3<P?_T4Y=>j!y
znR}pfoim>WXKrxo4XAA7-gZGWaV1soyP1>F^z0^g@jCD=+^QU~wQ}p}$KKAB(Jp2O
zcZt@Jx4EpdFyF~NoebO^ZZb`W?sDJtp>&TMa~YcVxtf3JbKgDOsXM?w;#Mz)c+7>Y
z1oso}80{nUbB(U(wxeW(1PCWd_)D}oO9rokaFHCK-4|C${=3k0lXN7aqaKoKOIY%h
zl+4D+cuN-DfiwFhV<XWCAIWIC1AQekD2dNcVzrf?e{qsJ3dN>N#^(W%FWExTg!7VN
zanLE3WT&F?uH^VmsJxM;bixY{nJ0~mx6JPmxP4@63!rjP_EQtM56dp4p)ypq+XbaC
znJon&kH}UhLL8M1?*ivB*<>F6M#`pr1xJn1vf1V!jgk2=0LICF-HY0I*%wNXCdlT~
zDlAdf(F$Oa?9w@OJ4N<E5k#sirV-+#tN@>Y`0ueG)cg$PCAPFcTe`y(7MJBHU}?E*
zIh<edlr~gXrcH;=s#r?WUKjt6PR;)I-C-1dpT7ZYe~j;d(w2;I0BjAST#J9crI~^K
zcft63n|V7dZU30Mw(E62^j(?tS{i#Mjo$eCnZc`QM3@|Nu=p}@H0XXz;4L`s&z$PV
zopXqJMsLl-%v<__hce+tdL)H0r`u_qm@~IQoyvq2z*-iw+ZAjDObE@G&oL}LK1-Qe
zT5eS`i$BIN)iQH4;NuPEJZ<*2F$+52%v}brVazR<vnJqlWV>nh;?D+PGZ7EOs~-P9
zmE@ouD*TMhYg%smGbcX=_7F3^5!k~_=oj!gl=+S}io=+~@vs@q*pGqcapo6#{Uk9<
z1L1ixvndvU6sC(_*Qv~U+Kk9%KBVK@IZXH>3_vb3^EN8aG39!c&NF@Y(7AGEJ-sk4
zGsZ1?xKYQrQ(Uc{VJ3p@CL>8isfAgv2_{;Z8cHr`V<IWypTMSAK_!tb>!w?R)ln=c
znT;)jW(u25%aByoFcRV<yHf#?#(uCHJu71`CIE1gO{b5gg>z58fH=l|Wc(G45nR+|
zn26+da<Ci4<$jEji{|EifwtqE<O2X>xB`1rp5SUXLj_Z<3Fu)Q_i7KEiRU^flI<&*
z`T^SfBwJ{O=r4IjX_^6&5%%cl0m)=<zyl>~Fq@JFNoLU_`JiNB7Uk0gOO{f?afoE#
zF_aETqAAz?uq1Il?1oD2(JaGFW=i>V39_Kgu$wH~WrI?>>{ojEX3Ao%0LYdNr!TYQ
z%MP4`N}=pGS`Zb<CT)l2S((5?^O>yXAT+&AX3-a%5=|6ZIyHO2q$eB2OD0|0;YF=U
z%oqQg@O87Tv>dw6&Paz}kJ!ufI`3rz1K`k0b_<1-+_^dR9L(X5P(T@|)0*QjB6F<N
z`1joSE3p0T1KOSVuJ{jtzh97uF_~vU!NDJnXh3e9uRad&@|n-ju;S<o{JpY^l7v?=
z-T3!UzeK~>&rWpgYxTJw0Q*z-3I6?82JPi<UAY9k`ezNDll%8;nsV-5MQPn`%t$)i
zx0ktBf);lsn&xsI%tTsUc``rI)=eU_E+6`*jLg6@(8*;wY0ImK`HmthCCopes4Qoe
zSwK`XZaMJ%8Z&$<9ByVT8d2(C98FNV$GkfkJ?&*y76aGMSXiRXh0PfToF}_|_5Wrp
zLjPZI{r`Ho_NS<?E56_J-MxrHSR_zMP<P^pM#HjC5GFcfVFg@7S0OFQj>y7-R>A_y
zqY*0Uh|$v6i4{DZXd^yq8y{_LFgtyyG*MHhJ~BpQe8-3~O{ZgOd?1k8&msLKe?ZFY
zopaB*=XEdN@Auw&?)iQ_$q5*VdD~<+*<>7pZa>u8s~X_Opk|#8HN)D>Y$zSkLi-{A
zSZk5jY+j{3c_6N#Up@)W4oW@&RXF%+gC%6QT?NY~I<Oy_yXda0%=c4U0N5eg@R{N3
zf6W<suN#z4s8=$UFVeZ|P<V+hBlEExQIEV*NL?Yeq473-J{zn9R5TOV=ahUJe*Kef
zj^-}VUD+((p$QTnc|@;zp?-*-laOntK5rP{XZq6-=>ECBsve!}((Bh^$h-BO=+@{(
zl2{^(tuGN<f}(rchI8`5;(e{^N3i)oi|Rtx9%@@8CNrqr$OLf>y%`wo_SGN4=Ib;g
z19~@LfeC%xH0KD!H`DKAr^NL8Pe9y8mQING(15H~w^M&BEbXA6gmCvzX9mn;J?DbJ
zKAN^wK8DpxZx6xJL2AE^9vq?xate5u?hnG!aY~YWhY#pPGsfr)4N6|hhZK+lnM+hE
z6Ypi(bP?LFkV``CS1DO`^w;R3ya;ifjuk`hQ%aS??i&;>F}Tm@ViLej%CDCA(p^d_
zgZVG%MjyaE${ZaMTDb*+4`_E1h=cT^97YUL{VV9&FeS)ru|}WzJe=v!V=Q3l(Ss6C
z+p9k{0B4Tq&62i%LBAol)ph-p%n1L|t7J=eUl01w_LaWj@8E1-Yy9Xfc*Dk_??UNb
z<A?dc4ja$Oy6%kemD}+9rty2b!1~bm#dv7@si{5!&Tdo10I)44%SQOL!{n2+;oq1l
zn?T&EI_2!;EwxCZ%-fVtBK19L+Av1uZS|zAO!lft5***xuFgrU<hSZwc`_VOpMDJN
zUFH5hyojjz6_EI&+WQlD@n^Mj0wn&T0?)y<!%7XnV4rfzGWf5mSzb1MUoD*g@uTWd
zJmik4LvnU`LWK`Q;FQw6aQn2H@)Ddmqjs!@_(!U=bKC!(c6pO!5t#phY{d&Qr-NyJ
zlL_+PWj;^}xf4Dtm@9X1QO=u?UD$sIt&2{{myLWq`{D26DUV@cN%bT2y?B7j2a())
zc?}v$|04;PFQ)$i4KMAkh9dveTQIQntML#hGb<=v*7^@n%9CZM64=uQ&I-qBbfz+1
z5<-HSM1-o2%mk%+Vh`%epYVdd!Wj$BAB0?}ue{fV)|z+Z!g+apH|Vtm-d}(edRnr-
z>e~A;DD~s7!Ig&NcTo@Tc^32*vk&#wicHXdta;_ke7$DQf|5QBcY?vt0n@r6Ig0Vs
zjLh_$Z2yvC{1!MJIZc6JL9VCFZnfL2_HWSqbu~@ZD{8}jKJZBMOl?_F>vRa8)n;|r
z98R0t;k3JL8UDsls3z<Wtf)=5S~rhqlg3%CsD1t8q#<qc|I^;tA#LNgYcKWNRsW6Q
zi@ZOgRSd9uPIMgieH;^IvP^e4N+L`9>CkD;zBG1DB;_65IC*wXc6v!T*bq*yC~v4~
zNzV<2S2l*~(i=l*jmv{+FNZ?4=`Ep#mEpSbiXeDu(;9=}#xVE-P1Ococ2@t+y0Wu6
ziV?+xqEMnx#ze}_MmP2*<S+4*y)d`1#A9)|ZKHoBkvp%A^)BJWVp9V5om6AEusL>m
zq~+4souzErq~h5QwUMV><GMXO{Og#poU+dp&5zxrB5|w6wLe(5y)GuQy)O0*6Q}l5
zHuE)=5_zLJHf~k2+n$wX&vMzHwb<=er`2x3_2#f;+8vQUeG$8ToF&VZ<<77Lof%nn
zS4CC%tXZ>y_DrYEZVyyeX1anI>sm)*QJ#pjj>IL;&O+qTKv>>1VkRd{*}ZsLAbeoJ
zBi}%=xI0j%ID=t^z<7fJJ68iC5n@&3RF?TdwAR7D$}zWSuk*xQa|`*Sd2_D0NZZA?
za?K01es+5Rx_GUCqkLY#NuD~-ypW6&xp|(sh@PLw#{soUPRtYXB(BOEMGpdns3{-R
z6brwQ59ZuwcsC%J?}H4ho`O-PZUBnO;M)agY-9I)LI1|D%?H}S=LI!JajF;SK5p`g
z#%Mk+=oL;Z1X?(ms|tbc;)8<5Ji}@M(4$<k00z)W0kA6IBzua$<DbEsi@-C&w}7J2
zy>PT~t$-0e4?x8(PF)0^er{R>Y8xLDP{WBn^Gt0$&-Iz7X!khiLmtz6*Z?Q;Mxk8b
ugP>5#zxkTaoJy{2R*TK4+Hy`?Y@ViV<q`n$kML?xO}*J>19QB`obX>KGaS<Z

diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
index ed0c6d73dcc32577d322fed29b9e27ab0ee1edda..6f883304dc47611a6cfa69ec90eae64da7fe5aa9 100644
GIT binary patch
delta 126642
zcmY(r2Ut}{&^~_8ZKvK|)!2LQEo#(gY|&`c#F%I_F~(k_(HPAYD<T#Iv4J20(gYMi
z1q2jqC|D>0A_$6t6agz@`MrbR_y0fN^XS>LGxNSPyQl5W?j<FB_`{RK_qLD+eRZmp
zUB!BzW@T&s=G}*@8aZaKSIFd@?L%ZTnS$XwzTjmFx$29*6)4!kGn`DJRC#{nWc*Bb
zRwkd=XfD|)*?zs`G6kpl_dE<Zwo?u(Gb>dKmaZb*pB&7uHxXqDyQwG4)y_EZgDM%B
zqKA1p2@c^P2H+sM+LY&*LPjQIEKe0OWh`S1fmp_LbFWr4VfwpE>i(Vk|Du*DFET~~
zv|$1(<uc`^&$SLrkQ;Q#pKD#1PVP(9O>}=hP|B27KFbC$P2CTw`|IkjKz4&MwwB9e
zlbDX~1?nd9`ds&V^+rbLzMdV{lnYbHR0)iMoN&yKT^X4w@pDaLnz`q)O#phu_FzQ!
zc3jKRKTP6es%i2DYbEpeOID`(>2r;fj~F{yrkeh_CNbAn^D@=XpKE$1bOv~T`CKzI
zzq;?{nv98`2HCHlWi6QQ?Nu_>tk1PJOy_>0Of_3>_!VJyU^>5+$yC36*7abv_C&<L
zf3Edm3Z}Z(aE*1oS!$VT?q}gJCd$1r-(<A>6hfH)SvHB8cUCS_E%;oU%Gh``WZ~!9
zPs~_yw@7ZF>obE{QU~1P&$`)6OZWABlQAbE5$v+hvgPs-Q_$4qpKGg_IbWa~R(uY2
zEz@`^B3b!aw~?uOg<${sT-zek#JLyp7Dv}~UM90l`DUt&k?H6LOnk1C$+T`B9FA2%
z48#gfSy#r$tQ^~ox2j|^{r<6XSr3X&rtjcjWWDKBDdR(ri88jY{59}OeOp%6POc`K
z7WmJ2DO;Z7WR3ri<Upt>b7=pMs9?QHCjUPYmrlIw1*0J%Z3B_bd5=QI6f+InZ9a3a
z-z=A<eU|iSkO&77m9jwG(lXgk4T3Dht$O@73t?LdSMIh-RT`j_IRcph^k~T4{*npy
zIZD~T4WI!HARay%K>srB{ulJ^8UZ!~|3A!6I#%{;1Exa*rW;{mF7ps}_#cc+Nb=@n
z;~R`V2R!9}jm9@)+W)VWa_c;$?5oeMus3ii$GPtj+s$aYOd%7P4qgBuY?)n27s2r7
z2Dxk_%w(Vara)^PbWtVSL{AUd8GhCYvc><u#gqTFSo*&fjb59h3{s~2i&2wQGDTCK
zC1ZuVTu_;>;CWXx5mnX|?u@Rnb=(_NTS*FDqZ0fZ<Gm!wRqE63J#~Ya-tJ3ucE;O%
zo36Pu-$Rrs6(<;rs(CN>Q@W*iu3PB)Go9Uk()Vx(vl*GP!G%)QE$A`2srwI3c+h$j
zRVZbuo_}@ba1+sGlC}N>vFwQnx4ta;0d8TLp%k~gtmpz6Z2cJzkL+@tfa8IBvd^j@
zn;joW>vM;&9sVQj7jsG8?F1e#nZF|u&y_49fsVF?bX@O4fTYEAj4LHc{9Zb@eNBM;
zdw5!8xxpk~>q2z<+u+%fMas!Rzrmz!K9JnE`bYuINT6evVPt<Wh!|eS5Q;;0sbmvh
zI7rlY9#sqxbpGQA0(Y<x?9*=qTe_Rv54cBBZ+k;-uI7=Y5)YwDR=SuZ;cLlq>Q^N3
zz-^|I#W)i~RX$n1y+JnP29adKa5}f&B#-QJ#(`qqGjb5yiPT$<()p)ubR6{u8D)Eu
zeB(fJKX@F`Inm2bR`wsYd(Cz_&Zr{EsFq}@{D*9wcP56;X`~H3OFU1zQCPQXNZVu#
zok#sG$Q&w}^%R-5c-YXs$<z+>TvDgBBhx=kbe!u$owmB69sMT~UEdzmj((G<#jbc;
zfz*%WZqF!`URh+{cOl6=T`8=p%Oqb=LN;No$xF*`adgN&m60fO35hZdME5C`09lPF
zpj#E>W^h9v%)Ui7>yMJnu7;jSm`zy8g(UwirnU~)PLi%MWcg(fF|3(FL3BDrlA_TR
z*03s)tZ%r(9Fu&ga=r&qtW2O7&os0nHHaLicOtsFu0$khs3)GRrQ__s=s5BxI{MX;
z<;aF^Z_^NHwVl|$F*G>4N{xAtPUo#|Q;2IDn&DYbHi?cI<X)~PH|7gO)YFYj!{}=w
z>)LRmxg4ahf^N|<BaT8D)bJoReMjg0TaaZ~KAr#VK{m>L<mR=39LFCeHsxZ{>U&eT
zT`|H@$$k%`i+=knTz@>HPsshyhIZ@qWOU?vBC6a+=X-vqW6u_36LWx$o3(UgBgv+F
z0%@<brSp07iPXK}wjH7)o0oIQv7ajiF>@CAy1RxXY->Ut*W>!DWbd`4=GPH;>KM9C
zy=&;a(K9-a!w^d)D=sCvW?kvrNkR7O|0JTZnItzoCd+AMbllkBcxyS?_&7+y7LeoK
zeW~638Im+kCDa9su5>EdmYt-o>p;|k`!0*k@#+Rq&nqN~>YLP!71eZZ<fyBESVxjS
z+=y;o4xL9dyiDGuQ6J1aK$c(5p!1Y!(iR6a@PA3i?5*Vf<KHB2*Pgs&yr3I^nM{(^
zCOSTL%%JEVInnWiI{^aqq!2HVd*6mD*S<fw53Q!4hdL3(=*A?O`wK~qxRCpOhe#6S
zPm-`*<o>~3a@kTK<{f8A+gKp&zn6)hpG3#M#yH4m#!NB_OCpzJN*auI(=on~sG}sZ
zY35CiO*%TCqo+VeTp>wG4xPUYBkUHQj!AXoeqI_KJ35he+*0bNAFtE--Ai=26Tc%%
z%a1JG6a9A(>5=ASly;4bHaN&=;9HVM45Q%MEF<k{KROP-Nx{h(vgwyiEvqP@^YSEe
zxuq?k=C7spm8Oz>Sx2%j*O5zh6Y<YzMK)iyQPVrId<3aIM^Rg+{Xnqjd8E#4c&!$%
zB+?rbNYZ*19iwW9DD)7WyRIbEZ$FZootFsPdN74pTSw>H`;xQwm|EcC?kD^8v#8HD
zG$)V8*5ceDi@^8|k6#!OF@uR{-A0l$ZFo8&Q|bIkAb|t^CRkDnBJFsR9K`mcqmPDc
zicZjR&R9Cmj3mqOe#G|S0l7~xljW7k#IvcI<nay9pu^Gd0sSzUT6yR_1)-cxUHZC`
zV1qH3LO>-1)*mHOE|Mf?!pXkRIcn<{airaKo*e(;PV#Xdh^O!|xq0}BP!TjYkX6rX
zu>XtfhyOzM#g1VFu$>~n-Ys;#p^}b)ax(2Qhk|%?jfhI76Rh{2L}XG>H=dqJsGG}3
zlDV5u?YdFlc#kDHA4kU<jY&SM;X88nKjNwVl9=lg=;*oAK@JX`CB>KD(RrJ{sC{}T
z0#DdL@`~9+@n#-Tch%Fm3+5qenc7B@P8g`FWqWi=9G9)&aGZuqrk2HqP*^M76gW3T
z3OH68SR5C9PwoEdAoWVAJLiCCU~eKl*D&ZXpCreArE<t;-KSR0%%UJp))9DWEs?Hh
zc&#?Cp!3ywIyP03rKgpsmq=v!Vm>uyij5lcZ9VZ{!JJ4f8&FL4Q!0o*e*i1P^FQYo
zit+UXirUthB0V&OOxN$HF3NnS!g*|eve|Z&j+wLRLY#;t2fxlG2iqG{(6UXWy|k3%
z{{0Bsv=JS9V+f;`d6kf*3OBV{b{Zo@wQMxT<7$Vjl{dlqCXvhQ85Gy*-VK+d;Xa7=
zCu$u{7-gTr$Z?n(b$d>b*x*yuX!$&}z1?Ods+|TcMYoRlW*yF__V7bXe~5eq?T<S*
z<9u564j_MWnF^NaLz*D8pP9cLsLXk}7?pX==##QsLsxi>FAXRi0Zk#<%xFfyyDOu(
zg2Iy-N~4Pd%;+ivd5~F?g4!X5S&iZ_Gp7u&Bg}^BaO%y>e-5ulnJ@dH<vvUYf53g2
z(IesO7^BOEr61#P%toxonMT`y_h*LikOnYge}gcP*}oAkPB1a_kqct3P5@gl)1)`J
zLzwar0E9Br{zZesnEg+{eUfpdw{|#FMt6P$vo;RGNXDrdYNwc=(ZQ<I%$l8mM=^hi
z(4Ao}?fx0u(aeBH@EgM{G(vio5tHHf95cxcZ0DJ_L8!$taVc;g$3zDLAJ6<74B-Vv
zc>_fP^V=Z=lgM1J2TKx@NH3y`Op1H;7iI?|p>mfwJpg_(n8&}Mb2AzB0dQq8+9Ysg
zGn*0+SuV438o2V9St$tjKC_bEWBJU^E+~qabLDXGh`CEcrxND7od7&#@_qnIDf6xm
zI<$iM<2Z1YjQ4v8pEHVbkX18+<2~9?!$i)9w3g{qkKzSWT@1f3neQ(^_lj|R1L14N
ze=-nnn4Q(Ay=4x!MWFAP<~49w&y0G7hP`J7$3yptdEFQ8o#Z=ckhDpDbsr+!DG&Q7
zz(4-AYfmqYKDna-Svtx=FWF`1W8i6d>+x{ALcI*<E0+wzJdey<?du4O?!n8^z#fH%
zaqRg|f5>~ew}7+WM*1H4GKHAOG?*(x+Mu=S*)*tTom+sA6T=|kL)4hu5@Ac9UlCr1
zG2`&iZDt(lA3(5$G2xxAc4p4Sp;<eaMXm6ja$%-nI<MNvOl*ax@hCHTCfIzKoI;qq
zVS0Rxus$%FOCZ}SkDCQc7y0Nhh<(32h6X=}<ZXOV^O1+_Mh8U5pUed=QT`DRqUwg+
z<qf8p2*;t)`7VW`aUM;tTE3ucNcRQXp&PPL4$CPC$e^i~Y+jC|E0dx|2!V{(TrkEn
znd<;aXB<&@WxQmH4*gFT2=&uJsJAaii#ngVgJyOS@HtR--M9fSk8W`rIGMaV<>1sk
zCVz>~ySnGxV!UX2z2nhOy~QE~-KV2BI=64xRK(FQE(vk;e;0zQIbdocjsqiTB=Th$
z4Od3I-vsTrZw@1{$!+PQFjHs)oB3al0?&$D?V(+})(E*1GiWy&=gj1+1h+fW>n%tQ
zIGAh>CVtFJ6^fJ02^OR=jQ39n`yA5{{duM#{8*+T{y3(g0r5;j3obAewfYh>86!${
zGD9tCxXQvqdZ$}nX5-k1r&yYF34+6xW6mSewtfFYf41MzjHaAjPyc}K?74d%kiE~~
zWvd$4Xc2-LVxr49bSO>4N8X%?*vFoy8PIp5RG^zO9ACx;SGM3=plq7k1=ZH~`oc-a
zC+l$RyR9pn58ZbK^06Nx!8qj^O>Q?bH7p!DF}IPxa;P>jg)>n-$UJ)u@<UATZ3yi!
zvyQ&we$171;5g1qss+%W`85YogfkTY;{CO&7Jefcs|F_LnBN}*exCU!1eUSPg|Fc?
zg;~B1fXmEJF|fSC3_F3QWHN)Mz$A;=br)_O+06AWz&~Lo?gHW|vxXW|%1qJ1^feQH
z8TdC$U|TqR%e>zV;WoMT3s`QK7r%o;XZd_Hgr4#{NaU&x$k%v)?4VqgiRc66!G0h+
zAx~HeU69=LBXBYDA!}iBR$jCUQJizgm&C)x75PibTwIm!cn{?*x#|;&d-4~pA$%bJ
zg05MCd?4YA<?W-;xliO%UZGYl5745!Udv~#L}NB81}z8KR>f5f0IrHzJ7Bp>aS9(z
z)j`F8``|pJc-#t>{tCmtunbT*nvF+!N-^siJe^i7oe$EBiu?({UsCvEpx$taTXg#d
zpw?ekpxP#(E85+5)j!Bpk^1YQ7{aJVT;2y?Bj?27eDtzn9Ot!>|IfYHc<D5>zhllE
zkaj7~!LfU@&N%k6x02!h>-z<zDh8<N&Kp#+0F+-HDMfz||MOb}JaXnTn2wL40nF6a
zn<1ZZnC4=C^nDHOVvnzJT$WY~hLu0$q78BCV5II;@#;y=aC$+#_*<w_)Dx*;sp^$V
z=<cc;Z-K8|^+!>F|C{WWvtasy)gZU3a^nB~gtofz$`LR<qm7S;Fiz|A7M|Vo)+wlY
z=<}lg=iU!znm<Qi_nCp2aPxrCVqHL0z_h3DR}r(-f<TLzm?OB-kC;^fC_LmhufW-U
zd1)9356InLx7IpbKOvkW@&PTt;VtLhpg1ajbP-@*`CmVxc1*rH7LJe0M~*^s{pCIP
zAhu|E+$j_>@~@FZRNayH_k{1e@=Mo2oGBks16-EeD+{=L@?U8ho+EEL7{WYx0Zmu$
z%Pq?g$pd+bqYtD7^5|@sK9rAHj^-E1yHghFk=%C?NFU1=P>Sz~eCQiA;i>$KuOTdx
zYZd|bOx~v$G!^p2y#T0`SNel{qhc0~o17H(d=#4%e$*{n6nQ@)`fZBA&k@Xa#W5Ol
z2PqawLm>@T)Xf9_uHsP)Y8i?OWI9z@3cdgivlabMLYSlIOw+_%h4cr4xv%(*rp)<@
zqFL_4+nOA{v(W5Ein}MkQlj{)D=eQVKE?uGs_@T1txPeFzOUtqxywLSp|H~(QKgvY
ziQ02TZXGOZ6y8>_)GB6nhviGfVVdB*QY>>v?Tup8YqaI9Vg|kZ-znNZ0Iptfo*MW;
zvC^S|=|{z|rD&6r^3-{>aFg=%5(u{{<&+2ArW_CehtA3)_t3H($_`5r{Z3`eP&jl|
zrr>E(?N*MYkMSPmo*dxZl-G~Ia-Z__zi{uNd`r2Q{mPIb&>c|T?1|!_(oU&@BTDBe
z2W-5QA(UM^s=Ra$QTQn5Q)7-PT?(M{Q%;OQOaV%ty@(=Ex$i8(4^q}6>!%7<cH9m?
zsM0YMfG}l#Kh(mN6Ptr9LiuDbqBy0TG8DMe%GE<5Jfrl_#5IprcE|?cobu1#m3WTM
zE4TLmTb#1sB=GUdvX-z(P|h*HCQ-SYriB-kvoWSuT~ZFfI+H3zxr##+mzA=1D6T3C
zZbNuY>5DwMDpmQ!j<9biuW~5Tlm~~vBwgu`l{VFF<>{edxueYUKrk7~A(=eBBbmy1
zchSOZW!6B@+*9^51Cgt2yB|fKQcH>Cd}VAAiU-Oy&Y&q&j{1bAJyh1x)bNoqA`PA%
zEBkIi@kE)|113+EJ@Vk9Olj{3;WOp)Tojec-#f!mm9p(}bV;?+2g?g8M~!mDdT_r`
zetM7aUn+whK>1oZdoK`gl*?Cvtxl;Q3DbAV;prfKuT(BVcYRPUIu4VKDg(_IoK&h(
z;5Msn{|uHbs=Lh*+BVgyN$AS$s$o|6-J#m12F^uwisk~YDt|12sCGG2RWsmXk80F?
zxY(--nFioK)yVM>x~mFeVdJUlIR-8csLCF};UQHw8de|1TOHh9s<Uli>8<*2Kj1#9
z6?#PBtIF&T6F=3Ie}Ox$YLY>BkZP?FegjoWk*Ec$nvQ{^5S8ON%_PHAOZ{PbQq_ZI
z&k?E~G+B*Qy_O)1QVn<p?lY>H^ihmawaS3sv#K?P@OxhM`~={!st=Sxj#vGV0h0?V
z!y3R7Rf(Q}C#gEo80(&@{eIMPR3mAgabI<E7;yQjsg9S3ra<-RTPO=v!y+IpQcVd2
zzF3tv6rLWd_A-dOL^b;fOrEN?)2Fpm#a&0B8`YPSP&lb4eg)xX^^c1X(-!p`nu%{y
zx1sxKyLvl)BzCAXufdUvdh!HN?@}M2gw}3#U|UL)xv7uP*K41;MG8FaSG#dQc&e9B
zM(&_`K@K|Vkh=IHOpd6BQrgW+z5D|F-c~z?pms<7>o2g(REIu7ElWM|N9gXUmkk0S
zN8QUAwLJCac(B}8kLn4_2kNDrQ7cf_3`Uwj^-w)ug=&#HoN_gf)Z0vm>9Kk!<r$u+
zM-2z*Q}v>`sFkTBBM{*;^}OY1XoY&;Pq3_1@4pUD)#|<~aM!5QBEj-f-RK5zuhh;_
zuzah&J0DThsq3qtd#_%z01f=0X1<~{*(Y@lme5oi*|jg>ViUVK9m>sYbL1sd;p{9D
zMzHf<!o?}J`$)Jr&CWguwli#26goJX-P;kQXW7@3&N#>Z#KCVYTSD{ZI5xQ%gcn#b
z5w!%id@^)NY~)RFUSyZh0M(JqmQ00B3j6XDq*qv%dyrmbf4Txs*V%+)@SDmu_JZyv
z8`c%NG`6@G9NuEvzQ;AZ%`T=d$6dBP&E+%L9(3)q*vh^rvf1M_$j@QdJwq**{Z@g_
zyU)74LiG7;QyRY&IM~@(<5v~3xziC_5$iJwev4VL3Jy!yr_QK7VV8u0ri|TompY$y
zqeZex_S85Ct5^>s;5F<^T6L&pZ(>7$>J?i{37*$%%}AKkvGcHms(Qz+rsV1e)`K4Z
zk1RU^QEcSgM|IIUOl62~3wI?LA#CH4<56tqvfIIK2iN^J_+2;?wZxTMunHWzxS%8y
zd$`v-V7Zq&`Y+)7xUcEnaOY-TM6sVs+>A&(x%^l}a*3-QipC~$Wy4Wi;dolKzsen>
z)N3kt-Z2Y}y}=E;3{Pp?@)saY=R8<Ayv<FW2H_p92_;c8xCJ!j%jDV}1kF7z!3DS+
zE|2p3dEC<9A-vDc+6(su+}h*76>{HnMy;5e;|0z~oC{HxaQ{7p?g{tBHo!}{iNhS=
zF5~*qo3EU+m!L5fTxJMDtm2kU0OC2<hPt(e+cFVFEqA2^x|dw%3WWcP>oEqxw_LZq
z)Ysfr8r#%!t<ItLp6k&GWS_XMOHgd&f13=;O?>`U)Hd^fOab*){!}T=rMB^kn~*y5
z8;+qBJNUd62xce0pcXD%dH)hbx|_e_2K*jApK?}id}EsI?&F0cpxMt4ae~m3SEj)4
zL4IEtYKQodG{x}ZC!GVCH-G9dguZ+;8YCR!pV2JlINx#;eFOdZIvR%t^2dk3(+S?{
z4rMUUk>3!$q&=bt<Nu+-*hzk$h$4c&`UJvA{wBRDqxghDh~f+%JRRII{JJs}XZc?i
zpe@<_t6;F?@(WU7lE<%020Wj?9FF1vzjX@SItqDPcSQP-uarajh)?bT;A4Ij4e6fn
z)7Jv{l>d4nNXz)-G$5Ywy@x_r$xrDHlPW$j0<{``B+{g+TK?Kqz+du1#-Mn`W4!}k
zQoiFe6mR+FqtUW@ehImM&ky<qjri!`SJ0-7PyEhE;GKl^yTG<d*q09OEy5lhbX$db
z<n&eBg-1y+aTebB1Lz{K_hGqHNPhv7UBaV{Fxf4n((>e9VGa%H+yuu)=-h>g6M*v&
zcK!^Ur*O^ylLJDCHvp#vhhYk&Q9?U<OGOJs*U?`wf@wAaJ|{d|h$zkr*{cw6oDigd
zE?)Qn*$GvGU~&abqEOid@QZ@_06bk1#xF!IMMyURa9PM14$G@TRxEVagg>efQ>w7?
zPjKE4Hcv$@UAXVK3esD`gV8|T6-JQ5452ASktOuj!zNpp)*YU5guiUK2D!qVnQ(Dm
zNT7^nzA*g}ObUfRo1*qmm>&vUv9Pc$ibsMkEee(hqiOu|M98KOd8v>)8^SUnb1PWN
zg|Zk2q!q$>q^4C>!XMwEPo4|yzXw~55Eukqtq@M1@RveS1w6eH(veYCy%i?xKv5_B
z-W$DEFC4A_>3gA$h6NvmE)N0tB$S&VbP^LOA-73<YDDyh#Sg=wJ0h;9JHcBlU#P(I
zcT~)!54x{7_De)@O#Cha?vINt?*QR19;H>IK=CgHiWB0S^Dqe(XSG5tM0BFbL6|s<
zW=JQ+qI7tQ5Wl85SftpMhJB~SAOW7D#2i{Njutx&hDnTgu@yo)CkDsRH}JgJBp=r)
zPCRuNMZ8#e6rGSLX7_|?lDM9xYnQ}(v?`G-uJA<dirA7qS69U)KB!$67fgo3RMAEo
z7;cI?|3EEGyzPbBE%ER*)NYHTcfkE!F}oU^8R9v*_E}<k?C(M@LrlwqGDn=T8P!}-
z`U1fFV)lIWY`*BIM$-z!x?V6T6z4<%SS0SrNBG6!l3Cz>EG|8a&`Lxz<v^Z_z3BET
z6(?B%e<qq}v9w&Q4MXukY##)&ty170DE3JX8d$nJB*iWS<sls#2>1J?8O10(rKztW
zJRn`BZ1F+q&UGLTNo6KDJR+T^^re>+YeW>@(l<vC(^1KT=DI#oBn9Iuh4%sOnB?9T
zH9zTPJUj(RnmPairDz)C2TP-TKo%l7j*f@)ret~nn>1++y<gL%@$>-Pl8$c!{<h@N
z8^s+d`yGnA(uZ{@GNjjp%aqb=D6%9aCikjr$xQ_Ao)k(M$%oRnJcLEkg%Y&>vGjci
zic+bM8lja*!L;D~OiFe9i?Uo2JHdU0^y_sLmC}n<YWTpv7Gr72pjAdOFs=RWp@-Wn
zxByAp7q`%ecDcVJ+V;!aLf&CXFW7XPz7uqvmQk+0vpfklU1qm}r0YIf#qX9*o!h<l
zKm^&tCWn2`WsZ@c=#@_k2fdF|*0|4knp*d5I~;(1tCG-y{#(o8V1TzfBm+my1>KkF
zNS~?(IVj;Y`1j4A8?yf)=!UjS!*SSlx)X=@@rTXV-%^f#L{(=v9{KnH!us~$SCIeI
z;Rep<Df-jXwf5*WIM~FT{T9V8rdeYYhnZ+2?0lH2$)NOSIxK}Sn0fgYbm5G2iv=A2
zT-eRKVYZV!POni{w(urg?_&R<;lysXKYjf6us!xbx0k&~SrIpO{|~_JW7BCk;?6q!
zJrIEhTPMMEKdamTsV6JZ?wtedcTGWakWD`Xr$<;1J!)R;{2tKxuzoaj^JRl5yLgN}
zPMzS#meb@tfIYqlfIzl%1428&R)j$p#BQGeT`>Ee)}cb!R=**NP`0h(5BLpZ%bI}n
zBs)ZoBAh))3n>xo3|ixfWJj)q@D#h|BP>s|0hCmYVizjm;tV@ZL=nxdcSY~Su*Vhy
zcb08T8v@U<jp+k*o*hRsgIG3s1%ioV`yD{o@ocawV!FTvUqC_@gX7vaC=%H#=ODer
zj;D@FW-ASdG=&YM!Te?R)-VXKu&Kk~;wo!Bf?%$(qpRWfI;-^s?gqQIKU~~o$8<xH
z#;!?0ucxzzy8wQRZI%bzZFao|EO%JbAeh``*;|xL%VPbAG@IR+4bpq;2Nx7MtZE2M
zbJ=uC^yRS$t-*GmJwFSr&u6{WAbr3tCHDpF_;lzB+4A-1(ub_24}vLT53~eJF&jbG
z{t^5BAy^)>i5s9RVGDjh%bu`3kkxdkp0d&un3l3x<hP6spv37jw%=sLRL+J_=U1>T
z`a@UAn(U}mvFQ)t{yAH_A4N6GUjk_jTTChXTK4;|5XB4jwiSWCWbe?{kXP)si*Wdw
zJzW9e8#cZbOy05fM<^WiZ0rRnKeEFP!t@iXt^(;sZdWCQPTUy!mTl!SE`obISBrhZ
zDrfHWC+J)_=}+Kya<3|3;>xW*4&5%U;24VC+)C<_J)AlNwY}WvKf&q7jixd4KJE;C
zE!{cyBEUTyoQ!Uv{oGGWP(8pMq};<n?olynhd9qmi0K&DdJYOdZuvg=J<hHE3IKo3
zyBHl5z_tAsmVsQ1h%0)6>;DQSLEJ1oSc17(lm`vrCR0i*l$#Tdn8LVQG}1ZA=^6nZ
z&N+%!!X|?ID2FtXyF}UcQ(V;~2v2i)G?I?uLMg|3hKpPb(r9irO*LY;owQ%+EH{_(
z8t1q_cr@)i_k$k-jpYg{$sfm6kAN_qo6!&O3*1B+876S0LC_^~Pbra@#AzLos9xlD
z(XNI|+|(!FPUiM(g))U((*eO;;dawX`c=*{9BkLPzgNNJIydkv{HAhg^!mKPIp4!m
zb(7Ol3NVeE+XoKQxp@@fEpE<i2yb)apTp!1H*^#n-Q{l5s&NLl<`LxpGPx;ZL7K%W
zTcgP4O2@<I9ygz61vy;xV*qoxR;y9uaaP){cb|)#3etRTDeb3tz^$hlb^&+&KLlFH
zy|cjmL(YvRN=4jI+Covx{Yj~sN8D3Nay;fDR>87_Q)wud{)DRuNA)T9RX9vbx%4J5
zE#uZCBbaC0(r9=p=Qg#5u7ZoAnL{NPngPF6+z{&7=bTeD;MH6h4M%D?iMB-7avy$%
z@C9d1MrbcN{Tx`n;=ZIe#3sHO?U^{h`)r{3$6<cLYqaSI??-E6UVJL0hQ0ZR^qxD)
zkJAG0!~cB*cwhd<;m{r91Lh+_KYkG{e;wx^(HGI5|C6SB0sPq6C<6K4=A$^lkNq9+
zApUE58iV=j^(aDk7kbb``Gd6Y#}Urg?M4~F|42)fk-UXQrl<G=zr*G<pW7OKqxfuk
z-JRhF?}5W;zRyI^#PGvuf#@uMk)G{yyhItu^ZfRHu#DwHDiC2DUqK^>c>X+%Z7%T5
z79yquehck5NaQzU1D@pIefy)l$p1DQrkD7xp)gJ6!@fb0!WYFOn9KYp25eXOq_^O{
z$}jyIme=^yv%p>FUDW83RNglVeRzXUrnl`)-j}}KY5X|a|C7#7rCklTcopSOZ}U$=
z!E%ScFc4SrF7FsN9o!lG?Db&F<fl?%B8yL>1=nnTCMDSJ@#|>uCWpV+9G1EKkF@Na
z$H&bB&3(Sxw-Dy@5pHPH1AZDcw1DqIBacGf`wA={@+sp`E8_pyjF=wtUs4{XguhLr
zs3&}YgHn%A`MQw+mh$t@fToP!Ml<hcybs-$<-CS6AQgPjL)0qy)-7OC#sAU;xaa)I
zLnx~G74-nr@a+=Ords~-Y6xHOZ543%l24^2tXKRL`li0-8+{Mq8{VraIN$RB_IIFK
z#|t`i;yeC33!<p!Lw|?zJwJCay5s}zeI59Zd^|SVV48UDC%E4z+@u+ylW@=rq??2v
zLLl5M^r0F17NLX|a<&R3yTG|kxHttY+l2%_SUL-9hNHW72wWg6T?F4!<q(=f_NRSU
zu7YhIl)HrSyWnuQpr@S{dxREV!0#2DY30F9*cAofJ|XNoSh@=#?o~sYI4VxV(P5!}
z6x<#W{w1`RuuzXScniPoLUB~sNMAS~;YZqx<SX3o29je!>SEOVgz3k?bzI==VDT6J
zrU^rU&<p7~RiJQpFk(0%+@Q_LL4pr$p9mI4&>qnc;Q)=_Lxs(bE(kD8DC>jjNx??5
z+i>C53<x8H@;(4Y3SCa4c1lRVt|m-**F_@GDB&25XU+)!<f9fX1dl{5Mkt|-<5}S?
z<)_aHyJ(hoUTF3L5ylDw7eN>&H2Dsk@xtu@2rme8PSP7RL3m2Nl_)GLgEC22L{r|2
z!oXiadP%4rh+49cdI(XZ2w9YEzAW_G08dwh6`_dfs<7lOifh8|!wBZO&^{QoRAGN(
zxVRylTMZBC!aBOuZV7`a*M3__n~i?DBXl^+;|+RO7&{QA8Nx{mJY@=>Xbg}g45v-R
z*}{gMaClG9Nf71;yWS&;T;bza5atP+Gf~_ZVhj-G3v+4C_du{*Lt6@jkYK<I1@9MV
z#6#i6pD-yBl6OK^EDWWct&ar9-wM1z9}5Yzl3OC|jfUwHVOlL{o(h*n!lqOhABBdN
z3CYc%dnUM12EJU_HyvyhLeg5asZv-)>%mn**6*l27yh84T4-|^Evyl=`@m8wTz?1n
z3!!}%SiTgZwGh4%4$_jb<F(+|2kzepH)&z$t?-_5Ty;Vsy=>nJ;lBV;FATc^-FqQo
zK7=0x11(B?6c&Ap)_)R`Mnbny>{t&MPGYnR`e~EsEQ5>9;xu}@ZV?O4z+|g9ijw5p
z#Jd6TyIstpoT#%ylxTO)4sj2y+q;U({{Ui_IB61UyG2(@gSm<Ig+S~R<Hp0UyQrp>
z22XLrLYN#7fB6pa9u%L`6+I&Q&~9NbaX#%#^%i@rL*XmB(rEpdxYHR9{lt~?&_My>
z^qZ&!iVh=f?L8r8Y2Y_RoJcQ^P;vJu2*bp=G~zoc-k=OyxcL4FxFf{dG+Brg$DKtm
zr$iN9k<+5;R|Fa*T93i<jJWtXSfa&B+UXM`vXs_2D;D)YFz3XOKmg8*i^5UFim{HX
zP{xU2FX1U(oJ_lsE{KbxQA-f_JVD%v;?+`^B#A$LhYr3du4)96OX4#>=#s^((eRrh
z<~Bm@vN&fZBD^B52u2iF#ps^snQP*|w3>Ha%pU{ysiG$(=x&IO2Y~aYn0%iyIBB8*
zzr<0ci;aT7c1twS<8)gL{tF>yh-KfPmMJ!&B1^oq6x`Y3)t&HkPwY$^t#ZT-v`CyQ
z{x%QrJn<0CT<(hx8^I)BOrvSg199CJm=uU}XkoNaT=)=fAByX{$npFYi9XMOC>Hl@
zN5GH7wUp+3EdJITz!Gud0FXWrlYPMUR6I%R9i`$#+HhAUmUsj3Otg4_v|M!Mp{o!B
zy%AxhSb849DzWEb;GT<1A3|6y#!))AMjUh>!dlU7J&j;qh(DX*@TJ(9lAf=`Zj?ZJ
zEjIZM_&4Iht<b#{E88Q&I`QaV=)`xT2MvVk#bvZ0{9defhwg*e^fcff#l*(wr%$3M
z?XBA=eNAa7C#k**0Gp&C_0VmV4%I`rO*&r*503590lH4kQqW=`c1V7Ch}1=D)Dzr0
zrE*%TbCsIVE~{PACYpTjmb}z3*(3e(1%lZt&D{<6ZW8l1xc5nIXc*@%_4^qB4`~SP
zE!i*4rwPBOwC5T89*~@AaqXaVy$9SLa!8M9A^EWM$4E$zNclS8y(As2AbU$LG|oOM
z-KG1=M@n;t3t#DL5$=yk>VCL}ep07DU~*h4q2#^4R6?Vh0I8C;8w5&58fBc2%&$-j
zl9)v(f~6aj4Gxj6enRU*CC9EjAi|`D8E|+~>hc$8!X=Lru!)d7$3Yk=)oDO;N?NiW
zo=!_mX@DCg9i~+N8L5L3q-UkA%~3li>0X2MyyWx(oUzhKT3Lycl$1A#m$t3}%LOU%
zF8U%tnjZnOL}`Sh2y96bw*Z}ZQL3c0(j_U1mR*vi%DvE~NR4~L#bxP_03fbN_j{qZ
zD*fIKfNRpCSm>@x(`g))D&^DOuNzWCI#_N>7NSm*I{gUCbZHbVeBYAlXl8g@dgqEL
z?nuAr>HBwA+CC3OhSZ2UI8%zkzBXi~ZhU}gwlpLWx_i<L`u^oee-DDgTxry5nB+-~
zXmoR5`f@Ca0%_B6gk30&E`sGl$>TQ^kEHME$4!qV51O2mND1^}E0wB4AuN-^15_RG
z07<{n$E{LY{TCcoN!oY-pG#4+Fk36_m<We2q*3m^qnbDlh9H)A(pXyBtCv>Kfc<-E
z9_@MgAf?K|`BD0b##Wysl?whgYR*!^*GbbW5w%Sk7kY>{Ym8xVutl?{IpAA012zG$
zO|y%J3EMSZ^kQ<>EX_jy?9eQ(0;h{+)jQ~RYDyhjLF1~CZlbzNV<|@zyEWaL0l!D1
zoeZ|U8sFn+ikrrZ_8jfgY%c=9U30W2OguDg>DMUxHP>kp=BfE_C0Gt<KAk}Apr(fI
z=0lnbmFUUCnkpB-k7$xZVdACv`wJA_nu#aqNja)n&<P>>XkOAc##i&D4_bIkGspp;
zpXQ1agvT|@DF^PaG0{3xfM#}ga0hD2C<T8)!&0^;NOPC+2f>=Na{&+0bPYgzLp8tB
zR*x{v6zcPnn#|tNg=>1hgJpzfLmvHF=Co#T5tLDy0D8Ti(YzlIhi5h4&^pFB&2ft9
zyygSF9%D5_GyukFDq~?8uTfyvh3bOlPIKrIG=8)!kf_;i0xn6jZVfmuYPe4TT+;OD
zfasGoV<fmw(dfwEWz8tevmB}`n$2MVUe!G4i{hH5AOyvA%@bOqPSsRWzWIh`=LZ09
zYHAw8Q<^59R(R4ivnk<sOEX{^*luflPNHY-X#CqErn?%?KEP#YR#VO>Q!_LIx-5;?
zMp$NR25-SdyQld#04$Ci&0y-w`<f240-Ue;hwiHfn#eFXEYSEWAuQB9q7BRsHKt?~
zk2D|uMre;UUp3@rH3zSNtxEHB4f^T1=EXI*uh#rQAFLY9o?NihYL3z>=nIV(Z8&+U
zSxZZluQXfB(1))bn#i_j#T$)`vPEw-d(8mWX?~{6$~%o_HEQ*mXqq>@*EnM{s_KJg
z6aC8Jqh`bd=ss!YyoLLX+UE3nbJDJHf~QT|wX`(8S?fos(k<FGjZtjXPNQ_mHf^`b
zD7I@A^ty1?V#^WmJG2JcY2u=7_ZOtD+KVkfvrGG+7f5$&w`QaF_Gqp1V6s=ck)CWf
z?U>=v?bGth&?a|n5N!?f(60U-q3zfHOGyP!?K&1@2efH@;P9Zf8SSPzr0upC!oymz
z0DvRf`Hm)_@zQ!x&w6W}X_$XhJBfZ3<)d9a3vv5uedz}q$FxaG)cmvuLcw-in@yuZ
zf31zuVFB91-vSV*Egz1sgSF-K+=gh|`=A!8onMHU!nEz0!sMh@V+9~wTTa>O2<@UH
z^!!C?$2V+G(*6*Ork&QFZHXwNv?18sjJ<ma4C0Q~UU-HmVzkp}OnO%Pp&Rh$w42+a
zc3xXM8_~yVV<;&Qr=6>W-+1lZ5Wp{JmGt#Y(DtM3R-(2CZKh1pdQ%qSqBegZ{W9s2
z_PbIjlePB}5owAx)*mrl)~4(R{))CV0H#;9Q}3g_*R&rP=&oz$2cm_k+CjYlxS`Fa
z8~LWzX%d8KS}SeBOxM2l0Ou`jXA1(ot$ofSraRgTCt-P48@LvMW@w$imgD)$)FwMa
znx(xo3of#?F*g9br*)#_K#sO0jn?zDOE(~j`&w%>*z&bjS{!_!wc&>vssimk+DlWY
z{k1EE54Gi#<t@_Ie2ZomYn5FQ%p<Lu96r|izCo=-`zOtApK2G-`iG-b`%hy?%d~H4
ztK>87_1B;&*ACJGQK5~dghQov6{RGrv{}u;{ao9u6Y$mAxouFZ(H^3nsnz;^0`8S|
z3w?E8Yv<C}=#91}54yM7(_0aCopvd0A9$xdyB8f>ue~-FVZV21WnTjLK|6RiNIz;%
z%|h!xX<r4Q*r*GoZriMDNk8q{qH9DW#jQG98vJh4Wy?@(*V$b_<E(Q%43-_bc*<(K
z=<0q&lXmJP4NP2hH!8rgOSkDHOm^%3q>-tc?!iHr?9(|q#Q^WFQ>;Kx9=axlaIs(K
z-x$sI)TQ2r@PMwKMtlc#jekHChjayjC=TngK0<dyXLt`bFWptjJ9z5~DSL5LH@_SX
zeRNK=O~Y6Bn6}Iw)9t6e@Y9JjBt5QsN?VNmb=@3vw*=^Ns$mnTo6rt6Cv?M(0vM!A
z*$%c~UGZR;hUhNP9=K55b?Trn-J5UV_oVKQ7fix+EC+`Xy3)5`iPU|!7cNfel0G2N
z)4EBtJQAgAgrC2w&ghEitrxA^O9Q?bo!o<-zq7igbbp-F4fKHf^SWNsK^m(o9EZ^2
zKF5@xdqyvlMBT#o;7-y_rzy`x-G6_eb_ux}=#q6EyMiS}H*`C=FY79X!P6Dp3>!RL
z)9suMvg^85oe)K;u06dwZ|E}1DcyNf*CzzPG~G{QVR}m!@(pUYbsKk}6Yl8L?Et*1
zQ_`;*Gj!kn15cT{&9pJ+p6*sO0?pAS_d*o8x?I}cm#1@T4#0ign5nSL*A)*(cRkPz
zYzKIO?rAR+g}PU??)6ZYG?SjcBHdwH9xK*m#{%(4cNo9lS3TC9ECY9m&UG|QpXgZn
z9z4|@+ym}Xoe!-Mmg%n2GVwFr8oGq#y1o@?Q-!X)5#W_N=LaaNbSJQIsCusZz7&9J
zT^mY6)acgKAg0&4aS8<Ec%xfP`LMUTRppS@>CSY7%{yIKGqBa`)>8)gz3wJ$lKP-K
zOo^V4x?{AU@<}(702}qQy%3s{zOWT^oAi;%&~4WLRRG);z2Y&1+w}o7YjxHy#_kK%
z4*d^*qHxhi(dcuhLqD`0A-d|D#37np`j}^s?$$r0bi^KgD1D6g=_|(}7<YZ(EC@aH
zhD<bOzy5;)LQnk{l<_{GKTex#4(c`SU~)*mhaSqq`r}i;c|^}AK<A}*rj1SB`YQUF
zp|5^AtuGwYJ0|gv`su5JfH<z-{1i2R{efr{0s25au0f!_JEad#=sU~+Fi4-^3x~n_
z+fRWH(I29H)}i{BuhEEbeOeAIBlHgXQEa5XdJIfX>FX)2c3OX~BP^rzZdj&NozdT<
zg_LN0@h_7QaEw028>VOV*LuU|oc=7mX3y(y(I(PZeNWnB6Q>s*fjeIRaV%m=)JM?D
zT$28JB0Bh@UO}s-m-Oz7QA^h6sNg<DKXBh<vtuFc3QyI4OY@x@`rCU!byGi&o~$(e
zv&Rso>vz%E`IdfMGQhX>_h^~xj(+MyxVftjrm1#@enJ{7Gxd*OK$xZ9ehk6p=+kBZ
zkgIQ!36ng%;R}R*UtiZ1@O-`eZ+Lj1KjNVEwE}%B6%d8`90~1us6R<_)*}5kdiX8Y
zWA29AUN56xL_X0c)A#wQ{!t2WrTQh804URsYz^Hr{fJ0#m+SA)N@s<>DeZ8n)HgqY
zT9y8JOZ32V{oD5tR_kBU?uZ)wLM`PYYW1BTAnq6XoAbf_QlCMisW<ur8)AB^52E>5
zoj!`T<h;|LI0d$P{VpYh@AchNQ2U_YK;Q0<`dh=`;*;Jt1hq|uiUfGtZ1DaECR+?G
z$o*EsI{F}QGqj-T`*wqe3*R00y<zZED0diKyQ6S1Tx$&FPD9xY1mkK*Pls@qVVM%O
zy@nL`q$y^H8*LNtFyxMhqy2_|r^3S1aFEu`4;bQ3BeH{r$RyYwGCW=de}@e(jv|&L
z2EQzr95r07M^k(ZIkfWTYY3)9$}vOFBIx`KR=VWJ4d2kBg1_M@^=p8kl!jY@hE4at
zdBQN;K^p;r3_%s>pJ2mD%1nnDJkCLQ(!f1{Fx>DpeG4KCzq)}t(y)*|h^GwCXjS~Q
zVbn~pMH%io5Yrih*D+j)vxas%pgU&>qHN)LgJCjQVh!&L0FN`c+<-9N;F^Kj1;d%=
zH0?<+WYLH+(GX2Lagq$;Toe}#e<@*e$?%%G`Le<58_--aOix8|)i8l3ZPyG*-Qe)L
zf%^|ds-cTBbT<rlXf^Mq;jiWhEzNM07T3}Z?P>YqmLa4+gtrY7X=h4?VM7w_z{@m@
zJqZ_ChSg>0lWfC+R;b-GIMd#@9K#^WjOQ9EDgB&h=)V(e_YH?;!6e^cnFzoGLzOE?
z3k*gZTof77bqJ=|&~rZEj|_`xn)TR_MxVYCgC}j{equOd0N|-%Hs0(GRjDDIKA~lX
zk@b*P7*<U{msA@5qiIu>p_aC<KQ~<I1e0pRs!gcX7*>x4O|9V{4SMZ`!FM+RFAW|v
z5q)JyrA6x3hHJFh?u{We37qc?lPM!!Zx}EaJ@ek+yBW9-hGG9e=lEzCOQW|>hBvfm
zwbAH#6*Nvp4W%wO8N=zqZZ?KaL7TQ1TS(AtH6ES{%N@q_pMZBUex$_2PUA;PJG&Z(
z(S5bcs9pj1ZsSa9sGIQ`P4xE}TTuGf-RRO8CLYE`&k@Cbhf!FL($iQS4Cw*mpMAl0
z&^UqqI>RC3`!2vAHfnx?-y_C5x6q|tMj6deyp8O1I6P|H^eaO1F%EM@&DXevcK01K
zY6`*WXB;pdEXR#`3S2^eW3M}?1sLDb=OWOUJP?*AjE=d9D1(e^X<JdSvEnL#A;$J;
zAPqIv(RxCdF-{NRN#k2u@(4G6brgUIV_(`u5NUk)4MIC*jHaylY2&x_L5woG%mVz3
z(N#jA(Z<eNz+;TnLjgEz^eRG=&KW~GLU-Oc(cy`>V~yuGquFuBI}1_78<SYrTrh^x
zTq?m>N5hyz;~Lskm}E?$<myG^$La8N$@p>@Op=Y4L%^M4yhf9t%f<y-2(K7z--G(9
zaYJv^t{JV%L4Do0qXpop#*TjjaKpIsD&3bijdST`l4e}yi}t1)uZ#oDE#pBaxVUXB
z4Fckhv6CLXch@M;Bq+o9`&8&MjVs=w$TFUwd}y}u`C;Jh867qVbBrsF0+(yNd=|Al
zV;sGN?i-~E@SAV!L7(LZ#@%ue&tHM@%R1N;8W$dc`-jGLw-HQ{anC5&6dR>{03R72
zkA}%(qq-WTCC170d3|CWNPwrt-)INkGvjwZ!Lr;qn0``HVcb}Pm@1817NV#!K5Poz
zbK~8iD5{O7ShTvvI0HE*hpN_?M?=XMMlS={UK%_4z{M-$_ZQ&swb4?C+8bjZ+D81=
zIQ|4`b;gx6ICy6qy$@{l#uN0Bes8SsgUJV@g4PT^8e?Se`^mVp9PQm`8luIub21&K
zWc?=7b@~OuW>W_qI>#2%S=xoO)s#ZRy=^9$9Lnvc-jpVEHrWe6v%}Pt-b^m0%lCob
zY04gfC|pfh9bvi4bdz>V>^3D*N@0&_#0yyNH5E{=yP2-_L!kRio9QoCxSLw{gwVsJ
z`yM9yP4O22_jH(!6X^kyAHCiWntrBi+94B5v$n&g$CNxjV)|J?gkGkV^oH>^jisfX
zqo$#>@yy30t3%;ya;F!~G1D^I{o`kP<%ZgE)3?-Kf0ObU-~p!5OVQ1Nrhj};J7GFB
z8nqyk<6d*%gH4`;QG}TK(@)((O}V$>BFwZs8nu(A*0i`7Zfdp#Y!Rj%AE1jgZKV!A
zWztMVpr=heXaO+FWL|~7IAgk73+`ysyjCb;OgGa2KWp0S1rO&;nT=69Z))cac&sVf
zQ3ZUQX(w&lj5l@AfaZd!odLiElko$JL{m4~QlDgMp8`a(>DXfcQcP`VtKDUjeheI5
zF){anyJ{NtHA1^)a?rQ@x{0SZTB^w*fcl1M%RlgY(=?NEq-iE*J*d-7zqN3H^p>eC
z8P(gSzPZ5PF(ust_gzyJO_eiD>EXa<no{ZZ$}%0Lw_diXpap98Og~SCNscMH7ff<Z
z-_Zae&t&+3+I>^s97K_CvW^1T0~1HfRRyM`O2k`eavqP`LsP=v_+tsGB2&#oREtd<
zC0!nwHrarGZ2E?BASI^2>G1T#G=*NlPfbnRfwa^#ls2H0nc`?O@-x%=vA~s^?6f<t
z!c<S27b;C22T`js{ayph=cX<Zh@#pws5_`@Of|GTU2E!$pV7Ksn$g^GwLfg%noiQb
z+B#Dw`nbL`^=}8;deayhmcKU*I)M;Bm?nP%laHqMz5skOwWbXBM)Tr3h}6l<s^Myr
z`C}Xao6U_qVY0<6oda&GdDUW=Y%`bcg2{ICA)0(So6kic{2k_bj-H@#F~6tH8#~SK
zv*F&=TtXSFUFOl0@ZN3i=nI-X=6}YZ*lV6ogF82~;vCrancGi*iM#nf+JNR^u6+mH
zezW&{6rSc=Q_&d*%!Tw~J!lpe!}5^%zz+16mpPB#bKd3&%^Xl3HP_L7;$zO*jhe6d
z2zIBbj+uWChS1OaTP?Vcn`ixt2>s29b%-Ls94&%7(EP=Bh~k8K6J-&C%;{giZ?IWQ
zi?Jc*PBaP#HRsZ{+%WS9nk}9*x7`owaC6iJ)FRAtAJZCkq}fERKV?p%W}h~Hm=70G
z<{|wM;u-S^8ooxGhtLXDjCoKbf;nq`NIi4T+`$FKd9%JNEMv_NjnKuJ@83WR<IS%)
z6c^0N8WaiU-yfhzG%uwU=_K>mUr<~$FaAXD;7jJ-cDP73AEReH#avGtfG?Zxhark9
zX3w4o?W#Gx5fInRYyEJ2uA9%kMlIER%N@8I=2u71rkm!x<Its<*V5W*y4nACu-r1Y
zUIdog=9%Fr?wE5ZPjc71i9UQ8=Cv8HbYz-qTcK%LX6sdSeztjkDwOxk)kUb~nETS4
zCD%NUrrdevpJyVN`{rZxTk3rCV4A@^Ft4J!tias=DBKsC6KVAR&|GSO`yzA1Q|OA#
z!W9&c%<+K;^s%{$@<}D;HMF+##9=;2+e@CBs}c}fsrk1%AT2Y0u@f$ynG0zUQf}ty
z=V}#ZhF0P$%@vett1>UBfaP;@I&I6XHV>}=ca3={Ek)Ow!|9fPZ5}laEqh~bJq+--
z=0mieUuPb79=dntR?lErZ+2Yv0NZ<WC)#QE!JO9-wU1^m+F||4TtT1Hjh1OSXpEEP
z_a&%pvSe)s&1TC&H`KOR_R?%_t7T6);M*)8cLKiMB32_9XG_!sG<%0-3T=&Wv247C
zcz0S_U4hQka))+7?6TB0{K1~xmVY0hy2tVr?ReO08AidlS<-0fWuN67eR|w2?vxJm
zu;>p%x8G8o0r#GkD0)T?Sn4u?J7`%y4W15Jk|}?7*s_BXeMc-CXjJKCVVi)=+fqPZ
zuA`PdXJO)FIh;%1Uth~B7buTehWdle&*DiB$#F|Lz2^Nb|I+(8z%sEfYJrwz>99Ou
z`8gQEAj=OlZVt9wY79>y7B~8?gjz<^LRXk2<wvlbwERSq$#6@nCnzE;gXu~}TJF;m
zbIKw()AM)Q;;e$-D9fTrke;!GF))p`bZCu+##lPhfZ?nqB^hkzEE{^j<h<oTH?$(w
zGVB+`6lXa=KhBT0Fkb?2!7^?k;0YFvOcE{q;sHpq*gGM#i<Yt#&|R|Z2nQh9a?BNf
zE>o3aDYt;;vZdw-5LYZ}>cp#-nbTo&%@RY&?dz6l0k{UKmc2fR;)bPN2hiNK1o{Aw
zX4ye0@^p(gO`UF8+D$^w+_vQVfb)*U|7!^ET8`2(QijEOK7^T;M&U5Yvb0b@=g6_t
zxx-Vg<&Vqgggnav2?5`?49$fy-=c7V`v;bvXFynB8BDW>Ld$i!uO3=%(X_0{vW0e+
z6<bQzAf`u_7nIj|Y%$PJD@!b0`@qu^i-|_cPc5@9Lsx21=YhJ+@?ju!&m5Lpv~Q{0
zGSL+_6&7s_fR&b<AHh~-5opHw+_H%NR8_UbDF}!fODrvH*IK@&+4Bp_aRzKJEw{b{
z%PY&6#(=-J42%N&jir?zB7AG<LcedSvvmIvWbZ8F={r<!IYkN8_ZG)OT9^M|=|H#j
zN6U}YicgkNG*Q@SeQHO|$r>>X?cHSkZ#5ilwkoY~xW(F>ru$p1za_%&HtPZop0-=%
z)Cgzmq^IECVO5A=ak2hDYc)Hq|9K&LS8E>4tan)ltb*lktHMF4#XZ)4D1Wlodh#6#
zH*2TMVB2TCLJP(2*37jq@vxqxY{PzQ3jL8fPwT*k;67m86ASkTtv{YX?U1ztCbg==
z)+rBRa>QCezm4;<ntH*LxAh--%O17P+5rzf)=rd0^R@mGP0!yk>$fyZ^Rpgp$jw<h
ze}Ij@^;g;%A7EYl3Pqq*)*UWRSYLkxX^?f}al{mC&8LrQh;?own1ovIe}h_>bw&#`
z^rSU&B{;*a`-v>V`rRA=BCQK)4u8rjOMuB~YnvaKpYh;XJB31e#yYMgOrxzQX<Qa#
z{qhxT&RSzApB!ubg%bU7)&iQw##?vfLU+OXkzPp&))!h7iPjEu(UPoPX%v3Z`aan`
zWNu?e6WT(2#p(!$`>WQPOqg7=W|tw*>(=WnP)oIT+Jrv1VI4tV%A3~J(@;yZ#!W!<
z>DKRJVR_5C>?m4&+uCI*g1BQ1`Ww2t)<v}WHp5!e2>vpyGuA+tWnD~r0kf_CcYwQR
zRgW$KTaGoCetnc{9e)^zJZoE;R^7KY-3eX3^_vR_?SXZm2V4|bZ?^=n&}vKt%|okh
z7CNTLS}@1m<<G{Bts78#V!cgc+o#rXGz~1ZuKER>W!7tpQF~^+N7KM^Yk%6MSYd4;
zqNuc*X%k?T^-u=Fes0a6KP6UemA{0)8mqDlfLiOi#^{O{)|ND>due^20nS&}CiF&l
zZSC3t;l8oz9Q1K`YrRB!tm~`=6yZDTb^29jz11@VF5X+`TEP9mdYh70AFcm-!sL^6
zGA+k!wDGH;bF%$71}vLw`=7)8X4^j&)VA0>b<l0KU86z6He2X40JhuCB*2lg%{v?J
zci0kVJ5Y78Jw1(pciKA8o(NZ4*O>tBvIQ<dvD+3w6PZ1>a!Qo$we8Lax0`J^?NHrk
zE4l=oyUk3KNe|mZ`ugs-?I?!O)8<x<+5y|eF7R;BHivd#9<tq|ADnsF-uj>s-nIxM
zZFf3q^XLJDk8N!gBK5UhpvUi+Z2;|)^|L8y|HE<HW!k{(Z!^)GJHRFoX`pSrKWI+a
zBGteJ+1fjyyMt}DQ$QACbJGGIYI|@G4#R9CIdtAhTc2ep!fhL9**3z~`<4u!ib&g4
zGiXlPZqJ2_)3y?Nbw=6BJP`01+mAa?MBDbq0}*4}o(=q2+a)zTowIeMzcF{-R!9Sq
zSldyWL&w>s(&9?IEq5<WF4z_{2X%riM2=db?PvP=Q<BYT0g8*Z-QUBJ<B}~c42?;)
z_1OSmitSMf*e=`7QwIBr?fXISd(}2Q3c72yj6JAbw>g%BE!B3IvgbE!_pTxAo3`%3
zz@^!mA4P=ewx73x`<6{L9hSFkYX>5VJGNc)M=kE!%D14qGHm%R;33mt>vagqESq~e
z5ZSgn-C%Ri=D!~{IkuZ|aF}aLrC$r?+1^zniu<-NXlq}-?K%AwfCsiv+WuN#n-~E1
zg|>|&P<v?8(|onarg{dlVw>j$czR@85edL!+d6s^mDqf5LifbxX!ASDr?#-`P?p-Z
zPJoLtn?(Z`&upKn04%rFP&Tu|7M=`Xr7g4vJXP7EPeAwFX5WfhwQa{E^hJ$r#SK{2
z+U^WMyf17mc>rG8e*J*%eq}3Epm=Q?pn!)rwq_#`;al53j-TMS&UTgd1H7|2=!bUo
zwt8As`DknM8)~0yhiT1mqrFKpxNx#3odJH6J%RS2ZMF}fN&6N%CO&x7?CzB2+Gd}l
z0_S%7+@%mY+mmSdXNUd5JOEtm_Eebcw6Cg#KUcd)F>QC+W!KnYv)jI#a!PybduUB}
zuU$@CFWv0#DC@P)9z=gL)7`$1h8Z4q?g(o8?GI>b>S^E0q1gxQ^Jz)rp#3t92oBkU
z=|>!g?ODyx>?8IJdZBvRTZ!QGwqK(C7Dw$rG^QVn`q+yKVd`s_jRNqP{n|Cq_}SZ)
z!_#rQn)Y7#+XpT~5n#X99wveI^8vu0uy5^#BFO$>9N@ur)(k+1U0jKnLhYUDtrcef
zg@x{<y*16B!tKjw>>XjR7Z6jVy(xCMI#j3Z3;qJ|wEd|sq)~Qv`U_KM>_>VcifDTg
zZJ&s-ccGWiS$kXhZk@BI{{y!3_DP@MDb~JvBx-T?2ZvF_+he~)alt;3cEcsu&(icD
z(e6#Tz9jqi^tU`N+ATB-yJTN^3lTb!?Ji5;BE{}TW9iHG<2%v9EA~>F6JE8?q1CHv
z_KlrEbKP#tf%{bZ={*qMuy=U`PdDxD{lJ!Hcc=EI+rOvL(JlKg=V5Z&KF$rbJN6YU
zba(At-lMxR>`niHF4G<o09=;4ZAlx)_nt7jZ%@1n`h2^GKdc|v`%Zz+hxWT+@KR(y
zL4O~n*zUX@x<~dkb)a}`Ut9!SiJi$uuRgJ_pqJBA`)=B#S8A`i4_%r4fE+%b*_S><
zt=!&q4t!SF7cNJw(w@E#ZLG4_IQjzr+}`IQxU22#blB9`Te(A6Yd6gS=?nX73jL+s
zkJchz+4Xd5yta=FL-EFb!H8hq+N)?Gx6Zz~7{xpLbUk$S_9g$1qw9{#vijmJwPl(k
zefQpbVLMH&%q(+cX*n8NHZ<G*s+S>q@1;yxG8GU7L=aSl$WjoLy<{pPBFOlCPk)`y
zx%Zs!Irs8D_qq3+b06pwJhgmrAjtIcK@S+5S$;AcBD2f!gT`~k$T(mHs2#(dLa6o(
z1%33wf$<M*-;Xf7rlIJ_xI%A9Cq{53hUUyD2!d-aj1BwI=gJuK#$enS6JJBYow4#S
zfO;^Vr03a_v0DX8UW^ucOL{X7Jr4^$jAeg-_%f#GvG!x^i>8pRKjX=HKnq|@P^m~D
zBW(w`AjUq5kOwoq=mls9<2(mwp^OJqWfaDU>;PyuBZZCzM;SZm-q<llHyv{#7!Fy$
zj%3(T_C1PGI0-JAp*?`U7{;=nVLp}-)Cmj685#sMt#jfSPLx88XRNoyTqH1@uK+EP
zkxrvXV#FQ<Il+jhQo3Zu@Q;v8VR-BVb}B<nVdOMM0@W;~Gj4B#_ZbWeUEny$V0?+j
zQ;gn+z|3UKd<B2A7+-l|4zn4e7GR!cyj=-(YYro{9-U_xuUCUT%Q)1A&RoWZ5|BKG
z<SrWX8FqBz@*Lw*E<g(yfdjB~o-tnupDr*WSWqu!D9hn?3B&s%h+Jf3RzTzuL+cG^
zE;FjB6sMH&2|d<jj7};HC}(7rL$bok=yQgPR~RR{F_)E$tyCj<m66*5jVi`MN;p+B
zUZ)#dHH>Ek@Tr#3RtdXxjGvwdxyGoa$iQ_5*AX7pGZZcmX<!6h0QL<Ab3ODL84^0n
zH!+y)P`Js+`EQrVSWN3dGsF4|?O0kEzth30m9gn8MB5mV89-}i3~a~fI~eYiFzRGn
zpnA0~#{PFOv~Gq29g}((R?4^cGS+Vdxy@ivdasXRxB$}6I7k`N0mhfzAcKtLr65C$
zb<{V^P&$FT!-(@Y{k+5)H4fvWj9rxgxzG4z5+02)La5;J0mJcS^o=ukl`#I0;h7KP
z6O2j~=4FyGKN^yc7>|kY7novvriRngjL$9LW*AHgOU^P(>(OY-wBTes$Bwy|s#WZn
zqhDio9hmlXIra!M*Gg|}N2Xy7h!Znp02<EBMYI`kVZPf3cU_qa>16E2e4WY?+?kus
zLd1jl`&a1mWd2IQTrXyS4bZ%qy^De3!#w{A9Q9>BPZc<R%-458#GlFi2V4NNk4k<5
znF}eO7R0pAr+sKJ^KXiggfM@zg{PrRH+px3G3UJw#c*cF58#e6zuo|HjCqoxZ4u1v
z3QS2P^YvrkqL@oRKwmU7nF2P)nbWie$1$I!ZF@X(LoB!i=FUL4oyZ)d6nPSp!Gbd<
znBSS{<3Y*H_B?c^Fx}X2DwX*;ZRpaNZ+d}CXR7`MOa_y&9j={Zrc!SG6f=h$&18N`
zNs%n(ReF(RGu^v@a+(>k4~;p@50r4`3{%wta+aA!IgwoEibjCtF$H^olFxhsIT8QW
zzr1L*mB6b)X8H}xLJ{-p0*vhf^K+WFV&;Mwa3#!b?ij{JW-A3LFEKaK;r%i*WFt^Z
znK32c%9wWH054}YJ`S#e`3@~iSD0gZkV@vF3XJJ0vo8?}Rm|_zfUah~N#B^NVg75q
zht67N7^Rl#m>XY$iEGRZisD{pzC}-3JyUfJiVe&q^y<68ocu2%#(aVzwN1>%S3zzv
zyTbu`i&=65q?uVlThA8ea>^{VGLxvRuZ_8m5A}9tKq?wLnC|yswv*X8_yTAb^HC@)
zbu&jc`S1RfY4xLWrhevt1d}<y6wsSvkl91qts&-qI@%61-#!PCJNP4lyUVP22L6sP
zpQab(J!U(d?nappm%;9RW*C)sj4^X4o%n!RNQc95<~Q|Fc*sor5ZnZ_+5;$)%(b5I
z@DcO9|GsB1#f)==%rvu@(yuej3OkseWzIN&*s}H{LBo#aRse(ctc|o5IIvdIbx|i)
z9>o)#S=p25b76hq0|i&s(OdX^xUqu%1eiN(Hw8dESVM0>&y&?jXGJg8Rw{}1W^H<n
zwue5f)$`%7FH75kPCwRWI{x~zPQ4E<fYlfbzXMq=Di{o61uXzfFiSu`$PiY(3)Dkd
zpV7slFjkcs&V;j4K7zrctl&Q(a*VY!7bJppoT@e>S;G_%k79Yg0flImZj$b^$FN@7
z0gYHzcMtTBv$jw@Q5@?etx)kS8LbTothfSbB(hG?#yN@gSv;IM!3v?IN-}HLcOWUO
zRdhs7W&J|4p2q6^2YTtOi&UJF!3r+GSWdDEXp?!06;T3`$(l)_?O_(Hv=^e;tRGwe
zbDHHyF~c0zItu!oVKH8Y!)IAj9q=%hRZk!J$zv5zJTjlPaSV;;SekaA6|kP7Kg@a7
zi?qosWQ|RLD`Lfb1iKeluhLpp%vw+Bu@Y7Q9g#1xY##%d^%CnS<zz0ie%uF`QkIBz
zKxM4I-h@m!tB~GJ6|8<r1YBX|9Ry4ztB&q2TxHGWK(C6m%MAvrSxI!{tYPhY4<fZJ
z3B9oDSZk@?@)|3VK0I-q6-d)u&$2%Zkp`CIYv{XSWu;KezL6z0VDwF_AL&SPlO>UX
zyT!5_gQaFxv=ZZOVGYrZ(pJ{5w6||#eMq0wXlK!<%I9>jF6D#kWG!3+ur5~8eV}x+
z1ec(9o3(E%8v9u5>_GZi4R_Hvz$$13${@?SYAxItVkK-u=P)akqE~lVpU#EMT~_{9
z%+LsH>Pv9<SR2!!G0GaQgUEeW>nHGVjMX*(^AA|#bl+{9<#`q&4_RA6V19!2GkvmR
zlJ!3dxjbSed;pOt)&ffKPP16FnV(^~TbE;=XIW#8K(l2}_JY{4ovy<tdv=&3#^k_W
zxeBfwVe6j;wj+D}EEJsBXQ*V$nH~5UL|oX7mqA?F)9=Ed8#|8P67KBWBXHY;y=yhV
zJlRWYq2R^l(h=F4{UR+;KJ2nyE4=Y#A8v(je(cxs(CW|rpcZHW>}4D{6UaV5o6#V)
zy#jr~?5niv4q<PnRV$ROrnFobyTTu?g|i=bfon(EysfZ%jQzw;Ku54&$inC&+3(Up
zE{YxX3`C;YJu~QwVV4^zk{-)0O@yW6?DaAz#<BTZ!Ns#1o&$CQ`#!BOiR_A9P)uTX
zUw{`U*yk!?KAAmE@5mJPpLAg$mCbq<LrY_))q+cB8|jFg!Ooz3+DW#UmXuR$6&;Z?
z*(nb}ve>)-3y);8F9pHUY4$UVU@3>)R{_y8?428-c$V!}4VYZ^HQLkWvENyW!Q``b
zlruZWex7op1?+<~-t+9{Rp={Z@1u3Dh+Re{Bp2B0<nXtcE&3ddCG6$j0PG@rjIM56
zV!uJpmi00_yA=+Xvo|-RwSwL7D?qQXE9iYv$u6WDGgsNQ6#1!QD=WZNvqP!oq=qed
z6_T~=Zv&xM$6iUr0oT~Kd*H=&b|O8#^=wanm}p>!Q)TB3wo@yH)X3J;7O{!FvjBZJ
zP3(tJ(7453N2k(ewl_T%E$oubFwx51M)B=7_8{$P+u0p#jH!dY(x3moCDt2j!1S<_
zC{@?XR?s+av!^L>-^c#06!!YryQoTVfSvdPv<KN^%i-V<yM@A_!)%*3(RYXa87+u+
z*?Rh~86)gJ9tXL{z8D3RQFf#d7Vfi476ELGz4<3tc)-@qhr&2J*18Qc580cZ1=<9A
zbq8c7*|>3vCyhPu2ryIZ9VU!(n*H<Jusg#(a2;fpz2AaHTTZPb6zn)&F;KAQT%wW@
z2hL#%3?Je6dcm$E$EO4$PMo$NC^&Pt7D&2qp7()SSI&-)>8RtzsmVgCJEx4|_#T|?
zlos~nd`z!$FOL32G<tJN3PF50aTMeC<+#`b)Q_`(PK5p(->+adfRii1WCwCiM8bR!
zXY?G@gE=4H0vEzLh^@e!P|nZ((SI+o7EVF_80Q-*$%)_`q=!C|^Wi3tC{E4<CN!GU
zNP)N*jxGh}VmU9T!K34xM^yhE$H|ICUp%L0JNgnh{|G=5IcsTOoW%K!gT54wI~9JU
za_T4nl*ZXi!IX4Pc^^myr_K5VI!|&e6%ake+4vR)mdRn=fqoWe{}XU6o8#aK#nT)|
z+CJrQTIe69oZ&RkP|kARx&dc$Ip@EDNFK*ogg<0H$Nwi_p5v@}2`B}eJCuqz&(VDY
zy+V#B?NN$2Hf?~uz>$AU3E*PR>)v2XH~~%QyvSMo1-MI`<yxR!=CJ4^q@^4c-Cil<
zEboV<a*mRM%@v%NeuarEoR2f1P|1lp2TNBu|5O08ieqkqUNz?#T9#@!i64U0a?V{x
zV;$!iO4?uJJh7N6FRpXA7ob?rxkDckY2bYHJ?!4#C_P}Xk+b|Z3^sAr(Lw(v=c_ls
z-Qtv*(AUgitb=3=CyuW6wsMYb1!?1qJO!|J&XW{0?%){b!^2Ka+8<Ep;;h*XyWO0@
z4e+;z^H~yoN4=NBm;=Sz9CzAe^l?6<U}!(*@@ZHa;QZVS(Lv5)H|P&>o}Gq=!<@rf
zaCbOoD1CO9lVJom!kLqXVc+A7uY<xUXDwwG?sH~7hsYRbCoMS-I5j>nG|utH8ad}7
zXTu@Pp>=}uCf(_p<P84~(MO!<PH<Bk3zecybH)oXiWyGQ8R*Y)(kS0x%jMnxvEx?J
zj?|vJ<`?+nz>N=r$Pw;NIutu{&$2OWC+=}t)1A434InPug|r&Fa#>}t;KrSdhq}9!
z`w6Y|UfjY?jKZ7SF^*0j?n@qk@#XGQLeY=wO?xAMZWINy0=SXRPzdB&dO?D?AMFK9
zFn5$rSRvf~doaRKuA2g53FG?3pf8+TwijSWxjf2jALIHzgh&K8YY(_cu62weT2b6U
z3PVP7U)=%47_Mw1xLEGJ94H>=4${Fnj?1JXnt1L-+D9aC`?}DV$gQAAauRoTJ<v{Y
zBkACr%pLy*Zl`d2Jb{wRWevf#G_HCn{7vURb_NO=TyYKhPI5D>=Ky+&>rRhhCU<Te
z^s~6G-oVc0UZ!R0G&kf!n9t$v)C2Skca(nCXSs{11}2y5)C251ZU8mrbH{>V;v6@C
z@(l%C&Ihn`p6fXX^+IkC{pO0eZFF9_z&+XqQq0}(9vxvzxQ$X+y2#y0rD>PAtvQ(I
z%iMu)0b0t<Jp!(bJ8TaR%ei`IC{%E@zks{KHOk>=C3p8rXuQf@KpC$p?oW--tLEAh
zSHt}-80xj$#ZGXvj@w3+0N1!*JqwZR+%q50WsrLATw1moxcW~ZbA$T>g`*m|ANFFr
zP22-?WBn%g^1nd4#T9t~t(m(%5+W^J?hbIRT;@6qyN&zWL#VfNgB5VCgZn+5fIGR@
zTA<#={qt>D=;lVGL8OO!)dc8XZj3WshP=(aLI(S|8P7nbpL<0DnE~$eJJ2}D-9c~Z
zA?`#I{JzWmBpHn(-0T0n)3`s<%#L#JJ_6c(u6;N9#<<-vP=CO^PBmfU+|5+Q^^m)f
z!kZIZ8SNn_x&P4K^$|CI6YN>1xN~WPIL)m+1QRpd2CTYsX1PmOLdKT&kOFmfJT84s
z$e!m&mE8_JmpZ^4;eAR$eMjDP`d*n6&w+|&oOwIwDR$x6P?*@2*VKwWH{Jt^!@Bbh
zP^{a7_cmQO_T+s|I~Ff1?<2a{=FOX-`SRgKQ^3rZw}y6>emrj~ruOFry$Q4c-aE9h
z4CHZXp$X#sQ4dSOybMaDhVX{8=nLglP>4T_cYG9j;k@VQ(LTz{rXd~U^|C=CcqZC2
zNAj|sMPC%pdi)Kr(LD89bjI))G^SYIuT&#-oOhJ!5#o3m^kR?aF=^RK;C)Le^+et^
z8dDN)qzsOp;O*ZI50iO;bf!t+O$~#j@(L-Cn#S8iKZtZ*9L4=Jcys85ev-G(0F+a_
z^H!=}$>hCAX~QhuGxT(1^Nuct-P1hFG3e*;eouy_GrYMU!i%%KeL8rN%Uey6^E}?#
z-(e}A_co>S&+#6oV)p{xMvDEM=ZQC>uaH+<g}x$Q{Vo`~z?-7)WEAtH-(Z|2yv4_;
z^8O<4+fc|{;$^Ky=VjhE+dxWrzf$Ex8E^eVpq29q-vxFBFS`+aS9sqggRA7Jeujyw
zJdGA8RlK(KAhkU1UvRsQw{0E_UgMqh#E`D@gmKWT=k2F6YXdKf%HnVES~+wXvXSS?
zhDH<5jm}~>dH1M}=@yUoU#g5(bsLsic-tsS+RE!Y0FgGHWEI?R=OwFv-NAEGL%oxC
z^Hub9@%(9N=;k%;f=CbVwH)a6^2+G_b(^<wDWLm!KhUnIpSL@d&dLM4nSaqa$orPI
zvO~Owtw0;*g&hU<9bUjc(74Ns_zGT(@Meo3a*sDb(f(0h164}i=bfhC#TaitdH;a-
z*A{?{^8&ucpYS2?`zUY|yz0L&-bvo!_W=EfcbH<HQ@rJJC|IX?&9vp8;Vqa1ndJ$7
z1ez^>6UC$K_}`oYvFF=-3N#1)UP`DQ;XD5d&XND^9(duzfA>WwIP<s4(dWY7^*cOt
z<#SU2=EffzfF*bSxm@&l@Flcm_v9a@Yg=CY>!~pBZRLB?dD@3x=>+1--@6Z;e*84L
z3hK}IDFhe5U-BC!A&~F20?q{Sg_QUT=F4db58-ck6@8)n0#~Sq@v~^N6wY6<34KTT
ze|!Y)7=J&NwMX!u+78J`z9$`rqxgAk;G+4~-%kQ9hHs_7aV)>h2!qG@eK#Q!$4{Z#
zJMnxK?ZgxK=l%<q@K@4PmBjy%KG|@BZ;S(WGJg{tF;e(r3Mi!VB{Y^ae%ngSQ#$_<
zU1-YS7f|KVNxt9_{vuiYt+`Oo=FhX9fc|Ozt|pKi{@D@8oZ$<;M(0^RkDj<({`M}+
zWgdUT57_zq6|aDt<8P-+YX$t5s5s+1pK%K23;A!*X1Iv2r}*pz{*IFvOEKS$15(1r
z|Ki1y#((PtSh&RBL?_A1{1<1epr!oiB_L(|i+1QN=QmLzq=LWp4`5&6`_bvRlK=DP
z=)20Fq~eY${{MvFs`*KDysY7S(b=<>{|yxa)$#dM@O+K0qQJ~`{@#~izMjvCf<goT
zwVyHi8~i_7fZ51@HJH*kP5jMN%W{+NPmj|rz8!sBubJN{1a=F5Y7GY3${!2_S{wg7
zMJU?&ofL%c;J-~JteyNV4EWT=kD^>wH@|;1^m_O)<q+xRfBZ9`Z}Z1ku-nJa8G%SY
zKQ0RsG{AoqM;z;%LH<*8upHtCuLjyM|K=l*JN)<PX}rt7MFm?UeA{~fy~mHCP|PU*
zIz^E0^Pf{dZ;bCr3J>^oC(t*}4^D)ohy2<c*qz`Ds4{GluR8|vh+jtWuPJ^DUH_Tp
zdr)l5I>Wbr1>>FN->L+RtzdN^K<xw`RY0>BbWzU3K~TLIibn*q6ee{PbkQA9C&4=l
zF&JmT=a)fT1QjEgAXh=?I6&P5J8Z$Z3l{33=OHl7g+WijWA6gYOW;c<5pRK>k`_Kz
z!Ip5y_zFaH7WEU%qj#&nAY?Cm3K9sY>L6IqNNaD1;FWMRh6<jng^4hMH|6}o1#42E
zepK)Z?M;sf^hVf?5EO|qh)98mHh@urkRce17EDlPAV$#K3$R$h^R&Pm7g)zAYZfP1
zK*^7IK^g7!5(K*`D3>TG{Rh}df=?qMazY@duvD^O-FA=^!ON5iNfrG3C1BD7-SL=&
zbU^^^t1<*$?*iqd;1sQ$rv$sH%rsL_w;p;~f}jQPK3j0{2ry3z#MaNCkt5ifjMg)P
zr{;k>E7&FmcCO&&1Hj}78Yp9(FE~r_#&d#vN<S3{5~=aL;LC&1D-`S=1X_{c5S8Oz
z5X4yEOtC<`2(Fa~){S6f7X_oefW9Q~*a_~kfb}CpN(EapXiHHh*hlf5a>3D^Fjyg&
zM|=4zf)pwjtrT?7(tlOp?Tx-FLHJ>qs1_7%2U?9_<;#$)73it9q)xEu6?k|}@Ix4U
zx-O7EkG^_AFhzbF1d0Em?}lIr?GqXW?_|SllVE58eT?I#U>OxI-V(^@NZl;>;}%GZ
zKuHn$R)K&bgl&SS=`+Ob0_|@g9fIO!fOZPTDfQ7MctDSTx8PSb4E6~6JJ8oFcx@1k
zw*|lc1=1(r(*dkskn}HH8xYLf2IxTn^UEh6dw<T5KvRs)VS#8J^zR71U5vrp6&%ii
z%!t7DM>O6Oyz2m%QNhvsFn?cAw-<vM6DVja@=$PrV&fBndH$^)EbEK|tj`GMQkr^J
zaIGH1R`?A?4ef+;X=`dPTono|2jM|lR*wirPJ?q4zC|CqauRAg@rQ60#@&Z;7h&gr
z&y>)QHmGhwe@e5t3(G}7@eq2y33X3lSp*ckgwDGm;w{`}%>nfhUh9GvzQXN3@Y7HD
z{UwaZUzqSR`T~Tu^x6y*o@Igy63(Tgcd*ds96&>a@06l1RQN(0)Wd|oP@p?p_{1+5
z#8F{MGWw1Q?@%35gs_B4Zz6?p7l0Ba?4we$XrX776^b#!Z=V7iEA*sa$8n*L2e>$)
zmDZ<t;m;H#NDzKXbxesuHa(h2!XxyzJ|Vnb0WMj%pBAJP;nqSlrV95YW1wlmx2Zxa
zU6@WAf(+pwv{s%JZd-s^J0)D12+U030`6QCF=h!Lw8P<SVMHlfPYVwphEF-dT}z>V
zMp#L2?X$u<%6#MsBMzW1Pq=my?B)xXjic|J@I50)fpEzf6wV8`C^313!s|KyHC~IY
zVY4t;A{<^1?=K4NsAlJq@BqcJE(`O{1Eo}W<2{fvVJBs3%7tI11EoUv1-<942)ED<
zq*54?2M4bTJE`WTN;pl$C)Gm6S%B3Dw|oJxTH*KaLa$CJq=4@=VK;5Dt_xkQO^~S<
z?xvdv4Z;uphnZ;--lP}vP2s-ZA$m)AmkzYe!fXBLYZ2yc2Wb@!Q?W;zQ1by`+J!%V
z27?{Ka;j_Y6s9G@i!R|W3n0=hoTOrp9$_0jQoX`9n!?*c_mjZv6SDTwYSAyWJqC>d
z;rVRL;h=E;GQbQ8-`)V%hJ}+fU3Y}feTRv?EA*kO8Y4o##n8Vee2U^Uqe2#~j`xLk
z{n0ljls*pbfiScSK8*`QXvKage1eYi6T;tK1LmY~imqrr5?=b9-qusXiVPT>7M`S=
zaWleu^rD*;w$pt?TT#OR?AnRa=Ah4Bw2^8}9Yo8hGWdw-iV!f4qQyzzoJ2Kr@zPne
zox)l!B5e^ATt&6%5OEVVQV7XiluvO{4^ilPaGs(mWJ9cTyhN{3qSss0@gxlTh}0D3
z^c5YV4UC_tDH)^i7cJm{1c?6p9N2-P>c7wzBuah>3c;eeT6h>Da&5rqLq#vqA2du<
zmjp}UqPQS%M@6Hv;Esvzy$miwq<aVUB1P|AL8CQF#C(9(XwefRU}Hod(Sj5!vZoa1
zaZz;w?8b>cT7$vFi+ZRSCqbmzj|oZ?z4Hz9l0-jg(04-g6Bj-ui#GW}Bt=xP0M4X}
zcDBP(nrK%uNV=%(8bmTgzJFu%Cq?<TFm%c)digQ1nW9cwXR<`0e?v4|WG6u5X;I$>
zc#$J=r5f=wqSzI%bXN53b#VEj;csB+oCpQSc(z0n8{yM=5hoLRg`&(lpcILgRfAj*
zZKV`=vB+o(e@jH~(Tnk-$eS+vToPH|Jq=GUi!y18S1P))6{Jk`Z3;}3i>5`;uMmw^
z0Q8DzE)@|~ipJ<WC|5;V3j9@x3aa5nwdn2tzH=e!NQS?)A|(rYbs|&|;87D*PeS3k
zsJaCP>qY&vkT!@`ya&A-qA05ad}|c#p{!(+=${=By(!8&g3eo_saC)=i^M0;*CN`^
zg?_7OqaQ@tM2Tx4(k}Y+3HaL~il^nKQ<Odd(j^KRgNbg@Av!tqh$85G+AHFnhr(@9
z71cZTiFVR5)h~*c(%E@Hw2G<%2SuNsfr%l}lAi%OEIJVjyLUvsRT%bN(Zjt^91&e^
zhKYNkYA;}qissVNa$mHFB86ijEk&6gh;~i_Wn9#;8|0yA$s+Vkh-!nuO^Tk#1m+`=
zQz9CtL_<$ew02swVg}eVqUR|FJ1c6MzzA){^7rAlo%o${n70=ry^IG>JoY}gBVyI_
z@X%5GOah3L_=W$rjpFAi9_AvxN}+C7@#`00!c81ZQ{paOwGVn8;&9q5c#0qPgLsLp
zcnw+Sc#HEaQ1lUd(;Db2PC0;1Kk<_5;QYnOF99Y%+(0|bK=H+3Ok0qcHxDL)#jzAY
z4iT@o2Y*Awf70R=CO&-tdg0>RbPXgzyde#<9w|N=1HCBmB0l<}#XA<lUW|BP9DUYU
z@pY>HI4-WIBH1|chIyF8c(HphWD>-4^I#%T`~`haB1!zY6_!qj_g@B=EcRLmM^nUK
z&w!+g|D+9Dn%F|6vgzXHZlGj{PteKkq&Vtrpqvs{P-G=j{27H9vcwxGkCJT_x7>in
zX>lJN#B;<4YJh!4{NMt7J1c&d0gYU7iU`<w;*CSFlrK)Cqslq)Yjip<5W7%5@4T2#
zVe~?A4rMKh#N%{x>4MnX5q68k|4u`_L_9$I>Wkvn{<{hzes?#(E{m=8e?q2I9QR*n
zM0|~Y$mQaFbZM?a+(p^0E8?Py0Id{zlZRKu8>z&oN?cnD&}#7zCDdxf<M!~PR-B9q
z*g19LR~+HYHSu$C7~yqsb0I|P#W!bRs6o7h{`NP-74(J7MzOz@z8TRZ?xYCkO>y^C
zaJR%wOo%p%7tju~MVz|_*sbEX=sevf{+`~+?c&vx+3FDY)9<QNtfDAWm-v}&u-h#T
zrdpdGF^^WQUU6Ft)NhNUsM4)ZJlqBI{o=IsP#6#&t)Udtp!f$WG#(Onl|g1$ylNAM
zc1P@a36pSFT=o+hN5s$k4suWI`#2Ov#Z_nE{(W(f9wx@bS{cX#abOwx#>J0Dq4!X%
zrytvdnA4BON%0W5_DDRBj$KpY`Z|zlab^@ni)<x_DH>rX30?=^>?Ms<AL1a<Q(WqZ
zWc>(49VMZ3&UBItuYg@=Nqs96TqFr}<ZzX!=%R_6q@WF6xJ$S-Fz+Gppwp_S#6oqu
zUJ_f%T6jz1xtKg3$-3>(^ObxbPVYZI$!S`Q{3SdN<|IIJfa=NuC7)7oAxLuJ9l!)j
z(o9ecku0GISg7Qe?=iG6$;g{f2$u|h24{{+y3>GiO!7ZZ^hHSOD7_acnV|B8D9L;}
zPe)5W-w4SViChA(Sjl4Y(0W{=e;sU`#Ag*m<0YN`08NkxD07r3DLw&%Ns`=bjPQh{
z{0I1yELoR_z7)v?`W9!Zq?VF3X_76J9!!^fN_pB0$x~aPcT)1vH9((|G*j{~Q&JTG
zk|kj+gBRHnG39AbTO~gohiHyuie95<B-cIy_E|~i{{WLKc{>yud6Lx=5XqM;`WEKT
zNyIud7D%4hk4Zc)*?bZ(g_6VR=qr+p(huo^<i`dm6iYhez?De;xdgC_5{ozVE=g9?
zl5$z{8l9(0CDz4P0aGUVDi&<H#P|--DkMAEK)WL0^Dx3niH1&iS0#JSL$OLSs)j<f
z<j)wGsF6(9L!?&ni5wzzk~%u)U6X8B2C(ZAG412(CBM)QxIvP09?sm5RL+A!qr|ob
z3Qdyj*2_S<De04=^_Jv05fqyxV|U<ii{#-M^tDO?hheuv5=*DmP6>;4EnO1+J?M8!
zf;pJ39?5ZENcKv6K8DC`$#=F;=#xmdf%HoPskn1MGKaoEF(_%LZS#=iuj}X=mLvpH
zwDyj~!vdMR5;Fy8MkL2+<9SbVsvTa8O3u)s_r4@g3o<5AB*5SU$@~<MafydL+<quo
zO);wp$!ncZn3Q-l0_BlpRXjwdBt4J8!n7p*HF!89DgOk}vywfJq0d%2KWE+=Jb2Py
zoq=sH-BgcO2kGo8a7Uznv!UTAEz(27N%|xcpw80YnBZKb^>iL_mHN=C<t7#SFAQH|
zjizmemsC@WHg9PVZr9H7ks|SlCr$d@6rAvr&Y|D7zx1#pKmw$v^FRWnmn0ZNkkp61
zJ`gPRrDZilIz(HhP^k+oZ(-7Hlo$w?=F{QtsI=!HM2<<nu7<q`>8D=+Gg2C1^+#)z
z^nn<DMoT}YYd$ejHNE^}rK{)weOx+Bf$KQwSM*57ONS%jQ-aikO1=`MU(?wrNxG;6
zCQe9iP|Z}b^zSDzAt}-++Qy|y?cLFrCe_<PJzZL{8eE2Sq!MnQls5iJ=fqRegv}UJ
zrqqX$jakw+e}FUDQax?xPfO>e0yIau@i6+%NEH;hIxGEj6biXg=3Q`k(t(%ZVZOAX
z9o#voS1S4nq|<*v{k+th5><uLPaXqGk+kv+pp;0Dg<{kfrK&@;k+~$bFNWx4>39?d
zQz|u5uBA-+OeH|erEDt2sF0>nF8hi!oDJ71r9~dFbXB^W3IVF52~wz6ODmc&Gd0p<
zH({bydW3#Qby5Z0KE5X1N@4fwQo{_O>!mY)fHX+Qx6r>_xgota37JOeuFF7cl1|e}
z_@>mKzTI$3dVMh_s99<fp|3^SxfP17(gTz%Y?BVrFScFUehb(g(r0Th&`zm69cQ|v
z+>IdJQp<9v_eg8^gY-)8&@S?}^iRqZ^+|P&Al82AJz6XWq~)|98kFw;60JkhMccp)
zOFuTkwL8)|$w0d+HPY5}MC#NB?w-_z{-4UI)PY{9_ocBR@Ni5TRtc~N(i3Meh;gYK
zZGaw1e{2JpkOtA}I4S*-_PLLwZmv+6vPzu|urw{bx)Pu>Qu!O;W~Fvij%h24(*WB}
z=1-r+x0mJ9^X4E+*@}T4k(nrp?kL+#r)($L$BRImWix-^kLDsvrF#pmviVdB?k01f
zvPgH?Z*<D`kkwI1wx{gFcL3%k`>N-2bb8BX3t-+y=5+;}uj~(s5%|d}C=BK=JJbcx
z02z~tTmogA@%oz+B%6B`Bv_W>2}>ce_9pyALS<Xe12jw)@+lO;Wj?goKPn6Gi(F!T
zq5;5BvTpiFP_(R+j`%UMw|@kQm3`xizIfT@-=LKs`&S6WMA=G82PDb9tB08rvQ#dd
zPL|ELhe(QS9_>_8Wk=|>nkFj^gF?D&<3T87$nMZecT)D~8%Um#*%e|SnKF}=c1T&W
zp$Bj?TlPM^%1+Ccy8$Lg)<}_wGqRl&&^s$TY7fv{*?~jo%adhNv0T1PM|tpbG8L`!
z1+p00%AJ?hQwXF`=Kmx}kxc$0$OT!?DD;YDm0<uYk)6H>FD}XsEBqHlF|EG|pjR%t
zPtSaXteN&wS7d2rnAJ+zqH=IoW!q?9SS7pvH=L-J8EDdKWR>*Std+g+0YvI#CnCXJ
zlkGbJ$?LKmLvX2HwrMW<8f59G;pYw6(jbheQMP#z3^mE_A3)ztnbkTBjaxEjdI*|j
zu6)3>$QtNK(kd$+!sNBdei?>FyKFvHZ*|B{+yqRgY>gj8x@14m=D1rnO56S(nZF6@
zy|Ud);OK4HBo)y0$?_--&@W4&z1x87f6oJKP?knfvmx1HZ+d49%S2n@%^g`x5jyY6
z(%*!M5gB_w$URw#7-Up-fHsTwWf!|a#$>-e5As0fK##(>%(4kn@=)fm8(<T%U+GHG
zr0nxxxb{f)WiHgGWClugPs`S%!O)Cs%^M)IvW1JO8rN3-`iEfc<jIdg!(M*h9oP<X
zJry_~kq^HD;wayZ%Go(C@=G^i$yM$|xoS80S3ESj%MVg@s)u|TeaXU8zLCC0;3YrQ
zi4l6skI~QAN8T=h1z-8Pvk>u<zY`74U;cO=ecLNQ{xenB1j@g61Za?a)gd?>EI;xo
z6hq{)!_Wwo*HNu%m^}X+K*QytpFxhww^NnWF}WcQXc6*Sx)2{J|Fr|=qvS4hG>Deh
zP5?7T-m()4vGTPBaL479lz@(t-=7AiHC`T}1Wk}1ZURY^AGr+BB)JEb3Z9VPqT^1o
zyqb<#De@-z9A~P0ihgBj@@-U#mM-7e04_tm<zEcqq<n-{+Eem@Fw9z}{BO$QXUPL7
zRh=zgeFi9}<>gd*kt63OK>dtW{*Y2`XXVXHz~;)6mx0TZzeqc>eECyO;Lgck_k~Xd
z@}m^#IxnxFH+Z4^^)ZMP$s3lV@q&CJ8S2Gy7S+U*$X8K(;iCL$HuNsZSCpggvb^OK
z%$LgRsAQ^4zB>@m<#KBcMT{!sqqL2`B7d|7ot1Jn9~xKX$1|Z{CC|G9OV#oo3QE<;
zqvJ47wQ}FrV4_YwO|^p8<RkZ>eqHWNZ@YT=n>Mi2AYWSwy&Ll1ouJStw|x?Zn&hEN
z(Rfq-9$h-TC4bRM@6KlVoe#mb$T{@6h*tT?4v;pvntu81avr_wJLEy1W1c(ZW7%lz
zl7H|exNi9qbRg@Izd`T%Ubz~9^*R0WqOTw_Aio_BkwLj%B<v2!*?r)K<&2vUxg#Ix
zfZkpCuNpdqkH|Y|PjydTN-3F9d8;k-@5?{)hT@ofyA8Mp@>r_rAD7p@fC+jicb<cp
znUL4KieXR6%V@*%NZwV9#wocX0NB&=ttgb9Gb7i~nRr&d@-~RA!k!NJc8XL1^z0Su
zHS{0e9TaA&2{@v-M(eVpLVOs`I4ORl4Ue<pZAuxqD4Mqd)Ky{11#wf9bJ6FnIAja&
zJrp6x6wdKf*iE9(OM(B{fCo?Uw-F|M6h$Eb^HmH}Nr9gt_%nFnuTZ}SLjj6C$PQcQ
z1S+!Qp&z99XFl|U6%Q!?7ovFZ2pXXZaRJ5@rkJHW4B?73w0%FS*h723V~T(Va1n|X
zRE8U=(9XhAl%n)IU`Hz~{_rA3G4Bx?V-?#{fpT2oM2E{bMJ8=u;uQy@&}U6hEUyKd
zsA!@%L6YJtcW@^ZpVQNktdP*7nxdFD2P9QdOaYuUg@yK>=?VtjLC8=fe22c1ibZX}
zKBdUM4fB}_Tlxk|mSQ;-M`kPRsFvWgVh_FkauoaD0Q4Ef5Eap!wJLs@3yoaGT}l|{
zDdsStk*}B;!t9+>yhp+00>viE&z@IoSPhs$1&3-yiWELn@qR&Z#SuOgE6fI9mnisM
z0K2Go#Se3MNnuCFoXd(Q{2*DXi0g!UnWE?)a90#7Z-J{+eDyIs7FQMHlohX1JWn-V
z)r#L-VWLK{lna?!#k$|1QK#4!2$5@wE&qie73xc{RIm7V4n!IhTTjE$8;VajFxaR#
z{}3om3PCIyZz^{B+a)Zq_IwKmTNNATgS06eu0pU~5xE7<cPN(r29Qog1D$}n6yKJ?
zc(>wrI-&L`3aBchS5f*tux=}ycSEmFv5+>W{ff5+Kn4`|zJ&Uqq9Y0;8B%Q1VCsey
zgZTivqgX}vi0&%(St)2RqFC@2%->UdLDd|i3OOxP_Z9#60DDZajebrK6wWK4IIehh
z2Sgq!_VogLLUEU(<dcdQN#v0t%?Bb=ibb(-W?B(12lR|0<`YcMtfG$=23w`N7Mz_D
z|0EF)nsQ+R#bz9oF%+6TqD-cR*ircjZD*X6Vk&lUR=)TT{B}`prS-*C`6|5z+>}w2
z_i$G}_ywGY((!*#_f)=2?_e+Grl&x>m6a7x_fclL!IG~sjcNz{lsD;!=&$7bmsC^!
z8BO2N3{<uU0wzcqUI_ES%GYUM7^3`WH%O>*ej571loPaZ3RhNNhyGC|XAAm{DW9PP
zK!nnU>MbLcVN{_KrHt<a7p=VVIQ)%KuA)UUR{1p_J{?!K{R|SP{PhT2i&sjdbRjfB
zx$g~VBr3fY!$gwOmEOfClpBMgpRD|;1ze^w`g@Qp<zLPiXtr`g8!Vkwen{DbT;(hD
z+s;!i{0X4vl}9K#QK-E0-@~Bvq1;b}GJ;AxDwR)s36ZPH>$xygr94hQW^1+bC;9``
zD1+%1SFKXD8ya;=5gmfBDO;w&T~}sOD6By_xEYc+lw!KW+^9^VBW{!Ov;$nbsm$+z
z-CN3<8c4P%*9O2+tFk%=mfDnij$wf9$^tsWbSRrCh})$cjE6$ERmr&kv>xRlSD^JO
z8+g#Tt$f=K`h7}!n!SEynmsfIl_9ha4=KN(n9{H^E);!tlxG-dysHeQ9O#JhFvUOb
zDJN)`JgU^t59z-0<y`cQDc44Wd!Urt0c>2klD<3lQ2Du|5Kc`fhiDHxsa(Ap+?4VW
z1^cFzyD1eqqm1i@=&VvQ1Q=UYr~oi_s%sQMa8OMZ!|fxg-w$CBj;ayb8ak;;X{+R{
z`q6)XGRs<e5##h!u~tFQOV#iL9Q0Pn&cd9ps)54zeyX1e0O_xC`~n~Ws;f8A7^wQ7
z10+Z_N=b}RRTz~GhpCp*xglItN58nEs&ikW@0hBU!b=e<;V4M7YA7E=h*7<(fk>>X
z*!l@t<5lm@g%=5`&rIk{R4IKxl2vJ!U@%2>eJ{+Xs!}LSl%X1@qv=Ui@hBWUrP5NJ
zNVdw6LeHmF&QxcdqZ)V#T&~JM_e1hjhCT2pUsYlS*m>1x7VH+P?AF5jB9-bP#ey!V
z{NiA+Sf#vy&Jxvg0{DGdwUEm3N>$r4z?G?LW6)QwDx)xdh3b2%>%5{$eHzYGsRUFp
zRIS=hhu<1iGzEQYRc{GlzD{LN#T3_6_b9O1pjt^a1~*g_6iRJWeSDf8@LMV+18B{v
zWU6IuQ59x@YgZ*Mg~1M0C7tg(RrORr*QKgD3lrTc*Do>99@S!cTMnz9NI>HqRdqf@
z?y5KxEErLxP|@W*Roe6D8&$nI0I>V2H|V@Mrn()7z6YwYt&iaWA6GR*Lgt~Wlor_u
z)sr>=om4HNW%-e+l@gOvsws*qPpcL_1rswW8!AGcRe9K<(N^7Z05fZ+{<t5F_UaY1
zk8n``^gY0is6%Zb;;6n=2fI${lGSK*R&z2iBp3Aw+KF0S)q6fgr<=MZ9;0_xKllKg
zhk9u{%zLW0(3N^GwGEl@Rv&x`8h+}#3DEafFQQdBK&>mlU;@=oyMY9$TN=<8tloAC
zeIaUBx;PuE&S9f3OkKMI+%Yw`2#!Xm555i(X;ptsd!s0I$Qg7-tJRcMj#2kzz>8S*
z60&q$ZKbztoccIDBk}6p&!I6v{r4v5C#qj~4&zNyyVKKmLVX|}f0$&omg*T&)lV&j
zLYmqq93)*GlLLhe_1-E#pHy$igvcqiHT5o9v(+zBiSB9j7zbRAI+hAM&!}S;!_ryx
zT-rhBszsE`$WwptIy}r*yU~vFoO*RErldffMZb&l>VFpjrBE%TYp_M?;8$Vdg4&&)
z>0<T8qaYX67b!_ps{V~)l4a^VE4{_a)&2nhtx$)>LgR|M_YAm7b>s<XTvhYSfnBA(
zu^D~UYP(e+HR@4%rPiwJu0p*|tylzdP3^1!xvrja0jXE-+=W?dR0n3lnI^SIEWmE6
z)l`3eOMP?@7Mj(`&6Ip>Q@_{;wp~4N7K$C}j0p_1Q~h`}^t;prgD~H%{^bRb9`(Xv
zNcO6We#4aBR@c)BsZagWX^?*P)BqX>)Neip6NBon8-X&U-boATu-es(#u4>i0i3z7
zj{I+ru3rBqB|jdhKPW`!xO#6nG#;uQ{>2PUsPk9C(xiIDm*{(>-b44MrqudKG)}8^
z^ySVO_4X@hoW&mvb7`-+{1u3UCfpMSk7$-tDVL*W0i8gdG@g`Qb=G9p!@P^;@c>}D
zYF6R2XPx7wDWKKMUGtF=pdOmWb>KWTy~WV?(L_@0%vUoM1w}v2?ax5`HG>C10yI5z
z9WGF_s2p5~hVdNihH55T;eD9K^Ba(G&FX1@9o6h|1$Rud?RQv+(p;sOLbS%|5WKL)
zXy(_zM671h1sFW8X)gm8r*ZcKXuRfmihL(%YRu3`)T~(pjU<gc252WVU-@FZ$(o55
zpqHr$+X#^?%{2-TXKU(7@3dwIeQ_a2bIu-MXEXvTr#P#bD1u(D#-Rivc~*^-zW$T1
zarp@3oTh&RNP&hyZ~OC_vmW3IH8<!&M3H8cehC*exBmfJu_l8Lv=YruFPONfiE=^X
zCC&TGFy70WHz{ISs+oNkmdZ4LoP}%Unpt{`Dm34%2g()A+jP6BQX`)2hvHSu4E>p_
zG<SXgXtk!3_6Ic@5v{1Tnos=0PqC~P3PCq$p5z1Nh9<}eml`$8^I)h+vz;F8o0_9^
zY`LY0H~`YD*|!T*(W1F}8>CfZnTDM<&36<kYS;Yg0<SwX4Mphd)VNR}rAzZPo#(nW
zQcCCaXtJnmq*oI=1#(*>-a$nfeVStxVEZ+{Y=WNy8a;i{bWmgW12l#-2^9St)(9ow
z?r6HHbl|S$4L^vCXo9I~_@1Vfu1bw+c2fxWzUBogcpcNY`1@oov4*BXa6)si8eNl`
z3`!zTYc5QH%xE^z6}eeW!4H@^d+lXffgH3My&y-l=|don+Pp4^IB7#@S##Dl?FX2P
zb_*piT(wWl!@%6MSsNhfuHCo{A|BfO524_x?f4KDytL=7>0rIJv$RX~(e}_T(^tD}
z7c~5|35}Rgf9+$m$^>YC-;MDFYd28}JVg796MPEQW-oz4m{vgb*Wube`lRhq?MHN}
z;h5I`Ni;@iGq*z|Qfr}8K$O<T1M1P*fmZ<*qwV;fPV})_-P7niuH8YIg*a`P3Z3!V
zOSETA&`!$%dP4gO)p#ar9caZ((K6`fPpWqBDvTmc+dBr4bnPoEFo+E8foCCkQv209
zm_MbhI1G_Y?JYVJWNBAWY&%=~^ylDCYlkKD*@ql$)#I3iGg|L)_;yyiL<_}SZ70oa
zp4N{7=K0#k8-RUIE1_zl0&Uzz_<LUaBfTaIwS^Q;DbmK%XOk{y2ZP{RvDT*)dL`OZ
zn_%#wb_>11FKKVAg=?3!)f7f4)joyDhjmVw_J<I-U#?yD8T2c(kNd#<6|FH9*p*sE
zG`OqUx&1I$rFEoTb+uOM0<K2;6BQrUYL`+8Z=H6g8wRgwpI88e>)Jo_AyThh`6TQ%
zXk(Xx+|b%kG^bH}kWRQw+N|GU&w5j<rXS}mZPb%MYu2u%q(zJNmrOLaYLB-7txfCs
z5L~-fOo4$8t?)}sLZ^21tC+4Xt(4A_-P#Yg;*WM)`wkV>_G!<?!bHC|m@1|RwEtTO
zZctnK6SyI5^hu}>YYS;Ne#ff)jw*@oYWx4Yd8hq{B4hWoyPV+gsP-ls*!Q)OwDgQ=
z*HQ56fi@xp9*%1lI)Hnqb)l@=g!T^Y^e44U+O$5>irc|WY3I*?o7TouLu5vK@-;xu
zYE$S+hOO=gDul7qSy?U^g}p8+60HupgR5Zhh%S@L9~^b>*TZioU0XU}oOSJg!LEyL
zlqz{$b@8n*@1|=G1&q6H*G3Qz-60jm<f;3DqOe}N3NzHbb=AAzjF0a24?ywN1(-1w
zKV9KnNc!szZaIn80Nv?5U;}ki_d$Ym*C>Dzth=%vCPH*2<XWh%*cFmtIxh>%hwCDa
zq4B7WeG1sebWCrUkI=nw9wbutj{n`9CDvTZ9mnco=R+c1w;~ac3Az=(LLyODeF9iX
zy3`NAozU&)K_ppMMKOvL-Kmw3Ow}3Q2bZP`Gy^4FcQgW$8M;f9?Kr7(UI~R$x}Pqh
zF;iDgxuh)JyFxT(>)wAEGk993wo+M1j&2hN!#$(>Z7)4qy5>2M$<^i2Oy=oQ`S2oN
z_tXg(Jg0NL48;Q7_}{R5UKfyyVHWDvYe0&0#lDcdpo^l^b+N9OHb^D9Y`Q~uQMdLS
z8ZYT?Pz>m@?k45!OLf+dDTGj_%c59Nxo+!b%vObN`%|!VMOQ%Q^h({gv|wM=1-}H1
zD&5Q9fveUXHUXwa_dzMRTAlm*uv@1qprq(E-4qXv*L6+Lg4FAhDX!3<yL1W)H*}+P
z9kfvw^eq&cbTI?8!?~%mP@&N+-IG)`+pPQY4a`N0&ix!nt4>Z=6WVl-)5G7cJG2FZ
z>C(B;ma1DfM)zfVblbaOw^x_m4eqw?PYWdbbl*`nv|qRE3rG&=nj1g{b-6>Bk|Etn
z%1sUHMr<imct@wE%80wVeROUZ(Y;LB<9oVsN`#N<7SVHaUso9q565&TsWR|^E|ivp
zab1ud$V1&bl-`-pRc!~E)NNV`lt;Q(UBON1=2N}&v`+mjP-b*2TR1waQ$=HBw)zE>
zB(mD+LwjJ}UVr&X49!7bvki(z^f6Qr?5O|b4~RPHn<=v8tUpIJqAvPV6#RA7%c&09
zO|SKZp1b~;6KM3%7rh1Zp8DPOQ1{aR_!Shq^*c&1ULXA@ly>mdH)g^oKm9#=gZo?c
z-4`GepdWe;Xo31x9V`XufBYI~!Ft8BXbjPxp-Xk4`gL?KGEARAf2MH#-y48-RDX(A
zqGS5UsgNW>uYU=kk$M4@WyR<hH3B78zn1(xuCJyaVuJo7+G8i`Q>mghNpFo8!QmAB
z7A+<?Re$(ND5mMR(ap~sedZsqbVlz+dCar=yA-?2)rVh!r9AzHIY7(TpQYo@IX#D7
zumyT8y&2Ez2dhB}^~<ROvPds_8kR2TCqD#AvA&<m3`_KmWtgCg`T;BL#V+aJpp(&M
z{qG0iTd7`<4w*82;5^8b>$g!gPKDl^!rNE$e|`*wO1*3o3|`fH>L603zdC`&YQ4kL
z(5ulGQR=5wKYbhC*XchigfrLlJ(Lu?u6KS8DE0b~WN;1o<D04VhF%Z{jYj<mDaO>K
zFZu_dH}xAfqwkjfc{4Pc^#OGArA1#71k$SCxDp22^eZXr(ypINXT}cwZ9W|B)N7r9
z(xp#v14_4kr9ZeH{a_iudi9yn;BM>lXph{d-|Ix*HSE`G=$$yAKNA7aLH*YhD<9Ht
zpd{C@{<8pp-qE|Y!^6A!r>I<gM1SrsxO@6fzJ}zeek2d(@9SSV2JA8YF#VYy=pE_K
z^0@w|6j*ww|M?|w6Z*|mS~sZ=`xnkU(x2T+&)<yxy_4{CR{y&lux$-{>9ap}hPEb5
zu)Sd<0G1pK+s>i!h@tK=7<4ow&?(Q!aA7Y%oeex%iCqk3boa{D5KeDDH^X`=Z*({O
z+YN&rhR<@)=V`e02z_3L7CO;*8xGQD!RljRz70@cLm0)={R})$aQ+7I8}w8dUbls4
zpdoDu6oU+hsE{kzP)R%JFvD?rbA%g4=xYi`4TmY$f6NdWiM|NKob&K7($GqG@S_ax
zN+A+$IM)x%7=wmTVhz811cl>PLjnb~;|z6_bB{MH3&da&3`OsPBpMz>K_khqzZqyJ
z3}y;NBpc4rqmp8H@H${p4NEowJI&ykg1&TvlnR0~47Zj-;iMsi5@)9jgGaz+8fpvR
zOqM}HA4$qK1Y7}k+VHg3J}BlGcKXj0u&gyB0LwSH&^h#+VeAnk3k>rn;OKe7^kp;_
z8Y<`%Tx2-81br6_hfaeO8*-^2x5U7u$ooY@@&%w=GW6TP!ev7v{a1=o!(ZpYl^L$|
zqOaUgL7B`7!w5w=t{9f*L!{F1&`Rl@tA<ZSV5<yGe_?>thS!&4DryXyjTlR<;iV_x
zMV;Z?SJ1y^SgMA>>jpjL%j*q)QRzT~p=})+Zy2)aFVSe2OG|c>A)KC+n}+D`(Ra)6
z3%y&K4SyBFP>W%h4*%_j)PE^m-(i@S1cRN1zpi0uT?W24^t%nMHE^xRu#N6M^%?}P
z!2E5)tQ7ivh5{<g=r?SpTJQmbOB56a4UcBw(~#k3`nwDp5{966$FPXPws#HLPeFae
z@Et|_?io7np>Nc%r=GrIbKfv85oluuWP|Y-8J^w&FUAco)8Bm3pin~pkwH(HiYdci
zZGf3Jto4B8jNywxn4dMUC@x`Z{Gk`b&iK($n6NjR--MonaR=>Eju_v29IiPUH{6F^
zC!-DB_;NPx!tcO3$Hh2F*&$bBBE^B+jQMoHcQ*#_hm42O5)Tue#=b2;^D-8G2;yx#
zM;EVsj7urz=xh9!u21+Gv)_Wh{>C-5FAgwXd=gxs@ngy~2N`eFLLu1rDlJ+e#x@EF
zh8l<HCX+SHI7>0)aAS!D>`~(ru^8Gh;}v=xL>QfED;sHar?+U7ap6DUqK)P>V8<9&
zRiQD~c<6g595=>Nt~Jhh|7C#18_QVmKEaq10Fgvv{PXBbGTx`y><QyjWgyAM&aW}e
zDORKX+h9|TwTpqBW*l#We!4M?w%!@Wf2l72r19kh=$|s~8pAwg8rx_`k!8%ELSMG=
znOHb;+PIps7&*qE38<ejGAP)6*2v|9%Qb%SF7)z@u~cH6ZyYIxy>rG-e9>26v_^ZQ
zwaEDPLg-&GX3$Be*eIG0{SssUbC9`ce33Hxmy8?QF_)K()kgG{8hxn9tjxHQBB$j>
zfip;jF_nrWt{9m+V4~9a#=j7`YTW!PxGLipY^YZoUtS3dHAcs^7(}fx-%7iNI^&D<
zjr(iHv{ewjZj7g$TfMQc3#7sLj1nWfVa%tnNTV^#0L3O_stpuw8t3nZGq;SJ=$+PV
z%*sYzi}50rjI|oC(i-1pEPWPw?Z$ggK%v7JSq2X~jeZnm?=pUzN#X8pV~Gn$kFl*0
zioHf(Iv3wIzDTE`KBGUqnfr|f6*LBni>P*f(71*+QbWd@%^<_ZifmxtG0yx7@9!GF
za|0PMMu>rO&sh5oP)3a^y1;zj$e_&Ym{D{FdJl}XbLeF_Zd_rD&WA>C+5}G+_tAS~
z(kOX|F+DPlx1evzc$=;mO&j+Pqi@FeD(%W<jh{RY1zVFB{eA6BTWHm?H}z&i!NIh?
z8r%_+9X+XzriHdJ=wkBHq0!a!<$8#?nI5ly49}mt={E<=iHGSeine>24(tWzWeWHR
z=DkhtT!x~L={u?b^EEZR4m3a0hXyqIo4hV!f&)xXg=6%Arj=Bs8)Q-{&=_nA9RLY2
zc~NjR)HFVTDG4*ZPD@$1DP<cPkD49@!JhS)Y2I95N0_$C;8dh(?SIwDrn#R(Bii)-
zN3axQx=96su_n*s&_8Y(_#RxGDV%;@@uqF(p_gE?Qgk!XWTf<AlIeR&Zk#avcm{pR
zrnjizEyYwr1zxEpLn@{+&Gf()BI#Dsx1CVTFtyS<>ZD0{7@em~ztR1!Ow*^6P|Pxg
z(3U#e^jInSPMb6ow9hdys1)&xsd6<M&zcTYVKBL-(h2nCnQZ9&o^NU@f%oT3^Zn6R
zU@~<9?7XR-4hw~*npa@H$YkA3wX7FRLv$aq*knV8h7wa12O1YmF_b93WLif5s{FDk
z`aKM$)O6-F6v|9r(oeSBR5%Nf3e%BPh+Hu}rUPh|>5v-!R-2y9fJlw$(m1$Uljuc=
z)R~sq!NN7u!ljVBZhG8Gf!lhM&0372!Q}BghJC{nLVJKl(~l(DWNM=-{hKB|eQxQN
zsq1NQ&8B3!P}yQiqO5kS>5n}?X)}q6(ARDnqo=sTl>8)y)M>g}jQQ;{<=z5xw`pKL
z4E31mouS@q3b$A>rrV~hY<SaWN}?!Zzi9<+I0sBO{({D!=~t>%8Zu>4LU-5{$AcGl
zOg(R)@vcdsf%=H)MY<z!&$NM}ccUh6S_<!*I1a!ZGi4^gwFjmRv=ok;u29taq3MVl
z^d?N{t0~GfX-aB_rAMaz=U{%ybc#NJHf>r+=gk?D`*YxCO`B*DvNi9y3m7|d`d)DM
z<~I6yIGCBYK#rK7{2m4!&7-tXIGGFA!V71!nqG=7=B;6{;A;M7Jw)8h_bD;zZvNs;
z`ZAJ-`6N|Ud752l+v{bXa)&{0^V53(>SO+s$~t|`Qxr+^Ggm$bMSpYhBg|g7dCpu6
z=BSxPU!*u@ju?Wa2=gO)VMdw-`_UL>eqIKVX!E<jV!SctV7l`gYgT%q@3{H3Yv{Aa
zncaNRnP~oUF7%Vk?KY4(VRrBUOtRV14$&0zOFx06nh!j{Jg1p|-T_C`&7W66B*Xk3
z?JQ23)87I)W&ZOOfM%L~sWHpk8wJd4vz+#_r_E>S$DLz-Itdoem?tQ9bJl83cLJMh
zeuWmlJo95k5Y0F5o57TvH!J$kSZEHVa_k~=kPhU6+29RQY@Wz~WQqAPx{Gnq{67&;
zE}63_ynoqzgAy*K=Hm;{SZ1!EL_oQDasYZ2W;2~}u9$D_L|>(uv!VzluA0l}5@VG)
zI1!!IW*!C5YRnq{=&~iMJlYC3n0edLcEg;$0uqg83xz+L%u!UdaMS!Og`;kn|MYJw
zTVh?W#q_k9ztcgm-Q08?q{DprD`<C`E9hS)beS#oQ0q1?)PeMv+gmV_Ub7$^c5a*B
zrBa<f^EWR-vfq4=sz3(J!}OLPG{3b2B17f^85D-iZ$6K{JLZLsuyEI$H3PFFW}!6=
zGWX1j{s);+^9K4t$bGYp$`Z!R4s?)xU|zHo&WxLTsH|<$Jdd{5kIX`UkSX)E>##I!
zwo3vxV?Ii^9cImcd<xFavV>|y?JZr!P<OBl48raa%WnFsI$B&?Vb;kKTkC%h|A)@I
z1%})#3Cr=*a<`1$gNTPEmQL!PmccLJnU{rk8l1Pq^%U&+Smskzy|3j(3J3XF7S&>8
z{uTjkZv!m3^b!cP<X=Q%kmb@83<X<Q|G+|s#g;+|p_XM777Vk@=+PK%sk0UX^r&UY
zLx3K$T%xO%5f&8(Fp-wnOW>j`r|2{uZSke8Rg9&Wexb3JZ2Fxax2&WCN}MH+DyiZv
zOXmSJ!6I|P6ee0mGGHm$BBy6I#ga{BU8$D8yWwb>C4mA!=@xqj+KyycMwzg5(jpN;
z|CA+(LamvW2jvjWvK*u%Shl5xR;SaJL!EFY$Fkrg^v+nmrXR^!i}@fVi!5*52Y10T
zPHRoEg+VX95=$Tp<}X^_`4a{&SvrECUTRso9>XoOY%Zh1`*O=eIwMqA4!A((ie>ee
zkhyC4ns$FxmiPaMzG};Nl;Wzfyz&arYAss&Q(UufT+w&kl1-~&y=6}zxCYBN^wiw2
zY@;7wqvdQ96q+opSrEBtu|#5Iw=B+;FyCz1Zl+y*i{+6Rc3Ul*<1oTD%K+`_+bu6F
zgiMF!n<mUmr{yq(8M`dI>j2tqk<*U9$Kp%LxL!*y?cQ!%vNnSBSw2$3e7_}*9`*st
zo6kUR(875h{tj8pR24C7@%#*pcP#tjz-_y0dH(_Eh~=p|Xxy{pzXtQ8mSL*kyl<H#
zzsD?}(dqwzWgcx@#x48xaBb4UrTUFWmeq8;oU(jK)#=lgt`0QLSibUas8m?J7D3S2
zMn@GIE;iqBfb42>mnyB@Z2BoK=x&pl3K376b$2mMUN)voNP62OQ<%-i#%2H_zBZTF
z0n*P#O}Pwzn+>#G3b4st3=(LwfMUTxHa8YPFW4qF3nC#ldJz;tZLV6=(HdqWryX;+
z&7mzoJ8DzZh7ldJdBOq`VPmA{Ez;)Ej~GLgjr%@`MBDs23ZG(Z-lNxXtW8Z1xZ^f&
zT!O(ko6ch}7;iIl1th^Hbqz!kZ9-Hqm}E0XAF?}Pqjv*Iwz<5Nu1BQUxJTj7nribR
zB|y_`Ufu;4(`~+>y+MY})N3%GY2zOO$t;^BI?ZO=2q|QF+D4*)+c`FO#85wD^F9St
zb8X(D?L(f8KYj2o-{z<1AbHN_%|$R@U}IVWX9{f=(KB3RvnBemHFz3q3OA#(*k*kW
zMp$AqCkHZ@Y#jYCrpq>i$#ACBruZj_l-c~f42u8f=(^*wtiHHrX4=ryG&NgVnVOX*
z@7{Y)T8_$WSellr_3LG*2nw>1Ekgm3r7T6J3}vf;AfU)bKtvHm*6(}bpYu8Q%zNMG
zx#OI3A4=^aZiBPT&Ok}7a=TqV`Bn36X+v<g+V1^r@bju&`+p}AyT49?@w%OL7If9v
zEu?))t=(`J8td%t_@OH|>{8!^K)u~O3VJoz87T;R)2@(y`9`}n6wYX}i^kpD>CJYY
z^xWLCdydjqx9#T9!_;C|O{s)Cc0RV>fVSH03xvCEcG2e`-)@&wgE8o^+w~g;rqk||
zFxc&~^X7o1+wT5afF8R{`ua+r-DE2)_1l@KeCVFtJChI?uv1d}@V=eHJ75{K`;kr?
z5A9YifZUK>>@qYyvio}uuwlDTme}CNW4rya5FD{vJR8KPb{l5^jM`O@nlZcgsD^Lc
z?kv3-lXe|+ta4!d<pjHqjOSJYb7BldLEM>9y%Sy>U~HgW!$F3Mk^+Yq1usFF3uBb(
zb`CQt$}twMjPC}3xiNxjsAT>K<GEikq(>QN=mB(RD4vBS4+evx`o|cOSJCLnFwjEp
z#aOupCcGK(ltc7ku&H>%m$8Au_<oG<s5;W0(HRP#0vJ9|q2)NE=UWH_GHfFF8^jo*
z?Q1Zjau=`=#xpzUU(tm!j?h^xjB(>-coEJ}e+j`8jQ18nO$4L+4lG47j#A9-Bx8Us
zMV(^Yr|eq{V-JOyV;MecAs)wI(votTu}X=?c!oj-fdt0A&%l|;Sel5&B!*)?>?Sk5
zp>-;SG4DMz+RicpDVlkXQA&Z<G{#0dNTf4frSo3~Bjr4PgG`2c0N_01(|B0Az)0r<
zWHC|-;Mzq-%0Bcdo8jdJEQeuF>HJ*Ax_SuYGdzniG6js15MY-WJzoP9GFmUfZV`iB
z3k$_I##(wlN*GIK!iy`6Gj`Bj%BT$jPZ{IzJCHADG`#|)6^zUPn5bk3sWzaBafvdZ
zR~gUHuXT-K{S;cRGrrG<Kn)}C4rsNEZS|nlF%)zK^9JMkuK*2<_gw*QGTQ0%+sLrF
z(`?+tm_j8p%?xn?T3Z+nAH(1s#z)T3*2?I81tZhOsQLw*?Tn^l=tT!(KTX)3jQ8dP
zbTeG3{JDqm4izfgWz5I`OD|(L9c%g+we@hOpW#OJDEAmwX<5I|xc)2}2N_&j3;ce-
zxU>Wk4;kOML4JsF`7dCP7?Ez!J<ND;7-}9fYAB`mgz@SIU?YrPANcf?aqu??j4@`d
zfR=HFi$DCGV6dCf!%0TTHkfc={xS&`N9GRN#yBwt+2B0DEK@<*LFV%t=`lIPO!^%X
zF3huZTtCcwhc2+XG8vTnabt2@Velxkdl4{q=9XaycrX*Xq3sxR9@VIMGQE7fYUbOV
zz5wFK{9`XT{Fzodxdbo=-Um3&Y+el|!OVXs_!Po)jRj{Yv-T{oFlJjDuyE#gRML5Z
z`O++mPXv=oN7*Rmmfc{9X6A1K%SmQZG#XDa=TW*khI!Txjj_xO>TMkJMH}tU<Czn#
z;5ozmJ`b%4%*4}ZOk_@>U|ACLIa)N6nN24^OJNRD&gCq#n>MHCn0+Ilr7|l_82U8k
z*m`KmVE#T8-e)qW(4=#o`O-7!#092;w*FbnWI2AFi_8V|4`H&INj?8nGBST3g?t{f
zQwY|4rU%7>3YdIagf21bmjf$gKIZ_IBIXa2k}hF(7ozbp(}T9(SD0!#d6Y7v{sgUz
zsrU>YmNN(G3u+b29nJt%OdjpCs+j?_fxXJSPz-R5IsFp-r?l(L`kyc~b<7)L^za7r
zdAhYw&-8x;o(AUBn~=ZBd~8EwBl9ylw>2?;I0SHu*-wktZ6=!rsD+t)2man+9@fEp
zE3<tU47M?kb0FT%)IS8Rli5wLdl&Ot+75R!KfFiVtsdqRDh0pGe4g$r_A<*UXWGY1
zya&O4X2KGT*F9zeC7}nH8z~TQpSgn8rUy(G%^DAxdGzu8A!h!+@Zu4(#RA>K%*hdG
zdCb&PvC|Xg96FIaW&ZCK^mCM%It83#%!=*cw2d>h_Ru}STz3=1NoL$?dj46wzW|(A
zo^<$dW~nKFcYyU~6Tm?hgMQdUtS@Mf<HCx*2f4$nmp=uk8|&4jpdDegz77*dS?^G-
zygTb=2v|H=KD7P!VsY&Oyjfi|1^L)m4%;E&%kr85hy7UVX2D^9Ry6&;?f_Q9b+{PF
z>b(Fgh~*)LL@=wV2;B~0mC{}#l=VF24Z>K@(bufPS?hCPFoJb+2^u3=`8$C{v6?9)
z8qIS21zwzFb#<cg6zfHA^d*L6Yo}dUEUTCD<#DW2G)<jm^-{7Xp7oSU-xFBTG*2Y5
zBrOn3VwI%B-(*%ZoupG(N4J7@mbIq_;^$Z&=E6i8OGF2Sbk;9adYHjlRRLw0tX6xt
zeV#Qo4$h0LH|Ievo3+SB&uk9M90-YA))fMIEH#~1^I6}Liv_ILsf4|d#iqicB9@ra
z4#h05voK%6Qk;ag%dEyN7^f?&yn`@U${L{XV>v6ER<R0}Hx-&zvi9u<R>c|=LUlE(
zcn{28Wj)wNLDXw3mKx}FmfdlH8decSn`>DHIzZO3j?sV3sAu^+0@lEqu?psIvQFyJ
z*vMK+MfOds=YPP+G_(A9z;3bPz6Y&^6&420J1i^JgtoHw(1xvzb#5tCx3fy9l)H=N
zVx`ZUb+cXwMQabMun3*G%i2@{)?QZjG+=$KQUyBG&tg)PdVsaE1lWDnuJ-^2S+6xi
z_XE~%R6y~NHM$U5hFCt7(0Rn#OG&)PEPGmFp0IjLp=^Y8oXS6+vO*&;c%v*mLP@si
zW2|txMKjL&ngS3LtRs|6n`C9xL(qX;Opm1_Tf>E*GkY6VWgKApFN8A(*+L$=eTcnk
zCj?yB+o)>qFnj$Ou(-1SpfJ-BcHSpoIm!;Ef@^p7FSPOUV81~Jj$>?}pTT1DW>201
z>cgJ77N{?qO$kvywvdh!{%naEoe5w!zl6>lXYcKUr6BgY1#mQ&o!$w#5Vm?Y1VY(A
zQ)o1d{V#ngD4czY>S<1}m(Y9@$yU&M5XCN`0C+U}hX#O?Y!yXVPTAQ0Z$mzYJ@q^+
z#j+h~vmM9oxDJWaY)%kZ<Jqj2K|8~aTaC^nvN@>`NMhHGz(g`zs{v;Udk<~+&aykH
z`1~Au8P%Dmve*6tW$EmqEf|svcJ6I}O!odw5IE2Ng6iTgux&yX1hd(FRC|`g{$B}r
za@hx8MSt_yuTuyspZ#4aKmj}cM<~6-X0Ak^3fUYwvKFyt(V|#_cLOY!*<Xp_;T3i-
z6?~Sm`&WadjNQtB>I(Kh6i=&Uvvr_Vu>-syca?3i(K>&P-KxM~TxY8(m|4SqOfzaN
z`=?I;>e%i*(0zlwoKC|HY$ok1Zn6ifA=k*>{}i+)wz3i0n%Q3tL*N!WQv%v;_GfhL
zy2I{$7OGp>i=4pH#+Fbqb~~Fj1%^7<-`%8Ay-xNZy;VK<@!<Ylc9a01m+gHEf_?1w
zJ^*V!yPMved+b-u;2dBt?}xVg>~Pu}4zgE%2Jn#WhoI#2A$BY6#vZYk(uX*P*-?}#
zd(1wT11%$L&QoAd*)>{#QMRb>zYi9%W2s7if_;D<#7VY+J|ybEc}mp{j+_H@@y3Z`
z*9Xj*<4);=gPgfV;5@|nhbn4ZIP&KqaG2A38g9FCoJyd~jq}b?48jqPum*0sb8@8M
z^x)XXfOd>i{SS0{a%ypMwoUiqL`(<Kn{#IY)cA3>{|n5YQ?MBw4dC?d0(P9UfHsAJ
z934eCgE(uGfCY0tqX0t)$8a9bgmQGg5D(`}L(RnW6P$0~02aZCr;SM@XCep6qBz=1
z82pnQem-0~#d-2AyqFck`I&N<ah!jBUca^E=f6KdV<M+;Jvfs%pYS1`!ufkY1kQ5m
z=uJ7t8KnI|D(4q^C(}4nUxF{`oY3#kn8C3-hbQ1XXZ7<CzrdN72JtLT6<v?L$k|Nm
zdp73+6OB0>AD@U@OKiP=gRzKHoCQ$K@tBH1F5!$*qWLoCWDE>k;r#O<td?@#qf3Ql
zoUM03E9ZQTd&AQ!I6rovv67>riyT#)-vfbFbD}6*f0eWDze`4(H`K6tos(#SKn>?!
z1VAmPrT|*%Ie*&d?AO34qO<r-PU$aTZRB`S^=cERg0iX2oLD+=+~RDQ0_-;DRa$*o
zIE56$y2JU2f={iS=U;$$8|OtX?6z}!sc5T%<4>W~PEI@3-ga?j(q))#&c8d*_a077
z4&?4~7W+{Op_g+=5BWY0>kYIHaI~x7#eGhFIIuxZIwh|ka5mS&?n6#Gh17>Q9xGtt
z5$D2cC>`c}v>!?zbKGeU`Gk}IKZuWTB$W1j%DI~hFGe|sN6|RO8A*k*an83oa87W<
z`{?TFBq#P)sBz#fd=E+;xsomjI&r5x0OrgM+ydGm?n|Mt>%v|C7W_TT{hSI)T)D@O
zLbn@tuMpq}S4cbXqg-b)=+14a1n}TyybXiLxS!Jl=gA#-ibiklv*e5qw+#VZT>a)w
z+=rka_v&U?^5;IL6)J%H(@}uq+?f>l3*=6J89oJZzopP~FgM^hXd&FXxd35YWgx~W
zocjhHbx&}Q(4H)U`ym~rBDqiA1ucr3O&@QF=5~d_?n&-)su4KFRTV;~Ery%W0Aeh+
zY!kp~u4x0ji03-d9_b8seI;B=;QH!dDUo|?DnJtVJ&M33b2I2iOW__pj2@olF6=_%
zIWBK0#8bH;^mt`(J7`wS<n}KH%Xx15RycEkd-DkfA&VPD1sWG^T;!YZQgA=m25)k>
zr{4z1<z`WQE{_{ZOG7^Q>Nr?0ad+&2--X;23N#jRH&AA*m}_%KM@zWR()YnGb2lyl
zxWawqcXYIrTe=DYW!w*`My8yrJp)<=S9k#8Rorcl;C(gM=CKW}SGjQ%Hn_&UT?)bL
z+znh9tl_3m(QYl*oC1kDZug()%nh!P66*EbFTVjx1GkhmE{)vj)c{Rg<sEP~a|7rJ
zyv03p3D|A!lD`33xPQ?V>N{MC7M!iz06G-6abs)`(Av&TrB$zk`*0PU>gMh*M4x)N
zi>HEimn)$YRxkG!CARyxH|7KMbBp@n?>+8@Um-WZEu*Z=eeMVJQK><$ioP}YfZIvm
z2_E7y>2l#C?v5(>JIw8*>yMAQebo4bd-f>3#v|NVIlxn{`Vc%F<+{y>wlVGsAAQ>r
z+xG9#=EPg}Cd8e2GbmPbfLGrH>>zJZ2*4rUV|qwjc)=bpdzkku9ok%ZVIM<@8}FA?
zupH&RAx0zq{aF#Z;=v1{D-6eYJ7Xc>$=gE@o)@p0UTJUM^ECJP@M``$6Y%ESXeIUI
zX(-R+&+DRuN+2)E2UrmA^h|UjnAb>&)(~E!Ge9VBKLa3)w{{NP4(GMg3Veds9|sc=
zy!kY-MDm0T3``U+U>KYyc_upGoZ`*F^|9$OyiCeQ#`5k_s639BkxcW`Y2G^&=!)kB
z55So-JO*vx6L|k_21w*ROPkIlUNEgXDZI6GUOCGPr)r*ayk)d7rSgo&VK<HU@{8zp
zI`8)quw?Mo&=+7cdD-;O1<v#K#6k51UeV`Z$>P0C;lXU)Iu)(XIlQfju$0S7rDS&=
zPf`Yu&s$C#hXUThukedp;w`R&i9+6o9sotWiC<y2n8&YxPbIvaOz1A<y-YjjGG1~k
z1j>1*r-HMBx3mi^l{|L_3|8@0?tnAZyaC!RUgiCc$|BqJYrNclAb*{=mR9f@-e32?
zTE|;=06o0H>-`k8dR{->RA}JM-42$Uyzg7U(#TsL0?@>J*N7o)=53z?-M4t}k+R#o
z*FQu@TX@cCU}@#KH3PKqitFG^JFln|v<}{^Gmx`&@*HT%@8bE~Lu)thm*cS1!~13f
zSnu-wMis>LUfzl+VCmzf`~#MIJQKY|13dqAuymg{;7>0FZ(})Jd%(Nz0Pv9a)+PuH
z@&3+)Pmg$+t>7Hyy}SwHk9i#jA@GD(xDMt=ZM^Ap?ik~_(oZtZi&+7l30^q`$|iXW
zLjWB3so%h$Bfo+?bmH%$uf;m^S^q%(06*Io;s^OZ*kedt_+L|S|1f_MogiKL@6jRE
zjsLO(IFIlbybEWJ^6wTv+@1gEC+PIx+n)Or9X-ZpMS$qZ_ox8Ti{C*p6d(S)0`U0q
z<4iE&$3K#W2g08pdKrxY{MA3g-{bt=XMhFrZ_~Cmh`;I#<bwI0t<V|5Z`%x=q5Sh<
z7>jWJ{0Mk)f?pv97Qug(4=j?u#g+mzir-WN6Vd#)snqQxUq|Kfr}$1Z+r{whXloVA
z52WCE9DfC^O=tL5DTtlGpQIytBLB!==x7puYZtso=Bua#IE9}<2kx_c#|Frq<4Y<0
zmCFC*G_W*&@>O8zd`=}rhcfw-lw&y054j9*f$vFkLKZ(o0QrmjU|Ke_`L-*to5SY`
zK+EN4Qa~_|fB$v3md|&h;9UX#7@b!N`Hv~QU&Nmu1P_b(qTK)`{I{cF=rZ4p*7qy?
zBD#fH%8xlt_2y;#_rHUha=!I@uvYMWUqhcN`3p;6zM7AyGu{=x1Lg6r@xv&QaGjq*
zIfEL0SqhZa@?R7K)bZD;q2&fY_yBa*^E-oqHSk|-gfln!p)v?G^9vur!(057uLIoX
zmm;2Mo8HQQ1>v;mZTz2>q4(|lH8hree0xtA?B}nhlhHkX4&5*s;CoZl`#wL}2r$U^
zrWxV^KP(O=9`Y|zjoT1^o(w&F#1C;oCx-cx^r6JZ{7H&MJmGVwXCwShD>$F>eRo0J
zHp*X2E9@9wHwAXb`Tmp{oZt`8`!~ryO=(#N!85-=!cnkwCpeu1_QmL$vq1Vg8V?92
z=b^s`1xHlq(;>k$KKkM!m`b<x4hv3F$)>A7NYA*N;1DIijtKb6F``EWk(B3lw+SYx
zqaK2)kD%t5;1!zSJOwTLA>k!po<yU!AlC<&kHE_cny<i@YWn;HRdhu67i_d*@B;*Y
zoQ9U;f)6Rn8Ytk?S{x)W(9aw!SWofE5P?e)w1f(@G>3%=mQ#UXxWKlX7V#4T|NCH#
z5S%SWYouUp9h621eq0Wv(E{~4NSqX;1wsCl;LKKV#t0%FfhAV(<zfs;oS@?afYXB0
z6#R}CETur*8G*ky`kNrAZotSS3Y;C_c9LM$C*VvLY^6saMZmOu0E1@*F)Xm26Lip*
zy;236g5Xn{ppCKw>4MW#l9(Y#q+Lp;U<s9{oEN;53D+(NBDX>yOYr5dXv`5DW5Cf|
z!55B@%M<)WyQ+La7!?Z?2=vKdxg<!YTB1V1Pz=P21Z(pCi!}+}_y|sw2!cDodRZVG
zfTb&f4`}W!6^v2+T$x~q9=39UdJ*I+1kH`GTPf(+0f8z(Fl}3_1@o!I`>Nox;}E|l
zVDiv-T~K-ws%r%MD49|#sN4)M>I4fXq2-2PSvTD%uNQR1qqRZssRR-?1>ZJ9O{2hv
zlDtiV4~Aj4S@6&TrMCoC8BlXukh~u9ErMU`;l&-n+pRFsD)@I7ur`5-f@$r7zs^FS
zLvVl|k4}NN5VS7Aa3rv9!KojhrAM%75k-gY3gU~=(Oy9=l_vEGs;Q!+U$9gLHTML)
zf5Mpofn_bQ`-0T-U>Ov2(T@6oz+nj3LxF`-$3p^c5m+7x#_M2rSn$mrc=%Yby#_2#
z1RqeGVMOpbb?~X+L)tu#3gpkB*S0Z1KoWSy1uk*$VnVQzs>CJ*4pg!2Abc$X5{|;%
z$H3wwT>BPSoP`Ngq;^2~#XC@XP?$sK{zJmCZD4T`TIdt7hlS&FfVm3SoC4-1e9Hjr
zi14@);HWT*Y8KpuFCK-Xo;Kn59hmSEo*zT2x9}UfHsT{3xe80Z!nLy@;U_E?L5;uA
z$sH^K!dm)<+Hv8=|B5?=G4!RfAmIoV9Rv%{&?YZLc#H~dLxp?ky$=%}rIb>*@cCf4
zeM0z+6gne>Z@z)vM+$9zcR-91c2i6}TG*2Wo|D1_?}O)*uwxTIjPTe@JOZ&o>x*zS
zPI!Vsk*9@86tRjIzN!K3jIi}N3_^l%$Q3M!!n;|(l7xfQ?PTHfVQ{7hJ7+@mS>Y7g
z6`m6&{st^nXt2ElH`0X7bjV2;{!LY-8Nx*JDN}f!BCzL$Wpqj5f^f?7pk)bHehCv7
zg`ZQPJzMyU8Z0@&bpyb1g&)wYS0H>n5(1ZmA#^FCP`E*bktq`XLNi3MaNCbiT_T)I
zbM|GS^<P^5t_WkZAzv!&a)n@-P+AAUa-oJYC>6pz!C<Wv?x@F*Rtfj&(O50adLG)Y
z3e)C6yheDD7NA<;50w9@6AsWP5pD>_D1cip{5=bt4Z^q9K=n=G-*h@@6kaQVmL}n(
zgt8;e!b?>9b4$2^Hi@@|Q}8#vMflfe;JG7wEf`p<u>5&|HsJ=kZrCn-K%f2Y5U!<%
zyi@2p2+$=oQWb2s@VSpc>k+<s8*bkf-kAxzy}}2SaqJUb&_TRk*gqAH-V+Yn(~a^0
z;WSDd-537NgW#YrA_c?;!r>OMJ`_4pAZSSVHYLIz33t-R6^Dg2R7Ubxm|_Q?o(O-Y
z&*6>;Z&GmLsqik{o*ESnQn+wTnBWeb<H8Gh7=#Jo*Pnr9Qn=0ot~rR_qRSXIN70QA
zusVshF2=Aqi$=R4aX@r{R>Om$FX%BjB=VXAnv3WdrCbh+WZ%J{tH?$v6E{)ret2<2
z^yRPc@TjPTb`9>LPH&8;hsgUyh#wREL4`=3qQz7g>?JDA2F+Wvm$Gd>Hqll&wE2qM
zrolHq(d|_r`iq*5pfNzCq80DBXg#S36rH{SOF<(4o!|@>{Y6Qz5YfBe!;4VSzXM<i
z6J2S9(r{5C6_1?|oucpiM2L3L3L7c9z6KsfiB@cZ_$g5~O$IR{n=u2HVnuUZ!5Sx8
zbplFHi)PuOF<$h;D4aPX+H@8s5=4i^z!F7!a>0@$nwE{mWKoY1Sc>RP3Y?u4CF-E%
zoJc?il2p-l4`@jf<(C6X7agU!H$(LC0octHeMAS_^P;)7XCZMxRR1~DWQpG11{W`i
zexO46Y*9}P8goR}*<j5TaX7&8L|TeS=8Lok(a{3YC4YcRqMp6bT_|GHt<oY<7zH1T
zMHl|Ykd%nFegWELk#H2)6;aIwSSS@`zY1k#qQE*@|H?%k89*yU_4lB=Qq)D`TqP1_
zLR+=SjrPP>MeC{F?3(Co2s(3JbjuYU)`(`k2}`x2HME(o7tNrYV}nQ=18`IHn=9lR
zMHLmW&?Hh(5n8jzM4y+qC0djRmfNC&PTGIAh?Y|2_Z?AU7QAQ`t=53pCi?s<C~X(z
z(h}PtDmw|EIz=(7(by#l;{tSxwvGbyh!&cl^seaA7_eT^8`)6SC%P03E&Za^p>X@2
zXeuo(1EQ03)#AP=nRZZvqN3O6pAS9|MbKX2p(rsIT^kaupxDSGQ5xl6hecOs!u(^=
zfv;iWiD-8t2605x>komaq8FBfHY&Qa1(wD{Vv3ZEiwa61HzCTPlEF#Qd@3_`5I>;O
zbVsp?5=Ktq8C0X~EY4{K&2~V1=W}Q~D7MjM_Cw-^b#T!|{NQa!92VdG6n0(3zy1Xl
zH}UV!V1SN@Kc_|JsCevsXmb~bQKf;0c!nBs$HXzsX!I0sy9F=2#NiBZdW&B_58xy2
zqX)uQ{3V?a{KRP#X7aa*Q+|b|0PzaSNgWqYZiAXY@vNm#8YKRcrn_KqGzDrx#A8>X
zCRE%(HE?0#G%C^x7w680+zIhE+E7J^bGm><iUTQo93^J>0E-qY|AxRx@xgCk{*?Ft
z1@>daE}rPiX|Yf7(95>ZX$ejc|3g8hL~*(jMw7%3sSG7qe0UaArHB*gH9sqM<N}-%
z$3{UoRXq6~Mkh`D(K7();$a6klp+3tLJXPW=|92tdGQiTd|wcU{|zl!;x_u>FNz=0
z9jI)vE(aEJ#9lTE8|I2HQ1m2EJna@t<crM|qAn08(U#?s_@&oiqELKb3zQa#f1rUV
z7Kc))X^Hp<O<9-4QB1I05!;`GK&jY44`<56b#K97x%ejzx?UlEsR|Y<#Y<@4R3%<`
z6h2jpJC{-7{i^s3-Gsj;ZlJgQy7*8uEY*l#q2j7q@t!SUsS_`uCHRK8f}V|f@r-V8
zHi$o^3eYC;P9++f#jo#%(p%zJ<^sDd{`C}GYY}rO?{G)_(J)+V6@NDjXWGP<OW|R=
z_~Sq6nn#DYk<O5v;_2jYmv{?p#Jk13Bk;6GTtgL+cg3}ID(Dr@Z3gHQd%D7Wzc~C3
zwA~YblL8Y1;;v61a9^DJ5&Rt#zeXS5d?5Cq1^J=)&y_GgByKYUdnAsfjmNOK9FbRi
z)kv&PhutUQuj#BXBF^#x@u~R7-Dn&Y&*??un0S6QJRBFNQ_aSNxPf{xDPHakgAS5o
zcL5wF6|@O-lBCcP(ph474{jfjY@xv7K}pbRV232zufPiz$$45m4olprpxEXr`GZPq
z-6R2&G(IAUIRXg}Nf>1)k4ZZA!V6Ey`^k{^l9bbC+gnmG1J3wJUP(ZsujK1q42hpa
z@e1VpC5=BqcYx&MzoGlM<j?m(3zUpshlL=?YU*dOByk_G5XmGRphInvPkumuPe`2T
zYD0u1n2t!1k~YdcL`mL#8GVYDBvFLoq~xU&P<l$T&k-hKBwVWLjg`ovpe;_akk;(e
zlF3f^6fe0<$=5TI{}D)#6#0RcDCv9-y-$*OP^u+aa+?FyDH2=l%W&hYWclk5JSX9e
z0ZWyvqGv8mvcLvs(j_UU(6tN+mm=hu5<?-hotHRMh0X=Zzjq*)C3%%Dl3kQ^(o~x*
zv1h?Vj-;Ocxo57#-y0xLV%-jwe961?SQSXrk&wG28MRT$tx&=nNAHUy=f~h;vE&lP
zqe>)>gTO9J>ZZW_70LJ?P+BV4#)Uwcgioiaa>;V4>aUPgUjwaDvStDNt&(Jp!^Bm|
z$MhwvYZ8}d0j^8t(09aYB=uiFu2yoJO8@F4UubC$dP6cwnU{LWC)Cjfi7y3cZc3_-
zV1OGXI?8=DNgOEL*(}K?!CMl`40v%H-+P7IEs{x!ezZyE(jAU=iPITyc1S80qp?%6
z{vgD=Bw5Fyvs;o{4uKxYr!<M&m26y1XTV;`13&oIC;56ky4^2{TMnLkl0E^j0m*K6
zxPM<V@+PzmN?KZ==7D4bm1RGaSf7WQA<3&8G(M7i{vPCpCGW*S;ISl<0v%5z?~MVB
zNcOG(?WttJ8*qD6l3{_eG08tiX5jrBm-tt}(uBnKINYC<2oFH1gEV9mz)@<TbB~iW
zhQis-(v(RE9*{=Trs$w_=4()TNV+~1G#BY0g>Vi_jqPA@mA?NkFgNM*|9!_)`swGe
za8$aSLPze>xwI|tkY*%7+;&WQ<0iCuN(UA}!b@si3Zl1EdIml8k;<b1e5Jj)0De*(
zodf)(;*02Sfb`TUbnUpbZa2&aN=N7k3X;A>Q%kVaOxckTh=Ud?Eud>sVba}HBp5Dj
zrO4t5X~#;~i?B(1DVi54on8ypDCq>{ETW}*@4?_nsmK=+r=&&|K#bIrKJ6DPE&LJ!
zanilCl%AHp!h!ek(%<Q*envVg2uc&A9W>h}O8ZiQB}w}t0FtG~vrwHP&AtFbXQiWb
z3OXmX@#u9-l^&xPK27TW46t<R4T>OVNac9|nNnsCXy>IhbgH-@-FzFCvZQI0?6@dx
zrF!FR>BcX>nInw~fOxLd-3oy`DdPY*^QEJI!21HJKRv5O($|i`nPO>-0*xh7tBt}n
zm!<dhkhmi4@&~b0s=fwdne?PHXyww&ji6OX142Qolr|N^Qk68}AM~(V>Pm;VtI{SH
zSh^<t@G8J{>4-n%YNRhU0n|z-@*z+s-Tx5gZ%D;-xu#wkHUPI9q*)f4VQxy7kAT=H
zT}d}Mo1|fMNN<*2{t~oX(s{ILzAb%N0Kpb%D`j);NEgn9(pIVAGk`Yf?RDU6m-^m^
zhaFP8a13y#^v(C7vrGEpN_f#NO_=~okF>%EEO(`K6q@LjZaPgBI(^c8|Gjw9=ELB*
zCw-|8UJOW&Q8?_rbRJdU4oXw$NqQjNK#R;n>F8NFGbBx#25pa|6W;+FmcI2l3_g~=
zN=LFMQZ?0cj7V2Z!r!OTo<S%Zl|G<I`Iyw|0iVXDu9yXI=U-a15K1Sd-h2o;$mUY!
z$5CdXv!|0Rz8^k0%TAs};{jQ^Bd~+A7JKMEB)dfiVHeq#e_{|0%Oa>E)m8Q;eWA)t
zrl)UU9g+P&`;()xpXNf`U8bWWhKDTeHdv0yN<K%U%~SU5kFe_{3)l<yy=A>i0DNTK
z<6!lbnU;X&FMEexjsRKnZ1{a#7E3QzpzJw2=nj%yya*61o4*2$A+k^^vI>=Lql+eC
zvR9U&F<ka5)yABV1;hf2kWKs-{g4GM2TPPqwt)POmbrWk6DMT{Y0rI1mO}-4F|xP+
zfwoxLZUsg!PUb8@w@=G1z5!aiOh>1YGqTBiuq4RtQ}!)U*8Tu2NwP%?p(R;n34v=V
zve#+$IV&4$0qvY@1rv5tWySkpFHL5P+6pvXmVFV#4B1SY<uhgOJ3u@yyGc3w3o<L!
zfn~``9Km@}Hby40WpQ-+%8_|cKsQ&m+7now%t{^2m-$d7RDtY3J-{Vd^>ipJl#R`R
zhefg?it-f8o~M|6iR^D1&B&K!@Bam!Qd!UdOq9tI9nn}W+emrp3RzPvBr0XaMo3i2
zQZK+@wd~(k{7hG6E2-Atn#|)3VAo~OQb|ya4F4(sFP>~oJRGf)J^KKz-H?642CZJU
zWD;5$WY6b9;HK=2r8dAu*=v75qDl6@U|4FF9n?VZmhARh==N=yjpAr6vN<&C-I2XD
z9okxDS8hPAO%_8Z*ml{^bP1+I#-Wo+r|dB$<hx|E$DyoSrnmuRJ+kHJVd1Xq2$eAP
z%8t_wg+5t96<zc1m!(qt`=0DK`e6rT{hz|bec2_t|2-%xT!XQAAp4dgSPx}!^eM3+
zS^XCfcqA*!hQP2)7!A9RWhoQjd?Gvb0caz#uPJf+RQ4%t-bZEHKhZcQ`)CWi7?%z2
z1?Pn9Kps`7PRi!rgi{Xkqf6nbqx?s@o^e3F|G#Qz`RhS2cu2l|2Y`$Gh#cUs{OtPx
zuJRx0?C2(ECd1z&a=TQ3qw;f9vEVK*mH_jR+fk_OnEV_au07>CIs<sg-=MEidCPT2
zfZ2TH8rs(R%6TuqQ$P93d*F<}Jlr2V0rFqzj`wjngKk0w%2!o`B}o4H5||H`&nW{4
zksqa9aH#yrx1fc|XVMlZTy7o&?S#Cw0w6;EVFEy;{L+3Xi;@@8n;I>@MIqReHu*jZ
z`ka#YQF&sFylW-oW965&;)jisFB1WrmhX8RAYPtB*E194-ETuplKj|v5J;BKdmD`@
zaxYSPRxY4}!8!T5aj>My9TjjpO}={{#M9*;B?4r~lj$MLl>ZV1pU%r|zrF_f3-V1n
zA($m!@hQMX`2#B1$(BEJ8ftRnWn*Z}m8ZL)hk5dSi_w@bPomebKt6@adoRg<PXJ4y
zeD^twT9MrQG)BExzKl+TCGz`JXmMF?aRPQl{`@A$mC9RdAW$Zcve7GEF4yb9Qz5Tk
z2osg^8FX~6lGiyxO|^Xc9?-7JZ_$4Hnp_hF_pi&fF=(uje?fC#t^6Iz-Pg&RR)cm!
z&ZQVky?h-lP7U%8E@NbF%6C(0tWh4=0=rG}wYS02ET47yTbQ^d|M?iS-Ih<fK%zxH
zLCM`a^6eME(<+ZNqp?k%HUs9{<x(X~bjTkDfYvRK%K&GO+{1+7x+{;T0q&K@Q;4rm
z{@Skq{qmlGh0jiX$F{Q?au4O=cVT`=UT_|?NAgwuus$qzqX_O}`A#Y^dm_K|7j%xu
zKbZ}dr}B;W0Y>HVw9g)s`+7plxLiy>$b@{-7iK5rUoau=ps1&$lA}U03q$Cn;L$KU
zD>lr=z#LF0ZIlT)sBooGKcsl}IxrVS@^$Dwtk^~S6IaFc8IX5VT%uCTBZ?oXuH~r0
zn~h$(D-PEJ^H8MGKKYoUmbOmE74rgMH&Ai*S%4sg<!5jPD+F|23{kk@b2`&Q6+={e
z7p92&h!QyAicFf=PAFFX1S~@F8l`F@6$xH2AEkIG1s1KC-3E!1is_G`^pxVa??H=E
z_$Q+mv5F$96^>IJ8%5)3#h*9eOuS;i0pN^c-%bc5D5@zeo2Xd+3Or0wWPbsWtT^;1
z-R4eF{Iw0}S;dP~Qgu!dNSlXLMI@Coq$wUz1zWm8MSK4YMKtBtGZpLTg3)=!p*85t
z1x3PPn8;E*_JoOx3N5{G*@}<8hWQ)?mx6J*ifVT><|+QBNjhJVM|-V8Mdy0DQdFey
z3PNkK;w#!cmnb6X4&G(O%$<<GqEP({TB%~Y5^Bm6o4y6DT=BXUSfxVA085o(X&2<G
z6)#f4=&B;=3cxkR_B5Edt~f#839C`88bM!b6~9pGzfSRXIKT}>uO0dlkow%zIkw?=
zJj#uV+;sG{Nm0HJLbnwIJ7A?nVNe6KDw^^k)TS8z4j!~CvL1n@L*Yc}_fEys&){U2
zA~*|Lx)pmV65XTlvOw8gMLboy^eWaSz@I+Fdg@ibVl!R4x~KS!YFY*q!L~*yy{~x3
z0EY$@3s9dq{edEm9@~cs{t{qAis!?i?UADG62P$H>tuk(ivB4u_(b8f9IlNh_EA*n
zsbX#?1V$BAh0r;s$e{SfxZ<}}P(7iz%EwSmD)J~0=cts@X3<HhiJ(1^vvTQrICV%_
z5&@!%vYWmDd01(r4YaGW<PliilqD8eI-(SQ4B(-hjZ(Vl$CQ>iVDVHoZUu{vl1r5V
zzDnmSVDVG#mjLruy3+3!pv<lV=W*q{g&5I5W#0R+5Tva7hw1@?mAj}qBt-csr3ylo
zOJ0C{n6i(eZ{f;kDByKMsqg_7p{%CYBvQHSF*u`?-+usqqm|-LfRoDVO7!rQ@;SN&
z7^8HjRXJAKB7w3v<!`$|JFQ$y`RjP)3_4((QND%SM7HS(%FR?alc*eug>Om9oY&z@
zvhwMNP?Mruszu{j<*NfQaZdToPry=@%V{M_Q_ksy?sVl4Da}x>tAwMO$`>hObY3~f
zfC0Lo455&FmNKvrIxi~yo`=p{<z@;f<|)6Y&7v(|8L$-Q3zSp81h}Nk`53wjmGLRS
zij?nWL20q_ZWOv*qKv-@a9J6d2bL>JN7_r3DxGL=QKpm{0Lqnh^mT>`<%<;HtyF$P
z*W#*_dnig>t=zBz&RkXcs^G;nrQ}DbzHU?A&w<h!Wf$$(Yn8_$Ay}u34F}esT>Bod
zo631qz}2Yqr#(%R@)J6%HY*R(9Cu6k#~QHQR_?wA6D>;LY2du041IzgwksDr0}nft
ziH@+_sbsr@Wk9)O8C2g_E~gO4pwfopC?0ZU(HihPQeJ-<Jj2SV>p^_1eBmZ6JyDj>
z(l?^)o(pVDd5X&4$Cc;j08A)neh2|aRfrAUc2apPfEH)fT#C0HP;I6AL<dz3-$U6U
zRX2I)sd|Bq)?TVLd3cSyRS~uoFz=(<m<hjqRn<AL<foGE0?}XPeH<nNR5=SFcwF@v
zjclMw_#!xiR815*4_5t4$Jr3o1f6k1RsM9bI862WUodz=^$k525vo_N;5Ud={X{{F
zC>59XGSR9Noxo12?(Va}e5`7V9|Yr6t~nr{R`vXMd{@oxhNov#ztBJ>sAj(kONpv!
zRFadVnk<8SvPzQ<ffUtADa6mJ*3+5(oGNS{uvFDotHF|{TD%u5>8edsk(Z&G(+Zz5
zRfp-Dby=#FV#;^qsIqE-=Bj3I1jtjpGX?Vbs@y+-6{y5rP<l!Am{O^Qsx~bKxJb2g
z4U`tEEKk5$qRJYAqnA~sUU2k^YMkmKN>%Z+pDk0>(AKeBl|uJ^D^%7)V5w9Meg@T5
zstlCUy+6HLb<PCzs>;3=#A~X@bhEuy^>!3Mv+7gS`%J&3Vg-Ej;?(&|L#gzsRmE;c
z*V<LKEzsSe+TDba=~U?gyue}`q$_22RafY1TfM694}zs%_44<ya8Kpr2A>908)+AR
zUlmEiHK=-$3JVWZRg|xIsQRt~jt;46|AqBOsy~ha8&;Llb>qjXZNH)OBdQ>Jsh+Cd
zqjg|Z_0M0Rjj2ASYP)fjhmD0!OsJavf$mAw3IY!5GK#!9s-r0C;H3V<0C{Ki!apH+
zK<!0e_&lh-)&nmNskih(sf)UJFT6jjX3~S?s=gKsPB*pi1pp6q(pq@oseX$VelN9U
zCOYV?PNF-bKI+*{HnjSxzo0O(pL$^~SdXi{n$ej+^_noyg48oP&>gHUe;2e6bpvIm
zLe;Bi)WXyu6tfIh+c)3`J)vIoKD0!tS5rJBO8x2pSfbVQL!j)Wdj3}sKc!y#F3iWM
zUz&j1vFa5&DRv*H-Vp;er`5*&P!q3y<}FB^QJ;7QY7*4@OaMu0FPaRJ)gvCjQq-^6
zL(N(BUAoY7PJNt?Ice%U&M=s+{+J@R8S2GUu%D?uc>yfv)z0ydyP)px1eT?aBzxIv
zE7C%?={f3^%^0>^_0JNt=BX3tqjmY}Sq${PK>Zf&xG$*}31H%~dd3GBi!16SC7_k6
zr%?{GOg*fF?s9eRG|(#5>nW5_rPj8AR;~WG9<=LfD<9%DYAe<L)T$dOI8&z<>_C@n
zH`K``5NuGds)XH}>P>VRxKXWOK+P@ny0<~Qt+tubnHKd=Qy_6iok>BsRyDr>0&VKI
zmqMUjJ!3yOJJk_^;OtTlQI&bOI`;->J?fb)@Zzqzj5g!F>dtI{KJ{P2=tRFwy?GZb
z-BbTd8Kyz?wt6UipsuZenuqGON~jr9FaH9%AF1;@KpR%a)8XZb`gh7&ji_%^GVrNd
z{VrHW)k-NE$JE8&LieQlnIdpHXkJ+g;HY_F9vYoAl_GfWtXWFa@&S!4-4EsuX`Y`C
z9v4l2Fu-9=$^ckhHHRn^;ikDv#RKk|UK$w>&E9mFIHviRs){`|UKhdQrMYSk;H}x+
z4RIe$GiAbjHH<p21ZW<eLE~{v3PnHyHAVE>2WkB2SQe~VV4H{5P|c(#B*HYiXy+EL
zNuda6gl2RO`WvZ<uYuhtjmiy!AFY|Q8Rk!F%5Ff-DNW5gpv7tgbOR_(llCkOp4NPB
zhsJo#H-2C_qxlY7*XaqGX<aawq*<~Y_L4R1AJCYhdEr;eot@RpqKdq8nw&yl>6+}H
zFzOi^ffZ^pHB;Zi0H4<kQhCw^P032gXKCJA2HHi<?<e44w&t63fE*3?G~CYBn0i6W
z)BH99XYw^KQ-rxd^A2q+E@}Fy2E0%+D;0){G?VKnc37-wpu3zUn(rw{dPTFh1b&xl
z;^`MH(|ouFo|bFAr1NiuX3`xjl^WhO$X984C=XJt`I4%+u4;DB<<V=J)k!daUGoP8
zS8FulA0SYxxlCK_I!yp2pKfUO{spXF<AUQ#z~Z@6XW0f<LPMkG8Wo2&X&zCTN3&*Y
zD}24J38uNCMYEz19lxXTTMSyOW&!0z+BC;$>1o$IzJ`u>Xm))CTBqi6Hyr5Flu+?f
zx8}7cP~D>mq!OsRn(wUexL5Opw)K6QfF5+JU-N;Dp7wj1*|cF8(6A^Pa9@-DCDc67
zRJKF#p(gl$P&1^-)`9j|bCZrwPc*A91B_@g69JxTLTHg2)%eiNJf@l047bNMCJIbW
zXs%F<c~Y~RrV$6Nd<$rf+8-=1@1(sJNt+R8?LqS5fOeWQSPyEazJSI<+B~XkaM9)`
z!2DsY#T_(PZTL5E-%Y!C7=v&`TSXO7N42gNVD8#OIgs<venyGxV_F>@hCH>)siwzE
z8%_~&Z|%Rdb@S0S(3aCz8y-hRM1ESYZlM0!xEs(GpzWf4(s6BE3bX}k87F}SX%Ah6
ze6V(qb|@j*Uo`L{RQty>&>f~-Ovk-&t+gKlC$w)40Yqu{2;qIS_L)^seNwxPZbhEb
zHd2%)M!WfaXo=PGvnYTZr;VmZ;IvjZ6XxT!%P7v7pdF^!EKyq;2au#qpku>1?LlAI
zP1SDR24~W=OXxVBu08PxUSw#uz6XPu+L&_C&TIYY9DhN(hhDNQZ7yB8xv2eu9*=Bo
zE-h<0+Df`>W6RaPwhzQSZBGb@`PzlqP+Fk9NJo-O+F4X?U#QLf2%t#&Q!z{wYg1{T
zRH8jF1@f1*uI2FXini=1K&e(j7p}{+vGfF%YbEK>S)qMU34uy&U=m!b(&j7&ty=q-
z&T&_5+TTYZaZUT~2B6oqPBeNo+Ba+9cdd3Mg&69zUpoTa&{np>wR-KU8dz%3K4C!H
zP3;=`ENG+F^H<0<Y4@1X?Pjf-9_L$Hys>zVv_*mNqDA`&1GGEZi<Gi#)$;7Y(x$al
zj-jLN+Hkt})S>l#4m_ROpji;?(k`VCd$)Gid0;)-uc#*WuJ)4;(V1TDf@R?B(@JO;
z(y!g)hd$lY-lX+mKr4O&2JdSR-2*nL9jXBKKs&<$h8}8T@*yy!UDg4AA8C_qRDwLL
zP3b@nA8Y;S$oN$IeIc+>?G@S-jA=vYls2w?Jpd*qv@NK7nLeqVzZgm#bYX|l=%`at
z#??s|xd<LQ>+a=3=K<a9XkZ6*n+73%NO$Xdxb317IDzx9E_D=*uDbpV+OW9kPEnfi
zh%T!Z5=V6n^qn4e-IFc=4_(?%kT|Am`U)(by4lt6&`TFd0dH^J7c^`8=$`!@27Ptv
zX!Oue$E9q&zb=o~l>i;f0TzzyEYr}XK;0m%U_rW|#b625wWuhvazghl8?6z#3(vz~
zr0(+s=#J9$&}0&=3)}#oPU_aV0-Vx~T!vtbZutsevAVDxn26H_Q^NSP?#G?b60ch=
zg}-NXm+AFQ(8ZqtEm1e+IXIf6i#-bQWZgOXKuC)2m(eMB|IX^ds6OhPuA9z^sk#@1
zkWbTzDEOJK%b$hD4BaRl@H2Hw8E8DOYixks3%aIn(U_&Pa3F9|H@gu&W$R`~!9<R3
zE`{`Sb<4}qn5VPS)r@@IhPh}g&<#;d_$6KDWzcMeI(Hsgi*z-WP+F{;u>^jX=#<Oh
z@MYaQtHE<ccku(rm+Inr;b@u8LUp#~x=|TeDs<j~5UA93q+y(^bdLl8)jF#Mu3gpj
z(C+1$&VCOBuItL^s92-ZFM^g@T_3$1bvE5?+UeiW#q%IouX}eIhz+`Xp^(3+yR;6T
zHtG_-1+7JQcM_IbbswfdX`4=X0JL_U3%y4jI!8Keb?W-3!bF#@n>K{qx_L76tVg%?
zDQI_fUkJf@Ul*JREe~}2=)r%evkl*e#E|ZtbKrTbd(jPjdZM#?6TXe;;%RU3RHr5L
zqdHdyu#D;68UQw~^Y;gBLbvxzfJt38&Djomy&U3>`T;pGC;cxJiE!4t(=OtGes%}C
zbWndV6<!?De|!zVMZe1SH<TXM57P<VRe$9V@VM#USdFe7(O39D_fdT`mFKwYdnmEs
zp=UgXwqyGJR7B#bpKXUmFTJE0z*~Qi9ta<OETwpT^_#2E=%=sR1ug#g&(-K}fIeRY
z@#FfaPhcTXuWYjc2I;@1t_ACxzJyaD`kxbEFjPN(0uo{R-L<e3t~U=t@Pt0b1f>yr
z!9IXUz2RpxM(KC`cizzNR{=YzpK}@`dP;99gLsU-U>X`@^>_GC9jCwg3Ho_jzvUZ%
zc>OaA=>0pRzp@JsC+H{Ngfofy0eZKS^#81fPs#dhU&yEEPkn^Ov-&S+?{`ign+Nl$
z`s@VI()7ZWprz}VW`dTX-*g{xnfh8Iyg08{WC6RNf1MV-EWQ3G7|PLeL;$(^>fO`u
z{^jX+u%RYjUr&|S1^WNFp!b*bOQ`&{P|rAv-WTbY{{)s|{c0!lqC~$i9xRvjRg^5b
zqR*uw=~8{r26$1X|4omsmFu&pzP>^~gX*^{_17tuR;3SE0`Y47i!_B^)tAnKJ=-<?
z9XhLC*H==is7CMdIwWfKA5(=^oxbZL)ZEbjQUg%0XV7t{LBHrQXgBp;fl$+^mtBJS
zCjGHHU}@I7{s7u7z0HKNxUG-Q2TP0oeHB>l=vUCR(W-x!%C*|`E$Oh=Zqu)&rK3xK
z^;7uPt^bj3t@P+sb3nYS|B52Pz50|nVCmD>M8VO1y_Txn?&(uaU>VRaxP-B|ub)k+
zqCtHxT?>7nUv3Z1hx%m;pmRvCqu}%-z004V4eMjNFhGy>Kc9k@Cwg1-bg+)-3&_)_
z`Z$U%kLnvJQZ=SOod~7l`tMue#e{x79dIV~-FxA_gQ1&heH;xP;b?R+jMH-DY?uf{
z;{n6Q7oqH+p#xLQ^g{;E|G^6vL#+cE4;$W10dO^J`VNNN3?>_80gf2Hq2TOM!;mA?
zxEn^ONWsJ4wF1~NLtZZodKwZA!jhL^I|T^54K7rm;$!&bA$0p1h9BUE@iXkF8$A97
z+b}qf8^(Mf9%#^f0G1#FOA1=BVJ{suLk#9jfKbDtd$d0aGnhAm7;eakg~SQNO3K4V
z7{ujhj5Neh*gwiJbOw#lhC>t#J85{H(nzNapHhuOjG;XST4D`<$-ok4s0f3WGlt`9
zVK>2`4uGXZ!?|Gin`GEI7c9w!eyV;=G5B1hOO$5~<v#*FXK?ZZPpW}I@)?E$UJ%SQ
zh=MUd=MA|P=+i}mn9h^ghHrD=T8`n{S)k<_exe6C&*1w5uzZ6LjbVY|Sqi*fGCVjB
zTA|?~g%^tq>)2o^Hu!%BP-1xCMwdt~8{U`#;uXWd+h8p<cv9s;nPKK#fO5lNE$mhp
zvS@=}Y1onqtjZu;1I}v0vS%T8)o^<{z%|2q3Qb)%xKU8H#<1c(uv)|NjTo*v!(K{s
z-7rX);H)>OwnJHiLH+|U+f76C3Gg%;rmO&HGN^aJw`N0OBET)f9Xh7mHZ;<?uEpR^
zwTX8OO?-e>gWEwUZ8QA-DMqc`;PxXxhv5mO%{mP}lqv2qEE`8-w}HdOPtju-qxI{q
zVdFb!>@|E}4J~~(L&$eP`wg-5^@n?g^hsa?hUWD!c;CPh0t_1ZX@+@Va9WFQKQweL
z1?Q0Ah!e)*kzp$>Aj1afmtc8p@Z1c$PYg%&kQ*_KPzdm;!Qm_PY}DXm0&UFjf&f~^
z4MlOlCJeS-I&w`Kq*NT?U{u_JHfLk?6$l<M)>D<iL1PYuA`TfJs=?`EjA8;iY_z`v
zFI<f^l#_8Y*3vQfi17oO*^U|m>B5w|(d~Ws<Y9dI0kC7nLE2<_8vFX8#ml(!064vk
z(KbpW`xs^PB{E;*;e}A+XI%6MJpRUY8vp`~zBCsdH*TcFVxW<K1Xz&Kk*306<GlZ&
zF~nH>EaXCs?X+_XGpgv_3^zUzg5`v9fHJ2M#$Ub#OQiAC6ZjNmtlb9l(Z-Jx==^um
z_-QAUo-)2b37Z(>CECiw8l6WV5oc_s667<+MP86dFrNGdBb#VUrZ``cam!&0VzO~^
zB^*sL-kOUZo;7aq19r}6xCAWKIPek-rW<?yL}P~0V-H-*G#0Ff+<D_ByBF~OT`+EL
zfQgGn{sbhljVsb1kz>3|6Kk$9+zMKrv5zv;`Nmxoe=0QIqgtUNqbdzbi;V%N;dY5}
zu^X_<#=TU_b;UUMzqiSF{&l!rW}L@{zvadszd_F`j9>afywd3WCS78#GN!M9V70M`
z-h-<~;ZvBnW?bI}HP?+Z>F88r^eTdUt#K1^))^CCg=;sA;R5(uZ<J7}ZG*9$Zg|`@
zhOGiiqjA<cm}oM-mkwpk#@UqGxn*4SE*fte=RbkY7UP+%aLsndc$3OK+l+5bg_?F_
z=|2En#!X?+-EF*0SMz&}`aH<rH3rhTwbxkg4mEwoeUxA9H-5ed*gfM{O^_Qf+NMC@
zzA=wZuY<-V-f;VYF}4xP9vO=>z%pzU(OrYb#%6kNpV*A=Q^nGV@g{Zcsj+4kewk6@
z90SH;%;-bqALGW<k0Cf=%-ID;CyoE37?Xp^+5+HYn(-10I-8seA#lJHFbtN1rs5qC
zIAj{%4-+n?iX*V#X%Y(oyiBW`z~XJ%yB#b(Cfk#E81yx{pNDxrQ#F+VA2-EQ>NU{h
z-VXU7lgm!%4mL4|KnpRwrUhrHsfDtVVW#RtC=EA#X++}*)3pu^P=u+G_5zWn%ywW=
zrg>Cx8*Lg3h0c?v&%4oh%9KJ6ezNHe+aTmqOtz;O%X22vEp#T;wDfmqOEV=<em~t*
zK;PfbFu6VlkZJm38FZgFwZ8<V7fdl-=tY((h$3VcP5<r#OSWkog)!4}Oq-ct$u&tR
z%$H{>eg&NQrXY&S7MMK$OI4WSD{bH@H2LPjn<CRgU+6A2-P;K@C8h+5j9)grMRu>4
zI%7dAHSIkJ`7+bWNYKhnAO8!x6{aUtvR-M*qg-y4sp2Ubt4$a0K<8D{%$H%|n(51N
zuv|9<(xh8s$|?k{*7VgfDxj@1Eg^4im{!gPvECFwhn)sf-x#o)rlA3_HkuYu#P^n|
zlXiEvO>8RhZ83fO4Os4&>ijW=t){t0;946-2B6(Eo`J>=Q``UGeW%IiZ!~t98XPb(
z-KG_EzV0!-hm;U5QJP+0f!J%RX+vwD$&<<^`%PA=RJ>>Eh=IWY(`!Spbl>z(C9px$
z()sA<1C#AlJe?0s_Z`qUWGb$Q_#@No7|0Eqex_W-V^jBUpgl2#ya_KxOz*!4fu|-*
z1-d(G%6<+4wlPy1eL!N|^z#%DCrpuahL|)(>LBP~?pO|o9nIrzz?{r2`@rICcHa%b
z17^E@Xgp{>N7W;T%;f@j=we>uk486hSp_<A#2nHBFOHhsHbBnZd?_4q9_G6=^&c}k
z(xKhcX4am7K`--H6jt>%e?<p4AM?gdknlAh`4EkM<||aK=5OA<4_yl|Pg0q{ar5S{
z;dY?8z>LlWnS;{M7;L_>6d=UhM!$WiIgm<H!pzR^f-~H_hmw3J%%k4W5@G)04|ox2
zwq0HZhoj635+E3D7W6>kq&b$t*Qd<c$*>z^4zOalW6dJk{>GV;DMEDG{PGsC#G7*|
zzIMj^IYr$Q%oifSnP?ta1QSW-!U(8NHV+iQe2O`mvQ}r!7aY-e&it4*2&v`@8y#lT
z%n=-bbaN-oP#NYw-h}Q<^X)rmJa5jYQ^N)GSU=>m%p0j<;G$VXTefWT>NmiWV;-W*
z)4Ar~DAbu}zH5Rr`Q|@05GXJY(p7{@=9!M@Z=rcQt&K(I7ij}nY)-PL0=^P+%N+FS
zvUwJT#IBh4hl91${O2iXD>GlE`}gH$8{M#~Fx$~)y4w6UMdGfTw^L%Q#=L^cbZX5O
zN(R-Lzg`c6H_T-b&{=O5KZ3yq^DA4S<)(SC16ZRuWIHT0nO|K)MFq{~6uJX(%Us+K
zp4;XFG?}!RbE(AOj@kS-)U=xCxxlqH^A-x6wwo)S0j<N_vH{vU&6{atyUhKI;YGLk
z;SQMZG0QhX;I7%3!l%9FD%yzknYVkx!+x{VNocue4oRo@=YaVodV%hn)eKk~G_QXN
zJP*wMW56DoXHznE$h_?;<R6)1^MMVUH79^QHZN>~?kDC1ib#)`r!4^Oso8x3%0|t9
zQ5bW~{M8HS=(u??ZA>Q2<#iC4G;`>L>R@?^KK^HOw9KITY$uDE;@bx;O*5hGkVU;1
zz{P@pAc)PD#k~qNSBpQz8r>{=sUpqYVt5STVHu&w<1tH0A86i|>GLrbJ{EVnee7$w
z_Z3Fe&$28Q%KR;xMnMa(TucHj$Wrq?Tnn~Yu1x?9u~=#P2(_e8I3>&yPlX5JmYoZr
z`-CNw&KD6DU)oMaTAHbNI?AG;cQe{D_A$D4(sFVQSWa1zIADpf=yQR^TH5L3>T#BP
z3UHpba24owyk*ff=saUFEkW-SEVj@t$R}EM(>s=A*>MTFlP#0Yz)~!`=R@0B%j!P?
z&RJ}yA((2Zpwm&B<(W6}GpAd2;y0Y0VR_*Uv}Iaer9n7vdD9A(3zk>@fwC;is#0)X
zw7g5(^=!*lS}=1gGhabtu4SXG9TIsKRS!VE<(fZ0fyGq>aLMuqO(unwNk8Z=vV{1c
zvDjj`4A)954tLRb*>Z~_tye59w4Rh&R8oL4i}=3~fW?C%OBEJRDp#ts1kvkIWqG>{
zSheNsZGfv5^DTP+u2~ABK)i18*bWmlmJeyuQ)~G>4PC3VxCW!~hUIBDSn4h9b)Yp^
zIBPMMH!X)7A>L@2b`{PvS+eQ9Z?@pWD0qJ?A5neU9m~RL@UYdAybf}0mY*pw-ER4k
z=D-fi)@pkHIxVHoVKBNZ_ViP9Tb7XS9*avQ)ZDc^rSDMmTK@hO5`C8NCD7JydFxkb
zyJwja1#JVCKPbL^-{MbIYlD{k3OMt?GV>z9L(6(9(HXLA{_o5576X+g3|sC}vhK0v
zgSV)t=ZWR#1axi0;^zVI)H00%pQDzA_aHcC8EFLTxMdBU)g~;dhd`UO?3;i=2kWir
z@X66SHUs`TS=Ufv&Dr|>8Mt=9YNTc1pmkplyf|dt^97W-Sl7|_8xLC-#>0@Swf0>I
z*xalK>60x-talfKc+~n4Ma|r;Z>)tS59_)pm^fzrmlEQh)_vDt*UPG)uflj+^^0K1
z$2yN97rxd<djb5c*Po)%-|Aif&H$^CDsGQk_k0a!0<B^?Ed*IVq8TFCdUpZ>AvUWQ
zEvli`wQs{<n6;t}Sh)3jsxm)e{VENO5!QleXp6MI5ePL=)`lXmoU+d7hifrb=@^DI
z)|x?QfOxAa2DCHQsHp%6*3~ozCR@E|WlynIN5bv1*1n}^JZBB2gJ!DLem6~NY1UO&
z;7z9WjXn&`dFwqRunX2WD(}j&CR9N1qScx5HQ82A+5qNQKc9kL<XVMP2asp&p!qf5
z+9ZYB1=a-tqBW@RsHKx_v32AYyf3kyr8w_p>u*%udc``29_LbP@I?reS+(@clv^)T
z%B;fr4P`MZt;aUQY?bwz1hi`Fiv#HHRjW5eBd=LqXTa=r>u1}*Qe!Q=4qC1C5Jk}H
ztm`SHbHn=4f8U|6w>DF%uEAQq4iY!5ni>!rt!@utqRIMFE(Dvc5=t!JvQF**xNY4)
z4^oRYHyX4yYh@(7Z?|e`G3>A=zYT+(*2ijqF6*nu;eEIDD>@GKSnq#^#=F)+@~PK)
zsEc0hK5O0^K>Mvm`X<yp>y}Y;d%*g+1`_wJYf9nTpq1$dyAQ0N{tQbGt-HnG9I~cR
zzT=U#g02t^TmPbX?PKe7ihVt??w|zch;^<%IG<Xdi2-fYI{p(>k6E`qgqCruzkcdR
zcw?-dRD0!U@7M}fC;J2{I(4?c_#t#3vj3<J9d)ta#(~nq_I?3VKgN$%{|E+;+8?F8
zi@QCW3bH)x6X}q1%zoKJG<w>9Pq{rW`>@%t<Za(brPn_83;%!@zV`E%L$#m%jcefa
zx370ZV}QMQH^6cGb9B@Rw7>ZoK#={u4p<MhuhOG0VfO#$=*r`&s-C!6WTjbFE@_LI
zS-;ZCOf${2#ig>W^zrt6-*;{GDTsi|E{h<@4vHu!AUnt|Ac6`g;KII$B7z_;@cT}G
z&1cS;`OcjC?mhRMnK}0{4*>HBL+zllqezC1wqa3>af)U}GfXdHXfcc)+VI6P98{Mb
z$CytMns`Rn0t_jEae+#F6B#pd0CSY_0##BUW4OH!^(2NZ0OU9$jux8949jAOoM22l
z3Cxp>ajI!cVa)yt9;PyWG18BAieY>Tou?T>EYO|O82sIkNoP16g<=L{3e7ra7!T-^
zznP2;QE1F!JW)eGn=zGsv>e7#1@v+mvz~$7JjTIbh~zU`uEO5}hAXZ83mMxfpnR6G
z$Onx@j43oT6f<VXDIQS5kPc#?rHp@1LbQzGx)GMj8Qb!}RWKqc@qLaFe+}4`jFF$w
zcb+l%O>ni0^92B{V<dhF4=*yJX_CLhc%I%yml+A`LFyT5Ga4Hhx&~Z}Muy)UG+tr6
zN^ifbjO)l;Ih<M;OKF*Mjqx+p6kTVOQ3T)yW7=Fa-eg2Sf%#SjKLs#tjLVxL($3h$
z1xyFy=?C~>IvGRzf!)KnMQ@y5#)q_U>ti_4&wQKl+dlN&VeIvTzXObmG<n=(q*DBS
zh;fj<2jm!L%>M?Wql|A)1M~r7`AdKqV{E+x7audOl%wwn<I_1H<BU~0pzU@(#srLu
z^D`cB#?|@Vn~>b=Y^cL8;_f`O8yCpK+07H&e&-*k9Q}YZuN9JB&L7ejxO|;=)4@eQ
z=g!w)&)?z99zkcI^Qt)z4RU6^3hZF#{WPJ5I<MBEFU<MRKA;_TzC{_RBhJrdqcPIi
z)d+<sXWoyHjCDRkOX)c0ZIq*qcW!+igE;E!RuAr&^D+@gl5_q07{m$ZY&z(2(m9g8
zG?C)`+4_B8Pdhi*;8dEkjwb7L=l2&uBh%UWIrL>Y&!_JPW;_2zl{$IOXMzitJ+<H$
zJuTeIojbmR`3mPb;V^j4`3=frRXe*<*?zrqFePmooP%htZgigNLchK9GqfeW>ijbu
z-D`1H{0``A&g|e%KgV2fe<_@3bzaj1(&p?>!IXCAUOk{YoEMydLZ|cJf5Tpvv+Evk
z-Om54fQ4S?eUy>xbAH<h$y?6eU&Bzp^9>3U-F7~-A43^%UQJa}m@&6ve1p#1vw*(m
z{040ohn!VfG!8qrINpNdsPin^Dm`#69fXN7=V`P(e(d}!eLV4rvrGVk<IYEDF}RDF
zcmayLnGqkrCl}`1G<mo(U!%Kg5A)r1bXzbd(QD70xsu+`9?XrOfp{`|32Yy8>}%-l
zXC_SocYs+KLIs~*%!Lb~@6F7j3PvBM$_K=k>Gc`B@MFHT0wVs*^Q!<Fz*MuLc#zpX
z6^((+xi{ci5VPn6>;^NXB9IW~Lb_!RF(+O_Unn!t4U*wZe4`IjAamzsm_Nc?6N=$R
zGXn?da8nF3ayk@anXBG|rwPo6?_nvC*$@Q%qfEILXvdkRd+1AMeoNuj6U@xd0h7vn
zWh2}^#au$m&eO~<DL0nEJktcdGtB3|1xhA!0nI2m%=mQl<uYR;p^(Syt%gV;v$L7z
zg0swsE%2s@*}4-$D`looRIZGvqldYi$)?KI3g#;p;Ke!S&~!9bGGpnPtYRh@fL6^c
zp~v<-^ObN|s$nK9hR6lx)^7n;%PiXlFD^2xs2=MQbDJN$xXetYY*an7`8g0r1M@2e
zL>rkql~BCG{L~eqP0VTJMKkmAQ_yc=W-#EzHRkh2VD~z+gyL{Fn6J_n>n1auvW~6H
zb!*{F8*|xdm}qAnqo==v`5le7lgab~>0wTypn5NJ#Wq;zW7cfNsBb%%KN?{74%4X{
ztpiN)2wLwl-=WpqATxIn$UWx&sLE)FX?hnT!^|JY;KhCB%uQ$<Vg51;3Zu-=R)9QU
zeokeAV@v}T!#!jss=+;C&UglPA2X}RL7p%jvG9JJ`RCst6U>DxsW4|3tCWXP>}IuI
z194&fM0K*RtVYUl?O{oRTfe}Qs(uOj9;}v1G<vd9c_8~(OV+}t{j737=pA5vXn|cX
zRu|>jy;+q{!+RfAnh*MXSwC0789&xjFM;^8zM$P#0PEXkh#X{9=0PEl6}|){h!vgy
zlwj6I$_R$ARF5HYh?V7-g<*%XUP*%8FxK{+fH}<4P?=6R>%A~siwM>Slqf&KDyJtk
zl68kl<DyvhA8~!7S$k~&jbVLBThLgR{uH=4)`moI@hlH5OeC<DE`)_d)~nOec$77p
zUVFz_=}g#5Vr`v4Z|&o(*P79q%*y>3*e6)e<^%gAYtBbNOJRLNf!S16232F7VvP?#
z;WX>mWN>M$=R5&(hV>cJQBIjGUpq(^YgQ~!vROq`wU)zLl?U&0S;xuIJXY(ofX-*t
z)8#5))oq|Eu0mEy5k$|j8Xa)Bh_yZgpvA2DwCOEjz3YTwm$KGp0;Y`h>LB#XSuPnc
zU%{GAnd)<_<rC<uWM$8TUKJ~ps@1DmrCT9+p7rPyNDZsA7L6BJ5j@zfWxdV;W*zG+
z0z3E=DJz72%1f+0KVfK>S<ldhsh+j-5*iy=rL-|^WQC5Q?+Pp9Ymlp~0lH32tVfH0
z*39~Zg7PgayB(IUu{itS(@mC(0V1ueA1GbX#)_o<M>}ic5kxvz%c)+plhv1vMn@OR
z_yC~YtgjbBw1@S>^XTklMY%$>j}?9xjkj3EbUXL6SQZTQHtP%>Jh;P}P8se2)>%r7
z++`(w0xt$xPq{<#9*eUTZV$1JQVMgJ#iP>h`z(z=TpM9+c7?(yE3_3JK5(#p=mR^(
z;#1P|A<K#OA&*#_b+Gi9HH8JmC#-F&06Na<e+y)S)pZ;qyV%kVFu0q2!57}Uuv2J5
z>&kw(1qyrE&QxaW#*U{#guU#k9T<c=n|lF1d9c5vz^W%ZfM%_IY{wk>y32m{SUL0$
zus3Bv!;2jd2ut4VlpetNu+ObUqc8i$j~K5X+l`XS{_Jo1Ario5t;3iOvPVxqB#^!I
z6MzP>oxVa}F#8J%|AnwelHuqfcF!tYi%|9?0Xz(2{}~FA!|W@LeJ~Nu&Y%*62)2rX
zFh|&@snj!)-9q)(QS6nJyohEu{R%FIU9u4(vFwzmLE_lv127TKo;?7x1oq0QKsm+^
z`T-`A*sm@}<8gKpeLLzT`@(Y=b_(0$6Zo6T{*o4ane6Zw2V`>Czr6vNTz1nmwC1se
zg&_ItJ+vVxU{6qAA^X=40eY7GJq3G<*b+JeTFg$q0MJsl>v?cxY;hGlEN4GXhI$2i
zkUkl4j=i%3m#dOJLY2$aY~2G$o@W=(3%Z8Avz-2N>jL}No9L`%d(n2Njy-1uWG=E@
zDG70jeR~fEdYQe&g1&lo^Y<{(z@F{~g+}%cN?2cE2fqh{SJ_u)U@T4SP%8IqW>2E$
zuZ6vye%EVkJ5^y{XQxs{+YL4|1l&z_K{REtTiJ0GEN){@=?7_N_fn?2gPnQ;mO9yk
z8StWu-RcUioBd)m6nogkRMp(e7Hk36&#oN?=xz3ncu3x1-){sNV9$w%Yj@eRGXOTo
zj+g*<kNpPK4h*rcO+aCoJ%0s$SI2$!s#>&;u>W8{W|X~j3I_Us{p%;-#@IWk%Kjny
z`lq-EkJvX~M&o04$t^TKVGnr0(m4AacaRD852U_}!`TFbt{es>CiZY%pq-@~XZ#x|
z?B%phL!UcmVJj?naI{Jc!qdSiqX}*wXVVvOYCos(eONlc8KvZh7v}+GaJ)H!FQMqe
zSxHa2FJ}vtO!#s3&w{=`$MFDq0i5+zfOL@a4b`p&azacH3F3T04@WTP6^bT=aPn3_
z;Sfhb-vSBcOgRF~Fpgt2{ji5QCuw^T&UumQ3nDo`P-R*ar-$Ak(VXCJpv7^1{sSbQ
zb6^b=5;#v%@M|CA{F?}oB#u}Jz2ltQJ-|N6DXT|g3TF?UDoEw{(rYY@^TvKCq;vLD
z1yBZO&nWC=at?Bzhovmer0LMl=1kcF6FHpIwA#<*to{-(`J9UR=quo?raW#TN5aJ@
zia6g=rB*TLtq%ZN!g+&!-%?H))v}avUSA4>6`Z$%&#rxHp5vv35UJtZy$*7L^YPD6
zujN!wy6z%pDjjdR#QB}lgqJzGX6V&(hL3=2;OHnW+sJA97L84u`&=kAbGF&xL<?sV
zZIP~V_?KbtIwyg495*;KBcO1T<B^G9qLp)*zIWcn+2x?AyN_e0W!WvxsdA8hPA-M^
zZ*yWOXL5%FOx&xSHp(gua=xaMa`!lYq~RJ2b4L83KFV1}M|B=>KA>&I7{`Mmzz;d&
zndp1OxlV;vk2(L+Ci@A;G!AZ@GeIx!2~N@~3Tf`*PN#+aZtiEVLc@jIzZKkG?wgNc
z$(_4r4H`YT@6Zk5$=x;#{e9dQyy$l1W>a4A0QboN?0Ru+6vp=E#vg_E0bK4|AP2eY
zU&lZLx#?8#9>jf(>feL8Yw3Vs2>1Dl=asnUxJk523FQj5gM@LP&_*wk`)&$ML~%nu
z1&QWLa$q-x%b=B4EO&1eu;aLWw8D+&-fe-21g=~LlF03A#n6(ub(HKl!EK@B&Pi@k
zaN##t%?*d3@icc)1tinB4k|lN=K>%18aKfSU|HOlmq4<)l~lHv!}VMWM{~LT|AX6k
z+>#&An9r@)1Cau5cnrV_x$ABM>@4>)O3xQ@&2ONum^)_#jTKxK1!>Q5i+_iDB{$e{
z49-+>i>Ma4nk$e4?L7A}rKW1Q^Qk)E0{7k&fYx$nR|Bn{JC*YK4O|TceHyu+&=T(o
z_nBufz^mLTJpgUuwo`>-Gxx<BsJCzv%VFUfcPZto+PI%m9YH(y>REtwa7CW9n(O2i
zSAcYJy*7h%bGKcE7d_k^e2`wQOAk!+aaWH5ZGc-%jd!_XN+=F;KZ=B<dt44h%!arx
zj>7F>?hIPJ-sc|w36dk+3kyL;xv6x9;vsj*^WYwF1CPU}$K0njPQu&d33tshppA32
z??PsRJ5&m^T|6HOBJSobp+uw$&xNvPt~_rpu=nu3`v=60$E2E>eY{1n;P&$lx4`=Y
zyk)dq^y0ZwpwF8Ze;WpUcr{dr<IB714S)T3+-tZN{=A{(^ihdmUe$3ZhVaU0Vmie0
zpyHrVo*@hxVZ67ghWaqiMFyY3c|Ek)kKpBQfr%r$j5QcVEbp^xP>AEX(Y+SWd!Y?_
z3A_mkoF(#lZ$kYj?{_)KF<x8)P?C6OSRluF+M57#r1Az881^Y%O%NPD%?s#5YZ~t%
z#R1ZJ3&vn6gQukPWM_EC=_Fz%Pv;5jEZ&sUFqq3LPl9?LPtXr8pZ6iHnhSWH9Z)Fb
z2_m3=mbcLZU`0IN&tRdLcXU2T2`@Sy!!332oG1lf#w(#XSUE3*!ot<OpD6Hfp66W;
zm>S+xx;-xN<_KV^mX}Y9hB}^tQh*nE`FxnT#EZxR=oKD|UTs%-Bb4TD;`vZeqM4U1
zfn*CWZ6m<0@sfwocb!-EG4yWm9CzP_Zymg-U|@Ihmb?zq#S_zs>u%oQ2OvGXy{Q20
z<$XxYi$31TV(8!EJ){EIyS#5w@KX-*PEbhl9`Do;K!<p(^I>V2*Up69`@9A^+cv`U
zrRBjWZ*?_L9`ZsccJqjr?^pu*nD;e>DxUD}Qhm!fPx%cl!UXRj?FHTWQ})7y2j6rI
z`kwsjw_su)zuF42pa0xds2||xC?Vp-|HK5l-u#*-Nc!+=qk!ql|CZvwetdtb#q#Gb
zr$WU5{;|_=?I53ji6Vu8{4MkW|6sm1eR(W||L=Cd9OA!7pO^^c-=y7r7~h3%`EdSW
znpY$EnO~#t2!F=2kc{HH1^aHmR8~a$m^i-Td5}ata}L0c@)y&caE#wc@9-r4s0Jv<
z`O1IMn9To^mSHFOj&?Y4l7CVUy%hdcnxs$hTWR@sny<5ir12+HT0fotS0qRVU-}`)
z8U9c|yw2iBiXf8Bw>h-X&*49&;B+qER{`ui{tpxt$mg$Hg9}^0-$@@cEabmSiM6wQ
zBQ45`_@D2<)h_1mq?)x7{uot8mGZyt1S#VyX`ffl7ga#7g0H67=Q;j5+O$^k<0))j
z#lPMHk!pVDe^oZ;`J*4h{TlvuTDn}|PwE18EkA}{*O&Oklp?y!ccBDXJ^xz@3^nlY
z&@J1@-%QD%D}2T@45Ep@@C^Ez`Ty&}KwJ1Fv|qc%e`_xEuJc#XChi9Re=1<M@>kH_
zsEvPg5p7J{`Nh}4cJlZ70IiGvEak$w`Q8+g>ES1~0lSwkO+sHEU*LmL+~W5vg~)CG
zz%%H(!?)C9Fa!KWG*8{-U!jR&kl*kpM27gQ=>+jGf7PoX_xTk85E<dSy#jlq{I}iy
zOYiZgzlsa>h~GRHijVpK?117E{<}3G<9q=fF`eN5>H_^;f{#81w_EV$UO3|-cy<>Q
zTm`+9wA&*{pjVum;FCk>+biJH7Z%(F{8>=&5Jc0(_Y{oqA+k^4l#cs&zu>Q_;J!T|
z_~k2H8ZW`y-B9!v_)yfwM=(qoUSGkj0NC{ttXc}<FUXMqCP1*y27eC<N}6CIP>>TW
z{sH&#3=#AW2^#MJEL1R@4H72UNww{V1<z1KCtSc?1ri~s-4F9e1pNQjpaPF&xQ0=J
zh6BKi7CiY5T#R5Vy?9~;pVQ45CwO}UJc}22JpovPAmtlK9uw$ZfrTVNJngrR3+6hu
z0XtdnB~BDMoe=cWHua<+aT-KZ1U2j7eX8J=J77);md^ytX~DM-p_nGnZG>dHU_l@H
zG6emUiasOArqFh#U}*)oEWs2ih0GSz+yGdP;Q240mn%5h4wO8B=kMst7fjaDF@XZX
zceLXv6!g(?sI!8okKuli;NvGyEEf1aglLIi4+RcN1;&Hm$^>2h&?^^g{thA)f~;Ba
z;+#N73${wZydPnrN>D_#GSvdv2M{?ga4dlNT0!&@kUGIms;j&xSc|j5cvJ)-FGBRP
zAZr6e>jnOKAPoW&Wi=ZGx@K6qBB=QpB3A{X33$;YnENt*v}VCA5A?MN0;!ncnxKeg
z_3MJU6bii|2$+Yl+!R#Mo3&LSSOfJoL7^TB?ScXg2G}9k5kh5>oq}aHv~~$Tn+(xz
z!IVsN_6a)D!QB$PLscsMg3JXFxh<Ia2SD!#+}z>XUBSOp$u%h8jlr3Fg6)5U8xq`k
zfDsN0Qaf=;?hEG8$(T{W?ORZPAn<<-^)bPgZiqY-+@|n><B{MQ75siI`1lRTj0-mV
zpmRbnK=I&RLd$*-7a{*w_~a@KUIT8A@X?o0bQ2EIv9Z0v&nXJ%A?(Tn@e~$kz~6ns
zrzj+{U-;rY_;f&6`UQxW@L&?ueS}|Ag4b8L@O{|xa|lzWq19iQ^#F<i!dL0`Iw(}J
zF~T6>-xTx-7H+1m4~7UGRCID!SVddGaG_ug8Y6@OF>vjOP)hN)NZ~Vi0F4$dpgn7h
zFr@|1u|iQfz~Y2=X~`5Xl+kgd1mPEEs3!^?ztH>Vm{3cv-6Y|8y7<S1P9xAy77FfT
z6eol~9fp32@TKRWpDJvpwc#mY6b<yWaF`0B(}WBmE=jsjL>ur7Ve;3|%Mv!y4mexb
z@C)3|5w2^7dam%=Lg?iQJ1L`3AdGaZ#$XDCGCI(3R#>tFtwqAb`7l^46jOyoiEtzv
zePzPQ^rV&x9rPGi2%k*@cTT8V3WJrx%9$`&C7eq8f%C#ndMav!Yh>Uq2<O|u)d?rl
zG<Q*`7=xpigqx^L<g&2tcZzh>3%jYnu~F!93gn6~h0?cIg|j+9nuM!pPuDE$ryN9!
z@Zx4Tb6t438rV04VQTc<6!y|PwN==39&Wb@4OG|FE_54*rA}ebbSQKQ!`}f|x3G+&
zYPW>3tD)B~+&oC%p13XSq7~yE;V(|m7!VFsW7vbjk8*%^Pk8xNa6`h+m>|Q#&3^&r
zzA(xRZbbNDHAF^*8z{6mCiJ3DY(5k&{SdA_5<aAJYLA7l(b0t`LOC6Pm=LaC3P*Q|
zPG5nCyG1!D)O9$yh=Qoz!d0}5&Qb3X?Vu65i6SVs>miDcfC*1gKmbJci8j!}V!z1c
zQ;-9q3fks+iL|#N;w?&{T!4>AG8KdH6@|v5&rdY14zBr&JZWMK5Y3{RlY=5zDI^0$
zFYN^92om{Lz_(yg5EaFSh<>~YyN5*nRR0qydZP~G4HNw{4+am5-mCx@F8YQFvm!*|
z*)VZLBz+$Wk)q_C=!+7${E5D3Q3btdV??Y<kXX^rHGqy2-KG?Hyr`oPk_n=^nXr)P
z5ZxC*<EY5K5S|_rO`;@rlIYnIh#nU$r^i28)aU{3gs6rV4<|+8lxR*7z1ao5RMBtW
zK;e{VC#3*Siv%kniN9w06<}vX+5S+-6uJEb$t;l{J=(dVvt3Zn6WybqFkj?|rWD9o
zQFaL~Mv+KEwNS;P)x+?+OvIuWX1OSzcC;0ufmmo%iB8Zt^=i?IuVCW5=(;D=Yej38
zfvXeY$;C}B@;`wqQ!iRbo0|qvq6S=}i1`iFn?xKJh%}2{dKIKa6yf*`GB-pQ=>+dh
zk%>Yht)e1|m$ZqpC@s@2%AbH29ij(c!BVG)KLsLPqTqKhv~JN;<aUq9Mk}vg(R*nS
zxg{Elhrj)zrp4fHi()A9bw~6WA7BHbe0pUJiZbbMjqZu^Cp&;WBs%>JK!-&;z5wWb
zQQR#!Ga~Acpl?*P{0E>t5Jj#><Cy5safmz=?K8sQBa!4hKp%_Ny$wrGM0S6Gj*B+c
zKypI#tPXv<#6MVJez$n}=KymN@3{gIH}Q6V*xM_9&`s+&ck#QIV8TOupK@EC;^|6U
zl6_*49-{lj+S3p{ApVEWOM8nK(Xz}(e38~#zTzbuSn?BZb3&iLIG3K{0C6!@YaJ9X
zs{{!Y_t66%B7V06eTT#sO)wNHp4AA2aB=-3`T$sjcyKKSb3{CkiUA|V%cv?YO58xV
zNsRdYM=&2No=*X(IC1qq=!+MtR-!LK+`a+WiQ<wla7V>oe2Nhs6Msix;Uw{|G=m=(
z@21##y7&go(ivho)tH_U8#rjp6t`1k-;pI&e22kgi`VgCDM$R)%dnIy-bZ_fJh7`2
zxP0+9v{xw*@8f_Jisw-=-&yfSip&&=bH?FzvA9DDFG|D#F9NhweAyG`%fzp-AW|+C
z(?YdE{1z<`&WSg5!I?_&=Rvp=svP1k?!ZK~_`7@1I4|!039U8aFscf=AohxeXsvh~
zeYvtuypC!ZFNzmasa?JJdpgh8Aa*_iM;pak?xL|t{5H)c&Ei|`P-qd?7NGH(cnKxp
zu8Z|l6m&zpj*dgLi9havPwisIvs4P%A-+KixlVDyFhsk=?T4V>EgpXf8a?8B^d9OJ
zOUgj{#Ctx0-CN>#dYt;j9)U1_Tm0hZxCnQ|Z%u$35Qkj{%3blZ6cia0U#J4PCteo{
z%pvjF9k4qrZb^m6eeqL{OYmky{NZtQj*2@ddH6uw{0d~o#3ITVKNRb3gFF(?69fCP
z*q@SrPsHp8xZLC7?-pT%6XH+k;_s4li=n<-Vy%VSE|T9V)Zi-FL6>BYB#EkI+$4VV
zr0tcMt6|n%a^eRET0JBa^l*7f&Qqc8K8gG~OzfA$d!zAyWImPTdr3~y`o>$bavmJ@
zlgKC@>@Ufn?-c|{Zc^;(pd>jGUIa=?DD532VJQF|EctN&dLfd>H0>Ocd}9O&l|0%D
z$uNm9jJ}m~Skg8dqT!ODICMrx*3!cBh-4nsT|`PQN5bJKN#yUa6fJS5DuEcuD`hYd
zD+vq*Oq_&4<qQdu7&^+GC^6EUe^he28Y0Ie%l?I4lB7V3YnUwYeF_)ogru+t3MVD8
z*q-B<xMbu#h@O@#p}8zgvWb4tbV;xcT!zG`fWb48*_0d0lzc?Hlq^XoeE=j|@)s4S
z=16+^P{@^>qQhW$5*AfR<x8HUV19w*&809{DCuZ``LmL}5oj!u^iu6gvE&pzn~oBR
zPbfxMD!E<&_sb+txq_5Sa_O~SA@QZ1*Ez{fD%q)&ShSF=k{pYLGu4v5bcmdna7$sL
zMq>1b-3yXK8$oI%3+XUdon-Y*C|s0;(R%xm#JwJpmnFSd(N`~d-4EOqrbI$Pm8+6{
z{{^xo3n_flEJ-LpV~b=R-KEzgWfWJtF8Q7&^c#}K572m15|<52t&$!(%+)6G`Wct2
zL-LjrhSn(=dK|oz`P8e9StnrXuH<VKGzKNB^TFMdWWEBYh9vRvP#l)@Q3&k5WG2NZ
zM<kq8Afu9#m>HeMB+E7EdnmEer(7OMvgqK)V~JoZ8lOmNi_thP33vg}6O!Mk%5t}K
z1#Na*r2RBAxk^nA+ClA={?H9e?$U<$(dr>>z6Q=y`rR~e`=pD02iY&}Z-#3Jq_+9s
zyrdy?e|Ssh2mtCM^`{`WpY%GF*!oNBk3b|qy7VFjaZuX48&@_^x;zDjf}|N|fD$bI
z`9oMZB>m{W>|Lm|h3?rf>4NJ}JS>f)w@bKm9Sbr?r1vTA87ZAkA2^AYPNt<-jC9RG
zT<%!uoD1knkp8m@>WR`jq<&N?rFg_C>A(?KIxXFH5PE6S(&_LbU3!z=jTzFQNpSm&
zH0!7T&cI2dDE^-#?OTV|TxtGPDCSAcO)#G?{gDzu1=1q|U>8c8zK6lH(wh{QE|R|7
z4!vUO8d|-VNUt@+ZmBen$|1_7vCl)HLfSzA-gD9eRp2V6D?fr4Rnk8qAz34JyGsw(
z1?kW90<4uLC!@1YIze0ci_$*^p?FDZ;DWm>9iaC@z0|fAiVf0-6l`mhp4<h0uSkET
zSjAOoRSZaz^aN$2nx*$>@zEl6Zi0u`q<hXm@49sF#~?SPT-u)8l-@dwK1ZvRPuq<)
z>C{Aww_Tb_tHTcIxmM_RO5;LdqD%TL?P<HEoil*lBi%F~BE8bB)Ym8dXDVE~CH)OE
zg;T%unKE#<rH5z{en<LV2O0;Yucw0Cm0BopKPY`C2PpTXQcB<sIi#+1+I(2L*##Q+
zrAzuDGa}^{p>tF^+ZkvNq*p04G$vhh7a|X(5j>zhlKLy~Q#_XLrt=?9r2E~WH!l5>
z^0*VyT>6&LE?G8ZD_vv<DN^Gmdt(Fo_R7NPS9X`ZvmGKHGDi-@^*m+8JAt-O_7{C@
zYQOBWi_kbAJ4UflFWGl==X=Yx2LR1S#-MM-_{x$@=<}0}O$G6nt&)HQ$l@u+7$)05
zKht5E=rTyStmr%RMaU+lLj8zr32liZWgmQxix4GibI?y2E&Fu>1C5c5H-d|mc~g~j
zoGgmgH}SGGdi)b)Hp=rQ%DSi?;;4-C8$^!DKA=rnlI%4K86KAfoJ3!;tkeMyPsoC)
z0_dd7DHoC{vJ(?9pDN20U}UFc#+7J1Et`LUvgc{Cb^pM{blIykPiDwI=!gCpS^6I^
zm?=yD09=;Lje?umG7U-Q$Zi>cohu8b1!SHqn<nji+1^JOM1gEb3CTj)C5nBWm6cKz
zRgvs}loBbHZKfSTiOiV?ky4o@kb)~^vfH0Pv_cm85aT^33#8ktQWp3=>{iJRO^1io
zvZu-6^RgtW&#aMsHWO$UWEveBYh_6-Fi|JlO{?IGvh|dxyCh@KoA$CyO!0_D*%yn@
zcSTm~3lFc#+7{v>G|8&ksCuPY<`xW@7TK&ecyUcO{Uaz|moX{iaYN=50xxdL_ECDN
zRhBu5#x|LlV&3htYX_j$AzMI;|4vz&J3zZ+eA?x7%Wm%iN{>wXFGPA}yI+CZeX?m(
zoq9`_`Z@agW&RsL9Jgf=6nDKN+prA!12QJXd+*BDXu%E2f+gVY$)?_f-62^9Ju<_x
zek$?3FH2htyCbr;RUo6XP3s}~Ko&r2wJ}-UdDwj@Tktc;BiZHOVd=3f`3byuBFpOr
z%DC)zGq?$dEbAgVcgZs;(CaGyoytJ=$aA9s<0hX;l_nnYN24(4Dc2o=rG0W#t>CGU
z|IGmLmitgr+DFb`4-sFvf$9(a<gZeRmcRVf9zX}kgEoLWD6gbC<v@8ft-ylhf6@Xl
zSnkOBAJ`E2cdH<JNS;bXvZ3-9(*P4DkNOG2J}m#6N}<E$!L*2vkS~4&gGc1gQIs%J
zUN9M;QSwAe%SOvrQG_T)KBWYGvGSQufyBv6DQg)o|FH-|N|1k_1I$GE&K=;A<ZB%(
z;l^?K?-aaFmd~MdXNvq4I*gerUq=hUQ}Q<{*mqj~Zy~reIpY_Arpqlap)o@q`5GKO
zBbUxWW2XGA05oRFCy4--Eq_FjgdF*|=YW|j|KlTYdGarR2g#RDKL{@h<bPP{Q7x2b
zQ-<-Z{5%y-70K^YR-jnkPw(Usd2<BZFO`2@g1$2OeF`v_%Nt&RGZpeJZ{w#tCx7K@
zpjFD3&@5dgKd~F6T3$i3{CPQ>=BXO_mPFXClkcFN*F|{(4~>`Pdur($D3|49PeH$4
zK1}rx4e}v69eh=uOq-7;`AtgpHp`!<@NKW0y$@dW$-RGu`CIZjs>bS<e@(Bm+w#CP
zT!cGvIjy+{<ma}d@vi*Wlh7NK@A(xL?#UNW<YP!)MMXEm@??bW98UM;zTPk~B7Zv?
zqNDP2m*M^cxi9%WCjXnZM-Sx{UjqA){Bi-t^jLn4iiMuYJ>sFaOEGIF&~__~NwDjp
zco+gbS4CJ58uuu?Jwe<Q`Ug<htC+5ah`VBx>X1AXS*ro<@Kktw0Ct~3TLItpE7%mM
zI-uZoL)1$#O35E@MLf-VK8oEGeezXIngK8T6x@C|>aR$n2`WI*$^*(lh3}7$3{<G=
zzy&F6lqd;S%%t;tA&PaBqBw-t7A%A+nw?=G%%Mo5?{6GdEcF2!uK4{dxCq6z15iAo
z(9t{@spwz=G)nOaE%KrjZ_y1EqnJhszgWdDlsJ!5WYY5!uSljyUV@^YK46ik_~{2&
zI;vRF4ZFt_8=nSrk|K68)Q>9;)5<(q;qam0%n5~#rjL_~{Z0T)QJlGpOOvXY@;qQp
zDUzpwoK~!+&|jLOdo3JISGdxqGDA`M4baXg9#JMKQ&I9MEM+P3ih!N1a0vs+QQUHa
z-CTwCe?ZAoEGG4Q#ToiAVS(Z|2OXv^R7?s&>siG(&4ERVkv~9+6;EiBRibdC&1|XS
zvmlJHOtJq3fR-!f(o9~V*clF(bBe{yz^+u>eH{u_ii|U8tX9bAa-UbMrTBKOVlQO{
z>J(0=!Ch25ZUopRg?zFD8kZH*XezE(yg<3K28ERh0UH&e`!U`tiZ&|kzpD6x!k|rx
zDU?QUR!p2gV~aw+8fe!P&D(IDuPZ!gaoDO@JA%G8#pnHSv|Um7GQc_%pWjAbr()9#
zxZS02T>-9F@z-psv+h$oTm$`Eia>XGaYs>K3&jD&n^KUw3NI=L9#Uwi>}6O{NQWlw
zD~_As%!neW6aJ1WwtR%X2a2}Wz>O)+?E>~g#lKWY^hjZ+W%pynYg9w}L{a%NTpL&9
z#zA31G3P~k{&p$d*TL>?Wd?05T$Bqbgy5>|q_c{9ls|05596*JxdChs<)3L#^i-D9
zgnU4$9)uTO%DHq(&s({D6V!c_Q<I_RtNc6(3VzBDufw3fvZ4@f2PordvvE)vFcZ!M
zD(zgTJA#yFXw4R^oJ-N?5aswg=scthyaLcr<;?5g!jz`>;nQJd<2_)9EBDYBLL!yE
z448;g9;fJ4w6a|R>^S8#3XH`o|8xRLP~Ln2eTmA>?Qrd=GI|QQW6DsfOHERS;O=%h
z?oht|8!RO&m$+a|CzK!cp!1}1h(ZV{%ALPLCRG{#6)c@nj#H5TwDMD$i_(-|&xDC|
z<<Ati%}|yk!ow_OJMFBqm9ZN!-W=tE1c($V)9Cvq#mXRx3zR5_<KRW9@|S1PSf+G%
zQ9`R+>30c=70O5Sqn}d_egefx<zcFltx_JPq*b+Y#vSyXS8nzIsZstb2DzY2bih)r
z^5f58zD~(a1NKGb$taLZ$~UQ0u|erIfy>pX{E9YpSCkKO(Rfv<qc>%fGSBfLoN87s
zpg47lGL=eauPN_PH1@jkXR7LLRsMYuq)j=ACf0W43QEUyC`)Mx)u|k$pR!9Sq0*Xe
z<xaXlJ<55B;Chv(o`z(<(wEL?-BvdKhH>6een3fy0p(8=w7#qKe2bpHL1jD(t@o4?
zC43uFCRW4XuyPSCAV-xeD30<#`Q9>+G36ne%N{EKp=#ns$``1n`LVJr3+hjlbEsNw
zT=~OausflgMfpP))#f_rxvC5_=kHOedvOumRTq@#^H4cIL;F8ZRUB<v4yaa*!c#BR
z5It(%svHhDKUFX7uKZQMc4JHdDqRkI3PO=9`hrz;UjjQs^>-lD!&Gs!%Q>t%`7&G!
zSGiKjN36;$fI^%ql@jOisw3&(5>%@whm)u>rO+Sg9#z%%1MQfqi?;GfsyWZY;Bl2a
z7mdlP`LxkJq3WQp(@B-&O^BqZV(8O!sVXg1Nt{v%`(XaGs;dO%(^SWb!KJIRS3oaA
zb>9l^j4J<Q7|aAF%x9_6D6EmK^5a9nk)zT|0h+5ye-mt;iuo2a@>L>FI9#CeAX2EB
z_W?A{s-_>o1uj-S9RsdJwQmFprK(q+gBNA0(W&sMT$Mz#Wrb>v2O7_*1}R8ishUEG
zgDO>#D+W=ms-Vc>dDZLgP_J>QzJC+GT~Hb4qqSDGV>httR8Mb({zX-$1{#-CX{P{l
zS=H`<`9@XGMKoSfy&ne2tEzzA@V7-ZnZk3|RFA0k=(_5N7>%te7g|}jsV)zruU)mY
z3S5V(?Q?LQsxcp+bg3NgErI!7Rq9fZK2<jD({HIRQ3&CVYG48`4ygX3QvbWE1{wMW
zRi~&f>7Hud8_*w8J#!e1BdTX;ULI9tyaDn+B|HW4NL4^ZEss_8lyrKc`fD7n?Na|k
zL)xwWZ5#Sr)L%MEF(x<lN6(^lulhPwPrIw*Z-DbqzecmBr#dwbBKy?tejtA8&>{5s
ztK%ti9-wwqLgb+OFqIqzswb(?7^EJW1WUo{ISb)^h`NlbO%JIX2O$}%9-~M=n0nI;
zT)e~Ts#uyn!qpo*;Z1~k))!DbqAq*`ossIN8E_^_J$oNWw7N78*fHv@(ddg+SJIX^
zPCb>%qT<y>^l8Whb!r3p64lZF0PLuGd;$87spVeqB1!!Z1xJpn9h2c`vbybA7&@U2
z%ckVsN%b?d{!CGyqPTpjn*AaaPpNOHp>bNhF%VpudYJCcboJ15IFq4{YXEmfU6c#7
zO!a0zpk=8AvG5{Wec~|8=cxb8LSwFaMGe&R)DjBK=BopyL!>}$oq%4UdUrX+U(TxW
zT`Ek|>H{>iVzrqLjFzaUYr&PO|Hy--GWGJk;L6nnfl#bahtjV5oO)jo8Y|VGQVm3v
zdhNIPVXD=$4#Ms8>hrfCQloCBNa+Q2I#pNIs!ajlE~%p_!*W@DBL&codUZn%V6Ldy
z-e|q5KDq&<Nj;+-eqU2}Q3m|FdhA~)-cWxpL1UYG^E9Bfs~6KzwGQ<-h3>o6{<I11
zQLm-^L$7-4*TC#k5BWgkmU=GD%l+!*^l0B!kG&0%JL;7bWgBp)f1w2YUA0pjU<TEd
zv+y(DQ>Rc-&9FMM7v}G)-=iemh<fiYusf>0yB7Kn)G6=5;F!9Qii01j11LH0NNs!_
zeUH_gpV9b4{RG=Vr*U<LFDy-{=TPu#mnPvf`gUt_2GHoDaRkwO!Bw*%A7qclvld>s
zX`;N*xmOdj6lm_65C5C3HQsli@2T0%g){p!FFFHzzs9K;jR!POb79^~Gcp;(Tl0hu
z*L*bX5wPT|G5rilKh32mH2Q0l^v#F>&9Q}$Jg8AS-au=h=7VcsgEZNn;tB<8k|_5T
zqFHbh&K%NYJ_nIdP0xII7^W#X1M`P9-^ajixW=y*jz(yv($T9Unm~G(BQ^h0B0EZx
zya#>Jnw#`Fix|yJs^p8+<kCUAIL)kefR5L!&ZOrrK{GEJiiw&uny8LyQrlqZm}U*V
z_LDSqG+`XqY?6Z{Yvz^%`-EoGSAaRGVLyU1DH><0f=<;GNuh8`b9OVpPHU=Yn~|n@
zI0+)@n#v$JlcCv2frvAjH)(a1saboLzQK^C8UGI0*&02S)#qqp;$S{k<MI}`JdKoc
zsrj1PrEtGMbCMz-g_=2&VDPM_(F>qOnkBQ*Sgd*dAoNN!3ux{v)znP_SEgxEz<jx8
z(g#ql(7a61%ySx#MNp{JY{EX-;Z&u0fuj4>nxnB$Jg-Th*IA9m_aLw@XhvR#rHh)l
z5Hw!WtXT~1vZm}hxO&Z=Zg|+B*-C}*jT)EtVDO4&+CRX)swtpYW0OX{9(~Q49S2~y
zMYBH=qrax9+zRfxX4O<EIBsaRrNPCUnzG-a*s6(I3A=3?*^4mIuKA7&{SM7i3L<xE
z3h4FQrJ3dm#cs_hA-En*++R@W)!e6SMxRE#5hiYFLjQtZzh-L;EZx?;zYZdIG%tJ$
zkpayXs;0cFvBW`g(4krO8(QyaPPJe#Lz*~x;SOtRX}Y_w@th4yBbv|lLu6EwI2C;l
zG+nf#7}GS~fc`_xQ#&B}NYh5|ipLr^IwJQ(6Jf#?9oJmhg1!mO7J}ZTO=O{Qx7M;A
zBip0xc0r$;)}a%ib+7g{Dh6`b&ZncE9@;80=&2P^z1=?Ty2WsKzqaXVh#b%shoI3*
z>q}3wxAxxWK=aWqXh);3){zb3r}d+I-CrxGL`i_Qm?A_6wPO}s=0I&{IffLZjiv;6
zu=covg8U)c(DyK=Lt6D0FcGSK<1x4}t>rYxVeR^d&=1#2et=?x_G#Ms9MRUt!$hR^
zCPn_Ev{I_siq^W4dW?4ca<~?&b)g(=oc4=(=!@6BeH%Yvf;PSZD2ZAom6{#ZZoNeD
zmt)#aDj!YK^5_!>$F(mWf?~4vEE^gpv{|(0IjKGNJ)B9=_MC*sY3)N=$faqkC<dLb
zU33#%hW0md`;2x29X!j_-cJNdmi7*n1Z8V4yZ|modw2)Ha<#922ZcOs?jt%ql&{UC
z&C*%zYo9@;NV|?s;}mO|<M63Wd#Vj4%C)mkL8L<aeh>7kw9!<-Rjqwv2|PTn{hqc}
zwc1FEVby8JsL<!4*8Dn1llH0%jm_Fzn%!HpKc)ignzpYV3fHwiBk<vHx}hDV(_uHY
z6`SE{tM(qfI@+{N66m*UH8(J(4y_YScb(d^RDj&2O_YOlYjbiS(xd&14odWD4^vpN
zPwQNOzFXQ^+hDg}`+GCgZ)@KWVn}zi-IS&s(AE#Y{9WxAbO$;HwY)L-c26s)MC*|D
z#@m1y)~>3A=zZ<qt!Nz4E|3FeRGUFd+(%k7-H4C1GYcW|L_5KQzvJ3mDngjhUOx?m
zUAo!-0CTtQW&!$KbnX7|X|Jx0UPtb_ibc@#(ADpQh^IsMX&vZ3-M4h|WxuZGDVRT?
zJ5M`4FWtuP(CDKZryI&w_beTH_tRZ2#P92`Tbl@&0A0K@)DP-XGSL^PD-409Al;Hu
zhy?3Cn2){?UF$lKP+bhwriJM?9D|34b#AAC8Lo3IDuz=LIwn=^M(Q5Z8Ph0TH>Iwl
zb(yaLCRVpK5krg9g;Az5UYANQw?tj9J7A9L65McQj_EE@jY^WPiHanT>m0q{PU`rJ
zz@_NK6opOIRnc<&lx~C)v!``oQi!DKUR_H=OV=6b#9M~$P6tHK=$Z$>W$UJ0!w7S9
zZLJW^)y<v($vmCyYmj_h_c1gU=z@bQtvDf+yAjTm=w$5}M5%7;R`iwWZ1iR?*S)_S
zeHA(zm3N%eZC{T;RO+0TL8M9-`7s7xqr3eW_Acl?P6Dab`BTwSovu~|^@}>W1nQS`
zTPdD*S;x*mW4$g(1@#79-N*2yQP=07<=_=v)Fy~t)qR?Y&Su?hI!@D~TbYYNT+?~k
zK(6Z+Q!ey|F8(+~Zt9xoxoy>b!9rh~uJ$UtZ`ZAKgNGfu0S+v6>bCczu}gP410vnJ
zneou;(XD$Iq*o`gqp?qSBE*5;{+90QyAbWyZI3|bZQT;e|J~7*c*CawT`C<sxTg!a
z3^Jsv7eZlJ_qHF*kLpacKYyV6upWaL)3v<=@=(|K4=%zZUGUowd90fvg5HGA{x_g^
z>7QN+k=^=@bm+-dU$~wsboS_1)B46uUrpQez4~uxgY2%?{0`1T-#~j|Pra}mF#Ghs
z*Z{L%zl&ZA2lQ%M2YTsi=%Adh{#6P?`ss`511bLcMO#1u^w;mhi-Y<yiq!?`|7QeB
zkp2MWDTDPFaCbSJLiBrSg?vaqjW&~^`UNy0hv}bkfy`n31FGT<*GJPK=Lr3$Oz0oc
zr;cFQk@}S9pb({(QN>HNK82DBG5Wvh+Xe~xK`KW{)c<o6dPnsPq)VNS=~)ydOVVE`
zhWc^+^AyZ+B<tTOLhA{ACgqh+>gNQ5r0Cx{4w+Q_NFfwY=}T_{?X<qb9R}0%&o+Xj
z>vJd!lcASV?)8k`jrO^j`m7hAo~7@kql?-4n15g*M_)h-sa*XHip=Ke6KM^RuOAA6
zUV%gZ_RFA!dc!FgJgd)QWAsJ(uPI|!tY^K1#u7bK0mV}NvSPrL>02c5w_M*z3xo>&
z_aDRHIlcT@475^TaS5bKU(SMLwZ7vTB+u*rptwzqK7w{*7xaNSAhr5LnnLUJjuSL{
zT-3Kx_T-Yjm8Rg!`UgdTsn_Ssgfk8Lr^_(VM*Va7;I8NcC=h>DuU-MJN&f;l+N?KF
zS$>Ot1x+c}^feTSyRQF-N@8#5LwCW#O}(Dtd9C_cRFKrB|M~$M+w~)kR<w5Mf2I10
zZvCa#(AlF`QOQ=XUc`Y+pMLL~=)0wVn|`%^{cG=Gytnn+DQ|H{fBq5%I-q}t!jO0M
zNk)umP(Q;6k$ZXr6?YBk{T85cSbt^~{2kSE7NGBezJt~*WBQ012i$+Cf0@ib(x1@)
z=CS@)nx&uU-Ki>NTp#>CL?`sCr@^OPh8dJ|+HLrh!YD3=jVB@EY6x@#x5p5X1wD7e
zA9M=H!>~Ub3Z90p+u-&YUZRc6enS@zA_okmTVcq{@a{A8A!~1gl#2g+459Q1KVQQd
z9(?jMY<wA({0(o?ts7v-m;;!DhN8<52{iC!5D79wI>AJ+;ery9A%?{l(09o24b1|f
zhQFv*B+PJjIt(5*MA2$6+%R=6u3ChlgR0P?44aZCO$z4xiGR~sO+c}R(F%0O8IJbi
zQpFp-Yk|uNh6*~mkZ4fTqj%KcIvXO#46mL7Y?9#yAC1Qiel&k18(yQ7!wG|!LIEj;
zDU>ElH8g~QJ7o}B;p1t;RVAR)48H|HA>EL?3w;>|Pse4@GlnA;fMyz&kHbWkfl~yZ
zvJEG<fXg%N@5kWs4byATSYWtK7re-@oDWiL_?rS&C59fVNG>%vb-_fLVeTSu<%S*q
zEq)Apf*^9vu$s=FR~iImFjQsuQV&vX_;UtL!siX?uLG^daGvh(3kCy425Jq81ZdP5
zKJtXa7Y!f$3iFo?yS@hYWkW0#hSVEc=b^8`a5V~OjfPlS&R#LN%|YK)!<Kh&ftn1d
zbaJoR@bWhpON(L3Oh8{VbkQp9x?$aVie%g{MAP-UY1m8kS*?b}X+Uc;#LybK-7upS
zeI15sSCCGF|KBj*ZHQoCpgo3iH(>V~D(J=1XV^gR(OU*@1w{G{;r(d5ZJ1Vx#yf_$
zX2O{PL-lqv-ZgM3=09lYnnOFOdxq^)pEYDqQrX0?!JWu`!wZzp8!?ETF_=+9HO1#2
z7@mI!Zp;uwo6CoW@ymdDWbhdT=wm~y8jVj3%K~wo#tktwxE2$J7#1AeWo-08<8C8^
zlHD%GQu;+)jasTXaqKZJt^l^1@zNl!$zEf99Xj2O{aZjhj16f3^)zk^2e;3-;uVPO
zH~vU##skJ5Y31o<JVMb5Z=-(}M0|{!>3;GxuBT*-pYdf{xBDCGe}nk|<JXjBJ7~Nb
z56nPgyBEe8<S;h;jn-h}iz(0uF*;Em@sP3nAVwc*%*g>4X3RbePY)Ys(~B_N_!iZS
zMHu;%!#ZNDb%SK2v6N=2C}Wcgex_(+03BV3F&=Y<NUU*-4J6LEn2uA#8;2+bonU;5
z610g%hvG+o9yLZ&Uj3NyY5EP5j2)NIc-*+M7c$Al{51eQVXUH$y`40U-3LsHv1<?d
zQjNk;{354}dP=RHHclS{cAD`?8^(LaIFDZAna1y_kSxpiGzAv2jarHy<rqV{p^$4#
zaZrU|o-vRve!eklIa&*hlhZNYLgTVvXq+{!rHQi0_|bB3#m4#@5GgVKOH0;Lqb&xK
zWk&m9sFxcJ9|F6=$aDjD&M2XLK&8=(%AKl=j8EWGwQ+AS$a&*$g)m!V+_BXGv<t=+
zl#j19&YO$QI-{9>u8YQi5*WN>{BsZbE*tad9a3++LKO}T#uZe;)o4twguyGupO2&O
zs<Dcm+a_aW1g>GTapou*Ta0f6fV*bANzsw(#-Fc(+%WzrhKDzeqt*16X067^t?;zX
z*y#<Y+KrvR0<^<;bqBakqvuiRcNsOb{O>kC?TNk~<2(PorHtPkfk>Y*CIuq5jGO-j
zO26@B8o1lWd48~T$2j)~T>JrJYBl`5Yg|IBfkETiOE7=W*gKt$2@Dzc(+YOjcz}wS
z?i=$dVLD<Q=>*KEaTyC^dSD!%1(7kMh>~6pjouw_=8@6d4TZ->K1Fk%7{6Zv6XV8T
zsHA?v_z#7<cbQJcz>D3c4}Jldi^=gf`dm#bX*ICNw2c<94tLYM(~$8nou*mS)6`CX
zUbN5T><%yXn-*?`!v{>C%|fG(>3Lu1`<gmww)8V;=p@fUQ`k@NDbTd|Lx2XE25Zq6
zY?`D22{Bbtrsa@n1)UcQHT^LgV+k{j{SVF@Hf6mE67Dd4F$B>F({uko=7?zqy(OYe
z7ouPy#`Hfo$i$jX6u?BB=|&W|cvC<IoJlbK@(V<cnRv8YN-|w~4=Be?J6EFbq-m6{
zOp0lYb`Pnh7z?1&OvAlUPd7Cz0$7I0a10`6OdD6zQajW1GordqStg%B$Yh&ZDa@Z^
zdY_7~a!uV7yT~)03js{NDVENw6qvFovs7eKP^7BZ<QW{k3p<(t3T9QA)-*u9+7z@0
zCeE8Ut&prSMbL503ntY!Xsk6op$VqW^uoX3E}Ak*z+EyW>v4fDo8IA}vEFpw2z!mD
zha2%TT`?V50+FkxOnQwqnF^l=*K9gXQJ@x6(lGR{naUiWg1v6qL>f0t!Jl9(H%*JD
zpt0T5^DWGGn4YJK?@p6P3_R>I9j1G&+q8))4SGxgB8c>vI%)ZE%hYlb>iwpw)fm!k
z(<`)?xMNCDp>e>}<_p*Ens$0%@Pnoo1Hj!g85TJpI%Ep2hd09}7dm}>-&Ade%!nz8
z0zacB)ogGNOk1cP<)O)ycEOKKOS<6iV^bbYj89C>bWUvCG)%=n6Q=uAi?qw!{Vsgk
zZJtDd5EpaC-%xio9|;86V_ra|d2Z&HUZAx2UULS$ciqh$v_tSP`y9oX_M2zWL~+2Z
zpd&n9=8iVN_?nYx>F8(HhQhAD`DNN+2beQyUOs64owAXE<~0UzAvn<mkwfM`XzmL&
zzkU~eVdjZJxOUiFo`}A1^I=rD;>>|r{4X?)m@9R#8);sX1iMk@|GkGXMVmkQFB@W>
z`6XP7H7h5<i#T%<?GEG3Ezbfi!Q4sZk%?vp{Vn%Va|WG0Ic`2ciR@%^Ds4<om}lES
zPMRC(xMqs^AVm;U%^`gtjx_U07igrL4F!P7FdL}=G|T)^0vygZPws;=Ip(>q!C<ag
zNyTk>=4&kYn{U<_09s)FburWn%@dSGIcq*aAAv41pASY~u{qBVT#4Ct2GmQ<@9lzm
znRy+}?&ap!dSS1^VK%%16X(q9L!e)2UQEf*D)Yw_YOOYhZUOdrvsDGO8na^)&@PzY
zq7YuKIkN+jb>>Xk^jtLm-T>~Bc|L7i8_ciKg1gbIy@Rn_F}G7p_o{iZ9gR)qJWohA
zo1gK+09(us*H58w%{;Fe<hnV_473~O(UtJ+rdeN&##Zw>D;nF(XB(l|Zm#WtPaWpx
zJ%QF~UfKh<yUZ`HhGe(-%q4I=X3aTpy=Kb=45H86KOMuqWiIW<u=~w_PJ#Mu^QROk
zx?_IeNQ3BrIq?N}bJy%cbKpI5<g@4;GW$@m$*}qN9{_XTJS_uc#Jso!&WxIuQQ^!3
z^LxvoFlP3kXY7%AyBXxMxs_IYPt3=hpfGO!meMB^<{499XqP2-6&iP266QnC)pF+_
zN(=0<1mvO9&GO4$c(K=Vl`f6D#rrLw?X#2wg4=J2w?guOWj8JEyezNA0o2=~<l!Rt
zSR(JkpsywC7W(`wcQ>KW-(sbxcYx)SztMQm61V^s0xgDQU<O&ZZ((G?mV{8+(S%r*
zQ!U{kODCOu3$=WI5uITc5k;B~Te2(RX}BeK1%8nT%Y!o@M=ZO8;Zvj~-vvHJSr+mE
z8f{s&5b7}&8HH71EuT<)JkFw_$t&JsO$SPX#s4%&qDA%uB1bJ}KccYYF^hW+TuipS
z^FGi{Si*Jz`=sTk$>35fm%_oNS_)@F<dmhy8)Hhh-0y)G8J0Ew1+gsBGw92-ylaK|
zEXxim`^&bhqXW`8mdCV4%e9Psg~mKfF-`LMmY2ywfn|XRjgCUgM@Qjek>w%<Es8BC
zDU4fU@yLLurIw1FXe_gs>BL64<w7h-g~fXb%%8L5J_Ax^d5V%p)t2~7NS?P$UVz3L
z%g+L+U$CrfgF>xk8jYpSQk#dyi<XSHA#%x5MNyf{4$G!(VCyXwKa8TmlG}?>G+JJJ
z3)~fpu?!dLs^$86{1i==m*_-Hvn7p+rdlkr0)Sq#)O`Sj>z1=rqjtkG{t)B6X_-sm
z-&V^mDtv3ROjg2DyQQ2eKD#V$(nQ{EnMY@+dn}HcB|z)5xKdroElW3*eD+(?v@n0$
z(n|Y-JC@feZ!%z+vjqn4T1M)CJ!ol40_Z)<B+3yESzcNR^<m54HmKjXY}f@dV%bUG
zA%0+K8HU1`Woaoc>_bb#(~x{*38$6JV@sW5HDtyu&r&30!eXS~X_xi>NtoYljdq4>
zF4iFW2HYO2<p%WKtOJn{*=x<AH=euoPg>=8SohM-*3)YBhU7l0c_+C2)(sRfI$)hc
z_o|omY1-L)TVrWT^0B_Z9K_cuT}KOLKWh;^vHsS;uOJg()lf+Kpmhr!4GXj$^#uvC
z_Ljk?Q0u&AkT7c>Mb8dfSv0?fTfcCJNQCvPjZi;g73V`e((1n!m{C@@VDv>>nGzU`
zv7Ri#km9WI6mW{S8vdZPK!Vj;1TPY;^6w#f)LKNF;A7SWM*)*$bv};~9=Fyl09vy3
zm1m)U!uoS8%%@l*rO->Y&V3mor>yn#HUHDr4?cxtnsxX~fTdeskAz5ubswFUIb&s{
zg3Gi9?gmPhb?Zly@cd<4-`WA+@~kVUCL!NCs~n`j`a%iJ7h31g4RzMa41r>ibt>%?
zi>=>Tp<iO1PqS^QHHwysW!CM#z;3xU*o2`~SU+6>?wobD0??J#O<SN)WgXuNg=(uS
zEuGF=TU)?6YOI?dp!0$?lvW6})+-eJuCsnh`<aW@r5B)o$$CQ$(aYA2KLNYmT0!rz
z25Ta13>vMAsEqrHbtf&$u3B3t+uUUR>LWPXZ2f`Ct6Ho=syDx8t)x5mruA<+ve0T>
zLPaJh%O9bwc)N9=4OhLx`oj=9JFQ;M7;l$#>P}qeZtI=35bd$fN`Zc_^~X0M*=L<c
z%k5j%`E+~qTXR=}+_ozJTXR_hTVQv<+C;TPcdhGZfDBqUP?5<!YYHV;hpaE|2iUOH
zp*;-6`&N%@03EUZGZiwU)?aBb53E~gZ#ZT>PRZ1V)>X7Leq`P3i@`j$4wXUViPepg
z1mo7Fk!YN-dXIzbvOS<z`fgjxY$&+cp2IZj<Z82TMdKb@23;;U+YH)x?X}%?oCWJ?
zYo+YmKHDaGE$z4EGSPUz_Jqonylg9rA?j^AKMIF^Y~S6-V0>*;(!u%J&d>|f-!_vL
zmjSl9k6_}UZL}JVfwn&=6BcAkrq^$<ZSp&~Tp_kEHlgv5ZTt_AP}}$K(E2mX_PQ8X
z{jhD979`x}_y&y;HosDEM{J*~p%`iFpp9yjZGjbzM%%pd!Nu6_Q;0a$_Cg7+MVxJX
zGPrnK7ezc0Y|d1sk!TyBIs2$>?slLg+fp>(PT0QM36ztzBk$3fyA)eG<qT47&Py@S
zQ?@axBspz+?q!TA&35+=u+weo25@I=N()S6+De--!Ytc?EijR7EBpkFIW{$I|8i~P
z%b=cTD|r_N^KBe5SYR_#rm@iWk`@YQZ53;vUSxY8FBgYXu`P<C<|Vdy8_-#9+kPI3
z6}H=(;mkSPzD=-OZ7ZT@<-E;>R;o2N72Vx+w&Js}bkP?5KPX(Xg*t%JV2h;!iALLu
zg=oBDdp8&gS8X}9AWgOf7l7Gp`}-C|ZrEgWtiW;8_9YW&t+pfSAZ@mF6hLjaouOZ(
z!?uDJ|DCo%TJm+-4p6O1w=MlokRDqjs!E-DZOc=D-DjIh#nrcL-PyRZ{kFNcAadKr
zq)U0n#@zu+1GcZe0Onnr>~mNcw2e}^(mjVwN(-tX+gv)jK5Wa`1ho6M9Cs*=*fJ>4
zGip0R+vNu~2^k!-Jv{;P&}O09$49m+v`&9)>!xSyiLH;SM8<9H-vMR9=Jh?eU3Q%Z
z?C!QtNd)I&-%aT)SG)TRH14rGc=RzHcl*?XFz8{A`W1?vcAgNU*k>=NRL6e%(#7!b
zfIavjF0hwfO4q{M{%a2!eeBN;1I^bSM4@Fr``n+P=Wl<WVub<rHS|(EXn)@gn1S}C
zwCV`5hcKWXY<HvDxDb1WgI4{A?B%rK47D$(LY6Rlm=Q9E?Q_?{V7Ps97WyLW$zOvU
zvHR|Z-AMbcYY>UDucOd^v^^#ZCSvR_{Rk3kFQ*K6oZUg`>3I938Vn-AuAK+<WA;}m
z*PUeVrJMUW(pvQVCEEx70(-)qGJtDw(jH2=w^aKYJ<Ol78{Y=ZY5Vyq3?|L~MhryK
z?U9ts%(Q1d1CnJ|Qp!Br-qr+#9DBiZaJlw8CNT5tfmBqQZ}*{8Zh`$pD(o$^r~iq@
z68pP{s4S(_zJemzW%k5Upq1O3C=63!ucmm>Is3DFfmUh%lga?9>?f#(soH++1V(Y*
z{u~Pm7wjA9*h#J3PI`6rJ<f3SqTNBOx=Z#Ai!l0nJ9jb~8|?jbP^-~iXaU$2dlc>j
zhtpMiAB8NM?9R7v@tf^>IYh77U;Y95*X=q=Vc)Qa&jfeV-a!v_tNqhuu+(M`r_5}-
zeM>ET>a>T1!cv$0ji*4m?V(h((PQ`h2!rUgd(%1VKKpK}9=c`UmJ54h_OF}(=6GVy
zJqDQx`!NZK%l4Spf$g@v=?*kJw%=q!WB>N&Xzupj&Z0uS$n8t7;*un7kEAq6%JyRv
zib~r)hjL$;+n-wlpK`YUE5ktZxBrF&m($tpU(x%Zbi2cb#;X6*^d4YQT;Kb+Gqby}
zOIg^No!w<&6KkT0F|nK2qb4Sr7-Q@;M*XN!6ODyfmMTTM1pyJIDM%A((nJ&#K|xSK
zL^>#-SWr<B{l6#Q-~V~?aJ=`P_dVy{nVq@!+;b;8M(qd7y&YSYpsmfg<Nbf3<Q-|0
zJ<+qH=Q5mf-uZ&oq;5NlV&SRp&eesm6tpviqI)NI*7N~BX6N>kD4pFIL0{m@+Bx+-
z>|WkkBtTr<+4L1u%66JilGyE?pR9w5?=A-wEQIWeID`R;*p)IC)Ms}Y2hho~v|R!9
z=yvX|Rg2)%)m`b=&{(!>A+0E?cllz?CT-qziSq0p?#j@@wP(A`DYW`}SI3vYz1zho
z;Ea=fzZ>YNr+qK|;=Jvf=t&x2-%$q6!}jm`ka_zTE`Uecucmd_Y5ToK87#%w&u@Wh
zqWw_<CfjE_KsD8V5<PFy?Eh*7BHezA5^Wjw;S?UovA;)8y<Gd(E$}JNzMT@3F4|vn
zMO(i8m-P^r>^*)*M=#rNqs-?5`yDnAh4vwo=Wx}2)=c!Q$bMBjC0Q5SAK42;iGB6A
zsJ(9gdNX{wVgF766Q%Zz^n<@?zxF4nl-qCZi?#~;W{RWSvY)UL9^SF<-viA``zaJ`
zsIs5a4VAn0p%i^>v|n5b&KCRafifWQ-z5gy)}UbiI1cx28=37V;ZY@HpgZj@vw+Un
z++$p5RdJu$tA<V;<Ibbh!1$}c-@^EdsO)6&C~2pgxlZo{2X+)?5_qr!c7i2<y@tf$
z|E!66+7jviFcHN8YyXC&fxjig*+GwKW%EhpRthGM+e(YIuP1(i=5L}#fPK92fA~AW
zidrXLp}osVy+2^2CQqIUx+x#JK{2(3Qe?h;K#AVdzNU2T>83PqnUTQ*`<?4zV88#a
z8agw-utMt(bM68Aqv{g=J?o4g250ueb_yo{^v@*}e$M?G4RaoUgkJr^O+atv#?a9H
zdM5+0c`X!=`OUFENav4P0MZ4gZPB`L3_Twfo#+L_;^E)n-%ECcLw~8&1Gu$p!yxD{
zKR_vYD|GItSs8pDR(@9ngJJcaD0=?<k*xw?%}5_KuiZ#z-qzirNACY*w2QT;EDnEN
znRS$Ax}VX}?ztN?nQlpUW&@?CdN9||!!DL{;h;Xiq<#VlFXp>0jD<Io9Ss$K=I(!|
z8<~NWEBl05I}4RhnL&7b8l`U;9qtWj5A!EY)Lhxjp%DAoS&zvQJBAW#+}YcI!h{Fw
zum!GqvV|`}bAatnhX}mbKpQyY%}%`mgU8q#w1^31xib)_*q`V*bee7Y3<hJ^(ex6C
zWoQ2cvNP=8bcW&MI5vg?74hsxr@@`TeoB#oL{{ewog`M#5IFP*)7Q9=;!5dk&^GX7
zup>1<q;fAQvXaJ)pd^@dj;E+)2B&@ji|4uAc2s6^!cJ&raVpw@&F0c*k0yt^{2N$u
zxs7Mx{snIFKVZq@{3vtjB9}-<3G=x~8?apB7W@LhWiGlut#S*vDo=P^$axKh&J`{p
z8r)a8xW7;;;>-h|9>FKvMr%QHo%^8@CT?&$CWE__)6(b5%eY~bCv%f)pmlUP*Yh!k
zt%7?+%i3Gq%OFtS<^~tT&>hZp4mc~hw51SL+!@lm%dxb@TFnij=<Yqv(gm6|TpwCv
z-{*vxuu#ht8|i0N$L*l-Zars3*?kS16Wv;k+>}(9XyT5TLNs$jDnZl2ZKY*#D>u6w
zr3aiKhrx&3pn1TxaRcb5*v>8W0=$FUPw%Hk-0D?md(4?m2d<Orp)JcNT)%%Ho^n6!
zSq#-@T+KiX!gKB$N-^%@q?=Lsg1d15p1$M;KLzj=mq2lnZq70ic3*R8A>e+)*}sIr
zx7<w1_U_@9s=?wQnY|oC=_oM?TzVAY`t`%nmLhpW$#SWZ->U#flQedsGF@^p4i+*b
z3+d-pD%noIu`)^iEf~5faVdmmx#Xu}h#E;XrApkFd~zL{EfT+j5UrALcmUcYV<;P=
zU2?oXaBk8(iZQuM?I~~9Lz-`-WFIdnzZhfaEiIsIQy<Lq;Eb>In~~^em~_BgAkItc
zXc3bsO}z(^B^BxNW=lUS1UyIjC(YV&rQ?2si3`%8B#1oe@jTeQD4j_DUXt1lhKHA>
z`3|TokT%D{P@yz>7R~XmNSmwBcvU*26LyR6L2cN*CiSIwd#&s#b-PZMIvt{3mK*}n
zAp2(s@Qt!udU-U-$_0pK*|vHBT4a(h>AJ|CzJ!ObWQlleOFzhp=u;sMCR^z+sH4f8
z3V7jUvfY!yg$GQAQl^NPiJv!Wy-iloCop_WYG~T!XVN+hW9e`5c`r%<Cb<_;I%E=C
z3!1|w0rWmSVls|mJ%J`WDN`}TWX~puV<!K*kIGP!OY}aBFe#zrl@yb!^sG)bv8OZW
zX(qpR(kbqAlSQdCz$O-PFrQ`edJ-D5O^%JhSmc<jpkw2?CLhx=qYEYmJCv@NB-32#
zs>wFG@rz8FT>-delKl-Ti%m8?0Lyg~-44KSn9Q4j-dCE`sNi;$$r_rL-Zj}!1fQx+
zzRkdeG1iz&oeKPYlOmee)|zZx2AVpP_yBM>m>i@SbE8RP0xFwLHjf2Oi^(>6cswvs
z!~uY4HKoP2o6M&f`y-PJwAc99WEV{wI!)5m@WRP-{|b12)bvpoa6zWwWvC1`z3C70
zAx6_1S3!Erl%pqMsOh*6&>S~CN}HQurk>4EJz*NN6Dkp=^X`B<(zKH@Q=&}kicuMD
zdYd8yr%iqSf-^Cu?gPORYdY`&N@q-G{0PlBQ@bC)l4?4M*0E`(7L?(iVLBue&YU+@
zF1Y~GOw(Eq=wz7=5Bv~<ALT6_hUB8D>R+^7GUY1)ylm=ElbHh3(5(O#nm+j+ZC6b{
z;$X1IwBIw3UNilJPPCVpc2h>@b<?R6;KdEoOMjr$W?DoGvUbxGmr#0S8WaS#ADbSe
zP;aNHCw&#}iRl)4DLpg2YouS*bJLsGp!&k}=rjOdng&v^=e=n<#V$XXmKOl;Aa{^J
z(@|cL181D%F%)KWmM17d<07};1=n2V_rC{Vzg$H>2RC{3Y~bAGqdr0h{p2f=$1e4k
zZ+i^tgYvESfjcDEE~FUZ5qZ^K00ZT(Y0a4^Xa9wzB>6ka8Bdl!re*Xwc@!lQrN}Qk
zqm(KikEgdZO}>ZTx9Re~en2Tho>YaAIWNDQ2hB|R`%b{K<QX*K$d-@Efyj~1q|=zW
z@<p`5zaaPDME`r?Jo#VmfVe0hNfYpVd2lve3i(W0^j(%;qEJ_Xe8EU?7s@-1q3w!%
zD}`0B%JV2}S0v9|1<h;niFE4~%TLaND3SMUg!votkXukGmA|13tulE+6db)N&-fbV
z%jF*UEU8giA%E+F+FSBAHB@iQr_wEON4}*IqDr1fDZ+Q<6KFYGEl;FP{(JK8njmWA
zVFB>>zI@6@FkdTIQ~bD29!+83dik4kz%|I%(~P}Q{)9%fNj}#Um!etjGz+3dKACa^
zjIDCdT3C7@H$M-Zhw}9_cWIN4_ys2X6=Cn-T7aT*2oS-FFRy?!L}C95T|1`um?qbu
zik00EVT!=9U^}7sJPz=1g~LjS2*o=EaFL2&Q#cx>=(R`XDaG>dz;asg??<4HF)H@0
zfs9o&tO9AAVzeb16BLSdU`tedO($D36^|)RBujB=Fnr2U+@>2US25~;AT3n<T?x`s
z#cMB=$`nRgTi;Z){ukX*tg=8`g<_)txLb->@gTdc7)}Sy?kI*{L9Z(nMrkDMRw;65
z3D~Icrx10M!j9%@&5CnVQEE{{Z-Bv8#b|n`K2YqUP~=0!s#|coO|jP%+#QN#bS~nN
z!b1S}V?{T`fjSk%^lp5jh@mjyQ^hxQH0_z<#WJ)#R~(%LmM(>}kxs$AP(1Jj_e;gq
z>(J>|xY4%cYsEZDNO_}pGytWyisXFI^eDzIgLtR-I|KM$Mc#gt-Ycr;%>D;O7|q)q
z%nHolnxomeArMYxfwVwyHZ%Nzl8f1N`fjDGnLHBXwBPJSG{rF7%qE1xeNVHqbYTye
zJ@^WhUS@Y_f#hSBP5J)5W|x$3&Cl$0Fe?4cY-!ycVAe)Ir-Np(KcaNV?5}-*hnfXb
zgy6W@uN0gOGfNAFIAOMwo~z+zhnrA}Fq=!)KGG~>4kd&&nDuRh``u<oz5ttp`L-2M
zbu_;m27^xK{o=@d^TKARxR}qn1V>%X&;9@!4|7b%;kLOKWg#ChAG8#tUgmRLpy^}&
zi3M1E%{zyqqyFY)=3oghza9vcBj&5<bXA~v)@Yi;A2t7R1KbZXucB~Ni1~^|;67#^
zLlf;#bCCjW$IVZT0OExCT$*{EH1DDm)NpgnB#=g!fA$LIqs%vrMP;<P_im`1GPn5#
zWT(yZhe0Hp$J4|5ocS6`YfUk~M4|Xp^S<;No0?|+nGJyH=G!R`C&T<DWkF_|@1S3L
zmiZLg*UL5kX%c{W=Dj~c^P+j@2H3r6K8>=j%gyrx=Y(VO{Ae3+cg%aqi%N58GywJH
zjWm^RFn>ck;f?0aJHgpxo@EMLi}~7>=vkY27X@eA&8_c2v%}mm0rno5pACS@6Z0mT
zEj%?Zrv&t8=9M2~M4y{y_J{Yc%uD`&=r+GYF@V?R0mfpOcw;`Y2(G;~znln5J?39n
zz>9b0$xqPMYu-W&0&k1{%OHF#4pEfT*Fx3<;b-yf6jb_K*wjG;SiH>w?x01$b(lY7
zv5S5Nhb?~NL4CyH>|l@uTA1bmchq7v-4;O>lK(zY5Nr{A7OEi@)w7^_%wit}%8y&5
zw?Z|{Lc&0tu-Hm@DJLy<()ughBJ&b7BP_UF^f1!m&25Nii;ZO%gi{vpXmNkqV(C7x
z#8|{?QF+E<!Y>%EIE%;AQ5kQM^DoRNSX`e>p9o2`_&y)CNfuvF9`0F-e<*=A+2X<&
z0MA(*d=0xP7Dh_PO|w`X4dHHSei6dM^3gnKdRiVC2%iEhD|W$du;tMa)ECRil$CzW
za<exa4YeFM7Jx9zyH0TQgk`{6RGzdPSW2HL2)8uQhC+m;Z8*$FT7ImAh_`%y6F#L{
zPTLNVW;r<=h;+-o=FrTrlu<~o*z#)%L6%r9quJnf%P(o-c-wM5y$tVI8g9ewO3Npo
zKvY@Ieu2unmWKqWR9mtUDBZKXc@!QRYb;IMKziS@cQ8!UTCS_W#jCSS8V@h(EnBug
zwZZbh9Jt?T`Rgi(W=k1`%~~w8Xj{J3(l!$`4=f|!qw=BUpdbLATL#fdqAtt8YP7wu
zl+lUDmzM6m0KBq1@FPmymM<u;<h9ZAE&cG`SiYrL(Ob*E;sNZjyzmt&-&r1@EU{io
zS0h||Z~5z6lpK_sKA_D}>AeoZNtsN$#?DGB%0YBdZu|zMuF5z%ma$*??`D+TlxH_V
z(_Q(A7H|)xMHK*^%1J9wc|d8LNT1>HQog<d^WMr=lse<1+=E>TsjqTD2rB)Qt~8|n
z${yO&4Nx|Oq4J>8@f1ewu(Fzxj*lp7HbDd`8z}ecsPX|FxC~P6r}%uZ@(8V5LX`XI
zqXfs4SIl59R9Q$_<;RsPjI@_^Lg`Ie!zYz`I^Y_v{DZ<K5y}sj(H5!vVJ6z5l=DXb
z7_H2?0dY!cJOvXm%IqoVOsw(^tvb&rQ>J4O;*>$Oj}fnY77dmJWx{{2WTo3=c#)(`
zJps<M$`;zxOjg=#rjb3Tl+ao!MLE6>eM(b){0yq;N{&t@WGJKUL3&=Prp@+DrJl0l
zvXl*f0H3XFqQ`5FGA<v^6e>@4f$WMhZ5{wumBVTBU8H<{4xHu6GB2o9C`~9E;g&LD
z1uAbV<I^Y>bw`O86K+;zKpyN?Dczo-Pj{6L=|EH~i_e1Xo^l>#1Jx)^X!&?wSxZZR
zTIDth0@W$6?gLxBaykuugVKZ2mYS4D|3qc8()cgjZc*N&?2A_ATvq@dC`C)CJXAhO
zro~m8ve^f!?aJd6A?i@BrrYF^a@`~#9xLC{cP%=Vr#?dE6Xhdk0G}%VtcEjP%3DLh
z_Ck5N2yHKw?(|G}r3@{G=vK0>P<gHFN2$+mlq+2@YHyX3A^~u;+GvkTC#$q0=&sS(
zD$5W3b+J0Q8GYJs^~MiuZdUQtD7jmi($vYrY8A~BJgr(B(00Honcn4IRwk4o=xw!?
zlAwI7^t7PxwOYRimi(-SMnL#m{V@xcPFt@sM<-&f+oa%(v%Z)GT!Qr&J2;ax-&$c0
z6Uo*KGl594?xodSn)Rb$u#{=NlZWaZYbFEuM(d6VXlt^b9)(h~b=?w_TC9)H1H9Gx
z$Nqpnu-4E<!ZYjaz@afrKVv!NVD(s+*1*y`>jsJ=^jg19K;?VuG|DjgV7(&&00-4r
zx@8?z;Y-2kq^hM12WORbCIDV4=Yz24tqL3mmJn4AWmg_k%{z#m9amY?7Ic_uQ8QFd
zsA9&WbW+v&2{a>A-Nv!hQI%a85Q(a8nlPSMZBK&8R1N+W2D4Nzzl2JGN=mc+Le)oy
z=mu65Gy#8Ab&EpMMXHuD5Z6?T&Hz`e`aTu764h%O=Ig3SYhm|>O1cQ5RJG$dD$7**
ze01riYTN``f!tF$Qi^zu>J3dn?yKHxfu&lNmm?5$s^7d&s#n$Df)@=c*`E-Ns$C33
zlj^~9;F?uGzeAr|RQ*~}YE^x@A09qXT@(R-sG3dtE^Vp>?_j81m2nri4wZ~jp&qGf
zzM{{6JXUql2z9E=zQgVDM77ooz^AGW0RTQz)zH4&bJg@3xYni0rI_LiRsWws^HOz@
zUYM^`pRI?7-KtCFP<gF-Uy8Ojs;}-q^R4RF11R;Vj#3=@o$6cK0_#;x+ynCt{CUK^
zjZ#N`z#EK-6L0?-Y|i}4zEE}HZEr&7Fz;3b?jyY62XG(dr;G$!5dYJ14E`~GrxkFa
ze9cKz9_Ov;MH|K&_Q3lSd{Ze(C;2|~;t1zO%9D@a1s>)jd7hFsqWFc=Fiys3{^0=N
zPw{3)VfQqDsvWg4{K}u96U#SI!onGTB1H${`0YA~cs|qtCKC8Llroygze<B<5<gA?
z?z8;w99WWhFG}w}#~=R-r4;@vN3f*wvD47OH2xMXWz+eSG&RgH@;NC`J<snMfZ9wx
z<Sa^A{122?mdyuIYEllrg(jo9{7!oyF7V&co_8Mq-6FJI<OkC`F`qv}f$U5CuNMHn
z%xmctRlu*H=uIIXM3K8Ie9`BCU*)gSTfc~ZL)(bgc;n3%=u<JTJcMEi{{>B?uJb3W
zfw;k|Xrri<KT7%eWqbm?zi#qw=FlwXCyaqg1s|xuHMqqW*TVd5eg@gS!yl%z<CXjq
z2~?{1w|fA;%OCw4qMC1^MC5yX!69_8hF@a*7{&X%<1wh#^79iR>UdQFdRWhoqL69>
zzfKF%Mt&?E6lvm{=q7LGH`&3p7Jf5*4x^P%n+$^w_>X8+^pH=vfyy?13=ZZ=+xZ*k
z(4`K39>stj@#A9Q=wp81Y*cpg%Ig%Pc*1Aifj3Y2FbV`b<BRATJm+0#@2rcLh$y|_
zGpE4BOMbu{*nP#fZ-F!2yqqk(=2z0Ok2idr2gF<6l|m~${Qcjd`Ho-oE8x9+pIm6Z
z=SQ7EcR%p<VSqabEhA`+<S2YM2enSZ8A{V~7DU=Ga1l1mLCICvdkqfn7tR_{auce)
zgir3m54S+-A^cqgpFD;6H1|Is{6$9xyaelNSn?KbbphuiWY8Y2uh8a*Hb24g77Y0d
z-_if)EkJm)h1N(1g=|wed`KAe->EDiV=YV^5pquh5h#2{DI`aQ&%7Xlg!3L4u3$k=
zFX|9sE$!|c6CTqhY^ZRJp4rER8AqTJChS`PODBYpW$4REL7W8<E;w$3GZ8|d2Hr;s
zuS1|>j1o*K!7y5QI1j*6f}F0%Y2n{cu*C@eG^2<W+QvZTj4&`3B2E~*8X{hJCBlmY
zA(%edn<&`OeVinCtw!ZpVZkG)Bn#tdf_zT6`wcpnBHVI-!BoM9qL^vIV;(B$Mqx=X
z5E;U9VmmJ!q?C+I;S7yXmf#Zt^Vz~Qdz5knbIQ!f6}sqy0T+arH4u5i<P`v16#iHZ
z&3vJ7IL7Ic(76(pE(;^y!ft^uv>T;D!QBYJ6``1tS+5F}HV{REv5Vq>*MwF|aw!&`
zgkda8gt#Oit_#1#fb@powhvt^6=Gw-R)!0M(oG>>hhCHm0?oQBgt$-O+AX2~YnZ<+
zoM#~J2)<h(Dupi#K~^O+(L?C2ka!V>ss-O+XuBtjHGTk1jWDYnmhKA!QXy)E2m4{E
zPH?&gQ7>#T0ir>eI|HRgVGCtMH3=q%fo~QxwC&I$6w}1MRk%pO%m;!p2%HZEr!2I!
z2?0ZaYZuIEZ>&SudJkle1b<prKNj9RG6L8sSl&msp9nb=s(&i@Y{z}|Oz5)^U3)J0
zQBbl=SVR+q7XnAeu3rkHY9U?;SGK|5Zef!OfY-uGS~9&6^69>ME4a`zp+|5Y56yQ%
z);d)73eI-0_g>iT4)H;FeU|bJ9n{h0pm9{&N@37RoskYUXSFgHe!HkYmO|B4{f#$N
z_NyI_q0LQwjwZ_P>g}!I_E2ZhZSAQJU;#g%9!=R+UTQB25_qczP6UgOI#LDmzUuBO
z0Q}VRji~fjms?PbFhJc!$5jrh@1;QJkotcVVLhyFE`rVxwH<|D0@ZI{LL60(qc1uH
zspVC0CRi;ifM$rgu@)n9Ouf_-ZK3KQ3V6h;kI^BY1ht%kDT(T)u~11;ucFxRS#=Ht
zYLeAb`i&URsRzu4-4yj$ng^z;{~QR?H1(k!@HAcRl>^r@)R=<f$Dtk_1-qH*PbdW>
zOMSQyq}l4z7l6xAYq|i)Rck3?ctKsoL*%JrodCF~UZDYJzWN&FlwVR`K8(_3^`Hur
z3XE#sa<CPugK64)MSX%+Fjv*)^sp~d&!9xzYwGj;VWL=l<qg<M)Sv$X;C1!oC7`*X
zj{g~!O4a=-*j1+fKu>|2>Xemmtz3QZ7)llD>)im{QnP=;&~0@FU6DI#>r_xzs*ORk
zQmj(%S_s5lwJs4Rs@0!GK=q!wIv?GxQO9#oy|1qM9F}U;b2w<$slS>GQLo<Q2GO9N
zdk7{P)zj(rXi`624%eF1kGF!XMXenJl~(nf<tRN+`(8)S9;!c{2eLMGg^@mO(5{Z5
zutbOYNjHFx)O)RA@Ugms5*9kumnm2KiTc+Js617V`51kArhc{^q|em`iidZp#~gs&
z7wWG=QF^I%NkQqA`im97b*sm<faSIN<(Dx3M%|Zk72c|su^5CNb;eYhf4);s`v^L{
z>Q8BY|6Xkv0!ts%O+IkOLG)UNt~rXEGf{F957MmCS-iXpmR!V4niaZ=U!6p0zqn@s
zxZT8dnqIk!e>cH|hj^9t^gPAYAHaD)OiY3B67NwQ+*>@bfbtA|L`Qnb_=>T#x92B5
zI|Vj>@xx1$0>oIlFbBo)H2F9r-hG40!{X$F@ac&7E3Hxj#TE@pM@5m2z6FW*hoKX}
zVicvEg@}F(JUk{w)j%^;%smUAj*G+ALnTa1oQIRcX{n60@x3>kj1aROVL4Kar{z_Y
zc=Hp`MvDu>P&y@^{0D8P#s94ZZH)Mg7DlmRmOI25(KQ{KapJv5XvT|Q`+_V%oT5f4
zQQUqH4kU@YX!rB1XrMPyvY0;;fODd$0V*ltG9&#2Qbn&Js7({Kbown_?8rl9h8R{1
z;Cb<kFH|$dx0Gd*C8{XhBU@C_vph$vq>;`QUnBr<L0s@2@I0}T!W$RGOuAk2#pa(-
zc}ZM+1f|R3IcsPZh`-2CSt#a=F@p4pIM5GWyDBax?jmtcBu4t0sQVK>6^s5YXe$v9
z(M#vLSo;D7Z-^5I!>3ZQu>_iB;(`}wyD56SLaAIV8v*kbV%{u>TjJnluy9*^OLN9M
z;vR}ZRf?a{QnO0jx1JXGcSUEKqEw5$^Z>ahT7C)D8u7$Gz~2{l(a6?{_rHdTI`Inz
zz<SZ;6Zq61hBN`tDE2;q+fCy4+tIaVab_({w21r0LbQrC{!n=!o<0c+55@WPWNs5j
z?T2U=n~~jSly-<;H9+T)IFFVOkHsMcFyARYplQGp(Ww)qr=mU4JQKIg1nF~e8O=Mo
z#4pVOcp=8oLA96S3z|&468#h5cDJ~`5~bH-xD!fm#Emj||5ki68@L|vGA(o7iL1VV
zim_MR`4x2Di?;$HK8PiApyQxvVBw;pW)aO)oHTc|C^>5^+R^5sF;0e0hcw%1je1yP
zbpdThG)pOmI#8n?1i(>^ZW`KxH1}UZglPWu1K^luE#>`&YUWTp^0;Q$M=&2|)P$75
z?g>r!78Flv7HNSG*PN!Lnh4Fnf8lqerh)cEqck5W0F2gD>;=s!&8Z;}r!~(hrW~VD
zM*<M5ner(#&uE;jaGByX5fqV&*L?8>%qM8Pcc3y!le`dsvl_dN5Xl;2Mm<Q+X_~dL
zl%nyXsY0s8oHm`)G$Y#JQ@Uoh7UPwnNzy^{ye62!Dw&!f`qWmIrkIv1*_uK9U^hpT
zNXf*x8sD$bc0q%n4t@@rItuw;)C_2aO1>tQDlcia`oO|v%^;%^CJHo1>6Cn-W|key
zU(tl$g{7;S)%Kt%(mePFs@F8r9-}kGn(OrGj}lGWzaYJ?nf5Kr-_TT(`BKda3elEn
zJ~{+(Q}at0D$6xe${DTD)Zd2YElo)n#BI&*bWZe+#=VXvL6w^3=}@iGl+yOiT}|l>
zG*)YxsrUCZD%#zv(Kvk#pYCgF_hJxhHI4ott<#L|Pd^9Ehd7WnXnq|IpBgpiDa*S_
zvuQK>(yV#p0B2e>_O$kD)nwNI@IdqW94a4b?#!YfK$~V=64=@`HcD9P(A56~FCJ+u
zr$9W`jHv=!r)C#Dgr8^-lgH0NBc(mfXPORL**w=wp#@!+=I&20_(Bu19|QDK(;Ee{
zR~o-*(CpSMvW17QHLuNJ_l>6RC^X+{gk2N_=+Ok*K<Az2eSfg^YEEv2>U+&_dIx;a
zsOau=(3Xe7Lr3k<At*U%B{UIr)+Sq_<f1io0?t+IPEm*b+H;f$?xyv2K&89(6eV4F
zXvfi3tf%%NB|;t0s-FYyrER868KbxM80}yBXf5ak?yI#Uzx}i&bjHMAn@Pc%0Ilio
zP&ufLxPi7q+QAg%Kdg<UWRWA<spMgx_8^5Wk7`ek1t3U!ZxrCc+Dm6Kh9TPF26XV4
zwq!6ws5ZhDWXH7w=nf1sYI7+2=Y+QJO?Y!s+lO}E!?h<;0gTX&FF+|$yP*S!D6Qj6
zl%lmyz6JLwZ3-Q^Kdo*07(T^l^VUHnR%<v7vNPJjw_qtwdyU>h@!DdV7ba-^o<k*3
z%TeN4lGbfCRL*LR|FeV}$=Y#^U^}NxSc=9J?QnYPrE2pQ1D~dSYXX&Y?ZX|Y%+QX#
zjna8-&TfcI?QR#0dX{!)F>u-1<uf31v<3gbV6HZeHa9M4Rf+I0PkSN?l^3<m$6zR5
z`}0YV6=+Wy&!JeTz54@HuWEmo1cOCd<8SconwHA}uvojA64*<$WuK$%x^^SomN&GE
zUqYo+8$-w2%e3+%fZx<+)4g7<4SWYn71~-CwB6FWQe5P=_7T0??r4WmT%=O_a6VY7
zv~4dad+4r~Ps6pZ)(-VUXYOgQOoYyT?W><qS*!i67nbU@YkT2vz4iv>lQ(D=oCkNK
z)@eUznzZ6IbfQ_?NSW9z+M>bWY}M|j%(w^I>6AV6Q2RCQLA7Z`n#Z<l(}n`xp{?9Z
zi3*Rj70IZ5tTir%YNs}kUV~4xNiyg>)uz!x|G9Poonh$G{z;R*7uu80Azo?+jsxzM
z_Dc%Gc5C~T!Qa=~p>$#1X!B`F@>cuS5v3ljoO0{mX)lzb)T>=gGo$y~Rn-&(_@Hf}
zX@i4q+H>^6QI|X#!bx|e8NyjNa5=ni(G?W~;i{{r&r|Hz-I)M`Zn~aasJQEXp*5<9
zZr&)cc<T1}qVj<5=tGQ!mrg=Ev)(!fa{zpFGs@BCtGn>uQb^~P37pYiccK%u0lG;v
z&p4=i_BmWUq~mDndRRB^4*Wi%%VA+YP^X*@6GwI9FQF8qW9Zri>%N@@5u)>b3ivVI
z3cA@sbrYuIN*>oOp{=tp-D+9|oY3u|ERU1AVKYz)*CmXC`H1<txbIPn)XkyfzbM_X
z3veb{7fX4;r*!|Y7~s>o*kiC8qq81^QmihNPH>#j&FhAxINhUt=vut4uL(qgu1AWt
zL|s9kJde?DSTqrirsy7w23e|Z9i8w_)7jDvK)OyxKZgw6Dic^guUq2)vzfY(L+DGE
z&OQw+*}8|6y_%zQ(F2#Ot5l&c7j#p1qcTsINHg?{x&c=}ov*VF^vPrT85h$u@T%^D
z8@f`YdlU`oYq}mE7%J9H$bp3t-TT=nUDs{;7b-V&9Z4W7)y)qFu1x1{3&2g?_o1*}
zuG8)Tb%pK^`VPe{-2w@mxUI{k7|R{qJx6F(>QvvMtxD%gS;u#ESB%{tt=7#hfzCbM
zXX8<-(aoVlJNI?5v}ata+e4w!I^E}X0M_fIbd?%(KYjttMxE(nR5s~We*s6Eb(8zU
ze2Z?zC+O!holhowdam0X1wfbXJKDo}q5FM3#7kWdJr-Z-nx<3us9RSy43=K&Hqrv_
zjV`DXrMEioR<!l#CQxqWJ6-TOINYmqq-E86-MR?S#M^9?Lo>nVA#L9$+0+d|Cz5R*
z%g}bt#^DIONU=%HLS?GWBQI2@+0@a(EyE_6W>uLscjG9akYzLWZ|LOM+@wvMTpKIe
zg}h)BDyNHP)29JmT(tRP6WH=?`h0-6WK&MNK9_Au>E<l3aT^Qx6&vdlbR}*46W~md
z%}g_>6x&Ru1pN}5urg>~w~_Wk<qex3MgmZ3)BP)bg`>>Igkl~yZ4PFlvD~JeLZuZp
z!)V%i%cg=h1#jDop<{A)Y)(>IZl%qawBb=@Q*i>7cWq|VlB?P#umC3R*_6}B*4PAZ
zMknsul+qELTAOz?>8`UmJs*|zHpkTPsl_Jj030<wwAp<hG;KCxX=kV1W=ST@ci8l$
znEfN0oAkSRY_o=fs+~46A0VFCR4;_)Gn;XJ!S>vykxq?v*$n#z;)PA@YgE3p`ScuA
zUfDFhg}>c4Jbe-2wN0rLU0$1?DDUj8O-d5H=rP(%r+fXK&9tj9(Q7k?-dpc&Mo>WF
zgN^w_&^YKTJ0TqPTlHvj(m&e|OV0YgDGuVIzd-LqSAD@VsO;CfYzC>Dei*%O-Sr!3
zSIt8os77Br_1&~ZaX^1P0F_?)wdv@mx8AsqW==l(RGQxS>TN0k^wXzp1!;i(>mpPh
z)W4x`T^!PT(O$t}{m_*#aYVnh7B@?v-p3OvNA=&+J0eKG=oTym>l;^qGeqB?k}8ks
zYnB2Rs(=3;n#c9wBT*TqFZ>vqC-fyodO@Gm*U`cKaQ*sw;EvSqkHmOI>8<CXztQ@M
zbpG*_{<B{(B&YQwV&Gb=e(^)#;`AatJ>vBRlwp&ok6#Iqr2p<OsGQXgOo!cM{dxMS
zoYOy|wRDO;y#f}}^hcgUGhP4B8j4eA=%-nt@x1;cPk523pYc0Lv-B5z(5Gzug^{4i
z(f>h-jJf(G`fXp(x7|i%p8lE*Dlh7n(0+2hzT-!bUDD?shNGADFaG;Zk6zTE6NUOx
zx-YKif1;$8tNLLy^C{BDSkqdvSYOo(of3TyZJk}$KVsqA4gGP7RhH^!QuMh@KVQHg
z+|<9ONzz;Wgi~O1vmHahb`RT26r}XD{oVm>fwuOPUJ-0NiQ?*^wp%Iqe8P6mAiyJR
z4^DvQX<O%bRL0n5SI~zuVr}hct#Zb8j|`ULY;}&%iMJj89lS`e-AgagMB87M)5zKm
zz5trDwyn+>u4G$BI`n<cww#7L#ny%Lzfx_Ne*yF9wl5X}mtmVh57c~H&lVWGWb0-Q
zT&Zo>K9H5!PQ4FJ<4xO7SHf<&?Ngd0RoGUnfHSvjcg;fAZrd)UNbMcl<Mg7dv~4{N
ze3k8=%K^M=JNqJ>skVJpgVH_QA2)%t#x`{baQAKdw*psd8x@YqI@?QqfvdM2JOe&8
z*v?EvTcfSI65cl(ZS`~@sKxe57TBEaZahS-i(M$a(OvC&Hvzcc?&c1V9<$r=BY>fH
zYhqD4ZkJ0F^Dw(Zuc3LuZZD<QoU{x7Z=cpKyA73*cIW9m5^Wc85iE&z{cK<%$?nB7
zboZ>CPKmZ;J7dOPT&Ht(a*8gb*vSe}O0}Cw)3`Ld6kk}nU{_5mfjqmTE@-=G_oW>~
zvE6IB6eV^m=R;h#n?oP}xnZ}4wz|vgUelggx!q|?Xja%gq&u+I?tcg2VV#`|ExqgQ
zrqTvLgWcr7zE_d4l{*jiUfB(whPH0I*t-~m*LJoWaY5eLrP1@a$L^0=P<dzfr8C-k
z?Y3E<^xp39URZZ9Jf|n9qv2j5G@T5_nK0{Y2=YLii$QY|m97SD9lE>UP`eZkx*Il8
zuDge!qYA>)aMSoNygy*L@i83rGW>cM2ya6TZE5-#0>-1{YxtTbW&Q@9epCU5@C>va
zG)$vx$U_GITfiMQVDAMFCWG>GXa*WWDOh#XaA_6Vf(;T1MuZq*e*z%Xa5Nlk#|=4S
z!4hq_z14`uQ--~io*QHEqB|hg&`1xcI76fc9ZfK7r*&<jfu)CLlA#~X7S0-qDY%ww
z7-tF6bA~SZ*{2w`X28Q#!_|psOEdJ#gh)43tpZtwA!t1Y;k;poH7c_V7wHR;mkpU}
z`g%@*VI3ui7aHp9;QkduHa)Db8veS1$|A#Jx)H7!!f2*eVrX9sn(Kz0$I*7fP<#<>
zcMN&-wS!7S4XrBb3_nnkMZH1x5nO99<V=R!jfPou7>g#u1`6;t8-_Om-eRzyL=S;h
zL)TxRd0?1LKe2~~Ej;jThEHarvfYqPSqB}4;nl!DGFaHd3%`%1JY``D|9vuZJFI+a
zT#3I!#vX=m&dlHRb8ul^#X`6;(n`Acj05Glx-ltxQF3S21_A5A%*Q*%h+|LY+hF4W
zbMPlgA6W?VEltc*nJE!)HI4D66?{6=IUT-bFg0}7oM$|bqLj%vQ9e}`<Gvdz+04#D
zh#bbq0+-8Nr4Q;|U^-W!`+3Yiv_o={ai^2>`OGv=lrAw_>3pg2GE+eB`(oz%HGTTX
z9x!|9`Ru}ee-@RlY#n92?q@H)LZus<L1!D>*>M>td9ceVC(e`IOz(pOY~gNHda-6x
z0q|zC6QSwDzFPtoUv|0$y5z^oDeK3dbqj_U0c<GZL$WX<yAK-|vRkYx*3Pp1+_Z6^
zIl%2goJi)+t(*bwBb>HB91h_MtrZ~0f8&}c!SS1*+hCut#uqvhchl^7@-Hc%{_W49
zFutUt8SbsyOsR!C%zlTaeYYoS+?m8H7@7l25`7yk-N-B}$0+7AoBI8~YbxBM+3tJp
z??Ev7fnzBK;vgvqr7lReSc2MLGI%#iCr$F{P)oSU!O38cFfpOTv`CXj6fmn-J}HOF
z1Lc?}u-~ct>KnAZRB|QIe5WiNkCL<10fd7B<4PE<an%~sM_c{-3oxgwocqJ%X{%GT
ztsG<3hjwyftxUa9I%5^E2K|h)`hjB2@m6VWU{A1mPRYfIRu29ci4?1AtD%`?_4R&;
ze5<A3gRIDE3B~WqtP1A>e%C6l2b|Sb-e<sa&nnA!6{<B>n!Yf9-zsq_M5oo3AE5fg
zYV<Xfo>~=9H1L_##serlx9W|D!7i%}LogaItO7>B?n|p>eF1o7<wm32ZMA$SRNh!I
z$6)@g)zFPl>9H!KoU(UTU(JU3UaNET$)opHHV<hg^1;f#AGjT?C(x|j(K?^@-<_=g
z^gzkYI(IZ^+^rL7+&!#2odEQ-u73rZ1J=LyLCN1**$xq4&Cyfupmlf|F3ln98F8?C
z*jic#vPkQWcp6yiQS|bTwLV)0z**~0-qA`R#ron#^f1f1w*#s*))Pmf@xJvMBCWH2
zO?%w+)<3R>XtHkq8{KZUUS|tSZ>*<u;68CsEfQeROI7<l40@~9Rzn1-zBRzo3Dv3b
zaQl=hk~Sz4R59&<r>drJfuU^GxL@c9<t3HU8Tf0eqqb<gsWST#s#U5XwA)dq8cpfb
zt*ZJYs619Fmcs4}RnP%A)1!JDLF2@4x(4CF*I2`nCqID#9S8VDu3+)vM^Mn!n}0}4
z2Or*zURA!l?Me)~AMbb*C8IxI6%CyLzP1S?bddjjB>X<ao7SN5Ft4HQl_R{Gx)#V6
zT?g<ef8rV{Bl#ERFc`%Tz6?M#znfB3PVr9~FqEhH-zW?a!&lUUC6<@0h4*LpY7v@o
zeBT&|cs_{cB?(4;I>i(dd1ENLmc*x04CpNX>|Yp6=B1QDb&glQg~3$bKLDC({FeIw
zrt@zp*EfSdN6V=5d_Q-HOrD{)Xck{yNCV8<Q%7_76;r{I%a5Qa#sz-%AHe1DWrLu3
zkvE<>3`_a^m=e@p;@1uV@G^hfA45{c>rS9gmHe4K;I8EjPC&HqBm2U`NBqVgz}>~~
zp#y$B{G;!{{f-}b8=Ad*!wA6N^M#bu{DHTl#jk@fgr-_v!Uj{QcnfZkp!N}xjH96A
zD|p9))K6IOF&h1ak@R#sD6nhb(;;DqH`opfo|Fl7MA-2IfPq4?2}(zWDGd-O1sf?;
z!iDS;C`AaN??DzR^rII?l<=$yEYZTXP<U}lxY~izX<_{bXvPY^hEZhZj1UqFyK%y<
zQ5dLrVSO~rCkSqo*^?*)wLvvWSo#;lSz*m(kY)<?X6SF0u(J{HT)~;ncU%zqlDH<!
zn+uj=K`e*nb>V;Gfx96LABs|?u;wkiuM+x@Gu6V782TvqJt3Tas?EY>9oSlgGc;vu
z70PIL=z(zKF<g5n<R3(z+Js-|=ie?QUV-QkhSQV(kq|;}=*L3jW&n_;U;;}|g!SX$
z#ZzH*1WM0@u`RIsTnOF=mM+1b!pbj&^$RF%`;{<Kg=^3)yqgI8Yr%gW#2aD70QB&!
zFz*RG?GXmj1LK|Wl1^6i3R4Tf_Fl+{fr$^oJevJFsK?O91s&B9C!pe_KA!_lXSFxo
zxi0F(7t!XePBfs>M{Usu0AF<jo%dPbr%u=gwg7eGO1kLkh*$9Kkb3XO@bs{n-v%$j
z)gctRico(}6RJqHbs<Vo>Mf6<8Lj@|2uM$<LnfhgTHPlMq%rEB1C<qwUgLcWb`#W1
z&F~^ooxK9MB=xJlfm15*|Mbpj1tL{lL9fg-wQCqk>FOmrF<u$!ex!O{{Ug2QGS$~8
z!kDGrbscTl>UcX;=BV$6!L?lVTFUOYpw`vFQl8pmI?P{GYbonAUmf)k0Hta-N;N4{
zXa9w^a`or2z*VRx8V8~Fjyj)C=~t?s&_F#_SDeIHbgFNE3eltf)Ddm()Zf&?e6PB3
z4otjP2hTy}2lXHdY&nR(3vkp?9Iyo5JBf>1VAol^`!g<@i#Wj^23^HD6vo>xj+}=!
zH*v&ZkhzQbpBh2qA*Q$k?<rmlMafIFqX~_-cutN=AF+~hTYSacbHME<p8Fha{$etH
z*e5`=s6yL8v4ggJ4vEufr~R-vnr7ce#2p7w3KZ>~z<E@Bn+JH1*gG4Q!D1~PSO^ih
zLv-h#7A<K)6eD^}M{TTlZ4pXmMD1Q&kvK7(UYzmb>Mwy$6gOnSZjzYz5`8)=o}k5K
zvN-8Fyf`P8QWj{67(nTiCx-s~8+w>LwD(^)b8hHr+W2+<;`fEHP&I6U92OdeO}|Lf
z-`<gTD3I`e<nt)h28>#`4C3ghx%4aw8fB#SNyw=91hA!yN^6Aq%cDd}t}Ga}Z8lU&
zMvbAL@q<x~m`qDgj~QEL22b(dhTVSnyV0=;<bUSTCdQ`0X7FOOqz!*}l+&zh=V+rJ
z_;+2t39JLNYy@~6nL)Iwbz&BrfQBd2w=ZZ8Fn?Z$2i{CO%_|QxqbGyo2op=+r#Q~c
z2?I$Ov#pzY&fJrr?KIQ+9(|2rJSZ6{ma$%mp*q7%91YHM%olW!JB9JGrx-*wGyV@0
zbC~CYAaa>8RRCUKx+t_(#Eks}&Rk<Q-UVqf^PvVNN|-P5(RPPP{tRrD%n%a{Ko#@c
z4JPg~cRW$qz|5l^mPRIV21FB+Pyl!{v+hfDu!YH{{P9-Cb$|@x|A6V&g2so;&*X3$
zlXMD=&zN31I{Tba(eJv8F`<~v3&xAG=U+1OR4DZ_3n;Arp4l@K1N4Cz7Yi>O*kSa}
zb!3lMpwfwLqiKjUd*xSXy0C+Z#g%oXRnvZU>>OAyy0O;Bq2tcV=7ZaVJ>`ZTda?$3
zVjf`oeFs%9_Bibrdb1hr7-t{WZy1Cx8+{1Ek9|dtGk^9j?T!bq*J(O%kX^@v><~M(
zAE*zr?NX>5VY?_E8pul4qwOfm&4-1cf$Z2R@HCiB6QC2qo<0btj<MV5Y*r|1`v!K8
zv+Dw%R$`?-D;Vx4v5oOiIm>Q(0k&keAp(_|?9w(=X0e+n_>j$dehac3_Sza)%4NT%
zbcI58>k718VR!mK^D4WBA_GP2yMF+`#=89kXNuV!+W{zHs}n(ekG<RhTn*bqbE*3*
zXIutgEz43!y@4It0bnz`av~5dY%i^-TG^m4;r0VIbuL{{cEmU6SsQCluZwn8P@=7a
zomq}H2X5;w0Nl8JbehVCbN(0x4|BgvMddN>SugBHa9e+eg)>|gonMOM?nlz2DxRA{
zH)#UrLMeWUob7fvlf(_b3>UMx54A9n!wsa!Yc6Ne53XI{eC|Rej~nt|xQ=VJg856F
z@Ff73xk(gYDBvE@fq+787OkJJaAP)t`YQLX3h-OphEjNOkL&!14$e1nX})M|<5q1$
z?NhFUwlli9DvF-H=cEgP*f06P7w)@BZ2O?nUGj`F8$2WybOPN|VoFQw1Csd^qVke#
z`yQpEk`J%oZ;&LPo)p27_$Ocqk$BR1gkzFg+R6!)SpD$dcWxzJe*kzwGJ&26Cna13
z#v)vDjxv%XB>vAKA|>bO!)Q^GTqTAyTJjww10+j2DB^Tp;z=nod6J4L@ac+V{0YEs
zNJ{7?y)8+nySheVU;t>6`1hc)L-Lj)`Hv*iC=cBDSfcGfu~XtW7c@^K_FK`zrxN!*
z@bsA^;%^|HOJ@HJ{CkPT&+y`dWZN5PI!J#Ef@_Y_3zQ`4B>m_gxaKUiI|YD?bO{}x
zb(OA<Lhs$AbLr54yR?>GVII;CCqd>ZeNLZIJ%Dhf0theZG@8G7OUur~gpYJHC1?do
zhdD#%sB{*cUI~&~QKEgYw6q=EAyVxD8cV4_q1sTXCCyF3q%uoro{;X_0G5-|Vkh)4
zT-rrJhX|?rKX4{eYEK7uqoj$n7n&e7uCIVjqEtpd_#|n|L^Pho7dOC`jE^WloRhYh
zz(k5PD+x5I(sN<(H(mOImQoqg?`f5IURsz5yP49kdf3g9-v16GlP!JZ0kRxv^(s{6
zN;hl*%N1$PTiClQeM33kMN*lu20GWIHz*mXSbB#-@g>slXgYBnpOb*j4e6m(xQ3-t
z8`>(oDIHG1l5(jy046G=124kuThfB3sJtx=%SP#rlt~A?QmU8<f2*WY+9SD(|4$mI
zTctnJR>=dYW*EpGN*8v}B)LtRoPo}?OFwl)V~6yB0^E<KKYb5;r*yp^RG&!yISrMk
z(!wxQK9g>|3C-tHfxaK~K{~++l@7AK&T!OG)<w}#Cz-(u)XuWp9cXirb&dhtRc7G_
z58Y(7257p=mUYs1#;_Kif}*D^oTk+WWcuMC^^%orM#)>Y;T_x$#&JH-gvdJRAm1^W
zEzJ)@Wviy6bX;cl6G~ySB8noPkPUG_<w;qx7d(uRUCIV^q%4+JTT!ylX^k5#tDS=`
zosv!Zj9yizWh2@!&M~rY{Q!)W-8~PTd|AybT-Zyp8rmi+k=f+I{aRVUV^rcJ9yI^x
zm2J8OyQfX+Df{rUiEJ$_6_|ASpt8oKvKW<hCMDj0x0`s_z_n*46VicuZL&QTWN%C!
z(gexqVH$h`2v5^Rv;%#}bblPohnW^rVC1Z64{i8on+9gX?q$<J4S+SKU(rFAXQsP@
zLFy(CTZXnn@-~_hgv(P*;6;+$A{(5k@?HTdMRFs}Ij_mD4+rjm!pR(!K8ore;hL{e
z@eAGSeu`jPmIf%wKS%9B#VX1{KCJlacL0wl_P>JP!HSdrLNi1WYzLKNin(o2Ij-1n
z2p)zh&e+0WgklsuNh1|I^uR?aj`>2IRtz@-{ER}r25kw7k#wm3tRl!8{+?49gMLF}
zilTHY8q*Xr17RXvv5T?*G8El(U!7OHpebmvVw^3+b;W_37=$uKp*h+r6d$L+#BD`?
znq^ih+Kuqyu43Fwkku%%=_YMZoa}^(lUXJ0*SeTxUPWoY8AsuAce7<iO3L*yYp17|
zpIQD{h(l%?+Pytu_H`GAB*<)eBn%!i8}f`MfcQ_n#U6iu)4YeP^Y2kM-GZI1U|Xp9
z68~P5OTnbY6(4|Ivg=Fyduc!f>X-eU3DV^kf?;7r+%i~Qncjy|A66}=ZO7lA+v4x)
zje`OEV}BBQx@N99{;rFr?Y!;l?9tmDyN2Q4J53IPV%K&z{M-K3w;<hJNwcfH4V1FD
zuZ07T@kbg?M`i#;#GDuzCA2#;GFt$>89zF_;lp^-<KNfFEE$TTAM+6%H3(udhC?Tq
zc{3O6A<VWl=xHLedl$S)XQopi{Q^^yk4{}-X3@O2lv#3!mg_Vu{XWItF!o!@F+0I_
z=7H}dJA(r3;q0kE7>i(U-+`m2+4a*<8N>QNrqrthR!4`z64`P}4oG5El+c*U4wj&l
z#uiM6NN2B6nsWx5upamv_AfsGa@khO|GdB+cE<I&%pTkf^98J3GT?>mk!#Q_W^Xvd
zZV6jS;m(`v&vbi~v%B))c?GMdITQY;IZv#hbC-QN6~$_HY5+?2*e=S4tY=Lblp5He
zzPJ>Ptm-r1o7gq~&3oC70@!V1yD6^O&W2HX;}h2EA}U|7S^faLWG&(Wf5rBt8>WZ7
zJpgtcxH%T6?2@zI7{-@Ih0SvYt@!UfBhoYW12cn$$AR5OhY20o&5r1a6YDt;U}v^I
z4c1)Pxu+pq*)e8l+s|542A&%${RiXW&W6zJ+Jg=L?={Q1(w52r_DnU%@J%pEUh!ss
zqxYi^t9?dGHD7j+9dv@&<`-}*m|dTO#t=3>3(lNke{6@P7`8jv^#8n6kEfOId<|^}
zF0iK`@4_@%ATJt-PDmH;BaS6S4sc=V!$vSHyVQxA<+Ev5dqr6;$W|`c1N~L$L*UWx
z#s{?HwEEi{ApN7SI~vw(DFk3`e+rze<A;M{{d;G?HeZ+mW82Qt=JQTJdNuBPIT-aW
zj2)dEaAmyxP`97C{WBoGO!*`j^kZ1ckML*Gm2fD4S=ASS5N59oqi~G5(?s*HP-a{n
zTnJ-+{R_3>j6Io&V)j}=oMyg%iOMsKhUVT0%%7CwSjw!RM{XI@8Hpa;WY|(zDrYQS
zz-|SzVFOB4%-0hEzt6Z01-y|l(Cy#OOySV>lKDV+5pNlx1}es0X4Ds8`@on_0JkH%
za{y?<*lcf9rm@?wH}QYJt_k#jJ<ohR0-#K0*q`9dV!rDEVKx(~Lt73LMEQQX%=c1U
zhzm?KodM5d+-Ox@#C$5igKJEFA>hS~1Kk@XOxJ%qRo590s=dLu(57rDlTLXeWlR?(
z4>vL2Q?RL-8Tk`REzJ1Gpy^~bQvB@+vz^BHHS-BQ?cXp_6w7d8hiAYGXSSH;@-FOX
zI>+J7Zuu9&huyvac755Gh0r|8b_dh%KZu<*34<HVuC9cLVC@57K9YS%G3qFGHO*|I
z*^2)HcI*%IcuZm+Qg+yR)~g=QWU})zU@41zb^-8gb`>oi3fSHEP+7>X4F%u|>q+6p
ztE^=Ra5vc+3V4^Zo|G?ZtY8<9Ko4)RGFsT&XG==ZSj#SnMq?d2f^OA%c0e!M8rZpC
zVVv4oOmk?_vr2=uN9;xl2t8(>&4uV>M{fuG32Q$9@Tcs3+P!+l_Us1WIXi+jxVqR!
z6ft|j{zS<+FO6(4jq@w^$!_@8&1zcV>1(!gBf9p6y&4VGx2$_9N<Hk$QmDLR!&ic>
zmt7HoHZLxL;*`N0K01NNE%*Bt^yM^X`74|`%e5SaDB$WTar7>?mtr7~xjXcfaFjgW
z0?ts0F^?`@qGanhc#|hta}%Vcl2$rlQ!5d60oWy}-44+sDLSWsVf<GnT|ir3)%XGu
zsY!z=)1_Xjpj_W3>9}ApwMrXzLZw~$*G(Ahl(IC9dM@?!hGw^P-!l08R_Zy3&L4e{
zc9=rdMfT;_eg2PM7*Dwo3sYz@y7<R?Xk2PW-`rfDP4nuNHtA?xe{(ZByun$EzyI8I
z0^jz`D*SuLHZ@G_wEG$;2PP^F-Em}Oj_}iixlGy1p3Ey>-~*U}e}Vp>k@<$AULj0Q
z1B%C(Y0J?V$?TH?7{!#(D>$AhrLb=T(@uM^iOk0oHA!dAJ%uwFOc=c>&oex2lV&ng
z-vge-#L+pLY{qy1zT_}F(!i3-%&~{c1;*wBjWknV2yu}y&Z22SJ~P??af!LK5ZsrU
zzTX00z<i+ROd%6Up}Q;0%JopW%1k~4(jsOTWvO0cV(7qZG1K>7m?&Yq=_b0)><oez
zH<;r)QCZ4l=L1*9@YSfi$>@|Ql`~38f2?MTjR!Gw_n0Ee#i?P2>R{<U)BYD-S7y{h
zcu~g;kA}(vW<x)4KV*)rfl3==M<-y~nO`X$*ulj93GPRXg9a>*87xicA)%xvKoTpV
z&Du2f37vY#V0Ta|LMHna1<SM92mbU%&SUS=8s!pOv=W^uWPhon9<n8+0G6=#Da2aJ
zzM$!51>3k9fNJ(S?JG60y8Up?fg8F}j#~Vu-cEfz#(Hjt2xVO}0X@#f5m6XhoCoC-
z?Ej|0^hvgD9~=p1jWcPpF@o(^0{0@>Iu@$P@4F3S(d@bzuyTqW@jn1hvs%i9iedlK
z0}#s&r<9vB>?kv6#<6QCND<E_#X~cJz1NCTBAa6cOG&H?r5&ARJ$9finSDr?Kb`$+
z5lVTi$`}Tki){2_kQT9X|3%|9maT>}#q8yJ=#;Q0zQq{dW(|MA{2jKLCUKQ)Kr%{I
z>^GNzt7j)nK}Q={6IyOJvNOH|u8A$&1<}lI-v>YotD%qgw6Y(F<pKL!F?@Q+u2@WG
zLfhE!bp6`d(F&+`u*nLrJz@u4f$C${{R^mevdT=fJz=Mug6L)gX?pvbb%}+)Z`fZB
z!O~kcjSh44uti;{e8*0@3e8^j-^mc~*|`VNwx44^#&EfDSLvDQ%L$DXs`TSrDL8zT
zyQPIr5NBJD(n-#YVmsm7Z)<>v<yO&N<r!||a`fUH=STY}DctlHXl8TYxkKb|k0@iV
zfSXDgZ-w0Pq44PnCj>#WjN7P(xXF#D0983Rx&l5`aMSQ0H6j``r3#I=xrKB#>JAt0
z54)Az+JmrE#W~aUxyw}=p;FClo(X5}adsb}vWC0V263PJ$^)X7)6;aVj&r;Rcs;k{
zJjfcj=JycI+|aXdt%b{@HDxPz@Dj{F;1*3rca7~_6HSmhxW4aDe8l-*hw5W)Vl;rA
z+~@5O&$z`4Af9s$%fa2n{T&X?UVLd3-FA?qP&TWhWWZarIZ4b`KsZaHwxP{MlF=WU
zu98!<vF$FoWeGzb68=YwjF)6;2b}RXN}9sqzK^7s?m%D3AWGl!lYH_I8e=4;6b?Bj
z>B<5kTQZ))3zsERW1vzZ`R6PuJ0!O$L*l)3z(aW9F8i8B#!I&6Ip99Bk8`1NME3GN
zsDows=TI3U8|s46G1(Usl?;^`tIt3lmqk4Q=?Ph^0Efe6ho-{QNLi^lNTX$YS#m};
z)D4xfvNcMOo{^<ch%`>NvjMnxSu%ZwCQ)W~5h6)8<1jeS$~y3whyNZ60=o*z3;*o}
za?x%F{9SB9A>AdzmQtqBQZG8ayzJ>TC@pXO9)H&kdj_I)Nfev?-~283_xhd|=xlv3
z2Kw7_D3{`&SehwpPYT4}9hJ?nw6n$;e|I~+hrSErt)sDLHeP`*-psTWG$PCo7GUvZ
z7DPb!F@u`u{GmTn-HTf%h^eLbXfUIo^>qldyBOja6V*)P#CSabbrSO?2iDS=<E~)K
zVX9~feTn&G8$=Pagw|iBjO*tZrrV5Z8hpIR4EhnJMrKeeoataZ9-#6SGlBwI4r~*q
zGwTuMK8MXhJQ4eN{QtQk{svU|G3}HZ=Ff-}1P@|j?gJala1$}$A&fKa1LJi$7B(Xp
zuTjv9Vm8z3C!X;*49^poNihH<GO_f!PGbB6^Ewgk-rNe6OUzzd48Ub(4())JFfA)l
zy3TB}h1oky0Y%m-nZe%xUdODBL#du|{u`VPOg<$GG%{Bx%72Efw1P?;`)wQD1MCJ0
z$|kVa=}Df*E~JG>5<7)H(sY(xq<~0fw;T7NFU4&A86fJ|I{E@y7}rj_qbIoY6u>#j
z9k>A#;T&>g@Lu4!&oNYyT<S!$MRDUk0WO*=rL&l)IBqLcPIGZI1~FVYh0<a<YuYmP
zm85=xHa|%ztr7ht&nO`?KvJ~bh>jkVtfJ86A<1-1sHBG_35&peL~?^>34xNalv;dL
z;zL`IL6ZMbR(r4{YA)=CNN&=!!c{hu66wy!`fi2Y1ldYGO6O#UX-b|Z8)pqbhAf#r
zeU>fzEg34gG9xXC@?_udqQta(*-##;uVlf2Q1vpgp@i%>lm1#%UNO0F9;It0NxR_1
zZIkW^|8L6I#un0g=rNm{48NYSC+PkClD$fyh&SwE3M{#CRd?vckN<?888G;5JPt5O
zf7~wO-?N%;!pqqjqZU;^{kjq8pZRzU%AE4;X!s>i3--D1qX1qqvK#eFJ>TH(vSixD
zTmG0f*H*+v!Pv@c)8N3WhjW42@cU5wdt;LwtZ$pY5dQyjh7P~&`A~-Xz4Iu6+m#uP
zj4Uh*uU<imo00LO*_%7_HLb5an1!@o6URuh0Z3tbE<z`hIZL}-dCWeFtrRkm$52_q
zEVG0tXXa<Z^(y8QS|rvo`86oDFl$Uvdc>@ph@QS=wiN)^%h)T?=FGnP3^)(=*zf;M
zQ84~OzfJIc`V<}`F(aK8l-nh=w(e$j(HBZyGZCMHriU5$4M^WH=?TDpU?$Mn83#7t
zdsI5JqXlTXuo*>Qa$|Q>#;H3ys}?E;S%(A=A7Y&qD8;kWR-=@|PHyV+-=#5PCKY`I
zRaI=I7dY;+i|WBx&E`<f<2^QS5l}U3J%xu`+0Q0I^8uSS1f_O%#|`+^!AiD3vy*k8
z)$$W|Vjqm|8}|N>pnuD*q@b%O_t`rLA5NYD>Hu!Z-{|8ZE?_@!#=~4F`t{#kqW+nt
zS6$4dU0`~_*wZZcB{Oj!Y`$V%9zxf;nP3Xayk_KMQR&P!t@^LqQTDLu#jY3)UT?Pb
zF6a)k-4_5q!ba0lDUkjDYP%MmsE#On@9gds!NprNs7*iuR4dB9zy*9zEDz-^j|EYX
zF3W=0g<V-5sfyNAYqinDKK8^Yh^9uXqHR>xMx~n4`T{Yb4L(3^#YZd{YY~M?=r^{1
z!6n0Y&zUploSD6MX7-%fYyxNQVct9?+Q^*cp!TxVI-c&?$1?gMdWdc0-=sOrJ_<*R
zBP_QbKA&J?Ucu5y*6<M2SysYVi56D=5|(~px1K}I1!k$m7<I6oQBc>Im8WEGvZZ{b
zy~QGLLRmK};KBADwqYLH-DZalqV5ihHhBpp*sLY;1o!XkZYRwD!8-YI@O!MR1YLW^
zZu4~B-|WltfC0ATV?HEI-VK9;?5Z!AFWGTBB!^kuYIN-%HgpfvCyJ(daAu<-JOCn%
zijAZjz+BtTAEY~qj7MPhD_s0j+;c@+1|&xm8{6RMCZ)O&)=3%rKC~QGo=ODOqWq5U
z+&Yv`9>C9g%BcO2e4+ev0+fBOddz33uT|-fK<!d_e*q`<shar#;e)C*HDK<RoIEVj
zAlcR{V0VvnDisDBr9HzKi*F?}a$cCb5_mxTh;*DMnU6{}d?xr_+SCQAS@O$+7j7xm
zf(AcG*Rd+8PD@w##BoO29}3r6q#F-m@SIeY0OomV)p#`jNh+L-=B<*C58C}K^=0xc
z+a<|#4KnRgN)r6ODxF>iXF8;(eB0Y8*&6?!-WIktV2Bqb^AF#NXZbpsR3xE!^7RaG
zQd+mdhtx9u#HPjULeunXPf@#=+R-ZG%2D{6`OYW|WNjNl-?KwB@Y1yYD;_S)Y1sm|
zau@T|^^&ohAewi)6DpS8=R5dizm`IE{?q%YUGDOMio#hE%zO~@7##DZPw~H~xek(+
z;dRhc?COOEtH`55CH*tODOK&o^@>5BTP~aI4at>dvvK{Qy1<2M+Y)~Bl-IaWQBkxL
z9D6Z8(B*im7sIsb!fm)x8T|~`PM;az*N)A=^_q*3;BOG?63~&)#Jy3_aZdC?+(STw
zTu=y264eii5s}&j4u`GGVy-H)S2(p<*{NZM*y<u{VqCn&>~Lsf?G;tliYliz-eN0r
zIIUWTt-7=fk`yr{#s`#}Eq13dyil*<e+Hc)Oc$jO(;E#&ZI#__bCT<YIQ322sC_B!
zc+)oa4vEv=unqT?VR6TOIx$Nzk-{t0)7%kvSy+erz%j+BKMm@<-lZ75auV%omOLp@
zuk_jM+o3>FqTuLIhlDZ)#l!8}G4|vM>U!WYfkN*xPxqZqJdIhj@|Yspo!8}ApXc`1
zd##91(3+gqN~hLhuC&>m+BmxfKhVS9>CD{hMOvrBY_S$rS<U6z*ac~!vF6I+!c=>4
zwar?XWiP3!HCI}-an_>hQu^zFYNC5*jaSg1&!VjO!kh&urucwJ-RqZW^J&{S_i3Bj
zs-nS5V`Tc#rShQAF3*`17wqNhc2uh0TRkO8ZwS>Jb-Eb=dc7u0qYuD+WY9(E4erZ*
z>d5f{dP|YnXf8IIb-IX1y}_&tH$+5Q43^mzeUZUvjMyCbN{!;}4tzD<6}=w$LV;lu
z^BYIp>q8vzxFJL?FmFLXAW~pB?~lNsz!0Y*j*|odU-=Z++k$X`qn{vPjS*OYAjr_c
zf&?Li<1|6Q*%N`y5QL>1F+o&v)Cj^>j(R*=`#jup=E|Al#BBGrh4Lg(%%}Z}<XUke
z`6bHf?3=MvktnB$v*;`*2fWBT31l!8B+2REHgPDX5dhomM`_7&8f*2V1|Zn|$zZqo
zQ*;X015;@`P+UtrDO__PX;Qg#Ag$xr7f4q*4g`^Z8pLc=o(8e*2x|F{RHuXNy-3T`
zU+ZoHDUPEN4r?iOF<>6m1K5$N^kgw)lr%pBTpMlU5KKJ))*DQkOm22MtplP9?U`Vo
z2_gS1koi=e1+rB~Eu5T1>TI;lrvd;w5l%<5!HuI4PIk|xG!s;{MN)%F4q+!f=(0%;
z6tk({Bu`f*jf%nznvx?2i9s|!N1iUOAS-}%&!O!(@-$W36SWXd=6HDmwdKgz@KO(#
QiXl}lr26KPCRg_T7pA^0i2wiq

delta 126694
zcmY(r2UrzH)INUqwr#g}HHp2&-eZd;w%B8jB^r&<B=*>%Cf8mN3j&ICL_m-#B1l&e
z6-5O^KtxbPDN^hOmEU{t`~Lsudmi1nbLPD7IWxOE<;*N4VZ+kGhaGMqRSk)1WmB-(
zXIRPen~d`?MH9R07MVoa$u?Lbk;oV>{VQG~lPZ2%FGIqLF`PsuS6uzfN%$kqtVBAg
z$zsxzvw!uJN@ScO=sXlSc78r9G07EwtXNBB9vsxKH4`N=o3RJfm3wjFS5-3-S$EUV
zBsh+X7=Vk)(JGH)iW!N78T(Wwk;gNJ5QrtrBIi0qGp4DtO4+Z|vN=kL`~qVjKpUp8
zS}KuW{F3Xy6gi>n(wAIkX0Y=LWi##RBDqAK{zdj3V{&#=_S1I10@-!O&{`^yOlE#@
zexPh7?S9X>Ub&SS=)8p;`t{&YnM9Gy=*bAj^zXt*6e(YFDu!_`V4DH-n(fZ?b8g4A
z9PKcflPG3N8@1(3lYy*6G3!f?lm77I6p7;JFF6&{dOa^u%>I(oF$d>@cg~lbiE(y5
z$Tb_|GZV63zQ|fIzqMCL6!X92+Ay8^iW0>Fss0zZ-GR}(kw_H3ektqD#P@*53%}%g
zGsfx8&$*`B++3wZvG|K{D09@gDc@|gISMW;{UV#pc*aU4ia);OrZMArROHVuxmnDQ
zWbQAip6<_FX6t+4mVGH(z|3&o!Z#apB@)iA{32T={b4Gqy6Q`AE#vkTnql=9XE!pF
zroodnU&^*Jt>3`ezrW;mO4N1E#k|=*^d>Knn5T}MCSfF6dH_>u<r0Y|$%Vr;>l6dA
zjFWe*WF!`j?aEse5{WM3N2#Pc`6tndc1F^Re##~M2|rQ7_L05;UOuudD`_WHl1>Z!
zXFTN-;y6ju|06kgT9nu||3_r}S0R!9A4%f3yyPXLCL&EEku~X%Ou{^38oAqi;f~rN
zm1KUAbZ?XhH&W!1Ks?eC$*e{}F8o$B*}y{BmfV#(tyO#-D3{m+neXV;kUIS>5hg5>
zOEx!xzH0>Wu+a$G%(VMo(6|i(bo&2)m;+i?@=GJ8LnEduVXj@~A?)x!7>V%Ai<69R
zRQlrZ)c;i){|(drf3@WCOXQO8ztqCk$R)Qs9}?Tmow8CU5tt610KsjEO-?sK@A0ox
zvK4BQFLu*VYFKqaA=yrE59#TbYX!-&|6k+D|7xuGUyUZ6%+Y$)9qCt_Co3efuX&b~
zWzJGTVXDXbE^8(#EYqABZBvW=EwZgtGG46^3Ywx{Qb`rc$Id;p1DU1H%e6Kp(s{SG
zxoW<PD3Qy87_*}J66YxG3TA|J3tc~Ef%7a~cYF1GMj~%CAy;(W{}|2G&0!l}wC<K_
zxkS<9R3{D(5#1)qtOkfBHWMCwNo5fpVacd+Jn|AtGAYE*#>*qQ{9eFyQ$6Vm)ufaB
ziAwKe5w^pBRQl6mlFtsp>m~89r{KMk1SZqf`X^nZd<gJ*8C}nmljQkf`aOO)0rdHJ
zTO_xGNxsp6=rY>i-IA0^$-rNOsI+;1GC%V(IpmZ~*Um#pKkXDTyg5gx!DudpWZO$S
ziT+$dnZXhCd&Un0o@XUk!><JMKS<`6=aJV5Z^_L2d!+fafi%BfPLhC)q}lI#YL6g1
zW(rBwUSeobM4DZ0kdA#INwyE8-xF?-#mbe89f@Zp8L0i1isQZMckga=-TWIViQXiS
z=}+cYk0rX_sI!xNW2btD?xE|D8j@^oNt*rtA)PjziD5w|m6pU3Pm^xs7W0Bi*Nvgy
z(dz|?T_G74MXJ+F$iVI?RF4&lsrY?6QuQ#>b+HdMTF7<sec2?U`?EX!ZZer_?1SD)
zA(?!F<ZCO*m7ckzf9Ow=Uw0(8YA%!9yNq-~Ta%TR<8ZZ0dRLO@&T<mP>WQxRbpi-Y
z$su_)nOW^cl9{(iXTCS-Tx@KKmkS76yN@K%%c!o)_mHH`InrEtiWst{k`pbXNb+hl
zxiz(hBvFk|n0=8CWjwnR#hPUDv7)ga4X4PktP|07MfahQ3{z7}G;3^L*T3oaKeOnX
z_kuM4X_Wum=xC0O*k<X;*t#p^deKe#J@YoXxU#Vt*Xv2AiG3cK@24X(KPC}T4<}N+
zL8FOee&d7Y;6`qpx<ywmkz5(r_##dDK);)|AkByO>GygU(&>MM%ycr4;Y4p@>%WXj
zNA@Cj7h;B^kQ@u8o30pw`;T|@37KEpSnrWKQu6qTh?+Rl@3e(<{k;Y0R2`#hoQAG!
zB<ajarqcAb^xJbOkzQ?lY}aT>r{iyA_=F=lab!N(VmFdxP-{Zv>u~=S5-oZ}h2;B9
z1fDjA?$gre^jlX+zpF9DLf=q9bW^*~Zx<QqNBvGj|J@<E@R&3wR?s!3(eSP+(m84;
z$)E>hcxfN1cRz+ClQIbP0<$ZvLUMjT6?g4O)I*#Pn6372ZxHp8Vxnl9NzM4Ij()#p
zsi_?{k>t1&(Rt?6@5hau$%jm8gL%hDbHH5s{l1P$t$~gF1L>N%i_G`hK=L{5$;y+L
z^Z@joLXr?8UGYqiced?x^>!vep^geVC6W2u#ydB+ADJ(zBd4cqBZ@6eN#Z_-BpwcA
z{>pKZ+&M{-hX=^KA%{%P5QsTBmP#iHR2q4i_`jb_*HdHcq~z4-#En!kxv7klf)3I(
zv6!gKRix9yiwuv^((gq&a&$&IN$%&<@4QgLF5&6=`aPNV%%p3JZB#mT1+~+JYxJAF
zM7R6IMA95PgQaI;**+o-Z%#^SS4ruNos?F*Bl+W@RD(7vsr1YVx-P##&h=wR=dZg|
zvzAZjcMFWYxW#P=<+YLO_w{v>pKQF{H??H)bE88}tw?8O8zuFLEk+RC(NR=a$LR#C
zTtdZsW4CJkn@A-SNiu6bUCW;nQOR-o?YM?eM`w_k)Qg1eJBVCt|ABt*=|h$2@h?^2
zzANe9olk9cra4(WyAi+bk|UVE;mHprqP~NOXx>(meBJnV+|Hoi&4LJgZ#}_MTM+3l
zVPv4TFI~5*Nhd9cuA_dW>%K_REbU8dJs*(y_a@S;pF%vbbtHe@_zv3bjRR=UsZ`4?
zAIXXS3#dsu)evlTV{aHyM&Lo-L^?Q<C@R89zjqwf^``_X4LeVU4?B~*%O~P7m5~{P
zglhbF0CCEeHtPRP`fcWrzSZ71L|UT=aCs+z&oqt#=cT0j>mqW(c8!RdHcmR0{!T<A
zWsS`^k5J4ilJJKJ+pa6Mjn|JP=M(5EX-4wljpN9(|A<F1keKU}>3V&?oebQJrGk|c
z>G#inQ~h+?2)zAYlDGVoDBdn1>V-P`?SOTNQlhky<XcQsm69~A9M_YpIb1j3mMJB*
zA>>w&lMKK0kpix*3@ok_f1-N-=|*j7a^dU{t>{Ih)s2%5Qy3Y}E0;pPrjTlRB$u3c
z^q#=`UJz;E26A!QGx{B(qw6F&Y5rp&>Juu`?C=LwX0Merx7HJXJ=R1@$?`{}zxNsO
z>-)13y#H=<$j5>S<n_0m$kUsHNp*`WH4$H>!0+0Aq?6!HSN>PJfA{0bfOF&gZckHk
zx(_-rrR41jlE?NXZ1*N~wO|UPlw_5WD+)Z+O372q5Mc}Raiv`{(~Dq#rjp6eIpkMJ
zug2Ta_#DKXB<dH94@>XHXWrk5n*G)(kqWRl$XJ59x7#7d?{8PFK(qcZaua?}TYLgF
zoqp*xN@t|*!0(w)_W?O8Wg6W7d2%zjHoNcNc4QV=b^^A<Ohd}5;dF;L<kE!F9`H3J
zJD9rRXjez3bvlxxOkbK^9AmcBz)3e|MH+I)nRjcExHE1QfO#-^Kf|aO<5df*-ptCr
zsJRa#o&?;NnLPrA{g@GVp?QL_+ZVuBe@3?(_>;^U9?}5j$6p}~WHPqGL=aO&gWM_R
z;{>n;GwXVRJA|qF0f5tt<7Rjs%49qNcNh~#y>>WLK~H`J<CXwnB(v=s<f52EXkf(|
z#$i9;(aa1HWoMbU2WNvjhFM+;yXTk*21sL>q0~jkF<YF#cAlAi3b}ZuE)C`rn5%)n
zCo+-25GFDGseesoW*vt!Da_}3u%t34s3W?-<T=-UWwJjeL)pyJ?_ei~X)+g$dxsf#
z3|zTP%T#dPWnz=zSpgF?6I}P0`Dt*skeN>X*nMV2XCx1qh$<K;Wmr8}%9tJd0eH%2
zXMm-gQTIWEK4X6K2d<jQ{s>_$^Ia9l>X<?HkEp|QrfeysFPQoDNM16sQrLaP{F{Wb
z*UZ_G5WZmwrU3DlNv%Wf9doNK9R0vddk%y3%;wjq*hgk{BFY*Njez-W(qx(>ZI^}|
zfrtC0p`QiV$G>)Ssnh7K83V|Q&35W!SC*ZFrB(lqhuPHwSK{}Y<wLQ~BlT8SIzppc
z@G4ZW`(1Zjd;HT6@}5^)z*w)*G#>df#aPEQs>_qwpti~dG^u9eTY!)gLm}Z0D6zOD
z!j^Y_fqNasjKxd0gR#r#LEg!XL7%SN%Ty<zTKgE^R_Lc3n3-74EA}%xTj6c=X8dS&
z>cgl@pz@YkJREL)VuoJ?*)D0qd}umIw~T@BuF`Wf`8h6~?1P+-^uR$hK!mi}@4%%<
zd+h}7x-{i2mYHzJuF&SLKta=cw7hEBVLIr#{jmpSgMFmXoca<GG{y3`Rk%7bZ<KH$
zkg+cYV<K~X6CgL4_0i}uUNH}k|4$PL-DiVPHv!$gveVftRI~FS3<t_CF<6c(yVm{7
zNu=E<2B+-4X8?wGWe@j9=xBPX1+-JI!4Khd?_a#oxP2<7!H>Rmsqmv;x6`<r-|b7m
zwf{w$i3}*A>B<j1(6K1S&T@xiQ`*v?FmFg3=q%kZ3OuXj9Z<S)qXF`5%&LQ^++Ifg
zH@Kadp6@_%%+82BR8BBQ6iC9DAQq(O7_V7yJC14e{yfv@emv9Ye*)83fkdXU21yKg
zt-Q$W8GwphVyGsKcUdrhL?f6x=Hc4pd-A1O=Tk7)a?W{p+V;=?(4Os=eM3vmF0Rwj
zoIMU60kT&GI$K5miGRVF!A81`Lx#{od;~)e&5t$TqIBYB1?Z-($H>@d%9?l!lwTKg
zMz(b&y=)zyY{IoqLKhexawHw{AA8cea%yvW>$Wm?XzIL;`G^3PU9p|HI1gDjrukct
zA7_^ChHLIj1dZb-nEFlN@Mm_t0PrN^oDVO;8JjB{h+uqQz-}ZnP7Ref=GbGv&okj6
z(2Qr2hQn$a6R-(@%gkTrpqb9}3qn=yFsr6QC6~FF4YT&U%;(O)KVc>v0OBd*K$R(H
zrfQ)2hAF)a{9C55EeyV6UhaT!x76|#H1|lY^)R?sy3_>WQE3(exr$@bP#2K7NeA44
z_kq&H6CewcCa*x*DXDP=aOb3JHbNy<YFP&_;_T8Bw1`WWc0@EzaYdR;x9yg6Km(FI
zX$J~t6iK_$J$oSSPxwdD_R(nEC(^#Jk*kv4)1bNDNQbXMWwy#ztpeFD*?Tnrj<Wgt
zpm{*{1cRo+O}4xcoX2HXT0!%qY}96G2FUDF$0LoBxm<;%GqM#+L3%;fcOvi?Wd)e1
zH{RkF`jG&&Zu<<`HZQxN-fe^bL9B|3hp)vHM)AYtBd|5XEdjqrpL~St5?1;@&tlUR
zGg1GJJ%0mf=hykTcAMM@*Pgak5<Gu>exgvtcLV6j8(8)SD8J7vM|%(R7zc+(#IA(u
z_%fQnOq;a>^11G`7W?hbHz-|pZ8)wgr7yv-#-RXpNKigN=uVNS9K9DtlazkrP?V;e
zL>0?W2FX#Dt(>$IwhEMbl>qxU*a7pQ`jS;6wyN01pKd^1o%sGgK=rI9F%iN9P4qih
zcG6j<BIlyhp8KC?Kb+}V3&#qX6?b5!h#87~0mTDmE{$Ig88<T=eZ*9G;7*q^!2w8I
zq?giR%vEX%1K}~L^PAQh`-KL$;~`z%0vuk_!EcdxOG_^R>?=Jr135qGx_B7&m;N&f
z)jcWw{SbVMk=8{aIVYV?OXe);*rTwWEv>l*;ycof&w<O8dgcO`Cv~P}c)oPTAPDbC
zjT93ol$uw<lOkzTdml(2NMr6owM5!!6{`PGYM>}msr18NAbl+LrV!r~>Dsrb!c*z`
z;Sg3xhyMj!rL@x{&^(ha>j^-$v{eAOx5`{--n30N;XaZbvOCl)J7wCL@P4;!buFCP
zBil)H?o%>f)euO7W$%{&pDnY+B9|j;DS#$d_Wc7GyenH424TLe6D<=9WWy+qP$)Y}
zOXmAB%L3<NZH@Na`KWfOEISA+WwPB}p!r1BD*^Cw*~uK_Dr6^Ve65nXuLRjMnT?)^
z8ky%&<Z5M_572xr%eH{!h3rr_Xugu&>IC6y*>-2--pV$=L0#U-R#NBxK{mGtxO!O)
zRq&H6$gYO!XIbkNsM9w2lk=$IcKOrg5blyoDGs_@{#^hJ?v>xpL(TTd=dFPE`{ff(
z!=R)5J>Dk8LHR$Qz;;NUmJghh{Idr%kH{}?hItox7d<px<;8<hc1+InMB*l&K%oK;
zxkt1eI-c@kimrLf-{!#!AGsG*#!v3`0A(lSJMqja0^~l2;YFbQ3N`a7c|D?jieR~F
z4*;j-XNLd~Do^Q)T)2E^bC5;In^9~dN<MW6aA)KpLm)gW_qc<59wVQ27l1gq$3i*Y
zqw{k2?qExhUkC#}QC`s!I>~Z3@;gO-iI#;I<Ue3euec~*o(}iZ<iQ-gxGe9}4#^d{
zF$==0^4v6NX2@+#;P!R-dk#saJaaHqZpv?;1=(%6>kzPH$+fO<CPzN`4v%r<j@&aF
zHM}bq27o3{{+9`e0{LuLB=_V$P$2ofy!IiIBDw!w&=kuzH=t@I^7gbeER|o(gr&#w
zF*}hwk!yQE<*9t}J(#GFkL?IyrCfRsNwxeK1p;g2ZC9a5>g0E@y`Zo^mj`YE_e**2
zPjLU0{8SMN-^l+y48&V`z*?}qmya9))erLZH$nPQZv6|*^-2DpKUB6VM$vj<o1*+F
za61$V1oss?6>JN*wp+1wGMaLaVx0wc_bHAmfpbtip|yacq5xYUiUW2<>v=G7NU^yP
zCJrl#=~X+T_-8zX&I)4!bdD;19|IG|6d!4Ndt9-Irq%9>*2BT=sd&}~nqG=%SHOJ~
zt99_gSHXV=l@p4+n}PFJOwOSvND)S{#6ZRCNaTVQQ^vqhh{B#vE6GrW|4FEZDZ10@
zIYQB$7ORnpPV{m_E0$M+`>bLW4T|R!O>$s2RuNnbyXO^cC_EdlD4`H?qGD+dRFV|>
z4S=U8UL6HIRWX?6Sb2)MuE^ypX3{#NQ1NIeaQ7Aa?62U>1BGoo3X2u%A|QRJm>LND
zBgMTTu=E(y0Qg;|aHUYtQ$=EHI8(0RuEEi*%FC%pwkdah58)2w{=eYUPUSsXiSJha
z+#i5F$~`nl>{IgBV8}r^Wdf)VC^u0+>!7l*ErrRPlpZvC9Z^nCgC$p`69>dm<yMNw
zxhcK#(NM>gk1jyPL%Ej1Zl20jNw9lcd3G>zS<1LM(7dB8DMc<<xo`%`@{}tF0+6rl
zxfi*6%D6<Z6e@jtK(k2c-wC+~%65YhCQy_py%fkkRF+ObQmRZa!l%c|wG?M~qTD<T
zq)(N;i;=5PmPNqBN~Py2RP>qh$}DJBD_yU_Qk`;%0^HA)(kQUJQck=M+-v38XlTAu
zmQjG_y|Q~P%04PL{DBI7Quh6x!ek9fImLgrvSF`aVmrI&CJJ}3(-4<XgtIOrj9|yU
zf{7@0-w2pE!!B?G+gVmPiw2HiFLwlKEZgZWa&hbd4tC?&`|H4xz`pwi!X#Fjf?P7&
zVk*i~*|HnpyudD}399`P+jKf~(%6m^(oSc$<w1Id{VN@ouCd8}u$#e7@<iDUHna=M
zGFdByRc^7fKjI$VW|z^(k<AJ}AeX}$>E7qExBDQu%jRzfbv_$`EmlPVyH$q9D`cHs
z!~6T}6q>(1u(OWX<5v{38d@+vWZ#d1-AC-u8W=2NKkP;B347u+Xe!u*Y-)Tqo#Iv1
z?31w&*09$MfInwn(XPV__680FC|<LQ`@p?n+l_?Ed)5<MsEQBlIts3SVz1Hb|Cw$2
z1H9PEIgjeBv5%>Me>=JQV7RcGdzXl04=1*V-ac;5ZSXsAW2h#M+yV+m9N>IXksRVW
zIY9F;w{0`vN4O32Y&dgAE+BE`Qg*<Tqg-t~Jh{lVr`PQg_swu5>D;1q5MJT@DD;}a
z)!65wve&s~mtiTB3wR0Ao7^=P25)owW<r?7HKQPE4(ClvzB}9;H_+s9FCBo(=d?7(
zzsLD6gs_lvISlg;xRd_C6?2<9A@_)L^8{xpmqOHKT;x-fJ>h=Z4R|>>X{a6C72IFc
z^Hp&Z%21hS+|v-aSi_y107Na<hMM&`w{sGb7hFLZ%3g7up27XsT=y{$zT+0r{^ENs
zp5`|7+{`%SK61uyLDs<OmLu89|2hSl+xd@IklVo@r-yMD|D>GOQoH%qHz3{1pYcO2
z_VL;^aArUM#|xNn<O|B+=|Mir3HU>N3LSEA;+yV4?g&4`12nFDi)|1d<@=|>t{cBD
z6uIO42wGxz^1I?d=Eb|XL+Hy-rAdMx-#iC7f4=v28Us)AU31}gAfG=NmV)^A6nhBf
z2b0|p{#|=`5z3#Y$ygYlCL)R8uRMV;lD|P+Wi<bCAiOxsKlmBk=lF;UB(ePAKTwyu
z{I}GR6!6{|P`Sq+xCHopK0h2u5g$JlX6?niwHrJw;hST<ttjQ+bqDY<AAAmeKj9B<
z1n?=pVG>9y_;<9GQpqnJ0%0}3w;NPy_*W6gJ?H;fjT`%d|8xcLSNxhWNM7^U@4!gP
zt16Ma<E5ifvwD6jng7U7oP$byw)26pAZ_4dDZ0H)h&lka?ZTCt;NB^uX;HRI=-w7=
zdj#zTsO%L!oCMH87*q(&{etWjR1OHXZBRKVG|=|sVPO<a>70bKTT$jL?3@6ci{L#Q
zxT8Wf#hZ=^#a;lM5$tWILK-c6O}$i%V97vxofC`;;BcJK{4aQMUg%D*OoC7(Ls_CQ
z9nlFzvM|OGG%13FCao8QfyZF!qA>qY<kAEQZLwb#@`pk5iXc!Z{i<-h20mp7K@?KC
zF8n?XxtoH{PHVVZLO<Hi%@#KPiNYLV$~6dc1&a<kcLm38u#_*Hvf>^T2<zv;M4|AK
zBAWMwgQZX@7CgR2u0-%U4csHar!A6FA(u7<%Y-d7e|aK^RY=MO&94wv2zPdYrAqiF
zmiC~Z2{i~!D{6$}v>{R}%>4;$&xOKMD0?AXpdtK~V5x?s*FqE`%8GYF_kBp-3k!Rp
z)#`;?&p`T7=v0Ds{wxeB0iZ!>VS;d*SVaN3?c!HPc<(OGq*aKAIG>&bFR{g6GQ5A@
zVgU{4zT$ra;Dw*KBLe3A#ThiSJSpbTu2G<PN`@pz>>Ll3V9})&av@?NEe=A(b+keX
z6V<n1DMB1hYp_UhXaUO3i2DUtiWaMA$2dluKL{%4#5b+rTAcXc9F2kJ#b)<$pAy8V
zY$S=I$p?*)B8oksnkq)oa_yp+N4pZ2#K5D-rHeD7&@xxV6Qp@f+%g3QGsN+9fZ>Md
z{Tp(bBBo`yucG@^<Zg?z_rZL&$UO&Vj_5)6K3ANJ^IeE#h$S>Z%@>_^AX^{~`wGB9
z@$OQz?0xZU9jf*~oJ#TGVsS?_fDgsA`*8n}xOG0bAB!v8;aZv4o?;+R#U=E3m5Y-t
zfLDq}21%7z5sKuKIQJCDcBu+~LvloQmL`_Yc2&0naLPq>w?E9gs+=AnIjY+I2Et>i
z=T1o6RLTq>j;lTzVbDWWL*YwLRjmPDc&R#gz$b5&3$1m1RFUM2ud1{+aDFQ1w#c1O
zbxeY#0M+pK00gQkX^tPP8s!7B5S2Y=Jft^NV_rfhQ#G6V*PE(s^a9*c`R@k)w#ua!
zk}TEv4@k0ApEe=MQFWrx;f_jbLz1iNAA{tsDqRFFPgO$avr1H3c?ch>&X%F}k5ywr
zkd&+bP{Oqel`m~LSE?@9HzTc54gD78pQ)U$A*oh%Sf_*y{A=+aMOs^7_(CKlCJ!y#
z#ybg;wjFMx673Qf!rS&I+Ctvp1U)YuC+`Q{w<{@D->F|JbUH6+1xc49w2R+WRtmqm
zEyWIvqWgF$^m|OPj{rqaeI7`A<#&Yj-Ziwe?(^L+0Qv@}q6Yoks$k$dFK0;lk6H}6
z0hbXzRSY~!0jEL7Xd7hk6?*rEOv%J`Xd*p{!#bUW&hV`iqyM3GXBZyw_!!(8=k`71
zvpQVI?<L>$qql2g)KwVR&gkiNI>1bBio~6XF+k6UX+0H`Cz<UlAPi<Y(mf1khTUQT
z$3F*l(?O{1XU|bL>d2ZhVfp|YK+}nX>@phs4zb-2q3kfLnu$s}v98mBJHpCnI^xXQ
z3tZrV3)__fg05`;e<3}}4zoh_7`x+Z(73TOcNq0xuj!EUWWBnh%!j>6Q#W6>h@y*r
zY(6!@3AV)wkOi>$e*qB47XJ&^g4mW}C_BX_PC!{O+oLy<5VqB?@ZvN(+x{EuhO*y$
z1=28fjTA{ZyP5VkB3LKd6NqI0Sp#7d8~PcVXV`o5AdF^x<S=oTwTnn%*h7wJopbEY
zWx&O<lU_p@$4;UF>O5<wl|ejvX*HZlU>6>P+llN0NBES)K1f197L()l?~tUh^>L71
zWVccH=n~t?08i7{LYmB9X63^mOlQM}!o(GJoCln_%FeEX-D~U*zQA2)H}->x8|;{_
zNHW<C7>5)$*;}0fzr{|y2i$EoN)47Q);JI<*(`gDVrjYTE+W0l#@q#I9@}$2l6-c+
zV5k<bvQ|j$v01IbR>;=ONA2&k*-DTWvD?V}19m)}jVWfUwxCH%*s;Cg%tQ7@ORzj*
zBk10jvOOMx<uUu}UzC-xM%r3`!Wt3Pv@4#n!)TwnoE6A!1sg|!(@M6<6!=ud7E|Lt
zW2g5+Sv5PxhFlFRdkFKjZ2O}~>e%lug7i6Sr4aoK_NVXR#Y<K}OWRkh(h<1VY{CT?
ze8WC{2H{&au@zK4u=S6S*z4I^>YhHc>)fE)zz(D>@~zy(Y6!P+b7(Bv#c^a}57*uW
z$zJYh1IipY)$hRX=QtW#9JwfelpWxVv_W~0TSHB9h#Q!L++l9Z@8ERew$PmU2v<R)
zr8BqwA>b}{t`9vzuH3BU$R6WPQ|!TwODErsbJs7zCqHi1A|xlcfFrQ$&xL#sz)3Fq
z5gI6fYr7emf!sL}cQlAw_8KauI42!gg1Pw=2Myu&P)O`Fw<sJwg>vaM(+T5V&=IF_
z&i-%>bRxLVQb;4Y^Av55;%X*Cc!txS2QZpDO)=K9oUk0EF`O$cHO_IVbY3Zz+emSZ
zIPN$OIV#R`4kzGfJokcv{0UrJnt3F0bNd3G#O<V+VKP^L3S}u=1_csRxt8`wWG`?R
z=~Tl-Zr>AdU*gv6LSY)Wp#z*r=PuEb?+Q0|7}&0Ir`JN|8rMG-b~Ct0>OQY?@p*Ww
zZg4{>1enP!?hS)CIZyKN7MHXD!rR<`wNT08){cUqZ0-{68s~7Kr4$3W!|nYMq`6%G
z)=2JhUsF$!$L*z6K|a^248Q_z<~k(zxN&q`uaFa_gY-V<UyWN)#2um)_5<$oe{i&z
z`(TFo5-yz<N)NgDbcEs&=Ru*GQtm5?s6FN$uZ3nAr%+QY{R!8OW;{>1mf=t>=VV_&
zwSo)11ZOI_Z85M^#Vu})vS(a5?SE8rB{{HL!wsgEt>w<u0ba*Fr0K|Wt~nive!=ye
z1K~@~bP2A#;&h9k`I;L*J;Zi?DxH})#-I6@)*tTt_BW`L2Y;OQ#yt586dLy8&9r&s
z&Ck;S@58V60N$6MF$`sX{Jo{{@C5Hm+h6{?Eg6oU<UMG)7r_6w07)Q!bSaV`e(plR
zPw^WpAPeT(QtuwZr#Qg1)4Us<`>}`f?++r4;3H|PGLkpb%ruI>u@E|E_=4838_kQJ
z$era^AA-Rc{*OtZImb_<4Wd~74ZYiO{4k0@p63($LNlJf{|p``@Xu)GkjU52+$M>i
z`X_u!=Ff*BN#PIQ1w7Txf9Qww0{`m*s9xk3o`&ir{^3X@Y5c=PICGirO=ERB|N0%c
zukb5|L-Q(M6bsxn-a&~b$>4LN(T3OgchuY7;G=2u&g93^`JbEoG&<FAiyuJo)7yNr
zP_Sh2zWs40vw8cvpTV8O|Gfolcldo2n8@X&wBdS}KN5so9v{&Kr1|`t=FlwQ_tUob
zJ-%)UXbSm7;~>1xKXyW$ig-t==mY*&nt2rS+3C<M;opx%?jir%4*2w#UpWP2W&CZL
zMLpr~*(vn+l<!LQE$6+?f~JB`pt)5ge}~QkRq?|q0`iP6DnYKApVa~?HT>buz}51P
zjw7k#1M2~J&W}n#onG)w)<gJ`|4s&julNSq!g|g3r7`sl-}xs9-||^sgYzAKu%8{-
z_q?D*BYxm_nBhe|U$PK|ANiC)Xp&ES_BG%?^Uw7lZQ!eC!TeT%p%vjaVY4Slw+jv-
z5bh9q(~5nk(9{i@yM+4(z`0v!HVrI$1iur|+$)3*Lv!sDxIkz+2)X6*!L){4MrTkQ
zh4D*JctF^800s{V-RY#oA)%Ki@P~!HwDaI39Eb++i12VCG@XSE=bFLI?4@U5$X)0@
z8fHC&NJ4uGK04IFOK?7b#9N4=5za^0Plu6wg_^D)@e>-BA$LO9<p(Z*fwO_-q_CbA
z3<1Itgy$52Ld+oe5F}ir!^x+F?R0!1Sond?h=vF^X#Rd$h_QEugQ3DVeUJ?k#?$IH
zT<AzIQ-n~}8^B0m$Qk6Kgk+p*!jd;45{^a-cWFLzRtUe3T#WEw1ajwuro#b`6}kv8
zA1AD$Ro;1F@=JIaFRb_r!UUn&L~tew9|Isv65PV52Tc~(M5v|+zgM6zRq&-{+67_7
zFCe`rw54_3C86jzyhsxS+ETkLEcq9f(uLKh;nNji@;f9~g-h;m=9<tx7`Y4~qbW>W
z7pgHE$5J_h9<^IS^Kz8k7D^VNow9_1u{?UvY~jEDP|Xn@nPKUU&_Hv5T;V%9M0{5`
zvmXZY1g#3fe8Kl4yeJTQ4T12U5O)Vjp-`@e@V?+q`v*lrpR1_L1HmsC@M0nRB`Q%O
zw51bC4~4+}D0?LIrIW3t!rApQ^q`LgKibJH6E4R<^@*_W1!$fM7e_#+T-X+kidG2k
zzCl@~kWLZ!D&g7BV0$LK-iSI?3&FG>Tq6jJkgFArFGNx&v~fobp9_j3V0j^Y{s8z(
zVQyz=z7k?I5WW^NXv^6CM%dLG=HCi8Xk+M|@D;iLUU;<y&GtbkodZO@Ff<)yABD$D
zA^aqaqD_g<g6}xgzCp+tfwHaQFZD37O^k6sJ8c*DN?>A#=t#ZmPVvE6sO%CqQ;>YO
zSQY@gdqjcusQ21M6`k(cC#KQ9y`vcL8xRM?U6YYJC^}LY%t_SHJnD#8Hy(DKMJ4St
z92L*}36*2w_Y>i-n<)JiLJu*EP78aAo4o+=5=U-A;ww7RY~4>x-3x;!#GoZ;paAjU
z4denvyMd1O28n_Oc0<IS)Onm14@N;4D!S8*FHDqBge_d`O2NknQLz*FNYNe(XQIRb
zbVtsJieKPpv^dTWnrB5nf3U=et!NYFoY<7YI<caW0{C%aaUcNaMc;5F@nXFF3JMd%
zhp%8MQQSkPk&;Be803=0HBaDoig=|QDyiauiD=*pVsI0vTofx$pzM;EI~sP=#DXTs
zT^8MFLnvJg42Bn1M7JJjnX6*tVF0d)eSd`c4DmVz=&p-hz60kC@m(QBa5BYF_!38P
zQ`DUT+b!|cTd>_0AN&m$bHs{~$lVc}QIadZT><X9;>-Q8lqY`Q8#MXi8QLT+5Pw|)
z_&xC^ty~I4GrfQJMQJ}6ED|GVOnM+LqK(mF(WeAvOT?(oQoMf;#XFTiJQCN?o@A*Q
zMq$p!;?Z6JmWh+T1L+g7)(31)#YeQ?Q7(?619uhTRWAT4MY9V?tHcXD%ASdZUhuG5
zEI$unjX2L8xLVP_1j0Jeo5H!z#pQ(%z7S7h)U+#Jiib=v_)1(rLC@FXBAQOU5xY(V
z{;lY<3uW)bRvqBsd-2`hXv7bq3r&RT#gj$Q{3y0{LD?s9${D~viz!XfP7UI9I$O6@
zwSmG=+f?<P0obl;QIE1+s+;u??pB?zh6Vc`)h4=6dsRitfY_(Xy9ZAlR1<rEd%voR
zw(1;Jlj)Sz0o8U|d>>S0DWP&mb>J&Fb6Dkm5ayj!%zAJiQT<HQIA_&gvjK2Xt)a6e
zuB!R8;6JKLtAyQSswCQ6b5n(OhuPzH)mz#~c2^xA0jY;duLIsw)rxkIy;RF-p6#t-
ze*v41D$^Mzd{rAnnD<i+?2CJNLZ$u<D*mdbG=(^+Dx=v=fT|T8HwaXXrddXi>c`i}
zol^Dv3rVm_G8u+KR96~M`_n4>fqOuNs{W<@zcAIWe}g7mbu9=w5vsbe5JsxHYCsdE
zn!E*;&Zwp|gEP^pFbd_LRn3!wG*%Vc9Jx4^_6<nStA2Y4&Un=b+F40Z^{1dzqAGp^
zSdvudve6dFs&Nq@OHr+})8VgF)nGasdqGuAVWo?za@uyeq-sL(t2EW5UNCW4H97!@
zbX9UsBv(|&x&m-j<r|N(YpR1ZkIGQ#>Fn2aRm4rO+)#}s>P*%A8PL3`+DseYw^Ute
z&-b?Kxg)&DQXSUO_?N9pT!JJ=)r1=Ojw%}G+7OkJe1_^>)tVHP<*8QE_?NFbJrD*9
zRHN2G<(_IH&29=+D}O}tKo#o`w~JM?A40Q4Rr4#7Qq^wyxaqO#8ZA!BRLRt_m8;r@
zLRg_H4N!Ez3#9sm2DfTe$lownqiUH5V6EyXZOpz<B~OCEm#WRqzN4DiGeh9Z2i1SH
zwO6kSnG5}os!ep}<&&yG3eL}}18tzvpc<fny{&3@3ixhQFG)deyZRix#5>e&Lt$X2
zI;}b2yVT3K1F&12Leqpj>ImwX_No`>qJ8$M{c6DJpbq?ivi<6>?Q~GgQT-hq_CKH=
zOEKw#>fgQr{*d~IDPTLS_Vq_qoYWC?=IDqzkpc(K>YN@>aZ%4+gv3?-nHFJ3)zNFf
za!lQu;?!>HcKwhXSHGx6OS-F>{eXL@YfnSPQ+=A2R9@<ZLG-40tG9d$7k$*MH*&t}
zuYFKMKlLg*fG5-iwDaq)4xkwLNwtyonF7?V-M}5F{>BCmgVclQ(Az0>Oeq`<R=Y0-
zJVf0l0QEhscBZ2qq3XTV=3(mCUMLG!TRuQDLVe~QeJyiFz4{>vqt*ACz^Sw9853YI
zR=tUiL&d4j(YSYB{ffHBc=cd4fC=g*3D8Vbe|H(&N$RZTC`(r7(Y8Q}I?)JRsybo=
zI4`KHJ_B%3y|@FszohP@g84M{2(ousJqqhAyCPj3M~}`GwV^MPt7_wEB-hl<l7Pri
zx1tkB*VU<?0KB1o-V~NH)p{BsZ>kqi!0(oN`Ao3gR{MmZWwO)-ZQ)b4`g(8Ra?~Ld
zGrFT55`nT@b=FpB-c_&OiJO+Ejtl^cJzu?=+OkmHfp&oJtHbHJDpEVsrr86vuN=Z+
zwQUYmOVnd7At_b&qSyYh`tQcrtU5CtY&Gf+8_-U*>JB8VQy-@R>$y6u04y)mITyhB
zQf;RLC$H3D&!O^K9b17md}CKfwnZ)8s{5>g7w^=UX_Ml;`Vd7{KB$MUL#|$3N$aMM
z>LeUSReVy%(pL_j)f<aY)}VHK2lHDs)2MsfrU~5!OWQTsv^Bm%lQ#t>c4|Ut*xaRw
zS_a{6&E6?U_Gms(V0f>_K3op`K8>DEnmA~_{u@$9&6^gWIiNB00_j1`uDfWxLmJBx
zs2tX8r8nD2^Y1W}9nn0ajV)(Q5giS4(S-a2*IYG`baLXTW)lmtW19ATV9-s|gEpp)
zYq~Cj&|Nc>z8CS(c-fnQ##56;E$gL8qGKrDnqC}8eKaBS;kU0Qmp<6=)4Y}=cR~|#
z8f^ZWyEGd-sri<saRHit#{m$iX)zpb2WwhP1!st6t`BmjHD1N=DOAIM4V5s>5DNg|
zny;xNjnMq(LGNFrW*bdtqBPUvQMEIgXD#7Hv?c_Hn{jq8i-F%UnirMu;+)2j=A^Nj
zp51_t)5OsM?(>@Vw1*Y1sq#QBLE|om-9*je5Wtf({b}?})--7X^C_C{beJ+#6G>5s
z3mW|Z`ZDRFW(R%sdP$>7g%@d>%#-lxvL@{y@adZJ0H|Kkj4MQauWGtUQFcw^6^I&U
zXjb(E;JQYn`QHuAIT{5sHREUl@1~}}1)R4u3(Rozwx$gSpRzPB!l0S0DclH0b2Le4
zE*yE%yxR+DuIA!=n7FICdmX?$%{dAV<ZEWoZ2g{Q#lP^PP%}IRZ1***M#GCD&3JsM
zp?ILVLT71;HHW)ESfZ(-DDOi}yYZ;@BTfG<aHdo<kPJT7<i16&OyfbT+ozfZwEtl*
z*Mv8Pv_jKm1Q3;)`)@!~rCCJ-^fOH*1stk1!4#6L(Udm_cdcgXx4_qFHnu_Tx#lpn
z%nMC)18}c3=V{b^qj9HB<gKRs9?ITn9_)hK?=}8(eBgs7_AnZ@Ui0Zkxc$+tnLPl&
zPny*SLHb$aG9R^X(Bz*&vQ=BcLbyXagFfxrshvnO#a&u!ChYFkR!ETS(N1sx&0ejK
zJ6QH<pHo!ZLEDuMG3?hiS3|{7E2##{0j+BoR1RuAXlCl9HPGtuh}J&;9PrLs*=jiD
zqMcj}6Rz3<`cn0%Hsdyg$F$wEq2i{UG#y?X*9!ERv%5BqI#v(usE=Ut)P_*p!Ao0A
z(F<>_R}~EUXwT6x4PWi|zrn7b){)xcgmx%RN&U57(TTQ`+C`1qy#d-P3Y-UOC$xi3
zkanFnfTy%+d%zZ~wGM`Ai1q~`PHRJ{fkL&NN5O8GHp>$#;o3p;ctvRI-+?7kyW=oS
zL}_1qf}>}&yJ&kPTH6GlzbnpaO_dPFXfM-*@0`}`LhoO!b_zWoaoX-KFn?Y<@@J67
zYfa<OLJ41dO4e3VXOg1z`3UY*?Lm6vFKDBGL+&DCH7L8J{iO?7(zI*$fcvtx<uF)E
z*B-RO!c}eR0+3zPw)z%cWN7D7-+5gdTSei{8`?iY0L;{$q4mryZShFtZfj%qp%JpQ
z1KR<Zt?f@=HRfoC{{u^Rv_*6<Cr^7T29D-y-}QtS1zHh*!9a0Od#*VEh1xOGpm|?=
zc^I0jNV|f*e14$)suz-C?Q7ciD$%~4NAKT5?Je3Kd!)^b2clGa3*YZ69&5uYz+I+w
z91Ybc+CelPJk@3%0(ZIgDD4qeXs^&VaiuntUid2QpU+UIXWAC@=u~TyijdT3@2^Et
zs~uAgK%KS?g(046L!ZN^H(I+4&e-2-{U{#xP8(bW>3i+jj?np_efSO7>a|f6LH?*^
zGGXGA)|~=9pS5>sL#07`gaBK0uAXpho36MO%C_suE}?9P?$iU|cIuwcjAW1Q9(|v(
zSLcY+7m9tl?|w((pi8IO=YG3xZ9QCc)QzSo#R1*5N=OgthRsHDNLNCG@ey6Cad5_2
zC!xT(i;la4%DC!!(uUVj-A~m>j_G#O;TkvHkakcxu1lkr(p{HNTZJCFj>#zV)Fsiu
zCNEuU3hDdmey05eKb^f759tYA>tG=Kb#YITJE@C}K@y-lufshE)cv*&bqdnWn+xD6
z-Ai8>4AxzF3Vev}=359)>pH$gCBk*m0%%6)&SoPQsjC|Ul_*{J<p7+~Rd<ADv@RXn
zl!~)D<`R+^-Jm%?!QpedFfXXa>OS>?PMofky4mx(M>|m#uUjM{Nze@`1$UxOKNdcv
z=pNI~T&nI`3L5x=?mOBwy{L0uhTJ8cS_$)Mx)n#JnCw1uDm+8CRSk33b)~eKb3^Aj
z7T`=>^D+o;>U?SLd`ma>62P~0@wCmArCTxyX0mk;XvZ-}w>=Y@cXW?mLYS-j&kxS#
z>oVs8P@tQ92P*e;qiDmjP<Ouz;P-X?DB@bAyKSfawFkOZ3LuJgYBlOrqB~4$)`z+c
zv?ugPhm$;b>~($Ui^wOs*EBvq)!8lsSFSsL5r7KaKdn(#saq5Y?kb&9fhs-IO*saG
z)w*dx$kpiD&;g8EU6)S~*6Ci;>4@h#9}UGKUg$a%!S9#4c7K5Tm5#dt;agp@6+XSw
zouc*GdtEsl$@!qW9|g90ov$3ikGkK|ko%-tKx6l3ot$Po4Z0m6$ZglRq(^gyKKmc2
z?9@+hiLzb#2pW)g>!&+IxJMu4z<0xQuV4KXh5Pgux*>7Ue`<=t{rVp$AnK@>-GcCd
z-cOF)Vf}mO)Tt(WIvo>m(I<|FAy<9mG-w>vXVSj;F@3@rc;=?RlnVXh`X=;by6Zd8
zOvgi?mkSkd{o8s}#YeAx1Dvn^0R>Y0^uN;%<q7?`$GDOH`c1T{a8mzO8zcex>ona8
z)Vt<^Gf3}hr_F^^dY@-#pJ06$MW#dbsc{g7=^O4t7_Q$yV?l)8*$Lc{`afwvjM6u!
zUGX#ej`P44t!KBwr?YxbKir8}{hWO$i_;fTwD7!MKLsrD`X0rAC+JhILzt+)kb_*3
zzM__vJ;{1uF%T*G7&?iQs{dv&k_-A%a_C&tcWPWd>pe$;CS5-{1IZQrc3QMu)u(oa
z!E1W%KO`CY)_YNQU9ap1+ztJV=5Q@jpF^8#H}!LA`{I`VKtBj?>nG94lpMWRDxJW)
zqyLZg=yUaZE6^r)_1>+J%hP+%*|&WCK#GhP=vz^A<(_`oey|nlZ_<!|U%zq^07d#N
zN02_ykG8_ZL;X!HoOz@lLA!FLdOuobJ=T}d&{w9vPRF>P=#S|Ec&eX?p53k}*O$@|
zTA}}^9@1y};0b7wYJD^<n`-pmQ14Kyum2V*b^74#$UWDGj0VjMeYhH}_EMjF5P(<u
zYe4|K);G{5^&5R59kzR`uS^B!2mKz3h}Y|vFGkCJ)aUL1?vuXtKPa<**8evS+ztAU
z)!^Q0xK1z3Hp6fVU2Zp&+5y~QI6W10+G&`M?|>D%47a91bDtq<7Vr*+UKBRlZ|F|z
zZ%4yadae!_2CfGDpkXLg)XDIP7WzjF(<%JxY)I?`6&HgqebeD;Hw;;Y^r%5b$1aZ<
zJo<pm&9I&RI>T{8acAJ&4Z~-_u7@G(7Mj%4AfXkCmthcXU3nX}{{q*149gsm^EDi!
z(|vx1;l<!QVOUP{Qh&oe8E)Z8!;&oI0t{U!ARlP>nr4DQ2K&Yoq^AsFbgU@Y(DEvP
zA%^yuAU$oUqy2<XL!A!7FhdubLxvlEqIG+O;ZHg{9BD9*f@@KRN{X7FF>Iv)G1}lj
z-!`5#_^9A$jA4NW@N<T?Ljj02WIaTc;tWY0QFh+2*?ts$#~W&PpxOxrB^~)oH2Aa7
zNiryCEtPC|Pt%wb!)#i7r5b{0ui}EC*KAn2XqY$*Dwhl&LcpD7_(Wa9WrK$X!gRy<
zpFn-ZkVmJtt{TRz0`)b+z7~LI7=Bp~z;%Q76?!gj7~H8d$u#`#i~8O))Q<(tEkouu
zn7C~yKLtdVVLk=+vJFFM5tL&%HVtKW41w>E<QfVJVd<`+jR$afhO<@(^9`%Lfh#b4
zh(+$6p^iGCLc=iH+`eyEOke*O84gNCynhc2E8jz>*zl_d%$FD<Zo`>}hO|-8d1M$y
z`{<>HCS#!T*icam(lWyy8eX3mx)b23;piabDh)ekL9@y*i9RWLW;jC|=hcSue<G<d
zn5n<0HL!FTxz5lo9<_dMa6*j9u6SY4c14|D8a(x2du8b80~4<eyOUt>jo}?N_gljs
zbd30&VSEsB?+rmTIrw1Mas+JkhWH<0@S~xnKU6*$EStdn*-#~c-3Ehy73#ay*g}JQ
zx6SBI!TRmS&*a4p<2)W^_MOIObP8ve@jXrVb{qRhQMkuwp)lcI<JbqF*=HO|J(Gj+
zav|{hjdy>57mh}O`h)|<8+2OYpz#%j6b>0@yoBaqqmgC|PR37t;ph=#9R1}AXXC6M
z5V{!upjn8k@%aV7kJ^p?M0(7aN8P)d@eoDRjvEKjs?FW_n1bgX#zO);^fU%h594M0
zkG6KajjQS4nUB%<9*M6pnmQUk<4QXHbHbSKgq*)|9M$)vvA-YS0mdyW(9D6xa3AD?
zj5kLkcgkqzTL2$ytQ&+R#MqTSbvtd;(5o71{4WN%FykybG!<_AW+&JpjLDx+7HN#9
z297cgp9V+I7$?(qX|&O_7Hx6X$kL`+jM1|dl5<ApCg8C~e@|G5Gx8LJIB%Td1$ex%
z(q036f^q)^a3>l?HE5EIbMycv8%KXal42Z2e={M~I5iE3OUAp80Z218qln67qizfg
zrW^Yf0(Zr@Za7@KYFtQT`8DHL!N6r0j|iZ?Zan`F?A|aQp%`hVvF{d8-!vX=VF&3g
z<2Px@-ZuVO0DP7)HV@p{#@5Zy+&RXZ;lST9Hk?4S<r;IS*Sl*pwnQ$^cxVb#@{Lz}
zLZ!gCV=Z#`jQUT=6&nA{hZpyamQf%pG7hHgss~2@YWQ1hOd5||iSgxn{ILYZLu0$i
z$UZU-rl3oy(bWq4W8)@@fs`2we}<(e#=X=9KQ&6)fwbIsoVK+qj0toYxzZT*BXCv5
z33QC?nX&sQRHE8=%?-I4<GSb2tTncdfERVfiQPc`+}KW!MtEUdfX`^1FV1al|JV<@
z?~IRVTKC>Kp9a?t#<A_7TW_30)AEnTRY7p^lX1^TsC+ig^#!28IO`K~TTOmh@N}E0
zzY?aln?5H1u){RzC{%WuhQ$H5%M`o}D!Wbf2cWXYbeI-jdrff>aDSi4)7}F#4yGP-
z%4@%=M;^>On%+?a>wsxA1-uWMe(?p(AyfDmB!^92G`Vv!S>nKU#57<6RGdx!(E&6U
zQ+wK+aW!QxMRL?6pN_^jX1YrqtDEVYWzalsy0j1N<!RDp!9y?8gm3I9^fswP6#AHM
z97N97^dC;ADf~<egCRU&8u0?${w9~r@bIMRyG`&Sz*H%MJJ7U#BD@GP#nMvnlu1TM
z8-h(5+Kde`4W?PZX_JQbQ9?}{n?NPZ#JPex+*F=~T!d-kW7@-xG>xI7D^aErs`eRE
z&p%)y+O&qEv}a8WO<!Y7YiNh+oM~VroQXA+P|L)bIyfLXZyMPJn(?L*1IiLiEJfH8
zP2ciJl1%StC6H`#DMFHB@~0i?RMUSHWxZhXYoI>(qG_=WCN7!$=p9cpb$JWb%O)N5
zLg}XKJ>c3E)AJ@kTs4K!8MkYuXK#?pFg<bx?z$=819iG#(w;<FrYVf}R&SaL7J}uL
zY1Ut0xotWUjwH*Zrmyd_O|CTX<(R^9plQEjYEO%fT$B0=8vm~8R0az3Oiv#omv6$+
z2E1J+Pg-){GaZ@-X9`U_>09dirWLe;DKZ7qQ})2L%p2y5O|NM7USj&%0P_z`kDsFK
zk!eUel2VgTARK*cVkpj7W(u7F%_nwKCLJ$%YHFPV-^xvEvp`y5`f5K+RGRM6B&5pp
z{VS+GGxepN_-a$jt^m}SwmgGot?4Em%dIo5e+KU7rnPFYyfBs0Bmc&<c`R!7)--D<
z;O|U_X+QtH$$lPXA51f8L$BUs|KI|)kEU<wq}?Zz_FLpWo3iMHb%UvahSRO)efg-&
zHuJ*e$Za>@*aMm!=0BZ~+iAW`tGQj~HC2G`Hus{#rF+an>)^~@bNK{Rd!KnP9gT1>
zJ70yr`_04CQRZk?4uSat=Jt($u;-vTvIyBj=D(@)K5QOJ&N!K+6mB_UuBM^K*_;vx
zFI>zzca*uB>vCZJs5zS6kz?krxxl%Zqv)LPaq~NhpShcpDbVL(K0~ugPxGK=AoDWo
zC~n|wUJwfvAM>pO8h?Gw-|k1DpLxhhu$?gfLobQH`4M&VC(V(xfDbTF>VsUM`Q%M#
z2AK~9LwL%(hYouMo8LBtr4VxxjVq_kTWF&z)EqPeEMevYH1!KN&wPR;!n~U9WTaU~
zJAhH<ulLgXcgF0YfZb@b?_@~NnjbPyjWKs<jf$Q#&!-7PtoiXJu*I3rbcf1$^R=$1
zMZ9_F9Qc%AzOfl9iDqU107+*1pMWQu2armN`L9F(Qq2>-g=-hg->gB|MRRgE0GG^n
z9r5Qf6=~)wGiWZG<upj9n+H-OUNIl}89G<Z=P0;+&FmO}dyrxN+Xr4;H_xHH${XhM
zJ^*Bzle>cZra7CIPPfc+CZlC;n{#}?nPn~*4q>)ABOWR_=DkZHyknji4wYQ<bQ#L*
z`R1-JuvB3F?J^qSp4nRkhYQVXDZp~yEOUVQBJ-iS5I!)kpw&aM`7=FNC1yD-%O09{
z(&@5C=C3!xr&4nVim*R6>*>?VGV{XTu=K>dd?;{F&GySED>o0k2kHuQPy7uGMWx*=
zr)Ry&ywDLk&&-;009KpTGr?A4W@yD(Yd+=;_v_5(P66@U>_r>fFU%Wg_59MD&w%Zf
zSw0CYugznc0{+IlA{y|w=9wqp;XCs$6w7~a?luEtAI$S<9I7`*Q9$)0?iTIKe=>KV
z$NIB*{{{dX%$sSUu+{Qa6Xdp89uGx*w_Bpu!Qc){e+vxmv`nMr{w~YW6xiKu@#bJ@
zkHt)t*lU^m6x{nPPv{F22a5yk)$F%K(@920i&g>L0n3rK&^&07*(tPm$P!NRlf#xr
zACNd%=3fTe5lcF46gyk)Y=nx7rI?}(u9h_VBXvhDD@wq9%#s!l^KO>@LC77qG{>S=
z;cl5)0u>KSOPW=BT9)^OB`-^OD{y*ST=v0&k7fQF<a{lMW9a?!vy7uv+6ha}DIokU
z3qC>Tq{X=zsvThQdyOQ}QrZ<Jf-IdHpmNHx)gL|uTWV=g4Y9a4fy!x1%}C@zElw>^
z(J;&PHQ)@lWDr?|W#S?LA}v0&hL5uJNruW93p<^ejTg@{|1_j$E%ugBjj=qUdD%J3
z%Gc0|wNz0&Io@*k7bFQ5BL&qHEy)EaOR{`R5&C3H2Q88m%RIVisg|KM3%_8|ra6Z!
zZfc+03!3Q`dpOKrv9!yD%2mtV3OIVr650Z}49ooOXoKsPjWkl;u!PJ+F4K}Q0p8!V
zOpJ%-Ez3!Y)8DrIx&lsQS$x)`EZgEshi`K%t((H$9gEWjl;v9dXia+8axx3JJj=k*
zWnjy<Xa<A3z_QI9h<ldVw5%$$OxcgJ`<9VOaIMI)!UZNCSV~(0SZo=c0h$uai1}!k
zhZf^+&JMpfwa5R9+!ISF&267r?6eFlw*=1tXNBd{GUO^PDq03sS(ec$#b=i3B9dxL
zdpZPIV>z4yw`(ojA23^I>Guluo?H4?0Pw;xuPK`1rNu^zx>uGScfk4D(u{h9H<pDR
z;O<+?2s;f9?<^PTjP-kq@j48Cu+-DRs(MRs4orNsxSPTK$#SI#G@mVzN1@VSSxnn8
zTdm)(McFp%e)<A^yEUU0=66`b&B*PvUe}^*m-Q1(8g^S1vjEs*J(~<ed#%}bVSb-A
zWdVIK>R|mU8V>Kb&Z9FCj@E_q06btVq{uHeAO-_?$l4+oh{M)P_rdLCU0;u~Bi2_J
zQRZy@krtCK)}1u^x>`LSL3q@fUWeQ<>xIs+;AVBB6PU-XDvH~9TD$n75?<EF20HHK
zZB6eEgpW0(2A=v_U(oC4XI*|8_!CwuoqzDRexL))C#^>6xdW^Mkp^0$Xm%82Eu(Lc
zPFaO*XzpO^c$&(GSkvkJ+G(pH9|l9MBRDi(n6>vxB;nRGv}B5~_PQm(P!VbUXaY@?
zRYBi+ov}8ht~1*DjVl~JYu&#ONsKik5r}iv|Ly`GYYkAsQk?ad4JbQrHBq=J-kL*e
z=mcvxZLTC*6Awcr$?Dx4)XCNZQsh#shv@UCRO>mKi(ar^`U!^Y7p<A0sLUnn=zjrB
zv)ZVex@^5c5$ts9?t!p-#kwpSWmm1-VdSn^7p?+ZhSi;-=hv+&I`VSE`dct?nO2K8
zJiKW=v<uv~tmPEZx@`^X4==K;tLTqfWLvGYpO|B<Z2=2+?A9g6QJ8DJdJ~Ad*0a<j
z<ymjLLMPwKP_+xJ4fM6(J*%3QK84n==xE=4Yny8T6j@8?`0E4f&H$J%w#NK`T#0q$
z3;6WVI-n9{kE}<NV5!s^7zw~*YXtQ~W!BUiD0^bHvkQ?vwLT=aa%=Gfn5eLt)i6<M
zZKwgT%Gxd*q|dDPE&*6=E$I$RHP)CQl+{`%>_V>2x~vp!@!T3n@6QXXvOoNNX`Ml{
z^;cGBimJc1nrLJDjrC9ZF88f<>JRYnoi*G(3wGaIKT>r3gY_(ZXjgB2K)WiRt&@L6
zuEBbXy2q`yX5YZXHe1eF;J4e7=^WY)+j3g8@3bMngICSAp2A$aZEgy1?y)Ui0pVWT
z>#@k~vn4G7z`^!i22}Rjf?vR%qwU%wI_`A9HrxiCgSJZ)Q#xd;ph(_fTR%E_>169h
z#~_Z_66kMcI@^3`n&D#OJdks>8E9#G)OMLewU61B(w2sst&C;_$8Cjqz`5Im=BT!Z
zO+g*1r){PPPA}VAI&a}^b7)E*jQZG&B~bOXm5v0^&vx}HXinJXRKb$JO-X03PTKmf
zL=s?&Zx59~TTKA)LALm=NKV;$(qXS)+aUT9F~l}>4SYInTR^>5sO>O|vM}4E>qx?F
z+iC6{Ve2l!r%2lroN%=(qHNxO19-;v6`d80wmHyWm^y3o=m9TcY?fUpJ7?QX(Ue%*
zY#O)XY_d&YJ8#?7088<<kP*lw*mw^liMCpDCdsytPQxYJ!fAPsV#}sjU#e|49lg9@
z8ygBk7i~ee;GzAJEoC`Oq}kGGE`8aydp~NJZY!rX;T4-J?Ot8AZS4e_Yqrt(FrQ(&
zd<eqpwqNKo#v8V|C%~3zyGr%FY1>V+qg%EW=b>`jW_Lm^%NEF@EZg?$M>JQCt@}SH
zyJIU304~?ry1b2j_fe=7+FoUY{=V(nNoW_@`b>q*65HocSb1o>Pk$fgku7Np%1Uhx
z6r*}<^Lq$fnT@%RR()byN}bbFTl`@F%5AM_Jgl(YkiurA&A$Y>D%-+Eu=&j9vkJLt
z+sz}WV~tI2?+bjb?T-?0*VzXB44vn;R?ZN<uo)MD^rfv61twnEF4A7)YuiYAG~U?$
zp-(T~+G-7O=AErIePsIH7WW9r2irj%%Ia-Cv<m)cYv+pOlkJ%!41Tsf@qkK$4G%Ql
zt0vAX?I7LOB$Yy_+nfACfAnHUlYeRYzO#wnCjfUfVP1jl|8aEPaamSh+>tYFII4H=
zy%%L^WonkGnU-c{Ieuo@w6fC1%ihRF6lBVht+HfKnF5NkWP=JW1W`c6-}m&_`J8*t
z`JQtx?{lAf&pG$OnNeDYp}8;$g5a7fBW^$X+!#t9491-?@jobdFy1}{P*28d^gMep
z0#&edgt7P_FufUZ3t+*AvHlMbUxr~n^!ylKMpDSupJAB;v;f8gm5Ky1=6(S#h!Of8
zV2(20z7Eh}#(fUZjxlaimC<oVQ!hY67(H|}2xWXp_r^{zm^9sCjO??(4rgRi_C10z
zHVH10vF9iBMKRVNfca=fLLV%gWb8&j(>g1L@eid?V;Ndo%tai-r50%MjD8wL0;A<;
zkW-8tDy2(g-1z~LNsQusz)oiDS__iGxJorksf<V4;C&inKV9HRXKdV!#?uV;1TfDq
zOjP7_mf?K_bC|*Sv=f+_j6WzfZp~s`xPs1X#(@T~IgGe&be?0_mx1ImJ{v}39>b1q
zT;?+#odakABk(3H6*AsZ!lx3(B^K068Omz7UB)P*3q|FOGc^#YVC?aRGv^tz==E61
z*h-Ie6{C*|1F9J}sv%ipWz@RB#ac!erF82UuThQU1;*V@Xw);-P{OH!!J`{njf}Sh
z@aZCBv<`MJF(MX#G%@DT6MUJm)CnG5VSMQdk!D6s39wrjPu4-Nl`)sj@@))F4;0!N
zxBlBDGT!^I6q{jnrX5QsBasePU5w2+5bb6Jr2(yn!T%hi?`3#U!l;k&km}X?8UMVC
zp$#yy>6mnl5l;E`>kRECkQ<Cmltmq6d|d)E#E79-?M=qf0gzh^obT}9G5)2#JB+WK
z!QExV_?r$av0i=%<D(2~9YF3goG0PY7~?N0cznP(_Zs>hGCr<@@o|P%9*j>gW~ebQ
zlMH?&Bp)#>BK!p&GqzJ*^%I7#1>6+l!xv!SDZ}&u8f}^TaWbA|#|)ur6?>+9FJ{+)
znMIdl9hrBn^u~5#eogmQoSEJ?q2a<Dqjb0{^Y1~p>&6t($=IEFfXWg)nD6I6#FLr0
z2Yp`51PbOJVe;s+F5XNwy$O7n7ni|NU*^i?;QW{ezJiE9bIU*A0+_W_@)O7$eE}qh
zX`e^?(4)-1DMk{^JY@?{k1-4B-Eo|`d^r?Dm@oeTE|hs}1IP*HHHx-{F})R-l5pmM
z6W}74>(-+$lG*J6pH4DgI0t`Ym~YXxJ(jsM8eAOnlR&r~&wNTL@&x8a7MwZ73^UWm
zgA$o7x#&z{{=kM)$xL7R#ilR?N5G{rcm4~QH0H+7;95GfmvZZ;nYYN%GfXc^ikxN6
zq<laI)4m@lnasL<Xv|{TQSd37xw8`_huKFtk#o#%TLG5K+`0=Wc}z2MBL1s>ebMSK
zfmcP$)E3M_G4ogf##X}grFko5uATx{#@z3LVU#nwC`ehsbfLrhd1l=vpjI-QDd=9s
zOr{rMHS;;D%c)_$OAAvib4(9X$6Q;3F<oGC6QEGfj8Fr*f%ztVW2%vP#yWz|i_Cfs
zEL~#mc?l+(n57i$zsx*9Pudmc&L$`}GvB3GUkh{czl<33Rf^QMF`s(_q@Bs6!@yPM
zL<>j<bAq;>oy-lCS?XeXQdwU&^ItyHdze+pXzXPc-G|ve<}0_K1MO!%cN~@mn9pqS
z-}xKUdVUQ?F~sCcF_|}+Tj|Yli+PQ<Teq3vbhN$0{39PCckxFAH_Ysu2Y>G|SI~=c
zg!$6Hz#L_^zYM$gng7u5d5k$o>BI-jF*+PRWbVBJg>h!bMsO2M+_uM4#XR5z4<9k#
z`tN%NkC`z}ka@x!r}XO-v&IhQpE9Q$Kx|n-G?#X)!U7nyXZ=iTfdlK{XYk3Hl}qtN
z7uL`u`dnE%e4yaQ@~0{UcUH}x0P|o4QUJu0)vyA3UaU4cD;{CFQ%STp%jFH)9{R8j
zE`-CrEJ-Ii{aCJa{Pky@UI#9K^;|Ig4rJx4U@(Yvh(6$cl(m(9kio2bu24V5Izmt7
zaaOMy&V;afK7_$gRxO2=PO#RU0|{egQPpNROLPVb5v-CGP>5vdCh0zV6zhY}p%Kj*
zxCZ@`EH|p!h+&n{3Kh%xg4TvOR$Boy;#q;TaZX?ziG?$#SR-^2OJwDI3zEe8{TsNQ
z%!;R3PhqkDg<dKvo{Ce_SVsylmULDDZ8A@@!pcC-uuS-QSZAGOJ-H6i43^auFqy0v
ziWz3H{yhMgY}Urt;BXF0OTWi+tY@!5GM6<<@yI-u{TLeaS(+Z86|ltghbd&e8v#d)
zSjtIo#jL0gVYh^3ptY=&WlQO?GFAW`k;_>b(*S0zU^UX#=RC`HA7Cn3t7r#Q#X9sR
zWU5(X^lqwQu_>up%gX&3Fm<fCR26W6^#%ue^{fDQ7;Ip5(vh=~wU3IbF0wwOQ1&I(
zVXC)mVs+4mCoZ$9X_~LF4jqO_GwYi-(AQ#RMN`bam1S$d=-XIPbR=nKZIgk!%E}yr
zr4H5=CC1yy67~S5i<Llo`)-y)J-8m$Thk!Y%X*Xtu8;Ks-J$DewciKI0BdUn^lq^B
zeS*e8*4uU<L#ze&(0G$IO4Tj5SXMEe32w9EHlgzltCylzcUfMuAv4Un_X%d`9?P%?
z+z87l6&j-~Q4>V&vzBdxhhwazRCV!y^^oqnJ!F;81^986Z7|GFuwqxDZ<3WpA(uz2
zbL%1Un6;V`yiZtbk3(dN<zamV^Zb-G*BNNG?1eW#?AW;!aI$CD)6u|z{q{<@=E&YV
z7uZg0?NcZ?v$LsW%Y|LN9U`vm=PE(m*v9u@(4E~zZwU|fT}Qa>$$n=Qz`WQCE<)i5
zdpaGFz1i>50_DS=x^9IxzU;$Y@Xe3CFBh%;Y`cp<3t+#`fir>ZpJ+20#LiNn?<jjF
z?Ye{6-n42RV~Z#)cbq+qe)1vg>8@}sl>PB1uzQ02>X(2HW3M`k(TB7DUIV=dcEmi0
zM6y}PA<c?ni%k?sk7l>W!_rB%tqh7W?8Bdci)A-I3+y=deOh7S*)?B5F@gOe9g$D5
zN2uT}k*)p$3Q6o_M_?zjr|8*CVfS4Gm&)Gv8hlD)mr_10oxPowl+)~;Ghz1(yJsBa
zEPLmF;gJk>eh@5Wve}DZDT~dmg=jWAdlM9M*o6&%ImezypOwgE|Fsl@$z$s%XO_?A
zQEs$=9Yf<SWG|wic@cXZt#iffDJmf;VgD<KzoqQiU!bv!y<soF%GpYKA5^e^p=Zl_
zo;}nBhpXAH9cZm#H~$9ETJ|)5G}f`lc+j}O&Y;LoJ^QN~a1HDW`!V`P_G_<0@*?|0
zAoMP=4^nYJ6PrV8$z^stJ-%1iIsP!w%+96C&KCBuE)1!ay^6MoZEW`f^tGGVnn-9|
zWxq|Q(hhbRJr<qpi7hbE#ok8o?QZrh+SB&1U*=#;z3hYj{J)l17p?(wjotYjtY2q;
zN#nf1HqvHrknL6pdqeDiG9ce%$3F+{TWlreGH<glQyBCP`@1*McbC1L7Q|up-V&hP
zV<$}q8DURG0A-ZjB!q?g?6^e$8)Liv2n!F`D;GlHA-ly&q5g69=J`OIVE@?*nMw9z
zM{tkW{KtTK%+4@joKM)X@4)U9`y_?;p0dlRLdTYq;RFRcj#CsA>^TV&@X&!1OSvjX
zPQ?+}b>gIzLByFe8UzIw4%Y%nSI$ZbP`Pn@KBA+JJE!t2T0J;ZbAj#2`H0fOUL0o$
z`i^k+zKBL|&O{N24=0;q{Jxy;>;dY>8Tl8)pX0j+b^|zfC7A3$&XsVO58}uRpnjC&
za1~rICk9)AS;siB{*iw#u|_|J{0Yu+D#;1s#GHp(ILBc#NCfBB1ST|+lShHLD9$@c
zFc;0yrNE<;9Q`~@NDSv_H2PvWZ_^hj<2b1Tka*5v+7~BqKINb<iBm*{AIY4#6y-|c
zxKc1BmGg8EB#pDwIuo7goKNTm!fB4vTNv0G&ZfK2Kg-!a1FmIovT1jb$;qPERTgJ4
zeIG2FGmp~9IUJi7ICGA3e=kIGImbo#L*{WRe*|Ve=g><)Dd1eAR74@?e|w=<#L1yO
zN-@W#8_*>j`;RCAT*_JQ4YrI^(T2`)&Z-^YDmW@F(9Ux<Er6$$oSk%grHZp*2$rfj
zUr?~QhV#L1Fj33-=nNF<I7jng=>o^62AK7nZ`+{Pz<F~D^VG=c*a&iwGjbV?mpE@y
z(!PoF>SC(AxXf8v0>vwwi}WFpX3p;KV7G<yl_w0gayHz6!8XpnbkJ|-1g`*hmGi`e
zz7CH1eMok4V(4mb7boo#kZ#VsX8_j2c`XMDy_|gu;b9-A?++;Sa}Mo<-2u+64e<9G
z$0>onqkf&Eo(07loFZCr2RUmf7&^pxoC!-eIR`o*dW-X(JM?dJ-g*KL?{HGJ;O=s6
zQ~GR}GhhUFkMl|jhCRZ0_&yXyIfrRYzt1u4fXEofpO%~loJJoQddTs{8aZp6WB&{0
z&^p0+lkRj)azvE2c*Jq+1NWGtrc%@=95r2|n&Nb3L;oqKnDPy_Ttf?p9e4WkAog6@
zukgu%+fMgU9l0y%Q0&CL!^W_kxvjLOyKuK|0CDB6q1Dih%c_C}ckaSCsC!ts9<<UQ
z;g0oT6yDr&y0z@XouGi0FE>;PML%vC?T!4o5fso0;5NBHA&|TOI!F*V;cLJg<;v;6
z6wLi+7e;uDTd2TTj&oz8&=<l@`Wj%N+>blp;R&w)I7Gs@gS)_mbFIo)I2FMSq%dS8
z_a{0yM{#AFz(sQxWkc~K_bDBmW4IcMB*$_mX&({C<qn`Po;xia3JF{@eZTe;w~5xu
zM6Q~G@=4rlUO-9aZnzECQn<U8!rxS`g=)gmxZ+0irE^QI`2ao5Et&z)Gu$^QM0u9`
zy*IEkxNWpdWpWcY!h9CjUk}i1uDl&0Io$WC2Id?$`x>xwxmEOA&*LhCVIrR!K>3CO
z?&kHdRLJ$Z1@$6s5dG$gxl8G5iY45}Zje&$hWF?QTgH8swr1sAe=1F@;9kkXJfG+C
zzXfO|H=P#XDz3-@9#(VpE>Ni9?)ep5EqAFLj@EH^zJ$gL+|`uvs^><xLa%|FMO-6y
z=TWF%<i6z$M=x=gQe35p8$2H(m$}*N=`zR_?rXGcHFNiFg-i=KaymL&xenJc-Zt(}
zbYs1p`<S-gSGi12pmlI<!y(ei<$eyXi~HgG7<M=JhjFO)aBCHCt(UuzPQZQKrcS8$
zb1%LF3j^Hh6o_2o&ZL;hb#9akU532DolfzuL2mCn$P96(OCfWUyYh21-r~MVZ|U1y
zZ9DuP=6WQe@g8^n3~(ddA82Mrxst~~yU)#{XvrA&#b~HM;LhIye;;zcrYf#+?%x#N
zoZxPuJ>(?!AKJS<;!fKFd)CKX#&ysq+&RAjbc(xxUcOJcOW%f!El=|iu<dwU`katG
z&xtC#9e8Ii0mhN{9R>BBc=Kuh<IFouMKdluAG!tL%KMJO#BRLj>Cf!WQ^|nh!8=J2
z4o}`6lzZ{w`HrIRh?VCU3%|X2Jv3iFyhsX|`SRYNouwbIjEbrKc{OhWEr9nIZ7c(M
z23lx>cu7}a=_qfY33|aip$>h=cr_H_KhC>CWym4Cx9QOi<qhFQGV277%>fDHy-R!M
zaNgj2^hNNjSu4Os@^-C3XB1COV~XY_(7xg%uaP!PF+6{IvB&b5v~0!kzM+(QJZ~P2
zDS>yR3XY!Qg?|PQ6M5(9t(3&m-UUhKjZq*qh37&)h*Vyi7UN9gJ^mL8>Ab@Rpq%Cv
zTB&;F4DVe^8=mF8NvHV?UgKie&E)Mr0sSmqVj?VM^9Cuvm&4nqgBRy`e=dbWF7NQ~
zu$0I9gNo$ydHr076!4rV_EX5)z6pIryzzSU74rtaf}s-LWBN`;DbIE<##zRD?*vue
zm-9{>gG>eQ>?(Ag=k47FQpro$ipDCQ?Kse?dC_ZuUBk<0MPDs%eImFz-p&Isae=p6
z3zT}^()A!0d0P&_?MuA<b6~KEcgG7uy37;CK<^4~7oAy~dFQDtzJ<4hOP3*Ac?E1}
zwDAh*>ptzg5vpUl%KMm#use9q48l?;ZyQBPyLjB6A=1sWu7vwNylxe+dwIEPsQ2++
zcmsX?yh>Uc26*P35V^*CBMW-hc~kWMy20DD6wrgbVA>T8@dA(0S@|Z<M5PC}cz@AW
z_BKz`4YWJF`cPos<$3%AjbWbM9(Zw&x2OanBRuVA=o{rNm<5>oyiEFCjPb(B`v<&~
zj{)|OSM@*q3CDR65#T0x4Tmt^NnR?IFF)e#pqS@l-Uc}otWS8uwB?`TJwFNZlqdKB
zXtw-+DIR6V_dN|_&;RaIpgHhED6{Cu&!Zb&PW%(Q;Ds}P?Tb)w;k(Px=gQCd9Ui*z
zxk&(X=PRie%!5Bd@d{7=8rrgZ@ek9rtt0&Tloa!}@=NGE?ZZ!V2Jz*8y$_v!{Jsik
z`15^=zy<K1J%~vN<d?n*XM*@2cYz$`@1SQpn7`q5^c~|zx<UOoe~>myA^h(*qc4=7
z^dYzt{BSC3592@c86?B`C3GB);GgaW7s<Cqr2{RB|2qYaqxs!N7(B`6UWH5ye>Md{
zV);91CmzQi`7d0;KS)ni0zZmA*>H-#F9z6&d>1-mB=KbwSx@HArLm;&m(p1|m9M9O
zbsB$&Dv#3nTPX>DmhXNJ>KXjyR=Nk6$q#4)$>QI<2bpaC*8ib1hd*N@V9xPB>&IN?
z@}Kbsb{^k%8Av|=har#x{!3JxQOMtT8s>}meA)~b^B2>7hZ6qh=@?5X-;M)P#$QQC
z{Br(p&%r_k--S++=lSnWSwSoLSC)WO@h9!jS<Qbw0}j{lm;V9mTK@TVaCQ9HFVJ^^
zulp0O)$`MY;2QXObi8cjm(tnuBL6rQ0$t*NLIuxF{GAk-xy=9iHJHD`e?I~W&HSGa
zVDv5gq)uSA@(o8Rjnl?=rQl0DzmguOtNhGVkPiMWA+S67Ti0NqU3@_h(7O2yics|M
zUvYt@UjC160PW+uG2l}_|8gbB0RPD<=w0JCS3~4F-}wNbZ}63D*d65Gx(AUVe)(BU
z&`thNIO14m-Qqt(2g}?1+EqZi!(aFq<SzendK!oMHuR+5<J*n^bc7#8p_ozrd^=#@
z=Rd1}-Wb2|5fmQqt52ctA-^^rmd5#WvSD|Ezx6wiN&f#%fIQ+)QT*#MznHH7JmH5^
zY|J{v&sv7@KIPB702o`rsz89+2^{KyW-nmSCfq?Vi~c^2f<+Y8brST`9Z+Y%UoT)V
zE&|{4Ag+RGbmnmrBs~PEyTHd5oQGhI9(taFm#Fl?OJG?Gup@#BI*E7-Hc`^T$0~3O
zfsC)<(;s2pPhg^VtG}S`Yxoo-*x(56s34El-eAFxA!s}%c<CZc92b;P&M!o8C<*GJ
zf@QQfJt5d@gxxSfu^5907l>#B7$K;m|DhZy(9Q)|lwc9n#YGEVqXp)qz&b`*vlzi@
z3(#T(S81;oC)i0rxp={oe}J7J_%s|Mrvy800wz)L?`I%Mf*<||XOac6R49`oV8&q*
zQUz7CuSyd{t_4cEAc5A-(}F-MGd&}iOL5?{f=b%8X9&t2fte}TZru)zEWx2fv}OyI
z%>kDq@Dv04oS^*yU~&ZuD5jVvNTYaTzTh4`%>{xEN@Eua@_vS1kzmy=pcM-~p>o_3
zL9+!4rGo8Ld0Qs<mtu3}0{IO<R|tx~1b1Gr=?92Z3f$9ZOHm~VrT9*@AoWWatPw1y
zY)P%4hss6k1m(2!Ul4eEqpw~Nau_BW1Y@58tx<6BHAr3*ET-C$OM=bI;9--%O0oFM
zf*lLccSTT3k>6%PIKB2;1n<*6p;ho#2F$hzg#Z2P+IGRqRJeFm@C99|?hqu=;@2to
ziX!w~f~^!G>=w+W&k*+rv<E?Y1>+q6MS&I-$M*|V6HpisBv5Yant<1bzUzXYZ=vyq
zAmI?mpx_fafDH-q{)KBd1<SVq`j+6s-7}}Hn{`{TyA+*w1fRYS{kwt>7Gp5Og48U?
z+!JK{fW{HQ-wuEo6<F`X{C&ZtuQ8Z0fr7Ro<AR428=nxE{JT6^R+A&FPYGsIn)<1r
z=?aLg@Hj;c?S#fC2-*vOKL#uZ;m@?JItry(;GBfNMZ*VY;hsMHAzXxQ_hH;s_{x9J
zlrV-isP4i_O0#(gpNfFuDU5m(>R!UBFen@m_R!njTe#nv1?nT5Hvlhug&+CAPd}kY
z1xDmAoK7oufG~qzn}NccOmIQMC&dssD$L6VXt40FO7tBQuA(i#apA8N=nfIi_!WZ)
z6;33g?}SiHo5?WY1eM-|3$tlM5FzBg57#1vCG}K186`aN4A^L43H>@w3d=pg#Rz|=
z^(j{P4Fw6}gkDs~6fgXU9?b+{4*ji93Fp^>OB9CFf|Mk5FG6Foa91J*nj#FP-Fm99
zoi+q%!X#QN(}kYTW7bX!UyTRm8R2T~Y!oq`6}I-k;S6D5C0a9usfXcHme6-8^s|LC
zdVrlHoT~=*IpL+B(3dMbycu@$gzF!oFJJhN5u`vU8-qfj@Kq%yuShsO+rRP1Vr%_V
z7%UTt*2DX9VJ6k=R0w~fIM#XLa3N4Cg$wC4R3&`n5J<J~U@A~*gnsm%s}=r6JCHhI
za4sCYAe>2mmwKU*Ldy-pjX3~o6n?w|U>AkuYoT{ZxQzn7O~L`%VqF#%Slb|TMR<-1
z4Vs1P|H90)3GeuUYZr$84$-T^nFZiFgiS-}>l9x245UkVhl)MAg_`w%=@G_mhrwRq
z)9vuEPv{#DFZzYf&qHKDsH0`=ns6ySQrCseG=(>WVd=me6mI&OR*NCwo)gfxDZHP7
zIlLtde;F{hg@0^-Yj=blG+lRvZ-0x49Tt|;RgHVXvc=FJ5k5n4no*&aR>%87NdWrB
zgv+LbdmyaohffcM!L(wJ3t#;J(={PH^#(8}g<W(-^N}$BcY0et7EVit!6(9N@4}fW
zp^RR1PlfmCKBBE?!7bRe6ZOqPpS@@k)tWkp))xZCQIskKjFafS1aQux*~1_%B5w+7
zxr+7_L%~fnLf^A;7qwCd$wO36aZyjvu@As`i46FST4x;*aVXL2En4#5^<~lX6z235
z#nB7WPc%CTqwp84=79u=k|~rPD4KN`eL<oQx+HN_^akBo2o@DIWAw*FAJ8B4xablU
z?}v!mg207}MxTN^A(AZv7baTtF6@Pi-m68UHA3{^1GGkpX50fCB{I^26fMf46z56N
z<2cxj5jn2LU}8nrs2C?sw3A9!;zfV$g<gUvT7$k*qG&FBN)&DOg-DWU^m#awEb{Mx
zr4&&>2S}=DstF=#BG<n$`gBpAEexHuie8%r_KfHOtutpufBy~943V7xjhQ0uMtG4W
z$_RrO*`k(LVJSxxa2Z^lX!_T%lrKuBNJW82`w@I96fHRey&}<#OF$_Wt#1G+5xG+e
zyi~N$7XFrrKBpIBxu}dT`&5Xme`mte^P(HH#j6xe-wIMC3ZPl97IllDUn3f-0cfr0
zH7X*i6A38paY3|)0)O?Qf(CfeAo{}%CK^RAC&Ax~qJ=EzT@s;+0FRnz2JNOUi)MAf
z;1v;%7Sd+Xy7!>hBD!pKfMTmCh_aGxqSK#4v|W_zh|a4bLpNYLMB7iHuT$jBg?^Xl
zZ$F51i*i>(q(|gM+4WvgJ1sYTqW%exeo@^RObm$P=;Uxs6h`OM>mptu6mE#_QoZA#
z$e)&}AyK51g5ftsE2%2*mdKZ`+uRnte*mC&L|xIadslR_9>X3MwSNu8d!ol3Ffk&+
zzedA@Cz?%5%YD&WiWH8CBot+OAo8CC%0to1^i~)by}t;36QVi6;3h?{o&n|~QEogM
zAB%*uC|dhO^!*gDr$j3$2K!XBU=ky=70cJbZ#(h!YM8edAAJU#gZRS_z&VO{E`Wzl
z;y2?!oW-mD+ct_9P&~|4JaZV0ZsG$aFySt)r77_chwOu%r?`PO3tnQ)O^_pED_%p^
zS>EDY3lx3CgR}<vihF)Sr=M7M8Jxek`z62xh!@bk=|J)1QA}Hq_~SV+aa7zw5#(U;
zw<GZPm^hghujAquX#W%<=1?V6n0P}9W<6Zo7zMou@oGN$BE_G-0DDp5n-9@vjTX<R
z$m&UP&UQ>fjCjKwOk%9q<0xd}#Bb!nM7;QI`kq9B*w+e6r^N2(!6k}IUx1@Y;$u@F
z$>Psx!<Hi6p9_Ce#Z3c1NfUR`$u3=d`5mB~7MD<D<&5|Ug&59?55<CHSjCGexR)t@
zTnyi`#3vhpoh^P)0^f4PYZ=fuCr%OpJ6G&<8<z6K9aJxrFaDWM=LO>L=0l-S{0W88
zi^MNd)}mOfrt@@(xXcN5OU1jMK)p=NPljH(cw-1eD#U;91lW18^;z0ZRf^mG3yp~9
zZGmF7IMfE%HR5*4cGZfT%Arvwjv@~)h@C`GtQTLr2+#(xkjkqX#clTR;-a`46|l1|
ziGOs0Gfm=GV=%(Y;zg8myCQyJ8v2^W?+<~rh&$;EnXTe-D=oTh;#b<>Tf2Dt0=TQ<
z=jlM*A)ZY;%uex%UBK=V+t7KsTO2{}<R0;#l-cSPul@!Ked3+})r^SW+y=V?;##V;
zxhDRAR;}ye(kQ6k5MQQBw?VOpQk+BLz7JsGrns?@iVkmyzo$au+hPWt@a~9LZpP5=
zic2am3B%&4AJKSE{O0c<BjVqtLt#{0pAGl#i)-{SF(%$419>3Ms6yXEv7WYi<Ko@)
zW1A3f9zx@!SV;FwABmSQ2Fhdcv$PUF5#NZQXpybt07WD0B(?9uH+xAd)rUAp^c0tJ
zl-S;bsFUOZoim*!)2R&JMN-!V1y@NN9XZ@2J1N@ZE*b8I7ao!=bZgX8QcPp<l31v2
z_lP9p3#fZb+PRoKAIbZlLC;qb5kl`jKgms6jQk}ZQ#3I^@)OmS1xg$#xDX_H_%2|M
zO8QJt43@|!0(MMN_Z^0ITq1o73L%m^+u=;8gqaGI6Otod=nIp~l|nCEa+S&#A|&t7
zc{)<^#U@BbNp?s87A<*?JhYya>|G8vM)K=Qh{j4@2>@uE<Qd8w#Y;+0!C->qZU#np
zO7ir3_>?I5HWz(KlFOa2lq{J;t5%A{jnadu60ZnYN|U_&G4#?Uj!l3*Em=f)+B1@8
z0zuA7STDni49Rvnz-L+|Kc0kWmc*ci-E2wLhrrH}yz)0-&Po0_28~?FstJhXN!ES?
z^ZAnPIy4qYX6(l#7D`;x0aGN2O+{a^WR!kLC6XVSp-?Jmivd?AIb8v;a>;&g=v7Gm
zq$TCN<YzihS4ymlF94=W5*!V-TC(q5pw&qH>C1|>lFdAfuuig@PIwn2L4{DPmyD{R
z&>;CU3MLvQFEm5sqQpZEkxP=f8===Ev40t0mnGY2A9qC(Pe0&hNlGD{X^}jg1BF&e
zMk5s3B%fK&1Fc=cQlRy!<ZTfYJ0waf_3V_4XQQu6Qhf(@dnL!|wAv?O(XORm^2rGF
z2PB6%n67J*lfIC=F7f#YA~z&qwon+9e7+52NK#G3oi`<~pNGON$xF6y=C&l|GWzaF
zt_D)H_O7JZ0-0gSS_;tIleE&tb3}5z2VRUyZquRnzGPSnGA3CN2ZIkJ!xXK3C<(WR
z+vAc|6tkL;{7mP>Nr`7GP##Idu@HGIVNHjHCz9AV;Ng_y=~h5Lm8_nIK3nNKS#wt7
z!IMU~0NY;bas{mpQu90D9HoD=q2VNbpofOD^d%-hU8JX&;9R9SbRKb&mebPhF5Tw;
zLdX*9C3<Zhk?y{THg9PSZr9H8ks|SlCruhg2@OB#>;4$EzckeeAOX^wxgdekaS6r{
zBrX3NQ*c!3OUr7oRQL_lk4by!wRv3XNr{0F=@~lwg-WZ&A#y_M(*S#6Qm-Ar43~yk
z{m~jBokz8Uk<!F%P>ho9qL+WP^!HxqpOlJ@Kr}`gOpkP|R1^W9;-ukJ@)a-rgU&_?
zQv5G8JZRGS4}hI0{c0vABuQ$ZcT%$SkO%rwq<bk;l`5@S1uji0r8}eP(&rA*Iq|gg
z>K2UYjPzGeXq=UP^gW!(knYWbOs3S74A3m8=`i}TrC(CyDo5%y3Wamh4~N0!O8In7
z%#$wY1(z=^O-5gV)OZ-`g;HlqR24}*rU9i`nzjNcWzrMJFzRyY&R=LFQz6YNh3I+d
z{74L@Qo4_FEmhJt>i}9U{b)7NYNW+A=&O~cu;E&r^noWVU6B4tg#h)^t5T>pNT<<v
zzZ#_%+hO9ObRYeWE=j+n+s92(cM7{-mhPDX^cAV;PmpG5+sE`TS6Za=9zmv6`pbEs
zwMmV4fYvVcr*Ai0mCj#+3F?sU6``+F`U)lHx}-l*vanlvn|`r9(wFFiZoSg!jTmU3
zH0v(7e(9D?AOq6<uR#5pbk27m*QL)>r0s?@nKDI#(*L!BScjw|v{>GhKBoQ9E$N2c
zXuU06yA9kOsk0HT-Iczc2()48KH8ezljaVB8<FN;0_dnTn_j8+rJ2F-a7=o<4qy+Y
zU33_GDE)ypK;zP=ZjcFS&0kQMlpdvh?jz|5Hz+)|O7je`^h7#yB|xX7J63>uD$O)Q
z##Yv*0k)m2l0J)XFS|j{n}aOr6AaW*W}+y%lg#x!SaOy*F9LCqnf}Bd%~jS*i9|Qq
z@Os#FmmQ|ENDo<HIXF+*T*@qa$sFDV*b&*DYhR$#TV|%Cp^wa|7M!mvfno%HvQ7$v
z`OD(^0U99tkcwOaWv+Pr%?gseaRKD0tj7zMf@M8z_=_Bq*%boxxUB9|D1^wOX|o?H
ztMUt9Vx6Gt6%n#Zx>6M>dqPM2DA^xBfJDo_a6@0L%=I9&;$&xpK#Z4tPw9XJS=ber
zIVJ1m!s$fWJN6Jsk}ap5O0w)Iy;f6XPmV(&Rp#_F6w+iDX{Ae-=_zh{S{6`*ft-=O
zYo#61Sy{saxS1haN3XI>*#>vOWXWz(WFlMkB?a_yWTEx|JtsR!-%rVv-JoK*JlP`3
zgXhb3(mG!tYo@JSp$r&!vSgJrVZK<l;|Guu8S6guN@aD&0ahlvSq?ACWvL4PMG;Kv
zDFO7VWeQt})W{amM>lF^eN~v%I@#K4a2I5rwCSst-Txa-G|1%5u+b=+K^88`R*}Lb
zSywo?CRykyNM4rt+=dfZWG=JO*DR~ggr6-kIpynHWv+{0s7<E$8GY@tvsQYruFB%*
zDAge=-~*;pwqPOjyJTZj8qh6^zXOdP*)po$>XqfwmrnX*hx{PYFN^*a>H{)4ZTqju
zDos$oF8g%}9K9i%qyoA@*>y?-49R+E?{-s`wg6zaWGNIiyDfXqo8DP>WS@QlZ|=&P
zi_tkOoA(w>+>`yjA7n(<DFzvpZKloQec2=xHjK$WT>$bxmQ9bsLz!hWres`}y%S&)
zvV<0(Ov-$Z!nH@TgXf_BShku{-A`nPQebFGc4!62Q<-QnRpZ*q4{QW$C-0sH4SRVr
zRd+bZ7gK?=qr7n$h?6`p34N~e{B~G!ljl;d+Fc&ZL!*a0W*>;Bd_6_bz2r^?a7W~y
zP^F5uJb-@2KJu5Ou;42{m;(_%`CpOX{N>}QWwg!;kULU^O`tr&37|ppkYC{NQMu!%
zPz;uTaTprM<QgLykIVD&0U9C~9RLZHdsCIv3HjGCKns)4S%@D}xICd3<|E|!bTo*R
z&zS^fl)UpxC`8K-(?>E+%Aei=W{iB!6fmu^@&+YnoZPDoBwn6#9-s;GVk#9pB`>7o
zPNIC)FW{2ojr2LrWVwOv)TPKbQYl)h+^HE{n*8H`F^F`zbQpF|%P$<qteugkQx^ZM
zyoyrQ8S<a9fs!eIN~ITB@}+T5&$h}nkD-wx?^pu%oV@#GaJljqX-AePU*-%hUw*(B
zJ{8EV6zM9IPiuyLk$m|WM2h9-UO{7td^i#6rSdnjz?I2=r}#p-d<7eN6>@Dg`p(Pe
zpMm*G`CKZmu961^0=immolSM&HS$r~#@EXAYtUIIXY-+PLEcK&^XuigcVVeP&T7Hz
zHOkM%V4g0@E8c*KOY&~26>O3>jX?dfJg);HSLDCiz*4h(O(pbN<Ze`H+bYkP2}5o2
zq@`$Vm;Xcg)vI!`mEN5la`A^?JLQ|{a}ix~=@%f~@-OL^-y{Ek-u1omnlCWVee$`P
zXzZ8U?FKg>ABcqcYw}-SgEQCVZy~TgYe>%eA4G1-IiV1_B|jeyySL>Z4T8HPXS74)
zu3Xv&y<vHRhEC!4<gYw|!4Y{OrDR6sBeu}LFF)c9#WDF=8*mTg(Nxp_P(J5*OwhPI
zZx&`|Lf-f~hCM02N*kU>at2*)dMsZM0PH97Z&*;6lJBOM&r|uq8z8odEIQ!ZDUt=y
zvsc(^=s&zWD88kd07u1jT9=&^+YiGTXN4_ocw7{JIH1o}QS=Ew-4t8Sfw(I=xajjx
z#M#1oPemOvg|oaAnUm-{qIi4*gYZ`TZG;IQ#e-mg`6{M=3k5$#?RI$KuW)`3h5{5p
z$PQa)1uBMOp&z8!xe)qC6|I#23syXM1dU^g?Nl3iTw$gv!w|(G+P;S>f@lwTLQ&NW
zE==+LN^s$dJydcYp%Bul6{%4B!;2`z@<(WlR(K`@<)k8)4wo^C8;hY3tB9dZqcu*k
zf$k{AE1rK9Y=R=#1KcUa7J51o72D`hO;RkUT7qQ7I0bN06#J=YB2}@G?jWQou6~QY
zbj8|kV4qf0-hlZt3S0UH%UQ(+ayvtjNwox-ilDtv$WrWI0qAT+KNZpBSQRm|p>a+j
znFsw`#p_IH<SBY?WA^eD|D<7N3KT9Z^c5=XR{^F-p{H7rVnqp6yq74ZQv{_{@vQ;a
zWeQV2z{(YDKg?l;;!ir}oL6Z5AX%ws>w|ig;=w=QY83~sf~!;Pai+)Of})MG;`NG^
zRO8j4IOqlwjf!<#$XrzXOZPc0Db@u-q)FjSXM@X%w<=)iisH;Hh%_tQGvR29Vk-v*
zTNU@mfzqbf8jZ$wg}=XD+!8B`Zisg&>=%M`D-K_PV2`5dV>sWdSa%R0eTpGE0re}s
zse<tVMIxP0uPH{UD&xB1$vR-&P`K=b-k@U5B=m+9zug46sgUh~`YpxFRLOc<u}y=i
zyQ6rT2e7+}-{~IFup-n-L4$jW)pX1sQS6{<j#0%9TBhzRPSbVEF@-1noE|88UWMXA
z1?O{!j4MK~1A9Utp(y#J;$0GXq$u`*$YaI4XgKpk(Jlw{l)`B%rst`Gy9Z#l%3T-1
z*(n#!g}S|RG?rpB4$5W<%{nTZX(4t}deC;pS-G8x9bA+z{sX^VmEU9l+fDfsy$0Ns
zXDILCp;Y|_&Qp2rFQ|Jdf1r2p5vAoB5O3v-TB!RdZ@9yfud<J72mF-nbVT%5{_z^X
z0+gRe(l;~%l`jPWCP;a{2<DF}zoC6$u+niS$T8(RDd;<{)KaZdh_c}_^h1@K=_`^a
zl=CP75T^W&>Mg^S$EiXkLfPIAE>bx)9VVibKhPo>tz658PbZb72S8$!36yS(Repw-
zuXR?OGIRwr;+3ToH%d@u(7X7Qa?erdCn_U4!JScF`3~f)GQ|Z0%}{RWhNT?kM#?6f
zQ?94qcCK>Gj{q%HI#P6^NI7FC`ihn1R{UXVly=duTc><=H$*Nd=TrQ$UU`y!%+?0w
zNAw43RMyfhu8Yc@JE3t&`6(TOo0N;Ez+G0Jp-@<}vVIFBTa?@B4s)xrla9D;%9{>w
ztzCKM8th(GHa0@CQ+YT5mb#R)r~<ZI8FT^z>`{)=8Kzgch_V6w%Dz}A3|N($DY|$~
z8RrJH>&gYR)4QSk!w&j`$`qQtA!VOEG;S#qX&t_;^!qP@r))fizPrjH1{#Nz7bpjM
zPnk+}1tZD@X=of(?xr8oedQ1IC5kcS;Ye@~lsoJI_E5QnzB@Or{NfwRFHI<K(;j$I
zDP0Bbu~IJw_7i0wr9!8aF#`~Ns{HIWU~E+v1c0$q&7%l{gUUd+107X~zhDqfst+h=
z=ByI_3gV*L<i9_WWi2enIK5Px=*V<LwSacs-YQuR%=xMoJOZSjD!KrW{;G3301}{@
zNtyIOm0d4LkZSh(Fn&x``y3#TtJcxEAw)Hou7HKA8g`@agsO|eOJS;6qacy0h4~ml
zl<IE{M50xt)~#rbRjr*3FXB|oP3VkQE%X6NRP|NBV3KP7KA2BdB~h3tO?8Kkrs=Bj
zQ8;>9wTJ3NGF0a%^qi^MPj$vwD*nsh&Z)kx!H{xQU(-dUJk^91V1+6<h3Jb^nQP#E
zv1;cyrBF*$2V-EcRP_~YRmxOc0sKC%8a;)^O4Vm+;Hp$}qS05anu-E;jVgk!nbfM1
z=fatKm6<Ar8dRUr;kQv$7Y2hDRlm`#h)b%glniK6$<~2uRvqksdW%Xs0@A8FkVy~t
zRn=DvpmnIasg}7@HI@dhN7b<u276UA=zQO&dX}>1{i^yLm>5vG?Z!Z_spiw$@{Vdo
z92)Pc@NZ}FQ&UZ&V8K0AAr)PYsEQY$Z&dXw-IKqs`i0J$W2#4i=zE|V`(zp(@Q14A
zaLA0Sp3ovYp_*v}&`H(W2sr#mRYHl$$0~L;$P?8Xst=n|eYYOusp=;?G}@{c(;a?0
zwet`f?bX^rs5_{mzXO<~`fpo^IH_N3f?a3z#40qpsNYY+kX+TLXeVlQQwM#DPIvX<
zIE>yyt=a(2Q@ySS=DpNz-oQSh{_ZCbZ?(fq(C|~U<Du`bUQ4TTfchQEO$Vx3?jS+x
z7h2GFRPA{heZlI2FJSPPdXSC2<LWuI-8-S)QVd7K)G^CJ!mVmY+8afv>$1@qss56(
z%28@=I=qNhzfHN%lj_~{mW@%j(lZjP4ty4kaq9HV(2rL?_bkSnpe~}P@09wdSo~oU
z)qCiznXF#66bdQo@(_?zb#oRJ($pdKfKFH2pMl6}wY8T5of+yE4*(`pt)#PgmO7dW
zJG0d-i(x58{RX9V&#6D8Tt==sb~!xEQx`r5$$a&yXiQ0g`Yin}3f2EE0!op38(o7f
zR@c4`6D8`R?=i8Z>d8=$a&<f<i7M5n=)hg29=6h3tXdr#0MHtBeKa&`)sxxa>eNlA
zpm9OXuLgF#df~_DYfxvd1Zh;uTR<+V=hj30lKRU<AWiB#4ajA+!42e!dgWJ`wN`cY
z8939XE{+CRyLuNz6|bsOZ^1%`I;w+`kKJnVAlM!?pPcDc_fBA-ed_)Q==ZA&Zo&M3
z+W9$<Yibc)6T7Z{a1c{^L;Y+R6b9ANbgg1YZMcQTo9bVu!Ne_fP%BVws}ImZdPiMg
zM&mtohyc#qS2z8)M_1eaNy(1~YP%wIK2-ZvLt|X+@GoX)LjBT8SejISzZ-pz)Iqf5
zK31;^N8=Oq|F*-@l-ju#jZg7M!(7^H9@BotK@;KygN~XFRP*4Z`Ic@=I%~Z4VVo|S
zA^O;ntHve(m~I*|PJ7l_?wV0ry*xCIN`QK5o?8dbOT#XMzK^DfVrRY@VI&m&G#n}u
z^VbLtfCOkd=sH}WW-UdxgEi`BVfUD3vJ2iH*Ldv(3DNxd1Yn_>uiU_$(0Kk13lW-`
zH!-o1n%rODg*8gEtPv)nH7+GEcv7>FCLu;s<Ok4L%}R=V$7#-*p%Je+v>F--8hI4Z
zPHBRDG2TRtmM$Nh(fmX8w`Vmq6d=yfJWIdaOpOoS49L=q*aIwEW2SP79F4XFdgnB$
zWe~}=YL?O0fATaTAA;m-o@@Xq&}^i)eW51D6I_vI{&k2JYewmpP@>`d3$#*AFCS=S
z8h?r?muoJ&qOn3_rKSJ8=2wbXR%*=e!BUmxXbxPf)|hE^uhIPd0Z?i+f9!>1oknb?
z0=x?v(;f`1Ui1DB0Bz8`5{S-5&8K-F7d0OKA*Wf^{ZvWNta*(Olom~m5iYfAHc$Y)
zP2)|EcDtsLjxAR;mwp22(CqsPQ_-m@r-N0OX8#k|>DHiP7r%5(f-Ai4)m)%LsXk3U
z1ycGoE9g8op!uBAIoC8tschuBrsXln4b7a-sVHMmlV1aNNK>~Ne%{o`=!>SeG@0K+
z<F@81ML+Lown@O<)iApuIjk}JLFAsMma2wFG)u04jB5NS1bkn!N(hB9O}@X+nI%@A
zWC%`Z92(FysTrV6*b~je36Lp`%ZqUSsiyIJOr5<}umU0u+S2PFj@pvjAWquheuy}0
z>u6bX(YEaen5*_<N?^EYm(9Vz+_lebgrtYo>1Bv`YVXmVGcWDS<k%7IeJf?ly|qti
zm+GTkM5#Yt?SZeL;itVy--GklT4<FC&?fH0_>O9Sp%i$qcAhhQI;I_30)^w+t;vuK
z(Q@NqB2>FO1?nfXSu@cXroHhQM8dW2(J3H8%kYGHq?Z2%z@oG-e@`d+Xzi}K=sc<Y
zoH7eB+Ikf_W3?5uXN}Vu6#zY@-Agr|iCPC*ag($gv*A;+He@A6k)mZkfJmx#*{c{t
zn)c*;NTzFpsgCWmcG_PMIir1%&ID(*uTpF~L%ZS&aG6?>ls@~ArF~`wCLvo}_7J}1
zXy4aD@tpRR0W{`n&r`rWPdmLC*!fxsRTC9xpKgM`h1w{3O%`dRDV$QQjit{fm1qS=
z;aaJ-yb^k4+VagXSgv)WH+Y41Aw{guYx^jSQmOrN5B;~rDs5yi+^^QYydC;AS{omj
zuhs6OZzI%czl;QTLCY9|!FugE+Eq7bSGa;})J7kJ-bL+FD&f7PHC=<jChe=wL*cU4
zgAR08v<GLxZnL&!DM*X<eTwF^YD4LS+onDHJM3B8wY%sZ-&O79nLz8%uA!twr#7B~
zNnP4jN{Do8OUA+VXtz^fpjRv0jY;U!N?*rx^=m)h4Uqw@!zcKo-O&C;&-I{oAQ~oy
zw6(Ni-qfbO0PdD{25l#9YlG9Fen)$WV%B%9+Ayjl9@g?GnR`$B8%4%Ov;od=cvSlW
z2iW(uP5(e~O#3gDOFhtr1;fLK+BFW~#<lsBb(_$NtKj{l_QS8C_ei_F2i#-rJ5%7E
zXqy`#GNny_1JF;kNpvN{Ru@TyFm^iYlnX{-uR9u!RtH_oN*Hw1oucvwC*AK?;J34G
zX&PW$bUlY)*Ht%4mAr1c_AZ!r*Da#Ry@xJf6NsnoqzYs5(!EVl*dw}W7N~pcX6=MC
zJ~|GS>H6xb%ovNG?$R(M{dF-Pr=vAM_rh+lfx71@G!>+qHyesab<?RbF<6&Nt{u~j
z)9d}XF46+?A-cd5XbjbTbQ;(vbRSYtP?+wQLXdEs!hbkxiS;h!j-z!g6hesA?V-(E
zobG#i4B~aO5`mSV>s=4-lrEeHkwjfD#VC?=*WZR@vd&{2xD;Kr87Qf`#xO{x=^jzG
zBVCvGHWW_lqRY{EM)#C*NoRF`3(=UNv%ZEI%+&3&ZbfI7&V_^FX6rts8m1iGB8u^!
z)8*1k=IVO+@FGvAKLvyNx`OjiEYQvW2X+f}0p~ExBHfo7kYe4qFC<HJmnn5!s$<j5
zu`*pH-61U39nME%g)Wz3K<9NY90y9JZudtNLa5RWvd~$r`(z7dt48Pj3@p{^M(Lbh
zr#nFl_61$-OVFs-{qQZg2Hjy3U>bFHmEbPwifB`CNjFR%l4#Ny_-MSWd;VFFE4prq
zD>UmWPD7zZH%iw*TXi+xK%q_7e3N!K?K%q;8eP@BMpd&Nx}z&F7oEDIe2^~P4!WAq
zt+SzrzeiX5F$UAGE2J&efKKTJ6W4T}1F(Bt*FOO6hA!Cx$wA#t%7zZ<*6)DiP2D0&
zAKcR2y^SfktrJmh>W)r|!>o1IUEMCKj2PC1(z)TDjz!ty5uJJ)&_;D@>AAVDtBZw)
zW4d^%41AzFMoYp&U638fxb811m6^~z^Et?*&gE^OJktH-2JW$LA=OJi(e0WKlquaN
zTR8eux0AL@w))iqSg_jZFI<Cpd;P>r49!75`%@@7>YFLi>!kPi1ES9QCW>si=trnV
z)K!0-g1>J19aIPHu3za3JrDhxr_kuBfAAK}d+7tOK>dh5iuMiO`oHK7x{uz2(hk1*
z)-&+QProP)js8|WvlKD`df@_~1?szWuoR?^`XA7a>c5<i#$f$zx>R>e|32M|Jgy(0
zKU0W4eFM-!^$D~RozUA*AxW5i@k;;=*9)jDD@wn%6)4gA!{qNteINZ0<MfWS$Bx(g
zoPcD4-r6pL!%6ymT1;@V{_spFrszHGp^>G(@dqqr>kB`FNRD1YG0}7S2CA6O)mvu)
zEl+=kjyw7K&GdpT&}-?<Sg7x704dUMpbE%h{p`80RHD~?2$WL&5S1C0>Ce$ZSgz+=
zKZ2zS{R%o6o!2M+4BsmCf>g*<>8s~Jrdsbw)i^bJZwhbM>XS*KPXEPb7`&h_(LtnM
zKXVd|4f>$D&}-B;QR?TS-Z%*FFX=ZG!I>sK%NE>az00#exuUO21lO!@-9o9d7QG+_
z8m;=PQjDoh|KJ~hw(ISwDCeqvff*Vd`T)B5(y1>C0_oB_y$yri`h%2p>CwMIXU1MV
zhmH?@`jyT=>DTwT17$$J#UI=?y`UOk*Yy>Y_`jjgr9JYXKE#>6YdECeP4`G|>Tibu
z^p<`t#maB%S5uPfj{ZmhK=10^d*I=)epwB;d;0uga3lI<|AXYHUP>F$`}*}KfIX(4
zJ_7PUe~#`fKh*!21WV)k*q6Xf=)b1Yx=DTgzi{S}{?6C*{7vcqNr$IT^@(=Cwl(aa
z&;HmM7PVu7?G5(=V9CL-F&~YNhRkU&=w!G`r#xrF!><AAV)&R=Vpl^I-Mw-%G|=16
z-C&ynFb{+801SE>wr8Qw%kUy)rH&XDzX^Z64Gy$fu=*IDP+gU;p`PODeuf!d;QS5S
zSI|>oI6xWPKttaWC<YmRp+c^sh8c7t@wlOt-W(x@Ci<E}s3Dbd{U;1f;phu9yj}<o
z!wpORgh+&8trQ}WhLIs)Mj14O5^ad5-{VQE;VK2RV+?cY@D*!V6^Oya86K<!i8rVs
zp^;z+?*Q5<!?zTQNHjFiqmpEJupBVSh9#SUonk0SLSL$3o(SHj8D4w|3h9PyN}QcG
z2%Ny3G0Z81GiMFk=p#uPhN@a{nTENg`=FR*@b{l8U|G-J16ZCRpMFUBhPjU+SzuT`
z0Y?iB#!5668K%)GxEM2nz7m5IC9X;hcMkxh%&_HSxLa;WECEV|f%hsboHw-6f2F82
zq>%M0L+W+(RU4+=1Xp8_(%G`s@Jb#;>I~ynO7C1Sd?x~1Z)iM(0X7&8yn?A{G}st1
zmWzfDX2Oe0hLJtcZ!)Y?!{BAZUdoqWF{Ds<qS>%?9U5B<L-dzuH9YwXC~bxYdQ#dA
zSH45vRYN?zTRIGfieRYIAUcW09z*ZHRHD;sFeSiXpTV;UL+dxZ><#?^LsuhQyJqm*
zjlS!KtyHIe!>~vO{XxU%dq5j9xNd;@O@lQ83bzdUX%M+>h^4>F9YgDF=-oBUqp<C;
zVdxq3-7|!pMc;^F$te0p4ZmHXuh`r-ERP4;m;u>fJVu7ypTmoXh7ag(K50-Wq5sIR
zmogQP4JqA#d16@O3CSsg-z}JbYM6?^JlPr}uY=eb9YbNl-e`UkdJaY(+NC%e|Cx^I
zaxz-)!>+UOJG$}ZVhq6Vz&gv-s7r@=H)99If!vMv=z#BGtlbY8PvibrnD8<VehjoD
z#-fcN-p0G+zK?Mo#T<Q&2kH8RpRw{S`0H;xMEl|ZW6Ml%fyVbJ(;Q@c<`NW+8h@fi
zE7({{0l{NNp$3iC<HlZ!A%_?zXipewoDq$ooiI+PJ#3gUk4U(&h~A<R#x?(di!_>3
zfE{K0p&pIV#$UdJ!bxMx=dc@NY<>-3vBoJDypJ>X1wbU;*uDUL2}VUF%%3tYs{%<h
zuGoudPO=)a-T|9zoI}rhic#GI{ZwN;ZN1ZszKM`YH~tU@{nN&PG0f8$<I+38K5ML}
zM<v5JkK$dK#y=^Gk!7rzfO@uZ<4V}gF;3@$J7@G;3%y)pG?iHA8Kq^gmv3C=i@pM*
zHPRcc#l}BgfPRTFjZQkH#!nYQzsy+oEM&@!V#?@O7+3dTF3%fhnb22hEUyD-m2nG2
zPOFV(7mylb5fw?)8b72epgQ9(6qmSQbbTFMy>SN{>J7%%-iC!n<GD2$#6{yhEA1LC
z8Sm4pxyjhK5~7!lv9xo$VvOzwX*RNz7-5UCp28xn#(D!3+l)RoP-r*4vlGr-HM-C{
zt;0B&fxb@TB$bSH8E4WCyxZ75A9_8;%QK+RYdl>A5BrRM6lL!>I-j9%_keN2737+6
zX&V%;8!PBse8V`GPD6u6e|j?y84W6E+%&GG+WA|?L$r~)ZG52<<c{%X2C(lMO$Xuq
zurbUX<eu@87$_sgi|+zu)Tp8h%=e8ODf2pJ{4^VS4~%nW)64LoQEQ9Nabp>6f+vij
z^d6Zsem0IVJu=?uMBiiMBf4Vr#27+lHdDr*Xjk^s=rJ7%wx&}0``Ve@Xw|Yeb!I@p
z!SqK1I7gEmJ*iHnHMTJ5YAV&C(ap5`1BkerreB$c=g-6B>VP@%H2p@=b}v)a*Wiwr
zsy>8yZ_{7rq3B}@qY5xzQ}c45`I#IHX!JLgmSchgOxF>$n-yphQI&3x=_?8f95r3I
z2@-5NK*7~xCN(V-$4v)lDGM<rZ9`+INss#rv#cjf%Vz^S%=C#2PKBG~|5YcO-k>~Z
zq{;drEJc~_P=R2yDd!~gPny<z4=%>kKtHco)5b#R#hKD6x*2cUN9n@^Qv@Y9PMQ9f
zjlM+FZ&dJ>WSULa3zJQTWK3m>Nk#AeRIBND9~9F}FH*uL-6TAW&eJAW`e4Z!lh-5^
z&zgd1OPyhwMs*mOrri{@&oXVKQp9Xi_bN2zm`>JXFy~B9CeW8_V!VUCJk#^#@IK%4
zjz9VeOyBeatkCqV4Md7evtNh#Vv{wHYFSH64Rjx})bw35WXep>(8Zy0Q}Zeeroyy-
z7#inIk?&zJm8RR7P^dB;rJroIY3wOPYD_uF5UDj;bO5b4{i24y4W_r!Akt_`cnI#I
z>C+b>a>=yb4i=hBYnDRtvdP9uf!iyl_t#()&8C6{7<P-PE&__JrYI6^GcD}`*KXQN
z*Cel+81uk&n7T88)@kZ|4<cQrq+LMiHho%*z8;g3R<vHzk(n4$pJ}ob^V@H#y9($5
z)6_y3x@LNo!hP3GAr>pfbi*{50dEFPos@+fGQCP0&YPy2hoEuG^c&SG-8S8r3G6$j
zHXgjVYr3`qjl(8|2I}`r?^dC2#AHv=yHQgaErs_@n;n2TX1Wmv*B+Skv=lxxO;<o<
z-1L__^d?OGt0>AeY0B$>rAH>-0+@enx=tTJdt!Ql&YM%FB05t(HSMKE$krS*3>Z6e
z3Ei`@H!pnz1qbtoS3w-juYCuDPUcZsD4fk>Yv6^8c^ADDUCrMdhXptD=?@^{Zk|&N
z&cp2YCVd&n)0|FKRbJ+N+V&nX8$4mq+q_~IKz+=~RMzQheoT=hKl9UPq3Cb!rZi-T
z`E?3Lgqk<K4ofG@mu|ySm|0JEq{Gcy_oFewyix{{Nb{S&VZ2f1TFO*Lo4@ix-%0bn
zCiGcj%yz!$j5n{D4gCc3ORqxalsVfIFp1{<JrGSYfAAwnvial#%yWu4_H#IzYWAg6
zN1FK`+F7KV``-dNZBAYW&@<)=YCLPMjsRwcc?Z4QGR=4B$DL(fkpK(XW-Y~Ta;)Zl
zXRznYKholtYqk_aG|#+l3R6;O{(KOPMdlg_hFxr~)Pa<kS9^n$nziYWEHhi^E=IXI
zO$3w*^ALsi&zl!gM5fZ*N|E>~b0;MNs?7^2#ZqJbmd-e}<`=(0U!9q=rx+$Kn5*a#
zW4*aH9-R&585BTkH1GD0tXiTPrmb+ZdB$gGYccmzc}=VNJqmxcnJ?GCP`lZN!ckYv
z$^P9{ORTn9Oi#BtOb5Xp^Yc_=+G{?x2ikq+PP!}7Z{BYYwE^=Q9mqBFOI;Yrb@SE`
z*tuaoM5Q`|=09JA<dFGissg!bzC&;MTjt;Bz<=93Ducou^P3CMch|he2^NOUgHtej
z&%Di=0+|u>+P@$(YPP2@gxojpqOycBb2c4hADG9Mz?p|;76(%|X<nWKFCLk<`GY(*
zH(iFMC+5rqa8u?BJj~fsbJC~a>@4q7<*&Wv89LiLSopVL*U=J4e^n<-K^M$ATUsvq
zk5n(VmUY6AyCv=w{IonQ@==I*TAb;m?qw0sA?AqXtxRy<7Pr%|=VRGNRrS7>7bzU%
zXIXR+BlEXxrR{Bi<u1Jh0xfyvXbiGEdJIEHEt~#<g<wlY30yj6d5*$@$1NrU8bd6X
ztfc@AwaCT+dcyLk1D3)pJLw~U;g-@0a1oa4bQ+JeRM6Hc$}&#B&}hpL{mxHX4$=W7
z#xiUJ5^GsE2cU75Ev}ftc*~76SW2|W>6uNk3{hEEvL$^0j;2_`C;*gd$#S6WNSfse
z6PD5~p9!IV+R{m()-x6r{bJ5qV(18#VVNBdyP1}_J~)$QSxrgSY|9_?BgwIR`!ghq
zEpOciS7K4qT2pG-NH4uIOCSs8%PlMZgux2S%SWMJY5C~`47bYST1AET)fNq1k*=|P
z?FyM%%b&X;bHQ?~6fpG`>tE<=u!K>HtI@J-8PG0TwDhNFvTSxk-(}0tvyi-E2?_+)
zY&lL(O^d~oet@l(oHi)5S(ao#q}{SB93#7GIbH|z9Tsmh?dm%%kHoOsWpRzc2)ix(
zPa)G|dHV&(^jeO$VP^U)sT5}Hw*+1S=zwJh?f9=*DyYEsx`j=<w;Ps0`gehY7DqMA
z4_VsiVZUklbsqF?S@a9w?`_MsR26Z@QnDS5cP*hY;I<80tPeo%S(aUb#)#$K8!$g=
z8K4Tz`xYJfJ!UyVJAen4A^HHzLrbV0u1#7D?*a6Y<xe_ZKDIbeb@~%ae=i!REbsa^
z*D0(;iy-J?qoWE9SDP>nklkz~lyh{qVP6C1VN;O|5ic9{FsA8<jq(g6y=}U;0n5kc
zo0|~vwP~X|5kH$<lqK@Fv8U})fX&^-Ab~ckDHa@L)ABs@j@q=Gg-Ec?DiIWp*_2yT
z(R$qG*)Vt=ViWf<&_Zn<bYny(Y+kj1gxTz)YKm|hJ^h*^Y>M_lB+|xZ6h1}S{6??i
zXq*0P;7;27QUQZ8Hm^_+Io3v42NGw~yBZ?#Hi;@2Ot2ZF580iv(Yu2r+MHiX*CUc_
ziX!l5O}2TL5}+wIKYRrjQ*Hd_f=jb8EQk3sHvVCdJZlp{r`ZgfZ4|Q1w3(}b+gUbZ
zituLJSShG_&gM7TKIGa|(g*+YY@(lqWWLQui(tOM=9?vOrpRV3J;TK|A4g7Gji<rp
z(iU`<+Sq1cgk?5{EXY*Y1p8r3=WPU3VqIxd`XfZDY`%IKiq$q(x*%C&W27Wktxb%7
zasB@}y6(6vt1s?ID_d%&shL)0mS$$kyZ7Ex)5<a{Q!6dYZ20pPWUI)KCCU(GDIl`M
z!ImLImLMXCfXGrnmJH$dJ@L=^oO|ZI@AKT}-gC~q%&~R!!`(8w4|c%Ma=ZC-1gF9-
z{wx?P?VM*oSCyUC1-{&}ThWHbYP;LM=t_-U(qahQwp&I)uUb2&FTirgZjd6vb#}8T
zoN?E#me#iQcAoUyG}v({eRa=HNe@$_U2{L=?%NgE=)Vm#*_{i7yUliGiI8uxYpKE*
zJg__a8wRG;Zd)+yKD5iH>$}_R-lqe9?RJmo_LVNXrY2Z=WcS-u=zeVX`2+;I?fysc
z!ydcjcfrzYcanA+eRki>g<QW~{d;H}u)8o5*r45a3vF;?$nJa;1c&Vml$;u|^Lid&
z)NaZPP%~!7N(Rd_yB2ygChQh`0KtQde;i=fp27JDm;>X(GY~(-NZbuC92uUpYH(s4
zprn8^W9Stqb78EeFup6Jq!?r2#t7&J=FT`#MJ4lx8Pj)RNRKe?pMs}H8Gk<qOCF3J
z6xBb*`0EWcdNLd@U`V_eudIRzZ$=~K5PcZCsd(c!<4X$T`!WKIFzClv7!05M84)AU
z62K__76O3`n+X1%V0_pIyFrZ7UxA%uFi_TIn|6wkNqe<mM$N16B7|{f69hvUU(Sb`
zFvfx=SUSxJp_tuS#?pRx5y5yr33ekH(G+HmVic@_cr;@peNti=Ta;)##|V=_AeQkS
z9o>mznB&kG&#=#e-3yG*={uFcP%cBG?IL48MKco_Hz?4W%<!^<L<&Pq`@d91YZ`uo
zOAK2#KpJBQ<%KRYIw_8Lg;Adk*RC>J|3sgzF|K(5OJ}%KRZIqBI~Ag2F+B4yGTDr=
zlfZHqZ*Kv}Wz3_D%yq`@Td<I4WBf?ZM?PbmqSb|r`*zTMgE1orJVlJ4cOhTQm^B+p
zOBgNwFj30b+X2CwjHi?VEoZEyU#o)Qwia3{89!t}po&p?AGBMH{kK7@X8cY^Fl!hu
z>;|Z1Slj^aFy^PhLLI~ANVD->#=272t!M1ZMr$J@c{L2)XMA!9+L{=hvoJEvjGI4!
zvxPCs6TNuA_=0wtt&A6G71PE@r}F1^#(vrqb}+c9VCiH;(YB_GF{2jFJYr-}vhp!w
z`gVXG#tYNX*vt6M)(F3!FrF@iL?7dKcgXiMp8W%CfZ^m0-Ght|sK{}MQA8=drwsL%
zz=j!}KJaOTaql+>j4=euq2(FF#Si|DGk&f|4<{I7J7D4<^S}gH?3t%&8RNiQ#sQ}z
zvq%MHPRy-e(PQGwY}o?|7iI%(*Ik+K(g9XCCWCT6?#$nsVDJcYbUv`7%)NsU@L)Ez
zLEACr>r|uW$;|Wds+wc--3Y{&S+N%!eoQOvT>P2c9{>a}XMYSOLCgdy3_Qtnivs5<
z=8QyO!OZ4nU?I!^D(MVmif3Sa!kE9&RyLgJ|2tUDFsn9$<t(#>0+ta><r`>>WM1?|
zV-&NUdK=B;+h~1$j`^88c+NAuGSM2#%!)x{9CH!{%i@_#`e<HYz7Pgl0<)KLE*F`L
zet_LX=EN{)Nz5r`41F^5Q+f+hnR_O~`%BDq6w66til?9xmziJC(*Fw6M~+|TDswLV
zLzrvKmiGTD8JUrzkk4c;6oEC1nM1LlY$l&RLOIM=-UpV;<QxRcb!JcjKt6L3Wl0N|
zITXYxWZG!waf5mLZ_tXEiVg6vn7NDvmJ;UaLjX6Kd;CBvV-{})XF0Pw51@j{&Y}O5
zR>^#22ZpAa`LYB(tYI#sQwz75MFZfeW!l|={2k_y4UKio!?bU^%k*{zXkgC21aOb}
zGYwE9)8{_?z0Y*j!F&^QK7AsZnI-h(v@k#I1Fe-ghl&IqGQXwea2s>$V_I&tGoMl^
zcn6br7X~|-lXn7iF`Fq=_=xGb5aacj*+fa`Zl)In0(zLs>D%;#xr=6vK4xP&So)b&
z2jIm3v(W<GgUq#*V;W+9O2tl3neWk#WQ2Kf7Wz5LY@GzoF=oln;Iuts+OLQ1apv|r
zAWkqFR?_p&+Vc;911p<0ABR|*DS+q5T6`D4iS;x6u+FTFw8n8^)jo!tD@(E#obD|3
zBG3-A<}8AVBdm9+R{kjKwNqg6U=`5v-;4Ddo%Hf%&7TGq9~&$AXGk1p<vkCFeOYs7
zz+pdDEfwhbvuZ2hVjyeD6<{Y=ZBj@Cv1ZXl0w-A$wAMJq;@Lqin8l&ntU_2T(_t`-
z^%@;UKh4V84J@2B`&GDhhL!RYyg18hXhmZL>t%2BC6Z;EzaGRW*1U57(X6^-P!q#i
z@(twAv0j-8o>*2b%@c7fb|VDiSz{^i_X2A+oyAFDWql9YMOG+n$P-yxGhiZ__2&(M
z6xIPMJxpb7DS@&}ta%&Yb{cEdI5@Aetgl1v8cT1ZXEvSX5(tS5);NJo*2lD8&0>8^
zE@rb#j%dtf?WV$^>#Tj0cF1GpU4;33*6&nDS-`5>ig7ArRXV}o4c5|Oa2B(kY=DUp
z)>$evEoGhC2ka)RN(j|utkFMUww(3BP70z{uy(0|R<eGgw0RZlIz^jrvFvFBS<T9&
z(^0os5d*+#S=<#ce}{EPkH$LIq~D<JF6)JD7@2z3-#lOqtcD*zYh+ahgY!Pitp}iq
z6-^7aW>(@NsBU46<$&cO>#B7c-oG~1OQ+D<&g!|2&UCQ6X(`*udNLJQ7i&U+&OBmi
zC`#SU`X(P(59{nQfL@la9=e~fBB+3(k2N|ETKZW9Du@rT_EHjWh~-Y7n5V3HMNl@(
z3ZU}O5mrSQ25*!lLnz5MZH!e_fo?xz9j5@qI4hHqX%nm-s<1oA9;L_9p8Yi!f`{0_
zRF&b#E|>>roY+Dhy6w!~LSIN1b}&`#xw3bj2a6l~Fol^8vok*h%Mo_jX(&6&4yA>c
z2isBzaEu+X6D&4w_S#6GKJ2&F06osuQQq5^y_dEVe(b-@=!`$R{uOj4fF0QdODEXd
z=fcq-c4sT(PO|sE27y!TofH}kW+&2BK_To2s;3EMD`<Ifn!TUC2jT273V@$s2ho@H
zEc*aOSR!off_ESv$+k;_r6_g^Ew-cC3#uRy!~XRISkJL{y$afScJxYgCXTI7f<QdG
zdKe}yu<bSAOkhXTg6|@`kc!U}+3!)Ec@q1_{ZN*|9@&Z^NoDs_tmG2={ALKGu{oaL
zyv(-krD^&a`yGm8q_Z#PgC~RS^alEy$u?04D~laK+30L``j1eW!~W$X^eLCEr!DJs
z_6+(c=Cfa&4weG;7h-r=$X?<Dw{Nf)e+-r)_B<w3m#`Bko>t1<tpn{Q+usXv<?L-X
z`p#Fd=P5B5m24XYGppG1GT_@Sw&qiSYIZhd=4;rSXg6HT{>2sG4*R)s$knmWkAQZU
zt*nE#dbY<P1RB`0X`Z^r-ay-~`|Kstpt^}Y-vKPm?7uERpoP7Q&Y3=7``)2ay;k<J
zm2k10y|)tXcd)|+0G;go1_*Yszx)uakJxSW<~(Mr&EV{2FMR}UJ?tuqg!Qt&*#OYT
zzJZ|Rw0`zHdbtMJi|8VbLH6yHXdGharbEjx`<D@5BkUKc8e^3GXV-rh7P0H8N`IW4
z76G0Kwj*66dXV$UZ}?&CIgZg#<G}f;3)mq}Hl+`oIEw4wbmk;bywipA?+Xxc<ut{>
zZ8uJ8K9sq0)*Znh9OekC;Pz2YpA?)P9QR1jj&aKNL#HQa2Ig$rG%rr|G!VTxbLT;g
zFDL8(Fh9=F*XXD}XUT8C0yr946b5n}C;)$g^J6@)AkJY5Fr4H#roow0oWGAlJcKji
z3@<`Ces2Q{<20JUa+>oQ&CB5&`y34ZS&oTfxDlL}w!(`Uk(>}Z;TFwF^m(gc;ZBba
z(HO@WUI)&2&Ne>86F46GAaIfM!n**8oaf#GOA_ZNdMA@PcCWyf6wZb3(3r~EkccNB
zjq~jb5Wmb(CPVxR=egT3aFydj-}h^rZYCPjIr!%a4GV2c=nc8f8NC9K$H|$DLC)tq
zqeOE7=WHYl6msI|DZaruxC5Yw^L+<s#heXS(906eKM&AY$~iy>Ic{>C0)drrQYc(s
z&e{IoAtR1O4Xc%$I1>b_I1j=AZgHxzq2)H`D;w?oYB?jc7r(=q_zA3aoV<9rdzVu}
z+0=SYJ#9D|IA2Zzc8{Z`uTLW<mtt7=Iom1t)WqSv1o39hHZJV8aE?>a)&ouvg;HBN
z^RJ>y4>?_wk8k57{(`=@bE?uI*TI?PODTj-&J{i6yEv@3(b~<iUjZ+AIJZN9^>R8X
zdHsarLls$loK6a<_jAIQ!^8mR)JiBF<b1ymN{2Yvw1#}j8Kgw-Fy}8y`;KrHXTpn7
z&b3iAj&WAe!txo%PY2F%&b~kC=;;LK@Ghu1$o*&;l-hImK7^nHcj^;hhq(Lc)(2;<
zm=-WD+;vOfuPgTm6_mJfOO8OdJ2yrMaG1N7R^Ugtmok7I<-Tzfz=PZM4h$aS?xY9K
zle=^jjow@qIpf296Ioas{pNnw3qfCQ($}!$#~q?Cls|X-5r6<LpCW&OTsAFWPH_Dw
z^c=+X4*=~Xw|zE1FjpCfaSGvnN?YAf?qOP!g>kpiR_ZkO>HDCCbCc-uhBMr^LSXkS
z_W;!hL~!@!LZ>Z~d!`n|C~nbafEe!DFX6>G?%%XVI?vr%3fE$}kvdq4<MvJli06Kp
z1TQXdyXZ$t;AT-S>mpbC5RHl4C5s@Q#63xmS1R`b&5D<}?@~fNjob1)oVm<>jXpwG
zxX$!IT(xnLHO5Q9{dxzyN$1{s2OxucWjf4fax3W5kj0%o4%QrQ{vYr=m%CYk#_L=@
zWybQjNk`GqeC}uq1PZucEd(g!%J-n7H@IUfAW+2J<O`j}T*-ORO1OI+A%2q^JOJ;@
zxHgX+Xf5Y9%!gAI+&M)MtmN{!Fj&P+prYMdT$cn$RCC+@MrUfc7D}k!=5n`yrIvex
z7A|$%X=MO+x&ONl&U$V!J%J6}`&21+k8AuFppjceN2u>}C0cMcas6pi+|0dfdxF*$
zZaaPT9&ndaq_mBDo=!`&bG4H}>)>vn9abmzb-GHgi~I5$0FSsMkKpfPuIDbub#o`h
zK%j^FHN}{ExhlGA@CkP|tw{U1ztG{r0q*IW@OO~AkPiz(+;<kD@hSJ>5qgb>xlwX}
z5w4An@s4sc=0MvRm*b;vUT6#Z0c{Sv>5CzLh{vT^jU(?B3g|iU#)1Hxc`I*1rwh;9
z17=-$&(WsMjaRuEO5AyelfZI>_qG^~M|p2tM^`*}SLq1DG2XT)2zc`Tpa;*3*G#Xp
zH;+eij}Py~UjUBtcG)D5@Z}w(Jd+>qAth7-c`ZJ`PVnx%h)x9YW=diHByXl8z$xB&
z20$?H$C+?Dgx5k};80#mG)#o?R5Y=i=Iv!*V8VIDgWx>NJ473t2;NK_ADb4*dqmmD
zDBgQt!9p}I?gGtEF}!yv&~=U%*9~XR^L9LgL@Y1yYk)Z3bF}D;=Xs-2Z(0Ix4eeJh
z@~S2vpUB%tAEqRpQvmEH^LnWwBZapoA1tZ7@1BGCOT04r=K^UwmuRTI%!~RQELV8F
zw2{2V+peOob2`s64wf=_t<3<Lyxp{t&EjpMg+n$^`vrcH9G;;XCUSXOJpiurKHCku
zdAxNc@F|~H$b{}2JPECwi+B&3AW+P^HyNBIyg3iSQp!8ZfWe!*kA8tOWxS<-fTf%l
ziOM3|v<hCue#lqyexxsW6>sxnuvYW7JEDg*JlQ(XZu8!agYH_M;%Bhj;r+A+O6zz_
zPlEF<?+Ys8uIJfkE7ibbk+OTd37WYZd54n0(!_JG2WaM9qpM(Acn|1!-UFWCJmhSx
zykz?1KjalWMr#`{Gys;`d0V~&YX|RNR6$JZ<ZYe=mM-4${a|^_b6x?KZeGu4u++m_
zN>_mN^1O=S+7sUU_5gjn^_wBk&-?chd>Y^tHGy-G*ZUR3hj<H|A@Gzp{29!T+IVl$
zzGIB{GevBl@!Xe#XPh^=2|N=#E#0ngkl(%q2JQJ%x<PZ`Z=%~`5Ak>HhrA=d>^Q`o
z_(AJ2q%Qp96x?^^>uCq+#{ZJuLU+F8AUF^6KYSm~9O2K%f%sAWM?0X?gKwL@79Bmt
zXN7_2$&aIZioEy*6hrahE9vafasE^@O!)Fslkq_K@hb|@=+9sIBm52EFQL;Sf&4jS
z@C5(W^N<VTyEH-PN&X;R;&Y1sI2dCQ!dHdCi%|X)Dv$`{v-rSH^ZjiJK*RanRWNae
zuZxC>vwR0i??muZX|{{x|CEkCMe+Aj@I0EooW4!x`O_(09m`+)GC1S-ng5`p@%+Gt
z@ZthrNF~4t{AMapzsR?*g<K*(n8II4{7++mCG&G=ah<~dwUnYmm-uUG|B%KnF95jA
z@1Qy13cpnV`K$Z`^x3?|w-v%}I^SOaS_Z#}0)m<R_ZPvnEPg5*j%M?Z(S9YDzcK*W
zb-s#9+Vl8-{tl4O-*5(o3i$5yeJ|wSrc;<V_;&-S-n@wa)pt-+%y;_%tR?)yH_@k3
zz9b*!%lL>o<6Yq=Qy#y9Uq*?9N`5Ql4668(Xp4S}FA@V(^S4vgdksI%5xQ^l7oG%G
z%NNzbnLGT0G6>Z3a|hsI1D{9h%X|DAh$q^nHSzmtkKN2a^&WcP!vBuOvWxHT34@RL
z-_p+LF~1`XcDwnx_W^qN4~zi4{Ct`rp71N9VWN-UOEqr&{MTjZ;Q+tf0i77+57I@6
zL;SUK!19#;EA?!czi>S`NBD)mLfkgWH_#V$jPEcBcAxS6C^I<D@22-}f`4xj8V?E>
zKS9D?5V#wh4g&W)bnTGf?>%UA6nr`d{dE!qtI#KBK`TWFTm*J>TF+H*l1et+1VVbo
z-33=D0d`oxUy2buB5-;GoJVbfwO&x;A(%{gjAH^hO>mxqnthP)5@^n%(OZz>1I$N|
zX9exJ;5gOv`3fe#37Vh4%ZkDG7sSRuOMt+IvaErE0Qwf65NxHNIY_XR;*%!@2jZdS
zl)#?muwa4lCVC$tutm{FJX8?f1J*D>LmpaB3x2GI(s04arBHfCV52iOX9ed^Kt4h+
z{RePH3aSUd5+(3hfFX$%Ecgf@MsSpZ-{%CYDNuJ_P~?sN#tO=6F*0$2LkHn@yg=|N
zI4=nH(Ib!`_{H`i3|<u6Wq~zO@ZbxWND_FTfKSPSX37$z2<{bvmMUnbRmvs7Dmu5H
zCJ<kOYnKJ5zlXpTLE<hnrVDbZ!Zt&&(H?S{f>Y1nOqQUMiUqO--(CPqjv$9>iE;%W
zMnU|#;JeKKVod_eCvYlXP}U080>R#HSSl2JNOSKE!CO=cP$c+}mfOXG&GR8&BB-i^
z-BQ7VT@bh_D5GU-nLtG)-sOVB^!`-{e&M09QZR8As;dN>D4B9gu>2c%Q7xD^0WCFx
zjcs(I{I+1^99nAyJ0y^}Bk-$-nmR!NC3)`(z8r+zdckrllr{*uQ=#UbAZH!q8wEey
zh8On*8=7FENpRp-V9f$&3Z}IP;x9trfgp_@k5+-V5VVJa6_nU-6S!@ImUi@oqC*{m
zb9v}!r=Y(D2D=2)XjA@3V5Uog9t)Px+t@8|rCd^vpgj#Ny@Cc>Q9ltR_XFz_xKir4
zU+~*?unY*+)WGhbV9Ouya7YkFN6DWGUZyz1u;2)Fa76GiEuKdOe@#cPZDWGsc<?+E
zxJ1K?altpAz{Lqc@*7ZkP^b%oguO887+4&HYnFiJkg$nPv^WYmblHNFu#fir&caW3
zg2hFsrYm4wg==O3a}&NF0nA;v-T>^dutW)PM0ka27LE!<N8qTZO}K{E3tqysF|>LM
zed*YUk8rpgmW~U5d<_!5!eSBB_z4}3g2i8Wi|$Yh5PJPr+#w96o61fIhpFfwNSHy3
zypzH`RA_rjxR>7hU||*&RE7w7L2x@%=qrWJFrn#f^!~KacH=&X;lehGsh<(PO>v5|
zLd^%@i4ZRM8X!`b`yw8JD4`owfJF;Kw}CT8*g_Gjb3(NSwDZDwR0a|&{E#w+al*w{
zfyE1#86kc_$Q}e|f^gvssJ<v%N2|g_Ve@aml7#j)+VLj~XS;zXMYxBmN>hc+<kKbL
zW18O6gbj2^;j(bj3!q&QezOTCt_qJ(p#7SVp$1F3aC<kf4B^)_>tzc+ISqjv;mID1
zMXvBm6-MT|FqBF!^Mt`aLUq1SL34J2(Cq+y{|bfm*C2mGIN}DuBB8Vzg2h4&Wl&0l
z(LrD>6`sD0A-ySd)uXXY*h4wsa$(2o5U&#U(g*04Fo^O$)xvJN5}`);DHZ127DiHJ
zy;f*m1=V+i|I+THPFRr-Eq8@$rIa117e>s5?grtPv`D-soP@t=jl!cFz;j>tW)QF@
zA<mBD<q~?XfzlS?2NXbhAY4Nad8^Q^7vQ1rJF0?h6LMCA)-F_2VPc2y^%=0+DV$ad
z&?W5FLHv>M-6?SNv9K1`J>k5Sa4sc|dW08v5bPCJCxG}wxPpFzK4B^ag8GFUC=os&
zJVTc&4hmnSFxHST!45t>6^3wu4GY)upk+k3_#uAZQQ<NQ7mf*Qk3#1&VRt45VO*HD
z0W1^3?H+LLplJO*sJ7XQUTy`egXsGO7`8*AkJ};PC`zNRp_Aw+Jtoc~ubH5^h;oO~
z=qmc>I~a5mc~i>7U6ip8UK|#A&{TLt^l|~jkBSPtF`^!#d|DnI6U9;?lBdW(g~48;
zj%%QKi^4*|>0=WG%AxJJ=;~DX<}1ox0ivI17DXQXMF;4M7a-b6Y63+uHL!F-)Uz9$
zL85;s33gJ%`~hB^5+!znC0H~{r({Az&2Pa{sHl$a_X!i7rKQAa(F;`27A|tw3h@Zh
z6PgSnMK-5YSc(!U=mm%ty&DRpF(QE-8qbM>M&ZnP(dLUV5i9zM>Sp6aKV^U=UNrR@
z8ZU_2jldE_rgxz9qNrI1Es3H)+K?oP!aSfQSyWXFEJc)c8d$362S?bwB>J8<wrL`T
z?KwzX7Tx|FYOaVjP@3+lD2NK>uZbEX(U>lBdkw4^A`S;wrpTTml3Aj^oY2v1QMVsJ
zj_B<_p*vT!I}pmQi-PyVwLDSxzZjByQQ$_<3PgJ;cvL8Q@he!kA-eVklog3etLgh!
zEOJT(S|WO-8@fwH4{4lliuTfdJ7uC2S`(LxcG|)33eokG=uD+3i~iSDm1xmoSh^+p
zjuz9mMO?}`){5*S0q%%Sxk0W@G^G?4?urgj5n8>-IT6k@i1e9YxhEQGrS)f{$ovUd
z?~Be}ffr4pZ#5t`i;jE&r7fa<I{*4WRCE?TwTkZ20hfoON-jW~C~y>@U8FTZX@}_P
z7_d%}`WlpViJqQ;mPev*>9(N9qRI4e=@yk&fYu|rKr5(T(d{?spAS9}RnuCcPn4B`
zuJwyvqS(lQs3RBJ21V0n!2FOX?HibQDvGMZAP$R`_(NbsBwPyGsA%qYurwwTQ>5gX
zXy^vy#znKXL)nCAXbO}a6hEQTbbGNgC5#-zT-t&h68ANMW^)wJ-3V<?;siR(?ks+l
zvWza`C+|SQRlIl|?7E4={{f4;c+V6J&|&dT`p6s+f4Usnj*9K6(!fK^RYUHW_-;KK
zJ;lKd@WM-ckpWI`@mpyCKH_)w!|rjh2bKT$iaRLG<YyBn?1CkK@n*_N1&G(~gqlF{
zqqm^+ggB0-yC88j1!_);$I7ARlz2fWXu;wFD$)uO_tVlkR2&=$55vTL4}qN)U#IMG
zxcFzPEk7e(@h=3<iZ5@0`3SKi1@<Gw2RzZ27_m=Y|Esnm_u+J`cs~W1;>4X)sS+<<
z{sF)R@wFLHl_1Wf*ZiXRI2RyM91;%UB=K4*`bidlKLsE~{GvS^N)>Y`#BfQ>-VWPo
zV&itGzAUc#7h0}}o9TzYD(<3VtJlO1>9CM4&a(vrW{A5fdXg!g+5i(-Vl#!Pv&Aj6
zWXTbW--L-=aoScWy)NEH1Cb}bMmyPj@h+OO3dFaWU?~*4Q}MzL@f|&!DH2yNfx%+&
zDGs_`A{O6-g;KGR)=f9Xk|Xe`Og#J^CEm-$_vs{jh4|H(0F~k^XJDyHET`hCTVj{3
zV5t@_q)%{-xP+dK+hT4TIBUf_=+l2!yjzLJda>zuC~XkWnhorp*c1WR8pXfPMdN+(
z_k(b)NgOZ;XPU)zH{fB5_=msgn8yS0Ob!gTil>po55-$)A>Jn5a~Phsi(jmRnhx;{
zx&*URtf&X*5?`nClSksJ`_T4Sd?W!Ty2Wo%`B#s);uHAWD_-#oCZ32r=!4uRj{6Aa
z`^C*>U<2YiwD1@d-$UdTw;GAnDX{xg{0;3DhQ*~`AdZNC{2h&>;+dUj922X`;NdfI
z3e{|ki(egr-3jp~Zx}o%$?X8JmrS8Wpo6597OjUQYnH)nM~Oe3m~oQ)k0LV8k}%p$
zxJc6I>)|RnN(IF>H%aUqNVrRiDQSFIQh68>9+FDRP#%*!*b6T_B?>wp>?N5@)v(@@
zDKEeoA4xw29F9wl)Aa?ulKrzF=O?NA5xV^)tN(@W07)D@q=Aw(Rj_bEvXc54Bx(K=
z*h$G+T49~CNe*vAe?ujybhIH%Qbt>((~@S&J%mfXcols*Bgv)+#aYQKp->tj`NbY4
zA|;<uO>dOspKxf4M&uPBMzWTw`p-$~DEWF`;z=M@GU5wboMa*0?GZ0&qg2ZU$s8_J
zCrE5FUV|GKCC}4KpD5Wg1}sU!r)Mr%qOrl56iIyqx|S+2P=x%F#4#7z(j<qdLg%t1
zk&cC3k*Mh)*;Pp^O|{n~@hq4~m)xd*?wKL+^9IP2xcv;4EXf!2SY=B-J`K4X$!Z(T
zGP#mH&(QnplE-6kF;5af@u+-BN-wYi$xD-AzECprZz#PX3FbneNW!OGRIy|eRrQxh
znkzsnm3%iB{@#>4dIl5a5+nVGg$l{e=Kv}tG8t%9lFp5gyCs=37cAA1qgq;n)<{<G
zho#$+&D7CaNhAem?nv?uV}R=<TPXK+SCUNO&U(op-SyQVaeW?M+><<_C!tZYma@dn
z62)?ew@6aYgY$u8>OwTOO4d0+{Gp^Y06N<w?Zpsim#n2pq(dTDNqfLf$p?P$txNLF
zI&}Myq+uy|9!t6ez`7+H=nQU;WYrRA>y`91Ld_G2Cq0OLk{@4yntsV{4jKm}N0vcu
zQ1W6l1coFvRyg`p^5q!7uq0+VXd@EM+i-hS(q)0NF-gMV=kfkMllYau(zqlu0Pasn
zgpN>pP<nC{z+P&geUF1Qn8MkIq^%PWbd;W^MUj(~|0a|=OIId=<|19T6uModPAy<@
zlYT{cPIu|T|L!rBuKgSqjz~9A=;)|aQ34hZX;(bNZO5cFcc9Hvx^w{~yreD^*7BDA
zeI7mZk^XxI;J9>2CV;Qhf%XA@()Cx-Uw>&`1iBU=E%_bh1Es6Rq3wj!OjApc)RD3y
zC#AeIpq-Lt(=n-FX%rO+hDhg8o-|atfTsK~n{)|9^G-|0s=yj9okhjSXQVN759(Rz
zpLFsiLh7Ufh?IKL)qYXZ;Y|>Tmd4PhG)B6V1MkmC&(K!=yi{-kN@Jx9hR}&P={w25
z;-&AL2Dl*o?jlqtNRuwZ&_(I$7>FlIZT|E+CP|Oc3!f~_m;x+Cdii5?G*!AS6X23`
zVLNDP(if>L@UqnN9xPpvcJScERp|iL8()(OHi9!<nnHIyW=M}(A&@Ek&Jmnh($#;%
z`)p|uJ*(HHx?^xAPkL8@#(e3IHVW4iNPF~<D3reC58@4}tpda%>7_%U6-x{1Kr4|J
zp8~B^I+h1ZH>FMV#*|6ZY4cVteSwZ3R7f|K15`?1CNHX_OYQ>PlD?e{fokdbKA5kO
z?u&=OZE0{f+^&`OSZId1Bi%F%Vx9DxHITn64W><cz4X~8&>EylS~TC2F3*8rqqK>#
zIrpU_v!Jv|x@H4Fvvkf{aJEPbd*I;%>Bk`$;8v;i1L%Ax4g3gRv`JgX!O||BavUrj
z(wA;QXQ$LVhAMQrq<{YR;z?(_f#<PQKy@hH(km1W>yf@r6}Y|9bMz!Vk$O_(x=*^A
zKJ@+4mZ{J-ApPunV1v^2pTppgR83p5r_#+-&oL~0X#)O^NEbeVvQg;=8^Adx{m}zH
zJ(Id&7QmT*>Bu}Nosj19A$U-xpv;fG%tCul2U+7I_;g5i=OP*%Wu5lGoMe6Lq1##Z
z`isC^WZb_o2(Gd)sz`N{S?Pu<ciEvbG#-|zXnk@-c4{`nkIEcqi{T;bxCfSFva!$6
zX!De@euP~wS@B-D?=4$G+b18{qH(YumpLy4%}+M}7JBb5du=BC4v^iUmn%@#z7D!i
z$nIVR2$IQ{qw%Dyf{Lt8$%5&iNw7@v9vVYr;Zz$FDvOB%7A9N07~r(*=2EbP+hlXe
z?=v!&)i7~ZcKJovjga+GfnKC+1Fc%4WKmSK6fN_UpxZIB-nT(JC)+~1k@K>(*<gv4
zP0a%qCu?~EmUx+d9<*GL*`0)I39`3n_PHn<YXmJ(wwVdLNwRDEU@uu_yZt@T6xp?_
zAg0RrG|OL-9sLEwG}#@>*<Y41C`NrnHij!wrd^edk%?=vTeSO1mw8Y?H$%436IiCq
zjXIhoE1*iKY+2fEfE-!bG$_lJt)eylb=gQf{LPc`C?=mTyI`Xkxj^>zKj66`yV(sB
zMY3jlG#1M&l&3C{&8mh(sch5;iJP*d%P?3bOKif=R4)67Y7Hu6Id222l-aF>i7MIs
z577HtvQ_8cXtm6a9=#gbVK!*DWyT3;sg?1l;_{BnvWP0=>SVgVAaPfAF$k9GWdRxp
zHpsG<pxgIke^MN+Q6{5V@4jsPG-zv*jZ>trS$3Cpur0C>O6@+7{YpEPR@q}p$Ul@x
zpFvrhOi=@6?Xpc&0o5TpOeIX6vUARGrb~9~CLQyCBy0Ty=wn#~{jlA#ch|v0k1U7I
zfA`9US79uk$o%M8?~@hg!>4}PnoSTGkWHfS-=J*o8Q2|?wT^@HsqFTLpbg88m!fe*
zwu2V$qq1*k@h~R)ek;6qCR;%(uyI*hCRM0T$X>bwrw+<P7Qs_{`Hyrw!%@EPziMdt
zL?8@0%MHH(xX5?O0bJ$29{{+?PtxAeUH<(A_<LBsH3{H|JTVY%AC-?vfO*J&qEOi}
zdD~+c^prc$9>7cfHr+<$Eq6E!%;qE4(6a8he9uep)K@<34>;o|5Ag$!zkC;+@eYu$
zqLYw;@-1axIU#2+g!v%(>LP%X@+?{fpOSyP6|`VEpO!!&a+hAvLgiCR0m9@nV*yUf
zbM`@5xO|Y_)HCv#&jXyb$)nofX@vYun(iXyZ>@lQl>F)U_+g{v8$|#y^5}N}&dK}e
zcxIe@^c|>)m**~nzy-PT9W*A$b4ck$`5&|~NR)r}3@k}<dj;H1mPh>w@f7*@aR90E
z2lS9#lIz3aQ<~fs{wCxv%e{9)@QQr%T7awa4`^hs$*06XO}c#2Gc;z%J6+JjOu5?v
zG-k=;={3xjucPwb9C>6cSaRjRCt}pD%kyI}>Ur|%v>VKqzfT#m0=b<7utNF5&5*kx
zpLYuaMe=YPz2e34LwfL($X}tSrBuFvw$3-@FF8O>nLO+d(8}evXuVw_KNt@8E9Lf)
zXsnWR?4b0P{9Vf3SIcL83|ftxOEH++^11YJs+DsKFfw=K&XgLflb1Ha?p^tsdtj-T
z3u3;7i3WMdF=)FdZ*qY|qkQ99u-=#dd>K4Vawjtyo8`&R!+eYUZz|<`An)@BtxbM4
z6`bwz9217CL*7UO+$nFQ5MP&Ew+rBryx4!<bCch-ohgG{pL`!3Z|av1rGYje-|`67
z2jv+Q!5xwZQHj}8dG$ZgIV|7y8dyf;UOfP#@<v)`kI4%?q2-x;-x#!v%h&qC?1cO%
zRUjTzJXZ!5d&OTfFoX^YBMtK*#h0&PU>p_yvr#6*Ns&$)A!h}v5}1qPK_zs%D$f1|
z2{*+HFF@X1@svs}4=a4AuH}frn~h!{RV3X4=Ar2Dh1@a43|cw`D3t!N8>o2r9KZ>M
zWhXd;6av~Wo>XLPgKMW0A5vB(SkdqaWeY<TMKrO6D!$ncEKKnlrD{(rn!I2>T+t^5
zc19s>hQwI~n-*{piU>Lf5UKFHfL=r?MutF(R^(ElQ;Z_62F{#QETvEKdBwTi5QtTj
zQCK!kv1t}Oj8{C_2yj7h<!?I8ouG){0ra9mL?u;;ic(rUBq?fk0ZUd4Pz76x;sCAv
zQx&!Q0WK-F(*dJ2#g$d)%w<KBD@<Hb40*!DRmA~%;jSsZ{|4sM6$T2%Whk1DqA^o(
zfhOrJ#Q?3fauo}4ZoxL~y5iaiwB{*(q1AJ~qUIMUEl}_&ty!ozZ~(L$3Y!vYiWJ`8
zf>x~f#0sob@jnJwZYowkgj|{8Wl9*8E8+_QDimSKFj1*EME8VMDYguwFSit-l=`n$
zY@mv)8pRR@`r@B7eez6O?KwQkb&8Y}^!2Wy_)iGkQ*{3VD~*b+YJeuitZWE1D^}1~
zxkV8?0G0=eA1M9as<7JtCm$-VT!EH0MGQrv+ZA3GDC<zvQ>9C%;>TF{)1}x+y?UhZ
zIR%!-ig2oF=~k54>Y%ho@wovG^(r)-;CZ6BMY+&E#qSG&^(!XmK+S;SP7c7JV#5W1
zAw}6F7<{Tor47!o;v7YlMih!x2#hM8yAGXWiY|(8JX1uhfa-C@3QE*ZC<Z7HXRrMG
zB4`fEgJHBLI;1pHSkGBG76zh=vW;$lbXD$mffsJdu>r8UE63;`V;xrRT@B!&lomta
zn9_A7SUi<8e*lY*axql~99Lc{1dFfo3kfhkWjg(C{>t`ha0V!s&BKTWDl<QTg%ir>
z{zvtILCUjK9dc5+g987jl*X4JAFS-6=v#=AK>@E&rNReTm~z?<s5z}XI|R;f<%tjB
z?-}Jjx-#;tvbhvJj8Jmu7+|C_mcGhS$~UA?7OgD$9kdwb$CST5r(Ez~K3KVa4_zq`
ztNfbkX5y6nQSdEZ+4mNlxuE=n9`FR^YAqTsD%IUEk*NHAJFq0>Ci)U3D`lO~ouYg`
z0!mYr+bOVoN%=BGjM9`c0|w}_vYbNhSCpl7(0NsP;|1u<Q2J0nF;n>$Ef#HAO8-SL
zpRJs{2_Q$=w;H;0mFE(GT~~f_1xoXjbI+jL`O5k`00qjLOt2Ix?P)D_LzzTtiy~#P
z0iamfPPa3ZC|{-kZ>iFkj>X+nMpKl!OzF8C&Xg+)Rq&!h`PYw7U1?Lkl>wzy${Vy|
zzok5O8iLiz!y&+Gm1~v(yQ5T60au-}h}JZBmD{Kare1lO=C}ssU#q}!PZ?DK6OGEk
zso=b?tayqZwkSWG0uLW3o9XCqt8({IuyiYp??H8s@_7n@^eSyhQz7549HHXX0p$xc
z!w)K3=n&12Qg{cJo+|Iqr*Bxf=yhOY$~p>cJX1cN2{5kYe+&V8RlE(|c2MQag_c7q
z1;yJORe=KlPO7UvK$){@5zXwLD&f1(;-z{&6R(lCD$KSV=6zJIbgt;Qsw^Frd{xq4
zLG)AQ2f&2Cs&5_y15`U`WCK-uUk2w1)vOTEf>bfIojs|VMUj+Ks-i|T2CF7$C_`1h
z)58{~k{9APIIY@FL5pzJZ&a9YMitr$?5wKePaDifsr-E*7_CZA2Qfx9_TTnhC2fPJ
z=T&+ds92Ts4Oog(F$>VAc-2G^<S(cWra&M;bw>*Ei>jSrpe3p*Uk8??`eh|pl2wMi
zU`bI~sUj~`^<EQvx}<WYJL|5fz7bQtBVBdn7SIgUYhM9msy?3t`7Bk&U%;|e`yN7R
zj%wxa7=&Ean>q~eb=8?wP@1Q5eG1NeRS(6F3skXQaI{dhh7$cZRE>KfSEMSUrDL(G
zmCpT^s2I**DOL4ufa;s7E|k)JFs)3LXaZWUa=!&)g=!^T0d`BZAsnDy<w2|J2GuVA
zEiX@=v#5efpPE$c7IdveW!nnf4^(IGVq{uX4*p(Xu`Q!TZii~T3!I&*ubja0NcHLu
zu<%%w>JFc}RbSC6zDHF<!_}*LDH#@?sGg(5b)PDr1djHrX3!pFKoxro*q~~VjvEiD
zf`3EjhgCP}r5aJaNZ)}`Rl+}@jj1G5ZTC#|n~jA|jH_n-54tB*oA(18R2Na?)n1*G
z1)76;n*s8N)Y`ux=&1gKZuoRkKWK*+&T3gFl)9)#_riNu^}>HZb5oB8fzw^R_ay)i
zb;}xf;i+CvAAT>j<wbPRTivn?G#|Cp!G_l3>Wvge_El>$z#5>=qq~X%)!zk!c0$eP
zKzERO@-om)s;8wx@RWLs7$8_3Pch37wR<go&`|YCx<2i+`df;JgsT<ZU^$~!orJQp
zYSkAIk5I39ALb*~J<s5FlzQ`Sirq)64@N>wjM`}*)SOc@mO$dX`qmVviB+F70mQ5G
zXfn8<UPS|(pnh{b)Lc|Ac7xJHbpUO1lGQ&nLTQS6HAQSw)dniqzofo%87yh)OXnbW
zS^e%qU{}=1Wbc~V8EGNgv~=}1^%%Acb*==hnd;azP?Mz=FwpyK^;BAM=cwlkV4^_H
z{SaeOs5a(<c0>IM<uHrXD=1n~tnQx*TB&+Hg%WP64>W^TrcS&KTBX`b_qA22f27)<
zTk4k{fmW^l;}>+vR-=B955ZdXic;9Uqjsaiz;)`67*Nxo-u@0~_tZ&dbf!^#Y7!*w
ztBWWI*QDlWL!eo`VG#sc)ZBgGY*kkWg7cxepQ_B;)V(#JwX6A!@S;OqM2qoGb?Y^N
zE_M7MI`PP+7X1oKkJX8kVd_=yxDBOG)H7)3*{5EkgqnW!rj5`&pg!{ev_W+`ZC;+L
zBPnY&tezu<?h&=^eXxwG|0hM`n0oYE=$=qdxem^Qnx%^X>@~vI(deLAE{6AqG-jHX
z9W}N<Uzm5+ESv)#7tNy}09Q?GH(1>?S11(Wu6Y&()}xwv6x;RC#H7H)F-@Wb9(ro>
zu7br&GkpVqx90aYi2G<}uLO2n^K&&={51pT(HNjPP7#nm&29SaPiXvTTNb1lw#`QC
zDa~3hNCa!nW&wm~S}6h=rWu`y{+`y<P@Q(T<^UbQJ)@C*4fAI;4K+{`p?UE=(4sVd
z&<UVuO~-RE7^692hsJZ7-+jSyUK6kma<Q7J4`DD~GfrQ#3!2^A(3qfkX&2?rE@}i+
zk(a1R&jpsExwajno~rr73N@EBcFQopX_{rka#<7e5#+CE)|1_<nmwWL@S0{z3P8H%
zH>&-~&>ZRnEmIRQ3}>=55{fWqYd)uiMUJM0YQS?fGm>EFx@PTKiXG-@UR@6p`I;Xn
zNLr|I&4=GNG>!C&7HPJwf~UnA58D5hXeN$=rBq{_3i+Fww~s(~ndawpz{)kJ$DpM`
zvoRj#D>bncT&>cGw?W{Rrht~()tX|e^s3S9{Rh}>jSIFb{tISL#^kvI8tODFg|K{A
zWB44PUh`!We7&bRFb?KMjWQP<zpu$(09upAj`AYSniBf-v}jgVqT>%VH@*O^RWm}t
zfQOp=wGeO9y!jNW+ckky0@a}jpo~JN=HpNZbZLs)(Wyt8uWco0eXNnr2I$u8qG&*m
zrgIb2JkeZlfnc8|=zmbtuX&;aZAkMPrI?;-zAXS4);x*>7}1o|M{ZOTK{NB1X8dco
z{Y>Lbfyr^rIK`MJG{4g{a!@PZ3Yxt($O7{Y+6Sj;F>*+InY?h+G7o{(N&DGLXmr-5
zQe}gSHY*n9UA3-9L37hqZGrplTEid);js2OTHGGd{%iquR2!HMIS=h&N@O3?ZlTSP
zr*_k7^u<dXLJ@Lr?YFev@X@|X!MNkvs%R=A^3~?G0rk^1)IgiR_AUC^1GHBYpe<1Q
z^I2dgw9e&_57I8XfsUTkhHBu&DQ)Z&=nmEzXuB7p{qYe5LbYr90m8L^2;u!1En@{#
zpVbD_smKWJOp5YEYJEO{mMAU%3I&j(wW%M$(-^J8i!gsq`yRzPW3?+z0E^R3L<7WY
zn<z$|sJ%?_?<DQlJK#*R)=1m&6m7)-yhzo4zYGR1X(Nk4OVbw7KK`=y4|>V2X!}!P
z@T%6G9*=9<e)_DXYnOioM{OBe-Jc+4YTq~oVwP5W4N9}MA+#mQ(F%SCYp%Bc6M*a5
zZ}MOwPuouGq<n44B*+(N(~IF@p?1<yfE(Js9)q(;8%0lGv37R~be3p8xCwz$ZD2fH
zyQxiI3R;<Vr4gf6Zqr7NLZU+Z#g{-UwZ1fZRocZ>@cWkb8(N4~YmeIl)M%&D=Ki*J
zOBF2DYM(No?T+@llfde<9lIcRR~v0cx9hbwdYl`ycw_MzX?p|VMWc2b1GM|vUOFY%
zq}@Z6#LZgUR4O%X(N@v9rw7`?>ELPAo|pl_hgvg**xR(frU7f$9;2Gr4(&FI5_M`d
z?}4*RyNp&LkF-DeqEC;tkLdf*t=;!F4EAW99|P;vE-3}}MB72Dmp*M|76kgWb`Rk1
zfVRo@I^dwT^#OV~q`g5~#u4p_TwtTxaat6NY0GJs_DuV_KTM2k`%w8ZZ9=PB0Hp_Y
zzOHDr*R5!RQU_hle0X?BH<`Y*jymZXU`{&kUWhyEUf%|{U33BmaJuT+N73k}d-oD8
zSlo4Wlx94v>$wGqBf3{*(0x?*5j`y)y5#MUIHsHRC0IOl(lU7Hr3<8hx3_L1&DuV?
zulK;<aoxvf&_iF{V#?P0=>|N(>95;$5EcS-u2a#aK;1Gb**c;7AKhSeO817EA}gUf
zKQ>y!bloq&;Ax#c7P`ZAV>FqZ(UpD)pU&#Gy8%S#=F{XCsoS(1Sd^}^9VVi6Wt1?E
z(Ve7|CFgW2rSSK>u8v;cSY6|J(BgEjPlu!Ny2D2xenA&Q7lb6}^rMsT{$12n+JPrg
zw<rrPCh1-lLOxk1qTpwWZg2(~Q*|G>!nI4fMGQ2i>1N)6-OIXJThVw$XW>BLs!m!5
zpRVbiP-Z+`r=XC2hHg_a8Z&haI+~HC^PG*wY+WbSgy-lU6@X^T)n)V0dR_M-MVIq*
ztcCD9U-#uwI9#CnoX*}B>Oww*{0&`0Cmb!(xl)~NvF=qlSW0wf10hhVTR{7po4SvL
z0A)Hi3tTJLy-gLL6*~7nAW*4`ql{0L?$CT_xuxr(m!sOIn?rHz8eJm~g12>FOa-x4
zw;&kucXT<Q!P7cj)3=~C>Yh!&Qj>0LGL$y!7>=N|=&sUx^gx$Fo2^z|*<_e_s9QuE
z-Zq_5hMu+S0!KjW&>a<mvqu*f2Q5!@QS{*V>1-<~)ZMT9JP|xYx|iM2r>8o*#qe!d
z*GOxN5uH7mAJwHF1k0FieK)XYx*|W&#&t29048)#Xm5K^|1AxPy?&_zn1eo)A`yr5
z*|dsq)QcXVOHTUBN$|p1|3d|Ui++pkUnq6eub2jh-Sp#sfyZ6{_DXc^uzm`qkB{ij
zP<hT#eLE!<JoG;gLEAC?`RAeAQ~$0V8ol(AdH`?z<!>SGqrXEb-sAeOZ=%sx{~T?F
z{Pcglfd2aH2SpGM(1(8t3xRq;vkmZs{y23lNI&ZfICWCLGZqF<=|32UM6f>U7A%G6
zU3wuHs=sW4(lEW?Pk_^U$DL>l*Ps4xzo9>`0(Ms47mX2((0^Y9@kss9R5V8E=L(=Y
zT0fnN!DICPTL8}K8FT6VJFg%A6%NPhCl<q*IDIR<+wuB@b@1te{>gF3C+H(SLE}aJ
zPqg++)JJ8)e3Jf2ENIDk;YXmQ=vQ9?EmiN`1G!83OGbE+rr&=B*k!%xTMWV#{h{qJ
zl&=3(1dySh_QzDbf0_EzY^cf7U!ltDZ2kXS(EA*{g34cW^*_@V`MQ47cCh5>zjZ(_
z^7Zr1fu%tI+&nZE>iY-5azlTDj(rsABlPH6vHl{}*O%zIRKH!SZ>3n;O?~k~h?nUX
z(-c~+kEPo@Y!&*sd*EB8KH&t=D*e^BAaP6oLmNP~zTqm=)abWX0o>OAtb@T?z1|hH
zJNk!#P*bP>hfZPK)jQt@OT9jQ8)yysS`)_Np8iZ0SQ_<TslakyzquB)CjA$b&}i0A
zN`<`^oBl)kbUf5gUkBgX^d}dAr(M5tCWsySV-yMQ)F;dYOPBsdN;*E$YpKfZvEJVV
zmTvvr9E?Se{*w}5z4}f%7WzcLX+1dm^c&|wXTM%Y!RZ0L%io|4>hC_p01fGPMnKC`
zy{&c{Scmo5<mrh1Dn*w^^|chK8q*(*gVJYu|0Z}bu2<0pXF|V-mcs`Pi=IJ^y<tHp
z8XXL47J}uF;j<HHbTsUK8Oodt1(;%{IUBD34_>$!ZXHCUtKt0w05?PGcQE8`aJEqv
z;IP4$g0n{qA38wIQNw%+NO~CZmIFIx80dsSPeYRvEO{AzrT~Gr;VKoV_!vUz_O0WF
z6@B<&d<|dlA?IgE8U$y6VL2s40u2X01j`A-TT;-140~y-dD39M1aQhQ|1qtPf(`4w
z0x`tU5e11*!&j7t4Kr*lM&oJ2T?+e$8=j9v;~B&MC>VCuz@s!$gkcBOI7Av+BB3S9
zP$dIPv|*U$&hv(nHLx3NQ2WDDoS`iU{>B@^W`pH|;oULlOfVE&r9+e#4U@M6O*EwX
zf+xxF9m%H}9K9fT$?#_o1}M$YUxGeeHLR!o<TZnRI$TRP_)&#xhCxFQa;Bkh8?Y=x
zfjz{t4J-=0<``yQ1})bxopvqP4cpmZ$uksv2as=Qcc()n1%^*2fmmp$cn7RE44zcE
zP-N($s+D5HvTE2ZG4#*^ztn&{0Nx|R@>Sq0GuS-`xpKpkX#f?5brhPaG-Oavw#x8Q
z53pN?rC(vVstvA`=&CVnV1o0u;lR&OR%_U_4VdkYAt)3)b%sgH0qz=XzreS8!*Cox
zgJEt5wB0kjLNy(YhR{zSao^C*2WT>!a)Q!kL*!bFT8km$M}P;0k9R|$)lfj0;)jNf
zlzMD4{K~~o(QbH+`q^RddKZnIh9Am+b=eH%-vNDOsHfW>9veC*fOQ*Y(>}JxuuBNg
zYj}4EN}m{hpkv{EhPU1ZXTKrS0b?;>2&50lpyBULU>P!8{~C6m8Zz~e8#b(>5a5X6
z;1}rGsG-0F+L+-nJ*3YJBhkRd4Ynl|WSua4PQ?)ijr;FI+acq$8xV9fzH%18$(T-|
z2xsGR4LDtl;Y?tzM)&*h!p)dUIT?53E!qYjHgaiZJ7PRf2d0i1Gd_S%9>#Z`06S(}
zM)jzk#&;e=i<fb?BRIW{)wby%`WU&CI5}=~od-3(M*RSI{EXXa$>(p}M{`ktaW^Fv
z1C8$-26n=jLQ`RoaoPXSc+!~n9OO<J>uBW`Y&<~kW{B})`qYIQr_j$7X8h?}u$(s5
zJ%vx<#<m?Wf5s?@rTyPo<BnD+jWAB3giWOJX)*+(jN67G5pB$*66Ev7`CgESHQw2R
zk&QFnr8r-_(ccw=c)_@K1sqK<zD`F<E*kxPfh8IpbATlom%a*vDaN;{xFOY;gHO)1
zOU9vfkV`XewtETh-({muElgZB{yq+gYsSsVkVrRn(8QWybg+V!X?!ORf?38x6o1M!
zzDJqC>&64gP?~4-h=JSrMuR)B0^>%i<tj7|ECIM-EPe}a7a5go_*-l|xdlBdF?t+_
zc&YKyVmicp)7ZHjf@Q|5^d6KOEh8{dVcgja`AQ?d6cSa&Yu6!v%jiv<)yCL2;98Bb
zN&tUv8zod~TWg$8tE@Z5N*aqgqu?``xNBskKv}&}Dgmv*xaEB`-ZQG6LT95f<9oPf
zyKh{}22ZmQ{^C6{-q;WD(C8fu-EGD>W$>cicqkL{9mZ1Hw{{vQdq7Q>(T(zpkBmp=
z1AA=z;x6R6jaw%{pvO2svAABN!W(WsG1k{X*?=)G6)c0sKk2N&ka0GxFP_?rUoC|E
zu<<pTrbmn~{)S&>)Hu_Cu^2NJP(uHiF=;gf$Bl3P21h517wO$RXmV}@a4>be41<SE
z|Kviz(G)WX7AI5QFA#7xt@#TkTuf8`J1%D0Cxjs{li)5`yiI$528)l$_VIZbJZ{QP
zgLz-mwAoM^U}~h)YoIB+1@b3MF1w*S$h5N`w38;C7M!O{v&Vr2o2JD>X^6>#&TEC5
zo~Nv0n5lx+0;f%nT7ZR{l)2Dy#`GzjAUJC}(uT$eQ!YLD7fcpgFXR(Uwh@eFqRF`d
zok=p8_dr{+sp%0UQcOc{!cwX!eLBD;(_imFcbaMbt5AB`<o*!7xMI3_9h_H9iGPCS
znrTfI#M4baOt55_mc0(0nWns1;LI}Jq^NAR>H2@E3R7b#1;KMoks0vjx~bzhbmy7g
zqvc?}DV8GR1*Y|6x6o7{1=<Z$j1%OGOdp*Ft=RO#0oW}uJ*ATMQd1`7a&MZZ(1yOu
zbn`xRmYewGXoZPOVed*)AWgberqW!{Zkc%RQ2}kW$w=PRn0T*&c-!<3ZFXu+U1PxR
zn4YK8t#zjP6!C2^Ei^#)J(I2+jg6*1wt(fn=_P-RVUtO57_K#AWB^)BYc8Sjf$7Zy
z@V?bl@Glx4nqIZX$h4U@)Bd{M^d+`TI7Dd@vOw%Kz1V`*E>rj+=ze6fQl;W!(*g>>
zcAMVphov4<0wpecO^fEBqfbmpZ{X?dGrez*#(vZ2ZHNz;UW<g>ph-u&{UOt$J)k``
zl`n=D!=|rZhQNr)wFKQAH9eUQ0o$1AO&6GdW(t`E;<%}X_7D@M8XW`=nisqehwaU4
zQ0hC)!TiQPupBaHQ-aCS{L`OkbTYS5^@y|io&X-Yn7{Kwqr17G1f4i+E^mYvN6Z;t
zLhh*fX$a&z%pElKA2Zj{rrpzK{)-NCd6|z<Sk>FiqYa#o*=sW-j+-+-Mx(EJoT}CQ
z%s*4c-`~7;1hfFN50x$inupBj%n9?&WHbhu$LWT>ljcGC?N6Dn(+VuueCd5~hL~N>
zqA}Dw>J2Sn=8b>Bi_>P?v-jX|xLFem!87LH=m^_cb3KKxBg{`Oz;2}3--_XmGXEJ4
zmS}ShMTla|lC5AlXYQx?+IjO4in_;|6T-k5XC9sp6Y=KZFsQy@UYY~*3FcZlWpmNo
zO}|#6c_l4@lFU>7yD2!?T+IQRVs51wD%Bjj7`iW+=QN=)%{)lEhRfzvk0F1>?3D}b
zs`<|!;o3Fxw{L?b-CRS5r!&kE6za@0FQy^MGRIMxEZe+{t}Mwhzi5yC=9<~`ZM<$4
z(ebA|bIW>4p5>co&qALH%mM?jLi4^5u--7oML=7TIf>5S7n}d26ILbWpJ*{%W`2_*
zah2vUN{m&Rms6R}EwhD^LDlBt>tL|P+z<wxx6S(oV6fKQ{~fg4F)wQcR%ed?85ZuE
z)vKtepx)d{XCNBPqmRII&zwe+Nu#-+N(}CsfA|+_n#@WUxYlg;r(AuDc?v}d9+=<w
z3ffxDJ~Xlq&5stqi#GG}T`=En{`V^gbeJzu__Wjf+&DP9%-?y#!$;;+TGu=_pG=|n
zXSZ2=5C(h9XBe>5YhL#Xc%GOiJp<Nfo=(Zwesgd+<Oj?lS-=L(2Sb4knYDMJ`>DB!
z3VMdkQ|E#<V$L3ivQcw9g)zs>zr2KwJ~Pjvg~_;iat#C~%)inO^`J#em;c%9Egfy}
z+ri>O@ogu|EDD@DTWkveTrA(yNj6tY_D#^-EJYM+bhpH?(0J71NUK5*i-pcK9<#J|
zf#z*t&%s#uShDH#@o`J}7Z_1r%SPN*GR@C&Y!ozqOK&`ACoB)?SX7YB^85tQlNL9c
zK2BL$*8>Z-G^zkXEMaq@JJfQD_7`E6LM_yswq#P?Cfu^0-pw<XvDN6>S<9tWV2QA_
z&>}C=qR#*pWtmSQ|7gp5N^r(lep8^^=PWBLp!2-Nc_DfqYq1@F2>Ce6@AQtvTaM;H
z_XW#fJ+K5z)EsELX!({Z&=W1*F%V3$OwjHq*}_<ipE<>{8^7VSREv<lqL(ac8iX{<
z-&U|(w)E4=?TTd!#mui-n6wVOW(kZ#KhrJzS!m3#c-dMYk!d;54v=Me-X9>_k}d+s
zvBc73l51H@Q`&V)xepriEb;=lmTyV!Kx2XBb(&ZUEq(MoxnT*H0u)*H{TBkT<n+LN
ziN%G=l}atK^g7(MyjcXS%o2SMpxolpK<{6Lr6wH2N=weqFi~aMO7{`nvg}Dl*Qzb)
zL1?V8yh7o~+m`t?pw(J_U4yZ_W4Trb@j45$9M0UeJTalM-txN*ZZ}$%QGMEdi*_nJ
zY_j-#2DxTS2nD8FESqQ!d|(MIqxY}XGBF*4@zA2BpQ6oTB;D<ntEEuWVd<rNC^{|w
z?t(;@rHc01k1SJnLEB@?x^QUgww$5(c8{fqs@8ff=M`|~iG_a^pwF_CN_6@yK6EeE
zfW>hSSOzVNr$KJW^7Rrb>UnDUA8l=iEm0l-BbKQY_#CxpA471=vg$5apIJn-R~xsS
za|Ug~5=CpDgVu&=@X6l#=?n1J!MchPYlp1L^Ki}4>O^y(ll5FX>^fVcH$s_<b^ARi
zbG3eS4u;&UZSO<C=5D=ASGF9sE~aVri1ibSnjN*iy#|&%te=I$#4&3kCB!|grz>FB
z%ep@pn78%Q`LN_;eVrl~$E^c<0er15jH1!cnwAYtf2$K!+y+>qzkxG>)_t^FIAQ&s
zW{4nb$2bH|+N^nhg6EWV%{wp{Y@N~qEW~<(s?0;JrerjRSsznP(P^tC5Ng7$ujYXz
z!rDR6jY#X?w3Uyt#?c<&ob^B?Xy>iBCj-P<zoj|wf;Er6><QLs6f?MJeTO2$iPkdO
zXeL?L@1!X$*}8)6h`D6_v<pL%W}Qq?zRT7ID(|{tZ7PA_Rcrm1pk1?i(gHBudW7<S
z8P>h7(4A>rK=W&sb(RcnXInM?qE)ExnDIRt^Q<c<9GP!@NEICg*59bQwb1%r8<gF!
zmR*HFk=34_nPO`lrOZmKzf%^Y)SCM>%-*y<PZcv|*6zpXZn-s|qLCHW^ygu=(t3CY
zSgNeKm7v|S?w|--wRI<jbZV^M|921lZR_kIwANZDuZ6@N>%l4z>#Xj5Fmc!VN(Kb$
zt$$Hsxxu=27r;I1m-HYtS~Jdo)@&U)4ewj5_Vh7)V14io47OTVY5*Qu)dBFn&H4px
zhuW?0e~!iu>oED$X}$80UhOXH0PWTvS)J%ksK?g5qv&?G^>Ym*daQc7&8gS=i!bax
zvF_LjOMTWTF*y6JtrUwLuudV`p!FY$*A7|Pd!h5G^%qKT4qFv|;2g0IM}RhJ{d@;h
zk6HctpyiqMZ~f#?@WxoLQ|*=g`V`9kI;?N10XVe2_haaGUjIomI_k1Mm;<G*>;Lkf
zyc$2+D-^ssvObH}E=SidqJk`s^<J+499zG!4~?GdPtYgIYklQwu;jgd=CAl&eb&GF
z7rZ#WUbPgeeb>KS2~NNDH~-Jkb;o5{eQ~vHX~RmbtTZz-HO<VjayHa*HeTMn_uehb
zS8xCVvSbLdWGbj2Lxv35Dhh}KGL#JpD7a9D{J!V+*ZJIY&-tEnpXYt<bMHClKCd&F
zL5#1hAi<2DL@*CCUS)!WF#hO-^)N=|HjE{l;pqv?2*wr%l^sPgqD+v9Vl1bi%2CGA
zmoc<x#t3crVi*!8L}D2XiqOO{W_^eu#WO~z#5aMlAqOzW7;6`Ud7P2`G1L<o$NWK(
z7}d1UJi&-x43U$J*{6Vcih<uP9udaORq!x{vByX^?KC55B05tUhbX6!#^5_cCY|xk
zF(_s*o~K#o3}XuI^fDPcqrl8!jH#iY%~(e_Er+3?T-RB~=4W9ymvKG_B6*By4e&Rg
zkx6U+0!AVQl+Q7^-e49oR?*B*#F!?hct9~jI*5UmFiz9nu9VTd5thmr?zw1{Gp<qM
z`#htu8Q2#XJGP<k65}h1+Ey_p6#%rFk?=J<yuvt2lY9+h4ZV%7GMat_xyDeN!K`Hj
z*Wy~#F-qS8v!1bu-hS5^H;}n<Om1Q*YGJ9FA)=b18;lW(0NiA(e+SGKM%@_9w=($2
zfN5iNZ-GcVBb^JF4#vvIxG|lK*`C1eVO*v+&Mk(J7H+p0lj%11GyXe(zB`N@s`<Ff
zc%F)g?lHP3{(hfvp1ud<c)*ym9->2xKT`qvnDN%DfO*1jqp;B^qrMD%V~o$<0(r_X
z>VW3#bdw1f7pG_4;LIK;RtqHeJISkYM_iqrbHN32bNbgEEf1$%18~OEiPs8AFDKy?
z81!*ELB%b;PVY>IJwJyN`w=<=oQ!WlG|<V5Vmd)i1vH_CIBnCSFVx9&8)!$I+9(4R
z;q*c_n2}DI6#0vC^8Fc-F;0E7l#X@UPdVy1r{Wheh+|H{*U&od<Rt=0bh`F22658q
zE**3^<#dg{G?DD|`9BBHOm&)Khf`@zQSSjJ-HAOP8ktTWFQ6~WiSZdow$py9)X8<~
z3o2MXaqhOGv~VkPdYgje<xV4Xbm_d)yOhVOaLS~z{cBD^l(eaJx=2CEI;VAXJfYs{
z>)p`1?&J~(W|LDWeXG9N>0r=jUtlg+_&J<tbuv;dYnxLZ1ykCcD)fNvaAKZ;LZ?&m
zPT1>m%G`@qx0CmmuyD)i0A(a^J54e|ve&6-4Gi@;-J~#4zf+P2hH}^GTdI;8aQces
zFb17m&jI?L(=W7Lyzdl7WrYu%ra5LqamZ;i#Zn(T4G+S^6Q|j<Jsx#3(Z>_Voc<KR
z;8Ulov>4pYY_5c&GqYv^d~#v_PN|SR%%AAjwU^1F?B9Oo3VQ9iGG+9Bc4Pia19WG;
zm=3T5%q0}h@?ajEfR-n-Aeah1y_oEI&_Bq`q6$WDrqCP2huQr(yzphd`XxmCn3KK*
zs6TTH8;XaR?Nh)EV7_w`t_3oOPQq>wGgt%?%$!9(nZwN2r=u@~nXnI%Va(N3*c#4E
zy$bUYObg{OjxrMl>2Omt^V%y=jA0r-f~WD!njc^(fms^}{bNkI7HCP#qxaBvg83(f
zTTe3k=|z{q+_({LpJuM3WoIgL3+2W#m}eTGcZRv<JD_ATnKYy1Ftezt@+`AH5(>G@
zTNMx~V0JdrTyTzALjjLMX7Mfzt%TW0QMpp4jvnSRCYvf-%b71$!i)3F`>%j`fq9*t
z$&1V;+J#jxpU`7_iMcThmM$~n7el0y`Q>*2t74A)4lk}SC(ur|hN<+07gw1Hl#RN^
zY<vO4QOlgofM^|amlBHgO!*#&HZa$d7mdspCqci7d7c3;nwcviVD|<yhvINInVV>f
z)xx~J2IgCt_O)=PjkzHeCfb?D>FMua{zc>MWO{mm^e|Vv2Xc$4rEg{3W<K*fM&0jV
z{%nBVJIrso!M)22d<5<Q(}`AdgUrGCAorL8sxrFIjQtQI519Wxffo;%KW_r_5p&NB
zC=4-`UxGYls;Nxy3G){!h8t!!tI--^Zg>`UN0}4HLB^PW#K8NfOw&$~apt_uRG71y
zHO#{(oLMul-kt2i`i|;k_pokLj%zO~D5&)-JgMQYLf?(mbOB6vRxuCc086qKK6$W4
zeWB;cdf5WIUaVPbAbF5APRB>QS+~5==fiTj2xoj*U%m?B$67+WFMrmbjSxA+8qbA7
z0PD)9Ac3si@jwY;ZKRA~Fe_{nB8ORb95XQN5Z3F7up7!s+y$5;tOzR831e|WaV^4G
zd`gr@utw=gjbwfJ|8IV<>_6lB9%ZR*0F7oDXbT#{@;Z%HENf>1T5+sgElk9-6!Tyq
zfwhUE>Bm^+t+<oNS>;UFOJuoCqqlYv>*GdnPp}4;U`!`j&*cI86l;X4_L5oO(d#;e
z)l1b_r&-JCJ&?+}ISH*a)(h@{Im7w{>8Qz>ELS^77He}1P_kJ=w1v%K8FS(NS(Z0B
zn#*c^4$yh5muPL3&w6enRdE%tItw9sjx}{R94=)2m;ult7K1ju#Vpoj47-H&PbOeW
zS&t|=RmM7*0rTaoK?>fSXKBXKcY$?j7W6K%N~v1Cf>rVxBrmZ>PJ>)#O``+Sm8=>b
z>{hY1ae!IPI)}gxK1Is9M7Oerm9-f|yULnL8>VZl)EY2rS+jq{=<8UOPtaG->RkhJ
zoi%SM`WjfDeGIflmW+b(O)R?|mYP|s55T7u))@mtT3Nd&UD3w6M*EL;R@(?fI#?@0
zVWE>XI|och7c1s5K)YGic@XVk@m@sdEmqVXh~8#hIRa)ctCoJweJn4^clWdU=-|N}
z)?~_X-(@|b#K-`vWhuNEWKDF1<ULl}Z*coQ>lmdlAF$l0wEH1zs~=o@#B$yPg&|gD
zD?EJcVC}k%<`b45B|V2(-~0eF!gAKZ(kN>c3yNbb<u?F*${K$kWSlkY1VnbTgEzpS
zGy7Rzc<;jQqz&yJ_R<|t*vs~yGTVLZMoJXyXRqtPAY9poO8Df)Hc+0xogGKB)&aI-
zD}CL?gT162`kw6nvY_F`_78xigY3>8z<9Htt_9PFee-9G*O#45No7Cw`aX#Gv%g)3
zF&$zrJ_V5gwsa{#1KDq_LSGPDNBh!X_M($;^f0^U8(fPJ_6h+!3}ycv0+A!^mmMB3
z5ysA-5`=Je7zJS>*r`<N8OfeTpF)UY`<VcGl>I8zbVswFY=lS*yYm^4SazHzOvJHg
z-UV7bd*u|M9A{tr2__QR^H+eG#BQN)N1b9n`yz&&%+@Z2zbR}3E%-9oVbKoA<goX@
z3z)O)T*`>#vK<8=dF(9O5ahGJcn_q2y>B5v&$0ieU~eHih|Yi(vD+#ETEaec39V9g
z;6->?#=dz1>gDYD6Tm#rPNmrR1@@vXkgQ;bKL+y>JD*<Am)X0@=r6Y_+51}1S;gKP
z5BICtTfc<N6?P^iA!^ujDS3aDz1@PoYwXv4go#@A_xqqw$4;Vzbv^r^k6`dRyLTGK
z(!j3tLSG|$0zH3C?0?GOeKVUyRoFM!T~yI_lg$i9tA(9$l(N{Z>;?)Jx3O3CfwZ&V
zr+{t;yNm8xCwo3Emb%z8XcO4Ye)%XAd)SYus`(aMupO;F_T+~E?Pn*&LGliJVLixQ
z_78DzZGgQc17L&fs&TaLvEQZIf&1*&X;=S%{m+-Uua1Z8Z>qq3#6H1*%n*Co^BCx3
z_P(WPJz*zNmHjaLjb+dnVNa(|&5W|2^ny9Yo_7$Ip0b@>LB`p;NPRcQdlL-q;T)jE
z#9od}1rz%?t?Qw%pEKiS^tp0owZeiMCz9UY?heifO>hS||9yo~cyOlD3e1zUn35k}
zoKK$zImq$<8j9W=Jw53@oW1v;;L9nP0ewGC+GFVXbN*q29OA5B2kZdOB@;vfIj_^h
z5yaU@dGcV+y)U6~m=j97`Vh{l|DWyQIKHJDdxX<S+lw&HcNAQY<nX96EsFD=4vI%P
z72QCK<+%I>636je4TX5lSTgSRan9)kh$M0Xh0sgl%)JHdQ=E}&U?y{7=u|-pr-WW(
zX`FXGppee-pbDT2PR0=IWpYZnFTzq5XT>Yf&*rS!4ih<?Qd;ew<(R$(Ode-!4*K#r
zCOT<czzO1F6onicg+_`v%N78%n6r)UZwY6FN-Ik_+vskUbAApww|3$z$J}`kxy%{3
z0aD44ZiRXkXN=NyS2%Ybz?mA(uaqXd%86=(-Zf5d1X{Hm2gPOUIIn&WW&@|53x!6G
zyB$t6an{lnshQ(`74~j$nrt99In%?T(89^3Bh;;&7pG$=Z5)3GP2IOSW?Gi@a*maO
z^l=6$wBOIUMmdu^9AM(N%9;5*TpQ%9p_6j=I38)Z1`jxo{GdL>QSCzCV-9~A6rON$
zDFQsqd76p75zZT_=o{snrcL%3C-x~?PdROi;O{u6<r@lV?&f|^KPzYMk8eQ3h5Nzp
zXzk}t7=<NQZqRBl-MCKlgK+1%KY;!L?pi7e_TZ*aUeS}gbO3g}xW_1reURID4Bq>5
zeclH-#Qo=O3^afnOcn2e+$mK59>iTs2Lyw;@0P!)#BYvUN4t~|uKyn(q1?|m116Ho
zN`{FjZslhnN4Y^cup7-iKr62pZq7wu$8u-WGZM%Bs2L{Wxgj!;1n%rM4DAH>IXYW#
zlKToJcTREhf(q7SHTTJ3FjKkQa!96e)7pTN&i!TrEM#(<CIc*sTmLFZHg}xL7IU~q
zmch}p+`doXb}skHPhjS8$M!-bpL-=5U<F)z3&75Cm6V<@<i@>=z9R0{M_`t7!zf65
zo?G-Q)Gu(09LM3zMeY#QB3E$z<v_c{9i`ONW$tpS4yfdQ`~pC$xLYcKc8$A^^7^&h
zh$~>$ab>i`tLJt<g8^RWKJ5l*1Gk+j6dSp7E<?SEdzC&A-ON=`zN(EYr+rsD_Z3<{
zb#MdRX*Ji$eOwOG#Vy<d(#>_h4ljDRNqmr7+%r8eahtns2xxb?69r%naC0c3ILKWT
z2}}359EzCT=MFrA+Yh)KX!ZJ#+qxN&kGRj$et3x6<pG1kT*-@Qjd0H;!KYE~#Eld1
zHW}jvEeG0DZsdoM8Ry<E0ora}@p5?T%=?rQkuJP6`ku)iUJ)1AdwGBT3$l;rNkwu8
zc-$DYJb2Yj@ZOW>McYL$-dPIf9pp9k!=N`WWi2j{5AXUx`0LB_X~wni<1Iifuw!x%
zZ^8*E2J=Q}Vmi#rjR#r?@0U<$gz{!n4fPS8iwr)6@kVH|AI_Vx112JPy{j>b7@m@T
zYq7j+`mM$B*3xe+p4Uc!vjkp63)GMCewBk9=N+j9N+RzJ3nYoBZ2_1gg*RV`VV~wb
zL!qlwp8sud(|C&;ft}7<@dTDKcuG1?c7~TkClNDw+uebk#aopMgJ*f8iBQkw`S+of
z$9tJp&H22h4k#4x%;8W!$FsTttdLjoIV=?MZp;BG=GEn4xFrr=57jG|@`@=AR>n)D
zuy6%$2?ZW5@%CK<%w^s>`gv6HwhCaWig%wD4b?mar2wz+-V(q>4X-8(p!Ga2dbM5W
zEuu7c1J6Q1iAG+w1d>g>w2c63=Cx7%-VNU4CD6Ocb9{uv#N-ZMEoFl`c@nBu?&1Z~
ziR*6Od^*V7!^=ql=q;X*mKV2q9hBnj<t_agWPtZaGH&G{uYp36_jo1u0eYX;ItP{>
z@Y<QM`;eFA0xur%N@#g7#4}X@Wtew~Cg~C0eaEMuqdY5xD#mypQQ++<@1OO!2;;n^
zd^qFEU$q}5-1xD_q3_Ng?1hN~{P{Kz5B}=wQ1|2yC?Vp-UuuHggZyV2A?eMZd=!{I
z{68rU?8`6f2bdpU><>r%`Nvb?+9AGQ4MhqA_<N54CWs$J=VgQWwm$%Km_I<_*%1D8
zBlJW0XXqy%#=lJEzv28)DlCiOPkRoMQT*&6pADGG?$ACamLK{eNCMyeEr1>4e@MTC
z<NSAM`IyLGtOZIEU+^E8C-^*ChMnZ6wZn;1{0=?zlKHR9hTEt4Gidpj%8#;xr18I^
zw0=7OR3u0SKX@U?8UBKPc%8++CW1&d|CmDy{T%*%3QnKpTNS|0<?o`XKpx+|8W%R7
z?@J#uEa0<h(RYp?LyNLP{uh7ZY8UZS>0m%He}F2ZO86@}K}z{YXr3zLTg#zW&JU;9
z=Xt(}Hmw)<jTAP&$bX|5A{G3{DO6>1iNAO$+`r6Eq@_zGe?k|qtN79Mx~}0rrWDat
z{uxS;UE?#}L|-lcL#ptt<2$#bubzKkDhAQOpLYg*jeG&s_%!jK(0;9%|JyszyTLck
z2f4}rL<P)NzLxezZTuVaX=B>Xe|!VYPJWIz(7O2FQZB5UUqm699)3d`uy65$6VZ2@
zzup_8=;gonIYj#T^Qijw4nO`H26LA`pXR9nemzYTgZwG~K;%B(lme6oeB&D+5BcT(
z5P8JUejWCP_?!3rKfT9a_XaM)2*2?iD30<|{)FNfpLH4JDc_&ABjfyiF3{gC5G_H=
zS@7$AIO8H1quTU6g7;fsey<>#UUB;bvcu@xFZi9lu;422n*jwkK_OjycfpGk3_Kv1
zoQ~hIhrnwJTHkpJ_N>CC@e=&r4aI|kVv5>$3qJV{pgw{*R0!uQFfIe}6NF0u<1gr-
z$LNqCrvWAc1Oq|hpYS{0AcEdu!PL6|3lV&h0}?7oeFo-_2)a$s3lpsQ1|(ci<pJ{%
z0>A&SK?S+XaSfvcw>*J)RPgx^XhjR$=*1HwP}7eyR`B}<corup90ORq;3Ybvd0Y_n
zIxHj#8tFZogiApu%uWctrZa#i1@BXA;*_9aDnye7&uoDADS|m}fH^JD(26Zp@aHfT
z(*#i)A(<{<-bP=Bpq*0DX9RaCw4EtfK$+|;!8=q6nJs9&39uZ&ny;XDR&b*oD7k_o
zzoIWsFiA_dB46-5?RW|Vv*~V~6Vxt&`-Ot_R47p-@EL|^u|P?IgA#%95L%^zW<Tha
z3F5woNV(w740v%~u$>lc7X&+Kvb-oLq*|E@LEr+2ToR<sh50H$-KQYcg4BiZ{)%8N
z&I;pE5d^;s(W`<tC?9f75St59D~LS`m^y*95tix&m$yRXx*%X2UNi`{zlNLEC}?v-
zUz4DWiW!;(Lo}=35WGX7(3^ttSr|);Ad%jztpdSnsJ96U^iXIQJkVf(9fG7_DwFIK
zEVO~!C73=5qTPb!ndrPNcs2vAUcnbsrP3$JoC}eD!OwpI^o}5#-Z%q-|EQ8{P~iIn
z&fF9Hu@kNPf)AfygbxH=owy_q1y8>K%8;O=7wV4%Wus7kBG}svkzv8yTM%)K2)<Uq
z?@_^$cOmms;OvdgalyPF0lHfl?*ZZ>^rN`N9%035wDt-=qseQZaDhK0_Y2h&1#}b6
z$^&s1)@H!p1Hv~cB;p}_c@})~6qbAi;w3zv2z76vl@h!@!g(LVp07jLITc(#VZ~!8
z`U^MF&+CvdjExZn3X>`56C~U<34Osr2^F0j5l)~Kc9<}8HJIVT{AjoqAq=MYTcmJ=
zf<8xub7{{SE$nOpbc`^d3}CUskD4+1IN{;TV8#o5%}`GeI)0@0&v9WSy>=6YPw3(&
z340zw|AbKR5TiIL+<gT4$-*CAgno+f5v>hR3)5(zslrdTLm^FgK!{6{E)>xQJVRKp
z26|b-sk8&m7G`aO+c`peBh=3dU;PMrxx#m<(8?EHb9{@z6bKK~frfL!Cx3!lC~Tes
zgGItXs<0>)F3Le)sj!ot)H31q_0TUD&QC+@yim6c1}_Mkr^Dby;W|2jd`Y;Lszojf
zEi$w!h5y*msuoVCY3_<J^a&iT5w4{&k*mV$Un$aYP1sEZj&;JnPlMD8lPP_BT{xoy
zq(Nw;Jzb-)l5!AD!soZbnH$0vF9G|euu6@-7UBC8!D<!0N>gu}@E5A<Y8Pfdg{4m6
zd#^&FOPKrtz`BJa6jkdLUZ=c9pU`=bzCF<|?4lLp9pRqI(6}p{P2rkBp(qDv_k=G}
z-O+uak_qxaxaA+fJQUWN(Rw5lRzPG(xPd~8PlWk%G0<V5Vj)}`5iXq#GAcAsfO1Ue
zO9vpvh5syrqq{{t_3+SHH1Gu-({T~~P4yOgM4Rax^<GiZ7Pz=iR71I4H&GpxWVnm|
z@Q26&(M}2uc!=bmfq07YX`AaMitLBTK~X2=0=z{*Q!of0kuT-WeMM8N;hLW)k0wTc
z(dI@#9}*odfn<Q_hh1nn0!3%b;aiaCVn2Kf7CBmA_pqq!eK12r?^a{Hp(5cd7(60+
zuN<u~QK$i93KxlI!bF59m~zpPq7%E&7bOb#8+}JbW6NM7TI6*BBu3<N8PKt!Dq3U3
zi8=}(883Q{LhA_*(RLv;j*0B^;OTME3QA%pissYF>?Dzf9{&@fY&Wz{ik_jx!zs}f
zN;D^nKI?*BifI3OD4Z7Uq7-1NX#Gk^rimu+0N5GPT|X#fif(R(WR|Fu9__QDM_o|Q
z6@6@h`8<)Mj#41!M0bmEF$zTyR0~xkGChFbrJ~dH!YmWrZv|+%XjUvVE{e|4iH{1=
zm#bjnlIRUuR#k~sFGs6d)GCDf6_NW%T$yVkc05pOMF|?T>O`LFq23_!c7aHv=!Z8z
znnX1YT9MooU7-`aEuvTojkJm$P`so~bcfP1?V{>&c+nyHlvZ_}B0nk+=@M0ZfT4AZ
zz9hGML^fJ^-4b!qAkr&pii5v>qF3qYUcacGB42kzN<P5uiqh$oF(~SnL+_qwV3Gsa
z_eDL=0`!3>iM~(qP~_GNXC8^xNYOVWdg~{kJr+g&2<8*f<s^s<iw+oJa6}Yz3814Q
zJN?$jM92LA`c$;(G9<@E-|En}TfEB(^Uh-LF97Bu&Z>vVK5?QS?ClqS+C%F&S23#w
zCfvjeDG}-}{$7boazGrQhp2}*G8Lkp;uI^;4vM+7Eb|sWPq8i^@uwVE@)f&JMxUSf
zEIq~k;>Xh<a!9PY01_ac-3F9k@pB#MJ1kD81x<)}a~%}I#4q7><d_^Tes&!O6Cs{O
z#ek7wRRB7p#8c>Z5iRD8z<i9DK>?{)@x=eo7bgx|iN1L8TeJpA5I+e;>zG*m8Af<q
z{1=6V6UEDEd!8iDpqVLM{3gxP8RC%t(04{0%>gr0{8lf9>&Oy^eviRqi|u?^$`Ma|
z4VKP|^EF`RiWQU5$`k)idzE}~2M44;ydw}W=fwX~WTsG@^Av6uiQlH#wpd*LGC)hj
zSKVR0RQwYQB4uKKTBw$bf1?G$dGSA8aOQ$|Q6PQ^7ad~V9hj&P&%XzaOXBX$;9eG2
zQB_c-IO`}xtHhh>%azq)5!EnW5sRtR?wa^-I?q=t_K1L^b>h7PU^a+1(_GRhZgYh~
zlX!9gn9X7dCE;#}y{IVYrg$A4hiDV8r#h*2vE$n}G3*ZUo4p{N;-&`>?GiT}hJLrW
z^;Kx}h(CT7ptr;aOF?dnvuMxJD{iF6sZX360Q3FgIbYx++!6maj@Dgq)eWEwh`-$o
z$wBe6v<bZ@{wf5R_r+KLgxv??X{RCbP(0C518*LQKS)C7koavXY<VnxnXcCpv4}Fp
z!(v@O$cT7{7}%rYGD`l9i4Q);<$fyuYd%IeE|y8r+AVok0(ECeLKWP0k+>?*w?`69
zmt?P`<vI-Rla$hvwqIhdfLT{b`%eyV-6Z4maJfr9UJ1JgBq29o!b1{w5KK?W@@g=>
zBt5x6J1AK>3y%6qd?+65C&{4i75Gc;Q|#)Hq%9I&1W4*A?HwrbQUE$g;<yXFV9ByQ
zAcrM?7(qfLpSeOZRB|YkzLj%CGLx!h!Xy`C(HSnW(ZVxAvV-a_A|)?I!Qm)L<gc)F
zRI<w(=A$JamBK`f<U$BwVkHOOhkCrElD^fJAc>(l|CnR~70Mr%EdLLBiIOW?T*DKR
zl8LxLCnXOHp>Rr4h3z?xiAxqx5lE^;LUUP~<UhKj>5>W?S{V|f0tU}WhJA5KGbN%s
zP|T8q&<8-WC0<mVnj?8%0EM%X(;P_VO1!8-Do?U{DkSqIzb=Ep0!c?L%%79wgo9Zq
znMFlVMUrlMHXX&1;t-6mMDkJr+%J`Uxd)_7GWZ5axg?qo#q*L>D%rUpiPu8%qQr}i
z<5x&#P?qzO#HR!%E=ywkV7F3oc_T=b<as*GRV^{KK;ep{iq_jTlC#$!c~$a$1NyE>
zw)vt}&y)mFQ02NL|2v2_Naj)arcu(A4`!3Zo&wS=8KJn^4awj13ALM&sh@z^B5BBm
zrB=yBI?UB3DWr8#hh)cO46ReLU@T}EbK)D0CzNX%kXTjF7?g1H(7Gq-e;t<YOXA|7
z_&{=-LSPRiKc9pCBZ>DnAVZRl5m<U6*`z_=uq5GkSQ?SsIRoaX#QYnWW0J|mU_O<U
z(@Dv3$uCr8=`2;zX2(VP!7`xik?wKO4r;%2aW^cvN~h2nD>rFlGg|J_zow#fK+63U
z#6$W)6I}C@9-D)fm-G_-J`PG3(YDuH>P|s!U+EikIKxl+QY1wDrHU&U#3AWxF1WG*
z(oM-Q6ez7d1C$`?)`hTeSi0!{*}D*F4gF?ArOX>pJR)tNw@a9G9SbrM(uGu05-I&4
z5Bf)?U(wPlT536j%N--#T8X}R>A&AVJwf^*mDnDW22(uZwDd{@ETu}7hoF}x9exE~
zq)Vq$3M4~%Yy#XqBhA|U|1)sXS~_T*BORlc%vovF6e#9O%?&W0Cv{LFC|`P20PF(k
zt3SfvIq7sN?<ti2*bcoS=^R?U7fWAng5477Jt~JNlU{!j3gyzbUxMU$>A8z&U6AS*
z!HbL16OoX-EIosq0M5WkU1-HyCB1$Eoz>Dd+R9&%o}f2vjr12TT34m>f+2EEdTcEe
zYo))_qNh%JYB&6?mu}pR(O;JqMuRj+V<{WeDE)XY)SILp4e+p8nspv}H>5dBKyFG6
zv^{B&&Y>ubqgCoX56w2|lmv{oU0O`5!w%`wR_J$1V?$t~OZqMCX}hJJ(}3M0{bvqD
zZb^TmzT482DR8Y<`X6SB$$iqVOVR3=9;QY39VxQ|%)8PbQ$Pl!@z2Bjp!BUApxl!N
zQv~k5Lz>wGOAn-5T%hq#D(QpFBk9gUbPh?kI05ak^elyjo=8^@Kx9~2L;qqmA}v$k
zR*XuW>HNo-w7?a5Po;9&7>r9R>03s-W!aRibdjB>NX<UkFB{OeUzSXF*;Tgl4~V$Q
z90Qx7=q`J_3up&qar7B351H}`G(2TD>9yn~`>PS=56b@V2b#Cc`3OXOWGz&B>ML9F
z|E;OaNUs%tSv|!VLuEVZHXV@#Tm=b}4SkQkaM^?us7J^oeqct*7W{yV5G7mXpj&xV
zwr?B*jh0QTM=M5FR03yWWwo>nj+3R);~y`JqdZ@NY!(&t9Fuwf0+Hjg*|bSZl)XtI
z!z5YxDfFF?4LjiBNm<1Vv`)#sISa{TneRBvr^p6rCO$2TSqWyUY>p>o&(mb~f8k=f
zY!l6s88S{E^v}r3|AN6x+3f{rWy!Mppph+$Ajurr93!yL$|`69nJc?XlXjjgX9R=D
zmn~31vOxC2YB0~q5~zx*Q1%I>M2ciW+7T4XJa`Z(ky!#LxKb*c`x!*bWtGDi?|E4n
z{k$&7E_@8T7iCGWz{3jJN^<y;ERpInFUvlk4zx;H1l3qn$y#V;s+P%U6?{eZ4<+hq
zWC!R?dsP-l@rXLvJM+<p@1;{9;<{`mMQ<Bq7u%?MrBRk01eqq;<~DfIEc<>D6mQ5p
zDdcfewk#N4w8-))z0@k}9|E&YW}}#QyX<u@=yk|e(Bi*ScFPr@T{1rHa=K-6>9ajO
zvf%$9a!cm?I^4c3Tj>F?URl={=<Ab}QS8joFH51g>mAw7<<P$?+eY!;0hxsY(}S`g
z30n7L>sny<zO0uXnFq2DXnuSs>!QObk7TR91sRfU`Vo?kW#zP1dm?*|A{fIm=2nmq
z*^5-^I4biQgBN46d)+{JD*KhHamO99J6F)TTi#EB-aT^HlhD{JA3O?}ee$2F(!@>v
z8O3|u<&FqgIv_{Y3Z4r2P6o(9xi=-Hz2$yCLc~XIm;$D+{0%D6@{@1s0kpq7a06P0
z<QJ$;IY3?~hJ`@+Nm>8~$sKn-K{HtX*EbM7EbpS?s1W(fX@Cip*KWqJkI0j$6go^^
zL5uis`Qi~6jF7LUC}E^Le-c2W<T;d<Ju2V&7#>E;SJ8_vM*j0ekXZRJWi8|6jzSD6
zUj8?QN)qI$beu3zZgZ@J8%gqCDR_NCzO@a`B+Ead!<Z>@J1qoH%Ri%FU#k3c0a|JD
z1KR+aE{}N?%nW(tn{f1uJoqgzGv&+t!OW6R5CJS({@Le%&XNCl9++q4Cl;ZVD>wWK
zk|+QE5WL8jpRm%SS|Gnm8OC$+7Al-7l)rEhFh%l8dM6jlUyFeICGszd(N`*em=0!{
zd<umS%H^NW#;rUr-?#>77vvI}r7y~Tok1$(jWo+&k{_gb>au)q0_;}HlW6C4Mc%{%
zvqqj=Mc+WVDqk`Q`q$*2%tU9c{63uyzAlfU%}0ZL`fFe|$|q3x_LiJ|0AAdd7t!JV
zUU?c-WA(|c^g8R8Ur576xFh#X$B^#IpZ)>nfPCXA=ncxVcEG|tIg{MJFP~6_z6bI)
zgzg-ZAIeMUO!XuAjH3`8l0Ur)_aDnk$nPieWZE7L%g3l1WJKPbk1>tPo2gi6Or9GD
zz1@n<yMX4b2u*}t7sb-U(A%S^3IubnqR1U&pF;l_3i}n`t0Cg5SWJO`H^rTA0qt;C
z<Ssz-fFiOSzIiAPQu4=B;nfXMFU4X?{v1>^(yZsL$e`$xkK*%b@WNN&(+5ZW6lF9)
z`737dfpSPu@-rj@6yeoq1uBlwgA=4!FbaiW#X3q+99Dcw!OalGYZR^ubtr;(fH|Vz
zd!requ$)6HT;c8s#Rx?d&6AOew^;y<QpjkLcU18k{h*>1>*<R(F^X-JIFD8I)AJLj
zc%I&B@rumbxG@Qe-9N$7F~yhNuzOswkdoqwitCf0o}@TMEAtZyM==FwPAYUXeVkGh
zOa^GOqK~$UDT?P`1k7p0iK!r|iq9$Zm!^1k9UM(pWYVTGLovP{XlE3kRRbkcQTG`v
zWhtr(ft{@g2nESeT;2z}XBFB{fRd{auZ4P^qK`gIn6LQ7L5Hae6pI7FJ*Qay1wacG
zi~a^FQha_Bq*#$no7obDG7uvyRph<|&@#n#A27=msbPRQuUOm&><fyI-hskJMei9f
zD-<%i+?Nz{SHOIgVn1aCsudrlqIE^FtR7%BijYYTXk1mSr>XdwV(k(PrdE+ag@APm
zUk{A8UeQLS{nr&=Q5dvAv5L~@jf(M;U^Xdsd<(Q@#cK>)=NpRLAJEsTSo;WlZHkR_
zoT**$@HK#SDAbf2>{R?W4Q_WSGQULYmLh2;)mh(GEL{WrUd094^4(GNR6+5s;!le0
z3@8eJL*IRcxD3ubP&}k<;6p`{3C=uHT<nCuLyGN-(Dzs|b2?g26i;^pdsuP02d<4M
z+-TW7s`!a&NXHb-ufesaiqu#rj4QUHn#wVGxAH7~9Kc!GOB)Lp<qs4>*rR;s6qtLJ
zyEfv+xGER50NYJzN`s=ia+D@yPvw?Dc;Tg-MyK=+Dib$B-CMbiiU)j@Y6|50Di_{>
zK|keK0o?XiX3=Kjkg|L_oC#3cxlnfmD%)wz7Nq=?qR+v~<#W+_Sm{|0&=BR%H_!@I
z{`N6^I-;C<AJ}2atn*+-DoYqJ5v6RU=+#l>Y9+8^m3QfvAE*3#GDy5~`V{mfDBt-L
zt{qd>J&)FLWhK?6CMqxB*F8DOp?v!nSURDUxL`~tm7*SWo>DIO1Fd9b{SL^aC>vM7
z(rM-LFfdb<a+-_MlxwELM7q+2;<g#e_yl;ErF@HO0kW0XH)6aw%DM3nDO8rx_f3kF
zffN@gR?dlo7bQyZb6}P#9fh<|C{vc!K(SoOkip=2<=|2%UQkw3HStBICnc>al=JSO
z?~+pJ269<hCkClhHdAz>N;!>^IMqtmG+<v*Hb#NeD7RCoVy&`p9G9z3xr#P*^~!m<
zU|v@`=uO$6%yle;Q;o{EDNfy_ET+=gX62?W=)9qH@rL<UW%3n}Hsy+7T!ePzr<9KC
zP!7+7zn#kYlve9f+NrdrTbW8(kRIid1hj4`Pd@|6K4pm!di~0&zhazsl$$6iaaXyS
zg4P4dy!Yw(8&tZpz`dsoQo^_U%H|3fe4yk~@^nZkp*YH8C1*Lv6Xju=%Z8OHR82gh
zT$>5=qsp!<sE;XEQnlPu<+^`hcU<`i<qus{e^o<ok1Bcx4DD5IxrK}1s%lfB&rRj@
zEbaf?RSmRh@l+Xy;Hj7DHa%(wRRbKfd{r&9yYf>>yD=tzRTL#(168Ky&=;h7j=pRX
ztV#}mdZ?<Jb~#5>9rVHsQ)TXl!5CGX01C0HE=ruosjjA@6|XW<4ktn7lT3f4drb8b
z#SV_Ep3qi4QT5h~FqotYISb|q6@xaqCsk`!!u%<foj!q-tcs>j)1{~)sY>Fs>Ja^j
zV5;i%5|~d@-7G>YU3K?M=w+xDQi$e^>i!ZK%mgOPXQ^&cSR-3i%7=m@N3}}|(6g%B
z@1dEi@_Zi}d8z<+IGnG_B~qZ;u>cz9RD<ETz(uN+(P$N`&OU-diE85u@S;>TGzC7D
zsS;_nELUxH1M|FU{zIr=P(4qHgNv$bbbO{ll~0kwOR67Tp?=w+`ujcjR;e=10k=w(
z<P7X;)ym(Xe?|4W78*6GTc-hYRaNSM`8w4I9pbK6@j@YaT~+Q3f16a3C_LA!`i$ao
zH&j=}V796PXl31|Izu&z?W$!L(dtmOeSub|YN`)Vx>ODhh2U?gx+o2QTXmQA>Ak8K
zKE{Q*qxxV1WbUfGsMLQzHH8B5gR1U8xOPvq^<DJcSABg1%txxPX<i;u^}Y-8Sas+$
z$cQSRidsfh&wmKXG1aN3aBa7`R)dza`j_9)=b~miN-(B<YW{QJ?pMFD3fQjdtea@L
zsehtb(_MWi79t1K8j7#^s!!ZUpPxF5GUxv4v<nb9q^^Dd?*r6tsK5+VFQ9dAkb3Jp
zT;O1JDOH;uR!_YL$q@AtQV3Q5Hw_o>h<ZXSO&?+E4eszJT)p`#C`PCszKhOC^-2bu
ziBfMl0CH4ak_+r;wcAnj#i++=OB}1dqXUUk7t*I8<JDcY=u1!^{TE=z)U9*TcU<l3
z1uqiSDUC3cq)wXzM^C6{J`Y1D)m7P)+&iWIdLk}jvbvk%@+s<7FGKOP`b`ZqQq>Cs
z&`MK(LdmXl^@3O7OoqC;7OgYtp|e2CR6F|uElbUaffw28lSg1aM}0C2%(H5z%TUi%
z2T^D?PwoE-MDo=M<IpQmpD3gF%Q^Mvc5n;T=V)j}Y84$AEmnW8MXN*|L(^rcTC*Rm
zGWCN1D3+^zY1e&TonHv%1-1M~FfXbPe}@}Wq27E5ZeLOt_d?{d`n5oKQK`O7)m2sM
zSbwx?)OGc6=Bj!M%@>Yq>M8W3*Q*a61oyi7#s-iE^@eu%-K_4S4EPQ8l3h@|ss303
zW}Di1D$v^1VmhkUp<Z4AgWc*f+64Eg4^#f(mfCF%FmJ0D_&}sry`AReKDCA(?SAzl
z+F##M>uDEx*P-4<3HSl^H?e>jR5#DSZN8`Oq@tP!>Y!UN|4_}LB;6x*&NkQ`QvbXT
z`j6HAAHm=gbqy5<539?m%40+w^)~uO)%vYqj;Y769i04B-RlEO<La%8Fy7so_*C>c
zYX<Iu>7sF5`~{ZwXm;j-?A7Ga&S0OW_8>a<YsQuV%~iAd|FgBGfa+A;H5ptub3pU5
z6R<rr%ZkAC)U4#fyq9LtGav^wEqu7<t!WR3B_EAxD<pk28Bt*RX_WNM2!GAZd5}D$
z+2VK?+yD)~8O=b=-Oq4^f;26Z`wG@DkHMM4n$Q;@5~6wU19%v!c|zs%M>M8r*bUQ^
zR>9G5&1yP&6`@I|hdEN?Ly7DtP1|1d9o0<#8JN+UpQ(~BMl*O7(6O4$>i`|6F=f*8
z7q59rz9ndaXrel%>1u<e<C;12+E3IhqB$^0b5ss;Li0`;uup3Kqlw~_=HLjNN!GYg
z6?BTGPzr_9nwTvBOVv!62<SA;(uojB*NoE-F+;PF0ug64Z_?^2Q)4?v-(bknuzmn`
zwnj!}^*NgQSeQSnad{uDT+JVpOU=_v{v7V-YYKZIS)kcE0S3=$rqXRH)CgySS)|!^
z2ztdDCWT*1G|x>$t5h>h3G-!|6%<%5*W9P_jPsgo$|hXUY{EX-G5MlqEk*Y$G&f?P
zcuCVlud~aVl0(3*)GVTc^edW%U@&Vmmc?jY)r{Og>zZa~H$1G>?4v^XI?Wj>1g_W2
z{ukKSH4mN#Sc4|yNAxvnIG(WEr16Nv=$kbss7&I9#yABEj++|yG`QHJne!VITQ#*S
zVYf|l_+^-A*ZjqWeuw4<3L<xEuF&hZOS66t6uUJgLbQ4`4OESGOS2G*>B+Y>>Wwhb
ztEv14dVQKNqhYCE!&?WDJDRoMLFBGRLe-Q58cQrB2OS#KFW}zO9Baa0?rR$8h5JA=
znWnpknmpQ(Khh{YATp$Bo`Sx|npx98o@nZBLVsBE<)4ro(abytkx`9`j>wH^YD~DI
zPc<)7P0qMx13~ZBHnYHV*2e#ck?qyKOG%V{T1S)s-2K|0Ize2ujE}%|(@yXNn!8p+
z^>zoezb%Ht9@<wa9O9|X4hGXpTS8CsLG8yYfaa}zyB$m)?H}17zS>gyt@~-^lqm7n
z7Ey%gkamd`mpMTD4%N;EYWGnBJV=}5pdf#+wvr-phqd8f!9<Ammr=ArwehJSN3=f<
zLqAL#L?03j*FHmAp9t+s@h}moZK242ls5QN_<K~FN$Szse^$V?80{I#!NzKJv(Oi(
z{k$KyFkahO3zP({CzYBV(>iJ>{&HMfz6RbTYJKSw2T9uR4ny&Tb{0*gC$-76=Q*Xl
z`2(Cu*1nevkyP!{4Ctq6Cn#YsUCV7jD?_`V+&-h-KnKq<wF{2{B}@C^OHjzxK1)&Z
z9IgMK06VMQ_B|AGwP#1@^iZC*pEgV9v_H`^R;aZ<04dUXK7~)E+U_=(DAR5^4Uux~
z`#sRVsI7Yp{R-{2PvPMuEt9rYRoY03VO49V(hPn@yZ3F72JLkjn2p*&n%$eUjue13
zYsctx$PKLv0w0daH?@n`(F33zqiXk7?Z<RhtWDc5fquI-g7)AY+GRA|b!s0ifJm3N
zSq{>z&B=jCk9Im8l(?m>rm*5|tw%okdbKlthuuD{E0zBCYk#4li#ytGO4Hue_S}W}
z0j-V_LykeMFO{R+)0(Lk_P(}|LRt^B-&}y`L+!y<Fdu1|a=;8}+lrwvqK%_jepEZX
z03u`BFQ_d4sdkWx5XM2Euv@p~Utl`xrWc^kMfa9JeA=&Tqt}tEu5mu}+;lI|L*?$!
z$*VyR=>DXM#zU7f5#~L0lPGNLrTh1LFuirlzXb8oeR~&7U)|LL++RQ4+62J(>l&S)
zen{7uiM{~c!(dnn)O}h4ksuv^4*G(1GuDHI==Rg(7ph|)hlfXWDW`!MrgOYk1gFAv
zo=vzyk-BAcv?5CPE^Tj)>N4L1OpMMg0Yi(`RZ*rgPIri2ZV9?kSHK+8HSNQdIj(zw
zg2#!v1}c(F(xu%(>y(Z^AFX6vAVpzQbYrw!KdpO2iP=<Ll@uarx=m~8SxMLZLRrWR
z-G`kJJ)?VV0Ih7@)Mkt@M>n$#qGxqmra>}ScWezvp6=a5F!ObTK^LqzAv9wXoGI2F
zZpR=>bZ)<)uT*!8-t1*M=N0HH*D<NQ<Ge1B5@;86-;lo-b&*Rj_{+Mv^d0(2-LyoI
zDxDt{Emi9#)3;}@=<+2{uhF?tJnyRRU<R1ibS)~V*Xo{I3Sa7UGaPlG^|}%A;<`?r
ziOxn{6&<H((ycs;K{V^UY#=vuV#<Zy)HNnSq(%2?D_X6(pIPW@(@k!G_w73UK6u!n
zo5zKvPF-Rjm|eQm42X2=evX4)kIw!f$Ss}34(4rLd$0rdzE}4OEnoX|iQ(w%*GVY<
zcSl!u5I)`271P0kd%C!*Aoq1IiJ<U6_q#9559wlQfBsnKbPa=eqMJDvWLS6kUtEL{
zUBzsOjOxT9=#A@+?*#O2{mPXPan^67Lr;734}YWzoxS?^X$`SYKat{}`}Kd&FUVCN
z@he(x`dhRYcGp|l0dqjV#|9V={h#z&@YILXI?zl13<XDg^lK>$>8mfI52X0%zupew
zuYcnayf~yUrC42nevc6-fqEn5DTDOS-l7VfV0{j)kPqu;(`GV6&!h=CRNvtYnIrm7
zYjG{Y^oQw?bGZHh6Z#SQu16Slq`v3{C`9Q4yI}XIKADmV(fXbAZG(9Iw2M$r&|6!e
zcTDe!bm`>ddM}ESCF-9ohI*2I4Fz)?C-lD*f_qY*NqOZ{`nTxRZnEAf2{I}Ax#ysG
zT0h(Zv{ZeED-5RTpQ{5&*I%YEOorZ@a<6Cf*|g8i)Mvc}^(_56H=vNMum2Y&a`X=-
zpzo~yO**rmtM{NaM4o<j5cKjL`rlszEzn1whQV|CJ8X=;P;a7)U6J04_AJGEPX!c9
z^r|Ajl<KEZIZBznoE8Y>`X83S;Ca3LISllIKEDR!qJEU3z7_hnZ$R>rKISYeT-Mjn
zZmd#&AqS*N-%L|zwcgQAv&R+vj6sOj=w}pwT-Dz#1k5%4z;rlMtAC~x1Fh4q&O@tS
zUrvGe>-z97(Q44IB1aqb(UcHw(ral-Y1ThOfw&v`6gow8Q(w6o7FzUris!ZJH&a1U
zo8I~u%y#`FM=Q8p`h8Si(XG#T6P-Q!oom6or4Qgh=C(fPJ@obJe=h=PpZ?8{Fy4NB
zBIPaa=qFvpK=10EC=5BEZ!uy_gZgPkh}_dhQ*qaQeJMQ^5A=OA;O~&0GZ%f2^>25f
z?}<L;vIFi9>whHkBl<oKU`F*jXqFz+Yv{!GQ+>t95FOWVn+l(H8#YkR$=UE3g;87#
z3r|60kHK>vT6+!QS<rJea6bXl&EOFR1$V<N8t(za544f-Fm&-C;%OMBteTgB^(=kJ
z`k*0r6`J0L5c-6lk0FQ$pL`AfQWdzLVLSbF{SAlT0?Z*p)>ViE7|u|vFVK)W876`Z
z&#E99Z1}JeeTNNyd;o<ILlV`Bgc{Dh0)s~kwX_-xGpu_DS1sI7MpbB0hD|3XObFuq
zjepbGMnEx!#plr-Yq)U>mnzQiR});0H;mEIg#<$pJ$lCsnKL1B-0;R}z$O~LrV~p^
z1{=*ECk#LFAbHXdNTGma!zxOXr5L8r2J*Dw5G~<S4X;qGN}Ayde<-9I+IFKa!;t5=
z3VOy6VF75SLGu(QvJ9L;_>^tv*p61N!KDv_%QL)k8O(e`2VL+&!wNn~ks+A^R>g+*
zXlYSm_@)acN)6lRqg7@|`v2m`kVW5#Id3otaBVIa1f?)^(eSk%q{47=8co8N4C!wJ
z?XqDKZILSt(G(e|GWf+qquTI_I~=}Z_;v@(*BH{*0Q;)pIu(XoGZfE4U#;PK6wvAn
zp|qT>H)OwszUv0(4{(7R3|;eJq0#W;dW@yXuxdJ>n+>xl=XS$j|B)gYHw|@ky;=-8
zRG-yqSeyp5Hbeav&}cVoXhmO#Vd7qpPD9yFnC~{!Q0kz^FuD)ew+v(SV!3VDN$=5K
zLy-a^eTFN2VD=l<UjXxtVaIehbJsADj<O6GeBOlKprPw6+DY9rBvO6WeZvtdn|NS2
zOXQ*9CCcYLG6XtdFhhok^bNwthHr<_dSV!$Xw<M_Ih8$)7>Wl0I%;^T26N1?JOJ0}
zsUhStuEn^ao&`sD8|%EmbT%Gvg`|sdnC{3Pqln(Wj=e@Pt?l<2U$}>Bvfud96?D29
zKiC1{X1tXKP<Nwy7+MF6Z@&%^52J(DjGjgZtvtPqSG_?F8q2aE;%#)M-;<B=A4<mf
z8h@m9yPvV=7nt`qS}DtR$k-PL%mCwC6gdfW7^nOTZjkZ2WM~8%zo9(hVPn}Lj6THJ
zn1fcRG35vbbHuoiUW8%B->7CR+~`L+tO#S(K1fCyhiRsYGQPS8x9O;{oGJ#QjW?Yj
z5@XzJ1Bo??pMb;}7j!@}-uPuWTuU%I3VsIYG2>Cns~<P6q<ffX9I62`$*9L$a`Fk|
z{nY?HX`DbGdpl)Z@(3`=###H&mtyn?!9_f6JW8q6RO9zgfSqO>Yr}ZY7<bTXJk$6w
z6_RBcS5jah+ZdD#g&gChZYZ2Jb~<KaFuBGHgBWO@@y-fx^Nmkv^HN|`1wrGS@mHEC
z3yq=`XcZY>qV;64@iZ-2ON`oRNR}E|N1$G2j9v)ra^pAq&^m8CyBT^HjD=M0bkV3<
z3ZE*B`-4C(8TV6=^0G1MHwVxvjbBnezRI}d9duS3_tNdUVk|F)!5X7!FZ!+;^XMIN
z&G@no%vz(CO1SEbtruXh-ncaheb<c>Xew_oj)&tKHX5f7f!SpIg$lo$jnm1C8%CGw
zAUBOXF+6NBF1|#6Y1V2SrcHdC@f|v$(r$d`7l3vcU-=8IPGcTz$hwUG(el6BxYQke
zJ;pEo|CTcT5do3g#`<K4^csc#0j1B_k%m^kafdG~-7&uN6E6N;V^;<I9WY90H85zj
z)xi8c<NL4DF@gI=1Fc{m7|&4=(?erAB}^X~7j*$<$f#mrOplGNGa&NB=t)VhVdFtM
zKrv#B>xROp(T{?&W5&Nfg^8!eWmHl>ZuF*b_ij^1G`w&&@wWlY#U$B@zC9*Atp@g*
zl(c|#xSDpPLdMP1L$jv4sa*w!516*P!V3=*`!_i3Y5IHynBJy7s;KfYb<%9<Yl@&R
zI~_7rZH7+)Ch<am2AbwqgBfI6p#cdtjZ>!Out`hj#X?LcW@0R%rX>sE%n{QaDwGd%
zm~{6c8g5$sFJvN28<ZH#QB!FYOhlUm`ydlzYRHF)Sks$F(TX$qXTX_w)3$98Id1Z$
z-BP0Ih50~9GVNN4zEh^fJzyrAnrQcsVyd?QI?eP6g^1EkQ$7Y*hAH|uM9!EtZlk4k
zrs;1)bth+;iU%Q+ZF=AhW{&A&D!w{vx<RpvT+`EFz~q@+>AXt5=?-O<3QeI3*ex>U
z1%>U#j%FT3dM}!G)Iz<&ba5|CTrzpKLh`byhK_4in!;#XS7jQb38vb#mg>&0m@<md
zsxh_cae=OyoOobfGcBZWOr7cFO}I_<rif1=a^2KVudxPG!HZ}$ntCV-)MRRT0KI0@
zh=VGkZkV_mp>fkxu@qxzF^MUr)o!}@9n5!_CQ!w9rztcV9(I}h>9^Kx;!>qSkLeE)
zL~fgAQdXhYG>v}MeWnStK<PKVPK${<rcSDFx@(&03)corscsnjpy@k*wC<Ur=Q|*J
z-&Ao8-aIg!i9+k4X`%%(k4!BT_!%;V%|z?5X*<=U44X2Y;M$1k(=PZsYPv_YIb){R
ze87BadO*cM<EDk%ps?Hg_B{CHY##apOc!&;PN?rOM+AWEHLsx3ynW{NFHu^2zqyCr
zyRPOT+99}^Eypk>5A$l8C_K%f3*nQOxv>o}KIS%BI{KO;Ltxj>{2}eI{muO}FCQ|?
z6VM7UTMTFgo7YT$$YJw|n;2+_dGP@HLd{>?gKJ03qY3B>Ggr@{WANeT!2h5TVLm}Q
zj!3gQ5q6`@f{!q!qvoam&xV*6d=1xP%*qMyBG%kOyTds1wC8~qZ|<b>$OQ8r;pjVN
z&Y;sLNoFG@vQL=1Xk&8Hyu}7`$~;vD%w+TVsURulOSeHBY35Td&`38M@&S`!jtRo;
z$}+Eshr`+CFK)w`9P{=!VeqW^XDV*XHNVb=zj@{edb#AAcPxf_f%yv!(9W4-=_AmE
z=1KI!FEXe3qE&1zp+I7Z`Gwt3FE!g~UM(}fc?<T+9p>oQVdA{`pJ3=;FpDV}deJNz
z0<*##vK`o$%n2%>T{b&50j<*f8-?(y%>5mZtTy-4rss;;wHB=!GlMp+wdOZz!ChyL
zyo0gSo8O`^+jaAY^v$aV^F4P+HkxPpVt`F%N9JeHXg2Sl_|XmX9W&5wnqQ*J-C{mk
z0cNY&ZUwW={HP9!?dDYal68l9f;-SU%?g?}y3F5w3(0PCUkzG4=7{rX-7<$)Vi32@
zm9Jpfz2@OQ47<<#_w!KiH_QFdx?}#-kq*(j=7yKx&49U>=D>UAYtNzczS*0KO&*wC
ze*(-y^U4g6M`kf?M~BR+0gUOfnX>{4Pt3XWjE$HR%^;)Z8UI3k%zSe)6rP$tqV&nQ
zc>`s_c3TF&0n^#iGzWTnEFb<yX@R|#@?3Q8vxxV@i~W{9x-_nqqW6Jzz)}~0mWQR$
z3Q12(1}*NqERU${{h&q3!$t76Tzd$EK9=5I^!Zw9HlfeYl0Z>!e~WA<n1?JE=E6dN
zCHe#~11;S5F|r^_QwZ&7f-M@VB|K~?r?YP%mLIO5Gt?6BIW&$~?p}bWVV24-aYw=}
zkI#TaSPlijr%20v7x)xqVe<ic)G}ip)T1qjDXbD>SxWKoSc{k@uQ*FWI#A**WvL(u
zmcwHZIc9mZh{BS`EvY$h@r1?cW1yY1oZJoUQ<mM6&`P#+g`t&Vc{mdyr!DW%!ZF?Q
zum@gbSS%fAow0bIL0_ijIV;R(S(2#iFWa(?4oK%%Mrn<9*0N+Zn7Ni(n&k5=ACiT9
z3sVH9qrfuv7+fs0oTs2gk)`8BfEHVFGvH~7C4U!~rIt7sh?ZHNr9&CzmZ(o*{=B8~
zS&)mCFDZFcVF}BG<R#1WxnN$lxX{-^DlK|C@l<75Ph+XJOr{S{T(O*=4Urm4Aw^}b
zIxO7Z(Y$5}_r)k`ErYi(iaN_rloqJB#FXMfUAMfk0k@*T^20OGZ?xR{3#}&0;e3EL
zThbOl;fCc=AIMEh>oCUKV%bjN-&RXH6~47uCMjX5-7-oQpIw&sXd>^nJf%HSkHzuK
z5}@6-D5$Qa*V0WTpM92FTA1&*d`p{#JC<#fH@R!sx*Y}wEQ_exf6!8$2+(^L&RU4v
zx7_;*>JKb~zeD|@Wy5ZeM;6}^^gXsrdkBRm7DWjz?64*48Ay&;l4&I~YFXr11(~Oo
zu`56ux5TW1!@I2?(1O?5TIU4UT&#ig4Y<A5_?yt*XPp-Xk^R<w+AzCX|E5)ro3(|H
zmb=w@5RwP1dv~GbVckg)BTwrh`mK6dSN6m1LF;vzlDw@v%4YajbJx*A+1ENmdo(}m
zU#lSFZ`Dvp`jB-m9SsYx-k_ITpmjQ}HbSgh>GLF^))_t^N37dvehstgTp<!}oxKt2
z5ms>?)FZ8BYk?VM%??7}QLCo}2BWPVg&0z-wUNG+6=ya4MQMR}>wYSuOR$Fg0MTRC
zq0_kB$E|aZ0VdJvbO|F&vOf1A&`wx4J_r4i*1uz5KG`}fg<gvFo!208+WOKgT<26P
z|1(IYSwHy(VCmMykr2tS=F@4JGgeg!TA9`h&Ophs{<dfWp1*ACZ&WpvYt?=WnLO*}
zGLU@hOH_thU>%{I$T_Pf7>b3~DYR28vi@a-ezBE7vu%mBmX?a8*2HbFTW0;ogrSvN
z<zJ$8-nvBr=nK~WwnO2fb@}g5sIcy#rPC$rjApbPm#xl^(OGE?p%p@v^<~;TS6e?$
z$CbTeRa8R1#`>lLqF1d8Hv{{cHId$9wbo|Z7}Qz0RK{IzO{Hbob?dYNfHhdRFM^|u
z)}N@ns>ynY>dl+2<JEv}vF@ZJ3$51IsK}(vVO=y28tvA3?YQb4)}QX9v(wt`gz<J+
z*X_b}?zUF1g=mj;b29XASsm{|^0xJLT5k7R8T9k$vktBV>9;EXzvi+AG{Np&Yd_Tz
z4Osu21~O><YaC$rtewj+r2E$IJOK8<>WDl7#fR41W`I7jrc8m%kaZso=CO4z?G2w;
zy}2+yY<-WG#v@i|9}H&Hx}XdqV^$R<37%RNkzkHni=Kk)wte~rP@HW|Goj#OTa9UU
z@*dmq-@x2!>!r)J&$fXACi`t4IVha!Zfm9N+yUEv^jh+;4Kl&>w0%zHN?ta75kwE#
zCOwA3-ZrO)7>ti?RXSR}wmy1c`q_T=LCfE^WdtS;*%n^{Gr)G@B@8ss=0mUFAlsx5
zaJhnQx=mmnwk`h~B*gaj2ekeSwJjFosvoiWYeB+nY3soZxA~T!6=C~A4aG>?+lzo5
zWt(e-qepF7d1yu37P>()#<sQ?*CN)o{28?3Y;Tbl@wQ|t(@3z*qdEJSZ5k~@PuMy&
zXq~jJ+69zTwyPh}nY(0LI^_&fY#z%n(9^ahm2f!Kw)!=UDb4oLU0|o%!fVkwV>@Dj
ziA>vYBSx5I>)H+z*|vvE!OXFRcLMvYt#vunb8W>R!eE}wn+)dL;%Es}U{h0y|D0`%
zl1_!T_wjOZOfIt3UPEWG&AtJhWj6gKD3;siZiO@FZTXvEx575m1TQYx&d^HrvTY~*
zx~pyN=V0lI?dT^^sIgT#fKqF_&V@pqZQ49A>uszcC|tJ<RDm?un3ce6v?cdK<fbi<
zjukjsY+IN>YqdqBgS6S~6hLjaU7$PCVbjv$zti@RmV8~db5yI+Z43Szq{lXuK16rR
zrb!0&ZQD93uI{yUXXDED*|zsWq~G@EWso~I!=JEp*S7sDU=G+0e*p`FwjnB4y63P3
z(}L>0Z95%Ze_$Kf1hj{?a91ckvi0r+bI5j;w#$!gL6muaVp};5GHeT{+Q$*w%T$Fh
zYJ2;2m>9Fopv2)*+gm>XW!zTy16sT7IycyLwl7aW%f+5S>8(BXkZEA<wL5&HpzmtG
zLorS_d+iP=y4!g|jN*WOlu{iYcEw_N=xMJQ#s&7W2h+7UXy4ZZrni0N1EBfX|EAEg
zul=3P(DSpep^UD-ea=ddLv|j8eFE%1(5fTQeu)9~Ap5^m8y9TPaL}s%u>A>bI793!
zsE{SpUS)*L5&QPFFc@ZEl7+r-d)pe22z!Y$>_*ztn;{Zq|B6EYNA2}lFcEG4;b)K-
zdjn;_W9<$~PsiC;T*e^c?UA#fe%!8Sqc73^{xqN@+1E~>=kJ7l-cB@6+B@mDe#%}+
zxwjO%g${k6wi{;yCe_|gDVj9<FVPT5w+B%&Gt-{=EJ&99$PaKP+di`q3OV)%ub_3-
zevb*vT>AwoD$TPOQz|##{@p!57uavp<6mrN9j3CB61%n>%~E?r3DC;yuhP=I+&-}i
z8t3ib?g!ch`^h+nT(qC08m0>Sz)6halKll16e{f->DWn?{Wyhhs_jZAIC{nY2d(OA
z>^mvQaLvAE5}39253a%cI{QNl!0PR__$4?dU$@WRk7k42sTUW&(Y`|t(PsN=KSBS7
z-9ahroAxj|hty*4pohBEE?*8yZT4i!%(mONSHY)F`=t<A>azbrWjNjT5GvZ}v6n2u
zAa2<Y(mCtf_Ef4K>b1L{{U1$l0v5&bypKCGy9>K4EbPqe!2*ezPt-&cV>B^QV>HHS
zJYr0|?<>YTF<uyT0XgLq5fo4mkX!CcZah#F5l;{mkV6CnMN||;e{bdc|3428MR!-d
zRoyew(_K|PK;P@_W2FEy_HFNq2haQMbt^%fc2w(u?Xshw6B6z_#D$RX+%b;kZl4|A
zbHEb51DXA}hC6PN?<{49H@TuRc1)rpvpG9fj)P5kJJM*US-9g@1h}LnJN~9E-uWFF
z+faFV$9h+w+}+`{2yLy#9bcY@HQhVfDSP70j%Vj!)c&2%X;135^IbgJe0Lrxg{GrB
zTgkh3Vy6`Y`M90&Cs0b==_-Nxyq$C2LGQVpZv>EwJ9Q(#Qn~XRN)o%ZQ?V8-zPmEj
z&=9h#IsgL{xvO<Fpi_4l7i>gr)~*Zn=yu_*Z3|%3#a)jtp|Nt;7}`<P>^g@%o3v@y
zZOXHMv@1sk)4Fy|*aQ`?c76B-<lgT3N&#b>>}OV>qX+CqxT4bAzJ_K}fBW`IU>>&r
zf+6+x&z&J2Wq*YBVX^jUMj13E+RtbPYqI?ndQ{WwyBxrpX}^u;n=Jd^9zr79K8hmt
zIrbF^5G=5_Ohu{C-s~Z4Dz<+>2}&jQFI~`f#(rfz$XWZsmFVa>`&i0+K5w5uM;1!$
zlPJ&OqW$Mn(X%r9`E8VBecAr<UPzSN7yN+QEB3>-z@`fOFK7dI)n4m_j$X45nF*Hb
z_A&j@cEi4j{3ti=w=Rc;x9#V@0cVx{4steB+q?9D<&OO^^1e3M`_kL2**-o<1_}I}
zWe~Oo1atH_%)4b|+)u!wD(1HZz`w(I(HWb&%v#!2+-K56@YFFIc$6M6rE1_eGo>0-
zb}}#0(V-rOZ9<y^yZ#A?2fJV=Q2g2VNF4r8n`Rb;L<T-eM)9NKzoF@W2hw2d#{+1U
zIY{~6zY+RoD{a=k{p&L{kE!_*=wmY|NH*?Aay5VVmSUIV`+mkqeZPGo;3kZG1&E3F
zC`IOnOO)t6X$z%m|2U4;Et5NV$o`bO5VBLgs{zl{RhDS|*@dR3X+NFC-_sNPFgP=8
z+sT<cbK6-Ie(9zK^Q-|MqF28@q>aGrS{l0F%uYk>_gCbPnUggTpmV>T2he$*HfWvy
zGtCbR!ux=*(Ca7sy(l39{ENHkrdbm9G5D7jQ%c@4y*p}_Up);iE9JpJSQUGc=AYGF
zY6z?u>4WA!Hqe>3wYO=?{j-(a!h6ya@!N%2N@=F9%ruIgyD<X^-JMxM>8Tz}{b}eu
zz>JCjv?p_M5FosmJ>3`!Zzeq&EC(6sQOMOZ3n^Fj3G>HvR6b=s#`I~F_A)bZZ%E%T
zztBR>g*`S5#FgFGL7Lc&MHozX_VZ0p;lXCooq2$L^8zrQ>{oP%z>5vChB4mk&I%|D
zWw{?=#W8kt0!R$IpXQ-hw((OajAJ*@OCX+&nF+82_86UE_%M;JrThF8`+F>~lh`HX
zDM)6AdV?p0?WhkL7RdBBdXrx%oAslV-5hou#YZ!_YVxdPaeq=0Og1;=ZwTgaKR<`Y
z(_D8ODs#E1JHeU9ZKMcnK37IDngZ_J9H10(8&Y9@5jSodP>Q+pl(|&GHBn0S8SaiX
zP|k9xze3;~*KgqWpyxS>CoC@IN``>v0@oM~?2FukzfdaUJ_vdmh)=j}&;jNOH=znD
zD!2vT1N$mBBNwJsa;txZz%@=Y3)t7WHy>iyZg8K{#CMbHPeGwu+}O)dbesEi7BH*0
z_QfF8Tmo_4;aCc>)^Ll)K;SOd-x-|uIG*;{_qnN4p`jMB33{yRxCC<V)^k5n=F<bt
ziEgb1ZWEo?YveAQf;4f<ssPi>#n86+A?I`*r50|g910(Ci)f$L$}ONrv5i~o1@U$+
zkKRv@xg#sk*1@$;f?OvzoW6JTgqybw<S93E&qA<vaaJE=5T0=}DM789lWs=kbMApB
zEPcT(rIe$WTnYI}dbl5=p!XHm9s=ywT+$0D?B(|5qw)=RPy~vDWX4hqrK4m}(BdO-
z*B>8&whYN<jS$F`1XV*IOQL;(%52HaL}<v7c>kA*E!jxVSf%95O(?o1Ib90Q>yrJK
zLGDRZlwNROviJ(jZkC)s1oBWahKE3_WFuu`v`JD2Le5S4f_zNw(!~+5+C$o7q+}m2
z=@fb`drM;}+tdeZ6&T|y9WxUB43jRH4T;lIVIoMbwCyfPo^&ETfBDkor4TQWuA)_2
zp>+Bjs3?*iO#vyE-YACN66tqj?^)@uLtx=KX^#Uc&r2`FLs6;p?sQt?Uy$nWpz)$~
zSts<C;e*=Hdr4X{5WTOJwNSU~WSKvL)XU;RKpx2EeFFIgSvS2r8f7LluuU@8dI&Vj
zz8X%~MK*x4#$L*rFl|fU%gX3eAr2<%vLNng;&KC4IGMyBAa|js$;x}^lb6YPZ`695
z1Pq2TJ|;!9?D8`)498d=G+9B3Uj8QCB`5`$oTvrNVUr8=J`FS(egmZ-lSIl?3^7UF
z1QKep>^>@wndH*@Fw%q}-&Tf6AI;U7CP|w?vP^#Kq*L74CO(-^f7)asef=oUWZ3s;
z%s09AHO8XAWEmYBFErukm{F05oh?ciOb*jp>Y_<3-S}lDdRGWsGRYr<%F8AZEkL<q
zGIIySD@;5lqxV%NRy@qEHVLL>=^c|5Ww5En<cAzw7~?&Yof9E{-{c*wYimumE&)uP
z$sK=SKQOsSKIR6Kh9p!rnM95TOtZ-qa*?%|j8BBXBa=}Vz|v;oNh|ipCPfr$>@bO<
zg+r&wV-Z$3nXX#~>yMbe?}pq_(<)jA2b*3y2=yUGQ;vMwp{BiCX}nA~hXCfdX#xc|
z!%T~sz#48^ODO}9roZ0?c9iKrIstOhR3Kk^w5j4f1Y%9k{sm*=Ox^znlz7vHEhr_J
z{yPnviKerE21=&s0NTf9nSMwa{yC=Oa$(GAQ`Mp(faaR=6pzd^T^sa11P`U0X3G*&
z^=`DCHJwrg!E>hDXfbo%v}Y>>OHH3lLEA;s4>%|+Gab+c&`YL;-=eMDbZ7>^u9)s5
zCvAo4tJNsAnkEK7yv_91S(F}|Rvd-d9i~O(>g_bmDhGLDTDB45U8WYs3lMx}D!UBU
z=cfPC%=E&voSZ%HOdpf)^1Z1^DdZjGnG$e1%5N0F7$^CyWWel~*Q)^IEdOg4OmmT|
zX(n}*PkMniH@S+OTJG}oAE1MN^5w{5mmZYI(h<)?a+mv%3y^P}Pd>yzx%oZ_2FZv0
z2*G6e*Sn!9Mg9f7x6<STbZASL*H9u+hWzz@lrrUi-vh~#FQfNuw*2JJDCNjgsxdOB
z<*$punJfSD3B>c{Ike!&mw#3OQXn5nr!foV3uuR5B;U4){=IOq{N!6ml*s>}1^5|x
za6VlM`99k8os&nCtLwac{YYS!%G*QHc0s<C+^QGlFQ|uQ@+T|6c}d=%ZoSKL=jkBj
z^5GP@uaH;X1j|+VXK&H%N_pc+7<x^f^DWe0mv6*BnlVam$UmpNmYZ@r4Onl<chW6z
zTOQQ_QY}xW6yZDat+bu3ktg>+?_K#%jUe~rY5uVHzI?|AP+uz-$$wlYze{f5dim3I
z$UTs+qZNCD{G)$S*(i52#ieMHXHN%dmT#vM6vl`0BFf-vkx!tt+9P=gtzBB>lYfPZ
zgNmDPVVb`}`6(oV6@xASG(?f~5?u>b%%R=%F~#8?kT6C0XrP5F<|jftLXo)~BvSE(
z8RViA<)$$7q+-NwRK_Tl{sfd*Me+xLjx#FK*MP<=G%Ep`sQAhPjY*2}Yk`)m*g_{;
za}@)cU|OEy_7K=qpiq1W&_adpp8zdYL{<Uxs=|!cJe7(aw70&dkexx7t}6n~(RM?z
z&kk}o6`v*n?3Q8#9XPwKm~jCtRSM&`QP5khXr(P+gW~L6kVeI9TB|iF9!*54S#g)b
zgAWxOXzFiK#FH!Xks|OW%x+cebpdv}B6~K}KUR1M!0u2C9SlvFaRUJTL{VFUzC2af
z(b2Rn#Sl75@Jw-KJW#q7IYv4K_grD)2kaM$M_0hpqj00J<ST^-C8WGoJpKr!UPTLe
z8{a54EdhC}IF<wXKE(^#t-Vv2uSe;<;wG)z9n5;oV49;@=qDgfW<j(;*l+gRYLuMK
zcGGt&UCjDLVVqpehQyE$!_90~1k68R_K+^Dr<o0{6THmKXtm;F)<yaLzGl%XnC53T
zECiJY&3>hQx4&6AJx+(r>ZYL-V0MxYU>!5NN*;paX71#i4Kr&$1`=*|kml70vrCOA
zMVh(MwU09Em_-R;56pgRfcZUUfu8}*K^eOYtd7c<Fer3V4oD>Pm9Lt>;;dYD7KXYg
zAN~v&59PPCaXO$ZSqKX~m5UYw)JwU?8Js@K#pXcqRd$X*M-M71l|b=VvPZxYs9Zs(
ztAdnyU(p)=h|*y_%s;AB(6kkz3|Ii{P$ftH$z#fC<ZwH#%>5D);mS3%@;agHrWDi&
zrFJ|(BbCcvLj6hQrqQU3R(k&nmKfzPV*nPb?D-rdO=&`(A4yjRpN0AiWi+|sGnI4c
zH8wFz`KdJovz76)z?!2R)CH2O+(A!zo^l7p^$L~y$3w7K**6WGCCbkA(0fg3Pg&R3
zmA8UsMPTvVe;ed(EBnZbD&@D)5U5w)p{4W#<)`gvYfv`r1ZJc1sVU@|l_AT~vsUHc
zDv&m%>0NNPE3=ZI@3HcsKUkh9b>z%?s=Q7K=v_)>e~joe<*|XV{-rW`HAs)r%mkdT
zl!eC2Q1MzhvJ9s6D$gZD(;MX~b6D|K+4KZ$eai9ljCh;xrFfH%c^P>*ea*+b0r4|G
zHUX6f&4<;2_?v&854l6;7p_2kfcYtU3=W&m;Q<|J{%{Dug3JdOL+*(AVY)4jnt$`(
zCkleiucm@E#JpxYSVPUzcfq#f=8qqOHO#!FA4s@)4CSSqFh4;1uL$$pv*3(0@1?gx
zl=;(JAkpUGl^BE=a}_-lvE~Q&0VU47PKU|_^R2&PxDw3=&|>G5`7@f)lFZo&^ofvU
z^Sx(Kn_|9-@^Dkl<0yeP&HOo?qDeQu_zHS6%roc+QI`3UXb^Xc2_+yN7X9ad^MFO%
z|6r59#lv0D8*FjqOX`coZ<LiDYO&cHh90xnJQ@OF7L`sgG~8l)FDg%1EWApeD2TB5
zjRFdh7E>aiKFVT_3gnc<m$cT(w6Na}l4bFI1SGO8=F$h5ax7%zlDllNg<O#37XIU5
z=oO1Kv~av-;Z85Z+ZMmwg4tCT*9U=ATP%N$$~zWi0$6G+M9QkUYjN!eEHvJ;7}pBW
z`xbpeprY0y^ad_ookjClSW#~={x7gTuqd7d^BXMOSAaBGj3KvKv&B;i%RjWR$puV{
z#hrJkd}Q&>Q3yP<s7MA%w?$A5+MZjCp`&y!EOPrG@Y14q8cIDD&nd6umC>S?9=z8U
zpBqryYjN@v1m9R({{oe7EjE)opwGg^2-DtKxc8#upxX2vZH}t&wIEKa7K$40SN%vi
zh|a1FV*u)+l6?g$TvfX_qvWPa-2_f|m4XtKJyheXA#gx7dl@P{RmOklGdy0ZVHcs^
zTlFcW4f?45p%A#Q$}0qweyVI5(u1nuFVN<%(uAY(kSZ$%qjp#|az5GuRbOoe2~ue&
z6ZweBhF*V1RXG#`3szmO#>j-Ij=n-ERP~n5N*z;`QdaqK)kGu3vcgr~lr?-pwVh67
zMW|Mj+ayx;!FjYrsg_Jd+eww@mk^9rJ*xnTQDwwHMVzW@0y-0~Qfk4HplbaQgOI37
zq&UVYRaZ1nl2ncVy^>Y=v}Z_B9SH|!s;ZfSnrSNQ%`~#<s+J+B%~1VahdyPg=5&EI
zTh&XRmK@bxdw`x+{Y=63T-B^0P@kuIz8doRs+Tmq7N{Pafia~j=Wc*qP__RKfs3lO
zmoZLds$sMky{?jagXM<Gnz9jYs;ZZv@|LP0i+oYHRd4;EsY-RB7<#K!r)eg=qsq*N
zM2)In8qn^lJSZFJp30iGkM~u4C@O1JuH*!&Q}xj*v|hEF@_!zvLMe}?QFUb_Dw|X*
zcf;&vmE}9MJyfl6fk2CDhy_?4sh*_K=Bibt_XTU4>Nt6b+EtV3HhHWH9S?~PRWE(l
zqEmI?15`dyJ>Cz&r>YY*Fs552Bj??7RZ|(-UZ@IaPI#%hPAl>r)z>ayd8L|1OT^cz
z!_FABUe)X<2sm1X+oRISvON&pHSV`;p}4xU<;BhDldI)DKcKl;Hq@ZxZfT&UlZR#C
zI=W{qFFK&j)3PNPf?k$mKSrguWz0I1d@N_t5iwuO<9ndV&vIoX$U)1a)1fKWYK0P=
zh_|wn0W;C6BM)*(R_knGOv+p<g*{ZHS$XF|BExD#2Y9lqu6_<pxmJl3RK0EWDjV_*
zRv%JQd85_XlPEP=35!u`wo3gS;t#DH212~Ws+Zm_T~=K|!{V3$MiVs#;f+<pJ!pDs
zrBQ&T&+5x$RKBxnrwpU_Rtu6K;GmvHx2&VOiZGqjwUptoUp-?g1iaL{4?&-|y6YRD
zgs7iUE<~u>;}CjwTs@gW&|&IXO<)OE*N#Q$gjzQkoRR9G#&4*j>e-c$NLCL$3B9M)
z@hKp=>ao8;VV?SvFTiqM{VlEbOVu9)&<(7vZiM_rwVW1{Wom13+Fw%pBtY)6dJ07h
z%hkj7qVkG*{2$O;p_VQHxvEZhhRRCy7+S<$Q`?NA9mrjE)-SO1o?1!1mHX<?{(`1j
z^?pZ4)Ts}6p;WI{(&?xN>M<KZ8q}v4kVdslH{_bs&TrADX7#*>C_PjUc7=s4>Jkma
zAE})v?$WCEdJ9Eu>b5(OYgf1agwkX6y)WqVA06t!-$1@o{ryk4J)WrlFoWPzb(lW{
zyVO>5(WhtXAMe4mZgn^L6rZc-{{om7>X-Dwe5qc(4i@&P&t3=1EA=OpXnU>x<2E>Z
z)kbm+zENKxKlEGmE((G5sr&DNdIz50ivKMjb>tVk#+W$qNfb!m&wnxitj_$e*T8d_
z&o2XZApgbBz&^t77zwnad@LQ<2;~zkA$N>7rFY_Se)8|IH;fne!1{1rSBcUIz8}3f
zBKRTEbhY`Z<iCjGKc=LOll=Ti7$;*iZ~H&U$MD}Df!<jDKpSe~_*_~d#`BGou#mw2
zL-_-Ve7qjy6d&LK6-m4crHm%?@@#OX@S7#TPUV9*prr9zD7`<OzwsAJ8T=QHK*{9m
zCZU5_{7u@*X7eX#X_#Z=?`MGZH1GQnYIFI#RFv}gC6rc{&sR`tQUSk(7NdpyW_w5!
z@p~xdUCi%UfVL8TDaB9D@Ks09iL?AaMG!y7&!Fti^Lzk#Z%X+J^4wkE%Z5VyBLAM=
z`epoQ<UYB?8)cLucbT6QfMPjs#h~#Df4c?}6}+4RMOXPN&S0tJP3ir0jn7wt^E$uv
zYp~ql%jto=$@kSl{Vo1q(tDe~L}$mV_>ZJuspdbY;QSr_%HJS0d^05?-{sE-po91L
zMaB<Nyw7Kag0+_SOa`gre>#sI*7NIWlk$KM)d94D-$VyR8hIT#rkeOowlJ-kkF-GB
zL%#icC~V<>r(Mw_zO@3Ct^7th_SwdFrlU*kya)M!9`kGBVQ2?$Is=uR{D3Ruqj<vS
z-i9?#`809_bn&fp4W99*DR$P)w}>b`=bub~iWmGxv!M4S{{dat9{xMh^ol=B$39;3
z4?IA6`CNLNz2Wb#1m|0R>~9e7<3|;O^Bq4b0o{GiCxt=WL9iZ4dn8BUr&*|V5)yo%
ze!nn{0tU{4!z`3sgg8p~brn*LD7gvdl#1al7;gg9Lx?VeO$UUzwD$KD{-UD;Uc%%W
zXz~_h6oB^;I$XfwE3`VI%}=nn2}K8mJ#k?17hZ3nJ<=he%M=C&2t)rnl_hli0TqEl
zVJswqgyob%azt3}1#(m<_rP!k3$wf+A0qrg(Vb9X!0*s>On9FJx#PluK(K@f`{qGY
zxUjAgeK{daqw_5hLe@VpCQ{g~h4oRws}QglPYUlnFi_FL#5oX*5p3v+#0tsBfEFi|
z(uyKpX#E;234%>LNTM)g704;!Q!T7W60QycXtMCjbErrWN>-sVRhao0ENQ~u*U*+O
zSd2vnGlZKCP?#zFLT{Wbp@RoYwo&k-k1ym1hcqCkg=k92$Q9~ogz|*HL!driu(wC4
zKv0f@M4>Qv8A?S$?HZ6`A$S=CN`#+Qf%A;;W(3CRtkAg}n$8L9dZG8cVA+FGsZd~q
zzy+a}l36bbasx=2V4U#}=q2HMijiFw4B;5dav?DV5?6%LaR99l^7o-@SB1KGpj8Up
zu_#>=di3bUbzv&4x^D=HgJ9ZCVg4(qza?~1NcXmIZYxNYFuW9C)j}gpLU)8SB~Vl&
zockPYcZE&H_kg)4IJQC4ePL22NUdPw22FKB_9c*dA=CsC4+OW#C^ZOMC?l#-7<(A<
zO~Q0?Co~KF-lOzTC?RKNi!kXZFdqrod1z}DE)0WQn=pZ5W9@>=U4T6nN@-u+A$-<h
zgkY!e{e5)%iSUG6^-l$#?YOVHgi-U+wP%7KIVHP=jkG{`E{u)`%nM<CEyznD{vX)e
zBRHrb@JjfBwoI>uGjw0|3a4pKcq8PD1?O8KZ!IeOgdAJwdncs0gS;1BrBa@ugXp0I
zjHCFg6bhZhoNS=&7bg|MZf9|h6s#_yoi|uqMaNLIxrvWxq3kZkKLoai_>^wz1L6f1
z;-2CL7G3iaOUOy!EiU{HC_ZA88tQ$;p_HNECwdxDc~HzWCm*4|ICu~w4vBX&z!M+_
zldIyesHedX6latBB}n}ICCCwRGkwwFsQ6tqj0qM;oCjx!_@Wjg6Dl4&fVN{|1vxxU
ziOF=xCrSK{oGHoTI9eB_h=Jt$O%<P!qb5y!OQBO^y7<uy=*<u}(K;|wJV9^6EU|0{
zEX@{63Se4}h$T244pDy+dUM4=lme0`#+Cv!U%X!gxdL%|Hv|gB8RRi663qpWV$s_P
z0wrRA7MN$m_ZeV0D?UAp(m8R_4V2CsMOR93Efs@l*?d8~MLU>_;sl!P%fx>vQTLMA
zIS?u?i*H{8tz2C3D+I5IuNMKPLTva2ny!lT$=OvYj-<EQHPK=POuH^#q%FV=k)=e+
zn<Bdrif)M=bVY89lQRKbB^r;?PO)0NPJ6UF;#*p3)`$Zl!FpG$IfHKB6B{_N-WRRt
zR8p<z#DTL;^rX;dz3AWu@<4PWcVL6~Bi$a2;{TSxv?j4~E5Mq?tzU!Xq4?!elv>1d
zSJ1OZ;+)?B)+(ABX`*QpYsoFqF7|%~!N+2n6%=-eAHD+V6wgtv_7l-P2P{v;jUS><
zUE;JI0DUI@M*i?_@oP`$eJ*Y}hSCesIRmAa;%Cbs*CTGG^t)GL^>C<vEzYG}g<jF0
z#UQ*9LnhMt^Q~zA0eJevCA7YOC;s*cG`$y9zA(l?Q?dkIbJPUqqU5AGM61gEn%BFa
z$yt+2t3nseA9Oy(Rg*do*lwCWT3)$pq8p*YLsLXCy#tyfG(&i5nleDVG?sJ&duxj4
zQJ$fXCW~G&zM49U?fGdwrU~w#X5>qh{56sVKs%%fq(FOs#-bOMhc(*|!KOfsk#;FT
z8fzU&M>K!Y(YK=-^>B0|SaXt6&O$Vi3@i-QRNVvTF-><WY&x!4y$&p4n&jVcayToK
zu`<5!hLMq)E=OpN()iK#>ZC?SnS0TiF<~ghXl`#qTdd~KKL8u28E6Mx@tO*EkOWO`
zHaHVCg;C%<rTM}aU`d*fXx)&k*?t!Wq-ai2^fOiS+ZY&-rs<gqfpkr~Em$%%zZ>Zh
z$kdd4g4!(247$&<H4Vk6%+cJu48hYHA78NMYCa|xe4gefO83au{Ez1H0*#VRoD^!>
zlORx}@uF>Pv1SUnH%c^5=yo}y(bH3MR^uCp(m74K6*$jpTxF;%)ja#!2+#|f|M{V7
z7d3|nyG-K}g^|9bnMt9J%bIP?Xe-y0(M#uwhNpORg{D7w1g>hdbVpZeyq=@&nx>F0
z+jY$+Bcc9=#(D<GP0i9J&~Quh`Dn=9)})dbs!Fq53S+7@>Fa2Ne@C;QmMArv5wr`q
ztNCF#Snp|iw?Y2CW)Y2StwuctD(W<=7zoyDoCm?C2bxL>c{gZAJcZefn(^DwwI<EJ
zTBvB&q>l!9sIl?~ON%D<1T;L-c+$+=s#)O*(xz!bcAHV!uKD8ucpht}(e|N3v+O+7
zcWP|N75+q%-HFmuP0~S>x-_v<0s2hiPwS3u&2ZW`Ki3q|LA4i}Ar!EGsfkL4**%)$
zRVcmEWICbrS`#jV^}U+U=m6sz&FlU^d8-Nh3@pYz&9yJU^G?$e1oB?P{0bfit%ie%
zj@kvZQgPCn=~3FRo!EvpXKlv!uqi<6PJ7hD+Ob7w3)CK@9O@vg_%Q^IXopTh+fnWP
z7a$?pXg>&qYD1#Ha!k95{E^4Ct3QDHFrzl95_-e6Ra;Ozp<SSZe1x`!l4>Hg3wOir
zDD4A^iJsJsP(UzRYf7He8121JKw`Cn4uQmJCqzLYUOQnhI1{uvmbgrb+G_I1ozkxQ
z4C<4#XLg`6McXnT0;$^B8$i;u#+-V9rfc<ddu3=#XsM8?oj`urEbX7Iuqj*Xq{DdS
zXwT}wd0JaO4EE+~D=5h|Puq{uj`Ou24}jhRt(?N2h1zpppsh%YBQ<y&wBOKvu0(5i
z2$nP2OsYJqjq!nobJ|5lI;(YFdyY=Ymuektq5gt4;tn)j)E==1Oqte(e5{wW_8sWV
zWo-(5`lDR?b~iw;XzhQ1`U-6gslTfAr0r;>c3J?)HSLrzR9@G9OF5%Av?84byQyWu
zL2hY-=$z<nZ9yF^f~vGlKZ3PdTT0=ZJ6Z{C#%r|tHjum8pD4O_PkZ=V*mPgZ(}J*8
zt0hl<opu8qfvDGxJO$7P+EXK7Q-hZO0i;nIu^D}7()M?RG0j?g+Iv0JcHM(Oi}s@o
zR6f$)o=#4HR&8hs(Au=WsGzA`TR#(4Jl0xF0O`>FTn)5N?RA=jpJ*%0A^%kStq9Vk
z{jdlYKGRO14PCd^;uk1<uHEN~0eYbw5e=}H+Vhll+@tlefrYQM!<5kbS}V{hu~$22
z7dZjmXs=p>=dJe3kAT*vy-i0g-)Yyrfc$&y|LE>?(3#L_Xh+?$Pf)^FXK5k2U)N-b
zlCy3cWdpkC3drl=sw<^La5vo<2UNQ2?orZ(hi<boFc0W#3DZ;eio#o7I{h6~8ohPb
z>|vCT&YWK0zPj0zgW;zur!yu8bv5Ly@z;%836?{;>I$?4=$4X~|FABbl0^b_bI8IV
zT{O8akLWx{L*S_H?kI={>vB^uh9SDOcIaTJj-hj#$8^;;06VT*KzCr6QTL3pf5LTh
zufduVx)CbCMCgJtAsDIq<vdDJx=;%AoYdW&ic+-h$q&Ge(OJ;J^jMvaCX+bbi?v{h
z*D<jGOVBMPhgG8P6upN|>H2Mey-B(=&%lzb<0$bgMVG${EU7x<F$<WHrkmaXv~*n(
zou13kt)*EnQx~}q@>#miDYBHUv)zfx9Nnf{D4o_lqu6t<F2xz6o~PS<8FKl$rISGl
zbiLc4uuzvp!Hpu_Psy;bSa<6rDob=dp-^;2=X?TS=XDvzbQDW<cYX%zMcuIRP*|qR
zm;>7`=|&eo@UqVLEbK1Vr4L2h72O89Eh}`swA#C>tKA8fN}W6q;@5Ot4&c15E2pUZ
z4IS@-wwt<><QKW6>;D7ny{%hKevvBOqq#t-*4e$F?4dh4J`2~rMz_)row=)f`yF`h
z>*VwSpjzF5K4_}bh4jJTdL1_nr3X5%)4*=f*}DR!Q8(lgI?<$SpiJy$-8=GuKh(t>
zfH5t)-IP7_NcRQBpjvg)XdT<8Yaa&jc3tjfN>q5P>rO*$hc06wSUYv)w2pqFYnFlM
zsji(i`p<M*=?p`+?gTCRp6hNu19_n{{RVO`b!*5C+oS7O3434ZR?>xet?QvJNw4m6
zCzRgk`cZEETix@kDD~+!(aPwZZhj3p0p9DZ--FdbKkpfO;iy;An$<}k*95X(zi=t6
zaMqVyhJ=e=q^vzxy&2`*yXh^8z~ZiVr76in?=cD}2lT$asPxqT`v_y<rT-=f0^a&e
zdhUJn3$CNhSO2^k!|bQe&xM@vpgz45wf_16w9YuB|9BWo4A76JrR!n+@Y}FEP+!SH
zeUN_Ak5F+$KlUt2NA+LPwF}nonhp}8-})5dq51&2*^cSAPK1i%dcXBhAErOjgHpJD
z4`q3r(6641QiQ&76x2t~)jybmVwB#6lK)QXCsLoH_3@M!9HXDdVt`}yb)nE3r+@wx
zO7Z%F3XlZ7M-Mb5>ig3Q>Xd%22}qK@R*JS{eQ%Jwm@%y1_#F(*(6@XAuuT1KI^mtA
z|CJ&D+4`CEIOOO9=?v^?{VoTn&DB>1pf7p)qgg=7*V{%yLxDcX0J%cFl1E>P^gI7W
zWwHLQ5A>DjKe_<uGkVh?pJHZ!@mE>~UerH#Ls!c5{bK-qNk7~diZ1JC6+lC|{>zyt
zUC~GE21|wh!&HD>)z654T&2Fi1_IagpB{tu>w4WDK;O_GrJ47pe!T=n+|qZEkL9-B
z(g~bZ`k#J6TeW@<WgXwqzcuy%v_|h#4xYRE<zrF0r+1kS*8BQ8iW%4HQ^{3Yr(a<U
z!Fv6-bd?_H9X<nRgMM5GDjW5ODQwcD|9&9UH|zf$gnoAElX79xGkqjE>AUp{DTec0
zzkMCZ3;mp*A@EW^ZZf%#dh}9SKEBd#pbgw>eMJ>Yz4~xUN`Ir@O1YJ9^#{{oaGySl
zwpH)+Ya;=3$~s&Q&LnGFx+_zxg-_9mH0ypQXiK+F41^UK)@^yH%(Q;&g~}{z;Tptq
ztXpVRm1}(`ksJzn)|>tYPl2^;H_!^L2T~NW$ojgRE}Av}09KS(AKe7BGu9*CgPgT)
zrl`+3>#KBgp0~~)4e<-srr~rYtxJ<&Oqun+W?;E&z5QDVlv{^Yg7b>?*8@;lVQm}<
zfveU-;Q}{GE3L<p&*PePH07pUw{9a>=?&}Ev~0a;Z5j*KTh<#(QMzq?TL-(Vtk+P$
zquSc^1S;=X$IxE5#yaRcRNS>5N+WyEI(RcWao<|<7dUIJzaVdFops(^RMuNx6Jb-c
z^-WJ0YJ6m!avw0Q)|;%r+GagF7wX%s|0SROW9tdD&h4<CqQRx?v>xLFi6_>o1>o$m
zp57m5&#blNoawe+JqF~tb^I$-zOY`B4wjeJ+BdMb$NFRXBEl={t4?%zt@l&jS+8|{
z3aofzwBGH5;#=$07onohdLtz<ytDq3N9B9#3Eu(6!Jwr4F-Jp;0c}o(kLj4|e#777
z2XQt$r+1=@p|=Yxu7=Z_0qSP>oL;x?hH#3ic^Jy*6GR6LL$5=Fr-40$N-x6_3V?YV
zjQeQi<YQ<%0(oD9brl5t4DDM1>TlRWNs5OIpUs9ufT4t91&0kQmqSIMA*L2LOOWC0
z0k9k~?4@_aQNzZY&=hQFSO&}x!$3-^3^iCSf!r~}m*l!TZipC($}q#L55XC3V2t#F
zK4Gw;yCuR9au?W92G=Nz*Ga?V-_hS_!*^Op#2A+Uh9QYH{22$+;tjr!AeU$`r`h9_
zp_ejjk_`>ZK~fBRC?J(;SeOmHX@=AEsH7YE({bDkL*or-$TD1h2F`4Q+Zysy=NRlQ
z(0JM~;sC73HB4R!&^$ww5BijEcs>#^1%{s}k+IOwOwV?a!R|IHiw&o&QCVW}qj>Te
z!@Fq!J8S4Z3`5Tuh8#uZdBZgNc2}w4D%}?s4Ergm<)UFVt$fN1wN|v3ylgOk2cB}n
zaBoOlG4$tPTZQ2U`6{m(hLZQW(lA%RAY3yHyM@YL!?+lrx!J5DXS;{ZZE{i`u-WT?
zwji4%TKWguY$Lz=F`KRAd=9tS^D)FDZ92w*GuCGJDOASUblsp2XT;mgroBpn%`zD@
zCE5&i1kWj(wLig%B%8hT5>2*oT}mTsGo%PGsWt{$nx@&@{V$cs#)Kjz88)XW|0~nx
z&}UGeZDX<kayd2~G@+icacqXdvo`sZ>v7d)Fde0-wApzdoW^T5X3L@Xy3JEsB;Bwv
zT@GVz+MJq>uHCXZNGTY%ZEnzuuFA#`2l;B76H6g@$7V(ejH$8tlwj`KIBWvwJ)5>q
zAa~zp{zJ&s+SEj#vd-pJf5_F_jGYXd9@y;5L|cQ+;41X9$!If+4g@vZT*w33e%l9+
zQ0r`aeJDU(Y)5Q{psTHnj>Cl7CQO6iG24UjC>^)$evVR@Z5esJ!fn$iwdREF%|Q^4
zwC!p|Wt43vy+@*Lt4n~AY&*aj8d7YBJVSR=ZD*>`mS$`0*o*6wZu=d17cy+el%kYr
zyLcun&9bd0msXLjiX!gCwpX0dR${xx7UZ(+E4mcrw#(;&T(Nbb_+f=@FeNTm+76?{
zqU*NzEx>uh)|MvCTH9mv+}GKr(AK-&_J0%rcwqZmQ2&d_*t+&R^u4rQI|*$)wgq?4
ziC4BZ8*o8h+h);x{Kj_Ybg;a&{b4`a`fOdzQF>>4crUa&*bO50g`?f|QgAxiWlV+I
z{dPw^(B^DsaRQYtb~EbGT~|AP2@G_%+eEqU9(L{3AP4MZMmitrX~$7syO-V1cOc<y
z_th+D^0D(Di;}P17Fv`Yw3|X7zw)=s%t6~BJNxy}8(>#@6LN>`5PQMIWH)IjID_mQ
z?9jm@cCS{TE!gfG9eNgGS2q&^$L#)%K-+OUExDPa?G*q0Q>Pfaz4M?c&Mu7ZfOtEh
zKS-ioHl?8?*~QbYKH2Vd7Fbg3=Fw^))$TGm*V61ZTL3iOZg3zfGwfn=U}2`+#qZFT
zWj7!fB-?JpN`U3qRjk7xoVMFxg~~j;j(pg3&hD{DU(Y#j7fKP%Qaiy8=3lVuqImK}
zyOVSfq|DBhZiGvAPP9@hxBFlbV6NCD9!Fb+T~7(xZrc^p*AA-e?$NHI&Ta`MS=8H&
z`2eOpuq*f;W;fV5)?q9f?at9+xyf#A1H_x{lE%{{@X&7X-+*bcbBcxfM|Ms;<Xi0)
z&p>6HUDs%kcDuDTkbi9VbQi4f`(VdY7OL<wXy0~d8Js~6?kAfL!?yiQG(8T^%%=$;
zF3h)8bn%&R%5!yNTKA&l&iru{vL1{l-Z4fTdz$bMbl}+2Oi4dk2(yb8=9$dzkuWuj
zIYT@6Y-S*ZbaI$`bl03_iYS3HmsvykRC!FnzhKE{5=%h}m{b;Wg-joPP_KyTT!HQv
zGjW9wC}9dd1<M)6{s2m6nRRh!GoE8Upt#s&X3Cm={bVgn8qLqn?4nduy0CSW_3FxY
z)6ohyHkr;gxU*|=Q1W2^o{fPzz((FeM?Kj$|Dw{1HJb<lZ#F#{oIdQ_#X#|8cblV2
ze(ZOY^>dKT4~7-~Yzq8CvM?i?j=+WNCVK>XXPGN!Pgx$G+$n^$We2&#lYt$`&7i14
z2zSRy0dV|$(?|)9V-jxxeO$0Fc)m-C2KM)^8GxR%aTt^@YHxyhYd2GB;f^(Q6WaG2
zK#e=obOA%-$(*Hc!(|&8e_9)yVIl_nf7ev7v_tzlF8X6Aeb0Su27??Vy~n5vk}Vd1
zJ}6oGFG?p&PST;42$K#9FhrV|P-0q?N&f{9uUCC^11v2n>nG6PshTtfZ7)=sa&W#?
z-5HD0e#>IGgMt#v8J#h24eFyUlPOCh#xiFhRK{B7Qdl|8lBY;+yrro(N(q)1)}Wt>
zmPYb5pR&wy1A3C>GfFN_w#+<;k;t&TzY3grmfyO9oUuGO1z=^Ce&oNaw0tug;&&{I
z-T<@4@=O9y?po#<FM{=+<@Ekgf8VlcF-WIn)X!jjV!7cGN>43&$s5>Z8SaVFGt0hH
zP}ps`{u7MGbIS`~LhlPpf67dKY3W9z++(?PCs<xv4hx0)Udxpm!1Bg2opQ?FT6&VN
zxzF+uIf>s{T0f$d$a~Au0l;>!+DfZ-N2@awe|NGv;enEyRrgnbakpxsardwqxF3QC
zth!$U#?vaOA4&(UCbfb1TaBh!?~qkhB`!^X)xU|*d)P`^2e2qBZ4wQvl`p-#<E<W6
zLLk*@&|BIGWLUl2fF9;q)whH7p4C4i(Rkk~m_X~Sh8+i~w{lno(rDH8H@e+q6>0-b
zudQ~p<34dvj}@TMOU={T-CG?}19DWooq`YH>U(2hc8vNC1t^o$;cXDlRR6dIit^Q)
zf2AXoXVuRr0C!1!#0HJm)ZY&WYqh#RMLX)$Us3w>Lv=sOcIZ%#Ukts^)fJvF=8d{H
zlE#VObP2?Rx1ylY0e&PoIy`wFa;bRnf8t@1dh@oa5b)vm(W}ar|9m+H-H+dO4JG42
z-kcI3{dr5u<UPdaQ%oR$e^2SihxzG)AQ;I1JOyY$eAyKU9^r3YLS+;`gdXja{Md64
zh~`tSQb+lZ=uAT_|0lTt;`mGTK#AvD*1-A%Ua19VB0n+?<P@Js>yjiRzuOuT$$Z8!
zbS;IyMLwWZ{$tuZr}5uX230ygsTT?}`BHyyX7O9@Lol2F{44}=_(!yjI?c~>2g&7M
zRYPGOf4!6jnD?TN7VrTRfl|o-N&Cej-f1=DiuuZq!CAr^>kmWI8Gd6qYR~e2d;-C9
zyn@oID*2h==u;J6zX#a0yyygpW?tJL7Cz?p{S54Geh(e+d&Bpi0_?Z^x?AAv<2558
z{*EswMB96QIBk9%gimOx<t2ofg2h|Nj{>xhkYXGK9$(?FQvmf7ygo$ZLE$Hw-3|#~
zuYpYg!ZL559TpByCRCu1@G}I1gftVBjtCz;068K2LP<OkLVh?(k-~NQf<u%r??+Ug
z6h6KKlxX47F<22J^tGcDD@=b6&UnE+j65?5LS;PkCJLuUVW3V4dngerNyuM;kx3Tz
zw1PE7So{}Ast|k*pt*vmM1S*y#0H2L3W0RKqevJ@<dWbq8z`5BY1hGdMfh_p<SK-<
z!%(Ucf_q_owa|}@sS%dN(MQ4W3RU!|HVLowKx-E2Y036bz`-=kq5{_m(;f*Y51~)3
zf-AW*+JvSHAnn3hn)x3KmGp-05bkV-K&SA72{b(sj*o>EPlY3qD0K;&nxXfZuy-F&
zx`oBhVABiX_&iG6ekqJp;~Mk`UyO(RE1~pvkk>-MN9bX%@cR>3`bJnt6UJNNlYgM8
zPuO`LXzzrkIH-6pxYFv^LEJbOa*kqkI9Qy-lmcMx7the0>n!?~pv_xMwnL?lIKCeQ
zd_@ffa_9MpjsF16UmUxFF1qOY61D}1%Rhvrhs7!Xz={a5avwBBimt>GC5|ga>7+Qj
z1Dw&~gg}7Ch#})qiWNtN0W?l@4pQA<4B9g{p*Km?HN%Qzv1=LRQp8UO1WmYs|LGn6
z5E7Z<4SHo}i7sI%Ws82aGtCj_5$kF3GkVMAiucLGm?xgPg0_6oj{>3vqD44ND-@?v
zc1Mvolde{=IQB=VFA?8-hRQQy%?A*;D&|uVp;GMn3vJiM74eX}A^v0h7`3;>9uYiM
z;zw^#>JUvMFczJnVhG3^afu_^-ik9RccM?!{t6ZE#H+JV`CeS)2muF8kN`s+H6Ja4
z^-db!X6W6oc})IbXU$f7D0I=dkQ>icqx~IiZkjbi0Oqdg8BFON9-4Z0$RE)39Ye`W
zGn*DP-kL{pRQhO?3n1vL`F9qu{WOn;qV1q2?L4skH504Rc1ZIfxr+ic_7rJ9tkKiz
zJ5ZBw2&EuRk`pkGXnKnwepE98OFTrpd0H!lXhsLnogb_Dffht@nnF5v7q5B00Hp+t
zYA>!xqUJHZI8SL-4TpTPW_=#?rf8a8piilqTl>)aG|jdvup(U}p&Z%_&4sHV;ltu6
zM=Nbu{caeOKI}+2P~1NYnhy=tpL@xn;lby-OKADqH}VQO65fp*6pdQ{QQovoIWlS#
z%|%B?Wmo|_WK?ky&@x74H9-BjQPU{7^8Bc|Gr&?l>T7z8TSjTWhfT3xe_m+@OYyV*
zUqAfbu&WW^8;dE3v1zFptl0cbD}L`VxdGvw8;pLy-}U+$WE~j)FM;dGEV_r16Z362
zI1VuV`vb<4F<yZM-pm79R~}|IP*zVMQ%B#YIL^3)0VIrx?V+ACmh_g5Wpw1Oi(^75
z87ZEbyc|Q7!1VtLnCZ*}I>?>Dl-QFGBA*FdjbZ`w5k10%%(`j_7BMp@o1u)^M6u&b
zO!ysuUS>wpH?GQ=31`rDn>qX`(5jem<aDfN2GPss4s-edDjzV@D8kafBu@ruWE#&y
zyom`Njt(|6U6eomkjX^=%_wbQ<~5`75##s{dRv+17&LY<md~N$86&6Xx|<nGKAY!E
zNh;)DFdmc^*T;B`gTOmx&r}T1d*+*XSmD4<q<5|(d;A6}omjiOfZor({SBPX>{3E;
zVN+?><jVTfCe!G~PCgDEcXrHNV0*ClD52~C`y0)ep6tAz!0N>wr--39+d&adANKs`
zAinI~01!X+B~51sSqrN4XIWYf9AZOxfCaESDM9!!+a?7|AUl|%`9bVA>(F+D9X%Hs
zj{c7wJpq;mvsnUoLfE`RFe;RtOJ}o=u{N)v_c$9G^t1{)b;n?spTfR41(sAc>^acV
zSWOfvbJ;DesLW#{$oY`Z9{2%Z1?>AZ&{W8NOX&)wY|JvWU0@IRfb$|7Ounfy_KWQh
zzr^OxgfW-dgzXS0XJzD`yvv?zhul53hSpN|*(Js$5UgdtCYSmHc4a#Ro7ltOL86%*
z;R*SN>>kS8X<^&QY50i!atwOb$|h}vrZ%?60&VT=zUydn;9_<`z>V8Sr>T6noDZS!
zFy}fEm7!c$AM{3YF)N`VfiwREm5H4CBu!PPxPLx|6-nG_+7Bjkzix*yDcq2AFfpGS
zSqBvb+`?WcEaWB*fN4eC**jn<=FI<d*Kr0bs6WdI!y#~v8&3{~^IUBXNGUg+_Rkl%
zjT-=ck^ABf#BXw8S7F6nZs3P>aK3?Sr^6MkT;M;beaf{{IHQNlBk$Qe?%Vm0aFzV*
z3-jG1?`d)2E|L6*l7~b>C(sW_#?cnrQ{qW3DlbXw6qJrgM$*?_j!I6`Oc5+;pf4eW
zNQxGLgi3hYb{&)a`160?xs?oF1Ho{~IGPhqNHjMv77>z1l#v`MDSZYKB}u0bqn(s=
zt1zU|l0DmiohJFv684^!6j6#yvE<<d*mObiOE|<UB+Niy-jY0~8~C2&HwFTYlF~P*
zY?lmGg5|Mf66Jv#J0zdBqu43QqD|Bj$>Oc(_ESkgKUmr&ss0-h&m>O2K>nS?{1;g9
zUK0BnoDNclqcF`;8bL{-PSW4E!L<F-*)b4s#{a(rri*m>N%Y<g|MCZI?oyr(%Xvsg
zMgZ)9bkGMNp7{4i3P^at>3~LWY2|6C@R3H+LFFLn>iyt3BHc)*SB^@@o&Zd+w4n{y
zA<`M1G?vn-_8`ZkKhWAFOxkJ=&T#3z^*}ixz3hY@Mo488+=!GKx51bw9H|4!Noh32
zLX)J%bvMA1ES1p%pCYv$kH%D~jRa_E(lg|{PshIkgNh7kMG9atrH{g3Z?<&EC=5c5
zbT91^PfH)>LT|3rsUCXsq-wea@})Woz7|MpR-m#F|8NB;7o-Kf(05U)PlG_2bhPmv
zcrHnMDH-Up)NBPvxpWULC$8Xg65y$jmeGl}tI}U6RCrA~f}ADSrPDrwiW^d!5}18c
z8v7KLx1@pjDBYHRl@0MK>FTMlw_2*B7|9)}?FK+U#9|JlMLPX+fIX6Wx6>lIRoaq+
z&a_FFIHIv#TC4zehctEy<U6Iu{lNM}8W#(er_wuNsO*vkT?6McsX*TkdM};jgh~fl
z+I|@7C>wkR;!d*Pya2slc8wARon-?@L)=9s@q>kKGM>_Y+-3fq^qnye*{BI99*|Yh
zvf5K-7y(c(8M6f?Z`t~{Fh5u}!vruPvUWPi7b<)I7%azR+vqVoF0-A9Qkd)=d6C0q
zpE#iMgsj#J7Dmcm<pVlOR>z=pQZ|(KxY08HS9B>xwhiGmqcm3bXDh}zPWFQz1mk6u
zr@?bZW;FvB_N>f`;xFa0Uy5OVt*o~Lm36WswEpOmZMq4)u_j^!(9W5R`2(8Hn{@l2
z@}7yZ9F=t@ue>4NW>RPk)4EKSWJB(iNqi>2UYpp`HzJH4rok1EIAFSwBG3V*dlR8P
z%=9ujMp8|Ozr!Hpo0jK8?>W<QEd=kGenAIax=d4o0qQ2dNzs@9`CD2NM95oBU`2}D
zJRg{u@)06f%H$bzX8e-8egxz^71>Hu`Y2T7koPqzTsai|6jyfx#$RDF47G<8D<}u~
zu;P!E5DZl0y@cJtirc%v8KSsq3zksD>{hTGSA+$?!Z1aG4HQNy*3(QHrARP9?xf<H
zFG#FHG=q48;=46yOHyPeqm-&h^oG6Z3gezRC}t=m|DZ8Tu`dWJvK5|`1(2gqkZ=05
zVhBCrmld0BK&~i?uVD}>6|ZO#yP=qq0Ts6t^J$e?rD!w4iaUzUQvr5Q@rZ8H2a4OB
zU~w{Qqj;^e*^`SXxtcv(3AOHKON^A1>tpu8cCh-Hb*6#@m`(p2@_}Ysx-le2%?{Da
zIMi%e7cBtsBW|(B?>W;c#xvJ)CVtOLq?v90^x^n>K{q**7Mk`0(xOwt@%Q2jk*Hr1
zO=$~D+k;WREO806F3;{qsShjurm*8msV#o53LgTMtMgLO(=~3i5nUTi;k@m;?a|vE
zyFSO?JHI>xh+P}q@VEV^lK}d!l0MP2SMvq_-uH?Fj?rN&{&r-(CXbjCBcp`&{md8}
z2zoQ;>F|aR<4x1QuaWs~7>a%jOGgckG94qp6U@Ax4fGJ^pEc-dGLy0kR%J8u$&p^f
zSe-?uE-;R??!C(R1<-b#hGoED{0?Jx-Gb_H)`C8Qd4e5BQOO84CJ4$RSw$5Ljb+zO
zLS-Bq)j_FON$fN_6qd|3Q*uBGtEPm;Om>k3r7ZS?$spP6eK(LCws9Tg3)oOPjabN*
zQT}HUdx`vJ=h#D=q5eE8q(Quty?hCrm)VN_&|A(bl@Peb{zA9Mb@tR5Sbl^3jMhx}
zr#UPfu+ls1FO;!X!%p-^=`K5i(%9-*1B227wxT~SMFXq;6!ML1@PF%G_QO)>ZDogk
z1nf5UCZ#t%VSl7A>pW+l9)!RP*8CL2U$Xt_hIzv({s+Ad+$wWacFVu^#xTAxDt<xu
z=)VDc$4sL+_B}J1hR1=uLeUIIHqsG2abk-|ct5M8FReJU`(i;{kWr2{S9UUG;JLAn
zXus;t`qS##gS~nJZ3oy~3aNOqg*5>4V#|MoQg3z+y&rwp8C|qh^JN#=g6AmP^c;o-
zv+FX@7{WH>!I&6!ZyPklu>;dh|IbSCZ`%3J{bW9P=Pjm(cYZr<kQXdOC!`Da5yqlo
z2bi$fwh;(R&UT_^sS`!Dm%S|n*mAEu;9t@D2`pM^Y@vwLs$CTTT|Ji~?`yV{Lg0`2
z<TzP7WdtDBec}wU%@Grz?4QoXsNZ>>61aDLLa{+-W;UH1aAE$Uv}spHF$*HTjLG*<
z=*N6biR}lOY!wXhX9D{}AcRSiVH83cvnE=99b>*Jh6!Pe`(LPyU>1{_lgx5UkXUB#
z3sfdBT3UN2F((qC=_(UIQ*I^0oJ0?<F<)PWrt8c^%0Irrgsn%Znz8*3;`f>SVGwU%
z?CADyV|H+8d%>vlAlJ)Gy$2R!AG7{5puJ}%(8p&T*~E_k6UKIVqcV$KkJ!ZjJze8y
zf<4V}UqUFCS-lasdCZ<S0L*8i^k^$!j#9o~A+uMC3sJ<}4FgaylTW+qGG>eb3obDY
zr4YZ&WYWD+&iqe9k*X_99Mx7Zrzt3Vm3d4X|4L>sxd9rPz2t0aV%Aa0PBSyM12COT
zIQie6F!AFd@QPVXv;Au(hkO}M?1&s#fk*NuusE|D=p2VP8$~(1K5YCv==EhyFM#t1
zs|caz|0p|sJO($IU04MY$tL+jeH3d;TalCOWLnuov!*Linamn#dQ4#_Qo!pp>s1e9
za#@cYXv$+B6+t|o4W!M(c{YVoa!c8eV-UE&7LmL0BHJGdF%4L)2K06I0OiXXZ?L{!
zqK7wG8EtItv&<DV*0Qss(OAd+Nw;b}Yto0d2kfXXFiveOmN~TP3DlzPF*}ovA$PDh
zXM=RI8))nGgth+&;!j!i1q@IZqDT;U#{NkGu5PwJO+U}s{dB_mg^|5VN!l-2b`Nap
zVW&TYrLS0KBf9pQ?TZF$FYA64r8lf8C3(JOBbEcLj}4&2EHAE+{FK4mhda@Bf(zP$
zzQl4}WK1e|@i54FPF#h`J6sz1Ksvb7+feB!>DU6yV-n*Fx_HTwm~UWBu_X8!K(9(3
z(g~Yd$<$pC?3VC5K;B5o(iKpQpGv70ZHQ~|1temV=2E6hy>vX~`Zh{82LtJ$RJ#i-
zZPJt1ptMu^^(H_(lWy_`XOA>}32g3_Zu*$cAHA1;C<m*vZ1}hR{tsUmOSuvATj>s1
z=x`T}i@#R@W@#7QQ_HQh(Yo%_E$Hz2OdWo2v!HFl_AAx+d&gW#H{Ch=TSz%DHCgD6
zBhyFIkq1*n*~<r*m%fnqXBPei_(Mi!40*jmm}d`A3}q%QMPn3`E`{JphM_p+DMmt`
zh9stsVz9}~9P*lEGmoCam>edI-jt`ADTg7R%lz*h#PgWi9th+!D?MRL0h5pgltRYE
z9xO%7FYjrj8Sw&031f7mWx*L{14W6?GOy+X`y4a(2gsjiMpE8mDN|0ay9><Wbzr&3
z3=9Bh8MBD8R4*}J49I0>?rx|kXTtx*5L{t)9)%SZ%#EF>yvlUZdc2b1YfyQOnW;kQ
zIx~sVA8RoFl<aqxc}KZ8_n4J>Xu8j|{YBT6S^Ef9)G=$L!P3Hn4gmHe=Gq#tv@)~l
z1WX&_PX54lCVnHZA2XR+pmZ?Un$RRMiFWfTtb~HKS?otNkL0i(cYu=1{z1<2e75Bv
zy^)LA$FxT|%O);IXG&RD+VPjMXRkuAoK=&9<SP4|mYX-&hE))#VN>>lrIDTK3ey}o
zw+(XC;zx|9zJ{_z+d+=8xw#NM&PEatX2TLNhqK2fLG=mt?LHV1!5XJhurZRISq}4}
z*g6)h$nU!aWzp=<lc6Ps{qs)<#<HJME>s-*mjMFt><~)1Nnod#fisZ}t_9~Qw)qq|
zlUU0Zl#<zJme7>KuBEi2RJL#j+R|8C+E{0^Cn=s<%*u^nfGJ_47Xq}5b=wWQFR>$Q
zV9aIqbv<~>*;_wA;ugE>FQ~uG>S^^|#hy$<shS;g4s!J@{*wjGPw%1t*1-Pz6XY7%
zH@iTZ*m!cVH?vy$c+W$2!QYT;VYgp~O^?`sg+`dz%8sS$*T!y8fVG`%Q2^~R`wh*~
z9qa~jcz3d6a?$pL-4p}T!<N6tUGR!M9S?h7v#xX#^|I}>t9!$~qmKf-Wj9;|XCIsV
zJ;*!O?GV~rIq^dbmm8NrbEYphwSiofeq8PX^zaBL*MsLM_iH^$C%8^Mcp|tz*FYkk
z3#9Y73Eaq~=tVkrp5iDO-0o&@=5u@8K?=D3<On>^O{9#sQtk$&@Lu4i9tCG57j6K#
z#{EqWs_Wd!8?fmHHwhD|5#FF3)o8rMdDGdb+nnD)=&j<G9D=55ZZ}<@JDk!1EH#|t
zR2XxYv;6>-_qg0vko(+V50F}JJ1y7hxU9Pnujdj@1MC5(r-!|XTS-C6X70swpgiP?
z&O&_)=kq<fYi#2hX@S(v&3%jFW3H6mKONjZ(Gcw9R<wb1alZ3Fo^h*|0=t`wrbt2`
z_X8b^cfh}Yg@B`EK`+{zB%Q>vUsCfA+MFdF1HtJciJ`!@yQIYeiaaD!reS2fBs<$-
zjJHuz69MymB$w$9^pz~y0Zo3A#oN#rCmHu0EKQdT&WA+4<V$idoRjRNq^)vETq-Kt
zC5k<CeWeQ?!3uZTw=^<dveah~_mRyh1WTao#eF~r%X-pL86q3zj8dp<6?r9($&9K*
z(Brb27J!D!>I4`ZA&Z#^OQU2G$^wj*rLkm;Y?vD=<7L4rfF{UVBhi*9OMC#iQ?l#l
z(CuW|r?lxvk^OrZn5nV~eCFZ5X+ijU1(@e2_d#+&iUWQx9IJ$)MXMJZVf|vSL9lws
z|9%A1Qo~gI{$q6)fYvtC)br;zTk!X~XO!`_)n+vK|9NH$h;4P{Xx-i%gx@=Io1kgu
zz5V$8Z`M2TJ2PkKZgxSA3~cdc?3dAqFh83E#g~~G3F5~rYNYdr2bqpO+&V{@ck~_&
zX2#PK9>T<21_@<qnrNJuEiHgfVLmH_wru8x3(yJ}#ix)v%Q*f6f;R%~zpgSzhGLj*
zG2^me<6Y*PX(%-?iyp$5cBZfel`ok;O@QgZmSQ=x4qom@2o_>S9Od!<=Zcitp~8>p
zqwV)WX4+?vJ<8PHhiou2`a2AG2$S<A2ws<?p)-nkI0~F68Ap2koMJK$!}26%TO0(E
znRt3#r!eh7#hv8trX1+A%w9?eILEkjpgZME^Kz7~FcCITdz<N{B!wzw=@^LDF(HX4
z)iXJN1M>mXkb)s<VEX?Glmu331(rm1S1a8E>|Q!<mc+iMnLL@DPaBaG_ILV7Q!2Yr
z0g}eX8~33vmsye4@pY^)7z)F<55|LpbDe*n?F5%l0TmJ4NP4UyxzR&0R8d?ToyIuH
zZ5{-<Xih@+ZVWeiD_CN=L>hxQ&V=r(c<zTmFwIxeM%e{^5((`Q4@y3!_o~07c)JlD
zJtPSv*JXg@M=YqMhb4^^iwl%+*{BSXOrzA|Ba*XWC>@n7qpbE|NzH8N4UurK&@~sC
z8=WOfkoDgRy-6~E14`+#OSB}<l6_+ZfgD*2eflh4HYW`%g|ZAf6jdx+w2PMeXJjjR
zu)dTX3<9f{$uBWbpJ*~)hsp~k&rhRt$s}bLthi;Oz}bQSo}gAXj`l+xY<C*$>SAxv
z`}+m^{16O!&Bl^r$&E9wq8C4YgyEEH`a=T_Fi5AxYw-8<o@=mj#&jd4F3xn{0O?<*
zoWh{Y8cP1bUw7+(KKtEC2rpXKgZjlqukm|H97XY#4rs&Q%Wj{9vgPk5!GIMLe}mNe
zpkerX!%Om<{Np(v_HV1A!*6>=(xP*(#~4VtFh3$A3){ly7trEnWX|6~tvj=Y_E#Q^
zH^plbnQ!tTkiiT(1D;$amZDt6O!^OKD`hG}QCZITTYy|=Jab`sHKU+SVlC5i52a>i
ziYZEunZw_qr!Sb;^N{Ofl2mBh&weo!avto<mH#bKF#f`xO|bpP9Xv*2@?*LYw@YYm
z-NT&v8&<qxss{t+4P!b6pl_K*%I<m3jHI(O4(#?RsNBzP5WwloUM>TY8=FEIr|#?z
zwO~2KW+nkRfZeY^=@e_f3Z(*eU}L}kE{zc@sk?NDznWEg1LF?sQxC)%_8H|o-erpy
zK<XYVQb_M1yZk$Fwy^D=pwz}DRKTuw_M0u>>|`@(xBP_t_5byD<v~pyVSL}d<RM2e
z<H=~Nu~Y?*kjEWrsTXpH$Q28SRgNGi5+o=dqi9i7ik5MdZ>Wl3s};3$>WJ~E3?1uz
zF=NM$R>fAWcuhMha;UYxrR^V`{%teaeDC|c@7kT0-F@HgOBh<Wli!#O^Ig2W9Kn{!
zGhTvhki8GV^hUX2KI*thK2-|6;?433)T{d{>FX<|S5Ku5ai{Q1su#1|Hp#vmKA%fH
zHlu3o(zEd(9a3m8z!L6}-d*jTi{Z1JZwiFn_59bXFt?eHYJz$t-z9F9h))vWc0NQb
ziPmuYJaD!A<7HyGX9q8R4ADJ&b`ad}<>mg+*vCt@A?5>o%u9G`;LZ2I9phWXDACAw
zbimU|-q;2+r+7*c+UOE*dJV3be<qe>uJKRBNc$5Hz6N90`NlZ_Z}5ZScRz0O7V*eK
z3lFupvMfy2mWu`MpLt)AhWmvd6x+dX^Xe>A?FsKa3+|ut(_*UnjIS57jyCSJ6%L<s
zxj(=T-fDwn7q1Y{e!k#FF+7yWUyVU9tK=L5L~7)NWO|0amUlqCMJ{ax_*gzCQk-q_
z`8Y_vl2@HapsO{%Z-;l%EE*3hdo^1k!8K~Gi<#RcjpseYd0S)N3CVVip%09Gq8%)H
zsm<C|t>Ct3hipU;JG2iYQNi8#&kKNCl~S?XQmxb$i^TGF<<Jy3tWkdGLR-`+m00sa
z-?daE#P=yD#UgXPvRCv3-zckp1b0wj$%w+CEXshwVMSMlD2^&jY@qp8xhB%njf#6K
z95yL+;tAdFlwCcceq1T=fcp1JcrWOkP=+KF13jaZHACitvN8&BUsR4xM=+O^p(~(&
zS;?*WyL$^iT8$=-SRrn{Baex3G>R0cPu9f)iS86JOsN*%*q8-dpgI-FeDqx#E<h`;
zz8>+$r@V%Pgqlv&J#nTHQCf;OiFDz##&rnm!&tF&o%CoGM3Y;^Cd!l!F@vA(oDI{d
zm+#{2N9TIM#LP4WZf1Et0Frj56rbs5mO(P3YdP#>p1T7JR!L-qvX~g@XKQP5oPAZS
zE$2kJLvl`Z0FLMCW>n&I?o@H{%v)E96M5-XKx|dvaFajj4w`BH%bN(L!2Sfs_Hb|D
zMWJyxUivB+_)2O2BvfRrRBMKfCdn0f5B3)NF`0Qd(YEJOkk5pW)PzL5r}+6!Sdeaw
zoESD!HL50~`Y$XsKX<|GoIHCfxwT7SLyL0q{CtI+(PZ>B`TCgxeErk_Q($VL&6aCV
zP0z{mF&b%lr!>gbXvE=PZ<^mO4gS9!_NR#*(vmmqb=VuW|DR^;=kV{6mfoezBTl{O
zeT)>2`z_q>5-q>t66$#SYx$2sV<v?7SnSpUyH7@1L2i-HM5}#np)KF1&^Ed-+d6ul
z&6ej=WGk3!&ri#+LMCr?q19e!hg|xC*|goH@t_wCiVM}5G`-d=yeOk+P_!rtiW5o?
z$HI%w4F`HhB!tbJHZIx{X7CL#b-yf*@Di7x1iJT7qo=`@+8%UazHX%B=oOdhWEyx;
z_HrbfT(iTd`ExfHO8rvn>=?Mv)${q9xLh|!T&^xtOIf4jK6Jc=52N;dF8v(t1-cKG
z3=B}sqgAuN>TOU}qn}YV;M(&w1*uqWbYwl!1@|<V{mlV^CaYhdS@qAzN(&ASwyHsX
zCRI((%nb6k2Civ*p+j+ZG`{Fr8Cs0r&t)9*9c<fS978z%Q-dLYz>vje+?_FOPhuR8
z2HX=ADJ>zx`!hB`&;g8Lsf8gQz>)+tFoyk8jC(SM=`-WQ7~3zXH)AIRMPG75P$Oe)
zf~xoy>YN={LiF)&(jkX;xW2z6HPN^TeUY??4oB#x@*Xba5~+`oDkwP;Y?2%85$sy(
z1Pe4W3gk3Zfp9j69z^M5xYr;GnGB)Rv~DtBufcQ;EKf4fh-kpKXmPZ#>`7<AaxYIB
zFa<Q$ljaDT^e!C%m72*p24Z7_DJ7<xtrKj-8R`=3X^NZ*&-qj($St}rNDY}|A)_}?
zSuA9-=_*(l@{R*pON&8x#85gLC)|3`fOrU1P)<Bx!$>+J*d}sL0PCevN<#P9I<P=H
z1?mw%QHelzQ&l3^v4QjeEH{}c#G)U;4bGHh(Z3@dqIDMiaBahDi8WJ$MeixCrmH}t
u^CV5v59edwqY=~e!?@`;iU*Z4X)$2w3#tY2h#jM6hjAD6&kHl1?$@7CMlPuU

diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
index b77aea03638db86fe159250d823b9547e2d4cd4a..7f2b8672f37cb05750fc58dee890723d90f19471 100644
GIT binary patch
delta 125978
zcmXV22V7Lg*WI`5?rYooYV3)LC3a))EiuO4do-5VOQObT7CS{yK}3oQDosID5a}qW
zsEDEzMG!<#l&08F6#dTS`{!rg?A&|Lxp!vYn>TZ3mRHV0_Bs#Q-%^_R<GI$89az`a
ztYqhU-gB!%)6sWryhJLMzyHet1-tzmCy~nJ*`GLxB5pq`k&d&?kVqh6cXgFYq?}w4
z0|Sn&%3&ocnf%XHf06D7Im{<}K5-b_p@Rn}87n;k4Cgdi+FL4-$c9anOqDu8B4O0O
zagu3`pJmKK&);MgTi!ZeGP6;lWsc2aB(oYn8<{DdTV)p2*{O_VZlk0nbI>zTX0cCu
zCz1T#DCxp%?&2U>(D=Cr^Jb!4vas=UZ)Q>tQSyg$3mo=mdSojkiyGyFnUEEXWO3u?
z;mjP^ERnjw=4VE6hL<dDl#gdN$4DiAHh!MW<fB>38b42GmcV|wbW3{xW-~9|^O6;f
ziup`8m4jqu<L5t^wJ=)MNV=3c<@vkZVlT3>lC_PJO-%X(g=Af$r6cq7t%GEJ<L8|c
zew|$|`Ad2o)NEH=<Z-jmZ4O=;yhNg#G-9%Z`JX&xJ;~1<;Bc)CVIY@sGX0DHsTJQJ
zC3S#IhU<z|tb}oh8qf+~ngg@lLE<1$RJ4>x6dfHl!%Bbnu_$3H1nMK9E|8TxCoKK9
z6aO>*Egd8hL#AgB#RSV(SGk1AZnPx*H;sC6sHeZ81vAGpQPGz9JE~OCP5RBOv2uw+
zGma%I2Tv(4H?EwakT^6|$jzHQyYfveMQ>4UEjsW@xp2XTkd#un;-$=U0pC~pZm#E1
z-ogZU#_%naNgkp^<`BXd<t>JJmhh{Xt)AnBUQCLolhDQfWiBI;H9C>W+nu;1NaXF?
z>ZKBSheZR?bsc-jq!O7#j*pV}pXIo=(eb$cQlP-KeK~{cp+qwHG6NuqUmXY}C+f-m
z&kC~PK9kmZhp-?1C9TT>lK*s)!*!%RSwt}*iLT9-(skZZ0{ASa>&|kLRPLkCSpx}>
zoacb6V<^d+IuV@~51(9OVj3OvC2ewVa^Jmy0$QC!*U<yXJ|Kt~mPHfFh7OZU_P(-{
zsBRHeY~l1-Ka9W!%>-*UpI}Ga$o;Jxidy-O+yvYwOW`Y7HY_7a?FO<OK7jh8Je7Lr
z#vWow&nL^iH_0ZtFG+j`(dYP^<nhxg#*RYzf*kPeNxk$4eXjVCuG~U0df`v<AA6De
zcO!`|0?({mGI$HM`}R({I#rY8d`q%yvVm-d-=iRw+$8NkF~no&ND}2s(#{(}pCx|@
z5<Du2k>o7;5ji+Hp4!oB0jYi4kZDgXU48wj(=Ohi*gyV8biSSFbNg}B;<tFT<PupR
z$&+4CC|ow#4_!j?Fjoqz+f|Z}EF+u!t;oxuUvRZc-ajYN!{sDO)DoTkCILb%6ws6k
zax<>652UxrX4et2899o=a-2t4lQT)O|D?9I-c6D_(PSAKL<~E}QxLZzNit{zg_T%I
zk|~XMn0=BzRs1^>MNAUKc%-o%4k6??tsT*MbReSJJh}Y*H(fWZp=-lry8iHrEN3=$
zd#}boA6SSjMNQ5oU8Ba#zeS%rWKxJt8k=#wo@{Q}XOMe?hTP0gAfnOkWEvSsYDMFX
zR_9G&Ro$lRkT?oO+(I_z>gaQe7Gyd2A$>0OB%AsB$jvAnIj;31%XNQ}_C{w4H!za4
z?N8H}{>=b<|8mLVr{w;J#&#Dg$!PEdB2w+A&p*$jYugrNbL<dZ4`Pgl<4CeO5Kr1g
z-_hqqONewz<83=uO*RXDC&y-&#vta9uSI{8<WUPkaT<L8a>+g=soVWS;B_PEdpiG;
zK0kR*pFiN;DVOAz6W#rG^jXD_eZ@i|s=P<?!Y5?eveEuPqvKgG$mYpbk~<cV<MZ99
z-PW%p54cXKydp-TkxTkHllsngM7_x~Nn^1)-yrG%kI2;F7IkB44Slw<ja~f@NiMk)
z-RAp^pBo30ftl0?9tX*?cou!meM#D;Cy9S<AG%6*Qa~^MCVAes<Yinf-2j^>kfekL
zUP-Wh7DbofNY~E?2vDaXg*uVkFKzthf_sqr=hYPS(Eo@c)k2cy(@Da)ko%fLBsm*M
zlIwWw$R%sD$YnR4n6E~YwopM@_bbG|eH>j|j<l0e^Vwt+nL;jGJs~4MSGr1yiF&s{
zHm!Wg@iQfT9;2o}UDHV7f4?#4(}Z>5=sL2F+=pe*b&{R5-pi?<KBUv<wU_DZj{1!(
zXH8=1p4hOPNI!l<Mynf*j{HYPneRxxb`S-(b_Hq6kI}Ws4GQkjSCUJ!sbzc0$i7!f
zW4qfBYSPBWR^A}_h_+;3t0tFS9Vv*;Ey+gJT0vvt$-$)VH<H?#HJM;-7LhujJ%Q`i
z5b360Npf>GU7x-pBAYjTe!G@XW2TVh(aVJ0)`voL_(-3Fx|6e<e<@ItC)qpCratTX
z4S78IH$K}XNB<)_c{mYO^(CS|?Ih{f_;f_xpwE*}5;$RfBdj@*_75iq-~QC-MoBhh
z!F28UGhG)&kfl#gVtZIf?z<Sta{YMXVH%&f!p3LN-n<Vv)=!{T27RK>qvueUR#y=$
zw{bL_QAS{^ACYc|Ad2d6vJbsLZS5RS+WoQQc;f+*kN-?On@h=kvj#$S>P?&j7Lomc
zb!6XjCfRqg4<bP4vjiBmojyBM(zUgOOly9pAhxCx(cH#K$3F{+XuO2FaoQY0wOL7$
zS9=L1bfmr+`U}Z_i>GTB8_Ab8zDMqFC7$uUiFrXHT^(KQ<X}(?DL#*(&llHF`?fj~
zc;yz7GxLa|VG&V#sOhr{CVUFXOCw2c^rFwdsAahRyb5!9$y9u03dy`s3TwoEOdch>
zA_QEQYFLtwr*_ZvqF&(+aCV4}b|um=x#YNG<9%?XTnc%?18QYmHU+WzJ%P<HiB#4&
ztd=})Y`2Q8Ga0h{&qUOWK$aJlP-EJfi1Y3T;-87xyh2i6MD}AViGS8ltOU>hcQYx*
ziZK-R-#<{KBm0r*IS=Zhna}ZRl0^PQHmi@&^~d@2{rw$B4sJEh?|L+$-g<yROd;91
zlH}4Jggs}b>pV<h6p}8b6iOT1)Cx%l%n%ile!s$_T_XAu>_if|EWAf?&F@AnzSKAy
z$UH&R4p`mbCT+aunf=u5_7IU261i>bA832q9hkYx+Z&goTZcvbgU^$X9Yaf}bbJHt
z)F+PkJZ*#%kkcLL5ub6_iqK|i*4a^6IAj?rOUh{ix@H}H!yC`hgwpQZ6p|fG<`8(_
z%Sf-HIK-6D?82M5R)ruBGqyC;e3;?uQTQ@*p9AK{xJ-r9BTV}$cs<HwcSp;QF&$0-
z9>4?*fv-TObuKKAGvC_hBi0klFnU*<WZXGOgP0l;1~V7za1p|!(@QRt8Tl*N!kAHA
zz<rA0hXQb#S-A-f4rk6h1$P7!PNVi2=EnrUBbk5WAw0`;YL41D<~ll9exBLv1b7tl
zj{sdX6YhrZUVeeGJb~XBW}*(#i_9q+qGOpg?qG{!s)JFBXX-A)eF77E0{BE`SSW-^
z%uyO&lbH-}1e3x%tOv^_CY1)F%S^6kON-IYim2RU{^|uk+04fo=-eD;!9j54GQTH*
zE01}VfXMQhIa9&)kU5cta0{5>G>#QA>pP$*VYXGkK`B#8Q>Ukln-c)#Ov_1NdCpAl
zh7PS_wj2kpnwj?z!k5fZnr6RZM%h224YkbsMUcK`s_Ia@VOBhb-?vOu9CYuPFGC@G
z&+MB3L>=>6HEJK2uWb-$J!5_aho6{fZ_%*N%%(W#zB2ph``jk|k0wdmrCA3Mp{sQJ
zX9524uk9!rG<tL#1<0z!b{b??&yIqpHC=vz+qK1Xi>_-oSn~hot>^v#i_Vd&(7-NU
zKDc(ZVnmU5Q#XgR?yhvR1~8Mbj%j3<ajnr>#c-Nbvsasekh6zD!k?8h|8LQ1B)z15
zsKywm*umI~KZ9T=GXrC~!ikZ^qgl?(5X{IFF3dDFAg)YwOFWH7naMN3c8r<u2qtw*
z(;*0}feB0j*)Hk)d9cK&Hv+MHN$YQ+<|FOskJ>S5lp8uAQu=8ja4FK}co5|o(lKwb
z%tUwC<(dmCplI@89wKfPFcEZ}^L9fwU<3opNk4Q$d@B#E#&s{l$Phv>v;Pk;CNh?P
z0J+VyI*%daEo1inUl$14=^)gu#;~vG@F5G$>^KUq1I3TwTQGQZy1N-kmd=!1QFOW3
z8?Sdo*Z)c|&~!^;(NEpW9wF!+yL{2PJ>4fGj-O_xAdX(8VfZ$Cw@${jkE$6g`?_9-
z`(fW~hj#SO-Uw`>ha>Fgd~FSzrJsg^XRU8rXg4j^L%xmK?25)YF@4s6+mqqmgT&j;
z>}O$eoav3!0-n(Qa*)O_L#HF`Sf(-hIHocDc&0J_1g5b8iA-Y)k{F6wk;+``jfSK#
z)RM;gKv?_{onTs-gR3o-Vrd!>1c$Bui9w{_{k|3b`Tg2vwB-CTcrv=P>!$-ic0Yo_
zR^CUy48aVTMqlHg5la!#@b$A0`!8o`1vHkEf^L%SKjbm!hPLQ3LD_6mM|^J6vpbx$
zi`j&0&&m#PJ}B=h<iDJtb>*a8^wc>rbqYA##=JtZ#V+5@WY0$RFjMjl<UY*ET?oyW
zxkT^r<IJ5+;5fnDc?IA}<~6+n&oD~l!7zUDui*DA^REb#SY}Wu;Bm~5Fj&Sj{|trK
zD~#Jl0Io95QLwzmln0?HIZWG$Fv(@6--TOy9@B}!e8wd11)`iOz6I0gOn)Uz-!ntg
zfUje=w1&eEOxx`c?v|!Ch2<V;{zo`;l1|V=cu1OML*Xs;^Z?mm>D??uA1n<&2C@+8
zl@-v1N@J%07bBgx0VWrv%wLEi)-EleMcg&%YRX)sOEvXS-jRk<dgZ=!RVxS|Nq?j7
ztVmi!_$N}ov*_GsQu|xfDy8pL=&twDNo&y<M~ASLAlv0269L%kAl(B?H-{^DY03{f
zoO=LHABS75V0qG^(<WF3IoLCPL3z%>?<zc<cTg_{>1Br(qk&I#Xpf0{<5%3WW*9(i
zR#l?<ZB$3J`?~`h6#uUqs>c*YKCEaTd=2j!kI$pVl;FCgJ@dbNvB};kXn(t>^Fi8i
zZXT|kNBw|nxBIOmxc_=OQL3VMjUPb$cKr#~fqy+ke-8=%1pyCVwgRSOUeN?*avw*?
zXRo2P*dGaRpk48JFs`eMYQeD1l7}`VD5fG6C{I)b?S|7N#naJHT~WMT0^Xa75mM;x
zDQc0lljkEfDZu|NcKRHczF|-Ghs`!V^b6X0fIl}FrqOCiB7_O*<ah9VK$|cTwS(Hw
z=>OgOXBfXK1XjR|$%dOp%&$oJ%8QsC^!_SgYz74Sgz@pkH(kn%Jc;6<bk$Wj^OC*_
z10n90w$0V{C0`JZpY&u4a2%1^-lI4w9i0MjfV64~YJt+YI5<8b-9H@7Jt<wY7qMNC
zwu?j&Bh95H^Id6QPx!tkExQKd9O>j&z~xFG=KyzK+LD&x52UXBAbcq8OF4l8Y15U6
z<dJloy$7U4(vP_?eJt(28qF_}&Y~<*sWf6KNXw)Rlu>vlO@4<aluPFig7AfO$}-?8
zqzy=S%B!SeHvp=oPRGIR=-~PvblV&{6rkAQP)yyj)8XZ0M8Dgidkuow<8X@R+@TIx
z!azvF9DL{-y64dO0&3X~jx1<$9ZnX)VV=X9(-1yz*hI_3e22}HM<{U6eTSmZ!O3$?
z3!{C;Y_z)6p&}S0PaW>Ihv74aQ*l5)cliD;YA+n7(d)I+Ve?9GRXN0xyBdcb2T^<J
zF#Q88YaLb?!1CI`nX+SV9TwC2?w!NB{ixMBOnZl>d~k@TRcO6Kz(e3ZIUJ_;H8^y%
zD`EP@p~p%zX`9R*iw16&xvqe4m+S!z^t)x_Pr{*-Y)%du<}5q39KpNF+J(a5URenq
zCb_$83cZW>$$q>K+yU8lKCtwVUDyQo2W9ChSbE94`a|a}yVwQAVc7x76!^*F&e~z)
zFH552+EH0Z9-=rV>qU(Tlqm|KJ1%Q>0Wk&1l=~4yu&juBIaKyDl78|qS-0H)oR;<O
z4?wu=R!`K<$P$`^EK)X<QXA)FnnA#wmlY3$Fj_W08(;Ya8Iuh_tZc&XGCW3cvZp_S
zEkRZi4t%04vjuFDW!==UNs)b~RpDjXWK8Mhsj~Z55dIZez5-EPl`Z-fMY?R$9SE<>
zdZfbgrmT$_VQ0u>3KW^LvVJhREgOX$6nU2H_&~7Sl~sEpm~2_lT^_HI92tKXEzFZ$
z>J6IvGCw^K`LZFNC?3jcDU(_#oAMaNBbmo8&=kwK&uH3Xnc58|r7{cUEz4xRx1o3@
z^ZXGe<+5S<aPdMmr7eUNvgP+tRLiEdhoc(V)z#>dSF$Fwz_QoM4*U!5H!{z9g#T7n
zRS4yK*+MrU>SVjug6*Sh-w>GA%O+=n^s{WjQgl~?Y*heE9Oe6Ixv)*%wH&w|@~zXs
zvQyrxIYQel_ZW+=+#{c0f?sF3UIv_tT*`xGuY4m5OE<ebWCmR9lXDN?V!u3P3V<H+
zhMytyl#hvp%^~?Wqu|0@zNiEaedPW$tM-)-84PZJxmzn(9+5xv0Q{J|`Z78=K)$jk
zOpeRfZwBs!Jc;@@NZz03^1*WVNYujQb4J3^DY<<EEhNL`gHOOTLhhY_5F_P3hodoP
z<!40*qvZ9^z#T20Pw&JSdC^_aT$GP5gx@&%oFKsC<+YSSPLwBQ!6Zrk&j!F#<j1`L
zza;;WrdapoQxBr{Kt76=83pp01A!})|7w4OXo}>wM?+aGKNAjViF|nw@K59)2EbF9
zJXM1JdMf`^29t8Rl-{h*<*wHdsH37|GKy`A+x;Niq0lTvOgj~ov=HB|(9r#~M-fEt
z2xrC2bU1QR)QthPo8k!Nv)mP)Z7552K+%t0ULK0>Y4GHw*sK8JkYWub<PIyI<f5Z|
z6m2iV#7{AvvTpv0&B?%JDTee%?XF_^bXevnoSvYTtMH$MnC>go{Q!8N$lZn7L&Y7M
zpBE_Bb%Nz1MRq&XiWH~%AWI;BtjKggwM3CN9!05Qh7R0iin0*2>6wBX4AOGNxdo`b
zP^6tfgcXXxE78y@#h|IMtXAY>lT7|fu}%u^T7@kVEN>MFH-LMm=x`R69~3PXBZ`lT
zZB@{HR%~5@1~w?pAQ@nne^os8g^eTIw-zq8v+7JJcd#YzP&>o6B4H%!`35e|vFnGx
z#d+4t3vAKszvt1x7ua{-gY+W1KL@o~_D>dm<Jlkn0!sqx-VDMdHX;eNWHw>~beGtw
z8{oXmuBZ8_J&nzp1e+`DQp#vwV~6BHn$8AL3i1Y<7XZIE*$p(J-eUK6fG(3AMOl?Q
z?6gn#4zt*u^yaw7mJdNKoBfu)`&{->4-|Q9+BQ%>U_G%LD9>lNO3`@*?2<Q#zL0gL
z>06PVt-OHN7qfoT5nBmcIt+fFu$dKb_>`^Kh1xT==PA&<V14dV=d;306xFQ%FA&zS
z3pIe(vb~cL#cOsswkqZC*j4$!y=M!D!Q><BxgCIdb}r>s8`!6m3HZV;8jL6$InNDk
z)%K3h5#LTOG87@~<_;vF*u#C-7Iw}YmkE9st~<44FSmLfINZ3=DJb@FkDXw-pYzxZ
zxCb|d?hQ|F%_S6GT*n=V<PfKdMI@=*u>ojo8h2<Aiff!1+spEFu7)zNH@UC&*=TGA
zw;&asGPxzML3*3ppn$_HPDPs|cezU=z?RMZM=QP@?w}WF?sFz5;2v-@Xo~-kGtGyv
zfLpf@?u$6b0N{$bgY8j!!i}LRVkx(csGoAv%AkA3t=|Fob50y=2lor^R~q>$xvphs
zOcnPu1R>UNT`6<-l1u9XlUlCbI25nBp{3Bh<(LYD|BlNY1>py7&OYjEE|aD<pSbIk
z_xsFQ+kxyW*9u$Qaz|c4bHMF<!8O!&@NFl8dKZ7QoR(6%d1(fuPJHE2w8EKxxf;Q^
z@`GN%#a@2#6GZCH52S_GK0b?5RtNY!wAS_D-}r#Wi|^<N;UWG+D*PViy-uU%!~aMt
z41eA~24qM0cpnG@_{2Pz1o9VX5p#n7783xw{3Nf;LEOQ7YZ}Nx_!b^ehVeH`P&>sB
z`wmfr^D#6Ri{S5YC?feIWe}d_%V?;K;vH$rG@3s+9o#Xz={bsv{EfwEOCIk_14%yr
z@;Xc&@|l+aFXV5WM)8RMG7)a=#r!8quRiA6W4SFa<!5&Su#CSHjkurj-8TYQ&i^<T
zq%Zh9+DWP4-wlAUnveYvCN;d<8Psa|X2_DtU-PrC0{)h-7=hv)pG1p^I)2Iv6d(B7
z5op;bel5BG%sWj-Bfi-AoiQN&%6motzfD-Y7i`;woLk`DDLhs~w@bK<l)ikAAWw#g
zlhFA%fG$E=J}g~@;@2>76D0q^#9auX-O2sJG@8;K5KdDb&{N<>19wn(Fb%jv!VN7<
zyalTt0Otk!-0_e`3D;?qx*#-5M}Nf#v6LB!6}~P-6mdf7S_GUR^k<+;6nv1JkS7Zb
zE}%&fex*t4Wx;j`o>B#$C8%8yL>&NEg@Z$2nJzq!gYLR;s2VZd6!!c9&J1DWB-CyT
z7CSBB?g*`DJNKS2og8KhGp<3HEA-L8CQlgC37#GZ1I_pj@`bZA;i5ojgKaN)p|I`=
zOp1k!rl>s@RJ+iKCj#3B@KRwb?Fl{=uF?GEnQ*uq#dE=L9)vH1jXS_nDSQ`ghqOwF
zMrK-GBk0DUPhJZB$APU@_%#^1*TOk^g})W*E8*##kcxz|{DUyn3B^aju`3*Y5)M>?
z^s{h}rUhSw&_@7#6+Y`B+$Of7-No%<pbpXdibH4-;wO$B3HT8);!g)We@DgH>4+vk
zjOv3Z0!7~lxIZB#(9H6rm`s~S!QxmciV#ttz6=xFw?gfd=uV4+aPbr^kRrtR40wtZ
z!)RJ?Rt%#h>v{1E4^L6zWLofD5KDW*Bu0#Bh0tO}OEkR$<HUId_?{BPcXv@Fiof}z
z6H>%|onU%NtT=;Os<?$VCDO!V+U~g~dYwVfq>BY)c|(jD2ZuMsEm(BRZ;20nM=eui
z{7}0iHlwLZmN<Gh+}{%oHQ>w^!|A)v6&Je$ZqE~cc>v`D(a#apd~t0P01L#z#pu~W
zasNv+tw{Wi(!<5#;`0EOh${*Z{u42NHn__~e;<VQRNQh4CgtKNy1kx@eP|b>LVWuL
zCY9pB)2KCweM3ODOIfoJg@<w(O)Nd_$~G<t>Y#FLFSz$ozA8p>NO|B5gx<=h?kEl`
z%dP|Aqui<ko1d~9EpGjl89GF9L^;+MF&$Mtpr!6HWf27vpj^@wxIksM?@&9g3`>Bg
zAf@aB0Kv*821FR9{MR33r<C^jze0LT=}`-tOyzPKUvDd&=mEH+)Y34UrR?4v#a-o-
zk0|ab7i~t7t&AmHj<U#%B3F4Y3PqmsJ07_E%ITDle5{<!L0F>PU53_|DL;gwc&>a;
zd9WACb*0onN|k*x%1Y&Z%GXvYKhU03wQ~151$^LN%bB!e&^o*rm^RIG(Zk<vNrdFP
zp10A6wwb>p+V3M;L;gcs+L~{7#u;?&qiB<=!`NilbR6Cik{{D)6Tj1f$B3)*d2G<g
zyX1etwQFZP<!HLSq<w?#t0{;ca#~sU+%XV<pN6KO1-+OTaL_wuKO}v|ECgNOHOQXI
z`%P?sW&b$Z1sSl4GN6OL(jMyID!LPg6dZ@mP!*-<haGJP$HOPkDTH5R`a?c_#Z7!(
zQqz+*BQ`0n!NGRsR~nz)m{}Ioe3_$K*d1d+#)0xA({nk5VN7Km=*}>vTP)!C=fXbN
z3o}>t6%C_%*;W~F?Z*1ibi$q8K`+03>@Rzv+s}@libft_`%*&8gZ-DLBc7~1+Y=ES
zWam;o(2H%g8PY@SCNoUE*}y6khuMpV;na^^r~;`!d$BWw$Jifn>`orQ_Rj+#kgcaq
zIL=<7#d{FDXc+*(Y=<ofErgwa3c65s-5BV?*mBy2I>n~XM-->ozV-$18_rH?3epI6
zHG|>|dzAK3BH4GeC2*FVxE8{5Y!k}vooB~TPBn`C*8wh~*;xXL3#{E4y%WQFEeGx*
ztHV(?%!cde1r^7BPb-6X_Qq-ilfX_rh_Dk`bR5l%Hzv|fWitEXJ&F`o8Utx6dzBur
zG&V$wNUyLz--PZe+h;I@*Vy<$aFNb-^Fc7z*|ci-y}>R!0$c`rs3%<9Vms3NJd>5A
zqStS;`#J!AhjqvYE{n}ng5@sTwGT}0u`ahLm6pqT5NRI!F&m`!*=Q#e57^cHVVckO
z#eq5bL-w0iU@Ktf&q3=8*)wvGK4L4#eGz*n1G-{%?G|+DWA<QI1XIF(ZUL4j>~;F?
zOWA^Au#~apf1!KI-k6M*J!7q{7>vK=Y%AKPe$MVCzc1K4%9~cO?I$3nN;Z}{zlz<}
z6S`{FZb7YvJzWg<FWG{FC|<E6Qb1bE4x<eHYqn+pqIkoeFe1>mtP`CKdB=Wt2@c=0
zBk4R_9XqQvOzPR$Pf*xDv8xlI{KC#Y1k<l<LlsCJIc4L@p1VTtvR#~pT<qb-9zfy5
zb^QW>3m3i!cvo(1B~12ml>yMXalg_2q&xSHx?~@xp^Wl=j$Z`M1KiO)sCjUw>22xB
z-G2=DK|80TTgZ$1umV+Y&W~~rhq>=5HXrW6CBziS_5K~jaqidw_&ve(qUqO3E~W$>
z6vVmFa2U)T<MEA#a4~OS63Y3jz!Jutpe@5wTysi^o#yVJMoi({S~{;6!PU_Tr!$=W
zmvyj-<ccJap5^`wMsbew91r1n&ha9EQQXherO{l{pCG-!t*50%4A+8^ix;_C2av{c
z9~5X>9Jf0FfyQ&QD94|`t)`hrBKN5$;7MHR6#$aCk3rC-aIYwjc!|^7BT&7}ZK6XB
zsoc1y;7;QX?}YLSH>)jzxyHSrC0{ysa3I*ObKW@eDZjx*VDAj;7dIL{Gq~S#@KoL6
z`ceuolauv;!`s}ad^o(rt(gO17Ux_Ale=8|5pZ;mYvly$Y)&kp96$~i{4+>%xk;^2
z<Z;=*!sb4=gjNL)xEmz^=5xK*p?Juxq|<r@T+#%P7IKT|W_iTjpc4>9T<jJETFix*
z;Qlf9l@>}R+)z3}@r3J7shU!53T4#FxGU>m`IM8ZBr|9=)ShNM<=l`6m_Fx@SYi5t
zb4f)o72L7&@KnhyYYkl$_aChss=43p!EX&$NIm<KV`~6^#Wgts?pjWZv%6R*={+y^
zXlfrwha<fC<C`J#<uz{*ydOXOIvVfKdzPR$!tbF0?I@ooq7BD*cVAEj@P7@0E|8zQ
z2%#M3N76Re3I093`cCo}Xk8b?AD@RJm=9ZmB7{FQ5AaalM2}q<ucBf66hFjHkMwCi
zlMeWt;q^2YMDh!1OY$rqyB)Q2eE58roaZ;Sf!`>e^+he3U+xZv7x)sIkH+xpXd~z%
zKc61rSU%t~gmHXT4_L<YNiPs#0`E#wghYNZO=6Px#eX8EWZt`R{-45s%m)4vf2#+I
z%e;a{{#4#C6sBqXjA1CQ@KfRu%vJs}y_B!<Bj1BNoo`RuQP=rT(ZJo{*UQi)H~GS|
zFv;L!X;{6*f1%fOCcoe`EN}CZ>GZ-K{v;(zv-lRsu;G^DBYNXIyT^Z=f=ILZh5vvp
zhfk#pL@r-V8<BZ@2Au@D&#&$X(g(cvH?Yj-{b_sqA)mDf!4&Z2bX>BKPu-8EJ>q55
z&?0^lO)-l3{4`iT=4G_?Qo^&_5K|fddAtKg*Qb1M8X%tWODM-!&Ib<#@Hzi)6lh-X
zKaYXK3jRSjfR%hM?ZQ>@or+Ma=J(OYMh*X=9dIvs-W$a$erY`bwS2o|H0d=zVm*X!
z_&_?<^Ohf$58OL`2E9Dr^NYtqXs_d!d;`)Cd_El=`N+Rfq7&=+Rt7}zi9hr^bf5XK
zKIoDLzBnEDFMKZ?sKI)$>vXtx6pqo-Z<`S42h#1r(l7{j2m&q5cM3ziV7W`^OEZw&
z!tL>3*(0O}!V<@#>8!Ey&%%HcFm)07mBW*(Fq+Pq>=m*WLg^+fb%jHB!9XV}_6co#
zfZs3tK$~d?1m+xY9>StuVd*JEcsB3d)b4%`j(mm9!{OFX@Fujs@T~^SM+CRMD2@tV
z^eQ_hSm}UmfY7HSNCJhu%TYTn{C*T%CxluPSWXHbuR<3j6eABO4;E7UA%+k^y%D-l
zVJ#h#2ouhFB9v3YcABW479#EK5Ma2F(;d|a;RjmAo)HRXKo}|TbSCYrFeehVbHW@t
zK7C%Oi9n!H!f=|nL<{}$QM(|#8;V+t5Hc9>i$Vq^qGN?aw493*X1zj$@j}Q_2or=p
zW5AgxJU9+vl5qDF4VB441@%^n(EB-*mxTXlJ$6|bI~$~_!c1Dgr3smb5XBWCgwo1a
z1z`(3T@##7A*OWUpE?xRg$lZzZU}=yQM)PpVS$Sb;n(%>a9hYb1l=8BDJ9jjgeG&*
zPj`hG(L5fedxG>Qm}Uz$6FlVz33S3eS164}FnL0_3mo1TG)f2`2z))F$QND=fbgNv
zEE`3E@J0<`q0pQbcaH>PI@(esOrVuPvCyU#jd(0PSO}96;g$<@PXz7-bfv<Kzv*Er
z6VB6)?NgyJ3Z~D5gD*i-E<C1FJI{qC=h4s?!Vk@$s}SZ<s=ZP;HWh4Df@K5RR4rVk
zecu|P>3q~)3a93wcqPoh83-)57t#r+*TT3DfWHwobb#es;V3;X?}S_dEcW-puI_MO
zC)j8Q=!5Wyl35>x!hg_h^}_eFfcPZbNQ3UP(2Vjw4MJ<$efT0w9gWt16`Bu)&QXjc
z7u&?vF6gK2;vQNf?hxP8fr*{s#Pg`_5@%30e7Bf;9DetR&nfxoWEaP$0pTo$)BgNk
zaqB`L+{A|8P;(dmrhL}{aU)HbJjAWP!mp>elC~5MiIq!W;w_H*4e=fp`_nh-Cl=DF
zV1IGBF91ixo*PjFh+Th&hd}Y@9ymNM#{Pj03KCajpcX9JpH~AIBJNYd?<uh_4IZaO
zX(WW<;>Q<o5g``Qj_w&Tw-nrw;`iHtKPy^e5X?C-n-W#$#Wu4MXq4D40G83>z~f-K
zAgXA$Bu1P}`J0QPiZb=FqGu2Qablkc6!GFPJ3X-p;^5ctlqecMfICTicpkN6G2toV
zP7#khgUKav<rsAEW$~pMCaI$IICN>^n-TDPMci#e?W*|AOhkB1+!=}}(#6AF&@<P?
z`)&Z-5L=Ff`<r5C%EV=en|gxtmbmMI9m-76<sP_ii<fAkhWr9OPFdoPbqFzAbRU6Q
zj(BM}id->kCAjm%awmAYFFJPx%>(f>Z3gFyOBMnCP~7kkxB@ZK43k1}aSu3rB>L`v
zNs-v64uE2@<0H6zEM|0&;`u8P54`~5iFlYcA4^3uZF-i8^<4mbDz5wqq|d|*f3TH{
zdKm(JF4oe)x))-NKL8bCrvo6Z6l+=Ns>C>dL|84(z6fEBIKdmZm*Q`<RCpyuQr@;!
zG(LdvwRjM3O}qS!Xf(j#ThWK^?swv5nm4@{|M?a8I?-h(bRWbgZ4u!|@$?#WV!e2t
z)<mDg=d|<tSxobQu0eFAE%-0uiYDl%ucD0ha~ze0lyBOmEN&0LcI7Yi(Ct!M>ml5&
z+*b(?_C3nY^gTH#&C7srR$j<Qq%O+;I)mF)$qxZ=uQF#i0(Mgd&??(qSuKajKILH>
zg4wSe=LYu&lz;vWZV#mgrH?$7FQ)=<P?<(Yf4r0et?Ume+tZmFZ{>2@MLVnv?+mv-
zc4he%(D*9H(bj^WGExP+ztXh;!Xrvgnou8Ay3&1hOxc%S9RW&D0qz5pySn2$Jg#iM
z5GE&-A1F(IQW;3In;_*cbgUp)`8~}tLX>&5<rAu$x)ep2GKSK=r<6w;(E8I#``vsX
z!j<>3;4nh@+d9ykQO>4=gptaJqaZx1oT~)QIpy#F!qa(W6^-jrN;Bo`qm_x2KfS0-
z{RXvI<x|>;iBm?r24}p|DG5b_@-Ste5|zGxgC$A%FYPuaE0>=ES&H%-dlA?!DR0sl
z*vrb+M}SXNUZee$G^L6XRacZgUEt!Xa>+>`t|^ndqDWUx`w@Wa%8-lD-B9XjclD++
zgwA+nD7)PP%PnOMWlu7dRg+<PTX~vxxbG-8(GoCAInEVP+*Ni`)BEq9^4%XOvX#3%
z5O9w2`61wQm7_nyG*5Xt5xV=zdG!8!pnONCqw|%X>tOOwIg4gD1<K8%P!uV>jw9@1
zWm*v|A1edrq9|1w7Q=m+vXoXKPnF$hV0*62KLz0nW%&vD4|ssk!SGwH^jZgpHOfJ8
z0KQa)&<^Zt<()Bb_(tjBnKihnT|x8PdL<q;-2ck?vta*O`AHAX24w*Q&M(RiG`ISy
zoQfZa$sJXvDYLsxH6j_c?J5s?h<B*kgu%g1)y(FA?@~>nF4(QQNz;Tqs(KojoK)ZC
zpnsfI3#-BDqB>UxovZ4TeJ5!4s-9j))lGGulF#lc={LadQ+*r{w*9JD8W#_!ta)(Z
zp<4VH08dq~&M-Ns@}vzVFICH3z#UReTMZU(m2VJghgEBOpzu)*t3*%ws%rND?x)HK
zg^9mvgbl?J)x?u@w&JKN{d<IXOjSqkm;lwVqiA8Es{K{~kE?Fb7VinwE=qQvRK1{I
zn*^yEI)Xb`6-~MJ5Y?A=Xj7=lT#7)$RHx|x<0)0n3AFdL>K8iG5w7x~K95jc>;~N#
z)gVeyMylT5r<wnG)fXB&qf~#<@EWb+>3r5j)l}NBh*bqsOmV7XXTcV)8lVC&K{f6o
zEE847)4-jiy3h=|WR*AN|5H?N^uS$G-Te!kmsRR70HmtC+9LWi)mRbkuc+>lzpJWw
zuJo(0YpPka(UPvZ*8}+Ls`M}vH&opcfVippLW$)JRnlhwZ>b(y;VDyfir$d7RalYX
z{#X4s8Ejc9!)f%)UDfJu5z{@DgpM6$tBNT(l%t9Yhb~w3W-Bc7RR3<nmv&$E$4Ri*
zAE@%FFAG$imV&!bwU_RzN2;jPa9E^rmO@yp3Yr1a$EuRcC`wfZdhE+o4;quOs*aQ|
zs8Ln?g+{zoxsmXdY6!isYE^$d0LyFDxl7=DquNU+OWvyLUc%&^YVI@i;d{Gk+;?b2
zo$B}1h~k4P&;Z~^l{2MK>Q&|IQTwE-rFGM1Rq;v`4JwA7*DtD;h0uLf)xCpzM|F7+
z0Nd0j9N}rZI+6Ckcc^DkPIRYwBn@x7)PGQ3WVgECI23!-(_PRqCv~&O4DinCDRiX7
zMcr{Nq<hsrwgiov`nu<~;Z5z`2ZP!}-9UR)p6X?E*z2G=VJw31Qoo?X5Qo$Y<$!ss
zKXwK6Vf7Z;Yw}U|SO%f5`Z>kvr|#YaEdJ_csi+-M&!YMKQT0^%nbR?Kr`ZTFKs}9q
zff1<Q&Y*T&9U2O<6Y2)L4TzI!Pnxg=soh5d5v-mv1ObMr^Cp1wl)CRx)K0707b2!`
zwfY;FM5sp_063$*LPKVxdevdn&Z<Lc=5kK$6NlEGSG%-86jADNqfv`i_x%c!3+iFd
z5k-vp5lucXs$)9Xfsa)`rz6>M>S)@QidUCYS~EfI?Et@t>aAhGC#l!bdoo$w+zR(8
z>g?U<giGoQ$~RnA&*}xgsp=)=(50yjNvK^>Ck4XcRdrW)z^|#B(F!nKEj~oAT}Lo*
zdqdqNh)zG<RL6G)B14@*x9lzTig9Rmrg|dn$=z0e^#ti1b-fOVEcIX(G2K<WhQson
zI&uR7%~rpr?#fX|?13;>{g_Uh<f$**1n$1N<yDY9Q2Ww}frsjW|00S4bsU|ADpb!L
zPScr3Y6*UNAum$@O~+%3)h_K3_ha>6l(;QXAEh&%Pt<|!5lpGNDLE`tFL;aEQ}sWz
zjxASf!{G3_`mF`R7wVuP092?)yah|8I)L89Rq8f$MyFc6i;|2r>h5#~`lWhhJHYL)
z)M=E|tyPbwu6eEgrUAfr>XA!f`d&Sj-aB>b(0u4VsIPBF+#l87(}{q3^|$-cv!B#a
zKO^kV>fybBYfz7K1L+ra&|I|stNKF-3P;Un1%x{^b>9KEQ}Z94b=jryy$QFw?V5>S
z0NkS)<qR4p%|6;^bk+n?qS{3>h|VRrY7zvP?$unY1dW@<{S-{xHFIbVdO*{M)`=dP
ztZ2YJH7C{}rh}S;g>d1e*=R+x4{6j{5PEC8vS4yplRW`Z_-LM;K;f&g7c@ZWr{O+<
z&0mv68HOX8$gOaARI{)G4v%R9w*eTSsii}(ftoSY7soaK(B$)k#=#SwPHL9X%@U-U
zTmzF}P1kQ>5~68CC)YwXOLl=QOf!nk!JX3N6X3Kai8?4;6K5X|zY!XRFKo_erqk^e
zsrlnQXwGWf+~DGzrlB5@p4S|s9gir@sKbaiTJw&^w+osQn%c!^a2NrPlcpQp9<dsC
z54exh*r$RsUNiS+gqHCCF(qrVX)H<6eEA6KOPZlUwDWLTQ}sKlshSd+;-zWaJAmej
zX5wyeU)2N+fTwF3A0u2`*W8^0wi}wu?GVLHjf_U042^^i7vIvX3<WMz<4+5hJDT^y
zP|MN;IH42nYEIB@^gYcr1<0~B?v&xk(WDQf<@|lkuqgO_pqWhzh<uItd*B~xK7Rv5
zfoAbUm=<d84Mu-G(rD<n%te}j&M1mC3ur6rv8K-)1X`l`DuKf%noV&4lxjMafvilk
zqa4&vHC^e5$TQ7PH1L;e-tGnUbIp@~L_B{lG$M`86`Cme4l6YsDKTHANwxrAt@)+^
zMUAE}_5$TEHBHLF{YrD0QsK3luvdubJrWHFrcU#e&S-zoxK%*-Q8S4;s9qD;3}l})
z%eO%HS;O6ghXxIM5V|j#mh?kb`&Z2dLO5!N`60G#+W%TZxm{az3CbPXssaFaYDdxB
zV~_SK{o=$)yE+j7XYDVGP`GGgXrAe+&HjK0_iDG&+`&!T?Ky<*+P70t?9(RGTh~Jy
z`3r*a)JD<o6c1`M@1ZSTcCDKBunuVrl*IPdy3%=>!`jhpVB@1rriap3J9|7x{j^FP
z<dFMo1L>^N5$y~5;b4HaFKrnFYNv7#9@oZ%0B}O<{|vR0THk0CLE4t|1L|Py{&i?l
zh&GTi6rtLXWAGQIwfj5+{*?CAdq_`fo!+7qXSDlrVH&A5WTAFes~!cDbJ`?Ipq<yU
zG;Bp_wO`>WTC2W{4!WRy`5WSm(XQ}^<wb3`?l6hf&ODE><Fxm-K^L!GMW<#Gw6}^u
zov58X3NfW<E8AQ^^^#VVf)2i{Z9~TlQnlS_7bZ=6+5zsbXbqlS#u)7*=%Dva?O752
zGPK!lAiJe~HVWuW?V2YL-q!liH2IF!Jr(FIZ3b;!-PHz;funocp|q;b*6z!IWsWw!
z7Q$TZfB=O1K)Y@>0QuU;yD)jE-AbE~1=_-nfEQ{PQgZc?_O*R8$|9}k07S9Ymq*JU
zYvX8nTB6;qg5M`vytZ)TYdz^lj?c6bdS1)5EmDDduHBaczzeOV6?7Hak&)o8)IOna
zzDnDLPOVgHxnR_4wDB#`1uwPyX9!<uedmC)R{KSyw8LvHQ-HYNX!93=`>j@U1;RRQ
z2&FPVXdls5{zvT!I%ZR^{rfD~K51=I2tR8ZXkOBwT|_VMFWUG)aPd`pA`G?dy01y_
zv_rRX6HIpMDqBFeOZSo9$h&oK4nVj^=e>vTj2mBf|0$Htx{aMsxajg}>f)+<Pr1*%
zx}}*Ay6M6h)b{H-dA|D1Xg^L{{|9xMzrvB1Zt)~o9Ma9Cy>M?`=d+0Hu+AYF_CC51
zbZ`3V6g1WG(+$so$x)q@eqeS?H|;HO0lFXFqX^WgA47Ls=U;*^@`Nsm)>kKW@zk$D
zx*D2r1?#@#fHOqb+Wr-!p}Mt|=$|m%6Pkg9>sruZ!wB8g0tnCO=F;0BQs=fG+-G&w
z^h!LZ%ch;~^SZvX!4{?a@*iS~)<p;4o4BacIzbn!tE0qVoUZeDu*B=U9|4}AJ8~1k
zL|xl^s3qz8R^ta!@?@PiO(|1!z0<*cNjH4~ip#pO4zNkp{oS}y*2ND4%{AR8+7U|E
zwWRggb=|y9aCk%Kz7@qy-L~D(W#|%VhwhecR&#`wsk8h7hqrYFP0^$~I^Ull%+huF
z3J=*j#}qnMm!nIfefL~l?KAXAp02C~YWH=|zJ<*L-M40t=Idtt35O4Lqg}vOpev?#
zexa`Q7yusW>Rdruq${BV@g=(38U*u1_aE)FmFoJ@imFVPMfs4Yx-dGL{Y>Yt1)yAa
zqH%10uB)bZ=nLJ3dPu8u&cC8ds&#{l;G#z7MbogCx(z?T<dx2arlPgF>mxz)TIZrf
zuf5SF?gikjt~0GU-|2p`Lib+R^fDaQ=`vHmS+83}$?s3P5r3d(KI=Aa2d+WaV-s}t
zFS_?XgZryar~tR4{vJIr+w_5yrQEK6NMGy@{rE{}(@uRf9a`C?pG310XMO54;9c|!
zDMRL}??+4Rz4}DDuiW&1tpeO#KY|*1Kp#bGdJnz(A_zV8Q9r=spngFOqVTfo%T}R0
zq-W?TrMEt#JJ=5E6BfeMM_<+fcwhabDe&v3pPY#<_1EWRqd20!M7vZ+_217$Xvg&P
zoly(WJJCWiP+#!~oX7P~X<~XpAJ5<`JgL8S8?_+)_mq1N*0VGh4AI*UC87+~*U}Fi
z!}RN}0eDKk{1!-0>r-j#AY6Zoe)bumFQwg$Gx{NZ07U9r(#e3c`gy|;+ByBFc__~7
z_s|<LO5d3d<wfg%r77VBeSa0;G5Ugm09@2xc#I~+>N#5P$LUwwJrQ@je$6&CJ3;?!
zDT+k>H3e*v^!I5om8?J99&9Q4<+S>`q|c%}>Sg`#Y4DV)?>!JEX?i!>54)l-prPTa
zK3IhCnm+3{P^as|x}bJl-(eM~Z|Hw&3HVL@FMk7&q0hcT*@s(tmIjkd{ddRE-rM>?
zqd{{=|MEY$$kIz_=i{!vfpU2F^s8wVl&ue)09}s0`#Ti5dPhoq=IN!rz}?r^8zFq4
zcRm7KzMi3%*F$}~Fu)7+b+ln!sMpYY`H_B=M8xw~r2kAb#rl@MaQ|5U%^d_&qW?Go
zHc#{cv^QR=UpN9LW%_O}LHbl5_ycs$^e=q?DA#B7L#;ypX$mYW^}au%XRGuxo*<@b
z{eUGXYV=V}p?j&f(*fgG`r#MR>RNpS(n)stYyF^(Xww`0E)Ce;>W3VKi+6grcsP8o
zZ}kDSI(;)b8vH^32c6>nsIR2yLB0OMKCpe#%jq@!S)UsSlLozFBe=ilH#GqMRnJ$T
zy^e-qDtvd_3~eYczumB5AaFYjPgv;eI}Q8rOGo)GLrYqi?lxq9MKF5|X37XU8EPLQ
zd}l)#jZ7{EzkJ|b4IaY~#a_d%??K~cSW71$+zl<)0KU(V@(Pyw4Na)m4;Z@rgg`wE
ztLTqWcp8p(g7Bc>o3SwQGK^0F{E*%750QEs?$Ypn*szfjXFi4|v~2S=NPD46{0z%^
zMCfl&(Fk+Iu$XpnjvBVmVX|X}Ewl~@FdU+RCeSdcBLK$@U-qMR!jN+X)F%zqG>r-}
z%wB<(1sfI|MJ>dTKLWK-gWcE+_%Or6J}6EZ@~;4Y+OU!y)o?>Q+AWJPsA(VZjNvlv
z7DpPIeS+?+VH9=nIm7Nr2=u(6JMHyF8MdrPUql<G(_hKCV7S#1MT}wbEx<1tJbmCH
z)^N;*TAX2|FFH2faLrx~e1hS1GPn~Bos^(SGPr60Og0>@N0DMUMW-Gw8GgA8M4G{|
z6o4y+f9Uw!Rl^0EvtKhjqorWFp?VNPyKY!d@A4alCc(hnGz{fHonbh+34U)Gwo*DY
z(;#dH^=(71W;CGRF?2{pHOp{=j)>hgY@{C-+%x=XMGLbHLn(8WV~C>LE7vfMa`1VE
z>=vlqHw27>$peF-3rzA2k!w+VXeh5ot-#RaKB6cz^cW7ZM~0@fGgV}$szSWQ24)Ou
zj|~(4!rwoTml&3fL-mQ_CM^<54Q3PYWrmD$#Prm#bUHjeGx$sacez3S9Y~)W#!Nud
zUKqa8qP4=%b0lz;1`VCKt1^VrIfZJ&R&Ug53`Mlsd}+8Hfhb-Xd^&=<)^J*bPIztD
z-(D{9d_A>=J)u479}JsXq4;Q6Loe5QgI62aeln!0P<%Fw4MvC!h5^H2^2MN~JL;?9
z_$SmHjZbeQ(rw1!4sf;IxGoNW9YzN)nCvvRxCq=Xqw_MD>^4@qz+{iHA1%L}j9F(8
zzO!+ny$fhujK9;#Em!09Y`EWR9M%CeZpMT&DBO+xkAY^N@zy95`;C)ma(BSk;{w<`
zjJrm|#MAifU$7lCuKfs|m(gztibKXN6VVyoMlTvz4;!cd2}>X2#og#Hf8!P!=Z+Y=
zeq)F7s4<N0lVisAZm0zqci_aCJkXdI4B>I3TP?Ux7?=Ko2u~VoHX({2qZ1GAU}L*q
z5k-h`3gr<(jXq7`H_SL|J#eRtTj?16X=4o?wGB6#X}K6->~s*+XN;{9P>VE{l+gP2
ztZ@^aQaNYrK+QgH9I+HGqKw^oBE)E8G)-SG7*Eq?RE%*_B!anUoJ?8&SYyT>6mdp*
zM_9%iZ|k8;Fh)}{J<)hkjv~qEA)rV$_M@>Z#n_)VpD!83nJ6wBw|=29IMuku1Q%(>
z;oHG>#n}5TOs^ViP9utI#!s|um2S+m0&(3~ehlBw4dWTgc;7VM+YelZ@ry6obj#R|
ze$A9=97)@#w~ce=f#r^I`7*F%8P`OhxNH1CiIRK9T{I!fHa58jOM8y-YD+XN*BE;h
zou6lHNQd&iG43&H4~&>j;^{KZr8W0M<LX%mrofm<KaVan{zECoN5(yLmlYX3{SaEQ
zaU0Fv9~&>K;l9Lp>KSxTjLoj1C^e=8A<#18GD;{tHTIbT%V&0@K?7j9@kA10dv3gO
z8_E|(XWI3yFox13q|zv%pP*G4_s}0Vsx~@z0HDVB^aU(m8guBV?JMKVN^sX2Khp2v
zUK`WsmVa-2GYT!MGd>*%_y=PRZQXw~9=Zr!y)o%IEI%3Tt>|ZYpN;AL;jqED@q5(1
z7$fM^^jG8PPWVO~O<i))m~E!WWvFd8wWpc(4$}^I)OMQMtc8nRri2Q>cbjH91HQ*J
z;3a}_GIjh7&2~1W7*V*Go?k`0uBKL3q1$UpqyrCbrh$!rgU8)uE<|;o=?V?r`%RB1
zm;<K8w9DdQnnbT2Pm>=d#15JU`atJpT7MVr51GCXLE&v$N88PZP4A|{laFc3L|FQo
z{M}IVGd-bMrN8MRJtId<O(}73)O0@zCdW)$9@x>)08<YqC<9G@1%mCk=@>mECrpDW
zM}E?jL@W3p(@HwK5^Qp~1<MeVX9$F$rloYQE6miX2|S%Loul{4Y14%en1q{Rr+_8G
zG>jILXG}?DC?ZYW>6<)j%AzOcoJqBdp1<=ZqXYa#nSLAxX|!pN1f~~E>6B=RG2N$W
z%SBU4D%fI8>pH_E&Xm>xt%x_xoq?DVOwpTQl4uI(13;4L=RW~YHuWHr6q76gfJ>&D
zwg~OAiC+s{s;TZY0BNQyR~eqaE2bO+Xs(*xQj+|d$xfY^ZW5-!=DO)NWw&pbUeiyn
zZ<>6LB8m)CEp1EQGKKjAkZBs)0o=Du)|N22W9l~+J(FefI10|YrZ$5iyl0Y7)+gKK
zz8JzB)5LI?<eH)-(AgiDmK=bmd{Z?glpmTliwL;D#N<I)Xj<b8_m529%!07Uw1`#@
z#ipTjUp+Pr_!GDi)Auwrcw*u<BBoN4l5*^2rgL;Y>Z!@28$3NTO&b7QxoPed=$@Od
z6ZH$zg5J<o*iDb=h*G6#qBCr&Ol>a!SZzw10=61cIITEen%2`_pL%7A4+f&vltz2l
zuT3&qJ-;#a`idytnhyL1mUpIiHo)JTiq8RFXWD-Zx(}v5zXJZz^cxP|$?Hwy=sonw
z^vnlge>T~jXbZl<G?i}aFQyF}0Q_p2M+*f<^LYzu+swAXXzzCOK|0&H!)!Oe?@sg4
zchK!JcTR@i-RAxZc-mve@51olncF@Ex3ifSz~W-|qs<yub0i&F+-tr-D{D9Nh_$eE
zH;=N@uS)irv$nuyzj<{XiUa24RIquN4fG=MH22>GlY{1p4{+~g{&*0=L*|La;Py7p
ziG%yY<{81L`IwhuQ7iW~w=05)pSdZ`D*eraI>XZu^B5XskD6n4!^1Ii@*C6w%<ZD-
z`3p36pjFy&^Ww(roVofVY)+bQ(o+>=-uf0ru(|X{xCk---2l>1^I_VR4Kuf+A?cL)
zF0Fe{oBIqyE!=#$IT{*aez*plXUx;;K^AF#vjBjz=B>1bKW8432$S<>>tqHeTcgYa
zPC*)NzS<n77tCo}(9jt3rPr{zX#PwI<#==8EEEamF_cwLG)wP8mt<DZ-xf_ar-~?2
z%tPo)yJQZdS@>o1IM4ifP3?|!D)^e&I|AO*&3W0dxNZ(FN1Qjz=USk4(=6SFF32$J
z=|y?V+-oXondbao5&Ug)DxEpGW1e^fjm|P}TaFm+nk)Z;?w+}}8r0e5P8PV!F-Osc
zYp%JHmZW*+@9zM2-&{JX6l@R79(}-_Z(e#Bh==AlT2&R8Sr_OE&CZDk?U8w@CtMVn
zJGB6?*gQ5JG>^?o=b~Rq%x`}8jGy1cer^kD&&(w>wJkUAr&Zu{v-1pazA!gihFXQW
z!Uram=2w(st1>@fQB<2p&~d*S^AyVGzBGH$!H8GpZLi_4*8H^`fY;^)Hgv@s^L<*=
zy*2-R7o6|RCuu-<Z+`S0!mTrV+3DTz!TdWNoBn8Savcuq&By77nxD*Hvf$#gd4mz$
z4Q97O(0no9_k_t;^IY1FakP}u;iGMqL-eEa?G|GV-0!dy8Bp742~k70%d(B;47)9{
zlL6Rc`H%!hPL{4YaPMsSV?O-`)WuSN4gtGbHqz;by_T0WF1cBju0Y{#c|+@%eHQyY
zAog2WI?Qvx(wokrdRThUY|PWr;EUQpO9j1ry(~Bli)YEAr7dA^%lwY;aM+^l54ew|
zA{HL}Et8L+5l1W^b#$=lsO8d+KpeANs6?az7FT-u0xgnLz#q3Pppy<KED!0Z@<~ev
z8n}ZjVI5EeTP!qwhgjA*02gX8JEFV8EMLci?3CqK72u~Wukzq9-14IWofl#0OMk%Q
zjOAzAw~e%Hye+|-;;dz;9yI4HPZz?)dCPkmIioDoJP>fS#cMZ;3zpFdK*U%E<^q4w
za$OEjv6jTYpo_EYrEF8Y#WEY75-f*@!F{6T$v&7QS;}ZTCE0S8K`q6yya6VcEH`K>
zdf765JRI3mEl=qHbDE{sW&p2PHqt0{)uQ+f&Aw*o-xq$<EiPxFyKa&0L+yrT{c5n?
zv=k)+mtnD`BkWt2Bf-FBT5>5Df7>#AC%EreK2ky}%To6fqPT0>N`I%~o`s?P#B597
z=J1eXx46?*UaqBQCJ=d+Xd002TdsJ(=7D8fJRIg*g6Ic;4=o#L<x^nkI~y(vEq|v2
z@W|4FevemVNjeVq#g?!1W_)Zp^b#?ZSem~8*%M0x9q=x-42lGx%(9;bqNkQ)8PGkm
z*sZ^#EVp#K4&`%;$7r~CVfiA!MTI4|3cyOsqSGL)vSeKXu-Y=5j^@=^+66)P(lTv3
zYOgGrPtX^&mI!)&URx4-A>KEZQkty4wXCM3`a6q`Hn!he{+7T)on_e&MEJqd&pr))
zKU&Vyd4PIL@2)_6vM}_+#V?keIjDWLa7*CA(R#fZTx_$}o&$cnwQw*Z++nT%42L_d
zSq{+cvieY#Yq#|;894V?<*OicvTmpSA7^VCo%(aJT5iC^)%xZY{Oz^=@R*VlZr0`&
z*tlCihoZL6noWtk{nqOFusL9j8jC1Atct#9uc!3{%`y&J2OLJt%j!Za(?iy8=@%g0
zRu%1N9JXGe34xDwJN+)h*E*y*n(b%R(tzr3E#$#@#Ogu^$BtST+vqo-$E@*%Fb%L?
z8V+EfRe2pW$F1RXX5fUiADyx~Y2Cd7MUXY6Elh%~t|x&Hv96&%v>a-Uq2uvk))jgH
zPFeq1jhIeb`_rfuZfz!mF2Xv3mQQD_nUu+jw2l!F(^+d@oMpAk&sqOl3*dQcJ*`Ni
ztV!F@QPI}ET@l3v>tQ-S5o29LgV06ma(ZpWTFW+oEzVl@8J^;;ora*6U~TY5k!W52
zGm0c@#uEUNt;z!+OR=s|!}5}~g0_P$TYsQMSgO@{8xh*mtjCta#TDxxHYl%J!(GtA
zYgWlwxKFnR(Dv1J>mThvbHkdG1NS$r7xqG!Va4xE@Zeed27)cqdXn0E+nPd?qdV5U
zF)+!pI=iEG*ScK+-978+dURK|wdDrra;!-wfy?zAwd7lSiYLqptk>^=zR<e$1gsxf
zCryCQ$JU2o@KRz`eup5RSm*x>U8(gArKrlRl49VVTJKZ7>zVZj8l1|lXWRgIZrx7r
z!xz?d4188trA4S!TK`@EpH<ceD^aVq_M>xjHP&(V?!dpa>Wabr%IY{BHnrA%`yqU7
z?fN@N-&p^qyu@2;5bZ_2vmT;b<Gpq3DHL_qdJTg4U~Nyo8~tb<QH-MAnyiNIll2rW
zf<If$9w-{DGxoya7psc?s>D}oe*rZ|+sRdSkZ!XrqYUbHTVEDY?657S+51kL@Cm?O
zwuy8+e79}QO*Czf?TsfwbF$4`0-dw12kkYu*cQ-vR99OlP3!jBYG{4pW^4EXp4@G*
zbmV9s{;(uG?6*lbpg3S#Mvt|JtyutNY&~s*=`ZCSwB4YyB3`zH>8KsDO{4_5x6Sz(
zNDtfkHU*oH?K7Px^0jR#0jZzuGOY~!ZP)0R9!G4KXq9u+R(lTI$862N1t7pSnKp?7
zZR{%Oj@!Ol1NSFv`Vx3JY4h$$*@7Tje;T)gZGEXPLTnisU<<YR(x?<>OIwZNlr8K(
zAWqxfE{A2f?H--aj<B5`j^d2X6ag2Jww_ZE{aM@3^iz#<woCIMJa4mo0B4l#(gMUA
zZQJ3BKD=N{rlo0&?LXQZw_mjVn+s*EZA2!jaW+*kl<~HzR1^ue@+t@uZF}fPlu5Q8
zu^>&hEvGYkDYnscY9Q6-*#z)3+o~G~`--jqZ!o!P`{@QuuGxmTBbapCFO*@vZhO}S
zCO2$Olx4hW8+9F)8UM%8b;o60b#Z5wqq3~z*?aFrrj=>s$c7C|EAwqzSypP9)x#D+
z_7WKi0x})Q5JUk1K|nSlTZYIKL^dMt_w?8K+<VXYo^$W>8|R*L?(ebM47<R@QX5?d
z*7AnUCaQ)kvk7j7M7d4tb1=BVMns3ODs5^hQ(0xRu>^XnZ4#aUsj<0Bfq`0^jgGMJ
zrp>0qV5zfF<N*7YP5&my)!S^Pt$c$`U<(8qZ6f~j5^WOcdC+WQ9c)E!i%lc#t6FUW
zFM{>9&1+OV-Dacz1ha3q(NVsr!)DtUBsy)1$S1#J^TI4zT{aGsaKCHw>boG_HpeN6
z+GDdP8>H7}F(pX*Y-Tz@`fU!Z02#1xrm=fAo1M`bw6XE~>c<sU$taXRu-RD(kP(}~
zaac5JbBIbC$835n7#p{_Pz-ewHgoB9I%(q~!@5k_JRJ_sX`4|#eu0NJFDqd5jLlXP
zT90gMo`ix~o2{GBX~*~)8{>ucj6+ne;=ow_HCES=F-_-PofvEX^Fy5(|E$BH3*&#i
zkT}d3rEIt><B2YqdxY^UZH(O*qf~(B&KOAt%TY$wE{u6FKBri&Cu61pXkLsh^d|6T
zux(+e598OD(DG$G`W!5NjAe(=@@EWF$xi@d;wg|o#<ff2hXyfhUIsbF2(ZG^V8#}D
zcN}M2e+hyijF8=Eg)-RWg@-YI-+|6>#$qX!<OD+;iq=U+89n<W7>g)g6UES^!`^5{
z9tp%S-aCobX~qRVm>tXba~@2KWBh9aW8xVCJ$(--f#H~m!9>PyOc<5KsHH3R3}b@_
zT4x!r9Rkcb#)9oI?L5Pn2ZhOuIx_SE<3SHd3ZsKwB&m!KJAjhL2>ceE>5LwVJzZoB
zG=O9<7E?+jlkxOTfL&sAd;yd!MkB(Ae!uToZfz03svO3HI;=u2ql&_rR~ek0V9H~h
zq9j2+V}~oIQNVC;1?M$}JMG;I87*%EwTRJ4G570?h+_aRX1qd$IVFrU^k6Dw_|tuN
zgCQ=)oXQxUF%T$c>{0@{f)PWXjjCjLS?^=8im`_YP1TIfXQ85o@jC@^YZ-sjopzHk
zUID>6#y~4n++sXKiKTi*Ek$7)7%ne@G&0I)Gtk6{sRL<dtha?g3&VvHORbD#D(kz=
z;Ibj!#+XL|n|4O%1E}p_wDc_l?PNR(gr+-;SNyzwW?EaQoT-<QCc;|wG5$FQuzp4t
zd0PXFJG8OA$MC!amO)0h9<3pU=OUPUpV9sov=1|u{R7AcjN8vc?Fi!^x|~NDBTJxQ
zj4?=i!*Ryy8VF1<@b@pcsTe9ZpiD8oaf5-=40kJS{U0(mI)Z10v3E1<eZ+Xt9_nWq
zKRSZgF&{e(347)zm!Z&s`2jr&9GM?|0-IczH55%e%uJlbm@Bi`3j#-&+o=Y@jd@`|
zz}%S!DEx7h*}MjF9?W3M7kV<cj6uMQIs2j&Jl;&Z#W2{1*+&~dU#6}TgMQ44jcEBZ
zvjSmv0CRvoY!%21r7yAvF|+7;JjR@MhIlaZCptlNoT*m8m=NYSTc9wMnNESFFy^I;
zAmPl@5zugg`Pn%LoMeu#fj|Tkr<`zCL^8`ihQul6CHnA96f>1-Hlms82}r~+d+wlh
zntAauBx0EtsT?Ve=^F)O;+fHuQb}O`^esptb3W~mlbDgT>Svg*&|&nm%p@vJImcW@
zAAmW}T(Soml9^K4Azxtr6i?n^3e&9<tf|ajoB@-@w4;b&I&=44z+7Y|n_+MUvz9K$
zOy)8AT+k(EDn%o+m>$FEyv&^63bZTCMfAgDGezWM<}js`Xyr0<-iF?*%qDu2<uUI~
z!R&nIE!rU$FjqVRwDlU3NyiHcnVDY$ridva2k1KU`B%VG%=DsCh!SQVr2$Hrx%9>1
z8_d_JCZLR2Nok96=5I%!u!6adcAS+==QqJp#e9k0SJg}f<=ASNhv-uhwaj-u0m@Bg
z!JlBMWA1+mW4El#-4wB}XTGn&>>HSpo#1I?eknq$iTNCbo0^${a?H1d`8ypQZDp<@
z*Zwxs`vzKV%x1!FXFfysNC#6xhvhn%UH5@<hj}_5a@|bl5761e{GD<(z09&fboMc~
zw*aM|X`M@3f&pd$eNXQm(}s!33^I4q7YK%!^FF|G-)CO=A6moAm1iLFfH{{AfsHWx
zKY)d!%zZtuaE$pQ9c&wC8tG!2VD1Zm`bj3|Rg6tBb1C97&0I(+r-#ggaEBJoFjtc=
z|A_gbbtTq$mO0@7G&|OTJ0SL~A8TNf18b`z=H$rQ`6^6vV)Z@-Y-iTiM-XsfMa)O%
zVOIRdU~y$JuYnw4#lHcCZmgY~fbGtTa)jAOS=@C1^I%n0K){prB<+yBSa(@q@n+?B
zSz(P2>%C^!=F1ABaIYV$pd4uatPdG5CV&-1zGxup6N*F!vA!gy`xq;Ro?5}IvWoyc
z&YJRtX(6ni55u%jR@(>A8^${HIiSN?o6lqRCs-rvAa|05R}^kM*7yv@B3WZvild)m
z)ki~96l<*ng3&DX`)I|ma-IP8Y1T3?sE=jsrSgn8)*{*=$FpXs+%18XL9fU}R=Pc~
zlURJ()1G0iqvF1^EH>?s&#~rHP0e}MTzaG=vp$~(y%$)Q$3aq9QU66pQd!IZXi8%_
zJ_SwbEcartUS$19m46v5Q8{2TS?%P~USj1^93_jzri|HT)(?~!y}~kl2!U+YXRl%`
zhxIW%=W<yMR6uf-#ii2ZJk|@JqBEZ*{u*EftjFkeaE-N;?k#H}Yg01}E@l~;&|AV1
z(Se>))+%pw-e9@Y(U>w;qaEbSS^3w|s$iX=ijzu~BRL;ctV8~gt7g^EIkOs8d<U$k
zWxYYS?@d;cH&oQI!m}WLi#3mm@#|TM<RLb&axyX2Xk>jC4v8k#@3bjxW+~{lXkpcF
zg^E^|Gex&=v)pN?+QzD5VovR>-~8U&zruQaJsMrC`#(VYUDm7!VBM@BO569azAuEn
zURFphko#D%PeQt%RrEXz9ANSHL(e@{>S~M)vSMh{J;Yj{3zYk;xH%xhtV1V&@_^+}
z4&MkXaXG+7S*jnQVT{$h7y{!gPwO`DOt4lz4zx+uXKmn_Vrj`eo@PCq0?b3!VIAf<
z!{V%k-bbwY)gZI1Km$7M*o{sQuxFbiAmG5Rnt+9lYzN9zIk69UK(8~~D-SF#><&K&
z9A>XEg430~n&MMO*l)f^8x}YA?-$VP&JLw0{!w<=KWKTdS@bIRWY2#JonCAM{Vv|@
zSc>rbuzl<S>dT)0FNh!8@)h*@v$-NHb^tp$6zT)nu~`rgVk_#=I>vtc4vYzA8~rK|
ztgx0&gFlS@-WG6#vy%%Tc7pvCecSOQ``{QBG=kkqakxnK>Nu!7#coK1MN#Z6k7Gfi
z+3ArOi(x<b7-Of|nH-Q<b_oTt;@F?FFqX*PcM|H7*zZ%2>kNC@VkkPx{)VES=h*kH
zb1`_HZ7K$9GJA&Nofp^<{g6*#<1)ZIjNMA!MH+i21rE~L?r(wRBKsUoC4)UiB@&tJ
zg<pZ?68jDhKV%mBqdma9%#K?Dlq+n*Utq~*hkXgT9Ci}<D7oyvS^<5PZGMO9p7Pjn
zo@nN?_tasqfZa_Ip=;~|lmahg*OI|S?8m8;>^i%Fy!vAHe2O)fu$8|-MJaoCG6Zh0
z*JVLd8T(EVFw5Dcw;)%+X3%4)lFfeyq>BA<4LYmYO^?Hv8g}i|RCiI!&dGt`P4-#(
zG)Nsg^n2*N#a`hKh4t(PdXYD<Wwg(4WVgSBRulWO0b|YVKi&jq3;PhA;caF2z7KMn
z-9QJG+St!i%($H$v;-D*uw4&8pp)JAIrQFP`@9W%yV(DWp%0_qWk-`+-_6b>C!>eG
zAPn-o?D;9s)W=S30&72ehDtdH*lQlb!h7sr)MyQ||EdGa5Ib6r)_wN!1WbFF9l8ku
z57_neOdnytz5^_yY&ku0#@M|cP&Cf2#xru^1Y1I9<gAnISLpE86#EUzT1>O=P)zb6
z`w{J>X4s2!FpEd*chez1%g&~BgB|C1Er>m5=~55}&WpdnCP&VZ0I)c5zN0;{Gl#>(
zv|Tt|^h`g@vAhN1${B0~*b&Yb6sdFL%$$O_yOk3_PkK*ISUYCn#kn_zL2nM%9WXwe
zQW*q&IWFWI`Ei^mp5@PJae_bq=Q<Vb2Xa393NS&OMA|PM<D~Dz41+mR+P)m;1f0NF
z2<P%Q01M>=HNwI$&h9a=gmX?%obm+6`gk;qI>~v7uDJ+~9qpSVIi>HSb&4~Z2Ei!K
z=GP$+%?YGHat!At`4Oi%^ExpW%XyUo$#I<C%|MIitfGB$0%z%ebsn4#Jb;qK(e%Q!
zGo0CHVDDMZ8mb68$N8R0cFuF!teF5!=7iF1c!6{46y#GlzMjBN<rLFnDvfjJEvQfD
z<Y}-L7dh_rV9DToOBFDgoG&_neTk!@&MeMX0Z?(7lSt`?E1b|x(3H*jsu$upoYi#A
z<#P1&eZ;GrL#-froZ$_$gU#nWPp(-3r<n@Vu5s+su+D{?9x9zF;&eKob)9p~9u^jJ
z!sr8QC7j18gHy_3NMYy=&a&sxS;q0CgjYFd>3=sKXD-EfDmho^MO?*^JHpUv&I76g
zsNt|Fpj*rNd<%UT{w8NVJ+|sNJ@13(7H0!Rqv|;|otSR}X9b;5Z{%<&DcZ#O(+z0N
z98EY_S~zPc=ibUGd=t~Y&G~Z_;%%IxGMLuR*+(1T4$jIJh<9?bUWJA`oR|c#ba9Ln
zGP%on!<kM!c5_aX!XD1RW8mrKL<+#u#~G(Bb3bP@y`={@OB-PK5QjtAo%@_cbI}^+
ztf!TIz&S7pv=I)w6Jw*CffEoP<1pWYz2ls_E5I_r*-O#QNzMlHA*VPY<hxFDF3|Bm
z>qCx1C+H04_OAea#NpD*ca~$Me=oG-E_)Z)_S}*cn1us3>?DXI_kR_DapE4Kn7%W2
z5&1tZT=6vs9Oh>I4!y42TQ{%>N4Oa+7<1!(N?}-cZVd%Ej&hwS_2R+ZL#IkTt=t#r
zyrLI(5nXfM+|v{<^Wn~^1o7qWTmemf+)rKxnm_lqe<2aTRnUVbkh{Jbnu53ilt(?r
zU8BKRFn11R(vNf7s0cZPyP0n7Q0~lbjD>MOV1a~leKvvR1otpKf=_a-^H!r7!3}&J
zgOS|LG^bPC4YW6p;x49YglKLCz1U;8JL$1?n)?bR)ML4;XijllKdK6d=c=~D!UXQm
zw5LhruA(nDC2>EO!@@J%4Rk@A<$6=t{~UKCz0l8d3#gnXnY+$PwJR66)jxtKg}Z|`
z^QqilmP2nE*XKCo)46Bkpy?uaisE}2+{d)AB9r?e1<o&VKm8q=vbbzY<X`6Yu)%VL
z`^;*LWpkTp&zi&iybNQxT;b<Xbd|d{AL4mj<CmCcKKJzys=F`XzI6;d*SLGvW3Z6B
z_+yYF?iW<|aGkqu9B9Q{-#39>!kxT@u~P0&@o3%PF8CQL%DBENpp<iYn?b6$`wzhE
zYHr5@D6HX@9>tVuxi3XQ?k4^h6tl16&ixi+x41i)^uKHM+yx9sG;p7$y;vi6;w$hp
zaiggOyP4ZfMI0^M5DJpEav$vh%WdxNS73e{cS-^5cCJtX@ec0VRT%5!?x9D+9q!%F
zz|zJ2APsVNxfhP0vzxo>SwQ!2_mNlB%Pk9}y>cJ-=06zh=XN$hVt||31hjkHq!3^a
za_bI3Vu<VeC9Js5eLov4!`$DtW9$Jpn2x88aHr_H80B^}L;V<cHSJW!x%0@~nBabR
z0<B5z$v-gPDefc{FHduSrjX}D?mrR;SZBDaDZTTEduJSEmYe$%(Cm1>Q8>z;x92Q~
z1FwThnjLve%BMQ<7{8(A%saOWR=DuY%OP->$CF~rmG{%{u<!`aHx6KKyeFv=%$@gD
z2F8x^WaP4Y@N5JS@Z>#7IWaFQ?>E{{d-HBOgZS_s`woM?ytnBns2{H;8!dm{$G>9{
z0(cutFeZ>U-3SuITSSlWW4s?<#8@z|kiN%rocA-;oQ3etZN*q9@5^`43ghvqs6Ct~
z_yn9Mc#~Ahagz6ED_Rje>%V7!7RlpN-1rpFYJkEh-a~raMe{Pg!DM21uahT!npg2(
zxP;eC*@-yb+<74Jysu6HJApUQ3{8nV0|nNTcp93^8J@>0Sf{f*e~MS1<MC)CdY-p(
z3cpAS&nF$?sl2t;SjeaGZc!0OI&bVAcrNn3`yU1~c+b8Km`t9o9cy`sH{u2CEZ!jt
z$YtKmyC7G1CaTTI=4GFQ`W)U`a)xtxE9tbuRo?HE49nwbC<B_$<I)ztfcNAQXt>6E
znRb$eJnx4T3N7M&`YgzGUgN(QEaq)YhQTE~SK8H-@+9O*-QX#<W2}s~bw5li=WXSp
zRl$4tX_!{YJ3)KTDqbg*0af#ysoc4SS4M%ETHeAJq5dXM90q|p-gA2~`&+yvO~9<@
zc?D1wr-7GC!Iwr}JKauAJpVHw%{*IjrdxPx*I}ZqyvO~4cAHm95sEh6d>3eH=Y2^9
ztR1}a=V4PPuc-j!4sYXYkn7^Dp?&3DUiQy`?&kF}ptpy2@E%xtd9fF;Kz+Pr*y30h
z_VXerem%f@Z!OU7@m5ZP4D#~nZXDwA=uW@S+cpHyVO|b}Vjl2DY1Kw}@iNGb@`|Y#
zX^i(*9LC0ZcBi3fg10smdM9~a--Ar?!j6MX^Li-$^^jLahks^xUKAU%KH~Mii22U)
zQi}m&$3I609_{&>GN3u|%P8gH$ai}Nf=>La6ee}%e{uoDg`c|&lR3;kmJi~}-%5L)
zBmCz^0qVxz{4ZMW{Ams3j`CMg<%0+R>Kg#_<j>Nh!Hch@oQ1cQZ+jd(KKzG2K)o;j
zb~%V2|MoYqDUfe#k5&*rfu6m`_*;&nGnoHlIaD0ypQMyu2!Ck;#6$UP@=e3|0Xpan
z=kF3>5-0fHlsP=fSM@<*1pg8x1|s=mT>v}9SJ49|if>(23Z7{G0?K{F@Sop;sh#G3
zOF_9<e)r$Nj^pnQ2TMFZs~a#0{4pv9Oyt{r1!I!<iZ1|jhHn>zML5fUhy1E@{C;v+
z&+|v=*_q5wq$1M`e7jAMOW{|O*PhBZH~}+_|CIF;NTl=sh(+&3e%C^@GWan<U}y5r
zj{xQp|Hl~!X7N9zxX@+(M-;rg!e2w3+5BJjKrV-Wln(Xg^24bZ_bQ)ngfV&i2T#JZ
zeE!-Y%&dU#*#+op{C7S_tB}9<2e1_Jzdvh*rtAFaa-bFSdp?E25`GTFx=Q)WsS^4I
z|0X^9%lNTJF;>o>Pl<sFegb)CmHbJ1B3AK5R9aHa-%F<?YWTkd!KPY%@8cM|$)BLe
zZymqyZ;ajI-=r$~dj9qlsBPfC|0I2NqmiF!2ka*PpLC+SnZJ#;DJ}d16n$*v_as5n
zZT@~|=xyT%?gMG(J2wEdga45ba-IA|6A-w=SIeQWi=RlT<hy)JA3D4FU;GKu!|!7Q
zrI(+02&VP%SswwqpWn1={+zcK4)9BJF?f&P^akVy`R_f0$qezYrGn=^e-&Mp!~EYJ
z0P}!f^Z@Ed`1N07GNb$=4O$cYL*!>n@^4rBJ$;yA{m35bAMqcfH1#Zh<xLPf0p}((
z*bAN{-_$|y;W2<Y3f`pWs*_+r8d}bR<&j`<5nR2EU*fPpISlQtg5Ce!RDvfdgy|+|
zr8Jwn;3N+yM+F1qxOoU{Lm}WP@c$evUIJHZ3aGarunkuD2+n%KP+!3h1(=ebpxTTv
ze?bwwHv<G?FQ64Dh^4)EkYG3ipvMH;3o#Zfs30HUxWI=Z-64V>e#0a}1$FTl3lrFq
zHyJM2Or<v`1QX;DoD|46z_bWKV5t>?k%AlZ&^#r0(+tok!S8NpMGGYKfQk`3OHqQ;
z0tVGF#R|^#!u&Wv1^w9Zg5B5AN)Xi06Dd&;aRr@8g4$S2^o-zLs?a(sNGFfroIpnp
z%kzTePh!=Q1$SeBc|p+5d<->=DT0^UU~sBnZ6SKo1eJflrgTB*GmyWCFGB-6L-3*k
z*qMUSpD=bwF#Im`W(j0t7`rS;)`MITcn?D$Td+os#mf==>3d{_)#ee@<qOVjhV2Cc
zU#i%-Ch#yqO`$-385l(ZXW9&17tA>TQY`p35f~+cfBuDBso-OBKyC<{GGShspgkY0
zazPrUA1efR(*af~`0Z1GRSC|%4!LSU2*rDA1oCnS)C#_})`RD!U=JNbs1vXbVqF>p
zE%aV)6uiG5tW5&`CA69a@!c3}5j;*`>~9t1H-Ow0RJ{e5Hi2Rr6t)ZgpyybJ;QVP=
z(J2^M3YI&9b@Wv065OX3>Ro{YEnv4G>kKe^1Ydna4~t&Gkx)qV36`W_1^WdrKL?lr
z!GbL??Vg~W7Hd$j^;<0KkRbRVSndnTpN9Ofpn*0H4+ID4;W#2#>Wi^aLF6NhjR}5h
zgH7Xtg|uUz5DaX>a!m?sUjpWoV2I9VP79vcPcQ3-f>mdra7MtSv!9OyyXZYPE9j)d
zh<3u@Zs@fa&Mv^1gYf$#pg9WfTn3DjFoh2oXW>J7Ke`Bu=+xz5p=~pWtMIiP2pkdC
zo&k%S@G3=++=UyLz|f<@^i61a2sh#iwJ!7&3MkF%CFIV9LT}-V6y@|0s>pxw6}HD>
z7JkA!I%DfEe2EGo1B63=Vk}VD{VW86gs14h!ZG2zTFgFJIB^Rs$AufHaz8}q8Gu%(
z@H&0jAxxNJi&nUB@O9`rAuOS?2<u7V@=^3g2yfj(Gg5eno=2yIEtKJm65fh}-e_UQ
zdQ2upI7_8Cr-i{(uo5eL{A<X?2`{TK7B5^ykHZAvkCbUl6bh;8CQ10mZD=|pEM1M(
zS>adJU^yqOq3Gdxq1+CNlC8ogA3@@Ra78L6lOpsu1c_APH(c<f3BP{}R-_Aks6hOp
zaG5PMWe8uZLMuzS`YXs?7Ve}##T8-9JFqERn0+2{Il{lHfRZb0F9W$M{PtVu%@Z!B
zV(5I~c6u)s2>&_=uxmoAA6;{W!j*iGB4OJHAlHR^<DjBgct-&F5@A3wKud+|pM&5H
z;SvgalnHAo?pH2+tqfLF2*3RAGZ(^baj>^a_zVMb)k64SxYdNq$eF4Yo^6K0o5DnT
zjMfPQ-hkXKVUE=Sw$%%Tl$2}`T0Q}5qj0AK2AhP>wF0JDxGWB1Ey8PT$hQjjdV%G(
z@UeAZX%k+i+<Lq4gZE%ehj9HkNT+beFjU+Ts%YcTC2Y@w6?cU$SrF(JmQl51k1&-U
zQoTZF5hdIDgd3<PuwVE~I#dh@<-Y**p3pB6dIyD*rI_}Ru>Ttf-WPt_2o=M^Sr1@8
z5Q^y0G9n!HM{87Ak&4!s@Rv!Tj0;!OJ7Gdt_B6&Og?9qcni5u=2j;Z!ozv)iD9o8h
z!P*(&?ipY|63(R%?5yyGam>(8bc3Rv_M$U|Q12iLT7Z_LXw^ovoJ8J>VWG2VT{MV`
z=*WLwqv-q=u(*mo96;w0QDY8NxQUdsB<`YjzJ}aU(dQIX@DL65fOv}T;w5BV=q1`g
zUr_cIh0-(7N900>rhP@;RcQH%4m<}Kf6*IsXgWZ|55TeoikucgMUcpW0?5Zi`vzfe
zuqgimI**I;eu7+xXd8XIDO{ABfK@*sT5=L{Cq?hFF%}{E^l9je6y=U$%z8@n5(9!!
zqT)}m2+<-7eW4{rG!Y1%(;}NpsE8G9-HNd|(Qki4Q@m*RHM9~$C!T_#iK0(uK$1jJ
z<gc9(wb8!xtSF`vDCa~QC|q)0w0Ip*l0|zcuyR3Upa?^X=%Z60saDb7b&yCCt)aJW
zy6B|}U|$q{o&(!5M7kFsktuph2<%Iu4gJuRB`Tt7q06Ea+MHhzc~UwrTXf<jXvz`g
zQ_><=<n}9Oe^nIe1ig78r-u;F7hNE?x<K^Gf9GICPf*E8p~#y12Y8A^-v32LMD}zc
z7mG^CPb?8VNpZ?j(Gz(9y&-D90#YV=Ljb{Y(eqURtq|E~L!eSL#{pJUiQX>9ShdL8
z0mjsbo{hu|YejESYUie?{}B|`iI&iBe@i4cV1o6c3M)Ny8$|XL;A|AVP1kyp=uO&B
zH;djU2eU<VW*4wqMQvx$x-F{D0$Q6$Ly4_+(KuaK9iqSgs~8cz`yuq+5t(Q^-6fLJ
zQ|qp%Cj#Q#qSdsW?h%!AKz*-B`W7_wiN1q=+<2momH>M|^luS(?uoj#Vrqk;@_a19
zkSKBwI`50*`$2|9L31GRK(sy$=8uTpRYS$7XaS}5#zg)_7#kPaQ;p(;Xb)X%lOjtG
zI;TWNI%GO6%3ThWhoZezATy$;!YNo}C%#O<2z&ANjj+u@{H8b5JBs&FSjtIUJP1~2
z@u#%SbP;c%BKX5%zZM9%idWE%<A`|vzmRhi2Q|YAcX3b|)E^Z~XtU}e{(-7?J;m3y
zL)=SzkcGwb7T?<rIUjLoFunhL#mn|!&`<16!9;&?M+PJU#F=S83lt~40hl2120a9i
ziBD1hELd#!J*IYC{OKzY2oW!(AV{cqdm>Q6#Q)OypKx(FW%o{qd#HNhq}Y|V(-Gpo
z-T`N%_z>MAr^HFL+SVv>^D1CRi|y8eHAXz<3((WzwsmO5ifzeJj1#-2V21Hx$K9|g
zLA)gsV~OHdXgi%GE~H$|8F7XX(>^Osp#ufy#9OyQ?!368641%wVaoko5ciRPk|JL4
z9IQwc+fbS|%_=@cr{dDZZ>gd8qPXZCU}uP5ItZ9d@y;MfToT(*94kv)@-@_779UZg
z^NKifHx@Bl%s&U19I-<p#&X3?bRk_8udjtbp4cr4t$cAt9>5C3TRk9mO}vdBDTQJM
zZKsRG){k!h=DOHF0?lIa$m>8W5vy&0Rx19Sg&E!u4}ONuGV#7E5G)t_svuAyPC5Y<
zmEwc+QHm<@TT-x8i;r%GT#Y#SIe^uQ$5&wXH^p1%0<IHpr@tJyC0@J`0`+1+1q2$z
z;nr(FYZOZ)=xq}3rMGaiIGqYTTf}QFVysmhGXTBq;x}ls+93`nuccG`!hOi!5nEYU
zt}gL%A8_6kpLrK7-QoapDtp8ywt@7D<wdZfPwZX*fqwB^igOHzkJe!9o;c5sg0+KU
zu@O8&VqZF*b6@-|IiADfeJ!x!f%x!KnA3=OpAuwLtcrocG4az0Amd^$E6kn{|Bpge
zlj0fLCQgaJtOLrl`1NS8JQRO33xzY{^>lppk@)CGfSwh9H;a~?WK+tbH*n)g+?;^z
zAhE55grnr*D`+`M<Sg(wOVYHEaFGPP0MNq{7aO!(B@Eh)9Fb_~spTdao$vQrz_ZpC
zdT)A43M<g*C9yYwcuRhyO{0%wa1!(Mm8_(T+fVYf6HxpmPMIJ9lKDbRB2bca5Ni-5
zsjY;-F-af!Ou>=>dcGZ(2q`fTB3bT*d4@`c={p%=l9z8lU$~_5Ghm*OEV25b_oU=Q
z0St|h?4(mZk&-TY`=64`r<IA4%=G|kwB#MSr(-1CaM*NO;uQhTSjlbL8pTOcu0ln;
z<hcjHPLMdv!-^zI3d=!~By~qHc1H4^9mLN{dR{~8oW!{VW}lbn4$w9+S+e_m%;|z8
zn39bt68GIOCRGxi0-iL<Q}F;zm%M%uV;3cx_5vnD^6oGMG9|(H(7Gh~h_;DYlHYEl
zby@ORBF3&r7=J)KThd91svOD687Rt?TwVi|d`ZbM%(_4l{0n(9*Cfy9g0)aG6^6+a
zN#;_n<+_Ab3eaLn%Q~QyNS?oru~NyT4NSWs8FGiFGRaR=2v9EhSOoD3$?J_+nM#R6
z15{K=4%3BHE$JY4u14}Ih23i<KTiYtrewu_kUB}<2lOW@w<I4-f~Q_`Iv;2a5+4du
zHA<#`hlx#+_m;!%X31V2##$tyl$dLkH2sUQ+mbxGWZNWH8iCy|xmJ#ec1RA=ex_4$
z`yG%wl5@{Nyh|ee9^|g%9=Va-l6#dPJ(3l-K&-uzZ|P~-Cs{<PqJGKF|Dkt4Qt|;>
z_atldFl|tBkDS>dNk3Hp+?V{*jn=T_Ln`KcAo-czsUwn@09ZIGVV3}GOtLZ!lNgu$
zOCHdK#D!eqNy)&U5SWsP$kCmac(_2|p;fY015Gm$?^gl(NYb_nty#$&19<GD-YQ_*
zOFybd%RyR2H=Lui_ybJTNxGF@AkNY`w9R&rik=2JEbTdfAI(+jO2-zCNas?f$W6M6
z$|BvR`)HeeRBA(+We@41^#Jpfezky{VK3<o+8cUHbtP!|NK+_8;45AE87AW=-P!?A
zf9aVjs0ffc;r+KTP`a@cBuLtL6q=4n#SQpHf~Dz~0D4@y{1XU-NbgYqI8=&Hkp-`?
zX4C@tq_m!nR7FSwFG5|Ubiq#`r=*#OF%~0zWgo;&OE>WW87tj*23T>@_G;*fm&#bM
zIzhV19xRE{C`zj*NjEHnf-};DU<jO*%J)FvoOGC;b?2q)DR7!Bt+|YuT#$xXsp36F
z`YSoHsZt}o%+jR490p9fw3%WP7p2z@Vk|@Y6UE>%r4_$m?2_~tRm){bU!<huWvMqk
z>90tG$eGKQendf#9O=*VKysyXe*(EGjU9qqo^+auoARaC^I=7SR3Y_ScbsAUfd{!_
z>0AGRr9`@oys1*@x<V}L4XOA#T4mBca{J1q`G3KP3TZbjTBS6We$FcCVG^j8dW54@
zBdt9R&RS_(FHE{AJ+%;Hb<*Ti*m+C3k`ngy(lYvrK!bGNFBof-K5OlVM3dBo?t*6N
zhg`t4NY_wZNUL;C9~SSn)Z7P&Ht8=^zSS<3)B~nNy2~3Zozl7F9^a9ELXLlz^j`zS
z?@C9O!_aQ&i7znS9%&=x0eYnc<h}JtpIQvCe(CdcCl5%q_|stAQqs^5Va=el<q8Ie
zqz_g@#eJ##JCI>%4<F=#bpIU4k4RfOK}MyAmVk^&f2Mn3T>8O#Sdt0pv7G>$lv-+m
zG9@kchiTJNzjTN{lon8~dq(<k5)?g>o>>DjD~)=Z%5m*vsc)lcFZ=fq<Q-%)bX>_%
zwvsBGon$R9f;h{{;(+EV`=<e#j>!6+0jHbH!bYdNtmSKvqq6!1n5c)WM}wB9ER9N4
zykx_48GFlgVrcM@)ue*OSGN5mT7I%q8T8pkf7#4D*cKoYI07_K_RcRbI7k+`4T8sH
zFaH6FVA(7cs~(rlp+edaS>9fdP}%5R%sx!^dKA#YWgT=L{)Fstijkg_S!r_+A^T(;
zn2|Eaoe(%Bi`SwRC0k4x=xEvAX<%AoWQCL$J1rZl1BsP!t^qVo_9@j0#>?7i!;>J3
zqm5RgOzQ`ml4L)`Ld6-`WHMT3Wt}x>os)_F#w5<my6I7yEE@^Ns$GzIP#Ql)HblAV
zR9RUHP|{?ZsP-aVRuB#Gi&ohn<=ir4*PcN$Q<n8ST9;&Rl24W;yGO70%d#K6Vbc|v
z_n!dGmIcu(JV*A-1F+=EvR^>wRar<p#PehvDvHUMB~gT-Kvqp9!q;T=v|B8cby0A%
zNESf#)z@X4`~h7ovldazs6=*b2PRr7`)eHrZ^-6wAW<gUoDBJLna=<;Rmi@euvDci
zDiZ5dC7XT;Dyn67mP28Uj6DqTTG<?W-QARp8=$F9R#X7FTe5?W5U7{=%!8r^nVQZ3
zG|KEL!P+GI#Y!*FX4!(b(QJ`zqpwA@${yPRa$B~WuKYHclwS7jvX^&YojYWb3+U{W
zJ@^8xJF+FTCF_!%rg+j_*~R$)>y?%50!yE4TQFGqWrxC{cR+To3$1&y!CPP%lr3(D
z+>lJIumbzOY&WF?hh<A>oA^N1{tx6wWa~X4I4W~7qBSNvNJahQvTv7SfhJ^MF2Kr6
z%J#m5X-~=CcmS4Znd4P-K9m{gM8b@$XC(w4$yU;?cviNW&Trev57HLjUj7pwat?Bf
ziauNHD0io#04KSWw#CkJ^`9`tMV?6>&tZA69mZVcl^+81h}@C^;wG1|Fy=0I{Rh?`
zmH&uT;X)7jg-MKg%FFIz5?*qq0V=%Z&4B>(k*}tj0$=&ll$-aH?|lP`{N=t#4_g-o
z$c0gm50pDDg?x~_ixPmx<fW642$t7VapZCNr*5z!ME(&u@S$=cIe}sF(>Kuym#4jg
z)(QDsstZ3Uul*L-5pp*lSP?1rm_X+#IX4j~QSzO%y^NM?$bX5EN08TOJuT<c8O2!n
zt7bIg<k_xh#mnbY&^|%_B|U-@<=3g0AW7~?A)GVvjZ`&pR<5c9IVa!sEym8v2U~!h
zEZ28I{RR1rA7Fiod>@&eD(|9Vf;4&D*APgTyRHWGMR^=m(PUWV=jKBqQ$F``$X}A%
zy#R?UxncmTcUhiBXW*{LH&B8$TORxxU~=R?kOz<}zd<GMSLOXquqjXOr~`JsJhTm9
z1@d)1Si@^_A#HRD<pK)y70H!t5Wg<3`wOj7c}6{2H{_pvNw-Cryp_`8<#Kl_@~V)p
zJPZ|;^1oQ%sgi&38zidbd;P&uBln@rL9Kirg;H+HJLZF>PM&uGhTf9D#Dv0nx&0_m
z8suJn@exd`hK`1}%EOm}+?I=PfTK<B_5rMJmn(jUbceiwHb0&6zH88WN3Q(_3cBPk
zzX_1L^8Fiu+%1pZ3ArA**97Ex<qbU`eey;BgLuEZgz7j3<YTm*yeDT<(cGZ?FdZNo
zk|$XyUT|N2kaqaPa^nP4Jdpd-^Jzq$MdvI><v-AMG$y}bg5bFPV@gX*$OovxY*PO8
zL1>zii-=`fe%=Et59JwDMLZ*4F9Gx;dEiG_ms$B=y8vdV7^kq8z2fD^Anu@eHip77
zj*71-D(j@M(EG<(kxqV$i((g*IUH65{SCWa6)wrZKBA~8fI>F~V;QV)S3LhaT1ORM
z`~`6j#a4RxdMZAd58|bG;yT2=6+gH_laFE@RSozm{-oWZpJLO0*))ayN&0qXfFhs5
zs)35jm!UpL5l$ZAF~#Gbg9IyT>E1Z5s3DIjM6se4@}Y{G?_n%V@lOn_2v>wqrR535
zDymI6sZh0}6`^=y7A%p9P4sj;rP#uSO;L)Py&%zw63R2iDE8s4Yh8F+vD_Ivv5Jk9
zsE<>upm<EY;sbxoH$kzX5v>b~9p8hbD86#RL{k+$t<aRA5Dh|orXrOt>Pw1megtT?
zVh;r-aujQ*WGYvY^)G&y5=BHL^xjZx`~oaxikB%7P_EcOSFyE1@g@C0m5PIOe5*>~
z^aUiU6(-vM)+h!aqE)MqQWUICar=F6-ctDbVJ+(we)RThP?Xxiv_^&V9q4URd`MsH
zXi-G?KvS#YKpLiWTj3jmC23QfqTNfoLQaW*PK6)6VDDHJ=P9t*rTEMhXm=Hn97uF4
zg8zklkHU>suUGMn9VGe{edHJqD8~N_-YE(KF*c|eeIA`dibP6&-dC)n(C4sXhTP)^
z3QxL_Mig&lU~E*85{}lGV&Y$bjVr>nFmyuk*&a$QO)8kjv7}Rq`4o+MsHhYHdq!bH
zInYOnLmgn9Rq*-&W2aof1&qDYgMtT+%Hpdq+ez8^3nt;Ld_+E>i?Wt{q{GT!zvIzN
z>ks*ur-!ncHcOt$b3ejBFXfLEaq&@hQv}~v8Gi|oeoED+0P$D0HJ~#<scZuYRBn9}
z%7c}4bcF4=^4?F-8lrrW4u6Fz7w^JYm{LeZT;a-h=p`Sa9J+)lL@E=NU^%7y-ntFF
zF-qM6SaDjp#(=?CrO^u{LAfp;3KNyguc1CkIYbenbIJ>JFy_2+-7pMIR{oHWu~g*(
zI-ZcG^cw?9y7Jo<Xk{v^uVYG=l)ZGLWGUPJ23WT8Rf^8%DEnTA^|{LUF$x1+RR%;s
zVV?37`6&6y-Si=fLglkmh*zX6OG4|qa()EHij^-?1iwUi@K?x}Dgz&bG3ClsI*L-E
zETddor7|uA3agYRKGat$y{L?$Mwvn})jH)osxG*tyhKsddgX_ybb~i316KmAS@~uY
zjA>C;pGB)pxoia#wktdK0j)!MjMC<v%Ju0`aYw275)<uGeowE-d&&b*=p0lo%>>Jk
zl1E{J`^si2w;Wb(rRUlMWqvonMwG9RpEs)P^TpVh^7uz{aD$I4mxe)pLTPvvdMA~9
z6L_YS)8zO}D+?(n`A|7cA>|om)Lf`|q)goeGOIjfhfX`ymOW5muX^?_IvrGVx*_hU
zN~2m=CzUHbK%G?|RYJXsN<-<x!zytSrsS%!BNx<qM0H>r2HjLK(U`rvYCCO)kE(`S
zq25E~cNEy3s;Hkpyi^Nl8{(^)h=RPIs^(j;_^WnNS~@_r<S<B}D!m3{K`JrjmyW6C
zQA{dWHDZIY<Ek~}=Y^?u&^{?#HMk1ogjMw&IYlQ`3F#P&Q0=CKa-_<97FL{6u}D*t
z>N|S9MytME3(y#qfT~YUtFFEa`B>HX<Ct%p%7yN}c-7%({4fcs1N7ERQsIkZ@HkWl
zkAs|5wNTmrIaTZpK%ZCbN(M`^%KFOydQ(*|`~sLX)m|oA>8eXnfVrsp?P+MrP+4mr
zk*QKr8sn16dlf9qQgO(YysY~3B$nigN=Da3HVg$yj%xG;ELW~-E;-p(RbSIRou`To
z0Vz=3r~FWnYJ_&$*Hz<IdW#jS0(}5lqDqQ{M5$_J8d^70-^GEaOm(Ud*yXCNA7HFP
z)wdR;QuSCJNR_Io1me}IsHZ?`R3arvt?C08kejOa>Awx?RrAlom<H9(NPsn}6jXWM
zq*~bv4b7_Wn<(#iTjfE1SDQ*o#<Z&j#xT(i)#8(o?^O9yDfS)JETzo5RA1$Q^R6mn
zAC|ORWe9;lk1GBGNU!QaFFN~FHnSl8s+Vs9Wk8ih57K+8eMacLuUf^0F(azq{&UV%
zk^3p{F{bLfg28c>Yat{iRM#G2xhGX~s61{;CHNo4rd76dGVGzs7>dpr)%}m5;*rXD
z9i6kP9pq>^sGG>2aa2F$4uwwYT~zMitX@r9PZzb{H<;&P^(NZwxvF)3z&xVfjBTEE
zp_}?;dV0C5UzY>)sQQx)XnClou0q~h{mF+=;iLXE9D=^;fR91^)H|s1&tJVd0H6Wt
z7z%eBQ(u1^dV|%k(98F@+VBlXh#LQFj3=?W)D^8TwSGS|oK)YXU_yjChQ3l~jZ}A0
z{PvXkn_MW2QqQMFh*nQ}0W?P4_#|4V)hR|u#HzLHArYru8v(R<wbcvrO;B&9V+R-1
zo>Y08qLx!=I8_}@!SXcq&z=}dS2tJzc2O;&N{S5i>Kw>rs-ttka>=T8V#Dq%buE?0
zT~=>=3*?G=`X(&RR;%66%2A*10Bf%LI$a4@)e8>+El)kb23o%QR}ZKtP`A?2;%n*x
zdh{2n=e!H?BK50pLeq8iUl(CovHDMXx|gU6Hv*+p?fNA+Z>U9nRC-sY?xCN#T>Wr2
zKr7U*`eLwB{Y3^yl{&|-B#~*IL&4`d_4gd0+)}@*g-P}5t_&z@PzTbj-KZ8&biGM^
zVGl^N+WB)VMT<I!c2uqE>r>EkTWz8kQJebkVOZU+K1dZ(_~hC<XmzT;ppD!e^~hOZ
zcB#{;V&ty6b{eEx{obckkI|zJrPEx!YP)w~XP?^nDCGOq>#4+jK)s9Np7+!*h|n5T
zKWYKzklNQ9Ecew8??CUc`XC*WdY}%Y;O~gKlLLWK^&-EVq!rfHbogvied`8>rqrVm
zV4P9EMjrbkwfHF*KdW9s`yvO;l9#~Zs8Lbrn3G1?2jZ-Gw;e1lngn{R9oF3b9$>DT
zxs<y&qB*tz6LZt#(zle{HTbR@u5-=qEfDa~+;|%rJT+=7ZI-+=;pC-yYt(YE`e;O-
zf%s~8R6^{hIYdtxf6a?uV17ZGt(5&frb%>!O~D$c<(SHG&5i_chG-trr))zti^(?+
z)7+hl&T!37AA{wD=0(~CoYcHZnSlsR(kg&OYC^uJt^6s?Pn4C4(j26mLbS$9fx#Hf
zS@Ky=YqrP$8n4+-)tw2Naq>A6H6NwIrX<bQwV1^j&BO>;&T4L1p!b|cPakGGuQ^2p
zY{{BF+KXJ!Jp2tLMUz<!@l?%&9cZO#@&)w0hjdLOeVO{ACU*?BWoQmk?SH1`4_etv
znk^Lf&(gec6WEtEPf{V#6;1Nnus2(iNUzBpP5*t2<!X8hL9S{x`opw5jiL~8`I^~x
zp|C*HO>gjP8lQDAtx%(3ptDG`93c<u!s{Aq5X>*uWPJkp5)IoE>Ps~zaqNBJ4b6@d
zXq9Ok?m}U?CWO4|3XR$stxApkG00VEj?k&<YE5t_6xL|ITLytzO<V?8Zfa`gKyRIf
z^DM|MP4P3}tk-zc*0w>zIskpvM$NTq2sUY|<^io)lSDzz7L5%>ky<tECZOHcEFDLy
zP18?)bh~ElE-XTa#<&X0)u~y%3oLguPk)FXty|MT_jQjZ_as#GY8H|M+^5;R46T06
zYH}wAH0#en{GKMCyzxP+M)@WLhcvB}$Gxu+k*hSUNppn34>W6;z#h?L(O+4QYSvQJ
zYfQ6*az5jlZaO|Sp%GNVrb*4bB3M7A+4U9VrZw|#qxDczPLJUk&6;wsJkpe}0`#mV
znGR#vX-!lEW3Ls74r3M$+HK+Jb<}3P3WZMEW_z@pwZdxH?V|nA@7MDytd10`aMR`-
zgPgl|^SdBNwIMQ0!bAHu#alhKPW0I@FRh$5OWxX-e}Hx$t=a(NeYI=otec;<^9(xu
zwRt<y3ef&ZS+_uK;5^6$X+5b3@tF26G9_5cpqTz~Z9i2?glIoxg`zi9t340wFzqH!
zs1Mf;Uj{j$eaVlPyu$kT=MX=o9if;(jP})NV4l`~Onc#2?fzJR#c7Ydg;u=wCI>7D
z+7~EKm8kvkWpE~G_isS!jMmKvl(SlE7&y;qT`8||UVEQ>)MV|ld~{yW=2F@yMcaB6
zlTOv1wP4B8v@ckxgd|-nW@5S*wY$H;V1`yh(fmxUkTMdNv@#B?$kHx74TYDrB?S<?
zqMbSjz1iBwFJhiK+BgMBu9oWs&a2vWl%~$po+XbcU#lMkXMy(FEOcJeE}&>np>~{d
z^hMg=-y@gzx;BoYKE>MKw_>$Qv@8lim1_Uk3UWjHIX$7vv=7O{FV{{{bfH3PV+2g4
zwu;W?RB0D)gx+fH^e_Z!wD&patkw2C0diBDPl1FwZOeHG+|n+kO1pY((>D-k(0<)b
zE={9$2^AGJX)}*NMYHy))mV!b?PMlMt9CV=Lb$D6L3ewb*18pw>C|2$AL@>_m5#=C
zX^rjBdsln36RmD-y9t~<+AEa!?A3n01Dt)@6Ez_H+Ex8nk^!xWvQYQ5x!Ap07Y=HD
zs0w08+eI6N``XtjQ9P{8prrQ$Z6YP6N3`>3*D|Udp(?;J?Ob{WjBDrHgG^|%H$&m1
zcH<6^DQ)G;K$+IQ?TXezZ6cLM&uF_I2g)O@{vQ}Rs|_aq$WFI_2Mtzx9hbsC4!Q+%
zF*Qfs=8qxhq+7ZQ#97y~53DXaD}}NS>tgA2r>ic6b~{IOfgu=k)9F1S=dK%$Mdwl7
zT2k+!`@I(8p1Qxjgn*ZB2OT%}*8M~Y1|Qx1WZ2}Z8>LsapH=6S3m$)6&J#cj(B-M2
zDNv{V3TQ#Phl|j8OgB#F=Yn<jUWeduogbAkhv>|kfflO!kRCl@x&SH~3D>QB4xlG=
zi>U-FQa3_jkW)Gh*&C(XLKos`-P`0;$Li9kdNxjH<?~^1qApp91y0iKm<z!(IxRh=
z(sf1qq3NQo;$yI6=;A0?m#NbhL(?Ul+dQCU=?>BU=CZDzHXm1XTj*7ot&62xaE>mU
zsvUE6@<q^eRkwBvQ1WzJFGEqj?ifA!3Uo<Ua=xzVKBBEqp)T+j*jA(qNCeMyUDspa
zDb~F%1WbwU9SUTZ>RzIH?Hjt=??7Rhu1N!ya$Ug$IxBQ<J_fl;-P;tKuhKbo!TM_5
z^c5IWqpSS~ty&#&M7S$-m2{S`PM5Kjl47@X+ae)Rue(b{4Gp@1zX95)`*JJBnsf<t
zt2OJ4a*!6CJ`ki;_Y6fqZtJqwV@_?lb+k!r*InYk&<>rRk`SG`Z2ES}9o>3ww7PVf
zB7oi1rG=x_t*a)dxJUP%Gkw9ZS69@5Y4_<O!T{Q@`;emI1G-2`XWi2k`T%rLw~Iam
zGlXSB>%Pv9%5H~so4*3*1D%>Y&k^04<G>!({XjqSm@bfxCy(n~5};{9=kOd_le%qG
zMmME9@;8i`)|Gut_unJkr{`eltj_OWVB6`J#R1J;pHYVecF;?Fp~+D{c?rfi>FcQk
z#aX}nH3+!qoxTC+Vg0Q&;B?iuox|7>y)V7)-1Hd<0CU$*wL{@i{jX^l^UzmMVa!wi
zIc;IQ^!?-=SiSX&U&AbX^s^K>_tndeqUEQ5Y7N~LdOyn52I#Y&g<zoG`(s!Uq;Dse
z`MCaDdUJ&6XXwKTq53tH)(_KHgkdaPzmm$1PUth}xcy0eml!M&`cEj79I1bcP)_MH
z=z5H@>Ys~%rP2EDszGA(w!WCmY5iZXgT(3+Pe3A0zo`jm@%l{^dq~hTRalZl{R)ch
zC+Rb`0{e{qT0F+i>Yo(A`g8h?&q3h4J|qpTWc{ooS{L*uFT<D={g?DTq*T471g$jv
z<EOrXV7flfPm{s4&I|!8OaCctJTL2iodo9<{dEelXX||m(3zuOMBCn6{k`QFyQ)7$
zDXKhu`7Z#;*FW(A%q`Fl<^tuKzSRs3h5ED8Ft<p*;R;&U^%L|lz+(MX%2}4^_r3(M
zQvFe?p1YwB`tQ_VnLdq&X1SjICni{-U-BH5qEc_sV=h(to;k3hT5tUl@-_N7N+_(=
z$5CedrhbIt5q0{Kjp)3k@1kF#UcZSR*$sLIWg;8(!*?Lpq;I2lOSAqqJqud&Ikekv
z(=Yg&s&U%&PvLV23p?~}m6%$me!mCg@92e8VbrC6`U{NR)pt-$dbj>_5#)RHKT-`w
zufA$C#QXHGoPa>Te(5Z18qmkn?{ZJy*$cTreFoLG4e77VhxmPcYBI)#^<1hvd7y8u
zrVrMP==VnhZB+m394H*qKS!TZ9M=cZ<8eyAOa}RB{aM=RJk)Qau+xk_*&UpZ^xPh(
zpVf;f5MgI<?gFtl*d2!o2gCboAm?a!kGvEo!(Ve?nzO-;vN|q?ZFIQnuwfsr1M5Op
z!}oNo;E17@0zYns{j{TZHw5ek&rw6gDX8!;ETRe&PeaQV5HG_NneS~7QjpQdz$-+j
zui@F3VXvRzG9^j<4O{1;6<~<*#aN)>d^rSy3<v0;b<EH~5x`(Wj2xZT<A!Vs8iyGE
zp|onKff0$Rg&Csgbr5dY=>T%V5J7LzlZNg?Xhj%e6M!9QV3eZsl;N2lArNJ_xE*?<
z4V|_Ci!u09ZuqpJ&Ic^9h9y+-5NFWQDaClh+G`*QhN1sqnG>ysxogo(GITrx>@$X^
zZ$tj9;WP5J&l$X^2LHU_*J#Km8y*Z}oh}%@Ade!&@ZuE4QVp+AfGf>#y$vkshN20G
zUo=#ar<h@QjM5gFhQ)6{?vlZWDp9fw>Rjl%Z1}<(V^<8;C+Q<+xrWnp5aFufqwQ$r
z8Rn7il5ZGV44wjm2j%Xs85ZBhS{53P(9XWdAfkG*>xT6dDlImMoIpwpEmRIsYS={u
zKQ|0JC=gL*sIo<?-0&F#;uVIGSD~TOu=jOLqRLQiC9k2{zzBn;8iV>(u+|!`kmq*O
z(BA=4XZTKv8QwB5DC%5qaMnSv!4PJKK%?Q>XE3J8@EX18nhiTrFxFz&Pt{?qhBkV}
z-!{DLhox*YOw5HqyJ1lwEbK7YZUc0uVf;MBx9=D_4})|W_SHe~u3<B6gu4wF&cfgx
z!y<}r_Zlh`kmxhSjDe-!u!<b10mDW5W6yhrvJ_ws8ou}q)(;tSXg_e@u#XRvVZ+et
zKzU%;^diWJp>qWkjT-K!L2k^@v4CEN<AzT9K;#6jSx8J8YUw>PWk?vsoTd#a%@BNO
zFjL-c#xO;tYL5(J^2%lnD<46VopCk&zV=2TJ+&N+N9Z4m9E~E1S~(f-(VgmS?EV)D
zU5y)5=saSyqjNQG#y5}+vo3Tu{%MCbIciL&kA!#_|NaUsPh;HMQ14|drE*Yj;~FaV
z@-gmP12kXbdL26bj1g37<ZoPd9J3EFny4Z-(0Gud06|9oUXWwP%svPN8#B6L=yBud
zPN)wtZly#1p~jW~=(C0y8|DK$+_*{%qfQvj|5YLzw@_j;!nl-*>LQKnsTS~*F(3l+
zQN{@>YmPQvq{}PDI7#RFPa8j>aAvHr=P=BUGrCeXBi{H_I>r)=SM&f&G|o^dSCTP0
z9!q(~_$<Bq&svSI-G<;fBWnpj&l`vTz+kd5hSIDTjEr#zrWkGM!w0FxBUEvbW(=ZJ
z0_ny_^_cHPqmoL_GK^1@VKSM<`U#9(GD_(Eo@LyX2kS2z*Z5-WigENdz_N{N&0xtf
z{%Z^Mxkl?pRJVH7SW8DA^NgAF(9Sm=XF;OCc<(h#=9*D92#G>t_M4bYk<ld;0@sZW
zbjcPQ{bs;YVhl<IOQ|tf1<-Qi^8ZSYjpxpQrP5e62J5Sg`<@0%wejbFVMUFx;~8+)
z8uR}9oc2wlKOK{)GhTlJ)4pYVhkSr~V?MDq7!OfJexosM5Sp5d;fv5}HeN{uT8mLe
zY3x?xs$H<@w()8<#@dYg=q_$Io}Y&)br^?oFr`kTr2)`)jDIYFqAp{P3&iglGmI49
z?luZ2!QNwBNMXfZV^jbP?lU$XfJDFXVisBhMo-G%-ZL(y@ZzA+k<M)o8J8&`e&3i-
zh_PX#kPA%@jL%U9cf|OT9WY0Yp)oLR%xI=Z;kYr9!qgMSdRNFz8oyslVWlafxDlGB
zjsHFY^$(4C%OEjhJWC}WkBp&<(V8`$qlb{4$!`!a_NIqlq2*wTq|3w6)N~8P$@J^@
zQ0Q#(RYK0iwDfgYaoF?*y%b$dp9Dd}5tD)rBD<M3P$`PL>G{?45u~H0ZB#$yVHzX1
z*VEMH28CXxcXk5Q+f+^!oIa+#bne^Nw3vP$KU3BeRxiX<NYRK;liiEZ6lSXEho*2-
zU=##Sm@MC;^Q5U=2$l%b+rMGHk){K5y!Vtz<&Lo^(~3%rS))y@6q1fLeZLU$ai+H{
z;E6Z29sx{(=~4?=6HUsWK$1-NMzGFjOe?p;(6gp*O2Kl@w4FSQ^QK>40ZBILEdae>
zilojI)6fZErkYlfFPmmML~oUJ6EhYXE}Hfvp_O4ZU3Eq?(=<H?f|pEX*<j5w?U})n
zWSi!7p)<#HQ-Epbny#uqu9{3oLGnz66b8;WSqEWLfvH#klxwCxD3DZW(o%+{$Ta#S
zI<K1!J%Pn5HXZ1JT#0ED?Qu#?=A9V3VPbE;0u^PZwj?MlH&w)7u)_2dMa(KqL4K8a
zE0o8{6|OTqyB&SEOe-jgQg8C3@JEBGsR)W1O&wJLX)@{kp3Yxk?NnlUZkx)~U~Dse
zK-Hw}ruZ)*-C>ejAl7L*N^ajBQ<4g#%XFm~Gr4Or9fzK7lM@x?^q5+o1ZS`5DK+fs
zGYRSNL%-=FZTJUF7bFn4XL@BR#s*D=4$v@U+V~J^@0-llB=8KI`VWHVf$7r!&^uy!
zoazupO)t<!cFZ*OEQ}d9oo8a{rcCS8V8yiQUvH3yrub@TnlVXEqxHyCPbV8@O_x7H
z%icUV2LcY}S1FP2X#SPzK%LA2`c<9H-?u=mi#f5}Pf+lzRY>(3Zf5W2acQ}mQwPCv
z)a*_>br16yIws+17Nnx(Wu7?;ecomU70~;bwG<BWHE$!=*Ux;C+*^P1-}Dj)FwZGK
zXP~)m8j6C<FH)%Sn3+qVgkbY)6bC$R4x;MF5c6l&T!4m}y+;8WW^QeQrf@Tl1(*}&
z$O5!ZnhR(*9$_vf*DBInLs#f2b1_}#QRa_mgA#4#nL%RA-3tJE+PuygOBieRBd;LA
zeB*N%lW6{d;(AHuSK49d8S_I50G&0jvZpQfIdh{8G@Un3(AFl|{3pd$FPIH<#iW>9
zPNFl_oJmioH1pPW7?W=P^ep5qny=E~p$xM-9rwvKKR1llRdWVCYx2w%dg<kx*D;~K
zz<lHY6kaor20*;XynQ34d)<8Z8r9ero1<xuP-4z^0Z*yf{eR#oGoQ=>Ou6~HKQUHe
z{+n`ImF8P70<Fp%Nk2u6`7;-c)tWca)9|Lb+!w7n^Ivq=+%i|t1z2yMsfR#=nVAfh
zM)S+`O`9h3U@_D;o3jn%)wh^i1<>1SUK52G-Zn>(SKnrSYZ-Xj&70}n*<l`KL%!4e
zdlf+Mm?h-#cbVfU`*znnMc!MtS^XYJk2ysF^}S}%5Lo)mRgXcg-`qs^^?<o34;J1t
zS8qe-pt&{@t&fMyEe}BNo5LyUJZ#?oBGf-HdtZl5BW4TPJ!(Ec9>AD+n!dF%ZVpt#
zv?=r7bl`N_{0VI@ADY!vh(2S^yp7IB=G}gaisaUkr@(mFvXV+NTrF${kdIiLD9Pw%
z$)mWSyCpjwEFPBqgIFd{OYM1ZdRasiX7jde>IRFCMZ5u!zLuOe$oW||lDp(@kvt0$
zV9`=6IM9;2401u1<;h?<X7QvgYOrOmmCn~4x9G`Z4zVaHVj603Y{rbjEcOPFaLWjl
zPn@tkO;__t%j;i*CBiZ^1e+o)KhW#=l;!PCw4yBU6+mIM<yt5d##j!QfSk5``x;nc
zEn_k$jI*qw&mYBG!j6C>SoS?<1x>W<JAt1y$?|X=B+gh`KZA*9EiaI7aL#gwDhDoD
z62iclVtGWn*;Gpig)Gx7%VaP+-O?$9_(h8g1ywUGbIE<UWO1c$`(;_O7lZS%rRpiD
zzharU9LD5W#v37*Yx(KqoY!$TSe9+YV4fu?6*J7Y#9jc;HH)hk=2U3eLB-TXm_1mo
zTfTlCg2fg_GdN2upHNn-)Uw&{{`D1B(*u}WVJZ9`c2-)-|J#vR5>U3eu-f9Y2v{{1
z1^FqpmcQ?y^QOh(kEzsI{>O#DEz9#1^s2X9r>f5eOBns~jg}o0&S<h64g_?w<y*RL
zS}ZS)L2IjJnC|l1mMxS^XtP9E_oCTu=?sLq9hME}Am3@(T8%ZhW2yWZ3)5x!G8B66
zT3%fRmTt=t9Y~Lbtw(3SWqms|4Ol*;dZBxk&S?k?T7oHlIApoQ1IvAjfhsy5SZ1Du
z+=ykF0G*?jcb-IR%<}U}DoY%<uwo!MX|XQD;FKkIA;`3avj{K`EgvU?WyaD%cgCzG
zfVNe3ws$E6ZEu?<Ma#kVmk5YE+UEZZE1Yc8$!l=7jrIg_v6U_b*kRjU6vlV8eUCDF
zM{Ilg(Q>n8S5a}iyY14Su%t(Az32k;uyvw<w5RPpit2mWK1rJ;Z(BCK=zVOLsiDHx
zb`K>D{cPD(t>JI0r!aniZ5)+D2HJi|;prgTr|47H$84K-K_J+6^=q*Axb0s<&>Ld=
z^Io(<Z5w~2|C|f6ZKu6jxNXi-SaHJk<82T;X*>BmU?OaDTc9b@_VI3XM*p9q>yFE^
z`r@XUWj1V?nU$3d)5_Jm_ujiSE3IspE6uEIyokzDM7AJ9K@gB3pe)%4C{vIjh{zHF
zMU*Y`_dP%UIiGv)Ip1^ceV^x!bIyHWbkhB&NQNJU+s-gPr>_S@F<$r-;?WESEh#aK
zUOKd&WgHemAdb;MVU~EtUAh~Uz$nax-g68$TBi~jPcB8JJ&EB?-ppji7IL&+U?|o?
zB872)&VQ+lOKJEG(ij`=gQPPWqM#{*v6c&Rk#Q{tre!jU_MlH$jKrfTWiu)$4JL;n
zuZKV$W8o!?Og^KLz9m+`5L2Y<664%O=q+SaR6|3NoiRxRT+CSVB&@i?_-GBVOBmS!
z;3;Kv(jC7thUj^KmNTyVKt%<k<_-ia87s-cDu#f5t!jo~HBhcG%CaF)!&q?(ZMBTs
zwP>qj7-At;&xqX$(!e;Q0ZStzDHR%SFzlbuY}~|nigILbGM>*vZ42Y}$57bHsCEEr
z8>3-9My8!ny9JybjJ~7j#cjq`I%#$?o~2z(7b7DC0^N*Hwm@MI<Fyp9+-0m?2e5mL
zEp;%am(fSj$@`2>TGk&hB4?uVA*0^j47>XopDcpJ0ONaS$PY4-|3Ybqan=>s!;B_p
zz>F~5D5N*as9%rLBgQ&!*fhrQ+5v$HM(uk*nPg;o!`>;zi}V$~X~x>0pu&N9X96ty
znfGWL<H&4cf%71<TLG{`%$L{G`{%@T*$D|}=3zRnyD;;&0Na(hEgWcW%!RE`c!c@S
z0+igD&6Ed!l(~~`7<e$1L8v^&9H+ymC$ozp`CiNsde(iIl{U2bG7s&BfFE;!4l@4C
zqwj+pXI6g%%oEJCOB4qSVopYYHJCa796&>u>8&V*GDmV?{z>NUCox{9n04i_JDgeY
zD_Bl5pQR5KMKJe=qcW0t^aWI&VcsE^c@*;)^*)-ZqV4)w<_cG^#4??;P#MR}IfKf0
z<{t8$B`_seL-C)ym>t1rOl1B<XSF2e=ih-OGk+cd>v^W!gsxp+-dO{fRQl8^UI%6`
zMMlz@Z#;%xWH8lq6u8KAl;PLPWOmXOrYxp}9?~4<0Xih*GNUMLk;hzf9w_<D&uL96
zV1~bglKm2Ml^r~V%)co6w3z8!fZEH<t+XA#!hAIsq=b3&PqdXXf3V_LD`Pg%$J5H0
z?v5apOe5{Pt}@rthPH|+Bv(l_^VNJ*USq!TBSxl<c}#!~)-!`%g=yEB?t@@yU<O==
zc%z+J{4Z*6FkhVoo+jo$2SA#c$IgS?V*Ww9j27l#3k+^$MrxqGjoDB4s@j<c*pTmF
z?xT#+PUe%8C2)rsaS5d^X7XKn9heoPfbL=5ZiK?S%%eYp++(ijg<LPw_caXHeWqPY
zX<dEHIC2a;U`|oErJtEZv&aCmAPYQ$%u9d6iXrA93$TZo!xVEGVXmZXr%|RGolwS@
zqtBwF<IIPXuwsI_eH%C@nG7qSr<g-^Xq#rPUxr`Af%WAdAdajpbQU?lin1?;{6W@G
z1IQuPyR^DEu|%}zac2E^7lJOV;!nZq#_D<vZHHNJz6N8Cu!P@$#hvw8AXtvFPSbI~
zlXZdaczLnjoe36i*8MFI@L`2L0egK}tfyeFA8RqO__G#YgM|UCsdW1716kD~NSt83
zaS7cHVl8?amBFmZH4qG8J$4tRP*!~=6rN&LQp7rpRlFUga8~SGn0A^~_cN@BV4b7%
z=}6X65A@{>E0{KAQLF(9pGULOY1WEi#Zm0$ENc&?zQ?f=$LRZ8@vIrQAeg{fdmaX#
zV;!WEbs{U^dyHNZOGgLvWY(5UsJOuTw-_Xa6?6girn1T@mXgLAvB2zf7Hb@wnXHES
zkjr8{PLFIhE8Y(RIjp7rAh|3)9bfZU`^dt4)^Gdg;QhPAO0I)^AuHe?@D#D86QI7B
zWe5Y>WtIaa(OzK{I6`3w>-S-Bma(E}RV!z`N13J-EWf=dRkB(Iz`n{#pMlCM)`Oo>
zS<OmP!HR1v6-Ci&Sjpsku4Nse^JE>%X&Bbqud|+`DXoEZ`U9wMWc{Q=?G4s^%Cc`_
zJ-ZnrbCcyn_lKKVTQ{Svg*A2poUN=^C@Hj!HP8=D?W|3Uf!)FKrCjbitROQC?P9$X
zgvxGKXFmGU!y2KT?Om3goDBC^bLC*^wX-<nweDkWD@5@DtM*-xhpfg1VE40DQ$oc6
zD{28?23h}6fM<y1PC>m9mJ=;GqpW8x1MLxO(PeadjP-OV25+1dPOha1R#FwZJ;_=^
z{)j1-lwxbstTi;+4(xh*EcdhR(JTlaU~i%<jf3oKFTt2Y>~AQ>=EQ!SGR2+QQHKEP
z!d`e5EUxTAayuPnpZ)|aN7!X2f#%L$^Z{6ovXhEHJlHKifyIlx{WMD6?4LeC$%man
zDJ{P2*cV`vANyky`r^;NX@3TtInH+JhNeJvJY^o8V5>VI7{qp-2Z>;IGr3Ab*s^N;
z2BGYK22nc6=FoN{j2%VmK{$KE2n0^E$7rREU<Z=NC6ayZ4Tzs%pGk$LDE1iTCPlLo
zuR<V(9qkX!v+RL+<a&=~yDvj$;@R60A(6n29f68->{2CI6WIdVpCqxnDf>K`?N5&Q
z^K8yOprx>#zr~QGvV)pI(%4yFLLi;}tp_+W*dH+=m&N{o92?o}Sw&#UVXt}_-OXi(
zkw+_!9dVi7zkK%SW`Gv3pM4*Fy2K8rBWxl2KUx%v+5E@BdYS#F5EfoxuRjL6OV|sS
zfu)rF?OI@$v(4{9u7Z6>jkZemIZ8FDVpr0#U(H^tz*t;kr_u4PhCN0TYAsvyDM%gr
z#XEFJu4g|(r{f0p+qBPUWUsG);0^X9U8`(jzd;k@P4?j-NHnu2glN0PE}&yrD|_+d
zz;0uA+riS#_K1f-2YcQW$Za;4!q}bcqaVV;ZZ^9b*7vaUcp!J#yXfOe_t<ss!6thz
z+n3&)`|J${u=cUXdVuzTJxZRjhwN}0$N*apC*|xx_Bq;}4YAGShZ<&oMWM41_T)vt
zJYxSjg3=h<T?I1EuI)zUB>N&|=})oy!%>=MKe--l4xHD1#SgQeGfEe49PON{9uyC7
z94VY|h!dF)RwvGnhf#9oJUJT@E*!6D*zL;kEdrVwXQ?X&;V|bQP2uhw2MIWja(<3P
zn+NA4t^UV2SLr0}$w_(~ZC;#nF9OAvBmEa8KhBe1p`ZSo!ks7`=X`&ivXlcjscRt-
z$e9t3(g{wb0i_^LRtk&>=4|(bd?;t#Ay{#e^YS8;PI2C)jY$}XP4jX%=V%^AJ%Zy&
zKHW%;Y$L2V!?{k`n$aAlxAyv?UmD&+T|DQ*HDFBOoZvw^k>j!l{7IY_-vmkK7#4!%
zJZCGtk{38H%!4T@oSsdnOy#hW@BpN9JfDDg2Isx=5WmRzz7`5HIUM>DK^Es-CMvTz
ze%@8r7ug5@0%IZPg$$4)&KC076>~Pz?))+*D-sH>aH8lTF5#@E+k~YYb{E>pIFDtZ
zljWTDHdIz{(n8U@O3v?oC|%{eN#6S^&dZctQ_X2nf?VU286Z%@@jVGr%i-h#<vM4(
zosNPHocSqG-^e-g3s`S(rek4l6X!MsS8sB-lz7n0*)Rj8TbymQ__T0#kxQ$UGlvDz
z#@YT9#M?PW7W8&-;@p9KoAU{UH##{18R*g-&OHjxcX5igq3_+CSF<74!`bOg5rw;)
z6I#gM<8;yk-p3IwgB1@r4?<9S$XWXc^8K8*YN2<4^UPl$gPeOyp<;*=_7OmbIj`*n
z=m;l-_K>5TfPWzVh_n7*{QP5_b@a8tagLobJ0>`x$pD+=G-|;)#rf`cx^p_s3EB=A
z2k!6h0CYe1^$rL+avS<kI>2@R7Hv-4Ewq1e<}Q2#_PTKMgphaT*1H1Rjr%qq<S;ja
zHsD9N4>M76=k6&3Im&f>3kp5BG4#A0;~p4Ar5AVn5sdNX{sI3k?tF6(-iM$sxA1Fd
z^5gEK1<Ie><O*_}Ya&Nr0JnzrFM-@N@<gBDmieMBi2DnD)Hj5?ml8Kaxq)|};v{zu
zZOKk?g><qC<N8x#NjP_7DJoBMuLeVJ1a~E+3`BCb<^j`whP(MX8l$+~8$e>XvM*u9
zS+0h*NU_{M%3xX?w_goS@!T(`A(+7ZE)iCo<Cf8nmdK5z&{h(+p&gaU+@-HW{5*FS
zJzlBYi!>>wanlxpC7tWK8OCIAcMM|?E^?jdfylITMRQP_#ciYHt!%CXC2{9)Pm{YY
zm+L}HLmqe5Bv=c$`*uP7CGLxIR2Fi7qCi;@*Xsy6TFfnPhrng7Y$3=M?%iL}(Gu>!
z2M{Rb>L_KVjC-FF(aO1-4nVw;+t&~4uX61^KcTjY`_BRxRn6T`x2&#lH5@3c;Vz_)
zsMc~v6ChE?O`~9AJvWo$>({xujbLfuw$aAr23JKNo^0Z_-vZ}N?oN6Fo4J~Nlx}f3
z`#@T_k*gus%I(sCvyB@}XXJM7J9hH(b#U3V>fPq9BgbhM*R243>gIki1-pB=Im2MN
z%k`%?_dRYTdDwcn>nXH+pSyTF<odYH6r_2;%_o=BL+*+<f!)u|xeCrfu4*AzhPccM
z*gMQ!#f63ut~MT+que)-&};mNtCNF_aep}kOUJpx<ky_wF8BWL<|6xFn^EV;d-@HC
zAK>Z8b#suHMgF}*ythw)IPqAN3gXOra0F^yc(2o;&6U^t2|(O<JCeb2gx5$%U3Z=>
zA8L>CLg@;F2k(_L5IDy3q6g2D_c6`8Uc9|D_jvQfzkvAg*4b$x_2qp-VJAPH6UA2o
zc==u^1@bOFiJqO{y)TCPAfDHLkYHXDg#ki%_nw8>p*)it1WxjNqM+gw?<tyC!g!BX
zV_?F0iwD6O!COWLoJigUD>%>a%$Fe-#rtUkG(_{(C(!&9!~1~zUT1j=dSOf~Z_gMc
z;&_Y=Ao0A!S0I?cdq9g$B5!XsN=dwPQ;<*QdD6Ocp2zZs-V3~!=tC7LycD|nm&)^=
z3H52bMf7#rbl#yzKxgpMKL^W2p1Bn)S-ciG#Rjr@+s;B$4$r*>B$xLCZDjL!Z2D|o
zKJV)<@QW1iGHamX5^sS!NFi_AHs~$lwa{x{%sa6b*d;t8ZJbMayKh0DjCXMcILmpR
z^qyDnmNTHRlK00iFy<=HxC<;*ycQ%H*=JYt@+p=08gEbxi5gyHFIek%a>^O2=Pg);
zw(Gq2Vu9VjtD*Iykr#anEH`-E6Ch2z=P9TACa;r@Qq8;%3G5c{@#W}f3-82vu(a_i
znn2ol|I+77I(V0^pzSuVItFs~PF@eK_;+}Py{PTtIr~9VH}60Cj~YF^93(}|zRUY^
z8g2J@5r2c+=cUkv%|2fKr_l6(_q7kk;vsLU1g7=#F55u{cmZ^kZjje^0X7Zs*0g|g
zm^bq)h>!5zJph4GUcxG<AGh<Kq+`bfubh68NuJ01;F;oWBEQ)*?+|@f!GV9}8z|h*
zpC$_(`G1`OIly24H{=iUb3Gw`h#zalkUI01P;AYG?@SSNSN<Y8qq^}wroHuH{vP_q
z)Diwa6h(FC&;1FQNBQ=5SD~XG{2d`^JjQn~1GXnWm0T#^d>h?8^5LiGp~9E{aS{am
z__vBs>CZ3w5%wPE8y`a{fUhHkf&7opLhb~AeJe17_@C0{{a}7sFvcR3UlIx{PVyP#
zqB_Oz<DwMC|J_c3opAoTYN$BP|By1@BKVsUQ5nf!+yb66{M{GPrzn0Q`O>5LU(?zY
z%l~W%^v3axbV85k|L_+&n!q2W<H|Yy1KK4f@^k3Goy0G^4!LB$iQHf3`KoA?F7RKi
zL@9+|S!#zw8b5Cn<kR_Y7lUN*YiLfm$p3}XIy3nmv}|VaXBI<mHh(`CZ8`jl<R8rC
zZ+#7><?*+ZFE5|}107c`@f*q8U&#OTI4msUf4&Q(nD0SJmY4ZEXnnuJAEsNFCHz@_
z<aR6NZ{Gx%GX9qD!CKCr@hbXM!Dn59`m6l)Pr=|S{%s2DSM&d%xWYAlJB1Kx_$)f1
z*YeW^Aa(pC1yJhwA^U-Soi7eRseymG0md})zm`JaCO?oakv8*PXn%Q&|I05k@cy;&
zXYWE|JOAsq(fbbmlQfq1_`8lmVK09NrS0D5t5Tr1kH3|i;1Bp)bRZA;Q8YvJ^M8zj
ziUEEVrMwODS4z;sA^v5`t{LWw_n<VwPk#X{qx>@qQ2B^IPG|Bl{`Tz<w~zBz&<Z=j
z|7IFwlE04vg;V@zz66=(hf<W*L9k#8B=!q-?*NOVz_S2dJ0Mv9D=H5PxbxB9LxOHO
z`s5@SAP0f7V972hbP;s@0TfrkH}s6V31+W`++o2@`Yz`Yf!j;qbhir@c>w09V0<}X
zJOtxMpzxUB9SWs-3OHe?^b)+}g_5_xVnLgaV9i#@`wHg0j5a^PQ)UdlzaTLRD8~i6
zDCim>_=VQuK!F4O%qIkLa!&>cKBQ1xu;AIPD1`_nOVRsKf&B$q#7_!dphNj7K}`W_
z!vsaNB@P#qQH<uaK(GoD5rVA&kdG9ke+$ktg0%x+i4qhp#E?V_)_e#OBM2d1_*ubQ
z<fn@j^n0Mcae~Ntj7+@X0fp)k1nWNq=Q%+>Jpze>XYKDnVUplI23V5?vuM^kFAxU6
zrVD~?6f{T?bQYm4RbV}b$~3_a3iqcA*3*VQLy-F&1TG4G+=|L<!NJd9XpZ0mI)~;8
z0w-Who<Ksm1Nj1T99Rkj&q~mCNw6Xk;)Q}=vS`CuB-s8jj4Bp<O?$k{f*f*8UJ-1k
zxwk|xP3d%{g1NNaE)z7r0{L=*Pb2hJ2-sU8P$}pql&gZJv!T99!19N9wIG#^%4>p~
zrvY6f_=RFCwSpTPU`3svcLFH&0`48UQGQ)88im>hK{DlDHVXJnfVm-vqL^=!;Ku>z
zy(wrm1GHICodTF!f@fDlzD2OK9#*spX0$>@o8aIMl-dPRaHh@f5WJNLf!l(W^mud%
z&hgQ9N3faV{9S^;AAr&=kT0NbGW7`hD3#%^K-LC@_XG))VA3lHqOSwp7Zm;pWBLTu
zpP=+WFe42t4+SB#qwW_xL0ilLLD}aJ7!>@O50)W;e=YP53*vUc!V$skDzJ<S=8>P_
zk)Vz`I41DPLEE_Cz%2CIJ|Sq21J9%&GzwNs2@2>`H7&UJ5<ne<&LNQ4FZ6H+i=*%s
zg*p!i7tn%vP$*mi&_lxIbRKaM&i@%K&O*O`V492YyXR1H71o|c$xXOchtgr;b#k;F
z5qeSzgS(J(7=|9R3v-&G!c*umhFUM7DjNOu7V;?N!$;`<3?zJoJp#b^35VUl;xEjm
zkEb0Mj^{!?K=@4^N`XQieE{x+a4v1~f`oR;yA2k4(|aEx{E{L}p~6LhF#Du1mbP=J
zgkLQ}@56-l-7RPg7e1i{>uKRcJa{66e=h}3q;PBl$QhyO2|NN(!Y)dIh!#eYCo)F3
z<r%0yE38nUEmnBpaSTG7P(uO4c;UKqloEtb=plYicyJJ$i9*IxfKC!R4WKevm`UN@
z^TH!`I`Ll+PSPPKMYx#m*rf^&lTB&D_s;<)U087(EE&S?*=V~c{FM?LGKJOTXU`HQ
zD8P~}93lsKj!;FjUcT_nPzV$Vchen-OTrl{j7*_0gEBFTgdhC~=we~x8E{?}?)sb7
zzbnFy49J%Vdz>IxDtwJTzf>k%^fySk@QXmORtU}Y7}82%J_YTr3g<luv?`&?e2CWw
zw+KOMg{>6+sS`f47KYXfv&nyZU3e%1oDD+lM}Te=zNLjRH-sAsfzl-0BAJQz@22qV
z%fN0Hj(vv4Tf!Omo82NTwt%Nqc!Baj+Jwli#>*u%(sjcQ;aU3P_idq_9`a7%MmkB~
z5e9z&(k0BHtk!PfIm%P)5xy}8dhZH%)PdX+{-cF>uW<h~?7c7SvC@t5KH(D-H+mpk
z!-n8P;mZl=MZfUcEwBy<jpPR!6ka|JmLcIy`pEsTP)u&D5uuUn9ThHMqx4Al1{*A6
z!e2Y^`;H4gCvV||u-pxplfv>G48oLfn*}V>!tdN+nuBQUcR<_si@t6LtD{KwDu(TV
zsOB~#4vKtfH9RExkscE#(Y|NV<}7leh>MFTc@q@6if&TG#7*@6AF$%ED4wRmBchpw
z5O){#d16G5irQ&=<RMx?c}d4avnfy5Q&gUbHZRe?6m0Xhi{?v#<|8Ve0o!~<#mms>
zCt5_F2Y=DiwBj8XIT1{N=zbkE1&YGAf%AmuIK{w%M7zI(6~Q8p`(OzXg<S_|sOT@s
zB|9k+()Zm?iH^`#B24rv<+p{4)^3D&q-c^RgEJy~HpM!kM5|oD8ZBxK0ceaUd^IZ1
zijI%Lm{?I&0#w9_uFQvuc+o4_U`Y`DL0Qu0M03dNlqmX&T+B(L04-3GMO*1Wa$a=y
zFi<XtJ|s78ifAkprBu-!I>x1m9+E>pUDRuz35g8RunjO5ML$uPE>m=z^5(Nd$LPCQ
z*`gnw1#6CIJqx8=(P!k4%oBa*h>qrq+Py&vMF0E->`S7>#{pI-+Cjd@B2mOX*jp@`
z|2f(&i%jG^x*~dQJv5YvB3}epspyAmv~rb+K21TfTvXW$><ZCG^%&<$Q73(G=c>qy
z_QX}9K=Kz>i!KD9GuK3STwr01=;zm=saCX*2hQsv_e&6O5Uq^_X%u-nLGFe~@dMhL
zL{C#r+D%aoO)1TyJ9HQ3mgrzR?LS*YbsvGXRb(WWUz_N@3XSa|@p=e$h+d-S>b9tz
zzOm6M^7;sscSNonkS<aCBam*<B|SiUMB;Ij?us1fADG+|#fAf=SM>D>n0;TgkQSFd
z(SLOF;(^FWJE(`E^;pa8v-?H8w3iqV-O5DQ21T!uZ)8YhEdbiE=!ZE_KO*{wZqkj4
zoEkBRk3@5PAuuL#T7tH5Q8@YjCq!S8r({y})fLE1i7ssh*tF<1$~txsdvMXVUmQpA
zB1iEqI)WS!*SDh0eo#DY1KJ^RCS7KC5_?gQ(OI0h1QIUd1FN9dRs6@FU~v<B?*%z5
zzCg~wBjSLiKyw#6QR2Z-ajqP49^x&Hs5~ZqoMs<S@#GqCdWnzG?RRf+Jv|UUVlJHz
ze8nfp&E#hnn|45xzc`;_Qpd$<KLRE|+`kB*f#MxB-JKA(lA|U_Y_9}Nuy~46;zGnL
zJ7909_^%fscTyY{0n<*2*LR{6CQhK>ak%(LFO*J;x%(gxA#UCX^^xK)?*iqFxalZ<
z>=?24@cn1)3uy_C6X%kXDPH`i0!kCaU6hq_POP2-s6_D?z2-^cTP%=du^|k?=fw%{
zVstKGG(l3tkN$;0sbVd;7}CVEeuD0F@war*HbZ>jPoP{BAD|yTQ_TDu;#uNFS<sLz
z-e)JbVU9R~yeGNhh8s|kCr-}-$rpbN_ucFQaSQ!(lS|^A-vYEy++BgTBJuHjXet)}
zMpM>hvGFsoToHRx?m~&!T?1oE#RuMk!ZL9+8(l9KCzL}&h4|D%j8&zW;R>6sils|v
zyILjQK{w&6#Xa=4UlXqjho%~FHWQ$=;ym)>*NGpe4;a;pkI=JmT|CtZ&Ia+E*<fiB
zzobOvP4N&Va5RgjDO2T^cvl2WYZ1?-xI?S>VLwc36Ym*<G40|{FT=tP@!UV@*2ise
z5eo`C#Ywcqx+8X22Tfh#K^IusEl#Hd$sX~R8fdyJj%)<EC*J1*^}XW%T7Y(6{Bt~1
z^og~fLg0aT@e0`cQ0y}X75(DaH2@nBzd~`<LGfdhR68WTO&gD4@iMIE_^Ofky9>}e
zDqc%xg-7D-qi7rxSMEmTxVV!d0u$nRy3{Z!UPgCQr^G$fi)pd&7!*24UhV?fFKHvE
zf}`Xx9U%`$7)xRHLCGR=EFO|Lk}us!5=Ey8XGuM+9xjsauK~>NDsiQZTQ^DCZvZ_k
zDRzOxQOR8L6M9H=zr%`Sl4S{y_mrHa&9;{$;RzVyEqN&xl|GUI`h0<}<dtV3=O=0X
z0oeYM8Gix$xa7m7XbX^pRzpLeL`wZUA#tI#H%PLb4$#4N37>AcoRl!hMR7{fLr0`A
zi6g}x!X<9=(5KUq1>~WKkcfi;8YwwRe!DXgPfGEPl6)Knv}nl(v}VUhUZo`evyzv8
z24}3KghH@!l6W7m#7p+kw>=UhCn(f%P9kLkI#FVeng=tIB=hK{PnJ|YLg~EZPkQDq
zNW}jEG)0mgj;^Ij(xxDoCRtnnv~<aOO3=xW__sjrqGaD(pk+#?XsXSU1bhb0Y{`Zy
zu;fS*JV0_KTYdpco}`H$t9*&&6yypd59}0iyClh^`MXf^_am5CB$?9&m|}_KK1!D*
z$0tFqNM`H>Xo=(_4g^XiFHHipOmdSxtX3{zUPW7lB=BX}TPfKv4i#0BPv}cn)e`qv
zAlD@Oq-d*=Ed3mEwG!z|V5yVLR?{A|USg)m%XJBhI@%zar~q1{<Xsxz8<IeZeKkq$
zle_b#<UJB>mTZ0kR@{>8o&&R6B>z#6xLwjkA=nPdgJ^KxmZ)AuWvAr2BgF4WvVDQs
zCDGGN+bv0@Nu)<2{fN$hcO|oZVcR{))EacVSF-0F@Z6U~2~g^j{Bs26KalL91m%a4
zubKhVFJZSqU_i3q3BU|W)-zE#Bzb!&<c1|5MnPail1h$_QAsR)=;o0`_&(akBu_7f
z+2fK)Bfusk*Ig*}Vp7sr22E3v^S&^DTGGBBpbpaAk3jZI3+UYADAkiY`+)Sf2?!pP
zzH$zghom*H0MtoZpM*ANX(zdGT%<3wg2h!jO<@8z>5q%Rd05);IW!!Reon3<cd5Pv
zEJvkwx)fyhkj7mH&oSu?^5uI<%gL?fCH>+odgv`(9}eOpoyrFBm9C<5fS>fYboAF>
zdh0a0c3j%D3+e-;e@*}`Q2I4ZEhnUZQ*<Oq+DmIiu=HEHH5DSALvL!R^xZtjos>3y
z2z{sQQsWX7!=!oFz#1;yM=^`jQYZQVYJ@a_F2Y1gCn<mZj5Ip{Fj3NmFCY*tT}Ml4
zjC3ax)}NIo&`~{BI&d7Iandsb=tR6UBN?RxY3)gnbJG0@fKHTdOoyT*X#shzlBISv
zy^iOlAJYqeL0U2mm=tLSd5}}3svM9s>E<r9rAv2GmSBdI(FB%@(#I&+ktzLz(vP#G
z#xKB`EsdmaJ?2PPk-tAzs@o6FJn5@@VST>TNY84abmmbQQzW&@P+2Vf!cOj*%TixG
zB(6xW`l7K!+FXgoQfZU}+RCK!ZlJAP>JWss3h9kPXhMeaKJ@Uaw2%&ORnq>0&{Qpb
zq5|Zabix~QHB#3GkXq?uc@U_R4nKtYdTB~51g=Z>^up{0=^Be2<J>3>r;o+lkhXse
z`6lTeI;7u}iYT4ASz1Dy=3CNFav|6vb*5-et91H#fVN2`Hjs9yYBe}Jq=)-p;ce-?
zU<`1lw1-}YJJQqd!-_6x{v=qsr6;|>(jzrg1M{xbFN#tx?nz%>3(#Ka1Nzj{ed$}2
zhSDcZEC6{Rop>5(52YKzLHeb?(jqe;Wza%DD9xP-v>~bVTa<>SPk#=DBhq{p25(gA
zPw5<wq#sWKdQAFWAHc??Oba+Cq+c9{O_S1j*i+#X0Mccz0CZX^;6l(r_6|jU_RF@?
zcO)HUnfGAR0oiYfs5~fZb3o~kYy}-pon)WTLD*TQ`xArUBJ-eS-&J;8he|iu!b(&g
zmg#AKazysme2BZtzM^pTQJGIOSUhB|pQF-#OtyP7^m@ut_n^^Bmhu{iw=8B1mioxv
zU5GY6Sp&Ts{<7Def!)VtRrGQN$cEPdJ5ZK$5#)r-v=o&=vU8MV6)amv*I+|r`nOOS
zD$`JE%t={P1WKo5oYz6ZWYgqe47bZ3C%aF}wtfs15weA}=Z=)!pai`$vUz_4ElRdr
ziqVUfwF=Sg7@5cGXge!2(rF}C_Cg+5;$+MMl;UL>55STj^LYs<=VV`<fN6=cJeqxy
zWYx`ROP0BR2EFHHPm!1Pg3O-w9f~Qkm2{*_mHk1pe45OAD;m>f&Tl|4L#F%{Fc)S2
z(OsHMSv9H1l3k(GSGH`$yI{$YY28uEm93<X=E)?K2$e5;wGN~}mOcw$mt-v3;}^=V
zlb5GRwwHYJ#j;=RG$UV@{qiSxN@Q>KLPe>}$pMvRvZWNiDwp-uK%zqS8=Z72Wuxg(
zcvZHr6+cszY)2MK)w1=AQMx8OD?zD7rlP|^tt>1GhSteM^yt;gerG`aby>m$P#R=e
zbSiI@buXgu%njMj-yzW?I~E8{H)ZWg2sX=#-$b`>$=-{A6)m!*H0!m>+8zU1o9w4L
z$hFHHXMuFcDk-#kTPCHGN~bJ<B6D|SZ%qKKOSZTcVBNA!lmXQvix#5ouI$7C7;{gy
ztekHB_sUwx|9xL3r60CW7P%5C9>_lRKxZDx(pO+C`ejM<tPjYd=u={YvfDNY49QrO
z^)oEn6$ZT{vZzULj>_8KL)#<SsWMcK$>zKQmT{SZHV+fB-#5aFN!iss;GB|O&8F0+
zX;~?`G#%tUuffv&^7C6k4$6K1pByb;8UTe(@=e=7oaJ(QDP81&@1f)>Po}e@n_L(N
zdk@PS=-R{)c`IcsxXbNAl#a?1$yMedkD<f$F?k=I0X*f0{lVfTXSktc_m(@*w$4ZX
z{8O;hSN_s&7~?0O=La5tc^hqbkIRpEpfW(7Qx29uxqz}}PspDu0SS^v(JnYx9=Z{2
zA@bj83lu6p_yBDu<*j8Pr{tf;f`rMve+O8&{4pA!)AB`+gGAWn26FmD%Acj_?u`7i
zWsr}OU;Q3GY_$AYAxMl|@D|8fc_ZD{jF-#b1Wbbbhj$=wPX6bcs7#bs(CeQh|Bwy_
z$?~Vh!E#<6DudY<pcmpP@{w4ORCxhCWNGppVX!G(Zofv8Uxu8q1A-Uji&ukW%K0?1
zS@OMS0Fy1xA4g@5eCQy0m@A)43Cwx&L-ZQv%kNqMS|At3g5{F@a1utXP|k?Ls29l>
z&}pz(euEM%F3Z2#kJ1&n?Muj&$PZqFK&jklr&qj8&eDOWTz;00dKK~?=;&N2U-5s}
zzWm5<XseR1K8(&(%fAVO`PbwxMWV7su3QVyT6x}bpw!7fT8_4Q`8@K$T$jI3i&KMq
zS0P5GQNEW#V>je`$+g!cfAS_+ZpstR(9+Q?4>$_6Tk<EJA<-gVwi2wZ@|INaw8{NU
zsBD*q%!c|7xj&`y-Ijkqk;pE2<9Tp)%fk&At{(YsaX`5%ZzLDrJ^90JAieUN-ioQW
z?T(cY8;~>Jh4w-D&uM5HlJ|B)`LJAj4`f8{K?!D~@}fTg`AB~E8L*7WZ`=nNmv5%K
zv=j0(9zdCtv*`Djk}vXx)@gY?<sUjI65%DCy<hRllNdoqg&U3X0mX*rFfIob8|)Ma
zIi&cA2Hi=qfNt42E7aA%c2T(h4hdI<@8ghnQyis4%fkw1N^3cyILAb%-4)+fqjXep
z*#~kSieTC~9arr1f!+Xxd?rYsV*StHJfV2G8+wBjp_^e^uwpg^WkM9+Ew@8HRPl-m
zjVBfDn^8KY$e~DWm|~F!)Q2nPOHewkxYr7a2t_gN-y#*a=oY{kMSKE!5v9naRN-jF
zJ9I>fQ5>m*F=rKvXhn`yly8GToMPu^;EY!^KL-mF6j5J*oKpntrMumUia&owF-eim
zgM6|ghV~BU70**P!v)2QMyO9wyhL07RK=ygLDCeD(RHJA#oguTOorldC#bln*nA8s
zG8L}$zGW#~zJdB|MIia&aunCxP?@XX%|r+D6l>xja7j_MhAtQtDiZxsTckKlo9ALh
z>Q;bWRxH>7`74Tzf1|BLQ6d9Osbcp=w3R8g(AKg-k@Oi@Dis0b^0}%oQoN{2F>o2A
zS`n2571tE8BPi7<a)!~DTE!-c{MRYwhJe&7>gXzwZ^vWL+aJZ?LB65*_5!-vq*${T
zGPe|5nr&MYaSD(&MNBSa+7(aJn%tqdGYFR3ig*gXcPcW>u<?!}Bm*d2igxltcPkRe
zq0pl^NO>-I6_GJ8=bl1Bo$6JT1%l<iBAzl@`V=qO8vy!1@r)k!JXFl5<jj7BBR#bP
zikR0>8dPM{?V2IQp?r{G3_r+-VqhBTM-_k2J;6tcO!6s>DW16vfpNwB0$@%ktmNI8
zRPdGodP?y!h3Tgi8^{f}UztWOeMjX#p|pEApiCjBo|E$5lW25SE~jC1QT|BVXIG^w
z`Domfu4ZUDtX%sE$WdkZ6$p4J-+l%x$COLH1B<uvQ_2hQQ9gAUEWS#H7$rYt2>opS
zO22F1Jgz+R5=JyYxsmSL1S<Rfrfk3y%5KUH2~uW|+do*jd@kfel%HM&PpEP~Md(f{
z&wHVCO6f{DYhlV^N+b$buKWP@o>t!M0EtjC%h1C}B_jxJXOu^1O^#BAi2)X^{O?z^
z#V8k3^!luF?*F5~%11ls`vP&wy_7W*ulzX@wk0T+y$)l}DL2ydov8eq-p(YYPcKv?
zE8~7Z>AZ3!twR@-b9#WCq8uU6R3*0*hNdao>cEn&%+g|jGL$#S;eJsW+X&1|<=7Lz
z%u&8Y?!;W>&$Lyv=P9L&p*~+3xela28T|>cFDVPop;V~+HVvRf%Knq+cCqqcJ;-IH
zC<iQ8ltZ+WDpBUp!da>`X+g@A<{Kd8%4iP6E0n*bL2spUBl)PWDxapT<|<{40#;Nj
zT{i>znq6tW2+$hk4cf2QD$ksPV4X5C1f>RL6(ut^D$7=b<%Y7Db~H`O-zW#>rg9-o
zam~sF^f|p-%4e#eqDA@n3~;t8eMZp34yD&LjJd5WrF+Dk$}LC0(x<e&4d@5TW#j;P
zsI;G-1^GecHxy(YQo7RwKdkJa8#E*6FEouRm##%eA1QV7QJPRLRYC8hat-Zarj&!!
zwf(Blf1t@x_3cYQIiR{nA>xCo4TB(uROOoi=A?2Y3y-OOeG4d_s;d+;@lpxxA3(jg
z>JD8h@=-A|p~+XJrnt4A>b@^j_^VvWp>SMPO)0(ss+muLGf>40LfZ+I4;^NMRF9D#
zC0MnNZW)KDp8pF9PpZDB=i-#=-OKn5!c<M<vItilrnH39s=Xa3MX1bs?NA@3%Jza_
zv??eIjWH?(xs=bUd~d_jSk*2Xs5n(KWg*6^T#L}B1eN0zu$)tUa{&U0s&~Z@Pg1>c
z5^c$<h4WE5uS)w6EEiO>_kblu^*H6@rK*nHf=y|v_sOSoQ57wqXh*hcx(3A@)%gt|
zxvG>&3}T+@{XbF4SFy;aTcBF78-s93b&L}E3su=G09vGac?g<{RU(SIUshc^21Bo?
z!YM1FM0JREv!$v=+BlY}mVF6<a@E&|z*3>|qoYryY7&WbAI!e0T4zGBO2w{0W3}o5
zg*R(e^`}5?szjf|;AYkMY=6%u9(!?d17$w7sh)2`-#S#mn*e@WrES2_bgF{<^PYI@
zC3_6rDC<!jrftMsmB#_F^s1665%#`nn=6d!Q(ZZV(gW3D8n1_{50jvxU*$q^>jBl?
zGFUpO8u}ONhg64;qBN}9PP^z4Rs9b1{*fw<-l{Q`nHGX^mDe9=n^472vfZTWKRXk>
zm{Ohp8`#sTnM54aC&=--Umcl?Hb-@g9`Xm&EA~S0pxWU-R31|6DVf+weY6Ll&g%Dn
zgY_=z<@6-Es{4<F(@j0|NsyyzCFPtRQ!k)}-&4(<gARJBUFZg>xB89)W!w3vKPE4-
zuli6XSdXihH=#2D>ID>42voZ;fqg=q{tnuL)SL_m2CI?fghyBXIJqoC)fIL4MNg{#
zco!&P>UHFB4Og4*f#tM%greUO>bx%?9;tri9jHH}esL0JN2zD-AlH4g`q$HdiBbRX
zJ7CVL%in-Rth)L!z{IKhj35c>T$&BespruEC#pZQ047QOp%Xxp)hTq!xu70#fWj1Y
z@>N)os{Sz@U}@?X)4-Ch_KSgBhI)SoN*C1;q%TYDiKvi$cDDMtCJbASI$ns{T(x!;
zY|B$muSM_k)gRJ^yFksL`yQ9or{BX^Tv4B*tBED*g%rXpRqrHcMVZ?27}_e-O!6dD
zs+YE)?W)?7ZVz8m@8&|hMtz1-e`?kD$Tw4`ewFsN_ImZbOAu^O?<|MjM)kjRHTZ^_
z@fl#6)$wnj?Uvfdh|aXACDYK`s_rHqT$|c44+8D#2MZz4q5ftMI6Ku@{@}c$zDY^u
zUFzdCXzNyYk*}mjEl9)2+*Ru?g4|Q@8Uk3aU2Wb8P50G46kvL&j-$|Nzj^^3JO|W9
z`bN^A`WG9pht$0tXd6}w=<G78mQm2^ky<4I_L%z4+h7@24~bAYp?28>>}mDkd~iBw
zcK-iNs(JkdR61&25WxBanjmsFAJo`$e4yS*6Eq*J&YHIaKwLCY_rdC_`JOxxZkp|p
zV0G6#O|IRen)YO<@X(ZqVBs;%#*1L_)OcG#yfms#h<j_QDG=tPIY-}$@z-pLLFI8x
z1UWzgG*NVt3DnG`)$oL7%03^p!J29hNQ7wkxgepMzyOd_n(pV(-!RR=D(DT@{7Lt3
zPis;)Kz)QpQ45$zP0X8Ui_-MbQW>pzZ59;9Xr8C_@2uu~FR;XF^w_%2j?*;I6rP}&
z^$zr%(@eRbGEuW`D}~OIG;&JFOV%i8yizm;KVsBVHKRtrq-l&xF~I4X6~vOEN%#=*
z7d6AAH&f#l3JbF|e^N{)TeCD8X6I-&ccCp;GcpWg@-zx^Fz0K&rJY5AM(hsgOPc=@
zp{P)^c@?=1i!^2{R1|BXDFx_?ChHRHF3~98fx=SFt1Dn>ndUD#{+4UDxr3!bqdJAQ
zO3g`EU|-dwt^!(>=0CbRTCG_V3-#ADl@yJr(X{;lfm+SHD<E~6y%c+@*WCOIrR$mq
z@zXQ>)$<;kYd3rVgd3Vyc+lLWnP~;NsaZiuu(vd)Xs&3{ykCHhw`!^vpsh{wGKEFj
zHOr^as}4;-6*_)f^Y0gE>(rbgU%(yBZOUEh(%c^cbhjpzGN5`ie^Nl<uBMf?_4hQZ
zy3na!%~pFUYVT|IJP*>R2_a{|1I^CQ0n@MXZ-?N3X6xU88Prs3&^DskLC2?2O>QB`
zBh7oUAY+=lw91WZo}-z0LKFTC%%0TbkY932Gn*EoX^kgMBM#cT-=b~5)?|iyM{RAW
z9TEq$#bm`n?UxQ<J*4G7iApE!ca+%RtX+E+>Rq%6ZfJAWe!CIoyJ@vU7=*)G8|`k7
zX#X{%<gQJ<2)U!$hqr<4p*>57p<~*c%h4B4t&|+(UfSKXck|Xd>0p|VHYtj7h<vq6
zJ5lu0zFiA6e{J=0$RF1>#se)t`_yTa0<|Ty$3CHb{0cf6q+Owg6~S8eG;9jdvgx=N
zs=e9+fs@)34?)7UUX-<WTAM_!#0YK2i{OmZI+By;j5h8)phRhtFe%w*M{8%&BM_ra
zngjJ`wU5ZP5T||NI7;!_Sy3Pf+5z%2Bx`qgL+^R*)Xy;Hf;Nl7k}2Ao{pew;R{1Uz
zrfKh%qAgv!h0gIATIs(4yQr;Bfx=AfN_sr9w0su8vb8tps*OEIJL`8e=4zh`L}Q-z
zHq9#e+JERwQlQ=XD_AdSzghuOsGVB~6-C-m+9(xk^Cls1SzB5H3$JM7-9SpTvniXb
zR9i$(V41cv2`uH>*%c6|&?d&iv`TH*+i1J0ZKH!+m0i1L6cW|i=f6bpns$mtuSOeI
z1-omtmuM$ir?oqP)N9Yu;r_bzH032WX#E*LYt(L}kA&XP22&PklXi&_-M*<!pvSpc
zi#Hapk@mJ9tZ31etU+6=HjyHhZCW$kcW&3(XHceTht`koVBOaK^f-7rwSjXXct?B7
zhRQDO`81TewJDSm+oN?LC(&JP_gmn+r`<`rkY4Q-Z}jQDb_cBwecIvIpzwkAt9vLt
z)Rvc^)UO?;-OGUXZY~4{wV`dWcSzf7e;#yLtEGe4h}MnHjAPoz3s4%@Hq)kHLR(J9
zv`OtQU#OVU?m^<q>}hTLD*$!S4LG54zwSsYKpl097r?>;x;JU9J*ab|nd*?Poo;YB
z>E8PRW;^R*_k+_#$EL8Nt8PXr#c$kn%g0bWtaGl0#1WmB2-xnrst%B&IvYJ~9=eC?
zz;aBNSOE(?b+^gi?WJqYgE8K^`8%P|N2d!%4}Ep-Qn21n=S}O1zwQUpa9sB><w^zU
zHd4k`pw4k2Sb}u{a`LR4)ICd?5~p<k%!a}+-J`R>4%hualgVk_t#z;|Lgz-_lStiY
zF$B-(^2kFTrSt8AifA35;>9t#T5`pl)m4!bJy!RKUf(!fM-1BHbw_5w&;(uLVThm8
z*{(oCqVA8e8F>GabhFliCt2rAhsE={%M`c0pxa2k&lKI?PoXkZr=X`hO~;}1#B^QO
zb?D8|`F;a?FY5Z)5XjV3)x)MN-K$|xk*&M=I^=S6o35ZTSI4EB8F{*w=c6)Tr}6?y
zfo`x6ZT3sLKj}I{p>8iZmy2}LS7CRtE^-MBzO2jn5Ik3Or$2yviSCnbSW&9GM<>8C
z-FixgF4y_`L7+l6dLH9ksoN+3xvG1H7SJl)CzSA6t?SwafonRM8Ynfo<OM*f)!n0)
zqt33oLOcC>-OF^D^t#UNF*G*lhG{Zr)U~dJr8jg#o6y#x`*9MQ+H_mUY1FR!#Sv{C
zx*&RwZtLdI^@mQ~zznFkqx*+8gk8ER33}G8+wcf&J-X9;a6Zt5o&`$3E}0(u0iFE=
z@^laC9#DX6M3>-<K8@<y$*cQFx8Z%*J*M*^_2as4X~RCDTX`R)N!{Z<Xq(c#O`Gd!
zT@=mP4*FOclKuKd8A^`&9&$w-&^OU8;-J2(6<s={uS$XyPWtFd5NG}D*Y^R`MejyO
zbXWbY-@)UipScWOJFMsUx4wvDl5!aG9{Tl^HF8Y9eKk~g>KEPs@zV3@5%AXUr<ksf
zzO@XMzIq-Ve*E+YW}}Dx`j12qKdyKF1egK(`E4M9dIt67g#IA~WrFmMvFL8F{@6GK
zLiEqnKvAgv`v;IasUNiK0eVV*<TsEoz5f=}hU?@0f5On0C{c>gzZi`%jMS%7R?r#!
z;7n9T=~wW89j!M~_IHdv>T8g*`l=UTXskYru2012+ZV%_c>SusKoa!3*1)E7`m5d$
zPt?1uKxLA?riNDNWc_n=>-W6=YAhNr=->SSjVXHl1+=B=t$h$o(_b;bigf+U87O7w
z3%<c1T-47YH&nKMkOz{ZkJ*j3Tzx$YD0%wJlxdx>?{Px!3-laHcfF*)Nr&P>{kEUL
zQlxLU(>ASG|49sZF6%k3p!SNMKLnl<eHz_3DAlKG(6uuCZc3;x*Vm>%MTP#Smtk+E
zeqtd8;i~>5m8$etpMt__y<sOzyQZ(F&`^#3pG6R;)xUoSq)zX85h(Tg_bFg{U4KqX
z|Cq5sKg$`7jr!O90dqs&kq7lndTk4MZt68ZpsiVdM31q!rGGjHEG_yMlwfJq&!vf?
zP5(UQXSM6wFF;|3-kH{lJNnO7!?Z5_SFeMmTW@#{Z9V$e$@P0zANVX-?&-x8WVH9{
z-);iveSMS>Jbn5v^D!0=^v_ak=%L=S2c>>}72OpW(7RB2%b<QMWws9K`^Ygdtl!ds
z0UFVVh680(|HmwFKGJ_khK}hQ$(=l||C4-E6Z*I~U{31!w_wGTK95c`({}xnv;lT7
z#87h2euE_#wT_0e1>iYg_|hMh2Mvqn0_~7tJ|>mfP6qqmu)^68@gFK(3<2>Vu7+PW
zL6e&yj@<r-4K{Me9x=?d1I67iN=XSv4L>bK$-}Ur2l|c~?m0q{r@_u8mw=aH<G+yb
zHavU)Y#+m%emn`jhM#y4^fSCT2-f3<*C_-NU^w?aSON`?XbW?~kWPooAcJ2jNU)*r
zF2F(z@(pMUH55fa;H2U64`JFVgQyghVTOpGp+4L&BL<bH4IkKZFqRR9MHDxRG{mg~
zIb&EC0hlO5wirCohT0Q=i8V}q3cYcLR0{pY8-fC1Z-OEAIk22FY#Re;qT#U&7@A}#
z`4OdL!&V=#oHqzaJk{{<8069n!N)N`=>|(FI5Q0=U!!AEmSJ-iY|AzbQFuMau!A1t
zTtnmcDCHTV|ATzKVLtg<3k*YPXuD+CIRkQqh9m}9iVRJgK#C0tSM=qwA&@5WD~9^F
zz*%C5qM&H0VQn`^nc>hi=q)$Q{TThMFkDTfTb`AM4_1Knsv+SqfL0l{(rQ|5Xf#6N
zn&Efy!`2wAeJIr$#B}+p&JanFt$M>La!6h`cy0w+gTecIlo}0RhJxjWp<^jXlOgmM
zn0C{^q{NbD!#{K`xn;Od2e}r*-Q~1HZZ)vE5NtEJI|8)b@Y8AxTZcjWBgkz-)pkg9
z8X71xe8=$G1S-1>Cn-Cw+wdoKw8vmtg37ywu5zH<Gko(MO1*}Q^s$Hg2G1#!`V4-n
zpzwjAp9}KPu#F~|e!~wd(QEsF!Lk^vgN7(dHXAbVX~`Hie6kKaBZj&S&^v07Y9RQ?
z5J_IYF+<2YbZy+wphw$;VVoY)Ny9H^P?|Cr$*nqV2%}^O2jjaf06SpZTnxE`MtK;>
zA!8Hy9-NG;Rp4~C8}mLx(Z#r?1y;Bk>nRN5X6&Vd?_pyW&1^@E!E{5)-DrCcHXSv(
z^`Ycp454k+G2`yLfblfGK#6Q##@1PA^EQs30H%*|?E;|q8bir1>1R}~2k|!s(p+@h
zxRD}>0Y<yR4aGp?80Ny+CycM`Lv4_;=y3=J8=YbS6JlIK?`Ej+J0Vz38v7|!ddm1b
z9rePDODQ)f-1s)-GM+Ya>8*+|>TUxw(ij&H@iWFc+Pg#<Jw_oAZLFe{<5=UWqY#KQ
zeq;X{BO7nLN}jz0WBMTs;yL5y4`FGdG4XlyFv<9zH%iII_FR<C8>8nzVT!T;4^*Za
zfBp@or5Q!5A(w9ao6=b`jFRh6k!h?Rhd`FGf<C;EZTz?Z>T`_V7PRFWGbkdRXFQca
z>)$0~10@F)8hw)iT4dx??6KHb<&4s0;}%NZx?&uoe2Ws}0&@A38p}R|y=BJSjp$mr
z(Zw6$6~@mOLt&+H5lv86jepa7P-V;<fre_Mz768njIWnNpvIV-5Aj-K{(H3k)fvBh
z8Mf6MwG?~2Zaho5wGGA_qcE}2IBOZuZWxDFLPeADi)5hPG**ew)@&Sp2bH(*8vwM$
z_~=`h)@po%0hV?n-hRABM&myqcZ{Vc0NrJbp{w}a#@BNo-ec^-LDfF{u5tVbVD1?U
zD5BVFeEU_D?i)iWudL5_h~jGxj7|Qq;-Qh_0lWK++y<Zx8JknkHf$`W%LOCGYI<)+
zjr|KD{>UhxK^QZBv;#lPxbb5h#$v+wBc*#x8ZDnfZpv7?9fsPcjh~TM$-%VZCWxcy
znRzhrfN5y~Bo3Nh90boH(~sLB;bf}c3l+|$2{))XW?CTt@iav>fW^!7@;0z|o3=$m
zp^vE{73zIWp_KM}-1H{JS_4eKv_m}5<h~uyCrrOTL|c&Ev`!7yVAJAp6hlnM;{Y0J
z+CdkzPMXR)FtVpir)e(`X7X=GDcsbW517-Yb#!GQ!eqXK%1G0B3cQ>%1@}Qb(PSIN
zP$rvxxrx4<H?8^=U>8g~dmxZv@_ZSJQcap!AZaH1S4)7MZW@{g&<xYHPW0lUsV*O^
znI@m#z>{TC<v>2$^cDjwIi`<Z0BEl1JSAr3nc~O~n{RUde{{m6qf^EuQ(-2IDKsf*
zD^g@C-UgIn(*bgYU&a@NQMzJsr<BnWlZ*Wz<V#H(L(y1fa{e27%T1jx0K3A}OyS!~
zlg9`uubP;*09s{w?HQ=3Hf@{$%Qe&Mlqy?edNv<zwI=b~Fs;t?0vS_p%9@9^>n1y$
zZW>JaV<<J6e(eS44b#_o5N|du*HRM4EmIif^tPDdzXngMDcu)?*k)Sl2GiP2Yo7t>
zFoma}^0w*GKA7KW`fnd9@0g<h!^m`*is`0ow~0kjpdQojOpv>#oo%SRXY!^r$zIbV
z85G_(IYdBTpXvTXD0*NzR7!E5ho&c9Ku7yc<`?mJ4ww}GfoIUPxgPREruQQuIBZ%^
z=lc<pYA4!8O~%(@#Us-gB?XO{hDy=jaZ~7Q2uzrU4?+E;i8lq)rc4{?2r+G1Lc3T8
zv-%xW?l&*n4Hif9Z+qw~2M5e?6jM5A_NQ3KA@gNQ7jZH#<H1B{vzs?6-OQ^?(Tl_8
z3%6j!5%bFR(CcoF41wHHvpY@w9_FKTOh0C}21B8z`O~*Ryv&<sK)~BPi+sC2X6Z6i
z`kFUWcAB5L=6CeW?r-)ULE~|ADkUofm=BuJnLzWC<cvOH4q5~fWZp=>eXu#5c3>gq
z>UY5zYW^b(l_$+V|34ya{$MYx2s2BTz}|54!5GM$How{lfe7=G8gwbr{CxuSo-toA
zW3;2p2`9l4Z8tCP2TY9lolW35Yu@=GYGcg{H^GWH^S39#8gGtV2ul;pt3!c(&O9?8
z>J!ahQ=BTvJfEJRWHXPpK<CX*C4*crzePT<6!R2KP^spdivgWxK1Fv~(#`L^hEj%^
zbr<3n&GwLd6f@0c+OuVu&nyB@wz-RLOXry5D1SEB9BYIzdFEA0NaUNprn?6P<_6mS
zUNYaLOzJ}OVY=^BWDc}~6q^@6i!NO@59v_4VvY?0XNmcx(*P?qd(wUTGV>C;QB`hU
z`v1-JRdc~56t9^b_d-RD`2$MKsWtDS@K2rj${HxFH&=uJ^tzcf2!##i+1~@E(Ol7i
z(hYO>7N}@4&sYJ4H_ftcjA65R^d4AlnR96_X)((>(9c%0?N6YznO8f3v)%lhjy63V
z=2heuxNQ#m5@?;~1vIjE%z>}LiY_x}JJffZS8jkrkJ&~J)4S#(+KAmV=N*HEz2*nB
zvAJ)4{yePcGjIME3LlvFu7Re9<~N=OOTT#wT{syqr_i)BXny)C#D~o4+^6yW4V%}5
zqBvqsXax4CSwueQN9KDkf_2Pn7zf(8S(yoz3G>{ipkmUTNlv6G^N+O<m^QDX6RLxy
zk}{?CTUK|$Y)8va<j_83NtgpLC(GhjL7XkGt%rb%rLr7tu9jjr7x90CEt@C>&D~N#
z+rp!kC$_;-4-2CQJYJTX=P?%EmVUZ!>|<$Lk0JH7ct!xt&k{I_Hh;^L@n{RQETQf1
z3Cr&jC<R&iDFrjwQbhif5X)T!NT?<DML?gl%%|hUDT|19llCx6Aw_D!Ei>rlJZ)+D
z7+s67%);JycBJJi7I@BBE>Ju^%JRqrm}tuxDL7*+Q!;e>tYv>CKw~XsucG&HmLEGI
z9&hoacPzp3b3UNYSu&eYO0>vd09cYmwHGAWa_kJ`&f6`I=y-I&vf~Z>%qf=kWN1pY
z*l8I}vz#E8RJvuk2`m|w*?$A=qJ>Xh@=VJIv|Z1#ET;uC+w$e}sLZjnwL&1*QrQWT
zXSweKl5eRMfD~9XG?!emY@ivf(30kf$|8&XVG(RAwutYb_Oium5xRE8vYOVD5{tVC
zq}1Z_e;0ryw-4&eEvqO)slpOWuS2D!fSi3-Ejyb*sw}+};H|b4pG4a=OZYEPQDYe`
zhg_|tGYLJbvt$IIvfi?{6D-#)SM0TDY_NQ~5@XqDd5fOF8<u$$Fs8|3r}zG*Wy3$P
zyTwvRyTVpW!!+93EZ(ai*KVmKS9FJ^$P>@pZOc>z#5*mEp1@e#vAjV)MVIAyg6_5~
zDg#Q7g-5Q{yOu>eAaKuuk87j9y_T1@1MR+L<td=`S&sXm@`1(pJkTCmhNV#0Z;_>g
z3|LMr0`{OKkUoSpWZAh3EW;K9h37^r)3hp$TK3W={E_82rLm7$mXN1&-10#$<R&b;
z8^Aef`J0~ADNFM~djF;^$+Y)zur|+zQTwgW%z?p<)-VdC9kBj<7N#AvzCg>uAuF>J
zdY!DjUjWV78ruXk7wZR6(Bx`e{SE}&tjFmSEr+cJ^35EvCXv(3-8%DASaH;<34;a?
z>p6;mAF~=NDNOBY{W2IuFY9NoLX)?3ANitutYY$r`C4a>q0-NqkOK?-tsRtNd))fj
zH!vo^8bGIoK<h(FhCgA=oq#})^<6BgvxBX#ya|ON)^A%;3bmGe24hZICz4Tl%35*?
zU}4rd$AMxGw{9;0Po#A<c{k2j3+N~xW&MVJ?X%X@(`bve?wy8woOJ=sf#<B7X=zWi
zwx5F8N!C>I1t(kg(n<5Y_2pd1U9iR%!I(5_U^hl4-O3>+Uxqb<61py0bITx?X+1^(
znk>6@4{ZRmt#>KgB*$t$1d?lQqWLw?`hf(R@~xFZ7+hc-rli_S)<qQcDYW|2LAS_S
zeFJU9)*$lpUbc$%q3w$G$ZcSkSnp&&ywqAsPf(flJvrLSt%D0dDy&b^a$jk+n?z{5
zYGvL>@2jlK$vatX{c1L>xMmIc89X)CC+RbawN?-EsMT3L$;DG|<^77b>(=M!(olo-
zhm{a$v@WPZ+YRd`+FmtTP1%sUY3-rSN3(VNR*+lPN_wnXto7k&Yq!?fLt%c0^-eeh
zZ(Cnq0?<zDuWFDx)|GxRzsov@PDkC=EuW*Z$2yN(q<5`LI$`KN>vEd4dad8nC!y|J
zn@7>@KI?=U0uQV!uE4a1)<`et?YH*Q_1OXIP4d?cT8k*&F=XX<{fx$8>o?@S9kDLm
z1JF_H3l!meWL@eD)-h{z1lq=}bAJT(g!R+|z)V`*bikgnK26D2`)!+A!Rctrtphn=
zTS6IgPPW;t=%};J$_A#3EyRE2GI*P}4M5)!+jt1%+-)CIM%Gc=c{=iV*lzcs@|cZD
zu{}@Q_IXg`WxGI`*WR`-={|&y?XR~1?Q3hP1gD>ErUNSdZA!Xgb=>woP1ymqx2zz6
zHf=k!2ix}O(UlOJpDQp!ZM*H1cXZNLupK<7Y`Nsy470_}MbE-*Yt4{2ZTpSVvLkFh
zXTcI_Tl+S;bjB7{4P&BgcFH-4wypmNl`*z`??L>mP2mL+Ym1|OXPoWrWnhW7Js%6q
z1RLH7yfC)4Y*?6Rdw&PrXGpTePJuPqwwt!==WQhp;JIM?EfRt$wmCEhrP}rkKt9cO
zJ_MEccej*2oMC&5ezc3WzbMv~X?uSb^k&&+`hq3f7E%X$b8K%@Y%SN8P5$LPo8u8w
z=G(rZd7{9!;Cq_wF4<Up=xCu$77x}UTd@?HifvD2qIB7|rU+<PYzLZvU1FQ1L0h?P
zgnY<XZ7taVt+FZTE?BkgIokGKv(5Sray7R1Bv4UndukUd>uj=X=wQ8V-YclQZVRBr
zu)%gfIs>y^ldY6qv75HDlvC7fYaoZfEn7Vux?60YjYEB_?RQFPZnLdYgQeY8L@}}s
z+u9NQFt=?l(%s}PTLrB@-8MDt<9ci{ItcXIb~&T%zHR+6*xP5D?*y=Z+afkJ4A^G8
z24WwyH3`8wV*8KoNR9rFqw9{#y6WO;k(H^HnWm+g+B6$xrj}Z2^_G=oK6~%IA6Mps
z$P`efOci8`OaTRzDN{fZRFoxCRB(bgSnv1r*ZG`#&-tEn@ADh?o^$T+*}QTJV4iNi
zMnR<E&2Q5mo{wy9p|H{D=6)5>b~Bip0pr3*aDy{@7?Je<819UZYw?SCFa~#Ff;<_G
z9^kwg6?fr`597=0ko0Bz^D+$jF`}us#h)R19rgkojL!zp8O(5+0nr1DPv|QlAq)XM
zUc(ulD)dD#ez*m+NXB%kSUb$vNp<#744wfB(TtaVhC(dk$nW6d82%%`j%W0|h(R1>
zjIW0?NsKjokYfxRmDZ**s_2|c8siLoXd<2QCCdwJCZo>`#Vp1$dUR(qWb>hs!$_Ej
zzFdZpJ|B3B@iSHG<T0KLx&P_-_kMSwbzC{apJL_}jCqkTSjniQJXSSh8<p)}W^~aD
z>k7k{p4<%#32jTRGWzMH)iuV~baJnmas5v~w=kxKh!*2nkV@z2+8J+BF>43oIE7X^
z87(?McQNi~L!p}yx()VjF!X!C^)MQjz``wtyb|1P#xw&Ydl{3zg`qyiPgeMHhY{(C
zq1<CEn2fo*&$#m^#`l2nZ$6+OGM3Wjv7aH<pmBh~bi574#|)kj<O$=<eSkh?Or_oO
zFk@3DL`N7ITo@c>OqvU~otZzJhvIJL@9)DW7iPN*3VWElDB0u6G_Jxp-I+~v$j5`p
zp|`asbKGYjUd%oM+slmq7JA;y3<@auFh31-fci46^P#_w*&u?$`<Z#ZAb!l;&)|hW
zGj%CM0+{=k12mAyX8|UNiK-P`K+OBiaP0tdC>eG`nA-#(q0HYYX&J^0d>wt^%;|2B
zJjiUO3*iv+^*We8%nYN9#u4Ug_vma>4AY6$^|8!X--D+KOwn3cN@Pw7g8osaRt>ad
zX39PEr7$PIkI|<x|NIg#8O)tO!tLYC&uI~w$<$D$>;%*ID)de=tJVM|huLr%3a6P3
zR8@I~dEzh>@|e1F5GiDSgy5RPsfgLN0p1idFaL|7l``i<0=ta)8a=binavdttzc%=
zz>7*|{}eQyWAfE-riz(Od$MZgFMaU7hWRK0md-POTm+E|%(dSGtd{Ay30~AOo8{=M
zXEOJ}i%ZNGf&g}zS@Hsi;|lY0eCEcffjLJB#jDJXE)Z>G?udXFP0a3b&~Iiww+UXf
zFkg#=-BzZ8qH@=nFVlvrjX9ojknPN*RdA+*DNBcmPNp;6{as83jklYr@d3HX)KM+@
zE#^Er4s@IO#-AAV9S8F^MfL77qo|_i9&>&_TJJME`M`d_%vcEWkQqW%M*Yl{??GgM
z=`jc|9x;p8qj8W~ISmSrnHft!o-n<sOz<gFLd9^;m?H{sL(H|$!R|1#Wdvk|`F;$%
zA7!4Qgy<O4ao_`Z>db27U=+JqoF)(#mYtqDdsyz2@p5H7y9T>%te%(Qs5{Fz5q%!4
zQ&WKE$r94<<HZ_fgY0F^Tm?yQR_A`8_^{@f;e{`2BW2z9v6?1eEc;otzUcE~c~!tQ
ze^#*L70>|IKodX%S#uj96U1sc1C3x--y)C$tf+Xvgs?uRd|@a{I0TU}mgh7~LO9Dk
z5q2Y3H59RnWNoIRorA2vP|VCB)@26BVb&75Z=+Zr{PzJ6)+|~T9bxUT0yBoyaE0E*
zu`E*t*f`dd1aR@JUo<e0z?wJ@CK6dS6ly=pTJQ^g*d*43%`kY3HJNrL$t=ICXiQ<v
z`xIkJW&J`29n)CjJ_cAi>lnSfGg!t?fpVPnFTE8qSvuM`WwDOA1LY*k!;{{{Ijnjs
zhL+3vi7M((u^Om|?KCTq(r9N`QRHbJ3oCfM;8`0dL%)Evl5V_0)<dejFJh(bg1^PA
z+)RL;Wp&VoxP)bU9wMcz%xs{Pu~y%QdO2%hCY-5YO`t4xC986nB5&tdGv9(@6)Sx=
zI;&ZlO%SbNO*;;9o|RvN#tW=2Htg220_eE&MV3G1>*`op^i$TejK5%Lmso$&Zt61Y
zaV;9JuwMEBqi<ln^#pxaS<&BtTx0!B^VG-+T>!8q)*1@fJDOQ7l-+G%Nxk4y8!JQy
znRZsimyqdTdC~5qlQn4wB3&#^C`@#-a&pmlgLQWhpgpWyinZNjy)qGfw^&p5K=L;0
zX&4%NS@S+bV;`%GlHqq)sdNtEE-RgaPWM<5lr*{TU_GNO-~(2yD?}f%lpEo9KkLm9
zzznd)(lGi*EUQ0U8)VIQfyQIjyVv326V{qr;GVLIKL_`W_2&;DL#$J3SQ=&({tdkm
z*70S)9A*9THpm!j?lFisvuoDF-fs5jet7S~cC^!OcMm&r12kOOA5qn<8#{u^6x`W0
zZ5V|I`)oCQ@??io7Qu^sfF5Fd+0Tig@6BFW26Z3yn>kSMWmg2i(mwXO8$j95_FjcX
zKlaGa7_UG3UCKBIuxH$cNFe*?)fiF`yVQ{anP4`55kL>HrOVM7!j7a}Ybg7r6nGlO
z_MqCIaCR;S9!9WJLm(2#p5X}-2icdXJmC;~It6GBvuE#sWEA@zRbxl9*HdQW2zwJ%
zc*n5K^tg&;?->sg$Nq3HEX1?#^wE`+z@GOKV3OE>&^LmPvCUtiF_|4qUy@2=OJBgS
z)7jd^a5#glrS)G9yDkbMr`abcig||JHVKV+Y)Jt~KKmAJ4+_|_*&v1N_dft;5qlOz
zf{WST(1Fmi>=V_%EM@b~QEgTk+jb5vmb1r_p<ltyqz_0`vft{&e4S(4{|By`ee@9&
zYuJnEeSMxiu@vSnuwQRMUoHEqczA!2eUZ|ub?o(&pr~grqRjp!_GT0MF0<FKgM}+>
zxeF8;*uIp^zRGqipzo_)WB)Z3XpQVas{U+Z$NdEp&1{cSxZlE#rlRat_Og56uCq(%
zvTS23q5;~@{*@xh9qc3Y!*;S&-$1>KT|z%vH@kqAPB+*CF5r6D3!|ZTll_otoNuw8
z`vY7bn?VUt#~rpP4x)G24Oc+!vEPk>Z}-`oGJ*Dh-82mDAzO438vX3_5oipsH!Q&q
z`-r{k0vZR|U;G7;$Lv{7@aYNrrA6SLvi+#${uz7gVobsiJB<#84YONrqj7|N%?E}?
z*^}Hs#vJSkr0>kRwjKuea0)1G;mVmIhY2^%-8Il~=h$CHp9iP?I!t(Sb}BFmFU|}n
zNbcpNP+^-l$73NZ`EVxx12A9CDM~Bt<FtGYz5Sfm=}!0Kh#o+}pTn3A^#G0&)lUa<
z92_QS5JyO*tihakBV-P6=F;5}!nq`dVkjqZDKx@3p|r^l=ScrM>%;k;e%MIP1=?&J
z<ZPnAdlY8_)u}~ulIR6;gcEQBU~!ypwt~cSl2$??fn%mhktB{H0V2mZ2@W0<lQ}Qk
z1a=xnbqTHM91l8Vkii+H_gEIEz!MtToR}m`_X$qX01W1EF1`RuxtyR$P(Q_S{v9Sx
zb3UWB{~68*U4i+WwRE_kfb$Y1c?&teaWIHt&g^EWpXKaa2+R@=dzd0`rJP_YbSdK;
zr=P2W^SBmVC1<M?4xi(c9E9C!PA&sn4M$Hkd*?Z2wD7#Zd20heYdP(d;j7~;qa!f&
z92R93FLB0Q1K4Fw(jjnHIOjfrLIcNR4H_Fcw>VH};w-k&0g-0T^R$m@;e34&c3U}l
zv@N;L`6U7xZJbLd@cXoL*1Ulcc5qs0wQ`%op`}|d=kGF*K29bj1MYB6P@3f~$4<NL
z`<xQWLp|X1z76gn=V%6IW`Hx*59*IOo9H;t6HYr`%?_uhoaf%cL_OnJPM~v$<C=la
zVNP#6JRRZO8wNMZ>7jS}7>D%@8lAcMbg}K`mc0rE7jD>};M}<%(L2h6+pz+Tp4@-w
zD)HjhKZN>Tu1y5*y}45<73srWaR-k2a_9XQ`QFFfp9uE@xf|aB3F2nVglI7LG?m34
z;I_0uBZND>0idDWKk0Bo7`KLYGT~es<wYa7NwgV^;u<Ob9?czF4041!<rM73aM#d!
zESCG>IY7s8hiDZX&%MwD3klp5DM;cB?sM%JS_*gaSvZ`^eTx!8X<Tl|{gv39Z9IU+
zOz!e>h-PtlRGXa5bsYsv4%g**kX$Z*3dkvL=yCL&=JqUxqi49aAHeNAuKUku%;(<R
z1CavmE71Te<j%bgup({<RW}rKznzV~v)qp!p|OH{iQ>AI-1d!7KgT`nNPsg{++ZqL
zuI9c=d#xJo8}uwX&yA#tf(u-CCxF&++2??EnR|sw0j_YZ6d7vZMo?JnD);5*Fu-fv
z+8Y3E<mOUQV-wd-sl;aPxe{1t;p!>H)xm9{%~>aRHZ7~VxXzxmIPB)~%Rz2%xBUvz
z!~Oayytv6-&I7r{{g?9Ix49=NL4S|Cj~efD4U~g?z!e>YrH9;A6jkfzzBLH92e=|y
z(>~%Feu3m5w`4xZW3I{z2A^?Py$EiId+;cH8s^6TI1V?*2v_|%&_=nn^B^<E4W<;C
zGw(x+H16gFQ}WV<S1=hOdw3JMz;@*={s+X3R~ikGy}acy;JkV7&;r|sC!{^4FYggW
z1NZR`_QBwOUj8afkRR`%H~jVIz0-)f2;i~4qO?#5FYp+K9m-3i=T#UlA|7bryshET
zh~W9`hWSWdlmyrZc}qFaKg6rt027CK#uXSvEbp~uD8%t<=wgfK&8KTEf!9ybwM5>h
zZBReTdn^M<;_)s6<rwcWJ!g`6-?swHk->XGj$t3?eH#RaGkNNpXwBl)Q?MYLcW4ln
zPVj!64~>(&KY4)3;n_Wboy(hb90t$u#w9^LkH_u>m(QC+Yv}@BY9|y5dEyAD7x5%+
z04wHwMCa(v@^;PvDdCy&Fx*lH?+z6;m+`_WSXRy(Tn|#sTTRi48s7R#fH}{LE5ig`
z;C;%2rCQ!aT1s5xO{1(~9j}T56ZO1TP6G5Q?+1G0UE{sv4v|LQ9*SHv@q`jcHuLHz
zLD9m?r;@)`-osCzcb(@bqg+N8FE1F_-MoMqAUAk3=v;OWFONQ#b(8mZIzVsn`o0Fa
z%`2v?a4*mLKal&pY^wNp!1JKE<wM?LI(E>{E1d&N13UyKa3S)p(*d|aUJR`o9`jo0
zLGg^Yo&r2WJf`Cl&|%(N6x1K#ou=sAD6e!CCSi;>l?!J)_<}t!;mO}~6#8C#4n_L+
z@~@ddy!nw=pzgyTFNcUPf2jd>_wn1WL2^GoHwu`3{LK_B_UF%}$Xft^vmYD{<QLP{
zBZ&V|EiDOx`FUZ03E}(GsoGF}p$#x${5Rd<cR2qpg#aS>db;Ef@~`zl{}4ZsYS9k!
zpFIc3Xns*h;Tk;3uF~!%j{o5cAc_2-=>R**e?*naN&FeKs657BtpQ3hKj|MdrtrmB
zojIlQzo#{L8sAd`y>$M0dPpDVi)c}p$*-}1Wbyx`N`P#>FKzZu@Q;54a+2?H8(!z~
zZ}1^<ivOvD!icB&tG5FC4Bu4_>^y$(w-|Ol|C4Vqu?74a<?yMH|03n$iui|UtyavR
zYR7D!<$ppio)Uf<Ra2GnCw769@sHATs+?azZ-oke8U;uz`D<w_dyYT-Ft{o{vk@ZI
z{5Sur@T%eWeG2!_^To8Fxxl|d(eYaTQF>q3^O@&i;u1ffa%z|PS6)Nk75-JaWE=Qx
zZRoqopYaj~(Z~;_40jWMK{p24%)d<AxE6lc4CuA;8|H&t=YOUEW;=f}?U*|FPZrV{
zq)vWR3)pUcsSnU@@Ew#s>*1Rt;ml3`?(4w5#lM({zT14|K8&K5zw8T$+~H@8N8eq3
zZyg46kH4CpQ}_9U^q_daFWLr?ettWxg$MWpuYo+`x6^xmkbmGc*n7-h>O$}NC;VSu
z#Y7G9OJ+iGn6KOd#S#A3H6Ww>2HK^J@lCs-?=0ByDY)GN-X1vPBKY4fDC`kPDCp}d
zaQY0`Zi0gc(C01~D?*=#pmI7CJOyzy`Cfvx6fxW@cqa?jvA5u3%GUqjBdA%9sqqzL
zc0qBUz?DKf`vq&(0Mt(~i)!cm1q(k12@s@-0TU<)F~i>=!9UkvB3Ljb#D6WW<9Y$~
z!USQx01Fp<o&ypgNS^@nk%A{i=p7XNx*X(?;5%=aKP-s(Z)qy{{&UP>wBVW-FpmgM
zP%bS-@G`x4Vg+}U;Nk?;YvEbE;LtF@5(ERQAekiSnF<TX1S@D4mMoa!*aYkpLA(#J
zQw6gqVv#23ehH%Kg4}iRK11-a8(@wLqG`pJDR`dhrm_Ud>mivfIMIW?6M}t|y*?>$
zqxg4@pq`d-xq`nHn5R>MUs?cmTHyH=^v(!8JAjfWxbg@3@&zxd9S|)Lq|-jAQ1CMS
zT15iRCvd-5kVM55X9WtXIx7+QQaGVh;OP&pOt8`)dgTJYH4v!~_`CrxDh1nU#db~*
zL=Vd<fsx8<ss+&tAyOlFHW%h=1*<;+xhUxT5Z>1bR^xA2ajOVICqwj-U}P;sFAL6|
z0=XjCLy6D^!Td&8x+<_zF5;RXU=&_73O<>NAFWBShB5@rg1Tu?Xc4s1Q@vGipVoHQ
z1%g=^OPk;#y;<7@L*GKZLr|uLLZ@IG{XSiSZX|gePThj#7PQ_Fd@~-RJ%Xexblw*9
zWP$4yEZ7F@K0)NW5V<2*x)q>z1)=oDxi5I{M}R&MY<dD`9tv7%v)(UAr&Id_g7ux4
zl1GBkB|v#BIB^^5PXw<GLH()VwJwM}6YQp_f@4VVmI8hc3qG9%nNdL^WtYYT85A^j
z7V`FjxCr0;4L<D=vcCoADok7kMK|Feevot*ZlvI#r|`=&AYQ_OO!&K3D5OY<x9}9b
zHhqM$Wgx!7f0LlTUsy*uVL#!E3t`XSAuO7N)&SvBdie(mFAoAVNZ8K82oDGcDHaqW
z^csWtP@$FTR3e3+Q`-BW@W=`%91=!Eq3^KpZLIyBqJ;6M0eVEJpsj3-(6<TDu|jJZ
zz~Y3eCX7B__yScECJ5IVpq?mn_|y9*Nw}O|yT^pAY``Q7zjy@w6yaC>7)7d35CQ#k
zVI_UcFheMO1jXaRIvQxEFokNUvxLJuj44~VjrQdygp<C7Uaqi+HpZuf=P0XsT6mSB
zu4ja^-h*DA&_QX30-=**1qM?ntfVs#MZ&HvXe}1L@h%LW70w?A>=NM*x#%ks4$^_q
za^YFJjVpvNWrC{|PWl1{&j|(7V6aL!lQsl3!jGuH<h<|~DYy&5Pc7gs3PrS%uM<8S
zgroIBr&f&ml5opk6#uv^bfUtV2H}DXkgGy>%JE(k_7Q0mzG1^CnuKkXsAv|xP6bG<
zLPHg>uM7Dq^tB0((L1$Wc!x>=I)sa<7OYeF7NU_(-NN4{L*a&SXb!-7gc~T<)+<!3
zfL@<)%3Z2dyd!j%!;8DZdCx)Pp0K(S!+s!KbqZ(?g)y&!>lgNJ0vQm#y$vvrggfwU
z7pFntcU2I1EKH?<<5S_exftj(;mC(@ZAe)94#=>OMRCg!p`H#+j0sB?!%=5ZXahXl
zElNjiufxejw2MkK_K1%9VDzq{lfS@4H<6hVz@DOPs^ahxMFv1*uV@>E47^41&p>=c
zuC&ed6)E~4vQIQ?HOPL^(w8s@KhgJ;U-uVntc7a<qQB|E7%19*70^MVttF5Q7LEP`
z&T&9=ycE8Lh*(re8!GzXI_!ptex#D2aM9uO7;l6~HVXzLMe!7-Iw<;Gi!mJ%{W2XU
z4vScnu#OV_yAyrUBDXE*J0hAvFWMN9wh|;(#Ha#voM@2p<nf|k^C6iaih3Ou5*?xm
zJZKyhy|DnECW+ENg8RorPIP=bSu~e!{}fRheIqPYltYV$G|{(bF_?5wSSR!{M5C*q
za9mVn1!$(|_hpdG5+zYY>ZHim9|}35%AX;bE80YFjx!=2B}Vc@RrC|)iyYtG09zy)
zF2-aOi`=Px>a1u(Km0Be$?1hzE^254Xocu;G&HJ2E5^f8wWxk2Ow@>$(UP`S)chs5
zi=rYv)ayiFrC??*i|}9Pc#w-yDbL;@dUX}l8%3`<L!?P$dkv&n^rGWS$XplQPKAD(
z=%vqq)-D>OC|QT-AIjZyidN8pj4n~<N;ujr`rHX3H$*<~VrV_0wdD3q(J%D1fLo%f
z;}Gc;4adRXK2a%syylLGNAa+`qHP?2-4jitSH=TTjTCwhMMGm0ujv=LPXOqENJoqQ
zN1}_j;mn}ufe>~dizfaIv?rqV>(TgBq&x<ZXQBoj3=WA7odf8wXwn>58WH*X0d!R4
zQv=B{5m${qXR*)(3%kYQF97Bu9=Qw=H*ptzfXrRoe}mR>9^#BHOoFGlj}l;BVuk|T
zUa?&ZQE&0Jbcp(hTj)^rK5;cI%l3=&XszWZu4BWJzxd_^^aY4{bQcGT|D{w)khrD-
zBv@>s8$ML5>_lIfxQrGw;o^>ZC>#|3{fxd6c1ZjO6$Kv_?~etE67LT{XSCQ%mr0EH
z^b?qm6)&fVRGfJJ4)n!~H!VY7g7_w#Buo@1go8UOmVSy6CW#Z@gTZ6so%94x7O!oG
zLbf=Rp3*18f72azQk=y^V~)6y0{)I%aqSO)IVJAlz|v{)f~l}{MqH;xW1iUSd2spS
zb+lJ05Qi{93dPH)0I*1$Ore=#vHvjKJ}Z7eB@-p$*jE5rD*oOJ=F7w%F(6VdK12)E
z3h@eBAXJLyb;6l*VlT>CRyoA#J1|i#Ha>txjo9fIw4N7#9SavPh=UJ9v{pQL4viPZ
zE2-|WPVE0GU@nW7Q~kyjvHB1kZ4h6+gT_Yj_w+1j60dQGLbLeod^EO*)s&lS73-*S
z=(>2#co^ysCw0T8PO;+}6)SX!tv5ls#p(wTy&(<@g?^9td76ux;w*X(-4eT=1-UKW
zz8H3U#X`EB`os}IFn>p^{Q{G4SNz#1xO-xL6HxApEB*(`2VygALLZ6;3A10k;vaAW
z;*Dt#c_d!%sDn3y;_4)HJ{CWsoZ=JlOq#E!;?7EdJ`?{y$KQs;-%`22u=rof366-b
zQnF}NoVWlZ920*_lkY4!DuT#v$*K!*+eM<3p>K~QjHbj@qQ3%zZW0;YY3`D2`r?3x
z<kO!VX!VrD(#_>1c}m5-dnM~yV8UB6Z66waB%bHd=qnjJ4YYldd2hi{e~BxFi321I
zHADg>JgU$Nl1LB3i(ttk%8eh89FhV$L{dxH>`+N2J$Aw*3_VD=WVSmbBP2hEQ@k`%
z!k-S&gA(c2P&_30ix!@TC7)AqMwH|SDi(^Ctfwr(5lOQz%*RMLXCWCY*%k(vI7uy)
zcPB`4>5FcO5*K>rAC+uA2azO6?oQ|(le|Ku)G3naahRY~$#4M_(j+C=p5rXJWC>M@
zWJ-+mEX$H`=@-qGBwN6pkl1A~cvA8%Wz2FUcjz6JD_Nlc=qX7}5%f+=Bz!2Gk<_vv
znI}o0GOBz@<V%n&ki7mm3>HdGU4r={Nk;@4izV-m!qKx58{M0Z63IviMp!CYa|W$t
zk{Qk*<q~gt?N>-zC<aw2IYo6n=Ok?^NLEQwV&F`*#P>KvY9#GvVdA{R#UFMrNcw&R
zsg-<6=f5sWF0??QPVzUcx9cSzQ8fON<os3iU6%Ci2X~bzxk5peYm#OEMY1K8VhpWG
z(s>4r&62ECkQPZE#noCRpV0&Ty2SQA8rvi}xv<nO8K47T9g-uoF6xqSCtymtCAWt{
z#D9*T=6EXwrtV8zDPr<KvMLYULkta0^-J>Opg15Yq!8F6iMRmzgOY-8KpsmL<H_js
zRN|sU-!n<yCRiGh2v4AKSaNJ58b>6Z#b_LreDETm$0V1^(70P_rOl3u^v}<LvPatI
zpdFOE)P4h&Jfth%N2{lFZVNasY2wS^_DWZ71o4($Y=mn*(ra_T`ARR*^|4PXr)}?k
zX-@!M^3qYN$_<dda0nuS($WhUM3D5sF3fDOba@I49gyap07{6o?;}_UlZv7!85l18
zVjuJ)q!CR}jFjG?x646kH-)PXOZQRSGfKLezJhW@`U5S!Vx+GIV!C6c$y8gMAPxTp
z>WNY%RplO)j-y=jap{vou#_of`a>^E8Z-%BWJ^=&-FQO!`Y0MtN*n%1$@o*!pD6x+
zTKY4Exz0#SUWQ_xH2WIN=Sx|X9x9M#QLL{}>hS{%7D<m#T)J3#tQ~r1rC-qMy+nHW
zD(sd@r%Z)Hx%8zMp->@xL;>DP>G?`<=cH3UgcnuPO9vr&URsQ#fWzs6w7wOcwbJY)
zbY7I+qpf_M)JSzn^->83+$HIx0}#0^?f({vSELhZ(bFJx?1H~nr8_8AaZPGD0@5hW
zq9j$5wC7!@H%sqcg@-ND!ZPT!O6M;Exh`#>&~=;id<6O&?b7ghU^}Gq6ENORX%?*x
zyQJ}L(C?NuQtJ1H^c&jK_DIi91@=v;+dB}sCH17f+tT)z;99TLj3<RtpY+EPaCf9?
zT7=(~j<%uko^)O+$bIPx6u5sNJ(~-Zhtgn*!1X(%J9=PgK>D^bG#*Ls-Gt1bR8WM@
z$I?ZA1MP{lgF-`3rPJ<0<e8L7f0aHY9Vf$2F)ZCZ6>g76J6xeRDt-MN`o^Tsm%>A5
z+2~31xyZ)7iC@G`cKHYNxyy!VDd8boY=wxY%&~&vdS0@&e}J}E79Io{Z`t~b(D0FM
zsDf+0vJdIX-zVz~0NQ?;Jq#j#GB+do{ADlyw>6awi@*iSIw{5&AuFYyDN?qGih>Wy
zTz^2{A=%7ys2`Sj?MGvj?8hH43DL594vL!|k<F(xYm98iWpJ^w_s+tZIN7(fzKNIZ
zrQ1J2mO<&iM46nbevZl}{sECBS$7Lyj>*I}h$PD<(sL?B*0d8IrpjJ_16-QSnhVKv
zS=K1bXUNK9VCcB)Z%_1P%2K~_U}#ygS@g!umW9!C@`P;VE$E+=<=9~`N9Mf{T(0ab
z3T~c~87TyPTBfHmp);~RT0rK>-lWV|zU-B!z%G!9<&Z3t{j~y(MY3EfwJMfPrj*E8
zSq1F~N@OE!h?L5%2T^dPOy>O}&?;naJq329td1_Pb29A$*sYRn8VAK{S>#e^)X0?I
zV-)9Qv!|i)g6t}lUewC`nqcChY!j`5>tv58Q&%tRroiPT*?fveG|1*IMBi0eA5}wM
zlYK$a+eTS*8y&-Lk{J#_rdf8Cj!Cu18b5*;tuh^jJg&<YQWa;LERfPm?Xp#m(AXhs
zxd{(DW#!(`>yjNB2G=bscL(SVSrYAXdSsL7+demCD|bTVmdyA%+`cVa<O#4|S>zJ*
z^~wHS58}8Z`;w~m?#j|>n{iJznc}_oWo{Ihejv-H^1z2OSBgXS%Wl#wGa&nlo{x`Y
zZ6CqzpzQr`Kpx8!Ya#hWrg$Bre=4(9!|pR#*RLQ$vVuQhX;_vy3@=7xS8f1hRQAvW
zZp<OubP=7-@*Ol^d*ts@afqw@<0!zm$+uAbiKqM(iuZcSjghdlSB}>w?h5(4n?d%;
zzx0Cl`{m{9AmS%Sz#n&oe0VaP36Q7K#w}2uwGLd6yjBSkESJ%(azMV47JwmgN9u=Q
zL*<K?Lo`hO`8|+u`NB-VM9AC!hhay`_ffs{LHQ0^#2=DRcnX7u<vmn-9wk3amq)bx
zTZ&yDk)L=34`bxB&Y~|?{?j;+IC%nPE#u{_1sGC-+>b&fiSpO%;Eu`j9ZTUxvYbW1
z>lFDTdg`Ui<LCfqhI|?=1dq#qr(j>Eyf+VAmi+v00L_-Cy@JLQ@?CGh(UbBEGtihL
zpXZ0hT=^UUz)s0`d<N*#@``d`o{>-g2wa}r@drr0{Nn(4Q6S%EqRm~QJd!euMe<oP
z*e#axD*$s=KC=hdCGz}(aKBWZSA@PY`Q&UgmdlU62xltf%jV#xtdt8Vsc=p%q^ES1
z{G>BTwR|1TMU8w3J*Upg2jXD&qWlZmdDY3)Tr}3p`88Awb4e~32mQ<P0xFZZA`hek
z#n<E$f-#Clc{n9|o8-r`z}=D$d%%m^@|C~Be6PIa86^AU;q*GYBTvl4B;1w1NNcWp
z@{g%3@xJ^a?Xw@q!+wW_hw?|{cE9`*)#41uKYWk==;e{Tz!xS4<z-P2eJoF{hx<?D
z8uI(8+>f?L&*WcHwe67HDGy^BmS@u6bd1P1#zD_nq5lVHyA@j#Vb?{`83MgMipPOy
zbX9b_gSaWy4no0QQ7(swhr&dGe^136imN%i6b&DM-K!WYg>T-9*%YYqQGC?}QC~$L
zC4crQcG2^3zv6F-KKUuWn*uNV6}DbD8ld=zE|x$AhX<4(#b30c30CZ^1$RK<MmJ7~
z!v850LKSREQG_YNDYzM~2%>ORghP?Y1x%#kPam)c6`Kpe9a1R0p?Fv^jW(Q7ig*S<
zqZNs?$UCBlr3)%XA*8KstU^bL^EgEe-9Pb)QxwTdP>iSWK%(N@j~L5Q#Vg&go22+{
z0-%p6vd2R`S#gh6<|zutx2s_yRk4>IA8Cr_=K-3o`0g&ICPOjtCBPh4q`U%>sc1=u
zNR}e%TR57nI6#}q6AGU-Ks%|}Pno0~#d{P%%vHQv2<%e|w@{GNiUC*HJ)?M;mV9}N
z?v+r_R}6YXp+Mp8I1G(K#k+xMEmEkK0JK=qz7^!GqM0^XC5qd$nJraJ55@?~6cupF
zsa)|jJ;^H+ec^zqRG1opeNMr93kp?=1ylf8t@xLwyGHTeS1@0zI80fAi;5SIgR4`7
zUjbOXB4oS+8kZE0DUESiF}4VUxuPhh^1uegJui&+s>013iq{meyI`VGVW%{Dlfs&e
z#%2Y71<+a)^Zvp-w<?y>;;>yYeE@wOigZehb}C+b6<}S83VMBZD^jMy?Hh`>zXEql
zaq<l+#=foCz7qPqifr2Q-Bo-?yUBZsk3}H&74;j@*RObm5+(zRm2ZN3q}V{u?m>mM
z3;sS<Ecpn1PZa&rz&%ym_!rpE6bE|X+K^&9ExU&mE>u}MqF6Ttu8k_Bu}~OOB%{X4
z;pD8etcKm)%Gt}|n~QQTg%I{AQ|Nf3t8&6R{4gHM`c`0jDraXx(M#D#4`d%@@O^mU
ztK?IHbD#3Wk5J#Qtf%4uKjk|~Q1DldqoSbz<@5P)J5c!^eF-W^si5QL!OB@&s5=fQ
z{b<b=qTEK;PN?$YTy%yhH_&H~!j(sxz(puo@584^CF23G4=QKUS4E<ffBg*;(aK_q
zUL8^1mjXLZ`3+t9@yhK^APLGN6VaEbd}f1dN0qYY!6hlDT?BVbdHH!LBs-ML{(z+v
zC3`o<l&Z|=MrWF`l|l&VO7Gtwlc7|tgr(!k*CNrFsSKxjwJc>XJ^HhiGbwI+LRp>w
z4|A1+w6i{?oKI=&)5;a`5Ghu^{yj!^R_UO)K#6kr2)rm&Ha>^OGNmJh77FFc*g7ay
zC|?xAV5QRUGbo-@j;G?;DrGh$t*Vv2z38h^{^164Ub$BQazQz^6P9X~uTc``qH;7H
z*mcU2hd}C;94cVEqMS$1n+BzGGf=K7Ik{-Oro2gShel<zgFboHq-?za(yX*igi|fb
zA&SPfD%HL)->w|E0MennMXRJv<@SFe*`<7gmQdZw68b4`D9=?vp-1UYS&*B`MRDM6
zDFensvQMd@gIsr%#TzlsyUI@}DREDE{yYrbS3Y`&?!O1ha3)$GDrd{!Tfg%5IT##J
z#!>S0v64Y?lqbqoI#cmfX{2Y_Gv&}@pbaUv(Vaf5tjvM>h;la7(2Xj6w!!Y0QcC$l
z7uCY^(A%Tx`2&VrRl#&d+C%lW9DSau)e~s{=cVeQO^c7}i$Qqms|u!DZJ+92HaLIP
zG)g}PsH(d#ra)C9C0`GyHaMX#M75Vbh7zg@350rtDus4Akt+36xOPx=zzqgtRVTSn
zh*Kp~;yhl}bR1lQibFY^M3ps-ib0R6s(XQ!q*|haQ^!=}C&FN|YRPFdrl|TU$B?Re
zbt%lJsS0O7BwbbX1w=Ab*QiS3xT?Dc<}+0<7Q=j&s;>xKwkmBY^iHT=rV!0Z)loVh
zpQDP-h51~ShadV*seYmAUdL%wjtHP<RO(q^^HgWvhDN^1>IsJnR1ri9Rj+;kjUv?y
z+ESlY^+kg#QI+>Yp;XmP(e5%;8`blctA3}aWrd3AhQ><OgaN3ZQ^n86tXHW@oiT`N
z)h>$i)u=vmh5C7iYAT&Yx}e%L2d%ZLKb(PmQI)<C`gN*OB{b?)<r#pvq^jEm^9`zv
zwP?JmdNmx9*Hpha;BT`k0f)?-T2zhAkZe_D3DMZDdXrYx9jb8y=<8HvRe<YK?fwc}
zw`$l2C^uA&R~NzjEmb6?;cu&kX`kM!GEoTOu4)k-v%04${~L<;RlO4QJy5+%bx99Z
zthb=wuUZ<8#zB>X!gG&RU(5n|qN+~=8B#SIhoxcF>+eExMCCmK*PPW}G^E|?K`Oa-
zQGeqo!I<3Cs^`$^uJ&FIY!CH&E#N%W8}k6;rOt|l$X>OdABeyD%?IcUQ1>g~Q=s~E
zIYffgv-{zFu=+Q;tPiLc(z-W9efM2>AFA%6BGfQ-*j-45tCx~Ogqr;-CNEO0I6}eA
zgX&CAcymbY{52F0tFvdLGfJKQ7o3S!Gdw_!s280Ec8vO4`t4)YX|yGdQ;%su;?-?S
zVIn~tco}_(>JKTNcvO939{Q5hZhPUyG4(16jwGu&<KbwEddUkgl&WqxNy)u5b;ML)
zr>keo$6RKpg>)+PxcVz4G&0p2gTQ5}6Y1*AR+qg3XHKYh)q^{!-g+8nIclLF&~nvI
zG4SG)x-0_bPpf@$(0E3@v<B*V>QoBN=BszU0+9ms!x88es$)th{!*l#^*dUN)pi=%
zS@l*rRa&C1Rf8*4H`3#>Og+~PT)Fy45ELuaOiGPbs#!&7Jg1&bi-#)p9+V0=RjV!j
zaJxo*;5J0gtM5{z^nzMK)m63XJpthA)w8d_nM>-P6hJ#Jt7A_A=BnE6gVt;6N9#Zu
z)gO1j?-unr%7C}37yb*y>*{aBXzWnWeHmz->V<TktxLV45(azJTWJ$~Q@w%m54Y6Q
zzXRrN^?Umv(yRWIp38meaJsecsK2KD^<A|y?IQ0v)I*ejzpsuu0+<JC!5jD~9;!93
zLvcW@z6tY>)KBPvF{oa$0d^m&zxodPPt>6cVDPDW&U;XJrv8AE14HWMH_<n&&iMt6
zBkJe$P#;xS?uVr@_1zCJUT4kh4D{{RRNqCTi^j2=-V1v)LuWu-H32p7!cCLqi%xgV
zg~dSg&}^k`k*B7r7y4eBwH!FJSM$l=!1mUBP>4n!O*#waeKnQiK=x@K@Zj2h&CE#X
z`Dyn33Q2!Wa}*i_G`}te7pVF7JxB&={&dVnYp~`_BiI9)xfB%*(Y)mcE>u$<4`;$O
z`4b@$uF0GW4<j@ICtyBOvmpw04{BmBz|ljRpXq$oVNDR-%u$*qN@PcC3iqJzi00j&
zff=LOL6v;5nvHdUj?)Bx2k3as)@-`}5;O~<p_r&?>!&+Mvw^~jNt*xBYyX(0l^z($
zn#~fB6irMCuv0aU=s}UD+4v03q-#E-GUyDAQVNCRn(SWzmZ=erLL^HwX&gkdH7&t#
z=7eS`1tLyrE?vPS<Y-z8=<io@H9ve0>{FVL+t7MiV~>UTGaAL);PN#0#=&5|X6ff}
zzd-W|Eouujjl*!eNORi<pv4-^8)!VM`I!ouN;Cyj4pyp39)sO7%^^8RxkgTb<qFO7
z6wR#Elu|a~oJN6tvcsuLvyGzr)tYs51=eUjy$R9tnwUUfU(l4kiJ{eLiYWeBuNkEH
z=_SqTW^k7^zuka`S2TW99^at(Z2`<*)lA(E>}#4$6l-kM%%PZHlg8N_cAGUZhcWsV
zO+J-Lv}y+E8@P_^n)fo{Vw<M^4=A>4CeiAyLsK~kCOS34Oz3xMzM>#<x8|MMn2Q^l
zMJ`b6(TwrH-PHJPhr%t57Z%e_w>49Kf{9*D`c~-mX&6Uf>5j&q^8R-<UaKK;Pm@An
z=KGqxv5<V=&}{!5tq(Ous@Cn-<j@OuK;ue}yGNS8--M+>%|43OJ=Q#Z8GTPQ%V<aO
zR5SZJ^q*;F*dRHinL{h=VU1@z4321CF<?eVHU4zMXiW10K|5<V)8V+?+WfT`nX7h$
zA`fm_$22NSan~kxfOu#J=b_b8`+*nGytKQh-fpk<&_{6CTbnW-B0k!gA!zi~{*Qi&
zeOl%cpzYW8wxiKcJC8!U{@Ovh)&sOJQ=My|RzVS>AZ@)F(;TdIlwn8*v~iRG57GYV
zU_mBSdyAHnVcH24<qOw-Is`64>vkL@QahWfyAEo9`x%Odv@u2~9M(>WgNZ2ZC`JCG
zwd1H}>xlMkQjgJ&egW5FwTCDN8>c-!6Mga8h}-xH6SQkC10_*=g-XqiY8TbgEF@_!
zQ~BsI?N0g(LbCRw5GbZ-&oiKrs^!w2Cr$eX1-R0+3u(8Xsr@<=`dQlL6obyz-fRYU
zLMtJ+Piiw=;9-t-aRN|swTUkR^OW{0ijtq!Ubh46j5c%)6!NqIPhZCUm#>Yc%~Fwe
zJKbZ&+Oh{AXSH4<@TpAuV;fAAYrE4SQlY(1mwc60MipGu+Mhp$hc((l%Hh;%;}z(;
zsP&~npE|A643I|cV+k6Yw9FVNG;4EG0oI~b)I*_F8;QV&!|A#<cNN_L+RR_!X}dOy
zUL76U4`@}`sr_Fo#?+;qOpm*6tuIA?Z)me+AU)d8av^e4JBtoV+|p)KSn;-YQa<{6
zwO>)WP@h)b2=zPKFR19^t~QU-wD+`s-hui1+TUpI9S^i~sGjSgwyYej{n~O0X$@%e
z$|3ql`?wX2gIbLYFpsrYi=Z*2T}Kz<uy$u2L`JklT=+Yx{Wt@SW7?@1P;k~6wgYpw
zE;S#0F1ptP;FG)VrVc)N=-yudJx|>tx~aSzy5;9V_v&7o0c>yGrExItquWnAK40Cq
zHE7(gJNYGupKjz18vS)M3-S8~=rZE~6R7Lk1oa@@u9N5s*2RRt(gB^h1R^22n0L?@
zsuQgO3D<>CZCZqmnE($Xb-r}Y@Sx67Q3R(B>1wZGhN5&QCPP13r=ac45#0gWV#ex<
z;xM#0-Dj;J@wzyAxh3lQTmf@bcghtrlcf8Og2%^nclH7$S-0aRxHR4HLa3+fhA9f0
zp?i@YlgD)jC^4I<>y$twOIN*`?v-qvna;tT(0O%2^rUX`J#eRV9gP^_X<bnpM9=7M
zOon8h?$iI`H@as>(O9614SA*?Kie^GJ)9}g-EM>VQeE|5=qu9+>CIlQ+w>*+Ds(wi
z-chNWzZQcyr!$hjRXW#282owN++o<ep!*^Tq*nJ26)j!VomWD=PG_MKmwH_q#q%!d
z#<I|OS=X<G`W4;YPvBC6?yQ5BgI9Ik<i$1J+LP#P()H7Enr2-xU8F6#Ml(pOu5cn?
zuIqA-L8MI=*#fRz=Sl~BJ9PhRfcKrctuFAeOV`MTrEcBuEi~THeUJr_9^Hp=(7UPI
z{~pLKU77`rw{;;Q4*d4Lx>ZzG(x>w}h|W8@0DREH>8`Ha8$R9BWzoTdhq|GQApN=!
z0Tc#w|LlYL$GYcffBr=GTpb4SRF^Xc<e6^PKbV9e-RpD(4eQ?ELvKtc+5u>1{h6;I
zvRnVta~R+r{m1L6LdR9VE(){frq8DMr@Ow8t{@NnBKmrfr+z*qguV1lZGhRUH(CMX
zt^bZ*3qJY`S_k^-{pkFhpMD92A^r7XR3{#ww{8Fl)JHvp7eV?Viq!?{zt#cefPN?C
zDMR#{9;(m@)thLA9HwW}V<TK&@G&$Z^e^v*Or+jikGVLgf9wf^hxFh54gJIV^#d4o
zl-~LR6r%OtQN_y<{bouk#OP;z4U(Y0Pvt0y`sLT5cT^vMbg5I4ej7!}j_IXEP*2vo
z)B@U(qCZ`T)>J+7V<@KS-41}H>-QgpOoo1DJ`|7ZTdxBxQ}5vhgIW6KOCZ_$pPmOf
zq1RIG^`w3W?Q?VVxMc9?){oMO##8#_9WZfPUpt0*I-`F`k=Z<bB&{Lx_0xi&SK!d!
zeFd~o-<$@6Mfx!YMqjM|hcb3&^`A^eV~PH-9Ezp-@x?GvrY{%6-*Wv;S|C*DJ3ocN
zO8xK8W1#2su5}<)dM_p<tM!g%NY>~Zb70}TzJ+#U7xd5Ng4F8s=@EKS@A#k*F4pNq
zls&1}JJTchl0KZCESL3PPlGd8^gd@X&<6dw)8MY^6;y(FO@DI<xJLa?<Y<%rPb$lA
z*8h(lDJ}YF3dFVQ-=LD%>w3*DSZLF)rFdSu{%0yk>d==^I;>M)?YNHC8+s|#SM=yl
zPebQTec88Yyrs9(w`*?eAHI#gUVUaEK>PHWR7rS8Urc$6yLw|C26|8b3WXu>>s@si
z(*u2m0U{6e6P`k$U$2~t#sU48l+t{xPoD<KC;Dxj=zFSvq1plWpXuk5`62yE+Jz45
zg9@NOqW7b!lu`Xp3n4nDfA$i5ayGm`Ij7x*-zkjZV)!K$B6|!4d%(FGI&z@rVGw<Y
zMo&XwI261LGikhg4e!xL#@pb{gNTnI{V#aoYZx3)-;&;E_??RX_8a!lXaD>Rzp&wx
zzkxLsmI4eMx^x2#hh_jK$gry(BEbd?#rh5y7EvHD#Ne-hWT@eM4f?_iGw3N0Za7J`
zA`yln`UXa%K}V~>g9g(~%-SJC^;CdG8$`+D#)a&);xBi~Cjcncu)G}IaR%)TOjW$0
zXCDThVECGr*olTMbn6{8+?)=PB*P~efIVjD<DfCw5KhmJ6vJsYBvTDl6beW;gxkPn
z7;c4wJ8oERfsdJnxpF{f88}q%nr*m7A-ofYNJl;BNy9`7KywUNhhQStP*eb)P8mvm
z1D9v`yBCAYH~3efvA{6H6<o1l6Bp#H!9)S862l{^NG>&$cfdrMp_|t9<%abc=&La3
zgFz|{0~EJ9XE;&{Lsf=rl&z{Z?0uCU!Zny;pq)2F(e-`7u$v+SwFW~hG%gyxqH|((
z2K#R?UvJQU2kc7*>m>ADHdM|+-xb4yD4;bM^c_ICYWRCP`mPy#=3s&v4e|3~p~=8o
zjj=QvtZx9i#W0g{ZmoubA1IP>-LTXSyKROrs?TaStfMq$hv7w9BX=6&=>6Sgn6w+D
z+i-jb%=Z|&D0Ohtkl_mKTZS3)p?BL*P4CfO!(ll@`V67HXuM<iy#kGQ4cyn^%ss<N
zI~wmBbQJS{V7Txm?W7(Wa;QG5->{R)CI$?VL>?KEwD4lkFl!SA^VkrS4A3WrA0LBz
zYKWoD<ugN6Jz$0mQTG8lY{*ccam1hsz&wo_*3%U^X1KK(jyfCf`=D{RQRNOv7h@{@
zB72NxsyT7E8p~*H?`Cv*fH`qDZmmV9hcWec5KrU8;{f$CeisRDuW`<65b-ujY0c<k
zTuLiXU*q|GAp4A>9Ej{U3h8?CGX_yI#^0E934H;^_b8|vXdFjbwjg733^0R@W8N6&
z0f#Yt2U<gn@1{W`)L2~y>@ee3K^T3wG5-{}2%{+io<<r2=|y<Z$f26CL&mvlpm*5#
zof{;hj9<J1^=RW`2Y#j_#<cywjxp*sLnPMtkrgD)IR6Pqys@qWk_pBxdTb^d9Z5d{
z^r-O%`V>}@(Tje=W5x~i#!oiZ<1OiwV$`k#XsU6!79`Dhe*iG)#ur@Cmtk~-;1@Y=
zoJFbCOyk@qz|Jz(w_&^|jV&7?nPc2Yg=D$LHz}}i%4ntd(P`tNZYZ2Fe)3-kGS65}
ze>{?J{A&qX3yiU}c_}phcmNtj#vgXVnPOw`SK!VX)h!SyF^Xu(T56nq1d?UOT@g?(
zH?E^tO@&e93a-)^Px*jz#t%CnS!K*z1fQynr-MLhjJ|o8!}G=kf6{ziFwUTSe62B!
zb{`jw`M-nI8RID*UvG?YLEj}~5WPb#8{gHU@rv;rm2fo}8_Hqus<G%O`mPyU>Ar0=
z4n<-Pn~c2!XlyoqLxtZh#(yX}(rWB&0J(0|i{N3Kad{PeP`urkvJswk7{8|zDxJnd
zzX7z%__-Zix3QQuWH*cz^MTf5oa2tZn?}cfZz<zJs$jWoyq5}*UgIA-fYN6iIu7oR
z@fSZ>x@#=>8Iym{xc(gcy>DDatAPi`7w95;XnZ!AjtTS|_t6S=!1((upgl5*=&Zz`
zac3uB9vhRH(0F3JF&!dLjms(N^~@;ifHOnJC0$S$Hil7fcEmXFF-(janI4cFGj?5o
zGtQ>nN8rV7({~#H=3=t$K;ItIR$2|Xnxbg|>+moYQ5~D7Y1cv!FVh|s9Nud><_0gk
zO*d#I=wrG*9gX`<ukVMxpXoe3E&WZ4)}k-S^!Ly3DcIEf0YDF!0xzI3#8gb@H$qL{
zoIqoksgsuP;ifLCsERNNK7=!ora7;J9CVl#KZNKZ)57hLIc#FeFqk8zEtJ)dF}1ls
zCf4*SRdB|cUX215Z#qWB3<)OP28bk?8fdM1%v7-eD9NUGzCmA_DVJs@-L$X^T!!g2
z6QHw9J9?m=ZAzXGuoI?fi4Zwy`e_v{wR22HM0K5VP1El|=9H<6!u+RAtEu?vjLH5s
z`tnT6=pbLdDU{Bu6qqcZqp{fZAw{arnm!Dv*?}F+9E$W-nR02TTy46u8zyQ@OIjg$
z-n55~YhEz*(6+ADq@f4QMU$B7&g)Fi&Vs8qJ<?%<E}4{UG+s7I^|04qVy(x|bk($q
z7JJuBW-h=QO@)+WZ!$flC{VNMOh5EmOzRzs!M2*>*FodDX_)eWZKlHK(b#E9{2u1J
zOvlb)*1ApJQSk7FX%$^-J*E<>G`MN<5JKd(={?FS^qM}TtGds0Vg-hD$MiZaChnR_
zslMr+X&$W)?weE|82kg%KNR?UXj;C|0nvU_(j|B^VEQHs+#^%G2{MBw83leGo3_6R
z?ukj61+-_TO4<bvnV#!{zr&_TdN7WdmieM_)YLKsu8o;aZh(TbdBHsRwA;Lv0wFHu
zIsZU?kNK5g5LdG^mFBsbH%z3oxVyQZ-n$;=1ll2ZngbFsCU5f+dQkY7zoaTHUvtWT
zaVK*qEgk*MyTV{Mz&ww3*n#E<Dx3*2ODP)}Y<^P@F4Vko3@BmdSLoRnZVskMM1*<p
zK3t15Hzq*+pn3dUItG8pyn81!4x95S#}Q>-p9s6r<}%c*I2|#^oPtj=X6x4=v1Y|6
zNSryJc8BriJ5E4LFwY7_W1@NKK@9Y$dGivCFxhOQM0SdKZW7F=nv={RY36stz)UxP
zND;&gGp7f{k!60H!bsWX%Vz*{!t6~419HuaW8v^A^Yk7#bK2}a4F=Dc|DfWwJaYvT
z{^pyn(#xg5eD4#e7n=X3EJ~4iV=}xbHm?ju-&ynPe&9;X?G#8XHNWA2dYQS2o~z~N
z+c#jZ!eRbyDoj+Gql2M;&U}}JF;$th6ho*sucos*HRg6X(9W9={s^=SX8i)7)tZAl
zA$ig4O`D!N^8nRT*PAEN#`TK%OImO@m>=|FELY8A6w|$CHd@ixXio5iWRrQ~J`Awg
z?5O(;8ZG9<6hCS;e_#aKb@OJL?l!Y?6&l;k_4F|4FvnbhVyAhSs-?Qj0y;d?ZSJSX
z#trk<6_D&P@2LfM)BJA*xLf95t1*b%=7*Cp>|V2|7sKu|BVL4?!z}a%ch@}0kp<Cv
z=I)8`=Dzt)$^|_%yEvh<-&{|{CIjY4KLX~FIgQGl2F-=E9er%hy@N45G0*x63Qx@k
z=^h(0dmBN9&Ex-p`iNOK0Scq$k12gJW|mMU%-LdJhQ{5N$hpwlV_Cn0(gLoQ_%rBq
zv;4USUbtJDX=*$y{glPoYbg%^=WUs2hNO>W1ugD;EpNsGbf3kIgGtzLnL7Z3ewON+
z=<~M}|Af8(%cn1+G0?J}{v0;Q(lrkjf-MQhfO)|3B7N5}#4<gUb~K@u7payo%u+*V
z-@+}P7ttAEIrjxLA}wnw;psuktgrBk9J1)LK@MA7gWyw?Wx6wbinc800`!Pw_I#+v
zSYjxw5^K5iBT(WjuT;Uqc+2-$KuNHOj)Npxo;-udQOm2JP*^g_a_b~qOtIuI09vZ$
z(7(V=vs@p8OuFStIJgYU{x=|U+%kg}j@gzfx^z!iuF^8)q~(Py^yOG)SYSTaayA#v
zoU)|sh56GK8LiRISOhE4m}gmi31In_X=I_mvP^(RN1>%I0WKC>KA<X~vlcalaZ4<W
zY<OB~nM6epWtI<}AzE%3M>Vw-mcEZ+zS8nDZNsW8@svEOw)}h&k~J35Tr{4yOyxuU
zf+hbt6lyI|G?t5&Lub%fXL;ith}2s=DJpZxVF~^d>}5;9K8)gu<?>C8qQO!@X@RSj
z=SrY>&GPel{1lCrcj-h-ljSfKO*LDh&cJSqCHDg;v|1W_L9Sa~rb4|oizkJD+b!M8
zVZOuiq8yewEx}ardBd`l9^^fi1$2h`rsb!1=s5gsi-PJ(dM!Ov^4Vw6t6=_)<u2_H
z?pk{2SG#8sY=FW0mc3N%|G=^{37`)x>%N6Zzhx|Bo(m4JKcmAhPb{W~5P52;rNe>G
zEX@-DJ!H8}YnNfm^yLs4wG>~3`k3VsmF78HN0MQ0w{<oHzPMPc=z;2Lo!km_H|x8H
zA>wX*LOWy+>-%rQK~HNSZDqZzKJ>YOy;j>l;JmE`4vG=^SZCAK>1%zv4|exiKc+)B
z`>j5-H}kV5P)^g|+CiJL0IS<dhy+^iPz*ZA8cb)wf~`&ztvg_yM9YhC>p%lYg!N@#
zkVtFFez<+my3Z9Nhpbb6g!*A?1!c^mtpBc}mua-MJqVpgtU3`4##oDsFs3+b0fm_2
zt*f>`G{IU{051})UEf3UsMU{ly-C&s@#s5d4X?%sldX~S0G48vIzc_vx|z;9rdv})
z(95vSdKDtat%)-+&6(C|pFuLqYF$P<(`@V82O)F9`h?EMoV2>9g3GZMIRhrw`jDb#
zr>slta4pZ;Ngtlbw<gg=R$vXJy3<1If~OEEvT}l<S8QEFTf?(fnFZ=4)`|24FSY)@
z4hm&f@o%tOZuK@|WEIxgODQ~9X<Z}(_Bm@2eYL8}y6#Vmu-aNqi=`TC%r$W5t^CL6
zyI`F_OM+Ufj&{ozt#!14sk2&Zpk8lXNC&1aS>O5v*q5y*>BV)$`XiljXs|w{6~R^O
zWm<<_v)-Zfa-%i;LpbVavff+_&}M5ZeVeewDxhn%&H5`HQfRlnO=Tq=*7daa?zC37
zW7fN@b046u+Zw(J<Go>>_YdZ|$J)9Ik~gicDNw&<UHvvBZ(B{YzV5Z|q{U93b>-I}
zcdW|)7FpJ7O)z`UVP$j!=DyWs3djTNo?)Opv`(jVPrr48C(s70<zY~KWR*7qbkMr$
zMTk7MCeUD>SVgoMd}@uN?CCS>E{dcNS^uHj{;>745{Qggw^LSN)cVF@G>%y(Q-OoC
zt(@NByKN4y8PIUCF+T>(9^2xLXmz!@d<+>k+XC8Zx!d+r{M5_lPU*P4w(saY<ZVk}
zpwY)RK=nz!wqJ`Oxz8qk1b_G23LauCem47YaQ?RK^o9(u{p|}b(8i?yhX}HTRiQE1
z*5Y^(13h5Nq!(_8?FJS4gxa=JxnP)W;#QDw+thbqDZ-`@VAdmTHB<?8(56{~#zVGQ
z6uCTXTS4XHQMOaGGmW<Gr7+VG+r3lZVr<hrAQ@}>u?TY!XS+5YT)b^Qd68fXUrph`
zMBBUcls;<X(_#J;Td4|Ms;&56z@*uNXwQ*un?M2m3|rji80c|ZpaN)_wkBH1WZ90>
z*Eh0lBlX};+C0oKkz+g32)$ez{!SV9kL}oEG@iEI>j3l_Tl<$7Zk{c19@UuT+l*we
zz~)Q2#X{TLDrgkh_I?ZfVw+|sd^&5JMPc$1n{X}q%55{N(O6+qY=ASBwq-xUZne#o
zZj~C_5n7s_x0TV=ebH7{2upP~_Ya^@Z}a*WC|7L1QXH?r_GlhOhOXLPH~@`nw#^qn
z8f{C@1GLFD^%i8V+x+MtL7UC}Z=ki?re%V3*zPYtU#IPPA-FEvPqf<awoP3Ky&JYT
zDo*LK9o+_U)25vSpKjTjQUQJ2#z9iisn_<&DNJmiZOLtjIPTaOHK2EGDjO`_vxU>D
z;l6EzPIf)8P5%~tKeRoj6;!`%DxFmyu*Lrbv`4lQcjyh;{3x>X*w#e*<0rO3S|~rY
zl@5VCv+X#9pLxh;r?P`#+k&aEFk*X!GKHhI^FIJ(%whZSd$7*-sqV15+def8oQr+q
z6p%gk@l<@|YOgv3eGmH^fiUQ4_xS^gUiR@qjAE}ngK`_*_V$n9p^yEYCzxPg`*B+D
z?z4AM_+`I+?E`@M*~2K7>~Aml1$qJYm6XB_v^zds1{!4li2^;r_OEE2alroCX6T35
zS5h@xsQsNhcoAlgq8(<qT@wK=!hX~Mkx0AZI~Y7@_oWX{9I`7Y0e9G*vI};j>_RGd
zi?(+Z0_BMPe>t!aV}C}e@>u&?Dj1Ek_c>@M5pO?2XF?L}D`rAJ$^I^7w~yJ+OaV-?
zy?YdWDfU;kflIYp`Y;!1_BGjn$*}*Wh56(5x90*S(_VcJW6836M?oap{zEbB=Gdbr
zfaKaQu7xwF?A)tRIBkD*3b-?N&1Q-W<=LmuTR7h?84s?&?sFg5h4y^9{Y&gGgn}!z
zZz}^=X8)xGXyx{oXf0l07u7(a(*Bkk(9YS9$3mpa&YcZss_pH^Fo+ua`&6fJ!7g71
zQfrT;c+Exow#{&~&i;NP-GBA=l?yS#%Xaa2v|h32(9x_0`(+c*uG&p>C0w&d?*Z3n
zUvvwT-((ldAlYJH{1ZT1?Kk^i>AKy08n`xl1@0=RcKhrvVX4C&MXA_Md*B85)NS7#
z217UOpN<3RvA4F4!~J*DzJ{)yTXq~|!%bq(r+T4Yd(<fyd}?3#9MDGWA16X&%)TrZ
z=3TZJW&+!7%L{j*;JGD?0R`_ZMSp<o+v2ndl2KdMUB#3f+mcCnkMu1m6no0rvLX*6
zIa@ZYfKR8loTaU$BY#Wj34j)DnM5yy(k*SYX{g#_+XI-UEoWHhyR~J_Svb?b<%_q_
zH?-y8S@^VPtC%hwkF67qqHq7!Ev2v&wzZtXdC^<bM$ve5t7jCrjIBqXgZa~2^QpwU
zWa|qQrLNez^D|heb!=TnWnq`M&Q?HX|F)s2FcGoMClE6fv+b>AfXUdlU5&;Q+djRH
zVdrm4Wx%J3ZBHxESG#QuZ6O-B-Pi(=u5GKSlH=w!`AoR>VA~E2Og!0kg;qPm+x~h9
z&bVwJqUhS*?eDmu(RaJUjUJ@|+YMB79K79c6dDoR#jeng-TpT1yb`x}JP%9B+vj#c
zGHrVf-Kod7Pum59+1u;sd2?cWWH%H}ZvSWs`f|1>Q9K}T`|dPw`P*%s@TqWnCY5It
zZEtfyU-9;rT0qWj|J5PJKufkC-UZ)Ew|CGXg|h84uG0){pYt<@R=NG-TTrapp1cDZ
z)!V~=Kx57J$@>4(^d)dnR^R)+_njG-VPIh9eP;zSEthgh(^AXaD|0DR%Uml>%hYn$
zG>298%?$+<7f=KRRQ4Sd5M)tQKt&J)5qD5jMBx9NzQ6zHqa5zJ=RD`!JMX;jz2}_!
z0-wsZCQ+SI`PLr#!e80?&NPTrY^_3&LV9)UEDD@l+v>Uq9#(EWN(bnww#J==WcAj{
z7ZACzb$yK)!*1C6ei=ZUw%$egYA-4No#$|Z0~p+lgK+OUx8)EVs^Y5V0{;dVyA6o9
zxK*@`xXt+s5UJz-R-;wVEwcrF6L(Yu^9gtLEXMPSyGPFiC${1Vh!-2P0VuoJxucY$
zHsin6X*j&;+ba&gzqfu3OugS34{!T9(=xOFO4`ehuA|-An3W%*_p^}UK>vKg3j7>9
zcsqK(_>yXN#+jyKrpEh@2ik-kFM%*Iwi%pBnil9z-bD4;Q=ZQS|H~pZbiW!tk2bSk
zcUMDb>Pc&Ke^W&Fr)e{D@cZ-&ewdsYYwm+HvnvO`e>-**_}~5X4n{TWIc)^K-#{}r
zyH7G?=Def;%-lKe!l57L&IRU=fmA^_?;PD9e%jOtg!!8$<M#z84nuz7=lAIQzvv1F
z(Zz?T2ye+w4|w`>WfIK%dXet_OWlrQwwAq1?;H8;h#z{FPoP6?D_rT8`@4$LR@<+}
z;HNwH5!IFM<k}jb;lZt<OVX3;PxYu?Tz3-edUJn;1KEeuyblOpuAr4_{QS73k&p@E
zI`%^G4mT<Vo;>B;z5(+YH<|9AZ#WOCZ0_XN(K^kY9UKI*lP!5bmY9?(X*^lOA28v?
z_R^K<&8l7i#fROKktH^n3Q7G~O$jDHjLnz`FAlOO1ZO8nPq007BZ^{$17YbTlhZ>W
zn$4dEv=}Cwfr(RWDMcnuvw6pX9m`&xgTXjv?+uZ7HZyo(AlJt{iQ-7fEPO3cQdo}&
zg+%@~MN*RZAyo8|%s-}cV<~*qGuTVzQ(M4H<40_QWIF#2Wn43ON6N`$@(r_rlEv4>
z!uxD~=6ayy@R3xhl*`xmf?gi~4%LpG=a<cd!Ug_;nRd1L{A&;RTfpBM0GUF5QzWo2
z@@apeRm86x476f?D6J+g@gGgXl$7wHT7Z`FTqO*a@yo}-QaOK*(p;B$<9ATM!uOv6
zg$h2ZHx#b&LA1xc#*4u)be#{n2(y*^-ft<>TE!1t2vW_@BhefDACzIe$=gwI_ZDyG
z4AB~XJ8igc^OYzOk=F7{=qpyoH&Sr-4!?@(p6dChbe%QujWqXn`FT>1M*hNepfvFj
zv_-zhH(y4png7ia_U`kmX3<8ng*VU_^8sJv1O12m;GY5dh(Ea)ppW^Blc4y7e@Pk3
zr~IV#AkX+D+R(M~6W+rlwDILsp7xxNTn*+6{)#6YZRZy}h2BeE*&BVY_&b#9c+J0e
z0MH%$-!EYA4d0z6>7|x-^0^woI7$9oh`Dr@$bx-$AzD9Y7&H<jepD-$D4ARZjU>r0
zkHJiql%9l%6v?0T-7A-TcmR5rB~vP3>54>=56KG2GYV$aNaj+d#BIr#5=b^lj_m@u
zCwb2f3N4b3A0YBT@|HaGkS?G)DNm^jmF;>-`~SDW@x@<6!6f=g%c$7YU)payoC%QL
zq`+^uR5c44snTNF(xgde+yqINezFe=8Pe4kFr-YWO)e~D;V)pqM7GqLF3TM0s%+TJ
zmF8YS>%26zA3VGu4WV3jzO?xy3>8T4{dWYSP<s42IxkAI9>Q)B-n$OF#nO`A7=5km
zI1Rf_c6AcS9og?8Aoa3^1EJp_>)RXV@5(-<iEWfUy$yvX*++xvgOLq>4i8_-hV;PS
z9@)3FTXM1x5~1#F(RKx1xL723&<)ndBA>?OYw?dSxPBII--k2)7ME!e7HBb&qPam9
zi>c0Qm&KJFwDwr6ptI|HE&9>+VV^}iMSg-U)KsV#YH?*HNSMX@HDDgJknI3DW?@O8
ztpp1R?eY>W%KijNvKaV?4sj=2^qhnFREt(BrA)WjJQkf979&SuE;21lbZR`yLZDMd
z*%p`V(JHj4eGGEZVkBMpMHZjALZR5=r_aE=WU=fXP)aRM(MMQjad<Ljrpn@LHQcVY
zI6;fl8y3oo@ad*SGDSYkH5R#4+k4w$A}w-jEp&?jQ)f{c0PK2;ArxY6uy}JC%tnjq
zPXW_pkxciJW{XMDP`Gaqk`Ivw7H^Y59$74#3dzS7{<MsEV&ScU7cQ3nEQa^{Eq`x?
z-T})`%D@b<eBclBp=QhaLV$)@%IU^<(9%8xFo!H(Qf@Qc(veDg4_ofp1d(Hw`>z8#
z!m@`7Qz9+fiorZ?Ifvo}QI^Nnz?qYltNH>Z+A^jQtr$zoZy<TfviK{YBwF^NU2T%(
zpH$$VV!0q0&ZJtZ!m|LHX6Zob$aKq;;Gz5QrTkWhDap0`XDj;7TfU~G*#*m4w6w{$
zjQ$IX1(tg#r+U${hmyucmam@xwAeE0Q}mTs{ze6zrIsfsMq6e%>{ql}EGuYx_P}xk
z?G+zcZl`U-W6Mt{()+}6X%Wa%%kA`tYPB?(^P$*g`P)T^zObA}ccymB4=M7~ZRt)A
zmmbTt7ohJXZ(@*img_R%jEnpX1sz@G50!v%lV@y#Ywq%Jx|8mdf7^yW4|zVl1Km>|
zZ;t^6%6FiQT^b~}pzqyo`IDQ_+arH}E=3*o$>X;}F<5?vHlT5Gt1Yk;FK?!j@w4)7
z+EkyD2T~nTf;`j(twg!u7D$qO2|az2<-@0<l_K9+iJ3{2FU^Kznq2h+>gn=IT7G26
zZ={1{$~V$s%q;oXK4@jj-B)q=Qs&5?zJW%re61av$&=Tn(?=oK(+=>0{4B-2^5u!c
zfL$Qx!_ZeKKS4p(i}Dx>;uXo)FNS2Xd^lZtm*jh=ft1K6QR2Q#KJqF=%H@6?81`j(
za0DE^BCi|;^A+-c@yBS)(yQ`DS8%V%69kA}m-nxPex=;A9;8}cN)^I4<X*J7y(xEZ
zhuvFphkB42`OyIQdt2Uag85o`+HAO1C%2+2;f_4?EcEK-m9Ahm$Y0Zp-j&~@a{op-
z_YFvs{MH@VGvAXRyA4at@_Dp!yD#5PE14F#(@dBMQta!5Yr7O120$Z3QIQYOP=$9p
zh8Ct6OH1v8iWgL&7_M;n6ljMPBThp7sABXYkYkEKOXx)?s-$o<QlZ%l<_X32DL{!*
z{N)JflV-*EWuVcDfxiIsl;RyFI%5^4<v@#5l+nS~G{yRQxR$PXw?BN!RD4Gn@GQl|
z-vC;m_~sfw%N3noXkAvkOFQi=ik2J<sY3CQ0)1B%MJDK7Q!I-C*mcD>XE7y}ia`Ys
zsZyBr$6&WwQAZoX2F1#1kh_ZEv~p`ytQv<_lcJNdgZC7nbn9<cBvM@RzJk9Bw_6mw
zU4i{jvGQA(f23F;0Q<4x1l7?!QPk42@u}kL9E|0eVltgfYgL3UKwq0;*5^QZu6Sjp
zLvSw?JRQ_-R}_{&=9Qw~Ai%s<te|?74uubu0lrbp$^}fPqVGbGw~Dv)ZSGRsp}kwT
zB4{~UJ&NgczQ@U`QUTYTtriXhaj}xn62#T&&aY^>S>1RE5qGQjqnM|iRvD3I=zCa=
z4~P5SR(bTn`dC$b1g5W*J*`&!t!g%)6<}3l1J?qr=IjSE$jbW!V0KxFt-#)G_2X2u
z_E?3{`KyCgaTG2%WEDrD+Hfm%D9B-}ujsyd)au7OXdScqiaz@YtL_=JSgN;rL-Cwf
zRwF6=?4&GN3{hug=^+?&QI3fr_m$!G5OGt6qYyyquKeh0z<4P?rEQeAax)bn`zY_v
z2dJ-dxicjFm0OfR2~aABVW2_E%Sxc^QYP(#$Uf!uczkHV${Qmn>bGB+x&rPWP>OWh
z3ROl@S!$RviB{bQm2nh(JEWA-*Z;6Go)T0?lr<879#vlb0-(o~(Ud@pRQh}Z=5ghs
ztq?h(y!zjUS-EWxFwZJm>1KUS`Eef1Cn%FCFrTO_q{rCAB&DE-VzP1wmEoi)hd%*H
zQ%<LEdb+Zf(t24++b^J)qcqV*Bv<Lb5_YdBi>c_kLiu^HQy8*GY%TOEm8MT2Ql)%C
zH<~-j1GJW|S1KvD*`Q3=2+X_6-c)nlq_kd)k+mp2u7NyIUc3RxhsyRC*n6Zb4TQ*3
zrB?zxe5OnqguYhgq~4g(Hs#Si@cyMTXDP@l<!4ezzE*ac`v9gxx#c2Ud!rn68kRbh
z<CO5?t@7z3nD0`y(f+{C`XkCd`CFf+m}h|Xs5c;i)*fGg8Dzb$24t7@#Wd*cwjM-#
zq&?O?^flOPJxK%TebyfR02XX*l?}c9)}Pa5alrbM|K3m#VtqOuqM_F2=@1RGenLgL
zhpaC*K{VW2(F^3T^^f#~Jz_nE&Tt>K?#_ecG3&?-j4;AF{u;<}>kXxtgcH_1wAGKY
zp0*t$JZb&D7R(sy2Qx9wQ`Vztv2)t`D&5gyt#^*4H-yAld*^@~Z!MuR+%wjHQ2p##
z>n}z^@tk%3E7(o2)=)KWlJ%8iAf7gdvp~FTVrN6r+vWuw65M4|xe<0lY}m&%78^gR
z<qNa9<qJm-+Ema|E!>88hNFjV4pF-4h|Q1^dPBicn>$p5bj;?xaF~y<c}gXlr)@Tu
z!>2@>pVosU*~~ivjbxkQR*+1wdC(g$muw;^AX#El^En(XwL$eiZj&~<>0wxD!(W5j
zRW?=qK&owuXjyf`Mx}<xO&ci{)!ed??SqHr8k?SGfZnzV8weA%He3ZJzs}~5(eUDq
zP1`Dn*4vDt*=w+QLziBojWg{Vn`|~vR{ow%U@~BuZI)BK`o7J;eNbq#`Gvye&uvy$
zqwj@{fet*j+vLB2!b=;;G_+pXT&J><*Jhhy`r>uiEH{Gt#%2^1aCX`_3<dM8%^oTe
z>#}Lv0oS^1+&j>6QcdbYpR?-bG7uNla(aros$!@F(M{zw8Z+arsvZt6cB-6Kq2;0K
zUI|H0m5S<<y;S$;!Q-v+T?nR+%DiJLCfHYHMN3RSl{Zz+_^YzFLoq<LG6c*(RUS=g
zkSc%@yt`B{5LlA#R;@gaS=*~>o`b%9s+N@?!K!bm^lHCq8$JFGsLoSDEJQVrb}peR
z_7bfy)gT4z9aM$Y!TcfBY%^uH4y$ZS&^)3VK<8VJs;*EB<(R7bJo+M3QD34jQk6ao
zipNzwB_JnMk0W5>q-x_A7)-RvPk=~_Dts~~;gsqg<(W>a<i~*$t2*`HBUvT;0$#+c
zvciFRMrGU$k+Z6_)fBxtr+PF1+ys@O7Gp|MH9UrBvMPt-E-9*lEdWhb4WV3nn#!p^
z%%`h{{0jXH)dae|W~#<h-Ftzmv<+Z|sw1<Za8Wgd7T-mxg0sM^P^r8ja#iI@6=&B}
zzbyvyx~e0A>KZFm^C`hxr7FvW-D=eZx|7~eJxPGZP1Rb8quo;FP%%)AY7T85Z>w@?
z3s9?yppa0V>hQlnyQ4Zs<v;bR=1(AUS2h1nFdJ3tx5Div)nA?HyQiA#0)=MPQ7eet
zS1rZk#4K%5mH9#RfhvRU(hpVB=rVbv62?N~v8uxW<`Y$bBbZNB0nSi-rZV4vGtX7M
zD3td?b^apy+Ew=1P<W{tRs`}&CDJj2*D9qOpgUALst<glns@{X&bCvwfazkZrj)ta
z)%F%;+1+ecQ3=;hTSm(b58Ej>(DJlh-VX-7Y>l)|@V321DPbR58+w-e+TQL1rk`yg
zCGz}jz2advz;+!S=Loc2On-ze$hO}!Sc<ayMu9;@+g*|X^ORlR6zIj;Z7{-__#f?V
zZi0!kb`dGiNU+;ZySXI0@*%L4X7{BnL@Vu%B|*QzuJUvA-L-pk46R1H;`wMb**%;E
z^?P>l^w(UP?W`!R&}!GYGkEba?p<?VJIq3--89-YytVt%5;9$OcClb~+x<lqMm=_0
zPea2=?M~OMv)XR~KwZ>6RPf-cp7#|LeAU%KFzBbg^$Acy)laB2B23+X7lw979Y}ZS
zaCM)%5IL+KFb1t7>b~zo@|Zf_Jd#GLUQz~)IJF`Ic2m`!R6w1k-b9Cn($%qpA(F2S
zr@LN(+IKfy!RiV1(7&i|Sp~f!^*5h@6suQ7L+_G0<1F+_)Xg-{rRpimV7E-&_eYR&
z^;@dSysUQ2#gMM32YyZ;*DduVDiN<y|46}=+v<unuvDu~q8D$}soi|gx}#3L0x#;-
z*;IkjpdQnWQQTG6wnDE_ZP$TTle(u7t$XUdRL0$`juxPPAAivr%oep*Ck#DM2USA-
zp}P7@v>vH*hEi(iv3lJn(0`&%nT+e>srp+v6rZWb20^h^J$Ej~)TTDkQMl*oREjaa
zP}filzFocMTe_ar1Am8yuhd^&hRADmRSEh!)RV76@{M}ECt98AYbmhsR=vj>%r5ot
zZ7}boDL@q5EOpjIzr>ulXsl`d>Z<ws9f-PVn#&=xSM%;gVDHmx{|eaqHE*a=^?+u<
z0!)6Grp5+(2Q`g{z&xb6`aS#&*ZlGiyg#gQFGK5y<}y_{9Mu?((Wk9(q5wvOMoTpu
zk(w@wO`4BuvfhRM3C)VVup6bhN@4Vqn$^=G6RqiAgI0_t^DVqMr5R5tsneQ5ipIoh
z#(2O)oTh&QB;z%I^1wc$dD#mnXEhtBy#Ji0eKlGMnnO-NN!0u}5d%!pL|4M6WQ{ki
z4O7gToO2LO)!cj++%(Ohc(l?rQ6Hm~p;<wtNtv1t$3Z_!leQTe*%~>ez;iTmsz}V$
z?4@i<p5_vTwa;sQ$b$L>&8Zq#%Gb0}_@+R!fX-1BYEFLu^^2M~dh8cz{3xqftTBK0
z9Amnq`8Np763qx&NtJ4L+<-=zCV`67$~7sj5V@>Lrw7;-&3pwUD>TDDfyh<OTl&IY
z(?r~Y`RkgSWVcfD#tO_TO)m*Vsx?N+)!)#h{0(wb(?x~Iw=|ZYK(a<-Y3_~YZOzJ1
zh}LS}iv_9E%*?|G?`XEsE~Q>GMhnpf%?>&!a#xen1d&F~EE8O7(oCS&VcgTOaWL4d
z5olX<U-LCp)VF9V?!n*#&6Tql(nHPtdN3bpCY*qyk2QwrU_Q}oE~X&GQ%&GCO!qTQ
z7d@+5H6`>Jv}vwWD($)Ek$~0<jf@g5?V5@7s*IPK3G~6f(j2@5(ASzbbnK%;Q{oBo
zMl+jYE1jCopCS2HGvj-xcWKt7L$X^lBO1f)(OeIMx|6VM7;TcAg-29Q>LOgAsx4O`
zp4P^0LfQ<p+=cK$IJ{GE{ueC|p+8k-cnWq`0qP~3D}+zpLO)vk`v{G6bih}Ltb!#!
z!LAj0{=#3B(hU$&&FBjhzP}1XK|&(^owr>=&uZEv?G{Qc;P4)yl}_F56?)Ne$bG`_
z<Io5eR#2>Qzu-aV;SUHIJ271$!hA32hYFulvL{S9PUSQQh1;j0cSxAJ8zSLCUwU`#
zVWF%HV>u#l(?E_2`_{slV}e-=?;`};P>7f#g++8K^0?4G3yLQM<#v!L!7mJGCxvKQ
zQbY?Dv;m6|N}@nc319sJa#|=7;6<#^^FBc1gad6b5ih)<aQqpeHyyM(D<slw{hSaw
z1_MkGCj9p`6#k?qPLfb*2a#m6P(&xgQiNfImMR?H0P|^rfi}VELU0JoX9&M+LMv1F
z;4^4s2_f{tfNVjx6eLHOu@DNm!n|K0nI}y72=jDa*!?qxc0u^C19tO;(J#>|5F#mw
zS16QGG3!M^(1R2S=3ak;77HIx%IuQxDhzX3B3z&>VW}`L3ZP}eiGMM)a$)yLpj{Sr
zo<Qr0FoeGM6+-R|fL;{>--m10gr*lTe_fbCb(NLEv%k=)5;o)mtXlZa8RUk*vSH|^
zFlaFPZV6M(-GHePertiH+d}^YkXqpim3!0)mPH_UgcA~I)C<BCv>F6~3Z(7|OLsxP
zQDBsJXcGKrWq(gtPSMO}q0fF`-WP_Xp|3^o7zDisf&-<>9tuyY0rp6+ZAaf@A-#p_
ze4hx-H!$p{!W)X!KND`P!*$gvoSutOv<cTT0Qy|Gegl0k1T7uAZWn~xATNdVb@2C<
zz}Z6KwXllzOdZ0_5Rf;*<uCBrcM6X`gXCLb!3r?Dgl;43bqf{lAU(pWIC}knlX%Js
zFwWvr27@l*phTd#inlZ1x0{&2AnGno_Jzn!G3fyMJjCI&QuY-8ZUVNKc$qG1Z}GQY
zQ1=n-sQAiPoH7bS@)Mh>z{y|SrH1(cQ9%U@f#Q%IU<QfRN(vJ060_ci#%}TXImql0
zBPmv~S6q1!GW*2huK^k?`acKRFV3YmIvfz6P#iHt9FPaeP;oKstiwc&C;ASG7QaLC
zwD^V&`NWEzU%}BhQAO*bc(I*g=4V7RMQYB9We;%8n9qqtw53iE-%yx4QJhFi#w5|a
z5uPTC6Efghinxw;SE=IY2-r;%r%**mx_J9MKr_TmS<uTA2ed&UOFZ=gCbGpCJCGdl
zoHG=1#UTPP^TgZdAaY)8+=bQ!adZV*`DSt26`&P}V`<%7C`u_yeo_3MZuUiD3>E4Y
zi?MxR;*!|$8fYbA<abak75|+Fm@;ubeF4hFNju=^WpM{R&8~>Ki{M&?xG5B^t77d-
zC|naQSHjSB@gI7<L#4Rr9H6U2^Ix=8tQOtpLgR*L9}5#V#fl>ky(KzQ2%$z)Q+WKg
z==%XI)rx+-AXz7F91C(s{M!wrUi@u0Of-o9(B*MgJh=d_HH!6X0oEi=9s!Yi;^akW
zHH(*uF|zw&=`4V?h!f0oD}ErJEd}?XIH(<pkHiKQ3_cduwu3woGa}LVR18Q2c_y-V
zFs4?qdmTXA#7sKr{9L^03A-;uhcL9-#n)%hdMRFA4DVlw*;I}9TC5%l^Bv*~73{qc
z*KnAGPI1cwT7SM3PdY%ROWZ&U{BAM5KP>f#yf2(_(n=R$XwKTpNocufx6`W9Rol23
zmfW;~v?_GhHix6NQ#+8pupZjSw7l}v&TN1QFYQW7>UnG5e+x_>?ZY!5zS<nRfc>;H
zexP^z`)f1lArqkeitGkzQ;!2JNSoV+)-G)_eK5PVQ)%(BM;rPQ%)Q##6n@>OO-zPQ
z!P;3mwDxQJ($TjA+KEFjh!E{J(=hr_t+EHqFzpVy!5q~3#>1yW+Q};*60V&y2PcQ`
z#c_7#*}ib{n6}0VmLs%D0q`zT+nWmcj%$CRVC4yI?t1h^X)Tun_M~=*39!-HEO(F?
z?fxW4p3>GHgXC##fFHnOwF7D05T~7X15*^QT}tWCGuk_&;lNq#XH%hYPW#LrA_-c9
znZ5#v+FJv`P10VZ>nvI8mknl$c62cmQ?&{H5KYrEiovIA7t>-SL;G76%x7v7Xr{BY
z`%Xh4Tl<jqu{m1f$LPz|y3^&7rwy78=6UVdy=Yy~hN&Q#uYFGfW`TCo2s1znwYvf^
zw2Rtk!Y<NYI)a%l*8W1dj!W81I(}B7?L`lrQtkEUFj%JTM<Ic7ts`C0m$kn?N8c6g
zwC8A5Xy1MW^H;T{Q$en28-9X?>)H%jGgfL-C=6AlmC;_aTDyA%?eK4CXVVhprZ%V@
zPTkV-Lm^tDJ-rtCx3$}7W^1)y(P@@Ct-Kc$?`Zq>hfnp|p|r4T(7HZ`+jq4-REpiG
zwYmipP1-Kn`rXrh69AEB?d?Oba9^vUJ9CS6nk&cyZ5oQ*%+iP2{94F7(gxG^;juRU
zJj_4Q&ZT9*Q|;ErXg$-W_@mXTZTk|SZQ49qcRbe`Xyg1stDvK8?b=`WL*%7)?<u(b
zO51e}t=HN}T4Z);Go<kTjn;+^Fm`Ik(KhF;_RWV7F?VT?4S`IzwrUSZkG6g$WSn%z
zdLZMhn@B4a7hR+Xhh25Mo6+Z{n=lSO?a}4Y9(Av7T{`;q>2imnFId+>`OE#f%@fdf
zKzHsrNT_ad02IP>!ABu-P!~%9$wNBk0Q2Ey9bX2!hjq5A(LAD?sD=Jfoin|X;+W2M
zEBubo<r8S6u7RSf$8~wz0CPg890(Gnvk3w@sdG32g=pRT{U8~m8>_;{bV_%fLUN~d
zeFwvQtnTziFynQFKS1G(ZulP{XLV-(T7aI@eW!<|1l>VeDkSRWQ6M%+S4e+?Em?O_
z#9XB4CeyjvR9(Rb@Hb8O3B}OUby2ik$<Qe%=9#I>pwi+joy}16W$U`A+ABx*h+_V^
zy2n)BmZwW3=6RjJFDzWpb(m=vk*_;Ur{oKCDfTd5sM}HnOBZ!%n*dX!d%F&z#kx(8
zFqlia%+Vkvx<{J<TB?&xg!wXE7MU;Ct)Lj~W!<<SkSjWiLts|uj8sB;Rp)XIlGk*J
zhd{3D%ydq)Quj>_ErP0aY%)Zvb(<)5aznSBHsd#STbe;`>5fx+uSR$0Q}}dS*G)UB
zT3vSlK<ji|ANo4zN@D<8uQLyYPYt@RaUgef#*YBjsAD_eOp`8%_FngNBPe*@tP70?
z^S<uIHxvYD(VdG0+5=sz5|$q7x~D_&k#5j9kjJ`n*Mas#=T0}_r@Gln=s(k4)_}C?
ze#(G{ZMykEaP7J7`<a-$7rF>{Oi;USKNT~))NPvt$yd6WCV2Q-mu3mO9lEw)NWRhO
zHc}9vQ}>$zGH-QP-UV8hZrfUjcI#fWLcd4%Pbus=>3KR0?W|wfA1xRCN!nq!>YrMp
z<)(k1YHZ#0p%iu4ska*lXFT-L|AOhMzd=<OUV2-~#d_<b3DZYEf%03v`T{DIG5hJy
zZh}+(`ib-a574I^g-oE{wiGf!`b-Me?9%5hhRAOHsY~eFqYtJq|6YCXTA1Ibk0uX;
z^{Q(i`}O-jg~9>-KO><YqW_Iv8y%|evc~|!^!o>Z9MrEf0PK){JY9j|X8lvD|2eEb
zUk-1M=*Lp({iuFo0u+zw1M<*{(Em%Bo=AQEmuMZ=_xT&G6Z+R*p%tZH><FJu>bEWf
zGg|-d34q1u&r`tal>RI|hfeE9)4DKLU-}dxar))~fR5Mi`4u8(^yX3}+&HUGtOMFP
zeaU=uCg=y!T`y6e@Duct^h;zAN!I6W1T#f{rUI>0eZf|cG`+toW<6bRD285!emh;q
znfiI_U@%MH*AJ7Bt>1YH9_Hw6Xx4J|%?Ds8Pe1A~!1DDK=6Ey<^gF0%{Gxu$7cf|)
zUpWW973;^PLGhB_JqLc5=u<vKU#Z@UF3U3g4O;D$>w9g4$YuQ|Dh0iwulN^|75We9
zEZtT8NEh^7(|b}}<hp*;1o&I2&!f0Vm0m{m1J(M!+RWhI(0iQ2XMa;aJ^+KcrQh&5
zWNzyxO$W19f2|Xi>hz1=!r?pm)TwCI>vtysyFq`-4KR20I|?y~Mty(@UNq^43;^am
zeJEARHR~^QL*c%@^(rJ=^k36D_JMx(hfsg0zqFbv6&~p;&w%?_zh@p4pXfiN$KX@_
zWC>)R>0i@EzfIprN#N&tt8AdX(D!ZyY1fORp!ZVWLzT_1^sc4w_qF~L`d~WrdudDZ
zMt_C|*r{J14D)aG9Bqob^p)N4w_C4AcF-*C(QkbVQ71#rQ*fOPwX}M0F{m3rTn&FN
zfER9t=|#YHH^fri-cCcn7#Q?049b9rr(rGaQN0Y0hXcjiVD<&m$8ez;bKz@vycY_7
zhKX`0_#0x&(HCH-sKPV{8V09A&m3g1e+2F>!=JRy*lqaXL%6ud;6+Q<y@qF$yW3|N
z-3#V}4H*<g+i%FvLF<6w8Kv+-46fgRgc{PHLOslIl`gh}h7%KD;*i1N510=(Y@l7h
zVZ$DZIvg<^n1a?(!+{Ynf9wZC&sS(h7#>jhU!>t@8q;wDDwFUXGyKD0f};%j5ZFCw
z;66bs+7L$PIbsZ2+HjvTu<aPyX~SI}B-X%5(HCd<DR^`mXIh#385~V8?EC~^iH7{K
zXeAlqsVFDe;Bgcr#c-C+z@{30{}*P{49UANmUP4RM4)6Cemo2dnTBx`@yRmWx5HSn
z4F|S>nPVvTfxTSA?*)L)GZY5n9UpznZ%<*iE*k1~Vkkw1o=89!8^-v;&?Uo~G*~Dx
z#7sl0)Zn)jB4vgpu>dPKbRCA?Wy1>-6s{O%g~48h!D$<yuNwB!o%fpIE(hnY8$S32
z>XilyXGm5VzMq1=YQsz_LcU@6(o7}EHx2ca<G5weeuh?!p@{N%w+-o(G_EzoQmC}f
z5M+Yl9m8MrDb*W384Sq=gZ~3C?-~LqZ_;R}>jU#m2K)Cg&Q?QEDtu})I8%`RxgnC0
zI4=xw%R$-=<LE~C($Iert+iem@`u3EYeQTv^g9gOD$#mlkT;^Q)1W#AOK%OIQyEQ{
zA(OUM-G;EkfH`g4ZVAa)qkjrS;*9|VFo?6ptrGN|GalXzFA|J>Q^8C${_G8AlJP!m
z+)|8pX;qbGoDod{g>>WbHIT_P#!wa~%eaWrklDsz7WAPRx6>0N*XXbkXnDr5RC03O
zc%9Nd7mUqxapoIGP;j)+SV(J!i^iW$!<i!EPD_YfGIo3dg%ac4a!8gMC%yw_nei@_
zGL#!r5dt?$FB{iV%;SpjLNYoljAaxmy=si5W$QKLgh+^9H?BXAR;5v<gWpxgNtE!Y
zHcp`;^c%+cwB@>KymbL4ZW*;Svo*%%KQV~g#@lNkS!)cWMR%RCeKwePjDM=(Q<JgG
z8;+Xq8^_)Rc8k%=7NQS~T`4gC&^Ux*_K%F0>3j3oI70+^VjSrQji<)h^B~!340Z%s
zn{hM+XPz5lM}fRBI=uw5-T2vAh`coZ{u=(iGFD2#d~N*Pg+5+m!vi?;#+Y#$UUZs`
zZa!$fHBKsoi7sOpRWWoMWfYL;F>V?Q7$?*H#~{w8Dg*jlOkcaflB-EO188oh5_%@O
zn<}3{WT$D-p8)kRJ)DR>Pg7wqB)v@6=x~R(Dep2Y_?QL;g6V6rqzss!$s9&2Cx6pL
zTHXYh7FR+s&{Vk=pu0>nE`qt+H11ny>@oG`K=zvMErf}Erf+ZKVhJ`K@q);H(?9f#
zIAF@X0!tyLUW<VlYPz@(U}2^{^PzXpq@vK>A=88rV1}D`M@Swv9XHbh`iRM%u9l;w
ziPgZ4Fr^>Cd_|i2eUI@TH$9}(*$GqicbJkWQzyj}qfN6Y#ed3_LU)hTCM_ju;!Lui
zLE=p-{({IE(=Q3Id)D-XzAEQTX|$J4Fa=(Qg(TC7R!AnBa(|^=T#9L~H9AvGeLUbr
znrRt@!qZK~ei&1R>5Jij$uzB|O2#bHPWo<Vn-VL)%rTucfSGIBMhWFS)6}T|J8v4a
z8;)KuRRx2YZ`vke5Cx`4x-JS$c~sSM(R6<)P>M`8wzQYLWZKpVnG(|nzR)N&IWqWG
zX7Zv~Ww~h>MV~L5Mo>N171OS(V7@V(p)*Gw_CHau-OGL)#Tvcse>bBq*xsM&D?;qA
zQe6F@eINy&58IpiLH(G0)fh-d*}qS-cG7<26?$<-wEceCtHjv5&~xCFz5NczoVE}9
z5?;jG_o9broP9AxRpRYeX94DneWnYh>#TkLC`g{OZ=>l>u#cbuutfXwgJ3?{e!>sX
zOR+yjH`F})*|d*2Z@-_4J<9Fh*#WT2_UShvX})4_zXWzG>}|$F=BmAcj>cTGA2t<3
zyKe7Dk=jc8&np2_WnX>*`qlQ%3!!+!J}3vy+_e9TU~bv(rZ>3M*!%Q{-fjD)2I$q=
zryK#Z&OW6#^zPVuOoC7K_U>oV*I*w+i{D1G{dH?#H`!aI1I^Xpn|t88IWT&nyE|mB
zg5pkx=Jfy#b7-epuY(S&PoQ<k!HE{;;SNU11|D{JI|8jE4t4KA{g}f<+Vn;^45zc8
z#~s$@042_$+yD#l4*gm&+%pa<ZP0ht!F>H6d`{;a8hLn;;1F^itwe_r$q-F)xJDtZ
zY=;Z96UcF>az<aS18)Mk<nVbmL`oc_KY)}vv{C-B%%K<Mx-UE2zD6_Zu#NVKR~=?(
z;Y_W=1^V9CIozYI_Z^2%C;?FK;1@hA4<%bxRD|%-;UT>~^_4@vDh%SaL!UqJfpj>8
z(EYg6A&)NZw+<gWp|8uKM}bzigXzBlbH@a_gE~9@OGTM3j)T5}SyxAy7d&%wEDZ<K
z-SHJgz;`+pEr5fbj_RM#=jAxG8pPW%#=I5Y`#6654jlD$R8&L5&#`4XEcrXek3lQI
zu`kuj1v$Rl2mM`+R};~<+ws5(*xlo(pw<0eN9=WRV{(*y2+3eacLxk`zhm_h^o2NH
zrI2o@<Fjc{IOurf2>K2=wu}VIamU!dD4=x0F_hNVCmk*63W#=mhi*`(97l;5Xsn~0
z_O)@25mZSZ@0diZg)@$SE{DOhj-^%rJ?HofeeDw*^;Aoj=;-zZ`jQ-%r-CFqHZ2BN
zievrnn1ocvWp-euJN8Y5*$a-Z)b#e8e8*18a27aTvxobIjvjQgzUU~)2eZiWAG#2V
z9U~=RmN+h*513NNrcm^iIX=!pU!~)ui*U5caq2!`*EvQ}mBk%LXR3Ivcf9ol+-`8p
zufbg0b=*e*-bTlQI;b}}=A)k1EWPJgvKlbWj-Sw1?7ky!2mKbuJM=Al;JA^h4jwwj
zR6+ldBew-!1ithAQwCG`*FSn4tPIGfFYX7^_P{q+?iqa@+_=yv5O+>rNgqCErb1T_
z?#_0!Jh?slq3gx{foF^vr=Xhtf(;*T#|%j?StwUS3-d&7GSzh@abM96KADT34Bt|?
z-gMQZa_fW9O5=Q}pemh<`UfHzoR;eHGr5c&fMs#F>4kdPoRaS6Io!ldDCBZ;K7dFb
zH^d9A^PGWlboiqV74*En#64cttCy^q`-FC;Zj7&mzB}9T9t`ee-Os`FV4d_X5l?o3
z%3i%#3>C$BvoZ8M@L@Gu!1QH>6QJP77RN%;pUHm$bO6&^VMu{&BbEIGv6Tnl#V$4s
z@gZ5bnSG4Jh3p!u#@<=BlkcMW_TlFuP9zKB>m~tvA8*|U4u|sNas2teX&>Fc2)}$L
zQvK1`Twln1;ZLjQ@vqJTdhT~0!uW#R2DrE4Y#t;x>6buqYY4^OJ-OC=49$nL8H^U*
z%P`;yW-*V;c=!K4Q(?S4`n&n%@55*hf58F{IY~aID=ttnPYLKC$(MBa_=rV5ooYF1
zQAG)cV-|C$GA+V_`w{AQRIZmH(yUrahhkB3Gzxv~sy~Y$`BwGb7_?k%e?T}WxTb*9
zo7emb{&Cy>RHbpk_NU%38D;x|(#j`odCKHQ+is^-Y>e&AWf<ov+r}ac^t5eXsx6DP
zT|(8xake$|+K&WV-7k<#x4lh8(RsGw6o3`k{!Q__%eLdbhx!fM0Uf}+X*)L>D7S3C
zFc(0y#`b|D%-^>CVLr$c+xryxerj7>h}JXPCW;2O+D3b#)n+Tw`H<(fGbuLl!q#pW
z?6%t$^@hSr+Ye}#U)dIHf=Gw$y9Z$YjjhY?5b3miOGRaGZNK;i=DTbiXz|-^`>csp
zB0aXtdIQ_ZE+z%U+3qIg-(BotcB18BxA|khc-ocFynERhU7+Y~x9|mEeC+o0;8O^)
zQ?!7&%T7;sz1?=JsVHTSUD`?5-D@|s7GM!}&!cH#?Y7dxJKF9-ITX&=b^Z5d^8~w)
zl^9{V-N1(st+9*x7@fE6ekRa5JF9~rckFim3Ub%(*<ToTqg{y+mOAW4J-~J1q@JLG
zL0|PETD$wH2ULL^P&-lb;jntn7`S~xJ&Ff2R=utT>WS*6H87N+Zks`W+2g!g?*jc|
z^>!mVuc*B#>07Nf`=C{)o<p(0d+NJ!5P7VAXFlw{P@nRKGo5PnF`6gM8Tv+eY2qkp
z<gHmjfes%{JcU$zHMSIV_0x3H*1=yhkRDY5nm-m{(gQVPFQa7+(&R=$W|t=U4rXY#
z#(x<6-lNIBiO#*6<^7<zPqSwV(1JD7FF|p?=3Eh&5t>4(F^SY{&xOKqjf!sMCp6x4
zs3A&or3cKDn!q}sL~CACHCc>CCxCfMGyFKnY0WEIm&BSiwiHv0)5M2jXz`j9iUFO`
zd`)}jvzo##kaL>e9Wa=v$q9mFl4i;+C?;z@&xJyY#^H1HrD{fcfTU?ss$ei(qovJu
zhNgf9nyJx`!^pBUH)y|@t@-s==;de<-h*VW#%!@0Ch{~}i@`mwk$wQh3!11vOvz=9
z$3cv#O0#bpuxmA6J3*sKW8WJdKGGCXvD0%+$U-nXHC0~%`>p1yYmn^HR1SxFx90au
z^z~>~(&pDmSVQlc@D<W6AmS&q9|5$#P-gxZG66#1DS!qF=jl9ekPu&i8QP8F1^Bc_
z5PX5QR~R}O`ul{wUqdliz-kU3h2VY%<cRPg74aMuu7#s@OepUHScK3x3Cu`gWhGFK
z3q2w5;)F1>1+6IIuWm?23vLG~=oBNwo`l^~!m#0(sMEqKD#VHvN~y9ZPRPFx(RktQ
zUm$0MT8bd22_XuMH(ltegL;-wPX|1*1v8Oi!TMXEToO_)!+fbA{TzB_LVqeSs1iC}
z!TV}qBsp_a7#l?|1-~U|qhYC07^nwYlVA~q);(btWrv!Dx<_#BzHn(5#?&JGOW}+M
zLS6yLLtzTt`5y^FHS`_}9e+aMiSUjLmYxcIM#GC|!t|qPwF)H-u-hj1{|l7oLL`Ni
z+l9C}RJZ+7aInQ^@JiT5_1CY3s#zc%!UugZ!Z*SPkKt*jFp6#%Zv_Pv5p)Tac|hwH
za*o49j}SzwUnlWjdbyypc<m5GT*L)b(e5f9qAS-;+?RzuKXJD`nEv87UC;{<2d6-C
zUZ6N(Ezov}PbnR~TP$yfZ+pbw-hrok#gEs)i=*P1ZO}L-j-~}wg!u7!v?9gON02-&
zhVKFB3GqiNKZ_EF9R%n}vE^Fu_)^ZO{pkt}$BKD(;YOUekv6gM;;+Gfmty(b(gck}
zF_|8jN#emnXeEmyH(|a~#9NdcPZej<Q!Y*Xk|K=hqOk;h8RA|_h-Qizhu~V4IG?IJ
zvc+5UY2}EsC&7HK*f|)?JTb%(3gu$ReptUOURi^_3h_l0^sb72=J&y^6tB{u{VK87
z8?+va6T&eUPek{AAe~|_C-l7)lW)O%mpEW1OmvG2zXh{L{N4!)PTFC1aMW2_G#}o(
zXxBHwuB)~mJwDyEUv7p$cWvWEfbG-{n2kOU?ce<X=BZ8YPp4D8wB_#5_tu^XL(5m&
zLeu4^-6#XoU+eY*6a%!qzXNul_PY<z7o`2{Jg|3Zk6cIJZmn4c<{s@b%Czs*I@0QU
zpEhzATF7`i19QLj3)-+9(B7X8W{CC$omdFfYIoC>AEj;G5AI3r#EIZWYZK?86{B6S
z4WGy<t&-j~aazkhf_|K~HU)O$wIiQnOlPzu|6=rKwO5Pb#X0R!ssc^Wj-c((;lT^P
z#|Y03ZruuJ&J7MP0*dDl(_C1n9%^R^3-v=ivT6C-HDU{8qq|3>MS#0&<fMfl`$x{D
zd(nZB-_!FXbmW;Bpe2m-y#w<XM%L>fl0S0AbcmFUTt#2w=8;3Fh$rgPn`Kt;6#rJ<
zrzG{C-!uSxRm4F2T%BnNFV++^;pe7<wCdWt(d-BOEn~}}>%@IM9JtP0_zkpNxSzuz
z;mwux28<7Ptr#BoalW*!+{-171;##Z6}_$E5SJAOkZ^A0OBy-%7eikZ*O$U|Cpnzg
z!=!R6mtd-5xFI8fd5#-KN4XQYy_+cpk-<&<1<g!uD1C*qINR$`%;tLifL0NAkaEYx
z+~7)pUgB!##A6BPoQ=LpF60BCRdGoabgbsEKE~3DtMdZ0o_kpYM;o}($sl*R2YFC$
z<h~z@0XA{#U4VIyo7YE%`ETYL>(P0i^X-J)7Oo`{ovqx~R+wnxR?zqQIj5(X%?oZg
zmCv_xkyIAf#o1C=zngn^Dki9hJADFPII$Rd<~p;63NT$*3@t-knG@Chxv?>X;?7Rc
zu4yNmG6Rxk54JiKGM=oJk~m&0XeUPK%`E7S>BDYKf~YS`ru)4gn|>ej?9T=c1_@xo
zE|5TWlWu20Y~3KVcCo{>9N5j?RRe4f%cRWtUUrp-$Ub(8PGbc#_B;Cav-~-*aNvFR
zVmv$zVc}}XgtC}GI2FcL(BZ6utc@Z^hgk36-W9l2Eja-9<JpsFh@4^3R5f{)y*LVH
z8mp$AYdU*=50jU{q9y<=lT|H)r7WhP<z)f$ScJYp_Ky!FFS25aO%<``^-wQnQ)j@L
zOKjf;D3q{<Q-Hq3LRz3#!+xjm?`>vlo)5)ZHgpOU>)C(@P;6w=#zLcsHPepj9@{<?
zZa1?|3L4&L6=N{67UoYU@g6Xv4f-Ck@5|BW#82N01rL4|9jEf=e{z6{y}V`um|=Wj
zC+r^M(|&=47`~JaFrDHHj?t~^G{2)Syolw$q!Pb4K8`YX@%%M9aGAmDYhfajk9h@y
zS$uVGxR%ZLp<q}Jul_Gw$Nypj^XK{3gQ0MNUqk_heBLV=q<~MQtXv`AK}nd4d`K14
zukrtu!HZjbt^=K%Z{WTB(b>YgtONHMKeP}Uudr2w-ERKb575{tS?UY-JtTd4(B~=n
zb|P9{lDI;c@RqdFIU65|{w}=mm5lrft^E>rdil!%i4WZ=LL`Hp03}qikq#t;Nv4Ou
z`-772zW(n$x02DnLh&$OZ2;^el0PqFE{;mVs3Q58#IqG7LehH&`XVKMN=)f-$-;HO
zJ}dcL1%Fc|6;vXVBN;XhJ{3yF9fW$B<g4Dmye|2UuId_zYY*(+mCSw(=0nM+a)>;V
z7%QP*ek|E@AI&F{H?siqRI++4hW$*kv<G%uC6d3O(I)wI1`Kvf&d!7vJrcLqkaUuc
z*bfnBX&x1cx=2T^g=?<Tln5xeNq?skwC+;d2#nrCYV`;DJf*Mb5#}ZR=rF*%r9V>5
zmycQc1>HY=rK4#5;wKd-zTz*PO$A!P(tA#j*)N?&$5#$W^@jixBArJ5hDyKkrn!`k
zpiu2W={Q=OgiDpykUT7PTnUsT(x;SgJSu%jL5E{_Eh}0P(y!^{ZlrWMCG}#Z=0|jD
zAWr&#f@1N~L!Y7ZjC48!+F5Cv6y%(=_kZzFY4&NrBuZ5W;cv2Z@d!*pinNdlZd0X2
zlp0Et-mQb(bZPjPn3)Wz(gR?bQu8lhW=SWlf}@4f-LGNqqVz4*co#|Q%oHFmmNvSA
zT#^PX0x6L$q~%1Zw5SR)Wzx@<;4>_jN-0%%MY^d9XcbbczA$lBT9^&DuSr{<f_Ys!
zAswws>5N3ES4n4n34g1l-&2m{hV;k^K;M%ZDOJ)eWkUdVUs`*g7RfEr{A3K~f%J<V
z=zJ&*lLPy)bk`K<KauVafap`H#|el$lNN=6*(#k}2FW(*pjg=Lk&ZWm=_Jc=f}_r|
z+#IO8$gX<<+EsRGJ^I{a^FD>TyX;qgc<3QJV-HDBS<NGQHIA3;^cQG)%O+oeqK_<X
z7(jhx{;SdQlZ}4^_d{g!B!CH(Eup1CnCxp>A0Cut)7S8jERPZ=;j&taA|IB$`4`M1
zvI;MFcuY1d4bTy?Ro(cQB4xvAk9%BJ^eu*TLiTh3J*uK))9+)RPs$ehK`~mkjq*i#
zvIXBj<Gd`9?vo|5!P#)XR_5^l%sSagT7PuO&QLXbl*PWoK)YbEVJR%-Tm0+~W{t(#
zVleA09(hCkfyEPA{<m6;PlDcS3(o|Aby!@Yh>_XLvbGc&-j>%NVuX7v2gJa9xaBO0
zshzQGqlABk<<(T!y<o}fz^t)MD2Jo1mcjc0>LG8UY|I|{Z?q&hD)*4Wi+K4g3VtWb
zf7L*wNIsO-oW=4FKZ2f*qFDi^zhd{-a4o>BNaD~8RJ3je%r1q`KyY^}t|vfrucDeR
zy?u(5cK98lh~5IpP{m9mM8XsUnjvyX5j+e&g)8RS!{9N+J9H<FP)s#IFH&)fvc6G@
zQ3|NXC@w8UU#!BK4mX}rgn7f?a|*NH9CRiqPOe2~lH#|$Fp;cyK~(@LiZ^s!r78sa
zieFMlOdzF-LziLjvVvEj@2bN83`|^C)Jy<qmEuP;yttw0q+4)}VlQ2!^@@>?AmU;*
zl4_UStY#LVwbSa=FEHzAwbV>Sxwt6TK{U{+I2L4&m2wF5_gTGtiYYl@we}bchFQfw
zp#>oRiB((hb8Z^tcz$>`4L^SjYy#T6?L+YUPhFlcFn=%An=Y^$g5MXOKLY-uaj5`Z
zTo()rONtl3>d#5tRQmTz2BjT;{mzJ=OD(Acb=jaejPy696@IR`K<T`VD>q@Zn-<ao
zZgc-YKx`>?$M0KHCIWPuExobn-%2W3+_9E&<mUHjI-R-0uc79`&8C8OSMItVihkTi
zO6B`=OX>C>VCKFUgk~T&fQ}j*;MNX>ObDl&1@ur({~Jac$5l{)OEQ<+1hj1K?;H%O
zkh??o?Q$*|TiX9kOKyMs63&|F?FENfD;As5BkVo}*pITBJur5R&AbLjqnO7;Fi$dT
zT=8bSX{wFZrg4l<2Yfv1l%q3|E$7fmV)98K$*j~3B!!))!r4p~=m&)?Rz~%o*(}Nh
zpU(yMF-4y8SvFNW6|m}yki5j!I>T-WJ3u90S6Bu;MJrfBHax$|9BIvDzQ+Erfy@my
zdOVsp*@6JHZn1Z$jO`9{>jtT3%V^cnz|K$z<t{t&-@2D|Ux3{fR!VWr2W%acH$G*3
zbHIGT9t1+6ojFGX>?QM}3#OBO*9Uf;_&U0=J(o}L#x%B@71NPE`fmcexq)<#?ctWu
z^f<9(Dw=m@@6#>Xh4t?XWmo2U4%Xb*{74XY7A8mEPFC|Sta-2w+OK-DXSBNZVwb|v
z=gn?XO2vour*jW@Mc5=5^<(XSz$DhZ&uFU_z>XLpbAY9_!P^k#Oy>YXSxy?9Il&e;
z!_rB1tU~cWFU4WB^ZjAjT*&^on!ddAw$woVrwFPsnm>my7Chep7Zw)Q17XntydOxq
zcs^ydmkdt_*w3+BA^*#r{_yBm^J>aCEp4Lx_p&XNdH?M-Z9|s_Q;c)PuXK0$LvV)L
znz->Ww!Y^l@HcOyN8^@D{lItQ>geQvJGU<Yyq(<4Z=n*vWqtvJft(f9M+9+)t>Mrv
z?o&r7gmT|e;c*zZu%6am2f2T<;X*i<yBgf1+#h5nl5<soL~%83V8(DGY3&`$eMdEp
z<y<7)axZhOM=*jbTv#bARd9|}e|(ku{SUONxevxd{WfPyg#r!SY`Xj(aP|y+?c7Hx
z(0jvm+=Pg^i>vq$XgyrnXTWx51$_Y%&h$QDCb1;sCjR&BdSJpYsT@BXN@?7|Kj2n6
zSI_~#3~m-BA~U&BRPUF?o#yeuXLG5C0F=X7)2_OR%b@&EF_)VU^-J6tx;9F<k2I92
zD&;(hTgDx90x9RFS^PIT4+;a^<v0p9HFEV-veU$=9|GnHH<%JPPr09Ij$d<c^yus0
z-lcOOE^HH}I$fC`t>xX=yL67jkIknVUVr927j^^K*b9){&)x*n_x}J}ITn)}!i<$5
z$Jq4%n2%t0DMlU10%&D(oEesY8ONIYfy6U`5?-n7SE|}gV||igDV^=kf_esfL7Rts
zHt!~w1uQQF3WY43!i^W1-G1m@Vec&kbOl?}8w&WNS(=Y9!fPy&Ha53e-6eF^G8T!>
zI_6E6>K*pMTlCelkso1#9xzuKS`S%`fWAj;CY?im%$jC_JYnx{fcjIms1MYivF((-
zYGq5eL7|P=Q-bR`8$h?87i<6(=d_#I5Sr(gtZfT?d&Lgkg{QCCXMbR59c(GBrr$8D
zQnWhRA}aEH%f9*<XkD!AF#3G?5qF>v!W%cB?+E|dDvTwHXWzq_GyIc1Ao=`(C1Bp*
zf2SD8W4?Gjn9h<htATk?V%|-U>Nv@WQSc^5vZf56<r2x)aKBda!A2-Pm%N~dW2a>7
zng6>5T$X-7sjr(z3z3-g09Cr&k$%4#L%%ESa{x&9@YZYKKaeUe!{`(IIdDL<Nq74~
z@|AS=0{Hw!y6$~Cf7Bz*k^#+4RzA8H28Mrve>rgH#nEPTeqA*>7v@uNXYmeNSN}Xb
z2{M1w{)qvv%n|W(L!cAzHhxlx-#0A~U}AIer_gfZ>d#>~&fG_4;CXR<C|%{vEu|37
zF7D&M0KePJUC0ABlnc9qW*FD92%Qm}nvxok+)jD~pXNL%>>JB{-5-*1T*GzrC3DeF
z;Y<pb`5mxRxqf?~p2mIM1@&~U<pmTnI8Sf*lF8X80ws(4YzsuPx%MuaX>NHwNG@kK
z(y}0r`_KX8JSYDF*cZ5)6xPq@rYu0KfLltr$U?3Uy@TT-H+45ai@4vZO0}4a>jiR&
zo3IroO1MC}h)TK0{qUlU%i08HIp>`Vz02H>H^98YePDxD1=ptv&fMgh%~Uymi`z5{
z^Hsw|X<_L$_iPP)uAEI1yr|>;jDScpcj6sj-{%@=v)aOaL?>V#a4r-Ne8_#X3fPah
z*&<LLbMNtJJ>jm<O(LH4Spu*m7BvcBDXfh?q%@XK!SW0?Cx{koIjr9t%<OrVxdekL
zU@K|IU&PjwL9v8AqY!I3E2ib<Rpzl23O89L<(2NT%dT+Ei68U399;YpC(&5L*s={E
z2ig8qs2*Z72`HTDvLSq!i4$S^2z#^*jvQs?q@B<^#yT&;y$F`w3!;(C6;C_db^1?%
zl@sji<xq@bPE-qZk~z?gIGSCfb$SeIvV`O*w&OM=PqUU7NXD`kO=!ijKpR+!XMR+6
zbcP+;fWEWrd^cQ6X6}?v&0!bK2LY4Ircsc$hz;6`&SG|}63$#=-%z%?g!xRw9A9T2
zu7>$acFuslDt0~&t!idI54}6=#CQy}p2bq>egoS{!JNCSd=p3`^VtT4CN`3eu-;=z
zoOwquXHGGEy3dsJ%y6-V)%*#V2kbQkhaWOt0klVK4c(<5vp*@|{e-PeLf=z1H3H-n
z`-zsfui5I8@VA4lri#%w%!>|lbh4Z_FyFFY@*&y9J{}9w&2j?Kx0C<b0n_Ed$Iv}9
zfDfsoP-P(hHwB0H^C#$_^#MM)7Of-vb3J5^@<)G#Ml`=63_iv1-&0QN9RG+)UlRB`
zcOjX<ukZlL<h!V1E}!37iLn&$Je4gK@_+Ax<YoSz9^?wIr2th0ucDf<t9;9nUbz2U
z<9Yf*U+0Z<O1F|v3WVJ%K0OGQs`=4}KyL6u{)Na*zT`_dbBpI3z^vhY?}OatcY1)-
z@?X(%t&U$#PxU+e<P?C_^JR2fZsf<u!?h-U9PKIZ@rgMw-^|Ns*K2;jr_uuHA)nZR
z<|96$1fq}m{*<|V!uM?fY31#I0BPelECTj(zK${pUHlMN4BJU^kB5S@<cALQxk!3Q
z#8r~N4t;JCpLZeYF3CQHDe;u7P{NRxWcF0djITs;AI|uhCEiEizQ5#ex&pD)r}Di(
ziRW5$o|NQLF!r2eTpBboB(-Ufyde273L+(voH#HaN*+>$M7Q*vW_aN#bEKK^m3=`w
zCx6+h42bNLjlK=&5LtITn4z)|SG2-pGbt*0P-Z?F4SGlxb`PM3W&f(-@KISC#j+w~
zy_EnxF0<=J&d4siff+3;wgza7tdK&ar(|>PK<~8d484aYPG*w>5-*!v19C=Ihu1v(
z?}4)5X9&-8pdH&!mt-(F|E3&<7Tlj_hW88qeji>hnm-vri${NrpUZ!F280#oDK`82
zH*4_w9~T-Sv+nQ+$gl51wG<mNX{E67{675L#5cmy=BYHaZRffm@5cSCqq*m#1u*Bw
zc`u|H;XbwkN&weQa~{a?4Rro6i2I=vSIGhHHa$l}xEu5h59JQh9Vv_(PuKWCF6ADe
z<2hv}tR-{pE<nrVxB<{R&yDySq=<V%`>%5D?m$e_b#6`qe7wcEeT`NFmv$G<JmgeO
zV7}x;ngS<QfaS~|h;nxzS%^EL#`FKziYV>D2;?49X;=^!_aSr-aD8q;H-yXo91|YO
zZJ|7H7<czm*o@#(hC?!vTT73h)7;5j@I02=asmo*Tpm5H<GDk@&+a4K{opP{&U52e
z!NLV@8f8FBIG!F6rQCf3n3dd6imX*}{-dE@$8C*4>khYY4KVAud@2@b;I2`WKZbp-
zg2*X0=005m?BWCrHI^MOf@B;ULK~5I7Cr>z46~=(^jWscybWWy#EPP!QOCBw4};<S
zAD@F9=KC*0-x1!s6ef=H!{}>ujDPY0rYeH}l}=+s@<aMT?>PT-J(wqWyR{IB;-`(m
z08jF{|H7GQe&%~{EkGjakG?=j1MLxmB&+DTx=W(mKns!Gl0XVw?vbR%!>PTJ1wR6N
zpJW5A5`rb2v}4#WS$hbr1Cn7>)gB^QF$;D>B{uCCn!9Wa71G7Xyw<{Qtn8p3t#h&;
z>1mrJ>qAE?Q)G>AFo+D<>N60@lD(!wQ8}_{8)><pC;LJT(U-EPdm-v;;TZw*rz}S3
zz$~;FoQzhnh0`W@aou9>XaBe4Yhh>UEklplvNQ0jm5q1}v37Q!LJ=M8`A|rE@M+h1
zn8QEeH>x$AbT0}sGOb?3@6)H#sf!ug%~ZNLGxv9Bf9nyAN%^jB9Xe*2>5WF;Ya^k&
z;3b{lTsZwDelD6rS-iz@_wf6Yvqxd<=fp{H;FtDqp|x_xApHL41j@~?*Z&CrH=GNH
z%=QE2;QxDd6tvvA0xi0Cat|(`$HUBhUkR=!x6d2Ii!;uJ)+sKPUKNnQIb=g7jhjv9
zh;q2`6k93aE*t=}gd0TfJgeX?(EL<$y7BP0miyr*T20)a7HB=<ipOH4?Oexs=yh?^
zt<mSo5(hxfi=ABZ-x3A$FAQA?-=`e6!%TeXP8-UN5=)Hx6}O+>Q1Y5<qf4ig6UPAb
zEteew{T}WFg|eO4vai5&WzQ%R<;Hp!0?C8z{|A;lnfx|HcC*w|0N%q^S)z5C{qzf3
znar)>e`{+qR#JI;z^Z04Utru|>*|1blg(0MK5ntvAE8ylE>U>+9^3pmB%7JbK(rn(
zuTuE+kS(CE?i2QecFRv$S{GdCU@p@zf;Y^Gg09~D?;RliyfPWkyZDiRV~l(F7FXz*
z_ws%i*Z&r4Dq3DW=k9C-(hF`1t#aGB!P{Z;CHFcAxUaa{aUid`HJ^a#%F2HJZ`d0*
z;}i8|b4CK!k9|Pv+P&=KOsMZ;18J)i%)G0?3}<$pP(RExtI;~bR{lfjo})}dQQT;@
zflkuIu&QCuIK?)Hz~=<!*8xk3Y;z-8nQSyA{<7GzSFlvTEU12=kR9KMIVxv&sm|mw
z8$l_Vn`|&WX>T!`YJk-+Ed|?evq`k2uVwn<=&NH3@w)TnSgdWN1b00<Q33M}ES<{1
z@3Mb>!_eB;b4uquXV+<|`hvyLs-vA1guviS_Aw>*UNhe{ki=AP#?U(1o(8mB`ERHc
z#f?AU2$945qTrvO;9eW>0_t^q72Wh7^QUMR*Uqn<1<5Ynq8N_4OSIvz9xNF$0VpvN
z@2}Cyl2p*jtz6R51V8Ue)*OZ8E6H*@fcZ!R=`OWbYDekrP^n!2oH#07`V|Hkg+K2E
zW|(Z#|Euk4pQ5V5_}+^g-dwmVj!BYHk_aNZcY(Vs_y!9K$oq?mAaJ>?w6?G-yU3u<
zI5o}?jbBRg$)duhhM35*ak{hRBv!^~Lc?UEHr9vG50Hii>OeL1J52rw-kmeg`905h
zUiR*}=bqPDJ}vSN8$T?-@4IX_pPlb#$LDY_2H8ohd7<t4h);+QvHiTUJH@7WOK_Ui
z{si<nGwnnaIty-sLV*2_w^Hzz%<=>j&a(O>g!UC{y#<HEY?z<WJ<o3Qy88{A;X8Z3
zWvfikyTGhvhrzwb_ML^sD6{b+b7QQr7Qy_$jQn8ckL={z|2J=25Abey{x~0e7u2mm
znZgHr1i0-^DL6$}dk{nM7=L0*PQ3xu(%0@lT4uitt@5#t5pTu&|G+_I*h75xstF!t
z_2JaDFtlCmMp!#~`O@{yB}Y)SX6rai>{`YT9oELSz;s>gElBIjOfZ2zK!lq{_ar!~
z!Urc!fdeS1T{;9i&7Vxbf>YqLLVLFHH+{=f{m4H*#n+Zy)e$JUw<rzy7jkwVgV-JU
z7GiAeItD=-9S6r#$~Sa*|M(5JX<zLPgwmdV4|(6O3E+2r&-b7l?BFMWUKA9*QvR}V
z&ITL90tWpC13GbrAj7AOM(+x?40E>E>vn0X-{ooZnJcS`Q>~7UCTBrzUW)4VnjM}t
zzq8HnGv{e;m)GYsd)*x^E|jE}86hvORn<H`C9OeD;UBBTnrgAjsj^~K%zlr@?W6DR
z2~R(69|M01uRd-c<1@nQ$LvE7%nDZ~sM=-Bq%B#Cqx8TvabirrJ`nWRN-9r?SkrA9
z2|`+ggsrC|3@HRDR5y);{redWJPePb;a@@*QU5hDT#r8xK373~13?>gbu|2L4RzKV
zBlYfth^)LV=4zj_-DlR+cDKi8&h=;=tqVVL#g3|cv(Kw)&IZ3zZ8bZxOV&Bm_U49S
zPjiRc*-+`(<L^}4o#tF;Q%8$_-W}2TU`c*uUc>h6qUyZ349mh*-EGqr>o(1}lF{qM
zAreiWV<D6_8lFrc{o*qH1D8=e7-N^M>tw}ZNsN=_l++YC4z<T>vB_5b>zl^th&Wkm
zQWdpXQ7sl*hHO<WX;xc?X4TR)xyh<1w(k4WMx;pn{&dt#R^mBSZLIkk(5*3ucpJ;8
z<su%kB2FU>227$GM3cerl5R?tu7(PAG?^xq3U0EeOC!P|5)`1LRIW&!;_N(KQlt_g
znPP0<){%>ocnWY*MPV5W%o<L5X%Ixb97*#TQi(VlNriT3_R<ME*t1bI#bG?zGXaN8
z^hzd5U5TcjIh~EBq%4SIsVi&2!9@_UFM*z15AI@et>-X6UvRjT!Zs{8tl?xm4T6Y6
z^EAH!LN^s`1iT^9n;QYsXp+OeXv*9KSVcXXptF>&gNU=sDQPpfb=0*P@b(J2#Nknj
z$>!2$Xm9p{Gyn*0SPr;1pQBwl;QDD05TVU+?%#=2=#Y}cGa<C!Aw4S`p%V@%A-D@C
z&)%a84r!IJf+oQc8p)I^C5UI%Qf98S8o{f8f|q(Yk?1tY@}<d=;X`yR9$k;J{{cS?
Blo0>`

delta 126014
zcmXV22V7Lg*WI`5?rYooMvXOA>^-q-qOlumqQ(|WqOm10)~sLyqzNi2Acz!cf`F)i
zqF6u>EEGYJqNt$Q8-nO}F5f>t^XARH_ndoY_LZ4C^Kf?^{?c{0cPnYDZYSDIb70T6
zVI?nf8Q(1q&Bi)>#Y?18d6$12P_V~Oa1yCZF8{<y6wkd`iFA_fXNd$NHl?RjBIV@0
zl3~EHtqWO+N+$n(<=>>6D~GwO?|p}1U1s`ll8MqlU^tg)(g9M5L^kp#$qcCrBob!i
z1Wq!u>0HJf@SPyD*n0fMOMYpRXc_0(jAVAxxsh@6-6FH7d}lC{Uz;SYn5(`=WET6k
z?<A51O_Cl=Tn`7y!lv^+OvkBm$)cw70nF4sqU1N}W;h(g{GP9nEN+qyW879Sk|j;&
zqnNp{St|8_%^1dZoR=(Xl22yhlBJU0o6e^(Y6U0xqv?DWvlRBrrJFkgFo*f{o|mj>
zQp{(TsvIPLHl6>*tbx(WCeme0w(kPD#cueDm8@x!tY<z=QApM{S#D*%dgmbdtLc2Z
zgpaVxC4Wn^K+X2VL4Ia7y3OHO4lj}DrhY$7!u(I3{ujyb?cs1Nh+rU>a<b7i|5GbE
z942+4Ooro;m8^tus2<!JKbk{7X9tOcMDe7RM51tX*a$1VSA{5Hp9s`Pf@26PsU|G_
zw;lg80j(S)5<`V=AH@{Qw%u|Gliy@X`sPh~aiwp7q9x<wo2F>bL?u2@^pZCBo+y_%
zwBT5>a`2V%a%0HP3W-BAh1@*Xw<rIV#qbW*HlhQslnYO62uUfGD_YBa7xLdqJJ0hy
z%v+d5-(<d}GRa4j$Q&XVqrByM-%5TZli)j9=+C_MbrE{lD}QAqvL+`od8ec21&O@#
zY`s(>@3MFZy3TQhOe&E{<T#adX_VtQUB~12-(3Zc^Byxe=A@B9?_U6t_<sO_WM@6u
zAAUkMgFlgW!ga#dZ6a;@LXs~G<!~HqKPRFXbC!-RmeFzVVFKhWr{ku_Bx&VM=klQh
zcvIwn<G;s9-pqyQzQ@fcmyBh|LD%m{du{-^U)D$gg`TD3*db(pEsPlcNFvlkbQmmO
z+DYWNgeu?1(7Apjfv=hg)?z-vZh4S<rjVi@{*K(-x=ohPK9gmy<s_+IN0uE1Q-9QF
zP!E0HMGPNH$Z}OS+0=YXlDwgG{vw+^maSy$DEilsgCU(s9T-UGExXZi@FFt$I*{ZG
z`;+_5qlwNN_pDs<&t_`3!wxzwe@2qWt;llHI<lF0i-HKqChhU$rsg@4WXKEBp81~6
zC4UPN+$yi)$XU%jau7P1+OcUNsjs&s(?7IyJQP5kR(q9V?>3R>u6Ltz)g)>$dyVV|
z9wB*f4TZwxlYPKal9%nKuzFo4`KBte@or6ChW?17UDBn7M0b{xC`e0mqq7Nc&q4vY
zJs~&S14!~Qmu!{=lFg>3o;W#=uyrmZ;r^hu&fH0oD@kN|FN_$<CQ}d><4E$;_Y~Ik
zrzCM}y29*B0;po|P87*!DaKn(?HCY2j_W!RU1k>|auBE|dNy@$^lCcqHJy%gUy`L)
zlYB)}ps5yOyQL;)E>|e@`Pb-telCTm%cD>l>&d3Q{TFgSMni7)r4rFt&!!mTNIjtG
zLi^xHVb$i*aorgTMchm_k3P`3v?W>obBE3!_>#>&FLJY4M~+|llV!y3r2X8T!Yzs;
z?YwCE(WeZ??~l9oA-SL1)NZ4SjD}4iqJiFYzGWUAXSXDqg8g*7if1$~(m1j?n?l;f
z-_ZG?r9|r1blGlGla1d3a%^^M3Sut#I`j`o^sNXrScBhRE(uYR`qvEvUi$-e&f^z!
zUQ$ixo$>CJOVrgwr|eAUtr)Uz`5O_n$|rgLeX_JP*<WdLJiCT$O16;v<Xv+7xEHnC
z`i10$S%ebH8Hq+NS?x+{S$m?6^*yVx*w0-h>cRKObig(0#*F85-k@me>J21$=Sg&N
zx0}wJ9wtL_sSkYil4bd9Iu~A&c5*23`wpbzhiw$l*Xu|wenVaszM=~tZVE}v20Grg
z&!*^JZl&X!Jp^#nlA>E0xesjm<?i+&_g_7ypr`*w6dx=knL3LkoEy1s>qnB(BP40W
zYey~#zd<gS^2A)9L|Pq7+KZQn|I{QpPXED9MpNgI(e-q4IrTmnW$vb<q@1Wz1+wXL
zh#WUl(fN2a1$y`*Nqle9`JHIO{>jmC(+6^2mP5y}cGCJSr+#{oN$24g=;z))fh@hJ
zvUE*E?<7)X3o=^LWOVC4GLpV0dH7HYZp{kPJ`SSe4_7HTebc+De?GM=t%~edq&Ky@
zEumcgZEEFJl5cGKxeL_fvg1|?;<r|0Gop=xo{1&Hi0-=|sIBtp1e>*()P<c1?6`(V
zW5<!?%N#m>^@@ll`qBB@HH31SPL}x>2)lP6g*f0Norm=%XZ&Vrz*t|he=vvoY)NzS
zc<LXV+a*r_5uH4Sh+2O~MC0uw`L5~ixPFz+T|)`{@-KpgeodrnV#vYI{pjeTB%91|
zI$FojaZfB+=Jh2u%{_9z*hrSgCKFG;raMlzk+k-&2a@B_Q>c|L4RmgwOI_OL8Nmcc
z0(e#tc$7bpM#qw*O)S|TJ4tQ*Erqo4r^#{59+LO|L_Bd1$ibvWLM<9VoRb%m{o1u;
zZ~cYr7ukmrpnE(4HapY#fTwiqD<RXi3n_?%Od|6AnPA5k5s|Zmx^d=QLe2V<B;R-t
zN^qpU8Sx{@C#2AEv5n;8n%*PIrmJev0AgO4M#qzGc5?7{GCAlufzE4JQ~S1TC2+`Q
zlJ}cO6pf3CI#W&OZW!<>Brl94x!Rx3|5M9w+_Dm5dC5BbWD3dNV-(g#ZwwwKJ7NVK
z12rs;BPLV3-S$zh^x4DNA<FMbq)ttP4#%eJ;MQX)<j;$#m5v1zMCf}0k9$F+1DhVJ
z=9;E<tLf;@kmUjsQTG$b^2t(a%xn`iM)8sOy)c?rNV=Dk{kEsX@7<4;;Qs&R7m6`=
zJVou&ks{sn9hsi+p)T^O27#oiAK8Qk(sAK@`XQpukOO8BIq35h^_I$sv}gV#xv39f
zFPZ5$0z()~Bp#4uTU^u%$$X3u6_T&V!J}O=EP!CeXUU~5pW@ori(34yX*7^~l&Bvy
zT`Z%UuK7AI>h^UJA}J(t+wI@b_V(K_a+i1haXGqmWb6i<Pb&yQOQ#Qg1MLip6V7K2
zashJIfN2Q-=PD~g`(@NxJ1UDDod8=}Mg!2*5%dfH`-ldVcGqT*Y-8ewqhH;bHkVQC
zXNqZb;m0)8BFF=b_9AKrneYBWaftD)2F#zSngOSQ%)DB7J<M=@(DEQgeH8Fu=Jaql
zKEli_gk=cR&ORTp9%a7W4tywck%Kghc}~J`=7}9HBA8F~k~_w18V9yW=1324M=|^e
z0HT?Y^@u!%dGHY2u}m>NwU0AhQvr`-{8J!|XS#ij+6kr+9V|~^JX`=zWabFaB{7vA
z`0eE<neq4GH<{_HgY*<rPLJr*On@iY&M<8vP)lJPGvGdz$vFyq8ngZwglCz2dcK}x
zGW-xsI-_X-%Xub@9z++IYTs5Cqx}gvy2V8Hho5|=+b`(c0>*DIxC)uS&w{In`6dmK
zl`uXtz;%Z?dJ*B?WjfGvtdyD21w|#Z{s|mBV60lOJY+Il0C>zyp9+?0W_d4kXf3lj
z1h{9+-j5KzVDf30{gT;W|A;ocV!AAW^flAE4#gYBUID*vnesExy<>Whgz!CcX$lY@
z80TlG)iHhAA<%ke+)FrYVBFuLVV{`TGthluF7<|cCut%LlANW9dl2Dnsq-fR{_(H<
zW_oD!Suh%qmHu`b=&W){gs0VRKf>)A;|iRw?KDjC|K@FcJHn!S+)6aChx<Vsds^{C
zk@p(;HJtT6PZw)2GZpigCU#k~HfXJ46b-7`4=q5**&`w0edWymTeRLpFR6~t@C;OJ
zW9&w{khe3Qc%~~{n1Ly1mMgQaC7x4m%uF>PyP29+xEl{M$7ysL#O%BWlMl?~;Rvgd
zDM|;~4(a@Puym95{T{LJlh$8D?Vxm40BS+f{T}FmIBAdHfJ>K7#f>P>kvhG_G!xxn
zmusG^fa0sVd5E}m;ZLCJUbGXs!5bM^PMzBe@%?#a6^`yqZy7=eXa4#PjA@K|10Z>f
zH35%|w~X2Ee_bGaKMRD~P(1b(UFvS2nT{LqI#6`2+>D1uH^n9-S-MklMbV>n0ABBk
zo{5!s(Db^&qMv%3%Mf&*ltbv;zMj(%M?bH0#L?dxg<o^P%yT#nY(*oHZ=JK?e&iHq
zXvfa>LtsDoY=!;YK5b#Mtj9?3thwGE+VxBHkUKGPyU{ooX60&d`!d{nkoeh|%PdSn
zm_LzPz#Zx>2Wc`hViv+a%``=ShG_~vg=vaEm1$}~8q?H*vkXP8$Y5#*pdl9-YDv>|
zAo$ZW-4s%QqwT{8#L_G{3=UhnCnM5t_HRLdc9_<Jrkq_}r=dH0HtYei_bohZ<pW3m
zfnWyDq@Qu<_sbB`sAIDc`;QN31~hT76m(N3{)apUUC@?xxu9&Z-Vx_*$MlAiPRZ+W
z?Ayu_&W9FVhWy83npaLup}TG?bBBh`PE2#8v+QzbCV3932N?5vkRN0=?LcUUn0NFZ
z4`E~*z;Tq3y#g?l=}?3yjxz%Q#Ph59OZbgv;zgL8X8wKv_!(whBrH>y4I|+75|i;S
z0GFA7L|9&7%EHi;0%rD4Fezj_Zo;j-h*{JH_(x2dI}neV*ED^tW(Fx?`kwjsBJdxW
z6K&wIj%ncx;ZEtrX0Y5PRoBCzi*$+}!u`@4HWYr+EFX{^kScB>`fzD_5Xd5=msUV`
zOnQ1caLLkL>tJ$9+V5{faoR4`rohD&X((kbGNq&Hp}a1=_X)*q>Cx5@-jmL!->ghp
zM)><u|9EunBk97os6CZ-QKP%wOZ%-sW41b!{Ry%i4*f&`+#RI5VCmuT@fJ)DI6Nu_
z=Rt?K*02n9ShOCNVGef5Sd=FmZd`_^1PAppkX~>YIS%*?hj|#NH~qw|ZjJ<~?Ubje
zwySnTyT7@zPVxV`5u-7Lk&i6%g0E3aQgA-nsS?MfD&~LJ;#cm|(f&?D7l71pO%aaW
zH+00Y*X`C4Tz`GfQmSG=Te|YT+wnVChlD>we-FR=BLW_EX$4Hjw~^vFZRJ+T=d7l=
z*l#c2K)b>;9LH6L*I-yXz6fndRqRG8P@bj;*a@d+6<>{m>XPEcQt)OgHcFwprD(qm
zzDg7qcme*ev9spF^bH#|2sTdqz0YXt9{$lVm?o(uX%MEWU%rFqJ=)ZtP}{4$m-N4D
z|2T8J7J=PmoG>tv-($AeP%C3j)BCHEaWo*%`%K;;{L&AYO`$0EN*7;-vwhO$Q6Th_
z`nLaCZ4da2aQvkuEx{2eo%kNbVd>a(fP<y2XP|aOdgcrqAC+Dnh31Az!`u<uN$Ia~
zD3YbsG-bXio!|@Kx1`!k5En>YX}Vb`ttbHQwsbm8!;7Wozk~3ObQR?U?n;~eiAe5A
zx7+(bS|<Hi2-6B_%T;K8rE~~okse6d-$7a>?L{fRN76U%(1gd*l%WvTNZtMb?uqm*
z(w*{Jsn`pEXVSAsc;Z4l{~vTt4)gD#*yf-^9$dcNq1|*uztdsaa|E-?!Gp%!#~kG1
z5J)2(4$?1l%i*_^sO3AHWI<EtP*MtqMGj%n5EeVEr)gq|LmcH1?mGNHQ|3~Kv%afa
z8ttBQ(CP;cPr^a+(4nd`3?Dg^p8>ksp~FqoY8+0`>-DKa+@Ij8bvRA#o;#f0i`okZ
zk2+YsayViD%WH>JM_9gf@Td9RJBJ<KsC{s7e}|^jIpj76S-nHy9pD-qa;bfd4h!r`
zn0|J!{D~$x$&yZ^fzGn?D<Iq<E2aniPTAy8ICPQu6rf?QvYh1zez$D;F*tOWndvd*
zDRcV-HZR%2+raIS{c;eNKC-O!aKBgfiBd89WZ8qD^OM!~Kyg5Jg)#;HvTN~n*aXO4
zQ*!OFth5MG1j$xVV~)sdrO<`QemaSm!emNsL=i4CBqRJ|vN1^d$s=W^od873{u~5A
zj4ZA%YR6?SzXn;H>|aW4oRDdT0+%2&4uvpDHZvbT`AJ#Vd;m_%b}o?NHaa7#>k771
z*`*lZ(`30VVRKHlR1KSSS<mBW;RRWL4C&<=GUa82e@Uih5yfTMAsS0%%3`lWm?ir?
z1D4sc>1KqTBkQL?kt?$ef=Qn2FRY-*Z^(8G0n1HUo4p7oUv~N?kJm_nY{*Ttut@f9
z0BCN@Zs>t1k*)JZaYxpk^2nt!w+a;ZWaoB(rd&4o6Pi{b8%Z<62eQss5|CHP#yO#Q
zB+KdwlgG04C2&zA+tnVzC$j%;qj)BB?+i!JWtUf>OJ2$*slZ}?CA+c-+;3!A^$7p1
zthN-&_p)^!Kzxv;t^wOe*`?tyt(Upxg7lN@w`J(AMwwGEOt#7|({#Z}ZhQ>fHhID<
zuxyvF_!^<@l>1CXSMHMUG{LW{{2Li?Zu0&-Sls0?EG#|j^3tE-!b?857%sf!Z|P3+
zk@xx$LSMPlY1r(SPZ<pte)9E|aClIDGZn%^^5Mh49U#wW4a-2e#uxA)xhex494rs%
z3zHD}F-im+mA|I`4U_k#v3$7vVjOCba-SdIC`xXRrio;X{GX#Rjg|YQBE&fPm>4uB
zUj9&oFj3z9F}RcDf6+TJSzdS(G^gawrSN-3?nBwx6nOz<kkjNhZouTMe8W1x)8)7K
z0e)USjD}dZ<-7NyRxJO8rWtqTUPFK@m2b7bK{RD@hjCDr%OAu*S}9*12K;?_-C%gC
zl7En(zaGkaJcP+(d4GDdR?Bx^L7-a|j^|J~DI5ktxJ@x?8DiS5$fJq)PQ@s?o^~n1
z=pEsz@XCZEH^qnXp!QH~rF@pBBC9QB$@VC|qnDSDV%bG_+Nap40Ajyl8ztlpC@e+j
zsDq037hvMA*g;vh07cw6;BF|^4MOdv;_@t57AVf%N3Bp1Hx)76R;a%Npjc731GPH}
z8D)j<Dz0^d<vj)08MQJ+`9Nd|<P{36Euz_qy2&UWC_HuGu2R@2&G1Muco;|@D;_OG
ztwvFI91%WI{PQOoTC4bb1}vW`O0Y;Kf2jziH|;CM#5l0LRlK|k+&jh0cv#jcdM!Z|
z9~H^9(0x*DS&9ZWDjpyiV3&VUC@KB3m0k4;E}U68<>$AtW~3$L$JrSqjAPfmfr}Gt
z?r^wBVE63<TM`?efDS&%cJ2t$Q|x8RW}IdZv+$e3w)`6`sqDoT5T0d2&!TpYy*~xI
z^K5Hc&$z(;MdMTZMOHoyHka5y%4lC<2NXe?$tF??@+w;t48PfIG(AzTvEE&v%VjrH
zR^>YD-hkim2D_c!9Jko);i%=aEdBO{?D;+@ir6|QP#3dVSPhhyunAIh-d%R-8$@5q
zo~ImqnVq#HqxI$Njai7Tk{vt>e($r=r*Qa?ZQOy{BleFd(A2PbH>va4p|nQ!jJ^3I
zgwNRn8o*z%1I{6e*X(jERm$J7P9?y-XLX}s@{!GQ2B4n(m2#_%>{oRAe`ePYLlj#%
z-*xTP_6605Z#!3Y3?b~~uB4*a#r@JAcCK8XT=2Vb%cv#p+>*86@Zg50qwwNPuCVmx
z{@Dn)59dbLhA$U(9>qS+aT_Ap&$T*@NHVyB!D#G7E@vo;E8Oa}5N2}EDf61m^=V2A
z=5U@F@RZ91yas6=7p;K98{CL#5Z>g@e-E~NE|F$@1>Dtrpt;SBbwMW;bDl3@d50T2
zAHus_gcsbGaWTQbm2+2VIqW{?<PXjVTryEV<Xo$ud&C{v26#0m4zq*1hTBR{zNg%h
zDm12+tBXL0&$%Vzfq21P>;aQkT&GDWUUSnQK=+noo*?{pT;XU4>o^}T>T6EA91a_}
zM#}qr;u<=F><cHu61RLSub?rYGv9CpwQc<DpFq8X|MHloQakxJIgq;Wt%A@BSH9h9
z1hbnT`VubOdH?%})RP}V6D==35exDdX6~Z7t`Fbw5NP)CnynD-=ZiDo_W-{>8nuIb
zSDIl2@Hgq59moeBgfN(YRRohG{1ckQ9Oe6C0AQDg^1}-dcQ`-uJ9vuVr9Mzb@?R=Z
zi{fW|gD7J7Y8s-(@(hn6jt{JYFrKfXM`a>^@>@ia#9y5S?qq&!HHuUG=Ot)M5q~`b
zEG2w9dLZ24E6xL6%9lo?xX1UN3b*!hzJb!K75p4bx8)D`J>3AT;@>49?nnHxe*t{V
zFPsR{8eXJ#;1j;{5D1^~&$`0oIiGPHwO9O4$dbxm^Ls7>{+4g~1B!S2S(;3I;0M&8
zsN)O1N6Q-c?d1Lw?>`HT_-yCTB!lz|pB@Xmli=?THfMp)1^0Hrq=9aS;LsLqyM&(S
zVB#Wl4*}3ku-$>>Zo&8lCLTiH|6t-Nl+x;?x9}|u>GlW}ln3+`29E`9ukdsxaQlVN
zly349Cinx8AlTPThBQ$~r>E3O;ipXWSF&)LG9#yjKEET1Gs0lHWm1JT40LJ2K_n;S
z=Y(FnL6a{0N`ux5!o>aXlp(|{MeUL>m{!;?3wwvdGE-<lne;3n=NV$k7SbrAk|X>w
z6}3EJyq%_S*M&{AoO?^~SO#Uj;CThYLZP_^HbsI{H+U)*{xah?C=o9H0vC6MSy=Xx
zmkJU0VNxzgnxj@B$abI+_k}@i0e>JQ(3;>wp@GIPkAz%$kyi^h=0R8^{JRY-PlaES
z?2y(9HONfMp9?>XN1wb9)=UE1D`9ImbgzX=^a_6~bgzY{cS0Bv%JMp4pbLtR!q%Q}
z*dSba3er!4>>m30vygfZfG<K%1B6cE1X^8m7K?O<{*dTD6gq#g=MR7fiuZrVR91di
zoRf)Yg2n2Ah~kKNJr?ediZ5wo87jV^^nSRwO^PBy9C`*Ok>b48s6~m@G&zV7%V~lX
zD?ZABr#LZ^h6V9r8ckUf#63JbC5lUF!go@%4unav__Q@bJ1ve+qIcjKao%10PO0L%
zn<&ym=Kyp<x_GG@OwWrgX||RjZl*<vi=uHaYFEVU<LH@8Q5%TbRq^U1ILsDLVA3tW
zCO%z&TCUj7AGPaZ3mU525a;fM`&;7o&%v25deLuRDEfN>ZZ8t&6hm1o-q?z2i5UJB
zfOo~xCFt2w@$w5atxU92dbnKNnE+s=c;qg^zc1#_0e6)ca1fzA6uqv&<gvJ!F0X2F
zAgy9N5#N4>$y0H6G-{3FstAznP`3RIg^x0b29~~d<s>%*wO6^VKiuzAep7*Bzw+W6
z2>p~gFBAuqwyQuKRC?>c=C52zt7!pBi5^h|DtjJ6Oox@lG}R4KmQgUl%7C809Z~lB
z2DK1nSt>k*DF@a85U!kLK!lOXO#vW_Qrh>8gY=p*lX6A5%8B%R%~PJG8{oQ9OOM$b
z%HF+E+*Drvh~k!V@kSK+%4dWtP#P>K3Y9G8_VOa-FFbI!l^&FktWfUZAgokwsY2_k
zlrN5<s8)7yKxj3}-ycv1DP{JJD4!~oo#4J!*)<ErGiB;p1$^LND=$j4wkazIrfttc
z^l-ZqX^?#LM;;o{K7IkB?NHtZ@{Y4<X}(jKE9g2W(jrxtZRcR)II0yST{CGBzndR*
zZuiGnppo}bf5EY*-cC81UhRrN+B=kz#(ln}nRVa&LjdUaZ#r7g-&g|&1CqTV8906s
z=)PTw?5X^_U9_EN(DSVz8XQdb-q0@DI1Xz~J86dB3W3dt5tO1IncoSHM@^w!2;-6m
zK|X6mHqMu}?MI6d>up!yz?tbr&u0(D!-Co&=CBraK}_i+P=+#I%OQ+pTG4NKoEdwK
z1swm}*z4{v+s!&mL3Hlyj2yW3U^8hr;mMw+m!B8=qdRoo><&tb>|wv9gqRN-Ps0&k
z*3Qw?U@z-S`M`bbjE#`)XJgGU^<#@_Q5;}v55TEEdq4%!0JgR}ghA}jG;|AQ*HCit
z2;1EWoe;u)q{(|2d*}}U!r3;P5n2ShFABP2Y{YozBH8A>QADws^ASZfyUM;0eq&g-
zW+07aLm3puStnZFh+{j`5>Gt4YYl`a*h!S#OJJR5Lzu|MJHSN}>n)%-$@;jWcaqul
z%Yi$^{_qyU)2t)Cpw6&!Xl9VYUR{M?Qd#G{2s@4a)(tV8Wn<E4rScs6^#>H`Z2x3P
zGuV2%!7j3;T10w@-I5L6Wp?E-2(Pe#L*XKmU3w6~WU)oh;P)yU6bM`nyT317Tw@*S
zeV)roGSKUJ?4>S%UuOrD0C$6xs=#uS?Ku!8w^+Aplu9dP{~^*Mwj1T0Z?iQnD2mz8
zK`<?0S7F1P{0`f_HQ4U5`{ttcrR)PaNbj+Y<i3o(o&#MuyJj=Gw1U0b6TwunJzIh0
zKAT0q{R3880hTIu+$QKAvY%<x|A=j9#o+n-n4Lk()Ya?-@>|2!B!lz`tD1tCp0dxV
z^K03ZzR*2mlPst`XDiC#{spVuhvFr>F&(6@*!7g5f6YE0j40l)#YP1BmOV>5L*B8!
zoQK2r>?YdJ_JN(<1}63F(EBLt4Qyx{l%Lr>`(gTp?L{l(Te;y)Gkfkfy~}oRqsYZB
zZrdIdF5HsO0Jw26i-F(GZGQ?AcdpeD=sY;*AQYb5JL(cIZqyCbytyHZ!MTUa--VhF
zS3z$}UoNEr@V$2K2fBpzadj(D_2Z6H?%@C@P;3V|)dj?Kg!^*=iV&_~5BwhGRtyFp
zlzUo<4hrKu=y4d%1@ZVrBe<t;U~-JhQ-LLtJ4#E2QQTBYiA8g_qY+aKw~Y4d#d3FO
zhtqM+{^MHM#BpU3NaMNr;V4dUzLOzL;7*<bFp(QWU7EyM{s8Go?ifuqlDTQLUFj4j
zqrApxt}BbCo#9f05oijxl5+g1Tqun^(zu4cfS={8G%`HLDZ`;l=kh6!c%J*l9*gP)
zE|xYmWN_Obg8L%3X*-mcxY_Ly%oVO<FOX((SBHQti@Ww0Os;aVSUbb~Wi>rMb2#4u
z+*Q}O6_f(Z<z#)}Fpuj&5nkuA=R$acORa^;O>W-zaCD2ax_~;L8&*j<fCBFB7?2in
zE^Sa0aU4A<Zgab6R#40}R03GS{kay!9WG=$qPWXhegbJJcc>OW#XYW+c0iPI&o(2_
zaxTII_Z3{9{h+So7Saxi``j8z)jZ(bXrDzD_i-&OA98Y)<Y$@<&7%>|W3F8+OslzD
zR+!ds=@|&-373!nPfxiCZJ?{=5^3h}jB~yPzt6c+>e(0Epyz<U<R;N@<Q3Nzdv`HW
z8tr?bPc!>pThJ6g{^Ul;4)LSjAb5ZNyDT(5fOo4z5y+>}1MM(hBccsKyyqcM2J?Rp
zh3*LNyBMK_@SA9v>nPvlEFuc!pU}K6jK4h(ML1u!6h#CdIS=q-{8+l}BKZ;Y7?0xD
z+3A*!=5uL-&v9N)&w@DqEG<dK^QWCrJHc1Zhe-mzzAgMF@`Dbcmc$2p!r@8YJOMPx
z{0>?OI>qm!oA@+ecmcvQd~13lr0_3l5Me66n}!H!ygv<M&hq}hBc^lwwP+gur}N4J
z;Lr2z`=YqOE9l9e!QVIr(~G?4NEDa&=_v^2GXMTFI_L_&={>kJ`OdT)mBp)10(X`F
zONK7V=5;4vlEXiv$Lcj+Hx#&Beql5$^Z04Bd*M1?atVRn;HM$OhD(n39)REM7T;|K
zBF*R5Z2(&V|A8_Pg?t-YSj9+{GHJK@P+FuZ=C3t}WeI<CF+APj<x3FEUB3Ak2ut}7
z-e}T2ejqipjE|)uMmev(1j`D3AT7OA@_2pW8smE+;bNCR<Ok3L;t?M}ImXBQ-4Os*
z^YMwGso}TK6#EIUqU-M|FHowZmS0qc+B5!AOPD<8yLJZd1wVv#qP^q;>j8Mh|9B2f
zdd+YA3&J;i67A}F%dam1?j1jfUY_sy4HF@>f8Ya}gS3vXrL7|$`8P^*Vm&{@fG8UH
zoCVN*;vK$4mo)OmEZ{%$E3lyk^T8#v;C`!6fZbe}7H;<ksk0Cm3E?(DpsD$GVckAh
z?hty?2xO<waSB*=2~kI2=^`v1g6?u1BMd$YQ#WDtV|dyv*lDkcyCDA!N)I7$HynBj
zy=g~<m(cGZ@ZLg4T1?v`FeiZX5e|)mrLU0d`}Kfk_8lkS=#UUM3U2*{YlIFEe%63F
zP{?pcaahQvS6PrSfi@il3*#L@azwbW9JLU^<1o063a?CH2^BtGhAvDn4nq6Fg|P1s
zLxdpz7rJA@v@xhf3h}-OB}zC&1NCU3(%uOH#t3{LRAYs?G>ttj^rM?8PT*-zTD-72
z4z&})T-rXJAhe}vN}{lV1};g$>JrpW3Y|xymMoMG1N@XA;o$zXuz{v?X9SOzh%iMc
zT?S#QFmOCL(*)U32+s<NXnIth6NFTlrVHJxp*$}n(tPZKux$=VGXyW1z+Dt7_9Kc*
zLMf${FAGCA!_yVPH3~6h3UfZ7$P!u}KrmN@p~q0m77kkAB1hQz7d+$%B3)|Ng>jTr
zzaez}75#KmSdqlzX1XQx?+4R-VWJ713WQYJ;a(`*NkTA1LZurV-WD`U2#ba0^@yTG
z_<9J0cZ8qvQQQ^2(Lh)#Or^=)J)ut~+EONrp_xIsFzXc>Q6coAokx{IoEvoag)h|3
z2ZHB6bTd^6`)I}Xp`dHZjtEy?fabAKLA!RUg-Ho$XpJzp1!$fKdnwiaRQNapY_-Dp
zb!gKwp`M0c&xOhJQF|ej&qMK2_!)a3Fx~#e8!WGd?R9{^5u&@m@~v=~?w5B0D}u%T
zURc%}?mq}NS^=sPno;;41sy$X>xDV9foKq}UWD$G@Dt^K8ikp(`tVuUJr=FUlzaqq
zTg57J;Uu<kLq9o-yJ(KMP3%HX*X`m@38?K5Jt-T$Q>+ew-(6x0T8nnEi<2(`;VM?r
z!k4?4um}hbvDZY@JjH(~-?c|{qXCnTm@p20eZ@a%NnyX(iY_QWvDXB|dqA8-zo@^c
z{)Em85dS*_K%hA0UlhS&&js*sM9kj>hauv#-_Su};*lKG!bN-aGXNvROG@~S5?9f~
zBU+TkK^P-;qoG}_XrNTuagn7gW1KjLW(D!$gk%JBLgeTdNf6u4L7<7^ufecP68{PT
z%Smwrt(GK<ODTVIN*qd=`qN@o7yxI)m9Z#N#F2KoV^hU{Uc*zG_#^E)IxA`tQ9CCd
zeu%i!#lS}}IWLBcM+aXJ+gV_eAxcA_yC}Z-9)2&0J8h_47N`7z2(O4|jv<OnaZ?ZU
zOqQsmWxK25#vkB5Tl|eOaXI4dzTmtjrWD(u%oWpbfjdt;MFX|#qJ(az8{+A;2r*yu
z{2sLe@%$(hg`#{VxQj%CD?Hs61A2m{SnT;84J{FuE(ZLL7)?`@yJD3YCZ(c3&3EpJ
z*Xf;9CJy`nK)JZ!9^7KF*inl6uTspZ0ph;6i54Fph~sF{vr6pV6TpY!pZ!4kNc<20
zw#VXVTG*%-t7&6hjd(KvfG1+NJs^E5w&$R$6`uzn!e`<fJcs1Z#Vvloy%3$tA$%$N
zP~P^H_(L&-uf+(wHSO{@;*SP6d@JVB)%{M4qxaT((S027AH?+S(A9~S4v6rhC|`q4
ztQQk#PShZ_pbg}o#5y178pZRJ)cGu~_zL~>MI1=$Ia`&w8-P10%R2+$taPl0ZijM0
zJ%l@zUQgk{zDqfmekT{@xIch!RX!;}q;AT@?%>|7<c9<3uH<Pqm4`BzX4#&~HVT+{
zDYGek>#f}G0rz{9zyAYnA7v&bntYY*W&*HRS@#hv`;-jL?Ds3@(ViPWWiYLx9Z-68
zhued8W&LK*98zu{38}xbN(Fp?^6*^<1C{G&Kz&$wp02AP<+t?e2v%kZaDPOZ(i^{F
zh>}?ZlcUP6G=vCM9-+}qnDRf`RuHb7vl#9pl;UgDjwyF9LlLQbN@?FHWnd#(AFZ_C
zECC`$`H&X+VwKKoL33QWCmc3$%06Qtj92<9L32VmY7;yqC|lD=Hc{D$a`s8eR}4r`
zDc?3n?X>bCt;C#BdcOu|iqhpQid1E8IhvHFy#5bZ&MMc^YU4TO#N!}KS5CCkCa?3#
zFH6yh7nE%RfzMDj(E7?n<v>s9E-CYRz{O?d*iay@D3A0+k*Rd=3P6^!^b~Ygm7{4K
zm8~qLJzhD=Ue~~KP1%a5bCs>9!!l1<p@94A%2=8L-cbIq8&TX;E>hF`@0POjViftx
zojwS-Kv}&X_(G-q6HJSg6=~4jR<5P@U$L_DKsYQ>`mTk^9i?|BNbf4+Mx!WGW``i`
za%E8&EGv`^zoK}c977*5RVl4)p?j$8MGv-Wr8*kI8fEiPc}Ltp%3tZ__Dq?*77m{)
ze>wx;3#A*az`j<>CcxnvWv1_qVa@E{(fGDrIgHlu8kGBH!~T;}Z2)JZQY!`LXXShv
zTYXXPmcidvl_zC(om3moq2{bQM>p{{Rli6$*sk*W8t@$|H|m0&s!udb*rihS1DT7e
zc>(&zRdwJQINekaK0voy)x%C3!rWCl+SKo%QdT1hPgVcsz<a5>O#z#?>NGtU_o%vH
z_$&8O`Bwnot6I?=CVN#`w4k(4HJ!eV+OKk71r|Tm^)S>9sKWZ7IH+3x6g_!JC8Mpc
z{;ChhU=pC(XhRXGS{#a{75QP+oel^wNG15A7OZN27%e=anzseO5LGEH@g7yBP_jEz
zRYPB!gsFOU1$VfrhH~u@s@}A@?U?H0eFPe*@}v!nQL3DyXm7OYKibm~qski(K&<Le
zFX)b|+E9uzPSvHDM*az^-epiGsv_y}nxtAZ77kCTcGI?})2cJ{-aDh(9}l(^)nFBX
zsj5w<V40@6eG%MeRVQ0OcTRPU^8e|ojt1b)s}%o$^MdMCBLEqy?DmNMqN=9|_m@-(
z@^@J^Z#R7vc15+47Fse@Y+vBBRG%VITvaWl#prBRZ`x^;qk8=bz-y{IR(Q%)mD5sA
zo(eNET>q-XX<)mdGDM?iZmL4tA*NfZzO?NqUu7JOqCk}x16`r2<A1O$QpG#rN4u>$
z7z!49u}V#Sc~{kK8MsST7wEdWr`k`eV`VB=DTL*!J3qs;LS@cC@jx|(Zu=^gswoMp
zT5t($&sB|oqY*Du8JTeZQnij=Sg%x(#b9}@dUPI~Z&a&jXUSWYBdtZgQ+Yo^AHKJ%
zCVhied{FIQg(&J&MYJ06QFV?|DD|r5f1}o*YESc~Pb%X|6pgBW15kWcO)rJ+i^}mm
z+;3Gkr^lO<x_B!*IjhYh5X?5UH|0dPt2bFt>`<Tk9m1XJeUnh^QcrS2%UskgOj6)o
z)zfK9iJQ9Z8c5yM3tNH4L*3}>G^&|>*)UN1s4Hl#%2ypko4xj`Urt02`_x}ko?yRv
zksL5T_0(RVKA`rZwWfpWK7T-XNZo?I0P$BZ`wA=p>LBXEK(#k*EIF(m$bvISy=V>s
z3|70-7Z^v>rx?^i)Tzfnc2wQV{uL0R>Tnvcg{jw!1tMJSHXH#)szust8Kquz7`15i
zyi&vzqkh#4Cb8<x1^|w$-&4XlPVIC6wRrVC515=#A3THBCaBX}B8o)yq_L<asV97a
z$w~G4YDAH&*3*0Ll=^8GJMgE~E!v@aMqNY8QYq@@H2qIiUvq%pH1(E9;LoZf=skH(
z%~;_+U7f!Zop4^=Ncn~fYVZE=o1qS%&sZ<2$DBp&lKRFGIJ~Ux=?VB1bqksSW~!xk
z&}&)h6<^@?s(Nu4?S9HuzvvD`j`}TKve(o{CZXB6>Rq%Zm#4n(3)1WA?s_0@sQ+OR
z(@pjH7+Bs?SFJ;!`RWcMAS_Vd-vwczx`K9_6sZfdfxE4qPTQr5)z@jqz#a9FO^D*I
z`XTLwDpe<8r-5C5Pu&-vUdYSTQIrEOSEqGG+!gA-DREn=&i@h3zOOE#`S%0$WO7)g
z_Ir!kL-lc*$39lGk#Jb8?qr3qMtx^E08iAj-h$<+x{%()wdz@vS$L*Sp(NvT^$)ZM
z`h_~A6X5oj>LN<&zEY2-u6eEQ-U#43^`>PoeXrgYh2n!cs06w?^;>7e{ZT!Kb_CR`
z+tGfs26goqg#Af<xIb`>>g^sN{j7HR6|MiGz8isJtEMOQ+BS_NeXF%yljwk$c4!V|
z!|hJHX7OhLcWE}eg2qJ?;)j~6ric>NZkoU6piR3qc>+w`H4RTe<Doec1rtw=4~;?h
zXjblriH`<b+Hn79j;=;bdo@=};bNaA#)@X|*QjZ&)=!g7LpyBN_z6)Q)aXM|9Mag&
z(IeDfGq?e40h&aA_zl#=ZGpqXngdVZFi2D61Yodc+yeMLq8Ukj5u!OxgU_Ry0klai
zR1-uOOPFTqbC`r{dbWc}gk~0f1AI)gbO*>HHJiVKWt2uuyB4E0!PG%9n&<XW@Efa9
z9D>bpjR$p9oaW#6po!OHc)-O8P4@;wnxHA56^}&C=mUs1Nz>smgeNs-5yE7Rbq@fi
zG)w97IIY>?1NUb%J~P0XqVXMr&{F?DrgNHndX}VXde?*cyyo99T6wsjX}u8D3{52s
z@h)mEb^*;L&90r`zO1=37@n?Za*S}1rBVC}wyT;8oe)K~W*|K!b2Ja0pmt3Yatyd!
z&3l@-T-S6Nh1v~Gp$j_Urly!yqi<;%6d=pj?4S%sfu{8+n$F+Wj7)^zV$Gf&h@wO@
zrUUSIG(B4YaaXhCCzzIMP7XtV-P4SsZ<)(9h22q<YZlT{R)uEeTm)LF=|c-%_cg1|
z0PsMws0w6Nnr)9k{ZP}Bwun5^ET;$mV@)S|PE~74Hi)?YYBVA}ou6o`={J0;S@0BX
zs@1%)0RK!g<t~cnnpIc}l)upE=rf|1nhTT)f2ApViJ0DNhD#942hCTM_^Q)nJc00|
zW-4`1y{4!I$Qm@kloS4>8JrCdjT&|@be}cT=|fig7fm!Fwrbb=BQ_`Pe{G<2*0#O?
z<u+|=x{$YPJ3oMMm$sh1IC0T>r2*iobzF?XO?#EbnY*>zM?~nZjij-IhxYqw2tBnE
zXQJ@ZzM;3SkGASZ1mmk!Q7U||_R=l1WuIL;lGd>HYsXL$+fTc)6G#teH@Ah&LG2s5
zDGzD)Oa`gH))5;y<N?~EY7~LmuPI9(to@dj4320Aau9}SpGE+1RD1IgYN6VcBotxV
z-t+-=xc2f|G$}$`L>Y=>+R`BSi`3e^9|0ewEq@PbwD#;<wBoq-68?;aJWe}?K68!N
zsz<}*g!VNh&=RzR=&_Zk{r(F)C22>}+Q>=mj}sAZvUX7bEKg~d_J+x6?al;*eMbAx
z3Az+*Foz;l%T$0mO}lC|VoKMxYD<f4=e4SIbnpf3EZSy}q3unpFc-BI4sd@-JI1%i
zc%ywIZS>C8J`~|ENBf8tXs&6S(Y=+c4Z9Cvo;HSt$=9`>89?9A9;c<No7$xDaCA%i
zFU_j+wU=^WS)fgM1!1AKPcXtQ)~=lcK#8{MCQR;V6KE0gt~T8f@KWsoO0M41cCgc$
zS(#RJ0HR!bokz<mv;j0dt<)ybI?sJAUR${EwORC$<0EY^x?dk_r)2<FtxZh_phi2s
zHFQt3OX9%&RBMr;NwwO=`{D4Jc5paq&$TaFp$lGUhtPiJm)b*f!TCztTS;k$*IMQ-
z;(nv;y#(BEwWDa@^g$azsmwa<JzC2Ds69g4Z0fa9@nCDvI!Yn@r0sPPwMOk2dU=1=
zz8DG@U$i?TQFGSyp^I~yE@nMUw(DAv`yIM&G=<x#>qs;8UAm}Ue0N;<I^`oMU3D?t
zP`K&TG<4amn@qV+cU@pEgdVyw1~qTpBHx!2jP~2K^uJdZKMs!e>HMd{V!zId*24XC
z-QyA20iF3A><{WT(zSU=_Z<y&{B;`&U~*X3=OdaDq;r1@T(E8~<xGy~Mpi%<qPtm%
zAM&WKn&wxbx);>1VY-_%;0o92Xp2CEZl?VUNRR23Jw^XS>h9ABBt|#xBuHa*X?Gz!
zuJfhWN1QIh8{F}_XY@)uq2mt1MS`xy9Iz$odeibnk}fG2zr-os_b$+#);T&tct+QK
zGFVb{*X{wHs=Jj9VVZ9CE!58HRz1T9Qu1@UYc!-x*A2)7_j%p&g(xoQwmHBiLl@OF
zQ`V)71kDxQ>ns$Ry6H4O%hJv328UO5o?B34>(=jtE=Tu@R_LzjhJ20Ca&_Z>gu^_Y
zwmF(~UALtlgg10OzQ9AiE;yZb)fMPoN1+o6b+X6klOmn16>7J2AKSsESl7-B(h{9F
z{Z)fII=dU#?&^$lVN$BwJRX31x;wi;TBb7_;i6KPr$I3Hb$e)~?SXDJ&8Vt$4=5k<
zP*;`<_#>TN3&3ODp{8ehwXO|quc^^R*F##XJ2wtp@=W&+&5)k!F3>RSg)X`yOkV2J
zX(;+i*Z2cyUhC48=(RVxSMC73)%`|u&Ud=yR_NaAx?O<754vacO?|!Y5GB7GbQ^y|
z&wSFwI0M(Hv#f{C{#n<BhHqbVgPwqUtDdDdjFY~o20~}OhJM&>`pHw#rtSI~+O)Dm
z?=l6JuKKW<z`N-W&@TJk`afx^?XJIG0KXpk$d!P5>N`?H_vou>PVb|?NC^pF{lkth
z*{k<^jwtro^|n<g_v?+cmC{cy=>xU{`j?AfdQhL)1^7dHm+A29ub-BSE)CEZ<)aAH
zzoS2haaiBsSA-U%cc<K8u->00l1KC{%fK0;|B607I;u}$@DqmW8}d*K)6b#Yd$@i9
zjRhn0_Q*7p$Mo%KCqtw@;tGIK`sLR^8m&J=DfJjVLkk$OdMgbgkL#z=6g^HqopuJq
z>-UaCXeabNC{LcCPdkqyQQw_5<t6EVr6J)-{TdbE$$Bk4QBLWfRG>+x_04F$e@5?b
z_eI<(`Y<OnJ5}F|w(+IuBNebYtM5sZsdM@Roxzr_pGdQ>^ZG=}qh8Q&m<dlAdY>UM
zxv0;G1otJqHVBQltS_b<{1v@?BB(R<4n0xJ($8NB>Z|&GtpLx~|Mw37Ir>MJDEn|t
zKZqVCx%%coXm6hW@3Ek{u5U-r(;IpTt$f_n_fn(xZs|kYf+k;oZwhn;`epA>6zUTw
z^;x9ve+anS`tBwOi}kL7z?JCxokZ=9{?|yr@9G_C!MapGiazMSr(Y=%asQR+d%lNF
zx!!UJ?kn_Dt|ORAeK)$u@9PUo0DPc7@I6eb^rjaeeW)+$2;C$7qk{lE)=Oyr#}j=I
z+GqY$A4{K!)arNNM@-N3YnP&UuCHze-3xsZZ7_bRpLq(cex<*Ubdp{ETK~5r+Vn=h
zLj$(A`r(J+;+;Mt1rFcqWp${1(EmhRgX{Fa(Jt<f`c`w`uwMVf3v3N~E4`*a>4gxO
zH0o{tg8Q>Rwh{0z`XNuy-mQlAD*Sd%hPITKcQ!=RR|VS)77jZ5cEhFr0Ni1iP6NK3
z_^1ZTU51Z6fN(Liy^HW&4QY=+>SpjS0e-i^XC$I<H>7lcrH5e+?SSw!OkWMSm*Ey|
zXz(^nqF&!)SlSPP`WTMVAEWR!-0lY9Uc)*XhwL-#NC$ks-LQd3{R|2kb{;UqP~z;M
zVG>Q-4jH8V(Ix(dU>*?$7)H<&CeYx&0VanH$7wTJkim=Q0l|i3de9s(Omzex#8Byt
z+EGKnB~XVN+5`h0X4ta=-5hT4JB(U{K}}zF95dK|XaRhrq0hG{q6{}K0UvD$p<6Y^
z(27>eVhtmEBedg&3$$7sXZWcBx_HB8>fjTG)TszG!7!CpMiUL2|3Y6R89eB(<eW4x
ztx+T!{I3Ci$`DSgrl$=BHq_1-)*eE~rWhLR&wx)gygmo+G=okFnzM%U8UW83a_do~
z8_v?M$Mc4NE&y@SaPk2Fmkg_E``l&2NgA_XF*LgaT&AJTFoc$6m_hIItA?)Oz-1ez
zbD+*Kl&pu}YlZ|$hvpiFZUl9nVMPmipkFu4&p`Et;WKR!yJ=WS9~ay*9Hz-~zF`Dq
zt_lp*^cQmq4em1lC^B%ZP`hm?oCK3%L;D^uDKS*7LG6y=aXo5x4U=voic&+LQ6Rf#
zm`p2EWrpjuh_~F(Z#-%hhMj-o?;pr34MCGoy>IwJlY|F`PA1^13=+zMJTwH(f~QA@
zyy@V6Y^ZJr(rQCEtzg#}zR;xgiQ$hQfO~2fMO(va4fklD!ZSmHA8OAHuV}XU!f-hj
zQM@$7ID-0>p@LSTUmGst`x4*RGg{hTc1FF<5ZfBXM?)A*sOt^K+QPQMP^d!j$*?UP
zAvPM;j)KW&!}l~W|6;h^fZA5$SJx4#lX0B`Tsa%po&jK+alk&9Y&T9j1>6qfxj$gC
z)A-p9CcBKiX!_-1ym1`iyBc@ddw|BxxS#fE>^3&$!@aw4Mi<a{7*mg<@HDQWC##o{
z8H2*x=t6_LJ;u?r-NMIsU@T00jgK~gZLcx>BXs+WH<qH<Z#+T!JN=CA^k6+;T>d*O
z4;mlrM1KVsPtbEN(AcxN9m>PTG`dcLjIBLT3pOrkjgCHIEDDD(#JKtuxQ`kGHz2}L
zW7`dgBFuP}2Y0w}+c-oKVRWNB!ZBlBGx&`(&i)IyD5E!RqmMSWr6rRX<2afw#u{~d
zL4DjfBNeqc<J(G_-^Lqb>BW1(IE0#=VBEM2E)tDPDIuF=RMYVFq_Kh)qmqqN;}Fa#
z<21_ppEl;~LUG3Uts^W`jCp$KQjHZ^XknVMR*vGVF;hTs&iLmY6zRq_wD^49IP4b`
z7mNv?=^3113^BpQMdK)Euw63#@fN0+jcw^Ebj8@C2SUp<N^L-78Jh>=_ql3(@D8<X
z<3n%Ya*UOS(57p~PV_ZXu5lABqvjcX=7Ht9G58O#+%Sg4qPS`7>WmJ$WjsIwvV7yD
zTd=ej80%Z1X@$nP%jo<fqc#i5+s1e-Cd!MA7*68uGWyb-`;IYmHiEfpjHl0|OO4T#
zV!UTeqpPgUnB|Yq%8ki1dap3ns^PxUSpEpQ`^KLxqj+Ep2}7V&#x0akdT3lZ9hQ&m
z#xWWI9~+C$BDQK{X&#g{Mprkucw!8qLC8~MU-|^C)|f_r+~}F{To(YI8|!Ld`NCL0
zTWwz&y`F;mm9ZPGI=?p7(Ix-h*l`S6_QCkoP{8ZZU9kLU%sB;Jz43K5EE|mW89re9
zWXv1{hmFRV4yb)L-q!)~#W=Scevz%Fg@tI0lPT^G)SOMNX{5c)w9ON>?WS34;9`gA
zFlAVFn!H>A-(_0+0>QYL7ED01T}^L|DBMg9ml5x7)9}mCxtm@MhI<dwUrm35$I~>f
z6jd+NM|yaBo9<CCdrbbc%Hm^kp;wQuDU)`1>@^KJ2;Dx@UpL`?zo|n63O`c>EjJ%9
zb)E@N2Tdm^gLcSt(*reslZ7ts0F%ZBvOv=WN*o+EIV8a($aJEZ@=L*{-(8?QV*2|C
z*g{Osbdwx4^`{(psOdG$;KNLR(%zMD(|~KRj4)+IKzPh_s0K8VrbS=DQ<Ui*y;q`5
zPa<FvWAdL4mRQqz8u}eKy{<wLXIe(TWV}h<6~zfts~vRzC73!mz;B{y;Uq|tOlcCB
zo-}1rq9xg+qyfVzQ#pM$dD;}w9VTZ?@4BEBDW+e4Mog)un)NVAGX)O>;H+uO?|`2(
zEg_S1)4)^!&YRkHKxh|CL)Ji-VREF87%!UebujL~OQr$?XfB&rdP!a}CCxx%GEGBg
z!Y0d<N7?PGrVdB(8)Ta{A4U{8ruH2`bIp_%06?zk-!9<JGfkkW({<D8iRhUdCfCE@
zylI*>48mI`N6Px-n>?35SYX-}1Cv5ijRZP-u_<5=Je8Q9Q9}8SDNaPdcTN3@pe!}5
zc7^+UrYW-_EHnAh?4jKBFI`s^rnSEVS83`%LxcOK!T%zr2d3eaW3Muup#4z~O_{VQ
z^O5PqVBj8`{<{QSwW*P)YfOIlvlj9vc9V&&^{1xAuCS>!wLb~qGgIAkust^&r5Wc7
zQxJWA_|o(u9Eew@a9YEDZ5l|k=QpMmUl7Gx)0GKed1rcO1N^<om;m?()8!!O>P-G$
z0RL#3fQ@(ZdecIB4>gz`9YollOm-Jqf^Rg<pv(HRDS91%Urc*xqOjHc*n*mqdEzj%
z*V%k^EoioxlML{?-JJgpx*g`<&cW|a^BM&_?J`@b5iaKT55etfuBER^+{`y<v1Yfq
zidHS$%};1%?O_h0jR&6Q(RTW(#LFz-0vm60=m!*g%x^Nl=3_R{i^SJFXgy5!nwwL$
zVW0WqUI_P_ca?+N&+Kys?hlv;g`;-RybzOG`5|+sGMM<ACsWcOz<jVfJO!Ga=qY>H
z{B$Qg1exEwK`q$)YZBdmN6cMlmKI|6Z_3V@+tkA*)cl3+sxWiHTNL5uD_!9t!W`8I
z(qrZWA&4o`Jcu4iQD%h=Ceh~cBT<VnzyBHyjWyp~4bJ0ccOr{3zgY-Cyg7m9@F&bp
zX)sAJH%w))vo+DYHVV=tbN$yaJ!!7njD{wg-@S&-DRWOsD5sc<W}`?oJ5g3W&D{Ss
zbZ5=IC`W(J{6R#KZeB+}+Ie#tjlwUO7y6dWYi2)5AA(*n`^Cb0rdce2MV2|{G2*;x
z-rEwjY;%A7=_+}Sc{IH!ubEfOKrPo?G7iD#nKNk5$#wItKs5S>Ie9r^xM{xsH*~km
z?P))4zIna{?h4G+e?wPjZbiHPip(9Z19#hO9bE;sVsj>aP*h?LJOIQU^K+V2-8Bz#
zgRa!<nugHsnFD>{qRc$JC4lATZJD5{FbDpMeyKEfT<DuJ|10~W&8R&xzont=WAkO2
z1y-BS{S3|;^G|=E_Qc$hW`R%5-_U-<TC;^i@ytAnw);IdkEeX@3v)JYjCg5Iehq)G
z%zdf>cy0dPhOT&H&Z9ZqTXWP+aK1B#(gWeWS>GPvelTa->D^FgUO?NXKbj|H!C}3*
zfVNOIm~}Vd;*&Yr2<}Gn_EOM%HY@kS<coO?EyrxNSpR~~$&y1;4`<7d&*6TX#b88j
zyQNeO-407KjTv@Y^wR;@WvM$0M=q8n1#s_b`E5RZ1L|h!o`8UNTVmRvaJRIZ1E7Z`
za0Loa%LJOocv+He0pV>KbO+pfEPvKR=VKX7qcLAgFPcm4wY02(`+XK`1%&%8-@ic3
z&obW;9u8Q(9|ZV8OG`@I1Xx@H(TG4xH$81^I&68}6^J0q<EMx;*m9okz9W{tQNV{-
z{-G^cM=hEK@EdCBLJ#gROJo-m;g<3Ar!yif5%gKnG0R6gx;xVHGmYe<EL&B8M_azR
z4Tmw7t_pNstmRw!10KgMTWH-j&hl@b1aFFX%fEWioUnXFpKm2ty3ms|(c<odfRilQ
zJ5ijp*i(T>w)8Co{*)zJ4o{~oul|PajO7B2M^Y@~X$qZcc|8*D(=3<0U~<-CYXRzW
z7GDOnbW3m}OwL<A(@^w+WyfSVvS(Nx(gx;>ma!WFykv=?r_^POZ33Eo#j@sG_|3Eg
z#zU87>F<TwRm+T3V9U0Y(WlQjmWi~v<(lPIIB>a^Ym|%6vuxN7?(3FPN@(4%IMPb(
zP0M`xI~BJqU1>cr-!kEAcqp)2F7Ai2(DFwv5JeV0dLZ4ly!3%hu_ZYL4ofU|=mWqz
z7FU}2+_ii=2QEr2QJDbTvrIb<c$wvO2;7%j`p{<w6_%VAh^f*twFYGOEseCn`+?=}
zH~^|Fm+3+D(2|}5-6M;=VLr;omZe!xR$FSv!bOecvj7)QEQPfIKD8W*25GJ3(|G`&
zSvGWor{|VVVbHy>xI3fv(h`3keeue2pYEU6mRJ1|?;DGimc8CuLO-Fq-&ua3h3)s2
z2njrVumlZ9gmsqH_L=be(ejw~1Jqmo><L7JrHYnSK3n)-QTt*Uyc90BTC-Zfg_Bj5
z0KBucbQmJsX6;UM_U+ai4$$qeZl)~PPHQA(_;*?5D<O2To}%?1SL;RE_2*{oe-$RX
ztsP&%pSyK#1tljutWzzp@wE1&l#-XV>j1d$wzi>7mV2z#l=Skk+P+15eXYeb%Ghfi
zd;qn5)^wVg?zjG|Koovf6|HC-uvXE4;Gi|B0JuZebzh^|{?-xnKn<|!1aJmg(`jeL
zVXME5z5xxg)|SFF*m`snfJdy#EYO5lD`~cT)cPImvI@2CT!A9Y8qyvn;nwq^z(-ia
zx}rE{eL5QONb3<j08!TCs}NJPbqzhWVyr*Opo_Jxq3P3cYXxPp;;c>rVv4t}!d_Op
z{Dd`e4S)&O?!k~IT9cg6QAyTsdm@UH)?C^@k!;N#i11HYgXf~5r>(Ys!FI-KYlNp1
z>!RVPrCK{3K#^uWHU`C6YuSAO&RHGyfGph_MybB@)|T|=IWAb|M#E8t^~XF!XuoJJ
zSPmDLtOsc*ec9^eh8AA2O5))@(|U`Rud=Mabpp**D_;or+14y~2y?9cE8yvxb=48D
z<yuRqy?NHRG&s6$4N8W|4eL2i)NWc&DWJP$t*A$L<y(8NgRa2(Iuy7<-_c9k+28uY
z?5?%(I_OKS2}fal&pLGqd{$T$QSee}9sUi1yl>sN3AzVX#RpJSS^Jg)_t1K~1ikvm
z+L9hlkF9q+0I0T}qW58qHG+Z9C)WODs6DktEricnt7;``&#d3kKDy`Dh4$XSzp(yL
z4(^xMleGE&mGwLN<ngt&=K_$vu|`o|;;r>Etwp}G=Fp|_-kK1F;)B&ui(u-k^XR+L
zkJgRlDC(_m)X+6pOKB4P$=b;WMWgj+cR2iP9YKFp;)`{VfZA5uu9fuMcCrOg2G!ZN
zibWLLY)feLzTMWM0l*!$U9>%Xr!62GP1|LA<BQN-Y)MO@bG7|W>-BCnKiZGF+jfkG
zb?&ydbU%C8dUb*)PunwkOM2PrXxZM|)_)y}J+>gat$l39V9MC~+Sbxv%G+zZN_$22
z*-Ss9w%@jEG-&*6D;|OLfNfPXupP9$q5VXMY$xb%cKO@h)65{ic7?w52(-PUS<Ycw
z`vh<Y*`~GwAlT+whuRU_pq0>t*nU|J_eX8tRKi23?OI>T7KGV)({nrA)`I#X!j_W*
zwqv&I)QU)3-6|AOwzU6%h_=054$BxDyBOTDwh9^=9k-38Jxg)6G1C!!ylo48s&T^h
zZXSdQwuyD%OtigQh<KB1al6rnCv9(NYMN|Iq_uJTDO-FYl&5VQb5T8G8&M8rimf$m
zg-f+He+FTiZ5Mq+dDiy(X^@_?EvG$u>9)<ZYaqjxMT>$LZ7Z)L>`S&a6JT=L*6%7z
zuGrRjBA86uf3yIdWqa2HCjZCLb%s@SG+|4ODVk_BMsDxDH#9M^B=JjPVu>lH*;7r?
zB&MntL{LCFhyns49R*a16cwa*5D*aQqEZEvCIa6(`8Ch%&O0-^+_PtQX7*5IbBv;l
z#Wn{DAz5Ozsda*jr8Zx8U@psSR8$RFZd2X_M1{>_$~RTo%%w|MRW{G@;L{D8FG^sy
z+NSAQkQy5nJ;Aj$D;?nBO`AhUAyQ|vEepEqZ7SXcuEEAcNBLVeG0gxp+T8qamuS;Q
z>ER|D>nz%_G}|mNLQRX!iOUdewOK~R(``22Y{BT;ZFH0`>acO8%CtK+jkG84w0VCT
z++CY6O1R&%5o`dtZ&N{KO<gu&*Fd^$R#Jkr$HqVh<zAb(#UOn)>D1S6V|4`gz{bXB
z*Pg}JFNR_Kq0OOED0yTvYYZL@+ia!M#t|E?E&4`n?ia({n9WRjosQdN$S^ODZG^#)
zoUl;{@E3Su^SS~~Pue({z)jgaOHs*bn@#Vc(T;J-6`VaIk;+vLGxqMr>^d-XbS^%^
z*#F-?)RA#<4LY3|Te^Wb%BZJo_%X&Ccj2xxLqZ2*7lwk$5?mQQsSr8N7~GCNH-<OG
za@`pQ`cjJr!=By*o(!EW9Q9&Ez6#EpVcZH4AI6%0!TB<3spQ9x(fA_B2}XVf?L++;
zHm`%6WE5NB=_!Uiy*mOJQ?CLT$f*1tToB{K_drfFqAA!G%vebogAm5&LEu6ev)@JE
z8O92V*Mu`xr^4R|#ux!28M{KkMKNN1;C3{_brxKUVO+9-GqH?M_4GZUIL1He=sd^x
z_`hO1#&fixi)Sd@;9>&fkAI;ik+J+UxORc@9i`SUGUnNVyTp)DP9%x3l+ppojCCE*
zlENtY292o<jttIRW(XQV(ikf#C6dlqa}&xk7)!T9OD1DJQX)RT{j|_JD1cX4jE8lY
zg>1&$OpNV1V>8WL4x^ru1i6f#j$s&ijKjwuna{|gvwHz!5uJq#88$iKiWp_|A}nV7
zHUnG<Bc2wfQid-*cV&#vi!r8hMouIE6%0QmR97-0>9bK)j9lv=I&Uz-D6>?}7+nMt
zH4G;T;?^?a=}EiEP*nj~$KcYdub%M|C6*c(&rzWE79(RBNF!r59R_YQ8tXus7=O{$
zvzd`WiKP~XAC>jBGCpDh-o~(vLt{Im>LJW_Fc$UB2ff2s=nqSsj7>fsKQpb1sGO;r
z(IdiK_AoA<gtA`7UD|E+F&JEM{frzcs(rv<8^8@P&di0ogN#?`Jvqc!a}X*YGIEx{
z>?6i@`Z*6XB=cZkgdw8Bzfs0(H2{n;3O@ih&e-7sEsq&qE^u&yao9>n|0j%h93V5v
zh@j-_6l0k^%uh4+IDptOUyB05p6PZ41`jiTqou%s>9PerIWcP}ns}7iHjchy%wi7!
zoS7S`2Em1Se?OGDGUF)xah#d80ysCOC*=#>nf6rs?7=iGw?f8~dGR?o?8R)S1E4qa
zYdZb<Fe~2y=gS;C0l)p20wf;hoM2k%i|qc)K{|+?Wa{Yba*BC|9?AgbDg~SgWCpws
zgF(z*3M`#w4qOHaW~QHkg%GA!A^@RG)$0J9Vd9n(o{BK$Q(J&I%gnd~d^ofFSBy7;
zxr!F3NG6AthA3v=6(FLSfwXUqVHSkLnONpD9mL|8`Bb)Yj=79Z$mf}LbRv&u{`N0$
z2~1BaO-W?x=mRhpn9u(N3m2JEIw4<To{6R1VG{G&9f&3~57Q^1QkbC>F-&C!?}eJn
z%zLz<OJmNZpJO_+j6N5X!R)4JWG3_45E`#AXSYDxRi>2wFxQx$QPv}i`Q<pcY-ZL6
zuzQ_ZO-or0Q#b*)bD8yYLe68pI|bF&eC9^FUQoa++YL2^%(b)uDq=2q12V<TTzWN?
zFo!7(P|D1vFAkS6|Dc+Ha^}-4;3}9=&M;WXjG+@}71MDoL~byDp+I&ua~qXg)-V(4
zQxdgI2b$)a%*?+aQpeo#D*EcJ%<UAhZ(yF&VDz_`U(ku9k?AV}cboYhg`1j~C31|n
znHf!2M_ZWtXlvif%qs)e#(ZfCq@DRcdPX{!8oDfZhq;tyrjvO)7r6UO$IWQ$V*Wrm
zn{MXp0W|h7-J7AMmubC2cf9+UdGtNKe&%{Al6t@lrY{f-Fl{$ux(AsLcYqsWeh?4D
zL#Cw~B9EABKZ1wD%$P2CIKtdR7u!ae-_eh4j2Y?&^W)6TE7A9uIYJSa3FcBtIXz*<
zV>>iwlKHJaM5dU_tV=P^)6C}`pv{iu+zDdO3Z;0{VV08v#^k`-x)QD(VR7d|w<F6m
z1%MOl%xp9sWwm??kz=fl`5?}$mbYQhh2=vp30GEw1Kd8&nzaVX+*pN`0JyUTP2fCO
zELxvDS>t!9R>X_7u?fC;vx+F(>%)3XxjA2!69dlpvBGIDdV=L9L7zX%pElhmS&eT(
z<P<CKGL#0ewDgk?Wc_>;t_87{d<46vS&3gkbui0%0izFL$>|&y%EBuO4<1W}4APu1
z)<zx0(a*AaBVZ|<wO;~Y1ncOB;38RB&q8+;YrY4}N3-@)c}5J&NGIf2mZ=ox<5>Ol
ziaf{awTJHWtfwe!8qfNZiu)2+AJPdqk+p<sYA&!Ww4_{QdC!8~ORS+$kR(?4f6<X-
z)=Pe{l)^gkA}pn{vWg*knU(hefN8AHDxfBv^$L9`B7-$Tag<CJn=)osSO+OHdX@Dp
zjrSVMYbE-!Sg+DLm(6;SLQ~gSABo{_4(svfXv}4Oz8lK&Sg+CRAfL6Go-Jzu>rfLM
zE@pju8?7ZQ5nbphW&P}l#xhnGU5zPcU9|(gf;C<Qu9DU99Y$ZpIzgL{8>~cM;Hp{A
zUIU<p)zSekYFTg7<9n0U;0Y6TtgD%T*Rx)3!jKwR*Jy`$i`AQszD6S}C>V&_tRLu5
z+QiyMk3}=<g%4q(h2==m?N*j6omAUc^H>;DJ1fd(<Nn3giZ{XBWl8qH`aPD3#(AGr
zN@@Ep*0BQE>t<C_t!WP{`URkSS(8iPU>|Gge%R?}b-#wb2dqdsbPurp%7&IfR`U#y
zAy#4tv^-=L@nPW+%VQyw4YPLafrSy)z;ghMvU04SKxT~f+B48L&hnzKRXk=%XnQ=t
z(oaCm6IPoJ<D6t|rUd^KYgskOG;6?sMmzS^BLLX5Rc8P=%uXJIhYsv`%2XX;C%VC|
zBRe4nB2MfP9{`TBR~R9AjJ=oQQ_k#vH`0N{h5f@Nw7RmZo`&w@Y~O?6+}NAwRqoDS
z_97ZR*xz0S@nmOEgx`z(yFHY8v+o`R@nKtb!LBd+BM~OskKG&u^C#F%nSlGVzia?^
zl6|-n&YWU@=Tr5^Vr#+#<WI95--kpn`(7SkA?%YIK|<N_RF89peVyWPVeIuWFn5++
zbq*edv+bY3gha3d!q6AV{$LCGqS(D0kZAS{3eU!{SFzA{jvW&UbLZJdDg6`AUPG~z
z1a<(W9240R>nwC$V1Gn65H7L}RF`v!eX|$%B=!%p;94?!u`7TnY)^V!rLwcuLF6*K
zoraRe?xPZkboQ&eAd<lz<KYjP$#(e(I<K&sDWH3mE&m51*Vs390++>Zpgl@9`=1u5
zzRvboPjyc@>=<{jx$KZSbmp<|Q$#4A?Mx}~0`_zCS<yoF>vVagi2dR{SSn_lDb`%V
z-u^30l(N6S2tXNoc_u8Cv&Radvw}Ud0k}%`hDpp*75kI*AUD{@YtUHDUPvkX8uoJw
zsqUhdotg#UO}00^HtN_3-@$G@`(0NUY+%3G34^!TU(q?gk^Kt&#BZ~Q4CrfOyR3y|
zGy7k<!`s51{1Bv-eTyzCwXxS-2B4i?`aC@BU|;zIfIDp7R@m)idwl?Z@3P$@>BH#v
z*q3Qrf1mw;R@^T31f8k7*~^k(sfV3>8=}2zgER1b?0rw*VLv-u4ekLup$;Mg>|1(p
zgKSY8hCRd%dKZ9)>=)=$CXd*Ee-4ph_EuVQM%dkMFf_`p#u_<ijQs`Ok+Y7o-=ND|
zkJ<lF)?$KPNHNJL>|r`fO|n;JVH8vBBdNeovu{wk!H#pj7Q~+O2JJ`>bC|!vCkM_|
zKZqRRyhmqZN6uy@hV8^*(wcshvxiD4k8wn_8ai{fQKZg=vmhLBS1YHOR(f~NjdqN}
zgHttvPEXD(SE%vg%#;J@&B>s>kq_qx#j|`liyQ&)<4jS}{s~UXE~xS6w9$F#B&T>Q
zMtF+zC8f>-IME^K3*>}S@p}-bv=JVj=6pW_kzh{Ec5opa>+2D4DwOjo{pQYalIh$W
z#wpzZ?kwl!Q~<*{U%drH1Sf_9$&sArDJ&MnvAu)7XwL5xNRHuf>5H_noS*639LHHr
zG5K?x&2G?gp0m9huEldqi{NhpXCGCBC33!_lAQ~jN7i&Gy~wGW38j}f^TUBp;_P>a
z?qp6AEmJ9+v2`$?${Eu@>19q9{jAeCf&YWs=^U>P=+5BmpvFwjN&3>}70x+IH(cdZ
zy$eg%IJ>$5&*HpBzqxGAH!lEpos-xClEWGLADv)xIq%TcERXXN1p)Fof2Cla3pkwb
zptO+Fco<v}XTlyH7IRM12i8hBum1|Jlru?z)iTcfC1@<?<WLP}1!r|VaFrYj#dxYX
z$@C(=!THz$j#hJI6jrI>eE2LxYB^uMPalTA$=OfKRvm}488Y>p12fRsz<IV4<GsaM
zOgGdUIhzka+ilJ-F3{G**%b_tX3mPwz_oCmti`ZfIkCflw{fy%aIKy5DII`2I7^!W
zzr$Iw3Klv!H{u|2m-C$gs_${$cBEU6_c^!8U>Aow7c$+PIss&QII7Rl*vnDVTe^?4
z`WE~i;B2Ps&LC&SOmIV-H)&=ca^l9J?Gfk0JLntc*n|Q;!r8bH{*H1UFNVk%Cy1h(
z<DB1U5BZoANPE`_&iswAXMMu)y8}AOd6{lUPjNoNsyk<zW2FCHXvbZ%0lMwEC5thN
z!`#!MAP!u&N~k%)4Y~lFBX<Suf1J3id;pGe2k8#LG46bd5<7GIo6+aO^`tPYEB9IY
zj^1%@8l_&`xM6gw)ZNN`KLUPxaJy-~Jh@R6FZ1G#($3PG>qDi~K3uogq0N^YbqEMQ
z?(4MBoZ$XN^;!Ph;%eYda`$P_cZxfMGU)-_MT5Wva;@}e2XPHFq|@AEERbMs_`47Z
z;buOAzEH09<=4QT;g-CG&M@v*G^VrM15_au&Rt2>2oc;Mda*}xx6-l|#eIVk>e1Yv
zX-qL(7pe+~<?i?l9>#G)=}dEuyNABqbe`)?anyM30s28CaPuhapU7QFFZ2uCdMc;6
z$X#Ql+LcS(XDDl!#Py)Vd@?tDA?&7b^8<iS<=%;brOVtVitnXypVq>QbgnZ6&NH~4
zzrj)__d`nLU*VRrA##=bzt_-rjr-CE=*!}Im!mJ6YxxR>u5(xA0-nQl+lg`Ja{msb
zy8Aq?-ATygbN9Z9&I0appMn%}eW~uDi2LU#v=wvruZ8Xs?sz@=O1T?i!Ig2B{|po5
z+yWJ}RB%6j599_n_7AvS%^i6P25Y!8sq&_l`)W9FH@UOv%v#4?{0;i*xgJdVziSQL
z<qRNhao?u1SR;3A7i4a8Z{@>o6PHalc$&F^6eMlo8h?gJD>vs2xZlRrDxtfbyF~$b
z2Y3H+^xffx(bCY#UHuhA?s7M$0C$gjpWa{hxyu(pbr(03c17LX+5U7^?%_Uv2%Wv$
z(c3`uaUam#(SB}wAap<Amj4UH0C)dRcrnQR`Wi%rxKW>>?;*FGuBSfYKBnKrFn1|=
zKf>L+8OlbvwzS<C<2r|c8|Q}piSa(>YSu#a1a}jKJfCncN&v7<a@SLOXNuc73Np>j
z{t?>jc)=8ovge&j06ENCN+rz>yp5DkJ;K}YD>z49=XQAE#4|4h;3)57Df*7_@_&Pe
z&OGlJD0AVxNtIx(ypw6@JI;HDw(M>^8vy|Byf@FmyoZ$+MdxWxUYa9_7w_qB(do@Q
zOjkjDcs19+`SRBPhDq?_9WcR}6FfELz5IDAXbC^b+p`RPr+Bf)01x1urOi?xuX7Xn
zf_VPx!JX!PVh>BfJi!)7hVV3W91i9E(gN-b&l(#KZDG8n6gNK0vl?J9oTqPuOayNc
z1wkTtf74DpiZ|yf8l!nH(Nh(}v&;gC<()hW-Elkt9Wl=Fc2i*eJZ~Y5C7yTv4a`#l
zuZZH+iM;peAbNrK!DIYIl6d*4fG6|zTcd$b;mxlHN#)5NK;|+pXa_pecq8=0rSo*{
zn9B^_Tu<oE<keb0uJF3<fn4R8s5avo?@=PmXYquz8P4WSP<Zw_?>9<@<?u9=0nO!o
zL`VEQ-kZ<ELO$<TI!PAr@}5x4wvgw!2&9O&fU1Ctc?T&EQo^&+siu_o1)Yw|c-uZh
zUpdcdKU}NeIdQ>N@-{AjYgN1&I(y#W+0d<@YF;`IW2xcIroc=sZ_YB9zscKl8h|?9
zdwVhZdfuwr(AmIq@}n%yE#3$PUmAI@(BpKQR}>G@#Cwl6)6Kj9x<KB-d)*h>T6q$R
zP_*%uIl)pp&z%ZbJ9tmM0-x^i7UqL=^1fIN++E&2I#=G~J))%9eIAzyyIs8aeu#AQ
z3NK-TdU$Ja#Ierl<(;AUbsx`h6}0v9-Wvybz^kLDae(&^J?VqIPX?fLh?lhnQ}U3f
zu!HVLyjU4<!@MVB0F3bV#h`DLmmCF4W4!&zushDn{SM?Y??wQ~1dl@{Z%=p^=<?4b
zFN|Vi)+ru;ImSE9Yb%BtJANWvc(mt>%c1Qse>QEx9r)K?0`Lg_VK%&Q<ZrnI;=~`B
zkHH+}m*s*S<2zCE-kC2OhEf;4^$<8$zD^6=aXyPGAKdt(Z$p_o-?R(Pc<?urqS4dJ
z|1khEUVJ^BMZNj+=-ukWfB75ubb`Oj9-Keloz~uye0!>>ImJIz0TTgm2HFDotK$F<
z;<IUQdYWIXgWX{Mb`b^<!uO=iVJLq`4-B5+4^UztjIX4sxU>8%w7`V(t;<Ux6Tx3j
zxsOP`{Cx~9ivJA-<)ZoQgU}tr-x~~(SpMLBsEOk%w}71EC+~tY=lR>HP9~n89F9py
z;5*R1Dv>`;8`cZ_URpaZ^4qA$^b$Y$UEq@VbLawKGT(3nI#c*>S+@X@%6ExI>t#Ok
zX>e)$Mj>>k^DjJtnhbs@C9E^~A5vWC3g3l-msk1wsPP)V=qKQ^_`mc(TQ=XGigB;=
zKQY3Y9KP&DxR%S`PqDc?e$HK}&gVOP1+IV}@dHE(`KJ>oR#n8;QGBPE|Ktl8Ea4AR
ztgDp2mWoBo_-VBCm-C~KqpyNLn-T++{MOH)t%|QPL-GcH?k^Cj=I^Cj5;gq86pF9q
zbDu@uO}?5oM0Nc31L&*gKTrFF2EKa|%--T3eSyBZ(a2A?gYMh>^K_%SiSJ5_Uo$_B
zqK_?n4n+uC`THGVw~c?|caU~|`YkB!;D09s?hb#&7yzC8opKnw%WrEz-#z}G9yH$P
z`~C&e#plrhteb!BU%1x8-}Et5_wpC+m_1|NoId`{>*(y~FI)@!1HSPk3}%2okqntZ
z{?9+4afly%7-}B!;~v8NBYwkf3}%>Lr~x;|Po&uRIDcM^&w`^2tBXC%Pw}6oH1#xp
z=}izj!RDK=U@v$z1d@jZ&L^SFL9mwA)gyxCDc~FhYr`PoBp7YQU*f1>`w*-j69oVF
zPzm@H!gLWVrU0R<pq2+M#|1Nx37_L8_%R3ocR@eB?mYy7)+A6*K}j3D@DfD2!%=U6
zOCE;gBT&=Q?JJn1_okmfwiMh6K?t3_{RJF~T%8oS7ohKy0AGs5BPQ^oNOz#%hhH&>
zAi=yi^qm&`_&rFlz)GbzA%f?#pe0nW^?z{fjG&~{3SgLE)@-n61^?2|BU}*e0xm+p
zrUfce@Ek=6q68Z@0v|2t?1uX>0{k};JYs_2B5-knXK6(`C%AbPjpqfm(HLmFAcnT<
z34#vV5hMz}rp5AtVC@T-wTpu0Na(yIc!l*eY8aCQ>^3-@EU+y=Yl`6Mzu;4<p!_A^
zFALh}wVfvTiBccw0>w}0%MeI6!fvMEs}b~F5!};*Tos%h0^pi}E63zz3BtXd7hBg)
z!CbDO^F8>UCn%tboqU0t5oQVmTdzPzp&*?OLq!7fA0Wkozt2HOiQwWP;7SF5(gvhV
za629Dl?!IkU!_9OL!~E`0@h_Hs}lVB1(e+oJo`3q)q+Zj_tpsH6#&%YkJ|v5n}Px=
zGpG}={>HrA5)68PYZM&a57FBKQwF#uLF|3>H4B*Z#r_sS?k$j3!HsoL(<a#V2@JLi
z&QVcwhrl-qUfdDPm=BRo!Jo9M-4#gaiMl8Fn<ntSpdubRy96h{rp2Ngzc?Uz1gnxT
zgS~=ZUxu1K!SeUvTE8HVChLK~=^ISzfS~+uhzts5E(Cr^aElHO4+Y0*aeO3L?Tx-+
zLGl#(Mg-w)@M%;qhfeHc0>OKju5rPSl)`;1sHXdw6M`B0>1F*y@N+y2P6{@zg)>tE
zKYGti3r6WOqMfk(KJ3~HO>@w9Soqy}Xmb!Us4V!1(4P-AjzWDjI49v`Kgdzxj}+B9
zCj27{0B7MaeYeU*czqUz?JE4@c{qApnEEa_H{n4nN7gy+!a0=Y^$>2F34@+OCPg{D
zgga>e;w^k32BYv1jxj-eg};0O-F`yx-{?CbWGn{2Usz8U7ETInYccv$LN)zC1BCyh
z%KboLjvu%nVG(`V;k2;J7F@9K29;NZ2ur9e!Wt@EJB-#d!uo!&VZyDn9-S2~qSBaf
z;ZqT?8zJm}6N8BqPE#pPl(3u%R-%Qk?*=YLI7D}mV}(Dn;ZvM&4`mw93Aa$y&3WOu
zR#=J`&RhX5L3pwnB8kEhiXL7N%I#q2qE-096cCq$(qs%KNx1i4Ad-b&b0L!=JiQKH
zqzbQ4f%s+N8e3RO6aI7qT&8gSF5s>Rw^E?us<3fAe7Yt~xd2?2FyRKYWD8%Z0J$y<
z{04S&ge$2SI#>83y%+O@34cRbzR+4ozqtb82Yir1;gXL)iiANl>&3!C0q`Zl<Hb-~
zD%?*cL}fx-3VW0bpQE^6g>ZE_yr>lVAA^Z1p=%8My&)W?dfRFt_F#C_gez$?RV%#H
z1cNt)ZM2Nm38UWzu3k87Jq%!ja0?|RZwdEofoP*}>tS@>7QWX4HBG`bG3aX+POyP*
z5e9icq*Z9M1|n_3A<C_{3y;xa(;@t86y%Q3V+bZXg*)ira97x#1266goiYKqFYKpk
z$1Y*_j}Yk=I*KUS)+78M)dcnm!&70RPq_6LDD4*(hQaOw;k+^odq7z6HGqRc&qkOS
z5}Mqh`=L-oOUomnf&zuZ!h&RQBf{`;Xc-mmrFX)ZaP~s<jSCt6;2sO{j|%bN2_2%)
z_(V87i-NV2!r)2ho)TIN=$sb5JBkt7iOMMIX)nqyfce8B|EIt?h<x4wcSMx;96WRs
z{TTt`B)a<Fu2FR1eTW<rIrpK_S+pP<CR{|@X-Zs0(Yt{=F7l?mf}2Rx4dO1khnJ9b
zj)&-T`hv2jXoS{4FHy$N==2tyy#dZg6!$XJ_=^6a4W^&y6F*Gb2~pY{nD7^+QULj+
zD3VS%r$pnI&=??M)AlJ)<Vtryf<@VJnDr3Rs!-rUMfPm;oe_Pp0QSN}*~93wo)!JV
z05Dv1ehVfcLS&&Yv_y)=PCzC~v_2gsqD3b9m_&>y>HsXoik$Po#ffTOgrny~o|7Qw
zMMr7B7B5<o4u2Cwr|&>ZqUZn}>@J8_u7Q?|qTLi&xg`3QA`D3)`?Da)R?&qzAW}pd
z=p3FZ`lS-OFN?m)f^TUe-77$(i`EIDJ41A!7nU+blT<BqMby;<x37x!Q9AFMsOD8z
z$`WxXX^}0uwhyDfE~+~MyE&q7p8%dKx=-8cJkh3;5Xl$4u?@-!MAnf%AyX*I`!6yg
zN}(Tev1q0lx=Td(Fex595i19XGSTo=kaE#K0st#SOKw1Er6`5+X;q>Qdw6j}bhrY2
z)uOz^aHdAIG7KZE71>>d$W0M{8iwjbtGXakFIr*102@TJth1o>mMDb+oQ<OGrQmLh
z{$)V4N%SslFq=hQ+o8KfR38tnRrCVAliNhQD6!Qp+VnL59ij{WRg8#^d<46lqVK8F
z=B{Wnty=d)rDp)YFWTD#K$mC+WjMP<U#^3N9#K#wmD%-*K7Jm$`$U%tA=59qy9q;k
zAbKhflQ1Bv`w5MMqOJQuhD86&0N|nM%@nx*NOVLE6T_nAB9IYLQX%?AMJZIHI3^0A
zAKSQSPZt^=i@y69K23;5=xKZ+inswXDS9iIf<<=XBnn2@i{0OWZ->QeJz?HK{5yrE
zj)<opK-5v}Nykhl@ir=gKPq-<2H==@F`YP^#mgwz<039<f)}ph(sGzTF8+cJt8U^S
zsA|_;Jn<Re9^!ZwCeKsc{~2&z;;K{h{__^Ep&gTtIE#XbzT%EFApFF4Q=sjHxczOY
z@fRP^19(z=i2`7!#J9e~&;rDsZvYS|o<~8DAhG*7XgMwRqWeF=;%dt7g@{Y3dLdMN
zWeNJui2qp+$uMyu#cs}u+iA9~;o_HGh3*LPu2m3?6f1q8G)kPi23)k*mNtqp;wwoQ
zVXXM__wXrB{9`)$&WShCar(UY3FT_y#r;AIJ3-ua8kQ2pyEg%MLA>+^R9_TJH=*y6
zm`7jxND@EwGQ3C@ucz~SidB4;ZpEdF?bNV)Ssb?>y3@qJ{0%kfVjq7XGQ>6%$I2AX
z_!{P~h_9;AcvT$sJtpy*_>)Aa$r8t(LtnP|HvN#Ui{GpTAV+K;4lY;Rp95uiVkbA?
z^2M&Sq!fs^(Q&#^Z2hzhYKp`~XTTPV<#e7d5%08two<VN3nMHOi|Bw?E{>sKQH9uB
z1wf_vd<aZbiI3Mn<c8Qz3Xy7YHl=K8#P?o?vRbi<_Hj4G_Vfd;6K|w{IZ!WNF$aJK
z@u!sl+!6;{^P#O#yhVc6+u{g%3pa^-d*N`ic*SM(wTK)0V7DC{@Ezh{+O^yfzds0k
zr+6m|({)$8&<m3H#PJ&-a$j6bo60V64OJ9&i?>o~XOB254}f0rfB);GPn=zYzJBqT
z4+U!<h(9+%W<VT4*K-ENfwb`)635VILLQ1U>CF2`9HRso7QYw?gCpXH6s#Q;hgsqF
zn0N<;tj5KLRsbH0ch*76gjgB@ktgDSX^ehS{3czWof2n%4As-(_ol(wNe(5=eH#y+
zB;^QnAC~-B3xtED?+tKABytvH93?$kAe<zzuR!ThNrnx$W0J{M^f^m*(W>PlQ9R|d
z+Ha9{0qrx~B~L2R=pjilfp|*x(4o;wB6^H*dP_d=#;|=Pr;b32uOuxU#7|-tVh|@J
z?SEqq{3W$j0GyQYz6Jc0<N>`m10-80F%T$u#slLFlGM_7GEPgrFN3{c$<uV82$4K*
z^+9W><XZt8JtMhHQLQiulh&KFl4W#&4wqQmAQ~ZYpl3Q#@=-8+ijst#fn>DgAsvlk
zByrbaB3AOhhtM4-`Fa*+<ecOQ?c>f%%AL^{FL9($Rf42zHMm4cdI{XVAo=<aIwoF}
z1b>JzU6LH2WMh&f_<J~$EU8X{Op4^SSSU@ENdHFPWyv9`+)9%i83G_(Qr-_PL*lXw
z9%f3STEShBc%4JvRmp}w0ly|`q(oJg<O8~Cku3>b0WG<bl9L#9o}~O2+R5Zg)@4Jq
zKr%lVgDI3)DA!UX*;ERp#gau-icunw7oo3IGLHe*$|Pc35}i{nu~H#Gh2*#h@Jh+w
zjhLA#N$M?_xFPw0en{1lrSl+JBl(@e?zNK838=m)d3QfZouqs-{S%dX$+2<BG)U5O
zq3xC=pMq44l8N8o;%$lJLipVz3FD!!SyJ^OfGv{ShtSt5$)TTYo8)05bhk^cRA8VT
zl6X4L+>yMz0i;vX`7+>lC0~9Aa!>LCMcVF5gtX7@lDu0FV(pfEL#t(vWcdJe_exgp
zKx?05#z)}#CHwSn?SVuX3vB}uKJ85hB^U358<IFzLg_=vS$d~FlBD^;!(j=#1j<Gv
zAEaOqqmmu80~(WL(3W^yBB15*vE(z_=uSvNod9@ZmF(BR(xfDBC6rD{mb?mXT4FXp
z#!i~2f^K`MO9QyW(kXi29HhmYG0-E@P4ohBl$z<7?Iitd0mxA)hxR4Mq*v(Lg0u9_
zI@ooQ>ZmNzRqC4y?znV4WtQEfE8c`Mcj>ODXfx~~okeFuPpPy7oR{=2g$TT*$}ce(
zAE{FZl=@0L=(XS{O~d<d&I##3%BcHG7r4RFNvZf2{vxNO9T`v>AYHo!fI#U?+U*BP
z@hP%Xi>-;Z&>Skwq$^ctq$PC750ftc5#+4&!cp`^N`Lzuuqf#vK2%0af2VvvjP#Wn
z*ol>X#e&yy(x2@ia!%SnY4!8c&*#8EytMTc0148qKLL;^t);c@g7mMiA$d`H?+Qk8
zNg8jZiuWYxKH9`4OO5n0OOb{jg_>090L3OQOY{FmUz+qsiovBz=g{X<GNffxEte@}
zQX>3{G>=yLtI|^1%w3bZP!J?bdUh5_w$$<?$aQJc0B||d2`X;Nl}_cti#+Kzsn41K
zhBbr-T(Q*dAVf-}uC$vfmHt_PX)Tj}UIeaO%A=iOg*5jcI8iBWp-HQfHqoE+hBT7^
z)za(1;A*7LMMJVyx}*m#-IUhTNxx2dBN=|yOO=$cZ;;Mj07JK=w!fgSQTmRx7l_-^
zNIFb4Nu9Y+(=6Rbbs;TMLk}jeRr*5@5N*;x3WBvump4F7ht$s#B6p+~+8%dG-Du-~
zS9-|+_&w>|m*D7qX~;GVw@W(rC~)1<$FzIvk-qgDl=VuN(39LJ-Hm@5j7LgZ^%1;z
zAYF6~odePjR=~ud)Ztr@At_S;@=&^E2Jnxhi#kDurCXl|8Ihi)XJJ&jc_XG|Oj@=T
z%EqO8YN6$^blMlLO-LiDWc`V>o^suj(&Oi0XiD0#0%Tg6x`4`Y?PT2_fVG!hngaf?
ztd*`SImjkn200?jUIyYQn~l=hImcwb--0D)8IO|HF0wsrG`h+bQHJEW?1ecPsGE$V
z1?Mh1MWrepvM%}=d&<5R!-AJ=25kksW$vNid}IM>^w~yV*@D^d%}@5J1C*YSMgIba
z{bgaF0C-aN>z_cJl6|H{V}NW1719REa`u7*$rSf7`qQ$%!=Wu$wsanTNFlP<DMlJ9
zOQOTU8JXKCbcV?swgPZg)}jR$E?Yqv=m?nuT?Dd5%El=#7A1SO9wb_}IUh=6WS&$j
z7%R)815cc+nGRa#WD+0vbY2!hzp{AQz(sHgGMid(i89dv4B~=}{Q!0^%IZ#G)-K7e
zQyM=>CJw}3Bw6-230hKQhp6@<RhAh6_+_h1Gyz1KEdM32>9WBk;4)-uX-}3Z6FP#s
zA`A6|PgiBXQLO8ltdw5iS+bWNLL^%j_6i!W%e-R&&yl^60xnn9P7#JY*)vSw@@18D
zS}c&glnC>MvSO;4Dv}-Yh3aCNb&_I6C9;#BW1yw7gf-|alg;1&Q7*Gy1inJ%)dx$J
zGG7WyRmoDrFi$sRy4PT$T2@HKf;F-kLx9)H%=EguDN`9?sZLgy2VA}ExB~zUviw;v
zbW661?f^8(QYgWCTXxuL1GY)F`~$GfGFSRqM2qaT&p}#cfqVelWSi+_-!A+0bIfyx
zZ22WL-jT_+gX@&_hr;|_*=<`mb5B-6KcsG%YzIVoWUi+m(kn|0hTT3{=Us69vIq4L
zc_3Ta4%~ojr-G7-gR)@SR1L{y(J}F%Z1^DXk7R$j12`;eHG&(F{Y^#vqq4wxn4mG4
z|5KQmaoOHiG3>{(Ee|0wA-hbef+w<<eV}_%_GBplQ?d`}?K3Ugdk@4;9#2Pnd-;!i
z;10|8sOYoB4)QE23OFKvm5#-Z@|}Od87Fxe?RbvL%k9v2OrG=+lsd~lNds|_zs5qJ
ztNhAAcz;|Tid5koH~IZ>^tsFP?qLufa;5<$JmoLZxx-7oo@xrb<!^rmFMQ<16hQWs
z7o4S2o1c73IPfRr-^>HvUtUBBz?1UQaUf2~U$}xX1;{;J;6<R^g*Na(@-4IpJT1R{
z6I`&o=M8Wnatqa*hsw3IYMqhW(=Ev``Sme0o|S)e4qC$HK6Jc{knf`XOQifJ?Ha97
z@=xfFVzm5siWJ1i9~}c1D}PK+N1WW3mf&;pDJmv7FVCS6PQ3i!aoA0e@1RQviE_Vh
z(04&DYJu*H^0)57{3UtW5AZ%o9z$*?%b8NBPLVh71|U^_>@}#qEDx;$Nwdn^X9JNg
zw>$%UhCG?lwVCqyeVDx~@*cVacU69Xfxc_<^3_n2B|k_zfNc3RmC;<6^C^asBfqSJ
z?p%378<geA#a@`hd^v*-ItB9e6zD6IZ*K#<NIvghaHaD825@EaFa7DUD3@QSj{sK4
zvotVYDPMXNCaUBKEXdrD`~C_<wS2QLL~7(Y6jZB~AEi*rP5IKNAW|nEy97t;<*zbf
zutA<O3@x|hxjwOHnATl%HM~V$JrAT+&MJdMoBY~lc-=1F_8ZV0@;*BJ+>!U>!)m8|
zHyuvz%73MLjC=CfccA&cJYp+wUGm&9;JW26((R-k`HCHY_sVC4VhDZm5jsxx%XL&V
z_duTc0pJ7jcI#)LgYtMf;Sb4;V=(bhUPSBDBl#fRvmBO((C=tOKHm)BsQd>?ON_|{
zozOilf13j2kL90{$b>xC4I)qEiBv^ADgR3X)l>4nKgPUF%M)ltuv4h2z}YK)eH!q?
zijfEk%Qz@bQB?MbVrMdj=BViX1wbc-AC);ARrnu(-^UcEE<(4n;#pe%T@-3cdAKUp
z{RZy1!uKD*-4sq#R_LyHZ8nI9;*BD}JryCxV987ICshr2EB>O>p^xG$jm1~7JCwei
z>8BW{i$Nz8T~}b<Ur|gu!jp>EzXCa>c<wy<0u;|ul~SN$aV_vcis$L;k*5_0BjH7`
zqEZGEA&TWxn-Z$n(GKp6;<agrgemsZ>UdV6<-(_MMe1IV2*nHvn?)*O@Yc1?iBi1o
z2$^Wb!IxknMzM-s!m)~PeBol8;_pUqmlPh~fg~wTI$@y63a=JeN>hj)z<j!*kbcw|
zihw;(dQI^Y1tzi-8>nO|TQPVDf0z=*kucaTQykm|k#fcBlnAI${EvRc)=I_O^arX^
z#MAYy8;Z1TKvXNfr}J-(LNp1kRw1P*Se+v0LrB&u3Vbk^4T?fK+}={mq&$D4;y@?t
z-d2260m){?O)pq#QN*QSNUe&3Kuk%SqMlAK?TW3G2)Ltgp(Ui#s<=zr$GZxzW6*X_
zQO5z|zM}jP@Lh@&n!RpCfE^IMiYeL{_bF5q@ak6#o<QFNh4d9P4k+3v`8lZglR}?E
ziUsG<_)w8UKcq(ryEOC-E4rw#e?+0CJ>96{f)<XBDZboDsikoRGXPWiSaEkXxF?FI
z#n3&eSWh|7DaF4X5S><h+zT~!%6GX?W3RkU!2<{7^mVv>L}{}ZgK$)Cp?H~-Qo9%A
zsPceMKm^meBNyXzQ@*qcg6_)BJ#f%NxrZVyUP|_3sPtC0WI&~la>o}?;;URjIdnhe
z_BN0c%H3;W{FL%pDi{t>3hBTQsQig)dxMnh?dUtL6jBjauu@Mi`7_D|l&B0-wkaWU
zR{5Rv6SPJubx*;IC?(f`&S>Ql50E(JpSdu2PPuV6%%4{dP=qK^8B67h7nFYv!O@G#
z5ULPKRxYR7?G)u7BM?bd1}+Adu6(8#L&{Kc>55XOa>+p`yQch|qVriw-rMj#TiG%~
zMMBq=e}%(fj<TNiD7nf5^dX7@<wy(~3zg;P!4)Z&ok3r*@+XSmmnh@uf=Q|J#M5x5
zLRt7CL@Jf#lxwR})&|1h4dwTIn6FlLQ68X1*+ntcI;AaD7t|{UD2m#k{5_c-@Y~9g
zrO?)-{FkmkH!Gh>1lOiqvls^3l}qVl-=Qp{(z!dzH&bDvQ>odBf!<Yaqt|4=@{e#d
zK2WYshsc0(HiZcWl>=06Iiz%=b?u>Y{63UDQkrR>H>{lUM&F1s;Nuy1z(<wyP6I!t
z{B|Ymjw|^l$UIi+Lg4U(GL~|ZPn66ekV$33OqiHbcE1ZUt=wvdMmv@LPcUJxdWXvQ
z535FL1L2_Rp~BE3sy(!TI;vc%VBSf!i_(WjRh!OZNXJxmv<0;~tKvREr;DmF0;6|T
zxzl0zxJudz^KPob<IwG{YWNYvL-h(BL%da@2;hBG&(f;wtNM-7(taw=QIHd=t{U|D
zt3JPgzLP53FJbVMN<vqo0#y5GpLbg2aTSgRt3;Hk2(hY;(xxa>)tZXVGpfJ^5DioP
zkN_{vs@@5Qws6&Z^m>g@1=2GTsrvL8G)AdLHvk{48hr-ijZtOL(-*5c8i7AdoGOmq
zn&(yTEe0T76(0bSpjwm+K%%Ot45}}v{4PS|qRJZHht_1(E5ATZiYkH$E>)Eg4mFom
zQ43%xO_f9k_H@;!l*Y(VbuWj9nX1jSmAs<*D-=_5RVAa}#WmHp3!o)SrJ(z-*(%Gc
zFmYXVik|5lRZ}2Ho~nlOLxn0ig(HhpD(hvaDOSaJL1~GqJq(Cam6ARdQKkxtflRsT
zYyosvsGK&VuTsTZ4N|3gtq$adYGEnh)vAUUL26W=DM4yg$DBZJs?7Ai4H{I-F2I>v
zDjzCBX;f{ac;ao9vKtnfRNHP--mz5`O8c%h)tB^2ZC7z=kJ6#)3jzL)%9l#9J5?{u
z1G%gEgNj1#sVaZRl-^f;OGl$FRm&xiZk4PDjXkRM(;&U7Uv5H6pQ?fu(tcHp5q1Yv
zKXc*CBURLYn{!p&e#(1{sCd`VIjTx30Afrv@dVR7uKN59SbD7bbO-t-R6o*^`$V-i
z2#u2}34O71O0}&BjngU*+GrhCFWd>@pnlO629K!ysNBI(?ML?{ozy;GW1L6ThiYK{
znEGoU=yX=Aam=&MaZ&$DtCy?#Z#k46SG)ZWoSRyk1H7l&jiP2=YR_N*z1783SmC4g
zpvpgAwZRWc{nU*V?l_6kQP@4DeuG}V0cyk7Ac5*vA46G?y7U;h)9P>b!$PQ<)s2Zg
zqi);>FRWqem&#${tU4eY2E)}_nuG|o#uG{-)e9)-9i{d+0uim={U#7G>Q!f;Emoc6
zf$_$vt#s|+l6v0;h$N|b6dF!e-y&R!`YhcENL9aR2W6Mlwp2-xrrw(cT)Mg{8zLE2
zwLcqvXR7a0dE6EC7wbT-s&(|Xzou5ZfXh;MbU-v)T|~cx>*`nkg|-|umji9N>PR=3
z$Wt$NLSw%AF)jTCYBR+u3)R1`g{2~Oz-72rtUgbxdx`qiJJ3?9zOoaNWol93eE`eV
zoShh2h5C~pptMr`yEi(k)V^sTH`K#ECFht{GX<aP)TcSnQm;Oug-Z=;W;zVrQkNt_
zuu=W#IQnj@@BakSq;~uYQ_-w;rv<S^J@puNTGiiEjHpeWc@$o^V=B<sp|-3CcSr3@
z2f0qQoH99g)d5s7a!>u-6Oj9A;}=wq(WTBT2HUN^wE=$is1F<mzE}O%9w7SgTZ2#i
z>i0$99;l5ikQ`7udqQMTow^=&ht%<ON$R1xf`Y$~)HYlIhSe*4vd%BI8tC%bxVond
zU60iYdR!;ff6$J7O8q%qj+<6<=v;JI^YyC`anP*n1UaI4qX)!MbEF+2PMTI)){bgg
zzk{-4nwgZlaMqMPg@L(fnCl?vsu^4Yk>i@+_W^Lz%p%9!H9M_zSn|*W(=OFhvrP_B
zFU_GZLA*5|*I`0^G>Npz_-cOIhVl7p_EGlxq~@Fhd^)8`TZo|qXguN|8K}`m!9<Ye
zIog|_*05%wF<5ivQ;39U*3l^-R3o6wz!^>ZawrSaRDMTC`Lmi}%1VW6{-&HlgeF&k
z&PYuH?OCHV_A)4q)i_dhXPjn~_MGQ5F0`nh*Ep@hDB?BhVTdGX>MgLFsQG3tBrj;{
zsetXGhW8IdE@||1CP>nx7XzNGk$nL!MKdm-?>(ey>ZT!jSu-*M-_kVkRQsQ<IY%>_
zp|Ph>d8X#=o6vnl^8ytTUDeE64}Y&|+UPZzrKuQ1U$&;Z0OY#npf6m@(QGRKE?4u?
zMi|V~uxFt$Uz5KEt`%rjQ}Uruvu8W~2cjZPl0V!p)?{u0zC`n(JIt4AYAJSCrtt^?
zSFZ892ZI%wN;}{yHLD!KRcTUA0(V2>d=c8JHRW_$rbZJqAAnj-W*S6pYM!N?L!D;x
zB9MAb6U8_iG?{d?y`^FO0ejX)%|tbTw>5KTLtB&PJOw$MHR~yg)S~(DHng>BR*!;f
z)9@)G(5_jv9h1<ZS+X3{bw{&zJ48A)Z-0b8+I`K7bkn;_(-#U8-I`Z_0oS9k&Ii}4
z*-P7rKFzC%fcI<aC|Lc#s@c94zyZx-sy-RiFlnnar0H>h!w)t4nb7@6Gx!gH!<zjR
z^%~JUPdT4a4f`;-G0mq{@M&CQTL|wTYy5TrH=$Y93hs&KsR?kCntc@znbK4&hw5p~
zMY@b(r~RI4VC=P`xkoXI!`csm(dwWbTnU3mv^DnN9JL#&;kT34*=OH{#n#Ksu;-#3
zJ_($w*17@YxVB7&LAYsk6mNCcrs*N?q1{S{B~R_IRFUhY-D!aH-r5ax*Ud+3lYmBF
zEqfa{Kdmce-A-srW&!7~&3O+NPHOj&E2p#@D5f8vou*2OK<zqK5L$z@yDvcZY3(5@
z01DPhuY!bV**?6Bi>((ZPkdG@pAU&h?H<~#MQM-I?><@^8x3VK+Ol=vVztk6Arhxm
zP@d|XHuQB!p4V3V4_v(Vnh{zOv`MESnW()&d5sHN$tnOYYS-kV@sf6g(nd+z>FXGD
zvi6PzQ<kEA-%2GUsoKx!t09-Q?|+TXH0>^m=BI0gl#$5Le#L<onc8JhFnC2fBOk!4
z+WG&$?ltW*mod&PZKeVwTl<j*B(H1#q%?Jo_73fca<y+gfMlNbolG?5Ywz_!XMt9A
z5?TtipKPQpZ;`f{qCUmi-!@^kO0=6O1XZd%M+fsVtv9XE<y!sAKvZb8-+`;t+8Cjx
zN;|gz+zsu@cVM?#tET*CjaI@%W386=9LP=WI0X{ww9OX)sMpS;O1lQ_LaK|rr9E|@
zwls~}=c%aZw)TNDOf+fVdJS{Ytkq<Iv}pIzEreF>yY#fTX&W|SFn6>Qw1?`{E<O$u
zceP))!|pw8_8oBdwXe`e5W2L<l=$q{dVdbd9&JqxNU!$iUQ9`!_7%!P^=n5CQBd%K
zHlL~>2DHrgATy|yQlfZB+fPaFhuStuOh3}jqEpMTwuh<!N3=6(4H(tVwg(y0K6(!Z
z$F&DP2YIZ0`VDBA&>lVp?uqssl}1l$na@JYl=d46VoqzzX@6v=Th4<8tG(`{J1~D(
zXPJqiIq0mP0(eBXdO3)rj<X-4PP#uRlyy|sMD?J@bd?n5b=H*xqR&P5mOF5+I%y0V
zkL&io4)boh=vu(tbqTal@X-B3*Ude3XDGqor5n5mpS*Q1C!o>Cs!Pj;jIVB(t|I&C
za@4SNLbrPtwE64w&!F+7PIVaMl&=3R00VS|RK^^r`{6xk3(~ElrRTJ+xC$b{x{1Y5
z8lroSO0dFo@_J}FtJ_8XhU>P`4>3x2m^RhXx>G@rjL}&?;ltr`x;!N&_`L4(nE=M?
zcGD%#RNdr$Sh}p6Ln+HNUGvv4n6BGh3`-fhOsav()FsmS=8BF_Z`7;0_vux5O&3DB
z;4IyvuOOMNn>QDhuIu){4=p*mO;=zjS64<WU!JbrN}I2I-N$qkD$teu0^bUCe&--l
zq+`y7OtJ27A=H%U)>9z6RQJn90LpYPZ-Bva-9q{YXBE1~V`!|@efBhPRl4mIo4=vE
zd>7tV>xQnvnHt@5__58Y)gecOr$YC1EVw#d|0W8c)ayP81EN7^Bf^+&=>!L%v{C0z
z1vs~LarCG)>5OuaW}W^7NQ>@&D`Buz_vlTGsZIAM9TMAh0~|Qop?iyx5O;Ks=-Vls
zx=-l3(p}xILMXeZE213#eO)zeio0}<j`Rh?Zrx-DhTWsPc^XQ4b+!~0@6(-vt8@Bw
zPrRV?fo?l}2xb7&25wO2LuI!^I`u9{KGf}`o#!Lnh5+au)*Ylj^N6lw4wQ}RoZ?_<
zOqcpHxN+V0R7Uq$cl7|Anb6Jtnx4NYohQW*rgepfpxaKrhRRXx^*wc%;KO=}H!L~m
z2QuKy5q&0=pg8K+(y`7-pY}DB9@WpMmH3#xEfIar`T~00x#;`jpv+Z2zXJx3>-VLg
z&rSaf<)7U3-gJcV&`;Cu!0M^*TZK`0=}i<l_trmu9Gs8-trhfC=nE-V>!*LT2*4A1
z&rjinzy1}vd>Eh)q&G*PzLh?l5TxHnY5mjsITYy+)_*`{M<M!tx^5q;zbl5w8NFK<
zbcX5Ik(RUie)>IzTlMdqfu|ArplXmv{Vs0|CQ6_17D%+dEd+=d{h`~?7OOu*v4=Rl
zMujOkr(aC5{qy>?P0$^$pP(O9f_{)9aEbbZF9UEvpOFIYqTWOmjhFPbSKv&N-j}|I
zl&s%V0xm`WOg;Vxb5iwVKAJS9wRHf>GWDKx@VufwG7ibB`Y8&rU(@I3p)pIpf{wk}
zdfrRuyRJ{66jhG?sl8B=tAArN+|AQJ$cC1D{bCC&6zCHs;BKM*z*TTX`bPQ~V6lFb
za+W3f2nuVI>W@?PT$$egzgvIh`XV0K3jN~0Fu+Rvs+TbpReBpe#&Sc?nF%kd^+`K{
zuhE;8Fj%W^rp)+Fy_|{!>hv?-MPt1lAKJk)rC&u$_AUJe%0xEmrFVh5tzSa#mL`2G
ztp&~cVLCpv>6ag{LZ)5+8a{_Gr$hg!3PZc2|IrQjPQ8#SjPB~+-iE$=`lZXD=DvQf
z2>332DAize>*uZmyhm>i0iajEdKy0U>09XU(yw1a$(;xKM5=8Y&`-<;d{Ezg5q(4Y
zO;maEP(M&jAFO$#kBxw~Vg0@tFgT+Bg=$kr^)a+OKGx5d0Y9O?LkFEFde;`Hnbco&
zh2)g}qb``A*3S*aJlPr2?}FGHk^^Aku;IfMz&RKkX_s=ukT3(TIT|ttVb{svdH~9f
z8e;x?7>^lF)3pL;1D6UST@0~wqIWeEe-D}ChB@Id;bxdi6)5h8=J!E73@TFNY1l$R
zMlZuF1!(j(NM47(K87JmlKL8U&jjaZIPHzT6NaV=0Q?Pcv}m0)<WmIjl%Y|MMr(i}
zYz^2z!$kwwAOj-|LpyC~pw~gL!H4#)A%>gu77aD94}d#kh>nBqFvHqXG@doQv<HB2
zL*Hkx8(}E0g|bLP5d+>w8D`U?6>V5W6%R3nuk&C&*04VxB+l^OPE7MTtHH7g?0Lgd
zdfwv=Z?^)UVDO^7cA_CH8Zs9QkrBXOG{_!eo-P@DX-AP{Soaux$%Z#5z?EW{qV!j)
zVR8)c%Z9lW-A*%f(f=PyH>`XcxD10ARib1Xc4oug6~h`&^j$SrU+_R{w&C^*z+X3f
zOckd&23y*@<Ql4<gG`<wv<{Z?4KrIYmj#Babh0lrd`9(TMTSo(R9bAXJpxi<7^HHD
zQiC78J<ALp|3akPFn1Za3d5HSz$*=pR>DG+A>u6z;)dZVE2W;Q4U_b0t}*Of3DH`^
zRoc1TG*one)EWMfVubYuHAS5p4Cy)mZyD^&05lpVzJxQk4SyVj_e}<mB=j{KVyQZ;
z#ju2S;H`#VeK3`6hQ^ryv>O-&@UX*R`w3LvF{mzDf#@{Y90R#)h^Yhcp2127;roWz
z1UTGfm`m~PZbPL4h#o`Z2t;}fKhs94&(L=pq~Fk=1l<n|zQ4lz0mCqz2L=r>d}tXm
z47>#`4-M}w19@byp&aY5L6QpGh+*j*dKr!y?xe%Sn8ArQ!Q+PK&cVcEL+dccG+~Hq
z0`Q699m?BH8nnIWn=*V(yRvD+2UD<QXWUDFUwh*gTD1-v?dU%iIT$yVfjeUCrzh3X
z$hN}ZG2;Oh8l8=Hbg#z6_%^a();X?5S3Atfabs^Il)4#j?gHm-Y^It4597>y06mTS
zsMyQP`1=ZI^EUpaL!*!JCY2ib8V3-jo8xDEg(`AS7~?4l;BPGI203Xw-2=cWWB+|P
z8emk=QWj|3M3?-7jEhddp7pfx#iyV<*tlE_r$UTN|Eokc+EZfljB)jPSPC<KLbZTr
zjoD{_4>x}JJ-7&CAN{-{jRSPAKg#Gr;ml|whw_Cn#w!QV7i)Yv6@78Whk7VGXEe}F
z!t=(6SWIQS@f~{iCs>WYwE~!ET>m_jUN8>*iO!40v~+Nnj2lJ)OfuTihYymC&Qx)c
zVl1Uw0;xtLRUKY7zCm}6(~NJFV=(E)7wAq$hVfa-LuDHMa^U?H<34ZnT{SA&pzNA)
zKOGjbjF)U-KHF$@(L(0B@$ySR<QRLq;Y_Zvf(1mLQMd+!$v1xW0EhzPwY3;bp)n&F
zfFfh+QHT^93#l%k#8`R`BBjQ16_i#O7yegzZ0wAONR=^p1m52;#w>tHwejpBcu`|q
zx(JfB#<BlCr+w2HMTK*9#))S!?0TaE?ExB$<0N{^m`D}*jmDk_uyos4Jr`V)@nJHw
zH5<QL3y~J%&)eZst8w%i`r3>!^c1%neP>}v9Y$6*hIGgH?k%Y9G`c(wLwAiFitpVs
zrWq-|ec$-$C3w?ie3inA-NtY~INW3Gr_V0;8ZT#p>oexeg6@9fN)EhuV055++XKe=
zO27w=tp(^CGH#)8-9zJh?GSln{Dp$5!^WyexHe*3%7rtd#ySd9j~OeE0XJ?uy^6w0
zkB!S3VQIp6=~<Y6VjP<f#H2BSN<5~FRdlADHs;VGWM?XT05$fe7k7g@Y^tN5hl6Qh
z1IQ6m<aaRWX!2G9=VV&_7Q8rW`iEYM$4q<tVZqt7jV>a)m_Dac6j#%_*XSci$4#G5
z{gj(Y>5Wcz6Vnw2JxmT;q14m#)ZZXproD9U+uO8){ysjYLCQM@nx0TJBFL1y43<ut
z=Jdf*u&IPzm?5S;-=Q(o^oj@~XH0MXit&b-;wUwF*0jSFec`56Rp_%um~K)?I@+{u
z4)8H1I}2oDO^d0vBhEC?4AFC@?LUH?HwlL^&+(=YK7*qPrU1%qB%0i5XK}$4`3A^E
z(>E3<y=1DR#w1fUr6`h3KhwJ{#gs^Il~mKlXjr&x3Of%j&1xET1e<Qs(c+h3nw<sF
zOw-0mOvyEq=`I?xOwR~0>}=B`707kd|Bi#?n4Tm+GS`$u_b&2G(*kJ8H=Uz+et~H>
zWmpPLiWkvXWO9ENlUHnV?gFmFbcoJ4rKTUYqOZ)vcDxD`<)*gtFj!%l6NS!7(-4J;
zs!XLmRXK~56|@zuGmUIPTfOOBilQ`_A}RcF%e1fvh8j&TQvB(*=^LK~xr?nf^boe1
zW@{kWW;#|4(r$9w33P{Pg$1xXrfk~wb(-2$Aa_j<n=q1lrtbq_=e{Y0_HA9Jp%)<8
zZF*4+zj{nUy8O^<>Z1dHpXt5?fPT{(^U(Le^yDxs444i+f!RUR57zUL88Y#ysN$h%
zU<X<snO>zjgkjVBbdVh}H7$ZOqo%u5!1mbmR|>qCFkSKld18vKhNVf<7g6A*OwZHh
zm}%3{$KdSEBB}~KZ2piE`3~mDZrD9y{*?Zzj^@+NFzaM)tMC!zEwXN*dJPw|=Mwz1
zT+Q7NAadONGu1r0nLECOXYS@T$>2Q9lL@frY5sjTbb6V!6b|w>e?nVdA9F2*M|{l}
z=q2E1o{@*f6XtnOV94M66NMU2nm?jY!YT7IiUS6iOEqW=G=FK$hSDJO*<mO>ZC>02
zOTp%kSx^&VzMcmz)clxE<7dp%w6zK|KTDa&v*u~~orjxU=ztPo{@4r>X=cxX(kS!K
zj+nw|vkUDC;>=}V!I^XB5Gvq0Z~m<vj>elGQUEBy{IfkBu@lW#ZD8qwS<M6fqWL_<
zRxg>qEre*2c@Z7KlFbijbxJWiwZoZIvnOR$FPm%W@=%&Ni>~`*n_nIRcir4iYfX-M
z554qq&1;x2pJ%rF0|xWWiW7hrnlHVB;TD-$1yo~SY`#Tjgc5Ux6J$!wSvw$8Zm!LO
znhJB!U+AkeU!a^;mAQTywB0a=(VwEm>_w@fTJs@V4R4yC@&Q+8PN1iz-aO|E02<7b
z4FKFSZ@dVRM)UXdO`F^1Syb@cWPXG%Oj+kNn_C31+hX1qjuEz+8)#SGW<EF{GVNw-
z17@bftl$8D#~ghFN;}P8(2oDExupwz_sm+_z1=tO+z8TT?oz;fxB0UHi1e7}&IPX5
z{D7Y8KJ#P_JnT0=^C=o1n4dcf?$ZJDqDP>E=4y&M51C_^!Tdw>(IWWt$h?RA9yZ6(
z4q(LG`~eJ(nhVu%?XlT|E}Tx7-F|_=C+3|UFh6NdZ$;yj`F)?cg>viUix50&SxO}t
z$1EQ*pxN1yMoC5&%P_?ST`f0aA>wA)@&ME1ZYjM0Ne|0s6lU|Z{CgiFUY2G5gGz79
za2s$wmV>li^0j=i2*l5_n_|HyEZOsc^S7+M2$7SPGjv2fW%<@h_v->Ii%-MrK+E<`
z&=zF5+=LOGwxk$9f-Q1--a;&I)2}(y^7n3toUzOvgim3X6ItNSTDIQ-7jALPgTV;P
zL=X%{S~5#OqAY={ArftQRt|$PmgV&MqgcynXOK9{?=M?H&skzZ@Mk@5(No4V-m;j&
zUI~`>X>X8dNn8%|mn?CoA(><urqgV)rIJFHDV6~#+)lOFP=xogC4+*h=@tuZA2KXg
z=-YmomPgM)@`|OCibk$lY!||rEQ{(kaM_k0Lub5&r@_Lbdt*74(qxP<*HUu{GWnK3
z4~(h6;t>O93M~tMgh-L)e@g%?wrpsEWQpZ9%4(HbtUiN9i>=>3gu9iNg74sGmE|eA
zZF9rYin7f))s~#O&{bpE<^*4AEf+e`c+;Zx#Zc-jJGcPUTjUh<YOqXE)#ois1^wk4
zEw58J<F+M}_O?xyZ|HZ^Z24&fR$DAm`Z2Xywoxvj&2rPa7i_!5#vkr>Sbn4W;X4+m
zYRo~W<>_BAF?TKgL9lzz^80d#+_zlSfpl3u)T6Q2B58-EKFjYJ(A{sbc>=%#OZn5#
zIbdP%Au?$BmQEWFEr!LwJ+iD3pmEsZ@B+9IOXyN6OB}UqiUe@nl0@04$Ci;fAQP6&
z6o!0a`Qai&CM^pnM?Y;Trel?z?L7)X+uQa?!5y{@KLfafZPd^3;)rdpGdM@vTkarE
zwqMSJvZJ<sRH$>zb|Yo<oNYOM;9P9kH>fz?)pp*Gn9}36x%2~cvrVCZw7YHO5az<e
z_RYm;^tAnuUi4nJ11gyCwhg1Cp^xo{RITA_tEVu&pKUXhL!Pj84untswt_KeIcb}<
z9e`7|udRl^0k#PPup4Ome~zv@F6*j`Yp#ZAYNa_UE3Isqqi65Ex24saT2{`=%q+`C
zR76yU43VvDWr-kDwxSF{WUGK|1Ob($fbxD%{Bu6{o^!tE-242-z2}_!W5=&(1u$OO
zM*njzkTLfN6oVK!)8R!hBVi2`PcuH93z##E{sveIVJzrGXE<X)KfH)w6jQn_l5vc}
z%ux)*a;TqWd`YjAbBuQs=!|BxiJ=h7m_es>;uvqoqBEXxB?orTGaTqWmB8RFL8tu!
z<5!AiCNeftp!Fi-pViPvW~5RaF@^CY6~93$!@U<IjWOdaETuEHa6vK{<JoZS5@U21
z#+1pZcSS3UF{uizY{uRiDC9EUxQv;}W6TUdE1&TvWx6gi+A?7G3S&|QEEL!oE9m;T
z%9u=F0WV~%Uj^(UM!zp)iWyJnj9&?3_bULs&Y0{C6Qzt7s2HG(@gsRy&iIXft(%Np
zD}hqMD9M6CC1YbFcvXzYRp3=K_QpW3hS9VYq>hoUfygaJ2km}uGwe(0X?%ylFNWQE
zhAbDocNz0PgTW@o&HWH<X4K8X%(O77Hbb(N@tzw-(Z<lzPP3iykhV;nj6Mpw-D5b@
zrm%})NQOu^W6M_nyUz%!hBG~k_ox7+m$BeSkOz$0&!O`nW4gT&em`RTumBqUjNMMq
zA7FI;h1MX$)fw1Bj9EtjGt6+Hl-^^;^mS-GVSMEYpGFw>cR*o`@#6bHdCIut34fn4
zWVbNTamJRPU}8UWWDFt>%*7O?JHVX9hU6jUJq5rVnZK;1`|mI_^A~71F;i%}euSB~
z8Q9LuZJ|Ir%G5W(;BltgT(n%652+5`l^I4S4BVK?0Cc)DmrLO931%l{@;#Wtbgg?a
zn{D8EGaGk8;Uu%4HZnd;*Y`nAF{gbDOn+w2Wy*sEFrS7)G>|Dj56~cHS`%8q%#U;6
z{%K_YFkfewFVWUEl==8qh=eg0(}#+}naQE(j9})^MrS0mgF@y}%sd+XS?1n%U^kk%
z(HSB!%*0G|#xie4qBD-Ui(+T-%s=oB#eec*z7hmx0yBX2Y8RNtHi9HF_YOleiMiK=
zp<QGyq`M-8xpN}iPi4MC51}-sWg<qA&it0P0vXIrGW=SXnC*0gDU-RU10vbXRN5rv
zFzYF8k;~jnp`kqH8hR(?Gi%>P%YK>plN~Zwm~mG@t}-v>qxTx~G%d#qnYtX1B4+*`
z@QRt6toYSRn6sD=xz5Zx08++u^ak$+)0Gyq<;*{>fZSy2^3YkqwET#fsb*dgV1PBu
z_<3-xmYFvIkve8+E!1z>nOFZs?`@`T5@hZ$qYi>JFfS#6G&0Z9D&sD*<}Ms=Vn%3S
zzM1(xy)s&usdOc^GQXvY(RSu4Hz;&4!!M)N$?WW=+ksj77|>nJ`E*jTo0(53)ceeh
zJ<#i6?wOD2>Sfv;C@I~?Y^K1#1LiYIw>)BYP%&LUvn3NU1I(Je@M4hZXaV*R^P?w#
z8D_pp)lQF@fwV&zVSX|b107|)`wU);F}H7n<WuH0E1;h-m(_qb&U9UdUt~Ya?N5*c
zEPvXI9AstK7eW6JYp@Q)k+qh7*uyLlt$CbS{@qYK!Wvr+(W9(I3&1<ZGR=oG$5}!u
zmUm%o^@E5jt8NtDpI~*-87~jk8cNZ5vfkYS1us_3RQT)7TKEF|J;^eYh!1N~1w8a+
ztxTui-jDS$J+1v&mdhA+0L%CiIs;iNRzop}^+h*Y!K~6tFnESFc>y{@SXZ~B70POQ
z5w3-?UfK*V!da12J{`eY;)bzAvTo9%EQ<A36v$atFBN&6V>MImCYt3$rSGw<_7VF2
zRvc@%0gCagElF_rJS&ZM)(NcA?=gE9Sbxz5J&_f32_`PGE?fmkX2oBGzbUNeN`RKi
z`q&D$(^y+aA$f^4V>a|MSuDC_vsf)Bp^(j5=L3?%TD%sMkjwg;Jj`Q7IZVU-cbU~$
z4gD*u(tjXRz*==4=C88$h5+pvYd;my7P6`jz+e&U+z=#7SoJoTxXxlxrD-XvcsE*Q
ztjhvm-@xbG&{@t}LhJaOtPT~ts9^1*EP5p?k%G@vtgM9qt7c^k!Fzix>m7Qe)v@Y6
zfcaaj03CX7vj%<v+8x%6A22iZtj%1s8d#@)0PimAvj9jou{2Z^+RXZZ7H}=B^^1Vr
z$||B-?haPD8IE?c-VH$KJ=W}ejHQe9aS0^5SxFPny3Z2GA<|=K=_zX6$2xNb%?GR(
zmw-HE&AbKdN35TzprW4@H5V`gtVAXB2U#wZ)Ej1H&@1OLi**fXPgo1CVb~)qVK63d
zl;uaEr7>1VIfng|wT9vm&scv^Zf%^knPz)Gd-^m$JFxASSWrC3_U=UU5PQmNaK@4S
zKgzKkX0x_I!--w*2+$*JeKbUz*|pz8;TSvYGl(2#Po#=#7q;;Oh`6#l3P9Z0{Xap(
zgB=ovmM8n~&(QK>7g9-!H@j&zd^*Yg-h{FEu<PwFV=$-K>GxpCkKIC*NB(SkD-;9R
zY15$*$ZnueX%PGGoA?ca+5Zfnb(;MXEjL2g_4GanWxEeUA&mW54M;e<Yz9o={|CJV
z^+@)e6j+L4e@1KXv+VX8P&mhK@PTAB`-7J$^d7@@S%$&HvF!=ah-b$P!^C;^1QkRR
z*t=)}c!6C))#r(99}2`Lv48y=XvyqL8!#m)?D7VXRQ98FP)K7--5{CHUQbWyO!l`F
z*vMit3m}rsUhx`+o5QZ5h*mE9)-}5S^4KqJ0%$&4@;=6NnVnn&FRrln(M$0v`*%A1
zbB(=62oDR{u2k_^#MUf>NHP25YG7YyJ5hYCl)X>`UK#s5m70{Zo9VTGlf6ZOxu{_G
z(Dtp8JwFSsRk1%^4pPllcF-odhApPuaUJ_hCy-n0ZKY7W&0ayry6&*wqz7X?J7*9Y
z4eT`{@EY0qv<+)wn<oRinSIX=krwvlI4HETMbALm*gGhV-OkSc5FXxRe|{6*cd>JM
zAl>YUdg$F}zeJ07dk@>2?wnq>y8)to?2#^@Jz#%AYsH7`S{q0|`yhgpQwG>=v^pDP
zn<)-8#6Cf(vtjm%OMrR8J~xck2s=*&GRl6j3!P8d58|QzjQu`ch~sP?eL{3U$M7qD
z7zfT{I(T!y&Y9Yc=0Q#hr4t-ExAP!+nB!0JPbUs<3N(&zoX^5<XHHQ8(2jDL&X|N_
zoI~^oci~)=K+=^H7y+Ie=QO?j-8oa}nSFxOF&R7$PTL%ycys>x7p;>V-ZvPh4`<{T
zv`%rpf0-7EzMT6MkoV)Pjzi0zGnoPo0h~v4oIa4_djk5w9D^ggIL%QnK<f-=EiFt!
zIKR+yIh2#1i&+ongi%a4g7ejP@FJ4)GNm-na<+SFYZq*}zZ89Ood2zYU_9pr584SF
z|6P#3z>(3NlE~Tk21JrLTj`d($Wcs(E6JRv>(QCQS$hE&KpLlDD%8_CUnfC5gL8_`
z#a`n4O7Hhf&RQlqvp8ox%WD_dKcpMv3P+I+QosqCfH}U(`GHpF*EpFGFi^<3MHg`q
z$K^+mVh+0#yb{i192lN*oio&o&QeZKFh*C#IdT%M8=Mssy)Wme|2t&Fc})eY6`T?S
z6e>B#PlHr(I5|M6<rwX>6|CdPlVScACwB`(Z*x{r_39l?8zookIls~Vqk;4F1hg7C
zXXxc~m-8Eiw3;~6SRl=ukQbod!Z}C9{H>f=7htz>exS%|JEt@qL+ap^QF^|UGrA39
zzsH%E1-&lLkDmX1sf%+%3;p|?cDlg(IJ=j@iwB$sL1;bXY@x3|JmT1@V7H$mrU?50
zXM71v400Sl0_YIOup6MmoC;b)KIWAE1NA2ySIPp9a9lFs#V99f1f64?%0z%Y<;>JU
z@)^hH4?1%?&arO?%zo~XcLD0a)we?N0Jp9Wt%KZOH-LAT8$|0DC+-_>V)l-3hlJ2~
z=1xBf?4#T-`5?!*w`c)=oV%0^x^T~yfVgr~-iARpZYEuC?%dSJ==9(&CucmlF-7!Q
zTQ6=}FBHAGQQyMSN$%hDg7V?saRxcXJxqZ>U+xPp!6!d%4@IK=xh3A<1#thRkNO62
zcT?eJFgLaXCQfsA(UR;8_Yc}xg>ZeSuq2ebrWl=J+$mIN70x|IB?A#$A4>JuBe`GK
zf*HlV_ch2l?g#7OMKo7TOQaZXObJ|z<xZikU>tY*I27Z#J_+#RJa;1H922-rP8i_@
z?u=G+CUT!&2=yfHB)Ys(xEb_NOy%~x0g*JW^AB()of}F?*$nPxx*#suxuR+4&E(Fd
zqpMlmi*JHtbHgZHm&47ZS3@qB`4po0+{)iz{xVl7N9Pr;ni6FN+^fei(5u|bEl{||
zmAwH{$bI`a477;5<U=SFbN`~eehIgY3em1}y$?dYjQd_cyuZP<d;Nsoa&E$0ICYbo
zTnNPq?x!3WtmM8yA5pF1esUff)!bA{Hr8;<D8F9IUH%<J>bT9caJkJ@m4V#h&Z94^
z)N{k=3T)u+&qJ$``|IBzcexW*L9dD1sexoOH<0$oE!;2c5767n{e|9oZCn=$oOW`v
z^D(A-TxVLOcX4kHL8O~oLV51{+}jjk>*2a~!{1)6c{}v_xO2`z;Q@D;LQW64pS%U^
zN8IikkR0Idqr-)R-0h|CcZmBF7Z!%O-^Bs*G54+GbQ?e6>f|6J++aGtJIej&RiKS=
z1)lrr7ue%|K;Hpg?;@xl<Q<^U%^}{S+h{rRruc&#=Iyu+OebE)ahN^ATS%KWXWl!@
z0dkb*nh25Oyj!%@b>aP-2eYoc>{N8R@m`LEf;-QHF1!;w5j}T3c+oK!gD3CL|MmpD
z3w9wiym_9Kb~?#BO!*aG-mnK+e!K_IV`TokZz%5?z`N=I63CnN1xOHY@l3cK%rhN@
z!fD>ID400I<I{sBg!kzxOiU=xJOIgX-Z!+tiQrwdLNb!)M4!)!;ssFT{4CEHPtT`w
zybmbu70p}L17~7*5hKuu<!$>KB#xKxIuzr19rV&k;O)MN)&*YMGw3Js3h2F*#M|Km
zyBB%GRG^W}OQxfLDZFdX!F($3Qx1lm#yb@O=yYDd8i-`@RyRQ;llPi}asyesQ_--L
z&C90TcMk6aEo5_fztCs%@^~H;NYCdztb~cnJgp1J72cU`uv@^Zq1*l{Z*VoRi+GN-
za4zOWHbS8Ukxxio=hf4FUdsEJ0fS|jbvSc_=lB~$%6YFv(DUgguj()8SMWZh7kDMl
zxd)=vyuAl8!W!OhE5NJeeH{brI^GLgA##iN+phq<&Ext*@(xc%HQn{RC$yDn;Bg78
zk=H>_?z=qyB#1QgO7DQQ@OIJXOj>!Zh2XXErbR=~-p+gL3s~yljZnt4lXvMPEZyVn
zTMN-HUN(v%rgZb%#=*PKJF*v~m)A`PHv4!BKZm6UJP$9rDR?W3;o2kKQ!1_K=aqf~
z%mH5CMffzxQ{08*5U=fPs1Nhj9)!YUUh4{&AGPxq(6(cYcb<Ndr@WmM5r4+>rnuQS
zFP%QCu%G|ze=z94U)2lV0sc3UAP4!bd!c`bUvUEJj{GJwrqqeQrVr!@{}N@;o%zQ3
zaONogds<r`<2%terjGODD2wXC7yJZFSHAtd6&R=+e@76Q?)+H#LeUAnAB9jn`A6yO
zkr)3J159}H*Ij_(N&c%>(dol4`4Rq};yX@6%a?zE4EphBMMKY@Z)^f)0AE6f_XGJ8
zgD@At{PAFTahku4>Lt$b-{YYb!arv}k7g);>rI#l<J+k6Eu8O7*`5f#nVxo${KyQ9
zDT*IOvGlY2Z|U6>!{53Xc4PUDv_p^M`~8K1#`8aEgBR!d9kfbJ;CEBK`UU=#TIeP6
zqbdBA#8;g~>mvW7GPIKUlS}N-NaYW$hkhFWOR6SM=YL9z>kNJ{7y6g@JL$EV$$#!D
z>}K(AbHU5zmr{H%hktrLT+8K$u;6GOe-mw2F7s#NtD94<@HbI~djbF0Zy;Csmnp+{
zjlYB5?}hvqE<wGB&pb(Cw_<+Cdcc(MgT9C8b^hvk7*i>K(`A^y!C(6V94_b2XMuN<
zf0ptJ75sU_@Tro&BOaht{9XY_HNQgvlp2151F&oPfBK?T$FHk{Gq?CcDHQ7YesqYm
zf$vZ2%SQf|EfaA6HS;^^AbShn;~k8?mCvKOyw8ttg~1+v=rxdD{vXM(+s6-V0C~U<
z(t$kW*V7Z?5#K)wCi?kP*FkcC|G5Ms9OOTBz#xYBtX*gg^Lr^2@tA*SE;^s^ms=n?
z!VlRFb^9oPBfVkA_@3h+Px*gSqVO62<#izA{7TBw?iXk`L&HH3xdS2x1O@bEzJmf+
zs`)%5*f9&^brg)rF{Z<UY6=iI3D(eQy(5CgKY`*b_#a*4M+NMa&^somr|)te7i_0W
zaTmM5=mr>9!6%gPa}zA52b{ZLKBZDm2=pQ7^bow{ftIJ>hy^?^!K$s$_ZIMJhkjDP
zH)HaB1np5kIVC8jq^qys@=6dtfhQfd^%v}=@MM7CZA#Sz3MBLl3le-t^@70yyMkWg
zrv*!BQ+`G;fqwK5!6+?>Lj@D*TtJv$7oD*Q7i{!}euQAoMo2~qw)8_JN-**UrsS+(
z^M@ek1P&Anj~1+?I9-h3eRqsERuEBxnTZoTpj2JFz?I&c=LJ=C2_y(4_N6d*LGU#L
zqKSe@^wdid{NW3qE(*3$(jZx|fI>|v0%uyKqzW7;-Jd3Kr3HPuAZH^KG6XqW(U~Pk
zqk`LP!3VSt%@LH1!I@mao=B+Y2{y$-Bww&t0^Vi8#t5ii5d>$_g0nyn@+q9UD)4AQ
z>zZJI0+WS;?ey#|61+u~0mT9VEw@Vq4_}A=b-}S)uv;qlWh)fQ1n=($xgl6b72oB8
z9d!TQ6x?T{vqCUC9MF{l9pzT41gpP+7uABEF`(24e(RtU<+XyB&Z4(Y&`GtIw*<f6
z0nBYdJ>`7w2u{(Nl6t`$3qTtLkEo!zQLuO=^zRB5*1(G<!RjWMXcipWfmVy49>KIJ
ztpZyD6xswo(&f=EIL`;KL*RQFtxmzen}BjpAfHR$Wa<+1Q7J>W;O}M_yf0{_0+Sv=
zxfn3Lf{{INrcW?!Ia&_{t5YHJP~c4~>PG_3BeePj6DgBCAc)O_$e^I43U-GCvA@B?
zVZr>H5P2-<`wRx32wuWkc*=;tD;vB~!No}!wS7!5kKzSS1;J79;+fzv?W)EFi(doi
ze&MAcXgCNjyFlcCu#r-o2ZdVNA|DdIyBMI3!VR?TKP;603=t=x%Rg}Kh|p&yTF%0f
zFtm;ex6n%dnDAu<$Z_EbDq(OD{(20Ky4!^V4KQ&+=r)3058*yKMdB&sQOSpwu;gWE
zcniA(fH^4~ItmdVVHSNn?UZo&f3+S$TQypKLLPkp&R@8Q7I^`}jZ}9VDD<TJK1k?B
z8Kz*Nkt%9V3!7*;cSh*C0HY5P+9U6R87iErg=m=YbBa@h3(r&VFGBd)Hz1M1!&7ky
zL<twY2uIHfBPbGiP8jqu+>aJcQi2yF?3#>8h!yU4f=HauB@L~3Ax97O^TM<NNG1rk
zy#VM7!VKCMBnlt?idK>^%T7D~i^3IDa+)lBmCo3u2y@7%RN*%ifK3xN(V2yG;k_x~
zWeCI9z{DltG>Wrl3R@Kr$r3KRk5;yDA3gQ*ge!ufkT2XxXCy8QC#WzpSA>03iCG|A
z|0AHU3TM(Y`<gIfFTMW?g>TR+wn+H&Fcgc0^Xc<TCBg-JL9Ppr`$4o+=v0F#EfZGJ
zPVI(J^gPhYg_*OUUMUO`f>a4#r=VfA@a5HTv_{xZ@!MKqdO9TQg!?`M^ey4rS~zoC
z`1KW_+z|#zp2PiDFLZqk*bTywFTiXRPQc%kyTV%*$TSJND1O{5#M2Ttm(cNZfVK+n
z(igwmgm${f+lAlJPP#*Q{!5Tf;lRh>-4nJ^onn{JI1P5Yg$~sq_k{^ssP_ny$Kh|U
z@Vb>wl=lhWpuEuo;bt}z9}3m+7{w#u^Yk0^3mqvAG$6bk29ZJGY+7#*3IC+3l3}5d
z{CzCcve9}X+{1>*h%lTEQ;iCbQM7PO_~a-sp9-JL!6ZBr7FZxMF7$DMYx_l?(b){U
zgUF)=q6b8}d6>3?qN%hzJ0vQix1poRpDvTbqQ7T==OoH_42>hA&h;?pEP6m0lcS>d
z|AZIEL@o3vJTCh53e;UhH&0+jT}AVzL)}fZk?NA%MQo}QJ|XJ41fGZJY#<~(?IO7p
zXkMZx6X2V-=-e_ePl}Ar==2c@>5X?vltHU3Ur}#0EcuC^ZiA%1=oIC^0z{4*;YFb6
zaxX-JM3uDw4Hm^wE!k<&AM|~nGooBtN`#2QslF{#<n|rZBSb6cVGt>@_fxJTO7s)m
z0B1$DK>$4`s$GfBXwmf%I1?i(kB5m^(X&}F5hr>%3nKBNKdDOkyl5Ilof1T@Zvym!
zs8kD-M9~%6kR*xj9s|ln5tqWa$)eBb*_$F-cmQ@&MN4U8n<je4J_#D>q9Ge#GDHEC
zrn@A%{up*MMNSdu%o6#{fM~X8Eeow2(N+pb=89YoV4!)TnO-3IqJ-apeOY8a1+Xik
z9Ta;k5Z(G4{$3Ty*MN6TbeMuig(AaRSSS)j%mG-j$ghIle<h;#lhM2`n%oQQQqe~>
znCCLl0*aU45M|MtxLky4M7-5R*L*RU3Q-aLm#a$A-i5GKCDPMkx>l5T8R~VSEfFBM
zM45-7cU$z&Ch+cvgjADOFB+gnN`q)&HbfdlX)Uz=yeoQ%ZkZ;LA{|~di{4d(*&_OL
zEfiZtD!Q)PL@o4<jds!1kI>m6%Hn`@isp@g+!H;~1GG!@=O|j;qL?&*-4`{50;Naf
zL0=2%6}>?(mp;)sI(hLxWTX|;L(w+8%k5JhiQY+pOuy(6Es6(3qihUqP~@Bsv>}n-
zG?*V2t*4Tr$D)i|n8YU{t~V4$L>Y_08x_@3?0-zOjv^&bMJEcO_e}KWCV-8Lo=ybV
zez6-DJO^>JKNJp#BWMe9P&~aEJo_Q>M{9uQDDI`h?1#lyDaq(0PFM_$BjVH*u<I<2
z*#nWI;%mD>j)|{PaPYXebP3R0#G9#n(p5Ythn|}_=oUKN#VmUIoDjdV8j>DjcRKy<
zDW1L;cD=;EQ8kdaxQfC|C+%X>4p{OL4;Q0(O5F1!V0^_@3jpdT4yDJPzj)3#Is?S^
zGQb3iS9XCHB$iUmR<Jm34)jioYr^5$8L?|SS|Q@wlspa<`+J}jCVuO0D1?jWtcUps
z@w#rHM2ah1@nfG8dk*!^u<Pj+94pSDAXA(;mI_zm#fz4LoEO`v!X`odG9{ZXh##>)
z62<ZmC?|<q-^1)&6f-7(B#Wo-gF`9e&nU!@DrWu!+iBvHn*g0I?%D&C4Dmtw;V+3l
z+Y9wfu`v@Cvc&QBK+tS)D@9Lo#C5k}B3GQ236dxNo|Y{6;@4h>iOb@!4FJ6&zE=uf
zfjBh}madA|&?D=b*zpU96p9PZL!n6Ap@B2S;)8F)V2OAd2SdLuZoLi*rQ+&`n5#1J
z_s;O?hWN|Hv|KG0htf&-o8q@-f>elILSd;=+|LAPmAI1P_|@XcQ{i`w_&8k~wc?c>
zkgOAPsUY-@_*Er3>&44{1!#kKoGMis#ny1Rc2_K*yhD?CX+K<R7M~r2Gc97tHF(%6
z7VM!@A8q1M+C#RBFVGUJL%jbhSn3pi=nPNqiF>I)vP&FP2}|AL+qXdOi{q&prAM52
z7ihg=uQ-_K6FV%2!UOU0PvGxEapVY0JQByO0$9ITLwVH!@kA=B9Td-f8@wSg5ASn)
z)kwVYBJ4gEucp1i6LGmKm?Pq{o#-4Dw^K%7Ox!}1A5X>0=xpjU@moW%J1+ji9R~MH
z)SVy>lDV`9JRr%TE#yJT{3USvki<xVMMuddipU(6)EB@DCrJ&xJ&s7euK<|cS&}se
z8b>8PzXSA`r2hysTqOdke{_@R{(u+m5_LTEPe|_4V%tN~Iu*`%N`@)m;3fIs9;U=w
zqL~4`lai)Q!1j?$_zT#lB>!6ip0A|xCM@_#q%=-{N#-AD1xP|@1086WocbQ)JuTTz
zA&N7Sw?2o75Xk|`J%mcKsctPyvWy}W;SzBmKqDkR6t|0%9HA25D9QIBKszh>mfqRt
zBswbckCuG!GbCdq^^}5*m9%(4Bu)}P8KaMv3{tA)yyP!7pc5qa`sr}vf~0Rg6cZ&=
zN6<==9HVRQqU6tg08N&(g<@zalHzAjOqH1PftDs&O9eXVl9Id7%aFvs2((L*XY{De
zl=OcA$t=m&<q*l1#JhpyNP@ONBv&$vE~`Ar7iXZCFIi%zr_5!^LwbH+k(_@57Yig^
z6py+p*+bvnx+b~)6r@lxXE#8LB<nd)D3-kX6rd%N*;M3zU81=GUa6#vHV$PH_feQA
zml)`uE8LX)Itipg5-$a>Qo>vVy(-CHuR^3+!dBB7v_|4YnU`A0CK_m+WF`e@Zb=r<
z1mBj#u7}1Q$-60#te1REiVYIqsqmsv5=mvIcO{8RsJBQK(UFc;$&z!BY?JJpht76M
z?E$EFNXor|*(o_lPuhEu6ncnsN#6g6_JG|Iwl{pcFL|~K!|suseHSvlk|+UMeUk6!
zNbUp4*+oEmDEXxUFpng^G((|ZvTQ0~1|*40bPh_sTmroz$@C~F3`_1)@xfzB6Mg9B
ziR2He4I7aN7s2gO$qEy|#w0I0Q|ZN1$*mGtdM3F`m38Bi76*Xtm+pK5;vmhZea``@
zjKbLmrBP#0JS2VnJUShvFU$q#VQJ|F@SLOz-Uap%siFxY&eBzs=R7L?YXKyWN$b|Y
z!g1*_sy=m*9xQ^0t2BuY1=-!Cv9*wKm#(H*{t4-G3&8Y{9*@QdJ*BRpAYRgy*&yE1
zpJ*R&QhGQI<MolgO0S($(u&_;-d7qs1~fmZ8|`WQrLiA?1V~%yT@fhVK&PgHq+F^Q
z43@6Vh2ClDOnT&>u}d8(ninEXt$=8#)P-^uVbY8q7z~%T()sTQ=?dEEL`t)K0TU&i
z@f8%#N?qtxdQN(P3Gbt&O|(^yk$&I{&{*jmdfLWG`x4QLm%exg<h;}?9?%KWHEA$(
zLHd|>L5Wg(7~PIZ(ogAzzbGA}w{5aCkSa`5q?@xrQl*Mc@Y1AV4bVuJZoUJN4Cxn?
z?6@QqQ~7bGbmf<j%#x<jw;r>lD=6NdBmK((lDSgdZg`(3b);+cij?6BX9}dwGIU;*
zZn0Ci=9<)74~;_Ul#^f<N$1=Evsjw3AG{Lj^xNQFmtG72uT(mE1(wRBtiLhB8`6<<
zkaFppbRyxVbVVshg>)u)Q7H|m1F4cO&V@p?^rJ^GUnA{~fkLfxR}b8-lWw-yG0(T8
zwZmZEmd>LCop+?WXp>$q-A(1p4bpK3475@DLk<-0N}VX1(<E(v1)$B+r8bZj>Asba
zY?bEp!NWFbOCTn=UHaBiV0K8W--j2S(qa1k<UMJX2SmE0hbT1BEiI0s(u@1j*H#0x
zN4n$)WO}7$Dnsd$*5`vfkdD0sw1-l2D99seI7P1erQ7I5KOh}^4rqhYzc!#XBo$Jb
z?XYy1N~9l4&(XoGC(>EZ06il8st;hJ((M*Vj!Cy1gHKPT)3K()Cjg}1y$;ZE=`Jo5
z_shPb%#VX?D}6`ufb8LY_;gSfm4MDevbhx5bd(8cdwN**18szzWXtzp5{}5+=(X=G
zyH4rfqcVLNI*-Xdr}fEkS==nByU0#Zy4qD%NC#xxWLay_X?K@J{s6ltWcPQ0=^^W$
z58^3n9D%1^vbAr3cT#qPZVn%r_GS2eN;Zj7kG`_HRlxR>HD-YL%MLC<XMn7YimU=<
zE_4hwNVcC|^ue<IR2p+ymJyED8QJ!QAR)3<6krUs%O;cGVY02C!bG@CPiyW7*(-D^
zBvK}#Rcn-NgA}uORyH8Su+PaZF9a`I_C4)JVq}V3h{Vb?`Dn$-(jP!1URL-jP|nK)
z{%|cpmP=2c3$mLH;3dlPzJT2%*#wHRUX<B;Hlmp<`<%9PDYBSkV5iDFw}P1_b9xhs
z>9UU~Mx7x`q_Z@aWH-q~rfkp?K4r;1c@HAlvOO+n<;Z@df#%BgP$5*FOjiw(FH4&Q
zu*<Tow8p<8dzqp<1+r+0$zPR)+v$mXO}1eVWQt_A9+)VWW$Z_1iEJU|udd79tAa+U
zEQ)qIWwOU<FnB|zZ^F-1F58ib)=in~BD5-G(Gs*OW&3DzP$dhAf}_>4-|5n;k(DuE
zzE;*c29!G4BifbUlD)Z*(lfVZVShm5j_isbEY-_~lu&GtoqG$zZj>zwhZlEc>%N3*
zO|rSq0j*gUPz}8nSqkl7TV<0!0<TT>7wuHqW$u)j>yX*#bX2EoQ5C@M$-Joos!MiO
z2wt}=?jW4GFXLUOQ~y1(*%bfomHkCOY@h7*=P>a=w%iSac_{1s1at97)<M^Lzw8=)
zN^C$TSObMY*^Ue-49OxwV0Tzn{}hssWv|f<|3p?z+5Hh2_jQPj$~MyCVN7=JJ9zO_
zHicGT&ty}wsq|@FmPaAY{qm>t;i-c>X)DMfx%Yp?(emegVeqhAvJJ#ZE~lIFi2UEB
zXgSL}lVRehd|NF1Jtm)$0CHU3L=_7z@+2WzuJZO7Fz6<4?14dd`Fo`xC*;R`AmSn4
zb`&kUr+hyx>%8Q$7vQP4{H2|6=A?Z3Nyzxfn`yy&N`BA{oxbvc>k#pize8&^fB9!c
zAOZ4vS_KEnE58FTNPdo%K*92~2jHESPrMFtMm{G7Bt-7{2f#w*E0<y}!sNQiAmMho
zLmNDekhAG=7b)Mm4Ej;>DU=yME0+jC&dGPZ4H7M%c^sDF<ZIsoOuXFhT_~KF$G(Nm
z1o;F4y&(S|Z446SFN{JYNggbN+ZW~6{(yS2{Nq@V6!~Mi$WrB|5crfPw?97@`swm*
zJD`{$H?IV_B>$aeHdDSk5-?fv;ZbyE%a=J~ggNp>^U#?qccj}ePyRNQ_vXw0h=Isu
z`LPR_wJY*%QJD1t`3SuouF7Ab-OV+*zyYm7`OoX1S0qoXfI_j{Xs27eM7~1@nd|bq
zufasAe9tP#l*u<zfaHce_jmBh<;#v?FgN9%A#lG!u8KfsrTnAS0Iibeehidq`TCE+
ztC3Hq7)-7FMKWI}KXe5%b4%__sj=Jg=tkJRBY(agBK7jtNP2ZN$V**;)+p~j42`?;
zLzLWYlHW~%Otbti6FOVuK~rG9RbE1+d~Na%C==N!?@5B>J$bDG)72%9q6zMn&m^$>
z@}=8BdgM8tif8ZGQ_7&$FW>eatPjWoQ^6XPztaWdLvjZS;10_(sKD&8yzWmxK9RpY
z10o~xSNcFk<-WAc9+Tg31IknR4*ETw$&H?{Ixe671=RN|>M5t>pwK*z89bl}q**?w
z_<APh<&eVN9tK56#d@0b!wM~(vU5_{Zvy*>B9FfE<g6%~4E>{ud@8g&rbwi+mg9=^
zObpsZ;c^o#SH)8==(#Cw(#q+SBFqbReHDA31MyR={TY(}ir4PJZh)fl2e=lfU{g{i
zNa6Fb9s0qF4^?2ER?ORk))_@IWokndMmLxbRm`H)VVGiZGc>{#W3+yYP`vs*c#(>@
zc#I-S@o)&dvx={tp!1v}w;IkwD~$U=VieEO3CUQ+FJC}1PBG^dco?s!{}SZ9qI@@<
z?M_g{{*2}YMK2HfiHb&AJ0vM&RLyWvF~<n=$qE%M{ZkZA_JX7;zM$hqX^OW$!C=xA
ztiv#oq4>caCN3#5=yjW^$owD7XDMPS7MHDPKZ?#A#ZG!g=PEYGLgBJvDo!ofr(99g
z`=GZ#5k!mUtBU(u0eVfLrL1P5!fP*hMT&YEV2Txy-+@=6_=lF3rHT$JQ7BWyP{`+o
z!btg|az+0&keiBnI=)z;a2rOeQZX=uu~aF%Df3^g5CnnLC|>#kWASdC_=^3`Ib6uM
z6<=M%Q12*K?S@XHf=f@^yNVnINVB3b2RbbZA-$7Z6-5IOX;Yk_<a@iK&kP?s6j|v&
z=~T?y09*GI@f1+#QY2HIOSj_oIk<CQv4;lLqnJo%uzD4DsiLJ%p|aNj^npUGhd&P$
zaysVtND)U@ZNH*%K3W5ci*&kXQ1MS5$dKZ39LTVudK~5-D`IGS^F;BGVoD<laT^py
z74m#wjwzfey75%8a~YtYDSqK%rp6WS6ozw9_E1RwfHEPNRu2c2-4xV2th{g<Oef{X
zG>u1;9*5wCvoh-uM2{-7%&>G!x#cquS7mJ>6x@_wz6=p}<(iEU@l?*Cx&SXF{~AQR
zmGi}Dom5uP&*r1dtAOMwWjfWx`zpVqvo?Op_x_=3K!4?%-@@+zWgmt81C<+Ignp26
z`3=YfE0ZY&d0Ls|fz}yi7TqNw%8v#i8LIs81Na-JoZSWzuGExZgb~VZ0pLX{W9Xe6
zrK}MH?5wi(SMbg$ms9pSTDj=IY_RgvU+DV+vC7?4H4~@&IRd`LE5BO^XU;3VJ_byJ
z(v|Mc3(CSCm`GISY(gtZ`Q!I!T~u<rfSs&-F%+OF%HN9NXsWWg8X{@RM_No!y7HCd
zAQ{Rgiqc+Eel`u5*-9IQ6LXY%X{l(>RZ6J_Gfx@u6-d6a;WJ=gR_32a>x%MZDnJXA
zZ=S)huPT#kK&~lwXG5e=IY=w1BIQGR#}zB1wIC(RO}9a=E6;MEUaE{rh21ix7saS=
zD1}SmOu6y}CA_$)%=!V)6?Wym41iWDvuM3urHniS#cHKj5L$K0aw=xLrJP9RTep>C
zw4%AAjG`KtdZnHoaSh73^f|porMMg>?kbN>fMk=ha2O+ORfdnlnKtDF3TLz{gN{R_
zPsw}-&<~U^Qvl?l(w;O4`U6VOk0CRt%zGI!L&~dkf@WBmM&E6HtYlKm_=)nsEVRay
z>!|kqsd6)|VV)^J{1^%jstf<X(gD@USAlX+wV0x9hg9wZAdaf@KLG5oDuq0BSB1X~
zloP6}lr!;A3GE-iyr*i;MfmNdVqAhHZ<Trnm?u^5o`eY>Ro3fJJf&)*5?@~x;{{0i
zskR4z=da44&1`_`Rf?kos$A%lageH?rt-9EH(hLJRBNx{HwaPPp^!zWDu>Dv!c@Ck
z(F#|YciUk;O4aWH#j~pNOfb)>)=@|~T2<5rPh(V8ny6USoY}Axr^+h8nBr9j3L$b{
z<#`bb397YXs9#W7PJ@@I($7LGNmcwIL@uh>yC9OR8l_N4iYmAfKBcPOr<hKLszE^6
zjx5!9C7Ri)q_078RNYT8iMgux_n?)h+R+Zse3f=5CgHN`iW<Bts{T&^TA)%7!qQdM
zZpyk}Qzg5@(Lz-%RYer3(sx0xSXE97#}d_d>!5I5C3J*Hsp=$ceaciT@EN2Jrrc0{
zWkR!D^-Cp~H&sivK)*^gJp`m)<xgws2G#PZJ}0J5oU>>K)s#1@UTMbIT2+DT0p6zC
zSBI%-SC#wZPM!Fwy^&6ob*XahL9$zQ_#i}jREbmw+p9X`45#{3g|28lQ035kJydZo
zz{Dd}rUH8Xs^}7UI-pv%59S9|Ij(38seI3aH>{fe3r7D$)l7HQh-x*x2u4*`{{(ML
zl}W{RPgNW2OpM~0>fT;pkE<9&_N)CV@amv0$N}$wx=|1PgX)dDp?FCB{XTR$syB4N
zi^J;Qx&Z2={^oahe?&d=FYuhzZ~8*=sG9LSh^zYF<?zB?t)&<L2{m^b2I!&Aq!Xl`
z>V*zeZRe%_l%mMq>hwzxJ*D1o2ZQldYXiaaQ)klmru@~t?}8Vg{wW=bf$BGC)`HY?
zDP$R}o<uj^Y4y?ffD)p1p@3_s`p|udgsDIF2Uxgz=u4<as9%2<<|EZZV{ki4&DcSq
z`?KnUlpH>%_WJ`c(dy^kf<}yb+H-)3RljEfiB}KO)8M>XL=&8#{=x#73+n&Trxg;_
z$+XM4s6N{W&}4Pu4S12F_D=&?s#=)}ku-JjIq0RUlUvcsP^Xf;Om#lWckNTM)Y3bc
zwrutDRJE3))~*0du6orM7=504IxV>K)eJiCaZO#f6mwCiuBM}jMQRzPFpJe;6s#yw
zADIYVsroC5B$TPYybIn9bwLey73!T_s8_1fsr08x{U&{ts9LSth9TK&)Qhh`u}=NV
zb=bY7K1&JF+v@pW0H#6R@+NqV>Ovz1b634*9Cn-3V-$mHRv*ZPLW_FId?>W4J$FH}
zUH!-hk{#-LDl+d>7gd6HPraxSUUaDishF8=wJrnXzB*zMU_EyA>R(`~S6xU6ribcS
zN}WDZYiZ-zuQtj7GoTK(0eet=qZPa%wVC!VkJW!u(&~wNp9I(=>V@w@WK_LOjLtE2
z=6Ya{tB>VDa=+%le|u7mX*N0!XtoL9{XtDRg_{p)>>*w-e^?Vg3!+Y%cYHyPXzD4C
z>#R9Nk%*(3kO+vnXc!dQb=AzHe7BosTm%o@HC`DIIia~`1@X|R+M({Lnf4J{UYfQF
zi1=tWpF`&<%@GQK_-Zm}C*!Aik=};>nkM@!^y2@$yF(*L^Lq|Ru%?Uxpl3AqUcq=n
zH0R4<H&hc#=WoL__rHeuaLu|Zz(i;o-vTd6^Bx@lI;$~Eg28hd*-CUqYj%4;Bt~;^
z74%{?b@T|2*R<2??7U_rfhB0Z+DfUj3!1%Dke8@Y(0nCp@_)pvr)WMg0VY-BxC9fN
zrrAg$=^Bp@p`W4o=xy*WX^sZN!%WQ{%E@GD)=}wCw&r9fcsZJnhv7`F=AST-Jk3c;
z<>zZyE`YwQ*_QxAS2VsWD0En$ak9e1Rn1u{0V>qoxD3CGH2=~sTCCB10#8dcakTxt
zuG!`Sky6dRGvJkJswfR|LsPT@Xyuy3QJ~z^tdD{D3e9AStyXH9H$kCFGrbU`S`$sV
zry5QDUue~8!o@F5@KH~n_@aH|2SB*3`IQIDcQoHvLFzT{Q4wsT=Fn3J-_<DcG4LkM
z<ayvVYgSWQq(!sg8AjErDJ{pq+cY&_g4eF8pjbeMrj2TsIyJq6fWD_mp$e!jO)Mo8
zx;3u{L*c&Wr%nv2M|0X<jNV?&*;hdNG!+yKc%TVe1DHn|*A^)DYqstM%z$Q^7QA6i
zC~cn}YX+}?Jkfj|12Up{`%?^VRPzo!na4Dt|AX64H3Jlve5PSjebBh(1U*LfYr8jq
z=b$}ohWP{9&R{z<4r<59i$hws{SbB3{`x#R4{O&_VS|%)bu`Q$(Y781&slr&JGg&T
z>oAB(IHo;10KMbd^=7nOv_%=vbJZ@TJhq!Qi#9{<+S#9AEGM*53XpqfZM5L<)Mn`5
znwPdCifV|wwd>l^JgNPXK6~J!okl<VDQyoOL-5t|!_e~67SS5pU&|`QKm)WJ)$k%v
z`^z|d3ex^U+r40IOBWPQYvUe*glavgYA;ONL7~KO?Hd%(jL@b~kS9{xyc8%=+6#Cn
z*{7V<zDAe8Ic*26d84&YD6|l(Rh&XAPRon}iPwHW`-Vhqs3+_uX`lTJXD(_VQCc!t
zJCjluDO%-wFqo?CE(R}68$|o~bglGXfMsZ>rNH1N?e}zfWNLqB0W3?qdMzBaXKR^%
zfSIFR?FVMAcK#)R=4rp9JxRXy^sf-TtUd7w$QA9xD=<-@t)zw0Rc-%MC|uJ{px>@g
z+j117NXzbqWU;n@uD}xQ>_muM*Ro5YP^wLcgKK5lkaxhlp`B~Mtd-lfn;%2trdGBN
z%?j<TM{ufA8&VFxtF%vOC0eab+7D8rz1sxWYPEIcuvDk@VF2xx*2@pA+uC8OBE6$s
zW5lrQwXJkHH)wIk;x^LGqMh?y?f5G2nzZe7MzC4yM1{mHTKj6MG;P%u)3K*EZNOy6
zv}^rdgkp#GRf@28YLimYx~J`SgQH#Aixed4*1owIlJ~V{T7~pzb38GoUabSYANsT(
zEr7uX+HdZo^-%ky2(3rjI$FK-YrAuxFrdBA41Wi;Z`r8=c}VNfiV+TLvuV#bqGjcy
zHL9Jn8!nD%p9=(es{Pp;CZ1`XUI*y7cHUfo?$>o4MyG@B7fQGu(3$7L!-KjN^sYUm
z%cdulqi$Xw)DP>v-UPRubTJN)Jfi!B(u&Ty)hU#}IjY+*g61*ZrJK+=uDdD%wu^2O
zT`jIU8(nN}x}|F&;;w7|F9fQ)L-B48T~jWc@zibo1qQuz%R@0jZ{0LX)}Pc}bHiAC
zbbe&vl<xcIFeG1{7rnv!berCQNT9A%PLY+<Itf)uoY5srfx!^ngJ@uf>h{pXBuw`z
z6+MOPvMG8Jp_@k!zewE>MaZLcMV&BlR`)yQi_hs^+zymzT{#8OV|3GLr4XxoBO1Io
zUGOA08n5#@2KDngZ6Pcq=+=!)!2NeY$6O7WMBOFYEGFr$37~&b_Z`JPlXd4`Kxc~X
zAG*3zb)41cOw&E8h23;r(f{CYhVBs?3YT<KYvEI-ZuAUHWa(y8L_b^SU5L&c-CJ}r
zBUh)Mh0Z*k&;uy>x(^G$vtQQ5a?yK57fl5w1-jkzl)tJ=TMUP<=>|T8Org%{1Lzm&
zez*rOigk-W!9YuN+o&A+x-RM@6iRiU&<3YW=OqBSp%WY7TDk5AD)_vqTeK4j6}k`9
zK&jMq&IL-9?mpcd)pp%8TItv5)O47%R+l{y%sSmW{?NarYx*3X-qtPK0N!2QUr%AF
zSr<e>qZZwU1K_pl%IQ98({bteL%Xhe0!(!15@<o#saq+<$nNRfpMck;tK&oRf$l;y
zP#)>pUIFRX*}tVo_keE61;`BR;+-(2$GR4Z>ORrA)7oN0SGXSLM|CG@!9J$@u@|kU
zI+hoB&vakX;(A<HPn+BQ`fQpK2mMSrS_kxR^@1GK&!VU8A^rSj49QVHH4$DM);E-a
zIO*97{|4w0eKu{;o%OHMM&qddxn&sIG5xPTO>?kK`j@Iz-1M$ff#$B?zY-=+=-;>v
z;-UYYE&)${BIR_w^i3t`^w#g(0iRClFH*wDN55VK^;3GM&w%Nxf4&*SPrr@E;;&yy
zsptUxffx)oP#-!9g&@7S5{82HryfA>w0@f10MIk~<G+K1=u0-EH&oyF-ws1Ru0$(b
zKNN*IjL?@*RZyh<!%66j(r@Ge`>fvaGmPw<zW!T~X#LbVa5P3=vmGQ>-?9kK#OXi$
z3nX42u?jw&*H57+ZG!&jC+NJO@2I3VbfSJHo%&7EPl*NdqW--Pz)aR}xCmZ~-nkEo
zsrncLyhzil)6q)TKmH#kAw$pI1WQ@^5BVV3`o^8$<>;rgfs(6_rb_EPeb-@(K41S6
zmAhWn&rZPTujtSG1d#&$y#2IHyQ=@}9AvKPe|;Ujh5FwIAycGJr4t9m`uiFTtwg_>
z3hJ-xU!;QVQvKhr!QV3d=kqZMH}r|rD%U5{=R0od57FkdLZ42lp-O$i0w`4JzoCk(
zYW@BUpw#H!q=ad$zD-O2n6XaJbOQ61exVOwZtLHmV;6VylDm+p*YDp1UW2|}kGW{n
zzmyG;yLyEZB29V$Jt&&>GRk1I=qJ$ufL8rJdRKJlx2}Y1o%$0CA#zW@VkUT9dJ~0y
zyY+rEAaY;-CnXu}J^FX<0JK+s%m|r2{klBN#RL7PC1^d=TXv!KNI%sA(SCg<mA4G&
zw^C*6puUd+6GQqSI{rGW4-N&&V|~mdNIubjNRE!^dnlYds^3GgsWH8KEHIzye{F;p
z&-6ngNRHd}JX!$nH#AalkAvYzAbJlNCeDM*L4zB86XcNL(-(o}Xc*`Q%wa>)UU=bT
z2;Ya!BL?3%5NE^X^{{l*&`e?fV}_#?jy-M=*n#3=m`5Q<S3|%OwA>8tU9jhFSbPwM
zP8jT53JG`^yr?3@)3B5Z@VpG%N4OHa4Qd_~Pa2d15Itp3QVPV^(Dpt={0w(!3FB`_
zqs?W2;baO(prNlDU_pitzXmVZ@F*M#rwvCaA%4cNp%|SZhFcWp4>im=ht4p=TlQ?s
zWw^med7}tJ^H(5|hOfc_6J?kufy`OM!~np=7*>1^yRn88O8vzd%KhMPyrE$xM9v$|
zP`PV@;fr)QdciRMBU*`u(_RosGHj)XZHnQcJM>ZwH&0=L(hNt6A$iG=IG?sjnTA7|
z@GZ-*?0GP=4JNvfa||;nFqvy;*a!VQgPdZm`G(ihz`JZXFadg33>|bhr@%041ISea
z-x*`MW{9N+d7&ZwZAcawq9`d^Y?yZsq{NV30lU`?0$S0R8m3&JQ=Vmpmp*~$4MW~U
zfR-Ef(cAQ<;g%5^6^3&ZhpjX)`p~K}i0SZEwIPi%TQ!EH)sU<;6l?`rogw0Tv~C$p
z!4SD^Xk7ww$56QiuGJg1Q(;MiA%XTKjfS_WhU2c`*~hd(ZZhb&P;54wJ^;`bL%>Q*
zTdTq0N02td)E&@hH_TWM{SJd+44s{ZDyojVXE;U!?J^u*jLvRD=XIdmH+XJDtH<yl
z0zUN`3Z9|WXDD6)gAWYv^FSUN&d>wqkwHnv!0r8pBa0w9V5q0)?4aRydSwh5e)tM9
z!-ki>f!)W3zcf&MVz^CFzY#;wR~Xu;VTJ*`F+&4gq)!dOk!U?LI8s=3+;EYKA@&>B
z-UZk}qwiJd9Ww3>0dX|mq1eM=<IgHcI@yi6U!Zx!xcM%;a5kn>8s@06hc>>)j5p}X
zcHDTLPDr^Jk1mBzuExMVwA_ppw5)PBMs@?{gmE?%vUwQiOa{->_{blaUdGjPf#Pkf
zq`2fs<G-}V^D+KQ&!SVtos>!RHQJXQMbppt8O3`1jUWDv-T-64WGDt2|BV4mkZ}#&
zo54mOAw*6ar_j%I#`p?t^+Js6s5U6nxSDDi!;A*HtHO;3+JG5h45JiHr12$MyF?jx
zK8C_sV-l4d#~4?*LLt`ZY5x{88)qCl1rl%Ub;Kl|H~M}EPZNyouV921jESCTB^u}D
zqLpN9m=1%<#`me3A;lQ@J6uaO?p_JKG~-?>XH7TmsfCG4#%WYck!hTi1cfZ)r};3S
zZQN}EFUQzN8R=YOQaru?E*oc1F7S%6h*l2;#?_R2ylR|!1g&dEEfsGS8tbXvqR6<6
zLO#XDi46E#VjTPqL%VLw^n`k;@z^35EHfJE0d>Q;lkS6ZW7#k)+%z6+hI)n3bR7zn
z#>PCTR~d(w()+L4xb8LhR%3La++(dVnrdt7jIYqT>XwnY3~0BF%T~a|9pjcnpw%0v
zQZ}c-_|bdlY{YK>(7VRz8{t}$aSsC`Ek@k^xQ&d)e?U5n69NF;X>6pU`1g#aY^Zk`
z7rjsKzi#7l7r@*%R-2&TWBhU+TD`^~sw?X={yYxyz&MNcs}GGoxxw#8#^36IHfU@}
z25-nXMu!WAjnim>@!0r2RVY0%?xIN;F|OZ%A7<3}sSa~7X7s0WkEce<a_BuXF4+M`
z?c>I+6jj=9`mP@2fa$?YaPgpNVLmhtnU)Sf#?kcSc4!<nP5%=noJ^k|g9&%jMghnP
zQ$`&`JWQ``gNUc;%vl)pGR;VZd2drCmHnPFSt-}*YYJ|Gx}V8qJD~kdkq^NOu$x@e
z5DhdLM$rs1U5^E5uql)dXq`4aM~TEUCVyHBgqTWN&<ZuZo)4HXlM5Xg2sb%(pfkdB
zl@c%KO*bhcpJ1{*##APng6lDsB-2m70_>tGj1v0Erh?aCD8;mY5=g4a{>@@wr<s<$
z4A68_ayv$mVS0&TVwX&Xze6U|v@aX_Stc6;BH5-HvjLi8N}|H7TvIc}Ve?Fv{>x67
z4$v;+vZ?kGoVj8W&{CwpG`0;WS4{^g6n@P#m+Tgr4pAPY$dqY61pQ*ucfnwmm@e&w
z-Rq|I*}yI}HBkDt%yfAeoi|LHMu3)^4CLrdlb8bC6{dw$DqCq<oCjW&X$i#ut4#`W
zrp9z*I(W6FjkLR|Gv$q-b<1?H2a>l<-{wNS!L&h3MI4Q$i>2tjYs&o=GEJslZ%ksd
zY28t{)?(W7GDxebHW{65rcd|6{dQC0-{|ZxHSEL8behI!$#&1QgB~<prgKb?Zc|t@
zI`5kzs7$iQ^h5@Oy{3!du-9kmeF#GjOzFjx_jzcVIvWFhWOAB=%d_9~&pyZun0#xX
zKWKVC0*XT>F75A!P5XWU@3F~oA-s5E`s_t0jF^^{V7#NI$|+D7GktUz=AW8&(npq_
zncQg$F>YEztJwW!J5|*=n7`Wzkpt$aUG$ZMgXU(+DIGGGP_Dz#{FKT?4x4#Axaefg
z_C)7Vv%DCiIA-o@gcrxnKdyyc7xV2P=((C*=+W<H?xbzHyLo>g44yD=qByFDSuz0%
zo@OS+cD>AhEkmcb*_W!*PMRzKz{u=A=4-=Xo-*I3Vg+AwnhAsPGxHMB>2EGy01{x{
zNxyxdxs6s}LFQ=`xD7TR4MFE=^Uwcfq|G1fh8H2`J&WOQs5y<Qti#Oeb|{3K*HmIi
z5$03zup4Q<XvS<unOo`9)mgh)Krx|n=C9U6CfXeKA$nuX`t|T4*8J6Jh{l;C-hij^
z=AVOsecsH-gZTur2j!_QnB{Z@C7O5A0wKxFPXxJWwowc$+5C(iP$}lwZvr~iTuo<L
z(#&7erXk(DwHxXgW_v{*nwQK@v}VgR-&p{eEORlPmd-XeQ~hj?xycA;a?L-{fzCX$
z2c130H`mef_p*65y&JEXbDluGz+7epxoS4dz>uz)mr*f8p*bc1l0{}!7{H3nyXd@q
ziFqEKsJd=mXQ##V4RiWsG%L(0v_q{le?WyfRp#F){Znmzwh9Jo%uPW6tu^l$fWbO*
z=SINXGEZtl>$Z7pGfdnuucp{$z4>oC^Uz@aqz596=D|GJy=(rPP9HXzf8GO>X7kU7
zA=zS<>S)o^YW|7h0&V7+bwF!3YiVXX%zpFXMW^}K?J$4O{NvZq=rSLrfN8gRlon$5
z&8hD2u*bY46ezvsSCZgGpV{|c7<^#9u?m(Rn%{g0B9F}f(1DYFb1Xe}2F$`6P#-jl
za$dsyH)P%%jOMVp^%k%nn|D(T`ic4e9EgsX4~+tC)ch|6F2~G^UVw?G=0pl2Ju~}P
zL1End6YWs<TPF8F(!uh2C)_?@3D96jj+WMG06T0k&jWF?7}i4Jh-Gpqc+QqFKdLZ1
zYVl^G*Tphv2*lO0o(?g(S+;dS#>4W$EX;+c<^36Gd0DQk#guwm3c`VQ(o*smJRb`$
z4m>~0Dq8;fTh5K46<~Rvo*sdgQ43l@mba<YAlT9{2hgW2vuJy9#<H7MllBlx6lH2c
zEvxC~471$*6hjNQypFZ;lnBcS7GxqV7bzbfW%-nX{AVq9sNnXTWu+X$j<$G}0W`)k
z@ePbV*79vT)Z;8C=pKu=9LWRpc}wCQv=S_PX9MhlW#4X)L`!HS^pfnBkCuU6w1mEi
zpE=pmk_byFmLz(Ordn=LNGi>8*aVSuOD8SeGAzGSl>Cx~L+ijy%LaO3W?9@`L1(sQ
zZZi~eER#DxaxL$AgXCFW6oTYi_S3WEvc;XAXjd#fC(v17v3C~0x2u*vJJ5U0a&-ZQ
zR%nsa`=rRyL5a&^OXhze0Lx$>%wM;BNEJ$@mh*Hwlv&a#*muM7V*^OJ<sGW(xoNp|
z8oUZi?G~7*w0uH~o+?ZG1&plP(&vlL8jEu~L~1S1>{VdaSvGx+xx8hu(G_^xA}WP5
zcPvSC-`88*|AF6kE!SyP*kqYOl^xBN-7BEiVwpS(Xswol6S(HuEGx^P-fl5Y#awh)
zUZbC)(;_42dlq8}P`WIuD74ybS+D~N_bs9GXouWm8Kwf(UdxYXfYxWZd=i}xERIyC
z_R#W?49+~V{GA5UZ>e4Y>;X#|eF$sN680NJhAf9DJvVGwwFr8TEzYzEe`1NIGWHS6
zVv2N*TE6Xp-k2q_4w6qTu5_(Fvs4|T`)}ORMr)t_)`lr?%E2n028Rz=LlPi!(5i`s
zYlo}~dM!9wx3|OYVe31zPj<34-2vJWD<=w;oUQVAp>WiCJpsI9)<bWAcieh`f@Ut(
z=a$0@SF47;>*i){n+Oqi>)tX-Q=hQ91)}L;ePbRhd0PLbSd^DlOc60}D|-Z;C#|=$
z;h~T9jZ#eFDeKn%!5Lp`DeV^gtV`($;cv|ugF=9HEnccq0<EvV1%pA>lTBy^TgShE
zGpDWniRe6I9il3t5G(f-Q0$@BkbKBQSYJoTbV{W4F>U3etTy_!qpkPDz>Bd)k3&D!
zs-<V(d8;qI+7qnvC}wcMdVe806Rpv-(@e5X&w<`WYg_@GNwvn_!_1^v^?J0@t$kF`
zm0=yE%8E<YuCKt$v|D%40x-+^Hf8*>tx5lt(OPFcg=ntzTL~=XStnD-KHoY-MYWf$
z3n=Sz#acoe-2&@m3Qk_NmQ$SfnpN~Sc!k#BHeeT77iK`c*gAo(pb{%f4&HU^G|FO>
zT6y%kFSFVYi@>~LUC@isms>Ybbn>S4#1uGFVXgQXGL_cn=`)H|)}0hltF{(Uh^NN7
zlg^*lTBUSosLty5ITUVLwdLU5wyvk;)g7xT3wrg|x4r?d!5Xp^q|sVNm(^WsO(=LR
z*5~Y};eM-iA-x>itfs{PZMTN2K{~8Io`n0I)@igmx@QeqgU&9ih(e^@)-~;L^uBci
zJ+*qQrw)SjS|2{fu=}iIYA8Ig>gZ!m53RR7VE2*rou6Q+-#S|i$pPyqg=Pn>zk2)(
z=8*M&6uup{uG<CB$JW`D;e29U=MB*j>*;XtMy)^m2<$Oy#RI@RwQkn|`<Ycp#a9kC
z?<Pndunks&9JH;Win+tKDNPutlg*h8%p*1j9~}00)qbWQ_Kw?@(@Mt0Hj65<Tx~wn
zLELQfAE49Sww-c&Cu||pVaUVQMU~f{HWQtP@Uq3d188sCYd0Wy()PrTP9K|qj#!<t
zeM66IUz^Pe;%C#gz<Qu<mmWh2vK2c6GuURcQ{B;N+vDw!Ib$27*k*{W@kNX*)TT5;
zBh0pD4Mf6ih0zd+ux)t<LyELjQi*SrEs1JQ&e~i*LgzVK{8Fe#+y3zYiLuqux--`H
z<uZuG+1`x-X1ope1a27HYBoGfuzj<`j=8vCYj_6HL|Y^+*OP2T`yq4D7KKlKO-Z&*
zqi0Zx&8Z*yskVDT=uERsqVnN%n~i?73|k!Kx-QwinFPC;HikDuvTPOA@HgA`CFRy~
zZ2c5p&b6f+M`xbRlb#d#wz=Qa)9$j3)rWyzvHcwf(E{6I87y73@h_ou&9=D!Xoa@a
zJHRfoeX9ZQy6xkIXx*^AmJQHyn}W`Q-L%c5Wp9Ozxe<Dmwyz~HQDuAKH*{9peyhL$
zYiy#|(OGLNZHL=+wu90Mc-q~uO`t_fy)BDsiW+P)D0$jwoBjqm@7lJG!hDnM4=QPH
zw#n2GX|aud^?#18Jieyui5FG6psiL_S5#ZoR;zTOMXP94TP@zc@B992ZM|5sNkUeM
z>>-;F5lIjvvhN{_$S$&y5JVyoS^U29`)fXP&dhh_+;{J}=giEx4=^2DHADDeI=8N(
zv&px&Ce!<;d#i)iaXniTeuqNu)-YG}-P?N58~)zkx{iv79&X)4;rRZo%jSSM2DUb>
zhUn1Nl+yrxy!GAbfEnI8{VrS_-TF5D;rZCsW(pgPZ~a&ev^@;Zt$^9fh;xQB`xuq<
zjb0bV+zR|6u8ij?eB#EabOq<Z7^94gCu2zqB)u4?Uw}bxMmZI?_%H%qg*{&fWAOkw
z0~pKSfaqa{h`tgM$nc}-HJA~iLSG2uyKbO`GG3yJwFt()RA(Q_@S!+h6l3KtP>5#K
z(#kr9kvj(LSVqZI4B|NBwQ4w%zzF7poM70fwDuI^nK5{g#OON+3#S=NyxhU2Fy>mI
zn99)6)SbpSJRch88BJ5rm(GY@403_-A64pPFuo0Z@Y#fUf1IOrTp^=?V&+ARXG3AI
zm{Cl5tTIL-mF?FsI_QOUosmN;<61@_ZA<DHAMb`<JwqFS#wNyVe*?Oi@k^lSbIb+p
zpTmh(#xJ!XZHyZfT4`rw(Mq6$vEVEeIvM3VV6TgDbRW1|jNY$cp_>t046cVUsE6bo
z#!uhF&|SuQD}3o?B)MTI_Zc5d!?k<Bm`8OOeT?IofPTo((B`q9ahU1~2N<4?x1l)1
z@DYMMX7oJ(=rCg*?UqLw))a`2G4i-DIL=u89^7_fZodM>J<NR{!l%8=Su}a<W2StE
zzWvPTl^CZB^JRJox-wnpZSBTfwiv{n`BEyt4lo<Phn@%1p8`sr%+G=xpkB=Q`OrVe
ztQEoGL(Eh!5O3zpFW`j_^VBkk_%idp1E?Q!H48BQOjNDl24X&Ff@_DFUnIhAATv<_
z62x3fNy{V5*jLdP%zWJ$l3~myx)H*e>#JZsf_a598b_HQ+^4fm$C%6MGeXhKwe#R<
z95Y}IEX6Zl^oRa&rdAEKlgyU;=u2e&^dUxnis`ZhFv-m1b#VI(a}6y*Q<(ozrtB=!
zs}6eSn9uwOl=IA&Xhyln?4hd4OUyeFP{?5FN+6QOT!`SBV{$h0&EMfo4)gqf7+OAa
zGX?1in6J>BUC3-If@l%*L^-@DX7*1<V+qrjp2<>X5ADgym=1bu%bA~q!qOGyx=$f;
zmHFY10IOhTY=#$A%vTiXt7d8r!i#InF^UM)F!P=Raa?E4+yc>B=DSKL)-j#;LbQRI
z6ap_AnR6yUzlk|(GrVYK{y;g98%#b$<yx4lXv1}r`8DMrTbV5@;Y=HI`)QbHXFAc-
z-@){t@pdvJJV9<Vqo|g=o5|P=3q8zV>40;u1EYZ5d(0XtTffg_^`rFxb2hE*`j}k{
zKpry7sLH6HX_^O-0cQFjym-VMT8qX(=J-q~3^BXD0(s2LvVjaU*HSUu6Xp^nxDn<K
zN|uf?UmXV-W4?0?-j6d=C?Wck={WuoJauBt;9?YeSce)x_Of&|>+EA4p^Vpl)?(TZ
zIJ0h1!H5gXI0b#Ktoze}=Ef4z@8iyTg#&Vc_4`Ulda!1D1I3dy!3;0FSk9DnKgfES
z-c*NJlW7j}W@Q$^H6K=q<0VjE)}2Ox`mwe&K*pc-Y6dg{SaUxEIn3G@3z$IG7nCmy
zV)>6i<OnNcCN4rS%OxImLs%341xhIE02S?ov5JClWx`o6P})3#rK0CHlEwS~2S8YJ
zXjOES#kT_U80)24dKX8typzGku-3$Zi)A@9FcHW4elASJvnEbM<8jvR4ftUbSg&t|
z!4s^XXjgKQb*v7Ji7W=4emTY3KnER@SnX89cbb(+FYjblG}UIEVV$A3LJBMDDI85@
zop1rlIo57BdKaH(l~^&fbk@IAQGbE;63wy~S<RG2yTsZ@o@TJHg2xM<<vb1gmsuuy
z@UmDRWkWKX)v+7?=CIOJ0Gi8sgEqu@tmE{}^L*CrG@ul)<~@LVA?vRcI8(&xq`*!w
zYkZU<ZzZfnZ$hz@)wBnlWh~8Rh?cWvo&mYS>M2L#Ro0sv*sWj{(sAcXmJj9Ys#x7#
zFkj7z-hiQ9W65YYRm1wU5{=hc(w{K;TGk(r(O1X1{sTxo%bl)M1FQT4fHku06tH(R
zv6?Bn+ss<$4ySIi%5;!vWsNO?OdBhcb|>wud#GZW+`-ZW!9*vkHyw>#tocI#y~Vmm
zv9{Z+_okq)n>BqOBzst&2cz*0Yw5>myvrJ)WOy&Doz5ZLW5rR>={~E1k|qxvti|-E
z>tjXlhv-9A_9pn<&zcnom;u%zs`P%uV)($dK^AK-G=^APTj1eimc1L?Fl*=wa8Fn+
zKY@&}?yF&Gl=Wx}^u}2E-vD!*#eW;*DQgRr={T_`(r>qi{gpSo-^+H)q91)9`}Rg?
z>}Lz8>eiWEL0JSB_QY0<!j*lUj<UG1uTmDloqe1pu><UH=~FKrY*PW$J=wpVhk_To
z$QPClvUhd?<q$h-B^tfiW4~a$KJ2ZOarR}u(E|}b_M%l7l0W;2BM~wI>_eXd^e}td
zcjydcSJJLEh`llqo*rSlQteML`yK}#hOkdjeLyICqZ>?wv9D2iLO6Q^1!yAJZ|#C)
zB>MyUE<zMLLJ!QNY`0C|j<I8Dx{79>p8yiW<{yBCSa$DSx|8DAbDsxH0((DwBj^Ns
z{}MEwWS7vFq>|V{&tcf7*?)Wvhm+ZnwEjEKu8M@nMfM$vVqRkBQnn<6z4tOmCi`6q
zFJERKc?%?q&HV_N+3Y_l5}d=<(}B=j_MI|d=Cj>Os5YyBeY^xN7P8w;LcfT8dla3;
z>_6IZy-L^#zk(}cH$H-5Ir~$3UteKQ$%px??Dfs)t6(pRh4+>0=e~kS6?+#YD5}}w
zy%^{<_Er=6YS_Ez%O2O+!F!=l%g&)>b{$*t0exSso-LmNv<CJf4|F!NWB!JTCibO#
zxZlj)Pes``*g7h3YhmZnZF!T;j{;~b+leB{ZR}e5VcXeZ-$K2EJxo7ZCwm|bUUab+
z(w6WRdqEWRZnHl+0LgClq(8ykWqVLU)X~chh=J%m_Di)O_t_hd!M6u&w-liDv8U16
z@*!Jv4jTRJ&M{~Vuw%c%5BrF{`zjg-*^0j*GQ^%U89qH`uly9;Fgu@W?w_zvevXSU
z!tR)c#!>dGchES-p6&%h<LuQgAWt3aZ%E&XGkqNl?&Azl+G0P)EQbkaPUUK7xNs6)
zK%Xn8t_3FCILY)fcjs)J49NqWHY#lM;9Ob&OP-vcC^6#2xliexgPd2XFyIhpJw55(
zoPa(k_;5U4hq^Ck`5^TCIF3V1P=Ah)N?8LqjYh~E=1iogBarhv1s8%i&C8&1gi}tN
z{9sN{C_qCvKhh5y${C@}Mi|G90`HL=A=Rlxaa!mFa+Fip1+W;7emh7kCt(E?;y7li
z6iMKO#6jc)r^&&C;z`bm+rUoZgk3}HX-*s+GDzlpbp&Hd<y>}yMjGcBl?R>W^bf$`
zdCsIMu$0azei7;yIB9>t#6`|ewD!NmS@JDVGC4cwaKUBHN=ou(arSaBh#b!E6e!8%
z99jU(JdVdGMc(o`B~)oyz_~>~R}p7^CAebFb}1Y#;pBzEZW$+?0j`|mL^XR?I0dxu
zyvq4wBS0%Svu?oOD$X1_0#nUlQD*TPXIVYKYB*8h;I4C;7eS$xb7?gi8#rYgC^T}U
zHaZ~E#2L8?nP!fJ?B3u!G=sEoHiSUqCg=Hc_<dSA_SZ1NHclU{R(d!bTDslg{8j*R
zmvftv0ll2tlxDfd!MS<dz?@;qL-ld)ybbOl=Tb7R%m8PGH`IqXZvUb0F=rOG9*)Vw
zoNp;;{DfmUi_Q^FIu&P)a^8=Fr(>KC#=wnpN<M+ZPdQ%SqS1-lPdD2hZvD$p*vq~0
z7dRL0OCzx4%6+sPjc(jCbeFhur}jhr0Qa~E-g|JLqlKp@SJw+iy||43N4^ho^Wx#Y
zAJ_RE5PxphY={PM!>KI(F!vheTm!kU*8((%E6c|yj&O%*Clky)ZUqV9w$NrUk{eC&
z_bBet#UMwyYc9a<F|M7~W6@lG37})RU(kaS%YC*97UH;VQjqvJxZk#7Xo=jPDA{_7
z`x_;MlDLMz2P?2SbEY$IDO^J#L{qswRGXZ}O&<r$dG5JqLDIRt(?Kq9%c-{UBKOJX
zaP$(l;v=}7!M*qk8Z)`??1#u@?vGIb%i?Zn0a!M-jH(-QxaPOem&+AALSqs4d0HVC
zb6Yn-y@Xrph=Vhw+!88SF5_;M0j-?-8qGylxJgt|aFu&;GC(W12TOof!+nuT0j_i7
zucEP*TR~y5I&SYo46vSC*agrAZaNh;Hger4mDt1`%!7qy?omo{wQ*mi(t~#HrYwMU
zaMRpqaoEZAEd=S}CjJI;i>s}J7q__v9!NL$4CTFhxFwXJzt7F3#s}OY%0c#VMPab?
zkh_wiYW>{NM{s+98$gxSkGRJ+Kyr{fJRf9;8|Ds!Pq@~p;6}K`$Klf`H+J1KcsRzm
zxwH)&=T4@e*Hf-1rO2Fke2O&g;RR6gaxbrM8btQ-zUKmaKTk>@Byr|FiGs)hp5Yic
z58i9E!1m;&FNUNS?-M`t9pqKrg~3C-sFk=t-n@q%@Yjd;cLT14FVAZ!rG)}{MJF)q
zAYKQ}S4Vgiu|Nyvae|={!t>k%^P#**39!R>ztA2aoHze>n26v-FUKgNdF$wAi{VX_
zfyDAybg#wnu2Xa^p7-)is2}GI$v_f#n`?k_f>%TH%t_vlHvr~H=B<!p*k^cVs)SA9
zsc)k-l{dK#*lE1vL0CG=`)xin&hh@@0p>i9<p%6@-k)b+@DguX0@O2j2k(H(<V~Qp
z^krU5I~1~bwh*Xi^A0)#EQcqcb9A}9<aa^xcrh6mZoY$8K}F34ykH8J74n{^*l`(e
z9z`e0dEZ|H%oSck0WQ#0o`eTW6};z4VX2Zgld^_YyaimCsOJ564xn|s?exa0=dE;s
zNCQt{07@fID1l@XuZj{B&Afgp`MbgUfR<w|JjV!S*gJR+DTCC>E2N_4F5X5umwk)(
z@FS4hJonQ8?dHv;RYwnRh_b?Wc=5l2JmB>t;-~E6rBK}RA@4^zw9(JYe;1Ypcy3JC
zeZ<Sz11|=7b+l?2;=Ni5lqbAh6yO=*c{&z>j`IGXc*Yp-0hPpz^XgXOB0S~&OdCd5
zzTZBWaO0mp4t;mNo+AAR_+ObpJouH@q3+55S`HB}{xSpX9^}tzfaD?my+~ks^AAw4
z*oXf+m2dg-_jtomKYk8vJ^cBC3X0eV@E_7^FpwWjr)q=v=WKvE!XKs>ZZLno0s0~Q
zqjbxM@n58gHJtB3wP+FiCzBu<#UBjJT8*jf*}dqC;q#vZiRTx*4zT0=yHu&1z~4xV
z$`gE>1}G=_QU9PZk^eJRXOmCyx7~yjN&E~A^iK09y$iR`@B?U3n8KfE1xe+*d;q;P
zehzK+&+>0A1UbjQ)B~^6`ELmza)B>#sGxt5|MhlYU*ap}z|P>8e2-yg@<rd{!d~VN
z7s973{tuLk%jQ?p5waZq3_GrNE?-11o;-dmRa52j$LR(x;NPHms*vAEZ-pX$2L(ur
z`BK`-mhd-FY`v84*#MC;{=)xPc$M?#eh&Aq@DJ01<|_X>MaL`n$LW1t&G)3N(lvfR
z<<x5U-LIhUI)54!1=sRl$M$n_9e?BV7(@d<h%(%bd^VK@HSu3~4ARWM@&@#7@L!_6
zT?>D)0+_A*pJ>O_#{cX?I)l{CuW1I`$$vt};Jf&#Oeo&s$5PzpHb12W*xmf+j-#)K
zzu_Q8afh$_5+c3)t_kS7$A7;XgSpRNMf21H{vb^hef+^45b5X7It`Qo{=!#59`Rf0
zJwM1VeFgT0_+tF@j>(Vt|GkV0HNwxE4aHG@=r$;h@wMe3<NTNY0(r`h*#mtiLDFa7
z_6U5aI(M&N^=>Ha69iJwcfVlvVqiN9st%*iMKG9+K3Bo`>rikL<kQ7>7ceMdctG$@
zD(+(s!4H(J|H)G@aXBuHm*92>6b}m0DYSD)V5h9Gx8P5zo%0cJz5wwR_=*AJC+MTc
z$X{Tohlv2enn0g5xR0j_p?5@Z<qp7t1@iMCA%f0{Fdr&tG(s;-@cDNj;esDLU_L@n
z_y47-VA~hChEamM?!Y`MxU(AEF~KT&@k9&e(ajknnD8?^ixpIl0xVAO$0|rB2;P1f
z7ETC^v<o{a=yT99v_wIyC$LWm{-n)olHd)>otzfj`x)LR3xv*qIU~4EE4CEDcT_i(
zDrj8`$uz;8Tj)D0aHj0_Il%>rf1ekW&@wJvpj6;GT@dh_0d`T4u@rij1Q~5W$q;n^
ziM~w1R5c}gE(=Zv!hDus75!S-f<ueoevTl6iYsyjipLPm6PPHRkS}oa0aqYc;sd=x
zLC<Q46bZ6lgBQgDF0I%~1jRI2mI{niUQ;HhUI3AD!Q%H}zCvJI1X3xOO^cN(0j>z{
z<7z?BG>BdkFn@+<jo|tPkn4i;QGlrx%xQq7I)RmP5%q$?ad^=n5Y51k)+qRfG6YS6
zXJ3OtvtTAA_HGCs(Aus=;5P?jxhY7cH*2e4<a?;M2@14OXcr_ZF~APN9Ncn_$(@2P
zENJZ#yfp!$w*=Qy(b*%Ik_PUM;2WxJxhn{LA0oX1&31s^6O_{%=Ye3}I)L^G+#bW3
zhk_flS??Eg(y9Fc!LD{(l1GBpuYfWnNbG_7W5K!+s1FO)bwK2a;4DQI93z516!3dg
z@Yx*5j0>76yYy7hML}aHq0a%3y~5vqhfn*22fqimU)cN&6rF|py&>r$bUp-iH=*(p
zh`Vq~D*Qblv{0nPLwJE+o1Q}1Hy~cZGYL>XB%DGyVQ=Bo1+eGi5DvbGR$t*S^z!!;
zzCgE^zi<`>rVa}i%>x%Gy!aI6gM<vKQwbHyDeWC599<5DaA6^(S|fyieFhRK47&)>
zqe2C3WseDS8UY<Gj4uFKj4-SbqmLD?plZT6VYmV6@j{0iy?+vf272wD5bjR{%t_&E
zw75$YF73xCP6_=&pnqC8J_Y*8Ldzp4o)LDYfTRf9sD?UK_$41>N)zs&efe48yWc}E
zT{!3o%nQOq%Bo%zPNS&nCE><-(8~~}Qrh9NaJgeS29qTmr!x@Q!Z+#n%@O|kJ`Cmx
zS<e7FPq;lDeFegLdQuC8@6cmhBwUyRu2}fumoQi&G|z;=QsM7%sFw@(QGv-7p@VAc
zuL@l);3|byTFF-l7Z1VFYT;-zMtx1V?Qe>I)Ceb2VNI>@tz?iop$p}B>xFlTGzfpS
zVHAzRTuM|l3D;8r(hcFUQed|TeO2hYDZEMV)K=j<ntI!WuTU*myYLT0BPVwX_fjsR
zOE~>KfZY=Ap;+4;VaRgm-4(96N0o}bLKiu_xF=*xg2sK}<6;cEPiVaWw1>jFm%;T5
z-=_%Nfbi`dfO#ZLGJqQtT4-@LBs@g{$6?{<dl={w;gW@LZAAFw9gtDs8H!tu36IdB
ziKoKh&*7+(sJs>)?h$o<H3`q(UXhqeH1>%iJu&+IqPrX5qO&NL62NYv9;)JS7dd<(
zazK<wAp;N5FN;AuMgLH`&`T6@7a|8mf35;KB+@*OL3oS4rTn^&Xj27T^A)+%#ONo=
zs{^#Z=wu!w14Li_3(j#^bR!?W1&X|=kTyufYk}P(qJOAlC|DG61>+47t)Byfp`us{
zQ-z7*wHQ;lXv6C;5h3!Tgmt9ozkkseB?{VxzN4az^rAf`iYx|+7I~BcI!07aYpht&
zZ<&yc6V<#53-JySj|Yw8qSrovrwO9Yg>e6bXaODHJ}KHlkAI>l*A?6;Q7^4`lSF39
zMxPd)Y=>U5=&MywI3p^x0yIVR<u{N_6(vwa>YOOY2MXs!^M8e8y2y<l?MosbN{nQP
zo-x9FrpRIG0-G)RG8Y#kM|6?ur*cJm`r&th=rX-93q>!r0<=gp|0py{MZZsgr7}_V
z3YaJt>1at?A!=Fzu2M9}hkBK0Q6jEPjYvnEo9m)elxMFMtz8NA2GKevh%}0hQ;AcP
z=m*CV$h3%hPC@^sXysy{wTix^C|R56bUz$!7yV8LGCD-FX;s%Ll23+6mni#v4DFU^
zM-E_ai#E{L0=h-dq(J13s3ive-W5Gr1g=-)L-DYCqC^hB?u%ZaS4N*`B7H3Eq3E+`
z9Kh}uU7QHe0Z|lv#Nv@CwFk}&ihdKJZ%EX$9%zq6YuBQ2SQL5!B2PrMIv5-gRhIyC
zRJ8hCSQ--*P?~03<XH~Mry_4P`kci6CYawNzW61;_KKHWhlsQIO>fw95r2G()^V=l
zt`1xTH}PD`mb!~Q6yOes6SNTZ5Km8rsHgZ<Gtdr-C(yF&koY03wY<euY*_LUzcUGa
zzG5Cd#eU*5FGIv%Jh2!gKpaC4e2{oUJNk}@kJExCSp3E{D1?dKpU_vr!o?CQ3XTvT
ziUx@k=lP;DN*qhK$uaSR$1oo)Hc-uZjF`0xeX(M<Z_pPfeurN4@#3anaL2^~pJ9Xv
z;%3@cpAZXa20tm@K@s;faXHP>XT|RSpzoZxn~BEr;u$>{t|MJMc@1DLh~MVI(nax<
z8L)IoJcafS8DibD;4;Nb+N)d^_c1}T#5#Y#WQ$ur2gwopjKb|)@rN|q=85ZH0%*SY
zM|YSn5DOR(DHK=GLbXV2q-|fZcyl|PDG@vQ<4!1bh{LI%wM_hXA2iCvlQ*FCidajP
zLs!Mw5fH5q_m-fsQp}~g$0~8b%Ydm78|Vz+b#Zt&9IX|<a1V_QVm-|zjpA=ypwJ}#
zD-(^);&95%-4J_H<xq=w^#mAd6K8b7r*^SpI+ag$h~saAbc)0KAlfDN4ubwI@vZ65
zxGnCc_fWU^bS_Ab_!R9q?uh;Aak?w6@Q3+c@$N5i5$=g)l#;wJ_H6{p1M%3ekn9u3
zmVi7I_Y!8m*!T~)0kLxuL>`IPI;!B!pg1=HokQYJD5v;Xyn(LQu(-V#pijg<(ebwt
zv3Vc*M#X0+CpadaHiXMPE^ht+BYY}0Q@x6l<c0_$dnDGYaC@&Ll%BDDl6<-(`z1%I
zl*U<dgq}1PNg91|z*QnyPX!Hbl4yFk+$Ecr!R`Uc&SseKkjy-YMo&q|6*PKDmeTs>
zpk(fwaMVX~n!?1s5{4Qgei9>9X!%QmBH%@UWGbx;4oj+~fDV*Q?uA~E<Tgz^M<gD4
zkYLFs7f6Ok{tKpfX{f~ab%=&ZGQNglxWttfo)Ho`r41t`+o@P6O0t%+2uCH=UNC=5
zqR)k7v?TEeU}7Yb--ddeq?5kr7B4wRbN+FOssthllJtL}cS7<Wl~N~4u0MkdbV~AN
z78H^s53oJQS#pV-Dn(Kx(KMH(O1$Y8O_Q`*z@3%Y>ED0ONhVRo?7U<i?NZVu%M}2<
zAi0?hy^E4SJ`^rVDp-)rkTfj<mno@y9+H<O>%V}(EXjpyFrO`XgMz3z64p2z&6OOd
zXVZ}<SwiXEe2MN7S_>o_oj?jDS@ha3l02XoRI%hf)%BD}UZ-qasl=Pk?3YQ>&p@PH
zGK&uCT#=mff!(W;x$8kHBrntXuS&_YH=s}@ai{fmwM0PC_-m3$_2{dS%=HFW$CSKy
z3fT1$-Tx!ml43E2)+m{sfyO3DH}y439#UNGhD1gadW+=vhiJSh=}m{FR!J=#0Be)f
z(z>Wa;x!SMq*L<VXrTD72{Rp|l!1C6NvDWOpG1%W?jeQ-r}`zCF;E<kWKjt0k>v1Y
z=nqN;z6BYQNHH@`9+m_s(f33$cMB|yNc`!n$fzW96B@@PvvbinF5%JP%BPZR1!&wO
zjiJrXUa1QOjrU2PI%o&wB4u^KlB?A8AzIy}?=^#Smo~ou?ts*^3B*JCTq9iblumyS
zoR{=@x<3v|chI)?ko1Nx-SX0}=sbt7bVWEs{G?B=Vi5k)4=LXeAl;Y<Lx-jHXMqwZ
zy}J+=jz~q3lne}(etZ!6A<~LQD27VsDdBgRw3EVB5z<_WdqztCrmvtJm2Rh{*D>i@
zKV0r;X)Dzh$4P^~g?hX+v<ZF3rOPNDaYou04ofLgjSuuvrNuA8i!^CFy&KO;7mTCv
zoV4~=O2%K1{!8)yi&8Fyxh_fLUVvhTG_4-yGo@aX9=a^;<^elPdg&(^%$C+tTslX3
zvlV)|(${G9o+rIl2fO*wH8Y@4C|x-f3PsXSo`+<ybW#bp66u<c;YF$R`EW>Hkq#hs
z<(Pa`I+b3471GuObXH2MXe(bOjixtkwRA0|O|D5-)5ftz`tc7?ye<{fqNi5s*bRT{
zq-Kg$)JxSzK^mkdC`r{QeS0p{o22vW;bF7%Q33RBNLinPv`Bj>bbV7giJ~x$R%zK>
zux--$aTssAw2)SZ9n!{|(C?HsQ0li!s;52eE$NjRz`iX#_YOq5rEb*MBb`Ne$sK7J
zW{SyorT^rC>y@f$5q?klMJpQbOMgEF@<6(R0{4B=3+X_4C@rA~T)#t_bPJXSq;ESx
z<B{}(ZpaKucW0w>NGjd}w8zqX3JncQXWoOz6R9T~Xd}{PGW-;y(mgZa_L%eyXXuSf
zSC*jfsq~F}c<3Y>KZm}(vSqXIi#W?(Sc5(n*>w7qU1e@oh`7ldMvCjX%U=H%Xa{5k
z{*dvI?W%-^r)&?!M!jVG2ADr6Yxf1(Az2iCi_Keh!H7N|*{c6<O=Vw-!THHvp9Rnm
z*^}>q87dQ3f`rM^e?nilZ1!oWN60b{p)pdn?k8M?DA}(L`YDgfSd?ZxCiAKR7cFB_
zVRnqnOzWFi*#Ua|<7Dm6p)Xz*OjSR}W#9h^kpx*2ZPHH2#5RbWlzmUZ-$dEV|G~pk
zvh}ZlOOnN>L-MpNa2)27WuwPn=#0$W4SgvxpQR2AEmig>y>ZiIS8_ql%JkjPKPM}-
z!{B*Y)&g+pvOg%ec|jIUA?S-TCn^)VB%7-NOor??nzS=zKMn)?vh1)Nl36lWihX6v
zLaEd$M>dU8BDu0g+7aZ*mT(}FFKh9q;7Wlkd@9h2WPc0;yIA(@yO1f7MScLgrLxV>
zK(S0#xeOZRGUbmL#TD6GGtqceHcf-Z3RynQOqH^)e*vkIeL`h=)v`G+K>eDGMe&GQ
z*~A6ttCP*8Kt#PvLDAa=S=3EBhTSMTb{H~EvS}@FxLG#i6L@h$7DXYC7TI4^#d%X!
zMCqkgne`DG+hh-J!^3vjs0Z{qWXYr8I%T62ap{sJ&@She>?iuR&uy9MUx;+ejIYA&
z9vRCGV0UDdU!m`=?95saN3U!xRqfrAb<#HDzU*0w_dbwapv7gMERD(oAIj1x4%shz
z=P^bxAXC%o`;qL`PhfXY=JYMdkW8@#l8<E}v{oCI#h1bE6WN;^K}KW)f5FnI?C>bO
z7?Ztt3n=5VhbC}O9Wu8{bUMkCDA2o4zLknY_REElfN_?ep!yRx`Hxh#<1XJD3QGs%
z>n1|cOaA^=kc09i?(qJQeDr6Cc*_y+$5SC6od#!o<?Xa_^OL9k49;I(p#%w#9}&UA
zVY!JGfPr#H`^R8|<kIgTdPFX#W2C|I1u1|Dk<X&ZK2)Ad_0nPTBwECW%O?)QV1)c_
ziV{Z3Bk1;slK)Au>!b4GNAU2N{7-uEMa%zv1|&w_^epsZ<ukJ|q&Rs#g-YV(>+Il8
z$on13;KoTgi-OmQ@=qw;d0Kv+4sa&Rf1!oo8M&B(eJS$yGr^_GCsE!#P2Tzv8qdmi
zzXnIo$)BYR?s@rAZ#1UM-xUDtf;?$4pfAeD3W0e^zF{G_40-CGAenNZFTA)c&o$A@
zF-u-a8OCh+XENB$k(=m)C%N(wdMD?}`@`UVzC0rveFgGqX=p5z-<S$#isW<N#ZOr*
z_xm1bC31h7rAy_(P9SA+CS8kixr*kgEAoZ0uv;lt(9Ww$9?nH$wcNd&ieawF{hon-
zjeLO0B(BT-=s<D3e3&*L4f3m$>}`}EO$FC2A9aNnJ#y1;Fn>p$^#qc4<yXUi-79ZS
z!9}<yUrKAP`*I<bB|eaM(>}XTe&r8XcqspbA|L(o=gZMIAm<}==a~FRKHvotgYt|>
zhz`lytKt4*c?9`AEYGLy(G$7yJ7AB<XJ=qcqw*B`n~pKLa}4yH6i5F7+8)KRc-Y;m
zm>mSYeTq;0(YRkR#}&j`v1SkoE{ah(L|hdyRG#Ff*i3OXhr8mXkHH>LEG>X<9*RvA
zsPa@OIw0z$m`ll@gNhWI9}g+qDf;BCFiwXTK8oX1+v2O>(9PnfIK%^rzrvL^Gy#g_
z3UG%N7wEwWR74L$AxOcd6vYw6)iIz1D~dP6LWo1*!39jH;y+KYVG4T|xNt?N2NWX|
zztB7xsc57Rc10<gH>2^WqMmN3V+w!zNKUjuM~U+oMIAjqv5ME|trn-~ppRa}E1s^y
zSdJ@R>V(|{#TS$mKcVQE0QHlKi8+u=R5;8OoH?a9K+{K(;uWf}IjykJRxw$Df)hLd
zio};dQWV!tLnKvE^F16*Q<T!C@~k3zHPFr}@+gyZUa^cKi0O*?S-`%a2nqtZsHoi!
zyO$I%(2_4hF^AMM6^ke#bXnozh=4|xVxu2gvlU@q0W?Q3ixND!idSxc<SE{xI844`
zLjXotpm;)6Fog>3K{OUA=2FdWvBJ~<>=K2~n@}iKu&DsDOz|IG?sCQCr7&Nih@h-M
zrQ+i=;Hnf?uLG=FQ8vK=jcbZeX)3N!Ed30Fxvm)c9F4V#E_aN#PT}kV#d<~bZkT9L
zB=`cmQDHra#wNw;<v?pzF#g7MzM;_2;;>cm`T+Xc6uFcbZC9*&8DJfXF?xM=D%xhi
z?JmV%OTl$3x?iJW>>kCb70|z<=%Fp&J;f&4P2N}Rr`XN|#nivh*RPmF36lYZiB48L
zQf#ETdr%SI0e^=SUoAx6W5vg>fg4u5wHw$^6s0uFk0?B8**&T_N0p^x3g&dUHm=}A
zL*c2S6*X3l$xh0+Rj|89x#>IjwpY1|LJ0emZFIbGzw(=(@x!<(r&7q#P5EjH6y23G
z&SFfS${i2jg_m**B{&Z%@2rFRA?4JQ(DPRQO@VwL<ug<?<g5HH6K?w{m(iD?{FNbe
z+&n-zhYNMbVdW)Svjr+W=-vrZKKDL4k0{sBXODuFHyXi(C|7(4pF))$eZUS={!U*N
ziB!67fr%*P5Jj(!DmTc09ix1U0%Nhtos&W0l(kdP7q47whik``N1g?jp!|i(RZl3V
zOoqZqhw__0VJT60a1X|GO4-$k&LrhbJGj%z&fg)EtPEQLOJ|hpLeZF_y!tIjs`3s^
z{b|bIDQ<gKnGgpL)0K;;tnh-8MQQAd%H^>T$x$x&5hKf0Iw&rXr~LRByvSGfPC{dW
z($Pi>g+gV06%>n<5-|)GE4>#(u|)Yb70;F`gD7cLri{FUzH+6+8RUwxLjZDBx%59+
zs!$Frf%!`1C&|FBQnrVKR4YBHfbqJLLGw+m(y0k3bxN0XG}bFe=<U#;jB?N?uNsv#
zS3#PTu2fOmtlUb`*c-}lFPLvtF024)Q@$IBi_oq#{Rhbo<*&4a>QoNXPuZnxrqY^Q
z$^y!Q+*YoN0oSecodC(Z$_P5h)vFxZgmK<e{zgfO`^qa<VCaGJlXvO)>r?*6MC(K4
zCK-I|SH4#Yg9FM2I?Fz!+)Htk$I6*sfD9{*G?zV5enCaXBg#a2(npou=b=8PTtPK-
z<H~(IVE3tV8|4r8s{XnHy?v^;Y0lrT+CgWeT~&+a=yOx8nn?RUch%eZFzBgL48l_{
zl_x!F2UTa-;CxgsQ2NnV)zX16`Kg*I`FdEjXEOQ%RhPd8c95#f59%SRdfMfLs={Z$
zwJ=qwGYm$n?sB0JqiUtZd93PXDzS`H9ohzwc$Hrg6@wmEO`zC8f@+-#PMuIqm;!?*
zRjP|<OjLbL8{JbX%`%uzQdQ4^$Z1vfmk>!-O%KNC&#30yhWQlL(j1siRn4UkO`57>
z8T8JoR#AxNoa)ABFnC^dosQC`t1eMk<ATaT)xD03s!|a^FR8-kfXz_#y$y{_RlFM<
zzO1SslBHVv5j3(@Pr`74b5(PXg3D74_d_9HHRm~aQJ}g>^}L0uKWMfrQh8EBxLEbg
z0MtuVvGZ}&OI3AF7(|)MPEo#c6?Z?>uQ*gczYX86sy0)NN`-2_6R;~)otvOvrFu^V
zjcV0sGGMN$(ssjqtx8&f#yZv7U`W=h91i%~q>95Kv&qe>85Ebhq3RZ*u~oH@R@QB*
z_I~uWt5S==b*T0%1=p#X;RTc~m1FIvFyF1J`~sv$^(F1o@2FxZgm6zKpdkN!Rl^o2
zK2W_cMPHw4E7c`ER2_H|`u!?RFd7F{sT7_YQYq$uJXTGmSk#EB_6#hIs(yYSl4Gi@
zF}UWWZdZcaqaLJ^`@L$GBM)P8RtHZ)tBX48J7Bx2mr*|4P3=q(CU<pUG(--lt==F$
z>V<vi^Ho1baUVbRgF=Y-t2a^2VSrjhxAkE)ht|D;>iKiweUQ3?icpWJuiS%Vuv$Y3
zA?kxK<Kl&?Lyl5#GfbW025-XEX<tJzLf!KgIwRGcf5Vw5wTCOnQT3-6fqhJEjzV9w
zx`VdFG3qugNUZwiGMI={7uBFIUi~q}6OXHl=b|q`oqPaZoKRaSIC4^bXaXEfRI8qY
zp;PLY&Qo$PNquStuurQu&d0S(R{!)86wj#DN@%30zw!r{s&1ycGfh465}Y}!PN)WV
zPJQws(9Wy<y@8gl9;E=t1$99P%wJSzpGV^*_11EzXQ<mR0y<Ou?@JK5tp13~8MD+^
z^C<q3t)BA-T65G1G_+i`flig?sV8f|<*T2&080hxEzaNy)wTXmEK>h*10uz0uWU4y
zs5em!M5(%&vaV(7I3KuOuJ)pI`W5y30C;g#9Z1zx73%Z8;HuS|D8q71J(K1OM~%Av
z0$}RY37%-JSARlP6Afx%8~koomrw@$hMMyq6kF79iP6}m-tq#_+SMEl>~^S)#V~kF
zeUdi8x7D$ff9O_k_yL$bYUUw`+)+ztUcRfoN{@E0T1DZTd+IdWMc#L)M<@aRKwWbb
zFnwzCYxpT1sw1eVW<V{v4fBuGpHY%-P_5bsyF==OKS2Mn`kxPAa9I82JSaR-^C&qm
zqP{@^kWqE%1~iVTC+VR+t{y)GOHbAFDfs22c`F%xdo&a7qj9gsahBc-`!ru<fb7>4
z($2tH)9r;$7tKN{U3AqPply+xX6z31-8DNnaOQw!(H3BPXf|h|(NojOf_X2^_%k2}
zHP?7>?T}`6DD=EF2Y-X4kLGeD8htgteGbk~b7meS{WVJ+Z=p3n)7Jp@ux1NIMFTZ|
zQ0^;8GfI1=Bbulw5DC`Yeh(goXbR85e5hteB<zN1>aW7laLq0{pB14=rH46EbMIZ)
zjnX{YhrXklt@H_uW11wY<crogR{=UkQ$m5fSk1{adj8@xQ=*_4ugRr}>bPbPg%uMt
zpVDjpgyvhC15av_Bp`{JV|l<nrTJtzV3IV>PvFdHjhM=ylQl{y6wYXZegjyF#(x|l
zshZW#KqO7`>R~u@R<n!(5$80e*KrZfYi4HA->;-=LVpDI1<l->XuYUOh=%z~8pYe-
zGBgt@mzt^3d;#|_YgW>tHcK;O3~py@-lLx>M-xiLExDTisGuoNGcX^0`I^?Juv?(1
zmV*>(f+?_Eq`5`q8O53*$|jU(6xb&_CYNdw1L0|zW+&Z&<r)dS&aP<c{D6H`^JEr=
zR;3xF_-D0d(L!+7G`1#iHJYEh;Nf*m4wc8(YW98r^L3heJAqxVaidscgJ$zj=xfwS
zJz%#<b1VX*Z`MRnnZymv!WW?6XwfiJ;NnfqXPcnds##5|yEe`Ei!jly`H}_w4$XQB
zB6n)OcnjB}OCzT9g10oU^1<EK<nM$+w<Z&d>B&8s>FZ(Qj;3=v^zLfDI|@s^ngYuE
z-_vBSg2;VM76l+5Xbwa}vd^J8^#@uXY7|th+pp=R7w&*2ou<1-8uwYSG^oj?Xx)(J
z^B2+gSfisI#jxhB7U)0GY_vggM6;Pz*rOUP9h@7}{Aj=x9oH1l38SZ)F{)2;(jH)-
zagVlt4Mw(KyM&S`&RWMWJhZxKo7+HKwTtGV)lJKD2b#NfH`Uu6&?Ya0!yekU2@vtr
z&Im-Kmv%Qj%?GufUjglqwyhP7-rCs|+V#;cnvF(Z?F&@r>Zesugvehz)q=|$piM2n
zkPd6zC;=X*{ma3EOpx~71sKy2?Kc$V3)V_Tz=dcpoB;{dzD3ntVcNa)?a^@UF(VWr
zv}<BuB2qg}k^d;|GOF1+s{M=9k7>VJ0@tFo)s%yc(cYSkzF6(49{hxHT6+yp;<YbQ
z*yp&GRYCEW1nv1B;LQnbGJOW&q*f3J#YFALG?kvx{!M$HB<-&h;5x1SmUjCoS}iT)
zQndz(L8ocoX$E&z8%S=S)28f&hv&7@IH06!o2LTvf>!-JxQp8Bc7R>dmam3FhSqoZ
z1w4P5+UvAg%GREuXDmlM(g%{O%^ZVI1=@dZ!bG8VPBKJ_w72M%FV!A-1pPAYE{Xt_
zYpW@TQ=yGjps!LJNrgUD+SzY_G-!t;Xl&Ga9)m)Yw)YgknzcKtp>RW6`4N2vuSI*0
z4vpQ^-u?}qwracS)zPM1POHLp?QYtGcWA$(>8?|oL($(ZZI2A(mUeMEL~d)x7Q)eP
zZBG|Sk9Kt?`tE3#Qn}DwZ7`Mo_G%SWba79cL226iT3Ij5KhW-_YwzgOZXSeh54H7F
z3)`<vppe#pHlq-tkF+nepm9(eAp^{i_E}ouj%at%jX0|PHv=ML+CeV-9oGt}2;r%A
zUNRJ%bjNlAbC0e)6McJi>wV#qi|)1#KDp|?`v7`wIx#&|?hc*d3g`jdIyw*Ip*!~s
z%zNtcXvgQJTecdFhje%8hVs@ep_B1Gy4hLyeSLK)F@W*Y&D{cZe_hHs^abeZ0%7T}
z&YTC4KwaHC=nK*XtON<x?V`yqM5l>^hoQRkBw&W=9G9t@G+Z~Cs&*rFcj)A4lrCfl
z<f!g2Z84*DgE1Idj7~<G%2=Hnz1-q;Pxk}nxbFUbT$u!&g@VT?bn`rba#ELc8(flZ
zbOF>)>%P1Nuw>nGnkLWa4pU+_MK@atkyPD;RW!6T-4@D1p4DZxL-d^Pr~BY8=-L`E
z!i&1Wn-IOEduuu*Gjx&_Aep+w323~m8xMS<pYWE0vlh<e>E3IF`F!03ic=Nn{OQeJ
zs7qXez9L-+m3I{DSZgqd5?wU;TdLdtDF%N<w`COeuIgS(0IAUZLq$uKx=HlC+A3X{
z5bD*s4nJJOYr3UrXspqFtb+P=-Q`8_rB-*}LCe89-KupEt=H{1ht5XbbvjPdq&rDB
zX|t}u401#FXbNCjboWj`<fg8Yp4(PkARX{+)9tQ>_wBlqd*NY+ZUzUII(1+6ps`E$
zQ7S}k>G(0wyRFNc2hy!evY@d?R~G2NZ+}N;rLvN{y38<i_Ua1pL66DzbPXQx>AtRz
z4jw$zO|Js!*OdvNFrYhq5ax$;-_id3v2Jk{1~IJbeHY}3?iH#?AJMI+J7`pA;6v}J
zE?^g+o%DT6A+krmei8<_PcK|c6*~L%A4THoIqQ39o9?22M0b#@Ui=q0H~rU?5O&w!
zy9t;B`e-X)JoHQHjpM2BqIIB`K7SHGz4by0L;C2CP@TB1-en_*pT6cHyztkLP^>OM
z@2vyMVZD&@l!5vP++B{zLHZb4As^A}Xxa$Y4}1cR5Ph!`WJ2|^RK*>pzvl*n;rhTW
z(2vmX8o;n4^)AmrAxdv-hux$4t&~(arl0dQNSyxV5~#=Pzi5HpaeW?@`X}fUDN1%i
zACwLCllpTMoNy%SA7r8Rl%Dws6qEGM^sVC4`n=<iN!I_I3B@z|nKyx!qIY$M!Bl<I
zHIOtt=UI@m`oIK;oYN=KKKHyHw+yCk{a4LUxS(&{1rrxhm4UuX`j6;fe}?}5MbVl1
zRsPVs?9k7j2AZXR<unXt>z7jXP>w#4GIqIo(KIyX>95J5n6Ljj2QUTtQ8D~2)R)o%
zp-A8U84MQd|9BPyEz$o|1yZWdWJ0n`pV|b;a{Y4@x4EK!)eT@*_1{ubuR`BXQ)s2$
z!K2xuN*_SklWKh$O~KdnJ~Xq`=(RK9%yqqIE(Thw-+2*Soj!yD@%8$5mV#^0?<7YX
z^)8eUZqo0jDWzF|{XK}>(Emy$u`T+D-LP;|zlP#@t@{6{AgN71OzE(8eVL;LtzG&c
zs;{`E51)z7+xq(N(b%m|pl{do=s$V~eRuS?DG75|pF)*{z4{@_Tinw}S7D&{^*>S=
z@_{~GhcWf(lMN7gsQ+dd3jO-f_s}??SH1>+hxDB@A^BLJ*p9wo{hMV}A@@YjBJ(49
z6YWAr_5PQkKc=@*Rm!;j-vtnTs-H$_ODDq$$~o;Z{6S%qy@t<DL1drd>^^Y&4Q=P4
z=W1B<F&f<rS;0_nH~dcHJz!wcM#jV7!GnmWq4RHe;bmAfk-jB;(6Da>*h7YW^w~de
zLo^#c`53&Y3f$M=Nw=<_Vb2?Y@i*A3ArfH7qgdZz!zu~{1{w+!kPI^9m!t29VI$1~
z!G><C6$vq9(>E|e4N<fj3^T;g>MGojL{(@}2GPl9o(Vi)#b53;OaxH0!BB|q7(-+i
zE>*1I?L!!NoIy)V?07>3J$lCt@63Wof?-iIU{4s<(TSy#hW}{(NHjcPL-Lg2nQt)E
z(}t@yaLI;uX#;u2V4x*jieZZ!(5Z$WsNgltFx?4#XAPB(YS43rDHed9H%uFaiF8Bu
zW%zW#F#J2X48w1CFt|*EPbnHN8>a6Emt)w>1<5tUP{1nB@Chv~@(rVHFi~KbvjAM7
zVb}i`KZc_L5Ggh+<l@?t7>?${P^qDwvQ=e<%P-R;Ty6+|187$aHFSSpHJqi$K!qVV
z8XA>`H|U&LmBH<In6EZO{s8Q2hIlFrsWF_KgTCvAzDS_e8f0xisWZ60j=p+BCMBdB
z42|<)q0!*83S((9#J>jUX2b84bGu;}_=zGJEe4Gpc5fQ4P<>Xb;b%%?wi$k)HFCS5
zf!^O8hShsOIt{mW!Tc@5o0~Dv+lH?F!0t9|oDaPo!vuPd-Z5O0L*%ZZ{0<s>4f~4F
zc+cSVDxA4*xJv=*2ZpGb(Caf?okcsThlXAX{`DJ@scd4vP)X#GAwdf-1`U61#$bjF
z#T1`^Y}hdbZrCtJ(Wobenrgs|7-}8>bky)7HI5lnzPL`~hVSW)d}?@?0Y{yT4?NMh
z#~9`U$-TyQ`bG8`zq<x7$A04ot?iwS%lmLmT#P3x(CKQ#9|Yh@GR`>zP<Nvx6x;#h
zgjXQqVGN=*qo+|rD^D-uB#KrXGzOf9$RVRY-A~@eVoJvN7+bEP&)2w&g1UajWt3&}
zH{L%6%mCw3ikuvF7&~{NHPE;<2^vAh36w`XVqEHv(FYrETmTnhREA(Mp~hHx5r!EL
zQJgN^xMel;B8)#cLo(8+pqVPl_^A_qrlZCVsu(zCjM@s3XrsUi5@Tf1af(>uly*qQ
z8Q-J?ZM@O(>@NU4Zv2Tpg_U5;ya~k<MqwoyPa3Dv_umtZkt+at%4pDnBpDYx0?cXS
ziv8$IHl7H?MLc8tlTxcG#x0M5oocK`iNfS_##iYze%|;M6_TYJf1|*{1!F`a6fPRY
zolv-B6gemanPD8IKOV_6x_*V$%f=Aeykr^wq1}JBaqGWuCdXK^6kM(`ycr^S#sFHf
z<{Mw7=vjeL90K)1<IazOU1VIdA6&8V8OjHg82N3GEHxH<3ZKf17yUuXjX4=Gd&S89
z%K@~j#y2P*Ut!Fl-AARd@(++IV`DB1RvUx&qVJl~pWY!g#;sa3UN=6a60Ta~q#_us
zGiD!0U%hcAP2~;7FT!vQ8;y4c(AZ?u`+#dUo~G!?4deTDAT7pCB6xVyXegx*inki4
z`~^?jjN9mhO1rW8cYt;n<#uqL#v$5}br~Dy1MQY^gA4j@8-4%(mNHgR1xt_dgCvOD
zF-mp;<*xCI6mY#phc_(UGhY4$7yrI-R|))mV6;AkhkeEsRWSe1xOh4p6X-XZX$3oA
z+}91XM@A-{l^8T8w*zL#*vf>)V`K5_5E(YgDe3jZC~Jc=BSsY+w;45Fq2TP8ap5AE
z7&k6=h2&G?5Pjy<$#nK8yx3#1Yy{X|6Jr<p_L)vnY<9mXl@_oLSJNQXvALO2Xx4N$
z?Nh<w1E!<S@WR9N*59~=JWVaHqw$dG5mi)qo37Ao>0=VFL7%_L{TKKYV0z_afF3p#
zT}5M{X^75m1ex?_(Rjo(o6d^`o8Ei_V+k?&eGF$pO`Bf@33HgF4<Q<E;_QS>gvnEe
z!5lT|DXV|X^!h%?M4P^+3eFhQ+DLG*rV~`m5NFbDgh+zvrFWrl!Zh{)P)?fO`4)Xi
zrh9Z{PMfB7fJ-*5GXXl)lynQ~X{Ofs06S~?B_1N@OzZ!mrS^GK2%@@^(@h)hL*{~M
z$P<khO{=K*>XIqpZS-ZBbaap})ASFWSGjD8qs&r{iBFNLToXUAd>3{!n<>&;YAU0h
za+zt~UYIC1q3i<py6HR}*Su<ao5DF2CJjw6m8Qc~cV1<Bk_)cd^obr9=$a{%jm8>N
z5dDQytx3BUKU1A)B`x;qO|kSEYcOR|j=j<JIn{+Unfm&n*KFG5_#EsFQ~J-)Xfb{H
zImU9+^ypbMwwpYDg!vBBQL6avG=)dP!!FY@y4P-*YN^uTwn-y|NRMd?Wfkt2_@|(L
z*K}t&hSY0%l@=5COi!r3>As0^5UxEig}GwzeWueC_<U$GEO0=y-_&vq-VER;1oz0)
zXoAe3=?DdWhD@hsfqQIHrULDWX`EhTBc@3m@ORWyNwqm+CY=`=$4$-C;o4KvU8+TL
zGBc>!aF2O81w!_k-~9*b`^+x|fb2K>QI)^5dG{1bi@TT?ya!QN^99-=xS8$o7?X!t
zSP1i;W+ffr@iIsMKkj5Mr=_EhIpqlK`kI&04%^RMLG!Y|c^hRT1I)ka!3CL3Pl0m8
z{3FeM!RC01M1+_Z^})4J^Ne_?hnc^AkB-5Io6r6WjR<oT<v1eE=6KkRGLOu|n2wr{
zU4T!=%r0MpM4J`kATj2C+8xH4=RF6sIP;t!G{&1h4Z}c>o40<25uP+NDUqFM-jV?G
zr_3#8kR<cpVql&&^C^OuY(8`g#F1)#o5DzG=9)`@Icv_Mg8}L0AEV*$1@rn_aOR@<
z;!GI4WL`qWZ5ie<Cj8AbPtyVPvibfZsArkoDT|VAUVjo^<d{tX=*u-f?+q@`JnI#x
z=bMKptyW-unP&Gwb59rS6*<h788A_7z8(Pm67zgYhL)PcD27mGUPWhj%FVMBK)YfN
zTL-kO=A$0~t-@T=4#`S$7HxW}%nNJ4Rhw7S#`U^+2`#v5%^%*ySnAA6Da=-HR#?&4
zU~Y1QWTSb`K@70T?3nTeG@8v)iXYuD^Nc`iF{|iu-!!L{qOsLHm9Ac!x$Zg?+s!Sv
z;8TZrD;=KcG=JO)x4X<ImqYTF`FsVq+vYPx;JVG*%P@!@bImji`;Ix_4u*Z#jCc_q
z4zs@xxO?W+j#P-=H@`6z-aIh7sA1xv`P^i5_M5Az*kr)GdL3XMnH$f544NO&c67*m
zuNPx_Z2og86o$=J^o)&|vy334=CA*O`j|OtA{55W(<puN)Er2eFegjGH)z~rseBK5
z`z*V5QCeWXrSTFvoh`C`@WRD%pDvB7<>PmNcEHl$3(mvxy&00879%b0yez|1_I}Xf
z%)v!CWZ5zRgWi_$+vxML#H>f3uSG&pZ$Hbf9cc8oyh)La087&eU>>$ieHSAOv}_2X
z9Zits2dX7JVmVD`--0b}mFNtyJpB?Hp%!~FJPosawiLfexJ8!+5@8AShfk4~4NmYW
z%3|OG^r&Tg9@LLn>L{!dZMn7%C^42vrSLG;vMm)Tah8BHAn}&ZMj&$BvUU-LB@-;K
zpNETymi`ZbcFL0cAFz`wuRR0qw52;3T(TwaHHe(CY&?iDrCCbp);(*P_WvN3Wl1Xf
z&Rd?CVLsjRn9BYxSP~Dw{6&k5)@YY3ek;(JVfp(Sz%nf#l7-6_9eq;Kk!2~4gNr$q
zcc}^}*Ah-)+&qg%8a&OnOr#=+0t?>>qJ@@a$3TiKPd|bAVhfkHVWpNvN*<M2R-J=n
zxyAY(8n0M>=0p9erN0FV6_%Q(7;mMe`VtzeEFZlCk!p*BqB7SUmiWKG)>twRVieac
zFLYxRwU#kT3)ES@&4XgS<-fJ~DH<$WCqlo`a&0@fCQHpF*lo6ieguUZmKk?JS}eW8
z81GF>28DlHEpwK`e4Aye9G2QGB~<a*Wm!fO`7O&7cPQMptpEEnp!HaO{R-?I3qE;*
zhs1JJ1@pa@Uub`D&+<0qP3~L#Hp1Wo%Vnze@3UCxl+Hs-`1cU$x3mS$-HQY4)99`A
z*b?&)BEy!+dAO8MESDz&dc-nDYnM@r@jHl&Thc3`{?zh3{V-0}g|x!mW8K7nFMF+}
zG@<Ud{&WNC&ep9F5OJ}7La#Vi>xZ-8pqsUq1J2#*NuLWiV0HZmoQHM5K`|mv>*sWL
zdRhOXOLEXEq)F(IHJkQk-qr~#(dT1*gC0>|t7-*A{H(ncgZ8(UP&6mNx}2hQhppex
z@*>#!A$^Y|#QL=tNT@aX5Zn&4=I)0`xV3LB)FZ4#lrfLAo>@sR(<tjKnn{mZqeL)x
z%sP~fF~wL1=%ZP&)|J~J8fUG)3@_rXZ~g?y<JNrI^(I&k$D;3qHMk5TJZY_*3$R3M
z&}68evhIn3`P0@Z6iG<7&UqOkXROV$ahX%BzbuAisx|%_+L@+V7l%RSto1WBI?q{;
zoC0^=I_LzLbn8Qknq9D}s7xxuI{Q0_WLjJ3CcA9)qq@^9>lC_!vaR|6=;c^f)7CK8
zdc*?tJnOgxqtCbQqqSjy_3-boTWB>HF|s1-rezc!EVhd2q*aM^kg8`(tvjixt;||T
zi=}dFT|KxfR^K7?UA0c6B|(KXigwGD)?(VgR9WN8p<Zp}(1EFI*3n;qU1JTV;`Qs+
ze`qIAYyF7ow(G1fP&H`1bsnXc8?1>R!%;`0_4elgZL-d!3iD>GAKj}rt-sMBg;wj+
z{{Yiw-9>xvcI$*TT=fp?dwuBZv<_^>c)P5Oe{h{|S+iF{^0qZS5$fGm+uM-ru_|eO
zeaD(ii=Dex)7K!qR^|T}S=RbSn7!|?syhMmz?wQ8q|cf*3bcpT4V3Qbx9*{c-hg%V
z2oxV#gPQ<4Xthp-$dI*(7L|{!0kjz$w(jG={1dB~BIzU6)3jS2waW4!GG^sbR$$!v
zYXlmfT7Mb?ak7olJA9AL;r<3R_S!r@0n9#|bQ4<l+s@JTa<;K4MB-x0qxh-2&4to&
z2W%F44|&*{7-;mgEu{J+FPl>iBoEpSKZ3u9Y*i027H?a^8E`(fQ}l-PwYhtN^Ru}>
zh6R7y6*@i<V0+a;xv#^v!}P)pv~^LTPmt{-l?xuReZL(f*!J`LuoPn3DZo_^wcVsj
zs4!c^YBYx1=1}A^!nT~s$0Kd`X=fT`J3wKkqqes$f;(p0;0noT+dtX37BRNz6T!vW
zwvrcdwt-a?9*nnbrCIv8ZHo;siMA&yaHniJ{{be+R!n=2)3%8e&`-8C(AwjStw;g1
z6x++wF{V`8EjrhhW?OO%+&SANGfbSf)iyvc-PXSm7B1LsevZbAwhw5(cgdDVC3zXP
z__<VLmT8M7gO_bNwCKsQZKI@qw(auw(9f}n|AkMvwm&IMo@Yy6gT6xBj50J9*+MqL
znPQu69qg9b(&<qtx7E_p^op&X?(RxkR~9T)*<3z?LbWaPKcHN<IZ+(1*7j&FMTY8Z
zD-J`W-ge+BNP|st1)z<#pSvN`V#`?wgEwtQwg9cwHZujJ&9;CdrtP*jgy1@C|I%u|
z)AsWM=yll|+F<aO&2tCHZCm7v@TuGOauT3>Y=@9koP5W&=mIY6U7M;0B930$wsO#W
zwtsA}bl;XptA+=*B}-tU&-VKF@cW_d(;RU9wx2(Qr2$*xdZ0bB#koLl(3Ve;ogv%H
zMX>bPwulT4+n$VoJh8=w<7XbRB~aPHsEsiL7RGGfW}|W3Hfaq|o;qy*{0P>`KEnle
z_t;m&fZJ<#ri9i$`)gEuwBP<r1oU0)Llo3>vuFPaMR)rIAx3e)-bJ|$5Bsc7;Gw7e
z@5i{nUiMqG-aTl4vkQ%f?Djr@dE5V`ShA1(@&@Sn+D(+g^|L!({sz?F{x1c30_^K)
zopIQ{ZY%Ty?MtW{F3A24B{PrMt7wNAY}bT<3$foYKqS;2@&gQp+0*I66XEud6(AAz
zw%xEBY4>k}NR+)k3n)kJyU)YIG5g|QL89#pDj1Ei-*wPVBGz78hEc@XjkBSjVBf_+
z=Lvfs-Q6ecbDp9v(f;EOaHs5XcX2I}>~>1FCEH!KFn`AW_Ip4{vEQYfOsYLA5+Z5#
z?{Z-Gygh0nNV@&GpW(~}yLTNFF51^l2Y1OHv6Ui28TK{w7S6N>Qu6k)J^KN$v+Vu!
z_~+SI1cA%9Cl-J!u>Y6`v_ktzT8kIi1InRLZ2!X<XeIVr(GV%MbKin9W%hv+7(}`K
zL#k7_YM1{EQem&Bcul39yA_UB+24t$=dapsT7VJO*nggY*6a4(O1NKZf58m2I(rP=
z3HA2t6r*Ucf7*?U-)R3?2FYgo=j#D_!#;8smRjsCGr`@o7vZUz+-l#n1eV(DDU^zB
zxBFd%Po4I&M_{PSE_nvzmi@+!XYl;pw%ZqC6y0`&UGR|DA5gu}9ed3M7#y}Qm;|&j
zyD%OiPwn4C!~EWD$7TcDd0Tfc6x_C5VL-uS+u)xd2e&QX49UoCJL_;sPHekP!Lrla
zyeamSx=oP*k@MSPm&2!v+aA-_(vi6>|13bWx2>iZLjJbbEod#>c6=XT8n<0#p|5+J
zJr~aOZ&SR9zL9PIx$tS<b}`*LuG_ykj=n?NPvpbWk?o@t&WqaKF^<OL+cP4;C2#kf
z1oIcSS5k?0-u7=PN?o))c`+<hIJR%2vap)%<8sIx+VRE9FcGpN+YeXh*p5HG0Zj6a
zQ))Dx-63hgurqgLGvHIvj?atHSFvOMeCRdocxyXEI(Ga`l^nNs$Y;Z~z8y&#n0UP7
z#V?>Yy2JH(IJ0->N2M6&ft`OlqtR=p<6oLeeRmqD=r~|!{x~#3c8d2yKYHh1wDXGJ
z`Nm{eI=ORJ2PBhr_R^DjX6G-vVK8myRGM$j?sRlQ;oMFE9f&!<^E$-?GIpM&Sub;^
zYdd_(+L=J*8QD8u+K0ZJohzC_a(6m8#29Ga&TG5jTmH^B=71FJ{G^4h(En)q4!9_e
z_kDNv3U?eF-0kk&ae&4WV`4NWnrMv1o~Tiy(P$F8i7m0jSQE|Blp;+mND~lHKt-?s
z0)kyZ5o{=k6af_!tRO|;|GfGB{-2LB%scP<yzk8J&d$8=JIf}H4z1;Gdao9OS2tDu
z4T)=;wu}NXf72+$9Oc(HJyk(P!KQ)q7~R-3eIi(HZqjr^+pSGg$#HUfQ~DfOShVRb
zEpP5_s!jmsy-n5>oh#n-SE&Wvez@u9>j16UWP}T#iyZ&Xb2z~P49+bA=H218?}I^i
zISt)u#atCFqwaH4XdCf>J1>BxoclqCS|t}^2mBiDt_WfSXLTI?dCQrr(B{Iz8&G(&
zRcnC~#GW8i822CkOD8{tH9fi<#qT}yS3*^<Psm&Oekv_9dq<LEZ%8@q&b|!)2(3d4
zJ_Y($>zCl?u!VFubND|Lto+(M9wRm4><FNZJl+I^QE`t!8Qt^*vSSWWe)iZ8Xx%cd
zLkHP!mdv8f?6-~gz%;(h2F(*XXnvaLeg?mPcfk*XGb!c?D3jaI;P)wO27~^+e^>Ns
zY7uP&rX|qG{V+2PJkwR=O`75T9t`?%#tdN2{EIROXI-NC;ivU&K=`?E41WKmGz$E)
zyFQ}lf6fgKtaEQsHt4)<p0ISjbsE$x%%RzTQSyF_)~`R>L*Tb)KeR3$Nr&8)xYLxo
z^cDGmH>V!L&#hc<$}8Q*^`vmQCpU#|NiWWs@=?7x`!wkF;bQ4cww-&w7a)AOwwILS
z=g0jV2c8{VuRRc~;8vu=lINVq1Q1_vV`%<t<+3QVxs97a>$I)Rr7wzYY)2hwVqa1w
zjTifBIaGMFJi0S|n5GdZ+gXc(G_f(1Nb1Mz^D+40%#AiN5$pk+v!mq)SuRaP@$7OR
zXi8wi=_QcJPD}*aAvS_eEgWWh$un_;`5gdu68nf;14mhZAFw2|0l~8ax$c&Y<VQ+l
zd;SDUIvXfK;3R*BJSnOCB1(Em<GYiWGM(4FguYXJLoJ9I{Id1n%;Y!GJ}HYIKrxxq
z{KFrBlFgSV!TKD2z+XT)!<Wo~_OraiLGBzsopQ&{^VyRjaDg9V8HVyA-_r~BUgGWg
zfafxQC=S?H_~)xo%jLIx475D{*L@JY%6~E%LvoETq<CvS-+TuOuk+)-hNc4EOrJC_
z<fnWO@f-Z?Nf5Zn$9IFkE&dYiac}b@DI|1<kG%r5MSR{AIxKOQ|CLUf-Q#BwYcao!
zBCI9+ICAdZ=X<(>wUiH_uT4DQt-pneGJY35V&%MP2Z{<ln)041`R8<>J>>1keO1N#
z$x&4EEtDNs!xz&Q`4R7U1GUF|s1@`*;iIS0MzWTlOb=!qpSvCMPx*!O0s4$Dn+wo-
z{?KR$Ht-+O=Z>E98~;M_f={Il-AjIbPYl8<{voBOz2@UqfcS>5_JW~}d>|zpHSt}$
zq3ta%#z1c~|5FH{Tlly)(AUa;mMQC^leh6rdce5IexHr8bd|jy>>C7cz4rh}oRFQX
zfW%4Jrn`_xmF=kqF-=yH02S%7D0=n^WZgp`S122M6Pj+wzP<>~o3dW?`H@nY4`oU`
zkgd7~&KlXhAQX>eJ?$Y-E9*ze7<Dr3dyw;#2a=1)3lA&I_Lk4KSivS=IX4r7=qFF1
zWK)0nFMq+90C@>Hek0{$rb6PBypy&x8FIH06q)jc^e|@0_g{ecX}SC?G-cy2Q9?zI
z+=gz;GxF#h=shbxdjqxe@`m?e;RSht1;mT;yaXt^BsWjAK>o7){v9-4k-vTly}9`A
zI`rnrJG!CwWr_&ucDdpfo${+t%nL<Psrb4N<R2<#(W|6N@dpiTwStvFphmIqW4bVk
zd9Pt%lVVXP?Cn%cq1}>;()uLCU6s9W!U{KKttU;e+m)@<Ctu}JUr_y&1ISW;<#Aes
z1uB>K$5`%A?xZ}gAf<wQAG?%u>FoM$<uCMh-J^U)o}XalH<YLtrd0fnB3$WM3Sxw^
zo!o6P%3<W%I-wjwyS$T1{tpzX%0AEN5O<n#;0dTdrF{Po)MqLW4?|;?a`_;P#c8FP
zPK{?P-_kc|bCg#dQM;@>ODn4@%H?$D=PFmbLm*H2(@+qvDnlLtC0|)dm+-ps&KQi$
zUF8-X%)X~ArA2D7lD`6*N|b5j`LvWOn<yCcK)Hbyxn)Yj9Ke(-TLOSxsa!-Z=7-AG
zBOq2QZ3Y9TMrluT$z$clL<l@l7F+~NopJ!J-=8Ue9S_cWWriEX8<aVESm9<hXD+PY
zYxU1d$c0$_ejUV6t2%$E53^WF<k}9m>OvD^gw@ng!0fY9Q8*>i>IX{gjk3yJ50)6K
zy?1~eYc-G#fW%q#CRh3aD{t}_#9Q5431bqh{^$XeM5~Hw)DBq<n*h$kR-NAf<)oFI
zcD1Qi|5Ac~y46a0<D9b6MrH#v!)h9ZBQve)gZuBnL+N3_kes#pdlTBuTYX#v!3$Oc
zX=!uOO12t;m#lVCO!bOYCk2gjt(qGEnrFr6K>IbTP)g{`w<;x9;B~9T3sI}JI=K_#
zbymyB+y2Zdg|-d#Rtw3~+h7$yABB5vRkRG^FRi|}(4nqZR-sqG`o?M~%}k9}^U3qm
zVU<Cy%TB8U<cV}qIq=|gRT)mh7&p~}!+>#DIoSZlLv?&TOxvoujbuCdHkIouw0Wvp
z=^N-?sv1XhFi`a`(%9uYRA13^w^PO4hukieWd?a2_NZz$LoitNh&G@{RU<Y+Q?kmD
zUSr2ppBd10Ty>H1h)$>q-B3HJntUHcs%jLyebZD+DA6HZwXFyvb4s;02b>wIF%1yU
zR29+kBTH47iQ=?s79GaSRt@WpT8?Vz9~>UaGpe3#kT|P~v4=6|RArfTDO8ha2Y5lX
zo8mqfRaXW8`;v+eN84r9L2|NQQB{x=FIN>m7o2%2k#4=Ks*Mv-TvKhN!2NaA@>^gj
zP@QW*w+mI*VqxeFRT1T5-&D=VAEU9zZ>dZkpx##13ShmXnoYMrk?M3MihHVj$`CGA
zWz*)iM76aMdhe^8Dp8cGP6oi<2dWP#TwA8f_yMMst47eBP@xJs2DwUAkvoVFRUhM|
zr@TsKR^U=pt3IEAqDEy$DFT*9s(X~c_gLjeE4L@ABwESTs&-C>iXG~!Z7?lJo$vu9
zLe;q!0UD;xp#@F2dJXNZBh-D!(-o;s`vPcD>iG!}->+Ud2Stqfq7~#~)hf!Ii&KBQ
z0mOsq&0~QQua0#Fbb>{_?pKtF>bVO5dRX06gT^HF_ltpcRLz$HJ3}2$nLe57fxThV
zY4ujh_RLm?{|3-Y>dm(STA;S26;PqtNIUHtYSmeE>8AQOHQH{eOU;nGtqwT^usiAr
z$1o&C>hCUr<*wQ?DF%A)sjaiY`cNHy4@H%F39a0!)zM$0R-^u8DHJ|Z7t+-KSpAs%
zl26owZ^7(ZbvJilKUH6t0`<?-O9Wuot4ql%)S%Yy1oU(D7IGTCQ1_;jX)o1<zo6}v
zdfQh(d9Chiq2!u3>cMnSyHWl48hGBS-|q{UW_9=;$hWAsQyO5adfQpRw5ey!M)6Ml
z0l7Ka)gq;NcBn5cMy*rrO6PlAtgY#5E3Vc%`k-*LmeCT#-CA6PnuoP5eYSF|^}+oZ
zr)}0R<1CQ(wEiIy=KEN`{cojet)z8=uk}<~t@vBpuR|@s`milb3$*s$3*rvzoP&S~
zvTmlwX{WXCc+_@T-=OnX5!ThK(U*PJ)#R#;wEiXxMU?esnpgK*`&OV9W4)QKeXR9o
zlWDP3Y2CLR=D)QbMDAx74L1+0uA1b1Q0S)l@(`J?xlsug56v+o0?4;&e)|?M-kLvX
z8|9-p{1YtPu5qFicVA7AD>(f%M>IeQ&}asrqdPQ(8lVJep6&t59?hL(T(n?K@j&wW
z?bS3af%zetZ)n;I)09vOSGdNGyp<7}>H%omr!mswAEh}@0jg+CsSKd|HMfQXG)7ZS
z0mL}X_Rm2)pqaA?EC)4Kg8>$=N$!i{m}VkP*2gtV&q4hOP3Q!eeNyu-4RWJWHG&a>
zX_`fphLf)OwE;zj<~w@QGd22NFeY0wb~psjXw0+`Ijiws4!t)towXR}o0=)XF5!qC
zeeoyciZtdgz;aj9BMt%;n!qB|DmBBOpzWdN#5!PBY3PqA%4;;E=Avh{nk;hF)@gEz
z!TD74;bG`|reTys^jwootA!Vu)V^qYsoB^KBl=3SwL7eD(!?x6@m8~%JOa&{Pb@tE
z)1ujU1*WxX1|NZ@HqBZMtazt+uO8~#HQ&)Q;%DPS(I<bKhvf4NuvyWHBG9JtzsQnJ
zLMhsUY}zv*x6@|9HK^ZZbA}#+-8Q53fZk)1^*+FYZ9d9@++LfNbX$bj{Qln;3PNoj
zCWAH1#_}Cl!)<z$LVll(oYLnaZR$HgjI!~iw3KL@NlI9_-=^anh%q+dS?FP`&B5C!
z4%j5*V-OD7=;)z{w{h8w9wylQEP;5)rt1{+^RUfITI?LLvDygrNj90o=nEl7ZF0_l
znrt(K(r{C3_EG-qF`K^zLGZXuD}Bi6gw3~<jhkwth(+OLdnX%(w{6uA;PkOoQqEP7
zZS6Yf4YmE^GwO?N6y@@T+urwup%J#q&mj<L+v);CqikI%+!SrQ=o)>YV85+M;e{C6
z?<1i;*0!ex#Sz=X1+eL)t^Z#rQf+5NLn6&~3C$4cwsqYAbJezZG&EhawWrl!zHKz^
z`0v<Wq?cil?cm!m`>t&UWn|p5Ev02uvF#WgSW0Y-lvH!yR<Q>bT1ssPJ^|<h+i?1V
zMVamAH!=9-w)=*_iVEBBR)DqAcEx0v|IoJoJQUToskCpbu}z?;{3F}IG{8Kz4I_W`
z6Wg!$K;V__o+O~Wwq0=#ZEtKR(@DBU+qbO{XtEtL5w*9rcPOo-*<zbV4_=FH7&(qw
zZC6kNXPfOO{Xu+ZyMdeo?Y6J}g=rnO87-)}Xh*lB%~f0fD+)Jlm>Hn%+6p=b;-U2(
zf|1#({q!?fu}$mp2Wp<$j^*I=(!P=)?yWW6fq;)TayE$DwU*=KF~Gjs5tpIfPn$!T
zGydAt%@7RGMuvhIsC`32x<h+`0=z-mK9L~q)J7h_sO{E{oPoAI+R?wG2-bQ~>eXIt
zGJV$}MB7LKu~4la?OejNViRiN+68Lpi_nIbL;XJO=N5`=MQQD>p&G4qqeEHywKvFz
z5~Fp#fVNm|<~X#)X<rP0-~sJGiWMHzc8`OK1a0DQbS6<7C4l9S_VySI!eMO-#hH$1
zRR@5Qq^<n#m8=~)99AT2qa%TtqIK8_mSftC7394-t}UQ^@Dtj}W$06?*3bafG;JFB
zUDCB}8v%MsyXYxcGPEaqLw%-p<U+`2X{XcldRn{g42-#?O@0Ni%i5wJAaF(dH+?K3
zSKD?Bm^Za!e86%`yN5E)Zfis5f_O*U?<D0l7HOwafcdVL&xYQ6+9sMwi?uyYLZU=_
zAQ@=)wT*h9m1>vJ_VIzXiM9Y`+O$-lm22;80a}Ij34DL@N^R@sV5!mu{0?HZ_Qy>y
zyG9#J$rq2bOWh#wSbNeMEKjtH@H(-`Yqh*TSnIS|G)q6#_M<fRXWH?@AW^SvF@e~i
zUE>Vmb8Ubt1Yc-R6vLR;+E2-q_eNWF1#OMmsW}j6(k{+L@m4#5ju|v-N753pMf;r_
zMy*vlBN_s(c7JaK(ar9gUFfdG-A?I`{(9I&uRx!++0_I9&C~AhV${6sHoXsp-gZ-H
zo#11aMj_$tcBAQC?rW!`1VKN$cNEC;x64k3-T=FUbetp5Zf7)#9d^G=gr<1=32JmA
z(Y}iun1}7Bq(d&r{(u9FNuFt6vK}gq*%zln;)Hz)?dDSLkM)D54EulVz*=M<nhN=c
z_SVDDR%KrmgIcwH=g+9s*mq2Y_#^w8_aOe*zJcB@FYQ0^44xaqy=R$4IaqD>b4#G=
zo&7)LNNBeomjq&meJo`db=uE90tpx0Ub<&pb?1HosGDv(B|Nz6{Jw#JudZMR6#D4~
zeF2m(T@Ug+hU;brp=<ke7ipG`)S0Tl5~Z6%UuBEd&FBTr7+sBJ5cO2I>pCQk>b{PJ
z-c!2Mlt7)K^QJ>XnYyZv!E#Y|n`XUBI^Ugi2kWL+LjH=*nO2jzI?LxM@^sO3ChV#%
z>loy&=^Xz7F<&?KSLnU2>oF5Wfo{MH5DRs~X%%}zr}>I5*L~eaN)a#BEhqQS1D$de
zG?nR&(1$n5b*HwYR-vo80V^tXZ<eBXs9V*6UR3GyuOL^g8`pwbjc#BKYL9fgDUJKF
zE>VE^6Wz`(AlB-#+n}gUcfJVXPj#8&P<y63)1N{^^}2%;vv1JVQ~ttp-4qoBU+C8C
zfZ$7=&kXeGmCj5@;a=++$jA6bXa5~w8g()B#%$8frGsj3b>j-b(yZh2(bl5dbO)TR
zx=3;rw&_%-py8b^*9OFPo%j#byXd>E!rvB<yXwoEFeYyLQB6Q|*T;1QtB2mP5Ino}
zKVAX$9(}+!z}~CxKLBVU`jd2EBV2E<g<OQ*j$VrU^j7qyjnvQj8`ekZGp?f+tuLeu
zhyD7#F?6-{C&_^ktM5ZO9C7+~@=aO}=wH7F`GflK-OwAaPpt(tL4TRnh>7~%rKla!
zzj_BN4(r!ZNa~0_`(LO?(yyYF(WCk=Pk=L7AH@SZMgI{8lw<mtl-_?_|KUp1PU!c!
z0Oh3KcN999s!yc7Y?|JO)`sa8eZ_IGp3>KoV=Y6Uos3$hKJzowvh?AUnsi$K(btgA
z)~9TMM2>!VF+k7ghtERWS$!UT^68xZ?QV49yncN)#4qS8X>)Z^-<uAvT+#=U>+Z7t
z$cGTWqOYdcey;u;MHTb(maVVRr>pv7<Qu)FH*`T`zW#VIB(CcZQIcALzTO=yg?f=*
zU^nyuYH;4vFZmoSxAX&4xCXcNMfaipj$TXe#v*-x4TyL3gJfX2r=LQx`eJ?kY7`~<
zc1lFPuOCLMol?D(r5mab^pRm;Ez|#$grZ#UehxjX&?nO_rBc620_#Kl@oA`4=^N=L
zuhvgB!?YUxdJWnh>A(0I3Lopo)3)e|ehX#P*Xot@zOU22Jccek)jN?B=$U@SK^R)E
ze@8p{2E9)nIVqm&18-xvU+C>VMe$PqjIO~ey;_ZteXTDLP<x{vIsz&h^`q!h8BO~2
zD`3o9{mrWYZPxd{3{5S1&KpIm-iv%IZThzP;C!e5WE#ZV^)Z>??9fk2M0Y#&>IjIt
z2q6P#ljJHqqjXX?;R0oCxeGP4HuezmC!w}gxJv21+XUAwsCf#rDKo=M7<UVx-olg1
zu*pYwpBDeyg=#uF;475eg(g2?^h?P33$YZ^4G>OI2rN*Tb_<Gj2z3X*5+rou>l7CG
zPJvm$;9bHKI(4^O7(~Y*_XwXJfJCqmPQJ#yLKdBe4-pEsVYott0B^{L313mLCtSEs
z=`<07j^^xr!t9-3i4=O!w`-#Wz5soR7CxVdV!v?pPZ$#;ETmOdtY8-g7E7EkolZp_
z5T;Cn;6b4)9npvv&e5l)5`=PEQX~pW+JGGr&c~xTEPS&7#Sx)HfE7u?!1n=qRJi^M
zDw2i%3qVW}40O=ym{3R4`f;J~OLXvrF!I00P>7;8PO4C350*5G&_O4|(uKu@c1k!-
z2^tx~WZDF03V(+}eU`9iJ!+?g4~Ie`TPUCp2IL6eEkbcdI5-;uXN92)!Ff*j`xA`Q
zd12>#bnSvLzXf_P3XV;vT@p$th<912bcetdVVn^~u3-6@9D#X)2ZhY83Oyn)me+&}
z6eY|ThEm4&b)j?%x>g`uNdQ`*ka-Zb8^R)b?r#cBlK^^42<!#ZZVL{LP=7~o>jbe#
z=(QTPyTaOw0J|rA?~0;W5ObiYL|E`K+U^VgS~>tzDumWT(*xm~6DZ0A#WrXv7l!4c
zs1S-}kf;>Kk45dFAW(u-m9RGm^3}o@<WHy(&e6*Lk+7J&nU95;dx7~xSd@XbS|O`1
z<m!ZJZ$Nx1aK!+7CX8)FTfOk2)&ju>!Bm27KNtGGhsGDe{WZ9+UJ4Iqpck)%+gSj8
zEj%H?H^RgOz%&ZuAE0Ow_N{@vZw0{)0?on{+B3BXC7~!<1v$+LZ9@02!1+%2WeJGw
z!e?ga>kyRNP;?4^9Hq|>xQGGPfN>Rj@=)j|_B{zScTsm5c6*4m46Iwl-o9YjCZ>j<
z%~M=LD`hV+t_IlNqMW`l<s*i6f%tZD9EYy?ihq-rz)y4>1{8lWNC))+;@9^e5GXGC
z7sMT6riPq^LE`IPkk~1{J`SE;;$8Ap>=q-hfM<```7J<$#q+OG>=k|Jiw+@TkGn7?
zRGdy<0|*oUq@8uR_^lV(BE+wjg7b)I(-Vd!iKoATp-07KpMxb?{E(c#DdGw8)EpBp
z*5RJ992awGOMOD@PYc15;)d=3O%+e9gQaQW`Yf21F0P^7)hW?27J4(pv6K;#DZV%l
z&@Ay#Hsnr=b6!CpTdaHo6**#sJ&H5p9#;sQ6&DG>JSXZXr~JHVw-dDs;>w$-U9^a!
zZUF6)IE>cKm&GqBN`6K3q{%*4tQdk?o><i#Dz1wCXmfW>EcqUS`QouzfVnOP&;w8)
zZu}R97K+E|ZFWO6&xL6>#Y17J-4gYbS9x2sS`I~b#G`aYio~GffW9kQR?$}Ro>)$s
zv|_Q7mYOAEZZuf$i_YXiC>6h9V0|E-rR=9NF{cYS%f$i;UsQ<hl=@OBhLS(<q4+o5
z9#vx5FEFiIyg-@PHR8U3V0k3=o`c$BvCCET?1{*x0jySBZ=tEUPJB#$iKpV+MhHF=
z4R%miFCL)$g$D6u9NM0X7fzyhA%4*neR?U*`U{}1#8-6E`L$T$1-);?Y2m0fip?pg
zHHo+8!uq%3n}<MY7Bl-peT&$KQWsjq7!HHbCjK&#)}QahGAHn~iwU&A?+{<~hNe!j
zzb}k&k-nURuDMF@Qc-i0Hq)xoT{6**&qE5NRpD02F$%S9(p-9AJ*6(RzxR^dA3}w<
zw19$oKGM(cfVo}jb_|8D)JTqSKgsP!`nJEn^om|G0n%pD8z?m#0NM_z=@n{0lKqcB
z+bP9R+<li+*aYHk$twsp?U5?eU{kQPjSge&mA26LYeJ+A{m_X}X~IPGK1}M`31YaE
zTnx?#>1;A=+9z#V0+vW=`gEKeesq+xw@mPbkuj3JD>TPSA+*1WlV(sN-vMb1IV%rJ
zO@E;+Ub0#Y*aT_58L)}cjjbpSN%^VZJS?4!0p}5En;*cEBn_<_j!F}YF+|DIUJ8Gv
zNFu$7j!CP>L*Te{%MmOmBs&W|0w*OqN>5Fd+UY(^lRR=jOqW*XLGY9m><`uqsUP{^
zGo_uh7|D`0W<&jHsg_1MTk<;sfgGvZJBXi=){=kYtdv2w%Q@-NcOagZ*6c>@f)uU=
z=SAr!8HkspLjx@Uy(|R<ples8a>CA)y6neD=Sh1g)^SyeqT^@Rq(Su3$(Pg=k-jde
z$R$u9{g4OFLMh@k+HOcLuTi@x{Wt*XZ%Mr;ptvm=eujoS(o0%17D@HwhPo>amBE;M
z(v>B&!!MS8pe0I)bg2<W-IoUU2WzRMTm$(B5_XDs^rX#SLPfbWybA;?q#nItQ>FB4
zB?KNy>Gd$XN^+yaG}Y3G`%qCMeM%dfN0KD~ERUrJ`=H^8G=^s8T4@92DAh?BNOrTx
zpGvJ|;CUwb)ApfWsyPq!4U!Kn1D;Ds^{Bm&>itoBDfOl~^_BFt7ZkphOtf)+BRSF0
zwniy<FIbwS_`@*!t@P;~)S9JqT4c6JFXgblRT@nP7~7<^w9R=Z_3sN7OS{zG4?G=G
z-7XZJk~9T8E{1!Z;BhsKqLqr9p+tni?uILm(dJ=T|21sdWw=9o)ZK=CnP}T%XzGu)
zU_%SVFZUXJMxrgmaQrojFvF$*2!tE1?FUPQ;cRyh_Zhx$g8E2{LAnmTQHHTAP>nW>
zk|4j|aGY{%Vhm$9!R}bYMFNd8G?I7qfZ;7|ZVwtp_CXPE7)?&)1jG1f2qYSMy${Yq
zhBaDTro#p`xq*)uX3?i*lMD|j<dAH5_ag*S3`>@wIA*Z;mjU#+VXG0EP8e>|QsJb*
zj~ub7hIf=-nr3JhF&62DnRKr9l%e@U*qdSaosPz28XnMgCCi{DpXX_VMDfpT!)W^Y
zbdI5&vc1k2#?gN6tf89H+s+wI67js@ye~9dF!Zz7K*dGFH994K$x!bI^_LAB??TfR
z!}Ilk$u$fhCu^SJ&@*)Asv&9!ife|>4FJtI3>^ja*A3aEzQC}PwxflH-*=$6Vd$XK
zZ#NB7D24QvA?-FeZyW0Np}1o>u?cF643<(_1l={TF<`xCSV6v%VnYgT#!C!G9;3K#
zxGx7wsp0h(u<3!}Gg=Uq89oaHXu09@?({eq*kOQH8jAbFriX@^BT!Ts96kY9wc(3@
zVN8u-2kpHc8J69Lz+=PZWDuVi-b^4TK&|0P642@lRT^k|YUub5g3k<nzeZ7SxO4|-
z4Tf@>gr6I{G?0H`kW*0erNKW77QQn4yaT4aHh50P;Jq<;Zp8pK8uBTbp~;X;S;%h<
z?q*onY<O-3y)A~`v`TC>e7KIB0Bwd)6L{Vk6y1T=Zb<$UtR03v^bY7W_~k>di*ax`
zEOa%7_eRalm_R!WcjJ5HLG>{HOv!;;jfLcO*k<h62gZ0B%eR2&WwfO%WN+hGcVPM$
z%PBExyRqj>i2EAb?t*CXGd^Aqqx_Ad=mj2Ntf$E@&}f$ro*l*q<g5uYHq8agPGcp#
zz;_w1#Q=M^@iWR6*<(CS76u!;-$t?5_z$H!hZz4J1o2SgZ2D|;nDJ95bTHhQ{{e~!
z<3SU^_8HgF9T;gb_Iv?}C}T4nIgU22(g0?^amWb>#u)e0hpJ<ZM=8=1XYBe7Y6pxn
zSEF{&IPF{1;*C3<VN-%J=~oaFjk1FPJ7jDoht*-@Zh8+LF|MR_VUn@)IarPwAAbPo
zWMl3^u%s9*%m!v0GhQhN+HvDGIz4y7IG1L<lg8kmAfIa7r2tEs@$EVg(~XaAqISyI
zM#1L{<9T<CdZy7X4{}+?&2%51Hu|lB!fay?KMX>SF_WTCXN;q1)Xo}PL!juKaYYos
zE*fhr$*5j3{!2;YSBy@>p)l7NIUTm;8P{e&@TxK84D7yU4EqRe`9^QLEw3AGDLhwT
z9JCHBg~s)i3VOq+q<j6QaegZ_-7+qBL)&d*Jo!cL7*~vhy+y{il-6?BsG$6Td&byT
zls;5!^gNDhUt(MrfX>`ECVT~+2gV=21F_7gA_q{pG3Xr(t}r%GdU>VsN-D4)8e=>F
zQ)S$78J(y$2AE+*jd9Tjz<gx9><MEY8(TUc@WlA!7C38-Tbf}^ozd$fh(9$Zt)NVW
zXU3)!Q0tAkvmn@DoKLU8=f+Jk@Vqd7d<Dc;MiU)rcx@a(SrBiGGhU)-G&a-C)?^$=
ze%QB0_k7sfZ2X-rOp7s(wj`~_N7TVK<MLpre`oxhHpT76+78&;VbmfzXpwgslW5uC
zV!HJlR9DkrTC=*DdObwpZi@N^R(P1c%LVpUQx$!lVw>s0mr&?w`Z^0NUZw*yC3%~=
ze+CpEQ;;u++f4@_V=R14-6=HdXWF2GfWPT%0onpg%Kx@PriG^<XW3!u{|wY1(_~s_
z>@;ov2qx|_Wz*7ix9Ks(?)I3z>jL$`rkCVJ+iSW=xvC+iUR%HtYD%AgBFwb!ImE+F
zR!3lOgsF5SuH-(`G>V-?ni85&i!$vZuS2xy`dHNVo30Op`j{V01HVNz*3`8K)i~2%
z)TaX`WG3MmGtJ>J!11O@^s(UtQ}rO!5=~ijp5u^d;u~l>Z2Dp|x^~25l%Ys6Rm;$J
z)Z`yLB!e?A&l?IuPnfoS4zQD^dz6xtYO0~6oHSF`eiZ4Z$8-kvl<A)>P@7?T7KFZJ
zn!-;4CClU+1r4W7Ysur2ZF16~FFB^`8$mo{YTFKdXH82l0s5RNJ2*Ro>uz~{7^8K?
zBzU4Lxu$^!0G(%A<qJhuO|BWxaLrUP5w(2NxlLfXZrYUuumaPYD99C>`q10&hG}3p
z^xZVM`~&D)raYQ?Z=0Gp7=On!k9;germtMVdDrAQ7H#)TV<`!_*z}L337{n=DGxmN
zO%sQrR%+^?c-{lk3kn*SnX1TDT5h^zhG2y$mabBz>GzMp`OtK}4#X<cS&Exfo65UG
zeT`{qPxSMpDdiMwdSyx_C;e+vIt6jwn9eOm(P#>xX|c)VI-1s6Z%wWJpsCq(^ep6C
zOvy#4wVE8O(bi@fL)n$@OrKF2O}pt8ZL2y=;ZcA&;*dhFuq21`>0n8AxbOiwam>M2
zhPLAl*J$5*!eQ1a5KlVH_W?20!Rb20(;bX4FgwFxQX)ANG9B)(1kY)Q3X0-nJFKQK
zWRAmPC0#U!0D5Dbb(ppsXy+VOQOe1AhbI*Fx!~}aZqADi%g8x;*&%x$T}cQ3BQPe{
zA>9frR~`C&0fB1{RR!S8cUapM#On@5I!ILD&@hd@!cpjOU?@iDhQnP-PP^%Fom{22
z9ID1a{cVT!6cxPV5Pu%EB8Q;{*nQVwBLzI}Is8pY=*12vXfIsiaQ^~S+;><_BU|e5
z_;+;TfrD-pILjO^(xSWE!HP~yRX9ZHU{j3)Pmv1C6Nfb=z^--3wgYRO!<%%df9l{x
zKKo}5D`=ft@9>F;OWEMC+z%4Z9lU0N^QA+gGtgc+tlSFm*A7*KQM_?*X#%m)Vf8Vv
zG&w{x!``<JwQ>-f9lmm-%j;lx3S(Lwo*aP{Z5D@9+fjYzu;?;Wv^(6OEQSt;q2!S0
zbT~8&FfL{%N+5GJYaGz#X5K=lR^83gB%pbixka#PtJ(S`Shksieg~+h`RORMd70k@
zgVWor(4!MR=C>50*lwO12%@jKlafOH%$9IkIr*F0gCQSao?8ULK(qB4fCib}C`)mt
zc`beGVwZUa#R_(t&6H5J$L#R{H%qX&$Qvws%}41S5n{f51DZn3T`0pY%zR}wz{1Tl
ze}-Iyc?`Mk_L)Zx1ToS)$Qhhb=KB_UK}VY>)7`S)y!IZjW6hb-7_T_<FVoQ91Lmg`
zIy-2#nTjEaH-8cj(-O_w9z*W1`6$gEN6Zr`P;=BgbUun?b2tU0Qp|f!K<_bg13fCo
z&Ch8seZrho2o0&`QW~x_^X-MSi%U2A*r4&0d5|Zp$T0s(uJBCr5kK@P%ly};fH`gc
zo-!G;&6)IU=a}nmf_TQf+XUiSb27OX&Y5SA2iSS@f}Jq*f?2Z{#Ea%+5uLbXj-&hH
zvia>H$Xziz(aI;+Jlc--l2^^iZQ!|Pp63gReDe<swp}-8ldrPCERgrP&^(axxo(&*
z-vY7KoDvH(Psgp~Z1;AYM!rTL#|X-x3U)kCOaD+ut9!5_!ZDDX&ry!%_aPqRIAAC^
z;~gDo)Dj$*-=Gg?Bs%8PUgePEZ*pil?AZTb@EmcxF%DKFId-9!=uyW`@~R{|uE+*V
zisLIc4A(Kou0z0i+_5)BN=`TyZ$)v^vAHkQr#Vjl5pwB{_h>>r=Qx4(G3OogDcPgI
zar(aiD|CEO0#3^f$IiLXd(+W&1bA*aPM!l}ZaXd>kFMQu{DC~RMUH>ci|($YEFSXr
z98+gQu-I|O85mRI7)vns9k2WW&{D@Uy&?C&(V+@*WsddHAeKAUcY|DoW9VquROy&;
z3~dh`V`=eQZE;l7`Jfs{>r9}zJI#3ns)y4T^hV$6^yUu;ZgX;^(=p*rAC8A$gj2{t
z)b=@@q=k8;(-evZMmY@_gj%$d{eN*<rwz2}jdfb`9n>FiI&cOkN1X~x(2(r(%S&`O
z#VOJjZO5D}>VI&ZjysviyKus(;5=$4od%|XHPxw$A2j7Swa`xBjFZL<ZD*YZn^9bK
z`YH!3*PP@(qR4mZO)K&1PJ<}cUFf8v%%Yo4$r^Cpa&nVkOqo*)J@@5Kx-4K;IGHE_
zQ0WvEJoOw>wwx&mp~<P+NVL6m8gdt7(CpNG87@eRQz*^HZBBRS=6>fi&IN7lPCCjr
z=x{RsmtgK(OEaje^IA&EbaP(t4b-|jE4*Quhx3I<5Vtz_Ekk#=Id}X51HGJeKcUUr
zx&J*BKF$@EO|X8u^U|&`)YqB22MIst(UYLb-#Ph9)B>Dm(V}dJ^GEdYt03n`C(*Xk
z`T7#*-R1l>t?qX_W3P*e$$7{};0$(N>VyvNb+(z0woqp)az=zX_xcV35zZdbXxryJ
zn%v9>oU2xmL+PM%7_F}poXvCxBsx!}3F@%(L=hcLavo0m+M~{4G-)O~Kc$R_6zAU;
zL*X%JMqAM1&U@&wKjA!ya_LSwdkjZgs`KJgDAJt2o(HgWXK5J*;gs{Q_8?|DPoXbF
zUU2TCr?2N+bpGTz<S#j^oM8TC=Pa76uQ(662x6}D0rG9;IeXDc?V9u6p8=Ea>=2H&
z>&~Vev=upzz5+w<I*;E2>~iN!%Ce|%PNj_JO6U8-VfI7k)>4c`mGcW)ELS_Xl|#J7
zxfS`m7WpG*ZY5wIJO6$V>Yq4E_K>f27AJsM=bShQ#Z%{syO4k8T)hES1a|d&&Y%ka
zdY7+(mJeF#!Tr!>7i@FqdeP(H!4<}%*vd^RqKnT(QlhITCvHK_i`%sqvfkW2ykjgl
z1?50H#O>ViNwO}AFwUM9<|nzCl-HHYZKfT38doz0wxx63=&m`%#RsF7!L6i(s!Z;|
z-(bn&CQ@GhX|ACYVA-5*1`N*OG&G-|;WnIxz*)|l&e5Oa7I~v~p0lGE9sa08Uy6%e
z<?4U!(nax@`<>=z4>q_A@>|)zJ)v+L`{WIXp6nGJZt!9+PN3$^vMDLfhpnRb!FFc9
z2}ECZc_ak<*o-7_`m;qp0Xl$9vPPEzSt6zV>|l{0up)?!fqzI5X<<tdxKP|?PqBAK
zH0#sP0kfU=fuBgRgBQjCdk;UVI}8rvf57qQ|Au`??_B&c^n+VKAJ*gxp5f=?fIXt`
zaX`=b{v#;=<t%-#Y{{{6;9S3kZo*BW<a_tx-ltO$+qw5XMh!_gIPgY;^76g^yQacA
zN3?hFVZETVlW$SNAQ#!vFzSMAmIlx}WdCeLEm|2*r&{(a2Mh;#jB+|<ro}2hp9%2_
zZF(VC9&5)nK!1aF|6sH=YX8jz=R55eU!vx2w;k@F;L=N+(Q;)W=m+d(Q<la-JO6G_
z8E>bg?C%6Si6Xg)cAIGxd&o}v8~S<J&P2ZEBX&I~w=BtS9%UCFwX+YvNSv_yZ~-_o
z?H*84^f|i;V*!?H7f1fPLc6uoAYN=Yv;~+Yc0P$fxo<bzatW-Zc3rzd{R6x0Kci@{
zbD99w=XRZ!QF~$MK*!Qv+Le2u_R3DA^C7S8CX;XCjor8b(A#L&(G3Dkb|2CxzqPxx
z9xN?(lR}`r)h>;)x7+N>DXHw8-CpuFx7$sl#czk*iyB&qblQb<1GbBOMLG&s`x1)3
zyV+N4L(S9v@MnPWvggPT=WRd54T3)QtKI-+yM1mauEGxcuWLaJvY#{$9o=cazW~Ht
z_RkZbcenlcGJwU}cRfS{Yk!LpffMap3LubT-~Qj1%}>}DEJqJB?KMxqT5A8`Gc-Q1
z-%X(9_9G%tRM=lxh@#5=#VT~W+Mc6bQH%YGI@~8Nx}JI{^wkB?+TBk#=Prs6-7yM2
zMCrW0gxLpmD|ir-bjxZXeo|Mn5{j~Py(iOO_BgL=qX1l<ZnFa#Z|HI;=zCAMemiRA
zy6NN_e5B(k+o4`J{b%TXqpS3RF>N|s42_dMg`Nm+eYF;veDrh4(Xm}$LoO9x{aA9k
z`sqKRyj*{MH+oeC=r_;7pa<#)7NTa^p>K)<PmsR00wc6j|Ab-!yY#6gXxyz2dmn;(
z^toe!7Oem7Dg^iHpX7oVtA9s1CUN?Jvk*9-ACpfV)#p@TDC70joggOYJ<EZTsK5U!
ztUsh5FMxPhKlT8MBYO21fF)V<W67s@R9_Q@t|ja5kq;<EzlHYB$Mo;oQ5@ILXo13$
z`o<mLOx2IQ55YA3pJySEuAfGs<5T+Oo+vW(NAE&mre31Wc9y=FI(k|^>1*^XTW?EV
zj2u1wk~QW<{fVC7Jgc{SwG%4N>67w6J+GI42*C^b2Z0!pLVZ>Q`gB)+^&eoD>A!Y?
zM2)_)D=d7bFQsIs*ZR=eAhzi>-vIlae)DZ`w(G4wgLsF2-f6UT>bKD5*F{)K-<t3h
zUMRuhCwxdw1%KhX<umXE2!9<0XrR#C6^%QD^EWX<JCVEqn|2A~eSx-H=syPXdxTlv
zLNHjsY7Un|SXzN1T9{8sJo|;)k*LK8vJQa73MP7S#0il_Ksg|EhQf-2f_p7$@xrtY
za3%_;BFO1<NT^DH-owJ;PccwO1Pdi%B?)XEM&_sxPe+!Mg?Fn^qzGl?LCz2g)aY-f
z@M#6avxPTwz#~Tpq9RWiH3cYFh5ACM&lluhLGHRRyDw^Yg?`Pj{+=+1j42V;#M4K?
z?+X(Xp{ZJ!YXn-2@YN2~9toEzI`mi&>S5XwAt?xbsuhlrJEKl`dkMu;;cuGxp9$md
zL9Slt_Xh+Tgy{-sdM?Zy0xMn!uKQ7YDR5QL`%3t83s7DQUgTD86so6F-gcAVWQS|;
zR!IH|^38%~8j2QSUJvxJRrs(TmbM8iXu^0Wd`-DA?SeI}S387f2cV);INuY)<su%V
zj|;krsz|W7iPI>f-CevzcdmzcH5+Yy;!Z~p{l(4gkP8qOrh{`<pt$}|paqHJ=h8(N
zk2S)!UE;TNm+cmp(w20;_~;)<#E3hIC03kw9<?~}-)G=FAnw@((1YSkN<WJi7e@dz
zL3F+oJR+ZSko<2zagzA93T7M?6K6v(Squ(dosZ@3wHipA6w~OHnJPx?LoH2Qz8>S1
zF4__2DRBV3<ub&d$itW^PPvA*EO8?RL{Ez^_rbJmaTsNH<cM~qP;^H08V&Vl#j=k<
zJSP@7L!dw`pddn_s91%zn_`~?$lVgpS$ct5BwEq={JY|yR@Can^^q8h1~KD(6m8-l
z7qq<-^X@}^yEtbuRCI_trhwQfdb&WsMOthRLtUlZpJBb56kiR!?$Qv-%JPu@*#L!G
zB@?Y%w@KDNpv_a-|31LHq-VY9bgH-1wiWU|(xY(Hd?jaE(D+G-3K0FJQ$Ip5K<f5A
zumh#7AEIrCH1s^MgQOyg8t#-%C_vmLg=|2dc1s+szV}EaL8u|(?F!7j(s0_ag-A|V
z;vwSQXCt7)q=`G}&X1Sgrv*`hv|$veiBjDx)DB70{=pSFERCdZO&pQfCy+lXm8C;(
zvb6j)`jjGZw3$36SzUz{$ECZJ1$shSM(LDMAE#1|*0GOoZ-Oz$Kfav{6t8~Y&wz$|
z{l{5BLuLQ099sUi4_rmj=#GKUV?hlXv~f0yy@LkRTof|Mlinv`gDxBb+KEBF6;OX+
zkYohQ#X%Fk1Ix8Rf6!z6c+jHZuqpnF8`rI2DgG^g5`dq-k9-L5KVtjf=ZaTWuwrFf
z4Sue_Nvp06i55TLZ(LIVSr=~0r@(dPZWp8G#*K~yhYxqX8(_9`kMm%GALmZ%%H3Su
zFktNAqUmcD`?%M%8;Im0o2chpEJIs7H-p@D37nC#l@qy0I?i;6vnQAEac+zkb%)E_
zKt6~pE@lC$r@0062xoJn?m#ey`<b#Ca=DunJI>=476J4sXI}~x*SK9dXe;8jd<e9=
zT&@fQaF6?vUOvU#Id2dvx%ylf`jE>XgQAM-N<O@5&a*!{Si{A;0rL^(*Ij|}f6SR4
zqVWlr-3Gn2obv%RzT|vgLd7d?E<M+;xk==+dBZKC^!Y}vgwo>Lxv}Kd@8I4Wj{)lB
zjvRy)E-ahgxvuQtO%UB!1ua9|*~#z0>A_YJ%2swO8?|jLk~WzZPqse{JYMYm8Nl{t
zmnfmkhkZpe=5}T`2CTj;jplnl=K2KV?9b+Yj3R)I4?+>hN@zOU!46V%Jc!+)<-kt%
zqYhxZ*ei;h?`F4nu<T)#<PQyIUo1u2Ue-Dt8bW%pHzQzaD2vpACyZqW!l-aIfevRy
zuvg?c+Q()Dce{zHYF7x%Pi7q5iz%#>vL=tQJ~1F>u&1<h&14^t^C64Hj|A9hruhw;
zvYDEemzP-99JF0#e%rx$g>{l|DwjE~g?JwOcM^=b%C4@3z%^z|?#cTsv=(xuEP~v>
z57=_c&k!tQzmgNZlFg}uU^R0Y28kNx=mYsjY#wFqJZ7JKPZyNk{1QE@W#{Q6UL9+<
zLEBU2S%5Yd-gN^6Jo!K9IF&!|?*tXQ`EN&p7|vgAgWeea`2uJ-#Irsi9_HI(XsSBG
zC-;CAN&G*Q;&+s<rpR3~f0YhgX7Q8CpyD)N@fHfRd7JlOS`I&xl1$I=jYhPc<@eY^
z{dvCmV+dT}=a7TpBJYxh;u3#~qH>q{e#-%Ug)g`Z@!R~d>#*WJ-{eFm=O6Of{%EY_
z)7F6cg71GB5^wpl<UQ-)d(DKzHrXOynC~f*ccRTpwr~_`-m(Lip~6S@K5enL%O;VF
z%2&4h8`Sp7GTy-65Sbgz6rr*O4L}K#CDMU}aG5KGaw23~zy0q!x3ZNBAs8ilM{`27
z?B7C+#eUfh%1DlpoqmZTR@Uubw8hEJ(ZQ<&vK?!HeN6VJ7WST!DalcGMmFYa*mPMo
zEdt`#Wt+PJ^NwsQ-PNVC^iJrll6f_Q_*Aw`1(s(rhaw1A>SYI?pxPkoPn)RcvhV*y
zw_nKic0%t<*^pI`cqI#-1ce>4W0PS;r|eWSI9=q+_JYM#9!E){Zt~@S!ZdezeJlh#
z@He!9xmB)=MejZ3BbK4fOWwBzoZj-^q5$S2_jN+C-6H>s=1*U_nbt3Ua)JCS{&Fu$
z&<d8DUBR<g{yQCC36YQ42bfU#T(UPzzS)PyQof8_wGr~Q`@k8AgN5LXk~=R4O0@hD
z1swOwRTSKa!FOCyi<NJole=;9ITX}Ol3Sk9sez;NI&z97%Wn-uV+y7kpdFL<rkL|_
z`3!PDpOD`?0+^HXF%hsgO}=v=1|ePk?i18b$!jSzlp()V4!xQ3+v6}YS@OZ206Q(W
zEC4ZEzVQ#BT$b-_hQ2Fu#}o+U%Iz)1;K`HQd7!u|zd)||YxuJj(3>yspft<t^40Tj
z4GZL7QmF8TeEnUZ-IR~$0Ts98**P%#w*2;U5bwwbXQEalcRLC3yYl#Pu=k$)w;!Oe
z7=MNq(2wL(C{*%T{zX54J(25cX^~tjZ%spI>g0b>==v#6kpsJ4{%kDd8|3)`V0|vn
zItZ2*^3re+U&>cs2j?q!-z4bml>cA>(M9pn1%|pRn$AGnO`-Myw7a5=5(PaJeqTU*
ztKuhrSm>#E<OohLg?&AJ8pm7la5$<yicL2lxLuJk0HD5#^D9vEQ;cYZ`JoCQ8DPQ`
z^Ju9MuK0-7hY^aK^ce0_oTI==q(V<qVU(hE3y9H*4sTc(qgb2)=vYN`2QE{b;#1n=
z9#C{lL6;6HdiJ4LRlLIW3C1}=G20J<iHbE8FFL0Pq?7FD6?HUEUQ;a0f%#>MtU3_O
z6~46oXji0AHhaACDrFyDP$n#bri;q?{vehr59EPZt~64Fv`*Q>1k+wB=chuhS$X;d
zz;I+H6f72RtFnAZ_*gx8iXQH=>Us$3BdxY=22YAr?{*AAmX#GHAzZK;Oo@i2RwoKz
z=u4|>djaaHa-iV&F4aa_66{xH$zesZYAQLuPpX3TV98beN^8zM)$mUsw_WXM4WhsL
z%C|5rz@mQ2p&F=upSGnz>N9;n-KoBF0<62$HuE94M_u0tyF=CG8^IZ-c6R_vxcY;~
zVA-d>HUKt7s%JSuVT^h@&7`sFe@&2!Q`^xxC|+$=L;R4s%dcolQl}@OmZCoD1AC9F
zEvu)adO}_HCmK`Lp}V0XO|5)^#&op}`KC{)$I~NzRXxOvB42&05DE*`gVbodr9Phm
z6?fG3w934zo@s#<#p+MK1z4&2EZwA)>gCVC;%5CV<t}+xyI(?Wn{~+osP(d5WTB*7
zf9pYOz#3@Xl!RiJ^+<}|?y(;50z(pFeSluZ;np<`v;f3E@$N?aobjAuJU{lLY`U2j
zX=a<1(htA?^eG)q_&JaAO@A5J55LcDjs|_s+EW0XYrPj5=H>kYt@BemDD`ha0fikG
zE^@%nMZ<bS?AHZH(bL~XTI1)E3lz><w`DzgyM8vk;5Pga2#Aemx8nCr^`ij#&sbVr
zZL$6YzyIq&F>=e#G@P#7@n(p*aX(N(yE~^gLC}v&q)@&;w}__y01NkCUsMA*YdUHW
z!X4-jo>0y(73g7{@i+AJD5s<xv^4H^4bXD9xHIU~WlmIqSin8QmiB+ca<(^qiDV9x
zV;05i&j2r)m6L;gKP%k@WiibCHVlnto})laVBK)XTkxf+o^&YeD3dY)pUm1+XgtaG
za;T-UMWa!qu?i0q>8zO&XHT;%3ZrDR6w3e1VGqb}c7c6Ho~Mf}m9m{KF`Ha)US)r}
zLhm(pol?GTuq=9u-ek2ou>2MqKx-z;ZMNAKJjHA$WvrF3Ujk6O&o)sSTLla5KvBs;
zy5UkhWGUoAsbWRvAYaWsy9m9tjM4F}I(CrK8=tdTXFz<zx{^Pqk+~)UtciKk4b#T9
zc88n`FRTRTYt?!m3}d53?fR0!9QfD4&80cEllzs1$A#H{0o|_bXPTnj*z6t<c4tSA
zLz@TN7KdUhyP-ncHfB#5c%H13_N!j(F|Dq>S(pD_vrJ1q%I)mSdjRugn?^&aA8T9&
zeOU9ppsiW}D{=r&2+Mc{YeShUodXDCjTtcJAPam9O$jXKruu(Yii>II`{RZg;GOwB
zJ-oAy&<6RZV#+c4c{*YIQb#A$X1}Wh!kiF%A4onofHJ-2&CLYZ{HjghU!eN{7A>@_
zpor5VhkStkdW0hHzcte~bn&$W{JtcZW|w6nTp_kHXatn~HIRbO8xrZ&xUoxb&^<VT
zP7ZA4Hc{I2HqLztL;|>1!=W&c8$pTfJGdwt7!<_);S7N=ZYw1ohjTkBY5f(!ZOMTN
zkzCUXQ1^4+k(xMeu@*%<Xa5?+L);)*dna*Q4?$A_S3))va<cvC!42+4J~Z9rexUs0
zTU^94)b4RM!yx{E>p_VE54j)c_OIinGPE^vqthYR%JsVs7E3#)><hF`j{geSuB@#G
zU?SP1?I5PIBZy7>@9C;D<Cjz1qX7`g;BGF1S(#j03jnjYsT7Dj%?+k}zifOz88<}^
z*RT&jXSh+ctIp*LDE^bjRbGVnRqhdaa;|X;|BF=RbMZvI&bhdtDBxU_|Mf15+yGVF
z=j3dv=A`dXtKoD{0n@-OB>&rUZa0l_GuNMH`xb6sDZ1sx)>Ej{ot>k#ya)S{&T;s$
z0LtO@XE_wV31Ht}0Oww2vzMO#5Vm|61~-)1(-$RTn3}?xvCK$YkvO)7RyGIN<o_IY
z%#o(YWVVt5UZ>c?G8mJ=W~M<?CiBULcoysP7mT^c{7OK)#NLKN;4-^S?#3&uClq2D
z_-PTKZ?cu$Ab>xb_3bC<;cXU28=D7AxQ50u)<P@Sa+X84Y6Y`-hqg*)`~(A3$J`aD
zJ!SS3Wq-y7&^hFKc4aDx2KFOuy`Hl<-68&hrBL+hC0q0l1YWVJ6ySQz=Fs%>hRvbm
zoJI><MC07V<eOmITXwSwmNv7=%h0tJwwG4Zt;{+fwKlezl04tBZ{`E7o$=9V^W~RS
zKp>R=crDtZ`PF}*FY$a08I!`_*oEREe|;W^#e4+$K<fD;e}U*K`*H;^BV?8<bn%YL
zmJNnAXJj#yPE;V1eGBu;Wb@WR@U^VZUntsS!&3fl3MiD%qtI6g!a~F*KSh}?75HO^
z=z5iWW(bfT;j7ocuakdW2&E19^VWcPC139g&bRU_zrf~J`HWt4{-{&_S^+c<MZu6R
z=otP9TMK|YtD5eBpM_#H&Tb{=&fMd)uAcvCDtML+{sSFe{z}BpwHIB0w{Cn9eqTSF
z(oHvXegP>LPNIwvSFX1Oc;4I~3Rn4Xi^zo&#4TL~_?;H+!Z}dGxEmFyhI6%Z&=|{o
zLqUx=E|XrtN4V4E_D$k`=?%`KoPoS1X<Yep7?aMO{vOz;xL<ZbJcIkF9pagsxe)?c
z-0wcH<uo_-Bv7)s)f>T*!+qF6Bh7_fL~)k0Ord4LIc`2hiO+Mxe+2dgPCEkf7rDP_
zX?Ka+ORl@i+{~q5xx)3`3D8__;&2psTu>JjSGo0@pyC=Avk^m(&&BP971z1f6x}M|
za?V1okegWy;tg(|EowKpnRj7K3Fl~`WWW2|A<D%m<sL}T^niP@lCCQ^q6Su!b5XHi
zdCV1e1@;rpum~)*+;2gUujA6lANZ7;@CUG;ab6-&>baggY7Lx%W`JbYeICG4*#kQD
zkj~_kijcut--0uXP2WKawli$Vbd2nI7Bvr@xx^xA$Dhl7gVPP~?q1{|DPVcD+`Pp+
z7eSzeopJ+96~j&wmzm$SR0S&ji5sb};Vfh=iU^i}3ZnbiSOSV<-@!A8g~^0bP#w)W
z|A8U<nI&}_<YHLwT$mTja=L&uj=AG)hgnBG7FrInEsG%-&vsHSR04CNi8zs6rFHrt
z)@%jN!|eD2a2{dKhryY|`p{=#j<Sok(3H$pQ`%7qyR{Z=$5=C6{xp_B@zgUc#}WaU
zvuq+cd2`u<O=!$xHg{pnRc4`R^)+^86vp@t+qweki`Wxd#NA~@M^U@SEaxFt!AeJ<
zqm?X<QuiOSOmgN_F&X)YtJxWHu-C9bbcFR0Tf7o-kJ;Kh*z|;roMnNDwXF1az|^si
zm0*3!2CISgjJeV*UC$<y!@Ge+(D|$9Y+Wphx6GfGx6N#S0_<&J`{^cXW!ZF?qm4Dv
zM*-e3zl-2(XG@2n=wOY3XxqmB<%Hq#<o#*R4B!jO$yFK1$B}b*FJDRrtwZ={WvE5-
zMdaJr&!1cfi9|jj95x-|r%_DmIR75SQBLq;H8`{Qa7r~j&3{Ucz>EC0BJ|}FKbX>%
zF7t7Fz*)$fO(<^g6Ujk!lOI|Ln{M&7^SWUExy=v0gT_1j6gnGK#D@ez?_K`b4rsc^
zf3gonF~4XFSW5WvaWLjS&pClu%DX>7@qpjriK2{;{v5+q&WDviyn^494zNnTlBVTq
zejNoVYxuRar+ma$QZD&pekkpFEp_}US|B~;>snBK#uwB3r=Fi32l)nmRxOH`{L~*&
zyy9oh0rqQNhyrIjzsMckc9EH75O9@kZ$X=z>>;tZ%Uai<%|mwPJ#cQ7<s8P4c**|O
zK#{l1Ydl8AS2pAcjPbL`T%%#Wzic(#fdR5Xl)e`zJN+jb6J$-~j6E(}n*oU|*_{k<
zUXabFq^)bR#-kuUm37-h*H=FMF|6=XIMc}ZD*k#7aeqa07FhNuhCBdtsN%B}5W^Iq
z?x=+;+{r5$p|IRdM7d9K;}Jlk6vuQhc)vnE0+z-qW@rF<KryZh8KWrl05MU~NoNHP
zDc<cz+hK)w1>}w>Zk$KAk1G0|L6NN3REi=+aSoq(_}>d9a6Xu4O`{##PhFHy__LN=
zy1zL6WP$awSJUa`IRRt9G<PLsVlUqF0tic*Y3f<}@k;!@EVCLsYwipL|6emHmtyU!
zt7u)<OrMZi|ELO@HjJmP{qv+9{2ttH1C2fR<t3=|<8o%xh;W}-10{fKq%jZV20x_p
zhda1sZMaK9xORGvhH|#FzYgPaub>F$)>Y9sabb@Doy?6q4Q*-MhweZ-&3#5o=<}Ta
zY81I#EA77uxTZcBraPSX3D|g_3;q_hhurfj81s}HQv+fXH$eeR7nXqK%rbbn`^^Aa
zH2c=;|L2N~bOZs9fh%x#aMd3{HiVmbAF`obD=kyQxFesU2<NK4fX-M>M~D65I1hUL
z9O3Q+!SW>d?jdlLJ4dhUWUe{*#S^%@+pEBGo?Ax&%?q5%Gj!(~$I~k!pL3#ZND=od
zdDiZ7=Z8SNoJ%@{S_QXbB`_<wnxhz^hg`qOKsm(z)Pm(OTlIwQ0d{{Rx|+mp(oBAo
z^`nhQGCS4}MGEUr)ATWR*+R*AS6N3QB+6MzFDQ)U_kD#Til6-}+M@Zye5lyZFXo{)
zhVStahANg1{t9hz{G#_EcYyCn_wGS{+@D~H=O+$E2NU?FEifjLcj*b!0%Svaqb*Qo
zpgrOaSv0*@gJk?#T8QkFT_o4#F4?JM7`0m#I1|`=WC^rN2$tC@K-?=kun)Bm*$0%>
z9x4l;3cX>n5wxt>s@U}%^<LrqC-f#M3XG^7SNPJBJXO)1j#j2CO!T>xEX9fxuw*Mf
zrY+GK#oTq2n08L_7bWpGDIV<xtFQ8OEYu%XE;E35S-CI`wLGQEdRTEsxpe6NE%|EM
zG5X3-Jqt;JT`$=(3U)U#fex9qFa<f5Jo)E$c&NiaA(V1WN1GEcA`>MEzkfH6PF+k&
zu~6#b<ff&No|2V_LHT|N`3I*iG{D|zQXGVT`H0Rm%yw<U&p8t*iZ{3V5q_Unwjavo
z*Nuh&3#NPzspW2c@%!)7DK`Jtq?xdPZFwYkHeW9QeT&r)NNwecB{Xm2BzhfrS~$-l
zP`$XTJ}A7oDKj8-m}{U<1)Si<=YS`Jn?UD?&T#9<w{nSl5dz{hZh<w5n_LTx&pod7
zYuH=HZ7)HshMTNJ?HSiO3_We+`dxrrJLhVHHg{I{0pz?HKmWfa3dUdXUJl#G-nYj{
zjLV=6<vN)a`u&#6r@Y%{uJ;FkY2%uQ0Q4RAl(Ks|xqalyc46Oq1EM?Yr3a@6`;3nK
zc(VMzp$QM~1F-C54YUT?#s08D?FjQ<fZA!c<l+C;))uU!-tGeF9vkWljAC}M9Ec@s
zn+D@?pOwvoR4MDyA8n7=;jh5?n5FeWt&U~q!>*?+@V{IH)`N~1JZJgsFrkIHO+*h`
z*<o)O>%)h(pz!DWrU5#LU%ncB+{HV4K!asBzxvDno0Y{^W6=JZ6Y1*~Z@9l{mD|WI
z+zg#foOKXz-*SV=Dbviwd=8>J;}`tb?R6V)MSYp~AmIA34{2Syn=L&J@ja{$ZIyzV
z&pi+$Sx+yBM=|{h)S_AB-xTiI&%Uh#Ya*NZIn*Cwbps%An8k#`<`e8(3pAZ%3Du~b
zW-I9}k<CKhLenKy_XaSRS;RVwQ31O|c_xKy8HHp@*g|^K-e<P=09MK-E&=fY+c*?*
zWo*&`w3V~j_}uwoEY=b!U9ysu-h}#xY#*hASFxiM)qBN0m<#o<nfeThH>{dg9gXaC
zC=@oar4-z2W@lG|vz6`KfUdQ%+=r;S^Aji)#e=`@43;Q9Ab5TQ=GqJNAeHl)M<CYo
zmE_`V<o}!s&URjz2Sc~YTJ}MEux!ytpd6B|_!hNnSqD8T1v2MHu(L|Gaz8lV%EIgc
zwq1UaW~trsaTM+jllKgO5&PwPDM2`1Zod}9aD_L8TlOgw77C(7D&~-PK1y-51!Iw*
zC_>B&b615C1>WA|9!XMkr6l?k#sBN&>SLNX<M7=<j}ELHAEE|7It+{tX?y*G0wPel
z!6qMy#VX~iP!K^{X&Fpi+_E8LGnt0T&t)UgCB$V3iOZ(vKH|FQYPNuL*>IR_$rjLT
ze-L4UGa9o!FWW!M{&vm1dEV!Fe_waG_pW!>Yuyys1#xi~s!+r{4;(%gwYZa|`c(9;
zhQnv#a3)H-B))qK2}9yiDa0?tCpB=tEQ)NRUlCn#@cUA1uRa3xD{++lJbF^>Do5Sd
z#HKnF^Nm=-Ud;SXJTv;w;q93N>}z<LIE#4Y?sV8Zn-vN7=TfSnY+LafYN&{aN569B
z6kMyW&SA9LFafXaAB>~k9XB5#LCv~9u<kq8WFe>Xh$#z!YMTd9)~+|%qifgFD=^)C
z_*;b7lW`8Fb=%t!+WqG&MjHm=5TY?0i8M`Bzd>oXvWpYX#6eiLe0>;kT4!ev!OOF|
zLTwG~Oy9o#H2Qld*|X)2!5CQX)0@%nEU6#HaF^<B)VTlHFb2A51d8v~r;*0LX$G6=
z!0{hZO3%Ip^aBa$(EGS*^bfty-T-=;@3dn@hWO8O5F^CnqMzfEajc5qlA~yHp3l+S
z^V~H%u~e9h_Fj*-ywuSs>tusY{+H(VclEY+bO+p2u)sS~`#QQ!MrNlo=!^!V$zU;>
zWQ)P-4*Gmu0k@~4Td&j6>v#DLF*+T(e=l@qf#3LlCtOXz-}!@&IcwTuj{l#{n548W
z@|R{P?k9DEy4n}erW=h;WzV#*c#V!uL>DSmXCoeLD6r@0odIu8K;P2b)77Uh^#(eF
zKEFQb%MR}KX7Bg;y7hg&p3Z>3xy1{c?(Cp95DdW1)7w7i4@aOyqN&hCv?w(7S%3J6
z4-?929F4Wb+nf%q(PCKsIF(~BL_gR;_uq(?NZX-NpHvA+WVjinW=x}8o`_!9O<_$$
zJk^CGl9Z3qV#*z4$`sZr^<6Rb_Xa0DE0jr(X1z#><3b`?r-d}?J0~P4MI9Q|p=66}
z%a(0sIYTSUI+IS;V#hNYa%3aNDGjrlgcz;OY_nJmUX#@(n_JqNb8~aOa*oL$%bwQO
z9JALtc;b!*ZKZPJPVC+Mj7&WCzyXfK?GR4DoOp*JrlrDgCCA}x#tCs8H>ZqeNk6Fh
z5Dl26D*if6nWd}z&opWQo2NO8)F-$eQkzw(<d4&NE7TCFasWf*WN?wj7=&nv!F_V%
zN>zd(mPT@=O2HLNw}Fr?HpniCj@m$nXo^uOp3?GQm77S<Gjt_V7|6dwtMZo<cmV>J
zP8af_`bky5=qFTL0NPJupoqN0;50e5u!s+7WD5qb(=A4e;>cPEdWr@LnQJ25VDuuT
zZiP=j^#TOfS_*H48lqK2pw;WBtq63U&NJ#tA+dOQ)L9Ilc^U%<WodMesng^rf$FD|
z0HG<9ZkOO+N;aw~-Y%u^zmml+J*Aq(yJ~Myvt8Q6zeod6_$xFH5Y}v_8+IuT#Xn-|
W_mo-+2vP+=)xTNd-lJcvQo>&{?x4B=

diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
index d5d9f7dfa20692a2d4582f25285758c393085ae2..4ba53bd11d79b34b0a5949595c714be9a20f603f 100644
GIT binary patch
delta 129618
zcmZ7e2Uu0d_dO2ZbK9x67p$?z-n+)G*jv=tjlH+TsL>cNh?SxuDs~VRr3k1fAS#NA
z2q*|577$RBCRh+q5dE)x^Z7o{`+M`mGiUbRYwbOA+RUE0_@)oInLc1|L#E(Dqafb4
zKTH-XYx2*0S(9q~>y3ZW^EZq<x>)f+QgE#`DO_vWr(7plYk7*YwIbz3&YF?Y^Zz?O
z%~>^aI_&x>{+Yjm&OSRSWUc3=EXDazUe-8zUe&zlWw*;XMelj=FfXG}8q(OYwd2?i
zG8z6cQ<(upskS-e7`db9*vN5wot|@AI?gL*6#vYDT8@8;j6!A5R7W>vyyKuE&w1k=
zU2%4?nBk_99shq;V~g%91{F<NGqxyRzSr@vV-v?(#R^6A?ADIMQC83XKf8=V`H+^5
zBjt_2_Gm&Q#}RV9qph~%Kg$v8+^V@5g+h}bmEV6*I3~yH`BQRw{I4ao91V^)sU36C
z4%l(K20D)Xf7|iDW(=V4gy9sP_<wH47P*-Q6&;y3w#e0Zu~<;fD;8D%rz`eK6hv{5
z<Lg?zXODCoQmpXG78*~WfaX-q$tYC+KLLpdr>>;<pinTKr^|ZJuUg)F`Nit8vgrBp
z92G8$EGBw+Eyr=)uRC5Z2-_ozk@b-Gmo@z?lNmS4E=?4>%WZLTQC9!tQMGL2I$kEp
z{@?#pjJmMBC{yhES0R(PuGI%x6~i^J$IDc5)sXcHnIifkFO&DIJ()Ce_V-JiOr=yc
z`Oe7{ExlM=vD$x-M#=8zB$uf;l_C<FrkhkU`I6dhq#4Yy<1<)UJ*8^N%D>2P5(|ss
z`fysy)DaeXUmO%M^#$O}BkBBB2_sW<FfYKl<vIy6yvAtjG9_M1wGHL<?t8gw8!!Q0
z!P*8I_pYKWk+}~WC1dt_s%`YE_?eR>+a+dZ<zrEnVn44X(|(9#WsjI1j7+9!p_QBD
zG8yyjDl5~=2`yvtJMc1t{and}O%`NE`#Hxb^Snmt8f&Vq%4Jr&s1~!uYoo3$bI0qP
zu2t(CFHSZ_-WhC~ofG8`6$oU|ud?6%M|yn>C!72~(iE>6or5iDEiap9m*^R{8H{YY
z{oKs>mMCO1?C0R`A<AaTsp0jQW0M)#EW5lRv%iH(_PhPODdP^C+4ASGX~C!}WU@JS
zc?Tw|lR`Gve%^(7G)X0!XFu=39EAOR`E?rrzc9O>sAUW6ivEn(3P!fjem<D-h0!8A
z=`g1M1zxt;E+5CNi;&Bf*v}_2YL1gFwVzL60%5<*9_S24sN!YI?ef`7XPrW}!hSxV
z35U%}JLh8NOqiF^U>!cR9xMC9F8Z6PGf^%3({Ad-bf{Fw*4WRt%CyV2sAPZ1XQ5*a
zbW^IMKB8~AR}Xoatp0={6J@wVCVTy1u-X>l3dp#3=NO1ooYGdr{D)wh_g6x}vUI$%
znw2r!&c<??oa?m}ceP9r&`>60+bHTmt*gbgJ&scTTO}*w+EdTV<bVFc$+%8*u9Tn5
z;ALD_I_Kp6bl!u`CHd_Pevyp(g(`aaw~GMxqjR%NF`_#v!{wuhy#wEoRe|wK5HI69
zlYva`q2*+JH#%3!>uzLad`~*(<nE(YGTu%o$;-P7GTu(8mv{DBVXXaY!c?`4ca#SZ
ztC=4;g;<vdDrEfV|5$T7f@$1;tkzU`oA4iN!Jjf2{~Mi4@@Z?}VJe;LWr{$rr^bdh
z&c?_Ddtgd=+oo!nU=NIwANqlFdtj2hE?~lcEtM%8M)NYEuY5lIOMb^$nfSm!gg<qk
z$jXEq_8H_x`{5<dWPA%;MLrOx4c?BB%fxIGU74?BL@1fO;RCM?rVc-QdGfM`N;Qe*
z;~#VEcbv1zElNl`(Yf67FZM65WK-?mtgRW@BZY=cTi}Uij_o1S9{zGjyVE&LWjytI
zEm5nI-BH*bk+q$;mZmo&i~Ro+Hs0vf*KD=LcU8*PD(vkcdWl{X$J(&C1=G}W*?NUU
zRC3RW>acShst*5EXQ<UIX`B969j89JO)2~P|BR=|Ouu|(WWOp98A8H8=9nq0mQptS
z|5wtaaXu^aN;8|<^&75|v5H3j^TZB%$fDZif7Gn4LW%0A|Ei<ZiC$*Qka=u7K{i%y
z?^*JZWbc*6cr@%CI9C44e;v4-?R19>r~HRrtS&UkWaH)kYt&z|W(PWOGUi1cx<d5d
z2b9dQBjEYDhu1Yry;@80BxU`t(aX&X(L3$nN*(6)!P1iPxKzigQ^+N`SL@pUFiNkp
zwfq0pbG%BXs4t-d@gnz<^D1-NbhS)TmsMHU9>G&wU;UqIE2H}F#Glcq8a}CnO=GQs
z*Qtcax_DeAxk^2O<z)&^ud<rkdiAN(ky-1ts!lEDwb#x%4WxGmMVV4@mQku2Jn_0z
zXC?F4t8v}#OoZ38x*cpqzcVtWon5J#{Gu*CZc~Qf1EiYTc7-5QP4A?{`Hb0d_*%{U
zCgWvF8Ezbv?DP*6j{llqF0;K<<LF(0cZ_UL3>joj!}m_6sRn^;d^Oq6DIpv457IVH
zC2Z_w(yDC>Nb$2jKAo}=x8O@Q=_VaVE~n!cUjhWJpkq`KNzU%0bGQCv&p%V(_&tc^
zMmM4>#WzwVYosIx)BBKiau1U1`%VF^zClNifn>k;EHS)`uo0{tdQm0Y@`*(27t?vg
zc{+C=NZ=(71Y0<tU{m*!`=6gu(Cim-6ZecPBY%+Pixnhs`-dz$_oe=56GuICdM7cI
zydcZL56I?dZ;~7ysIsA`^?+RFuOfiv9XSwNlbW%&-r9jAI~R~m=5dlw?@8`GhY{U$
zeBe|vugxrujdsv+Tq#L*G$PBb>&a$$It6hciL~n?iDz;<l6?BW$!uuZP^wH>Pd%~o
zA~`#sLk>bGQad8%lh(Nz5%o3FG2MqOZzWMXHjE>>BOU47GL9NBAerokoFe(QA_~R*
z3E4kgLh`Nd6xOM`B=>v^8=LH5GjcOxG#v*N6O3C;=Q|BVXG$c%h&mL|xDs+R(B22l
z9+8dH39@-*?+Mvl!pdDqGGaNkb=Xdl)Q=>~ALodn&IAgg&Lxt(9!6o=l1fRm$bO6M
z^`Y~79f+a|ZvmC;rM(?Syr6N_+YsG{wnS7dQco<jcW=%gbe{1W9h;Pq<sG}cl|9hY
zwTP{yk(^DuM~%r#rt?L~6k;Eny&d1H$!P8ja&I<}n^iZ6XtgJq28NNgjr~R|_NK5_
zCDU>5H3}u&{va)=qH|?KvRs!%=ij}^CdHH7bT^XYHueiwx{S0Q9VuMtqK(v#&(l?}
z*PmQo$S3zp?CmbVml*vqj))$5(s|=KbX?zvY;q3K@c;%ic<w{VCgK`tdpDzVrzOOh
zZoh5E>dEHiJaYVt2Q_KjZ1R=6UQPG^okj$EXCTp69jUMVL*Rc$&~>{0iOwC~(fKfp
ztyQw7MMQU_HJx`;lKsMkM7=JZ<c7CoIjNYA`|OUh-;vFxEhGuXXBU^UD>d5{qkr80
z-xCNnD2KXkggdFPG$-nNH;FU^Us9E<9ZTR?cRIh9MDklXM5=s19c%qW=W#4C)ZIvu
z4)$)J^OVkS+uts?9uW4JH(73(PUrHE(As3J&XUVnztC~XPI7Z;9l^RZCpW7<(>>Al
zSCU-8$Q-fHqHsTNp<`>j+41Jkll+(K<lY!Uy;TQ8EZk`CsTl*EiJ^5Jl6;v;62_I>
z&pJ#Jo9`(So!Cw86Vu3Lu0Yh;S4hqCq}_9u9CRH=$Hl|Q=7c?ntefO=Xdc<j@UZh_
z6LqyjHuH~@<32ijGmI2yiv4XE_ngi@1rxT1ji+Kj6}i9kkdCD;q<+7WIw~T8&Uf6Q
zHk}wlmR}}OSW9*hsjVT|w6ojvbS4|;FC>3FfEsXr6=@rvqGSI=3U08RY-Xkt!`^&4
zcZ|jLSIG*S5v<+c)V@PWq-fKE06sc$nY5LHc+{9|!Z8FyXAUH7(hzEE$RtAfEFyV!
z8^T_|a8M<?IhrILFtkv~dVV4v=?I;dV@`;-?PRj_iIvm+->eVCII)U|3c8cCW}B%6
z+(7~~_?^13*H7f~^xt&82V+v)^T9;)<rgBF=0p-l`}0zeK<7bc3EONfp<Xp6&i3bt
zAG2N@Cuqnf`z%BE|G?o?85l~YXSx$zvutv&vXE)quS6u-AHr3eNE>1Qq<)w{t(@?U
zf=KzDy0pi8LUnFO_6y(G8*_{}FNcxjTPWGLilU}=h$iigDEPI>M(-!ZcRP{GTXL}C
z2f>c^B2wqY1n9Yj0F9<opzQ{dy-yf9{%xBbYyU2cRFLJ$`4og#0`dG}ABOx`Ks@1c
z>ba^JggUf}ByoEPYa7;qIwx%yDLk*zv3@;L%(H)5);JN-=iWs9F@}!*?&M%V6v;P@
zwYPW;wQrphVP!UwXU`#q)=P<bo&B}uiou{-W~xn+x!vhJOs~Z8y=@hTVh^sFTDCTj
z;ySiZfphkPfa4<ri{ps#_I7(yuiW29_9wcK1AqH4#KV3c1Qy64&woL!Y?DDj9Q{Jr
zo*#+RX+4FgET;3RdOF@vkmU%g{Z?9vA*fo`bt$#xUk5TxswM~Fm<+3BD{~3(&pUDu
z--9gA%%Bj{M^n%p+fbmp`;cYy0qUVi#TeJgj6KOF%!iJx=g{SIizfbI_5oj6ZR#z9
zi^2wV+A30HVM>SBXB|3fFsf0@D&J5j?QmBkI1C!qvY$th%TXtY^wUjpc{`25a_>Sd
zj<(+i?M@T*d;7hjvfuL^_EWdl1d8@6q^fONgtq_eg5kTWl`VQXx^>X*4X8|%`=O<i
zMpr=nTUQsHPyWjt&?&hS5&zWw^$^;$pXgSccbEppi|WxwX7z7$h1ctUKyJI&01_AG
z-9TJ1ccyn7ii1ph8gF<rkKQB5L(J2=s2yhhT#w=iV_Q}T+)<|CR5(4(j4p-O6O5%B
zTJFRAd>VLPX7~^|JIU}*VCl!)`yHX4VuI;Yahlo8LwJVqoDHErGY=C&)mbK<K6~ew
z^wA&-U>0@)bs#g!5r7~jV*}b7%+$>X^?7E6jb7U!%pcLfhcW@tkcKfO^-;UPINU-M
z7nzN2z+YmTi_nELse8bEnQ8hOey=b;86k{dZqge%lIge?WKoPaCgG~9OtU+1AI(_L
z0)CAt354)E6Hc$!8_b)d2quPU{mllNo6L2*iBz{3HW;R{%+q6Vf18<b9>pW(GWktq
zGH^es(wK}H=<LT#>OpX)GyXRLc*69HL7>l=B~!rtoH5@4?gcZRUTc}mi8d&5nJXo5
z_?mf3gR3`;lN$i}%=Jku-oFJ*=WgiWcg$Ts081G6YH+`20%#=uf$^?Jn?5p|7DM=n
zsa1udjG6lyem^tMqM<8i77c;0f;l<?fJ$cdd(^%#KYm7_Rm_}Ea9GW3Ek`@QG5*oe
z{a_w-g?ndtGKNt$)fRc;K7{Bd|NKLMfBgUR^UYxD(rOqmE5FiEXjRY4@U;5!NVxrD
z`wE=@d8!{Kjbz>Ucq>@6&-xP$>@e>*jvX&_gS^w2hH%z-34Nb@ne>SNkt^>sLu1uj
zXw=PqXkY^)$DD_VpQXlZl^7cZ&q91HHV?-`=)!cMxzkoA8}E4aPR4W{&DzDZz>rPt
z%1qY6+>Hruf`{`2Q$*ueA7)+-Oe&e?gAi5?lMoB8ZE^+OwXX7Gj)?t${9hUj9hQGP
z&Y}N(<okD{148A`76KR}e}?pcDp9_w0<%&IN9VN)@;U=(0@kPuNikLX<n56630A;x
zg03^-Tj9GJM|Wm{8X@>In-+lZ8gt=aKprxyF5?aInQ3_Be_bGyP6MGn51#?Gt@Y?f
zXl9!rd>_<pcl?XDNxL<hIGMaXrDW9|B6_1~9gAP#z0;|Vh;HgE<e&*%%8#LQyLOz2
zIJ)ha4maHsf^emK^tg#*PcIso^cs-}`JjZYh;oG65d`+Dn-lD3j%x;+#omL#^M@^{
z1=N2xGeY6atk{j#?POg31i2Tp@he!onMxiOevFSA#d&5257H~l8zi08k&Hd~D8?TB
zRmL8EG-Hqd8e?z3b%vr=$1?VY+-9gH_Ffg{d_yN#Y=<*Y)b`58v2NKpIBawy3ZXXp
zWivXo`ENg=Bir7agkwj`J|H{4#LHLJv*~gK)8}~-B>mRVRDJNXnFxKjf#yhKx+>AM
z2}_-jmZS^lFe?R&^&7Uqc@sUo=36@bgJaj?b~OL(H<Ypq!&lMNbHZMF>YSJ}G?sQ|
z&LDxQ+QP)lMC}mM<_pLVGmW+*vLlS+LUfWJbNwGgeu{Zs2Ha_8)H6g8!rUTUDATG8
ze#4mGk><kN$@LB3QA}|VEUz+U1K{)yW3z1p;x6;>3QXge1p#QwW2VzY*rYReQ{nds
z)2<!xZyDADh<v6EHKu@>t%qd=;}i#YB{Q!n9DZT;Y=>~Wd`n$e?vOYA28TQ4YpoC-
zl$TLf#aq7Q0LTu>+oU0Sf4N{g1-7&DPc-E{C!anEz$@}D8(<S5H?2byk@8m8;UZ3c
zwkZ(z<U$Q}$@1+#P-MtMnn0K(-$$41rQDg|ujKW^(YbHsZOc(BmcP}ayDH@U{zO}x
z6wOwHY@1@11^{=(*IhQ4dMJYM6;&NlWW50CVa0{UFg>kk_zz6aC`_YJTu|J<2TvCj
z8H+%AOJPHnQx&UdhH<<75;xQg0j5c}cc?bCwnw|0xokj2kJJN~U__%Dr1XNT!9%a%
ze5m(p92Y%hF#fcg)QO*p_P6|J9$4EfeTHNE-K}u!bg&T!y3V9zMvwM%=k*@51d_f-
z^3mS|LPsIq!Ln7b95qpi<HQ%vkk9x`bF=wZDxh7SGYH33Vi_3z-1HP}h*k$oK#Q)a
zU%SGm?YjE#Na*gUBdKKx>NI3oRjKM$+u-b(`X>#TlGu}TU|Plw`UNJ={L3F`t0(_;
zAS}bRgRemtt<`>kXHWgWUs2nyKXc`O_kIWy^d5n|U^+jBmn>#AW!PRaW%T{ZWn8S(
z|F4)%NU`JV^uZs+etFw?csn3J8U#jfc~BiN9+EeSL~%s^PzIBu@(m5ac3kdQiQ<I(
zSu9w5<q5x`c2Zsw1<O<Ny+hIP)AD&p`Km6<7hgniMcz*j%SZCR4<d?Gxp1G}zmMh4
zG!spiZ%zj=L+(p+_NPelL-<@CNHf_N^5K6VrYw24t`NSIdq06?j=aTcbVRPa31ysK
z%Lgq3X`Z|@r32r}6TTqOeEFgQ5EjbkF9WVf-YE|(@8tKewxueOC!S{U{c}<*q(OkQ
z!kCG|MbVWO*tRMjOh)+I6`MaGm>r5UG#WprNYOwTpqNXSDpk=p616l%A&&^t73Z_z
z@QK0}0^w6d3e6v%DJm%E@ItYQ=F*vpQkspuRCq1`JX=wV-d?s>iq5mp&#x6D&!YN9
zaT3X5)mugIHLw*Zf*zw*sK}%bZ?R&^YH+_(IFtKQ#Z+(9-Ye!;!}6nItpzNf6b~q~
z_E~YJ4TR;2?Ov!=Dz;XjWnUEi>8ntsNXi1PT4AH+*4PwYT9|%UG+c=mIx9C_MSHg>
zkFSJqn{q@I5Zjd(Xh^$L8T$kc-K8|HL@V5sj|1S)U73c*Oto9-Ujw#1%305W^Hd%<
z3d?=U%m2Xrer1XdmIst4`$FffeBBAfA?097DI8VWzF&gPG36mj%$-o0pCSq$Wq)eS
zNu@CxIzMHd2*h+o*?2Fa@K=^lub)%;u19DA$_6_C2vU~y0U%ge)D5)|<=zG$3sqj+
zizqHAcl8DCqB5=@gyBlpC%6SJE1RbS5UHGLn}=wkls7wqEn1m*9{6iYu_<hBD0}N+
z6Qk^X0WG|x?1!<xDppx?4}d$$H$0-at6b0=#XaSoR0!jhGw;GOK{>1z!cJ5!=1@FP
z=JkciLuJ!TAWKnt_5;f!WzK#Clcs#|n8rVkmHX4s!Y9h4UZBZP?z8~$OzChC#dD=A
zWnnXwvtFafQg+z^nrvm)?`T?%GLPnvua)z$^rp&F_SlNzt#V^~nB*&4J%@`z<*^nJ
z7Ae<1M^U1@O5ev)<?dDJk`GE39gROfDx1=HuS_|#2H}5Jx@JLHp`5)Jh)U&$Kf(4@
z`DG9sRw*Yv1nD>Bfo15f8f6lFJe*WVX=355`kD`%i|X|>uxwQ|ZG_OatB(JQuH2!T
z=m5XFRJ~c?TveZF(%`OA32Hol9xCVQaIr_V={a2NRUOCDnQEWv@CXRKRBq8=JE&?g
z94@?7)AQi)u&Ve5ghy0c2ZQ^V>aQlSJgypX0B|4G&$rRRzN*mfF!58V{{`-pYS?4C
zgH%zJhV)mtT|g~BwGb;gDqEoH0nIprRYhlDdS3N2&9XyP0l{cYn96}3j!UZgh2RcX
z-SC6^D=ID>ej`-tUczsbDx5OAS5=vmeZHo8lLnLPs%h&0k5SD!1o%zWY8rfHsEppI
zJyo6YN9~2muRm~^Hr2s$MDtShd=!+~s*+Ghb5%)afPbaxO=|^t_^>1HH!5WTO!8F&
z>6=@i(j_2JCw25K6wd12eIayF7cN0eTh&i!#=c!$m+q$>>Qef8>{3VGha*?@=24*b
zP>-a<*KV~<{22~C)k^xT?NfKT15XFke+WPvRIjGg-66FW>xHVrYVTVxIja6a>A7R-
zg*V_gMSZ$2YLC>+bXY!Cr{$rRuKsy4bQ$Wiy#RQsPTGmubM;FaxxY|f!D7BDOP$sR
zwU=rSTW<uMqkg7FHCKI-k~*)|VJ5_sr>+V>o8GFI4FqYvx;y1j3e{Ia5n+)!e<g75
z)cdBuvP3=OK0JL;KcR2%M|F#fVEL@BodjIDn!5<gFY0+q5XD#ZruWc&QwJ?W18dY3
zeQd!0P=`^X$cdd<1{Yh{2gy*nuo@&VR3YqO5{9w^ux~?kf!#O=E-tb@hrkxj{(Bi6
ze3>n81=0xiF6BKU*;+jOUS)s#8!XXmUIPfPvlnPp=?2?&B6K&|I<yvYi#@qq#PfHX
z&71_AJ8aqoNaNUL&tQ6weM8C0`)q@g@SDKCr8jC4`w$yKR1esplz&NPJ-*=@rm%1P
zVUo(K2cee6>gd|1v(;TuJYoN!(LaVA#i%`FFDcM@FWAHiM4!n%NB-WXddU_<p!L~o
z-RX!emn|9szpvO2@8IwaTeK6kw`_JWXbM@URO)=TfD&6J?75K;ma@wYfPZ8+-9Qwd
z*yi+YEoV1o0$0Hn41vj4cBKmdRqPhZ!q%|q^!R^g`N4?7=EQmRhSZr`?~bYqceoId
zZsiUJBAD&m+3P5FaLt<ov5RY$3{S3Ht_w)rx#R1A^WetBqS(W!-C((w+x!pU`?z6r
zmw0i1+(L1HYvzKO4syRnBc@m`zaOsoZSLg&6md3A!nP09J<f48+$V6`D3zGV?Ysj|
z54ek;LHdx(;@~iayEX~JN8I=!U`yj>(5&z=x8o3KGB{UP;GS~xX&UgH`)4kMFSrGJ
z;r=DJ+7GyF?jS9yz2ZEMgYz|)MAUCM+rMw2e9Ogc1HORUhFP_$kZVcrz+&#i8#Lw}
z*EI+cmU0)y0P&u)b%4o7E^G{nPh5|;(0%5%l_2_ZZsAY}zi_qpQLl5EH0Y`35-3;r
zjceBmWIs3!HkGKHc#rY0+`^k}@u<4+{&Zh%<GWMmZ|8d_q1ed}^g}Cl@i+cNFmC+q
zGPrQ(pXVXa-TV|!;P>#?uuld<Q74)Y@8i211Iq!vzB7ae`KY__dx+l~jM`y-Jk3Im
z@j+1_JI-Im^0La8FL_4!%9DKKG*nOVO}C&ir};7(s`~SL`oPm!zK$1k0eoNb8_54?
zfhdA`i3Vxs`IaJzP`*(Cgkk&;dJZn}uYW-l;k@rOP+#F27NdyZhb%!`p73GxN_obQ
zPK3#G-gt+{^OwmhLP3+oUzh;D*?iBAh%|@aO&QzQ{M8Ns=JCl9i2E(SWdnfue9v(p
zE#xz3^`(fP(jUSSKC%N$N_p2X)IRcekXXfs?npe~pZQL-YEjN(i3HzNzJ3vkFZ_2$
z%70h$K_T$;jej^Dt@zG6VMmYZ2fsQLcxS<VH`ulaFO$K&RY=i6w@q+t2DTkS>zgpy
zDJ(q$oU7126P9j*^cf}|!gVK@>=r)J8s}bN5Do4;h3!tzc?qXS0=Hif$e-<?kYt37
zx3KC25Eq4l36NeAlIVSPSr~aA{dGl{PT7-4A!`|;h!URtg?OWdCkp7U3H2U9cSC66
z0hSn{E)8FA36eKF#R^$VQM)57FadB^&<=p*Jt6NZbn!w_DPl^n2@4j1G*LJ-5!Hvn
z5Sr#C3oU3(I92FI4%37k@erm9`LrDJL<sEwPfvv-*rTC(CREIXix&cGgk`3X{Te3O
zLgY`V<p@oJfO{o0ZHD5t5Kk+MZ-n-PQF|*y(<i+^u+^ny+d^UGcF+_H{jNazPPm0^
zwyIQ^ItE?xUa0dc*ggt#&O!G{_)H)3&%&Y-cq$jpBMGhgA`IGv;;V2Qd)`#lLMC>M
zslEwcXn^ot2+slFhw#G;p|d!Y)+o1#H6}!VL>y+L`N>gn`cUAHi{F;P=7g9-pLSpI
zNH0WjQVa-#`%_{njWJJ)(`cc|U%aeDaaL4QUj~RyO;8IIO`|{-EPB$+>AaZp0G>j{
z9yB=%6ED-O_M$jLfTK&|e3}$q7UO!^U~@%eo5F9T_*(?p8zt7fz;%iiN2H>-CZ6_z
zFh*R5%_pjxVoRFG#flAPLU&tCr4^z$QAQuGdtxVF)b5M@=?+Q|cPbEelK9gC)E<bk
z6R0JNC-0+{B97Pv_o<@p1I_=^#0PZk)5WQtz&{Zuy@2wmxZ4G_XX32-0KO0f`e0{@
z*FT_XFU7%>QqC6VTmmjvjL1UtuSD5waOa81hY{Kv@qRK)^2KI!cNK^;YXM#)E|jAv
z7LB1OYQ(nZ<aqwJNj399x=&h1V@xk8&kYUTFKwbt4hN*dS11lj9_0{vOa7E#J|w-l
z55Qq5-wcOGB|S}hk4X<rh~l_3{3v2NA=RU$93RPW1ck5Ex-)PmC9WB2ev;n}I65PZ
ztpdR2FR@mH7$9Bo0b8JyGaAw)$?G$09!Qhv{rXV4LJvT)#M5gwMS9-}#Up8N6^c~J
zaU+T}sRw->9!t5kP^3%Amr*>Cc8kDeNI{ge%#lPIx#ddH`DlHfv@RG$flX?nLTrW7
z*|(?`NoO~sD3+|P;r^YZO+-;5$=9mk1OGRSqGW92)LcNCw0epjZu;+aNSgI~gf{#f
zH5bt~|J)Sv7DaTww9N7VU8_p!jMg)6!KTd?np?GfbOMcSH~lrOzqfDD6H#_hGXQiP
zGZ++|p3qW5=MYLPcTo)htZVau0Cbyj3oYnwcn1ePGAW<abK@e=^}2x!tE#t5hGzaE
zxqz+D{%o-IYnFs#|1WeW4w&i>n}Mq-jX&sHYgi5*g1rnj)yS{?p_uYM0WmJBqV>nW
zC)|gFEsUII-5!inZ4^hCSToFgnBT^O@-&mU0>S{M8(qT?W;}L***nOUWj$f$#%`R5
z=-k=X58>K_y+y-`-RwU4`0Zg=?SXDD+io%%Y4c>WD2cm|y-nj0FLuvCM6jP7NIAm;
ztm$6}53-{jVCv02EJ1OI{c;3OkFv{kAU(!Lb%4-^ZH3LfDqr?bN<f}uM^h*Gu}^3k
ze})ZT4uC&<*9oDWWfOy;JI8Jw16_cPHDOboDv(_|8&L$YwHCl{Fx#pgNYArp<S0Ve
zQM3dS%66w!p)hvNpAcSPzkG+~MfM`)T`#d(6<ma~f`sBSYja2MTw$G;0~f*0sDLn%
z9Y`OjDE3d9BV1)G*C3c^)>iu<;=abNbw^OwS&th~-e9|YMG?c+i-a(iJw*@LZB|RK
z%sZ?<4eRf+4F^CN#|HF=i+gOxV+bamP5S`9_t^(Nz$LQJdcs8#yOdT~AF%80qSqg?
zpV|VR%&vY8Tnc;LrUA_(_OCv$NoBPuut{f~iS!BEj8fAX>}@v`Pubu4!15WZ!$wur
zbM|RdSiWH6en;yw*_kXzv)C$f|B{_R8*H-K@te@2IV{%&!Q`^v8iVB(TT0jdHCvDa
zmOOUJzcwh}u<5^{X>Zw@M(~@@{-9Y<0eh7E7P57(g0zUW{0dz$dyhK*9lNaubS3P>
zTBwz>6}fQ#o~`GN;sd+p7C1k$9+brY#O~;WD9YF>D+2w@dei=ra<=zv_^V+1meBK8
z$<}EMn<}>I6^d$haSW8-+3AO2`hy+z9;8m3gME(ArO>x*8`p<i?BH%-m$_;u*N1_n
zE4Ow5;BK5VZD?}m#+-uAg9|%}VmG&ex?~TxG!?bI+^$97^yEw!Gutp&ub|JR7q>PS
z`2E~X5w!!{t>vhBbB8DkafrK1p&jP(Z^P3`&WhcwDnD-eegt}oJJJt;(_9n!^q=8Y
z((BNlJE*}0J<G*nKc?y&SD^z-0GCgzjDg%tN{$6_Q$rDxEtp$N+y2gTw`rqP2sh$S
z*o1Ohln{n-`IL{pz}2BGNEf*+R{^}l<x(0poSU#5q?fscG}XAmP0B(CM{sp0!x72N
z;nC12?)WJLdX?K$2Fqyf=^zNNar?Uhew}MXBf}duZg>EcF<dca7;kc;!ce=#ZKd~6
zEH~pVxNmc-wn2A?JKPGv#BpUb`Mbx}^aoo!=k*s%?sM%U;WvQ`rq^d8x8n&Osw8eR
zB?BLD$2-H}L#`u5n9QkXLzu#CD}~7;&em-xJf(8uXrVccyF??V$K2`RAWi35G(qu%
z%N`Ar49=Hk1y8y6uK|3<`K>|moV&RlfEV0^i6G77!b))|vN#RRwO?`<Xmd+8x6lIj
zIov0jDCKgiY1hRot_dY=UUU0xv^gV>^Ir?oH=IfX)3;nt8u8?Fzl6ZFfb*{d(?ZVe
zHi9YQ@-D+uG532D=-zR~v_ewCJ$($nrQBNT+4r3MBj6vnKWI4eksE>C@|Y-nm=0kX
zCt!;$=1WuN!m^w@+S7(+Z{Z)&G{l?t`xmB1_)g_$(@|bQ%V)><_&gNH`4W21o#2P+
zfcN1ujsWk=M+}1QB;R8ZBJ|_W(+b%szLLI(r}+q)?w#R%XQS}vBNwAM%V*97{2afW
zp2h(F$0mCI0{L<DqzCaF?G*~)d(bN)l>bVrnPGhBHq<WguJd4Wk?-CFelPLr<EVx6
z%{}4pGT(A6*skyqw1gDFucK!>lD~fk!YKY-cUWHKUl$|7Xuc`k3D@}jG`6|UuU$&x
zpBubuFk*}08)5gn>Ly>@4aF@!fQJ0B{HGw8-sVpZL2-xAxQ<}%@})Ac#qk5ag8LqS
znuhi9eE&$`?(<7IbV&l=<P!QYk+0hh7bc1Kqp$Y^{&o;7AM)7Oi5ro>N|{t!3g7NL
zXddy2J#i^h`LxO4PUGio0^4KWa2<Zr`E#@+`-E>yskRJ0l}MlRn`ukZGrlpcj6df?
z7K7yl?=l?1O#ZSbnv}(NqK3ZYchJZqn`h%-nZs*n)h3t!?t+-|Z2YDPV0**YruW8M
z{sko=^ZC-j02c78!$DKX$J5xVh|doNu$Z?|F615GKNqzUettukl=7A~z`f@;(5AKz
z{H1RIeB>v`ph=(jJ!>H>;}d9u&}V*CCUE6EOW)KA-u7WUq?P>jpFsMB|F;KfUwH=u
zI<boX+kz;ndB1tkedEJ=qf2V|!UW*I^S%a<{@`^};oeE`rF{j?!m(o@-6Bj6gwRFU
zO*8hb!Ub<wZWEU51?P5Q{sge>5Mupcxl<^%^+SK{68`pwsjJ{v1W#^4AKJF!E(9)s
z&O_+C8xD61188r?9%11z;P(n2X$`_taG|BXeF8HYmR`a+8jl|oZZ3c)Zz1My=ne^`
zlmR|0WQL<SBJe{I%u!(laUK)g4D{d~7l!XaaY9%#5mF!F&{#CaSI~9<{-p3?1!{gm
zM_;%&C0Oc!=CtrH%_GhT&HJK*{DtIS;P<R>jy67@6E+V=EkH=5{ilJ#ZW`4G31zJj
zcCe5`gPrq2Ynt+g2!GC?`G2S|iZ;E43EucQmFj{}f&EdK2u}?|q?d%ow9pwYguX!S
zvQRz*wJU-!2>1wL8to{G6kKTX7bT4Ugb1$+O_m|1XkqX;a9$JQPeXWJ(1$>HL#TBP
zmNCMLV(4xP8!>saVY1xjcaX*k18BN;ThP<|@{TZ`*5d98(>KFKoKO^qnC=P9zo3X0
zrX4{r_XXc`s3iz1YQsgMa1VoYOrRa<4ont06hN0E%$|dOdL*2P0B5T3raLUtgi_jA
z_gLsk>ms&vp(AZjej+UPfWr(yCqepDXjKEmGoid6gwKUvpP+alj5a`+DX3^@pCyc@
z)X_^JISBA<;iu1NM2@g>Axv_G^KQ_+68gM@?zM1kJsOcGoS-G(H$w3hSiTiDegsRt
zO=vO{HU)x1IBW_9OG7A&gc+2gFBZB^1=~Ae&fjQLiEx=#l1qh?b5VOQbfDscFb}&b
zFgf2xd#pYQBdP%}6aH=k%g;ir9>Q{=JuNm@2w`2|zEb#u7LL9MT`2mmg6-iZbX%36
zngK+$(C;3U--N@9A*>Oa(W=FFVJ@ZSe+aQdpmP!f$%V66*A@M=Mf}RZg^MWBOLwdI
z_%ckkiPI>HzFq80iT)j8G9^uSinne9uuD8a>;3NHt_1*ih~sSIP~9yartFxf=t9G*
zePRvG0lma;lwv<9E?No`Z?V@H1bj%`LRa*t*ycNW@0b`udt8r;T{oie6(7?W{-n5J
zCmi~TeHWpF&WJ0LQ1cgm`3T%uv4R#f0!2r9r38svFVgyNu=w#ET$~s0QsON{tbPOT
zP;n#8A;Lrp?byE{rchezqPToE0=*>GI|<8hvEVdlE{ndjFY}6ch_XEq;`j~-CQ^KS
z7Jw+RTPTXFVpKeI(PEEsIJzeGr)^Bv#oAZs`*%Zhd5gGX#70H1xhakuiw?dePN@x>
zSaGBubhpLt!{PUiIE41?-4!cn#VAf(AAl(CiMKnVXX3@7wA^=JY(5O`6GRWn+a-$i
zdV(`a{7SF&2jZ1<P(Kv=27)YEOstgQ`AZQ~|3ZjqVgt(SJ{HFhMv*RNuLSoK@ti9>
zWr*{;g665neMLi`i3gSd|6II96Pg!dWG$Fvisxu{lqF8u4wIK+5UreMi@w?Ln<GA;
z`!QF{Ee7C~xQ*5<UyDPZ!_t-~{?Zx1H)2>XkiHd<o&a0E_!Emr3&ei3b+1q?JPt&W
zIB`Eni^UoNx_4smagdgXFRwyaDmFR{+<S3a4ul`Xqm<?SDE4{|;U{rFeN4;5)fPDX
zELtcPS}yLQK~{xL{4@smN^!^zD8Gn9S|Y@+;(#?kREgy@gQ^zIFJbyktaAXm8Zm)V
zK;OmIb<j^g#0j)X&q*qy?3A-qpVlX~NR?I4ZIhbTK)79cT?!97q%(Axc1rt}1F%av
z_8ft_O190N!0jfD8UmoZw3_y3c}TBmO1@iqieGi9_DI+3BAC6>+C6aZDUDbQ?tM}r
zrKP;2`%?heFWsQcL<giPlm|E{b$tiF-coZ~eLEy&(C;abt)ZpXBhqwQkvJ-;^?)Cf
zylpQbJudC0(f0{y!3?nZNR#N(;VZd_aDP(z+7;K(PZH+C<djrQIsMa8-GMMUBSq2f
z1b<0IgO9V)S6V7MCp}n-B0!3zBypgmqc=p5wCXtk!BSNk{GFGEuK`Plqz<6(U#OHj
z9MUjppbj(_q|uw;>7rCl@AXTPL>c~Y={F@vBczg_P>Ym?SE5U!r0HcKy(%SLM-eS~
zQm*QnwCQiKT$j!~hTj{~!cdUKNCRot*iC5!?XkTj&GZF4RyyfI`@e5X5BETMN78hL
zi@Va?GeE>ig`H5`ldiT0B3??4g6_T)Lc^;BDUvpgB}!M4L6anziTi=Hd@?K_N)fa&
zo-Dc0gfT_hya!P{lD1KIr%Hd&HuW^gcOT+?EPXmG;Q33Je)|E_CsI`mlo^uWVYKk6
zG`BY#K9h>q!o_oG0S$UyNG>B#yp(pHLhofuQMs_pk-E=8@mlhtA5P^-ku+y{BZXfC
zu0XmO3}K;E;SXGqG>g7%CDPfy;ICBLdJQ<+dubo7+<uZ~jfKN9>EuP2ewGyUGANhk
z(QB(hN;0BWDb1w8aFx`KE_1cCd?skVNeiqnsgYJH;OV=R+7u=~q!lVe;iNf8*<ojm
zV+?9rG;`_EcF{}<hTpB4u!ewdvuTW5fY`3NNu!4yniKTC+Nl|vfo|KS33(4vR}E7I
zotx&#Hqf|h#6;9QG*y(q-mN+P6X1I^stI7*tEqhofqH71QnGiSW=$>tUYY|PVX|MN
zqrE5xG;4MMcTn?vHCVhgwyS4RJ*3I&hT^cMZz)=TMDx)V_@kP2fv`EI8B-U<aZMO)
zq&=Z=X^jYdG`&us=Bw%JgBG6DG;spXPjjCZj8AFiQNsMRW(6%uozXb92erROsEr8E
zYKGG$x^tTF*9bH~<8502e4ysnv-FT?Ceap=U`-3U6z4UsIztztDftT1P)%dn9ClIj
zXAX3iH2=~|H(axO6dXoqTxfe$q^6L*hEbXldTCzO^r6XQv}SD-EU#%I<3N2~Q`QK&
z8=5LwLx|DDn`rCLO-<ePAibrz_8o{=&4HHibX)U{M(B4mL&)J>&9>cWOq^!Sc>wQe
zx^_nquL%i4abGjw1^@|~*0hZ&QBzg}T$1K{J$QPcIZNNohnm@xK26rtoeZ)R&4Cb*
zJ<{C$S&8Q_Rg>QZz%)%9Wtbjox`siSu5omN=@ZS$t+;9#nlt{Od8%nlefdH&V>!4p
zH6C<dWobfah3%!Lts25?O|u!W%+XZdM)6uxz8<0FX-X5&`V!63dmt;-6s<=;z1N(A
z(5CvJai{OtM@{ZC(0tNdq&3qr%|EnJ<+Da!24J~nYXLg3Les1nT2ZM9`U6pX(VVsb
z_f<25(lAw;ZtGC1)-<3=);G<>)hKE-D|?~%u37dHx*wXLFL3Xq^*jfFvv#vH9ND&L
zZ_|>xi&mh->Q?Podh2b|RxN{YyY|s|6g#v#cB5%KwJVjt@6wiKA_`aSw6zerYvqkV
z<DvcB8Kk?l*%|1(JzCpBnC#U$(F5<P?Kcp*ecD1=1@qDt(f+di+7aUs+5wxkMHomA
zYNzpF^VZht0*8mRquPPyuy*cB2#;tx)9+D^YIoHG%`vUh9n_9%3whv9Xq6mDeYD&x
zgzc+cNIwWUsSQ=2=BI6?1N@X$Ru6#FS|1wRozZR>34p)$mw^a7Kx=zN4{o5gtq-a}
z+7mAkRIs+J9&FBQ&sl&7(H2oIJ5+n&C~9HaTJ~K{+AP{-cTwA>F`~Gn%^8kbxOSc#
zVPDqvEk+bqv`=ZI8lgSj7Vt=I0c{A6(srTsuB+O&lrW9fKCmg__nP))0Pxqf_vxd0
zLt8|tuo!K^F0kFyc9@6amNvd8LW|WtE`aW~c0dejceHiSAf~(8p}PT((@vpT<UMWI
zEHpb_dxC-PzV`W9G%!Kit`h)>S{aQBleB-2hwy>c=^o`jA8M=igEU#IFeB0wZ3hl9
zJ<{$BfoZDt_y$CprhP{J^;ny>3&M15%eipzL|d8&T!yw=JlLLU|DFz$=UR?_koZD-
zkTzUpYUem2iY)B_{18O-QrnTX;ACqbwt+B5TXa{z^OviAI}*))rM*FO_}AJR`hMnV
zw^g9_M!THm!ui_W!EjihommIMLT$+)0E)B=D?wAN-AbSBciN4VohZ?Ep%i$jHi|ae
zz1Oa41^5T8tr=<`wHv8tK56^NP%GEQ;bUx5RcO1?N2*ernhE6>?b5A?`>U3r-*Z-J
zd(o!1YHiF2#QjY>vL_tYXj|<D>36N??`ZuGZP_^#PP%vak-N%8_mX})xK-y$8)~-c
zetHN`+jVOg6gzYZcd+c#rP2&@mrnZvIGd~P?ku#)P1i;X8+TpVJJ5LOZk~tDZrwQ=
zv3lwP4#8xfE;RypFWvIhh-tshKN~I%=xWzRvk&S#Qy}!#1*gH}kZ#KaL~&U6<P3@<
zx?S{MJ*t~f1F~bf#AEP#T(`jq{!Z9*tBc{#M>m!>s`%=5&=%a2x^>hSe!6m+hn><r
zqdm)~b%*XDiZi<TA7SFJTh#(4XLZ+nfIFv~wG(Usx}kkx8K?`Tt#d)T0P3J%UA>|3
zdtRqM4wDewFuJ=!b=$szB}`{?+6xyKbfaq!=|$a1T1>g5+js~8hwJJVLU>vCh{l0e
zbhY;b5ur2F{TQjceh}`XbQh+A^s2681VW4cFQyy11bUam=q`Q(^-Y}%-SW3|i|3;j
ztD8W>!P~ms?Z9$J*VeWJ+;?@eDGd{+tF*#Jyl(Pru-(@!X^AKjbYtn|nW&2|MlDIV
zDG0y^x>GdEN!C?3qL!kY;f79lq`OHA-Kn}V4rFP%7MtMdvF;)5=gH9By@EiW>aKP|
z6wh=sTSE9;_e%qM{$A+(euHVI?$!YGSC+1#Dey0K^E;x**8PT6GF6VwVHN_-)rs`m
z_E)-1*8q5}`#B$Mc{;Wj+;4QTj<9^I`{adS@^$m~fVx1pi53(KbpiCwF4E=FB`nsh
zr;PtQ-RwFv|0~h``Vusyx+{O7c&{5<1jGm3G+Ma$sH^#im@0HV<p`!yXQ1TS7hP2`
zgkN>lEnrfm`_uqz)w=nVZvLk0mIN0yy2ksV`>xwht1mxvuL<C!&!m0M&iX!$q1&Rb
zbDP#5T=cc*M&7D_Lqn1s`YAM--Kjs0y&9@r`mPI6xaz;spwvyjqZ$#q>rc^;!b3l>
z7{c9p*QqG>=ws+(yiac&g<!n&!+(cxzrHdZZ8@Mnsf6&LepV?8Z~aNyiE~Kr*$gJO
z!}^W%R36cbzk>9rzSj*XkLk5VD30qZ=y#01`d|fUPU@9Bgns(jfdHJ+^YkV@t&hKq
z;*8$afNS8dfBqNRdsc6wbjCS-!AUp_&_65$JWyX<31N`lsS=F{(SOc>WvETRA`R6r
zeeIF3xuC~57SDm6r`OgceLXpPCR|_t4vNeAZQ~H|6@4#XSVrh;)1W0%-#r{*N9j|y
zLU&akFQACl_kRWMYkKua#1x~)+8>?+{rDL4?=5|d6QYmRe_MvyZN06h8t(7t=l%h|
zclCq%f;&!M5(4EteXtCs3Htq7xKGrl>;-p{el0y}5A@64K=@FfNQ3EQ{f}4xQuObB
zMPEG9w;l(-srs!nBTv&GehACQ`o855rt70m!NXI%Wd;Dx^t>${HqZ6H(t76$J=+fW
zO#OLE*k<X6{EOnHKGZ(0(%%!&&>a1uY5;TfnY5zxN<UVK+H1XT4OrglXVK%EuOEE}
zxB~s<TL2X5qnbchq#qCl>SFy`S|@#{Z$kTHO7z3e*-$Oj>zkmV@AcDaApM~4Lz^o;
z>KAE2^GUz$CE_mAuUZW5&-y+zysFeE)<!G7=xfnD?yH^~1y5D_KQDr;T0c+);WxeM
zE^0OUj<w<UyFP9JJp9m~2t;j*K}Pqgiy>|!e*dW2Y8cQM%58=f^oibX7_lF~9R_cj
z1MD=sDu8a6;S~K92v<WU{g&L#;64L7cf;ls2t5qAFEQ9MSbBrh)1akmx6iPV24Y@@
z@wDe)zaerI{2nm;NgEvx8m`kKytm=PC7S;oG7P%~{9(f$x^<5jzMcThQA6?**qku@
zT8*ap80J+1=xgXg`InQ1sjr~(GkE9W!k#h+!RX-AhB-9zI%7CS<1v4OK${cJ8phJ5
zf^!D{Qgl~<q5fIK6l|zR`yJ04-oJ#<7Gmf^AB#}KaC&Wp8UCOz<^_ZKC|q1L{5%tE
zmkiHrh$-Aq<BO(67`nMa7isuPNu4M|FDz%Mt{QxE0FO4DNQCg3VR|}h*9~1ifcl2P
zVIcr9hHJE~=cZxv0u;9lmsK!{wHXSj*Y6r?C=D8CxJrvo_YAQ#tBW_(Z3l<<4J-de
zkzj~%g)Y$$PiuoohW-r@+5>}S1ROpz<kd%;k`0mFAxts&(LR?nL&#0k9vfPmhlg|n
zQ-m&gVrbeJwG4w_3q<kMU>imW^=F0*%341+G;;&n3&VonVUuZy90Np_;i)@lUK)yM
zQ+}@Dp$@^kGQ=(h{<UE+&BO8xDU@7!V+ec*_*=tb0|5DkKJ@A@Fyzn|w$Kn<4dFY(
zqA}=_5<@u6s!9!i+Gv#a-tf2;Y(5y;IHUH_5H}PwpA2qVbX%EW-yR@78^+Q^wcH@q
zhOWXe`wkpd8mg&<RfajV4XWBOej$41n;~o~a5aX88=(7c=u3mUABGO^K<#9d(Fe%c
zc$gBNTa1@&bYWeL8NZ@UTaEOma8%ojavHqsGKNe6-qpB@vTbh0jx;}aH^$Q<nTPSi
zYT$Pp4b)IiV+>^i_8A2lt#}!$TES$$@%#rwalqJ_UTg=A;{ze|HYRoh*&$>1g|Iwq
z#Gfj|^LNDffo6qAjZah1rN@lZ=*c;5JVFa$CyWX7GVn1rqFqV8##q`ac+%K42c&++
zwxd9E$~a4fem-qfrlNMn_?kW^{zfeg70()9#Gp85Or~F91{hP~feSR2CV?}^Sczo_
zn=06tOp8b7jqhotB*eItCibDmHnb%n%oslep<OUKQ?mV{@p3GROUBe$z=s=y>BmWz
zjeT^0UoqzQ2Oz@O7(eh+MH=t4f-cI~=>WpMYFx4v&5kzSS%%`8@h|#u-F0I{XE?Im
zF!pZ+wix4Nnw{M=Zl)!UTgHT`@Dyw8*B>^wjopL6eaHCF2d%hklxZQ1Gup<2`<^kL
z_JYM5t5$>izOlRk;0eZk>j6kK_K$}y$+(Z+B@c{ce(0x%#xi<hl8pnM;UUFloI|T9
zkBk%b=)F|qDw-vw8HY@S^0D#vN)+ive@df1F_s?zFvB>{0m7%o)Z@TCGuDkj?YYs3
zUP3R73ffeYX{<+|?JQ$1eYRg3TYP~@wz2d$YB|QUj}T0*F~<=muZ*@QnE<{vei{m!
zJY&^+kiIdVY6<0A<8?yh8!!HXT9I)K?R76UuA-l+yffPJ5L1cKfj0b?8Yj{F;=S=+
zKNKH~yJ*YEN8=qzLVYs!YmX+C83Rlp`)qVQ0T1QI=xgv-VNAABcUKx`(Wc}t#=HKg
zeKp>v(L<H-+&-{X8$(CH;Wwl8G)!uYYFcXeZanh?_#Z}d3EJyq`l!LRb2c5OY}ppm
zjsC#7n1&0`Z8haM0k_SxmxhDeP0n)Yc9;fGa&f20A<KsFcbTFJLF#I1kOjP(Ng9MG
z+)b}r!qmg`Wh`pDO-ug-evc`q43>LMU8vVRO|`ot(0!)i^p`WdO!!-Fc<@XYX_#`r
zv>_JogQl8HaC)0O=<R;U)P<65hfNxq)EzMm=}r6ZkDBVxmXl+qw)BQMZkj?XLMKeO
zn}Wv2be!f1zNS0$qB&{uq`gFbrmvo;oidG}_MSGi^8@^hsn;s>v%l$-FKTB^&xWCP
z&eX2~-~pywTDuK29l8g2kSXX9JOrE8N6_<k-qed0B|}V+Tfr7;dQ<~tnCUO-;0van
z6A|e}(;QlSy=0oX27M83notJr%ci6zD6W_`B?BH|dU6adB2DFWQHwHJ=@$)GO=YEk
zN1L2uL4D1XDS_p>>2D)&H%wkNC~PsND=z@NX<Bs~h}$NQJRt6v&e6ubyCz54P#$NR
zKvTtgrmh1KTD)l%ea!EhmeR(R1e1>l?nG0`M)*xK?V;T21C!!ka6dHt)Bv2xrmlBU
zOELYRy=jk3C+YVMsist#N~hUOcS3=GZ2Ei(-Ii|ZNcsFHrlyTi%P_V76*f;zrJZ5&
z%=C2)YR^qmzoYiTw1a*smT6i)3~X7ZdbG;*(iC2Tc(YC6qfpB+Jy-{axu*K#P<v&n
zq$$K}lT$6g^GtC?i0O^VRxk~o-kQ2i0e8Ns?$01CFuj_9rWKkd($?l8)1#pP7MrHg
zrnGma5407c#B}2@YNe)9nvA|T)w_TwKA2W^0QX0e(TGm?WZK&nF3L>I8Wf*Rt!O#C
z+~jx$MTO~~OQ5baRoU9W^o!{s4FJEIDrhQRWg6ccHr1v!G^GD#8gLfj*O-Po!sNSY
zJPql8m_ojz=45_P`!1c$=TwMdi}~|409?$2y<xJ|TsIQ9ZRSNQV6xp@-~p2z=6*DB
z+iC6}3irFrn>*3^gR6NCZ6|XxH+cg0?q*Ya(0G{pPzrswxxFuF_Lvifq1bD-(Kyi4
zyn!}*>@$BK4HGYOFK^WLoB#a=-2wBJB`6M>lWEhbw|O3ow-1?*Er;b{^TeI#%423W
z6%igcuWCro-wAVV2}&RHRN6Y}YhFx0|2=7L83>`Dx%VeTddfU!6CylqzP|xcoH5sk
z;PyAijE3K{=E^##oio3$55EECOY49OG{@eCF36lj`+tMYk+orR-rVv4s6))FZ=e=x
z&dB5O{DqnSradwj%+-|hyJ()c1THR_4^W0T+&qFtx|hvGwB~iie4Dy0!u*7KCej@1
ziXzIqxE(C7nmuTZAlm#q0WG{{&SOzrH(!)c+%V6{L=j`|No(9U&2E&Ty=Bh)0Y|o2
z^8p9AxNYve4QzMJT`FLD*PI&+Wt_R1R>$s{Q|bT_Zyw=?>vP}ywGy=i^II?A63t(a
zqD@KW*j{k|z&wanYag1s&jCxadE+v$q?qT0pm=2VrxZ)7c^i$@(#&Tb!}77syolx}
z>E`wE==>+<5s6S{m`h)y_SB3Q6CONs08Q7Qn@7(=FfYviltY+l&Y<LEmf3~wvX|xp
z{HaM*wmFYR_BrO8dbrOuN905I%KTFtir40={s=VB>_)k$H|D6xuzYK_Z889uZ$5St
zu@#t?gu|xLyoDCmi_BRVps0$?Bk31%@6221k2IB-{o4XiYA$~V_wUW}#W49`zV{Be
zkLKC5y8X#~l5Y75bMFyoS*3Z{0KmVP>mPvSSM!;x&{dh^>1QF;W>4FGuzfSnrY(In
z=KU>E`)&@St=vD%%{n1cC(CacXpFOkU5VNj%VHXYyI2A|QQK<qp^4u%iwosuwp$Y1
z0N-Kp{D5F~TCzu@*}E+JX}5)|rR#mf>t>l22c5emz8~CsSo#j6oW*WSgKSjySYqhC
zzSpvjg7LK6p=FzWmNoQM^0K&5Ds8{z58B;+z*6}b?hjfv(lg?1IYG<Xhb(E6;pwoY
z^+Z@6vFxEF;Ze&g8gU-8Y@#gPam!rFIh?SBUxtZ~<=%6e|M^;)yFq!<5_%eJewHKj
zkesrtqMZ9_%RQR=pRt6|78!rbfMi&nwfF@>c+Rq$c9jKK6m{V#(Be#=oFI!71e0LP
zv){mS-ZGZvogtREd=#OU&2%NhES+gh@q$IOlb*kemOg6uy<|B*9@212sT`)4E!!za
zbH&nt#u5>hFSo%KX-V%0lPC*I`x>uWw#`IL(H8%IU~<jUvnK%8Et8f3e#7#2TbRUH
z>RbolrX`*JoYpN%-8Im~TDsA1EN@%fccW&zWBK9$n!A?n^!<#p%%o1dXPG$_Hu0AB
zwD0D=rRy17g9OWdA4HL8k+%de$@10*fCrYAlwN;mnL^X5WJ~Sw=$RDDY#M4lvbYa~
zFxB!i<%`lR*Oo%~*fJ*+Ch3+j3h18NEYtSG(=*GwICR2uOFIn$eqmYo6v|A?l3j40
zWjQtz!k3m{npk98%IUt!u|zEcF4yuCjT&BA#&1AOuPqxWCzNN|xEQ!MmVI5}>8)i}
zKj88$-gluZu(W*!>O#xh-q00UY_Dl6RI%k(ci6nM9J~x*i6wb5*h($SXfpcVGUzzM
z|6sWv0K`Yj4O%MyWa&sV>oUtD25g@#hH+piw}jUQyuy+j4tS*{-wzRfu{@x4fUlNa
zQ$SW_8AacrYRiXX2>Y8Q(MBu%HI`j;TYtC2{0-m_OHwXeI9a(ms5x6@1JK?r*6(ZJ
z(8XF{fy1rVz%S5kvktilzuT<|96ar?;^%32@T`Fa;NE48pr5+9T3gXNkDE1wwoJNP
z>#2eBu=b{(FzvR!d0~U!J=P|a2Hk5t`W1zzHUBQy_F0$Fhs4WT|8JP=xAvk$!~v_~
z5QGP<F*)G&wr(<k?T~fiS=0_&RW#o{Vm+S=lcUxQ`VrnS>#UCOblh6n7@Q}pt#`qL
zkM&9gYQEN=uh8>%(wa=0js2{8dtT34=NoKJTYc!MI%5qiN8xYPwug(eR%iUmKy}WV
z>xY;Etj;UoDbVUqQ{o_NmLqDx){sUpIdA1?bu7fXmB>P^2j>D1W}QOQ`wQ0TF)+Dk
z?Kz2le|E{*AqdiNtEv%9FIyLEMnkVyqsw6vVckNh=&RP|G%$&_#?uV<nzh|?=&oBU
z=#_NC`bvW$#u`Ew?WQ$>2I#k}`)Ph2Yi(X1QQWrP9fjhKHNgQ<+_gH<2Ie^Hm-DFE
z?pX(=0~l}ZKuP5L)`JaEOR)BK!G%q<cB1cRk~LxqY7eY=V?p!KIyf4Z$<|`Z{HIvI
ztUzdwthF~lmuh`S8J9HcgxYZb*jlp=x^(MAM-)%2L8-uHSliKW;+|U9_6GGcn|0Aq
zAf8*_(>&~jwXHjpnbrr_5L=eD=|Q-7X)S6DV77JBebD4s7ygd!%C$b458Nwj{dw^F
z+FDNlAkSKM7R4K@`@b-GYwbvr{(Nf#noJg07tH{m(7Jy)YDLy8noJg3ZSIu2duP=N
zC`zn0+JabWwNcvmz12dyH9lCklp~6dR;dt(Pu6yI&_QL^Gc-5+Y_&ZGX}Pryy*(<d
zy<4CWmDauV9r<Fd>WpB%T8AaTVU;zWerQ^4{rNFGe6wz_g1W{UVao>1ck9rDu=!!#
zdmc(BhfZsubawC=4w@|v4L-uXi$kInwXF{4^w4c{m`($X?G9rm1F*y4mmBc3)4?qR
z?sqw`vr%((D7lDu-5f^Ih75OyRkMKeaEPG%@@|JJnh))9c$RJhVy{EzEO2`|xO{_h
zpTh<kx_LSDr8((-hjRK-A8@FC1>r%5x}Q+<cHr8;#UY0&eE~o0@HPrAjyXj5pb^I%
zJ{VCu;h>~#Xg&@XN)V{8!%5nzdD0<}5($0|YT9LS${}(d{r#WQ4(_!2dB$OUYZU$t
z(@ulttb>mVz;h0)GrBv#;Q-AD0v#^ufDdxW$bgGrho%BL@4Um}KTw1?oS^05P=~6A
zU<q>wGK1xU!|jD=*+qx1^p?HkFya8>4R_eN3&mxJLHHe*O?Aa#@l)U<9M-AfDbk_G
zdMKkD9@F6EszW(V#iJd3Xc6a{L)PB^kE833%d-07Ep2FKrSa~)_aG}rrD>L_nWbiq
zvaBpCvwoFY`LZ{%1QZY%$`%Bbt%#sZnX>m3kfDgml;8LC*ZG`#&-tEnFYj}od(S!d
z0V0>JBz$0BK}H5#j#V+;$+~J)Py5zftBTFAbj|Ah1bC5W^#)b6=Uau*igw+~o8sa(
ztUg!{M+>aVFQCs-Xmy3E$cwDL{1s@$Rw9bhmsp95;diOkSS%E8T18UGzs%}KCt#Ob
z^-y4}!fG!ige$Fr>6;r>R+09Yu4=2RLYTN^_4ow(YOMUqp-^kpMq%|jE9c`7skb_E
z8TJ~i=2QH$(PHI9C#WVX`>$Z4*{Zq-8ZB0CRD9cNwI~Ya+pPA{#ff$+pHcYKVdYM#
zkxnZQs*dckTAmDrZYvY5T0K_vrReLmdgg18+g9Gi=<BmmY=DJ+s|O2UVZcgx7kYQB
zDkvyAXk~eL4T?in5e8Tqwvxu6bHr+$Be=U(`za%I&#H+Ypi!&Bx8U%7tA&(Z8?(Af
zvHAyAYbk&J(5ith3qP{@aWy;~x60ZMyAxJdsO(_UYT5*aDXSz(-aNKS{1V)(mBSCP
zV8d{>aACrhv4n0l*fIE21!vEY)7jsFQSmhT92sjVT;{}hb}m4j8D&4C(S_0T5ja=I
zJ*q@>V{9shh&$u)eHip$2)lso$q+Ija*XjQMW(zMjT8^`W=wny5g*3ao8W~nBW?xN
zfBG>}XiIXOu{Ic-Kck9HxB(2$=io&k<NOX7Ji(Zu-NQ*n4BadVV!X!3u!9+|(=r>v
zcyB&HPcf`xK|&cnP>$d<qrDZ9VT`sl&<kh876K)L5lxi|k&HE{{F-xy(RzUL?`Ih`
za>zt6UZ+ZdXhw)0B!;n>O3h*!+ZRJ4j`83ie2QnhL(5hIW8GZzon!2$vsNPG4|k|1
zF_zDRPv;pLDzHsvy!k)qr7(uV(0G9%bHY4bWIQy$i%X1Xs?tbh{DnoxGAE63?@J6c
zow4x{&@veDsUVq*ORGS#7&lLXWHVk`2XdK_+k^35VJxGgL=K~XLWWlvnm0gl8EiVS
zU1R))zuKHU#=pP7L_T9K2YuHWp5);T#;@mLzJM|L0#FJW5n7;FiWqOz!F(|z#S5(^
z40R_gl`^yuK)cC^rty|BUW)`wIioTIA{C5(e85#QjL)I3ijg*h>8fT34x{fD<NR6Z
z)i8p*VX2nU=m=8Bc$q?I^^D!LnQdU?(>tn>krDuuCJRGc1@p~}D`$b$!q~k9PPH=}
z<KaaIW4;2T=wu}Si@q+#qDh$OW=wQIv4^pPf_1%&&9r#kW*ndr!ahbiy+!*O4Nt?T
z0mf82xH}AoZ{X7)<1>nx4>7j*!u&8p^#;^O7?z!MckM1?_jbtKW9*?zouiB+bc5hN
z!<K>^V~lD_i9TTX&~N7<!-KAiJYszI3Y-~dd`>rGCm0zWAd`%Um(e%HD5n$kG(+VN
zGQ&9I0fUbj|I!yUW*N)rMQy|MJ^)Nx=3f?y)Y>uoX)f)VZgdoIV5%QO(UG}<O4^;6
z0i_t4Gjk>YuDLMp{(wGLrraBYabq5&B3gH*EA0_In3Hta@no{puyl<1?4Q8&VqTaJ
z3*OAqKS6w$z4YAsGJ`29;>SEQm(JqHnSNBV;?MkK2e<&{ZVJQ)GC#Qu&=br^F3?Ug
zRewSwh*{7D&|v0iI%b40qmMx36jM&q9m+IZ0`_U<G8q)Yn9otJI-JS;6@3v*>w_>K
z$$SnWk2z<UN0)#*%X}e>;xAE5wGAdCnz@nE0x`@eTDD@DH3vcBn6XsS7ta*^3iAof
z&%X!uIp$J|Rwpt)I}Z~{%<n&k_ve|*;sBb=lzolH6z0bhz`VeGmx`?}GFN+I4lgka
z=$xC%OrR8f8uLaS)xV@OZOg%CFkkCLXD0J0D%8tjzA%EuZ004pCVH9qdlo>iFh>Sq
zDTnE!giqI)0aRC&$GlerxAU1^bPMV_GqV&TH<;F5aHfDMr`Km8Gnt<IA|{ifnZ-=U
z5=fRX+nnK{rIe}e#a!NGT2rlN8Plc}8s*GBD>z)iWYRUWN~T%_pQ@PtWw2Y#oHHNf
z7V|nq8ETlx&hW67ImZnmb<9umfL+g=SO>iZCX?a<jZB>%z?zr^|LrZA!%HC2!t9|9
zO{<03M2ECCW@9=;+nHV|K<i+peSy(;GSet8)x~^a0vg@SpVne%J<Mb}a`iILUxJC-
zOw}fkKIQ_-BK9+bb3q1}0!qx@Va}yf_aL+CHIO0Z1?n4S&UFDd!VIRXTz8q4z#Pzf
zO!;<L8f6N{;mmzz;7x#zF&9q3#RtqNs>6K99C!<TkC^vv!kKZVJ?T#{e^y~=lT07V
zzDzOSm*6il&HP)3LCi2OE&=zLx$I>aoMrCZfJPgZfKJ`EtX)(^W5-%&`4-b{&uXA6
zz7DKqv~hK0{ksOli4`ye4QG~sb`LHrO&{EMW!*Z0MmN?Osupx-jc0=MV6FNFeV(jP
ziXk6kbyot+i}e=0IlNi9OW~*w>);A-zO18PLBx+W_b9mItf3GKu>D#23qb-{FVL<(
zkd;F5mlLe_?BMB1)?s?r1hF(Lpcu^hdOx@jR>nslr&#wXk{8O_r^J+;W_=e5E{ydf
zy(_|5e^D^#4C{Bw#hhh*N!$D=R$?T$XjW$++>T*|&!P8UENedp-o&wbX`>L&a=wht
z1lHUC)c~?C&@VWVr8ou;lUQB<K;%4Y;SRW#%<`cWe+tWy9KFDLJP2};l}m4)ODxx3
zpro>j_MtJ2HCF{^(ph_2Kr&cIC>N8-T2fE{e<6$Y&DVg*W<A*g?8~g1i=lXhwf;kp
z99EDFvv-x{Q;#XhWeKT7`x+~hCNYn-?J>A~))(#=({<KicSzn~1yPisfc5hxm?&fo
zQ{=yhbub9f#jJHtgDYWq(W+I-+C&ef<t9s3f)SRn&cr~YoRy~qb_L6sKA=^}${s~u
z73(ERZ&kB4TEWCERt04oYFM@NV7HdFxf*(PtXJv1S<l)*>8%FVUlbB<WL;be(!_d+
zP7=+mdkr8htn;*QZDk#%>{gqFb&hHe+gWodRnfs(Nf)&`Sw&;8+r^qU1k%k~83ao`
ztin%Wx0j{u1-Z?tq`YAt>p11l`&q42h&8~PFUNG>VGRYr#2^a?O+0uksSw;S>(mv9
zjIefEgS*SR^8!%ru`EV<w~n&<=)`!Rm0$&D##k|0kO!=dl<0iOil<ZPBUTROg~wT^
zQFAh9f)(Ncm`Rq*18z^Tq!fCXX1(JCkr`Gx<%J)!jJ7a8%i3!XV#DUdLcx~(OAhSW
zv2AJfuxFbsJK&TPdy>ML&g@51=yYMXdqKmMZQlw|H}=^>KyzoeQ~bq)UAh8_p6u^K
z(RYj;NY&h4Z0$0Lc(WU6Vf0}yZbzRl`)@jD`>~to?0=kn=p@|sXAjYLzXI6n=u<9%
z?1DiHT2HWtU7&xG{VCm)3S#$b;Y=|5$&D}=!hV7hOQ+bEvp_=GxKWEojU9Xe3SsQl
z6;KFg|1|}L2zKmtC`7W~q43Wc_U!*K-m~nDw1!2o=hNyD&Ca+2g&6jCv=@(Mhey--
zFOI$JGswiVpQ2ZL0^9xv_<fGOn`S+c?L$RCN$kT^MsuFM;wlD{%>L$Am`Gutx(;%I
zU3C=BTx4hTLh=&(0HT_6QrQ_4u}owC{Tooy*<-Xv%wSJ-z{5=T{2oYVv7dNI@4sxe
z>lj)uvz<GEc7^>q{bh34R<v=w%HA~zE|*>M3G7~Dx6^W$$1a`0B<8a@bn3p&PJ9Ar
zH`wx7SSnz*e-D&G_Gh$bDq<(CfJia>1XXF2u=^<uQOX|q4JbF+m+3NwrHn1-L9v{@
z!3_p0*u`{;tz>(zgG?2hLGQR~b|8H%;TBu@1T<>ciZ1|D%l`6Th}5y|mZ7hn9ZDI4
z26h0Qx*OR~d<BsvcB~9sGy6pfceSu5)R@>-wj*7fZDaSwz)-t|9aI6fgY8b(oopdJ
zBwg%-?*pxy-FzP~J?uFJQ0!ypZbM@~dw~PU0Gm0A#yjk<I{-7t7SJ(ch+RRKO^4aT
z6gwMXGoFRWUH0iMn4o*?xA%e@WnViFh5PKjYKV-nEp}Vs;sf?igE0S)J#-1P_lW&E
z{n*CYs{>(vg8dzRnPZZ@o5DC#?4y+Pnr44RTc{cKJUSmdW<R3H)+~G65nwhPr#=u{
zPJIo0vg3T^gdy2;!ry~y4xCS(2ecz+_AwNkIBP7=qScw>@&#mEIMN~zSI+2K7<A)I
z(u>5MQ|t)8JveW_2Q*L4STz)maWr)5_TrTBAmYubq(qAk=T<vh^X24apwW+0UInn@
z9191|_;V6z`x?M`ha%yDoD;N9Kf#H5pYjhUIaOHz4dSHw!?$40_s;MwgtKQW?4IIm
z-wo_gj?V>*{xoMfoeje{Vb4P(oU@fuSP`7XRDu!7QO1It;Y2E+cb1b!4^<Q=?L|OG
zbIiUlAH#X|OX$UNv~=i><2+wZ&tE*}tzFPa;Kb2YhjW~AdN>m~Ayk)`#8J|z`#k3Z
ziYF#>*3+7j!tr|=b}w)iOn_YE$jbqGiL>q`ETwXWUV)`FPJbyR(>YI4F+c`qSrt$+
zIrnH6oW)U53^|+A{PGic{w{Ogp{(r{P6~}ThjV=;I<Io}(mI#RX`<qmYn-`MRh`Fq
zdM6t5IYz28y3R4vOX3D+F+E%boK<w#DdsR+&{)Fxhwd$vax{KuyvgYhK%tD2Lb0TB
zPGc#!3XTU=!&oXg@?{XM;{4(d#cIwB-KV?7X`m&dhSN&VZ!PB+Uzn)llu}J<J!b)3
zBxvA7bbvH+db82j#3>GgLNlk?5tGouG1F7g%1QeSCfYdZ6kTuUtTlpka2mN7QYR;7
z8em-(&d8_G=;nmb=D&wCvj&~L9Q?mPyyG~%GGO;{&QXOyKPS8p8Uvi7JXpHJiCF-J
zLC%kqSsmg8Q}}h5BYGQsBb>(vFr>Sj)z^S>kJI)f$S7xJ1W@jCdc?3W#yRu~z#ecc
z)jz?+L(WF3K7Ygs`W!Oj9MgQDO>l~+mS~c5f_B(boDI`}ndU^%k8OtY9n~T{=Ip8k
zndMxvMxzZk#Ssd&+zV%*V8^wYfQR<n-zZG&zzz3;T}N(VK17_j!ayiEb1jxPAnL+>
zL@_W|?&i%PZrt2dG`e$D&jZ_o`-UAjPwsCr^c~}V@iH2{xVH3X^5zy%0?voK&kmrz
z+>xUoe%uBMwjby6<(Pbbu3ae12XMo4pdQHG)CBGX_rz^DbCSDtz=HV-;=V<@mSAqb
z2hc*eN2bA@;_jqcqEK#jAz)5(SAGf-#yv~5MB!Xd3jIZJe@?(CBDtTRhlgjl%b&*t
zo#m!PqA!Z;`UU!;xlal~Vz@Ubb{5NB#YJBN_YzgCoa1J#qVK;Za{ov1n<Vb96lp!r
zb$A+`$=shyAezEmLnTEQxFI9ZzsUXZDY$lt`>`jyNaZ@vo-2)8P5){pom)#o%iszc
z;Y=pi{ac7+al<7TQa1O@0bpL{23P^*3b&MYD>+=|xAgtVtK45`50lGfv;+GZw}hV9
zJZ{c0aQR%n2J~I$y6*&cgZn;JCKPa&zX(SQxu3QHw1_)Hul8cDlH%JX+!z0ViBfJu
z3KVW~-_L=iGOno<nC0A=Cg@dg4^zOjl6z|-h^30_QHR!Q?kDpwid$UGs~|Pp{5&Yu
za?9v@Ds|lU{jgilUFr#g4czB%!(b!#bqXCcaX(%Gu9+)%9epia;W|jRa%cNN+PMGQ
z3ewI!N)^N%+*c?}-O2rX0X*#D)*XUEw}t!3S1{PaWo&@Mz1&Y?FpAsUvN=%f<Nir|
zkbZ6zg<l7_+*DY)!~L`cl7n2aJM@RRzs<nIVQ!Tk+z7Xgl6!Z#&sl@J$9*pm!ye^o
zKZL@4?o0IjmoaYfPKZ3<T4+gn$h9n_o!=wwR$4>Hxi{%n-~{(=x~(?J_4*T{Q(Sur
zgHChJR75+&otKMIJm!9q3H@2_OO)cU;YCrotu606+OXR3B)`Kad)^wlf9t^ejLzAP
zym>qf+lhC#48)nYXd{RVulB#MP`mP`DLm-L+d)?h-FYtbA~?qD>&7U&cp<o^J;$5(
zga=@Jc%^D6`tm9%lkCU4MlrPGyh>*%`15k<Izj+%^jn|=@;;y=*9qRt9t`j#Z#AX%
zgLwBN&=<^${SIIuyuw!6f1ctsO+Y4;7ymW5)4VB)p@s2UDDWB1o4W&w5xh?+h8D>a
zr$g}!Z<vnaXL(T+yN=>H(mo@acc2G-F}yg6UB~hst_N5g?_)ZO$MXg#50JnM^#sZ}
z-e-ewEs?i%G2MSi;%%jBw)4C@73fUn$*ur2g{P;-@B+^+3i=m$zk31u67M-$wo-Wq
zK8E=;UY-%4>AdV_h-C2gQiV<?&#?#CS-f4;n9bWtU){OPdyztaS9t36FqFf)Jp}cu
zyld;}{g=xVz68Z<JePKmJf1xTN%DESXzO;Jx0-6|Zt%)8FwX_NXMO}|A#VdM$VI$a
zdw5vP3vhx$32)o~z?Je03OIU`SGpLDWxPjgpkB^f@!x~T^QJspC2xpc)K$C^y69x7
z=Jisc!Y!V|JYd)Gq%M%D<+%x9zK(Z-Y8mQziBF-gfmePT<89=fr5pN9yn{y}+02Wk
zI)xTqK^R0@dEe{;*T#G4Lkzo}SNI6(9lQ}0T<hd*p)+(BFSQlw-MqY&u+U@S*`I?<
zFV9S2nA^PNE|{7=-U5oK_4C#~519d;D_w}W!+Uxs8V7mH=q*0PyWa@6@A3*0(0Grx
z;wf;WyaJlp`@DnG02|}UDE{(**Afo(hrBo{W_!f@gzC@6c}5DDPVg*Nw8xy})zRK|
ziud7W7@X!Ex(zbJ8~F{Ok9oTNAhWzbS3$&ve}_VUwtTlm7=<0bHw?s{?_32G2Y%T_
z=sEIN(DulQ-%TYw&iuLb6ua=3P+;1Xf1?e3Zu}h-*>&gVS|~{3!9Pan9#4J{-J?Cm
z&y9xPUi?0qFK>Pgh2VVnV!BW6%m4m0Sn}g%y#uu4{0$Z;`15ztLKDCbt%0RL{!_H?
zJ;8rlkG_-q7bw#o#IGBLUNC<JJ=!7s`81?cd<B>EL;1xYLgqAo`UP}`@uS`b7ta58
z4f-PZUNojien0Iq&hTewLv@z#O)vT=eh1~+qWRb8#23SVi^deo-%M2tar}fG@Gzc#
zoX$K6{MYGoSLgUgC^VbMkE0(%5<go{_ixYhJ8hwn%nze_pA`NLs;#-e7g472B7fZi
zcyWn;gI)`%{3lOAKaGDS0hZGFJrpv`;9t|hi%kBu*PxKazy3d1%H}&zdh0U3j0ce`
z{6AKpFNc4aj<i?#zgMC!m;b|8bpPQRKRF-zdHkZi7-&BKy-;9Z=RX?^nH&6pRp=|=
zpW6yj$lp(O8AW{037{48Pp<`b2|us_eWm>G<H6nJ#~*-+GQO`KDCK<R29PR#&LOy6
z&42efjO-Ra+7m;n;Rm0Ao~4$*kj}Jq{53zIv!0*Fg=ho+XAVdsUqolMCcccSteW{x
z|CgNOZ|R4nRz9y7`fdE16#8rD|4NnG9sFrEusiwhYM|c5e|I_hy7}3(H1zQQ{SqR*
z{Jd1?-R3vY`>W5w-(>~te*S9OCJpd&Phy_$@Z~n>9OU0^gT@eF*9Np<epm>wNB9SA
zpm3Le^c#3_j~{pqBBT6GU!d<k{{~&W9pnE?Z?gyd2kkKbke{^$V2}7m_X2vH?@tAk
z6Z{{KV7QZfi^~VVp5kw(FzPh_UnMkV_zR8be9YfQafMmF+fP8V5v-yhmaSl2GKigE
z2~}g;3l<@VJI6r~Kv&ls1vz`*g_B@xArzbiMyeBX5q$k8JaiQ-ItMT}!QWJ=<}Ua)
z8+{&vtrptSdkX4>&^RXGQXbAr&_>5?Z$X|Dh>xJ0?lSudzA1!;pMY@{+;M^9Uzh}c
zfochy2@nV=*A^&PL@W3SLE>`sofKSjg?f;nhBiyVf^RmXFGTRmCUB<&EGozk6@0kU
z0@2fgGCD7Z3C?wb3m5D-53~ru0SZM&3YM8*@Qk3V2_k0&AMe9pq6EpbGmjQj{ufRW
zOj2|)RuD{|sE89Bi2`=K;9)x~B?t~vtp1!}4vi&IQ1dS4DM?UEA@K8p_cQ4GugQXM
zDDQt!kdXoXOM;K%p`R*vrU@iXu$Y$Mbioiscryf#>50n}T<pPIW(l673dn4M-J2kn
z1-%0xR|M}+kw}gp_X5mc6)dC8aIT=60=(A*UFR{DJi!nLBwsN17JYx|x<E$-EH?xn
z(n+&G5JGX3LP6SMkRrjqHs~uBI8$n+MDWxRV3!JZ(&_o8;F%rhD-#6&1=q?2ZwkRx
z2%=wwYn6h#<Cv~05TH~G9H~<KmLP%RHZ_9KH(<V2@PK~tmO8=S-!S@m!OAv(HVCfJ
z%dt_gf+}sA1l{yFH4B`RKw1R%#lUVAtX++Pwh3D4-cq~ZYYJd=2y!T_-zk`N256Vy
zO(uNm7Q9dh(jypL4ZU8$W;%D?7A&JwY9A&6X8SFIkh_o>5Y$rT<sCurbLbotETwbj
zkf3fQ(1r#3ra(pn74$UT70BsHzb9zC571G;(`(`HeL<uhu*U?O70`PiV3EQ@!8l!-
zek90^g{5(UB^}Tcf_YT8HYpf81u`YDOi_SrS};f#mu3WB6g+z@sD2CMofR~d0>(yI
zLRUF$g`ZRc%}zK*SrmI=?;_|q2>BEXb`&<If;b6P3o#aF;f)(0F2eP6=5ZA+83(4D
z@I6~_?n1c{dLF{tb70R?D7Ab5v}3}*aTJ;3CEQ1O4{zc95XkrlBY%Q<U*TMOxB3Z3
zzJpHz!Uj8Vfx>iJdrt`82}a{dp<fkD1PMQW9$>-3)N@b|5$>S9=_#SV8FoX3OC%V?
zX<?HGNSIJE413|izPT2lMF_v4vb{**GzF8+2(#%ZepdMX5}-v1!)UJ;Ej&&^yBOi$
zv|)`EX3&8#PI&PSVB&>4zW_-PdhLZX=Y-Gf0ZO9qS`;QBNqC92Rp*7?9{?p;=tXO1
ziZF|cU@r&@KcfBTMWL21GhPy^9RQjtWPbsTG+{wJ8q<Xvo&%R5{96L-OyS~jz+?&W
z&!_R=3BRPU(Pd#E1vjq<YiB`ngmZp{-c{jeg8<7FuBT$*YeN6mp^zt>rn=yKp*w}{
zt_x50Q~k>gVcC~p3xv0Sf=r=s$9Y&P5^kvmTCq_7B@C7bcT&EkRQNJgYTp!Iqou!0
zSmuSka$)yjn5Yn@?SP||!e&|#tAq=Gg-EsV0{w4+Tf!6y;MWMP=Ao}vxatoWsuMcW
zTi;SI+)5jT2I0m_u-hnHLMh}XVX{52n}z%6vUrPdMKegN(D4fT+Jt@-L2MWPLdo?G
z;a~p)=@d>h1GG!{GL`Ok3qPmGRF80x8U}lXf==|^7QQ!##y;WF!yx^_m2?0bum}^5
z!nZrZ$!)+M6z=>6&I}1V^U*mhJVZASMuePKF_^o;nskWV6Fxyd%TeJ*d%)Zm{y7Ho
zW5Q>t5afZ-fwm&!LMz&5ObF-Jf=mj3<e_m&xHJ~7O$)bpgUkqH?BUa6p=B=R!)Jx5
zwIDX4KPc8{D|#FTMLW^jlQ3Z~DyG%eK_p89=P1geZ+<z6vZ%<!StNS^pIk(H|9jL#
zJPLfeiP|WC=Pq&<0mVb)^A6NKMaND<;h0GE6-2y5H`748MK4&o;f9Z>)fevjiXv}d
zpnjs!H_&-pR7Y=9e-WDnE<lt(C-OiMgTh@WL|+u5@1$ro?F@oMAru}D7VZBHg9s57
z$D{9*=zRn$=7fr3s0iq^XayCOg^5h-;99t-3Lk8q6CrAtL-Ef@k@5|Io)Ou3f;%fZ
zL(5i_$ckbI(V`$KsEQHA48i?aQ5*dP;zZG<;NnGDv`!_6&gY`>oM>AD2AU}9p*?((
z=s4{Y&WqA$2~8FqT8LRo5q%p6%nKq1%4b~^)pyYUAG;))EkbLmNOA;DrHLjNK|fuT
zK`-+R(VJReXNrD2fW9ozn$1wm7HxTizRRMMCXg$l<Ofj55p7ms@~(=uq{3jX$oeD9
z#Wj%?ZD#XC(kFqEFEVVvSgwntR7!M1RDsx+Wln+U&{cpIif(=YQY0FsbWgD;ED4|`
zBBm|;E)_Y_Hsz*BkOj~(5u5%@<)Y0LpRN#fX8^5Il=USBQ6);H?`>3z4pY?lmMDQX
zVl|@VCWzFEo~Fwbb)w$C;Zvh%)EAtkNwkqFBbr6u(XqEhq@xsnt7yUp<82dt&<d_y
z^bHNBL-fq&FxV+-*$xl8L<uqQqFc0WAw+sapU~phD_TVl-fhv!VmQ+$dYBB%e$j8V
zbPtFePC?<0h?R!97!)110?Lp@<ggLG4U5KU_C`c?`(XF3$oC(}+!HBZh5o2$H$`*q
zi@3Cgj)^*tqwj$z?@4eEMJKx8(<9L)I@phkCO*P+O^AY)19MW;OgB)cM7t<9IxRYs
z41+VGr`E!m$D-5pHk=h%<fmc6Mw~qWySC!j=AzS1Tyzd-_Ts4=z&MCciU8v%UJ(b*
zN&M<P5NEL+1;1Rxt0)@dDy~R^h@1F33N*QkGbotqA-=W&oTqpj{bY}chuIME65Brw
zd*0&SaaiyXyI5$O<16-z!zld3rF4t<xHyyI@&01_ztI;UexGi&2a2!Ky^9lKT|LlF
zir=HZXplIF;-A6d@<4DQ;$=_5;3=`yQgET-1@FV)Y4OK5ArdCuNtaf_#hOuY5n?5+
zT9M+7!4&^IBQA`B-LvAb)fh~aSW2I{ixw~b5i=AccKHs9vEm#p`r^c1eE1YE_Mxa%
zg7{fltj~$NJ76hMT>3V+B=Lz_h@2PyLR;HpvB(CNQp7go+6D1;y0>&ueE1(IToOl$
zss1HZ{AdHbNE7d&I`?$(*c-5vA^!drxNPyB?_lY&nEM)Fu81c#!KWPYi<f|QReZY|
zFuCH7D?qM^Pws==Jn;@&_?s_|rPt?m@s=Y1yCIIC-&}#1Apt2A=WGQj60_qe|6VMf
z5<|a4{Mk)_mWuaTLGh;e97RXU#LFl;ST4R^2`?(dJa?F=6rYNRzg6N^ssyeUW2=To
zO}uLo3N_+@Rv4@m3us-f6Td|V>w57oj?ilmM^a|9QM{1ycTM6gj_9*Ai|yJ0(;^<D
zpI56mm<RnfvC#)I?c%sKkm(Q?QR2Q+97U^7m-x{HNVoXkF_`EP`_cKLSNtg*VsDEV
zUxh-S_*vRW^@~-sY7L0<6d2hZ@gMY#8WiuR8$(0l@q@q|wuo<?f!z`D`xO}WU2*+)
zP`oGhX@!YVah5l*?~8w?rDaT<90=}#m`AawhvKV~fO#Z-i(V4r;@7DXe?nXz2yRk*
z^8zrZ#N)AOoEC4K1F#wK>BoS6EZ$48(OL2L6BwY4#Il=$qqdT%Vwks+zycmT$-C>o
zIY_);go}=nPhvovB%?23FwT-U*F(fb^6_0Xx=QZl!GxQnji$t1()}IuJR~i&qwth0
z9RxWh`9%d0FUfst=y^*_v<CV}YJNqZuO!`41J+McWd)hzl3dz``b&HQVJSf3{TxgL
zO1vn}d_wZYJve+)Qk{y%Aj$Rv&<mFM(^ZyG$$Lqd_0y7HBA^#0Il@O@xP(Qg&<Kf{
zVw;f?ITw0oB&pjm31=nR=P`#-lEDDF{}3%<Wx+&@Wcg-v#!40)g{3%2L;<*X$)-wp
znjndq1vw}AiMDl#k}f*FCP|uZ1LnMBFGW?7CHGbVB}Jm4_{#-J0|g>3O4d;J<&xxF
zBNS34wscxglSEenI$biDNA)imlF!)C$dtSw26mRjcNmtkB@T3;xh%OsXZS0U<u5=Z
zM>3y+?N=pVP;MhvGM7%>*ChWs!fu|#Gz0Z~$*x4`U6<GfL*$0Ubq~M_Bq4_&QYZ=8
zhQ1=nE&3f7OG@9s|6iX|BKgY+=1V0TZ$RUwL{2W2NdhELESK!B0%(OK?iw^IC3SZ2
zqDoRvQ&KJIa)2|pBu}5g2x}xklo6_xeDnnR>Lgq5fYeK#S%S%LkXSzh%tlEHg+ZGn
zLFM3@C2Tr$TUsQ8v?p(s1nmKKn?z5i?skcS-pL)3rIZirlz4s*jV{Sg6pQMX3~q(p
z9?2(k>h6_13W53ClI{qo_eoaMsk>kD8s$j`BuyVd;f~}MP4}SWFnx|}NOHUcBEyoO
zKf%aGERu!-Oz>UF#RF))C;9C!kWtB+C!uj)ay<j?k4cv3Vd8=0juhmf<Yp229!dV8
z>d0})3Hq^3NFoQ&I4P;v2A`%RTsoXhOU~AS%t(Ht)TE8{4uvdirP=G?nw@l~H_Y2h
zEw51Y%0XH)3Q<StQ96t|N$<W1yUx<W4rsVYU!-%1tMoG)D7r~6x4{c{X?P{fdq|hl
znbuSKKPo6bCS6at4KFF1kID0v`fP`uk2E+0lD<+qT8sRoUvV)d$EDv=`I^79-I5Np
z0BOcrzywNN%}_icop~0WC#A3L$IybLtKNY|u++R0&V)$w69IEd`Zrx;3YCsgQt-6&
zA=N;HN$)Yx7cO<&49N)Tzx0emO7m#C&q%jZZ1b%2z)DC)N&EeP87+NcHPxTRNHgML
zFjnfAiV?<1*X@T-@zNt%=u42Uqf_@esfw1ZL}`W$gGrKF(UhK-Hhl)YWa$d}h)s&L
zf>MMRq`Cee7o`d&ytpLgP_{Q!+Ddo((xe-7u$wNu@G+n>q@I6M{x4IyD+n4{Qg`}h
zZMO96cQAih>S{pa73uyTFo`)*UJ78YO214*U#|3tg}}ZhEvSb=p7gmGaQV{P*WuH3
zsoWcSH>BHWNhy$u>C{~)ZM+GTB5C{?aK+MXYXMdwUBagKU#ZlEhY{YC9-w1jne>kw
zD3(i?YM@ae?TdhkN@;u@M5?5TN{CcT73<-}E$L|n&}yU`X(LxF-AzB>I_a)lI8!hE
z<yj~+NY7P4p;0O+09cdsX9XIYrN7c!xJBAH41X=HQX8tgY?D?G!)~YaLpsxTNkz14
z>6U(dANoDgy<E&!uT<>=$=lKl%9!^_f3<-^zx3a2AOq6xsi^dhw7&ofgVIy9Z61>T
zUW2}2=}C&zj7YzK9U^z78!3u&PuffS&QXiBuN`jOmwLa9F^x%gXh9xG<<T(sP&zLG
z<dM|N4t|eIf1=3Ng!CYtCMTu6jewbwz7qwJY3V`wQqzpInQj3;md>a9QnS*<PoU36
z_6_9?ZDkrKK-<aA)S}T|_WQfw9AuV0HZ&Y%OcOMmWOLa7b(XoZ!MVuNJJ9DU`;wL|
zH<>+ssmWdTF`c?SWPU94dCGLO>o_KBt%it~%yS8dw+z`*Jb1DJ%7XaH=FxB6Pv+(X
z%;U14Y!H9hIw^(}AUkdO2cUs66)m$TWV|1se^REV<t|8el+p>ovUmM3>=0QP?O0FA
zzA1;nP+8J0fS#7g{LmOCTPTB1;j%Fbg+<6V&|V-?_E!hg&&Zl7+I?2`1wG+WvL)g0
zDOxsk29hzdCm&isV`b^rVIofUGX0mQc$wj8%us^NnpVwovbmIBN|ZgO09TSs^FFxq
zvb-|5oh&;-arG2g|7RG}1=$hGP+pXk{{&|)$y(ANk}Au@CT~uf%y0yK>9QRZ?aGh^
zjX@z(cIF=CAF^c2=@^+U`@0LBmu1@%(RoESpYAc_$X@k=!K<=0v#^vaOIQJzeA(j@
z81{A9;@=>0L-tNSNP+B)aEzr;_QGp0SR~`#1ZJ^pCDn73$iATjc&Th37p~ouB~T4+
znJg651C}}EvT_;pD`da6VrnX7BTX<-C9|X7Rkdv00*Ky{eM`am8rhW@VAsly{s~ei
zo4*Aj^|CLgA<`gQR0tD|GFOUhHOZQPhlkCwj91}yi!4oqzE;^sl+A0C)f`1%yKHR}
zoUwGso~Q5Ib;|myFwibp{#|h0vadb?>5(yMMeUV^{s?kgCZ}CxpKJ$hyZdFf4Il%u
zK3Y5P$YyAJG$>p5H5!LxN49_)mhCgcwGmlOJizYCKBb-NJz3!ZxKUXW-FvuiksYB|
z?3k?o1YCR|3oirOL)o?rjN*~(2ig#g%kH;>Ovv8-8yb_cwY2Y@l6ks9VOl0Pz|xHD
z{z`y8mgO%4H!J&}HAHOW**ZYm%8Q!7*~$M$&!4?~F5QE5kRPJgiKE=|0iC*?<bS^c
z;w-=L7yfE4@)1fuy2=OF!>*hBS*o>km!G>1&O?5hO2a+nk*k4rOum7(#$NI+Iw^X~
zN9YLQBY$NvT=SLhrr4REe0Mi6kISE<N*RB-J-rPB<eSSu0_A}gFIYMu&uhe=<fOdi
zGC+gmBcDSfSnf-k{}B122M{?WFQsEfsJ!15<g~ntu6=~buhUhqaJgS5%ty#S{RJda
z-tUgSDEZPqfD$b~ErxoGTuMoWSowlF*o~9#<6#i-@<n!(|4WePQgZ&B{0!x%66N1h
z_%%sh@e4H0%ZF$wOqOq^Gkl7inTw%akoT2=T$CGVi+f4Fjb3%B@@`k4q{*$$qc2?^
zO<}<d`4S4`Wy)E<p)X55hZetVIg_&Km*w6Psz19T@1wn5j(iUVNv_Iko`LyX`K!Nx
zT$7iKLNQOS3j$icy!bl2xGs00g6|vh6LeXoKt5H6zCw8~ou`WAS@h|WVtFW?Y)j;w
z^am}K+Z03Lrd(DGu1vm&c9Z4uWB*eAuR{Jx17IrUFOl6U`O@`}sg}#a!QGN;;vrfi
zZythcwem~~57f!qQ{jHSd}{y(+8}@96<BJNzx*run&k6FpwKMODTPRjJWdFdR=I#m
zPTJ(tgP75F`R7AW=#cwUB+b$(H#GyMOTNSpGTrije}{gLd<`8JdgXD}(7!F;y%<C5
zldq!cy?*&27bp(MO?P18j{MMkpbg3&QS5C<j(^~c2Ty)v3!E8|&(B5QUHRk+Shy$8
z`2l29ZjgZ7my2nOIcAZ6)C>ARuAC3@P##2&%p>`3`l#Bt{Lei=n~(?B0cKKuIS{T*
z$?G$rKP}fY;M0tJT_P+!mitpB@T`2nA~f14_H6`btI#|N1v^D6-M+F{biW4TpqPFO
z#8DwVhdvjDCAtNcTov_{2X|A{)6UUd@dcH}dMM`7M?5?gYmMNJDL(7M2)z_S4=8vm
zOfs18QB<Zu#8<IC9Gssbn!c`bTp>eHb&kKn=mg9FMfXAY8>ndg0(~bG(TAXLQo%E#
zF-Wo6av7k(3XfkwLKIKj!RSvZ-Z%@iP(}BP_$8fIJV}w(Fhwz)D8dz=P69MSA=?dw
zNJX3p+!@8(VSt`h_&f$^lwyGjBwF!Q6G)80x(JxDioH~&7^m>2LsGnA)34wX6uSc{
zNODe*OTV&2#agO+OH#aD5AM8Tm@XwHE6fycN>PjiVcISzGO0q~qT(ycgI`jVP^>Xk
zQBQRpX^Qt^p`NZ-Is=6a#lUOeG8H)ta9Ijl+Q(%p7CD2vtdRS`rz?to4%7F~aulQV
zqQ9#6^C4t%748gJx~5<zLO)NjJ`G&H!j8fc*A+_o#>)-G2|8jHDDskFzEF`)^;ks;
zw*X)lD_$K3DN!u@0s}2obgf3;O~u<HD3mGIUxIqMqUSCQRVdsM%CgL<R6G@hiK<d`
zE`y0`MKTp8-cpo|Lcd0#p_gK<BFh?<>J;mXpjfXs>;#1dh2$AnYE%TihQ=m^H|1`d
z6|J}lKBq;|`7yXw#kX-FZHn%lAnl6tV(4`!s%T5lsfgT(X|{AJ_NSt?Te1CXusw>o
zbdKv)9D5Va+*WkZFKIxr_Zx`ZQP_q+WKfYE2D?Lwn0|1>ir<?dGNSma3wn1Ii!{K#
zr`SuG#!<ytI$GXWblO0DO!0#^^d2bAz7Fo8Vur30JhCXt=`)k#ilVugnhC}8OEK(8
z#di-OGo?6r9gWipEnShAQG8BAd#q@s<iM=rgFbj@qs*tcfUQzZ32Zy%*Yx<>D{E+9
z<e>bC7HdZ(`)@eoq<l>KB4_2G9r|39qqKQ&Ra*9Dg1RXa`RH_4swf}kp`4&Bq^Gif
z5`D*%Pv5~Pyp(lRzUr-PJ_$4*rR4`G_$r6D!wWy<Uu$9MxH6Vf&;H6I(NGUi8efEZ
zpz@hFK~5;&o`J$iWmOJ53{sYOz>8p|orQM&A<977E1psws{<FR<gWyGTA4Hpv@qp<
zTDHQK8UFAhLg_Mv#z<vRB4ExalWZ{hv&ul)=0qve|Jz(DcU6LmQNHsgBx99&cW`k^
zTY5O+mAi*9zy#$(s#7?p9I&EvUZPS=d(<T5t91Y2ymIM2bS5j8b^tp?xw0STFDRw-
z`I(E#Zu0w*vX|-<QkCi7LLp6A@(!@mmDN<Clc8KR7Ydom^OTItQub3OI9oY7gvq<C
zd_Xt$t|-@0?l(tyay7mGt}4&dMj=<3N7eS%lnb{4CQs>T1a`jCw;O2Jl`DKPi8qvT
zIvo`#ySyP;sFZcXiz4OWf54S0dz!)BR6d}(wK8S=%TOp+jv8RTLiv&#EL1AL=R>4Q
zSwvS!s+Ifw>H8D6lpPd`t5If9{H0boG8Zy+%BN`iT(3ODhrtHrxkrF$RQ5)qu}PUk
zA@pYDOAi3rqFlKNLu*y8p!@G_%408rv@5&Iq1T}d*n;`(RL=hsm|e<7I!ARY4-`YM
zNBR8sFl*^mmQn@CZRO>4!0uBHe+|WcW$+Xf2b4X7Aa|5K-#~v*IiJdAhm<LFG#yrc
zeHmyY%GWkQ{jSnXp@)0QuP9hBsys`TBlnd*(5f}2Orp!850szKuj`?*Y6<inDNpTy
z$hbw>M@4ND%18>fPb%k;%#<?G8#2?%H_pPD8Rb_BU_Vx-ZN-$%Dj(89VWZkx1<qFW
z;qy?pQ!SuflD(>%BD@YNGrg4@RZr5U$4TWvbrsI4zy5*SE~=7CfOb_46vCdH%Hlxj
z6L*#353nAp#DAdgsk%ayjK@@Sp8@ewy-@;vZ`EOUSn^RFYJ+)S)yvC(=BL{CU#d>^
zPdFs~RW^v9&IwR;<-mNPDxY?fCsdugK~AbHN$3kwEu*@qU{y*D)I(H`md)rqrK*U9
z7on<PD(*b38mGl1OeOCD7q0sGNjMy#8lzP+Qe_mt(izp&gCJ*BJPN@@ss5ywakT0J
z?XY81XDIp<t9qG2J8`OjK&Z#7er^GGL1lUe3KvzbE*R$}mA;+gpBbt{l$FR-#nW#+
zOV#`{WO7tK6fV1}vO|^DoLp5P?Nm!tA(60qQ&qMHB4w&1$|{tr-lku7h031(K9#C`
zx@J}dJt$PG-k_uOEmbWYNNQBE6i};EJ^2|V>s5{clz(qfWzf;MQS}Rz7Bs0c`vBUk
zs;`1*tLo+Bu+*kHlz}m|t9(K+B^|1TjnMB@y-8VxZq>`QwDhPNX;;~+vU3C2ZPhrX
zm-|$MHc;<ZeV+j60o87MC=99$v@Q>+UPSE7GG|!je*&E&Di&SlzpFY&nbmu$K`LSx
zRlPx*>HDhsgMb-Rt<6N=1C>=cxQD8Hwm^HNI&6lc<EqUf_%xx~NE_uzmFPWi)2ehC
zpl4LmOF$m0W_uwytJ*LG6dUztLZDb|)gMqK!d~5;55FDMU(uP?QGNVJ*mY9x{|&@h
zy{8YLuIekRFi<!3-g<EEYHzxd?4ec`fOx9kT?O@H>T5s4Z7+2a#dLhsZ%x6Hue$y+
zEcvN@cLDmiy08h2{^~b7K>{r5sSn}QNwtwmmxI*)bm$0Hze(5BLe!hSLEkBL6qOl<
zs;6m75U%D?E;K@&po2)HdfrwvMych`!Ha11_h$6Ps26#I#H(!zU@$=){vFJpQ~yap
zsPpRDYDgxl-=kAiirR95YE>?&4^m(|RlSmGozv9iuYt={8|e;9mOB4S_>`><wE!(g
zy^#_CSJhQ(;C`+;bpkNg)ZS-dFi%}h$+>*>2z`X3K)rw}0t?lflED?JS^ve})WMV^
zC{epmX=$n2(?XvxDOdBUYN<lKiO$lM>cgjCuuAPHhWTo>^jFNxEw$B0;Of+WQk_G+
zx|IU84Qe|&i8QPCGlABk{<sa!w5o4V1xJT^@-;Zqsop@rf-d#^HYjwfuV=zSkGgUX
z#@VY5^r!vju==-Xw2r8kW<%z#noXgHdukCaRHN#$7twcLopT3hW9sa4P<WtL($VLk
zdc_vNJW{U>gUGm=`7Z2EsQ11JkxBLPaQHi=_M>aG(`xHtkQw#c&%nZC_3HH?v+AF0
zY5!@XDLjCgwbd-?N2{IYb=q#&Yp(AHnuF%B4HO+UU*3XwC(UBYP&#X#O2U|2G~Kje
zb=7>f9er+^O)(g~yXJE`V0&m*bi%x+#>orN$20=6;HCM6F0lG)`l6ujr}+$vwPnt6
z%~{HP`)lU8fdpt;YS9^}5m5^3gr=RY|DM#mM3L|yjhJ?Yr!+2C;b^F4=W>wK8h_eB
zg=wPG(HE}Cdj%*Fn$;=rB2qJ-ES=Gq>1BLYQ$){5l;-0X&={@xWHZz)F`D7|z>d{i
zpr<lU({~nA8n1Drx9K?zgKAn6HJKqGNt$sAB%ar#Q~*0!v*iLrQZ&9JXuPCZLsi15
zng%YoG!2JP(lvj-0!ta1cslfFYS@%0$<hQagNNA~XWDmOwrDOyVot7T;^>Ewqj6sZ
zn5&vVy1$#N>01gD*EE09L!GBt847Y;lR+t{Ld_Et@hsBtGXYbqi8~I^5=~en6iPL_
z=tCJdH7_SXp-dw$0d%?Mna|Kyp{ZI4QmGlD7j2cs@<JK(t2HmuA^MhPB_+9QG=(l8
zwVJoT#I!YNR$YWMjhg4q0<B52i(-_`8pRMyv}k<W;BUL;6m8NvG#}HOwo|i$HZ)zD
zIrLKO)-Z-)zDM)xOCY_P7^*|Ltr_?eGuo&5+tLO%`Zf8Npg5p;dkC#}G&WDd#GvMz
zdcX{60%?66)`Y!|#(SD3A)Fc0ocM1quNnLcdJi?-x#)YONi2fGxTgPKOwfepS*p{U
z)abrJ-;{<YN8hyO*VAa6(Hx|&o<7!WFQNVRtY$6k%j~q7dqM2AuOEX!2kil>sBqL;
z4A5}W=Kg?zI%^~AVBSSL=nqg=?V2Er&`ldhi<i4LS`APS?d=c2d1|Nfpzf_TZG{CN
zZAv)we6>?ly5Xm-{T1Z6_Q#WyfA`mRQ*`8n_O1D_ds5rn2KR%srJn;PSZkUF3DI76
zLE|Z{&0jDPru~dU58>MM-{D1sc76p+L~6gg27_m`N}7bT+Cg7nMrpejf{WI+SwkU4
zyKD^<VzsW}0E^RZ@ul-$yml$wf4HDMya_TFwVzYC`I0t~;_<24JznTb(+1iBEnWM4
zDCQzVyDpD@&)Skah-7JBpw%{8`{gE(%i7$HAXl{S(<UHC`>7|mtJ*rclaZ_4K)-}*
z+DHEaEKkc20L+rFU4INFu4}7Y(0W6wv%+`_v^Es~EYyDRA^pg;F&S{JSbK(+_Y&>F
z^?)hWE}$D$H?{6m16ZbgK!4_Pt?y3&t<WaXuAx%vnFUg%ji!aMTFY*O-YxBP2u5F{
z4PA_J)>^bbQ}sffc8d_$_1agB@U%fYodxra+Vk|lH)*-k=xf#rUIA&*mhFLJtG09i
zq)q$p49vG{-6+u1q5awgmO8cnQms~(_9BI0y0x)%8tl>DO9p1IHib%6Zfobwfb?lC
zkMF~qer-(&*a7WpR6BJ?d(j*EgIeF8p)sUgYk*I~+9NV>BijA#ki4tSJr0q3+GAAD
zJgQBs1G%s5ra1GMwnPAh2ijL3q4A;iYl>q$(jK82v2kri63B#BS_#QX?QRQwjA}-^
zfwudPwg1rNzFF-zKSRS#_sVj}*z1;4QJaHq*)WKsPSpbuCtVmVe$KiDKLgE0ca@ST
zuJ{*67^s_W8+~ueUFTy35f5GRMksjd8a{@FW4fQ{0OqCJC4z#t?w53W{(N+qyP@H$
zTi=KY_S1F044C7(bV^+Z>f9&|e?k}O1fNdoJYR)EknV>>NCxXhqG2LL=SkNuPU-GH
zgT_$Z``aOMTK75~A;NS552%Oh7A^-^gzoDf(HE(!pzPQgUG^G!{?6(~HRz1eRnvwy
zTDMUN&^Vov%H892hiP3-&>cvFPv>;IR$&y0I_X1*B<T(=!6?q_c0UivWL*N4)}`o<
z{sWN<x&?HgxTt%(4C<G3vpd11>f$AkOw(<83X_noTRcwZzYN`BJrpx_n`vgVbQdT}
zpRMbv1@>iK${hG~MfbrbIGm$9O>fhyx**z!<?5X2(%3a!dH`I@)4f{^y?mYPr!aV3
zXGbsk8#)F>$qRI+DDP3Ii~brYMY`Wk!24p|m!Cu3Qlh(0A<I%-8wCV!>JCPLE7SQ7
zK(t)9g0|!pI;{)1O5OiXLa|CWFBNFjx`^8_cuV)uLMYVehO;43tNZ0?*saq!F9xaC
zSyO1JLHCIdP#SeJf52dqZi?!Ynsv`T1F#m0?igiCT6OG8Xl>Jd*aozA9b*z)hc1Ak
z44pdHy_ke9-6u=&r|i}-=`h-(^WKU-TA!|p9{+w_as*5a=xnLB`;P9@m%t6`(tZIq
zr1QA|^<mv(s^}Zh9ixipySi1BPrj$KM9_w6RQJ3S9KNs9@_;?2OQaR*fzF+3wjSzc
z1L5H#ozMZ?xbCf6@M%K#bP?R2)b-LLG^JbE0d871O^fx6?$auWJl4JPHlSy9?camg
z=v!maXsdtO1%t5DOCr!{ug|uuf<XuU`&5GAsQ<7Aemm)Nk^tkZS5XAtMX#lrV^@7y
zJIuT3{|N?+yMF5@ARhWo6~^SL-%l~!WBL!wQ1{Zyzk)N~`inmS#Yca@8e{R*ufGRL
zKmEtaXgsdpz6YGY{^SG7{{`sto`GVZe!&KqIHCW5d^@T4qI5!#zF-N=2kS*)XbjPd
zQh<F*KZouMhwATK1v#yk?Sc6){hL?eZ@7NdFCY>6X-a2D>bof(5vA8h!$P$F2YM=E
z^zLzhj@6&pK>5EoeLNpB@p^{>IFq24y#vv6`hPwIm#812d!<QwMi>;&>+2}PlB}<%
z1wBPCE<oc2{d|fHU(_?`X7eR|(p#9(RK0i``qK0TT#P<lzvVmhW$4#X{vcET3{7m7
zexHE;|53I+jqaRY*4Gq5@rr)(AK1;&yJcb6SM`T=Ah~)kA2@tXf0NSbdHU_Nugcf2
z9EId{z48hgZ|F-Y!c?GtNVNoo`rV(vV39t70!_vGqm(Eq(SJx$uTs72Q;?hbtF)e5
z%JltK&?wg*`4Mb|zQzQYO1+^7T$TRhI@qn&KN^F^E&VDX8f)}H^FV6#MoJvi={Kf8
zp<ZvIiogc_*HpjRsCOO!Y0@8{pH8#B$O9Hy^xIZoE?V^;Tmfm*>*!8JyG8#jtp*+X
z#h+m?-THRgi1p~_9D|8o{q}Cyy{)h71=pu9dL5Ge`XNdP59qsgLh_FOnL3a`{pt}+
z$&g+^`LJPqCY_8&^gdLqaaaEboi^_2N9k-gs(*`e^Y`_6)leAITUOA~=Yjqh9fTh0
zJ86k{q@T6{8Q1?#<vSC4*$$9N{nB><Go@F!f}7Uwqe|}?{f2pfd91IdlC4?&UD{>Y
z7`BLD!q&i|$da95A60zX8x)^I&%tn?a?Os0Z~ua%li_Vk1?)N-F0KcRi=jCTimryC
zP;|N(bUsjYH#Eed(Zdi+krPkD7q!qoW^mdI1uugi{pP$4wTEEd$FS!DeDXEir8m5v
zAt)ar#|^K~2bjO%NfQhO7?QpPSfJq`Rl}Sx3^>r4_N2kG8j3-N2v0a1Y^eMQXd#9w
zTA5B6Ms7hQ)X=>cpr;KwDiw<`yweDnNW%g0_l#jD{Sc!Kf6+!N#*lmplCg$8V)&b2
zaMojf&lw)mCw3DJ`|P2RW{5ikL+OUCUr_x^hQXd9ftiM%Z^BZRVfY!KWgBAXlyuqf
zfQ~R%3|?!XpJOPYB=uE;l&Ugw4Rz1L(ltZ*Mp()-v{UJ0zTqS-jMoj?&9HRCkV*%k
z0z=F}%tfKW>O4e>47JZfq}Y%xrTgzCh8HQ^Rcgp2jhhCqO)ywyXw^fe+^}#8jTMH-
z=b>0>_><BBRfePeaKG9xOQkNi3}rUpY7EZvfKqE{r>lu|hCurAL%qT0EEF0HIvIx4
zXej&_m`#Rvsju0v+6)Cti=m0`?6exz2Y|F0{#Xfv?FI#<bUF;b(n+(^u!{~IT?V5Q
zV7d)K^re^{!#28o)oXaO1ZcMniz2}F88{I@={NjId7c47WiN(($Iy8i+@Rq%y5los
zsHF7pup#p}Fh?wgZu;!aT|;dN*n5WC_rQ%Bmh6S-eZvmgzm6F!^nYC+7>>}N`JrLW
zvp{=fxE&8m;|517a1(};RPHxvu(QCKDMP~dAdd|jli}#BVUsPOZH!*GA!2K6Yry>4
z84dn0WN)<0T!A+ZM&~DB(9t+fheIdhGy4GQZ1j5@qAtcyl3~f!*g|hZH{*CB(A<r8
zdw}L)>_|nQr;$fFuVcnyItY0gr)l%xZJbyMOdsPc#p->H&wGONGqT^Nr^47v>0y84
zHOpcs1{l+Jz>7d*@~;pLGWOD|BiI-}4eSu(msD?X%6K~reW6BX4m><<eC{wr!i?Ec
zh=d!z83bsAkx>H@Y5d@0D4a3=bOw%|HRe*@Kgzh!5$e&#*WSmFVvN5<Kr+^7XxRg_
zIHQ~*81crt^sFQpx4i>r&KcjO0>MOM%{lZX8J`xz{qsidYfwlw7Ex9%#n|Wo?t(Ej
z2hLnHX3xj4FBy;D1ea>G-3PriW1ipqVzwpz9<Z{FGxR&UZ1kOm;1%P8NANSpSYC+6
zt42MYopX&J(Cvq7#y(1l<rzbN14zDc@fNsy-T2itpxiL7dJ_f;jKW!XTWH*M6<m?=
z>TUED8(*ZF+Y)07g+@w^3ob+Crtwn?y;RDKztP7i%8hCNV0;zEMOK)KO5+|AhEiqx
z>uGpVZJgZ;{aeO&v@lp>+)26kTB9{pE7Te5)}gW9I75Gk24fd}#G=s{OAktuaYY~W
znvDi}x3m}!<ib#^@kfdnbQrfCr9XD3ahCP~UB>5YFtl#t86W8P7!Os#wO-@ESLnNK
ze4k3^`;1Hl^!tq$s5WH4xQEKq?-=JtLSfLj{|Sf;88hh5GHh(8l>UhE4JyIAYur8u
zefNy{m(VwATs(@t`^GtS&tsJvGnU2x?Sb*&6EOJD7*8d%kBr~ZpM28zkp}ux#w<Dp
zO&h~I05fBpafjq%<ElF_KWpSuG{eR;dK<*nWH|*Bb|(LKp=WQpK${c?)A=VcU5+N3
z`>^X|>OTrFXVYf<4lHwAOwq|O?`j&O;E|i@V+sqnn<Dl@#>4b#6ij%U-rEMWW2XL1
zAYP`s<i5AbM3G7#Q(F-leNAca!e2jAKc!`ln~ppK&fioMfW81zT_qF(O=oD$I$>(1
zDB?+zry7lxAX6&^q=QW>DUlmu`i7RNQ>GSr9fX<!X=i)d^d23?!c1=+1s85oB>_9a
z^llj%BTY>|Lg9=lfD*Z9O;6E&Gs-l;f%nlS4?l>+m>%?EfU&0C1u!3H`lS#g-sH3w
z)0|*2{kRJ3IaBW<U?-aX?SOugDTlV==S^*NRUp}969eoN)13!^xnTN{HWU|4+h@>s
z$#j^4WT~cnO1Pz&9#23$-Q-Cd#SGIOKDbQN=C#nvGHs%gm~7LIJlMNz`oaf&S4<X(
z7g}>o?sQ+`nrWO)K6$2B=0iW<6gm$w*G(rIVd;kHoi5B}foTK90SZlDmjSfMw9OxV
z#U_a}NQp_D1yXA2r9z~eru9c5Qf7K*DY$Zzg$MNt(=YG9LZ#`S_c4enQ>ukF4b`T_
zp|Etz6hP_K8k3GTZnY-2Zjd^YSd9_Zo5CoV(qKw9L9x-4wFC-HrZCDNHJg^wi>}4A
zGYx&MrXi|YYct)VHNM@{HxGIprl_Z&&}sUt7#?<+8Yw*7ZJM}9S=Js?m>Wp1DXtNU
zw@nf{Cij`1q{C6a$(7#B1ExbNXxuS<LFN2|CO6tg4Vj*90~t0=Ujp`sDfWNx{;uhD
zH;{X#9b%x2nx;Mg%6*f^a*#38yH+stz%-l=y@#eh=h9dHADI@}qjTJJls3T=rbS6G
zF=>h#$C#!}t?lTWHvLUG!5P!&F!~;wjI=46HLZC93N~hY`up0NHMDBknd{P^U~gVW
z)sPP6w>;psqxmgc7<4h~bZB%nyKjJqo4Kpz2|R!9=0o<F6AyD=D?mNXuY3pYnAv#~
z%zK$tg;4Z1`%w{^kNL&rK=U<6QAwzuIf6=_j+>tg#_0Xce5xD{F#k<4f<SZl9gq`d
zJBrAjG&j?xJIGv4OIfgaY%3Z=%t0q$&vMGVkE%yQ&3`H3)M@jo{|ctfRXd;&ZuZy&
zOA%)8Quq{Uc8rAn8S^o!zCLS?qn}rldFCqgqRmGsBpPELcZ1up<~6i?j5F`bL|?qw
zWDT$cbG;pWI%k$AVk#5O6*dq_vY5Z`gyMPgpDzM5*_?d@ohjx!l)=4Vet!ar7tQx+
zM}5gWTZq0?^U?PJlV;ve)sX4ta=JmCVdht2Fqvi*T|LP%FJ6VdZ1a`t@cy!S{5blq
zn1AR3SdLk~1R__>32(uCuGx}qgv>Q_I9=q-Gw-T}OuqRp4;t6a!>civ8|E!{p;2Hi
zUWdUHn(fn|P-K3aezL{pl}`Ys#O!tsBBka>I&kIY3^n|%F#nSbkxH`-oi3`(dtZh~
zwK>-Y7H*lBE{0@{`8^ATduz>azK>DVnZ@*;t~W2DJwSum$`+!HW(T@B&}2>?g)`0O
zIWK@~F<(dpTB|wj1BkSlGrk5&ySe@v`Z~-l^b~iRzkC`)>N3BUhxzR`uWA8wkGXFF
z4E37xouPi)JpBe8Zu-o7QsGU%`45Us4w!TN;qV=E6MeUO&^(<DZpi$AYT$;=j|A{y
z#LQWN#=GW^^iaQN&MijYsQCpUEZsLRq~!3JS!)l>2j-R-xc1P@62O^9W><=JkDH(K
zgx-XCWF>uNVA5=Cg{3L;?RhXiZO*3;yUm#Q)6U?r`J?&ZX3am*B4lHI`z~N?twrC1
zv$HOvpNGBmCaU6eupasm1|6-J(&Rf?&tD5KoUK#nrRZWE90Uul*1vrO5jSfO%Cfp!
zS1zY2cMt1{UC{8f?x$_<G3)uBFz97{>nnhITZ{e%@v$DIz>=@^-g!{;vwm?JvlnbV
zMzM(yYnx@Tbjn&X3`?QbYx*!3r>z(5M`M_E5nap(xBmN2j5or17hP74wB{T`-x=$r
z)#$UFwO&B+(irR4=0ZQ#+Vlow;;cWWYLa;Cn;j5Muzvmk$T{mt3Y#WcAKd{*ldQuj
zKXTrB@EQ1<Y<=rpkQD1hZvym!_3O0VxM+PR449X!m(x}@)w-R2+-cSeVqqcOx}HKg
z85ZkPPGB>w6}0$eS$F3`G~1f}7*mpCt>{DJRckJlgy&k%)q`BKHhO{lpQG!J%d-07
zW?7n*nKm>>xihm&-o5vpmYQXmY4x+rtSl?*1ytOMD9E0&1ldDG5fG3KB8coQ$VNnz
z`TL&u=X~zH=X=h%_kEr_&N=ttrd<{}jkD~I)Af*SJHMrnl4Ey~+)TIZE>e^x*RGA+
z_jz_*6g|kdbLs}Jz-}d-aSH9$e}%RpJDV*XDvIr-QBYW7*AR}zQo9expLW~sUrHS;
zvlHw`+Z{WV6y&a*LmetB?Iu41%RRff<Ws4#`-Yq$)pjpZK17Y(402Z0+RbHx)Y%<<
zine+?(Jl;ggPoLK(MG%CkAQ1}`n#abc5dH5T8mu~2du4j4fNu***#tha^G%7BRbk{
zx6%uGJM8Q!P3VE0<~4A3+7(d3NtfN1bcdtc&W+pwJ$7%r2SBf#@FleM+1;h>eZSq<
z1oRHrt%?H6LpvU2a}3(CcF;We$ZjpAKn&S^O2^#Cb~$rl%&^@HGzpE^ZM_03M(uiC
zK*sFWQf}C|9X}kU3A^VOV@N0MwopLEfw7TtlN}j{(ouPk@naA49%3A!AN?@HMA0lK
z#tUUA9buF$#aJ9=TuP){UdI@pH9+riM#6m5o?zS?0MALrrZ-^4DaKkl@tkIuDV%(U
zVT*@)XGRRIQD+%kavr%bB50$0j`1OFhR-v`XvuJ8?9E1{8)MZt^j=`BCby+KgF%i5
z4@T$_5KqR?M|8^eVw7b;s5c{)z6RmL(APtgFJtK<i1B08<e=ow$f2Wq0HcaFVu6fG
zdY*$AVf0p9WUQy-OfcgeHb@BL_ZOfkl+o&h5e;KB#lgY|#?SPIM>4)4r{HBqTq_KX
zV!VF_ZMJB}$A<unVT8_yrdWpO65!()4&<keXKc#{YXXBo2ew4UD9vR_j4xYYOfq9v
z9B@|{-_kRa!kF?iI5QX?l=+m&Xrr0wCSw&Xky(sqC<u|wSo${<<}f<k0MBJ?)1te1
zHpX%avE?&*=tNP#m`X?RLWbvd@DwwOGa;sg@!8*KD`oscVYJ(fy=+J;V=SYeqMTtm
zhPDbu9L=3~8JVsqRWdgJ=VM?*(eqfv@Tvx&n!!i_OAX^?U-Yb&!KXa!I)?2A1HGtc
zEL;h_4UB(6(8ET?zjOv@Vg%0uPctLA8Y9!fV7vo-D`U$Y2yJ7mr}M#m#+wxHYiIP(
zUay1EXa;$}NcaFUI~gAif~AYWn*m%mLqORAJ&flm^P-pW*=MNiW2~`-pxDp2`xs<^
zkw_lwhm6f!s2^mQ3SrYDhMDXhVyq`$!DGgKBNPrZs%b77VZ1{rBBP9zbQm3Da9g2%
zoFQyQ<pkr+S>T*x$SAAdf%(e<41y!`Z#p|1WIn6|ImBH17Oj7Wnaf{;v?I(}lqzzR
zxncp-A7f_H4|AOPfIN*Sm;;x=a*Fwn9HrCDrHSA?!<<T<J7?yePE?*{mS`c=h3VA_
z+&Si_v;#ZO9GwH=%9N0M*^SvY8@LNhb0S#Wnc8La{&_IdVo~eKTtl01FJ`qB(!80&
zl$PPc9HPCGFY`@$DgBteKcS=k%thaVC4f2m5o`)%I%lF3#FUX2<s#FP1BJoNul%4e
zgy~ZZ63Xn6f+dU@w+0r5Gq2@gEG{wKaA5#ZR_6NGQH*3J2H>~9%$!b<*eIsrE0`F~
z{C5UQG0YAg)W<U)`G7Nl`GE`UO=OzL37W)Q`X0<qW`<Ib=nB)H+_YDj4zwdlWp>fW
z53ez!XM*!OlRpRQ)0i{oz?gLAjym9M8O%g~2+d?(pc`{HnITuu!z||EMDXM=y<O0!
zTg=!<$j)VczXvRN%#Yp#FrT@m5u61~4u#PQnI3;bQxQ{3+04bv#Ws)<CgU-zFJ(G^
z4-L1OHUFJ?n3<G{dWYFH1ER}q%xSb0s$l-nf!e#wo$lybCG(xdK-^=#L2k7wX6P2M
zR5NeVlTgE)P9Bq5rpyDf>zJJ_&{WSnISeZrn3FU$G%|M&0oTNg*^5#$v(f|Bw=kE*
z0p7~2t$?9z%(wSqobEGiU;9CCJ99UEr@MpM{xQe{=0ZDEb~Brrp{a-Icnz|9nX@N=
z=wluu7iB-QZ7Em=n5XGLGsyhp4d5OzUtW&NA!hKaC_QGLn-437nIDG%_mug~t7scx
z7EK2kWxg^UQpT9xHcI6gXD*>sf=TAK{{lj+MhED1V9i|(F^;UVAm9(OV)np_L#&mw
zF*(e7ox%=IteLYQ?Fh?2fr6u~@*<4IF;;6IO2=6N6)2rxasNvOW38g+@f53rT;8Wy
zKU3J?3~SdLbpCT@&8NM@Sr&UORJgD_DQbC+mE?oA^DI}26u7e3l+5YIitvR^7g!&S
zLX0~rkHR}1tVA*F^<?cEgkCQe>%WYBRu847_^>w7Y0#I|`YL``KUU9X;QU!$^B^UF
z)!s<^&p_5&U8oIats8<BAuRVq07F>;<j4+VIeiR#IO}Ixhc2<q8dOHGT;u>;X0>es
zXB4Z0u7yRjW@NyM7}nrnXo_Y1uo9JVtUt+J8qb>j9@-LF8(07&u`;8eKADxCLSMPM
z!aCZA-y((8cL|!VvI2!5sjR0N7=&xAus_hJ>#Sd#QA%TtRHAf)^}#&=GFWGBVPrB{
zMcydgWQn(dWU+FtLvJ=~75Nr(SfA13af?+l9aiMA{Fo4(&zkfCO93lzDd4t3*4jA`
zTEq%-gNkBSVJCnkte?rm+pHk^xyo2SFd*g*>+?(?%2_L#(N@74xQDj8tTj=<RkAkh
z2B~7T9s#LlMbno@YFNDm7>imKs|b4QSSxO#vXRxc4*Hr{c?Th^*~W68jiG5_J^K?_
zTUpI#(2F+KMmo&iXI0awtb=ts0Eh>yY&v&#vNq5ur;C+HC#P<fUlok$VbxN2w3n4d
zdx3tI-857Vuo|1d`H=P80>~U>eRCY}N37F-p)|yDKMv84S+=Q^lsU}WOhLpatW95_
z^py4MIoLG9TD2F5G1mQ65Hrroaf87VEKV(YILV6rA5_?5w~a~%_TRMkab$P!z<G%M
zNC#nu*%6-u?!^9ZF91i_vE&dq%0BTwh(5*+4FT>rdxxzB3Qw}T=A(FuJ^2`j(`*;I
zHgSf1&<~Z)>}EReo@M7A0MLcKR|0aL{mf@*b7lX%4*)lIG@X?$uy?Ekac48uLZ%n{
zeh#E~v(4e)^kE-}L&=vdXhX@5{mxBT@6Y~aCVAxp*xjYDJBa=Aui&}J{^U#W1hd}{
zL1hSgcrGeK*#qR24`U}$@59;7%b+)c{on*xBH5R3pz<<%Rs<@e*pKOaAI<iejZzFd
z!4GY*>@9Q}jANJW0EuTG8$nwF`>ACr-oHflAYD#PX8-aG%)i3kN$#T*_P(j;#Z|V7
zP8+H0GfMni*Vr-tK=ySuj~>z+?DA2JOgej}6r34sW-_E?vi)d{y2*aJ9HlJw%l2T&
zX8%R0v$xnjIjGEKCz0DIkG(dNvi$Pd|N9e-1?&LYC={|g=wow5Y~Epz61I#sYo+X}
zFM+tt_PqsC#-4W*m3P<|zsJbjWxpvw4=dR-=?=y{_Pxhosbc5X0A9^LYmdqrwqhDs
zYT1hpgVeKkCxJAuZ_@zT8rd#QFt~{wYl8Y__A|6*w6M?cfp2B68bsTDb{@U{?d&&b
zPu;<e>ZR9#EgpmHPWDH2P}s$;qabZJo81pw5Bux4F<iZD1!bT0;irJiezqemRS((q
zG>Htd2hzau$i~k47iJ8xU)liKkJ%E6Y7Mi$pscJX>_@YK7-4@s8yy{GOQwKxjLrNJ
zoa1cSM#!FEZ>d7tBs+Nxei3_)p036^a?a3s<{)P+xeO0+{-n*;VU9Qbu1=htv;{iC
zIo1Q*QI74z$6!6qIZn~=6CCXVs5r?vwjDgDI3eEPIn5cO<Mvt3Il8&#!Z}Joz;m2k
zKLT)`W0?+nT{-PDV6PizloAOqa8mEULJ!X5Rg^qARWbm)IIC`<+uod+FQL+hvyBCu
zFXt5-efi6eQ*#3f12|<A6c6MK?L{ewQ%GLeiyXrbup*e#)`7|pj?M+03FYWFpe>B!
z8x9iAiKJQU66b?$fJboZDRKWY$NoJGP!xyJ3|utlH@Y<u!|9~6dn_k-C)(mTzuqCo
zc0A`o8dM~5BJx0zI89eza5CrpVo1Bfsn`g+Q#i-Q!Fi3tpbYx!oQC~Sn8sP;0l*E8
zE0J{0>Ma<A430lpn90dGh{`NZLlxlJobG>7%Has(q5c*}bP>XGIZL<GSFZ9nHxEN$
zKIiABU@hb%(5hC%ai)yeVrW9Cgi|Vp>{3qiv#7ky8Q+D<GER&ZR@~w6-9gGZzmR{s
zf|I-m!tQcz(`B!FoR4TmtKwv=hWctwy9t#wobjI_td_(7p1yKb$9d%#tf}X8eT&9M
zj>#9SO&ks-uQqcY4M9^2XYoSFZskN|fu)`E*QYSFgY%;|Dj#rO$_BiX^KuC|yEu_k
zQR?QrNa=Y!93J__`#8VnqSVi+SP3$~G1fx#LyqH55M~?XeD@~AJmMVJ0zbqVr?BBL
z$A^}jC!F>9koJ`0SAcGhaJC0x^hP;lC-IApaXjcw&^X6PE{_RLqXL|hoNYAR_FN}=
zEFHK80dNPo5uGR<;)*8#ILr;8Af6L9f)>mpHm=uE2tCT3av40wxLw}@ae~{t9y}+x
zEkTfWiu)&R#7=Yj^FYpUm;C@17j9N4O6R!J^(dX^<_w^tu3QH?ZMbo{8_<^v+`5<1
z7k6${7c_Zt-+TjxdU2)gz<G0<D68IwYuiS%wJ$gB4t^3pZsRaY{@k%MKm>9h{sKf0
zch(3H7r7sicRrYVoSZr#-1+YUAIc5C3Qb|$muN2@&VA_)0GGJlp5Tn&ZkdI)NN&Me
z^d*WLn*cyGcM;vciQ#V1fisrtWqSiWaokqQl8@)kqlEYbuH8S7mc)I5B7Vu-_C}B^
zT-jD2Qn*rQa9-uIxWHZKO368r#{D`MEH}6VbJ5>)ZUQ;YGPuzc{?6ns`W`ZGa)(x-
zOIh6hB3O~l{VNQWx47CDX#LCOrpjSr9#?-3cIR`qt^rR0x0nUlMO@Ab0E@XF8qik4
zy-Ud~x4He3U@7CSS7R*haEIwQSI%8^1Ey7Qe_sc3m-|X5L|1Z+bfT`}s*izGb3<+e
zSHpcmS4C^Nfwgr0tK&922BMz(EKO7m+-o?NO>5$Am<HL++;~SQY~lLG0@2F7O77-1
z?skfl-{(fW4+|e~cT~XoPVRG3kS^}#df>XbcJG0+hx-Y=IKA9X3po3@|Mo&yKld^D
z-Uhf18)^SJ$ekg8v`5?=+MW$@PmwR{F;_;>xnZvU2E;t&<~~Jfg!>-le~faAx=}gK
zjiTEG6I=~Fh?CsrEoignt)cHIIPi3rAjOea+k?_UUK<504)aQ~!Rf?1NgmcCJjM$E
z*pBjErEHR8JhxkrcAU5TBnIIGZ%H}qKE-QMfb}%*^H8*%;q9W;-<elOC+o93#q(%$
z;ibF|F|IsU8%l1x(_f;a7kG1jLCKxBnf8btJYOaNp1kpBl)QM3<fQQCjitaC9~;l^
zOQ`qbxg7)X=Pg<YX#u=S3wQ!~-_yJt#B<NW;0N>WlG`|hcVauN2<5#=QPXhV`8nv}
zCEj&P)sNt{oPybrye!(JUFNy224@uSJr>~6JVzm9#`6CC15)C6Tj>3X=h@O|+mOKf
zfnL=_-keupViND89jHv^*~R0zNa6X+0RAfP?L^>HdDrO<@HL(jE&JDbGbw2(jdzK{
zfEm2!1(1@-6Ws><CT{~1r7T|00l>3)?_LMV;gwE>y|;LS6bH}cEwY7zCy&=nk9<Ba
z?|YB}URoC#3whJ%-<=ilswkhLnD;haPbuMD@j$7R_dbOaZu7SNccY3YqZ=r9c$FIf
zDCf<gfAUem%fAUJ_jsStxv`4(P72gl^J;zsXAMtC$+opTWf0x+s^huQX{Da``4p5I
zcsFRRYUF)HUb7~iKe@Y_dAnZ%zJ<4m2feMlJI;{Z#ydsM-1|HiN)>MBy}2HmI(QYk
zF(eOoU!(!o$@9GcW4d^MngH+S1=H)$$Gb>rwf#JfAFY1_JjodF4|#_vVQi4Mja>eZ
zcwz5B#SpJ(4TL`Cwf+vF!@NG)aX#U7QXu*%Z<KPoMtGs=uws;#KZeRNUO*Crjq^?!
zz&XK-_yeU$-qD{R#h$-zC1g7ArT2kz<Zm6MuM8aI|G6EFPW&p`?Hu86S^|TQ^1~?K
z<rqKzBxE1w?-GNY;0Mn{FHZ8sr0^6!t_0*X|K1X)IK%Iwr_-6w8bzfGUrENC<0q0w
z`8?k?0Gum7_Dd*o<4@3Pc7Z>YGT?3Q{B7iG^x!|D-Hs=JrX#HI;@@>gqc^{tJT|`k
zaCZ!wAO8|%&-nA*X$Kd;=O+Uf$lpzgE<yZ7#i+c<pY0F5!TeiWz!}0nOR=X={^=UD
zh4DY$26BnN?sHfX!MCUVRHTjXPy*X7^M5cxQxyN;RFG(Xcs#6#;a{R(EtdcNar7{b
zKm9%`<M}Tx1U`Z9LXTH6UqqYBEBsd|;Ge=@vjfIl<u7@PZm05NDS_k~AK@^(D*S8T
z!I(7uckh7Q;Cqp;FP(2YPYX!~pECj0oBW@DgWXyD#cEV$^IxaPT@HWuDRlG}e`-4r
zx%__@g5>eJzoMi0eD3=I6!2d?521zpAEVG##DCif@DhIK5UeldXa0c7+x$iIVN)5u
zp#Zo${LOsmE9Z~ceuat({zx1UclnMK{jB8YRzv7LK4%+vs`&5wfTf0CNFVI1<##uO
zvyPumPhdU&>ui)7_{9f68u{4_;F|b<>cH8|FW3#eEqwVPDqH#Pv_!V?H<N3&gMT6m
zU3$O|okCf*o&3h9AYJ^u6nO9EN0Wc9hi~bH!M*$+_W;<(zfDo2e!h7beuDx24-`On
z$ZsnH=Oe!UZLkdSgG*rVWB$h?s2Juu#X{y2{;rcS<|)5k0W!j0aTJD*@(bod*ckuY
zXv%*X=g%Vt^#s3T8;HH2{d3565FGv%td4^IMG$&WP)nIphXkw1XLwk!&>O@_AS;EY
zBZ9?e0XQnyN#k@((DxB!9~XEhfaRp%6Pk%n2|Tl5%xOVU3M$VC&R+t+Sy1y8?LW^7
zI_XV!5hPOF|C}K0zk`L~D=84J0uDvT+yv4OAjU(Gcn&2`!LAq4UoXK*1=M>BPEh>7
zM^H=g2VcR4*)ZErpgj(Nzu>h<XbKSgNb^mgpq7E*3KG0E49;MInGQ*|5W(h8z#1y}
zz5u{5f#M6O2p5D>;Np^CBRS6^1S|VtOr#)d42a8u*;_%P1V6t4T(n^Aaj?V+3d&H5
z6U>?dP4R+KTHF!@e|eykD9EHdk|Y8D7Fd!6e$$}-ir|J2y-u+SD#9WAsvvk1cv1!Z
zbQrxZSfv3zO`y39O*aJb6rxWToS@BchM@KzkW4|#XZS^K3RIO)ktGnE0m&A0`~+N%
zz>g+_TY{@}1vy`^g?8Tsg8NMX6bk0kxxPs7_5-jK3vAi6NR<dm=we5yz>_=>w*{<l
zh$$0fQo{2c!6w=SlnZ|91?OGCyOh~hDPY>6?Vf-U4cS$KrMtmWEl@RrrABbr3#3-C
zz=9F26PW1`TQ7Kzgf$30`~dxI6wFKnOS9ldTODYNAoL!rX%&pqUBouQfy)5i7u=?8
zL%U#JA1XTpP9D(oKoCs-#-vlQ^)7H-0_Q1U=@y(l0G3`s(i*Vz37S5Jrhb9>0y;4u
z_@W4=JrvAy1Q`_ku@!(vg1srQX-KfTh2Fo%g5EEH9~Qjn1jG|TjUCjF3Z~Q9WlZn`
zIf2Io!K=VBA^41ZZ<B%;`rd@SF!XCEbP#SJ3mt{O(PwuL3cLRS{E)ExJm80gnolvJ
zM}+bLkfXw!B;bw-7tuNQxG>*=vfNJyKUx86P6`7l+Ivda@jnPXE&Ps&j-C;Q2cXSa
zm{SDVXN6hhhB+tPLD#I#3-uPLa23u>0M1SLAP<!ngs${Y5!{7eJcp8p@FXep6uuV;
zoR{!)D`a{LfBy<HeS|lBY5(abbPj~U{=!A%=L!&x3Q-CaejkfckkGyYDlQ7=Q6hY>
za0BJ|hX_}+fF)Gue;s`a6aGs6_;BHOv|>dHnaiN}vQSLN{3u}pMFpaT{dDGu5&lFw
z%~;_sI<&_Lzo`Pw7B5th4=q7>DICQ_p|}jCB;m`nwq6lRz5zZ(XiqusSA{h+C!`9O
zQ}XFG;or2HUKcv$LvNb!s1R*8gsJ3YOc$0ffN2@RKgl1MDXbg;OP0`$A_m#Q54~Vv
zj_}prKyKND_bIlRD~zONKTpWJ0ersjS9jnGgoE2b3Wcg~!CEA&cnf_h7Jiij^`*kk
zX29Ot!Zyl2C=>cnY~qfPg^N4W%7y#mAhSaFj1=UqP@;vDN}=x|h`uL`^FpagSWydO
zs)e=#3Lxr)6OUnHy>OUzqYc9KlvCF%9N3Gt7Gcyf^uATNiN>;9s5%RUJ;METy6P1w
zuRw2~@N6SUzwj*+$be8w`=W=!S0kWeP#8^_d5?s@snEe8VGtz&Jr@4FAEja8>;HY_
z_=)fUb?vFJiVpT8!nu2Z9~Dlgb$3j7ou;&L;guCYOb9p9c70M9Na107(GaCsIEWnf
zfYVWQgT8ZkP_+D4R2~w!(I=u0i_TG0&PmiPKwplC*8d8dj*1*9(e#)ofJyPc<Dx$q
z0G<$e(`QakiZ)V0`zg@?b@a4IM3KfbqIYS6a~Aph1;AO6M=&Z~L^4WmJSV#IDca79
z#%a`CMeE)~o15s1PcZlwMClQb;x5`x(OwVHF<PNLMcHW}UZSe0lz-+e`Xd%%d_-Gm
z67v-;rMyNz(JETn{Y6XYU>_hFAty(m=$%Rk4H6Ynoadq_kZuYEi#R@jhlor&z!@s~
z;4xUjM4t08B;g|FYLH8!V<vPdLi7&#`XWW!UC`ajqSZCD|BMnnpiOwR=<{`8jS;O|
zi1CUQ4N;~}oah_}tns4NH0vdZ#=KxtqNtey4@siA<gQ8<ZH!0d6;V8;9i)i9r+xla
z(F}?trHaOOqcTm@PI<vML=PQ+OBa=n!<Y=wXOzQW%M_iA0nbfQ9Hl^IiTL5bXN%l#
zpfN|Z=R??ZOLVdgrCd=yIXCk}GimP47kxk}2?e4^de{m@YVx2LiPGwzw^$Ur8-Nm#
zf;O|IqAPS#ye%4{_peN}j8ehxh)RPYy4)t(ND-O}(cUj%#a+=?Q-H4&g?FIxo@jL>
zDyu{bWI$Alj@3g<jpz>wHrI-_4?%C8sPhvDtrtzX0ziZ40TWg<icHmz(j<Dh87i7Z
zalfF{A{r%!T&rkF0sw8IL-csu7ug2s)ZQ*i4MMR)<n%4XJP_@A8<m}+eL3i8mq^?O
zh20`IN_^=NO;bQjuV^m4jeQ~|g{S&Ovr@q_Aj+))?xE-z+IS9%E^Pwfktie!EJLEg
zd(it>G;JR&92U*40Lv2*%SO(Mry>#ca746}_SB=I_G#$$nCM{)c*aFjXkwfYz55|7
zoD^le4x#qqPJaL##5<kA;wbi|aOpwu1YN^9BwkM6n>Z}~n_LG@;=WyAIU@eZ0j3=l
zn_ffdn0P}NO2@@>%;bMLA#T!uoD>gH^290e@F`g8EM8Chg|p&kCQ#`j{wM<dJtuad
zT$A(Szh4EwRr~?@ZQR5QPJ`uwxS2jS=PsW8Uy_OVD1E!lQ(QxPOD}N_?eV<DK5Urg
zBfd*(o3D6N3cY`R;#a(2x4$@&_HzN^BMZ^{K=JivC=3$Mrj+N4;=X9G1dIP(1(p!;
zy)QvR#s5ynBM>IGyaYqT#pQ5kPP-&7C9hY6c$Wrkkz&~k7=+8>^kZO&5{F(xDO%iW
z20TXWJWOBth!wAV5whdN4v$eAFD}@NQiAvn`3DlkDRlHn68}KCu*u@PWYZP#x8%i5
z5zqDp%T;mX478<+A5#+0H8GET_1DG2|83yJZ}p;dL;N|-dYR&X=qAWban1n7B1?Q$
zjghfsi?30}XpT7Id&s^eK6DAJx#Djqb0tsw8ZEK;;?83L7KnW*`KVCbMsAoQ@yqeR
z6^n1&!;qGU^(Iu7ipMCfd|TWw2k>%nEG<A4V(sgYa#w8Tz|cyukP?LMiJelxS!EMD
ze*oFl;#fMg)QE3Wj%TgdEJtIV_>VUryIy>b_J|GQDfpY#D7I_@OOyCd`kYC#xNtg1
zi#UEggtm$glM|{<T=^SV?u+9eg0zcEwt#eqLn!(7fjEWIDLcjcDg56hw*6HF+ASV4
z0^cKkdnzpL70=uVy?x?mDfZMaev=R2fY?43Z4bqZ=r<S?8)85niEBeqIV4^{`|ZbK
z56Wg47C&IXrYGXB_$WOUFXuzbi1>$g{Jf*$?Jt0giBF$|%yDtCEgc=55Kr9*o=Nc{
zXV_*h(d>t82g&C9V0D!2U4UUbC>d!7;*jJKt%ips`{*fglK8%cwj+|;Bd9zo`S2Sk
zJSO?(UG(?3WcnYl;)Dbr+{L>kS#=BWQ<6>>^z5|c4sDOlNLHl(7k`(`rhMkJlF{pE
zbdeY+WOq*TnG({@OWvmtu&d<Z`)G5Myh8qn3z8GG;<-zHCovw9la<iqDdFq^r<bIh
z;%MFy_nol9M{=zXEWVQ5YRL4Hlq`fIf62x?kO0Z{v-Fj#KuHQE+674pz6L%-@;u#E
z4wZ~kz$8r4OD{mUBsvg6FG<=MsEm*lkHVNp$%c5SxGedOvVEf@^Xbx6wB+e^RK`eN
zBVSakB<LN;jFSW#AthdNoDL)j65rF1k|_BdzF^z5B#DLQ-egH5o#U=Z#B|<Gk$f@@
zh^vy1w?Is)q=!O%*CfT1-hW;43Y{O*B;URY&KnYM0ZQqTFUYHzA$jf)I+`g7aRs?4
zd9n|pvm{lX5SA@r(~FZMvHu%Ga!ayfGumvql0fn)<w^WMhl+ej{+p0iAW5%4sZjE7
z3Q9$i`TdYxEXkvBE|GMkKw7E9k@m#5C7$G6ER#H;$>5Hpoc^^~xukb7G*w8Ji@<qL
z(v<^vmE`v@kZQ@=qrlZjHhhP+TASp*|MOBOnV>nPUNW8zo(4%gEx3)6>mPu%N%F~c
zSkWxm=m!-o665Cpwn|RW65A$`2g9cOlG`7kvR&dT0O^qQkwfi)<V_1?c1nyBD0N9f
zQX#Bc(i02~J(4ecVRo;?_E#A2eUgiGL!@6a?+26yBsb^5{D+b;+Di;dmeJ1Qkz_f!
zOok-8D2Dr3Qal6dhb3nzP3ehbcMZnysif`#03(u|rDz+KET#Ctm?Vh8MB|cQ3W1xD
zZ21ntCMCI3A<SO7%Em{dgLEndogAf`=?HRADsMsKA!+$$NINWjXF3p0(v1|TJR<%1
zT>y?sv+bbwm~`jgU^y<$eij3CLb{h0nUm6_l@NAHYNa&J)6y^0z@3rSQP9a*`ZCQv
zXQcsbaJooeyGnUV=cIA;M4XpCp^SW2X(V}{+@$k=f~E`7dz8WDE_L}HVmzc{w3YFc
z-lpl!OR9JVrg=-By#pye(jO=n&sVyV^1%G06|V#5FO3a@g#pqX4^Rq}S||b?BwgZ)
z(naa2zv(MG!P44oP#+?VqUb=Vbmlp9=8|+bxzZw}&g6}Wl%8sY`In`#QdCAsYbXsS
zTB=(G5+nU%286~+-=WY|ob;doBwkuXA4p4(zPu9Slqijv3X&v!Y7f(rrEKywT#+*W
zN9$jTwEa8CzAD}H7sRAW_4Ei_la|rW{JM1A4X8+yruu>0kiPZ-NV;@u15{*4)fpg}
z(hIbAxhZA61r=G+zv*im+0xx*Xv>k_z6njYq`owH<x2l$gC$S;0-faZrAv)4##SJe
zz5|7Y(i9#Bp-B32DO40oy&r+6MEc}7Y$}ybSq^EprM+~qzf9Ui@BJO=)DUPYmv(a@
zv_ksAH(<Fd9i_#%QmUh;<epUX0Gw4)SK0*BN`qCXtdn|EK1jVZjq+X^Y|<Y?U|XYf
z4uvtAq;rSRnPzFgV;IvS{igsXwn{(y3u4-&WptXnFWpO<t#)bX7tqupefA^_eIQ*y
zw;?*EH|c!PC9SOk>6ZFaZcC5!L=%MdN)<8C&?nWe2cTd2@FUneAhjiqL&ZaB9~;sJ
zrRyn9`$+l{CH4+U*DOKXV`&h%W{0I^<T808O{qrdskH1Y+D4?Mzo2qdx~m(NW72IS
zfR9TfDamp|`sOh7PD<Z62Zi>sSGzzQWa+dWbd*)o_Vu95U|RvZ56Ol$!?we+%j9f#
zlHJXPm?N?|pTUZwvi7@>c1(8ibs&z*5`Kfw6SAZ9!<?2iP`vYuZ0$Z+;VfGo1Nd3l
z720;Y$ljQN;W{Uqbs3fCWnJ_&23OhQSAlbr&7x%R3$pyb>HTw;9igYxL$<mCDm-Ng
z)KM>4<sT?{%OdG4?ISDSiT?V_CITQdK-NuXr9j!+9B>B7ewu|oU6hH)R}n1x#~(67
zWV}OA5h_bR4H72Xa}mPAWk;rfT#_B8TL}@e&wilzU!?36is)XJ^|_%jN;dZe^gdd)
z?thRLBa;gtJ60CB4lHr9dz9A^FFQO2n-XMc6p2cd{r9h0lVst+=vuO@>KRmCk*&{$
zuoPJx<-%T-J=Y9es_d_qA?%v$E85Xtm-(}4{Y#TIl!NDntb+0e(q*dM;K`76odC&{
z83O^lDceBvO_nT|X7X%V*eEQ_kp+`y>Xz(V`rufuEPE0pPd4RGn4K>>EdZcE=0wM-
zLRmTsrWMJy-9cNiY|k4Qyb>8_0vc?$W#7|(ttgZ6o&&if`&xm<a@i)zZ>o^3dlNi&
zWd=R^TPX{s$jm+2d(_b?*)sCfRLeHd0N2PG>HVvfeQ*_=b+S2xtC!804l5dDRrDk@
z%3h|JbBnBm0=lg-)n#zD*<^9^QF~ujav1n_*)tvx+9BIPlkNi<k7kih*&cc<yJSyX
zVOqEB0{y#~9$Ef!u=L87h*0X2ZKXTJ{j!9`5H=wDz6nwu%2X`?49b3+0V$7U+qkG4
zlI>p!++*3YZ~%s7Hdk_aJduTtfjpI2-b3Sv?3Kl^dsKFE1Eh_~)F(j3Wm}7&X+n1B
z0?eP3RUd*-dwDA*0XfJYP%Ot$UPv30gL3}~01nCBX?t{7zIq;HI?0zOq3wvAwH%_4
z%AH!ka!hWvQP}jjynYc_Psk5!go=~$OO(udN`9aaJg4RF(KV(s@^!Ufah5;(HUMYk
z%!O!kk!vH-!*g=|MUeCINxA{;D)*xkft&owHT3s_yf+j*bC<vPJJfr~4^2Xtr~D$F
zZoK4~tI7ZAE&m||jXv^)A40vae3G)e{N(Gi0Q8p&$afwfH<Mp4P~LSHoI!Fg3Tj-G
z$M-^Euso1%?u5t{bmj?_4|qUIm^^t40O9hvbm+e%pTmds5%LH+v`5PAydd+kJb#G3
zG7u$CPDC+U{zec;j65d}vSa1nT!W@K`EGJz#mgHhGMXU2MZw5K`P!){CCS^!mz*sB
zBOT<5e9Z&2rO5YF(&1J4)_Q14l|MtlkZbZ3N^ZU`=WhmQn*6~9z;DP?kaA_4mM-se
z1Z#%;#Xn(wraYM*)@=DIXBd+s_g10umV6UAZgS-dj8Ks$pY4ved^!6L+6v@h2hmn2
zzf^;^B6)@{+KT0KZ$VRueA5B^Or`R{YaqAf=bfOaOunWR<c{3m5uCPixoa)(6>@GS
z5O?LnkD$I%{x01Px+l-=huu~3_6->4YI*bs+G^yX9|2!0zelI_I{9Ksj;@#Aq}_9a
zd}}6fjq<mYFs4afFdH(P<vZv&)gu4M4xFv>y93bMCcheh@x5=8iz&OZUEcK`tmu%x
zI|-f#^5OH~>6HIXUWzVxF!|8B<x&5=c=CdyVCj`BDXXPVUP+Fze)&6;-#Z|$q6g`r
z+(?VepgfRr9v{g!JO^Pz^89a5dMtl)GxQD1`zhi23BK}8SIM5rYw5z%i2S7iNE?+`
zd<xbv`6s7g)41H3W`PO$oAV%aQhr1TpuM7O2822&66h4_sCdu=n+_^|jz{Go#dQai
z4l9y30_UVyJOia83eKMxgrf>0E&In5I{E<DafOqu6tyQ5f6@l!q~gFF;7=*${SWF-
zD+1`w&Kbpw&rs>C==~OY&nl)+K-op{5*?(@DJsXnd0vt8Hrm`2&sL)M7ZktEg4ynh
zw<t8}p_t2rXir7YH4ra_`$|-LD}pFx%SU0cC;yAD!j%?!KZRQ(H2Eu@grO9m_;wLU
zpkk7IjX{c=l-+ev5&kh$1S=eA_Z^}r`U`qP745Wr4O8SQFnHmL!*X={l49Lrv_&Y+
z(YYj2F((r&mlglypcJJLJ_1X$V*Cwy|6&xIykT3cVh7DWaf*%2XpC2!;y`bL;vhL(
z6BTYdQA$$8)8Q^zkwnMsD~gOgXiHHj7Xf!wVYe4jQWbwVg7cbUBdNHqI7#QQG(|Ug
zc5f(Nro5(f#R2MPh9UrIRroL8itcl$y{Xvx0;FXrd|rTw*@^;k_~a;x$UA>a@heTp
zxr*oh0ZYE(?S7~zP~4yws8F$m0@+21yA=QwD{{;LlqmRDp|Di3q!mBYZAIL5l*$y*
zi&46x_>F#;a>chRF^0AZ#j;3PdRMWM9=%G%0S+4PDZZJ6m?}jQ-B_wti0CR<jUwd_
zAZir{y`ZU1aY_$dy(01*bh|-ukvwXRif3uoYf{X54#Juh?p46GC?3#RwpCF=vEMeu
z$8=`7uh>j6x^|mlFWu1UPz2nAv<Hg6D50uT(M^uEE`=A}f9O{HQ3}$dSVo@kUd8=I
zFs)CqYduu-E0lD9eL%6`BaFpEMIb%vgNi1aeI6<P-VDHy;%FKGj}=FQp?6p@I0?=t
ziq-VKKULTwDEvR7_>y+-qY4x49>x@-U&D%V#bVllO(+^Nz%r>ABIl;Payu<m4$7D4
zF32IJ|9`30%6B}W&`GJ^4RS=ei=tFVl`$(pjwv(g6nR{^FdFurP$tnWjFZZ_v`Cy%
zK5vtvcv?B1yk=*VLw!)_tTfOW;H=Vi0X#0sttU}Br%a`7-FfBVnK0B<DW&DiO}Wwy
zEEkkJV$kNUOr?{PhjP3WES}1lv{&;|stZ88mH*N%*he{SJKB7eTG|5nDen!~(CDw6
zUknnUe4n<efy%A>AuUL$UWKu^sI)x~60F=u?w=5)9Zh$kO7{D}hbe1!;)e}a&X<B*
zQo1eyiBQJS_0lNi)TNLTt<*0EAV#@=2`XciuanF;rHKv(@yfp^X#bg@yrhBMiOO1<
zT9T9j(ICmnBznrODE}7(n^KhNH2GasI{ge_s?weTa!qNVk-e_m_B#M+%9kflc|+N8
z1U*bw{`of4XDDaTYnZ7V{uC@Xm4Ya+WGP4EFlyOK11>z^zYHtW7C^-<WjkeJ<SN%Y
zqLiof+6rL4a@JiS3Y4?x6)#jOOkgQePNj#XSUH0Z(IrZI2mE%WO5c5GyRF<#xBAMI
zmLOPvN0}Ce%5vqmGzV5F|DoHOca<M}fVN8I-2;Hz?kUx@I#ns_b1^j4%HJtUR-?>l
zg5Fx?$wu(hDYL_&qF(vwSx9S84jloYQK?xE&L-vdRIoHFldY(1QM%IkuT|+viGgj(
zkKNJMp<GM}y$_TQRt#6Ca$yXlbSd4)*Vk=RKD!6BN0~=oH0@PRo`#8i$`^No^edCJ
zAOp(3DEr`{@_(feI;iwq0n;8ScclV1q<pm-rae~fAxH19QchFZ6J^d{Q2117eHAPt
z%KHN#qe>NB4IWc^Iz!61^3XV>Oek#wt}tp+DQ5$3ud1ZjlY{ESix^->RVn=j2UVZX
zg8D-$BLz$jtCHxD<fNLQ?AIeITLokvRoV6fa7>l?JmAMwos`shLZzjon3JkOK8EC!
z>PR_Cr&X!6i9VxJ(YDH6)nIdjUJq3xeH74Bb>v5|dZ|3<H0iDS=R26@qjD#ghp$RQ
z?pr@qI?a0is_WmP6rd7NL^n|NiVM^SsXn0)<3$y#6@Xw>Cmp3jRG;reTc~PL3_1~}
zdf_SB!c~=&C3Q*lYo!g=M5rFygG8#Ndw{sCn$84kluGd$OpI0~d<GJudVW6?#;VTk
zLMcx54CQ0Rs|2*ONKl=mtcOI^qEDbcNwtd(2Fa>T|AJgmO~imDMb-5o`f^qE=TT@#
zRr%8q@0zM~CFQ?dS2=wJ^=Ybi-a*%Hs7g=a$4gi3qA5H><wqN_EL9y7(y~<!9;nPw
zmD1MwmdcfG1Lmq$>;XJa^$g`@<g0$tKuUqiyd7<Ys=-fCDpq;Wt@098IJt&ORT*@T
z;I``bJlcPjsWRz;<sH?QC#Wq~{rVK0sZf1GDFSy@I)9K#RWl3f@2RSmfu%~dfsO*z
zsz(ucWNTE>SJ3TR)$6~btwDAEC$u%HHt9f`Rq2_4x2PWMfHAEq*CDX9slK3q{e9K{
zK7qZqc2!|2#B`{>BIor3)m3smbgC{<a!i+M_GOsXt+G-NdsIt(!P2Xmpfs31mADo{
z`&IMIFl|7!h>}7ds>0|29#q-hM(L62q(6iWsg7lXJXV<~r)F3cFa`RasB-Bb^wg%3
zl52NFHUB;kqpG)aAaqQ%m;4~(ssn2vdqTB9h+&&l?I7QsgL*0LDjn750>ODu{e&EW
zPHI^Y+K#C6a?!P;>glx6KBkU*1kU5?8J|Ma3AOt=kkjg>LIBRF-=75*XSFSK2YAk@
z7f>?6dG&Ys;Bi%Nl%eFNK0v?W1@*NGu)3>fzl9<7P%~CSg{Rt)9xpHTEy^eHRwq)Z
zz(-v(6L4R3JbCH-)SXg@_E#6XpcJ6~<~v9UR1XY;Ge|924fsX%eOo(du=;QbdKjW+
z`k^sYolVPkn0lH5(!$kqe?{9R_1_foj!?fyCy_|C|Id(iS$%^tZKBkv;V>;)JxLd>
zV$@&JvmUEnZa`(6+OHoP;?)C`hMk}m(2A9)wsu2wlKRsSI{ziBcNM|XE9!5_wUnZs
zX2J+vRTq<&K2?3L212i?pMMcTZ>SHF=P_L!LA%Nf^|K41K2xpP402Olu@17c)azqW
z%2pq{3Yj_T=0F&FOMQtlrgPQYOt9ps|DY{bzWVw1=>02Dx05HZQ2k{+NRe8~1HM?j
zCk1*-)V}1{E>-_;6^yy9uA|sQnR?cDkbOtJ|2l-0t8dZHzCzs}0Nh=5q#sIE>QG9H
ztX4-ez*3{Gr@c?D+L7{R>eTTx+tsV@U|P3LYfvvMhl)n^!Kq+vQa8{H)v8XN3KQGZ
zN9oq{ef9D)VChq9mqK>G`rfl31L}llq2iJH+FGy-sUOV(%VYH{2HJ+zG1buYM4d-V
z<Wn_wE=ptS1ag3kt9@PtnNYv89yptW#*cmjN6nQtP&}yNkz?+VCWNjr9oD4mgfu6O
z2U+N>`FSbCoYj<5pv6V=#ww^kr)j0zOy@N@H=xN?v!7z!ZkjLMq2hw3;Vt0YHT9G%
z?4kK^COADcr^wgtrC}aK$=jxpyQ9%ZQ%KjHeKlh=mj0Ryde{Oq%k%IX1Zt*Id^bpQ
zigFn)YDU^o3f8Qr`6f)W))lyLjZYfdE@`^{JLYSgJ78#}W-+;xE^FH7KvR^aJr`Yy
z);wPXc#LL45&*Fp+bKElahk6J(HO6BoP$z==C=>Plc;%SA9#{9juGfnvc|C)HeJ!A
zuZP}L&1>{>rD=RBP`aVn^f^en#yka;8Jg+)QOeXD>VV9fn)iOgAY^Iokq;|dlfD)*
zb2M!F!rCnj-!=qGb2Y_hVQHQwm{KY7HRZnpSfH8y2lN(drhg7Zk!A;NHH$TzjUXkO
zgIj<v)ijt<x~&PV0K7~y^+&)fG(HzW>NJ(K`>xllnvUK#Xe=@aYt$_I7d>mzypRTX
zv*vso`9E7V_jjPNP4i0)Snq3m$;5WeO7eAdXuf+N<bh@#-E!;HM0Ek!rFn7$fF8|8
ziV^f`Tu#8=K1~DdUHUbJG?W9HpAw<|p=KGy!3Q;e6hY=A%~^YxHl+FY3`&nR+Bmv@
zJFMBT7en(@6Hag3h-M0{5~G?iT5!iSb18doT;t6_4<|I!{)OyGjpZK@d+koz!8vHl
zGtlO!-D(2-p!UKaz#Y==rJeO*?U$6Y?4;e;1(`>*d-uWmquRIrLfbKIrYC*><+%34
z7lAmf4WYZ&&f4vCap|mf{Y>=GMf)M$(mAJn=O8N2Yvafj?W!%m0Zw-<qXC`q&~Ela
zo2Pb&3)x=Ubt};3t^N8Ma6Vc;F^I2r4LLsjv?EpcvHi8{S3ydkc0KJqY(ZLMFL*9$
zoqZrJSi5oy@FChyRziKKHe(!ihiNUe?GD!#heFIHt!h8SL}-`33qYiH`m+#oSsQ2p
ziPj#Vi6TZjc^aiy?Jt`kB~H8G7-Yt4Gw7_8sP!OsQ<9cd4l9yv+I`m`?TXf#3Z4}0
zu?PUKYX59UDOLL{c>=C$o2G!IX%Ez4*luVOr6{Fqr+*C7GPK(%wI@?Mg?8;XwSP&V
zB3GNS3S*I{ouuoM`Px)^(+jjq$mLO}?Rge$#oBMlA5o&U>6+14s@;DNjd!$(V&KcQ
z-4yYw(7x7<w!7NZKcP>R+WEHttkOOtH)yq1OxKlbw4bsdre53o4%!;DzidEX8nu_6
z0ia2{HXc%%wSyS|v}m8=f7(uK)rS2J&imSHp5ScPK4YT*dWSacE*c+bhsfj7sm-7*
zeV4X24WwIpZ5X}i(F*C(TCaBEPjC)sb@w3jq4r%my$)(W*Fwr8?F*EGF{DjwL)&9*
z6rF&cXa_0u^;G*2Wi*UvpIZ)=QLR9Z$}#QqZ)}h~seL8~toFM0g&+>P#q=pUN8LOL
z%s;4mpC;`?x~r~G@1%SFb+8=Kt?>pqsvGPF=P_MWBgk>x!7y;1($&z&oYpO&`1u)K
zz8n@h>-Jp-%URu=O&~71q6dJV(=k4v{Fn2(TKWji1zp!=)Vk}=k{`uGw}O6qPu<A~
zRC?+1Uqhvj?#Wr;eRZGEw$4viLvGXnT^PBB0(F<}KyQ%F?j#2PqHf`rP#>(@a1T;K
zbZ6g1TbR!99xB6iE1rkGOS*D9djBGHf4G7tQn!V+xR-TXJD@OHH*Xmf#^|n|KxM2h
zhIW;4y5F+V!+72GY?P980~Ewb)`eOj`-;xG0t1|)`<z&=>ate@o~o-Oz1MVi{9xgA
zT?Ykr(sVCTD$xzy@lLea(sd7?!kP@-M)Ff<>OP@e$4%W{$|=v%O-Y2NY~2n9+H!Os
zeF_z~bgCMN$<wW-17p5!C;g%YI{Ak%v{08xXXqlGE(cPIb&)}6E73($jILDYLdjvb
zbtQD2wM;iV3hM9JbW6xZTds@P3859bGuV?)yQ@1$A*@PW+Mg)h({(6eOqH&U&SBNM
znQI`XMz>G|^|d;8${eZFZEpojgU&>5%tqa|EcCufH#`q*%{n6mSXy*Bv^cfumX)LT
zZMr#I&~{&EyG4G5cHJr#@Ey8sPa*q(ZiE(#PTj^&VRx5q34Iu(TPNs3*LrmOic#6C
z`+5#YpU#*33jI3GW=MIcE4&ZfppHR{%p+Zl5pBb|B^0cBqMOJCd8*qP4KkwZp*3by
zx7bGW^O#QgCF~y8@xDXjgl;`$9Zl-WX)>|bpZ*$c4*IR1K)s`WeGmW#^|#52L;A~(
z;5@8%e-V{V`WVWVIHFIEg8HNS#i!7AOyBf1tUs>ze~dvmp*Pd^_oUu;14^g#V`;Sa
zIjtY-fb27R6CItL^;vY%JgYA-K(CAbOWKi~(^t`^^t?Ve9Co|v7d}AAO>evhX&3Yp
zYXNuH&!xbDhd!R-!k+pty2$3GpOz1RxBhoMtnkr)_Y6e)>WlsXi=V!+hxVWT`fHEC
z8l<nFRKSb+SKo*1V7-B^Yli4MzD6ljAH5P{!t{36U}3mE?R}6-`ZU@TN9g})Lg})8
zwiilK`q#)=9<BeA&K2?cXjkY>(BJwVeM!`->Fl1QuX+S4lJ!oj=>EeM{ZEBxOwrfV
zq5rD>6?;fa)fdz4o@@F|^mts?NAMsmO~04EXmCS6N&BL7eU%s5GW4S~wPfnO=*)6c
zpZE(nv-H6qf@JISZlOy#dM^Up($A)KBv)Ti1Pk-@*H3}i^7X5Fz*?Z6K~G?z{$>J%
z7U`ca0isy{ZZu3Q(KoI@TdBU6j(WHCBbYa)mFX9JfzloQ;vonv*RQC6*%kU4+Ns{v
ze{c|_QvbLGrrpz*mP1pO{v#HIRqMZ`52V)U*Z%}utxf-%72U4Wd(-n=uRk>fJPrCp
zcc^I8zr;dYlYTBmKb!R*(M{|YJ(JQ`TlGzJ!>Ua`^gLMZ>pfotu3i7tW>j|QpIkxd
zfqsPxde*6TB!5$v{=`yncI#QR73tAGxqvS9>TPwjO7!U`7eHaZKBf<)0sSDd+NM3!
zx6>YGQ2zxjV2|{!Z7_I9ubKn$SpO*<+=lf%bf_HB&!?oAQGGh?494_@bc`F<`+Gpe
zgub4VX(sjEZ$YNLVciK-Iv7?{?AFoXWSa*Q4;psRf_uo&L-W;PLp@y=b22c#h22LC
z!46<OYG6==@|a<ao{Qs#mE$O#Ff^9~aMCbO2HB?!!}mc>8y3;ScE(WhIar(xvu?w}
zvj!Wv&Rq<fXzD&^2;B>P=MCzM)I(Q;i2|%{h7?*|E*Ql2P~mQHeGYx{F!<6s=4mj_
z2aAt^LD@9^20j;+0fz7wPzp5s5e?ZvhJ7@bTr}*YM5<uJB)M8b4C`p}3pLb}vpvkv
z*a;2ch6NOQzGSfMq5tw0Vc0H%!I6gb^!{Ep3|>ZKlp*nXSQ>3`ISG7>VQwK*#2S{5
zf-}zWEE_EG1|K?2CK#j?0!}pSA}?x^p?M}MlMNf`>Aqt4mxIa_!}J>Hy=vIA4fduQ
zPH+LZW>8d<|MR+GP7qY28P-#D;D+IJ0W3{7Sn0k;hT%<$%4Hh%yFtuN!;)OIWf=|$
z!I^C+FM-e;!~f>P>|2KIl%tYssC^$Sd4{X+0he!B-3==W4B8JdT!n^lC0L3K_bA3)
zZ0JeEFxyHDN-=1u;hF`u-8QuR1>4FDJAMP=j-iT9ljR2g`4CfK=%$zBuAz^%`;~?<
z0dV&WZqK2u%8=s?c(q{}6Nc6pp4*PLM#GUQP}poZNDihJ!yPBIwHp4S*Qm{~GY?Yk
z+YABEKt;RZ4LTEd7+zGOYYz+|qiF0jT$F&d-%u3=gC81RrYC>Ua9{v{M}{7XwGA6W
zjzh&0Lm)YbpBhqVgE3+V`Wos-4RH=&88dv@htjxV*bQwHhJBxbOd85*&bBw&%qrj=
zjQ3S2IvR(_S#i)<PkV_&##dU=r^Cj^L|EZuj4uN@V*KO)gdR06n+AK288vj;IBpcL
zMb}Ok*HR$*q_LV3eNGuqQ;6cUaUZ3@oH3?PhiGS`nuW@<MxS~R7voztdLqslLn&H(
z-ng?AwXVjLpCQK0*iMnC3&z)^z`Gl>*F%MeQP~FKX*^0@^D>rDxX0Vr5($Mq#@Gn}
ze2vmdX!0{U4*=(H{MQPZ0mjzfK?02-yHFWq4FB)UVa(Og86?>F$|VeGi1GPC;6sh8
zpF?Gs@dGhrhZ~dEp`(|KYqx<!7^~;P&`6_Z56ETXyGvk9l(CTB?Py~;6E?*dZ=MG{
z)|k5vm2t+#O2~{i`cke|g7M~Mv?Ut1uR&Xq@!S<!|B{V<0{~tzCYWJGit+txC|xza
zM+;x7v56eLX~t*~$PMGu-_VwBOyfdKhVedSb7vY`oY4E5#<3G%$uc(389Lke_xE7Q
zG1fYw6Ss`cm%x&1eDzIK<{7n5z>;rl*h=ePfl+Bh*9wi^l(b)DEV}{~#m3v@Z7VT8
zSO9#f@kN?LZyW!85emzU1$17$V=SYfQ@PQ$5P%BfFO=(b*LW%oQYwuW%2T*!{Kf!<
zRmS&@p{?4u0;|Nd8si8hsMi`DTEJqfGZuV@#(Lutx=htz^vncLqj8ZIJWa+=tI^hM
zTtJy$Eymf&P}pirqNStV$YjE_4&zsg!1BO2J_~J~Mh$t5yNqdctm!s-Q1r6L7()4S
zy~cAEu=E)VGBFnYMpY3?12&`GZzw)AF8dU$gT{T7IP=K(J7v!f8B58L@!0527jK7+
z)gch`#5j#syr;%1Wax--@pYIzYP4Gm&M{+H6oif&cQnC@3F8bp<xCnav?sPVRZ`ZF
zgXxk#DjiJ~^T2Y@WXtzJ?IF{Fmm%%2sR~ofG$+&ke__QD(;f#@9yPrk2Xf3b<r`=^
zZd!N&fD@(=a^IdbMcPBmDbqUgSe`Z+SE6*r^lc9mI-42}L(^H)^W-IPF~!hP>zt{3
z5TehU><00}xSBTFgaEpkW)6eZ-BjlSyoV`fHF!KtZ^_Z-W#SjZCT~-9GKh~!Mk}<h
z>EkcZ=4VO@1;F3rNfF%u(_e+C3^Z+}16Yvh<IAYLXj+qrp$s;?LIJ4|(}~YOLQS89
zK}wh@TTc7Wa8s}k5Rs<w_0W6S6hWSzC{vv`430KE{~B0gO#8>tr&yEuIt-07jen0)
zyeZNRED5Gr1Wz{2JPX_v)5~5MpcK>DVsKtFy|oCMuA5xaU|O2#%NNmh!?b{&<8;%u
zZz=wsVbakcW||g~Z}z5X=~XmlncSZRFx#}4+!{Hi?UX!m%k=vxbSBr7O7nW2>Ds&C
z%r^~C4n%=zobq1^O$~RUx5)I;hv;arX;vaiC8iDZWw%n(z2|_tZ8}d&Ynkb5IInEe
z?wA6|Z(D9!&<}it=>%Qyx@+o6Mz<?X3JzHBnf!l*v?^1|w<uMcRt15j#<XNLNUiCO
z-7u}r6chzgZ#qJ!lm^pW$_{BXrBjw;lc`<=(rh|)7&2Q-`3#I&tEupN5L=t6We*Vd
zO<!#XzTLEwqL>{fe@eT1VDg}jcA5g0qO!~M<873>P4zoa>M=#pM=5$uPo@CgXWBxW
z(tgurA;^GfKg}=?P0n-yebBUO5jY>2b~<7#hD@hu0eNiVZ2`-$&Gf~W(EG&Hs0Z+=
zsh7NjBc^Oh?i@9JZ$aCbsgoYkag#koAty{`^1@D<l$2&+Z{E`kX$Q@L`M@1A`vij=
zHn)>M!pY3ngY$^_IUY(!%@RrjJ!USWsLgTn)+CJf3A1e_&1@&lm2?T~l$k-X#nWcb
zhbWyf7t$`v*}S_KV$PapP==g~SwZpWbLKoh2t99p^ajMZnmx&l>1JN>1;_=n`c<fK
zH-AM@NDs5!36wm|muV{WGQaT;D!t9vui|YoKWB@97+>=*^m6){H4^ann;%jPHozRe
z4LpJ7b(D1!Wd3#+)L%6JL~m8F`RaWL4Ka_#0v>8Epsh@pS@0BqaP#%Q(H3dmd=`Mq
zX7*PY*eJ6<oPE=x%`efeFvh%N4GfJnPoHB$597?AxS<$teklv31oNx2pfJhY_!laZ
z&B^;<+7)vm1Hcq>8s*7eHOEvz#Wl0j1OV5~rAYv!nf-1;{S9-%CumDICsV9D!+f7M
zm09Mt&0xtkUrd6`9P>507Jkdzc%1G(<eERFw6HvL!#g1PW+(Cj6_}&hFu2g1whdh?
zGRxh7FE&4+q?!`*+cZIynl<zu+&0&ZKt-83wFU4y=7q%ol$)!v0Ix7-z6Z{`=6SEf
zv`X`N5#aaCk(9JsWnO_zmTg+K`PmP^Q)7PD4k~KR-bs*FXSS2W{Ccx~1u7fNzdwP{
zMzd%qOlvYPryP|QGt9+%Wd4XgOxJE+;s@Cs<~J#!>4Ev<48S|hopfyNGAEybly0-(
zQ^0%7`{$$7Yv$JiXX`Vsp8`a`xrRJ)1LiSj*!|G_OD&`gnT<5*J~l5WN8+%VK^u%G
zX7vK#pPEH92qWfw^x@r6Gsl9l7&A|w2i&-M)<?iin7{rRhEAI2Q4q%7vY`RQ(USTS
z^c}RcQc&=a&0;qUp2L<8cLU*MS@9=S9I;&a?+TiQBY~!~mV{ccxLE2bGyR;UG6D+E
zTRN^ny{jecRS0#r9H%g?hb6HMa8FC>UdZ;c{4j_%Z_C#PaQawwkE7&kk;Xu#pG9v$
zrN6~i-G&hguvF1zAkcEL6{R4{a2CW|v|RRq&|u3~9jFYkB+yzBV+o@VZpT_~jbbe0
zEtU1?OoGMfJ5(lGTqqeJ$>RAYG$mX1PXoDP@mvnkDVE3dX_>1QuXc1I)$$y<$*x%@
zY`=l$x@B`FtVy#R<bdafWtg0O>6Tw9RV~AEo?Nq;ma_k%8I}k-bYxjxqyuBN<qz75
z<XC?C2~uuZUZDG7xt3X^H_tMY!Y28aZw>=qVDSt@TcM@;ALuQz1iuE+#g+%3QkH*-
zCG{z4OD$_D!gAa4_AIC<v%E~c?>iQMnsm!88?w<>VPP$WX?HDK$(TyZ%2&~L&*Dml
zohpmn1WMHw`+jiNSc>V?TyIIG&0T|~?=~tMEswT=rOC3-9mCaZnR0@@KiFbf{t8TN
zwFIZ2w$0*o0OsGfeD*gg+bw|(7?}=BT{hYtSk_Y1sMGQV2c*lgzYUe$mUEPV*<(4b
zfWlsje<&38S$-LUrhZF2MK%X4tKUFBA6mj+$J04z@w7+fBa3S_-G3Oe91Q{Ru|-Q~
z;bF_Uy=Z)5`D_uacxu`65)dPn4aMm1sO5P&LyTE&J3;-prE3b>CM*m(LQGm>48Yl2
zwJTt+gEj9sN{-gP-@$UwdV@kxhpbH${y1z6p*$2PYq1y>+KyO9D1vs}YF~_AoUkrw
zf)yvN7d{8@lvNY};A!h2n)=UJm;C}3XX`RQC_HO@a|wux^%Xk5owNRLD*)%M@2^3n
zt93W!y}4Nv_n~JOtf~>Txmyz{&B4R^+$ZRZr&X1NN-vvLxCqqS`YHYPKGvTofyLKa
zz8tK6)(Q#(`dc0Ui(p$H?uQkD)`Lr7Z;<sS<!@iK3OfJ@wi+tYrx5Fh^c|H@>%c|~
zcbN5g+Wv-H4dfxZWPRovutZpk$h{V6_1F$8E?aF4G>1l6cg};Q(N?zr$d0i-dlTwo
ztxw6>5NF*%2}beOo3uelur5smNwl6Kk64oRCz_y=t@-aj_7&^vO{h$<&RK}kRV$+h
z@KkG9HcHp5hiS`p-8xQvNweOe3)wfUH8#r3O}DPu0BbU=#S|>dw0=yVN4aSYqU~>%
zbuF!p+13kmrz*!9vJvE#^^aH4r(EkZ<PpoWw)=rI-@1wZSx<pAhOYD%T9;o(&x)*z
zXfIuAbtF&R9cwq8SIe!d$dz1SJ)ooa@2)k50fm*;HGvR%&wA)F6joUWzJZu(>%4Z9
zYOIpoP*H1L^C1-0Sq0q~#Cof~7c33d-Yn>Cw2IrIsmc23-;mO5?K=w27VCEMo3>ho
z<RxgcF4+oU_pR|Xu<h2*=F|6=I;`5Cp#FhXuoZ|->tqN>mv#0eSi7zL^xqMBtf~-*
z>9x8f!-_s@vJDFRt*%UH8nC`T3oH+<$LS`^pw*71okv!;GQfwd#+xWTw(bi+Y1rCW
z2hmTgLzMmV)cWdMbp9LpKS$Rcmu2<EGd0bIX_}Rpm0Foif2HL}%}ldl`tH5=e$mRx
zUPNRGD0_o4L=aFBkd1;02q;5D5m2V03`G=C#_xOj>wNCL=X}q(_j%qs&N=saxBW8;
zw5Qv|h2R<4_ScJ0F}iI9`IN@CMO=l%__keiLUm>gP?pth#?#vvJr~9X@^9~DtR}yy
z8>8q=5O>D=bUV(2ajhC{o{aP4YxH6mSD?~|(MY>OUq&Q(9``er_M*+<&uE^B!3bbn
zp)1XSjEj5>X%OS~5ugP#?mR(T2xHC(w1qP^()Krk!5Bv=lCc2O$K)tRJh@Y%8H1Za
zVi?n21NK42OLV?C#PFouWGusv=JPnltt9}9XS_|0gapRb&%kon!SGrMo<zp?r%^n@
zXkY>+iLw3%uqHEPo6zl}jHFtCrZB#mi{7U)BDx`;#;Bs-*fGYT5?~)^blpJd1S4t|
zz|t8jcY>T`+)RdC24gjSTr88Zem<UZ7DGjk@D$??t)kfsM=*J)au~%7@Z>V?)7CAI
zv4))H`HT-~zh1z&ats|UWNe;+$|6Q{2Lw(tE_8#OVVn&CDQ47v2U5c5od>;V85K06
zon!b0qVhcBcsWcfWvIGQS;mN%hn|%){-ovP0wd6|9<+in=RX$!V-~rVsu<3c(R7jV
z^bp!EF<i*?SIvlT1*u^?qM&arV^KWX>KMCCP;r@|x&*m;hBgabyTZtcL}dfRts5*?
z8Os{bc8w80KIBHmR(b=kGd5Mjm?p;fHu`NhGhU}{=uHNbve{Z0&pith+ZcuPIkR>~
zJ~^g47&qx~*U6Y&3;8a_3sW!_w-^k16t@{pgx$^HT>{D-M#Dd-yvyjI4NVW@k2e9<
z%Xr2Nus+77c!2dYwB+8t$2c{UzW;Kcv3Db^8DKc&fjnURPFXyIj8^&t*F(l`x;p-d
zA)t`m5TlD$rN@jTv<V+(1o?tIVSG%E&!-GlALK?D(M{kSWgMb+b&Rpm6K&&+iDQs+
zX0}X*O}m--Q(><Qb7AIx-#=q2Qec}a)1T(Ry-dMv=yhXOaDnE|EW80U59Xgop~;ik
z|2{yynEU86F#DLR$T#E7Tt-eaALiOGp~;sS7z-8qnO)C<<p6U>4fOgkf5De#Ci^p=
zeFKUDn9q~vB9IwQ9x+D{bLCUi1~co=fHj2qUJV8@l$j-kF=5OecNi1Se4A#72<B3{
z%@oNzNQ-I|leqw;Xy&R8lwz0{zJW0ZnVV0c@(?pO4q&m&P2oU^V;-ew;9=%da&9Ct
zFVRW<2(yXK07o6nm+6<D!dysU;#B4WngfqBXHG!r1oKKP>`rICM4sW3%w{@iW-#BN
zDJ_$^^a9M!W+wMwWOA72wxX2F)V&CWdCW6akjrPjPvM#ZW;$&E3z>T<{#V4bdjR@0
z^8=b*&oCVy{s6m+ne6Xia0&A-O4mKh{4Xu!9CMBeJm;B@o6%OvEGD;a8S{l*U@2!t
z-Ujvs=A#0LS1|eX230b@bi+_qF%=ZkxXA1h!-`AH-1TUyW<Jx8-q$c?<eaQ!-kAa`
z>X@kx9e6G?57QTW>zQ8UQM<yNKrWsJ=Fc{?U1cihHqtd_BBd)eGVOI}yUy$&Lz|dE
zg^+7z{zk#(7G}2z<OXvq-mA$snP11Ft(|%P5UlTDene|yC-eTh!0ci!{0Zb1^YbtV
z%)iY%KMSng%#9q>-eJxqAL(7@$K9~BhdF_!tzPE0t{{EP@u%o^KhuX2bMG<L7hu|b
zW>^sP4lql#(DZ<Lmi)DY%y<faJY;@KZI76dH0cg8m;VmT$IMI-#D|%$2h;xZ3G;&_
zG(Ke>)B<~i88QHvQRa?cfj!3DPRUxkS*A9Cy08)(K=!cSr3^bamS+b#>dum`0;mTo
z>>va@SucM9Y%f+c1@rf@l#ig^n<b`wjSuThO6T%r$zKB5&zd?w@rMJfR9e9NSaoZm
z*Pk`XhQ}Ph8l-y{fvla2pecy8vKI2etSGwE7{dB}2S_N(OjCFmtAGs>&Z_Q$!YI~L
zike2VJiUP#!;;Voagg;jozV`l)@lJA%bM~M`WeS6qSK%wo+aUcCxJDd3ZBEPX$#Q9
zMApU2Fy;trCq1<!mf&MlCbOD9g#1xfbRb9yYZq-pQ(4X*LsJ@S^D%%PW5Iia-w*50
zZ(-pH);Cs+Ogih831~aX($MBTgH_@TmQ2=#B*<ksSW{?DI>icl1fFcx3$dupVSQnQ
zd@gH@-0OKP4+@0kvvMavZvpFJ2v`bP6R*LvBG%XNWK2HIsv>vu8P<R=DvMbsXxb=Y
zJxN9n&$4_5K+duH>EL&sg}inAnpn>kp;X3l*vo-d&brtF><g^0U(i^^dO|McYF29z
zKx<exDG{rdwU~B}b*$-12wrCG-vAZ$tXeB7udoc1BHF;(@j5E6vI1#syvCaKJ=&UB
z&(Id8nWdquqZU>pxd(2rKADTko2)xaN1?uz)k$&IHrCN!z|+q9Spb+0mgi$Um`>JZ
zFJRwh4byVe&3eu=#I}0EtB&LTFtMLC$rJJetY=pO^#QA%J~}kWVy^|-5UV>KFppW?
zFGFycb(y?KBdpj`w2iVN=YWi{a`nL8%}(Y3#f2U10rh*>Y4kB+H})@ecn0q5N4qg3
z9_;76QQF6@qg-}xc9x?JtUheR3s87~Z3_X6AG>@O6#BCRhR_zo7Q6x0V7AMvzz$)*
zNb_qryOOTjMzH_r0a_&cUrJ+(VUOja@*vwxZ_6R}*3ICIXQ$EDI)U9f4(P+|py$zv
zB=+JfFeaIOMM7usqwLKepciTEx5i+_F}6Q_FzPt_e_kk^WV4+hn8Eg;t2>$Oql+Mr
z%?_E0wj8#NzEPOV4xsd%0`|=R4&Ut8D2P+UJ{1jPirFO@D3!45C=cu`TS}X}Quej=
zFs+RJRutXaFK2sD(5sStot$>{>{Wk2@Cy4XIWQa8nRIBm%I<N7;5GIiA*gI(`)`BZ
zX7*p?;A&w{@P@z*_U{xMxygP7(a6cI>{XN~+s1bC18HZMo6zkJcJC>Oce1_yhWajc
zz+Unj-C}1hhkQ4?qymk1*yFUrxXb?QTfp?NKcw$k_Oc`Qq1*lJO*7Dod+cEb^xkL3
zod)&*JN7079<ZG#X>pJp@;2m#*ljY9$LuK&fH};bPABUT_OJ9U$5Hl>82ZN8H)%q4
zICHo)5Zuj4`4C3AaAXuk*~3v$WXP3cp}?UV=Q~<4-8s&*w0m&Q(!E7b&YPJ)^WyY<
z3%Pw9$ulT<bKVVwy*`{x3nA{yc}E3%_j7vuKn`%OegP}|I2*qLi$7;zB@_iXI6v|r
z7|3aV0kuJ#?KfdtFlX9v=ndhpWgwxPQxxzF<BZNmTR7+Cz2J=Eq|-YS%`w(PeGKRM
zaP&8p^Da4D<2c>ZAs5dXS^z^6IVBsQ=?G_b2*i^(VJ3j3a02e5EtTU?e2A{4aRMm)
z`~*j_5q76@d}+sel5;E@B#Sen34*6MpRNZ?HmAA}0(qRbve1^#NjeCD0?xfEu$<<U
zQbyAmj?)$xQ_MN@FM4*4vx6LZ=Q*J?p_g)`mEbJnI90=na?S(C%c#A;S!jSY6`Zql
zfUD$e=!f}L9N%bYy2$BU0+vghrQZRqnlqIRD{48@=@eYYVfw*}%bc%5fmYASn+9@)
zvy}zT2F@)t<gRkYT*2AMsfmUa*EuUFakPo!!-f^joYp7@^tNyoormBJ4vS7_H#rk1
zVA;y?TLWX-I7ug=qMb9T9TFX!AF02coDDu8w>j(Pfpl{|p<79JIB^VgyO(p4Hq3pT
zqqkAn&-vjYD(`U=v=6+`nMEtl0OwW8PkO-dTS)unK~BSCSn-fEZ4+uAah6iT&JbtO
zGLXld`rko@Ilode-4o7s9ZF9*J1Md{!dW#AGRlcR4C}`@?0-SVIol|w$C;ZgLML`}
z-LO@j?80rK32F~_=q0qda+lEIVJ{c?&-nehan&!N(Vd$-9cUih_6qQLa=)iLJ6_y{
zYr(pYo8u1{Z|*cZtnlG3{}!CSTr;g>`?-e?pzQ$n)CHL4#~pha#Gm^%o#O(y`X;ah
za$5=@5X9~K1SFUnkqDF!E|X%5j!<s$D0srSezP$M;oPYy&>O*h=U>1?a<}e)L=@L8
z0wWX6{g6WLG2E%|pz<Jh*?(Uo;U4`F!yU_2ZwF``cPbrb<GF@(loGhvNhlrWh8dwD
zk=sX(rX$=hY1T^OCjE@(n(W|y$%VqB-0gHrCxsh%9kr?4cRxp;(zw0_z&^%ZvIJ<y
zxs|lEpWw1T157&CgI17}+^`8KWpHCXfpUtQMXO6Tcfy|_Ib1Pi>*sPaDg7;vJ47M3
ze6BYcTEK064$y^MN6vI~w21p2{qRn6C!7WA8SXO_l`rP5JO$7a?uJb$o#pPE43=};
zfo#B>=k`*RtCag}Ce)X4d&vz{&fPVRwhLVMw;)%+-A4JcmE8N=z*)uJlMZr`+i?k%
zm$-T%)K+t?4!U(+!xgwdqL%ALkFt*Y_s{6sW$qtz^s47hpsc4W+*iIw?;E&_o}%q4
zH+2ojH7=9JsgaxcKG3dn{m8rD#4X$oP0ifjykOH!?hXrBTDhyf0!thB0-a>qxjB^o
z(!t#xL3!hy+>3dr?czQe2IwvBFgfOKb9K|u*3F%=2dsCvx=2*s<u=pX-NXIPj*j+n
zhv|+(A2)+MRQ=pL6k)l?9ifQfeQtz1I0v|++hFzs?z9k~404-Jp!W~CW`CIWh%0oZ
zywxG@(l(g*n7i*T<cGP%6g_>y-MRtfDR-F>nnt+cYzU5W*((7$#;u+YGS2-p4J^*Q
zj31zIH!s&8*1PZ?)6sYjZ_BR`aOE}7c404Xj3N$hymjs9ggft*YS`q#>%eZ-G1-%s
zOp}-wZ#sQ(W*=`uIpn>0ujWF+hgTZ}O}@NU-GJH8>syP;1H7rfpuc{+B@~|a=SB2_
zC4jelE&3G5D?SF6Al{)*ff>x3vKnn6JWo2|hVn*IVQ3id9ZDMt=LHC1p(BEqP1yvI
zylMNOB8vAE$qbXDdF#oW6T=&!#L<JiHp=Ec#Jg?*Xe{r!ttiFuayEh`o;PC>NCI!U
z4^$lHt-A-XMBeK!0VSDtcOz6B<^8-2l_|VD`m)tAUgcB_!f{^kXR!B#gI7em!))G5
z@!-kh#gWT1pXW=ll>**@(;$VsZaO>^@wUDVa+>$jVt}6EO`u<MF>gNIOD*9ITm<Mj
zo(m<so#*YSfQ6;JC#euG<J}xXTRHE&E)3TN-lU&Vs^kq1fwPL|SmZztFY<PkLH#A3
z8{HnM=B3j?s)iRtvDjMP5sGHi@#a$+z-8W^?P#m#eY^oGuJE#5A<)44j3VDxc|nVy
z@ER|FCcqkbY9F*+=Y34Szb2kv8LV&S={iwr;Vm6N=>{+Rzq`RVc^&ZpZRO1&w{sgW
zl^$$6ubx8Y9lTR%(A3Gxr@d1b@6sNWZt={A0CSs{MoH4$Jg;9->fvpr=xHzSP$D?{
zc<)^U>F2$Y0MqXAOyq99&s##<&;edNxtkyG#Ltk!Xpm?43J>-nZ$dR{AMtK7z%#^~
z@jPsL%)3Y5?i%KeQquktUj63~c*@JBTW2G@%{{0b<&FD7(-`jy50G)*2@-eaYd1mR
z9{ynpak%nRHPEn^-@Fb2Zv2)P(dN#7t^Ec3{yg}{XfgNXfBGC)z4)n=6t|Dx`2jR}
z^N&#!#fN{3VnM$A&EG(9KVL?_^aFgK0SNf<)8|0kpZ^TyUkC8Nrn6QcKbDeUgZP<N
zumtm8rXNQLpQ(ggC_iI41j6_|a0oaihx4<e0UE)#(1VTSAMk{xDE>9_(jVmSryRFK
z{9#%_V)-$*fR@02^-qw){N6PXNaQ~_fv26!PfP;KQT`_q$ffX|x}oqG|G^bh9_MG$
zC503G#gXVz20v>b1Ty)Pj$*VOS^R=WP?*hM@;o%<@JC;Qd@lcgTc9G3&!KZdK3}>5
zFopa*@1U)S{~SexPxE<{w_40!*8=ep{@05EdX}F=4zhFnXv&H?&wu3$C@ka8t3#=r
zpP+%g7x*tlLvJPjAs?kG2Y)f;`(5O3rj6$%{-R$2TFw9U1`Mv{cMgKJj_*cc$jkg?
z6icn={~3$Y6@Co)eH-|fzC&drzg_@=>-=56!?Y&;2Xy3W<_k%03;zQrkQ;m^9Y}8S
z+jH=ITKThQql0aHM>tLBclcXr>vos_YB@*`f9w%pdihNhlj-B*VdD+vFPRF{?(>u1
zLTP~Cmw}NP<bM?a@gaVf18tA_WwbO8^Nr+Se!?HjLEBTlTL#)j_}?YN&{6)=ag@gR
zGe3sC<9s&<r6xEF-lEO_Zo%iXAmJkDVW8wDXrM*PUEuaDDm?_X^p<!EE<c34mtcgZ
zyM2OhDQ@X4Sk@1{J^~%N$$bUCC&T&x0b@Q$pup`7bTmky8v|IdU?%0)hX}$Nff*_&
zETi*ZnBW1OWWoh46hw^>4A8;xpx|F})*lj#e*qFJc%=Y(;{-p`ek@+#Rtf9`!Kd`Y
zIV{L(f{H{zz7ph!z}kkcr3zM3WHwDOn}SEj1QisGI4)?T6pj-Dz8S`(3r>ep-p)zE
ziZTdh2ofpFIa6?80u*Kox}O7fj^OMoAi08|47BA5ikAW=U-0tBfGH4kZ$@RIAkGae
zMFLA46rL7*d=p@21R<0eQ7rJEhqe*{`w=S31WDu)E*JDLA$~!yIf?FVR0tN353f>i
zPz|&yfh$c-7X<~BjBrWNKLw!G0!0<j>IEOa540<SV>PI35LoE|cU6!*5&gX;n0yDI
zje^xTVBvK^F-0Mp1ozIP_sxO`ijK7j7OjDzcELw<d$L2Yimrq>It5M_K)VF4zku8l
z>~4e=w*@(3kZyq&h0N~=u2O8jU+}U7mG=abD13Qe5OENi1_b|*NA7{3^byP+6v%0d
z`%rM|XK+3e%%&6dkl+t*D10L5eIBK!f=x$Z(}-aC4-go22t1YoZA?(T5Io}oW+~8|
zg?e&Q?iT(|aZeZF8x*A5BkZILe6GUh{{h)6e2Y?ayo4XeqqI-Bu?2G8!hh+A=_9;N
z&O%?|?LH{nFHBv70XiUjeLw8=6Z$n_Ec}Js<<J)*bgWK8w?l>ZX!Z&d`X&M`TxgGg
zM1*iJWo$<ZyVbys68=pmf@q;+3sl4ix2-}i;)Rdt)k_dI(W`e@cz|BLMBxqc#2pb<
z+=O_NFq|&;B@5lI0_CW1#(&=d6rQ8I1}B6a4h_sm7k);*u#>{xyQs|&4wLU7Q&=<%
zO<6)ua$TGf4hjI1EtGo#J4e_^@%wz?^i+r!2;F+1zEC)gw$??$_AUsV7RE<I{ETpt
zJHU#C?sO}!MELf*AZLYcMd<E1;l#xhD?cxM`vLTp3d8B%Mx}5GIV-A!mIlCF6y}v<
zfG!DNkU&$lu$FcfHNsj7^VSMwBB-bn{*(*Qt3oZUf7gT^6jg5&S}Z`hE__xF&L&~=
zj{s{H-lcTG7U445o!t<ozD@TQJA?tD!0r?}-UR6qHpkM7D6Coxa$C4H9iZL9Ewl%@
zBP^kS@?D{AGsr#RJIC=T?+a7O$2lO}LbpF22q#iFVNke)1HBK0SuU{RkuaF{5JSS1
zRX}+n^da}pQ(@*O^xc{fp)+|mMujuTl{Y5TeTP997xvQm(Oq<6FI0GleouzHr$|ph
z0x!`eCy;%j+G~LE7P)J{;v-Vfja^?+StB_2i=NQs%>$xU<Y)F1y-Geif6;4{78xK~
zdJ?7uid@MT><ALgiULfC=yE7PLq&abbP5wqq;F${i$=*I5Fy$`uY8oKp0bUjMIn^N
z79)zD0?tFC>)C*b6{XQQ$BBgGu#Fe}MMs|m5o;>Q5mC+@KqrYlqW2<MWS|Y_QPHmk
zV5T@k-#eo=RrCjK-O@yvZ9qFF`pgKy<D&WRpcm<){-02JQZ#1=NQQ_(IR%*_=Yt?w
zqKuC~PKg}7=tPdlNZHM~qABE#%oAPv8_@Y8s~XS+qM$VxghJ7BO1du+{jUNxofbKE
zTtVX*5uY}4#iDEEdn*y~XjM8Z+7$=+bD~wZK+cP@Y1%3k%`S&vndmF>t(J?vrGxGT
z(Vyg(uMq8N21}*rw{);niMD(W>o1B-wA;BP;?s5KYEc8N<#nPU3Qt`Y<v3mhPrYa@
zxt6Yo#^?=h5M66W<5ki3FQ6BVqBpbAc3t#E7dqM`dVd(CS@i6iP}m|GTm*7MB+>)4
zRrG@^#M?wq-Umy&=<W@aIz`$00oElFQ5^1;Xj%-6xh+a;1$4LQ!xY+o-Vtruk6zpr
zeX|riy`q+hXzUZsxq{C0i&S)J`<`ei%^UYckvqZiK-5kf<w4PJvp^n-rUZiJktpm{
zC>#<s(6fImN|=d3cq+R67UV`mU;F{NQPJ{?AY&pgI>C&K-gYJbi?jHjPf^@0-r@#h
zT*U1zkk}*MPTpfz@l9Is_KFXLq0LP^k&?aK#nG=pz(ahH2H#WcN&ZAHu@8A#_ld)4
zrS%rCScQ@C5g)w;IbZRu4`AAU@!IvkJRrUj1hf6bTbEMaj=wlU4wwM3&vqCbC{AdC
ziXiceo1h|CoJThfL&Sb_Q5h;`$N&>2&hG_wxR{#@5+UxI2+l}x2i+@;66;ogM2na0
zgItVwu>vdy#gms}NDhgwctb<1cs0f7;>2&zs^o|lm+DYV5YPGnmL3-Oj{+@G{B$i?
zlf}Qyg#1x)939zG#Gf&NohrWX4eT`W7v$YICSLO*IFF0Z{eV855YMBiV7mBs+TEQL
ze@^*W8RC>p;LH@K-9cNHxG5WbIVHYMZuM-3*q^q1IpR<qhAmgjz6rEE@d!D;^2I^z
zfGH458E7jMFC))okvN`?@~6ewbT#XYcpV*2ip3R_v{53yO4)2@#eb3O;hZ>)-iz~M
zeGueI#UbB;rA*xZ8muT6zdr($3u1>qO{Ep$PiaE06yN>;JXPWq??HXFSojG@jktXY
z%&!%%c^)iv;?S2sE{i8o_@!PvwGiZr_;(7hHi&;|hNi3HCqIMbnz(EnRy2w~o`HvU
zUHmUym}(M#{u%_D#Thi^w}`hpuEWF|;tWbfyeY1vb+=U<xC-)Z;z0`}+Qr-G`E-b{
zhQjVnvF3MFc8R+vTk4kBJqvAj#Iv(dx+`8t88bcN#)V+%75}>vn0;a=cbIlhd~yRY
z?~9|Kz?cDX5#7#tAZ{9>1eihbi(SBeC|*prbcV!tdm;Z=JZ}v0!{W7FV0j|mNgjx&
z;vp^U9ufccHdw~QukT0OI9?rqI!j!<L0lx~$n&vBlK(AAu97R?KyI(3$RC_;lK07v
z=pk8G1mY?A<`muA@RCd<ugX5j&NpF{w`6n~h>t{>0{Q(CBSo7JNPbuhg?^Iamr&_1
zVbjhaKr(?|uRuu=4?PT)EL(_Dh@_W-bfFRn<-bHqKBsVclq6{tDx)R)Vqsd0WFj3C
z4oZ>>DQ_oM(tQaE<0My`fgLZ|UJA4XNmvVde^{cVG{r<oqZRT;Bt^71B}<mkntW8k
zIt7>%$&H5)PnCo|LMPHBTO%QUT=Mxeh@X%+KZaboWDX^vpOpOg3j{JGatVecQ*wrm
z@Qy6Wu{99Pk=&v~bgm?m!nJvl=gCEzFOe;TV1XovLKH=k$*a+s(~>N@TX9D62|eFp
zN%uQYSR(oDSzw=)Y|Tg8dC465rIt!A(66{mGARS4a!DyAvtE#ty#{?1l7*D&S>=#?
zPMIqgC2UICza&|(1Em_tN}Ba*C27O3v`(^uQdTZYMz=z~Ub2o7b{Zu143MjmX`SG_
zCb1G}lql%@cU@9RF^wk4y<cEVi^TOJpl?XNe->>wCG*J#)+*_%g4t~n$1jv*)-I_U
zgQiZ&7q38~OS1btpxu&)$uD<TQoag;J(4f(L9kb{MFlJRB*!L0pkFdjfo|WItjPn~
zfFy-dpdLuVSs;UwuD^itQ1UK)V&;+L+e)wuN%oU-a#%9sJ@oU5WR+tHY<nu1`wqy6
zL_$8!QHh9dV~k6d(2XT$>14{$-YtD~8LV)TZl>IiJ<_WO(0f;D5cP1cw2UIj9?~Px
zP~j;J2>^?iw36}-_DK(X4&p6Mq$9D9G@utOzS0S6LH0|NU!e8xfV7A{y5}dYBmaxP
zG?`|`0BPQJU<XS7JO|bw=@6yg1xv4%!n6?S-;|&mDz&#lZ<uro<syYk7u2G^5z^1+
zLSdxzqjHp@q#Y)7DOzfN0~%tac^^XHpmZa-T@Ok3?xf#etn>|9cjKhS3n1}Q*D7Eq
zNZTpoepuRg2CRwFq*+jLL>ejvT9UMG0Srx+zDyzWqtb8bmUxPE1O5C{rBxm%rAb?8
zD{)M^?L7K&T)Mvtawnuetb;(hbOG&hPD+hmlm8_{`o$KYosxD0Kq6aOy&0@IQV0FE
z^Q9V!q7+E&^b8B7n<$myjP$wl7>i=5kn*xhq&o*;_Ias*md{e@_jCj)lirGhK!sF6
z7ey+i#+A@eB@M!ccXG8fbSX+T(ikbk9ktSQx;juV{fLe}SENlwlp3TJYarh!owf%&
z*QK&qAWhPK8mAjlJ_WgNN;TwMX_amvk6N2Fn&Ld|Qo%D&*dgs-4MRJng><s*k~Y7G
zp52oEat<iBr59-<)-A2d1j}8Abm%Y)?vYNSdxX8x7nnfnla2|2)-T;kYsP))Q8fey
zq>^XR!w1q?^yUvrFVP1x9!kUR!k9-=cRAXIq_chm*kkDxir5cJm8oEPBK^z?g-@lG
zmB1X4%IH-em1+WjIVN>Xr&~$m(pm!=on_@VsNXGf{vXg>WQ(tXXRoZm9}3-M&(K-e
zT~^o$;vri;0Bld0N`sP@j9~`nKH2LT;PjS#-~=#VStxDN_RHL9>vcf3g9k-^GMC9{
z^Or56UvYq}!!Z*)fwJ}rkRX{0{oq4olRMBDCQGLsO}K3J6-Y$Mq@!SomOWUD&cw*}
zC4wB3jR&IbknA6NOX6gfr%)d+J50Ik39{e+LEB-O<Qudl%DR4p6-Q)iqfkncC4Pnu
zCd-a2qP(4>vXAKSo+3L%Q&XnwOPZ#$WWUfa?v!i=AC=j%MLp<mj_lNWz~st)5kXU)
ztadsy<;z<2s4S2zpNvwW%$*K0MY2!$Ag5(7QDWg4Sqgb^im`pe11*t_QtriBS;ET{
ze>f*w;R*HUWm9<IDV05@jcb|g71|+`%Qkkxm<zJ(PzYAY3i_a;QZ{b@0#&kCensU)
z*=J`^x+L3s2%Ocj%qmpY$hK2HWv%SrSAkM5TSbW=S7gE%7}_AKzK6<2nFe!-WAb&`
zzh01Nk}Wxd+Gbe@#qnBX36zp_L$-DTu-jz0l%>@!`<&7;J7k8tAe}Pr2jJ|IX(Azh
zOO{S!aa-0(>rl5W`5ed{SrZ*W?#kX=i&BrwHwfx`Wj}m{XV)k5rRb%jUslr$n0vA%
zKZEtY>{2Djfb1-RK9HUL19}H#c_+Z~P!?VbV;;#ir=e{~=0V}d$1*z&*RV`O5$Gqf
z;69M2GP?}eBeI<oJ{*;G3}d**WJf+g2ghZbXz-ooixm*x?T{a(izY7e4djT}BQK))
z)m2`56$<yt2Pn4TCjYt;dfnyuKcdn@{uS+{Jms%1hh8uFk`}1gCtvJ~N^g064Jv))
zFVp_USI(aYL;d6%$fN8ppRWT;fP5Eaeg(=G(<whl?pQ%_^kDfyHLyeE6%_dnm8a0O
z6DI%C3KA}F@BnLs+%pmeN6OF70cVuF<uKZ!<r`?@86$t0@;VO6!w$jTL-I;msAJ_X
z_(Of1Jmx$!#LK^o1WJPZmA4_DC>OZFrX%t_4x00m<gr!YNtTEG1Hq&6-;5Z<RQWTs
zV5iAHDu%={`CdA_r_2AM1eBBVoivwa$bY3Lnko0)fl`({P78&n<Z~&ymMwpUPANI^
zi4=y<mCvL^**y7LF$D7ELqc#C$df*HpjarMO!0ss`HrPfcv}ALRj5BBUrr9!V)^gS
zK(Iu9n|_;T<@dtT!*g<VA&faM&)E%9Di5S(zf8V>&SB;92`9mMK`u0avqF9(9>!G4
z^%-EPlCL=r4HxA*{Gs-e{LV(oo2!<;NjJ-C<YhM@Q7iwH_S<#xj4NQhEMM7(wtD$`
zf0VAu*OABNn%wc9(_3zop=;OWGm22zB%e<&X|sH4KR8?D=1(x(H{^aFqVlFZBNqx=
z<*~yMXp=ktis9;z7fqt?=6A}!qD-4Ed2j+6`{ZdwApP=LY0!I5K1~bx`*LF;N(1t?
znXvGIeEwmu49dUnL4P00t;IllBrjSCG9+I?)8w%HJl%48BEP_d-luX|4k}0FUolZR
zD(@&k<(T{c-QjeM%ej;Qx?7P;M;{l()}?^iqj+fyB{#+DThQdLSV_0PJQM}ZD0wQ5
zyo8dM;tdAKKE=09FwI+W{#}%O6wlJj;;T4Hk7B>#HFA&pDPEy#BmRnchrkk`m|urZ
z1S$e3WESL5I30(kV8yLdfC*6qE{2LQMMNCr!xd6`gCi8Bl*ACJ7@@T$O5s7Ctr$f$
zxkwKxT<HK7tN4jFVsQ#h5QZ{dafdRP6BW&?Abv#g964-~6!R!ZovwHg14SnlhCs+=
zC>$9t!Hi7BQCcdq6#tt5y{8myzd$fo@gqeJ@)SMmP?-<^76c0vj7F$0RA?x$RHX2i
zK<{bArSGBejN&~?9x7I3bU>~|@fL06&njNM4!!3TW0YP|s+j!(1j-cg)4*A-xaz1x
z@q*&vVpvh3Sbh+!7ZrsRPPnA#Y(-nO!aoJ28pS$_IoB$3Y2B?;{7Uhb%ZgT7B<dBy
zHITca7$v`4gW|{C;Jm8%WDh!VO>r*)q*2jE(XH!>uNOePNin|(7B(yT%IN&pqA-36
zazpWW2=X@-8p^wARkSWZsZHUUi2k-KGIpZWp}5}$`A$U##f-ZYW;)^CQVhHb?Awat
z^TE=s@Tayriq;ol+Fiv`nl^eAzm=lYtN7pFXzNofY)56kV(b|CKkq4iqO6Deiqd?*
z3@EzEKlea!t{a*L6<w5>@K7=HE-ZYc2q{L}kYXAK0*@6X<Te^sXzqjMiQ)?ZK%Xl9
zQR7jJD0WYW*`tcDD1&lL@ioPT#}&3RSm><$E*otw%6fQl9FzAdm+ypLH)RYxW_RVn
z-@)UdEGM6zr}AeyaC#|+=)Ksd{J0j+&|8^Yg-Rb~&~>QyRd#NNG5eJp=qok{l$R;(
z)lVrb1&Y7&A6jGrlv7_vDMD#2gWgD`dmW&ol()V|n<HB3aU8WV%3;bXJ*f2j0md9s
zcG9DaRo09HJ5K3#6{UD(2c2*elpoXn=CJZ*`uQg+mwpKGBg$)(Uy-EbZ$<Bul>%~z
zA64eiMmt4mr%Q#Y%3c4$!ZhXIuc35IS)32f;|`^K9P%fWuSy`1uH5`JYELS2y&;&P
z)a`<anaZJaAX!S;UC5tOX8#FevX%A^P|8uxAjfB}GJrVql&8$V&Q~goAO%VT&ESQ~
zDI@4ak+N9>&eO^wa*Ul(Hd2ySvC{Dqg-=S9g>*nTt5gWVb58jr5H_7x)_n%nGUcKX
zypQF|QF^^DD7U>2y%oyf>9DX;*|Ho0Rm#@25V)vZGY4RoluXLms8){B%v7V4(w?|h
z$)FHlow9~*qFq+Hk$0j&`PF~_8*^1z><1ICDgQ?^MWb>N<wIXr9t#Celk(?QSkbI}
z<6{W6C^zfCc|-Xy7*^a=2CN2ltMZ%2sBBaA-i3wj%3dGHbtsF*QR-C2x&yOI`7Aw(
zTgp5apxjn^{|lCG<)<?pu=|d(mv#tum7l%?i5{gVeM6*I8A(3bK4r-NAm6XNPEpr;
z%0Tj3-&c+)Q5sMNlaKO&awaWKgUa<ZKR#40{1_;Yl%K2s8B!)~1m|OA0qxv|l{FW^
z`9!Jw738V1f-&iP{8p4Qx*<8LTu*;iIi}3BqBO45UxpRVszh=E?@`U8v=Ud<?l{2g
zRh>rW%483fi1K|rRVg9&wG(DJ7SlVkUzN52l?PPj7l7iYdS@oo`>S&3;1-}N+JsV|
zYRmu<r0S3ZGgx(u_J1L&8B0(KRjpVF&M?)=0g!N25QPdNRCj(xKO<Fp=qD1TdX@I@
z(W>nu&=;c`q>T21s+o>S06nBSOd;G@Rl{TSK2A0FEE?lgyC#4ns9v4|!NaO4CFn$=
zDu!GoM^rw4pmbEV<ZD=wqH-focB*P^JB&H5nojpZPpA&jHZWZkPyo!6sugEY%24h8
z6_}Z-=cl7GOSO6yJ;_t5_}5XJt@<hewK*z{9B8?!K5``FsouW;(0tX>B`6iBUfu>$
zsCp&{Rurio)4}Vs>J~*G&#2aFpto3+OfiBI)lFK2&#E{FVf{JP|IVT9ylPh_Doa&w
zzW`&(RBz4yFOyd#UIVlXsvw$|D^$L_K`K=$8jC8G3(ZUyRnv|@Z;dLH4qmmYZV@W$
zRC_K#{biMYBE;)eb6-c>6_wBk71vZ>(C42TRTE~Q^15pH6iVHy2VSt^j%v>@P=8mo
z50P@m<Q~;%46u7uQ5hJ7K2_&QfcC4lQwHNb)!Gvfys!FWD^v`q^knw~)hn0KHmKq~
zM(LsI?*mZrNcDX@IEPeo>tX$4RSuawtTNN#=!xnL%FBJK+I$*a8c|K5nSWIEBoT5B
zXZ7h_K-;Z;FBy7W)C<EQxJRuCMy0Eo?+LP3ojD8%H}xS6SlrbMC=TGEew+Mip6Y8K
zqU5DsO_}uj)ce~Y;H~C&fzwC5`W=AzsxQ$rw_n{xNALsc5Q@wCsaq)v#^0enK~qwI
z`fCwj0@ay6fi+02s6i=MeT9B1A?oxINQ9~#l(i71{*ru~;p+9|u8L3x(x*To)iZrj
zic;@6gHp8mJ8#IvsCUx5cu@U5515D4ZnUe5RX<DbQ=D2vC);?n;}43eC#a9n59qM^
zI63kX)#Z2a43DUJbaY8lAGi&@$?B)i0{f_X(?rOpsK2D0d8*o#d^2h4Dw;2jsUJ)R
z=yCPe_c1aj)Kkdyovu!O5#*$L33>i9)PiqeXr|he&Xif|e#dt}JEg9oz*4q)^b2Up
zQL{>bovSX30LfEV?1kQZbvmtB1?q#VAz!HOrVk|+sn5hh;Iz6u5S3@tTfPKnu{!@x
zkP>wXow3fU8|W;1PF)j%4xU%PN8jozRli6xcbR&9G<nj>)h}NM_67A9Z$hF%t)N`V
zN_89!ca{1Va&K3w&rwvMMm_N)O10{WYe1`0S3L`X%j$_V_13H9pP?^T)MqJ^utEK{
zFZz2`{f{T)uBoH`g@#78mO|{;)en!MvPrF9Nx#2lbs-bu+@jt^+rd`#&LK3msZUeX
zv|T-62GBaxr)k0LREN)m-Cb(&GL*X2v*&>2j=F0##P6zYp0J`%?L~*le)VZ`?c7t#
z8EAW;t|)^sgX(y?q47{Xo960A>cTF{q#sh-K0)JS^`qG^e^?#o4D2WBiQVYvQ}s#O
zXOF0BC<}E|oi+oejj3A`Auz6<{SwfeHUH9Q3U+Jeu7YVU8ZLPd_GmcAQR%9Q-hc<=
zu6dh0jvg9a7UVoNmuN!v)~vq|D;z$WA&PhUYKne@{C>?Y$}BjbnUn$vKaDHpW%z5B
zo`$9X&3Zas1ZoOq!<ZmV0Uz?gnk?F+g=iS$dk)n&y@$3i&F}OzrEtxS7L+11<_};~
zq=qvH=qL^Q0xAz`YT3|m$f5bz4*6J(n;O^&nrFx{c387>GDxE4((`CLqG|dArX^|o
zo<k{FGmkP`k7~Zb>peL|^Bn`4QZ-+?pigO<l-p=KrfDP(!g0;Jzk%h1reZZTrE4Zd
zq4K0=_ctIJn&er~kg0K)-+)nBn&KlcF-J2*2kTr-`bP9OPZL2Wwqi}z_vl)QCY$^M
zXEi<Xu;QF%;uKV#*9a({RjS!n2e~p$v;qptH9vm_xeJ;JlxAC@QBcgPQWMpOwkpjQ
z50HzRcVr-!G}|1sm9N&U`V#7EG}qICU8`|F2vVm>rewz}n!It0SA*tlI>ueqIOn1A
zn&x?mr8H`8P)g5r%>;5&H)(1p_qJK%{1e(*G;0n(eXC}y7Nkw{Q5XiHUGpl1Njo&%
z3t?}kX6|eB`|Hxoxde$@8dr*f+}8Ya1f_1xvdLiW(d1Ym*sHm?4IS;%yiY-ie$6&=
zTHn)LcpC!uHEvu~4rm^#VA=!CU=<V&YG%@oaY*yP1C@_8v0s1;YaY;4_Czy<(vhEP
zPG!><_(n8CIglUK{7CtBW19DOLGQSxcN<t;v_DltaE~_pH)wLzin=if?pmo9Z64Zo
zvd~j|pH3;>+J7FyP#-OmB9p$_Q2|PR+B7;&`D>eQp-TbUYKpxEYi~S<wh*le-&k=>
z4%M21As?ajIu1>d+G<)cqqH{42Z`6N7DFOIn?qsr!`g@RDZ4~%+@D}MqBS3fy-C_R
zl&_Pl{lfs8j%puIgTfT;j|Heq)o!MfZJPEo@;V*Ue*HFBj%z0^1Ir2R=afO=NY~!H
z1NA4hpVB8=GPIBARF$cnNq*ui?O8gdoYL0Qz58tKr97z5(YDaWF;}~gGJ*57V+w%g
zYwd5LRG>|o4}n7Mub!~CNc%gH(^{v+5ICcqNoVL1?I-aloz<2+gupq6)@drtIInGZ
z2}YG_H_&uhrrk^d;d1R~4<Ua+t6G3juh5>`gI-i>e<mkim9}Ot<S%MfZ^N`pTEF*D
zS*>j#cVLZnBBkQhY6W@-)M<0mfpS?};(+=F?Vok1ysF(wez9v>$9fkS+@$@QeBaI5
zGtFRa(fZ3#*{XG>y>y#4Z4hnk+OI27>d?OVB}$#z;r)Q=(yk&0e7Cl2Daak|bM)%n
z)%uXnpilb``S|;_!yL%n)0V5yc3=A{<tz<ocg=<P1MQcNDAYdE-X{0lkT(1+kjL6@
z(?OnUH_|qCM9ZU~)2Q~&7)*24&8I%?*6m`T%|&NBhd%AqRZd2wn=XgauibT@-bBem
z_iqtUJaxwsz~ZIb=Lh1aTTbad{<`Jl=n2qum($NbQ1{j&m>;C`qt`lEC!l?Ah_3!U
zm>;V9U@b;AOqWk_v~ZoG93(;~oQctk)Fs8E6s1e?fHBcJ&2q@a=(6Xb?VxTV3&tGM
z{pbY}tII0{bewKi9NOY_Z_ybmL3h_k>)&DBf)!AasB39J;}P9dawjI~uD=JKWZe(m
zu;QpLy%CyHbY~{Q&{W-mDbSRr8_z-IG2P@>fqh&z=Y0(23EfL{y)<2SREM^cx}Snj
z%Fvylw=+{WZ#s<0(#6-KbV_F}q)duz-8Mg<<>>Yth84NG>5)*Mr}M}`WxmdQ5%LAP
zf<j;y>JGjFmLeo&qI6nUejYGqbc?p3vRIczT`SQg(CyT-y7@+w&gq`X2g`Zg26vQ7
zbz<6sl<B-FFj}rNm!Q&dLH7aWKvd|w*5S!i>e>Qeca^T97d#hrt>h`aq)VpMt7_fv
z0Vvh!Hd27)vhM6LVAtz%^8s^J_tSn<Uei6?2-2tvX@}X(x~U%lrA7D5zmU73TPR0m
zn=bH0fVJzE8=<ztq0?4C;VoSUJ(AnHHXf|#*8RB#pm%gFe&D&Qdxz%b9-TY=wtICl
zI#KuO_S3nsUzbba_j|f_dK2#J%I4rv4Cv0!g501k`YzNz)NP><-6P%Kze4YjZsi(?
zKh~u!g1%v$qmdGcpXlaOaNwz~=5;iV=)U+Bm7}^ZDC=lUmwy17#&z}N?Q+&fWuR@h
zez+f%E_xqY7WU`|i$GlU7wKTISD)yMHaC6W=KyopN71p!LtokpaZi1T5XN}vHC#aN
z)BoZqMy<F0H38K7=(mxZ%~#(nf^GZtj2H+W(1&dStDnB%5Gwuko=Z^*&@WsBfk6Gd
zw@?|RA81A?SU;b<pdtDf15gUpH`9?ROmCbDmT>*^@4><d{r+sIkJPV<h1w|nzH0Jh
zN9#lBDp!oYihj)p^)iZMAJRv-qAgax_$PqI={1z*7q3sQ2X=yfYz?pv>-|oFB<knK
zLhgv(m*%M?J&XK^$@(Fjt|lMVZ>RYpMSoWblB$2B4A5!%)vJJVOdl~qk)-2#)@`Ui
zp`WIJM7sXq&p<n=AEskQhF(7b250K4gJDdTesBg@PU*+4VGy$QgT>I4qyKR|uygg2
zc2wr+=hLw&UmyPtN(K7YDU@2M|LT9RzDU24_Oz$<Q^o;(Mt{zSJZZ)HGD>bK(N7A7
z;8}eWC5N5Uzxpgn=k;%Ep}thFB3E*m{vM@gl<Qx79|9Nj$LO3~p*N6ozf$i`Z(x=F
z!@J<Ts1FW=y_fVCUq{bs^{2y7S*LIQ2&Kz<!wr<`^)B5IcU;kXQzm_bKJI-eysDr6
z53sN4^QQo<QJ=6LZP)cOZ|H5(_r#$0&H5V*lv?zH7a?#%KR*)|-qh>1L9SIl@HO<d
z=~G{Zigx`K9>hEJo5*Y2sSl#%w@csX3b|YQ4N{bDJM@OXAknQKpkT%weGKLI-qpXk
z6M{YZt#Q!QtN(K?So-t>>%h{l-})T{@9FQxgY&+A>Q+<^=)+pjnFsm+T5t#TJ~Z7u
z)PH^uRy@*=(bt%U^xZF@?Xms?I#3Mjb8bNViQch$2Uwr#f2JMwh<*=UvK!TV&?jKW
z^q){p&ba<_!ge+s;i7W4q3{QQx*B3Ah_ctPQ;bSC!=6qMcSG|6RC*Xf_5sY(kV|(3
zybSzLVDCP|N^*yI8#YFu(#P;QJqlj~$FU4(`wj1OqV|Ac5&3fc4DIx;`x{azP!eDe
zk%uVI@ZNTebC4mZ9HSR(I7spD5W^sO^+OGJ$paT=_@3N);f8-lP>L}8brK}f;6uq>
zQ3f7;(lpv&v_K%nFz*O795k$3O<y27WSB=OTd@W)$;TOr{|DRR4cjROn_!qr*8&b3
zj`rdiCK`6ob@n5MKMp{Bl3`mdIFk)$DYf*d;T(NlA;s`vIOI|dN}5U23`un6Ic9kJ
zJ&ZYS;GY1?NyBe+ttP{esiysBra^cE#Vo@~vip=F#RVp28&)R+CdV-S1xVx?z9heR
zo`Lrl(DDrv)<dAcFliKBD>Qh}S?P>nC;i5X4QB>HN(@C~u<5*E4JBok8rssqQf63m
z2jUfm149t6G<d`1=a^h&Xr(N;YQtr6V$~RiDAA|ZV0jay(Xdv7%Ik*k1V}U)hE4#j
z+2DHx0xgDU@_gJdytR&g0EQyUgl{#>S&LGe!9=^lcEjg4z|vtDr66;sA!;#Lx(sL3
zAh!%B^1<S`ZP-BfB)bjokstAnVbU2i-ZfY$U8u+K^L5Dg8m3dyMW10tKP37MvU^Z}
z&(Keyp!<f+k73$?;Z^c_Jusxq2g;yfT?IHF8hTq%`N*(S1(YGfSP2B48fqt^6C;Kf
z&VXgqVOS@I!D9v;B_WI(m>H08HlFz#pu3G{PovGncrg$*xfx%h<;dOG_5lPvjECq~
z<!Rhe4dP{d^9^9{GrCNGdT-+Zo%no=?(0yw-}v{JAP0<_=)S$5QFt1U*WdVD5>Nt+
z4o^1Z1C4*@pfSiO35TX&W7}Eqgc#fBqb<}}z7{0hxQ8ac2xDS0EQ~bj=}uylvGOcz
ziZ+fkVSo-A=h3x`Lq_`(kXR#&j+pVr*OSn*1mlOTAcu{9w6+~F_P7Hj$r$9=i=jz2
zE+lvHQR7Owhn`||??&mEv33zk$Bk3&0PTcv5>1ooMhOLGPZ|dlV978Zpr1;n(MVV3
zvW)&+;5=oN-9stYsBS?I^Nbf;!I^LDpAOCf<Ly--g~r}wR2CUms2wolv@!Wp^x};1
zZ#uUY8?)%rbcu1wMzozZcDAEy=Zp>pB+eTRwBDB*?O&p;%*dvck8-171G;v>$fizI
z7>hp#*hM326jod^etZ<9+89HbOf|-C9mH#mQ^`3}XPh5QH(4$lCuF0x-uSEz@>h(u
zPhet$v70uDSB*Vn#WmxaY_wfB9-{j=O~y|PU}3Xy=?;(<<6;Vl-Y}-5faRv~m76HF
z8nftvaGP;QBdl*X>i5FJ4r7-9iaL!$J*ez5CY_=$5ZyA)Jq*FyM&$yKZsU~SA$Z4l
zmCnm|jo&T;Ymf1tXtebjqo<+NXFTf*oBEAI(I5lH1@#~gjB}7CGI`K=_W;xn8KddY
z{@A$qGCDDAjClv-i7|s_yQju&^jeJ=lO>RIj2l<}4Qyvq%rfxoHf@}U9_}&C_yLu!
zrZu$b*=u@4#<-a(>Ai9{r7%$PFr`v{t*5D`9WY)d!*&SlGihk8@HU;M&7qH}U@|Zd
zm<D}7{7mz1LBQWMx&<V_R5A!F0v)Dh6toR8Rhj`4Yzkiig(0RL^v;Evf@$9zW{RQ7
zB;3^WF(e{Pt-HYzX^Nsm?<mvzK2R8Ks$)Yu#<Y3}-9BilejWmcOo~qEjWs=HqDyh6
zlk^3JMAPC5h#xVT+aQ-@a`;lzG}-heInR!oyw5^D#pGQF>{L@t2`bY};}l&!X4)AH
za@^FF0+th|Z%;!m-Skr{&`z5E^?<?*laz80GEG+U&19KgqY&&VQ!|}@vrV{GhWXrN
zpfFsnDPb2h<e5Hm(Do|dR7DQk0#gC)EDB9mf*@FA8hRPzv}x{1C_H1@%R}#rO*f{Z
zqa`L6I?0?hrKurz&NSyNP|lm`6tK6{)K0sGGE>YaP*`r-FclrWU`ne8sW3gy2WO?p
z;|4gZOwZ&wpyHybnht4~OxyB7s!dW_+G|XVW|&xOG7NyV&a{)}<;$jMns4e&F|%RJ
z71Oh&=xBq<UVze7({=LBUo#1pq10$PN`_uH-J!5>lW8H%GtH*;<eqCWZD>K|4U=Lw
zeS!9-sg%5Yt)|F6*xhC-qOe%I={K4Mx=d_Jy0~R>pM|#DCOzeGb(<LUb)!3`(s^jR
zYigp%OpnQPA^O{EDyCpYpXteEbhO{}IyoornU<K*rTeD8=my(>DT^|`9+-Z8m;5h-
zrij;I@Q~@n*TDMNw1%>phfNG}Nj)*WM(UrMiVbKRF<mW!{HSRkrK*gX5<URuxJf{t
zM{qXlK7zvCX1}j6KrZGD$H213{GkU*uIBf1Am?uWeK9IM%om~{;Au8ecO72l*>t?w
zXZ}<O9&d9#6PkR?uC!b7HS<@awBMXK9WV#XHwCcC&&;FLaDOwK-rNAQ{&m0vnvYxo
zOOW{)+UEzGS<gX5h<Sz%oT29X)o2SdkIjcbxOpx)3nI*CUWUF%hq;)-Hc@8LTnt;Z
zIrJ5v9WtLuL1V0W+ZPawGvAvGw0QIS3t&kw``*TI9X2=m!NNrIV%mKlF~7(GXp*`9
zb+9CxBThj4sM$q?$`o@DO(Lo0cPSc?W=<zB!Ey6zf1q^2>}ZNWG2QGzyStO-1P!n=
z%q+@<%`|5?qb<w4=Q7AC^He)Pv&~s!P?2N)tpqmZnqz-Msle>n2SW?ZvoE2t$m~p`
zUTlt(fRvc)mIL~%c>?V^&Y4$sLc@9U$`4Q~HGk(giN-Q>S_nwF`Jxabbiw@Ud1$II
z$5JG#((FUNjw*98U8cBbo=vCcOXlt5GpII;4@02F{H`bLtu>GT2K9C3Kh^;IvN?cq
zMC#2!lvsPkyy6hR8qBe@(Y<OG%|Y8WbKN_%{xzD17D2^zv+z4~rpdf%Hn5w`zm7w&
z#r)w07<|Kgg2wBn*_$%ATFn{c8fr67rQLJ8IhvOC4)fR^kWTZ4T~L3^yqg8N+vWy0
zKzEyaXmPn?E~UlvuDMnNmLBuD9?E3uHFGOa+h<-OfcgFA7wB+!&upP^z<u+BH(~IA
zxtKDy9+>%*LNRFmi^xN>lL1ydGM6*anIZGH^r6JZ=HOwJhRxs5x$}v63FSjQHCNq-
z`VsR+9V$o7_8=%4Gf%>6>6kojcH_cQXUl5`P`lf*-W{wimVSC7dn_@OfZ}RtqFw)9
z3vU2J;%0fa4sGt1Pq%`2Sboj~sHf%MXq3DxcV>WPpQZX1h__`OZAyJCUgXE{wTN=T
zvfuIpy-x=$!4#))_*rf=pwZuwLjK+Wi-H1hftD4C01dL#`=X=4mhpd38De?$I3z+X
z-&_WEm}N^KdLM4-$wMi^@@)(ZjkI{uY8YiXM;^Rriwi}!Vl2z{g7cu|Ir3H?vShem
zd}A$p{Q({4u=H@i6L0x*2S|d&`~>8%<wiSL6D_;w-qR7wi5~%)WO=~`m}HA9J;S4x
z?UzxRVrik3GSzZ&H9*rWnI@29mX$+5Ic_=QhPD%yEn#>f=@vOfT~Au9!+_4Pa41{h
zl*J*U#XQ?G_88bXmiv3qm}~isTuXVDg|{J*ZwVylWPxQa4St~|@GDdnSqA7_bK3Gv
z2n5bpzN7cJ*z(U;D3w^`loEH=@)m7o&so9}z<J)XGZNyZmL=rHDYGo!i&D8I)v+0Z
z7c5`Uw~Q++9-qUgO3S$rkSa@F5%gZP{6Ws#OBT<GfT^~;Jr`{?mQD1uYAuNrsjsuV
z=#I9_me+5hvflEU5tUagQ|XV;8!V&cP<Yj{J{4`(EH(7IZL~az!5Ch*Y<cWJZIk8Y
zKopxTuH-psvAlI1<c5VOgNZjS>o20M)v}%eL)$DTd|^|&<(Dl0?Xdjy2TGlm8ak?V
zSzPI0aLaPq9c{NQ3;tWGECZCya>p`u0xWkeTXq4Z$1*JorC!T(0d$kB&+^+Q41T|5
zPZbQlXNh_SPvpMEsSfG~EKjGS^uXdt+t@*i?Jm$BTGA+%`pEJ}7hr}gUR?C)u_gUA
zunb!y6c2l1xlLCqo?7Hx5E!wPlG}FFvh5RS7_)ru0nTyDi|~XyCOcb~B%r^$t#h{k
z&BZGD8;yIcdfF1WTI*;V>uxQ{0E>t9GR>Nv)}OVo*UQ@N2`lzl)l69EZH=Cd%Kg>{
zlwEbeIzY3fpLIWdL@LmF??>1aWL@zQFoUgc*P=4SI>P|s2(|u^gW53b61qtiZq1p4
z&O}(nOJGc-^@Z6WQP!P<V2!rU`3Ed9)@C(26KfregNit7|6Z`fTbEI8XM**EIFt@s
z=Vrl}MC%{FfhE~G=N$+fwJ!MpC@I#g<!C!*y-g!?++ppdGsFq24}BXZ!@A=R<TI@S
zi-4A8U7QS_Q`VKV-_EuMk-s;``pN)Ua;>ct0LZf*qdcs9tAX4a1=f$~!e61)m2R>W
zS(hz^K(Y0R26{`Z-<D$V&RT2VgFvY@{x^^^tK+){&~j@dIln5bt#q=kw61l9-YP5a
zCgd+#@6lz?OV;1W{Znn-OVdt`HG}fhYpn)4Db`shnK5dYt-S(N)?05_U`2y<WD}m<
zRqK<F!E(*|lL%mqR-{1S&9{1x+o;Lf?HGh$vo+;&6kDvDN#cfegaU^*t$gx<wOdQS
zgZd7uz6w3;w06hA!Y->fy@9u^os^ky+v+3*%N?s5?JVwEm(#o6V=Z2VF7;Yx(mtcl
z8b=vW{nlBuYq)3i^~8|ex0(Ye{x@LVPw&+Ot6x2g8MKbYqV&-E&<>tQ)}P2zG-Unf
zb(9`k8!~|Q#HyxK^HZxkohU}ENi<uIS`+u9a?Cn`@(RbT%eO$l*=AS(n|9j@C|l3P
zw)Ss`@3DOl1mbF2xNaJLe|v3*=_49$wiWM!xZ5UC6w|}zlY~C)v+-#9@V43L#*dG!
ztphLzZ1J?K^t0K*q1WGLqZ4_6?MuqE3ACN0=w*=YLkmiwHrq2`3A3HnqZDpSAkRgF
zZQTQy7HO+GLjKPv+l2QpG|{$M4)Da-l8w-N&~`5gdJox37NSqFwnhJiPi%8mz_fVV
z)d{d7!FGbqjfZWKQ-GFeTNr`1Besc$(3WINO$S(t&5I)6skYx!G0bVU_qT%_v&AWZ
zdEDkl9!JLs+pccV4BKpSJ7wCGrvZ~?lTnIjj?J5v!Cc$QZWxni6U>6be4FZhfEL&;
z^Pr;8#xw)8$QH5$;-_sD6m~gdyLb#%6x%)xMO%q&T_8$lZ8b9>e$F=88RF+{9W>dN
zI&9`UP*`UBVFpx`+h&A9{({X+(bEc>hI|f{w)4LNyUHfg0_~#h$Y!8jvRTOIS8co5
z3C<c@8=Z%0ZH@+%>TF%)Q@vud(q6p5*3*Z+T(ymn6Zo1f>JL;l+N!+3dEMriM4wS=
zvR(ch63w>R<Zo)R#o2&%!#4a4OuK2@U5Uz8+ZHEOw%PiwLa^O-_BL$lutm~cn@-zz
zT5xvR#4Evh%hpnhPTaQrTaHq<&2|x;xMMr`GP-@&X6Qq=du%(WK)lyB*FmnOKHD>y
zVC}c9nFeF-*$&doIAH6Zg0=@X8zrX<+7dSc=Aq3y1LTpdn+~c&wv2n|(_`B%x@9(O
z`<s4aPi=fV$cQbF_JO0eF#1oXG22>-w~X7iQRK|o&iw|JyY0R2Iv}{m9!ismt39y*
zjeG4|-C%{A{T_{syZt6beZ1_GgHhUN-|7TTZ+kaw`F!j%5&-IJzbM8a?6)r&g2Ds#
zfjemPvtQbTHh+5{dC3Fp$9AGJ(4O-iGz8hR(tsIkFP%qUU=OiRjX-BY?Gnm146}#P
zUAb_3a}By3VL!1H5|Q@k3K$w?_j?^I(e}P<40nvZGz2ysv};{p(;@pDF+gMOUo3=p
zoIRL4F7b91`O_2Z6*PGrwtt%iltjBI1LTN3Wt6^TkYu0vF;pbmr{}`NRQq)b-lo~3
zoq>JKzVlg>j@#cLSIY@|=xbm}x7Sg|S*Cppy}4QTR@%FqvbSfVE!#fP3F>p~wUj29
zYd`D-^?7y`?cDP1;%`w|VAnJNtkC`{X>b(TXUkA~+Wy;7m{@FQlRu-xUOf$<XYGtr
zu=JcgVK*wz+uz*-&Qkjvy2Mdt&;Jza%k4HgoK@KKDcV$N56%T=mHn*+sJv+3FM;?a
zdvzNGs_iSNFE#dzLR8k;!`}f*ox`3^9-GVd`79Lc?TiEH#TEN^chHLldkw`AuG-g?
zVl1!OKO>(|qx~c$fL*u$MOju&_KSr8ZMI+f5CSdsjlCc@?AcGy-<$SQau>JSJ1H}$
z&Av<rMeTNf$_eeVC(uNG%kG##m#%Ny=YI;cJ9a<HL%D0e^(-2D>|g4kzSr(br-nXz
z2R*fZd+)DMc+cKZ3+(&$C#e7(u>bTeSRUBt;cnpMLHjpMh(ENaP;%uX`&?S19^17K
zAuw$3I*);UV)vQ|&ZqXb96WS;#QxSw@Qm4eE(2}cewi}+oShoepnkX0FdL@1IMvhq
z>gx1bE9Cb&Esq6@o0E`MJa?x~+WUAoEvECXr&GEwIK7;<|BKQ-r*iToc{_>eUG;JD
zqyh4ET0}Q?_B(kmbATRjN?U_QKc^k^i}iQ%Uj?23CmZ>&1D)p5O|l@T9pu*wcKU+$
zAmL7LHiASrRrrELIyD8r>?o&JH?TxI&D{v`7$;5<#1A@ot_9{Hr>!Aqi*?$pfWA1V
zl45iz!D)Is`Ckq@P2CCBM5h-@V8s!qU%m%xl9LaejFX+Z$xnUMX<ik2nBp|B0BEUB
zfBm1O>wt^mdj8qHJK&CTaJzejgVV&sn3!mc8e@tYqb7DuVoTJRSdti{=681}wxcOX
zM?pnUs)C>tr3pw;kR}46g3_c}u%aRgBLDB?^Z$JOIL>=B-<kJzZ}+{Kd8--pll0SL
zU_M3v?P}<y>gPs*oYv3MVxG_FCy#+-n*P>AfTin~MWQc5Z}=O1nfiiMa9R3rS9<@Q
z)gS&4*x7nvD||brxBC(@dHTC_&*kf-#V}u>zd}b~3iU@0LGiqP7VRG|=vV3CMUj3y
zJ<yBw2Wb6xQUA|;*e%g-*^Egj)xSRhT$x@*$F$1zhWSva(AQE;+$H_zv~)66>Q#+k
zFYA+DqO(f>F0Bx%^=oNMU85gLb*oqOJFB5zt4~}D$*cO|vw?k0A5ZVG>-sIUTd32I
zp+fI^{Rk>1y`i^%0<fF<#UH`Z27T-(U^eQzsOqRmpG9}>ExoWEeXS<FwFxk7dV8vf
zYS*heFzX%qnCIy1)PF)z&D;75J2208^p%q#c~^fS1^V~&Q+1H+(kIa({J#DHt$iNo
z<39&^sQ=@?HJ5%%BkVrbue%GBC;CQPkZyhL8-P943zRK-rZ-LY0orr@gm5VK=u?^j
z`a=J=3^Kj?K6)*@)Th#p@s-~97ntwUJJ5Q$Uq4|V2J>3K;vz%_^lK@r@J4?s3XOw$
z4b?}u7^>-&?rQj61qC<5vXMY>H#99oqlcl8rfauBWupDq9>Xz;wC**0uoR-+2LHF=
zg^%IPQZ)J+CR2TrpJC1gNctNlR)Yi>ZuMX=frhkncpqdar5ENt!*_w;_8a2pzpV&1
z^wN2Y5JQtCoH=0ljb6V84et)abR9CdP_bdCp~snie}@fg|4YsrPX2~j4>#Ct06AiC
znhNtr4S^TIMHv31>hnlL)Ca(hGWbv|D%v2N0~cecq2O_>!Ega{am+A94DPr=PhP|s
zqNuDR-Y|il*(VG>^eKQ-hM2#>B^jc3()%yj&^sKSrWk&vbV8~jZVX0v+AyXH4xcf6
zYKt+Y8LrW>xOBskI&hhWQ2K8XvJ4L!p?B6WdOl2K8|pqmV~(M#6WF;1D|(WiGu(a;
z2J;Ma$zZ<0mr|1jhSL<ADKtEsMD?HN4Ptt`TrkX_fO?T(-E?%880s#gvDBcM3unp<
zrte|*lHp|oyr?vcr<LkugB#u5HHPPfuyn;xG!hE61~(U=TsNft0);xm*x_ibH=I8N
zg&T$qS3qtWKC1#|gTed(L`*G)t0Q6XmLZGEq*@Ij86a(jc@$f1H_ZAST!&#6E&e+V
zcEh1~+o0%x!8?W!XOO#wt5k)0&k#qM)h@$w%1PcgY|6&<d0>dV50Qt4fXg6{3@f+5
z&||}-&w=^GFnJs-bejxIslMr{VQ4YfXNLdLQTOMD(=&nAV@UOc;tN9yg@1Yt(sEdO
zY50{4zA`)=0O>Q#io|8^H|%>4+-t)wJD3<Sd`g+dH-?+jfHG*PoC?mxXhx-NuEs$M
z8M+yl*@CzmO@AxU>R}ue1$|GWJQxPOjE5FNaj!9UCH)+Xb(971F;4yn9{L*9{g_}s
zV;U`g{f&(jq6sigd<L{YV=zUXgNzGiL2sY&UrGV*H_oP)Vz80*1ZIeF9IZMI7#}Z!
z`az@AM8$N6j3;T;A8Ncv8_vT<!%=Wy#;i?{2{*2r0)t14-t^syqsF(X{yM_A-W7Hu
zjWeiTF3NcO0#KrjvvXh~#%MMhB-Z#N6`US3cGAA$xbdwj3?k0>tv%Eej2TPOmuTed
zX#aQ8IER78DdU@M;F63Xk1!X>#;KH*OErG75#~=D8+3p<W0YLNVA70_q9KxQoKXzB
zS;pyRAZLwPlw;2}dNx2I$M}{UT(0rl5@4P)s_8A9XM94r-+bf2XMip+p4>+7zar!L
z{{mG;w=&3FG)hZ=R$?sP51CTq(Q0Uv8J|=BqTE;*2ayV+y%x?~GHR1Cib~_}ROe7-
zjQ<{_+PI4JYK)<a;pi1(EUoHljYlc;aLp)Z(Rkg+U4{2`#sIwpzrT8;Gu;X|j46A7
zebboo0F&QfoVymHO~#3{q2FwL`52a3j0q}mw~S`=t7<iVHx8ECjFFz`Yd0#Z;Zvva
zd>Aa<Hu_Rt>5g#+Re9Vs9vz86+%x(!;JS=96rsIuOg;yDrdP%?n!N#|Ya(O@jhVlL
zxH%Qs1ADjA<wwx)a?&q_hL6)`dUpFeEnNhWNT-oEFeQmj$0<XS;uKE-sx+rn`4Gu+
z`td9Hl;bpW4F;O$^j$WFROrOh`=HqALjxKsoc`DYlm?R%yBwYOoMv5wH_x07Q?*6E
z)AEb($$iVubnkd>u{(*rfGt}t!cyp#Qi}OSZCSxU|HPK<QQ%UyED^(e&X$%puv@fc
z6%SIn<>nZORB!o<ips8SG5-T10bAE7U?FU4B~`}8Y&B`V0CwuuCx4?gW9w&a7<S&)
zTeK=H-730-zUr-uX-9E$>nGT=NjkR9r$UgsTi;c~weGDiHo(Not?Z}Jd%bn449>VY
zzg>xedOP2sU!0%wv?`2cpYziiV1_t<$dGyGpFN-+>pW;e4X`BM`H?v+opk=`4n&ik
z^`v;(d7TSH)1AMf=S_z5n%mIGbPl8xf0py21n8Y}o=e;OJm>Yd;ZuS0U8-m*bawMV
z-+AZJEg%=1D^_EmMb6u((yZ7y(;noavvnIykn_lywD>4<{`CPAE1c)iI^&Y_*>BNU
z>3n|^e7fxHNE^5+=Un>1*Er|Qfyfo-Itp3TI&Yvj%2j9SDtLI^If+i()j69{u%X_$
zrWYbNoO>y^*XF#B-e#T7*AJRO1Ai_s$Y=w?#P~<RziZ5OT0Pb=sY`%=gJE_7v4L@;
zT}2ZUq=ZNd^A!iKmC2#w%$>|J6&fEgrDrgpUgk%7C%CXVk3sgbu~gKwkA03x<NvHF
zUB<(iVVje|zAOC~mfjmU180Zln`oK&{%s2WO{}NQ+80S5qx;K&aX|m7kn(3=ckM#&
zq-;uSP98oNGd0EcTflwe{R$9M+o`7J+XgBOpLUe$yQdE>LHmqLJaoT1^fPq7AJGVz
znF?F<&g!AZ)9fAR@$WfZffRq9``3Lm&C?g*-}4i`K*xenLoup_Z+(r?{Lo5M_v4ss
z$ow>ef=i2D3<K!mpk)AEvYaXqmtLUf!?L??fbjFq8Tj`vc@zj;E~Z0ZD~u9It_-3Q
zzF$qAXj%0p3s!zV5KdpxU2UKf1#4`0D6Gx&L-)EfuL1PO)FJrypRXxcyyNmo{Joo5
z`w&Qb7&Rr<J(+QIOL{TOThX|e`8FGNy_qZYCi7vcMgYQ>DS3{$@MBuzAri!t9faO3
zW*pVlK4t>uQU2!%<3i8RK4u&44M{&Uloo2c+0u_e_OQDjkR?`IfXVb?w{C!my{vvS
zT=izfF974ieoOH>UsgngsDA9zDi{oBGiVcYgw3M>ZX9b*&!Ko$LS-f=*n{*ENMN7L
z1(+$3?WRKyC)skk&rh*`oB(zb`;4mkl39%(WK!4%w}73>2GJ7dG#mdexHIgWR@hBr
zT}Ob+V0BbQk;zt4`EM5c3nf+4Mb9Yck|Fw%>S;1XUr|6aOVsxi&YTrp>_TI<Nwjk-
zL~}&xw28_U&7iE#IgyUaQ}aZ>orZ~g(H9256o}kc!L>q>iiP5Nk(WJSE{OUTK%q#~
zO&j21(b>Hi%SBPs2M{R{4UGqMsi<r-xH8dXI$TvQ+7}7E3Q@vTxP3`v^3njbQZ$k(
zIxmYBO@XB<Q9C8dszt+pfPRfAV?H#li2fJ~jat!R+5le_bsmDHYocZ<ySgs=egRC>
ziL6(E)QeOkc|-K_JPh6xIZ_<BL1gCv$wtwUevl^7#96S=EIRVv@2^Evw;z|}mZ;Gi
zmRdy;f9SV~3eUhqyJ)vLNQdZEJzzRTFKGjPTlA(D+#S&(DGc5f_0x{-o@fXCXuCwb
zFVydg_S2i}foSw^=zA!-GYxu=M8oJyN{>a84IocM_1h^#&@KAreN4hr(L}0VekR)Z
z4;r6~YJA{nk0_a{nO=xWDWcLV@}^wLOVRvrV80UOynw+zQSUi4_KT8~KyeYLt-@5g
ziYL>eGew-(3%yivuK}2+#qCkx&WK&cLLp7Or~SYBKXJefz+{LwJV9%wc<?0bW{FqQ
z&$UYYiWX?q;<9T{tP%fN0?8}ld6z&M#d%bP(Ioz|5|W+b1N%X4i@z73a8K;K3?g0P
ztaqX3DOp36SzeNzR4BYxGM2VPzW6T=sQ$rEl1$aD{#d_ZOaT)8Sa=#C(f$aHvy$ty
z3Cfo2Y68iTn9)Vgm24@2{yB+)YC-ZOwu@mRUlNcCQXp|Fgxx~Pbn^Ft<oXDBSR}dc
zipF9|TLKJSloZid7fK|S_2@H|N-`e7Zkgn}Ww2W=;V53;Y-TtD>=rX6t*LIAeRdS2
z)$D&CLch&y*f8j~o4rfZ-C@>$3kscPhS7Aj%s%LWhcC>&V9_^dHhL#8UCe*ag1W2u
z&a3dk%{-1WTR!G5Xh^;$^GJWR`k8CUQ-AYrTDAq6Pxu6L8Dt(zHDvqDuM~m{HV?W5
zm=N;-dLJJ!A94-cLGwk&z=fHA{|`vG`TQ0%9x;!kQ%*7FpHXZq&HPi^7p9v}-w2Xn
zzLSa=GtHSynqPBMJr!@}nBSU=&Rp{?6X4r9^N=a<8_IO9Dc{`N0bGgsaaxO&n*UBe
zhca{j-B2hufBFR)E6kJc0;SS?1pVJ|m(3%;!|3bG9XYsNZ=Ooa+8gE-<?!jI`NXp@
z-)R2fRH!$Z&oR-uxY<0Liceb1{eytrYCe%-)NSU!B%!gxJpXgRbeiYU6XuTj52v7T
z*F2>ZB3<ThvOyl0_fP`!q4_7Y@OWh2D!>aji*>)k`$HCcpF=Oy!cc?8!xpytU_Q*E
ztrVEy788tAk#@wQJ{&MdEe=!4G{WLl2Sg(+R&IezjKycyfgNkXQWeHAi)R&RJZ`ZH
zuXRbh1%jV=pj#xo50nIp<9EO%S}dFc$&(g}SwKm*m^&6;WLR{}1$350B)y}~TD0c@
zGuy(}n|^;e7D@^(pR+hjFW@|j4^E&n-(uw704=b{(qN(rEq-xE;{}VgbwDe!*i0*=
zVv8yN1KLH4_h|H`7BONdlv&Jq3Y2n-<ca9JWD!ecrIi+O6#2buacT{?dlr?n%j>dO
zffzo{KU;hrhS5K?;4*0TEcVj3=^k4s=vCKk@m?tupIXFJK=HZ77J7*FSnQ?<(i;mm
zdPfafc$PrjMcOTaq^tCob8yB@>QAvtcj<IFP&}lIx5KsFQkEXNd!)0Uqt8=XGY@(u
zFX<B<Mi?k9p=$ad>EJ_P@0a#9K`~gGvjpUTl%X`iLFwn;LNQtTY8x!2NY7J}<+PO1
zpzn+{{3oELNw0c<OP8)`0?Cki(@Q*48ZsMPmQ;2VGjmqzd>)e7(ytyvJ;x+f(Az&(
z+LQ-!PCBd`?&nFj(+($J`tLu`FOc>RK%-Dv!NHmH(sy#{Qb^yXon(<ThE}k}(!lY+
zz9^j&j=mCUD#dC`rI{29ER)V%1<7)$j_$__smmOYOVS^xNZ_*6wEj9|s-)k%#;~iU
z^~d39ja2hB%wLiIMgM(HtyD%OG*_jzDo9?F2GcEYUE0$IQZJP*f#eP8-YJ-po6_Ew
zu-hPwqS}f^X~sVI+a!JC2=mR-Z|KBUi`0_tgj>>k>CkJHR+-$<+9tid9j)!s`4+eo
z9n!!#Af3{Vb{M=ZwQYf=JJLUB0eDv$O$(xXQrQnM5hQCJfNT3?K_5cluq>z)pkcC1
zS{H@O`sg6<5!r)YkO-OoM1V!gT4>)8E#rO#iIKgMnV=Xe`;uz)j>&dzMQfbQb0%Qo
zWd%cleL_~S4kSVL`R@QdDf`wIeMz!;e*!I8CT;<CwrpbuT+5L)eF&e<$pWdoG*4Fl
z2QV+nHeUy3mF%T2xN6yZv|+E2F)<kR71;tS`jShnER1T+ugYSQfObumeHxwDWot_?
z>^hlcEbP|H@Jqxz$pUYJw99O10oWmXHU(U#?0@TF@V3m0-UoMN_(fozWd7IS_C1+u
z51{dVa5|mwKsKBQ^h23s1Pncr)!>C`l025Jq~PNd*<?B)*DYh{M8i{=6`fOmCi|TV
zd7jH|1OmH9_7=U<du5j?*ZETRGu6JllKn=@!9Lj^ML_A7ja~`zTK0;5%mcD;FK};U
zfBy+?P<EO&11^@kt>BugW&TJIlbhuLZ9Cj8SFHu>Vd+O7&)jV}>NqB9kL5aA!FgI9
zjfVT)mXH5i@LIm1&8DwqH0`?lE#KP$F2Hh&9Igdg79B=okY#HEQ1)3~pkLE|%ZS<F
zf-Se~g1<*B|3cV7a@2ANMSLSnmTpHtBQ5RdX&Y@>(FQKY@(^A7SWCYJ;94z*w!-~h
z%Wf(tb+Ib{6_T!2r4cabW)+r5-dh#7L&U?XgHi~)t@39<Z?BaP?Z&*V+<$?GK30FO
z0H&{%g*znut^TwIN`RGV)_4pw$g0{3F#D`}4?*UD)e<`6b<oOTBKi(ljb9J<L#^!S
zu@z=Dav8A0t>(;wr6X3|W6^ii>ee_YL|Sd2MOu_qtp)U=t>#VwW{g!vFU%jay8Hzi
zk6XRJ10r!&8I%BxxBA^Q3iPzqOL|(Lv6@)~^J!Mm6yQ&{Dx;TMhSlc|P|UPyng_`&
zt5HutvaRyym!4zQPszeOEBzGc6<7_&hDK6owPZc))>su&mG>2^<F=5jwYt9$eOIj#
zsbcn;)rS88<+|0%FX{bPXEizw`nRku&?3Cm>eDWCwps1k3ek3}kErIm(@MVz1HEU}
zS_jf)^^`W0_pMeX!TbZOnEeoWY~@2siYHdjKS5u&mHKT=@KdXU!!VW?Rwvhh^jdvq
z0m+wE`uBkH%1S7s_;a6Cb_y)@TTQWn7q6}EKZ5xIE3bu^5<lyU%R&6D?H@otz<Ogp
zNT9X<6f_1|N4J3Nvu@6X-hS(;wDStK-bKHP5NnphBpk5bI09e?ttS>h?~wKHbeDu$
zZ=fB_Ve80L`u&Ajo6Uh}xV6z4z8$sx`VK@Rth3$%iL@@F+LtKngS5wsw%&9Bk}=jN
z@-f0#>zj2T$E{Q7&|jSO3i^%2TTi2i{t0V;H5wDGzg~!ep0u7w3!+ojUsDn~$@-hg
zAj#ID7tm-*vA#bPY^wF84>5|<)`=6Kc*a`u3U<@1Z+1dI!+Jy<h?h-SA;?~vQHvqz
zZIdz_KJBx)z7=*4+uR$AF@@Qvs3<<%W;ku5kJ#{^Lm|TE=x#U~X)}kiqER;MFT+B#
z&1lM5#F%XOD4376k=uZrvT?lvr_yb{bOOn+iK3#>Oq<*Ez{s*0@g86*Y<wupdC6uv
ztr#n94pSiEn$1IcH(s~dOkY2#vw8SFNWD!LExm5oY~>+x(`I!HxCR^BP<YsAGph@j
zO*W=!RNUTd^Vv0AycU}|U&4!9HeQ<`+G^vo0PeThtojY4!={TioSinq7D42;jUopy
zcWm}k6#TBuhEOOxwXvii{4<;G2J}6*dF}^Cdu)UOD7>)Anhmbk<~tUHcxe+%Kf_lx
zUz)UN?Xzi1f?~hT%TLkz+QyYa4g)s#cfqwcHaUIZT;%C*K@s2QqDl)l`6ha)y2~@D
z`q4vviQd<{<-OzJ#U6RmW^kVJ#Ty~%C2vqceXrcA4hr7#E5D-ANA5WX^Xn_ODy68H
zpWOWxM(8hJMv0IB`HC<!2Fe|Hpasc2d(gK}ekTHr`{jx8n6?o4&i~d$a??K$IVhh>
zRbPkXsm&mva!1Mm9G0J}!_0)qhrI$9F8|0H29L;xw!{2U`D99$MaqM#sQxHQp0^A#
z(eiQ%&BVwj6r(d%{=+PY9+T&cgW_?yv>GH%J}n+5PRKu@7hi(Bm-efP^28aKgp=}*
zC|7byzWz8+lH@J_y`klsrof97`PoQdrpn(v0Fl#jciP~dk+axN;Y+&mHMcOP47ub9
zL^I_*6wS$!FWU~#v+^+d-Dk^PK7{!kc|!;s&6PXQV(XmzuM2SIqI~-^pq0o^ErLR+
zd<HGh%j6f*fO$pE`az^to=9bFSLL0n(0EO5kp-~p^1YO`Hr2^r=fiHjynr68H{>5@
zLF1-ePvN-+c?eY;HOiY8!C;g8=Oburmft%Iv=(_cElO|6k5i3NtK5f5quS*s{y}4h
z{MT)8yHh^w4f<}&7wv|^9XTh5$X$8o8IXJO=K+xHGRaHmp?zPjqB8mi^5v7E@lfud
zL*pa4VF(%@%lCLd<B5FTO*r#RK8*r|&*iVn(AOiMejW-h<eM&m^va)jK;)(TQ(7^;
zk`JfS#6EdsEEHUAgSVm4&DQMzhU;z{9)RI`*qU~2!kG5h4g><t)7GgGoR{r8w36Cu
z`}_~OXKjmJ(C1^ji(c)%wnguv(a&}g6<Yb*mY#v#0NcOmI7y(bF%~4q_V`>_insg5
z27^ej`_vqmC+%itLodlL!U4{t*u^@-!fCrRrW|Ob*?H2AFT<{HG%RJ?%~wG5x?T5K
z=(pLmO+sJ0-TF9i9d_53gX^?2(iORFm+~&u@7VRy+ojv?(Ox+7)b97ukbGgMrDVlR
zyWy1nePtJ63DRfBDKJ6(c1vh`@!Ib3$F%+&uoEYv^^Kk7_pm!?XGj8?i=u+Ev95~H
z6)@<gn5BfiyW+Q5FzBl=KLBh$Mce0q2~$WY))}tY6^vmYRSeJ*JVLSLHbf#7Azy)u
zQmlU;k}-<?6KE0?f7L)CSuqex_3vjD+f!gZTk+OUFqoqV84a0Y#Z`JDUR1>Gr@LD*
zp#%D*iV}*6mnmjV1Swbinh3oL#Ux5uUQ*nmYf!1s{|UR76~F!hQl;pnV$o{FlJgi+
zjp8#3=r$-WEP$hp3J$RulcY(}u^E<{6$?F}(W02*5AK$tr50YaD)y`gX;b|17D&6|
zgXd7}P)zE_m^u}+?tr_k@TcnXJBrI{sNYqbqr}fWMgD78>QZFZL+`$#^E+@46mP~t
z<e{R4iUb}h-uez#%k)?=!y2tm6v6wU*sU157-M>>h-ku?o+&O;<np;<>s-L}C<^Iq
z`a&^{iWz$q<+TubsTjD7zE_Ho*CE-b80QVHU%}?U#A}6z4H^d&x*ag@!Y!x3yDN9>
z6{f_ED|`tscN3TLHbgzRpK2fz!cC|E_5p7AY+xVa@~D6|l<TItnsBbb4vI&(v`91_
z<$hcQe<Qg5UGP4VYp(_u#T}-iifC@jak|>vA_{=Sa?1{ZJI48ci+MWE9UBJqIIfNg
zV&XYdSQlDPaH9E;N#Keb!6kBKgYe=ccYu;$r?`<6!%pH>QO#;Hw;>afDO{8o*r{Bg
z2r#F)DGGRhhU=x${xt5O3sBOzh-u(5xKXt2&E%438JWdBN`vHC?!bF!%;rK(sbF(B
z_X%KgxiwT9b&fkm3)ejErybD9=XN&0L;<(=XY>_v>nVYAo(rQ$`UTD-AL>P18|}l2
zxs4S5xyUt8=&yvkPtopD&Vg1?Wn2a2G0VAyFEEx0ZgViWOI+JqCUjPEWew1{%;_&f
zql(khv4LuCA-&vcxGF1%Ug1JMhe$2=nnH(Hx$-8MzsA|pd-FQiY=g!+ZodQ~_1vjl
zP`|;I{}1FQ_fIOu(!hyBFu+Exgi;DkT;dT(Hgj*M(Dw&gxE)0p;Vq7#NNp?Es0L^o
zr={~N?VKe=wmP_gA#kme%dkP;ZH}D^gLk+sw1c|K?WscJJ+A2<40dss&R|IQxeF9T
zdcZx1hocWU@mw@M;)*IUq{kdz4`-fm^>~e$B;8yIU4y4wF(vPwaajVm=bYKMFww)!
zrH^~O;4(JBnO?5pGC*H)w&k$&iu3XT>Ejkq7^a__wic4Fxs5+UeSkZc2gx^FQUb<1
z$bA?Abr-&VEQl+wpN~d2zKhDlOz!+eS~q*}(-wl=%@>!!;XV9p7jT~Z2UH8<#qYWb
z(7pV*a`@!UKiPslAATL3Xz=A5Zo-luZ%!2e{`@XVA_ws9Zs-f-pVY!q5O4M0Zjk@@
zfADZWze5UtgL&<L2gXdi{12Eo!0)CyuY-ID#VQZ+y>x;<l+WFZ`8v$c^@WKrK8eyx
z;ryZ>VCe{7odmt3yeHL#M(`IG!%`$)RD-cZ@z!+gCYoPhfHN`tY+8ZE^2@>?a*X%&
zg%`(ppP!%?$D6F^<VZa4as+56cojwW6Zl!QS4-q)odh|_2hz-*;)kl>MG`+a0-(wK
z;U1Vs;hk2aF_mBR2qLHXe0r{*;op3P5vK89{P#2Df1y`S2H!_<@k~DVFch+QFZ%yn
z&hiILR1=cTZ>AZ_;rE5Xd@lc^Gq`j7Ka-)6$G`O}xO{&9T95+1eI*nM`Dv>md7eM}
zDdy<{|Jf=Gt%!H(huvcS&I@oC`QJ@YDB&+tHEk(B(H^9XKR_YFa()cu=qmV<qbAJd
zC4L+oBB<nlq>}T?{3D7WR`J^sfmY3bl7NBM@FM!%U*UOLlGpN=KY(jjd5d0{zsBET
zK(6y&{12p#?<@vbJwMYG<OcuUd04v18%LwBfsY>qN+W-z3x=BbMd|eYoo2q*6P8-|
zbrm4DcuR9=wDMcN1J}l9E&)tCUmFbl4t^9RE;{*aTJ_)Nd%r{99bO0p=w1GkbLhLr
zca4Hx7eA{9jraM!27o=_9bTgEA>T~LS03@!jTrS~{u_k)k^kezI$^xs{98*gw5Pn9
z0+`SE)<!5k=cRN|yoc|nI+GWCoF0Dn@_%zsc*)z-e(DuJjP9#GzWN(n`+olFSCD+o
zzxxLo2lzi6Vek$AofpU;|L8RIT!f#kfZ{6bl)#?JO-RZ@tGn=w%3?i)c@l{37T)uN
z%pRd29DSZb7_Fkcgq^p6y;tz2+uB>;D2?bNY!zW>zQTwvFeX1?)?}dg3kwx6A0Tws
zLm^Nwxu7vf*kcXMeF8rM3j2lCQ~(=n5~3)q5h9e9L*{^>pis?0Vb2SYL&8Y<1VyOu
zOFa}13-gK~878c!U3a+fjt}~d2<{XdIVEJ!*`p*uMS+)OVHB;4QiQP-Cr%ZfQB3Ew
zAfn&M8DRnKw$p@dv_?!9Odrs4GDFzz1Wz-CFY@7Amhd<2yv_>asJuH{SU@!>Il?<7
z0L>MA3!r#TSo91Ec|t5j7xM*{O1BFHZ#O6u3KOVI`n+%@4I&qWxL|Na!q8f9#e$Ja
zY%dDqXh~fnNKBNNFBKmD1Q*MMM5+`n7Y5&ji3(vfZTv0?OBX`1QdsgcU@i-%=EG8z
z(Bc9|s|9a*oz)0SR>8F^g8V4BT46L*a$Xfa+Xze7geJNo*M$ukfUXl-X%|^9XqQ6a
zhM-EO_uoxn!7;Qp2m$9Y>_$OHk@O~^>myid7P?u8wg@|@ME91k*%PEySQ-oyZGs2g
z9_@nr3b@uGRQ?ZOox<wRAaYyyWF@#e!mCRd*<E4iPXN0o9HMVAbP10rWN}{@(M$2q
z2SSws1|JF=UV=OlKBi*v$HIwB$UG62zKt<;3(t)JeJW%Wf_o;^_`vRSA%n)-BWz0t
z_d;-53B6t+o9h2w3ZgME|4Num#S(o2Lp9s|!ojI%d@URp3XuW99czD+<c(1O0W1v)
zMRZEvMcGa{Tvz3bEO2hhNLp38D?i=_OCCzT8J2b{Pep^<quj9s*q+KyXz%Z(4DEo4
zy~>T06!cd9@CKMZN@TzA<4}G~H?W_waw$aomG|i#6QEo}W=(<0)hB=!r0jSOcAs)C
zU77vL7D|5vD@$IYF+@3IKYTi%Y&Z*_4l0MM!5vbbrI>E0a_Sfi=CHD17DgYY9M8hT
zaAj-*B#$Wfo`%7r%6Ha7BtqHnBSa#VXDK=nrMy1_T(n8)76^x9l-};}B37A7`><om
zcc_f;xN>;}xHx645q<H>nzhh4p<Lz&y9vrXFOWoKa3&;ADsRL>@{}?!2w+Ld9v)n>
zvZ@i5Qk0u0m71#jmflLIl@n({;f(T{BSg}armyJtkgja{5Um-?;U8m4GnGN-(U_&2
zUkSyt%8&qvW-Cuo=sriek`^Yp%7j9gKc^g|S<h1r*@nJ+Wd!Ya3zQSbqpwieK)23$
z<&Al0yr6t_5L}V6fKEphD^HuD@uG5>=`$#nDB}Y#v{GdPVV5aK#bVaWm76I=QlZ@4
ziM~t9YZ`Es%Au6<zO4M}1Nc;>oI`hawKC*6`f8LLd%#^$YRAHSt@4LCAXk;SzreyZ
z<&cTcyRN)V;i@|2KW1>IUit5Oiq_pwI?{6GrZO)FPBkdkje%&RGR6S?CZ!Y2Y_oC{
z9j$3mZf2o)OZjRzd}>w7Xpz^Z-1P(~?aH%TFtiS(sR<@JmFsDjb6ffKK8V~=s-t1y
zuJS2`eeWqBQlhd;Iq4zAU+ydOS|Rg5ImQJ2hf14^F#kw-l9mLIl|_%iJy9kGf$LVf
z&IIUF<#}3zJX6}*K;gMEiB8S+C>Mo6<b|>-8E*F~m(+uMsXXQe?v=8iDk}Sw59UFy
zUumK(&uit<QI!81P~N3tf;UQg+NKOD^A|$KMODqfMOW22TD7>Tl2qW_RsLP*^H9Zp
z1D}Fbb7;RBqB?XAeFs#9pQ7)eYQhL898zhgqc2pYqUwV%)%qYPgsYN{LF9;PJq0e0
zs$z%0tSLgZpaym$Rlb|RMyb}>LqA#-M-@IXs{78E^;ngNK#!>=TSD=;DrXm9;#5{2
zfyApiDENFrWgP>B1l8&fA(^O(wZmmPsj{SS@hR1w(J-H+dO?|r6xFe1P)JqTZU8xL
zQYqR1dPemg-Ck*`a#}W|tCmv0Hba$v4?bn8#!xUfOLd0QL}yhpioay5ex%TQj_Mh0
zU2;|5zYDwPR6qQUzC4wYKAoMf!ucNj98_+UDkxOFa~C4#Rq51tLA53T7K&7+1#*}u
zRs~X3?nRZKBg~hmUelJXR3)a0zcN*`5u)X)a$1{Ks2b=CC6`nWwgI$K_183*zpQ#q
z=BrdoD3)8TdTT#Ojp|wy8n38c{sZ+|l{FnryQ+E-335&KFCAsQuF5kt!$h5G`u7m6
zS3Re!&ka=(9c8$w+S~=wppsKkuu<jlC46d91ySvFv+C+TfVQZXyh}d^Rrx7^wyKVf
zflqBJ@l=p@)zWbQ>rlng60=jq&_3+8YHc$V?x?n&M&n)8;5@qJ@2SqG0<BA>lEcz{
zm6TEy4^*4J1$n5-uLs&Am6mpck5$<=(0`)(ND0!diqD6KPgO3#aP65&G9Q!oTopwB
z1z3-&feIsDs63}bvRAdx5gxu&-I2lWD^=$qNcO2zTj_ri>sRGyA@f?b^<AJ1sLJ&a
zeWOy*`(RL2QVqK<YBmBMx~fw@0OzKjLyJ;(^-Ma^;Gu4#(!||rH;O>)QCCt`x~KXN
z%6@vO<x~T`S3Pq#Fum24&w%NpeoSdGU$xy$s(<%WJ5buwUp<Fj<^k${diVvZ_g6wD
zNd1BWH~Z9Kt01ypeX|mM!RklHfgPg$s1@c9sC&u7gX#%&Acxc$pF<&3&5eipVfC3a
zn8Psjk3%rPaCO~>AV<{OwE#P+R?;14ico*s4UI_kyen`qN`24<FwyG3Oen^vuNH%g
zRmXHe<Cyx=_u!7J-=jcAoO*C3xOnx^q44R1`p0z;Nl-h)11wSfl7d$!)w^gfdrF;7
zYs4h=nQn+AtKa(=&?)N3H4sTPsZ-@}<Fq=l4QOZ7!msE|Qyb{1m#&Wd8TuLOzoih#
zRNHMuW0tz<8o0CS{2d_K>c1%BnWL`11if5!RSldur@m@{!94Xw%7WypyD3Xmpk7O}
zR;d2)2n?N9J4XYoSZz|JfxW1f)9brb{lR1yEK@rzhHvHSe{!K%p-!Z4G+t7-e}ukD
z^(DG3FRMFg<yWPiwFM&8>L4matx+53UcaJlp=5ro+RFodSJfH$(7UGod>Z_{uAW3O
zk~;O&Wk9J{uQ&Ce^@duSiEDpTJvI=7X;9}*f=rXTl0H<_tiJUImRi*DZ{YAPbuksU
zx2jKN0lQ5t(CM3YbwxP_(V?EFg%_RbQ6qtQTfLlW@$RUr8E|*iT1r;kQ}3d@QkQ!3
z$56ko&fG}r&j;$7(;yGk|N8}^kJQ6n!u(@(vl(QbsM!iMK2^`60~OEIVk(|^u1<Rg
zuJx$LPK4eIwFSj%d)4MOXnd(2O&8{s`diwb^r;iv!1b&B=zRKXwIywk2h^@VK<|xu
zY9rNu4yr#Mgs6*V<}|>#Y6fWa;HI(Y1aa4NuYeaGn(9ly-mOWb!oWS6@h2hasrfe_
zB3>FXt;P3hMvn)Iw`NBG8htdrbUxNsGl~+rewt16|3Ua`u3tf4fadIf+ak^AT>AcM
zkmjSuXx*n7OY4mNn#H5wVz9=8ma!ok`+E3&K=Zo@<_~Jb(_!L}=F1{*p_+UD9p2GI
zn}Z9}{PhIt;hIUw@b`$ue=4rzQOyQQvPEc$d%;C&nrNpOrE!@7E?RT!Gq`Pv(F}YK
zHdZs_2H0boV>G7Yngj_%<1`~!OjNvP(-GJ`p&2p(T!Q8rRRJVwCcc2BlbYC_7}_a~
ztr<v?CRu{MWQ{dmJ(3j7#89B5YJQ6aIjwP}(@keIzf6X|X__IQflD`O{`v-NhUO7f
z_+)CDkAY-iOz`Qf=1)4Tk*)Cy!Cd5M5;B0DtI3Xr-E*3g6cftR+~+XDe9ePxXe`hK
z(i*-{^XMY5&uc;=FnJd=oGUC8X;xCLaj|B4I{GeZj_W~6G^TASkSW!K?ZxQJG*6Gi
zZn@^;0C-WMIdcx?FKM351y`vVx&tDYHRUO=RHfM-3%zPhnFADRG;@x?nJb#;?EtOS
z1k=O%s>VtJgV!|2DMWK!)8-1vI?WH?qpx1$PF2%4G(VWAhWe&vNF`(%H1B*3u2HjN
z4n&(Yxs;D?)^t#$wMDZ_2gO^O#dKj?HNTIBWSeI1Lo~K)YH3N(p*i{v%y();!!Zfn
zn*40|^i*Rw28CyunP0$}=bC4Kf%Ir*(6jS}X4G^OXs>1jtvFw5hSL7;mF8kSxIWF`
zZS?hP&QitaYmGM*><nn?Xjk?|Qx^l6Q}!cekW8`<%z;RX{lgD2h|~7h>3%$8zd8h7
zq}l&37mexmd;HLtVgGJ5)U)jSXd#wuUv-MspE>sL{0o_L_I;Ef%CmR>1ETr%hoy8y
z?Y-zFQ)u7uH_*=8`_bXO3-)7=p|QyR6RLJ9w*UQesF&D>MAMbD7p1_NGW%O}l)S>e
z@pC9#vR_AsLn`g}zKzDq_V0~@LY4hQM9@u=YWt-WGO4kb=AiS6z12{_)Y^YdE8VO1
zhbZBA%|5Ca+;#hB8u(pj{~6^=>g@~vhrS#3Pbe39(|%4dOf=X#(#$s6Pu_$<G}%Ac
z1j%OmziFM`VsBc4##{CV9zJ#2d;7sr(_Q=2MquBwceaCQmpzjU^Y`tGDCGaZURs4~
z_|RUX1bJlN9RQ8T_G6YovfJK~o`Fy8eLbQ6%wGE?$aDLruh7_I|H&DMys%&04}W{@
z$4b%o(tf-fU0(Z}58+IoeP}Yg=r`GK@dx|ben%-x4A{q0fy5j86&xA|?N>|!jEh#F
zQZ-j?kpueNv|)Q-$z6Md;wT>4dU}oS){34&WRF(-4?sP&Yp0^mOFMxwc6+s-3K)yG
zcJvik@X?0uL!+;DF(udhwCm#*fck55XhjsDeSIB@f!e!zfbP@ID?{Uc?PdB_N3b@V
zQVk*6f|W3FKzq0aH_Jio4sVDY(x%XBB~*LwDl8q=&ZJVlFzw&V0T!-}Uk<$^+KmUJ
zs__5q^lX7%l-7xEk7(_mHvtx_eG!WZI;Isb!T^tJ6O_=4(~kTRa}cjRM)Ai4ZTLOt
zoz#9tkBd`UGfM0vYsJ5Tq-dT0g-EJ)dj<@h)_y=>XSA8L_fFGhT!DoQ?NyqeOzj=h
zT6AV<7t7IkR{M@OyvWv`S_9A=ZK6L0k*hsD4lw7me+Glg)BZz0=6tQ~H8d7zciE${
zP+LUdi1XTKa{zWhJLCWyEz<5kjK*T^pK1)^qE^+1z7p-nwDu^~o?i=;GHt(tUKthI
zWp6+(X>U`ity24w2)<p`rc-RQN;^RJTDA5Whe@c>mRv_;pY~K7&^#SX6rA7dFq>kN
z-VRDP^c{5AOtl(^9i$EL;)ufy3RXutbiW7n7>DMsAQ|rvL!ZMq;V}6soi|HxU}!&+
z=<tadES+?4aD~h%2lwybMUsODy=api;#bnlI;7?SCe`7E2d3+^!=*1EdB#CZnUyq$
zRa9G+?r>o=%x602mq9PfA(@__=N-K0AkhVfP;2N_IrLHCSGB{PCW`mqO#dp_z2dNN
z8f0o6B7TK4R~;&6VQAMJW>aMMy2C&8GOTm3O@MyA!>_->#0`gQ1#sr3Ll|Hr4Gz)&
z0JPEJe;+`v$zfS1^qL(KqtV#nARPw1TMi??gHNpv5flV!bNJ;a^qD#wzM>OMoeuMJ
zfadP_^F55o!;z)8{%%K`O;Ft9xRB28ggbi7hT;)N^$BoC9b;(m9^oiZ`Y_V*uL<Cy
z9Ebmx*LD1wHpa1zo%G^3?&x_QD9Mig8dyki-1Zd1O?CWPj=s|-$C916PG=lvQv@Q-
zvHl{sbjP8z)XQ)T@rR{+$1d6}6gZZ9ps&#Jm?KDqqf0)}E;+_80;zP|Sp$*Fj+T@+
zuXdb8Ikqc~Pi!Dr>-YsdC7T_`?T3dgj#hcVyyf@~B@9{}O|>gwsogPe8DKgb5#qp8
z%Q1wq=`S4rM+ZfF9Y4K^DS7F*;2&I{SB~{VK>8iOqypyGj$_@?H{iJ02HYFR{vA+v
z(T$*phpX<ZQb@Y#3^U<{yKc}6eIB}NYe07Enwv5DJ-TZq%BFki(rGEOS65jN;;rl3
zj=}io#=Zl;eRbm+0OO}KQAX5X_iPfl0Nol|#|7z5heCayPE8dU`*pTdcp0qwj5Y)z
zI#i0_!KC}+V@Mv<t=D0^hjbagqwlb;ks`ujI@3JL_aD)PN2Bwo&f;^x9M>)S7oBms
zI$DyS(5dN$NYJet3UX2xt;Rr;bPR2UlXXw2kUvHDoQf?{b>r5-;A!1wHo!ci`-z?c
zX*&CCc$ltx^ELW1bO~ocGIiU316Y>s$zT8F`*p+Y(3+#0nFG5;x<&MOF4j$~f&N8Z
zoeu7o=$_ZW!&2SUQZ$z7zNGu2T=yd_?k?%R`2}-XsrxDdeV27yA^NWCN-E%Jo$d$=
z^%mV4D&V-KE2PruR-KNvEN!~F7W)0Q>(VJe+@Z^FgMO#3m`aCl>-3udb4R!31oZFf
z{^6m2Pq$+>8oP8$scPZAuI?rzALt%#g%^QCOix&h0)O6rZh(~$v#A{P!$~3V&7E06
zzYY&3H34KdGx*=mn8`v#tqI4ra&|(-izzt-<-N>$ddYY*zH||M81MPwx6HyA9j)cl
znP@5*%V3gd)1S$3lo85e^5~{H%cO;Z%VxGxtyT{6<xYs?G9Q(KoMVPk%sh|Dq0a>7
zGmGf)UcfBPhk~h)*-uCR&oe*yfW5#ROhji9^CzX%Dwsgrt!8%^TiVQeumb&8mb=-X
zsK9m)+eb$`JlPO8D0s0^RA9T89Z&Uk-fYNK4Ah6+MPX21_M2~@;K!a!g`__l@e7~>
zSU+nFDbU2u;xXPJc6d0v*vCG4Tk@7!1p5*49%ffr$BWXp%=U<G(R}-eA`x0L3le=l
z1K0;dE8m5`VWI?u4B+@PF`*29fB7|)Hhn!N05X$i(dv21t8^eQ@~0x0U#8!Ndw&e0
zvPGvPx(Q9rK@_|9V){!lHXo*)zId0(gwWdHJQMWJ|6f!7<00sNBPx3zMh8XRQaI!y
z_C88O5bv-BbddP-?ck!!3+PZyw0Se-Ct}P`{sX*N^A?J+-I6!eLgbEo<YU->Bp>?~
z<-2?2S(hOCT3-4!MBQyqQV7Z0_7N4I1=-e8{O*wL^ex~bY{hFKdE9mz)qTX-PI(7j
z#M|zoMD+<<(O&c=*hbUBHqrLpS`7W9ZQmt;ow9Wxuq4~1J|M}qbAm8AX|^lYK+=?B
zdzDJE&)cTX09u*tJPHF=+dlmP`ZsK6z6R(`+rg87X|O$C2FXTS-?w4D$u@U6$RpeE
zcr-q?wV?gd6WdXAdam2{h!41@woa#D@R_aeM;OF&+uf9I@3B2fg|IJd-==x*HQB~F
zLFSch_hFdtvwcO6uzuTwXJ~wFdx1jM1GZvX5WlfC+=IrTt=TYOyV&*RfVkRyN%hWd
zc1QPu^R)YUJW#ys^5|0Rwd-+%p10l3UZD8cmA?fp$WGM-vd`|tZy4u(JJZc-T&`fd
z_fEoYh~1rLpvBr%(|$VM&V}CZ33iFq&`7o0GywByb|*JrggJKI_aWJ67cdTeO?Lkf
zXp7yOBOtfzqE~~o+vyA#c8A?rM_77g=l%e<j*G&YQW3t22j9b<pTf^{12j~TNI8s1
zMfg|nJ5F(ha-K<wxChWrS0rtOrCdeSeE4)h@z@Re<%(=7h^tX_kA`HuA}Ih|i((%|
z7;h_@Qy}tCF|ZtVpDR3l;7q?lA4BuRjVlM)%b8Ic%A2e9qIjbZhckU}iu;9Pw|?9s
z+D`a$cT3P0z$LH3umibOwcvs{mg+6{aZPP-W<Pg|G7G`ny(aX9aDToJy#w4Z8rngw
z`ZDwmacSjfjOD(fU;8nxum}prxw%yQ636Xtr|&JsbA2pCPjJO;fJxvw*24Wn&Zvaw
zNzUyA$SE$2mM%%$I*LptbIC_Bv=r_(MUqmvFxqRM=AI9NoZ<fMgTZueM=&HaxH8I+
zWpash=Vx)^uhDmwv-JYW=Gt!3dDk2+oOb8AoE6o#o#PhwVrY3>1MMO6xhZR5sepS*
z0rx^~O9)Jy=iDpNc!4`brMgAj;66-AHP;-8G1YPZ?f`Z(*X{v@PL6pS9zNjovjP2#
zYhQ)Ney;s{K)>cjU4x`)fSWiT`fs=m1?U{)l4wKh!k^9twlAM(0U1Aj4n-mSdArXc
z62SYM0%#zAXej!E`1)&@p#6LgIU3A=L8s?J_yP(^9^n6;1-*kj&P?D^@WWa`qWC;2
z3yS6)Bf-U(c*!8pV)^f8p!FDk;09oh^HR!>#PKs9fQ#oH2O*lkhed)*<f9T`_axsl
z7V~t9FFy|RN&JsgE0oOp-GgKbU%Uw<m7iG*%xs>q#&~o1ZS*wG<Np`}=zP9c2U5<P
zau)!mg8#M_qLuv7FQIsu_okYKI{s82+^^>+)AyNg@}Hc5egp4Hztj$1sf9D0{1#f&
z-R8|GY=4KhdIXWX{Kfqk(mj4D{rtQ53nd`;`3bdve!x#@fZjuX^F}B<;xC)bVd*h1
z`4V0{;r(L4b@LNvV@yx^ZMy*TjQ{Z|6npqNOQ7+B|Axmk=;iND0{4<P`~>ofcX<yZ
z?BjPmfusGrd^=rVzKG6s4Df@+7{nVssskv4eEo1hy9oA+q30^xkD~pLoA7HsK;4DM
zbnAKuMFr^e6KZJV?=Ku4glhr9S2>Uj6wc{^wolki3HJTM&KCd;7G@2Fqang{1MEf%
zKT-fJMyMi@SYcT)xMRZVhmbrjTs{QMIH6_|xOn0FNZS9L5Oj2uH$g}^3HK9)(}Czb
zDOkpXoD$M%;Y^ZH)dAO%h55AEO%W#Gy@*1FbrBFbBUI3T!ILJW-UgR0^w5hoL%4ku
zT&CdhUyNEvr;PkrVJ5vBvxToHl$j%Jy-e|rTwxofUQxji1uyc18B|k}FU+SaS|I#5
z1H&#9hEpNzdEx$0T%RhzFBImhg~)%=cSSgw2)$Y%U^p7D3)hu&>j(?`!95fXMPs@i
z3GE|5`h|sV=zA?(XomR#A(IZ%nBEAD3(-0#d`$5$7v&cmJatuW_!;iIDQ|VcuDdd2
z0cOTSIgSq6?N+`+%iTT7nLnY=Q<*seXkJSD4}r2*`L8F`y_HXog7Z~Qqh*kvGTH)-
z{>r+g&<jw;QMp;5@}G~;7i3bVUIg|&Wk2O7_bcyGaw%AO${Aw{QHp5Men9zK2)Kht
zi39YI(v7x#p~~m;(0Ew6lFm?sDW$>iK3;h$42>t0W#6JPL0R}SxI|?SJ>*X+-RYAW
zNQsYzda`m=F3hGVO`p8Lm{OH-v?V>Qw7U#1&M03|?P;2F9~E&%e*E+&jPUfwP21qi
znU5<g0OK{PXE99FkKQVSiPq5v&I4s&+zX0EycxG94vqW9&tD00X#4_tT!oH5VF&22
z@%NJemNwqD1LljyPcYd-rg;1hb0KqSyc7M>?~EVy4bb8z4AfY{Rs321CIEl`ZR!O2
zhBiu<{4?AVUTnN~2Y)-sYN5R4&p_aB{q71>T^PeSz`8OOjo{pvUm_vk&G-!kiVySl
zWq9Dn+@#fLh>6in0mcF50ezO^C?n8QJc3DoNh4>Z^dgRD^c3Yg!PqrHF@gDW6{aeY
zne!Py&oE=?RC*fYPPaxb)3O@eImU^8<$26!b<oRa4p0e28FPe^)aA^+dSF&C?>EE3
zCB}5|JUXv4#Up`M$8Z*yfO_VZCrsR6E_tJ|l}V>uP8(BCImvcLT@3vWX4e>uu#<7y
z4ba=nAf@W=FiShocb91#fZcn{%Xsv4Gl!qU!c*n|{q&zP(<$)toEdip>OD+|Ndb0%
zc}CB_H_T}|IXlRVPJ|aO>{WU#yRt6y;B;e+&d_&fM^m+-2m1%X>}D$q!0llhXm9Gt
zo<9QfUhKePVDDu!y)Z&=_IrA!`mkH3L(-RRqST}xJMBLF^=Catn?M6t^AM0gR{b_i
z1hLh~!(%HT(2`+4yORf6Fgrjw`Ve-DIYbVy0aQ0|kab*-zC-NvB`^`nZkz%~53?7P
z5D8=R_rs@f_6IsUc7$C+;isdl`6%ceXK|777-U}*P`o#p{oybMlfn+ATQil7q{_|H
z?41}iX0vx``<uf)x<}WSy+0k;=h*gju$#wTr9l2gcI_(km9Sg<Az8|1QoO5-Z8t!@
zoGqIV*DBZ+Cn#KE^OFGG!0H}CuaR{^vI_O)?D6GLY-UG)55-n?{Cy~PuuCRGqm#Av
zh5l_e?h}mS4(t5`U0?R^FW~+?_Bj=IcCn>4=)2GQQ>xEJ6y^*CPtiyYBL1Q&LtrpO
z<n%2X!$lJZVK+up_B$*jiar^MM$<`=`Ek%wqT=`9MUv<QZ7P#RBaN8+6jAk4H0FwS
zx4^_X(eXZbm?s)F40iKHOR3PcK-8>3U!kbn7UnOAKBIR*ktmX)6vd)kx>^@SS1B7<
zBKm#<pi4y+H=%x2w5tkUG?+xIhXSTelpKi8d!k)>v_27~mq4Re<Vz8`H=@@|p|MB2
zHvsN?imPcg;w64Y6%~8M8|fImxA;@qr~8Q0dHCxqJ~R{DA+Za6@+MSVK+lcC;tAbA
z2@|{0fr)T&45g5ch)v68L*}SBe+}G^6z9+*B1*i!7BJD`CMt`L5!XHgi4|*hq3@XZ
zfDPS3;z>s6ofdy&3xCgwTd6dsKzwZ~d@2#|h=lrOvFAI$ye3W>4NHyU02T`EVwXNN
z-WLa1Lgaz?sObhY9*Se{gMB1EMZ2!Y;${ECu%C#_8F<<)p7$>_o{Fa|fc_it#Ch;y
zP<-tbBwZxN!*I=2a*hgB-S7ogxaKaYKMn;C{LiVt+%55s!{|NnpRS?L3m=|<<X*{l
zF#z+HOdCq;4<DQ{hK8@?U0U$?NtRNO#$QrE2dfWCTHGOWNa8`qYeFS=BLH()@(cMJ
zCJ|A}AY8I@8^{sK;wVT)NV2UV8HxYG5GYZSweA>TwB#o`a}y)Ub%Haol0U70a!e9f
zNBPbq$>yt&NtTSD1y71(+1Kbyl`NG2?KF<ngPf6kN+Inu$*UB=q)XON{dT5g`glx2
zmgGy?SDuyhQhq60;(7~qb0jR?0=beCUI05MdFMAY=1CT91WJhn=Yeq}N_tUeZo-!?
zBn^-$m+aXMQX%>4SCC7Rk+is|lzesrpqC|4zu_8IN$fs@evO2uh|3kp^7mk(R#I^u
zZeNu|P`>k;WO^RB>yqVkrm9Y|h$;l?C5`k+jvJEge*yZoWEkaJ?np*`0x;8E$&LFE
zy(cNm!eF{2w@m1~FPUu#?1z%j@1Xxk^3y(uK9+2YhsYC&8QosplJ(V)d@2d2uR;t;
zrnsTe#Vpw!j=GxFQN-2Ftiu=3?q-Ef=<_g}{5jNjn+5HIhn{9X4uPbX$?VQ!VDB~S
znF7|^tcup*K4wm10P1VjMB!gQv(vQmJ#3b12AD9j)*Nu*X127VJYu$b2DqbUGv|Vf
zFw6ZF1|!Xis9HYCY`+gYj4^XL2k2O{P&zYn%xsk&=8v0QTL`mpW~R9#(HU=c_8#W>
zgqd3)6cfx$IgmMT)-?wg_JY~+4N$yfHmU&bH=89qKx2zp2(3m2%;sN(-FWlmF+eLa
zf3g-}#pX`_Xlyk1q;kC$^HaW1?=o+o4MVs2#!TqFG~byHuvg}uCJH<4wfOBaG`uZ3
zA7O;S7RQrdKEmQ7ip!;1d_9Os$hBao_@T(6UWLX+i_ht>O}E8?Fo1eW|6YN<VClcK
zK!}zK7VsiP8bSf}bm@F0M9QRov;-}envH{=kL(T|KlGQ4o<&zXKz3dXHc&Q=HnRI<
z{~L+M{jw!g2OT1t^g9#}$gFzd_hH$g?T`$UEujwqhs#cOLFA|`I0PO>$W#t67$cib
zPtsV~eJ%8k$u3jsI9_&J2K7YQ>~-i%l8wC%^;B7?AJzMuktHocXPWG#9-SGoFAu>)
zrc8K-!DPw$=)O8DTR}hZ3fa$&AeFM+HJF5I*$ON4)ygW<VB(r=H7z>pWD892;)ZPH
zEPyr2a_A;)m3{meB5sy9DCz5A>01VFk7fJs^!xL&45Gqdf6MiHhz455rGNxmZu$iJ
z2P}s?#gv3vu8D=gaLdGQS`OlmkhK+mFFHhdqs5o0if_pPJ=vD-7=wQ=dqUx-pU=O6
z?k}4@!M~T^q?33nzRCgU%H&X3_?4s0_$t!~7UZ|7l)L=B)DeHLevj&4*St){NZ0CV
z>-t9(<phoEoiSRc!(;I8EqCd|EL$zS@o#7CbbxLjLf@&{Iq_5cd)Hwxa7+f8PFJRo
zKCtA*BpT7?&NSOY(T{1PVgY~V&JC&o2w?vD7;GRjjE*~mGULZU<}mZlBA|ycIS9c@
zk{O4s@G6t3xeK&>CiDUZRl>}qRd5yaelTtDX<81xkG~_>&DUW%k{v={0*zunqts?J
zd;1`4#jxAz;AlKsJ_C&>Sd$~&@=2_k4yGlu-{*l#VV}|wv~;#y1TKTMoeqLeX;G<l
z78|u5`sdh%0Z_<eJE-n7pLKV~^(kUs{{!>ItaTdHFS2b^DO17z=>fZ!*o!hK)UfIF
z7QMo@6~gmcR%@a~(^a<C4l*~`DO17SWL@`xYhWi)`P?n`7z3`A&3*@$qK#elA@tkX
zsv_uju!F_0dyh?{NN5*(h{`G-v+ow7@i}{ZKNNacQ4-W&u<PlD>1Vy(g`SIO)MiLN
zlaBMF^=FSP5-F+wCh!g8K+o7gCXS}Zh0UXkh%2je!${oNY41VVon4g<YaZ;ZIFQ|J
zxE1>Lu%A-c)|2g|-K!TnBoyj<*|uo(d9w>CsOiIwrLz~ltnYN#^kehr{pfFE7k9&8
z04sBZOem{+0dEhp-Dl7l#unzFFOK!N2TLc|_pkqds9SKOeemJ~OCh_&pMJbcAJBGr
zSqcMtKX0QA{4f6QaAEn?HXy8c_!yEa*HLQx*QMtGwu;#S`QP6Ekm@adpSu$ZtG}%R
z=$Z;j->=<R0)=%fg<Aet^C=+y%5a0)#-rcBn0_~9u(z~P5&72BBhc=_{7T0cb~8a#
zuDyq07SNcOGWynaAoE=n#Dkb3J2<qD(G7({7}IQqSqNuLOFH245vDL7E<`Y2Z$@i0
zvy{vnW5(Em#4}fW(3r?<rL}hwGl6O=tC*4W$gO7PAHx7@nA6p;bcLDy9Cm9N<KN)w
z8O<c9H!=Uvo~n&mLAQSw<1R*D4`Za_iautYsSz>*jCK^z2AMIFfbGhLy$hHK*2@o#
z8SDbL|KElRC$w<#EHi2>bg~)E2Dp{OTzL(^T*g*|zH>~?IFLN%tQkg?&zz(~>IIAi
z?Xk<4;Q~A;XZkKey@DyFd*c$mw@B%(N~VxnFEc+<qPL1kqhgb4rj>#M?M%lPn6eJ$
zgL&XO85t#2A2ERxuzSpGpgDfYgwxah74vZmz}(pEOnBkWKB2X|2kS^@N&MLH+d%x;
zKbOL80Gm(($wRE^>oCwz_S83++{5g&8z3?4bgGGnWuH(~`xyH*t!$375&wnwSTQ{w
zQ`oVTG&{@QZpE0g*&%0PDTh5+2=!ccGi@G<*_cK&USvO|U115ka~<rKvOkf%8g}d&
zKwn``n%;#*En7#AysPXa+SoL)w=SWxnRSUrUklr`9s0M}`q$`dWmnNTiY^w*9NP3u
zSE26#>rCOHhpgF;Adgr_Bh(+WVZ)*RgxyCeux@tub|^e$S5TJh8M~MsKhN1M+e~14
zSTCCA7wpsR@U53UbQ_+&WKA0|v{&pgT21${0oCC8*#s&sea&|L3bX-sObq&bMWfrH
za9CtZXV;=cZB%m-FB(S9q>Ao^fE0`LzoGGl$Uq^HhoTGv8ePTvHq-v|h<LmM%qNQv
zegS6+#0gZBR3(<rf&0zkU?(U(6R$LY^o#S;{{InBjZbnw>82#ilEfres9ffj<hP9&
zdb?zG7?5sDy0<{2OY(Ltj6RaMQOVL%iNOz&y^?=d!skAGZ)!N$LCG8`L_N&@ocI<7
zhCh7j72qz-rOoKiLL)kte`E=mm95_cdR24=Wd1U2#DLd#s_?gAFKrWyQ*YqkPVZBh
z>z0=jq2<E#r(-w>#n9tuFLRNqro9<w3h3-(rfxO?e?RjD#lXUt6RqIF8Q&G?jAc$z
z@Z}iukY2&3m<bEveG(%c3CU#UI|`y?GCkdJCW|Tk3D{>DO$gMpnHK|4&tW=WKp~fj
zqEf?ij4lf(d5qE-Tt2h>EpP=)Q3;)QEo4-*EI7}M8Uk{GIldIwMa*yCK);x&py$j*
zCXXU{B~0{sh?FwZf-%4{X31oba%KesQo&rMu<s=%kZz(%rv4DTxXhSSAg_vvya2sw
zrsoD4YnYL?;I1%IlwF!6H<@$6n7Rh0jOu$D89VyGSren9WpXn!?hd?YVYbCV<PP(Q
z>c#Fdf3AhdJ!Tl4!s%irQFQP=!)*Ze113QQl!pwGqx6s%M^Ath_V3jI%V2%zIg-V`
zp^KEwI#YDrl*?`mf@lG|NsrbG?1@zv%tf}2cKl^*5JGTxcehi(wThj0ACq6pez+P6
zH`!C}5NT&y_P{k4QT2K$TJc9%Mq>?U&p3e`VS}@wdX)W_fFju8=OG-)u9ybXQS5_V
zwEm1{llMR`hJCvN?!~gJ#SlHln&WMUr_PKSuoA}({|k!oZ2VO?d4g@Uhe87TLoy^2
z*+o{6Jjvc~hU6*sWfCO+ueK|X%PDRD=f3XqoRs20gAAs@7>r7xFotOoni`B{D3PZ<
zlS*Z0Vo0)Q=|=YLeQBXA4~;GRHkPbS$i5E4*owjLdol0(@B8`u-p^Z3-*aF0wcXcq
zo^$Tyx{o}v@M~)}&>b@@ZKOC(Wy+`VBT!d>_iP|yRtgK^_5VGT$@>C|=use)9-%Q~
z;P+7yC2-~#1z&^2aZ;TiagK`OVg5Yr_!xB;sM02sF4E(Dkh@AVz0uHX)SQRg*J(0O
z=G>s2qX0L_WgG-<(MaA#dz)4!K<*CBI0m0m?owh9T)anXeuSF)^cgQLKcJ^}(Dpl(
z@?H8NWx9g(5h>mS_6N0H3wTMBxqDkqy|dwO1^IAJ>MQ!f8OmN$<>w&&MQMk?`Gy{K
z0KBD5b5S>0-gZW~(&Tx*XU<BIIoBaLTaFDv3l~T~C-5wkd#<6hLhk0dot5%1CyA|>
zQM|gDEwi}eyh#T0%FAYX?>0Dh$c9q^J7qJT7CayuT|iq7O3A5Ehvd}-;5;R}e+)P+
zBY1+UShnUov@<egI^Rjp%IFKIJSWHTo~-jSKLd6z$ounQ>7uk*2`G^hI9KI2Ih^0a
zQYt(0T;U~I^Z;;K#uUTtD>9P1Yi06GDa5ZzZ%&TBCL8mY{ibZ057%zV6FjE8Elc;p
z{2kdX<!cDumkzvg^FYS@h0^bG4Zpzip^W|q<R8hn2Y@GXaX-MHa?n8Nekwgzf%A>L
zmkQnE^|~eqOwgylLfy~$17?}1U*P4KNxBD5&8F(kxoGDU{d83rO4ow}5Si)v=l8iy
zGxSPp(2ALQjUe#M(z|m?;B37(33coAvF+jMCcWEENbJzB?*!+5ea0!kas6Zgh!6A`
zqxthSHNOilrWnB-ndye*3B+d_V|Ifj)3|UMsuvl)n?TGm=1xRuv7v_Z`s)%SAQzr4
zHSX}%{^iD5M>xFF$n=4ys|_>17i_JOP3(+uC=JB*MxGf;vyDQYBF!<DU58w*aeqIW
zy}@W-1lVZgUk2nG$MC9&4-b?;3z+-8egnxs4_g=v>Tb{bt@`f`g7?9Byn}jxw=b9m
zdimjR<d!GU5Ve)(W}`jhaUN4~2Rw-rJ;9$;^%E#c-o-tIVOtgc4$nIa%7|~cX=Coa
z1^*;LbvX9o<0CLPLzqK2BBF0qXqhF(a?EF^h;BFGeTEqE7MIRKQIn^+7K!Wp4bKw$
zjsg}7KfcD7i1BxzdZTdI1#4E(H5J-+imuHdw@)19edI^PDIR~F6w6!?rgI|93Xe*K
zYXC~u#e~~%=7F%g3*rkgwi0xXr<5n$pUI$1UR_*4kEZ-9;Uu6w2(!gQ&M(Ul4m>5k
zP;|Qj*+rsBN4T6NN?QRIi?Lp?xmsLk1<o~MC_jF3MJ#Xf%@b+Jo5$nQgZqOUMXPYs
zZ4<wAL20{43`77@3dPmipzagPIHO>{82J#bJ1zqFiSeuWzAn5tFR+ah-$yaCJ+zgH
z*c_Cu3Yh>C*Tf#qHn=VZ_kfmc8qCQ#Ih1;zFA0j}Iodor&NucARPY?7jWpT=kWZs3
z0}4`T(obmGG1`~|i85OFIpmkg^Bn-o<*G>3t&sapz{E-!rNizj>EeROt(NO~Q^*>b
z(FAg9rQiwne@N#<u>4cr<dCeBh2!DxdO4q0V`k|_6V%PtZ}5;YLqAs=7Ut+F?M9-Z
zbM=53ke{c2iT;&ozMdBd-I@Au?ldU9AEzrX(Cv7Aa-kl{nevPDJH22xOSj`}fmGvE
zH*UQ#btvrS8GGxXw8<#s9{N_Ja}5Y=GwSdgV0IXn^TD#q$nFj=_89&tBf+}Y@OA|2
z3#0xbuuiur<JX(z*myaCc*rKU5T&Cw-;RP8=WHrE{M`e*N27Uo^pGMq!>=cF_Z8Tl
z)4DlusDe(k1b3Rm-4o{U&oQ724Ej9JMnwF#*2H;0GH?D!`7Xu@q;6mR2<h&B@_?_$
zxnZdI-oG}q_Z+bX!u_3iYen$La{L`o%xioDi|^t*WaVlY8&t$w$}H1*LTd0RSDgR2
zofr3$76iio<W;-}Z|ufm(8qnvN#UuYMIBU67G^x1IRDLh5!5Nd;Ne!fSj3AtIig@E
z1U3sF&gLr=)qjQ2Jz`ZS)EyM_vOvT&>HsJfk`sY03WLXtSH$$oDBTiHl~DR!<aa<z
zpNqZ+A@@eCs*1Xaw741M(y3!8dMud#MsN<q!gt@fj)+9(pLu*aOs@p`OR=6)d&|W$
zzI0xT246zyUt)1C<ll)R-oi7UhIR#UA_aT|&Pg=nC^V(f)N!yhg<4((%Un9V0gC5Q
zm_16l<Q0z6PHJ$2yV^Wic9Iq-kS@~Rnb1)}Wmlo`H!9>j%2F}~L+TQ}<k{leG@>Io
z?@-YfDBY*2C*aouI`ux8fd=#7`41}95Zwx@;SbfX$a@-`ohrAz2F#T0wn6nAIVlls
zoG05)w!!^>zFdTMedxQna&POYC>{w-&%|=>^gb7j5hUEP?B}CtFU2iyK)Hx(3*toj
zE%be}JC26U>16eS-Whb5ySekpvK!)=l*=P0MNOEvjH>Z^>2kWnz10;IoWg-xNuE5Z
zyPoFohMsIHXbp)R>arL<Z>A}K!O|95avP<cl!u1~=AAZFz|uk5@*HXok@IN8=p<#l
zL+KRt<`tUX=ww51meL&FUVe!lM}vs9wyz*}h2qztu8bD+<)!hf)Pq;QuaP6q%3Y_l
zT7Vmr8-=F*Nv8+F{8PHgJ=bSM<2fWWZz<$nkTb9KmDAD$aK57PqtUe2wB!~_6Xgv~
zWtk)=e+ri6aw0DUXG<qeVcRWR@hrgwS@446UnYzBk?>H~<T2iJS>6McZ{)OJ!J4X9
zTMlQG-p&U~vvuW%(k{K6`*kPv7q{W|4Sn4jaK6+})_`l%Omq0AHQ&^Vm&UV9pUr_!
zD^1ycXzxEwjfaD{*f`6JF-wihm~~FUr2WkR7+h{#dyUYnGuHEhShlf%r^|DUGdy{c
zXY|R1V7^gy5v8rhn||=ZYNUokV7qZJ9bWum)T;x59fognxVFoPxC?`Oj6J+>xX9>J
z72^Ah0ZtI#Z#1p}xdTQKFJ`73F%&0c|7!U7!|xM@><?#78b^6z?u>D1`QLZDE?v2k
z-t{;S&HYyMK<(Sv2IT#Z^#moLU@Cn0?ic<7cPq()X!k9DpteW(2}pf^BoF@f+=xru
z)T`Mmw7vIH_OefDGk)LZ5B;XXt-kk)VYuJDNnj0JaTY3q`g8xj{}<6v9enc^Y6s@j
zfR7<dY@ldRtNWl>+<52`x_ult!{+g1Zg^cz8Ho@)XB26}{eY;*<v5Q%#|zOh8yvtn
zctmTQ{}_;Irv;f}FY&cB#F~kUxD^W_5Z|8@#1h)xLMw-6l);t6@lSD{^r$K5Bm8^f
ze9WpgpidCRyhm_~p!U$QM^whFh*sZ0)1;PbsBA%AZQQ&Q5@KV*EXgtPaY=5ydVkl_
z!)I7%gkL9LS4%>In@@aPaztEmlACW>Y)nE@gj+)Fu&5Yts%k{ODMKt_@kySoLfl>X
z*Q13;%NA|jTe^FCc)BIW$HykQSrUi1#Kp%&xI|b&W87lm!eWPoN4P;OIwmec`~Mmb
ziyz{el<b<MoQS@1{!dP*R7n~CT|@t~jSV_A{vX@0Dia;G`D8YCT>YzK&EQ*;InvbC
z+Z5?)YU6Bb{WDj5WBtj2QX|#rSfhq2Dc9>{4l(L0=cAQ$RkqS(vbrZzA>J#}U9Ya*
zMcJBES(I%vb?1zI6&3%ulF9luoy-xccpo_`nqgNnvy*}U`PtdNvO2cY!A>>HHL9zV
z%C3>Br`y|D6aSz}C#}|9vh62oR>#Us(p;`c96AmY4g-gc)#Xa1taK%lshR5h*tSYq
zt!P_ot!TUXP1VSyMpd;u-A1?V5ufDT#KWUcQ|s;wyPtZg(Ys^^>x5f&Rf4S6j+I~g
zc6RHN6p@(Z7G_C|jZbpx6dyKh$os3ZXW!mk-I5Y4VG$w85tbotKHlA2d@PCKA>YM^
z4~vZm=@lQDJi?L~;npc4bXb%%Keckni|So_`G)-99ni<uxlN1rKYh~D$J$%d$2vSS
z)DMw1=FAeKvg&usu8Gw;(P6u*bx(mqq<^Kh?jA1go-JA^*S8LD$)1$!JBM0Eg13VW
zm0SJaIb0*s$m&W}dfKAa`g7$f$->z^EY#v@3HP+LXyMhy-NVwNm4{cGFpsd-VeX+G
zo}OOTnhsUg+S#I~rr8y0+WxcywW{E#YCTZP+}AT@2fna`E(q>78b(;!dUQ#sil)uO
zZI7yH+GR#ZO)F=trD^C&YJ|xTjEFU=r)h<Z&YE_Gu^|q79E~-tfU&8jy<}{zX^yxj
z5E8$jN~3|AR-4hJS+lyC>)DC3YI{F(cQH@d1_F+&z(DgD4#4?9a|3ZnRRo$p2hXQL
zfZvth2N=rmOf3YEqrKW2WNu7)ZFQfqy}hd59~kbS+5yF3W$DjswbfKEK34fCinpqS
zsdZ~B3I=t9Y8s4Ugp=xtBGs*@Ml<=LS^+YAJHoZS>Zm`tR<Ez>3;=#vSA7G7lQ9Fp
zbwgzU$lg^If@=JP2)Jsh^8j-La&%XA1HqZ2+y{a)Km{_CstF8})H;SY>NG=+s$iI=
zJ`Di`C_jcvYA8dFTF6kQiarqU0SrGxxJ;<Y1I-Op+d<~fO-)=it*+XFQ#E~%xslNc
z<p!F{3<X08Gem+=qFRTU8>yxiXy}N~#>M>JQ&<|sq}Yy{_KEmF>aC7|1dpCD>{m{q
zU~pI_v>_i_Cwi+GCXEK^Cr>pz9Co&YAj;J>h5%(72CK0bgchuB4S>}^l<~PtU<g<1
z07lDeLVIhg)<#0Og4x|42<;<vE*k89;b7>D9Yr04${YZOg&-hoMGU>wJ+5y0NNCAI
zc}ANX3NO_z0>NIQED>NhuF?TUBdoH8{3{AfpQuD6J}$@hs#zqsx2x|_6sy%JhQn$F
zLnn2F;hB2EkfWTUps6~>Qvd#7yQslY=EkP4L93%aLb%m-<_UU(So|HH#mY7s(ifFG
zLvs}fFf5oOm`@)9ykD*3niuLc!)8?hFg3&%zJdBI2JLCD{9-`y#h$ebY8WU~_pMqK
p1E&Y6BGkaKdkno*wZVWXsx8AdWdYQl-rcNWi_*V;a4&fO^MCj&V=Vvx

delta 129486
zcmZ6z2Ur!y7dF0o@7=rg_GU}$-NddjYU~<&josK=tg&m17Zp1e1Q8VkQ9)2ZPy_`L
z0lV1fpon4vL<KuozW0#d_dMVKpC|6@oH_4%&dlykIWw1p^ltv?-FDStuSV29E;@Ie
zWWt%c|4e1-R^VSp{EMABrvHIi>Nkp7XsWv-G-b*TxiC#tcQj4acMjwa?;kt$zpHot
z;Qr&F*G2u$)PZ#O&PB~MZFHv}?hlAeosLshP3ibo(p!OHYWL}{u3*cUx=e-ot)*v=
ze*P6IbNLjh_c`a3^1m!SE2jK2hp7`gxqNbFp|);jp~Qaw`0cx@x7^#(yJG6_{I>s>
za`LLl9cP158vKTlhxH!U8!3Z->=?FN(Y?t-Si(dWOTyG*S%h4Lf9k<STP!__yr&K>
z+H8(27Bo|fMehHWdHgObqP193cbwF#SoWAG*BMTpOe&w0S*WV}|9T<Ahw6&@jatpN
z9>;W?T0W=aoXCo|Z)2yb@;NjLb0Kz4mEK+3pYMJC#mSw_1?Cr3SEk-Ort6A-*;8q9
zdzEvUN@jjoa6ro>-eMVr`TzdMvD$sjWkx;fUp1p@TBS2eIaUyBhzzIVEX&o5dQGIr
zs5(>~MI|b}<0*mRG#vL$VAOgK9yP7{H<f7kKU%36PT(F!qonK~j#167x{XSD3Vgdv
zo~fbXX3t+jiof#EIPe3ER<X2%hS47v^|~J<MqSU^pYC^-u#CEebvo{C=SgtO<CeZU
zd)uQ(UrTlKs)u5z$?ouIW~iy_)K+G0u-BlYVP%iehT6kQ@ZfJ(O04YkG?}?md0&Om
zr^oQjUG^82VRVi3DvOF?*hlAh#;77R!<M!X8B^uGhFv^LV$7BI0(-B(<A$M*?&>)e
zW3LodVS9O$8-8Nvcr-FLX&UDtFoRUB!KT|hLUl_GM|uonM*fd9V35F!`XA{*kAIC0
zXU0;I8Cxkavix|K8CQ94W#^ZunemnPRoGU)$jk&4RlEjUWfaT&St+l@PHDt36D#lQ
zv7MkZNtFYgM(o=63^Tb>-hw^eO3h5Eyl=z${lPI)EAM|{dqaPk>bw(xPVD#$Ei=8c
zpet*b$1*c2?|ZUCpft0R^mkSrAu_Wn<wMw>(JE$k<^2e@7*Fr7%KOpmSm@8GbaXtM
z@>yi&R>~)_tU=AptGu7aPJ_<;O3qpApC>(bo9umUHF)OlO3@1T#c(aNs8ZF1{q{l4
zEUvtFW%M1^am*6cpJ-SUy_DLsrD$8>=q-_9ei+_s1cNuEzDKFa?(B{yzzDOBu@G^B
zW?&KfAA)b#RfB?bEnN>R<QY~NSx3dF1i=+=HKPu$#V~v`bqy37st7;%B2{(#$TLE7
zYI#OAs*}J7t>|8(nwBXtLR-2QRI};+7rIwe8#Be3jL?ZPM%AN8fV<GW6|Z)CWcsQG
z5PJ);CC`B|_PEH1tx17VEz%2&*pBWsDrObWh#lx&P>mhPF=8d5qKauRF=8d5QN?<c
zn5z!+9;0Q%-l||?wTk^m6YH-bYDOIRA8U9^Fb(;SHTy2C4gZfdaS_9aBk5jIHChY{
zW9Z(9FU@1LrIyom4a-QCj%idCb+wFC>6oCJ@g4V-jw!0bMI0mjS5rn^d!Wcjzp19d
zzOu=eXXF$U5&p=H;29~O&xYJwdC9{aBR0ZQ6hm-Z^K?HIBR{mzlle?agkn^+l080K
zS~M8xE;6+=S`tmeKh|d=?)iIbHITNVdzJeVzP-m_Yt@mvo3PAXwT@I9;frQ{c9N<#
zPz7mwx`!$wQma?V)^SX-y3!D7R}xp*@+-^4{Qrb?YJ0?6?M|<@8fK}wvOYxbR!QHC
z$18Y9t74X`6{1qPkI=du6OeWMmmRN7t1PYeUv`Lg_67~J;{Pg-W-QWYmKmmoXK)Gs
zSRc!pDjKHm|0}7>Kj#^b;Wo?9y1pF4t84$y65r?+k8GR&QS$>oXpkN7Uv_}DkB6tN
z*VOAjNz7nXWy_L{o0V?Y!KYE#fP+<?{%gRw{Np529Q_}9mbTEsFhf=UtJD&v{;C!N
z!{%0_Cq)0fLCX5<2Tud7M<;uYDueMQJ@{Xx=UQjr$^Hye+DRS@?Ty(6r}o<oYLy%7
zalGn3tlFbtwXP%ip&X<BK|uqeBll2=ob}K+Eu*f^bN14G_=<nf{#WG6a{t`~vO2ET
zk&n=+qgRUtPTE)<pR1zcv~78jQ42=Sp4`mie6^Nr50BT?s<43`LiL)8hnLJ~)IqF<
zt9itub@lmdfJZ>}_Us0aoa!x{GbXZ(rjlL5jXGZ)gWKr$HDrbx^JcEZaN{1UaX<d^
zC5%=R@)(iPFnDn|X3=*J*NGOWGXwLqxK4k8K8BfaffPc<V!UI{mxF*wDJT8rC8YEC
z8<oDfOV~wgs5H$vjS5tO7&@757h#JTkU-apIdr}3Pk@#4=z6k<BujVG{lc!KpP8k`
z_5E>@CvGLWR~REX=Czs(H115LqkbXDq;KTVZ}D{P+@1921`&f#w3A>()kt+(8Hsw$
zqWgQHbnn)k!0jCbvri*f!(C+lT_!o5{*lZa%O=e>-$^rg9!XmLLz>~8sXbm_q83`T
znHX;8lBPL@bY^!X$;|GY6UnoiWOC{P0^}Bxf$S!g06)5a(wwd%r;|>IFUcEsAoI(9
zC%Q}wa2&H@4UemK6J2kXkmQfrq&a&z=`>F#Csy60(w;HI)8S{5q`eUsCmOR4WrXF_
z5+ftY*gyGXVB!d>$Hi$>I-@=j)iu*~gCA+`yh-)wGlb}7wWNFZ!BhdwZPK?KCOKO~
zu5`*E{l~LOKFp2W>O`*-Gw~U8oXnc~WTt!oT@A$qi&;ST8WYhyx=w&9)ySbAOUR6|
zvJGn7C7mz6q;sXRC2mb7?3yhkX+D?gYTrx}YYb_o93zH$!^sKLDUt;KPHs7Oz9LcE
z%2#Z-AKmw8K@=Y71vutJWj*qP$?&_TL>K=P5#`I&68$Ti_tM{VA2*V&rDdcUTq*zL
zL$24VLToQhWUS5=l6c;x`vJGf#Wv2$dfcoarMctD{9_}T=^Rf)wcJT{>PafqSH5Vj
zd&w=~HeLUWBUd(5en_p$>E5L#Y4&_T_j^4^C(517aAq=m{~)o&&7smoEi2uPa8hwV
zC_VL}E@aaAoXoectal1VVl?j%A_{S*dww!qd(|eLFmJj}#e{}q8ikXNM;w)QtWWoY
zW)tV(%GdUX$|{|hN`_y$krO{oB3t3hwe<c6*CyCG6N%ysRJ`>c0{_&Hp3}B6y4Sy?
z`zDxMb4*zwnLON-?mw$Zzs(Gy?wL+<;TdTTD5mSAO2a!}l1|-qBw2-F7mu<HRr^=W
z{_+0byiPDvJ~dqxH!42Rkf`@05NQ}jQjW>f5_p^&-S4?c^1t(m^xjQs*vqAK-<>Ch
z!j&YkRW^I`EV_3`AI&jiQwTd?FKMnDNB4K$pw!8H3M7-wI?>g*nar$RMle-FGSm7U
zy%QBfN#cr`Ieec$bcyTedT$TuM;S@}K90=iS3b%Y?Wlg2UsE->wZ!nbDoGxUA<6zN
zWWL8fk~mi%Cehp-WPV>NnGBbRI{6G0zY?f)!X+}G9zxf4zmv|~KS{?cflM}jLOQ=}
zr)&F%M14&morb<-ST@joEi*alahW9NbLf8l3BsOs3X~Yi$^6<|bltO_iv8wOLxo+Z
z`#+ND4X8GVG%x=_ZnfV+q}^+gPW?(99#bKX8T^Ul0o};Cl?$l!UI1Nd+#u)7D$?nm
zP7HrOr+aH6o<GM#*C*JQ<y5~JH>tqXhyc|MWOA`<r9*W{XI(wI8oN{J&0bX3)qfCb
z-b|8*HY2PPvq+BFF_0wR{-i5kMm#zD=>9g=gdEdg6lu;&RMGqYq7(U8r<{nq+mo@k
zSaNbq#vTGRo=A;W^G7l{b46v7I*IQ4aU#0hiHI^PB_H|{_Rw`IT^U4JX(^$0*CF}W
z6U3k0j;^;A(is=T()%C(J7s<hC)LI6iSBJ4nNPKns^>5w$|)sz=hbwLt{hV1hf^(Y
zSCA7?6RAnHuL;HeO!{q}5;oa~IM<&f$@Os3&xxU`e#459W0s$VT_;oBlL}USA)=wr
z$iU$51e^UUk@lQL0Ddt6e8-ZbU%HY0FDFUA-UhnASvfA~D|>=Y)5wX**NI1}oQ6D^
zPCQ;JYPs_9g!*>@Nj!HF*7*rbeAM-KDrj<!uEo`<;9=#^(#@r^#vRFtLl@|}#ElFX
z&XT;};K~{=rurFN2zzS{$wMa-L+)&1?pfKbZN+3z%Oq7H$&~hVzs9J+HO;v|K=M1D
znU)zFLVo?VTaEkZlM=3eCLY(zL#W=;UTT%2yGeg;8#1sYiwrk7L55enP(dD&TUpBt
za>C^kVSg+o&Oysbv#^Nn8ye~AuO`jQw#pah7feAhr~Hd*)89d=`zy%6IxL2@%<xA9
z==+ikc>O|}i^r3TLkE)6@0yaM<2#e)oITV+b&K&XF!{fb&Kf_uex5{+Z%i!l+ou!%
z+p6UB!*yyWiVrQI0)H&&(9u?<>lVyvw9KWaq?(7f8qVD#(t!SCvf4o+O-LY<?y2O~
z*fvz-EtT)VmBU0mXB@RzYUMkh=|Ro@E<~mRhO7F+Ow_%>dQ9KBCQkpkXx1LHRw6Uv
z`61Nw590?EkF2&H_oJ%20XjN-1pFVPt^wD^zFdU+scY5&HPb?a%))x~gqP>h6w|r9
zCM4_GS>0jXjeU0si5I5+5bkCDUc*Um_Vy*@_OVr$BiYY7I}`$UfNe4cMt#{<uVD2c
zThJCY_hSPN1Mkl&y<qqdo0$&H0QSm6xO$i!PD8~Jc7O=sQPzDDgn?|!bubacdeN|V
zj6FOMWWnshR-g`Hzw`p&I2*STo}XX~pMg4*?dzm&JB*cLfe&Y=#6o(KE%^bt2=*yj
zn2TgPZv*}mdssr*Y1V%yxTDyz$FO^b-A|LWXm$tn&@rrT7s$@C)3FHW&aqN5%*V3X
zfq=)cu^|wiXV+2p8qc~NfHN1^&lOJ4B(NRO6LA;W>xcqyiR|A#FrUP}q!;@x+fqi^
zJ@#k^*iB`Rjz?psvC&@OPG@H)0Fc4zF2K=jw*6>u=dhtkz~!<j)UDlTt2IONhz%`)
z!2<TQ2`o?9LE8X$&TjjINB{eR{m>Q-{F41M0KgLV?+S3gW|zMN+Z%Re1?p7FPM!r}
z8T<7!lDBOA0@!`WM#ZA+J=?Yygdf=1!vXln{_z^QPi#s9I9kp&FN47fcG!E=^9#Ez
z7G>XAKYF}tRlb-;Ik|PJKD*)KHr0{u671vu2FIuuY4fQMF!Qg_RA_-M3YHdL=nu1h
z&zXn&MTfg!(MZ~L<}`su^X-dJ!4{G)t}P?lLEfrHEf{Ovp2jDCc0=_4$Tgelqq5po
zH0$Q?)pUYUh&Ta}n8RVUN{qEv(WupEO<#P3>)CH#LEy?JqmS2aW*^0&T3c8hrfk}+
z>?l3dx3TN$;^REXzN7i8AKNk?Dj(VR-Qm_();keg8&qm~YqzS__J;3!RCbyS?Nep>
z3TS^nm2n3eAY2tR1HcQaAcP0F8>$f>uqq{Y43if?UafR0Jg$9l1n8R2+6Z~)Rca^>
ze?Y<2dGi<I>c;lb!i7Ng(=-sqv7`S5<Q6+43O&d>_RhZlHGvd27KFxY7zVV?rqAx6
zn$5Oje9->%$G_-JejdGAU{uX1B&%()p(Co+^6X>uJFOl_Xr|ULAEF9va(vLZZCj3j
zAMM(YgPHc;$MK|p(I(*9VI<8=e(iPx@*du<@Uq{a{cvnpJs0Rt__028X07fCp1++d
z8=-hbeKQKyvK@DzcAME*i$LzdHu(&ez3e3s8UgG)MC<UywiiKqhJA{lvo?mUbp9+`
z>HRsj(*0Pr(*HQNvI6H>@>-k7R#qg5rJ7W>s?_`o8o}nAnTe$8<cGLcKYR=ZYp*>E
zSL;h_(4Y<P{eXu2smC9<whVIzvh@jczFdd0IdG=);+v3ksXG@Q^$eN-*ZV%CHPWDJ
z8dPogFD?j6(gSqVz5~V|YBj@s-PCrl(YVDwxVAm}Gp&ES<X=KT-_Er39R4SLbuMge
znoF-`*CK$)tz$b*K+c;j{|NGZ?CTBiY(Lv{1{x`V-G+ENy2E2{fjh!h%Z3+WtS{lh
z*^)BYJ<0y0he`}P`YGUN*|W!?d5(SC4Mvk$=fG7!Tw>kNK=m>^J{WaLW0?`qNoPIo
z!EOfo<tN~uvHosAJZE3i0`~=LG(z(OJLodtAKBmQ!Qdyh-9`vEs@7G9<|b8H1q^Oh
z)we_Fr8<nTKDSrZeh<jJRi;#UAE-)k27oO{6|fM6$5i9~0Pu`TwGukfsz*!VMU3hb
zE%Pp`mevE}iYkj9+ilf|??^ILtLsAeK=lVbvOLvVf<IQJoI>M1Qw6_6u2^+ikLLQI
ziv1gPaZ$fr0J070t~vnR)WKUQ{;^%X5~C>Rtv;R$(tYZm>Ol2~`W3azQT3z#NFvl>
zS70ep9WfK67u8!3<>V68Zz)nq|JT~m6PUV@#kjBc<Y&~o{?L_(=uuhs_L$LdJx=e2
zsh+kt-1nJYfa}Z=Easn;D%DnuLH!$Vm<rZrKV{?Ed|?w@TY1$6LEEMj%=qQ2FF+j|
z&4%Q+)z8u1-ToZ_e|t&`pgEwO2G<b@Yat(hgw|%$TtA?6Zdeao7i5=#VbSC))FD>8
z9D#K%PP=t0Y&y?tXZA-~vUWGs?7H?4qO9CK?I%RSxoqtt1xz>jp_8HdmhaICDr?0P
z-%(e0@k)1Sp4LC0p)*$h<|8b-8@mrf&eOQ~%>Ul~Fn0cHIF`$@X|VEu9YzthJT{BQ
zuSaZeJGDPPNrc!jI>iSf@l@5j3Tt~*%a4O`uj+U;FnX)vqLJ)Z`A`JzfT~X|u=%R2
zACVkXZAk=+zsh?ga)(r2XQ6pm^=BVc{D`V0LcUy-s$C=!yjezQ-c@z<f*1Ex&#qGc
zo2D9E3Shd*kq%&{YCf&mvs7I>L71c3Nh{f0)n|G^AE-2KA<R>?$be?P>Ij9b9;y5&
z;#8m-I0vLpR4j!9pQ*e*!O`cczq>(LsA@F_xFS{KCt!K0x`Mqeu0(b62#@j4Mcsxb
z0c+Lyxk%Ql9kjvbsy;9Z?r&5NcmroPscRpErDN)YItYW+o#;{BQ!6pZrK+Pvc$lvK
z=OGMcs0W5Yn5A~1^<%a=nPLvP>dv&5zORl$pqI;2&zTPRLv_RrB+kd`Du1G#3)D{n
zk$tM3_A`Lb)T`pa_Ch@_4Y@+~Ga7h{)eRPc`=xpunSZ5jxEHzC>Q)udELD%Sfu&3x
zPLZ{D>czAYe6Q~7f!s&+un(x&C$*YJg>v=&2f$UR2i}M9t5ZE$57lpKA8a;pYc>7O
zp}y-hbLK<1K~qj6z(!5KBQUsG6O@69Zqek=LoK#xP6orEo8}NcGj4}w360V_HO+E>
zbJwgo0L|T+75~7zrzXk(%{`h0zoBfeCZZJ*Z;g2v00%VAi>ILDqnY7`>_N@rOnBj^
zsZW(Tq)E?1S%BsRUS{s7CUz&h2-L(<s~^)0p?G1i=D<b(j%%_y18_n!qaAW#nm=oT
zEL^j97rcnjZ21kiNR4L~2v2L)X5bZw(x}q`h|x54PK7sTHS1e~Emku+6!<tzY+dNY
zYib#xb3r3UpoSMUv6%aFiJI6e03>TpiSXi*rgcLkS2PpuL3mZu^b$0$YnoJn+cz}*
z1SBb%$lsuHOT(N3*&U6p3s~-I!aU(js%BRj&41D~Q&LgG49)&uL6fN&X#*l#^OSn(
z9L;EoLEqOjD?su<W84Iqhni~NP_=wbB&{I}G!3!!#y!zgtVi-pGqE{To@+j3!$hHG
zO(O`4G{5E`DbZ|h21BnjvlgI9-e`szX#QEMDf<`PZ#A~BaQ~gA?gJEl(A3=p#79l~
zBCvhdT<!sb<(j&;K>9^9dJdZFt7hk6sJL*mX<@OJTlyTh^<2bQu()z%wcy%DZs0I9
z<tDC<19rD?-?YGO<q~Mo;KrqjT6}-oxf$bNVkb8_2PSrLbFg*B?dI0>gV2K;6ALyk
z?!)gev6uVt2@LMz&c;KypKH?-+&<ixy3q9Hn(qPJk9(Mi2KMLvZ4Z?IE{!4vhdFy1
zy+Pb2GwcR(V<M0X=GtH<hjWH-2WZ84f{Qr{)le=Y9xjG+-D&cFl6$Iy@D!&i1ovrf
zEe)1uxbN7z=AyaLd9ZtyTSt-IbKGcJB*$^bQlWC5YqJdS3tTgAz!SLEH2KQp^1YDD
z;%3o;B$r#*6}bCOZrXczlgAw!fWn7dY&fKkxamiMf6NtkgQX{!7r^hQ+&zjJJ?D%x
z=Dy%AT!W)7+Bp}ItksIYLAYLfYc_mx)eaj9XEtgJI{>grdyqztE!vIOU}&p$%>Ynu
z*IuE(*AA^Sn_^Gy+Pqni?$)Z3VQG)HwgiNiwl#(BytVhU&`|rdEiOXkfHsA~b3R%-
zwbLE#qTi6atChz=GfjKw33BP$!jUM;)CT<uK$dp(X5@0TC(eT<SDS#%eC~nvP&4H6
zw2Pb_;c&h-NQ>+v?E(tw6lm92;L{WB!(i0unYKfBkUrPepg2mQ)-@a+7HMzJ2kxbI
z(r9RwXy0Fjr8n9b8iPx<A0oi=PW$`@aPPHGBB1$6+h8`l_^j>s8f9O!<L01(U$x1d
zoxp$Bx>2CWh420rCf4!Ew^6vBFT;*A7sfXxVK{&OElfo4u03EPk{|31w$pt7C^T>s
zpVS1T(Y!|{axwff0d~*vUul6I%SYCP@H~Hvc9r7!is2|r;J@Dh=S6<#Tp8bA5+Cvh
zbdvd)2uLsUQ?j9Yg+E5Y%4>X#KkQ!TZ%~hVlV3y8q7>dn@t52DxG#8yclb3la@^zB
zbw@6h-$pNDI={Rvk_^5J&Hl6aTSdra^J~>;yj=dD5Agmze+&~lCzr=3N2B%+`NFaA
z?GgX37wkUf(_g~iQ$BPva?kkC6QC*N2i>E_=g&}JtAt<HAHrAsP!r&#ye%GHl<^H|
zY<<snz7O07{!A~ZeC9i?2cVp9MN!zV{9*e1zwtMFzze5~(4!-yYlVgsm|ri<EQF`7
z!n6=Lvr$-j9?2%*eFGr22-0m>+A4%2bi%m_J(mHuUFemFWT%j}6`H$*@>PKE7VPwv
zcnDoCBH1IvuY*rsf-M$4B??hp@XV8h6Wx$pb_#YJ`{1q!A1GXVUHFSai8q94$*`0n
zxV!`DE#bHTgLi~Oe?WLw7}^VLsX`N46{ZP)c!MTWSg;kiETI)G19F7EQy|P0TJM7S
zJYhfpa1VuPO_6&njH78}fv}&bp9;>2&rtYGIKBb+7s3Xts<}epBTYVvg}F~rnU}(+
z5P0}Xa1H|Ewcu<4l~Up4AS7i%#Z#2M6WW%*`}e|(J`jEqp1V`43n4V=sSvy=R`^8-
zX$-RO!j`#6T*U1|p}9^>ab7`oy|`oqxHpI#HU38N-3=t0MPmSJu|;&l@d9p}xcDth
zxQQ2@z|kFI=`P@Riof8T45p%0X+6AKRQZ5qkGRhTLN9UCCD`>A6$-TP6Ioh?_=qdd
zg3MQJxgSD*F*e%?okQXqTId`WpHqKxM7&5-)j)AVXIKgny(l^nEY>BvA!1@9cyU5}
zMbp?&QI?T}i+7(xcv8%xPV<x)(FtCh7Uz!z^%?P15t3-pG8=Wt5cg1*k}X!Jt|3QE
zPZII{-4`#1f#!ke91gn=#ljZwG+$gu5!(WBa|-~Uh`!PA`<XaoC4kRGeh5el#iJ<z
z6p0PGLRcbhYyp*5;^>pem5RX#ta4@ItgC=y4~2Fu-izmH@%vHSSBT`3xT-hBzbnM~
zWd4ijJ`T0`CJu@Q>34BJIPhzwu{*%FPC9WL+^*6=1Iji?R_e1iNqhoSHcQox0=HHA
znhVWsQqEhbY?rpVKxK!NKzp3Kqzg2;bC*WApv*(s(jPcaDP=5hPA_S{89IBV&If^r
zl#UOF^puoD{Z*9I;u_lPj5Lm-Co$6TIq>4FRImj8#!5%jD2tP#5WnE!rBaGZUy$-}
z)`7by<#@qTqU8S<a>-I33jmiSJuP{!NRbqMzbeJNf=}0-QtO!@y&+jgAbU${Ld(3{
zQY+dMz9(tOV5&6tDun6MRN4;7kp67}OIgw^oYCO2rLz-YB3DYMAn1K5v;Zm(rHwx#
zmoEv&fqN{K)k9JsdC|_|Q|T+sWS&X>G^D?foQ1S)TPXdw5j4e8y)%%$ly)MT&ApNu
z4nmW>mR<}6TdCCh7|P0|Xd2AlNo`AD>Alo=Ad*kgh0RDlON(*ljjNDCaAJ)6BIVEo
z;hVHPAAs*tiWS1Oa$VY^TqobK!2A93Fej}~4#=5!6*yn{`W)ySly_Z+Gyd|dU*W|e
zdHG40KP>yx9P^0Wh&Gx6<@FjQL2}wzs07P{>LM2+|1bb#C*+B=atf8>QeY`uenAt2
zlky5$)kex$A`G398`7dMN<RLp6FO()^t!McBiD;Yeb35Xxp+>oa=~3Baq=QR2rtOv
zaQK8vkU!F7I8m-S0cA<DzZY_s<)<gnGFN2AAGvF?n%<!6@<=)baZ`RY4Y?HgmM?O*
z<)Jibxg+bg!2CVA6ulXquiTfOeY)Jx9rz5nN-hes<nil~%a)t{0AQ|s?k}|LeR<m(
zR4q>)L?Pvea<x;yJ(4#(fcKB(q>12uBG1|f*PhC56ef8tzonSo3t2}yA4ReqJFXng
zfrcabDpv%l@cnI2ZcGE|Zlz~mG@^%+uniUURQh#*`8`VXV<cY6g7*;aRn}2}*;_ev
z4S;=0h!qA8D0vj&^ig~)@WNNQL_OO<C5jfoeo6>A<F6Q719wOf>LVARER2VtqskBE
z05}7cbeir5D>MAS7NUd=g!HB|`5kmplvLVAxTPGR58$>EumSix%Ij80?kWnMY`Le@
zT7@K4(bDLUri52PlCJnhA<0n2%fMwSD=BE1uVjl5K2jo|qxMgfc_)y(a4G@^-wKt3
zv~69a3|fPvSb0J*-IvP!>qttJJ4^l-N~yJpb{XoNegsI}5}dZ<>h(VlNqya2)S*G!
zDe$&oMm@+I-KO`YvFmowHQ99zE;em?5jxFU)q~`xwR9BV=f(xJ|K7X=n>t*JVg`Vg
z*L#4X)sYO4wq8w6v`Os>Slgm*0JLjx5jAL^Rty8bxOqU*p~+0p{ThV`E7$QB#iTlw
zt^-@=WfUdt!rsKS>t%WqyA271PWRs^jNjvWQ#44=JTC^%zkhI76pY?{9X`&yO8bv1
z?AKsm9jnl)dpkR&Dw6%|A}iGV*p5R%d4x@$2VpR)p=TJzw!<l~%0SXqK5Q4%w(*@u
zz&khoa|%pv=Y459v4fvPgWpcR=1!FD;=fS1#OcmIpdjvU-ks(n9{dDaBzW>hiW%<V
zAFZa>kFV~4>R#Tb1c^6)c|VLE;D;JO>cekp0ihqSjX}<z?@9s4Lwu|CXoLX%2rc7}
z^6TaT5XjGUfonnh$rC6$#t#^TvS26wi1w~R_`fE>i{tz=9313M@Sm!KG!)yONW%E5
zwDl6sbM3%=l5f5U!U+EIH)uxkE);h?#oyP!#A!ZDMiRw$cSGx(;lIuSE}CzG!=soN
z8}B1I%Xg(U!Z|)@F`S9zo$vR+?>K&}8=N}NkBdiPJg@qU<O0veK$yt?O%0XA-#5e2
zWPZs_lwIOqb%pRUU%x9%T;abTfHPNluQ#xJjgRyL?gqc515DiHtI>F#!Z)~tR=>q3
z`~>)I{<j?9?(o~3I?&wZ>ve|CJwE<6bkg~+v`Ek3-)4X`lXu^SBnv9g%;q0ZEHH;Z
zP!F29yeCC;?(<D~kUrqglleSeO)L-jqJPk$`FuueIP-|VUI#3X`GfTA3-~knV0pq1
z`qzoVr~KiOsM<4rWo_7f&Zp2S=mkHU>=yEQ6k9Fg-Dycz%<rMbf5{L31!X0Cohrz^
z;*%f2{A<3*3&|UP^hI!%@{1^lU&e3h3@_gDSM6~09Y5U-xc9u61bZKNrG&n}k9@T{
z&?)DaJw{T&x4VGCZ+zo@Q2ox^X;<Avc=`&$wSotYWgCP#WMY$W*aOLCL1v-3RTw-S
z@NGiRS5R>iS|3K)c3}@~Y3>jjQ<Llz2H!(&moRE3INgO$TPXgvTS%ti(nBcC2i{ZI
zL9fsr;lNzv_6p-D3gInuBiHr`QAx0LNO&?8Nr2GU6FwalW_1DJh){|!CU;c$ow~z7
zp|=hXG)UO>0V>CYECX1A1s4jHh6qh5ICfkR!{L+jgfN$m{e=o$=%7@XP;U`*!i82E
z2u})m6pxP(sttiKQW$a$z*E8_3d5cjCd>tCl+cEj8fS#M575BT!UKwM#0bqrRP?Mc
z=P(>SCv<rW%~&CjW*%{ZXIsF}3$L#L5bqR}U=&^uW>SPPK`@*|?xHY^`k_Rj$un>#
z3B|4`OBVVzfistdi?sN=BHZW-wyVPAB~ZC0JjDJQmM@Jc41PnHoq><)rZDMekfjK|
ztzqz%@cljv-WH6LAiN{Yd<B)ef>YB6mhK53w}CrV@TM74ny{!ZNYjN6IF!w02%!U^
zk|~V23GOW6ZUKPV!luPYa)hHB0mv05i~#9<Va+Q%iU-0SIy8|dIB~cG>z)}ln9mmy
zXrc5-XiTRr9t#2mZ3=`bPCA_NL|C#Es!s)u4m&*)c$)D%7h)(H_d?iK4XTC0m?St;
zBm_mlQn8R*2W2mXv$Sw15dza-_m!}eTK2VY=MCU*gf284DHU`$Esup#{5S~T3g>Xd
z7VD+aQ=s`?=-<JKYOfRhXc@9soc=FV_lu7AsM7(l{5r~fu;4-BE5=ekcTkiJ!25{{
z_XF=Q&g_A*L*frJ;bDOI5ABd07BA6=ctqSl%e|xG{7Fax#f`I&1c`oA06!-FN?&8J
zn6jF_zYy_9`qGb!F?3caOnk8eNw}z<0B25$6E`3iA&#b3K2mI77j{pHX+FrE7T?op
z&?xaEO;gW^t7r=;TI@;Rc8s_;8N##Tx%SXJCtfOshp}QkdK2QrDKxh^FZTG0=0EY`
zXgZ~EL41+{e1iDC9g>S;FirUr#f0NfO%fOMLXs?QIuB<qiK#SHUlt9Y!F@$MLeu)I
zqB;h+YhpD4O>$inPN5BNh=tVK-V~>I2QEb%e;k^(M4aoyizsfUNUHOW_~is>?uvan
z;8ETaV@82HRcx>tY-!>{+IvbDm(iANhWLgK6=jP4KZ7(&oJvQMvPGVD#&g8gv%r!o
z&gu){eQ~`zs`Nl)sG@n|A2joLD89S|&3rMpKXQ-6u=ViiiBs%HA(^M*+m&$YnV3L9
z$me2QPXJ$tznun6q3A_(t0FNf9Kd36AjLvniuy;$m58lsLFJWL&=k1W;-7S=?Txth
z3jn2}@dBz;CN5bD;ahP#9T0jacD@hXdvQIDsUJk=siBa56u12d(obU7Uy%DOUNNE(
z%f;R{cu^rPoQkq9;<=7!lCNU)b>P2=^GzWAE<P9y^DfeSI#;k(s^SCEbyDLH2-i!$
zy#<-8<h2)?8zdu5Og2jMhl6F4^jiQlH%oV%UC>@zq(*^I-6~mWvAj)^LxFdbc1}mx
zc1hU*gFB@1b3p8r8v6jhOS(aO5bjdz)4=VPo(+Jehcuby<6hFj>9Dj{TCf6T-qJye
z0PmAhPb1kcW%h<M2c(X~=_8FX(TC?NId&pBD0LeFsh>21jy3s9cbfx$ND7{ZT!5tW
zhl#_|rK+GgBK<_`h@;Z`&S;=OsedQf4Uz`a!RKRAIUT$RmZo{Y!w_ja&FYU!=}qDG
z2`LP}AmBo!&(vID((3WF{tuVFv;**@G!{Rn;v%FEI3I<D@NcxJIVHWJY0hcMGZ(oi
zDXAB7XQV6&Nk&VJ=tNPB^qm%eXQkG3e*2tM`WJkPmEH{oXPk882!!XQyif?^rMq;#
z<$^Sg&g~>fzhfcn#A3PpPmm@`23qbVNvZqbMY2?r_Tnx{jn}}$Wodl~e7YhX{)ptN
z)MY=Mxh8cuhTL^&SXG#~A?;ZT6St(M^akFRPEauZj#PIt+Uc$|IU1bzr0eaWnJUHE
zU?@#$OZy_ubg2;?P|lFrZHK{3$)G@*C6#;uB3nx80%49+D+5Wc)Z7H&eW|E9XdXz~
ztEfz#bon^o52crHQHgwM#SExCk{WMA*<-2AOOzEz%kX10?uk@w5rj{rvuB|BOd4Mb
zmgi0>wKsHLNKa2er%)=WiNYeO35Dp3r7mN@_EPG-0(B~p*3(Y%D{12t<X%fQO5RA8
z{itE7)WH)hWm1(2z~4%}n?duPw1_^V_mYV=n?Fd++Q9rrsWxpKeUeHj@by`8`p^u!
zTuL1WM1}PFG77&)GiO2gReEcO7vH276q^4oZRmwE7kLGlSSz32f_7Rb2eUA-Ud~B`
zimU7z1(gkQBZ{JLls_DW-A%GD1x+{0W9eAX7I`l1YP-p!rUS5D{?R!E*&T9UijKL<
zy=i*2TfQ+6c0J@16k_+1+tLfQS3X0L25-3+J<$WQ{u^4)NB*16xcbVURwD72(<Z^h
zA-NA7_YaWk&O`$pl{?-<E>M2?2Dl(OSr5A*vX#1&<8qrw+W$QvUw8=<p|S@B-ooSu
zPr)57Poy=(Nx2{z&P2!uDXbMK*O&xHPsv68&^#@lIRcs}c|Ps3oRP;-v?p3_-2%?U
z$N@nBoRu}<NY2T#uc9ng*1m_KIJtf~sL#vKqiFn#m%l%S-xuV&h0sZms}4p3Uz8hE
zg-)XU<Pge|<S?AV<C5iGRgt?S=hBYRWw}={ytpEFX^ED(DmSC;zH4&J-(mhb;uWxT
zLw-md>P<P1y7d&<H67Hq<hCIoyDj&@*W^Sr!hZ=|OqFZ)0(Y7`v?r2uIdnd_Gi2AT
zu#_n`q!U_Mat3WGXUn~21D_-Bqy<f`>{|sY_vK}@I(i`2-3XODc^v)t<e|LbA?)VM
z2k3o#B!?FR@K|Oy!QTSeMth~sC$iKUz^C%0UqSjzUVad4&*hi2A@V|QM@RPx<>_=7
zv`E%?g0xt^A))N0yvi4(CGw7Q5WbSXdIR@bZj=w<8`&`rfKs_e4uoa$C>l)P%D>rQ
z@SR*hFZX+S6iu=|IOV88z<-o2n^5>kwls!|pXL6Gfhd=c(h90Ve*6HcU*s2_DElgV
z(^mdBxoI`D(|5V{MdVzRixiz&tEBu4z&d4dIm$LDWnUoNsCc}Bg-uFrdQ6*@Npk_%
zqWqNuN4F}@0j<EjP5DB5d2Y%dbUtgl;z3LD9ZH}UIy)6V3ij?&deF%~cctD^aPL;4
zDJ<oogpCHkQ*onHDSMQ`6bJB9)GuLoukwB`5^rUA3)n@phPGPwD~)MK;((Gy$HIM-
zu}<1z_EjXBeIHc%jR%{b@@h9s_$xzYm_MXkX^UqVplqB9mBY$eis>Iws&|LVQRN_=
zP6$*|DTW!O<k42qF(vXZB*Drq3KEAX7Z~_-ToG~rIH8<Rg}qS4u^232O4>0R|H75x
zzL1_&j0Vs|DA)dhrAQ@*`t?)FZHn-pR_bX$8m-*^5xE%UGwtA<RWi#!dQO>s9!ab+
zkz!SGO1~9gIj{Jn!EU_rI1FSLlzRCfOHiu(g*LpX===dsR2HnK^WRBI$W9a{E4i&;
z;*yeg1c=MZ^j1i&D4UxDaaB2e7G>8I51L+GS2oh2u^Y+^TGicDK2WSBMfr6UG;b-`
zMZm|U45dxsJ4*eX@ZzpA+z8k1DP3kFNmV*f`=%)YI1uMVu&Um7sAecvFQ70}nNH(h
zmeQgl3}!0_mcm4i(wZhcxysOfNb;1ChtYZumDP`+nXh!4jHE!BOh24@qHL^-vZu<l
zNZ?*5J5E4Ys3ZphSET$&V_S)`bP4ReQu@RJ=X|Z`X~V2cX*L)J-zp0tq54iyQ)lpA
zu~4`5LAhy0?xWI_Cd1{5g&uQ-^6Lc9d{G+Nq4HJfq=uz$ia#CD|E_f8;Dw9MOnvrR
zo%I58>vX@-r@dZR<pk`y>ekc(e1lV$zZQs%x&WFzY|>5c0JhD#-kE5&ExOgOLAq5}
z@EK*>bVummnVatUb>z0|9#Q~%hi=i2fbZ0$4g=dRU1R_pb=N)5f{ER_ZjS))&`oU#
z6;Is*+LYR(8%@8`^3oM71j}BX(=P~FZ(U?NB>QyAE7X3!?(|mR59o%4K*vYdx;heH
z-Qpk!59)g3z%}Qm`${8^zwR7;IEQqlwA2gGxzPsBVO`5%$Q{xBK$}uWb=Kyf4%B5)
zygo?h_=GAQ)3qpoqrp0hb2{)Ly1qg5k?88u5s?$R4}*XR)&1ETWnsG6pP?GAdy@mw
zNZqJ>l%3K|p-%U-&YL3M(Ym3u=@FwlK|Y<;J)utXoUSu1CS!F&&q6a!xA8Kl&+87?
zMp?Y>D(xX$(0N(t=ud)<Sq{>Rx?jElk*J&67?zTBD`c2Y)-@r6mvn7uRd!idBNV_Z
zI(2&_S9Pn8Be|wC!~<|$_nCszH*^=j0(VmvM!#ZA(JiHM^OkNB2kP6p!jT}mqw5t0
zvb#Eu1{!>S_jFNh08G_+QiLf@_mtui>AI#aP|eVFa>Y~2)GZDKO_uJ>&k*M76gu*F
zUpJ24s|UI!w8NICd%!{XQ1^BmH1l<rl8_YWl9t1@C%U-GK(6i=iaET}g)T=sz1IB=
zp_6-~8%yI@sV+PlG-Wy$+B1Et`}iAj?{s&{&}{E@GhUz(Kj`Y$M=d_;cKr=6KIs<O
zfcvboP#C6Mr&)$vg-&xBWnXk179#no>+~y<Z@Lb7DEqEk`3dG-^b?N(uvR}{Eetu=
z=~HM+eZBtm5SVb)x1nBdgI+_ym5ut`p-49Af8K$rZPs_v0KY}=b{}4B)w4?>bkpCd
z1)A;p#MU6)q2HN_#@neMGXpBS^e*(lyX$py6nM9O`g~N$Lmxxu%RKc}hQhTyPW=Zu
zap9$xM6m7E*J%TT-g?8&pxLK4&xdfoo_z?!0sW{Npz+ZUN=D9CAC1#1+(EqyofP%c
zmrQ`${`xlbgOEddPc?D@`W!vrhxNCr18_t?g(i1L_3!%u5U7{B!|h<b^W<=lhUhB}
zB70oFJ`YZv&@ZR~olyN&8xUdoo7BIC>z5or?xg<fPN+oamz_n`BK769;l(L^eqZEH
z>l>)xc9dQzh8Jh_fizQ%*01{s@EHA>2FRV&tERx2bNbU1L5S5KaN;-aT%3M+F!1N~
zdudRO*Uz9(*aiKnEnrK~zonSPMZH%C*iF<2yg*r!zQG0LlJ$8<;L|02{&v7G>jhdx
zUePyufNEdWyRay`rau;h3SQTLX$im${VjTrZ|Zvwg)l`w{R+iDZ|RqLg7mijg$178
z(SPIN(_Q_@FsR<s&shmiQ}sdAUTOM6TOdr=XVa0E41Ex7RA=fnSHYI0?@e>~9DU5c
z@FG{g=oHBA>*w@_7Z3CX{1Al8(|@Pv`a}K6W)SA<_g|9m{XNp3rX!}0^={4JOo9Fe
zjh|2Se|<piss2}53qRLysN5~lH?0O?p+2?;07d%7A3;;BA4bFWOa1T1AS}_V6j*wt
zUrmSYUh6wI0sM`=dwt|e^?y^#l;O}ia_{w?7>u3V2fdmGsgL?=_fhys-`f>_f7U;v
z!v^L0R66ulq2JyQet*&b(E$d(>OXA<={LP@B5MC#zu*`W7sEMfwe^N1`t6{rVKmJj
zHyCcEz|uxTI~K_%!`*FQ*=*QDJD6Jx_bCMK+-eB<6Ls2Vc&&quo8jV1&}=uX4~5PS
z!!nw&x*K+QLuI$YKN@%sL+^#~$<wgpAx!KsJg<godl{P0Ht=4<s#K_W8)goN7yAs6
zN0IC|aMZ6JFx37EG9N=93R3tQ8oR*WL8sxjVi@!@{6Gg){0;6?VfT<>9<@b)A&I7{
zhYdk=67GoMU)mc!YG_yrl|VzyMo<YdZ1n@~m_ff8Y{3TGZ_o@e{Og6}xS>8Z&<R6P
zZ`chrB=|rj%wQK_FWm6^XRw?!I0x;5i3mgUukbX|uz)sGP8lrTaQL+0EA@I&20xky
zo-y3_03zD(m|l+<!!$3LKWkVr2BhZ<vHjp$?0-JR8&*+Ya>3y81=I<Kp|lXXXlOSL
zxkQ7S7K}-T@jrtl*-+u!2<}UUUKED8Y{<65#8pG5NnpEXnB5p&TsQnco#zchPdeLt
z)6nlYfGLJhTIJj}B=<({j-d%X*t>=u^?|!*$f6%jrW$TjI3&%G)eD-LhNWlVXqI7f
zD|nG@=+YR%9D`JozQ0_<u#r%`Z|K|&?e)NrTMzg=L*JH29vWU_myF9dJe>eX9~rXM
zF!<Q8I1YdU!@Fl-dt!(#0{2rxVsB_ZGbDJxndgSS)K9%I)TIr@LPK}zvx^Lu=@Awi
zdX=C`FAYCeqxD~jp%xw4ePwXPHY4}i(7OnTH-@paaZzfxQ3{_v7=Bd2nU98txiJ69
zaJ3l1&xVRdP$@Sg)C60Fp%u+Rz8I?Cgo&?)SPK7qGfbgh+I}}g5WvM4Lg$><8avlP
z**fF*MB0B?Z+w;qpsR5*O-VKx8_;5QvvDNOYH(YO5i~#9YK)^v={DmZ74Xo_=%gvd
zb|Yee_(qJLW034LZl}R`w=uszobfOYr(aEa8egTOE_;j%Xm`xZ*o?yCdyPLd0jIZd
zaeb&b_Zfe8gTejAH?*;M!1$Kz`WWxiNgQ8eGX0Lx-#A_knnOkx0m1;|&mjODHfBCY
z?uc=16q2LHfhIhIK;wlasBe&Q;CSGU8P6Po!C>R1Lcl|e*FHjc+&JhXDiLPP&V**T
z)7UW;*^|a={h$+J%$Wy7q%pHGR8JX;XlLiNu{a4ylyT<}IDE$V$Pb#)#^<e}5@WQS
zhTCV2dt6a=&KM#gi8a=L4DL8^!lw(yqG;q2j74-n?4ohI3%pM>X3Rk@$>`*@FrRE}
z@i**VGQOpKxXZ?kVJN&}Tt$b?uN$Z6Vg82EV;8t@8hg;EmSXJi6vA7^9W<G~ZS+nA
z;Er+DFto*8<Ez22d(SwGR^+M1nYW;sW_<My!gOQgVOYpA+QtKrZOnA0K_|yps|G5Q
zYh3>m@b`_oDPa4+*yLX%dB%xaARZb|$f#((v4EDgkBsrOqx9G~n0~}pV0^F$EYFNx
z>GOSVY?Tb$3#0o*01Azp>Y}X3SRM}QVq*^u^?Ye8rSmZ*M#nKHvagJJbx_gQ#ztQu
zePirQhbu~rZS|ljGq%lx-*1g8XMy{ju?|hIJ{td_Fz6@aRXQ{9*;qmcddiJmBSBVS
z<Twbw7$4Cz<*PB2#`14Q&u*~r-B>LIxpk&n@i4UB<hcsJf8<<E1~R|F)RESI8%<Sc
znZL<2mev59O($QVY>Vmd7D%?5LTD<p&Ez#6Wp1VccOcwuDpMo3%Tz$|OLtRHD7@co
zYC;n+4^vGE08dk!0kFHr)Rhi8dYQJ-Cj4I0<Wsc%^ESyBf!}9ZLa*+A(-oQt9WeQ3
zK<A*TO$DmvXKMKoK!20!Gm=B5hL2GeV4D5}5B9Jri&kYvOwDQKb<|XazL7vv3LQ=e
zGPPj=KW6fMh2{!2rO^E3gz3{62t!TJ@*s4EnN&1bgqs}HZJjjLz6G5K(_`9Wk2D30
z2iqxA5G@l<o4ou{wP=%ujvB_8u24|ttf^=?XwI4D=K~&VntKDnI8)<v<j$Mav=bF?
zdP+0S3#PertS7<LZ90;Rru7_D5}l^#%2l^1v=3-5n<8!?xnkNytGcVE>OaHaH530Y
zlIx}!TTyny<VAafH%)Or!nG7r0d3XYGF|%tb-Hb8(;mV*reSo>CDk-D0l74jE))%$
zZb~jhlVq66Y9p6vn%)RrWSN|w=uOHt9i0P%Ii|Pxp)i+g>NgQO_f3g|fOudU;Rc#K
z(`_3}JTl!fz?sLU4YPnRFg2!i*b|cn1y`P$R?zYAXQn4c0G^wk{0r(ArZ5^|3r(vk
zAbe?RI|xluV%kTms#m5#PMW2?HU%_+&Kr}7em+xb@}yrLmYK%r(QI!`lXe2}&eVn$
zs_#wNwB`N5R5uw0KblTc4a-f<5lQDNOf_eqWxkl!xB~ap<g)^0-%JWk?!KGMFG1~M
zeoEiZTJuZ_c&;<AchZAhZ_XTsI=PyQ>A1`W^YdX)-C}Ms8u+c|&J=CiX137!+|9g=
z-mC5A_=UjlFmI=dx|_FCBw)8Wi=rDI=KD>c;%WZp4ZPT6W~pQIGFw9++-u&~4rJbD
zZU!{>nYT4#@%`;L$B%;D1Ln<l(4;<QiM||Pvy(Q$4w|o1XW(c4N^wYk^M)|c95So(
zK^kDLpsF1<>uKS4#C-2Aa!1V(G@JyQtI$+2$b9eul4E9HI-?Y9K6n+l5c8&+;5=@A
zg>48Ycf#yTyCI?G^R!bEX6|zkh;VZ`eX1wTUcKO2gn0%9+at~UF=BG3%=i8T{<L`k
z%^0K1vH|cj=BTa!M4R6{LX*UpH#I@oS+kx_cbqe~cSW^h&AaCyi8H^^Lgl=fp{15H
z-rThb*e;k;DP);oE~hPyi{|h#u#{--+Z8%VX8g1RgM`_~54E^teoXQF%jRi=!F|Pi
zuN87v%~uzK`<nTEO~9|4CoKoyhFN_TWjD=}s4qz|?+-vb-7;V72bSCBhHGKrj?-Ko
z1jJo)oyrK6xihVjQq7hTC`>c={D>soyqUtN8Rn$@0A`w7Iv~t4&+!E=+sx45mSY}t
z0*#+*zDrx>_svC5p!vY;PQ!MdS@#Jl56ydgk;^wPy$fd^nZtTR<+0g$gm&c%%n5y<
z^TfRDHAtVD|EA&hnRyx^o||3hJYSKy2Ay>;Hn*ams=PE$egdCL%wJ|9d1bCk{l#nZ
zo-Rn<m<OCgwM)&rDF{_&)-^|!-kQf)K=#gD_aH31H~YuI-UoAk=O<)8nw!y~<WJ^5
z1Cje|-b=HGa`Up?V5=}MqEY;d`N?6Zd^KNN3GQ#^t>1zFZhlOWRu{`W9iH7<OW&)|
zTxW6X3fy{&LqeIWCCml54VI-e9o%RctU}o)%lXP!u;uf8C*0p+SxsHjR?F@Cz;ClC
zJ>Z3#C89A@w_839Ms9~?@FL)MS`NR3<}OQBYIS$Z^LB7_x5cpniH9Y#1%#fKIGU#H
zvGhp<+{+S5oO><fsCW0asMbNa&ysrrfc=*DztZ{p1C|#wNcmXI)Wi5%8qki=LCev4
zpz*Uz`i#Wi@-KBXhb-M%pb-NsOWlz>Y$?A2?jx2jG|M__5f-4G11*31BNt=|`W?Ar
zmfAG|54IH3-ff6w=M}(@TUOGSdcrb4n!dkKi_jLng;{2~f-T(Q_Z5XFEn}#GBP{#~
zcp7P`MjMBxEbSMgElyi%(_UMYWq(~HXDt1010HSJ=K~WlmZa*)owbx5K*OH1Tzmz1
ztfgflsN*c76|kJQ^fm(*Z<+iRiSvSGWiEgTmi|dVBw5DMtD9^YOb7QaS$g+@!OND~
zxd2|VsJp|ptCpPp$X&Di6b#&T%M=;hH!QKMVE3kF0>xHSEO%Ff`<6vr6P&j#>PyJo
zv82%1w7VAXY*62`_|sB4)oEEm;jT1GBE4Se7CXiBGc0Abk;}Avr5H_?C89M{vMqUw
zk;}1&-;m3-{E-DO?pqrE4z>rDA{uw|EG<gl??cPF0m$WB4lIMgN0#Ej$UU~)rzJ#z
zrAHOOpIAJL;L}r!^UPRSdS=m#2KRHz-ufVYVR<<mRV%cV(3-Z$a;6V}#g;~NDD9;s
zo{mD4Slsp@_sSAMi_zB>O9Z@lV`<p}+@+R$6B?n+@+bXn_pRmjA|&rDIkfNi-tyrH
zk`ET^DNuj3Ty-{s>L-g&T_m3^xwI57w^$oOr^52uh~$gKfMcrMSBs-JRK8hi(#!VU
zvicixF4psO?sBblD+e#uS&zg4u-<Ck3l&#uAsr;&U~M}ODjTiGw?k!<wH+<oHe0i4
zg1yB$pcU;uY_&H31v=ZTLI%vcSu-g3wcT10fn<mED|Na%t=_*Q*<~F_^FViNCpzr0
z+j?;zR6ML-y^!;?_NVQhJyzG*NW84Rbm(-iRigQ}w{_xNXzsJN*o>z1v8GcW=xeQ6
zi@v{u*8B7d`B@ovsQO!<&?&e>*6d&i1FX@d@bs{?IlWLvtb6IN8y&UYkii{jy*3bb
zgRGY*0&&cG{s-6%woY9JT!?i;63UKS_tVbI3G2qHPzkjjr8rZV^|yHB!mazCi1_|a
zT6@zOnFwn<RXfsJXEscnvQDK4?`i7@n(0PaV`$IojCFiCoQbw>q|JpG>!Phl&RX03
z49#=a?X*V_Ydu5J`8ew}9?5y@UIj_Kwa0xV7p(kgXeL<4j7M_O8uA^6oQc-u4wy)?
z7SrdSY_)%Y>LqJ9^-!0s*IL1~E7pV6fVgUH9)Ra_&3fe{a@VcF6py%JU3vg@x@k@P
z73Nc{rWlmnveuXkmfP0f=YZvowPhHRyVfNXV!3Dio#tw(*2QViOmkY>()uLbI-h>@
zn_<=6Kw+l!X#sLsR&-4G@T|*ext?RKPUjSItsm)k-S@3$DLDDSIy45{dDayCsY&jk
zHIiob`PQRGn15v5@Em22tuHSjDX_K+griTagD4jD)VgUDG@n_W{Y(HpxBis?-(Fbj
zoQ6)Jwfa_=D6*!}If-IxRr-b8OY0E&BTXgNB|ic1${O<$=3iSQ>HO~->z<dum0EwM
z-R&~#0(#{?SjB#**+;9r8{nU;$#g>Cvvu(~l$Be(ilJFyUFP%z+ZXF3I@0&mI;Amk
z->hrsDED{k3mR!%Y`<ipGHY$o^N?F-GteY_y={y;a;~;{i(z7e?Ryd68*Sm+0N-Sr
z_y*2wwuKHvwYS)&&}oaUwofz_*=Dm`Mwy$<s|(C;w<+BzX0gLol85Y0+ji>LciEPa
zGw!zCv~9E7Hkw8y58F%%rFq(<eJI;w3rd4|FI$rkBztXhX<OUdc4!nV?Xww2Ky$xs
z!VcsP*iO=n)5q4YI>>x&Jt^jJ(6%cIDt@*-Ikf)sx4qwr!b7%+)HMaz?0ewiVVj*|
z?ni8Ul7T;Jo75h;K%3z<G=pplLm)h6TS%wMf^B!J!BU8Af)8@XZ8;%OIbr)_Bv?Xi
zKhU}}%;xzVNw{qQJ;{?cmi81QY<D)%_ZMknw6J^1_RmmAPut>DP>r%}q!`T^TM5l*
zqHPgLV2iOGZV8pMw!)uKi*vTN6W~*<ZOK1SiL-U+0Kj=$-8q2A+s2a01>1`_01|BH
z8o{-Tw!%dyOSEYy;-6$2y8}6AvhA1yG?#4U6kfk<Yf6oH#nyBTbgtU2Qe6C+t=dsM
zgX=b<AH29>yF<I5H*LXw0HoOT6kfk&YfuL&w{6ddpk?mZc$#Y7wT<l#;XRv*;zg;p
zxqm^JW@{b}m2_JTHOjJ_wnm<?l#LeyjgVveLeb+~TmLK+-nXf?!2AQ-UlSnAv+baT
z#Y0;Xy;u3RO|)WrWV=Pj*dE(zu7pnowmuY{e_|U!zvg^uo75JTp4nz~0q(hN$R(7$
zu$i+#U1)335oJX-X9WHFr`Tq5gU(A^^C$pIY`&ww_R2Pe7Nf6iHGSd!8{6JsAWCh&
z(vDx5%}y)pw>Cc(Z0~Fj2ZQCk?Q~VZKiI-g1OCw#6#x%E*}`cb;Ipm6XpoiL4BL^b
zu=!Ik_KWQwC++lqwbh~5`kQV03IM;`_R|`|#hy_WxwZCNT~Xh4_JYMQxZZxo27|8l
z6?76~gWZw<yBqD^0xWH^U)=`o&GxY`z`e!ZnoihlwSO7{z&878UwH3kFQQfVc6+ZS
z(A;5Plk0@top!+qon3a9&q&<uQJ28B+g_ap5)b>w<xugo*PuYe9{Z`i5PI3S=YxB%
zy`Kea-u64xv+c8=p!M#4`-DeOIbc7!8)ZKBSuJ77*B(~~oCobj9C_ya?5-b>^S8f?
zqVMmJ-ARXy1MGRhKpeJzuYk@G`@HI?_EGza_ecWmTYrX$Ap2na%78m&Uq#!z!S<fi
zC570RRE5fMyMJ%wPS{u1hDxYCd<i(i?6bdsEZpuj1%Q+G2HT(+VQ+i^Dv|c65%l}B
zQ}%CkT=29#wH8#P?ETiDqG#+|-a{waK9fSx=j;kiOk(X`6pxRyf5}GKdHX%;lH%=G
zbVx4PSJOjFuy3ac`bGOFTAwG{Gi$($B>U0<NRsW>9q{6keGnaBzHE1=K#}u`-INaC
zReOFB+`ncw*Fx^PU0ja`d&BOa@$;sA!)WAE?4ER{?w0)>op`xzKTDDSJN5_j;M!e#
z!U~k#v!A1gORBwXRhUn+KVF8ibbB2-beLfucMrHs`<JI6%d(H{2<mL7z3l-Ya_r}6
z9hPga*oMOU_8D>T?SZ{)4@~6QL+b$e&_4MZX!7lCCZf3>+5M&g_t>5?1$GPUH6#F@
z*xhI``P4r4U#L8@zoQxQb9>2f;9l6<jt8L7zH%;dMfT&gm@KwC{~iE0UfSP@NJ{M8
zBY}8jUq)f$*Y<+haORDD$a{EEYR`EAM43ILDjMjmeE_Wu-`NMIf%Luo`XzYy!7esJ
zB|h5!q;cevy}UJ?`E38`It-TEL+FR5752hZSomV^Lr2@b+QXa=LG#Vt%nLf-?ZZP+
z=;FX1S;mLwnAaCH>l`I-V1B)0pB*_@$1)?zHaNP{1Y@IP^e6x}InvL=(q_k)Oqk!|
z;3pxs)e##Bf44cR(SZy%N9R9*+wRyfAIT1frW0^G9YN_%Aa*%eI$-4P82SZ;yB(cq
z>gM54Xie(rNTQK?k0bsugkFw9`a^(w9YQmh@OCu#4e))A)ATDiABT@0D&gyhHzRk@
z@vJ!jeh!ZkIO^|MKu0wXIaW|0A;58sPK6zIY@AAe|L2IKKK1fP9YdQU33PNh0-7L)
zD+k~)$9fkucd)~cRs<mq7X$Fe9Y-@^;)ElO_IW}bRsKd2=9o*{!{H8(TVOfqSZM`I
zgu{IXY8L6ZLcQ!MN0mMB_q1c=79>#)Q#|dzpK(mg0zTSN#=%mIL%SS>XB`1Fc{%4u
zqNRAOBbYXE;v8dkLFK%o>_>3NJ91d$E;ziuK_$TvNb}Z<j)TKsDbexpIJ`)5l&=OZ
z*)gAbv`dcRLs0F@4tpm!dd0E(6v~`e9d7h%;cJdu`eQ2B9kCRpzu_po2ET7Q5`zIu
z`9B<8cU+d$7q`;X)XWy|-g~dIQp<*!BQ-4>nj@{Wt!0^6FGHpvd#G$gKm-}G1Z0VT
zfC>mGOW7y_vSf(z`<~xl=X35o=X=h*yw82^J?Gp9o7Lg)@T$!lPQboqvy%d2*KJIc
z5U#SZp>J+f+gKeiT{SiiLYTN=(@qJ)TAQ8MpipPCg%+=Rn_YeoxoPuJF6`a1X`ma7
z4OW{~bb@NMG4FthCYy*dXf)gWngsn8o3?0}zisn6U7WaMvwa9Ywc31n4`^*ROQ|}t
z-R8MuD0JA^(5lsG<6VKiE*smOAl)|GuAr~S#`G~P+_j0OZ2Uc&TLaMRwMnC(=zSY&
zbs-e{Y<@GqQol`Y3_1sF7>?i`*mSpHE(UG#=>ZzD33w9@594wG6h>^0QLKK{<`v4H
zKeWlF%fe$eZ+rj`$8B7{gxv`ncPcxWv}rX#;gOA+ZeBjI@!bw?+GgWkSg>U{Te&b{
z$Cx+|eS5|=s)BQ1%%`*e5ytgr(C5e~qHviLqn0uU&WzZf(dfcRr8JW(BVsQU+!%AO
zK;$T+Vi*S983S#=_FxRqRls8mAw{M<866Z4^kS5J0}*e=N-DPSVf?&|>OXxMwzMVj
zV~kNPtv@4t1vCN}Tjs!vKt|FQ7z|>h)9&Fo!;Nm1oM3eDFzk~I8(L<A8H?rvG=xDP
zzn>M#SWG#BFh*euB*Ph7RzNR;@g9AlA(C-`Difj@qd_oqigD~$%D+c5K9NJ_G~*en
z6o_H`pa+R%ET&SkIEMTcXq;gb?SoJ8j0Lo8on`2sMPCAAC7rbr8G~+6KgW1(9(+n-
zO#ThYWX7|9Kre-n9gfCSMx`U>={)110bZmr4p5awI>Qb@8SAVJM%{J{G?QUI2(&DQ
zGi3)ZFiyM&lFf)a4wAzdA!l+KM>;Xyi;OlpO5`#8DP)+>n4~mQ0po5wEEO`A<F7WW
zh_U7un7G8aLEG+P#@wUu@G@g=63mw{nw|qnDPyA+DAqCtuO8;FFb;U4wVbh_4VEex
zk0O9p$v8mcy~^mIozyjkUlv5JGgf<pt71&krL$^=<6}%$4Ws=a`ff1(i-uk;!|Vl1
zb&TH~LFyTcD1>&CF-FVWEymaMj%r}o1^}he%9v9P^Gyu*XrMJSp8pI^-C^vEhZn7k
z2Ku~B8^ii9`q~-w6EM-iC~1XaCu3eS{)SzQRkV0@GuBWEVGqNJ-lBIIG0(uKdyKL>
z;CdMwcfqIo3=zf5`xyP+FyGJUdmZWn46CXY*bf+*FCjC?SVWgPhZrilK`_i%PeG0m
zhWka#-Y8=`{dOKQzDfWYW4!(%oEc{<qnoi4jL=q)Nycw<3;YoynNHMGj6Oe*$Bbp}
zF!+S=4Shjlnz58#)V9p|wA$G*S6C^*YR}A|Z+18^-=d?y5oZ5mC^|CPBS3Rv?ytbm
zoS6v$aLt7|xfgw|%u!Da#*O(-5=4$NcO3+%JF}DyJ08p)6)YWN*3w(llW8{}7QC1z
z{si%6o~P&Dhv`F65nra$vvd~sW4`|%u>F}^wtx#@YA6sN$gJ!FXb^KB7ih<sRR^GP
zg6ZE5(38xc=}LMq)9w&NLYSj;WC~?IIS=eG=3E&R!kKlG;3AmazoIXa`Sd=Rk7Aa$
z!@?=%T8f)SGn2z8{&JcbW5r~|FuTiv7R&sDmaRBu)IN|i%%7;FFP>TbE6kr|F8dzX
z3CuYZtxjZ$l3?N-Q}qSBPh!rcZDcZYWG5O^nA{0qrZS(W)Yo~Yzyoub#`M1p%ygzV
zrRX!5e)UxUlF9t;8rUpmM=LrnFs~PbWHSf)(U`;h_IKFLWxksY(2LBl`>>S9{9Os3
z3Yoh(z%F9CmBH;x%&*r&q?q|b1w<}0pZ0_^CCpJO2`XhK({o?OWKuNq3UgCAB+Hpw
zs0`a$!JME>awRiqE!eBfbuG}i#;mk~!`GSqbj_@aIU$5k)yyxh!fp+-dmhLQrY}Vq
zYMEa+!^1jejVnaznZhDq-(((G4ZT}Te~Jq<FrV`USR>Ql9sV{kb7;M2X2#Nnrp3yP
zqeI$l=I@yhy~A`$0a`0F_$!RQjhR7tsdnZ~s+;Rz>Q`cDolGkoxw@EpDevFSJiQ*I
zhuK8sRd<=T1t9mB{S*@JW!~rlxz7xL6{L?DM1B3t8&v2$z+6LDxgIdBEAv1Hnes1T
zX^1&624{wu8!7=h!mOEui=#{t)nPtlX1<BOF=k#RoEc}DNq>U5QH7yRGPhIq<q`8`
z2}U@@RO>K^$4vXz!98KlrD*6hbN<I@v}N_vH4{6QnyR|&Sq$s9m~IDF%w~`ythuyt
zb!4qs0pi5+=!1qcE0~h<F04g8aNm{n&mlCrv0SNI;wWq20yuY;d>8sWSU*t=`4}su
z3SgeB+4Sb{VjX!4j(W4+Sq9FBwRQ(Yd|5aC1?R`w8%)1^f7Wu!;{~vy=zeG*D}~}O
zL99jg@boxq8@+2zuqKy6@g!^IkKlq?p_FkCVHIpeV<_u&C8i{dWeEir&RV}3eG#m!
z6bw4WdYy7H(X0<>n}3?MFA7`?%QX;g$Fg?MqW51M>rD>4Im0TajY2%@zg%>lWnEyy
zrv#QAZ2%Klr#!%&W0f9;ND`}szHO4s+FlHUDXdN8Xez6Maxv#wp7iEPW7*Pu{&ZI0
z9yDgKZctz=ll5UUNET~5<zg<d7&qzvFJ!ZfR1%oOYNsG&F6-Y{pm>orMRD~!*4Hx3
zUOr286H`*a8lb>wA?qia#3GjT3AjrvE}goIS<0i3yv*7|QGycI5;}F4vT`W$U&i|Q
z1fZ|57*sq|&e}_>Rt0MVJ(Si;*2oo%@G8qS78=)B-dbQ^XYHg9XjQS?hR|2dYUaXH
z4Qr7NOx$4kQn<L5l}V3b9cyt7^y*ootuS$uHS+(g9BT!Igd14)Z-F$jnuCGa#LBw`
z(#-mg_N^_fm6YAOZDlDbCVYq0%Y%L^YhfZ<+gO1ku-neMbswaIHS+{4b+V3bg554w
zb0<hQ>j%1h)x-LLg?YNmI!lFE_gD=wOm{D<`UFheXLZpAu8%cL2kU;;k5nZ*z*1Sj
zJzyn12b4jUb^0)z8e*l>iE)^vuz@opED8POM_GpFVfP{HZz@_GWBp2b;c?c_>%mR1
z?A!q}$$HuyZa-pGQ0QTbHQ)%5$1JC{7{n9S6<e5}W<9nCv1LCM2L(I!(mdF+XTL?O
zhXea5>lQfW#6CmeOlNlSBXqj3|MrB2EBg=?NVu_oKM1s=>|%<)xU)Z621O6{^P%WF
z#{QP7xjosBXr8^;IrHJKH+%ja^!cz?VfeFr*+=Q@@5lb|INbJUXKP?DfPMLSpaio0
z?^FIEh@ImC{o`yQ-IO}PKC6W@C)r&e!(cG`Dn+(J*hjNLLfNIKU?PmYHx&xu?6b?D
z5W$u|f<h$w*q2a<Vh?nKJH_t!1LKWmFM0%p)9k@+a4~G>i%^JVw^5Nu9Q)T8I{%$v
zulN))@$C8ZYCp^VgihTFYz@tNBKuD&0y@VYWk4f|ZOO-AlG!i)1`{dlkLlE%$`1bz
z&YWk5c0n?YZE^uhI(t7wEHl`vDCC&QE?f+eEOs;fNH4GlJ0O|OzKUq5byg1h#}TyV
zvKO}j?IOFMLg0DqPD;Dvv(=N}3fTXA0=tFmdRp#^*e4!i5-+jS=+s@zK0E_xm)WDV
zSt?;ieGimU_5#{7m9ft)gUA*3zf`4B&Mv1Xyn-FJA1IaVqg1Y7y~-Y?yva2-+YJV<
zvxDdqTg6^Z<zUt9uAgA3hW#y-ir!$4O@pgtFZc>Db?j&9H&@So@)r7Tvi&JzaEl#I
zm%kd=opj1+WFM7*YhpLjt*>Twi5e5z!rnv|XK%C5$HLGZD|^p%u&wMbXF#TnJ&+5o
zoh_tGfgS9N!+_~z*Ib5T4}0I|XuQi#a{#%=?jA&AFWW%7hWqSby7=D5wx!Fa{p=iy
zoei+No`uK*_RpVTf(F_1cY_;ZdnG|(n4Mk&krB4leKTAfWxquQArILhbb)V-{S5us
z#@T{En4e%<-bLReTk|Pk9<kr0oYxdvM_Z`J?Cv0lJYkPfWNVt8?FcYi&Z-^|JI-ke
zY}s>kP8gB{=acv0+7S+aE}$Jb|2%<$6KB*)#bwT%&GbcR7tU}gh$|<5B@DW8Zqtk8
zC@07fe!FunyazN7PHznqj&WjN1Lw&}rB%y|6Gn*^Z_bfBaLtDkM&V{(PDnMt{5U%~
zaK@jrjkd1=90^6j13BN(K0S!@$A^@EIL;}{2IvXS5ej#m<jin}Z^0b>X4nnk$hQGI
zl=EjQMjys`j?RYRobb62iQq^mg%!!+Qwc^C=YA~6Db79x^rAVH^iZAVe7^wDF`RZ<
zU}8Bh(XH}0&RjZlpW)PBrROi6Gn?YuXE_JyszU;24IPvdIX_Tc;yKRP8}KQKGmqkl
z$sAfzXQgm<J_Ea{oThP*^PGH&xTJ9ggJ3D0lk_4iWpFYoAeqUTN5ueHoVnFNxxmSz
zU2ryMoMJOMoTf!H@ciX+o~EqrMUE|vH;?1{E;{o$cj!)W0Vj@%TM9Y7GB{ksv2H=*
zCC>D>Kr7}vMK6iVoJra$mT+F6!_E~>cM}@RIU2gRRKb~~mrNz+oB#?}IXXM2U*p79
zfV<B5imG9(Rh)aYL8;~}^@m~&r@R0fH#iqN;YBT{g`VF!&T1c+sOLCRZRkx-)oqOF
z7U$bmkOod+4*D87=fa`T#Brd5ZZqd8dMa8tj-SHBZO$hYUBAOwX#{EI#BwpDHqM_@
z0Bg5$!l-_&gYz2I1a)%CSD>?tbCnW@-JEh7b`R$t+D_i(d{qjKdz{1~SnB1(J`aWa
zoHr=5+Q)hCZ=m#Z9xOxO04MQR4Cw*q#X_JAauS{b8R9IA1j;ZcRSXLwoRLKU8|7Ft
ze}ajJoJG$=V~n%s3&@Of+U5amf)m&VnMuw&w8MVHVNU^Oijzb?w#OXHd$9Y2qpky)
z=Hyw>Xv@_(LcxxE<`fj{xl>fz;=o-;Vd^8?Up-;hk!yDeB2L^6N?AK|_147@b>S9M
z49t})*a+gr%}ht*QSLZp72LTkcHlg?%jwmAjH_6LMo;c~`ZIZP|E2_-H@AcSus+-$
z{{!*m-lAZ;AGeQ6iTt_SLSa6D`)eN51G%O~a6#Pfy5Y=m?vi_ycsRkWrd`WP?s57A
zVlemNBXA*H)jDW|a@}Z62;(l?1QO158;3#!cka`$6v;K5#VDe<>yzN&DeiM~F+tH>
zT@?CGbA7);UktZh020gfqu5y-_aX;<XSoiMFrUD6eUHBXn#g^R;y35GZ&Rc-iM#O`
zbS86U<q%EbzC;PQRPGN0&_B=p;c2**#<h6Bi*)XH6sySKM$o^S$>e6z(6YET4RGcH
z_qT5$lFi*M!H{ye`+o&yE_b&LP%d(Rr<(9QZZ|68t+VpEt7#8Yz)ijl>_ToWJ+VdH
zFOGq`#655eeZ}0PTftrC&ea30g!|kAI9kdT-UetHw~Y=4SGe=KAX(0Bq_|H7cYg{L
zD!I$@VCgD%v>ce%xaEz|yUtzt1oKqIja&y}t>%7JkJcJ4pK1zja3@~`spV!DL9vdz
znqDjQ+^8R6_a=9a2Mpfg_S1{Lf%^=F4jQ>!`pGwO`z`2e=60-tWDEBkU1h$_UA!6O
z4p&Eud@J`3rOMm5tDc94?cC^tQ0TC7`8!~+lgs!R4tH_2u^2@+*LxNed$=Fa9^@|f
zZwkNO<361ZOTFCtO_03L9i%GMKJN0z@UWj7t_L^3y+p~q2i!U{xIyl-R4q8f)vkiV
zFt?f3{1NWCtq>XIeoRZ!L#{R73zo*X1GI*Yb5rP6-~<=9DDdEM|Dg2ABknYXL8rJX
zDx!VNy_JtqJmK=`TR79)YD#g~^7hh&Lp$C_v|+X9h0{fU2i{9T5IMrT?gY+}cZ-W*
zJMk`F1##xJeGKBlJ7uNi(v{~=;XyYZkFFRV<!z=H!7*NX2S(w^V^Bq)7w<5|(7bsk
z)KK){g;6Him$#o{XnwpfXDImdJi9>xcvIg3C6K43BUcbFe<ucbocAJ~fKKqzBhhz~
zC;bj!!MuPL+JA=dj!r-(l=t^H;KF!i6hjN=HB;a-g4at&@krh#ilIgEnlhkxikD1B
z@o3)O|6fJnZK6nA3~yN{`eJ#W6uXY&U0MsUGdwQUNXPRsDGzX#x7Y(H3B1?u!?i@7
z<Q2OAaE`Zxs@alwN3NqYnRhoAE~fAvKMl}S-iFiAKhGOD2JAFmIW1f1JkxrZ&)|6*
z0h-BkYl27?&qNhE7kJ-y0y~?hrp6qeBnVTI%R5b>zl*$yH87ON3+#h>KCf^sz5fb$
z1J6UTkhl2`ND<G0f+UxC@6gt*nD-*Z6)y8GXJMX8c-4CWTFM)70$0YXbbyCfczP!&
zl=Gy2fUDr0rC4qyuYx}MbCp+2<)hbl^Zx(f@wQPOu8QY(9O~7)7`o_Wt>K-gLWLW=
zjq`wA%X`iRGIhM4XxXag{Y$kBH+hGjM&B)7NH@mYz>B6E`i;EJ|3R{ew~p!*ntA@=
z5NYAP^fkEKyylNE>^r<OV^DA9<*MLX8?TDa(CxhSEl}^^RlW-gomSrV1juypo}w^J
zH}AePrlyD2L<aBjlyf0-kM|2*i0S23Z9(IGUWP4T`gjEmaQgu-;4B&kdGnqIH^lpk
zW_FnO&J@5#cq0^l8Rca~K>Z=_;70g6#(S9ok#XJv3Ybpttiu7IlRRhI+dkrL+6aSF
zyd~Wrk9oQK0s4eDg;jUfG*9*(L~Qw46#BE{yS<E2*z>L7AP)Rp)j&DI_dX9jNB%t8
z9y#$Fsieo5-%Ga{T=+97Fzw3syNy0KzES~{qkK;*1xeibTd#n4@b}O?+GBiA3dDQz
zchhgqi|<GwIB!0S?vwlQ*S-o%zI@krfab?%TcP03=hH$Hz;~#Hr9l4m8_)~l&)1{x
zIRC;)jQ0dTYY2KL`Sa+}4(2z|kV5zmIiw%T_n=iXjDO`hbcXZyz6~ydzh(vcBKaF>
zOi}y{+Gm{Nm-~W5^XJox{xts(ty(es{gm*J<<F)u#qn2B)xsJ6p)K$*p8qGEdCu}}
z=yO*I{EyV|Fp+<deh}yQZhE?Zo5XjeH+(XGmkBT_{6DF-CYAqyZo-`BGw9(+<NLh?
zyXpKc`nM|?e0Ta}Q6_)q$M7PHU#No@7x+?&)o1h1`~gcj{Ebv-kjr1qgUChx`^(Um
z$KSRNefj)%tI$`#*X*GC4~6{Im!Mz7ui1@(Ug9qb1$HsN_5@@u^Y6Wfz7l@IW{^_;
zn^c!k#@{jlv@3k}N?@1s4Y$x&!EZkUu9ENdD@<JF@6ZF~8h>mpNHzb|LAYJRe`XFw
zc7uO_t`FAoEvKMot>e$8Gi^P8&R%rh<a=`=dW*k=1Jb~Ma0mL0{5q<#YT{Q>`FJy5
zOm~x7_!$&;z0E&Kp}#x)L(AcPEB}fb*lqmhHBfKoKfe@x9eg)h8anyT+ac1$-<l4+
zZhj19+Iy`01vbFG%NNi#=^o$nIOe&RKWatieSRwKbo=-(-3D4e|CeB35AYebP<X(f
z{03eO^1mvC$Pl0R75awx@pSQag#YR_m>A_3k@pYzuAc#HjK3D!jalRTT~t6h!Dk)9
za3}fJ%^v~#5x<tgs8jqkN@zUh*U*XJ34b=l6{h*Se*&7VfJZ?rJAo`2#9lCys<9me
zZIsMBBG~;0I7flUPI%!Y7<mB-&Vp&G6LJy!^d~%Y6<j(CFgL*}s#H5FFz2ApU9iwf
zTY3+{O(8Un33?M@-cyi3$89gcJM`l87Q}srJ|BUx6dJyQ<UDYG0?l8T1b@N8*WpZn
z;F%VXKtUTl+d+bDOVM{+U~q-{2|*NXmQD(c8_^dmSh@jRh@i&-hC&4sTdWWb69m(F
zIb3k64P1m^aT3rX1>aF9I!ds_1cRpp$&C<+7JRt}gE=j*(#||a5cdCYilCGd9&v)b
zGeOP>J~|ETc)_JRuyj_ig<|yy0y}zO69rMrF;C|NrzixTBoJlM_g|9*#wq+s&I>}b
zpr0n-#zQ|{P)+y!GX!IEpr0wIrU-AA;1E4=7X-U01eYx+_d#Ed!2J!7TtVDDkc)zW
zb#OaR;F${Z`GSl{C=>{GP=L2ka5xELDH8N?KrRVxAOv8YRV;XE0mge-U_<%c62TAC
zAf*DwS3t@H-`Jw>ir}*}I9x7>qf<_WKt(&LO2J)<gIpEZ{sq^r3AjRV*9AYk1lOtr
z7wKqP4FZ%J!6vHIz9Be7ahqB}=wg_!6I9VJ-dZm(?Z@bE3Krf5=q<sw^m1$v%-aL5
zQIJB9Q<LB``o>_hAYBaX7QrVUV4$}JXX)P39l=i&z-SeCxWH1IpwSti?Sf~S@To&E
zPy*5^IQIecx&(p>h;$3)QYy7akj;VFyH<hS1IXMHcv9G@SFo4PJog1}(Ydovkn=9k
z`UR`0_Gv)iOHbnifsvl{L4n&aK!*gW6sZ{&?6U{<h+v}vdZU7=NhmxN4A7<NF@a|s
zER733&II&?;MNZylY+t!kVgV*83o9u1bgV>(qq9!7hpdTM7)XdP75+B0AnlM?FUdh
z;YU?KvlkXp7R5n${$=PL5w=kn)luk{4&o#nUx=|d3*#??xCmKv=5ZBHi~-Y4xX2FN
zQQ@codhWtqvtZ9dIBZ=Bv}3|m-@+SDp|BFIUc!Q4$ao7~eu8-)VOtf5uQ2yJ_!J;a
zvj-O_w9wicBwTP3jmL$Xt6}1VkUJM(Cxu56pdKuoM|;x{;Vv`mh6-PoU=U%#KPVX)
zE*$EEy$E6DvvmI<QfQ>Iy(r;LN;aPoenv;}XyI#=J~=JiMSHy%;Rh77ixsY-4Qrfm
zBi-USBed@YOuSI_706lP*Sq0Ng7EGRpd<=oPGb_z2_0x#l_cEs5m1tauhZI@B6Ou9
z*i>P_8rpxJ7cQjBjA_D44ggIT-u)698A7*sG-e9fbHHT@S4n_<L0CKnm~3IqGz{hl
zH&fUsSNJUjH!liLQDdHP;cw8(7hdlLSb?yViiHb>yIzAcMZ#993%(@$atI?U7Jh%1
z>R&DkgSUe%5mr!PRH;yz1WRQ?F@=Aw2#2=8V7c&J%C}SqZ&NXArSR=tn69hB|2)xm
zO?dHdn7A%<q}^GSuz*&?YN0#jcWZ>ZmcYXs!UGh*uN6)`hrT+YoHj)DLJht3tv7`d
z+9=!-a?)V8K{%6A$c@6CR94v}e0>fYn}ze}l+q&HL=pVk!krXByd#`V$@Ny@Cx3vn
z30s-~+Ah37`H~KyYyt|M!U@WbbqVp^S3G#aMU+kG5zhG=<gRcb9l-8cg}?p>-+G0m
zp9A~8P_+xr^a+zLp|fB3HQhWI5C*-7!8{N~WkO_7*hwj<AtA>BFvG&3VVEBgX6(UW
zMukUcD>5#eqR{z-u&owkQuqT8jgN%)V&U495FhWulP2_VfKN|^)@LanJ}q2d2VyIF
zpJI)6qK0rN+KXN}4igTdL$ul+5sjpSa}>Frf@@A9*LM7UoJAv)BX<#*{{N_nT4~?v
zCQ6|E-BHm`BA~d7K79x39-^&bP&g*C?0|@;$SVWHOEh3@ha27^M<2NFBiecy1N9Y6
zEk>uGD4O1;{-VcJWD+2Xq7!+bXe1k;K_W#d`i_f~v@<v%T1(;alcE*-F^FJM5LIG?
zh+d{WW~k^-Dgp`<%_ss&xM;>|xE3MGxC*^U5#s+~qeRay2Iwi#1`lx2qLZ|2ofbV$
zv4a@V9xAAc75zz1Y@8^8egbDi2P(kDi(F})IxG6G0F4Qv+4P1_6b;ZG{+#GH+9xE5
zf@uj&7Jc{vW-Udu^$ajmMH_igKQH>UmHz)&n&@E}TGK^y55cJnQPa!N&lEY|0d|(?
zSuL<Hh}Qp#zHHG;8=;sZ5|5!TSM<FJ<f7=0Q7Ghzt|~Ek`66RF3>JtiYcLmuqLLc;
zR3sXvy3tFbCu=d5V$tv{kjo<5#dQCuMD$@kKubj@>C99n%BOVC716G904*1F+rsY(
z(c835sT5^h0O(cGjbd=uM2jgteO;821+*&BkJ~YbYEk}&(5n%xq^R)?(F)p#)rzc*
z5UCR_pvx5XqJV$kQ-dgt-rm+m5$8{cHi?uM!8VIpdePY;YVpQ+Z;QsM$mEV_7Y(LW
zboX-@Y!k(Q2@l&vidcBjA!5A%kxmhx7QZgh3-sW1i{7{bXL>|g$-ulTT24#%J<*I1
zDD;YY(lHnJMc>!}rOztbxDLMci~dldb3l}{2X-Hbb{vMxplIGp&>s>#PtlxV(H%PU
zkBE}|&^Ib_dJ5b_(V=$uG$y)B>-xB;WDTZkLbPWoFegP{{0+=UqM5X7m=b-M41<qF
z*XiQl6VcD~Hk=k&@6mNjTXDoa*tHXP%tEKV_!}yXbr6^30p^JK6%k+@#q-X9a}u{c
z0C5&?xDDbWexU#gu43175OEW~N`a=M;=>e7br<jd7@UV#N<Z0S;vXoV>?!{C8QAj@
ze?zfRZ}Da;ZF79Yd(U7LzT#xMMeHYbp?JK%_>+Io7a&%=3XMSVF}imVB%Z1V+HvtB
z`iq_rucr9tNpVOZxL|Sb3>XX%cfJWORP43_2E)YDRFDxaR?(%E2yxROxJYp{ty)oH
z^GS+-o)Vur4ZG3eUp~NKPK#@OArm8Rr&5_%@#gQK7$^47qVJ6OYd(C67r#sCgtOw>
z7vM~SIHeVq62&Lp26s;UT^&S{#IMlSHd&la72YXg!&Bf=#T>e~bY49A4;0eGo5WQA
zk}fX(7+z$Emr<R2rnqo1EM<w`zX2{sEcp(Wa>d+N0drAYvH?EjiD#w(Enl2g1DFCa
z_c}<S`1?JuTO?N6!QV^bpXl{jEEXRE*k$o=8E~yc+(rAqQnANokTUTYCfz#giuf-v
z^vlI-Dgjy{UQNYIm10+lj$9SbrRd-_@qsFMab0}h4JN9@_VMtyTKp9YdNpEf)$pi^
z-=RHMt$23}4AzP9adA9q;wgIV-xM!(gx)RjKFVx1h({?;+9<|1Ve$Mmi8tH<OtZL<
zeqJr&y*%jO7BBFI%pLL1D<IP<4txd<w~7Ct)u&xtJOR=n{$>OwI>kHbe9<MoUj#3@
z#l=)k(j(5NI?TJ`g|uqj6aTKj$a=+6DptHNev`tWed5defZ1;qN1lS+0rA}H81@74
zrxchQ6mM^Vi6OD87qExLTv}R2#MVG?qvBVxz&#Wnn*_|5cs9Kx#>LN2CH{o?bRf7%
z@k#oa=p*svI5bX)IkN!vSp4%7KtB<iC{Q~sUNwOM+Dfe3C^%{-xp)QU?Io~)2T!tk
zHMk>^Z42O{ql6y|;v~uc|K?Ki##)HDNVpHs=qkx8f(bWC0!_(LN&k1ybC<-^j>1DS
z=RU|W$x;<WJSD>x=y^$&(i-S3iTVwFK9YZ|wP1ZE;Wm)*lX%iL)L-&vAf_!qvTY7b
z1WLZ9ICGF>=^z|FE{UMk>x5+2uh2Uw*+o}bLM6kAnDsEprby_8OSbaS7a?KMDKt{j
zK90U9$tcyBoRXNn#3V#Zn&)5+PfHvF=;?@&^jv_6SV`t5=!}z0{0mEGBwI?r#Y=cq
z@bs+Yk7<wuNe^x75+%uWd_5<r?gmVf#6(e*WJw-<qA5iprua*$<RS$k&P#-peMyu2
z(*T8Z$p>^=&yXCb0(7P%xQOasvLrLv(6}IZP7Lg9$&P+l%8_iO15K{PkIwKHC7F~I
z%#$=Mg{6GSZpv*GNN)U&(HBbAIKpm`BykGrmn7;$=oL#o`2Tet$>%!(RwDV~AVf+f
zKYWh9GD#%;j;}~gEXMy|pH(j5Q8=?gvgk5ED<$^|K(0!5Qz_Fm$;@hiUY8s!ghrKQ
zlRdnsmYk+3sgaZ(fipKGx1%t^TFD;D2-QiLGtgHrk@SMxl$6kSLvKl5oe9hai7kae
z8zo;~1J@+E%YskVW{EHD$y+3^?gaL2iHuI&cO(z<fYvIRL;0{aN#OU;XqUW2v8WEo
zh0U<rDdE$pyGv3N4D;QR9dyv`k-SK!?z@tXPME(ZiCY7OUP&ZP_kD?SA)xyt-;_h7
zU-I)O7}<bT5>tW+eju^`6|IAk<$r+;NeX5_V_0$^3+|6d*m{^4m0XvCJd`+<p>IsG
zns$EUl0)=kn~?0ghsH@s=;!e1k))TN#wp3~wIGirpHphmR_a3`3p=UXYPe=E9i<u*
z2dOolDvORtqlO^rDBVSeQ738Y8?fsv&1;2*i}W;|OI)QQTPV6o!*0WiqtaiiVBTH&
z9Gz)Bq>|%MI3_i2g}SHoE^V*8q~281<}KYD3`rm9_p}!IN_AXJiJ$ZpDqr)L=2$a<
z79e$A37A0X=VmAdN%Lo;^SD&-BZhWD`ocTVI4N!40%wAyafyHlk-kmWm_nt6loSk;
z?q7n@hfDJq=!=lPwh@w%(lzvqL`l7Ax=%^v6x)oJ_AZCyX=#QpFk_^L->3SsSn1w)
z7>tu{O2-J#NcFVAkC&RW(RWt5fKJ^B(s4@ZBubqrsd!F06$VR5($G(#mn@xE3+xnW
zD5VHfrJnvE=cP9p@FGomkB<52(qnYDFGI@K!EUBhPtmR{>HdEx|93&EJ^_tv>5@sv
z<VfAVgZW(P=LR%hl&;u|Nz9Ypr!xC|>5@eB6-bllmsBYI>n0S6q|-6rE=enj;ZrgG
zu+Y0Km1e_IiFD8wT&eW;N}!ZU|2_roid0I6?s6%cP4B-7=?^@Nuu{5=j)7OD@8?1B
zn)EFVG_Fg7B4MIR`b#}Ts-=gO5UG(apv=w<>CX(H)k-<Ek*kwx=m%Uc{j>ni+>~yZ
z4TW3Mf2yI-AkDoDutw>61sa>AZ%d%pEX|_|Q)`QqnTgKZ(ujW8ZIdpiGi|%HnszN6
zQo}IxJEeChZQ3Qh<ORuY>0Zj1_ekHig~DCwn$JP*NnfL)(q3ss2^8*2f3$-$ebRSp
z(bq5iJ^%&>q_4dOkq6R66vY{oo~M21kX2fF2W|{Y4=lo%Mx@KNAfwW#(=hl@>KqR;
zCf#TczsIGV^{_i3-At#+Noha>U>-@cqaiXSedlSIcr0yt3m!g^HqhnTX{q-#I9u6A
zlsB}K&2a*>y=;FS6dYt<EC+W)X6<1^#!=R7gocx>j0I3<+2?F<E;36i`dnpNTDII|
zpU{_@j>@KwLBw6=%R--r>;>9&9Fv``frzJU%j+OsGGt5f;K?$l;FFK+mJcSuSN4Sy
zF#TkEazOlL8YzYpAp6;R7@&c&qAF+v$?nq@>bUGRTJBEBc2PRvq^z6HhQTrp?N~!(
z?_7hyP}#p<12jyQ=Yz&@S&bAvMaZ5|C@fOOrqw4(wzU=Nr(|a++8r%Z&=Y=IHZuY~
z#mJIQK{8f$Y19fDCp%XR6K7<@REQNXJNq<d=&bB%S~U}72_EQ6lvPlG>zu4<1-K-c
z_f@!^EZa_T^%Pmgrx;VJ>>*_+&&zy%f-`Bd_zZ}o%L3wonISt%M}bV4lA>K%vOObE
zxFFj<Nco3s*>iM^%#p2XM`x}~o`}wivWCB*pC`LO>8*U3Y8sXbWQt{gxg-k=!mx{F
z?G(woEL(61q(n9uj<J-=2Iw<AWwPE1U|x|eTmi6hnXCeR6*4s!u2sqo(aqPZvYn_N
zu+F+B3z0$py6o*1Oih(6w-F|)Wl!jLRU>0O578SkGX?8wW#Ny3T_@Z1CrG`_<x_~<
zlxe3Ra!XcU0uv3g&-($^C`<nx9yZCGUxM4svg0E3wa5&V&ATo8<v;Y@k&V$0*xD+q
zZw7Xo>`pZX+Ai~<<4uQ5_X$X+tlI|qT{4FsK)PjjXjj=IQ_{Bku5A4+kbANqT047X
zw`qHHUv`<^qJ6UMpMmR_y>5nU1G1=ifIW~2X{S0U3%CbvNajcP9)_*5kLVRUB0C!d
z7e{5ETm{-gnKTQd7?X9<hG<+?a0g^UCjAE*lQIqMdmqU*xI$q{Hs1hCk7Wh#0`!S2
zZV9+)*?Sg<*vj2>fVPt-HiEO4Z=mPTL7x6O#(6}p*b3q(x4ufJZYTLFDm!qN+x>;V
znu|P_?oYVN_fSc?n>;ZDqDST5(W%>AeuVPT9&(otfObs&cpLgW<;iqX^pbbc5yD$O
zLJ<TXxo|ti;w#s50Mk!iM=uF~`6u)?43G=1fdtCGwR*x*kbG+c{v^lcS-Ai`A<z8+
z8YktS(dIu`-Zlb}5IKU9c<|)*t{`FZ2D<hUE`OJ<f<?%8UV!;Xx$qZ|D7n{B^qrQ^
zIRKOx`Ojjg$I73gq(Yp$sSb9}$X}-$Z1M6oJIeo^m3vZhK0*FH<);$muTl8*oILFp
zXe7z^#=u0fTtH{|6nRrVhL$RizY20*ZlEo0ntV1B2Giwbu0Y9<H&EmvQ*K9L!7O=~
zJuolGr}v>RTV6vYc{y@_%53J!w@Ik}?4mrK_Ii18{ZsHQUmisl(+cFRKZ6v?lZK#J
zBriD*v`g}!Vt7$3-%JJHm*pSPWtkGWUp@Lt<pFe_DwDg40Cq+0KquRBc@q6WE9C30
zK%r7TQU>m-yp6Vs*W_>iOZmU+^0~JFQzdVvKYF!%&RWRS$VbA#-H=b7foQG#OdnjU
zle;{NzIyrbbhv+0&J4gnZ^>u92uls}+rOf(QGSb_zb5%XdQ_U_2Zcask@wR<=C-_r
z$`0<xm-RuRRlbi3$E<Dg(MG_u%V+vRrbE7l_SBv7m#A8!OMcJ-{cgGN6%4IM{@!*B
z^sf9<`iRFp`HWte=#_ssA87aGRTO*clh@GOzaKLLX9nbh`RIEfpZPW{49d&)f(*%D
zlz<G&!)8Ez#42ZYfsV?f=Yc$w@1aL#O#b|*n38e%2Rnf_A-Amu%%uEiAY6MSKY0QA
zQ}Q7y27fGPB*M}Y`7Wvio|acp_Qh85`Z{oSipd#JuvdIV>#~Dl$EzSm6bIh~aa0V`
zwKx}rHMAL)TotD&5ALQo%}47|h2nb<cSY~B7^sKh6(hJ~itAJc<Ebd6U$>WHh72aW
z6$u#-@lmiM!1*dd>FX+fio3Jmg}-9j5tspr{(bN_P;u-l^aUy04?^L%LSaPX2}QFt
z2cRbv-~9#>thjm)qYqKciUwM!B4q)7Nnwg>Z7?6M2%-~3ghDt8&`5=B8x*1x2TkBk
zDSG+<8m;*B2|!OP9#G0HMp4`V603N+4483>Ra63eMlt^}^x_q-{RZx=VpbppNfH#E
z@i397c$@0p&MD^K1ec@;rAtZ4il+u)H%0N|2~1n6!i6dX&MQ`g;4hM<h@n_xy5cm|
zbz~^sii3KlV$NeIWGPO(3hsi!g8?pEVWfRrj-rh=0lA7%ANX`pF@BJ~f0n1Hrx$&`
zLiP|c1&Y~JYF(&!ArbmTidj@}b4js*!V<-bF%A?jD?I6lS)vF_hWS!O2-S9%DZU5*
z_7z1d1)9ngOTNNDD-_8eps!NVFNDHX1uG5e*A)H_VCcHy%bRrmt5Ot4W1^}RNlRd&
zMxmu(`whj)A?VjCCYv$Ab&7BcEY&NfN}+gDvD66)w-iHEDA%C)>Qyv0Dz=@2WRoHS
zH^FB$E0WfOYf+f#Lm9UfDO*AAD15}wYgHuDmY_|sZ!4zR+OE*0qqRdJ{|0QQ!af4#
zyA)gBfHU2SQwYz`x~KSM7esm$>w_V3U*Q%GyM2m3?}F=Bh?^iXpjgoky$6a3HLwR2
zCdxDpDb~`_a##^<3-uAjVlU{8D$czI?x7-qt`m$|6(P@KhQ<|v&thsO6mw|<IjK-S
zgv=ww_jDI)N)hJ^?8gc=4eg2I0wo8g6|eTdLtCW}#Rcq?YD!?+D-HDcIw&vDzUYWj
zPe*A-<=sPY#z|Q~`yyv$l|A}gl)roiOjo6qdjZr<xsQ*|qsoPp4|7+RP!`fdnK6mJ
zW6H^U7=@>@p2}CflxL0u&0F~%l`HrtbH0QZzDm25u;i!wi&D@2%8z289-vH^5A{H$
zEu|KNl>JjsIIaxOgNG-SNpyYUq;i9mcKyN1!?afnQEsgV7pm-A4lYdjFO|E8D-Y1J
z6`|bW4=*B>n;)SuN*S04m{ZDsZ87?2<+rrWIjwa1|K?KpUKO}l<pTPsQk?STqu|ac
z57NUCuUt+~>RDwY)hQ$>Gi@lHm#7?chuw3^R=T*9q~z~GXR>lmE3i|PGw;HDs<QTH
zxPM+*Mt-L$&r_X3y3*-eC}b%Ac?Z~;$}3c%lcjt(3knyM|4}kBTbV(b;2h;IeVDvl
zWf9%jyQpN)p)gPR{Ri~^%UAwR8-)U8G*#OdD)Z^BR;1iy1okE6XB|K*R%Ur)5-%%x
zbUG?g=6OM~R5{WPFUpkL4uh*urZ$1AR2I=waaAc_1chtLd;`p1SLV6GLY4A0K18aO
ziN8akM%nF0-=DalETT|ct@1F%U+R>(&qAhNc|9GT-c&01FnCMpGX|Ij<@qQyHY)#J
z3D=sGdGtlsX63sZFtirsJi7mWTe)=s$Q@<lHR!b}cYlWYZBsTJ0A{-~gw9bNO4J$Q
zNmKUIIoH~yJV6y8-O8h@f!(7F{RWD6m3tpS@t!jEK1i=Jbr<ySD;pv(v_54D9Zma{
zQmWG%P<E_``U53{LJxyV9R&-9l%G-M$gpxTty&|>f4u-bs^rtJ>!Gsgb?A*LcWi;k
zxK)`>MQszxeH3h;RNktC%p>JKFUU+Ob<uF<u~Mf1_7kOfGp2M}d5IPZTa~FAoSn*M
zF4XN+ZggODP^D0W_lRmCy_FnQU9{<OQvFPI70#*`4#RC1)v+`{yQ(rvVb4uvT}kPa
zqpF90fOS_LJ`8;im3t@9j;ZXQ0r6CE%AxP2T6q+fyj36GhIt>=q9s7{Rqg+Os!lZ?
z4oQF2I>b+B1*r1!U_MY4PP@q<RmnDx<EoF(q3?uhF4aYyRIRCnda&vT>qc~jsBGil
zMW|{o6?cZI#%VDLSB-Xni%_k93JyoAuG6X+rApw#(ka!_eIU`QXD9@BTJ-_FjAK-u
zw8M^7?WfX!I8`4_!Wq?<fl!ZEt#1aGs+#c*6wa$YcfmN*RHe5m{+Xpx48i;b)i3m0
z&sG)u44FLDyA<TeSFJ#m)~o{6x3p6&S23bsw^Eh56Czht+bOGXP1R4o?(3>)TGFai
zKDU5ft=g~y3N@-(bd<iK%BBNJt?Ek(sMV|f-2};-s!aiuf4`-2rnh2)Y7><fG^&z&
z0NSK-sfK8a>Y*<z-Bx{=g)!YxZ4bqiw5nR@=+mZpma+;RsyVc@bgE)0M%ks>;0Ca6
z)n!UA_o%9Dp?+8O{#iiZQ)wKaa9=e{o9I4OBO+7QS^cVgbcba?HN`;d1Jys2Sshee
zpdyAL)g*1EhgG@sOBzwVLUH0z)l@jRhpId~ppB`Pn&IfU>Z%YvO{ltQqdch!eGlA}
zDnth8$EsFJ%0E$^>w@I8irohkTeV0C6sw(DOOXf%b>b!XeMGI>k5M?PLw|r>C-s5-
zAkOOMZh*R~e|ZlBbyGj4{q|Ay^54L@s|6(>9_r`cgZeSG7wy_T)gMtz$6G!75iI$r
zb8}(ISH0tFK>Mi!8qw&lezpxHz^cBu3QiqYzeJ_WC)9`N&~Z}zEL~FzR=>0heIe?1
zsLU`_eUP>U5$gIJ3@uW9NC%N9^*pM~JFTvt4KHHU?I!fas=Yix;??U)VDPNk={uND
zP%kWjWRkj)F7PC)7mdQv6t(r=%jir~ze82z>FV5vkjYSoybA7udb%8A%2vm1hfg``
zpR7R3Q*$T*kgpD30rv~kM<xJMsGd)!^&)i$b~LjtsZ;1993^Tust7Dq&qxMWrtXPC
z-xakj<p|2vo2j(4LXGb~z?*C8wih9DT|I-&(pBouLSV33y-5u7HEKN-blgyPQrxy)
zy@l!=ZmNqYP<u<ggiaz&>NlA{YgTh_!<iPfA60O)s!Lym!8Wytf(7mB!4@cVs1IC#
zg-&(VPK>il{kA{tKl|097_<(k`8kkzpbn(L45~Y+@N-D*y#Rf~YL8x^ji^%-pfIYw
z?~lHR>Sdn+W=uU629a@fH?6%B>X+Yu$fWu?TC5+b7gFeMO5I06>&NQ(GhyM0`o*;%
z)9M~u+JD+=0)EBJ+G*H#(Q2>J^g`c3<NG7fj%Y?HLhGo}-hg>0P5b+3bk?*`7}Q1M
zM;lgGjp$4CxoLQ@82wR=j1JiDnt5$7@1gmWz7udv)Bg*Ir^ZNU79Y)}(@^)-h_F~&
zXZdONT*P4fHCJ6h0yKGb=nT|6NP&KkCUGka9@jiek?<3m!NuT0G(Xd^DpaFd3KFJS
zM?0u+%>hcQMQEa51WKgl#T0lErRkyU%PGw{Du0XC1ky8dT4Q+*jWHTN)gxPDHKFr?
z9jCFQr}B)(E*euBuh~Rz(*#Y|E6_;PxCDco(=<~cF-c>49oWelaVkVoG=B}CF-<eN
zA1LXX7%Csl(4<jqX{Kh!i?EcX`I~aa7c^s(D9P4DEP;nPn$Kw8nQPVTio%>+)O<xh
zj6BVfmjRQn`IheQ7HHDnf{8-S2lP-EX%>cp6l-3)5A0ISRXVMgX=Yvk%oWYgegG}k
z{1OF)3XOn1lu@a<9S?=8ntFQQU(-}?Lf>^w_`4ugnrwO*S8J>TmC&!zG%f<Up;@Q}
zsnsO7fYfO&Y{RtO(!4<5RcO%EQQ=FYMol&FO`6{OFwv}Wy$yfwXm-#htyN>8H*K4S
zPaB$cjUBxdJ2a(K6W*yYF9hk*{77{u-I~llF{3@2Ro2^Z<E|zy4T|?P^ZU@+t6BFH
zOx)M3xCxj(%~!O(_G^B54UL1EI3b)F(R}y+y}YLCFX%ngq!gfUOygDtg>jAjznGv2
z&7$S7G^v^T27Qk-&&bg?r7?%0@v-I|`s(Qu&1>bf-=5aILi;j%t;=o@2W_VZ3?9)g
zqlyYgt*ZeVPTGBYF;HjizIvE<(O&QesH?W%I7aBEJxGh!QSAXWK;5-ztH60^%Zi}x
zrM1}%3*K7W2<Z7}%f1Bh)t>qd#812EIOX5{wJ8)G3DQo@gWcoW1GnM+32p6ekds=Q
zDWC;wx4D1|(XRUoCc?EM3Oz(<oqmTGk=h;#2}fxyg)n$Zi+_eZV^*~Gf)6lHYs+2$
z7o*)`fkLcy?g}WxX+;qLJEIl*(D^T3J7*yjQ?;X%6gjV*rf_qb)^`yU)3tg}^krzj
zwFg?JRuzi5$kH;3==ZFRDS}A0wo(AMbF`ujAi3Hj>p(7QU#3k!p7t4<%6x4W-N`7>
zKBiwnp|<#6fE8&cDRXAMq-7n0iDGTI3tBI0r)cRf(XONTXQ}qpRrDj*?#zN~SG4<S
zc`w&m)&izNJG>i`mD(?<2Jou3XcvZdO&k0ZK(A~4{LojW-JcCotv#?D7HYKREzrB6
z^$*7AYqjfM!8q%z+9g!IP_GpWfqhduZh)t^v{$lWzCr6x4}7Dxm(Dy*+I}jHYu5g^
z6N)X`B081b)~<OB^LMmgP@t(*YjA<3Htio&tJSWxr!Y*1_86T8JGFVq!0giMs8pp}
zdus}$M{7Mql^}Pu$I8Lp(+a3|s#m+k3;Or9JE#P|PpcuH`n4a)zzt~MyaUMx+C6>{
z8Psmw0J}rl!}TD;+RGGY9?>QVpfIX!eTc?~+7~H~F{V{fjo7$0=^V&}w&yw|C$$<Y
z)o(x6vT3{jM7w$s1~aXd{R|Cz9cL+I9CXv&AV+jh`am3Y;~fxj()~h<pR?}bPe60g
z<x>*HRX1Zc2I{8UN#C0~s@rY@5qF(+9TYrtG3#OBnC>k)fO+b^7D2&Fw>p!aKX2Wo
zZP4)1u^KSJzPc1zi~Mv>J2Bos-TRb=57KRNf=|bF`(J{>3Eg5U6hEoUje&_^-3GdT
z5uz)YiN;W!n#w!EbmN|A4A%uy@GC;svIJm}x|KhmFG`m(8-1sAKdqqWFItzcLFZ|m
z18sO?bQ~o>&*)~IfM~o<N$c`i-KQDwDM6=x52Hxb4Ua<PoNnLi7)6rq{kf1#)*YhK
zx)j~o!w^Z;HPM0Mysp0z>S?;lt>DsiUJ^)V=y*?K5;Aq|V|4z@(yi1(@q$j!iPmhL
z-2#Z_=nmHbJ6HG3EckR$w{Zg;&eQ!&Z_|9;tF#d-&<W_$SfMT?0In73p1%UUOS-k2
zV6a%XfnM~Nb&ubN!4lmL%6pXRlD`2;nQnOyyuYH`{sq*n<+=hdn6J<!Bmlco_f90Z
ztGdtbLG+qVL|gLfx(CkSs&wxihhnuZn=Xmh=zi;l!5cc}3s9)lCFek-PPg<K*sa%n
z_6o>N-5AA9Z|St&Kxxp`AArF|T^ZFUHR<Y}0a&wDw}&z%ExNns(Ry2Fa~o)PbX~Nq
zYt`+hC_|g>&E1%Uc3tJ0_)~W1y1#))r*7M3{Ly-J;q>_5)p<n1#68`5$_Vx9-dG6k
zzRr<$9ep~NRH*ms3TP`opxgQp^d9J5pfZ?2o%J|vsD^a?j&OKb_lUy2Bf7)1LXGOa
zq)^&JT~HuA9McUrfE(A%z5$;mbX9arnADZiHP1)7mOJ34bgi^lKh_DWA@W35xD3$K
zI<N0RZ1rcU7{^ZU;fz7p>&qk1=%9DAz6XOx^nH$C9raQwSas5$ItLhM{Y;AByXc##
z=Gavqd<W*;^s7$-=BQrs35dJ?k_uz;(09K9&|`Y78S0+;(d}@?OMm<)pm^(-SuhqK
z{lY;=`syvoX!O(X+6m5IzxDt5zW{ygOehBGo2Wc8NIyWn9oPRs>4Xz{x7T6*q`oW+
zjluc{$-oZL*HB?ns6HznBupQ<1Lni^ReA6?LeKdHBvOBc(%Dh^6pBZj*3XN9g&6(f
z15k+7|8@q@ar*rqQ~vLa{%<~H;`J*_;M7_Dymug)pm$mYE>WNT8eq=pyTYKDq>rWy
zOS1knE$Auw!OLh&)i+Q=>%6|I2wtS=|E16Lr0WMaqc216&&B97^;O@ZFH8Rt<qt0C
zTMoj*Z2jv3`u|5cdSAM8nyZg0h2lkh?qS%?)4!FCVdv|Y>Oczge|W>;Lj6ffrx)qv
zXMuf5KXV9@#rm;aG+x$!L=mPE{Uxd;DAhM?fWb2TAqq5I(d#IrRIb-i)T=^2ZxcwR
z{ur(2)~osq8)#h9fAj;`>-t&~V5;;_=&Dh*{`=LiTcf{4iP;<a7ldf6)$f@HQm3D$
zAVs~tI~fW$^=)2o^p<`l)o(WFf4T?KsOMAdQ<FZ>9TuAP(q)*77X7OiL2m1(5-}Hd
ztoqtO&{jSFQw*j<UrZaZPJN9BOmyj&bii)6KDrBBk3R4<NZ!@^QAYNjzH}=jd-Zqg
zK<?{b9Ke+H>4QIqPyKoqIvEe>w^Omk1O5AS+8EUTG6qM7^s~PJ*s$K4GUg+CYu{<O
zII4e*4nhz0IkZHK>HTd%#`W(~`ObuX<SUR#{hZ~1d8B_xuh=R59;)<ytY^;y%oBa)
ze{ghKf01@swgxe!pzI7iT`+HNSWOk54u*%HL+^;8fO5@_2J>H#bTYhVy$-w12K%*u
zaWR|;hoY+?I~1L6hCweV9yP?AL8H6jFN&Oa7!(wsI%fEEHxxV#Yw0$<mm!;y8s3J<
z6!_$0h@&^WuVK$6i1-<vnGZ03L$VQu0u29t3$Q@LJI|pp$dGx2&a}r3)(@a~!tk31
z96o7CUjwvYLm911A%@%=5D7Kxcm<$gh8FtVPNZQ$17M;I%gEnT20r}|V+<>3BNc1V
zQkid@K`(~CXAP_MnBN3L;!Nlz8eXS0EW>c{APi+1mV8C^FIk2?-^1Vq!;(r^$~Ih|
z3A7x82c42~4GnaJxoCKY^8R^-LP}ES8-}+-vcRxuHY^nyLe{}jk-;k;mM$5-ryO6g
z;Sp`%E*sX<ajL}d=RV9usiEW?M9K`OW<%tP!A(l{-^&dPDBM+HaG^r;O2Z!;VDPHp
ztR6Dg3@wvryl(hzE)=T_Z&Es-+OYO6+^;b_EPyjN48c@lQ)_UZ2b4NPB3(_aH+=gk
z$W6n$(NMT$ctM6CH5dZ^1!kk+dFpF2d|-xxwb{@}cXnC~o&F%V4e!4TgLe!M>Edpy
z;WIjEwi(oP=x8^LI0B}_u*VHBod%XKxGux9<v{B;)JK5pF{IJf`mW&vXQ13OgwX}q
zUPDqCxci3w*D+mvhJ%zq>o>Ug0dv4=@N0vM4-BWMerC`RNcF)(hLl|p9X2ed{p*O~
zJ^H_{qlRVlXMSjSX*STt47TyGG;Y{r18%~wmCF4l4I8X*=8@sh_aILU99pcW4LmzQ
z+Zs30KF-cqa0~NmZ@l9NLk>pk$VGT_#Q4k%7<4pVro*9=vHE*}IvWqZ4N({4y(Cz2
zHOAB1(9L)`5okw^shvP`Hy%nypNH}O6#9-CgXkdSY0RU|gO~BZyTJ4|R#L3q$LQz|
z&ewQ%89f!oa!L>T8@;S_zz#5ePsL?{M(b}7Jz+dgua1*OITbVp8$Y0WgAij{IQl}3
z-523un6Zw&9uRKKkwPTGXrwT8q_K-$%~8fzDI$H!_|_>n8g2BXFJzoHwj6<ajPcP5
z3@O&QJQ9*|#wSfwJ$uGD`UN`Ujj8mkoHfpV2hJoImwy86L}OF}`py}xBDkMq?0p3a
z$wqt1%B2`%kAO=x9?63<=Z&HBG3+$sH<jShjqCS7FT?2V>wbl8l@9_d$5>9kqg>->
zQxLppY@ncio-w2pjrqox>Fiu!R8j3hp)sD4VnxQE_5<XSvHerHTWp*t0Lo?K3va+c
ziLvSlye&1V^TCxFmr{uEim{Qhq~*qV3XN14FXlj`(zwY=FO{pt*XUyu*Noc^V|>?*
z6R%<_s*KG>45iw*;u&~RW31c_{Ts#wS{SS~swfv<XMCEf73z)AtI>GVSWbV4TShnf
zh(&|(FUoy38t3&uugUl%7bwj}egO=%7~hD7LaTA<fAq(0Gd9v5pxsz;14HXDuJML`
zr*TmgT<bDk+kw7r<I8UWrpMSMhyGoo-A6#XXViZT^<HCYBoyu&-<$!FKBF`JS^ABI
zl+qtC>SEFNz$l-EzCoi;8v2HeV}s}$HkQ`S#VR*qJP`}DQRBWDF!<1zMkTakMkW2p
zCykHP(0^ofrDM>P@z++sJT?X#h2#^Xycg!DjVHq~PqwD~ZV)@u$00CbZ(6Y&dJZN#
z+N2yY{r426%hB}BFzh;+GX4XYvq^y8fpwOP=|D2fyP66qc;sfXP*~uo>9-#t<8B&{
zh6xYT@MfSLGacUm;%TZLf{2%C21P2pO?72x^f4V;4u5@38C0v}XIeHBoWJRC0Qv$<
zsZ~%2G`Z566=eE~G9t%K`zax6Jz@IleXu7@GD_qIo2F=)3Ngjg>mbzh?GcbLlY$Oo
z;ilRDfr~ITBmz6q#JP&bC{x-GP&j4UO^MuS(|@$zJZ;LPY;=rik1s@GO+{T8V4UfF
zx^sEPw5b#%-sH6#(|p!ydgDE?38wQe13S^QrWN|<OdhlqPclW)Re@yFx>#VRn6gFz
zlWKZ{HWcSg9QqV#nn_7PvUHPA2ShSV6%$a;H0`I2VwUN9%7|Pr306Wc+q8j7VscE&
zi(oI;ROf}hizaLCF|-z#zN8a;p=q2>K1HUndC<RPV$Fk0v1u!n3tTq6-j2B}F`10$
zD>WIe0<_G;qHyaKQ#a+k%S~NWfKg#8r$VGk6YD>STs19t3*0r6o(J{oreEHHg(}nP
z4>5>p(-A9e8fr}5^k%+c+Wjs>YfUA|kf}30+W}H<>QZ5ZH%+@JbbZTYH9@h#w3yx)
zjV4FRAT^oh(2K6wq{={Fiz%C`)^3|3X^p>Qil^97t4Tzqdu=A0EAX)0)Ij0k4pYf_
z%CdHvesKfoG97GyVz+579g}-Z<0)|XuIbGr=-)FPR6(QHq@Z&C`=&2wAJu27qJO~J
zZ%Ru8_JHZwAMpNxiRA_|Xj(1?%8)7kBcKeMmeS4Z5!3TFFf?k)$%NiR(+AJeSN_LL
z+4krhH|?TL@Pw(2UL%vHKgKbpN2c04=$kUVO*z5Gru=^NJuywM0nD^XH3JH^=1=JF
zYiC|$1J2%jH3JF`W*LRPj+m?INp&>Owu3<z^GiB3x|)}K3=uc;;o2E^{*IcLIABiP
z&FL)w^)Pe319!~)*#?;RG>=o&s+V~u6`^^X7c2#ukNFQ18hy>bQOT2^`3Tj2_?u6z
z0|_v%q8LG-`PW{MAoG)6C>%Ez(5Cx@`8+LUC(R?9(HLyr69jwK5cBI)JsN73E8$d_
z`QlrE2{&hKfkuS+s|~OeY2H);pQ6k=qo9Av97NUE(dL8n^Ez!F$%kHyc?X3=W6hV{
z;C7t(CE7inF@H*5#fvx3prX68=F|4@DZyNyfT>J0huT8qoYlOl4T?$TFBSka+5FQX
zbf%aSDTAA8R!>0jym^>*)M@5(RO69uUQ3bw4D*{*4Vh{7p&Qg$=DzC~%mwrK1p2bg
z-t>OYF}oMT`&{#7KlEKRuWJWbo_Unc3i;+kZ^C?m+3JK1#;ig!_a$f)nct%`!zJ@Y
z9yE&0IUis!m(61O@9`z(L#r{EQu8MnP$)Ccr=RQ<^Fk_QDmQ<T0FerFu@2ldbCw$Z
zUN^5!hDeop>LIvlvuP1TYRso?Vc~{(&MT0tH7~MKxVO&yhzk1Z&9mq|ebd|)0mWP9
zDH3fkZ={O@jb`f*oM|%G%mvqMwo3<Ei`nrbh}<?ie*=^|=F^4fYc<EyQ`}~5q$jT3
zJXDDJ?J&=326U%6{&^VcGW$3~z1w_tF&%Dt%z8@c-!*?lvB`VpFKEBnYYzPz8u!iq
zIpF%tMO1s&Z!Q+Vivcr-ZlOOgKhi;c(Cm2yeM9B}3hoV?TWBd9F+ZZf?5H_D7Op)s
z2hdVDX8wg@-Q(tS?$Dbs-*}h4GB9Z#A>SUE)8@hal-Y+q?Dp9FBkc^Hn3?mzO`G*<
z_-$)RdjJ?aOXqjs>@BJE^Kh`d)(CRMlKle=I$GYM$#=3ed<ZX`Ew=Phbg^tZ0Sm5{
z<!d0~W?4_wFGnruOR37;-7@htG(0RBwCz1+X>f-@PfOMgfO=VG{{!M}iA;w<AIpdH
zpy+F9q~zsE%Popc1Y6cEfu#`3P#-LXT3+hGT!dNLen4ZmC6O*>L|8<BV!V+SHC<MY
zvfQJ?)G5oWHR!WOThe^d8Ef&G1^qb7jKz>SW3jlyZoK7WD@4y)>VE-Au#}DgJJGUs
z3miRXak>hTB+G@F@Hg2Kxf~?LGO-w-sg`GGyK&y~J?#wAEYHzaHr-N8Kkf`mQ!FfG
zT5>6rlV!F1=mhqHWdSXI*_M<7h~`)VsTeKK@>~xZ^DWa747<S6qXQ|lj2r_gviMNY
z_>$#|A^22m`B@B<%NAD(GnH6eDN9poNu}_8nI&;PChv-6)qUudTSn<FM1|!k3I$bK
ztXuM7;;N;Q?p0p1B*dZfx+RX{X;qfBR61B~v7w+yjb$Z$aHY<&z8Q`6|KsSo<Fc;4
zziDP>mSw}tEE{U2EqV6dduo0wt6z@NGDpKwGauOkqJXF@ML<AMK-svEsqBp`*(e|g
z$WZq0ed3?<y7!*<Ip^NzGtNEd+z)pDd<~WwyH+*;wRX!X7*c1~mk+)5b{&<F*<d%y
z0J&?&9>rLrT_2@Mn(P+PE!u1s^ciq1b_N?&y|&uDOuL#kJ1-7c+wHRLA*RDF`xB6R
zc6XXE(ffA80npoNw~5Mxy6m2(v~0Is0TrA)uzP{daP-)1*#MSayY`g;JhT%&kFh?x
zb5v{CZ<jv>y#sb5^q_cTH<zk82JL2Vq37g~-2y6s7`A(lwz(sA(pO;2W4o%iu(D%z
z(o|S6Zdc(0GGW(P4Na4F%c9Vlvb(nwOFC`0@+-9L8Shh>sslqsH3W_fZZGsYF@B{V
z-I?(gWwTruJ!NRQG92E+S{!D4lSHSy+!!mGpx2$Tg?8{BjOzp7Il`!*ZM`RBg8n<m
zQN~<KCm&;cngI1)j4Skx@@8~XEvOGePLA?%#v}z(d>Q%l$~eJzE(e__86y+Wdy4Ud
z4ioq>W>Mh5pRvakB!H3i8SSzI84lSH8pQbX351?zEN+CRGmL?^ASRgMn~T<2hA(a1
zLl}|dh=nr3>3R-h{Iv_MbBw2GI}^@$h%;leBN*~I&=kqI`Cq{aqlSEl3yj@#hhJoT
zPC>yK#;JA~8p|lBXpt?BF@yGBml*FYhNjDmZSMjf&-jVrv<VCaT~LXPS+rqGV&u`Y
zESa&Y4aTG}*p$dkWqe52Od6wO7dSH*nqjmu8Ts^N%3_RAv^JaZ6eS^Y82S65Fqe^h
z67buMU$mHRo{ce>2cCS!RoYP$FrwVSQ^?r12|UG&giMGjVXXKEW2FoorP0b5zp){$
zoKYDMO_hwd+%Q(fI7H9RYKGSdwC*sL{}*Fm9H8s5mSIOF<aLb2iD0Q`bWsUG17o@f
z>hCgao(#;Qkx{f9dYc%!2+XjVv6=P&EezKe!PClcuEWZ-F=o93d^=-h1%!4mo}&H1
zJw^weF1ydTO1@qvBi0Pk#c)^+nca*@dNe#>%$*Bd4`arB*xSpf%!P#y8N#p8*~b{O
zg`?TeI5z?^z;L8(@*{?T3-yBxWg%=DVlc?=Va8JwD;QyHA~)wT<JzY%ZH&=Ir)b9+
z!*pVGg7GZX(@!!UwxM&1ar^~vPBR9ns^6aZ`w}dI1M_2w^Efg??}9in8(*jQpEGmL
z%aG>EOs7(j!_0Y0px%w?MY&IRW&uSSJ(!6xVDV&blB0E$xi|@&$C#xQx$|OLy3y&)
z^wC175A$crLmg+nM;@3jGjAct3FeCwUOve@@e**Sm`jtu;>Vo-KHY!*%%scc4Pc%p
zCp?guZiTcUW<wLEeVUm?zS9}z1XXneGq2H$;4E|2PhbgQRu00ZQ0A}nh7V&tLs67-
z%(ru)Fr2xX!qO4U?ZqIG%yKDM&NKI{f`w7cFX{VG(acYAU;tTG=9*X0yvTG6!EYbK
ztd;{2%Uno-v^b`o+>J}jWFFKfFg;I$Gm%+I8{{PBTNDIMW(Kc>*(uCDlq5=JI#ZbT
z3e!X$$yH_=ef;nm^WS;kyw04ahvp4tKLze?GQYSBoGpWCJPV<j%x~z#To&`sRLn4&
zxiJYmxy=9b!JKX}ZB!C|o4IHgSn`+`Ujs0oIYtSY0%j7W(F&Pc|AD3==2!?=ikT&p
zSuA1BqC8_M^OtSVP{xe<Z_mT@iU6*HSu_`-D{agQdjC~16`km<W<KwSsoi0|^EMDQ
z%vuVo)iU=`n757@PFF%b)2Sb04a}GPA^R>ffG)O1<~PWg&2C~A(W9Z6`PndVEzE<z
zq1DO^_lNau%o*{3w=<)wU}y((#&1}sdraG>!O(l3$>V{ilbQ4dNEh<~eVL|*`5o1@
z_cD1@*7T4$G6_T<^M4eg>}Mvt2bKZmx3r-dWWM_va6`=c_t81b{9^%HBg{REVZ~$S
z>*s+RWq!T@V`I#~XF<l94J2iP`F}R5Ih<rZ{TawKbHRTJA=W;7=(T6H(pd@zR!SJ~
zj;vL?V1*Owd2&pgSz}%xF09%YAkCHaCM60Evz#cU=*EigL(83IsY1(x)x8TVdW1DX
zB_f`zd<uCVWmze0aE!&qKUl*J#Ol0+HSuO8u7(O9mW{HO$5~FNG3LusP^RDn>lrf?
zo@DK#0Qf1^;26aCu@oBt@Mk57VQ&CSHVD0ete1A96~wwqr75RbeA*43VfikA6~U~>
zUjcWP_46B$62i)BCjT>(RZmgDaMm=P{fc1ylmuWTYZnEw&$HHj0elqeLwXNIvzBVm
zd4Uxq2Ox%(@IP?IvXbdoSR5<#CiGrn1yI85GK;eUo$;(;ax4;9FMWuyB-Sz(0Ld&b
z+F_=!j;7I9u2Na+`|w+&u_~jX=?ZJN5acSWDg%pfjrG^xnA3HZ(F?5`tlM|cN@tDV
z0U(1Vx`ma=WCaGHmBo7D2as%*FXeo4SR++Xk;_^^m&YxZ?pauo$J)V!=zLaDAXo}m
zKfVXJt&lbGGK3bfoK8YTF)N@Oz!H{_Oe|wL)6Z4T;xHhlf;BG_h)UK_3&yHgi8UCj
zW<5(4S9e(K9U!%=o30>rtbfy>qMp@3rvVyROQ@3PE^8<goz1L-&!Mk{wa*d4T5T-9
zm#{Q#tb`q4ZD(Dgs*Vm;IX&g?vDVYBtdkWS0z?<9g!Y}?tYx&zdBAd{ol_5MM=gx$
zWkoLq%R`nA`2zi{nX}P3z=~}F=Ob46n~*ukTJ8?`5bN9hXbrPoafj#;maWtcVji=m
zgQ5Nj>w|C68f86y95#)yzM%6V6RgCQ5Hrd8>m&@GV!hdb8BVioKSRYKcEL1Q?AaO$
z1Uj&jdEj(npVL8@GdpPm#$4F1{04w4+miwUhuJ^=4AE}v|50+uo&ANa4GNF2V;7_8
z$<CzW{-f-_>Da_E_8Kal^I~73{jN8A;{gDD*uP0YeA(GwVeACkc@F?5*>SX2I>p|y
z0>qC!>l4TfWEW8VVi0=<74V*BZ;VIl47;}-tzh=UOjv)GEuKeF`4ILM+C7J{AN>xV
zbL`i@2TwSAlwzb2?3`E78OaVgfzI=6Kbn0M`*+$ATwteofaN0FEghXP?DA-I#<C+Q
zJQv5dy@b{!wpTF5F0)rULSa1n>=uv&ww`X^MD{JqOx%A-><lKvq_BT~3g)M>*HHK<
zjV+srSzKX1N5v9X+4Ge6xvsH)z`?B9*V%LFB28z9(mw1ayH*0u4EED0kdnz}(>p4Q
zed`0Xvf1@Eu;j4SloP+j-cD)R+iWND==0bU*z4dcA8gh>3>L60U*T6PWG8dLQ^cO@
z3{t{=iJY}kb|iVhW$a%m8dJ``PmWjx+ie?GrkXt=#tiSUi{FH4HSCBHu+*~s>H)7~
zOAev4p8e5mur#p8oIo1cnq-hBb^<Mst(pBo3k+^yZ!|%DE4ySjWVf-u;{)H$KKBS?
z_t@cd``>5BWuw)}KJbuk2X_BBWOuWt8ldn2`vN6td)UwP1J}#GOU~>=_QDLb`q<kk
z^w7`#f?idR*ca&`GRTg;0hS>f+w~yK7-m1e7P3d!FOEaZV|L9N3_f9}yadD;`_q>&
z(Q)>BGr&2)Uhpe8C)qDi8heT@s>Rqe+j$j!kwcut`#~HyztMiikuyN`S5BM{$=Pz|
z{6fF03+GjGfm}H|dx1O5vF-i>tnQqzC>!p<S+xWzj&L|s>hH<%2m;ShP8RJUyg3`c
z1o7eg@-$eEbJ)KE;LCaYS=f7mvzb0Zagviq|C9X`XI%v>^yd^^K`VgMCIcXlGm?vG
z2XSi26*<lMgazCgPJ@lSv|vtoIuwR*&MrZ3C@1_kw8A)-pNDDZIA3gs72%u)D*le(
zjC*4;k(|#dQ+}SaKMEv@v!9+?(VTJ04qf1cP~m<I$M_)@D3-IT6}UK#GzIov;-u2v
z{W9l|A2AlsF;!4tJArfH22><*yz)SjIp<Pga0+LXvNfrku=TJzjkA3coYy$BUIFkr
zCuT1c-r&sg2OyoZpU6#41Z{~kIA$NH&*WTiL}xZ9rWWuVPT4`Uayic@K>aPwo97_x
zHs`%f^p&eTjtjXt`5fUWSPMB0^j0h4tfh+BVrW9EgrgTjb}1)(7COr~1;3!PoO4hM
zD=Ik8QPoZ*=XZ*4S8@DlPg>0hegf-jID_N~)pCw~1od^CBojL8Is0})SOcdA-iB@V
zT~0ThT5RN`{e;10j@=osws4mAfwXcmhoPyB^Y&Yi-OkxZmFV|5>MvnvCuepLI=eWX
z*?@O*>dDi6!111mRu88}4VGTc6vf5+IP%+Q^>e~jfDCZfG(hwtj+rVpY=fMwuS3ib
z=PNDn!<>_pHhj$4POqFNoEP&UZIojwz_iCWpM_%e#yR^adNsk>T8?Q?a@J7DV~UeQ
z>APvpC$!v$xa;V$wC64m0O!cvM`a*R+!v+*aOPS>fV*(L=!NNO<NkaYLJxC`FM`L7
z8%vQb53bJ|@EqY@rpj<nuIeMO9Od4io#HX>{a?W1!}W<o>o|8d)u8%v-KdD>1lL5n
zjg#DG*J3WGxOeAcE`D6E2hbG2?V!r1K<<M3zy)!$sH*-n*S3J3)@QhfD)5s8bG@jd
z=PbA87!aY{JM=yX<K7(w;v9F1-n8M|uPCS!!JT*q_(<;G^s({t+&c2bqqqa*07P?t
z2>|B>?#dT2c9HuJ1qoxhe<lJD$1NU%hD+R)I&fa*{%m^<Jn`HgsIWYNn@6$!MDEOg
zAuX9(wHZs2!cA%hN#(Bm4u~}Fjbq@v!kx_p?mBk`1xIdhKfMi>bnd__nD0%l0|m`8
zxc^f6JCob86*9B9bt^HYY;FQ=dvmxSok!;_?xH#L{=3cHE{BPE+{MRXcRp9N3Oohe
zAQog7ahEO!u$Vik$5;v1g>L^cZUVjb%ehafu@)8F9NNxRa$D$$TE%_z8Avs^fl2}H
zaF@`Ix|aJIxfylbpUZ%&=jM)KtbuE7p#9%nZp;V}jokV4plafNiEY{J7Vfgyklo7N
zOsAyVxW8ToqMdt~!p$9AIc3W4arb=;3%j@*s$hLLH&FuefV;dAxE}6Ia^8En>*&UL
z$W66?vyc19LkR2VW>f5KfNNS${^ua~A>yF3hq%63FmaeGpjg%jcO_-#9&;C`L(C{Q
zdK9fO?h87Qac*D_Iw!dY=rq9;_jS4ur@6Pj!Pp_*7}ZnQ^Tx^RaNtGvqUFd-poE1p
z?{p40U3lM636Cpp@f-kbhk0|Tn#7H_<rbv5^Ey4S2p+tv^a%IlT~>hgDDT5aj2+`G
zrnkQr?*cuuy?G0t!I%&4%&QP{g16a*)=AzU-(#Yuc&)#o<;Po2KB7PGS0(@fyn;Bi
z0(oW%QUvkx(_qYL8?T+dOCHP<xPhGI&3X&cLU`d8@PzUV^jr?({gjQx59j$)*f@e`
z+ypBkc^y<Q8pYeR5HpPC?RXyW3%moKF#94eo1C;5-dB`4i{(9L0v^XR3nB9|Px3dU
z#Pj&eKoWR1dpf$A$lFf0Y7(zyK1@vJ4Q@tf3a>XF*F_p{`&{6!@VXL#zsmEVGr-q)
z>+XW{I<J<E&KtZPCm=0@_ly8iGI@QafM@a6GSSNBT|EGJ4zKSTNG|WpOxSyi7e;yT
z+q@K81bFgz#dOK%^D5{Y!UepY4=`BBo1in(MZ6%YrzqylpyMeeynp=BD&;+F04d{r
z^52On-b*?dQ^9jx3qU3BxpN>@y!}~_Qp2m-iAmJ*9@4(Pju-VSIO}=O)8aMonnG<*
zf0ws~Dj^zq8)l%@#5+gts%GA26g6w%ouzPBE06a)@NK+}bVQ+@=ja959lQ+`%)Q6^
z;X3AYpLd*&_;m8Zc3?@mc*EC$>*gs=!I%d;6`lI+;f2%f(8v3I6|Cszm7k&a-vIB$
z3E&^`ez^m^gFFR={D*kkKZJ^5o@Nz<j_~6Dg3!mj>*R4h;iXa{dX(2pwOwPpJvU*+
zIL~haofEuW$q+Wl+h73a6mQ?(Xif8;rbRf!A6gEX_Wbwn0q4M<KS*C0aO4luF4l#A
zgS;JA{+xGV@L~R6RPW-(_d5dF?tHcw#Do9GJj~(<{{>R$$v;#Aa+DwOE>s-j$J5p6
z#h*QnP9Od&WXy5CBSn;b`Gx`DPViULsfm;PSbCeC;>RBWvH9^op;)6ozm~k60DeEk
zz61F#ei#hmpIQiVhA;KQvIX;Z&_4MrUriod2>-bh;6nL3sL&;h|7tNh&+(grp*Ngg
z_6;~A_&c&7Gm`IIkFoRo*8c;E=Er;kD=zT=CV%Rpjc+P}Z87{$jL;OzSIz{9;~%B}
zX>^IdmwvU&d?w}E;`zND=uF_d(7B;RzLYMn6n<X=NGiYKO|Yc#S8ahYSNQ!;Fzu`S
z)pS8z<0Bo0TZJF86~^4)>nTf>&euH)^*8ypP4ptk;Ln)?YZib1pRhZd-%FpQ$>Dob
z<}R1d^Tb4N@kj3gahw0iTOfJ-XaB%N^Z83Y2B3i7Lxl!~{LQf#E8=(kw|C&D4#WCV
z{_oq-S;p^q12&cOV+w$);8)UjsVe!Ewm+bvihnyE3aj~FQ1<f<-=hvfYxqh32cBAf
zHn}<V{2%Fqoelget>C=NKT20%BmdJJw3_%q2SA$nB@EzN`1^F=Y~}w$JL)$6910S)
z^M9gOWCwpag=RbXUuR=VU3|A0HVk(2!$v_K@Yhq~y@&6+5Tuv?_Cpx_kk8!(U>`p?
z3W$FG()aNj4DjEi1i~YJMmac#_>12J%P{|s64*P!pCN*Z$9&CY$b7<|bp*zY@*5Q(
zWBehC{EzefUxBa*{)cf?|1!ysuf^aLzw-x>LxNKqAlqKB_9w792!34(p^k!Rs+@8X
zJZV77S>PWC;v#s7Dpp(txpXGsuwaVT$xU$mGst!qe3=NABZ77GB=!`1mjh#t3S83A
zc}(CD4S<)x1J|Q%wznXL?sOl4V;tstTyW&SjfLQ6DG(<Fb0|7^QXpLoG5!L_<7fp4
z*w10Ufr4Q<)CUQ^ru@NaK{REe&Ip#h1haz$ZS)d9E0}u`nnDCzdftQzGAJPxCb%~O
z&TzpOv`Ml>2)<ee)<^-f0KoHth2KI&l;8{{E}{j`>;}0Y=<b6t7X=X$K*R_}z6FUD
z?0yZnI6)P?xGoE}l%o|dxH}Dag5V6j+!6(9f9OpT2&s-FSx`ma+DZ}Zm<{!*0tX>x
zon{mGMM3rz!7{3ky(;*XHlx=CBb1G}A^0E$n$iU)T0w3KwvscPA;|a_BvWvkBKTQ?
zSMNYYwqV{dkQ_nsPT+C{C+T5uOOQ=Rkn;sA$@?x46tn<PDCm3&oJE3{yTDQ`u;tK8
zszhMh0c%PHwm-mACYT)sG35ehDtN9Cd_Yb>rJ%bPoYjIpN6he!Kx~Jx8o{hM$gUL(
z&}*emVEPk6>jg^#!Py|_He*Ha3Kr5Pwo%aY4**Sq3-mm17Mx22ORE4?mY{8dGc^FV
z3zG9O*dfry0C-OjOm4${!TpEm>=dl?ho&yUm*g&V3r0}8G5dkw`x#*A5zIdTmWKkT
zRbc58Joo~d`UOkrqbLJ{k7yhBNO0dCWKf{^4uB!SvNYH<Ea+{e`)@?>%eTNk7IZiR
z@k9`12leBE0@}Mw2=3D_GAUR_QT8dpidL{p3l7rvCJqVrY=lC4;j%uAISBhBK^%ow
z{sr7gc*+-WXW{E#VntnrA5v29u+Wzh{cge@x?$age)d%5?jaof0M;B4I#IUQQ<(fS
zgdP>X&csBI3BRU*x|h&K-(U9@iYW|pT=)eYv+@<Lw?M@S;r#^QP6|`<(0NL@>nGUj
zC;aGXwETtNkir0A_yynsh0g7e86@P;R}D@JJ<pK;87%xh6b7Fa_DHcbA;LT%TA@NF
zWt75%vMQ)JCmfE1ig4kwcyvYxhv*p?DRjP$Ih_~wQ9M3M_&U9@E()K1A9`biFFX&<
zSfRr|m}s2v2JLw+34bI{^RiG$oA!9&L=AAZ1fgXQR3r*zQD`O!XO*LsEUYgEB31Yz
zZ9&q6#ypTK!VY>STopb?#i!SVkH5p5t_zv@(0fDZBg9y`@E`>lZwf<~z_bjZisFHp
zLRZ@JWDB=Y#vn&HNp<+S!p1*9ZrOy1lv}(l{FYw(dBUk1z~>9U@&mp=ShESFQ26Rk
zU@a1cEyA3Ng}hv-FBN`07xtD36R7&2Txg@*M1^qn6WCNKRK`PQm9RttQZ0N@3n_Pm
z8=WA!MtCX^ty*DN1B|H?+Mdw=(Yh;)9f66B!YkyBHVNlbO<k*S2OZ^a6CQXUvu_uE
zKx^3}eAOEYdxc8cT|E@On+m;s!atfp`h}B5kOASR<QF{>Hbz6mpzvR+%o`HEufha}
zg}*sq5+lOb_oDS!*k+@6#uK5IrZy^!q>cTUaC9f|<HBnC_Qr(JV+Qn23b#>)a!U9N
zeO7B)xO*u&4~eq217I&Q?E<HR=v)q_<|rDZ(o`qW-i4U2vuHhK<y=JH3osW~(NlCV
z@v!JaDl~NyS(r9Zcae$#pob`kK683RR8IMKPf<Ee^r&bVWg3r(`i?@Omq<=ITyN30
z;pp@cb)P`%xG3aHjQNW0(5jsfEqongCq*Bv!{VP39lZc4ej*1gI{ih*=?xtqI!wQE
zpeS-C)t?24c3y^<)1r@eK+GA@bP;ABEE=I)`B_m%KUhOV)j8-46+I+JIZPDr0fe3t
z?WU7L;iBdsz#~LoZvkhdXnYtf=SABVV@aY!Pk#gwEt+k@lrD(c{sqfLk;(_tjS<z=
zk^dPhav&!>PW0jDV7(+7qD$bisBQ%m#)~#`z?vYc`xYt^MfriSDM{o*iHBs-=xvOp
zh~7^?XR7EgDmzFMG1Fk$6;awx09+M4vlE>+L`hT^oGuEr2kxfm%p{D-5DBS<!Imj9
zT>?**Xpa(u*`nv7fX@;An~uR;k>FF<bW8Lbd49J=eiYoy6P=@HZ@%arRs9u+yy;>q
z6wO-<c#$aSF7y_QPVNApMD&pZNU6w$c8X=9EV}>7MUVLCtPq_Ehv-V1sGKr1Rib~s
zhZWVL7iR!}NA!0mI%`C|7tmQN>XrggC;DF_#MFxvba^$1<ipT=SCqOALK{VCRCe7Y
zy2ykT%_3zTq_l|YTcDy<wCQ)W+C<G1kZTw9({go)taN$Y6WPL~7`!iXqwlA5ie~-<
zF<qj?Z=$nX^a8!GABbM)fWjWp7Akz{6;;R~=Ao!{KaA-Uz48TG{i3^9z%n38uLtgt
zsALGOLD62yP7jGZvcWPe3aEkJ5mC~gu<)^{sS+$tL<u$uR*Z_~%fK@xs-OhVxF~Nn
zrad9Lc?mp|BLDNSVoKCUd#!2FF)A}ZBrZ7%fW3H)7g!v`XDD6jC@!SZIwx_+GRSlm
zYbbQ!BEC+QP_E)ThhW-a@mrK^auaLMqvbAcF;V=*Lma08IU)|H;t5Z2jwdYj5-%cu
z!CQQJ5}iKcDLU(NT>LTBn)r$}l*~LKzAJ;6lj1^8u$&V6(8uQd#7$X%`-^S#?Y02%
zpH%!1D0U+sFG&0bl?R^|yU@GsjQE2zy8nX34FRzGta!fyLPNwqzlGU{ialDPFif05
zVfl07>v3QS7i(66B|;qWJxHW@^Ru`F&WqoE9)?DVowk89T6~70UKhkB4aP2tUz&qO
zh!KaofhAVF=NejZ;&?OQm&D&crmuWl77x#b?0B(>+`<I0|8Hm|ijyclkR*1ctxvLe
z6CD&x5uYQQQpI)@#Z41e(#eV|Vz0RvyDF}yBA{#HxfH9vF3!<_<%W2YqU`D759z6w
zDHewUkR|?W0Beyg_EuwMY&l|gsu;}`@7o61x5QR@Xx|opPQ{&h;>Xv3&lktI0aze5
z-T|;se1gI-MdEsT85fH^Yp|px;ulTmEEVTJi_S7}%tF8`#WpEOm3R?F9;?MOI56~%
z_<1T2su8cd3eH-a`1jS2T_?Uwo0fX9J=J(Nh?mMScvn0~HAs!(<K!bYiD%$%cC+}E
z|AD1N{Bi(Vt>VIGLE6Oj^by{6@h=pF>JYoqMSf4b`4Px{vClUkonj9vzU>mbQaNR}
z_!~<9KM>mlwV*xXd?WC^;;yG)=|i#Wm(bfM&ZSDXe(?l-I&wh#<7JFJ68E%#b5Q&y
zrL2d<8IkB57I)MC3>Xn_jR1Kp?qa~EC*sw7v_{3B@*!nR%%QIdjf+2<12Q50<p^X>
zii2!7G0`dU^XtJgE$%r6+YU)y-wWCHlI8cn>L6LR1k2_qX}AxBlO&VghRzZhT_r9O
z<I5Oxl?0EW^RQ%c6BN2hmM_D6-6gGm!3qz_b30+-5y{iH0QZ#q<b#<Vm4uLcbWAdo
z{$KuG(nR&l-jc-Y81#{RNGZGHk`+ow^Oek}6z~bj&W|y6Qqtgo&Qp@F>5b<nk&_sI
z$p?3!DL^9I1<pW;6Xnr@BpZH&6{jWcePB5wiLQgpV99B!X*(-<KMy2C@|ib%<tkL-
zN`-b|lB$isM@TB^VGt=PpoGbJ$u+tGq9p4>Av9W&z(D5(NzgcqxhR=M)o3x2HVIm>
zl9%YvRh%U1Iyx^&GOcJ`mN-+GI$rXJ5mFK)zO*4pl>B-WQj#Pb#DZ<JlO=D{vo}Q&
zOZ&J~$qTgKO_RJk8;C2C)~_Mvs-&D!eb*#GqtJ9+GMn~~Hzaloz?m-53(&eL`G}&L
z8Iop4Of*yCZ~`PtlDh|@vn7!M5SAn9JOI;jCB}cSB)24Ae1$RFZOLwmDdkC=H$X+c
zWdG}sRv-zlLaR`+Ck?G4NoOBq7fUwLI+sY2(;%%>^8I<JD3fes!R&I$)gVl*LSlA<
zg_V-aZ$nd+WRQI68cA9%;I$I@d5}8EbBBSemn_?gu?CxD3suA2l@!u5rBPCF6Ff~4
zKYHOdOF~zJwMC-44l7zEZv;a{n`Frb0NW+I=@r`{xqA*a-ID~bM(2IWW&ud2<T?e^
zx+EQD$n2IZnL_J<#DV@lOpoMhI5hN1KBDg>J(SoM(%Yp^a)?fd^h*ZGg&L5!yaDqc
zN%F~;7?j*khu$Gc2!%|BC2Y#!j!1&2s_e1k|ENsqiG){=H5`>(I0e9%#P>anjY|f|
zd7qH*DK0Q65f=hCCE2nS!los1DvmxRU1{TE&|Z4~G!PEb<&<i7l)l`CK__YGSCHl`
zok{=a%tgwhM5U{A_c8zuOOM+@ubXtuKVWf}?wN%J@{romOXi5wX$6FNN{gv@;iy!i
z2JV<NvjLr6()uP?;Vs?52B(iSGtCBiTzZJE2w!O~Rpg(L?pK4Hln(8Hrc=@g%4_*a
z|K0{M{?dGMWdfwZ^tcO@u6PQj1xXXiA?37`^8gCZNW1T$Ggun-DsX3|w)3zsMEXS+
zTA|X_&X5u&?e|6Nob=p&`pQnYH2MdqkC1*(*?~xDybmT5E!{z(v<p%(MPn{Xe{Y8Q
zG13MKLd8m>s0=1f`o>C-OVV$tUgxs3jc)jOsZs!vAk7X3E>T)fN#7*t!I>b*(rbrc
zT8cDrJq%5iKK(Pj|I(y|TOs?3l)oQhu1c40hl*>`edL*6mrmb+iW^cl3M-~dn<<WR
zQ#!v1Dl()`Zh~Y=e<a@}OFDZIRAfsv^tFu~>07iUxl;EmXu2g`Ob@TyQau|idD1FB
zEJ?m}wGqbH3Z&9^ps-Nt%EKZQN$X3XqFDM1xlkq2N_W^)D$RNy(#oXQ=wN@jG>z{2
z3TbILG*wEka3Qoxnon7QYUu@f8Q+oW=qjm^zTO4STIptT0ve>@Ds<kJ+EYD9qx1&V
zy)@aRos{}&mOgm}y)DwwAxx%Kx@!c+v`NJUFtJ^_f_%LW=~>!M-jn`D&enbD|Hvip
zl$LqG&@Sl^)o6B0z3)KN18MYKkRItyci?)ZUy~d9P`d0AH1tUqQ*BwlH0d+gJ0P{~
zorH=<(qJ~E4N9M)JnfM58Wr{qOJ8^wV<Xa^C^Y+6x;+VcpGbeku3`45^n^FY#-!1|
zqjOxkxCfmRQpFhHlhSXg$Z|^BL6ex4w);TgAz5QLh`sD6xq}X}^R$_Cl;znzfZa~A
zy02iHv+P3(&bY{~(#FD7mPId;!?IIU^6V!2hKhdOWe$HrsE2F|{V+#mF_iB-CVO@d
ztniXG#sTgvb7@7VkF5P!EZ1?F$3=Ad%F^g-3@2nyF97bOEd6JQJ|)}#58Z!$vM*O)
z&|mhX5-I{@2AXJ~Ec|b@f@J$?FMV3p_#@_fR#r$yGeTrnXs;A1dy@msFd6?v%;}tL
zCdDekWvkCZW`wNO5h@~OTaSXAmkG{6Sd{F`86eTJwR9@sf^5ll%Ku%Il~G1FMt1!q
z24iKd&tUd(GTzUSc1iZK0J1O3e*7FP@v?Pq0+=9MI{}*#W%hK<CCMHfgfYo7=Wt9d
zMHciFI#Xp&<v>`P%#-SUuE@$;fV(PF&xf#UvM2P+y)KJp)BEp+>{umu(q+z6H*iz-
z>JIQ^$kOP#%9Q1Y0GK6PM$emU*-3hm=g2(AVPURp8I>pAlIf^4^|mZ}8YEAawHIdR
z%f1x=P#|N{cB)VoPNx!zWbajAtXL*^4fdAE=1f6@txUFzJ^)rOOPK{yA^TK;!AjZU
zuVGA;Z2C3uRLkDfW4?D}?v$CSk<F%w*2?aeL0X+`%o8f=Wnq*uYmkjo;PbAmg>a3s
zmN~GZNftR5W;e^~DGt&mOQeKuyX;l^sz`@Tc4#qr@5yY=z~7f;`$1@@><fD6cF7);
zp|e}|fF2(YWVt6`T953M9j4tY^ZNiS4`uI)(CU-b9sx_g%;9Ya8<2h60x6GVuTnMW
zpo}#aQif!|aM3v|Q?3ARM0WN(0FPz1%@p!@BHJ?oGAeufLky0|8YsFkF8gLJq)o_H
zdw@*JMhc;6O7_Dkm_IFZcY@GEa^DFMd$~XDfE?sm<d`_hou>eBlB>x*a+W_?1eq@K
zCCM0bmCybFq7Tcrw}Hh?zSKr(Q+IjDQm}f+53GlZBl5je%<3uMSO}h@^2e8eKPGRf
z2aA`yY%u`d@~7Xzn2&tXMa=NHeDOIDUwKhF$O-ul+7X<T|8ouVJte;uiJAGyFYkeR
zf4OxU!UE(jw7UtEpZkd7pF#3X5g0rzf9q4IKO--q>aJk<Q`rEXmCvJReu#W2#q~nv
zt<~TRlYdW1jdODQhfo+U-|Y)PgnS|Gc_QWR^qs@=a_4UVh?2L`J2hHf&4cw9<es!?
zzbKy>2$?bRxMBLrK&;$33C%cpdnm{yxm!GBUzUG!4VvQRybHi5$h#>snkc_T$;c%6
zf|+O~%QsTJYKr``n;@z3^PLz=lPjs{@QPg22u)YzB|=znO@3e<)L)mUQjq<I{NgFV
z)8%O>xw6f^DKBsUYlggLFU-%BJJZFQBOjrFdanEz6*_Op7as)TwtR^ZD)Qt_r!bZ;
zf2IOs1@i5V7%P;^>M>R%KXwLV#qy$DXeyEO58!7imDkWVu1vn$1&Ye$&z6Ez$agw`
z(^e_}ssZ>a`CtYR)$*JnsJ|nBhE507$oKZc?pk@$TC8)O{NFK*)yt2327H73Fzwdw
z%6q@YSfkvVyyqslG!wXH`64BZX_2d5g3MNVGi|5Z<Wp<F*)Bgf0KFaZjUiaydp7wC
zR9$&rUi2ZX=#=+Ofu~EJ;|rc{xuyz2AISfp7+Q}!_P-lX?td6859KSVs-;h!K!LG-
zc`1D%X+T~|7t$m75_-uD%3b4O%#eH;osb%q$8APyMBYK=O^@X_sNnjE+;)h{Lq_Fa
zO~K$X`NMul8<&Ss(0oGvI_>`^<zn(BrsN%qAaq*(r4YbFinDVe)LvnrU8sX1r583i
zDufB>bW(WOqvfpFzaBUjMK5iMT@^`tu?UA1MtbeLDc+zDaJehi*-Fvtp&0%M<cLDM
z5O`0;6zw*SDt0x2=a}NoSLpOoT>A-ny%oiO!F(S@-4c-Fifa?#^i}x2iLsN4F}gWU
zDb~LTv;7ofAA$HQyciH2poq8z5~$d}0-ZsM->78kwBqeU6n{CR_?uqz!HO--&~#RD
z^*mZ33iVQuP(=~N8p9M>RNZw>@%0x_5w0+k_Z^`K+z-8xiX?Jh&nsdSSiC5OT8?Q)
zE2fuX?1ExF?Mp5yS~9>AqY&q!6{~oN%=hd#MZs%y|6Nj4P&)6jVhcTe;uX)dVlY9m
zfdjpXijOGZnxxqBBU;Id&9u2oQ8>|4K2`A>m6oR|l=NRTuP822RoPXA!U3Gu6weHS
z^SWXi?Za*;dML7+uIM_7)=h<$=9!_`g|aIAmv6;wO5SEE=F{nqY=vzOOw3XEQ@|%z
z5lGSbTMEhBK-^YbH~^M>MOPnG6ev9D1}aooD3M*HI9CNgvBH=3JSB>%G$<@p^ta(>
zDpTmF7NK16@7riqDArTXxKd$9+XP#cqVfVPtyat(fE9NXE*uQjC_bNtm|BGsomi?<
z%wGypuQ>BJ5Df}TAT-@onDxLlDptOOX*VeXDWcY_DEk_wwJ3(@G+(RYr&{3J6e+Zq
zZC9M8+;4|s2JKnyDNK~3yKhs7CLyg;VX1+%F2(;*K~=XRhzg<}D88o@RF8sN3eu~1
zh9cn)6^Zo2_9;wjprT*VMCaEB6y2X<EgmU$Qz&at5pWAO4Jn+z0$^CN{ssUeiuK{p
z`&f}N4bCTu=jnbQRoM2Gpm$8MioEx6#moE9JE3Ua2rDKPy?=pqN)eL*mT5%~1vd{V
zKcH8Yz4F>l5GSSizfx;ukUtc<C~yA?;;Ou-06DB&wF1OV=|#Ipcjag-?DbIk&?$@~
z${4C>@Kipq(LVt_s_a|<g~yaxw9ocZzF7+5tz2{pJU+^gkDzs2xt-iPU*+0)F!Y47
zi(Y3Zl{Zg-<&^T3OBnN0ZaR)me`P@_SOS!;RD&C+e5wE>NU1*#D^4pbHe&3IauK;e
z!ODmM8wSrRD=51bqKqV0HB>o&FQkPjKU#^kIH%nB3`n^0e-!?SP%fayU8M4vkAXk0
zjQ$ZnY?QK70urs<{4U4^<-w!S6syd67gFMspML<rC8hFRbY50IrrSSW`4(*q5|kfL
zk^h;f{6+)2la$d^tCFnT6$g@{bfT*)RoM{=o6?j=-vIuKa@}qKuPTiUkZZ~}X=Se~
zKcPp`4Q2f#I@6WOu9)FXC7;TnGn8p`r)Mg2z648_a$YQ0vX#E^ShXDG7t!>Ut6U{_
z2~^xtCQ&8EZDpK2T6xOvzXLE|dAACP0_BTzix(;vn!r+|EPWj+ij{>du#_l&w8w8(
zs{C~i#>$j)k6|w5%D2N{eTDMKd307PTj?2CrTljlq*N=%S7Gdq(uJZiwi;zNy`5^6
zA-AzKbxICp$?BEID9YEM<Tr!ot}>cZ6^+XGydkYg`I{>M&C0cFz}cdF`6^gim20f%
zY*Q*||JSbEOof3R%GOgD>r}R;fU`?!vSPWql@DlrA1JqYf%MpvWjjH8l?p2Mc&PNF
z+o@04PBqs3%499bfO0=oA3RdBN+EPmxotU28&a~b0ynH2egM-(l<OXXJXXF#kFqC9
zxBXB!s(fbwSjLoz10dtdRcwq+D7Se*%B0dtzt)t}mVN?8O)Fn!1Aj=BPz)Y>)z{Bq
zfgM!G={ImxZFmvtom5LGVdAWEqF=;CRY=vZt|~(nWFJ-;$ais5MLq+#yDF86Iz3d&
zebG9i3gcr*JXM?NQ0`Hc8#&R(RIid-<)_NForGS0RqWFs0V>w7U=37hXg3+8(rtxl
zr&T{u$m5La6AIr3s~qX6cUBep6IvlEJId&Wsv5kZK1}sAr5MktX14<nt|}RZ%m~$o
zKVmFWl@f<ZoL5y*S#p#roT{XvRgyb4SaU&@eF)^DYQ-)fVpPvkxH(p}@MV}7r*ilj
z<dW*a-%xm2wec6U;#DOg;1g8y$g@aPeM40bNvdKhe@j-eX=9M0`rsf)s;cl3SkhE!
zpJFaoRNo(lhO4Tbb3m@C;#W}p%XQVd|AYD)sx}JRrK^s6;>WwGGCd8287e1o#IjWv
zn2?sE`pzGnxvJyjTHjJ_rqh78RYN-g&r{tyfU$hl=Nd>UP%Yhru|iccIiAI;tt_yV
zsD8Z<T&e0CI-6UjdNFSX?!R(XBptA<P*p!hZ>35yipf-|KBrRnYSkNOLGGw7v7o+2
zRr@|zYE`ouAhb@k`vNZ6dR0U!rrn_Gqdj<&N>0z^X4PUHNUQ2-Cg5$Vlr1o(UG>s1
zSUOZSl(4_2GOmNYw)-mQs}R$vTD=*1yHvk?32EJ`BUBvoKs9m^ruC@a*#+}^RRgEN
z@=(=GWiWlJ7aAb6Uv;0J2?MI0Zm>L3Inf0?s4~2X){tt=SqK|e9m)Y2Q7Pj=9;@D(
z0ew$YCut)zYE!KsXKPH=*#X43sw)RVCsZPegG{Qls~~$ywOoj0n^t{6nFD+Ev*cAe
zs5gd!(@~vEfj}4aOJNvuRd2eDsU23gJHrY$wKoNG+|_s1L6e92C;HOFQFUA)0LRn|
z=zy`8+ID0Mc#f<6sF=W4&BzDO33a&?t&?gk{f4L1epO)gQ&+x@CG}S`=#Wo<+Dw;M
zp!x*WlLV<9DOGS<9Yx>YJEPW@f+bj;N@>fp>a9L#g{akAAth9u{urEL>K8u({G2+`
zb{{lctuDa~Bh*g^V=z*EkY3;C)fI9`i&8KB17p!@A*H-8sEhtfA*-EtLt2dbE2^}K
zRd0`iX>sbJB{1fadNp0^m(`tgr^c&yP|`L*owyCHMD;v+V<oBI>4E5E^`Z#c|D~u+
zMX)qg{ThXq($p13tk4y85Jl;)syEg{=rwiaTnJ59TPX5)Q@xYC$_(`^D(B2pYrX=>
zQipvG+1cvCOK9b&cV2<aT=k7m7<x;6ges<QtDnsTOP+egMJUQwcdn%SuRuLOk-$Rr
zvPO_1wUh^Zv08xBd9zE@zfxekRLxomW6IPQw6LOFJ@gY~SE$!rhtNv3Y#)}ZO6?W`
zT(x>-Fj}?hNGgl0Q~NT&Qm?*9zE6YNOm#DN)%NtXYgAX@v2L5)q<&NZ70v2xGr`)T
zjv2)a+tmkW!o&{sdVA=-rye{CmOgdvyO7<lUPqyl0d?Xms2Ebae*%_ab>@p;8Bu%C
z_mm&257t4`6ZH{_GmomDeFd!vwF4F1PpY?*voocBNM}uL_L@!f8#riOUPIGSGnWE$
zPMSaI7?ZPx@gt<UXtq{DwwFfu9>jQS3MkRyqj_y5)F0Q}q|;2kn!nPa>4awG?-)C&
zkx~81DNPK89{e;RccH;w^U6GM255digRwx(%akYyvT5c}#O1W+G97n5quEPqc~;{@
z7h8yC@HT#fP)$5VH^MX<sFvZJCi*^F;hOoB-a4;YcmlX6&Gs7@i`K;QF?K=oeJ2dP
zs0pNXiqRA<gr-<c5>-IPX_5=Ua!Io+8Gy?g+XgxC@tW1N_fOE67owG@VXX#FlBR@W
zjmesQ7ci$3jiMDcrD|@jf!?c{W(hcNXqZ)KrEC7T0pzA;=?rvcXj=b9D^p|bgv>0>
zV@keeYa%Fym7_WO31sGK-l8w8-O@Z~8-}H~HCk_2ny2}LY6J2$q2%`#XyX2Y-a<|F
zH$W6=Cdt(-)^KQ(RHE7T4e+I!CNo-Pnmtv3mupJ5174-seh%cWriHxkM$P<ZG5aRX
zQ<N%i))fDXnYCzosC24TBk!R2XS?R)77TW1*42acp5|9F@xEpS#X34QTR#Tr(!55F
za<}F<xf>5O!L9)GYSvSZ;GyOR57^tM*-O4lzb1f|azOKW64XD^%%wc|phi&ynM0cY
zI|S2)HTq*{jcAs~)A`%Snq~BD+)>TnbjOWp4h%uexTa+<fD@WK3t-`-W)TN7oYGYM
z3)$0}w}~9mzDgdPz1EW=7Y^EwO@KRU573L+N!xo6ozB{2RI==%E$@a*SMB;eu>P>t
zmo73l?U?}j{)@ZzmFIvss{NDh2QTes<RN%#+n&P=eYCI8DV^imhqTr6)o!9t^a*Wf
zIyn8bvnZG2uU#IDu>frr7qSDj(;r|gNGrGo+-a>7oeeyr?W3ZyVD0T%{Mcu;BP$>!
zRQnY99=0&;XAi-1PW%07NDJ2ve+_(u_URQ+AE^~g!tV3hx5@2}(t1ZiOtkjZy%2Lj
zJMazw7q!(hAtpw<+X51&)gD9VC2i4Bv@UDkrEed^YrE-)QG)h2+AAe#o0}jrS$n?%
zR;1XpvTKl*s(t4wc+#~0y8z%7t?E8nSGBpM@VYi@2FMMq_AZt!U7IdN>!$YEFCZpE
z`xzUiWoi$Q*Pf;QNCFkNwZ~RsE%LNQbX+oDdy4M#0&PE4#20F>&cax+_HBwslxS_M
zTQOLwRn}mzLi?i__)2ZuO{l2S4pE4wTKi-N=5$9pP3Ku_wH`&#Tc=$@$Cc}~WlV@^
z)LwfBV@+D|TFj+cyZ0#oTC@Wc$ZORe$pD~D+xR8`?OM;jz<E#WPDOb4wU=#F%igIy
zTaCdkZ5Bmby0yQNOaDN7<OWEO*8MSN(W||(3z{Bk+xCHTK-*5K*hkvFVu%^k&eKB5
zkhbc7kUgyZyaQt++TUmg^hBFMsjpG(6r~o&wB_%EWn4Q?j?M{f^(Gr+Pirsdfc20r
z`YjN9T`xs}9CYtVV7{Ynl%m#7I_3$echTj&0v1<YLm<duT}D4R-E;?<LELrQ&V$oa
zmqIIZRM$_Hm&bH|a#-l4lU)akx2|P9h>z~yF2IlLX04|B7hhd;HF!?x0%OqYr<+ez
zfBw2I`t1XBe2Pv4>Xa{|^RzD48~8K2cgd{_)<sbmHAHuQ0p=U3bE$ydFx|`}Sp0Lk
z2j4+`xbC$YNQuz>wG3nDb#Kz4q$u6cZ0L*DrP<N_cR|NJ0iKJxmE_{a=;n7qVVv&7
zdr){uci01+mvujoR~fJSnhN|9bUSFdl64`!VAWG}N34*Ys(WWS7C22OCYCEY2?f-y
z>M}|1HQlelu<*LhJ_+Q8u8vBH(sjRfW6X9_cXJfhWa!?fICZA(UGh4zbc?(pJ6m@t
z5t?#zUobG1tD9N}6}NQFR8o|u>%9fD^L1-JfWiXZ%b&u~LY)`wp^J2H<U&fZ&N~ca
zCAxo)0A8y5l8VF1bf@V!Yq_qMYO5=3x;Yf0t<*XH2%%NFmGH@DSL-a4!n&jL+lN+-
z&QA$rYIPm753AD^e+)78x)ma*Z_tHO<;Y##*Hl^Cq${B3MYHY=`uJ~)uJ#R#wd&?j
zf~8I8OE0H(-J=T3zC-sGozS?avqe!{;l8eh34Et+!6;;R>7wan(XD&`OW6HD*MAm>
z9^JeLm|Cw+Mwk3U-KPsd`gFfiT%lk03FYq|>9XztH>m5Nm&}mvpb=w_b^Wy0dZH`5
z4Kk`*Lsj-;x~ue#8P~Pix?skHPD%eXaZ)#TD+Z@@i|Fk%t#hJ>$szsGjTp1ne@umT
z4*HQ$037wfWQCL7#{rzq`u)$L(?uUi)e^4yt+7ylSpT#q#@zIA8)3b>ekYx=^UyCP
z_xFf?@mjPz_31ar_c^N1?}Y4Q`j=_z<fV_Iou;?GzyQ5I`Z|i+9@j^jV4AP~4>|^M
zLjRx>t&{pCHIQ~nU-${&e)>Cf;=x~UAAweYe)|!$0`(Pn00imfdRTE<uYU@n&*%fG
zL_1g?)=U29S-outtYLa*Dg`{JZ=}<n;rcgUgZUBqWC|EX>i=B<G3WK|^kj<C+tVcw
ztv~V{)L+oAZb2(X-$akJSbcLeNSywA+E*m#|2+Y{iTaRjm`jrWHQKu;>#q*MiWEI_
zC7pjr)z6{CQkwoEZThe1Z;(rHRUbsBd#>p@ba`CY@8dz*4gEhGU}(C&Xb;A2>XQO7
zmZ8t1M@y#ubs5$vOCRt%IJ5PCd<v4Izj+H&%GLi&fLr>(X#j5P!-`;Gp5DU~#Fnq0
zPc>=<`ZT%%3-!T?;3?8q76VbNzY+`6O7vdKF;=R-X2!CW>6`G}m|d>#raF`geJd?q
zrM|inW>@K>$WyJ>k2`?e(Py{8v>N>xDt4^Zf5w8aI{hm8Kx(~SuoJijn_g<gwD0PF
zq3gL(?>PfJO?q!XsA$&LF)`MnZ>8glt@<gt9oqCyQ~7GUK8{XUb?CF60n0soz;nRe
z*RQ5neW%_#6|FA)JRi)gTW?;CxjfK+{T?`b^a<pO^y-7@T-rmu?JT_|`t<Efps-*6
zLmyfL`Vv&N&3>fcOwqwX{qRj7hV)-`z~Ev1hYLYQ^zYHe?XmtUZ7Rp~ojGWY>yMIW
zFrg2iZQP_@<qs88`VcCnnbwyrg3LpP8h3Qs8zNdD)4{OL_6AIJG_0T(u9Kmho>$I>
zi*#Jf#W3q9*zIZ%+Jp75VHRa5-3<A3UAP;DspVm~RSCcm!;}=VJq@+@K#m%oYz5$$
z;q(Tucp2`N!a{Gu@_(V%$1sN;-Ny}=e}g_>Lv|R=@Pwg&609c;uJm>}Wq9EbRQMS-
zKaDy08-AraumD5;8(=wYSWMM4XARF$(M5>i=p3{{4Ljo?JIuf)U+<hjy8$+Z8`>$<
z5@G1R4P2z*A_d#e8)CbmA<ED_3DcqtZ||c2@^-<nNd|*28b;{;jWJ}zU@#UDEm#_7
zc;N`}mkjd?q2jV3WDK0~hBB(TN-%7v-DILcN-5wZ!(xh}CL1ozLuZQNeY(0+4WDq(
znP#Z2gWfBKbw9w~s|F7)0M`s3)lvNOy5SgwSZ^4fqU=Dr;g14Xdecx$!Rrh|DfzaU
zhPO{bOqOBJZH#3btU_?+7(%I3CD))^46|<;KKKCk-Zn&k43<0t^F!eB4No4xiUPx;
zPqAEuhMQDkU1SLK2cXz+H3`dXD>1wx1}!y&SYTV3A%MzA%MD-r2}FhAOA4G;8g?#*
zm?}dL-5k}1>*Vg=G2{z?t1)bO8e_GF&>+C;43!KRT5l-dh_Pmab_Nu-8n#h@sm-w8
z1!L_7^?Cq03~TZr<(|#()>BY%-_TBOVW*)+fvI&F{v5|(x8ZjQSo;k@u`u|Nq3>mo
zL4$SxfFZ+G%C$W<tapcsCx%c85RV#M$-x*i{6^}>4TtQ(GGSQNht{Ma=Oo6a3^H=C
zrwyU>%synaEmQ$-Z%kC7>0r#FV1=U*|6(4ugR#F2b8<GuCcz39qkTDutMT0f5PI17
zi1zSq#!qOs;co0-jj4GUCyqn*5n~+{`gj_JyCC|gQT7<Zjv0?qIf|EY9tEwvjfO@L
zALFF$|A0SkbfavsukqDV^qw%f?uM9?#=JS0?<r%m1b9E=o;6V6ZxnQZ1Q^%T)B=sC
zzky9b#se3j@U-#IDFDtG7u<oSVB_}#z@0TptdJRE^!*DY)cEHw=nOM@{I};Yp48AD
zB;4p8g(ZzJ=25v(r18ltbe=bkiy%A7==?b*8f{$o1IPtq`YSN>qVbbmATh?WWiTez
z_y^tFamG+4Y`SFh_67X1aqs8oj5mhefy@M>F$3xojovXBOESK^3S-H}^{Mp!OEK;k
z05H|~nHg538Aq?8b;bDj2Q0!>V=e`HZy0?=AnC?ie`4&W@dy`UGK`zp0Av~uxM22K
z#u^W>WE*2>51nJwYy(TKG1>u>xMln>8Z5Vsjg)rDGcI}pmVD!}@96zkV0^`hsTCTJ
zQ_+5r@oXwo6dQdP!Qc{O$`as9jYZTdGmg!L!g8ZO?N=*|#sIV`jfS@Xs4|MF)~nj+
zL|?7HV^mjz)EGafJx{Ii@nMYB8LRyvrQUd(PIfdH_qKt>cGu{?6@!h&RTeB%lTn)q
zo@Qf@20Sgs_vpFNYV4-eNSiS~84BBt-_fh%zVT@$OzSkRrdp9M<GvR$)@}TRqQ(!5
zJ6{G%k8vwyFMEyan;`R{@kI+*`ixsLu@?Qt8I*Gxuo++Y6U|4)N9({kXq3GUp+m;y
z6v`epM(@Sgi1FWhSfIy7_Xvo2Vyu`A&QaqwGIY$?N}=d+qunRqoG`v03!#%nWecpB
zGTxDabK3Ye`NW4z*Tx~m-n92DIvq?`-T;fE$rk62UMG`iKBPIDzQiMDwu?!55LURF
z-nK{QVN=0n5I56vo1w|wH1iYy9;QDje0#*?eF$PaP2E)PaMZMB1zN{UcD+#OWs0HW
zbl#@qe*pI}9i*++anqGSi1szj9K;WE!c=Y(0C>_=I|5ceQ<@L({-%Q;fhWM^OCC+2
zsfsq7L8d=aKu((mA41w0Q|tze1)F>#0XS<qKpEW-)0#qbhMG9E0Shw?Uqt6Q(|eg%
z%5YOdC=^DRzNTsk{KqN!{=|7xiJbh;D3kqZATF8;)<AEJNq!QVVoeu<U~rtN^Chrc
zGASo9r^}|L*I{V9sbCvg38wug!IEftK+oP3(>X8TQcaHnus~_1|0@RPHB&w9DX*J!
zH(=Tg)2in%mTvN+>-eTg@e}3WGfbb+B4(N%Y=O`$Q$rdCvrQXj0hnXzr2{~@Ce>z;
zTc)?D*y^_FAU)UfOzdUg%s07H4Mc%yUl&NBDW)2Fi%fOo;1`?jCZbhhDxpf5Qd8j5
zz?GT)N3Yg$(?$fZY_ls&yC`m3Y4Ym>zRJX-176jpSjw5*F+IxxYmI5=uaH)2I`9)(
zb*2(32Cp}je+bfG8vhlh-8CJK1!**WNxPIL(+F+unoW+M0nlO!5rMRt%+8S6X2N$!
zaT}Qewt?6>OqX{7anB^*1pIx|nkn>lns!pzU6<)wnrOFa_j~AkU|K@uU_GXbThQt?
z9iWd=JT&Fb0KCs6BB!+9<Rb(bFe&K?^T_l(9Y7y6jl2cUA=4TMti`Zt1HC{-Omn{h
z%VV2K@;&rEG3Dq195r2|DB+lC4;6Qgo0t}iO_+WXLd>M;N6JD@nU+!%cG@(T$}A3<
z1+9?gXx^O<oRfKbIEb_P6vZQ4%+Kk;>1s~oqIKB(VhgNrGaD&u<8B_Iy|9Pb)=f{g
zBjx})gym_TMY+YJ=I<V%b<7+<UY3`c_Yh*d&1qC|=3`z#`RL>3-N6v*YaV(HVosR1
z4TI&Rd5B!TQ|4@X7WtXqr7Wbs`I0+Y0p@?`Q5a~hJ%G+2Gm5xzH<`z6<hq?Pi|OVJ
zHos1<y0hja%E5-16Mg_ssCjx63l(PmkcuSFnLm%gSh)G{JqV33KcbU!k!F8#WzL(^
zo&XSK=KO=Pi{@v&0f;fbMQ_+x^8p0=X2+QaT(O3i%wNz+-OJ|cmu;9~y!qXeXeOBJ
zvd~I2H@*Oc$>!Mo=u9y??}2HlW=95qY37|&Cws+wuofz=nb%DLaNT?+8GsvRb{5p9
zn?GBJv72UR%5`U$qbLZKZBF<KEIH=ilOZ$LoNy6RZkc1<>HNcOa~YL|<(W6U1Cnpn
z&>dS~_GQE1Li3RyFtsA{%O`;^Hs`(#g(c>$4<V-1+)wvGnfdG(RFs?D+5oRGKPUpA
z(wvkHc$L|UIIGQXyb9Cqm^V?{vc~K}MZ2};p)vaYS)I9z7Ng$Ww+1R2%>PIK-{Y=%
zCMACw&5M_#v&k%f0-??3nLom`7W1bZu(X+BF76|9-ajDs&HZN}yVKlJ0xP=AGco}0
zHmB0I^?})$qLMx41z!T*YgR5s>!G=-9ynW{Ic^%X-yB8T*8y{l7wmpy7B@iJu=##6
z#zxG8xsdkQJc}HRC+63v_G#2SpPtfV=5Kc6hZ#3_(Z8mcFjrF@$)x$k&w!gUZ{H0=
zr_EDzZyvHRnm`;Ztmk2&qotmbf=)KeWBTTvvt{lMAY3d%d!fSB;^GMvUY0pjSmAB?
zy8$ddmQ<=tKW@2p0SbLB$ycEMgvE0Kg!)-_QJU7@;@AOrfMxq{kR50-3}P(E@~Huw
zr!A&Qw9Z%-T!PGC%VG;U&suEfDeo9!DJ5qh)bcxh!8Xj2lMONFEIy|pG~BYf6P*#3
zzv*3Z$?_L{Rrj*x?{TbUf+f5WlS#C!+ltO4%ilc!BwK8+LsN?7yV)SA7VQTRoo2~?
z0Wz;xUcZk?T(xv%gY%lD&GsjFu3MI8!kQZv3kN*umOm)ichm9*m8xY}Hc@Cc({lE|
zY=&hYZ91|oMd>gm$Fh`MkzC8#ose?Nl0xC}+m<2nLGmm!DQ%K(`P>=s0*f{jV}+LV
zf1$U?68<to7hC+lq$>Xs%h^%%mRbg=Y_`nOMV6LZ+$O+NVKLJ~x6<-j4#ui136ue=
zwtP&++_7}Oh_M>WOSIXkwX{#7RcDd)gR|bUH3RTQiyJw2O_umFbT(U3egI30MdpX)
zYPA%*)AtA4EQ9l5V!P!JI#<(SIdlN#-?Oav2c7pVyX~<uot6u<!S1q5(1WJi@(~B*
zfkoMY&K}EpD!}ZuxGSLWp~X283i~YYQgvj%#g8(Z1D3j1G0#VqzhA}GIcTvRLg$cW
za~++37`7~n0C2>TOBsvDmc74W@QFpZ6jqE{1kVF8W?5E@`HovE=Ro0vCD;Y(CoO3+
zFg9gbOq<GS%RvKhhpda1!(Mx9tUFo`*6V+P#nI~dCvZ;ITuOg9TmPgw6c?+v7#7-G
ztxc3cbGOQhF$)iCe>1E&V*POgfS%U*Apjn=+Bt*unDvw2!Qy3|5e$Xi)(MKO`dHm(
z0C3#OqIj>bb-^lhp0M)TfjenEwg)piWqoxFV}4dgDs%9+maoNJ0<5nlqchNEeV)q6
zf~<=uyLQ^DJr4XCYv>1H4YvAG8t|<3&Hpmk*3iAMBGhVm5B7#xy{Uftob{bf0K%<r
z-oczAtdp0aH_{ri9?N~+S{VkGDC>e@NQt(VP&WO775_pUZwKqvO|T-yYO4+dYpnIh
zH(+U;^`8*PzGN-Sg!;?YMhZ5>TQyW*lwdti4nm^!*(8u8>jsL5C0pl^SD0e;qkoH#
zY8`7vXPUKzHVs#-ulE9e)%q8e6kM~eC712G^(4*ZhSg-ks-;_R+Nd)3rge<|!&rtj
zfs$pJ))}ureU^1Cxxd-giGvu+vHnPBs&cJ=t_Qhg{dxiBblX~DLMzXDDj1ykR(=G8
z6<AkM`CFlN37y(1viAH7^`+K*6p5>_meGE-(z=pD$yL@>I=cU=tp^!Uc*oio0--fl
z>j)IqT6b)Qm^$nIduY{LpWXo#4c0N*Hs7_*>%k&6S{Ku&F`BFu^e}0*zHlF!TC9uc
zLmREu>xaSFX8nxfrtQ|}DN4{`?f(|S?pgh4VeebNUQFL#>a;G}3H4ppdEWuiZ7rhs
z=>uyMIbuE5Q@*gU*ZOJ%#5}Z0Q(#4(HOK~q{nlV6G!0mDUI5D@tAS3k3|c>?$Ig&-
zOF7`fRz((CBUV`mT92)<cOm+THH#wBqt=_R)BbPFx^WWH#;vPvfM>!gcpfSyt)G))
zGG+a_28d~^j&`Vr*508iEBm#7Q>C}V+JzL~c3wM=;-)TZJr{$xt{oz`?(o{kQjEE+
z^`%&&`&up+ot|sYlUI0jZ3IOgkFA~2i!qze+RT@+7{}M1qa)3}Yqj5CNl&azJ`ZUp
z*A|Xp?Eg8s?zpOsrk$cOnyAqjW11}{rka?<7^8_AHKv(%d+)tp-W1cW0!k5-CZJR)
zf`Cd>kS<8C0yd-w2uhWvh$wu|e1FYvc4wZMJ@=eFyEC)r1~Iyl(RY+FhnBw~j1|-1
zLK(wU+!@BOQ#d7@QTQE51f%~2U`H}?;~;sA!J*Y;6k{&U=h2L+cL5f|sQLdAUPj0V
z5IOE(a5q9Gjxm-GHl7j71k4G>TVF#of$_mN7<MAVSP#%7#*?pL^d}j9J-9Nb82{2U
zcACL20(LT^r43vP!>|Zosf^jXLDCq}3D8StETfN$onb6khF|$C;|2N&GZ?k>7R_Wh
zl>IPxj#0&cOcujLOSf#s+zN>1F#2d6n9GPcje+JdmMlPHJ|poa6bcx@Js{^9enB9G
zjOedGiWu3i!R`e{GR<hk3}FBoOBiwGaIKW_T@M<|7<*pB$jTWT>2*@U2zP7)tz>l3
z<XOe&7=rm~#vfGCRKv)l$Dx+7n?iqejF5Jai;N4D^sQ&yjz(Vt<0lhLG%`M>Mb9P1
zlCv1vWrkZQ8m}<ErPRh%#*8cIyT*`xj7!<XSVni?b;kR3u-D9}{*~6fEsXB};P(y2
z_f*Z+&gi2gK?mb=`UYz!!;=EjHyOKqanE%zIxj-Mn{n+aT#H*66BKSUwi0#^V|6W1
zdKv#wk#Zj+j}|oj4B^WF8({on0@xs9aSXujFt$^8dx)`bA$|X4n8DZyZ$=p0Y>-jL
zcB<kTW0cS*xb8B3qUwcvjJKbH;y9y{-b(iw23mwqFt`Un9x$4}fx$_}>x0mH$S^iT
z@)1Kx_v#d5&>el#j4oRH>|wUfgim{!o=?MHXJ#XkYxw>dvyFBnu1qPt7xpo?+=ku#
z%p+W&xiP)kfacEJm<UTA%+xml>dEBM$@2ruIW*0BF}rKg=*=9W_}D?_`%y4)h?)Kb
zM0}XP(6Lfq<}2ag{FwhOfgyk9If_LEFu$XSnBy>W_9R*ZnJMQX8pIr;;@x1Ts}#;0
zVP2%|!cpdvG(&_iJEox#$~4nUHH<mqbr=k1&bbLLf*HI4&O|b|W}xvHGcX!pQOw0h
zffCK!P1(TX%s(i&5yuRpoqRmAf%X824rX&4I+K_qkAs|K4hzwl%)CLb_7r9e1r1V}
z*QxwFjhRS0&2;8-G^L$kc9g@JOs1(HSLPhk{TFaq%=OR0U^ep*?E!L_A5yv|mno+O
zU>=h}`M-ST7AgiPVBV$a^*qyYZwLG?WNxGgei8GXF~D449(I5fGrMS`Tf%H=L0>7;
zhr+&P%xo&UC}&D;1G|EGAs6bE%(v(cs$wSZ!=<cdzDYTa8fLl}Ueq$(x1q0&`OhFm
zf06kC1t;s7nX}+U1M_c(4l<3*%?;?h#C(b(YL}VaR1|uJ`LYdtSD9<+G}1NZZy!UW
ziOFd|-*sjHIoixzlLx&P=29{GTA3LpkT&MyXV7<pc`+J&oy@3X@ct%qKD`^enE5M!
z+07jJ4&)YdD%b({Z!=34L9~bY0tc<V%pUTokNMy>Jnd)JE(JHheAX3YkXbm1Vc%hT
ze+Pvj=CTU7Hq6u<hTRcnk`|UmnSNhEa*S!Gz3^S;!vOT%WBx#Q=Qwlb@4&pzJR^eo
z1he}vtv??ym!3f9Br`z^?1#+VBY=6t9Nq=&Ddtzt!SB7SjU51WX8m>r#D#Td4Y2pK
zHr&KO-B@cj0o0xKLL?MCSo78b+mrPpCG!ukKDr0<UaW1juJL9CDj{-^)k-^{L#%;e
z%0Kw9{-zh0FDr8k?E10lsn*1w6+-7O0$4lWfThE%<@L}HWNmjvV-V{#Dt-@UF=z@u
z!aBePIm+784TE8<$z3oX&f<6hGlF%UZiq<MYgULHW6je7I*QfvEXEnla;Dv&BZhUI
zP6NlXZk~k9an{w97-1YMp%Ko+v&8hPonXC97264{#J8ZI$T9|iB(Zq33_Z#E@jX~N
z#hQB>pr={5tMUA>-ue<Arm$vNab;3jBUHbV##%=uU+FC29*CS_1)qT4SqEzt%}E(7
zE^PxdS=WxC^&G3+0R1dh6@}NcS!_y#<*?jmz-}(9C<r2XtlL-NT0ZM3L^5U;utF%@
ze4cgXAQ}r<fi!Itu@Vw6!V9b~MnH;LxwP>sVO{+ihDup=dEm-ejxFUtD`$na0=t40
zy$hYytTGBI*Rf9L1N0*6#%J)bo>fS1fCg3z9dK@BiFUxmC03FZjh9(FsYLV&Yugeu
zUS-MY-FS_)Xgm6vSvB;;wXoiK3tqIc;wiD(#+sx(_zhO(M~`5>o%J78M|ZHyyCBoa
zS}Op|O%~@qewZ#+G99(O&H9aAM?I`Y_n_e~9)I5PpC4Sj!>Xs*WQ0{m0r^o@^vfV)
zEcO<ljk9W~Q1(7cH4lmttSE{iJ!EYxMc*S<=!+mztOz}@_p<-w0L7X8qdUyIu>ZLM
z$^Go@4fqY**yr}*lDM;z4}d$sJ~j-$z1V6;2SmNu8=iqdANH;w!1%I*7Qvt&d)qkr
z4zu5W38I1QpPvVI5W9)y*Q4x12K0rn&HX?NWxqjXY!U2JS!j%8Z=$>97<<`wkc?sf
z^E0?ucF{DTkFyt0#PkHa{}P-@VBe6?UObWg-D-^D6uXy>(41yV>4Q<p?8iO9rLi|U
zK{1^zpt<`D+xrbDWU^IHqwgGhGkv2li!Gz_om}<}I^UAVKAi}#e6}VW&J?nR>EMdk
zE>s70fxU(nd8O<)3aFQ{gG1@uemUFy|4&7*Pf*bA61$(?XP4Q>X=1;^K1!RGtL&^j
zP`t+8K_>>A+0tKOw}t)9eE8JLPB{RDHuikVjoe`0y#|GL_EIX8?O^}p3)0EnLCc1l
z?CcDvcd@yD!+bYewvXaQx7dGDDyxU>TZztI_TOfR_OZYD5-|PjC!7E}z?K}qu<x+%
z)4y*Fu}c}SJIr<z0DFXOy#a+$_EsYr$JnZ+&>Lr$%0TY3FO2|mf?e+n^@r?P^ex9n
z>?|?tO|ehWI?}O+^Cm5Y_HzDu3r;z6KA<d$3+H3H5nVZ7P~vbu=Q(;~x^aZ`YIo<H
z_z=W{(?DpRoSZMAcYt%9qEB9&tRN6?&f-;2Kgg-0ddNc@e_s$EPRCk!;mg^%4kCV>
zf{ifb@8A@30TaOKd<LzDIje5Kw?NL-)36)FStSDr=7=fbd4yB&0{V_};#?sa#!01n
zCY<y6C76%k3{v_digR-qCZahR^Pv~RX?`7!#&LXiz*0P?I1uV5INzE8mc;puj)|S*
zIM%*}p`GH$J^@S$XYEe-oyz%zR;+0pdnU+P&iU(5%-}ry3NV?RaGG$kIc;aqm&5rZ
z5(>GT$ZCibaHJH9JI~qr6PzjJd_jSTV$QY*K$mcWX+kgMJV#}-WgLASyeQ|4I_9CZ
zf-~CyZz?%{w1KPQJbwr7S965nuvEhtq{7i!&Z(_HtK(c|!HarM3k9kgI4}Cbi$+c}
zg^w<A40Av(bE+wDdWCad4ZW+JDpyE0aU#Ou#dXfpd%!hwerCgq7EW%M19n?Eua-cu
zjq^I~&TepODPh^pk!*%D9UNmCOmuS6X`;Bvd6CB3#d+Qv<ThtM1>}1;lT=dF%ds&q
z>;aB9Etm&6yXm!mhx6`TG!Ajr(mHUM)3F+4gww8uGou{IDq1&>an9X`7k4>VccS$k
z=P@eS8Rv|y1G&%1`W<9~Q$dFkA8>d&aFd*!Ghp{2XU;UpBTmS1ct6E?MA_46&I?r2
zvxmE1ghA}((o%V*Gj|_NP%hl8x#)A{PBg={ecW4f9>epupS$=Obh>f>oDVd2u74$D
zJh-z&AfDWj%@94nb)#=DcyaerNuM`&=9iE>$lXNmu|wSd`Jm5-8(IO^e7RNgK>WBb
z&_2$e`&lzY0=P-JP&mxZc^@Q@`(hkWg19p%x9AAw{`m+pN4USgfQxXHo0$l^A>5h&
z0Vb5Y>^EqHahV~wGU42NT#yLvWqNQUxikL%izM8{Z*jS!xE)Rajpkma&1?*JRVuhx
z?*0?tj&n6eScu~`tb~Pl?h`a?o#3YZfZsL2!5!zoU?TS`I;E4um0U;bN$wpwdT@%n
zIv3cdxp7nkn9Myyul5w~#t#6K%4O3VB#rwYZL-q2zj^>AgDdjFm@>KXe}J6hz84FW
zEUpXH`($&ADdm>Kefoa@%jLE|1?W7k!)-nWn$I2j8e=Np)>2{rd2Y=fI9$l>I}6Yv
z?(?*JzQE<pgh(;BAQLbpT-^}#OS!G-Fki;iQ5dM4`~5WfD!AXh3cX718mgDA;tu}`
z$!hMasUS7nf?71za(@!SY#sMY2Opppxz9L5qn^v9pR$4b?GG4QBlmOKdR^kyHlXn`
z_vP&v{T1%$1N2?x{!RDAHSWp}(bvRvc@t>Yxe|)*H*<q26WqeB@_<h_xZ5lcY3I(N
z+qr`qOgouQ?z%~c+~lqbp$$S8H<VKK-Q2PXfZpPkQef^j_q{pj>)}Q^L$sIsV<;N?
zxRG>s_j8}KW1s`vQaa->$W5dO)g5joWmtx|6(7KhVea>CkR0L8qJY3CH=1&xW8BOX
zjQ%dS*B7qc<G$lcb*tmt$2#EReJ-yL`V(9q%AP*pE~5?2BzJ}pmL75)Y$!hBzO)gb
zQ(XULAk*B3Cn2(j=S;udUY@%jym#i6(AL<6_sNe?aOK5P)$TrC6=fXu^WN;lAl!Hj
zbV|mZSB}-JW2OhsM3a~&uSE|11H9+Uq3^|OKL-tOp7UW?I>?*T1DHd+oGobd;bs1S
z@%r*6`k~;*`+fi-{=Br!7*hbx=QKnP^IX;dGmuw7=NN)`9NOUq^D0il(IdR&R5o;!
z_oomZIzo6_)SS%><z4lJi7;LwiWz2x^A=DvCxUmG3P&S($yCjKjMrrWXcVvUXK>Lx
zH=3?ucx_LD#PVi(!^Cmk@Ew4~@yebBN&>HLCrl*r=6{ODB%TL-+3Ga!=+n3e$-IRh
zz~2-H&zn|<nY`R+$Yk?uuK^~9H-~l>xx8-+K=ODQw0X$qEn5mwz#DlBpyzqrD?kc)
zGw57u5${S3K#O@|DtIg5ZL5TbrM%xyLcNSvJcYh;-VjCED|q$agRA0QABSW$&yn{Z
zMp(mpzYOMUc?LQ?QpY<%8>x%DzbM~R&-<OS84bJvR}8d~_c47N_!95Ic9^)#3v-3S
z72YDsd|%})cmoEn@f-^Q*2MeX8-3S#@6q$u%#)PC`xai;O>nKe$40=l@qTg8df^7|
zdJI6@d0i=Rv4i(F)g5&5qUj{SP2Rp!u++u#q_tBwFU$qpE#9nS(7Vn1hl-?oc%DCk
z>*p<_?CAi{5(mja-q2N$JG}lFxHiQ5^$fs<d2?wQI>P&c!p)<+_a1X#Ok=#?*5QY}
z%R5?&)_c5S24u#0=bwg8_j#A-+g%g9N-Elaz>EG63X{ArI(7Dtx1=A9k9gGwVQGpt
z?FKT<3ncYD{7=7uK^Ol2D8=E*&(OfaK0c3L;`{kY&!W$bKezK4Jb&)|f3+Be2mc{W
zaGw0XKf@>v@Y7bqk{3UKvMApCD#}3}<S(Hrf<ycd=t=kC3r3*e%ir@N)cyE1_o3&{
ze~R{60sLR72=*}F#R`!?z9&5#LHv~zhzRC8uZO}Beii}(j+saKVc`G`;V+{fHk5Dl
zfTb{g9!2RR`M*+)+cADAy+NY*rdvRZ<+uL<a-1Kw847Xy=oI|g3H;wqKqQgBPy)Rq
z{?;BCJk39U8I8$&GaXV$;g8d6ES;}D0EILBFj_A=&hjJf!C)qT?rc~($FH0V{Ve|D
zbO<Gz|MF!t=J3~i4wyXtFU!%F&u=^lu7JOqLOg~1*Qw;Ih(Af&vJ3nJQ{amEE>sm$
z!f&NttBgNU53Zcg(!k#e{_!x_t>VY>!Bso>{i~o@!++2QQp+FR1<*SFt8H+&o-Z4N
zXaoOKN<%jCXHYKn5`P(Gi!bx#6!*Qt5Bmy@P5fV|j^#T4``_VOGk+;<xmx(2HNb8w
z|5@6>wDD)qhU5l6g${eS^E)Xw(ZP3!XhQGhKTb=xKK>kvvG((;?g3_ipLZLIgM9qh
zxP$o<l(ZV=C%g)7grAa*D>KIL@`L&~|NsC0{XYLBy_zTZpHqPO0YBy(`X>3zbm%?g
zKbHVUAMwkl!A<cGQl;oLpXs2|ggt^@y4m&$MxTd<vmlEBZohy*FDW;{w_l>sU64U{
ziH9KSF7!PG6*S!)5Oh&JrI%pI9oY32tfw&fLBV!97vL{gu?!?Yz<db<JuK*=iuypo
zY^tvh5`5bP%wWOZGTQ$g5!BL7=BS{ElBgkq0@^r63Vuj|iDQE5wIES~)*RT47QDO#
zBu2oj0(Pw6A+3Us3tXFFB2M6`1c?`X*@2;*6fCC$45tL+{lGjeI7r!uWP#sCm`@RW
zVumxRg4kfH+es5VT?WN;!EaRMd`2LC90oH58BYQGoWSonkSu`$hXiM43-)~km>fag
zyMW0RWPFFlJb`ULMDhj9Xc#OIJZJ;hd4Y<G0SX1u*U(oaSalDLWr9B_BwQ{CrO$#@
z2;MwF=Qb(@!&LfQB`~XjRxNmqrluOf9x6tt739tWXq{kfHP9{z9=rjx%YuN5XuKl$
zlGcG&1)n^L@m>==q!@OSV4xKqUKi}6EM&8wssy8N5$vJtSchPgwrZV%`;?@<DVRe?
zLL6O!trei%f?w&*za{vo30~Y5xQRh}1l-#&(JKfU2ihG$Gc^tg=27}`Snz!$ER6`>
zqlnz7VB0;oJtp{&mbiBX`+k7rJwYcGmyHW{c){QULH2BLlY&)=@adso{nt=<<Pi9M
z1hgqZ_$tUu3%)M}+8*I&6r|iM{F(Be&cez05OEQv34rY?yg~`(eZpR<$@3IGpbr!r
z5PsPTJujg<Z85!tXDN_)P<VC_1`i3}rpeDoSauNp`U-z<#<lPhzDcFWK|;qfr!eeb
zVIIw1M}$JEMLH@Rr1)uwa4A)6hYF9VfgL9Nl6C~)Lfua=5g}Z^38RP+me8#iD@>qU
z@3>G*w_co3Ky@hb!kssuenNOu36dcE_bN~lh39G7NfQ3n4zLtqs)NqvrwShh!r?Sw
zSRY!`h1V%|a7O4n0ZV6v8z^*<AsiC`CR5nz4(xM6_Uj-y!j>ec=L(tqFrO#fPkVrT
zVN*903WS<)sGk?!*blHmA&XAs6$$&7gIo|Y^D*3Fq2nzFG)jau6j>`3is;-%l`zhT
z#%iJZ3Ser49_6?|wZdy+SgI37(#qnZu%6Pq^+JOPCK`k<WdZc6@KbkyUK6J7he(sK
zkK!2Dg-^&K*(~(_7GN#Hb5t(aDqKRVvo@jMQaZPIQz#1tc9(G1%OKst#3;HEg&}W)
z+!iiN1!#}(HClu83Vn;9-zVHmVdo*?%w+tO!$J>=agGQV(gB81VcJSq8WX<Df!({p
zkDTGfJ)x4;5aYtx)j)Y56j1nQQt0wNeYfVJ@JEVnJQB81C~r#m-dDH?)52`pKe~wm
z_rZj_XnO+mJw)$QlE71R%?adyDDoO$yhKI~M7%}M(}~@KqQE9d9uk#B!IF<?4#k;$
zMePFs^An9wFvwq2Njs4Mk&a@)j>DpkP{0I<g6RBiu;}ogfH@*^?1$e+MU@l~2oWv*
z2P90CLDk0LqUWiMEkg9;EJz*`6=VV?N_2{@bF}DL3fRVo*tGSD6@C6RNW3WIML?er
zt)TlNL9~GuoQa}W4Zuuti25jXeNr^K3azI^M>~LaTC~Ur#bnU{P2s7cTv{@wi5~tB
zBwe(EY6{MXexyjiS&{QQAQ_@v0~o|P(JxYnWQqE9P|p_a`5VwVqJ9;ib43aYE98l0
zeu>MRFS=I&p9(~dZI{t`Ui20%<O)R|f8gR5iB{8F>4IogH1vx_AKwBg5$&hFVX5dU
zeP5(Z^fJX(%SGcUP_Gb)C@x<q`lSUTRifupAyO@R?L&B9Bicx-om$ZxZ1-o@iQMR2
z-XKz3goQ?to8wu?ToOG=p{2{BD!PNOh~hfYc~$iGGZ;mas3HS>*G1D^7-+L-jP`gf
zqPmx0uvJt@ht}FebM*ji7cFvydWWd&O^9@g&b5K-674?(ux`=2l!v<|x=Jyf+aiy4
zK=+95CDQt{S9IYZM$spl^$}zSL`6@cb5PWE34^&KdV!{`AyEg-8^a>~ZitMEQc?jk
zCR(}(<gO^gA0qcen&)9~T$Dz?{e6+!LR^GNQShtKdnlUz9eR&MGiyMmL|i)LIxXsV
zq4>)l@po&$?iIhbAI><7J)NQ9BL0e^$FAaNdgJXAi;tjhzxcrg^tp+RRR8TR=24Wv
zL;QmnBA((mDbjjCETT89m-y*TxH8`2-M653P<)2sK8M8fwgJ;e9CH|M`-+!+M0GoU
z;uqzB@fQdE4-N;2Lz`jZu(*jLae-ncoj42<Z+!)g!QvG%z#I`D8vyoE@fTSjA>wo@
zvkw(ZDMAz`?%DtnF0S>2UW9m_0wR&(-nF<S$HYgxU?EDpl5%v>;#>4(Mn{Y|iEh?d
zamNmLdR&}KG3Yq)%&ibj5HDQ_{Y0^iwrok_L<X==iaou6eM&q{8{O056_kZZ7W;pV
zF{Oz6+<=lQ-u?nm(!?)JKrdbV*Ef(nBmSoseP_iDloihqpP;aMrbFyOOTKerfex1~
zOZ?Iepk<3IK80eASkVcXT=DA+^yP`WjgZV2e?eQO0`Yzq=${wAN!yb`@j)uuC=$C<
zHQNR8JqkS(i^T!pO2i8eL$6ePjLsXEiBlHCi*j)kE$%AB4k=BgmEtutp;w73Rzs#*
z{PaqguM@xXKFCFJ%DZsCUc7lWL>k1wb3q!#^C<mtNnDu=a#_5c60BFm+go7is`$YV
z5V<A}oQ4-o;s?*+N4qY5gAxzT;)RQ$&?0uGDZf>`%0aQ!HnH=o7|advHzCky7YESC
zggeAB7HD*e*VFHFQ+zxaes_uI{f@?NvHWpJ-V!U$qOVt6a|T?W_!bq)_KQ7NL1aMu
z!){;>inqGKwIOjDRh12kjSt|=i1^4~;6}yg$Eg5jOx)B3?7QOFPXIG6?ihgneQ_V<
zmnXz;bVKBUcqc_5CdI{C`2A4)*iwj0i62p#Y8tl=K=(*~_5yL1Bv9nTMdJA-I9Ex`
z2I%dR#P~sSzhsP38}5?%`5+#WhiB>BhNq<Db6kW2lHD)EDKE*RPeHsTA0<KmkmPg9
zHv35K;f&!-Uy09LH2O(iqLqQar29Vl0wmr%j4)6#V->g{N$un43zl5xVJxANDcVei
zNzyi<F<hdFf@=|y+iO4~CCBopZYN6OOxxaQ$?+Co$4I^^1zM~`(~8j_mwZHJigA*g
zQ~(+;QPayQK{A8h$%&G+8GuQW2<}4tq~x1>7{n>bvQVfeOQvQ+Jw>wZKJ-#0O=m&U
zBx`m-AzkvJ1efHDgil*|$61MeGZfEB&d?@0OS1My_?<1eLLu55$+lHc%#|o8MUgLQ
z*o46pNL=Y`#d*o(pJ*(UWGsilBFVZZfPF!-EC+oh5`TJ9OC^n4pk5})O#@dhDWzi8
z3dw=RuvaM=QA54jA^DstS861yRA6f*@BaqwqGW0<Wa=gVOu*9y$yzE|X_P$r1^SmH
z!z^%DB)W8vtCB3r9bc0y?*eI(tfl?mb;&n$@tY-iyWmW#<kuQNw@DU0fxa7(859F+
zm*iB#?GA~foc=eaQxY--OI?y_N?deHwyy-*Ey;Tnm+O-RZGvLIWbqIb2PAK+;KiWi
z-<eRjBdMvxu!kjcvw=1u@ud=|QHg^EGA0T93n+IbPg%j;lRR4mk#UKRf|C=H(G?iy
z1IZl6yYOvN(z6WYp+rY9&PS3BbQ)t?GVvh{?vXZJg@=2k?d#x$v$SLhI2WnI2cvhD
zDrkiJq=A%4c9;H6<slx@=lvn#DLqQ{1_z|iehA_v4W})!w^TL&k%Q9O%^-)Qe?CL+
zKOgDYcy#(ojdk$NPx>d#jQ&!O>%b0>eq9XF!_wmazy(UvOW|6OR7wT9!O|`5uzN)M
z3DqJUl{Qd?Ylt-IWf%;VHc><?Ogd=7kiw-)UxI}QsRw1gBc<d2q3@XVo89#MMM-b1
zg^6hC=M^9^Qe8E$W2F*WfgP86QjtrX^xz_xh?ho*fp$XL@H!k#kTz2ZWTJGOO1F}v
z&(q_7Qu-||&`(K|Xen`8y1WEqNtXWF4ZRfUqODL!l{Wki%rxok^%Q?em#+N@Xc^K}
ze`sV%o4$kSIjNFf9XZl<ltsyva_BeAlP>N7cV609jB8OSeTV9@iljTo;C6{rMX%3N
z=|b9qlu3)Cp-?G(a|SF`NsSv}p<1fIf_G+}H25QM7o{dC)E)KG6Un$Vm!$WP1Lm^S
zi(WEUq{*A1-z2^244LcF4;FzmOLJ*`(k2}}1^pY+b!&mvE?r9zwGOEZ<#{@#OCN*5
zo6_7b;AofBYZgShrHLysvRl$u$nD$G|7aoBBMmtNkv@mi={Owjm)5@zc0f8r!LvbW
zrx0j&r1w4H%&>H~8j2&*txsTtqtcEU03DNteFo6G(ii&R%sr{E9DU<bpKkzmUwWA`
z_7l>NC{Xl3+Gc^lNoh(IFds@kSPnyvr0e{FIVE+(S3`7Knqffa9@!}y%<q+Xehf5c
z+4xn+?32a%!Qg&b%`J@HP3A@GKzG?p%B*_GKGuNql&vsB@_?*64U%56XPp3cP^P9u
z+94T>qGdj^-*_<OEBkpS`ut?mv?=tLr8*WuCP0=_336EWGd=LZvb~+?JR(~|E1ILS
zm6xFrCR;<Vqj1^TEf`FMY-1cqr0iw@`i{xIqq`(p_QfR3$H@Liwd}Dn!9VCbE_;6i
z`r>5i-@=P{*}O1tCuANUV1Nm--`}9RokZDjn!=N0p)@s}k-bFI^jX;}^u%SzmhsV;
zDI2Baz&Y8zZGg#=y+T#W*|Hz!!%~jyv>uJQva}iC@?_u9MkZgjo)1zWyG}<!&ddIy
zC{Cd)Z5nPD$tvlD)CHN-Jjy>5%NpEazC?D33z<?`6D?fJWUW+@ST1|J3(i!?B*C~7
zDrE--VWLWQWEcw7vVvV`tdW%!fUA|sjzO|cmQ;<#i?a9Wp{$qvKvjR2WOJwx<g)CY
z2snC07CwZ=CfPR3C61ZbWpB`3)-0PSKx>QaAIjsk%EVNX)F#{VIIufp|5BA!r)-L9
zAa2Sw&^OS#WVTUAcFX34Lj9I(4PA@dvJ!d^^~m-YgY?Q0XbaLOo2I9!UnV>Z^8>Qk
z>u?bUWx{E2jytlmEr1!4O?(g0VOdxe$cW59prbOkKVWxE7MTK(yRwh#;mkeR)>G&k
zm$51Rcwfe(%QYc;kuuN^WM9*<x=Gm<8L%J9c2fHAkt}rrmwQU~`)UkuTDF)j{vP?b
z9O`==^4)dt+gbiR1tMJJAvC|b$}^}aXP>-)9<}}Qi<PkJCinanjqdVww370WuUrqi
zp7Mznm^dIW^hTqXJoq9Sz2(h$06Qq3^BNrWm9Ovsrk{L*zMbGN-$IpN0rGLGh(9cM
zJfb{$pnSF(*g^6ml=%*p|K$R5ME-;o<fuH>9iky}PAD7>l?S{C$uN1+arA}DpQnXq
zguIzjjFEE9G5C8-UPUkJD0wQC9Yo9JC9n`9e<BnpvGUf}pdKe*Pf?M0`7aKd^H0cC
z)sRV$fAkL&6XnkvaS>0-YaWNeQ}X$R&^RrZ`9UL9E~EmKH2F@N%hKhq(l2^OF8mGL
zSvf-sgBkK5%C2R~@6tQ!oV<nJ*IDvQ7oe9dpGUQPIr2CmBy;6|yypO$CvSKLqWSV|
zAHiUOeDDg)pO?Q%0oOt~mx`{6<kj?SUXbS<#R!Y#U**A>5_$MukW%?>dhM6VyD30b
zF7Kvtp$hps21r)QSH-}YD*4yx5UG~WErEp^`8Ge8t(9l)q`J8}c_5uEyC@I50gZb3
z^R(V>kULZ8zEM8A34NF33;e)cmA^?5muvD}{~z?08)X>Ub@{zKG&aj;&`sJRzf3{5
zR{18H&)ejZx6pV)?wkdK?ee7)Q0S2VNCn?F<;P~wck{dCPg12#xBP=xbPmdQ=7Zdk
z`%vy`NPdTcE5q_P^1zMAlNZ9nQF$gwj>*R;T6S0dWg*b+$-Os%jLV<?|5dx(gHE|U
zkOwnicT)brIXLrBexLSHkL0OEXq=LZ=?tf1TK;qeTK6hKY3t*xSoRTMToiS*pW3fD
z*9}W<irIAf%U!{40q3FkeJ(gp#VtDiaX|5GGhFjh1grq(t+;g_pa&IZ+7cg9<WhLt
zSJ6tfzkZ6oNQn3=2I?`00L7n_GCS;0e3}ePfr`iszyv7*-iC=Iiti~KcvLaV5BedB
z!>v#ZRaDTsCQRW@k*x?tIE6?f6+82w9;JAR7Glwgb%${&V-%TG!5pXX-URh{MdK>y
zolx{qtRhumiGZOr#hL)<r7Ijq=E99Lirw_8Jgc}zukQ?nA5E-TiWez!kgYhq6^%KH
z!8uUORrFtj`8>rsN-X6oq!QRIP=sxV!SjkC3Sk#2oaxj`ks_EXFE1$WH^FYPqKe8Z
zN)?@Rpiri;&w*sQ;<%#<Y=xrfZFo_scr_BDHHt_|C)6s^+R<01Feib#sF*=H=X!-Z
zy>}ZF6?|YfDo)cj@{;16&Ct87m_<vVD~gFdki4pBq&UVk#jRM7CWQxOx2`Lmq7$gi
zih=9!utm{OM*F{3#pi24+7#Io=Dwj=M=_dqMbYcvIux(PVZ5D+KX!w=smSkuewQME
za>m_?O|-+krHFbS*tZpa%OKLD_=@^^6{nwtYki7&G;Q=NmX?AWP;}Cgd{FUJCmQc4
znod*vb4c;h1#}K8@^Sz(qR625+^E8z&cTl<0;w|Lu423w9^O;@T!_AL#Z@X}yRX=M
z2;79?#bJm%P%IVzbW-sh)z&;z?41v{A1Pj@3d$+PBFYO-D?Xvv*&gL}N-;PqqY=e%
z%-pAJrCr^ArJR0dH|3h&A>*zLqL`nD@@3j^dMdLXN8bVEgNyhLy_A1eqtRQbxDN9N
zm1+NjGl!Hb=qolp$|xK9e3i>ef#Rq9P65te*-HV)5asML*bP-08vq@qJhL5rj&S9Q
zWVA*oOV0v3Qn}%4ICD&SheE7T%7|%TM=QU*3NA*ON;}+G<pWB^9#`hk;~%H|=q;$n
zE90oX;)L?8UoiRv<=YexPgLqCoS3BK(4oSUO8I~A@RagfsxLaN^vQu_vP0QA1^pCd
zJ59`~$|awnHBG7af?~RI{l9SWjIy{G<g9XAAM`VnfBy+*GL@Xw;La)A`k|1el#yh%
zGSm$09OXAgkX+@@G=t|UFHK?)`N~8MBny<@6c{_NWV0}cLZxH!BaF95xtBHw7nEy-
zkSSLB2f(Ki<*^SSTBaPG#Qj*VY@^$&Lb?7;*sWCZ=EK7(Wzu>mR4d!JK%qu?XEDHP
zl`E-cqfS{#Gt)(7Gp&j1l`E*euR$3>@7+cvlcEz>lqvuJzcE*pJ`|U@rhJ@2yG_bV
zoxr}X{5Kdf&C0dy@S;U|i*|~w$|X8Twka>t+58*I`E=~RT{-JM8atH9eekeTne7d|
zn@Z<ta9v8P8!)?-skG<0rSxzH%55e8KZx`w*DQ3v?_Om&tq}T@&n<^WzY^tLcvh4W
zipdTtRrGHMca+Xi7}}6hPEqS&<tZh&5vB45?2amL_yTQAxq#-!yUM5D1Ij(+`p-ee
zmAsvhystb!2Wlpi5jBu}p#11ZkV)kc#*FQFR+KFd;l(56g4-C(l=83@+_dtuMtHGD
z<wZeY7ggUWXt=6=iU!O+Rjd`4#9j3+#ezLlmLQw%@kNen2jK4^)jvDX=%X@IJ)^Ix
zZUM~usoZGe=C87R11>;y$^dd$l}anHKve*(|AJI)?|=(dJ-rc<M^v*%K#r=`qyZ&F
zmH7k48LIk)9+5CrJFR5GRjVGtUWBT!1C5cYLdTN;J*LtvLTi-jC<R`kRXy~oi&1_5
zI7qCj`6(zKS6wQ^AmUUe3YEmG1b=`_R86dh7fGs5DUy9sHIGuE$*Ov~$x>7nS_Y=7
z*c9taQ$2kiT)OI~AAxyB)i)1~XH{P;qF*vYWnY5UOx1lqw4PJFC<j`WDrYUQvsGi|
z0L@W7_Aa<wRr4<(d8!)P#OAA7Xya9&Iz!pV^QtE`uv@4yRRX0*CA<ab3#vCF;eD~H
z^8)%xREy7`u~gMR2hNnKf|ve(C9mqe%|NSADQI4<RL$87Ql)x}u0^%#XPTL6RCnTF
z_o7No8?Sm*h6s%fDoHKOH>y5+66%*!JycL}S@o$ACa$Tj($=F%RZEHB>#Cs)a6PJM
zPk7O*`ehf)_o-$fnCh6>uj+^Z_JGQej*Bp;I-ds6J1QPkFb=8Kr$BL7wc{6<7*T!p
z3=~IIcWcl$rdoX;++EeTJ}_}lwJ`>g<EoxUcz<8zMs822Hu0eMKy{1CNhVcu3oxXI
zs*E9c@kmt`2R+9gb?m=D+pC^B0lUuXkt0xaQU4H#MpyM_50HIo)dV#5tM_Xl;-(&^
zN+x%8KgHEN)NyZt^He`WmGlSH|D#NhmwHn-B)!$oEC<*@br?-^ht$aweDYE6ro)rI
z>eEyO<L6NSkM0(K^;06i1gKqTKXX{UmR=cw>KJ-dg4Dk~ghsIX14>vNQ9nVk&7<nK
zC|nhyeohFOQ1zfUxG?pm^WehO&v`*FLcNpb#YpuS7nsM?Oj^}Nsq5%|idMf%JKGqw
zV>M;fW7YrC19V)SMS;9H^^RWrhVkmvv~@Y5-f|mu6V!h^0qjKe;wPb>q#mc0`APM!
z6q`Av{+H&9)9Ujx0h+9SY8Y20MLml`->K@8&w`|>S5o9JUA^T?IC@6Sp*`hUb*|$p
zpk=5-D6y2OE}#J7IrWkvU}vchgn(qLchV`29Ca$av2xY>zJPw7I)grxn6I`)L7_mM
zAArX5>eoI2XrbEkPmm(DZ!5?Jbu8^=i`5Z97+{Hd#vEXls+*`}u}r-noFZxE>bNFg
zSE#3{=%P}+mTD!d)C{`Z)#`EzZ`Y}RqpZM1bq*zO>eWZC0j)tD@&ptb)fc}8cS-%>
z2N=s`wI5XyUQri&W4u?@?@@{8HT9=dFxI60lv3>1)v>41*sSjUoSwfHwHFiDxmEo=
zEeG4xZ;zw1L+wIY(@u5mb3nVPK1i9uF12<c{O(r2_bIp@^*Ch(de!M)K)nz5D!dp}
z@1o7*9d!kTc81g+Qg!jDy08q+jH&HQz};2fvA~&oYOijpq#swWcpshj)fZlX`x9#0
z9$-IEU!-Y$QvExvvmdG>s0#Iw+O`0$O{uTOL19|m`7F@(Xnvs26ztXX&`!cxvw$K9
zE}A!z(depi*?}L%P1An^(C!-PS?GCa!e~PF(&P`p3x~HRobsIqHQwJs|B&W;sx0u)
z)F(p2SMv$g7x`&kEPy3{%~MlwCO~uG1vqn9lgo#GpvI3DX+fIBlyM8zY+Z@IBN|f^
zFpp|Zwt@@M^u7t7LN#xU0Xj^xssfFXnn*S*9CK(E*r6Y#@lgXiR`U<t`NuW8XM)6O
z(r2SDUX$<#Tsxup{V8w>n!W~biJDh%d(TYLjQk2qCpAwvV@#(sf89pkX-zyu5Rx_T
z{tS^6&5<u)DOFQXG5$2oPc#>$YZ4a0!WoTY(@SvbtmeyjxOh%eOdIPg&7PeYZ?@)>
z<B%!T?B0%{6=}2-7r3A)qsqKuP03SeEYZA8`K(e6uK{{xns@~amTP|a0D2XgS}I4b
z)U;8~s!AgrL|?ULp*u*8<{cSGt!BN0mhyF)%#UIIq9!91*!3DkBuInCi;5jDYdofL
zy{>37ngMfFBg{tQHBA-09hx+U-h)rqHTUa5nl%Abd)uP%{2qO+nz{6hwQH*CK{_<|
zX<5{%$=VCao0<&TTy<%BUZCf%Thl~!H@7su(iOU`*&Gk9N7Fq6qWu~-D-;Jbp}%6F
zgPJx<O5D*rQ4dQ)n&72S7}h+&MdOI3Nd?zNHHFnMIHtL=5hEMd)VibbzQ&DmnG>35
zn#vw%E>Su1q-I|xeSz<xCixunA8DSTdb=r2^*^vXtx5hBqR!gYbx?HCYH7}Q)n2=e
zi{PexU5h?<t^Z6&dT8@$m*S=U?mis#)_zZ!$%EQT0XSbR%LSaDHsThB<gYzLxz|AL
z$*0g4r2Q4&SaHk@)^4O=Ux-$n3`?Qf@CEQKOuL!tL1MHk#n6b=x^;s)u5C&O7pJvR
z4kuo_IvM_+&~^;~EkXOa0X`*a<LAI&lJ>=1G@jHhp`Gn1?FNcEoz_mi29acK`Z|cD
zXs4)x!jY;y)eG}!+Bx*emUQg}+Ety=-dGRCvsyperDSNMKY+nZZF)A$pVKB$R3l3}
zn<{~`wdWN8&CzmR1(&P+V;L0kw6A)=-+b+MA_dy5Z$sg{_Fy>tEz(X#gS()Oy$gk6
zhj#1JaHB-)HWyBnYVW!OtxUUw4tAAmAB{o3LaU<0L8aE+1*53aj)p+8T6=OI^lP*q
zFNJHh+N~?mSf`Es0oWI{7k`C%y;h}%LW9;l6)26`%?_BqqTSel#;e+86c@Xubu6G*
zeY5s6ihZ|e4^dpMRV$UFv0b~3*3uo?cgE1ysl8nZ?xyzTPr!9)a}EKfTRVroNYJAV
z{0O91+erKJKCOTX+XuB`it*pk=5U}lqzzJ`Z&=$-HA^E}$tzGF)jr_}L+d^5SqjgM
zYqhU}+}FNNv8YMy4XSu~sNJ{{qK~whQ*dpM?rj>=UfsV8^f~L^DaM%g=}yf=<9?kR
zm0!E*hTFio>lFDw@zA{+3lUG<EDEpr>K=@u&rkP&^5*`!nsR#l19ZJqo_JWtq}w`B
z_cpD2gLGLd;eN303e~F~(H)~a+ELv%<sc!tcNXI6h3XE*fD6;@aECMDx^?TJ7opq#
z8u}u27nyM8nC?YSkSLuY575!N@9DRX(e=_EI98`I();hYu7N&N8K+CSg3fr|vA=<K
zLdRJNnFQTRFL;rt3!-pHlJ3xxaP*{Z_$gRArMr0!ji+^G3xS=i>v{v1GDYX{Ec8-!
zK05TJ=}H5@rRxIe?mVOGn+Ipk>h@d$m!bPIk18oLb<2H$c24)#ad?rXiw}YMY#sX?
z8gq23YoMR2J3yh?Jl)T9k}O|W^%%GUU2F+p&g(Ayg2qCfD-Eqk_XC|yy`UQ~fGgHD
z(`;Fyd!A~XOLgzj8l+6;LW$9G-KHWmIx2K`cc8UW7qAt-OqH(GAAVQs3I`xlqdQHJ
z(puf0RC-mX+wKppLHEKnm~YfYo(A?MoqG;ouIgSogvM*SqMaa3I#nm!Zqa4F4U|@0
z&A-rV(?!bA*rAg@3$RYzOe4(Rbm(?f!r(1kDs6jj>-u@{qDS}jW`OqUl6)c4ryC4`
ze!q@I&-Q?B8||nEbt2j~-qB@I`h7@OMt8!n?!b%qDMoYwi=a2AJKP8JcXh8(ite87
z+aF<fT(@I0)bH!wc?0$)bdE6kaOeZw09AQR>e7~=^Pz5R7aAYw+O5!^(s}y8(zGs%
zqFsCRyVB9OS6_Mujm~-jy%t>bh4~<^`m|bju}}ZoLG<m{-~SL`Zh9$gi`?}m2B7Yt
z_Z7k!PyLHrKp)V*?I=X6m;NRn=DqdHpTP(Z>Ukpgc1ZtZ1QdPr-~I$qUp?a(8vXPe
zDDvR1A6W&30R53y(0Ev1&;l+{KS1f4Abk^MzJm3I@o?sd{`M@09MxZ00S`m;qD+_%
z)h~&H*)Tn?jw0FN`oHKXSA>2)J<XB&RV!ilm|o|Kz9{|pcL0snucI=*82z7@fE}x^
z+6?UD`rk7^;`AZpTD*P^%~L1zuTvZ`LGMJb{Y3qLG+!j??<zq~>dQ+3eM<k#CZL?w
z>mE`jDOtasDyCEPa}>}>)xY`!(9-m!w9QD@e@5Z_Gy3pAICEA%wg4g-`n%U~5i<3K
zg|Ku^&)5d+EIqpujoJEv<7mv$Gna$Q)n9)S2J`e!ehlyP^-~n;DA4y$0s6e&-<u+7
zh57_q#un-8slMrgK7j(R#rpQg!IkLyH85YQ|CmC_WqKpUFU$3VlufA6OK6{5soy}s
z{VKhY?!apOJ$jqf=#>HRw^pCF1S6~0A3TD_27Tc>;2QNC+Q41X@9u%R<FejNmGoEi
zwl`t$s=oejU|-XF&H`GK-g6uJuIpP4z;3gCAC*<L=miXLt@^j0g+iNtfNGp?=$(Fr
zUc0{FGuZ9W|2+>TI`!E+sNd8-Ls8={J$EUtMYlfQ6?(VyPfNkwcIY?!1&tnk0WGF`
z^$}Fx+ozxY6N>%%>L^$m(0{!JB7^#Ztq{4RU-T6ehxD#7kQ~-u{uzxUdLOFf9o5U|
zg*&FV({y)NKNSHl?&&){Au_Jdcm{p<^>=AQF`@sp4eAf{4)t#koz$<T74}2@G^Ldv
z>DlxN*eU%&s>zwwuO{q0hTpkp+-vaq8lbKQS4yJnGwc+jalhdgDg|;g6uyo|cf&si
z0On!PQ}Lar;kEbS?*YSX3Ws<Z29KiA+wcPY6bB7&I6ej1A;XJZX!S9?O0isDLkivN
zeuk5jDDgMUrKn<nVaN&B`LIDzj;j}Fc$FLtGK^7FKiF`NB5+3x3n{F3)bPVYa3O|o
z(m+BDUr=#Zm|^vI&<i(wO<SJ`Lth*$L>h)SQ5okkL*ILFILh!I=|>ylK89~GhOa1<
z8f)lz8GXkM<^lYMafWU5MV@%WD8-OZ7}nH7GQqHgN=p+B{`7f;B*Q(r*-jeFG?Sh(
zMADw;w4r=EoJlskMMrhg4D0AvO}fEFP3zAyhOKR2&l>iU-x-D-baXA#@Js?=&KX+f
zKqJfW1jWU(4Uhc=v>Ze2S5U|`q*E*_&%madr}KuL^o$i64vm2n8N8?9Q;A_N6=jwh
zl2aj4W_Yz1>XnAy#-UziFeBvWm|1Ozp{z}v!Igqo7Y$id=u>a_=w*;5!;l({*A0$X
zXfzv&Q-IcD_~kMbS`9{ue6$&Qx6lJ%@TN-mc0(7vIXVm<(yFl2FhzUtn}%zYWbQH;
z-iAoG;gA~SmO+*S5yx%Ac{(TAV;H&x(rc(MKxdy}IU9ES4KH7Z{(zxHf-wym&QqH9
zj$zdh%nunFDHSwq_<+i}MhurL&^T&%YZ*|+48xS2x@$;oN8>%iP8Cqb4NXN*m^4H_
zi9tLxWEVi>k;5=w42P!->(kLXZFn&q8heb#{|4w@qhA5~oQ<IY@M*uXgkDE(#@N+R
zbT{s&r^>^~uLJQkPSZqlz&Q07%zGINXvgPmG;T%XA*1vY5Fg{>AvF3L@8;v@^)sH0
z2a3PZ!C^x`!1(PsbRIUoe-xGijelQ&Opq~U8Tx{aL0dqM8mFl|D#WNyfQO;RuTuaT
zW-Ph@pTdn5&A333#y&cvdd#?mwl`5m7Hu(OjNS1VS*-CM<tdLF=hC|^-gw##C?|{x
z$39$|1mg(Rs3aO2gP@UQWc7eMZLEI-T(a>JMPXBn-Lzg$HEvL&G0j+@fJnOWH+odg
z7;h&5^sG_Z4ap4S2SebpjEh?_!faz`J0x?Ajq@RyYpmV`l4s0LKx4jfyV?Oa3XJ?U
z7{z(x-?VQnG^#0(USwRb6MYwqX`L8av2hmz8YRXJ^u8}O{__d?%8d0?@=<QwumeM@
zFs}L-B9%t_hXAWFzWxYa)EeUxK<bP?Q6<wwV}=gu^~Qx19BDAl2&9uNjmFvxv|cjS
zX`z4F$bKI#UNIKaBJry69(i%iI5!i0*Nv}H+N0UnO1Ex{vEzRrt;X@$_<h=pe<eZW
zhVd>v%<abAT=aDqw>820PUC0$;NeYUx&Vf{jK%$E>^AZ;=nF)*j6JbXylwpGb&wuo
z#&1yUH6EupWS{X_TGaL%zY9m-fYCSy+@R6zAbh%G%%Y<TBgXDVkWpio6bfU;Iv<!H
zHyUZve&0B=5rdd8x-JKKU=+}7H)&i>x79;qx&(TTY2)m_fxXA%`YB}gnsz>k5xSV#
zcA(MKlpTqyx6gEeoY`+WO81qU=`RL2caxR!!XBo8PQZAYHvA6?2TWpmS9qBY(&EtD
z6g3l=KBhVfPWqav=^HJ6rh=b9{7vy=@FKur>ZTChVbf(ZU;<5xKZn5})3#n%3N|Te
z-F(C(r^)1~DS>9`5R+&xL_$r5%eWR{rfM%33^%o~p&ns+W*ozgH2Kel!ZFj1F4&DS
z-DhG*(WbO@AaSOS3aH1MR2|SeVRBgSKqkTTga-^Jn)nx>pJd`wi07m!q6m$rOw*KI
zK5be^hk=t#=}8btF}+*>y;Rdn?LbR2t)Xpey6L&AAZJV;&jLAX8cBpmhAEMDznLZ+
zE5m$l+RzGxER)l}u#jzf<ai97Ii?T_*yfrx(8?mulzJG7`KIQ1AO)tLR2V#O((^F-
zLeu%DG0-B@&-2lE!SoNJ!840ZU9^=bF&$ID-%^t#8YpF^i1%Tz+;n#q23lc?y#!Ke
zy268Gm5JR3$!b$`mIEegOyRUit2Hgp0jV?XpjZ1v(+WBkP;c5W0?`K3&hsFRro%Mf
zTr!znfHRj(sU;Zb6%!{H+*Q*Fiq2m%z4Ix!CX+Wgdfk*sY2jwm2rXt?ObaMH*J^sc
z6^(7CwR`Ccv^PwDP?WFTq^B~a4wE;f#X3!o(JatyT17<{w@gniLf>uE`&-c1V_G4A
zNU!PeYv}7UB@_X)-{i3h;~g;hY)0RpsjLwLy<_U$0!u@t=gb(=u!%`0*hWmQRPi-x
z`gjG!U&c(j#c+7s)bs*G@0;d!qjSQvxEAg|Fx{lR;iSpOfWC(&8_nI1Otbvp%#_J#
zH6*7^OXtF;J?8b4iP~%4O2HLp^Z8Q{aWU7rfpazIXF|`-Jn|MA-OYc6LBYfPIStq0
zY3@7(69>#|gplzvdop3k+x#o7mJXWV`U2b`GiN?ve9XN9_~dI|y#SW{%%9Pn>u>IU
z5ikMfh|3T;Y@S2w{6O;(iVg;u+q94jHs7v8-w|`?GAJB1KbirN5cBzYuovnu`z(Qp
zF!Q^w;If6A7d;2GV`hF5I-|@_tc7B<Ic+A;V$2IFAQEeKx{b?q+#K%<597?^bi^Uv
zyqE*f6Xxh85J@n9k^=QavzG{sN#+H#JvnK<BY@;7^B#&4B%5#k4lc#)NT9uCs+s*i
zc$#MR)Bro(e335j8ME^q^qn>T(g>1a?yvzg)9gA06X(p26~U)0v-M|ix#m5Ca5T?c
zT!Y4Z^J;f+h2|e5AVub56w10_uBB4tV)ODYSST^iUJb6){G1~Von_{Kf<Vg6X+m6~
z3Ug91ELEESp-fhlSwOLlYO|dVQ`DF{=_ao=e?|92o%!?QP`GFgbBDk6=E9$0zQMd>
zGq4-Yf6hhUCG!H>B3?E(L;~!J`3Nm^ubRJl5q;OpXO`3ZugP3YC;qOR-}wrIX*Mr@
z0oX0(S1BFWYQDD}4!4;dlyJOZ=2PWXyLlI7I6KUj*FmAvY-~s0O>>nCNSFEfe_{TX
z`6m|iZkuEG1G>kYMK70L^I>|K_L(E;1Zcn6zn?0Z2F!0(qIJ;xh!6Mgn6FV3X~_Hq
zr2~e|(J#Z{5wj0fZjGAX;(&~qzaethyvqPD?wL<9F_>}lv!?-i-~8tUxC!$%+IK!M
zPh0}Zq&Z|5<{z4W(V_8?dF5dknlew;QYHPgnaPExdn_e~(7M;MfHL3CmR$NpTrBf1
z1I^WvP!8;UmenJ;B>OFO_2_f6Jp38N-7=qQ;XEuqgoE?6s24!wfF+z(lU|njv?%qq
za4C*)(DH5;L=IUN(f#COQBt19;cGd01)Y8t3&nf=Eo&(O7hrjG9H56S(FZZmKuh&M
zXbiHnpN2-TWfr9vk63Q|WAsNYvDx54EM4KaPN9|`=xrEgNuUT`xaDWcZbevXT_G81
zX{71un8n!{*Eh<-@B?(T!;-~;OpN90-#}t5o9Lv)am&e0h{jpIkAQ3Omh5i<dcx90
zDfR@*uk;%xTGrERKgp6rZ_1OFy<Y(Il*Ppaa@sO`94N__L;KN}VtMxnu3@U>L(00Q
zS-zYAbh>30Rp4h>9PiT0Jk#<QeZ2gfCEo>|S(f)Gw3KZbxdn|Ji=2X!xt5+`3^dOo
zUx&tgOAqa93M{jNpm5$YlkVd}%XjO*6<I!{rRD`o?-7_Uw)n(Cvcz&X1nQ-h=O~I(
zW=V4eS8l;S079|CGEFgyO3U~3!Tc)AZ$Ti{mdJeAt+DK20Ik-tfim@VmUh~gT(mqx
zzgE5Fw+k@XU`gALzD7$Ky+<xt9#OT!Wy@tM=elCKRt|$#Eu%^3yJm@?=eEgGMmyu{
zmg#W^TAMA+{$N`yzmgZNmfj|iHp?X`T)bgfP=mg9%Ps~S?XUzMgioE8kA4E^O^f6Y
za9x%N+NyP1cGAY+mL=2;eYY*$o5A&1u23~gucaylB7K&H{{p4oa`g<j0ZXGFog^Ey
z{QM0r{vFFN)o^&oVxT3#uw`ol%#T>g=Yt!y%%rbWj#=1!K)Y*+rCjPg%Z_fqj9a)|
zjOo5*&0>g5ST<5V?13eij#f-scG5YVhn6G?+di@^e;*d6ECp_moVL`~)BbOdbs`4i
z-D~Zk`a);x^}o>RV*QMk1g_RVTE@CrebXW0ZjGW@)5H3v7XEr#eLUdB0qZABc<5yf
ze*uk$tQOiC`&grBw)C}%=!{Q*_0qTS>9F<bcYqma?Z1e|AZwc*#1U-WaSp9VtP`||
zKWcS*5rYY_zDK90Lao;pfrMFijzKis+VwX?BCLf}^%`aEi-w74YwkXX#8?+nZD*|Y
zZWOrV)^w_Kh_kN#86pYRE?V#=S|{EFN|N>Ldi0&PR@0S9c35>c!KPRRc3`JlxAj8*
zjP=hqfOgh8F99+c)+ulNYME9W#e2_LTPeGpWsRW(K(_T8s>8~$E~KPHuJwK}Q1Yyg
z(N-<r`pQR8D75}gF{~o%v!%Fr7p(Owp-^g#`5C0l>bQOxwA>mWh|WrD4DGC|tZ%r&
zZnbse4d~Zc^XRZ=t#v7df9kAD1E6rxdW7oK>#Z|rr`TYvH{q%^TI&U9yktFTffrY-
z`QPBTyJ~&#9z?ELKNJD1$%+yP-1$~E)sZw?GaO@3Y_b0JA=p;yT+(Q>R(yyN-mtz!
zF|bbSwy$9Rrd3vr5q4RVqTyk;)rIcBTh@50Ot@{mBY{Y-RZD4zKI=@n*ZZwLn=qsS
z>q1&*3|ehe0d>dP;RDx(tU?c5l40v6f6D)jSVeSSjans_;LMn{Dhk|PYmpr?_pBdM
zq-fmw-4by3t=4p)J+OX4yXHyj`dje#q4f`%EgxCE4xw?%nz9hCO<QOF1cg1eU9ZEZ
zy*A};G&<X^{RMRwTLE1|SKF;EbMXA_v$@kpH1^wGT>;`|E2YhYyKVLfjOl=F9Zerz
zw#`(><!!rm6EHqD`&Mwiw#`Rj*U$C|?a2LYPf(>zfbDn6ULLmHGlL7ZZGH?QM{Ec6
z;Evj~6uAho%^!tpp|+5CihqXLYN-e|+}80QWFl;D8euomR&@e)kJ)@zVN6lBOS$kV
z+SWw>M-pRme;i)K+8oD$ecYy>1++L@<5Bd*+Y%ztcf$5}D!`I#Ppt;nN!#|5xXh<)
zV@@EaZSHiuGubAgh@&ILChq}Fx1HLHYjVc6h{7UgZ68pH=sDX@ad0@x_F4~|$+o?{
z2nKU(?G(DtwMFq@BG0zc4A6XA(7RACuq9L4<-D!<G`uLZJq$u$k?poWxC^$31yC=x
z?R7xC#Fk2vZK=byv=;`;Z0|0BiE`V$Am~@vHc|Gp()KNdW~*!^KLWej_O2FaH8$>d
zK&!QV@dnW9Y^S;)dC`_k`=NT<t}EagZ0QtJy=+@fYw;_#tU-+Bs;!FRa@TCz=_^}J
zwh&K9Ubi_)eK5jiThxcpXt8xRfwbCeHlVfHa_Dm3u>Dkp#&+9lboDxHIai_BY1=}X
z;G4E>bUw4oHd719ZrghsA$iMIRF6U2w*62JuE(~k27~Cey*dxW?z3$e#IXBqyJtat
zz}DmN2Rmr1Nr&hi+lo1GX2@oy<k5&NV;1^GZF8<ebj;?p6EJse+H{b6whY>+j@z7v
zFsA#q?>~jYgzZ~;#wKlV*+CxK<g^ZaWc!c)4`IrdvkK;?ZOdoD&>s628_>Adp1r~W
zMHl<OG?}>Cf6GPZKKr8m@M6C`jXp5tW<RwIXrA`6!{83sKXrnnm%WCTeBO3%Dw98G
z|4)pIaL7J!4+eegjlJmewSWH&`uyy2ijw==19qb^!0xsZ77p88PXRN~Uiun+fj!86
znIibX_V=mU@QD3|m!Npm{`*A?JH+mw$W*A^SP4hN?2;uA3Acx5;&MmWJ%iv=q<xn&
zd^%?D5&<;Ie)4swN86PYafz|3D4rf`FQm!qxc%9)K#8-zn+_6h|LYNb$>4<j#=9_)
zVDCEz7f;$xQ1bSaUA70<r|mnR0GDiU4g;5B|93G&Qtij6;_Qrlx(8mIwV&<+mtoI8
zgT73=!w&Q3?2%L^m}TEg2dcB}n`!HkV}I{UH0IjhxdN~}`(;`)Ir8nDQnVJ>cP7Hc
zLi;0%XB64P=K%DAeMJU5Ew=waRTCxlJCv&~wRgpWl-V6?V7}b`32n|Q?Z+tFRAu+h
zf@HP5jZ#Q8c98_?wf681DAd`Xrm<YKJLjRX-Y!}Wkp_qT1VwBb?Hx?8m+T+-U=)|_
z&-G#ySL|mgk8ssKzZBQ<n*9;QgqrMopM?H(`!`f&)of48189r=d)nHz+Fuv|X|sRw
z0OP%3KTP4`c6%BX%5~VgwJ_9am!5`txBW|+$Zy#l-gM~twte7zp!M44Qn6K^{niuc
z?6<$9hxq~fLE1G8+EeLQyJOG(5eA3ssrA4fwhx~K=!l*5B}7K;M{qW9=9qm06Y6*E
zI~*YQ?5&gNyKn#WE)*v0=_R<Z5A07p3CT%&n}gOj5AAPmgv^w^vk_?1_NXu5@E)hL
zr(k}sQz;v+IXmqOfuyU`%^T3)=QNYn8T*~Sq&J?MQx~m$+?_tA{jP_T{2(Mfo!0*c
z?toJe#ge?7R?xlb?ZlxAbkJ#(rldno{7)UAK2DjN(dp~7jh<LPr+J$o<L|VB>J0*%
z9^+%Yhn@Ho*9&x-OKXs$P7kkvggC_=1POI=q4_n;sboJy!kvP?hI)k4tbC|PI&mlf
za?I&dnpdNomMCB^+R3*NLyC23>7e+_ai`2bAsXjYQwT5OonE00=LshP?Tizgj+{VW
zqSM(bj4;Wm;B}y#bo%E1^Y2b8qG3MSX_o?eDNfHF14(sS@(QkVn$z61kW6<vwE<vf
zoL-GY-&v=x4Cu>na!CP~>7?IF@4s_SN8bT<mQyEHS>-yleGZvCr?Yg=<vX3Dy43=w
zAL$6pc_(Qw6bqdmP%U1O(;6p?;(}B2|FLu(P*Gh^-}iPG*rhD&E4#}AnxZBeQ!I&p
z6KgaYHAa&dyRk%*m}p|yRnf$yDZPjyC@NJ!r7J~1Ko9}xpaLRA0Tm01iUk3`-{gGf
za2V#^ncvL4`}VziXXZY(Vf00gKYs;<OOBs^3%kXRPyfUulsNW&3a-?#fsR66cAW7o
z6v`YUsV1)6v8E81#tO&&Ca{%`|GY$JmE(C@Ayhk#qb+rfqnhegYaQoRL%+^3a04W-
zIO3nD<E!HMt~1Cr$5~A<QSbPM76=WFmQ+mI=y>-Lz^*%LKY*i6jxiqs^M+&QYlt*E
z?xicY&9P`F`feH>y><iUmg8O8ptn1Awqw>i9KU~t&Q8Zk6xF=#821n6`Hth)Qz3cR
zabGg@yBw_@AbHPmF)hOHJJ!(J=Yiw4i69RhfBA3C<!DVMTaO&yzYCPdj=9z#J&tLE
z0DI!tJ{CiI>S(m|0opT1yCYESb==(o(C3Z|6_9!1*h-IumySl-F}`v%TLJTZj-eED
zf9)s>!eIIxXIz5Ffa6W7LLGG66^X_-j(6UGIP25sk?x|OqlSX3ek9#x-Sh>E(CDrY
z_y8h%^qoe^?eEn)Ql!;O|Nc^ldh1ud1uuN`E=$qqtGA@1QGR;cLP+}SO{+ly^wGT-
zOrYL14c_n5AEXCnkY1q0<$k>v{o9HI`XV}S5v)H=IsJqBW=nV&qQ63QLZSKvRBU)i
zU+6^Nzr*@*Z^KfU{?E0T^&|Q#R7rJIKXV2ekLjmTj5A!Xq3ZJp{oeP19jV{&Hyn-9
z_vC<!)`wH@I7Yv$5OZ-{ZzTnHLcf^2h}EB_vW_^tj1JzN)Q_b@BMJJgzk^HEfBr8$
z|C01Yv@uE6D=6}xqBnek5vJ<jRKnpi`XSaB(^-8My}Tn$KfE4XhW-~i8kMQfz5%^+
z`u}|k6IuG>AEPl_pV<lQ9KGi_sGrv#91erIdL0?e(=R^^lCRI9*vtie_7tlBEYP2J
zhD@QJr-1rJ{a>@tS*)+DL}Q8m&U`pis{dvV?3U}B>8nzqml$EGQa_8X?izi<1z4)p
z>qkSOPQTC@DA)8x3ij3O+sS-`J}?vtjrvKoAlLQMDquG0uil4<u~nZw8V1|+yQoa+
zrhZmB$Su9yNOZRAE!TnT&}(S%->Gk<CEsm*8x^<Q(c3tI+|@@}!ly31fikQ2^rI*z
zd0%gqh0o`Ke#?D`Jk-yjsqEIjwH<~Y>6wYZe5|(|4+}l`4^-3O;uC#0EvTOAr_oXO
zXL{$af!3=ZLmTDi`UDF9ywG>kCi<m*3>kc-uO9&E(~pS2$NXBqhN>3&^=oWkVnA<2
znZ`kV+)SXn(WlM;=WIx)9D$3Wi9&|1hAGw{ZU*CrRJ`PF;3A>#Ver`xgPw+si=gOb
zh*?cv2g7m7g7_FLKY)k6hTDCZU_XN^&4s_=)Lk?N7<5m87HF_eg8Dwg!nx23GEAiu
z@P0!vJroZZswo&0Y<NMdj)R8ti=iH3NH)^GHPo<@R{e(zakSw)Y<Tw=xG=-sKOu9(
zFn$^g9yM&F_f{M;m{9$7xM89T>_!;)W{5-@nhSvvWzc5BM6}_`T#y)pNCl_I4ZA6w
zeZo*lXGmfV@6kU5Ic3OSioVl^o7S}di#OOZ&`2<p?*x}<*x8M_NHSPwqA|rVxEbbC
z4NVS!Ib+Bz!(h%D>Y^Z$W|&+AyP1Yw8OS-qUdpj&85TD|A=^-C1un<nvjmvu4Y#QZ
zHP?_!x!*j)hNpneH|*R=&%cX?K+3un85Wj8=8|DZG0=()`)OrfV)&yP8l{GUJwUr`
z2%x%wGJ~xS&XgNk5;2MjgK9Yxstil#fK(ekB)uAgK>t^u)(}Rkx;n!jBQg4`1|J5E
z*9<S~;C;Pem7@&bzXro<x)d4>yY~Y7x?#-&On#H0^k;}R8@gz-(_+Ye1WT=k<!W$k
zhIIN?-82Z}Vd<7(J*9Hn4M|n-snZY`21~aM%c*SVjzOR*kGqCHMq?0N27fx1eb4Zi
zs*Ua&{yh(S##aU>6QB(kzC8_@H-<gyKwP&4*#djdwz=KV@Z7d^DKvbxEv9?7|F#i}
zAri6eRRgBv^fo;uXp*<RO9860+rG$yNanUx^yZZ8Z6E%Of#z;|f!vqu!nRj5&Z2Ef
zJsQilO`!KCH5s=Rtw3kjHq9k?^K{#<I&{9?_WdRJ<hK1O?MXehx1L5{!1h^}VCm5I
zgB0_N+&-Ft{>klMM}kY)UPtS>?Cnv5uzPX)3?8Ipd)y}wsop-1ips8TciRY&fE{C1
zun@K*EEp3My~B9tf51-JarJk!rtgs6!mx99L@$F+B|B=$&{w^qmUa}^cL><C$vSqZ
zs1W4tj(0V1t!KwYIyCljM>VZ>`gd3>;Eb!&0EOVZonk%E=;!n~!rZbTrzm>QMzGUM
zDys@}dg=!C7^e>7M2N;Y<(R@!ywkip5KVHLPKv2c^PC}?=A@weO}bNCCp0pgR$HSl
z)9I5_&^zy>qiue!(-=Ajm+#a{6-^hMR=cCGz{#c+q|oWmdJOcU(;TWaD{|Un3v$V+
znhGOIoMPwDUcA)l#|Ka>a~enMjB=+5U!t+X>D-_2snY4bIZRYJdD9oZ#wlVxL~5Om
zzm2{+Cs{Cjy5iLR6Fj`;^iMw|>z%Gpg0#UY`~^fBonk2_d&_A}6)-!UVh|8O@g)3W
zkkJN&ky#lI|E@BJX!Tgn99#nYM&>pxqnemO3STrcKZy`&WinOZZZcjf;CC{PYBY8;
z2hU(YFPOJF(C5s0Jp%D!y$nDJVhds@nT;QD0VPV_ktgBrce$;wG`#E#oE_n3q-EyF
zvlRUM-&WeJO$r=??$67{1O1DD-|%~K=5F*(@ualo)NAuGQ`44z3ApJ?Ujbsqb*icP
za!D6-XSz{+_pFK~X#eUk58c@tmqT~X&>N8Xx=o4RxrKClnzyz9f6qT0Nb%=yKD&>m
z1@F*O_uCzl(6O+8C`PsDAKD0fmqb(d{hM=;`9V&>rNtND0qBp@mjQH11ErUi?xp*~
zvd}>wEcf^df3NV3hWtwB+i+{uaJoOP{)tNXe$sfLWleh~tgM@Sgx;jPej%MG`1uA0
zg$)bojRYIlQ(@6BGlt^tUw2S$>z}z);jxEVNoA>fnZ6EacreLyNqREhQ$4E}W0D2C
z-b@BP$$Xfg_W<F`1V6)E_%RJ}5ZT8Z4}o4A!%}VSBWCIX%KtoOKBoI;A2Wx7MX#A7
zv{2i_&Kv`>m;L1dSz^2LFqxjL>mM-T#ZLbVu6nbzy@2syP3Y8tFDtQyGk$D-6$~C>
z-DwkZl#QkUZY=wTB3^N9+87u*$!?&Bz$v!x8-N*4vlVpcA)XDTKt%#O;UusV*$Zhf
zn8e=jg-kO0Ya6gr*y*&yNoC_G(R_yOZ-d>ltjl}g(%A<Ta>`)!RQ{XEzE4TjG|8V7
zDNC2gsh%c7qM(3grlj==oH-{sa1V`HM#;P#5Y3k4(IzTKBB!j*c}e9Gz~oA7Qeh%b
zlI{qYe959UaP5MmlYwG^<VUJYE0jnVLE)n0HEn>4B*9)7%O%O__aRa&>5c_-i6rDN
zaHSHK4p&{4Y>$9mndH<AxLqzW{-_0Lh2(9j=&Y2~&=#Xgl0u2HYRNNNhSW&hzlBDv
z<d<R4sFVD96OC6S7eZm_sw9#Q8(x!$3t^&Of)`ift1nTLWTPam00ys1?tc!2Cdm~y
zNZydFq1|}1#B?q!v`Bvc@B7y(IldnsNt@&X)l}V-9HWcymgMLem}r-5G6m_76gL2-
zQ*wzm(6=S!b>Qwu-jT!LT}dhJ=(;3x=}UW0lHddN`;xWvBzqv?*P`#CWc^I&bxV34
zK;e<ZQV;T2vUL}Q2zn&Sk(h)hl71?Edn%c;8I8{*2YldZujF5<W_m91c?W$jBukIO
z?n{Y1ot=0k@p=w}eUhT{XnZaCM+Azq^yf90N*C$N3g{(ESG<5;inK-#%v9<ANN{JQ
z3&ug=tn`QW|LXsws~Q25E}irktr^mSc-YO9en4N>Drv+KpjAtqu0pX!`e`vFYo&Jd
zx|17HU#h}rmdYz2*(v>bKgezAOCAbc(%Dq#aZkGIUFdnp#!_XLr|cDF;=N>yIUM!H
zKWL!(2S3?pU$pwm{xV=p0W!yN@H8C%5D^;ZWHGb}%971*2FaG)qVI2xY*sP!&&%Xg
z3zCa}3Ir2*vZ*N``Lcx<VE2No_X@Z|Sq#0%;-c)F3mS`Lt53nuC0P)?b)i`HxE_7R
z5}A89?3T)A)0=)S%X;awLyL*-D6m^iF3kpMGifI7rb+kv(7$EULl2*JlP3a5he>W5
z6go|Q{D?j+6Z2kp_}s*dMc*5fl7E2dY`QEH>Mo}9uD}adQv+qTd`vIWkbI4%Tl~@L
zXL@HOyzw{POv|=FQ`yIu%YCNnsD>=aG~xod1E!vBfC)BTMbG1drXm&8gqTjE%E&O&
zF`Ge-n10oY#-paQT|uHvbrc&rYpSMwVVdcvEg<QpV;*5<GEA$|X?{(OC#ZNc+ca@1
zI&(~CeFopon+8vV-?^s$EP?qvQ*S$P#ino5TCBu$HhmpRO&#|@;j-zINoXuH{r4_V
zDomf#M_6gPWj01%Z+c$^w;N22w5)A3Ew~JyuA6pI==6r^OG+j+o7x&FI@MyDwGuF`
zrknNw`=+TW#i(zYK1)DjhpFF0z;v3H&>iNE>97PS+%?@@0+D;B<yjyPOnWJT`OwsY
z79QQENdmlZHM_MM-iMmae+IonW;1Hgc-Sm|AIyiDC6@s6h*^uCD$<Uco%ru;w%Mv_
z=nOY2?to~7*$3Mp6Kz&?71%Lm)l~Fy-0VUb8c&#gh{w7t&TQINkdtQ1M*`)Pnf?yA
z(`G~I3{bpT+t)xzGb<enFVf9o=|n-M*?M|LoiqC<7noUQEnf8f%Qow{42|<<bLjz`
zYgQ14&OEcGO#sa|+pEPyT`-&AgvLU%arHpEX!d|oVnt?i{|4G6v*9%Q60`56P$)I)
z?*YnXvvdDLU%A=eR90GHW}wJ#rP;2Z!F8E^O@~tMnT^Jl6X&1JOu{gU56vD?0J+<2
z1HGH>k(nJm>Uzwc(pT+?+14^BJ~MktE3;m+?<s;bXtt1^QE$u^7en1yo+pE(i~Ly*
zoN<+JqS&RIe54X6?(%`1aBYvg`fDicm5+IbJ`Z{L0_Yh%<+%<RVW50FRnza2S3Csv
ze);)kC?1d(Ede<wui6d85V`%AP)w2+?}Vjfc_2OUQsq^&H$NlaM0HDN<x%e7(&S^C
zLDJ<W^bpUGucw-dOnFu#X6BrHb^#=_<O&LrWgF!Mw2aA-U&#eIFAt|fp}F$WBf#a!
zA5tzXUtT%@jSKPw4$c(Fv$N@=kekp>@}hhwtze7f-%kMcC3$BU`ikXiDOOt|-$Sv$
zQu)|5ki0BEOxI(Xynh}@xqR3kFkdM*PP_)0D!H;B!>*Q}H~~*<<fUK0e676mFNoI3
z8}^{_io8XH<W>1Px&*Gt3vYom$j|)<$wv8-X_%7h^4OQK+azDq0dhm`M92A?<?ZyI
zy%za&I<eI%Z=~3Ao4hRzdN<|28fhPJOMZ42THEFJX80&N<g4d{bjnlPVeq!Rr3IGm
z$R}h$<gVPE7DQe0ibXK7PmweL*Mby3je^2qg=Yys!xVd-V`xVdCC(VqQAO4ZkZ{Gy
z{{bvQkxl!CD8<XwAkm6qg%OG|3VW*6JFZx_1Ff-&&%OpsoWg$?uum%dH-el}n5+Y6
zyy7WUq9rQqeg#^RqL$9rW+}etfNR-`h*9wAyka$F+jAASegWns#dlP|Q>DnJg;ce|
zjyCKyio;PDb**B81-;3oPO+M5I<6?TCIaoM;(I#wc1__>jA7R+8lz#iL2;AzmA4ds
zUk7Pdw9wY1L(wn|T&H5mCK$Y}_>msJcNBLhzIj)%@+#c!QWWn2^nHbbPG>w&jNk$N
zP*F$0rEWzy9+*biBgF?4e0;3P4uruTMb#>FK2h{goa3otHWl(bQ^W=WyH|0Jp6M?X
zm6Ypzsd$fSUtTHJ(sHm*G2tRmUMmJxf%Ge`rbB%|vB?wMpkm>#;NB>lX*1w#{=EfU
zb20ZD4PtaPKS<jSH}elSfOR)tK`+nTV?O)@CTg$w_&Df$n6Hh3``+f~>4Wt#FCU9W
zUvrN&aLwQR={9fy=1(cT7-)X-FdFxnC!GRHkonXeK<_u-JP+If^I5y0e$@OkgdJqZ
z%%v3Z4L6$qauhVeymcEoqs)_Ufr~cZNS}R-`HF?$Zkn?<;r<Kro-sgkwg~+Rk}eiA
z!(q_XV*F|H-XgXgBJLKkg>ZC_h2LE0d08x@-I%w<q80Ga$Kumf!1T4~aD}A5#iy1)
z39vBsjmJRuSyWp9Cdi^F6fy@bOwZy|3$ZAlh`vw@$tJje$l@u*xWX)~mjU~T#g7YM
z>8M5CIP@K}h#n7x2#b$skrrv;W(K_|i*Kd?Gup!a1<W6}*gXl2CoJlBK_u29j1r)6
z7PE~Xf~H!q^xBg%7V3*If7Zf*ZV_n~A@p!dx428CEEyIB3m}<kVf`2+%VG<C)3Yr~
zDOs3nF?|~J@-41?1IY^(pKOBN8jJl@<y~v>n>8fsEW+rN;1!D%#o(@5EczQL*DS0)
zr{`b2#Q@!Q+AOkY5q{HxzlY9S79Z|_XuCz9959_0)7N02T^338Aonb~XhV75Vpbx|
zKd{)kA0m$|mQfk|V~ZH7fA6ulJq#24#Db&X#dC}ID4g`dLNJ5mON;5lf%3{Cv4rB!
zeHNRNVd=Gnl@+|`x2Wib`2mX{+F1BmR<8u{x4e5F`T>?-yaoxh44sC?eU=+qL4qvf
zbD+21(wcT&2Q25)w<6e*<uC~cEx&&cU?G-I@}L)LIg_rELza_Rh#a=ul0x6VFiVs9
z5Ith~r4xKRW@&y0qT!a~hk!&_22t%xq~&tj<3(AT6+$xFG9nKnjIpe#2RUIGT!l%9
zwH!v@kvK~gMf6WvuGFCMw59nX3^d--lomt@mTyxMI?-~(RFEXgUkcG^Ot!2Z1~$d=
z@F<KT)zaxRD4wyrL$8xMYZ=!G{dCLcCqO){LN0)KS@kc5q_>sh2>29ab!Z3d9=6ID
zhcSg&UH=Y^N38OE;pkDTTeO@Dx0<yFjz(COP!cQB>f1_Kh_V{k1e9o_)#C`5kFk12
z)uIVj-%^}1%}TxvB;9IKBs4Ot&e9Dd)2iWJz?4}nqcCT=6-O(^3M(T860TZR(X;WI
z)s(AnyWZ+Iikmc8CD78V(dsK6BG;`(M1yOx$`6HyH>@=GfZ1$ioJqy)EmqR2`0!e-
zKKUG8v{?oH3DKKY%ND}@TUH;g1?jNLqzz}MmDys5+_oyn0?Zw&9TWw>YxU6~C_J%h
zOa{tRtH>twJ+mtCgQLAxFZ!YI+-mPUa4)Q0Q0>Y~tC{~m<dv1&s6%U?RdON}Ut495
zMQgv+fCt<kuyWrG*9NV;`oK9WHw=NIi?Z++h`1_$poglP(w(Xw-If1LM&BMKGXY-g
zRj&REoQKk63nV?2OVm*JQg+jG$Xglw6B>P#i|1p0eU;aXDJtftT-1gU`YVS}nms@{
zno5!bm4h^;`;?1&(HEpl3rFLArBfWHEm-OC-?~WYwHYEIN^7ct4pkcIX?RHahVpEO
zl~J_42~*yF3GRrp&jJRIDywh7{4r%VrOP6eGpnfnC{kHMN5!I)>nSu7t$chDoiR#b
zE<}$jy~acFgtER0Bvz@Svpgr20zLRnDYMiNIjwa13X>48d_>u+1f}EzP!g31|2?6V
zlc&LpWaWeiV5TUq1VbcMxr#QpXOz3Kox+=Rm1Em5rgY`KM-a_WKA>n$rgG#ifSyzS
z_5g}m$_1lfK3jQ=ia>Idt#r3Nul%eK&RkNycmlLy<*vn0C{gmXKrdD9I}6NOWwkFv
z>XciktnG^O%o;RaRbI;g*fr(Hl(jb2D{tn(Zi6z4Zmf;U*BQ{buAENcxhCa$syMo#
zjHE4Qv+}*8Xlzl&p95N}GS3LKHl?0Q?rtg<OoB+ea{Fd9b|{-DH`J-@L4}9xwo<bP
z3U`#(tRQk%8GHt$OIZ*A$$LiSc0{3M_m%tUGI^jJH5D2UmF4zm>{dQ@K;t9jr|!^r
ztQ>zG&OB9)pa9`BWm+lvdX-!O6rL+5mxH`e=DI`VrE<t#V82p6bH_mYl<Q-l;9|XQ
zCmLO?e>sTZx>@fCz;NBIjr0G+nD$yb(c;6ydgcvqp4Of3!=RUS<1cj0T2FUIpO5u=
zdbImmpL`dMe%9|$p_RY&!85QMVEw;;VJXo1%NUS-*7|Q?DbA+H5`#EpGsF~_@ixP=
zpqFUlVh3lEZGLcqg;X0CV>UF-+AO9WU%Jh<k6<awX1ofb*KF>dgZ?d><SFQDw^<tt
zuEQo~CAdzTiS&uww%PqI)bH3h($l5KCdUiTJh4%I1j*+%Wg^H+n-P@$ePt7F4$^0H
zlWM?T+t||fqTlBH7+QZ0*wiMXb<pPVY}kEc^Ed%$&MJSpo?TSG(1OZUHCKebo9d&v
zFzBmF3<kEJ>cK?7gsJMN7~_a){s9d8n5vBK;NhwTw;>XtTK@&ONY(t2kc?LC_>3k&
z^;r!Rl2m0eRR4ZX^>s4LXQ>M5KvTAA=SPq!Qbo}n@ses9Re2Yy`r4siq6(&kXQ@g<
zNrTI(F{hzdrs__EUb!lfK7$I?JHNtirAoO1q)Juv1dY`y>jDg^MwLnd-6qvODqO#z
zx`x$?QP!+V{R@^_R4?72(W<iY2iK;`u7ejhRljcnxuu#v1f*T{f(i#aRPVgTm^xLO
zJK%1sM(%-!cT~GIP`|74p~O#@%C8@m?x_wnK<~b4?QC!lREgst@=%pPMFQQbN-CHz
zK2klmK<i`Gy8Te>Q87PaOixtbHe*arRR<_?`AoIy8^H9c0_bV_T&1F7#uuucbr5-}
zYOF-xE7dEi-Rx6YdxLwex|0PH{i^RM2REQPybI=?xs4Qfci|jgVM<)NfR_MsGjhA%
zf~Y(9b`4~LIawL74{}{}^9$vosetwn_nPWzj&S}qP&~>7(gX7t_ZB^c!?~#4@IHb|
zsRkFx&85{{6gP>g_oKOYIGB&&>_WjE=ls9KJe}aY-+_88mlFcBahy?o53MIT%Wolb
zid%gH+-WX^3K-(KpD78Jz`c43lE{5XHLFS7M;VYz=KhodJB3><0Zb~FL#GbTa79$w
zf0p~$87OJo=9%Eqxfa^?W^k+R;Akcndlr)CxMjo9n8kf(OaYtCef1gG9BwStMxE!5
z)50~Ed%X)9dE7cmy61CCmZR?iH<1!J1>AOu#1(RrX<c=ZOKydwBJK-1Q*((sNuj@D
zF6=|7mvHxJNl?liqCDnhZs>E2rHq?$09-k@dWaF76<kOYG%C4Gl=H9Rrc<W4np;5+
zw;JxK1w?DP^%Egd$6cn-;T0~v8RoBYEoAo^7jK2edTy-@A`RRws$*^BLjMN2&Y7fO
zEKS_m0~p{9u9#8^&79LwNVaf~lIZ;dt=!s+7-1WCn>I8zxl>f*cZ=)#0bD!RNEdkr
zH+3jn>*U<6(07}wo(_X|xLLG=y374Qh5lXK=`I+&$L%?TA>HTpQ4r|?R}u$DA9Bv~
z(b&y-RA5MtxQq30<}nvGfxdq|oHKm}Pq_V*ynD)x7r;H^uFQamUT%Pv?a#TeKjF*^
z?qnrEUve#_u=I-i(FdfDbD%KHYwp?4knHE~eFyac&L<a=gWT*>81EZS84h)4{=_&C
z7vAw(G`jMKsZ7l1#vh<{vpa7}JNi9*WGNip%fF_?kO%*Q;*g&Fd^&OB#rs@_Pu_gQ
zcJ%r1VgiUSfATsk`SD#(py$uerzCO!Kh70>fxK58EbZg3pM*#d-@Fwb?&s&q;qL)n
zbq!pwk#D9Wga`QvROc1K@1$5|D1U=a@E_uhUYM`LypEpYVf<=JFCF10eFsZN`D1j?
zKE}^I2$699(vPqd!3Wh~ERlTEe2^&KK@Vr5`C<{?$M8=ML*zI=jtU%4@WDSoFP1k}
zQI%XAzu+j)PV$|!+&IPe{SPvy`RVZ>@%*$6APIc82rm-(iuVAT#Q)k06UqF{^=M4t
z=XXOSmG`6j`We3b3yknAUq`|HH2!@GgQoMR1c+qt-iM)($^S@T=lEqtstL*Br_g>m
zo3{#s`5gW&CvfL^`>D{#<ttZ%%j4H>0LkYcu7<(|K7Sn~3wV#Qn5RPi(>1Vkk)Qb*
zc8hqt4;WuV{$r|bDCYN3HEjv6vjr*TBPe8eng5(}bY*<>F(c-(oUfq7WCdRp2hd9X
z*b~fi6+h=R(5m^tlNe|XU!%n+YWZ8=0<@0b{XSf~!asZt^H=#a2ILw)^ly-Qes>YT
z8u(ju6KdoYRMdB!|MDaBHSyct0ObZBLFJvzyj2>#f2V~n@_?mQeta278~@M*8aMe_
zv%%fsGnN3RozFY~{SLmLLJysMIIa3`^Dkzj?+)J{3eda!U=I4a_{<NXcaPUla_&BV
zz6oFt_<OVmf5;co@s)1=Q4>b}h=1oDI)Cz*Z#Q7PJ$&U74DAV@LIKRDe9R3fKI7|8
z0;ZQQr8<-6{5zBgd%=ImLE$BTkoHrr_#C>f`uJmXPk7BoeF4dSesCii2lxs0FgVD6
z;0f}EKb8tTXW^PTP+Ww0GT1Y^3ac~G>Ly&sh2QRioeZLTgh*e=>=phxf<6!7H(Et|
z3iECQ+e=tVm$kQWlZC#I@RbBZ^A#*7VN8C4W-3tpg+(fu4-oRGL?Tf5#u<(K1lAIm
zLBg$(P}nc@pMl5$qu@r-*kIux#h?!gZF2z{BK+_iBvg2H5S9)J?>9j4urTT(B*TO;
zwCg@1JoZN4QDG4UM-l`lI(w8Tbbbv-lZ1)1E=m>{iW8>@4HVN!75XT5dq!ADyX~{W
z99ko$2}UbgPNoZAQ}`!CFw28)nSzvdUgw157}(7chRlOvw$OPApgF?wd?=n5-gydz
zT;cB*Fp(!zb0GPGi7ON?2zFE^T_8kIQG21_b^zQ(p}Q7bk?;qV*j^Gk+~9AqP-mp=
zO^I-xZuX^u6IBXd7AoF_i85i}70}9s5sRQ$A$+kMFqOhC`T|r53C?h|T3AYtvl?OT
z8n{*~G}Hc|P8fIrg)74C&9HP;I8C3(HDOXZpzDQww2N#IhA)Leqp&}bo`2Vc*~ih^
zB)nIEVc!rQNFmxRWPSikEkYd&(N<wEmFTt!<EYr?rZD0FOxzO2)8)}F{JILRbqHTm
z>365F`BRA87UJne3wMN;a*XV*(EUBYx`d5%C%z}tQOM%Hpm;&?&j-R$6%0NUCegv?
zZo!m_#UBa&8IXA_jCc!U>JbJF0DU63UjX-1aPfiNXM+1NaJ|APT7NzlwylQV3&E4>
z|6U5lk753mprvAoKB0=mB)k^58EEVmejWyq0bvo={zloLaN>PfdLu;8DSc-#Wfg|z
zBGzVta}^iTs?tq-?F38i;ze2&?h$uIf!iz2r7x_9_>`7cp5iYZFySR`proL;_}L&Z
zeZ+fbKzzm56f^e|!<ItCU#zBQOn^9+%o+p5Pv{1>Pb_@~Hb`7TpUi%-i_#wl#Q2wJ
z3>JArYGnt-464u%5ud5Sg^Gm~(>)|we}cgr7Mtc`^kL#l1|A*}_tG8asJJ8*29Jr4
ze}hQ4*z`R_BE;V)IuR+}{|a1`QG7oT4o8bi-QY!xIEMCN$Hm7ZVd8|?a130m7->LX
zoOpTzG){`2+r#cD(Zv(ww74z<lJVkV`l=*|8}<P#QQXRdOA?JYU@2Lg{5{lDL>qc4
zrHZC=p>RfAWDk+EqH!F3AJW9rqtKczKBH?cL-Z^_W2R_d0mXBoO#no*L@x^6XNw<D
z?MaTf`2x(J7b|Gib4BS+^yP`02ce!Xeo1kV3*t$-bPB}S1!yc3i$lO&6#wD?T_if2
zpz)G8#rP={i^b^y7+Q(AgRo0QE(WuHS)4*Ck}{E@Dvxq8njSzEVs|eLR*IQa?_VW;
zLRWXSxc(XXYQ*n*!PSbx$H9D^xN<(o6)|!JEL;^I()#h5SVrNhdhv4;IMX0b-9*v4
zMzO*L6Lnqm&4yD=;`mP>dP7XmL%&&k5)Df&V*ezVXcechP;3)ljet)##fEk$+!E*0
zDVTO~&2|i}L;SfJCOXB5w9C0Ing>DTj#v^23wOnO3j216rIe_=Cw4!e_{)9K_a<Z>
zhz+!rcqrZ|g86Q7CoKsci9wIRJr<qzf$I^!rTgm>F_6|EPsM!NU_TSL&H;9>_)Zu^
zo{K?AaQlTgyaC)x@mE)Huf)?-QQ0SEEr8x@@f+Im^ot`tr2OB2m`=q6gJN?CMBj*h
ziy-5yPGjJri&~^ri>rFS8l0PY<vsMdtN)%3pAM*%KL9jXtv`>xgX(~>=nGNbp<HOF
zx@9K%4ylWugM_Ik?t{V+^*?lQ<fwWK1ul=N{~ijn#&9)P1G^FG<$r>WRExIIk5YTl
zt23h2=bSL>G3qk}dR)z#L-B;#Yd2tG)z?RZ#Hmv$_<T~`MQ=1arRGLK^0fMI8+=Uh
z>P8CPC8&S+2<8*j7q_D^S?#zC3MuNA-$7E1>Vlg9J)?fAfu*zRP+B&msYg)2HeK!4
z1)nn1Z`7EtO!YQO6P;5(_yGQ9so$c|d$#%lZC!HIFW-UP^Xiqqqc2zeCA~U3PmSmg
zz7A?%N)=pCYwtp&K%GX7h3c^Zuy9drbWp-Xk@^p+%DtpsVGr}g>iFxhRHE+M0hm&C
zyaA$@)u9hDm@@SedP7OMI%y|BE7YIOg!xK!JcVYf)Z-$7Qmwub1X82^ClZad>Pu9>
zTBmNh2FWYxixD7K)l>h0*=y=(V+%~wt9xfdv_XBJvObOKAljK<S5LVI(xh&tW0*J8
zvp<JV&FY`1_PRwK6$H>$_3(G;>!1!z0O(D1+$ZqqmfC6tNW0pMGAkWwFIr-Dst?mS
z)!XWEEl{|l{vj2OchyM?jF9P42c`h+p1RWtmhP+1(W%)7>Y-nPJXE_j0Igd+oOXkc
z)Sgz*f2{5kKzh{M^5EeU^~bcid#bKmfXRENw%m&e>Q(1cVZ?LwVtTvb3-wTYc=%FX
zu7KTF>NB)r>{DOgPX9^lwc1MunSS+G?*eT=9qI_tL3RIA=)X~WSHrHerurB>bkXd8
zADpXZJ}pY!G@~if>aIzq(!@QQh1USOR})B8=^mO1l>PM7G*bnKmqtw~TyIS(Vftu(
zr?i-_rWIv3sDIHgl=k%3^oKz)K+{Gyzd+3g6_DAdNut0_kj8lpMD}a)D$sX8lXC*t
z!J0=@d2&#bMIMG|`Y6U3su?>G3Wqe@1gIa@oH~O!4AZ<d6aze>IX(*HsAi20V8=8a
z{uq)mTw~J%jR=h$z0@F5<75SxD2+!36r(jEMc`sId+tHwxaQg%a3?gwDUcDXk<-!n
zIL#l!;L}OX#ElR+r3sA%*lEor3SPx)`sg{7pmC!$VxlIv2O>$Ds~-S5S+nJ5h@==b
zMkU-x)oi&1v@@Eb)#yB{nL&5GG>zSI=%;J`M=7WbP3v|vW@=7f1$R#4_YX*x<}-?T
zW^1a-p_ijMTLWj#Yohcpn5!}MgQIzxYm}wR*NmfCyP$b^1cnMUv!ei3q%mGU1NM?e
zNssRm&G9KPSgM)%BYeB8`7Q^FWg3qH_+75~=>zmtX#SzgvQl$~R(@5QkG4akS~H3Y
zQEN2I=vuGUBv3NHPP5q^eOEMpQjFxP#$+b^y{56C7)ib6$x@&+XeJta(b}jvN2d<1
zYnVU`rb**H1v1T=KzdP8izaapmRdF22H|j<X8$~JH#I?-z`mu)@dQk}#{V(~(V<yD
zW#OHg{!zfZt(i!*cy~0%7;twrDoR#$Y39?K_MT?S7^vUZjN3x%&j%XsRFH?7X)7Sw
zt?8jP^&?HZ31l8?s%g{zM5Cbt6;Cy_v;cgj+5R?M>(wOD#r9nD&<2)XXfmqN_);@K
zwFIv;HdN)<r`h2O?zLt-)%o{p8tEX@fM#G3^aeHmyFvAzZ#1uI+2E}Ga3)|}w5GIv
zb=8)2fVgR|t%4WsTIX_L@6kF@Vc=e^O*|w$wBz$2;;F5rTauS{fDTl6Yo`XF(MM}`
z7jxmO?GJ&1pY{j(e-QrKL$&A&(0cs0Ez%BT)B9KVX&-f?HAtI82l4l7-~A9S9?*VA
z%h+J8O#}Qss2whW`4DX_MbtvI_Y1)t(q{a3ct^Xz6kM3L^AXgKXx~YKzelwzXW)}O
zrk(UV%!h0D(~clQyN#+tBDD*?0vDxq{1k2*qqSvoz{Y4FQhniZ?XNVZ6WUWUh{kGT
zs9--%JNYQ=p45hY3htEFpN^B9);iGUJ6`McFNT(&?UjKfYDde^m!xf?D==AG8w!*Z
zZC^A<s@8>0H=WTsOohK^wL?DzmuA#{Fdb~VHis&FGPLo>K{B;}(J|d~+R@H%CQG{_
z7;}-WU7rr@9Bp_M?4H-|q?k~y_8f;1=4oqoqA_3l2d&{RXgw|gyFmK|g6^_HZJ{$P
zT+~`oNU2EMau$7;w9bwo#aiRmWXP0gfAhlVOSSnYVE3~2wLiQl({4Kt^X1wL-+-&o
zc2h>EQk#?vOI6yxW1v^94Y7kljke?noT=4*z6+pr+I8XZ_lmYk3WHa*dJ558(<bAz
zpR8UxY!3Pwv^%M4x=}mKNHx^gwGYc7)1-a;1-Kj9xpe5LS?f*t=oW1%MOs_6^Bthr
zrhS(_*qhpqKZ4{f?UILRY}ckyN~S}5>}{Cu)ZV3+H}q(CWWlE=+8M{8@KkF-`Jrdp
z^xr^wwF|$7!gKA!Sw_$o+UFm`(o5~R3($Y1J<tHIPg`&seXq41RPoubb)kZt0c{TL
z$_BL_(SS*?eMO<PMBCN4kY&lX*`qLsRNF&zJ)W_h8VoPa+D^+sW18)!erQa$l~+SO
z)3$^bVp+Dv1X_P)+dlpaGUsheC_$8K`xRw4^K5^W(<f>>k1F*q*p~hdv;x~dsko)k
z_BmygF4~sT^;~58@kFQ>+kO#6pQLR~5}YZuEuf?1WwsY4LZRIDO%)_7Y=3_Xjg_`f
z$3daW))WzRqpaF?1cgj$Y|E)OuGTh(BCU0{=CsniV!M$Nj#q8>7J<8FdqE4o>usf!
zFKMt1_#1tVwtY*Wcipy=-bB%4JCbJhhV3ItzBb!t(Gj8++y7B8w$*mV5;V5iF5}@-
zr|nWdIBL9Wd+-LZyKHAuX6T;n%WRmxZ(B(r{|B~fKL&Yd8%#0TZri*7XgsogvlNm&
zwry_#?TPJH52!!2?V1Gg%r@#38hdRAQz7!)_LJA}_l50qGc>-mt)$Z=uWaL}!mZEN
zkOVJY8*OLNwcc+#p#&xdY`2*~W6*Xq#WUX6j-CP-XI*<Yh>I@B4t=gV=e@AxraMY;
z6nEVTdW`PT)$~AQudeG4fO_aQP;s@V&W<v6UOHaDAiQ-0HL&2L+Z}{PU)?v9T=Uay
zT0)C0f1MYthyrxM*Ps}vOLqilkj}0Yjr(;+=v^HLbe@!I2-Y2^(yfEKUt4jpgy`ma
zLnKtUn;t8Nbn#bU>9FqAT409hey5_&BRap8&^xO8BIK=V{J)(-dWc8rmeS=BrJH*l
zU@^KAF_@s^y4oKwz!SPtBJ^T)ufD?^#OWMQ!Ix9IO<mB7*NvguMS|`MRqrI}YS(}y
z>t=6-NQ!PvIt-=i8tJ=nMz@Fd-e+||wXl$`i+Tdd4BaW?26SfX-c_RWoUW7N%UQZr
z6gtn=jl}sRS&q(mJYdf2I_M}|uI{@L(9hHLUO{8Nu1|}`3%a14Fj$~VpAWD?-NRrw
zdQrFbFdB<=pVBMHF6oNtLMYa$Xzfv=i`@W}QeEkP)gfiNk%N#a*PW$QTZQgz34E*6
zxs3x?rE{Wab+zs(he@cx2ZF{v-KtoidDyL>;JlZe6~!jK?K)i07h*SsYBdhq)l(e)
zsGS!Dt0U}shC@Bt?(P?mjI%qOgvOJ0mRIP!*(tj!+RvP}i>GHryj?5Z<P+=`&4w3=
zcH`+mn`F0bHO;Ku++4t<*j;qTbfwx|`>#sLu9l|ztlfuHTb5?G?<1Jcu={iw^fK-K
zos7l;JL4S~EVTQ@5_(m3B~<uTZI{+e@tztx_n%<5){dD8nL2QA=89eFTnz21-NzK!
zy=M1$BVg+7T24a0!EVe?FwtnYB_GaQxBCq+vL?H~HUspA-IDjA*K9YX6M8LnPElxV
zwX1&{dTn;yU%{uFcJ61<cgybmAJAv)uv5?prcS%NSwM5Mx9`H}-R-N#0CbQ2jV(~z
zYyYVMphxV#n+L_C_RlDXbIjh87VqKq?Gz=8u>b5caFO<A|K)Y<&1qvCV}FJo94G7-
z7XT&6-d_s~$@X)eV7Mvv?<vujYP1jj7oXD^do4vE&f1^21TM|KeE~d8x8LdyOL_L0
zv|Grx4|PZ11$#$(kTQF19?;6|;}(Nd*w3SP7**OgJ_Jg&z2+LtsC}*#B<t+W=q}k}
zuiXz1TkY@C_Povh7$ppD+8Yn9hNX7<++~32ut$gkcP;y+i_!SpehD2EePQ3*h$(q#
zKZN3!uk1bPe*D^gkgoN9`{xu-7_c8lr3{1i2mXP&vx6l?JX{>cl|a(fVaC_+!p$Mn
z6MgOuGosPB$05E2qu=WgZKQ0vr$ZVoMZ6p~Hh_3Ll<dM_d>oj!;kU2D=q70RIe1Y<
z)ZZa`3b+7=v7r#z=iqz@>Ol@ondsZ^(EA(g9&nJ-h9KAhsT<sw943r`WQfCUif@HF
zxUWOsVTTJ85e{?sW&!2<k2+|g(0R;3H4!i;942i=XRL$AGFUq4&~z7#ryS-C1BrLo
zpus>B9jYi0kmS&n36W%n0$MGkI9P3j!Bht+?OM+`ynPUjXC3aIgNJDjgOkyh?(pR~
zkPL@CYXO$&ko((z`F@9YY|xtRFgzP}FFJfix91`UQz}ru<Z#>p?iV{0(9OEU!MX&E
zr4DMkE-pJ%NzqvDpj?5utZ-0-qp#B8Q9k;vIc%r5HPk!&PJz}|hmlkY+vX5JrPVhb
zDrdm$TMoxt>HF92kVgyb4hO$m(C>8EPo=}R9hUwHm^%)$=o@#};bR{9T@GvKq4A!>
zWU5-Y?{NG&Bp*2ZwgX-S4*ljai&5ZbWTPHd-usxcr=u)_;hP&Xn!X+G%)wJ2dzgy<
zcE-%sVygG?V7&f?j3={(7N=g!M0&`0Gh69H@L`sID;;7I#yp_4d>XTXO2*Qee`wR6
z!QA``zGX5?=%P8txE=zR#XO^0t!zgAFGO;fKB`4O&#)}?av85Ba5#^V(d|8-8IcDC
z;{|3d9sMt0-u3}o$oSI%*^A8IlvXQa0)HMd#N-asOSfxxw!IDdd)ObSz;-WtqZf@H
z>=&+3@MQl@2j|7Uq<TAVb|*a^eAx9A2K8m9PltjZ8=V44fA-`GKnJiZEHR`&Bdg&t
z-hJ$|FnAHf=HT5+CgE&fE{1)DZNqlkWUr)%=G#ZI1)(LAeG>62U>}rx@GkrflWbNg
z0FIykeOZd%pAVsJ|70-$GE+3PdY)FC2IR$4s0e07ZztUQC5Q3~+cN1QG&)VE*u5uH
zT7t3pFeg3+m%*&B#Vi&uKfV3`pDF*ER=b0ekdZL@MsiIKhn%HLkI@jMA6Nr=pVVX*
zxJc74=ul0R>0QcCM4PVM47?cA1d6e>DNoly<c>0yPL6adpCf`~M9I>wa)|aTeI`TH
z&3Y$=ki4xusQ7H3wHw9nLam2x2N!N_wE>bRtmjbON38Ymx8X&c^>j*9pR~S2@$XaC
z-_gSMv~|V?3_aeuq#R%g)@gg8o@m|U4U%O2$v#ZZS?ggxL(-US?Y<YZ!1~}<Kr6Mj
z`vaa<TjzfV{YGnxet=%Lu80Rrll9-Fki22N{4JPow)S2L(rrCI4vmkjuU!WB*t(x$
ziapl9`+$35txSNyr`BIkgyWg@_v2u<*ZPmQ0R7y$#v6JsjMgsOAoI$);xNqjS+`K_
z_-pGCPtn+KT|pu10qa_Njnkm@yIs(DV}0dqU_0BCP;lDC=E^BZy4w8V1<u1}>I9&8
z+W68(;bl|k3O#R|X)l1{V-q?A+&-I5DxnFoxwsbN+;3xytH#H5z(x@dyTLZjEkKL0
ziKqQ^oQ*d<-%r^%RYN1iX6OLSpS9Wf2S%7}v-v(GZ`iCFkG^J`&+mb>+LRv!X|wrj
zJxIGvr6Y#jVdG&BORsDeJ;0^otn%Vu&sUW-2lo6_e;XS?52^ephY_LL^acEmRYg$F
zGf{Qy0rb;Uo?BokN457`_*AI+-4*(mRht~pSEI_KG;)J#aR9hh)eMR--d2SqL*${V
zY$fbIQ!Vy^Gp|(^wC8o@D(Fk%#a*$1A#ZNGC&e3mxVsdY@#Ws9*sULzL)!^|uC*9_
z0o>nfFzi5XNgcR-Ty-o&g1Ed}aArT3L79aETw62xg1JvANpq0vnGLWI&bbnLp`7bw
zG{$fW`nDhE+%H1m1gE3omsoCXJH2l)jyumn^dy&a3oxg+H5=gmX>N%K(RgmwNst6?
z^=ybFa^rQF{3PyQiasWD;S@<q;hbr&oys-70Xf4>?SsKIZtej{rgKg$(97Uv`e4|Z
zTrKUa&T%asAX!}Fbvo~w%}t=)c@9@a13k}8e1W0mawlmIna5defTesc>OHu2fm<02
z69wF&3N#jS2~?_kk*f&8lvH!^5g1cFH}xN2w{YI>Q0V0T9R?2{aG%Zt^iyvC8Z^G<
zQsw}<pX<K@N#g)#Isy8F-1>ZUzTvjghS-^(N2@Vk-pLFye!MM3A^iCZpFt#mH>G;K
zKz`#e^zGxru401r^M&N-0p83XV8MJog(MI1|C<ZF5FTeH@KNyLZ6J}nFO>yF@#*2<
zqK$mrAkboX<jsem8sz6jz?|UE9fcRMy!rvSIR4NeL{IU*MSwfa|9J{_<N533Fi#1*
z-wBvc<R`Ah%p~#hE=VTx;eUdp@M_B3WbsuN7;iQ|hwjF?{HURT&f~KjKrZvf$c2C@
z<8A67TEQRt9Ez3vQmR>~=XdqN{RaLKWp%IfgK^Mr;y2PawS(`lg)^P}N?O$2=I_&r
z>kfbYAw=%-Gia;Q#gCw`|2=+RG01(sx)#t6c&jGpJ>(Z}fkHQb#ApgjkNA6&;KgHp
zMGUwe{>yn7(-Z#rzkqqlS5b7jm$zL4jpuw1<?CMX=~KYH<Y)W<@`_(D93$-GKYR>F
zU-Qkh8|vqS=v>DDUr~fX4D$9AO?$&<jR3T>aCb5ET!eFx6f$!ae#`@?n{b{kU3cMR
zK05sbmtko17yfwz*8&7ZHY5WDA4i}C2?1;9Ll<840`!1zX(${G7C1fZMhO!s02VDY
zl1Pj&p$Ob@q4fbIPY8xkV8#kHQ^3UuVg&7fP6`j|p?FGI9uN0V3-bce885`df+Prs
z>flVGaI^!iB?;qcvzsi)@LWV8!<%CeIV0?%f5CHB7;_t3nsA&RwCRG8`Z9#?c3?&`
zg~O|$cTOle2}iSpHx$au7QU*act?)#+zzd%V2Felxk3SD?em23l!(a}-ueo|z92+>
zh{gip+%TY32`di4e6_G;EBb1MKTbohPFOVpjn{-2dN)D6F!VLJhr-4vOjoy%@*c=*
zVW=zm`h~qMFh3ydp~E!BLE+RQw7wBuJ43@+9Lm8{7x9nfaNku-?1Wu65ielE2P3j{
z&~A_Tm_mbl#iH-g=OG??4``m^-S>gwC4S=pb#F2M7&u??eOd<ji5_NX^cRmWg<gOd
z`z@dY#m_%L-#(+b_7bpz#8S#n?ibVP#MuFHmlMVmEE;Lieo*`<7+eTa;s6a5b+qj}
zBo-_{<6-ejIztgA)>B44PTWPSsFPyimuNgC1}q16T0BBG`FQcy-vON<=6(eAB+)tt
zW|KwZAO+l0L<4O}Q^nQ_cyUH7rrOi9;u<RAj2P2TrD3UKmhFTyXU3$K0mk#g>p#Lo
z!$)5!VB+RSKNkRHVEjXhMhuQ08;i!E3HGZ&LMN2RL+{Xp?exeAn~<0Yu(K2L+hP9V
z1ewtmGDQ<A=R>A^!U($U+?min4QO$nJ*%M_W&CUk3Bd2)w{-&jkDxL5z4@5}UTmqn
zgWua4XtB2a(?H<w5Ne_7%*+@MSQqBd4REeZeK-WX8NXpb@nJfs=+KX;q19-xk$Er`
z7zddwdM(E>rkyqs;f&i$8aY!hMPD4Vn4)|qnJW}#IK_Or22*vKDVYG!Gt4t@8V|FG
zE{z<fYdyI0%u@Q6=Q5gl=;bjHR6<e8{7y;g%gpu$V3skx&9G3;7`+P6d5xJq8ff**
zHHuX>Fp2blYGmekqwyvaPr001jOQGXc4pur^gEdOpJ0TY%)&hYz0Fims_qUmxdVN7
zncM-`?P4y)p|6Ko^$ZrCFq7%4|CHe<@bipe&p^GGS#MN<9bg(hhsGe2N+)OEFs-NH
zg)<vMk7XBDTZcwh*3Jp~ZY)pLhVJYHg4x5Kq|Me|wv+az9&GGUnD=DMC|l&k?(xJ3
zy;+g&sXpw=S&;N){U|l*$ExnbUw?M-M@G;9_9~UX2C^k|$J@sqLmnPmfp!a!{p>s*
zXb0Fb%Fze2BTXT4kkwP&KnQ#PH}r+F+!B~L#BP}eM-Q`(ROcSXy6%ThN7%}_n8Twi
z-v_(L*au^vcY?*E8n;3AL_WoPlh|R0F_>hwJpmditSg;sOJ&pOpko$$n&KhZY)%(_
zzHHbmV4r7GHo|T$>+S;3OYFEc=qqL?`9rdV-9z!NQZ_{o^~-F?w{WeDP1pv7ayBdx
z&`oUR1L)mg?Y(II(aa{VgklRjKsolCtmHlvJJ{h<q0z}U(XQ+^`wmqP-C>u0N1reI
z`y{yE#TL{+<Q_YdP8!~49Vyl4Ecwj|3LcWt6fX0Z3?B-E!IGI@qVb5NYY=v$B_Zoz
z;k0Cs4p<rEC0CDwCP-q3!;3`8_SxW)B(ErAm@L`<1dTb8?^|KwyhPsz4|65`Z^Le$
zWCR7+@+Hgv3js<(tzo`Ua{CiZ&_&5Yic%Cw{-96ml4LVw1B)f%AAl~A9J&tmE0XzD
z@S@2m`D7SiZb|+PL}!;|z9U*6OBNJE<Aub`1a=1{mzP3guk?TPLV6GB{5R<Hl%~%D
z=Ox{68791?LujAwBMsr<udj6D*Wf~>3+R<Mhol*F-#9Fl^#CPI`Yj!pI3nFjDWs!P
z<H&iCIVO$y8SY0&v*{KQDgChyFj3OeR2CgAjeH6cBTfAmeaEG{tmqPwS{R_0D(#~v
z);VbsmFDD2LubIJV(HWfs8>oCzYWZ*(tkdJr5n;!EEL+M8~V_AU+QQMkq6QR#zts7
zl>TxbY`1h5?YbUGuWrS#A4@|Sc-kW!w-p*sq*e=|KPdg*0(kL88vP2A&ay8L!!;M#
z|LD2uiZ{l>H8<J$6HsuMnf(gPJ+eKq7`+GnNgVn-@!|<cddY-nfO*SQ!)X2CBQwz5
z)K?Zk3m!jNPbN(G%lxTGEJT*z29Z$NWIA4RNOmzCFo$Ih<Zqa)#+T+&Hg6}$QQ5nZ
zkPMf7N@bN1_(zODiIfR$7+{o4O&OAC+4^m8CPwy+1yGL5JnAXmnJ61}1u{vp28ygD
z%ce|5XNqiu3}~r1vJY}bHsrq;t1KrOFln-{!{Kj+jGKT-$dt)xUwKZJO!=iO*+47o
zX3MJQU}kb;dprSlUiS7{H0H|Q*#bw4WofTruSAxdLh+YU*&PbHUzV-g15zei@DoV6
z?A2eeTOpG+0<=>0=URM*RkGFz(65mt)B~+nHflIb)X548;Pw@nj!w#7m3@&5?wV{=
zCe-U?Kh1%^4YKebVX#rQ<~Km!mYGq$<&LbMQf9`xve^3&?UDs#VlemcA6U_OU#2w&
z_Cs0pZ0L8(-VTE3BiS5U0Y8?NhNH1Z_Ej|`pU5U8!tNWHgaVPyCjYv@Q5Tcr6mfMm
zN%aM^n~D22^tqc@PK5d%lZip_(8J`dp^)@6nxs7fwwFoaG_c+#M`<1IW3ufNfcl!8
z{u7*^$vWEk9yU2<0+=w9ec9lSnE29)@~FuOiYXs6`T84h;U?Y`nT{~gQ-(9r<WC=X
z7;UoPJfLGtb`Jq}+{Bu8#V1Un7r|_-iBUHiopB}}U6|*SCSwDkc*<lOC7lXPGUwxi
zEi{=<Nt|+%{yezfViNEGjjbj&v>F*Oxl0eHIMY$lK)Yy~y8&QDrb>S_-Y{KE<$A5A
zUcOMjXL?cx*LqAxW<c+y>AW<6y)s>FJVK*4>!a!tZ?ibcd>=47nh5jZW_`4kOEEKl
zgGtCSyPXZY7tKykvEvQ1yR~q%$L!}YfO^Omu0r1d`S@n2N6Fhw;YG6i!)#!t$?Zjm
zl*(7o67;gXbR6`26ls=d^jGk6>C+BS1X6`-pyGYn$Ob8vj7H;rg(=lR2P-VrLGhsC
z`g8bwSg~;zB*PS6*g@ooV&y%E98;_dhKJz_wH*vbD>%B7#wgC|pm$txBmg8%u}%T?
z(+cfI^d&0hCxJ^*tn{OLpEHV4i@}~%TyjKbx<Vcb6B&vIy7gx&&eL^uPBEIk;$@2W
z>_I9N-`8Lgsufc$&{wAjI|~z66?16OS+D5Y4KErMAIt^V4MhlDq&F3>yCLFgeuR>~
z?&ix&!R<Bw2_bl+%+q}O7EHIl`L~V`4K#O42036pnNq+9&81H;C5Oz%#=zhabEh6!
z4&p}$+JWDTH&Wi{$0Jn5x1@~jY)j{Ug1?vLQut|k>>zYkO#T>uuZ)X9`zl2?Kv(-5
zf`y+7e}dID#s&stt&Hk7*7?}u_xh*rLG9;DDH!R7>6ZBYi;;4IhA~bU?Y6n}fZKj?
zA0T!l;Q=ml>Y54AT@Puo^{?qz{Jnb>CEATMXgXaOcY48+E3<-%>fM+^TPXT5$y6-h
z&xABm4L|_XNu@M_O!#4tLyYYwkU7lM{s8naCL1AGSrWrg?OO(O;4aYem|qGpsA5KK
zj>am+;s9;%X<9-?;&(VZg=*U(*oJ)IMY3ZkwHd`841uj^c1}GUjbnFyg~pStvF#xM
z6WKmmswT1Kx!{u7C@Q2(W8)>@(plSCAQ@~Rm0D-Ae{O>Qd3H<y6mr=$@54kMyT}cn
z&qemyW|%KxrDvgjiA^qpWErb*huw1aG?kjwunXw&sAY>U!1Fq`#pnmnE9^lV$TYHZ
zXMnrTei8((iJe2`b8YOe47i)DC#^bevCBq5znwk%-zu1`D1zNC_7Fuv@39-Htnv~2
zBp;2>Sp9w|^s;9Xp#GelNf*p(_Q!W&*ICj}H@2s8){oYoy^1YJN&Pp0gUr2HD8FHr
z(DXR7C6p0yVIR0)B(AJ#IF#MkFVbMmogEPivWMM7CyDp6Lnv(P!LD`0e0Z{#XtC|Z
zCP$&qoBfo6nm+9F>j3j*m(PMtKQ@$}kN!sXUCLAkunl&QImA}>!rQ~F_Zf7Cu>slW
zi)A-<!O}^#{_6jSx`l<b5B_o4Qphe*(3f{<4Q-c~?Pg$aIY%4#6%*Xx!pf*yKv;E@
z-f^^gJf+5e8h;*OYi{p?{95@as<&8oo6=V6ZK?qJb26pxH#ihSVdI_C`1_Z!V*&A7
zkSo--*iMHr$4!*M-kwaSAa;bjhjw>n3>{zC!&p+e_FksyTN)D+Lhrf`WImwk`hASv
z1`Y)=l3`E?W8zIP3r85^@D8|qlvz&Myl}>xDlej#E7JgToJmlE#4%BH;`=o79<99-
z87x)lnzyD~ZZ)Gijses#&egC~%V?j$ZXNUG@8BAk;K@*LW<I8BgIkOxUH<o&MN;(j
zG840**T;-E-hj*i(?#`PZ<sfef$hTn_AX$;+0A}vOlM!X{QovoIH`k^=a^Gtp_9ej
z`5kU$GZFm&%weo4xp|(c84r@nc$i>RdCX2aq@K@Qqdj&h(?v<7%gmWeP%mQ+(zQ`;
zWd5RbR|T_^S}U2iDA8NRxKgo6HIqa^fp(^pqEj8ri*LYnG7a+p+Rdz{fZZcz63y{T
zW)t1*Uonp<wBgErp8+r2*j!r6yR-KVQ1D|VJ3;)}PnW`O0K2&ulA*}Ig@GPoS53#{
z9%esp1c_!xQB6b)n@dsc<LtRdKs&*@{}<w8Yw7lw%ufCkdgs`KH!-Fx_F*P0WwZVl
zpq|4{F~FH3cIyo^USid>D=cQ`ZG_ztR!#P5SmtLy*Rm^(??R)F&7oV~6?O`3Y?|4`
za&)$^+vCvJ$`;V2+Q$CSkG`Ai4cZCaW3kMkO%JC=-vhRn!b1;P*Y7~O+55Ehdc@8f
z0rki1ni5P<59_cC3QyS4lqGx0eonWaXY8z<MzFo?k2KHE*|c5o?FGB>HavaF&iDgE
zd&PRwYPye|S`F?syP1kh``LRx0d0U4qtWLp8Mp<7!;(5$W<^ShH)AYul5lb+MY16n
zq)4)KEgBmoGbkkTP%>7JMi=Rfzi9t?R4TE9`6TIvNpL1#8bCEkRnj~<<<lZ{+6Kj^
z(l7NOucd#U{r_7)wQMs*)UV6tnUk2zhstHzWFKw8(A#C7gaPTcEN?qR?#Uk2!f3bb
z7b;nLB75u$$rrMztKoB>%qSfJ_KnO|4pDcLU;j4*1H%s=R}0*w-n1EA-rj`Hm3<WI
zS)D}d>NTIIL*}>LTQJ~F#cKT4FQILM0k2-dGcuaWT(@8PAGDmAwloaKh54IqM_!B<
za$X3<s3@Ql#904j1pa>JUJ+WunC&;g9btS|p)-crNm-ENOg24&6BxTi@IH|#rbKQM
z^8p1>GMK_1IFrfjpeN-y=FS1AXEA>dKs}o&eh!5k=1(d$JkLDH07@>?u>)KlGinI9
zd?u)v&bwY<I;o1Xfa#}Hb0MQ&3hax_SJR<i#3a*w<`NT4k-TE&uT2msVe%=!T*}l@
zb?jxPaR^8m6SWJV<;?eV5mhi-L*Ydwb9DzAtC%f?(5q(r8_`(9yi$UzW$NqceJj@)
zp97e>CMM*2%-0R3RRc@SOy%G7xiaD%c+twtiG|1=rkd)-?lRwOfJhh96NJIsV=O2-
zc%OOrJFp)xJJdjV$RIgNHwl*R0LiRwJ;2i0zvw=a$zGrjDT|#=(RE`EYq}4j`K*&8
zS_|3XYcQBg>~Y%hm$IHUP%LLtDBxPf4$^Y7jvcig3fI~9-5}D=ChUc4&XVh!<Y>i@
zFp|c4gmu{la+F<{1=VBhuLKm%KDz+n2zE5pjYhIbyJ`Iy#m?Cay=ZpeGTe({IVnVs
zvl)2W;jU9K3sz#;XTL%*j{W@#oIJ_iu!X`Y_G>ERIn8P;AQ{h|Yk_0}dnpl;iR?#r
zz$LM1*07Y!-tz;O!Y<g3zEt)lef$~hC(9}SpU+N?1k44tdl^7W*{^rO@5^jEozyR5
zN8N-*IlEydG_JB`f5QAVHj)a)>)EnYa1E?iA@thVmD4fMo9sKZ-M+>CFb8_=tdA2&
z2dnxQ3Z3kG|JU1fhgEfK`#m%J3|)^ch)OhSEJP5HBI-5z6nm^O5k!y<f{K6zMUDyt
zG$@jYqo|0zfV~_wV2kCEL@{cvg@|GV3mPv`i3R2TR^of#_rCY{eSGJf-(G80n>qXJ
zJu_=&LytVF=0$PPyUz#xh?q<dct3xH_>i0E`+LN#DYaa~Pg%p-W1de}=_kA?UEhA^
z3A6|7DQ`i0BmU$u)V+Pl+ZQ6<SG-9sJiX?xXjJ!x-*^sYJr6w($+!GUU%)%Q@LQC9
zC3dt!b7hFJ^lXW2lbA~vujOKxKWey2*gHUGwOCdOYJ=!ab2}Tw*R)7%r|_igW}z5P
zS*!!1KV@DH3Uf6ii$yK1S1l1QsWWp{l+d!dbK+-OI(%N7T?NTY!m%~rXVHTus4j~p
zv<~fxFlEt|^s4ym8VY|A!)Z^}KZSD+{9Y3|^i+xKVmEz1H$()jRk<mAh9Q`8@s#EY
ze-%e+0JntqWrSTJ;;6fJTWlzY`W?}je%6)ZIgQ`$3APWRRf)AUrmPm`({O)Zv@!LA
z;v-Q)9i$rJT@UK9NVoveC&FtR6n__eY5=uj$^^h4;@3&A{Y>baAo*69(^2gO`Xe0*
z3w8h3C|jgQ1_Dy`EtHN)(>0o!P1lbWp`MxgipFrXSa%wMmdVm>A5oo_>J6Jwi)DH<
zf5>F(j<h6jxo%EC*$zFp4<bFFw<&=}v3{cjl4ta^OMsvBb^F1r(c|aR_iK24A5mmV
z+mBF|B?r|)eVH730wODA+%1^SlTHV~TqC=sf?6xXXHoujoouxWk><-o58$^zZfuT#
zH%h+&h;*~8u!YgBGKo_#a&`uoJ7uyFMhj&oO_3JKsdu5bOKv)YYVVORP6GBy(=EV0
zIXL-!&$@Z%U<gkreG5%L%?b|v9WlXcGECg&kLUveX$SSB#=Z~=Gz`UOL~1Q8M5fW)
zY}Ec~IFA0;eaOT|c|ktm7A?p~%%Yyc%ru41S;<$ynO(jJRhwsi2l+I1iO%M9_K>;&
zOWBJ+Y7u797*?`b!WO`C6Kiu1(dV#U?{Mm@W@U6A&12{37rutArz_H0W>4q%I#y2!
zuDz_h1m4WdIUUwYn3EIqzGqkC0j2B`jlarRh%=h$7v^S0MCGiOvcGrPsA>dL!>->4
zvyKh3gv|xqG}R3bb9fkK7dP<Y%>Q0+(&|Gnmb1O7u$#lmouRv$wW)w^9;@q%kk_ys
z9)Pth*&9ALvq}$0ZebpD``N{Y&?evAY&_P@<97KY-LChtzF{ak!oC{}>L_bZ>$^<H
z*rsZ5zh|RpMFDPmltTT9)rWw(z}nKN<e%)G2bkAbKp$AU&3YAqy2BpO3aLt#v=<e)
z%MwS!N+It_i*t(jxJPtK@a{B6yPI$S5t4g&2#syfb94vn<9%!Z`%Qdo3aa)aPbq@N
zZ64Vf`s>B!zJLNTBLZa`MDj(r*eE>dSGGyK>4uiuEauRrkS!vp3-q>%vYB9R6Ti=Z
z$aZm$nq-H_T!46YirJKn$=0uSM%i+G9}O9E^i6b|#s7P(q)m$7>aCVSe}!Ii072#I
z$$qfCQXhB(Or^KB0&|sqy#Ul|eG;vd&(jZ$gWom!W9nt3%bO#q_A+b+{O*>UTY)+t
zGpUDuSk^U#!V&p^9@SPXXYGT?ahXITq?59dX%0kB%f`(iS|`u0hG>?>u5EB%WMOas
z^Sni`W1xPpcs&PE{9;ku_k9oWA+Mw1(G%`*5OLM=!*n};!PCD%K(BZX%`;_)E7zzW
zfLHTYgW+(%_l0PY;mBm-VdvhL;o9_>H?58wX+wjVQP+ylD5G!BM8TNz^Z=%@#w}2u
z_>MM`226U1&q<|};|nxDz;RH@W;mOi?TY|{bH_q!%3v29$0Sp7KOw>o@h6&S4_<N#
z^+D%1>J6=Q_RImrU$MvM=y}H(Z0&V$Gg(a*U@?oLWKI!VPy&U6tnDdiA7fS*;PfP$
zK~pW~Slk*ge`0QSfXnP>YM<+DQ9s06!TfK5s$#hopdK?*U)1yk`}iF6-m)3Aw=k72
zbb{VuJ~RY97R-O6amr#5yKiuFw8Ws%G`^gvTY~>5n-h;HUb53&VCD_W?**gvY|bv|
zH?Sz$!n1%s84PABZ`A^lY25V(SjylN=EGAace(?SZ~4kSFuZ~{vjw$_8^S=9@cg^f
z)i&W>#v>G1*ZJ~guyKR$x&w<hc_yu+Ea!(NLhDz4))i&d-1k#R-sjn$fO^CyTtr+o
z{Lo*E8F)_`JU`|68d~=iZ#EpJUvo#AgIyx>-T;<~XEgiyjTjq`I<62OePw~`f3EnT
z_xp=<i=EWldd3Roz|wP;PMzKt?0E`&*0Hh`sM??GX@9^=*2f3TRK7jruWCO{g3m0T
z?hU(3c`$WzbNQeXP+!R>(a1^hQ`f;<&#zLxw16Lu1+{@YnW&*Q^42t|yOTHahWkQ3
z(-Rs+yu(_=e2{-p4^M}<sTx!XPo}KkaX$YQJe}iiv;g8fKc9p)D&uwype}JA%Fx{8
z>pDQPoc~8TjQz@gi30N$Poxok1^>qml-=e-zNFOn9sVI@zbpCOD{z083p(?E<MSd>
zwLkd!$#DOS?>`NA&hOI=`vvcv54}46yFHjMc`Q9J>NOuQ7gc-1W2!)<ir;7{OPcun
zBZw4;aGGB$6r~Rk%n9K^vjo?Ks-yP5Eeak$=81Si6QD1|%h4!&D|%mmXu7_Xa@R_?
z8~~$*db6RRj_X&cUstA|sYckp>3&-v`KP|F8AAKoFqtk|xdsPHjju60$U#gS4M{^$
z-|YsQSzxY}ijpz;vJkV*CQRDj8v%y}a?cwy%?>$-5@Llif~L!h<Vu=6*)4nRg5o}z
zeI3+cnKS`WnB}-IC>)h579)!9WDQ+MiltLGgmzr^cmRhd<ub}?o{}9JL;ZW%j(+!N
z<nyM`J1es(nQ1DO3CE#vK{la{d>5sdh+xX(Dw>$PBC`tKU+o4zEkKJ8$)ln9(D=46
zFf33)fB5RL;EY(X1TlQJn0~+`x2=KdsJy2r9sTqow8r@EM!aKFa3M5|d-4i(|9lTc
zIlkP9p11jh<r0MT<sw=iG$A|<qJGn_!i4{a2Ov7}RU}LYOs+y{;M``2F(}3Yh9>WQ
z2u|>SrsFdtc|IgV2hwD2*rR)}5YA}MDB_21;6yg8$8pq{;owK-*g<m2GY=fc)aP1j
z{)X68I+v!-U5SEeV^%|9dRJN?7H3g~TFwZ%jZor8KErWBaaZtXJB-Egycs>gU&zd~
zM=+D^?+qI#nGI$|v<y2<6Ix3P^$F+R-3Rmv8233|pY?DbFf$~4=s@2fHy1Zo7q|b#
z3y6!I85un-AwcDE?)&lV=xIINNzTR9#og7thpVT14>wO&uYknq(_<3?LZYX2cX3e<
zb^f7^iwh3_eyIk|+x~w$v{#n}pZjn2+UehH|Nk`O2j<fTe$c`(5uMmSkUbb?FfK9-
z>2HW|G4yO_@I<PY@qd`{RM+$f)g;Qw$vh>IA8(<;&)GFK&s)NqgsX}iYeyBmOSVy?
ztqmR3v>0h&w)+>iEK}L`mLI5PRn}e1ADj?9+x8jItNZwb@c4x8p~3O7v%3!rPl!pJ
z9@jl_x^rSwxbxKM)2DTxJv}}qAuc#H95U0K6T=e{6Cf8dGg9TJ*|t>q=cTnOskXFK
zd(&(!GPYI-ymh<{cuTx3%v&ogV-_p-vwBk%w1gYfr%Sk#a+qV+NUd*YB{N1vS(!&g
zS!Z``He{S{&=>tjjQ4Hl?&<p1-+1%u9P5;EYVch{Gd1Fdv{VhLc3sSes;nFPE3fsk
zi3+L^_U1F6+Pv{qy${-2tF!%hV{_ZDY);f=)F#`SYm@DsNfq&}-dq(t<(<r()9jAA
zs8)%5wE50{yNKbIo^C$QZayAvYUDe+cRY)!kqvhCa&mt=3x32L(_mN0`2uDh$s3Ke
zLaBM9O`}BC&d0;Y)5|ryhnJ6=M`%QF&z?QQ-Mo9ay19jfg?W2~dzroL8f~?<%EK?x
z`k1B-%&4+&gm+_emA&yxFBAH?8b{~jQ$oC3;6le6X<7qe6HUWnAB{KHG|b#+++NdC
z2r=zpV+(ZDv<`&rG;J_p2ThA1?4)U}@$2VZHEl9sH%*&Qh$UYzrSU*bYe{I(%-@YP
zI$E=X>c#})D3++Y`T>emlAm!NH9(!8u{|qR4*tf@>~qzh;3pML5UX+suBxL1D~PgJ
zFa3>1e$QT6Pc(Mo#Wu>F@Sd&m2jc(8ESzZU%%9t<okYf|pFy$|^@_Ol_NsjVxZTyz
z0FYHJRXj*u-$vyTd#XAGHsX6orB@tO(@A96QS~DHuC)pQBGAQ?AQh_i0kFnL-2~V0
zu8XF*sPUo3j?7g#1wyWy8WRY)ZVLaksWY3XHV}lVQiA!amLN+x1OaSRe}Zl*njk>s
z5M-&N1VO5jpjcT=Hg-0Yexhl&)!7JRN96}vZg<wSHkyi<ga(XNJ4oaVSnX9h4pseR
zV@FvH`i7?JqKqBX&|v7CaM3hp<KH^PYBjMQ_tmtv>~EHbdI%O`Y7zq2tb71+X+G1Y
zzW3vy78C0=SSenrE)aHakmwx6LIK@WSAgL$Hbn)fkAo3u60wJ<4Fm&KDL@`Tr}LfF
z-wt)<5C+!1M@(z+K88dUO{{Y@OzX?k;Sjhu3I@|vC4q;s3WtjwcqB)n$_+!4dnx~L
zG`XW%hyt8hJE(j!hV((y5*^hmVhi<A1irE7z16S?2>YlRAX%DPO)x~ABIu|d5+tf7
zk$^1a12BAp!PNWjc92>UY3w9Vg3}5oZYWhABJyTETH}2KC9AGcP@bU15ZJ0DfUJDW
zv|O%cML?sJ__I_k!3yON4Hugj*S=Q1(Z&v}jfy6Y3)cEvRJq{r`nT#>G$QV&Dp7){
htfl}wlp8^m@*`NK76MwvjxuW4p!7d~=xYD<_g|>V{cHdL

diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su
index 8067aec..9dfcbbe 100644
--- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su
+++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su
@@ -4,7 +4,7 @@
 ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:775:6:HAL_RCC_MCOConfig	56	static
 ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:841:6:HAL_RCC_EnableCSS	4	static
 ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:850:6:HAL_RCC_DisableCSS	4	static
-../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:885:17:HAL_RCC_GetSysClockFreq	96	static
+../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:885:17:HAL_RCC_GetSysClockFreq	112	static
 ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:941:10:HAL_RCC_GetHCLKFreq	4	static
 ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:952:10:HAL_RCC_GetPCLK1Freq	8	static
 ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c:964:10:HAL_RCC_GetPCLK2Freq	8	static
diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
index 879ca1ed8a135f572ba1c5b20615241e740a066a..58d33fb73e876ef66af3d05c86e57ff97b9cc882 100644
GIT binary patch
delta 126590
zcmY&=cU)A*_x9dxw{7oO5=+$ByRmm;Z_(IW>>7JXG%+q>K~YdZ1jUN<ssc7Z!Gekn
zq$!}FAVmblt|+|E!SC;n*H3b1=bZCA=gi!@b7#)XQgC>H<KY4O8Zq4I#$j@~#PE+K
zI#s?|YR?oDl8`mLL?!wE|H&AoUn^0fSn#h*B5iH!1FekVqHVlHCRH?EFGIohI?YLB
zaz*SHPNI0ckCjNrIxHYNIa}LNDv@!D%ds%v*t`r@qLnL_tXN071`3#8wuus%&DgO8
z>=lhG7>TTdX(~SJ_T!?bODz63Y{7+*s2){%zGGW4S3G~@8fnu<aT57tss1>0awf!c
z4CgScdNnVRPx~&@F&k$v68ZG+H4_tEE|bV-e6QJ<*_}m+e5SO{MFYlVGAw6(*EM3^
zHusF;>J9aM58^+*3p+5kI{-fSd#wx8bD}~bpZC4iomop{^S_hzW_&Z068VDfy8g@-
zPaR)>-m`E7w)nej9OHXdDv>YwUYp3=MMub&ey>eooQdnt?_4vOo$rBL_FXrJ*{Vhi
z%fHv=Gwx)$LaGly2P|g%Jl%K)yP_T|k+1$P+rR|<hDg?Yw|8U)y$5>j_u4iIci9n5
zSSOWL0xr;fRb03zMT<wI@Dhn}!jOsR@$d4>4@f@Dox`;(n1Niz$@9zpr&hN3M(Uml
zxkO@@?_0r27<t<!Qi)WqbHd{xQM_m*kto~99>I#`*v(9P8E&SOV<hZ$Mn$(+!uV0m
z<$Fyo;pQw-NLV*U%EOY?v7XE-f~Yw`!g~E5Wc*l}g!N$@h)vGuL?C>bU+VZ&67J7=
ztb{$mNP9!8n&it$_`BrEG;4%Z!si<);-gTR>)cz)J@bT_^#WG$lD7h>=-*EK&m8W8
zM)Ci7P7s?eX@sYo`CAa`AW+8F85}1ArxK~;Z=oG&r0(;jCsmB(AE7Q3srx#q@gId`
z)BjahN#pl(lK=j%x=eaHgOS+(uew-bdspb0FPeLs1-WFr&^HV8Quk%j-4|KOg#WWz
zCs9*}I5gLzuhaOt*1)yo8bcxTX3q|)hKyhI7}a9wXuq)viL9Z(l3wO16&0q@)07ff
zeWk*(<`8aVL&bO1Hb(yaLm;D4G#c^&HciwrUZW6{^>7zeQiU>2<|)(mWEy$))!G;*
z&&k>!Rb4&t2+D#OPVwV@PbcjPX}Z7X8*MkHxo1mV2m8a>_*T`iVx&>v0h7dhQ{bx5
z@wlGKQ{wuugu(US1TttfO^R#K2LacTFJzxuPBsI+kye>X*p2^?cIiBlXPm?cBAIy!
z!;@rj0$u-JMAuJ8$-dhDCl%QxB-*x*K6~{gK!a>NloIdYI@29Q_j?l-*D+FZFuWIO
zFLfvP+wd?bB>NKRy0j13_YEKhpXj<E9LRFTE0Q!>NT1Jz(dV}V39GT%2{wB+!MeGT
z`_5Su^_TbL=5Q97j;STnY0F45@-MQi>_hz#pF}<M!kHMZJ|xSZZ<CF&7fA~G(`Val
za+$f3?0dZ+{;jP@%ha`gR6DsHmCp0XNH{`@2fvW}i@y?G6~;D&Wd0^<_nU2Wy;DJw
zHjT;BZ#~(3PNg75r;zs2S>k!qiX=}eNV|M6eb%m}o;Y!e+}F=1{%d2Y8SVezC3dvF
zDVa9V(e-a%G7U(f*hh>Zy3g(DvwR%2AOxe1Lel*N$(a`vis=E_k6TFcl-(4T|8<i4
z7m<x~BXTo)7+oipk)+F?^jWSaw$3TAw@XIbD562-<Yv`jqWI|^8U1&ZjKrZ7R@iI;
zt6fO)aS63`*$$Ev$B<=BATfB1r63BUNFp6fVNHKQl5=%WSXW>A{A&kds7{~|)9RXG
zuL>f^rdCAvOB*7(!jsEwb=_ODl0ILVNLNc0Sw5?iPpJ#Ek&Wn9sma;8WD0%RZThUg
zOCk2IYsRK(vdNi3?&oXC%b0lLY2iwiLH1LmmexIJBYY^XS@-E0bdf^YQ};#6`$V6^
zek9AFT>9J%qZmTmOK$S?<oMnpqWf(rY2DgWxW}SMTM<TgeO_O3dF?s5pHbKDWEI(T
zA8#k3Q+uhRo=w-ke<Y*y19W|kR~f!qQDn3BB54;iqt7=M5vgO{V|z?PHUsC9<F`90
zhzqmG*^s|T;`bw=7U@XRUnK37jfC|WLbs{>b=~vdwTvn`G&7O>Qc84(Thiz7TI#fv
z`9w54o#gEc$#QKeU7yuCUQ|k?(>9Z2MIO2N)QQ^tQw_;$ZW8KbKK0yA7t-!;M$Atx
z5oe@YBI$=gMoQq6J=C(-DRs{B2>jEXx{j@&&ofw}=(&+3MQ-H4H=91|J>AS!d-K=y
znGYZbQ;cN4VH<H4t|$4w&4{z|6*VSsJV~Y->6$j3f=h9v>pBmz-=ibBGJ$-x4yS&4
z*@b*vd`UsC{*M^StRyL%Op@s?6tltZO`<U;NOXS>1@SPATyDjy8ADSHX;YP?jk-n-
zBFEBIGPJI#Gsq?=kz6)>N;Z9W({*q@QMVS!Ms|=K?^e_2scH&z&J~ip%BIh+!tDeO
z#q0pz?@#33`wm@i+esa`l=`FIP5S)#3bn~~3|XF-Kw;f+Cerx&WaEB=Y`WRW<`dp+
zcvkvRaE^bH_S#XpX5OUW{+5tU=>uX&d|vkqHA^IymY)bV`fqBVaGQ*T<^-s(C6^(N
z<RGIF*_>%Y*CqW)+xb^&>(_~dk}V{;v^8NTt|87Tqev1uldcD=h-ak_eg0_;p(1~m
z(-?X=iNJ%qQ;ZWo)934*$XOv~<O<23`w8GZojT3dfLx}pqt6@adTvoT5sm3ZF2^~N
zgXwkOjx#CrIW&N<gVqwtw;^%P3@84r-ROEBvlxt_c|l~V9ZpwS1esQMCA#j9$$hAa
zOec&dqMolwzWyJ&{?LOQPyLNrSyoM-_syg(9a%xBf9eLq<3)r$dx$viL=r=81lecB
zP*cZYGOCc+cU~aJn>|Re|0@wi7m<V7YJ#onPNbve6JW_20%)g`{rdi7fBY2L@83$F
ztLk0?Nj20r4s$68#Vz7-nM$Z5m@X<Loob15>`X!pT~3mZjH~C54i@{~dc-lO?zORM
zGvSQCkk5T_bWL#~zMsyKeDrAg?7f<rlj=xJ%Ku0{Yz{F@UO>HErKQg<m}n{`UyUTW
z^$UGItC8cXUcuoy6?aG}nHfw`?6vQcp%NV~;OePkaqTgln)ww|NsQk62=J{Fkw(`|
zG2H5IdnIP2O3A)#YO+0(g6Qypu-TPFTC|=*^ed&$^|f^EEg{QfGcmUj$+BP(HRiV2
zPNtVXlY=BIZj_Q2PY7_VoE)6!MyBJYQHa+@Q`FsCP@sz5Wa;KkJv6Kg{UDM2LN+Il
z&~@q@>i6^u<RH9mHrJ&d^;QYSETtrBImxegBJ4V|Kr@+>n6W4&-bED3AUwoMi328t
zN{M+Cx$JkCVEkor`3=hzrQ}K{YH?)UZSU?+)Q{^Pjm~wC_{M$I?FWKHQb-gIyXT?p
z&9`E<t!VXVDSCB~;vamT7<>#3{oQ`M3hGJ9EvQUR*a_&A_VksWy5EWjr}d&IZ{D~i
z_`Ikmy+Br_(H;I<S_8S=u^uE_nV^B_*FB6P8N~tS6U`;Onc4~j>BDrmirPWu=o%D<
zn5a^~d>NnL;qwSnUe00^ILd73f|eg+n)(BOoLSr-&Q36cGGXe+G?;@}Pcm`zX7Fd4
z@(>0v#Uu=5#yG-75M!hHK`^stB$^PyG;a^?P^RSo0K%B}f1|<S%)iB;j$p>pARWo9
zi32=}SsMo-W)kgwK=m}!4n3?m!>o4(KAJfwKpDe)a0PcPGwT`ro@EZv4D1}!=_>r5
zXN+!OyTC*Tp>~mZoCNoA%ppI(;~72#!UU!{ji#5Fc0LH^GSj*mEQ!oT8g`PHkRVuI
zu`|yO!~IoeVg!mbriBRQ1LiuOCq+8be>yrlgW0hk+?h<bcp$QvNeKw_5p#JGxN{iu
zHQ;iYA7~WIV`^KYc*<nFfWtzjiw-Q$nZjKFlrRhF-BHTa?}+|=$=vq?u7a^o_zdYQ
zCYz?&ubGyg(55P;-a-i9Fa;k`yk*3E_<hHCU4ZUAGk6e$ADF7~0DNRL6{vk;W;H{g
zUzl~T;jo$seusvBW&XMVT`kjvZtoW9eVQUUNpE@}!rfB0Y61SStX4EH*aW67enWv-
zQA_ijmF8%8TGe+L+^+Wj6Q9=z{UvqgiYAFa!=gRE0uAgCeh}A=HjFTeP7{8Bv(D$}
z**(r|!78Ti>6hPbgw`s1(Uh7EY5+nmA{Y|>odPS$I{%HE(@W~-=fm+O+{$#Ib<sBF
z7>0D^PUg);G;0^5#C%NY!c5ixvYRnB!I$$WGj}T3jxqh7z~m$I-vEU5jbW3(wOu-8
zHY{DF*9RkZFX^(os2!B1_@Z`98s>%$h>{Lm0NiD%{T#lTirZ54JFF(@`>HjpfTCVc
zT3j`DoB+D^EuA6nlh43#f^#Rtw>)7bu6vk5DMAQjmM#EeJhOKrAorN=XE1`iW8QlG
zuM339Q$eWn#Hg=q-8&7fY||2N17+L5O&Cn<?WX?2Nu=#5bEWKH>4~Ow9Qh36PNx}4
z^i$`8JOte(<PbWy>yC+tqg%g3#PN$Y6nC?`<0V{sq|!vBX9P`F2E{r-JEGMA1oqo=
zN7&CC*AzC369<B4_1EUmZdho5d<&Dh2aR*s$;?~@a!<ze9xUEWD-I@p%mcY+(vS7*
zb&+0V>OzfU>OzfY>S9e`C_v>ErY`2I3<X`+fx^TuXs>yCCaw<7<hFi>Kd2jziA7M&
zrvHboYjL3=x~#3^@3?jx;{jmjGz_zf9_yCEd!Ji(AnA8(k%-ZG@Pru%b9ik_sK<O|
zKsVv%%}7zuy|O0X24%wyZScA2C;DEs{N-<4yN+lJ=lzByLq2>btso~{qVJa@(~D-r
zTNq~~oD@z>#7xwDnAsn|eUMqS9g!Vkis*%nf$tws*iSOt8vy;8so97kk~vAhC?>cP
zeorwuD%hN7juZlafnh^od6Ah$YxHYO;RXP%GqcXXGMT9fz|F~EcK!yFOlJB6_|0Nm
z+W=n7Xk7s)VfIs7N}1szEI%+I*8u-$X9hHZ!%xgnCrEcluhxgDvvl$oINT|nrHAl<
z^ac{03UBElPq6t&&!r;#K&jhNumwqfSO#6N^wjUbos~xY4U==ydFv3xdFg;SxJZ`9
zP=?}$^c&r^`_coHM#+{&H-_-B)ZT>d*%N6N;h#xwMWJ(xrB~mfRxaJGL4SRawq1k9
zILdad0NZw1F%Q5VS^jody2_s8eW~z~9eV`QgR&`2VCgU0wh@*Avak^-PRq7jho>_#
z<zjFq$vzGT{EEzm3HkTYq0!C305v^Rj`~mXwrF>=lE3l3C;h+~n7k+k#ks-P;Jp{|
zd1&ZUTo<ii{`V}_3!jMgw|qMrtZj^$xVCTE0@qI2je+kfrIbYXCiLX>`fmv&eODEs
zy9ZQ^K)i!D{K@0_8})$ZE)$dNP|VmwORV`J@1S1RVj!+7+rI(D8a4}!h*Ne$QdAMI
zZ0HQ92}=D)sIDnX7J)cLDU(6>Kq=V@XOEQYk#JPpVGqrK<y$tiH%zwhGiuRPcYf6X
zSjK3EAPZ<$#A%MdgJ*YL^lz})ud9gp-?Jad^ejhUxy<r(xOvR9Mc!QTgbAWo)l()#
z5B_INCtuv@LPiyUV!w3Xb$IiVx`lwyTl$hFMLyD>&Z9UaWoi+Zuk?pTAUh&m`T@mJ
z=?42H&>WZACZT#lT5|!WC#Bg#&~SfgvMa)jmD*3CI4j*j%j7g^0}n*;Kzb}0E;6J6
zw8G4k{*(z^wsa(|ydO$mP@*YEI*ZZ(xzhFYfIgN+c7gDTv`-c+3#67+=!mD%V->W{
zFO<eD0%?(SK4tZar5`__F(uL!eIYE9ZdnT83+cG0pm`}3I{{E3b@v0eqip+T=(fm4
z<)YXsOQH_iChIl{(eIGCS0Wf^nIFx&gJtdMiyR_zr(5+v*6=K9>9R16#r@Be$)CVs
zmTXoyqz`4zv@(1on?|XFT-jM#CFjW&&qDD;mbd`;d>Ko_*E87<GtdczvQa^(J(ulo
z30$#k??sT6$~vc_Rwi3Ouh?=~HobCQ%1)8{N|}onYOiGOpJ|O&C7WOb%^TU`)-Zi1
zyV(l(_p*t5QTr$hevhVolKn?7fG;w)TmY+O7pT48WCvBStdVI}poLrH*UqE8PV$On
z5N?+j(OADjeugHmJLRJ@&|SOae=S2JcFS)B!QUSFFEoDH-Q<B^!M0Z(`w&2P`S61<
z^^h0+4fp%yk!qNF$v^gn&Rg!#5rvODfszHja<3?u9F{+!^x9GRo@_*MO#TD4<%B#g
z2Rc9b+*rgEAfLStQ3T5GP_GBeCsW!lMBd67fH1rKTQ4BO<$rZUHB#R7N3cc77g8?c
zwET5n0ME$#_Jc4+9-WRyAXfe@4S@6V=syt51$l5Au*JzAMF1WzzxD%6F3BA<Fu5%M
zEeb76lDESwUvWh~I~jm$as!7buFJ2{eCh_)=xLDNl>1(VX^LE7M%=gM#c~vP<*oa`
z=AQidDX^u=NA&|unq0FV!KBNlQGzo=z9<bX%#t_h0hVm}7b5_V<iqx($dS8HGBr;g
z`xM1vxp_NS^5tKv(Xs-$*$pOz@;mlhped3sazs%qpVAgKCGz>$?ogD;e`yBc3wfg~
z6czGdN(ENR6IP;2UdxAQKvN}eMKim%@=Mi-{++zTW9UA}hwK61qg=BZWS`}k17P_@
zzWy#azslz<LU(<Wk2?kvN5!oQ%4%#;tS<p@t77I<&}>s2_z|(~P@EZ!zI0ajnc;Vr
z;<OY%7lk*i5B4a!a<Ft&ESm}!dljFu;bNacIT<()#g$<YdMf-bz~q2p^H6y3R>%wB
z@Ss9UGwVZ&Kl*|Cu;RDI9KL@?6g3{eA5*-(f(|~eFm!{BpF;I7fF~98AJ8MDm}P+9
zK*hr-)It>gL*Xe@QQrc~aD~zzmJy2U7ZG8UB9zvzrxXq8%Mq=JD+YCpVj#UN@%TM}
z-*bvlxrp$BA{zNwyW*naHYJhc6>ILpCP9(*7x0%Ay$%4MsL;|pD_ikuKWYyZEotqM
zt8nNCzj=y~w+QBmqQgk&@)dH*LOfO64FLR^!bTbYBE??}!hWvkQVf$4#ZY?ZmMXlj
zBTz@>v;-9PElN{wNVh6879pr@%ImZ^-=SRH9SCP-3B5jcDbL@4Cl}?bQQ&q}CQwSt
zP1&82O76<e^jh;!PP__FUP@;L00)%EC@1HmOwB?+9aQ=x!Nga2g7R*Ml?Aj6OI3RG
zMlH>*+&CGg8Oq{ksAeix{f3~jm6~2aJXD_9hFXp?Ar3UT%JFSs`B>ShHEK_kD|;Z`
z0;N)c+Eb-K*_uLSjUL=Z%4b1nQn7Mse{hy4Kh8z1Oj#6(2wx}_%Yl2T{BbfYE0p$;
zx8Uiuav}rnDkXagH1CuSDFD7#-im_hCuO?@h~l$yWd(F!mDvl?!f(pu$Pg%Mm76I8
z<j7XPh6^XQ!(HgMvVQMTi)5dXFpAB73lFE+E&bu)47+AO$YR(z(dge;cA~u{NYAl0
z?3F3bvlm(Ty~sMP1x+0Lx*>!K>^0gQy2L&l4_zYr;1)=e*t?4$yvlZ(2$O5<Ldt0;
zv-`6kyuq%gEaWY=<q7yrVGq%OdWUtUjqtl{AZ1$av*K6W!c?|6klud}*rb7|rn5El
zAZD`8T~TDQGiaj!ke%}awMT468G0|5UHb;%=do3khJV8PV{crM&n8bnXiwRyf$;l`
zb$bDa&)MhOP%CCX(VVr6y_iOw&vv6-vI@3lIE0n#2rcJ%wY9<C^dU??uzd$Z`k8fg
zg3TB9Ps*r%WB;Kqd=2|^KlpXzR&|4L3pbMz>RY+br3h^sR~QWUJGfVID4e-t%>mfO
z$?qUE7w*m$aPHx5tp?7O`{Oc-y<DqZu-wNj`xkHz?k_t%7@nMaA__0gz7<_^fO~cp
zF<s$i^+iLka=-USk<9hN7QNyI_l+{IDclgs3f|@#UV*2(-1Rpgy~pWTI85apOn@+r
zJ3j<u>0It|^m+#O;s98(xgI-#d&qfI!7_(?KgSMfF6X%y?w@c!9H%bjG_6s4#yR?e
zw2;du?&sWuLg<P)@2$X>axeRVyNvUg1nzRKrU;FB$z2FUgq57rC;(n@S3AI@ifcR;
z#T)MFQ|R7t>M}(Cp1V5~!cW|Xy_6^Z%zdV5PBj-niNLR%e@n2{a@EUFIPx{)Vd}&`
zxq;eNe*ACX-p+ed=kMSZcTnu)2OLKucJZTDBbeR%$X9T&hoAHefx7YT?tt&*Lvf-3
zlh2$TsCn=$4uQps|5%?gL<jiR*WlNOcMXTlLB1!gI}Y<M=fHM^KZCtq#c_TxO%P7-
z=V@tklAo{{jq&H(W+3c9esM2&3gWGv(1q|9pQ0AZD}O>1;k*w`%Od#GEQ%;Tq!7YW
z{I7wCBAQR@i74zb{D&#vKFg0OLvfA|S%k)9@jf()JmN>+f=v$ZcNzFRJ|GmuW4_e{
z_|50*w?Uu<yo!>qg*?+9xFS9>7GW3jv;GFIgx@;`oMrq++BJE>|JoPA3f@Y)hn0MG
zBx+T5{uzx)Z}_Xpz`x^Dens(~$94x^qx``#6rcFpzoKc?{AhCjm7g&gt*GGxa27*R
z%Xf?be2Z{u57?Z9D|f-YO<1pmZo9CyDaf3K!~~e^6jUdGa}fsSz;d_H;Vn#D1^Xm=
z0^J16A@Q{kI?{a3T?n8pU{B%hZ~*rU;gbM7Ak@>t#9LT#7=SZEr?C)53;8ra#R{?;
z=&rNEDawqT7iKI)6c+@JzA<saA}Mt7f{5gV;*v0QH&`wU8k(>s2|eux;OUAGyb#rE
zLWLHH>%#g0Fufu0lu5rSjHpCRDZ)KUsoWOEPekpW@a-B%?+fi|GxvcIy9By)p<gnD
znZi8U*~k)(w1cOI!f^}k!6RYYRCvf0oM_uEPv}<&lYF67L+n#13WV+3(TZn+zA5m9
zLN4{ib3ru_wPImv35rr7c{YS)!bB&~lnYH`Abcq(DC1cvRMB?GD`D$6kW~r81EG5(
zc+%VZop9qNJiQkVBf+frB#haG;<IqP1N>DBugYck{(Tkh(VU=0n3)GetuWdMPg_LU
zMF^clnE~M+635bl#8>=zDDX$bhf82`R9u{lV2+E1o`~XvxHA&&Pl|(RQt2;FrrA}X
zSSm#kB(}Z)lMr!FW7I;$!?Z967x~^&eE%ZEvnlWtC1%r{;FLIv7P4o=dptZvi*ISa
zI93eq4wJJY+XQ~ki_2rt-V5T%T->HOvBv`x@#4uN5MCB1wu5D&*q;_|SHyL+CvjEm
z>V;ae=oyKgxgmBuirOvFWeoh;Q^Z&Xao-V3=Ae34eC3PUeX%9YQ&Pnt+u{C!_?$NT
z(#0Kg?=!{ty})OQH8eMUC{}Gj?U9&TAGlnx8@-|P#HX*&-Y25GJxub&S<%2f6;pB%
z{WI~_bWj(GuMQ%#=e*dFG9x9To9FmWrWs*jfPWLG2LZlaRc}5D57ix-MtZ7F>_QOx
zRd4Auf|qLYQxpeOYu`ZVt=dW1Vjq>_761oT?R4<qtD5yYYKK(~3~+ly^{Z!6CzHKR
zM;M+^b!rCZek!+kFbAldKEWbTwb6togs7(Y0v)P4Jrcq@s@s$yx~m#O1L!@~3VOot
ztLD)-nyTvD8AY0^IUPB9ph}>`f4YjN;Xgyw-ijhqWyOkKk);}kgEWe4Rd+k391Bzt
z9HdWGkBZRRB9%4-MXBnA6rq)=uG4<<3)S|2P?W2Bw1oSYD#u$WDpU*C{x3PwD2y_x
zO@f~Q(lk9CJ^0g+cu1Nxy^l6D51NZ;TkLHN`OoF_K(uV`0=ib8>=zMZ>)w}P)TY;u
z5ViHEP5O4Xs5jex!j6oh!`&KOJMxs7>7>g7Y3DS`3U?XR52&uc_JMu3<CoEZUyhf+
zL3hu+kn{+g3$~ulNRKLd>1trv`>`W<`YfdsXTOWLaP8krN?-Q@Z~S01a26%u2MuZk
z$AkU75!T48UXV|Dl7i2R#&v_s4RP1tz=>%_<F6~z$Aa1+CQJ*nW6ZL#p!8=3Erl?I
zSwgoklBvGU0*(J%*m15f+s$61adHo<y#vp#tbGzq7~I&^^mg0JHs1~9K6VpjK-}3*
zln3)*d(wQvlU+vB{{3tMB@evVzyF2s0Q<%QOK<kgOB6nAxeuKBvLn>sJj{0N0O2vV
znC4~2*^`t~Ji-331)bo>HeU|10Ct~!DG-6|$xVnYh@BM*WiXpD3d#_6cxM!$?BzL#
zB8=TK4}Qbh`}IK@!8Vnmh-5F(zDX2&h;sg?*v+dUJk4^H)H}nrp-gHtdq)NjF>JVi
zB9{GUCwk{ByOQP-=h&6+?2w*kf2UW_1$H}4`!BLhS0b1=w!#x}$FnV65K{u184ukh
zcF{)^ms!bK2(PeJ^o6?0n)C?t8XHIx_3Nxpe+ZM=`TgPI2HWTmg1O1geF?v}*tJK1
zyUm{M0uOiCQLRPKG2KLaL2Cf-v!#!KNM+}$flp({cZbab_P}l2kxaHXv1PF(8DPt1
z89FBMkiCcT60_kL%IoE@`9H!km+eo<nLM^u0nW$lF7o??%}s$WpAFlDt}I}4IwFdv
z?DWQ9dBz6V>82O5O$tC$#P<9b%I9or?3rW6?B5uEOW4J<qA6t`?Ltw;hEbaI1uOpz
zx^lLNdi^C^)D5}{_OlhWN|rBx`&X>i3&m@;HF``@#V(@M`x~~h52AR>4l^UrcWkB$
zeFxsN5lL|PfsLSpY9HC@O<?ndJ^l<uH9Ii@x*B$#H!N$}=@lS#<c83e-xh8oy`;8t
z?=OMdnOozIVkft>7CINse*xgTIUT(-_HgfxL+8p(qMb-Lj-ig-%e}u(X|H`;mjxho
z=dL(I>A~?YQS;>LKLvh2H<z9rFYfg+)V#U>D5K!R{Yjx6<dTyR(+SQ#7lj|!-2;A4
zay$C~;LmM+h7Jngp3^uO$c1zCjB~Hv!6ca5tO832SBlL+yCRfxq(oO3rwBt(;oMF-
zi5J23qoYfa+{QJ)M{(t~(4FEO1ED+3?H&i=8E(OO;G(%<)TJ@p?ZqIC<@VDW;w-m=
zjv<}n_EECpJlB*%%Pw&1P9V^W+!spe$8oWg53$E{)m?#4;6~7#?-F;{AIi&IDP;>2
zxymrqlDHf?tZ;=p@EqJ%xqaKAyT<+248bIGzjX%b4KAlI*lu!H*TUo$my2C7EKC;B
zxOtnKnT~JM9nOLBdUrW_7x=r!&7}zM+qum%AWh|_m%}EF+cN~79&iU~dpMn2^9(i_
zT!Y~t&E)RlJgg#%>q;X;Hn)`K`wzM61;9Px5-G=%!@1Kbyj<?~IB@21SLseZ<{r|?
zh9{h2GXl-$g3NGV!2RwG>ZhE&CmoG=#xae7FXX}~cTvPOUI)|XoC4>Mu*|X1T&9HU
z5edsuZkr93Wn9=51oMJhcN(6`xeraCd&zB~B|!xj_5gk>xjgFFSKRwbz+ZE#XrfWY
zy$lE74L5Zfgm1YJ&+$D?t+VNHgEybH5voIc>KnAdmtRPmT!;B$O7|Y&7tw%rly~#o
z*VANgx&R^g@da|gPV&|SMB>l4r-fPoe{VL5Kt6L3iXc8<7MdQ+Uo-(7!q1~|JCt{$
zZ*mwPN(Xi#`ByF|qWIOc$9RhO+Jf3?{_P(yIm2&giWWrk?`a&1;pKbbFP2ZTj|R<I
zekkqtoa0OByL+BzDQ|dzA4wy@MgBr5B8=mA)0`ll7rR53z<Vq~OqclcVJI&1kq-b*
z<ik3nNaAZ~vVMiH3W4QSzQ<q`*Z8d$5X^Nxmfpe1e3y@)zQKzFDOGTjPmKof7VjuS
z|D^Car(koN=i8v?@9;_VUcSp;3xnl79vdTg()c!%_Dto~VW3IlC-=audca@$9f79v
z9veWG!T%fwznT0F+9=K98zU{I$mSD?^C3Tj&ILW<6Bp2!k;7YYx>}LThtu)LJic%r
z+Vq$Yq3PHYej!aM^7+eG5mNy_lD1f$@<n#URK&NS?8$R}AB_ve{N#r)Dd86k0<M%l
z91WH-{@^H>yx@}~fGg*HDR1$TZ;+2#1<yC4X>ujss1<;(__lPi>@{Ef1&AuX@ny8>
z4Zmb9gm3x&wP@2jzGDu6@A-}Nw*0{N9E~VG^0yj*^b>!$Gismldj<627e3jDD608S
ze?a$@Ki3`bZ~WbxfY<PIb>OV!XHG$cc1K|_E#|fe2M>ePN!S$v=~lr)i|uW~0xy_u
z7tZVf=?)=pENGmC%YLxjDZKB4?%E~P^Mj>}u&xxIb_;*fVUj(9*F5N4g_V2Y&`l8O
z$i!X&OL1BXHljT<ccJ|$;5_U?tC2AE6ar`}eLzT?15e(<U+bXs5oBXfJ17L4MsY|;
z9E@Omg`-4zSa8?E;Sr&^D~h8+9=+I(2}?$!^NtH&TLFGTIQJ)NenRaLcsME4n84yM
zU>PV;1PDhd)fOn&m-U9<AYn0`H4YX=(s_swLAD<uh6+VAKMxb!en#BkLboocMF<<|
zbVQ`^VhV&&Ld#CTof3LPqIO!CNr$A*2rnZLXtdCY<}Wcq>qn@?3cUxTc2@Y*AMkU6
zAD#0#FSyxh-F89f^9mte6r7hJs5oKjNRY-0fB8X}AhZaF@RIP1I`OiwyA--a;TWyE
zk_4}rAiW}7=z-c*A<7F;Toaa4>iD|gun8`bh4N6ubVEq^h~lQ8@j)=RgcHH2r3fRf
zv_E)TXuS?D?g?KGKzUyXr^I=x&~hd^Dotod-^~ZYjjpgv7d*}Ilp!3ZJ&a7@OALa^
z5{B%C!)!sTg7Bdb{0V?Z!pOc5<_G~9C~}2NHH3LWVOy{~7OXeXmM6mEVA?9r7xZt?
ziUOf{E^M9(*LFksOqfmwRSSh}>(PoLVGnKBJ{MAAU|B3ItOQMoAQ=dgQepNPn3M_5
zKS1|F2%&6xxe)O?$X*J){z8)~glQUtT`BxA2enti>)9w?3*8O~`2JN1xpegDjnIdV
zbG;Q_)7bk?2%`<{_rf{a82%u%?*jK9g`a7c=aW!FIjhe?CmMpk2ot6QP%UI$f$ppD
zZ6So;gtfH6P$Qflf!5awPw8-yqj-coY!TPHpr4#X&u<Xgw~Cu-(A_3Fo<?=M_z$JL
zcZlasz^}8&(@ykG@yb;oc8OBjg5D$M&jY|!d^`p<H_?gGTJB;Snm&1m_h@nFDf-g3
z!2$91VwiY~Eyo~UA8{nzP+#%V7j)iXar8j|j@ZTdf1x}sw)_JwPKcMC;m}Xan~xp}
z5M6Jh7AU@Z31E=;m3AMn$fq$SOzaQ|VYoPl=6MlfZ8|I?#k6POjuJ=G;^34xlg`MW
z78}wXIU_EZjzFWu5yxQ}Bg#*LC06`BkWNRQ73Wc&=A8Jl4T3o@-UtBVg19vT#YJ)K
zHR$5RpttZ8FLIy2ogj9ILG6-Q`y63k7DJxHBvFhRjSfx{EuQ5A>f4{vK2EY25Db4e
z#DN{r2RFrPSD<f+?S{ZlikQ(3B)7$0U4XtLuBQR~uDBr`B=^K@nxEYl|Df+psu;Nj
zp&(H(1howD{9qKB;@9P%&Jq{wgrjV6R0ps;6uW*zgC2=V_W8i)h#9mb$rTS+V3Q|`
zUE%Pt*m)alo`^%}haLH1gU9e&AP#8*wx{B|G60^5`)DVzP&`Wc$s+MsN8p}|u3f=d
zEG{_=vJ!D5?NXGA+$jjl#Ns0Wyb#5G;4Bwg@iZHMDdrpoX@%%=7Sc-b)d2usiTm>*
zd@b%;4n&ox%ZBiccy$B1<gNIZ5f0yp8!21)UR+Gmr4M575rBUbn{J2hli0ZhBK#~~
zSP8%v@d2%Ys>Q5aSbi1Np3r?0pPo|Un_VL=tA~!N6_?WPjH7BkWstV0vRVS+q;mZN
z-FDUZY6y3zd|$wYv+5_hO*>T|=xqHiRTk|Tx~Lv^0QYWH%l^RaQ5~e?QLd^)T2#BK
zoRl!xtNO==VD_mFy28D?>fm|_zS$nCQc4|ps$wPqv0rui3uwGljcF-=KsE0L{Ccb8
zv?b=Fn$!V)52`GiKyyfSdJu%Zs)-uF53BmqzV8v$Zkk3PRgIelvSTV&PegxQ^|J`~
zCsemP;}-g<KFx#4NtFZ5Ang7sCpuFTpju961_D(p7Q%gy%DW1+VAVg1QG}>$W8o=O
z74j9W4^x?Q00>t(--p8p)y6fTiBvTSf=QIB^j8Q^sS?y+Ij!oo37*cV(ya(4S`|x4
z_!w0QB}C7u{OhB3-ma>mZIufsKzdPiHvvVQs<r@aidTL73p5F;BWdW1OR9NMV7sic
zJqBB%>ir^gVv?$s(nVKPiL`TaRdvc0x@)TZ4sdZ@H9G)+WYywMC~l~N+X8S?6>tu^
zTdHiDMy06id<(>VTh*7=XLnRDC|z<_W&Itd_f$nJ+}~H7rlnu1>c(zFk)}$g?tY-k
zT!127^~eM9W~i>?KpN6bTff0FOQpXAUAAffz33jQdi8+AM=HP7Fv(F3r`b)eDrp#s
zC#tj4{SbG)YVKp07O0|Tq9|1LrC%i#sb)5X?zw6X4Pm7!br^(Ys!V?XU#Mo$TdYF$
zaSa?+s!ZpBd!^b!n^<pD=FxEYR^{k9_1F6L88pBBqPp`MvTD_p>9GH*3a1k+-&Ad+
zpsZ1)(!uvyRk<AQ9M#(?Rl7yK@DgfH>JIcJ-m3l>1P9yH@jn2*T^;5Kzz%gdO$VIS
z2{bP4RBy;Y_v}(9Re;k)?fC(^-RcH*I`_3leVh*IyQ+OCne3(xY5@FR_4M&z+ox`N
z5>0Ve-_3vv4|PNV0G{eR+E3W8Ui$|MFZJN<z#ULGSP2$ywO;^gKI*ewP#jcue2ES@
zq<*;ra9{P3V3-_Mw{bvmMBU}29nzy}m*xoZnEDaDOpdF29YYIGsQ;$bnV<R-?bn`E
z-=XZazxsVCECbZd+JZY!ZLuQ4AoV6X!xpTbR)|1D)Z6JqVyL?OB-$IM4x{rK;p+TR
z07R(&=nP$?dh2IcMyZP);vl}_jJlGB&S>>?8eL=5Ryu}tP8~#to6f6uQcM@rXK8r6
zsP04Szc_WrbFhq8x4I7Q1a)`==q{;CDWQK^z1#>~qWb+ha3-mLs{!DO`dte|e^tGL
z4%l8(Cy~GF>fTsq*%irZUwU$GsGD|0aZ_C#g5s9C5&h&SMLm{I5#3g={s!P3b%_<8
z?yBF>-poDq9LnU~S6`b5wp8_iQ1nciI_)RK^gunE&J?Aq`}RSRp?*q<giN({Gc2>z
zX->Fl*=iquu-G4}8S2Yi^-kKh%~MCvbM;sqM!Q{4)CU*{^VO+SVOpT>cLhbEdKG=^
zi_~-KlCEmc>tL%?JJ8P~Ua8F_e62o4@2e{HRLWt!Q9noo=Ua6*IwkT>-JuF5@72?u
zqYppW)nl8X6(7~xS0ai}>Nm8z@LAo2GACcuhIOb_tFvj@^i?fef#REbXm=Df>dkr3
z)vB9(gnLI#L?8fLG)Ela$w`w!8`@hnjVK4YP1BZ!x9yrWln&XU89oMuvnG`?zB@Gy
zk4k~xr8$^~C|oo<RzbQ)6VwPau9{Y!!if5Iul}I+&}7rzlc&au4sz|+Fk=yfm!@AN
z&<8ZD<bZi=9(Dk=kES1O9v#%UErIZm=2!Ybhp)z~9#{@*Zc-N>(Kyf{k)xVJEI5y8
z-cCn=$2I=+i;5GPzv!H&pJo$%rB7<c*y{n|uNg)&vjENFkw64$Vg?|<5KZ^rKpLu<
zeiXGZO}#wC6t0=n045QdHU<D9HHkE0Mrp=*qjpMjhbAtkHBaa;+Zj#!Mu;L>Gjs%M
zF`7r;U=pk8ScWLhYHrgk^PJ}2)-<<2uNg{bf-Y$CX`AVyCX<%`ahj1dBE@U+Lx4}v
z+@#m!CCx%gQ(e}a+Kx_0)O@CNLz3piFYtRs(}gx>uWCNWqjpVm>^K}=*KBhGJX!OF
z_Wy2ZX62yQZfY9T!0j!~hXC3FPSHr{g>hT+mLAzVntSxRyQ}F=rzh`eKJEwUea%xn
z5UH9>7BQu1GQ(l{Kx5m0K+`qj2SS*k`REK`rl!eExX99+zYScrCYX`{4>iftV3MP`
zyb)34YSx?vS)OL`Ao{uGV@((QwnFhlqw#`izGg{F#9g3qOoHiC&1O2v`Al<*mfwY%
z4S&O7k*4W8)Shb&(K@z7)1qz%LsQ=dVVP$BKmcB7ir#>wTvJPL;+L9@lv$|IWKnLh
zQuBe%w7t@lv;^G#TC;=BkymL>QrEoE#8m_MUbA{JOh0IxLQ#CwR6m05lV+R~;{L38
zNn8A1G=J0KvTBWaIKuv_`K=pp-!!XSL0Y4+&qnKOHLrtFIBMOg*S2con*p~?drpp+
zwrc}#!R-#aw(2W@&f0=qpxLQieE_vx+Jv64anWv{fi~^duH|96M{9iv8dvSy5SX}W
z<7f`*uANEiK@V+gEa0A6-&Kfdzt-t7;9lAW4rulPtz#;L-r9x_VB(|o8ILFqYPX$4
zaY$?bk%mxT?T%`&9oF8Y1j7++hfQ#JR2%aG4v%Sj(s_{M+S=LhdqR7R`od2;l_sAj
zwZeXQ^4E@|hb2J!_9aXLwLdq7Nsu=F2ynsL!E}}<MC;ZYmZ91L0)%P3se{6`f_(`5
zMraFtU=yjWppJ^t%HD(Kl(x_fE>3InKO@pJS_j(Uh}IsW--O0!t7v?S)&50OyR+Jo
zy#Sok?xn}$yjJN6_ZPGieh248t^Y8D7WX}-OWFb&OD=0$R)acG`&R(%NhE3S%tiHz
zwt{AOSG5&wKyyvIb_ckxYnM_AC0YBg5iV|Ot+T*(OPkaZQKV?+(kOXbJD83T-_cGF
z0q(9gl-4cxwS9)5ma6SR_ccu$LA%Qjv=`}Dhw0i<%4B3{GY8T!;B4*cGw}OR%g_Si
zk@gdvzRS@LXb42EcE@;_=4m$#Kz}{fW;6l*iFQGI6#3d%+PNywE|`fxpK7~H;qaMu
z?*#w~wO-FbR;1lq4C?3FmUQN$SbN_c!IWriG)|Rjr(u`Rt|-%vrP29?_8{HEa;-}_
z+VoO8&jx&jc55DrN^L#t{V85)mzRM1wKj<|;8oh0Rfy?>Rw6+#AGPUp68n>OS~-ND
zwG*g=zG&Yx1X;EA{D07W)mG9Grf=G5l)0(VF6@Mwy;eJj5RSS$I#9etx0yC0oOBNo
zq1>v=p<l3W)9t3YhqG=LtwVR}7U6(|VwbMzLKH4KADU<G*42DQgnM+eY3|^vODl%Z
zO(&g%Vy`Zr-nt$-$p{4FsY{}t9q!k?q9b`;cHL~+vpS$#{St+@&e{s3KDstdU~^D6
z*#!;{=^Bp%sjp6c3A)3&6=f)n=sHkx{<!W}+9^1pD~|%ePq!%;fRnl<B{1>VdBma!
z(50zh5~zz=gC+&(?ouiuSeJVY{z7#2m&FJpR9F20(lFht_h?0=&YlU=DBVA4sGZWa
z`xPdqb)|m-aYna=hOKDbaO^ZHVsu|=OC(nJZ4}&})onct%X2#S&M-NzGoC@%7j$<W
zp}VLXN5^2|bn*G1j@SM8D`L8=E3?O<nyCBjGCDX(7rz<dU(vOu&6lgXC33jGrt7;B
zey{5q^#FIWt}+t38@l`&2vc-g8eebgV)uaij;;-T)$ZzM6+(DVw>%ia`#K5bMN)ME
zw1JhTTR#$hALvSG6ER))-yK>3XXuh&Lz=0ZcpNSs>Xyy`;*rjh4x1d^N7{tU)h%ud
ze4fska;=Yb7TP#_qO(Z>$k(~?XlQ}%8!c9!>gKE9_n8iFF?<hnYgdD%Soe(H*Cjga
zBjU-|jkpXznJ&IDt$<(X`kn%JxvsMuZF;F2e*g|EbiD&ntJF1Uj4pYloAwpL*E)}x
zAg$81RD<S?PMw3W-|9-{gZrKCJ<X#&>S8E``AK(?R%V}d9Y?^^7v05EAgk7$mq7Sc
zH~lJV-*gdpm)jLJx&|}_s@3_1A_^ycBYIf3>issrW}AL=Bj~p4`_UVEhrW*ogwA>o
zn(gn@>q?;8rGL~8g^Ruw&181#<x`>Cqknx5LRY<;1hsv7S2`r(uGiAN^UzDv5rwDz
zEu90f@7D*7f?qHF%?Usp(1+2^xVL_06l{F-595J9s9!>l?jd~(nhE*p{W4&3RA2NF
zO*^LF_a3<8`adY8azekX06IUt%QM{9lX^ZBo$s%o-2_E|z9$Dqf%@ola0cluwcrf4
z>#vogze4nvDMcNwe;5PO2)!*2!btrBdRav2o71p$O8=SOn5XsZLAW@hH_ZfFwEoj(
z#1x}vPoQb%^wV}icV54m(li(JW5<H!qW<F(z~l6nQXq`iN2a5ep#Pb6i7x5wS7^q0
zSwA=#+==={f1pUxm&#ysMITqUkk;o=3Nu;X@D_?2`s=iOyQ!bu4i0bWZ~liOMgMsR
zbhq_C(7}N_`jQ_I+FiZta5%iDzfvDfy00Jn3xuiq-Zk)$uHTS|T82K(9*SPb)bD$a
zKFQLzY=m02KBOsZ9_l-qLHbDFi}EZv`afO3maA_z6DE234kH10tber!G*9$5jd1Z)
ze-C4^;+fu+_TLKiO=!VYq_6!Kme2JmbPT&#U!((|L|>l{c$De~?WF@?W%^dtkiOKX
zjzXVQ=sP@ti%R_%nx(zc*KY}v*LnlZRIBuThl1vfK39cad#k_d3cx%4FSI0muRmpj
z?t}g{otOKlzfLXuqTfMD@M?X~eDus${SGJKzUeg^p{vnn4X5v4tzKCMZb!p;I@Yzt
zz)`l+$&f)ecB^671hi?JAzy%QyTL}2mtBU#Q-F6d9OmGDx1k}e#P=9h({tr&n79&f
zH-jrR)ZJj70lyxG6_oMyG<dau$$mp(C8F>$Xfd$i2%;e~08(#5tFB=4G5F4h=|RJ)
zHozY;9Q+-AeGPN&pi2)Mo;^Tu#IT(<v5p#koQ2Si8J<vT@wj0=9nd>r81@9*eunEb
zZ#`+aAwfU;8``F#7GOxE*GZtExGOA!41dO<um>9&(!quhLuxXBp@zqIKpJK+mjM`V
zXh<6w5r!ed0E{#=Jp@FQ!D%9Drwjpu5ZY<O0Lqu2F)XJSX0)LN?d!!DWHe)pHMpt)
zKWpgI4}fz9r>AJrdBg2y&|NSnJrVXryCJ~|&5kn+qGNmU27%U035K(@*1BZyX$7{+
zh9R^#OEj21p_XKDnG8=?48Qh)$yLLIP;g%}e5Ik`x?!gPVY0z%G`MdVcD6_DreWtw
zP~S3iYXo?T;n{isZX1HHLU+etUqFM&T|@6<XzxA4pCdqX-(a-EMXF&g?SP~i{OWQ}
zhI>DOCf!gu9=Z&}J6Z!|8a8FaQx<v#xNJjXGlUNfc}IYIWT=fnEyrM|K`7TSmA0|-
z43p^h`;QI((rf#PA;JD0Hu;8M4#9na;h*~m=BZ)IudsP$U~>U1G=vO+Ns-~NS0H_E
zs86roVuO+ZC5BdXD&&PBcM>ei4KwK{AukQT)1Qr~Fi01ns5DHW@#2-CZ(kIz4Gw3~
z>?*@R1#oW+N88f-@2$Z@1GaaD{YT;Ay<s5zcIJa&0d@CB!+1Ig{K=3^=T<)(tTO=o
zVi4WIR&BUB1P;F%ct4nYGj#n6+%<+}-w<!DVPHAh>u6lA#=YBOY)|=lCu7%sz-={d
z;-K4RJi3{VAZ|AfrupCwqq_u3XJcYrde>O-2;uKC4x^FD#TfJu_}#{}gAm0YW2>KG
z>1td;=OWyUgI58**Es7HEcY30G^21gx_3jM9>&G=rzbp(rR^ZxZ)`OhCSJy~iGUw4
zZU?7b;cZ+>!@H01F6Gq@8hg>I?vSww9r*S&#`9>}VWXKwm?Osce_(RdIE&7f9W&Oa
zWx{cz8x1rkjB8s1;Ai~cj@n6M!BxcTZ)|)V@Brh5<>=-><AI~71sNL+MJ?F)p+4aD
z5Mya~l%dAzYruyYGw#DhxUoO&nnf5_(XpsV<55SjMHz>Eh3=HG7j^Jy<CzHv^o+4J
z?fFF;!`GrOVvN7i-^7VEwr+yrtg-Sg;OC6%ec<7|k)b5T1!K`cbnHc=wG!|+yRp$F
zaK{_Rs6dlod_hN4FBx}KqquCGO@9U<(I`&>;;QjRArRM$Rl5+{bz=lg>64AoIl$d8
zhWAHkH;tp|U4F}0Nry^OjQDi~zG}uk^vmlz#{4xX?iwfm3+j8uuMNO?-)MKZifXE{
z!$aWHj44^*eqh{3Yw2|3DoSi+7)$66<YXEfP=-Fs_){a)vW>-*qIqb{Y6p`?#`M*w
z<rv?7MlIJ^OFzlVGfo@?vd6~Wv_bX6*r5XP<{R6NLao5qaXtJ!H6E~!MfI8S60IQ$
zjgO4L7a1><BBtj?&nfU!Y|N)2xWwq*45X#TX>`=2%s7Y+6u&Tj83J6n(Une$y)^Em
zV+<9>)84368vm<+<tyX!2t@JPIHNVFtBf`sI^m7+75$Xtt+C@RPsbVc><wE(_{o?<
zQ@zi|v$W{`Vw}<hfNJAfn!JBCt_(z+-;Bow!=%PIm?rPF#@w%{IhxYx*y9#cb1D2e
znU0?aV5{jDFPLmI^*;yPc2n`6Fxg=$+yxV7({Hpy+i4mQg*NOm#n?N5#>JFKM>%$z
zBGci1k4f1IG_Izy2o!Fnna4o0*EDb#ihZV7n(?`t_!zKxn1&69iKnSAoj2QW3jG3|
zm+9Lg6bDQ*CZI>WP2n`U`j{3ihUGz1*B$7z!=@Y>?2edzu5X9(sA)P2<uQ{Vom@O_
z($WE&6DA=LLO)Yl6}V5DV*f#e{-)9mh$6t$RseUP>6a0RBFOZG){DWW>iX~-Vp_Te
zxKPt?G!+Olb){XEa8sNWCK0CQUZ9RNIme?GWpXUwf5w-}lud8n)27On0G=_eUJMt}
zrmd8;jWJ!B0-9J8<JoUkefy*~kX<z0Ga#fm)5@D@OS~yefg-`QQ9yCY^a~ALmrYw}
z&pFZ5Z5oOs)4du{UNQY<0@qbjV>)+p%~bC#EU%liH0C6mrgcONH%vb`0C3av`WSA+
zEmIpxf2WvYD8+Ew^ug|n=<k?X((jb+ns(Ff={-}E*`T>^@?Hv>RFiuIiZqiurA;1~
zVrc%AZrbnwmKmm{jnV2%Qx5%JHp_G-8M<tfiq0H8G<BsF%Og`fEx>b3XJ;UoT$BDi
zgn6dvw0?PP3O;8C_Y>1$U&NMgdO(x)0@G0q+&?u{6+`#T)b~1yLesfG1X^U`Dew5)
zG@tf#icNiWz?GPGUP5T4rp<SuD>LQMUiS-AHJw^0H_f6Sm%TKtr$1a&VLII!fJ)Q0
zQdqt+wVOwW0bZM0yaacZX(4SkzcDph2Gb9w^kHb)M^m?cz<)9=bO+mK)3)=_eKCC~
zgJrd8hzHodnr`%l!*8ZzEl{g5)zD81YEA04xFe3{HW_Hk7W1Vgs5zPaXkNY5JjWHa
zZD!dTrDUOEySerS@H@<#cLDEgu6l)FcABS*MzeRBd(hzr7xNK1yt~`{Q!;dW%s=#n
zdsp-J{s_j+{MTdD_L|SoP`%Imn1XRPiyaWXhj}`^Xgtk5Jmcrox6h$nW*>9o$)G%F
z9`G9?J7i9v44<!g06njV&2~z$9Wj5SH_}n_zG#>nGv_=+i;kOJc0qT-JpMR>_cMFb
zV}H_oo-*V9=CCV(2bf*yXiA`Y>0MX`nYRQ(7;K(j3YHLau)Q8Ug__6GFU`WtB5h@b
zn>{9hCc+#*Q@Tj=hvz7w%<gp0PMI6i9^Yv*w++FZF-J4-8*QF47Qz^FV+NM7<{Ok=
zIcq*ZvypS=D_22w-h8z^OfH!HS^;;_ym<;@iZcuU(Aps0e7pw`3Fgoxz+W;O$>y?o
zZX6Ja=4kq3Qc31NS3`HjJURk^tL7zpP`hS+Y5>i3a~7q>lg(k1(3TtK7n5Of)7&8x
zoVU!?e(3BJvpelb-8N64y~sP}-M#?aHM6bhCz|)nGigb5-|RFNU6X1KISSG=^OF7$
zJ}^H!3-{^f(ghG^nEOY-B-5PFK=;s`-~msM%%3TZoMXN%BHmncRVH+K=BvBl{;_%J
zbO@iAhti@T-@JmJp8|73T5UZw%kjpyE1sE8{EeUr&5tOdQ)CXIV^Pn|RdfWi*u0=O
zfF<TXu0vO9KA#2dGILT7=w6sR(nDQt9=#JLFU{Vuz*U%=O#)e^`5v7#d}Y@ABKp_n
z;2;31%yG1H{l@%>&fdK>&y}EP`_BAqG-%$N-#Y;R!F=ru@E^^^#}VQu^GHhKe>N|l
z0JbmYp`P}6_3c^;x7OT-X8Mj6lMS^kmJR*UGAB!eHL%}m2{eLwn<e`LblWYim*8NB
z<%<%O&K3!UyVKIC2%Wae(vps_xmcc#0bsY~h%e&YV;L(4&ebwu6)fE>yXjXTdoAxa
z!DOFh9{UlcyQP_DqxmNL9m)@QS+YDqcEIvu0m!^9PI|z7EaQVvJ7_7~h}aKVx;}=9
zuO((5bcZcJv;*}KOI0I;bkvfw1C+-s%_uQ;+_Hjx(Qv}jot9O8mNs?SHp|n`F!8qx
zrbJPI<=#6KftHo_c5o47iL3!>u%+A&frePR)36e18R-C<Fw55gsD)b^HA2fGEL~`K
zD$+9Y3)rG8<#PczWjRW#?$ef@2{1Whc|*TJiMGrNg)qh<{0Pff%g9Y==UGeSTbP`)
z45S3{MN7$aTEfIx+EAK2-tsyd$^?r)CEYJsLPQjoEgHH@iI!nBZ%(rOl!)SrMMr;f
z<EkZRD2i(q(S|6lTk<;ro^1IXf!YmATn2DAE$537{VhwMMyRD&^jpv~w=JJ36?Vrm
zcM{F)?^-^O0L?wiYdTtT-%?Hq`BY25p9n3@GGrZe4=nkV2uZi-EO4J;$zBItrllht
z<IA#iz6V^kWk3<QA6h2&0QVzH({8ZLu{5I9QLbgY3v_vwd+`YEv4z<W4^J#r4e8sH
zZ|QOaGzFIZv(R5pEj{U11<x#&S@2tEX&?YmWO)~a;<+Vk6HJONv9uH~v1HL2uhfz{
z4S+JsfTgItu!ywAE4Rc_M(w2~i$zgkX-tRuDlLCgGWV4wkxoUtwp@IRDC||1aiu`K
zv4lFHhu&H$55nf1W!?jjzPFsBf#HM2sX1El(Xy4^1)nT`&{65n7RgOG{9-v;2p83s
z==*T-)pElG?r)X?%1qT*sy$&+Yw1LLF^*QvTIjY|AJf9Z$vXNK+;6p8`<PMPX8ojr
za=Z0cnj`G6CQksu+1lq4JngjlWWxO}>x?<5xmfF;LA<-IRZURrvDTXboU7Gy845Qm
z(*wA@)?!ME?z6tn0kymJ>=)=ftUOJ#JgpsRrMTbPln%{!S?&H$AU$9m{u)(p>zp=l
z;bXnu8~B4(k+L#}tuv3H6-TUI2GovPkF^2dnAQ0O0zGamqtlNktR3kk?PqO9#~e;t
z8_$Jbf2%9)Nd{O$TB8WGHlkrX$huGlT(I?<BYHc;s<zWaJ=A($4fkPIeKuT#TYD<d
zdlA<C^rtx@t)a9ain5m71I;Px5(8*XTiei2{mxj2(f}H5jqpUgG1hWt6tUL!@c^8)
zx@Q7@&Z<(v(|PM*T1s57E*p;GqID20kmIa@1MP4hZ_U{Un*?jihTy(reaE17*&0v3
zUrMyTr%7g#_1|&ubj3O}98p}gF5C#*HR}^PUVYt~L+R>d>(QR@d&9ag3c8zC-@T~a
zvW{K_vJ`7mN}b=fvNsX-9qZd5;O<&q9;S)XJ?n&R;J$B7r+ihawGZvnrdeCiUz~Vg
z-L(b%m2UlpFM=Y&dWQD#GOeC>0m!oUr@<@RI^6>%53LL1;P8>PA7v$TtY%u*<XSh;
zQN28C`V9acTN~1^>z-JR{&1gf9fF@4*cAoVZLbm3Q)@ZxSUj_~rUQqC)?HCR6j^OF
zY(2O7-GQ#y`sNQ5CDwg6p)0i>9}X8~R#AY97uKicz?EC)g~7#3>+VG0Dy(Jg;HlE8
z^oQ=1HDW7judRC8r>U}f()Y*y#`;5d1pL;TO_TF?*2J&q?)TQ~^n3CT*2%RHezcw*
zhzLJf7fy!X&sNg_0KQnib%3tg+L%X7HP(YOQLD9<(n#uPyV(#fw%C$SAwnnH*M5j_
ztF7`Y9B#9v%AnhBdrZ&84!i9-<@23w-<CtV)0RFQwOzJ`G+A)5)k}fRZd;o-aJa{|
zmwtifYFlZAiJR>=N*L|6J*9DOpKa_PFmbnS7=tK0Y`40jy`DCAnrrO0)$>Np%eIu(
zod;}VSw!J&Q_O%rADjIK%?l3NHm3u4$QJhln(b?QV+QGA+cp8DM{MJQP#m?LqXow?
z+gbW0=yBVjA;6umZN3Q_KieTXFmTdlqa#-SHm^TX1lUHlfJvZjd;s7<wg+ud1l#@{
z3V4X^wh@3(+f@511Qlj;rC}@Frk6t*VUy5uDblu&5>-*QrvhR+W!tv_mZxpGYXCfB
ztA8BAXj@k&^izzjXGcU4YkN+IC(hb7Q>x^g?et7E^t^4^Um&|+)7Aif(e}1KYH>DS
zZxr#i?!zcwoM2l@r`|5vw$W<fvdyf8X`*d!R}@LM;bHJ}#kS@iBD`w*N~?%#HohKo
z*KPj0(ZXcg>Qiuk!{$VLS2u0be+J7f+qDe1PqBILhVZtH$%msmw&^E8cGvcvntRV?
zKA~)hFP`m>SlFc6^7n!?&6ci&@`0_W8vT`S8@nF54BHcb&pXS0wwt|Rl52~+5AHnM
z>65U0Y+E}H4hw7>Lg3=5?a$_j@R@Dpzt9!hJSh8AWLs1K+;dyuL-c5|?Oz(1N^Ill
zAYQ4hEC;$Wn~Hvh`@*&)AGLDZiMa^$rS1F*)GBOlbb_wZX3%s3{*`TIKDb}o!acVv
zH`ya8z3|R<gti^u+qThz@WJ*c{hZ>XEl&gQpKLn%N$6)=*L)OTYz--SRBhWsOWd!v
zPy0}OvxV=0hZ<W)`fCuiw%+vCb#&Og5}aEcPE#_}$zeAOuUj3~(u{qZL&#^~wmbB<
zzX970ht?@*i?c(j2Ljybuy`SqyBu6-Yu?3S934H~?I76*(mf92Xdlbfp;=3Ka&su8
zcj8`$DJr<w=kRqs3U`MQblBO$p$l#Fc{((afo#9Sh<`xs<#3Ds9>@WQn4w_tcDP$?
z2dR(4AN9d@&|%VQAPza?&>!LQb>Qf@+F^$u{)NdAhiSC5IqEPp8r;Vme*WqIadh2r
zSyo>>HCmckn)U9z_be?lHCyJ&tTY>D%N*_cS?Mb%$dC<+fGibc%N7JgWFvwgOQtND
z0wSO&`1_vzI-hgzIp1^c<$dmR?>Xl_Kp~7_qkM2UW9MG<MKCu04D+WLNo_E3nlWJk
zcZRWvvZav>0ll!I7|ST|ewOi&1`*AW{7j`WF^mSPkBeoj+Xc}$#srmI$1_H0ca*@`
zl>ifojHf?>`{x)tqXC-42>S|+$&8A708L>Gd<}n78B#aQVH$%=iKukOH)T-IU^LdE
z?>s|Q0WOoVryYG+jNc1DE-=mx(gL2%xJe&F%wf1@0yLNL7nSE-WT>U^DWB0r3BSvX
z_EPv=z+kU~NFifo2}Ft*UwgorV#XhoYc64o>mgFgI7ku0GDbovB+D87N8sTV2Db}S
zS-}ud-Q!h8Rtpp=8AUI`Ut1O997TbyF<zl0WHn>D6n1ME?oWYSXS_wvYb_)15In47
zbR2<5J;VDFup1af??bPV;ZNuE8;k|sKx<+Q{I^qNY@~<3h2cTFlUBx3Gf>(XP3Ixm
z&iIr*FnW{m*Qc104jV&Gxt~skJr$vKG2B*SXx)sJbTsN={7t#_TMWhqkX}Z+4vl?`
zO&3A>89tQ!9AH@Ka6HIpSOhY}*hPJ}8J&*ch8geBRi_b#^#aH!<KHbXbceBM0?v#v
zwpRf2F2m+A0T;&^5~^yPV7&J#Iwu*-D{$r>Lr41e8EfPi+7#nXFeD!^-WK97@{nOx
zU=-7g2s5}D#){`)@DbyechPu|IZf9v?3oQzsp7!={u@m9A*PHD$A_6(+JrhX3s!+R
zF;i{*&^W@hr^L52v#cBLyD-No1?0-iqS`w*=G^lTIm(>99ewUhZ;I1;FuC-_6;Ea?
zy$8IQ?G`xd%{>1aI3K3s3yAnKxBd&xkJ(SvKK{%%DOGliIhVHZ$C->}AOTG6LHdTk
z3Fe#h;s|6iUxQ*0^Q)cUf|(ufft+N9P-HEHnJB}Qgfh1Tg9~H&zKgzariy|yr<rro
z;qMuyGi}-<nZ{6XQB0K|+&;^Ei2@YS%oZk`iDBNNmwqfWFbjQg%q-R{Jb&@bS+t!?
zU@rH7i;2wAzaevu`P~+{mc;a?G<q`g=Y!x<m}<&*q%z;6P=6XTsuM8j%zNLVF@yQM
z9L}6)w%h>8WNInhk;R->3$P2!`CkDgn^{jW!yIP%0_f#3x4%WDF&CNP0=SsRe5C<%
za*6pWeMBms`5sN;W#(1N1{5$iAHkRknO`1(WD#>8o#u;~VmdRIFsmuJUdmh^0PHg6
zU$elKGoPSU>k8A49?A;l+hrKwRpwFpZbT(BNd@RC<_vub%65&}K8nt2<_m0Cs$u%S
z029}lFHoSimiYxehIP!ADk#=7`{*)$1M^$TAT=`oreN$1rfLaD6LU753!0gaQ&g&j
z=|Y>(R%Wvo`r4Q=RNmLl?4oSIP3EU`jj4k<GzPPsHl}V6w2Rs94@=$57w9s34>Rp1
z$Sr0y<>q>s`zc4=$COa9Q$O=%38s6186E%=gUlY<jtw!DJaD&}|7JsEn5i{_8)0fF
zH8IM3mfodzm{0D9p)scXB{*}J`856F$C*p&D496Hbfz=qB=a4rTDZp?UkmO&bAu~j
zrkGE;!tV#nIh4+R$douhWSY6bH}CgFw#TC&Vb4m>fdvQF8d@$6v4Xe22`5$(#S@RP
zlyrP@W^ugWrwc2t2_UYlr~kqnxUpt_0rFASk!8?xXPu*Tp9iaqV!@uQ(=@MMtgoMj
zf8MM&TF~di@}NVqFKdJj?tZMzw&U>ApY;JH8ji7w<^$$9Yn+Z|0j!O5nmNI8rw28V
zH6n*IK`iA5Fc{3*@IQ#0WQApdgs@z~U?P;2oCJk1*2l}B5YBpj5(*J4zfYiWid9VC
zwK>gdq!NuYtShu;MY3YLZD6BVjXBUb%W9y?i)hxtGjJw`l|m=8Sk~X)g2b`3bY_lc
zy+*T~!1|gBYZ6)GC{3|D$J#(2cu8V0cf&+7%S1=!6jpvLoJnOZw1-F<>qiPUrn3%F
zBr$_k{xeX{vp%s>Vn360jeeC`Eawh@USKV}3rpFopGMJ`!+Ne2Xt}IMsZhMgT1^R#
zJXX_vaF<x^AHZ%tYb*ogGOL-AVFfG>9hnPR%OAmf5$hwmY*5T9-2s#m7MJ!&rL4to
zK%|WICn_IocIB*#^h{r2vFIgQ!4gmnz*Uxs4aG{9uL}%TvFhjudX05vHAJde$0<!y
z!+MT#YS&py=t~l{tc9NfrH-|XVpa7l-fQS<U}d+1Yh)QT82t^_03A`9SZ|5IHM9P`
z3q!UR)-46b+sfKbH%Z%AvuUs2&N^@v+)Y*xVRx_|qlcoCwQdE_x>zM6fazx06+*9<
zb>>4f_OS*iJ=4!pkDzgYmDvWAK~@u8^d4e$uSMT&mM=xVhFMv55E)^;y9u*BYGd_n
z2YZLrlmLw}maqmgcUe;(!o_h`Q$JjsV4a}*Y?G{)>Bn}D^@2al-)FT@j(Cdo<cENH
zz$$qcA`e*&v}KxRH6DY=4C_@2OFd$Z*#qn#`^7F0d-jG}_~gJ2IgBA4V%rY90pAX@
z4?hWPN4EbAG@RH8RIqh~J^CqRoY_wogSfC=--ba~wuoLTZtRppaQi6x{z{;^v&X8S
z;K4p`0q4n%qh-pAJ@*!z@n&yphHE}-TLv0^*(p^3^J7~XaK@i)Z=?O{F*b)H)W_MS
zv=a|t54{DM6YOq!Z3eP^ec@UV`_d7(7R;Xa5$v91M|}?L5ca!C7=0-F`YPy!vGEk*
z!DGKmDWnK?Ed?k~vExsJoMwAVp?8M;+D34Z?24xV9mVc<_g%AZo-O|(tjDm2uE1<8
zyNh0zaqMU5tQ^l?L8sdUb~M%aC9-X=z?XCE28!e)vA?9XB$@p@9hFnq^Y4MAvKLpv
zi8QvaKP;rP&GRw740c}`B+s+=QT<;gJFW^SS?u}rm52-MUK>SJve_I;mF2KClmX3U
ze@^4P$c|W!zC89UTHh|QRTQJjXLpI=?`8JrXJ{;7AEBC^LiQ*0HYj3`(VnoFeXbS$
zma#WAqp_TAqH8@@*q&65P{AJJLg6aAhE|43_6Oy(gQ#N9rOJ|P?6<8Dt!4-R_Z3U_
z(mZHfX9sq|i(2+-dT#638@ynmo_&n!I~&*;O&C)ndrb?-4fYRoox6$sa|jfg*#q{N
zgci0dJq@jF{w7#xV>g@tN;}()j;uG?ayErPJJ`~PK<i{bPPJfNY&Y8Fce4jpVZ1$T
z&Mu7N7Q29k-OJ|Dwy}@Bs{{)DZ2L>FG{8PP9}0u)J(Rl~V*f)i)7$I^uc2?4okpke
z5%xEifHKPdd=|(Z_KGl|jIp}~R9tkIefN2wjk8C8goz2Z|I^TzWRFlH;2!(kCxLdK
zt>}Qr6g!G`(ht~c9{}bd`#T+mJ<V=;6Lx3VKVAoU#Qwv8#)F(1M=02HJ_v_`184Dl
zczB4zr`YmgPN6$S=E(6WfQZeBQ|JSYBb;qUh&pqwQ{>8pb9MuWE5|hjjc%N+PXhZW
z=fwly+&Krt==0#5rIWfRC*UH87bk|&z}_4e2Y~u;S`L8ta<n^O*N<~Rg30&iYzT(=
zV;uJ!s2}G@8^8tFII-RE<^<>NEzDOSXH^I^f;eH$Knvz9cnIz!Cz<MULO5YXfC=Tq
zYy=78ES-QtI7c)amLfRMoy8zdaYp0d;c5I+7EI6?PU0!_MRI1*sWFNZ%mF#e$)tc+
zH0KOm(um{O&W6E!JSTwCMG2fV3c4h6LMRt`j<a$$`jR-W&^?7@PWCbkG=<|i1pQRb
zkF()g8fT6h^wK$7DZ-G!*+n1vI?sutp=EO3qyP1i#aXihA{RJkc^FbQ=inY-=5U@`
z43u0>jE%M>7diWPKrxTAf%YnwIJs@W&gZOJ3x_Xr9(sT);OwkJUm>TRLPtfMC6xOw
z=B%6xM@u;0(G{0cPEZdlm2n=??cH*Y^KUS5g>xer3Kg6!*)VjK6Icw)O3p_&pjXA&
zHBGtVYn-*~K&m-ywP>y3*gp+tu5<o=9;B92p9jS{jtjj`>N&CB!)^oT3pW^S<OFrW
z;0?}C6eDQj$mu8F%$aXOUkhg`6&|&6j&y^xadJ0;v~zCF0@zK?E9arm!I_vx*S|VB
zDStwvi&Opu40dx|*23W)&Z9FJ#VyWTbOPw*Y@)qKABS}k`u&_)RJJw1x!(-QLC!la
zP#@xq&{KSylcxbU%=xh%A|sp$1GrI6HwEGEaQxnb!WidG%1hkkxNgP&6to-XxcOEc
zSY#X63w!rDZ_u5tDb7wxay;NDC|dcDvylo=r#Y%TxIM!$pNB7xIKGsKILKXp9mJk{
zn|7iO+!ua>6Nk9MV-Pva{gMvQj@<oh{3V>Y*J+JE!rlJ?h%<KqEsrkTYZSwC<+j-(
zpzp>VaDZzb+y@<S+mmagTgzVDmyQC)o2ybn(TCebnOtA)KNRWm<C>kI;Lp|ffE?rg
zNO$j#bAO?;Q~<Y#Zi=7auBZ5XAos5j^aXK`e+RH&E{`(YC%J!&LnMSdYdbB(p<Klo
zI2Fb<(vK{hTSSNK2yVf8aHqIK8BjdUeRdTz&TuUhVvgj>C|(xDt?WYIS?)3lF-LPh
zSOc&a?j>3*W4W6sS|7)abO%a2SJ?;G61b-q!rw&hQmO<y$GuVY7=8#z-1JO<CUb{o
z0W^ghavJ)nTvtzEr*Y$GnM&toz7O*mT%jJI=eY};Ad<;#rjpYv?q~GFzranUA9pr4
zlfI~#!<|ow<XmpYd$4qo`%@p(^SCDZja}jv&4*q-H@}U(;BlGTPtlJ8?mepPFXW0S
zU{J&jNXI-EbJzR;&=T%8T7gTswf69^j5|W#Su5w7eg$`h8%ZJ83huLu(Rh`6ooX*D
zxqgk%tKz;x@t|v5>oKTTbCc+nPz`qxg<!68GoFTst(Lp_11Q#UCA3b}a}%hRpn-ey
zF?2R^^Sd$L8{BzxalMJVl9H*-+z~1iXyF!zK%|wsjgs<h+^Baj>~`)}`f&SAZi^hQ
zb#Qmn;kc8#trhBB+%o!DU^n-zScvp+eN2G9W#bADV`_T2D=1Xf$E~!3Oh5N~x=k{`
z-Le&pgWQ$$+8*L+Zouym?#&o9j&d*j_fq4or<on&elrEMyWEc{urkhd3x)awcl!qT
zJIRfq+O2!sg%tX{&+YaDnc`lcJ?sOn_|iHUe8?4af=qMg(WU7b?iwt!c8|E5mO<tq
z?;~G(hefu}E1`Fo_XUOb9eEdKL&AyoP7x%I@Y;WaA!nYI;>9k!$MAQxbLC}GP}YrS
zS_E>G_bX*#+<CclyVQf%at3~S@*dIrc=2Y@r^dW_!fPNtyw!_f$d?zr3}Ak|-3OrH
z&zrH)QgV!^sDY*9yZ}nH2Jq6g=sdw|p<sU??=n>z2l2w_Sq|nYXbdNL6>N|Y-bb`q
z4&|w7jSb@!E&&(L8-ELZ5j-9Z=@f5}HWH_KUr~9&8D0{-$s>7HlmUz4z5m}gYtHfl
zXiU+(v=Vq4!~0|lT#V)YNQap?-rNC@c%CB#Srd2x^b1Jj-JuM?IbPm=C?xTmsgfp{
zx2_5#g*UScBB{LLXW>N}Z_x{|o6bw4|N4=^I~fB*=XuvD_?O9hLPrm37Vpd=Xk6fR
zQoTSnFN3m9IXnXwGP%4R6bHJ<i=e}59<RF+eV2H~ZLpNjOD@1DF7sAw$3P2s#$aF<
z^11>bQpDT13Vp@A*`I)v@GfmeV<|6h5@2P#-R}UpoVTp;F+8YOc;Cc=t>BgJfr+cU
zQ4L@!dEc)Aspg&d6Mon59Ol5_b>7fXjH#9vO!cyLJP{pM>v;>lMPCEYp5n%hJQWk<
z25+Vn>P@^4cR-|>H|M{c8859DhFW>gmO;IZ_Zd|w+uC`5Era_vdB3ZG-N9R<gnlP4
zbSXN!cmcE)bo0hPgGdjrARUUgc+>QT>gByn(epkYiqi3D@x%d`=K)^#e)J9UPS93%
zh!@igu-m+=L4Y3St^XGaBfQ=8J%Ul5EEghoY`l;y=p5s@(>2w*yxp|tALm^o_a}JY
zZ35aPuY+!@-Qzh^5#oKG;7^Qqinsi2U_ao!OYzW$yk;2`rg<~8<)7h=PJle(W$p&p
zLH+`YM%nY{CW1KdFH`CAA^u~OSv}0RO`*if&XM2z6})ibTb_r;5x#>Aoz8skU*Vz)
zKkqEiT=`9OZOe`SZWj8E^7*u9cjq&NQ1IYCjDvYk{wH*f_Tpc40`cb0e1|?Cel6Vy
z_2o12!1?i$e#IpC^XHl2%rX9??FQ&^{yKWL1Nd&Qpz{R(q6_o``AxJP3gS0!L|-t!
zU>&%V{Jjpa6vAKm2_!@LztKTBj9=acE}YL!09XY7RSGJf;@gZcc$&{?g2)+u@i!Pt
zB>#EZdPng`{|l4w?GzL>iRP>4fW+`Oo(6U-e=Qv{;`oaw>K@OR(qIz!AJ8E=k-vn3
z+2{DP=?I#{KSuGSRK8~h)YJG{x(=AmFKPhE;Fk<R<UBu~LbaLvA$sDn_^(qe?E=5f
z1JK$0troftn8W|02W&3?BdXoF$UmI~^LhMNX}f!g{}sh*^Z8wr7rV^YQZlrF|0bR7
z3;E;Ez(f&0l#Y_c{89>#l<;#Ff|T-i96(<gKZJ55<@^ph#$4gM)2X<EKTH9RtNcIy
zpqxV`e=!ei75_FJFt71PCV^ee=S%{ohTkQ?V6OACDI!zLw|f=l>-d-HCtuHh^Jk2{
zf&Xg@KpXi_(#!A$Kb(RtP5f>2G&S?n5<pt`Q(Qo|^4G1vINSKo`2(z-e}f_uwwwH5
zCs^v>w>tu~lRvQ-^VP-AF9hl4&wUe$J^X?)h}`0b{sin^{%b7Q?c*=K4Uv9+7{!wY
z_~lQaZ;&5O!R#Uai<FzZ&7YbC8RqY!r*VX@r3ZbK|22I@>khwt1^gYe@jWP-e3u_1
zhvGOtjx;9t-qGls<flf#(mnpMbYS1-|Fjciia!<v@_@gFYTzF7|Mv>aPxD<VDmKGk
zvjpRP#Q(VrC<g^|{DEmN*l-nK4uY3ymwiYu_yY6}3${}{)KOq_N(OZj49>@3jtCAE
zfH(`5)2YTqkU9oXSHW?*GvFrpTnELYg8g<d=q_0JHqbl-ZFJP|6c{Ve=q0EMgowA`
z(vL9jBWS(~;wzZ<9eg?_xOfoUae*VPy#azfR9kaGz_(q6i9o?9B?N;6m9fwd7A&I8
z=t;p{1MG$fz7k^;p@Pn%AYlUEK^P1dBvO_jLU8#O&`t@;j)OZbh^4dk8Np^Vz#;|x
zw6}{A<n002S%Lk2Kt~HM(}^%fAfj+otf1~w8)%#$ZU?-H7Yu&^m;{0IX-q<*pqDmM
z=LCtgLroIwp~W*<5O^Lwr3k)yA9|^Rw7Kv;P2hMKpy`5NK7~StU`-Sn&kGJd0WMR(
z7Xvy=kTV993xZ>my3Q8-O7Wl^!IXufmbrrOsr8~@|86Me399IF?<GOUU66di_a-=V
zS#V=MTq_WSP*AQ=P<#v6MS^{wgDV#JQMpoyz$FouN(En2e5XusZz~Lz3mhrNbw%(q
z6^~X3&e76;Rp97`zDmJoe?Ruv9=j^Rv$P$%Cdj2Fv05-gnc5nGmlZBv7i>HRpK1lI
zPob|)z@`mRy<i8u_8SDVXrIt1_&XJLZwQi}gNY{mSb*Iuc$Uu0ErP#j@oN=)Ls7>z
zL7eZ1+alW^loaU{yiDcpU4l<3*3>PyLwT(pL2w)TZV8SIps`o5<$oZ3g0&Ro=@&Hp
z4Oa#PJ3a>1py0{vFg_&s=ra0l3&K}JeOM6i0(>74q^3h;R4}s>jduil9Dp(=m`C$@
zS77?@6HMcR5-r$!f;VYjabM6}4KgK&<)ZO{fOQ70JrvA43NkI&XAhrd1bANXXbHB}
zfgBV@*2Av7FfIgo4#GbIVB(PQLt0%A3nl5`9EJ4}5OESJI`H>6B4mugCuiX&BlIx2
z2;*sE>ME2{e9%q!EgvvPh3A$+-(Bc_5*i-Dh;0z@6n>rp;w5yt2`{{bGEYpsk8n>B
z2I?zJHlxo^c$Z$D{=$aE;Eo9|(h>W(@OmaN1B8DUqwj<;k9Goq!lVzVOejbg_$x*c
zEW8(k&Xd9&J3&H(XQ>t^R9Hb9gD~OG@4~fk;lEd)7$JP(ad4-Eb1eWpE%b8(cSg93
zR;fs#l7azI!qpp~epdJrJ)qITT>6v82&>A##R^TdF2xBwFXDe}+Qkd!&>KBL`1yKR
zN)&FUjlntL_;QdW;eq*>wq)T<BtTPyM<^4ODm*~nYE2V<U5v(b;rL(hDMNVRd8nTk
zj?ue2Q+QkjgIPkx9`s!hR&Rh_ws7AB`f`NN8$oh~x=|?DE(%K&n7urqAr%HM34_)E
zJ6{-D37;+tKYRr91;SZtFqlGNCsp(m3F9f6RV?((1!#%zTRIb!3O}a2O_^|IEI`YJ
zi|NRFMYx`}B^5%!1z=tkb{B%H6#hdQ$||AyJixBmgsEGBRxQj~1;rX+F~xtc3xjCm
zRVyrLgiM|AAG&~0FFg4de7Ygbqt|tl@Bo!GGz%x_Slc2@zlFY5Ve`izZNjQXkal4i
zjpe3rcry%k2tWB09(D?&&%%o?VaQyFbPH{JX|d}OuA~R=mhd!9X|FIK9-w_f&u`J#
zFSI`ijRE2PR7~lhu;WF*3<)=X0M~8{_bSmhEd1j;%=3t_=WmFN3X`6L`W;~p)$xuA
zU#BJWu5h6*`o@JTrqMSc+}jSHCWW8c=;VG+xc+_2*L|V$Qh-hg%k}~Efp7<H6CMgZ
z6Jc;#`1jjzW=5D!Z@)*vB1%Lb6m9K=U3-zA9r_$ZW$^$zBw9s9#fL?23W4G%(w_zA
zB$5t;91;0bG|O4^bsiL4L=}lP$he9sDRkr}dh8i^dQ?>ZE;x6Qm434xq90ih@f6K^
z3<kYK|K5WMZ;=OWYkWip&teq5q8Pej>nHm5Ghq9RT=t>wn5gUpC>$4+(+!3I(MT=8
zPKZ9HKWL!n9|~v&iSqp^MjR}veF*lX$nI5ihKNd6!(gbWz66b7BF}L&hKss}z(t5I
zj=}sX(QK-wIW7A0H0+)cy-X*(NKvyVM509dsK({2$n*{LqD8N0&=(^L;=rd^(Yus*
zj1xJ~;v6q}>n2?QPY^9!1~ySNa2+z|L?8Tv(I<)iJqSz5BIYzSQbc{U?4*jm{}-;M
ziMDYek}gVE11~Z}Iw~YTFWUVIEM<z8T?3abdjD(a<%qtZctx(rX+3<pD5^_>UY=-w
z4NxwLx+_6!`Jxg^l3x}vY;d?hq@nj^q3HL0Kr0g2r@^&i(O*K45|Ml}NU3OkG)$C<
ze!<_wu3VH+2GA=a2~{0ch<qvfaaEK?;l4`I+6s74C3@ft3)e&+MZ@1}(N-q(YDCzY
z;YqWJh9{s=E2?UN!8%beEv)sTPv3%KgJ{bkC^m}LQI7J4=)otDY!ba@kG^J6M;l;T
zL@T1v*D89G>g(D>3q2vyE-Iys;!V*6W!yVNrj2l>Q?&OUNSBCp2Nt?TC+IlQBl4Z_
znQyyBMUZ`>#@*=Y7yT>3fCfb2-+&B?yfOehBy##0P`5?J5wJEaN+`!*M?^&wZW|Tl
zHv{;ND8K`VW1{b9J-I9L@CP?8x|IfQLX>wOD3hY^>D6#g^cq#c-xob`9Nd)XMO!jJ
zABYxFIr~G=fjK~%7I9{PJtO+ih`vXn`{NkbL2)6)IPJwdieTPBeEe~6hs5u^1MaYR
zcrHA26zd~FoW!aB?I6X`6n1hJucRVx7x9jKSa218OcUWI-nIjJN5#%t=nwBMUfU1i
zA%2N2GJ1-)T0p$SF|_h|i<9=E&quua8aQ8Z!;66N6HDl(w7+<@KW6QiIOhqNI4&-w
zaB+b6?c4D8ggBX&tU&R#UC;{>$I%6m5b<yf{y3rHMPbkj6C2oc>IoNrwg3hr#1(hZ
zc}jeO1;x|i(_1hJXT+=Mt1Xe@HT1ocDDl!Pm^dp|(HAA6#Z&*lQjB<aF}PUq$a8Qs
zPTV*R5-;why<38~h|Z{q;`?1dIVb*!LMKV$ohyNoEcQf@g>RQ4o}_R?s(35{Bu)G{
z1@_X#&(pg%L%htF@6WQG83bmwcsrd>a>NmIB+nHmP!{i^xO*uu^TgF3L;jNZM><63
zi!UFBh0Ed+%5xNm|BQoPp_u>QeHgL%OMn%NFZ>0O67ik?;vwSg^gAsRtE_-77due}
z<`r@4C16&FGi*7aSH;JKP^=Vhtp;e7_!gznu8HqCz>8{eY$f_?#HkK&=DIj397CxU
zCs7KgPQ2_9EY*v5_CcgUJV@WcY!oNcntDV0^bNSyB%Vz_>Sl2s6Ot|BGTLFcik-Iu
zx=nm9fzr_J;^p+ty(#vh1XhRGj!w~?;^!&S+9me?2zI;0+o;&4M_fqPmTrk}MnJz;
z9MlShKCyxloBiTVYoIV7{_z_62E|`L1Lz^~6LhM(EpFY2kqwJ;3NZ;I;>Y)*aa5fD
z2bJU95jQ;sjWO{rX>k9pc##Gs#>J%~kO}eeQuIxVf1<L*d*bzMxOQJWryq?|;(eRp
z(*v=H4qFe!_i8|<#V=DX@u1|T-(cQe67w!xbC8^%Vvs|U^9>+}C38k0=_q02Y-zJ|
zk~~LM@JA#)t<Z3md{5^L7s(3;py(>`ZH5<a630rIKPpL}!MID_p|V{M$-J$w<SF5D
zFnL~*9;!C;mbeB&(nn&T9g?raj)N)jlRQs#W&V=jbbuX`Joh$Gj!Om&(6a?dmQ&d4
zgv8@}3@uQS^#(M8Bx(wM1WP`N1I$UupDySNkvv9)IH3|>Dpm-SB+?-|ToOpt0uhq0
z=xI15v5<$SB`!|^`;0`n0+NxEmwbU4CAqK)+*!%DQLq;+sYt~DV{DRlX#*cCdFui?
z<0NA@U@2bmGObSul9wq9m?+7i3kBySk_}KylDuC7>}1K357Cz*xkLMpRLS#;;6<9`
zM>@5qOAdxXGDA{GZ^`qLi1mQZlzg!dC|Qzk1E6q0BBAJ2wuIyL4b10AdbMcHl?3j@
zBwm#4ItQ3M3E%fxz#?1tX+Rf9LN7zTQ1Yn<1dAkp(P~jF`HMFCC6dw#sFg|_BEXeN
zR@2v~$|Z{!K)xbb&ccW)BuqNSU6uIfLa$QdqlQA2#5Dv?T$5;PAW|&}mO-ROvXL?|
z*Co%t1h863u#Glmb&`ZVnAm#B&$)1>K{7Z88jX^JRnWL0Sx^kLCdpG0G&V~r>8;u#
z`5%fs?OG-F=h4?DnH+-M4#_q;lXgmCXcN*U`C}C7-I8L;YxYRK@rL9r$<=ib>6Lie
zpwK5N|CngM#EZ&12PAz|L^3D|q<!#^B>p=3ZcEDiU~pJcW`f9wWHW_fMkN`vk-Q`M
zrWIa{N%lU6G2N9cQGtw0#8EIfA$ckeWKxoQ0B+xt*i&HYzGR3Fhf|WhbwGI_c|DQ}
z_8v+?=(|MIl2xz4#TiKkT|0dwiG2j_p!6Ne?Ac3SI1FqDDZ37!hot-80C!lbU_-=F
z`lKETPSUN50eVDQ&j9Bv{eq4gF4A;blwGAMkHdR6=@WEnJ}SM=M4!7f51R;^oriRN
zHDo-con{a(=`K1XdP`d<ZQ&zb;)6->mHu`ZpnlShED(Qbw*X^0CY|#SK#xlqw5$e5
z*M1N66Vg-kf((>CT?4m+q%L&U3zk}G1A0=r<O<vlkxo;6VyN^BUo_gnq%R5JRJe5a
zCMZToH_>bUlyr<{_Ow*!4$(8xbF0x9DSb8+K1E4?L1~HIS*eYVLebLle3*!lPEv(b
zth8u0CMZr?Rs|9-UGIv%1Zf||rxK-4Q@HA!bnpt?PLh5^Vew>})bB%#DMji{DaBN2
z;16&nO?o#CGU?KI+O%azxqqYYyfl^ywKApgcc73ZtsVw<L7Mt1Jj|9>-vpN<jf_KI
zuJq^sLH(k1n;Q(~N#{+&(k1El%YafK<x<5(p>!WzH7JtW_UD5ZOPi@0wnW;y5C%)7
z%dP;lOsb=bi*jjsG5W4ZvtNd56;c<vDtcA=Cgt}lr4PkWuaX*@F*Dbs>ziPrT55{~
zsgZ7&2g&PF7mBslN;gaax=tGWJ4n5>@FR#cNRQg4Ak!%Q_cG9KNbk|Xw@Iq{9WFLY
z|9T#Nw@5$ap|4fCozib@QXQ3;w@WMO7kpF7rjNOGNP8<W&`xRnZE#&u!+MZzY5j{(
z?~$(g0pyl+l(vh#($Q*=KI#1ikbbFO6opy_q<ysW8I->IHCl(HUYo$(mWCMM+OSj@
z1GEw87TS7_N}GDY-H|S(3eGWU6}?jLN}c`S;kZ;$2Cxa~-V6+4Qu--vb?!+wwS(N3
zK2OWzl(c&k<bl-L5eg5bc3QeGJ1xDr9H2AO$R)7*Ncy%BG6!XM)WEivt!@P8AlpjM
z-yvB)<>n5{exdh=qpbaHSaOn;E&w?q>--acG-sKRZZ5dUnm&MCSJ?(Cf^?JpMW^Va
zvM(ur>@K^q5?~&(x3TH9*?G!TboBF*eOL}rZ`m;l3HZolpJ6b*vVcy2`pI6TS{8rV
zuk`vmCbL$69GCs>4od;Do%C_#6S7|~05njx>{BQN$&zR@A1wP|3?e6G2rA;ildW<E
z36;&OgP|~4%BS$j7A|X|Gkt_iw;SY?%;=2HNZF6S113rqD}er4Sx-E$qh(dsVK+v$
zhmBFh%1rhUiIZKSWO}@;hu*UZvbO@EkSM#o8w%%S{j?M&$$p|Ed9o}z8zW1RZ72gt
zmHk3{*EE~#O?tPb%Y2UjCPS7<p@{P`F5-H2nX;h+0L_x!{Rw>+Wc#UDE?cIj^mmSI
zm|g_AvR>NTU6grH%p*_s)EtmYvK_lY@?|?mpm$leE)ZY^vi<^iQ7EgFVJeGc@pMh4
zSms+FI^TAI4~#O|Px~QWE_0xb))iTF3FIndZ<m6*D%(h##!A`heQ>Bs_8QILHQ7q~
zQ&-DUNTEh14Fz{yrizASt*mkY?$ya&eFA;;vY2%E+#s9s#^@Sl_ZPs>4Vm^Q^fk%;
zwhcj}S>{4dNQ*3;2bfk_&^+k3$*TJ>k?pdHerVj3ZOj7KA#17!OsDL7Z-{isZvF!G
zZdnHH{(EHYMyTJComl`!du7MJ#L)X>Tj=W*{W2fg*bT^*&IQ<@>}@)<49Tn>^p?LZ
zEBOfC49f~~(K#ZU^%_i!%3k>n<c_SI4>Bgpd<^<`WwG5L<FcT+AQQ4GdQK)~zpclV
z+>^C^39$PzX)REuWPGYPcp&>B9qJEd&Xnz*mi;dthGt~XE(3Wa+l=p7;&GGTTnpA-
z{`w>6JIKe~fPF~*)nbsta_1!=j&d;-(K^ekZora@{QX6cbd@*J{?JXHOCQ%hDzA7P
z19g{s=)if%r#dh~Px+7ZllGFwNMONR?w$q_ANk*5;C$s-ne+_$$%ALXH-Gt0hXHy_
zzHKiYJ}%GS48;I>;h)erA#bI+)j;{`9DoMNFZ>J=EZ0(D)Jgfbr-2qCH_yWlDOCOw
zU5yKqx6rvET>kbwU`ELQ`2q^3<WEyZ;IzECADCz4&rJc-7AcRWL|K$PwhrX1JhB*|
z(ejmxArm8)PD3$PzIQLUIC&I(s54%kN58TJ`2s3OOO&sv19wh-hAssq$={}^QL=n6
z5VMvdZ>79`s(eup{vv7eBNQ-9mwQt6MTWfj4Ajrt<a-`KBU4`UJlHJxvvj5Jf?Pz~
zw`}<|z4~+Hk9)(XT=|a_<+>=}Pp|hpIrk1kF3F#y%IAD}atzcj%NJ8wOo3cR!G%J(
zg$2DL`2!po?TY1xDNb4<|Clajl*;$}0lG|Xdz(tc%jI5MG0-dWyp`yzkWaFqaaFEM
zfqtd@<RC0n$=B9l_O8jD!ZA<P@~yAIM2%cSA@l3<?RTJFE5F?Ykve&{5ti!Z*9)N6
zAphL~3XSrP*)ViN-bx=cZ<7BM56Nb^(MB)U7WtZWU|Z#H(FY~k<ZC|zX_v2|U;a&b
zA#DUY<ebki&z<rINoeen*L(%8TRw+QYd!KOXd`e-{>f~B^~;;TgvfwAE)XJv^289>
z9g@G)3+}f3K|Mr<<@FuV8<F2p*nmAM|KtG--jN@oBjlL;`TfwpD|h#R;<)@<Be)5<
zBbD<{%Dtb(1l^NAd>k`#U;gt_40}r6MZ2K~^0@_Qd?;7?0ee~=_YxFl<S)>P`H}o6
zl>i@9Owu{uUa?yMJqJaAnofy_6p6GQI;?m|YqX={*giPpq$s7`&=Ez>LG(E*VmAZS
zMWM|Caa9a3(dVXEupizZRVb(+(p~ZW6#6_Af?f>5Q^7LAgqNc0IKaFW?^BV1kK*+$
z@WNMd;4K*PQye@^;dFn+zBAB2rih;h{o@KR$_NH18ty^kgd#TwV+vH*==wsCB9iv{
z!HR{nlRl{^sRI|Hc=!gmP{qY*SPD~gehchy#cUsV5uy0!J{nIcI^uwGTCs;to@W%B
zX>Sv$@T483ElTkuU12<{2%#uKw4&1)T#SNA@%vbXnI6?RMGjRL#4AQ9j+3C+No5p?
zinVkd;haM99r}_KYukXGtf=aO`4mMneK#Rh5kPLIDOSq?ovx_;1_~L9vr7SeUQteU
zHJLVr&unO9DL#A(`WF;YFF_+)v3Cfwm!p_Rk>p%O026%|740hllc(56yMs%LL@IvI
zS2#Mtr^||I`r2=S;<a{w6)KkcU=E8EOX*BhtSIz=WQl^&0rgVFmw$u1qKLWyu0ml;
zp~vE?LPlk`m5OUxn6FZdJHo^@MI#3?)rwnmwWCJygFi&BD}KYt!LC;EUOp_<DcE)p
zsaG&)&)lFeFk!G!v2q+JHx%9BXlzo*s2;6ZaeM@rEsEp~7+I@gE8Qh;Q<!Yeg0?H(
zses~5#o#6krbBV$cYt;(p0>e6mtwLIirtF4be!!`9HP37TZ+x^0lQam>vQP!DN61`
zuV1ln0AxV1?rW$IDjtPmWJ8JxI*{I0+&K@hVMWDSsE;Vdwt$Q(8s4BY;2p*CNthT@
z%%^4RuHpqxV2>-@=;t+|@G(JgQla_;BKH(cRC;z_5ltcUDaC3Md7$t;3XzA3s&F_n
ztyn7s_Kf1^k1<`36kE3g?4WXrLO1rxKc9rUgK{qIjSeY2zo&5eVdXF_%#O+?+Uhtd
zzo2r6Bg$+4!f$8gXSCk9D7VpT!BtsKNf0;X|9%5^RO$LRM(D2O(mUBh89WEXQ#o7$
zbuVRx3oLmnqp7;UNBKWGUivEK|0Ud%`@$jVulyVlSA5S=`M(^PKd#(Do5%oV#Ws)=
z%7A#72vqK+O;wQc(^}{UD}y$m@1!z`5{x0rDFsY~Dwj|VOPG?`2`*eYFb$Ci<t<t?
zPbnLCuyk6P@C(Qp<uIipBbB%5WgMkkScB=ZomIwAkSSVOLGR`mrNtNHja9C?0WL+!
z`vD|X8SjLFrYURNU@23nzYX(Q%8%%`enIK73!oR3e^XE_Pq~Ilt1c<i55PpZ^290F
ztx$S=36ZPH_b4?`sT4bbR4HGlzt1(Bvc4YJ)yi{ULZe3MNGIs)$~ULM)hahr+^k-i
zwF#mP%3eRrWur2JUWzxAA5lR-ld_>3cAJ%7(U(73m4)80)TaC_14C+89t_5m+*CR@
zLcK%z5~T*Zlri+)?N+{Y31B@+Tck74ZYdw9onNmq=K%Ekl=2v0_bZd_p)sh;qjh;m
zY5OnUr`&N2eZ$K77tuJPtf2hpsM3xWxI4;5+Ch&glj(<aSGhYAedEfU5O5R9)dvAK
zsobuGqxY2e1@P&<a<7f{$5YCdm0%w#kBNajt!y=e%qWj^K=hIF7rNDUP_=~z7<<)+
z6n;3Ql3#|~hgAi1l66$gqX?Ums*|=(M^r7hfa#(NT84qTs-B_9pqnb2ZUi4y9W4NH
zS83mbx`*n8-8T5`sX9lY9B<W<DOmDRd0l`dU)8*A!1hzkrX0M#>erhf$5e|}!>1Ff
zOe!!ARHe{SBS>|eYJr1Qj4#o5Qsqy@fgvg%+7g7Tdb2UI2-RFFi#w(I>SHuUs+P@x
z7g4GnBgJ6Os#IQ(iB(0@|Bi@LE&m4Q<5gc%=;@rQmM+vJss5qERI+MA0s7KZ?^AJi
zx~hHxA{i?8Mc}ej2D(~uL6t~%o3d4}901rwl_nK-^HlGzhWD3Lom3T+uW~;FdzV$-
z*wEPQ3RG%*{l%_WH8&QmC8~#U;7V1a;ZQ77t)QTPx#|qvP`RQyWd~;}Ro_vmQI+Z;
zCFQQE-l23>waQTd^EIlIRE2R}W%nMqdet2|!8WM=MLgE7QS||xM4D9#7yxTgMYh11
zZ(CJ&sqo^aYWIsU*rD1*F@jE&GbP-+RKKLdM7K)%H3r(FYWIfu+p0~c&^WAmCJQ1X
zs+TF?Fse$Xa?Lv`11)!Bs${x+e^<4cc7@}r3SWKvBAfSe*txG-VM5!KN=K{n1J!dB
zp?j#Bp;+{^s&Y0UXH*ZUJo%C8H+wW5RIBOczrFf;4;mfRn`nD+NZmnoq=(f%9fXLZ
zdQ~;dIjP-Oq49|NavX->tUgK`R2Oy5C+Krk@3uu^xNhoq=oo!ey`dfE-PL{W!1hod
z-UH&PPJ00wKI&tqq3^4H^c_U})Rrs^%wPS46UZ@j3Vog8xcbK=^aZH36wNxJu6r4M
zf$E@Fz@1dTNvEg~wS`g~q3SPb#}uZ%^52K(!qsai(;T4|or4#r)LC=~<+M7Hiqy`i
zGw7j+R4;xCjZx~Ss7&~*`theQ-e`3_J%lmpzBBkk#Hu6c?HRBBjtWl`)bW8JiRxyG
z7M@cdy9($ewS6)~lGXYlG^VM4**jN<U#$8#Re5HpIRtZFy=4I`WvchoLL*CEO8Jiq
z>X29AVYd1`-;o5CE%0Sb%q8_#O97UzF4~1DysTak3{t4J3<9J?t)T#Bsd}8=T4n10
zc|p5eeKi6KSJXqP;40Lb7${s-Cl+CPE7kiqp|48){tA$5YFRx<wK~5X>NV<0IvrnE
zf1m=XRsUsk0<BZ4zr_4Bs<$M=nHy^HDWEl}k5bIBS)I`f6D{fs&6uWkwYnSJO|^ua
z=}=cv60lP}n_hQa>M*Lw?p9||&b&wcD%~8rr7rp%bJwd*YlRnm>a!`(>sN0aK;wWq
z<&h0^P`#uUFhgn^t(>>jbtc#yRk!ls%w2W%f17l5(H~HpP*+_<-=um~F%<5pR~^6v
z-B-_F21`@w!`spKK>d)G*oW#DgU~pwW`7C`GwRzVXnds3r2UqIMzjOukY><@PREBe
zN2%b!QNyGosFP;s8w~V_=3FhzJ8MdP0qUYzNyj}`%^_Nr+%*0QfF9L^yaUc%!@3N0
zFAe7-nDEvlg+k9q^T($kzM7>!f%s`s=!%@b=2?n_2Wb9z65~9falp&gW*4YYev45A
zY3|<#TCj%a0`8<{+aE9yrb(rsLb&FsU*ScBrh`Jfr!-ENVDPjiw+P%B&3bQuMr!is
zgNxF9VTQt4jrS@jL~DG*0T!ci^1^syHEom?OVRwW0V1iIaEcz=(lkdYzMih}^gw5Z
zMsE+a^O`59m?Bf7xCF&4%~zKoazXPB8-8bNqSt`rXy(2TlB?N5Z}*FuXI#MLY2rH|
zc}Y`Czl40vXa551vZj&^umX*bJ1i7xEJx5-q#2|&z1XHXYJ)c=8mD()sZ{f8Cb%-q
zcXSdh*SNj|m@AsAUqiG)Gt~#htC}@mV`!C{XLbU#O0&ZUeb+RfXM$8~cyGc)jpo!1
z=v~)5aT24i)f}N4^mUp!6t%9`6!QSxpjo7Yqm3HdTNHG^q4A?fyGgTv;_}U!1yp(6
zqAA`6#a2!KEs!?N-3Kt=t~o~gh?|<TM_{Q#<3+Vpof^$La9x^1bj<74yg@0T9!+8*
z4BpbXJOt_0_)(okpC+^%T))O+9lRgVOxx&xqz-EKQc3)fMxupNw>3YA!3}H5+aNlk
zd4}Ezqna)%FTSIhRR=Pru~FFgt|pobg>lWB<7k}FFepMXsqv({%J(!M(&e=K8uu%Z
zoYGu~fXKAwZ`#MtXv&_$SRQGZJ1Ii!pk*w9%pq-gC&*!KSs#d_HoX%vPTDK9%pK7#
z{Q+ps+F6toanWA3!$4iNmG42)O>2D#B1g6Ft%ZWSR!5F{Xb;i1NIbP6w0HH=D%0Vp
zx7PR>6nwPv8!*4V+Q<d;pLG4SJHEttk83}ogn5A0#Q{E@(C&I38iCq(sc<_;%ZY-C
zV683&`X{ygIcN;g8mRgrRLi8pL74WHqfigm&MW~~g!U`i*Pha@dmMeIwI|+$_h+>2
zO7ul)vuP(Ar7e=vJ)9WrBo&9oY9;h0j?->R!_eZjDQ{vF3EKC@VK-6RV8tlTX(jZD
zw<K*pRlX%_5C0936zvyuR7lkpl|nsDyZJM4=~@>dBr~*MJ%&j*ul-{Zu4QT)Xp5Ak
zZKa95pv|P1yDeMmQU~lDEsF|{a<zFMz~PJ9*&dL|)9Pu9bxFI8Zf)gjcl*J$%i81;
zC>CgI*1=$*b|IC97imAHsCTh;l%g#qS{?;RO0{9f;eDAl^;4*qYsH>0e?>b%fxZgu
zyJ6t2+O&cmh*oMvwArrG$`6CPri}=IVzoAdZe!PItGi+Fy0&OOG-|a6=$u!leKZSp
z>$R&Ff;4FVp`cHr*5nD48`=;4guy25x?1QpYn|o*tVP>G5z$udOfnkVv~ybk)~>a!
zz6bWEHj%d19a@JkF$ta8779srX&tshrd#{kNBFDtYFAK6ZlCtcFqr7qcGJQ-pfx-T
zZcxjj?ZuFG>p7_3)`rn0eOUW1RUnUO^^^}D)xJhMr90Xihv4s+Hk1wMyV@6Qv_g$*
zbE%|iLi<GkT%6QS(siqQ+L&tibYCkff%{Y1!#kk(K>L0>xQE)yQ{bkx1$4c6Mmzi}
zupepX(PfT<x~V8M+UwZP7=(jvPY4<h>E^6}!Na=ER6^mX<54-OlkUTK8(@y;!uP?h
zv#yqEfL(MqTVdW+x8($2+;nm4L5}M7%P=N)-Q=qP_0YX%fWD`0GaaeCbla)E*IQR@
z#8`ZEO@om1)paDG(NA~nb8!B;mneXBOy@cqddGEb@54fX&O3yPJx}P~pzJ`PF3|w<
zLAqVRa4}f7Aqm(gbsbbf6r!uo1qszH+79z!x+Qt=H(dA2UXTb~6s4z6>0Bt#5UFdS
zy<L<plb(vRy5G(MI$Afi23(A80}mpxx<QI;#Od_QC_@^rJM=c#1YHwd<V@7POxMfK
z=~5_RlBC-}3wpB7zYvWnIv&M*Q*|Ae;YFHm{;QbMbltwq=*!TRu`v4cx>ZyFm8rXI
z2fZxaKQyrybbGk)B3l;|3D<ITnMKgc)hYJDtnH%Cnt@^G>2@nXF6mZzLNs3&M%nSp
zx<6=NRiLY)+lPg^U$W6yq<fb_N5#6C0Kk;!)^3EsQr#3qkjiwvl=vvuEue7L72WF_
zK`L|!w4PtpeYO}1l{(1};Hq>C6Hu<%boyej)w&Ju!fuVOWfU6Mbt`#jtku2#3`m{M
zo5BzEy7kG>Xwdah)p4WlvG1U8LnrA4Y0|w!MM}-OC#mkXMR)Zz%tfp2%WRM~-L?eG
zMZ3;Ii@{Bu`v#1qOIJV}v2LABaTF$cbh?|cdrQ~f1+G`Og1)WLr?XOqwO@B?D?|r$
zp4UMJb-xZ_N``dvDZh1FH=oYD!@3bM$cRq;K14=!&UBCTj;@PR?PEGKJw|tRZ4vNr
zT(_HQ2`6+0S|KKNAKUCf@975Khr#>0-?xHH>0WvRFb{NloxwfS#Ze*lwC*5P+t27S
z|AnKEbi=gEI;h{whY5TAvlKIO(Dyt--y!{<pFr=he%BHZM}6rZkaW_AQ~c|Q{u%lq
zI_oPbWbC3J47Q=uRlm?3bK<6#Mx*tp-f0=kyX*aGq3@w@rtOBO{&Tv%?xnx`Cro(j
zzfOTqKKdbg!~5#zU51FC{@Z5&=CAKm!_qPR)*S#lt`DbbmH_?QLm(&gJ#RrTP@hVF
zrXc;)dz2v!*6*UF>7@Q)HDp5cU%d#>Q2k4b(HNosumLcq^k0+1r}YE$LyXcV($4&>
zK7p!mqxIhj;BTD%4<#lzUjO}L&`Z$2L2FosUh)?#o!2j>)M%!D@3-(iOMk2!hA!xL
z&!Yc!m#zPajzc;68ak`w>UYzt@}j=15+qL_N>!7W^n0F!rF^~92Y|V(w`Idpfj*NK
z#zK7qC8Ue=8Fb<)*5CUHu9fI7$3mo3|Id>UDbx3ffKsksM?vu``foQtp+bLV9qfH^
zRsXRLGL`yO_t9FV?|vML*YtywF{;-8atrR)=wG-9XRhmoHgL82BXa>$r@u&71?%;X
zZ31b~o5G>cs4o>_f^O(<{R_+{eYEfTY?f`uav-<s?I<gAQ!l5(V~74LI$d<?)eiJD
z=-cVrE8TjDC%7IxyA+VO^Z_Tq_3EV&FxRL5(h(^A`dRcY9MIRE1UIOkv0`3^^h{^?
zcU#Z#1?I4RcPm^O(LbWi{-{3GMs>P(^x|(II;L0AM)j_qdji<w`loM$Oz3af0c}#>
z8w*SK^ffPnyRUzh>hh-ab^GDW1O1ENfz0UtJqJf0>HFw+d(beK%2(|TX?2)M2g4k1
z7&>HFkPT-J8#s@_o}=OC6*g!%84|w*=n=!o*CFa`_%I2UTnq~+HRNh|E*@xZh7&ho
z@Tj399ewVGjg+<WFr1<jkEg+nb_rgF)D-~rHhe+hb{_-Z9h|S>m)Gg%Z^)noufJgd
z9hr|A&V39ojvJQ$M0f534c_#Q2r{go%EMs8G!+V*G~|W=Cd9BL7aoQhy69Sdn4w1k
zk#K`|KR_c4y9nl#;Sv4tP8)Vbz|k{?tCX*gG+gz@SfUKe-vT*n_%#d)(S{$J0TyHM
zqL@Uip%u@B%`VPhri?(mA&Dya5)7%a=u9*O3gP}aL;j1<NHX|RVlCOgrxM8&!%PmG
zNj1FnG=`mK@GA$GZs@1KL54v%7v#JF1qFDf41FJgWEo!l4CI1g#VAO&;W0iu%rPvu
z2X$Mn!Ii@G7Y+A{(3)qkqqFlRL)8Lw<{SQ(4073^{so`~hFzO5ibBKoe83bL^j6p{
zHe8s(AGXABCKp_(;dKiBl^OW`;K~i@6a=|q$T|;^3d3>A30*bp<AJL*{Ph<`U1c-e
zS%ew7W@tBHgw=+qS@5F95c4(kuN%Hr!C<YSma^=1h9y*dP;bz@hsFlOb^7}>8ZP|}
zm>Y(#==o_fZ0Lbrv*8_jx3n1M=fF~{!HFUUHx2TCA<|)pr*A2A8je+AWL*Z^kUR9d
z4c}jbZ#{<EFVK0*V5Z9UUISkQ{XWAQx-rpjczF%<2Mn7-p)hFp{1JQ_G6c|H>$V}C
za`nT8Dypa(F}(CR)JF}cQqXtDFl!inV+NmU7`$sJj|AAb;g`o?Z^9t5(f2qe4O?h=
zoH9HvgZ=|UFP(!P8dBQ;Gi|Ut3eg!uJH1OE8Q2ufIB5Lv7KpuZZxBp47=L{YdWVeR
zv`IN^)Xsuyj>g@TA#ySf{|m4q#tZcGa5m;9!n}*IfucmN#-$%o0@BSmxf3!+jg6;Z
z!rdsNN*52~%o-3+V>7w$Wn51oNN?jxx^UrRta}aq`Wj=Y_Q=mT@(6?QH*zUIeaskt
z6$;0V+h{2ZFg8(q@Pu)f0*!&j6I3Y~WL!xZ+F;|J2)aRi(wIW8gAn5$2ar&sVm~^=
zjFbO>3pduqz*2;9aXA`K8K2pOxj1cnv=w&G7(Hme8EKqg!uu%WUV7rr8h@nfiD=_u
zx&j$vloo-+8fU(OhjGSt-UJtKG%o~ng0ZEY?h_;$<7q2?&bT8AGD*fSBcY#c+<F%i
zm0}E_4MnQ4o}QI7BP$fnq#H9Rm6l=r_dd*@Hy+1M(Js^IL%EJDWB+RCT`+o6iA%O|
z;UyT%F@EBWzFgyWPc&XKKCuAm`Np+W*J`_LY<wE}1;zzbQ&DJKNp%24#?RX^m&L|)
z6bL9Wx>4O)sZrvMzA_{45J<T(g-R=~7$fQJSz$a!XN9ZAmtO@}Y23tsdX=$uIZRwL
zR=<ToR2xTV&roB0Aq0l58-H64$y%FHM;o^~qrMBI-l&vfgbl_P3Z^s~Z|R|U!}t!p
zNScgplp1O_dK`fJEym?(=xa4HC9vCOoJ||@cB7JlM>mbH&xS&WF}n~Rb{cgb1G>xD
zOlPZZ<9@o_&|_?BfZi>m?KwIo_ZrI*;c%bPLecMjW0evb1IBBUkQp?((mra)xVQ!6
zwy`J;*u%y{zry_yV;7wcMvY4ZK)GXF@D@<Uj5}Wexodp;MOYd)S~H+GVKo2u8Z*9-
z1q=6#t7#8>->9<D+hxjlVgh4&V0@A)l^+_Prexo=ar+SZW{gMP2h1bmyct+JXkt;}
zm%Ztk7oqQ93QL8;ArqfMUx!UA=t*@nO&)+jXVW}28eL3b??S}Y<U%PlH&c`iQ*zX_
zoPzJ}CfBct^)QW4{eh=RSp-Ed(@iQW^EUndIy8JtepKS=Ys#k*CO?y15JvBBn!g_8
zm}yLo#^a{$evkmu%m5TlnEs}PBG8mYOIeWVJ^F+|u<0-Q2+K)R02PCVnDk=!6l!W)
zN(qoKlg}1tgquEJ2TKvAdsK6H%47<M{%O+_KY%-9n!g{4k){Pyr5k1Xh(e-gO;#7U
z9c^l*z8I4<1AVck$Ek)c&NOKcpW;n5(U{5v(@xqFB$}4BLGPSthF)Arrr-Xg_g}K<
zpG>eRrumalOf|itgTrYif2!U{H%-vBgA7yo4UG4^>GpCoW}3V!F_<iq@;>@5n5yWt
zpKZ#elvIwX)(3sLrtWrtT{MN#Ss~9PdKKm`nId%%$v1HpLgBKhw+14%0@Fh_Gzv|Y
zRTxZ>Y2Pq3icM{+F_;olc^WiIO)UD&mYFurK&0GsJ`N&ROmAoaT4{Qo63kU5|3rvf
zGcBgmMYZYa=OI#K@;Lw#*G<j~Az5p>{RzP8OrNa4AnHxAPhr#zHq#>78Z?@EN%V%P
zi3<OlOs7X+soC`EQ{Y-mZD~MjHSK*HB5kH`z5-0UDTLy9H%(de7<ZV)>51z!#pYpx
zyG#QO!0tBbo`Izv(=!weyk%;nYk<9`|E0p2K9hn%ll>;!B;B$eFg^1pGzLx6+2Dpu
z@;R`3+q9FSk;A4#xO!waVtQN&{ZW&t6n%G0y%gLVGtHs2?_HA@1!l)hRgv&%!gPt2
z!b#Kj5{TS0ZFGU&eUs)*a8srmjWG1U6#Wd$KQt|}&4<RcDUr4YGo~RrQa&>MMvKrv
z^E)Geu{Y1%0nWjEjD8-6%vTyf4x2abgh5BMj|zHD=1r^N#S!xh^ip&-FFghmF6L+G
zmb0swodeFz+_V(tkDAv}DVDqW1KJFGnDuTp81yvzeF0D}^Vt7Dyv-qWsocjr_#_m4
z&Cfo->;;)GP;esH+_nUkPMQx7!BU7h<TMmQ&AvO)7-o*5ixuJKs9!MN2=j4DT%Izo
zJ&L~5<^@&gJ7fOD3w>wJaduFTHpf_J<N1p*&!IYzSaWn6MB~iPdqCpNvI)#{g8AMS
zc$#Qla|I&j%rSG|Z<0Cx4UlB>gax1}<}qqaHTQ-AG|lWvFSm5_E;<lrm|s5&FV35H
z#e>T<cRGU0G7mony$fb_9({8y+nhvIW*5yfU1-fSpQj4%OXhGDNWS@}6L99T`FZ-W
z6`0SDz^6j<TOz;|nRii`so1=UvNR=T*XPh!YF_yiCa=u=BIRYu&0chu;fi_t7wD@n
zFUp05tL9Y+uvcl$jY6NT%A85@v}@*x*CA7FPW>M`Ys?8NLF&vGXv17@9@+wt2J>&P
zK%>$8F$F_znDa|ux5?ag4WP~D2@^<*SvZcqR`afJG0$yg7d0lY-K^0;@1}VL)v$J$
z5AOh2r+JVrr*zrO=P1h6ZLU>=^qASL80anY=0Mo(HGfR?KYeDeXCc~eeoh0Q2F#Dq
z9gIP97li|c%#YLEhTG;h=Am!cyoibjN6f!X!|tg0<9LYNF~3B08e`_5uhDqd{5X|1
zjGGV8F?YgjTe%3{Oqv(cA~a=Qkq$2&m?OME9-7muVQJbdjsiDhzQDqiJ~Gew7@WPu
zWfl}1EQ_c(;E?6Z0oXlkd4c}ujusb6XE|AXD#0DGxN$KT&X$jp0On$GrHT+&%gGnf
z=w|s-Gz^)emKr+NyIUH!!BY<llM=<A7F8lNyex9xk+Ma$9*Um$St{rq;cxl15W_uY
zkw1i?;}(y9fEi$k%7;rQESdIz4z#?kLt~KThdh7;TXc8f=SfRk3y?!Bzp#N4YB^H`
zF3i$HNA+;adD?hISR`~rJ7tmW1$WvKOxxBo7Mslq8fl5N189_`@G$1^tR;pv4Y8KO
z&*4m*Wj#d!<1N|_IGSMjox($j7AFVjowJCTu#{vuNhhCV%a;_FO|iU8KcG~Lna*u#
zmfN&;rCS0z;7o?)y>rkzZ*im_Nv0)n5B*3kSp=hC^DXhT6kWC)r7c&1WhD#d3oV_0
zz+jPO@iFL^SiXM;<1MwUqe|j3izA&N$}O)WIAC|hlCd2kS1nF?K&iCk>_cCb<s_xe
zu2~vh1z5GEDglPBTaqaoRcrbE8A?UeStL|}Qg69L4^@NZA^iXwEh}z7<A#Ni474Uo
z6IBB=TTYk4e2ax^hGeUyP5`@YmY+{!gzc7{lnT6Q(aeKLhebzk)=tY(F4Vg$e$~M2
zwm8#ypvUqT<@at`SlHXy?0PL*HlVZ5vQQ1se#_@{*K5Es{Uj6zEq?Ua4_S0nLvh=}
z_ymo^7S(BRBbL?UAfpy(4HWKJmc9z}W0vGn_;lA|Cb!2eS7?7QVX0jQgOip&)NpOe
zvYalpKCq<y413Q%wEW%)^V621Hnh%Ie0{x8z7{_pl1Ho(D(G;wKF$QRi*<k|-PL-L
zqK0l(-)M-qTQi3-O&-?4BuIK%H&7JL%ewj&M7*uNR8`_*l~L-$*Ls3>Q-0R4g&_V`
zZweJ3vtFGCz2nyJQy>yx-AG5+6V@X;6VMuHRnU$)$U3qCXu;OsS}>%O)?(TRg;>+5
z_9E1}hZglP>(k#rB;4vb44)#b5_(&ovJQ5DJ8k`?5C+d!zdQ+pk=ExbK%%Uw6%aXV
z&GZew%Ceme#UC)<`URy=6Ra0MhcAiNq$k0hvtC*PJ1N!~$||N>|MY-kY1U$jT&7!3
z$l+gx)k2Zp^VY)@T+OnoX&Z6D+DM-W%(i|s7m_*FLsVLlYwe?GTb{L`8G4tj7sG&=
zZ@p<-kIu_h$8-#(z`8vJGDX%OJ>Yz?^;`^`DY5c!g~+bd8n+mVW!9%!Az5zSK)J6g
z)<5>aQiXN!Bt))S>nI&qY29-d-d9;K{s0r#tcKO#s;wtb8ERK!{p|@rU$?Gtf@`(b
zAA2akR%cD{!_fXu(sjpWU48#@R9a@1m8F$tnWdJd^6b6$#LCLFQY+K6{FbA7P?X_d
z3doQt2r>j&A_B4mSuz9^1VKbp1Ox<R|K6t`|D4yo=bZOB_dcI-?>XmwsJGkn9yD&)
z&7lz4O}l}wAk$#yPd|C1UGQV@ZrLrwf#2y(cE8gF(`@%>5MJE2W6@RAV%PZ?daZWl
z^p6hi*s)K-`!>7wb5Or)cdiDGw%ZNtz&zcvGoFIk4!gT7`r65TyHDwG;RCzBKS%E)
zJLfyF)McloDx+?@8>7(ZvHO(bijVE2??a^5?gZ^Z`t8E!Lhp&)uZz(+VAuaLT7!1R
zH{r#Q-P=*n8@6kv6xN8{$a5g0cFBY?X1AOQ0LSgJa7);xPuj6*yXC-OAB5cljIWoX
zb&zp|5&@2k;NRfIAx5Js&<-=Mx`8+`oMr*dnUO=~JuZxIC=ck$sP97S2;<`_w2m^i
zY{QHmV=Sc$?>J-2Gcf4JSVysbcgD`S==5N0J%=f=c{2Q0z=RiL6Qvrx8EJuFo?!4O
zyzj&4q1sAc#@QhF<i|)D1k6cBI^|^i84E=4H-Pa|FYE>~w)|H>&*1$E^;3-JT%Z@s
zD1Q-NgfKSSLobvOOy7MAV`MeKP&nfZ1^6Ou3~4{yh+^zdhT<7U3Pqoz8DFl1ehh<6
zFO#zjz5<=G41W<c;u#z|C6vHe8;{O&jG4LcB9SqL(p*W5uRcWQdB#=>eI_%0{usPe
zM$B3$q%m&B!F)QS{Q`c23yipKkPL>cJ{p!TGWK&pG8t|;@a+;~@t+t|7Q^a>RyN}j
z71QJ}w$?)<m+@gfW+sm@8i-atV+SR~3K%a_qNb3s_Bu>lVSGoIM-gND3-ID9W7ir$
zmoWPLAyUeSp%aH?jL<p2ENA@o^9h)!U~s6?;2Oi3T&!X&qMxgp5w;pIHH;C8cwJ|l
zXaTR55pW&6I!0G4^y(SAwt?Ja6dnd?U<}c&xRGI^$M7viPYLWcF?QslvxOn`ey3)>
z?G<;p+s=^DR`VWX9c`NKGonM_%L4|Fc7+caoHU4ZGB#2f%Ogf*J*;*y^i;;u%~-J&
z<T2yNsp#xwFk0YWA0uWy6#5w(oS^=M5x*C$0Y=0TKo2sOP$}dPBaAY9PZ?8e>(Lx$
z#Cqd*8DWHOhsGF#@eyFg8U9`v<^*FledBME@%m3N;lOkng~$Qs=M<(p$mFvjd5Aef
z0kp%+#b1Kw#MJ!;1!tx+ZP#6x7wJr_D^o?epCin_T4C=PQ}6~_$C>~1{kJn`uB77%
z?#vGZ(d)rnFM-3J%=iC+q8IZ9UDPL-5mxYgm}hsvgfFw7b~1iUw~s(hG8ZogXdp9~
z>IQ?DtEh1H6mxbWTEWc17PLZ`zJq9mGGk|8y26+nXlon6?AS?f{L{=kUqL34sW^?^
zC}!%b5Iw^z@I+@c^B9djhPjN^>#@u$t`Lc1inGue&-9K$X96>vf@kNLAJSVgk$LbG
zcuCAG+N+&s+Wi2M%zU2i(-h|KCX6hVsiMn2o%#E-&){iuf$2p@3^SO&J&RFXWG+7n
z(M;wya{OGEm|N*QR2K8>eTd{Rua7|gGIN-+8M(~2QUR04jG>oNK6Cm9XcaJ*Q>?#`
z8BhdL#GFk@(_-dT3hG>C{&^Xsgz2&eyi(?23w|_P8I#Y1OgVFjBgi%8E*~%}nTKeN
zTEz@51gU1S^3Yks6mP-I)G_S^7-2p0yEoz54QA&Ph}>i@YJhqJQ~5VK8<{Ung~%=D
zG)ItTrYZ&GHuEc*pcW>x75=s|uc%@Ej*a;)y&T$@?Q|vGWoGw*d5;-O_jw2NO<Dlo
zXNEnZ+kx3I1nh@QNh1t)GBYTL`iQxu8+u*LCR%!SGgnb<SPxT7fq}=&ne<NTV}{bx
zqMw<W4Us3z{(bObfccLF(1T3dZpt|gF&kHd`IO0_J;(@i@hceUD6?h^UW_p}{|eD@
zroR=~6U_EH@FtlPpWqj9U?uJWImp^f+YLw7HVWt+Vm*5k<S^?h{jN?dJuPaSSs!&m
z&xLhtB_xlqj#H}oDC=3<Tkz%>>mZfbA7`x(fQ%b!fHuRPtX4WO=EZvMS%`SEDt>{+
z30D7e@Yjd+6@B8tm!%>RKh~xic<9f1?;=_OtQH{@0$DE=V%R~fL|Sv4V(HgHFPLTS
zL@R{VO$nkf*24L;GY@Ai+Ky%f%X=n#JIxyT30_39rrtwm6l;nb26Kk>y$QT%mggCe
z7*+#Sik)TMpp;H5>%*5I63+^u12zdP%WdeLV;!Z_3W=;A*MlUnMt{KMooA_NgPzPX
zT!MvE)(=H=|D~~ZQ3Yc<Ygrl4F0lCafXQIZAA#s47UxwcX0ayzg28N7wJ#KNSSmk|
z%dC0pF$uY>FUZ3@mLC<q7qG(Wp<c+!qCCVEmVFY;7qPl1%vQ|W^F8M2Dl7W{?3J*7
z7^2ePGS*CbeU-E7sW7#I_1Rx&U1J>;0=ts+B?aB9SY}$PSF@JVO0S0Xiyz2!Rx(AO
zYgs#J$5_XjHU#f)uo9@s;wGzXDa<#pF6hwN$m-k)uv@I3s5qpFwUW*$H?w?y1kcvO
zni>SrR#yEZkUOm9v{Y+jZF~pVcUk>;km+ExQG)Y6>(3x`K469AVK5I_Hd?!Ovi_hj
z!y}eS0g*129Yw8sSnIE#^_aD02}m!i<R+l|SR1IGqMsH0CQzQRT9i;9u(2j6*Ehu4
zO|P7%tl}b|4YNKf!d#57HicsLMp^SIwlv17slu?wS+7$-VuCe;a&D8X_i4Hv*h`-W
z_5t><Oz1hXv+tvIh@JWxoH@+?mojfo?5p%<bY@RD0n>%8i-m|Q+jjkXXdGo1d<vOk
z?2A;8eVl!nR$OlEw~9gB**#kz;>FI7M9Z7~$){+YVB1p~+=sn{_7A>n4-*FC$8MU1
zv7BTdx(`bM?Aq7hXdpYO9eP3RpI?N+DfUbBunuM`Yw#O{uw86aZxhOHJ`Rm=cG*s7
zM6jKnLgO@h(+!YF_Gc7wiDIX|1N}4XV;5j4nth*Ymtxp{l~6d#o}`s+EPLZD@Z#8q
zKE_xQ*rG%zoMT@YgoQ-*94fa?Vu#U6?>xJeiqn(Xg>g18Q`j#1ftJQTzX@}a&K{xY
z$OZP)uc48_{>lTQ7um<@DV@b$l7`M~_9lv9=deG29pk;s_MnhfF58=O)_Lsbe*|Ve
zyJiW7RKWg{_NayIuTP`1i2c`eh!nF=3gF>Y_Bl^lZI`g0E`>}f`^;Kkm$Tpe0E!jt
zA`QlLjeYz$6sy=f=(S(Xj#XeTYS=HQfOnnUM^DsR_P|PzI`*^ofnCoQ(f;=)`&Va>
z2KLM4&}(FOJ_YX<`;!|0Yhnv%lhDkbiRTplAuIb0IyK$Ou9^nyJM3TRNOBwdpL5W-
z%Pyf{a66kx>Fs;$w2$H81NJx7aQ`8@l?&3z_G*IOBliA};8Pddhi;s1c9;Q@J?!Tm
z0_-vS16mXIvai{L^s`^%0PG3-WxBU)1MJTz(lp3kM7gse_77Qr8D_5^L~Dd?R)LJN
zxt-`7XWu#p{Ry^`F2qT8Ienqjf%7+gwBP_|c@$6%a%Mh4%aKz<>4d|aSp|@E;v^nL
z%b7Da4GJ!tm>9V2%1OHdup>6kLKn=?QBE;E!jE&RBoKAuxJH5L&RIlne-F+gdT4uc
zrc!Rji{tkiV0<{1f6(&f=)b{0{Wy<*L+d1GDy<RyId9lOA%LS!Kr4_lYCtQ9^V$VC
zbBeR#E0_=AR2~Ki<=Dn(Hy_3^(#j;9vydLl5uCsCFzb<=Efmy^;#fDpi!+>0DXAI5
z37CTsp5@d$5B*rqLN~Y_$5}>!#CT57hmcI*xU7ZxInD?jKu+Ss{{fWqoB_Ijk~yzZ
zbz%x<8{Mg?oFA}Kz?IJ#{tmtAoK?xVFfuqL&qMzrN09>kOil@%y}iWor`LWK$B~K7
zY|b9<_098bBD!x1InQK*T;WWmU|kW%i&p2wocGSa!c~s*$1q#M5z&doQjWX>yfV(b
zi*UZ2bFdYi6`b4<4Eh@93;K^zm7MDo)vx0GQ4e#~oK<whqlWW{zG`xv6Bi0n%lSD6
zC^t9?8*K$|awci3-oQ!!1)_}{dn$Up#W6;}d=n>v_8-k0R0d!L#POh)QVVAn#j;vC
z&$B@8aH3{Hy^XVh3A=YWN2s)`opYUHs`ohmW@1Pk9N*7j=su_KSB(7u=i6-PJ>+zF
z+u%(n=Z+5gk2v?}!tddDeF85Yb0i^X^>TKMK);XkN-ga6b5`vIdBQpO0Za^VK3xvb
zLC)Mi0XoF#p{3<hPW0bUALg|FjjLjWlT9C18s&_SpmU6KC<S2Soac0qoZyW9_w}Pm
z&YwE~<G^LU56}bLd2LWU$ZhXN%aObFd+?mN$7xyP%zfn@`0K)5D1yE#cg0a)AK|w0
zL5^~pX<>eh`vn<1&TT9QapT@y2!rn2|2{J1!A%%Orx$lGIpfW3Mr0S~%DKPyK+%UA
zvH_NSxlZ)n^5bT>fSlz1Lm@zaZYC{j0=Ty*x){ifIRRb}cm8aUVD42a_YC2(XzLrw
zJwQvfFzzPWaD{XIs0<~7d!Q7Zr@7ODVK<U1pi+V;?vh+!8qaXkZ-5!iUG_D|S?+sZ
z!;4sMa64LY+|A{1EuNdIf~5rR@HiCDaW^Kxi$v~gl#5K_$|&V^o_n<ooypwo-on<o
zwzuC#Uk3NUkFb7`>rdI)Ozuj$0xoey&!aPodxna*vbi$K4&`u@C@y!I`;gucx!m+|
zNak~0cEVf%_kZ-Urb2G)AoQ+qlaFCwMcjpVp-{{<&jY#2ePb5}R>H0Q2nwa#yEaPj
zmvN`Zf?3WT{%=>nZR&@+mE7(v=&a%{ng^e%xwo%Ev4%Uqfx+us6@AmBmfMsFgLPaM
zvX0a1xx4BBdV~AXMu^<xuBDwyBR7*iV|j}!X@z7H_g}i=nz=RkXx-*s-$#elTDXVl
zKz1v)MFY`0+##wwZ{y~5qw_BJB)$CFx#`Q`(|vAiKF0Kb%NmE<54jr#AkxYGhVtEy
zxX0&!ba5{~g1_Bd<#y=xa3?8Q^O(DpLQK8f4=8Tm2cIDMgd6Y{9Tpwna<0MQLGE52
zObl_C#sl;z_jgJ>4|8R5kP+@w`sCUucjsK7jd5R~dgF0!&Q0(pxV%ju4!jnsTspvO
z{1K7|d6sv9>B#e@0L~%a5sLa9=Di&R;>7!?0*0J<KcP&<Hr<8y8%>leZ|h26AK`6D
zfy^;pCT)a|^FGOiB{!a520Gn&E6%`#2k-iN5Kmq&-PvBeGD^35^WNVEa)P%-00keO
zjj~d{JSR%8`19Jl&<fzaGy_u-$lF0#*&yC+3gg>O@i>$L3g&$^8-9oIPSfi-louNf
z6Jfmd^n3~DWm6(3g7@M8BqMoCX!{ezi>ErMGrR`MT}Jb~zlMnz-cCv%oaG&)@K-D^
ztrO0~@zxDPA)Yt39wdR6^ak|K@qTiGNRo|ru^P?uyl1KQCz;ogj!~rWw)??uDsK(d
zZ=~^-7C|JPS2h*qFYuaK7<LBlt4Ls9<avJqkxZU1Z8NiYmnkWb&6`QlnH-)grN%Gw
z7Sd6mTwdOOkUU-l#nJP5Z`Z;?0nfJSIA|eHyB&&GcvH&YR1t6A8eo_3__VGr<$Zq}
z8fCnfXvbd8W6?&bg14LjgV%UYKf{?y-tJuxsp8q40ZKKmcMsHScrtpsU*|pSf@B>}
z=!gN<^9EOfcY`-K9?&;=lQw#dH1N7^L#C1E9td)a_qzd8+QjptjaD=7OG3NN^PmTK
z3-6^=h}_}5+62<ZtE`1HcX>r6;I;F7Vxf1Br=s;h2XAjTI`8w`{9x$;FZfGHKIBcU
zgI*`^<!2!Bh-drT2AOW&>vVJV@WMWWrN_KvAB>`x_YKv+_3`Ry)7Z}|{016Nc=!)S
zxMO%V&5#`A-TDUVL%e;5pzxG8hvH?Uys5M)8RN~NFzz^SKE=r=ctsRFo8&dp2OJ#u
zuWW?91N`J}s+Bm%-xUoRM}FUa=pW*TdqDp%zt4;*b>`opSicLuiPoU5{9oUOGe`JE
z^w>DcXDos<$M}2N@xvbHZ~Y0NZhYw~4Ah;kp^&%--=iGRo_tS=uXyt%bh_yTzd#2I
zKKza(Do6L_mlvVek6%Fl9N;A1bqZSk{0K4_z+Vyv#Xx>sD?o$z0{TwCDSp=}%tZ*_
zgQ^Td`My+65ym(1&<f}KCZZL=pH&4Dr};&Za4nL5APJpO{D0^fc!vLFCWaKvpFx#_
zwirH}UQuy;9|~>9^V?|ypTPH^!2UV@clY2$BL8`+7f#}TOWX1D{2BDvN#_4a!Lby6
zYz$hd{Bl})r}6FRU3!84Xd~1!_zp!N7x{PSnUKl<j0^Qk{GaLNnZ<wk3e0BP`0gAq
zbNFc#KD^BLdK<pw@~^SrX&!$U?Pd!2e^AiBkk6pJ^%Z{d?;u6|c1rOT^EcCL{wlwe
zj&zprKcXFbDL;85NEtuzM@W|Q_szqQD)>+GVZM_8)eQJs#h0?dtLEGOp!7lw-;WN=
zT<5zd0<@ODM+j2Kf2sgXJ^$NWv~KXX_@i}`zq}F7H1HWRC^Ye-`ru(RUqkE6+x+i;
z0rnmK?Oout@e|(1=<o7Z(^Nj<@1esmUHoro+tkgUk_NLq{H<S8F#Iw9QyoYze<dx1
z`uNLZV4|Nt?`w!Y;hV%5;Q&AH07fy$5BdYGA^!Z=Ao7&Ih=w-I7h54Y!vB0b)JOSx
zdhd?$&v`F=FxU2Y0jxU+cK-s21A^ckU>y|vm5-q~3eu<q^pN1)S1@;n1#y%ya}u1Q
zc!9IPaTg4@2*gy;=_>e_F6tu!&1&c!6*MizFpmkUDb0Oc@V*C7+yo8FfZ{HY(eunh
z@DF89Jq7RB!qDp_I7Z*@@D}`Q0rP}lIaU1m2)b#*?kjj;#`O9LLSg`OQedMbtG_@+
zZ{z@hJ^ieK0zZ261qp<dnmZ+6Z9^+qFkFJsh6n=aRURrxqC+TQ0(bh6!v!m9ff*rK
z_5mNDrv)B#A}3OC&>#9yf})KOJtGKu0-0!m;B8Dvj3D7-kh6k46d8{d7$|HPCwRkq
z=fk<S8hSA%3J%k6oFu6E5Ejl0eq~@Pk_C(Dv6dpZNk?Z=1$!trkR~X*0$#d+m4wa<
z0tuz_GX#osxN=eO_V-Z8#P5O5Y(Xv6+vW&j{(;_Qfu0sqxdIW@2IL7oje|(Opvp$I
zMFoQSXP{pwFlK>yMbPmnd@2&?Xen1LcuHZ(tAZq|M=KEwQ8ituz>6-XGC|nuP%jsB
zG{A0!V8b>jTob(E08%OVllFL3f@-?Iss-b0bk+zaP6PV7KuS53TET<$6g00B437e)
zUNGZ6dT$8I&Y<(AU|0x^20_p*z%&Y`)8%wapzMR)CV|ib&}KmiRXN`lRIP$~i(pSZ
zyl53DT4CajpqT=JZGtiirQH=w|F4!%Fvo(Q<({CDJ~hxGxES_dicYY53t%1yEN`Iq
zp<vS$475|QnhKR32`Z_eq)TvzJ~Y%Vc)SPB^a$pyMC-Aj`vOFI1--Oz?h`!eL#to#
zbR86)2sY$FWI*s<JscerT-pf_hXgg%5P2#{qbS3$U;&oEw&^2+ylgN>1)HZ}*kgjK
z1jvjFo~0+>gy5$YaClO%<#m8M2t9%UdO+yw29blp+mz9C6#lsuyhFmWMF2f4^rB6_
zlW@n+5OEg1{104n5$3*vmaFg)RU01>{!I(^qr&&-+~23igr}%R;kfYnQF!VhJl6~p
zp2EOkbb1N@p)(}j!UI(7d_p+*viFLvw{4F9m2C)<>VOs?JV50Hfx>cHuLTJ|rV86r
z!eqLogM}fKGYS!M1K?q(u%DJ@VM6}f7-zV!vIV>d;SvobPYd6nctoVIfuej-LeaM%
zXN0on@MA{{UwaWQ#R#AI5t3(xbv6o3#R|O@V8#jmn2zzr3x9KlOoA}`B3kE!Is^0*
zg;@iTOcIvO0QPy|?kDI>7T%{IeTs0$yYM1a=u5knG~pULYL_m2Kt5d%{zH-03}GT2
zS-2=1oCaQ|Fl`+yToR7Yo)4NObXP(qTbM?n@El<*J<#%m&w6j{o@-k}cl#CLx-9@J
z5{5>DRV*x`+K;Qkl8cZp5w;%&bg6I&eWa;O7(}s=a^d3uNLC0LH!y|QguZHYRtm#j
z09ci9#j8-iE?g=CsTICJ;lMiKiZ$@8UO1adY;FjnC}e(9xJ>s6up5N)wD?^bg<A^%
zb4yrEiKr%FKb7q?3rFn0yDfYMf74rpfo6!b3g7$%=I;oR>cV{^45R=3cUQR6Ti7$#
zwrd?E?h6l5f$9U{E4Lx|Q25Mqu+u4ATnq9@SgwV9moV-bc-Ac}u!o%<;lvT}9t(%*
zV~M@O*Uo|0CtO97+%F8Eh|UvXK_of{gsW+3JSaSQ8e~XlB>$cY>)2=w3zyqifEf{P
zXvYsYDs-p7-<WXc5rB>hyK^wG3E@67L?(r!$KjfT=tDYuaX_TG3(13`^>1RD97UCP
zp>RlakJjRcMP76nIEkERf#)omMyV4Qk@qGTbQOhC?&FBa_7}W3DyrT_yX|A5tODpC
z7j@9LlH5dlUV^^6=vAsA@(^vMl3!0zVHS8^qWP3J^A`0=fp$U^Gl`au$g&JPU(v23
z==2lW(aY+jXg;C%i$1T1r2tXVHVh(Abb+#2L81ej;KeCXOE=a01&e~~0TUu>oDWN(
zqT(WuFp)RC_rpaesTM6lB-sG{D3O$I>@%Xd^p6ChMWu9w$B3Q=1N5v&xdxrFBJC)g
zi4#pGz(l<0eKA@Iq7_uDdrlOYfzCwHM-(SY67do1Ld~scR1277k(xFSI5%?~FsY*E
zVzkmk#xS(fMQa>k_kw5v?M*X8&QqaqQS^pAU@}EVDc^QUq#cH(EYX=LbY_dvUWR0j
zXfG43%OVE~E#`_I9>6&BMEkr!@<re52DGg}ly(wmg`%E4@a>8yWFMxjNYuLy%wkda
z2wGP~8^3~y5>fK2Kr0n#YS1bZDbmm?7p>?9c7^CSn&)ex(sY1TidNDA$|}(?h4`vP
zekU=O8qsZ6cz9j3Y(5OtiuTjG_l8Z>SpfZ;qMxHc8bq_5px7vi*$n0_(P%3yHHlt7
z4`-T1vK)xq7VV~YXNxFs86;apTPa9)M<h^#*Csms74+_knDn-67s(>w(>>7>I=Rvz
z>g0gj7cCeCc_2D%0OmuHZT}dWoucnEfc8k#5&@Vlk%qn&)GgW{4gDU`J~~A4Sfr%Y
zPp@bJy_fq$jkGN27o}ukXir3W6x|pQ-6{aspvdC|m>&|oNJrwHiq14(4u?fA`$Azv
zRJsVfQBeg2@yA5*HcHlvi|&>{aY9u61JEW#8>oQTLF`UN=Lf`TfzUW8uB7dPqxke4
z@D7Q2UjXf}IG9eYJBh!bbfL32X%Q4$#7kGhuB*6ZFGP-rzng@=N5y;SC2~w0@gcyD
ziz}#tz)gHuZiAw`_^Sr=dWe6df@e?h<<$`N5@*wv&0AbW7sLs1EfuZ%h^Ht(e8nm{
z(Ca5wQ*!B~_@6C6@fWif05m|HLyxyWaXy7wg2YEFfO1M)O66<8;z}y73K2KbDmYZ^
z5k+Ud!o*%3Xoia!j?jn@Pg2$RY4IETp%E#bxe?~0#9Jste@1L|$FF@>oJUcwSg|Wb
zPU6Hf=)D>*{=5>M3F50%baGD2S^|<N=06Y2B=HQ&ADtJ6GeMHYTf(82BDQ`=!NFAV
z<!3NoY2u~-z_)bq5(*4l5O3ZJFEYf3Hv{{kn70Qond1F)30x8<($Ul`@!l+$$QCD@
z0?83Svkc_2xV-@;a>X5&K=Q=9u@0G@FFyPREEI^VHUYCxJWvka6>%UPPPP?^CqDr#
z77y4#=Bn5|5gH}pKsB5x6+143!7}kG4kn>oJgWjGD#Y%z8oDM<b%9Tn;^!9vtxD`q
zXWy&EoY^2X;&-V?;kx(-7BFkYl@yw<6VI6rx9i2n=qkA({-y(xH*MlVdduGuzobNO
zllUT4Wi*Q?=b&|4{BsmsYZ3Rpiq2N?`98RIM_f1nXWGQ=SK#4Y@mgB8wTqXsVep>#
zJgu8L#Gzln(tWY$2poMNcA~PzhvG_F+joj*-2!<eE}#mNF0rk!1!&#k=MrF|M;yBf
z8jr;-%iwUYc=a$$^oh$>1Fc`or)239@gh1nJs>WkMaH1Gi^8Tu;u?x>JQa)T&>9wp
z9tUqkJo!61N5y><%^wrnRl>t@@t1VobVAG-gxN{4!sZEs4w9)4Kn_R*w6r@YNu!;g
zqa^=B_<cyyvJS2tmb^@H6eo!r?Gc<ML-ZnXk^EK-G*?N(Yfv~Mx%&q|k4j|p!?;Nf
zQPR;}^3VU^g@@$*M5ud8`e+61B~d*OXS^jZ#Zw&Rgk=3g%!!X=oN8fxB^)Z4_LCg=
z3)m+m6}U>L`%A{FVIn}1N&^j)B>xYsAW1%LdrwKU-($R?l8F$2hDm;01ry<tgOoRj
zkUW@$A)S_#RYD|E@?H=yqa^bjVBw5p#!))fA1(Pl9B46;z4ZD%D`~$6pJF8+Y=vl?
z<R+z6<0W@aKqNsDIUS=vCyAjvNuuN^2iQpx-7I)<USgdOy=2MQ2wEu;XS(K6CES03
znI`!n0wYV8d_mFe3zGf$0LzeUZlN<L7bQQoLNQZv^F^Rtl5C{ad6s0)T8L&#wpIcr
zM{>*!<g(<-Hi+a(KBns`PofEjUcN*`&zl0t06oYHCBF^B!z&UEMUjdm(<lm5EIBp~
za#ix#|A1K{`I`fUQpv(GVA{$g;Z(U_F6pWOvqCcW4LE#Fq8fvVD#_>cF|2Ay)l`rg
z$xSJE*CoSLWK=7OcpV~jl6E!5TQB*OvL-hq_2B@!DM_NJN`oZm2<Ev_5<_{bTM{Xy
z)|w=TNv~Ow`W(EtZIit80{m`~6eywJCW)uC>RpLE7NYHvo%7InPm+27`W=$c69Bz0
zsVjrR14%wTMIK5jY3<V~S>glN9!VzFVAx%fy2TLbmbePg>XGa|4w1)_jCTOmE1A;-
zls?IUJ5cDC=+mYF=80r01HA*1LmxtMP_ifn8bgu^Dkyj=37~J?3`@d40&hg}%{%aW
zR3b3}ZA>!e0x~Yqmc!D7#Oyt5WWH@PMVlR^TgSjUB$ZO-`eCWvo6vTWcAp2&S;|-p
z5EtnbdcV6$U#2AG5$VToL-MG!Y8|kSNoP`I=eTqYRl~VS#dM^{U7Ar35f7>9Ehu<O
zpHR@rOS&f(L-CgGivT$xea}YARv+n`wAS~PDlcGQe$w(tjNzozZWqk^OOwWd79bVS
zGbB*@E#)+Vq|+k6J0;yjXP$zkJE*cRMEYtT^g^Y}D4rcAJx8&&aOvFZkc^PNMU}&+
zrS)B~7b%@i$5^7IO$sWXJ|mq&U-OHWF8m4_G16Xod!Chk&Vc)|Qcv1x$4Ni(2WY(X
zr+$ngK{}a?);Z~nFpxy)w+X;blKz<iOXsDo6j(}@eo41oiu6;uvs0yU6F^Cm%Bc)A
zT`IZ^azPq>pN?^6NUzaG;-YkQBV;nAO3F}Nl1??ke3tZ+FCm&Ob)nBY=14!GaQtOy
ztpg-;r91wD_j%HX^n5CmYTe+>73mr}XICV3qToug^tc`hSEbW@!7Gu<s=zCi)>E{h
zOloX=2Dfy%G$jbk3Tg8dSh^-%x(_3)l*ZBqtxCG@5G++or<8-#NSnQ&cwNfB0a7cS
zmIsA8>1X{gUoTCGgTf7|!y~wTQ@YWDd2W#2dJ0~nH2PDh-;z4e4!cRZoobGorEk(Q
z*>+p{`ei7#NNtpZX_YGG0Q8RZopm5>(&*I?y(@jt0}tD!Q)%sfPpVx4&<?575_oZ6
z`q~6U9!MX0LFA#7R|C*a=^=`9J(9k@7MNYqIW7?CmM)+gk{;==6uo*Zo$(^TdTr9*
z=}PL8mQ!H4U%Hmw=uf0`rUGq1dSnw?gVOC(O*ACkO53of(kMDsH7xyo0@x$cr(HlB
zmHumi<e1bz8@+MqJX%LhNL}9q=A?9j3q1$f?iYZ0K$cC{+CkYYx)2>@whKw<JtVv3
zfaYP@v$O?uk`>Tq*ID+_UQB|E%$?rvuCfA3(jJj5s6^*cSpzLZj>$^qK>fH(lnD>r
zWR1-bahIj6L#Kz#ycu>qWyb%3=Ovp*8zygA@CY0|A-nn(c)qgbHo80fWMePF?~}4*
zy1D#ip=*I1AWOdl5-3~!0Xl<ZRa7B$N*4Jq#uO}D`5rn$WHD6N5-R)qG+JS@cc^SC
zT(;o@h(ySyk=v(bM_0f?q)bZ7>?qkPI<#>{_S}AeMaz06w4{xZofcr&XJu>N0W((i
zIqg8=WUF%_6EB;UhgO2@N)JTN$uj2xCQ)Xk99xnsgPuO;Wz9|CCCeT$U^hkf14Tts
zWs^Ukl_vX+c5&&la@tp4kahh6UWUy1UFcnuy}yf66PdD7`rOGSSu>f)l5M0NSGH`$
z2aw5;^&CU%vdo<Znk&0cRZMv@TRlj=?8+3N70Bk(y1r00oB)5X$jT^WUL?z<CvUN=
zfI_<^vX{GIp;YGMfX*`69!e&c%U-Fa;~^C?3+-;M$#@rGuu``74t}R9S#lOy)w0ZY
z(5jKmrgEO^G7D`8YGsvY;AoxfwQjgpFLSg5?}n^l94I$s;j|HNkZI^xRHMxMe^9t3
zOA3H%O|mEj^qOUsg_ykCGF~LSu(im3{Sv;l%Icm4+8tRB1?t*l3#NhGm3>M_R@!Cp
zv^%*c%PfUPhin%eUb-*)_&U%Y$Tm><(nHx*sz2(K`5uHbk7Tz?LAqo)6t3=;Jy-zO
zdSu&H!NOyiqdP{{E1UT#=AzFgQ&3c@UlvQB340>zw?bn;7IFz1gR<`;V0TEiWCEg3
zWrZJtH!O3f9Q=qZj+W`8vVUorFec0V4qlAQMt4JULYAEakxALRH{p|mJpL^>dO)84
z3&<gPsvMn%<?jT*o|D|h-VW+4_outkMZV-Cv|Qz3v|l_TZ;pe*N9BJdf*g~t@rTH9
zxm1XjoBY;n7<8AvKpScgxsDe5p7Lfth<M2l96`%l{w=NFPRLVdz)>Ih4tksU%D?l4
zh@bqGIPgx&r`hOSqrZH~HOK_WovGwCQ2uHuNRa#-Eq71JZ5zQ0miN4lc?yv;d%+8p
z-z^6TlP`@2375~^4YUY(8{Mg=<>OO8BIO#2^F+z7Qfc8CdEzHfkCuN<iR&2oP9exy
zdDy~_L1X2ubk;IKKI2`$oRfdD7#fN4`i1CBk|z@AdHElHqAAbLwJrY>3Tg6-@gV8)
zyL4S$kZ*~A7a8);=Rx73{QDgkeWrZJYLH9v<usL9^2FUx$d(Jo(3vCGP{H73dHEZ#
zmn-+A`z}wevqB_aek2Ye1@f`;n5RPd+GtGk6?rec4vOSF8>Os@<<^5}UX_3R6%<S4
zcWR(fDmT(iT_z9IL8M%6q|2j1zLd7d*W@M&T~*4v{{XK_9(xp%UM;tU!}}U}Llio%
z%lqh|S1Zq54wO21<Z|%p<;N+`azp+snZGHQ7to8dK_2M<(kQ=v8+LEW=iY)$lRTah
z3eED*-GO#n{)`JWTI4e*5!@<&IUOQ*<U7siY?H@QAoZ?%mJ%k~<<luMcwc@l8Ilj=
z4~>|vhjP0FpmfUrpwDzYl3TWebjj1dd)BXd>az=N5!ayEFL$A1Nl)au3~&eJ2@ha@
zP(F)lPKV@6sO00ReBe)@4$HrM86qR{xpWG3RQ|CYcw_Qncc6^R(?@|aA%Fh_3{T46
zv4gsUBEA$N2NanvU=j~1HqbmfD!!hLsX3(h+eW#I!wOfLb|(dsPQE!Ss%wDlqG<aQ
z8m<c0Y0y8Scub{{M-}gSp><4A$-uaeE55Bl%T4j%1oYe$KhSFFq{90I?D{KqO$7;1
zByWXepkmQ|*bP$L+YHxEDb`UQC0Oy%a(ZWkC~nfjEL0KwBU)jKI;y}6SM2hD`3S`-
zF<Pe;>O0VgRJhQZElQC?b^B)&?<Has(F!)z_Qojmv;jJ+h_8b)v5ME}EgYxl{S^xF
zir*;unxN3U0uRqAW_}5hsQBPd`npq+qTwer&nxy&ty8jMbPCW?6pw#JD^;=D0P|^z
zKWSl~uK4zEkP8Y8odn8Is6WMEE-IEf!9=Da-2)~rDYnr)mZeD90Q1?3Zz<-MqbPMn
z=VisJDHvd`;&VEPT%cHua|V*>g$e_G-SCQHBQ2PV6mz!&v{)gb#N$;($3E~%6vw52
zDOF@_1g}iNqvd3UVh#f$*Az^@RnOsWjyey}8pY!wcyV3va0uSlDv~JuUZ>zwaa6s6
zX$S9bD5g^3)J;VrE$JH+y|K8E8x?y}G0t0xAO8gJwn9VC*A~T2ImjKw3%O8lQ<&*3
zd{?n-03z**zQ-W<6gD#)>`?gHG68d6kx$X)2a0PHD|o1Ipu&?*#p$zf?UCX)8d8_y
z{UC^RD?F&iq(?EO0icf+zv<yxui|?;cG#!*moC|U#Rv1zdZMVM!!QGipgfR4#XKrl
z8B#EwfxV}SV%pCPD_S<wLt#W=ZHLCFVlp3~V~W3*qH|mk@(Hjf6pJZuKB>s0Sla<*
z8U^kTDt`%uq@(g{irhIVC1Kz>D}#$MG#6zzg~eQzYKp!bQKpz->8R4_GY~iBOw_kc
zcUR7!z=4Ny>-SVC@2#9knfepTt;LY>QO=Q|<*RI`AI(qcRSnUT%CA2|r@!($IvNw8
zbfN1hQ2F||a63pDO|kt`%711;Jy;n|VYLut5v2@6mCw@=pfIJLO3T8Pcd4)^Lg~E}
z>Zg@&+@p`!M=HBYFv2M1ho`_iqjaaYaI~^t473>KvERTutDFo4iB+=xOV=v1cK|J3
zc{LE&3CbWknR8BgdI6kCRA#RLN|KVVMCW;Bc{eO2D=+<sR*KU52eeX^n;!x?O?i`2
z*0yxz`=#*og0j07G8xKKI?T{T<tmD*XDZ7n7JEs#`UQaID0fk)@Ul`(i^E){^c|Sb
zQwDztlCOMmC9n&WYm(3^RDO2>m{*h@p>VWF=}-q!tXy&#B3G4*qhY8-8AeNqQk(KS
z4QQG2`38`3Wef-U70MGAVE39bmm<-X%ETpbrb;<q1uv?V@jn8)MmZ}Jpx2eDv_P*_
zj)Xz4P8kz|)=gy<-6{=APb#NsRHo7r=9Y336{R#OrSyDjR=)WuL~bi>KGiVMqEtTv
z(N^WFPcg!~%2g9^rd^5uB#(PVIpsJ+dX%m21N*UZ2gNpel_^u9|3o=;1w;mvBeNhf
zsC1)m1P>{HzX3~6mG|kzH>`|%6|FJlHY!ygSAIu}mI>v$<xn`Fs<7>crGu*HUI&b$
z>P-ry9a3dH0XeKXvl(bks+sgy_fTD11Q<_M2W3XQRKle&@2v`@Ge9R)n=@g_M|GO=
z%)Y8usW`+>)%gbWPO6-5!h*kQ@C8T)s6;{F1*#TMW+O<|=1p(YQz|7L`wdn-q`3@L
z$>_oeQ^|_)8-%MeT!9^-nof(C)2f4QXho{d((@)-b;k>OF{-RA@Xo4cQnWZ$<#-Q{
z#;H<ip5j%7b6_b!)o}$wI;V0ghDf5ymI{R=)h}YY|IVw-p<pJfgmZwFqT0U{GO4On
zyCIXNnok9C>8fST@acl;BZ}8#s(J*F%vMQi(aKT9eGPJ1)jEMW%vIUwBMf;ezk9&U
zSMB{BlTe`AsR6H0#iVM2E2_FDP%lz_hVo0>^kP-1Cp^8Xa-lMY5>+CtUrSYMeuv#M
z)w=c2C|B7#L8L<Ewhq|WRFW^DU#T*h(5h0sR|{UX%1k-STGgp=kS3ME9{x6~dZuIa
zw^g6=0oJ0b-HVa6s&X=+en+*S6)oFc)$Q-VY*#67K=hvK4RWzV<wj@e@2hf_fjm(C
zCIIiDN=xgDPSx{=pwOj?rJ#PdD$N!C_NW%nlK!zOho-VuHIWGOeJUL#ru$WXWx#x*
za{Cvq4XEPW&>B>|NK5J=n=1V`OwF*Wg6_BxmG2Y4jH=%L3(PUq*Hjrdu3E~%2q#qe
z`++^FT0z7?y@1wb2h_p2;2l)g>7nkZPW>PB4yo5unD(%`s~uiAsjD9X(^;+g1Kzu+
zpW6qXtJ>ovB#)?VgOqS^Q+KU|7anS#L125TRnK9BUTWPo@VwQ74(L3gW>f6gN8OnP
z$&>11O&E;7T0_Z%0Cfcu*n#Q|AAlF6e&-_ePN`$~Ai?Sk3RH%uFV*9+3{|ri10`H-
zrZ{Va`U6`hWKOF+0)ZB(4*L@NQR-Rm!~7Zb7vu0dTD^i6(=lpu1Ypjp^XSNItopO}
zpb)2angW=3^?a)HKd1hR9u$e{6*R#~>UCzIoLAeNftjqXqdiZm+D2icG<D83c#*EQ
zUbF%2g8JtS$YiL~&qDE{`hGiFnQCV;n5F)M@<Q3_TemQ6IqFLSbY50#KZk3%YNH)o
z%Tq6+wRpbz3p%+`tWH>hxwxvHq(g=!>M**~OVxoCxhPZrI|aN7^-2mWTvIQ)O$(_?
z_4#@*Yt&x!CARD8zp0L=R(+pBHFfHJzhX@F>S{U#dQ;s>amxnvTsqC$sBX0bOtZTG
zUGQ$J8%-EXi@IqNc3ahj6p*{4ev%7?Hg)}5P`Il;xEqr9)CDIY*`a=jx^R4(L4BeI
z%m?bvZo`X*>g}{p?^N%nZ(Ti7_Y457OTBz2EOq0WgJiF|mvX0l>glu#?N{%V!R;sN
zM0;Qls8_XvH>jTSCe)v*r#_3R99BnD$-#)a_kD<rs#C=198)K61hj2Z?UxHt2hHdI
zZBaGbUq$ah%|brhchuZbLgSDo-3R8KG`d$H>8zRb198zjM-eesO)iBcj%c<;LGrjJ
zoMy&N!%Bq-cg-9LJoM0HWkSSLlWhg@(%82{-CMJm@?R%xn&9h@@zeOlp!cN4MkRIr
znzQuV2WXfSWeC*BUq$CB%>oZ-1Z#pWgM?@*C>k23dGHFx8?JGnBY+W_IY;noo!0n$
z1M`uZu^OO6X?}YTylBmdkI)&Tu}p)#vzpq^(HX0;$vhzwr%7A`#du9SJ>Ji0+!w=O
zqQ=h^ok^Olw5mL>S)Pv(CTlD-U1^$kwqVxNHCaZ$T+oz!hzZWnyhb7yH5>|zWok0X
z?j=oA2t3TvJfKWWw&p7;<H^x%>;UhwrrkCKZ*nzjDcqc=Nk0Y`^EDTb1G_*Imk3LR
zn*7z^UD5n&g^40fR|8<KYP|B{c8SKk7zRr<`&PiwGR>>BGcMQU9EV7S#vBITHBA>K
zKPol*s4%Nab8QqT)tc&9n6J_F@1^zUbxp%&Xw+){y$VvN$)cQ7y=Lt`v~Fk$MR4Y(
zrk!?P4VqU!0!*Xk11`+p(!62;Y0@}Q)#`0cJ3TL2G@sB1ZCf=dZ-944GmkPNZJIA8
zF|xawp(>2NU2}9Dc=t4??!MrM{{r`xEr${ZotoD}z<s3I_5j1^(tK5h&TdW39FQK(
zIE4ZpYt~S5txxl?4Ho+~kLZQ+MDvyoydjN0ZKR%RJ}Lqk*8Ck0GNRc`?~_qY0zHby
zG=Ur7;<zS+!jco3P6{wjYLaa9;Be5kZ36RvHrWjG2es+J&~VhIk{5@x|2jbQuy*0|
z=ycNVrBViG?GI;R-bGt;1Uy&mvG3sh5$!XB81PZ8gqFI;v|m`zI<7r-5qfUgPdWhY
zuH8Y~A`fji)$n*~xq2JydTF(^`ta6n(ZjbB+L~zi?V~-`ftIiKl{%pLY1h#2d{Ubh
z4>W)6HA>nBXd~#TSD^O8t568i{;P%;r?j6=!lz(u&3=f4Xn%VEkx(uBF-U~=JeAy?
z)_(CZpd+;}&ZR|2l=gdy@to0q^bug9wJr1%iqRG>0XeJfr1fvCb~*()<F#-3qm`iT
zjRrZVWql7z$=Yyl*iF$6{)DllYUk6&JWZR^ixH-41&d+ug7(`o@G`V7Q!whHws1ed
zGPV6_6oI^?T|uFuEbSo{(6Y4;=sZl0_Ot)NnakQU{@~?mC6@r2r(H+;lYFiFPDmDL
z53K+x)GjZCi7VPtS~L}DBgUXmtj#EehgY@Nj)IhEuRMfgsrDY#!<A`6&O@YJyQBgN
zwhHb0=iu8lt^Xo0E45N8jIYuzeF}|g?eFW+s?naJ*}JYysD$6OS}m<g>$LL@fYfVe
z&^G^u){BY?Z)*J*0Bg|d0?}&J#{L4mTiRz$7<QBPWm*k4YjKO>meD%;!iyH0_P4cQ
zwrZzPYVwZOpUQmOv?*g4=w0nxijK5vKb#Jcd)k1RQ0&mor1<)M?eGP(9%vif;pju{
z2t|xKwQh?b`AC~g%Z@Ish`zbftzAVggdT0v+c5Z8`%@=cy;>J4t?kp=nrOY!ul<%@
zR!_A2RyaJMy*3+UP<yx?BOKB;(gt!wd#nJhQ7z{$csQobq%GUH_JI#fOlTQY=`yJ;
zc>|yhx^2$rJfN#=1?EAW^i6o^sCz=?FNbu=^k_P)tD;j@PCBz~GyHbeO&)-#i*6~U
z4_$SO($RTD_x31SM|In)p>a(2g$UTkb>(d!ZaN)ZZ0<VddWd-FW?zGcp1N=M!mgLD
z>oT12*1fj_22bc@r!hbuUE+U*U%DoDNc!o%v%$hiUGWqf#^kR{rFT|<uH-F<p3-fQ
z!$hbqnTgIY-A-D^hU;F519pUN+C6}t)_q7-PLa9<ilap7MvI|$MpsJl@n~KDeVB;R
zEvK~bSzYROpv3B~O5kstu9j}!cwKcYcnP{?Q|N!ioYTb|gMOm!ud6VTq{|$E=y~1u
zc92Qd{YpE>6kQDEXH#`HDMZqAi)W%UUFUxYu3gZ5O$CS<y7@O@_o8n726SfX`q)so
zq|2>`Pg%NGB48m~C!lzKj!u3RotJgR2shiN=jvK%9h;}i^#V-3uAvaj0$l?aqJ_Ha
z<p8~+Tk<CSF4Fx>1ti6~j*lU7Rk!kE=#}W+c?d^Kb)K{xEYmFzL!?~ymk$&wbZ^ma
z=bA2C08*)|Ho&zi-T$bDvszdDI}~g+y7x4IxvqQlEx^?39?{)Vr+bZp*!8;IJSg7K
z<xc_crtU-l^c!@~(rw(RTeJzh7TxqQSh}OzO2MQy-JOHr-PN_xZPc#YOotQh=@`$#
zLWk}QtpM-qHcBzF2fCZX;61eIIt37YtlNJUFnu~7y7K#Vw;n^|iEizA$PDR@Iblps
zb!`;l9o9WVS(p*s<&7{us@rLU$e8Y6H(KMm^*-QD=%&zOdQvx&p4kri-)Kq>=(%#V
z4(b>8fH>;cErG%zz3pxb#&lSplMFAM^nR5f&ia-60P3PorTx0Aek<)Pj_8M%VrWP8
zo?gH{rWYyU%yGSpzTD)d_oo^acYXhJ!1mCu{2ZO0`VXnT$V)$!E(mY^Ka}4+q3<e1
zr;q*}+WPqFH`^$C<flI(g8oVU89FrYumAB5NPu2WLkrY1zk*Le`nz#3cuN1-2o!?#
zKDDqEqEC4Yy-<Cz4xnNBz~4c__4z-eGeZCW`wP8Lg;u2g#j}{vDE*EisGreCPeo_6
zem9>s0Wo^t&oI!l`tEN*V)YkZg{N`)t=mE3^$iQ)OoIL_-P`B%d28TPqQ2J~`bqk;
z%h7pW?@EikWIZnn=2P^&ap0xu=YIrVntpK#c<K7{v|_!Wk1)cE4E-M$(YmOQ_>L;i
zGxcQ@#m&}d@IZ3(wZDUTS#QS%Os@WSDy7cT^PDmIe0{SkL<;nIv|ldNpWF(OEBciO
zFo+_(=UIpp>r<&J<f{I!L5P&-Z+r<aO7-I!jI2ywSdUh@{%tDAuF!unmx@}h>A#*2
z{Yw20Xil%vKb`@D)%wqN;s>hHU!z3Pb$$7KXw>QtQz2HJJ~R_B_4<7^AUE{4v@m#6
zuX6^kK|kyRlt%rp`7nP=A41<FZqom`8N6nFfDUtUThF3O_ZIzbB}8nk`k!uqc}M>{
zB{$mijcG7=S3l_u#SXpC8n|{}AHM)15A=IygZEJX3dMvw^=GJP_mTc2WgNTopEd%t
zTYu05ksf_n9_He)eh%e{di9RG(dyGDQQ3dLzJrQdp6HKKW$S=Vuh<Lbp#H17n4uy4
z-{F9Hs$V+|qQm+x$kP%1If^rn>i1CGYD^!Q0MKzgyBS_g=pATBGpP@wG_!*tco--L
z3^BpzJZMOM6C#d=fBn#T$WZeFzz!Si@r0S~WGMR^UN{?UOXysNi=ikU#MQ9pJ6Jkm
zsG@wpQ9~4kYL6Mb{sqi&!zfiKxEYqy;ShJjiB1^wFo+MqlBXf-FQ|JNc2ISSx8Zg#
zuumAi?86V^W0=E-p08ow03=Tuay+2!Z<zftL;?&oek<R3cD`-lHxLOi{1^#ds9`Oo
zTf+>}GIWL;p8pw!A`I7~(Rtb+$ib{d8n~1^iZa~%66B0w?P*w#Hk64V5@Yxy5GZkm
zZ$5{Gc*9Ie3MLpT1K`;?gWJmxNi;-`0yD|5H4`qKH!QbpMKjqDaso0bh9-K-rW>T5
zP`qHsJ&CEvFkCEy=q1Asv{TG7e3K2=vJDGofR|%%qbv5ZVd4k0at*6!w(<;rP{1|c
z(3JsRf#Kyz*ex_Xr4uz*4DVB6Ly;lJ6=Nwju*N77ch&I2B8Zk4Mgw5C)UfvfNSWc$
zb=WO89HOOsg<(lDTGtFID<D~E&_4rbsthxyfK(f*jZmmD)PDxM*9|9o(5f{Y`U)oM
z4Erg)Rd4ul4J2<EvbF*2rXl=$v>FV%La4H>(a`t-L~j}Le}QjJ20N-JX*Q(Ne&n{{
zA#K@O3<=Ai(P|iHgWNH=8~|vW;lgUn+Fiq6TR_?kt9L-*p5eWXQ139Dq=e&rLkAVV
zJutjUZ>ooe@I~nCG(0H-$|Hm8_w+T_F2gPQKts1-*(8`fhOcRh`q+?8$LV?vk@PI-
zGtB-R!|pefzXQo9h6#$$4j6u>SH+;glk!7Dh6Ufi?o-1I4fKW$P89kZF=SJT<*4C3
z19)SGNV*)y4L?!BaKdnoLaVk(!)B_1a4;Th0h*(+v>1wqj6o3~hmB(tWpFa?Q$y6*
z*t!-i7vugGc;RZiM!A?H#tmth?xRKrdW0P_?xkZ*$BpSr;FFv2<8HLvjS?y_^)POH
z1QbtWj{_vVjQNx-_O=;crG&`|<Jva?<6}II=;U-?qdP6`{EP+k)H!K%qhzALQE(Kk
z0OJx0>I52Pd(jzWyfO`Xr;Mj)jTUTNNq1q0F;@tYP-7RROT&yW&<-!$xPeN7B8;o3
zRPnU&l^F0MjkdR`jxowuK!?xH7>81z7;UV13XK?J?0)d#jI)nJBi^|9Tg+^NaR-I)
z&Ka8yV-gdM`JceiB;&d{7~y&2;S*>j8`XJer5N9s1%qkEulJ%e-RS)XT)SX&UJbnr
zV<1(lUNkPX-Gqrt#_=&|WEqoFppk71&4>9M<8~`}myOfnp_ps@heAsQM$Q)yDKt8!
z0Q8E{p0bZc#&=!ODmF@}Wb3NYX(337v0)zEE;V}E!QV3Dqwg@Xa^s>CP_HnKQo+kL
z<G!Wz60S6Qg#f0?`1K%6R2%2FLBGbxD~HB);|@yW*BTcsg=C#^{p)b8-uNPAA8!~N
zsdo0J@he(SH5k8N29ZYN7oWq#E#va@0BbV7PZ^zN<Ch<x^S1HNAz-%P7lCW7#__c?
zaR0R#;V<qZ<B`8XI*f}>0sFo&{u;b^VBD7j{fEZyX@lBnJaHT_kBoklQ|vMxnuk`m
z@lGT3dW=^mK^`01D9qMtY<7d&ea46efDIT8>EI0-Kcwj3ka01sB%T_r_&9=X`miyW
zhBjg}?7%NGYSe2n7h}d3--P10(XtYX6ULjrVlb1&QMxxBOdsC@IcQq(5<GM?ar2>Y
z$aKCBB8N>IwnM?mH03Xta5niIg@+y{cL9i}>DwC+@iNW&6(ZiIUt(a-cEVJ20p@*7
zPA>!Wr0E?>xB8ok+n^s{>i8Adfu=7WgBN59(LnN)X_AtW!KSYh02*RSrK47%rn!_%
z3^NVUTR+^?+=f<!Nstee)22;yHXzaz(Sgn=QyV2;5>0iKlTWglHVt7elTD0f3?{|o
zz6)rnrj@j7PBZO!9hTBff~g=EOqPYf&M?Vm0raBj%?^wr({w2hl9x;i{(wl9iE$a~
z*`{3#h~$|5pa|Y&Qwr5%<(eue-kN7>|1U*hilyB}fyov?d&5H0Wm<GxF&+CAFhwSJ
z3VIit>S(ob)pVLFMN3REhoE0-;s%3PW{TYpyXB^PuL8TmG(jocYbM7bbXJ<`sd%-@
zw2d6CHbsm<q{g(ADq*ji+Af1vYpS5MR-I|5jl8Kh?RXK)8>Sa&TXWM?F^pD&X*L}?
zZ8TlWg?_W?cP+4Qo4%l$-4;{UHxOwxnSC*dcTDmlaIMW$G7IFc$t4|~?WP0!;Qc+*
zo_*--Fb&e3cHd;6o%93KdfFU4G+k%XX0+3Etqr}8OnLM+>@xMrV6fZd5($Gnrjf_6
z^w_kG@|C@&*XCfLeWsz;aCP>Zw*8CFC#FX?pgv%7je_2wX*F%@hfLdl1MjJcu>f8S
zn?hznVZ>x9!*EAUEZQuLncj4wlTG8MQTi~_glQq|7A8$wX~F7Xj-g_@1Lk$V!^4AS
z%m1M7Xr4`VEQidQl+-wEo=vfDCvz7E9y*&7ywQ2YeE%v2anyXU1zsF8&sh(><7Pn!
z^xVw99Dt;|If%CB9_GFvIw9|A9-xS+m-+NF(C{|5eGQEh<{6)$)5lyuMQOg~X_R^M
zGiN^q@1(hn$`$<0=S&z(fO$g-Is?t31t3A@3Ht3%nT=G25^UB|gf_(d73KCq&6!?6
z2{Xs+h8N*xmqqZ`7GZ9nD(chbx$V%1G|#TZn4-+eMA$uJt~Fu0qs`N4p&Mf^rC88e
z^Dmnq5^J9O2|DA<(v9#U-n=Iik_qOhw_xI&nHvJ^MDyZ2m`^glPYJ2>=Cu@dO*T8y
z0wKlxd@@L?&Af$TUuovw=n0i>=Dr8)3uaF`tde0qOxuHt<`*AAKhu1S3I#5iQ?|gh
zEOW(th-91d44AbXvo{4bFPrO)a3<G0L<aNB^>nr%-@KmIxdrA&e}h+OE*OFO74w)C
zq{wWWd<kPJHh)1S4Oh*sfe<Y*zjGRBrRHsP3ck$D{O=1#=HF@ATxo7Ez(8xvGyjB%
z>*l2tAg(ogQl6*IymT!L)|(Sg0rQ60?+FavG~fOKC=KT2?PxWcpZ)|3x6I$u{<z5;
zXQML>&E~i+$lNwZ(Zi(0yt*BhTFr<40?ZwAnG;0Y%so0t-ZgKdctE?kd_B<anQu|N
zro$ZYHoUlR-nt#;ADF$rhQdSh{78^avveGikIXDjc-Uo@p9V^|nV$?Vddx2W&`<K%
zY`+?odd<sbLZ;9B0v#ynH<#06=ZX2}O6U)mH(f?+(EL*fT0>^WEnq)2|4OmvVe{~-
z;Ek9iqW~K<M^V6X%zWv2m>4(L#DX_r?yiHvq}hY^q7D`hs+Brm`Rl(j?1PpBEyi@%
zvYm>aoGf|sK%6aq(;+n%OI8JVu9nn5kRz5nCOVH>o*x2nv&`KFN8K$Sc7o?+$$SNK
z;cYR^M(c#-(t6COkEJ6DV7`{Whrsi*3?_gVU|C7a-$2U`<CF;wvh1VB$0^G!doY77
zpHsa-h{f$yV24_|BOn@PSwzdpaLX)uphs8=>GNi%EzeNMAkuQ>6Np4vo@GPijHN9T
zt!RsoV*4?cU!{;dYca?%>{yFk1u)|*{qr#TcuU4TsM``ONpz2$vuw);cA{l=6Iw}@
zPC9OT-V*W`NV4U}C@7{_ZqV*1)pGw`{LE>VIrJN*TmGTf=mm=_g`zSnY$HT2T5i+I
zEz|NHMaM5$7SnP)%hD5%ab{b3UO{J$rSc9GF54_w9iX|E0UwY&%K{NdzU47}QnSEf
zqeohyCC3Y$S1hj;!L=gG)DCnOTlUV!(5_lu$OU$ZB~S=bYN_~dvv1i=F{E;fiprEK
zEH=6wu36eC##d>{YX+&Z=%})%+G2|d0kg*P%&#zU-7;DM#aheU^B7v4B{~3|^_JHu
zi*dt}PzT;k%K?fOH&~(@q2FlfD~B_;ENAJyZ?Yu)1Gif&U9>7}wUkpf;Esj28hUM(
zPbma_*YXxU1KTZ5l~BKDNwhtO$>^}`qTk}aWfNgPupBH0%tMRcU+C<#yhf+^9$D<?
zVZ2?I?(IP9w!9Y(v>uBcMY11TvR(mNuZ1gv!9I&51Ek+FpGtF{SWYIPHDIZt1KNWY
z7s|s8SqkW_^wgq`p*P;J#e=HXM=T-=agJK{c0qB>vatc8<CY_Iu})al9R_dG;xht8
z2W#_m_;kR!;d%Ib&{|0;Ge_&jIJkDm%A?o9Ve4=^>^fQBqJ6TnHJ}M#F4i%+kX)^U
zi=c4Cnvp~glcUxIzog~ZivLJyZ4axa0wz4I`%j_eW&L*^K)tQe6ks}GHBp$$$C@#M
zPG9RUIgs?TYN&?xq;=B<*!8z&(Z(Ra+D_%}f!4B7C<Ixj(d+Y+b=JEWM6k8^4q74B
zkD0I@YJDvQonh9WY+*nPw{lJbCc=8X05Vb5zbIsJ#yUp3_Gs(>=!cE9&Z3(-&bsCq
zka+7}dfX*i-=73pl64w|2hLmHqHu4r^%dGvrdXHL!z<N#u@KH&u(IxB5;Cl_DROtw
z`r?Za$+WhX(Ng4+HJEZRS=Mc|*2}iOK?%GZYwdq!v)1+WD9yG0CWWOu>j@$J&9_dW
z^+|y>Xg^4yH4l5*=~t{34d4}7?@^UTu{Dp1CazkS-34@swKfy#rPeugv6NXKP*$wm
zn*IjG!z-+7=+%DB>L&uT()xEdMqg!3p@?I(_3h{2OpUeVCx~3PYUv|~wN__}lGRyL
zDQr`3{h1Dx->~LWHtwc%=I2mou#Q)P*J%Bf9KB`r&4yl+wS<zz%~l;1PTsbT;|j7(
zZ?P_3hGDl^cZb0JyVl1MP;9sQE&}L1YmgeG!^-r7`}eKS(?;ll)n^?#A6l6d_w2N;
zr%c}?YZN`8x~$(if^=K|8N#r8tWVTXcx+u+0@r%2W8SdaXFX46V*9OJF(hqItg~p_
zJ7D!B=AiXodcF=>op%HDsdXkLF^8>kABc`vFGqqmYMr+k*ke}59>9!Sf7Ane!fH1g
zZXd8eLkZo3_N{dwj`j{zA?IX2rv;PXY@bF4F<tC^L!sbmZ(arHBiroNl#M@XU-Ja!
zkJ(S7HOz7Q7pNY~&Ayp7JMQ*TJ?QkXZ=zR~r@i$h*!8k+p;{4d`;`B|rxW%!7Q>Q{
z{grEw^tIpTfKEUA@SPwh?LVZ4wZHuqzf~(y1^Va+P(ti~p)#XT`;P74h1qvfz%tz4
zeFjDrVL!tJmrmR3=(ug9y;m$mqU_JTk0G70KTY+#(e?sbti;&YEJNp6`_d&)kG1#o
z0*SNNoPtQaeGx6y66_yQp#Pjbiu!TG*xTD!@F~gOmEtz%?cK)zkE833>$3X(T4|}J
zrCFIatt>S&+o{>KW%f&h&)$1)E7u1_Ws0CoSpovekg13)*&stu5m}<3GDW6<ApG9v
z``3A$d(U~FbD!t=+~?kN&V4=*O>;O#EAw=R*C;D>)}cHWisu~g4N1Ie92U_Q@4Um@
z6KKqI;3=Sf!9hVW@+^mF%4TId{QD&A<~T6@A(HFhbsetdImFST|Dr=T#f<YEVm#4U
z;IRK7tvw1IOk%(kIsDXzffhSFlLXNchq@nNsnnq_8(f(~Fy*$(9d0)R`;x;8zoD<n
z;g@CLY8+<f0kqcPXFBb5#X(H7`&9>-7<$(nv_HT?ox@BM8m~KicLf8iclhKbG~RG<
z>7Y~94Gz10L}#<Zc3PjbIOwTP=%&LX+WNOTe6<9Pw;V(ioVe|9kCLTr4kN!nq}}0J
z7GUl;bkX^{yAD2dn6=a4UwYMaIkeM?t=l2;4=CJscyI`PeGXAn$ML{H;R3Khhn)zq
zzd38jVdtx`H0+S`Eks8hb|(XL%t1CEFyjuT0itzyO3o{xzt8atM=0)hJa7Q!ogLlr
z2AFloaZ3#@o{QtVdvQrz9k;oH^KhI=J6li3Z*D^Ju;cUdV8PpQlOIrg99<T|!coWd
zL+JB!RJ;sHf5#e%-UK)<qxtl>V}JsE!H#}i01I(EY<C6?cZ@rS))S7o^sq!YcKrg;
zla5bO#yHy1G70P$$EPV6dfM?EeVi-KaVr-j-qA|6vu7NaJ%$%aj)nBOh-AnA+`y$d
zT20VPcMMtvl(UYT--g0@#|_V*FVnH>BajP@F@5xk%W)jY3)uO|%(v|2e*>V@@&73F
zUFNtX6c)=J%PBim=~zx>`E`y%^p3jjIFBalddEZbl-+RrmbRY_j%q(NHapJS2JjX~
zCkjyAbnI|}LaXCHl*G8@XjucNZaXf#4$|i6a0H~?F@xUvcN{;npM(Bg$38ktb<c6P
zGq?`N&~?!7ax5$d*X?*;578dS?HgdX*YO_<K<_&SxL|A#96x>**RtR7PpY*TaQreC
z*n^Hw+=9Z8V<A-%4m*Y{gWjlPqyS{h@znufjyrxs%Y;eC-_vPp``Ga!8wRHw559p>
zI593=hT=ZP(0lM{KjT@NKAagXU!m^+<J=~COc*x&<Y&1s7SsFMl~GJ1bYtA1Pa(Q9
zWE-L9!5E?Fktf3`5acl9{&J{$F+LW;-y@9Ayg<AefomvS<-<7h8Dx$!@U?BsdW<hv
zfbnIZGzCu-W3maZ`7^o_VK;!0Cjbd#lu%|ei1FhK=sV6(9)x5lqnRFzFvfpZVLqIZ
zLy3w=M)G|OG>Rde551F&y0_qHEF<Ly7&^u1JWB7V(~M#z&=MH-K6EBB4DVs|XBZFZ
zRhPnO+6=!_84GE}na0>e39xgFpnBNNU@ZF%Fy|TBG^b=S5>n8Y&8QEDLJs5Ka)?}H
z=qQqw&sg~foGD-=?ZwE78CHtNl`!UPMW4Nt(OC-7GRE~Pcu~$6nvd2?jJH*Arh;*s
zHei*EFYm+sDu!1GELAf$uZGBF#{KVrR>Mf!4lk}SzM)O*RmN9`;l(w^UaD58W7N(9
zxz3pD0LgmBOA6@SV07(=WFw;{1YR`R8K2LDelw$<-U}^^BuaSPWVliYu9cyr-PJ9|
zFW<oYZN{8UaHfs%Z4ykhGdyWFxWo8|#(S6H;R({oxJOIWE{5}VnCND(>9F#BMjJ)&
z`WOxO(D;CHXAq73jQO;<8(`R<px4VF;~y#|8e)XL4VhtvY6M=4Fd{dj@gbvs5i~{_
zqo06`F_NhGZ=A7#D%>71-co>@V2n}@bds@V3gj_kV-&ofVtl$2WSYUE;u|OCTU-oc
zAM=-Hkp0a2GzmE~@jF200p@;M{2yd?%!Q|in7e1A(}nrx0-(7vHFSU6m{*t}?#!Lv
zK+=QR?F|@D<`{W#n3+VWbuZ>>dRHA`)_bAPn`tP6Yd*}2&w(6e{@e`AW6V8`5b<SB
zWkbP_DgV$8>dy>}1xx^QBV_>tnJrYQ62vqt!bLdFOpk@#VCDdY=R%nKs4^#%*%gE<
z6UIEt010O%zJbOQ%*8RV8^K&i>!L{J-&SBoF$J_2J;_w2f{SKeiv<_Mw5eesmRb2G
z6>gqleofQXY390Labx3{*SEu9JaZ>)K@ylh)uS<y>9hveXP8ImEMpSWlPdF)nZMEN
zJB9h_hj28NdF}xe(wM?&IGWCMJqVNx<}|%Q&NDx>fMha1qZ0ZH%-3no&0@~arVoK+
zGk21wIn3L$ft}0TH6QwU%;WUKyU4ti57B&P?p`=t!0bo`Xd&|x+Wi(W=gfjgF>_7^
zE<y>@xgYAK%$uojri|H4QJiw-@MH8{Vm7@Dy$a@+RK!}z6mN%Q74twUh`pM5p%Sf^
znJd|_Tf@wyBh9tUg?piKg_%XS@+!0THw^6>Q%F0fI_BM4G+t-E{2fML&)hbSz8lOZ
z>A7fNrqOk3WJbONuqLJtMdzED&)Hz9g~@S;Pq&!EI*8n6&Zoz@&CblB?MXZH&k4xf
zVg4Kd6L*;}T|nbK=87?Zb}*+Xu-3_ppM}0IrpOtR-OSgHqp^p1ho0_UW(=jc?=x4A
zL9dTlN&%(^%o56w^fRsW<{Mz{bB5#~)AlFa9%8B}mpRO|hbCe4BTUUv`1X*wZa*|e
zne%VK#W7}B7r1feTa^8L#0;b=)CuNsH7rds5B?3k$4uMj0G(n!w-jWW`CI}-oLH;r
z-tA)rc*Fbstjn~sb!Pp$1qugP9keDm$m*qx!68<T{T4>y!upp^nYyxaDP!Qq`j;j#
zcb1I4+v36cfWG(X$>N-c#$i^p4=j1H;;EqT2&?%UG<vgM`vv3mVX-KWe3Z4k3nIr@
zgPSlUU)F*%5b<MepaZP_toOb|UjS?3RbU3PRwmN#FNozr1wO}Fd)aU?nC0OQnGlxF
z4JJZa!&G$;#=1Z$w{VtaCnQg>o~LggM6k9~79)~n|37e1tiNcwI?4L(36N-(%>yQ4
zSmQkai)F2O1}Jf?7b(0J&-(OZG$ycGJ?MkRNi46YG3;d4=o&bj!g^y2<UA`W95Pv~
z#mfMb&6+{Gg&Y?9B1kUl7YZfku?ng0BCF>;fabGWDe7Cmdi*v>AuFU3n8mD@sWh#G
z<#!1lma;|@p<c#{okU+bYug=4*IZ&{{R*~{<uMG=Dwf@j5mvJn6~X*v))RE3qlWc+
z4BW3}`BS>)3d^6e5m#CJoiWgBtRw^a>R2b~D;?KaZu_B7&st2G>l>_j^evYL)|2xA
z*2sF*1AR@b&~32L%(BtvdhIQ&yLZ6eWWC!Dww3iVtru>w_Cx^mHfwD%?r0mUiEeB=
z>kO6W-(lTNgr&Qzr)cSPkJYyyTnFpl2<UaPJg9QHi#0*-)?U_+l>EHU@{NXMAM3Mv
zkO!>XNVwL|`YR1!19n!<1lU1VG=+<YSbB=w53^RS!;Kwb^<PHgL)OE;ATr8Y@f3U-
zV^yyLH_qa<U}%q6%Ra(Im|*$SQLsr?Tn`!_vz8x*r74!fA&_ZSDXBZL-`EU;&g|F!
zw~%7LD}{xFY<nQR#SgJh%tNOO`_o%6;mW>AFLO6`0!?u4>}S7#Paf>mv>x+h`%xC;
zF#8Opki6K-sS4l-dn5hQz1b-PQ1D@&Ukvr5?4gIyJI0P+g7~uSRIcjBzG8rgKf9cM
z90BZUy9kPb?75#qBZ$3)HXp~?+7N&SvxDizhOqx|fu&G(5JlNfu-8yAS_Hd}-XM|e
zhI>GZX0Q7PB!+$IYbeCB!>Rrwj(t29BJu3|T<9gRuhN$=lh`HK(3s4&)5(Dp_TR_p
zs~zd=5Ep2iWzUMo<vz!b8iK*|?6g_1l*!I}7Wx<130q+zi+zXo0@>`XUjinV?Mg=m
z^4Qzypz%d^5*3&huwQP1dLet$JHRYruczBv%-&7qD<y0O-K{eA&}DGt>{{`>0Ow6J
z7uwfSEnYSI3avFSvv+L)P7V7ECGf7WchOOntL#)t9A0B9DE(Q-&JP23oqd=hwe{@H
z-=VRQUC4n#6Psm)H_hz#XeZUeURMKCH`zbY&ZL#S0(GaeZm|n8a7%8pFT98`wXq}Y
zG>3Py6|`FGVecpb>1Dt0zatCmRLY|CvGL&{JhW{7Y`8YS?pX$Iki9n<7h{;+>jm{u
zcJChajj?0sZ9L9ixdfNy5&Ohh^i8l;spy+ze|HLwK4!l^1#XIMSp|Qm*^j@Zo8ZKe
z(DSvA^Unfk?C1Qq4csA)j$TVHoanF6=*l@n4~84(*<t9rb5021z6ZyJGL4>`XM17y
zFlQzOw!Juor*ILDaUxy=@#U;q0!cs4G*!0ybJkLwdjRLH>%a`;yjMh<fFO=5ZC;LZ
zCe0wh9QR)VbArQ5!i9?9@YjMwa)vIzZWJeyUbQDVhb{p-n!}^tN(`sJ2_|AW4HA%3
zoSNGhS|VqN(jR9yJzc;|;=D~oOUazP&tX1=<EDo*sT?a#x!Gr>aoD9$Oy^v<4bZck
zoN0ib=Pa8AlF7L=ALIh3g(?`cIB_2WCYw|G9$<1f^}nDom$UBxMDjR`BVh0%N8Sps
ze9l9vWhmf;Ek$1;XXgkS%Q#zUiCoT^NeR|VoQ<(?&0fLTPG!lJoZqEDtKuA_$*7vM
zp2`O<b5dplw1)F@1<>j^U%msh>l_wEgX%epY3X-^v-L@gw}G>~1E7tZVk%Z_;;g&`
z^=8h&BA965Xego8#tEU_SvzMAt*h>EmeA3RyLQgqGSGXR#@|6YIKDUFMJGqf1?l2c
zQ<l4%<2VGg2b@f5?C0#JjN<@jBYhZQki)0I+7O5L5N;218mWGIgp>ChBp-4X(<XY9
zbJiUOA90R618#z|{xp1=<b=_eVjgqszkCF=Db7a}=$htaP(sX!TlFzK-N!Aa#nXOn
z1f|uSxu0-=eSrJ^E|7!VrBqbo&Sgh|^WYkrpy$c`W(_0{bAR_mpBHzc7Y2`Tl{DXZ
zb1%EYUmxysjkp#^xf!3qUI5q8o`7Koa@%Rb3gTwR0PQ%}5DblAZY#yDLb#7azz*fk
zVL?BPTTh2g!?~Y+jZvKBu4{%uG<TdHy%=skJ$kX+DhjZj;+k$j{WSLh9kPq#Ce;BY
zo;%_IlED3=1z;)MKjaijNaY@-de=0r4V#cz>D<c{E;!5GI08%OxZl4GjSTLuT)>>?
z>fC^x$z7icgW24^IH>1v<9fj5a>p#_%j3?x1BHv+AC5ykpL>^zn+v$rbULn(`_>yE
zMcnEf47Zs3-~06GloD<X#mh>$nG`;*<SwE3L=`vi8epoqAJXG-nQP_2QVn;I78AAH
zMU*4F!fjx|#8s~NJV0-7J?WL#z+HI=B8^<00Vqveh8U8~+(F7lv~U*;q3<TQb|v&$
zxgJPd*k|407Wo7FE_dJ+kbB&g6Z9Z*-*_LSle_B&V0Uph(z2tQ+g<?u9&Q)a!uE61
z5^*aBxX!g0;UKr_0YHbi*{{LUFxQCzyCd9sI@k7)TSUu-QSSN*pgiI}MFF1)?&K;E
z`y@AQ3ayX1uTg+*itD-&7h#&~NLxl1-hOA8aOIsm4ShG>cn3_l^EwP59=s=SK;M)1
zt_&iFc}H}x>&1Jb5t2uE_fG)Ro414F#Xh{*y#PDP8>9HoG2SO>aLt#ufFkLBcHW|3
zzy$Ct^r^8x-m6x?1o7s(!0+R{SM|^j<|*ir59P(vNy9MSHmW=e=RN%-BqMlv=KvGQ
zdr|_>DBf2ThCRs>(rzc3w`?}ZDc+730ezbHOFR1Fcop=bkLPLBz)axT-`<VZMBe>(
z(0YdVF|Emycz>v&n9O_Qb&MjF7ekB0G~R$2B%N3B4iwMw&V+-U<E>r^lELfi!5}hu
ztN9SQz#CLRJ&PB#1JKz#z8ugwyylI#2)Vq&8*rKPc)=y`=_2pGosPcd^S+?9TLI78
zf{S0stN9XWMZ6NKq$=jI>3J^U1<<rr%G*-}#WLOq6PC((>uGO$iT8RqxC-7+O%SQ%
z4JJaQinnnMyszdJeg^2vytXz#*YKXC+jNzeOKGNSyzCT;=+*IDo=4|(-rFwFsOSAm
zDWw~{d2=v|MqUY}Mw@t=yBKIQ@4YdQ7T(2|p?8yadpSre&rJr<+q`A8gKFcM--Ady
zZ>j~{UEWeJfZgN8Gtk(<n;QyeI(d6;0=kR0B902DyLo~m7)1{+g+3#ApBFt7oqfE9
zs~F4!-ZGlD`gt$Whc^d!S^q+0h*v^u<6)lTLXZ(&?h%MQ<aN9NgQL70y7yze4;SDf
zOz>)7hTbGkv;%sNc?^n0Pw}3l!=}@`Ifw??XF2hQKLopvpGq~j`}z5Mq2bK`KMD#T
z;Fr-G?;w9D0DXt}FBPEAh5y4#P;ljk(#3b<Z=(pJJKrlEPoM|C`Dt*T{6$~m${gmu
zdJlSD{JMAH+7Z4BC4{~CX~*EU58q`ii2W$vO$?Z0{A?o}_T^VMz=R+Fz|Sz@&o2%K
zXaIlbOK1$_Pw@d0#Ao*a`#68id5~bfl;S@j{3~?6Gn7B_6-XH0+XH&x{I35kT=}!t
z;*v!0Yh7U>lD~^`ZBcv%y_HVd`Kk1<M)MPXgr_n52a`aH<v&4(H{<vV={$KnUq+j>
z1b!!-L`&q4djk6m{}~EsB=Jk1fn+j&=}#C;3g77vP*V9z7Xu}YKlTuM>HMM1kUYzO
ztqXnU_|cTe&fs@YxcofdK0-^rOuj^h%XWc3-2}8Oe)XqN%;sNi156G-ZY%n7`C^Jy
z=JB7TUD8E<6djw&=f6Qak^=s(RAy1gH;+QHh<}ix4aIz!H@Fgh8dYnQ^20Vkq>TUZ
zVt7%`&!)xQCH`FdZ!l58H&CffCExiS$W-w+y$SO*e8nn|TK@O6l)1u(I(|9)z~?}&
z@#j%erH&t%338o(G6E>|{2h(3bc3&<Ttx$a^EA9@<nLa9o7TiX?}EN&ema#xwD9lJ
zlz)>ydEE{dTlp7X#b9pn%jvy)n?JDu`fdC-HPC41Z>0Nkhrgblz`OioCN$pT@16<C
z4!$HEeck-lv*3F8+o{H-mw)UHh}`E_{{zfEekQ$+`uVTYa$|sBOF@!B{^z^E4e?DQ
zbZ~E&pKu4*Bm7gJ0%nvyrw96D{NE;_KhB>?1@({kofLGK;O|ht?@9hUOCU1EucYkL
zH2;Yo0qP`(aR=EiXrf?;vmkB*xC4SeXev7>uy{lAkbps<Ls!9@IUsI=^3*vqo|@$@
zc-wyqQZp%WP&guZOy3~z7ECXP1s}n}XVG|6aBUbPJ0>Wn=gC*_9L1^p1?%4i7a-6~
z!Cs)?52{fK5gefnW2hkcD=35szB+-vaKY`>ASVPlblxFSaD#TXQG%W(K%W%&mH;eT
z&~I<XaAO2gDkY2+Y|}yil%R)VcX0yeWHiPLUN{Sw1c7Y?`iX*X2XX7p2<*YoPZmg?
zfqIHyidKrLf>?}fR+_*}_0#EsW*&xgR!~9P^mBshuc4PIm`D5M3xbnd;dYil*hDAD
zvIUcGLNQ11bPc#X!It$H%tgWbFM;F>_RtM25O}=_gN1^ZX8^lMu=WD_N(43Z(<~L#
zZiIT7U?ycF$_4W%6?;jrU?B`v2zJV#UM2W~ic6{m2~<~qS+LCnu2!)8L&}(65xhGF
zPp=A?R913Lpr>F(o#0)nsi_yNPXW0hI7&(12EiDSM!_c9@HGi8P~M_hz}f<5ZVDb&
z0=re<szl!{K`^~iZwuzr)Y~R_hRVR&1wT@7@~$9ZJ{0Z=a$lotM2FyOioNv+GQNgl
zui)~1DBc(BmBEWXLF<#ycpz{o$FK(kf(t+!6u48F(vTo|JIJsgbO(GI5p2?fdnn*n
zKx9;KlMaoH3ld((KpzPNAHcN<!HU;GCIxZ|V?Gwlqw^B>X~Eo&V9-gp=LTHdC!9%P
zy8Xfus@ZTBzI7O*KOmf<s@a3WEXoMG3a?XHhnvv%7)0EKt7&23AzZK)#8VhUd*H*u
zj9!R%3IE#!azxlj2Uop?OiH->2n%Z9+EL*-nhB5Dg?k!+?JEo{f~cSH_dVeJg}P$+
z79d<gHMD`kgRQU|B>ZqG8jlO(t1#YRVZy607$Quis8y(ttHzkZgp3zqB3yWyQVb`A
zQ#;WYAxyWSFH-13@7XA!XF148;f4x8M+@zJlsS(P{zt_ru|k)HFmX!wJO>)5g)hDX
zPve9Rl=_YrK10W|6ND=Iy(bE9&_}|~2%n&}Lz1wF($mSpFWaD(BFxzYg;Zgq8JKCp
zu`eK*E{yyWU>U-CA1Is`*8dF2OySRVD!0uR`cbANN9axWFju&PY9R83-G#Uo1;WEr
zI#nnPrA2g!&_eIaQsGJ3bCe1FBA`$qY?wx4rSR%{n5Ysq(+amn*t`y0t?(I2pj{FE
zo`@?`CuGI|<+|`0da2Y4>o(e<-zenogG`g~D%CeN3l-}i(<<apvig?r3<Xeb3vW|Y
zrA@eD2>!MU8zx}zj_@a1)!h~L{qKaWu;on*twZ=Rx!oyrq%Q(=36s+x(jy#>fxo@N
z6|2GB7rwO(V12?|HciA2gdX&g7!bZl-wGQPw$RKrB>a({{9$3v=KviMF7AOd4~5fw
z*c}z#{sm}b!i_(naa@=Z50OX0dm0#=5FWS$4=05>de$Ec1ATxwC7h~)<h0PPLZ6eU
z!vG8WMBlEZzXjMY>bVY?gQBl}VDOOWYufy}h{o=KxQc%32ezANzZ{&q=!zDS9-@y@
zA?YcaX#$#;D1}yKM?@L4*76ozV!@J+Xwg&XJ1Y8{e#OT`-OoeBSLARB#81Sh-+Q1a
zz8!t`Akhh0!W<WsU4=%d=rENjg^3n!z+l2fTB;p9Axb-nz6enqJta}1d*d*FQZ$>Q
zRnelKccL#wboLAM#ftc}M>-|?HW=J#(f6xyx#C1mQ}8%mbdhH81koqAp>S5jqgnc#
zT@<k!of)D>478pXec6riW{N)g0WcRtrBq0qCEB_Gma;`tDm3PZs-6OuD|(N1E_tG8
z`Xa$a(Kl54moJ(}VVeR`=mgv@6m6&3wn#KWZ?j^NuN%ylh>Q$~l!}~ap;{)ge@9D#
za?xvT@aB?erXQY!3ejtQFi|N=8-PZY=-pq@SS?zc5AL$)6DlmK5xr7@##+%gRPuO5
z)c*od>O}5z(C@m)Jq(W4iwgVD*eIH$Xh@Uj{2?ebi{|E`u|@PJrRr{q40fs|Y88Du
z6WDE{U#YyRU9@*0hJ8oWNGrFyqLl*>y(dZzgnox;4PA>)(J6Wlb%{0=f^>^6(VnA6
z^v*ZndPUj3Fn?dPW-Ts4pU8<aln+FIGy$bwwB$EP4u~#a0vQxN7i0(MkZ8yPyThWb
zNst*4xm|%X4@K>9=o=MnrWE6t=+S(LjEf$W0rZh*Yd6S*=y$3fm=v9+6yamh3zR#W
z5<UGMMmQ}B6N7USUlT%PpZL2PxV>L|hJIqs;=gHnJs{>?r{CW}@!RxMJ0xCF3A-+0
z%g^w_RUAS;E;sQFs_S(Z%UWQ<LoD|~qo;Ud6&eqV?`H$eOT6Y4IO-#Q!Udp5#amSn
zIVPT<NS3eo1KQU6i7!#A++SQE0d#;kmy+9o;u-s?cs59!rU!dmoPG$R!Q$P=;c$rf
zz+#AoiogF1ieX|4tu({M|4<t7gg7u9{ziy5(u+D${5O>rM2SBtfaFQ>3&(*HEnd6~
z>apVQC=7B+97S{fY4KdDtB(^8?S@{wcqx@p+Y`luGhpzHxGfJFNn(XJG*ZQjsgfj3
z%%iz1UA&v_=vna`E4Xvw%MuvO5WhkRwDaOK^p46Duag7xf;jRb^s>Z=2;dhZ?x(Y3
zIpVh{JeDgioeRl4v1BdmT@;sGh53BDxF;B`1>$F@cB)V;r5|UJcspf#i^UUJXe<$j
z(=1&oHq&drOq@aysdDjoD)hM|zNms^g*ckd=~s$3r$VGkyr~E#s>M-0uzOi7rcG6i
z_+2{tRV)6y6$)3xOK5$4Rcv>m@ccD#S_3-k#Gg}z(GBr63b8bZAASqbMsdCfLu(S3
zXQQ!MoO%YNMZEMrByWm+R^f8Diub;U##`csOjx=t{&E}&ZQ?Fk7u^wWoQX?vSFD_b
z!aZ?7H2V6)NqHa-#4p&-z;3_z6h%`8#GmJa8x*glVxl4On=z0X7FSYuY()I$MW8(t
zzy3AIs8~VM<ha;}PNF>$zw$TiPKbZZK;xv?{wEqAi=Qe)<CJ*Y96(QtZ&BgqK8XWu
zb@oe=X`XVHc#Kn3%ppnUJy>#)9AAM}SBazroSWq7XTiBk_R|Rs4@p=PT=SHC`6jr-
zk_+^(cuB0Z2R<SZP(0j6A~eJNQOR%^M2<;T*J2R9lK=MNI{Qf$C%}-uBqakV0g~Pi
zU?E7dF`U+)$0euf2@aOHHA68(vP1#DLnSQ~$_kf!LRBdzBrno;P$DI6v=EDuu#e$d
zo|G)AMqjMt!WU3KC2?p$-)YHQN<^nh`om!<P4bmD^wK4}=D~}zk}-Nyo|B}|QOXR-
zC~~OyTL8&wN)=>D=1~YNTXJVE6mulw4KSZ8IY7yyJjnzP*cT<6DJ+*SsiK&5fn**X
zxha&)qqTgI<j4)!EtW)42}P;o`#Df3lWd*?$#O~dC2*G{S69G`3Q0>SB&#L9ls>Ru
zmgKjhvqrK#4s5L?=xd-|kyO!p_o`$A2i!Hu!T^ZWNxs?$#p{yAv;?Y`%-92eZ%76y
zaM2)fiv($u%r}BGNxpmw>dlfJjqtEV5>o=bo08vGgS1L^&}QY9L=l3%+jhzBH^H_^
z4#r}<?UHs{E8dYjMM;6Xk_^fV-;?xC!HW(_(|lleN)*c=(j}2mU$^Ajd2p>q@*+(e
zy^>Fh!QGd1(~`VT@~9P!4<vbsApMe$DX2dnY0L!5pyXG|`3_0!H#%TxSQ1Lr2P2Z?
zPRKlzhzig-DzVUUf-y-W#fioxZ`_B-Bgrxr&?Y3eq_`E6l6?!{_G8Ixs+gXVRM9qJ
zTGBw@IC7Hya2|d8r8_BXb5MHxd-NTW=F-B#MY`P#5m%{`oq~LB($Dt*&0YF2eT2$G
zDzAlxr!<b@riY~?jWF*e{rnivjz|~LCuO{)$p-ZKNICOBj!IXEK#oa^DdHF`okzDR
zM7ppRBve}WJ^I3=Zply&mnI%T;|Zz!J6wba>0<-^{vxHfA7h|V(vPlzJ1KQ5f-})l
z8?AO?r2h2tkCh&y+~6r`Jk?N~mUjFJkvQp>v}22x8YzC5Ae}|CR-#n08y=pKe)S@_
zBx%D1NG40ireHordiEp?rAq&GMPHhf`56Vm)1^P{f{SORqlF;nq+ihY%QB=LRv0`l
z{l9m?WlEhW(s@Bzy8=FCN#CU!qHO8&YQW@3-=G{>uJqA3u=Awf$su`B8c30_eCaVN
z#43<}Na>P7se<+gMbZ{FM2e;B{AS?yS0YXQ5Ta$$ZI6ImE={M$>ymWsJFr_JZJ7&8
zmD2A%henn3m+vr&YU%rQSmv_yJk@2?NO{dLQ7irMSCA{x<CN38Dy^l{V%MZr3P;pS
z<0&bBLpnsIlMT{%3gtFR6I%goZ<0p(L#A0;M(3qkq#IU3@usw#A|9>MLV6%>N&lnN
z({1VMhiGh*?xuKnyYvN5=-rWSq^-bRX(t6-?nyIg&(k4|aRN%G^tas*>5>{2!tHKp
z94!!fq*I@uuUFbip|ksTX*&gB`=kp#f&K&OI~4rwm!?pddO*5>iU$X!W(rCUNkix-
zGb|O-T6{#BM<-bxN<aMqWK??Sdq|E+=h30QacONO>^_oywgqHD`qnmBnv{-C!i&e!
zs1Be^NxO~UrlqTzuAtLNrl+W{vrL@`jRP{L2*4ba9jD?HR~e6Ldfa4x1%&W$#NoZ4
zz<JB`^Puk|oAVs(9+h>_j_sK2+7IA-Wh<$y*-v&v2rz%yDq8sk$fn;17bx@o3X(xG
zRX@manLi~3f@Sa1v>qZ$qQdD=*&<rJhsoxT;lhN=)=)I?ge+kiT!ietoszYYGKXOd
zJ4&{m-f<^o6Ei@fW#3WqGDh}eKD>{W?WGvWDcJy>n~0Y^^*Ovqkfl=0I#ITr=C@>-
zBc0hyk=0WDN~&x*MfK8Tf8~Komp%Fem}g}^^U!!sw)aIinj!o36+2qb%bq-f)=Zg@
z2eb>aixfe~lD$_3&}`Yp55VQfivI-3m3@2+UgXJMGUEDPls%$6W4`PI3G5cg7M22~
zP{!>5c9Dz`2Jeey<rmRcBHMcwjis`!6gnuA*<Z&^E0;xYq>AfHvPBeQtdJ$`1F4j?
z(}Z3n<I|K>EgOu6-C9`~ZMm+<d^u>mDq~f`{54s?OgK{~d+R0iU6*-iVWL5{llB~q
zvZoiIu}M~t4z5eqa0p&>%a(3|`5xI@6gKUZMd8JTuMNn`({K^`WceuoeIVOP<%#{W
zIcK0aAiMP^Obp77lix$K3sjRcEYnfUZbZiPf{BN+mJ^U1mF=eknPW0Pa(i4>PurqL
zG9RiHnUFPRVMvp*Jo-b9$Fi4Vpywp_*##8)KKbHPu)AOWav&6)<x73hdO$wM1>~Uo
z&k<-Gl6%S^;vx^BG9_2Ji~?$I^1t2(=Ps91DZGb#9tEg8<!jp^d04)Yaz0-2!!#2f
zkuQ7-BHr>ho`V-Y^6z?anUBiHXev5pmmlH+##bKoD@6U|p*7(A<=5#q5+GkY28}@Z
z=aiZVk{44@^SGQvajIbXe)>#Dh<w-sT&Vnyd~jiMR}big%ZF%2JRz@j1ZIT%+IBQX
z%AcU;DN0`V3%HYVPx>%-G%}}O<6^|fTPcJWEB~n*7x9$*dD^p_mcMcbcH`tePXIe!
zKKlviC&-IvNuDU5prFhdc^pj?Npcev+9b<YJ;0Sokv~mA?o@f=vmj~m;be%U%Vitj
z=vjFNZ6?pjTfPNYhWw$OQb_0JcUQwwru=R$urJ6J0U%lO-h;54EuTxPyBvAkdg$lM
zw;YB-o?H?Jg^TixqiD>Rm(pxkAa9~7nnL+w+FTXMf2HtCvHXl523R7Gn+?oT`9_+v
z%jDlv?QXd|y^$&zFUhY{c}0bM=Q*@i%Gq?etK^jw$gYv^rucuYd`23$EAqFg8uY6C
z_a~rmP0pf8w@&_lA7U`q<r}C>upZv;6C)B`K}Tkq<Pq^uZ<as39_lS}#Wq~noAP1G
zo!*weHH5x4`JZ(9sa+oPJk;;VKk7x_UHP-L1-~cH{}f!8JZKR_y5)K6q243k>H@QU
z^1(_pK9GMY0O^-6`3rqR@->tR8J3IfFM%DA|48%lLwW5TcsMFw`93<w<UhU$Zd|^>
z4(vyA2^AJi$Q@`&Jt^<ZLgQok2z_yOO1|?X6sG0%R9xkxxV8y)_bGPLo?*Y@ZHg5*
zD~xB*ctBD51MY;2;$w;}x+>PC(N5e=F+o$Xr=p=BUL00rP%6_)@%U%xA5r*I(SWz&
zuQ+J<D4wO#p`(iK99TN0$frz<uVUVdaK=xukOOsp#qU&#7ob>A$+SSljyKU4qzJDE
z=5fXIE#QI`ciw|fA&Mh|PhnyURoKhWdP1@1Z<vTs{6>>zq+&`8>}bVqdembS_!I^n
ze1-qh=sTrg?0{>h70jo=#VKZ90T-{xcoGT;3dUAgN>ps$hasI&gx^D7l47n6T(Tl)
z3q(>Bnd@OFRk1FFz9pEZ82=KT>53kj?9VE8QiS%LBJUJj%v8L534Iq7s-H04EJX<I
z%?cECn=rIOg(pP-iWJAG&aPPT-xFvoQEaAERjH!*3iQepF9~6=T;cr@^e!ocR5V+m
z7^iu)Qn9)lefBEFZwElD6@fgE%ZlZDV5vrt^$E<^DngQheMR9A269!gfhrfTE4I)C
zQ?Dp$2Fwk`hD<azC|u~(*r*6x0iT)_GbkY4tXMP~KD8+3{DQul3Zoay-&VBMfV3%I
z3&2Haw<`wrK=h8ni<U=s6)L)w_Y`(2sp(LpQof^8G2<k-E=BkZNcJlH=+M@E#XEmt
zpnZzvlzw=iXr%CTzryf36b2MlCK?A7w<K_FNO7YA28R_rbY6W_ag9#(j47f%0vT7>
zchThaNbxCE7f&dv>8CxZ$j^lSW5pt>o|{rU^&jj`E54x2;C|&>RZw(RE}}{PfU=<z
z7r{ljN{T*L<(8R{bW_&Re#BFm^bn37R%Xyo%}aTT1<pt5K~MZqrKTN2I;M=VQ(o0y
z89ED{0m?r=2X>$`%oqB>%HPj`3sGLDS7fL%;~)&4R6gcFAzC>^8S)rqLn^pf<<Jg@
zoKk9%;qPhX%3grQDZf|1r+DT3*)W)(^vObFqH-hcVb3TZP<$y#>AZweg2~F;Yax@O
z{D`U}Qk7RbVLnY+m=E*m%Ekh4XO%N3B79D%uz<@@&RYY6=au1fU^Y`(OYw^f$^}%`
zo24uj05e<pf3JeeQ7(NQ3b{&OSNNN!%qDVCDOv%AeC2|0+6fdY-;4xXq&z(cjbdfg
zY<N+ky#EY*Dpjtc`t~wqBISC^mD`7*e@Pj$99O+UIZXSQN~Isg2&<GC&QPybnwG(}
z%gW!VG^Iw#cLH>+()%x{Ur}C_L*c5jGX*Hul$mz=mSDYd)@8KbQ2t0Eum)v-6C7?<
zhSTw~7Ucxh9Nkn-2+??3SxT$sHsz1Q=xbMAECqK*x$jeOca=9ifO1c1rdWHIa%wF|
zx3ZhI;62Kn6dmYO&Zpy650t^%q1UfmCq<uqK)HkJkp`7tzXJUs<?>*(K2*j~AZ}F2
zd=+F&S(^khq5Or`t&_@ON-sTDHa~`IPO1PJ(>_%ny`uK3))(UuIH>yV2{ay3t^FF%
zE~@$_aIUJ)Y0`94B}7BSUFGTn;$v5xeSprRswXI>b4(Rc3K?J3-&A?%r{dCM?XPN}
zg>HZ<?M=8JsCtUNI~}BA_d)WwYAGoMtKy!=#S2jxBEf~KX1l?eFjed4&<j`1UWUFC
zD(~%ZCPJ0q3KFSeUjTHJ%5IE6=SkIW3iL#)8nhrWsu`cbM67C{4t=LoVu~D|R+-;M
zU!3ZFcX$!6T0?=41l90NIGU&`n+;26RCO6>Oj2!`5A0;s4hq1hsO(hIovLCg(3htA
z#SdJ%>IglZXH^>ebMWSzYUdTO87giz(9Wxzyn&XfS{4N_E~u7-z<ib}@jM!{RbN&^
zKSvcpLD*cC+dPQmsa8=L<3$y}2q^igum3<}f$B7ktWZ@;v5_LxgbG}-Dw}4@64jc6
z;7V2N{U{S#ri!B-b-C(XK3XrS_WX#(3YE_{xG|L~e;@c=rRwU2NVRH#AH2A%dW%*D
zHL8<G!Ch6&sfRPyR0k>IQKx!>e(5(<yAPwWLA8PEAsSVqZE(9qmH!S<ZmQnc1HD$&
zLNWdR+Ehhzf!3~aQN!*X)tluo*rEE7Hn^QCHf0*RRPv1g?N((Sfk=;PE6vNjs`1x=
zeP8to?VbBn3A96epqij^wSLuUdJ+ay3l`y445}&@LT^}=-3jv}s_!Wq_fWM6AI7lH
z8dZJ20s3RAcWApjuDbmuG#;tEC=D>7@>-0(N!6}j(fC-!qvGHxRre8CnpUMzV9QDU
zYcl%wsb715#{KH{|AQrG^{pI`1L}XP;Kf08-C^_{QlI${U@q!Iv=4Gshjv5V?xxnW
z;f=fc_wB&;P`Blw)l==wg89R0mzf}5>IxoQJE9&r4n=SEncpDkqrMh_#-nP@hv1H>
z-(C($Uv<z@H2SHRH-qz6@1=lefZE^#E>K+@180KNbDx38arNRi;bE{{U4IVdL)6`r
zU<p+hUxue)>XmdbD_k8wzvdI_Fr=(!MW}B(qc2jepzmBnsT-(*@1#0|j^RbCn>GSF
zMr}I_602So3B6P5cW9nEtxjlzr8xCrdhN%nduhH%P)kH0iE4XNA+XP=(`lwiQdd8M
zGs)^zcVRw7EucELRP~W9Kuc4*PeUYK&7A>}v+5~&5YMSUqaZ_udIc@7&a375u#~C(
zzi)wkLA~b|8ne{vqtTeH<}C%6qxPCcU#{BsV|bsZzGSDU#zl4YB>c`-&!hWPpx#2u
z*h2MfDqSj4ms8zWv3m0ia3$(;8O)ceizsMZroKsq80G5Nx1n%JeTp{573%6hI9jRx
zgPy=D_0ld#R;!DS0s68!;U$dhin@$Kn^)CY?^BHbn)*Wu;?}88+=KpgwVCST>(xnA
z0DMFJ&A-5IQ17KUVxzkKJM=ZF|Mi63X7xj=m}*f6QbEK`b;w*Ow5k<p@bH%U_EzZK
zR;y`o*QS2|Iap{{=QE&wNBt7ThwrLyEul#CJ#{f^!)A4;=hLT|I@Rv~L8D8ZPK)Vo
z_3WQvqDTGZKTzydZ;gVb`|5tm@b{@NZ-U4JwUI)|{p#M6kQ`9wZAIgtx`2vwhtv)9
z!W~v?Xu2CwpQA1KLv<<z;zre8^Jx7!rmmzN#kg9~3jIgwa0^5y)KBF?W>W1$C*~fj
zd-b@aQ))*lx0zP62-`{X8J&vTr<wH=hIT-6kS^sx%@7xjhcpYQ%Ev{M^%fdkHNU$7
z%uN&K06lk&=zaL>q0vzM<2_G}cK})sYv#WXQ7_H8Pl0ws^GzEXy)|D_*w#nm5D;O&
zUTMmNE9<9unyO^|HKCN;4$%C{gxi4{$-5XtkS6vsfF9TEod6fCiAe<s(X60Ktx!$U
zFVG9q1RJ0bu9=L6p%a?dzl4Pd&HJn1VWcLX)T1<oAH$cEnrKR|Mr#^gL0^pKYkL>&
zTCAq*I$%y|mVJiS)0+3`h(nyl{tcXo*DSW7FF~_55Q>SKW(O#o(U{X<B1vQU5zZuQ
zEJ+Ya(|k(DV$wBB=sf0G&5dSo=QL^Lc7|rQGdw)6Sw>$h&(wTB2MQN7y190+S(>kG
zK+D$L{1zHHnlK7i<!b6^ca*QWLBFa3P5K~6p=Kim&`UIlw_&1GvoZxDWtty4pkASQ
zcLeH{niU_w!zzt{_E9yO8FKX1YQCWwo-3NN#UPEEzr<*4(g>p{YuT)spA57X&C)B-
zxT$&ReK_2znY)P|dClT2@btE3);HkVG@sKtuwA3R36VRRc$(ktY93H1_nziu8AykQ
zcOD|0nwXVvv`e#}VuanA{#^9+X#S>3pkB=(s`0(A`Ik>w%RWsxrC=Xu`g>r$UsFeE
zo&ilO4Q5cYs|1Zhn(c1@W>`~R0?84Le+wEPYW$^u8Py!4HSL7v33~J<HF4Pxd93N>
zz~3p26V(??YhI@8l9Tr6f56<QeKrq$`?c{$;gkK4_Ir8(xoErIhK#HB|LAw*rhTIt
z#9cc^Q;Uc8m6<T_sl7#eyu;e!O=vu#-MtRPTg&M~qmPz%5%>3~w&NsFj%nBZ4Rv2_
zVFvpAv>O6p$zR)E1d#x3=WFN-)W&=Ra@?*p(R3HAT@`~dg=kkL0W?(Gnh&4Cw7HGA
z=_j<y=?q1LHk`83ky?M+Q=Zhm9E+hvYyDe6VzhR8o1M~jI0NOhw&?(_Oq@1k9Z0-(
zz9&!;v=yD;lC+cWLOoggStr0!wDxXVpr>lRDCwG}T_Ax>y4Ht&D`&MTI`Vc-TW|-W
z8QS~@;4WzU8Zg2v?K8I_nXRpQ4w5<A!LLDbwM*mBn5RvpZT3a2<O2*MUz<l8)dKA|
zt<Wpf&i@g8McNy;;Zw18%)Sj8CE9#?!<TB;eT>dB?IhK6lxv^-5ktGAt)@{_Xiu&J
zTDA7-B)qt+{U9EsM(avdO10XxN~mAaI#Er_RqfSdxU$!@cg~`*PWy%u>esb@u7Zd4
z+B{km-p~$_7Y$lz1_fc8v|mt8qgmTXk8X>$%LsB)+w%-yTD6Vw5V@uGYyo#$%lsRC
zZQ3tx!2Nb@l`}lNqus!UrMuehZZzK0I;26QL;Gtq^g6Y3mV<O@b4_UM)>hC4xknqi
z9Fo1-xKR4!-F<DvGhq9)dG2uPf!3eS9SmxdYe0sy1yr&-tPS^q`BCjhv`rt=PS;=*
z<Jvv1gFMn6-Gz%Vp=Ho>HK~1@3%zMAdnfEV>GpjJk$t+KpTq#2b#6bQ@qlgvt#S_P
zy5Nj`)*;<EJy$L|#$T}HsvD&(v72sZD`4Dp!4_zE=)CFe;Hhh&<=|o6fhPg#t-DU~
zM;~2u8x)S}e*PWgm`*eZFMM@3C`jk0`%wcFf8BeOiVV<2(K8pQv(rL3NT;N^#C}}Y
zu@V}=x+nHSCPXK=hHDY3Gq}NEnC|!O&=1!oj9}O&bPMSaZ-nkEs&I+a{o#NyMd@Ds
z93)mZMCB)^be^ryJFSyaMl??M0!7Q>b(adDo}e?<0y<ImLjfAk=ol-Zmt@!7@CQxS
z-Hn4xitcI-6jOEaw}6(WlOBM<bY16Fkh8jb6pcBjn?vc<3|$57chBoG=R!SGS3xHl
zFX+a1!9<qsEm}`y>lV?${v6#7T1w>V;*LQtPgnOW$VJ_{6xhqx*?*#Hp#mL`l5&N*
z8rr%P=_+JUEY=AM08^s-fa*_5b+>4pP^N4D5C+S2oF_5ROS+gVAQifF1|%zWtu2tO
z(q*5AiE7;^ZUDQiQ(XY5(QT%8d97}76Fj`43+jjDRh`V92YOAHLi0_Xj<*QTT-OB_
zV4(H7m093!=;qN*qCvOjQ*e#C56ICbT{q=?n{{fMXj*ieDIj-K7t)NzR$T_Y)Nbki
zq_Ey?-Q<0^-KI;Wj90tv#!WQd(;c9CiVoeAFJikst5fH;9<5!vZ2Edlw@&*SI(u}l
z(p~G-rBUhNechaI(ATG{x`Kf|(CH~0*{}Omi!lx8PSbI;LEVRspfIFc{RSF`b*vZR
z@2GC!i;x`CwbI&UT$e>Ls7JaV$^3*asE*DMPwE<|gyONzmC8`2biMCFbXu26C*GX&
z3`#cb)9WdkvS0sw5=5N!UmO5;K))grdM^6j_tEI84-JBXo4%69>#qNS_A?%OXD&oM
z^$WMdi^KYKdPjNblh=bgqW8uZ{_L~7^-Lz5^3k8BI`5<U)%55d)8Bg;FuwZQtFYv!
z|CeHZ{`!iUFcF~7mP0a7-(Q8kAbs;|P&lp+qT-NXeg1qH4AEE9sxVZ4c?qssnEu7*
z0T!VzNI+kt{?paai_*&p%zje8q6{+8`qlSvy<+qmz2Rc4-jmkbr}PKt_jg+V^UDy4
z(}$!$KVJWcg~kN^QJO^(^}%dNp3$%T0^?2A@3etS(a)vLWU5|jhNEfvAE+iJUBB%Z
z6wd0e(wuuvpK}!?!><3r4AArXl1Z4z)IZ3DQy28}DEE`2kEKfTTz%*zH0J4#&{Z$c
z`>{a^_4%IxyGYNFVxYzPj5e4k(f|A|xKh3Q|JFtN2tSCF>oeK7K$r9{mcUSjzLs)T
zmHH+MZdB>*@pLkxTK^M0<d^l46eXz9KYJ1ywffa`R_u!Y*DWxARbRCc*w^%IDgdd|
zzd)P9>-rxffL5=+NK4xr`t^&^*Pz$Gh6~iFA6*U;P5P*BF_vci{TBh<qOYU{+)e$g
zAK-7RezAQA?B3E}psK9f`m+=aYSSxdz1*&U_7?i?=tcWM?&^Qv1@j&HmD{1%slRvt
z*j;)bdb@P%FVNexM?X^zkzRdQ4;t_5H<Y8XPrva6IP*ZipEiU2`kY138_+i|hQEXQ
zm_qug4(SW2JYrbiPGm$Mseu;{^{v}5m{C20K2$iSfBzx4aeWHyG#}}wt^#I4KhO_L
zllnXv8XxO_qR$IV=@s-?PU}B%griP|Di1X7Gq@ds<bFdN-4SO)1)YvQVAxtlvHF9C
z%mG}JLx#E<bh;R(w}QADnv((QW-x_-b2rFefQW}-EiETK4FPo4@~}Zckqa+F^m&LJ
zF*wl!<!zY%5r~gr9j)k(8Xo=u^T!N-QHssikQ)h1Kf`Paqxc(|cGCMV!0=rXGy)Bm
zuL3*B;NpwXA2*!K0vBv>35KU3hIRBd3^g#RQY_41{1#~82JeHAJYk5Z=_<nT$39%(
zNW(dAU`H7O93XPi@V5md+7LmfCSnXr+94Th*b@rZP8rT`2B!VA;cF9M;tc=LJ&ZTZ
zq}P6e;n^<8BpOz30O%RR68bP)l40uzV3G~t2hf*dcr5^TB-QZfcl4zhjAOt~H?-0!
zE5q;%z01!Ve8&KtX?WfleHRQbP%J6SaO@rwvJKl7V=Os#!!Ek`xrWhC(3)q+qJ7Op
zgTfyg`3BQ2I8$I4{uErHq2?w;iVWicFkfs~7YWG{!;TQBmm20!+@{RHJP5Abkp46D
zE*V^@tf|7VV-<X=Gz1<4sWMn{V7J=v)HZ-!HrSU>qqW9hehH-3aFlM>6+>wu3|=)X
zb%u#+h7<H6sWWWRpz*rlV=C3EHyka6!5fALr_k46n5N%tqoFGl*RaVjI)uh%!=|I)
zS`1ATD!FN}G=Q`keip&QTZR>t=(}ymvi}KB+YB-~h|+G5`~lEAhQDp#?i!M5uXfMi
zK^ub(L&QP!bsE0^->b?HLzODshL$9V^ceR32b5kzR~oqchIVgQ>N8}}KchS_BvioP
ze#4PzcsO8~Ll4=Y;rIEtKSPE?@$~*1HZ14@+KAyFIwA4UpuPi`QNs-eG{y{TUV_ND
zVVDY%9vO_c;mm|#`5h=s8tfFPeQXG#GW99LpRSOcHUw3}87Je<QSf4)@xUJd+i(11
z7y6uyRTQW_V6@RH*2Nf;O20o><1Lys-Hf~Fzl_|C%MZZ|5915l;G(Cobuk)`80UIJ
z-`m(kv!#!5&kyMHH7@xDKKU8<y$?`-<G^J!1{m)vK?03l^ktbKV<D~Kj~n?fV=TeO
zoDbkkh;h#%kWi!NApQQrjJtM1CfvA7iorx04^vJ*%J|^{$ec7*P~B#<aq0xP7~`^Y
za3<F1`8!17jLTk!LcDRwyD*qweC<p0B^h_pl}R?L?tn`%4$!Av(v8YasGl{OmILgZ
z@r6?m$uNFS%WeC4<4TI~W*VRDhs*_I35EQ#jLB4Fm2FI?I7W`~FrA&sHJa&^N}lnH
zwNNN9Zl|bKp)t7_7q7^;XgL&0jf?*RDKmCn2PrpZ_@b}EsHcr}rSXORuv=yPs0HfP
zMkReg^|IagAq9MDj5##z)EW;`4f++MmbQvljc@62*{&HAS!k>?{y+hndgIa`ar15%
zzoB(tgYk0?&>D>wDevB7+(e}!&Bo^_rP5;bSOe~+QS}29T8*5KFu+^Jo>^#YH}3x)
z=I<EoRhKZryGC6&T)by=peL}yD52tmPNPT&nQr4#Pk`$&zC_P@ukjUHyxcb~q;*E0
z@ogm<9~l2R0@wPDsV=xA1IAj4jSd=v>9HCzR$PNK!?=auMvS#ah&(iYK#`$Q<E2e6
zfgLm6NC(;@;{w_?PZ$@p!{JF|JJstvHgXQ5amv{J99)|=KJy0@oJ_OdgirfSp#e4f
z5JdWcO7RYw*33rZAyXZ_eqBtPX}92NazBkhc$oT1V9?X#`vJT-Y?|@EP?YHrEhBwQ
z;XyET)HD(ey<?_Nsd~oO^aUj-{Y?Mrzy+EfOampzWT7eWxareg^aY##9)K?)rU`p2
z^g~U;H*qb(Ot0>NMz|?Z3yl+|_E^}BFx9+`K}4Erv0a!IW%~Rxkdr3!V~}W5EA13x
zOyA4~TC8c5sv%FAwuEB1r%eu@;KC%BW~=~MqRAEy^Jh%%W{@P4L<G!a)Ao6G&=k|s
z4v=({VLvp^nx3RM$T`zdIuwv;dOivcUogFJ56)znX3$b3+tftC`5e<qCj8Acou_w9
zp6S6Vs9!YwOPQ5?lOh3L6qtPc(N}14_XbyF+VKL^i!p4dmzdVK(<D-AdUzKG%S`Vq
zfQfQbu^;p=nU+w3w8HcUMPDmTU;GK|DpS53Xw{~ipMZAR)bS3`YD`1zkgPSWosYgN
zrfqfLu9{}iCic2%8!f);O|88c%MH_P3dA*-%FSqOG!3}YB+_K+^27+6O<UGNqs8<m
zMVM}yo~ECFtLYWG+_y{-6==L|N;9Fc%`~$fCfZHkQnL4s={g;pxob+N+2fw+`qz-`
zFsbN-d8a9?3|yD#=L!s>+q7&xhTUTd>cv&-H6fyeN#wq1%m-|rX>~e8ADBw%LF_l}
zru@*LY1wS_4VhkUg6OcR<|n|6n3Sm?4^1ly;moKhmJV2qnKYk5VchhHN(LuPokoyJ
z({Wn(JvIrSfWnmN9Gx?tHjPqp%*p)q7iipPH{X8)iq2*g%^nBLrP=5_Xx_3PUK}##
z9tLqSZ=<BGyZN*aI1lqG6C^#&)3nArY@QztP%m>S3m4&tnK=T3-sZ9n^!b=WenH<+
za~%c3kD03|X6<X{zYPn1X1@er`kU>~&^I3g%o?h-4>Tt(1PL-PUINAA=E_?11)D#h
zC{BnutQ?Mpnp@W4j)a+yr-Ou><;URD3G-J@@F~LV#06-iId(bJqs-$JVmWE9+zgax
z^O_2H7-K$^4wP7PbSlUx^K$znWKNsiSHVP_xgrBDCYsCM0ooaJ)ox%Xndi;~mux;C
z1TMwA<3)(1nv=aSrnBaHdUDU1U-(~`%bb^nzVqe*Gt6h2Q>gUsf_a7q%x9T>X{nZN
zj^2RA9P=<u>$&FdciTbp%zFiBy=d-=g^LB|a0*})nxCXVZ;?6pEIchXJ5yamiP^Rf
zlBMRpD3CI9(g!eKZtj=?Qei$x38hN2AOn(B=H;)WvD*AK59*iA3Adn7W3HG1ky`U)
zHX5&(>z7i(;i|cbLNwRRs{eyVo%u5_jN-aEvJ0cAHz!f5;D%XUjO)~3j-@D2quE47
zT}|d7s+?*zAIb)3i}@$o%ic7{_JXvUw?4vnZ<%i<LGQMCH5I?LnZ;5VYB#r1f#*GQ
z3}$W|y)-X#heoG4;6tEwo1dowsva{AfZ<1CUZ;fl`{qg7CiIzCQ!eF!`Q#QD>^Be8
z0DHiEEDoT9=56aCGGsnY2mOZ4UVlS<#5~&x<e@oe6n$gn`XMNco0;_5ePn*~Nl4l!
z%(=9pnKUo|5;9ZfJGDTYHZP_7<YWm>fcbrvpB>@ae#<HPO56d9t`+(RE%Rw%amdn0
zn`alxdoRI~t0jUqxNa7eJ0#sLQ9HqTSQ06E<Y{?)6x?A;7hNDP%PaTMc*Jh$p&gsI
z<t$}AeJs1^7kkw5(FVvIvy4;F+Sk%VfgV502NcNjx0DpZr{k9X>mb3FL{E?q%eyqc
zhFVe&KqSo4xf$x=mWPy7KVfP82AC0+Sv0RkTGB+Y7iDSB$B?2ec29~v#aQyJ5RJ72
zQz_jk%gXN|dfHM)d*L|CrD*iUTb`xkdkL1Qw}6&t8Jh+DGnSzfFrRG65<oA-^6K*t
zNwxg31lKvuV*3b^>6Xkd0Cv_g6%3JcmK!ScWmv?C;LcmJ>`s8mv<y;2?SjRd3aN4|
zu3teW*YZLMNS-B}YEds*lysgY-?G6MiUpR}Xv0`&@is%f$ReT%z1XtmCn%Iy3jcuJ
zQj5%pk(F8Yd<L%EVvzy*lI1>q&#J=WPGxVEmamHJ0IjkdYXDnqIWvmR%NF)7G}c(I
zQh2=9(nZ^vD;7~T^sicOQ2_FqW#~6x*IB}xK(1S=X@5{}`FkbE4a+#qqz#sD9ssP-
z!dn4Hn=GAcfZ1$$naaysEXDNX-m+Bgpx@tZ%fr2ZX|v?fj=bHnvJEEgSXT8z@vi06
zHjMY4<@8Qm=MIbOCP;Q#8qYw#%i>Ly6y282gYdA&a)K5+y_S7cV|?GD_}?PS@)}iT
zJ+O>WeNn$fO0}c|7TE;A1}#>khwQV4ERhuK8@BWWL2<-V*bLBzmUYiSX4FzagBi1=
z&=zsrvXcYzk1PcgWS_9SNSl>O%i<!4Jhp77G{Tf6F&vH4md#TjPS!K@O5bO7dl?G*
zt+gwG;%puI6O9L~cj$824_bes4cH;;%M@F6v+kw*ox9bG-bx<UISe#<TDMUN(_yQ&
z0FqwTvWM{Zh?PHp!FXFM(!lvxPtptXs5Q<D+%fA{qcGuX9i_t)e%6=f;@<gNTb_f5
z0oE2O1q!t0Qaxdi-D><7^tjdZzx=z^#=}()u{Kk&RH(J`TbK{CzDGgLaH}un!%kT3
zD}Wtg#mtVMlQr%FxG3ux3KyTWuFl7`h_+gu02gDOMP9^OPf_K@DeL@`Fm&3QVF5~_
z^=&n{GgkZL9>647@4f?1ldUgMtUty2#>W_Fsx?Cnv^1*|Eo{=QmL70tt<pMh8P+cP
zAA<AN8BNg3w8s7p6Bn${(JwB`+R_f}Y^%p77;la>{7o3lwN|Rom}m8+CD29dN(B`1
ztxfg~&@ZsI(U)int<O*dy~wKj9-XDuuPf15W<9zE&XikU{uy>FtycP}R9V;4O10YR
zMo)LGH8&rYu2}cH2ZgKF>wAH6-MWgRd-c{{GJnGw?hl0qYfBACqt&q*m`&Cl-Be84
zYBkU?f?HPhcA(w1ewPZ;X7!_BYP)q2AKV>lAg%WATHW4-;ytUm9R@qB&i{dQTK%7e
zPhHlFluGTkURwc?9;@*JE^M!LMh`^pTUk`6(`P+wfuRRh-Y3B9w??j`Z@>&#KU)tM
z2d#WsPz_mybZ&jv`V6IqN37W{P<&|3LcnL%s5PH<&12TL$l$m&a{}a%^%W|IoUq!d
zFk#X<o6d+nww7K*<CJyn4?vl=&Z9a3CtEKi1@_qzDMq;8_Qibq29vWb^*OX2uw4s-
zzKiWyUl???_5BG&H`_QLqj0xfq-n>)c4#F$^t8>RLoSDHtLa*J*?y<bV;r%)+YeB0
zn-7JVeQX)OLGP&T!DDd8Z1wa~^tIih=#QUGLhBlT+eQbd+XHOds9rA6_B*ZmgKQzR
z#XN5NnQB{tZFTe!q!3#oMbJZSo9QDIVYXFNQyp%5(g}7?*qo>&F2Xi`5h#(iHJLCG
zW#j$|a?;jDDe`FBCTBPkW1CThLB!hLqCen>v#p_Qc)Z;vS^$^?n|&Ici8k?n;Lg}S
z>BY53vb}o_Fe$bqEzGCdmc0R(G~4A03?|*?djcY7ZL9*=J#RZhrIwktwLij{3$|Yy
zppa#Yo)0eD_M0Oxb8M3}Xw0>}NrCh{Tk!y(FWT%Y{zGe#Eu8YK#Wr~<xDuPT2xz6Y
zNLrbf*-ERSQEvPCAkZ$^PEeshg^jZm&Q#iR;xLLT+h!_dxNJK}M^9>O8%eL$w#^Za
zUa@UFg~qEk&v!AvI$QKiG+wub)x!IF+q#uzpxv-B@F>h`u=P>oqS5wcCoX=IZM_Vl
zEw-(jp?}ln5@7Pies#|}V7J+VDO=lan^glZ?%K`<0sEe9?+lO*+uKyR(P_K;0o?Ag
zdC{rrZrceeA?mStWx>L@ZQT>Vd~9<%4UuWvi&3z*e@D$LfIhh6w>~Ji?%+E@!DGiE
znykHc+}#ez6FX$~8@LGZJFZa{BzZ?PrBc&(jATRR{0{b4@F{D@95IHLyJP4qK=XGD
z(#VQ;JY_~>#g0n{0MoR?n}NQr9czl<%+L<z67)^%$SZ_T&i|y-Ce-Dh{?q6?@=ri9
z3<dquNm0Fs|EK9az@oUm_i<-t3%e{V?96Oo0i!XR#Ar;S##j=gi5g3yiM<;&YBZX}
z2F7HmB3)4g1f(lPsz?>Vf{G$YS3rt_3Mdw=sQ7=+=lA_T4-bcP?>X-|_wMY>z2}@e
z?EK>$1)URiCPacw-}!)6aQQoz^}_D?o%gIjF6|sJ0w%8Q988sBH9MdE1`&UUJ3E0L
z>QHn56BOg%Fa{{;4&fVMH_O4d1;ak=;4%+BU2?cfq3>%BrL={pcTnzxNSi|w)!N^4
zSgY?x_X~%`8)4$5!<Z3JeB*Fe0cTtsj}?LQa?ElE@pU{#_s#&vT~vo0=$KEnQlXBS
zZWvmuW9w*4NxY*`21~~s|89e1s^c8e%W(YiKNvje*hkeqS&l93P{?*XL`nP{$7%6&
zzbJ70Ee-5xNB$O^Dsq%j1;-i3^)3KC>nLpmIp?@z6$X0VG2}nER_wUc2IPWc7S%pn
za(qd<vJ%ICJD_*PaU?A)N*%XNM&nh--#5djGRNh#V=H%@N8j)Y$F}JZsdOAY0DYz^
z$5@=0lU6&HEQ5=+jt#V;sdJQ4c;UL^`Dc*1;b@|;>n+C*%K_T%_!U9`{itC69D`#V
z_%1Nc;c%~pSsV_B>X@*3z`wy%{sX`U<|V}|ZZgeu+Mt=q(SU1Z6xM)mXL>{vTDzI2
z85qzD<^(+joLD1O7kIK~sZuF`y&FvlYy4=NzkoCE|CNfr2RZ)%Qy;XX!`Z?2XfHEl
zI_>4Z`kZ!WV}JM<z2mw*2l)6+>+pMmE1kvs+J_RC-;A4vnVMMjEzrI-WxoK#B!(&%
zCokxL@^{;)X8Zej^U*%VhKKT0%_1mIn{xv)KU7<ycX~G6kY<c5!rwEad@wn)mUf`!
zM+L2Ie{vmz_SseaF{nA=wDSLXC(Yb1RymNFdzk_-^Ii=A=KSrZxd2^ooia!Zf2OLJ
zMJ~O7SnM_#e=iA)g2Ga#J8)}RQ$I*9FQmG>6*oN4va&i0W`1p^+x_Z+bV^{2lLqo@
zpZcQrw^>v=w9b|8vFqiOz1n@{IDWe`uANZW!*sVo!^6a+(KWf3*+n&~o=nwA*!5x@
zA^`2p)V>c4ALiW?%!Mzr>wmABVS)mo*upHzfhP}{*dL(xh*?87%wFbZAV&3?38R&n
zJNwZvkUi{@4zk3qK8?BD%RX8U3!dx~x-z|3(}&Lh<ITELgwBWkj;c$2*)?S_7{(r;
zZA&<Nl!CO!*m{a_#j~eBgrx-bB9(3?vg@Y<Es4#bgAB)6b93k=vr~=%JB1xbp@CFZ
z@PtSj8_)vibapzeX)@SKN+q9QtAlz284J?{3NB@{ul__|4!cSVl#|>Biiu@$CaRUm
z=JXV-%;AC`!HHZ>*@?zH?&=Om=5xa+C3}jiqC)cmj{OBFr#XuhjHr<Na2rsHxckfD
z(itw0f!<ke3YDCl<Nlrnh4b7?6K!>ixg8!D#075NN07P5ji>Wzm$*Ayz?E>r=xEes
zZVas{u5i|q;e9FBOS#yq+}v6iEaR*u!csXmG#8Fu<95%6dIk5#EGSfR@$W&QihE2u
z-D>W{AsDLRrd)*CTJFqGl!dM1mMjIi&MhR-8(a`&U+cN8bTF)eo9G15M$Sn4?wj0@
zX)w{mU7+t>GdDH>q=nl@)l#k8BtNL%;=<_|-)(ND6r_!tSqGGMZXxBv?{Hfx!QJJ0
z&0y~ymobMb&pNo@>D$`L+4?}gi?dh-(EHrO<p6!aMSlmyZf+{Q0O=vOg$hv~ah6m!
z{+NsW0F&^9bE2xY9xnV3G(P1@J>cjwPW=da&$)66oxI?VQX1qXx9c#VUvXtmVXv3F
zolh_Bd(FKk0>(*_yaaRUEK$(%GEMReWslM&Q?>&%L*gC|?t~=kGr(j@p0)z!q$HYR
zhgp)t-Du2~M8(5yj>Lz)rR9=IAppB3nNtD13d#CnNLEUIq_>nbN_JCy#ZAeQQb?NG
zCFcV`??^tgf<}jA5Y=#WN(%c!(L;KWqEUOLyQu2dQ@T<CM}6=wV=%M6(hELl^pncA
z!5M#PJ%xxPq<_tULay|aZ$a{;H4Py7(rWtJo{}yphI)bY1FG^kEnPeZ779($amk=X
z(#wUgdq#To8n|=PbA#dHd1(UOql=}@iLi7*I&3ENFG>&9pzo6Og9or%g15ZG?qz98
ze~i9KRzSmUmi0^mX_1)@gS5)-eFXJeG8cO2+?E{@K-y%njZkQpnbe=q$0bugfs4;&
z>u|f5zLR;<PRdC>^d$71<+Cf{g^OHCds}b$EGjSYk)QWLqpw^>j{3<HX??a&p8CJ6
zuUtb*<pBAUB24T-dEQN+1j^^oLjRClN2M}Ba$^j*Q28?x9XSt^JJA1@2$%my?>>l;
zcT>qrro5Bx@h9a^HiBfyM|ELlvgK`=G{N!@=*<uL@`4HIJ0-6l1=kAXZzjU+)AH^G
zFkdLYVhiq~d?2mCF3CTluS1D^g)0;;%NLD9;}!YYJ2b&p<v#QomdWpakI~o3&uZZJ
zb$K8yU~kBWUxH8d@^%W6Hp=A_p?_08g2GTua`iI6G|T_=2X?D`9R;Ir$(N>}u}%Kv
z7@)Mvi|Gb)SN>TN6z<6fUW7=eyfp{pzI^Eqv<P}2*V2NcTmC7X&~h=Gy8`Y9o5>$R
zF~lsK&SxGryXXt^p=K-v!Nbf})7>)M?Brp<95KtKWN3t$`)x=@n)&U3NQ_xy4ZMgo
zn@t54ab`RP-H)32QYZmS9|~zFn5`a2l`n~AA?;w3%oa_D=y9{eX@EItR{A--$TAyF
z#{+WAMr6U6T(h>*0L?SoO8LutGc84t3(Q8)gZH%A#|h{wG+RJB`y#U)I?U4<vr0!a
zo-?~iS+?_LLuqAHY?iYbU>D4MC^H-MI+U?8WsOElsabvoaIczmQ^2sy%z8Dr4ztU&
ziR&~A{a+oDnHYi*JTQAm;o)vGdrHSXH1ne8+G8`t1?W97D=mTEQ?t+M#`VlBfZ{`a
zW|t}4`OfSW#Vef@_7X@sE0z|(0~f_lCJIfuDz2IX#!aE!ff2YX9-&%Kx<~QZWAu3_
zhEO1Eui}|4hP6*ov<xEq6`Sd#=mAB{4d@+Id@&c~kfLxm^nw&SXq%d<*hYJzG({^_
zo@Xe2(xLB!;>phd%Ty$~fIF$!*+3UzmZIwuIGn9;{Q+E#BA^DdnyZ*bOW{1l%5LcA
zE1uJm<&@%4K1hKgmkxEFR*W0~u28Y!52zO@K70d(Gm2km1%FoY{wbP&#XB9GIj`74
zl?%lRhY^6jpqL+qzKaUCAc~w_Qds;5#S+Ds<q*BBP|-zrMX_ZjNU37WMwl;C6jVc`
zT#?g@VP8{Ri3M7P;`x^_U#VE|7bL3`J+5f1R%k^?)+khUXslJty9IJx@qp@%Zz!(O
z4!B;i|0%p^P<+%vFAZ!|xcR~1n~Fvw%r_}A=*(5K;%B-NS`-->P;6CvL~H(Aitl%!
z@wUQRj*p^EF?BjfyJ8%b7u-?&*#t{>6;o)ncTeF!tDg?V+*z=+Un#tSYXQoz520{a
z`Lr0Ap~?nY1DV2<2Pk?Hu3SR#un1+_mq3eDR^qE7jaK$81&LASE1(#w%$2~=IA!P#
zG#*oieFvC$Wf2`WPf%`L1Cpqmw+f)gm7kcSFGcw;)dQs}N6`V<Jmsoea4lci_5pk<
zPzKro^R!7hdksJ@D5q2bv|QP<7u+@F7}}3lD9vLq>`J9hiM}eOj|~*7m3ha3R-??%
zKwqu$(~B5(o${*~*uAbiOx2UOl)u%1+*bP2YOhWC8I?=7EBmj9!8^)cdI;QA22u3#
zp3=0c3VwGe-#P=kOX=_<%->h86M+3dIdd>9bt~V|Q}Utm8l6LVq#VB=1|KW`p(6=T
zl-lut=}|tTvvg0DN`GKKQ(nFbkr&Frp8(~haxay#yi$78+OJo6g94PVmF`PH-Y8F+
zGNJ!g>9_}MpK|_h;NB@ep_RXr`4D;|i?ez1M<6cd3uuqwYHq$7oSV6X-gD`0elZ&J
zw8z|qR&5^U1CPLaFLVAm40@Z7q!ojY`LDE?@iX7P9h|>;4<!%xnL7ldald&>Jbm^7
z=8GN!`+)hE)4?4yKST$)!p&6_R5)T@MFHIi^U<Lok>=mhEjHSGY74j+^I-byW6i(&
z5nQYJa|-&rFdsD>U{0!+%OUBkDvp3b7gbmid9Mm>fry)GTOk~ESM8Wai!e`BS2tw5
zR5upEMQ;_q1fV{uZYPNPsVpo2<FEQ;1O~cabxj4B09EH9h#XRJY535BRIk23U$81<
zJ-iQ5y`TtIsH%&qzrs}KX{8>nn)^BWj;Jnu3WZ43R$7@wsX9=>YLZ5)GQS3BjOsRJ
z9ph9<qkwi))wB~b$5g>z0xe!O@e_~?)jPUbpHS^T3-g(({WIY9N!4+BqGhQD=%AOa
z>X`}29F^n&NS<mTebe(*_b3&3TD9tH=oP8P(dOlhYR~U5YpPJ?P}O#&>VY{#t5p4F
zp|e``?KyBYDz85QQ>z*`8jW?TfpO4pQQfDNcdN>b(xbOjqbTQcTeZjxDDA2T%Q4Un
zRX2rqJ5@${oo|<_Ckf{7tE%@y<e_TwN%;FnRXY@Yk4>tA_b|avRKqD$@mzIy4af`C
zHi{~|R7JiIm{+RKOYpQ;_1ke+dac^0f){U8XS!hit*Re=V|*>Xri_)J#V(4I`di%Z
z1=(j2I023OEoL-;1Xv8thu#5;%&Rbe(Be3KD*`P{lX+ktvY0s-Xh9ZS5fp<h#?WOF
zV$n(amctfhX&|8%J7+>N%;M2bxOT)M{0<}|EPm_<5@|7>p0ZIEH)uZ>ZSm(hNXA&4
zI)xF&T5vTWM=ci9sl8(strRVYw+Q|hC<zub|M#kbB#X;GVW7t?oM;u4Y_Vh~%%@n)
zm;jP$;cy0xX%;0^>z;0rN9DK~7H*?}cEZAu-eZ$#v5Sg(vn+<hf$X)E6@hqK-uMNQ
zUY6Md;8TF5bUW-Gwp{fEjm2^m)wqXQ4)>+ZQMl#K(a?yn{KpxdMq1vY995L1Pzn>#
zmgba_h_O6N;o(@zS}Oibwp>e5$di^?+d#4`lc)wX+tQWp7de)#{eg1DlA|DIspUXg
zCSJAtnHH2amfPvsSZjH&8gAEFt{y^1HLqK)r}fqi%h4Lh)LY)AyGVoO?SpW!(Q?^6
zfZntW`v@kQEIq66;Wb+h{|a8TSoYfl$yQ4}P2Mfb`V}B;mhrU9Y`6UC7l_=kJe>uU
zyOxV7#(mGyJP-;`EC*4Dy~onAj-G!{EyvOUy=RukUP0rz<%k*JURbtLY068>84e(?
zEL$k{)NA?rI22!7whTk#8%rN5H+yUOJ<VaC<yUmgIjMhogFa_<$7&E4^(=a(x~ki#
z?%z$FK*zG&)!B5&V~@IiBRG?X+TwSJ?o}_)LElq-i=IPX>d+-<^i~&7#{~PRKe-6=
zzUs$ReB-D7l9K5DYVX5n+^3GEDc!GrPFdjqwHSfM1L`A3F>8V9XH>m>Nd001NRT>?
zinxN+w;Dl0)NzzWJ8V)<qdiTiI*ML(5T^E~caVjv<C|dqh<X@h!y?tTSHMN7N7Jd<
zX!W4I7;lW4DMnwcdgJ%#i&NWBl<KJZ!BvoB>d8l8B0)X&Ym6mP{WTAfBsKFrCgHgH
z8Re#u)f<ljB}HwrT!+?F^~|r~MVdM*5}@ho7nB#xP-oD#_JrDjHc^@ColO{1mOADE
zB(v2#opZ=huW*EVuKG27@AK5nAHsaTdcrEGpHfR`u~ncxb_UK|P+Ru^?4p{R3x!MS
z-{=(-C2DgMElw-dYrP>;r5-~C4b|#>%h6b)zIzgAwdzWLSgKQJ7QpUx^&z^k-cWy+
z1%-O`d<w-isK-)0QKR}p+E?CGFAhaxliHDjO3muje*xB_R?y_PsuM>+<hI&<BO2S(
zvv!%_cf0y9)o<KU&vu5!UG-umWbUc=r-F2-^?nfTR5#L1yGwn5u9ExestHhdpnjxB
zW4GGaAB_*yo1CEVNF8|t&h)68=@i^k^@S4jJyW~TJ>j`J_%g@~^=LPUyi^<AsQmwx
zdW|av+N&NE2@PkfKOJDu#cK3HjMvrbKVOX3&8qAVjA@TmFI7Q$SY53Lx7X?;T1k0Y
zHLs;h)+*l#eco1|)1%$TDtaIqeXY7E`R8ZVoDRGGR)usrWS`Yc`loLDt#;0!%B6Vg
z1qzHJ(R!^EpvSGT<-vtvJ>LLl(yW(khlvd9fLv%~TA!qCUY51vr?8Y~J<JM{wbprA
zP`_n8hN{zVTXV7C+N?iW0<PV<a5mKMSgYx{(Ov6ydbm8co<n=6C)UP~AsO^Ip3#|d
zsG#e$bwAooys<V>tl_Qo=P79HvmQAGR^D0vl>%KS%|W_)oiz^$-bLe0<r1!%h-pyp
z(aa72psyxx6i`AnjZ|0>rui!Xvw1{QOZV#t&Gy?6iPUT!3oc3{9R$f3&34l$8nR|q
zIW$r=Lt|k#SCc?R*?F4jKfz$WX6rDB6l;diHsFG$`2bzZnwDnhU(!sWWoC&c;Y*Oq
z8ecksc16>f4!u&%$lYkXs)<+)yJecm^FhirosZCXO*7yuhE$=c8c!EtgXSQWoi}Q1
zDEx9$Gja<oHED)BL8Dn?=L4=qbMhLzXw|r_2f3vg-iJ}#){K7wy*7>X6}WcIvUYHH
zH22)$;ayEO5A}PR)P88}&`fv(L!BDm8mM<^GNyvNuW1=>j*IYtCWkWq-J0O<@!>qw
zEH#7TBaO#?C_dIW&%>CWXok?qyB>|Q1Kd+h)C|Bp)BHFa3ePp(bOP>$=I3&Vywp@t
zsoE>e+8RjqY93RF@wKKh2NvFFKB9cuTa9Wr%scVb2&tQ-&V29-%!vy><^|AP`IG%2
z>c)3ogG?ZwPy*~j{5Mm89n2Sw09pvYVKF8@j2~wOy>Q-z9*;-(zMtW51b<@}ypQB>
zmw}7o=g?9vntvTdpElo1A&yx7C6#=|@y{rxX*$Zg4uJkK-a8O><9S^tS`+wxC?B54
zZ)^mY#6N!vFOKukl;29`zoA#Ir0{N3aGJ`$$$(@U-(LdkbbbH}lnnk99T_;m8#aT>
z<R3c$<s`42i~(lxS+vK^=7VU_m}BB|G9jAFhrfr`JpNERxO{#i)u^4~)2Ys>fLDD3
z{nNZaIjBPZ)pdXt@go<a?+mY|$KzRk0|nd8@jn(q{XEap)2f)SqyWzaeh&rrF7mM-
zLH!bckp5{)3ICLGl9zdt=TnU73SUJr)l%M}A3Cq{jW?iC#@ABCTRA_6vcA{&5_*(X
z@bBofN+s_)8X{HvD5{L8<|FH2zJ~vn?AG#&EYMiT&yhgnI)7p})Nk-Me}UBVo6|9t
z20odVJ&nAX={>MF`6HnaZQ?hlfHd<X&tilv{2AK5wDQebh~DDQ{|xRnZ+{0OZTvJF
zxYo|!QK9b+|HDKWyvwhp?b1Cy^(q=WcyoI4ck(4CFr+U2CyEo@=bMkh(Fc4F?eM$#
zPfAP}(?dS23e)|FFQTW`WBxpS22c3km6+KcexwNQDL;#{H_!NAX^sAzU;77~dBID_
z(o5du5-h#q*Ls5V^1<|6d(F>V3CTD7kYAwwmajeq$v!?c5yO4QH&F$@laTlsZGxPI
zHmXf^5u&K(%T*Xdxd=DGk52x$3yUwp;XMMo8=Qv_MJ1+t1%VcEo<h_m_~a!V+loGK
zL6ZRDBdBh`lCRM75PE*XDM|?Y3uFI7-#+0`6%6ec%;O;vAT0WWHbDmjdowtEQ24G2
z4hIUK&^gOP!f$cV2oh#dJxZ{UL<jCeglu<A*I^;e3;LnLG)f$W2^(j_Qn=8U480@5
zP^wXj5RCNR+el&lHH;-nSWRbUqJ<vXR>lYyweUVxSRD!xQ=Cw<7j};d+#Dz#6UO}m
z5-+5L0WCq;c^{&Q!Vub+B?-6VL5>SiG_%RVW)WVb2+M~6G*zhVfr&Jsp2GO)!qzT`
zWC$^ITR$P(ABzEI3J3r9H5B^MT_8)iO_A?xlh8i|8aYBOg&}i=Vyf@R6SmL{<qQ6y
zFn>zO-U+Tim_8O7r-fb1z!eHFC{R}<ELj4DGs5SqA$eBt9)Wo}CwQ;K(9R19uVA-W
z`1d)u3&Ly42woIQs517F@LUU0BA6_<fL<2HQ2OnP5EzEJEEPtjLF1}0I{~0&!o>eD
zv~uBM0?@7rGvmQk2=NAtqEd+Z5ujCq#~`>?EgXFc^EHA)Kag5M_!Fc~xKj+U>q3k(
z$PJ;c0EX&?xx>)cARIRJ0j5#-yc3pg3jI%lGzrE%u+%L4Rszx@cyiEa71n+a?v|jU
z@~Yc{M*#HOgf$dsXcwGmjekd2PO;6q!sK9J-V^wI^mPc=KY?DSu=yz(yM&lJfZZ2<
zc#ggY!tM?#AMX}!U&pW?3XK%be<XDNh3o3E;5#2fdm<PpT-hUdT}R(j;mZWTJQGIU
z1bHq5ZiT-ugbaE=&r2bVHczjFVRT*f3Oc$cycTAThvXaKmvv}-D|}#ty*}Z&JIFiX
za0&$hoy1aez&MM^91OaMi!*`dDvm3F-)>?v2T^x%ye~xdhzEkv=OH@Kl6kL~-41L|
zaoAQ^@)F-?pzbXuF&LVUs2qbK`HEvE0L4!Xpx2uCi$kgSVV^kRKQ!(aSqpk!RDk&2
zU}zi=*U&kHgQ5q8UIWETmmqUUO#A_$LE^KgAi?6&Kv)V9t0=&DSiF4(lA$6`d+acA
zr6>Br#k&*=Nfry};82QKHWiMhirph2k|r*tsBpTtg(5f^;sE-Nm`;diXmgz@&cKpT
zdQz0r;xS81+73^%#lZz|Ek`W=4<fnZXH=@4C$6P>l6*1aEI?0*)u*9XAUZyQ!fBCz
z4ikmqYz;_}nB)S5GonZ(&u7KH6A(Ek{u2Q1ytud$T(L>~gX(23h&Hr>z9_Dt&CDe+
zm~QqZ;uCu1-(~ULK$y59Ccgq&saP=^idV%+3jtFmj-@X^x!6eGk!xZ$J<Te_@}+RC
zQdEb5s}et@s?2Kf*9|aKBVM6Tq*k1f3Ftb}^bc(suZssLjD15CQemQA?1+MBgShW3
zhTSO6;2?Ta{A?&JHHll^!EUqYO69gK;zn1HR&mb(n7Ab_pv&X7xOoXg+QfV+<8Bw<
z{{kX+MEm97?uzM`F|vDN^3MS45Q9wgCWTHhm?9KiqUBR4-WR{MhQSBo3OcsjEiR?P
z?}wuANr*fW*YwAj9*gh)4bUfIbRoDNG1~)npNd&D-e=-qT7NzluPle&3o)5$`Cf`H
zBVhiO7-9u`y<#DQNq8;(Jc-tyZ$z{Hka;WqN=yAd@%9i{dM6(BhBHpu&z50m&f1JD
za4uR;T2;Dg|8;;RH*FZL3f;BIk>K`d74(Jm(3T&BYkRfFZ^4A8)|v8tURuK&V0vpi
z(m{N*adZLuY8~d&Cdf}4Lk}5$?H01TPir~`wEbF_C*T6K#q_}(&@Q0G$3gAV=V%Pn
zZVP}<hqOW2@F_@pg${THYd@pobRpWPPcewY+DS7o`cQ4sTQr7gchL<dTw9R_pN?pw
z)<YyhI};_|CTXPhTLdGdQQDvB%{bB8D?V^IM!Ve^Uc_osXx9~|JxnEmN41M0z#Y@R
zzYTry+J3)5Awg?p0~3kbTsM#;ZEhAMk85jVA(^a|`vELP`<DPNRlDFi45ev{=RiGO
z`x!lzOc~nrAE0qUJH`$&nc8vmbvUV=_c0o?w13bwm#vL0L}QNj%oQl+YLELvGEW;x
zar%6194$;vX~)uiy+Es>qb#Sj$;nVC)N0>Cy-53tq8?|ocj?kOtNm*h8qaBK1Hqj)
zX%j3VTCBY#LF)zWxRC(8sBQPh&@O2o6LyLAX%uGtveuXKAy>2v)o+w)chLjrs`d-Y
zYL{s<sCK_xE1|3Vnl`rweHB_&54cKg!>2G`rEQo7Qms9<2o`Fz7GFZIR%<#!(WyFZ
zqy*kv*FK_8=7zTVUrbcJwk8)oHE8F43eiSw<)6^MsohF5+oU}@7ABgtG5w&|qJ4h|
zd}`Gmx&?(>+P}Jia$DO@Mcr-M*Y&W_uANMqoIBdceGs{;%?pQxd)jIf1$jHPRg{bD
z)Lx*vxi0M|Es(jdRsRG12U^SXFyF0Bq9wsYZQTQKkF=Hq^H@8E?ypa@185D>qa94U
z>8IMOlY#O~n?nnW=i0xL;Pwmcnp$u#wblQDd!?O2M`(Jr^JY;w+H0*F?Rnm4BR+x5
zTdm75$n<G*X`Av+`{8VeIO&4kLBv`26RlcYbUq^db=5iFL!X;2;2ZdKP<M#-tAV;<
z`RF^Odk@9g(jeU<q&ua-y0H_{7osbC0urk8^M^v1&OL@+#2l{si{g|=bjR#qK0=pM
z3cHcIM}L5e()}btKU(+iEr7=8l$6nn)tw^HIGwW$dPj9?3aB2_ZTuJ{UMB{CB<S)Z
zp^&Jv{Q#0lx<oZTrsFzK3e+X*whe>%6x|dQvzVl5I?IL7NZ0xQ4w9ied=sE2beHw8
zl&R~cWy48b1Vv}Fbi?n#r)=Fr5p$8Flhe7~TwNSRTk>=hDbSv;lhp(Jl#ZcDXo2oB
zRVkm=&HWU8g*tp2@O9AjQexnYZelw`OlNf`sr8&L&=)4o>yB8!M6vE`s<6GF`<%{K
zU(~tP!qO#O(+<Ft=oV4v^|J2c2N=v1-8y=|NU6@a6QEah3nsyQneHT+FV`VIjjx05
z);^F5o&6CsR_b<AF=~~rr5cjeCSAu7&>CG09Yn3wjctU9I^Dp@5WTMRjRCo#TS^=A
zdR;S(zCl+ZgGi$;W;A@dsSBby>L#6(0{qRo)dT74pwk@(W~*-baQJjfXZ{VyZQa;U
z0oJDT`WMc$>sZ={-O-s&HA3UA?yEGk-qQ)wA=9CYN(EY{?uG>{b?NM9qVc|N=GPz(
zbnB~u)~!20H{^%9A{Eph={^@g9_tDV;NcV9m;2yakM6%8F?mmQVS6w^&va2#`|w<M
zlj@mY=pu~p@TD%rWCpvhbUZB?dv#N`0ra)*q5(2*bUOwD?XB+UUl8rnoqP=ace+pM
z>U7dS4uglz`k8~lx#**4x8bU<P=RyP|KkKbcl{}fK<v?1Q-!$)3NO*PSMN(j8lL+8
zl(6;EZ+uMaPj9_DCBc03gRZ01S3j1LoPPTL^f33=pNWRZKD`SaUfHiNqQFgne$R4<
z9MA_`LEl0BgIHh(>T9UD<dA*^c^ITWPXWzf{iHEa2+{8v1@*)F-D#M^Q2h!!3@}XJ
z`ym})4A(C*0PTo=DqVpQ`j|)1h|~|b24|x5{V6>ktzVQ0#TfmXGvH$Nj+Fn2(^q{D
z?x@~}0vX5jvZ>(W^)dGFDMA1B8i*w74e<a=($A=d!Q=W~dJZM)4IAKZiaw&7%0W~0
zO+$d4rhon`WYYDYSi*}8{oE#?ozPn@Mqj4hgYJ4K^?r+?pQR6$LnK@OU^^Of^bu9y
za`ij~81wXdT`}wV`f-<`cS;{d*KvV<%vKmYt=~a)f`xjw<M6OZzlLVbbVgqi3`=MA
zn<9Z$tWQY=cR{~{%Fi$9+rEau5`F1hxOQ1TArFdI^b?CPv{L<dR5@@}pFo#onO;LF
zymI}Z?GU-9FA0Qtg?=$z>y`TXuVJZ5zsLoB)p{q2k<{o-li+WyNgqu?k~;lhDl)jP
zU)F=x8~T%Uf}mc%${&Mi(0?%jA~*HA8E9<MTTn2lS>Hg3^%lKxI=EK-{w!eM(hqV6
z%5D7@7chu6y+4(Bx9fdB0_GjPfkI(-^>5!n;hz4xYDjkIO>ZcT)T#exDD=DZaht*2
z*Oz60JkU2Rf?~HmfY#Ix^;_uh^dtQp+VnrspI?N=9{nR)06x_(qJqh1`a-(cp6l<Z
zVd;h5zZCwy)VosUz$^VPv_0w7_c?)kt*;G&`8WE9rZTW^_1kHg)TiG_6{qj?vA9u6
zoeV3w(dcX__#DK=klq5~YDixKFWd|ZF9F-#(368n*khPG76v^GOg=>R8kDpa_cR22
z0TeI8DsMD;8_e!uE_@6FD1GZ|7_ESUpJ8<w#b5jlJ$0DpeFjY)6!#nQJJA?mNNt10
z0mI2p;Nd~TPFltW8YWXl?~vhoA4Gx-VUuAZ*icajXF?1U=-9|%!)5w6455a151}4r
zsGy52+#s6-3r7soD5Dl(D1Htu(r`DFDv_cLFTV#HZFoHr=3@-or-6$#{7of<afVSe
zrlW>LDbS7?PE+xHykRrF*f_zEG#Xr@A)*W<$xuhDo#O_te=xLULmj=RD#h@<6n&`%
zH@X7T42wd5l5Y4l79_(^i>)-?*KOD}7Vc*n_KZgBNyFap;Ia%lN*81sZpMJ*7^ceM
zQ?4OsH=M~coIZdN<{P$U0sE9;WhCqt7$#9n=(OQ04MtdKC~!byk>PJz!=EwKUjX!3
zLsKXw@0{T>#gfh&#D74778RiqiKpe_C4++phFoHJ?<kC2Hth3-=_`iGxv*Jk@SX|o
zs$uXhh?E(Yr2xL%AkaSPnqjjo6e<iqgu{bM!}Wh)tjgd@@587zxb%aS8iVpzsMi`8
zXGqo=LZ+bax*>`x&u<t^CMt=pH%z+%nFfQyIB<=IXOs-QX;4{UJWYmQDZJWjcw`I3
z7DL&$;93pA!ytLfu)7P5w+)*=hNEqU=7BKZZfK?VEj%`O=E0{YhG+`x_ZZew3h1ff
z^jeT-hFMdf@Z2zJ5?zEZ3|d-dzBCM=P2VfSjaqQMhIp!xe{HCtO3pWiU#KMKts$Sb
zVtoe32*4!UT&3_?ip|zsh@{z!{0M`{u+ekqJ7M$X0eF#V<C%xXlQt7P(U@gZMw`7H
zn~E5?ooDk;0tF%RZT4(|Oo2@;rGQS`Y@#G)q0Le=`WS6Ky9qDO*xcFxw6iw-UxS>p
z$)=pqd7H6R&{S-5V>Hw++BDG`<C2YS3Y;miSucmk6`Rwep-^fwkIs5rwHaiO#xk3|
zR2NZh(}u9QNqWuZ+BnQmg-u8nIxB68DZE-`^K=T#SK9<pPO-*j(K&FnHf#0pyUu0}
zB}uN^d_Yz3H*D6^Hm%-f7R8zxYzEQHHrhO=^y*C;#TH05*}R~|d9zK)&uDD1`B?*>
z+HKZ(!%@>cn_;v_@366_Y*43-kPGu&HsdMIf8VBxzF!Y)0x1yNZByn8jfXa-g^+w~
zv)B%3Pi&S^K&Qv%=@^iwHa^eL_{?T$21K6Q%zp)cU)XGypz)=RzYBf5Hb2~lGrcy8
zli|f{lTE!3*f%y)F2TfGn;I&C=(9<(M&mo1nhAh$GJZwHXwJsbM)bKDH_<s+SEJ=D
zpt%``uZB<V#vzX(vd1`ZBS1ZjrIXON*Vq*VNl#;zHOAs)EUthBZ{w_eX!J4mr~H|(
z@yAm$K>dszLD2U%M%O}dpK;9J01Ys1rsBr~Mt6F<#zEr@79`M^M8#Q$jLA1~u>={<
zdO{@FIGo}mA;uj+BhKTT&-%rX3^%T%0N)Ygw<CcWVQjaB7m>yadU8h@`()svjbGOR
zEY=tti3y4`{_zV2c+}WM`L$!loH>|-c;gugIwl%Z??UgmvHUpPO*SS`eNL+J^OYcJ
z#uCa}r5jgd!fb}|iiy4)CyeiC$DL{PDTj$H<4c;LY~wXb66Y9?(pNjzXtxJm<Qb2y
z0BFAPtRDt(%INkvU<!<D4}v>woG}RMg~rfIG!_|q>2UuUqd@uRvqsf4fSohC9E79i
zjeiECvDjFzrH$1EV>(?47mY<!1#`)myc#ei#y=>$a>cme4M?f+9Oc)p8Y@}2R%Yy?
zfM&VTkwVnhj3cQStiothgT`K?Ukt!JYz2zQd)hvwNT!!9<AlB-+b-G@9JU>M173vN
zcCMtvTBNOUF!W<=+rNTnyzO|JwglVvD<PU_TS%LjB-;!0fH-bD<6np*+rFLxFH&q(
z^mI+NeNLg5G~0~RKuNbPb-{FH*j9ZB$rHA7|AgI4+X+-XcG7m>aA0QJiu0hCV=Em`
z8>_RnN9knHIol2@4k@=a{0Fpawh0Xot+0K*0(L8HhkpZ+D%%yy;7qmc^Jy4bjje{l
zxwW?E=?Pe8%f&<ey6vT9(7Rz<TLfq7ZI=;BgKgm^U^d#$9s<3awl%k)*JOJm3XP^_
zTg3n<w%AUe1gBbUT{F;m%XUf?+;6j;WC`qc+u8X*bG7SeL!+DBDtgqr+jVY&-X6Ox
zTLBtoH|_`Mh1;1Q19!ykTiOLg*qKqvFw$<)C~#4BXWoZ;jNJ&@4aeFor{ktaO?Kr)
zfJwD0H^4-iUHxN>H{I?XWgs)`hVI7abi(dGiaKQ4F?6orq}}h+;b@lKP9In*w5y^m
zLXq7tSM;5+i#LK?v2!j2SgGCHc_3HqX46}T%Iv<P)c7^Kvy@n?w0n;>kX3f3<2rcL
zWOt9g>CJXgv?*_~v!XOXt6kV)Sh{V;F9uAT9X36<YuPnZ!u+{i+C)gcuxqHnm|oiL
zUXRb`mEC^2AHTM9r)&L<-LLe(dTW=h0M}<X?|)_M_OWyab+(V73Qre%m1!E>aJ66L
z32Zm}wg|Mk+v}S!`aSkTm%`z__R2-*^R(Z39mLDN))9m8whwp@Zu{6TyAB0k`xlf3
z^|QbB6*zzU1+;kEZ|@%j^#J?$O!OVFFIWe=2kl?dRUK%Ld<||)_Vb2Pb#IXURSIea
z+xK6E&cpV36bBBqA3YNq;r1cX=sRM6X(V8d+Hc*0zGL?Jv<y$MKSmcsqCH~=a@_tk
zRk5Vl|4IAbRQvps5J|JQqt!yX{p#OfFvI?(3YaJCv*|97Y5z8xHdZI?*M5!8Ec>Kf
zkZk*&WkAcZx7dJ5$hBW%jmCU?)OX{)VSj^e&&Bq?Qr-Cl`w#5k{Y85(x>;Yc-$<_!
zD6zMr>*BI~hXjqK_Wp~3a@BrZIQq)$<4>cn*8Zo9aJ0@o><}&Nn(a4Ikw%OC1uCCz
zwSPSUe&4b`aT9ZK+kQJmh1=|hwL-t$UiA$c@7VAE12A{(e?JEE_v|y(Q17sh`vHxe
z_G771q02txIwbGgH#oqHef?t|vKR$^hLrscBOjVm%Jkz+2kAxJuFPoqdblwm@gVNZ
zSGDxvGcHs$>%r9T2Dg{F8w_Pn#)}>@UQ8l=2;NM~EJ;6EDC0~E_>;`w2zZ*sWYSJQ
zn_(yol*6o{izb&j76dMjaiwyseCFGKAaaU1ask9tz#QoV+G%Fce0W^Q{7CorA||o`
z8fTa+I=g?Caqt9pju}CTz4J^9J@2nD?Q8n=lig)r)7{#QecS|fclJN3q20r_(1{HX
zcI$so*vtN#3C@!>QAwQ_`yM?WyxBDlX!J3$@!vwjm))KMQ9o9<5ZL}~fjP#skA28v
zy!%;>juHg0Peo-vSp=&`vO`wQCS#8++ryou`S#{cAQdj#&wcP6un%#|DH9ROJ+@E+
z8$Vx#l;HQc%M}2h(C!17uT$dyJ+aYr0?_lOQlZO|tF7>F-5@GW+%b4LL>+fhz<w{&
zd;w$gW-5k)%VvgFViwObqw#*5|A7k;cIfWovOj>)cU+Df4mn9Y!)OGOwdO$HF9~x5
z7bP#Cvog{0c1lXb$X9Qm>bh9@GzzS>s5>hlb60(gj)ZipfBq82o~hrv1kpF@yJNt)
zTIEpO$jfRP)tBwJ@}Zzzu+^!Z;3BMcuY%-JEBS1o9J8{24_?GuU83xCf>j>{y%Vh#
z(ZV*#O12h5KW?>&!qlc@s~vP`FvTi^s+Uu(`uSsaGOY%$glN81o(srXtNQPNR$_IP
zLVwq+HvSC#8&(%z0JPppp9Gi&tLep%Y_#(45A!#zMlS*Bw)!^~jSsCpqeBmmtp1}@
zagVL~QCj+m)y`zt>oHk<PhpLxRtr9Z-Dg&l2LSuIm7FI2g_S)G?UhwwFwFN_9i{T{
z*H#m$Ozn-;%pYL>t<`Q?5cgTVX@kN$E5!g{J6T)PLf+YWJe4%NSTlRUd03DC0w{Z}
z2krvrX)U-w&&%5M`UzmXt*7+^yWe_A2S|YRij^4X0qZ}hxaFXAP6F%(TKhHuE!KKJ
zz1uh5+Jm0&iPr7qP)N5{yn^{m>o>n+g!$HgbV0JwT0RneH?7kNv)THSaF7=3!e2pd
zTTiFgTeevbHPKG#mGz-cTsux0PaXz+G%>WE_tog@KteRXQsN>~!;gdC$26-YXiU)*
zcR>H7=H_NtI;F{;1)t7otX!dfS+muEz6#AX${k<VyzmCstl36k#XFjYG>AOV{I&#U
zpK7jp(GkDbntx+xqWJeOgLv|DDf#5ZH@iW@o3EyDj1Rw=YE683TdMT+<7d$0%b#~x
ziec~LS6l<PpMMqykpTWgGn_fV|1kn?ALKO+=nLdq21D-<U;jP8g7}4(p%=_om(a_t
zWBE<=ZI9#U6hY%Czk^C%j`5wXn9F$nPYNL<@VA=*lgL-Dh5JeTD-9Zt^D=rHTQZ+V
zE0+}hZwg1I@<+ljv@|}A!bj=+CfZ<U@cC~+PVj%df)^+GMFEh^;^)-U_b;3OnEusK
z4!@gH(7F7450E_GoSv-t{9f9UpW<t1pauNRuQ9aK{At=l7V-(Jp;yEwy${JV{Llk1
zah6|q1&!x;>BrDJ&p+9RDY?eqJc1$B@%#P(bQ51h6=Usu{Cn`wbf5R3qNyIfaS2*q
z^IuH`_8WeEHALU?L%x81A8#r^-#gxsHpEWC33}s&k1*Q|BEG^53O)D<-Je6mU)Y-r
z(0#&$_t3XrSW7p&1H$q(@adqi+y`KR!jSKven{Z{m$EhqSnuJp5K3A=qJ-U43=}O4
zi3ArTxb^`pRv7gi8smh8b$~f4G={*7W5W1OaPh*4K1e1Ce;)ytB$Ow>?s4JyXPBpC
z;m2s0PZ9VPn3+^T(E-Uc;prBTbRnOD&v}B$fs$7FLRSm)PYba&Xe|^b5xFc>{s@>W
zg0=$YuL{!fP%IN1s8FF!81xFmzAk9UnR;P)JnS|ILL$K0guMoUwF^V{gS#WRG=SU{
zMm&JXJ>lE|45>rdNfC}t;kM}lXcx+8K<*3d4JbYk>^4E8TliB3OAm#+W8lRj!6_Qt
zW8sT7*nJ|b{|_)dLI*{pp9#<ALgBgau^OMj3*pRoa4!YBpFv&;KJViL?G;Afhoi5B
zMRdP-Bdntmo43M*^Azsx6P8oC(>q}+Es&kWbH6~*Sv(s785i+ys*!gUAJV1kChk6s
zK3~zxh(<s0lQ+=w7mc})+$RqB8(;zA+oklOBgGHb4vLTa!_h!7kanrj;#U;)iV>&M
z5-V2hK5K^WU!2%{AEHM^T_8Y@iDRgYEne(TpJ;;kS1lA1#rg4YKS}J`hrZ*YDjp<R
z{H6lVq=<?(xRxr8rOj@d*hqKqbn(v!h@23UhXFHF9CioXNil_<vsvP!BjB>dl{+Y=
zkt0Sffnu&Wg&vN1Vmk#e^F@bJO!q1ArY#x^#CZ|$;<PxD3P}pZEA)vLiHE;~hi62O
z;b=T7cG*LrT+F8w#WivGpXjR;^Aey}CCcgUQ!5S<AyOyK=>_*d42r~bnYzV~hk(8o
z)lTSqBW|jP`M2U`Ixy2Gdi;dOcj8PZXgF#0)^OBWdxrJ{F4~Fhu<NSrrEs&GHq`+J
z-L*3)9=J!#&PAVx_U8`(wpVNRAy7QEKf6QSOWPg>&PQ8Lljm#FZjhnXPrGIT6#cdO
z*}&eXb@&*a`?XWg0y{u!R)@X=+C(`T4{G1;#FzrLztNigkoM~X;DWR(odFuGbuEH=
zh;}+whDfgO-U;YX?Uz*b5U=$LL1TheJ_(J9THPXWNm^6YKln(FYe#GVcCwZo0sU01
zDhGDcwC_K~n9{Wu{)K*qc5ErUIHA2y1*e(X0IJ-K9QOMhj4)%^m0fV=#4z^~pzIyq
zG8ZPUf0|?l6Rn?aF9OQjk^U6C>>KG6hsJ<WakRGy9yQBE_p6XmFVw&e9p#${w9HY#
z%`ks{)MTpTEFSgkEQpkj`hmXbcSmifC3yUoZ_3Q!DSmz*N0;Qr@LNFN6#5~4|8Y+N
zFE)F$<M)n8TCDB7;s<z#q1T}5#3X(WSZBt!9-NDbSr`ckFQ)80z<4vBCGfzPiJ{eK
zAoH4zW*lOI=q(#Z7=iBM5zM{kG;-!JRUE}LQi}2=FnLt>l*k-ffvHMju8#ud3FZ?z
zZJx>W(WP;US+EjZ0b@;H^3#l}8hV9{$#Ndp66Vcd$XsUZY5{tM8QTaGrOf=(=&NN0
z4+UBsGmm1G*O|fee7eEZd7-hD(NhBF7W04-IJcQ=XQAH4WPXYfwlhVpz`Vn}rTpAo
zrn(h<_n6JSu-n1Z9Yx<`MsK2nB~O^<gV66`Hc;T_DWgk={xfE*2Habw<|}CQF@_&7
zLGPG`qwvCsolcKsXLc}ED!Q<tv{G?pzo!yIH`bd_+}U4gv$co)WhNv&*d3t|*~|Vi
z573@$1C_3MvE!m?|LM&}PKKxtdyt+9zU+w(IPAxk4FmCKe?I`SkFB6P-hNg`jREZU
zv|>2Gx@v%SkY(Qkb|BlrLgWzp7u5;`v1`_&FPMEa7ZyU;nu&1qFnin@BB89WKYR*f
zznwv+Yr@$+3O^lT+lNB&D2v+yZi8&#DKw_CP9Ydf8hbVY8tJUhBZy?MBAsQ-V|TWr
zF`sR{OP?=$X(F%-*ss>Y?rGMWY9lVNWy{fbk^S2Xl9$+zDA-WK^4p+(nLRv<?tfR<
zPq#y(lyy1|><0GeJt#J^!+r;MleJ$2#U^&g6ezZ`j-60!W0NO9p`HEA3q!lZ4jzFk
z;V%2_Z2ElJ%CYdigYEhY3Z3kCmgwtZ$CRVbiQBmo3Le}h9wL66y&Wv94dm8*i`Fo%
zsuy-+xI3$0B8jvA2#v?N-WZT%ZskCDk-`PhrZScDr!-+2*L4=-J;k**!9)QU@)8D5
zb7Kd<wL;GGIz)=N#s3Qdaz2M{AkrC`4fzY43cGH+#$wR#z`Dc@yaD-Y?noJ|HgLb$
zL+ut<<%hlwF6D1DKH{P-Lg58BPzF1F+|LW3utze{8{T?IetU<$y%Np0;5;Q27h%Cm
z@&WD3y(MP1F=!vjo~hu1C0k9;;9!WPiEb2!C2Jo7CR9?l7$i&*9SXbQlAs?TaztYK
z6^fCPH*`mclDt=ru}4d;QR#Dx<j!M|SjpD^&=)7!rot2+mE>-PUWTMX4S#bbeN=x_
zBzZakK3$Xy2!nc=#OFOqVb@5W(e>LXIfZ+d^tNQ`OEh*#3}%qIFBx0|jR%r1?t<%<
z45nSyL&;RCPJ1MI`wn&=OFrBJg(s4PAEDkSN&FFBypz<tgrt*neK16vrFm41>Vh{?
z!!=iFQ7jbPq&wCqaHYFThtSy%5B!5nbnca&rze=F)IJJmUI@T|cuP0X-P1>^p#_ew
zbP>g5{G?;35-dpig$qQ2r9aY%nGk7KI8Y8tJMX~XP-%-7O{MfIm7Il3htc9CLOR+4
zl95vF@BR9{CykQYnlQp>>2(TK#Nf5La3)szDV-gTlja7EXuwsndK|cPsXGV#4Czox
zVV}T%1psKKH1s(1PD=IR@Gx6iK-;SvsReBubERh}gOn#7(gJ_;rH`gyE>20k_5iFv
zx^op8Pvbu!0p+4J;su<zBz;Qd<0aAtimG3hZgK^=BAshm23m?2;=}G$Y07oTlu3;%
z@u8JV*HPlJLYh|xv`XpH_hF(++Ej=^R7*!aLSv0|VLrH8>9{PY*GZRB;{UpIFr`v%
zNPk-g=sQw|GAehaYlZ{tp0u<Bk{!}J*%(Ww^uoU;baqJ}D1iMy8u=acyQQD)gXlwP
z{4vNpk|u?s@v(H`RY*ROhNr;pJL#7H(C8%7xWG|oS^qOocaaVB2DYp0(ckEElVyJi
zb$404A6)^m`F4=pD-*i`?J3*z4LC1ZbOjaqdCT%X1E`NI_Yc7M%4X8u_ONU$2bfTq
zZ#K9vnGY=)!(}e?#XBO)qx?#Q>;t;lMaur6#ATFhwkJG{kp<-gJ65)`4<A#U%x5#q
zAC(QIx6mAu9i%K=yv)#nX-<%R<wN_iL|H%%WX{T>rbFYLY!}@KOJzS6!u=-Mv`#cO
z%Uo%_@mBVX9zXH&rBOgTFQ2;xXvOjqerRlzzoPI)v)tbc>YeggHgN5+d`vd<Udj_P
z0rpD1hT=+|X0ywn;AOUr^4X??X5S>ie1zEyioB(p{rMJ?aLTMA7k1B^{i{P`qghcI
zM)=swJp`a0ilIx;cTizNXQQGO-^<`dn&J?J%ug!L2oNbzR1ZeuWkvUJ=y@xrsL<%A
zTu5Pjf8|3K+&-m9JJkT3w*LsN2b3I@HwP+n=+Zl+-1HoNA6Dkll!hut*?@#8N8W+R
z5v9igco?BvXbXce$_;eyj8%3Upckk7j21re%7sd(Cn=w=Mqi3jQ3dsM<v~yQdqTNx
z9{Mts)l|Ndr8I3i1aGpH2dJnZNBI$juyd8k^rgO{{LKh*RatlqlW<MhPIs*;Wm^VJ
z)F`9ql@fKzL=(KYp`1AlXpPGKbdk0y!yZ7y#r)+c`0HkV@*=oB<`uuf?q2f(D);p>
z-}@IN_nEIZrGOqZUp5^2hs+BeVopNL1L$!ZW`5)$E%@*we(H$d^WrHpH2=$4_`P5m
z9X4LrKt-jCexU%<Voxe%U6M5%e=kjsM*A|iT!1eBHwYG1sFuL&%Cm3b(JB)qCx7J)
z_`TYs83MI6)@c~&T1RvIUe`uhzwII0G1?uwKf&KSFZ%<+VbUJ_?WmXx(0}@9IrZ<5
z5%~K*D@vuCX48B+Gv82<%!T=tYUN#-Q+g=+G7eM&;KyvC`@KJNnF?g~G4IhKh7c1o
z`cudpX1<&abi96KEk>HkJl_tlvYC|>Z!cu(&R|d%8FM8X%bAA#w1cN<IWq*mBiPAQ
zvKGm96ag@beMfQlXg2o%jK#3yYv5=+d+b{@Ca}jlfS1B{(^@o@y^azB6#B7dR3CYg
zoz@SXS*&gnNH%-P6(om!Zv*rT*e`scahhHH5lj@a(G*KN&ko%T^Tli}6;EAYFO)#?
z3j3oI?3S{=R6th2s_F8mWDgg@^D0(LtD<Vw24Pz14R-1`;C`rQ$M}J5VEd@NvW0#B
zEl4YS;XQm5x7c(FtK4Qi{<qF$`xnD*2OB`K&QA6eRZBi(zbiuHQ`R-exfPF-z=5#j
z#3?tUuSXH&jfs1v?DvGyANc8GrqfOJ9pgsx;lv)IgNe@U-%fDdh5hV(=(@7wPXOMH
zeMzN;?ra_vPVHg8rbw&@TSXhvz3h70IeW6Xk<jyE`zY1o%{JE3bo#J^zJpO;_Q3`i
z^ka8Dg1$d{$p$hZ?1je|>tXiE3G{`st$FA>#xA}CO9^ahh4TM-DZ0?scK(>TkX<m9
zzOD<`Q~lwhn^dE;cqL&h*=T|bOD%5!VOd-kT9%(ep_oa!;z1tJR#rMfVb$5e7~ikQ
zC=<1M@>PJY38ResTFE&m{1%vizt=T>28az|PSD!C=vx@u`aPwncP^%9p~JqxXm?{q
z&?y9W#%~|m_AtACqA@Z3zkxgZn8&3M-_Ing;E*YRc|*(0P{vY<SqNjM-@+7yGiM9o
zLIe}F8I92lPiEqnWHm@UGno!iBr)@7Ii13|CBafT(?vd9W2z!CfC^?%IV@E&Td01y
zin+W2+;ygU0@QCZskBYH#f+fqz0<^GvFLop;N3Nd!Y~&aAoG^#r82H}O#kt~c4j9I
z0!#!u-W!cs>~Q2P{@>TBlj_29ndHx*lgIq~JKV}=-t_|S6f?(wz5-?p)eD|x?np4I
zLZ<!*fQp#cJ>W{1Kdk6+c9}VU0s2>%2)Z~*84ZOluQJ}$SjGf8gOoEnsD9)c(@n+4
zx0wqRaB5@D%mmlY*mq(e-OPU!gL}xF{Tk+9G7)rpf5p^Nu)>AS&xRMSY!fZd-Pl=l
zCd8MWOEthIKemGMI{vKY97KcJ#zP<>tk-x<?qT+iT96p_6~+8x*^#unh-0g$BI_u-
z;(t*)_VHl!rLjGqLob)zd=t*(vFoy7DW6R|4fRuOHSGtA*(@sQy};f%426sA9f~<#
zGO;~mu!5bv8rYTW+Wyd}Vz1LZu9}Uby~<6tAHD0Wi8aKbubEAuE478){04okY%^_c
zI$30QX&=K;GX6eWPZ6I7Y~jx!-RvydO+94i4uJY2R&o&&^q9@3>ZT{GX*OlPdRR-k
z;XGx3p{ku{Y#`0^b9R6OTzkQKx53kw?DX{*+ADS=Etq>*9TnxhW;IkK`iA{xCD7io
zbyULT!wqbO!eQ>4t>}y5`fb8k;<-k0CY`$z2vW=~UxCIO++`DmIUaDa+tBJP`C$`4
z!zE*EU_MpiJ_gPdN#>RTv|KW1D%@|9WNd?Ck7W1XAg?7G)Bf)ka7|iHJKlO}x{So6
zVN?OrBK_|V4E?rreh856NayW<NT)QQ0yewxFX91VdLs4qh3E@u{ZcsHEA9IL+&k%R
zIYixL<zMx~!0;oal>>KSzb@b{o>Gs_r7IMGSzb;H>6I~AklAqmcMSOVXaT>s-E;=r
z_O5FDy(2~d=FTl+pyk9gpTKaOnRvP#c`~MUDu4E3vit!Mz^vE;`~%FjGiVHDZnuC7
zV_KJ?FP51=iH$g>hn~5~%&ec_Jzn-Z7?P<>WexhW8M8-lCWpEC6R>lcsRyB+$N0R3
zdOmZd2MVVcCvW&tz%W@rIn9hRIY6e6@$aLlX3iIboMBebI^Zm`o3h8}n4jhY`#clz
z4fKl{Z(7S;V1A$+<wa)JdWc+NzC8%g5=Qe4$YrLdAIKG^-Vr8BnZlizf~(9+O3;=u
z3n(^M&fKE~_%$Z<20iX7n13w6Rx*?8;7mQ!9e}B8VCK`&qDH1%3rjbd>9j6xVw7$0
zqM2C~2a&ssr#-OmF(0mmNCz_~0P3BLkpg~Q%%n|#zR$d*)0GdHK^(YlW+2@G(%3c2
z0hY!7F^0msIqWg2QOIK-(F=)AvB&m9w21AcP02YnXe9=7f&H?XM#%0fgJLObO)-yh
zwwBhHRjg?>6zbVBN-o`I?cCv-6E|(00<HKFqiC#Qtp7HUa5gs=sz=yA2`GY<nu;JD
z$yQH-=_uCt4;+bR6&}!wVY4n_tg&qAJ6MTh{qeNJU5A+hE63Qlb<m4vM_q$L0&7P%
z;zYKK7UoH8kQ|c7*%=gfNM`GfLo$UuL+ig(b`-@C(^z*uaOv#p?Iv_)u*+!koXwU}
zp0$W=4hPH`b}~hAOV|aD=)26;)xeo6?3iYVl(G*dVUBCquQtJaEqj>izU$bC6mZws
z$CMv#VP)T9psj2%mHyviuTp&GHamtQeQhjHQTBFr-Y6<By2IMw06hXU3$DPad+hy%
zaIu4}-UygZ_C7^_yVzhl#C)HfOgHHV?2BQL>}G$Vvs@3^yD=ay*jcomeaS{8z~5Kw
zwga%#%MPc2$!pfW2aRu7+hRz*WnYd5>0`A4GCY6waPQk<zC5@u>6H-v+};)_?&B&K
zVuZomOda$?I9&_4C~h2uYofXIRZvLe0>j`_5_gbR$|pE0tTLsUoS_|(r?`H5K?=AZ
zDbiQWU9QDgE^xmN1N24i;2}s}<17pyrV8#`3OZGC=H+mzifdf~(Q2-z8l5%VMmk$n
z%cbmx-8$|IdOO5*ZuSw78{E(TLZqJa{~pdXa4#wR*T^;B1G&ldd4M!=gK4?e%zZ%*
z^%l-E2Vkw-BKoekajPg%*>2+8X%~5i`?Cn<?{dXoW4xVQF)fg~xRzdU_qk$v{ygB8
z#6hu}bM63n%uSsS@`U?wIk0=UQBjb5%UyKEu$?4_smj$^qU=SVi{u80xJrg>MW35w
z1VvljB?BnCy;ow=o5PZ)<nVM%jgO@GE}Zd|L{UAipJY8<f&P-AROPo%a{Mp!B}n#A
zjrIx2uzV<-l03_U<ax;os_iP3q@<y-OS090K40l?ci{!L@U{@~k-h7Nx}R)u0YnbT
z{=Et4!?HJ~G_;1w9=L)Hlil407sF+1lR%EhdhY-<QZ|r>!_l&nU&GN@*+~^ZkIKd~
z<cuuY6^)6qkJJE7lHH3&-*H(+3-pp@nddR=RGI7yNSe(0CP=z07q5)?e-9Lol@MNN
zGN(P-qP22ZTx?Rp(vswb@P6q!Itjfj_d5tJPo0L}zll`&wXThBJ?jT;!QUHn?U4C<
z?MTRPb*37NZB19uyS?oYe(#vt21`4`Xk`Da>w~--Bh}N~GrqJ0@MW$omE-#NV<svA
z<IjlEAp4kAx8VJL=GiM;Iw4F8Jx32SMf431WfsyMDU5NX_o{|7ZzyM##tbWfwQR=V
ziWw<jZqo|-95ZPPND0$R8?JKZ=!cl58fMZ-_}IWqoeJ(2GoT&Ln7Wv^?Pz_@q{;y5
z#Qymi4DM&YnFq8ecI4jwzlLOvEgJSQwobs^&&>S<x*?2JBUBGF+6izulqvZfB#gQJ
zC2YnrL7zb~j)|nlPckzx0G_8Xzr{l#mHC3!gK5n1l@#>LVFuE9?_6d+)okT4o>VG*
zj#)!F&ht#zeT=S@`JSE_R~fYp8fzIpimcT!HDiI+%p6Vv*TM|g3=^$P0TmG3Vs24X
zKZy;sg2-_;_#RyntoKBWJcV6V0?AZ%EcPX|o&1&F1(nX`%Rn;NdsNbQg?*a{jb?Vw
z2QV1HrH%)Q<m7A77sdIO!9+CI&cSXBH+v{1E|wcWhdbgp(_rWw<>t_pe2km$7ewN@
z8DlWO1kRG~_KDnx_u-nq<i8>4GwqXbv`O4AIY7_Z0LgD#G0+2&kG!FOP;xgFJ_Sm~
z(JlFqWDzYIg7ED|W3WU?DaR0r+g&IemITa!-B8IRT4lJ)rcu3Jk}UTx*iDg{bl^_N
z;%SARCHvG83OTai*BHbpldLHnGN)yOXp2-N+qDg%XJ!6W{f`&g9)hTkyeSUmkIUV4
zXuK$Q%>j2=&TNMlHFEvf|62ieu+M3G^nm>#1AaYbS5W@@8SA|d4!vTtD6r(g>1#Py
z!;f&DDpV&|n-VZ3GnQz<%w)=7dsYLbAbyP60PUaL6EP>VB@`c=b5RHMpB>_$yd;~B
zNG!E@j^E2RQrd3$pLg*0irLXHwo>;U99YHu1g+mwKf&J{C6un;I(Y&7-!>-#GP?)R
z8uVYoR}}PiXFNsp?_uK3qsxPtREx&FOr95rC-eP0XdP#c&|3&Hnd_7@%44=uR;!5F
zKM8#om|sKCSjzC`AeD?wE?mFPoS6uJo0x(IaP3U09Nc~8qpva0XUu~0(0j`~wxECe
z;mYp%5Q?5`_VWK*vIrA4!1wQ^JZ54_IqfgEOUy9t7fdfz>%L?*eF&J>OyO97zG0Rn
zLH!-042Dlm?AO!K=*s@gL(+|{DF%`U+x-u`*vl@x36TTrv19-rWF6)7-i~B8@>j40
z?4?`(x7IFaO9IhyosIAT#trtH79iHMyDcyu2z$&22GT#2!n?zso&d?aY}-fRI@!dl
z@T-e8{jWTMEu+ozLw3;{xbTYIH3K8)W&8HRSubw-OAtR!^8eLxCC*J$VSM*(vOwB|
zMY$|j0fhp#*`#gK3KnV`XlPoX2eiOg(lpd)n#3j*Ii!OW7(rCZ@eRjF(NVbu!9gNY
zC~`S4V72XxQo*a(0j-W4EurA?dma1}*v!kf-|v0b+w8u5``)*y{tUKjr3C>ra+9R5
zfs4(Ob>hQLdcX}Es&9)H{>K@2kl2RmPI1X=@YyA{z5}~=#f~(Ph<M2ga3xcnJ<aao
zC+C~&gJhUp&wQ8RdNX_CIMlbWWd7tt>?@vmxU-r?^EJ>q7F7Xu7dy!h)O)Pu21NI=
z;a0fc$F`}^*v|%RL(GTS(r$SAlm*+s9cMrAd&UX&%UyUn$Fe(N<x3`1;TSctvHybm
znhoKLFs-bKr+$6UV)$F)SJ?Lp0bXU*n<hf>2j=7N@Bhe_<w5Z$=I0CAKeN5faQ_RF
z_?h3vuJCocTkM$<xWCO#^MUIf*31VXo$Ts1=ykE$fdC`yPah<^*~hP-W%t?p!=b)X
zn$ELRYNW^rh}22Nd`4}bw5yt@r8P*~d0PLs(oFupA3sWG+adFZl*FI$Iwj96)cq|z
zejbvmG=@4@Bh5SMaIsHQW(Rjdv!0LZ8Z~M=!fw-K?}FrA&H8>YwoY5cJFU&yrfcA~
zYj3YdOz&wkcvdm)1tEU@?U0N3tjW8wj<2cglneP}eVyFD8%Ji3eBBOkpRD8a<NM_S
zyze_8U*{deA-TK-+!6WrB193E)lw)Nm80K46vyPZ2ScG=9z7nRose7F;qau~iw}dp
zkOvu{ep)`#pT9D5Mh^9Z;#v7szCd|ie!3nSm*lN>#Ql|AG!MZv%C6<mZ<d$uc-Y%b
z+rS6uSq=Qr+&(`JGSf$Dp`M*I3y34aW5|i;7jUj-8&qfH|AE?>^DaVb*0}?SH}C2{
za8RAUyAy3M*v-Q%Oq>8iv(r|iRdc>;!hVr%6-0{<G{MB&TYP*!FRL7;=P&pbwa<Uj
z4<<@3XyInT!5cuFZ>+|5>Gj2sbY=4wv&xoTg9W$9=ZqE__&A_EP>1~&&SV4kR9kfr
zeX%PE%u6F`QSE(dJ7TPuR}0)1+6=^hXe!(U9BnvCFQ2-KP%1ax#C~u}9PmY5JOyQG
zj1~9_@jg%9KtieoHcpC|5)g!A=+z|QAa<E}-=G&nY=BY3gamr2OB|JAOb-OS9+xxZ
z@%w_t{DPcBb4FFE+n#Ala0UX#48Jer_Jx8*o6GA71l`7fx2oI&N%|`y+F~o5E`QLH
zRANftAG2ysR8vifCX3l(4Eg=uAgK{?&=g3$;PJVINAGLHqi)aKd*YZ!?E}YbV7RDT
z)VI^XV!eS>eY8w-0{SuG*MDLkHiq2?C3ys$iI0j~v%673(V%EiWRzYgy~Dd3`_vpF
z`7ODxK0hy`WTrnD8)r5bjtfs-q4VWY+(9WVe6v~CTpaF*k9ylS)mRvGR|btPXQkI4
zG-mo;RTVwIdfuFZEMqX>bh%4HZfAutBRw}h!&zBYlH)I{^14g%{R=~joRw~4rn|JN
zoJ?jGLk0`N{cByXr@{@vsG(htW#!vSW~Vy}ZLuk8&sMmm)e{|V_2@k^oomx5v~!EL
zH=S+PO`yAbbpyj21N!?*hoqX!@g|F^j*B&!5)u<ku{gWTs?}r`gz!fl`q@#jCReG`
z;w-Z`Rn?keGCS2Ivo*zKb|t$^rDlu8x@K5Jk75W9i}W4)?Dz(L8DIc}^#Ot5o-Uvu
zD@4H9RbU1|IL&E4L5TDY`;wJYy~RyrN>g^S7J-`5lw4BN6b(H&S#gLOdU>)kL-f)Y
zla)nch*GC0GuVC&t(~IevMU;D1r=*(Tsq*x{b@-$;QB#yfzvyKDCRj-KTV$JV55MJ
zg0MS-NtXe%fQmDK*3ceKqUjzdNo3FL5#7qkGP=P@4W-(k_&}w#HYj@Oau0io#!m$s
zqQz6WS&=Sqb_YE%4LZ@}0bv&n^!YTPlc-M?&`nef!X6Bzy;%tG@G$BIg$cVIwFR^l
zgw>Ct-|RpglsX-3$2eL$9c%$z=4^dDjn9T|M?5V76*K94HsBT`#W=uv$>V^j`E=Bw
zOkfRtsNJEAV%L&Lm!pi)>IEirQgV(mT4Yq5ql^`^Xay(zX%8nU^bIFoy2r^R8kwt%
R9UMwlgj(L0J>34^{SQxcD*XTe

delta 126655
zcmY&=cU)A*_x9dxw{7pl8jZd85_?UoQDceS#BO4bE$Sjlv49j26huHk!2&8)Kok`f
z8v=sT1x2a~ioLwg!SC;n*H3b1=bZCA=gi!@b7#)X;utuvFmRw}V`kyWACJoA1J-R~
zPN&K@OYMTFki5RfNK}&l|DTLehPD<Ziv9n|B+@pvzR=1T?wO63$fSx%|H@FX3r=zp
znOyPwBPUT9yjY2JtiwFAle1krOC>T+QE>(a9IJoGO0;stqNS@zH%<ZbM4Kp)*^Hf9
zz+N$_ijl}Vn*P9N-5y-@bUB0n4O?(QY~o9wH*9O>g-;`{v6dUnN#v8I`e5kfOuo+;
z&f%AdD|v~0>UWurnLeG7$ftd;nV8ZFnM6MQd(Fno>LN<yGo*Dc>NEdLhULufy2eb)
z7CzD355qUtf_Tn%VMj*N3GhF^*Sa#xepg83e|@j@WL6Q`-0x(4nA8lVL_Y7kZU8ga
zN5|LutM(WITlih}8<TogDv>YxUi+PqD$$U|-)mDCSK?aooohN1Pz&7O-*vN@^J>KK
z&-dC~#)~YMO7-FBfQ3wwj|cBy@BITSk+1kJTgT*%M<gr1+dDGrYJpz$y|zuly>Ubn
zR!e0s02k=KDlS}<qQx^(c!|U~Vd(GZ@$d4)G?K6O;&8olgn?Yf$xY?|Q!871A@wqa
zTq3c{uP<dKjQr0gQi)VP)CrG=L{Z*YB2l)LJ%$y_v74C=GTh8(EF)o^85P}P3FFM6
zw&QzEF5!F^C?u>0BjsVq>R2CUIYAn8f`s+`KZwg%nS}Lc9EeTM48`Ni1~5J9_*4=u
z_%Bw%hA`4T(5iL@uoC_*c{2HokV^OhBSjnpmATHnrN}2&nDN86<-FvzKq~s@hX0ws
zu4oj$+Gm2;bkQh0<;+?^sDnTmUuO_Z2IrnjC2NKDq>*~fmAa@H$p)b=6sgy0=`R};
zl8ygYT`n!%!$~&%U-fTkNd_aa|6g^X#MbJmPl0IeGeVF{#tHp0K`-_CTYC8-E1B?r
zR;wjy>JW!%di3=JzOFTJExE=}$ovSOj;aRCz0+e<3#Fs8#wsMT1_DcZnU7Rdn4G36
zC9---g=OM?+{gxs@2YK#{QHLpMx|)H;Vo>MsAarHA^iLU?xISnP|D;!GHq{WqEA1q
zjq&xFtZk%f>w`y7c9`K5jc)lkX_rd5aGx4&cV?PTD_uu>+$?;n>R9D+i2@Ipr0k0V
z*B&|^*Jrs(T-%m1xW*)q!K|rLTo1n$a83D0_KHffS@VUoKc^CQ{RYw={EOt0FpMCQ
z-!EZ!lFUk=>)Hi$ZFi9DJKF!I;@)!-UGSvODg6jAE(;H(#N!Cb-@6dqjwURwTczY+
z^UtKc)RWv_z{8-BTu-3u;=W|RIGh;#PuB(EK$gKTNiumpeJ(yqpI;9m>|m>%V6$cs
zY>5ZCUzkZzcX&%~?q!l`r*CAs`)`sAT0@o(`ci+~zd}9K$c-3kACcvZ+hp_0&m=Jq
zq|c*olgsnV$bNY_@t<!^+U`O0c}sh_9mT@G$f*ATQm{SA{mWrQmw~ZOA=$T)+TFsL
zuF+K_ne!uAX8lVxss|K=QwnKcpCz83+K@!|g0we=&}Z!`>WR!4a`{^U@n0KD&DcJN
zm)I4OJx$4UoQ|$*1IRQxg<`jlA-eV*>GSik)Pi`7Its}@AtZlVMxmI}$UbU5$-nKS
zu)?mB{P9z=acxX)X8ls<tc)aGm(b_uI$~Rx0(-l}$wm>as~|VwfkaX79vRIJBBKGr
zDXhX-1b(%hByAT{TSHt(k{3&sT@DjN<yZ<LJDMcsAr#iqa*|Xop?3cgK%ZOT6`_!P
zN}v#xp~PTseuNzV+L|hVw<V%?Jh{A3*S%eq)8}`;({*GuSz6c7XZN~5Wj3PQswQWV
z$rSqEx9Rh+yA)!Vx@MgGL^fUjAou&U<Yj9-@w9L!%NzEXI(6NHHo~9cnt7kDxfdyv
zU3Fh1{RjH&(TFT_bLew-jA96JH@VRp$nm}XMCZDgv{yS&h#AqOZE}oS@86GHet1Ui
zz3Oh?Cl%TB9A~d{wwo%0X3_OnBQoOr==y_(uAb3kbMPW*=QX3xpBE76nYza|qt0gS
zpXB(p8wK%VCOO-%h9p^y2o<O!$pn$K@75F6dnnze#?^Jtf7>#us6LVD-=*a8K`Z*4
z_>DU4+gu{roKEuQ#bmj-l&;pg&RkGRq~kV|<WMfTY1f6?{nJ;HcezEVM+MY#2|Gx8
zs~IsH6N&SLS|aJMkoZXnoU)5r*6cPZe$6HDA9w0Hwu(OY$D2?gS+<@e4t3q0nnj<7
z`FNPE_Gz!^bH8wMu*69A%eE1xZ4Jp|nh_`SiW-wMjwGH&x+<qraNiv1y2P98ujokL
zJb`@8uDfwRcB95rR#MR0HW5QZ8%b<aNHT2)#XQ{ZN1_cOB$B&R5b88?c^<E3jGnQi
zRj{OedW{?ukELt3;bgP9E{GeK$>rE5WV3iDU56A9^=y%BEc?juWi@^NLrsCMN+L-~
z7JW`TW+$*aW(Nw%qW9$f&K<fY*-0I-nEFG1lRme<O80*G7_!WqKw&X%M0&p-*|^;x
zn<aL#Y4?ug@A^{%9G8&xS`b~CTNK<e3E4DACx+T*b<fb$%j9z8PXu#XOYQ4_n~eH5
zC%{(?xeRtB2mFs@^SlXNg9ebc%P?wdr-_8>IiKV`+7Nd8O5$`MMUsLUbiG$iJYoLy
z`KOhHDxN5(G4#z90#EKqF>e1rpRac&XSR*hg5W&_sGdfhHo88!ELlyTr`7e`f@4Iq
z^=ER~#gQCLtNV7OrO@YsaKf%zMW}!V#OZyE_|JEz>nY4)Foq@`CexZ<=-S~pnRe_>
zbpPa$`vMc0x{V{EWv@scwSle;dy!+0@pZTC6MeougSynQicryYgW<!cge}@noJ=$^
z=uVJ*W-K+;8Iw_rp+_!|<I~=xSo@iXN}rO0PM--D*^@|T%_Tt4N&?hOCHtrWWFH(u
z_P4gu=jN4k&G<@vGv-eUqW3N0N&JIQX_zi5By+zJ=hzv9+V~Gi+A<zKjT|iYYd;Wr
zaNTPod^6#i_aL91adiE*gZTb9M{=jp^!d&TYEG&nG5x%W<eO#_!{m9?%gyV?tR0wW
zDkYzdB)QdtK38buxDHy%;kq7oNGb6?LQ!0^d&*EbeN4dhrjEt6{y1u8OJ52&%aZ_|
zyO4v@x+#W7-ED7LDuw(|7BxBcAq6q-En!tJiPYiyAX-YFf78-+se~*e&BQ!MBun!`
zYK+8Ur`EjrKn~twaif$pDj+~c1v$v<PNvRNDa6C0De93eDA3-0$kM}$dT3J_#w1C%
z9%S?A09`$1Q@?W;$-$Gl*<9BjsJH5GA??$DNdBlZVO`Av&176KV^K=(Jf%<u;~`c`
z#$ZCIl)N8FE>{N<tRKc+^h7#^^{z9uxVY}!-!qJ;FHfVEEv$RQmwQsTyB`)wAyGIy
z`wMMvz7?}=MQhCx^y*;627LZK?;sjF(Vkxo^`xJ-pfWku4bUlbe@Fa(9JV6Dsmtlf
z`zzKFumzpy1+rX8cX(}&uaMgve}H5wvttmv?_!!Iqu9&5q`8D2)Aa>{^k-UJMQtDB
zyAs8I<|*!*B7mux2%iU-#+58afgt91SG4>fqYMK+nE7u29EULL9>O$~sXrUB9%4?>
zn<0#u!b2F&l#noj+3E-vhndmzN;|?_8HpxDGL9X<9mTX72*6RM^*Tg;jEN}$^>OAu
z8l+D!E8_r<W_;ox#7v@nLsU;Pf6?3R6yxR!{Ap&R0A(!G#sl1E7@s2eJ<Dv;LwJr^
zKm+o5roRW+E-<BsQM<?(lHfj$IUWjlJku`{!USd-ji#5FX8s5!k(vDoESH%BH0)eq
z;t#_z$<7o7!u?g|_v0uYFoFnW8uJm)lOmn@cN#i7gNfS%?uX2;@jzrUI};G-W9H2y
zaAz~-Yry3&%&)-ZGDU4rJYjB^!(lPANC%c@jBN)1&zS&vca$>iJE4Confsx@RWWwA
z50JiOR25)*#Y}sTHdQlY=R;V-nBSv#%`_~4-#5&a3((av>jy*lmT5j7fOpK`D%9RH
zKFtv5M<((W9DZW*-k_nMnWGn=`^GGy+q*?7Zw#H2^r$x?+$r_=B)~tG)r#h38b!Kh
z4F_gvR~llM4Ll7`%l&_W+ZB)LkzFYakkpwgn$)(0MF)N<8rbpBK3qH5Fv2K0yETNf
zE|v7`1~Xf*im7}0<@t@#TIJ6)rDh-32O)R-2qb)#0xQZo|36NnmsHDVzv4@{m6=ED
zqHRnDhIFMH(;^Pd+Rprp`IvGCGg$-3PUe>;_;Lm@@iaL-$gIwX$vfuMK!o*$>2n2K
z&eAEfV7Wv3aR_4fmHvGfwSCgJ0jM36dU&7%qNQu+0hcJXSK^zgxGf#@2CGT>zG{ar
zh2n?aw7B~5%mmPNXypodUy~Gu6XH7~zJF?#;kt`4%Md~YGkP8v;~AIrfZSs`oWcn5
zhI#G#zb+7V{Q*MVO^o`=HhmtTm2IctZJ=zIvk`-dy}ic<P9p6<nJZ<-k-gEhPL4$w
zcRDXqqMy1L@(^^_{Qc<MZZ5wgj_#{3BaR-UqHs5Rp1Fi;uVR{r^bVuR%HVP*Xh-zj
zi@?S|bA<g2=cce(SUU(jD>}7+cHMjf<XaepI~wQU#&|CWxesHi1&bdui-Soh!zz5P
zH2T3_7wJW&F4Q=tF4TCYF4hEw0#qh3bunLMDCoKl6t;gvd(EB?adn6%xAii@K>g#K
zGYG1g=O%Pri@*lxvUYz>#I@5HZveX}F?K6@MJ|T-zPIi`(*NKB5u@`Ex9JG;*RHhG
z8PiD$x(PEjBSk^?%KG>=C>yM6i_c9(8q!<!Sc_{ndpkJq|4TCDzb4QMa>8p`#yT<$
zX-2$-IgNyq!in*mfto+F=PkJRF@esAY(L{L7u^xcj6-TgVL!z5tpPBM@yJ3HCz$&L
zjAr6qz;6trRm0{ylU5A;1*T6FEH5%sX^no3v8@N-I<w*wER&hqaNL{>CV{@R4;jxi
z_|0UJ+5%p}Xx#yL&K#z;lrq1HuzbtpUjzJ|omtZa4&O7rPLR4tuhxU9t8~{#ICPWF
z)I+#edIO10g`f1k57_*rm8l3nLK+eTw!_kfe?xaf8Z!~Nv(l$)VRBCDzZy}Tm#&F}
zi)3jTWhib)JAZ=izVtSwQL?0^KSG!%wRfX?mM_gDe3A54G&;9L8u13T3h8AH`s=M!
zw-SwUlwDd1HfNbl0AQD_z!{eAvLEoiRQSs>9)onB?B^!143k};o(Y!~jzDozcJ?|v
zosuaRg7b=O+z7yvWTP=5|2{f2J~{-TroI)Z|J17;+TE=FI%S<wF~|#(7scQ>5BM5#
zjo$ae3!dP*U>x(mXYq$)zoY%FM$ZOo+vX2(?J%tcuAQ@f1Vy(Vl#=K<883Ln&zlxO
z(l7KWx_e-gk%)Il+7cem-zYf)!0&JEP)y%QORTy1Z=n8r`XF4F&8-2&%08KBM4WO7
zlA?-urO6de6O_Y7LUm2~d;y44ls#q8r762@g|o*>HzXVtci8>YVfmVk>I0K4yw^80
z)r$`w2+LT_P-Fq^ia1T$8+i88ogNRHJ-Q}m{`c&kU`AIUupB0o`Z$l7g}k{UpUI_H
z)e|O95B?%%K>+S_F*7h6#U82ab$IiYUW^2xpR|%DMgG#C&ZF2b?fwmM1xP0}2H64W
z!M7-ar0eXLKocw-Jqgti>DLP|JtS2PL&L+QpJ@0vBaMwgaaOvImdOvK9lQ}mn)G%u
zTx3YIX@&Vv`qM+;vZRi*@_r<3)Ca<BsSmA3bEN;$1DYo-?h0YPv~MOX3#A_@^YldO
zR7LCjVySr{NS{jgQC6=++V&k9^IUqfAB1Jnvx@;Nmkxgdno6nI8GtHjawxbRWfwO?
zw?(!k2gO#|YwDnFvL%xcy^AdQ1%h#vIn%uRh-|J3!bq7H-KsR%__L^`%L+Lb_y3`+
zS3VqO%6yJN`bg$VE5paK-IO}WkyX$tIahXICW?I7<$1st$XFV_iewX}qZ5i{qYk6?
zOm?^xa3!*97eQ7k>ynCEnJkfBu@y4aGEi5_V#xgqS)wm$FJ;LeXpL4ab2EabMz)_4
zWN&0&S_5AzTd*6oce1=%H0{02lU@KHWmj_m{3Lrp?foLVr-J2IS@l0?;THLa^JuS=
zyvaWhI?JEZSnnb~MUz)Ixl;zZYrFjD-)O{6`Rl{*w@dyvzGVu#hdk#q*mldy9|7nk
z-@Ff|-tu>A;eL<2SPfHOdE36w`N_w0Lg6p3p=3dT{75uR0_DbCs0GQdWFd-!@(I+I
z5c$1q=tAXwc$O96@>!mUB0|obL-a@FlPT>NDObA!aMUjE+y{tb@;|zxdP2Uq5!j;T
z0Un6rr2JJs08hzR^@lK49+i$q;EcRg8UW|zrE?I>1$kUsu*J#aj{_brzt#{Ym*itK
zFiDiV(!%hHTt5oBB>A3X0Itc0bBN-)`~%IWZpiK39zc3io_ZCgDe@j>#C=<CQ=qsj
zpWPQW_vCsc?-i-?4*fy%Kt6a6f=QSElM0gzdEf)IFjGFc7g)079ZUc`mT%gFB3qtF
z$<$nV`4bd*@`27^DUf&ijFuJ3M|i-bSYBYi1)8Vw4UQ;E<nHZY^IX0U+Z~EB`J!eJ
zmdm?jqNtMR(fjd*JYgBS<duAb1~k?3SsTIqTK@VIqJJarm<Qck`IKD%yps=J0kRKr
zVGt}o%A@Xr^Rs-_0(93G`CkWN;;8sqMOlq4iYd<l+^X>Y12o$dw;Lfg7saX3=u1~c
zmKlDxE3Qca+@ZKb>w{g2#T+c%6(N7X#coBrM{wb(_<1sL-imj>K<J~$x&V{Ciqpg4
z!B1f=gu{J`9yGJwub9&x)PV}uA31#g4k)_#0Dn-SyNV7DRt)bBn^48T{{TFs_$`ed
zA%%|tej^m>7}O#akB7rkl;SrFERQLE4uj=!#r2DbFj^5s>(>~?c=~djR=g?!b*y3{
zy)4fv-aUZdbBfJ5i131<G(w5*-$liV-{3c1;d~!935o}6fKOB`-wXU@MH8B5Whs90
zMeUKI53N0N6l40sZ>}Q$HG;`k%o_<^fuh$52%jkKh67%tuu;bUDb_~_`<Y@<2~3_V
zHqtw{RN;3WfjTOuCZMoyQU2No(ydB<A%fbbJVJ|e7iC0GAY7Ht>GiQ)S#<-Rb|_zt
z0=K&|m{M9E%6}-S<fZIFuQhMw_N(yZt8`TWuvdACa&rDkM2=op`d@)bfHITvZh=bk
zW#CekH~OIVz^+W64ATr{J(}V?RBj!Qpt6*jpMiL!JhctAY-J5i(sPtY+rctVxu6Yd
z`O2_fh__JrvjVjz%KntCDOPqdfcvS^N~wnurN;npK3BG-1WB3FAsP{uD|`O~T&42&
z$*`<a+DG1kr&mfBdIwi4`^13ejdDy1fVIlnXqdiN4xEQ5J}ASgp!=-MnvWKKQHCNz
zp!lYYq70BD+p!uhoY)q3q1(!4)uMKSwURKJz4#g)PO>=z;NcXzau3L2S>My>-!trX
zdn=HhV@G4JOmUul$-?hNcKs^Q#Iem9LYTnD(eBVCRy`iN%PdP<8duo63n0A8F8CcL
z*Vuq)2$R{JnGoJ!-6#uri)|GGzbWi}8c^@BuCx(;m(A%6fA`q|pK%LQ*^&r)|D~~E
zw7ySgpU{K&kX_sjMJDS-6a7c5FZN0mkJ<S$^j;3Tss`cbvdw8`m(QkRZ(LEpewu>N
zp0Fba!*3CLwHywgvG2E`R>HPB3YIeV<pb(`b_wm0Rk2-0K=^{SYdN2*Z4CDAk6`+i
zT{Q&K4{VYXY(BC}D5Ls?jixXBSN7-r@axDe?+)P>ZU!aPw{q>v5ZX4*776z*+)wc+
zT)B+q0Bq+v-a%+PIEEUri@Ur6ICpMJB8uJItnIM$<i`F7xHosyegX&|F8MMFU(UW2
zU9y*}J&Tx<IG=uK=v8jV02Ilb?+OTSa9=3%n!;_Mtl(|#*Ccql%YCc?={;^J3x}y3
zOIsrkxbs6nmd@#D#h1Y~@&ij2x6}=|N8F8SSY~sr=TL?!hr78O?(?}3!PKSP;5Mig
zac2TRTFjZ~oBoV*E{3jzyR#MeQm(Q;xXZX3G~KA+x;#T;D!Drmi0}n>ZWI77xvL#v
zQqBE17DWyB<_UCfICUAKujTFzhwweu#*^~IAGr2Q;P4YyM2W!9oNFtvedF@~M&ZbR
z9S2h<{_73Yw(>6YAUgARX!FyBZ*~WT8^0zPjo8j_S%F}7@*`iu#V&ql5d!t#y}SV5
z&Aa17116u@E~t6))AxhLmv392GDLg%+1KFLpI?3qHv9PAwC)Jx6X}J0fcM2-uOgUV
zPZNX?zKWJMhxqxM(U>s)&kTee!5{b;o(}ULDfJM^zkGsP6z}j8qBzE<(6sD0U(BM2
z<|B(CjNykxAd1txk~U23v3#39z<rkAT882rpT7W&$>i@I2F+vM=@x9V`7?>Y=kn*H
zP~`EmCctk2U#~3!E#&)A^0k=n-T}C$eDN8CUBdgU1@1Y2Z45Ze__p-^E9d{~2VoUI
zssl`3@TzFks_ncLX;VcF|2`S`H~hC@C~A3Zci=V3Z!AOco<A`RP5Z>pCikEDWs}j0
zuYC4dkbdK5P-=UN@N5^@oP>9G!M#n0(n9Af9BB$NSD`WiCT@Z%1h^f-+H6?v6z08#
ziMwFmNl&1M(3|$bJO$HIc=8gmX$#m#kd6RwkB~SCz`ep)Jxu(BLxBLC5{8b2@U)Og
z1JoIz=M8k%Ss{ipBj*LL#faj9@F#s^;)Fmcbn$|S<b>jquyH3?5``aW!g@tmX5R}>
zNkZIwRIdq*XoLN_@b5sF-VpjxCjF*he}R}%1lfF$-WIz4j@mt;GcD}y3)^WkH%%yC
z1YNqYIvK);!Z0mNGKIAE@bpM{Xu&;rEcpEa4>`g)N^s^1tBYY$Ak1ojeF{aPu+bT<
zC=!M>1-@9&l>qom7)X<s62ap+ic;YdZMT*QzdM1ZLYNW@VWrTUGM+Dl=A+RiFNO2J
zfvj5C906U85J7M6H^S#ic&ZibNH8nj3!P}Y_Ja`I5&k|2KUK=`{rfCPa?#IUh2^<G
zd=s3E@U%tjK%0wBVow9Y-!Deef+Ro`hXa2=R4;}}khm}z!32xLdn1YvF@ZKA4vFh%
zQW+-hqS;l1*g%HjusHhyOd`cAKcW^TzNLl1F|i-kN_NF@u_y(eqQxwl6U2xsXd!z_
zJjuh;X;Debz%ycAPnet)`!s>y^J3^3wD*E|C<nJGPVAM2B3^uS0K!CZdwW=37XPJ%
zTavh%_9U)~i+xc`7H^(F&)g8_2cdRLJTM0S>?vY7gShXAA7`U_SNtguwfkZ#nx~|S
zQ=H*GO|({lG+kUo_x_<+y&L#UQBNBLkHqFqs67@H^?}O~yVDywSG3UDFkhTW>EZ%$
z^J(Coh~IJ$eUX?u4b)G?m-`UfGhQ4*nUUw>RiAO4P18e<0{%txJPf$AYV2GT-YVu7
z^qP<A?sf#RN7b??{Q0VOJwdTo6<!0OpDLEJ#r~?^w*c6u8mNPZ0F@8zo&~DL8Q}JS
zs+G@`&L;buPB08nb#4adp{lF#U=CNEdk>2U)d`xxN2;a-03D?&842MXmE<){?y6eS
z0D4b#h@SBKs=sI)O;vU2g5rUSrz0n6ssu{>r>pwW@SmZYYen%;H7XWGrpj3WE=%=~
zol=g4sv-{3C#uw^Xzf##G7?3ps*wz#m8s%sKe=4BaRZ79)zVgQU#U7ndrnoVfK~rX
zjx;W$Olp(td_bC(q@xFaN{ff2*_8WeL-QSfBH9*LeuTVbW7>Id)nEtcTEDknM2u}#
zB*Lie&y65z7e<@(?Y~lQc4*fFQFfGm!?jc8U{G`(nhDY_N(!Rumi|C>`=c-HyFW}s
z1A3f(4hKDbc0<xD;!m*k-i-99;^(1XVcEw(yB>W5>ATgxg!V`WOqJ5tePCHAj0X8o
z5`OTy)^I!|%nxCW%={VhDfub*yui6TT&}x!4Gx?bj>cbiW|;-G{mfA<%nmXkV?i0l
z99RrtBojop@C4KG4huB?+rbWZhuKaxi^j=a?2tR~?9SSqXu{yZM$p@BH`{zCl%DKK
z%7A#Wohc9I%`T()h7TLE2NCRHYbbf(%O3j=!o6$@D=huk7F8(x*~a_eG=R0M!5PTT
z?+D>R)^HZJVD=HE6hqhv)Cr;NG+LR5v)Ao3a73{CHzKyftWOk_M_7I|l#%S_E-0ed
z#My}AD0}uV_&vtT>x1+-J4K4(1RFy8CeiGD%K68zr&mCDlI=@Ly;JNQ%A}rV896+}
zvQGpQXIOVP^v+p!Jk2G}v0-oQke+9E&@1Qyd$9<`MYicO1QW+P;CPuLo}IY^F(t4<
z0(6(yz;`GT*=}bcOk$f;KV4;i)g#brYz|G-ud{atK$y%99{?9O*opfQ%uV*+O8C9S
z9ytKqZT4(ec(}ukY9soL=`PyMZ2`Q`Hpm7dmGx5t|9~CW6E<n=-rKk%57|b<mdVzq
zG;<c)osLO7Vr6|{`Is%Eyk0h2(+HM1?7x(p$z{7L!I{SflHYuU23-MrbR)X5kkxiZ
z6i-;sAHh<@hTG|;7qgQKLGzSd_8*kb*xA@K$BfzaNBDit9-tLXDXSsBW$YzNla{m3
zX?0e?I?$$FCF{@wx+=E44Ye0+ze2cw$qw;F@rs?D2+nFYkW%k8?2EpL;x)U;j6mP8
z!cO`Q)Uria;P5S5Q~~Kbc3KnId}Oy4q4>mZPk`<#>+c84Z>(n(NFBKiRS<6BcF{}9
znQKihT)D$IHLGyr4t|4f2NyOE@SR-Ka+vJmT7^L8&h0#i!h>U|V|R0{Qz`A`$t{`(
zQZMeEE0o?`ze?16xUYr4@8SID+41FG{f(L*=Sdj_e{KwgwvYRC1u=ziv45fn<^J)8
z-$PtNUjV|m^VlR%gmcem9E{+OarBIHKh?tI2p6LQOC(o{%|W{&iaSGzuA`jdD1ti1
z+36(Sajpp+T{^+7UkQ9PSMd$H7;bF@bSJr;zd?A4+kYOo)7&rArLkPIMIb%H-J&(b
zSuQRIU3rc>M9GTt+!PKiyTC<;Akd4P`XwymxblGz+T*!T-GEQv>@?@Q#1)1?naJIy
zY~f{&IfmL5PD=w&5_kI<xUX`noT0nMjc<lvk~vq}GQYuT`-AN!_kI;jZgDx-6~n@0
z1ZA{ubGy^=ZMwsaq`cl;PTm#%?s0w;;e9*zXgZ{+oO=aq9&lHN!c!XON!!Ee+~FeF
zWN_nt1?fXh+7v}5w|EpxvbY^I-+#otD+KN_S4%mbY%X~lqR8QzjRR*c_nz)#9#=sp
z8}hl{n-ORMci0T~h1?EW0zKjEQ|V|#5!d}k;ETCJ%3VC=Cas3)Gfsi?M_A^Jrn$^>
zuKo#FmU0(tuq@*WlMqZf=Xw&JD!9j#@2}*}(vqNxD@=pm7hEoN>`SioOTb@o;WW{x
z=Dtyn)^HwEA$-k6`i$#sYNMjV5PtmA^-%5S@%6w!%Fm!pu0TGI(!B@xKpN13_z)k@
z-X{B$c?cntH!A=;#E(iqBw_qqTBwEdve_sicwr%m!~FS~X!;TUr3vUr-k-+pDE{hp
z_&&-<(Se;4{L39EqWRmj#~8!=Zb9uN-;y5bQ~bK7Xu)Z|bpUFye6QW`cZPp!ry1s1
zek$$voZ}lLL3*C=LwUmsykmEmUgRrE5n&v^lja2R`~aGzB=9#DA*M@w)ln3Q{FOAo
zFY}77D6a5dX|kTgH;;nlRetFZ6xaBz7ZA*KzWggXB$;3I4%9bzaS){nZt}&a0ldXK
z%FsV4y!Iq)Zu9+UG`+)T(0lnVf9)tN@A23e!IQ?%p|oczKj<iE9`L<;;Z~*buO}kV
zbUu6?$TIjDaq#<)kE4y!Onws5Vu~!jmN*~rUiD%5n6I5jV@5VV3a6_TIs6kk{+P?#
zywIjRKEDSL`FsFPDGK;ER}oVo?>GXrC;U@8VtUF?9|yK)yeEwdCHyW*7(VCs4+gH3
ze{dQsW&FKSFe&Fh9S5$0Po=%KN`71cYE^u{#xzZS!B1=r;7k5bI$8FLulEUvYJOlM
z+El{_t%C41KY>o?z2WC)16a#Xr?=%>e)MQW@s9smAEfX3=q{*z;PIOP47mI!Bck}k
zxBC;i&%C}D;9q#@Ex^C>emF3L1)ld5L}+&u*3)8ci?A^eq)x)6NJzH|7Fuj?6ZZSU
z)LDq!1yUEG`){Ce6+%N{=_a(Mv%}kkA3|ZdLx?Per=3DD9VXc&r2GY)yAZYu4n2f6
zbYx<;VDksuQ)o<kW?n*v7~s6^!mN=n^%1VqRC=%QU^YDY32RnE=`YB}ptes4Jc(kz
zP&)*{1PJLw8Ym=d;qZVk%^gLMpq~KYK_O@~IxkqzwgEgus9b_tsL&<|9u5g#O<)NV
zund$a!i987wM7W_v3=n8urQ0x8Xpnb|B70qAlriwqXY+<pC1)2w?y2>ge5rot~f57
zpwkg2gdy}DixygS1};Vzbpo}M!VEejeM<O|mLsQy1vGz&6=pw1?ToNu2x@1Ab^`%F
zCuChfab8$qr*+!}VcAQBcu|O7grMStKSqKy9{mhqf-wCUgqH+qJS-Chr&8!H3mLTT
zx+0{^0BMr&q8Dmcg(P1@aZL!N)bVv;%tp9K7Am3;(+wf`9g3U6V1ER2O9(lFT8iLk
zrTxL%!tB*>aZl(#PvCuFHzm$fg+4RTQ4fTH^xaGoK6is<x^UABPZ>fW?O{9=s$&sM
zrm$fr9A*hx6@-t3xc2}&799IQm@Q;ypvVze4TQOZjTUivLXVqhOTIAc2yK-Y2*Ya7
zib7!k9XWa;9Nr0KkuaVPsul|u{zWUE3d?A__L=Z47M3M~{|nGO7bJsVQY!2@1(Px%
zz9DqwLO!KGDg<^C$SQ^9YtW=BVK;61z7Y1#M(w50jEYx6_q_tXf7L=79et`1R?=~<
z*Fv+lFnuE&r48*`p^OL3Tfxv3?%xS5X_x1{(2&CaAS|FE_@m%94S-L=!zAcF3!N#=
z^F=s98w_8CD#}TI6W-9_Bu6ogJZusF-GP2`5`DfvXx}QHrU}zF(eWgz&SEsByj{eU
z5cqW!`=z1gCMI14V!PObwxD;3rnvyPi-xhNd5BJw*76ej)AY$(l+k$OBL>j6!Cp~9
z&y%018iRQK#hG+N1H@M!(RqR5?0o<nu#0QgpbQpU&4G&$@r^4ShKl-m=%H{i={9N+
z;+skU4~w1D@EavQn1kY|*zp8}$3$P6=N%WjQp)UvD5GRzwCG5SgBa19&d8q>$I~4-
zCC;0MKu?SIU|7bAy$*rpj5slej_#Zl*HE73oY;`E@#n?Q;Xqsv&mTu|Q5<^>x;QcS
zH9W<Oed%;jf;cZ0wM$~rGlZQeMm~edWwC5DI{1n>(x+lzJ-cNpVo4UWkHFszu~{ed
z!A-Fv?ZMp=-G;(XipW!L?Y20kE6{huC>p@;ipSGIa!<TR^RxTn5c=Mvip47tO1kJW
z6txWT{16lm#ZF5>ohf>`!BLhtt0Pz*iHm8Y_px}zJ{S0Gk*C~1j(FPwn_O`~H#p1_
z7jA=1zBrVA*ij&k%Y)xSaRWVgPsCQ`02GO<XeY5)OsD+hQ!%3xaL+{dZs05teFH)E
zTy&&eic;|#ot!HZZyf-jTogUQSs~8iX*OOdY7c<4O5AZ4(idVqKLB5fw+bM9CH_r&
ztkvS6EC_4FOnPm;7LOX?@Qrwa9^+c^08N+PiepCr{tihK=-!J9TOh&@qH#F@AH_6U
z1AP)jIuHI?9OMJt7twN3iEs8-@$VndQQyRabV$xowU07LTU42?fN)YR{|KG4%H<P;
zE~<cXxNudmber5%ZI%GAT_t8C&>bp6CvfjnwHg52F4a9c9_6mOOp9s{)j1_hcB_ur
z5R9klo;%!osrLOV!8hAm)qv({KB}@wK<rVKd<2cJ%0^51y(<55`1Mou+Ka+p)r)?t
zuus)$BWU)kN(Mt1pxUkhJWw@(_I(eimeMpjNaakA)j^fJ526oN%@E-}L?!8pTNtX!
z`3ok8RAW3Lw1=sj=uAzxDwNI)M5qo?p7F5i4sGBZQAICA5vdwI7M`M1k;v64j;hSr
z031{8r%k)#suQ#zJE59PCk3NbgN8#GqpDGZ<)o_NMtC}<;%EYUT6L3>@Ug1;GH{+#
zW!6LOyj@jI+bS1S88slisJfegB2Lwn5+d=cwrfF?pxW~QeQ`-OEE;Tysu6T*>$0jf
z9df;*`bO!ZBvmc#oLp7qx<hwOW$FYM*HweU0Z3Mj?2O`uDz6;?H&xl^pu43~(N<}S
z%HEGoZQWM&qxIPxRej>Vs~R;CruS41v|oK+RYFU@RMn-Oh~j~Y(;~Dql`tPgy6Ukv
z;>}Q9$AL7Yo6diMWu|J_CFrtLztfBEk!pD_IDD)MT>+D9)#jVv%u&7l1x3E9Vp=HT
zE>QiO2h&0oKNCf<Y8Cw|>8Z+_Rv*t)vuOw`RSh}{VVOz@2e4c<lip%gs<x}(@P(?y
zdEj2E=F%osjcUYbIDD--<MYR`dUmf!#PU(a(Ea?RdN&RBpH+!;g5`^9juez%RSKF~
zeN#17z@4LdA*E`!r~@vc=A@oZUt;{6<p>;XQ&-croU^*n5dar;K1~N))u}Wtxv7_B
zpnJBf-&TQhhx+<k=ys~d+3DQZF7=(8sJg4~QZm^?om(IH-D=NqVDnTrJ%pxssS7jU
z!dqQb2!M}T-w`Hz)JNu^@KvvO25zr<+%mBEsk6dS^H*2U)4WeTzY-m?U;WJm@Bp>%
z5tsz3=QyA^pdNn64r!43Ky!q6P+dtclVEkjgJ@xh`WUUwLe(PerW{f;<4_Az*V2zi
z!qrpTfjdGy(uxQVt54Dywj=7k#RxP~y^u~MMyZPqp}j}dg?(UhOl_h*Kdv6q1-cXJ
z`5#~zt#){fgZPS5>ZbWno>qI(=o+hD@hcpjQ|H#8q36{B6w?Lu@ffgORQILzUz~cz
zIatQ4XI%$(g8Eo}=q{-nbU+k|>QEzam({KR1?LrYx32&ssav%~^jFp6=z#4t^;;UM
zudDlDon==ft5fO8xuKrY4aH4$$0!uH)Dz=@NKtR2Oz~}X#1{bXsGnQm>8`pJy$bKC
zXHzEczWT%OU`tgGj6%;mP%E1urZn{)I#ZOcUPU>f4D}OABs^4)+6>D~wQ?(NT9*25
z7+CC&)ZM8sbJT9MZJVnuqUS14?LoU;`Rct4gavBFRG1d3S0|w;R)?=aXiwF?bxBwC
z&Ff%$p>9h*k9esbLBdz+3`(I@t34irrAE!tPc2@n9q5$E8}+<unAECwJwqS9wX4TA
zLo42?FD^qA@6|0#0De$Urp(Dl_3+iGeNwBgLHAkRb18~1>Ww{7d{v*$h3=br@;kV9
z)D%Skutk&R2v1I$p9UhBt(u9H1Kp<i(~81bb7vuhE}BDQP`GMtP{!9y(;!_6{C3U0
zTtu-$vuQb`yEM6tLF2BO<s*!!XHOXbYH!U&+I#ZRq|iaGJ(})g5rnU1HDw3(YL?3Z
z^V4+h1ZscHc-lPLr}0<>;eO43c>n}xQhoqSpyms8;Q`GUIwTUL*~EhLpr++?1Q@J&
zOuwiI(Hvz^3)SpC46;L-t@a;)2-8fXnOV4I<VYYQG-U%3V5H_BI#L;>@eD%ksAg;~
zVmhYjRUanDH8TwWoY2(df-PF}mmg{|8ipn=CpGzWnC+BiZev7oS~GkEYO$KiFEBZy
znO}w|&T1s|nmeb7X+v}S^O}v#P`#ir%|<X6H3BXF<1~(P_>I>TL;|0n`9eD^mo&dp
znkrEf<BU$YtWnKEaYd6!sq-YwBHEa}s%f8q+BMCoU^u+4+2#RwvgRZ0|J~3`%to)>
z)QtHGx3@HHB4`UZMboV#5VtigX-0QPBl``_zN`6%HreiJviE@WzQ$qzB2^=Bi0Oew
zph;hvX7oA)nyzsf1Yw4zts8_7HBDx~MW*J_ZQ!yrd6Wcrr1>-zCfS<A^@t)z6GZ2l
zay3afHegreX%^A>+<eVoI_grO322453pI{cVEROJnvQZ7X};3(yI6Ca-iS{%Q{JHV
zOmm;svClOP>vk|Szu6!x)9f1rK)L2!4Ol8PT{QqyYEDpQp-Ll)aP&gM*9Y}WP5st@
z+h1w+(K+&J&3@{d8qK{=0M=?E=>7UubB>0Kcbb~V(7o4ebVA%8G(XZ7|3}SQI$ZWi
zGvZf-{aJIYJ8)k#;qD;)s`+ykTK`RxeguW1HkpNRtG2osaND$%a>V4UjkpE3E_SV)
z9t>Blc?W3RwA=Qgwq0A(8#X(%7pJ35JGCx6Om}HVRf5J{`)?#nJhZRM5So|PdoN79
zwdH33_t6F{M@)OP=kfse)sAyOv-fHpQz7)zj!%P$zxM7pM6pjBa|p$LtzAk(Xn;13
zG8%!}qk#zcfVSgCI1JL3mBZmd?J_z_5v=`VHvEQY_flVkYCUN3c}UxzPMn2lo#|l-
z*D9-E5}|F`6efqY)dzq(q8&nKc_Ot}`@k|vYo;TJN3|QMgN|wY+lRvMac!|bY))vK
z(Bl=YwbX(pMr)(3zLQ!#t%Xi$$IuSPY3+XcO=zsPX$gd9v`1-bcUJpxHvs3f*XZ#$
zul?c;_ZPJDCxY{$_VF(WE$(|vm$Zd6mLzIteggGn?a^@BlenT~{z5fLTSYUxtJ)^*
zKyyud#0A{fwFmpcQ?mBB5iV|ON6iG=E$x+7h$2PnN2BCzZ3{X=d`IgU3EW++d>Ab6
zYgZ0MEmga8J38Tkwup9@)3h&@AWPR4P$nZo+hH&r1J2T}I0e6twB2a|@mSlsIq=!q
zH4T8s(YlO-X|8tGK=fChmTwAtzIJ~H6b0Hdv~yLc-9H0?KGFUog~KAP%LM?6wJFa)
z_EfvO1k}&8t?0~0iB?Vn|8wnVcTksV$6=Sxt|-%vrO~-udynp6g*LGQZK~Az+kmgq
zp3g<`LOT|Fe~OpdxzEA<N_&Me;MH31YQ*$b+f9OC-f20?d%f50u7L1^b^>+KM{SFS
zAp4}P+63KaZPOHZ_@bRknVYZL0NNR`f77lbgriO$h}gF1Hq&N=la9Rt<yM`R9^`Gh
zr8M_&)%nmm)J^A#0}_huI^}#6J9I~Bp1D)k<s%~8rQ1n!2Y21m5(qtX(<#BQTW3l{
z2YKtdjX*Fyx_Z+g+@mW=LtA|9x;-*T_v#`lQTXXTwgRcYZe|nM?9=U{FXevSq~Aaq
zp!?|(bb-1<Whf5l=23D!ST~Gz3PN;WqX7ujojd}-AzjdOn1tz0ok0<<d#Zv-gsyBQ
znsitvoeta)oh}&uB6arS5`+<@>-Y}Rqq?8oq7^4}u@7Myt&4tuT8ys!FqoXwHTWBd
zQ@XRQV0l`%89R-NSY4+i6lZjkN5lPD-G)F|p3^0FfysGY|5FJ2g09dJx{Ep|ItCM`
zt1bX_ysq;w#FVIOXs6A!%ewK2=-?~5YD$bJ>Dtid%T-;F9PY2_RxN|y>$=9hz@4mn
zaRRy<I@31@Q*=XUrE^<%leTH@=;qK@?XJ$J7{YrxN18R?*GVWZlB#nXkG^=Ia~lc2
zX}bEf#!lCrx<f1A3|;aoNFVA(2E)Z8-Qwv$Jl2g&hfTJwEp0;P=ti~!K35k{xz;@0
zNZL5d*V&{16zHz<XlS9XkQS>?bbD#Hr$~oI8@>m+BlM%j5}k>@zRz{NlYlGLtw{u+
zOjrFQt$@pQGh@JAp<771mz6pfI+aqTTM>cU3*9(6HSton`!j^Eblx*STCJO@22G7l
zosF<x>jusP_ZwYnnn%6U#Zn6Mz3w8d%s%Mm(<z#dx|ei(^pozk1j5fc&#S0?(Rt!s
zZdZKOjiV{hH{IqaMB${LNK?eE`mA-Z*`{}D44t!nHNBx-^eep~bk&E`Y~M{k^f`3f
z^_mVScIao(OlGHkCgnVL>6_h$&|QC7f|{p3i4KW)>9ut4y!Fy_MB$@v$pc{Dqu((K
zetq>{CIGQlUr0OSe)<{Fu<_Sd!~?%iA4HGte*JWs2?gl0GGG#<x6lvD4(hMd9$T<}
zFQrsM^dW`Nh3XTFa9<DU`_cA7n0`+a6yf>?92`aHlheU@SU>U`IFH!%aTVyVNPQxu
zsE_I8bg=NaUYiTy3H^S0yF}}!d4W4d|AF3^C-r@3<NK8U-E^>>*0-b6O0jyD&ODye
z@1{A(d3^+>X)fr;js?p_ecJ-S<MgjnAdJ@+r=ymjpYa0Jm-O~`G~-Ov4@n01W&MUZ
zD6Z%m$YGPDe?`51U7t-U%w)ak7K$7CkF<Qdsh`yz4sYpiZbFfwf8_$*ZT$q=x4WZH
zX^7D7>XT?2?VkQ!Jv8aQzC{lRQ}unm!b7^=|1xSB`d9WSxOk{P^bCEHsh`;xwJd#n
zQ`kJxcQS+Yv3~htILy`u?*Lnle(DUE<mz{f1RzhJwhJ`*`Y&|&{fYjb7QqzhgK7V*
zSU;H-Tu=1|N|!v-f1_h)CHfmW0G{g&bikujziu}j04vka`UGjEUNIVdQl+0q3$_>f
z4Kz!8ssF7NOkU}S(@eEmzlwg#SEJXd(QB{u@7)1-qyL+hq_z5Iv>p9cFS`tf@AS{8
zg&*~Clm!2z&!v3mXMLO#a9{M*>!ACp7e~<d@0-478Mqw{RrCegV(3fRN+$zPH+HMx
zmkDUoHiHR2?NvA%M$_bFyTLvM_#K7^l%d#Z7)vYhU50J+T)7*zF9Y1eu$&s|Wf(CX
ze!UHcC|}`YxX}V8dknSo3k_ex5DaWMf@mlWht$t7s~gz-4XJZsy3a77E%5sd_a?$`
zfMNC>bZMZWC=JB{!$sP}3NkdBiO>!j1UecNY*<SN^g;}q^1&Ty_(=2CLxvj?^mCZu
z&s5aH4Yl+-i7*VHsp4V7<~S7gBZl#GQYg}(prh7NhP*o<J!(*u0eH+Xo;EU$8#d4;
z#|cCC{Xj$;&e7T57(@18gm%)fh7#qc4561%oHn$eeZ5$Ng=UOr3`umG&Kg$s2jHCH
z+!HkEydl3CbQcVreGv9VyP?Jj&5kpyTZ|&!P^E-Tf<Z@XtxE>~)?iCCw4}w^Wy3p4
zvtBVIPKKu>LvUZ1Ts62wf%}@F(?K-iy5XV#VX`4*G`MdViaMZn(~z(X)VB=X8v~wV
zu&x2%wju5+baxE){WO@|HFP<M_TDoDj{wbm!!LHYNHzRPJ0K4XS(M^SGstL>lx}D`
z9=Z%et6CHf4JRlunrWD_AGj>TBr}AM47mq@du-@>2DNNMEDb_A1`pcC&Nb|$-|y!c
z{-f7+zM;lWGzEtC`{BOO5PcuPJTbTrgH4g4PY!^^hWw#0d20CMB}ktcexuiKiQ&sW
z0G=CW^+B!NpqmWK3d3^xNl2x^mHuo*m7&K16fX?!G+w+ktm=p2m7(ofG`rfcma<JX
zhV*vy{(Eik)`0DeVNVcT)EWlSZ)e^betD1LoxvplF}*h=)4A0ThEX(o_-Gj51-4Iy
zoS|^|+0ZW(CSMG{tO55|L&z7z`^~Vn0_}A){-(yg+hXiM`FSVf;{L#GHJ;?4+h$DP
zOh*u%jq7PX=weKkK<R2cRF~d0Hp)i$+l|v`WZGdo{0R7+##Mt6#V+Hlmaud;E~0Z0
z9>(>{0pD$0@e-Dv#?jR4UdH6^2-Mqnfd2G^kFh}q2=^Gb(KN-^SaBKfy+&tn+7*7r
zgEYMR8>L$y-Dg}*tGfNhCf(5`0mf>2Nd+25&<JzDSiJ!zK}JtHTXxXco|Xy0#uGHq
zgcw(~0U*@)*bB8o#=@(JH_SLG81Qi8i+|9~5ysm=s2w&=q#tn{F}AD^xINN1s29p8
zW6d?-j~aRUsva};pk1@$#_%o(?SwJN5p2=MO`oBQF)pVLK52YD0fC+}j--v#)5c?~
z&=;}B|Ej@##yGnPinGS1_W(a<bn}OY^TzI!q_|+z?MKI6G>&=!c%0qXn0^QsZ|tN3
zO@gtJ9>7b+xKAh&jVtMt<7H#VD?nT|el7;$nz3{{Lc4A}PE-11V<{bEx?y}W0HNJ9
zcBFUtEh9rCT8i<F64bYiE9o!H+%cLcTYA^H>pxK6Gj?hK&ih9Dn5(F!8s|L%{(<pI
zCb-j#*J&-CZd^`@tqfy*db}PQ$4vqv)A&bY)Uu5AeuK#)V_AEcJT`JPLC7|~{(xGJ
zvFjs5k!$>YFv#+ZD`<l%-)O8tyamQTN1;||oc}NUJu%+4k43e}_?p%b#l}h_@K22|
zN)gjD<4yW?L5a~c3Ea<(tDAwe)EG<q+hxYVbfCE0*kKrO6~-hwDOPDrpkoYG#u7i&
zUKl-TG5XS&dmK@`GA?Ta>T2U?9Xg@L_)}YWcx~)-%g1s05BBkGAbfAsHbL>hSV4>K
zkH#fU0Qh8dp~?GaV^{>@{9?=)0+X-C^#|eMn^8vzZ$}fC3bHMxDN^`zG6kOpV5{kG
zUzlt&{d*2LXH&huVd7$XyB#L3reA4^=4KigjW%pImDxLjW{0Vkj&kfY6{o}fE|WuR
z(72n*j-&7}dDHN^+qCu<6rQH?_5gU9>c@i3+cfQ0nE06b(Rs5yrh<>q`I<T}M6uW8
zH32>1XF5cqtG{W(LRjuI&2d4e1)8*}i12`^Wj#BTL8hfFlm|`w=;UIssfNy?g_wj0
z2t!S=)!;s4D&K$z!%Pj<BZ_d-p8~ieOkN`p#bHwi$~7D@b)<t1k*38ffr~QDqoeaj
zO^az)<(TP}6(+|`yf3IvnBwD6i#GWb@-6YDGO4KbCru1B`;;kSAzYj`ou{O2tf@ZD
zY0sFt`}Ch#&%U!QWEV~M3<xRC6hNu<cvGPQMS|&sfZ~#A(PI>ern9u?eA%>w(yLcY
zvTvYFGHo+~>#FHTI(Ku;H0m`hubYO@n3HVU-3c+=Fimg(;HIfrFmA*x(;P~Fr<iU~
zis82Du{{9M-!ZkK-znWSU8ddBd#1^=Ky%-8XEA6}P07bmJTN6w+9b_%<39k?O~=z<
znPEEkBU=5?^niXZn`ye93|*E<MrV#5nYz)6<*})n7U0>Yis=X@$MlAN5uIytr+j0c
zDeoN3it<el@W%la1tzv9Obbov8n}OAYW^I$BGantD2h${BM|6QQ+-M=Ju~f_2+I=F
zDjjgoO$nC}TB*tFE_7w4T-xg{H`UOog$k1o{p6(56h(iysLE8*27nhPzfxGfG`0VW
z4g<V0O|JxZwJCsp>Q-Z#NDud06Zb2c_Rh4VKk)BOGrYj|!F1s~bRSJ^%3=A*w80x}
zpG`OVz~L8DMhn!wnz|SO_-1O{4tK=SJTn7r*<!x52sJ13KAKl=HP3cOZJW90N~L7J
z!r5F@4!n!`^mgD~&COpS7&o)~Xf%7fc_|%!*kO*L!@E1pLz1D}Wu8Fi9Nf(p2Ot;^
z^U*xicAKBmQ0-~XqhP$u18B>|+w4g%8XxmKpZMAJ?7p<i>~Eel8I=3XYsMq8{pK3V
z@CBIH&}=c#97~V=0doh+7X+E(Ps8M(S^F3*3N|Nhhc3iCE*Qawnm5p6f5;q7nei}l
zA+6iP&F*wGCBl60E-Vk5&mMvBh<R@*SR&1N_8;IW%KRU_FOHfA&{ozl^S_fobKIOw
zQ@Ru8HuU?xXmc{%vl#QFb|_Ao>up0Yr_9L={GK+ukA*PSJc)tj8S@QFubegCrrF3j
za}oXU@x1wc2bf$iXS4?HqIvTa#1v=lzk${U@#f%OKqQz876E_BJd|t_&3<t}TsD_B
zM`%~f!7HFkGCLgy;Ho)j7i!ncPYj^BZZ4zLc(S>WPVe3@H<|*Io92#D;Jjt-cnF=H
zVqQ%<Qn$@+v=@2D925Y+U2~r{^b^f{W^Y;&-8Y{bi>^sE2M2-lfjMXZglT3CC417%
zrSl-nF#mfTCJ)Uf`o+m3bB#AVJvM)!G;+3CqC&hm=H{8u<(jW<hx<J9#%U1do7dB#
zpul{Ho}WVVcv@{eG0XABw=0UwnQIYLu~|c@^{3`YIu`ZJ+`KD1m6#Lz0QlUz<vMhw
z<|^VYGr#QxUAcKa{a&WRJlhQ>m1e&)z*U*2P6F8r^L09D_|n{${%FW6bKYS9s?9;P
zb6sO@N2}u3W<Lpvc5lqqF`%h6*E#_I*8JfV@bAp^LJ;D6^Cn8-e=z?u0c;=5Q+@1z
z)w2(waKD-7&`jUa@~aKCEtca0&@v~>xRtQqYRNHzdYeT>>vd;K(j_=>v2<WT>1r`j
zxNertPtj@HEh;*~w!>nf&6u5*G}@KeW!XkcV|UAOI#}Rg*-5_w*==dH2_~KvfA$?p
zFUwS)#&b>fukYZ`*OKW2vb~ny3qj^*Ij0BQ-_rFkYWpnN>k<2YOSe3j1X#*Ep$oLE
zYY*xJmgY2423fRpNcf;-YAtHPmP4@!H^kDDmQ|saId$1Ki{&Fs!Yu3Sp_$<pSuKhP
z%XoWxxHxPn{tD6~mWogW8fh6x!%CFJ(E&C`E!sh-9kWbqjFug@w4vRp6Bb8ei?&q!
z2|$b`omSl^Ez1&Ma?0|MeuHw_;u8g7tfhY=Se~&sZbUoJT8dx8<eX(KC5SIt>QAR7
zOq^v7rOD$h%^pFSU`eH<`z1@hh$7K4nC{YL%QTudU$OL{Wpk26M}KnTswI0kifb0p
zhA6IEOkDs^wtP5_+6~LA4B&2B&X*wiTb9O+QA@E5!=Ip1+_to*H{czM-z1vZ-?e-g
z0h)W3S9G-GzNK*x`Xbemy#%2>u=H6CU7E#2$7RzkgDh~LVNv}H-9yWKI>wi2>2eRa
zEX$gw;C^J;ML)cKY}rK1*KEr~S{>zBTy{X0Yq=MX(DE$Z>30kH7I{PZ_7qqa-2hFY
z<<?B}*AvS!`c*-Z#WE9qi!IoM!B@)i<}iw9mcorNDY4w7iR*KVNNc=Oi((o8WtKII
zQ7g9$pfz5FrJOQql@^ghQDx~$hx%SvmQphJrKNTOf_Y_m`5IB!t1Zr@K-5^=9neFs
zEzfAl_Qv9$2GUwf3=Ir#E$5n}74IzP>0R*NGKY>zf3S4B35OposdP~4lO_2+Tzs~C
zHi7$#C5tjsUo9Q?z~q}{DDA~KS_iL!Zj06M3s{`2PA}nptKGWNjOsRPJ1vyX*8gaZ
z;9_n3I}onczL((1&3gAC+;6u|pN-lM>u;wJ?@nuTI{C26I(9m6?$(=>_Vut%qgBdo
zYrPBrJgu#BK<#C%_z0c1wLVR=e5~_nrMSmBh2FKkR{ObpNcUPdze3f|I=d}g_*><D
zf!}8xKv|hUtM>u4;(#^9fLf6CL0bS0S}&9%&|quBi(m_}&Zn1jsI?~@b2wz3^e6m=
zS>0(*GTa*321SH*Vkk@wTLWak9kCWVqPHWh3+yyekFr+LfwZI6VOel-%-UOl-aBsH
zLw}m%gtdScMA6o=d!UK21{pwe(mH1zT%59QqyhA_wa5qY##$TGpG7=lof{9pS*zPa
zz|UD<D&Xn7^#Ls<E?7fo`f<^^juyyqR>@#G`w(wU@Pti*b!G!_U$SN~s3lsfzrg0Q
zwe=ztSFAC=!BdiT_%TFr)w+H?aM!HHYhb%>t)g^wvNgRo{NAvxkB081HFY;?x2zqP
zgDl0`lv3xnt$l7H>^s($M}WI)Ee@oK(mku&HgMm!o~3+Ms&ysp(>|~Y^cN@6tY@~M
zztXL`25^yKeZCjEht`{S0m!sArNJx9>go-XN7jHiIDBkfO+V+$wzi~oO^$UV9o5UV
zayJ3UvyP|Ztohbo!r;EZx&c2muqz6!7hWN#C)UR0U@Nk=p#z7-)=SYqJhhIdVe6SS
z=?-)y)`xRYJhxsawo>cIU*V$6DhhB>ZhcY#T!q#DC|p!p&s_$t%G!{Q<-M>f!=QU<
zEuupYudHv1&==L#oAmv$*H|a?M8L1DD%$jVW3By+?yj|dl%aTQ-Tn>2ch-_Yi158N
zU^4uEu>Lv_fREPBouK<<mGg+{tM%Rt)V^68EQAY3+sy`WvBmZ{1`#^hKKDn2TWw8g
zMZV331r5Gww#$^ma<SV!Qa<0+_T?W)-E17~{%p53pvl4xTkjOu?6l3Pfx}(4Yfr%K
zZVR)*#KY!F38US%pL@WCr)?V@rS!5LAA=~oZMi+sULRXB%{BJee(*!h*LINBoqKKD
zSVZAxQ%r|Hf1CX|%?tL~V$uQJZ+q1c%?_~rM8j;L?ScT(12*TwD1vO2wBR^sE2X~<
z5p3Hu6u1!E=9{1iwcV!!1BYxjI${-O^Id`>+}6GYOd@P9;ea2uv9ugKVvC`p@sT!(
z34kb@hkZGMI%-RzVe6P}m>kOEwzjlfI$=9RiK=Lug?3M4Y}ePp@}y0-3cypg--01L
zZENd<eu}mA?u01L*nZds-C5hCo{0XOtz-rodfpbY24oj(L%srj(bjSxYH_w3ekkH?
z|NKJv;so0!I`wwR_8+YV5^W>s^w?$FwQeY`*ft-9rzG3qdx-F=trO*FuG#wi0Nr()
z>rS*V*|s7E?r+#)Y47T$ZCXpP+_HVhfcq3%)J_O*+qx9M(H)y-2*~c*TAM+3&o&}N
z*$Q7g+v+p0Nwt|gLHfYP(O+3evpIZ5f2G_0{1>_mn=#zy&fhKVBYa_!V=KN7?p#~R
zAz0?wR{aKtg|@IrxOid<ZjK0xY+?UFS8NNX?9)?QU?FhNY{kfBDN1ZBX=HkC+e8QP
zN^K446<KB*D22arTTlUN6}HSj5oo2YYAI?}HV-;M_rlgp(;4`ewy*+lzp_2?+47Ic
zUQBVmu_e&9W3BB1JqT}Y!Sr*AcQ%a{-rw7X(oaG^*cKO{_-GqXzi<9zyF^Re&o<Eu
z#TVPLUGVVLHlO|)#5Y?Xdh0qm%%MMnw8f!>lA%rxm#JU2I;^4@`!<L855PG){A;HZ
z-!2Z5Q_vPyhg5F_=;n|#AIj|xi5`f4hl4X6J>BUbSr5`(4$icX<?b-G6+C%3*j9sd
zw}ZP1E<7DNtwG`CV5cv!w?iA+=<{*-T?Vo}4kI>z+Sj4!6x8-Qlnn=qpF>QE9i;va
zd+UL1pTp=CK<szW7J)Rtp)dW|I?$ove=s@Vu$z`PK@J;FgZrSvjGq7qc8L9eT8Kl?
zQs_b*T$aQAA%|-Pa1rLv=KpbY-Emo0UEC23E7OMc?7jEQEGsqB(rj2+R^}{yt!xid
zA3)g%vJ?f`dkP4sC`*Qb2#5^Xdn+I!;=uQN`s;koz2|(-x%c^vd(S!d_fTvyn(;nm
zOJf+1(F-e<v6KSuaSQ`Jg5nt)f2Puy1jg`wXe2V$?S^O)L$w3g$qXq)gi{z{RGyT|
zV1EktPccH`0h-3B+l<C^#++$@W-$1aT{_M9!~=7f$ynb8>@3D{N`q%J=GUX|3}bU8
zxU-Ci4)mR4#210&Fk1ine&%^bCw&a@0weD%Kyw*?QF&e-W0Mp<6*3qs=wD=Xl)>*J
z#>eX*Qp{L>2_hwoV_tBkl#xJX@0S>pdWe)U>?vYc&gd?KWCf$r1s+~ztna~8Rx%!^
zy2mSw(N-u_G48(ve{IzaKRRYr!}x)ckXIQC%3-&bk@qCXHO4=*>#t*EAB2bXjF(*@
z(!eMw0CpoI{(b0OXZ%h3^d`m|K0s?`@IByf3&WXi{#Hgftxnn)duS`w&S*XZ$qvSc
zR3_cYNcsX((q&`FDfiRO$f6>&9!3bQ)_WO$(blMsae{K|{fq}6f($TTqD<W&!!-|N
zh*3&m*I~x)UXT&SvoC?%V1!ZMO~xzE;6@p%=%~{e!<qv!&e-=Q4BcY9cL&Z)FdQm@
zd7EJizXKO18BbDG;~mC<#ps-3e0Uko+-2xUf0|)0$I$LEa9|8K9^+pjM)-hXR$vql
z84YG|GmJl<gTY6PUsj{ho@u1bu><qjzX9gR4Bn3EKFIu<HphpU+h`H$#GGCM;>=96
z4MD?&xt$W<uFOZhaNmvjB<+sfnWI#D=fRwF1|pu!SGS<=Fta2a2ECZ;>5D7g%#IfT
zbA&lzfulam8?S@&Wp3I85kIE)K5+ibN~-n=V2UVJc9i)vE#Z$b8B0L|ncM7b@bozI
z4|;K&V1D>I6oZ%nyTAoAU#2zqNoFlY)<T#)GE7M*(<>NU81vF<^o27wQ*b7VxhM<%
zMl&yvLJV_dD7aXr&>wEcF_jdch-W^}f-?zBHof!{nLg*xm&82DnvMG}nQ5ivTnba@
z1s7A9GkYO(iWx*7?MP#mP#Qg*8Ep?PgSmzB9jBRp&}$@<8PW}yET-mrG-fm3mBX1c
z%;%dy&N8=Ay5k)4%{qYPFjs5_%6aBfl<v5|%vu1wT;`T{s5B;zd0GG$^O>(UVonN}
zKhj5}3YiCJ5-&36J_J|9-06Zb6*Iqefn*6Yg?96$%rDo$#3kkvMc~Sqy90q;&P<|j
z9aJzMr>E9sra#@3mCS$3F~BR#0{U)56|+wT=xXK+eG1A}!+eRVWUn$;Q3|P+8TUL)
zTw_WoP+P}5LbqW(^Z6PmHZWQA7HnkhpbXM=W-1l$G%+{72GY!YmG%WK%-0%0TA8`D
z2yJ67qzqC!^Dve7bubx}4d`SZrejQ9OyO;q?Y1$ukAU_tCjwxpmnosc?0wA4PLO`)
zRm#l`F!xiAdXTx1ik*g-A5eMhFta`oCPtWjv>dy^{FVpqCNu3kL`Iq0jNrzYZ&PYw
zoVlFdrMH-G?1!NV=F>03ncK_}HOM6MwI`p3-8;++w5Ob6uA-`iyG-ReaMMgDcfj0Z
zn%&{|edaxiBRpVA93k?M>ExIH`-`^MVj<zc8m6=4j;!7ExH!nF`4Ubzv(hM@=)(Gz
zwok4s&Jp<O#)@nPh&$`ezc2?LEE7dbJX!x+3cbUuSjrE2u^v$@*qe2o=Jg26|0($A
z!?LuZ&zE(PHpzahG1|EMv)paR;Aa5KfxcOFlodZ8FvnO*x<&(8&MweD&MKrE^#p6K
z0?q`nzFiB0!7Qi0A###ccNQds6&wZ=p{)KiD1@;*mO>$%wQvdw5v;NeP>5ue(sym5
zSo5hcCYsew&#V|$d#?>_ENea$lf<!dsPZD7l^G3Z5?IfE44FjMwH+WytZlSsPG<c~
zvz)>@Muj!0tj1TMaEi5xKJb#pV*UUV=`0g%nKM{ZiE!pL>khp(Gg<p7*qFtNq)1{m
zYZgTU&#*kLl-NJZnoC#ZIo5?Pfab7P--f00tnhI(USK`f2DDrjkA9du)?P|*<g*ss
z16RQ6SPQ#_tf6d>i>!qY;C2y<LtExz*6)vCzJ%pQxtCH_%Qm1~V!cUgq%zi`Hz88a
zN<`&@&8~tqPI-XKEEc^)D_NgY4Zs!FPRdYJu`ap6U^VM$7PuN#^h$_aWnJD4OSP<b
zD5rLf^%H$bqK>ut3!v1q%yf-4u;#puzD8C?2e|7j4-H1&#Nuy)NHgnC5x5ps+HDxJ
zwX)bsjJJ(-lunYivtFgOeg`Y#3b;;IHDPzLEOb+Jv(_yGS`X{q7+`u?ONya4z>59^
zjf1Q%O3w_jwv3^1n01qCSw>j7bkO?-tM>!+-DF*&$k!-q)D9wJto`dT+v7GCcPrRi
ztOcpim|$(Fh0JZ%r|aS3Bx?cHSlnS9r}J!6tPkj7yUThr0OqGz&r>S#9_tN?!Q5vx
zuZGA2*0Z!^ddR|&e7w_GizzJii1oN5!0g%b9uNn%QyqMAWY^MG;UL>~;7#~;h<)}6
zU^}t@o`HrlJB13iT-Z{&4PDu9mV&sk^WKF)clH<W0o#K;a1d^LvRjq|?J#?&8VX+Q
zAPYEeb|)JmN7!#uqQi&%bqiecWhZ8%(T_bqSvY_8P6nI_U_01oy?T`W2}P)nv1giK
zB9JYl$JB9l3%xc^urK++wIFtZ3tS6kFZ&dBPqJIS0d@#`e;P&~%6^J=c42JXg}Cw9
z`)AM>!Pe<uB9fgS1ro(BkwPz;9Y8l#47>74K*zF&4*RY7=Na40JXlX)3oBtZk<IuD
zl1c34v{z1Mi)nY8!fvYpm&!i<DttM`9;Qf68rz?qCF$&UX{(&UUU3)XG<#7MoXBLm
z2f#uWd)0i5FPqJ+faDo=?ON!aWp`Es<s5qjeVZeP&9PCa_dJ_Jsj>^~w<!af%l4&l
z=CK>zLSH_+=M8vKz}`F`jfHFmRVZI%U;7G;MeOrbvs29WoB&!0TaKH`u9V%|27k-h
zt}SS+V4LVz&t-NIy-X_ELLL;Zu(KSXUd48(pcO<l`)#T$sbPO<h3HjwjXxA?*?aP#
zagANo4KM20E9t(iXYa#*0@yXMv#7qakzL-5F<obGY6WRx@3cX^nH?Phg%);~116!B
zokw>=8~d~Mu+YwKJPwo&wg+ulJK5i`DFoWZ{^|kHy4jCWEm#lRgI4*yZ2mhKZy)=U
z-EgL#JuQaa0rsb~Y#d~JT!O+7JBun%huLxSp)kUZpxosR_OBE(y~)<Ufxc08Chf+@
z*vIJr#yHz|HpngZpJ70mU^B56wAtNeH!K9&BwM;0ChoA~o`S{{Te1N%ciF3-0NONr
zQx`<;u|sGjeV^@kA21Kt`E-#zWIw+Qc4ye36!v?>uA;IWdrp=U6dX7!!lB^EnZ64T
z4|3L0Z21u9-eHW)iIZLg5t}oo(H9ynoUe@#b>%!o5q39D>qj8&9ES`vdT_ic_V3Ag
z<^Z_EoD4Dgyg042Q}^an=7AjHBv2aIhx3CYKz%v+2SEHd+HJ7w&&iNr@&h>gf?@tB
zr|<&Qk8!?e1Q%%Ibo9cT;~d2R=IaD!MF=#4IAN|p3+7DR2X~UwPjxvVoVpUggmT(H
z1_|TrxdVl8&f{}nDS{)6!yqC#14-~OinHh`Oi(n(Hxhj@oUb;ZFP3wK0}{u%Ndd2T
zjw>5|NgP{i7|bVgDk)u*!Wp8VODd;!5abl+uQ}*T<7}XF3hA72ii>7&if%yvGzWQH
z+-jV~9?;9;c+y)en-jJcB4;>lG_<pvx9PuL&T;IwK_rKh!^4oyb25Jf<^|5uML@~r
zgxjdfE{~H=)#dq|eY937;N-RgyO4A812}w<^S}#S5hth~eZ`y(3LTYj)>0C@l=Iiq
zaP$%<h>p0FajN@Zshne=pmYW20tIU>bDGkjP|5k|JPcjoB$ooSisRM<y=qR_L&_D`
za2(fxT;;r2kJegF)>Cli8YgujNFC=&J{0RYKhW!>fs^|^>^5@zXrp$WQ{4lDO`Ir-
z5j1nYc^zB}XN3uUt(*_2@TiUB(hJhgsreYBgVR47V4a*F&Oo7yqk5K(e|2*P{)9#k
zXV$kc*voPI01o$YR52JuKW78&00ua&wDuU}Jbx1ULmcaASQ_R`w?J})v(F9cH#ibH
zqIHuqsR1|232lJL7)NCUH_o|BLHJu7|M#FU!TE!NF1I;(8}Xllc9WcZzv=@o+W325
zZ<_Nao$0#A3HcrB_c_mWgL}YPO$DeAIh*t0_6%p&8Tj&u6GMpzd+ye2AP!tUtwbHU
zlXSrSAa}!2h#cZBrwz0dH=T`N!kPONJ>y-t>1#n;xhv`M=*F#~7@j-#mMsGM9$Y>>
z`MtRMZn*8ueTmBHj&Sc$q|1l9SqVj7E`!!ce%ya4(&f+H<qU-Y?v6f?quipcKsm;Z
zp}kZf_d1;vKh8Zw@%a;6_Ym|2arb@)uwd?|l;J+f{bLd$AzbSgdJu<lH$}s#Fs_j<
zvT*Kw+GIy?i#`Mw$$j<=6r;HO70`(0uBH%k4EO8D;Y=*|v0n7Waet){b3E5!4Zsq(
zcj#f6$aUQTx0ARrhk=sJ{dy3trEssm0Dn`td#DoZ6t}5*7A}M|ZrNFYrgMdK-(_%X
zqo9A9`=d9oGr4*6n9AZ_ejnzuxf}EVJ;Pny43V?kg;ex%j(fNZ*g4!my137CZytq-
z3*7mXNY3TH{5~w@arX>DJ)di$Ypj5Ke?IgIxl`@*1&@o|A&Pz!ah0@2E9QPd1!*N*
z?<~x7Dc7E=WiD~o(-XLiJI@gwmUGAGJ8Ko(oxg&+%ypxXYbE#DMQFUjeTwp9Rot@c
z(5vR|Bd&(4ISTcw+*UdzRLgyjLNM33BTqrZR>%EpEfnjy8|XRJ!0o15f=2Elid<di
zPW58EP26Yb;CeInuYEvk;r3IZKr8nF<?PzHUsF=Po!hbs!|vdE-iCT7_jv_e>*9V$
zo8xZo*KJVm;fmjag<kH@i4f`ImYM+FZ{rFNVQL1rf0DsL?(D}QGsF!RLS~rjwGoXY
zTnW9lZ*aFZ!S6BdqC_-~bI1OBsc}D~nVsMsr(<ikxgHc)ndD}NLj4Z+C{=<@aW7Eq
z)?Myf6#AUzE~K^OJ#G%IVefOrtPf%E0oU9O@{qgiSD2XL+T$^6_lUcGDP-(<Zhj7q
zFWTIypm&J(3x)Tccw=)Q;mmup1QIU1m*}>2<?W_;u^Z2V-__2YH%dWS58h6SdVBI>
zDGPI$H$nSmFW&QXY|)$7Me}onH+v6Ie0Yo+5MSQj7h%Yc*R~X3{=D!5Pzc~Hv?ajq
zQQoFnSUSe5q(o~VZ&-`Y<GfZ1_MhNQQnhgqug(#_L@;j?jo~D34hJNJ_dP9^LwQ^1
z85_oHd<|SUPq`9(5j-OeDUv6kt$7qLfXWl1dH(b!kKt8Q1}v8M{(s-BiQ`q$nBsX!
zm*8mv&+|*Tn8*vJ%}f$+=`ct#?;HhLQ+Snf^riA-S`73QFMB@}(s)5sNt4c7R}GTE
zGg1EVG*3)-LniM%`c85dZ;1Z&Bb#?M0fx@-vMKm?miM@hZq#$UrWc`+!+Yg7SUS%e
zp{&yd-iutw<njV34wT1hpv`JNk4fvz0^Z86VX2UpUW8Fx<OOZPK#O?a2Lrp9$2bm=
z65huv&{xWvvjOB1@6KmvEaOd5*<LyC!&QK;;4QsA3peUz-l{~fmAsiBVd4r;ss&6H
zFL({eRo<09;dd=BU@i<^;|Zx0r;Zm)^|JLmCT&(5c%mKXYvg57-1s_gGZUnVXQDk=
zGw+ja5NY8pE`{Az-VhaawDF!Thk85j2vsTDI(Rip;eIDCUIpwfp1l(K-Mnjb9<PU2
zNzZ~_-iKd9q>opW1;u`zkuu-|ymu*jKFE8M)<HwOF9R{p!#w5z^o{V6XeoPx*WLoK
zo4mQffF9+&yAKLuybtMn1mnCVxe&Q!<JEqN&Iw-OY{1;+{XlE}N#5h+{vBS>dZ115
zUZ(ZLUET#MLY(Fa{=|6i@qT|7*!Ov=kAU`ow@?m+hrET9=b7P+-vN2VJNpB`?D=m{
zG|GYhYAT2$|L*4iJIJ?CX7v!?ruz-76Mx|rc;U>qEQE#&KU;=QSN`y?aM6vQ9|tsd
z{sO82^Wg74hdxjK+q7ms%x4Ip;Kes2!@M`&llIX^_-W1{KKz;Q(C5paR|*9`J|iET
zKR@nQOhN#EnHkO;<tuEI0z1Y(NcVOi-{Vzu9_L56LH`7Q0acp?@fUuAzF__|#eq)p
zBOPHWgui?PBt!Xev=I*D7q){7=dVrySOi~3LFGuk%?N{0{7;%863rJ-@FRx*E-k%d
z`O^QwB>W``ikigpx6B1e;5$bFJCW~5n~Ws>yA*X#=08P)N#Q%Zg?UQl|3ty;Q+zFL
zLDTpZ6i+(MFUp2`CVv|p2h8H%r_zsX{=FLzIm7RwQ0-ZMHQjON_-{}wEr&no1?cnq
z(-t}oc!BTQ2R4`gDb;S|@vo=Bd_JE=%iRM03X0Vh@_Q&Rc9E~8WM~op58B%o^OaA-
zL<#>IZ6!<jGZY}X#J}|dNEtuy0Q$=LwUi^N;9sY0%w>Kd?TRb;;xEy6g`a@Z51U;T
ze+>_8HGlSV@U4a~q0Q%2{wGs_sm1S$!Cd2y-v_DV+bxFqdj2R~@(uhye#Yn<`LV44
zz0RMZZE6$0o`NpTd>^`-TKGdLAg%moX|>$Ok6VUuw)5Yi6QLb^GestBo%|XK(0B2l
zaRz8NU-dHPtA{^T4ARTzz754b{&YD+`uW%Bq{jgNXBO-Z^7q_?$PhpOG$v@6KZ`as
zBm8g*X5Zky|2DvG^3``iM){s}H;(aL=|&&tZ>6tj-QssFgTE6t{zZx=-{vRCp*YEJ
zn}Wt2zH2->r}%@huymJSkp=8&e$+0Idwh8?$bG&&MZO;JzoJt<5BVo4DmKHne+}b(
z#1Ae9ioIZN05BZ{tF8ddQSbq+vJVOb^!pqV{7&&uCxOj59n@JMcn*Vc5o8pBxC(x!
zU5%TdbONC6g8$CUc?f)UQ1ldRwu8aLg4OQ=%}em&b~xiL_=GYT_~c{|M0^By{s;5E
zf+y+K>L*zC9eg?}7`6v@Ot6!ly@7%Vs;xOLFxjra#0i1)NuUJ@9!r9Lu;4{njGh!I
zjPN2vuvv^zgbKPnLBa%=Mqn^p&_h{*2*KTcphXJq90M06NTj`Xw7}gAuo%HZTHD16
z@_z(aoFHpIpyLG>X-AkK_+khsiGruUw1FlGI=8`_WP$iwz@!K+L}3zA1svMFoe~t%
z3N=lzogSX)f~qs{DMJwOKJ-ot`e~V-DR4Rj&@4gB7f{F+Y>GwW8A0ab;LZv@69f93
z;KBq@as(BWx;`)1Me(2u0^NU6%UnS)wdM&Let=@WAcGF~76^)|4!2McY=Scv1<ySP
z*NOzS6qG9#Jm?2@i6G@0aHWE>|3T!EAea7ipiFR#;ydMnr@w;13c)#waa|TfQ}Jk}
zz>gmNR|HNT=&KTZwRhI6AML6I%V{}QBbcB^;#EN>Wol~$N9Z`jHNp0y@TpGl!c*w0
z7kvC1EHwx=(rdp_V5N1!bwTQB*liN@JqHubf@2gmX%Q@c5{<2bBzpL@364|Lv0c#V
zH|Fu8Euje@-2#;mf<1!6bi4NoWC|GQ6V$Y$uU~L}7>xr0ufIVC1&&<!Hzc^Z7p@Eo
z0zU`Vh~SMaFn&Yeb`gCy1@$YTJ}UV4dH6mi7|epmxWGi0;VnUgBTyy;qZ63V+qmMk
z!}&?UB`w&yf<I_oF)etKY9{Up61ix+FJMK(wFiP{JV71`QXJsZi~#owZY{yr^&s}b
z<_6ex5H^ND&rz5V2onc|pU~6wkZ@xbI49vVkq~hfZtBAC;UZi&0iRrjo?~<X$4!_|
z3sZODSMPxH5T4)z##4B43G@#O3r|ABOZb3Z`rg8yGeC|Ab2{OLkC5vP?|p@bOE6GB
z;WHNW`3n{F@(d8pdl}qOVHRz%j|pd;17@HwwG@5Fg_E=rI3Y}1OJzbq!V|w@6v0AG
zB05hB1F0@4MA%BTIHAH0S{Q^0qp7wmT$qM$4BJHrUw;f-r0{JEK%<0Z9^j&dW_n7+
z2n7@jh!yVr2<madwRD5V3n%C&PY~KwfJ+qaq~}tSuqY4zRce<koJ()?6k#?k(o=;F
zv@kd&RMImuO_(ts)0Qrri~(qd@H}OrP7Akm!rx5cm!)XT5-R_OPuap#3!#2SDDMFF
zS>a_$e4G=m`w@LP!Y4k4-g#ll9rRrgzH0=@6)qo#f-O&&sKD&y3%@xHg9XB%HNY+u
zhE~C+i$a%2Fkd9JuEAi6g|ASAyF{2w(X3KoQ7%9)2~W_Ts7&ZVd7E<KXNdr<5U!yu
z?`7d0T9#A_1v$XHBE-L?;YJglq6}rVaLXBh)!2lmHv;Xd@a1=)SSx%$@!xC0AX<3U
z38$%&yIxpFr3nqflYhadCSfhTuA7A!e?YQD_|!RYt-`E+^tA~`KL=?SR$m9{5SG(e
zI)&oTVX#Z+`2{@e7JA0PiymRx(-7$u+9K&;*C+goZoGbB5KZZTFfkdRgTkU6XdDu5
zKM9Rtp*9m!IwE{|5nyfz-Pgjko5GKk=o=L#e1~}+6SDq=$hffkIjG+f_E8=0gz!Up
zWZo98_Cw#K@Y9FryCV$ifKOAxFKo1PzbicSKIUs$cwq@Z?+KIt0qA|<Mp`C35EiAv
z;6q_5or;?g4%6H3k?=a5MYI=rQ)JIURAz@hM^Sk)zz&N3rlR6QB9Ra%PNE%g;G9KY
zje@v{$|;)VDms=A1vk-+R2yX6MO73!@({f+51x988diflEZR-ite5Bm7DT*7rdcp}
zMD#61JAFhK>9y%AN{YiM{6y_65P#7L3a|%=a{oc!QPBfBGI2~aOAQYLMUr}e9T$1f
z4|+oMF9kG%L{kA2BMuhTJpg-Bw1kdRgou(>!eFSV;Sw6dL`9Qm3>Wp>02d*OpvP9E
z=vAtwi4sLb!EUtZgLg2P7*UHiL}EoLRO1pS+PNKi@uD9z=t~e)bKp~=Xf-7slSJ9{
za84He(@6)wQ$(wmf=w0i>mYMVwBlckK25aG9+uKY%!km(5IvyB&S}y6``}up=xZ)S
zvP9i$;6=9Rs~~uBMil-kES(kYssVRi^vzc2T@Y=ectx%#=R^3EC#p<?UcM;37AOTG
zW;KYdQ1tLS*u5xPXM@8<qPOXNSuBeG2WTatEV|}OMM<>oyCnMNGmtXTl6aUX7kw&%
zeuXHd9H5s)8>s52Qj|y0k1L{~O)yv``k)eCREzZgeFQ_~77u@~ik32=S1ZEO40oDM
zB%n1`oe2NYhFeWkLl4#l(e8Jk*eLQk2-mKQ4pNS?Nu>V*lFg#m9njYzdbtBIt)f5U
z(bp#WgA4U`(OcdS=@7NhLa|e%ngf5kL_6u}(=Cd;3(_O{=oT#Wimp&}wNK=C$9KMM
zoQfa^Mf2%lH6+?6!hnWF;q+!25f#%3t{bA9p8<7K^dJJ(Mnwe`80?rR{yXT6i>6ut
zd`nd61;h!_cl12DExH&0Zc@~i3GR+)avCU8qTtOScSS!_75ud5^<&`fiQc!R1N6S=
zJt}8^Aj+5vw1=WkW`I2-a-kUKBa!M3#$_)qrWmJ#_|FoUcN8Cc4BSC+_$qLR#Nub*
zp_6z=42ZLMa6ZQ3B95o9ldJfzn`m?s2NuGDyV!#!!b6<34SJs93t!R?e^~4|1mY!r
znGP~~i#J+8j)))o5;8vGzMs(NEB>MeoS*pFMS$@aZ=}U$fOu~JEFBf!dK@N>iDxKW
z94P*qzW#Y!+<zL4C&VgRN(G5K>3~Rxcr*b&PN?|3FzAJex3Ov06E6O00SrcnD{rGS
zQhbGqLZZYjUt$uX#Va1eB*uu>9D_)#c+WYQh!fAJFG|FVb^Bl`LF`!yE>SF507sL=
z^JhSk#TB%6OA+6vJ!-0WtOqEk#8DJFNfU=G2THow89^4lU4~fw6JSn@d6Y%T6u(A+
zy)3bq-o4r4U;X$2EL+nEFwcvR(*ERvxS<UW=8AnNi<c*6Qgl3Dtfpi{fjAWBl<W${
zcMrkBMRDQ-I8h`{q{Vcx*mMjcCE{J*0<2U#_7_AhiDh&!q)dF2uG4byW-Fj8#QUiN
z^Rjrn01B1ja@z&aE8+?v6syD=uL87M%%*y)8ga8Dytpdvs6t<@c+e5fTobp3V<>gv
zK1$)#i+_CtOAX?XL5MVpAJKO(uZw%=nc5_NvkB&##V^rC-6Ec3Lb6p{Kr8Gv@$M~v
zZWoWHP#U^J{5!pKJH^H1aF_Vo?a=5Jze};D9&!1nu-hy4p<<gp@i-k@>K7M9Kz~47
zO{H&x;!Tv;91^>(fx@sjv<7`6;;r)leM9^@?dood+djs~M#Z;^F$rVh*M36dxOnOh
zD#yDe&YcB~3GpwPaR0XWJq=7uif2S1cf{Fc=$jHpQQ6{Mu>+m%ofa>q(&u~Pl+WPP
zeeoC11MPuWa}DI7_yfu%+DqospKduw+E>FhN6B$22017>(+F}%vUnVlPLhwYx3t+g
zON3Mf?;>e!gNCc*d)jBXNmfye$6Zp~0xvuy=c-`dQ_@X?IV@R4WxHOIWk^QYc}v!F
zFnLELeN=7cBgs1fNngo#^w9B>ETIUZzhoiRl?6yHWdZD{<ehhca!evHLeCZ``Gmq=
z$0Y;bV`wKNqi;eZNTR0DN3g^*2{0!mZf@uckyxk@Csgt$6)S{EdKRHCTylb{1tKH?
zbT>pw{zo20NphbAcC_T#Wsr=Ktn~wCtR!RwxH!p<SlEk~%*n(66Ks<GyWmu!WP1)e
zlO&JRE;?EA0X?5mBp*-~FjaEvBrKhhEdB_JX%bs4u+t?!eS*FWiOe75v}ECn@FG(Z
zO1t(fiG3I(vnBWFEqO-bMAdv}C4T<^<(%Y1AQW;W5{h1(mvD-=!~6vaM~Bv2$%$Q<
z#5_sZDZu2z@0!3DZGlmME|Ofk2=!vgVJ`@lNRsGjQ7TEIh5jW;StZoUB-s(*$|ZYO
zLc2op9s|giCBLvRqDsk!w2iwWDW{lFmBd#Kg=&d=2%M;qEUSgcRY{EuBDE4{%EVlg
zy!$f1>LfL`moVIVN%xPK*ape>xp1Ztf8_>^>ypfBXf#O{lme|;vP6Q$7Rh5GD7H$H
zQS52gCUH1}zIKWFChT@e*3+J}TarMFkRD0GIMjP336$6DlWg~aWWVIfI*1HNifm9A
zl+4;dbVyQ6<(<P4ZV5C-BvrHyz9H$lhQ6DUNAwenN*<XYGA7xHQ#y9zk`Y=+-jW=r
zuYOEOB57xPTk?|%WK!}(EDYX}3{yyUN>XzGZr_zSP+)3WBJ6;|J;_h?K)EmB#ZbZC
z14%7?m*}Bn#p`f!MlwRjP9I6U9)Yu$?xW0}gY?Zqz;={=To2HL()2gM9g-^85OI>e
zp@)LA^v6X2b&)>91m`MUM%xWH=`cN%-K7JM!Fvzs<Fsq`lwM<^@38b1-j6mrFX^GH
zknxtjVgWfK-A$WBAL;WHuJV=s<cmr0lg1qasK4~(9FPF%%R-FlsC4na06ivU&|@`F
z>i9j>k4qoY3-W~YP09uYN$qK`7c6Da0`#PG$7Q%3A~n)>Aym4_4~@1ksZs!^!lfna
zp%@``rPq9<R8G6-DCvg75RI1hu0&&uba^Ozij^Ls0<So!FKvb5rG<qskswvv0(PP_
zehwxmN&1MEY01)e-O-mK<vKt;Rr(Z#t4>J;bZ|6H>PBJlbepv76O1WC`nxAIPD_(_
z!kJ8|f)?yq((ANn%a+dGi@r0`j-LT@R@!w73g@IxjDgFM4lag==cP|{fx94WPC{R<
zH2QC-=SkOlz+k>~8J)B!kiNeZC`D2(Ra_KHQ|PEciPV-}2wEx~4aQ(DNja2ZDU<$s
z8KC9T?JIy*A#E!~-(_jlD{!q+n(GNmSETDHzh5Oa&_CW*OTTZy%+yE^HN(VJ>DCyK
zTB#ESf3Hb%DH~iTb-V}YdTGt?APv&EPa)DMEwJ5#%yp^vMW8iFH8+6PELHsu7h9xB
z3*mRG^bikyZPKHZeruQNsKmTOT18iIr}Sg`m|K^$y$S>EmOew<l^*GLAA<BspP?sc
zpVWRQNWXL;h1Uk8Qd&k2O10NPhNS+n6lxikvPOYDB4uqw>kVn~dT=+TwFbC0D&3F(
zv@xj{Ej`Dj3+P>ZOS-2Tpc7KN4QRYA4f2PFlTt-F!0t#RvoVM%>Fc!Axhr+;0GXD)
zOOMBUQYNiq?@NQ6pzuJtL`&yoA4(U!4bT~B^J}pCNct~TTiVNH8eluf_Ff0)D08O!
z@1Sgma&w1dztH=`N%j)$qMc<k3qV|Cuh6>0RkndnF1X2Z*TSy5Y!wwjddQ9ygY%U6
zQ~vm{Z1xI(dCA_zqSt2UE!#|6zaz5uDj@13yF?)YU)d50e)-8Ny8-Gid!K4q0%WoD
z`a3GyO?mTUviQTW6e!z8A6Gsu3&{cK3E8h-Kp{w0M2q=gnZpD`PRbBe#EmCg;SLfi
zn@b<82$LP916H<h*@Ck$A0gZR14yJy;fl@}S?KS8iIsH-pdTlDp0Wb*GP^q1O^`*f
zF^WXlP6vo2$!62iC0RC2@7WaDKPRA&Dicv6>XfXK9))SLDB6;z%g&$2$TDQxs3iWh
z>=#<QX4+(L)4MH8cF6@W*|N(NiZ~<VBCcn5R(9h6K+nk(Kcg>4mQKZT=VdQY`ul=R
zOfQ058Ak-S^JEt(=8-R3Iv1os7We~5p)6z!dKYEuP5`V(#w&&w#j?lbn934aG96PX
zmH9P<&bN*6fl)4t+7IyxSvD=SF3Z|3L9SBvZyC5NGH0s2s*<hz2M$%sj5LEavcKr3
zzA76ag<9EHq2R8`HpfG<PWIRc+^d)U_&E9+WaU}#xl#5krR=ZEv~*)N$+qo5U$ZRL
zMt5C{ES@%0t+HVrVA^EWv@>a!JvM}i?2xI3q0uSZPXVzm+06#PbjyN$AkrgSL@VcB
z*$A!v`(!Vfpx!S#vjC0`$c}xBp%2QOC^0Z3E2V|qux!uM02`6LOPiJ(vfW<vmcJ=`
z_$j;@l}+cOb4>Qt>o74c^Z5?smh2%PWI`4^3;MTZ9laovvI9?p+>zPQeKIBc?L$n-
zUD=D90X8lBstzdkWS<>{YxiaUQbGFzSrBErAIg%GVQ5CSd@0By+0N(Y;U2V?FIorI
zLH^4l=sU_AJ%D{szG4x`A^GmtK%C@XQW34IytE0H+~hXOUc1W|aM9=?pV$H7DW5~%
zv^Xrkr~~IEZ>6Jk-tsMUNgt87OJKoAel`;#zVg&CaDMW%vvd#o%Ts5=w*Yz6A%Gs0
zXZ-|+kI4%^gJPik-k;DoE?=xg;|cl73jht0=ll#3EZ;_jQ77dmqJS16-}MYGq)>TO
zC(MV*pQp`XxcuL{z>JXpy9o-B@;43OqU7@_B^@mn-UFsBM&3+`vRHX;JxH9qnbLjn
z^1l{ACPDtxLntQ7BWbghBoFa}Ps#F0y2?`IPf$5ps@%RF+$ni99STa5|4WbIba~YY
z%vy&01u8{6Eq^ZvzeuJ$g93(G@*=9f$d=beL;Z|R9&sNUXXUjE!Jd;Zrz3qiauF@x
z&dZHX;4a8t^MOyf@(=z2Xr4TsUhnyG?k$KE$cLx~y-*&X0QHM<Yc{wd`PUR&D3<?^
ziiJz$x3FcjE0v$3IO!$12OZ2Plc)Owx?FDimrBGd<VQAQpqJ&7%h6dWpJGGfihO$p
z^sD42M_{R1?nn`-8u{^X%+po5_v<iGD_=k%^K0^VZb7|HE}~aqy?opVOAYdCMbK-M
zyEsDOy8Pw2Fw`U;Ux>zLc@$+_TjVQk^kQw5+ph!LCjTc6q+Ra#6-bACKVA8q@^M-S
zbjd&Y3iI48pP!D#9{H17!1c=e!ePEo{yHrL`sM$d1F#{vbu&bU<((%WG9vE@f!!PO
zwFBU8%I`NoWK{l4H}uBjGNldJ<8n`0aNUycr7h%yT)ZFpx8;RiP@I(K8NuC=J5f3R
zl)U6wOwe7q!45MsE&q85hJ8;yMXRCv^0(<M)C2jmbVT8yJnv;F%*a>Ko9U6ffJ%Vv
z6>8e&J1Bk-K+jQ8sis}xK}8QOhYl&8qaCx8qT(Mo<E&_*)sTzgmOc7h6<(hK)J?JO
z9EiJOhKW88#mfEg-czxOa)*Z%!S~STrFdlkgYZ_cj4*LT!Js{fkK!9DGVoRW@+G|R
zQ#4ZO*k6$uMd9=SMM^aEk1CEl1N~!)-zXy(sA#+kjpK@m3mDT0#c4Xe5Tt0n0sUab
zYFZ$kR6MK)7osq{1uj%^`yniaDVEYxD_k+{11};Jr>4;usdzaVC{c<C+IdDR-02Y<
zqbQ;kr7c$R1|4CHQ`AxvAztwcox@2`ETs5-qT)Mx1SctOQFTGGLPBwz6h(+9?4~Ll
z={UkE#m4W@m!@!R2X?xmy9eeo6fL{p{b@xdxt*!lOVtHgih1-Z%vQuL0rVL~A=TBK
zwJD0`K;xXkg;Iz)iWbV>o>zQ)1G9HQv5X?gxr$0!*5@f+qJvKP3Qt-c6ev2W_`OhZ
z&IvwUR2U7wE>f)P09dht<BK^gQ5a}XRH_*Fg5)K|x-O`fDg5_>yR2ww0#~W94a@=d
z6~#O%yRA|@PGw%zib*G!s8P)4LguQ1{VOzT6>9<@a!nD9or7JS;_E_Ks#kn$2ayKF
zx=c9Qs4y^L@Ver!NuV?-m=S1fR(!n*uC*wRjRCV&k^T`z)~4{@iN<!tPTRAf9f~(A
zq1dSqe2T$zDbD{6&~63W1`|DssbVPhDik|lw@-0~>Nffn?(YG6K+*pV^ad3Vr=d5b
zSUn6ftT?z8>LUts7)EwOafddfHx>BrFWh*FIqRT4rjS#BVO;U-TeJtfrFd%!CMFas
z=&^NMvC13RlZt%0yzVGQOi-Lsytx4)cNGizfIY2fqmcPM#a<G*uZZ!4$OA=bIGlN?
zaFhajMzQ{LOxGiYH$5oqmAb3o9F&PqK;2P!lNRX*l||oEIQ@{4MXx0%<pNsjI4k|A
z9KuCevk!i|Dt}4?wwuz2UJLHZHcEncD3gB!=c&xwixD1HuBUghm(n&D#9JvYgZdHW
zh#M^VDBGyIz*qS<Z7=<lj%I-QE5D|vR)EqM5m$WAQ5kgs=8q|zXb~BxoI}UQk1H$b
zmN}t}q(xPb@{2m?2P>=T!@eh#X_R0LQR=7!GgSE+)v$yqKkNn<uH?)>BtrQ@0!XAX
zhX+ehN}pdqqLpF_w8bbzQp{Sca$YT_%ND0>ryx_ja+)R~LAlxwE+#7fXabj^{B$SC
zX=Rr)2AZj?Ylo$?O8rfkKd1bjuJs&c?rwnQDfd!PEMK{aN~;Q#!v|oZLb)#zb}N+^
zzlF#Z<$IJGs8WiZL8_HJ`h99_%4g`9*HvZjx6r6no@0Q!ru^d}xH{!$6gO*7o?H*n
zMkOZzb9r6aK>Oh)r5hClG%KrmVYfxOnZEqdro86^OYO=d*%(rXGBX%c(y6>a8=fxZ
zT1pM{D8uQ!+pAn#0I)u#t=Sc5{mR#9<u{<bbpZN<%1>$bhLrsd&=^tH(%Sik^7Mc4
zKBf0j^o=T?T7<?i<(x}!bX>WFf~B{VBea5^Q1<Tu%57!%S@caRZ&BFpj&iR(z^0VH
zYvJf!Ws3klO)G!0(fatFGJiSP2g(XDupcU4pfu@>(xnTckCZWVs?A>I#RH6k%7wxY
z2UXu(gxiNy)3lRyQhi4eHfPn+Js>Ws{C;4%se+bbpzf-96dCkTou?DQo~naIAcs}k
z-iErDYSj-m`0cGaMWGxY)lc_e$yZgJ1519YWnTl^U-c^G-~&{#oghb5vX$`ZxN3MF
zES*pd`~YWyRF~;O3|6VXMc+wP02K#@sQ#cOLAdHk%4kNY-qt`QQnmSWG{&fw&V?7T
zsxl+RVB%Esk3c3-)m99HNvhws!+f%8D}|m;sV>ujnl#lZ+DxUZoQlwwsj^Y{I!kr#
z4n(q5g)f3Tr~0lOW6DwW(EW2>^}_*x<*BxwhTVLXZ6&-fP`z>&D21w@qhar&sssxf
zn_ZFWE&8HGsp@6|S}&;{B!MeaN&kzuss5y(e}$@vPN-Z~McTocD%C%9mZe(tfRb`G
zs^2J`byamv0Q0q~DM}q&Q!RN9T!TtR#R`q8G^+KvuKIy?A}y+w41l$&np@$_jy9Fz
z6xdEx_)GA#OBF^jf^O9XO1Sr^e#wG~UX^q!2HK};pqJ`R)%r*@j;h`|2az$=eHzTT
zs+h_(Z>hec$K8agpAO&OR;{H~;iRg=PoMmvt>i7(nN}?`q3xb(dng>duewFa$_FZL
zImkoRV^l~sqtd?*@<{c$0~+nsTj=D!gZim{G&-u^r{%>#^~<{fc1Zn+Jw%+;e_w?;
zXLaEUG`grqlQ0BVwI?l5-PE@>pwC?$Zi~TiJ=FVX8||rf>VWyfYA&72_fntz5yV@4
z>3L}Qstco_@256X63t(|n)1~FYKAk&QFSj>S{ze{rlBuTy^T)W9#=ofK;H><^{e1c
zs{f!}REYY2OF%-^Hd---sb`;|H%+*DKV_OD)L)!}7m?~d%AQ22eW^$-T0KHHMT~mQ
zlW2@pFZ~Gmaq7pO#CYS?&(O*zK|L6aA0koRKyS}vbr2Pvrl`A4fTXGyW<ueVy5b6;
z)6`k%5J^|>xPit@^)Ej?t-}?ozRUuft>zHS8MW5}SURhYpsoEm^(5s#a@2R}n-%BP
z2mHoTShlKHFfj${fF%GcRNvo?DZHruGZ>^;{mKYHE~&Rt0JBW3JOku%wZ{=?SE%Pk
zLgBJ{RwlSg_0|L^Tv4Z%V0x?6>Fd!~t+p)#sZoF30CH75RRQ%{^<%U&yQX$ffz+v!
zY|fzd>gT@2{9IRirNfyf^_P)AYgQLf%&|pXJ^&M~>hu;&Q-}JkUT~f2jr0obQqQKP
zO1HW<4C+1VFsjM!RhLuFyidI*50d@r`@duE2Gm1s@M2KingP8bwev6<ht&g*DA6~f
z-dzWn8){#Aa^6%wZHC=(^$UDBb6Y+B-y&Uo{|_kMQQPICZ%VzV6bg6MD-K|Srqw%_
z!qPqU*)8b1uQt$;u?K2-5E>t<KmGz1X4K3wG(J+_<X|ctHD7E4Ij9+Nquuc#O#u}=
zIB9;Tqm#~>8{08Z7fo*+%)4r4`~d2vk<fO}U2}#WOCFkX1wcJDwX47#)_imk>PIx6
zd<qjjn!Zrz`Dzlr0P)l8*#qLQNub)p0L^lWga>N8p1?SdYaH>iwb`A}D0g5KK^pBn
zpapAqZs1O8eExumFwGzZ6~Z-3e}xwjn)#J55vj>3fWauuPzktb%^@Fv#%QMIgNxNH
zGeaRxQ?ddI@fyEyfF)>hj$pirnirpgUWR7PM-Vx!38d(;EmKoK@%1cCkrz6%H9H)D
zc1FXXVv4hxO$AUqr|~R+NRDPB8-AbHoL>WSLBo9?Bv<3r07vsQ^W4DYYudXYS)i$-
zE1^(xWFNpTYG!i)R-`FC3=74Y|GA*CL?d_!!!5OG_E5dWB~8vMSSr)_o&{H~38I~7
zh34ccz+BeM-3HN0jgD&au4wGHVrW&G?YjV4tqJr+Uk&s?u4+Dg8zyQskxkIMrg{7%
zMqj6Kp%e7=n#B~gZqPj70lHE1o(_&)*Vz6!2ltyaWt0eL)~vjT&KAweJs_=`(yyV|
zrs?blY1b$oz<h_Mg4Pk8npPKB>e9GSEmgN>E5%oOG-qg=*Q@!BQb2tg-&7dv*W}W1
zzX8o(RHreh$*TZ2q#0NT?}s(FZJy8{(M0Zs#tqFzEu6ZkIVlD=s+rXR(J{?zdMAu)
z7$3s!EseDvWI~fhVdLAHHZBw<HGfQ^@s5T;5sE2|H=R|!t9g$Or%h|ZE<^I3W-J0C
z4>hT@j-SyydJbcGq|xl62(hE~x7Q$ZP}|lGa!A`c2;!t2?uLxBc6J7a=AvD)6KJm5
z*_0G<)84hiK;5;9_aW(_-Tg8|JhcZtfWl$z_H{7fr9DI6BJtLS(AxEg_VX+_>ZA4i
z3JSj36^)o*KW*~@`X^m~Z6Kwdk7<9Wgn6LW%@IBw*M=>G#tH5IB!~uSKZ%8jVC`}`
z4RKQY*<3V+XusP4kx;FMHV0u^Cgm8ywWcKii_iwpx;9d4Psy$*?eVwaeYEx^75ZYd
z=V>JytGzF$b2tfF5tW}OY9;h0PSU#4Lq1tM@HR$~qCG(0?n~7+S}}@K+Ko>@GEK{S
z59ZUgXZJ!RL+eLdh11%SGN@;2-M<2trOg#WGFuxk3zKk0n=l2}&T604LhqdRg&s8K
zXm3)?-F9B<RuAk8S{4-?<!YI93NKIlD!n%IwJ*>Tt3dlTo!TnYhWo>{i`xE6P%P5+
zt%Jd0?P_|XmuNkf!(gfQF$NkhY5(~aC}rBZWAMIQd-@BgS7^WVhWX1{6@5~nQoBD4
z+!dSF+y~Jr?H9DzuGYSO2waV}ArOjJwb^tUyH@)|9}Hg8-k%SRI<3zch}3J%b6~eY
zyY~f<My(eGeXeW2^#)3lcI}@q*sMKR2fY?;&Rl@CYFjBH+NL#Sps`*1b}PU-w6?vp
zVC&TO(DJ%V>-a4up<A0zA;}(X_7=$WYJdI|zuJKIPrCgFwH{$GF{EYEx_DUo-Lv3E
zv>(y(;)eF)Q&7LD&7ej4s5Xr%kjJz;C?7noHPTAymiD<r@OMIcjScAA+Eq4sLQQHX
zsHEzSc2gi+oYJZt!QIuiQ|4}3`vq+P?rG1`L+HNN)&cH;_AWiFA8M!RxXFxmbTP0W
zX`i9P9QHaLRn0i)9=Tu;j=Jq3XgsJ}ybJ~p>DE#Sg_Ca0Rk-b}b4j)V#zhzY5A3??
z>Zk_TO}B^w9qu}><ACwdb<%zBsY{h%Oow$%ivjATJ3yZ%@z%N1mg<P^DAo7+=$@b?
zs;}<m2qgV<FQ=l>U#HpxE<mTG0M=1m-W=#1)4fQ=i-9`V5GwXOuKSI$11EHa2AB`h
zZ4HKt!8)fjV4u{z><#lFx@Yo0LUmJ{VLnXvT0Z;@*ZuMnNQAD1($kT;TnaSA=$?v(
ziCEoDx+~&zadCi-*Xh=ROVBy-Ad;wiM3Ido-HxS{Ax+k`z6&-*x4;aTRNV)3yzG>2
zfD$HYIwyLdr|Zg#(U_t8l=4%jb#v$_ai(s?VoYh4F6A@yW$SSGAGexLN(E47b$9Kc
zcTV>&O>B-Xf(tLs>*{0R+6CRs66odX-uMS*ZFxFtHin(AvnfCdbbot8v`|+^+3}0I
z1X@=W>ALCkVX-deJQ_=MDheHy>P*K0b4jQF7zWF9I;tKh*ZEQ6qe8cm!daJfzkCc*
zsq3ca`4!!fMNp{HZQKd2TE{Q}rN*Y)Q402|&S^F5*6N<S1&wREzj$b@)BQ3Jq+VA-
z;fDs@hw0F0)D2SA@pYYr>MNUc8wWs|buUwqQj6{ls=IB~&3yxN(Wdi157MslNx@un
z=>A6!gHB!lM;J?wZkiTiy*k?_PnhV_ZRv#FejSfaM-S-!v_N!Fr=bk%kgjnfM2B@n
z*FZ*eu{SU!H+170;L}ar3fl9I>LgTbF{ax>+lq1BZaPPLOUL*eU=zAsbQ|5)wMW3i
zN!>Q8CA_0E&=X=x_qojh^sbIiNuFt4{6>&_y0vct=Dse{72E?|5*1=U)Me7K#TngA
zDz18@6Nh1F_Ih_dOgQM5_rkoR{*_r6+ChEd2Iw8qhrI^kq@Vc%lFs@-ihsH2-&z9{
zSN&t5&~wuZPEvWlyIy)2iXQr};?e4<&shrdhxKK3(D%|W+y)JA{eHUUj_4JC!Mu-t
zYX*Gs)jxX*jeh!N7a`)WKQRwr0s3w=EFIN*Zv)sdeLYpP1nM0Rf*jZPy#u`y`a$}c
zg7mugDMK2p-%5|BlX?Rcr-bNNyadot{mYBc7@>Ee;7O$Z7{$1w^fPoJ#_D@$Wge&Z
zp(@;XeUJeDCh1+3nBZjn_p_jvqW{eS3fcON|NQ}(ehsBY&*~#7!go$zK{eMo`jFZ5
zZ+GYQQM4VppnsBHxVict=vA4gFQBAzzWy3jO%~`sdIFXT^*L(+b5U<Q4@*V*oAh8T
z)<63ZES2c9X~$El*H9Y&lKx^MM9TE1o`6WXo+}1Qg?=3c#V_kmkV2)tX&vlsx}x{c
zL8eOo_cU6o^>-hGVvYV0WsI)sWBM^swfd*>;LJ7s2Fj(?>0O=%Ouha#9TjZQTh@a#
z>P_KLxURo1!~`|z+53UntZ(!C@I1>F_!f{m^h@4>^PT!{X!F>m58%P2Zv9)1knhpI
z<PP~>{bFx$efp2f0NJlkJPB?<FO7h?LA^g^YKHXIUW{*8KaYNo5q+l>^KwJK&=vmO
z)PLd!%u)RhZE$5wZ!QNnt`D_Qo$f9D6Wbv=q2Ejk)!TZ*abQpC**8J%=-H10ZAw3o
z2upYMPc8yCtzScRdH3{BAAmFW_3wWNGNVtUP{JcU*B;pRhPSDF)xpqTkC}8d%=Lkx
zgN7&0!<j?)<OJ+F8KRfbw%FOwvjd<mhO2Kt)Yb4w8Z5aPR#Ixn-SAE_&^!!DoiONW
z=*mLhVS_Vet-K74wBzwMgwQJCh~d~WfchBxDBSLAn0pwUpCRTAy8I0zl;908tfVdT
zQNyXv;l(k-?|bOX{Ru+}y(5AQVyZk0HW;Z;;G|(91TZ0npK{@0sDbepM8XVx5{QHw
zN`?R$Vc1PDkp}YzP>3>wQM^0aFqgJwF@}3S7)z|-_jf?z46$KQh&P1NIrjuZF~uYj
z4db{cY<5WoGi3yl4QW)#mtq)9L}#jDzYy-9GEBV$jWk0BCDzgnpHYcqhQX8zXHFab
zd<w(PG?Z0<%QEo3hhDZ}!_y#V3@9kTJ!KgD6y%&?@mC-@2Jtw^d4q-at``iVyHK~~
z8uBLLex5;7iq?F?652Z#80JtZLZQKf(p?t~TYdp(ks)k7Mp10oQV5t5!wxI#mKt*I
z;fK9sXd<7=3_J?{l^Z^z{AYz>n1Ude4d>24q|$JVaza-Oo;+|>hM)ezsH<%T*-MzA
z8pA~cMtIfGG8<mh8rru)|C-^L3I^*8^VVY6^@g9Q_@KeC^*uB;8lIy3&2__>y?|*l
z1knA{Y;fv>UW;KLy<1uh^Dn?sn<0lH2Azg)_Cch}aGjO_-G=yTjI76C>p2YlUc>h_
z@U71<kIqo_8+K7;`+&hDg8rbvo@zaY3?Hn4{;*+fC=^BvzK`J34MQdUS~m>?gU}l_
zlu||Am|^W>P#-rmW}xqu!8D4#2}AT%7`$zm6$`LQ!!NU7?~Y-=jY?pr3_sB0@t)x^
z8T9WPI8>SQz%WQlt%n9XPl(PKUK)h?M}|jXm?wLqOFxK%F)|1y9F4!e4!wiMdivVL
zA>+2$aLvgWLKz}wqnM74xfsXj7IigFP)f<o_$-xOx*PX=N(o30qxyf4@ifklf{DXM
z8CAM?8E4jjcpK*v%n{=u3PJi9U!wyTzQ)1V;jf>ugA%U(Si*t}Fup|j>7&N$SD<jr
z=tGaPKw~cDI*uE|6lgqQ+((s?LB_u*LmO=TF@jD|pEM58>mbA!K`Yx(<EH)S3^S_t
zfeSa*CjdLbxV!?5k;ZwuF&9xrGi7L_jla-(GsdW*Jaeq^1l@6Q#!#xBh&QgGBajKk
zuS!4?jbCiRG$$GNy$vqexa$Q#rx>5_r1J!+#x7clpECX#3z;;de+=}~jo$QCstjW#
zEhtVKhv;6(G_peBOqOwkQfb-7v}u?>W4w%&qTN~JAC&7jXXMe>nR1LiRN`{pxViua
zFBq5jpfA_B#T$(U#@81>z0mjp)wS9#8t2c0evxrv9%PD*pHUq^iSg48%w?(ZAO!+0
z8S^g#w9L5J2Yuy6<3W%LV+oa3TsAh-+q2TxOM8VY#t#;Qt1_-<K)u>n_ZCdl7@t^)
zL0mOTC|y-+oTL}?HDes*P3vq%9WC7IjW6_oG#HmkF~UaU7zI<V8`)Hc)nruCi=^3@
z|23RxF<zu+eyj2KO!T!GKcp(OcH^tGAn!0PrQlJgkw>L?UB;?nc-U>!eGcdz<3ie7
z^%~P%LHdjfu0yZiXnTjY$pglMR5(0nv{3YW$XKm}#<1~mD!d;t=FvLphH(uYg}G_$
z%LMkQ@yxGqf6T~m1sON~Bml}S<AQg9GGW~HD#&f)zc0bkq;YpP^zImU*?~+M@t<3G
zjT!gS8hF~c*+y@dd&VnwFsA#)nN}!1FtRDx_t1Fs2Kr`<=idj+Bjd6eSh6>LM8B_t
z=`DI{Ihu~0hQdM9TB>e5WLidds*_1=gC$qfGBq0AOkt}b;%;)I6q<+W93?e9O}|s{
z{jjNLE3sZC$%ioSZThwZibqU~7Q%#&>GwCF;cF_>qtVYaRfGxlHw{pzFTgau4&<mw
zu0Z246LT0O(9}5$h2y4FT6CW<jc$VZAk%yF34vf!(oq;ZX{w}R&=8Ye44*<xg-a*_
z5@ss>5*pzq-*vDQVS4%!e2O%E8xH*_)8?JvqD?FILovqm1XbzAnw%*l8fV(=2Djr)
zFHo){!Nkc%U!v(Xs-a6Vsp;HevZ*#6Q<-84p`~o9X-_-!PMP$SzDYCv_9wmn(oJ4x
z!Dg6NOhNIq=~W#Z&NKy3^+uLSwE{5Nrdd?oc*ZoFO54twN~$oJbEa>n(U)V&px6F+
z(*&iYE|})|p)c3Oq;oNOrfalU$Txkl80HI1%{qt_nr6KKg^MN*Z5eDuCIbf=#isvJ
zdcDMyG761SQ~OE`=8|bv7BtFCAJH{iZgQT1NQLP}5=1VWe$xQ7%CwLY%+;pyREX4=
zrtg5eYI<`aL~2c?2Vmlw>B0+;tTTxy+FNh>-!crM!PNRBM%`#Ly+=!f>n09uwwp`~
z+QBuOu8+Y|i|NNF!L^!R%mP}QDe_&2w407^226*k_7q5`X_Ri`E>k1jaowhdd`xhU
zX{Hg_y{6^!V5!ga7DWU5P1ord;D9OlG@KbUZKBZRkjXX`0EdT7oIjy4VtRNU+zrz=
zb7A+UDTJbtqo#v6dSo|ddQ1uZansH+^xZOXc(62KT1;u*+ooa)%ubr@V&T&rQxrW4
zr%b^V>%MDR?FPMR)7H1a-80>|4ny}%ZS!FMf$2Tld}us0rP9)1#w2_i+#{1SJ%sGd
z`^Es{VCHTE=V-2=%j2MVHWg(aGCS{rK_|1X3VP0F*Ol<X#k`7Mimv7lj>3eS`K|XM
z;%?Sm0Ow&|@H)(Un%7Y&)?u>)Erz|!J3Q!C^){Dn0_YL5{2ve>a|j(O_ce3r2l6v7
zzmM4qGLKPkBG~-m5?DHEK6?X}Ld>=F!VEQE+J(k2a|<1;2selPg7HR}FH_<&((LGo
zz9{n>)#!^huRDUiIJ37M)Z@+V);YNU63mO;0h4HMYlmo(`NEGN$>y)`V4hRVnvL)@
z)ogzmBB#vlRK=8Lo_Z4`-K??#G{Y>X<;H1q1+5G+&3W{4%QA=2)tznrB@SMkF^46C
zJ8OQ$8QeLum>zyP<}La3&9(Dpf2uOeGwXZNnr|KwVAuubS`|p4If~*47tQa|#a3j#
zL50u7=6^(hDKUppn5oq4N?Dpq<~)kumzh6%5|dYMmJdL^!dy&e87`ZTZbDzB`R!a-
zxME(B0(({FiCFa6s?EU^PpdJjs3`EN`SjoDtTm@B2dOuY(So_bT>T|P8qIO9LgTu5
z7X?F_%u|<Ox7qwOMXOrODl<r{SxDb-YBTTNfq8B>=c+Mz9p<e%=yjU^yav)`{(c+4
zy3LR1a7vHO{NJZPd(HDSK<hJq+=hYno83>q?ts~q>VF2!k<UVO$o!lJJ`I~^(HV>p
zGvh0W+%UgJXB%#s-+TsrqvrRhh;Ymt_Yii+%^t}Rxn*8Ubs7`q>aA$JZMITr!=yQb
zwz+rAHpz?dX3D&pKC^kx{AU)txNmMa0`kC|brqH#n!k(%H)FoR!jwKTFa8{ygC%!1
z6dWxwDh@bk@gIiWLzY$aqdQr0DV^nPDXjwMV)5W&E?h02rvc2(l1CLG?v|4;q0z&V
zC>n)~rzMNF^@lC<X(QxiSwe|oZ;L7w8b>USeq-e?+E}#u^|#ES0`CCJuf-VdQOh?E
zVCb0TBAo^Zw6qk$rQ?=U4uC#k`9+7uAj{5tfCO8X--e$jEuF1E4za|rff8ydE&&&2
zVNsoJxa9^dydo?cX^R$V`T8etQI;B7wnke{+pM55mS#JE##+XyBs<O$PK$;_OYt{w
zCdqOr7v_^K+q&Rrie)#2hf*y$j?g=0d7KGLX_l+B^GUb(Q(QK~@&R2yr!Bi^-<D|+
z(X%VdQrQJ(vMmQFLwm*&NEgXjOV5w=bS|(6#=#a^y691K(NaK5t|H5F7R(o0n*M;n
z63d#S(7$9UScUPHSq@Sqak=Fj?I0>FCIkoUE?Y*nK;()gCm$$PmRtXzuiA2z(q=W5
z#>D`;YN<|vp=*|Y7xdLx;^$E+qTaI6A8do=4&79Z76V;?*DcGMpwVPmmkzXM%M-yE
zT8kyS4CY%c>&=jCv(yV<x7`vQg%NgGLMRp3Y5DdUh;&)DH(_SFEql07@3E9!1!k}1
z!Y)i@pCyU%d;OM=u(q?=4OqNBLg%1mwHly97T<Bm3|ov(LUF_rOSk<E%XX@vxM^9p
z0ga=U%~9aSEPE$G#w}mfLgAKW&tjOLu*8?ar`wiY<o2XxHiZoCSkBP0X37$)hHLjM
zpU|P!`<9`fVQ=9BOMExXKeUvzqjkper{58jueHyIq>EKT1s$%|*O-8Iv+^mC>24kG
z1m|ImiHFExYw#$h$;;ZE21#$L6Gh>USpVvWh>!I?Rh9T!zowj$pY_TR`uweRFMtGC
zOMZjbN3B<$f!;A|a0WyIt=nk}d)#_pR|;BBSf2@j+d)<d1yqBrajh8AN$Uez2ZdON
zsP-b%8bJ^BFzcJ!Arfwl7==#}){p6J9cg{k1un`OQw)RAR{xVQ7-M~>5+v5Tc^O3F
zte5@5udr;bq4)ult$r)em14d94SY$p_B{dal=aSQu#;h(p{(L*>yKV=EYteneL!Ye
z_sQX3w)KA$={;jTOTpE1)-AM*$g$4Xf}FRyJq^hV)}vHfl56Esv@PE{-2%M=YhD;I
z3$3?pAENW3^;{N)Qe-`x0hto(elIv*YVA#cGncG993iqRvwAOrV!3r`8zd{NCdz$X
zwkG@oOO@7<lMuOLt*3Ngl{Mlvysx(A?SzRM>v#WcRIFD}8ERK+jeZ=^*R1yR(yFtD
z_ECVX-Wu(Xp*2{y@SxFX6;p`px>ZTB*(PfR{p8J7hcWcESU<yoU%OW8uXMq*Sp}5l
zYPbGGS5b#`W(<0r);YAR?XvC(g!kRng{Pq2W9_MhqrFz;|2ewuxU8!#?yNM+k!h)w
zm8mV$ET6sio|t7;T3R_uo7#F93L*+Bd&v?I5s;xWWbdsq6+sYC8KNSB?Du<K{yCp}
z&pF?7?tOma-gD0V@iXS>&W1z5Fnf2yt8Ds4^Suq<u7haThQyE2+q+@sZCJX$VfSTV
z_icD#3>ptMd`oe~hZ_#O1(8P^N@*AJctgWN=nZTLdmEikHms%;=imm%#qeTigCPof
z!y8_j3*N|vkDdh?-Efak#x@A30C0T61Kbj}nUfoSrtOwJgY5{r4vgcg(Q;&rQX;^K
z;qWuOILMestBFI533m`@M#c+3b72fndCy_Smy`!|Wz6YA>j>lBt7y3~cI?889%XEy
z3-1`ikK)wsjKhyG7aokrh3Gua2ui?|*iJD1`4A>fGJGi2=*j4z59W9=cog3EW~`vv
zN*~6pAo%3V$Q=ZXA0uEZ6#N;>MDRC&5&Q^t0~tH^q7}sWg^p?jGdPE#cZyN@JiG{D
zWZOY6lu<(;kPTxzXojJ1Mmh!fB5jNVkKslX<2>yoqZwTkeLllDwify^j4$YAa+dL{
z0-dpp$0BING4^hRWISVM96A#ivvXnhJY$$%P>BrpchH%{P*dnLnepSh;9X#}d<un&
zj2CHJc!{xuO6XD<ZG9kV4BH%vXr?pHb3rl~>Dln@GGo&p7*i(0-W{zh#v>}G$z}vK
zKqHs&PCjNPkFhogt$aoVCBzCC5=zt*GIrL&L=nS_E{|e{@i}-=%82>|&}EEORMJz<
zxJ)MwD;Rb2fmz82{Lu?0su+8_pjgegOqtTF3=92S*BJHd0aL>mp@>&4qqG&gI!0VA
zc=e1|sUWI>5w#2CI^)qHkQ<B-QemQrp`^#~O~#6H*llJ+<f5~calrGnnx!_G2i)ys
ztTw>2I}8?Wn(i^0DeBh6@cjYE-Hg4oG3jA=)5fNkF|!d??=zgJjHQpUjpC6H8UA!U
z{}E$%EBxzcv@C_fW5zybs1Go1A3*B~!}$oH2N|2G6mp2+M;X4S42JCsG=~|np7>ox
z7$bY2F~-=v3NYgg|C1Qz1VcpM_?u*?e}D;lrvE5J9GKtJLdB8!D;tsrnX?o?JH-5V
z6L`){$Dg6#!c3;^`e9}|or!g2swnq!gn6zF_Kq^mi_kj8Jl_BRojG$m9ar#Rz7vSv
z<4h0Qjh<k>^)D1pG8^fl_F`VNg6GYg@e54&Fdx%S#+T{73dE1O=>vcUGHVKe62x3b
zg|op->3OtHF$-JK3SpKHq7}+)orUQNV|vooHiEfqAHDHUGoO48nMme8^!3juX7>V!
zMl%aepz{nfi$)*A+(PU1SmvlJM9wjP%0y=zGb#$5@yu`vo+U6pqqpRFW_&PsiOhc5
zt0ggaeG8JzTtfG03NzY-kzHW^N0<L4<}XvH;AxY}ET+^*8uRp2j3S*WaD!+DQy|CB
zb(#4+orlU~-ns{oZ04*{=;tuk2qBrv)L#Hh9y5ksM)^$k3bYECTPfCG$gC~~DP~G3
zX<EXZprB4EGd2gLjG4I~ymICt3w|_P1@l)XWGb1Poj|IYQQlx)VWxcv(W}gwLXd0B
zpYqUI!~AmxW~QEbM1T=CFn?JL*BY72DQ|wAx$y?nZ!nerptFf7nhueh%(YG+EzI9j
zKyESJXo6aqOWWXY8?#6a^S5nG3;h?IcIFZe^gEbg{b1f<Hqd>3m${f0!1tK-y>vS;
zZwvvuo4LOU278!&ltb-h2KGVkJ~M}wo_)+6l%syY{F4F$51F&+oz%~)qo>7VW>XeK
z2AI$M4KJQB|Fr;mkZFsdoYN39Ydx4xnR?oTj4(IN!$3!wGsoe@7<2n>h>kO>tiYaN
zE@=R7lDYnU{37<O&ix>cEMMAgII;etfZjpY)axLJSQGTSI<xe&sBvL^*#o`9tlYJb
zJi^MORJ9vxz3o+abCl&sCHBWy9s!VXXT3)Y{u8W4b|5EN%&8FZWKG`%4KLQ}XW_3m
zi%Xw)@L~N&XUcq8TWjE<Kg*hqRsf4lPvt<Cs1U;rVs+A*Bbep%DfCXUTquYY!s?_1
zQ5ef^DecU|S#Rz^GlEq@G1AklkA8#~k*twUbVjkJxnnTVEMHo7ond80gT%1r(o^d!
z>xHkN9?N3Rfk+&ymJZm&v(&esm%z%o0DsT3{Ap*M$XfdyCNGKgJ8jUDSqCq}!UdLJ
zG2MR`SqD?#@Fmta6+la6{b~o8G?s1zqL*2Fsc=1$wVtloEY`EWP|RliM<j<eN*mT(
z)@S5l9;?CuodvA=2B;UZ`Y8`l#5$4)^Tn)J!vR*p+P@9+RLZ*Q0DEODzac6Ou3!o1
z^;OC0roz-J)^~rRRn7WI2<$7YU6T;K%5tHl`Zd-TTItoWLMV-1%Sxu`a~&&`c8v8b
z))2gJWaUzo#dX%ycVYep>%I=1O{}WD0K3Whfr>+#SugR>YGIXs2cE5!#SDUI8*9#e
zklU=Sv{Y+nee)WyJ6NkJ+;*4siWOtJ$ND1(on5TTJPf9rl|pOR9@d#DX!Ww36%e`4
zQc=|U0n4KZt%s~1SAslZO;R+cpXEvQ6pvYF76WB~^|A`;Pi(9S%JmJgV(69glr>Nc
zv|-k&V$8(|%O@1GH_BQ-v86HAbF^(4XQ?S5F~Q<f&TW$Q8BMo6dkbBb4s06}dQR-e
z_s}}XzWWlKImG^tGH=f833@ZSu-DUW>oD6f79y@}+ud!@aAOy&fy`0%gD{{SV?Uu4
zmpfZu0^-4*_B}*SvY$qx<;mu)LCcH%1Es;e*_&zq;KMF7VKBbz<`*y)Kla6YuoS?a
zy%3HDvhQ?4FNhuZJQRZ2bLe4xiv4d5euEJ9VH?%kgtBMT^Cp}<bssb$*cnfuahmNz
zZ`w%qcNB7oV&A0-#%OkKDlDC0zebDh7<R=KD4b<~;t$DKw)YF*ons$-7h{QMThBuw
zft@-C3+LH#6(kec^|aDUVi!<7cQU*1oDIwrcIMweyU4z~6?1Zl{n0IuR5o)nG}74I
z;}A_}=h0I-lf9Wj7g=l{ieYE7KYkhG&0!Z(NGq3JLOJU^_LA>_na_T16^2y6-bH)V
zLiXm<=qzTRn+cH;wx0kVma;oe&}zGk{ocEfDQDmO6xfw)?FuMXvBxwRQ#Je8F(_VT
zJJ4(Y8oO12xu{`FD7sn8UXTsf>e!8ILF(BX?g6`j{Ri!Tud~BkKyI+#tb|?@dpR8u
zyUBj95n#>i-v*)3!v0Q3tL<CtMRaPqjr|PO>)dAVq$A1g?4$%}bg(BW7~IL;N$Kr7
z>>j$Sy4aR$aKD?~#s%qN7dJz%mwkQ}e7eu}rW>b^U2lNo1NJlB0DH*(oYsVo*fTbQ
zJZ38?NIAfk<iSJR6ZS_GX&Pj2q}<sM+b<I^!|bDjXpOL4R3M}5eLd(LXV0h1`vm)6
zx)3MX(>@2!o|8z`4i20T=$wEfN6?Fw6X&^gz&^wg7eLaP)9Hqm3uoO-C>-X5#=vb?
zPEQfQj@UTs4`YVhI3@H5KgM}R3Q>1XRuq^XoHyz1f1I<C9@-~3Ov<gC<W#%_7;nzu
zf6?;cIDLtM`f}dci<TdUNoz!Zj%EWC0ywsKv;sM6DWVX>QKrI~V9tl1!+Z#*_z*}a
z$F^=M(84%}Xk`-4v7-lb1Sc^MvmVJgKtbIo&i7xzi)hZbl+=vjRL{o<&vI&>g?=n&
zxjWoG$9bOuiE*5ScOV(h$@~=R37n7kz)a-i{0fvL&Z^fzk~#0Z0+AHXF1k}MaQv8a
z;NnHjoNv&3iDOE}g^|XYq`g@>=bselXK*Iz?CoVv6}|Q|IjKx^W^vp+zi3%%`-ASA
zLe8fdAVnM|1?!4ACuwzF!g(Va7D_p3bZwV$0=I*dbL4lytKiH{hx3&j?>2N+aRx&$
z=xWYR`j1jqICm+kf0c8FYMQTccF+-z8cr{L)ufga5eibr`7s+Pjhy#vv=zM0`Q#GJ
z-{AD_glH4z2o=5F<QOAhzM0cV`;Qh5Dg&?r;uO+Lsg<*jVp(mRXIUV(IZd;n-j0F6
zZU^TGm3DP<W>MPX4ktMSL%Pd3@G%VC<E+|)v3GH{WI?Z+)8c7^H$9xidg%9Z?$Cw*
zfK&V)ym-iwgrN0^6G1udevYgTb{}(gP~?4pleYpUo^a-W0MJ2>>JNYpaaPdM@+qg8
z^1;KLMgQWe7~wq5f)}HlkEsr1jFXlEuyGDY2gwP}+CS)A>m=v%p8#Xe)w~5z2d=su
zijLgQKD3;;>TTdTbMt6f<HDWy8vH%XwG%<#mAlOi*hjdF1R!qQmuM1>a*vY1W88UF
zAnx2(>Ej3<+>>+}9_O|Xqw^#;egw{Va$iES7U#;j(GQ^L&2{_=mVCI*^xpF2rX2?H
z<0erE(4YH|mNfy~`E<xOkQ?I#UJ!T9T#!@TQY!Zh;c98?8_IQ{rCJ!*hc;Z{Twf|f
ziQw)pN9SoS>lExpa{Z~4Ac||w1*S2Y8{Y`#8SeX=LC$igZH5=ITyI)Ao#O^n!nHVV
zi3*nDxpO9<n85W;gcs+zO8U_fxqng0D~UVNj?QGR(NoyA&}LYIzBI1Gcd(w$ts26p
zGq^9&6>ym=dKR6T+?(5BJ&XGnm40V)6Dcm2!+nDVy<BeZI3)AAxA($a0rxC@tf`Re
zP6@Lj?!BWJSTT2T2NX)U=2t*Uxte_#SQ+=()lews&a<5aXa#qS3eqaMYYsxcn!8{C
z?q1>c?Lg;M?#5T((>3nGGAPz?8#ypo%T>`gP3pJ{5}{DfWg+W0vw?fC9-xif+226q
zI`>oBsWfpj=rfi#x%=B7+00F*E3Sq6Tmf3QxU>GYfwppQ(ShtXZmR~Ox4A=9dEU;g
z>qBP;w~}6do!s8{;nO{CYd*%*#oa|~^=|IIClKl3o}hepFE@`OZ1=fOdf{&$_h0%)
zC=a-w#6aO8H;6(^kGLx+Zr{(nTMfwpZuP5lSo8^ZZ#5hq<i_)0Vu;I$1L#xkFO+y5
z=E~$CBV49493ACGE(F>bcPZ5yk8`uHgEztDZ3VICwNmAh18?4TNILR1ybeq!UJ2DP
z9pq(G)b9{)JP^d0_hl6fx$wS5nT&1bVcyR)QLen8wZJ~Yb54QGQC<dZgpcufxv=EU
zyOf4b58jGsm^jX>{Q~3!Zw5VoPx7YHBgm8Y+5dM8yc_`(ym={y0OrGUru2$G?-ft9
z0(hcXn36zV1Z8D|cnh6CY{9&}4A4_N_qp&pgm;==&!N2VGcXax^PuNTIPdX#%vS_Y
z_ym%XyiK(IiQ>gk9aJ=LZW;8>@JcqrL=5kHN*|o%Ia2s5mRH&XXU_2s4?`i2w{9~?
zJTGw(^b&YqJ3}PV#!J73W)g1$)&3;&meFe~g%|D%yBBzi>6;iAd8>;da)~!}2F$1O
z9<ea&G~Vt=V5jr`pt95q-T~TXX7ZjWpq|Cs5DQD$ybMZ>=kT;8Ai2Duzd`bNjTA@E
z=Nal?p@3)eIR;wDbJzpLBHl3F{l&amI@DXn`<2$!<vib8(5T>vXvbd3TYCp0RlE-v
zFj&oV{t?bx;l<EW@+xmvG*GVbW*mTe4eu`r6l!^u_aRx&``rlxY~UH!f!D}W#R2*{
z?-ScD$lTzS{|wM3o<|@=Z}OrIn9^q6S=wl|@OJHo#x35j^Z;+=&A9-P+q?zMAnm;3
zI_P!q?v{bq$t#P6-W}e5v>v$2i|<3{Jzl;qEOqftZGvPsZ+boSdU%p45b5P@`-jfr
z^zqbmb3NdVegsPodH1|AibuQ?<#4T^H^(02F>mBcXbkXPqvN|zcz0SLImpZY66!;|
zgo99c%9B&PY?QZ%HYH=c0s2M8c@wK3GQk_8=-DK1ULc4)U-k{`Iq>iGQLTg{-%6jO
zb>gr32l@y37mh>!5Py{gQ|iKBOv$vv`~|eXbmfOFfip+=WAxZ?<E!6<Ge`MnDam?_
zAM^u2-TBgW7^nwdLm~0w{PUH7KEeNu;wzr~{dBs?i~qVF7QFc{B~dxL4}V$-dVTo?
z^v?nO_*v7?^5-|wqBnp)>l_pV`4MdZ4dR>WI|0G`w@zU$LimMLWf00Qr>{7M@tt{S
zh4ag4)fmBFeibH8^B+gTwMhQOM07^+ljs>3%|DibA)Vp(QbgSr!)Mbg>Kwm}Lfdit
zC37Ge&o89FegfZ%{_W0r{sb)|6Zx*R9Z%xVqQ_1$|H?j?Na4rEpml-YN=xsH{9Tn$
zNaeptdy6#wg<_C&J{L>xnHl`=xKO{$*V4-~lm8+e9n7-vyEtHG^Ghjwn8Pn#0^f4^
zGbqxR$KOZ0nF9V93i=oFcT?WFh=1=FkYfIl2v{oNZ>QIMDZhn|be8eI^nrRg|K2ws
z75vWcAX&*zcm+eM;x8|N`78X-XTjgA`~#Hqzs9#kQhK3=UqP9KT7JQKfY$Njgdp|&
z50!vv;GfJztC1h*kJfem)+RV}gTF)ug=T(KKRj&Ve?{xeTl{T1fqk2wM`z>P`R#9E
z^d0;kXexX8aUL*upMQe3O?~_|7h(1R-+yy6=tKUuI*>>F?f-!E^S8#p#ACj0GeigY
zCNW0%gg@kfQ4I1ue?@DEZ+r<NPx%{ZXv6$JX~#ao|9%hDNBK_l-W}t2crNc+XnW^1
zShp9%?1Y4apynsA90lj{F%&0350!u(6d31W?hXmEDP!g=u%~!|iy(C$3>+4)sG`$V
z@E={&M+Elkq30%OejCF)D!4#t?qh<_jswMAFozO+9)iE<d3Idz8)Z&U2-e!d(0fwg
zbP`QZL9zu*FTn>?@#igAz7RYg!Rr=Gudkps1~7ht>y%{m7evq-IY96O{j7n43VQSf
z2^f@`3l{uD&#Y5|cc^?YL{Oa%M?(b#y^stOWaOhWT(GSUm=S_+R`3COT2M$Qav}u>
z{GlHucylX6qXkz7Aah3W+Y(GkjG&#$uFeWJQ)E0=u<b91oD*m~_jWI|J+}_5^8!Em
zjS~gWt%QXnK^Oy5kt}$d9&0Ir7X#qL1;KvG4O|pVEe7wB;3ry~qzX1tIzLVD53SqN
z1xvO;Awy8L6P;Ot*$g<AEr|ISdN~3oT1@2%{-D}`Jb~yOMDhh4HmWTu5E!GOUnn?~
z31*RC*+=lHSl~!Yxe~#L4`8WOkVy4tWrD?&>Ms`*)5TOFNO>9Rm4cQVuv;bY+y#Yd
zfreJ6R|K)N$Ga+c)(`5}1Rqo7b&X(sB%o^rt0;$3Cy;EWpn1JucoZ-V0{%VpHVST0
zUFCJb8mtg!-Vj{93794Un=YrDg1`D<w^{JJ1)wd0ZmM#=CFocO^;W^p4e+8(@J|~|
z+!nM@Ah2C9mA)a-Az&v#p;I8I%i)gT3J<)yf(K#$PtgfJ+X0v^frZW}bPKi?VW2&N
zAE;2NS1^;d<o5-OC4lJ@yhFF!1A&e*NDl>Xr$OYA;2tfU`vvdPC+{B%KBP?XfWR{k
zB2NU?2G|`GT;2;0hXl{nK;)^wpP~%I0uu&kn>ixL%K~#$;5!Y&9uqu6(SmWoRC@AF
z2!d(zG${yt8KCyU!czcs5SF_`#8G&QGMY}p*iXSbC`@=0pofITwCQ&iM*Ij77vao*
z;o4#0;5@Wkh3!;rd_<T?3wAf5RSB}@s4$pn6pjgJ9fhaIg&i$0aY7h4jLwt7BsxRl
zDRiJ>XD{LVb3H%2zr>dM|FR9?nR=iF2py=LAW+y!JFy_)9ICJl7ADgzeM(q+3F;xj
zeN-G1DqJmv!7$<8B^YP8aAq5L5yF)kNS+p&6Ce^PoVyAlQNlmAfJ6)bdImrC8KLrd
zxD+Ft@*O143ZJ*V2uEXuB?>Ul3D3;Lc;kep>Cjia@Nqg?2|`B$^v?_XpFlEEICVC#
zlY}v}@J|-LwhyfoVJPk4F9^$N*K$$#J{`5YBz&EGN);wiq%}>LPe&Hgg@ZG|%MkWZ
z8O>$k$McqgW(o_GkjWDEP$)cG*h&wyJmEsmZ~7M6ex$p-Na(f$V8z0^Ghmen$EfzB
zR5+Oq`7+_tLx3(9uB4ANRS1J9Hc}~khq9wp!rhIS!fIiR8l6{!_0Iw9s&Lx^sMiX&
zh(PLuyqADdFZ}Qmc-A14QW<8Wu!%zE*M(bj?*aRU@D(k7mnPx&1%SCJ9H&H7v#_4Z
zc3OlZ8^F6IoPxiZt-^RSMB0Q}s_DKhM5+t-jj*1=J{`hHPvL`wwu2iXaZi{=1*%;_
z8I>G%3qO7ac6x*x>Ogvh(<nTAU)VMUp7jZ%?O^ADa6Tn~9tzj6q4!9rOaQN6xT6)4
zkA>9~(HRg9N22qI@CW)3<DjteG{}(9Nd7$)KF>jGSm<nH0cJ$#N#~+Qg#{G&8xsZ{
z0qD5!?HmkjLRf2t$fR(sJ6y9Deenmd9YppWkaQG%u^7|jB$`Gmse_`WQ@}eUD&7k{
zXOYVb;JJuclsY*qD%lEyuA*eheH;<l{)889qGxwgEzeO=7ro+-iONo5XzrpoTFQ8c
z6jVcWTognlzb8bUnc$riDS{#CDOxE5nwO|)5-o4hhWEkq5k(zAr>|%iy{!C1Mndry
zecS*`0ix%3V-SI&RLW)riM+PLi(t{q52)tvl;}zWU_wOmsO~FNG+qo6CMu!#ez>Ue
z19%uA3jPZEQKAEMV@Hcr^j*?3qA8T;ixEAbgPUhX|9*nbSdqghoH-|&jE9Lh(M&N~
z@uC$}tD7K-Ohe~+(JG1)C5rYUR*afk(OMl~l0~O!^N=Fia11aPM2||)x+ppnhSnv~
zkF@7X6`5#nnkKqD9SZ59MRtJ65am$5?Xt*W7?v_cr=rlACF*$*lG&mIOtf-D7bvut
zD_Z1;apsAlJVEkBCw>F8tw7X6Z;?XLgZ=QWNL2e5rma}C@-r|?L=7Wom5RJShlw&#
z@&cfhi|lLAsu1xnqE#u{)(7k=(a$u`)uJgB_`V|gk`7Q_6|LC-x37uL`e7_JqC8i4
zSS#W$g`qmpd0O{2+C<AKd3YUugWM2toT1nxYN5^WP0?DaA8Qt=>1z`$qQ9~sa!V9L
z@6J}ymG>dpCi;qkbhkynsljU(UH=?<9ilz-w(JziBH_~=(Yqg@^R8$)oj$rJGL3?C
ziLM)f*)6i2A49W8<emn!UeU`GmcB2tr>_O|iT*wV{Rg5bIz;hMq@>l)Bhg3nUhWso
zONGc|QE>)_HXw?m=*AP#d`hGaiVCR?Ye*#g3MQV4Zr;Eg4vQo{P#6(Sc?-Nz(e!OF
zG$x9(QL<)S^lCX2Cqy572ee6%hzf}9#U502?jY_7godMdCOu}H#Mf_wcToJxXFxk7
zzCx$goyA8fUFafCd=m<X#aq_HuB-UvzaVl%{PiUKbrZYMOXR4y@g0C26DPg|6nAmD
z+y+GtvHK159vA!5m(EX!Yt}>bq&SPVY@Xt0{)SyI@oZYldy5$g5FfFM4)pqpZIoQ{
z6DREeiof`^WdIEj576T+Q2c~KEkR<pDxd_5r}Th#O59H6RUzVel-~#y7e>*UuP|}(
zT{OeR-%=hpLi~v*TBpUse?cQsEcgcIqr^KXL?12Ic;MGQE6$^+SFG5TA}8m>e0s0O
zi9f!A&Uo>J0_GFMKdl5gFaGseU?z%}QT`}Ne1Qp)EZ!0hy%e$QI}{weAbv6h^L0_o
z`4_%j63?Q*K&m+4dw7v1PTvmfbn!3y0h1yAn=XON;%GXWnkkOYgo!M1doW10_|x}6
za>SiCU?Nw1_cBPHIEEHl`Qr3Nuuvd=W*aaI#ZM~1D-vhq!;r05eEU7n67hQs$drl;
zs34(C{6r0B%EeC0VX#8HgM&$^6pO21qDoxQj~}*L+;$i~T@f!?4z#P{DmwdqO}uw5
zNR8NX8kTCsek@?tiQ6eOUoW0N6K*$%kJ44rC_Zr)lGknG5qitt6wgtjw^{svsxn%{
zlk?HKCDum4wN~*;$|bak@AkvB+v1TYaHd`Sv<Mz{h<EM>Os9AYZT#+tlW5&^R~-5o
zEZr0TaRiQbi8H9Iv0FToBJ@3C@lB9k@i0}G+!xzMT7lLl{x}{c9*A4lLF1wL@%wQ2
zkyt(q6aC_f^+0<p{&h9X4~XBSgVRsM!?eg46i=a7`H;AVq8m@eqI$H3#mUFO8xc?b
zg3eKKKSlG$#JlJO{<wG(oj08j?;V8MN%23n6EJ8mVRnHyNPeTGouj0OmZDCQsCVG^
zLCMP$B|Ic~L@ya<Nq!N$aFGnri{!B6=W9T7mCU6&*&~uye*>tSWFP%7?vgZ0I(kU{
z{T*H$mx#|p{e)x{m9(Ce{P!%J@svC`M{yJ{iAOi)#9Q+5i%|5DaJB>6SK{y|u>B;{
zSAyp+`Irjf0wfn`pn;NmzoQi-c}m;fU`f<Aj5k!Wp5h8&5`WtEgi9PLZxA7Q{Y4Dv
zwB*(mh(t=>2m)r5WUf6dL`$Z)(XswB65nv3#Yo~Qly+9Kgev!AB@D`^o|E+M0Ev?<
z_J&Bj<i<>lK0z{l2hh$-ayY<FlsLWsFOnpTrO->3tQ$ouMG`>Q+y%+L|A2W>;uL|A
zU6Sk^hhD1WJmss?B->l*%t^Y$zYU5Rk{9W)*k#E#v^vj}T>BKFS(5Ls047^<)Ey*8
zGP(;QxstEwy2_KR35Q<3<PUn@6iD71$LI?sr-$KTkz~znpcG43RPk9N$sGqNm56@_
zW|<_B1BG(Q@-blADkKe`!naDvlxi@mB&tPlxLWex7))H1nCTxgT$7|s2dR;~C<Cun
zGRF>zb&|%HAyO|{LK)BoN$dfbXp~H+fnJvsP*mlH#PbN|xk+;QYbe~59H1Cwvm~AL
zS|r`iz>8ZpiHOdXv`U64X3;LWO=;B*$=|UM?UY2mg3ddV3l7k~D@pbO=sn5v^w8~+
z<kM56TarwdWshXDH(cwLOnic2-<LeU0wR49R{>fNB%d9F$U{lrYXEyBS<wuXe#u3;
z5FbnQr859CAjxH*_lYF!9ViY;X2d{aNV1;76Hg`8^sSp=Ny94eMkFUFFfl6GZvxtw
zWSuL>xI|kCOB0g+JYN`DYWtF+%}&ywF|ZCwrBu0oNV;n=w4J4$N#MCicfSpg!%{{Y
zL|mnkf6+Q3<t~AwoAl~NU>%hTD6(@*`ePYH+@*geK;1){)&P;?Qs-Bpa6<Yn?H5i;
z<6<!sPiaB~h?mrA%Let9YH6+SBi)>ef%!_OMPUqn(hv8+yub7gT`K|7ee?_olzOZJ
z36hS|TOnAwmCih!l15NvUx-veInGe&Hx$nflXg(7EnND1EhHnPA5i7+Y3UrQNQ{)S
zJ)saKU7)1nRngM<^fkXTQoGNg5hGnmZ_l$*83XReO7m%_eNOtNKS1N8!H+SDc<Co8
zXeCJbVIb$Fd*gwfDBY6=OG(l!3M?f{lPEozB3(mw_62Fn1W+zY-~ABdyd>S41ClCr
zyGO@3)1)(~#xGsEy$LcI(tjyKaap>^2=kfJ7dAmOOBzU@cg&W)N8$J!=~M?u=1L>}
zg!g&UH|U})lsdS>nIh?rbk43=>QBLy66rBL6iTHmAMnbge_aKyT-r_1h6<^%X$o%X
zN@-URm{rn=B3P=HZutu%ydrI-4cb*{)InIfCS6krQX_qI5{k7_QzJ;7bVVK%>ZRX3
zhWQ3**EuLOO6_~$_I0VZ1@nAEI-fpF)Ff?Q1NECyd)i?)OT#}0uSKe*WwPy-RGkCG
zR;i70Fm2NJ<^%M$bjn7Mc4_l^h;~R{e+Umdr6a+Z;5$->l>ogfO<f5u?n#vs5b2V>
z;R%s$=`R#n=#i$yfb>dV{uG$^rSiiN>67ZIhU9_NFCXNgbk_3#dt{UT7y;TZoknky
z$I_kjMjw#MrvvSYG<z#rgVJ!SCK{3ku`zp3rD=4mYFKJF0qha!dwoC~l_pytIVRn9
z1U`*RU!ir>gfwe0Fejz!dC;?$#XJX02U!+fYmPGUefZ=gv)xZb??Kso3OpW?Eu<}|
zvuv0)yDqZX2QUeTWghf?ca;rOlJ<zqbOoJmvP@ct9F<MZhx#$uACy#fm(9Bc5f53{
zMsyyRxon5s6S70UgLhJ<TMFVSs~Lf#Ub2Z-!Sj*5ZKJ!xSGHyj{PvS|(#_>BbNUq6
z0kVe6Ac3;&E6^Dvd&Upg!Ll3wVN9oF+ulHDh^&Q9{e;RqPNNkjGf>%7xXg0}L?UD}
z$nDcIw+~?<Qg(or*-^3`2Vgf^#-VlU8QDrHEooz9mjoF0S=o=Tff*~4(GKLC?1x;)
z#L1TDp%pJHdH|6G*+VJ-Ixk}c!L>wL8a;iIWG&6$CClEVFUO?FzM!b+1=%MQm%b?b
zns#xQWYg$zo+`V)6TCE;%j?ifm(AQqsfi5P6bFc2mbH+HOxaP|ab?LqTmhME+0tWZ
z<;V(Xpt-Ww-UUpaETsV?Usf~?XazDIt?LVAYbbP6B%4Yh^J3W`J$XxH85G(rlS%qu
zp<GsGkIo9&&y-BAl*#Jocu1A(Fzs%tWxRA4ydsOgjo<02EIAXcYqE#0p;aRjQ6{%m
zc9=E<b+RkbaI{_~qf4(r*1Q3{M%mm6pj?+V&_?`*%$~N#O|p{Tp>R`nCjhQB%hD9k
zYmseOj>)?v`y>)x*ji;_o8ViU?D=UxyDeMM2*q}pX$DA#>{~jr(kZ)r0OXD=i4tdb
zWl>bicu)3jEzr7To>acnEi0w^qaIm|Bb@1#^_PR(mpytPq)+xb{jLvWq3dAbq0Gqx
zBYPwhtifFL+hqUD0@`C)c`=+Ckm>B8@kCa885)B!uL#&3l5L)V=u_FyJKzn=3MdCZ
zB5R{%`l###EfdCM55I;N<Fd81)S8ez&W6aO?B(n5$zGoGDjao?=kEkLD8C>_=OOu&
z0N8Vu+g{rP>LT~2yYjGn7A3M=<@FRsJ|dqT2Z!C{5p=rYsQeRuh#Zq2pyQbC^7->%
z&_m9n4fS!kBQ5q%$Xk3Na#DWr2wI-<Ewp~~l6TL7qu%oE^fvR6f9(SiU-`Uq;Q7f%
zZL~-7mv63yOn`hRmAnSZKQ0Fel6TN@H&~wX4S1*ID`>3~BH!}}yioa!Dv&Vw^Kl^I
z@`b+vEkgb>P0(riN7F$f<^OiT(J1*7DlLqbcfJSpGxG1h!|xg+j}(HOmDewS7c^GB
z=ol=;%a^?lm<0LPZ$sm}e9oKbOqAcI+doNu#uppig|@AKK;feNK^({>`Ky5dO_i%6
z;6<AJ`&XclF8BQjqtB2>tOvO)-%3-NDewFZ3R&{s$IzKAw|B;na^$UxU@upGg6_LK
zxuX>#`SR>@5Gjz4C1IWl<vY({nv3MM^g1Y(|6-$ph!Q!&5zSIL_j4$g$rsl`qg-yJ
zo4P`Ng#t8{@<ViaRLMECJ+78JQ|Ri7{B82$syy5clYUK}5)SWc<a49ZSu3xjhhCjL
z_XD8R%Wr%DUW5D?#aSBV9Tdj9F8{oMUYs}NsrDdE@>#90dsDvfCS;oBw<)2}BLCh4
zXt(6;F3@O|f4dfvZSof{LFBgFVn%1XJeC5f9dfY}COYLaDKmIao|g>CF8LcKOjoyj
zS3FR9<Yy?1*DF7~2jspy;OnWr*QQThZfmTD=3{y03fLczJEnpAMBd&7`-5_EFUXMG
zd;-7WQ~7g$0(Dq^j6%gDauuCI9hHAYr(eh9;~qd6m-kX7(1iRmFBqPbn>Rq+UU8k$
zJ`Re9&tVcB75iwOofMnrVrmX55^eO48xAS5Xp`ft*h3|xE{bPsfqhu<3N1-o5e<a?
z5yd+%qti{HruvhkiYp9^`<TM@Dq8M}*J%;#q41;ClAof)3wHe#QPV*J6v^L1GEnj6
zJ=hIWEZqUuf)#F*M>(bV@&kHjgeZFHVHT=r{tm4$MI|Lq!xd4-VLn2!PK?%Rh3z&p
zA{CjmW{Xk`P~CpC;*Ikd#TmuVL*T_IoJP=jR&l!?&crIz_8{jJEB8PlPVqBEU*i?_
z^Wb5ELa+(syyEje=<802in%|cnWTv0LqA!umeva?ig)&)bwRP-0P`0Wv2R1<lH%k)
zAgKy_Iti4fu&u#h(iK~rVIo6u={QVWRs_>MmZ|9a3g)vEdnx9Yt!QyYXO3bAJ(qJ8
z-^W3rK=H$;Gp0yp7ApSsMQ@SfS6VO^D^z;`TB6ubiN{jKGOB?nQ-n$ZQ?BTvG<=1^
zNXyA8g`5GAYK6vk-7~nGo9GZ>jiP1<Ueqeycna_96n7~7Ua$C-ilZ77dp5xPM#Xe0
zoVu=Pq9y$eMQtoD<R-<>7ckD7itqja@0LPC&(~IklN{u>f|m>Rc7@Bgu->6~@d-pa
z6?K#izoSSo!@;|Xi?$5F+*3TIXmgjMnqmdriX<vL=}}xi3)gxTr)fy{6`ut`q)(AY
zH6{-fj2i%bs5q^MYmXGZ-4N+loTW?lvEuWkXbmVT=rGI^g=Zefpki(U$dF>m6xe&J
z7^nTru;S$%^iUX4xOPHgRPjjxK*tn`6u1~y)V>Go3B|vZH=k5Iq*$ASvWEiqj>?cw
zNIEHxQ{>KBxjzg%7v-rE4DGOT39Xl1l{SjL98q?eVaZLI@ezo-Qcw;B4<-Kvh#Xf2
zZKFzgPv!kBaLP*=R00`q<$xG1ALWv*FyX7rx&~1{CI2II`YXStqcH)>OuC)|mFg{U
zJ4o3~vHf6W(rl=oQifAlEkrpcg!xeAvvdR~OzA|WW#P(K2O$}uELjcp(@G7#{%D&S
zshmP@>L}$G!C*!!6X-2`M!8x7v>4@`pTRq;TtMmNSf%#=>00IEpMVypETt-zcx4cs
z%t=sQUj}E+D<6LdltiUTiOwYDG)kBzE33alD@9rIEm{|p0o{PUsO%+7+a={^<?u9B
z*;fadH03oNW++{`gQDsg%4tmiy{!D<Ie=y>qbO9EqufG^!(65GHJHy+p4tSGuN1BY
zc7gJfM6?Q(Ua7z=QeF;)qs7W3sxvN8Zq9*7sq*bJFjS_jp*Ll@O_`<vtxztx0aB@q
z;XuDiS(*yF)yhHohSC*fCxvvbDvc_5aZP#qJ7Cu+Ss4JWRr=8ay-qn22EBUa(Gaw*
zE3eY6azj}}<y1||Zd$_JRQlwCG%F9#^Q}d>cnw5uDQ#u+5xrKWjq3f|l!~VqVTV#W
z0cSdu8|`8Dj*@W<A`g@WZvp$E(nPV1M@sBIagi&TA424b@*{e>4=VT3H-d+h(T%Y5
zR5?m7zF}qC0<^}Ip;W3quJoD<GNE*%7`ub2&Gt7eIjT4>1I9_Er9j$2Ro?)}A=Q!X
zKyy|JY9M-CHG}rjCsZwz89AvEu7-I}RRx^^@=|TjfF*C$Y05MEs1#Hj;;ULt5d=R~
zz;#&gSG_+Ak^!neg1`$@DQWi_q#E?3w`s8I-)8ilQdQDihN?Evg%PIus|3G6xGK#R
z*byo=EnZHm9NW=~RGp>g%^B5VPw2&{`ZK{ht9p&1#j&c?J8<-z%8%wLPBlWsg7K<l
zR3Vd~axa0%c~!~<C?u*v#B~29sa!(AOji9qA808m_tlWOpxQyf!HcQ|R3LXr#czR6
zsj5{JugOrYpqnd8C8<LzTXk+TNRDdJB<3(zW!sNdo~q&wF!NRMzhDvyRFM>PDpc)R
z1I!}T^YqoQV%2xZlG|pMsN(4hN2RJvDq|>9b^Zp$a@G64z;1=g?F(pBs+i6YsZzOb
z1a`G*KYh07ippq0>#E9H2i`T63*{{9RM)~mnpH8hh;C7>ptSKV)fzs)T2*xiFtRq)
zKnB!rtCqE)W$RGg`Wnnm)nAPey`$2Qi+5G-Okm$rWxo&7r8+GDuUq9n>x&-MgcB6*
zt70jr->2$vg})C}%V<geP&GhP`A9WC5$5|<j+B^wtg5I0=71{yKe+Zp)#i@Ypo&3D
z>LHt|_h(GauxdIT7adU@7y!(u%J3(cW2&F1GHzV;JPRY7P(A${*psSlMC{eeXkF%@
z&dLSPQT@CD>Q3tJ-=TL<&7&~wA@!6y@WNSrp&OVkYWrW|{b6+%U1YB6%YKkNqPD&N
z9H_hcEvg$mt}Yt{_6fD>8I16x+Hn_np6d4<(CMXSQ|#DVy_|}f{nWY57>vK#o{|Xx
z>gg<C2dX{kY*>(5l@7gNbqgQll)9n{UWBM0HQ=%gRqNgcO1RpE;;a$sjkX@hoK_c7
zzB^J~zX|$L>KERE`DitJ9DbisZ==O@jCy+nV9u(C{s2s@`nxxva88{u4KQ(PqX{HI
z?M@Gh^XhFh!HMdPW}qagQ(S<Vtgfd$&jt1UTfn@i&aQ?Rm(;H5HlU@dPo+U7P2GDI
zis|at?x2;S4j_Y>>PX59WvS;kW7@LSi>SmbN3H!BFuCeO8{k@=dIqh<^VOfx$&C_q
z`%273srr*5@XFMcbf=fAuTbQoLY+JfyehSk!V1-D%Pm?+T~Xhq6Tda;lk_FFTD1q&
z@zkl8bV0FRov<5YYEVC02*vB_Hi}!`Pz&iaZ<D%U17KRztKR_cmU^BUV`)_{m;!}1
zbt47jZmS1!q0p|Lvjhqq>Px>t@{W4g50ZD)-KY!4w;9w$HDGqBzoW=Ww|WmP)O*x_
z)3>gA)hp<NxUZhO7nb_eru~q7gr5?i{c1MtLLaO5%HZ~Zy3-EWPt*%L!5dV+ycp_F
z)y%1w%3*ag<pM|4E8m95sJcsx&N219ZvbtZRQu*a)LtX|{}xpfz5u<Bn!osP-$}EW
z9@+;r0p2k0toddhBwaL<z95G+oClC})eKTt;)o_R3X;b(RWvj1nxCkQ(nBMcz{BI3
z{tSqm&^)$+oYdHLLfuodiSl1wHcd?}WPCNgG3fQvY@?Doe@!O+_5m6uMHvD$?=C=R
zu*P&88mBZ@b3j5g(*r=lG+pyB-f+!1IszD>ksrb2pVm}-3G<PfxwSxv(wu$+yfd28
zRp^Y-9G(GtXEn3w-59H}Z8`y&bDGXipctp=q{n-L=9jl&@VutN6`hHi?`c(;q}iH}
z5hiOaG+h@pukFCBU()m&0h6kkd<PSprcshey5@BXjAdvZlHJRi<`8(8sp+CjOqRx-
z%6PIhC+~unqgi5m3U6{XJ0n5zG`&aRV!kHv7_bX8=gz}Yq2}p&@QO6aR+uQ(+`j>s
zQcYw&+%D6&&@Wo9N%#<sR%jHoGp^KRAA?Ah#w85AYRy}2P`{!%Muk~dH8Uu1a!oT4
z3-dLa)qm0YvsQCsJ2dJv|CNH&Yx=2bt3mVWUuZRI3Po_{x~7wMUN<!FtO87v=07gX
z-_-21fHZ6Vq^i|hni6_mv})A!LEARXokif?)-Wj}(ylp5FQ*R82iGwAPEF@V@a|};
zJD&6XaKY49Z37ng*rQR0fZMAH?ZPnbYuqc)*{6AqmJbg!A5$pcq2|YpaJ*mB)((r0
zHNEsg8PMo;;0<Z2Xe0Gh^JOu}uqH7MWJD7{?~_qYZYL~`X#&53i{qMF3QJCCmeY%9
zQj=(-2Zz13eJhv_+Iwc0chr`hf`*f}o4h!vO}2;VA+7mYbUJJIQYnLr_S>^Ce^~pR
z8+fkT+^^yN5$&gg7_ggmKh>}w)v_&U9n*%SL(g6N^<6-FXdP%<bX?m&H9RM@T)ho;
zPijA+7lWrZP!Hd{w9m!BZ*OhxU9^0(vU;HTYJa5P*-u+aCkOnsGa}In&|ajYUV+*#
zN}&*>O;*E;VC}b)@adHHIa;WPXdSyC5~|fb1c}flQOVtD?NJIOMrwr%X%P~o^`#h3
zwD!wYfH|XWrKeDgws9rMS?%&!FdwU(NkPsyt==E4c<o9Ga3^Sg+6GI>+6D@Kr)UR%
zz*sJ5jkGbpsD1PZBfO*)ybXh?+AS5}rD-J;j7rxQ{td7U?dnSufxN8!x&xw_+BABR
zWoadw;Ayt@yWinVj<&`hyj<=6%K**OvLu+Nd~LyANET?*J_IS$zFi0tMcOH(P^_&R
zgF=b6uN)qhYG)h;DbtR2L$X|Zhw9-fwB<<<snl++f`Y9|`&I&ctJeCz3FZ~;0RyJ(
zs&>m$Xk61qe}Ptw_B_pAtv3D&{I1hF(5kdvt8)Np(DG@U->5CV220nqz6^lf&^iX9
z)uf%d3wk%T8%!8>vsOZvbBh+YC~g^Tf)BiCwP{a(3TB&@L8-~x+A7MUwQIY^FwhRI
zilQT(+Ak>Yen%TH8;W<e0*bHS(+;Pi)uo+#9FBHtKl%`Z>CxuD3CUiq4=p?HYnfgc
zQlC~zFN6o$1xsP@q4tL!v>s_w%Fyc9+Hz>U@>sitURDEIQyUz9qMbSqWKf&li4hKI
z=dFdo5p8Y(TBF*%f5O8t?L*qKjcZ%IVPZn7rb?Gd?c^eW+UvHtpwmH@+y+cX-GRmM
z&`I|!y;~3J?$M*^knWj>P<Ph3*tWxO7u}=-L=Wq>Q2NkSw-Fb{%p*F(C|Yj1@N3XG
zsyiwI_A%XLJBYhZM;DuiZqFAGIj)md!^0Cg>jBt3sk@&8XFPQWeu6<S-RjdAptsJG
zlAk`h1@t2E)p^-q!B00njjH_pb=~yN3ed&93YlP?ryM3ib@!O)4AVu<L@QkP>^WdZ
z=oZtu?zHZU&*4*~uASm2QM#q{po`W`q1DG3-Rdrwh|z7OwD4J7_a30c>PjW>_nht?
z-M(=E12103pGN;HCP8=fDD=<kekz5DMBS+oh$iWLH$Wy?7e+hB6kQDEXD{e%QixpC
zZJLeFOS(eZ?x*TDQvqU{&UhVm({&zSp)*6*&xXQf-CzTJ%G5m$hlMQNZxqkZ*8N?I
z&KzAV!p*jsxw@%&VCLykPXZ=iH@67P0^M95L<@DZD70Lp+q4*d7wi6^0+JHlviBfT
zs(a~O=#}Zr-Eg#AS47*v3f)Iyh*av1ctfE|r>EUcweGP1<cjWDdShPIouwMiYr1jz
zFSxcE-82ngYITZN0aK^zrMshEr=%cugD!>##YWxJY2aPg<pe<ghHfg|#!b47TfuA9
zy)p(%w{<}jOlsF%cLc9P_lg}9I&}fG^}3^5G8Go?>Tc2s@Se_Fijj5cUK|0h+ooGC
zgy=(^`&q#B>x$=sJl4&pIQM{VXA)$FbVr>rrl-1g3h@r>K3xsJM|4lVf%#Egqzxit
zx=Vd%jq5zT!JE)AXfZvh6VNl;Uhha#;-KG0C+8gXn<y^fq<32hg@bzAqBe}_kbWQ;
zUO4M3u7J4cxBmsu!}{*&aM)EJL_3Qk`r*|Wnw!4pB(RU_MM^kxOfRD^H@WMps7A#@
zznW@Aj_V~Kqw|FR9jY%nsb|s!;i*rc{H~Y&emOe5^=8`o_~?CYls)p*XN#ckr;nyX
z^ZxqHw?P8*f78$c^?N>tPeJ;Qb1)dJ7mq;Ul)kJEmO}Jh51|*TZ_)uYOdt3QNVxv#
zkLZlhC;oqbq5oZlR;0d<>I9<n4#iN9);CW_=NWwrpEdz8`tpx3(6jotzXFNX-(LVv
z&*_8qfW+x<EQ2%g`Y^h;6ZAu$z^C*2m0r+K)SvwTok{wj8h|G2d6_VuqF)&Y-Ua>A
zRp4FJZ%6^}lKw8OSX1@RMtG5?Ka-ADy1wyisyxroPo)r5mcEY%lC7WpE0{U@U2MSQ
z>g|}&$kX#&F#3G`Y$|sx&=1jmxlmvEJw%H1+Z`~7V*QD;5Gm1jQ>LU;e{K*WW%@=s
zJW#IxSc{QW=r1>*RjD^nL3Wj%w~&fjs`ba0LjQ{X4>V_9)z{2|!E5^O=zo#a=#wZ>
zRI8u13>tO%bSlKE*ZXDwra`~22Bc9xpY}J`^^Pv!-Ovwv1EonHmJjnc^*;1H;%0s9
zcJNyC13JvbEj^1W-COlBN{HCn^udi_-quG`a-&^8dJzUY^n;#IysIz!1g_oF-zM{2
z`Y-2#*R7XPOt?oM{Q^XK^_BD;zWe$$O#toFZ#O~YfxaRSbMa8Wt`e<BdZ*ve>et_)
zvj4~WWs870pm(Fn)+aW-;sBU~diM^@(2)M0aKJp(@0<bAVf|<1>4-j$;>@G^{S>zv
z(;top=(v7&3%r=nU!Wb$q`scg%=U(wVW2n|T27(U(Qt1uM4SxCzUVw?xbqyq4jGtu
z!pw9wO#K&LxEO3J>0HKPLvb94tKr($uyn-mj5jpg3{4cOJ!&Za4=~3JODQ_(ZrJ(`
zS{{bd9vD1s_><11oiJqn3H6hP2&zu;G%V}~wwK{pKYkc*!vGI@K8A!Rkn}V39EZBU
zLHaI40t^>@*S<Ct-%R-uA|Zz3k>G_IzNd6+nBlt$bcP$a6zY#K+&zQN(}oS%n6*g5
zK1v=%8D6AXhG@g5r(yk!VWk)%F@}&ppqw+D_!t)A46`XI7;l&v2+tA>IWI!wyx|5F
zwk8^aGT>5@VXN(XG?NXrUXV#K%p(0u2I&bXrWywQFcoQr2RI!)^RnR&+9_rl{>g%C
zSq8gV;AI>3(G{CxSWm&pT*D5UtvtgS3b^JQUPuS8!0_fI>=qh6WJ09K@EH|06dNwO
zVk{*F?HEPkN)2*4I#FgA4S?Np!<Stk6^1wKV7JncMoalB!{%hPstvwW$8yE6bqbuh
zYItoL$Th<?BNS>3b0`>FYxw&CT6KnlpTk7G!JX1u4Te8Ifn=khe;2^68!l`^>xSWn
z5UOlzGBmA#=uN}Zo$#&Mu#4(RS`6K^AGu{%MztHQhTQj|(Po&(0l94mbO30(;r@Ee
zT8H7>4v<d64?jWSj=}m3)bAQ9DdBj}u#AhJqRa3ey{Wnl4R4~e$1qR<lwLy?s(WoS
z?;GYv!>K;QH<MsKFdY9F1|J%F={VgZ!wq_t^c(uuVc3ri(_V+<fMLA@=HiLr6ul}2
z4Mmh68Zwx^gx#kGz6N^3h71b*jTo{%!^lPrRs(orhQoZIj2nU}VK`yvpuLrC(y*Uu
zAnc8oT7l+doKgzKgT|{=OmN6JMo|W5V}cr@F2=S`(K>8A-wH2WjY*V?Ib!_kBBtBT
z=t+;TqsF6jtm&Asmnvo4jod!8JdFFP!1TD$yB8=Yj1TM~dD8e~8hD;I<19*;co{!k
z3>a@?-ebu47z=1|=WC3nr;eX7><@_g8{cw6E5Nv!9(sYsO$X2!WGtEiy<npkt<g>y
zx6@r1VjL7gB-A*Cex@+vbF{+?H+nvWPZ35bl`5V#z8wQzq|s)$1JEdA1|2?&Hhw^h
zmNUkSPoWWGbpIQ?bH=&Hpb=->v;{L8Zw#OiUV?D}t^dv&pS}l26OC^3F~THcI^{Bx
zjkY|rQjD4xVDO^x_yKfYGM3Q0CDnL&J@nFyfmE%UZrozK4ilG+ACE&L(|9ih8d=8B
ze3;KR8m-{v7+G;p%rzdT&{BbM?`IGxG^VBiw8*HX>|?Rf;)+&@aV3>(l^TCs4pL^k
z{|ekLHx_MxzZJ$ezrn~VjT^n7US(YSI_y;&6IRnp_=?dr1Ta^PKMlgfHKVZ|`ZdO1
zDxpzp44^cAopIx8NY)#_cp0uW7=@I5Y&14e?d)}<`!GDbVf3YQzD>rXAH&2=qaX=j
z&Bo8f;I$Z!tw853W9$$xTa8P%!nHQzXB%eW{%beFU))E=BmaQhHEs+B_C4e6YIxCQ
zOvr|Qx6zk2s6EEgV}R*3o~4}PePh}yX!RLyqnvE!1LL_#kcY-sXrKDXINJkm_Zu5;
z0PKm;a0$FY;}>*_V92<MRuWH*u1hErHEgV*p^X?1{)As<)Tq~DF2;<)#ZVkKTGm2w
z!nl491~X|~OW`AX)8?BXj;48Y;GvUgeLfTpnhN_Na>(@69w<1Q7=OZqi>b^F9v(Lp
z2tZDl_BKM~r0Ip-5b-pH#K4}-%QTh>^WLV67Xj*LGE=(M-!$G1{Q%S5-M|hsxjqCh
z$W*I=WUy)72wJC1$KwGSV(O-&R-q;pB@@F;ee~83H@(z>R)p!de4v~*`Ow*bNK@lo
zbViv5Dfx2V^!y{JC)!L~hcK7Prrj+VOp2*sAJ8tCw$rZpqABiWSh{5TZ8}J*$+8^S
zX{Ntl0BE{t<PJuWVS1DY$;&3wuMo*J?aqOEmMMw>k!;gOis0p#Qm7s)*EGEm=JQNT
zXd#ntYOMq*FxlcV;7y_F5-mE4Ou4%OQ*82}pm&Msd9qt-3ZzQWGE)ovE0uB+_Y`;)
zrq;h<x6*WH0kEq~6O_WOHl+@s^NOjPidV0iLdnr<Cg(AT)R<ONC2Xx}FbBLkQzE6c
z>P?Y0N|-d59G(ZW(bPwuUA=Cq8b<4e>8)OfHkqn(q2FSPrghvc)6PnCwwkVd36VCF
ziw`F8w(0L9aIM`m`2t9XDf1FKJ53k=g7<e!aetxnuIYVy%*;L0LE1@onLOw@(`}l?
zqRnWJX+{TndrfupHoR|oB!j^|Q)VO#J}`|ugr$e3P|8<6GQBh(1MN3`un<@0V^ipV
z=o~P;c^&FcOs-MT8#FDVZT*lb{Aci<nszUP7sIC7*-#iU9j?G|M@>IH1BEe@)|pN=
zjhog^!nX;N9qkq-O+gwc+M8Qepwq$Z_6t08G#~yQ`c7u)uTVT_en?4;LuM(}j5wR8
zaN(hgxt-EtN6e$87=)YoQY*YTYL<Tiy<_IzLZIhv-su2I5Az^x&ySm552h3HC(Q3H
zhuxEAmnqQjG`~VoTrV^KJ#>1Thp8yd$2@~FZ@%WoR4CwQe&uWU<ZtdUVK4z^&lGe9
zn*Ue^5@eoFDYIbnKU9Wt%IrW9+7R<@%I$@kGfn~}%pCI@ya+dEz6pPA5$3t)pm^FW
z?}SFASz3oNMVbFS54+LkIuoY*jG0Xf-57HV#e&Y7L$*RB)~tFDo#)I4zJV8U=AT0$
z8E=ky6($nQ`$B+y-n=Of<`d1IQ9>%oypzJN$>vmAAf%YN$siYO=0J*lT{QnpPpC`g
zeQy9e)m%h}RnpAqv^_{S^SYs*Vb0A*>$16P2VBcEPhSR+EOVp*vzBcxp{m&&^BkIz
zT=NG?DCC*vEQI-d^B1(vEik`H@5Vy&@Cek4%<Jqxip{olFJMe1=A%^7P-=D!glL)B
zd>UxwW<8yPuP}e~|1TVwqyK^VE9RR87-)@I@CQuPnpabRxXyfn@;vqCEuX?*gE>DK
zn2qL&0T{e)&ifW9H_Tf*(P}b3PoK27Y4)Z4akIJ2MrRsY%x(7}bIaUB50h5&4|LA3
z&Fo7xM7PaTT_D<SUO^Gk4s$5Q13JyqHUsUBc|OhTU30(^cyZ4hv<K$9%q5$l&}}wS
zptQ$)U>uUY=Cvo_;eGSpbiT3A%uj|F56qeW(ogcxoUk629+}^t4VixPQaVub*jzx5
zodNTyE6{&p-jsvZpgA}Mts(R7o4|f*4x`xfuz7d^cq8WhqW~K<H&MWH%v}8}OpKe$
zV!@j*zuf?ZNpm6XMeQwxR4e6R`Qra&*p8NVEyi@n5>7==&X%E9KwK<|pF`uYrN0V1
zS4%fV6^~eknCLua;SPbgTYjP#qle{-9`H_D9?rvDcv_t2qUB`?`2sWQZCMr#Fds|&
z5O}_p_Y=Siut;e68))$xr%Z5=C7}^$!4@$EPEJ|ASAm3BauxtP)Y2CL(J;$KT26*r
z9?l17gk^+2Z+6-;g+d0Amh109B+9aZ4UuR|dj?u(EWcB1KgJR!h2&YwK{<vUYf)7J
z^PFY%s~CNp<@_C}+u|*WbdM!i-132a-ttT{T8WnBF99vdQcG1`$(BE(pqOHr{VvD_
z%WH4oXTE5ePru<MOA@_CQ!QB(ib}J186lEx$)lB9hQ*7b<CiTPXdReoSwSz%EX#`d
z=*+gvY==UQ&C-7tG}rQ;4@jQHBm&8|yh9I@0!s=#(h4mDC(&7CnOzLmiY?5$=q$0s
zQ%tqgvNRXiWtJzDp)9vd|Nmy+67vw|D=k7QQ>wC@q}!p|a+6|wS1f5QAXhDpRM~UQ
zV!IpyW{u_3-7ryWSxbwaI?KW&46WYM9DvRS%WBGEG+Ns0!Mkp`NYUaOmgXktH(6Fy
z!I_(uTSjy?TkiY|w_7b8v?^>vAv`?1ZCSn^dhM2PDFoeNd6k}lotBI%P`_j8v^|5#
zxNG@=ev5k+AHwdkT&e_2x5fQWboN+YqEmdmmLsnK?Y`ye9-#GEtl>a=VA)2I?1z^A
zc|dz)*(ZZD{g(Y{Adf9ZD$N<NRMJPPo>-otl7vA^CgtIVEW`9xdTQAcLvOrcO9WM~
zk61($;vBWa--qIu#rp<C$1TBhu})ZYhrpY(6w}(r-ij|K;s&yMJ_~;xtyd^z=46$e
zgKGz^ztA)Akaf)+*mbt*Hv!DWTHOq=!`8XcFyv~T^%fM4So;#`Vd7?O_f7l&TXBC%
zYah4%Sp^d(tmlK#I%(bd3P3%rXDGnrWi?Tl%iG#Ff=(Z+Pc|fdt@czy>u2@(3U>Xi
z{fA&Tz`BGU27%U!Q78miS@il0w!ZK>264(dejBY2>sL%z54FxtL1&oN%N7Q-aO++_
zz(iPQ6+$M;`UQn7qOI%3FnedLyXl9GwTh#_J7@ioP9(-z<LPmC-ufB6#1pM73J)Y%
z^%U++w#sNvnPPpL9$pu$>4k76)vCRRNl3H4MUlI7tMGY<WLOtf(o*EI_339|W?FaA
zS})70p#)yGb+!vgj@5%6rMcGAQdr8fmI~o-zI7U{PYSF-e}fcShp?xeS!A6;5yxWd
zQVQjkSo5f8qSVUo0Cbsk_GPG-Tjg}IR9MF-D^_VOTSW2jD(jC_iCAr|5P^Bc`gI>h
zf7RMW5yxv*!!z)r#ya@}L~5;C`p99Obtgs1>aE>W#@S#!MTg28txqW%cik%Z7z#J6
zA72Hp$-0{yy=nEyf?l(Al9m}QR>$2Sx2)s1f^0Ket#7}NVYgdDL*Rag^&NT*c3R8d
z1n3>>RW-<6>mFaYf6w|XZG^h4WgF4iZQVn0&mOA>W%_!pO|(tFZ$0S*(q}zBgke9h
z4yd8<&}uA$Ymcn!ykNKAdY8_`KDO=?L((>271Or&iM7ZR%t7ma^n4w%Uj7ZBPpz{l
zi8*Zj+Z&=I)=QD#jaq-%4(u`Og$IBcw<`3&p0MtsVk-x`o0QOXv|B`F4o-F#s6x)!
zZhk8!!NsnJ4q_g*I}i#5S3C1MKp)v<r>1PYo85C1t~zSRqBYDhyB_*dh`U`bZFW5D
znjWC@xZMKE=AE!}oddfk?Oy&FKeMM@?C<c&%kBkQIC|TSRzuRqZl66meeL}Bg812e
zK@V$xyFlM{Yf%OIrW;T~>~vIS6l%AO_FrLk%PE=?ZkIa?Ba5(GW`awn?bgz9+eo|O
zScpW~b-aZkMcZAWdfqd3ztOK0WA_{tPM@`#vI^?4c10&a&e{EmCFaaHyD?g-#oJ9%
zpg+M5Mg6#8?CfkT_>^duMRA)XyPR=|Cfk+J$~?vHHOfj|u$!RQ=S4ewLlUnVyOp%X
zOSKb(qBG5I%lA-Ew+o^ed4}B$%4S`*i<=I+nRdr~Ad+R5Uk}%^?QYScKgaG3x^Vx;
z(Ur$lRXuUdw6d}?+pNs8%(BchZFfmqEHf>6`@Zk{Q`72!h=3v>2q+@p0wO3ot}L>H
zfP$#(AdBp>BM2zJ@BIFn&zv*!ojLd2d+s?ibMDJ@s_{Z&meU0{T6<(WnI(Y9ar&_b
z1I=~%J`SRJPM@uZrF^FaY2XT+O7nqM==5qGu&+63e??!3)4vp$Ep=L%0njq1pXs#M
zO(zM>?&VIwbcFbp)A4n%aNB9B8I5<G^i<PX;iP&Mjg?NRZFH)-%4yenbk;g~+<``&
zlMB@e)jNGg`OyX^!y9P4>l8Qv^Nmielq_v>dU^vynw{3N0n_3%ZxlbwJ*PAeV7EJQ
z=~dI=^g6BBI-O4Z4u$(pZ@Qze$ElLiZ@o?-G?ffE#UaE#fBK+P++0{1a!OkR(GjNv
zIs`T9^vf*3Jan1}5--DDa$f~~7lw`j#odfOdtly`k%2eB^u3IArMP(RjIaK~CGlWv
z@Bp`;v9b^5y%?+NA$fp-^Ch@r8QK7#9Au=<h6O*yw}a>lV1&E|$w0>R*?<mWY@zuy
zm=Uc+-%*BF2f#uYdmL1E7RHD^kJfO;Al)p-8S^$k^c3T3${0s5A|`+x$>^ki1USPe
zq>pn&GopAPF$^2k&c-sfJc1W-j8PxB9nXmM1ee4(V}@Qb<N8}bNnz}G4+<9<=BLqj
zi7{^}$Yn-N553~j7z?ik?OZ<fUB_ce66Z7ADD+*xn4r^0g^WVVP8BmAQ(69P#vr|;
z?l9KSWL?3yLU&mu!%l&oDn=L`(5+>x`4ixEj1&q`)ic`Mq0qqCPDzZrjHo4Ws*$n&
z4oDNjg~BM!j9_}}w=gu0^U%M?Sg;f3TNw$i;My4R%b?%E7%c?X$tX2Iw2R^K9qe{9
zwp#&upAqejvGp=Oe-78OkFkepE&3U<bYKrKzPt;CLB=Rm5)LuSXj?PFs1SmTGXCfX
z=0nC7S|&^|w8^x!eZ(l|z~E!XWm*S1Gbe9A(S^C_L-@3txt8)BuFTn#!r8;@T1~eJ
zGa8Tlba&=jdS81m$7qC}%qLR-wvQS7J@oc7D=B*9#dJOla)9~X`%w30elCK)KFm+N
zL4275ODJ4*kQuuIGJecgz5%E|b1oY&hnOf$!5zh%sDW#N%z3e}8^jzEf*fY1QD*W8
zllc<*f|)8eNFHO>(v1<yj4g-xFy;UyDo!x7?_;1RnMY<p?-X<9dvNqLvvnN|MKRm`
z=pA*2nX3ZYS!O~HI?pjrQKU7Nxp+BX5|}Uk48IeZAJB?3iTNibz|J#|RKV^9=9aa9
zxybBKg~AnP2GvTYGM@{FLK<^NAw;e+^%P0VWD0+WGg(Z(|1h##<{65|<uRYxgg!?;
zvppZ81<aBXcu~k4oQ2kFOr{#n6fs{l0Iis*zYq6InAst)be;LrClI;8EL{t<QfB*K
z@Zu)ZN}Jen=Eei?;uh0R)e5(nWz#|KFz-{`vx51m5_*-)d9IMGW=<zBY8*`MROr_-
zJL$bp$E=}*MLp9&A-D$SG1^_-W&TT_1#4ukS`BBKn198=L^IQiW`h>y*)TNTV_x+F
zX=lFqHb@8a;$JY)$@HPa%J-Q~6v69Z&Z2jDFY}E-H1;vq(c-S3>G*OX=m7I9l@bjy
zZ@veaA?DFxcrnbZ_z8^<m><wd!4c*sUx17<Td4T&A@dzG#x%xcD8Y?0KY0>%Cz#U5
zAdi?|oP_s}nTvOVOfq#;eB;bw@GuA$*1xqNyICzX3AwWH9H4U#>jEwQ-B@ii;ptx1
zKQqwj&f4<=&^%aL`h7fE_gEnNSaGW$xu5k8o#^sn)sPnlSS^%V_hyOdUFE}ij^-p^
z)~N!xc91pvJcu7_RV^_6S&7vUImB9?2896D(N7(qfvjDp0Taafp0a?4S+gnAafEg1
zWn6?{R`O}sJ<3}64`4!A=c%0e7;9cIu1qMalL->WYNF>hob@Xmwm#09P3xi)tS@cA
zJjpsld(l%Yk3?`0tY@OYMY5tbuyC3+^<665jA9vS+B(DX+JGN6n$__a492kHXbW<d
z#i~H#IaUfCc8O*A&{@VfmXRv+;#qupeJ8NgpTf~ZRu?7XlUM<ha5S0a;RciotOxW4
zxyX9o3UZ01p%VJbtiNc^y~0|TN*@AAW%0?=G*;sbV5hU<XF)%Mb>k<D=_>1$EQn^Z
z2LFS@S**51fM&B)wEN9rt(p#zT-K@!xCnVHMIY4jSu>O1OaUu{qBw=Dj~=7%8ms3u
z=oPVKRK!}$lKch964stX5XW^^YcX1Hu!J1gEoBW-8nBEt`#)&hWc7K&d^u~zZy4Gw
zmX&r+w^?&<qVW#PycVOcV7Wg;UnT1+x-Y6&?R1^0SrzXCtcI0G(fL}|^LALOW3Ac;
zpYF0gGC-t}wQe~?njEYF+MYDCmW@NEh4pg~Ox$DrMoINn7H<@wZLH<*LA0HfJ{^4>
zEU_yjJ6V4Qqp^!MLU(sJtA<kC_gP{(c+kU2rvOtgYn(D9eXKK|!Ha&Diz_4tSU3KF
z+k-515Kx9#j>0&Mewek%557HMDR)C-gthK2TpVSUQ}xY57K5^%W2_RYLLFz_(7@6J
z>+)9UJz{yR1n6Vd{5L@+SwEbGh%;MEznu%a*caaKW<N<kx-0wKMkwrIzeT0AZtQng
z0D3Qbz;PF&aA)tQvnw9#L0YkTviH*@wvQbwhW>uGARqc(Y~PE}IKYlL2ut4VyKR8+
zVZXE*jlS%+f5CVUvb`yf?8jcv0TF-p?bR64A@=%Mhy<_=i-8%){`xEQ1+kY>9Plt(
zc#fXGBW!mn@Cjxoap2-n_WnS~gs@L|!o)H55LF$7vU@4z7RI*jgk(7TNBZ``arQa-
zywwSI@@8-+*?VcaI>p}h1V{usdOu7=vLAK<>@<7H(?E%4Z=iCh81~Pfqwy?zju(B<
zIF6nD6owtou3iF%6WCj61$dDi7Y3Ot>|fskOe(wiSv01xcU}caXa7q(f(-U3^<8Dp
z{}7;=>^T(m&0;TG0FuovD+XpRdmWXg<*~0_gNOO->T^&pVAoEduaNDIAh~1uHFn<y
zu*K}OA&8c+9S)4}I{W1un7_gPl8$tgvVVw#`(^ARN~PXp7g08%oPEI+1HHwLGotS{
zyJ|g5++nBhhC&7VSIS&hvU}c#!7BEvvjA4j{(~w!YuLyBgoRpmbRN8S)UgX%z}B-l
zRK?c7evQ@(ciFb%0BvN;<ME3&v0v;4X=XQ5%DaU<Hx`!evA?FJQ!9G`Z3^4iJB~xI
zoqd%mmpj<w^lt5D|4qry`|QF9NcONb6(GIr&J%F0kG+?|#r+O;?>N{2b_9is2iYed
zLt}{TwhTY)FuU&t8XvG1{|S*1_J>cxr&0E_PryB7`%xwR7<<cSxCrCyB035-!EWe6
z<0Cff04zOb@7oJ9$)4DPK4;F>pJ33H^Viq#cMr!Qg9SH^V;8-}_i}DOi%xgW;=3^6
z!FgGUQFwA1X@c9wS^Fh?+RqU$ge5P|HOhh<;51Vz$D70Y5_&!y3q9$+oYsCQ9OT@8
z1?qmBMI+Gj=iFg|9O5{rTs4666m94OIcMqN2;zL<pzy+B&gzxWIKpwEkADPnj)wsB
zDCa2supykkX}fWZbDg5>;heQpjCPzeQwzNloLQ6si{L1?gG6$!eFKHloG_~Yi00fl
z4Urhmdwl4f<viU1=s3>!Ei}e+!sz5c0>?9$zS@z@32}!;3TJu@F86uP?Lip4$hkKi
zmM(FIo`e2nPU9w+xWXBsy+A6*^((-nbJFIaFN5Pj2aT_CS~wU)7H0#6O0qeBz7NbC
zj-GzrTuuU&ujFyO=+`RXyi*FUkW(gkHpq4L)Y*=8REu|=bCcGZH#qSdfm6z9rUc$i
zj)0D`lyed(ad?XpQVoFHoQt90?r_2>Qd_~<wHA%loJcMdYB=6DcvH)Hn|4xl908fC
z=j^1NNdxCY)SXVh%Ne<VpQMq~OX-9rPO^jM@J^1BR%=}xeI7_R=ci%7+~>4V7Nv)S
z)9|=yIsTMq>gRO51#W<IFdi3Uh|^79=^5d?OXqS%IW_b)e#jA0On8hFo`Sw{PG}<f
zCOF%o;OHX`|1r479L8e!JIPu0HT?+A+{1K#xp4Qr0FB+;*gwJT<!+|ek~{a}*J$+M
zUZESqle=~Z`un)IMR0#V_dm)sdU02E!|nm@N(yXyb4R1#y+8NP+aQOyqBkHJz-^++
z_CW53ROcSVefJJ94|BiHp-sRMZZd6Ng1Mhl-t#CogZ6{rTtAAhALsfn1v$Z8bOm-#
zax3Undy0GI8n7d{ezfq7<bF^K6Q{YeWFS%8=}j2gIqo7lND#|?o6<dT+!a)`6wl3A
z3G)eDPXnAu<emwnPnITeee$80%<XLiXbN{=5}+5kTc(3t;!e&2xy+rNguW}>v`+z(
z%FSO0m^AKl8_<}}J--Jc8Qfo~BKIoyXam49xr-@(pT#YI6Mfm-xM4IFa9t^iTgaVC
z3D#>|^=Y`~DB^lhS#mMgSq8Kct{Y88*SVXheBcJRbp}97x&IUa?KW5cKG5!Py(t=0
z!Tpt%ewEzMr(wKR+_`N4t>)%Zv0@GP`)g3I<tF67L>)Jr5?W2%GTNOrb5~^otcAOY
zj%M6*aOW0+wsK#fJHL%vSP3uMxkq>)9o%W{Fwx0X4+5>1+e3|g+&h$U?B{+T0!ss2
z0R`3uxoaN4?IG?9pF&}nJM=3gA8>!AP4o!2a~}+jadYU?DdSw_8Td584W%!|JmNY|
zd<L|~T-gH1Ombr>A?D0`f`W}Myj)s5?dFx!cTHS*DlV}1@c6qx+<2R*sAeC}=OnoO
zJY@~^ym*I~K=J_3nF4~|yruVH(1-UM&3C@M8~fnzLEaD5xE6lA?iH{X#M|#Ui(wz;
zy-xS+5ng{J(1Lk?9)-qHUIWFgLU?0hU?1bX#fE+;@AHi?5yn%0gHfE~De2aW;4PtB
zFOv5G-Fl~a@f2W-;%&VP^)tL)I%F5ki@Xh#7~ZfG$XVX+bpT7??N(4IA(59K0Ed%!
zc5FhXC-bIO06T@Zc^H<?^L}^_8W(sQc!0Uc+w2MKOFUB|45soH#6Ufb*U$wnomXQ;
zUj}a!+vn+5d5mDFXYyWh16USs8l8^I<}uy@$>B{)$8d9byhZfslssM}#mn+}#S}g+
z=1u4TQ^NDP1(@qRNdYd<4c-|(ES2&;EP|yn-piCDyvbY6fr)Zn&_#e&@-pd_SH%<V
zg-A7TjS(m{Jf;MawY&k!M%3}v52CN0H;oo#4ZN#JTsWq;@E%gS=pJw38z8N`*>n`U
zjkk3XNINfn9k4ri7Fu?6@?Ot|eiv^ZMUVS<?Nr{;&x@nb<pA$)FF*%*sc*y55YL$j
zyTiQ8yWzzH-otZH7~z?UfHKDWngTxKyw5)YaZK>qDWLI)_a_DD9`lZVkBczL+fQ3Y
zcm4%enDF3Noq@h5|2Ycw@8hpEf$ZmhRSA7BK1U9b1AHGn?0WORtcIiy|GneD^ySCU
z7YPpXzwHK?AOC${IO@+|o&?tp@z<9^FTlb7g+8<&#NSJw8avE?$p)As{C*1K2J`=*
z7{F0}2;K6>_;pkX9Lirom1kl2V=qV^=MS9+%nAN9DL_y1zoszkDZUr&b|Uy&=<H||
zKWYx3&+u2%eG$!{LTk(zez*phXZemd{z2<GekrZiV)+VMlgIIQYoHj<-#QPYNaWYh
zA~A`-&<c{wpF(8-Dg5Rzkn?=;#~>H@3%W6gOMEd^9$)5vNKwWseBW(=PUWvv06LBT
z5=9cy`B~rLGH38(^Wf7}{(BBe#AWhzw06tl`&x1Fv-#6$!JWfTqe`k={+1SyJbp1v
zTlsw794Hp>Kc<jrA)iZo+iU#4!oU^rch*3pm_I!hA|-sw5_o@|Ke__YH~39WfG*`v
zqo1jqKS*h&Tm1e6is;?u2fv8UJA9@)G%EQ2P)ezizvdZ?qMDyasnHsK_&p4?md_mp
zspAj72EBUztF+f^;Cspe+Q{ERJE$i9>4gw!<}a@YcaOi>8(^*cyG%5;@mC*%GwuAi
zdO&yZdC^oj-O2yK2cziXw|)+p`~2#u=<MOox`n~?^53FqtB?OGeR#8<-?sxIgZyz?
z8xQgK&juOhr~5$U0sk#JcR0fDpx=I!FMI(PVVqy~8uTXkf!m<>i0@Sb@|geC7LZB)
zs@=2+a29;D1gwjojcRar3oiZ#4Of911%>wrYUqvUCRlVBeR~DZXQ9tsu!Cx|Jp^fV
z@jV4{iXiS2cqiiy+%M>T3Y?eVmv3-o4ha5eg`T%yCPjLD1gVq|_7$}I!|j8D)TJN}
zKY>mH7=OX5W;lFEkXr>40fI{ud<zuhh5<B4u=7<k9u_PY0_KRorwiD@0_jDNqk<#T
zAQ>V^q4S-`1eITdgbIB3LoZA)k1Axt1>Y{kB{?o=@qmRBf_TccofLS{Tj`WT(53_%
zA!u9=Pa_5IKLXlm0gn!EMhkwX^W-stVA`ae6%^4)v~z-oUcinOd{2AZIKjiGAsH{&
z{38aFAV}E@ltjViSAdcv_>@Yhk_C%?hGdH1&kppR7lcqE`-0%D*P(Dx;OM3$-zC8|
zIWF5}!R%U~T@g%M0mW3olg)rh6QpfIU%Eg-vC0g=G}<Ly6;#r(sZ7Dv#qd5$z@svY
zY=LD2k~snuMH_Mja$j(Hf@rGN$QO*RhDd=x@d~^s6ok>@?wVk=gQn6VfssmWiUld}
zL#9Mvn-BA)f{?`^WrFQgmU&YEbv!wO!_R}<63Ev<^0px66387v)p4Ly2=vvkR4LF>
zuA)k?YZ6{m3ld(yk5(gyb4OpTpp{A?>I8Es@mDXHxZ{9}4T9mh7|dP4S$gj_3dX;K
zev@Fn78=b03;jMV0#gwDz9-mcMq{f$`2V9Q0-t2`bqXda`rIW@YzKC?!2cbH+!svS
z0n8pj551211aoP*(Jz=m)s+K+mAk+V3L=N;;NFm+u?5(}g8g3rW<)Th3;Lr1#{~2r
z3Rbq@B8&;%ZimRYAVvwlCj{@m0g=aosRz(EDfn_dK%Ip(l%U-$eDQbq<SK0V4%{B$
z?ysQdCXAxvWqXBQzEJlNI;DYl3TqReneycHeZm!i8<Co6jfR4ca2aKZeT9<?VBw(f
z=jYJqCu|$S$oz$m9{}Z$@CS-h1qw|R8VV8~dklMrg-fYMB}AA*8^&Y8ncqMmR45Ne
zUzqS!+82Zilj*#}31KDeY)=a3*8=*KurLo`5yB4~br^1>@CcO>o)(_fLqAH`M6tVQ
z;l+3~#t6Sp0nAw;YZ&_Hglh)y)5Qvtk3v6Qc=&0kCkS66M-zpYF|z4N!qZegoh*Dw
zfFY#_i)fpEUfB2z^eze4&_4OH(0vo!z9I~$p%Y}O!X@uQF-`bgDYy)w%eNTJRUw~F
zI%EnHx1%vjm^~i`vxOU{06Rx0zl^>-VG=!>`NGBY*cJ%iO$Jvee3nwN*M#rQhQT6X
zoE+*U!h=*?a$VR+b@exdXKB(Y6R!M}GUhjhoKbjMF8qVaN^S`a6s)){{D5j|Dul}t
zKq`fPl=Q6<juNRB+GxX9BRocVi&~-gMmSS1TwDU|24R{CeRqYW^h#|MuA`~9N!Ya>
zlFh=uAHmQ)VdE?)v<l1Krffu;&`7bjE@3w%L%M}e_CWEz@IN`c=n>9&5*oe2q(Th4
zUwG&;&<2DVFM=Bs-unw=NO)`;d>R(o4B#FJ{b{K-BCMxFBM*i3^Dxjc;h~S<+PIK6
z4`f1kmBN^hgkREm3CE;x^=B~XEK00|i!P#-U%-pqqBF09a}~XQ0Hfa{T23Q$6ZKI>
z*hBPeC`@>Yw);b5pGZs*g#Ds{&p^CH$7m0HK-Aq05pPlKY7igM3o|hYU(p|wa6c%@
zDuru)qAp4t`a494Rlq(ZD#?LpfXMk@aDk#Dx$rGWw25kH4~s50!0r)|<V`dNi(*PJ
z-lHO)xiA<aN~EaOG0}Mq#uO@I&Vh+AQ9ZqQ!bOjFqVKpU-;TZ$qC9%fo)l$LLDMOb
zxd_k^B1ai5xgte>Q*p{^QR-}%h!SbI&^RNS^FBO{7VV?dcZ_IJ4kXWtLg{%wC%WPR
zE>`p<tsUY-4=FtzFZ!(sdI_R|)lf(jRa=0WB&zumlF6bIe*o-)=sCKE7e$}{0?A9F
ze;o9#NEKacg?^eSmwv-^Q4HlxGDYv?;96vfvZ!<_TXd5a(Rrd0T7~9|su}@WAj&)r
zg(6Y+BpQoF<=?_YiRdL-;g*VOmw_u2eNPFro1!1i;mX_=9f$<V9nsVDQmGKlT;+g%
zwaDKEGBu*7Uk0fag)D<igNRGX>bs(53ZOKKUZw<XlgLcDoMut?I1ILkcG9Zuo@l`g
zh_s4kzl))@i4@sDX%{i*ivS&>dr1)K5>-UP-)<4_6L9xM3<|IHhz2<{5%-FA(@UaX
zv_THV0nrPS=o}RNJq@5kqJfnF9Ttst!kGsmwh(qlL^;0zZB+FAk7#@-YK?)&n5b0?
zgX5x0*WlrV=mg#Ck3=PuwRtRhTms2SQL-9+&f>RBu;3yNUP^xpuv<L80y1u5<3SkQ
zD>hPq%U%2_E&M#hjy_;}iZ3X@?Grzxhva^-ED@4k;+1Bgd5c?VRpuk^rnQ!@_!=9Q
z4vK$y5`BK+t@IT8i{E((B8SBLu7L!I{poo>EcR|jpW}$wm6kBU;z#AsI3~^-hfJvW
z11bm(6YHpUFkIa3hrZ+D2D(d5ir*ZA`BUO=DOwdF{%0rpBE_9wqVKfWe*?UT65Ef0
zJ0rGzg3A>x{*HpjG2)XngP#?v8ljLP_M=()yhD8FA9P+2f5t-VMX|mU<Gm!7tpm(u
z@dOu^u82Q>0hUt5%W3bBCXRm+T)Oyc+PP$iCmA4D#nu3zWQx~N*d|MSY#eT9i#=$z
z%@Ke6JTP;`hdg0EPaMI7NWM6c7ODke$2Qsp7K;C9f;ZR1qla)O6p8=rfr(;qU_UfU
z#2;)x<8|@UOmH{ELMkjO6~9n~#xk*hN*-^DKcLFI+v1EjVd;)IgC?j7@n{bktHq0G
zE~yd6?S(?Ecy$IE>%@B~RaY<eaZoK$gLutUU^j_*EpVz?oJ7S8E#enCLGFo#{Sa*x
zpFRxzHt|bzE!xF(^d9OEYqLQ*#gnw>=n}J6f$J9cAA<S&;<Zb05qiWal%ebu@2&w#
zpLo-+kn9&fNn6qZ@smd!038(1u)*$-*fkC^!(z{yaOQ!yIvRZ=;$4(t92I{;*XyCU
zm%f8ECf?KuGA?$e>VXMyJ*5aAiGQNp(PQy<3o*h;aXA&RI7^-pL&Qb0trTwWmNe5N
z<|=WfOR`7ecZZ%oHwlv-wY`!Li(%JY67@5@@Q{Si!{sSi_66+jlLXhn#D0mw8;xF)
z%_V3&AbF1#G~SXWufx%Uk|h*1_LFQ<L&RS)i%PZ*Nd)2WB0y3{sq#R{h!oI4l0iyt
zAC|1xO~tcEB<++Q3zl^3h3HX9LNFW-kz9HOqQ@j5E1(!EiK3NenB**_5yK@VVet33
z<a>HipOE}Ur3EJ?KV(7jl;o#iphQT1eGBTRC3-sJ9VMxxIsc60ZK|t}mJI#_y%@<7
z6|SM<oaDo)Fc>R&?J6|lB>uEpPn7&jl_W_LKbp&uB?<J4rbt%Vz@3-ekiy^v$@oEB
z(u<O2dPiN7EK>mVvLuDhMqH6(^P!L`>7%n_X%Yt2Ri#TNW<oMUa(F51U6tgO!+fSg
zGM^%>S(0z4b}CzPgdWZuiN_I)Fjw+nDjM@7w`i8mmz<{8et{&1B2tBt`&8(2O){*8
zWRb+<6r3rRSP~&pBC+Mb#C1vKLD;<^38GC^spRSX5Gj*r8=!DgvWeE$<q}6Kh39Wc
z+N;ocTcV{3qe{s$vB0j9EdGC#Taqcp&}t-)Q_)x}X`{Y6$!3bO)l2dg<8n7hk`|)z
zu4ERiPZ}j}K7>M(WZv(%TrCpgR9upKl4BE4Xq5y-psz;~mjTi%8FEm5s!vi!(Ug7(
zBOTm;L{3M+1|{<&Au}W?rtsLXWY1NgJ&^qM4akTjgr>=dl2ddNZA|j}R@fbv{Cxq9
z6B55a(D+F5bv7CwOWdCU^rYl26>hpn-D#_{TY8V?DOYLeLkHNs(vVhIa+lut5Un0k
zX&pFE>37e8+b6w1Cp7j;%WL48msCF=+yQBC20*=~?z9K?kuoSAeoz`f^|^l1kHR40
zFBO+z5Qn6(|KU0ZNEe-jp+ITb1)u~;yFY@3Bhv4~X#E*14W~Q!s5HG6iXqZXO89+D
zT1TO*FsX`SqT$jHFGK%?H2pV-oRs?b<654Q{&F3Cr=^#_gnE>8Umg0+NLN#EB2ii%
z21`lOjlR%Jmc~B|FH)qRQrhIaG>48-UXYF;hl;-ikcuf)a78+gLSU)V{FzWplRm71
z`E=<eBb>>QE)@X#s&p5H<uavDP=QdEbWJn#vZX!0Lm@|+Qwh7d(n>0!$d_(^1_}kz
zUC%(WP}+YD+%@Ubi{M3(bap5tuS@eNec-queb9i;QmG>vY?<_*Z-91F`UF)il}q2@
zg1aUCIS3-RrH1dJct>iaB~XQQ%D?cpQrba*iz=z}36N^(bQ4I8R8LEhT4_u*Jgk$}
z<Uy}q>ih{vgVdA4+IOWPR9e&MkjBmj+az^6jqx^1AJAH{Mf!Ck^zTV8P+quI`Yvs0
z+oUzKfZZ-V@)kroq;l%(l-i$#YhBVcG;MTC)w$sAOFL;v-Xs0wE*g8KUFSghqzVe^
z_e;wz0cAk?AI0MarH<#@VQENujH(ZYrT5w)^FZp7h0YOa6dflRm8Mag=%MtT`w$tE
zZeas$T>1)?&rC>NUVz(=q~B7-^keBm+9pg&yXhN8&a!nE(YIR`M`0T`*^M92w^vs7
z|C2_ta~6nr$Wj~><nxqi{{`AU8J|8vwO@9$3>sdt26{;ykbO*dzPD_pKhS(+tLc+6
zzOs8%uX<4C`z(l`j7KjSf7!?!fF6~tp`R&4_H!A?G1*Kiy$Y3i#zQ?!*5rf6aG7E)
zF2Zpc(?rkT3E8WUG0>B;A8vs=B}>nNGZC_ATJ1#20_pKTEz70cV3h3ca_FCty|o!4
z(X!8I#}*?qQT*_%>>COUpOYQ_2Oh@C3{*oDC!0m5wBuzpk6}JR)_Dqs5@qK+(3d3p
zb_E5(lVv-1!NnBWCp2rGm#N#Ke?c}z@8pXzw-3NwlBIM3=CW)Cg{QB`zM>kURN0Rj
zz@*8x(hQz1`)mx@8M18(NM4ndP$Vo<w#^9_FH80*rAxA9J86HABb!ajs$AK!fGK$X
z@?>qFLbO2UJ_hVUSu5RM*JSedVYf)uHxrhMW!qLlqeS-0T8!elY!Mxnxgonxbs42H
zzgn0mlfAeB<fiP#LNu1kX3%^0mh8-T7*d7IoBm*>QnrZV5LL3f@8jpKmYr(=w4+8=
z5eS)D*&{kHRVOol48?lcV~Th*$a?99xGRgL)KjBO`~ZzjGM_eh*ev_W3wkZG&9oJ`
zCwto+pslh?wC8D))i?vCUFP@)A{{d0Y`EPiyF&|vF4^)g(AO=S^ApH@hwK3bVS8lj
z>E8l+Wp7gOw@=neOU-`S3sgKfAUjP#$w65eJu*YG09uO=%la3=?gN?kmmnjuy+1&5
zRJMlBygZc6pm4^ROtTSWT*mklmL_D?6Y%1Ztg;O#k7b=EaFepdFP5XzS$>kDzOM4H
zbI{l$PdN@4H~9@JPVtcYQB9AhTox3<#}NnakKlae1}auOD1YX8*!7dY)eaPY`K@)}
z4#_{JvgQDJjtF3ZauKckg5+O(1n#gr_iIQVk%#ty1j_>{DR5NIr)fPz-a>`b$K=1z
z;yqM8YZMnIOfGFgW4Qe6B)H@9DGs_^C*-Oj4Ev<qMDMs$@}*NjBIMgBc^N7HI}_fY
zmM2k+Buc(;8@L$x*DK-0S$QJGtk20kXnu>AtLe;Uf_w(8{}SaZDXNzw-<tt0S^gQN
z-&5q-&!X|X{J%MH^n(1q*BxlRD1X%lt(W8?KF}`9hbe+^Mb0e%XsX=u5x6w@*dHM2
za)m#<$dLa=Tdu3}&*&>Vney+Xu$v|SfIerEEnnRR>>RmQD7?>=7hXkQp8UTQH0H})
zpMf(4a>+dWXod3X@2TSYn*0}<kc;GgE+ED72Q;CV$o*+bx-S1P5_Zev<u3y5ro502
zxs}V^iedhiym%^{xh-eBioQGY{W_SalA8lCh-&$FFQBnTekmDThrDVpyy%o~-U#zu
z@+T>5+AXg<Mw#RL^2bTI2tD%q2>|VtyHa^#pL|Lz6#M0`Y=(&e`3>@WP~J;5IYaUj
z6tf$aAMl2W2l89tkQ|ZkrURLy@@wSwL-})5voR*mqgs)1`F%RlJ0Z`YKje5M|1A=F
z&WgNUKykPz)<(hZZpFsKP;^ynK7`giidF6)Zi+vKp|MwyDTj!=qKwLvJQTqcQ1evm
zT?B5Q;wY8E?^mp$0F{?Q(hSK13Jc|YycJnA6Z$BArl^yzV$1XJ;-F$%H!icE;#s;`
z{2hubJir`MR8kr|KykAaT%h7vN{|F8){R2ruwo^pCXOh^s1`3+;Z1R>qY62FrXxf#
z-wWI^g+3Eps3L7Y^uiR2XhsZI%wPiZxZ)XF&Ye(vN%zx9#Z21Lo>F+xhq)sZj&Huf
z#fVgVO)s$1ibWI`h*JDWdzLeb*IQsW8XtfKb`1W@3;Jgj6|^Kjr&ziMCSn!QG*QGU
zBBuj1ULoqml}S)MMM3UF#kuD|k`!I>5J^@9e+NfX6y3C$Jg=C&7GM_?iyftaxu_WZ
z1ePu-M$>_PS+O$+<ci{k8|<bkX42{|P0{cz^wSkC2cVFlkcL9xs-oEsjhTuGn(eX_
zFH&A7Td}MjBuDWdZDMm3%>fu-o}zXJF!L1_DlIKgY!3lSp(45ZFJNC&JUbT}MT)rd
zXf0N7=yI1R;wX?^s`!WE|7D8#N#JfOn3X^)S2#Zbg<A@5%2(W0xP6Mj+)<dROt3;B
z2y&4i5<P{|=QWDsF;K5nbkaJkP7(4aE^NKxBU<=1D&8GLUz0-84%eC$H7`QFMIoak
z;626Km*8lt;=vc-Iuu1OL!?tN^exo86s~ldp+_;DwvD|CKMLaXDK>3E-=N|H%7hFl
zf*h}c9agNTdHI22#yxmAqWE|bI!6_M&jI&PVRis}OmVm!u8k{Hw4|O;yp5XD>5mjo
zKM&U)E6k^$FsXQsN{F15&#Zx67iApn8Fnjwpjd&cG9ng@dz2IF@JqNW6%<?aP=1s|
zJ8@6t((@RTmol{vUK~)yQYzD1xs3jd(nncDMFYOdy%e!OsC<q}hy0Z9q{EWG@)l)c
z4k_2nfinTh*<7dxDz{T9UXXGVCDRToW9Fmph%&GOn8C^)>%bjV<}ZX#A<CSACo!=d
zQzjRnHC&mv6()`=9W-g4P_m@Jj!+8eR*zKvJssq<vgj%FMJc_u!L>8W15bjBR<67W
zE=Jig4GL$K%uTR#PU+!-A;l_h(btvZl&kIF;+2C`&yb+(`4)x}mC6wMmSB={3C%vq
z$}XDhQ<QNOp*^oW5d{}7DK}n2-(_VeojJRr457VQma=^{hL)}Lq6k2aGLP!)a+O|B
zpfOLmi&9nj%CVc!D^Qw5Fj%Pc{S127lmScNOp&sd=G9{5>Q3}IN|gLPpx2cHe2^PT
z*1xb+stjEY^JU6{cwpaDx`cw1D-Be+ct`0%6HJ9Nrxq}kO4TJaRw;w&)mW`O{2_d*
zQI6aIsZ}nV0iWuWQVP4)D<iyNzESyF8Ay}z&mdfcW{0x<Ux>CSvuSyBPZ>%-WvkMU
zN^07aZIth5SH64-T!%7j3M9Lg*9=g+uVin*Kzo$yDE-i@tfugEpYqf^DD*3tEHn-%
zUy;GJLFMzsFgT=~Piw;w<rG>EjVdcY19_-)?4rqQOsS^o;&J6Ps&SrBHeQ1MBjs|c
zo_nku-vPUm%3monxLfsm2^3vbztAMVN0r)+i{P$WB}1QwYU5N$da7np#if_3<pCT$
zpo*nO&0AH+26s@ko9=i&)ql+xlE13PL3!0c)y?VX3{vf(Po5lBl^=rsQPuWXa3QK^
z>79B^)$Im@r&P;$P>4`1Y6Tamnw13Zv})0Ih(xLO$HU(<Dq%OkqE${x_!Og>H3J6E
zs`9R&@tn#+d)QdjhA&_~P8Ilu12XZd#-)%+P|1#B^ogpcJ77LZ)td?P$*LD97?Yw}
zK@s8est_x<3#v6sVDO^q79E(qq?&OMeV0}1sjT;ks#*xlRF&IYaA~T|^PrHfD)fNA
z8LECFS5<)@LLpN%5K23NY?adqusN!l0chl^Dk-j=r@H?%e9BiXruy~*RnuNH7OFgk
zpnpvjxd2zaNcEI6Mp3Ntq8MR`s@WCl*Hw{k!L=KzU#T>uRORms=rUFA7O3A;eX4{)
zx$12y=((i|anQE}D^#!FKx?JyZwi4`sfwN9aIGqgj+fP`mQn<+UbR$=#zs{&Ed!fW
z9}c0fS#>oZT#L%(3vl;T{riE^sya=v_72tZ&p|p>?-W6=OBF}afgaTwistvKV*i3(
zpGql1pQB$DL-j}lD&6bQA5^i9qV<8Qh5~UTssnRDMpZK?>NKwUh1RVTs)g@B@{#H#
z3UNBC`xW3^)IIcy+O6j1;udgI|MLVI_p0UJ0NP#MSp&{PtxW@pr`jh1BKy=@3Zxx$
zs0(`0>8E~$VmkinJNb|~r1qrB!vM9BZtFnxEL!LWsoUqn{ln@fzr~e3qV}PTS+IID
zDI8TdyoiezqCRy3+%feGPdF2*p7SO2!qnfsg}!ig?q6``xVq5;<b;}Y8PF%yj)>#v
zJf%*c?QVoRmCB(a)l*i$#A)@yJLrp2ODJ-9M(y+-`l8ia_rZ%8wUh!MXYq&GaP*w|
z(F|CMRnMfSDNZe%1?+fr3<cm5)Dk)Xny5aYL|>A6F?}04S)D_7XNo%9@jSdaua3M4
z_JaCgD$p*fQ+$DTN&WIkcyU?%MhMJbQ8!&gW2%~U9r|hNvQ%KFt398ENQPQOWsFzV
z`*MJiss847G-j#mX=K^z0*Z~~sF!NM<*M6hw#-vY-N5CmO#zgNEl?k)9d)6)D-*5P
z)QRiSSfuWv{A#hf=pg(qQQz%^$aVGl0C;gj&7i8PQgxLdxN`NX3OI91oj?(f+v+dr
zNv~8V96)20+WZqpwfd80xLv2td><(F>aG7muR%R5rsuCo{g5(+&FWMQ?6#<#3SqEK
z{WooJ+ttaGY3NWN{T`s5>OLQcbg5lwUhY;ep=bNP`d8XJ_oy3bhuEtgr*gGEbv@k)
z{p$B##!oSzp87KMhSW*zFh8u`PV>bB^)J8Exs(xg$al~mRX;`B<%jB_`Op|sXHx;k
zxccfV=$lY`Z$RTCHJ^%uAFJP?-)B<Y{vpQetl1EcJ{QfOy=dI6d7WMhu9{cULH20Q
zmB0%(%}j6f?bSR@6^rhgBeW0l(A?;Ry2Dd*k^^t{X@2_)*!wlJuA<dTlgozr1De#S
zAl{l-K3wzB3<pEeR}=dyBoAsX97m&{M*Ar^e+_d1BoAr+c@vER8dfd1Kur<_JcBf+
z4uU(Z8KXVY5zYOlAQG(kbv`^i>d-uQ0p>$AuZF|!G0oTwcp9qV(ZQ@R%>{az!!-#=
zSx-N%d36u^PG~~tI~ON4v#5gal%|`G;YDa(Tm|e%O>_##Y0V_L7NvQL=BYE9#wJ*b
z)|lwEAEWt+=D@R>G%?6IjUz4_*s+=pnknKm)5hUUyoP@d<`XnRs&h-!ST+JJNs}=N
zkz~!mDG*7~EDwY;=QS%R$Z$b3kCs;#HAgdH>5?XT4X`h3Y<JOkMPrIUW2%P#Cb%@s
z@k#WhYYIPy_ZgZxM;q9ynrV;Vccx~|0f1&{{-b4Vw&vACP|VRhUVy$_&8{in@-&Yr
z3YxEZNI~NQO(qp$6l$s{Z*WZ$MH}NH%`^(*7i)IY9ay5-OmDO6nuq>?zM*M+6(hT;
zc|@Vja!ubNit*plNGOPVTNBg@{X3ddR2N^NX`uq(O3juXz^>9HQ5>;a^E$=zYBXFg
z*saw(po*zF%`Pg4sMnOughGQRgvyuiYQFsgdX1W}uVA-H!+#zYnl%rYP;b$EMDgK!
zn!z_H65Xm9+YQAw&AUAO6z!UfzoF5g>7bJeothax!$g-xza5I*n$J(d(tXVbYar62
zd2$UzdNr;TLhjRapMqq+W@r-{2Q-(cNOw>(%M+4AnsA!#hBaNZ1%IGvqd?q<Ci_`h
ze~xOVz66<v8es$U$27O7FnnC|HLb8GG*UV-_ek@u5tsC_X8%U?O=>n1wzF2lM5BxL
zn;$W>J=)83Dc!V-_-Nd#T~Ad$?%KY0(deOd_5_%xHk9gd_i1g5;O~BI_!AIW=%sZJ
zLhAwTIto*JYrDPxnvZrx6B>QBpHbNMpmtx-aU=Fh%PqLF0ov~hFp5B}GbOi!v>RA(
z`>^)#2N=W=ZS4wx25XbX!5!7s(2G7q`yo|o9n-e_0=-b}Q6m(>w4X=9P`Gy9SFmtg
z%ct_I6WRx)eo{O7Iea;#t)}#9gmxB{_(y7gcXZ%aJFR_m2QX3EEmSskM!WR}M5DEm
zRd6Oo`>P#&XSMRfP&}tyNpokcR-FVBaoVW$a3)?G6$g<dG(tUDyNLqIDca}jz@68&
zliL@xGhE@}MeUX-pj^^!e+CMdwI^mez+TZVwF50x`|?_7q-jGbT$Qe!8G|d6seOJK
zM6$FU10dO2%VYSIr)_G4iF~av0U`z3Z`z<<q~#1ly;#fs2p*PbEwqm+)lN~MuS~mz
zYItsHYv}vf)!Ho*G}dSXPEyvgR=X}9Xm#2pH=$9l{f&Yf4cgUoJnXLa*NyPBQTxp*
za823`v<__6hS4^=MO#4$<a^rp7eS;|yOHXH+O+(O5NX$Xehf!Dv==Bw*s1*>1ASfE
ztyBrrt-V4uzW24~1eCSx(H2q)wpTl?8|M48GwGh|*Uq6*tpTk!mAMXTSH1(7A#GtE
zB!{(U>d^Q=TO<R_h&F@PwBy<@>DHUjMyEpLk@j64{C%uVq56VJ?Z=c|a@OVl4NMo^
z+6?sV*4_1kPmaC1ALs?-uA6udG9EfNdX7AGTd#xc(|t-uU-s+9r@*|I?v?MLctAI{
z8jU`>gk>PUI^P~N9@O!#;`jB_wVeWrzfQRo>W6fr^d1P%nGeHKpsqOwB0;*h=b`Vg
zu7+m!V25riO?O9it0FO`5FL|_6du#v$%Id#y1{Dv=;1mRouN3cyG2>)6S_d!Q=Zao
zJdL46=!z%_8L5-d+bl{q<_eTEx)*6*5v?m*1`?xN=LM9rx+xvt;&c-qKs{ckX$M$>
z&hZvajEOpLO1dWL)=MFitjnWkB}KQ9Qi|twBP|fUpnK2@?y|0@3M0It`@Rv9sk$d-
zK{8GE;r}Bvy3NsO%+NhY+w7}4=|>nurY?gvs#&^K4baQhsn(+}NB4Xae9F~*>i7#9
zdAbLiVIp7W^*K5VbPZI`QK<WBJ%)BoH;p1ZMY>aqfp%T@^doq2L-$+^NU6?)s+7uf
zauw8X>Z%1$FV{UyalBi)H_oH+wr;Bm>UVT|sLr!O*F}rMO5N{2Lb6JC<N^g@Yjkrd
zr%|h`rdzj8*I@#w*Uf(hFb%pF&O+p_E|Z?-MxAym`kHjQO1R&wdtwhfY|)uHuyjxN
zP8S+mbxuhTY191|0ljwJss$h&x^y!dJ9Sei(%7ZDxd4*gx`t!)$-DcyDU{;t(cRn!
zr+Rf~=-k18F1r+DP&Xog#*proH_VUdWVB5m)h(uq{fD~5c_3pt&t13(<2tXmAu^%+
zhX=h$ozG6#b=IH%0wON@pQmAfuKM&J(YQzd4lO0z^z-11WBOkG651!b>%F$Xl81gK
z<$OK$2O0pgPhV<<#(up!y&b&tvnio^K!0f(Kz;R3Q2g<rKB5T<etOPtApZKm0eEpp
zUr9l_0DY(yD1rKCC<GRyucUkKus)d<%189OXfAOC>))bj`l$Y%3uHp{hi>6o9Mda2
zVK7u5@fY;N^o_$9cDVinI>dWiuWf?e6Z+qsFs76Gxhp|V>t8N{dX(O^0eWZjf!z>^
z*8fD&vKakj7Szw`BPd95PQN1yjj?*>$Iy#&=qm$3<Mnf6Ad{e<OoL*g{_b6%CFx~*
zU@%$VUJjC?e@M}o^ZFIh5V@eAvIwKNsJ}E5>X-CW>Y;F1zl2JFuIL%Go=VmKLI?ZP
z^lVy6r0ehaLoY)=^Ldb~dSwFaW$GO}nHYVR-iMNM+4||T(3+#4Ld))4{h=(t<mm+x
zIGnG~rgcJrzWGxaEYx$SVW8La$8LfY={qRgTdbc`56KdJ`$d?zu2*>i?1nz{GDxX@
z7tO0>`d_KU|EB&rWlhTU!48_3Z|S3GzPYXUdl}B$(I3vjKr8gZE8r^iYiK7?rI&sI
zu3FC}M{D%&P#u1)K8%*Hb^2WtkgM01)uORM-%T&IyZS#Utk<ajoGOr-^lg;!YSvfQ
zqp?+giRvlZ^sO&ryFR^LAM!0)JM{f*$aLzDzm3i={U7wJb?cL;bnw1@)hhJ$=$|OZ
zKzsEkSHn`D{y!bY)UQ87$I%A#k})U@>c#J%aY*ky2mX%ef1U%$QT?2I=zFNYPBEx4
z{oiDMTz~yGogtpkS5XPYBfXZ+aX;3-OL@OZeJ-7Nb2fO<&+K9_P&8$?;e$AcxEhx1
z0k_BS;U(y~8*VH@qle+x5h!>XrqX!#8Fu)<#D0S-4<cTMpZ|gv2Mitbj`B9#`xcy!
z!53fnb4>R&B(mVtK|?*&dHWdzbnE&X3SR@vAwxkqECm>DQp_*VP(KwWf(-o%NFFw{
zm7wp4;U$^{f(=Df9CFl<ISU3u4AUs$c+BwRTwJwK!w8jH9XDj1Mc)a-7oR}yq~UJ@
zbDT2p3Lq0<5VzubMH(!=aPhPu^Ds!1p`M<<GlqX&gGjU?Bmw#{hOKmJ>8!y{v&cC^
zDF>3V1|h`-;tg?ja0!Ohw3$pa9HGTsl3@qcq$C?w_(LJZ@U%1f&Km~GK`uB9Us?cq
z(J(#%6PFCV>2T_@Va*@l(hQ+gNuF*vb`6aghP`yvvkU<okZi*PIt8C&@RDJmxrXj0
zn8-8y^8vVgL&pEtMTR>85GgeDPz>vuVNM<l6&cDXS5<6y@g?+?7#uNlGUB>nC*9;X
z3>CBsEj4^~3L0gG7wD|mO#^Qu%$FOUSOx4`1|KQ_xosGli@rOC^~Zr$VYom`+e(A!
z74%gZ!r#UPsy2M`K1|dYD%W5vwTAcTNJE`rDka?N4d1MTzYT_89h6hNYv?_W&PGED
z1%sLlA+%m@Hmtpiz7|8^ZjgHh=Up)0W)S`b#dgE+9$<GE^62f-Y3OZ)LYHBs0wUdp
zc~mld-(W68V~@f35}fHZT%gThpJCu-==B?FUxB{^hMH`8R0j>CR30&8c%1<<Y&fBX
z7Y__`{=#5J3|{8|I%?oN0Qb=FEbTPM49lt3Y22`|AC@KzZ&0}Ek>N-Byuf3FfNsl4
zgNy-3osA{?(dc4K-wVmz#@8rA?rL074zN8&*8+;wyBT}>aZUCbXO^MU-T1{HARflv
zcz}8uBSXOLGj4bZBKwVUT26Wyi|LyZ2aF*Ux$rhtUxbK{F@<g@U*kGT#T+y$X+`g6
ze1-zN{>HtOVmo9kI|0l9<F^z>2{gXAi{5`h#%*!XIBb0K7O;;P-49{(!NxmRz#TRI
zcNBvOG5$zz!(+w+6tfF8Myvr^n9<h_lHta?G+iAx?smZiK4I*l%7Bx`Vkd~4GJ0A;
zB8+!NK_ZQtnjv}Gm`HPHlyUaYz;v83enVfxiZ-65-!R5FhhF<<jcYp~bIvII4xq8d
zO*)V`qw6qW;*GcVpfAC=AqW>S(fAo9R+Eeolr~H@Hqa{Tg7JHLmtQn)9|iO!<BzWB
zyKMZPVo6tw1+7p>HM&zYGR<L(r;DF%{DiVi8OB7~*IYG*P$VGJxMvrf$ufSl0$jFn
zIxRJGj7w-Wn``{&1SIo}>=3Bu8&^@>roi~E8@NK_EJ_YsGp12lQ<2egF?=dE9`*+*
zF-E1q?senWe*)}=(Xn6>t))h{S3$~*5x;}nG)`p0V7YO&D@@!nhSQ7Ww$Vk4#yds@
zm1<QO)AM1l(%2h?zAEDvG@(};=Y`@L))+?y(O7G=`GKo5zDQow8>6Z~8jK%{;o)5)
zkMakN##ivkcRX>%U@th;Y&`rsKwFHSc5wHM_h_%yY7C`~L7TC}4SnrKr~kjIj5SoL
z(rKI>50Nh8!M}mhZJd`3?!NK$gRs<Nyg>hq(rauig1>#noJn}tZ(LOl^8-fbS@?Yh
zjp`VB{|y<}cK~hJXrL1k4~$_gfEh79&w|FN@ugQG^3XW{8qALwO^tA7+{kKy!h|uI
z0=18f*B8UYW8*RpNKP8hUWYTzrhiVt3m4NRDjnQyTDl8;uBInwNwCM{L91AIQ%xd0
ze;%e+7DCk1w2S`BXrF2BUU;$J^wXbk(aY5E3L1S(_o;Hq*HlBZ<v~*-RU#cSZTba1
z1(?n+0%)LVVJRAeOz){d4x6$m>vF_2N^AIFlmBZN%Td$7M{p*@l=w2pF;nIMJ%6F5
z_??gmGsVj=m=mTwl+!<HlI(%ZDbvUmn20bfKMpR^^wxPebK2zf8$_Z_TWBK{W7_lq
z44yT;{T2G+OmTE&;!PV{z$KU#ngN|`I@S*L6jS5^fSot}6a|qBrVX^*c3d<uD8hTm
z^i>~ZE}N<-<bTB!PeoR#rWlH2q?xjU0F!QVqEjjvCf!mfWSKlDYL#uemy3&+V|sZ3
z6!J~4Yyl}Swci0LG<8$7tH|U+8|z}zPrG5a#3ZhR`gPMWI=FemVUnyyYpE%Xrkyg=
z<(=Sensl^PEH^RqxNNsfO>|cCwrPg}UR0QttjCX6X<9|=z$%lL3$$v}Rm!{9m~2!k
zQfvBwQYv+(t4qMuoBmk`g$9%FXBgmJ(|ihgHJju=z<i6zk#h|ryk~L_gNv=EjdTaL
znYK~!LAz<a2r`|fm6UksGW`|@{ch9mw0OC1noaAB9urfA#$MA|AGp?MYNIn8{iYdy
z;08>k^fDeaO}PzchVT=D8#c`_L*#);K#`#l)8y(`!H$|LlYus7T2I^NanlRUaCpM>
zI!%|4OulqT?6IlydAK%d`u=w)IGewk51(Ajhk{C75JX~7DW02IGy{!$%}>!$9d|RE
zb_*V6{TU2mzj-dr7hdK<I=^$kJkkg-U-M^_)jnvxbp(d|%umx6+~2IG>X}34UnxNu
zU_Pe@ci8;?6o?!#N7Z9w!RDVSRB_bo*$-br%u5|n=sac)po-Q|^B@00Bh0*u(jMXF
z7pTPKxOqASJWrU*uw9sb(!5~>$SJes5lDo2P9)SL&DI$}J8d4JYRD+_x?}M0jM-^9
zF3eeTGbOjrnWJfw5^K(|fW(;(i-8$$_IQ@g;3k+iw}B*^jk}?dVxC5Ekn`sJK=^dY
zyx=4pzHDCC3TLjESImLIRC787=hMtW7W_>&-=}v>hPih!)UTS)QD!C6EI11<vdnpb
z=*u>{_=3wZ$GimfTys6mU3q3xGfg7-<_Gs+u)xfI0VWE~V*${=X5K^z(jv2if(*sx
zFaH2`i5WEscmT|4KLYKB`7H|am6{i|K(fp%rw!0ev-@pu<>qf_6MM(}CoR4!%yaHz
zES2VODG*m>zG^{ZwRxc@O(Hes2``MW*6gwr8g=G96k)12e`f+(gLyGs?z`qYMQCg^
zx6_=^WL{YT6V2uYl<aLWm$(D%p1Ff&k5==u-$Js@99jyl-CSM(uET6C!XP@$lh0$=
zUFPfExN6;IM3gXz+&6zp!K5CuI2oe7=7)46_L&oCDjYCxnSs7R^J_H_9Wqa+&lnAx
z4<&*;F!QqE%!s*`4p@wu!@q#SL-S|!P>q}4HiJx<Z_vW;kvZTAC_FYFc^~E{&7V94
zL(UfCmuPfxSl*itMORBG%^rI!6RGHQvj}&?i@lbz10e1ecS`K+v!osbx8EW%L(<Fg
z1+DQ8So*2v-P@AS#zpY492kZ{U&~k<`VLwgzo5_0GV@t9`dgmZfyP4?fBNWYfaTg*
zU<O(oPt!LagDl|`q(5wFnhkQqGD-*Ef-S{m=sRi=P%J9MQeFs0k6HSb;TH+D1Sf-p
zS^oBiPvI7WGkiL3N#OzXgk|3XsGqbfp%BX{OYu)YiLiW71P>!ESCWBp+ESee5@lgI
zCLnXhlCc;jqAepA;Nm&UqxXRpYq|Rmu;VPNr-F;O6deJVV2POnkwnWqsv=9VRM4G!
z-tyD`!(5iGB=lXh+_J#@B}*%n{#~|Aq2th3EQe^RmTIZ~4vlG+r^*4AZgKj@0h(b+
z5~B60<?d;?m}Lp107kauD+=`HSV~jiX|81_)kWl4qFo@FZ&`2(q`;E(5zH4_#-@N2
zS*j?ZRBT~ffMkhf<vcWAw;1_QzhP;-3x!h46dFsJ<?}Q&-n4YSNePE?%S{T=+_L<$
z85*}OVsDJ%j-{dlqo}a7P^zHP5|)eWRAs59C{VQ}l8U-&EZ4V#tF>IAGYNH;MYNZ#
zx72onG*~_#!+7snUZ(hPqeV=`Z%r1742GI5b7G<1YKg?mjiZ;AN!ly5TZ%sgTBl`j
zIk+xM+Y`|5wkTCFf8WBOZ9<PloCL*QOVvgg?6WK^19rb<Uo=1mEN8!k$e_iG4*CsQ
zythJq*fPTz<bmZZor4**JU0Y|hn55M+8wh@n+8e8xTTC%G!vG8zk<wTOHCQjCM}!k
zcXGDopM`lB>pu**w%Zy-Uy0jeJ<$MtH|x4^i0rjKN3S?{>%v!I$-_F%2Ipy2?}Ow%
z>-nAF_FJ1MdgNt&k?z$4)_M0~*W3C#O-Viu>--g<zSbAMN9RFnJUy{~*4f`d#^3so
zg4TzuFS0P+0IPrkd4bk}Z1@yxeXj!KsI|%qB*gj_&9BF-ZF?XRYAyN+>S5LglvEG5
z&Y_6MaqBlUub!~Bi(&7i_4O<aDZ=W=r0;1(S~F}AJ#CGpQo1Os@CS&VvCgE2B-(l{
z0(~*o=jiy}S?lumfOgLM=?v({THm3wkMY)5D9Dgto%<q060N)6z;#ZtMt=s$WNXit
z086pH6ata+*5@_oyI{4S19#Ed=WqthCF=l1)Gk|dsgNqon)Wqh(yc$`fn-?2s226A
z^*1`tl4<?p5EQelZ_|b`+nQ^EdXAMv6MC*y`XdzbtfRlfZoc&wI?`8QO<V!4&>BUD
zuC7_%`vVF^)(k3pE4F@};{a%hwV(>@b!+noI&WAxyU<u_eVX>rW!Ag2t+{Cpybk?x
z>nnS4Np4y1{0i*bRu^ZGJJxA*!lA<INmbjG)+JOST4lBN0<79<`VfxRSlgEXv(~zi
z%FFAlW2Jz;Yc1YJ&tIdp>Oa6VS%(%tquDBKf{7OE;yx(evpzv#lvZo~PF&|Ut9CUc
z+pRCeLBGSA`xYcStqpGQu*-Uz7CYV6^HgJe->UroBFp+VRb};BpKbw4pEZzbN&Brq
z;{Y45o<Y*pF@4ZlK`Z+q>-=CS4qHcS0s6qId>S$%)+scYQEMx05g%IlT$mrTMo^G_
z+`7RRgPE}YngfwX)|He-cx-J7L*t}%*JBW8TQj}VU2LAOL1DLT2F<drwndxKxX1Pe
zomz6Z*>+OkWUp-_#a2CS|55&KpDp_xc(LEMiit)qn>&>-9k3mzd)C|b=mGrov6=fZ
z7+>3zWN-&<RrJF2vo&~w^S5b7VB(PNlVUUm*nXRd-!9O0m0rI=wmK>WI&2&K8I4CA
zwul{|!M4c%=ihA}d|dSqTQ3z$9kWec3-h72g%s2bvmK&*Shy{j_N&KjnA!0-+3s8h
zchc5O;o?&^aVD-sge~d`aFMnz$&1srCsxDJDBC)kv(MOKtw1?vV`{*~+8h)A0w&Hj
zmv$oYwwKJXlwjNXIR=_&>sA0Q$(BM3n`B#57q}GLk=x)d*ydSa;-YOu4fHPArcx#0
zW!n$*#9gt?rd?pF%|J70nk{TT45r(rlEDmHAuWNf+V)T|Ce!w!g9<saY*q9nnrz$m
z6hY6i<^O=reB0;6Xe_YhZ-g_2wv9i-Zn5nQJt`$O6RlLQ+d}B>F0<8V!qQFKzYC#I
zZhMv@Lw9T<itbg|y2*T{?N%TZs%*2%K&ox~uLHBj7Sl<^qz$&?bd2DxP5&3r8f|M6
zL7HsWK0sfyZJ_{Mi>-uK`}b_=wB&2Goo<G~Hk;yakak-U6`FR~hAEZWX?uo}kX<&@
zWn9>9+lnrT+_(Krbviw^a4QV;+DyxV*=MU*M&E$xx2^aVE)LlIX+bq;3!roBL$>dK
z0ot%F%pHmkY<)Y?IAVK1yXH|FgA6{j^^Ajz+167z<hU)F*69<ruV%r-BikSqjy$%>
z*8yeHwq`9jXL~m#1zhY^6eHYi*C7GsnC@!NeIBiQ?9YTj-`(Czp-vC`0!nLn+8+uq
zihcHB%6sg$U-=jwdfC@J#05TJ7t^)ywmbj-o1AuLA3%NWHVQKzv|soYdVcozDd+2N
zzf3R1L-tqPfEi%lM(dhDyTu9Wjv)I6s+T)#|BY7tN9@;Wiy3VHnQB{(+GiRe6Jl?o
z2>LO*g+4+NY8O$)F3kRwGn@&xr_g7(j@$dL0_B8VdI=^@+7E63Ib|QF6nTVwwJV&7
zw6CB8A*byO`U8$=yN46{VjT9s7XWkCo;-=pbM~OW!NuBD-MAKUb`Is?66`HHm`}97
z^$uW??7ft(Nwyb;LnOt%ISY0#+GD4JT(Zk4seal1UlkOt*sEuOOSL-~z)Z7$PH*9K
zyAuV{GwfsifWB&X@cu??j{VmEBUARH`QY;G(j1`W+bbv<Q(&LC4vj*)(G6(V?6)Hz
zQe@}831^D!rO_BgiTx)kWw>E?qoXIKb_?m1*;g>&=uP_<QD`i;XVMdX+wL(Hjd$$j
zW$?bjuKd^nv`V`d<wC3M3*5j}+rMhZ#jml?lS8!5zUe3E*V}`G%)Z#KCN2YZlRcKQ
zwaxbFrSRgOz4HjLTkT0xK-%o@QRPOveJ<TB9d>UzRo!X7NhL&G_UtRL@X)^O31B|5
zr<{Svq<zjw*xS8r`Wt|D+xBS>6g;;1GoY}4+m$~+ytmEW3d!(o!H!B?gqUs5_<_W4
z^Pp5}^0s#=^L24s^4IX`%C=P!3@v@zU<yDpw|z)&fZT0gThLgvZIYJcHQP=y(bus}
zngeGBw;gx`edF8CXTvAg?a8zWb>IF$H2QqD7w5vzk?n8ifE?d`Vv?qoGu!LK!6s}k
zr4`(j?WQr<&DlPeqSXc48B1ZJbUTYG#cpq}R6xXMN8NT{AKfwRj|+5i$GNY7lCa~Z
z8g|d`$hwPRr|$@Gf=>lI-nxdq(j9TMg{a=KdOJi~cJx!Neftji>r-gH*x{r7A5Gr@
z7RCAe@9tjVj)Q~S-76fRi7h5EniykZkEYmTiW+OIN$hDBVmX>3y$C8zy3(6SZ(>1^
zVxg!=6)YfjvFq<M`G5b<!^1G|JM)=&-`m@L-<f$An0U5*<47pJ+HR|aGtLgzO2K(J
z^w4+A+u<<XI|Cg4r8?vwhx=4373z@XilN0iXvbhm;vMG7U@6&QZ6_qt9QKl4ro)Ea
zFnHWy6y0F59Zq&ZA;;kyCGm3|{y{vzBrS3XO$S@-Fr))cl{&n>0sRvWfzALea~N|C
z<fKE=3Jmm=L(OiucG|(;2IP!G1=T*Bb!ehpS%t$tx1o2=VJ$5zsvH(fMPs!?#3uMu
z<FKDfmuek6=o@~)!7vjd7ai8WgFe$Ghgh7Llh!%BSqc{$9IReKw9#QKg%>V6Jbwb2
zD-I?KyLLD%tp#Y8!zP3P`cc9BN#-!E>Mt?b;c%~>*%%Io8kr08fPaON?*w2I(=-%H
z&5R&Iq?HNPfNN(aS_8g|c~5IX>s@BpF%0M_bBmq=j_llfAnxqbzX21#+Qv}A8b4Zr
zav=l%OvB%Unl{4JU@;TU4zZ(k<xmst<-hoZc4uREypP^-14aRSeAI9FJt3FQVop3k
ziOWgjreUTgn@s`Qm!>;U0WswnmCZ~YdmGAMB~X>=*B<lH{>^thl)wFUA(W?0y8@Z%
z3N?CX+@TxN%(bQXdsdVeCTF%k)uGK%(AxI9+|SWI*K7a=^}Qpl{C`NMnfvkUT*&;?
zOaYjAAH54q{QHBS0J@-n$_js8(}RwM&MyG5sAVetUR+7B&LyjEz^$b%{UEvQaS%X%
zx#EVF<%%4bS=m6h`&DzIF<GmRYaqYou{U~uolT`fzq!yo_V;cI2k%Tx#_v7Mzui#S
z%M75@xtodEPuJu==1;0ob!ToIhg}aQg`QoW%<X}|@M1oFgt_o${`~J%Gt9{#D7G;^
zx$xv36FVJx_nFmn!+gPLC_40#G11Cw533puvX}L~O_tb0#hA-|?2NUr;LZ-+3|Bo^
z)6yq^@njECgwBioimFS!+29%&3}esIwk4cxq9E;2R!#Szc((XGSV~}DQR!wPTQ&n|
zNo)%pWJqQwQ)D8A-EkDysq7yV8c1V@x<e$L-O>i=40Z;sX)@W1luACv)*XBi#8{aA
zqTo^vd;bsg<+2B~KsnCMqL^4VmvxK!xY>UIESIak4=3`tN!@77=U6JtFW}s0w^Yd8
zphEK^j{OlR#hgVdMpVL?{{xg#?j4E<oZu>{)Vhq@p$E!Iu4*<EPH{h&#)F>bqTMiv
zGn~gT$dq$`()qNrobeBE72ISx8db?{JPgHiob^<AU&W2k1GJi(*#Ltz+#}jc)N;%7
z;OKcSgVq}txaiqXxX8s1fWjqi2;Ca%xYh$ORL?CehuH?M?>nk|Y2^Iq2-;=tXA-@_
z9i;5*RW6<mhBa|NIzsds_Yv*8o4F;^V4{V4Nil?0ZZm~=+qlzIE!ECV@qu~=S3$@4
zu5(UOkWS925hz`pH|>;faIqJ`-Q-3nVDA=p^Lwg1yUj&>0?=;G)(iSQ+>{jny~7Rq
z1)#m$p0A*Im)l9%%zIoc6{6hdEU9k%0arg5lkkw+PgQM?xbTf=e9X1F!O<t&SNEaU
z$8}KX<SExgX^>}JS_q(@a~x&RUT}KUgqx%<xp^XB93?4>F_%t~VYIwVm;6ZCqYTM6
zTL79V*%J=#n55@pz+_2=bpYnLq>*BW*^=73Xv~ph#lvo{<OF?7Yb9R<1MIxy`wP&!
zAPGMW$%_(~N|0-k463hamiSdc($pn+P7mN4l8>#Raa*#GYB;(j7yCoeO<F<GsD09<
z(eTM#8blRBUeYu4IQNz&P^GGmblg91##efkLc|gHU#d{ZldhoMPQFx0r5IQy(1%_q
z^*asqBB?D^c@#@Geh&*JCh52o&{FAJDu+8Etv(O#r1aSkxOht1Ligy?(y~NYIwM^<
z3;N~KbM@#uD_ztJyA^oLJM30U+xlblEwU^ccB|~s6p%LA))0_(*|}j*?~vutL+85e
zoB+}(%ee-HE}7}e59#BQefbbB_Q}F<yO+L|xzkR{QU306=sU^xT!a_S@=3I}^^`l)
zn7riAz0l|_A4iV*$h~QO<|pqQfvNPDe@oS20rH_Izy-=Pnt>7|-%HQo19D3$l{qM%
z8v`y>{=R8FXqbF6{cnkI`4)QjL5zGLMZvP<{b>hyTt0LINVa@*4`wDuZa7X8EMG)r
znFaEP6VO*ESAPcAisY{*!|h`Eg#|EQB0pyfu3RpqHP~7CGWt4H$OB!VP$^$H4vpvJ
zPjAo!SIbY(XILY*rHcMW`BM%2zAUe#1?(01;Ir`Qs=SMWq}Sx*CqutkzJ?aSEpqiz
zz_iN4e1Y9A52IjohkQvY8aw41J_kydyg%JwZpwd6g2FBNf^vv-%eAz$zaw8Vofbj8
z@+q|7xGP^Rzzb)yF~7k5LuNMjp%`p-u@;RXX64>6A8Iy+g5Y6hi|B3{Zq^+Fn8RjO
zlnjk9%fAlENVAh$ArfPDtsY*)n(d*}BXMTaDCmB~tc*el@n)m{fHMhZtKOx`mqfFg
zF0e^vKJ+S|WV6<3fH`iK_6fYmHv5u}2jrSf&4x31W}U?V%{PmugC+%LGbxH(WHyo>
zyv1hkC!nvyY{9Q^t<)?@hj}_-cF_TiC(SgC06S%7Nh_n%W}3|aJ7eZWnc0IcLm4ZR
z6&-r7GP|D%+-kFd6W~vc**B}e-8M@Jgi^QJ`7&^K%w_~*1ifa)ESfR18T5XLduE-#
zL;Zo-#52%)XvS1R^0ApnH?AjU<rE)!WA^qKe0^*7(HW>aDt?qe(n+zT2p%{qc9<wM
z>7saR4j5O3#a4`9k76+0Y4<8tJwTtEVhIJp_9@=C!?64mrAr~=uZXz=?EQ-DE6@v6
zc>e@)K=F7d^bRVLXq%d*NT5AYx<X4&xlDzt4t>WIL#YlaOVR2K?zkeki7vuyMa_qB
zI7g8?9bB#=pdPcDr`SbH;e18VUFa7m`e?~gsJK}GQlto@L!HHnPu~GoqL{J~>ZOXM
zub^;3vBwI|lqm)l()=qvrG4TlMJ(NSPb)k}0{V<%ei-`76|M&<a&}fRWeyZ86dRX8
zv{G?z8PLutewYPPrHEY*^EHZxbr7jl^uEBb&nx=H0qugKZw$;|RE+%-l9v?kQAJFh
zVx|bmdc~LYxi=_0IzTQfdcTL{6@_#XrsS%^|1rF1QVeUOmj+%_9Q1+1%?fK<m~T;J
z(wVDPg&T#A+Y||zP;6HWqcwkr;@^MKcwO<093MreV&@EyF2x@mFnB`|M+Ja46+39P
zcT15-tDoD7-)6&-zjFF3xE7$i@E#OGls%_`8LG7E!^liw%Ci(b30L~{fkY?`p93vY
z`G&HF(aKRvL1L8msS-6-*&~6Yamw>s(RfrD_7z~_l~3rnd4e)>HAte;V+BByl^>d;
zFIAcOE5Oo}>*#=NzVZN-+!iRG4u(%f%1XMPicQMI)c`%C+<pn5wMrQ+o6ajo(0=@a
z(mV#kzNnm~MBgQ4gbftyl=qT>R<A6`L|=pQyK)S>QMoAwb}uW>&>pfwd5EIg*OjMe
zAJVD(mCB{Nlt29rgEy2T=#hI<SwYduTT0V`OYr-)^0gDNdz2UF!2BKMZvwD;l}<xo
z>8|qA{lLDblu~H%zOuhR3_eh%FG1f!<xDzR{z&;g)#W@^PVxoz6J>WbM4l>#d<c|h
z$|5Rdd9L)NwciV+<w>BtROT-Md8KSO(YN`vGIcN5H%iZ6!M#<kpq0O)`4V~~i<5cB
zFc4?+1+>R-F`v8&oU8d4^q$K-=Ec#Nr@iJmv}$uRAAK0!dzeq757yIsEv*>5%nvSu
zYd+?QTfq66H(0_oKl7ABX!JK16X>%KFdzQ_*!#^l%m5c?evS@ug`0m#L50KSW)#qk
zFkc@E5^27bZn4qkJKMm;m{-$hA8YO~2VA@PdoA$(srl%S0OqI~{tG0XRPhlo=&TA$
zBJWkzZ4hx)xs|}tJ*uQ>v<P!o4WO-;hstshT=Y~;TMSSym5mcbeN<B{0OPCra3lum
zuR5;+On|EYL5Lhsaq0Nb4yvAyLf;`(&F}C&ST&69TA``|3*b|j%6=v+g{#~@LEm9j
z(+DU;s`k>#EJ}476|5#{v?^;NKx0(;KA4YFC5;B!5mn1J$Q)Hw|F_FlZTS$OnW}|!
zvp%LeQwH-{s()s}?c=KUT<B%1-qArXNA(_6@Z_pK>jlYI{Y>BV0+rohI8&@TFcEsC
zs&TY=IicFS4rWakRK4Ap=ZmU-Du`ZE^_z{(I@Oma!PTou{s2saYTRdNY*a0v+fJM6
zI<36hRbweV+MyavIhX4yA2XnIsowns1HG*p*Z|V4($MRCdsOcw!~7kUg36KZsbXju
zabMN&0s0=8R1XJWf*-1^DOAy?+O-<wsVae@3eQya0|E0~)qNJ8zEJ&|3`;Lnr&aLc
zmFiIs%)eGGqHm11#UaXA`B<b;oYdFiotGef7We+kMp-PQlcE6@iwmH)-{N*P%m-Su
z)3+kX!Zei!_5lm0AwWB5F|ZVhhb-37WfE-BpWbv3V!>sAgj#Hy1<5dr!Q0{5VT+45
zAQ@rtaX*kqi$AHBCCcIs?dPH`{x}KA7>i?t7-6i%i#m`a7QS?9@2JINiWbCMRPO>x
zf`!w6uPR8gc>5g&nrw0WYqX|V_-%vvR13!mAZZpUC(xK~@rJ5gGc4{=Ic}y!-e{m5
zvq+`)*koCxbwWMcVo4mxKFe{XAnulyKS9#Nvhp4H6kw^}0=prW2S(9YEdQaZz%a{?
zyeV@OZkbGrxCqO?oZxAs<!Q=MMOjX-f{AF$$&`|avAj#+;aE#^6-bI@$a(m5+_L8%
zkZj8&ssYWh%%%H9u4Q|Fpq#V(oPwBDmJ4W^SZ(P>L4$hBqx5WSu(Yd(+l`jr45g!*
zmo0bDdh3eidJSZ*TE3vWNR#FDK)86#GT;_Kn=QkJ!9<H?@g;nCt(L34fER6+i#9;A
z-EuZfUWcW6IY_5vGwm|FEH_bN|Au98Hc)O_`cjPhmZg0V6dqbGq!9ZfONT~!{ynzb
zOb7IySYCM!jXujYGr>KzY^TzcXO=U!gFLqsjc9yfIWh%`FD)MpN8>BY%@kjFZTU6L
z;Ty|MFTgpfzk7u~C-tjUAkJ!MBQRam1}bKBRVUD~tUYS$PvFH~_0{#@Om1q6br9XB
z9;<`CyIQD&hKD+JF&aJ9FJ@qZz0@npVcuIkq!lCdQGY~9bYFF82pav=4K$_x>JJ{H
zFF-vb0*(9CmyTf8g4Eyrw=PnDzYZb?)mN#A>yTPUPs3n!BW2M-OzK^<rwLVOJq8=5
zE;Wb2aCLkO%pX=;Q8p}6ZF>$}l-iF@enqPX?ZbFu)bE@|U#xof*XWB=e>VzxN7V09
ze(|V!`w^H(P;Z`yu_UU$=OL1${_JZ^LbBRy8MqYn`XfL|Rhy>%hSoH-(?ocYt`3d_
zXomVJ<wY~qnY67vrd~{&s4R7I3&xbKzT6AR9JP|pIpnGX9iX149(e~M`D%g6>k8C!
zS3tc`t)s<Ok^0&RICDn*_#wc`)t~<ag|q6=O3YJ*da{WYrx(>Bo{+huo=J6Tb?Vd0
z&{(gw%?4V7y22Nh8r8RpVE3~6EZtbIs2#GQa8>P@0kkIdW~wK;rXEN8%4W51C>mST
zUKCVnRd?<JSetqxO@6z&Xf#BwtMk{Ru~R+rUlaW9QrA-b#tro<CurPMZ&X6&mfAlJ
z<hFXY4@A4w*XX9*quxqa$sM)XL@4yC@9WWcSN+BwjrY_W9HDSuU4I46JW^XzH1M(d
zMg{twsB`F^(5J4Z1^QF<dOEf6Og-0?%Kx9MgIzGt7wR#Q&~UPf+YW=yR_g;XUKguG
zZ;aQ~ira)S?X_z51Dcx^+XQZ()p%M-xmyXeYVfc+?1(;3tKaC+?q${ZE*ib922dH5
zkCi~%3ty|pJ7CDq$|)Me-zs?~RW8L_FHm3<iPj-ffF@gioD0QN>wN||lWx6u3ru8M
zm*+tv%etGkdD+%WM!-_O^-3#9Hdtq5L%qX#;{^0ww|)@=uG4zOVsKs77w1C#hV@r;
z+~}tDS$eoUu-;31sE5|Z_aS-kK|G@~^-@9COKYBX6R)hZDAw@W`nOaxzOi0Q<w|d@
ze@ca}qvj}OR-H71X!+!<@uYGI7fszXD0peU4FI6GM)(XUp&Dz7Vuops1YkA~Ys@L1
z9iiE99U_sMn6coZG-C!qGDeeV8cjpiIM+fWO|v`}cJnkXX(0KUrF0spKodV4BBwP=
zXd7@w)4HFoWzC~j=%3Z>pk-!-rezFBrKT(qdgnCV8PKcJtlf#mYE8r{*sak_oexs0
z>Hh$Y=QUrJVMrG=+2iRVY|>QBfv49r!zujItXaDmmRdA}9ih>x`N0cZo2LCdylB_t
zQ8`P8X4M;v;=1O~htTWPjC~HSOB2uq?uO>p9(Z_Dlfy&(mZq~G8gFa<dIdw>nv!~`
z_h^E?1$Rf&_K`U*!d^`;&Cp#<HB~>{(=0KA;(bk_KNKHmvMI^;P&1TH-aXPxqH}zY
zH4PNdf1+`j3xz&SDV>0Os`;T7BF{8$sZ{N`CZrycFEn=hz`fMS^I+kXW*OzvUTf}A
zL9iqL(I$FxvlCza6m#OtZ+r?g7rwhcL|ys*7a$YFw^RW80RO``z&^x39tpHy{v;g&
z3FH5;f?hbEN{`3G{HPz{Zv=n-Uw9wM>ubS9@!!)@E}FNDrcaw6!NYtkZ%!2;ar_gC
zX_}7kx$i*#C|^p|E%E#d3dtw%^|W|Q<kw#Vm&AWS5rkyEQ4f;Be@3rdN#*mX;53a_
zAA@8%|C0pR8T@<}D4BeOHM~E@&)Ebni+|t<l;ix&sTg23pG|w*9R46J8gotj<t&Ki
z@#zE5n$KrvfGgm4Q;k|7e}i6RSH!C(LBE(cryNuX{}Cn7OZl}wqwfU&6{Tj%_#ldr
zpX4`{K>ZXyjY>sN^Kv>6bA~UV;9fZ&I}GY)`3hP9RPe(n!cxhbiXUT4=XkUIV5|7W
z{m@y>TVI7n4PQ+aZ?*hhs`)?952Q!g1^!cWNM7V~KZD36ew`AZK^=ebD$LjOTgh$%
z?_+_+Mt-jZBA5AFJE4As|L#watNf-6jHQY1pk>cB-pn)rY%_l;6rwGB4AphD@@va5
z!ZyB-wlD3xpo3@!|NIAV*ZCiBK%|qOW&_u{cq6@T;|9NbG7R42Luk8ni|?#P<86L2
zo%rkKZy&>udU#ig6W!s>kHXPjzJYf5clk*bCXDGGA9e}TeV@NXPpt=hCw&GF`3NOu
z_7SfW!9C`kzl4b={7PD*_wgYc;mlM13$pZ#&p8WA&-oB{kQaP4J=b3H^Oi&M6|eje
z>aTf45hUO6X^9x_Tb>Vxx}(tgF>QjJgifkWbrzyLVBSU8NVy1CA!-)5J;L5{IJ{S2
zcY<>h8mPo{pD?`+pzcD$S@`539Q_-8o`NO;#7p?{3M_dGgYQGnM|j{05no~KZuI#H
z2QI;ozc4u-A_2m}jkF2ckFz##I8YdO2@VGdE9m^+0pZs;XdD!rDH?f5XmbY%7Ap5(
zx<Z6559o&q(<pHiCPdDKrEp;s-Lnr169XU;AsFesw~>P9d5k4WI5ZO^T6m9M_7fu{
zYT<pXuqqTHrZ}N$AM73xmVOV#qrx0I_7N{!$Gfbg2|_Y0E)s>Iv@uH(uEv8T3sE$)
zDME}0FH(j5Ljjs5$mu#x7t|}!m?5m|fk>usnQrUHgm=bafLTJ|e_umkGzB`dh3gdg
z&M^r;1w$iOFekJ;;WE{C<O{JhLj}TLp)g-4+}Q@MNSHAe8pT4|Qg9{0hpRzKh2x8%
za6%AQL9$FJ9f^55DR?f&&`t?0&tdnpu)Gi48DZpZD3lA=oS|@5cuxmXA((!ruwbPS
zK<T%0!ig}<WtA{G9U9fbs04u42wQezXtlzt1fZQ4oZ`V<5Sk4b#YLfE4nQvnZiC=j
zozV0c=Ie!&ejp9P^glovg&U^<c3FsV0=Xh|7s1d~!F@RTnuJ;tz4Ygr@LM-5H4BrD
zgR}^9sYb0;2(18V6ACzJv<o3$gX<7fR9<ymC=7sprw~kmhAttS*7!GsWfa@IDQrIk
z%v-{=0`%P$Ea)wD-9ii<3+NHD8v%Al*i9SmULoVQ35s_G@d}20Pp}+-&ig|5pSZ3b
z2xapzw1<L$!j+GN@XP3XENn;s%oAZ<Gf1DX{crgDR5(rV=XoaVr_IxIVK`k^FN9fi
zPk1Rfjfdnb;m6<5_*z(GguOSy2YW%@3L&W!1auVB%mL#hc5pE0EH26dnv3`cmAJZ!
zf&`*_#Qxq8*(>fpgg!Shg_g|w#5-NUb{ALDW$hvUObJ3yv5mpdyu?YLV@TfOMk<f;
z5d$<Z?<+2+;s-zRuia?$7rRvSzNi3k-VkW)7gy6cgg`Nmf*3*K>$8wKAhu2i=t1%Q
zCm@GJ{~%Zj7R@fhnGjK32FXxy2<@@M#2|O{g^RXpA(<kcr-MVOA~y|=ris%=LnK}F
zr>Jm-7)ueHOi@qY5z{g81Z}RfL`N(MrN_nbw0O)G+qS^d9C2|GT+0<t?}kX8D8#{T
zzPN_!NeaZ%WdJP{6_mm$5>p>Sp;(;O2NNaY9t}vT=;I896XFaic`g%2QGxnN@n`_J
zQ=;!haHmb;YO0q#Bihgkx?BvV&CFS`nr`+L;!vvktrR~U2ovYTj^{wD5@p{*v0B{r
zGhk}O&GZGR6|GHh^t^b7?gAIYVN2oKMe(aJaF@i@RFzpLu3QU4^<qDY#59PGS%7X7
zO*?4Qcv<YF?b;RbDJ?axifvI4Z4&*;FzjohBL~rD@z)PvsYQ%>3%jjiGi5m1#N93+
z?P3AN2|L6Eba`ACV-`cCQ#?#%++E_XQ4qNyG89|BDc-2W$Zm-pKLG5uSY@I&DRhg~
z6rt!5CqIVb9dWBQ4EBnFeIR$mB~<u*Pb@nQk^5qBe~jsYxa%)~J`@{Ez&#Rk++g>y
z*hAxeA`YSTXP<a(8T6it9oK>KOvKw|@#PR}tYGhj_?W>Yyc9=Iq4no0aYBE{ycQ4A
zQvZ#pr&#e@@uDZ3an%006hm{;wq%2I*1FTG(nXuO9hO|RVYDjTqwR<Uw^uunzOZiE
z4q9IA)3#F;s=IbO<^4Rgb6x?{Q){0I;-$Sx5pr*B%6!@c`DicGL&jGdI~2rEn{^au
z{@R>}-~zP$=K*cMHiMG*fm;7QGzMuC0^rjD?a3VYbWqz*5AKlG^E-$HYa2#j5Fy$r
zGco#5ZSiX~hG~;8Lo!?|%YaXZwGDK}AwoL~CEg}!r1nb$BcxH<ALz|E(b_UEI2@x*
zbb=SLT7TMg#c6AY!o(5n_y}-EwLkxZzIbiFU!jnooniwMiP|bxkR<KhY)B?+^I{>H
zqJ85HuvG0&0=P8og3B<Ju6^-6)HAfdj)gO(Ozn;7&^V?w+Ce5u`w4v=j%z*MM`N}&
zny$GVZD<J^bG3cvpqQui^@U`<wu<8P1=_2$Fe%i|ru%x4_S@?KE!M`SK%qoC^EK2<
zwLenS<Am0B0MyI0M`ok(q}KcZxKk!=f+a*xYjskzp3(mCDL~7$UA`FFS?v%iS*g$t
zi^i;1YRf1ea!%XXiM}dr8a;rjwZA`x!5VE4)$Z47zo4u8y!P%R^j*+?`3T%a?dXv(
ze@Q!fI!K-N+Co^U*G?G&y#}r65=EyPwe=Esb6GohEeu}K*6qSXUDYb{;Zu{=eFQ|W
zX+QiE`pw$;G_x(*rm-;5s=eF~dTrW)L*Y}q_8g_iJG4jc0_D2)8WnYSYDYG~LYH<s
zZE|jC>-`{dQ=3nz^;=qniEh)kwQngG*{wZ8b#p!16>X5Yqm}J|ey?`wDVV>jZKEZ@
zJ+104xcl0v1oJ?<@mqjC)Xt|h$Rq6#+D$*!woL`f6KyXoEc&#rNpSnAHn;)YGwsdY
z;GS#uQt|r>t;cLCM|-Kwqdm_nZQX~Ed9A%R95QdTRr^8SYM0K1h@-CREkvAj-_feY
zS$9H&zb?A$Tj+Dul~00Cfw~0RuLkKB7NGBdZr;b}JE*&lbf@%?ZuVsK1?x&4f`sZ$
z`a&U0mmfnfVh-22Qk?Rz?wTFUN9fK~!EU5(@Fs9ky6;5jN9)o$02-s4<N&{8b%g{P
zrwf!p?}+Xz3aB2{MZOObubV-k<^<i%NGK%gYzIR!N!O~z$CRuqra)baE`gQ=sk$9o
zsS+YxH}z*|Wav(<1Ig5dGz0XQ?k#<(vvdQWfE?G=QFJz2x9S#r%FzwdVlHxZHgs+`
zPuDmM{^skp(3zV8-8kC16zUj?gcj)rQI51&=T5J-F45uJfUkq@C)(Sc(2ePWh^b6>
zoLW!nD!pOil<pGkC{F9vQHAXp-EVZhx?Jbl083|eJQed*=zJ*jTB-Ymic8MvX3+aZ
zs&pT118B9*YYNQQ=#G>5THVJHKsm3o^ar`16Az>DqAr<=Q7`GldPvrpboLRT^*ZGa
z*lo~lz6KMGx_75S^s>&CA}UvO{<JZ_suOO5H0flN0=%Zn{tP}f>#C@Zx<xnEAE2$e
zL+{epK{qQInC-gUkKj{>Zp|c+>$<Tc0M@B1*#&31bS&+|Zs<%8u0i9bZcRE`Z|Q^?
zkh!gENCR58&e9T=dUW=)(0E5TYa&RmZbu!^?&^B!hI~)=L<RNxy59tl2fD{a@bIB-
zj2~Qkq&qeTllNF>+KUN#qHCbqhd!O=D@Z=o)fwU8Gu?HQ8SFmSO`|2_3*Ewh0Qyq*
zit0#T>5|?B+G|}Co!We(>wW<Jx4J2Gbvo*Ygu_E8{q7;)ob^$(+i=ly6jycCr#nJ#
zkNyEgAol8SQiZvjel(@K_UX&0NW)$KlM66C^pOu}{pqRyoswW)`h}O#>aE{QNlqVq
ze|nhv>ig*C=cjk3!z=#!HVWJX=nIxXWWT=r9Qp$F?^5tTNPmlpOAhG&A`cJh8!4c9
zNI&><C<N>O9S!vm{om=B!%%&o9R?VtA2E!MFNW)V3_v@q-$_?sg#I$s5Jl?e(~;&V
z{rBd8iPq1}f?|w*+X-;7`XtK##Oa5B1MZ04ivk%(^~>o@f4u&(J$y>g|GgR_iTYPZ
z0hXk9tb@U1eKS3WQuK3ZjhL#xaF@zK)ATJvft{}ZU=?IC^eZgkMW+6@7N8x|TP{Lh
zmcFnT&K%eOxd{5%`f52ua`f+RMPshM?h?2>{WJ<N=Ie`GFzW^SPb#5Ts1Kv-xJbY8
zZx}4rZ>2iH5`7-!q)PR{v1l}%&|f<QOJ(|~NT8k8pGX6DM!%KH&(G@1C&FNbo|y;N
zD)oQmL-Cw`Ln($<r62ks`l|H_bXnHuzkLFcTK&Q;5IL`}2!i?ry)Rws7xkVmVd;|I
z#~FQf`bdhA)a$e8+16mvH&PW$qkae#8C=!}JVNUg{c$=$a8-Z67lUci|2_dC&HDFe
zqOnCk<uxp|>aAYG-!}c+8Q|LWXR?9ap*QXU%60uWXE2CPy)Tt`cj?P0G=4+>wHutd
zssDtEjc)13QEKY8-t;joYP<F6^dh1j{k~1$?&$Akg7oUG7D4o`zMR(7_w=z+h}_p3
zE715*|C|!VkMx77QsS}R=OM@weKcKceR`u6EIrlxR>9wA`dq3Uc&^_^+mjdiQBL4q
z>Z=dJ{44z+6YY>+>-W(z>5YCRRh+)nU%`!1>S*}uE*hN-I$FOv8&0)>xEO9Mh8M1e
zpU(n&kKsM4{o8AB9}9zS2B82V`wWw4zv^x%9|aT-!#|#A^fdI`#9Vk8<{yB9w_!c~
zqXr+t)*6bx_!{2(Z(n5iHXn-qhMI0P1{eZpow480{UJOIG$hk9Hpnox9v&Vr^t^${
zLBj=#s2ws~D1kG<hQD@0B*gG`CP=8E;~vz*46+pX8*Ugk1)t<$!!F9GMHpW6fr~WU
z45dn>D8uk?z(yNJj)wUdL*g`Wv4*2mLKtV5Mq@f+NTh<`qlPFdzK=J=(2I=|3_hQM
zOEi?!fFv1IwE0dpl<dIJQVc2yNUGsIDf-e3d2|J)8x{rwCBv{X79`WqfUPv%*KP0~
z3-_}Odp|?#aYN{MaM^}glrG3IXy{9lYuHIgZu1O@JK;>e;n9AKu)q+Q4eUZgP$cXY
z8MaYOsMxScgAtY(9&Sftso^lK;ZGQ@o&j{3p*|FochXQvv7}Q5aR<o3g{7!OQqpqq
ztRck>L#{B)I|5^shST0Kea<jH4>qd|rL(|Q8y5cyks3olD&T7k=Cn^bZ-}vl!Ue;J
z;qc(1;qnd`yJX0vJ9M2Ps2{A<8zxa)ror%;6C@iAHB@qT*>H%8psyIROjHtm)v)Uv
zWSR^q<G@`ryiccwnhjrCU_32`gA`tEH4L_cVw-`ZPqW=nJsgr9h75Z5*>yuCWnDTA
zt?$Bomq9xSBY$8>$cIl44UH7oe`MG}DWJ!O3u{207>?5Iv(Ml=g)YLUhMBa?d}eru
zHhs?xmW|+E7z(IH{-r?~3rnvIGpHozwc$Q(#oibkA^?+O!zv(|Y7<Y@ZRs{^hhY$z
zHXm^4J7%+LKfK7YDW-+&ahnP5Xw0_ZYM`ELBa4OG`8GQeC<swtQ?MB_MK<ORKr6N}
zQ4+Jn#@~!SMw_pi;l&9X-8!I^*?j*J<fKg{<%~|*jHQC6(>9i4pk8iMPiu^`Hs7bh
znF^Z_IYiFcJo*d@RW|eJtVgxYe0wz3*c4G+M6HbhVRMu8yp5FNBo}OwspRdV&1nj+
zUa}cR%iB7eD#|I=+xVOW*I*MuMZk?V!IUJqY_o`};IG(}(f;|W&1{M_HQDT@nZ0Jy
zN9omOn~9qt*<$k{MPOTPuKj?<HXAn$eCo0Z^Ms?OTQ)1N0{gbjkCYASwlU9x`5v1C
z6z9KVGmF;4y*Aq^5PR2#^MS@ao2;K9`M_qQ9nc=y1nhzOBb#AgfIPPGdV<C$HvX9q
z>9g^C4u7B8?31AJnT@YAeY`fisfg``&E6Dv@zP|YrfdC`&97%+;<b&Eo^Nk#+UU%{
zTN~v>z&IK=-34(nt~a93*%(FVWL=Dwvw`MnTt$!0J;o&uAhOrEU_C(Hj8#+6x6e3$
zl5+0GTXeX@!}x;I8lFaHKQww7wUj^eHqI%W3F>3Cr&W-zF}eYYe#VV|0W`oEL&cB#
zjrsI;jX<L#3ld~(TLKdYj2+FmSPmMWx<llUaTPsEf{pG6N1nntpYTPH3^xW*fbX#J
z%TIwBVbs~di%6r4p4?H!k#u=P8~>n^saWHoNK8<iG5SXg@QAU8@@q$pz29RF;*EV2
zbWAjM-h^JV@k}z@O)<7neNLM3x8)$|#y6C;$}k3I!EC1SoQb|1$BduSjyubkTMHA}
z#^Dqs$}wK2Byp~>iN4x-#*usBMZWRKF90nt#`$0ng~q&308?a~76`7`=ty7Y665)c
zXe>208_;;dIGys(Wyb!~0Cv)t69`978RHJ2@w8E`qm9)WV+LIb<;EvTP&{kwSOu60
zV>E?V&KVEC0;w`Sqx@R6QO?1&8smUZz||U;P>A}x@lz@WyI}mT9*r-IJ~04uvz<&4
zd3Rem1tdLeKXXLiLE8aa02X4qnS$@(w%yAqu@-4-90L6q+eu>~8gDy_rY*tt=Zg?c
zw0$hXrzG11dO#%GF53l>6x)&C!i!W}6+K<kY(H2=Gi#e!43rF8hSsc^w!`U|`7vAf
zKVUb@_Aja)J8rw+BVgv(zBdngxwd1+)5faIHk?idowT*5s-0TfIlF;&-nOL)q8Dth
z`~tfdZ9kd>kxRCLOW{nN?FZ8_w0hfbDV*D2`<$MDjkcf1L;bSt>!r}UV%ty(XRg`?
z5K5En;|;*PX1ix7^qOsz*P+*9YZ;A3Q>*R7cc9p2yL1YiYPZd$&`*c$!b@<!({`IB
zu)A#M768q~?o}rmUF{CgqkfNF|BcYwYZpt$al-8Wm=3*gyD>+>9k$y_yMPG036wI7
zwA(fsT$J6Tfl!aJTSL3ySiAl7;5cHklhE7G)9h*uFp+Mjeu(jA*nO%-XQtiqo%o!N
z*&U;(LzdlVr@<Y!+cg7@X4}Ph!BUBx8P#-_+O2d!-wC^BBgi>BrxJiw*}a|zQf;?~
zl8iNWn<zDY-tH+S)-Kx3qYdOGJ5#$3-n7`+`NPFlyK35$x7j^f37K}gv_-IV-Hu-b
zm`*!vdT`gWdq@fMKD(~TkbG))w;p49X1DWqd_K?Z{ONxD((Vvl>#yv#&;#qWU8Mrt
z8@qY`m95)fp*yIP{Q;`*bhiJ}G!1UJ*e`SkwyS+p1X}ml&u+o!_u4OC0*Ck6D;J{A
z-Tv>(ARhMSbU@Y9zI*`O_Ok!!G8DY+zn=w5KKAFo0OxD(MT<9o`%?#@9$;UPg}(jv
z4}XK*K>Oje3kb4Dz6LiYdyfxH5Itz0PC>0h_CKvaXNdhhiUWt*ub%~taQmIn=sRrx
zF2$yg*vD^1-%<MlT81as=hFp|Xg`W>SIPF40tT9DA4j|YH2cis5J|WHfmRC{_N#t{
z!A$$%7Qj4ae~0b@S@xgg(#Gnz{hEpB%(hR;1Ie+Uy$oo%_EXkk67uX<TcfeS{^LB@
zJ!NmMLEmZngOn9LW537_-j~~#(9Qa+eIy<Cs<59<*F~j$l?07d_NNvBrP}_FaP-yK
z*A=6$!T!5)INE3*c7PUkt@gXANTbdEr7e7Gw|_YSes|d4YQ|h#x38sDb*KHxcIbE6
ze@WHBH|)=B1k6qQh@&un%f4I<_1pGW=}XydznLl(dhBa1L-LM&@pgFO*Z=Z87Nfw=
zQ0{LSd2ceMOy7?Rq!)3!Fze~-;mXv+gY028HPDC8L{rtQ8>6O5&wb3zLr`{SO6Vcu
z!L-tc;K_({B>iNeOg1gxk27CHz|(BzHtqCtn9nE;l*_E9izbh`b`V@X^DC8O6);<O
zK%|hlbOyv!#GHQvv|?uAe0W^K%%S^xDN|nrjT1}{z3QNhNpS~vk{L>gy;IEC#jtda
z=~~^dpX??xl6J7J?2uNd?_qZjg2BD4<`Ej**mb+1u#Zj10_V;KP)VH!JC7a@o^0@T
zG<uoX_%EU1&2FIo=;g!y`7^M6*@xyBlOH>Xs)qd8&*>;Z04qlzNfyD*F2b<u*i!7V
zWqY}&G~b@wtt(tV{6CUKUjh37xBp%E8_G$LaQbiBzX-0tALE)Y0DOXtH)JMu#sPY=
zwJ8hG^S-4*m&MiX@b9-lRGPTekuE}qZ4|KI#|Y&Zn<vvrFR9C6mS4mymNDz!{oiLQ
z)X{494R>cSjK1Z1<#5PRQXEDjkgPEWvcKel1Gp%8B%PIsmQR`h@EG~3wNzafE8j(d
zwKjGCi;%gg_Mjsnchzggz}OS@sIw4#rGD`_I2Ws4iW_-YO{4lUe=9Ev+8weg+y*Yf
zs$m5rk64YL3zVZ)KMsHw@m5WgoldZ_ri5^!)k0d>CRvSJgP|u|MNydAlw!5j4f?58
znN+=;W;NOuvy)}@#d3%iSmir|lv%0223my`yB?07w~G7$`d6&3J_YDitJz6_X|kGe
z8j{znPW6ZRW~=p!LGD`Zibdl+t6wX?-M2c1K%(@4)o4mfKeXDG0(*~4R$o(C<FS?3
z$FTdvYWq9D?z589#6PvNr=dN!>Ny1SFRYq=hsaB-fsfGm%IXNksb5=V(0iEPSiS0m
z!dt6}?*QA;`WsrvJ6VsXl4fV?&-Q_Hv;K1wQ1)3b_!peJ^>k<Gd03k)9|6YGdRITN
z{?>lCK?1A;mt&y&t>ez);|jFyO@Q4XYws4I#ab89yM5!W+sDw9THBn5LWZ^CIm~BS
zf4m+eEU=#21IcUF<3B}Tv-J(aY_(ny4$@}*cqPbn>lvFd>Q3wBCR<o~ZhfvB*N&rR
z0}q2<n#<q7ptojrBS^3&kP;V>nrY+U_fgFuN_3`b3U5RIxTbj%EEQ_*%!W@VHIFEd
zSE>2ifW8YF=|_;fthwt6u2u67g%xjTUZz8&R};DzW*=)<PdeiFQnM?DCW;?e3F6MX
zQ}W4!Z*YZ%C$FGGNnU&mzF<;s{`+(&`0!Kc@#V{VF2S(<`1$9-`Sb5nNo4@v)e2|!
z^W~II2;>z_=nLXS%FG<#)ikn${LhupJH#t0>E+h3d=!1#<M`F3&^W>;)zCos{&Z*}
zo_C=TLIQua6)=hX@ilNCg+4qQlX*iNND5y~E0<LMD1{@__)B3JS~`E8!bcf=6m76G
z`TMUyj`2sH!;9m*PXHvd`R}jN_b-S4r3@Omd<Jc;@_0`-kbIt{Cu;$}kGAB6{4E-2
z5wD?h3dQ^*+C!G`Evukc$|ntk<OzQHewZlZ!_J}cBrkm*dZ+lIRGoF6*F<1Qjr{2y
zfNtS)sA8;(_Z$EZO?UVRDw=x4Ut5gUm;9!0f&GdPuY>4oe#t24zu~tQq3<p4MH^yA
z;TXN~!b{j=1`%(;F$UN^!rf0G;w!9A0jQtw*8ueS3)|_2w_n)58a@RI`{`6%kTCQs
zs2>nMpANl)CIRa`d=^4-8%UIpLB&AP!q7-?F+%Pepv4O7zCvT1;N1wABf_;{cyUzt
zvm0EzaNrFj6NRIP!6gY2Dy>TvKKKOllp?I4dahJq+Ao-yG~v!INTv&qH-lsd1r&VF
z7fdNp=qwNhv_rpG$gx3di7<~yr6B(fFz1As7ht|xkdB99jgayoxJF^&bGUz5(2z4%
zh5hlc+ayd+1X!m~WB^!~u$<O(H-sEYEZr2=^g`s8aAZG*bX!QK2uHV|H<g3-2%+>e
zxFd|Y0>xh8hYirUE5ylQ>7HQw1-!T~9FGR~K=_>s$sY<ccLU~;P(=~xC&K&lpwK70
zuf}KaROlNI?wRnz4<OHl69e&qz7RgU14my9KD99PN(iHq8?S}GPEok~jo@(vCf*8h
zv_N(gpZy3$C-G?nWSqsdR3q;q4tfDaS23d)ecqyn5sg0LvRBaa73Wey*iW4Q7r+9<
z1xx8e7yF*TwLr11KO7AbD`}S+EpDQySBw}%BC(>)Ni%%^;>5B$5IrJV1_AV__&Jra
z#fv}DCz>E0X@Fv)I6oflCy70N=t~w=@gOPUKNsLksyML|uBC~aX|tOyTI0Eh>V-cd
zAaYDh84k=W(dq`c<6<g3XS2oohr#8DLD=4!P_|IN7>aq~FnT!Vi_a*4Ss<oVVY&;&
zQd=|@i5?N~qFB^XAxVkYkFqbNV(nM(@PxSTBQ%zY1NuXuR=iJ}^Yh{=Iz@O<yq5sI
zOXBz;XlxJ{(z^y4#l19@y<$})rpt6!{ADQUOYtj5biNWzS7H9O7&8YZ-iU?Yq4BNg
z<OmH%?QCl}>ZCnE`vGU|mM++J(OS?W)>YfN9R~Mk9Vs5TSKIX?`rNdxg8{ZrJK;T`
zxNCRQ>tQ{#HsRpBv=Ukdd7HF{WoY%$1}}i3uU0=7*nZlS_tELE{k9C)0on<T=-aPt
zrHoRb_7h6#2Wh9%n*D(G@BQEoYJ;2rdPwV13iV*EX*L=|v>9|tB2>G9svhFCCBbM+
z(2k#i#zgI`h2WC3rpg`oNRqW{)&e_4%Z`M8npTwyyXo4WA7e}z+LyEj&D3tLf)~fM
z?@+mJmbSbGBy#wv?=iy6;i><^nPbEAD}b`^BXJ%~TprP81{3Wg5=(*d`qRA>ynOTN
z@i;UFjJ`^Hn?s{V{`W8GgGYZzkDSoak%>Ud8hxl0=1+~@u7}L&(Sv3KyK3}w`ljC;
zok&aY_%V-a%;711){Ub}a(!S2&^Ls>hu?@b!HZ3WUHHAVo)&A{`uPHW`*J#x;mEX7
z?7)dBy9&<P#EgrCga=bI05G0RSOq-rW<qE+8pMpG0-^&<)e4ODFf;uyP$C$+r!;b=
zmP21WGlrsk2~0JG84{UubfhYYDHu)D!Azpl=2^@r2Usd(GM0lYVy4oUyqK9-2fY%;
z^g9(!R4^Y?YPyp7p#h-hn9cNVt}142G5Q)9#RouZWPYbu<z;3uJ)f>H`5tI&XVjFy
z>0o*(fpeXaQs}Rfxjh0S>|&m{0P_a($w0V$lTmb_?-mpJ0(NgRs-x(8z<gk$gC!4{
zhCt{)Vh&Se>@hQoYWANnn>FBGGfK)DykQK}F+p#crX%pekzGoUWhZtBRVq5O=V_(l
z!v0GohOTTWq3mIOXtTAKO`*N18=Djgk$vpGd4P6jt*9v1gZ(3#_Me_?{Zxp0v4QkV
z@Mdq_hQmHA_YsIM8$l(ne(VLh<N33*hJy=W|D_efel}MFv_N*u0AL5PZ7f6%ut&xK
z>>wNbJNgc>gXh6QFk3$vj)t(w)({D0BYojh7&~YtovsOI-%$AJFl+N66pygDE#NlD
z1{I<)jXfTW!KAbG3DC%3i|<1ulbu0l8S`0>E;JUfS_)_svS%j)yNKPi26l^CPpXYL
z!*ai%ubkcE0m-xMG72_Su+#p5dL>&so9=(-*wtI0QN<=F1G|Ymatn&r*p(DSZf3XB
zsjU_^i6ZgsY-%?YJK2s2Q0QWR^}x_>u!@nm5^l0v=hElPUK|VWZ?gmF0n^P6wM1VJ
zyRjC1j$HCKD7bMOc!>CLKia{<njkLtOSFb@mtMeb3}>YEX%hG2Ff=A}BVs{PxPW)z
zMJiWCo60oq6r~B%xsEc7w~(`Gg^41r<{1nYbDQ6RYb9LqWr&n=6aEVUawiU4L8S9w
z4&={pD(t%P8jFSNfOVEza0T*p+@%^=ZQ?@hq1M5fQQgCB?)qP7yw63IL*XeWmBG#%
z&TRn{_DUvu!do}V^tb5SCmH-DICsg}a#-+?ETVn6r(^<!xx6F=--0_Ni8noggTaz|
zx>1BkLhb=3RHC9o5Mh$WP}mKZR85D-VM*3XC`L+N(H$X5GO8A1kCtGDFg+3@mGZ|*
z{@#tgI7xyEQ+Pyj_iyNBN@P~>H%~H(f^DS|`9%0sF8MSJ>NS!R11N=EFL|FX>T8k*
zxOYjfOLjg(V~=E}8D#EAhSWo&SMtqGaCaq(X_s|R^8Q~K_I=4GR6z4UvUD>P9!gr~
zK>dv*aSptAD^b#_)=?UM2(CFv!>Jn88ShqxYcA3!u~2ZuKdx8cO5Y>3kHzTSq|&wM
z+$VibPcV1sk5NGLK+pojQ+ikd4KL}FUFh?cE~J=@k8~qdf*q9p?hKJb(oJ+?CRo}L
z4wMk->l^SlR4P)6AWX_SfP_m|(&8mTYOsK0q*S}EU%vs;D5<RpBaD{zP^cmXZ{3A6
zvC`Fab~sL&esE+Hu98FJz-8baD$viAE~gOxF}$rFpjpz?Wau52&Ze^L9O*;aUgb)s
z(8e)O+D;iHywsu%{uW3F(}!Lt&E5;JBI&jjXe^dq-2jwwX~a`FaaJm1LZL!xK_zFE
z(nBsF=cMkYrJz-KH9PE9ORrM}XN`33a(rmD(y&jVe?gkx2(*h*f2wx8B&{#OAnK(0
z`)I6}epdjlLHY-si)xf+e+_>xOTVC0$`$<oVL;!IenuIUo6_Kq0Cr2t&?@@2)R>F0
zbW30EGNH3a`mPe#z0wz7LI1AwS3ii}lQtiP%zbHbC>kF~H&jFNp)@=dcHc^!ccal!
z_N_A<b&~x=AysGD0#9JO$hg1J=PJ812I_lc7kuanka^lca-VF*T|m3bq9%d!kTqVQ
zLO)Mg{>K3IlHH{MueWR#?QKJ38#us(%Di*Hg~>M4k}+HsL|?qavV6*~M93B`gTYAI
z4oX}`$#%NK!x&jr0kC6bL2vLe#mT%j!Tb@~a(WBRQCS6L;o@a;ZeyAgWM6pEek@Vu
zo(q{WS;GuyoRp=}jj&4QQUdo|WV^c2*ed&#)*G*7Pw4RzFZYiE+9|m^m3p6+AM-)u
zHTg$XXl#`ictE{d?ra0s9>{;rf!;HDOBTSM%Y!Md<Zd>%1_~Z#Zj{e91)6=91oIJQ
zjyoZfVHWoqlTc_T%ZJ@lW|=xPUNbAL!3ZCi<p%@QO|g72`T`Zh>1<TA;$IoONLL)7
zkoj>%p8$~xg@V?Yl?rAA^gNY2RA}^3dQXFEzRE##srxBs&`veLq}($Mt^1W6l{W_|
zd+E|Upp5E+-yzB_n$l3^IvbEM<)=3wa#&foA09?1f3}6e80BFfaIwmPHqeVx{^|n~
zuN<d@dXn;k)#yuArl*0+P#$%MzsHm_=7GynD*i%Ww$c=J0N&&%k5ExTu5vtuu=A81
zwB$Ue3^jsOD<4zL<GfO*K;I>$;TTNRD;wyQ5{=446TG;hbeaaVYsw<JNZXYcdLiO$
zZce38uIAn4;P#qlQH*_`c@dTS`j{8}2}wWmKvODcpn1SY&_7`Q@E+zQ*u0z`w_)a&
z?$Lq|KjH`n{GQiLnW6a`X5;sQ06J{^v(-ray>K4|m=+bkg6`rTy5BCj5smhxc~k|l
zEa4z5{GwV6v&+j~!=n`el$=~S#DL$cOy3TL+Ujr8G14`u=J@?vCuRM%ByYiJx9<E9
ze{bva1;q9*_Tq1ciBkc(V-zi?b}bo+zjqI$RJv&ol|wl(KTwd&nORA-@-EB+Jruo}
z6siI6VK&qK-j_+C0vSJsqeBeACT9Hz$b>Ls<^mnBA6bKurZFFEg;zPu-xO~zVN_)p
zR5>%5*15HeRRHbaX<AMU#qS7qdmT(ivI=@xXB68<arkI9Z$FI1uz%LW(RlXgmuO62
zOKt-%l^swIlWA-ZN(fNs$C^=n<Z<@je(20*|C|Dn!#25q<g)Xq^0SEj#Ty#M?1W)3
zQNlJ-EbSEg!6ukL%~n(K)EV|A6~LTh=QzS{6<bCHWEWU9T^<+N+7ftvi5*6(qB?fC
z1w^i}QIo(;zsi2@1Gb6%nX2O2*w0>rw6iY<;G^hZGbpTboh>Ybekc3WY1qBZmQ$>=
zn|(m5hI_0-DH<QMxd)xv@i?h`7m|+Lq)q61q^R=5#63}ten{yL{JddIbW?rHxYB$$
zviB*;;lv(wgzL`iuLGg$!v1~?@UHBjIFLQ;Jt~~q%l=J~ST{DCHl+L5Uufs-&fblL
zo(DUM;*_53y#|_2FLvQqFzU_ru7yD#Htjz2ec9JGkO^kbJiu5(*oVi^7s_f2(07#e
zx&ccGY}y6o|MODJv4{8bXZ{4)1@F_>_2+Qf0WZ{G5Yk1<31jg}6I@s_wF3xC<9g7t
z?7>P(FaBaE0NQf-zff55cnHR~@+f7ZR&B2a=;{lUkzXS@358!PDbD$u^(TN>d)5(J
zo5p_$V}Jj<2<_W^=~=k_^boYWGHd7*!X5^1s>Eb4Y2VS9n4czLPW+f5R3z`uq^RJK
zDS-Ld9vY#{R4QB!V@w@zIh-jgfeR5#!zMIFGkuc*6UX?eLE@S1bWS^onMcd%R3<M8
zmTH*+bdNpH+=#>gE-(vgVd)|hOZCf_n73=eU1oA7K)snMqis?LGm@_NZWGhPqVox(
z&w=6#=4BIPUNa*;1ln8Xr}4mcVz&$eOa%L<CmOTa!N^(scX5c_R2P=V_<aJMd?s@p
z+$vx`eF?lm=6eJBikQ!-Ua*)kN-?SuMomY{OPP_hZLVM(t>|%9$#kB9{yC<OE{-bZ
zE6QM1GfC7~!)$i~sb!L=e&jqekoNi4nU|kq#yXikD&^^7?7K0LyUa0)!QEq?PK5bq
zOq~IJ&zaj4tZ-%va^Qsv%YOqASJs)%gm|;=R0C}CVPy+o*Owi95~7FLdj~**S&#9U
z+z@tk14s<}5tTW_vTJE~5yxgzMb;5E@V}@XJB03s>Fn%L(92^tHN%;FHY^903fQP(
zs28#dD$P61_E1Uh8P-S}y>iyL24>HiSlK}+USRjE0`^6AO@C-yVl75ugmr8j?NyrD
z(N*YcVXflO*UDaZfPNeM{VVjfvt_io>1L7LrG3ojl#IW_7E#2fmyP}b<Sy$>yQzEZ
zPwzneKKn&ECg=fMK-EnTS<@cMd_7{P(hcV^yKg(VCu}7ZdH1oOZij16+0ssU`ix!r
zJBIe0jid$h3szSJ?j<{zibP+rla>SRHLIdnr5Cq=VwEA>545g|;zn=4SmL=7awdbT
z2m(3H?f(UhSGcz(3Ul;wZvUXwNiux{K*J>)>Dinn$^RVAluF#G%&1l}=v%noBDwhw
z6dy@4{sMU^S)cyDTflj#L<Oa*(hM1iNeih0rVamo5JSH%^$Z5m4XMXgh;&QKFTmzq
z{Fie;m>x<uc|-K6R84gOFQn~*!M&Ac$RX+~tNo%M28JKuXf1Gm9^C`HMLVvdb4j2A
zFv}#gkX{~>4VksytjB=Y)d~3hkA`*vTi(>+@2z_UU~Y^399oWyK!qhvOa$GI+!@m|
zdggmD*}eb>U;;M-e?N2n1R6sbeLJ`?rhO^;Vwt}vu@T3-NBPSX#+gFDsf_&)NTxAz
z3X9}06Yj&AT&DRuVCOMA1EHSJY<>;(0_HVk91EFMp75oJ`79eK#mqX>cF2@4r{2(1
zGtW<hoL~ZJ9Z<$(Q1<vF<2oPMr<ghl?Vn~!={|FY*-gQ@a>n_0h@52x1p>5!c|ujL
zl}tlFkaLWhO6;nbi`y^-)yy+W(AF?s+t66c*p)%=JQI3_9(Na*bW5-oneB~m<|;FA
zKc=pU@%#bvb&ZkeV5ymzLF?icW_%~SXk~ojAaau_um|=nX6Y)3+-CL$K)supO98(g
zX37RY-(iMpfzrzi;=tWy7SIMgon5^QVA*W+=M>(}W%KI+lg|#Oh<PD<)E}ayti_L*
z*^}(Q%Q2WU>;~GzSFmn1P^@CVp_oT4+d%8fORQ-X6t1!vE)coS{;&tGIdajzDbR`^
zv4J)lVeF}YK*HI(c~Cvf{zgC%>{wGNq_Gs43e!>SM?2t1G^=ofUJToD7GsTNtKPy&
z9P5jx9qu}vU&G2#_UdoYi)W{uhe85tM>pa`wu2VtNo=AVlF6)N3nWumRSG0i**;qT
zrLpVOFqF>zPSr^n?8vPqbY`*vZ{b@G%Pa&}$~J@p<^(&HqPP{Tmjn7LSw#b!Imd2n
zg-8|q?o`ZiJ-dGc%r~&LRQKJ;W~PF>%s!y}a2q@BOANG~Eu_-_4wn5Ede_;F6a?;M
zr|p137dvk>l^5M$|Jew|o9wo8aOxKO&O*3&o2^?9m~QqR$`<#q)k>h<Vdv9Lx|h8=
z9Flig6P@L{$MUftPg!SL&pu-t65#K1Hi0gp7wjqun7m|ve1yhV?6lL6e9aD@0P=>N
z86d;+XD|1eE#}LOv!Pc)_;N*UQ1s*E6#hNLIq9Gu%*|>87sc6AxF(uAwE_x>TxA%1
zO5y@(rF@M0nvyA5+?*~*7ILHaffR8r6zMz7RW@KOXSjpI0bR~j9Dw9`Zi)fKbb;GS
zL8pt{m|8e>iEIA_qIKMR_2{hUBI#^Z1LyA#yN%rY^md5L+_#58u5fO<Aaa$9{u<6S
zanC6Hca3Yf1=7qtaRX`L9BH}M%Kc6c^){|J7hvt24}I4=xdZ8Nt;@va(=PG`7gh@M
zH@O!RG2U+OG%b*NIPoR8JKPI;{`7KwaZtR=W#0yQ!0nt5@{s#@8L%I5>!Kj}ntSDf
zVLM7{smj$!GU)~SoF#=M;v!k{H~L&9Yv?q@9?3hD-QFiLeP9kt?vmOWm>Mt1i<@x9
zTXHB0?)yl7rz_A`vV03H`AORUL|=lWfTFF(Br6M`P$;>R56M%KK&tJkl3Y(mV~-?$
zJAJ;=(3|jLpG>rch?neB+A8_Te2XA*K(?zH&>^yqO&MqnmG!!S4U^eYpfOw)LK*wR
zvJp1{8Yx@A!{KPzSqfLh%DPnmJtF&)A!lSME@(`YEmH$DNoGgeuw>cIHt40u>P}(U
zX|f@-%Se}f(+rX!3)}g>m9<c~9Kt`FCet2mVTc?SabOpg7I*v%@0a{WC!v?#{R%?M
zI;Y|HuQMJ1;WtAF{{CIQ8Go;}?1Ic+A)iA2?`*2E_=l%YYK!3@es6uh6Jy#IMkCu1
z_6G8<%ve3mJyS+Y0B=T$VmTAGS(BB3@nuxeAb!k&4tVd+n7zQI6U_9ZNLC2*gudaS
zj4R!d!kE-fnkJ@|a#rcg$|6|HVdl7CMv545DD+M;VVglJm>0C+s%7%t!!*@1+m6G>
zCT7vM;5wN3U2w+K!+dfBt$j?V44{tej~~OJKl=|Q45Qe!`~H6o$zEGD_%S0Kf$Pt>
ze+b=R=Id)v4Pj<ZfXkuGn@>Q(nCoL;GnRSqF(l)dWAyk*VKxN7^He4@9tvs9C|VDu
zGqM#F^vh-5rSsl-%zUcZ%4fo;RQe<nOgYX|%!NA`T@~{+Ju#}8uV`1&z?`JWS|g(z
z2eekEHVIrCGk+6Iv@^|AK+wUApAD2G_PiBDlG*B8bV;y>Cu8KPtak+@)7Y`tm(X@{
z3%v^}gRPN)WU_X<Ftl^*C$y|@WeWzwU<B7W9wd?*zXp9#TuKd0L~}OuEsNpye1M6I
z<>pU7UmTY;1bRofz5k%`DEHT&5Q*nzevSbqa8v1SpUABo2-kci$A+TM<R|%@Hi`a{
zvs#!4kSzTh1KlrKM#0KJ$;~wQ6eRiMXJ8+Y_|T%^pd>|t#zT@xlyVG~?6?Vq5J~y>
zup26Q_c4aHM;1*-(~@L)f5L96EJFwGn5>yr=-ILnmQcu*Rlmd_3Qe+>49FDA7Sa}}
zROXE$LWH(XX&~AsTXq1VUUHu5wv*-gIy9Ecb92E}%9$<jqF(;N*#E5nZ?jiud(_MB
z&V*kN*g$%kKVftH;Lvln;v-1AakCpZSi_I-oX$#2RhV!fLORn=3ucy31KYE$^k|vW
zuol|i<tJiJ<}UjS?cXQTYm<K19tY*ccj!Rqk|}-oy>um|?Uu#ez~8^@jE1r0v%Z1@
zE0%r-t#zFr;_vl3O4t9reF6OcXIBJdcFw0Y=&m_mP|$l16DFd6FLU7(y4;v;4QSlQ
z-17i&Xa1%9Ofqw+018=*qy!@Q%m&J8l`?0hpzjRh6O6_xW|}$3MdrIaxPF<5oeY0l
zn1@Z^x|jetxI4_Ui5Tb;#_JUHUNb{1>EC|1uxal>(Veya<$p^S;ow^M{`FWMGx3ci
z8M0d>W*GNVX2hTH;u#b59$;QF(PIJnig8bZ`dfxM1fLw)cc!7yg>~a0>B`<Z4J0>q
zAl0evV}ERh$bR-3ElC1d2RXgBBZaMB3ATt$>iFMUyOw<ugqF)}ofj~!u>Z6H5$h`|
zjcj7y%m)V2Ka|3|!9JP*$(yW!%J90`)@u0G!)E<gp1^W+65$@Z;T2qX&i*?SBY45S
zPZ2^7Zs#))A8wE-7uW$@&>t9NAUDMoCW1JdasRtXi&eDRdc>^X2BgO*Y(w`GCT$mN
z_A$MFz<tVmLs6M$4Es46UD!1%{u_25U7TL*)zN_UW;b1d=^%Da5!4T0H;2B1Yz<W&
zMwr<Clmm@q%{PLLVxR1QC9D9uA)3fCV_-gsO&JM||7+&jgQBX!_};U-mp3kgrY4Fq
zsV(i}?y?|`LI?;8iz2VUb|My5T)|yrm(VQHN%1)~S<a`(<RcqJ&2om?@tLA#I0TK*
z7^z`FIL_!yn!17&{Z8p0{nt4C(VcttJKyhnobR5w_uO;OV-K<9M#S90J{>|ypRten
zz@22_e4_6Zd*&fZ`jTn+nuZI^=RqBHvcO?*->@7$3G+Sk<1gMTY}{oyyUJ92u>BgV
zZ{z<d@&o&DAB4T^ja(RBXM6dC_K&Q$3&sD$2KXZKJ{GnRmv)!AN>Kc->>=;C-edkN
zd6ls4M%X=I7e)ho$fEgd#1LzJ4OjMvHB5l{Tk=f4I%SPq69tuB@=bhp_n>@tJztjg
zg?tBJ)_+;PmTx`kl@IYZ!fm;Of8*VkJLW_7yF9!NnrjtzcETGe&L^XYgNk%BxKoOw
zykFO;un!>YK1J4UX!;bbVQ{udd4M-sTa|u%wtI(Cd>b+CQ7+@FiuWr`9{&6_iIsfR
z<O4B@4>a!-3;1CDF3~)MnrRjzdC%man8e4&4~f%w+jm%u<O}hSh!x%7J{LQR5QSH?
z+hA~1Oy;{7j*I7bJ90uSQX{leV!#a)cv_svrzy{fmQa|V726{CmYH*6a~KTIiy!j|
z$~Lj+1T4N5JIsi?Lo9k3!E}n-R>HnZT-o%vwM$>mJLwts_@}wqIt@CRg-V!bIpzbg
zXf`5-Y#V=o=O#45bl&>gkmlsJ!)ku>VZ@s|au@~F=N-R~YtO&N!z?hyz)@jh1Fq_&
z?=B%<bbAd{i~BCY#RB{xGTOd3E8yCi@-w8b+z5k<l3_l$^Xhvyfs}4&z_0Dma%h%i
z@r_yKNBZHxF7Pp<g_C$cprU#g@{9Im0e93p0-?INCl*ZQ#4Qk4jo*P7mpHcocY3x0
zaShBtG1aU4P)kdF*APn0S9g$i*G>ao7n6hhih1$CR||SRQNCX2jf0QV0-g<-3}47H
zx$Iet0W;xIXoyU}0T@ZpYN_&pFj<!}!<v_mGuvoLskPb7sc9vWR?=&we_+<?s@e*N
z(`}{IJ|S&xox^D~a6PSFYtS2vdXvE@ne=g1kIPl%w%Qy{omQ)>a@cegWo5e3nk5>i
z%W2oxOKlFFBx#LWiOZjyr1l9D{}+J__=I<#Dv;;?RgF-@pfKgB{Qt)_?!7!HL=VvB
zRe_Ntq3`d_xz09r(&(<hMDLYP<jRRNQ)cK2-1Zu`uB^1Cs!o?`cUO8`)jE$$<5^_a
zEOEJ<x;j@)rMtSc%nlu=#$$JT+|aYtR;=^ulp`sSlt?0yACkY<uQOonk?@SXw35PP
zOF>$c!KDA|DDduI73j>R^rcKi!&{a9^ouJb#+%m_*j-F}M#)Fg-46L^?^I3DJ85Lt
zrwsS1+(Fq7)>S)#z15D8MI!AD4vwJE>ud@QoDB;1YO6#3STWWlC1|9CSn2twzwfyy
z+^PnBykzjE-wG)Vib{x0FvaQZ#<&D2wrpYP^y$;>QoK<wNw)Ix_*i?~x|6;Tq)_ik
z--xNR)N1}1p#!Bse}Exji<k_nN@P8phRS4GbRk%nOjZ`)4K=A+{poa~N<rPTR81^a
zpqfP0T$V3TE2vOTVM(faLOYcvsp^Do>H)`sm85<VN;8%8I;hZ3Z7%|j7)9ff0goR;
zi#g37L&rdc%@i;jK3b?4gyoN=1G9m)&>%<q$(#aGMcX-fpKfx}LJ6rLS7`$${nP`(
ztP-iyVAxK}(>QyUE^@Y;#?Ikx87-az_BT2T7XAX#fxa+;7Ni4hqGqtdJsRYwHIgzj
z5MaavY6OLgn;DRzR5PUGqiLfV=ppLitVK=gOt3AqJd;bcbP+7GXlYy);JxI?0vxNS
zW1MZL01I55pkj+EhN%Oo!J?YXQcZNgqMD*yCS$T&^sPk|jfx$#sHO`0X;L<bhs>O8
cqotg*({@gp=nTl1Zj(y3g*S$ek0;qb0rF=T>i_@%

diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
index c506d45faa5cedb82ee25e6e289a13a1d50c3e46..5a167514eab7fdfbe396f84e49f94faf799516a6 100644
GIT binary patch
delta 131343
zcmZ5}2Urxz)^_*I^mLp&gK5n<=bUrSy5_LE<~8fCX>~9wf(l5KC@3N#A}XMmP*G7#
zh#;VX5d$bD%>M5gb-%s8&)%*+={={atE;O{)o`<-y1m)cZEGdfgO{;Y<}|Xu<z%M(
zxhOSbUMw<onE(A}X0>~o%8brwg_=><E!`ecGb^;IATnkZcX*MS(RDo}GV0c4Mvz3s
z7akNCvxaNKh>UKr7tg2%mYGKq4ZpdGiZKh^>qLRkwO_$8>gi=Rk;E?WGjH)sH4Qg?
z_CiuDB|>9<C7IEbwls!DnGjrbuPaH6rkb@c?rpKerHhU$WEo8(>ty1dBQ9NZS5CmV
zoz;%}UrLW+TeA#f={kfN!={77lzQT#Va7V{HI_l08x3K`IS8TD*moLcyyIRewL3t|
zOmN&AEj?g7(Q$8O%1`q=(Rk!<IV04}7Zu@^X39^#A~RoA-QdQF8c3U%j9c0Ln#eHK
zhjt&vu#E1XL0U$eq}~I8S<qxWVZW>LH9wH*7eRyTqxn3;$}6g<7?qsoxwuJr`<P1t
z@gK<qaZceGzPXxHF-(O<LZizl`I%V)BQ#N{)(l@^u7(ksI|vQ`7kENz2O;nW9<z+l
z&Os>rqauzGIywj=f9Z_G2wfb6l|NvIT6YIgn!lJP+ZmycgZhQn)__re2T_UNB8!YL
z#6eW!7Z)Lf;SQn}-?tP(7~>%7F}lg^)Qm7uRU45y8b+8ZsZpQZ$%s}yIZ%z-Mz$1C
z+l}!uqn4AkBBPNP@6|9Ix|NTXu?w?R*)X<|S;aaPC1#@FatHT($ZDApTr1K&!?&#o
zH=8R^gJ}4V%^=xYp*)CY{JG5t)T4qE)SC0phC#Be;(ZXU_=>q8yeq#2(T<<n5o*2;
zq7y$)#WRAxgXq?c4?Bi>2RNu+{JaxrpCAX(k8fQb2q6w)5Pv5e#EuHoABOQ2hruSi
z0zH(G{29+*o7J}ea|^89s&a5w;TN&N3_NZ=_rAo4jT~*o@Ohs#jM&0KX!xkdko<gh
zLH!~5`RwQkiCrCPMt=4r5Ir1(mGAvYWW?SMqBNtM^1GT5`>M6@LoM(5wV7ZqV0koq
z=QNI~BzM>%G1cVLl^Le8e8$EwRb-b$6;oBdb&+F2WN8b}<S{xe#sqP_`fq^P4&b62
z`v9SAHB-fGr@^TB?Xi~WCVGW)KOTwbQ-$uoKN8WeGSySVdmZ2yal5@rBt(_?Bpy^?
zWqN(9@$FJU1Xn%=q6S~2ml-j%%08&o;#a+ZB+Q{!kAGK}XT+TjwFdkzMW|^+#Vf#W
z#P{)oO=Oig*firGyMl;v5Um^?L5!|U9ibg>%+{1<#F)y*Vbq?Fz+ffDIfxGY9nW7{
zRIb{&n~D+7t8YMFscKu6Db!FcD?KuDOp)WZbhhWj7Pk76_VP@m%87(pEyGyJF;hCV
zk&5wES?FE<<^Q;iJa@FHR^_)RG9y2g$imRTs%6ILamN(E5gV`-%IX}?f)?fbZ>%6Q
z<Moc`r*a?5=o0{3c5@}3`Jf|M`u8_VHee!8Hq!(MI*`4}y`NBRiH7;4(^1Q*+!qQ*
zJ%_aP?OsnMGkO0SHv#|~u=%HPp03Mx<AqG^h%AX=6Le*N`U!EUo_DBvHf&Y3I*;BG
zqyv}vj>2M8QvX_q2eTbDfXaQQkmI?iRW&;?SN(^HFxTix{q$s5afWAxIe;cQd`$ld
zG)&j(Um)20`X3u1hh=K~$0qQnO^yGxsRf%Mj`mo{7*bUlM(;4H<#2TEr;%RQ{J)Nj
z|L3T3#5oP~PJud;;;?BYQA5YgY(1EDs@#KT3LLUQ4jD#GdT{A&{%%t+P-NnipKaI9
z@r;&3)$xqt6vs1CyNBD=PcTfyDFf&ssog{D>gc%DZP&29mrqnPZi=JtknevS_^Ceu
z+?4h|TF+tcru6^*kmstSM{=+mNAHo!eKu3}Z_h#POLwG>F-7U~-KLvbhoN+eGMYM{
z%Dt1i>sJ-XKk4(Nc0XZPPwl8;rYapttaeYZt1~<!+UMJgF%-0ORCb#qm>%e{j>p|j
zY4Ef0rb-;sLHW^L7YgLIqw?cH&t(jA8*xk-2Sf`8#L}M-Wt65rA;_lOPa8b5p}%3&
zkug~D9d#z^NO^KI(p9^=+J&6B>K&8W(ODiECJj1x&m6ek#vh@j$^V0UMgG4|r?rU8
z9*2#;!zR%5!)A}{=nHE1B;b2??wntDQH;bammTja`6%tsKS%l$>~gu$&z@}b^X%WH
zOmE`OmVZ2<nZk#~DrT<yZ=-y3kmbHN{#?fRF^6ZG%l|&<X%6&WW<vLj=~97x<$1YF
z85YAqmkQ-Rgs7Mj>0jN&4qdawp<B7@-{s8c;JN?5JnXyt0OZ}Ss+m*&zr2~%Vc)ge
z-__IXJmZH>{IinN93oW5PiptG!$o`E=~m57b=)9z{aJHUOihtl;;@7XhLi(8Etg2$
z{#E+wE;2Lzqm=nmX~w_sjHzNJ%)|bp^!caKSgF;&NNpE{YncB3(W;EkmE&>rmwvt)
zjOoj6mg(>xr5+9?&!q0vOcZ~^|EM<gEbeY~)T)xy`lp*Z)e=O8Z6#v-z_5!>#|E4)
z^TSUou>q;6-M6g}>gd!=8}Z*Kyw<8=+WsWx3fE@}OuL`tOkqip%(VYWPQ&B}ugnk9
zb4?F_c0pXlp4V7*Y+P}#zgRXWZfc)owyf_eEfXmG98L-xO&pBQjy}@0Uw&C1JU6F*
z#kKHpV*@@{AaPuW{$o`@**-9tWs^L|4=#<av}kaC*>010ra%7^@up*ds#MKkGJi-@
zRj)a9G>r9Md8)(XM~56OXXSr9)M1YC$I1`;KK=}Hj6YU>()aOafS|45Svbst&Gd90
zUb-Q*d8YP9pZRW?sU7-X%S`Pb|FJwb+{4~tpTvyR{tWYoBTRb@3KL)>wVl2{s!5J8
zMrsFr2b<^!W2AQCcd+s5%)@FZ&!vx~%6+6dqpiq{(l-D83NnuG<QVP$eJ3*|W~^4{
zQ1;CFwO*aycWRi*|Hkmu(G)H<f5cE(>*$q^;bN+1gAw`cJ5S?Cys&X~M&_~X15bH$
z8Aor+;2izRF>XzbYd$)e?N#xOz{GPuD>u;roLKh<a6I?#D@Wgmc&^`n$M|?|?Dxve
zW|XO(9mkfgNDZ=p`_cKox9$RND9x@^?szVqe~)!xH+Zt+N;`V_Ag=9?UhZhRL0sSe
zq7UN6{6sgtULr76xqrtT7e|y*{U1?Q{og37aznm*{Qf1X%KiQmN0~92W6o<(Sx?__
zMn??iH9ubH?~m`irq_QT-+9f*pO258*Lls<@6T(b<9VfO{^xmJ)O>$l?sJ9n8161<
ze!Pq`8KwO@H8Yp|I{sC2^dRG)20!ATtNHP^e~)3VX5jbuzjvXznhF1nVXkKOe`A=h
zv3ysixz(ca75Z*4aZCnYKFk2|KQ^HGPcIp&W<SRi)7+jaCgnd$qkk%;sG9s#Ql@z3
zjW0cl9;u(I<-c5M3(NFV{j5r!!$;~*^M0z1KcA>AQVYESAy81cFHpbVB7&UwJ#@4P
zd(d<6gi?;r)F<|5VCv#<k@>`S`>r*YQFd(7G6&e7&h|K*)ou8r*$%KjyAPub@r<2N
zdMd>_nQi_v*7~(>YZ=u9O+~^}Z-QO9iJ@v{f~GMs%9UG3_kD?9rFMNS^P5ITd`3@e
zr3SZUj#1V7Ve8PXr)m3LH?GmdN7~_yv6fPo$I2J~)SfDdvz{HRWz^+(&dIc$g-H8d
zw1(xr-|S*_T%~L8p;JY#77d)#1B))TqUN+SL?kK%Bj=Ri`RCLo7#xG9mS*ET<EK_s
zDs4x?Kpnw4aTSw1?@gV}N}hwKwPZ_qZk*Q0zGEVC3=VJ&txWOXc9j;_NSlajjk|PT
zhy^ysj7la2{TLOlo4!i8HvdHWql-xAIm_YdkwMpCt4JzMA%19tfNPf&8Q1=2>3Vw(
zU5|$mTCRN#6(e5~D{~v&pX@>g2eZ|<?%z-RKQ<HG?dm+PJ+Z#xnCn=2bIgO5<bE$^
zeH?T67+rhxAbmNK5R#9Q)t<7X`5FThmO9hueoYMBm+3;b6H3|1OrAz&e`EHAh_Wc^
zuOG<`pG&ItZ=@PImpFCoq}jUzwMWi*YN4YW2;u#0()7JTIy>4DC$>A?Ke$XTBj=L-
z$0EXK>yq^F4!WP#L}N$sZ89m12_%83ExG^Lhu}2t$njHWs`uiJbY+W(v%E5CZo+uR
zF)3LT#Hq_9ZE%Eef*TQM{A-eC_o92tGHQtyhsfoye8Tq_N!7@kEHZYE393n|3#@cq
z5k{&uM?G#Jg~2grn^8SB45AvmM9zm}u7nYP_)`j{LN@8Yo<aQWt`t`MS>m@VAe}9>
z$xX>1x*mT{9RCG$KgZ<gPpQziGd0UoL_J@Un^OS<QRgNp{Sr({efv^ai?HD5n7b~-
z891Bjnz4a6wqvAOeGeg+hfxsb1mZaLqp*yxh~w+%VLL<V{&pim=yaSyth$pB?6dch
z<27}OSk;h#vUKEfmZNzeFQEIkBk5Z99cf;4@FN|8ZYoW178^P9$5;qw>2$yL8im-!
zQH_b8NN2$~avyFaFNG%wN9#qJt?jWSo|Qumdiqjai?7gi)G-QWs^dip|3vo<E0JdN
zJ9OW48|hTs=5S*s#~C{auI?<7Ml~h0KMs;~)qZ;F&AO7yu}{eTYscezVkDi8gOEk!
z7;jG^I{iV{8kI?Dk{?~G8|Zp5hIAs1lT=%s?l1gFp#7$h^sYna-XwB-Y%2v}`-7al
zT1=e$s$^AQCC+^_Nkf;DZJh!1n4Z3M^#8-fL`*<Z72;<E8dRUmhVf)DW2yt_Ch>PZ
zBh5FC(V~i@F`ZwM&d_zlzno8QR<xjcCnD|3F{zix>e5|mx!BDlO|MPJj|#|YB9_qT
z|3f5F4RxiO1*Va+u@6Yx$T9fDzomOOo*+6erKX<lNe&{j=zcJUU${vl+dkV#^ZIDI
zZ(U5%b@;4eT<J(xXJl_UChc$H_pD7`4wj(8cE)80u})d&I$=D)`LCwy1b;GkWh8z{
z61hL=c$V{9k^4cfs2<f;Q=4rqM;xcI#L3%8?tQltr}9qXaPH)O?G18y0;xvytwfUM
zN+h*soFNAugXns<Hz{R0g4lDCTn>3eN>#Veb^cv~HXBK&Sui;sX{LM0MuFNd5a;z>
zx?dMfw%-K0w)#Tu`D=7dUr$n(`P5EH$SMQJj<f`Z+X1BdXavPI$%R1Us*+N5hf?R&
zq;v8E@uzmC8cbS1(u=$3x-N}^tLylB`DYTsnWv=heuiA$t4UV9uvSGIAgPAIyAJ73
zF_6dD4UX~rNHtROtwGmq-AL@!o$8u5oXo<e5x+u1GG6~Tfj%5SoGKIPy1bZx8f>Tg
zo%6_Q;3(33c#3R;I#GyIKhpj0ZK=iwR!{{>yh*>&M3Kh-5tYd0z@^lH)0`b~?IoaY
z9SNxEO5(ikPsYnq={|oq8P{7xR$(=W-)=8CFt?;@Ssm$|#F7!8qTY19x}P+QTNB#V
zJaTWek><0ZNJ68pz9qr16?E;^iX0dGO0{hHneMM6Z-I~OOENp_7#|ZKl5u<xfj*0+
zP(~sJimAgfs_WlJNV+7E94C4^9)SZV{t4l)VX2ZI+Y)A@nb5a0l^2jf@E9`a;rM9g
z>?g;^)|2sD$9G}6mY^R_q9B~p2x#_bvNBF1pm+^|_8Ci7f%Aw{--B#LB+K#A_9A}f
z5xTCeNc?X><ZIa~!m-clNYLj_(^c<A4qhB3!PfzF-+Cd{Z@4oVn^qD(d=f$ER?~I9
zV_aK?NwAhlC`Zm-AR&Ymu33ZYyLkexRq)8P%u6Iz(PKQ-xZiM4!nIW{MpNdPeK5uH
z#g`h>eH$4Bv?S=Ux5#mpqaWlKsK6h0*U@yhD2R}cJUITZ3Dn&&(6%Y0`xPd-p5jQe
zu@fP0(UIof8C02_WeM~2SHho>i5(lp_dXWf=#$UMLCrR#dS@)f*c>mUmho&zk+$zh
zs?(8A!P`+pQEzKSI?Y1pTIV-<5Ot1`gMN+~-$A4n@K7*_X_;kniC?iT*>dISdiX81
z(A7s2N=|=l!f2VDm^5mcb^XZY)gUrEe~MhnHz=%x7F6Q{j(*@8PSC5zQq9bcK0nTv
znmsB888Gxfu1vdWsC$it$Uk#+l4qk;yY^m!`(eGqQPJVYKS27c>ss882;B<Hk#-Bc
z<D)uY_k|m+rLOo#vw66mdXzpgbBE9qUR38B`1V0nz*)_zy286F%ch|4W^2-X!-qZo
z3PJj^S*f7>*q2LD__I5nz-&8PdNiB{va4UhYY=;}C2AhbW`@H&gmt#}g0oO|@J*=h
zV5?6+tYPeF`c{Oq8$~d8vY%vN?_x)-K@q`@q|e@NHfbQxBH8q2z{a*)9~eZjua}|1
zds&x9z>a2{(Wt$TjXw&^7<ST8F!!??%7cn!3(>&b0d|F(9rkf-kp$sEcH>rHA7U5X
zhu_02X9hE#okb&b0{g)oXo>6y+P^x&4o-plqwJVSm?yE@qrp7JhSK<YoE;c~U{0_d
zJ_F?>8$<)qDR#y_XeP4*0^$BN8x)P=8vBpTV*I<#j%p3R>1@CRH1-X)vLCQB*x{#P
zag(iZ5|Q3wCyoYoHrx3O40G668rO2!f%Q=2v%_D*;eB?Y2`CTQDXuVh%tq12q=5aa
zHQM(%+cpe#h3wWZV7_3zUjXbSyYGvD@voS5n*r`Cw)|%lui2tU@cV|na18Z*%MR!X
z<~!D7I4nxoUB#f@vm@#t(2wl%*KqiWJ^B_E{md%IA^XOzr{}v;wSuNmt5own5#c6P
zKlP9PS>u^AfSUE{1(Vr#Fcq?MbIu)xr@2x6;C7zd9Nf=u)Di1J>dsYi>p{KYoWD`Q
zMronAHtv8ChHJ9FGMqKtPJK6ojlxRDp{`+Sqqf?vH0|bZR|cS9*$<9bU5j)90agy0
zfbeQP$C#*H&Gz}KLi?{_^D)M2H?Zy}P_2z@cg)$eF081B{wB71O}v~z>?fMQ2D5AL
zL#2f6+#O+kVM9&>Y^|#Mcxbw)xZa4}OSO(BLw>4@!JvXwzhSA*#i$ad!|sGCc|Ghd
zs+PaUf|J5A{AQmILD}B3p;g)ZE8rULTL(dVPY#+xotmP8vo_4d)s_86KnT0oCR3oB
z#0IWJB`>p6kI0Pn4SPB8M-xc<#sSdy1fKzIUH@ySX1#s*JZS4jFUMfgV8jY+$Tp;{
zcx|IA9Z)lS<AwJy?ljTp(N0Zm_YicmhQVmu=59j~M~m`j5l72a(RiAz>LlaZ`W($n
z+6=r3_gzn}gS1cc00cH<27M&PeX9nYX-rSx%qvqD(#0C2z`2#|&@HIk1~zUXuszxL
zp8?{-7Rq+0>|njHLyk8#TLI`{wmvrSv<a*u`b5?d{t?y@|54Uafh5*ZgJUd3txaYf
zH95^vO&rZCjr@j2u<g#qwalS=xR$HE7Y-|rPC}&Be_w(2tl7Q-+OfX9&95jL_wj&b
z)8B)sf?GnsX@CC`I32mUh^X7e@rb?m99km{DBw`Fp~_0^_0kh8<(Ur1^2d<v<Ejp6
z11Gi3c3hh~HG$iXV^YBHU7nVnLzmNA=giKesq{*AqZe>ivGzsdLHe@CKLFg1?YR!2
z`LiSFyS{_Hxf~c_Y$gsaU^rA|BZ__OPBM&PXTO8r{cIbgsxUe=e+=_P)^8s)kFd_2
z;q?p~u?z-h*%^t@OkpkiP?Z~O?O&mi!Txg{Zf~-q?2Tdnh<!w}|HtfaRG9+yqZz92
z*k8}VzJztI0f+C|T`pj*Q*|u|&Go9oU*K?qs%#lBy;Vyqq3}^<_yEjT)h7ed?@|ri
z39ty&nuU<<R>cp4-C<S#Wl)J%ZCQ*c5>&5`+2JBZ)vg9C&Z+1F$X!t_rvyx<s%>>J
zZ>t*6GrOa@P4@RxiScOMN2)t-Ks{3x>(N~AR8QukGS2G8^I*4DJ;DG3S9KpZXu7G#
zrbES7{p}9?`l)lPKr>w3>mO+DRJZD{#rq$tetQ9)4yY$j1?VaDqyex`R{w&DyW<g8
zs@fe!RUbbCS<STp>Ro-?QfwKJxXTL<&|Uq#;j7ytngsOh@(|al!R(K|Sa#Jo)W3H4
zB!Je-%f+?f&3d>tSy>tO&Fw=enb9f^pM9=vE;fz04sK7--krk+BH(VV=0dgK2ppZ@
zhMiaq{@5+FHk%av0n(Z8d*C{!%WELa_sK>bj%qItL(P)3>=rmZrhV5JqBGhaRIya;
zQy#MG+N*2f>y}n90_c*RZ!;OHulcKOp|eul@eOr#7k77q>Os9r5|~Hz)jz_syYa|i
zP}_{-5`Ogkee4U$FyyeyFj3)dvj@wAy2Ey%?^ixMs|@h(vEIRW()U^4NEF*t^|8H&
zF>*{a0DV+5%Q9$xU)9V60Q;-9RD|Jn)tpK|3sfyHK@p@nnF5#))#qP9g{qFyH$6<X
zyALWJuIh~}C3i>_6o=xls<s81*Hkrq5yf@Y$5d$EP$kepG()v210FI}rD(~XrCQPs
z%xu+tEM)Cmjw*+G=xtT|=HT8@ZNCZCJk?XmS>>y46oR_1szBZLfvSMA506wSpHP{{
zs#jg$>51x(KVkP&m4cH1+;i3F#xN*UnIljaXSFNk*H)@W=b~7x?uCO@+#0nTGU(ho
z^{Zk8V_&cCOo^V|>L??)k?NOIV1He`^9ZPP^+Fji8S0();P9q8XFr%(>OW}#c}x9~
zat=A_RkWDSRp(7aaYtQoGR*I)E7Rz8Pd#`d8sWa$I|9^0^^3-^d!+vR1i%W^V{k5j
zdtz5#rw{Klb&UnUey%o9S1D4T^#k=n-SR6`i`5>b0P{+1YYfdd>IV(Le5;=21*$}S
z^c|}9UcHdM3Ln))d9eGWK1cQaqINby^Q-zEece`SnkAvWt2AG5j)_~VIsXL)>oj)5
zPB`44xt)cIZqy8%gIa9TY>R?JSIq;wX53~?;uoN8(TuzeLwC)UKxlesCN78jZJKK)
zXnJW1J3;27Y2F-#uO^gI3fnd74nrkC6GM5qAWdv0q6pTEqq>A@Hr#`3hvvE+otfLI
zVYecRU7BG>5&mw?7)lsMYCf-rMU<viCs<(G*Amn|&AN&}i_tvuKoqeWrw*_?pvmkA
z=0VMd9CU$0nu(b(NYMC9MlgvQRdawH)y&-o^CZosnov2enQMm13C+9%H2$5^1Y_>c
zC2OKnVR1&2rXY&5nnapqozpDK0Q0=2X$mw`HLhh5_eG6eLXoEV+!-pDH3tp??W!iC
zBT%ks+_xc^bWKgljNZ_EyMYSc)Rb-yluXT|(lEHCS?!A=TQew(@=v*%phpni)_mFk
zn7f+R42nEWUs^-n*H|d$`9Nb?hvJduuf~u)*38d_izk}Xb-;Y8DZGuMP}8U$JQZnv
znS&;Iso8Br0~Kqk(R}Z<=8vz4{*7k*ZOGnfd_7=LqA6KO^Un{Or`@6YQL`!ypr19}
z=Aga4XiU4H<IHWKg~dwl!ebb&<}$_rW)0_B4WX^$cKwRBT+iLZ0WfYOH%fw?3-^T<
z4X&J|gQgo7JPz@0;dbT1!&YwG7}$Amcl&|q$xTXvirt&*)fX;&xW|v-(2q+!0j@vS
zsu!>WIQQyM4dncMU?0pCB%^^txXG=dvV(g@8G|q`E`xdycZSlCyST1#pdz`^{orX2
z_m)<idpVEY(2V9jCnLfb?hP$!_j4M0IpXZx&}YCt$f@aTd6?5?!*4vdG7o+exwo@G
z9pMJjA~}icm<g3*ob7MepWuT1VSkb<OOvlmZm1uqEbi%UP&wS-F7TVnH7!9fceo=1
zAiK*|rCdcmS7#T@?{ROs1Ns4HPht`GL$1{`=sf1GR6{TYoJSfWb=K}Ui(;krO-C?S
zYoGjynAT`}4?!^Nv{T!`V7+!deLXg6*Ia}r7kqDk?WQ%0P}!{2)Ph5Itp|P8JhV$s
z!;zQvj1C6g+98y=^VOEOBMrd$Y4@Lk&UWo>%FhL8+fhSZ)t2i3>YCO(7OFS2D;|N$
z(C!}%S*EsG8yIA1&qM<>TRZk7P;#_in?Uon_E|$vceMWP5pSOMjtDAW>qj}A`&v&Y
z#PmS>7v&=!X}@;11N5=B*Hn;Cv|siC?WwkCE)1V*V@E-?P&@eoJiXKw(l@wRyX7EY
z-e@1D!S1crI}V!fwdPrf>4SE`E66@;m&`#8zi4-Mg!wnEo$^G^{N%Uru!_Ha1G3e;
z8TkutAK&jSkM}QzfAtzJVtKARTpZy02LSCLUpD~_e2DMV0HE>wvTRTZ{8s^fkMK8^
z0p=)gsRHIPKJqN6<NWVKAv?+UpuLb&d{dgap61g>K;;Zyhmzqbyzd<_&+*$RS9yW=
z3Z?vSDqkrG!b|)XoCN05`0kW{xx&Aoy!}<a5q&zY^S{udKb>Di9WjG9wLo!`pGvd;
zEdJN0pl<Pt)M&gMe#A#apNo@~sQn#2D-pH7%MTla(DM25J>mBrU*iS*J>-jAKvjIi
zyTt(J3E%iSH9lXK_SXvel{gp474e~-mDgD9FDdo&j#u>p?*qSWH8ei*zfjus3!g{t
z`&YhGPq=j!`gH_zrSKj{+PKxiivmQpMyRwG-q#6!Cs3>x%GZR!Mq%MKMCKx7t_7y6
zP>wPdZbFZ9D7FX-HbHZ%Q0pI<dk9<X)Ga)P_>(BGQdx}_@fM1XA*N)(yEE!}T5#)%
zB1Q228_aV;KBZ?<h4qv=yeKSAfu}TKAoj1h%R;&YhgXH{5nx^u%611>x=@E!fj5Lr
zen80-HoL+uOZbhZ{n>*35Bf&r2$QzL{T-opIJKzYO514n1QX30?+eoj`=Kzm0J29y
z`3<ly5X@Lbb5DdPG~0M4=pLdn&xNJYh_Fa#O4+>^g3t&m#X_wCC|(I?o<R0Ss8NjQ
z-wHQ+fcakNy^X#RAA}s5<$MwrCn2cM!kgMa`zD;8g~D0nXkxfZj5r5swU|TwaINS@
zjlWL3d=bS4ad8+bu~BsW3&Cs>o0Y(YtEhR5KsSr?-C@2(>^Tma?&5@XpghEc0HAn@
z?~whqbKc^T^YH5{R-??ipZKmco>PEmP6Aq>ICwjlA!0->R6@mDw6X~kyTqd{!o{{3
z2z!^<i-xcW@f4*aBE@NsK<yFR)<YC~#fmg5ix#WsP{fGI&%oR-hS4Y)CyEV$Vm~PQ
zj0N^#QAb;t@#69ssLV~VEDa*J#4<D%WQ(U#V4o{aiA8Z+)DMH-yJF=%K+6-|u>|Mt
zi~X9w?t$2X=5~+7*GpjcSS&LHm`_9vef^$_S2}`ODBf=hl_Igr0Z_$u@!~v$@k*R~
z0rqdiNZO`&D`G-{uc%n~1jT!Cd{0#Elc*>6pT+$X;P<O|`!GPiiC-xJzEbMC1!$|J
z0qMYABjp$%TPuyC4TAMjxn!tpkSvj~bCI%dLvxeV^$k?qBs+&wOWbBDkTx~9O57ZH
za+mfxL+B|z?GM9k((~~!^p-}Oq2eP=3WmV}Y5oW><D@e*J{^)4T|{#omI5hTk|0IR
zMihzCAN0l?m44$OOOo1NgY3ApiSp1Vr0FzYJtZBpd&5(*<T@MV8OfbC=FdvoJ3;lF
z)R5Bc=cNWkh$&U-HUpp+C3!fg%hEhr)?JYTXcPFlq#=jtQd}yS8PY!5|F|htZv;<S
z($2DY2DhZF-{2ufQrn=JD-F00mAg`<Dt3^0QcyGu?@5WYRJ|`PpuNP0l8HW8kECMy
zh8IX4v`za&%HIf>XHsGUn9rs6$X;_r(u#p-k{6PBIKYaf$UTs~l7i^t{YHv<4o`0-
z-2fEtrAjU+K1l6bqt!l1gI=id{(Y9z`Do{_Qk@5|_$Iko;c2DZk~Sq*$)9Zq-(OCr
z^~iSlDD{LuIeaEmg5*CgBbX35v<;#Nm5n%Z$%V<sX-*j~|4tiAyW}VwB<CXJ-Z&V_
zManVNLG6*n{s7x6`(mkN=c45rSK%o}u1Kq~{c>HJ@g0z>Qra|5-c75(LvngMs2r9L
zSB2jMd3FNon<!t)!DBiq`&>tnB>RPcc|xAo1ez!13AAoYmgmsM#cBB_eiFc?$Rpy=
zGUw!Jp`b3vslURXJyqVPMckL<i_<`+$*n^`U6JR}Eaj>^U=!S5mzU9wV7lCio_&Vg
z(F683<%@S9%aS*)0d-4GsRX+mIcqjrHdlW067{_!$5IOUt~@XfcKPz}cM<(PIr<Mk
zKaj`ZOey!!F8f`F&SP0a-K#)W(N@P(*^5K*Og<Bb;)~oS0%&WM&y!GiDBd)u^i-nU
z5YslLNn5!0Qnubl;jO$c0n<mB?SaBqse1tie#*5{aJXIRLd)C$Wvm5J1S$_{U<*<_
zYi`opdpC!AsFIGOd)y9X<|*LsRPsMTZ<jK;4C0DZCWHZFkMeteFfS?oB~VFIp3!E(
zW#t}q`zuPpT9{u|Ry9F!O<DL6#dU>UiXvS(LUuQlIi*o#C~om6ZYpz@p~zHH?ZXj!
zo>DA=%vS~$qRtPLTCpe!l$%<F_C#s>9Mn_Aa}|nb%JBMd|6KV*yH$mX@V6E|@L#2L
zI<8XX_I;RC4aq^XRy&;pPW6}@s6&m(e<0eL?`wcxOQ3E1+L8z0>a@307Qb%JX(-j}
zS_`cDQMBXVK=lA|HC%zM8?I5J3I>fQ;g>pGlM0ytZCXg_<7VZ%!K(TA?$B>h?KCRT
za`+24Xf@vloYrmr1X`QJ$fI&?ODOZy?vJ%VYadK6T*p5z<JzeLPh&u5J_<@*USao#
z>$(}Iow#nHJ_xJtfo|ZBe4mQ@sXf}j<zm$(I9SCd^gt|b?3r?){Mo6cpcc%A3<YF3
ztDXa9BzvA7;XZcGRUX#(&xLR11+`7QW+b9><?UDD*^Rfy(kx;#|AAJhTlkkA5N_os
zjzBHl`PP&h^Wf*xB*c@y>Wc`r@#QHq=*5p&0j4+KwG=dcc&-SAFaOVWINi?AG66Gy
zk7)#EFkkivs1Uvur5Qu{aB74de2aMi+sTi$&w|A+K41-Ei{PuoK)9P9KM2A|zGF)i
zd-(ITc@xE#OoiXQe5GFi8qH5vq1eY;WHdw!Ur3t+`}yAU!Hnf!u%Hg`;gnsC<KJlD
z;UHfiqd3F|;kP~9VZJ3zFyi?SB{WY@;0x)yl*pH-rN9w><01relz--fxRdxLn-SA7
z-hL9Y<9y0T6eoD^BVZ=;8T4A6=2bLKp5f=yp`^2X<IZ5F@FzOK#W{XP5W+ssmwE%g
z7kKLq*j?m3+QY*ozHT$@(_v~n>;hW-GC!?8?62^;Y#3hU&+7nljj!Jss@M5sIslWw
z`w-|&zF9UvGx<83QDpJs+C%de&*3LvTsCj51<f2jf$}!Fd{-WrxA_j_{tnL*%3Z$E
zKWNcBeqwXVQ|0rs@GC7$pXYc&c%PT@0rP-wH5h&$@|Q-UYLEC@l;3>Jm(XITfLD><
zCwzPoK%ep(XyNvZkD<nY&Ih)ItdQ?h8WiT)_u>8pzrzQ`Oa9hr)V`QMM!EV|ytO@|
zu)pT3&|>xt|CK=B@&&Xp@Q!auhu=#0&y>vk$Se0zeBzrVL-v*5wjG+^_@tKrbrv*^
zmAue{K45EwFmkb8(0QZSAT-fH(?w8EhWRGpY%x?^1+Sfuxd|m<C^p-L`qU;{gbg=9
zZWWkm0Cg8i(Nx((nDGLXr?5UB_S=LY>Ox+^z?q<YgsYTn@D(!ef$|fYq`*_C@OBD{
z9fGSj0u2*PH0cT#Jno@^b_%s=INT+SGooQ5gySEevRkmfFaah~s81QuJwgEGz@mhx
z1Bhv_FpEz2MGJfAIMhDj<2<Ou2+lm1`vosbyT=M11Hn8XG&%;mIAL}>PzQxgvw(R>
zh^F<$VZlnt#dx6=<uMY3=Mrj`C=~8Qphtw0c1rgj6;iu{n<P|j4*O$5$$3~D7dA&h
zc0yQBdBl@K%mGlRgsXJiAzAQz1nkqo@9Q8tBaCi<U{Zu)TH>7(4tD|Ad12W?s9X>*
z{h~!nG7X;>h4c97A$Lhgp~G}(LZxgw99|Y)-iE^~Lc`y{y($#Hgw8c#P;Yp;E-c>)
z>~tZD2ILz;a&LfU2o<WLxG9_%2$f8s=_O!i2_GNA?v@bw7m9456rJqL5&8}XX0A|;
zI?HV#iOxpc5mHwo(7Qr+8|8`fgm<()$`|U=;fi}gC(6y-7g8y$@j&=zF;pK4@d^Tc
zB!nCQ^;oz{Nw)&w^e@nSB3w&GFi!<%{1^ZWqNP<KdoJvt<wBv*mCjcc2`XyX7s7|v
zFn=jT&?KZ-I2$K2GS)}6!(sSZDE5r?u-3gtry+dADYSv?FSaQ`CAN#gRkT5XIQA)u
zK=CdOY(ZjU&zBxnd#mY)VTTw-J6&O7`(p?tT#Tkw+)gogB8pvN{4^91;>Ibc`)+Yt
z8CXY(J!$;jBgVTSq9`$T7i9ayL>m5ML}@&n?-#4kd^1*@PJQ}-Sf(nf5GQsF26a#z
z;R%0-!~ym}fH^D<rM;kdv1$sq31aYBFcU=$4FyNUn}vw*s2ERkgCwyJ%~_6#3uhpv
z<DyR#iWB0pY?z-E|7wlml*rS7pDdP+hURIpbWap##OPB9=ByY>-{KUp)n`DT6B~D?
z{&QZ;Jp#iE;xQTRlPU%sLZe+2-Dx<zB;KO$bDF59?AT>dOB=>l#HExGy(+rI0Op#Q
z-x|;Ax>!64*y&=;6#%;-W>cmiLv*LD)tlnPNKlz#FWRQb61P`^<}I=549c@)i~sxy
zm>lsrovF+f54xjHx5a`sut1XN3}ko3rsok;p2*VfOTIX7Jz{zwW)1<`L-7Wkq<AD^
zm`2|c1AD-(K-?Y&lqX^zT2Ma~yHdY<Cf28v#&gmB092tkx)RNyi^N^^VfaFfqr+)0
z#qM8WQ7oEIpiZyE>_uR{77Mg+_(pWU3&XeKWtv~V6PFGLvqXGe383%AcXXKKgBWW;
z8-5f+N+XI-VlL&HKZ{*Dph>=nweTxYtp3iLf%#4BJPHxoouxXo(pxFD3IymXX<8(>
ztEF%6fVM_r{Gqy5^4<o}b<)^jfLSjs2!rMZsZtj-*G8!gEoEJ#F@^B7N$NwVPh6$*
zQz3Jcc5a2k&C+N5u7lem8G~THRkG7og1b~P0d^jCsmeg8dP?3j&-RukPlqQTY3V-@
z`bs5~$@P<NB%<(_UiLyT+oc->8XzsUz+s>?#T`YE^ydgLgQc<q(Rd-!uT5bdDy^Ok
zYKJ84fQK;Y$S*(%m-^G{V5fAG(r~*Z`@?qd8zJ?i18=*fJ9K~oYu#-KagVf*X6sQ>
z+XjexuT-xUsAwsXj#KQDR*wTSMoMV|yZutdL!e@%)pYXufVBSr0*#Z((5&&Gbc_1M
zAxYO85n`F!1?KV6c*;X3NE7X}s7sWR-yp;z(!`nI9+i3w189=ebr+b&q#iL~9+%ST
zpvnnJp+li3rA%6sosx=w18B0;i&k-`r6b!B#Tn@XrIpW01uNhwMQR>}n9fP%-=jD$
zZ3{p!7o=yqL8VGA<?L{AQA)!!91CM->Va1zrU1gLl5R2@>YCJs-p%XMtJcs=mmb*Q
z>4ua{-~J4#Hk~uRDNWr1hndnTdN;EqF9vqEBtsW4v!zOOFe^vuYXM5G#Lx=wwv<O1
zp*zyb{WO2NE7?j=i#*9^Ds=Lt-(4ZRC*@K_?@MJCqZSXOUJJl{C=E%3<|FCRYrs5~
zGU<3vfpp~%RGvu7t3vivvQnn~nN)u?z@AHcm!e9A(n&qSE|S6~fqEe|q2i@v3X<^t
z6-y`Rtkf&1^H<ovmS)$3>Kkb+y+?1QTC{2WPD*J8_a#z2+5mbloulwSNKP~af0SB|
zg~2DO{6)w<OV_4@`9+GO&4;g27fP{zlRnUCCTBU6Jgk&I(pl71axGdX+E>eoG-FyL
z&rO8RS~-N$;p^nZl(1hfJ5%y=gIshP78~W1Wx#foPfvw`oBY>cP@ClrwAJn|f4C0=
z57|zOHBb3EWy-zf@IRsABl}YV!B=ib4|KcSl@1gK$SZ<T1lr}iWhg`B-zUOFsJwLp
z9PW?@PDcyvl;bXf+9lt91H%aUKJ85Gk)3HwiIUNmDG~6r5H6x+9p%&Z$y&-Z#>m%b
zk+5G*OGGfS@&?LQ9gw+62sBRi4}s=Ed20kv4#~sU(r(FNxhExY;^qBK5KMwxCK48j
za?ySiM`WK%kR6q)zk{bFxjP+4Iwm)c2X$N?`Uqj4kdq6ca#Ef#1Py#jKIYlizntAV
z9<ijzYj(rmIr&y&w844VnfB){$lH6vPpVvz5^on}uXeD$Bv+*uHBEk=1(3_~bDE%C
zkx!Mt!Bx5IUkD{#F6aj8hFq444Efw_K;M+-xWZAUybC`aMoyuKHi2)+!|k+3lP%A@
z1H&9SqbziC<?*fH@V4Ax19a}lwdvO)cjeT4_|20~Q^(7f#}~rjp8Wd;#Cu<6X>;>|
z{InVD9?H`@0P~T&Fa%(ak!C@l1#(L|YWGB5OQ$!V%1>$W`b>VPqm}7%xo#jp3+02y
z!7Y+s`or*r{7)X3FXeHwVNoozXW;&oJd!?}ujOU<TMpbCxj&^c-^wrPyY)`~X9&zo
z<dGX8doPF8LWCdWx_`moqr8vSLZ9RobjbX(9O4Dp7x`WsouK$CKc_Q~-{jiKKyy~^
zQhI5na;FI_Rw+4@Wmv0}d;@cxvgQ?BtXGcGW7?oxnFWK5$^+U@bW#3k4(v?|(;IfK
z%B^0ggqspTi|ftGc`a17C~O4;vsJ0L74F@YvVSpnvptlGG*R<Z9*>5_Hs#Paz<4Qx
zXi4v_RCxivKFT!OF7s6i=@$@w%7vAH@mK!p3FdaCvIXV=ijMY#1C=^7j}B5+Q@09M
zTs#qdh_YFR`%q<YOSIt*<>Vx&gegxcC2tQ`c6Wx(PR08xxVw~e$`VB=>^rFLR<6%P
z5ve3nmUoXbRfCwKl&;w@*sBbq4ZUck@dCi?Q&OU!5~B?73+8_18!g{sl@i*6IG~tm
z1{<gNQilGZlFtDXGhI62mS9&hXv-y0QD_(Gh+?K+cN|q(QL-sX30w-8V@lX9_&u(C
zi~-sSrT;ykom5WIsn}DBHXP>3$~oFrIjwlRLv}`)+zc+xDwbU^NKw8uL2*uL)DQ;e
zm9|NcT~JEVHfpM3uTd9qUsPt$`s|WYk+9R0fM20{SqY}C>?_J#TKip9qC64BH6?_a
z`?~TMohwgQGU({l4J8C8*pPN=pn}0o<<?2aGL?Sxq03T|+QH#1W!Dm@WGms9ppv63
z>W|`%GTy!eao<(CKZI(YGVym5_Z4Y6+&@tE(emS=(wv5{0%h?&FrO&&%SPm>jI>fH
zRH`mQXhlk;6R>-saJ0eoO6fir4qq$6A!xo)F3~9PR_RQ`(>o=~45~y~y%!OFR9d{X
zL-mvL#{|H9RtD0cmoLgNH9UP)4%dLrH>ENDs0-(;d)FV>D|N2NL9NoYrFVO^E`iR4
zuF>74oxHWWg{xt(PS^M?Wb1XM+5>EZ?jQUy6K<of3LO`5(UtxT*(TlRwLo#z4NepA
z{<-NIJx3Iqb+anLev9t&FraPKEeb=V?mGWmxbV=WP`<!ZSF<Tpw&^UBP<ZK5Y4PQ)
z;}!taN2j8!w6Crm{ldae*Sr|D_t(93h52?}i@i_@(EV8+MWF6&B$z?E6AkFg8myB-
zK!)hD>CFk%wOa+l9l9vm;tkV{p^SI9PEWf^J9SZwfW1pst{fta(B;snx7|8F6{tvE
ze>&N?N5|}?cSIN33Cz7Z13ijp-TS7H?bD^w9#M?0+Z|vY&;{Is%pRxnr$P6iZVjcZ
z<8?>qJXC@%k-mG0x`#As9?`v^r+rj6`6x7#bc-(l`<U)vb;yqE<~BkUCv@o+*qzi(
zSpv{gy47D{kgUtA2T!MUrzwARMmL8Xp4Dk-`IVy6#=!2JT^HX1<$2wdXcQN8Cr-j5
zRrfm`Ji4e0`2xdBI{%9Bl%|_NU&zb4!IbE`q7z2}?W*o^EYPm$-qb=&*L6kBV3)2-
zqg>Gq-QhUMGIW8fpm|d_eJvhZrtWD3P_lIEsVQ@G_9EJE&ef$;zq+mKLOW!4bc01O
z@9M_mG&`54JAD?#eVr2x1`l*Oj-0Hn6J-yIbY4r)PA_y@iTP63l0IX_x)ry8@=Evq
zBrsp=+&hALqiaYTl5cg3o}vxk>0VMMx<r>_Uw|;)>zdeL_(AtKWmG=uBK`*TN!OQF
zQ=fIC=A-zcOQWAXeAPMSLH14e^aI>G>j%@Qw^ARz5}sD+2hbMyYW*-uk*?9tEQeyP
zz6qsC*6GuRpjfXzND1K$`n7bJZKM8NE}cho(Pu3N*H!<%5@6i)Jz4;CvwoiEyd75i
zsBR!U^ii~J<*EOTj(}~`Hy(;uy!7KKdEl*&rh}(G`n4_K!B_83`%ZrPH}k;s*WaOV
zx9dYI03|@*F9lSfzDR*xkp3bM%wT<uiHI{qpGLpf2-W{iCq#GX+tZsJrr&HY2a9mM
zjq+YQ^|$)MVwb*u7sMH<zcn17d-PF3prZ8W^AOWsefBR<iPqmJ1%rM1x0HsC(T@oP
zwO>D&rZutp8b?s+1A1FEL=mSS&>Pf2{YnmDAJQ)`LKKJfS7;6zulH?8GyepAr#c`L
z^-;7#bwpp0k^@Ke?i%<_(%0St`(yg!v^jHJe~q$OC-mjqfOb-Uo01Wy^fl?xCF|?Z
zp6+RV#3@i`^b;cx(^-9u%`i{Vv$Q@ur~myPTJ5|(R1Mh$z5gECJx<lHYYK~t`tG~o
z{*r#qP*gijznAvsF6+I$0D47V$q9j8)t3_x(=~l3ni5{uA6|w))AdiOxo+q?xqz9W
zPo4}HH}xxNXE{^<j#30!`aN`RAY1Rh5>e#ns~rMZu08_?4(!}*{n=m`-qFveLo#>u
zP7M)Tp8h;#bMy6be^mRPeqaLxb6<ac0yH1!J#j*td#GPRtK7%>PO)%UpieFb<`aED
zcNjd?XMP0AGrjK_)c(0Xf$|Q8db0xaB7Gs9hI^r(TnFa%m-?fW>MhnsP}989uTz71
zt8f1&RNv_fY1Amuf6IsLy}t1}#Qi~Ek$!ObQD25mrG3)h?T4^G>u<M(!!P>In*sV&
z-+Llz|4knmiNe{C$%DDt@QHrix5luAj=ZcjT)zfK>+A-14a)Tf)n>qKF#JP%jvEb8
zl)ZK_#Np2)aGMNHCaAa?>J$RT%}{keR5lx`(+t(!aG!Dm9tP(lF!wZkq~l%N4Cm=o
zwU^;tc~slm;C~fNAA|2rsQ4Oo4@VS!hQSdi{0;V@G?H#NJfwU_fMF`79|8?Bat>UO
zA>tVv1{=E5Ns<u5{z>o~Y6zpY*kPzoQ`0a*cRH&UZa71oWv5{`CCGOf8r6eJgkjze
z*zGo4+XS#k!vs1Fx5rS9&Mrn7exnB3Ysj$ofZu4t@et_jGc={{6=S&n88G_|Q{3Sq
z)-dTCB0XU6p?#1z!%g}b>Oq748JLF*xis-RY+$@$5O1hY{V~B%><{;e2G4Q8JYu-f
z51}3X9@B9{c{<>9!f^Qupidgk@1~uLQ-+z7K_(lbX#RKFkk}Y7XADEv1N*GOt1~>M
z7^;?mi}Qw2zXR=pL0cP9q#8cnh51Fpl4qbU8M2~bmu4u{2bxz5`aYnp8pgPx5w01A
z*M!}5Lkj(@G2L*E@*Fn|U3$_l>@p3%9YLg7hJLiXxMf&V7xvkPph~dFF^nAz)m%en
zXSCOCgQX_y?-*7!MRC_~fcCfY486xA(0oH<9uDsr79s(_-8WbZ0QSJJy9m$^4V!vE
z^O2z{jsK4gf$o4VFigW<pq+bSSe^^vQ-h8+A)guE6roPf4ehD#6dGQ6f>~rp`U}(x
zL(vOhzcf6i1bMNcb1`CiXLzngFeQejlofk#81xLx4+h^_Q2A&Gtq8DBhUJtg{%rW2
z4nKV{jG(;ESHp8`oN)GUhSp@^Z0r<**j5@VR)KJpap_qIR~y?<M_yyROFI|qjqPcb
zy1_W|7z{QVpV5TG#TZ7j&`rj$&xp{~=t)xuH{-e@FgF{wQ~F_x5x?!gJ7T=p7r}TM
zM^6NEoAGTn>f&WLuBV+XZ{u~^r0_9LtpiYBqgPGn_!*bbOX+W{a~+`Djc>_sfN|0j
z6oJP2l)Dcx<{%f!g&HpkVD2#LqhSzcT>KbRxN-F%6g!Ozt#}5zjMXWL7-5X1M8$67
z{2lNYX|&IxCf#GyzXvzUxa>V@vCnA8hH8wl<_%E$jVS}55^Fq2d9(w@Z?&NrXY9hE
zWeysr(T>R><I2H^_pq@b9GdaQN;FGJFrKAhHqjWp4zeT06AFr>#u*O)on)La05P2~
z+U-X`o;3QLKm(sLo?C_RlZ`Haf;w#+B*Og}qck6W&l*2>26l?EHvQiEoN*CN3R8`9
zXdQIXD0l+<l5s4(YH7wj1z=t_Hi!Z9im@JLO|BXz3`JX9GaecWzt@dzXa$~bEWAqV
z;~U1*_uyt2r|*V~EaT)cu()OH`WtkzjlF2AGRIiH0qk>)@2L@Q8zX66f5({am`54I
zb*N~bvF|6?<r_0-FX)~T6I8qhM%zN5JTkhJ2J^9TNeb)=j5|-m;E8cZby^=kHD>Gw
z_A}!c4i$ZFyg>(A3XPj7`%z@<SREC8VVv~^%$G*Du>dVLx*7oU%2?_i!hUV^oeu0b
z#_2SjDlyKb1m}C>DcbJ;U>q<2o<17u90b@W<3s_>&&InnP5ELhU4~9ieKqEFg^O>-
z)TQ9AGWDRD;%ZY{+S*@Znp+LBwWhQ5g<fa6x(&?rrtLK8-(Yfj4%tT2+a@SnOfzUE
zv&j@l8Btf$pXp$_nJjcJa;xbV`lAo-rcwJ4y@yH3K@^^*hIBf{zRgscRz6;)=_6p_
zZR*$>Tpv^ac<A_=N>0Px&y@W)-20mr(M)K&sZADCf=tuDplZRU2_In>Vk-L?MW{*h
z0J0sXn~(8a!%U5$(fHw}?zGa{Y5IfSkzFR|9AHM6R5Wbtwwt=YL3>4-?$QKhuSuaJ
ziP5Is55U}K3Zbt{jA^qMu=ks)Ux!Mp$(Odr513-d0WHq-jn42NG%W~4)#6QIGzUpA
zy`UscqN)5ypd2w>xDWHArU&#F9g<A7vp^j))uT<M<0kuNnsJ^mb-WDhlcv7YQJgYG
z@z6;&b#^SXO|g9elVUnS+ehb2n`jkx-V|OR4lkJcFGrDTy1f~)izX`_FSum-vm!!E
zGd1l4hnGz(ZF5{PU8WQ2S54O_-<WP%b`sPLlif~x^%<rGg=mwTrr4^WGEH~tB8n_i
zA@!tNCM#uOvQ6za0WHTgm5wdungR#H;I_%l4KR01d}+AIH#r*+%stb*nJ~X^`i<6I
z4@^5fVE53JNhjDInFg9*@YqzFj)4@IQrzkE;uDjej*~t&t;5oXD>U7qbySgwq2c3&
zX@5PayfhhCgDN&X=n0rtrs{gM+H2DXcNn}e`9#9tt%)rI**lZr96~EGou?XpG##fD
z`6rXxG_=fT)35aFmM^B%C6IkJ{n3x!zi+0hMZk78*P}_qO0!2H9Ii6w(1TrV9ykPb
zT4U~lUkY<;&9!LqveDdO6zpBhBXn@T$-INo_O9j*)UVvkpXb4Rv-!OdD(>dPwDR{b
zccFZ+r@2dgsBAM=euXH!%sKPac>lc3-h09IG2d?uG+%SusZjMZpR5OafAbw$1#UN+
zhe9R5{5%^i8)#0TEv_JQ*>MOh*jzw~#}IS%Sg3@W^YVec!#srMtzqU>0@^v;oP8bC
zPV+tboa{3D(o`|RyeJukeYcsV;}4PMfK(XnF_&BdXq4HT^6q=h<7k^B+H9aX=05W<
zTFA$ktI}zL{pOgS2rbsUn$qY8%)RM@8E3ZA`MrZ?Z~FPrA#)l%ro(2I2AFtrR6eSd
zU}lgO;1bOmI+$_9Zoaw>)jn$Wn2jRI+?Li%$IO4wTI;y^HcfL*n9I=O?4<cG+PpYr
zP8b7E$>!9~P&sXWxDVK8%>9B<iL>Spl&DWJUl<JRbLQsFL7g|BUjXO}=B*WBo@zd|
z1O^w)FH#}9WVV0FM2KnT&<ND`vUyBjz+5r=t%i%M=DoB(a?L!)k&!Z=s|}cRbJJfT
zyJ4R60Y!#6HW!|5niu-RF4KIZG?-cDUO}+CW%f!0m2KWdgHVq7KJ9Ynn&;5p2e@rE
z(*FM)bA9_q=-f4r+yOGrJcQ<v`DP7u@_S~l+c3OuzSSEl56n?70Q%7EN1xwE=9*;i
z*qqo7)Kl}UQP6y5j&FvReQtJngqRA=rRYR{k+}km7cb0zcSiBjT>Th46q`3t(&?3X
zMict}y*77s0@@oh6ATw`&6Q8U;X88*HFt^mULYFiz1c`dy+4>g(d^-)d9x?bKA8pj
zihnkb*$I^|=GbMx{%Ve7;rE-FeTn)yTM~45b}KE5C_T2yGOG*hR$E#qkgc)IUP-4H
z*IF*nd~ls*F$dv#%Lqy*Zm?9j3z&_Tx->GmSYq>Fzscf9f0)SCa-uFY-7Iqlg4%5H
zr;{jKEY;{QhHSO$qgHpfRBDMpJuH9F-?s3y%x(haHp@Pmrg&Kfo`$)%WeYIvoR8%=
z4e!2|#p~e0&r+6Fb^eyGlw{v-c~2jy0Lx!A!US4EmcuZ}a*j@*1zSGRG9kp`P6JJ-
zWk@p^?68D*fC{tJqWXqg5@?pS(<01AGw-t03<VWoDeenuw`B+=Xzh`f1szcCvG`ts
zeUxP-y{daHbCN(sTc*(AseP8Z8-NyLDf|lAe#>HN;8=_IFa&zQ@(b+<##!nwKwBKN
z^mzyDLzXtwEe~6!Ux#_T#W@Hb5-d7OQY2a)210hkQs)KCkJ>HMQh=Rg2~z-b%(Bo1
z`{NcD2A)n>>fMFmNy~(@usChWdjN|wmJD}<cGhx`rt~S6m$XtmXL&%U%g$Sl_XBmo
z5<_QBQY{<xfWBz?WjXv_vdEN6O|$$$UGB1_ZDn9yvDlr@fxK!tMCZz`SuWF05UyKV
z{(|OCw{)lc)(uN*>RuU^ft0_$X-TKwj%Qk&hCwCE(x@d=Zdtm~1R>j!$-+FxQY{Nn
z<XWor19jW-`$dF($1<6It9RF8>JKW<lD-K3@-0j4gFxQ1?9l-GzGX%^pgpi~lq7j*
zsXPXr9$Bi52KHl%tp-2~EZMaC{lpSVXOW*;+Vp|lGs|;2Pxjn0l@2)+TDtgyDzY?r
z3(XgnuZIxDOUvP=fG)Otqy6evmZOc};kD(;U(^_HEDvc%@vY^>ZWQk<@o~T|v9xXo
z)%TV!Gy(izc|c3?j~2H&Q2AtWqAC4n%Ya>o{)^?0UQqdJ$)WD`&9aUKrn7ZI28xx|
z6Fj0=WlcQ^gVoklI>NQax;P$oYpu=a;xCMF>#W>X=&ZN4q?OwS>pwKZ-e|qr44^L7
zC3O5_leI$@+`C$TYXTTI>+wS<Hd~`<(A{D!=!Igd^%~6s-L1Bx0Q0bJ7z`Cp>*-|x
z+h!d^+dE#?Z-1ijwieNGQ6H-b(``HFYwbH1s(#jTE@;aD>y&ha7-)T81;GSa)dt9d
zt?TI2V~Ew04zPt<Cq#p}!}`1!*kRVCD-dD0^~DlIvD0cb0DG4;d;p?|u->3m<ZdfZ
zha)1bvzNkdk9A%OWKmXs+KI96wR-&mooMS>N;K`Wj`4*~jP;KK=<K&{Z3CTHYj3Ld
z0qfA|a1m!M)e;dNw2q;f?jft{Aj}V2zfr5jTSw4lLW0$@8AYP?PJL(|vCgDTfuq(+
zX{cb5^^}O>m^DC;;<(*9^A5@r)?(VeK50EeDcMujci-SC*?Nl>{im(_==DEi4So;J
zv(}<0$Wp8ynj^Gx*70RwaNg=3j^}g1x`|Tesn#?v*j==G1)xfotOMJ?eVX+X?ZaNS
z4*vrvSFB6^1j<#beQq?$Yt{hDv0S(Irk$^JtMMjOZ&(LaN7XW{i_*~eH?1GiAj`C_
zdIBoTT7#B1x2)x9*_v%N|At_4to7c4nQK+kV&}Fsk9yf1Yx@v{cGo(ECiZ#Ow`RD{
zw-!By?4EU!{VdA+);}W<=>uyd<)R*1pV0QuBWtJ`hL5dNP9wAeYu^ljKC%Ah0vAuM
z|Iqy8nYG{@G@o0S(4SE%w6<&rgCc9|m(YA+O{Sx}FRk)(Ko?v4)3)_1>zujJd}lq-
z7d0!f=5(U`%X{l!Kd64ND#sxFXgyQ})lb$uZ=ij)7Pf`MFV-@3L4CD$ptINCtW)V{
zo6a_$Td2%R+m3mlR@v6kBz(24qZg<(ww<)_TWf1ZxtVpg%Wg1VZ_9XrU^dv=4M43o
z+JbHL7baY64=y6$O}0uY5W3p#b%uL4+pqN3em2`m-2=77c9_QXtu{4fKHP1;(l(8U
z?I?YfJZ)M^rERmN`9bDo>uiRmw{1VYBR;kpw2kd+<3_@vpKb83(Db)$rX=BZ+eb_|
z?OcFuR0W^~+NMy>A;{L;4>b(7&Cf*<V$-=o7HS(wBhwCB3vWaiW(%Msd$`R^L-$Tw
zowlHM*-Bl7W`ynQUNCptR?=~?NZW_9@U+J^C<s)PtqJXl?X~qA0hDOlbea{~_t`!^
zMHyo&R|1FoZIKO7#M(^s^REN8F(UlN*@VGh9<*i9pRqb*n?@;`!?w#bqlvd2ISsS~
zTi?b|Nwf{5BZ)_B!+t|dM{SqroJx`{r4<a0*@9-l{J8BTC3sKR5|6{+q}}$a4q`iH
z^Z5(HWZTUB06lGs+zRT9EwC(L&f4-Ry`Ey*G6HDlZ2ydg%6Z#T%8OsH{S$#_kZNlb
zf+#N9=F)EGCEKS^7^K;%(eHyU+aA)Y>WZ!Xa5%hb)6-1znyq^`Ft6L}PLwc8x4Fy)
z_lE6QELtzac1r_cmaVrJJl(Q&PDLYR+Y}w_b8IUqH<N4YMaM^O+cL(1dB^sq9vt4a
z4WWLOXL~mjcKJ4UI-hpW=DZ9s-M3w#oX`WCFb#GOZF^e5(IeXvdnXt^wv9UrVS%kz
z4zQotmUe*fscoJa*w1Y9HbdpP?fM}Y7TQuq0j<b3mlmThZ02A@|I${S9(u8DH0|)c
zvOQ3N`Pw#C4X`&h&w)UBYx|4N0KBtpiHCWKt$a8ld~ds|wgdZvt?O8zeY7py0_u}3
zh?23NZEL!L`Nd}Qhv8RS(NY+Gvkj*;gtJqbUqG#NGSMOJRZiUBaJbs3eknLy<Ft#8
zUaWO$nGC<{oUX|5wBAXiN^EfI`y9|4omSA%ITt6>P&)ay$?0)0!gqDT|2YR<Jg2jN
zL3OiJVh;Rnaay_(pj(|nKA~`TI+g-752qURA@Ov|S_GACPJ<~C;pG&&9ZYYhUU|Uw
zaWWr+dtayKyFvLm6|Y2H{GEC|gvxd&o+g|DP8XZf{zITsCT-LNIZfOI7r{=kC7?o_
z9#fVu)af;?6LvTq-wTT{rwU)867J+x4%Oc2l>ZjRE~jb@;UdCm)c@n?y5q8}zIbJ(
zWo4GVd+)tSGp)?5v@%<cQcK%q%gQpXeA#=+1_x7Q35W~<Whlr-_EJ!$Aj821h2Qu5
z{yLv~?>XOd?&W>%bM86kJ}kf_;uza0tsBqa(Uz3JI7Ua}M8@)W&`M%3<X}0?aHecn
zGQ*X?tSJoHmyk$h{OSSLGmO?k@T4)4=%UP7#w!WvOlN#20c!^1ZCgw<laV$BmMn%N
zg`#s9&y!=4%Xo<5@#h&Iv}5c7<2Txp@)(s%LGl?d(jTpW@iaN;g^cxdKEKGgL`ly}
zR>toifEF=4n6RRlahQsaFEiFtq^N{(qXB}YjM@>HU&bgDp;gZ4bim41FnIL-tYqBS
zj#d?;?_;1;GdTI+yuyf}$bSvv!LKl_mJ$3f#_AZ|6mh9%1aqOjfwA!*#u^#cHB?U6
z#CX36g3XLp`cg^@!~PXuw=yD*L!yn5Oy{txj4)4(U1L0V0j9Mxz6pVf4o1Hma@QGg
zbbIXv<D1=Bu1-ekcaZC1WPS_1-3+{q@Zd3CrNd+|Bke!1^fCUTGyhEn*Gi|!eui#0
zBnB9|F@WA;?4r};Aft|AcSDS!B_P9$MH!G7Vf;s7<J%0+y)fnu!)*!zcNyykAaIZI
zJO>Lj%2-Ng!!bs4Gcd;)Q<TV>U~JZ45|a!UdXG#oTx?*>G-E%$@PP-9kxK<zvkY6R
zIJwVQ!~pgK#<E_(%rSyOz%tJmO~IHgGx|@A*)jb$0mh!WiR^V?syS#mGFLr=F(>9h
zaxk2kZ+!v*7p8q4G`TX@wLrZa^PAmhxidLwu-Ak6x|H63p3Jz<A?U^2{VRw!)056a
zKFt4`AmPj0dIQ);n9oyw$d9Qa*Ug`Kk<O$6%r1IS2Qppy&>6(sIF42@^Q0CkLYRwQ
zgLo)YP2rzo%(+NR;y82mS+q_tzoPoGaAxOi`ocg2^EG-@BblG1Kt76Tr82N+W-!%D
z$1t1Yfp(HPq5+9zM#ci>6!W7+m|-0Ah8>nWp6Nv=f&^yxGKeQKg)LB##5_QGp3}^k
z{UFKAOged`Fc(|_N-Fct^FTSnjQRl@tZ7Ua+Gfu(UkZZ3=}ZTAkPPNibcHLE8Q2c_
zEaoeZLDM<r+kay$n>kI+OAb@{88qcGpW6WS=b4U2z;c1P))Us}G3Ae-mCx*%14{w3
znf%s5ruHK!y2w02HPn}wvxgy9WM%$ETUs%bvju{enE|gtZwYgICI(BHBmQWWF*pAK
zmU8Cz`4FsNepv~-E18@`bXGAxJP8Y{nUl`IzQX*I0%JAIORF)%TILzL30}wC>xAX1
zXO79Bp@F&TD8?F@tXc>(F|FeiS8rzi5d@wV<{Jf2*vfo_;-78Ia!Ti2W%9m;ifhd9
z3P`jwJJTTF!F=Zw)L&<c-$d&M({&s+buv3CHPXfWlIkA2nPX`X=wUKw*Xm{dSc$Pd
zX6lz9H<`OCG1kv~%1Y;i0p|H-P;rY{J_^A>rZN?vL(IM+2o5t}pz^>GW?CY~ZZqF>
zM(YmqKgtN*WiF}$=RM}~mtpTHvzt8oF=jo*>c^Q&D1Sb|y!I$GOfu~^z``kJ&nM73
z&1|8ngBd1g1!WFqnSVVFqvn{E{<RmETl2CYV9%=G2$LLGS~~1IvI-YKpA+k83XeIn
zhAC6v!rJvSI$c>OD6izkIzy#~?yT-Iuz0X$C!oQTRZ4|kUaS-rSiD&WDHP?y`srn8
z@MYOh3Fi@3(nrwX$C9qY{QOx@TdCMDfHjV?*oA?tx9Lb5#A4BXlVH|EJE1Uyb&0%%
zP}Tt50tsV1Da1UFvJTR|dW>ay8lcBnV^p|tf;CB}lW^AH4RA)V#_3Z@k*u^*phU4|
z=#(AJ8a)O@F|31sfShDqQCh(h%W9`D0-a)wm_g!Lx$i<go|VOd1n$w$&oPlzMKvW!
ztOxWko@RYt36jjZMIo>h)`lgpDV4Q_N@dTmo<0D%G}ez1=se4Mg+5i4&a%?&_6*k3
zt{BT?Jx-fW7Hjki@(9kc_8tOSHY@!hOgo1qcoVH$*0G}?=UIPKW!nYTdsJ<g$NH6y
z4*9IE=b)*8)kS%wLY9h-Xct+N^c%m#diOV|C}MS!n_bL$-4heM%t}gy`V!XYlRznD
zePsqp8EZ@HqKDpDSkAg~1iclkl|9f@$zn$Wt%|jRw&iNpCUTvwuzo%dmKxTVerVOQ
zn2Rx1$MV4?!G-m#ibEJ{U^)A1i`CZ5U~pVzt!uzkuCW$Sbx=EN-KWrZgZ1WVDClJE
z(L$_?_3B}ab+fDwAl<`?=z?4?YnTFWeJm?&L^oM4QvF{)>j1qG2UrCQ@z=S<it0pb
zkmc|d%p79vq4@VO%bg1MMp!>tS3~|bYY|-`yTkJR6g+oXlR@ab#}fVk&{6!CHmDzC
zdFNqa##uG=vzTD@)1{6{mhEyFGsSYG-0(E3yBlPNb%MS-Im>#EgR%Rp1;HQ>SPq_0
zILFGO4*<=x5P!z&iv7_(`Z?LL%PHz=&%Q#-<iIwPTkpu;|1hj@V!ts7G-vj;YD~?A
zofw8rSN4)00qVwnib??7*)8-;c(C928=#)-<@E4+u@iOB<jwy3FJStx^PYqTUv}SL
zAV=8JA0g+*emjmz+x^+Oi-8uvmfHh6kp1N@w1U`&-vvxCTYM9sA?!H;&_da92Vq(m
z`}bae9%Tn_f!<^6FAss`IQwZ@?i1{dnZOQb*HA`3f-R%Gb0quV?-+|>^L~T+Xm-F&
zXoz7ut)#0ZC)vp{0F7loO7E*v?Click7F0mEaKTK_Jbs_J*XTnk)8erIFr~v`~d9J
zY%xWiliBWPpdy9+_AXeT%H9|c6=&F*uh5ysJ~IW(v+S&IU~f8mi4WE=gPl)j)=YK_
zrQ5Ap?B7~3c#a)ji)J=^TQ3H4*cVGda@nulMdx|;2D+?yfxU@7x|7HDy#r18>{cp7
zxX70AAbyEGQwFn(*y(gtshIss4OlL-ZG2!%3HwuuN|&-%(<5ERepUx7%Go<B!C7Ht
zpLd0cmF&F(Sj#GQ0A(Ai*`*zjxWZmYIjS1=3v}D7mc2s;o9fta)Ix7Pd+sTa2DU#%
z3>w*`9<Z>9{ir8cn%U|iV7IV8rFyMa_P{OZZDX^j$n+}P=mmSPv14c}XlGl0Bk!bx
zJxT|z>uhN@SZ}a@!#}-S*vUS*3$yQH8!5-s&3=0Z5<P5l2S9t-FVpd<kNqR%@Ncq@
ze*n_Y{+9Bv1MJ&PF#8t!DN3>qvRBgqdWhZ50vTo-i@-9%X1SwvoBf-WZd~1A|9lDL
zF8jbI&~%T@nuRf=Y)utF$JqbO!NPI&c`BluU_bH-#wOV%)i7p?{V9o0v;U<fonh~$
zOv)^KT#6aqXTMAp+z;3*SE4n?R#9Ygp8fcT=(Od$LI-F&&R_pffYYAy_BU8=2hI{Y
zK|69R<b*nL0yly<b5@K(!iBSv906C(m$zWP8|RP1=yd0dP^q5>=T1Iao}7=r!I&3E
z6$6FdoWNRu`EY{irQpk1{VEJS!f|^IEk91r9<caxgtipm4B)s?Sy3RzgK}~~oDa@p
z5rR2uDV7q#dC3u$hH`X^p(%_L{W1iPa(?(3tz(?|_dt$wbaco*!FfZAB?;%;I)PRM
zCzW0Uk(_@huoJ^sN_mx&oRj3T$8ttbqIHVHI7R`^I8Odz*cQ*J7s9p#&Z8^9lgP1N
z#GH~i^8eTKaeC<&oXlzWhJ`7dlEYw0<t+LPrk&w@Rsw}-oPWsBvz$SySWoBp&`TwQ
z!yf`lCTC_ZI<q()6r?)G@wg6>%{fbH6>ARXKpW6<Ic-$kcb@Yk<y9_lerG{2k26g%
z@_bH{8Wt9CK5xO26mlLaz(g-{9{mCWmpFgSqgBND+zWFm=9E)p^D<{55$a1gTRwt{
zQqD`IXq9nZI|k@-&c4Ucs^GjsyH=%@(`p2*;`~JE?`qCa0wk_*UZTio4d-?GT2(D)
z^d83QI4weGs^_fYKt%&5=V_2e4k}^s;BodfLav!3pjToGr}qCDHqI6b@3wLFz6^4e
z<4>o8Yn)?OLE1S>*Fd0yW8LkK!Rws2DZG1wBc-%MC+7g&rt0E6L?`HO&g)dz*25V*
z3QfJ7kG4Z^AE$Z%<R*tl2Y`M~Y9z!5I1_JUYPUFR)L8C8j*{LrL!4&v&4xKHbVwfI
zaOnVjo0Cq}MRz!jJD&o~T~6MAFzO!X>BG=8%JF9cZH$wr2N~yVcm{eWI74)zoaB5+
z)e%!1>xXDfb0X;8`V42-3ue!9mf7R4b)S>w29^h$c7IXTa_iTL;IQNFfrq%zp8GOw
z7Y^Lf&tQZz*Ox+(E?l<<7<1+3`@l{&ZhJRC+_{+tu>>C6n|}h?liT$Q<h;1GbaeFQ
zs%IeJ!&Oqfg)g`MY1ns!`zxIX{kV#LjQMk2>DV5?&9)weoq^nil+Xy`E?WwiU~W47
zMnkv*Zcq`*eY6fRVcd7kFy<&%@&Obc;~M`3%W<w(9>@vqJEx!`oO_mH=@H!CS0E6{
z9jA*iQQVT95Qyg97(^?E`wkW0oaAQHo)yb|{T3ZyPjTljKq8K-CqFu#`yd|1ByerE
zf+vyNM6b;x?hF<EpXP?sDkpRMNiK!E2PH5IQ@JaOF_|;mIr2f%xc|_J`7D=X3uDr`
z-TmOq;Qm1Y$xQA)6m87nPSRWR95>-5Dj>+_K1RRF9PY}SV9n(or%2{`?$`u6FK{J&
zK+EIaNrzxQH;_^$1>F2;v<kTmTcP(Nw}rO1OWaG8bSvV1NhjuFuHq4ZUFOb{b5z1T
z{UcCHxl74MD&xLP7w^is8F+hH7glh`D1}hTwWALqS8)sJ=0r7j8|6H%aKCnk!WwQD
zoj_~3uTUvh9k=gSfYx(gpxj*pSF`{Ejoi0(0i}uiE`_R^xgl#X*21+=w7-?xK_})m
zuHZ|sT;<lN(7MK5Opz*UJ9oPl^X=dk(S6qI+*tDbZ*ZTWFLrct?FqY!8%|~K-CQ|c
z)$8HDM=R6Itu2LIKlh)V=p5jVx`5o`#*CtKkQ>zllp*d)Ix!4$Tj>Vq2)BpgUbne(
zkAdY5*K0c#=&qHU@im(FxckmRVw7uY0M8ir&~}(O&i#gJIVQMnbgOQXi%%=!(c(TA
z3iZ?6=htIwhP#O(Ftgmnl&`wa{SGeE!Ux>8FtE&V&rwino_pT~V79!eK@dCMpN+7|
zo>xK#2M3;Y>jv27$lI_4*iO95bC7W6{qO`jU3eSmF?8kqTLI$6`{8XUbmzTBFBK2o
zb~-V8^0ur8nip@n1p?l@*XhLU!yBZM9bew!ei(Cv_iGPK^W&YRNU=X}Z4<x(czyyH
z6Uf_TC4V)Dw~M0K!MyF{n1}H4XqyV<l@|asjCV5_rXA(I<pR@=@iHk4eVpg<Ij~Rg
zo=m`4IPdIRkc;5$r%+WSZy#l!qImW%Kt(j~mqd^l-oq-$o#f@xLlw(A{0yK^@yY_N
zP#?$J`Z)ySd3-uCC-4r|L46|c_s<}a#5?H(?9;p;dNz}J+ZxbH;r+P=dQ*9m6wf)s
zo20N?8gKgo=sn95PlKfMOcX82;H4jjrc7S*^H7w<%cutDIo^X0AeYTkHc|n34zHEm
z-dx_V4E!n2^KzF#@B+_;GOl^NMcW{e&pW&xV+FiJw9ggteq4&qi##b+L|@_s??Pu0
zPbYzC#k{>^0K3eykZV}N8@Peaa^4s1=&azqNSBN%dCvx*vx@hOls-{j%{yri`76AV
zE0|LaZwFPf)bb+8A*tgD10h(?tEanf4ZH=knKbf#r02JZw=w`Knt3i4Al|}r?8cm0
zc?R+#+jvcR7`w__77c-GyiqqSLObsddMY}2DchmpI`0jNj9YK;+Q{wg<hk)Nr!L+T
z_kq^UtJ@BV9^OfE_Ir7mZ(^*EH&02wo4f@y?S5VuRR;|4UMPjYE#5d4@C@>HJPm;%
z-UdpF4)aDSbUMPjx)x)%d7-pF-r>0y0_83*`eBfJR^CJmU`BZX<P?tac0UWWabDXm
zP%*(<wG0xIydyinGR2#I8feqJkGjAz!%HELdX~56K49+io?C%wKj1z82K3JH9&QGi
z=Sf~fr!D`aGX(7TU&KSeo_}B(7CP{U>0Y!W-}(t%_H*KU7lFr_UlRfe7yk5Wu)6Y<
z0nqEle|rmvJ3l)YogRGSlfd@mKkbZ`7e7*kF>n4W%hBn>-%fufUw##33y$!2Isns;
zA4+FPfBttAClBBspt}-*{GAa{AH@IBdJ*!${GIJ+hVa)9z?e|JCtbJ-<EN09a+JT<
z7mIL=|M`8ij`Lss00JlY&(WR`&VOkeNCZED%77yITPSQ7#ji<*`e^<WR5=jC-|#pV
z=p_HE7>vd8!**iq6u(UZ634$VPX2W~U(Ls05`S$p)Su?>r`%F9{|gGmr0_qZC}}Ex
z?*fdS;Xg$8BGUL{uVJER`TqAHp3dL-2u#c1fA0giOui4j&9eAY^nYB=@jGc|+5Gpe
z!<ZcYvG2f=%Wqd=O6U2T_E7=P1^yTXfb;n0$UVvD^S^~)0e^)z1Pl2?*MWVJUqYof
zm-r{>I!F<};VQ<8`By2PbeSJO>Gcx6dMOMo<<H%Kp=ErVL1-%Hzd)hs3Vt_*a4PxF
zQ)xsM|J5QWs^)iAQv&4*|HtnkSi|?9!$Q^a&F_QM@n3I4XFdPdr(sM3e<=f`k$=7v
zf=&D$`ix04-{)88ZQ)1JfvuHqGXRBcd{+t;T;(sOpZqm`)C(AE=Wl)woE`j#VUX+m
zxlciE@S`3Fn6;C?^&BL+_}iAj#BTn^gOKRqC(*ZDdilPaU~nJ5G9I(I$seMFKtDf=
ze2@XYErm{R@q^Dn(;#2j4$dLIuLs13`N9XVaD>0nh}LaB>l#?@@ZD|Dy33DE#Zunm
zAKeInQ7gZi_WUvaxzE8f&QF#Adx9Su08Nwp-L!{J@f&`J`f0wAZkEmP+x`aUEI*J!
znD_a0bo_e2|F8g)nB&i%hxj~y3#BJ)1-xq@c7omHpxO(n>Gr*Yz&Q*ojsi0stDOYa
zKg5`}vtSSH`7Q#R4?$c70@^O!1PkfR?k<R+`+yz-2YL~B3;g>q3m<{sB*uIN859mX
zB4EO{g?@rx$aV4;I8Zn&Kv3xlfj~hDT_p$-aK8geu)v#+SRsOhZ!p17L77#9$%F}3
z(TVG*VE1=GJ0>XTgo(!mpVC*PPY8OyMk`!U8v~mn1bX_-MGD5~=p7}f*o;=Rpd$-%
zF#_?s5I8BgMRDg?!H<hz%qc-f560pI51)lVyr5|_z!C&6)6qLoQ1$~oe@TM>ya01r
zuwewYB?}I-U~r0{hAPog1y4|^&>6wS0)VCoo~Os~tUyEY&2)j;7uXqsEZVg)1=Alv
zeU@P41z?^N1Y8G8w!ogMYjOm>Hvye1SV5iV1v^5a;ez0k1p4$%p5WQd(3CH5y$ksQ
z!D{-=6$*6p3CD|qgc~521b3-it4QETu3NDnp6cN)3rg~^&Lx8PegbHz;A`5D%LFGK
zVPU!8PiF{J2uk;(RVmP@U}%*f@p*Js3pzGH{EFbk4toF92o6vVtyZx81mx=kesoKz
zUeHTL1`UGWo&t8GVAs14Y!ZA$+g7t6ZyQ)z1c8rYtX1&zAm-a9_~i|-Toshs0_>Wg
zfocre1zyo$=@3{bpMPE8{0^plLvVc>;+=x`G%(HDC6M^Qwr+uY2jqJMo7Y1{uV7gU
zc=`lp3cK7Cq<COu`UT^pa6s_+60qD7#45ltD43yB_K;vXy~KwFYp%lVJA%Jb(0Nzz
z@FQs56MRn#J1Y2o9$;gF9TaaF7X(E^d}5>E2vwp@3f6GJGbNbD*QXXv3;IGpW&}sb
zx1ANNqw?MRf=9`Ld?0B49iVdpJ-v+Q1;)3)Vk_+S?`&IcEo*?7qi`Fg0GxymlRxAv
zY@qrZ7vYEW*t!aHDX8ow?7xmNcVUVaCV2>jY!FXj6{Tjpgtc_X)mvyszMYRSmX^m?
z_#K7VjtEt)Abvtes@V1yTGj$AK=_9h0)fJOEA1>n!k}AN=3rqsWnV*tFBmZxDm)jC
z`GpBLjzjRMa1}kv$An904#$N8KFA4Szz1Ln7jkIJjSvc7M=Meo`6kAqgiM-JwD2<d
z6*0mga-dEM9q7d#E4)>WzuYO|S401ICWT%!r+DFZDlte9_EHsIqA;A!I7z}t`l{4v
z;SxR8B3ZbYegP@Mr>XKRRhaDrfiuD`s?A9g{?!6<R#^TESki@CpN16~!gzWOWD3`W
zLp)2!p&0Wy;hURbMYix=13gSR!d}WN<O(bQf~NDrLzIfTAj}YeCr>y;;h}tC9-Uze
zgnJq=Rw!hA4NVt?#dO#2lJMR)m}rsk-w0qA3pXAI%Vpt#*D+Qi9N!93D*TdaD9VJw
zS%8%b=QjYlLily-LwJ}fg|mrhRteL7gNkb51q)!V2>Bm?)Cr&X2X@yBHA|qdL73--
zIW-EWV*uJDTuf)!X5rXR7;6y<gy3uymhwT`gkR9n?5ePjDx$6luarY?yD+gIiaLbK
za)@6S9;MKp^@ebk%Bnks_q4$764uf>cMCsRi@_eDo|3=4LT@Tf=o8jvLhz>WElP{`
z3m>7F`hbv6ZqY4acNo@rP*`S*u_58N<k=1jKj{S6h){S8(6@yf9U*W>sQDUJ+!el6
z43>LVq5TdFjtURbE!i=lGrhjXg)fl#6T&-NfHo<#{|4AoLLrsbP7CFSG2a>CukQeR
zR#-`4()+?v9RwZ-KcQsMoUoDN2=hYLPXMzOEu$cnov0-Z#9p+ODyJPp9h7%;6j_ha
zJu@d!-WRaKSycZFBwR${S`501W)8qaH<2P0Xzrp~x;5q@T9J=2Pth`R;k`t^(@)-8
zbnpz+`-uLf<F&6S!Ug1r=(BGD<|mR?K)_%0c>!7hq6Pn85duXou7WW^BAu1;WWl19
zv}K2gzIzRWp`s)7aiB2KMe>f0iV8l$*fG)OkI*_UvZLbp6C&0gaE6PD=zJU@TGx+O
zq-fv_z@kJSQm8pvRBeXB7?JiGSWb%mrYl3SqSfSypAs?i&>1K4&{?sF@gl`zAPJ)K
zIAAA=ggwxdBzk*0&`yh{=!s1hIlhi{N)dTdj5}4dl1`>)MB@}@N*Bq`Lp(#2NVgF)
zMGCr%pC!`KmU~V#M-kj?(dYEU<%qUYh%Hw%6@anxq9@nTZNv*A%?O%#qIFc!kuUl+
z6Y2{@L(z~Z6je|J_o7I629voYO6GwSi8j-bzgWbgVw20FKss5Li1yQ`B1%OUnP`=X
zzOctwxhR}cCl#U{{{gyE^ej0}RU*k}7^@cbp&$g#q-d)Y%^J}W25hSpEugb#ov4Xw
zit0rZ3V=3<qA5_*DAK+N^-ZE``pGwo8h^*^TSWcWG1e+l(Yvrs^e5f>xGHL+r|Fug
zIvJ#0WF+UgLsa)B=6PN84qZsSA=<GWEo-N!)*YI<M3>zF+ATWH!Fu(GR+fYGiliGM
z*e6;`=gga;4Zj1sU-S>9M+QW7_rP*XbcDi8gQAEf7#k9mP>6e2^x7K$8xdI_fZP_n
zMNi`$Q5rqycSY|`0`s0Iiy||lR#B)Uu*XC*N(hdN%p@@(N;reTNf9p*nx;g-*}$F_
zZKNWz8PUKAkXg|IDxbSAdSn&UKM?s-uxw7$_7dhhFA`q?immveKw#R5w>1IGUc8H(
zZU=EM19Fby$0^q9B)0yQ1L`b(e;Fp@BEDA&;woNG$$d9*z$`%B#X$~ed590%K+sd1
zybub##2p)e<}J3;$-_rHOR0We@eAQ#IU-J=qo|*FBfVPv#UtOsrXX>IBU-^?)<$rK
zi1Vo6CR99ZZG?(2@ruWRc2xXzD&&uedE|^97yGY--V@@7Wtc^{IL8wtLd?Gng^}U}
zN*+Xsvu^?|T3m4ytr&4}C0I_12UY+qR;>9LGdm?#P>e24>}dz+c(E}YED7S%LqJIs
zf4`G%LnVp5zlJrZ#S*HcNftjrMV=|*DDtCH#h1uKJtO{>HqSJ%<N|CuD<0kixpc8&
z8LZC`Kj8?_O!2e3Adn?~lFpLn#Ot3xD_i`V4A42^$XTG|iq||0==0+36ehYLe((Rm
z%slav)SEAU<u?cxh!+k4tx)`c{-x4I@$gEFT@st0gK0%##u%nnEKVK*_GPhP4_YPS
zp<lpKDvnBlrZVwT3ip(YuYC!H72+rgeN~FpR8?Ii{+qV`YVrI27`q}4Klso?KQF8i
zCzCr?D;}UNu})mK4?OkapVq>}2Jx<Au&Gfz_9Vud#9kB%ZWiyN*M5uGhx~+A@xgTH
zZ4+B4MSN8(qY}t#;*aTGce~h$Hop$>0*cUI7q9dGpl7*NdL1C$;`gYozDN8cJ?_2Y
zRbK+KPy9{~#%_ua4WYANyyqaufOsDrux^R>*}{}Tan2544T<Z&g7RUpPYK3G#GP-$
zzT4sj&%yRP;+J#5a#y^FeunqN`yGHXDpt~Zj)_aGKS9&D_$dRLQ{q+RS4@l7wt&ot
z7YfihE8dp`)9#C#Xqg^}=bd2FoVbl5b@SpJ`gcUOlE<$>ubm_-3Uc<6%OOzVAo-DY
zS4YW*nP@plzB&aKXUUg6_<OiW_*1aSRkHK{;R82`FFB^}l1WO)c}QYpfbo=+(#y<C
z;t&A|Z^_4BfW=4hLk@_q<b^(1aYV8t7}onqR$j(L{U!gd##n%)iC&(8lHEMCf+R6?
z;trN9rf^n>B%%akp^{(769|)>+)C;3qZ01#n8h(kGZh;im%O<b<b-5DRp^9EhR899
zkSOSTK9Q0;_z?2KC`rd+w4x;|Ujk^1WWWcllag(;OT|i-Qf%OqWc)*j$4MebV12yg
zGy0P!NdBurD^YTh_N63=p@{0APfH>x?2#;KCnr5cA~_4tREdc8%rla2p2f1INuEmq
z=vm2oBFLvpZgs-m49P?_Ix{7I{R{CdiGm67bCRp{?#`BcK>3gy$*;d*ELXDkW5}JC
zcur#Mf+WHMk|&W&L%^CZVbPWE0!d946c$RN-U0SSNl7yn|B{6BC}4^tX`3*aV#yK;
zd|#Hlvj%!gB-;xCS}J*i&O~LB1&2V&B@5C3S|JfT!0bxNYvh(xNxsbmX0@b~%66_u
zLMU-rBRQ4}uv)8R%U3|FlV~<VuwIf#Vc`Zz2031hl3nfKX_73bn-0yAzsWsslXTJR
z`l@6lRXSXgJW_~OyX4AkjCDvh24KF|C2gH(-H_DMTskF^9Z=XM8Q1{}yCv_%!-^is
zy63>sE3tk+n_Zt|D?NBOC9AH$n10FObbt;>extqmmPB*{5`z-EY^=qQ<U9v3!;;4~
z!?Y1e9xdK&N&jBxy(3Aas~~qJTc3ycJ;^*3`;JOJpe=JuvN;%I<C0FgVlW|z?uAX0
z5~Gz4?o*Q1_pn~m5+1qtGZN=R0G*XwrQqj%Npcz#K9DHrQr?^-i{5_olF10Du$A7U
zK%bqoZ6U_&rOT56<{%xWRGg!<NCFfmX$ZYFouw}KKwPByP7qhAYXJn@q+h2}XwhBj
zPLU)JX*5MkJ*B}PqU9xRq@0Pjw2=!IAF1;~DD;)KPeH{IsXw_je$w}nFbjX_fDj}=
zI!f{OK<W4YVJt}cJ6*yEmVQWgB0{9ETm@LDbmSUX!lX5HIpC;tYY2t!j!FF=g~H>~
zP`aUULMnR;3d5xfYQYmB9hpLBq_k=rtte^RDAY$wT`BPyBV8W{y(gtbZ(uU9(%fLM
zoRWS-r7v;P`EMZ?FU`<nEJ2zlhE0i5CFLWNqzh<sJ}v#ZlkT4<OMBL#nIiqR6+EfZ
z9S$(&jPzk!XiAf|kZEV7<FxIhOQrw8v<&IjN_1vQJKl#CSyB_#pr4b@z6ed(()cE{
z&Pxq@q3MG3IR;Sjq=JuNQ@#{m5yX=wjj9Jqq4cpD5bH&0`CjO~BptAW!9~)M)6i5b
z{pS$SE=wQJfoUbueM*p0=`Wvxlu57Bs+UX0rI4?Xep(06N@)^Z)v1#1r{G7mRR0AO
zUXlLL2rFu&d@pFIm9mmyZ=JN5s&wn6NCDtUvr6~hheV^aqXP<?r0>wi+ARHP69ikN
zU%NoCRm!1a-!`d%5_DIkrLGveCS7s^FzwRANf_&p9uYwNx^&tPEH|W`<S2GZZ&M<^
zOIks@Pq%dCEJ%;kX#yI0rM7gO=#yG)>C}2tI!N^){n9Y<oCc&u+O}><9d(%6pmYTl
z77j^Ev!G&FdU-!UN2Kgn=)EodrykS3BlV`Z+g<4@a(?eg2mOFODt(N0mNDtQP_)LS
z42m^PNb6^SGAUg}FNrCs+WI^Or=@PeXwFETG5|U&jZH%5ed#xgf%ZVUX%5(P(mo1)
z&Pxx^VurS|N(z43$r7rd-d^VVC|VA(^moy6l>PV&EOe5cP5^P1G5_yN%2Fu+<tlrN
zioo4uCoV&SyG$@k9+!vgsqZ1^DP!z{3NKmKFo?G-gx*R%GTRqGd}Zrt4?H6K?>CJ3
z$)0UR%U{;c226mgnB2}l*^N-FT97Pa2~-5jx+snuBD*{adqZWbY4Zw`9oYxDqp}LR
zWpY9mnDzvozi?Sb3<M)&USbSJ$|{#aVU+C5ef&kDWj-PZ#>igSfkikevwaea7%STt
z43<-}JvmSjCrkMVWAU;nD>Nm@R+ONXC^IdCp-Hk;55vOKGCp~6$+FXQT1}DtIt-Ll
z**FT=tP9V`9$62VG?|&=EoWsnDDaRjE1>jBhU`>3Br;_tdJAXCKCcD#Iaz%POv{!H
z@*$8T8<GG!SN7N)C_FC<qVvlIS${Xo&XX;mix&B^;#V=j0@;t0yC{@BNr&u<vS=r$
zwO*1j9zecGw&V;1i)Gs5;JGZj{RPlUWSM`1r&Q+u|A2{XntsUTvL13DD`ehO$5|<R
zPzr%6SyK^6wd_q9<gUoh)d90cW_t+&wX$-`<J8GstjAcrY_$uFX^<U0i3v7ZW&0@Q
z(<J-mAq+Ol>W4sDWN*EM8Mew^d<>v%vLwVg7haX^twZaYY#E)h+hv!?1@Dl(5d@g)
zvSoD2z9Cyg@8nLInets-vP}9}b;}M=?5RiA_6hX%%9^M~r%!hI1mteYtbuf}?U()B
z4T%9+Atgd@$yRNG#GuTBmU~F{+_S(Qmf2N<WklBd0j73aCM(Ax+>tH+9i4Y&kq1HU
z$)0=|0;95{7hwIE%xs2=aoJ)O$b@VU)df$={-A2dDOn=@)~03C)&ca+$nrjgQL{20
zoyP9V{%8StAj^(Ir>*=4ic#3f|9l6g*~{1XLcN3hI#mie${(RBV<&k!9X_4qKTzqs
zi(G#b0<Q8Q2e7!wCu||-E-&qb6&~_sbSu?UuBIcbmt1n3TncabYRX;s$a~1W@|Aaf
z0>LBlh7(}*le^Gf<S*YwA;tjt8mdPNl-J|{El6JfHeiC~yY_-JM1J!LjD^b0KVfQN
z^0(JQ;Hdl&3XL3-bI$<fxICI}7@d$yseUJ1{^ZN_AGRap+vt=XDfgx-gDAPP5>`aZ
zQ)#(l<cY7KbyDuM4(k*v5Az4;DLI4kM{)AjWGIZ6zj6*UOpt&0Gi*wfub}(bN%Dd&
zXgV!VqFpOlzDxrPQ{<o1il)lH`2=!j<eiO=;rUCGmr@S!tXv-gk}j{}!io%e0v+o!
z<t}kx&62M-K<_#Ea}?gnmS6u5Fgfy|V-U!dKThGT^YTmIL;VGLx(zz><kR0{4fEwq
zXMs{6AEsb<p*)O!NEhXwUW33Td1ew?)*|_HbjmK4`};xgvivyhDJAm1=#*V5@2&z&
znS3@Dt#bJ@bjq%ff6ND3rTnM}Gpv%w?M7#{JeOifSLDrf`=UmEBo-=a<+C`ZEUc41
zsRm2E{Flv;Ymh(S0<2N~7x{5bR(alUSm$Q>*2}P_Meg)CBwFQ9HbA0HE-eAtRe690
zo!8{0^cHTHKXVuMcF4=lVeGp6iQCZIC0|Ep*lu|fm4)`mhv{J2D}R@d<?55ac?6s{
z<;S*zrC%Oo3xNT7%65=ja_cLVFk?`jQ3i=2`APDdhvm7A7#xw~A3owylk;B$%N_Yi
z1+eeRzbD7@p8VNvSTQOurjziPe47zuT)sFC3Mb^@Ng$K*y^b(@O8yH4vZm!n=`cAX
z|GNVyv+_H!V7V_3w$f*m9>{-K4HM_&FVkhFdHJ<@v}_galo+&AjJg2ZUa_tT5)O*E
z*U@rR#B;&or0_9Az*%vJ4^S5clZ%$CqMVK=Zi-K7*K${cJr3(V6g7Te@l<T#V9ZPL
zCOIA6it;8aczhJCt3Z4eYoEa25k)7ZIs6po{jdoB3Z@G{0~9aifdncxD>0`a#m)Z!
z8mu@#+iZy9{U0G7s@Ou?U6>-b8D<|<{7h%VV~SvMSdS~>YoYLjqVqFghAVdZqccLW
zNlov+NW~DvzM>TC$QOuKMAFK}C`Ku|eNwTX9`RVk_Gs92N@1Zou{g!=baaYWJVU4M
z1jWCTz)n<5K7s{GQVfz?cUocN2ldH{F^XrUC~mxsR;nWO3d}yEC_V%YX$rv>`u@sU
zh0zNV>59YqutFJ%@pItGR2(`D&@4q89R<!QLh1R<R>&uyFh@~42GCr^dOAj)SLF7g
zbwRO=zDby;DE9=(SG?vAg$0VY>GnpU;^HenDN^hR#k7kR;y<9_vf}w-5NnBIQ#2-1
zs!&o!rcCipB|ys+Gj9N<Lh<Ysj8!U*iC|ilqKt}as}&E^RjezDQWfND6n>pBtyXd9
zDpb@dY)*mHD_(pCoDGUPN+vfd8s`Dsq;UEhq*-Cz3YHdyWgaZ8R>h@qptULNDUx+n
zk@N>lyr!62jumQG<jOGCq4<r`b=MW?hcR|T(MrGIPDT24V0S4-nlaIC#VR`9^eA#a
z0O?g6W<$JB5&aX$O+^klmHmqED4jH*5VV5aQY=mZ%Amsf%NVeS6cb;fcUTcZQRWdv
z&I;IeTj6yYXm=E^k*j)F@g}{R?<uP2BEzWSH+sd6Dg47=;kaUJ9ndBezvf^PlZtEP
z5KSrmB@cO8;YYjWjN*OrduJ6#JRopiA+bQw1BJ779YE(4wXdK#uc)M=O<U#DW?<VX
zN88b|SFUlzn1ixlCnoBs+(7RWCuKg>ayctMe;&j|S#<z^G*{)|cNlY1Zh8-T-Ic#l
zEv1L@4?1;wD!nM*?4^8i1HinMeH38wQ8pIR{c~UCSRI;2l&?|<!B4s5D@?{;d8P-T
z0m`H%s0dV^r?+8{@*<_#gO%w=U}1<dxD9`iP-Rs<K*N;cPa$wrSw_zPF(r2jEXS1y
zLgK+wmb!t2E1&6rq6p<yx~3JWeD^$^|Du$$lp~8)GJG)@tCai+m{ZDXIppJ%XDN#i
zujIEuZ-TOp(n^WS)%IXXQocp5%xR@JrK6ISaVH><qHNv=fmCHRZG~r)AJP#%O<8&g
zGdrscrpo$s<x<M4WGL_BO=n%0sqFUvOqTKxg)Yu1zeF5xVYV{f8K61JclKi}R~bb$
zcjuMOl*+uI?57t&o-&wxy?o_1ijfp3D;|UTLgnUtAQzSOW01R~%%KvgBIPs1u%cM`
zH5G7QR{lemUrLno%^0(mDnF%a+A`%{3DC-w<8~0NP~NA%Xr*#n1thAJKb4_Xt-M99
z;uWRH4gxjGwX~MC%7vu2P8m!tTfK598m$K9M@ispRMy{tX-&$*k72A?c{CH&w<z(C
zD)Hbc|9uXM+N{dyUom)9S-BH~*OVX8v(m0?l>(+iIZG#*>q^~iEa?rU_iadYDxD~l
z)}@T2Z?kkOqXNOwqjcC0g}uttbXw?BHm!vCP31-w4DDAsevXL_DA&^WHEt<gZ$ZPL
z^7vB#8&X<J=#(?8j22-sBg&+$Fy^-M_e&VOqjXve6?c_wdqM6gUr>OIDsMdm`7vcq
zFUYv^&JvIb<&X&qCzb2ygJ)C9HDAMuX=P?BP-c{cAuw%Lxt}WJ?<?7qCV!yZej1AA
zl*g>EfX*wYDBEJID&CBiol5#BB<xlGp1^icRWLvtRnM*laZ>F}#+a+Bp$nSaR4dug
z<gSVoqtiq6`S&26s?x=nsF$kMf|j@HTPkz$QEjFlx35a2fQBQg!fdeksmdcL@$Ih)
zFT`Mg>W#-?MW8B#Dm#Nz)qlX?U{%QH7z<HdIs}POm4^*F!&L4U0D4r#*#~k=H9U;j
zA6GpU1F#dS!%yLd6t0TvhWZHA20Bbes@{13%qZ1gpFtp66}JMd7}f80==<C!Rc#ML
zZ>(yY4%nwue|Lbysm3T#7_YM9KyQL-KOK@1RokhMCrRaZ6gHh!-K1YxvTAKES}Cfr
z7PL}Tw)Ox!qdG+!a+=EHC|2#P>Mm6Tq^rWh@fXQZDb4{UQ<aah4eP=z)!oyOKc}js
zE4JAxA2wP!s`u!|V6I9-j@)@wBsl>WRIzlt$x|ulrI@dJss(5Tsz+wPQmFc!z6^X(
zRgnhqOR7awP*bG(o5B*ss&zul<+AEHoiIyOA5w(1R5e2NR@O4rGr_<vSDl;&sZe=*
ziiuXL%HP6Zm1<rNiE7nM7UZv}oX4Q4MioY}tXkEEIIL5hYG4gi)T=_M?yy1i?>&e&
zsy5S0u}O7yB{VgwcvX;VQT^u%fmYQMk3vzK%8rfBt5($zC2Oy#o~2i8yQ=>qv^rFU
zNg&r%@w-88sM6&S>{R)YOVFhX{0xiGty+|g&K}igU!m2j%8G*eK2_i<7;{rKPd}tv
zDzC4>GN_6=4wfO+Ymv}9th!5om=P8J(+Qq5m9?)6f_GG7dSKsG?WD}&J=MQ-wj5Oz
z*+YIzB{~9$ag}iuS`#Xts}P)2jV;9jO{wx1V`ZjQK`&w2Gpc6ti)K}ymZI~%sv!W-
z4^-QP5SUZtIbtsJDl63#+p4!wT)<Avu!<pQuTH1u*Fi0!`T|Eam(J2o>KFclgtPiI
z`9&`3^^|yURe!S$pl)hm4v4$DOM)>E_0x8+-cvnCSw}DRyE7Q`R!7~zBz)9+De>&9
zex431N7RO&A>gML?SK{j>cNfl{f7YcG^LsY)v0li4^mG(3He|(hjNJ_>hli)CRBZl
z>MX<5SLi;(QFZnR<d3Nf$yGeAZfZvBgu3N*w8GV~j{qe??M%B?q<T0M;!$er95h6$
z51au?jQSNjtmsMgwdHi%GgjUDf9F#DPd()0)Z5p9HC}B)7kd)a#$?DRs=a9oPEyBH
zUBYSgIK_RE)vL)xO;H!oMWj^q>b)2{qwehjcAEO^5Y(Sl7yO3#rmOqO><qP859myF
z);AEyQai4v_un~nEtTYCtF?<Ek)sZx<YTUSGZzx))zQOPy$fnB#h~-lE#%<mtIuoz
zOo93{@)HWxFHAu1MRkrFY`UcW#SH8swV)qh#p)hEtl?#~kWNP>>O_hTma4zG3Gp)Z
zXNS?UR;m}>K(k7Hl?v0U)qeDW#w+UWR3KKP-s1%owdyMpu+*t*=&ne;dQlKq8q`x1
ziEC7UUj|K0>aoYc(yZo?_uQg>SOSHu>a=N~w5fR~(Ro!}MG^FC>Z4P@Y*%N$kC}B?
z)i3{m-s|enr$BC~2O1#QsrK5A$#ki^{sw5bI)e^UJ?eY(8273l{{edY)Mu&U<EFan
zU10aCUA~3ffclp?$lX%c-3A#{7kvxyA$1T{iVUmQ=%8>!J(mx#+v*1&Li~=}DyGoG
zUG;AiEx4za&O^nhdN*xbW9mS<{W-1<rJvV?de=)3oK#zPgJnvsq@uNHwJQbNXVf1P
z%dEQ34=nf9y;P|DKs~Mo^qg9=9m_SZo}rDxR>Q4B%T8l{65{rnd@K3u4w{`5;dRtV
z>9ypfF_Y8dtQpG%anWr17k0a9zB>nOH%$V)7Th(zQ2N9}6LSD9PtBVDAnv8n(>vK)
zQ?&rZNApz`#C<h4yrAibMtB42{WK@&py{u<M{^0#=%XnA5U42(1x%2pz7XnzHR<F|
zhG-u80wh$UPs3Q4#!PikM>Uy^kUyqL+=8*=n#WGViW8bX15|`-+GsC{(0tpER-|U%
z0;q`6q|>Gut=T1lq8QEI-$71l{&a?Ev6`P0^!<lZnnUDa$7!M|`V_Bum|{B#n%6=h
zpQ!o!I$CEngRem%UBht0L^CuCZa`DEhCKoGIhq&gx1Ou%{1q(u8Z8Am3N%J4$|}@c
zpcj0F=Dir`t<uzd1(s^fdlUw}qVd6x8|90d3EI+XHNRd3cAds<4<za}#dLGMK{G}N
zl17b{B5KW={ae7<qH&`u)vcPh=%v`E`E?YaS2deQp!b^Q-zIQ&X!Zo5^SVYs<+L|6
z<q=qtPR(gL`gCc+DHhzL$*0$@wO5l$LCQYOZFivE)F{dG>({Jzfc$`FoL29arq~G*
zLz?U4MGtFc{vQa`d>w|d+nUe0=)9vDrOfJGO;{?#?`guwmmbwDrXSLnCMFwW<C@Q-
z(VEb_K`(+yP3}q<I%U=TCxKDZnl|#3XEdwUqjg`?r~>u_&Eu3{ozq0z0_(iSaTqYR
z+Dr*x?6m(;Ai_bLbQxwlYQLp3t&=w8N9c9dZru;!qBZve(@lGTDjeOlW(pa4XeIPX
z3{S1P62wbut)~N+w|4Yb*zKd8qM*(Z?WS31^3%Rr08Rc{$IpQspnZn2_kmiEE|4It
z>OI&Ls?|_wa+vlQ9XgI`9jJ=<nD)W97(1>_p|Zjg+SB9`L~2{lV`fp>W;0l#wK<eF
ziPavmE`b@RwExlF*EnsXFG!+xTPYMKY16)k`qNq~1));4SLue%8SOiCtV+`sQP3<y
zt62+@spV2FbCz~F3#}aOgDPO>YP;z9Ij`-r1z5f|;~exBXeZu;^@ZAF_knUzyDpZV
zzf0N<@@R^*Qu>%oi8hKV086#C>1dT{_x?ZjrtP8}L4|f7)s9wbZ#)HKu4o@8x4A~U
zkK&NE+Ku5*Sf_nK3ib8c&!~Q*L0dy%+h%P<2gF;n%jvh;s(mFB8m?)-VAJ#0uHDcD
zYdW+~r2@NC`w0iebZNIxw4htNl2Y|O+M{_;(W~A41t!|3t)Q3ch;}{!owv0Sd0@Gt
zt)!6FU2Q@Z^xo5+dj?~p+DjB?9@G9pUg5a5B^a#<ZRi%DOlt2$)AKi_)w~A1)7p+T
z;F-~0CO2tTdx!_L``QwUT0hX1Erg0Wt#&iWy!K6dblU0~_F-l1bU)EW0ef8oxf>3;
zBC1Gr)O}<J7AIX+Gv?x~Q&5J|MdzD}DY@$Qk;CeyTfPfpR(IVqiI}~I?g$;QJ$3!v
zQ17Mt$rsq(IvuI-(S5>!grDxKILQ0!Dt-V<fNmXSz5{hjJwbwWf>w+L>)O&W7NUEW
z;#{G+ANpWZm`+1p;c?x_MHqTQm-z}vxb6e;pdzfgo@p#br0(`|z(na1(_uxl&gB%)
zVsspO8K2bcdL5v#Ivth0oYJk@0{J*y#!_I%>u%9QnV@?s7AT22M|zo_*2Pi@YqIXu
z;~*)z-?Jf*s*^MT`i#yt4J>K8Qi`Hx=&a3Dkd&!=fe!Xrx<e-cb557K9GbFqIdtgH
z(FIYaBv+??6&9Y?C6VKKLAUD^mLyMSOTUYJotz1j0^NQ-ma9;Ado@&C)SaSd`jYNs
z1W2)NFQuSLbqWf2mgzjGNU&VzV5KkKR_OkUf<&cmIv1@fU4Akos&xs~z`mmUVhhG<
zblvMfYIQ4GK<acWsSu=I_YobU8+3IBkVf4DcaSFC#BQuwt8PaIjA_%QQsK*0oj1iO
zujzie0}buEp&r<KL$`F8{LfBZF1=~HbX&-y>DC2BLcT|reHZF`bvvE~>C<hen`$?8
zI}cz<`*qjoAT^+Sl_Ipabh#tw9MpZc04j!bF>OE@*0s|9I-;w55uJB+MN$|urhEVY
zuDtF=3P4Wil8fm2+NAD81tg|)rT<}trgeVnplL?;{WlPt)vZxu?7r@`NOV5XCG3Ev
zIbC=aI_GsM<d)g%L%#!Y&}SZjLPz~CUt@us^iO6&g|pu7XH3*Z|0$gfUG@ABV7lo$
z!!SX2{a4t$tP4H#3$+0C)K|X?2`~M+OOW@~fA9%Z9MShjLC{aXXeWrjzUw!T0DS{p
z$qUryP;ewfFI@_~q54$1=M$#S*#VTJ`jvAa$Mi9-=sd2!ORE;4PoU64r2d7!U`3RE
za~(8TqxDIJP#B|U(;}SI*ZBi9R?num`YHYR3y_G@Z`}Zic>R1N&=T~80hn*1{>`P3
zJF6d}oJhLfiNehp`fifT)bH`ZSeCxj0bu9!FH*5awmz^Jayk0kVzA`uUzNe^^H%-9
z$DkMV@6z3iJpJ7^SembI@I|XY-$j=$3iTuOOSq_COUdF(dNti)DAIrB4Hd=uDmQdq
z*8f3Ue~JDo#Xn2+FK>dTGW}QCFs)pFmUj0Fefj%9sniSU233{baR_qNdaLnUOzn!k
z{AYmH=;z37sMU{N0IAcTqm8j%f4U2T4f@}YWA=^u^>lH+NiU-?ceDP24A?DtvkeSw
z)gQe8^=*0$J@8lc%PEe3P0xECq+S2rH<0Vl|47^9b$#d@)Zfr&Tglz%)E{((rY`-T
zRIJslU-mv)J^C^FmG<i6DTmaje=8LVZ|Z-h>xKRL6e<K6(0^Zn)-AnvH{=HOodF<2
z`qdOp9M->1A=VK+Q-RiP{n&MI-qDYQfaR|Kmye+Kp8o4L%0G<i`zg*mrtg<PVqCv;
z2Avc7F$%Ly>K*8g^pyU`bdYKNjs|ef=v7p&{Xj1wcYjX5n=bFo>*wg8YHx_4eagX*
zOf_we2J2lAC&TStus9nkX!CP1MC=2YtHF*-75{FA3yU#Pcf-q@!RldfVS>lg(DXhe
zybReNLWQ>>ioSv3V^~YMZePRa<f0xiRP2U;pW&BwEU>>pO?y#*LGUH!8*JcH8a~9p
zaEDEyhJ@!K5N0S&1?N%2{a9!?X1Igf7Wn?3VQLY2PZ+-537&An&vb@}Ff>x|E7IV%
z253=+FMq;VwBaUY$6^foD4TK8@VyRWv4)??;XP$|Lk-Xb!_-l5CK}$SeL2Z6K);03
zh68V463K>L6JSX(%&ovAQVr%M;Iy7GL{Mp6n&GR%;5ln>rxQiG;a)A|GYk`-qm^kW
zrJFKYh7Aj`2<Hr+PQtWoLkwL_$T2Yc(3xw9pdkHu!%ZqkykKZr44d){Z+r-Q^9@e)
zGA%H?OO9Bf!M7CTqG3@eOuJ+?=&K-DWO$Cgx=?I*>M`_QHrTxdg(Zes3d)okYQ6$Y
znL!!?^UDn>+aX_J*zFJXm4@e2fL&!Mj6ti~@F>-eUonWOy0^w)c1Nq$FiLWDhEv%9
zt2Z>=g1!dB6VE}Q(O`9_<6x6v`cdd@HdHb|S_}e;4YeBB{(xySocj|BuNul)A$ZMD
zxd3SGhR-Qc(qSmeLg#hEk6l2!VHhO0uG8=aMH#vbhVQWm-G=X0W4U?^Q{RB4*U-Ba
zf3$u>1wH-)hP~DpsJLbD`W?+d!<J=e4H-~1ga^prb`J6*hA+sMzirsC5rTINMU+s!
zYuG{#)jh)=SJ*ph2owW*%rJ2nDB}h`Mbah=J41jnX((|-Ysw&RhE3Ckw@YFDjA4>C
zp;^OMope09Z+K`P%?F0Hjo_IxRICH`ydi>ai`W`HsTjx3IO2*~*c<C&(dl4pcoPa8
zjh|5ohLh308D={h8EHUqG4}oqy{^V=sxfvm9;9%HyYa$tpm-SH`xwO2sL^9eUPil@
zDF5zl{B{N8eT<4dFvi!I{R?1@809N589$@%7+C#{v1id4V6^`dtw7@w6z2*u{`DB-
zf{nhLpd!RLL8gTo_YI;IW_)}#)E_lojzQ-!<NId-ecZUhAL>sSGcJLI8#}(B`m+e*
z;Q|;OX{`AfB+9sH59Fhbw<#VGYfK=Q@078Zo{Bi*W2a$7ywUM}v=WSwLa-znZ76}3
zWZbz9oTrU<-a#wb_$yU?rx*+AW@@U@N?$fSV;rFUJk8i$hR(A_H_B&O(~bF`U}ZCm
zB`;%1GmV^2F_>la6=L@1j7z?wN6q*+B@l9q`LwdR#&R*NIBz_V0EHKfx(dkU8S@T9
zZ@zI)KBiq@EHQ%=8cY4bdC{n&Z2BeRq7*<E8J)(#S#0DMp!2fT_#Z`>N{q(ifGIWB
zeh7tS#?@4PP;UI<Q><Qv@&2RGRB7C_6{O1e8Exp*#tmEuTru9I$VH9udkau%jrYsZ
zsx#Vdg5G-Lmz0=oFy0lRv(fnX5|Aci1O+LYjqYg>Xfaw#>7r_@@eeBCY%^Y<ddjQD
zS^Di<Gn%Ndx83;ITC7Efaalgdb>pAOSc@CRbHN~;#;3MoGCjr}<cReefA)roKI7MY
z(0kKp-;Y+mv1SE02aFub$lfy6QoLu-C~O58GMcUTuqMMsclsNQ7@wk}@onRP8sv^~
z7o9fl8vE&Rch4Ag0-8pRDNPU<Gyb_4D#ne6s915rc${{KN#j*pkSSx$yHGf7{A4G{
zjB#`wP-cy5-O##kysHPx1LNwafHG&yvb6$c-l&Mi)ND<UN?@>^>C;<KZ*TgMDn1=d
zJ3fJ+qiKec%}%Dj{syPBX?-K~x|jks1IE?#EghNMOkLp^b2n`Wgq(-zD>~tNn!Y6U
zUZ$ufh<lp~$lLHSeOiR+`kL+?qWr@V)A6$~%FpCTZ+L&xh7#}um^Lj1TA;~x1vCYj
z6yE|Z*yQsRIzvpoP9UMCjc-6M%=EY~>^*8?QhCQQlOyd+$4&7lZdrK3RPj78!%f9h
zDi&qBMIn}G(`W=pj41*?MC-y+rZeQ4$C=)vGT(U9hztfNnQAQf37j@b=tYujdYU$|
zEK|iHXgX(lgL0|aCI<=x=9t!3LlZuzzX;PlZ*rnT(goAA^uo<Et*19-zNv<i)CDFc
zRb>{MPAr0=i>AyEfMUI5$}EDWBGYx+8H-J>A41b*({egbm6#UqhiRpzkh5SZGZiiZ
zOSvh73WO?5QzEcbnx6j%0#&BgkD##H)L;b56;srGbk>->o`hVjDS*-eb*2kLu)f|j
zc^Squn8Z|J)2K7Ov;;6srkCk1VzbF-J4lOZbvz_mO<Pr%Q=4hzKY(5}tqM+A{xJSm
zJ4H-xn3isY`JJXFI#hO<-lFqGw`qkd1bR$o=%X*arVDh-vd`pM1<aeKA*%oEH~B?D
z-+*a>D^PBk7Sh{r(DW_+MTShSFJfheO>;i5aKscJ2!Y!sYaeX6V@j$->#oVwN|nI(
zOha^eW7Jegp6ZzC{cz|VH|5dRGGWp#0@|d>k_1gtrstSwO`FzJVc(4Ds2z-%H65ao
ztvQo~9OZdanmw>>&HKrXv@?sYVJYp+9U)NUU>?7OPDk_RhoH~N{P^qi#&S0Q^F2Ua
z%%!h^)z$1p_rcuEztW4(-E2q&nuqz{0Vwn|-==GdUglKFZh4y>aOPR)V}6bN1Yh&g
z*8zIO{0@cX{mgk(2jXx3?lt=Tn_sa9XQ255I!Xtbop-~EV6*iP`k+{tdF3AT9yR;W
zCmoKNzncK-ar0tIBb+errb?)A^TC5)i7>m!!4hfy;5I;`%<Bjy+H9oYbBsBP;^HUG
z2k2uLvE~CV5I<$MZp4)0%*vAxh&TV;4zL9C&7BxaG_SIuh)I(9ne~7<Z9Ye(fXQYv
zd6g+<ffVManxA7p;*8mm5^!nehp5Q%tU0a_#-y7wp2oB@%zLh&m1%zeN62NF%a($i
zGviJi9xC&lk3n+GHakFa&AaY`oHzH;uj_*O!92vRdFGjEn4fPxS%%&M^HDlH7n=7o
zFnH1Im<@8t{L`NREiym39kVDlAG`>d%jTjNp|`|*@DW&FYJUGBT4iS6n;0uMyHlRD
z!W{G}z$(o>1^C-nnfoYrRBcYC3v*Y@+iW3MV>O%ESfN_;0SjhWXZC&!R@9sSqAw6O
zm=7DFu+f}N+4v^&2_ev$&6AtZ*<u#Z->21l#U3ziW?y=KuA2J?Aa~6?od=Y5^R{AW
z>M%bW2Z2s=GF?UQG9QYEzHakZEtpx4*;*S2`CfBzEo|#EFQ!{sH_fFl0jA%)RSWq6
zvxe?u+%j)`AM%6doKp}OGCMs4mSOYr^w%0OKSK$n+vZ*>!n<Q$yAWe{%~}c)-ZMK>
zP0XlyH&xG#neW8|Y~1|YL(n&2K5wNW+DUUd?T<6&Cryx_HG9)R=)QRq1+N~MuX%uV
z&iwZ<)X$r1D4bzy`Qj#so#k9ORM=ZKzX3T1%L;N+94-4F#&S7X?v6vRvt`B>U@jIB
z{XASP?UZ_QvwTg_BX`TspU@l2!!r0YcswmT;-JFI@?Zzhye;>(fcRLxAQ)c@heDM{
zEKPJv#?Lac9`^cMmXM<yU<p}-R-ol^%3}vv*bNW}wmfkOU?CQtQ!q5t@-t;b!z^PI
zkUnbJO_|(dmewdbu^qQK(EH$o<rOE8aEsCogAta?htZ0({F?^sD2sCqI-@N=?8REd
zSawn-_oRjO63}8Tk5E4Plx1HaSmG?zH!;I_i+dT=Cs@MDK@u$~-(Z=OEYdg7I&Im%
z9MH*@$2!SlOtJh;zIdudmJFUVmTL*XPP6n)0OqV^J9!l87T;$vmSK@lm@Lz>fN~;P
zmOax@f6j7|T*Yh)Lxfh2rEDYQaxF$GiaBq|Er!AimWL^EmuFevgU&*W%W{Zcv~2tY
zE$bzVCpj2JmT#!`qS&&u1DY;d>ie;lC6*s45>RScbp@bh783<r%PlH5kP1sam0(m_
z8tC;|WeKo?rP^|04O&+$H)$8BvCO^-6}6V2jhIB8WsbatddnGlGdEb?Uk}bkt7R{_
zZcP@)9*}0sZUbi6VrigoN~>i7Rc^IeYF9$yswHm^jJam{*dEyJmM3yB)?w*WLGN|T
z!{n0Ru+%*bxlYT^k3gWyvViLOyDclX0=ma?iVj!3mT*syKFgk~kh^KIzE0=le#>+g
z<~v|{f}-TNEYE8oF=z>$0nd=-C32*OEy*`PMl4wwz`ku6`wQmZvApC7a@X>=94PlJ
zahrfLYI*ZDkTJ`<l-C`%#O6S5!m{fzkV(s+GsdPYW=j1|Ti&tK+hxXbd=_(>wXEvH
z;C;(yloWhm8N7|LIm<F~%jPXp4@1J%W`_R0b~bO*u4Qj?<vau&Y<#I6($R+H3A3GS
zO6;J?)kbYXr<=_ly8q*DbF&d+9yT94VM#n~Zgc|E%Vy1YRy4hBygr6{ADf9X2>ROm
zMP+D5Y{J$+!q0|hL8re>e-Rcqz$S(&Kmu*7?}G%{{6<lNV4IdfkPsUiiphrBJWCrz
zn9cB)P=D0s<!$IZW^*+R3Xj`Z9|!aan^k()6mIj$n*Uc!+Z22TiAbB9??Y3R&04Bb
zjJA1<;>0mFmw!U*q|H70dBxg{(`N}z+2m7DG|px>B_rc)yeKD<V6!zJV~IBIRCSkR
zGe<>br)>_N!BQsMu*fAyvH86Ra;Y}IE(PWpn*)dG{g-CrQh?@Jn|Eg+m~Qj$|2Vqt
zxU8!#ZUfs(v!P~|R;HEKv-jTH(bPB7N-N8Tw)J5Oq6jD(6c8B-h-^fWDMLX-M3B8y
zmIyLszTXr7oX@%Ue9t-eKEHAAIp_YM!;|TZrg8u?7~XW6A(L^+1MX)r=29`-S;o`!
zrG{*VXaarb7^~>Df1cr40`GGe?*^jp0^`UnD9dGhz=lX3V~YUh^BEsdeQg25gHCc5
zGXAWCh`osMI-O>^2;CS=G2`F>5G9O1%ot25LvR*|GKPq**-H%WBT#dh5tsmxa>o8O
z;3^p(|5qc;SeXWqD#quuy|~8M`2s|$8Lv>@?>b}4E0C;V?D!1IZZLN0Fo;^lVtRYm
z*%@Ug0KCcgiA3uei5=h?7;z(TrjgO~8b}kPIUU-X8OJC`-ojY36>3@;ZWkfh#t5L>
zxSjDfWr;f&b153y$;fJj?pus&FTm1mMuR)xcNo7@My8ALS0<e4W)x9uvWH<G_J_m0
zjD7zA(Z`VIfV<1+r7F07#+MY1yvI06=gtQhPcwiYWSpi5&wa)_bg+JiVWCIiFk^))
zl#VdoJO$TA87g`djxk~=*gei*`2zQV@u?Er1S7T$h9((LKLhhqjP>^CfS6{?(9&Rr
z@$S>$W*Kqx5OQR$8h{!n=DqL1IWw#2@^E4P-2~#wT)6`V-I%rXpxDP;u7?-y%s1$z
z=)qLcx#IoIKqEvvnF1<*Il!DNf%$_>-6jCMn02%mKE&MRMHQRg%o|&v)Q7oi4~Q@G
zwP_#@GdDd0a)h~b3bPl=jHT#A7&Ax=OGla8@50hC=3l*-i*RQ9k7$fw-hKxnk<15w
zVZ6tg(UjnfV!F_F>IC!O8uUdo1r#uiV>USeev--KP{!^QbKN1>jb}c63!(|k+Fw8t
znWGdpJ<a@iBRoxF=2C{_4D%XQJ0&x>NkLMWZ}6csmAQzP8)?jcX=RYkyhJaz4CW+V
z-I>fqaquFGxtfAGXPJfjz-2QVC<1Vfd8Uvmrq45Hr!gnF%tbwD&11enHR1V8^M@b>
zOtUXYA@g5~8W%A$N8r;%rvEaiDQ3n|R-lA=lkzmB%mE7EmoaN7e{hL;=^k*GnXl6Z
zsGK>6Qr#8IodvLPh3Q2HD=V3T1oYXjG8Gh2t75uQ?cg=$_#f!3W?q+p++dc`g1MHt
z=W~eEG2f%0%1vf6g+uC@><ZXzV9F_6)yRB<3(~}#JB_|(<}*KGo?DpLS7Y*8nGfg`
zMH}<bO^|k`oc1~$OtlD-opvVM6>4rVzgPouo0-;zf!<-pgureW^9(KPx|xgx5ba^E
ze-A$OG9RNu9DU4E3JBa~?pgsrKNE3y+$v0w2TTkwUzr1CgG^Q;MD8<7|Aoj9Q}7L(
z8D{cYpmT(|iuSpqOnc&s@Met3UW%EWVAf^>ILQ?GgG@2=>S1Y`=^77ihWYXvn8aD8
zmQpfKERh2M&MXGatP5-F0PMQ5j?<6s#tLkK-F>XLu7h)D9ij7;9xOElO!u?qQ00gx
z%RpQB1FY6%Ly$Sh62Am5yja`l^v5CAQ<PBlX3fb2!iRM;(7NoQ7ws?6^4E{`3FSom
zS#B3G-T;<h8kPcCzf!0&h}B*UpMqKW`=L98<xUlwp{z5d&=SUaZVHYbWz{x8^)c49
z*Ptbw^%EU6k6=Ar1}%{+Ry+oAob?Uu(V|$t{|fE|>mgdVMzgqf0cZ^CpC_R-mKE=T
zNsMFNq*X&aD{mv5NnpKCfxtvo<83&4n)N9~h>}>r`+z&cI<yd$l36ax0Z(B$Q)D)k
zb+8<gX{;Y;<Ce~n(!(o*mD~YmGFeq=z-6&o=n&Ldmcy@hh~~52dH}Y7)kDvsLe|gp
zQY>N>EQI-stb)BTSj-9z0KSxUolY;7u_iA;<Pz&^+Cp4rEv2n^IV*SzM6R&5(BiO?
z<@7K5uCfX#aaP5e;Xv6nR&)joU1#Y%(O1K&eVR(!Zm^OAz}B*?|AiG;t#k$6WbLd6
zqMntM0c{Pe*ZzS>Bdhl+%r~)Wxfn$=t9d2twy+9fF~U|>7$pPSSjS#~NIPqNJ!YnZ
z6-Z&oPS#V^(0PmXFKq~Jvwox$-yPOMEbi<MT`Z9eo!zXKHBj2aQvU_g%PM{nz&_SH
zR3UJe)mQ@a{VdHFXuQYT5({pCRW$}O$cn6m()+A$gfKtET3-d9hFO=$?Ge^Lv_KeT
zscBs^#^QYh*Ctr&=-liiYh)J;y)eb{>V)}eRxy<T&#;;U2j0SESwZ^)7q)8~h%39A
zzFXwRwo&@soxO$1K|I)sB`~<39YhIEPxdf{6A!T0BVFU*#lEcucZj`+&JugGnG~J#
zVQ=X}qc3}f89EQMH{Sy82>T!{vi#U{Uj*@I=lp@O1hDP)7Xb`pZ_j{C5PKhOZG+hn
z8E6b)m(oHzls#tyw1u(XXvaX0vQ2D|V{8-Mcj4^w^sJ9y3%5fglD%OJJ{@N}7J-Xm
zSN4EA!49Nq_h@!uBn-x|J*z-s*&nMQ632dVjU5J0vM-ilN=~tN)3Jbf_Phlk32e!6
z{Mw1^H!0hCn$6h^50luto&tA<Ef>LjD*O9mkW6EL9sqyS*$K1}$zXS{fZLhu&bI*1
zVlSjvY&Ls*3%GOauU3PcXJ<bJ$sG3EFVTsg3+xpO;7uO;UL%0{>{XQ4EnvSv$Kndv
z&z!>ui`ersAyUjf=!Y?tuxsf*mz1&}`3)jv?3Z5#?h@PF0m;kkeoB><v)`tNW(9jF
z8X{NN$y5ei$re6<_gC3V=r~*zdj#7WyTdiMDHOnJcKcJ%eVx6ERy#H9j9xU}U<c!)
z?GCl<b4!4zV=ttD+D-ONs#mRNU!g0ZfqixWeT{5a`t)@Z+wBf4HM6gd!iyI6TDs&~
z+0Em?wXuVK0oTrc5CZQz*eR)i+dJ8sT6lVkZTJlnb(<X$3A=aL&xjz?#r}&4(#>AP
zL1Q0#s2!H>vPI{iyPv&a4)FKbyC@7fz!tp&kwJDa?OBG{|Go;`F#DSoXdGeZ%?CHi
zuBC5qjIsYd1w#+mZ&J!@!p?Sk6m*jPfYeN}xl~s;&32+2XqG+qT>u?9xlXX_#2Hux
z&YAOS4Dc?TUw?)duAEi0_Hg5vDYvkXQ~CmwxpU&FXvl-(QH8nK&uO?1&XdEq3GM)=
z{5Q<#LC!(C9=$mBUW#iU;xtg%syAo%D`@rMTuZ@}_;So2z{FvWXg72p;Vg_mpC9K9
zItlI1d3`M!12_>B<qqV8&Ol2LXZIEWf;n<2{0-sk7=_(X&c&VJ!Z<7FD9BOH7qsC!
z#@Ra`UW9XQ**^m?g7YVRh%S<Iza3s2=WL{SU^M3no$rd_sIvf!<ro{m#c`S$z@OwC
z%7z!GI8W%%7|)rj1|X5sNZFdxoCrGmmBg{+!|oZ*lav)p<~;rm8dEr{zk!FToYO1N
zm(B_2QN}xiGoA$VnVd(cGB1mhdk^F+=leuh%I17QwT|aF-Gy-NJSU1CnmHUk)$U&4
zJkbCym$SPLfPBu6m*G<Z#~22#kR#a)QpCy1h24vs@*A*F%=wxwj}lJ6<M5)4GsdCU
z!X=JN7-TMUn%@S#oU`&JD6Qc99Rw3sI2U^XtmMRyhgF;y`n9fc0y$7q&5;)aaGg`p
zj=mbswnp^b;AAHOSIhZ)C&*1s{C<#n&bD)~(7+kGin(ayY^}tQnmG51X#LpAd7cG>
zZ5*LHw6$~ocmY$>!SVkEqMe*JZ;av=Cxf2rw>kN=^XlT<r_fzDXPUN_J)Aum5b5Rg
zQ!z{*XG1-lxyw;fF-$+_FunZ;IEKg3ILKLg3vS=%Oe_Lmh_j7Kwd}*3w7<cQaGW0p
z8RhKsgqktV+-R5|=lE;{_ka_31U^l0=Fu6DDbD&;P&3Wh6#{=}ILc;>aF)~mJxn-q
zZI7VQiMxdsJI-9D7?Q5sNDGv?anElAd>@zn8vyRyG1~Kc*txHM2i^O*-%<6PC-=Eq
zFnEw#Lq|BhxIa$-afn+=XCu71@1a7@!G}9UTUuXkEENJD=FZTy?#J!eh(3R=!yf<y
zaOISL3*<gc-|Y(G#=j4pq1<^C(F)`4OMv82Zgm>CV_bV`7uay_Xd&E>;C}lo<|~qW
zlfGvf#oa=0{}bHrJ^?<OTTNlm7_RUo0Asn~!NA3F^J(-axqfsSD4yHp1(5{q(R?%}
za@QxK@ibRUZ`dSm*?e$kxL%RyOXhB%4POfPhMg9*soY`OGNo}pUW=inb0s{e$>gFs
z7`FrWe-t4)%ME-OUSxB>rVYh8?mhY}$$74vszP$OOu9&OxpyW3&*L7GK{B7)c@|m<
zxC`hVRmfej0$dT7;Run7+`JNy67Hrly8lYKU(u?)j5~o1jl(6b_h0C|%>7~`ezkHg
zQwWg??uYImmE2)}^j+o7qlIo2_j?MsT;qOOfW~TW`uCWb8(c>PMp(-oSpwJUxV!0#
zDL1)A&4AZ)m${;`fjdr{!A9<_eUx!)=62D`t%W;HGt|mG(FTXxxT))4zMb3sGjw-w
z8|X^v<lelGzS~@1y8Z8PSJEQ7iyJ+NpQ)RBVHUc3xDCxP*vobM0i=)n)(~)ax!OgT
zu72)wMd0pn<0!f?z<mv`D!apd?p-SE8{#HhfXp!0!x3JLa9!6z_b9h|3Tno<zf$GZ
zIJfyln3&-1n}>l;azA|-l2hEGA0Ro+<$ns@Gu+(`=$qy0KEN;H$lFD$NoQUN?O9xS
zTPP~%%6p2|T5ddl`d#h&c(e2<cIV~Z1JHwak_k~y-n!S(d4RWR2}~U1z4<Lfym+n0
zAaaQJIBgnyc^Bz)+F{;-xez(Ri~SJ*KOX0C`0LL*{RI3C;Jr^GfxO&mco@u6WrGXh
zeXRl@l=oX1MjdA7z4SC%kMi2-|JEGisrtZ$^QwzrFp{@<F&dBa+;@YE;$=Jw*G}-(
z{s=Fkd9GC99m8w$$6#W4ztSQtj`zQKkdwT4dTO2G9oY<cJg;;<L=t)Z^w>DfE4u?+
z67L`#jX1-zH`4w*nb)!nohiI@+UBS7rm569omYDqB!jny>L4?DW0a@K;<<hXzt8d_
zW+8c=$D}Ix9G(MRvKM%th60ewt0a=gi=$m{K93y$^98)usLH;G_YjpQUF0d8z!md8
zwx_{-2``(1b)~%IuP{+%yb^a9yu{l!1<`U|JiXN_cz-X1nk&3#{{dIYyDf$8tGqdn
zp|Ogmrse)M-W5H(sOH_JWc+oWjY8Npyh}@=>;`Y^1iY`~MN+NCP2Sq~V7{LBorU5j
z4ZPT2pskTNMKvZ(yc$n9)6Cnl4SlV=6A=(?<L#sh)pp+GI4pJWS{FliC-0A9h}_}*
z`Y9ak;<bmNv70wl40sQ3f>ye{ye}zM(Z{O{0J+PPQ0V&}ui_E_1H5-vQT}d__h&P7
z-{-B|32j3>KPSix^G;EkXoUAvCX|lxF3>AyoVTnTY98?Bodh?*3yQ+zP4Z@a;Pw<x
ze+|Q)=B=fu#tctKiMv^zb0Z`j`8(*cbmA9FF<mbF6;$it%Kv<Zwnc9I&nbVmkDo$s
zOm}|3ekk?eXPt)3ets4OuMY6P;y~mepF!2%Ui=O3LF5p>nD&O={OX?|a+p662kr>p
zl?qM$_)k*q)t`TGK70z`f4Bi-3FLb}gRunhBk#gc2!G?taMT{kU(*F(7{C5`Add1=
zDByaG|08`BDV)E9N-rY#MZQ2B=f6n{u_(TI5`Yu@+w`W5=KE9JCWb#mb&#?APjX->
zj{gCz#ZU5A)&Ovde<2i-@qEn-=u6-q{0L(?&F5tTkYwkF&A`MNzRU#CWPS`S08{w>
zR6U-`520{=8sB7xwhaE>uQ4T={KM@aS^N*b1mG<H5no7V^IhmEox?v*@sA7q_o?tC
zmw)v|j5m)z)CqV#|B)*o1^nJ0ptF!aZxx1A#J7jjM)xBBF?uVO@GVb5rj)-^3m41y
zA5q5q5<mI_h+O8s&x7s?{>Li-yux2^Mqed=2i^Wvd>*~_ukmeK%tbZ-ISP?p=XcNp
zwT6H2Ly#MM(_N^p<sYFv^i6*Hevo>8gPkfE8~FF8(b>pn(lNj${xaG;H1iKB(bvKc
zrCnJY|78d0Zs)7^L8OE4K;eZ>elkUrZ}FoV;L~ls@O^mL&EHZF?|b+;Dv(}&L^E)G
z{O4)$ewV-CH7M)nSFMBOJ^t(WY5zCCANdk8gZ$KwL5BEZ3Uv<i4_}0fBYZZ6t48_D
zC;>OdUzG<n5BM#U;3oJxO(2u};=5>^=8q%+KEt=ug*eNfvk85Uf`e2u;UsXPvq8>+
zvH@@|f^C$Oa1%rq(?87FCm8ku>n<3390(6VK{EW_FK8@=Hc!F3hcF2T1aDu5-(G?+
z6(kP{wo}QZw_wT<N__+`(lgsvu!<5ihXprYh8BOpn~vZD1pjWvKm!GCzk&-A_|h6N
zSP)H7{SZNVGOa&D1ua&vVS<`$_<d9`>IZzdAk7P2L<j`0gNqa}X<>3)aD|@BQG$+Q
zOn$V$jUvM_0`9l)B359c%;-tMkp&pxDS<21<HrjMyx?|%z$ODp6jZ$r$<qQEAMhl>
zelc{~lLhbo1vM!G#xjsp!Tr}ElO}kLZq;-_;xlkKL(sGhjhTWsQ*m9K6}UYOe6~PM
z-?ls_`0Xa_o)>)B0?8b~JSq&jAaDtUvV6f2A+!_-I<5m=C}?GYD-z75yXm4JJQt+c
zF35Zo4wne(Dc4;p_%0SQWdi1E;4ca8e+P0|@Z~-9l?$fnTy%xt8>*zZBG_^Qb5SYS
z5(@6BAd)f$Rf4DfJ2fSk(!-f*LG~vATo>fWfz$|+OQ5Aru!#1JHwEsrudf%_U4DdU
zgJ2g`)HVuEM8SNMz(_R^%>sOzA2)#DC3;u23I-`m)+TtL3(_w5jWU!Sf^HG)b_#;2
ztmBs8bxNt+7HrJJknRZHXTVaI;QEi4l5WBA3lQlMT%#m&uOMhG;C+H`?Q}of6FmGL
zyciH9g@YRuyf_Q|eL)0Og$)T(D5^g!=zI_Ej|ld@2c@HenctywOz<!T_s0c)&};00
zpv4gv%Y<Mbor|6nY@`~KDS?HSq0@pM6C`H@^?!kz73g<Di=*(zm303(3Eg(XuCwsU
zC^#44TU*h&PdGmucHM=qybXsvglFl%!+zlzFX;9ZzA6VfAdIKw`a$9AWYA0KaTVl{
z@UgdG!drNZu1+7}x+yds7S>I}nIpmj6gBn}{yq$xzwo;+DSsCrOsRz3K%onjxd#cq
zr08O>u$fjnA;K*b-VPPIhM_M^c;O|GV?u{u_!};~r~ru&enc^>NMRK1!;TBNRN@jP
zTvm<76GHz8*o_v}QJF%F(23GZvBGn$=!+9x-byE4PYIL0z<A?@FVcc4K{$8~z9kAr
zY_N1%80i3#BwR*OzB58cTJ<Ljw^2GRMfgz{8dHUXi_w@S{EIHHOkov0LbHT#FM-He
zVfI!ylP&ye0>eHhETI~a^TGv>p)p5zo(jh77lf`<XPztUr(j>6u$5jU`NG@N5G@o=
z?1tY(LWv%Y7lju_0W21}dSRd?!hk*iN`($fLCS>jzhR)4gw9mUdRf@z51r-0C8_AE
z5I#!T$4X(_I7W6=c#fWkRl-RMIb5>~<0}BH7XBoJ!Rx|HzrjR}FfJW3H-sW&I2~$*
zV#?{)2?sYr<fbt4C`1~BHI*QZ!uM`NvPo#7E3jGkMk%-!Vd`FxR-uIpT$}KY9+K_C
zO|+x#5PFQFu~Yapy&`W3?Jg9I?GjcMVocq_3$&!~5pJOESg+8Va_fD<athDg73wLS
z-7kFcX8`XBn<+6gAWWeE)u8Y_$`RZbzC+8`VPXA3h>Qp~R>I#=p<WIPW5Q?CpmSWP
zqa61GVXO*dLddmy!qZ9N4T_3R3CofpGcCM*6P+`{-#3FeiZZB5%1P9;9g@zX+9gox
zA}XYsDOXW?BRDtF*)WiOqSR_wau*q?B*#P4K=ZU;RJR7IJw>0SLFAyQO^QY@k**Ym
z4v9R@(uq57kvs_qAJHyckPg10x9Kr`Skz0Y{Uf5u|27t)9t9BoqAw`}79hGzshnWZ
zxAXz95Rvvtj5kyyp$u@C=ssl(j*5l_Ajd?~`EWa2^sXlW5u&0qun;M_L}zS{i@G_q
z|BDhmHv!RT(HFE!iV>wz%~h;u1D)%P6aBFfCQgdNDN}Ju)b$%kyy%A^IFlf1m;oSB
zwE9bs)1q%*0xn5pJOq(s(JQp)NfEs}2bNMrC+XdmCYlKbmoC~*r6L(3LCGB4f0?2a
zkHdVHh%3ji&x#f%KzFw2IjVs@CwiDdjya-m%0FBX)t-i>T+xM2kUWtGEr#<&d3KNj
zQ5A*k3q>h)Fi|8L_6E5q8r}(9vFHRn3`#^wK2%>4CDZErvgr9v0PN)=CT;91MA>xv
zUlFZk!(gT8`(NP9RnaY4aaM^oor0QcqJ4XTuNFN|i-7B**ZU!PL!@!V1l5Y7*yyVh
z`6fg6P0?j~tJI4YwL+vpG#LugD4M?xGukBL(<ZiAbaxK`Ep|~WJ<wZ4nsmsti=<5;
z9ir<^aHdn_a|wO7L@VhS?QKyVEgSBLHua;iOO#7d<8INeuOQhY`sxO7y`uGVAkrri
z?14zX=*nt{+!L8uurwfAAA~^+idN7z?!GA28DvOgKe-8rVUdQ86px59ZbNib^w%cf
z$3*koffyG(M$xuO(bKednG)@xUu0SoPEqz5(VPy5%!;b$qY{qd9bdzslQ@t(bQUi-
z3F0E|qZo&)IFZiQxrsTSU`E}=(L*2};$}N7RriY%7Qq`&@iiBS9uV(%7tS0M`%^;K
zOPsL-N)L(KP@3xCEnZ6jbszC(70~S~UakQ-B2Kyp5kIkZEll`}gVTWv5U(glW1x5$
z{ilN<u`?ZO2^OCqdm-YS1mHr&Z}!-sG)%l~E0i7;i;iI~!o{j+co899O>wSBu|@{&
zxY+*;xF~TwmED~X`%w{IwAc}eC5IUCxAY8*70;#BS)6$JAPk-qFQ7M8g7^@{#S_H_
z+U1`X%l^eUlf=!m<vAl>nnGWkP8P4EU3-dn4Lx>J#Z|w<M4EWyB)D{ONDa6QaYrQ(
zS>i0Joj5BtUIxh)e@hGWbK=jb?DV{tK?e<U#7|s--3#LRQuO7Db1BG}Ctke-uH}m_
zir{F0cmr*Dio~_Z7}y;yinmj-eX;oV?;s`O#WAo{D*lmP`(@(VeBdvM6GMQ%EFSq9
zq+I;=caW?QUw#E+x+1oe!u(Y+UOc!}#M4w@a7`RXxru7=KV$Iex_E%{l{Mls3aGvz
zUSWimTJc}|pxRz1?mG(hrZ}+$zSWBltAJ<{drrW`X7Q?}AT8p2icz+ULlKd4=n!vO
zj?s6D%l-lB6Q>@5!Moz}3Xpy=o6bVr6NgbCeL%d$1~MrAfYwF##TOD`VMx4-itmQS
zD-0Omh+SMpg+8O={(r!ZiC=sfGUMW3X=o3`DYUVl5HI=#_(}2W^xmBk*U}?xTKpH~
zBxl5rYyp`S+m@iwQBwF508Wzcc0$rw(p!R&xk$RH`qWiYumIzAlk}M|q<xZc5ys*!
zu_x_@K@Z6rR86{HvWO4jDXF3)+X2bmWf=BBiHNG!y(F9bpyrUo{X?knmekP$&PO7o
zq^+-{nZ87KSn@{*xFeFsH=xf?a^QQw{Uy6!MPGpApADG&K*{3M&=Mr+qx5dDWWJqV
z(IJwr=w}X<<kF)sO!67!|Bgx==;Yin$#+z`7%u6eLi`BHx5JQ(l=PIK@wns$EtI1q
z%jt;13CVIM0MU}DNWfzxe|`hWSjmbph{Q>J7Gg?HO5R%ua!S%o@$`5}r=9A@5+uof
z7;mEFd^4uzw4~Gyzmp`&4<UL+@(o=A$&z_1VK7B<pAX4Y$%D->ktPuxgHP#_JW4!d
zNTd|5%9K2sfyOM!7OE^bE2*S)ezxTF_W+!eFn6Nyg5*0c9L<%ux>5cwPqK#=Tltbg
zs#7SC+)IH>p`@G2oQfntl+?c{naM|AvE-Z8@To+SaR*$fB$I-hWs>LU*?URSMTLEr
zB|dbql}kRN2zrI2w;gt`NHTT;P$>zc#q3qdG1@6sN!Vfk<^Lp2VzgFEVopH!b;;9|
zp{bELe+e&cNHQM*zE(0zl|gk9uhVF}DXCEcP%mM&LQR82MVD8jq+$$qn<Q-?!>4A+
zIV!krk*wmwi&n|MEzr^?+1w5b?Ghy&vhI+qrGT8hQ*xE&>y{*nu8-T26I3^PM>2Q<
zq)Q^)1~uK1hn4`*BiU7qf%Z!5T`<@uX{OqiyOKUN)bvYs97f|k$uUY#4M={^0XHZa
zp@sH+$@mz!AxYyW01Qj66+>i1;@kkUqjpKepKx(ZqN#(-xWq)kiU*Q$8sUWGNm^4+
zN@nOV#gyc;RESJV4D?`}k)+aIYgQ6g4mFO_52FBZl2(xy&Qjj%5OI+@&<oR5YJC$r
z-K3vW=wP2Thl-utrH{G6H4mxXumJ3S=|hQNJ*BU%19w1LV+1)Ub)sqsFX@XuFySNJ
z)BzK|Qu{-YJS^>^11(3SEmg4OC*{uvz+c*?L0^FMs4sAVQuoE+f}|Jzt16MEH-ih2
zCQ-FRsPti4<Aq66?etlpqf#r~_s68qQJN}T>J<XNBcw&No{N-*ypGWymu~MwUzBt{
zRW+ZGvMJUPEv;Mykr?UGuRvm@wkL53#7TdD29BPT`t5+^DQONxz2c?S2J|IJwNGLa
z5~W24AaYvza}HI2BuRT{*k_~%sbniz`q7inog)470UA@KsgyKMlO|AjAYGb8Tb~T+
zRyqurDRm;BvZQ+{h<jFg?kGgErHp6LcTU<#bw1~%n<-YGBmKz$kqc7u0JvOfEj{!K
zq-Rdh|JW&%ZlgmSMbcRfrskqFg^EIprEh)*-6hhG=%HOIjVDLTq<`iDe@WVZ0G2LG
z*U-nO%B6o$5~f1BJ{*!)q#Nrnqm|MdYteXB`q&dtRwXTX3GnOE%}S6OsW+vNZb+XH
z(f+SiTE~I5I%zqD=Wj~uDD+S-ecb?O8l*|(P}3;gr9@wo^nX-l)GS>}Ys41m9Q--7
zN*g|hNSpMjpJ2XS8u2(9JESZ+7}+U}qK~BClKx89_-*NW+F#$1CjSqlOBzY_wf1gl
zJC#iKNUzR8Yp-;GvY36+y=LI=N@E^@r~T5sAH(iF=~Bu)4M>-Z0UVUprlRk@w5$V?
zLsADySr1E>Q*wPo%B1!7sI-#mSH`5jQ{ZJ>`m7k-18JrhS|+5Ydhqj3+NHlz$Z<-#
z;SiKgOJB^xKxd>AA46tVDmV<+9A(*mLbsDFup5%jvS(h$@9QGF+YNxL?AeFV=O)`k
zSIIsZcLDm`Wm_q0;~`^w4TJk-fs}UflokFCFAm67{tOQf%3di0+)HNnJ%XVfk~P!%
z$Xhl*-_`Pw4VplFWf?i>J1l#fQg%mVS2fV)C;Na>!2YtRRp<+l4Ie~fpe%1a3<k-Z
zNK3HHrxun%WWW3j$xzuL%A<wJzWEMb9F+~-gUB&iHJ$1Sm))_y4oeZTm*^=HDZ6q6
zBRno!LbY^Jvf(Yj$H*q=VGt`@K>unXPIi}WfRnOKu~2$S7Ro_myll-RoJo*f&wz<U
z*&ZtBJuRD843Q*RWj-3u$QDs7Dp~gLo6wmebF)HAs_aERz5mi=uHI0SE_;h&!5K1l
zdiG|@G;{(dOV&kMfwMCGV?bof`Zht$Iobax^?Y8ohAQ}TWam$#@q%phIY{QpHpsx`
z$%?$d<;yO+VW0)FKLbGuWi!7+b&+f#oqxS3yW~jkzhYU;KbVsenagMBES05G7PCxt
zXcH#kl5FQfXuB+HpwH-*%YMHAu0nQb5W26(DrlZ7WdY}*?W$~=*2Gn^6pAihla(HW
zht;xVPk4A;_U1B7LXGVF_pneW%Pa-_rtI8FihtJ2M)m{PAdCMFY8quHZ^KfP?4@*w
zHp}i6K(s~HL@(S{S=MSuw#keI@S+{p1x$3vRGWb7l=;vr_Ll5;G<>=(dwvZX@5tID
zAYHP8S&(j-a4mH9$liVk9`?!ta-huKC;NyZ;&)~K^i`yO*~K{E@5ydgqjNwOOG~Ih
zS>j^2e_yusJVb_Mc?GaLEE7<~WJI=-&d-j@K6?u0$7C*>VPagC-herLAk&2aFd<v_
z7WyV-A(TIulD$fCfoa*7mB7u|WiH#HZC2*}Ftj<!)2V3QN&ZO$5YF=NXba*ZPi;q^
ztK9DkXmgWuo&;c@d>17u-Q{1r0f2}6A2#gnm+##J5l{K>Tujgbc_M`j56TVn<u5Ne
zk190}$uH`G^Oir>f<_;?olQ?4U-?2IL=VfmXd8G$UPl*%pPWY}MgH<~iarI%<9>vt
zK>0<=YX!*<e-Aam@^)Ivgvi&?<1SRLeFUzB$zyLo%TakgRo@+xr&1kQxV)8C))De&
zXgw7v|Emw&arrBDcc_VyuL}fwLVoQZAfn|Bn_)giZn+ONv2t!826IY2NujiO`Ii)p
zNswn!HCm$FcomJO<$gMtPm&kB19C>Le+oL2<#*|ZPmxbaK~m-aoB}RQzLYA8(&e!Z
zAQ|!oXS)9~<?)}uZkBx85AfoweEd7;&Xx=Qg_?8ndb$M8%TKxhpCezE4-*&Uk_eDo
zxd(-9^W^vFlNkB()fB=mkndLkUMT-^5lj@x)4zevi}Dv}N{Z!23Sp>3ZlQ-)shr8D
z{6m?1T{;k#<d0k6%w>5KEndpyc>+vAh5T?8Ok9y4p(RwMJog}cx+)j0fVL{R^A-4X
zP5#gG5UG}*ii4%=^5a6-t&yiuR^W!*OfTbFIh(GMI{9!9ByY+?Xc5pTpO5#g-JwYy
zMFk<v@}pGv(jtE?7QVI0*H9XxO}=;xuC>eSM&V3{{Jksiuv6|A0{kuc5-|+kmOoAY
z-jV-KOY$!H_lMwUx4e+5GJE8I)j_gX9@-4jCx7Mu%-@waw?SFIygC^c?Dyn)HV^}H
zJ`)ZP%4g^`cwhd75ZZ?1S*u`vSbpzQa3gYu<uE@gf1h6MWAbM+V0T<@piRRAdBG9%
zO~@U8MdPIWsR1-j$&=}z#k72eDnMrB<}uivl{@>xo}<Fj58`B39HRB0vtk?V%v}_k
zx8b*|Vm?J4-4y?$*vvk~!<XTOyP|?#Bp!;t>Y;7FVj-3JdMd(pLFoa7g?^YriXO^$
zdMjpj!3!V7Svtb(t9YsdjfWLaQ|aOnMN}dh{S=*jm=b@5ef>ND0~9?}6cDJ`Nb&d}
zMF?G`!3zHyFcG2{pwLjLLQ8MqFhx-+`i?55zXc#dkxHj8A{9flS30hUqufN4V%0nh
z>4YMfVinPfw@*N4jAE$=ypL7fJq!}3NQ;KDlZr_D9MDsW;oER3Uh()&h$bj<D5IOG
z*d2(z(~9uNG5REh@q1`Hqu3~g?qtQndGI1dkxO+Qsfx&HaA}Gk=$cDcDC}@1L$N#-
zBg<5bJ&MLG#Vn=D&nnhYxlgvj3rE)+&M7uLPr0D;ic_?t&rz%tz{CZGcO7JM6+Z-k
z<S7>X43T`rTDq<Z6tl+xEL7A`0<TCBK~M6FiiBx+SggpT$W)0U>^`_sMcG3zU#5uv
z8#*s397F(IRy5Ogs$5Y)Uy`d(WZ$6m=M}{_FTvqT#hQmOiYmoqDNI~bJp3p~wZct>
zzUvC!COA{0@LmXmHx$2`AX%#z+XG8=iW4!=c2lvJA~p32N1EUUg%_pF8WnTTL9$8l
z3*nj-4<3UTEs9FI5?U3*h=bT2Iuw1B(d|_1IStWUikBBd>1~C4Kk#=H@gY#!rLfUM
zw_DLtgT@}kQo1aA6(^|{s86w+iDBPWJa`8p{fZ<pxO<9uhafVbc<Bu&8&ouRLd$(c
z2wjLnivK+gEyIfYLNwY(6tV9DII5_pXx*5?i$Wgbies}N4-~mnGcuvbq3Fh>!eaxp
zO(~3CAk&I(D`06xu`U?i&niqFQ0l1MG6$n~QhrZ6AZO*@6xVi9o|pp>SLLfzkME`w
zEP~E`%Gb`J&)u%PP0<_=<rzBgv|rgoc?3`8yf-0wKv}c_CJrk5DIe{njJpDnL(1Az
z;JuZFEfDch`ckalSLsUuuEWYt;xWP_$~U7x{FJI(5PzkRb_4;+^|=^tpi+MdBMVY`
z&?%Q-rG4YWU_+F9XnPZ?e3H^9VaiwI(RoxELr1xeDaWb0D_pskvaS)zP>P*LD&r`w
zcU<{cBP64gEu+AlQ1;M=V5613bUG(Sd0r0^tK1U;Epf^}HUV%_xq;rPr<4aJ@IGGo
zl6@Rglc3BBh0;XjI6ZAoD|cstOHxKeft*pA)1f<A`9(e~r6?Dj20m5!1l^5k%Jp=^
zrz<~v6kLXK@_h_6Q>n}Y$x=>rq3^6Rs}q21<@Qz>I;VV<k|F1n3My{SQO0~q`G*V2
zBf-GuDnF#if1WbK6{7jdMSsKn0%amytQVCnK5(X3IbVmy66GRC07{j9CIHHmfkEiI
zq`Y5^zROA%H}sV&_coxfLa7Qz-xXzSF$`5IPwvG4uPQ&IZCsV|3lGXaTvPsZ4F;=~
z-9Z3eS3X6l+#2OnJ`gvQGh;ActNb$=h&ttW!|?m2Qn?=UT(5MVMqh*S;zxitD!-=P
zdXv)jIr^HFD{1xIq8uy&u2tDa>7F)a$_vohuB@f)RELtor23am<yS*+@s@IX3?}%t
za_ts$-cd5%gBM*&!7Q|OEBE+Aq(_-dL5g1GLli^nQwsjO@s#Zz5b0O)sH)|jvV;O-
z1Ip}qP&TM^rwi%6axuMQhLjJe=5bibdlbq>lnvj2vyUpD{T!nhQ~FTF^|;cL%0nI~
zqh{dng!0cJXq!|PQqX)#`HK&HnpQGtEit3qy%<Vom24?+j;gFDpwvmVl2Q%Ms-<)x
zx~Nv9qtR8>;RMc2C8Le%KGjOv61%H9{=zst?5g+awZC5#XGW{1N^}*i2UII*fpSpw
z<b2@0RQTWXxbaklEfDcmee@|BeN^|i!LF}rH6@e}tCrI~>WHdg29kcNs3qtNP_3bx
zBT)6@3vfF~wVCd%VAV=CREMbI&Vz)i?78ovHB7ZW2)d7|zIVo$j;Vs_MIWw`wZl?`
zN)!(+QuWtTkmIUPDApLII!@JHCsZrgFcGbKhF0G(s*!(SH&*q`zfcyZ`cR9>JE=Oa
z!LU!MCYGWvUL~S^NrLLLe265f-m{m1J*~Pl2AL$4{1vD<qZ*=gUa~5Io<1q6!CUA{
zRYeP7H%;{>1zgirySIbOQ0=G9U8c&Lw%b{%b(9@Dt7>}<xNKGPFVJ#M)$9t%^Qv~T
zkfZt^?ZYmpu25t*S5@OfxvM<YJ2cRI)gG#=Do_<s^0rXr^dz(usnVW+hZj}zDBx49
zdW53$C8{@H2cT3H<p_~Ws(C{&aar|^3mVH+{ddt=p;~eSfGetA8vvCm=WH0fs@ie~
zKU0-zJO|u0Rr4G4#lLFRdHQ9pt0q@q^ffAF5<I=3IzpFTt?F5NOVp|CbI^BF<yZ)O
zz3Qi>APuTV|3+h@>fumWYEs>{0N1RlU5a71sMb<ItyNXH5w5kV3LK!UUA49mxDHhd
z?PWVv6G;8q9d4-%v}w7m+C)jZJ1SSIuIy4V8lkOQHJl9-J*o&Qi0V~^)A@%!RYEn$
zUDXbXg!ikG=!d<h@?gQlfa)zeqdurQyc%<HUzJGL`jBc@349t>{q`9EBdTq=0F0{Y
zVqw-krgD1--i)hktI+vCwWu1c6RLf*dY@EH(CT4IHN6#HOsjnUfYKS&D223URd2Sz
zCr5R_8*tP~9s4VYtJ?HmskQoi2n_C1Kl~GjyV`+nN)Pp^cfjpeze~GFPj&nm_<O*v
zR;Ga-RR2sR4PNS<N^pnN5;Ebf{*Lz9KI&_<2k=!l1VZGn`kSBO?-BLaw5;<}hdm2N
z{ndH&Itx&541h?W`WAg5CP>{yJEvfEbrnQH)b|&{e5ksCa*AQ<9$Ez-RokD~iq2zd
zDJ_A*)r$ww8KF+B0EtxR(o*%f`jvm7ElRy}CFbIUI^c1TX!Ujq|HP=5)8j5y{lO~0
z<J2!vj{KyWsRTKtE?N!}uYTDVmQJhZybUc$>hInG;EcNUEi@*pg?3V!qCW455vHmi
zP;50#{fP-AUH#PGz-Oo}DIl3@7F}go>V+rZ(^>VB*MQGffA9-%=hP3gK+dbvDAu2&
zo=t?M3+nJ$H0G*1JTSmK_0}b5%vbx<ZCIf0{{%V<)gwu?+$d6WQZa28)ujoT^<s7O
zVwfmVGbmYBs(#xAT$y^$R{&m8|6L2fW%Vh##mm)i*&tG(UP%|r6}7VfB9-b|7ihVv
zUic^as?^>`FqUiTcaFpRYW3cDG+tN#OV7X>_1yR9`w=(P%ic$4t$Mp7@OA2Q^me+b
z_PUIjsaM-5OV*&?K~cU&^*fyqX;QByN1N4dN1&}mea!=aR&@pol5J{kE=1bZE7zg1
zL*4Z>%y+6&sW9-Cx-}GiUFvh$knC3fwZUP|s}4Qt%QV5g>QoB$^{Kc10&-XF6u4&N
zLvPw2zY5@xn)5cy53BhX&^Mx1_rv_CI+}vHW9nDvaW$^~<zFa$fGZaw6YBXRAd~9#
zbi#K^9qa=w)9RP#7nxCS3c}ActB#_2Mn}zSRS<E~oO}jz=&VVhX?D>(^Bm^aRkPeq
zIT1I_8#L?tG)Yw9>aH=>LAQs-=Pw}kYX;~<il=6T3O5gE-lRI)gPH^>hV7*(y8-Ty
zW(O^ly)`2gN)FO|5DdG)njhwZglJy<8IqwIK5ZDoH1E+G{HSIxMKz9Tlxyhm9IkoQ
zip~hl_!UfPq~;#g2Oif9ABJd@=5b0Rp3t=40wP-T$~ct9XukXweX*L)&tMdBn&1ia
zozx6bCDbX+xmq|AuUSm*<OGf87XT79{uH4-t@-Fhc$lP#{{rNU=FR^;h?T5q+yOR4
zb4CVys%9Cj9?~>rRN0WOd5Ct#8Jb{P{AX%DaRkZIWKb;ltmY*K-6NXQo-lDvv+4<u
z^O`Yw-{xrCzJ&P;n)MWy%hkN{UmQd88XXJB*NoCyt4Q-M@4xi0#u|#&V$BX(K9^{=
z{sN_?nrC+cU#7XW7k!sBkw&PwtXc34`pPwXXmNQ(6TyK<rDjnta91@o7cs&rjlB%y
znnsuj6V;mjy^y@FNtwV{YBYmX1aL!B839tO`GAkH*y}VWmIHB9bBmVy^%@UK+&5@q
zb1>{i&DGuLYtgKxXK$<K44rpu*BmSYzC%;G4bF6G)FTkNrFn*u^0zhKAH&}}8uxS1
z(xur-@#${O(a)f)N0Z)yzFy7tB)Hb6;nM)`+BL6)L#AJ|U>2SCG+SDrbU^cf?)yQ_
zhF-|r*Ys0@bV##%5x8LupHA+KXq+yAjA}llx|uP}_Bk*(uKD9Fxb{G^jt*)}Xl%Cu
znACh*3Y}A$hu=fvwC3CgP(7oGm0;FpHFhrw&pB!Trj?_!w&MguU9_hu*tbvnL=5`e
zwbx29G!Jd1JG|JhO&f)zr&de>@dMgtKLk0X&8z^xTl?M%5b@DweG8Ez+Ux&=PkvfP
zIYj)mI~3pov@-e$1GOWykPOmJ+81I<gSAa>!$gSInJ%wT?E@+q3DXW!I^d}G>{GxW
z)1IeDT(~xh5_b{WM~;At)NcI_YL08WCLkH5O?nUT6WWEnAko?l*D%5u?aoN_#cDsL
zH*}o#f)dJ3YG-z#@02z#mcn!K+ABm7w6VWJTcValW%j4Fg9&ggNjtI_&YaPDegrki
z+P!qArf3gRVm4J9u>)M1_K$7g(zTU$p*uqx5(j0O+JH(pnx!3Yg2-9zN-HKPTbo94
z_;cEZ2IxGm?SGoe^K-RAiZ149H_*y4Ut6>o<_omGpMVr<-(f;`k#=V?xQp5m`i^w5
zHuMA>Ez$NifRt(<y$F#q?S5KTUDCc!%Z$s~a*FkpYp=I~RA?*tfM3z3WWjEwwu!zP
zbyfTCO8SS4RoW^OhIUQ6l%kT=+U>bedR_a=-<Yo&?YGAPyrI=bfV-*v^(}Dq+VdQU
zG-yAF1Flh9LA5bWS}{HDnzb9>he(U|`C6E0)v_OjWSjPvNer-4d(#0P-qQBaQRdrP
zxi3WQ_q5+EgYE%s_#+^LT7->ok!#JAd>zrYy#Sd}?OQDLjcKnn!P2-^PNC!n+Mt)g
zO=&}^u6|lu@B+w;_E!qaJL$GMVc5>P)>om$MVI&w%)9Co;~;Ljo!>&)KAjtR=wsKl
zy$v<Kx^haU9M)ZU2j-9Hu4ln-KV4WMEcxr6q<nUO?q3Qt1?mPC0vM!QPcs{=d-@qj
zhUnTUo*t^3b_Exv>!<DRQQc@88jtB>XeuLgbLqN>)csJ3-{82;g#s8+I=c(iE1b}U
z_JWPp_0#hvPPZozz>~U;9Q2*ieN6%8cwJ>L98J*Org=)#J^B(Xoz|sNm1B}F`zl1v
z==P=qkgVIK20TUAeH?wMx{?>crRi?0fk?Wpo5G11x->`hW$K=Nmg=#xbS4Jup3_|p
ztlEkr<K+(lk*_QK1C0f`)fCe$)J6Y}VHfG9DKd3Ym+=AA6zkLvAX%bgjKj53-R{G1
ztxUI$^8J@|Dq755*6sTnlUJ_ee*r*+?j3iCT+umgfa*%!FZ5}qtGZ9D;Hq@W8uVS$
zsqK{LtkD(Lz*3X0lGfDCy2&Rn-WHt$CBR#CXPhvYHr<bTz_;sI-QYTP2ezZ{mTpfI
zBya2d$iq9jG!Ark=^mwz&~)oU=;&IHuJbN%y}IWP0&rK?NrC@<-7E!<@98caqUw+V
z-NzIh8Ptu^DUSO(FUoEY=}weG>98)?86J-4_IQIE)zzh<Z%p^)ukiPQu8;1q30?9q
zv`p$=`3HSdx*0klHLXjb?{UrO4)2BPSzYrU5J&x(9eqyvND4<d>$5HN$rBg-vA+Ox
z)$1M6>ZZSX7hdesKh_JS?)vk8z<m#W0bN)7^}b<{^wdB7G{_-6m+Do0^urIJ+gHEu
zS&Z<oo=qojj_8YN|K_JxQheE8pPC2BApQIF-w=ZJjp67E(OZNRG7QzPT!GFoz3l>k
zNA=g`AjkCkZorFh{bITeBlJ60LCtafXLgJ?N}oLdkrVpiaA=FxGrj;kM!#Sc%*X1Z
zr{Q*-{s9%%p487j1udua+y91^c>UUC03_hwKtfBRe%1zJPtpg|v*C<><`CFq{d-?P
zO^W_yPbf{*|3o{Wbp2+!)iU&VYT-que&_<UW$9O)hsardz$xIe_1mZl?wnpr26Ob|
z4})CLKh}g<%hgMj;PUjLAHubKeJ2O573hbY(N}2KGw5VVseZ02WXklH%g}jA?@Wo#
z%X&M-G0OFSI^Z|BqJM*;43+wiJJEMlpI3*zYW+|2wYls1&_cj#^bY;#yP@}_T~)1K
zT?X7u{UpUU>-F>K404112M)9}>#c91uSIYF{$mWLRqy)<5N-Ml3eUCcpDqBRL;une
zAUgF!e?s)Oek2T%cl4oDpx&jQtwUe8{^eG9(W4Kfb$YKpr2wQ)Z>9_4u6_>14Eps8
zDfKj{f29sO@9TZ9LCcW-aWk|G>qqRLLHCH>?G`#m^+B|+8Q1qvLhFHkJ=G~p=!4&e
z$fUkcg~lnpeJga&>RZYn>1bH=28fd(kwQDph7)pl?_!uoPia@f#{n?E&oJ;ZMBEMa
z;UFG{ZTBI$-|!j5C_D|9PuU^rWf<&*=ph52juCnr+BI;|$FMCIGQI}I#~_CdKiviX
zh#{U9mwtxcn-B>!OrJqxkU>DDe8Gkv=(i6sB%DTLs3CbC8jl*14g+w^u$0zu;f626
zKq3w96z@51=&Sj!WZA$tgvmc)c<xJ>k2aJwKuwI{^fF9aoZ($MYIM@D>IoP;WhiH(
zG2URM6DbLX7%p&$h8cRECmH51hru(3vtDRSHW+9bnPP~bs=ZW0C{0&}A@?WDdZwXb
zJ+x#Qv~N?$@T|d|WU>thRsw&{FhO?D8*~wHF~_i+@=_NJ0SWLs*RZD#eR+oNDL9jF
zNI3~oVBpg_qtI}S3dM^IVOg+r(eN)9eZ__?bY`@~u!zE^WrmxV;PxfM1pT0w4FMm*
zQG2;zkb-U%hBr!}=89n`8l9Dfm%M?$YPimWwkktAoea5V2v36fYQrvyyIwc&zJbyj
zLl7;(Zy0V+IasaXufM?68N&2%=B6Q#c3$;{A6G+5gCR}|^Nj|dPe7Usqumf`u^YD0
z>!H=~b`eJ3W)Lh!XS<<|(k2}S@x!pxY4EPW=x-U8)47Y=hHMHJ+%X)dDyJ?(^AvP<
z8&1=^qQ_wV6mIt#5+VWUGpy{#$nF}-uA;Huu!%keaL@1@tpNrM+dhYu`v&`FI`}YT
zD500ku%Xh1&M||SQc&ZD>t!Gh453szKVj&gm&~NWmmbek238PsPa7oL(KllVrWo|B
z!Hb?Hj>g4bVMtEK^;A9QZ2U7C02iZ-Zai1xqi&FNGkQOb#(l;(JJmqA8=s)0qKA>|
zjn4f>%@(-tY3v-qBpfhmXu*5X_`-T{UdEt&01p}KV!?SEooTP+W6Y)MA77(_BIt*W
zkJG#2h;fFNp?=1cIJoU^e5warfN@g;lm!~C^xFp+!_sIm9BlmJB-jw+jw;|ojfOHH
z!i=kp@ZzX(;Umy}%$Q<_NVswNAOI1@IpZKv#zSg&f5O;Dp~h(A;g{ikjInPExL9NK
zJJ1qmd@>Ino-{6{OW>3-<{6leH@-qq&_tvDD6NT48-GefYm(9PTi{cTtN_?eGj7-p
zXVQ(Sl(x(;D#zeOrcv`A3}zYsC`aE};}mW4vyBlh(00zaDia3J8})Q~<QN@9P<FxS
zyb+G(8t?2zU!F1UDEjh^cj?JeU`)m?#qLmOytNCWMaCyT1i5G|D~E|<qYEKQj4S9x
zQfhpcE}=5xavzXO#{b=e<Yl7^U4i9BTLzR?7#UXpxMJLt1lKB!kt@-6)p%<yX06Kj
z%@hFFjPw5ouG;8BlXu;iMVU!^jj@Clr#Fnt+(2rLk+k=(GtRAprJKeaHni0n1H-{J
z7=PFaV52d39fsXx45I6~+2}O~A}vPO5O~pQEa0NA%@{x_&35AxpFyO<7&L_oqSN@>
z3>t44c@(j{ZA4lYw~^g=>=U$h8D(d|b{lv5!P6e&pA<yuHST%~qJ74)wNP`{_+A*s
z)Nd@Im&85e;@4qtz-Su+H)!Nlg1c|bqb1Ccad$qH4IAI+hQA}m-xh$38u#~LfMdq3
zw2PcD*3;phNu#}umIhNshvOjA#wU-##Eh|YF_g|4pI8K?jwXvY8l6l+%E&sKdKbb&
z7gNOxaLv`ki~;9ns-ZJr`%KJl;kLWU)d`XwruQiAxZm^{T^F9FC365cV0yh4fP*Gy
z6;ykfdhA`GhfE3EfbceX{|^WslixMC=xh4H33d;gSoG{ZV)FeBqwq65ppc=zX%1yg
z157{D+a=KSts_hXnGVdwn1W3i^co8>u@*w)sOcD$$V8a#3(y#8+DA*<<ED4hpgPKQ
z=f8i_bHcQa%A=x9%mW}XrXqUy#hQM57hIfaQy)y6G|i`c@+s4%pF!eH_vG+5!E}y}
zAtjnDXW;f}Q}q*YG|8m#0{o2W)hd`sHa#&3$rRHf0Yp+wdfGmwnJOu-n{Im9L`McP
zOqI`|HPe(s&-^SC2bGKtXHBV%u$yi2+5(5qnO>ny<$2T2M);ItDvE-M3#Kh^0GDgZ
zu0Ug+$+!ZI`KF&2ps~P|5CScQCi5lq6`8I|(Rk7H8O5H9O^Ni7FEJfM;fdX$)b!)~
zkSQ}cz6<;%)7E?N;<BlcHihLTrXFLeFgb?;amDls?RhFqpGZNjn&#4Lw90hsZ@6~N
z^!;uCs!jK3`*_{-_!4NTG4;{Sal^FnAnewf9-%|3b*3mPn!joCKL)tH-gJ!4f;5;O
z*@Dhi)73}N*>0MqGkP7S9#8ajn(7Oo^p@$v%TROMwEZD)cTADAD(o^X*J5bhCN7;x
z>@l5J!tQ`cm<)gKn|O5P51H}?02nq!Qvz+wH0A{h<0jD(xc0zq@}~vHgz5NKFh6OM
zIzwj4<bMy`v}rOBeKRJ%&p~EQZ_`8D(d<rB;$)7Xy}z^h;bAnon6G0k;oxe1l}<{y
znKfDPVxM{04G?#88&#utn3Lwh-~DDQZ8kj357EK(17`bclwLk))>65wm-*e_p!<+H
zVGP>5%^6QZw~yJAk49hfYAQ@RY-ZC1am1WLDPTYIt8^OI-+b{GXbCXSP<koQyi5*w
zkXgxriC}Ym4@ijlB^p_%*?SXw3NwF@2zy7(6ZVIIKW6@l)P$Q$1_6vPKmIYeNOSn#
zAji$o-=i_gykHOpPnd7(z(t#jPGL%8%;{7^6l?B(1dVZKl>)j?nio^q_$l+6Eg<pc
zG1@#Qn61BnB%0gbf-|ShS#)bBnLlRR;nW%PE<fOt%^DV3Q_LUJ0x;F=Mip3T=Bo+l
zOE)iDgT4&&>T~GJG_RyAZ<hHT8@xDczLWzl+x$Mg_|BQzw!_i|bEga>*Zlo%^yQf^
z@}VW)JVh1S1?GZ%7=59+(2LfeMP@JBL|-)jy&W>eW`!F@QDSa51({Ow+?UZ<W>!x^
z<dXUHSMcJp`F$&fR&Fk%O8g45XEsb+F`rume=E(lrGQ^G4-;2qRy_%W*UYuFU#&L(
z6bkOT`GeO0s4>6ROC^&x%x;BHQ){*~fYh1uOfY!U9IziU_2%nGp{Bu{T>|rs<^{B7
zYck8Xqp#V#gic7cn4O9t(rOkPA<|}^LywJi^LEO2bePLCV6fBN6AIiNvzZ6iy3Ef~
z0Z6yG=sEP+d(2am&g(UQO4Yu7=E`Vzde_YDfYN^R+_jLoXC9~h(15wV9NeJ!Q7VYK
zZ&rK^$su#~LMR<JKk5$ni21;u=o>W`&}rH+a~OSxXxzN`2}nLLhm)fd=5x7ld(xcq
zJ|w5?W?>SPPMddjz>67k7VUCo&5pDtcC<85Es&F?H4=@^mizQNa<M!bhDKM*x6ebH
zo5d547>9ipUq^W1Zh6QJjUJY;bddd)cfW=uPs<L<5gf2=pm^;;i;pw3cv*_5hT)LK
z{KLCoy)EkoV9>`>zYmstEkP6}IBXF)0&&FBF$&#&mLG=j!}wcvhye_+%pHehkR{p=
z@L<d2`w$7Sd=Tif8!?^E`+y&_6mNuNxaGr>5Q(s~Q(iXG@(j)4am#Ajj7C}flhAm=
zvb+S77j5Z`goPMO&SxO8mbQ3kiL>z35IJet6%IgxWs(g;iI&F#G3wKnua3gOB+ExH
zLgb9aItP8pmRIc;;9831gC8)YRLe(!kV&&N)6+K7@|G`vSr*MvOvzcxwn|8zw-{*`
znPV~0Cnhdfx+(phYw4h`-sD++*$yt>vYKYC!14)2UkfeGXVF(=$(Re=May0RM2aoH
zeFIWriSo5$Fr}79DS}sKx$_1@FIl!x*7UNaq8p^#;!h`yDl8AL#z3!F-pK%0Y5DF0
zNM5y!J_cNsC52w5*DN<J090Fs7_fWYQgIJljivlca5pUOl=-T)T%ZtToh5t+l-;!K
z`<}|6>n%58;YEX`<9(1u%c7m|t;sTR2Bg`ti}ocgmdB{bqt)^_)hf1G7AQd4Exz=*
znhuMRl8~Ji#djdLEQ((NxNZ6BYryYV#%9sjWyzxAxo%54y|8*Lwq<DSwLFiaF1tgY
zWy3dM?^@2qz^Q&q%frCmv;0ZB*8xkr6lBn{iykTWEioTq*h7{jOCULH32?z&j93=#
z0esZ*(ME`jS@fG>cii%j1-J*6`DTbrSo}6)WRn)lI`mCh=18Dr+R_sb&OT$wr%l$Z
zWe-(LI9eBWLYs^A&&vS1TC1t*z|HDM5r}=(H5N#^TXV$VJgk0g@M6F9TT0A$S~o{x
zE)G~<pw-|(D?b&Sm-YHe_;kqHJOa+!>P!WyKGv@Xp~ctwFV&45wp%w+TKS0eNBR#*
ze%79s@T>V-ea9gaVC|(fUZC~4=V2nq`XnV9gRM;mz=c?!q<BxLwSF%e!>pN)0(aD!
zL2I>R)>(R0gj+wCK_tRjL7CJ@t86nwj$0q4+My`x0<5VWPFU?#bXP@N-=#Xp7;6(9
zfQz+`rU4jdWj+Anq;=cB=u5En`vH+?{rD@)>}l&xitZ&@w^EMnjMd2pBFWa?1sGw9
zH7^Kmr&`;Kz@=HIpNGK=>w|yMm}y<{J6y}MKEna-taYVb2!q*H(@o&dTaV8Ikz?I^
z7KjVh@<N!;wZ5|feR<ZMX8_E%{zOryB5Nbn4qdc9brwpCtv^v_vc#(K0#|Ci^(g>l
z)+hhFo2=PO;r3<gc}mEZTXQyJWEEC7+7Vx|=D%Tw!Ak45^hmmD9i#i8%Br1#iEGxC
z9Z*wk)mH#<-C9-*e2w)PlDuIZe-W<LS{0O;tg~*U+S{AftSNX{Z(XzoA`Mm!3w@1N
z?pY{nvffpoui5&~3fOJ2?jMKFR%_pOy8qg&Ndm}pSeHHoHJ#Sy{sp;XeK`X7F6$LK
z%inEHpxtYawUsuiz1Hg#hU~M}Qoix7b^l^;{nqCjfxBm&m<1WIzIYT~3|fm0!|nUl
z51XKD#JVvPeWTVvI)*T2&BT3+fBb6Qyaf0MR!<t*gf;qC{4$eP`34xAvfiQ$|Fkt|
zHGnhL;9ubAtaU!+SsZQuYXfn%IX?{#U2L6~0C2TMPe8=Yma_wZeYU{AV9DK9;|&Ww
zwsi^+U)xHmb31I?L7y+PAF+LK8V3DrmK>P(w>8a!(jZ$KrDB6^o9_T0Vl(ZA?oeCf
z2>QZo8?2B#YICK`<T2Yo3Y3Q1l<UzLVSC{=CMeSOBfb2O+r~P<McE3e1owpPVakO>
z+XA}K7-RdBQZZ-jwi-&<C)-rBn9Ee#=4K2g%_fM3?sQuz<@+;inXiJ&w5@s!B+K^2
zyU=~s=JPC+X4`(agHfEbt)aNsd7Hx@5XrGc6~UPcHU}O=a&65N-OIDBeF2jBwnmD@
z7TEUum%Xsr*U&bj$QDCKD=ymNY4K5P+x;`tl-PnPAYN)KpzL&+?Q9bIF4^|G0e{)1
zh(TYu?L$Y{t+2VygYGM~a!Tk{+VUpRc-5AD3p%T8>E!4&+u#&Ls%=WDq`hu?xD<Ug
zwzc+U@a=}}aq_0t_5!5?>M%ky-n6AqQA)k7Xb7SWwmY;>Znhn#<y?zxc?}v{ZINFC
z&}PdB!5p^RUOoWVI&5p61?jY{JCDX&Hv3+9f7@pN2aR`ZBQBVkF56MsQFq%uOQ#@x
zk8LY`Jg3)|)rHnR+fP(SdDpg11%v&zu9Gl$&o(m-O9Qr+N^pa=%2(jpeOuKlxH^Yy
zgU)Ciws|)JK4LRj;r*y>nIp)Ut?)PWjoW_zKS$Rcmv#01wKOwJ%e2h&tEQD{X=&3e
z%`CHQ`0Ty+erRdy0YyO>vWM)g3`Im_iA(`;AcBLT0wT%=K@bpr@ALcXyzaf{ywAD!
z`F!p;=iJY;6jnUmxql7>Mt3f$Mt8?{j?bhtu<@P4`=S2H&X%XqII)vShla_W!9PRL
znGs7_cP@;Jo+#~M4E+g~y^PQQgeF(UyX5TN$B0Ba$@Kk<>04o;8)JJ2Di1Q&UO^{3
z7%6vPg(u^H2y$MG>6EnY%^0Ss{}5v~g1wIEK8z>PQ0U9}a0Q4TqizZ${24+CBmx+-
z)}S(wk=72uAjYCys0?Q89|H+tWKt?aDC09GI&+vIJ&npR#tcdd3uiRbZy&*6P>M<<
z<NTZ8jAAULNMAJLv>ygGhLQFUtZ>9KUVIY<$1xsL21q>PgAPa}Fhup}QzD}&6MB;v
zDFO`l5ynQ^?;d3okWVO?afc%2DGcd*s7z&ib{(ZOh8KNu=osUz*P!A!qbUy1>5T2g
zP=A7<pjcG~BahOAPBO}9gOKT9M4Sda#b`%>XL=UnADW>~GuEvDS~g=-D=Kpsf73A`
zm!a;3d>-RrIZFAAECWnC!&pZF_X5Ux`q9raz9QddA;XP<At_>fvI7Fej4$RveF@_u
z+V7S!@@Q==V;CkOevaXY;DMGiLfybq!D!xzQYFJD4y@-Hkw<`5#W+Vd^Di(K)8(s+
zj8ACyT+P@+uD7d<Xa9nVT1NeBSW(A#heANt7^go1*mZ_99^-U_v5dmIHyKGPpwu%;
z@1xYfXtY5?BjY~@os*jwA9rIAZ!vtj!E>9jkS3Em3<q6QY-UWM?`5<wdJclKmElI7
z(z^`R479Z|gkqrGV=SVPZD%Z82rKS0(rCZ@fbk*i{5lv(<S*@H#7zO|Vk{1Yh24yQ
z>3(Dn<NG|?y!SF@(+kwcSn?S(^)nh@0?z;=j?V5687(yJ3^InULemiA+X|E(F(%1r
zJ<Q0y1JDu1OXPxn%s90WZKDk5Nq~(peklaYI72lDC{Gw&C($;+*x3MqNyf8uBz0!4
z?5EG*x-hHm!|pvy6*;u`F}IMXbU!nEF^C&;u^1BW%<Z*kJHVVI=i)(T_C{2CF{kx`
z#hY16uEs;mclyxg$J{`Vyg#$%Wt0M#JA@d~K<4aZa0W4_K0#YB^S_g5JItJCp#5hU
z^ZTdJ7|v{J1ZV`4Nq)#k=KUW*qL?2q0CqI<Fr6=An8$tuXDo9UP3UpV^7nui&y4v0
zOkCz0m%)<AT=fN5l9&riQ98oB%mvC(W-2A*CNmd)hi<1ZpQdnSD)aCnjFTgcxuF+B
zbByUm@7QsslH51x%*|~monV%|3bYL7j=w-oGT%&tU?y|l8jw@W&z9gR%VI9hgQnBW
zuV@v`W_poFDu<cN0!uD4jCO8$%zfk}&u6|%+x0U{S6VO&nCzEOdDg*PbRQCh%$eOF
zMa=gPgA_BnzX2&>W-Wo<QszRM(#n{lL8v^(Ou7Wq%9&xEsH|XSlWVn-`8KU5=b1~s
z0jXk6(A;@}$?Jpqi_Be=vvi61BE1fmnQr9kt7gt@2f4y@ETKG~8m1u;jaQjJ+n}PB
zxrjDBb<AnG=-M^rKqM-!Ge^3>a)WvG8rp6$=dZ_D)-&IsC$NF3se!^qrhwl2CZ^08
zX5V2xlK~aY%p3{|v@mPwqhzhj>{kGGmpPy2z&7SoM;+wvF&{mH!Dwd=^g!Z1b7&o4
z9x&Hd1Ez!d2jv=fGM&tj=wb#e0$Mk-m=aujm?4Qk>t%jI4(&c>3T3hNGfmrJ%mDM|
z8IXre6Xod)GKJ)%8)82B9W0NSG78ZRGoN1OfZzyoRyw-&n3+Lo?xW0`JD_lk>DdFp
zab_W9UOi!2@UTvwV5+^)HpyH#1)R>T%hO?#3oG_n*t>^SNa3`-tYJEkxU#xwEcUT{
zJD_(z>j@8FZmc^k0CQ)Zp$F*zYxOGHe;#CIpFpDrD}D(YJy{)B0prCwOCB+A)^l-C
zafp@t6j*#%r?0|ZU)F^Pl>Ar^7C@6ftB;&d0W3DTzyetjqo@pGm6d=qm^DHvxFM`X
zau^fJ`kGD)hgomX3=zgUh&xG+>EWzIT2v!g^WTQTNY>Ogl%iNI8(~Z|YfC;VV^}H%
zNG$8ZVZg+(TqyjP$Vw%5MiMKDj`BxX-gE{?VeL4Iwp7;Z(?QZ$3uz8aXU&|3(g{{7
z`3y2x8_5-XlJys5#5yurFVU2CigoHDirK85UJOkR>t{AfxvXu^Lt!4PhtezZS)WjV
z<_zms+5i@?o=`T*S(f<#unSo^G`|+HHgAV9#jLYi(fbnCGqh<bW&ODqq>SZF=iGCw
zr^y>x&RR=;-U<gRf|6e=S+nWsKF|8C5b{;5ujmoFz(SA#FA(cTieg-1Eui)OGAs2P
zv{kcC&{vqQuwJc)-Wpc#bFktnD^(AcT2}H^wAHcRA{W{<)-UAKxz75~j<y@Dq(`W{
z$r97?q@LwCUWdj8mW?cJWHl5(u!*%ripE>4x2zzyS>5zp-C+gAqpg+Yh=cieS$0|*
z+gR<(0D6yQSpn<YS^6+of1i~=r=tg~-CVSFuojX}w3GD}U3~3g4b$1Zo27CE>0uch
zlMw7>jctcSAM0@?Z0l#a2SM)utDJ7yK4jIAhjx&qqO<T2YcaJwV!cjJ=P>K!E`W}(
zri&r|m{l1F&QVq!W#EsoD)oRKXFW@Yh9|7Lp8!3<3VjJ?yRZvez`2Lrd!6>5d)YfE
ziEcl8vK<|DW2e&fPIvaI7)Tso2fq*OgY0w)-+Qp7!%*+ZPN0pA7rUB1S>nxp=LL{M
z>=y@7>BFv~^~;z2=Znzm$4<55XZC0N)9r}>_LY@T6v*b+f-{J{$DLvt!R*0ZXbfRL
zNJDKXJB0^wm~HQX!U*=SKSF&Z+v)|-DE3B5Q;KGPL1(lW_GulkW7$*Yprdi@?R*Ht
zvuo%|ZvvY`?wdsRl;!AP5_`sV7;}UjOlc@b**o7wWitEom300~VXp`TOe&ib1D-VY
z+%@1i#!jQCz;SjjrM;!IKiC2bPq0JDx0AtsnQl9uWcyKsBa<EL43<;uK3Zb4*dyeK
zIL&^Bj)B?iui{Xd!!EHxJeOTS{`5Syn+9_E?C5Dw>o~)H90HyK_Wv4S@LBc<oeT=u
z7s$U{#9r--%3}7jG;fr!ryBuN%3kvb9W7%=oCN1N_LlFUshoYG2&D@4cjp0C$=-bj
z*yq{*{e-rQ?4#sEu4cb|7MNGqX1Y37!<NtraMi)yu7O}J`;To<QODk6L+v$oJdM|N
zcKvIpyurTO1-oyuW4=aPBRh-UxF&WSr5W8~&$tB8+w3nFqw)^>8FFAWvzMiVvxWW9
zPO!AHH&DdvF8kszewa3Pm?xm`v**x<y&tf*P4|Fc2m9y_NOZH~*Man~KlX>gz3fSv
zS_arNKZlBk?5c$zgY4E#U>Rm_rmNE<?DW}ydCaZ~E;<NjYOV>`E}Tjp<o0l0@`U=m
zoa$D3xH*g)7(6%5jlCEWch1N3>0}Si6gvERa(3PWrx)jsS<v9a*-RH3eL1t~V<CQ=
zC1Yp{<d|LuXAnpI3ZR2IPt){znDe(4ZDE{O1^^b$33PaXMsaEjP#ev;L=Q_0r{V{&
z#&Z%FC?#-4rb2xpM??<Oqny1rQA*}a%0N;$1C(rgjI(wERvhO{_`~dU&i4mVI>{0L
z4x2JL`AdOvic|A81hP5*(dPkjINJBYlFOMfKs)<09P$4jzB%$#pq=IT#=@9l&SWM^
zC7b|C{3_*qMti(+j{7$-t%8#s0hmh8atd-?;OwG||2obvt!CFa2AbBdbDnpl2Z6JR
zPOmpPPsmN&$mykT(>8ImFM;J2XU`#8OmB0FC>C;u<3o4znmPYcDr^hqbAOOljtA`;
z?s5`xAm7Hx_y_9mahC2!shu;t0SX^*4$)UBJ2*vFaCUOmZ-(A3&WIB*yE)Nb=yors
z<z;lDkJHD7-hPgMF`x%Ht8vhDOn=CUrzFKe&eWw49Om3rf{bwd1_An*)8PvFan45i
zBI6TIyaEa*IM-+!>CFA67IH4!hvY%n!@Z$}z+SG2B0;WPHwqN)=ho7FAvdm#R(5x8
z3w7`Sw~oLLaw9gQFAfjxTT@W<<o+81gT1(4u7JEZw~P`X4{=`$0`cK~^C7J8<<@=(
z7C-K9pF@*B_a+~50o=e@s0`%JxeL>RxS9;;4d%YC0tw+>qWESgw|xQH4s*L*!5P67
zP+n{#_r+^aALZbFP4SLcu9_UKaoi(wAsEk{_ZBQo;{NjuG#%lV9ESW+?rJ;GQn{0K
z*(;6fNsiiM-0dF&<^<Pe8_dq&#>D~UB=-jjqh)d9ZbR-gw|xsxvbl$8y2;~aXQM5j
z`*t)0&Tt*^SHM%q4WksMBCcR3j49?C>8fcN*FgTfbKDncJ}>9as|IHUcUK*(sN^Ql
z@$o!&wHd}#aZ@coyTIKz0P8Pu2cn_r64!$gMK5!|+XAp^u9yugYPg%}41ASqrtdz~
za`g^MdZ^>ho(*!1TS|V@>)hWp5WK-1+z-}z?zt#f(ZH2F1^Gtqs{&Zj#7(Do$t~`i
zRgk;QtsFqx9qwxspls&GZh|o_+z+zQ(N=C0O%!*z<x!|?<BGgM?sGp`4Dx`xg6n{a
z4sH}(mhR?$Mf>F*?rlnX@8$k9jLJT4r3~2pT#vUw2Dq<MLefKS;agxC<o1lhiXpDc
zc2qv%{`o2dhPnTepLm43bT`Oj?g(WGj&gS!Q5xfZF%5dhxtvLmCtOAfEv6IPEql<5
zNv`)ASnACCSB74=@QyTt?BNa31htpfOyMwB-qUxWcOMVuCp_J}92zw@-l;i2bLR!q
zY3=~;Ejh?R-j`dz>A`!Gu8w)~GM!+B7w^k2!RgIo(K2?3Hy6_toH@MK3$V?XxBNvA
zKi;mp0QKk1zXhHE-U`Z_4&>c^4<v~9&k?``^Li*pGK9C00wtlmW3OTm4)azXhu$#W
zpXA*O=Y94&1R{8&6pxDJZKDW#6mNpw+i0F2-Rh3vy+#`-M=bBf-vJuOE2gt-JddA&
zQUb4tp4mj+SM+VpB;Kqyq2dT{8BJS9c~L*&hfU_aB7(vco}5lFsl2(jQJKcuu^!mR
zc(rtC@;I-Na{khJU(m{ag17Snpk(k)4MN}~ZwH;RG9A2!wB(%TwbJU6&2#(>lEXWe
z1ejdjG8d@N;}ufGEuZ%>8G43y>KR}c@NUs?o#lN?FJ2*U$2kZT@w`c(nD;Ojm?gZ4
zZ77xUex44NGTw8!Ksm>Y?1OkY&xg{QDtNER$O}}-3!MVA^Srzz5Uk?87Tn~E|7+(-
zP+853rCZWhc-`a-s^LBIgQlxI;ZNvAEpIEGvFdnya%ElPh0$5|I&XyHB{z8GUxD1@
zIcP}gdEc)DSOYJf{P>ML@84iW6Yo6=%-rF9?F5!)Uckp-Y2p182D4jv5e~|2xyySa
z3M$%o<};|h$E*7Q^6k9+<bk`-W4?g42fTZGz}dlzi$rB7Z_`>-cJY+-VW@7N2VGd`
z;iZx*s+T9ESV|vnfI@@)yxAV$9N-NxVfI6whN7N>JOkx`5Ao*v(<JnW_tZW}4D;-5
zFmZ(UEL{wF%qyfg=_pVC9mp8(S2IR-oR`gm;1k~EF9ABio3<Qel6Np2EYAEJ-$J1a
zzas!P?csk%Kkr_??H35R@-NZOU?1Q4V?gic8{5zcH~yU(`rd>)e;zqw5AYBB!^DI9
z?P|z-@WZPh@5!&qgM=5~ITV__`KvkrbBOP<8I?Z#Q@^0UzWfCgc=qFO><5cK|HsYf
zQUL$26JQDCKX@OQL40SrlMu}Br=x5Le`XpC4dthOHU;nIVg3mTObp{|BEb{R@AH6)
z2>y9WQ;6iZQgAMce|k5DEt=n(48a)w%M|a3<tulh6vuy`W~O-l${8RD{K!L4k;reM
zoU$bT?Kwb6=Cde)DuwS&si>*^<=!yuIG_6*dhJN(r>=#;C-_f~fMoNtlE9P4pS27y
z`Fu77QO@wig&+m|ugK|qmY+jyh5S{k0b0cWANhxi`5WmTX$k+uD*!FyS6o8r96#?o
zEG*}HAA@)W|Lzo2R`NLyFkI*Pos{By!NGr#=GTjSxV*8R@P!wk{xUzEu7XtaWyfIt
z75-&2NDY4##VxM#7gB(~mOqtFCw2T^=zAd7_;cJKaGn1$#kg<q54{P6H~ES40anj<
z970<IKYk}PH1hAChxJYT&nR8{7T@vC5Q?|?^Jr&qhwpb3pw0ZUOqkfhKTJPtD}OEd
zfba4r=vQmw|3<r{d;FojD7EwN#z5{qKg}DQ5BN|0gi;s(I|`F_^Y0x2XAl2kJxDL#
zBN3+c@!QF-+|S=a8_ofKw}TwZ5BY5J@elI7$Z0mjf36ypkND4UATi8WJrA2k_?>G}
zddzpHeEd<qb{z!9_&IcgY@8oW$=^@-S%;u$f?wbcGReQrMw_$X=kK9#uON+L8LonB
zI_TXec=#0r_6we#?LecOAo)I2xC`#kx_v+}Ky%qaK^f({c?d?{fhJFZKgCPD1cxcu
z<SjV50dj`~HNQiXkDzn_0=|MXuR+{TFgyl1f5C_dBtRgf2w|Wg!UmQg!3uggf(2D7
z$b|@|Y@k3#sNj7%f*cmS5ChOK0h8QZ;R3D)G(`v+$R8gq_$&-|#|UC*t%wy|YX@3_
z;JsZSiGswhp(07}+bIlQvY;y&EGdH5<&aAiRNe>lae?FpD$@nFe3VWIzK=kcG6l;I
zk)!pL;O7(!ca~t~V<^lPY?%d3If6IlKt5OC^D|WB2~N<7AYafzPhf$dZ5i6m3JQ*+
zR4Dj`Qc{ZrJIH@hBKYlHSWzk{Bu`kGAdm80&Iw}a*QyXm>rko`sEx4qykKu6)CPA2
zPo3#dBaLtRB|%#&$YsIwUjSGwxK1&@8bQz?*scl|P^__5(A5Z}I>B2M622z5zYYS|
z1^;bDWxe1NN>*tQ^w9L%D0r6+R!xFP(s@g;h7KyX1#9ToaYyidK7N~K!P5EYT#MkE
zgEl1{g7_C8(J6TP5=fUIjN${`g3A<m=@Dq?z}+WU_8d&>7Z?|zG$8ncF8d4$s_4T&
z!-8QKw2cT#Xa#;OxI%8^QNj5$Xd4rJh(v(t;{sg@41FTF`V`bp2ufDN-bum6jSkd0
z3)ij!aS<-0%MN>lFR@YDFU+I$$xS%<6)N3@Z_^WUK-hrO{PcrDr4L{{giaKk^c2SS
zL$8<6n|$Hk!YQe+-e36C5|9AlKd+&qfx`6@01FZ(QWQ2=xcU|_LxkokS_DFct#n{H
zENuG&Bux0~4!}eU+fG77jBwRQAhE*wv(OtS)X=soUdXrv>;$2dUYbPVL?cur3G-AS
zM}&`?(X}+8mLev{gx^qv=(zCI94Jf|hHZlS6T<tn5zP>e9;O>aCxy=C5X=-Z+5mb=
zm^BRwv+)6VVCM)=%mv96{+NZfJmIvD0h2GhycRHLgt6bFvOwtR4wkdRtOO`56#jGv
zU`4{?Yk^WMOkRSv5~0^4R8|P1$nje#yv&36dEs*@FwIdVT=^XOdqMar9k4D6FVd`Z
zNw|_S4lWD-nhDTq;c2*ar`HLED}i=Rc=0MKuM0J_-Mb-lJdOU|6vk7`pk8>H(i|Iv
zc8WDN3hz`vMU!wU#lTvGwR9qD75-iZu)D&~>83}ULnylldQYhO8KhnKE+xR-7Y;~3
z9tevlFy0}YCxD7x;WjBM`-DBe0=r+hH6EG<gku!zcqp_zg4u&Y9&KcYgti^vd?YM=
z6J%I;i@sMiD!e)qr7_{NX|QQrIOSUiJP|sE=<GKkTuE-QNg<13XwISq<cf3=eM@%?
z_lV}s1<PL1t0G{#iq`%EvQNaIJe-4~r{YlZ5Pi`M>pexC>%r+Ix*mi!Z;_}E3J-}&
zD7nW+6zT_ieMNb<Fcy9y+Xm<h7Iiw(As8b1AqA|VqOe4u9Tv?FheVi2MTywqB5wn1
ziV%ru;~yy!{sI+IBI%dtMZ9Qp69f`O4fN<Gie4k{Ly~AaWt$ukMcsk;QPD~jNV4c;
z6Hrn_RT7X?k*p11Cqx+r2h7M2ttW@qNs)IiYBNQ*7r~fQq7UhxAF@Q>lY`>4XsZw~
z*`iGcft@4TkO77HBI9w0pAntuLa9KM`5W5KivH|^K%wZjXoweys@!2{vFJ6rY*!+h
zu^gmSw5tdj%0!hb=}$+_i4KwbtXy<)2gn6cvl%cKMd6Krxg`4g0tV=^s9Fw9)uIJe
z&~!!QPr=+8k&^@}u8LOV0rZAwh}OQFqUYSeQZM?z29ySoj~twhqJuvItV#67Alhz;
z{-d4QZPEFq&*J^NE1IMTQ=2I4Pt@KM#U;>#DEgdkNZ%LD%mnBI(Ung@Iz%%|Am1rE
z^gT$Q=+6xNl>MTo==Su0$bT5*p{VpNXc`p#%7NY?(b2uI;*lth_7B6N8JB@FD%wa+
zo-xt3wIGgh(GQef_C)js`RgV`(cfSYCPf)^N^}!H>kbv};=M;9e?WYUA^``*{NF)5
z#P0Qw_Y{Zd!Qv$zqD8`6{9*$*4~bplpvgz<dL1QS@pF{l<tM&HE+2of<s?iC5XX|o
zH_#!T83~wR@qdQ_8X`9R1DH_p9rEfP7Pry4KTK?)M?OOQ6-~2|;xtO3j1u=h2hJEV
zI}b3i;*AP`#);>XS2kY!)jn`0h*v%bazy;(H9#K~7j&X6S$v#U{1owzMqs9j9k08h
zHcf1&ZQC*N?YlrbF8<g8!F2H@n!+>0*J!(VQmptBBvZVdG6znHC!#>I#L25bPK$T-
zpc6S_3neY*if541F;BdUQW^8bZ)pL2Mx3?<gHRyeyBWiLR@`zCHWiBJIw*EmB<9m5
zu2>xKHwM2%JcoAPrQ+2`AYUe~rsw&b_-Q%<mWxZPAXp(@P9D@s@w;@KJuf~>&i5*D
z!X2<&5Z}lI%SCb7T3CNcobwr=FN?>>d0s8n)6aBOY^;HXT5<664)D~8SCI$ln%GEL
z!`H>mchPu5yzB+^qF&rb8^Z>%?jAbYDE{m*NRwFmIuza#A9x$&ws^G#pv~egSBSTW
z``!Xet2n3`r8aS-55Vq;4^gzOU2KVgG55t8t$=<Y{wa+<df6d<#s|IV6mMP!o^G)(
zWfb>_f4qs#^osBKLVcgOi{_1faq(`jJQVw$0?eTJ=T|_6#1X+@c_e=OWhfjLN78RU
zBEB*YgD@s`T>`mr@ehAO?ul4+5oAK#PN$bi@jN(y9Mhd8PHRwfk$mq4OZP}}_d{Z@
zB#3;(u97!s#oH&zIE=RalCes(xk&=(3pwr*ZyNjql8?!2cu-PF{!|Z%E3LGil7KHT
zGG3BUy4UJ0k&t)ikc9UwFnuI5LSVM9B<@2Hho5Ad5-|RfSO0*)0g{?#s0fs-`VK0B
zBp*ZrG+46of2a(R<j4UNDjDbn_F+kBK1i4(`Dt*5OT5Vu6d`eJ0Ev{$_kdiKWVISB
z(URpKVn|{n6W-7eD@mkCT%5$2R;74{q}+&Ng2ZDREKQU=MXu%~$$q*Enk)%?8S*KT
zHFR7{mBg}uohGUF1oknB3mtNgOFo?q&UDG`@6eeOk_F_S&ycv#?(U@IqcO;3N=knK
z=P5~2C)%<kwG{h4E$JffdA7tMSP8To$u={FEmv}(6=-=9)~686m)vg!%o#}s2W<tC
z3L6B^N~X|psZer^E?gB!Hqz0gSTb)aSV|<ENsv+rm)s6zlC2>qos&dTf=9XJjje#L
zkjz>LD=H<=QSR4yNxFlk(ke;s0u(Pu=BxtGMM?Q`sIQiEuK~FtSwmZy8p+Eu!E#md
z{R<$ql3m-tStp4v1i2<TMjzt5F8Qkknr=v(C~|RA;yDQ`>LvLv;zw(cgdaj%qeMj6
z6HSt(6c)TCdFHkQCf=4@pnStS5*@9(&5~ssA>Sg||0^U~B@Fs~?n)X%p`uOFwi}iA
zBxzH@*)Dl18*Lqu>Qg9nN-k42Y?mZ#C0M#8X@3K=NAi3;H1$dTq13T{$@`R$IUxCq
zF5NtoG(V<nlR-(_Jzx(>Hhlz`VadUVkROo@O@ZKJiQzs5VN{|e@57j+%!tZy$>XJ9
znUL(HSk$ECBDs;Br5zN$-6Nf|6E^LYuKyAxSE=XcklQDn9SF|-Qa}3N3U}$*B9H^p
zx}2F)rcFO6{U=x!k5J8`V~{u`6$#J_AL)$upu$%wdI6Pw(#&yG`b(do2P#0?&&Q7z
zBrPE)QLwa+Vs9bRCfcNhOTVKid4%-yO{k2NZjFaAQPK&zVHqurrK=LL(t*q9eVlaf
zZ9vCMbI$=RLF((EEmWfP0VTpENlTp|e?<BPEl0`Ho|C9dk$#f{m{h6H5aiROD@O6#
z9g|jvK|Wo&_<4w*klq@DT!!={x;Fi!)bKL|GNmjT2H}+SlUT@QN$+ieT#hu7PRzN|
z`9H(#JZbZ7auw%G)o(%YjC4;eN@t~uH={F!(s{3g6iG$&ixx|7FNMMq>C@AIT`Ij?
zfVOkegY<5eOWE|^R!9d<qEspU<$WkTFU@!j3ah05=plYlnn&-!C8-bP;$N1g(X4Yt
z`tL^+s;QB7kHXTc(tvyDcCGYxa$D3%1(cX_U24byxgmAF544-ommYxBOKa)G*C73#
z2EP%%J&d^}wO;}DZ7Iu$wmZ`8<nd~jzD{#*i&ROeW3AE$6c%ig_E9|Ip7hk4bR2G%
zMvxb-Q~JY32zE)e0}$+%Hqi#MM|$pANc2iSCHGFhbYCve2BgjNP<klM=7J1LWB!9p
zL(-K_C_R$8(q3&?DkWFsV`;~7baYhu_j@pHO#1yBAmh?pN+f$Cy>SErj!CJ{Iw*9O
z#omC4F0w!*15e*0``|T{_R6LQqW7+{%wJ&PKG{zcAa<86TMvZ?WM2k=<)G|E+F5wW
z65j{$l%>)k*h_Z48&-JB=57W#BrBSYPWZ^oX=wA6HIlQ%PnJhhp}#}cbPL!4vVu~u
z2FhM^K`BU9Q3>0EWhW@_Hbl0#6?#KuCQ30nEGw^r`Y_q6uR~$DY?S<05wb;;`xPmB
zc@b1Z$zDT5dwR6&<{q@g$lm`OZLzYYw9v-MGAIcuUY33t&<Qd}A?>*mWkqFRO_H5^
z1uBlnj!GeMRCa1PEKQb0zX$VEWYg%jcd9IdUidUw@&S~N$wDoFIWC)9iO!_UUhjb1
z3E9vV2xQ1^{RPaEvOS-IGgEeyTvexKh5(3X%eL+SXO7I(LGO0HER3QfXJotSH!P5e
zDMg}4wzC3bQ7o&VbgL3sI_;v*$=YZeS}wat=iLgKA^`$bG8el4aY6Q&E<9e8y-i!(
zYT0UvAzzWHln}3xsZL>J>SUkLS?8L}LaWMk*_17mcT_L4?*mVR>@0n;rcw5Y2I{sf
z=s4u>$R3j`rCFvS|5=NSMaloIviPS#?#e!=ZC#tJgwC?}WS(!JYwfa-a-iIoSv$e<
zK=yYwSUP1#l3;I_?CbYY>Xv;#j<z0ImxN~GUYV6viGJBZJp>12ifPdFP_~+${6X1H
zIs**JzVC!Fk7Vgev<=IC+YYo5S=3fkK9(&ax6r8U{I5_rCL6hg5gnKL(6jzTc9lXk
z6S4)Dz&R<qZbqB4y!uzDcae90M0vM+<UcfmXP^9xKNRkle?q5UH~HMFP~k2wehBOX
za+Ma92j$D`;PjBck7&hoPr1|YK=YP=OWU$T@)+7|`N+$7(BvzBVFud#<R|GZ_Ltw7
z2bKVN^(Bx%c@e$uA@a#qv^hfMBHF_omh)~vB0~NtEkKd-Ra?=SDER`)H;k756pXeQ
zc{)8MadMAwsE?O-(BV5lUO`_rNR+31j<zKEG+Nn@$m63>Ix2r=9fm7eK84)KDe|i{
zgQv=yX=XYlXVWa5<&bNf(Rf<EQiR%Uc`Stja^w|X1149#iIR`=<e_t5VZQv10hMRu
z6Vp&Ckbgi&m$ULOg&>9U-Jw7!l3)K2q*yLQM%VNb`6o2nmdZC#;(3|;wF6LpPF^kq
zOSyc-e8^SE9skfVuu{%whc)NrUEvU{l27e{iVN~f{gAjQZ`+B=OY%a>G`cMRG7g;8
z^4uC!UXg!X0?r!wUzE*PCqGYT=xg%&NEmuuUj7i3^>QxFB@Oa$ZwNHXkCvdaNnS$X
zxm)s29p@o`TfTWJG_}azrR1wtIghd}@5)tOAZ_x1A+X+)Ux|i%yL>l|#eI1ItwRsw
zhs!}a<c#;Bw^RP}7L>Z=n*yP}TkifTe!Cv|kx7(#<zu&j(kH+B133HTVdTmhkgtiM
z!_q^!bvN`5%I9W+XGq>&17jY^$0==bSZ<-X;)pzwcJ`0uuTx}sRQ?IwmK&4X<-i`7
z%PB7SM1Fo8!#yD%Uxgk{%J)z{i?bqH32_&Nq8euJQLHeaZLi`u4T-CwyPn>^eTtd%
zs_j>Nbpd+a6mdVm3U|c>y<7(rv7bTjLB+4Ppu$7(tT!q>70=b7(o5k<I~s3AGo3bk
z70;9Z*iVs0-$3wJ+$UF7fZ`Tqx(6z*QG7f|@sSSD!HQyvXoo0X-cO;@P{mWfqIg(g
zBxhlm;)Mtp9IgnWRIUichNEbURD3`gdr^vZ9!k-Q%dxOGMzNI^>R836lui(*_^A>q
z;uXI~LScf!xCEM#6mO6p<cOk@=KQ0Ioz-ATR_yu*aw&>QE5^`~rdUWZ@MDUCQb-(E
z{79D*GZg<(X30rKDa~b>ipc=TpHirHp_HXinxOEsqSy~ZnyvVj&LuetUo}8;6-DKc
z%TqW>Ads&(Cj;jhMHJ;(6)0A{0M4_D&JUokP*L3g^+gVaXEbVy6<+kwh7!fxdnlDE
z=7yt(WeQFqj5()>*b7pwsHA1TLNT3AUX_Y}PJ#2hBGd%VDg{3Q##~U0oC3>5#jFab
zxTN^a4|*>vo~2V&wW5U12Uir<W(d?M*3bs~s=~4423TtqH|XM3oubkYr5lP6^0C}h
ztoeU8w_;R=t~DtBEJ9_Y;*XOcO^ScW&2~$XMxScCt$1q{D(@&JbD*hN5&9ScEs7}G
z7u{7{dj>sgQ<P6a;GSYI0c|~s!LuN}iX#q+RP`xdH$c8$@iyJ298i?ahlvjr|0aTG
zP|-&Iu^~lXDbOA%u73$Kte8vF<YUF}bbD=7G0uYCF~yvG7&ERo%SGiA#i|liPAFb~
z9?+AD21@I6Q8vE=WA-R7#)5ONk~5V~BKwsu(B&OB<^Fd8>aO%{Lg|2V?~5oMRKCOk
z@laMaz%)<gnm1AMQU=k(;;rP-PjN{3JvqdEm7ae9)KB?k99aC7H?N`-0m?rqKo+RH
zmI1v%%GlFD308ja4m5-+w<gj4^RUv3p5QR$gJuYZE5~T9iBMLPFDpv9pPZu6%B4k+
zk5z7>jaZzrn>J$c%0fy^PErPKhWHWX_zK7!Rc4TPB13tAu3DW`b}WNjrZRF4tT?4q
z(n^`7{OknGKCL{BdDSsJS2;{qx$~6E$p@CN{A?CXJfrN`1l9uO&lE;FtK=%6w@~@t
zw@_H53?-*^v2u_uqm(HB`3VB0$}gIrw@f+nMF^BDpS%Ep3gw>Xz*(t$mps|$m44*q
zu2TLN3(iZ*RRgfeaap;7mcwf0(qkxIQU3l0tf*0bLzzlfm4$a8QL7xKcuAdd{#OvZ
zrgWn%&~;^lD=Kd&<+b3vsf<j<Ak-^myFeP0?X(qXR1V*Qg-yzZRgk--ys{SLwvt1K
zl{?C+XtXsulx=UK*rL3g1Wm0<DeV>SD#PzWzD?;z5#oEwb#$g}S9-nz?EA_EO%Qyb
z+)Qm9%Gz<Xbt*^6%h#n0t3+SAm1*?)_9)l3p|V%$c><(Q8APtEe&yLBpbRMAqv-EL
zrK6WzCWFeAOQC*9`CT_kkCgmkG!83sC_QaNd2j(LA1j|7g2GYd&tjmBDV?=YF|J%c
z2Xar8o(I4(q5O}I36sjD<Slbnd1Rw)kE)9NHv3ek=uo#`b&WO_ZmN88ySl5=9X~?w
zfU3+HjR#fpr=!tB)pP|Co~l1CV-UPlOX<n?R^|N(V-Bh2(dTG<RNpwE%~v&xzRu*Q
zdPs|mziP)ql)_ZIE1)-ARayt=2vzh}v_+~)(@`0vT9F0lXw?_rLtl)_`nv-Xv8sxv
z(3v>ZcmqoDs@-ovFhO;i0<Vdx<MjF`sp=`g>xk+D$^$y8axfr}tnwolc#7&bav-Lv
zDo>y-O(l1Rg~wEducCBZ<#7g_>8f|=HslG_H&O^>sHSW{<w@1&KJ@-&svi9d6Hlp1
z%0aSJtZvAkRw@62G1;m^@1T^UdX8M3xvHiAfhA9sZv%F|N=KXjGpa(G!3$Iq6BwYg
zs%9NH3st+mL}iicM-DnstU6Eek`mSTbUr9mvBh91Q>_i0g7@#7>eCOvTA>=5z;jip
z;*h`Uyvn)~daG2<bJ4X6s({ZRaZzR2j9y$)-F*#cmsP%$p;4`JZ-j~~szTZm*QhiU
z)Vr$cB{ycR>d6<d_quBBTWGtXT0@SAo2qxnms_vOq%3DggKAwfijAs2T46<#inj(<
z+)^ztf%Uekl&%onQ62pP^3AIEDbU=a`hXnbttz%Ru<xp#rK3QbDu)69_f%)-%+szq
z;R=-ds@KTT`at!<T$tUV%A^fKr)uyMv~{WCwu5v#RQt&b+oOtH5BXlz0gAKssr<=L
z-LHzHguww-b}RHgR5{ZtGpO1^^W%`pv<6l@Qk~rhGOQB+0L~Fr8|~a4t2pG&7**Z-
z5oAnNObL?Xs&AgaiYKZqb0ILHGTKm@R5>`;(devprSaOUu1kl6tNL_2VD_o|oG>Kr
zY8z$u98ed<K=7dYlcyl)rC!1U@m41vg7t^gHIx+Lqh2}-mA>j+O6BrXU!r52zuL3|
zr2w^$6(mqCq*o<KeUr9>!D_2x6^bG1{a=7JRIM8VIjp`yv4Sx5t)J2DaP_fMz>ZM=
zNn83z^#D2hqSV`3Q5miNY6d`K)IJo#ja7d{{-QXwoEE-#^;c6t64cXXLM~C=RDv!g
zsTZFG<`H$|E|gN#2S0Pbj8rv?T-j;rPMY=7)sN|!JE6{|{FV&$T5|TCRKHk^Ql|RW
zPXIloe(EJuW~mp=gQ2I@hZmqSTm5DrDs$9RGyuz0f4d&gdFp{GVCJh!-bLw*dWZ>9
zpf&}=inHp;U+G&Sg=)V>@D!<EFhXy!ntur}CF*oqlS|c$<6wT7`X&0H(K&U_DO8rL
zH<Cl4LjCj-JP?)YKPbj<Ud^Xjx=QV`2jqgfgl74RYHlFJFR2;H(0fJgN$0Q{^&1rD
zysECeLXoIiwa+t<uT#IZ5RKQ=9Y(0QsSb-kFY47j6bWun_vfSZK)ux)R&=P3`~>x#
zYAc1xyVP50IqOzeoWvmXsDGs$Sg-o*E>!lZ-^hYozuL-zh5>c=-_ZL|y@pbD2Gv94
z$a4&-L;RrPk$QmQ9>ePFT9`kgUPbfkWAz%!=@?ZnrTp75^}S;BX<U6|5LP@<=O#nW
zS@WthU|cjUDbTw|bA)cj?A2t2pwd-y$OB}bX8jWg?AOHT!Q!TIrZ|AR=HtzPKH$(?
zUWwvC&CBP}Cl5^yg@QaaKi&tcm!@k8(7ZJwn)ME89@8<wM^i*Ekgw*=E*R>k38RO_
zUt<shB|u}L<4vGu9xWh2ng{ga1Zx&g0ZWKxJ_Rg7HR)5K;jl(d&Z{tuV~H3r;hOqG
zC`M?0DMBey!}o+>l*UN&WVGgI9zbI>*|f=v)m)+nDo*qFc9h~Z0*b09XvXOMNz`nh
zRV_&q+JPVDh-Nb#WR7Y+=z`v4P4QEJPSLD+8se#%R@$ehY1TWwhKgev7n(kfYfe)l
zPP%68Acp3I1}WQk0W{L*K~8FxlOr%w<Fgrtp3=<t|3H{#&laGa*2Ga@DO<DYBWTLe
zOgjhcT#Zu%NS>x(KlJ8no_0g&jHYfA#0xZ+4?*Cp#*j$+&q7TsO{GN|&WBK6thu%e
zq(n38Hb|-FDjjXhG;`@{^*POJ&jY4hv&$cq6`D^ei?>qKQV$EyYu;W6fhx`4IjFp#
z`HY79qDD#X?P|@h6cxCl>8IdLjb<OEg<jS8K1JVht<@~1sklyaV-2jhrpcu=!t0tJ
z{LtSUnv0$gys7!;Kd7kJa4E*#p!wq@DjPM<p98H)lghz3-_pEGo5N<!^f9!xXr}eS
z&{oa!F9GbXCWn^KHcilcn0-$(?^Bc>Xr71L$T7V`6SWEQof?}5tmx64t%YE(<^g$n
z`ZU|wXnUwhpx1a%Gn2lfHl&HO!k9-I{e9RwtXcN~3?0$9&PVC7rqc!3qZ&S?A&qHX
zISG_;&0)$leWD4O2h%1rhf*Ohso5|aU=C+(2z`yfMZ10zY}=z<NDhU)+Uazu#8o@v
zJN#U3+R7GSyKCin5ImqAr3u+nJJ<&+ytF}dg!k5-q(8|#q+NXiaz5JpGzj==U!nXW
zKW#`cH2G^iDO?kvZCe0i0<|v)ARgq<j?<nkSQ|*sPKZ{t0*#^CxZ40dtlfVbr7*4T
zZP*m9l?($rLi=tNDx<Y;bD$zdyZ$$b$7+vj(a{8LH9h%>TAcFn9%xf%q3wwF`fiwZ
zRJ-+Al#;c-Q&ww=_80o>RjStU0~eaow1Pe8(=lx)eZ%><wwN3W>Dt9R!E-{pg*Fix
z+P&eZJgIg63?x%~fTsRaS_gS?v$V>iurNpa#d);lYD4MPTAubEo!^SJ-P_Q!6741|
zj?+uETFS~R(=K}smFKiO9Td<i*KWKD!3u4;3JNQ=b!#AaUi<EP7*nO)MnS6!+U9<=
zUDPrUf?U#WSAbmB9(94HYAxeKsK27sX9BxMD~koWsx6}QvTNG@DPXy-9cTo~4Xy1A
zDsO7Fv{Ke<qu-|=uR;3^d953@d6anDr2T_@v$wP<eo)`6wOj*f(H;xMAhc>b_JQ-R
z_BNfh+O%KO_q*?D&r#k@yY^`sp!?dQWRxD@Tb<zS(#q-HSGTr|g?{#E=VijsUhN}t
zVfSeZ|3~j%zxEZn^e~`(SqIx5YQL+7!a=Qx4hF;8+=Hkb(H5=;d8`efxolKh{{(1b
z+ROB&k83k>ApS%<Egxh;JJ$tzC$)c4_;8QTs|Ip=b;G~FG*{hw4=@OBx;ZAax$9=k
zr1Rea-FK9r>8YDN3QN6oTPYjOTlcXDC10Jt8%ln<pE}Vef8EA2uqjAa_6*vBb$@LD
zc8KmKedQ%gw;%(haNU`gVOoSPcs~@z>sHGkkf7_khf<=>dK#r9UCm!$Iih>&1nhMj
z)p_&+Em`*#xnojvKg@>0RNegoRHo^w>7aW|mqSjd<2utau%zq$`wT26bZ=4$MTTxk
z57eL3{qG#qXX?Hphs`Nnz$cK)(jBHV%W2))>!2`O_fY}V=jc>)sVY~ug_3~t9J&-O
zK=XBn{)gfj-Al_MQJ_;FfWc>VUPKCYS16oNq&pS`gG+Qy2`H87){H=)Ot)(mtT?BO
zd=WO4>w;*utk8W!0pUuWW(eZvb=xS6P^F9BhfZA3WkrMYqAtV@;+J%efTghQvW`Is
zEY-R-dx3pLw~__<8r>g8NL<ymp8!m)F5DUFuj^{)*7yxwT{t*z>VjNhZ=-H1IqRBq
zGs#PLOJ`T3vRP-Kopp;&I*7JbUDsul?&^}(qtvGRzz-<*blwhf$Uo36{0O8&C!lkB
zr|ylF7^ohdKe_ySbqzuY_UVr3(AKYeH3X&&=!zDj?V-*bg~~^|AL)MFux@BE$cQeG
z+?Zp!y|jxR*R5Lt&L_HQlQ7L$zk#~sq90<QZIAwwG6(v!Pv1HNwfpt_FM#c)k8efE
zU4NJSO$YR{M6evxuOn}pul{e!_wm!;qrkbpem;3|1N6%u!}>t|W_qlH^h;>p8>}B#
zfdLND-=SR9Q2hW!)eh?qktZNb-|-R#FI?Z3NdC_Vy@xxjiPT%LwVxiP*Dgk5wEhha
zjET{2^#F<0`xXN`PCp|aZSndfIua-7V<=}TQQ!ClR3zyS+(g?Eef!@4JF0*52HKMK
zFL=X>6n$eO^rq^MOoyRq`q?v}=$PJ!R0hZN<NDtDz)sg&$xDAiUrQO_8Txc1Bu?tv
z15wJ<U!te;l>XDXFeXdiM7I)8>o*huEnC0S7ic;94^m)7u6|!Q)aU7|vQe3@pLz-6
zXY`+wqqac5fi8@l)jxb1r9yp91yCGC`ZXNX7VF2TYbE;SyHP6Dmzz*3)A!MIc}`#B
zhElmcDijJU^!*ekt<-NQL*;q>SCj)$rJw&bewYjT4}xI!MZJNd>6i3=fw1DTo=>S)
z)%v&nQM#(vQ@Ev8&mgZzokP#3H~oe_!xyzT^)FD?M7{o*R@mL7ucUDJE&W^nLGZS|
zT7k+Ieaal5wd!>i=)J2CxCn*qdMh1*@9Q5@82y31_e)@Q=w}CjrBfe8vFa{;?;C*b
z*8fHxu^zoQog#bnj=vXTy!!O3k^s}M&sd0`VnAO;DK>-pFZ!W=NMA=2#v^_7&(J%p
zKerk3Bl;thI`vrp$~zDk)i0n>!I*yj>u4L-=j}x06Me~V5TDTJ`9Ra8eqc5F>umTe
z8*MIz_xn(}$KdLqbz!fepcur}&_ySMeTGDDH10PDDX-DZV4!1>yJ5H&@&^p#G%p`C
zEE56S!|+8ZDm@L)ilE-hV0i|_+Yl&$X@?Bsv5@mIgfYSCYjBT6CH}LR91;G8XWs^A
zfMMDqdjA3qjZuIJGJH>2x50)13WS9i-b{fpp@#L(g5|K`Q~EEfFvGT7s1G*`Q4l7=
zFhOqHNW*cuQ4nSDF9T<^ArN8h=`n^PS9BuQu=pon#u>^MgTxztx(4V3!)bElB^qYs
z()*WWs3zNv7&g&Fb<_|@ZpCCn1D&o?42NjKNHxsUfTS6QtAKsXP(l;Mal?BPFecsb
z9c4_PFoaMtT!vxFj{rMqaD56YG7YX%!E(yr5(Hzi3|C(Q%W1=E+FfNEV#+8JD#uW}
z71+6khxbvNXDB}k_4$VPmZNmW@G(VJ3k>T&hWTd=4)S~y8fHy}!XiVX7eI>*gOuD-
zV(_LAQmMgC?$<KI=+i(sX9(0meYqi>9Lp63ix8$&8rH9bz<I-WbWV0u8N9;KnG1$X
z^i|-C1}!aTmkiq|;&9o}xe%Ia438;s=BlCVU6g7KUM(oq8J1D*?={0PtwYxhHIyZM
z!@#Af|E6IZWf0dJW`B#e2E!{}(A#KGM8m=+1A~RqEyH)SA#mGaXrd(NI|exuMl~BA
ze+s=VhMpEQwi*V7kiTnK8-%ttLnST0_YBo^gRtE&phW4u!S^o+JTSaUo9PaNj`Dju
z4Ilpvxh}&~^xffZ!-36U=`o~y4VGSmJGq(r4BIIV(2o&ipmxCUuoazoXh^07chHbb
z)7_9Ek51%|3{QE1W!Nw{3vDBYb#$V5Z1B1b`B8)WpWqxbWY7+K+@PYXbWaQc^kvrx
z!%uV*Y0@AjXlG+NAC)e~YuhnEuExC-QrTxTI;5!GZ~TsOf!vIvZ=%-S7)A;Y7=NSe
zyMxC3_hGPykwNYdPveOwRC*aV(NE!Rw0;J(L&nSwRQebflWW)4_{0BD>1X_$l3@Lf
zx5z^jVD$eD!yIU2UqF|Fj5{eD9&FsmrAs&=#%A)!g&IfcTy)szJC0JAF(Csa+&GII
zJ`u*<J0KWo9JN3o%D6ijDx!^}o1rkqcx(;qjWy2u4B~OdJ0HQcc;lT=up}6r7ojcD
z*h|N;B;)D^pd2yAeu~PY#(-M#za$&$DYrDm_}p$ZrW)np5KJ@vPE+YIV+@^njvJSd
zgDc(mY$jMv8qd>4F4LGpKIl`%{mm$48PAc~r;Q$aU}3f~G!-a0#_{JNkZas92c<mY
z$iD!~H|B1Iz!~G7DYXAAFm67Ep(!%{N$*&(F?$%K#Aup;P3MgFTA`xccsLU*6~<C}
z<g1K<k0F1-SW6zji^f%Stg1G~k`L>Ov6<3-YK;8FAoa#J11cMg%{03=8sDRYwI<{J
zn~=L@3?Rpc<F@hmW_kgPQIrbbZ1kqMM~iVG?Fw6syXXvl*O*1qU7K;%yI{Fzd`%D1
zZgeXI%YEY`x(@lk=-Up`VZ2m=woc<J`iM`LF`xnB-Nsr4y3}LLprCE9G2tQ9_ZhEJ
zV5r|={CO0%4H%0lHTI$L`Vznl8cQ#Mb;!884V90KyVQUgHujW3V$Aq}X8CdBKq*+B
z82^&M-U*`%r6f!m8?zwbY<ih;0$fa4#c11Onhb(X`%On^IdU`oZ#CrHO$nZ0Ibd@5
z*MJ^0eeyc6JxtrDLcOO+PbWSvQ{UI9JY)*}7{tev-;YXPQ*0rAUq92vRKWO~{^UVC
zz_gw&?FE{m!=Wk2^r#dp!KQDPp)JI;XA8(-(^Q)L!c1MMurS;-LZ^iYQ>lY;OCwGH
zyMqzJzg3a9EynZ>9dBYyAJP#s-t=WMx|U$NOmWLZ({@_ij+pum0OqJEZy!b`*|eIR
z$0?>@N|H=96+A%cxGCaIl+sO$x&d~=WTj~`!_=)t<w;Y&5-gdfV;@oe%PG?oib7_Y
z&OHF@X;VTkO1Y+yX7n)6w5$cJ`KA?f!Fk5C`2YPkrqQFQJZn<Ysk_i*T!&5+nWn7;
zcCl$^JLF1Cf7ACUN=+-;(X%pBBNGDWObS}=%T2dGMq7pHm%H@$hn1!l@|>JEiK!P=
zroA5m?ULy<1(q(G3R6I;O<NbC@``Dl3Gy|j56C%k)np+rU#;nQE-LFxQ}qzPW-_gX
zq1R1s+yJ>@l5Gd)O;h-3v^AJY-hyfPH@zZ|Cey`Tlz(>1lsOA9w@o=I;JIVk(1KF4
zDTFQpx0r&PV1BDfy&o3dH8qK$sm;{Wi^_W@c^+8WP5tqZyKfRK2YFyB-i^u*lZgC~
zou(kV;L&9oi$GhqX+H%8drZwfu&LKn9u49cF#UT2^r7irO7k5wt?-BXVN)%g+DA;r
zYv{#eQ~nzuqo%BEkTFx{QnZbm@??;kG|B%4wzE0)Q?$95ku8M%l=-7?QR!;#i^1US
zGyg@#>^DczW94Q}m%s{l^Cw&wdca{8w*%&&nfV(eJj_M3Sa_Px((cg9Y@^F}KIX&*
zRQj3=D4E>P?8XG~H&;D^6#?ek^!>#^^E4Y!g3RfZh#YJ_NY7k|dAU3EhMITKTyofK
zrdc}7T)PJ>;pWtvup+|jVEO_((p<%be3bdq5sY)RIrn);#F#CV6ccM^vCyYD^X890
zlFa#(v2w)x6zx`ynn(M=l5Ad2zOxjwq734x=5caaq?!LahstB-a0)gbH`fJ$q??~V
z29^`%HN}w2FxNWn0PUo?-vbIW%>xY}r_A2uoXIj@O9Rho^XKoN7ujYnx*nfnene5Z
zTyp_kVaYRZr|ng~`7Zfu&zRq*okfB9NHFBinn&ovH-+Z)nNV0{{#A(H7n>hFhkllr
zBj_MgYEIKQAXsK@rK7|-^9z)+Qf>~QZ9|25<$F+AX%3l%j-EHC)`L`;*YUx5!R$=?
zlZ)oQe5kl&&Z0BgW%KK2K&s7KX=%S={+*_j8gmGRRIZx8E(NJI2hns>XTJLijJamM
zbDrXV*UdN1qIknRKv9L8=FCq}sy7#tr48nvD0jcn{5?%HP3CvWJ$K8zn6hSXo3r*p
z#T_%BynM~(JKZq5#hgV!vQ~2^eIenVnN2Ae?Pkk7wB0wye2vNn=9lRS>@c5MO#h|R
zY0fAGXqTC_0{!ha*Hbj3$E?1Fj`o_@k#n-oyv~L`^_!oi)qlWTLkVCH&Bo=Z95ml~
z74{CBUtIvs5%Yp}v^_R2uYvWW=J}+4%=`fzO~=juqpACed7VFunJ{P5JyXY|`5XEQ
zg0rQZer6ZTEOM^wvD`ckp1qb$o+!CmtT_;Lvuu0^mF|}K7ziA&q*H$nTISL5#>4U-
z-Bj|loaDd?FH0D0mb@*An@~Dr`D!jud@TJU*yL+@@FEoXS&He&^><iyE&xn`rIg;W
zK+8L7@B~?Yr7u|rTio?v4Y53`LtCijb(#eZTh@`YAk6aXY$y!3T%|o?gr$u3T#**(
zivWwUJfDWPSj!~Mq;Zzn1Qu`Ea{(*~meLLkSE8lR4;Cg_96!+R`-o*451>aa>lcA1
z*>e2^<WnsEbkix-@+}=t(kw4iG~$>ghr9&omKZu6ov;Y$Y?)zsOuM_2mMlFgGcDsZ
zz^5$r&S=ZBRMmo<wq)CZnQcj%3X~knC*`my*K)+cgu*kHm4mRfz*1R*+Ow8m8uen!
zM@o<q3!8jdrIyci=xCWm-3}G!EQWVbDz}XO|GvobVF*|%EnVc&I&XRV95hu~-Zz0<
zu)IDOZ5J(kx=eA&@-7{oFI#>kpFy?dW)iJ`S1c0;U~rA)01N7`T716(cCF>#IcTf1
z{PQ~6u36G!fOg&TaVKDISpIqqZ8t5cZ(xAxEs1YJMT6zHZ_t-U3v)iOn=ErDA$Q9%
zXB+IjZ7JRby>~1M%HwLb^pR_*#j^A>`Y)YU%Qr1(ylZ*v3esj-MLFT^7AqHm_bn=N
zJv^|q(CX4*d4^WgPRrAD1+>dDPT~J<OX@{b_E;84VSTS9><?7-S)R;;T)*YuV%R%i
zd4W=CA6jM#Kn5-E5E-&eMWoL${gI`YvQdXEUF5nSv80Wm^w`3pbLXff=sIA=EYk)6
zI&M)IQ2E5NG!&X9EHmk`oV5HVfT7OTV1HD)SoLn;+++Qnev!S_#gvZXYOTBg=zZ3R
zehkTe>)a*ir<?V_FJN)FTWe1P^nmrLC=?G`ue<~v59=n{PI_9G(WcbPn(GhZZJnPF
zmP1x=dZ2u)o)o9?wFcIs&CmKV`Fs7XizomWV09b?W}tN=IaPwJp8ujU*eW;<fe`B;
zWwwS|T?6nN9Clcf@=y%3w#32GaO-?p4I`|JD7h@sI-kN@QP%nUz#45G$9y$C#@e<Q
z=Eqw5DVZS7x`+#wc<Y1TK@zM}#z7LT>+XUx$-0iRtd3aU`~jFpt$7r2PqvoagItRB
z(sfj(S{+riRHj)Kn*e&uI$!}gZoN1Hm~?BcJK9cI{}+Z|B*W_V6WUH%_dW)8ru8E2
zvQAsG8Q{#e4vhdi$NDPy9CEF<(jky%o%;X+`PR+_=*t<alm@@R`u!)UJZtTsV@;v8
z!$FRLBI`3Qu%_6$_al@_tTSn=S!xy2Znn(2jWUbQS?5PUzTEm9xp6A2t0<~hX<bI4
zg7a4UeQ;J;tJlM(3)Wx5KrULB(V6s;HJp68m#x{)0Hxac?Elbq#ahD#sj+sK(E4}P
zy4(Yewbo=>Nb0O>OsKqOy+zqw*R9=EP<X@2PDk5KYc;*N_15*V7{mr^!x$<Xt$zif
z)MPCs$H^`0E0pwf+xn6M7T&Q2Q#7I3`Z)`RwpcrSU{k9#cqcILTFZ8m|E10PUK)7r
zSqoPIt=;N&0FC#pg8yHutlMHB(P33*f~C{?GUe-ZS?$><bz48Cs9cY=U>gR%*UG;H
zd;6@Xr{EXqx2~b5Y{2R<2c?JB#q=%8L2FVsz=o`e6iR($&3ZujpTpLC9{Mz54SfYX
zkF5z54;!@}cmQL@te$icXWaU*3gn6P?i#3=ur8zNYSOB?24kFUSCe3ci){k~Htn&^
z{0D7&ZED&QxY|z9F4oOvKMfXl+taH+4%q6ou=k*ChBvHmc-X?2FwxWY?|jrAvSre(
zJRh4kO_#p5@4i7>fQ`QcHU-*Vc^9BTwtugpGT4@51PQTC`5vI5w%BcGJ8V1tD*6&;
zJGutOgxmBBKq73@9)UB`CjA#IQMMjRf{nGsQoKLTVdJ=iC*JlJrFtgV{!BnA(Z<b!
zF-f-FEbt`TcGE#B#a8haU{Y;ge}cB-wz&^bnQl9C7o`(6|6hTfY0K<}_$gcZ+W^b5
z#ixShw2epm?QGjV^7rQ0W(<KP*Y+9(0P<{(&UDD<+v>=zamKcWZu}M4c8V|vXKkzx
zAyI5wLQbp_+e9TgT58LD0|Mo?MZbVl*uK3EQfYggJi}GC&+7qt!4|w9dN0~kEfBwC
z^P<b1mu)l2{ZnnrrD^Ai?HNiusj(RxQ$erVo~A3WwYCN^N_DnQ8?3l)Te|~4-VNK{
zcOh}prk4V(-WD(ur3Rao5=k0uONSuWWP52HO1EtP{s4j7wzoe-5AWF8o<(J=t!WF?
z-?dq5(7`s_nnYN5&*n-`V7u*?DHMOdZ(A(~Plqjnb{3ts$di!ovdyN=OSi3*uD<oy
z>?Tz9+D3h0TAyu<?u_=^SOF*v*a~PderUT{2V(|pr3okv*)+d`<&jN5j-p}Pa|=)!
zvAs<BE2B0RotnpND?6WCiKp8(-U`7dwmZJ4ov?+?hi#L#oSz`!Y`4A%n_TSkgWs>m
zZ80Hb@9nck%tGaU`^(Eg-0VGcT5z|2os3R+*tgSs;b~8&D?eWLKmOk{WiOy@q_4d%
z6pH-pS#$>Xw~x~F9AF<wMk&zlZbvD^{?Qb$;QRh&ln&b;kgp=leqj){gxl*KNob6)
z>)*s!MB3kU0Z)`&W`^EqdwL4=#@Kn3yccU9qa$XV-RBFCc>9d$=u(2cAOYfu_B}Iz
zmSnG?1j-}!6A5TLY8RdYSgPHXLfvWh)MFUfWA=A{2RUxfR0A{Jp7jDfG$-sQJ3%t-
zgDx1$Q}zwy2g$Nuq<aK8_A9jT<=WSD!k9d}W*!vg+ohELcE(;Mgo*;YuN9zY?H{g&
zc%i-82(Ti%b0(}Pwyz6CTZ!Egf>Noykz9>s_FK*nKWATYpFW;aZlBWwg%$R{UxtcG
zy9}R`n10@#Bt)O8>^0<NxM2VCCtzQ+2kL=#$<F=>XqWBkH-T1d_h<*_75fu90oB+$
zZlHA4{yZIGui1M)1?P2pYd`vO!~O|5;%?es{~ML{_6;8NmCgqHMt}6M(Z239tZ1@}
z$-{KZe%uLYx9v_e+;{BdbO)^2&i)ORE%wlQsA#nZ+=oqf?YVT<rp>;CW{-Pz_2=Mh
zw~y1U^!xVG3X~q$PgkQ89d_+(bi32e>&K{d*?*h?aYwg(2RV~^?5i`u+H3##c^K1Y
z|Bj+X1NPf9(e}{(O#@g5?Js^0m?8VZERaX`vvf2awx>KqpGNGHA3@-;eLKBWWA>H5
zgN)mE)5h<KeaABpn6Pi40L!HPiy2Vl?4<r2l`ama@MRF(>(oIGE?1}Sd^GNJV!OkN
z{Z4miWZay-qY&;vr_5lKJe<OR2dAgg97;Fxaw?`Yd2c7J0)ueK>FrS{^l@tILYuGC
z+U;obb8;cSxW7}?->3|5I{pSU1Uk(<0n8vL2j@?K20N{y{N4~JH_A2)b#kV=a)+H(
z(Y1{*r|fl*2zN4EgrN~mpL~vAB+{ugA0*1j9t!bjr?alGDaNT$2GCfi)hi$#=j2N+
zmUyQ%<Uvnxs;22G(dp4?pd>lXCm;P0rwYdec#b+f`z}-@J5A=n#55-xMQe{aIsYF^
z-vJiY^}Ox9%L2QUg}r5WSy&TIG%+!j#6*qJm|{0}jmDB#e<`N0yC}wFX-bo(AR;Ir
zh}dW%(m_N;rGruw5ETR!><AY4-pTiW9v{a!XWp4PXKy)YX3o_Ex|5yF%)q5McSeIt
zbv~_zNSd>R){m#1A9cZt3}>Me+!^Q9XV91Fd{PhdS<dsRFfiMBhab%6I198{$#r&_
zipD(Wv-DWccYf|pZ~p@4#&u{dbnZ`vi$%_!6u>y=oJWD)VrQ!?czWJ>JC#XXaQ4{&
z$&1dL5<yCw<zr#~l5>zH$Q5TZ+CY^$2NpoG%vn#7sdDF*HGo$*D`<^a>3m)Skt*ke
zLNr!8mk*`gdX2L+eM_&_`RMmRTy@s&#we~i@9V@U>YTeNaZvB9D#1K8I4`0oP@{7M
zm3&=y4yCfH8_u7ch0-SHjdZazJNr`=TZ?nlON{rX^P4o_TAkleDbOwFp5I{Tw)3o1
zz}uZ$(+A=HyX)NT2SkUnK*#6rIUo51+<oVIDhhqz{K;=H-{l-l+k|fCDEieNI@ivJ
z!AH&q={&$==M!mA`o#I#6o@=^{&+m#&z!>+0sh?CpRxfx&N~Ot*Xz8b2Y^231bXeh
zbY38Vr0JD&Kdoq9J12bsnSSSc4bV2={D5lt-1PsWb+5brgJp2dL+=?4NiY4BJHYSI
zd((;Noq9dJ;=J|OX|dy@pGX^AU;W3sA?c?d?*`6a-$aYqU3yEpRs-~9G(mxSM>?_-
zWYWh|!XsEeVJbR9^egC&-K|fY1erbhXB4y!)yr05ykYvJ-5`7QZ_}z{zkbmTkVyTW
zV2~)ijGnIt^y7UYa!~*GbikwaBhLXIqmTOvI%D-Q5$HRle}5zF#pz{57}8<A={veG
z67=V`L-dF~`#iiz)PFJ!qDS@Lp2l<^(+@t0zT^5~Wf<WJ{oBK!?WBIPIq*sP3-K_Y
zqW_J`j8gS$<3Q5%!*!VFQ~HpPA(^h9@;Q{9*8hG8eHr>xI$d){KO-GnroPDJ4mDZ&
z&qhFZw*J#?a3)WGaS~+m_4#zo73lAlz<i<p5*>j#tDn9fz#@I`J~W=w&(H&2tUt94
zqd%{=nE}8B{oDnxdr|-PUzmgvy?z3?OZv{Aq587EY90Vr^c7SDSE}DoOxH)5erhw=
za{bv}bXMqFwxO|7Z%upXD!rNtRjc(~HNe;Cb2mY<R=;yLbYIoGyMtWQ|3&+QI{lwi
z=v}YhM(@-H{Q}BIH|jG-!O`pbksm?l4SgO}q&MlE>B_ySul$$pzgGPj${F9%+r0zC
zZGBN2X8n$SR4;&S`uCP$yzTlU|6-o+>TgehWQV>l75Gm5W2&pTr!NhFhxhgG(&h0$
zZ!r<1ORu3|PPcwG6=^-x*WZVhNBU;^QtD&<y+Pof=sBc^@L^m1ySvc(O#jzG0H5oB
zxCx~_`We<R_(DI22GgrArY&NhzMC=*FZCj=kYDLHQ8B=4y>AIb-sqhujnJ<Tibvys
z{xOT`ax+NjfR(#pvI+nX!@Lim#nUi+F&e!LgGNEpw8J3M25hHcA;ngG4Sy|zsGs2r
zdMo)Gj;%oBF2gA*XbLdwrfW9Pu(%KY1{oIgVHClJ(hP7RhCk_rx!W+3R+D=S`LAIj
z)Nqc@TZ9>I+rpW>hWF_88*XT$!k~Qy!yGh5m<+btLH8R%|I5Z3mT$nUM;QvKbn1X1
z_#2o%X!!jyxM;(te*hR`$o~MkV-24>!_h+qX#u!6LnVca;|;avF&BpopPGY9F!+%d
zM+_fQAxEOYo1WQ64YKXfa?<eE@8FUQCij1!CfN{5JCPJa+$o5r8iL1QplOEUayWd-
zFqgxa(hXLRp!>AJrXJiGgWv)anTCDMz-1Xem=9dG;eEQ}at!Zd8z{{+4524!p5e&*
zFqm)9lEDJQd0GM$8p<dbbJnolM0FiShU@h8nsbKv-@-((p>Y~IFB)#tps~c@G8fKV
zGW5)Z-BQC4x>d>y(`cnyZn#5Nca`DnSy-wz>=*?=jUmzlCaxLcsDz@<@QlpY8zhkc
zG#I|W3esp;R}P)m4THK&kZCbEQr_{VVgC=%)@m4&4RXuy6Gc;R8(z>aa>r1wf}{99
znuh_{Zg8h+mb->2+dw)DeUvKiG%TT1>OI3k%0k{ZoX*C?J}~s$gGiTQ2u)?TLFNiW
z4-IE%4e`kEd>nl@=CQ&48@Twy&_fHVr-tCG(DuwwJsaAd8v=a*>@oaC0iPF!aa11F
zYw#k2eTJR^ke7y`hwwAMG7KLM?zO?91zO%1hEQs;-|%c2v<w(N{T7^?aoH}|bvJHH
z1m|H4L;}nt^)xP_Y9%kDF%EcdV@4<p`WS;20qARNr$d{5#`To<@HbY`x%pj2ML#Au
zz<7+7zk$Zf6qE@v9(xX@!N&Je01q+d&jfC_QAau7J;tBtr5I`ye4#VUDAKxSukr1r
zfSbaNdMcmWXY`;|e}u7$wwU{k-%+Vcq%r0X$V3_c{Tc=j7`M@PD-If$QpPUYSn2`0
zF~-0qh{PJ3OQ7YDQJW7FamHbDLE??!RAGA9SWF4*1mg}mLvqCUqa)zQj7iJUcid#$
zN*U}E#*eAI<D_xeb|_6UUZHC}+4v|Mjj6`|KVd%2=%Ry~Q^tK)Fqm}XxWf=RZJc}=
z@J!>+GLS6ejc?#gw()2)069i01-M+}jqjl|&*(!roP47N1=0(Qp*>JtXf&Ot+rQW-
zIRN&&@fkgdFBoN|(00+-L(!NLqoE3jOGbyC(01AAM1=xZjMu5ksnqyyDn?Oebfm(D
z3gePFAeF{-y=bg5S}%jLYU9!rG}aiEL*egL<2442*NpS8fvYoaFu6cmy)lV$p$$fr
zFSthIf=8JA>qf~&h&CD9X|vO8ob(h*Ta5D@z}+-nq`RussQ(lm-ZI8h?)J8Ea3y?d
zGftyI#&%-@Ws>e1=TlinhjBDrI-SNyIdJ!k@4kY)`^J%llyvGdcG2v;F&;SqnE_+Y
zIuH++tB%mU!^PAMypK!B3LyMlvKN5_x@@6Rz8DvM1E%D-%WF!Fq_|9?kW{+M{Id|r
zbZMK6#vGRw8!^y)7pHs->8#64+TxveF}k4fipyGWy8o`b+@Uygr%Tv>A!U~Vs;_wE
zvhoUi^4v0kt{v|!o0H&Z(3ZUOFc`7LwiqOK%VINladeB)8J1GF=;#!E&X)IBC@bEw
zOGIPImft>xNadE34&bhC$=d{xpshzaScu%ZXfN&m;<k?Y0=iSTKHrSijIAzh7<T^F
zqE%2+vUOQG`YN~1ryWJ(*1!LT$epcw9zk2j);4;pJ>L59?=aE3b@3;_z1})k4%a+f
zH&tMuey;cFjtg*|S&OmkcHMgwI>TH~vt-_Nf*0VXcvoxMh$XuA%VFt+YsUkKCcEw=
zV47>52SiW1{zT844A)QEfjHy(59RbTU4;|C<+;A1r(V8mPbYjTboG7+_*vJPJJDC<
zI<Xbxoa<NXaU~SH#{8EWbUjIj8ZNj-w9y2aT>WX2cFDD$D)X+mj-_=*scXg8Xe@Kh
za)wXku5#MIRk-RXOkL$VpCZH6t}}+Auf{bt3|y_N)mnIX&DDJXl69_XN?F&tmb`>W
zgR3tEVQ;z4tbooo*T#M3K;X|gCJ5O&=wOsF@b4;fpH`1`OvQ4z(7=4}294L5?e78A
z#0(Z8(!vboz_l_5={R#6^D(^>x|yeG7|;u*h~5cq>_9h&FMFKIn0B)h5-5F*KjOae
zaAxQU`UJ;2Pw9$z_jm?Xs|^dIW#;e)di*`%3~kmX_KZUJ=cZ4febV?}@b?#E-OxK(
zIUX)eshN+N`Z9hR)J^^KHOBju$0M|SeVj_czmZcx_qRRE(LQYjWlW}ztpj$(l2*vf
z{LCJ`vs5j>&bFhqf@zLhC}wAFVmF$;TR=<Qd9q39nE%dO7}Wxi&IvBuM^m?GUoK=8
z`%`dfNz1!Xx^(s`C|&loBYMBLpy$K#FIlv#csw2d{=qf@@+)iUqFEJTiT2fBQEYzA
zYHzgs_)89~tThdaMaQ~_hcR30e^UXlVQ&DsH;zFmk#tiNJ#zooK+)mtYfs|u9gG<j
zqV8mdQYPJ-F(d6hOa>LO`Z6uKu<OTY;-T7~vHB3B*~OI8A&USe=)Z5(F#95ayUA?H
zgeMP~5Ys{cA2Ac@`T3Ih7uSaL6?4~yEV0caL3XmEslM8qwV~1*A2ww(O!%@>^>EdX
z{k#Wi{MnH<WQi@-Kr(=BsfNKQ_5f{S4zLqWf*fH#pyyB`dtnR=9c7cK;^!E9^*h>s
zA7@Q;%;5xkhOYCI?78F6oy4Y6q#&7{8U&FPw*Mw{r?LxaiIc|aDYJZvy?Y0C)7kgm
z1DC;mLm{U#>}*$vWU?C_pzO4yi-Im05@)KQIU_kqhtM)5>~lDiC3$m?PAg<fPHcl{
zj-;73QMr;B%H!lo>VJTme95iTFi{}6V}P1M$qWh<oRwUsg6twmmlkTyNqQClP%PR0
zCCGV+n?J^KK~nQRL@r8h(vh|jN$Q{AE=jyUfwIezhC{$zk$m<Q?Y~PU?T%1dCi%V@
z2FoSCehEtzl1R#oRZ5%|179UMumFf^3HufXS|e$s4REa_eLpN+l?2e~!fTSl^I@V+
zGG!G=y(DcgBpW0x7htea^7CW>u1g;5faDE{CGEzWBu{3-f~i@er~9u(5=#d!Z%S@b
z6;-R`4qb$|B=hL(-)+fs8OR+;GS%9(NhWo{!*<ENYvArmew4vrhvWtA=sG3+A4BOq
z$y0y8?@PkzP4+-CW*z#vByYX}u3NH#zNGX}GTZ?2$RycA)#Z;R`{%>N6Uk62SAHsa
zO_|<jlB)sm^tt3Il`r*3%!Z@yg=B0Z?Dk6jJOJH&lJ6<8_EK`T5RI=S)()6TH?z6x
zF&1~T>N4O`%s!)>QmWZS19YaD?K%wZlv(vS0MgA&Bkw@XX|svfp(ev@`BSu>F<YAq
zyP0MRx?L;G*3m6mY4$?{fK_InT!Lh^nL|0q4KoRqDm0n>uN0DPX4Ch8w3~IQ0O&M3
z^gTrGnLQ)7y`}p)q1s3KQ5<~om1=F_=q_ooiC*gg()9so4U{Ijz?mSaIo)y5QsojL
zvZRk_6O=7odJ`l^dX?_qTxroI;Pa&NOR$uW55U7jfz*z!)k5ia=V14&w5}f9Iq450
z;9;@U)dP*^r7l!_bwPT2KHwLn!y0LOSt3n-2)mc?UpBz*WvPk+^v&kYH0&00@f6hD
zG><t1uGM_}2;gs-htkXEwz-D}<c|4YcK~QJuNgzXmU-w4c-Uk9qZEAu=C-uIa<f>G
z2e`XM$5nXYVbS&l?D<=i-=z5SE{kPBXbrGPdLPaNTCAsKTd>8*(U{8+i>YtG?Y2;#
z1s7^@zYS`_EYj(Hyw}2sDrmwjqK<%zw3zz`NR-7<3Z@;f*s>EO&LXN1jp-J<=~;i;
zV%DD^85X*y7}6Pw<gEXyr7eP~S~JHYVk$awEk;t!X`aQ9FX4B-#V_B(e1XMmM{pM{
zmeE?Q#Nr*g9WGh4c>{3S!ZZ<$S1eZCgO)OjkG23_Zjm_)qp!1gkAvIw7LTrgYp|%S
zfKQDUiaeOVVR8Fwz)ejSxwI~Bwvexcnih+td!W13Vi?7!Z&@THq4AEzh4E0+W-*hV
zFn2AIk^$(j`11-x?pc)QfjqESHv^Jg7B6-H-fbb%zzYvc-H-5opJmw#;36z%Rikmg
zWkMLtM_Rr|q46k_<!MUjAF$L!L(M_UD$0>YTjsYxG{$o47Rba|PP_))@s`1K#^kW&
z1d7EcSdN##i$u#W4IoD?fBgVjj#;+d19#j~J_nK~EPZD~%W2DXAH$0b%irk?L8j%T
zJUEkO`F;U(W?P!9D6N@ed8-tNJj<>00?xNI97Sh=Wgiv57Fs&dWA?12=!(X3mTVog
z6<hA471DXj5e8_xV7X^H`bsP>(lhLmW!H0PxokOg68cIlbE%ND%(8$YzvY&x8^Cp1
z{!FJ(?pc0pqCMvWOIO-{bXf*c0J+<;q73Ar<t%#DJ+|C_8Ner&uBDKCW*I;avFDak
zYQXhdeo61B0n6!^0e6%2SVGcW7MllWJY<d(yY!Szwucrk+4Fzl+74L`J#=@<GJ4SG
zElZtG;YJ_X3abALmi@R9G9j|wZs^`4`?D3mP}wP}<Jl_<Gyxbci=~ZhvP}68ETzag
zs8l^o7DTDIQ?flvp)6gtZ3np1GDQnWhAf6&;%8*vQ58j|EUF1JlO-F5a{|(Anf@WY
z|8iudw2aA>T|EbqC#!t~_w!|wMu01j4gVeZLRk$KaniH07xay*BH90P>8FrQrk!N5
zY`Yso&daLDL-z$)Q55<v%GOY<wnP?AvA|2RU)MtNvh3O#NM4cMoC8uSTY#znleAnm
zz5y~7vQ=*|>`IwaB0Q~<RZ}5&wTyFyXpJm<CmL&IS`8$x%Er(oa80%~2&7(iZUrP8
zWU;hIZj>2c!|rvNssrSPECI<?X_HL*7R)!xvgnLfi)<)e2{&b}*}$1vWl5fBy(Jr<
zDZMRgl;NkiBir&FNSo{(DnMwLMKr_GU0FFT06S#W-O$!43ta*eA#(iyT-z-l@*x2G
z<soHI8Y%Clby1Z3E83zTkl*bEiIz8h4rMX&XxcX%l8^ZbB+eusYYkw$e4!kk9+pRJ
zL+cUwCv%}DQU1qU(0x??*(Q)<^3T>n=?Qt05`9T>(=X7LEI&@+j%@i!DkI8~Yd(Tc
zdGaT8J>|=ppP}=DJhdJ=E97s{LaI{kL>u-h`JMklMsm|cTXfdQcQ^r9D{n}KwyW}<
zG)&1gdG7@byH4JE2zKk`&uL$IOCEUx<hHz-wkCJvE2*HmO}^zf7;Klf)BE7A+>wE$
z4td`-xZNrD^M&gB^4AN|_&_e@p}I@19sxt$at{-|F(1mUDERnD-W~#jkL6ESqw|S;
zDjiIJD$k<BchBVC?t$*-@;&rUe<A;sa-F?$t8l>k<R8*<@THu;2raMVKmQ2wTHcun
z_#1hWAGm(`ufKpBkjMW3)oxbntl^rwmD2}wS9w_7plyezRow<~URI^_@ys1oH;!SV
zc3KTP4!pNjRXp7Hvl{jS2K}w()9PWDRXpvw0<9Lif(x>mtbl95R{c?E46(AH&HQdF
z!(*u4V^ur{T&UFnI`?(JY6?Xi4q7cgNYyIQR=LqY#8`bmPuoLQ&+mYXvzku7eY}-n
zA-Gnn4{pQ#7gpOwLYtfQr8SUrw_YCugC5rH$H{x^$~K62S?{5<`a7%><^bnwT|v7s
zKkIF);Gw^D>?-KoWnJL~$v|tp4c&i1)|V(p8)EH2Uj^80{dWXp_F6xsY;3so)k)~v
zXYKqe+>fx{PLHifYt0YP9c4Xc9xNTOJ~9q{2d#(D?H^;k=l}q**2Anp4p}#T0iAKy
zX)j^^u(kJOG$vSQQHjD4>vOd4HYHlG8V#Ce?MF}RQ`W)-m`}H6=@D_-dJDbWGOTNL
z0G_cPPDMVM*887;WLr<7J3Yrbn39G0*5+RVS7`le0VK~_xBU#eRo1yw)?IBK%t5lo
z`q>in)mr<~iL0yDdIPjvGg+&qpta80K#!f9){kfr-fI2s19aZ9o<Lcd+txf)dAC__
z`3VE<v<|Naxo18279{UmpGkrF2iA(c5P4`lfdXcatWSS}zQ@+KZ{ufrVx2Y=W9hM8
zy8+~d^)f3+_FC7K!a|?5Np}gJzO?>49hP2MH`>69*VfCZlJt$W7u_-eHg&5&0&V`h
z4}6eK<x7xY8_ic}46#w)2H9=%Pd;#aY(~+}E7WEb-4$UrtxBlgYvVrx%EE2T3xV5b
zvze}v2%FI?ME2X1nNmO_ZT_7N(I}h1zv0_Kn-lF2jkYlj0*SHtiK<;<ZQN;(cgQB{
z93<mxVv8}tcpHl*kOZ6ZDonx=n_#*}5^YwwL(5T{r*wq&xXs#yn648x3ur-f(q{SJ
zFrQ@OG8H7*=FWMFf2G)1Qr&N=%?SE*Oqz{+0)VG%R`tSey3MI};4^GiCxZCcMi+tj
z+IlX5q@V4B_u<oSTla0SyWjTF$21n(SgIS0vX#;f=78;GTFyn=diuiA7~9b=(HLv%
zQwa-)Z0mlN;QouVEu#Q(ylo$qhn}>3d=);OwzYQ!$*@%&0^*EqF+DIcZ9CtCnk%-+
z6y_|o?f(*L%4|QP#pP974Mn`J+1gx%+jX{gsqCZP_9F^KHrVC~5NWhcJPhu-ZGIFy
zykUFsKE=P9Y+Gsj+H7l9j~}nacKH|Z;-+mOmEX78rYwN_w`|w11-WB8k3w^8wzp`P
z(r(*9F}=IC;S>e$uoWW#cw(D%3Vly)JzLQC%+`v|T|T${Z~!`cY=t@CUf8-wF^FE<
zVQvsH_1TWmqV=V1a4LYWY$tw-*4MVHDdh0R_A-4Wqu<tvt~ob_jTwOMin3oJ;-T0z
z7)m`ADfB+^QtX%tvO}@{GkCF6@udNrx8m_%kn~X$sQ~v?%xwU`PhnbzMt{ZM^Dw`=
zOp1jUVLm`Hf+`dP6{9K59;CRjAC19^88oFK3IpYhcPlnTqj8Vo(NX*qVG84a>mtRO
z-yssNm_}t@`xM{P+b}|*<<PiaQQv@>iB!111{bBUu!F$^iX19qKd5-I3O>asOfzc0
z#wsdSK<1F*D1~O?6mN>r8Lu$SMc-jX)@J}FC|oH6c|_rH6ef-;HhhJ_98<K?e)YKG
z{0vOq2}J|tN=_<D5}+kXVfQN<lNIlM1us$*vtpq$RZ&fqwrL9c%@8@IC^5Z{)^vs9
z7RHpJ`1}b(&nSHFViGbHlm7ueOVJerM7H9}NSM!2y!|t{T*Yd7+U6;yP@(+=#fML!
z?V=)n82}}UUG&Y0ONzfKSzoQ_2!Ke90!t%2{1mf)LgQ7%AK6fLO_339f~7je+9KGk
zhZ>BjLGf)C5RHnr5uTG?SHw`o(GA7_Xp7mT$fs>WvtkDYnpzb9x<T7b#jywgS`}uK
zA#z)>;CD3MQON$r$l4TB2GG~8SndtLUBw%Fh;%62>E+U?I37&*-#x`83PRmi^wVYX
zKw&i%h%UwXx6s(Fh#ri_hl)OLARZ}_8sW@S#ja7%_Dm6U34PBM+H(N(D84NNd7%(@
zK%`euKr6;RMSwR3`clzGMRM+TGWuMRhg}t&GV-)rA42&bFT3WyFs7Y$@wE8xw)?IH
zoR8h=kud0M_v~l7X6+8TqtD+ilV0t+>{^GRF~II?Dzpl;yGh4Eg6zELQ5I}>o`QZM
zcJI-Lx)SXz?J<aB_V3A{^Mw6`T;P)I({ykq#eU5{uwY8FACnJ6y1jvRd>Qt3qhTrA
z-is2q*X%p<fxl({5!J8XwpX73cgMbLHMlnWf$xEDx3_!`@VoXW>Fx5^zS9rRJh318
zF(iBJ3pF6U_Kp-N@3Y6N5p!X$Q(}T%*_Yjf7q3nB6Dbn$#(s7ZTKnw{RN^#XZ<!2j
zZpy86J-aJ|*TA5M@=FnTPvw%i0PIqJz8|^+l)rrrHId3CROK0^Gz-J94=PvE6FgdZ
zpGxavl;2GT7pn|;AChs(m<coq%7$71l9i^KIM~fn7A1pZEB%(iV2(0)3}ntL5786x
zg7U^5y1JF;?gC$;45NkTCFR;lAeWWD9Ru!)vM~#|Qe_|g24%{Re}mm}rDhFCg|eH<
zLo1b<A`GcYIfnwe*OfXdRllK}XQJRtlkyuqEHx`X^#P(qxhfdkP37Cy;6<x)=Wigl
zlnyM&ZDsm%0PiTjdV?{wDW7+MYgcZja`L-My%z8eWgR7cI+bs~hNXMT-bUc=E5Drq
z?t$_j`ro~~l#{7Qpj)|Rh6z8{L!}LUYvYm9Ar!#J$_+~~rYFiVt#IwB@(o2UpD82e
zLCtezJH1VNlmT>V?uGLAI*9Ztzpg@GpHhDfk}s97C;<6N`9BJTzg7m>qVbKgWIN2e
zantmeLw7FfHKxRa8}yR$Kc3tdlp6Emtg0Xr#=TPx-FrFHchJ3$yYUIMMR4pI0He5E
z9>4=!0KG5|az2aUZ!~w;1K!7Q|EmTU%Y8_zyF*-VBK_Ljj}!oj=Op{V9p<!OW1bSY
zqIUs5!VN>Ap-Gy^{dy0rN4Wu7P9EbTZh$+^#Zm#o3GN6b!A^41>7y-4T$wLSBy*P8
zkWAq=m_c_cr<KC{G;X*O-k;+Ba0Zvoxwt{gY3{pen63=2khZ;NxLJdtC6hav4#_O8
z`aLw7vN`WmusPiMiC}X%N2-m=<Hk+~KA(F^&&LApNE4J6az!i9cb5B+5;#TNFBFM8
z$4w~!yqNR72}|cW1BHJsaAwOPd67FY7Vr`-i<ShJxLC?#Ugo~<!;r3UYr?>lnz*C1
z$|~awO+b`$TPf#X!L9UxOeN<_FSjbLosPIvbE@$Wso_`!W~P?A+5+=exie(<8W(Ag
z#yZYb3Xyv5q#NK3+%zLdBX=|vW4X?y?ZW_XaBC?t+{BGK2+3y7)Ij5H;Sw)kgf}?}
zMQU5QEG?AY;$(DS<u;em36VRTdI(%=;}jG*Y3Cfig~7YrRa&xja4V^@zmt3N00!@I
z*{2|KpYx$0(gW_qF*w@At)Gj=Zcbl`AwA?0uEUu}oP%is=wt3Q{RU6CN=n{6<)Q^}
z&o~{Wc%E}h>1!T6T+Ux`<^`8p0j0g%n^IWn<GcevUUIe+hIz$x{tuF`xz<I1zu}?^
zAlc9L9m9ABI8!X(Zv5zRAnyGA@6hPM|GJwlR!{yEt((30^2OkG@Taf9;hlVwCpd3j
zNwpw8{DfL4_2pmFkt;v`_}}RB=eN=khFyHfbyy1Ew^9W_Am8Q#ksw~!iN0X|Sq&_O
z@MDidWH(=6gok_hwKDh{%4@FEf9xB^+irr1y?o9IAi{aupCP)Be-!{vBltpp%-4SY
zV|t56^3(o1)58C~7?uw3Dtcxg<Uid9k!ap_DJ;eCRkavPEZ_AV$RU0heJ?1EA4{*+
zc)lVMB8T~`V0e+hdoH1`#UJ4--GEQz2k2u@NBJM9Jnk4Tp}pF1{&fn-34YwqASd}5
z4)7w0pY<V>CiAhqFp<J<TaU(6{u$+^()dxddOpP)Ct-x?yym~#kl#qJoD4o%4Usc^
zGaXRN<Wnd{Y0BcKQcXxUzn5kxhyN%F=5zV=+rZ`V!@dS0pMSCjTmc`x5u}iRM$e+N
z{G)Y{EaL4y!91PgL)Tzv#k}Pk*gek&_kg>=AEUJ4MZTJ<X-oKj96>JeZWJ=S%pay4
z-4zob6N9-d<^QBp17*C7O3usq*&Y~L1wWQPdRECdp8!|I_h~SSYJLJO$!qwak#Mb+
z7yDrTD(@@-xyJuu0IB2q&O=!}{~pzIH}E~hu++#mjz-^gzGwhiZt(9>T}%^ivO5jh
z%zOF3QVTzpYHV-vLu5d-@}sANyTuRC4||&*5)S+w-i<;JZG1kh`rG*p6!^T$kEn#w
z4*q2U`a1a^KLYL^?@mVv?(=`PK-mLc{R(|uJl_pmH?MBSs2}p*nkd%)i0^jArT3U0
zyc|P&!mp+P=2Lzdtq`8^;!&u1&VNl`V(Q@+P$KLFzeEI}m+z;dz&<{LuB(@P$2a)x
zU-8!`LGm@9wh@hQ_#zz)_Ve5QKnD0fGJtav-nNDocOlf0-hUo~S1wvTg|<TY?Ikpr
zLv)AGNI8+6!tb>F^%fS>D%wX#Z-;JQ;YYfx{RBCs5&eZVQVeaEFm4jY6d;_XlBz&q
zH0^$agb7q45iB@q01px7+Cb-S;p-6q>=B~VDgPZRSX0I#ObDeI^j_gJ3e|)Q?k_<0
z3E>g26e09d$Z@|g`2r*(g`2l9Gf{$X0QwFHg%lh)DLkRWMoB{dY*<PbGABYLMUYXP
zI8|_JLt~n7i0+Y7LJ94*(}mY_X#aOwm`2OV3}KxMJUt_r6~VVmVHWMYvV=A&@6Hz9
zPz_3sP<07PbA^8?6`LpQdI~_k5KYm=0%3#-q)_<B6M(bAVk(m^65gDG$T?xpUU0=i
zRW-Qtf}TojF9=6yNo~3)NGLI1A~Y?9i<g9RQ@~volHP%dD?&&gw3P~{7XVl$7*|3~
zxllbHmMVn1bdOXDJLz>+CAj?r*Qy1547eKME2`wI6-xesrK`f?DNuGzsG&1fb;1PN
zMb--()gLvOgyXc-Y!v#BqV>9vTZCcX5Qb7Dy-C<kr=yyMXJ!y>5iF*H+!PGHAgzKd
z6eey7W9jm^EyS*YYj=b#dMIlXy2eAKUFe{a$h*S3^dF;i2ve3oS*MUsA78j9SXZO*
zzF^wZ2jBzYiU5OM!a6$Y+$}Wy2`?TBL$e|CNbnwtF+CRABGC9ma4QD)R9HwKL3t)P
z#DaS+h_wFf5i(an<b}}J0WH0PW(>^t2_FeC_)@sbViH~nC+YCcYoUKAMBWIDi5CC;
z!m1BoX+ZD~f-`QSuo^>i7u&PJd5GWAs?t+jxgD0g!~|Lu?hy5KBxk1>`8{-di;c9r
z@)5sjhY4SCBP9j>#HE7(_ZLkWP`yjMOc!u~*s}~Gfuf3D_d#Ok2+IEji$m!F7a~6B
z0k>QHmVTK%qKXzDp<?MvG=_;UcEhK=;*}gI4Hq5N;P#2Biy#sqZl>c&`^A~FF#1Sw
zkrW<AiOEfnJRnX@hrxs5BRUrmEiPIFkr;6{MJHm#i4|0Tdq_+Ug~M^8+YWdUFMb~a
zPY;V~DkDq~d!xY}5$A11U!u5X1Mo-1-v-0(F|o)G<hb}a1Cl31Ke|;;iuc2yEJ?h<
zgG&~Fx(Q1u;zmlPri$l3hcjv7vRMF}5_6px+<)ofRJtEdi!~$AnjvP=HFrkzy@<w4
zaZ)9KS>hr(LzgXXrqF$k=t2vVTyZ%)*Ym_<H0$}|h0_2Oh&cm*7m5iK2RSRs-vPWx
z?4O6mbK=DP;EKf+A|%g?mt<%(T@W{phti9pcMyhFA{LSEOQJCWvwm6p11S>e6>&)$
z`bxzs^a3gq^IpJUxyVxJphDbQ4#`Tf^cni9M3)!fszsl1Fkd6im<v)XHm-t&t70sz
zAFqj1HE668*IB}udXqS1GYmF}$vZGnjiOf{oVqUF7!A=I;z$>WHi^S&W}C%vbhM^L
zTxJH~P4Ux5P}(Y1Q2zXuXnYDSx5dxsWX~P(XbZe(6ED#=uw5Lw2O@XHvxi}!LmZ&6
zZ>N|}6;k&^Qw!DF-4{39g3JTa$rJc4vGF3zcZ=1uBzP!}e+=%C7_uAOWAT6Ve0?I?
z&>G~aSVudjXJRXzlY1_1iGoOvI5rJ#zYuL2!1ao5Uf}w~a4ML8DOxQA?v>a&1X^B;
z_e`T8^F|!?F=YD1;s}rd@yue#xT!oPaM4|5MXMGM)fEjmPgPkL`n*)1O@&XPs%x}g
z4O96Ppl`3LU>y3wRlSr8-KSbO1AP&yxR)T2s<(Fo5T)ur0+9o%1PWXpRBe8n-ha`m
z9ks9<quNKO1Y=cJPQV{hrBQ`XoXUP1{Ek-@lhVVg_iX`8P}RCY%@NhIQ6Pz``4oIU
zsv4jT*fG^RA3^fCDulz&bV9Y6LU$)suW3n;q<WVsT~bsVRsxW!YW|&0tEZ_>wn6DB
zm6k5AbQRMBa$5B#1#B}^nfKt+8P#5Te`cx<P?{)9wUFX3*{TkzxXn==q^(P?N=C8K
zJeA*X=*w3%jzwRA3R@oB4ysMGw>zuK=z>U*%9k3?sjh@j{d=+MS0zlGS6NY2?gf=6
zoyoqa3T%d@64kuFq2`h*eJh-~tg`LGV6LbhPXsAdg>Q$_GS!f8V7^?HN9HS3c5%>B
zsVWHtsZx0+ps`wYfeKh_R9ovIS*vo31-YuqqQk4EYpRZ$Fj1#^G8>}xszb*?8dRUt
zQHDm<&-X#DtM*e;@P_IQ1-P12hp6_tS@mTYl(wjL4x`&a<&g}fttzWe;L|Nt5S5(Y
zR@KpN|BlMX9nQ3=zMy?ryJ}S{0C!d9>1gaQshCBO=~TU+4sG{Tlk8yWzDh}{iU+Ep
z(?Pma<8DA(w`vhRkRPg!*a81Y^_d#vvC6v;9zIctw7Gk#T00Mu_e}M>Hzw%0YDglK
z^{8T}L-K`ckP|%YRTW#qZl7xJK1jY)nTlMY^p&dA2{Nx$D~Cbb8`b9qi1w=n)B9jR
z^|}TkZtBlt;i0>_?*nii>QGvgdaBnd!Fj2_q0+=1>dO>?*r^^h8qRpDliktiqt2xY
z4qx>{N=y5xuTtrizdDA}V!PD2CaSv$P>-jyXQ29JG=M?suc)9SSRGXcnGkg*1#Wh$
zv(`dnkJ_9<_o3={C>;={K6D4>_o_dn`zKr-(g?CoT}su~5$c#v0N<}Zo{2e(RC~OQ
z0Y<6Ckst@u`<$Tcp!%N>3K&JJy&nM)qdrN;pkvj+c2ILj?L!Ao;?$lc;NsPL9{_P!
z{pBoh3F<VIZb^@*^|Qexst3`-<f!_u|3T!KdSeA9;kfz&1+Px1H_%@8r1}Z15tG!P
zJcCHGx_vZMr>Gk@QvFM+`cEaiNK=2-4sEB@No&!WuI_jQXHKhibmSvLy~r9OXVe~B
z(U_^`8o*_#>;DDGRtI^(V2-+}3b<T#R}GxWQ#Tr6Fkd~FvLFTO8L4P2R7V~`<5~5~
zgD_O2mc-He^SnAb1MCI$KQkd(qMkAZ1}~{Me-HOBt84NByrPbzuQHaZLq9}cnc9sm
z%W`!qt^6v~VXhFVR9~P%)GGD&bgfsbUr{o@M%}U#eYI*&ijiDZ&z}x|uc^PG7)hP_
z^-5?l)vJH%MQellY&L%TM)lZW4CcD}*DoQ{q+YfNjm_#z1|lu$iGyJ9rur}yx3{W?
z=Ro%@^~V8Fb6dTw41>6%R%qcxo7(jw0NT|<DHL{B-D3u>Lp|dLBs<kNDX(--&Cvgy
za^IwO{R8X+bpd@xyh}ZHHAK7BI(iL0RR3%VnMdlSWoUe&o<s*Ko~p}f0r*V)9+g!-
zSI?XPT#xz-9+qCHkJrNAUiA$6Vfxe)X?yZgZBJ(gU#VY2!~ARY-?iZ0sGltau3v5X
zqZO?K>Y0OJ$xV|s4Qkvq-n4%8(1dn?cxqbKpwCO=RSDfYH0!7^aHqyJ8Is-_n<9w#
zXarh|`)b-gg+V_}L<k!FH7n_S>@H3EJ^%tVbLjtr2-J+ehQ1&T^WU~eGhm|g0wJ0|
zpP+TOMndb1JsS5ha4}SKj+U`un(36|+pBRihxu?#IUNw#r_oTMPK1V~qbB<`Zd6Vd
zsd1pnktj_VU2F$5(O==0JgDJ+gZXGpJtfX#G>fP@BvunY4csBk<MAe#kJD&pf{oW)
zrTW6dnyECV1P#6riF-`*kP7w_HS6iy$VWBfJ_C15^FKOHa$GaL7nV+Fd`uYHNzFM6
zkR*+Z6n)8>_vvJ5iYAO!?WvlAc#t$r6`gK6rP=)zyieDh7)SfR)0!AMgPx%&rV5`k
z8lG;FOichC)6LS%@_;khn!a$1Fh{c?1G;lH%wgEg)9e@wT)xJY!w3sBlm9_up=KGa
z;m>NiF2GWeW<oqB@0{ka7bJ@{k32xmYuxF~`~{7Reh}`zi<%E<<yfNG?~l=6(hMAi
z-OCy-7+ze_%qxWXQjMAxkYyU_zYr<cynPCmDm3rYmZ?%x;0QpKrsDuytJbWda>^P_
z89l6PH6tux@T%q*g=ns6EIlAur}>4xNL#NN@(6HKgJwL{P&aCxQ~Kn(=JzS!ZfF`P
zRoJ9iYKx&YYZ58a+M;QH8^D{IP4vUIYSPC*@|MQ!5gKo6w4>qZ9gW)%m~Yd(^&TeS
zv1VH~e0rjp6%W8uP0<%{=9%WuW{~HaY<iORm^6o`fxgfjq!nkcW&-X1`ZRyh3GbI0
z|9j|rrTK{}K3{7*s9@)fW&!QW`ZaDxpys5*UAh939DbzhIK|=8hZsbfLm_?c>y*Q|
zaCnjK@Od5@PdiwIpfSVYE86&FI?PH0F5AJ>N+G-)hmV{gljpF95=8k9^C`nw;P9>$
z{h|*2^pZL2aDOwj6*<HY0(Z_~>k*J*hXlHw&pY5&$D+mI>m&3_I;5t-nM)3vDX4kH
zp>rZ|r4D~oLbA+Z?NH##9j=c9pu*vI6NS(#9oA6Dq{`ti)y7pjgi)lm#^D`W>DD@2
zqlDvChq8;{t~o4lg5Pxx|4_c9-r=GieGLvBlnZTi`0+eUTz3eenZ4oA=!`)$In@3E
z$!3Sq6pU?gko|zhn+_o&d}?zz5=8f3hr@L`RMzR>We?GN4t<3%f8XIM9i@HX5Jk6I
zm%||XmPxmR?QQ@bI;>j`$;S>0-i5X&4!7yl>r)3K)y+S1`11`KpF8}J29X|z75(t{
zg@cnd8hagh5Bhl>YN*2PrNi)4`da5JhgCsfUppvDVB(EKCKX8ZJA5gkalm2yWT<h|
z&UpypuKn;W^m%BX_`s5<R+s~AURvcQ__RYi@d-qBYOVgj(7d%zrlQYB`xj;Ge6_1p
z7>l2_y$TlmwH={o+@<{v$+ZR20PWGm7;m8VH(C(|X$RE-7_43I0;RjPp;RTgM|+w+
z&Jn8pmQoF2+U6f&Vz2hwR{VD1+C6>{*{4-fs3b!Bb$GBN%bWJDhU5XQ4+Z-UYBzlh
zozdEWqY#PFZlsrZtadYfY2c7nPxVys+UP_~&|&TCWf)+BHbw;Ch;}}GX(v&;=p=kO
zrk##@0qF^CM>^a+skNuXPO?_=6G)1-ff87$+UJ=to2IQc(amv6`v+~l)3v>|Fp;6P
zqIl66Z8~L;Gqvq>YiDVP?SdEC+JzK4&(Vf)FrTZHe+o5u+BW(L^0j_+GZ$#*)}gUb
zyTJj2IIDe1;fNybocU08PHP(u$zpA76dKQKFKB65bwL|OSHeZDR|<e7+MAo8=92aW
zMOv<C=QBW*Y9%2+lxfuxxK^&U_!L})_6}WZmD*|!lTf7%Ye3^m?Zo3y=I!_g1?PPo
z&r(p+&(Ycoec_Joly2GYSU_?31CIaxOkwpH$J}>;k8^yt3I-D$m(a8wbqucqcg%4k
z?PrcVzMyx-3CDhV$e(nKoenRO9LLj(HrcU}qA)3rFY=)!)iH{euW62}>6H2@$Mpu-
zO?Pyr+OpG*-D9EijN_73z-2nV!V}aaEpl|E&CWT;kEx`m!tpH=v{gFFS|M8HSokCC
zRy#^(K%~Yo_9r+~>&VT;(5^bpqsZ<x$Kf}iyUy{~<AB#YzOxp%21o5#IMe8ucN5%o
z$Jou#dBZX21K^q*J?{e7?C2hgMpKJp<`4jHI<B1sr&=8~XV7`ek-HA}?>N4%gzh%S
zupDUfbSiy-MlYw4^w!_ul<@~}JDtAY0;N$-zs?2jfKxr?a1J^hr^S1;lQpFeW1LFp
zI8Ln7-2d{rPTOf?9PjiMomNdSIV~!Nnq;SW8kk6N%72XUraEm<pfk-$LA%~lPE#oY
zk?xdq5!`8~V+-MEhSREGSSoPZLh1WLr}I0|ch>3m!5~+hE>O)db}CCi%ABs!cDLNA
z_Yt&II^DfWGwRf356K!Q(>_Od)9mCK1{YhLUeo^krc*g(3|gJs*22<lC)?#vbH{0h
z4CI;9;N@uSak~BuBwsisHepJ7oo@Y!->1*%Cwd;gayn1f`fDd!Iz{ouX$6%s^gA_f
z2i#4!kRl%Lx=Ce_^w8Zm&4L@Ax@I4Adg<1!2ic(;)`HRR)G2<1!#+AG72Esj_Sb{>
z>AbgNF#fv8cj5Lf-A^~6CP4T1d{_$9o%jk|knSF><3e;#BLUy7OV2^y9-Tmim!Z1f
z>VXT>H8D`OSJ(6*l{JRz7U(eEeY&s>=-jXCqmXc<ZsU9)4(R5_q3@t>H-)JabSw4f
zJE99&1xrVDesn<`(@hxyazeLDi-9KTUQ!?+S$8iFA}PAdv|32j6>WgQG~Evh=sczS
zo}L2fx{_Sl)|}S)Q}JJh?r9dt8D0EZXv@?+{27ywrDN^Un4_DJ2fM{OcX~XZ*D0!j
zzo6TxgZCG8$LV2RqElZ&<0YMhu8Ye$2fATPb^0HmrA#*_27To^$vO00)BRlmN9%ME
zdudtKqKlylj+?p<s1~+WS3M1W-_rHn!d%?eO_>0LcXS(X1K*}=qSE1Z-L}7==B_UH
z7|eI*mZ<>m)D_W9c~7^2suu3+`kEm5Ko{-`FM<bWJYq2l{24xF3yi!scP;)N@eqM&
z94lsW>GtqqKBV(cJDBNp^y4$LF9PY!wEhFmhZ#zXQ(q>9UNU~n9{LgdnO_!|4Kj~p
zYH2Nhnz>6QV;M{&ZTinJrPJVBCgV>RO%^kLKe%jWi7#~KFmKVjJePTJ8N`&w3^fBV
zpZR+QJT71wH(~gN%&fCOoMoy%f=m%})*swCW@ZZdiW%2609;{oxLD2aG9S@q){9+y
z2k;&2U@EZP$!_RHqc{5-ovrX;9W%lCvISIc=f_rG!#MrfwcF9S%fyy{2}A%Jm;up1
zHf1Gr2eI*X7*jC2gi4A+*i8rF#cp;fu6grlw&yH{UCWkYyKTNx(na&_FPV+dl6i<^
z)C}m}E3u)ZM5H8CkV7~AOgKfwlb?q-K=~KHgg|EUGFm-<dBl_n)l24m4C6nvcf!9-
z^QmsprH(E_*IR*T@nIIysSJPS13Hv-hM7~1SuA3_hy34f%7+a>cfaJz;V?QNDYt?{
zZf2%v8iAR}L34=NkF*(zwOCAtY7SZaO!<j8i|HtOGfCquqAAFBQxRSZnY)S`babR!
zabgOLJy&e1faq(*)T!V+?XFV@$<MBgiqAsqLMeW?&u-8baM5-nH$pPOE_xxf9I;#V
z4!lUTv!v4VqjnaQ8$M<?loqzf?K(DK=qK#%RzR8Qq}{8Xz$e*#<`0r=w_^`xC*4l|
zKZxeoP4@#SvU8XTZI|pE|A3>FcJmei-(Z(M0Huv~CzGM(y4`jT+zmV9P?&GBOIiie
zZD%$ck`L{guYh}Gw~AtlkL^5nfqP<i_9W~*HQCLj5XUpSCd$q}w+p38*d9A)n)nxX
zYh57IXIB^n^DpiC=@ItI?uVynd~KISA?r7GR<t1Qw-dSm7_fWz4s^TOpUVYtx8Hdj
zk{<REe&D?A7k>sVKKADSfb+H2dIINXZ|Z&tHU9R2gTRK^e|HaLw|&lf40MluNF{!*
zQ2Xskup4Hd(+q9#_N$X<X6=>qem`cvvJ!w)`>sJ4M7n*`?-*f@{h|AiykWoh6ZAFN
z$CJ($`+p9A+_aBf2Xfm!WeWgz?B6!gPN~m+P&cj}H{~-926riIX2D>9GVwY{gff3H
zEX62iPln$|l&dVzn53Nc1o+d+Nx#EVuJZl@_;gNri&A=*m0!P&zAEL?F_5fRUf%<*
zMQKm9+wICP<6)>vS+oXbpD7Re(_-V5vMP=yiu>X+h%eX4!;&A@y$c9`ZiP40?BdKR
zb{oKrO93E|>nKHE5VvwYW<8kOP!BGIn@;tXySa`#aAptZ@G0C5<;2_Q3*%M~2W~GX
zr;&woUe&<u<6d5(V<qw2BD&iTbAMh0B7qx<P%w&qYT7ZEiJY3E2}il*9Z++O+fOI$
zQS+mQ<O%NLagdW-IjvlhxGfZ!Oy)XbFtilz6h)F!xvuRnn8vx&NsLpR*GqVDnmf4{
zk{R3&x9I*m!}-ybpUGK$fzB*$xDQA+r=T}$4i`zg^IQ)93o6#RoaNV0lg}NeJ!Anl
z_<yie$esESl4rRK;jmQ1)m5PJ95?HI;EK5&doU%H9DfKys^h}9Lv=G(;sZb%_u<>{
z(DZ;SrTVF--1hZoeZ@&;L-%XWg+8eFhRgW`_<nBvdGrl%t7t>)#`n?(Gj{PAmJkWx
zJrbZhkoW%_B0>D%Bq$B$1K&a)ib?2!w}-DKM??9?flwC4&!yU`z5GL}g9tbA2)yC9
z;K#Ls#Pab}7j%f<69X=eztj(H@%$iqnH=UbZ$M1~e>)al9N~Q?!C)ePryr8X_}oM2
zJI*Ij3BU=S`xNtZl2;ss`6PY`)e0r^t2!Z>!Y`u#!7h~-D07p|o4Rc=-W=YW9>@87
z<PhjC;6EU8nKxeqHCOngT8NhMAAAmAIX~zlaCQ8>U~u)khMZ~Szeoi9I$uwB>K*=H
z9h_<7FVLE<ogYnM`@8(t-4N;EH-}<Ko&3KP;kd`kOcz1#^R{IE0l&5xz%JhSClK9y
zx&<sf<dt8*i${F*VQ`Q6-`X+VPxyCCQ1g^Gdjc<>^Anc?(8FJ+eBBE^_DgWR{Mw};
zeSGq84DcmC_!%61#phSR&})7_o$GkRU%fyJ+<yK8S~U;w1MgwJ+yu+-0dyBWkB5wh
zu&fwLJq7j^fL_9gbLa~YRt!aBppZ)EXM%+6JV*u$=L}G`TS%e=`yOFf4_pfsjBmlw
zFySoiQV$8AQ2;DX=p~VOVdh2JRv#AlE{G-w>;Wh}BCMVaE>ZZIe$k^sZ6kokgxqAf
ze_RNmSwA5xO$0e9JiZENl7t~`a4lKbOq<;lVI<y*C}g-14UtpAtWTjcU2ty)cUs7x
z_iTo+lKRdF&#}EVp@N}i4S-p~09Djv3ndiG%n=-h!C<cNlM@>A1Z_OL$QK?_*1kY+
zrC+pA_;n^cJS$8Zg~lRb|6BNdDg^5Yn6DImH=wUtn3Dutjj&@F8m|fK>DvT#!g`v@
zE}=XQ(`D)w3Pymw5?Vaa`C6E83+CSl2N%Lbzwp@tG!6)h+<|ZtmkDsxUCgEZfQLA*
z4R$@niBt>bCC=RrgFD1t3JvZQa~Gq}TWlTyWj^B8_o2mC9PbObpXd?|ZkOmz%b)<0
zXq2NhQ0$?KnjmrTJm?M<`$wWPL=3tN-Mht9%1`bQ^>Q?ZiZ}kon8L(+G&6g}-QnQE
z#nE0+x=$=A1Uy2losY)-;x;-%5h-Txf%l1G_W?8>6~|KK_?Vcv65MgoR7#1|6Qa*%
z=sqb<9|e4}_-P^RrijD)Fs4+o>|fy1#JlD2;*@9#g{5>+MVqRak@rv<CQTdZO*P!7
zM)s9Ki_b^ga+s(ewZR%DT1T}OL(7{_5-E7u|H(VY(71b?FYRsijk{wy31GyyUG&O{
z9QR!+w55-;SOne0<7PNQ=KQ#{xezHGH=pkGyW^&P18s?)v2|AP6n}ncqICGL+<j>O
zEp80{-n_;dUi?1z9{zSYON+HF--ST^)-zWDbz@>EcHqu*wSe<5F%M!O;m2%!3u^qC
zN~$^xU~*|S8phPoN#DK9y7lnqATv7_TB4chFKOgVs5$x)89$2h9c8?!1nL;G=|@b}
zac1qO(0Pg(7eK>dqUh4dWh^&<%VQ4EO`gweX}}y6Fs8ueU@tKpA3)|ZbFvXiuQ1gu
zFj2}F&!g`e<MIKt)iH16n1Fibg*QwzFh+kgwldk2%elqum;-W~`G!J&cbLkLF~T;c
zlS<m#ncKtQ_FcxK9eo|l(*fA+WELMs-(#lP^a3WHFqfl%f68p9$k;RH)@k6MGcihV
zZ<s-pK<H=Qnt=%#VCE&k3pe(O6vUnNszIX%JM#u~d$LOwL(+>qNLqHVc}3uMvURjK
z^=4Hu5b<H3QMSmJ{l*sq^kV}K)Be++y*VACyI6n9O$M-EJb=T2tY!>I5Ze<563oWZ
z6EB2aI~v?>_Cs1R>|wWy&=$)24TbJ7_Ocuzd)X+e8wh7N{)WDNtZ^wUM6j=>z|sBe
z|ESJAl1&JMPf={zYzEK21MDpdKOJOQI$xH+;wg&9Alp=o#$>jNo+l}+X9^IhtbGqe
z(%8I1Xv}6;bfGba9Z3O=TsC?pbmy_3{|vkN?8Y5{UtmY9L*GR<G#HX4tl$Xl5_`n}
z_+@tXJbM0JVL$i<ou%yD6zIOr7CZv*1{+G*swVc#D)cq8(`N(N%KmmAz&q?;Q(>Zw
z-L?xuYiILD<4U;8{<WBXU$%DwyzgXn^n$s^2HB$TK6`>veQpx#Z2)*n<P<Iol&pFi
z_Do@tQD37qN)p1tV4S36EleDj1X8)~3CWxzASWdchQo^_$=d1Qk|kqYF!?DGz6XuD
z65AG-$dep+1B3aJRqw*J0*NgJ*a{`*HRwAld1w#w=Om}c!9uZQIYlYXOB7Zh7fccv
zcH#K`#Usl8lt|7u0beUQUJfs=OXduLnp={MA?WLrY}BLiktF{j052qq%%Qtq@^l3N
zJI&;KFl*js;RERNF&i-xoUfUlj?w#>ZJ~X-zgepYe|MQJm<ev5*%tcbO@x_gF+Di;
zo2`EaHIZgpSA#^E?V}vh0kgT^LFS-Y<wm$4W0pWqh*+~O%8MN``-#e;<IGl5m4Cch
z??31}Y!+@uSCAP`MF?qTpV`6REVG+bnp0?IJq<oxGz&Qdc)1z>4s>2M`_e=g`3<wv
zQXp=ddA&yKeKS8B$UHC`-2_CJSw}axZZkRUx*nQI=oR?LES0{(_1NrRJpfP4rY!=z
z-z;@5ycjU+=!2x2w2wCZ?ovIyRz2{MJGka4ed{OyUee(|L+1|Zq!U!O?v4K?2c16B
z8hWGoO2ZFBo1gRqRi61v6J7wZOIrRf`U0e}SuhbOT}4G=;nHb4A+k@ZqT@9Y(zCJ9
zvR@ia{zgjKAeu_)iR~Z<q+8-387+0EvdS2#@n>j>mDcb4udGWNkpM)TbmBHR6E9sz
z2aOL)^C$_MBz>zMlaMS;rN~-}G;j*~Ql+abp)F0?ZUu4*U*Uv_bm_`d&~jRuMfKZf
zq;tk$5;CQGXj_>jO{4r$wsgr&*v*mV%)rd#O8@kuV?BA&lpoQWk8g)V%|)r_01TE$
z+bAb<Nov;wgO{aqy+N)>y?+8J#rG9qw@g}750P@|VLEbGAzd{d@G5C)Gq`H0)w?iJ
zBRzK!Zr4iZQ@-=6^ow)gu1U|)nW{SJrJ3;8R4?7Q0tOqTfBy>I?b0tP;c{2%HWu1C
zq{@d7?Ub5jVlell#gsC?FMZz%y1S${gzuJmg+lV7)cXiT9!a%yc|De%sD|VdX?+sx
z4oJ0B*yLt@%nPo$o5vLc?qNPV2&z3z=F7LD)60C?c;I)K=kJA!-sX;PL)6E-_6c<R
zn#X?y&d+?}RRI0XWn-Xpm-&uA!3CI)W&qf4USkO@k>+O#FqSCuvkxG0z<fX5h6l~h
zQuZa<+<h$!#+Waq3}>wQiU4>RXKtFA58d(Rb6Bv4&7ZhHTY`D%BG^4*-Wm&%Xs+nQ
zJRdcegaUZXd<!L=ip;CN!w-ATeBJNBm6{t0;C-|C&2BWdm`|bA$Q$!TwXmCLF(d(6
ziY=aPgrV~mO9Ih&!@^LB#uf{MDG>O37GDpBZ;vhBKLcQ|MPfR%^;wiq*vZ%OmvSKd
zEZ?Whcc|s}r(izXav{a#QY|Y6K_u656BR!cTb8TPc*F9>H8}d%vf==AddrqmQa)66
zmlg<zWDZvFB1Lwc0_vw_CpDD+xFn0ACFo_@jL!h{mlx6b!$A4-t>A*>7cIaA%lFbo
zcDH=tNcg))K9cI7!{lGB18%Q;eh=K<FHijkl96(Q4kA(Vx!n*sD0kS4pD9{iuZ6)l
z`RibC@$wQKaEImT!E~%AQGQYm{Be2FMsz004fVjM%FhPD;ZyRrm!dCS{<8sn8S*3h
zVd9K@IX(I_<yYyt%98J*Tl|XLc`!(s{L?B-LZy7EE&6KYZKq-Bs=SoGMo}jpWr7zC
za@8y-yCHvri_|1-l{-9wjEB`iDw^`LT6-DXPOBga!TVSZb;fiDTK#1NKG<qp8c3*B
z+bH1oS`B}ODT%O}NC(5BtPVY+<skkD`mOkTNf70YmUb<G!^?i7bIRWz`2_!7evQIU
zD=tvY>krIW+JCJaLA7?Po>9HT>VG5AvF5}&nEi1Xoqzqwg>si`U%!RF*Bu)Hlj{@G
zG13h`D)9HFD#{5Og}*Ucm)Eoh-;%Ni8nzA##J^o@zk$xb|E9&(Kgnb8?|(BbpvTmv
z$G_c~4+l)Zc`zHPs@{`%<p^W|W2%L>fs89X{(~6PNN~YSK_o~7v*=@p>}RCQp*@nB
zN%?|gX45u!b%yzxqVWaHAH^8cMaF|x!4-_lUfSQ&v`iU}zoXgfbub;nJ}88~Sl09r
z9UMHwhDO3z9P8T%PZQaHXQA;Z`_p46Ok$Te!e%mirx08Un`MW-(`=a(Tn6h!N%=Eu
zl`lvp`^RR$^H@y?0Qu~(_hF)dJxY<bV%Bdn%%5kaS%6<)KP`vk752J`YRgO6II1<P
zVnhFhOf|c@7_Qf_<7v@U%jWSAX<)BVrCcMc+6(SFdz|VpZ?fmiz_qfS@8GAn#r9Cp
z<u?230^oPpZ_mSSCtF34(0lAWDyw|R{!)m>XKY;<0MA(=)dYMG`z~EEuUMyH0J=%8
z(Ua||%pnl-_*{Mm8L9s!u%CIKp0NYW4>UV&?2OOhf;;<{7e?a2HW1d6?aqKTFZO&Q
z$PV_90)0E#pD1kW%?24TA3m%vZL@vZvH!hgP3%&NYWlNBo1twNE13?X0qh)lK?bq`
zk6|!~-JpX=1beIx&hBSNrlT*Cwa7u=5q8UcSUSpPHT++wTNp$8;H6tvLUtKLH}Cgi
zE8xqonZcJ8%V`7ugWel1tQ>xu@(-&5pF(tX%trXQW<~+D{kZ5~0Dk)8LwL0ILt5Fa
zE2)Ii^+Wv7zG2Q4$ZuRup_Wa*j)fCH|KkPJ@99%vOs`*!_AMrQHEyjKfp#yZ6~`Bl
z*ccyzww=uC`7|cx_E)eM%$PP*K|X|8&BLSJ%;!UZh-98q#d8$1_byyMz*rQ*g=l8x
zUuZnU{7z;LGrbCsM5dw#jmMb}Y3-fFJWPV63PwYZ+)5^tDle*-=o(n6W;~w3ZVi*a
z8C*RxYBJzW%rcV|26KzCqRamt<7$r1=Zt+mfG?TH*CF$UaijXL0VeSa=yqpA-hrBE
z_G}OuGuYusaQy$f>lb>!W-;G<3`{n&bTiz_VGa*KUoKOnMqeJYn(7SmnS2>WRltmh
zhN40fGeA{sml!)WJh;pRTmb$Gqo#|al*y)aR~fUI8q1kY9v~IW6e>2UWWp&ZaGQBN
z2{U$w`Ht#-+L%pLjnmD{q=4N+W+%;YFXKv2`#vU)A{!p8BokhEvPWqx@5P#=beJT7
z{eg;y1KIa}fZZT=`DKXiWA8?RM6esb#pLd1|7r$_V?#q>KAs&;Tam+T_d{q)U}OIa
z@v*-2cuZmQs46Xsb#KFvve~+9Sju68E&!g(y3pp~Jo{ZU8ZWTFnWBNX$gcbuc1zfP
zGFZiqT@T&W?B@4?s9~SeBd?adLK~YVc33I;n%R#|qOXM=MOW%gHup99T3MGdm>_(r
zZyEaTvqewQ_kaze@K6`)x(KA3l^Owm$gUg#kw@&pE0hX*%zpVd@K4y*2srhW&7~OI
zGxh=PmY%bdX`Xx71OLFa7i?W89PMR4`V&LzW4ows_9gpuEx1=~3zfgVW@oH{vN!Bj
zD*f6e`Mn*0{gOmlWyMN5spce6vX`7mmF(C{`_J=|kacKnkR(w|q)YOn5uNU4BMne`
zz^sJ!z5lPaEAi_od;jM=_kM1XRAelpVMf+L3u5pZnz0*8V#bms$r|lqhWXT}2_s@~
zMn%aosHB-Fd$zGfmJt#{wu+hTZT#Mkuiu|A>C^i@=RDgvpL_2)=XuV(()GsO;Y^Nx
ziuWYt=?8|P@RlAw4|30S-?@M)eO&g3Tfha=9$p?7m_jadUzvP)yG)U3;2co*Ob_Fs
z>4AyngQdh|w$6vqr=}&dq2rmU?Q*cbHo1Aj=}Oa2tw6mqdDH=Gr17$wK*R8BzX!n=
z)9B}X28=yhh)S=<*3dE`j_1{rcI^Srj8uO#cxKxs_#5(X6x4-g^XBBab$Od>*v=l1
z3YVeTX0#_l?&AB=64{G$UQ6X@j_9nC?E;|xSJ{YTVDYm04yXiK=!Lq?vMXmnw#Wh=
zg41M#C!F6Ydv^q9x}3~0lq?zk9L{9Rl+jSVSDsl7@qMzO2IBkW@CpbVke@8${y!*l
z_d(4e*>gU44$G$!RE~^24f!K7k7or(<xNgCACs%cLicfbhVuX?<X*nd{3WY6l6O)z
zo&}auvXleNr{(NkfHTrj0?x|43!yVt_TZD~ob0>~UYwV12;`Y@LHnJ6;01Z~I!Z6f
z{WhR3NsnuAra-pk?Swbv(~;<}LOHhyEZvm5c$R!iwtfsRZp-}bV0kD{@_w;La{e^1
zJeGg2f_RDa=jdRm+&BxW%j6|~D)WhKpn-ZSpYTlruXWKm<GY7`;~Pmfh1`UieUx1V
z)&sP7C0KK)`#ALMG4l3CWB#H^yy8DiYx5zOOOrW3l1KmWbn`N0PliANB}Ibe9`#!S
z*TS{ZS+!7#-v%wYsR`s523Suiw%q?4XfA6?q(BZ7CQ+S!Fujp>g~O3#TF%+YO*HKs
zyxUCP7U0}M>oD5kuH)4YR(_`!vmm#P=o$pJ(|Ug2^A6H^7f%ZHvH@o*h1>#X8jZ{V
z=T5rt08}~=f{td~u6nEhnL$7BdtCk?J6>65QH$}Qa;VQ%s5wGkj)BtCWXYQ^&d^sk
z;LKTyF9u64W%Pr<6{-k;`Fy(08^*6v>~2uk$l*BTiYU<?eRPKk_>qCTw1I;;_b8v=
zp<^y4J2NEilM6pb`+y1pA^4D*pM_74=*MyBi^tT7zrPZC!=d6*dRrUX%4jLyq@Pe~
zM{qu+=zXaBhcbT$yr!i*y?sM<__5RqO6QZPl3wtlu8Ow3LSZ$9od!#dnOe95-_p9(
zsQg)L;)wo=*2?&%xk4+w55ZV1m}AAiX|0-q1-Hoipf+k-IkuCmt>H~#JG2K0@F_*>
z%t@?2wG__0WNHp2;5?vxwhVAk^X9PN39SupoBK=a$XlUKYUU>KV7;JaHU(VN^5?_1
zOIjH3L%Xb<p8(dswMExacSU>0&t&CmqgTQ1RqYdgtHd>JH-A6ZwQCVzDbVtUz?mCb
zz6RZe+N5&S-PG=`0Nm34<qa&iwFx|^7iksyq3n*9ZRU%;So@ySn)kKcyr_Jjojnfo
z549S1w6{dt$@8O9Evg1onRbcCpC?+{HpoBKO3MJ{+N@d-c&0U)2;I*$zs=yR(Jn<p
zb+}%{TVf;hr@ZU$Cw&vMEYdy0P#39x)QZ<1QTnVjG<31PzaA_t(T5L%`^)t4WpE}&
z-@}`Cm+L-!2CmR^_{xdZ9p<8LyPm<J*+2E%!w@*27aRrWaedVlK(6k#8-=BM-~zC`
zHTgV(7mE#tmZ)21^x_Q}%Z-X7{8-OgBjqM^#~C@hp)}qIS_CS=D4Yiu*Bh0b-rr!X
zDuLZ3qne)`O*YPPENipzG2RP?)w-L`&KTW)LE#Q#Ht!5fF=9DHnraLxhFqGli{F!z
zZqzyg*k$y@_9Ih<5xNkM)%|Zo8SM@3(a!|5k7;8Ci({wS;CNh-7aaBS?*OmI`}PIT
zgi*W$d};+hhcT^79FC{I@yGFum?z)~itPse;4t2h5u)=q6*`SyaWyx-7;Osslw0;g
z+FS5P%G-Q4N15e~voIGU-%dg!mdkQGs97P~?Eu8eiu>?>rOc6N**dwM$I&?Xj<4`|
znUf1hkPG>3t?T9RhfuvsdLD$eESbnT^Mf*$XVAxFCO=1hTF&G3SDutEP<BP0*$W?U
zNOSZskay+Shw!FU4lG6KD;ZQ9O2f&*6$V#QBxe`#nu{g>zu{z0GZe(iQ&G^nQYJb<
zbe#;~4TEtq@k_WIFUND@I6>Cx3Y(i{pRVBCBAfE?lO`|nq-UqRmkI%My6m0x-u3aE
zp2(JM`-9pm+w%smebTQ4g~wzY-cfK|rawXJa^?N0pw7uu2Y8V$9XQZ-Rc`GCZMWt8
z6i`L7b`Uz}jvU58w7YVu2ehP+2XD?vCE{x)jW!KH!*`mg-g&U5)0e!s*+mDs05Zs@
zF5nN!<;&wNP3LL-ZR*$-@`>6CPOm0uzfVKmM(x}4Fp;c%&R5wc&Cdx<+pLZ0jk+z`
zKdm9RRa?ks^6#2u5LmWpf!rnAwaY)j-yNFy0H<SC=+&)J8LPMDHRDRXJCC!g^lW}e
z@mGED3dpb4uV%rgHTt=+(7jf7+>b(~f5qFCf735)0<}&z{R@FOy(#Cf;`LCTWkeaf
zhjHtT?t!q2*I7G&`qK#J!FP{QWNrY7Y-2$cT5-T={0Ddr8J4_6$}wKe2kTKIuRd5`
z8H+c7bD4z$Z}LvHIME1&CoTH!2X)56v=Clgv8dgU2U+|+CU;vXd_wkF@T;8kYOuYe
zz}0Z5f^0d=6s_&Lj(Gs$Pnggx9|5+nJ$9l?2B&@m<KLXW0^37Qa=v2d_kNHbHZUE1
zGJHW8$~{~gLHmd+TOd2`pW#sIwXhPk<0Co8H^H(L#}gg4qI}W~ex%HMktd{Po^{6Y
ztS6tsdhn6a@IS<B6OVlh60V?PVO&p$Mad=(sQ+0C9-gA*r2-T#md$v%wM3rbWKODF
zkOTfq*@<`a?UM~J!Dx>3;!w+9(q}yibETUN;F2ul{<$Wb@|y9M9L%xV`?AOaRGG}?
z4ddpQvc)L~*2qKraN#0KX%E3AG~MUJl*PVgHhk|}j;=NJ>z)qQ&}$ZG_iNcI6kfcM
zC2gRlN_Oi3rPZ=sI>g_}&y(O&I9=p-`7EOE8iF&Dnx2EEXu9+x3@xUZ`(XLiOpbp*
z^J;2m12T<1ng;41b-wpuuAN6Zhup5w?O5ozPScB^v4C#dpg(TV-xDEJNCP?F_kdP>
z1<r>gI)W;ptaI?Il&-wr%RqB^@%#@ta=fI1A_k!am1G&i`TwO_UJaaHuD#^w=PK=G
z5E{8!`<1uOuhDj)UH_ZA_2Jppb9s*!4lm?Qp7g$yy&_=qmAt<eO?xc^I7ahE{@fFV
zi^$&heX}e1<XlEybcNa&TEny4HFWX_#Me@|nU_wAUS30KA~lGCd=ky{1GSMhb4MkU
z9|v`J&^CUcCxu>ggFq^Mv;i(>lKCAh?WWjApbpXr9y1P+dlfAGMN?lw%Sk%C5Pg(K
zqd7BlfxhGnO#x-M1m_KMyv^~SLi%?mN^g<_FY#~DnjNUTO(VuZu!!bz_WKUyU55F)
zG^Zip9^K+3-!odv*}doFbOP{##{9%xLT{5H_lkb}7=>@>Z4fvs>GK6>SrxTz2JuB&
zKo2+*sXcY%@i$33&bi<eZC@FjIjkM&gvzU0&KqdEt=W}9%@fUm*LW{A{I{Jvwdi#b
zoKbpm60|9OWM7y_(O(Y)bx4227fznu0Ve`7N+Y&|^R;f@0Lp$b_2!$_8q>_jpyEvp
zR`Y9Jl1-ltMtirJ0_UML!D!4;lMTjQ4m&3rUL3nmGJ<Q+Guw>~oDfSfL^D9Dagbvt
zJB?JnF=QBlg`oBrF=OCGmQg(g0(*^{7_&_KjUOB!aKLEU5w0CFJRieej&Y5j8#W&?
zzPE+^F{6J|$R9T{>p}2@v5m8tr;X?wNSrg8a18Xk;W-x0<QerMAb;72+WcX?+yB)T
z^!Na)66hP~*$nc7KDLDT;A5ju^37>}>|#jcMmQc?nE=sYrRAs{UUL~zW{>gd&^=-?
zPZ>Se)S&Gncd(nI=Cy;dZ@0(5tMA-6%{{s>3Y=rcU4e?R_jrCkuHAH~_R74E+6gHQ
z(6<xQYD3Q?y#yuRb$RJBc_D{*eOmE5f~NdZ3=O{ahvDMX8O|t~W-d$u)ATOipkl^0
z8?erd>4M`~mFrOL7rqHT&Yt=k%I6GQj}reM2Ej}~@dKy`>{bL<f~+_N8SK>_<zZWS
zzse6|_#vYR*@Ls{i{<`a(2*mnai<sk(I`#qM24GWRb6W#)#0JkznhbLK!D#2AMcPE
z{&RwzJVy@c<ob2!WZ!{(`gZgV2ypt^e@=++oRDCrzCM040)l;=0{lX!%>btw?m>N<
z&-V854|eN3(WN8*b9Hv@<otz8Cl@zYH>VJPf4^XLY8W;9uWf7}PV@e28{xz0lioAt
z`1plR@fH7VpG7B+pseH(+D$__?y|C1Ys#%#WhIQ!`af0wn(OGQN2--$bn^i^J|=t&
zd@S&>#HUtP^8vLJcB^MCO!aFG_YZE~#?^IH+pN5r+HX8nv-8#sRJYyMZL(^Qu<9^2
zYhtQZ=f3@%Mg{u@1v~k82l@F2JN5DR37!4^`yTP#$N^5l0p32o6GMExXFGlEKD5Kv
z-a%6)4)LE7>gPMr(|>A6n0Jt`Qy<^Sm}!6NuGy>b9b~A)euklXU#6Do@GX;N*6nhu
z6>sVd@a#MBTla59^=;nG`TftRtl1@X_MA~0JDcif1@E@5+f(gnW3p94`dL`1t97hD
zRy7`0)@oWq>-t&e%dI;sX#9nXYX=uMXXm!fU0gbL>gduOXPc{YR~Of;kLJ`(YS!Gv
zXR^1O_Y^m8XXmcnTwJ}KJG*x6=Hu$q#m8l`tD9Tb==_+v_}FCS$Ji#1G9Tm%0oMhl
zM*;~*(H$c@;jV&Qo1i*E9A>O5#7jn7AuPc|cwNxPjP^o2U~DJ^VkUwb3xRy6AOwQ3
z&sva!5WgWhOf7`KUQ$6Vh48cnwiY54I;kxdKPzl-&_ReJP)<%lOtJ&I2=R^)<3MhG
zU>7KYF~Y?4Wdq<BLOg;|!altmM3(6*A=)G8LH&gI;uGLdA--Y6STT`tgb+cDBZY`!
z{1*BcM<W}T!Uwpm9%4jn?IPm@A&MC%2{FDI5HX#6Mr50YH3v==BAs!%5H_CzXTmTe
zhHVeVIq0d+fB{0ZU<?u>1ie6^LL@QH6XH3e@ApESa>T&`A!-<ZMAx<gMhG#Fagh*H
z(Onb;&l#hIIK#LEhT8yt5yF`<Mu?G&2pncJt`y=r<F7(oZksjszU`iRRJ~5sdt*CP
z)=}PXY=_CFDubcDk`;iS%A>+IQT9>gOnE8yO4~5$r}kEY3Q@JH0ISuQD%(U#h*OnS
zwnOPaoElUO%#BlVjDN?e62`(f)x8E-9jBH8VeWbjq?@X?ZvlPOe1<9NG(%)o<9D`s
zSP;dl5@|P-Uc{^J1gwr%OMxs)cJF01KxZ{yvkQZ(<(ge0d|aucaEiLa;HO+nfDjeI
zus~fjfiqGKG(as=>j0FHph^rVFHBI~E$rq>N0niLT6-le0d<rIfHE^xvL%>`kE&;k
zWhc~Ewcv@PT3HKRUg{1*q;jbZa8wZtk?JCVGEb?`tiak+1zMqWiaNp&sqE^YGWD#Q
zTnG9xbJZU}?sjYTsYs2meot;>a&w@1#-yWiuM09aL#?X&UgI4ms}Cqw8<2h~!Up8=
z)9MnF?bWBYAdAncAX`}2d`=w&vSB+Emt9bk?LaP286fdB$a?R+@&HiT4V7FEl}%MS
zmxd_!`T$+61W>{)b+<k$mnj!}yU*odHQwH?1-dK3-mbN&VjhXPDveA0)kTz0=4@4I
pZ`X>di`8chfJJlFARq(+8*ue6Dh_0$+()*ektIgr4?pq){vRn8jz9na

delta 131427
zcmZ5|2V4|M^Y+Z{&Q9FCi#g|<vz|HUoYS42dU_t_aAC!Oil7oiqJo%EQ4tkTF`%M?
zm@puqA}E3im{A1%o?7+(_kRBFrl+c_o~r8U>FKWS<=ws>sr!3uuBz(uI<op7P3<w9
z%v3tFU(MLBu}ppDfB%_T?e8sQMyLNr&8Qoc?Sxu0D>SJrGG-NbaEY4Hl{+Rf>UQNu
zQ;mwxI4Uq^4cCMb8J+VMo>31jH;-yGylZn6V-~oqSb@>C`iEoGv&wCt8oR(xyU#N<
zHQcPZ3rWx*l0;RR(Ui3`gG9LyTy$5eN{ptawLk7{k;J8ouJk3#XqsB56ZaBv>7q+G
z1LclZJMJr%9m}?38OG9m7&D$t0f#B`*iFMsaNKJwL%KE{#!Pe&LYWaCG|VK&y;3G5
zNXtxi+#4;upghHKZ)GYq@IKRQ%+!?8YNk|0cx9PN6Ryk57gZ0KaiRv&#>V4To^exT
zm|DYoj$l|uw{VD-(VkN8Lxow;B<Hc;MEN?ONc6p+!S&&Mo?+$1)m4m2PW4{eypp}&
zRRR15IWj?<QFw-LrRG!&Q@N?o^cqTje5$|*%@vB8;hmf{jL^zKX!u3o3GEz&!0&s;
zGD1fOq3{n2I7aB~AdLK`3lbxAa}ZX3iydM;9Yk3^K3TRiLO%ypk^fQ)N&_84RerTB
zGQuziQIr3@04|Jl5Ow+PW#Gbi2hotxP3)*<gej_e@YK;T!VF1`c=pD_TRCR18qtQf
z5fJT)Xqi#V(OQww$j%2e49Dm?Y}GP$VXi6-$~ID~!c>u%DT3QW-1A#k$&BD$h3*-?
zMID&gSeY6`!^gEm&F0FLK(yq8H^Nb`%1#h##lIMV8lNiJAlmXy86bSCy$8{e_vj2U
zKL^o;pQYj%A;3ZO=)niZA?_dt)rTK(2JN%WK@8waDgq(IK@8#V>;$o+GWCZMe3=o@
z*;$z$${0StdsNGM_J#Ms+N-JnbCoNKjeo=A=C@}{jM&uCRt%q7qG80=4no7veTJGJ
z&(3!sYJNOBdO~7%hnSHcIt@fG2Vv!_d=?q8uY)Md=qCNFX2kw#E$mRsdw*#u*fUuk
z&E77VW2(yRCW)yjpRdL+)#M8{hN&*Ej8!o;<eNzx6C$fN@k}P8`?3!pYt@SZVmpG1
zZp0I~ve`_5+0KJerRbTK=^<{}$$ft$;@0YP|Lu{8{?#Z>4exP;W5hsv^>9>G<&W~9
zf~(Q%Ta#~@2x5D+I1sh@NWIL6q16vUtS-O25H(>Av4(s>1D+9gIm8<CZ}Ji8o+{UY
z-IVX@51sJpQP640KXeDN-$Ar>bObS?8g+z@ypX0T%ZP`norY2;eh&sKG0H*w#NY9*
z*t%Mcc0E*#cv*cL^;NYUSSDXXQC59u<d_1-ZP{DiQ(D^^O*p_a;VLJp)M^>VN`{%T
z@l92XpUOh-a>f7S*7e@ex@Pq;c`_qEmq^1<+p1;8>v6~A!Vnv@8N%um@7&gv1`en!
zGn4d==cn?V!02NDT;8=R&wSDmEd5)Ik`0=|lg>;56+e-_%5#8FahZnstkY4;sXP}7
z|9B5;<JYs0m6^<cm74;94choaIaAl|oAN@Y-fyWA!^Y^!|F9F{5WVaW^={I(My<q+
z60=PQF7pkA#i*nnRG$a4BQ=1^bB>VWy`*hTJ26-OhY2@V>&pDFWLSKGXGS=HrZ{ZO
z`T;aT*Y;l^=#2W04wKF@wg00N{6nYq|LW9*&M-%NEMyGvDh;D|DAjcsy7@y%uWR*R
zL&pCzRBihu4f8>PIFsPeX)94fN6l$BlyxfCi)V5jbweC=7&Ym^rL<q%o*N=EQOb|D
z>*#n!e?!#qjG`3BGg5o*w5uOun2J&c(L+*uhS=4+qE>ZS&Gub1Ma_69j=n>-|8n3b
z{s8b$I(=_FhrWk0@Y_RnR__|aL2n|xM=H;`O!=|iLpqi1OdaD_rQbK59%>Fl>95K-
z>U=8CF6s_nR3K;5=Sl5(#;%^+S;fpyI#adUGsdod<GrWTV|yNkf{u=0eH_m8LXUMk
z?v6_1AB{Iz;+UV5@7;BwKxR8D-ygIyW0={LW6C)oT00<?|9~i`wD<u*Iu(BC;F<NG
zicv?#V8wUVnW!UW$}LG&?dfh8Qle^gj%UZ+@X|2JkimQA!1XnLcP&}|AKdHm|8=_0
zW|7(F&<Swp1e?C=?2{dRLG5`8_}*Q+K5o$dki`5gJKj~YQPv@UiR8)IzvZSsda}{e
zdtkS6eTh3){{DpK2(Oo_7-#w4Mk#WT6}~mTGh=*{&NHp#f1mVB2YMefp?e?dR+)Y7
zeXUzL7Q;ce$`xLRsF)(@U)iM&S+m6<Tdn)z3KBYa#{XX*_O1R1>O0<0Gw1&Q`j%FQ
ze)k@WYhASSj6XW@k056{st}I9)bU4$+vWYRM@>7$xK8T+BXZNuIwG^op$QcXDMx;2
zE|YrvD|FjaWPbaP(7hi*zx@l(n95YeJnTP0B|n5FNNxW`>M(n!h8g%DscQIKIUdJA
z>Bp<Vm@@aW%uoLj>g5pfKGn0PiTrQ!AJGQhuX|b@QB{@N{V-F%I9g=bwj#z447=!b
zY|!O$-|e&&8<UvY)8`+dx=zis7yo_2e_J(7haaS~kT^$RI{qN%2+jpE)9D8}Q*gX8
z-%0P)y#m<TQB`{1WZ5cFulp=w*_5am{o>j3n^$U?VByDblIv*V?da_2Bi#o)F24!S
z&FSCjy7;)UK_!)`I_jr^6I4J6930QGk=~PrmPJ=uGW2ozj?;N&ApZmLu490zTGOF2
ze^?7upBeQvjP>98M2E#<M?G53%71^TBOK$8l^^kK{2AgHf2{npZ{yD(;Y%g&{1IO4
zRqque%Qm4lzo-4)XTE9P(+>Zy<~{8%|IxfO(#!rSLSn{ff4F(V;ikPdxe2f_+AiN7
z)ij42W3)rQflYC^F-AM(8`vcE_2X&?JJUx}<vB+Erh~|g)wcTf3NnuG<aq7>eJAfp
z%ml5@A?%$xs$u<cyEII-e|`AkXbQJF-+id2b@WQda534t@#x10);I<)Y*hU*nJk;(
zEsrbb=xuj6N5686Ta%+&jf-ddSl<auH1{L8DGuP+2H%0Bxqn|d`bI=^1O7Y4M{^Ut
z1vi&bCVO|DP__y+$O7(r=l|Ba3%KDlyHa`Lxp*(0;Kr`-W+#?)^ztEGhwr`I(R4$&
z{{KZE!j1odZhWy!U}|vxjyY})FQrD`y{z%SUe@4-eY5!OOH_mV`3H{j^Ei&VtU<8e
zeiMxjA1-UYztG<v-(^jo|31FUnlV2fA3d+jni=1o*BHn1O4R(%^GecudtRQ-!etD1
zS2f>X#yO1A>VukbCcBP*H61<3IHd7+|D848-}Y}lIBN!f^Z#2Ha@I`#uMf_ex&QTH
zzQ*!RnC4bXCROgg!o)Fm@bX~>i2vE3RzIxVQMLRrrkG~-Rxt_x5gPYHC_&ZyhmbPK
zJ9ARmvGhp&Rc-#|=5J(~0jeLNWIAjl{!kyF>ipx0>cX{<8x#TomFEKWwM`<(Dc@X2
zi`<Ly9y+;<<1_V{{o$DU(oT{2%=Y*u<;*An8??+3_J^^34r2|Pd~dcR?2qolDE+)6
zCzqW;zD{Rb{qVI>)dyNeHCa=I@YEZiS7A)3nwhL=MvMv;SGw;{{OZ*jX_=`S9q}1G
zt(6+zkvT@y@Vl-<wxOoOH`%DBQ*yK;>tQXWu7s5@{;9oH5@(H@pk>q*c+Tlv0E;T^
zx2n}F_w8mktK+I(`3RZndbMcaq@S?pQY&gsJ6S}cLNIbpe%`ZZG{@k$ZAMvky?6AC
zDoU9^Bn;GhSSPN^QSYo7b6J)5(3x#mgZKKGP3>!@AjjYU*U-uo|9PvlxNftFxK@5d
z_fN6F=9r=JB%mFy!gbIW3D>fpNq$%X$vk0cHs*GRu4PtIt?F0eZ{8!|+AcxHwZ}!e
zKKO&K$HNHiw*3z(2EQWKbsxHq=|&0%($u)_IZXW8n4qIW*5YyPjP(`ABx30elWoZS
zPR#l^=3pFMd-Wpu;=P2h<|JwDC{L2P7@#;NXC~b*I7Ij5x{>baGImmvXOh}n%)a1J
zDtY~(n9P)<ljzT1Ni@`%IMwVV+3+W7kI2i^LQ(4oA^!nMZoW=30Ud}F-jnV#u8~Q1
zXOe$YK=_~PQ|-YWbU&rJ#*U(BItdLArV6nGnSaxd;GVrF!&xgRZs+xMeUeX{Mb$`h
z6~;4;2}&g=Vy{tc?GuFK)08;F-%@Q+AG*K0oLZvsF)}&eG2wfSp)g9Pi;SIPeCv?t
zY%5*6hLNbw5yw@eFgPZzCB-p&2t|;9oDaub3L}2o=j6)c`y_9iO?+>6ax3~G@muDS
z%&>Z7rf3LVkG~{Nzyi7-W^(kWM9ABjDwW8i&acQ!Y!E?IyGue}w~<iy{^ZslSnzX9
zyc=<P&!t$C*AYjFBgsnp2%*UcazczD&ddJfR?chUY<BdpKSSyMY*Rw$a++MMu!|7v
zzaAjNe>EUtc@qM<p(B&i9nJe_0o~`1p{w}=NuGD`LmiIJElY5DRx;*=v5;fNr_lZ1
zH_63zjxff2CYj9>$$XHJtUNtSI9Gf~vZ6hbs(*HLwBCN?*V5~B9U4cj)OWl{L7(Z~
zT$LmnJ*4{<J|t7dhs?A$lVQId1XtsCsts#F?v6i7waX9FQ*YRvOpeGS^Di8a@3E0&
zIuAh>5wD6j5p92=YvpPrG{K*)l?-%EIz%$Qr>Rz3i|)_OCeR+gQtds5OxiRuykavs
zq5Fl5Jzq+k`!z@_(@LCJGu8V4O}h05(PPSb@96&#uZb9eq$;Xk5U6h>QmfCC!p}1t
zKzE5B^nxT`I7W-|j>hc%ie&n^5<lTFnOWSL;{FS1U-X!(q;=sDwOsf{s!gg#$l<x9
zH3ds(^naT~qM_~-*_LE7R^<s**KrI!%iq(zGfxohmQzzt^(F(MsdV2L!!L%TWYX0I
zlH{#%bl>bX)&7IeD#n%0bX|h%4aZzuO#IIE$ckGL0=6?NhY>5*Lf6rg2+nI2T}K6w
z!gC|>(@v537{{~xtu2}F`G(>sUP*1Xt^#rN6C6#wp3H9!B#v<xaY{Fn`M+<I$!Me+
z(YIo$_O?W|_T&p>z-<U!@AW02>kcP8&XURAIV5D>MA!L`2wF0djI^B$4>8kyvXvYi
zd4)L7AJP4+2-3|G=-RZD%zwQ>*Tl6{J8(X=Qxvkw=$Lk-B`}N(BGHGV$*&1+1iHQk
z2~~6mwOd6pF`tM(xhq9bX93l2+)dX-$>dxO$Jfj29wD51PV(z7kjb<<q}2s$RkQ(;
zY8c|`lYCzTS=_tMF`gf(NkW@z)78BPRd4A@v8IkBwZNIgcWOe)_QeGHU=VT2Poe9g
z*925MknVTQBdy+JN%Fxt(p}hvT%24?_q94u#QXlC01ACce&7_5#{a=p$z-kN)PVh0
z5M1N|0_xbAfSg>2^L8L9PfDcw`+G^b<`UBSwKnlv9v}l!8@iS%Bol@uBVO#jbUkyJ
zB=g!4+T~0#FW5*jdpMHN=&SFkV!%Ii?a`JDXO5yM%a_o7BJvja$i5=AILG)H`IMA*
zZzIs`NOENeQlJ<aPf@IMPf+cISTY>xOZ<xtoI`npzl^0I-*g~M?HtJ4nQ{wAVdZ#I
z_{s6nOg~J9kF6!;e8+d8vzDMAOd}_jCKJ%F<48-GNk9iQ1ln%`X>FNDoLXL_dlg$d
zc;0=8fA0ic|E@y(EXS8+!AiohckfKlZs+N$^&kV!PEy5(L3H12A;mXx1u2Uz#1EQA
z5Zo%d{^l6h{=_6$%luh^j1?jwq-D04HMkbc6L975$h1r@602xYZ#C}wAC+)zngM%E
zh<zx<{nC#bbA=Bn__QJD5%<Y(s-qv=&sBln;*q22?voRK#XLA(ZwYk0W1wxGPxp&W
zbUn_Iq}7R#*Xl@e=Wi5DaCyQ!`GxR*zK0zfW^*<c+~|`p$v~C%BzkuO`B)Y&q?Vc0
zggkB4nM4~RpMtlefV_5ZOEL{Z=vsX$J&5XYWT1y*#&;B{1&%p{K}^dma3=oy_N1F$
zk*@xj)M%N@Ipj+EKy1PwA%ICEj13@@m$#AH*>hx4eVg1m+?pcZ=jaFSI|=&N2^5*+
z=<_4|sM&WMLI#W`ujR(hMC`Q}BLB?QKQR}r+P&{G+>hwG6M>HO`Gne0tJmOuwBKfE
zj<L)1j*qos_k|nxWj^kI8M7K{Gmg+l#<?Fo;U(3-f^WA}2WJ)gv>U9uvrjIf@MSC0
zd}Awn{0*G+W3MNI@@JndM-jjV<UuWvZ8Z)?gV{e{!Rj{ld>cf*ojtJ=>LKhXdmk7M
zW&7TR=nl5lWcV7!o}h2VPS!;Pa~Jzo2KH`t=xP*u*dg@U+shsu4770eRZC!F+pQlI
z_Ombkgy#p?l{vtUU~AB*eUObl3Cu%m?~`C2X4h2$70EtD19L~%5gvBvN3l00R32qr
zHUs+@`$snH9%plDmKM!Urx7}a&GiIYEIXL?uTHRi6JY)%+bkUFr&#X@FymN%8edPd
zy+Yv38Mbu^P|mV0G!UI*yBvgMJUb{D=FhX+B2e69C(A6xzgz6kcCeem`b<V+-)77C
z1N#o!;5;<$vQB5=>3w$0IAEu-T`xc}o%Nw{ErV^|5XED5z*`v1X6KlI@|2zA4uxlI
z7=27~+5YX&zAxDhVbIHG*Oh`<$ZjkI*ef=yRKWQ6nqBi7xNlfn35vJug&f#@$Hv4V
z-uG;;-e7)U-9|#Ah~4%Y)JJx3eK=aoK6wj+pV_GQ2(*ONoJQSO)=tmYMYWiwQ7cs=
zz2V^ol|lWzf7Z@k0ic#$`aoswT}*}S+#kn}!;<sm0Wdpn%^$d*-?TH<gVdd?-);!;
zCVwnOfK4xi;@a#dj4)jDz13i>g*Wxx5OywBIu3Eo-MWZYtEFi-f2$e*g}cc4a-yI`
zx_|(y`A&v=bzfpk)UIN?eNmzPSF`sq#%tHH>(3yp^=v21*|ct~sE7Opwo)CuoZHy4
zlYq9J{W}{XMQppCaI2K{I}flms-BY|>82{}1K+o(Txl}ouR5_E)OJ;mO=y5as>8FO
zcSdz$E%cI9i#}q(N$wcN+UKL9e8ahrswRyBT$6*YsOYqTgXD013k3N43TIs1*?9t7
z*v;C0h3qNT#|1%NV<(-E8SOjPGx&QGNV_Kj(D)di0d0eTn+UUE7(Nf$M!WvTVA6Q-
zKiH6MLR<0Lrk8#~WcFrrvM}y6Pt&2DT1Z)Nx@Dd1XxvsF!{JA3+eP@%W_bjjX4~rV
zxV8(XnMwOzH(<Vdj4NvU$w6>z*l+Zam{?R3GBZE+0?s^B1Jo|nAO+63u>Ch7xOMFQ
zg~0Y^PnG~=EBjQoLu3c*fgN(ZvB3&JkF$-ifv1gO9p1;X4);&64*yTGjsQ-vjtJsd
z@>(0uIwCpGQY4OMm4<vpBiKUHa4i>+g=>YE`(dzJ(^K%Y*0_Jro^`5LMmsjLR~m()
zSwAmmwivga0-PTLPN(dv;B@Ak;ZcwCli+*b8MH<kl*u8q;Tjk0_0kh8Gb;s<mEw@?
z<7(8UalYQ2e{gN3Zw|Aa$0vZ_*G5av;fv_4Tfq*dsk95bbPI4+vi5P4K>D%AKLOmI
z?d%HI0@%UyUEjf8`x_Wx>~$Pmz;IYhpTvW#4=EmEdwhW1!)$Y;sxUe=dIt4a*7G1F
zPp~Vx!s-Qf`=3y_$aaZ^WCAN4L@2k}YNH@>hh2CJX792??aiQ{!{*TJ{~6ncg2`p$
z%n<#+4!Q*WB6ewQ82rcvyMgJd>RthoYgGqJVQ`)5L0K?;Rh_D$*s4n23NSxaw>$8D
zx2o1IfbCJOUWmHAs^}5WJFe>aCq$xEYnQ@{7}bk7J4_^~TGocfCDkW-Y}ZwbC;@X%
z)q)Zp4^$d@W)D>lNIy&US2P+oM|JKUs28d{J(}x->gs$1vqD{O9`x3z2N<B>uGV=#
z(nCEW1tNaxqKAO?SD&d4$(`yhe?fAWy6HeI-v3B-{uNj{qMkkjpy$*sgP<R;wqoM$
zc*Iq;J)u-1@de15s~aQkTJFoSWkA*4o_T@pKG7GpdOV~_K=1ZXah<V}{oWVLubhbZ
z>z$hh(1yn|aBY&*5ZC4|)u7+X-k*{gZTI7|&vnSarV;nk$~?4p*TBJWxW`Cmhz=Nl
zqZ8bS=vClP7)EQeX}dn5cFwC_xc<@pEfD5!N<$1MwFx5-*(vSEjW8OgE$EM`3))^3
zSfVzIN8K&$<u$N%U;EGipsRMi{d9=F<!^L=jEflX6|s7XAw3{^RPS~Q%#-@^#jxyY
zJTVlMk8xzo_r8CSz4!)>rLzk#QQ;o2;gvu=WZTpC>oMEC9PqQ)job00v)RqzD11~k
zvAu^evR?!Mx2oopXVCtBsyQ(L4p6PF0>wbpjH*BjRxK(*u}!rq0Wcw|ccVass`k-0
zJxmqS4}tGgbw!qvJEroDLUCO6mDblcRi#_u#Vu7{A|!9C4%0&Pj%wu{Sh%M$(2_k>
zHLoL>X{vNAWbItKDxG@h168Y5;679Z-i2tUDw%Rtk5$q6pt4m?)NP-rGAa9zqdNT=
z!8}tLy2DbQYW!^IJy*ryBmnnPHLe*H@>S9v#Ii!Yn(}Kd>R}luR;fGTU=_Doy#^U{
z&Q<;VHJq`pRoC1OOMBH}MsUN`uYQI8Ep_k-P$}v;GGOkggR@}pt~%u~n5pW<w1B*?
zenUBjboFvtOlPQ5r=WPKt}-3!kJQy@^vY8Aoq|TlR{QP&^;CVa8T4}0bI$-QS6vzB
z0=PW8x{yA+FVvM60Q;rdKwYIk9p?|KP~GGUL|?1j$^hn#T51N#cj}DBV7^y(-vX*g
z9rXdBeN^|OuR^gpClh*~)n_Q)QuR_JB)_OH($~#J)9@7HU8#AGb4=VC&4yAaxN7W%
zT`;&#b0-ynuGjSb15s?ytlAHQ?wSm|X52<iWGT=#X@)$2qNnCkFeJS+t^bC3AI%jL
zB)4duc0t`%O`}#Q{51ZQQV7&cI1Z5@%^u3jZPSF`gBRO1BPo_p&7>^U?a(CJ(V4kj
z8g?_h*sU3G67KKSRQ?mbg=-$Ig~onO)h^IDpvi6x>Y(PIDnL7=$@YR5ks7C;pm#)b
zy)&3cHTHCLfn%D%_n;7?*)$!_#A;Go0_>z__(7<j(rl^&k<*%)W{8~8%sN8j-#N`n
z%>B7|&8|dfT+m!p;KfBvB+areX%^f8^RlKv0wfbPF6H5Ol4hZVB3bjUD@3koLXQIN
zhQ_TkP;P40`@oqLP3b*|+}0G`Mu2xU#!f)Fr+HWw3imaC`k_eE^a-Q<Q-;Pj2bB*r
z&({Iwk)|1gB2&|y){xnnyc>XdqRCr>B1iLkGt@oP{FVk2d77B|U_RHJe}E!iQ@0^3
z6=*8{fhKvS2{EF9UTZ4SeDAGh{1<rtPBZBN>ON@ZdO@K`Q@D`kpPw{YJt11GS)L5g
z5>5F(&|amQXY}=0!L6W$g$sA!85CD>$>RaDnp<5HuDNo%N1-j(a%ngK#;xa?NYHcR
z-qWJNom1%`>A`KC2!A(m+cIEbGdFTP^t`xx1Hkm=CY*wZ-IwdqA11bPanE4TpNl^O
zZUEP|53qx{^|c@x%z18w{&p@Y9t|AAO>75|9b7hL48pkmcVK=OcZ$-GySWZgpu)Lf
z17K+%mrpCs1DxAlNJemH;^E;T?j0>^4|633Fr(~T{};eM%H7Ad4R@R?y$`$5+~Q2w
zjpg3|4(bHgoEFKaI2%3DIL@{h`e(SU0nk6oy$S^L9@pO=R4R9NFQ{~`Z#US@;2IRc
znTOnwL8yDgRiIqOW3K*gsAqBSdII_hXFtlq@26bT7m#_zU8)IZa=DSo@N|WC`b88j
z+LxWdT%~<H8$PYpHXH_LT(y%sLSe0TEqy)KYyV1uB{%Jd{=oLozNgIBMr{e@o;<Z)
z^i}iH&OZ-BTeNF+Q1I2(T?I$|v^G1^0Gz+}@Hxl?YVS~fE=c?J9PHlET7Cj`Q`=+$
zL~m;s=YYDSbsdMgd)k)mp^&OQ6#>vR?TE8LN!M0r0m%p2>?WWdYP~wa-%RaY5!7R?
zC*^dqwHut^(-ZCQl#j^Ke&}ik=re7X86fkt?+*g)xi-fciZ8X{V<DQaoqh$DUTL%F
z8~j?k_9$T9X&)p*@4a?S6eK@tb19SaNjv)u>PocBXn&_v8{8S{U$t{7Pqc!c_#PHk
z@>g!7ZWS*ff59E(d%WlI{vG1)yoHHKzIsoXIKmr)fOeFx5rYOk#<y(@&}e=^8mJil
zg8;iH_@qApbCQ><gBiz%Tm*HRA2%FzXZfFKFXSBGf@ZGg`J~YhxxiPaWOxF<=^>bx
z_}?g3d4=B+O8MVJzU($sUgd{Tx+t0NMERHN{4>hi-{70lr{fm?wHv4uemZr;JN&y=
zDDLu;Y4)GW4|)#jKL3XrjhD`sFNXISI9ZA4AM%%C5&a{6z<9X!nE$gk>}K(m3t{gm
zf58n@l^lM}A;9GE^=?t)^Jdy#%jcKjTqIY(`+HYgZM7#*>gNMr+#9@4y!$Fh6!VX)
zaJQ6CrT6^{@6;P+R|o?-gXtoi+yrWs@GKXetrp52fOS{F^9+i$f~^h|)(gMfglBHT
z^)<kB7tEBg@DMs(La|Ahy#bP&1^F+idkJgp)GfS)LuXNJ5j3mNBEG_fIQSGVZ0w3S
z&kJk1qeu{<7K3?7*h%TxM8Qs}!z5uw0xTs9y|I7IT@#Wd7`!3e8V%-6p?pt(r3lq&
z6?j`%<qwp5f~!09QiZWJ?N1Yy{6gP|bYa3~n13jg-AOGftZo1*OAu+^m@P~t?5D!?
zT-4<Vwsp|Y70g&gb9usJnr*xgkQqRy7KTK?!vdiJW%mjNp(#XO3v~yfcq0Vlq3)fK
zM_UT-h1<Qr{3vwwp>M<|A%$i+p9SYraH>SOR}W}kh26iSSRryWF<dFST>`aAOrd_b
zMqERU?<z(np;#w6hargd;_5|kW`kJt0VdqVk{md?QJn7y^-W^^iIDUZC%c035)TIf
zWs7(p*<U;7E6%$NyM7{1nRS0LmX;ksqI3#q!D7omFhj)c84w8-Z_>&pOl%g7w%94Q
zxC6I$i(P04+avCzbVRr~h3xJVO%3720ntjcvIwz^4#gpH%?mIOi(xcMMu}__pxBR!
zn<fDJxQNdiUPf`zZwThDXr@8rzG$McAWhtw0R0THV<d_PqILxAJ`$gV11(c@r3`Jh
z*rPf0o`{WUZkHpzSO&dkqG=c~^Td*?P<Sq0>I`PSnBD>+1!DUnpkCX>^Yh@w8*%0p
z=)V&~X`AA`hzSM0qT-D_6d%Q|y%E}H@yTIWDiK{L!|oUH&T)W#74s<p?jm*A1hkb>
zuM}XfmQoC;TO$pnL3*tu#Y1GBbayZG+@xC%Ah|*6@D3s#lD*UgG8?5Ww5hpS%BAU?
zr?hhgD!rwwfl&03;wM4TR~lx9$X02>b|@T?`iurMN;*m7(=q9fBsAA?DVVY)F;duE
zco8eDpf~2EG?qi%DXGIv)SZ@AQ6Bn?)S2e1=cHqHUs#Hlex3{Rg5*jY^B1MSE)cyW
z)uD9zWvO-nd`gr${szz_sbB=CYtk%Q)?JrkX%qOCRPsCOQl$NfVBV2DY5(J{RH-Q}
zrAoo&@eJ-u2dBb9y7ZZno*7cFY=}IP%2v07%#?g1pqM2^(o!{BnoWC&PbHB)SUFN2
zeZzAlH`=DnlXk8L%nK<p2F#bzD`c;^0%`GJG)bW(jRe?hDRdv|-bf3B;MzMW>?JI{
zmtGA-@ljH{q4*>*?a*qUr9OpfyniLqN174f)WH*Ie3jN%VaY|VO`DP{<##r?A0WT#
zhPps`8})=>IcN?<w#l`x!I==*zdgJNl?5ER<ih0RG^gAtkE4yH-EtTXl5>0Ht~eOV
zh0A+tf!Zh69tf}l@@6cR>|BIwy8%mw<Sd#I9F|#{@g0%1ls1i$|DjdjF*&ItM2^b`
zYrt-d{A&#2jg@bv<1w9-x86c=O7;u^^Nc*JIV8`@qiNk1FaJRs7w6?`_(=elAP<g0
z%UqJDgo3&vhm3+fd!oEs3%{?*p))}y%gsVSU6)(ZEaiq=a|6uZlAUQsFh#C05<cCL
z+jv3$t{nOhb*Zw;YEbv((^a9DE~m~#%Vx+gUm@Oy@-<2!Ka!hALGQ6V?h(Atl2`o#
z=qK`coGIm=+T}lPLFSoULRq|A`C@tKKbOaFC|<}XqfnH}&G!Ipjq+|93NK|N%_+T=
z01x=&qtx#J^IMd4*(iLK{30;7Digg>_$f86K*3+xQw9bDmG-pE4N^u};6<=<nFh9P
zig%q2dVAMa5D!&SaCDE`p-ejm{9VfZ&yd@#Oe_b#!j<Y_z}TmZ8wloA#j6M+$;vg_
zEV!nmQMbRY<gS7G4P|9>6gQR8#VBqm>~a(-$`R7Lt;{Hk;*PQ=8pT~@#-AweDe?A^
z@I6z>6G1*!dgUYLCrXt_6uHVZEnLe}n!g0~Tya~8;)OD>5zN0--qLPWzQQcl!Uq1U
znncG{s^7|nN{z+oXx5r1Pk~cw&uzp|yU#E1woZO+@ar<PjbD%T0$lx0cFN*6NI4Io
zhT6JdHJVF1{*8;NO`9yn)(zJ*QU!%(y?X$nxzjy>ws=bE<CeA_&}!APC*)gKJdXg{
zG$@3Dwym~;)2{t&ptX-c9+m4*NSUXO<JSPKlh0$Ibsl#O*Dg*xjR9T1?1NCZ=WPMe
z-4&;uxE`Tf;a2}6J-{FHF%kDOergYsOH-3zU?m&a3%+=;u@yiCu=UG8Y&+{W9FRNN
zs(*kP&Yq=5c#xfOgNHW$bK@Iqf!GE<jRsG5e#s43_TcRyG>h2Czor%HCO*mwm7Do7
zqY<Si-;Q!)Ui@z~3GwDH`@sVr-bR_hE&T9*!1U!il!4?{zBC_&AHOgVMg#fjCSV5f
zdzyl|ofl7l3gN4!K_Qe6qDI)kH=YNuUHl09@6g!Id#{FXd-(E)P`Q^MH3XI6e492X
z_VJf#^JYI^I0JSM@MS9kG=iV1LUEA)KqJK={wZw^9Ok>yK2s$Bj0JUs52Ea96#r5K
z3rG1(8O1SvA%5G#9p}r_1S6V%T}1Qr82%}JmtuJvEd@^S>zBZplYH7%_<f3>hhINn
zGQ8w0>Q3{gi&326H=Y19o=>LN>O5bJ1HG6G|3-(BF7oxdf|<bY=mHa$_@B4I?aO@r
zTiCtAD?6Z<#Cvsug{yo)3+&TjYFy?DTKyV7r4jV6^Vp7|8S+^jU~ck_x<d38zlILL
z+~JoK=v}^H8bI&y)#>O(DnGIlB=7U3l<`aBpVxt8I)9k*HW_>e9+(e!>pPf#$S2-H
z-6Ou~Uue-xeoQOMQ$6OV*9J@$-`pFO*}Up8V4m=8hr%u<(_;`?4ps!P`;0H7#ZE3?
z?13VW_n-{wbAC20++Of|sPSL&TRNaFpYK){6z194Fki?AY(?>kzj+?fzvhoouKo>g
z?F29EZ~5}Hn0?28pkUtfnY1zRfp0>G--`GWN@f=Gg;^**^Y!CV_l0*4gydKL=qrG(
z5K3Ny=^|9557-(ZkW8!<&@(aZ5bA3n=_aVBLw$n~NavQ^1&>{*^AHNdP;9gduc%En
z2`g@c+$?;Y0Z>oDKvQKe;pak7-okH>q3<L3QWx4H44wmOtFW7r4SvE2a?M|;p8!jt
zLjJEPb_lC|;Zv9((xhvr;Fg63+9lMZ;c&N5)rf}OBOLz(k-dWbi3u>_LL<tE?h||{
z2ex0Bdjvim5T+$SG(zy8<4^~M;&~7`By{J&JS@0V+C5V68Vu$Up>7=XqJ+5}K^+zL
z{tnDz!Y*2092XQyE=CJ_%45U`Pb5SZD?Hr=M^6a8c1ri36yke=drGL*3i@$E;bmx?
z7N+e--5KFG$|If?)*JzKPPk0R9pZ%zIlw+I^mIkt1))-7IFlgc(Gu^HaIhP|E(;45
zLgb2Yna&F)3cG0dOcLVo(?jm6aFPzwB@0#4>@avu$bA5V*M$L7!M!2myn@V4p-*2}
zx+N^!4D1vk><L6}3n%&l^p4<E1I1k-dN4%p2~JmmohlSQh2DK3bP<X)!9XYb(uJ8L
zftevxq|Wj{@S+v<Lm}P;jy@84+9*$)DHPE9=&_)u!xdRVTguI33-OfJcp@xZ3el%R
zv;s$S1ivGoo(WNubjuY^R)l1pa3vnjJQqgAz|sq0Vhz;26ar|ukS}zg^Hl|ciW;_1
zc>NaYuY~P133)99Mv07!_0iWbD83brdPjO$8>G=`h^=Br+CUBvn-?L7K=CV`*9j7b
zKSvQP-lKtSo5*{=^0L~S;@42z4l$5+y28X(ad2g)xQkYCyTq+iQ0x{D%|x+Boct?d
z-z&P8gLb&sna1yZ;vssK_lpbZ$j?FXFB<+2iFIgG^04@H9jHigD)s3jV!0X!Axdns
z9n?{Aus7@-6MNZ*0Oq(@kM@G1#R>`F#)w-lf*C88w1?;kF)1G&o)n{LZg5KMMst=p
zan5h>>9n|MKZ-Nr&@`x@6}{S_I4ANn;Kz%`2uPk6jlEG^5S=M^b5ZoCZ*hXyv;@$X
z#AaQo|6CT2oPgpLafOWbNfdpLq0y4W^)#Gb6%Wz(Ia$<GcI=v{r48fj;(W@8-Vj$F
z0?bYELOVRGTVmc=V5f+slmWgi-l9yy9dSKvt=<*KgoC;#cA;&WRMERCB=3t2exp1~
znz(Q_VA91Wbfz*xJm86#9*CLkq47{GrK!auvB72dlqr511nRNaaxHv%B3>T`w5Q^2
zI!TcumQphDnYg7F^m0Y-D4^tt-DpAmT<k#o?uA&3QW`JCB~L)*i^HnY9J)Z<)(DD)
z;(j`u_DbyZ1sbo#_oorl8}Zf>FyD%&>7dU$as4AGz853utNB43G7`)p@kv#HeiW~E
z0QE^+Xh9nmi+*L{#b@z0<(f;x$v>e<O2w-96)0AJab{qC72A!4hxQdxbz14UNELzs
zx>A}F4(=)`o>t<krH`~{vqtjp0jR6AjE<77l}3d@a-CGR8=7mqR7y)(H)(i2ENzgw
z(diR+>Ff;Dc}T&VVQ{1L2*2y#Hc2_bP~R-sX)D1~%8G`bmt8797^2?NGMZ=mO4Db-
z(pIU{U#RqxiYSxoFD1pI2#|97z?nelDuD(`&K4L9mL_?k*e3ll8qDpIc`zC;L~7Uq
z>Y>t~b3yHpK83<UnDjS(y36g9jI=t~C0(O5+-}K!xg+fEk$$2BZ+oS4bbtZ@`M||}
z(r%iq@0Xf3hTjLInr%TvNRf1$;-C~V5zIr<`u5N}EWJMpDpFcSC$Eo4dyl};D9J>#
z#-q~B2cV8gTwi#2T-wqN>e13D%0tIU-R-ofi<P3^!Nn8Om^t8{lzNQ-=qaiBZZPAd
zpALa}S~^Y#RnACiIuv?Vx=xF-b5h<^fW}K*Xcc!}+Dtj$3({*!D_@i{|AD0hsnve?
zbV*`9qPQ%%2f>*u(u=*I5~Y<D>@bleUBomT3*)8K1FuWjlvKYVWluvx-IR><Zr+lf
zw}WJglwpIV+fqDz`|n6q>74OhY4Ro*yeFNbcQaL*%|P$I#CHQTO)5(Vv(lw57NBHE
zADaQ?fpnfSLJy^-hiU%wNYWJ{icIO~49Gl|db*=BOG=?YvnA6~MDavwumH@bQomS8
z=1A#p0rO0{N5^||rAx;kk|!;yfx73CLYej#QonHkdnxT)j*#-D7}^jnkOHTHDwOI|
z@k+Xl!x1>=A|0o*Qg5VobO7wF^lL+izLToZd-PtaM4QGRr0|w7UnCVSM`$0VedPWp
zNl!y?vD9P&6h2FtiKr`)uFL|nRN7CQ4_~DAlw$uXUGIas6|z5BaFL7YEb2=6g$5Sv
ztK>+UF|C$c#6o6`>__QvS9uU6?AOXmDfzihE;tX3_44UIf$c7zoB;(7`S+oqHp*-{
zz<A2nv!UQ6FQLVnx4eb66ny2N*$~+(|2+u)`pMjMFazbbbf7p$9<d!ouw6d>C(01{
z=P57|Dz94ygFEEjv(Q4j<o!vYcFQ5}ptwg)r)|4^@=_X8_RE)#fq6jA%7=*v8GEUC
zE9B45@L&$fS7?!NSiTqwXCmbll&v}<bJO5xl<XA($)obRJwQ1okNlf<OODHxD2Wp-
z?`jTbVq{Y|G-BnP!zfP3<F2Caq+IC(ES-`&l>j?Vt``mJwA?xeZl96Y<U{1F{PQq0
z@HzRIcmIG2c4ZQLNs#~A3wxL3Q_au@m*u6jKX*lr=?goFav4gzCCRfpLi?&*fnL;P
z`AI53uF2UnLAx&REP{a>a)(85B}LBd0qV9~o{Bs2nYn<zD^GHVp?mUQ_~|fm3OTe1
zd|w`Er#+f9dD=rLrpw9YA(J7GY72u8<kssT^H6?Cd!3Ku_{XrDDW9Z{_gEg44}~nb
z=Q{YCEq|iq<r6upCG?)kvwi|*j{Hjqz@Et!BsiKYH>RU@dGbs;z4=^@pvCJ8`GJmB
zrZ43h!2r#dmz)N-Kz<Ye#X@;uCYZ0}E|jo)Eq|gZ_ZzwKKWLJ-@&f!V2kxERlTw-Q
z<y`u1eUOI@gL;uXWIgIW%7Jy^;U~GzA}AEg2Wc(zS#C^+%u8gyEvPG%)1v4E#TWS{
zoq7B!SBnSQ3gsT9mt2(4=FnKFoTe<p8l~_nn666iH!!hQ*+!3PopR}SD6Cg9Xg|?S
zS=b8L8x*E5^xT!3be_sX38KaIM&+y)BAb*CmEg=~rRHXs_f*O+V(?~rDP?G)=B+#$
z2Mr%3;wxabD7|S(@2iwAgx#&m6xuHHQ*JbcU4Lb}3t$42-)To7P$_4DdXSR+7|dWr
zNAu`y%AeG&wkvMl@IFLwm0><q>DvZvxI+n>29Yo&i&FCToyy*>klCed`~vQ7C5e)d
zdz4SK<Fi*uoP#1<iKHy=KBYd51^bomX;3(z)Ta%-2&LWvz#LRg?}x}CWqyA!4=Y8q
ze2-MpXb<9uBGC*sN|{R;`lHHy4w%u(`>LQ~?1~?4xx^}kZvc8iG1IR*PAW|)F>*@T
zvK%mRN&syuo>m?l0@@j+TNcpHDzS7b_MCEs(nj&h8QNAkudMMz-34W0OPIK*eAoqr
z1SP9Eic3n}CQ!Jnv^a&jD~f@(Q4<w=<p%IONohnY->Zt1u#**^Q4qbRY^AO2>&i^p
z#l4~I@P-#R6+de3TgvZrt~^D#;{|_jE5BfnM%t;i3JQ0Xn`cpXPpM8Hx>V(8M;N@X
z%vuJKG$rUNMADT%2BLVVjI!^5-;b0EPa&GA{QWbEY(+H-=AS6LY5DO~`A9=puHt+U
z%si!EI24~NMp`N4D;1W&wF2eCY3LOyxkC`>8>Q1w7<{WR#~}Gmxk{tJdqqRT(+6e0
z8B~$-=K*+FtTcXahv;Wz{A9qCD7EO&OQ|wI4NG5?gS8>^RjJ3pixs;2l-_mGtv(HE
zrLI1`+pBaN>0Ib)-96gLTcew^3JR{e+V4@fR+mr1)jHh*{4o=5y{<eR7je_+N>H~!
z_ihbP+;v@&1-ySAy1Fmn#YWxqs?gu0dp81Tn{`XV;Hjt1nGPL!=}uF=z*|?P1w?#w
zG94b-qKl`+m#?mLK0vqXio-$q=~~h+Ec|tiUL*PdU6MQ019i0yKqN@_OC=P+x}<P0
zx9PStrZ4MuT_$~FLUeKT=7j26u7u(aoeOR8hUtb=#(SskChaQi(uFkz_HLb}0zBNK
zOQBP5dv%^FP~p0!bh2@uu4q5KBRYRN(s4k?)1!#crME!cL0tsx5gpQXq|;nSbUs<A
zvq$N?XwW^X3#F8GwC)I<hl<f{BA;S)88m91&=u0tKB*gV5|XEM&R2jPr(04Bb*FVR
zo5G7Tx+Dwq&gv#D1L!&3uV0`LuS;zROXqdFW!Sx-n?VLI>aKVqmIU1w>Q9&Kx<jo|
zUe-;DKygJEeHI#tx^Z;yC`sp63dO6siB(`JSvQ)#kk@oWDbaUb$BqTs4c)#-pxxBH
ztP7uR>2g{^FGY8eaz(dw%c4+sN4I4qB=72`uE9gQr_0&{lvJIanlfEyFQEPA3|$iS
zs|UJT5is~rXBEMGq#K3P>|Cbq<V6(OIz0^rPjo4coUE=bWe*B;vzMWr3U%v<`AXM>
zK4Y(Si|+&FjqcT1V7}EYq=O~zbaiM$^1W`(bF|?H-K&}iqDYrwUjR2g>gwB|_(?aH
zGAhNo?TbNu)^(@VREcird=#a+i}bUHFFJiD>b~l-KEeD7eP0^&T=YRMu(VP?o3_AL
z=?74XbhUn31r%%agDFkos((HV#ajJ-N(ish|II^vz5Y@Lokw)jUtbEYyZ%*Gz<B6?
zY7Nkh`j+1Fc3AC0dw}rLZ~Oy6c<aZ~5ilQpz2Wd>i+&U(4}A5`bntYmen)Fq@Y6ff
zzLUTH-8?V@^mobKK)ruupakiAB!CLm=P1zIra#C7bGyFs6!;mUzevB>2-T0H6QVox
z7J9S8^se>_(AcSeLG!j<`cwU(v0LA>8~hB{-y8|hefqF%p!Vy}X2Pcf`nZY^iO^pu
z1BHY7=ahy%q;E!Rs>AxeG_8r$*FJ%ukLYzZ;YE~wP+w3-^`kkseN4Zo0A3u|U!pl^
zw0?6Fn)%1*+tOj8SbZ4nP@T}1q2$0x{dx`Tp3>Lb2mLtx@erV$)*q!T)*1ancc7is
zM^Q53oW2S@x_Etc+S5I+-+m6%1%2y1@adwy_C}~D=r7Rv@RELP7FzAH-dByfD|)Ye
zw0oSW|EC2slJuSS!u(bJjNu47S-<lNnAh~nwgB|HzN`}*y`i@V@ad+$Elmk;=@0%1
zM^p4!)LggqZQa1UqmQ2s6L<B~XlMDJzJO8$srnssZXiuR(FI<l>n+CsmZ5)x0|$2Q
zfj(|K6d&q;qeC)}^l}sUmZ{%B+1$r^^+1H3rSIJs&SdM)PKM+Y{RW)S=AP>3(JJ?u
zzD*<y=IT#W05ebT(-R8M^%2EDd7<~afaqW94^!SDUoR<8FVLT-({P3QiS%1n`zyU?
zU68N!+o);Y=qIQ_z1O#z4bcz!r!;C5=|4P1-A8>@SNQ!&Uxt2gS*$Ndr_w&_?+t+4
zCHmqHFj%T@w-KOU^bMyV`mcKTa1<*H*Lg5k8Q#*b`&Jv)(vg=nhAlT?$klF`p+ULU
zQ0xJib%tTI=eXVwM%imO!+!jE1a5=jr4b_ThU&CE;9>Z52qGH|m1u_QX-E%%h?imM
z38;G;is^WlkKrtxs@`HKsD!Y64FNa6+-lf-7b1R!kdg4h-_T_biU5PXHI1Z!h6j}I
z2r~4e^h2=W+A0{_X4w7$2DckJ(MggJL-I7(4K)N%TkJ5@qN!<^p%a}|+i5sOon@Ed
zA4-t#HoR>Bkv)c4JD|7M;Ijc>;fB$48g8G#LT4BE8+uR!9WW%@d%<pm!6gJT2MrCV
zdmS>wmH_6kVUj0IL>k6^g{Mahn`j>-%5ax{hI-VXegWn&!)==Q9XH&i(~i-GTGSt7
z47mX?A8VL35tt_oR|mkgliz$gZOEjt<cuMq6wqf4XZO<1#W};Y=^*0`b7}r}-VoUg
zFc%E{*8=;Z!J{iIB^b(<gNe(Ap+5udia}csUL+dcJc4?XVZsYgR}D8JpqFfD*$<M}
z4cdO7ZWxBsbG>O8SO<Ey45uZ4r5H|Ap5wM*a&P*D-91Ci6Yw<E(1Vs2_YKP$KtIjk
zTNN7Vh6&>!nqfH6747xFAlHHZL&I{~e0yX#Li<~phOU#~=wm}Y9tN`vvylMcvJFZu
zz@8Xp7XbRHVM8xS<`^o_`2WnX#S_rEhRN6qv~ziezcWzz+<>!2cx4PP3lP&wLo4b#
z`G)7-U=|pTE&^3(cv=YTSB7VlAb)LW_ZmKZFg#JinIc02%8Gq7^mzg1Cxc&Ih!h+A
zs{rh?VG(7DOAO=a@KdQ_H05=^7@lC`gtLD&G$V}_#<n5w&Ba)yIx1Hh=U+tSDr0l%
z$g7R<*<h|UwxU()I%9`8D6BVLqX~(daT(1*Hy8s;;Gw&5B~2kbj1vmL+-QuU^us1&
zDSdpsjOY8q8E@l~DPZ~-U#20JEq0@wcD8(tiL^<v)!45-K>dtvbs*z!oVO7M1B~Tv
z0W{E<N_K;c6Y@|58*5SSKE${Uxlk_Dcu)Xyhfx~=g)pP@Gf+E?zaB%e%h=C~XRzB?
ziIRwWjNz21*lYZ42keC#?bE19_ZhVx!QF3M@DWiQH1cT>J!GtM8`NQA!XSu58V^t&
z?TE3c9weiT?K!l}QR5WaF*#=3HWdCIH$K`4$!KF)nx(`TkJ2z3Yh2}ux)a8u3W}4)
zpPvBwl(E$y_;kj&#7<jqXN_CWpn=aB&#Z*|@kY1Vpw1inh%kS_sG1ME7mX!dft_Hi
zcL;TtjDOIiFwr=J)<H?ehqQ}x)i{D)wPfRtTrjU0H8f6LH#VfK$qi$-;b@DS#tp+^
z_m;6at-w=^PjArr__opGBe-{rQ})6{s&V>wXxuk;m<pLRV;9=0OgA!(p`T%VMUD8t
z7)tZ{helt=JjxiPL!g<)#-E}0*qBIrL0LvjQ1KoZbqj%#W3-nA^O<p80`zi?KIfs3
zXAG!C>*MFfn8Uz+VI0mO(3i%mbf6{Q=t|j-0%Mz62(-{Ry%fw>Mvn;qeQjKA0L&X>
z+GDu=)_80du-_S{(sZiG*n$$AAC0SN-S)}YYY;3I8>=4$*k@yF0n8HPJ({MJ8b9M(
zZs)!jQ@g{&S7ZEga95gsqRzU?)PlD5SDR+mMBN%w9DSi(O_zPZTx*&~lm2xk{Y%uX
zH{~}+;b!`oW-=R0CnzK8Zu%t!Ob?Tw1-02^r9b-MX&QSF-g}v@r@;$vQyn@TWA`zA
zrsK_9OjAcg!`IZN9k^RfM#>BOnUc>#-`{j=G0X>;{@4bXKvVNnh-@=WDn)49O{0sU
z7h*D(pa?aU&{pLR)3s-Ku3@IS5or9KrcSid+GXlR@5pY`sB~cNF%_$zzSnN*_zvwA
zZrZUA1`n7%$ABAQ>hc84gC;-vx*RgOZUOdTQ!afmBTbuWd;EyWXCly|Oht5t|EOs}
zC_;-i1=1WO#`KJmII*TmV}NqPbS@j}Crugj7adNSs-=R8Gu5O`q|+w5E6q61m{iw*
zeb!WM7K(GGFdj1Trgn~HwkfhdU=mEnZ=kqjT1Bh4%ch-;VDO4*;NK_`O}96qF3F_O
z@q(+SK~>;dvZ+Bo7`$fsR0SbjH$}Dq^M=WX&ZVT7CY=R!+qA?^d-Zoree=;KcTM3n
zK;1JPZ2&J)O^2x`-8U(eg-J8D+yJz6(_}ifm|;3G7zz(e&K`hyX!=?PCLWts7~o8n
zsrMYHXPd^-y6cH4*b913P1loA<d~Y9pzzF8m5zbrnofJt>BT&gmX4FYH2s6650`Jc
zOY5itQz4yOFEs6K2$5GNVHK#?ri|Wzd1I=iN2|Rxz4nB{JJTjwnZ7rDqTT8brl$#T
zt;n>WA}lr?rxf{T)0&xRnG(|=`gKdGDPkGwzL>@jp!e^qscZqTSD0(kB*Mk)mJfp~
z%_;O?SD6P7Lrkm9?eR-tZjHGrO<vZUtBr-en|ZJf<~NwPQrh0#Y^8qXVSYCc>Ko1J
zMu>Qt57Nrt%iNyw!QSRJjUeJ<F82mrY%!<I!{6QIe9dzXfV<V4-VSJf<`y#`>TeEf
z2>k%_U0MYOnwt!VNRasuy*a_=!?eY<&0KyWT-$EGM~TM}^JhBS7ivy@4D21|el%|l
zGxrqG&O6PwZh_imPNUDsZu2pkD(*24j7MSLYyLD6frguX5}~-yTyzzn`^_GdcRyer
zN!uI|W}fDl2hH_EpmE4tfld<~Ht(Sye@2@Bq%`^wb65IcMwzX2e($Jx4$T;knJ>~~
zI&S{d4GPibu*V1~#(cLC>SE1rec|>AyZN#!!aiwsn~UO<xiYPp;>;^(t##V`fTlTT
z%q5hfJZm09n-}NIhsVQGy!lyIh@3Y+I0)<u<{sM-#6@#~0n7yRxuL+mWFFQE)MfM8
z1%SR{-dqLhiRRd4P)IUgOhnyPv;F-&xR`AA+k<$onTPiW%yqNpDww!oK0x~;H_bB~
z87cFbdVonWHyDMw+vW+MP~0)^&VZ%6<~ae-yJtR97R*$0pKZ{)Z}x}<m1f>XgHXCT
zop!l1%rofk13WON&}aLhxt6^cGLOuIcYw?^*Y$-{kIf~$Ad_YGcmTz0^Ub~xd1BsJ
z2+*fyPx}1km@AXQGjn7|P|wZN$3pUj*@J#e^3rV2flv8n1D(h(FgwwBQD~mq6~!y_
z=Toro+Ps32PH)UVH>dC4TeH>)Xz$F-c9?i?E_Vh7KbXU*xr@wc!Dyh5W+NT-{$zej
zvxj1{t2fX-n;#B@!4mWET@WcXul*C)U(BH_?0z+WqRi?FOP~(V&c)K6(qk(v)9I%N
zt1OKb)UCGs>O!X%*I3Tce9+b6%%O6vr9Gt+*ICLu0?c{~OCyt;Wnm`tH(30;!3%dw
zbOT6wSeyrg+Gz2jlPH@k#dHW_vt>86x~HXV8#wA^8Bc%P!rSs|b1;1@Ni<E_V(EPz
z>b{m?z_fE)Eyrni_p@|xg$aL)nO1cHmM@fK5460Zk5rK5cN$@WEq;GPahv5-ZNO}|
z+@xhfh-D!SG@%w-ODOEHtnvaCW_ghWu$`8}G|Sp$VdkTmcU!82g4$!r>kn$LrFS)`
z+rurJX<K%mWz$vY@3$<YSM`A9*HfS(ER*Q))Im!D?KB^<JpF>Y!xm?1;7H5H5peW~
z<tuHgMp+syKwBKObo&78W0oe=EstBK-hz6xWz;rUh_P^#q=>cL4o2MxOZ7sipR`*V
zBmn!A#Z>`JoMny;`ll@`8CW`FQ9Xj<S<9e{&^T{NeFBXOmaCp{?V{x<P3aRXxwKNe
zWXYh@WtT0X^ew+)Swm+|5-pSUfKIYl@k?&*szpt?)MSg5y4*EOi)z5UZm}=D1oDO@
zg3guQv|Oa0Al$MvsfgxIu?Upkx@~Dj-Rq8}H|6i|T9W9u<M%B35fDkWXxl*KzNI5g
z5Yj9GEY#C26;t6whNb2JP!BBQlHm43OCS2J-Xn`R5LBimX$kB-w#>H=0hwjlp#gTb
zrAq~%J+YML!>6Z~a^qns$5L?|u%B5z)&gj*rHFRF^DLos7WuiQc|YjAusosjWG^j~
z>5xOdrF{UX0*mk-l7*J{$Kb^)i+c+|zqS<7e)StmR8v@ZYq_+D8snX1Fa4zKz2(SW
z6dx?nQNS*;G;0FUkCyi|0sLgiprv@R<(K*p`D}S<K~ZAqwHw}-TE_Q*$QMfrb+50M
ze^_9yu#Uci!o_-&hZifY9%rGj${J5cxK>-8qoKFP+Q=DyVT5zFrf-7GT5DrkxvjJQ
zMKkR6*2^sc>SmosC&4yYTc^UjyR}Voz<5|)C}qCUx{C(gP1ejlC^lQK&^*x7`hs?f
zy{walLd4s8{!f7USo_fS&K7IYY!trM96Bz#)hb}RZRh-~)tn*fZ<XB8mO<7@DR42^
zda^p4*=D^@U1+=YZ#wlDVqHuJ*g~z<Bf#8Yz5W{5Vb=Noz{8!^XUpKlE~{by_HOIB
zLGWUa^(w6*_gcSJf!%Oxv*pm+XYEZBg#A`8+KI6ruzFO4OoVkWC7KReEBis_khNVd
zWDZ-`(cza!YZVInh_(MLn253(+Q7r3)}=JlJ!UPAg8FgmS8BCrYx(1ljIrMJKoM)b
z+X#{;taE5n;H1@%i~vtrV?`8kRv$fz({}6BhbYfj^Jx3}to0P7WY1X(zQR(x^%^bu
z&s*oM1KI_v&qqjJwC3zbU4r#>E4X&aI;uPrE?d{{#PhjgT}3JLL~9u3Ba*C3gAmeH
z>)`e<pKN_g`>@xn1AhU^b?dy@K)GSH&x}BM)9OPxmRr^;wDXl>74AaxwzW?!gm%X|
zHyMq8*Lpn}b@!~x@<63pYt!=PzSTy{)-<a$70#qv4e!CsuzsZE<O6Fe^|FW7Rv~ch
zk#!PH>@%(TW|)6$&3T5pEb9dOMU>grL3`lo6RVwaQBSRpX?rNg>TibPGwY=Da4pwb
z?G8ZmtW(`!;<<GJ%}-ufGe1D`rF9<t8Krz{lO|9ouo_-Lvd|ho8zQf)>X(3iZS6_h
z)^DscoFVzay01SXE3&3^q5R87Yaf4zezI!fP+4q^D1hi^Ybu>SEV1TyfWcC$sR5`j
z*4A|P`m425D>%Bs=6)Z+xY(x81GUojH%-D<*;HFVt+oZz!f%bO4CQ8AZ3!MwUu#P)
zgfr`GEe9d$^|q}x`U?|owi8Kkc!N!yfJ%2;T349&unnTW_OsDu$O5&=c96#P%{Db<
zK0IxMXq(2%7DZnrZ`*r1A>w08_D9_oTRSr(eQgWq9ocHTO550ew$jls=x^&g3X%af
zS4t8F+TLKoY3G7$Ln{L<*fySW4%=*v{1M@H+iw{tLTsEn>OyT5Xk^-9E9VOj!))G^
zWZ!9%Xz1Q$%Wn^Ax6N<^l6!0)4uHAWwwR8Kh1*`2hoybC&f7rkx7DXzu>-ayqk$4(
zn@Y=0`$5~A=O_=^EJZMQ*cRFtMWpT7dN^~$)=Y%mC>t{r%%iqs`ZHF?Y%?iEbKI6d
zGn!~y@Ohxc*t$1^NUW^~9Z5W48!;6=owQw`b1J8732mVeXY>6X>ZfhTnn2`?E%G!J
z&f0Cy>%+HmwoQvr8E>0*7@+5Ep_@TnuuUlsn2WY(O0Or_)>0#0vMn43k;}H_lo!8Z
zTS!0UPPAD<;6;*cChc}!wcQMbLb9zQ{XXcL?E$T-uG?CTguxp&9HGDqXY14h%v&})
zj&0(Nv$@R$_qOd=BwFu|?WP8mskW|LVClY1LuX3TY#JT(({0NrH<MxOL&rxR*perL
z`Oucv5C$LF`cc2iv=z*O-ecPcnl)tEmi`H!vTc_rC-lT7(C;mu+IF;sp&XmmPP6D|
zwk{V@nQQBk4(vSJ{GU+y+&0S$>=(A)8zJ)2cIy}v^KGZc0<FL{gBGKOHg-F_e`Tvg
z5B;^R6YcQ5v1QQ8`mJq*8es2i8|X0Bd)p#91MtDNHX7<hHrq~k_|bMzZ3p%zTlWb-
zE4KBc@6c!4R7%E{*jD!dv(#n_fZ`Wh&T=SzwGE^-#0n=<MNlqIVpqhw(y4S246bsj
zRR#uEJ8h$*7i*lF#KW$u(<K>});c}%0Q5R1{YyZvcbZB^=iHpc;dJtEgVUq!aNpfY
z5}@eel(h(=8=Yd)VRw_$d>4RjcJlj-!qe$k0?@pi@@TKw+bMMkM0}ijQ6gfC)51V7
zeVw{w0(+~I6bJKuPG$Fk@^{L0K`a4I@>7TeI(_wlp&+N+7PS8m>~x(rYPLCz*#HyU
zox+Pig*a)Z!i!L+<8)4Vhtu%`&<JyK`T~)iP97By_AaOU|Bs}rj_dOJ{w{PbTsZx7
zcNcS|o4L)E+nmnYoL}8^u3fwOkOCr&5=tW?(n<;vf`F8ybVy1n3K9yx_u22S^Sbw*
z^FHTZKF@vbiTf}C63uwb2o+}-A3cIe#4xr|TK6ntoZhLi3_mtl&M^kxMk|i-v>Yt)
zjDIK_mcXzjFl!=1wigmfj00|9O=eW*gC~XINf%|#Ggic+^8({@30PAZYi%*nG)C+c
zSkf7PQz$x%L7(JZc#$zh9&R>cV;jbD7<(wXe~D4}3`j1+NPo0EMh_j(^BL@7kOIaL
zN_t+lGJg6Hw2<M(gcU`M->CTb3S&J*ii#PHbr39J_>IE+Qbv>rt*eYC2dr!vV;Q|a
z%NdQ^(5hhceGHUJMjKVQR51b~uw2&|6F<PTYKF((7^`8lP{gH{af}P~b&NHKF;>s8
z+E6)R17m3e1g|ry=}Re%j6Yukb`v8Y7!u8lX!65a7(T}^*2;K32d1?#J_~?~cE%++
z<T@B(bbGCn@!98Ct}aH*0m$88r0s{^ZU){)c<>mnlQY@Ni2VmFeT?_W=kI4cZzXSX
zfFb)F5;qyLy8s<zY$0!Qh;fx-cf*XHCqYISZB$%1%J_xC#$yb}uVKtBhTRkdZZlTi
zgupmsij4)j!&pSV;ax`6bzn{~E>a?ElJTYnleovQ(tBiz;cNqArWxPj3m<s!7)f+B
zbe8c6Rh-;s%u}-V0b_A5VCEPe0brSDlqO=#mU;45jM*{W-UEz1a|7Ayz!Y=Pa%7sG
z#h4TG5FId%F!ybTfHTwn5;VCmUulGTSLT<Wqji+IGzIp$F<+I^`|lVtY&QhmncIE<
z@nD`Mf5?;hYXc;_nD2K2+nc$B@<Tq%xgw1DGPB4h^<y^Ei~2b8vp#g5V6K@!%b$5#
z3l#y(d8+ITWQr;LbBZ|`j!6VF?<_?tgt?vS%R-qAWAufAFy_njsD?8?OoV&{b1T(V
zL^3_8UOI|-{VdQ<Ge<Qb(agYTz?@;e^B86r!@O*V<vz=dC66GM>Hi$W&oP;eP!Y#`
zl`gW!GiQDQNnj?B=atBOqzWiW%z@=VNoEEega&I0(@NXyd8YXU48Fkp>nKPn6Q6y+
zqsBbe2KjWRXc07JFxUQpu}tP|I=o~tg`YvwMW*R3sLy5|@CHi`^I=NNUSckO7_D4p
z>l|3}m{oLc&1XtCLs0?Kn`)>pGpqlFT%ncuJ#A@4%v%%~zrsBBI`kGZ^=TL^VfOi=
zRmyzxXRuslew7QsGUm>5*j>(CdJdfx%#EjEVI_0y2(YV|+bJ-1jd}4^%&?m2M<2zg
zVeW9ka@8`g%Alc+X*!9qdgim$5NKdp8!4`Sow=8yL5<8+c~IEIoLL0Y%nYM+UJH}=
z1yr;${mUTH#%xM~d^>a98L01Ivfn_flW98vo4S}ylp49glvCYfH*+`z0zJ&9Y1isy
zZYsxEAJca)NI!E+ImQN<8Y}q;H<{Mwpkk2eeg}d>Okom0hne+-5FBCZs623#`Rh51
zjWJ(4g4QkO9?A&aX3m#`bDa6qD%g96*+M7#yUa3*)lV=Vq5SzIvzl)A-edmx7A%}%
zwr+>sY34PmI+$TDT|t?HS>}$%VbmP6(6_o^nbj{H0`{!hjWEf9B_(Iyk(K`l^f|F^
z(+}YYtCunb&a6+rL#GSt1m%@nS;<stc$9Ue6fAD6JCo3GjFm@)Uhb?jEU<X64pAt|
zljXV!8oXFqD&h2IMQw%#AJ+65%+Hs#$V$b2eyofTG>@~^l1qDn^(@^t@n<dA1%&~u
zXgVzfvfAkuND%8$A?A6K^*!yYr&y||0UFF2roxR7));vwp{&kMaE7rO-+){=E2RV|
z5v*}4MTlgjor0n$)~cUDPP0;!R`5i#>gkI>XIOn^kQmnacOie4mB@lbENl8F*mRCn
zMB7vxYl0rec-FRZkOWp9g}@S7tDl5TNv!v%R5qEl=y%Aau=a(a^E~SX`c%~gmX&U|
zr?M8gU@VQLpiL*8HS|9^5oECT{t2{9R@?$iJB!751FefJx04{*tRJbeEr%tgYP(CU
z{p332vYMZVraV?N<(2YTB686RSYz}Xzsy>H2r3F$Ep*H-V#$wTf>&5^Nl;(R8h8pQ
zB`k#*D5b3TnjTy5&cds#)86PUV`+P!shss(IM6CsdIr!cSsUo+RK;3PfxK(1ojzz)
zvz}Ruu^N^$E(tEIWrhEVu{zejzS<(SHNhVoEv#4SFqKx;Y&00#SZjAcUnlE@cqr&%
zZP!BV2J6LtG1kr6`T){BtbiMk>t!V&NVc$#^&4$O{VWC5{|&Hypf}=8R>ng7bp}~M
zU1$xl{@MpKhgsVx{yoAvN`-r)taa8`AwR~NzX9x9ESDYNxy{NtfzEN3@E}0%us))I
z#a-4Ry6Z5(DxsgnB&(Ayb=+h9x(volvHqsq@HDHX8)Sxcg05iCvKDhNcAwQmLDL5;
zhhtDU$4aCR0L|kEi<T{W#gFuJvSSxe)YYC{Ov~iJ9%n<ZBm13)V1*NV71f;|VV6~6
zYR>HMgV5>1R(%6dS2jLSf@g|-jh+cN_J%(IdW`)PJ-qJhNF6kJuz&mwn4avkr=Y=$
z-ToVhH=Fwn<b2p`VyLv;mz}g2XnyPgDnB{SwtkA%3HERA0>+>HDAm~quqOpT3uK2L
zhG{|UuX_P{lI^(#dQY+U{t1>~_99yD5cZlhV283xD5D?7=26}`oPFpgj76}Q9fJBu
z_SgN;5XJuIMY>vYnteJ7pwaApTdc(y_BM*}$FMVK7H8S|UqE8n|D$rebL<O0gENl(
zzk|SzXR|5toWQnEhKfYC@Kacy#9nh2Dw5ffedtVKpPd5cd3NHLu=fIc#sh1Z%1$Sr
zHI03Z((TrC_Q56$X0ZLM(adCT>cwCdJF5ibBKzgr=*(unMVB>m*c<4hJD1oW--4!G
zb|n=e6tH<bh+k&Ul)~&nb{t(*Dq@?jf#nKY>j`6u*&k6<x`h2IJ<_G@Cv>plD*NMd
zaF$uwp)N47oW1uZ*0O^AJJnfMvh&&@QN@112J1C8lWu!evp36NQw^I_4ZXGOJ4-<7
z*lrXtsAuQ8!NLaieK)XNXNwDg-N;@=^;%8r@<HfrW{=Y4#TK^G9rm`ePtjJ;#<spi
zr;~Q}5II~OY-uJ~JK0~Q1Fef4{3&LCgKeZ7Q#X6<3?zEk>UMzkvR@$gsgJ#ha`^ph
zTPi&rVDF|p>`iui1I!*|<2z1x@Yoh|poiJ@ERYelvJfnz>}QXnHO79ynvaFL#Wr0A
zxy}B4J2Z{6pPhv<ci2lR0D71G(HtzCV24r><s^G%6~^wdb1PxY6q`rl)9hbpNoUyG
zD3dbF9+6^(_u2EbX+2;YUPNn-EuzTgJp1vF&}qwAK@PMX=lj1Xz-iA}`z4m!f%6D?
z(2g7p9YUQr?i)dlaCCPd;ml#vLBNHxa}egca=!i-okux+RO;u(>CZ*$80XzDG3L$@
zMM0ql$GsY0o*YklDR^<7eI15+bL`fj<-=*+0~TKn)0P69ew=TqtmruBd&<e3;Cz^k
zMeygWrdUb<$Lt78139wA&=kZuxe9_OIsf|(ty7$P?}G$$WaMOra8_xtB%z!eA!vnh
zV(2vx&iR=FJ5iio+Kx|ig6YT}%_%*N))~%{QxxEg;T)&5`&mwz5Vpl~?!N$@bDZA_
zFsC@q;{WRTIBoO`PT=Huz`{gM?!RD3;>>>v(~>z`i=i-u^D`NGp3_Zvl?xnada0yx
zmJI_XjWhl=I@3806r{@FICOwya?Vj&#hS(Wwi##_IW>C$lg)XE@+vu;6)Xr|;!IPF
zJeL!vhJ|^Y-Hlk1e9lxZCR)I`Pm6e&^UXY3g`5}2gD&E@dw}x_XY?G@7jxd*3>76D
za|v3d9OEfKU*&wY2(2>CJG5(+TRBZe&<f5Ml>V;d^u$7<iesk8=rztd`dU>rXJ{N_
zHJocgXsYEr&4G$Kju(Y~>p6w=7&dUes)yWl&hzw2Y~)n`mto_)N8#OO&fZlZEgU!U
z3R*dSEg)?iT$;vn$FXkn#b5_VN8#O04wupnU7R22Hq{Nz)LrQ9=DbRUZ9Sa)lhD-5
zQEh|XK92WIkbVx29Do6iZ#cwnaz@|A)CM^=YAp8<M@a9QVa|0rn~iX+<Rp)Bo+k%-
zj1x!IMYlNTb}a$SZBE)hFlwB$=wE2M!}*N~w7Z;eJ;(%S)w9q$$>|}F@*Zbd3k0S(
zzkh_*G$(-Wt<P{;-C_1DXR$s0TK74>x`O2ar`}govCR7EIdIr<x8sDk(4H%#?ZSaO
z^cjpe!u^;+k<MJZ2N-kV=6b?TS8iQ5K#p<~4r2-2xE&NbImRt|4RY?>5^^0qxMIp@
zcyfhQZ{fu)c^dY4bN7=!=))BZV9b~6LT<YsH`#g;b{^+Gps#A3;NE>2F#g;)`i%x~
zyIi3nkb9pV)F7_d3}a4mIUhpdDX#Kwump3RE`fw_MQ5NQlzZ+11j4v&uR$Q3n=uE0
z2yX5!2t;xthtP`RuA>5+(_By5v!c1L4w3_VhI=mu5;5Fo=^TBQJ8>4q#Bx8}3Z8S^
zN_uU^amT6XKc4GPtDL~?B)LTHdh(c)xVj=tCYhU0XV4Vx>*O(?=PtE{F&DTk1K>>M
zzD?hwO5^UPXk$8ejNY0V+=y4GfFP4Q+YJ-5xQ2ePUgRF9NM<(o<|I0ExV;qfxx}r#
z0Kr_YJEctWxareq<#X${LT>@Linh1Q+>4ZSE9CAakGY5|co<+;xcBIARLphw1}G)m
zaVh~T<*uTOcUQUbsIaguEaTp!6hb-Ijy{B3!Of(b6P4UeBA8gk{q!glUgI{C2U^X2
zjY_#{xa~gxw3e%*++7`)^#}y&xvzf;lm_lP3RPX_{<RWgja)TF`<uA4<S{pM8GFIf
z!Yxvvh0<z@R9V}&A80Y(c5XJ^XYJsI(8<4(`!Id6ql^0|Vc+2TQ`vhrS58;;dbsOo
zWqP@#C6F87{<RC8H@Sn(AcNdfchEV+4e9~PFqcgp!w9#DZh($*TPf}}#+_UQmRnq>
zZCIe&R&M+kXpVEgIuD6ETvZ)-?sEON!NdvfXH?5E$$gJ*)!pMhp!@Yx+=m09eww>v
zJ;r9Z8z=%Z%WeM<Ecdye<H)q|0k<>=EOXop3QEm$Yn%aQ%c~p$vEzML51Z_Hx#T!F
z@T^<kf^Ckx)lUN3iFbAm5=VHtC(!B4TSJeb3-6aQ5Le#+-iE@XyqD>v;>P=cJmzD(
zm(~N#op-Ad0v<d$dCZ=?ZV_0#cnbz#j5p8H1JitX5fmx*<-ODZFh8EN0LC2W39WQq
zJ;B>TQEY$S2XrtG;HA+v70Aoa185Mh!yl%d<h|(((@yacC=4CUbJz{+5Z<G)7z^c{
zdlPbDyk96(70&yLvQH7b&=;U0lDFX;NEB~c3Axj}MtZ2Cd262q^cmi<<5sAT;ceXw
z!Lz)l$YYM>9jbx)bG)zVwHe0?b^>-h?=U@^3A{~IQ<%v6ZYA_4@hT`4m&_ZZuv-f6
zgGZqEJdZsMa)D=}Xh|yXTrf1H@#2?5Q93Wa5}X-44khw4dBS=sAkX4e)3Ns=?*IdT
z%52`n=OCEF`^*Lsmw59u-(22r>oJzc`;7LveBQoi&{@FaQbqJ--k+bMvydl~z_cRX
zUV159;c4)2EiC4Bb)xesZ$}$C%Xl+?0JEI;gdaL9c#Ea<iSkOGi#_D4c)3-W(>2~^
zs${9={YD3p8XogF1Z#O^boZ@}H%mK2J?|TOej9jlKd89Q`<fo=M&3@k1JJ~Kl&&f@
z^NKEEtcCY@Bm`P{gRWSFHr_Y%RJ8NXY=edl-Uf<{TRVBpbnNZo+3_)_8@z|_1Ff4^
zvkekGywh~p@8u=Dfw4Z`JxcoZ^JZ1R9^m;<b-+y?vjhTzyb&tk8RG4H8Un+-)sz$+
z;SEygbd*=S8e?O;PicR=#k0=`%5C1shd{=yywNDY+~FOgL*ZTCx}`vy;MIH&6_dQD
zpM%6bp6gDqO!2ax2HG_5of}}8;YHJldX~5SK49+iOe-+$2fQU4pm&ZpO~Jo;-s+do
zY0Gyx0s%Yz_OlSM=kJ_`g%12y%6d8Stsl~5KPUd7Lhu~nM+ZQ{nV(HLDHp!b4|-ks
zYqx+L<tJT4ryF1S6tIu+alIA~9zRfpF%SNVW$5(ee?WgGFMcGYJiPg@I{?#%|2O%N
zzWf6eC->w3KzAjM^WO=B`V;(p)&j`;^FM4uGl0MHCX5N>I}T&Lg7}GaN;%2bdtnhy
z@z>r*E13VnhY$$iKS_H+DBt`ENEkn21_I&ymndu(!H-UW`bhpmR5=jEU;Q{1=rsS$
zD2zq((|2L)48KYO62niOp!4-v{!@Gm#_?Z@g!*{?x0G8-;P0SNOd@|PMM;zRdmq7A
zGQayOI8*q;YcSFCe7A9kU*PY07^bE2_jp1sjqgZjtaSb@`adoi{05p?CVxW*jLG8r
z9RSNk{&^*)l+EApBNg!E@P{b?e2Je($CF(C^8FCZ<IBhy%;yhx0K0(SLr?5weh6I$
zDdd;7V62GWLh+<4{I4m!Ud$Ii14B#rlbtZMl&>9vrmK84g{I5+Efm5j=P#$yhzkCS
zLMW=_r&m$}rHa4rD+pfWyUk&ts`=^<Kx+7}Hlwqaf8c2tQ^$Xd0aDLDUjo4feldN<
z<U0RL`j~7ZKZqQ*CcgG26gKm1DOAwH$Ny5pgU1hg0b^}^+56yZ=kFT<>EPGx0O{m^
z`8dF=UHtbmAaR4g={cC#&0ljE5<UDVde`*wz21Ytef*1OF^hhF0XYH#{6so~+~ogG
zq0>RWX9hG4@s(}h9Ok>YL41VId;kka`D=`5jq#st1<NhIy$xEo`F|&2DaZLIH$vc!
zm4Aiy{JZ?5-QbzvM@xV`$v@}^P51bp(;hm-FQ*%P(|nxK@Zj-l{s8AJ{|^db-shK+
z`}KhTb{-}%$G?{i@p-<6(i66V@fHv}!4^88+6$8D_PvAP-ypC!3YL*u?If^%BgV9k
z2)5In?<~-M1mYrK(01u6SV%tmQNeF?AJ9$k7rh8P1a5tpg{R=xdl>T)1W-84Tks5>
zAAJP->FDGuc#}L!KS7}j1da>N&{cvHf|m~f#b0oQT&w_r?U$HfpdjC>!DNC2Pm{-W
zQn2m-&`t?5x?p0kfJZm0Lj-MKpcN`8je<>K0zLia!Ue<RdPfM#HlY<M$WMn{l;GYw
z5I8N!qquXlVBcdf=8T}B2V*gUX^K0a6;y5lSgha$a=p(9@(<GU7bp0~9We2NRim&i
zLGT+31}6$is1hwn@C20#B?|)b0Gc9LLXY8jfrR3l7X-_^fSoFEr(G*eP_-HA(*=Dm
z05d~ytOG2Wf<LLcCQIPd59o^mJ#}UaHU~mOj$nH%efs8-;E7Gplq-1mHstdJuhMTW
zUm&ATI2H&ZIzcWAZd18dq2Mqb-HHU^76@DsT)KpHE*8A;EkH{IyJ$l$6$CrN!mEN`
zk3gVIkoOB(<$@(D7+N7Xw;Y|7f`+#sUL`QL)BEq5;0MZ~RSPzSK)yy`N4Jz}1#MJh
zP$xLJ1laY0Pv3=LgJ3&tTh|3?pMa%N;QlDangol6FyCgu_Zz^{BFM7^SgW9nY7E*0
zPLW_~7g#8t-y!(-9Zb7ZP&W<nF2Nfbm}b2pSm+7cx&=quA>SkTW<6B&3Kk@Sr%#}!
zuuH$-CpWCjfMA3a-V}WNBv=LoAqubz3C2G|=dj=&WphRZHZ3swmf-tDblw(B|M!j)
zXlY^Z2=>ea?5<!l#akv|8pJ0z3S6lY?VjK{svVmW40xe;T2LPVG9&P&v+b;4H<j<+
z7c>uoJP=g<1Ql}vIlYYM1;#hQVk>O%?P^|T&8UNzqfkdF04L$}!{9g~ETj4xXW`rQ
z*t!VMQ&8De*x7-xqrx*<nB*p8vO$gsizqeYE-a-xt{%d}bhh&py3+D^2@g<+&08pJ
z0`U?4&4MCdp=LF}{Dj|FA#hxH+)6vk38BXzmf2tEPubT1q0WfGK;d7Zm|u|awFwBG
z6q@K+J|%pF<`67o@IgX^U(*>nRJfG3+%Vz9TC~E2fp1_eLO4PhrAXl=I#)yqd*}dl
zTDYHH?9sx(O8n){2o=Ns9VUfNG^ew|O;lnKD{P}GymLZ7@^RvXC+MqE@xn*+Sc?SV
z0{R6c3Kvo3S&}fx2?EK&j1|zEB7CJ0<h-!pd$3#(zW+3=NEL?DYamT%6AJNk;nGAX
z$`GnH!HP`by9RogvV?7vSGXuF{0*A2g+Ea#evU9e0G><29tscT3e(7k%@b~~!&ts>
zcpo$s2#e^h-(}%5`!Uf%;V)spE)uQ@2Fn%U@9QvDES%U1QX<?*H58>n<}ARj3U9mx
z=rZ9KO$+cal?&U?p;;k}Jp>h%!c+@js)Wlw1gQ}|{1@!56)t!Z3hRVv?wC`(a5@U0
z4Z?YPCtep`rQ-WWAwvkxCSe{Qq*=IwT(cHoA5}!P3X88oZ<{c30E*g$%Bv9X5c*PR
z&)O+ut%Lbp!a*&tZwO0iox6n}uEt=GQ2r|fdxhud0#l!`It_yT!q+J+J|HZjnEFlO
zQ*<mE6t)Cmori?^wip{0uA-Cei15QMfQ<^7rvN=BT<r*fTf!w@z>3>K9wm0it-?Qd
zV(^ae5Z#i!D?CE4uL+@!%%2nvYysLm;h$dudrHWp(%Na^z(1JpjPSraz@8N*Qke9<
zFi!`82SNiSgXV+*6i1jBvc3hFt!M!Ssq93>DIoTu_o;H)LDWEbM@Ny>kM5Z{iPHWD
zD~^b2pM`|8$X|;=7ZLLhnCL3HnFzF_qEfmw<|fkTV(ggcZZ=x(qK)e?<{>(i4E3I(
zU&y`o5;-`7c#A&U4=^7Qw+sTlqTP9D`H5!!#3CFQ8DEAmCq!Z^<;na-2HLU%L<iPj
zFi`Z%QOF00vgmYlQk1b7W2Z!KZbmCubeM|gLqx1S;0zUIlYbm0dU*h?a8YA2z#>E&
zDbyS(sx(7klt|hNmeZo+bY&=7WTBJz8PPMB&>16g&{?sFXGMZVAhDu?7+{|hF?*mX
zPPBF#(Befc^u#8J{$7W5N)$O#j5|prC(krlG(usf3nG3t#8X9)bQ>{EB%sUq=^`<0
zxf!BKir{97*3uJ~C1O#C?V_mC4`bOP^-8*pm?K&+ismKJTB_*C6&*-}`aDrpBqZ`h
z2^7IC5DAkpnaiRC9!R0+O>+5*M9)&O$rX`1d6vbZZ|PGJC88`QTBV{L_87Y=@~6~E
zndqZ`09`J6f(}j<BF<+Rs}!}PAOwd=(fd*~uZa#YU|Y3lb_&=vqDrbMsuhhY09q$H
zNr9Srk@h91ZxH3sPyV{7;wQ|$QPkOiu_lp_-i6Jg@2D!KMN~siQ>*Ao0!W)^AswFE
zMPqMZo*klffxzq({Z0W3YnQ0>C^X#=rMd#NTXdX*_39BBu7dQ6rr&~KpXep>Gy6rW
zDGfRx`kB%rH$_*+!7?cNg~CijqJSqcHY_Tp5ci1a<qZHE75(x6WK6`Pr}37kiYmWu
zi=Ms*%yCgVMP}|;Mc$6UzAKthLU2N)Ac;v)crpg>iI$y%rYVtUCa|YPYpBR<M${Do
zGAsIl%IEHjdg+qU1JOYWmd%N3Ucr3lMbB0N#a6uFI56$R?>7L<Uc7}4-45b52IL&Y
z9TX*X5?f!%0zD#r>p4uuSv*KL+FZmdDY@?|{(2UmN5vivXt{|G*+B4^*n1%qx{Dj$
z0-A^Tck(<u#qE^p_Y&(u!Qw5BAXn5!{1UxdeZ_tIVbck*rz2Ya;#t~z1H@@ma1$uL
zY^{fiAhG^&pq&(dngsb%;tmrG4i>w;2)!ZVhh&&Vs5t8wNSJu}7!-z!BPe+gAx`cG
zTBJDZBwA78qH?gD7I&=xShRS-$C%j}v4UcBF=9tMK%W&GL%|X&K0OSSbK*U_te|n?
zBVWLpcrj-mU=qX+Q;}z)IEc<sN#ekF0h28Lj5f~{F((H$ofr4M2e}Jk?sKp{Rs4h_
zK-0ueQ1T#Md?Oy68RC^spp_{;C<Ans_={PfTol_p1n6w>CJGbfh~M}xn0ZP3DD~!w
zcOHUZo_K)jSM$Z4cR>ooy)R<yvRM5*Oe+*WeHT+J5=RdM`-+&c2d!dp&-Y*{5eFqg
zQ>pkd3in(Ur|gBoGI0=vzRJa7s;aIK@1m{0QoPg`V^!kN!wVLCxA2-cnvP@D;x5_}
zYs9HPf~Qve?P{1<C$^k|P4(j8r!dwacA`-5b@9ja+HVv)(>b9@eCPu7Hj6csB5o1)
z)18i1@w;@dyG{HLZGP?ISqesWh+pyj5EaMV4uEuvrBqknBi=`$r(W^PdjZ)eUe|-M
ze(_Jk=o}DlKMZnH{1rJ^gW@-BVakv=WhbzP#bx`Td_?SAjImL1)7!9bOx#DIkXzyx
zE`sH@c>X(dj*Gu_0LmTl6SSUp#l_Zdp=m<A#DM0M*hJ@wX|bUZWJbJDfX-R5O&m<S
zFAk(-dLX{%1e@l>%@nDd7iZDGBeIn|)C#?JlIRG?*-I`3K!t<EK)b7><n1)HoFu!>
zfaQo}XAk}!&XVO*u*pU8@qgh1SIK^gY#x=2Q9{m5a!Ll6W0DYhnYl~;3WJ1)<VUJU
z^pvco>V7YYt`AmtOCI)z^*$2z6-?Au68I{{{3Mn1@;olt!b9tX<Rp3A{*rq+zzmQC
z6k{w<vY$=@L6Xy3DLsBt!u<)eI3=l~V#8p`YhQzeNWP^Colr>u9Sp)Gg7;xsxMTny
zLS7glX;_R_q{Q$FK%*pGo@kwxyidDSv}6&TgU(1sK7x3RBybegpOtK-q)e>j*9x@G
zNwR2Pijyb`ss1@$5=dc>1j!5?(i0`mod;-=ghhL1vgEU+Shf_&6NvylFL^@*`3sVY
zF4&tY8L32Pn&kVxA)YSbG9jKJsik*!req^s@W_%JIE1l_lD!{8E?eSw4`Vr!01L<^
z$<!1Cthtg|HC8WAlA8{N`I3ltfL$OtdL4^@S+ev|z!XYi-@{~zB#%(w`-)`AO6V<?
ze2@>&63Hs^iAp82l+L*-X-WoYnS|{Cv&$t?iY!)0_Fn{MrKFI`cB&*^l(@Vm@w*7H
zYO7?+KA_b|-r5MkT1g~@h3h1#bnvQ|Y-s~egTzcX9j;4O(($}ml0mQQ7Kwo>9a<%g
z<kq%He8w==E?MJ;`F2QxyU^;CRMT9#B%Ga4ctg@fb<^Dv(^**2BVj%dmR^Z<BW-ql
zlK1Js>z5d-V9bDI%LRbmlpLhJdQkF62qcCihcmGj!;%Xez>G-d-iK+Ul5h>i#w49z
zL+>p~BwYo$EqP}-#K$ECRP1|4qM$AFuH;RBj7><=>59RmB%l{I-IExt<hV~ss^7<Y
zO-q*1@qR{f@K1owN@^(hd0!Hp0)-DG0=juRCrPBY-@K$E3@U7;gB0kqlh!Q6n7wpa
z0>B)ky_AY`l%A0Q#YyT#Z_Oi8>o|zBRNe*RBDKwffUESaBnmAamA+4rBsb|{ik2Re
z`cn$sU0Olgl!r8f3l>l5UkjnoOPV(Y72Z-eI@b6|SH)o#zS1tb;p-<IqImmp>7IWu
zc0zi91p$BQ+jJ))K)Rv@V1d%UR<Hy~edD3%r1bp&3g4ZQe)1?321~u^hDM0=u{WVG
zRC<LfEW)IHQ|JtrdQG4eA<el1^^sCrN_<91Eiur0TAIB9lZlr8>kpPQ(s!uzB}RI0
zKjh9z<MkMem8OYd(>duNMWy1Tv(Lkrc<Gm2bpJd-+PW6aMCtA(@FYn;a)2?((uZuJ
zDMfmcOgk?vqiyGcbkRRBEmf*iqBBj}@ByqymkOx{JwtluC1}c&1~j0REq(NBXv&d3
z&j89LDPuEi%9Y;Fgj}99s1_*s(zz-SYk{=jYv{c!?XrWxh0;QLUlvJ!{u5|dqz`4m
zv|{O3N{|xi{v9Bt(yO%USEY?o$d^e!tO01bG@P#LR7m$x@S{>H{~r`qNp<zG;+k~1
zJ2X^FpG|<hHPRRk<Z7iz0pLlqN)O(LM7^}39SR$y>u6)WE?xH?1RJHFIzzBYx|E82
zo23d$(6vb2=r&NR^pQ@$v`K%9!&tl2RRHl0>3|PdI;H6w!O|t|r$qb>>1En|x}}C$
zkRItjlhDvB{e#?zKB?7~yw-kc0@a5MNdKXe(@m+8wyi<wTRKc_NV<Xw3x}n7=}<8u
zz4Qw}N2Sk2L+_aMqgqV+mh{j8$laEj=<qu(?e+oo9qA(4S?)>)1JRn0E}>Y{q_k`X
zDEFi$dPz)4#n$B*oR-@8qd6n}Cl#Qx(h#b4zc2l4G0+}JH_QQhPTEev&w1(3vzVc+
ztek?Mb~4)vsJEB7Jc^cstomKF9A*2Sg@sPC)3G2&WY7F}mXsw?0Ln%7Iu(Jt%1&H?
zhNCjZES<RAWSXxacua<m@8H3cC60i2$O7oC<SDa#0mMtThxR~k*{_E%<|7+uM9WuJ
z&jyU2EQgMr$7PLyShW)}d}0$1o~)VT$N{p8cVKUz%tD)2kSyUx$eom3rduW<vh68P
z;Q0%c#YaIfOlB{}V7RRO87Pd9{c<0Fkw}@d2!c^E=1wfaY1#Uxu!zyJjs9RcBio(@
z6)`fO%@{i?yJdx@SQ)Drt#dNfb1*bcW_kz~#>*BALm)wRn!MFS+5QorB*{ilz-C>T
zESsV4C#A?#6mK~%Yox%#1z94cS5jr6ZIDQlEuyz@y6lr`U}wlq6vMPkSppvdS+ZdX
zurJEy#-K1;=0W~Tj;ymAW?z!^QPMA0mh(C$m?v|g+(o|ZQF5{iWG9`V)_PesO?i<*
z*(1piERsF+-(4G7|NnqiEKB$UJS8%>{{kkm+w?=eDr=?VW0}l}>Nv|~wIu+pki`{(
zRLWkHL9R-cQ3K3tvOg|EpjsABd7K)Vu@+;sGK({esgr$o8WXIy%D$qMPlN2U1sJ?8
zD;oxBl<{7{44Y)SMF4G<MIp|)utm0}2CY`v<K$(x$+GAO-Y&B_0hkWiV)C*(W%GFe
z>yoJ{-*rP)OFye_*$)(Z>XFrKhu&UUCDrKk$x=fg*DtgFL5}T!?8|OQ+>~WfB6Lt@
zdJhsqG6!1jVOhg-z#fqut^~`dtoK7qZA`|yibc33d+H~2-j)R(1{s%)Er7rs+3p-z
ze^;h9L&bz_0cHCpW$Q~Zc2D*VRXa|}!sxd)ExT>KiQXAm+71{sD_ch1*nQbIjUW$X
z$r0$ZmGAir>h0v;y#v$i<tx3Q-a+0$l|qj48LGK=lE;zrc|^XNO6Q&BvVI7-$cG)k
z;wm4th1^kjP8Y0jlRr+kQjf{S<ifhkdr#4k!b5JM+=ZvSm5x_l@~-U=^p=;0fYnEC
zrM<{kzKKGNe)73I2ppH^W&!PlyzFhj_{+D@P0j#$&J!35lyCYLQwx%>T@8Vg@`ouj
za!USuGEjo$hv|k<h@4CHJE8KimGmFB!{nRD%MO=&P?bT1{9h%kh?K|Ba!1J{UqkD(
z{HwKCr)as4FF?=8r`MwuBR`b@g=gg}GBCqf`P+2BKPP9=7n<YbCvHGfygZ6_tpxew
zlr&6~e?lvoBwx85a>??h`bBvDQsjA*13WL62Y_6VdvRe!syu=R!8G|hF<?!XuQWh!
zhJ5k^U}ws&{{xsTxyLC8T$GnnmLpq!@hhm$k;mDf^OAh}E39Fzyz)Fy^5m@)49}N;
zwiM6>a$YM0F3aQN(6ScFpCm84NbcqX!7K9Pw5Jryzb7xdMBZHim{R$jXtb`%7n7G=
zCV!U?v~szZ2s5mZhkcIDO8I$;Ayvt*)9s6E@-5L&Q7x~Ao3gM*{-_!(wetOxxv7&+
zZ~;~?|DMiq4OV&DA*}Ot`FmGjO{4tJ$05-qf3yw~&2nim&|2iK8g#bG^XM(yCSQCT
z_O{DQGceX6e|QXfZ^&OJAGTW_NQaglc`rGpy>bI(Mf>D$c!RTFerg+72IL;L5V$En
zvkhcWZe39hGlt~xrH~kw2h+KEM1H;=gQM~X^cNYEFMkOvx8#2*fPGuOXA?Nb<xh0O
ziaYWg@`UfoHyJ@D<U?nma8hm`2Xaro#t~*u$-k#S*0kK0oXHva%66d4%4?&+a$oLg
zrOzlmkRN;%CeF!Upvz42^4xi}Y!&sC7_?K|a0a%$;*|zSI4Hu_q2;JJ%LR**!r2Ug
zBZ@10fI2Il;iBcDh$r{NRq+w+T1OQ=kHdO5g|81-jw!ZqFy^j!l@1*qih>3!csv!=
zFN1g~RzHD3Z$%TOIeZise6R?<if5bw>ZdSY0y(Z&uf&{AC_4TDsK4TO+GYb3Z+!#t
zK*b^2?t&EOufyz<iZ94FJf--P4y?h7fNCfVQ8ax9%uvNHUv!2kBx-v9g)1K44#5b;
zD|8l!R0Pt>Mk$6Ux_w&lEj{AViVq@T(;3BLsuPP*Y@7x;t5{54cdX*jJz$?xG*j|C
zPSJf0BwnGR{855pnBrN9iq5yuN>X@N!R%y3&Y#ebqF^ANY+ZO>vD6(B7Zh85#0sS<
zMl!&YrZ^Z6&~&h3EJNW<&u^xJPuGpJ6s30odQq{G+{kRj`98FA6pzz42`?!Mj)CMV
zUh;*)JjGhNy^*gt{TfgT6*~hl?IH#HXK1*hSW*OHEmlY(F_{vDkTNo*igo1xy{Z`B
z0GKkx05aSQ%N0L~U|NMDpNeWL71yaeph}Uag8Vhb(Jq))t@x=0DryuA`UTc1jL(9z
zPH~lz$@Pk>^MGzp{PPFMb;aJTU};on=E2frRRmrITC?I$ie$AY;(msSt%}KISfMsW
zk_=<*ii4D{>rh<y7h|1@Q}he&Qp9xt`-Y<TIwsn!Fp+!Hqd5N|NU!2IHpKfBC%*;h
zR|M0cazODprIT(d7)>C9iZa?ehZNR*cY!^uXxfY35rr2;nMV~VD`4B0!YLkTw-hha
zQT4XsHF`CVD~jkM!yUyzdd1#V91Mbm6AD%h&?XfJvM`Bzid;GnO(}lq1esPGrQLEy
z@fMwXXB7wBAaGy7u|UxS#lP0I0G(5mzJ}(!qL7L<ZIz4Y)`^{Rs0}T9rN#wg4$3@A
z<vA+fqW6iDGM#F<jwnA_4&tmV`W=5X7v<0ajJYa}RAPQq`4!btx+y;)ultzNiSo_v
z%17S<n1`~D0!*IDihL{7dnt#=hwxU~Pzb?C*+s!JU**{zfchz;s1)Y7@&dgLPbjk}
z&F-&^^M-{1O8;j3MFN%Cxd07PvUfn>q%xEa|EHACPk|*^i6A5%JY|V1NT~9$b|?x{
zzPtlAg)7%*lm8c?yhAy%NaYeQ3`Q$CzXIlr@`@btG0F(aBAit&Z-(Aj<yA^6ol{!u
z!4ju@osKf`$}cD#m7oj@fk2|N>PHA9DU)NMB3b!1x$r5<kjt3adF6N2AQzO+P+lcf
znTt1_bzz#a(+x1`$`4a8n4#Q@IN-ue<+l{M%TliU1!EVLK~!^>t<0iSW{$FxUIdqv
zo^;mBRc@jfNuKgD-5JYQzWF0afwJr_<Sr|-s6?tzxwr^c6e&NY0`4oyzjk1r#mf2X
z7_*irc~nhXs@y99+EwL<9R$micj+%$uG~}xi3;TxrD#<uZ_rV(O4)4-fosYaX)UXj
z52(DfM(IgMwpwLRBwBUKcjCZVuPnO-(;Ae&EyCD!<-cjLzERoYk9jsJe|a8?nyt#)
zKVYy$nYasst;!Yjth6bsrGRNy-XTw>Ln$7^l6ESOj6tGH`3qHs-BA8Z-)8An1|0`W
zkMgfyps-hYn!JTRW#x+y?^g;~FmyoaxEm9_sWi~{H3pTogU~RfJiY{A!%Ay0c{wA>
z{US_eR2j7u#*8VyzKp?J%81oaaa(!sYmjlJS^;uLS+M}}ca<r<AQQ^kCqX8aJtio;
zr(8=PJeyM5d;u$_l?hEinNem2z_eNAJ2?=)uN<S|?gz>b;-P3x>1TZnbY59W*%n(>
z&L*_%RNO})VXyk_7_c2w2@DWN)x;|xPO6U+Fy^8vy8%tEDgzsuj;aF1=yX$k@)gK2
zRo-Gu)Lm6=LCZt+HkG+}s@|X<x0gz!fCg_>QYKh@R0Uy_`1Vzu$j6|cit{+EIIi-d
z%FYw2p`T%}zbari#sX9q|Aa)KD#iw#L8_xU06nSV{0MSN)jNXO2dfrF0W3uI+Y<bc
zLRDeiP#>mRP0nPvYTW~1MyP)K3<8m=uoY-UsSezt?{lA4B|QYa(W-ZKz&@ke)D9A(
z8m2_yS=C_<^v0^TJ%Hdj)dy6_6Q^=L37g_o9rP<pP`!8&twhyuBU(wS_4WWuR)x}r
zoTB>vBv$Rb>LyhLTu}Lh;xCe_TAl%vG*vpvHmnQNRRi&m&rlW4K_XMNnG(5KsyFDy
z;6>HQX`p4R0_hNtqY9yr<0aMO^is@K;h&b_!BZ7YgC$?JmA(vIpejg#_+`}~{niUr
zKT=qtNcD;kbGf4OBM-A!wT2?BC8|EEx3ZS17W)JHsw#LIq)g?u0~0M*6}*YT3RQs|
z5|yfP`f5Ox>g~JGbWP<$v8-wpKL+bmqv~1-6}76rDA-=7`g|PX^{O}NrP!c4_aZc1
zS9O#_u2J=|3j~@}4?hY;&8lr|bhcPkJ(R3%RSgKyY*Te^Myp+w83)p#3jZ9WQ*~Aj
z!7h~@9SLrz+&{x2bgSAj(AlHfx(}^hRZs-f_o>`phB5uBdio&^s$#zY%aAH47%ao8
zm&2iVM0Jz?Fr%uH4zP@=tnD`-cuO^`2lj2%#|ywZuKJmL%R8zdd&u8avAiKMp?dFS
zv?f)X>3+aH)$lV|pea@QVyw)x>clIU_KYf?&PB7Tk4n&aUzP3$=m#nt&1_DU=7_n>
ztA3}NVq5hliVN7O8CEd_?bUJg{5q&vRA1nzzD>KelUnx=B#x*Z=v?HiUP*}u7xl(Z
z0P3oKI1A*cIzxgnH}xVrSbt1CNm)mC_4*l%d8h+#VG^F|uPO2DrCvhLinsdF?;zl#
zX6=L(zUswq)At|z)VC?sd|Vw91Njr`mZu=^uYN$e!~nH*0bl~veg&{FNL}m!D^9AD
zM<IVook>T<V0Gnnv_jO^)}a-u4tW?TVd_ZQwZhdsfe?>S|2_u|k?J2P$PlGoL9xEm
z>bhlg+cR2S{omnI{c|nkW7Hq41nXI~mM-?hsuc;4Kc{w}EjUgcPIU?K>Jf_jB&aQP
zL`_s@)BT1dwdHG!C9B(R06RtPIt=ya)eeU+-wWzaGCNhR)&n|Co%kgL($$XZ>HU|X
zE@^^_Otok+B(l^VlzhCXev=D{Z1s^5tX_^<N-^k5>T7hs&sCqLyTo~F8>&0WSF0zX
zw?LiZ3Y#vg_nU!TsJ`0|up)J_57zLCnnB)Cu{wyNgC*+E`XOGb-uf?E)^hcH2bvY?
zS}IJdRR2mJXsl9yKm}sg)KYh-s8$zCz*3_wp}Qir>cQh+sZ)<oB(7fldMPwDsD~d1
z%XRfqIz2b43&l{_q>h~iO0#;|X>_)ziztHLs@^>X%r<rA2bfvARs8~8PVZ2AF9GRP
zch*6$OYO7`lewX8{sW-hYBzGEdeo^E5bRYybP#&`)aR(;qhH<pF0cpG&h)K?o9g{@
zkQ-EA9RnFsXYYsju-YR6GaFH_)Is5>x-J)BW9o^IAbv}2WmD+kw)!AN3&z!bR4Q^u
zy^Xf5yJ~m3{W+obrk~fO`tU0dyr<s!IasFDLMmFDR@+jreMbE*vCOKoeZX>G-AaYZ
z57Z-SK+ma{Y{PQRtH)`hu+=<YgO;5}{S?IQH4#=iuRCZyrU<X2W+}avoHS}W^c>L)
zUj%X1eDXK!cG0{>`;Dt6f?f+pH5({>;-)$EJ6gvyHvd4}T_dM=vWF(=5fD$!t_p~I
zX&T+3$y>whgnA!M2sxU*nrHq?)oGrMp!~yeO=ciqPG}19q26B;Nyo_m&D0){K#e>F
zV?i1<)j^%qq}4<IlqPZu#)37al$s3Dv>TuzRMSj*NtkB$09xUiFCT%u5t>NaG$S>u
zMNkx_dH*Mn)0*#&z_e)17Yh3R!x_y%I$_6XPEz#gtmYOiLac@n2>ElG?>f*rujyU`
zi3^&iT`|#A%_E)Al&NW@q(qix$pAPnYMOokORi>=qGfrSg<oJSUz18N_%e+t3VJIv
zCHufqsd<CKpjDd9_;I6rQPV_QTD9gt3$SZ6hxb6DR+B?F*XuOH<dD>B)=@<5x@OxJ
za5ie}=t^~y=5=~0Hfs*t0ceZnjZx@r)vTruiL`6BpFn4aMnL7XotlC$EJ>H<G`T)E
zH2xF|?$M;tYuDPViJ>56pQisP(E2q(I{6J~RysibrlyBhZ%~ut1c_lyD(%Z7n(_Yv
zftrtlFgB+7n2XL^njy-p-q!deL3~{EBb}x1Xco{9>8|EfCdMW-pG2ZHsaZuYf_ob8
z7h&j>RkKF|qoy^@bW)zta4E8NUsIt1_5;mBlwh6H>>C8@yyou_z}RXNB!IEg{z`!e
z2W`|9nC+<DO+KxYw)`9DJ)-^T7Z7LdvH@VaYJaB+$D>*^g$&)a68a>@F|DW^#9eDG
zBL~bwJM;tW_S8;MP{&)lVHTQvv@hmCldtyg-N5$KE~f1LajnA*kQ3TD%8&$Vg;bgx
zr1c}G<D~X4sv<t6t=*5YU~OV0z(TZMbR-DZW>bk)gtp2ImPl<1rA?x>uUVgj8E3S6
z=<aKbHp2_#oOV+Q6vk;|zk>RBt(AgMN!l8^p_8m#M{ZS$Hk*QGsanZukTmVwBv{h5
zPqEO-(oR$W`=Yk_f3PWA+inZ6Ty1;?^yX<t-+=Y`TEF{1DbUKI>G`{?ZJ-lPp>~?S
zkWs94q6)wgt=|Q-O0|3ci@j-^DMwJI{fcTw%e9e9U`&;^V>wu^X>G`tuGYR33WYUV
zofPV8wSQ9mMxC~V!nW770qqcP)ILSO)h4ZoPG_y!9c+63+O(^0z?ydL!X#jKX+Pw^
zm>b&nC|c01HBhR)N4xtHRP<^;{~spWr!AnD>ZrCL7M)|-fJ<PxrA?%e)@`kAI`ocf
zJ)Xtb9c>21neS@9q*LL9Hi2B9Np0X3pxo1*kEG{sN-J3dz0=z8mEf7tUZP{ttoAb=
z(C%wvDQf*do4*h$=CsmHAoE(4Jvwc5<v(I&?Q~zzMFD$V867tqblFsq>Zn^`2Now?
z;&sgBh)zHmN@txl2~%>>+04K+SKU*eV$6C}xA+`p@1}Dl2m6?=vm5H&bzgV^+e0TK
z6`nc+IW0cA%`uSo)m=Ua7C#*`ACoz*>!pCg3ElHe81vWFT)<d>?g@%>1?u+n!KNUc
zgieLQy1oJ!8lp>h4J1@&Lno*(tFCw&ixIBtSq7L0UE~E=5vlv_4A7!<52)Pjv~J5f
zfJW<NRQ7U4XW9b!7~LPw0Q;=&20fIqx;LYNa!&U*y-eeEAymSepnEYGBvJQuCIpgn
zoH{@!>;6aqONuU!qNu4l>vbwfO4I4cu}|0ic^WVox|n6ql&MQ0r$0;QM46I{x;I~k
zh1t3&I(X*jglDiMmvrmtcaf_bU;rgg_bngGm9Oi66)FmJq4Z2&)&+-w6zSfl6jX^$
zKmpHEodXpKUe)ce(#IRhbl*onqFh&X5v>YcdIBUWb>CG2yGplX3&yVLTGoP8>-3Ev
zH97+og4F8XAt$;{chvw=ubVgu(x7Yl9IMu(+nfqxnsqT$_|l>~LNUr#-MU-Q(5CC|
zfxVr&-eEd_cInR3oA!q8Z936(>kfxQzDM^r6@B;WOiMxfbb7j}*01~ccP#0Eu8th3
zo4OY%LOZBCKZ?#F-RF-$#jq~087L#VMA~0Rb%igX^R_Nq3S;i--umw-uQO5ra#9yv
zNY~fy>D<d8F{LZ{2P-tKOI!<0GrB!rLU2}RqsG{M9U~l_4|EYbp=nO%QGw2R-5ENT
z+3URzfH>$6dqbh4e*YI(ASeB!X;5)QZ}%N0>a72Wd_x!g@&I7E>I;J~!K3<J*u1O@
z-SiJM06nI^@-8IY^{-rpyqA9CcBt^ycSb<aM?b$4#8=;Z2*gicMpyEV>r*H=5}==c
z8hQiuNp#OANT0G3C@1xXIgnHOC>L}F>u=Jkh3O+G^boGs{RS%{^sm)GgEdkgl@Enc
z`o**er}bBT0UE7;j^gTP^o=h-B1ZrITaY-bpAQFGtUl8Z^F613?HS0O*H?WAmJ9m7
zDcqc@Zy~uf{dP}`rR(z?0G6R&Ld6=HdiNs8W$9y!z;aQ)j5gbBt3LN*&>X#ZGsq?V
z&1P7dtM~UpD^Gu&E?wm7lj)aGpnr*y#h3L03D64lyF8$xNMGcN&MW$FXzMT5*HZkm
zME}Bj&{V2_GZUs=)t{r?y-XkW0Z_{IOu9i;q5pdra+P|kazCb4rSJa^px5-1bZn^B
z59NT==#yw;tkwT`1A=w>pMo*_di^50xZj}XQJDL>K2-+nM!nhwhBoPabD+LiFQEs%
zMgJ7V@muxFmV>nE4}1x^cKu%3COh=rb5P%@Pqxx=qf39t1)6T?zolZWZvEpQpw*)v
zreA5VKAdt$eR_2g6!z=Cybm&<_n|_NoBDUl&>GY`bwh4Q-{=Q2thZ1&aYX+rg;+=R
z&nVCu(+_um^On9h04%rl`!_@Fxc<{-%0JxEw^5w=uD(+Oi3$B<Gw7Vur`uuL_w){Q
zM|w)X_X5bY-c$$98NDbEED!W7I_}Tux6$Rjd3_x@s`iF_+NT^0jzb`hhOM_joDBWF
zU^!yAOq-vxA?!zhxftxYRPpa>NL`GH9yRRP1XeeLl?k3>hRP2h;ciI&2r4`bLG%q2
zPs3`;b$c1!&w`=ehJnu^;A7a|h6VODh-okKGcfjIzW#;<l!gy5G*NId&=9d40zrnH
zBygTI+>M5YQ-&+JZGrFq8E!p>-Vnp5yTB7_SWiAgm?49LU*U$MD}fea*!eBSA`PvS
z9g8yjNZE|jhCMorMH@^@(K=&Tr3PrMq5mW}&l#4|z8q)hqF+M1;fD>FM1o<<Bv=v+
zb1N{3B!im1D`!nM1W;*RiecBk;5l!wCy(NSA+;LvsfN+rXr&qQ=%!4%Vf8{RLWbd^
zdoV52aEh)bWEr06L+3?900rr@4gFM*m}3ZB44W<){`V2=%{BZ(FVj4OfevE%2Cov3
z0>gX&OuK9~$SWXNXt?<a6c!m4E<*1W!{Ilfu-I^h@*X9Ik$r$EHE;u9{#8TbHprJ5
zw)sMRxnW5nuqzCiQD{{fnn%D{Wnfcv?={0?N71S_43S)o;p<F*)fy@Xp|8&HFx4Q{
z8?1ZC9c(b%eiVAI8wwd9jfT4vIBha4_61C{A>&slY%%0FL9o?O_z2M247({&(r(C4
zM`wp&-wmL38oKFN*JW5mQHC1^!&g{@Zo@mTV!3(@x4r~Ruc2)#{%8Y+%k=o)H0-cO
zLB*iK=_fRY4DUUM*02FpLwJA;wi%EgHM~S;`7y)ljS#$L$fktyZNs~Cpc*%9cY(ck
z4DMoJ-!+W>3zP}Na*Cu)8g>N$<(?te5v?f$|2k}%Hmogy^)rSs+Jt5eySm6dx^I}G
z-THyyrF!tp8OqiId)^R6w?%A?j#P|eXRM~{e)h)FXmmOl%in-PN8=VM!EiDjx(>6C
z7@tl7inFoz59oC<{!KN;uEs+Y4moN}4F-yv@r{o`jv0k|Ov&B&#VeG5_b~2W0eMfO
zU=NJ(GA4fy7;hv0MNG!Wxc@F#eT^aK(dlOl-HX<7W9Jme3FG&RAm?v%c@HWAj3Z=P
zpz*6Aw1SKsRKao5m=lH0Q^vQF0Ud1A`$Bz)G5#`0s4@S4RDTv`{5KB<ha0bb2NGf2
zum|#y#(s)NL>mL?$alurMo&eIaV`#4oHhRa0a~%fKp|Mp86T$vTAcCYwcw05E_oNN
z1mgj!`c5=v(#_N)<L~rk!(?L@?dK`RmQr+{H`-A?%X+~Wu^lU$YRskY?xY!)?!aKW
z(M5>aXBbEK)1zj5h!O}{##~z2i^c*mtjIR*kA=b<qpS>amyCY@LT|27nu}@Y8H3Fr
z`Nlk7a26P4luf^EoTp<|p>fv)IE#$W=b`h8)wqWuOvOfJFkniI7e0c*Qlo{c53U;j
zw*#wJX1x0-G?g1SYz3(>Zlw*q(zu!nfhyxoid<YXeq{klwejv%v}%lhya&Ct#%=c?
zP-na;LTA14$0tD=i~$s+xNba}0)a-O)s0F5n~dL30cW!@br__@c!_>Htwt3U_O==4
zUdLLr8z0XF=`enmfVJo}Ci#PO88urmnI7Y2I*9cezx05LKI4u)=<PTDIe^xHv1A1}
zZyKMYjO?JXbT>GMjLasGVWZkQjx`xEen)?UQR6~#jmL~#YLHvTE#z(7HkRFkrQ^mw
zLZIo6@k|2*?i#;a3>6c`LsYCdX$+<v;-0a^7G%m;@-7rk8$a9yGGiQC3zS*oORi|$
zH{RBR<$=+%1SoUHL|ZFh=8b|#OwHDGUkrooOdkzGy}fA<ReU;_HgAWZqiLLy%}%E8
z{{ZI^)2sE+>ufr<2{10E-Q+U4nwmo~cGSc_4mmf|F7j}XnRb$TcT-RU#63(IblUJV
ztt!NHy-b6DQvSi)6nq{=`IrvS8{XHnx)?lurVY;k?YL?E3TQfE66^<>zsY$CIs;5?
zP9TA%jT;~rWO~R8_MS97L**T(On=eN6l@Adam&IGQ^Im!hMHWcR4l@DgF-BkrlBy9
zDARBFAzBxnF`cEOd5p<KWxi)keKHsvXNtDqClGJyeGGyLrbV=grJFAQ2~8QMRg_E3
zH2p<^z%0|sN@%)hnxR^)Y|}sFB;}Z%pcn2X(|USS=9-ErNu6hUhN?32O?Hn#QGqGp
zL!ekMn+_L3Q=#cP?Tkex+mE2>ifI}7Q^lqQzreH-)2{PiDK%w229~R)cq$MoGfj!W
zQf^wZ83Gli>djDCX(~5@rOFg^AD!1s`<{Yawdre02h^BShhcrKY4i$=sWY*u!lqtl
zdgV#LG?-qXyNK6K&f7p5O%JH-r^)n=3Ug{U_5B0T7L&<8aoIy$>jH|HbebO92=lv4
zmE=_3FuhLxMYrimN^$g<&eBI;dQGWx%d*epSOLs_QxDaD4w!r*pzo$>mV#G<rUy4M
z!6DOb`il&kzM+u&h-tzT7LJ<2k3(S0w5|`f+%iR#qjlT#u9bpr<EARQym7~rNhj62
zCV43IPMG{?Yne1j9|PJwlO+zCrc6&V(V8}~sjzRx<ZB0GW=%g)$<~~SLkHz~Q>;C(
zZOz}%G1AVwycJ7nZw?QDA_w#EWpp~4%?qH<$^6hddSe|i|NIp|oy~b`!0KXlr~6>8
z<^%NNJ8D)W0nN?4`6d(|GmoWV%-tMA*)0$AUlg$MG&AUqnU{H-s=B<*>nJSmV-BY}
z5MT4>Yv}iHUSSW;<K~UzN}n(v`5adGn}7eAJ}4GsHta#~N%K!sx_HX``6O6_%?l`v
z5Mtg&l~AGPLx;f<W_Ff?CEUDm44@I_wFDDsR#Nae${a*-@zdrXu7gCIe{hEQ8T0QO
zF{K!@@H7O@ntyBqSgg5Y7sk$+pSGchNu2rF^?->tXHY3%f>}+c%0%-+Qkb7)ev$!+
zWb=V^v{KAdj%b}XhvmbV3+C9TG3`|I_A0c}%x`@IxpZ^>Gawme+=;_OWxn+>NS4`V
zC&)$f>f0dM=63pZ<(O;dA#S~79-oH!x#r+f^yZm;$$8E<A7o&#z`QdP<g)pTUjbTZ
zesmjVQDi<`0GKQ0?3bXo*u3gtSYKj(s{pN1^UwVlyK1(lJZYKP<8^?Qo6k_0Uxm4k
zaz~YBN4hXqWq#ila@VY8H5)5bZQg0Y3~S6s7Qu>I^Y`=x!aDPBMkuT|CsQ`Q!F+<E
z8rRKZ@1e8N%%Hzdllh80V4BS?^!&7#J8wd+)qMLBP}<DwB4}ziKM@0gE_1XkSZ<gP
zo`t?{^DB**S&!LTavbu#=AvrY1_SAqR=+v#6~GLbwOYvEG)w4C#-Mr42aq2!C!c}9
zu=$?_U>Pwlp}*Fsc_Af~#>}l$gm=sQ(n5^gHcKf;IBx!nYGUq~S5WobUGv~sfK8YW
zEr7mBbCZ>dXz!Vi(*8JOt};S?)_jB<q5I|y6uf$1Zgm6eocYHQsGm2Vr*MX?Wk)}V
zoh2z0D(o$rHbBn7qNihuqvhL&uv|`-z6t0(Vi~sun6rgNKMxm6J*A#pEuT{K=&0q(
z?exZSvvhw4o@18HF;L-dd9V{`9+vSfAfA>_2*%5@ltPu>mI}Hh<6|jY4|{zrkI+Hc
z&+`3aXdSmKpgi^o%i=l+_*)*n46p#pPm~e~w0x;YXOQJO1*A_}woxYcl%*+xJhouV
zU-Ui*v8-?c3AG3*{TODs^e<ZBmenc1j<EcC4V{segI{AUqAVYO4!x%>vo8ZJ+A<@6
z^=B-f9|uc}<w`$hc-CTH3iYuTpQ|9}EahKfnd2<n4QRz%zFh|B1j}3}ofs1>Khjw|
z$ubiUo@7g1EU;57?UR5xZ~1^u6c;Q`OEH#e>5YalX_i?^xusjSPeXl%C5w)VnU-lG
zT3MF-jgY%&F;Y=Xw&i>g6y{iZyfJpk@`xuo^DWk85HGN7+>Vy@vc-`O7=@ONRC`fm
z>1~6iE0(JRSj%F|K8ggCSWHy_EwwD7fa_Ju9K9CGEXSz?quf$Xug?n0F$!l?T28D)
ztIE<ryTCQe?CVfbZSmNMNz_;->C{kb@uN3$o#n0d;H<Y=zNVvFgXKUE$aTvK17_H0
ziKTE#lV$b=2sT?Tya<UFOB$t+S}pI|1G~-ga2CeeE$u4k?XXN!w7Js~L(!uy%ZCp`
z;D)8C92Rz4Ufc@k9!n@WSG^YhV<3H&?Jbb&w^&~#KY74%D;@K_X{n%B^Ppw91`<OS
z?-}q6Tg(#teMT(Nogkx@pj2RwS%!au`L`_QV<5LJKgxkJZi#shD0eJxtO2=eSx<T0
z2}?*8<R&d!7J=Ne+&F@<DT|s?ztfg=R(iY4SdPzPPO}zc9|rGRY$z%Cz|uX2u{q1*
zbS#^<+<FKSwl?GR_qDTGOS_i6&6R8jIM`UJ9@5c<bqr=Z+2q<mlZ%bmgicqRJ#_!)
zs7-%8#@uYwPFRv-HjQ1tbhp`lz>21ajnl_a?`bny3PCTM@2L#U+a_owBz$a^S<vZg
z(^-fG_Oo%O3XtPAd#QBzgv~*U68PI(8v+TiVNgsq(B=u+D1vNy_d@+in^m8n^OQ|(
z5EKU6{QfwgLu_Vsuqo7L<^NYq+hlwOiEx{a51=W+W_cBCinN&^UpC67`&+b5+YHjr
zE81qb2!dy9E>KW3#%3EOBhT76QBEY*=Dl2uowKp0s=GLwNh&Ifw^@~prA)ASmW~98
zHV1kjmt^zBGr&x?dG%j<|E1V`mWSqfoAt90{6CJaJ1*<0i)&?;m8CYd*Gx-I%?8ij
zd(X-&N1E-@)Jm<)9u#CLOHq)GfXD`!f~ag+f`V+3r6NNa0?K^9C;mB~bMN_{bMAe9
z<KA=5{gG<-&ssQ~W*1rxV7i^N9BMM`PP@SUOuJ?^8qeE3RRb=|jyZ<DY`eKK%*6$}
zL&fku$L?)k^j)+&avRDn*)3;5<g(ocKFsIZEvNe0JiA{O0FZCDs~#e@0=w7fG*hA7
zlp2F6vUBVQqS$Vq34^&}XLlZm5<4bcv!!+)J_$8tcAjw%DYrZLA-GDr&;P5Dwp*GC
zk!yBB+Fo3@`(YkLs_kB)ykCvohSwo^!|vNJp{&+Usl_1b?B>ziyWVD(8v$U0-S;Hg
zXcyT5uE{QR7|t}?-S{8KO}pAOXlt=MNjdUcb}PSunpV35g^+Bs^Pt<f-R@b+5_i}Q
z7hr-r?L1nc`?lTLd9ZZHuG$&!yLMd4$aLB5&VV!b>@HAjvfIw~@B|$0vD>sCh+aEc
z4!AzM4ywMpZ?~Spkq_*m1!(NItNa-F0lPC4;Tg1hiw@Qg*{LZ#{LpTRBa{x?EsTL{
zBX%p7z?o6IU<!6WvRmT~++#b70^FG0fi@T#w|nXZn4hpS*j@x;(r${D22*x#KM!u&
z?q7Nc*)x{)L(M@(;m_a>G0N!jaA5p)6U33RbUO?lX4KJx!in*w4qiAj-k_JF3u6(T
zD|Tgg8X)4vm{$Pq2xCeF^G6xl%>cMFs%SCn!PxFj6`P)ntJ|Q|i?RIxh&N+s0*GUb
zPhJ2y&Uk$SvlqY!q3A>)!%GB9L5!_^uoTSL-GjLZVKnYQV<@9#1w_Ia{eNM+rx`(%
z;0$N%r|nb(<Ch!gi)4IE0n@XL%d-HFW_-k^j9m;v?*Y59jHhlxG>%cZ8zi1_pW>zo
zj2}0_(?muFWk`}3rBv;d%-A9UImdW|2c;>D1+?5qWo)69K^h~EUT*1(A-cLV7z@tA
zi%iA}3g(<=WIKV&!q<*~%VwO-r;6zdjP^;)$tA{1-Dthcc$I3xa~blFK=K&xc!T6K
z{-CIF0V9zPh!is1mqAStBb4Gy#f)o|r@6xDq5ysgBlbo7TBVH82f&pvUZV|AIiofY
zTm|E+JXpBOa8H1}N`_q=`fOE<<rGo7#yCK=gV!04_Mx+yQ6mMZW#rO=xsI`Q14QZ>
z?@&;sf#FQykVeMZ3fOI8d_>`@X2u&FkeiGWI%n0wc;Q#f^DRdC2bjE8#sHn7Xk$1v
zfV4B-rM*rE<4qwXJ8g`$j!<)(@#%*kcNlSP80cL_us`f}F(PSMcaQNbC1$%BpRIvU
zJ&aPymGv?%Q$V1Pv3(@~_Zf)8<5poXso1ce@zM+^8(_R250OE}<$oYD#IXAg&OBtS
zr4oo?#xmOHjxcOqFT<Nr#@Z#A*)c|C7J%an<_VAqhC?GPO)~z81vkZb{%uU+G($ou
znS)Fw6{;R$K1)Re4$O`Hu<OY5ryu<=)AJVWIx+uO1J0TG`3lU13-ehDn7T3_-GW^=
z=3LssA7R!n8-mPH=G(8r3wP!gI{o3nyic!KPiB5P5MIm?U(2$YFWctQ^4EuHrkuzL
z=HWt&_axJ95|(_KKU1jEkJ(rRpH49|U7_2bX`_nG0Os#kpe2xbdmN4iF)MFEbuhE^
zf6x-bv=)I2Wj<8`En&>}V=;)+%+0h%3upfN8@LGOW7=9qGC#EOLC-LMp97^)On(<l
z;#p=Dtr}vPmp8$gIOe+)2#jae(4or&rkNr{iA--N;F6fT7s669bN@SlpJV<_k=Ycc
zV>u*KncvXHEse>chgUi?x&zK+FiTQ_%Veg}A*l1r$=x=H<}$me+9{9OPS2uz=8yDJ
zEMVp>g!w||`F~-si0OS2_$$l-iX4_Ohe{z*%G^X-h%)ADv=uLBdT)csRptg-99A;_
z`Uibg%xp@WU1LtMq3k;IN1FQ@rpyg}H<*>rQ)yc*Gx{XhI;Q5oumZE5uD}N7&PE^_
znNjJ`*2H{eKSY|Dxm7TKlUd2ZC|a0dt6=vQGb;)sY-RdTGO&$#d>%yFnTAHpOb64G
z!jPTJC##|JHuDeK5ZqyYM=8F$%=w77+GceznO1b(W7d5LrQJ-?Um!iqi*o?%Wlqw4
z-^Z*ehWYzU@kTU0U~Y&4*Uu~&1sPzTs)N!&=4JuR4>9%E;L}599=Sct{GApEBh2?`
zT{FsD`!QS_W4=dKA>+)xKVWFy1oLnw%unJ6!g!~cxxW4H;<EIj{ec5ZO=r{{Stl1l
z>0y?N((lf!cc~o2g~eYCgRU$uN^rWd?ol}L2x}G6HM87VEh=yxtod1x^kl7}=$sd8
zeJ>ilSyM*nJjVLsHgLyTj<m?~VNERnIl)TXhq0Vw$!sqJ=*!xg4jDhzCfeGbV)>?{
z(VrDd3+({bqtBo%ko8781{%atvOt1aO1ketSgG`^4`nfagh&``^(cHg&Du#X@o-jT
zH@FCvCsn&gva-Wq@C@tFHIOKlNePj&tnLqNFc{4$q%ZTuu=dcgfLPZ2S3u%e?9=$Q
z<5>$S+nT`oU@JUKWNm*AToQ{Xg!vTK&%uyPWm!+c-!xVPZA8*p<@9m53|8~IfM>Gi
zQ!F-%)xQl~HtWj|KrXP(JqO7g*2F7x;^!i3$t&>YGV5+LfVr&Il-JE;jnap=^I5a9
zF~S1Y6B!UGVr}!mn2K4I^q)(vu!??zNC|6<9zLZkRR<)?Sl1|3R?b>X56uczI#n!R
zW&J^A(3LF4V|ZW1T1>~`uCe;Ct+CCz&Qb;dSk0<?4!Ubt%V@Q8gO$*O##)vaKH5I3
zj+MO_h<aAPGejC#*Qj2#k(EzZLK7>nAAQZNf9TWKH(8pyu++l3G6FAdv2=9FwX#wv
zL(#_a+6}IqHQ*2LJ6K^UfZIA*;yQSGn<f7p6Lp7mEDUz<vStY()5Y4&0J+Cnz(!*)
ztF|4M`dCXYK=*yt3p0R!z}ik>$bJ@c1w;l|-n3^KV*T+3a1U9VSE6y4mAL@i2&<gF
z!7<AEEe3`jvlddyYs|(v@D%7cYk<^Du;x--;UsG>-9Xc<DcYRbvo9Tl-Gl6|)!+`X
z=bZuGfxT`Qyl`YMqqWCjwu*8KPVCF`pv;*aPDMj5Z2dLNg)6&y5S$x(q#oQ6cKPp^
z(W7ifx*pxxwpNO3d$6mhY}J#!<8`!pu}jZkO1#-0t%ZqWY~~*5KF*#WiasB9CuIXp
zuwVNGjVIZDA@IqUy?Y8;{McV?1K<=}CV{{H>~BY4H-KHZ6I>vB2^|FqVt+~-zF@X=
z0lWyo`e_4zq3m7sA-XX3-FA3!n*A}w10&f*biV5hTa*c46kE{@?kv034)|!cH49$E
zuxDz~7|UL!0wA7UL)n@HwjZ7SN@SaJVK<3Ald@vT>=`T2c#b{)J9wDFPFRV)G`267
zGT!Oz{zRD1V2@|wH^^jXJODY*-WCr_S?o`#)-ju1pAXkAumk9!nZtgMYIiTPXEuSm
z#NJU4KrZ{kGWe9oRs@2}XS2706tI&n!EPbDpcWR2*qi9`C}#il47?~|KVZ{qp_IKp
z5He-#)aAgJvzNXKr4{U-{9xiLJEsT0N_H@Lc#R!Ezt(lOCmU+2*|UlOs9_hjqwfY=
z*o?kfc61_eb?i@ef;6!GT|pYzTe4xHiQQd=xoBo@ti+IRvbzgt{n*NWhR#2<v8SD&
zt)0DZ9;T*)ePTC6JJ}7M7{zV&DSEEoVMox;tBc)Dp}TwRg*#xdo4qF;B0cOoR1DM0
zHa5bUKDL00VeYftC~DQumOq2W0ru;+;r1YVa1j7QY~fMBZ4cRTe}f%n|NRWe2>S;&
zs2OEXQl{_`+hr5D$LzDm;nNuV13CjT!8WXhnn^a>AO23Uxh)vsH2coaFk#PG@gy1#
zayHOn=MZO&2$GJRFf)`L<}_>q+=;XHcL1C@cWBS=V&lB=6Lh<B)=>4F8)x=y7(B{}
zr6Zi~9Mu>Q9-PZ`Ho}wh;4~V&I6btb_2xuTA@DKI6kY2+ob#K|cY?EY9{?vgGRnXC
za-OH}cKLC_--pfs&K!zp1#+};kPPCKrGg9Q*!FgT4dL9+hx?(NujXRD!Z_FHd#2%>
z4fOVp;C#Iv_()C}g+b477_R~t#o2ZWxU-ye8htd!l}-c2a$4OX63023i^h1)Dhh}t
zaGs+#Y$E640&q#3f5On0%rVl2?;Pi<jTW^joYF~jrgBW5U}$L^HWz9#IH(TB?ZEk*
z9zy3io=?DwEDn!06xp2XDqIN{IJ2lKB!{zxF49Y!TjPLV=A5LING_-OJhbF-UZHnX
zK4-~Fa0Q&z_7ExLWEO)IbJms6{da})C9T>^ID^>G%qrzL|Ao#n&c;pn)yg?*1Q4m<
zyypy3$>}|TzADZfTIgQmY@>k7b<X-cG*)xsf5yzza{iQKgms*<#c-{jvxB~v(!jaU
z0(c|mjsqH-IQ_I4Z06KBQO2!>Q%5hiTbx0fp;nG_8ys%qq<jkV?VPq<(A~kQrYotF
zb72sDcR2QR``_iPqD6EUCujga(>>0?Y3T0eRJXuj59h!yAibRb4FT83S-l9;b)Pf4
z0Nevk=sf7`=d|9T_{kvWHWl^_aXc?V<{{@Rdw4O-ar^|jM>u5@P&3L|N0nEPIH@ng
z#2Dw_`55Rp$M^&!CpZPaKys4v@fXlN#o5t>zG;qhEq)Pu?si&D9^!h^p2dO7p{SrE
z_i8K1VXiy<t~Mub9zBYkxfu@tbm4|EAnL}|zlF{t+)oz6#8K|j?;+yOtq+EX2X_W-
z8oaqVbUN)A*Pb$c$GIUp0Px{{@C^Jt!S#L?{+{H%OCrA9OV#l36jzu9&Yycw2|xh%
zmlBLR(8itnJX(Xejr4zOg1N$8a3S2%0vHVAe(@$6Pjj93fD7j)%!O+aT-^?M5y{<8
z72apK5hpO1DDKbe(07(=j0K72hSO6khI?cy;IZ7`1rUkn-l4}v0{8M=;1aoxbTlG~
zYpbFCc`~=|2Xvm}M$k4tg*!~8&S~7rGLUrcr&I@-!F@n^noRCLU&8P6+!ND~yue*U
zRq{F9$v<K6BG(cCz$I=mk;~j8wCl~~J|++IxUW!^eF67zGvI|>{y}g>T$3#o=8L(}
zk<fO9oBTB<s)QRv%bZf~mI;WKbHnMaR>8GU)$3L6)BC|ya!Vx8UB#_^8jaVuB3kZW
z=N9SUMK$*}CF5(jRtjO?;9gn+WwqRmWAMJ7yN}K!HE?xnV7`(2wVC24O<cF#(ALbI
zpc<2#+yXZ^)56{G1NvIIfuRs><NiPus_opNN3hhvZG98EJGncHAaa-c^A~Wmi`yQE
z#(UhJBEY-3gS67^;jX7xMKAZ_NsvD7E3PpAfLmA!KtK2G)s(**;O=UH?m_O-ozOPK
z{rMnd9&%4pnrN8&Tn3bma?|OR^N2gY9BLkO=R|`W<9dZ-^2WI%UT}MYE4z+iPjYn>
z)tKT+DRDQ={hOxSp7$+XmIrx(5=@r^Zwb|UIPyN3qHWP(-UiCwIq_oXjp@wupb|nC
zUQz;NTzMW8ygI^rhYgXVywz0w?ani<frtn1BJB-5dC|W@<QQ-8EV$#m4J>dzyjCid
zIl*(J-Ns4Yd+RV3U!La+7>gh8WFHLq^FDhGj@klvE4u&;<W;@|L=bNe1zdx9-_ci*
zLU<q0Vk?xF;tj-U-a=Z4h4WP707URw=uI2RbEmk?8D1CFK}PY+Ik0q=x184E(Y&QM
z0EpqG2S75GC!UACIG&l}fC;=8GXO}m@wQCCL=ul{glIA^m==KNcz;s$cnWVb6}_kO
zls0Hf=k5I#Q<A}RYX`~Xy|)E`^SnD=kj&!kr>ArdFO}jS7kTee;mIXl)yo*~WnNDw
z;JLhUN_^+>a({u&eBPYZ7*YYxwud&lg}l;Ov=;N!b0Bktw^IWbOL(g&V_wShUki~k
z-n(4ruHczg0(g~YFrlxK_W|8p*LW||YyUb=tHE4U^JY_sw1!ti57ZmHogabJ@|1m0
zUB^2@d*}vUyemi}FWFWD-A%l^ljv;bjoyNqo4iG|d1&FqD$sX}7eKqRHr|V~pu3&-
z46Twnc#|mrbn>DpqI{d@*94#L@EGsI!+X3h8{vI7FGmT|!}Dtau9x==E#CWhulx_n
z?(<4Mh2#TX`vC3#`gwg@ATz*={TyV7#}Y%^L!Mh9TpZ>-rf}5=ZxJQnMtRFFL(OAe
z%{aI*-Va8Qao)u~G*0sR5&@s$?V}5En)islPi4<{q?(C?d__F89OCEpgLB|-p`65F
zeoztp!yG4muRB<0{)1<LaN(a%hTpFInj&a(<4?O|5{~ef*T8RgzK;@;9{jCTGU>^`
zWDliY{O9SJ?ag0C37TX4tFJ-J3I0NRa3}eHY{fu*`3HUj=f`)YHR36L5JmO<`SHoL
z{tV#PS-=MJE3)8s5dXFh@FDzIcX$!Xw|fg*7=H~dOiuHQ=(!xuZz{s%NAfpPWcUn!
z?)UH_im#;1Xf*%GD;Qx6U;QHBvHU!DxE;s0N<rfJQSU=CfzRaup2$Baf=*j9fBH|T
zImchQ3?zkr<t@mh^8ZJ-Y8pTC1vs3}Px%3j8T?r(xGv7~4?GWi7GFf)w#?@L(g3>`
z`0w3<WDb806$V}8f9VTlx%}e-XvyQBsR2Bn-^v76z@PdT@It=tC6FQ;Kk+FzT+9!m
zT=y0JPf?I5;lK9*@TL40>C|Kye<^*=ublso&P7-7`BX`9mA@eZb5Y6X1c0mJ@1u;t
zHU5+Totol5)WMl*e%5*bYWSIFL2mH>D2A4L{?twkqJeLteSIU}wtojioA}$QqPCeI
z5f1Y=`3kCmXyN1A{I~)5bLm~x${(OGSsVX-4oExy7s^m}@ShgJZYTc~m37?azeXvQ
zJN(ZsV@P-TFWJFT7r%T5rsN*~^hJnt^Ghhn+{5>xlfAwC?`?EHJm8P5h8O+(#1L=;
z{O6~EALRQ{RoD<ehNAip`B`h={xJXRHBdUjAK43~qx>;iaX#Yjq}SMEew{romNEXn
zbS`?F{~6VoOz_pT44ve+8zDKxzy24vY5w~(3HAc{D!Ts;3J&jq-9rNJ5pWKIXTCwF
zli;}!*mV{((V=G-K{6e9a21?&hi*5)JQ>IlK{zefj|yHRgYE+RDi9CB^gA%&Dfok~
zPA`Fe0*%K6Rg-Y$xWIv;#y)~y9|CtmVAw(xmnQ{#Dq+`GprSH&Kf!v6E}jz9(rU+F
zuz|wc0RnX(`T_+$uYv>%W}Sk+A%a3VNT^_#7I0yL0NRJ07I3J<C0wwu8jTSG_fXi4
z6bx^KGiL<53ZXMfaIO`7X9Z>7(23U=!Lf}PZ>-=sT2RFa?p=p(@q#idEF}o`%>qdj
zETSl1lHeO!^(PCqP&)0LU{x0yQv@}1HYimfpvx;m;6sbcOu=Hx>7N&5eFJB*1YeF}
z*x7;@su8&$cx5&ka|EeWFlM_b_=oDuFA0(<*mqe_PcM>OLCYjW^98T%h2I4NwhoPj
zg0K+)iv<6;W1z(X_g(<52(G*ZQX&Zd9Rn>D?0X-8GC|!5=qwk!l7hYp!Nh-i2SLLl
zjI2tKLQlkNf*}eyT(=3rD*&t(SOqXxBPjhHCT<8q(;!nTn1KxEtUAHVEl^r7sM!jU
z20>U5M4ALQDnXhB@7#gpO@WfGz!t$9SHRs8#QqD?D%j2eu1#=P2g!E9X4+AA2)-IY
zW2ayfy&`W5Z2Kt~+a)N;$C&O3QfNuvEm%$4u^xdl<<@%z1r(m^6UZo?eP8hWE&v}0
zYAG?)FNmQ4)qvo^a_Aluyh_X0hl1-1Au=rZtP=i?2xKx?7!`D;K<6WYmU7&W1yM?n
zF~Ns6H+VWOxcV}*O$b7gAu}ns(}2z?!QQPP_QG_kk~%27@gpP;39}YMse>?^YNi~8
z@f0#VEDQ_;aT3N>!;-U5P9-@m!X}z0S7FtMQ0*q<r9$MWuuXzSci~%CV8}!G%XvC+
z=PBeS0^ue60~h2hZ{Y;p>Boc}l-fTo9Qto#A)HMw;}gR5lmR;_ETdG;DdAVg!TAd%
zb1>cjAzK6Ufx>Re7z7D>`5?hU&H}g{B7DycfKXv}5-fxX^XPGNTG+;>{a?6n_83GX
zg%;W+oe`!|%~h1pcoo32!kwF7B3gKoG8HkxuHQjoh0-B76DO>i0w7+vVhc!u@cUPR
zOBBjIAd)P6o%THEgm2G)r4(Tpz1vcSBd5Tn3Aa<JNV<?;JOlS%hA{9Mn9mf>m0{TD
zh5fP6oh2Mx51DM?ZQ6|H2z@F4a8X#4085vIDV-pfh5KkRoGZ+<f#eBGC}f{6jH!o-
z0%5NwNTINICvZi=0D2e{3%}+;b*V6#R^Mg9XF36}l?&I<#=b(BOt=44;U_E@tQ5Y#
z8_rY-Z_<kMns8kV)La*C`WN_W;WM-ds1ZJKACk2~G1auy2`{tIS1)u;hVBMoKD|{M
zh5!2#I-7*!0g!AKKKChR^rrA7+Qha9^A7-U%O=dH2YRbeod%h9q2wk=hp_A>fStnM
zOVM{*xRj33-Vs*Ovf-|9-F-B62{Qs<>7MY9uOZnj{JIvn9-(0dM0$mb4?yI;u;>Gb
zJP`iEgr$C=!4HEN5H6u@+@LVz5Xg|w7Pc9Phr&5@q<C0(^bSNvgqt=4KPsH#48$Yh
zGz;d(h3!<fGa=kcLEuT@A&Rn32_I4HZCY4DAC<5defup89u#?!hlfOu&Vo3IIw{8C
zC~`On_+ilp^ndc4ML|O#E}~i+Emd7b5sToBo2b+QqDMrs_u$M?ksBp+-9-u8q0~bZ
zfzs4jo}yPMpzb9SR6w`4Xto;UxG1U+B0i$;K7ol7B9}DaPKuV4qtREijQ-PspXl$|
z;7*AG$)3L`G!D1`(Hq@1C=C=n-Ug*XB4#k=B19ylV#iR?3W{@uiNsQHr$z2b;KD^o
z^)L}3a-br-NYS6kXgnkOik^W{qNz(5(^=8%0T_%H)dxUloXCmd;_)Im?eY^u+<!36
zL{Tkmd6Go0oue;KCyU;oUHduFhxFJ<5#6U}eyV6V8eE!a*9~y#qNYk9GDS&LJ8@p5
zC<Dn7InXm9Tl5K)on8>VN(T*dMCBE*dr|bE1bvr8Cn(5xS+rs?T+0>Z2;pd+=ylri
z6o@L3F|f@l6m6wq`yx@xUXWtZ%V%Keis(anqLzr_bAc}vMfw9@ChGeZq+GQ4CrDO^
z@?Xc8u8KrgV7^L(7Y}X~(J&PlTo(mVZlYTB`zU;>5p_|%@`mWF9I9(YOAOFbCo(%h
zwXI&%83eXL6nP82HH!8qfw(C$j={wi(aa?vw?w%Vqih%bi-_E;4$-=IF#1kW?tYM7
zQS5OT>=PBx?&`kiT{;W(K;%t<^nTF>E69LoIjxHZMd|UdFeKVe#di-yEA<%QuuYUp
zg+3#q+xx+eik^QBGLJ+*)6gD^VrXMOCR(r?_;Jx|^xmBiRnjAEQY4_9<do=1`gYc|
zNV^z~_Tubc0XQiBdM6|gi93ohG6!)RRi8SFGhV@X4~z4R7?P8?Nr<sHi)~SRV9-VU
zI#rXpid*O+cN3RTlI@82-(?u~QSlP0T6Y((^MM)<@jo9yji<PZ9&lb_J4)Jmi&LY}
zcuf4OKe*%K8SBvJBR=vo;3vdCzk$A!;@{U{@_ofGCqRpz_*nxQPl-RY(JR_t%%-0?
zK%7C3!a%Ww@_#|%NqUF{i@%`K#Sn38F&qsQ3ut2>CT=K3<7x3#S}2E$-=rf75#l!)
z07Q!Y!vH@cKJgtSqr^)_A#zsivJg`eEq-SeNQ}6g;_0#CEF0C2#fhVRFy45vtp!t)
zAiiRQ--%+uM-WXC^XU>u7SCA)gXhHEJV>U9A8&<;R53FcKBb8rDDjXk=1{mQLp(ui
zmrOB-Dhtkwi)o#oB~JJmfNZgKCmJt`zvjTvOJen5%Ku#!@1ez3t~i_O6!OG{=OB|W
zzC>kC1!6Bs>KBSfa?w{L-uwZ4Di$Z)1$RZ9NWsk#@r(5AEftqh)j^rqg)X*o@iP=b
zuMoG>m!YnT6LtbnDfXeoY?b&V?G&$x*9QKV{}bO3p|x5Z90A=m;s;dTaYG!k1zyyO
z|9%qqI`Jq~2GxtdNkC(RxIzIyqj*g#)HI2Oba^$4^G0F!rnupA_|zf}&H&(+cqR{C
zw2FVf1ubpjFWO<DU98v(u0yP&fSj#Ud?g)-+u{JaKJJJEsc!VH_+A7^m-ww8pyr;q
zfT}IJ#eWoGpgrP!T`<@yuBF<RK5?fCYVM1_J%+{y;**q~>KFf-18zXvOAGBmasMc|
zA#u%m03M1<iy$&A{<{fgM{MG6{)CI8VsSlW9*IAsV8vr`KaFrqTv3F+aq-Y>40}Rs
zrI^E{SWgeeDRC_AwWh^B<xpcUc`qD*gOU>R;*f;<7DOB*lS~+Nl-MnW&cl*VD0JW?
zNuy#XXUUW!Tyv4w<gb8rl{})#XE({bPr)6LR2V>xN)(S_-d*y%7fg6b)^)&yw?sA*
zlE);ibfD$9<kmG<@{xSJ0Du#cHZ}TAO163f=PS{@3C>TF{$EvzB(4RVza){W9Reiv
zw8jgRoU~C1aFApH51ql1*_5UVksS7i-=UHVw4Mu-c)o?vpO$RxL|?dM0aZ0eNY+xU
zBT`bl8X{*TC%y)Wl4$4P5;!aQ^#wQ@E%Dh7$rwo*MZIDrWqS0*NhEVH3GtE(M<9|Q
z`7wtoKoTYGH0&gaBb96=OIFQ+?sJk|kI|SSiQNq@RT4(wfiy`HZGF-u8#19gL-H5-
zlquOuLEQ5a?;wa|Nk*PWU$&%~>U=IpzMxorj^ukiL@r8H{opQ1D(Rt@Cvl3P|FM%V
zSv8EwD3DC6F*Svf7%B=ak}UiQx{D>N=%IZ@5>AemNOsXHwp3DZ1eVGqLyf?dOL&xo
zsgM{#AbC~tSv_X7QWEzG8mlDJlvTSX$$Ay=8p#(5kQ)+bN+H!so)yymuTC<|hPHZ1
z0fpxqBo!2TXq3FAhciu*-^!t;S+ZS$zMB#$W%^qrOK6RFOELq0vsxv|8z9mqdGc47
zZ<mBVgT@ZY`*bj}QxZTysM``IUE_BouhIVcuEhB(kS@t7s;{-(lQdGvWVhtZ47B!0
ziYSZOE7@xTzE2YTBs{$@`TBF%eIOa}LSMh+O%Z?tlFAhH4N7u5AUPzNL@;UAL&=+z
zTpyOKq4oBNq?qbgMkRYG@bXCVG@V>~EUBT8#hB!DH-6r6o8)H-IZj9v9#A?ddHym6
zIwg5+J!GaOcE{kFz4Y9l(0x$qc@L6@q*aUY`#MP5?*ZT_eR?MP4olb3RpKNar*aZ!
z=|;-hxJXxj3xlrG9h7!)ljiS*7e}N^cfrG>(%B_|yGw0<9LLZ+q_wm@@|1SbceT8v
z_lzLk(o;F;J0^XFQg+9sSJcqvBV9%*;1g1()#y7Z?LCS{UuouNFz6@!i?p1Qdey;_
zztm$FBm<-#lt&Ac@_&LCLDHTF5DAuEp;J8}(p$E-U@25Om!2YF(xT%S;c4lsR7)2w
zo%ap!XQYGlFo=@AK>upttn@bB0MXLVqM$TJdYp~MSn0}fI1?xJO^1ni=~fxI1nILy
z5J{9C%SB_7bP>g(lBK&TOnpvzzyd8P(vNub{!5kq;|Vos((y`g=~5d#do!eBXV}e@
zwo+E$yi_(Dh%9OEW~j-Q?x(8e3(}QT!Ji{dNkHR8>HQZWc}coX3huJ>f;+feY1Uy3
zG*9}2FG#+0WG_?~Naxe}*FvegJ-z>mq`~_!C&kkJU!wDhG@fEgB~qu&n1oX4#|xpY
zOj=E!(JhzmxCpL7>NEh|SEUs+&y`Y-3(!_2?WHyGHE9e*7q3f$gW+Md)W;1T)<_>M
z#U$L2rv3~I_0q&EfHz1}qAC8_DD89wut^&J6Vx<I!|uS+P3hb;h_*=Y=0Wt9^aj0f
zTct@KK(b9L&x053(uq)*=#UCG1J@~ap;zo}>FG%LbVvHkhiJSjZ4iTWNwcOw?nxP+
zKxemf@l1HwBR!l0Wwu`FDvF5rN!{tINcW|MXMukpy-|(MerXgfp$4Q5Z^HdS>Bb8X
z8IqpNgWZSH#R3d%Sh|$X&yGl~&%yktbpKYEcqEN)!W=%9O8o&Clj`3^-?;P`<qsyL
zZ%|xdQo6npxG9@7^hao$mj3nxwAstjsA&G6%uGqAL$a@F3*sP)ZAYJ@?C3^lJ1ko>
z2LLD8c1lz_%Qn6ZfQ#&R7VNsp_8x$Un=IpLOwbXT1HEL9%H;IrFL&9SRH^A9%h3Vn
zDVwI8lb6i4mYzP|vVJ~9kI7<b8+cq+MHhsR>?0~EIw32d=+jBr*&VRtE6bt0mY>Y+
zXQ(+PYow)&zf4b$y8xN+Nw^j$`?(fcf@J5Z`Yu@JN_Ai%vU*xshstKrdMZq|yBFMP
z*=(CL)P&3QzF;F{Y5ReQlvQtq`7^TlgHRJC`@k22iII&{C@ogDg`zQWvP7yzi<cRy
z(3l`Qs)hMPS=I`WB$@0v=uDR7(+z)4c3lFJBKs`{xK!Ee?_r+OWFfOa(q+kq=>E%)
zc~Gz+Q?}(7cyV6V{}Xg)$?X1tnrvAkT>=+mp$@?3$QI?o#6=l96y%c3ehtWF*|~O@
z$dwHifaJ*zDgn=ztzQHa1+w_>ptDd`a|3-vvc35*R4n_L9$r^uYj~7@D3R&YfGCx{
zYlbsrvYWJcDVJsPF$oniw`(wQRd$4yP?fTTqwuLpHh(3wU6cKF6+T^;{r(a}s%59C
zKB7kEFM!<}GB?T!)XL`3r<v+xEV@eSWxd^yY>*wJML@G`0p7Q^SvO??R1nf43!=i8
zTe2BZ@U2z0lF}G$vX@8UTDz=j1kQBGp12ARJ7q`xfxj(#m1+X+$et&E@5=VllDtc{
z%>$0!lVwv?X18p2JtTW%$6G*pWwVaJe4nhg4a)Az@{(b}_CO|M0nsmei2;WPWHs~}
z9F%PoK--WkX*JA0ls)(Y+^}qn)*vIYC+XEbDw~@QyN_gZY18mn=64)@V>0{S&^Ru;
zN*RL*Su`EAn3UyG1;~_4H43}avcFHjp1oXsALO7-?nLXsL-H-OGk1`$S`NSQDMX4q
z9+pcfHsd58D}@)%@(Oy9xX1;x>Ts3Mr!rqRxz8U^dPFXwAI3x8PWetx`P3iq!b=`V
zN0`0kPj;a3nEWX!T|6##ibtc5ytx-sazbu1%m?tKe6|Yi`^w*<c)Xwd7+s~O<nFaF
z;V<u}&`^L}LT}+f`Gpkp1<4ow06?fbmQG)U$$Mz8bXtCvaueb5W%Dtl2>DKmRYc0~
zg+u2V`D-rlK1$ws4CJglE)vS3<)>^jKx5>+ci>d4yoFM^aq{Ct;^jMh(U&0ieFmdX
zl>bDzm?ZgU66j8r&z}!3&dE<xT}O)i)Fil6xs<NCG&$b}XVT>hqA;=ydBsy`%#@E(
zs{FkCRVw$%k{@mZE?aJVi88Af<T13Q&ylP7FmX}-2^H#HlCM1pa#{YuE{NpHb#z_j
z$=go@m@luO1YUvMkDla(@`y=zSS0tS$W*c1XAs;KdG1V@FOeVo8#+tnlL7$B<YBa(
zDwh}1m*gtsUbVFTyei-PDjcqqubhcdT$8t4fr;z#+jJtOT7G~&kyayraWkB`A$MK~
zgSGOXjgYL9KR5tO_44Cqpshjv8AWOu<@;!Yo8;e6%B)#FMGLW;@}CITA|IFyFK)?;
z=}Kso_aY8ro7Exjq>OH-d`|*IZ_8hN6H4#MXSo7@SANhRO1tD*dg$JhpQfisxBN-E
zEPLc(R14HAe}{o#_sIuVK;*tWQ3URRe3(uT_si$L4P^uJ)J|v_lpmuDaY)X19$FsC
zUlgLzHY^W$55N(5PBajs^1~GJcqBhL4f0r?K{X>|@-&KWjLYrULED5};SMq>|Gom2
zrsT3y@P1nUk_(jDE8d-f(H~U2PdlJPiro~~c2ES)fQX}_nU+U~6?TiD(@F7iHu{`x
ziWZ9IxG2ujfhSkR4ay_9DZ1W<=n+N1I+!@BxI_79cSYz`h<GR}Q-JqWINgGXm%^1|
z{oV>!3UD1$m}4=*<BEmhAU+D=C6E&e2JHw=Dpp;>czqSJ7>vwMVWU$nrxdo&o&f8w
z_>CSd0gCB0Ac2aPV$m6-I73Idf))K#-4&wPOIg=Y#c_(AhbclSu6J57)db0KMH(eF
zA{6cPA=pTTE1k|cqe#_(L@5sVL(5sk&dmTsD~$9`jZth9!~0mpbGApAnm9#L0F=fn
z`srz#pxBWCE>YnZ4w9sJCk?uj6`$n7(mBO~1mIH?%js@RReVM_e41kUQ{d7SE$?HX
z8HyE`K{6G$y3luCk<<x5mSS@&3}q|kQ8MI$;*Bq0K1bpD1?3+uDt@A`TV7IpM3Mi?
zibzL@<|-Ea4fpdDk#w;ZD(bx8Op)R_EgFjz1N7d!qVO>SP@?ekLtm+)yBd9EiZ2hN
zuUzqO6Z$F?!VvUbRk#(wP^BX5UktEHVWn-{HHFTF@(<S)o3F!Qwc?T=fHjJ?TOc<S
zw{n4~Rg8?ne4S!fG7$BOH4ou;gF^5b=DAVv_ayq76geLQ-mF+byY-t2?FRI<D3;Rd
z`Ih2d0dTE~HcI!jDNf9T&UQr>ZKpaEA26u?rBm_c5L~>i*m4FFd`H3DhR(Z+m2@R^
zDeR`9?Ve)K35awnqA5txqj($-(yQSAcjGA<T_AE_v6iY@9w^c&FxIa)FdxbW6#vqN
zG^lu)-Z4Xp0jha?sQBn9C>vH(e+SMsqIh}(Mlq^zp^EEAimg;0@>t<C1&7BJJBFZb
zT#-#d^9hBT_J5O#QF;nYDR#UGrPGSF65#BWNzX#*LFFn+H5^jDP8Xtsa!DE*9hFT7
z!5vn<MjKTp<<e)tIV+3)!Z=-Q%J=ED@2U(nq18>vtU~J%<qNbxIjVeO0r2k1SAT(d
z4`uc(h<GYjeSt<VW%m!T>#bZt3FTwTH)$VrTv<H@NgrjvV)UI<u4u;SeU;nh!EHa~
zI!aBRQog`~YJcUC3m^eXTk3mg4OANZpgTyp?GVNktn_#XjUh^IJ1m7N7f?nhO!?~)
zkkd*t#Tvtvr>VLtLfJzf1c_A6qSf~qWgnIMMJZ?f17&BG?`bf3(aK|L3_C_SxCDK%
z$_2D9iBnp0Arh~A!d3z{LFrEacQ#SUdmU<$l(m8IEm;{yPoHzj)Z6GwQ3eTMH&yw@
zzc84l-0>s0bftkdcNt1&ddg=iKc(#0d1c%GfXh<mQc+p9veprj7nG4?AxCMXeb`0i
zRf_ChQWkho?&`AgEgER9au3y2<tbArd7H0P%z?H7W%RS~uuwUN0zO5`@kodiD;K^6
zz!jyxJw!^CbB17|Ou5+sjpfSQeQ2yuzFG^wRb_`2fJ)_|EEud(Zn%q|>6-FU4!G;e
z+PCS8f7Qxl`ekaALn|@*8_L;<@U&LxLYH2ha<u?`^~!xS(AS{+GavXy<@a>jt4TTW
z7aE(DV-&8ssk~qYu0@%(1jD|i)W*Y$R%P}kxYnl3ngwO;N?kK>9m+b|%XTUUk@~gG
zx~-Jcrsa<EGfL9kRsJ&xZC%QdCTP2-?9GCSZe=JHMD-~5PztJ7d8itsPx&=P!tX1i
z=!bovv}eLZzw%u=qduT?`v7w>sEnj*eMq^!7(P8zdVLANuyV^K07jHmQ7~&8RUViL
zZyqUCtI_#bxu6=YW6FPN^**kwqSeEMa`+o~F{yOf2c=WW`xMfeR=&{&pX^oJ=~Z=5
z_498ajw<7SrPitte;9O9-QEG>teQnPrHjga1vppL+q8>xQ~4*s-y=4aT`K5N)h;S&
za991H0Oz4%lL=4N*R;>}QkBvkz+2Vi3z1{0&AZ_5an*_l81zy3%!Q*TR2lR-JE_`q
z5+c5;vvdsIPj!oSPN!65*C67ry0H-E15_6&rx>Ver&Vx}$~N;GbOx(9v;+!Ky*z-<
zP?c8&NSNw$JjiKP(|%|RSADw*a}l9B@(f6%YBPm@&Zrj9<1R|Id^O-_RdXpv9<5rV
z0EtmuphA#X)r;P+l%T487g`ckU#|clNmc(Y8k1EY*+}U*RjM0Cn4-EsvDH-7dLu}h
z>dC)>PgkkWfn=!O4}ghG)nqt)I<I>5f52y{mhT2GTQx?BhYPAWiuLEH^5S9XqRMv~
zjh9qSE*Rit6?ZWjb5&o^ZJ4LJvmQG0Reg!H+$d17Q!s6Xs>^Yh^&*wan=nzVS}lak
z71gs2;7U}Vehpx$>bE)o%2Y9Qi<hhZXN5?GYAIbTS5;ro9=cLh=>RQNs`-DS@0!Z#
zIL2~a_10;4U#;33i^dw&7J3HWP(8hdz8_JmTJ%0T>r|`lfv;Bu)7z;*^-UROrct$m
zvSdxFZz;;xtm^K7$W7G>a<oNt;5fA1Ql+^7(5k9tLb6RYei0(=suw;*V}~l1g0Y>d
zSSk#>tqKo7Uzf@|3zGL#yVuQ{@y4ufRX$B{k1CdeeZ8uUyFvO?-}-*IY35Sfj4A+!
zR39vd`G=~HFQRW)CAtsuBdQ<@=8mdn)8p!qO8pO%KE{;`kulYC!yw}-1D)`lP<eYn
z%cN>9{UTGUb$<Anrd0t{&uFiH{u)FMs>5Eu93E1;&@?-!Uw9Go>!^OyMmdqg>NjZC
zozziO;p(hb)<d_8+T|}GT-9B4BE?PJM}?b5)bps$_NY2ef?>O>Gi$+lsK2F!vZuO_
zLdkyW<)>ixl=_>eLHyNk?1E%~dXhGbf$Dc?4IZT4OHqwrHOfPP4^cm$CtIkx|0<?5
zOnryy15c}ak3lqC{S2iMBh-zzfrwPU^ax7NsMpiKV2o04NWv)2s=de17p?B0N~joh
zN*$buRliK{<T$l>HvsYK6BMCMP_KF!9ww^8H-aRo7ykD_tYme~cChEvXQjZWs29=d
zAyu7Al?`d?nY1%bS9{aqKSOP{2gy_?(D9}7>bZ7wkEqYM!9=!t*|Q)Q)V=h+%~2oN
z0`nKutCnG8m((x)7spV)LdODf)%R(wRiJ*G`(JukEe=3yky=K}=VJB7-B5~9>`vfI
z)HnY{U#WVZ0cy(BFMNl-a`mUQxV)<NV?(4;J<ttYmHI{@MtDtaD*?H#W@NxbwL1A<
zNY<!h#xRx}>U&fKP^&Hu1*uan=V2_idUeD*Ks2b&(sI91{R<`To7BNM7<RL|Y7hEu
zsRyZ8qgCx>0%=z}769L&zWf86=~TZr43XRF{(g`<YUj`4?_KrJ+0fFZ-bnH3d+MMs
zp{!dSa|?Yv>aB@ztyldq4Y1FqeklYp_tkTz(fL5V;TDwks|V=5A5a^6ATy}GNeR*+
z^^Qg09;!czgtlSzpQRup>XlSCGpg3lfWb%Vo$tc6$7($t)EHB1?*K5a{^|;JPN>Hy
z)G?_}Sqs%u>H;xlZCY(ROyRkMn%`*Ucu3O}0Z|9d84C6}X=a{5pR?xr6%5TqbI}=I
zxN71?AnB%IQ9%5N=IM_>JT!?F0C;NNnFkRsP15%eIj+h03O@O0R+mHMgvKlfcT&Tp
zpU_v+SqDi!%{ALXOzA1j&E+uRulbuUuK>-!X80Yb>7{f)kS6&#;Da?6C=wT<382JX
zsOHJz;KDQ;e}bCRn$|H$hHIkM03M;4-vbh<S$!QNJfry`41G}=KE0vOYSI-@7Oh#d
z2YoS`lTozIh}A?8iPMDq25s>gCY9MIXj0?gTB4@!O*oUJIrK5qBx^pipz)l>krJ~h
zn!Ve>rD}Hm04_~a+y~w1nq6n1EJNc_2}d(E**76_UbEDK3ChyMQ5-&7Q{4oe7c_UC
zr}F$u8U{rdFKbrQ$}v|{K&AhA8t?TW`I@&F&|RR}nGCK_(?{QtF4DL~z|mq&YZJ&7
z%|ro2N;C#qR+Va&(lVn=bB|(u<(il_kP1yD5Ads+m`vEM)ZC!2MpbG4SVjMk@tUT@
zh@oBAyiQTcYR&pfP+Ft;>~GB14bAtb0j$-m4h7es`R!eBjha+8M4B|q&jQ!1DJ%rJ
zsbSIMu0^xyeTdxBJW~e~t(vt@L9$Kr(>Mm$sY#p#4{vMQ4`CASXn5Wbu|3demO*#F
z=FpQM0~&;laFJ_Nlzbi5G|Yp{h~^n4`bIUSH(}|K=5;!9{#fJn8n_9~ajL7I)MU*A
znbQ1BVflkv?m-OukhcB}XmQX+?uU6tE&mb7VeKd1Lz$EI0D0(T(>5%J8gFerB~y-R
zFRp<3<J$a8`0b<Jk`GHKv~wt*eNy`g1)6-dT?+y9)2^bKJ*9o>1xWg98!4V1pzWod
zZJ@S*w!1;v`)z0p*1FPEhH9Isgd$A)%@zCxr?n~yV1#RJ`>9?bLi<$@*huYtdfuGX
z?(qdMTHBO^z8Ec!0?e`6;vP5}r!Ap*iq}rO0!s<nSgLYN)E=mUNRoDM8UV@K?JB^}
zY1>YtFGYLlWpJt5xDO$crfs8eV!AfY9(@_w&bhbYRHoKw2fNwYeBW!|;K+EvOdxW#
z`TNkAr(HoY-F$7(UJScHJ4}(OLT$oYs43El9z(KNyZRAayQ2N#7+fpS>M7q}suj{=
zwoH5AZ%kgf_T!BJRA}coL*%OV;5w+T)c!=DW~$Pzw}88*72H7Ib*;!oiOw6^>>IFj
zQ`<{x>K5(Lvl#C!?JP=ww`zYsh{3dJzq<^4yY>;q{5rKqenj7G?Qb_Bc}IJcJiMz-
zWkYwD_Nmn%_q508=vue7xevG=?bAmA=+kym;QzjMl!C_(v==?7I;3A~qTtAYwwz9J
z3~CQkc6&%0SPrERwcdx|;jng(C%6%9aSHlIwd;R_zmK(@bdQZ`eI7!~xb~&}=$p{i
z&<UwY?FlYMIHh&_7pkYVwFf}#by*aWJ*ab}aKs_qIWv9o#6frRF902N@7tsGu<lGB
zyl~QWcSEVOE_EN=chN=Cb>*tF4}_$f?y2WNJaivYy{eb4_c3&P>$Gz*!ehF%bn@o7
z?jr5qd~~xZzI;L#dl`~`x_9ZnA)M0HgrLt~rxsAiFhI9-B{~Cjl8XQa>B?mw!MaVg
z@FGO_GTnxuI^}ApIjytWFy3%oVn0M8biE<a7O7jk5%4p*`c*I=rE{5t+h=tHR9G9W
zyB7^DF}kgPLrbhqw+w(dUBMI360aMzg4hyu-t=rp(v5h4P1dd12sP()FS<c#itbn1
z0j22{wL)pSE~XA%WaxS>LR+S8*#(H4*LlPMm!;c6RdCt5#W66Lqw9MD<f3l68MAgt
zx0y=YF6#n5f|gueGaIhu>1q$5FW;uKQ^Ld*U9$sZN_6=p=q%OkrbK6%ZXd-l%5}SD
z;WxOddy1kAl{$SV`l@u9_2{eC{Yqb(tI_Sw2mFR^jN&%6x<j<9s?&)|fNRi=Q*5(Q
zH`5P&O*#`BT3U3PrRck*vu*nvgK5>dJ_$sd?kI)l+I7$80nwqGyBLU0UC*Boy`$?3
zgydb_SCkd+(mkw4-#y)nt?;5-x8V|Irbo9Y52RP8q6?x=*FlHc@9XAM>S;jtdOdUw
z>Rhiw%aHCF6SO?k_1V6J?qS`Jx6wJG`<3=Jk96&n(0Z&hP@Te<&U-mT#&w-aG*0OD
zeFNRoy3-|)wAT+T0Xe9Tq|nYGeXb1NJLu=oQ`%9_Jqhzp`l8n$;;at}0ddi98HA*(
z-byhFH+_DL4WjP)dp!{K(0@$F2tD<UYPjg7-*O2u-g^G$Ajk9{^#OleA5M!)AALsy
zM11v^lhEj=UreQZr}R?#?fvyT6VMo-_nD8zAbr#^0D|?e(>g9hzdjHoOz->>hI?Ay
zbmPC0W&LUoOn!uZ_7<3r)Q2=d%^CffWtg_J`nTz*QM7*9voIK=FJPfDR==E1q{Qii
zIl#s1bLn}Ws2`zsTarH69gWHQxwM5pr}v|(y%hadG+pWXOTS{)GxUX@K})7yvYbMO
z=k+#{$<qJ23ixdOAlbd3*M`Ey9Q`|#m%6C;h=bpk^uP6@@3Ova0?y>>W1>Ow^dHkY
zBVT`l3dIZbTQXs(Q2z%9eMR~W>+lm6>lab@v_zj+3b#x3gY<)z={-JzqqcJWJqo&2
z=-()YnydPrNOV@}=XwHPrH|o4+ckaT1k_yDdnCeqwSGIrU2F8*@1XRC-j5dHwfd`6
z4pyiC>o0Ki`am6=Y0&%9&Z|)`{{UK=^o3MK+N_VKa*&()zIzb4Wz+vauZLFsv-I8G
zHvNZhqO)CJKxvZ>J?jZr>eM^m!02!5rF8D%jy{os1$Xt|QI%7dK5PQI@97ihUD2&q
zeF3+7^buhI^y-)1$H@Bhxm9SquU|)>0(hXGO>2OD{gw^TGN`w$?*(v3??x|~hx%eG
zI!E;^N<lr+mzRJ%)*q+Z`7wPHy=2DqKhWcOLjS%WbWiHpKca6+?@cl2X}vo=OY9AA
zevKg=G#IFQ?vTM034nuvOE;dQVZsrThYgO;qtVF_Vxt-eXG3{1%)1yq^hBqtLA(v_
zyBV5?F$qTuVp{MXH9Vv}xVz!kTmU@`*-_v;4PVe+$;*&I)j!?_IYrQq8G0xfd)zQW
z%TOOf%vrd7!ti7_xRZu;O;F}*(9m!1XZS6Z7Q?3upGJfAH*CKKe1JhtUmyxJtT4cf
zAjAA8p*z?RV}nSDVXPm3P($q~NVvg61@9vaofK+}G`PJ6@6Q-Iw}Fc?1g(IUvxW+K
zGDRCk)`G+sf?t67SVL1MxOjssh}OgjhVLl^o@hAqJ@6@p_fNuZs$t!aa3;+VOKHn=
z19uc&WEkeGfx%3}zH;=PH$0?mewN`I2WZPSEX#nw3kES=9yx|dyxeA8G=yw|qn8Y~
z_Mq>w!8ZtfxrW>HWXUu5$mx@p`G%W+K(xT{#77{7hRfwJQDoRph+@P4=tXkH@HSmS
zC5AV>KuQgtKY(PJK}A<!xj~W+r4@$NR{^+c*qjL0Dh=P#+px-T^ApV4HN)l!0InOJ
z`wCpO;rmC>S!38wnMvCX!zEgr)*2Qa2B|ZgqP>5;VX6+68VorsXlpchhJb4_xa<V5
z+2H*thJDlEMb~qS!F>iqZW(^}hZn7eEDrkG3?7uyY&XpO5+WT2uL)cborYiN4A*VL
zM-;KVV?bIKw~@_oay?qR4AS#p?-_RZz|(HSE(#*`7`DF)(OyIDCs5O8SQdye-8Tf$
zOX7jy<+ot4-|+GfxB<h;N^paQa9Y9)8TRBt*+au<7yKPI{P+sUh~Z#21~_WiNV~`}
z!*x2`Gj6ao(9&SSFiAVNNyE%wn3ysIQ;E#9Vdf$zwKu9f(Rk4K7G-1)89NrjLkDBw
zJh<j)TyqB8VPgfI0dq30`5taN8yycq(#7}=r5#<3R=O_SjIYiB;E3_HIslFu|5ie^
zyYZH-3)I6H_X7}~M(3}9@G>5~4i~+R+YZ9+G2^2vaOSu%;dhL}$JiW!5uPx1{8uq%
z{E^-+zQ(WYVZzVo@HEDB%9uc}F@NLh6e0~Wo}?0)P-8bAjbX-rX=!`fxFi*-!;Lw8
zbpJ&d^;8}eX<Tyz<cu+j9)3~AU)}?E*0`=0CZdhcQ9e1wxNa9ntnq;i{>B--Qvr`R
zs*~V$f-(A8IGSi&<qmj~@uh1pk!<W8gXB5m0zO1ijIu&_m};z~yl$HDH6tAvNH-S0
zfYuCS8a?wfjcimh&N^?5ZHC<}<Kb;^INSI-Z7MGqe`tnJImW1Pn7C-%@HTLljOQxQ
zc-i>DN;Kvge|!avdB$*mXvsIKsM?{xctwK7LZg*p&qc=5^pGz${;`ri*>J`9-TRO!
zF@EzN@TJC$58y?av4%E<<;FQWjH$x-MF0?2jW5xjr_yMafK(Z$K80)7jKP1ywd=-h
zdjP05UZ?G2jd8|eXt_cEm<jim@w20_TW1^>0#|SRi;CtOjE=#8+Zv5uQ<;2|ar|p^
zwi?eoiOzQ8FrCrsFt)j&uhW>552d$_@0CH#9ix6GxVy$vv?}Z}zNx{`?ioL%Gl|{C
zR0Ztz8|Ty6uR-Hly7GsNnf(AfGzL)uZPb|M4hxTr!o_gyvCZgC3yd+NKbaplat=Xe
z!sz}0+@x{H7kyL4qZ>e`jf?4_ZExC4Q*zLBg7*H0Ok)(Ca4?l)Eiuc{G?z|F95#tF
z;f0fFQ7wqGse!6dTuf0<!(UgEhBg~+rh<<!vLhzjE0kV7YSN&5XO_FEmsTwvrif8!
z^E4&Qfo?C;RvsF?O@nP9$4qPKf;eu9q7<-?sks`BCrmlJq2;7$h|){GrbRNq{Y<mj
zFmcLstsBJOG?zveU~=9Jp8`#5<6$qzRArk9e6Z;qI@B9tx-<Y_sHtTgxG>YUzd=r$
zf__G0xM|J+3`Uq*wBRC5Q8Ad(Go~X{LlkAY^CTM2nuK!bjyAnaW#ciXmD@mKO%GlL
zF3zOc4H9pPd>76nm=fvMPBfWVHaL}J+U^5<vS|+G|IV4#&;l^Uq$z~?RMV9>^re~Z
ze1N`m)2wXtWtf&ymN(Nh#|kgboAPqNWtrZk7hkri;YV1yXlj;%TrzFjgTBkA93Hgf
znr=~rcAhEE38T+9opY!4XMyQ3ZK4ZJzx@cAA`|~GMp0~Pih;}((-h@WN=%}0h?JTV
zzJ?cNrgtqETDj>mRpM8e4rRf_Rg?E3_*-exE&;sCR7%`6)5<w8c->S<`_*cbH2_?V
zY5D&ExM6ywhe{@EP5<OWO`S<a)d%&aOd||7m^@q|(`fPyf|@4Nxnh`aHa$;kwwos2
zkLYVL@#%!rEt7)k>RU}L14P<PkDAceZrV!ujt)~|It+H2+5&*PYf^FHT9@f*Dge1>
zih2=!wr<lyO6T>M7QF(QUQ;pUB>PO`R0Vh6bdM(Zf$0(Lhx$!9<=_TPPf<bCpo#xE
zB!^683!(I(Y1|3$VbhU6(KlksqSLgarY-axqDQ8epM~UO(>8K+%;bFuZjYOC-iPFb
z&Gc3xlunwy?SL0krX<?sOq>3sHL<<9nreX#n(M>Rc*xvMuOkQZ1bvXi(JXig+76p{
z;1M&+$?R$mFPzN<j%ai-Z%G4jHLJdbB{%c8lp{D|Hd4IysM+NZw78q2sD{DAZ2IOs
zu%2dpKMZ=AuRFn#w|OIl367bW_COprH;q8IkNKM+{4giXW)XlV%~Ny|#?S2I1NbTP
z(EAYaH_!9++Jl%*)F9x&=IBk33^6Z>hDfNnj`Ff$=KeA?o;EM0&1ks!mqav1m=_ge
z@*>U6VX$z<oc1M1lsO_6TF#n3r(&{b^EV*?#F>X!Fcfc|P1(Z)^Or$zFwwl?Wr!r1
zH8aqcY@TPk2-nV;m;ZtxrI=UwLMGK*K~LKZ^Sj;vW}3x8n3D76EtQbGU|#w*EajL#
zq)$v-G`CUu{gSzezIt=n{L_!%a?LAf*7D3|ioWKXbI+r%z<l&+;0n!q`4A~G|3W1Y
z#b$qRI)-<}+(-}d5_9R>5G^(TKv~l=bJ9JKa<h9K>{gh^Xhnb3{8l=+O0$7J&{kzG
zpAFnKvkSdUubUgp092cM>|nRXob&+P4RgU3aJA;ml=-SN`%s9o-t4;_${Ng@ex@?$
zMso$#bT^sLybscBUa%9s-82s-fwY*n)4t@Ed4hIxt>zXx;M>eSGLUxj56)29VOB6P
zYn^8PPawC={NDh$WB&46!0(zLOrx>OoJ7TQ_sp3z&Tg}I85(=c)p(HFX7!ql-+}Ej
zr<{RP_sw-r0RO<ei*~R5=0*v~fO$JTQU=YgA7j`<=2sU(@}b$o0dp~Io__%F5%a1|
z5E(Vgw!-cs^J5cmkIm1SATnn5p%Tq;v-(r?O_)3As+=^p$AYs>na|TEYufxNRZG}g
z=66DygJoA4fR2_jIum%<;zJP#C(BARB%LieB5*F2qiyiQ)uN@ujGKiOhPgOmxl50-
zqn4Laz`0w>SHUL_OX@H<Ps`s_pz3AWGypB$7BSV09kW@ilvX}&`If$W=40u86~EdE
ziz@{#Pg*)?jpu6_q^FOcrFB0fPgyP>0q1Xdg5o^^mZX2t7--3O3b-IkJgwD&Eu-|R
z2(f%3g-EC+oHD6l7U@=qoVH9%z^8Ca&kmT6u-KyLu8Oq0O?8lGEH!ihF3NI06~MEW
z*B%2AZPERMzBo&=4-oMd)7O~U1j|<x-AlA=q#Rq4<y$X^BwIRO!3fV;GX3Coilwmt
zT&iXGB^XS%4E%$}49k+ea4pj^iw)d)%PJd{yJlIG4ZvTp_)i0oW7&Hih>Mo;e3-vv
znX?Xkmn}ae0hnu1P}HfwQbV;vg_bAJLurxaJIYKJTg2|*u2`;o0YHhRZwW}L#f!o|
zWtLP*$d+5uwqj%zmIJgSzG^xDwhaa=Enm?ismgMn?t^QV#ZxeG-LkX;_-c!+0*D$*
zW)bi=EVD?m*7E3OxK?N3Q)aT>vWaSM8!Sl^@UYRc;6sQsSw3K*uh}y9Je1wE+?J!S
z#q#?~*u7;r_y{^%EqOoE{nutG=R>B$0)KHISzi1H<gVq#P~f{PMV0X4o+XZUuich<
z+Nkze$|(%lYl)|PW1r>Vo8azSUTOyJf#v2jNWbOzAb2rgNjV0$2QBa2gtB4FrVR9r
zSnkm=gi%W(?pyrhSIZZRfq!f{L_-_11pS6zX51oM2ZIxqo0Q?7wD^4h;FKkOHyoX|
zJV$vJd+VodAcw5qJr55ZtWBi=I9m6QLFBMCXFC8+R?oj+$=O=r2@76Uy&S~bI-?aL
z$E@3bfr#z6b$J2|`dHODFn_{&V?LDnSsN%7d&>I7UEuw##y!v-V7)eszCf$d0?8oj
zUzC{)wsxI^(h#fQGc<-;pS^<#3bTGoFaOil2c6);t=Uw98(|#_fzC*)M;98;SWT3Q
zNwQfhC}E#$eP$YSnPUB-1%pYou8M^2H0x!`_orJE-vF0kT{ase)4KRQ=ss_CnG2;^
zR?}UKBHOx>;$j!9lY1eOV+|;PGZ(Fs9Ee=9=2CR;vh|aBkj%B#P%Jjjy63;_h1Ir_
zwiyN1f9PmMq4hK^K8mb6c0o<CbrS`|uUNAvJ6&Q;N<?3&_26OP%dAhIL0`G`J$u-#
zusY6%?yJ^vO6XQvGsn?bW%Z&Q$~9{|IeOh%GXarm>ujo_tFhJ>qwj{5X<G*0YOOQK
zn>y>=`RJ^-ifDJ!VBJGSDUDYDA&53v@6tZG#p+MXxm(sT`g~HWb>FuDv{@7UF^BEe
z7mvWT4(rOfAe~nI1vK8a?)w+s-?8r7kH)*!J_pQ9m-PhgsP9>=|NUR^ZtF(+cutQs
zsSB;WRt42j_E|qw!r*;tYcvc#u;xC3rG9H&CAb0WvDe|+pta<6T%AMKdxy~Y(CT~>
z@L}tR7I;5mecB#m)cSvpt~(&hs*7u7nrWJ8sacklnU+>+Wz$ibZQs53-Y+dp>qSM`
z$Ob_~HX<U(lpz8lDB>P~AhHoerZR=^cfP+4_ug}U=iK`~&mHHS`;hlL+J?4S-hdUu
z+y0vcfst*mTtRn7w+%c;X<%d9y7xo<lWjFmqj7xOk9265*mmGo2s$&uDC=%Fqtpwf
zJ&dlu!LpaJ`fq4*VZ2Sw?tP44q?1h9&$zP*7P>Mvgrd@eG36>c;mL@(2P?c7yG4-m
zW;}_3oDU<Hrv3wr6@Sn_-tuKUI0A)!jQ8IL@n_^rf<yp=DS<>F<LQ;C3}VE!K`@vx
zcRMOW82^oegffyTmEj=cBPKc%#^7e7GMq877~~Kmn|}KU#s*4JIm{@22b__N9*XoG
zVPyMbV51neU9iFt&6xHM431&+QU*vYV`&E@;ux$N^eLWkGXr`P7{>${?nK5K+V37^
z1d>lEiBUxn^J5I|2dGSDd_+#5;|v%2<WLG@=>n)Y!MGU%=v2mrVyI7J2q;!{l95hn
zLg|bG+8|^&7(v;fnT&e!fn_mv(F~Q%SpGK9au}aBq4E^tcRD8IG6da_&tr6!p_I=^
zF~GC}#>W(JKh1cVe)K}dI`VCvVK^8Vk|M^cpCC}oSUVT$OBh46-#yDnr?s(^p_qX9
zIff&M2U^DPa|KU1qk0=k=NZfxuwGyUCjza4ag=W6Uu4Xs%U6|*RkVA)!q`Esx9f~a
z|3JkJM$HSb;wIz0Ur~9BabhjNZZp=#Vw|cN3n;u>&G4Y>%{7etc9iZgPTHWMmhqQ^
z&dGI*m0cLby9~E3@YFNr&}4Ft@i$#mY+&4?{Gvuis|Prn7!LB3HZw$1(bmFXih<V3
zm`fwu##p!zR<tt?(SG?p<9*usbuc2yU)sqCp9J!NG4~)W>|*>$_ah%NX6Di6y_@kY
zy+A#TFV{g+FC+3r@bocu(AmA8QBBj%0Hf<VG(BQ`RgThQ#vnPZ2N|jN06N5Yj$F{g
zjO`22Hp19G0kBcV_h-N|#`t^|P@XWF($O}~*m?&76O2i8Bz0!K(MzAf-OWs)gzY^{
z5jnK?F+V3y>3(M5Yap)7d16SoF*n>mn>%xmoQodJ)Gtx#%^d3nix0DxT#W~qZ}y<g
zpZOj=@&U{XFQF93TqVSa1~H#a0%tJu@fg}dn17|CEsWWrr~PL*bK_HJJjA?N3(yGW
zkK~6u%)IwANF;N`d|)48is^h2#f<+MoY71nP3SSq!ViEJ%anbBuEjB1E`cSUx#TOb
zBrxkrP)cN$ae;D_8A}PdNz6Ilqua-r)i;5e%=BM`adI4Ie$);56s9Y^V<(uK$$gW`
z{Imt7G-kmoKs(9&mNL@QnWM=N%wYbr5+sxP(PBJhS<HL6(3H(wN2_QKb02x6PBCw@
zz>>@Sk9KZ(%zw#Ap3i)Ww(AAVU9@1HX8!ylDhnOVx$TfR!<^g&Qp8*q22#vy`3|In
znL?AvS>_y?(n^_q!KggPJbVeJl`#W4QCZGRCD-bC<`Y^^E-=6R4y1zlnC8xl%-_hD
zRLQhb&eA1jYYf^hGyfxB-xcPhHjt}K$16>+<{EQ-JQ}Yvx7eWK26HZLdTuhyPN8eJ
zm>q{vd7F9Z0a&V-6}Qk<&78R!V_Cy|lb*mkOvyDUtYtFjy{}{PoMHAo<`dc#HZapD
zDA35vUJbb>X6nlTYi7=)Ik1H}?4XNMt;~ndVldj6_a8!{o!Rv<VD2;Dy#kmHrkQe$
zJDE;qNIYPAEdp8>GtL6EhfLpipmj5sl0&<P8ADlYy-d|s7}LkRS^(0|R8gMJ0Fy~h
zx<|}MbOHP^lSd)CLFVWi4hRl08)y?g%ygqP_Yr3GPf$3@ba@EDF=h^BUOi!cYrt5H
zGezELn_$kG1Wsqx<teafH!Ex!?A^oKOX0M=tQtCyxUgDiEcUV7JD_(z>k$uNuB@s?
zfVr^(jzip?HF-JhKRsBfX=wCh9a@Y=FV=B#lX<iDkVnjiH9ZC@4zQvr4(`i}zYcr-
zSZ5<p@@HL~4^08AbaFlgvgVTuEQl2}g34f4MhQ4WSUr@28_Jq1hcO3PU(jhGjJ1$v
zh;Y`=xRd0Va)@=97S#w=)lw)t%o=V+DUwz5C5$=3T9=Q?D3*!=63sdr2ACMu4hsLp
zvks6uBY_o3NBKn7KKiwfvA#Wuwq({zQ$UWh=Fl9N%9{KPN@=WE@)?|Dtsz%%I_oRS
zh;?MJrqPs^$=Y6tVh-zUH-_dE>m73I<+8q+0fl+2R!XnPXR#<iQ^5L!Hh`yDk0=|Z
zkfnA9_8C?h&96nQ&$hytVpjII=zR(6JgGR#`g|`)DQiESbI-Ac>d{uldYAmX<qnpN
zl3&lWnmd7gfn_=a`3lxLdW0^ru2aaYlJyovF)p!Y(|UiI75g39uCM~>D@<2evudFC
z8mnzOthmmK)q~{*E9pAgZnB;u7uqe>_vF*L&3fOCwklTSV^mhN*mOLpVL1|RqVW!E
zHEpkIS$9rDu#WY)6peRTuUkRtS*i3~-D3sEqOFN#iGlgeEIqA_Ev))C0ouw^(!GT?
zmOLERx3l8tbabC(=c28HHHUnnovd|q@$~_#o6hcCERhSyL)Lo71O&TTqgx@-!>T<G
z+j?2f!O+{sDx{mX{j5sz&<?OfbQXTZnn!JqS$ApD9b_Hb4$vXi6fwkySw%tM9ARCg
z4E#}6s~*r}tS19NdBV#11<>OxKT5~i&CY2A=N@+3ZAuc^%l?*<==QUV+t5*0b}U`*
zbYstqf`mIe<U?S4uz#oUy(gPH2=!j<2-?_qv(xFL@;>YtGeHiprwyRemt8{Zmmk|Y
z8+!fOv3C5-0c;PtJrT%0zYL0k*xPP^Gnl=@jba)h?9T0I3}rVQN9{p&3=brXy`}>S
zBiO(H4E2ZET5o_xvKLdD(h>GrI-^CgPw0Rh&3^O(IvT@X%!fcMJCm;T#<71P_f0%|
zXbC!)z<zuS#w4;2P#Vfn_SW}NnZ#bbjLv_@*o%Sylg$1u3OvWz(^rBgg}s-e0w>tr
zl=ha&{%9jCOk?|zZ|5X?+S6!DXM0eDBZD3743<oGJ1wzU>>+YQWV36B!IHyX7lX=E
z>=G-)bJ<zsPtRjJG?2?@hdu+fjskXXD0oh@U%mr_3)ww%GC0FNOaA2|_FI0aEM`xl
zd833q#R!<Q?A}M{Xem1=9h~Rb((j?EjD5BUrE>QA3jjOMw%-Hx1$Ou^XscvLkq`L_
zdvPH!ud>Z_b?h2jLMy;^2YZ7Cf;ZTfEl_cjy~l>yTkHTz1HH|@wg8n??1~4lyP6%f
z32n9P6nf+8*gIChio5Iyau3wAKY0z6_t@j(P~X6QGZmbT?B}<ErHTD9Ma-JnrGxlk
zTG$?5fNp2^(Q<U3z2ymQ>pIv+e}Y68JN9FchwPOBFu0pNNK;E6d-4}h(a$bf2r|HK
z`UWh6?9b@x^bkAX1;7lmOG1h~;7mPf0`_iB5f5^EI5#|@elMrIi5_mw)+!91D<_3=
zhuk<H(5I6<IYR@`?!}qg3Qlj1<#}lE<*cHMjeeYG>0=@OoW>Ef1#wibf-{&Sei_gq
zoKc!k!#LZlXbb1e>;u>#j+es|G?Ei?8ns6_=jdUH;+**rtg)O321;?9uE|gz&-sQN
zrbjvaYLt>Vi{v23IDM3Co5Fc_99Ep*JPv@_sho`-D5Z1Qf5N5=PR1KR$>fy13xOQY
zU-Wr^QyeLMXfT&E(Mvn~0uKBChi{HN8EAzZRy2$$=1gRuRKnq|fQ4r{AJHDKjN?oW
z^m0yk1Ypi{-l8DaMUIU!{%>+}X*IjWQP8x0oAV51LR4`+rPFIQ=MlMyYdLN7ZQ44H
z^hL1T<$QO57Sno85ye98aop%`UIWL8Qehi8%L71~I2PJ9G;<<OLB55Pv<vE6IrI0U
z)W)g&918DqTq{xP;KW+N*~wY49(o^ehMa)e#rew{-R|bZy@XEmaN60>+soNg4Cp@2
zTR3Psru1_TQIg^SXLvCL2RXG$kRgu806>R1XIvmZ##u~XWPHN;M*)T7oJ+Kgbmo3V
z8=>9Ye)1sf;a<@~U@uoiksueYg93&7xfkiakSkY8E4v%FhC1lZ%^@%kZqR!4#o>u`
z85F&^|AxX~Z|)~=L*9p5N(qn$xU+*ne7TA>u)>dfV+~mRxu!3mDS(^Lhg={x=y_BI
zaj!MOv|z5}B=m-GUs8dDa!V<`d5~K$A8ldWE*Ee{a0QeXdzd@z7Su;NxL+JXf1|ly
zki#{Gdt?p-W4SYy!qNopAKyV!B6oin<d1S!*nyVJ9q32fajpwFYE!ryJ^@S`cgGf(
zeUiI_HmvE~Hz|yk#nse9E}L7w5hyuaf0}OcxIQ^(%jYgW0)YaqLwglGXSm^%!c@d%
zY=bey++XObX(?Ah{=9SC*)*S*ac^G+XF1n;6IPt(#?kTd0{1O5jH%$pT7Y(uyQUA;
zS8_X!K+`3zCnbtr=C0TXuq#|P8&+K7enw~D>s&Q`_u&Rt=Afj9o7}52L2hvq$ZvX^
z`=<tiRon;r!CJ#T9SJM$a5+ywzLwiXOGX_xG7|E4xr-_wSI;f#L)$&>ixi-2;D&tz
zV;Z?rv(V8du7W0tW^Q35DqFZLZ;*EGs@Fj7a~E+PP|?8+q07=;+zqr}e#pH|N$=g<
z&4Z}y;TFk&-OJtkE=V7D79}M0b90u0Wq{i>0xKSIcWg!FW3KfT2n=%nBtP*Gcm58L
zVeTEeSvbPA8&MkNu6+i2$GE>tfIQ)DJw}V^ICtG1^kRamq9h(?-k&n`VmI$d1IQlU
z1Dc@r^0Fx$=E57Thu(d>JW4Lv&)f9^+FW_ZX93NPC!pWQoi`=}@!);35uBd9*XZh)
z7cayKR(SJ1`5K%)yq{<pJHVTc=?cyq-kpoE&5!r$Y!H8*wHcrRyqR~w6UbXcdDB6>
z+7Cd2dD29{gz(ZRM>3SRh5{uAdGW7c5W;w!DbO3vvyyl35bvWuArQeEp?K6`-ZvCs
zkK{e3_x1?SgKl+4@fOeq$`Q@${{x^gyj(iV#`3;AiBcTz6g{)?ymj<hy9D0T??6Q&
zZvjnPM|t@_<A+V+JrF|SF&>{zFv-03yQn<Q`*t<3Q+PM%(&PzVA?5s~@?IhbZyImw
zM?g8rJ5CEoI`3OLV`VsaSzdt2=GD;ZlEeFJC&(#Yd;(x{c?)(!eI74|B5wJ-1%Cpq
zfS36!uut=D(Qp;=zNQ!N4DZ`>5Gdm9CxK#KRxU70c#pTBbe6Y;zQ$h4dny+w=Xkq&
zAYR6EWI=s7@8wP81v=03n*_8AJio;dtl&)xsq@4CYyVAx$}7Au0pzdpQum?l8t<V$
zG+pO0e?c#9@D|b;>n3j-xw3BYa_B63o7eLMZB@L&4ItILziCKncpH}i><;e``SELc
zK7YW9I^Jvw%-rLB;RKcjp4TT}Y2<AVhuKX$XU8abnt3gUp`wMSE<kN7uks_vxAFcX
z4_rI%y_smc&uiTS&JJGqVN`bV=B+~I1D=pR4AsTkI|{jnyclvtb@P}MOX=ZttO80e
z@2Uql`*?Hc=-<!NP}FmP$4|$|JmL-c(<JnmH{t?`L7u(^CJyl?(Z!HqUJk`cM|kq@
zK}LB-Ge&ldm&$|S6JFfc03GMmECHF|?MVfTGylqFDBR6&41`U4`0MHC-OJbg1_2lT
zIXZal<8S{2(EIty7IeaupLLDCH{r&gLC#orzAXSIdhj>U7h*j5ffbPV;+Nz>!kfS8
zAT;^#mvjK;0Ds4NRQmEWe?x!$__HbS?9ZR*0ZRb?!}aJ=Am1qsEJ6Ic9|AL&&smSQ
z5dM8S%7*eMABUj_`N!8y!n+y9KPrKV;r#dLH#o#^_k@ZF{sl@?ILyC8!MR9&_6`i&
z5q?_|1f%#LQoJLYFWiPw41XETOtJhorh>%rgAYJOJU@<d$`bg|vw)Js|A`W)j`3CN
zP?^ks)d!}X;Qu-uy>_JX53GX0Y5Y;z2j=j1B!DN6|MZ)H$>)DYL6idi`ZFM>`RmB(
zT*yzOwln-CD*#%=f0_Kl#r!pNkF<n8?J7V^`Pr9HI>%4H01M0b_7sSh^J^!e@;v{S
z`xveZ{HCA5dC|e2Li1}SA1-gKC;ZnhLj7faB3%W!!sn*I{Hy%SW{_+ACF@}Kb^aU*
z@ZaE1rqjty{`d4fkX!tzt`NA*f1YC8ReYy+ps<?1YaYOA_<tWj+Z}%FHfX5j-@5?o
z>-dW(UHdNI@#Z5G>-lqOXK;`2eiWb${DKUa*vR*%AGV4AF8P3)`H$&WYvG${m(<Gd
z+KW;fzc~tW?ff_&aNg%X^$SW5`0FW5+Qq+{2+oK6(i)I%{y*_Bt%qMve&t^Nr?lbh
z<99j8vE0x9nSA^M{NFI?PkF?jeg&0}`QvOz4D#Qd0h@;SO{-8E<~!G+Ya@K=#}F9h
zr_l|vF@9(#DxdIE4nWg5Kg$hdf`6IBodsKdfWp0kIErPs2>Nx<yH9Xy0|fR9MrS(E
z=qiY6hYB}A6|LLuf)1L?JOl-l@8&7!c@LVr1fCQx@fP?~u*pXd^*Q7Y2rm2yO}>Ks
zJ_z^;G8aJHU(h`Yxd1_r2qaJ-qzGY<Ajk%mV8K*+IYI;_D#(QjhSpJ_<Dg&}J$hk+
zDNz6o7yL+Wu0sM`Y{q*axK94~BZ67suscd{kk*Q5!KF5!#R=Zo4iYbj-vkv2f=@Fs
zcu9ihB(NM4yd;NQvY@CP&?f|(DpaNlnE5EB2{uNcOBsSzA9A#23VuC?;m#7gHVlP1
zf={1^rc;82vml=<aQhW1@&vAQBFGoi&=YuCQ1>R<3I$mwP&y;{o>Eea1sm=`yhQNB
z`>^7yAd@^{rGj+IcR42rqhG6B@XJk<&I{B=*n2^+_b}9kJP4WmoZ}0m@lClTNTmJc
zWx<nQ0eD4lnPPs|1Um-6c3m)^VvRQh&9y+fDR_-S!nXvcKZd|<!C&8^vPQ6wl2z^q
zT50;N6}&|Ut2%)<>AWjg`X@-epf?Hv_XHdB@!K>A=Fdat8U@J?+LUw%w6sC%6pU1Y
zJP-s>e4tBkmI5yi1sXbV_XrkDhiSb6<06#$1V3e?lLG=D`Y_O-pnEskh6H)E0uKw$
zlN)(N;7uPe8x_2tjkYm?>=+DvBB-Emyo?LtSHRv0!J01}sC5>;yBuV<u;*n+>=8c4
zMrptBFs)Cn!kZgV=_XuEPl&tlI!^ObJcL4Dz<3Jv6rA)DhV(+Ow{SoC!hM88$6$Sc
zaD?)t0)>ApKu3dwFOLH(SQtT3*bw1Ex@s6I+*Cn}z(L_PI<SNZ>nKzjE}ZofV2%ju
z(xD<sxMVFzwD4LX^u`D!wC#!&{%{G{aY8P=H1Wd6wNQ~DOjm&<3VR#Swc|o5MNCqJ
zpHqbBgwS&q6s8Kpzk&KRVLNR^PYV0O=mt@`aC;d9GlW0105nsW@(dK_2yagV_9@}f
zIUu>h@3PRAC#+cun0%rCD!>#7!+t>JX`zc7SPF$HaZq?hxcMHyii8QPfKn`sUW~R9
z;l9VHEEk55<M+JqG7sVxgu_WN%~2tIV><eKQ8<eZSe3#`nw2gI$LX{GmxWHx0rZOS
z1l+n)ZVH*pfObn*dL5Owg%aBCRS6YOqrcU{aEck!2>lyj;T_=?iZ#{>FPB3_opAUx
z1R8}G=|t8fG?xObS-6^RdbBu%yh_kkp@^RRHsRZpH`^}kkbvA5o}$2bhj5UNV%@@T
zq^Rr>K93;flwRS~SZL}Ko+h_jzmWMDW)BE|qmAq%q3$PeJ{IP`12QPQMc=C$5mr2h
z(x`AS88(dxCvAqn6QN_yTA+;!-yk>Ggz!g-p*f3YlPhw!Xfxe0+#{Mg2P}I<vqZpl
z5xu($WS{5<%ER#xjYOm5DO%eA>%BzN=pgAWx*Uu)9}%ku3J-|lzk&6>B9TAr^%JGv
z#aQ@@be}_Ch^Wbt3c*m(CVFNMiUQ(+7AEQ?FKM_)MTyvlL_P-C6d_tIhx}pD_TQi)
zQpEily@(ZkRtJGN(RF(C;zci#_aQ;_K4qIEiuT-t_)*a^6-bgOsSYT|L=_T{WYJqK
z080}k85}U<q-X^>ywXM6x>1`Uy1fX-WQwNKBakJUNe+r^(YHdt<cOAd0Q;2a<C9RB
zFH)X>c!4PM0ZOMuA+*yk6j>fX;Ed>pBM>hV<+{PpV$q9q*{(!1u>|C-$W{amrK03z
z^iN05i5QQew@eg6zU7Oevu40liUMi@b4m33MGVkoQMnwNu83w=K+{!G00ncei4I7h
z;<{*29zd%^U9|R9i=J`?OO0r*4Jda+zH)HZiadS>Se<C$0NU<~ey5#Ty{H%wczkq7
zG)NJq7E#XMsBIO6$I*i*T1_{k+eMQz0D50^p7JI-M3YM(-zjqa0i;J{J&B*PS5!sM
zdY?!?2+}WdrI^8h=ywkEJ`#EDg%yuQ;k17k6iv{yF(O(+PM%TGH>*G#W1>xzUiL(^
zko<MyqQAbwAWVpo=#=Oxp5z7<ZsMIsA@44Bp-6y-_^&@fJjKp6koOY%>cQeIeng9e
zk9Zp0mp&lg6$4Ga;$62<@)JKr`Cb0vN^<!Gh%M<bEl?ar9^W8`c=BPugos&T01Xu@
zcLC<0xP-jAVd6SE_lJu$^vFkuKcQ*%u-KQ9)gtl#xWE}D{y7gY(c&)^0F4pPBd=_%
z_``kRj1#{x9VAiQw*b&b#hIOGOA;s0ihoS}oe`MHV#gf%`15fwi?(ek;@izYJ0V_a
zfncim++y_Nr1%nT7t_Upzd<s@8z^%iQ~Wp*BugB<93)$8dx%b)5^E@FIafSkgm|9V
zN~w(b;^(x0E)d7j=eACZcdo}U7m9N#VbdA$bO*)mip1M!6IU$e?!@4ih^Nxd`>c3L
zBIHZOW%N9s6OYogRVEIrfMB`!Rq~*o7tf;O>;-W)Io~V95%<7yQJj(imP&EKDp-F>
zoVE_om&K>ad45H#r=RJ%Sa}T^Zio-eAP3=1@g(vf-4ZJ)YxuT!JH?x-#0zGk7d7H^
z+8Evu%UaRVTJcB2Aa!Ett5A4Xy!%~{dhrSiKpVu(bd+iow=V@tlh~&Lr516pFTh&G
zt`u!+6KkSiOuIOt3DEb&n~&2+FFVBd51<#F;?F(?PnX!8GKwFHzpF-Py2VH7_H~c=
z0nHn|;@llz=@+|a0%kzG<z<jZVp#}S9*Y;h1cifQZ~E<r#OLN>5JtsY7DH}Kyy<Vq
zJrRp4LB_@Pbb6T(&wvBSF~wP8Sc&3p$wpULx<`_>9};^dKI9{Ikqps_w@;E3hPM5Z
zzVm2vm3UEBx0}RHgYPbxL0&@-$$9dpdP)Se(t1g}zQV|OOZ@0wtB-_3-kk%I-!=o&
zS27U-v;8FDYd{?SlI2Rk1W4A<|9S|NoNs`NAjy*Np(0rF(Gh@#NIG9bWvC=g4w!?I
zj&5LwN%HeS!X?p^J%31ICr40(MDaPuVaYsC$VE!tQiJ7)<kdA8k|@ayA83e{9HvNI
zjAT2lO0f<}Aw8^dlD%7CX}o0Q3D6QGF?1I+N#gwy<c~>~(s3<WvX2Gq<B}_0z)q3u
zphNBn$p;i_NtN9G9-T>(%qIW*Ny!e{-K9%D7=>JhB>zWnW=bME(Uv8tpxAe|q?x?u
zITD9p8PHBiUZdp8TuF2j(DEcdeFnjN$-O4P6iCi+&~{o<PM>EfluV-I(iurSUAQWe
ztf8Yxv7}=XSV|-dC}r)e<a2U6luD+CqI6CYL<t^cl5f5Rbh+f|g|Onhq>DCp7bJ-e
zno27q-SbhrD0yZ%cq%1@Z$bSPNy|!*tCFR(mANK)={c}mm;5jj<c1_@3pj5|{y773
zOA=2X;=C=fH$qdD#EBvo)e@HpSWzR%n2jIpjwIj!+G-`+D0`w#GM~bNcO~cVQnpFG
z<SgYI-jn=z2oepFH@}2@qh$Z@kZ6+pK)+A3<i<g$Xpz+JKxM1McQQEJB)!>a>yV^p
zqSPsgqqLX@63H^KbV=fN0`sBdnOJD*k?f+>v0lkCO33V!{6m*+`X$xFlx;E~scQxH
zBgvArfEkqR?uY!4q-zochb4-348n*+O5TT2Nr4fSW0L$gz%nk`O0lR3Nh!IJou!Qw
zzTG38x(zn%m9F?2B^Rm77m(X0eKrW3`=uWAe=FRi*+n4k(qpHdoAk^S4=E!=7K>2L
z+!RP0knRwm7rxR9??Z*3lr<BT{!))IR0c@LM*tHj#c3BWhcu6zL?O}^ioJzO&j?`s
zA?bRGl1E5+-=OlabagC@iIhI38<t0;2kELrw6yOsdLJX*Sr6z~>B(~di<7!LXbTlD
zZJ<QB1Zjg4<P)W9XgNxfwx*-<m~_o4z$8n5e+2pC(zapzb}7>GaLA`h=gok4nlxh+
zawnzk=-QNYsp3}%WJrIKVGuH<pGHG2OPaqCa;K!hbYjkx4p9^~Pg-41uHt;DU?~I(
zr2pJNsZcs^JvwtnI^$K4A}Nc0(PHWCH=wXYI!X@4v(mEDXgeo0)4N$Fb)xsSTzWGd
zrSsC?K7_&xQnv+ASRwsG5AjNA6}<<Sq;8ape_48gW}T~2=2{BXT$8qpz|!kd&sKE%
zhV)NzTildxqr{ZkQu!&6D(R+npjAt65UG(~q!ZsA=?66UwfOB}%w4JeDzNLNKN-<>
zPr89TUJcThXzp#4Zl=_+CTYV26tzg(DIU=(^?Zkp!)?+a^1^jWH+>1g2U2Mt1iPel
zw1IpmJv|K)-O_i-z0)iGHy3Dq((1V=^-EK^AOlj>f3WG1^bIGJ9!q!8UTsh+C0FFI
zwEiu0bVU052QY0^x^W4}nAG=QR6dcGB|^Y4A$9v03Y}$PRWNb4%p1wTQ})Q_E<kCo
zY%CDHcabIk1`GGeHdBDuO*Tk}V0YP@fnf2FO{1NKr_B9B5HDE_9fG}O#a*z%M>c&u
z$N|}@7tje`nd&&&{A9J{Z1I<+(^MGXklnls>_A!8S+EAlrtL;4SeAVrwuQ)!Qr>N-
zY+e)e9+asl#VAbXaTDspWg`or@Q|#4{8tgOb(H&cSa$1GsECxkh=}%-BeFw#&=w_o
zb|>1RW%FsFjgci$5>%`#@iL&}WR4ixbH&SCO2L{SJN+_LB+AZ7A#qfe`4%iql7)T%
z^N-2eC?hLbmP9Z7ahbO}N+~iw3t&#jrk_V=Qf0mOA(tlW+6aM@vM352rpwfyfipvP
zlw4KWGDRT7b7b<Lz<Elx%R!4pzAS*EBLy-${f4JyY)X+Rl5H)=SQN|7P`Xu#ERlB6
z=VVXOqgy5`rSopNY+D=zDr8)`|8Y?^Ocx$2Ws7NxdquW_V#rrzA|=GH$%L60nVYgz
zbk?~gv(Tz?TQ;<T@{Vd``hDQJBg=jTq*nHj2C7~bd;;?KWWD4{X^;uYf7U2_g_8f9
zWdA%3(kxp|+qxE69-U=dWiCt5wKkb=8Bp3~A9sS~zU=oLuyo2i6JYNH*%u$8)Fpe5
z1GNuj%@Uf4yJZ?$C3<Ch^bqWmai4*ve%V{}<PXTU(iz~9?1N4i^H^4?MBAW@yA^0d
zvdC{yIV_t?ZlMvG_wP_RD(ks~5gn7c(X;+URzabfaoPM!;GB?MHlxj1Uj94O@0L&h
zgz|3p$T!u3XP-PX01EfZSJCO$RX+VXRJh4=`+@B)7im%HAzxqzr>A@wq7_rT<c2?i
z<|F@_wq*z82WhkAD=+0ilb?LbRJ8fa)9Eb^kYAY#mOy#=C6FNbDSF>S<&8~fa~za^
zLwlGo`EON_h>(9s3(#Ttq;JugNco*4kR$TVA!v(|C(=_ABi}m)^|A6wI()~;&-{nB
zczMhhXiJcfZG{zy@<Wj*9hHxMgyBk(579CEm^_PS@ML*4%}kl{pJ|rPa>ymlXv~(s
zAwq4AJd8pCr{rfg0VY@eDJ380$#>0yh57O-11byT4bPx-T0WJIE`@TT5af*9eh?@{
z^2=*Lisi2(qiafud=<^MXXT&10L)VP0(YoCCodF&rA)qH9^}g9jz8!acwWAx4c1(c
zH&NuWLOx9SuNUQMy^yGsw`@b@C3y~I8eNuu5ChID^0aHHyeeNnFXc746J_(=lo!((
z`j-6KVHkQ_Uf7Sy8u@0LOYX=6d>~LOk19cBoji}ib9d#hIxaxIUcP=ZG&RbfqSV4B
z`EQhM*(?{)7s^}YUXQ@qDlb0*`8K(T#-d&B^$bAo%iYUBI^;im2)&*1EgMmKApbN7
z>bvBU&+ywllpmQusaxJ(50oBx?T_H>l?Tw7v`_v{6djiO<=^dq-U0da4DdXXw_SrV
zkLCR*(Kaa8P+W0H9zZ+$Vfo!F03DH!^n#4a^>Sd3$@vr)d?GI%!*Gww2bQCU6Y_s3
zpT$`bs)YD%h2RRz-lJG#K-*r$VHy$_MN196fBO`Z=~dgW*l-bgT@~R!!U{LVIK5o%
zio$i!>!C2-g$hr_G#^xYDem1srMJR`b~HYUSUPR^DMmd2>aRFX-#`dZoTke&fr?wP
zup&s2O!4tx#Rob-hbVF>q8+Muem{ju4=P3|P!^{6g`9=qiYXB=_>dx)Qn?}&A0I{A
zVa0otu@|YR=b>~&Q5Fq*qZHrLLLIGGMd<`Finq^0MXbVn7z*PQO3HgkP`pTfkVHih
z&G|<a?_L2*l4AQV$Q@JMv|<b$#}#uZ2A-nGItz&tiZAJM;z`Btlv$Fl$fvn1LopZ#
z`AmgqJ4#s!r3nhN6><I;(j3LtbS^oi@KXacR}n(_uXzfC1OoYrb24xiC_*UD>a=3X
zOmG$|nm&TQGm3yaP+#OwxEw)kv0@K>w4p>Xy%nXiis^^Y!&1d}XJE`ZMbKW5GDQ(B
z`{jx|<dQnC_#+dX7ZiRba8@Y3jDs;36>XVdsZ=~&4i%RaCV%L?te8Znsw;|kIv-qB
zXd57KO|g_V*w+<~SIAL+Lvf`VjW-oV{wP%`e96aBtyubhH@9L$hOXUFSc_0utFWYl
z)G7WTH``rB9DS;-Uh(>JRNhkzo`R+Z#jarpG%7-9U(~FqcosctQ4~%<pj9ythqi}`
zfkKdOg{OleRXvKA43O_tOh1iMpQ2zMOzc<u8xNiVMI!mf9x2k#0`0Nl^4B1Pboj*U
zp!m^(KSmS-Ea)9oOwETeV~QXyDxWBpl%R54@zM-HPbdykTIX)%t@mKe9%X4XIQJ^w
zpG+r_{mPzJXmVBl_dY<~lzw$6xhr?hM#)3@90$ZxS#$@cc`28^gOaz>haMIm<w~;S
zfN}#l#Ql^me*x5A`AG~|0+d&;qZ5HjD+S1cl*uQdH(0qZ8z>>lkKTiZgUYE1wEqlK
zy3i9Gu54(4;2~u{tu+zKE9A?HRQ^X!(Id*obmWRweo7m$7-b7>#A1~>l$e~L3|<fM
zMCHKSkUOeOBJadW<!-uam9DIR6LJ~K;90ODQz@jCGD|r|IgHuLY|N{UDY?pSy2_oW
z9Hu2FU%BXcm{_1}{06M2m0Ku`RH*z_0ljCGe{F`sBBdWWt&5cp=rT%)Qc8RIv&yw~
z&|9jUJR1UK%11LHP_F!EIylcO-zHD?1*JcExhs@^MT7H_a&aGQa$Hs}qUG?4a#jk8
zSCv05ffd)3Us0ygb!E&wNZe3fp?Jwn<;)EbyrqmKPuy+gVHZ?ZDfu_RS*;98!XVTr
zxfG<lqpYW`NUgH_E-b85&Z&UhUFG>zAoa@k>9BH7Swi_V4Gv|^J190PFDF1#lX5NX
z6`PfT&5&<VvMEB`s$5QI+BW5{F9W+>IlB&m_mxjmTZi)E7}`3O_sPrmKpAized$uh
z(d+wA`F0B`yOlfBKzfuul+Dnq%qjv(pYoj{$n`57ZR9c;P%e7|>K`fBccJuH`DHO0
z2bF1*o;IZ1Gar@1%8CIf98qo&18r2fT?-Xs%GI+V_eAO94wiAHnT`n)%E$E0BxjXp
z4%+spO2}`sPnArEy8WtT`juT()#P?{Qzbgc%jd4jcSfU!s`D8%da7<-g@l*Nav6i*
zt(s3yzK<&XZy0kx^)!8s##i-~6WaV#4K(Tct2$|s2~cfVh*G#}M>+H!Qsv(Sbc8DO
zTeKZkolQk$q-s$XppU4&`T_c)R9=5NAQ7!P^AtK0qq=qnrC61HDFowGCn)e5uX3W-
zKS5PP30{e+_b3nOsOoP91d>!9<N`mY`ji}q$*Q6>v>jLRonc{$D(4lHPN?=4fHPG!
zgKk5nslJjz;G}A39V*jR<Nr_9%TPW17ba$^^2$K6R9m|spRHQ=4~)rCxxR<eDb-Wt
z>daNm{|_vAstg;j^Hnn1{1>QlXa+y6dOVH+DpXbLz<EYx`x=!+st-BnM6t@7;w2@j
zH#&fMR`s(OETyVdL6h+Qol|}I5m?JrJ>z(;&a2)hf7Jz*b{X_ms5o>J@1n|!46amJ
z)}t4fR0#`!c3I_485&nq&b3f+RTV>f;%h1i1@*40+Q^N0L-pt@*n3+wXDQmMR7=Sb
zQLTEDe7QBMzbVVvaYwbh0mWLCr3qHlseW4tEAFaho4{JHN~bGC_f%eALB2t?i~`M#
zs;T4<Z&Lm21MFti-KPN4qDrFxK&#4`&OB|Zqb@*cSG`D%*88fNb6|FdD#jCFovH_)
zqV0hyd@D$oLnR_F>_b)XYRGr1oGH%Qqw*v_b+0Oh5(fKJsZG$^ui8$p%z)~1njasj
z<SSvtV^!^!AcHFLkKi0q)zQvvSoI6JGe%T*e+C&<<x+y=m}=P*Sn)*lDaDn>RYn_1
z6Dr3qx6$aV-bLfJS6!J32^aN=SitO4w>x1-+|)YC?r~R#L_yF){pnK>^j0rsf%vG+
z2VngH^#w|b@KwL@JSzRv|57TKzxo^<;{w#CpHK=^`&vPQ)J%F+g4I`PI~bzYI+mjt
zs{ZdQupU&)9)X0ZuTrcaTz%_Tbo-DxJ`>mxYAbE&534iD*%zt)hMa^))Xz)>Xp~y>
z3M!-3&y&9>M$M;%FIK&7GDw_yj6$06>YF9#Qi6J3Autow!P`+frrxv80W*@-EOKQZ
zS2xkDm#V%@&s>^1mGWCos;AJ(ldhgtj8caB)-M3fR1eNZWtMu;To{_I_MeZ+9Q9}*
zDo?2=X#ke1{(3c_^VA&`z|2?Yy^m6Xx{C>NTCEC!6@}`--|1T-XVf0G;3-l!QQB3p
zdetSsl&AyfLhV`gJi01bs=iT<wsY!JnW!vNuOWv*xw`drJP_yA7K$-kP;aAIx<akm
z19DM)kY@Qx^{+t?zoh;l33{)pUFaNkO}&ufoY&PkS1A&8L+$n~<Zr59Ux>zA>JB4R
zRIB|X(2E*%D@B6usN3^Vy04y!1coUc>Lb5EeW#j1-qZ)`FKIdJQlCl3AUsqnXb0A<
z&fbp79`%AO$n~nVENJLcx9o)8e)UpH*%?rGkt5IXNbTzn6_3^TDef_-PQ3y1htx}G
zejQdXrJRlt^?b^|9aZNSqfcXMBP|3^)F+c5=d79K44B=TtH+>skLC#7jM=M62}Pxg
z#?=#KpXM=rZ*ITlpdKu)n(Y(^aMP?@4`_FXrfeCC9-8MbpiiEfGztZIX*RZl)mziN
z7-&8k7R`DGG`)08@YQ6|3*@JH?Ewt+*VyS{3D79SKnc`n=y(&PnL!Iku%>}toDfYv
z-R%g~R8iK#K~3UhXb98r$$1s7aXcjk%puMB11LslRu`dkShLLwf{_{}&67toTX+DC
z(xlQRFIsbs9;g`2?{v_O)d(o69;fN2_a|P%rBy9Kv#SF?Orqv9I>;Q=43HxtNfY-J
zppR*mJ`M3?%_-WaAJ?pKY=Vju&2E}LPH0Y0B2KF2-2n_ung%J`cmXuh86fGJh2#j#
z(73IKp_!TqI$~yN{@Dn$Y)v=?mU1-nC~R^{Q&S4;T+R0pAbFao{m`4Qsiu!F6lf~H
zf%s`n*#QU?YCedk{pT4?7)_-`nqSrcv{-X#J4lJ<>3Wc}nhHAFmTIQc)#`Ja7iIva
zOk)c`Wx3`<%Hln*X{>>T7c`3(LZCwP`zcgj)Qr(^S86tsd;5y!6N(C4)!d-q%{9%x
zloonj<Ng$V%k_q49!<qJHCI-`id&kKlty@4v(X>@t<v~<L9kl0>p!Td(fmp=_B)z&
z>8PyLD8B$&ohFupalWg0n>L3Hn(`5}HEL@9zes4Fc@bdEnlxHITQolNV0No!#%Czq
z*E|Eakz-1SCgdB)cWQK=u;QU6h|ZSXnrBrYJ(>+{wDoHu=rtbDOkRl6BTbAI#yr-@
z+hOmZ=Fx{RbV##n9!kTSrrp3E(QKnMq*2WS+IEj={3+M;iN-P)rj2X%CqrOD^YIG+
zb2w{#HvxOMcEvZaZIAW|ZN2ttpPWRci*{lQelAySQ6sS3w7fhBx@-GrLiW<$?tvBF
zT5meS`)H5RKgm3xeJc%ezS@lA5b)DhH$tJm*0&g%0<?<BC<SWk=EImE?Mwm0gB{vV
z+Ovgdjr8n<YFTfi@t`)W9-v{`|LRc+*Z%k}Y&xXn3<5hs`*sB?k7yTjpdw1U;tz;N
zYcFci(Ku~7J^ArkobvG=Xk(v8TcY;z4w!aS`{gv0lC);ZYCWd??l}k~YaKswq3O7m
zu?Kxh(KgXHoKI+T$)S*{{d^mE(zKt`CgP-a=OI+4Yn|7DWN6)K>d(~vO<vqA?dGGf
z@RWA#1+?XA{pi+Op0<_FZ^hb@E$CT^_9-lmQ_gBRl$BSi9i&gyoYQV~P(Z6pyXHCs
z%eBq)qo3E_TnWJo+P5jkwnDp{K3H&3o861HO6_|dAeXcn1;}M>)NW|HqFuWN>aS{f
z8Nj}#{WTiox;Bf_%Wi4!PXfzrZC@==s<hGqR90)hqLs2ntNf6DygS+_w?S&Pew27y
zrwt(A>|Je)Kh!s9HMc+-webfr2u<3Cec)`?-lnrwi}s5J_$gYohbR}JO*=|4k#=oJ
z5=!^AuT2Bz11+EKeRXLISm@_N?I49Hy0xdsh25jgd7a+BUhOaswSC&>b+D~pyZ#Ck
z4ro<$Fc{PxC9lemHfJ@+u$KD(f+N~%Pk=V6Eu%MmOdE6x;!m_~c_8E3=XOKyg!X3&
zAMVlZx(2zuy6)d#nu~7seGG!DuEmHpH{AtT=$PWJTTcm^Ub<&TV5zt6i%XFA(XAAr
z<frp+Maf_HHr+}L(5)$eO~JZ?XVDg-bNU?Ep}MP~5D(W)J&DpGUFJ(LEkbu-KNQC5
z-jYEePS@UwQoK%^jZ%W{!arb1)U~9-UdK`0-fo~J>Bi_Ne@yqn3s9J>yLTFu$93g&
z&`r_ZA}7=d-NrY;lB(OV4lHT9*C>VJr0x~^H-_oDndhKBL${6`Hkmpv`d)ID&Y#XK
z*}BCaLt&2Y14@WGr4!Mms$AXYlmwjT(CyX&G+*cXI*J9l=iY+EX`R>|1{dn~5jmqf
zPvL|jonIsjF3}m{P&%u7YX}0RI@|NG;+#%C8#a~c_%vIV>%O9Z@Oho&5yUU(won+M
zLig7`bmF4!_z`ec>ReqReo5!>dIPpy*3Dar+AF%Hdx3pb_XZ2{*K`3!NL<&|rvc`M
z&fyI8w{?lPP+6s`JOs{aosSFbt<_B?XI-6cGI{Cl>hx+<Ht5#V&bm>zaR6;ix)YaC
zYStyJMyW+N)gLIWy8RAv$luq^SqsvkW6(LhQ@3y#2I`^Cja>fSx-=mKdvr&1XzSI@
z3WaHXx~$jG)~{1XqVlosJGvh?sOx$SWJu>tZp=~LUfRWu>E3-CoKJLP<1o!x&!sNy
z)<0sPZI6CosRMo5r>~ld+Wq=%Ujf@y{||-3-SoBOZ*tdfiU*5_eja(-{Pf!>-^X8{
zPl59Q{Y>)W2I^lOhV?=EmrbY)*1tmg-Vl8UrAdeC?@_MmL45~B)xz|y<OvAZH@=9$
zJEU)qC;w-J-qQ`%9M)^FwVx8Hm%fI^Bl?9L7!#%c(i0?F&ngCXjD8{pZL#`DIugg}
zT_|TNUSInaR3zwkSEDUa-?kHANA=Z9(3Yeh^M)12^fzjuH(7sV3Jg82e|9PqrRbGN
zWpGS6p)Z{W>{Pv$lD*UP*^~i(QlDsqM7sV$5K0;PbM$m(>OY(VW3u!YZ=;m0|F{Tf
zIr^=BKs%*hb_`bJ>h~Rj`aFF}4l48Y&6N-@(61&(?P>j!IbbQ&cRr2M8GT|oP#i`2
zl^oO->-%G2eu;kJ4wTO73r#4M>g#E`Jg2|lic*<A<RBE5>)R<#dS3r=DJn1M*HI2c
zh5qAB_+c*U-wTG>m3lcv(=X{gf?&mE{WeOyx}skkfYNonoWd<P^c%=4a?_#TMsIqR
zKFJTY)%q!vHBqA<Z-m`-dan-vb65ZRe-NzKrz=p|sE?Tiv?jgG0=><8uSzIv(`)Gv
z+^(N3gcbMoZC?YkL;q|bSUU9~G%r8Uw=Ds5mtIdEv4{Hobc*cOJ9aL_c=hO)BmkyY
z@3s&>MW4QaQfvnFYkHynk-m~9jK})WU!iwU-?Sd`LwZk2of_6ZphV&k{cH*qjOwSq
zincMmAKmwSqA&Ra;^X>sUuc@pcdS5voeg8zXxnXA)`QADhFuO?7xo&mia}fq&2%!@
zXE^MG#{GuvtAXZfSpWao+VG$o^6rKKnwLEcZ;F8JX?XuED!mMoL{RT-&^!y`W7sZ%
zX$K62(a_{;2xo%R&tQy3rN5zKElL4~N$-L)(9rfOy?;T5ib%i&8#YqbZHS?R0%4(s
z*N(xMgNB!<fhElFA^k6_aKksbP=CnKOhK3k!((#W9yY|%je<zSU!~wYVlX1CJtfL;
z$_1T>Hq844m@$Te*Fa(on{NR+&TxVpdGUs)bLss{Fr<@hiH0RKQ5`jSlUp&#aGFk6
z#|+6dVI&(q(tsQ{<W>MX#gIo6#R<bZ<1i-G@Kp!Yrx`*i8SbQ^=_i1t8+JVf6&Z$I
zlfjZ{*bxk4vJBT>1WUGI3GJ?O3<pao6Y7+q_gi4+8amohn`bCI3ibJho+T(17-mpp
z^|WEdCosRzz@|;@8N<_)p|Hqs!yBN*hWnJ<QeyC-5YkzLp4_jchQ6nPa?aqbgZeT<
zA~}}J4cmk;?Yv>xG6-BSd{5_OM}=WuI68CDa4sH#l?Ev-XO|4$P{iS~p=lvBT{HAj
z;>>kJ^ZO{>FzjnY>84>m<^J9>JfL;xw&4P030E0@rK!K#@C{`U*BGANjJ7+5VK3;d
zH7Jh2!aBoRN}9N9SpNb9>K%rgl;nKR@E;RKH5ht7gWg6%Ya<$)3=f2mZ#GN`Mq7&^
zl9u0ALpc)2rnDK#l_<3v-2Z{VeZwr;Om`S`l;7KFSh*8&4-73a(9~tvy&fzN4KbU*
z(ru7Xs%4L1E5!kN4URSjYWoZwP3TO&A(|H40YfxRcaIF|bRvIj81Vwjpy9#uXd5yt
zrxV4n!Mh&vBL?Tc!8vM3q8;{_VGCWQdt&gSFT0K#Hq%X{2?L9uosETjRPHuj+KK^k
zG47<0%08pgAw}(e<9f;kay9n7gIYIZfH%<Gjek(~orlr?Lm2F7{DIsdUdF^oRC*gf
zrJusbs9guN1IA+=sPr|?CD*Q>antLl^f!J%Nw5LNDDn^m8a@BOFb5fbzKAXb8`n@c
zJjD1VmoDLi8mq}8chJ~J=b|v9`xr{$#)y+3hm4oTAs=D1{{+Fq#t{nyB8~PWs5oLA
zSr3I##`u-6H`+L39mHddRcm2dtg(tBvT?@ki_jKtEbYNhm|%SC4p0(}VV|M$sB!NN
z^1mb*3n;hrnDMC{XiPTp4?*y_(VsGsQjDQ=<~d<}g&bU|#z`4qNjDbLMlQpcMn33F
z<9`h(Wf@PC+1W<VJ+Lsx=$8zXQ^tWA5Xd!tJPV~fWB0!R%Qv3<76Jvv?<Udy^R)4^
z6bwy~(Ms=Fu`zWJq{OHihfU{<cblN1%;=v1mU3erJ@OSs?_tPaG@d69V5M;q9jmSw
zqsfPL)tF6bKi7<_UIVEywir-($5>6Xd#&*uN?5Bip00-6U85H{J{<MNg!S|S7(*x(
zzQMSk;vS909u4H1j5a!hHyh(<x@$2${XSS)jW6m!+KfM(0ZY5Fnyy3MH@dfhbQsT-
zpsmxmoIc|7!02@c;$6mz6g_!p{Id@N-Nv2$P~T&$pukYC!?=aAyZVfwlp5P_%v}ta
z0i)|Bus$;W+Jef*Mw=QigT}g2NQ@dAXqF!{W}XGh6Qh#^_Kq8OP)fpt@njYRoK4SD
zPQY$cN-^5@m<EGk(|%JTEk~}Vf#r~MGeyu#<!*9#UIX<ot$G#Mo~HLH!_LbjrxTyI
zseKbF519Nu0r53u^rF(w6nzH2ufJ*H7+?ZSRvyFyO)KcqUXUsD5Htmw9-jqEi0P|0
z(H3g@XCp|MshN_c!cE1=u<($njZO;@raTAbmL4{}d=DdZ#Pk$-+oDWg(eWnQw1$qD
zv8GRw(6u;I8O1H*P4Cm<mS{TX4w$2+^nDnaB-2~uJU(U$p(M#<Q`UWyPM9LzK`GTV
zw+motCKXMSCrw>yRHmEmE5VXsieF3lFPWyM;{eSvoxTs&Y*R!xO1Y-I2J|q`w4f2J
z`KCp4z*%6L_kaJ5sqZK%3r)^+>ONyy`7t_CWO`;5u!~J|$**2w3Z?H+oHZ?KL(fW0
zH<%DOXA;nIUuGIZ=E;<D)9PmW_lM_AHRL(DU}94*DomT#0PT|L1O=8Zn_`ZETro{u
zgvzU?<tE5qGyOtoFxO2Q^77p<CFG*=rfFCQ@mnU<Dj0g(^kNlAmFeHD;H)+UW~1$n
z>EKeBR%<GwC%4YzyPfjS?wXRH2TZ*w?HG9OnLchrslj9sfv3@Qpbq9YnZ)~HVYBI`
z7@As4t=*_>HNBk&mNwJ<Sje@T7;k~xH|^Vj$_^8Y{E(d{AIdy=VCs)RTbJoS3JN|n
zW&6UWZd1e&5J#VhSq0i}`jgUp2TY3spnlMFkxuPHCc!QAV%U_i1Z2b%mjg0tN`3=v
zW2Pz@<R(n~oxpZB$9{&k-DYG9VLxU5U^6OR%-5qZc>BywWXyhZ2t8J==0pjsa5K-O
zD6zZ4yt)lA9_AnafP|+xhZYMjb2jY`z0JC*0QEIT+(D(Ed3OgS{LNw}NPxNIF{}tQ
zN5`WSWPZ~Ilwfnf=TI18-b2q^sQFbl=sjp&LMO~Hvzlh<aC7z^upBbSR>O)2v*QOp
zU>`QOb0HsT{%{E6e8lWK0}@eYWgFB-n^`RMDaO2hEl7enk}_5j&BK(Qc+}k83zj7F
z3i6#DGYd)~o@^c<m&I}OU*}MnVm|a9<W87x27{!UpGg5rn)$V2$elD_bld}4x;euW
z3Ny@^cR(`Ds_7tE=F;Qf$u_Tk5534Sd(-v!Q|5;hmCH3}(G`|F^9I^p<(q5CUt3^)
ziFOvJ%^@L>D>V1ehi}f9S7bn8k=ZCj?~Bcy)6vfoa}XV5&YI)k|Ha#3zC%ZebLJ_O
zvQlRLoBmxvxp~<KP<Y-fd>$RWV2-H)sW30+gY%+!JMB*@&Gq?Eamk!QXSB=amkL0x
zn7^c@{i@kaQ_3~7FNIXDo4=s{L3hLKP1DUybM4D8=9W3;0>$5No39k2SY_^@s6w?l
znL>;;=4`U`j(IcX?$??((nM2dew*BLcg^!CYqs8;vKK1unHSM5!Ul5{B`r0YQz%H*
zWKN+kB($1;rWA}e^R~HYYd8PB36=NF&(jmwVa|Mw{+CXtIq57wADCHhqrY9|YZT3R
zXcpf>N4w3-$vN3$UT#C5dd<^l_3txZpaigfv+^xe4w$Pb&^c(HH6NTq=Gkp%8#WJ<
zOKQYClhluz-=m}HnE7>@x}TWm1;Chbb1L04bxfFFoeiU$Ers+m@3vg}3?sD1l79j`
zdo7=Mq2yw*o`RsOW$}BcbhBuqAmDCEr2cwXX3+7*)AFAXEMAsl99ZFP382lAkLB<;
zC>^joL+4Ik%L`)I<Y#G^4MqNzY<hA79F{fn0TXD+qjxOGvRMtDV9Qo=4~AHr^<WLP
zblpVTLCZ@t3xrwTC1*jn<@Xn$@Q|f~_J|Rd0@`yOwrrdYuqexn<7kVv6w^!^V`-iS
zuvp7K7r_!|$?w2$#anXxVPS&Bv59uyiIz8c06l71u?Rd#mfLBNKW0g#n@-7=_vm<X
z-10m{BT_7B<RwV89Hi4xnuSSc%afK~+TEpFQuL_Iu+-B4XIic~qb<u)aswpWl4A#E
zjwNm~P)=D!&cUW!%Mk|?3JWZY2Vm)Gi`O;O7Fv90)Qc@^l^`XSpUIbX*0NfMj+R=)
zZBTK}qIeIbGE3k8_eGZXL&0+1(o8O`3zm1!K~sh0LlekF%S&_6R%u!EI>0Vj-loIz
zWs8w~23IWQ3AFxQwKTZH;A<8s3+k_1+&2LGhUL#$XuD~VzKXV6meeSq-L`zt379I2
z(*m?rTcVa=fNCs<-+_ud7Sng=OReR{dBCo-OrL<<UCY!hu(#flyB&J(Sp-pNYq0c?
zYpBsOe;xfVohHjyjc9DP^tynwSe8&uc$-Dbg<!iyM6QSXmKs`JIxOR@P|;}_r5)G<
z%K(M{yDYJlsC;PYlfe3JOTb^K?6EwW3%Op)&#%GWKFbtJrR}#&7Jv*`-X!wKG8vIR
z$CSsGHp)gFv^10Je#jC%iqf#fPUp@Mi_dMqj9SKe0Xk-J7*P4d(nP_OamyrnEGH}`
z0StAv3Ib5M+bVYj=N_w>ev!RaC9T3P)}o7m-e(Q!#gOc`PG5|Ex>|St1{Q~#H7OgQ
z?$(jRD0)~kUIdS)^;6nTdRZ6HrqtVdG62NKIx`<E2dw+)f%3JwP@Klk>Rp32f9nkL
z_Xb$!QUET{%03FrAnO`(ssvkI{zYYom2m<Bq1FeK*?Q3G5{Ta*%whE)w{f_&ItHCN
zWbJH)V1#upC6^tx&ZO{Gq;=jtupY4vV7{6XWv$x_^P{czDVZR~I+qKUSZl+dAaT|q
z`YuJhb$K&56RgWA%PP^j@kd}DwdPU8J;|C!KjATJ>}^ygTOB2|R35hqz5!^8wZj5(
z!df~6m{jXUH?*Z$XNF@CPg)(npe^0Ha~RkeR$tm>Wm{7j;LNdB4FUU<br$&?a;=rA
z5XiGmzYl?YYtwx6rNGLi!9Q)?_$ew2tqpXnIb&^fkYk|8TI&pJimf}>qEup?Ok2&f
zRyOTsORZm1X3;t8&>_f|S=W;rr`$S|qI&18UsI^yf>qxR&I)V%YS?tq`bjuQrF8+F
zNiSIg$(MWCy7O6}T(RDzbIDa}A{*qIwWWmCzw6e8o@l&bHPb?J)4J4z%3Ic3l-+gP
zT3Z2yRo3~GvsG;^rx&-zx*{5bc*lBp6qU7Br(l%otoh_PxodralAh|V19Dh+&w7BO
z2@O^r3x+mY8+~C@ll8zhU^ZI|c98$2#rn>1@U&Wk>15Dm{mUJV?bZ+fzgAhliGoCj
zRh$8qPV4>u0Q11A&q1lnx{{)D53Q%SVDP)G+b+T09_xuo_(giHOX(@=v+kXRQonUl
zGD-v1NJ?*dWR0Lu>SJrleainFv}W+ory=XEm%%e^4WxM3i1nxYFlN;1LKktyteq7g
zPpq{op<>+n3{6)P)-TBu?rf__fEBxKA2VRn9@~SRXxnQO)0V)+=1IF)SDQW?EN-?@
znl#;QHCou~VH@{`6%J2Z023y9+5Vk}+5@%_U&#B~w$XIyXIuXr+5&Cceu7Owwin(9
zXt3?i>!=K|r5Qm&Z9`iDde9cO1#Mxrgjdj)a9h+$7<0%bpAQmY8+!!K!#3`}V2QM~
zQW9*m?I6YbV;r_$+`toSn@6dhaW-olO7S*s7K}--?O=f?$!4d6)G^zcrGQDcZTb{#
zCv4O2qcYWYq#30&o9FMq&afqSK|Irz_%6V*Y=@G;l5JZ_`|TXtALQ>nWt*VjcCM}4
z50!Z~M<?ZF<=ZZjTcg0Xly3Z;wyhCi5DINSt${?b?G<ujmDnDiM@P@vGL}G~%(mz^
zkaFAR+aTv{FOg@s!uDbfKrh-3?1$b;8^00amu&m!vgc*nWODypvE|aVbJaFZC)8^;
zg<~@4b=#;J!*;`VU5wIATayh|+_p{m2|r$yZSVV#sJ6+aK&!DK#{^HlO-qR+wYK?>
zAXjI5?qihh+L%8=px(B44SIObRyPfmO|~-|p}yIsxrPq5*q(`pg{`)o^aQrqmQJGh
zd%NugdRIDZ{<O2`v<0U_{(<dT+Prkx&eGMlhc>+lmEE>JKbY2I>!&-Ty|$kMQR=g0
z(R0;ryLuDG4A}DHP<mvO{0^4KHU>G025nExM`_6R66LRq*nXl@^Qf(}WBM{Y-L`=y
z2tKh@`Jr~)CYcA@CTwZHK*HIsdIvV`w$BLpum-oqKBDZseRlunQMunf?JW>j`&l|I
zxY?H`p%b3=&uG5zvL}83E4=OI|9htFS+tGxv$r3FB7eIVoxua_eKb7>+AmSOGRW?1
zM=8|)!6dL8v`;pp6lO0ZUq!h6>;P;zWWVM}Kx2em{tm|Cu>G~&;EA+vGDGhXd*m_b
zjk5nn$$QcE(?zf;#;*AaB-Vc68FVSmo)ri2c>6z7ftFwoq6ErBdtw~gj@p@-086%O
zDb#)39-D%JO|ifIC&&qVvKpAF_LTpBJSEM3tP{ly`@n9DWv2Z}31G79rF4(rls$nK
zzFhlToiHZPE}093`Sy*J{#IZw5kkdjySo*jh4wWoAb!SPZUk77{qGD|QEXp+5N#!P
zbtp<_?KjBPSZXhFhWI)AqIUXtN}2sy7ZjG;e}4%o&f9rmkiTG$6rxWR_Oc;VUbKJx
z3$QEg-g=;2va^2y+GV@=9iUyY?`;F;Rr@140bR2<R-ts={tO*rZ`n`M=KHq&PA~dW
zWnV>(xN7^Hov5s_f9y$L>AYi~6M!Dp+8<@XiaI-+JWO}(2~I$(w|`H=ea~J<cfcC#
zKmUQsM!R1PR5aQDZih|H_B6U{(_;UYW{+08_zQ5h*$3!Wdb>Tp9HsmA_$%l{hy8~a
z(Ctq9Z@n0`2X^F%Vz%tEe@o7!hxWHJz}jtJF$2c**w<6EsLy`;IkffLzq<q00sFKc
z0Q1QHTo%Y<do~?S2kkNa=+lsWa4iIe?HlN&8nwUiC&-xHP8+``_HUnsz_|T23b0Jr
z*G`2ZXD9I&sNC&v3VaiSdz~6-`fzb-$w%Wprxk9nV!u-sjf|_)dJ5rsIC+Gi<mnXn
zCpf*Frc%0*w^JOY$@@5I6&QpAPK!sN(ATNv0oweW=4?fqztax#iw8KB>_latQ^FEx
z2y&X92Fze5$M1gwG{k8M<@bg<IVjukpp%mB%7r;Cr)wMGPN^S5;*gV~5{5=N&HMtt
z$YCefe2_?|Ee9cf#3|baHbptzkO4H>>4mo;9^>RrE|yrQmE=K>b1I|hD&FZ~Hc%3r
zW|EIS(dmq196U#zCcO_8Nlp**VB&En9Yt$XoH%>_$I^FzMRh%Id++W7yOf2!Wp^oS
zVyY(o)Tq%Uwj{=`F){X*s4>yl!tSCN;{u}eq5_JIj-V(YP3bC91eB(NN>f3xU_nt7
z<$EXJ|9N~I=bU+G=A6CdoS8XS=uUR-m4HieE{Fh^>U=^2kyFlZsKhM8IgPH|OlRv3
za9PeXv(R_iIam+#XPl={VPLlNPG6YMaTaK^lIy(TTQuf5@1w_hzH_-dRqGZw*Q`Wq
zq4SGmxOmQaD+MslJ7-X!x5!y?2A*DU)>D~8v9sGwNR~J+PXH-(ZW#viWzN6TcC6gF
zmrC*~oOc#LveJ1fMW!w}Ut13NWoL6*BUU-*(O9aTj})S@#yR!_+O5|*OXypAb<U;*
zKwNQF?7=9mItO=P6xW>FDREHmtSrSmH8@YFDA0B1-Bj{*!`Yw8s%|=eeilj_oyX9{
z(&W73A#lykrq>v6i}Q<9z_mKRpi-b)&fV)^=(h8BserdTx2E^Q{dd>7+82m>&en8%
z{=Ty>Rh~R>uBW2Vht8j`gZW3!xwK8_bPl0k?Xh#kY#4mv97g8>o;t^zg3@QsUE?9r
z<t&Z{{JC@J9Kc^V`%yNa+j$Aq%e``**$qIC^AUROzIGlVfu!k;a~-W{dY#M1Lgt-w
zYXh|PIp3jLJ~#b*TKBr^KbQ~KJoJ+yAnB<ebqDyJdJ~<9-lhMOUU6Rf8?@N**3YL6
zu8+Q(zBb^ix1mL_pZ*FhX8rX|`@se1FVF-9>iK7Y2buJTDB%&TpZ6^~ck6$qJ9dxW
zZwzGi>a!?l9inHJV7#IF_&p$DdRtm`9MDg>335>H5e#xj-;bWJhxJ2!AaX>%Y%<^x
z`X`iPkJKOh4mzXs`@_)}t$%+t?8WGra~M*b-ZY6WjClR7Z4f=G5552|67-)>f@q?C
zYzC(LnEqB0`i|>AuEYqF^xBW1?S%eIGvH6^Gh$&rMejppMydMIF(9Y({dJh<G`-Jo
zNT%yYeFJ3~`iar#%hV^*>6$FPE*;!yeYVLRYR>3K4TA1${r|SYnLK^L7|7)7GwGTu
z&>y2h)k1v|9f3KkcRB#zIeiXo7|-h`=m9U%AKQx2U(m~@08p&|;V0NF(M#zRV5$DE
zufUb*Th~DKMSa<i0F>)Xs0gk?|9cT#AC>yAn!sMtpLvDO%lhW6XspspX%AhkS5l#B
zjlQiG_*#AXACRomubB?rSM;mgL9Xi8(Ei|>{!c3OuGc$L1#p9YD&?cE>jQ_t(Hr`~
z|AWq(`V6W_Z`7})E4M|zcRSsGt@;C$Grpy__z;NO`s_B$`W^kVmjJfuf0&Q)w(BFd
zW1jEoi^oIqp8jbn@E!UNs;juKKTpf<2YM&EJRa)%z5;oq*HSR2Q$L-Gv>xkEK7f`d
z`m6M%)TjF9e&C+zEs-9=hi&yv{%C!!UvmV&7y3CZP};4ZU<HFO^%H3@uk^XJMeNa6
zQ@ZuFzK70PzR@oa!C-pz?xhfUtM5l?gm-$cSTy$OJ6KGYo8c|J(%lW?)Bt!GCVvJk
zI}H7QL8GVP6-}3Er@@9cV7m;{D7NZj_<KG?eGMb&t>kBjUW7(}!*MET3NZN6H5+J{
z(F1>j44?F16v2j~OmMpmf6@zckKrR)P3|?M^}<AmA&1Uegc@$xz?m?ECB1(484{>4
zXuo0I3^azD3})Lv4;cLa%f=gq{Ek^aWC+^`a@gQK5$2B=hFt^~Vfb<*fRTpG&!9WX
z@QpJZjW#^b2Nz=~rEqbqq2dDOBF^wXGjQ<+6M1peFqH~95)3AKW+xi@ZG)B*hBX_&
zoiv!-|Am@lgFo#=QVgzX5KT3B55quD8FDYd;WWb!9LAJxkUW9z41=s5T$aJw1tv}#
zf}4OlW0*1<xNO7wbjRfw-p4jjmTQpFlQhq;b|4Jq8#pppV928-P@&;I1!K+{mYBu?
zf6h=tU#~fDnDPTm6d7JlLT8Dgwib=0h7B{}Oqro`D(qGm?CDmiG>oH_>Lo)qUES4&
z*t4)yW0*1ofLg;|516=WI7lTF*9=)?zTWWW000e!*;hcW8x~)J&KrhT4^5D1HrP?#
zvBj`yF|@TBo}U4^Wmrhj)Z2zi`bF*-s?>0_&Co|nzIKD_Z5X_37_b%Op5ZB_$~z1*
zDV2KPFpaX14-6UEnAnGg&ifE~WRTHRb{d+uz|dnu0IeaO7#@wJ@5Vee*iD3s&kUWk
zpz1PsUxBvghKtjo?S<iQZveXut0>^}(lD6Hqh1-dk-;8AXCKIGgDM(7^BY6|Pr&sW
z`kJ8St-+2`i|-5%CqYY};eS7Xb2Hle!>+q=O#(O%<1Qq?OtKxu&!}3-)3`nccrRmk
z2n>1~z2*SuV{E5Go4&>+l=tv6meIL+f1~+3OmKiPn&u+Vc#eWHLB@y|P#SEsq#D58
z#{8+k?J<g!^WAHlNH4_@qqProh8iEbV-muQ+IfJR_8Hew`P_cv50w23Hx|<t^MKKg
zN?i^b_iu#EA*0LpFnHLwhQ3>I#5jvGb`i!R57><~?rMZcl<`U_v_u=Ze3*za>Slt(
z8rM^WX&fZsOuX^mDh%SNae*V?$Bg9*(RbWr+(;ShB;#jP-f_aH+Xkg4jpylFPd47m
zMq{e6dlSr`GP>xXCe8RyIR=w%92^Ic4CBa)fS)#gE(bYdteXgDvW-zq0OS}YN^rTx
zx&_dgXLO?+PQI~^lD!2+|8A%*G@A10_AfHN`7bhMyhcyrVq?DwXe%*xQZ%O2xUL$A
zGNWo2v|Tg`R47nxyg^k?6~<puF^Wo~BNaAWHqM;^Qf2(=6&kCJkLjdRjd5lQ8f%S;
z58&?=;~55xSB+Dyg1cs1YI1?LdSg80LK}=qA8^-={1Z(64P*Q75N$NJ(`Kj1sOo~!
zW~0g;T#M0{?y6SfUthw*TgI)FyS;7fUj?7qjN_<~vE6utGD&xhv#G4(p7B$<bUKX7
z6u{j#+P{Il2gZ*IDe2T>OrhC(Ym7*OOrJ4rC5VShr6Y9jbXm~}ytj+bA|U)+PR#)c
zblFIye334HHDF4PyVTUce2Pnd3Q48Aj6VyJ(=IHn$8ubLUX6j~yR_tCNM~KXrT4)F
zm-Q}aEO%MtMfcwgm+a-}>~IPAFQn}9lIknoxXdYsPdhe$Mc0nk=HE}k(V)#47ho`a
zvsn>H)aDsdc#*hyh%+puZf58dea_~043rgZb{ElDx_Q-bh*WKkwg-1*bL1Zo3EC3H
z!NS2U)5B>07qeyHSm;jO@@PF;Gq-GL!?5$W>|Y8srCWZygubdR!)ZrxeT)7dh}_w-
z<_Waj+tNmFwWnJ?+W-@<w#*m-T<?}26mZSMb>3wR)YtVk-Eje~6Y4OQJ+2F>NIBH?
z1WV>!zw!j!6zeLbjaY(fw*r=uT$>+4G}(1K0Z+MRctAA6bs;@(GF{c}KxDZZDW`wh
zRhk4`o@*C9_3~XSI^a{G>-NWhpLHF*3w`HYhqQv6cl~-5u7o1j{r{x~UE}CbL$T{d
zs)Q&txo)6MTAAw$s>~~Q9YpJl3fEKLqp{L8)fqlra%E`)ciB~>Fm<)-aEc7qxK8*O
zeYLJpq2TIVB`e_JRae(ONM3WjfjqdZ-nH;GL>gRYP!RT(>$jJov(2?;zZnqtbDjx8
zwhlTNMI`*Y!knem<29yaAzWx+X1hV-4QBbLKs7RI5hBfu83(SF2@~K+8}k{x6FQj(
zRMzv7$)<OL8~d^o#D|TcGNwK3uy{&e<Bu3T8qR!>M4#aJ&{hviAH`%+wc5u4w9NeE
zjvjx1l|`GiuOAFS_cxnIK>L`XYw`EkL2l?Brx*>F#@EiqOieg63F^N6vlrw2&h-ge
zz7OmGb|Om!-9L0LMEj(lDPuBu&^2JE%xHzo)FF20ou+ICcDe<v6-+a}55errjO;|y
zES{FSKQd#`G28JyjOwQz+6ep{Oj9=}I2SU%{6@j0xz|2|(s|RDLh1aE9nrg>@fq3|
zN?5ckvY|?e#b)u4Uy?-^&C(^POqVVDnqu?ImwBP(*A+RivcmL|p8hMF;xJpQR;dB_
zJuCp-tDpD5l|LHkk^5&ZMTfWjKqVbJnK#b>*u`illkUabZG(U}bAk$3eVB|~*!5-X
zVxiiPY5fc;{F!1pWD&sZ`tMscj8`~tEzHK#@Z>SG+w?PlPnfUi`T3f0!L=cK!(6l`
zOYGUfAiLP1RA24I%Bb|lo2^_A6F%%$dbsM#4)2B<KUQK*me?XKBm>xMH86OH4W&)Y
zVRqOFkfZDe^c+fHeTKnMA{$RHfn)5mS+xH?&TgP%4oPe>UFRp*oa4}al1-#YK{Bfj
zf=CM6+5+9FtUybgQ>>mc%W3SfJFuJ14*V2cCOd{gPFd`Ct`IrRF0+TS3`rFQT{0zW
zse&d;5=V#7PD@@thcjm+FYeQ6g=|UeR*2?E-q0p0SK>l>oIFYWVyMZN#AU!lfuzI$
zHHDH16eu_=silJKbCNa(s5vj;eg>dO5<UUsf@Gr~#!@UP9|(~WNj)8DE0rW}0#_zk
zIs(crN~)uQE0>J=j`rUbk|swet(5%O1cR3(vnIgOWyxO3j8#d5Ux2Tcg#H9Xjf8y<
z1Fe<R&<40p5_15Su1HqW>B6g$!?R)Hnq<^ckb23f{*Y{tL{n1sy5zTU0NjwA+X=~=
zk|z3)MWf{YR9G-IN&ceyuUWE+4qmoM>ZyvVRdR<e!dsGYboTGIWV{^Yj^rrS+O<hW
zJc5Vql3Q27-IXkm!{9y1W7^SmNV<nZ>3vC;AK(upLG&hjC>gjCeUBt96M^fL{7hd`
zdMxR00C{4P?4|1Rr;<IhVd9yjhl<_0B)ydBeJ(j308d{?9#HvGx8yoSR9;F3CBW`0
z$)AUzyGJsc5^Jv|XA05yMk2MxRJuuLuEJQ{r5TmLrAS}X`K?rGi2*uKNq>w3mnOY9
z5`c86>7zSPlOg@$2GnFqf9gVOmUMJ7?4FjI)9rd$x+n_Ts-(IG0IQ{+mqD^ds=5Sn
zQ~HMLE*ho3RzR{%I({!myEH`&K!^0e0*Ks~Ui<_&FIjL0RC~+pV&IdHjI)8G{<2&X
zz19O{lLOEih&MW%36h!79Ty=}%mw0%>>h1`vSqVcKyqY7bpPhcvde(alQCtmlrP(~
z5GD#_wdo**vPtJ*_pIzdJ-G9-IfLL~k?d~|G+vM`q~fb${3pJEm&kP2X?s~JJNg)Q
z%kW<|!0ttv6$R*<%&yR|o6Q<dK~0O<zG!f*W)6dZzh&l6FQ40HTeTo}%qHIfpv|mw
z82wsiJ}=>6x7h+2`ufalXn*Bq{!<>{?&d95;Dv{I<5<}9GcRtT__M$Hk3nb+FpnPy
zX9CS9&xeU%^N)sNE_a)M^%mS7bKA4vLd<W`e;ycWo<#5CFms+NX!e<h90hmK{D+Mo
zhs+}>n0DBF!!D2*^N>O`rknfHvp&Q8yG<aO=B-q=m}P$S%zxF==H67TnPa~DTXg1{
ze?&E>dFBHq!0&wXnG0aPz<jzRxDxZPX)RW2?nt*onR%lZ02j?oU!$?y{O9}7QfdD2
zX236*r%c1>ubIEc!R>nUd*$F7%u6oAr|af56gs_We&c(<O^xR1v@UKkS1f^=X7eBR
zLU*gVj$+ie%;Qg@@s4@^XsBs3UrkS#yXNu90NgYGvm7G#&5QFu9-6P50?9|_?K=VQ
zG-tH%!o!0372fZ+h<OQIxW#uhXgpxCCKTomTD(W0@k1tyq%AaG7IqO(bHw5(<wzqe
zGTR^;X|ZWDWMVA7z6#y37T$EmB+g<O#p2^FhDzW?g2iY9NTS96K7*EH7LE789k*a-
zKr+d~eLA#cSWFrYFETAA(iwu&7OFfrbH-v|0d!_tm?V_e%(1v$0Ysj~H}nF|w=g84
zv%sQ<3SbK@1bWP#wGds=c;4bQCEtoH*3b&+g2iM5v=v+IrG#y%g)cqB$}Cb|K+8po
zWn<7+VUbRSq?Hy~6#2bmk@!2f4vQId3gy1VXQm5aA6oo<7^8n=@h=6CJ1z1nK^|ND
zL9e=}7KV!eKC}3{0+P=yHqk@ug~cd}Aic8~P4B2ai}4o$cawKoK+;_vl?P`$<dzh>
z+#w%s2Q8lRhuh)WPI($Vba%;*ccafso;aJrjo$K~ss1lm{_ASU?3O?2gzmlaNv!~e
z$g8N1CrrMJK0L5b9!?wCWVzyBSW1z%P^tPUxfiA4(&T>gpe$YPyc1l8+`JhiQ@(><
z;#u-ZR7G)GzPu4Lb4ISiIRRO={IAFK{>zb9&@v`hUU42IPoDJz?&r(<XopiES8M>j
zP+pEjob0UpA${ZOoczyR`YGgJ(oV8SzT6EW7vu?}p}Saq?hyJ)<O3*HTPhEtSYVla
z<qAk%l%H7+$#VJm86Xw%si+Dt$u7x<HbCaGeC}HeyGkx3z|(4Z4Hbgd$h#?sSSt_O
zg~mELr-kGd`M_&vyeeND1X3?QzX*~I@^IQCUzd;Wh20zS>r_l}Q@#z!Rav8)dk^ND
z<Y(xNR<qoJu7nnOeKv5WR{6;tXuTzWNmF`TUL(g(aYw#!7D$`ikqQvn<-40;>8`w(
z7J&EUC7saLAzwQeCUz_S>Vs>06!xD3a6sW*38e=W?X)gBr1+Y)=!X@}uRtOcHQzv4
zq#}^^4bh5$zk$S<6oae)j8#llz|%Oz?yYD&su(d7Y7!KGya(NhiXnf198(Ng0i{Wb
zNEP}{DmK$c<C7IJ&Cs2#h@+z19L3|o@F`DmpRT8Tg>DUW7AxYZWaqM?I}luzf~O68
zwW8#|kdealg$+7u6^oq!tW#7cL)#Ta_bE)tRmF{B4Evg*AsTk;6?bS~c}o#|6Xdqy
zDs4^fD1M=W>Nds3buiejXrlMQU4<P3OZOB{ufpvP#Y`WlexT6KLE}S(jECw+3fn<2
z)T!8NqBrJag@l5SPZVXlVeqNq!7_9{Q+!1S)4LR@bolPMV(eb%exY!oclt}kUzF>7
zrI73cyhrglEeBsKtV*EejpDaoL3$PSrvZPfi1!8ePO)+=xIV?9#Zc{Lx!4M>xmyaK
z(Ou<Xd6TvsJ1j5%4$jlEh(4aV)3Wv$CTf?Z?l|yXmPcdZzOSY3B@FsmPNCI<zvUs?
zbp=|^a0M4+`Mwga1zUC>LgQ}BzT?oc$8!EtsNQRtI|E#ZWhkBdI&3+Lq7Fwae>y_d
zDiN0H5kN#*en3y#Xv;_R!Gaje@$}orTCV#UT&v}Kx8eRv%dLZ<&CTlUa!9&cO^$>?
z53Ba$<h|8}Hi&pyttp11JFSk)0M5s%gmz=TR?bV|p`TUwQt0%z%J+n1pw(a2bpHie
z`BRQ|x0MHd6=08*J{&S(R+)6FYoFDXG3eWGwe~N#A8z$GJ+=;7*)4|dLsqkXgr&n)
z5hKxe#Ol>303xlX9R?uEs>2c_+UojP=!~&C_8R8nth~mdG2UvM36e*xa%kUeO0b$c
z6!etUQF>aZSy>mue7aQ|1^6?pHqy&2(`ug%z$~l&ROEBoD(D$VwpAaM3guXNQ?fAM
z>fLzY3a#G!1j(~jZEIk++A5vOx@)XfbC9gHdOjC@byhRV!CkTX%K$A`O;+mhXuW2&
zjvhNLR(EL;-fCt45S_QIdjEmwZ7VCP@@})*_!|b=VHH#la^Fh41<40i$tf`Z(8@dv
zB9E<xQNZkp)s_+HdunC&K7OWWR-qqYEZtT=P&nzO)sL2td}UQ!0Si4=CS4gkeQotF
z4VK<m)mX!eUaJ{YN&40*iZ&Jj*3YTRG|>9b2fznem%auGw*K-vH14+Uyalqy+L#aA
zUh7Y2=M`f83EdT;)~zb24zu1d2+H<ZcN74(-+BdICE?bevJg37eZiChdeD0Nbci0Z
z-t`ZBJ7OK%4$%nf75zXWtryY@H_CcG?eU_m51of(jP?E^j4;;v-A#~q>*8um!cpth
zbdMxh&vl2EMC%7yG#<BJ^fRU_$$Ba+h)!7l^bgFRwBGP7NV4_K3l#rKvF=B8zp2&(
z=+iN$tXaySq*>2>1-t3i$J>F=w4Rp$;%&3<9Egw2KXW1JYjbWOeA;6(e=F=Bu(>y!
z#$vOX>IM(l$Y=+1*ybE9=OS#j`oPgh8}2n4qio!&U?JM(@?R3%e=#<>6hMx(c}nG>
zCu};dz^4owxhqJfjXD~LESp?<V4Su|`V?x)ZH`iyv%;o(0@PI6d`yeWD>gP1@w#e*
zKnkuWn~PNTQEwxqP-KHmh5(W4HrwOC-LP>#1P^c86g;5#SEEfUZC{&gdg;48%{D)c
zg%>S0C;`HSXp`_0+`nbBWCh3_o5>WKYqPmdyOegD<M~i?*CvRf;P-4EQey6zO==qY
zx@;yjqwl$mBoL0iuz9}^I=gMGXMlTY^OX#PcxBT;x1p)WW}pLFU)y-60{F(p_Di((
z+I&kPhqpEt=_48MYy`UI+>})k0Ns@_e?i1U>DeDjcPNk2`@~bZ^IMReO7~IlVwZA)
z0i2gI{clKmE92CF`zXI_0Kiu{cO@GAl=>erzy2oWv=W#PP!6C9#X#jJlx7c7)*V1&
zuyQO->2BpZ${X)dE{#CrUgf<+{1l<eJ^!tXlyw^*vQIgV%Dna~XVcp-TxrXp@qn_b
z0W)(@IlmX&A!VNu1`jK@x5NAq<#qZ>OQh0dSqnBw`EU_rqLqmhnu$@i6rnR#Id>-d
z;*_bQ0E}1uO&Q3e%B_hok*Hky9R_nunMKEIk1O-0VDgfb$&@QOp)8GumXk`0ztEVh
zeD6DWk)j+N1)ZtN&~S*HQrfMDNSgAvX&_qDmFBlFrcCAVXAsR&y3t99)5<UZ1^$dO
zB@&2i<@v!dpQC*FC%9bY2wH6ADMwMEeX&y61#KnDL-PSBReI7lE6S95O4ipXTLK_b
ztGq!+#Ojpa|AxjZ%0IH9?5gs_J`*fmQ!Y9OyY<TVyD+8(<=8VoTvuulo|D~B?x%{Q
zo62#t#cWh&(l((<xtIb?%}N(HXlqeMhXc^6ygn8px0O>jpz)6KA?1eJl%x94*RCAm
z1;AZptsO+}DJRm)r9&ALO!wb?Wf=vb9w=MsGI^+!d<(=QrT2Si>{NR6N8@8<t``tb
zl=0W$OqbG~0))?%&SmI(q2$g3(5)O>3Gz~DvlAk(lv%W5>{0IY!a!dubErtp-In<W
zjUKjTbjoOl?VR0||M9fF`Zvb3%hrn)A6~YTn!$P7j-Zv4kL^SH!jP}6yF2>)Y*Xmf
z?r+=hF&YDGzo9~_K-+pc4iaR$jUHvews{ov+im+EeW)wJuADxiaLn#KIdmr3eVPm0
zNxP#uIFn*G;9poUow6I44@A1%I@<AN+I0<qrEI%xJVdYBwd4bT%kE>UU%zdqOagbu
z?!q!~ZFW}{0N-xc?^D3<+6B|w<*8k(FPwR1*Zu`0yX|&pL0;K8QlPxY4zEVcg`KFv
z1ii6~X@M8LCc7^v67kmV`;%yWXSa?@ocin@oP;(v)hxQ6-BsSpVbDW0K?Ht>YUWG;
z{8e8ZfbIa5&o@wWP&JdPJP)aQLon<ks$b{{9-+GR03wm9N#nppsdf#7WQ=P6S2PK#
z>N)_DRi^S7*gd1lP6o+V{W>28b5!2LAag-=pdNOMRX6w2)vXG@3w)_6fEJ!*szqZ!
zE~-`?1Fl?k_zZ9rs;BfDRH}xrgWXFi?Q)RIs`eLXtWx#Tg11^VWGu)Hl}M%PH&q{*
zC^*xo8l#7$Ce>hXAevQkgTb|^Y_GzLR@L@(Ah%R17UZ@n=>>pyRA0ZvnA%j2?tyDp
zt*3JGyQ(i80KccYOo^Wkm9`g_?yDYM2kwFD(<$H{swRwr$RpL4UjyE$+Bk*sua8w#
zO0+&vsc80|s+P{fn4YPgx4^Y7)eDMTK3DDj5o%tjn&@rXt=dVa=3c6XU4zIg)fd(1
z>rwr66_T%2_bCARM)fNN!h2O-HfVgSI=&6&-MEz$cz5SQdNCy)+^ZhS|LovKQfkbT
zlT<?{lykfU-C^9^S<t<os~Z7r;avaa03PDfc>oV{+vtUPgme1^{zh<39`HVr`?UsK
z6!&;LaM9eJ1p2kP1rz{@<r=6=ERJ*d9`h8>Wq$<tQBH?KLz66ln{^+piJT+l(2sH9
zH^Cj}!l{5EiHo2l*a>c&7fhVwF8IJiGS_qlk}2F$DRifDoDANd;uI=)pT_;+3@)8>
zaf6l&Zqg)7S0=ZEw!K-Lb$@6%&H1N8@(h>oDH=`L+}c#IIo!do!RB&2)kfuUUyK7j
zpSw@b#{w>*5lRcW>_zB1%PpV;&N*%&MdHqL187}U#JRV?(gkiEg@1~<UJCt{a2x41
zEag&ZNl?axQy%joH@gQzD(B{hf~zob{<O-f<kmF;af#bVIsePtFW!);;^OJ$R?Rih
z5tkZHIT|9h+-tgF>$r=}Fn@(hCc9U;y>@84#{DgWNIe(l26zKE&IodyOQf?uH#p;d
z4Dcqmf+E9>+$TpM*~FQuX}rx`WHCnA!r_avxa7H12PnP8F?3+%Hg~cEB6qkO@58k=
z?iuCB+d0(_FnE`%q$S%u?iZ@;@8Iq~gu(mV;WUUm;M^#P^pHDv430kHCeK7;CpWbU
zLwd}uxdCUMa8FG19(&5|r{CZiS4zpdF3v*$_nZ?c#q)xjM_=>k=F<L#GcUQs%TW4?
zdqL+<dN@-6$ZO7w!Z2^Rjz1yU%N5N5{4Ez!0Lgb;&oPX*kJ}stxEufJNDz1a!7Ma-
z@c-LGYoHzcaauQf^09PUXeS?A4u^N~kvqV7@d~O1@#crsL8%Y_oQ_=i@*8Ml;KzSM
zM;QEhpBu0gz^|tYfIz;{8zMn`{Z8}+^UrHxX*WOUzuh2TV1$Qz`9*U08^YV(p#Ru6
zlsEeWCc^mbROhviH(LX3`}wW_cpA=!`C+~e@So9J{2)K}zcVeo{ufv}%q!`ceT28#
z50MDoW*#g>@?~`xOBCNW3nZG?ZH6;3yg;wkSpM=sh{W+J!SEuUkDN<ii$BW8y8)lT
zzdQtOiToTYk2}UoXs>ph?@9ql;zzClIl)h`hZiUL?>>jpWImk!54{xLc@-K{`3GGP
zImLfMtLHR+{TPfeo!9<%8}iHOm6OS@&_E=Mze)$xPV)&Aqcol2)vhp~%?Hv9<?wcg
zU_O^$vK3q&|MB-g<n#BJgDc>JR)ZAscE18}makn2$#cAX1m@{HAF>=nE8_dTh20Ch
zz8hRIA5Ce)5<Y>dX-j!$N02i9Fog^+^5-Ull$-dVNX%sgzllx_RPqlKq4W~}y$6PN
znIA+SJ*(ocCV{KwpK39R8h#ip$!qza2g9{G-lhlUukdRnAXoVn29Rrf&jl!}=Rc)-
z?gqZ12$rt%HAB&NgU{}RmYe*0R2S38o4V*>)WmP20+VKb5Y^bW@M<{_t^B8x!QJBf
z=!d<{+wTMZ4!?y$4{dxVt@_*f-zo5Ummg3CrT6$}1?cPG7yJ*n`@Ab1C3wJ3YKF3h
zyzLwGJ>so8f$QY0n=tCf{MROm^*`ZLU2*9><<$!@v}gP>3Sf5egK35EoVQ7Yniu>x
z^d+WleuM%3zT`g>0eHo?Qc++JA5PcRYrbV7e)~6k?HEY*@~2j#@hzXNgTZ&a!55^D
z{~{AOH$iFzE$)K91-<_~gvk^U-yt*>!f#KZ+6<yQg*?iM>=K62^4Ck4L91wQA*mg@
zeS`&cS^Eksr4jvv`7#X6Ul=?FV+s(?P)SvwFqC$`LBcR9kq8z9E#SL_q1Mp3NBCwC
z0DFaqbjp8+2n=N`LIr<{L5B%LC{(jgaD54~UkD0^rEuX1g&YqEgNq?~P{^cR_aVVO
z0DXsr(-a&zA(YZ#qmx4SbXZCju6zxV6oH{QajGD+q4AUuPWMQfP)fV)bm937+W%z;
z<7hdVDJ*t@r&&VpS@?EZm_|FVGeT(`>}CsZsRkuSI9dj!xq=I&V)F#gE&%d{eH2|R
z5C*703WZ;H0B}~AL1ohCgcoTLIWKsGfh!WqYQS9()>4UWv9Okw)TR>Q4Q+2qg)8&m
zVwsRL9^6GC{zI537kql4twK2Q6M&V%`Xx|vNw_#0mM#m;bdOXC+v#;yEgb$0uGI*C
zMS`mpzNSjfI-&G$Sh^z2pxDe+p`6ZGT@!j~7g;Y1T?jyfNeE1aiR;3PM6})za?fGd
zHw6cZq&EsE<ipJ&bVwoEEPVJaNQ*Gd2c%VCLSW*S@FD`ExGjV)hii9)MS3V}6BJ)T
zq+KYdlE}M)6aB|1_k>Y%p{zs5q>nG$7o;_4d?1*-djNbWoEKp5k+7JKI(G_<o8ZM`
z!66$mPXyBk7}HasEgX%{ge^tjx&(nfg7REYMS*)EG@J(4Eu3Bok(a{Ld(iSq=p734
zJ;KKV489hcSxmwkA(#&D^a|Y{K;*5^W6A@4C(Qi}mimOPL2$-Rv|fgxxr<k_!Fh-l
zw5r@8{<000JjFGwu(VVBi;m>%68A2EZZ9!~_Ws`Dn0A=(5to($;49AR2e_ZOITNb=
z#dCB42Z){XArdGm>2)6@whp5FU$E#v54hdpoo;Y@#1-_*>=j4Q;v+;XdX2_V@$nw`
z6eecpK<Pe_*MQqEUZR+8xcECAPdXq@orcjL6bH)S;UO`$5t4_+uhL=gh<K0AMMQ{m
z=0GG;w4vxkl=$`%)!#;o@gZ<HM%=O!Uc`#u&^|0qw52k_c=1LAxTE6aE$B-Sm;VlY
zqWD{X*gYoh_XRmFc4R^_NnB62$_epSD3qNP3wUtJ;)k?|P7#+;Dm7Ki`v%UO5`UZq
zK$;lg#Nhr*7e~|mkRg^2LTjd&Lf2fD=vIQp)8dFK0MCeD(iysJaS4U)bHoj_Fv%5%
z&~rUcjHX%77xOXzC=k>70525JQyk>1$bJa;IkEdkG@ci~H~_9lbP^$XK|Cu*qp4V2
zHX2GxM6VzWtyIh=-DTqXc+C1m@eia(WaZ*$s`981&(jO2Qp|V>gO|iMs?518Zn^}?
zDzWG}`l`hZFTvG_aU)^AR{VV?NS#=-6c(<C;k16dDt@U&<27-y1)QljiKEuTV1wvP
z%a!ZmwjMZjL#!JL(VOBl7l<~B3Yys_aWEaNX%>H!0@xyc_5?~>#S+S&-xAk%LCbCN
ze{{0vju_PpFWSVjv<++*9ri-xuIL#D3-`pA6!z^9W2i#vzG#Z3TDu40(p!*uDDpdi
ze<aqFz<j58k(LCH#i38ZJrRBOfO{(bO3&A4qKwucUE%@SU_TeLrbEjMaU-2#=@u<c
z!R?o#tO49Bah@l*9x;dt=3k4FpMiTLHVlB4Uh$S`2xQ)hGloOvop>M|q)$x#1u|~x
ze<X0xU44nN`5x-?T5vnm7apO{Q$6Hc_!Oc}qWx;9dUFB#!qizK(YH^XL%GoX>QASj
zFI>Hvst*pTwR-?Kr0zZnk;Ce36u3O1{{4M=|3#=5*THV2I(QSfDD@>r;G@+?slq2l
zE#C^iW7S@yG)~<|QP_BOg&WiyRsT2yBtboeg3pQSm$U&proKxHljCY14nI?p`gaQ5
zolrlgCBaFx6IHsTsFyAQAXR;J1D#esrQXyArD<x8F0XWT4=o!q)PGXIHdCE)A3kNN
z1L^&FTCJxv(HZq*ioay5Td3kTM;%66mt1wlC$O8RKDrKl`RbZ4&{v?wmIt?k+LKZR
zXVoVjLFAm;hZ@hT&+n%C_agO56--=Ezdnlb7OVfEGub8TpPFE)R6Y40s3}t?ZGkfv
z)n<<{m~wU9*B}+@_1mDdQf)sG<}az;C^UOn-A7x~Ds@%}NVR%vJQ{1%`BcDKtKL)(
z$vX9xD3B}aR64wBx~gtzfr)GCXVW2CuMR&B(x4trM;WfGe|rFOL%oNRf;ZK*<KR=H
z`T*5lH>pR5LTR&l`^R)UsJA9VX{-9v5%B4jI*CfoZ>tZ`ZvT$j%^l9PsmIbjtX(~~
z6@a_y7inm`XHqkBAk(3KKONfct4G+v(gU@MQWX!?A4~>$q_(^XZJp{(^gw>Bj<5y(
ziFycq9pkCmR0t2BsT=mewJ!CdA2E5))jxS*f?lZY6QHbH9X=V7FV(Lc;o&QFt`+R|
zr~~&y^0nHu-xW&VsEeE+)2sgFV`zJ;9&Ui>JGGkL2Yu?AT8Ox5hDX6ecTMMK;5;-T
zv?$%7nXdxpsTo71i90ptC<3udBO3~5yfjDM(dey7rwR@q&0R`M`)Vp*K&PK(2c^aQ
zHR&d*y9v+?rL<?DCXZg`L7K0rpd(mws1h=}H3!cDzekh00wQ}g@91S7qH&~jK&WQR
z9heW(uyp_I)BJHAWWOevs;$E{ks|;<pou<>IXtM@`aTADNMkb?<gg~#3CfOWjJqjd
z6rnLa0U}ZpN5`O}G&^mfCR$_41u#aluoPUZ#_u5zahj#mz{P7$p>#`jR1-WMT!QA+
z`|v4Iv*u5T9Mdejj7d1I$*15|l4c6+Wlw1C(;D%lX5e#(Bx@3fLUoF!W;NBnq-y?D
z!HZKG>vm{M)0|v^&U8)76F8HhVd%(5re?YoM6xtnx1jN~#<Bt28BNu8kZg^YCk*Cj
z>Z*au)wI>ZnLJI65eD-$GbsyFpqY@0#zM{Bqi8&<sX78f=QMAkY5jRYW6T6wtoe5;
zL`yXT#=~Hl=Jy3~|DvWmAHZ^rFMXA<LbLgE^i^uy=(4<|X`q$gWlex9M5;8!RES!w
znN8Pvji!r|`L&vByU<ssSxqsLE1D^j;qO(=7>bcx)ATNZ7E`@u;VZN@Xgss=+h5lV
z3dUe=XjV>uOrvJ-95gm*QW%IdYrg0QgDslFGeKH4{d1uEmS#`@)ZEt0uEZejXp|1{
zqD}Mn{{U#$s3;V6SJNp4cTY2(l2sj=dde%^*Yx}k@CPQ%l8s;=YNF{o;*T_gmO->r
zBhqW|vF0}m$UM=^szl>6%?LVB(WNP-1>keddsJ5WLi71oz;$az^04$$v!M?DzS2yf
zAErn11#M4WYvgoh@QtQ30_J-)`Z{oLHP?Oy?w!W8x)rT`ns58TlAHF}B&c!M#*W5d
zJhW@?f$Y#;TaG?Y?c^%x-l<(og@L=Yo5w-YOMCk)M7*`uv=;Z#Hhu|%zS@nu(defg
zPv>L(wMqK{2+&Tn1|U#tb`^a=+Maq$bFlWMiOvh`)=qkc);-#GI(olX>pBcBhG=tW
z85^n{*9Z^8wDZhhexJ6O4hZbm-YfwZu6<3Zz607VR8DqK`}Q&5hqM87u^ra#`wk|K
zXsy=4e1x`&66cZHIaD1Ir9CtWT(q`hv<c>8wA@s%vD!+iFO1Ww&%v2^Exr(mdrVuy
zV4@PVOOC*9qE<5s+%fI+OCZO!<6ps2lGe?Hp`Fm?n1h_uE|j4!S^NGw08+G}v}#Y)
z7Q}*_(pJ;yrZnxJ-@*HIZPG~E|7B=h=nQ(MHkT@Vvb0uolbqJ>q+_~gwC{PqnQZOT
zeHdYmc1k96=W2VXz&202xIb|D+P^uBut59ezi2GfPNFsZS?!}@SURU28jHz0ul>^#
zl117y50DF5cRDj)taZ`%!~IvH{eV`ErP@7y7=4-cWgP5Y)LI6^i*oHpg)m>CwWS4Q
zrS>glgf3~dX|Qxz`yOqXs<c^-090$s55u(@?NTbItkqtihjpE{p9KtF(MD5<=Bl=z
z2PCg)SI`$}>$Tb^fSVe$L#c-Py7m#JPi|;ej|X>CTTQ9LM(r#c46R8UNs-oOZPWVz
zwrH2r58J9u8V1Q*+AUAecw1{b6pr4}x($H&Hm&AUOu|#`(rozjO#59d0A1SslplJo
z-Lf9!h4vafNxMzjf=Qq+wPCd4e5L)0_J2LvHFU!Jwf49B=zF7GNEM&GT30IAd8?gD
zyRvuM?~g*w3HxR`>~zw80bR!__GdrGAWqqb(dWL>>_6NGFVgLY=b<sf{$em1Gwr{o
zjo)ee?-GE^wl~G5pf$(-V`s?Z+51s~DBu2L%5WCgJ6X~%YF|e$nX~q{*F)Pm`|y6?
z&fCvA3Q}YrPuKGWd)u!8FR}mnDE*T5iKpO9nf+`EYL?r#ehplO{YE+*QfWW`1K=*%
z*Nz0>vi)ikh0v?)=Tpd}+WsG^jjOR=FaT<5?Hy^QTW5cX5{_5wFO-10YCqKpeqXaU
zQof|#zJRLc8|-DYW4mtuD}|kI*q@}Cy=i~g8G~rFuh<C5Ci_n*7~5>$ya<gg_C6wf
zYO{|BqWkZjeJvd->#*Nu2hscXPYPlFf&DW&O8d~h_6v|l_P6Oh)@g6H2Y|=+ix)!j
zsr@G(LEAI?8+7Wm%YHr8%|Evv{uYfd?B|?<NVomZ@8IuC`z}i~zOv^%=;yUBrwX^%
z_F^i1t@Dlj+#s;M_RmUS;;nrO6-d0ZA1$J>&wj}`sBv?c_!z|9;luaP=izYQ8<uuB
z2s5C~(?RhEeA?;o#WRTPa*%Aq(7YU;eTzPChc%S3^KqD?#vpthnyO*J&!Hs*js6Zl
zAi4IFEWjc07mPR1VHK^2f*kr?12EWOi3^nOaqy=q$-NFI=;ItA4r3|R5bALCSC|NM
z7~6{9Zl8mnFGTh`C@54C?x5Wl?8x$_z-5p;?BGVhz9SBQ42RALhfNe*jC5E=FYzdc
z74)TnXoo+ko+{R1MFJ)$&f)od3^3jyQUu_r!xZ|`PJ+Yq6Y%Aj!+6vS$dVkI)8Xz3
z2RS8nk{#as3X<YbO$n@2hexMj_LM`YiEfTGhd*fZo$heA4kj`kBor^oa`0V)zS9m(
zbZeh+=%x5_w!_a9I?r(k;9x%2f&CI{@*EoJC&+j3pqshC;fHHzEOeM+k3pPuctGKZ
za}EP$L)m!;vwe^(a;P|j#tRPl4z#Q)c341HLW#q+6aY&d>i>Y6GKa?$X(@M@!T?d>
z@P<-tl@7KNxOT~*k7Apb9ZE!)sB);`FbUNT0S#z;?eO*(lzBNWqu{)c<30*%`Z`KI
z(YMdhbs@%bz%h&B@P{3@uc5Gdq+{+!z{fZ`Rl{I{;|!X%M8}|O;Ep*iqy5Zr$LsX2
zNOG*Bhx`f0@X7Gvq~n{*u$1grLs6I%$CvrglIj>j%hywm|IjJ*G{+?d*iCm_OSNSg
zj_qGSXO`n<OMyG>*o7ykNp{YWqs`8F$Iqyw=dz>51Z`E0Oe;jI9b<ll-5N*P6o}M1
zhW`d<>KrX+VrW+!CsSnis$>6~(0$Eu<#E949UWHy*Wl=I7S3FE%xD33!!ew`F>}+=
z>oedQ9sjutT$7_~6dFy<jwu5GY;hbt4NkQ>+GU~hmSYF4kncFYuY&G2$Iu*T+u;=b
z5RINrAJJQXr_;%e!0mFHy%|amIjx)t++n8@%HbSwilN1Ogp-ughmlT&bQ~wj>AU~(
zx=se#7{@w&O{Z1kO-|E`peEVrM=eaGIAuP?cvGF0D$#k$$((k*X-;2J1R~ujz64x`
zliSa5G}CEDFf0`~ZKU*lp;O*Y^qqBD-5;dfshDbpE1aZrK`NapX}f#L>B$plsd8$j
z99xZ3n;j%;olL=w@TSS>pHR5i?DT;4=PgdDlrd;^nzsU$Zadj5gqk}}Q{*7eonBBj
zz1yjFA|zirZEwVsymGp=3BON|(}(mte&ckIuJvB0I}}fN>ok-~8QwWv-v+pwZW={A
z+;zh%A?cyJZJGu*cIcYC(dnsMxe8>bPS=dl@6wt73WvRQGAg$B(H*D<@zt5OVK9EW
zy&u7Cf8Bx>s0q;Rr;KQzF6ldPLAqPCj@zw!a1ii4I^P`h?bTUR;bn+!RXuQ_x<&@d
z!gN<Yr?SR<x)C~zcfT&+cXS@mJ*ANFLEW<1KpfT$jX~cLT{4BK<8{C2(RWn0n+kyw
zb-&UDaZER207#N<g#!k9QumAk0m-`7Jcy*|&e3WiRd?=p7(At$qlC^h-E4Xar0WWE
zX<L(_^P}RwOkLL*kSyKV70`BCcXtgY;f#*8Lt~Ea(>&NM(z(#%`GU^82KZv#b{)Jg
z(Z$fix>RRdhQ>18Gg?+%)V-CWu|oIPVrZ$<4U9zJCEc@g=)0;LNB8YDU3eHRtD1E#
zRKd}r`+#a;TXi*);P)-v(_5H}+qxxR!QdU;vfIG7>8?=eaJ$a=Z>YJeOFstl_jH5R
zfOqJ!>88A|TS`?64|Go(A^A|Z)fHX@_dofB#VGLSlTn*t<kKH0dphVY0@FBF%%s!p
z;mLeR=bv^m<FC<=&-{<xab8Trzu>%?55fWVVG`&i<IDKbkKo6w_(|H&>>yJ?YxxW&
zk4nZenZ2~>&ti%u!MD?lA6+zOn4t&2Wiz9FpfiWj(7QaBxpNW3l*eeK0Om9LMew+Q
zx&8-+U&wrS7KpRV#s5L(9COAG+<9g~3i^teu;l=hGdf(XW_Ov7X*27|&bR~kPPYGt
zFu03d^a_n$>`FRY;mul}2Is?uQoWrod+{p9>BlbGhDLuAduaj?0qjot@4^Dv$|cYp
z#2&K6n1b1vR8q8?U48^!>|tl&nm3DJJI`X+b!;@Y+h)5YZ8YD0lJ5~(GTSZrWD0bL
zNo16iI4D^wD4-jEzDlFw$#2#-K>64eyCE~~M_N5kh%lXo>ba`nFupjk1OELno9Y%_
zp3_C>8W)HbZ)O^u%J5?tI+T^gOsv5yo?}b{{_i*C0|ub`on-VUFxn?6wuD1&(#;Vx
z0%-%)VDFYLpv_Q}`6xP66K%eW@)I%U3KYGWWU=P^D9F~L461|7U1b3s9YHzMco=)3
z9D5m}y-M}B;C9&7QV7Y{wvvj^cH7SXA9U}x?Y9|RgzdD|kc_w8_cOE{wVnGRyhyNZ
zqC|C~ZKE&xj@h=;!uGgr%kLO^l5O*4C^Ma~eX|SrleVM$K$30$-HX{tw{7_YqB*t-
zUyyUQs;SUcX3KAcqgA$(=K$Ye>)QvV*KOmHq2`9|-yFD`w(CED`9|CLr68TQy%axx
zY<smF+!Ncm6jOX^`;R}kXSQcgz+RWh)|NsX&uy<zcJ_s>KUKnZ+m57(e`&kI1u{Lh
z$%kP6wQV;&!rs`9>q29%?Ntg{zqOUng7}?n{X+oyZ0~*u-EMX{xghR#yN*NB!)~`P
zI4`>yqoBpx?j8LUK6cy=;C$^&MX#a8&u&*gu)FOh-3QrYm$nK6-D~Glg`X?L&TtZT
zL+x^!pe@#J=1H1ayCL*`KW6t!6#%JrDg7{rbh|4XFv1+Woev;+(=KoX`Wo#Hk<Mm2
z<6)2%yYQ7Dx9w6k18~PqYoeV}kKL<BxOUuB*EksTSCvnL!2ng{4UlkET7OuIRDC}V
zejioMHAmw~)!1jiXQ;+(fTdj3?VsS&dDR6<>0MNrQT;`=YSu7F)~jmvf@@aQQG~Hw
zH98iC9;vdI!|Zcam>(@R-l(c$Xrj2W7eRcuRvwmoxi)_w{J5XJpvIqjcN4$>Zg2_!
zfn0M1`hvJGR$<nIxh3`Bc5~yY-f|Ducn8kx<wku8w?jDV+vp4B=6wQO7{}7c_HmPI
zfZNYKE2Cp2vD|dJ+vB)NB|yY;4hRLK=%>6LbD6+(${?D^&AtaU$GCr2V}!@KFbyP=
zxWmUmPH?fbayiLuq{w74*Aj`LrEp;sNlN9~w!z>j&V^25q;cC`!;1_qE)0^HobDFg
ze_5O_UHPXu$yjur;re@nWOHWpW<{|N?ap(#AR1^M*YA6%$>(Bd4_Uye|AeJN&gFAR
zp5^lQ!O}VI@?|uh=cWw=u88}0FQ%l5vx>%$u5m%zpt^}G@CKlbQ@#%mO%J(fs-NoO
zw$V|<H{6?P(A~>zpbzT3<<dp~|BhRH0eyYkaM}>N@vrEE8UFl93y1{pTjQZSke~Gp
zM1pvh>hXg4UGJf9H*Y}?yuEw{IU2%u1VULTKa*;!!uZEj2eHq@Bk+dbg4eWyMDd5H
zE-0Gc8woCkKTBVwh~;1XfJRh<+=QBVK0XRw9Ob>oz+eJj@(z;6`1EM>9p~ez1R#mG
z{1WqYf^SQJ`IG!iI@OuXPw0ST3O{EfNGfklnVW3h)NX_E=I|zZ9Ov_Y4}flD<cM74
z-~9|V<$Qb{L@W8vz5(zO|7tL}YyACSaP|C6O8Q^tM<xJ%gRi1H^$zc%gEMV>KCS86
z`A;cqf0zHJ6C(Hc*&!HG2k$}=j{7`gDgk}Ko00j4{GuiRAMxuq0ny1PnZwd!UNIJ4
zJmD|KfqTlYYR7ax<IPP_)5YJV==2Nzi-iDm^G7IO_mU5v0PYpPXdXxpfAkX!@HKy{
z3y!|wGcUtXFTaP*b-d*(i)n%Tj<=^(b07cwQ_Po}&~E{N?!xd`$an~|sDOTl@R}}N
zPhr4$^aTh`AD}T%h-Ux@5>8QWI9SLrK-nIl{5Sg11$j4I3lSE)2S-DNGqg*M7KTs&
zEJhIM?G`JHE}?C8obd7?MB{~?Lr{8DST+t^g76#tqKQJqbpVeErewH(T-Z&so+Qjm
z068IaT!Awu1^YI*mMr{Eo81)QBfJ+;$Z#_PB58v4m(ZCmtZE0BA-K|eHd9zaeObaI
zY;R4dU?^V>;2Gi8F?gCS9JvSIa)c)oF~}7rI-xO7;9}uLzEDe9`vT!_`b7(cl~dv2
zS)o4_!k!cMyocZCvLFqI`6^+x0ev;X#FN0)3jcnL#;d{-`ZmEeVaXeCkA&hFOqZ!s
z$QlItM!4pI&R#)z3+CSnVL!vfJ7LIAXzUZFy941S{wTmvcQKdt10Le!HrU-E+R`i5
zQ~Y5Y4DJ-4P-t+M81W1Gyu{i;Q06Ue8VD^u;wL_U`-&SP!1;@=v<wO`iR%?;4HP@6
zq9#b}|08q<i`|3Kxm*1CB6RN&6DdErSNuzX#t^aYAB-tftfZL<6MgrA+b4eN38nkR
z(n7$)#fsTzJRmyL8H$7AslD(%L2N&a#zb)tMUIb&DNDc|7ft6Wk(wmBt%vRt;^ZN~
zCyPA=u$v<G@4=W-#S7bkKP5I_f){Dx<`7s)7nQWBiX3b{4<kG^crAT;Hf`|JN@(%^
zpXEZBs2{S_3MN{IG!#M0+Yu2IynHvp@faHSjC7~H&Hj-krV{{$kMyKh&cTr%rb1i#
z$iAPUyJ+MDN61_l89Eap6(c!%?A#qWZX&cLjOw{+2~Y87ZDSDr{!8%y+SjcfhQHU(
zw}KZN)c5hX%Nbg%ZJx9n>bE3c0o0Az|0UGAGi}Y_JWR~xNJ#iHTi$~jKPH~44g;7p
zT8)M>m+7Q$7_)d4{5isW9|bKD%=p(da>m~beF=<-qI`+WQYwKu#w`C8Q+1sA;Y;XD
zV=Mz`I7|p#8oA6zzk|zT_Rvk9&#Y^}92GF8;}nrAV_H6g%ta>dI+T_(7n@<Cf|-5+
zeOH-<pF!I-rdELosAnE~!9)YIzz>bBOe*DaZZSJ&fZS%rQ0VUtQ#u?YY-3ufq`jTF
zL8-dC%+_}F-DB?c!EOgL<2d@BGU=w5F!78zOSgU(W1z^`bLM&m@GqGCDsXR^SM>aQ
z$GkTM6V%73PQnW}wv=AW?yP4m8a>!=Z$kGDcIGdT^kl<G%T6|lHe0*c=d?HVVwI5)
z@n#=Vw#bJa<AVYEvOD8w|LMopPll*JJBtcW1K5!d;cy^pHw+|*?F<D8W>?V@Z#TPW
zD7ZcBhqPkY%Nj&z3t>H|EIE`7P(UP%4WYV$eeAMz=-bb(p9c%!?3?j$^Z@%A)wv&J
zw}rwde0X9yem;D8B96jON7&ax0E}nx6vbnZjVwZAGFwK^lN5Gg3J|HRSvN#Zu^G{5
z%w~r^LSqj55d}1I*@&sooyQJe1H1X`z@2~>vjbM5uY_G249QZ~+7VnCd)@%}MfUq2
z>G@aAPFai23U&+~1HQp}JOS_~>qptDMz(G#`kL7B(*bN{S3Lmm4!h=Cm}q02{V}w5
zHgYJgguCpTU+DK`UwsAdJ6MrkF!xz!8}vP3V=2|=CXsFhz)PZ_a9N;a?)$K33YC2F
zJz5V*eqmuSMpC!}CXP#XQMqoCWa3ef6Oz_X;KfPFqRHTrB?DbB`6-h7FVL7PF>8j2
zJW1$V7|fT<{RplVNX#g}Rwzl(qVKHat{u#umuwjc3q_KJ6s5Qzsi9x1*d&o-7mn{=
z+@tJIsU)uvczm(q61=z}nK%GyZb_EyMqh_ynI4T#B>5!(yp()t2Ho!@4;BHiOIo=H
zv*sn;+J`=rL{A0hBV9|!=zXOdX`k*Vy(+?Af9cez;Py*5zJ|ZyQqy#La2${>c@8xP
zrJI(49Fhi84(YJ;hgpz0A}w7F_amk8^n{3#o~OK6v~(erMaM|zQI&tJ^wq!Ui<1V~
z(iJ4Nq9TM-(jm6+_l&fjN^=UOw|;<6CDK2l0ly@*`Vcy=NJpFKBEKm;Ap_#JbXzZ4
zA4pBska;NWx(UQ1X?`cTPAN;fuE)}LXAJv^G?Bi-^;GJj2jH1>+#JB)NmFOSi#};f
z4<y}WPifQdE}KWMRS$d|53cQyX%YeOlucX%ojYa2lc;Rn3;(+gI=yA(^hWcM1;s&|
zuPl}-&-`RZUIO7SOWlsX09n)-m<YsYZNTl5joSs0{j%4k;KF4oQP6TgW+Z<P%3cT3
zRLWwvfgF}?jDci?Y!#JNM#_w9pe0InaMyojU9ydI=q5%sY%83Jl})3A#&NQAO2VF$
z-KLWZ$uh$La4E7~<I$HYn`;4Wr({i*AZhq~CrqTvzDR?X3|VRv{LPY09EnLdE%T#o
z<r!Hh<(IN$qg!A%N0v4PGm|S@?n}pd@?<H$qBUQ3ViVMq$R_o{V5zK>ax!HyStATy
zl#THMDVLdk1F67=8DY0lR$dR0OR~ds<nFR;?r6ZPWr<DTYGjg+V4_x*T>`i3WW%4p
z!WG$w^Wd(^a_CIeHCg*q_-m?{jiF3SgG~Pybhpb!Q^Mu0Y|9tWc2A~w4ABl*Zx#k~
zUzSTL^9Qo`Eus67Y!Kl)W!pj^`B?Vf_o<)Ao<^bZsqA14B%jIZPr`1W?CB0Px|v0L
z!ZmlZgGGRQn0+4v)jLdPL$;vP(`?*mnAmBS5e65%%=q^q>TOo>47z>H4t)pC*X#@W
zCWoJyd>EAaoBg{9T!2{@?R*cIm0Cc{L9?y2a5!WZOAE@wW}E0XJYsg1vM&*4t}9?L
z(o9Pk&M32~0q`)!%=B$ObjO-aWWmOnJ#&G!c(bB8uzS?3AqphH%)A5hoM=|O7r<j?
z8ww$E&a7+}e%SM7i#GsQVYaRS-Zz=mccQV`YyhoB-kQy+gWUvk`*>(6GJm)lhAx=T
z4MgKj^L15dY&KtM3IzVX`8WOH+f#F^EC64bN2Wttk9i@5oqR0TUIN0`qVFk27-I2b
z8q7ynOryA5sznJE8su6mr{aeqi()kzZ(2lLg`-a`N)AJ(m;5J6%7@7FXn_zdS6RY~
z6!{GbsAtIIw3PoSlkcY`=ta416o7t;Y+E!2Do$?!7o;dK2N$deq>bzz#k9fjcdz0}
z4*EhBU#|o%OfjV!ZXZx2{tL;2igh}O98%bJLga`-6^5TFLQ(GkgE5Nd!Qf&Qg*xEk
z6iLB!tS3PctN{MFB6~GDPbvy%Cz-0)7X*jX6w-O<OIQ46KwqXJ;s8u!DTZ{T@3i7L
z1-Q>BJn0rMSFG(1QmOb~H721-G2I4zwTi|JSh}Jp`T;&&Qw%Y|iw1>q8kF5sJj6w6
zlC>&SPaxxA`6(4md0H;I2yU09Glk&2EkAIEGl7<CjKBw5es~Hb#IkV+@L`typJPhG
zEx(|HVTUXaJg4O#{s{Ul_<ODw<&EaG{RD^SucC9x3nE6~-wQ8M_-Ro-)x0k58AkiB
zB?G9|Zs|j+msqy`AUc*Ot%TWM?dkmMZ!>5ovZCfa{Jk=I5KOK*l8%x7zCek;|EQ*%
zpz*<0jMk->W^QxDUTE0j6o`MjR!oG>fAqB2`uFHC{Cj(#IrNws_4v0t!}ghg^I!&2
zRs9a8%Mr)`W^*094P?eNqA`eBF&JDh6MYaQoS8lxA_o}RLTEq8Or?B5GP8Uuyvky<
z6pb%n{wTtjN|>#*3ck#22&4TyP0RRC@OK1Tdkv-|*~^8{7sZ-BqJx9c?EHf;7Q?z<
zho=eb_GxHLWJl2@f0CVb9X6BM>_TuU>^58UWw7UD;4;}LO3G)kM}0s}vwy4yJdd^5
z4M08{Fc2mR*eHs$6|uhSVg3T!OI23I?Efx7vYb6)@`Bw8_8`@oRkI=6AydQ7D}w8_
ztPL%i>e#(JL>kz8R4I3zy&ekg23tyXm@RC$6kIFY`XPRbTWmK4U2d~o#em;o$6kQl
z4z`RUq4(Lzdob+B?21A(K4&k70`P*ZPcZ@C&3;5z%o|qt7(h44C3>=T$yI@v#}|s5
z$VmM+f$y02j{@AsET-9UV}GXujqdCkPmIKattRXawlNddJlXUFke%!SCHi);3n^^t
z#X1`>AKt7RefYqK9rWK@*2K=DsHPulYJxU@_RS<14Pa-`3o?-1`4k3&*rhs%gtO~=
z;Oqf*a60-9vVGa;JIbzm085GNwub);bqfP&A3Sf?63EWKGZz*Y*t7z^@RAh1ELun#
z_{D3z;KGvrw<-Uy^e2i;EZe^tJ}w_s0Byfc-wwcUt3HQED?X={&C0?mC|zami}v4@
z<&a<f6NOs-SosB<ShLO(s15tRg)#kK%h0}gGrbzOlng?<C)0rA3rK7@>_*!zX5MTX
z6LW*Ubsfx@mR3W4H}gIZkM=Ob2LN%9c_hay9AX0R!sWw^c_CbgV7~nujnT|cWG0Te
zp#(`_O1jZ_ocWyA-Y1#6Ct>L_V@HqNDrPNJUQ{#tYGJ8{+4>xIYnjaT;OZIGIKUg3
z!6qs<xW!yL0CJ!C+YFsAn7erZzGgaZK;|v8WeBwOF_B}T+nx3K5NaaWGeKy~WOYbz
z{QtXaEj?h*FrN$uCYzbH9&Y6@hx?!}m#NmEFOOM9b%yy&rW~UxU<O1$QK5->NmXrS
zOgm+fE;5^nfiGul>Efthk}2I)$&8}LOUyJ6kju;{DmJNNf+#3(o9P&X8N0(wqPm|p
zW;s>kbTZ#k_UAFPo#yxz^EW;1dl*-WY<RGe)9_*k8%1k*PuBF-2t)uohl+;-+4mO1
zZV)@<B1HGId51v4+0{Q_au2Y7Hi5*j{vj|Q%l4<ONE}=J7~105@c%-5tUEm(Q`qZN
zm3D@m*oGlxvzN1BDTm!v40tZPfi@2p*hx)jEM`}kB7i7ie^~>&rEDD;tY!zTg6<l2
z=%+x`vXAJISI3sq#-@?gRiLkl{pbYxn%Ph2N^M~ydePU)E*ypl!l(M?qwfKm-G#n~
ztTTm&9<fX2fON8NY3ucv?LP=2PuOYYlnQ&wPWT7-XKVv~(WHw_rx@FF_73fqUa()%
zJa@DDf8p9o_HqXteZ@*QVQ4*U8`aIeX3grry<sz`{I!>zvK-3ZvYX=2=Py~^4!{A)
zc3NdcNm{AqBthaz&ZJ8I45R($1&Pl}v^GfMDJJqr^1TtA?$RfEC_OCoqkV6()b49I
zQz$K@nxxCp+#k`{B;C6OxGw4cYwpU!dd%MbIrsB?pDe8^86(4(G0Sh-WF0e>!C<Ue
z=4T0okX9{XhABg0M%kUABGe2*F~}B?tt4xTtV2Z!85GI9pSzj&kN3a#`d!z1U9YQe
zpYMIny`8&fInRBc^B6Z1P^-7Z){^>T@dBzj@cFvQ|1!tQ)Q_j<cT7D4LESUmj)$gF
z)9YDaDK|x$uEOYJ{P&U2@yui%2i9tnvp1Z6ZSrXg>Mv7&bFeNjUUU|J>$lrc2=k*V
z_y`!2eFL4IHWtt_eg)5~z0&uA%{M0q1D@WpIev#dh=#iGI9{AQv&s%SBYy1)sVEt+
zKN91aCx7GX(PC-e9Yg*}j^d2Y3i*C8^skh~IcSWR&+mdtkT*Qhmn>bl3X&o(@hy0V
zoIM=Q@03lQ!I>t<a1JFy&iWJ1?3bydp!$G3z6#<8Wo8}356M2SAaGd9B^>`udEy|{
z9Fgs3gXgF$m7ucZq8!K{lc#xBa9kE}sX1FN83WxX<Z-S8oRquxI&(_?$(g*<(#8)g
zXJq~=3@}Fy?GDJ5W)g5#?wSjodD4atqI0tST6mE!osr0k#0fq5Bm^(W<JZu7QT}cP
z>XPiw>n^X$*1VjsSeA}Jyl%+A=CE{Art>WMmTd75Ufh=XTftH$5A%Al2Xe+#usoD`
zD<EDjr*d|%LT>bf>PIq{cV$*edkxfMS;7|yyw*kMitj#J#ut+P^vzAEIY{ZXU_DHW
zmV-5mtj8j<+0@$`gE>W`_=!J<Vy{9jkH&C<<UH->>E>nHKM?}gY5oGR+@o%b;aZf|
zz`r3{@ni4ELrtI-5r9OBv*!4(rvTQpfqXepm_$0?0yomaC^)i-;<!4wnZ7*-?~>^Q
zGjOJmC+>E*>U94aR(_*LevsQjMTHR9N{Rfw=WSHW^Ym1*w*u#O^1lVn9W-zkICs*S
zQc!7x?ZAkCI<;I1au<d2dt7!?Lw>T(pm)cC%A&5nLd`MiHX2HENbur|T<TN|XU@{f
z`(VkVtzSc+fSS&L`Kxr%5q*U;WiO~Aay$XKJEVFdMtA8VZyET5)^IZC9_8~pbRzFl
z!$?S!kQ?u#Ev0H!Q%2fZ`1F8gjzugUk~{zX%IPVmiYw@4BWQa>UVM?Rq@~W_d`vSB
zqVEZ9{tZw~Kl1bzm#H1__Z9ud2hnSK#1D0~l=KpfZ)i#mSn49_-JZa=w0sph7iv%2
zAYL)rdA?{a)$Wx*aGB=Ex#C~6mMy@tR;#%WYNNK8b32<fKVJxJ({3fer&O&y7qNcV
zHgn}=k7i#E&cj;sC4fwAG^YhmY9I5mxl>wOUJ7+ui)<1P)(hJ97J!Rd{%rVmNt?p!
z&@OBF<H34G`~DjG3bbn8lXX?=x&n3!HG6)mM3J_g|325W3-iEoT}v4RXNt9a4Z3e=
z|E@ycP3_uJz%9*!r)#&hZ~3NvN2@vnWp}moNIu!`Yav|LEYWuGLuILU@C3}4X)k(W
zyye;qo*z|cb9tfqBQ2NjKb2a_7RW!=?mYrjX_Fd4;F(rC9=iY3CMSclPRosf>L|U4
zm&DG~OJAYyM}6T0z<hl`1o{@}mTmd@BU<<4TKFP;c@tP#toIuN_m}7+AHkVeeFrbz
zjngOb5x7*}&u7ju-F_zew(47XZTIi`iK7rWtY171&J+6L0zjVbycdlXy6+sYyfuw|
z05299cRoPh62qAnWW*U&$9P-M8YA^4bgwh^?}gHMBV<0P1mnsqxR_`><MRG`<EL`i
zO){SI-qB6Q=C9#svSEw&g5hc1S!ZXAI$kTV&G6xsfvLtKPLXamzPb;&9mYz2PfnWg
zC<~Bow8!!z(=KDwTx_eWzb@Df^#=E-asln5TQ!EoG2^Z9eQc2@9QADH1h2=9>jR$g
zgLnn_lq%kbG1X}uzE3L-!gt>VmEZ|k)EWGtLA)R%><zzuGJJx<@0mZ`$Cx5o^T@tW
zc?<ppvXGDF=tz0_EX>8qmtGh|oZMprHA`jdZGdI6ss!FImun<OwpK3T`{+7Z&1ZPL
zOv?i#$Z&pJYoc^7gX(lSAQRRyq>6#EOc~8H=xlkB_mStwS^WHUUKYASS%Ex$06rFD
z{yPNZA97e3ys3~qE71B<PHzOIQB=<JndLNxtBV_{4u$EzqqXxrG%S<rqoH@XR4x!*
zE2r^-!F5t~gUj)9Bo~eoWW!DnNtWK7z?mYS%>nF?IXvmvDT}v5ATmw%$N*2e{Eo{L
z`{gHnK^>5v@dB@d@~d(*X3L6Jpiao&Dlxh|SuzFGIhpJTFRn^^PP7%u_1&TEww#d)
z>W-uk1m~`7w+jRKL(cbrmQ?D`i*vTq>k2+3Xg2S9+ZjnRAFOF4`Qav=R&)UDqAr$z
z-E@LakF(^()B4-g_7li&&|<i}nxt)*ioT6nmwcGmq_yF*Y_m4m1w%{LJbIunMJxLV
za=&Wfd?X{09Riju+6)fKR_*MM@OPUQxr@s&OZDfxK4F>Onx7e$>+SeHyFyRnO^Pe^
zUP~drN?(@&pH}N9$3XWQy~QCkD!rLG8h_ExYzDPffAa(a>vX%}up6&W=UGOyacKyT
z-uQe5?CvybTY&oA@Z+2BK4WvFJtX!UVYL{=VdEWsogxxq{D_og<jn@_apSZtSYH~E
z>%qCi%$^r{Z#T<qhQ`xoUmgOLYj$Q1yeKduhksHa4^be2!b&pFfL~SghVSMt$ZHiG
zdPSuj!5yP*xrTWF@=wBKw{RHPdiCFlkPJv}3gZKl3t)TDQLa}E4)KTdke+FX$<VbC
zX!o#h2JOQNQXo6FY$%j^hQCJdxbL~fH(pfW`vmh}(e8Dbx0HD&4Tse9Y*&2u%We(p
zp$A66|F8j@`QA5YRRKEYuJ{6C(eh~v^e>c8&Y&ko=3YnRBI&@7TZ`p!F6L~PVOikc
zBj3*k%Ry;*2}ZNz2u`(}lEV_wm?xdB0GH$yj!%*Ns|WnOC41chRU)&^Ks}P_ykI=?
zg?#r61ncBJ-ds4JHh%`e#S}g1pDBx7bKXqX=OIFC`np{jSi_6VFz#yEG8|si$Ui=Y
znp*j8S15fW-${e`U-JDV_!LEZ`k`??4RHYH0(zDQO)-@F0}L&q1tnlv8A&a6L-Q)C
zv;?_>ET@9XB!_$d%(c(co3&^uqQYg+agDt0K;v~Pv_d?J>B<BM-JqUa?<=L4ufSPG
zHBO+)DeWBms-ScAYZ)kzAD*AkYYoADMf1MF2wqb)UaNo!w|1fqPRD6Qoc&y(Rfb@Y
ztF)ha>HKPKCC2sl-0dTtZT%^WXG7C-S-_Lt7qZhl*nBAut-;W$Wi01tYUB@Jpm9E#
z`_vCRb1rNyA-7IY8%wKsmb;pc9)tKA>J`b4PKsU>p>+dQEP;FyP4@@2krFsin`km8
zb+^&ayrCzRayvs{JK+t)I0Pu-FId`3(GNgnQYPOsj!>6cSUN@hUqH)g+BX+5I!|4>
zGIW7Da)stPrGE&{Vk*1E`JWr~U^-fFl084--=f%U=)6tC#zOE81#<QKE}gy%^M8<s
z1K=KA<s#oRikk%Uf6_-M0nf?fM-B<S*aW$kH1l0F*3iokaK0wVm)=@x^d7|LYr$RN
z%mS_S1HS(zX$QC#oT|;`HEc(<WA5lI)b`gv+ik7kBdDp=?D-k*g%&&%eRUdL1ZT7!
zodj)4AJ_*bQuXWoK^@Txd0uy3|F8^h-_z~4g0osTw}-NyO`Z9owc0fCA*gs$#Y%py
z%O+Fv0T}NVlkY6FCKyk+7_;8EZU(y>3{TG8CmDWqh|E@F4Hv{xjT&BGv)x$9xs#nn
zGG7>W8SS}Rwa*A14KFf`=aV6Dz$jP@FAf=@ju1F(I6A|%BgTM-u$N_A;C;i9$BYnb
z$Y&dleBPfhwl{&`Nh4_l8gq=9S&%qq)bV!0d}H_+ICI`;G!OEZjeg1hJn#0cOhLr^
zY30z@f53Z?|Hiff#0MN2iI#!Keu58!Y?|Tw;AaUC9dfS<y+fa0hE$|Sk2L5W7R6J>
z;eK@(`-n~K=Ezx}!q~U|vGD5O9l6Xs>S#1LM-MN6iZKUxen0m8X;AH{O3*ugvpr%v
zA*B)Yc$Gawi?<~|x=b9-Dc(sBe}taN^Y250kNHu!IHfz!1ExmaNCMNeW&_dTn`i~r
z>A@ZF-7j-3y8R<I!^eOxenER+lSH%xg?<Aw!8b~wVutG-xDujq2{LrVXK0UD&+Apb
z_ux%N^Q1dh)fdS_-Jv5(zQL7V?8cxp@eVFvBx@}#gj7cdQ(u=}pL-4;fuBL{?Rtez
z^y%Nb&jdGTH&<u3|Iy|d>>obWH!##wS$R;O!4bZJ?(LY*+10t7Ydd$>4(;6CI=FW9
z3=0bK5A~er8|dQf?Bee`(PiqSNiN<Y0ZxHIfj&+?-V=RY+}xbqo!z+qzkk$(q2$mh
zz<bg(-#{Pn|HPqL|50Q<{9i>zg?Uih|49G;LFAjp3>romgNA9R4R!K+-AY+|SeU7x
zx<+Pd-aBS3RQeOM4>ICLYi5tX?De_J$WWh<P?t&GA^s6Ay?sLc!h(Wb!h)Q_rujGp
z1O)}UL<EKSg$8?1@&QkvQ<zU^SSa`=hEEl0*EZcD=1N~39}_+XK4$ndz^7rxmA;Ll
z_uBRw-e<zMJqM2L)2dwu*ZO}WGs5c{)eKk1`<OW>rz(rjGPZd%b{eD18k^auU;F9~
z8HK5h+xN*BR@Jz;M)fdsJ)?KI`L0|Q;L-TYj2C+>T7RMJMr)s|=uaEls#c@S8fDC^
zvS>4>K?k=kPHtV=yQz%<mbMwY11yu?Yt^NFmku3WecU^Cace(mig)MEoqgOoxx2c#
zO`JTrQ+uC|F(I**_*i9x#9D6}8Tm1vOE|TVb`hvy3S|8R;lfnLXf6a&;DRiLz~VST
z)<T3b;*CRitA!vtAuu%-<RAoQ!-C!sVh<y7$!{1PakfGSwGm<f<A*{Vu>gJ~go73E
z6Ffh?<}Xe{d}af55#lVPn-J4sgm5eA1S8Y|itK@y`+7A6b`fGYlG22we*c0|`br3e
zya|0RL~={uU?DOXal6T793}++4>L4Eh^LI-Lf?D9Q7Gs&<uAB0f5M3L+!u`Fg&4x<
zCBzv<q=kC60-|7bka3C-&07Pf3Gp4{bQosz7veBuAR_fXFj$B<#t<QHBMKBQMB@*D
zvxFGW82OzL?g$HEcg-}$9}wEMz<EO4W1KI<MTCo@;W=ZB5FI`SE{0*opM{8Lj1}T2
zBXW;zJ^?NlqBrA8A-a7ETrC6wDd@Bi2weT2yfZMvy2Lu633;tkJFBe+%V1SkZ9POr
zsX;Y>Wh#*&NmbTZZ;)G5>?=@N>gFr!2zfz`d=08dr7+Z}7q6{R5QtZ6YOM!Tt9Vt)
z=o+s&z5#ZQR|^??#H*`}Uh%4JUA?*RI!H&UlMGvw{ae5p<-_nGWA9t*^F%`v)Iw=9
zm_{Y2tBhU=sx8^DtKno*FU#<Yve#@P;A*U9vjILj>1aHo<}zGR=NO8VqX}?F1(?A3
zK$S4{RCO?HhLA{93k@jmk*Ka3HZ$cSHOLITvs5BOu&M-5v%RWY12FZ=R&k6&PpMl#
zFgrB_SC*Q~@IakoSfm^q)l&fgYL=spGy-dqvS^IfGin^e1GNJ{)_Lk}W9VykP7O8(
z6T)uJKHXK1|0ch*0NEf!#aYx_yUC>MZslxQuW_y=NUuzl&*TN=Xa(})Toq_luPT$t
zetF8$8WtMltMNcKY>noj7u8!P@2EjGa3@M7GCWX~02+Ejb!&poC>7fTtwri4!!+e&
zi%xM{{a}mEr|O)o&A;S6^~%<!4Z`JUXY-M1GV;&?s=pmtE~)^uP_sa_#?GcKd6lRm
mKvVAsOVM6=S6kbvH+DAG5VWvowk4{gJ=k0ys`2(VP5%o?%63=)

diff --git a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk
index 239b7f6..c503441 100644
--- a/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk
+++ b/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk
@@ -58,7 +58,7 @@ OBJS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Drivers/STM32F4xx_HAL_Driver/Src/%.o Drivers/STM32F4xx_HAL_Driver/Src/%.su Drivers/STM32F4xx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32F4xx_HAL_Driver/Src/%.c Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src
 
diff --git a/Debug/Libs/sta-core/src/atomic/mutex.d b/Debug/Libs/sta-core/src/atomic/mutex.d
index 55d81bf..03f2cf2 100644
--- a/Debug/Libs/sta-core/src/atomic/mutex.d
+++ b/Debug/Libs/sta-core/src/atomic/mutex.d
@@ -1,5 +1,5 @@
 Libs/sta-core/src/atomic/mutex.o: ../Libs/sta-core/src/atomic/mutex.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/atomic/mutex.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/atomic/mutex.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/atomic/mutex.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/atomic/mutex.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/atomic/mutex.o b/Debug/Libs/sta-core/src/atomic/mutex.o
index 4c43a4f64bad179f3838e6360b4d3058fdd9b6c8..94fa554d2fe70dce8e8d4ee6f23563514875d40e 100644
GIT binary patch
delta 3067
zcmbuAi&K<U7{<>6`w7bea#uqHQ9)r{7L_0^4UoJ5hAduE*;d_11u+&<%luTrF-ucF
z9Zjb(wZg(~?v#nrIGPNOI$8#)iDu=cOwAcXr!+d}*PjqGydK{3-k#@u&gbuqre%9f
z>k>?()+c5K*Y^}6v15P`OH$U)o}n*%L<qCkYf`qox3Y^hWjEn(3RdS<KV@&kDf_cU
z*~hyn>oO}_K;-fOb>2Bp*@Ji<^ibz)o3i0V_UNz9)tv8!sq^<bMd$jfKZamulJ;hI
z<++P}2Y*?j^7tn!o7hL$UJ`^^oU<#Nl!`w|*+$Nd3}g*eo}~_DpJ$ZIjQA8aMS@FR
zIJmw;@^_@I>#O`(@L^}_OX14X!TBPE-Ui3D809asD!YqY9{^s9P@Zi@ykD#yMEtx!
z<yj?^eGsYaZ*=*bftC$Yo{S)6X92q(bxh2#4H%v5p*KWKBDV|hwQ$))mlnVWQ7xRQ
zI`mjo^e(nNN}UJ5dIP1m!s1GjU!dhTB!@(+$WYcj21&#LbqFzq@#=Ofb;gmqoyy~(
zZ!Cm%q^KBol&=11qQqm&K9`_;l4ruxKmAn90yYrL`Ae|oqQ7#~wu<-yI39!yE+B*Z
zXxEQA52)V?qzZ2LhYDSm9>6TY%yovvZ3d03CU4gfY9`qRX)c=mgy$ARw82LfS(`wA
zq?gLAr`j5p`!O-wfx3m;6Vk8Cx09|y^VpV!4Gki+95f5rWgBfgp!tMBlMv~Lu+j}p
ze8q6nL0`x1rNOGQmo;4hOm|-2AJ{bI*Tu9971TzF3rKGzBu~d4ft&5@bvGkMGs-KV
zJj7lPrl|_=qKsb|qL4Zs8h0|pGsLV#&U;yh5B_u)i02@;`N(hyxThwlqWKJGfxtwh
z<fQ1v0Cj7@#*y_S+{80b1Nd5bm0l`LVm0ew`ZGqq!D_DSQ2jN?I+!scM3p{GLYDj<
znuUqbi==fioDJGvB+G&A2V3p%beshx6F(VNtYNCoTlhWr&r)GoH^ZjI=^6-ZOt%wy
zlW4gTit1n}9S&kaGlwrh6&o!hejB$BVX>LqG~PuQx#ckN0rAJExq<~PXNZ#_Xz~d@
zBk==`Hm$E70+3Ic%L^^L(cwvItOarlj2}R6$-vBE)oY301&x2QkE8g_*m^48;!*Ww
z#~UGM1?|^S?R_0K?@@FIkG%<f4rZ}EX%GXC<)p;}+>KU;qpleYx&i+Lo_sa{n%Qe6
zh$jMnDzuMe+!|i?W-FX#!qK7)fw57i==%$_H#7RZcq271MNa@zBr@3u%h{mG0(TPt
zz6E7}YL+0kzZm)pniWy*FifwY%`y58Vjw%CcMxAdOanx0VY}C@d`G;HR%%=f9Ijtr
z;n%@^1yLL%v=i;^W86(F?id^oWw>0JScEi=;3=lg2x1C>7YcuS=v9C}4W_T+nMBR~
zeYn`gAH{6i#nesU=u9^D1@(>E%@ot9dX|Kv(Z<c7xR7xyb{qI}j2O#6eGVUt^%nJf
zR+AQn90FLi2R2j5s^oS9-Nupi5D5%tyl{5Y09}6ETH$>;la{fwtNyCXU8;?iqR>QW
z1g`V)S`#+|l<jGpw#4d7WwIvvNIhtx4n^IDwIa!gCjLfU*Fe@A*2c-9HSrSdQ$kgn
z!4kbD*5IiieveK0=fcVf_HhUR)pFsQcobkQe0@^?`%inG<Wv)7xVq$$HQ}bs6uUYX
z$z^JyO{z#%mp__#TE@r*QV5!;k+?Mx1%Ot>G9JYq;W2DPw=Gh!nmCMz4#SX@vCjGF
z>LQ#qxuj$@(I`34goE}Wv_C3wYhr|4lO_TYx((qb%Uk(H<uMe&Tpg>qBlRXPggK~P
zjS#w6*|0a%Bk2CR;wR$O1Q~Hk{`w2kF~eg`A7wA~daAwlS?=nJDz81SYF2HfXMT;>
zK5?>hjNQAyJ<H>&@whAPxlb0^a^2OlU4>P%Yb!jilB(xw7P_lFzT;L)j4vW-jGysr
zcAT%Wf4zTLi8C+PHD*GIb9A1|mEiE*PKgc*Da|W(<>!obN>AocBPL^q5s(q>pI_iK
z%Ayl}KV+Qu%m2T#*z-IyYs-Bt!?ybS7H3b<0<#?%Hb-W9y6@b`mm^KBMrp}H(|zM)
z$pk-<W5hd)ObJG%bAoAs(d<k$oiQ#?j5HoNyPF-7vDHR+X_D!HF|0J%)Md<&cBoM=
S?QG+t(q!|NVj<pB@&5uSnxI4g

delta 3103
zcmbW1jZ>6W6vpo^>?^JdxX4GE$;w8H$jU-SpcEOTQU)4}la*|MJBX4XyNoqvFO*Cl
zl%}s~W~u4emt_r929>EZIoe<!qcnY(=9F2fSu<LusonFN=^tokJYMcS_nhZ>&U4@P
z*KH@a+Mf2<a#oBk9MU^nsnMseQEFStiaE2*tye1LP~A3(=dP0YfFW^Nmc+gx68G9A
z#&i0EQ`R>Ok{EJGY^Op;tgOv35)ZQz(2X1_*DujcW=W>3TUnn;l=a`{NcnGGjKph+
ztFMst@}UyX5I3^lK3aBCd=g93CFW=n4)s~CL^YOuuf)e#Zv~JmL3W~f5^I361Bg?o
znc)e^fsf;1SIhb!*Sa%geHV;pg8GPCc22WCNTC<tadn#P*SI9U!|8DdJf0*wA6ldA
zY3Ah|S<jD?_?VLT&oGHD;I0JF>}=V|A1tvR+ILdN3x;*j_>(!5AjJJ3JPY|Yw0sLx
zn<4)bHQk^ZVN&RNKzx}j4W^>{K1#oiiVt#m3z^%15}zWO35<IxmY9_)I}PMCkCOEV
z)VYbf8>oC6@|7TH9~P=jHYK%>68C_89!Yb#T!&7XD7O+l{LJA!xR&C-2Hf@<`4KXU
zvB4#5a1QU<sWS>yzJby*PJ0uSsoNKV#Rjee4DKLobTxh2O{x!Yenjh_SuEv#14I(}
zZN%-c|7(QY?WEdM4EF?@ZGdV&r~P{0bf}{NNu9v7jw5e2so%nNEo}y96Nb$efO;`$
zKdKDE6FUI60QQe?IxtQuM;OyF$dvK=k|2;H`=*+aFG&NGIE3|Hq47h+jc9X#xvmFd
z3Q#t{awl``#yuTC{{;}YQzuO0lYp2`&U~!b%{T^7)GQt=?YpqsR^H1pt-C`l_DC!S
zoD%`luu_nst77HUNu0&4@6l!yfcC+1FR!wZ3KpYz6r~RU{RE@QG&$&l*#R&n#Y^dU
ziZ=0?vXQFrfgAf&B6}0Je8kD9<s^R>11hJ@cvNvEO3mf$Kg#}jDzp!>{KiPLlxAMg
zZ9-lzEnh*Rdr>HW2Jx_I<V(=ZL~F=j$7wpHKjdx>@8S@58&Kj^@=s9nVFt7r5c}it
z<c)krE@W8)Mus_wfu90bBeHyg5BF1JDU|o1_<sBr3(Z1Cy_EdT$at1{ywCmx=GRN*
zp-i`oxC(I|ru`<W?KM&JAVpuai*|kZvyQ?338_NJHgN4G>=VJO6LHsUfWFOsEi=0t
z0_T}`0gR*2uSE6|;I8IjtZ|`f0UABAGA=Fo5BmOy>__my@N{czT$Y&%vnh;y6)G3O
zrV!q1AaDkjnbfS}WuFK1S2Sy(++~!0mp1$8n+>2zK>v>X$H{paA)aNrBVAnRM6^ZL
z;kb!rFWNZK<`|~<fYg(C?+xHS!{B~L<C%a9qr`Jq;}|>Rs8d5u2lN8yw}V~_*v~=f
zbL`BdW?nke-OL}Ite*#UKRn{HtnGs{lGlS`IaM!H$)0MR8ay)IhjZ4!e~y*v9Ai%A
zgR#OX7HH>MB6dh+)M3<&<5oSVpV7_7t&3RTcHp_0&9{7Zk8pP!x_5xIhMD~oBVB%_
z+C*&%LnS1!^^HC@)TvmBiPq=NG;^cAY^ZeY2Se?|QEs%W(25x90`5x4lyW7gcB=+$
zsBN^*N|60J&E8PE*l8kv6VGEks{F=0c0!<458O~uh<!!Pxh8)s(V7~nlda2o$cCz=
zO+~J(TQnd;4QLnX>iTD>={m=u?$t)n<uq?YB}3p>9?5MuwwK4S5Z~_6jy2S7Otc$?
z#sTYVyD0~5#$;&+8tP}QfuZtfA4B`&nzx}UwA6;m#^`>GdzC(QC>xKV3*{bRG@oj}
z=>z2$+%FIknk6PaDUV=im*|u9l1FEJtpCL*+ecQ|6(}g3kXs!Iw?=a7Yg?NZ<(7pb
z^P|lzxzT2SbZ*#xUvu+<+(pf;^CK;_^<kZ}z#k1qqLH2fmov5a|J~I+>e?E54ri3x
z<EzVNgeKoy9t?#%1><{e$n1)-Y6B@fr?W1`C6!kM3&w{^v+Boq>OEesXWBID@4Od#
z-ps#b9}x;w1<Oi9Q!A^2x0LD2c`6jr`O|}USR38RJwpqY#H7}@w1jG-(bmSgHjUYn
z9|#l%il+5EQFONvcU@kQKd)$fUeBqL#lviGTa8tVY(H8@t19g$Ct3Ny3Y*L72v*we
zvAzh7we7Pm2E7iSma*N+toGVow#uu0wiDJu9X-}s9j9Bns(n{1ouSkgt?hq5Z4Z9`
E0xC(UF8}}l

diff --git a/Debug/Libs/sta-core/src/atomic/signal.d b/Debug/Libs/sta-core/src/atomic/signal.d
index 3816ffd..6bb4d5e 100644
--- a/Debug/Libs/sta-core/src/atomic/signal.d
+++ b/Debug/Libs/sta-core/src/atomic/signal.d
@@ -1,5 +1,5 @@
 Libs/sta-core/src/atomic/signal.o: ../Libs/sta-core/src/atomic/signal.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/atomic/signal.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/atomic/signal.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/atomic/signal.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/atomic/signal.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/atomic/signal.o b/Debug/Libs/sta-core/src/atomic/signal.o
index f628bff0d0a014f19dbd1033eb5d0c5b2b49ee5f..5eb7f21a649f025e67595cb82d34c0a2ba97d7dd 100644
GIT binary patch
delta 3128
zcmbuAi*t-u7{<?LcR!JAB#1;VVv}{rBH2Vj<64q57D<%dlp<D|tePUxL?&_lDjh?I
z&LqBxX-lV6N=Z@Hj8Uqz1R*mj!!Rne8iUqoOEn#%?KwYxLNm$h?0eqZ^SsYlPnt~|
zzA)9>P40%otk8ooLL@F4EX11RhBCLlLVh&c%-w|iu~;m^D&+6ZIAsr+lnqKy_B~D6
zQ}|m$)%jYGveEsNeH@}}fh=Mb6;!AtvcaM}O-^O+;jzhfRxu_;*+dzsTSd%3^`VY5
zON2U`DZ0X}&N<l1zUur5x0asj{3U*0qB?gBQnsMKvT>YmxYT*zP-T-G%I@QQjDg~N
zD9=0T((2+ZX1T+RGbuXEuC6oGwfKYNpGj*-Ql2t~OJnFqjMBmRHg)y^<F6<cS#DFd
ziQDf0@L@0I*+%_TY8uWUn;uH)%3yW5LGHmSY>~?TLc=4BRyRa>vb!r=1rM2&Oktd6
z5NV8`04FoaHKnQeb>Ye$r^`8b2&Gyg13uKF)wP9kcWFE$UU}Lny%j<?ki3?dc9Q$`
zQ85W@eirH&2I?GQmZO>$>g1DqfXZ_~Jr!<mC94W=N9yXIR!WRv_7wzGl3WR8{|+FO
zW!N~MLw+8lScC8m6JG$`R;h2R2!`k`WZa87&#8YNNFSh=^F4$vLz9^$jJfWx!`+~f
z)#UAQLN$`dLE1)|-NEw@Lv+H2o2*lye-x{78>#j&%RNEN0id4d_6O;gZ{Q(&%0sm_
zHZ+>hg`lZrmz}ingXSQEX0Y#OScygx0fu`C^ai&-rm7*{Wlf!c8OuYA2f$e6*G2Jg
z71T+IUwf<bdPpwDo`IVK>~-&phs7v+KzWJ1o*1UGcA<<~R#Qx!Y8rPj#9U(Pk@L5#
z<1qZ`B_M7@Zfg+ZYH)Xe#?5fC5a>WkWfX0)sFtzVVPxHgn^XpB2jw*$Xf+iUuo?rV
zZ!-EbR@0?JbqmODF=JAgDt(&-H{V!22@OF90{Nsudo5WRFIa)CyYSS;f;_Z&9aiGQ
zRn4vV8}MJJLVY(QMT^&?K;UA!L(rQ+%k@yS4u&ScK@4b?^G#5}M$3tB=GIB+Hgd=E
zE=)kGfr&lDw^DO63#wy?n_+0OkgpND)3~A~>HPq5lDVp>u?HQtQKKHnEinEydUFCZ
zmsQsjAAm+H^q$4v4ckcNSi2&m5ZeSfn`yt9YP)sV{F|Z&QB*7XoXuk6Xpjxq8q%g9
zpHj3s6?GLe=n4F<va``I0I=6Q5PN_>2im7G?sgu=CL5gQ!O`-~!O^{+(f0|o-$w@y
zV@R-5PXdwyl{7)}WWczQ;c@0~2jmD!mO@7eF+b631=TJ?^nSWrr|oFwNn`SdV4O?L
z5qS8V<wn{_D1@`MMn~`%y#uX8Ld~CO;v%74Nbe})HnO)?D4x%7xe&1&Wt_(2q0TsB
zih&mnef#NEfPXAR-^247HNWc5#ZEqyu;>b=J_e4i!N!s9Ns)V*Vi8rZlW?Vv@vwV*
zSU!7g27kE`72?zv@qMu)M2Te+Y2m0rW7E~JnL<_tx1Z82pRDI7Ad2x4*-bm&x)yG;
z;C(HVma~tiX4T~>)h0<zXd<B(t_Sj36VENm#u=AFqV>HpSraZP2Td3V>Ni-MCmGR1
zD2(3&Spuw0kwa@@7wxlps5avzdQBX~vkEcpPf`9Yu+qjpP6D7#E?g6n0CskuiW&3b
z|Lnz*Q%(4Ah09fIqJ%cHUFtkdE>jboQbn@5{L#dG##$_epowJ?w<ZPv;0bSJ4vIa)
zTiAkbuS&&g;xZz-3`1dzbw5Z~7m2KCqg0?Kj!6zQkxu(?+P6sDniwzFq=`&~J`UkJ
z<*ilp<T1>HIfK<amU@#H!rJ|s8llHZWy80rM-Z`9@zZOaT}FH_|IEU4!SLJCCb){K
z{FPO%(vr%>6;-a>iqh&O{_<s2t{F4EZdcXPl2X5KnZIO-D`#S1N=`{-nXjOtta`EE
z=c!n*tfr*WAGlzPj|vQMxPy$cQSkwN;0|-R$D5nub5HYlU&;0P?CF7i&IiF^MY+>`
zdD)Y_(lavCh#9`4@8m-7$V^{Oa;ei^YIiv7`T4@<%ggr~OZy}SI)>i}%KN{=xpMt)
zRKFQ$9r2MluzJ)iEqGM=@RanCX=#C*FYCQcmyBXhO_0bou6hcCg0qc5-a=EdQSF^(
zsx{7dhnlV!zk40l49VXnBc{k<`o<VnG}vmMAVj9o)6?5nRTN>$GTxWIg%gGF<GWZC
NVckAmh|kog{{TpBq}l)g

delta 3094
zcmbW2{d3G$6vppvcE2JLAtE6S@=6xT3XzdC)JtemnjpJ$s=6f7G9gP|8Wi6VWoS(+
zzWktcP-)eK(rjBZrK&p9)=OH<2wGKbL@{2cQkiP1_k8>ZHJrJ7?>WzX&U2powRW%V
zL4$2WoGqg+engkn-b%$UAE4Bco^^Bb%#ZcYpwOUBO8;><9LlNm-}6sNY_v&C>ML=b
zA#p>B#1ma4Ua(8d>Lc;b5Q)!g5U28kuor|nhwQ9$NeqdVI9gxlROzV_<8`K~x02;Y
zEoF{wvQ7qcX^^bP5kKrD>+PI6y36_i`zzyReXqYne?N(-tk1Y*Z672tH&No7tPepb
zwyW&Cmae0zX2Ins9H#?X5GThjIaZNL60cGgNRag!$W4dzU8vk+-3-n?+Q^8O%<@o)
zpL6<<2DU`V&Jpm_z_eWUP}4@~>%nrkR?oqyLL()H!F&_cd;?`?Y-fp;=r9+^Lg+Nm
zkpcbDXtD&d57A+DxKuTA%LnLi9n5$L4m1JE8Z1fIxVVa0wE?{kL03@x8JP#5(x<27
z_hs@g;Es7wvQtCOR$Ox(oUzpI2YCivk3rkRxM@+ODP<>sm<ji#ByFO&0?GO#qJ<u5
zNs|9P_AA1QH5jj%{3<e|wZENeAVRle;|Os2p~}y+^aXx7-c^}8H5)EL@M>X(SLsHh
z>C?-kra*2aqV3}{Cvg8lB7ywX#1^_w<PB^F?LCJ32+j7>YI}?zU();f4YUlAA303x
z2J&W;dWl}&<(gKmDW#j;5FN(6n@}YhPXr*BPxlt5=hFmv6=Q0pnT60AMFTmqZ>pl9
zlGF;stsb)8!^I}?eY9y|t~;QZ43(2~d78O?ihEW;eKDh%2~IT^-+{zbau#5{V~nF2
zMa@xz<jRBC?GR7r9j&{Too+@!E(QU6W2HHO);lC8hB%L^D`=Ajp*Fg_zymD<VHcxW
zhtiLs{)o{GH#s;=XXoIU5GK%l0A0oxt2?QK@j(RknT+h^RJn-HqE-y~-!PzRuE|7|
z*l@wDV?XfZdJr~rvQmv$vxv)*Vb_Sf!?<z}5*4G+Xfz0?n<ab+{7kf*{02@Z0^LMy
z4)5YJwKXWQhx}V$Ze&39koYAGPZsbQ=}588842bT2HpX$GGsZ451YVPL(AWy_>cI_
zpv`PXy@vb%GCFbcm+W^izvCe1#EBpaiS>xHk?ZS0JO0Fb&47M_qfX$@w;60ZP0gX%
z8p`HlpK8215qHgm=oR*hnb}J;5JF26=(w8pryzSFbdT{c)`z0$1T=bUV{mkjKI}h0
z_AZbfZw(A~nZ0OiI#aJl<b0aR!-iYn-$wp$AWM)Vgd7Llw&AL9MERZWE^=))e8$53
zHa%{E`9XB}h~egiQZNh6c3GE$pEeI6O(xQ`;fYhE-obkNp}U#6-N&%Ckb4Cow&ILy
z><j_NM^4?7|F)6uD0lhU&q3(F*_j6Bn11xJiyxa=?}c>}eT1Y~2RkQ3?tsO1P*t+{
zAR@}T-8nYQg>f3_e}fej;xhC2UhE8!q*}_taYHXAUHwE&s!BQimD^lYbttJyfnGeb
z>4aRrQTrmguY_qi^Y|-B@^67QQhUNseIwYqsgDiS;gHzfIvo;ip3=pJa%(#n>NFpa
z2()`yD`KcFodhVH&PJo!bDFfFe&VA)qN|)%=<W@5o1JBtv7Xm)0#)uZkE1kDs|RkV
zH)!l4n2Sw*tk9YoY7JZAdenxR%{7zVvR<SK8LCygNTcgNhMEPfVr>LNRq4JBl|%zk
zm}LfzJ;Yn6#JA1bv4%Q}iO!;s8(KH)rX0jGrmwW5hHBRu7%H9Xom_ui_id=jT53a0
z<ME8dxc&60Q+4MtY(+VX(VW(P(+A4g`3IrUb&<sIZSn}ZZ54eYcE{<A@ASVQW&7GH
z4IPp>F5B&`EUl<?m&~r1U*pa#tt_kZFLYP=Q>*5drY`XN%iT5pin7Xuvr9^KPI+oo
zX=PPq;9O{IRL=ja)przEzZ$rgkZ%w3=1%cV7@P0$`QkD&0)@%Dg95>>KY}Cj3p|+_
zzHuofuDFu8#KgEsldONzcLo}VKDNjBd_|tzalX95BG33-U6`(XKAk_=Gu1lNEiw?9
zxje|qN{$U|%JLe)!_%`;)3Y+t1NWaXd)N+Ji;8OOx5ijEiwf)y##q^&0$ZfD&QoZc
zV_ozNvYoV?-bANM3s!5TdJ}C8))emm``u@(rQZIwBx|R4fX!na*Kxgd-y8iO4@09~

diff --git a/Debug/Libs/sta-core/src/atomic/subdir.mk b/Debug/Libs/sta-core/src/atomic/subdir.mk
index 340b11c..d35e7be 100644
--- a/Debug/Libs/sta-core/src/atomic/subdir.mk
+++ b/Debug/Libs/sta-core/src/atomic/subdir.mk
@@ -19,7 +19,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Libs/sta-core/src/atomic/%.o Libs/sta-core/src/atomic/%.su Libs/sta-core/src/atomic/%.cyclo: ../Libs/sta-core/src/atomic/%.cpp Libs/sta-core/src/atomic/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Libs-2f-sta-2d-core-2f-src-2f-atomic
 
diff --git a/Debug/Libs/sta-core/src/bus/device.d b/Debug/Libs/sta-core/src/bus/device.d
index d0188e0..dbf6311 100644
--- a/Debug/Libs/sta-core/src/bus/device.d
+++ b/Debug/Libs/sta-core/src/bus/device.d
@@ -1,11 +1,11 @@
 Libs/sta-core/src/bus/device.o: ../Libs/sta-core/src/bus/device.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/device.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/device.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/device.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/device.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/bus/device.o b/Debug/Libs/sta-core/src/bus/device.o
index 05d8f6ffdb7042a63ea91e4e9fae333148d09185..2032923bc76f521a3425da150e04b85e0f36c44e 100644
GIT binary patch
delta 8673
zcmcgxd0ds{wtnC5+wZscW^X_RWKaYY1w`0Pf~Kg9YKb_fh9Q&6Js>Dho~G@9ibD>4
z&RUw5ddl%YW@@EIIb>?7SRIFB<&<eBk3*Ao*0Zec@BHrl@7%8bSZnR|4r{IFS?k?c
zja&39oAm{ua?<v&$rksNUP6SO^AKWkvJg)3?|)>EEFrWge_9es8h`f{LUyK2T692P
zcG)`nlWT#ETqyy0aB1q;AaXs{np|B2E7)bVj3(E~0&?X9Oohv$2B(tinK(E3aswB$
z&pI%Yd<RC5Yiz(qxNNFNJh}EokgGIsH@mDiC?|O-fLt?zk(kWZ$*yaIjO1VYkiDi2
zQjt4blD#$rImiL|WbbH$;PRU&vUi3csFbbEHOhZn_Y`t91tO>v!^l1tglKYti|k8*
z*;0rW7F9aFTF7oW<hl|xf?UdC{jMwRs-msBZ;OsN@eN_52l!BR!cj(h<j)pzg!&A?
z;%zg;@OK}f?DRO_S@7H?p?C3F1-oo8+1-7&!v1?2*%`iVal_OkvitbO!oJjn>>S^R
zU{C2p_8`9;*du!hVet#tkFy%=mVrlMuYQ>9R)L?hZ6&*PP{&L7pc3grSl~_AckE=h
z4Z08eS*pSk5$J(S!_D)Cf9jM+$deR;f@NBFvQtBVhuk-c>>i=)pEHo`-Vgj^9Ax)-
z;NM@LXw{^<lF)A?mYh2Ymo?H8I16VreRx@VW5GsTTdt-F;rBOU!up!jSHRoyHG<8*
zs=7ef?T)XM5COv}8K;NC@ii?kB!?#)Q;9LGHY2E8(T@cm^cy4|th>i#KG+aPi`{<T
za0?p(OVWu*gDe?@yQHBe_kXZk=F`^y`hB}EHd!l)4Cfj`{ux@B`rD$gUM4(!4i6P#
z5&2g9xBr(gA-V_k>?gz~a=!W7f{xx0)*q?lwwF5#aflX9{=PVi7jd+sw^?Bill#qu
z_SWrslcW0$%C{qB{t*2<C=^%e^9T^(b=f>_Z`W!|D79!a35+Jvu1UY`6y8aumq&2I
z4>V7^$=P}<<?G1y8s1ijc2u2gz)r4H1pn|56*|D0LYTBkH%EDl^1MK^?vYIUl(ZF^
z2RuSsWkw5emCk4jtBqMSdEG;hi?*=JIACgy_W!m%iGn1Cx1r<O!b)SEnf|}5cZ?4F
zeSNB<z30E(Z#Mi7&m~8DnQ1zm?MTKsgGfH&4Ag#1svqNw*E<ZS7eTk!l~INv&<&;9
z-0~q;2OA9n>BAOJ6>`sf+dIsoQz3nJYRWifUh(ec?n6(Q#iCn{2OATttS$6M*PP1n
z9tJYd=YjLrB|$JK@k%$y-m#EH1fUWb1ey|iftsi&f*eK<h!P+8L1xkurNqxP_)5&8
z&Q~I`gAf%;G*X8t@iZUE(qQ}XrM>9wP-1)w$YI2<63JAh5<@vmIF+ZwPl1rjXe5=W
zqxVUPuX{qy$buZ^0l9&CO^KP*c}m<hn>Y7&uYC-5F9JddM+jtg5ac;7<6TZVif<c3
zOe-<3Ipk$7Y;F(O?=l2K2y7*`(>N#*PS1rBpF~1_N}wsRiL+|i4E8a46_hxi37PIL
zff~aHzUd8nEQho+5U+W|)0O?b8K(roT?rq0t>_|piO6OMZgA2!=-p64<6yOq!tTp3
z_27b=Gxi}P;D4TPK9K6hhsU^jTU*#F9r7$E5zJC+1J6(<>k<dM#<kWm=_j+X`Z#0%
zFk^Xv<yq!1js07gy&M;IhBI0<95FCXxXBe2jD;Y27L^F;1=&G^yw9+kOzu+N6T+m7
z<dD&f+@l59`NQLo{o>i?Fsm8l(JY^&;UqdnLpDZ1&SJa=5?O8~Og``lAO4#2TFor>
z<O(kH)s1|`3YP1Oam7^zuow5!ydm)X!xQo%!+s<Jb}l{8G!RVID(>UD*6{45Z*e8!
z+mm#Q)8Y8=B0h+T4E|2edJ9*4j}sc!4y${8A=5n|yD%!B^VQdx?}Z$)XIrdpV~`_x
z%CZK-)0$VanM$85cy7`oMtFOTgzCq@9^(!l?u6$TW_q%j<{RuDP2UVk91Vdy%&Suq
zU?<oh{kRVna<@Ov#e^})(>Q6Jas7$gxfK&y$LPi|i6eQUw{xswF7H)l;~h@1s1@#C
zJcP48#CTk0z+dBP@=~$9h%2t@2mAA4$We^PON`|zCUFjjFW0g9%uvW;Gv3eNeV!5e
zo=JI<Nleehs*}@N$tX5(0~9rfUmFCujrWJAz@~O3IgyK>83+4MJt6aWXEMiqjH$nn
z0sqi2$ba%+jSpZ9YM2Pc%cB_4{pNW}t}~a>hf7j?YzvR^9Nr(zyhU?U$M9+hpY>w8
z8@SZxxRLrf5b_|eewhG!HJ4p%hmBtslsFIr>BG$U4Tt@dn=7+0Wxuf9oPG&YVmMQC
zq7e4{K9F6Qhs#{$sSfb$=7hX?L_T~3o<ThzeYhDi**}g+|B?|3_QGlu`|mTKu@;K2
zL@Ta1F%tGJ4ym~P6S>d&FcD)|TDZQO?XYt(KXko0(Zh_y0S?xO$K_ly_Vi4L+|DyQ
zHwpF`7vxFCU~)RYOhztTIo#mWxXK0&vyZ#*2Yy=*_r{(wCd;4caOc5OH3IT3->``>
z_{4yxj&ZupkK|4MLb%U>`)6YHefDgmJLzRQ!OwZpC@l02g`C9{^kUAMa}wbk;7JB>
z5jWii4Lg@}Do=6q9^%So@t!;$rhHB@Hv~JM<ZignUGg<2-2=3`#Yl<eZ+Kp^xm8QJ
z!<Ta1i}`9hcXAQ~8^HUsnVJnu!JI(c@H*EwfE)HA(=mf@Gatq3QJ&mdPIq1rJZqU^
z_j0c94c;30Fcz8uAg^$kWBg)ya6&CPcLx(;a+mbxwC1N_e<$wkmr;|L$3)EJcV!^Y
z!i(%Fip1*E!H{vBgy{~$hi1JXX{JaXYzKL>JLK3P$bH_BH9T^@{CutCT0^-T_A(O1
zjKp@X=?vd9fg7{Nz}W?SPgExCP5c5C4}+cGiTnQyAKuN!zGt?a{juDe>t4bY%npU;
zjrNdtGaz-YrXyc{m-{(|c`fHgew_ht;{ESZGaBMBhaW+E46&LpGek%v^}iu1sY?yf
ztphF{NCRVtztGi&7(;Vxh^<UPO9uQJU1x~34EtHG;0n*nJ9O3%D;YD3!aY;zB``$m
z0@$0mj15fj0B-Zl(eOV<eM9{}n=&;-DA#?6xg5aDYn|}-;p*4ZF+=R;v~qgFR#c@S
zE)Y(J*w!3!ITPn1EDcfH4D#95ke_u%un#;T>lxQAR4{b_;=09_R`@WD8U2DTRpPsm
zI2OV@4Y9(WIta3)1hR}0HAFSFE$xYhOy;(o(-CKXVw!A2Vdr^4o}?rwJV{bQg>=T4
zwhe=9?;PeP6&r#r3FCZ7CMTl7GB$wW>`yV{!~0SYmG?8+Y}9<b<|X&hFJoTDU{x-_
zo(Xr*-;-KWvg*$hF#FG~N4rj!6#!+vT!+&OWCji{m!}9XwN4(QC&8^=m%eDBdigB+
zW0&mNg4AxgmdICoWF;7UTQ)_JIv@ult)p^P7g9~KKMtIh$%M7~N}h`#wMILNwT;?V
zAlabhgS|JjMQF?&+8$)~rdF$y+N&j?vE1jh=b_JQ#kgj<ejF!O=*}WiEA>>6@QQAt
zm{;|0k=lAaiV8Pg*W1x2W1D^u=pWVV9Hfrvk--1BeglzC>I;zJDg7y6+N2NcP3jxH
z+W=B8SS-|`YLnZt9eupjaswahEw}Kg!Lkjo?XY|{=r`8<P<gw_6pLB>#4-W6e`Xnh
zF}q-Ce4Nw`3;vO-zP0p2OHEN<hmopN&LsL*;T%<7I$mgVRe8ZAimo=HTNbN4cL3>S
zY9!KLse*9uC3T~i)FG7*Qje=q7|c)At~gR>)h{%H>Vo<V{d!SN#@baC1GKNJj*k%{
z|4=(<uG9<0NQ$doGOlCGE5;I<8nwarF@@A-!wbDuZ#1+(|LrmU+LhFP<GW;1?;Fv1
zqz)P`Ow8Yn+0-TKl2L_&-xw1>@3+Q4od3yKmP_isvBIBJtu-p0)B@`{w9FFg0ZK+K
zx4PSsT4hbaEWB!sz}iOZS|IbfRZGS9?{@1Z8Y$Ia?I}qevN}-x5$g-c;+XXr49ch0
z#X#n7)+4y)oR$6!Ng!B*0p3^E(;(}z)vph!e_EeJH{Y?oi0^}+t)~!as_i!7PPc6(
zK2@FV2^*<7w&6sfTg|h5iSAltTLakMvK6A<_ieXv_i5W_sOfXt#w=1_+JeCLRofjT
z`mN1^vAt;<+l$m~TeEOd-`hOV3HNP>N0ORizkoYy?K;BGwC_RZnf7a=N&UsX9v$c2
zWS97&-EBXO{@-U`3Mv}yw=sSn*`x4Y9k=fSc_-}svE__?8G7`h-IYM<ntd-i;XC`f
zLQ=Qvr-0gBdrx{h)sOaggVa5H1UQ)Nkp)7hdCbQXJi|lByq<A8JcCJp;fMeT7ac?K
za$RxkLr&KmDFESy;~$v9?;Howq|==DX#CV{X93hwXI2+dE1hp3nbppud{XP2LomIY
zoMEVUo3j?rQiJm$(6rN;jdQ!5Zvuq<PWPe~qz^jtam{h31-X6Z)bZq<cX|Q6FP!yh
zq%JxOkmwa>FTh>rxfuY@_4GoQE%5v@j?^O0JY2fWGXRlRc{WE*+dV^3OM_=Vig?r0
zM1k*lemsKIRnHx6@O#@c7;%5{{15@BdsTKORp+$~Y%lZ*qGtm`Z&<4F#;9c!*)U2G
z-`XkT!J4wfBLjm7BCpk#r0sGFNqfyhzwQVd1^6R}5naYKc~GMdwX(=fl^S*OHhr_H
zS#mq2Va%3GFadMqEqtxLBum=Ur`0kBN!^vjn1FjSB#G2?tudR_Y%LJ|u~<8Ysa&ot
zp`_Gmtr79JYK4gZt`-Q`Kh$p1Snvzx{TS{Ga$m>PgzW+<uF2pcbtT$*aQ8%#<wtPU
zTzRk?sr7QAH>o}H12pAPxsg&ZZb@_WuQz&-7OL5Is3Ceb6=ZZ;KZs;ZVGzmKqjaI>
z!hdBp;&dv|i0`1&{22+iL2u$t40zJ%P9!_GN4Vs7Ky6B=Sdv|K<B{*$4Kw}F5e!qt
z7CdVY&qu!vDn*-*8VJw0i{NF#+vxvENuYd++zD9fqysmZ@(93PDsQ2i)=KyE!K63K
ztvIklW>USzPRZH7B{}_FlJnm!xqv;AD|lNXYh%CUO5T$wg<<vh0Zro<h%pRoK)$Um
z0?)8(ZArG*&_NL=kV(w^9Fp$%ZIV=?9!0Wi_#-4!^FdtCZkY1Sj-aQniEpm{XFN#`
zPNN3mQ2zA*BDix1$#y3Ol8o}e`Of{jlkDlhEqxR1BnL;LuP4hIls-jn!TMCWkeXGQ
zBf^`xQ*qH+d9W*~b+S32ctsutcw1yFT5GFZVI#Fo&HyJnr3>BnmRteccgZ$wNHxm6
zsO^2}59bH+&v?L2%3$gMbxO`al1*|Ia=Ikb&_I`^6Eko{?stQqJJN#k?#d3h=6k8K
zNzKr96p@;#y%a#IPMeQJmuS_Ph^1OF@?EA)#Fx-|tr}o&(85vUMy-&#jeg_!3TeNo
z{R!i}Q!5W6^?{ZJ>JMnQd`TVC(qr7DPixK4VrR8i!P7bIEZXr4Z3~{ROWHB&V0BG<
z+K<#7?L0D^tglHWH66c&(}?KzK;ZLwCk)au{SL}ru78ZnUeQM)!&miaym8z09Ay7j
zJq-Nr)87cfci?{gDe63?HS#dgV|40InHw>gbe$3V$Ow|I%5ai#3kV6`7jX^LM!t|v
zvZDpxlGEf>fL<$SqrmC%J$ic740#_&&Xm5`QYW9GTj-@34YX!UZ;<SsBhMn{N{Mjl
z4f(M*sU7kx)SEJ;kkn3@<3;K%>5n>h$*wf*^jl&SZrdY!M38!0ZU%(!$jcakcjZUP
zr1r`i`K0#AXXr6g`{h}D>Aff0l#pta{XocvZuxXy3V&ImPF1TdMitYwscEEUXhDk9
zOwB8gRGroz9X?C@F@e-<?F=H#(cXoctNjgq_`EiqE>rWgCvbee_AF3Zp!tWATBx-_
z7B6T6sdJ3g+CaL~IH{RM5q@r<tCr}yqDigPUq**+(^F_r8EpHv;La-yReN7YD$PPs
zSBqb$+j&R$S7?<&3yLmH2S}CMa!F3=@Holm`Vc}Qi#XNA_jE*)KY4iyNq@*qKhnG#
z5!l6*R#{nAT2xS7S~0%LHF!u)VnRkuVM*W2tk{CeN>@h3`0A4J)m5&nqO#J;suEXa
zS<To|+G&PHWrda(6jf9uC*{Y-;%`D+LSkIk_{8|+gk)EBMMYVaxu9dqG#Bj}S315#
z{NbTeT~&Xs`oqKc|M8fa?r7&99Hm!un_i{ki^^(>{~w5<dK}|i1ry6-##f9li76>4
zEOk|nt0^yZJ&{rpQyx90(lxGNVzH~Rw3_%ET2(T!%2iY_v8<xXm03|#Q_dYY=+Pm4
zTve3?MJ4&wB?aZKjI{nS8FVT?r=qx~tR#PM#hB_R3nrGBGBzmf|KgTbnT0j~c{=qn
zHm7C%oXmIHX8)&^xiU)%YsQ-SWAC@j&mWLGxbN`%VSNYpP4AZ#nh+P)C9Z3I-ngSN
zL0#h$V&aqI;-W(1<6{$J<7qJ=Auc68LDXj~c{Q#p{^y%UKb@fIb?FC9U%+M1^x`go
zrblZpG<{*+g!UIAyguweq9Hq(LqA$AhnTlN%9V@EtfRTw$+hN^qy1^&;?Z1LYj!@C
zt2M4OXB_LVom^)&9eYAL&79-8bmT>ni_GgJi_O%JbG3$@=Dd&lYYn^1bEFz~nX#YX
znrA=BmHo_*NLHJ{Cvv5)Sx&OreEUSM_R2of>m)XfI*A)MldLuGkxVjkPUXrx^Tkuq
zvafmQR69A>ynZS|wWnW_pECoS+G*<+n?0I3Xjc}SV@MtOz?|3AK?N)oBFVgP#K%0+
Z)QqB@ZHkbqOm#X!^*bO$lqrw<{0jsjRQUh^

delta 8781
zcmd5=d03U@wtwI6+wZschRvYNsEi5-GHj4R#RNsvRB$d0GeA^I5e0{a+jam0HB-Nw
zJvo<_nkG4$Lz3D#sW~=inmHaS%PcL+?)ojO`}Ev<p6+x0IzGA9`qn$G^;^HSz^-r5
z4{p?Fhsjf$!zWo>6S9N||IAH@13p4H#Gn7j)}4jWS_Y(%TS=ptpAa&YHfeEz-PmOt
z8$hnvHgcs07Qm&c`aa}Z*pystf=08;`qL0{y<bSKo`F-~vZ!wD$+aWNMZWx?dF->!
ziXq>gf#ez<xE3y(de%v<`_beo4cf&n>t%{bMh1~<S~CPDb9J(7LJ*N$+m-C)AqYi&
z?@#v1P{bf}DFSV42p*R$W69ngibthvY%W&;Bf6!N>r4<Hl|S?+`?FxYCO0OMeKjao
z3eni2O3NyRboM0I_27ZzQWopAHngjPw(7o(=~}v+Fwz5kC_CXklJ>}-E#wIE>4n7x
zGt>xh9iZs+B;Q(i?vT(ke3rs4>PvQ}@0+mCWRu;=Hv%{8ZB2GpzXaIlGRW@f+ZOga
zt;p`<*AsTHEFmm@fd_E*ZU?gcgO0+U_b}N_f<A%0%u06C;MlA9=$Jwu;X$`x|6nIO
zBKSV+os@+oI>-%|7Md4~fc6u*lc#kk5|-(iWVa6m9&+1YvL6a#|K#3ecX{9+=1z9k
z2mb9_QmmSE4I}gqQk5JV376&412_xElk~AddSSsvwYFTy7Q*jCs)Y4*sV|1te>uSx
zP*GVZ>~{CdN{GNb3dZ5)?*30&o<j}~I3^Ad0;}Exbrbq)!H51ei3jVhf}95%l4!Br
z9~*9CL(pR#sgMR)G8lJBLygaSuv-qHtxx{3-4~mz8>kqL^Mw3!v@qrOMPY4DexH3r
zotMeC_<#JF5kh1Jr}hwHJvq1izMz8}!uk!R9MPOue1sNG{jpffi#QtF!yIi7m%o~G
z>`f!9!s)Kd6mKj=-j@D8NEBD;vj`C3dEPv3k8IKqMiljyz-TP(n)v%p;WftebZeHJ
z79+$iayDH<@w(@F&ZCDSDLYw*ot&p=cC#%d+RGYGn1p1QgWU#ugaiuVmPY%Ov@J6a
zxrH^E94EvLI-||0G+fkqnW2b9n^R$&GBx)We_DT=9!Y5)LdUf^<;Ehj<NvW98yED)
z`V{vT9)G&utovV{tL`o2WYgh@B$?z0CfVH)q@|~B8Rl^6QF$~Gbc<aXMQ8%uP%6af
zORgvzH3I4PEgmZLJ9Cd$xLZUKeLFN|)SK76+PNO05oWRIR^!3OWGib6{n0gtau=zz
zJILpO^S32IFetIO9b{Dk<Uj&YiAgjdmDmT=L`gAZ4;mm!=ro*^n9TAPHNFz_iTSiA
zN{G=)$as8=;RBsD*nRlYG@2bslr@GNK=oCk6=kW!Tz;mx5A2L!$XV2qN<2^VNr{Uz
z5tMkYGvoj_$k&K#N*ts_l=#YQ)F{BU@G;nF1cVY@Lm{W~J*PO0w>jugzO8^NP4_o~
zyvB)5c?kAihTvfWTZyk}yeJV&<3b6qmXLn@)=G}b-y5EKnhHvs&VkHul|U8nflFOr
z59TLxsnwKt-3v02{rwoHWWrsEUa^q%G>OP&2;!Q+zD#pNiMuSHc?5O`hUr-jBF_&V
zzk!f1^38kNyYSJQv+o=M`(8HWNe;q?Wrq-Wx^uB2sTY*^oO6AKi~fEtJWGNgvlz>>
zEKhO`pJ)GSuHJO|p`t`{M(ZhlaX^xAk!x5pEO^scr0B9Bqcq6d47<t2J;i(cxG25&
z$#6!lXCZdpd>pdY37M7zIgddez;XgLrxJ&sfRv1!i}9XC#d0Zeoa6FJ#_~mu>l{}x
zl`}ZcS0Cgn7PDMB6gzJ)fLY9^s($c%;{o|8!)~WhqeN#K&`K=lCqHH$*Efad7e=wH
z1=%j)3ne~bIie%%jU06YXZ#%pWJdBa>S852x<O_zDgiWzl=y<lbu=3Ga}ki66l4i^
zS-ZZl2lDDvE~ULQJc-P(P|F~EbYx)bnc<H*;K}3|$D7%{&0GWMCxa61VUX|h>Rv`G
z*~Wh6!BNim{pRpI&dlG(L1%GMGUDNH#09NqbR)TlgSex=W(u$1^e%BV>Nv#ZO>pW&
zKaSd9d5r<T#@X~?#(c;bm-fKc<6N4)jK|B2<y<b}Va|1wjy+@hL#{BLegUqg{BSBG
zJ&KE%k&jgehqZ)Je4PnU+z9@=eDhaaL}xlYL|2k;a`Fe6d4(O|>C*?Yg5O=pr9ayV
zp1I+WH@LBe1~LY3aS`uvxPuwd?dAmvE{-32h*Rpw#~Qee5A*(Tu3I>h`bl05<+Bzp
zcO9o%$wcbmjwcWEY8YdGj)^hU4nKZfP{P6?_Tp9dN8x$K#hLw-fsbF=wz8ear8!ar
ze|1;L1g=AKE?i@-%v}!1i(6!WckJo<5M(bWWDfh+F!o_gjAowjw`702NZ1J$dS8i0
zIpgve*qiuC#q=*{o>g-pR<X2jeu?Zq!Go?n2l_rEVPQ5`b0;>W;kH!9do%a!k=F18
zarqjtJ-#DPrk|PkotWTHbCz}d%zg_F+~nE1uM6xVE|v$EV_X3|r2`?q%7<LZ7@RO*
z*E7@&JS1;<!*iPf_sHQ@_Pj!O(quZ)3$EC~kX2!jE-pb9*Q^l-5zG%vU;w8x>0Z;Y
z^Cb?YoXKl&X0^O$5w}r)4sm8EcGfW)?lVg+a?q_&R+ktgv3!a9C6lSTk}rCZ^Pa(1
z|H^$ghJg*_{ZqLFm$?LogK)zN&M%h<dxgvK9N$*^2v!gB4bO16RmJeE<Py6Uaei;`
z){uv>;KSEl=V$79Vs+tw{5f{Xg{WngwC4t^&c>-yrq}}HB&xU&2YIf{N`}W|&+-`9
z+j$T~aS+E{;cyvQkknHo6=!xm6ZYz0$o<UNr?};M^Z1&>x%x93e&PKq7>UiC(>cCp
zI1_Umv*822Co~7Qt>g(bXaMY`t(gBoT$^2dEHw-ZS{`H-=Y5hhIK=*2E#UvE6J!==
zGn}t(&3umMx)w8$S1{l{QP}x2k<k$Q`1yR=V~BZ#nIQ^di2sHdMl3bNMBdtk8paS;
z>1so)qCPgn8ZLo@0gs_QhFHk3pX3Za<9@lv{yB`9g=ssHCV?Ru7vlMUavFcjg`LYZ
zZ~Fx7T~uh||0Igk5QCYed%2dmyu8u@e>G>nl#UtVE{D~r1MGVgmLbj(PKMaj2=YuM
zE*(jQFhrF%<j$s${%P>P$1`9Z<GPv>re8nsu1hpD!N=2F(T^CqYlCpikL%RW3VR~8
zoFN`7fm}y{8lutySr7-=ifMZ|7WZT@pYHS70#A4vG2L{M^dVH}*hG>Mk3+W52B7{4
z1r(=B9^peWt=yMnr@x`XxgVj&ADu>zsDd^vNDh7p)4Ze|_%dt(8moLZ_Kf)w{GRAf
z!K$Y>qW7O)3c6Oy^#J81c@ZR?EhmAci{xp-ORbUy&1RQ+L-q!Rw#W+bW2fxUnA9$L
zfr_to%VDVC9_fSR4#{o^>!_TI`E*9+;J{g#Mp&!MvI*$8Tsw%hwb~jWS*I;U_1@N|
zgP2>j9}(F$tx6}gPm2MuT%T!Ep)Y7dam^y#BZbsrT`MNFL{9;btMytWvqry(&|cL;
zDRJWsJ(9kRP5L`P|EON$PU@Im5=QE{9tSp^(x)N9)A}}GdPeVp(eb73>_uv><)`+f
z*1IgPfyZxJE)!wZ7Rx{JRcHAMux+&*>+^fn+>v?YczTPgc)~IUxPNTPN1J_a+4(rB
zuPyjTuDWTd1*Imd=m=6Zs#|ONSK$mbs<cdKGu5cViS)X<0YK-eMXo^73)KRIy+l2N
zgRiK|LrEP`{ZZ88YB3t~BXuW<)OnSOug}#n@b!w?gRdJZ5@>&=!X6_;zER&%U#Ypq
z0(w`yV#G$1T5Zgvu2HWU-=ve;V0eOSTa3EK;NNazZ5vVtjQeS%>W%OMQiqL1bj(HL
zkUy!b#v~m4(io2N-ZXmS{5@k9ek|QL&JvMSl{K^@soB<3pv-*h9tuV+vhD^5OReeX
zg*Db@SX*nofG&B%dN&h4e>Yoipjvg-4wBRnt3>wyu+|`oW7ZvLl#i?@fXt`Xf8d(W
ztn_b40>L^6;9a)*HYat>>fV*qch)+v`3LJK_<8WNwK1NbVr#&=)wVTMPgP?ZZzDCs
z_NWH_&$4|CcD-yn57>6tmLcDITQa`R+KwToPi(JrCiR8Q8`ZvH`vHO8v}L1hZ`lTC
zk^0`&6H(l?>0rWr+rB}hCfh?0OqKn|CrG_ue+$er?VsaooqZ`7=UQ*SgSdCu&w~H^
z?JuGf2kptpq&~2RVqP7$Z$j}-+VimGoPE{+QdjIFv8BPj6-@ZnzNm=QZTsJW+8uib
znw{z=yVD@`i+yMWsYz~~QP8Pw)ig`hG`B49;+)I<Va%sX?#%$g75DD_NnLl}h9CY7
z?v()eYxk?@!f)Lbsy5Z}9krjD?sx=hfukJ=vBYr;!7Ovc4k5M5@i4k~y(0kmZgNy%
zEY&$Cpr^JwGI4H~V*@}q;BdX%nDk*se_V6i@e{)T*pY>icfrveHMrzhmrd%5;}ryY
z-H`^kYdlr~;F%s4uxz$R7^c<B9({1>LXZA<X{kpZV%qHCk6h|J`Xh;L9<@mDU5`Tp
zN!{>R??QdQ_wWHG_dIMUSGDJcR8lpbvrz3hp58Pz(Da6-5;I24qL&S02;R3w&{*Js
zU@1!?!=M6@H^-Nx?R+{(`%`Uy+Yvq(@W=F^av4+QVU0ej<Z>5fYShT&mh@RGU!yRL
z>2fAIV1~R+W7>E{uEgYDCZ9x5cjQoXz%R0(HK}TCXD+Gfniu#nPiumA7ilvoD78%6
zgKmCPBVGu#SMvhwf7g-|ehbHIA?^!yeF64`ZvrZblTeHHAA#0=pH3k;>Hw~qDc@;F
z>Qy<`i_~tp8>BocuTTiaZCU%oZ#TM;7Rvh?a)>(=L$cM<J|yFp5voRlJ8jnz@qd|(
zq#ujP<BZa&|BU1YlsDyjG<a)YbZu%AJeO97(x#VEz$#-i4PMn|B39cTC?wgb0h90H
zYVfU3DQG@;7Ca+9MP0`10skk)_9Ho2ZpW~ykzH|<DGvbL1=1NpYNd2N3*K*#Z{omK
z*_QG(wo8tFhve{gN{)Y*<OFt0&R~y3)W!kHnY=5J3iH72CP?Gw1s(@|i+GzvfVbf>
zktADaU{JI-W?Fo8Pm(U@CP^wK3j}Br+?{0mkswY7C%QZ*4CU!oOB7Uj=R8REO(z2J
zQvvG$M6<D>BqNXXCfQQpd}>Z6$qs?IrCW-fWZx1r(j@s5QlBhWV||L8gK1(8Z0_w!
z!9^?OI~YByWFtVaTJ8gQ8)b7)>rJ`XMrxCM4mH^>M^Y`-4!Ib(@05=L%7bzra;ujC
zaK0zEq9ad9A7X$yE#F0uXXHA>bXBH<K-Z)LJ#bzA>Oy^fkQStOM@HeAyYe0;?lf(E
zF{u}{PXkHSXw?XGzP1@1u|OMyco%9T@I&ZTZ8N}rO$$bjYqe#d?^f+H!rrD8qP@3k
zuZNR*Pn&{*9MYVAq>gE>co*rjngNQP*Dghn`b-N(6I{|ZVsu^A93W?dwjC#a&@Ldt
zN&5Wuq^flyI<<)2HkQ<jdITD2q5dV(UZi`X=&SW!h;WS_jv2REpN{C?(gRT6{rat7
z{0uyxmv{QDtTFqjJVvWLirk2AOV=3**)*(-#0||!CVfCiaQUMfP}-Q9jwEBV!KkS+
zDw$N3JcI<R<qjG>YMQ*AOX>yL8(V7R4!VUV&EJ65bg58e*9>_QZ!VE|PQ5KZ^dhxY
zo`>2d<7t9W&3k&1+9CUas5@mF>UR1qaTspfEuW1hwMVW3gzw1nXo0=*6U?7|^70T;
z`{i>q%+vvS5<m3bmA)mU4$4{-<nJyyrW-wfO(IWKrJVqEs<nyPq^4=Xiqs35rGQk8
zmIH>@YUwENbnOIQnxVZ7HB$=&$zIf+rOVVTZ6uDrr2Q9AnyvK<BQ-}0K@@YfF2o#T
znbw8wG)`$|akQTc=&Jepoj6iU^aWt(CcTnI27_(Cg4%h8BWtfO5Q?`y@@o7mv7L7`
zzYMArWh3cQ7eFe1HJ{|frjL_+zM2pc>#3%?7(yF0dC${BNcux=`YX*l(Lsrw+7|Tf
zNB{LqN$xbRsH9s?=ONAnXHtUmPrickk>iG!mQ@s(<*}XfCX|+?Bx74bQbKZ4a!OKa
za*8uGDXpM#^yrZl1x2N0i3tgbBTI`ChZh$o7LFYiUpBg|B)+7us5H^(Oh`#^V*U63
z%<x$MjKooe#Uo0~O2mIgJf^Fq`p<wS;6Eb_e{)nT_oRQPIxYTRY%yPsi~4smb^XQd
ze<EK&X<6~eaYIWAisRx69uTqM&l@U7j2l%{Fh0E`epKAB@`4eCV}}x*D=R4R#Qqf}
zV=EGi3&)O}keE|a@l@sL^2ExJ(eafdX!q#RWr-6;kA145ys)^0HkHL!mQ++$m={|$
zN&8o4|MF;XyTqb#|N8B}KEI_dKE*%t-+P~OEE+d_%hgVMBm9R9>6PEN+oMAUbnDx#
zV~@^Z$w^5WNo~xAVfWt}@j-l0s<TbJvrTJf%diKa(t2`oQo1vF%e8rHlG>DE_|RVy
znx@$nX!?PF5}GFbFVHk3qiIxWzCsLy4iI9-miqTn3|V9T_>X0Bley@FeEE%e<AZ!H
zX_eXbXdW%p9?h2*&5w`fYhkO+*kgHG(rWXWW8>ur^V?(jbR_#Yj?5vs&;0y&zUIBd
zO#U!W^WJ4nAr-dEJn<o}2|tl9*P3HU9yj-sEH@jSgk5+tUlRw+w@zY{JcS#3le}oI
zAUWIomgIIb`*a-nN1cw8*UdSnqt#6MrM%MIb2?HJ^UX`AqqLm)rrVh)E#{D!d?rd&
gE)b%%*?WPHS$@WwUY&d<THZC+kz8wjcqZV#0UOw8jsO4v

diff --git a/Debug/Libs/sta-core/src/bus/i2c/device.d b/Debug/Libs/sta-core/src/bus/i2c/device.d
index 448310c..2dbcca7 100644
--- a/Debug/Libs/sta-core/src/bus/i2c/device.d
+++ b/Debug/Libs/sta-core/src/bus/i2c/device.d
@@ -1,16 +1,16 @@
 Libs/sta-core/src/bus/i2c/device.o: \
  ../Libs/sta-core/src/bus/i2c/device.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/i2c/device.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/i2c/i2c.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/device.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/i2c/device.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/i2c/i2c.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/device.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/i2c/device.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/i2c/i2c.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/device.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/i2c/device.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/i2c/i2c.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/device.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/bus/i2c/device.o b/Debug/Libs/sta-core/src/bus/i2c/device.o
index 28f41f2a4baf6173cdc7dd631ac208b680b25045..189e665b52b179e49489158dc586947d070c240a 100644
GIT binary patch
delta 8929
zcmcgyd0ds%*53Pl&wkH2Z~#F-Q075Eg~Q+g<bWcI6N5Nn28f_^MNrW6S{+kSoN{>8
zB>QsAyjROH=Sndv$4tAHrj^|^&9X8zZ>9IHXHk8_Ki~KJ-FrXnthM&q(^}7Z);_4M
zc~L+4ANt}j?d!(v5htW;XLljO6MTi(+(`(B`0u}DWiKJLxE3ABt)#KuPY9V$i?p@@
zeb{BY--2AbZRF|{@F-lG`mBIl?Ssjc7FfkD>yQ$1MV69lK)?*REXwRkuFXj<^5q6D
zXP@;-9Ql4IB-faLO>o&%Wiq+)$*)xe9$=R>pf|ae29j%bFandcI@$Fhh)A9%sjUe?
zC~_LbrmYJ_402sD*}Fq<xzyT{y*Ct>%F>QQXz*?bu9KNK=y)jZk)^3*pATezv!P^v
z(vtma63M<6*h>oGXHga7YlZBbL$2#Bhm%WLtTB(!?zMD;?(5SACv7!z^dMJgHhH3a
z2?HU=(LH**=96JJe~j!z-?^}(=>$Es`3tb08bo$y->tBJ=|Og;Zv;)tS2~cL?Uw-C
zo=)}v-*nj9;>jN9Hvsm6?m}4n0vfTmJ#7C#<1_{<&2RM<uB`Ut3J<&uPmmkg5iK9W
zHVGF?OrRT%_>vf5iEZf*JH$qIN(fSxGy0R=J`}miv0cdS63TvC5!qeC*gtz9*}a?m
zW8KNlZt`EF+F0^K%{t33uEt^^-Xa)0?-LK!NDtsFJa^Gxt@Of#jjC@^nL-3;X+l{4
zEcNH%4ZKY>ZCO)WBJ6heFsl$=`NM?>a`XJoBE(Jlw1Od|8{B@B1lIVIE1W(S4D>c6
zA_Xr1;o<8@lihz`;3SU-$~Pm8WSe(yI?U6p)EsGqY41gwE+fEoE=mZuAg}hc%wb>X
zNrPYyfY8jINa(nQ@W9vJHJ=8dJO~iBuPA!2;WY1XcSne?8#Ei;SBO$CAu{MFKSi<7
z$I^oa7Mv&Cuzo3#53UY0mw|Z~MtXk|O$%mZH7yuSlf_uT^ZA$$eue-nfh9w5mb;Jr
zncSw;vW}LD#lNqw#wzP7VprgMM5T2!vFW!-Vf7(@*hOlU{Yvx~hyHV7aikD283Tkk
zOTNp$`So!K-|A1dC-_jozNLwuexIDnli1m@t9iv5p0O&3))5|E>C+VbA1NCBSsjOb
z6d^<}x1K`e(QNVWD{w>83J-6yhb<<k8?DotNnrZ|ty=fnN?|`2W!BkZ(nb&?9HE{G
z#e~Ks%%Xrgg3;4pK@d;o#t9MO>@0*wo;8&)iyUuWwRMsU&0u@qAkS9B!CAC0_79X!
zG(A6SX|RVrK85B?dplWZZnH-g7Pg~Fa%xLzMOzTdgIY-RCgJnjl>0sh#bFCW5bkH`
zp^&yVD7t%3>MChVMKtc`M#IkH$lCp#JXdzcyLHh=_eZl^97;Q%0mD;iWyB=iVpm21
znp-!N3fV*K*IV0Y7wO{`FBKZt3v;I|&DdvYl6stX(-ONyxs5KRwGK@gvb%ZOBVA^i
zcF#E1Exb8_e*blsMNs}qTqK;7nCygXpodQhBLMO<!dHm}6uuHe>3LLQu0N!;1*FGd
z$Zhn(DzP^P@&`&tiIu#*MuXjx&zv)o>^$+E4_vc|4@zWGrb-0xH5;45ez_&2Nw1C)
zo9RhZBB(p$Ym}}MPr5<ANkvd%2Ng_-(Wdlj;kxlC><jGQ76$t^pX19Z9pa$-^J$Ce
z-BO|%$6zH8lsMT9@>7POq#x`{1iKRbsCG(>qG~Fk^Ib1<RE5pp2`_>CISaC%s~l<}
zZ}8^}#`2Y+jKnQ^6qG2<h8)j04djdC=!sUspB`H!&NG(J6C;(lL2r!`4_Gc6273s@
zRKY=f;0I4)A>{jfvb7t1@hUNe%1wofgbdGw{DgxDVflwpc*+MsE@iyG;9U1JLJxbx
z@5Y!dVJu@&ETNY{eiI0JmpxC?S0)vd(OSwkW+w?3xwH^W6w;%wL_U{n5ZAsvGieC%
zSBa;2&0zM-;w#%Ta(^0y*?z^4(~==$lOVrm&kmL^Q9mgW#VapzQI0X*Pg1d3DbdJr
z$rLQIGWCvg6(2R7-Yr}wIgfa*+^{B=Fl`;4Sbvv6ew5w{C5q^UR$?lb<^<EWBp9A?
zjKSg7u*a~BkAeLxBkjg)SkCFS<lFB?VRj}LYwS3t?S3ZscYO49rcyXxd4@}Nh9SMl
zoi&8Zv?UftY~{lB=mp!xd`ceydj_NU1GBA`o*!x#F6$OE$tT!Vk_*pc497K|ZDe~G
zJzIn{7d@O&Jj-pdo$b^#%qDXM+9bg4%CkEe%As7bOFr<A<hx=xy$=}r>l~q15N7>d
z+=JT~4=X2@&Z)l871Mr<P3-{Kq8xG<!?B;S+{gIs=Tuken0;;t<Q;}%1w*-jQ#!!a
zTgR>QK3A!MtD2d|4e=~TdVsJ0xd=yG^@e=Fm(Ar3{Ziq{5Re*Uu$!5;nOyYR6+o78
zDD#*M4|>9LEdufmH`Yo<Wqvz&!g+Qk{kTKFwG8u2bAMMN-!{Gs^DB7Y1@7auykjWW
z@+qdz8$6rE6$)hroaS`S6k~6WJLD~%jpTZa;>73K;rBEk?{Uqlc~>-jLn^U}kRTPq
zWsK(*8j%Oj94^;)rLcE0iKcLE{JEHAjCFq|W&%GlC;MaN(r%DFk|8IvzbzBNhc8a!
zdStWT#Wn6_;Y#%4jE^t{KIALgav2Xs<DhV^L^qagIKOG^AI7~fnFIZtiBQ9rJ;oj6
z$CVqAi4#tFK<?=P>CW~0J0tW$CO=J9&Uhx1{s?Dzk+1P(?iu~C?M^o27%o-?m*ee`
z@T@L`{E1I^g)z9zQ14+nbmlb$Oe-&5nUaO|-t0L`XS$R)oe$Tv#~?onhup$_R;*yh
zSs<hNf)xzlB4*uRH280FD2JK7_qjBic+JsJ%x>iC?}WilXEwBS!1iZWjYU~qqMob%
z3-?eplXV$Gw4pDSUgD$Oa$xsmVDW>C5?^x(9_JEtY6;IlCe)LB^aC!(Ha>0rFwDNk
z-F%+I-8>qece%u_?VR7IytD&DJtGj){+yrUqNH&^0q*d3;6iL;mSl5ShkL+3A_4L!
zQ*{v+B8A_YCH$_v$etgVVS_@jasUSr<%-0hM|ViVm1I6=mdre8-U=So401NN+=srf
zw{Whlm<@TY;fY}+KIEM6hbkr3Ffo@i8#?njSzP<2d|EAkk31XC{9nzRZ}9bV!?D>T
z7jiP^eV#LD)ztkl@Hgj!OwQ&!gCD`%E@g_XXUw)R;N`sj7Lm~q*LYVQtue&=gqb0>
z#u5JwvFA|?PVmx7Y8XSLwSinteQb!UkKoE227DT=F~oX?{Tt38wj0mJ!vAp>*ij0y
zk^F`jKMM9GPUHRFu%Ba^uV5auq0ou{^C?n89A%bX<yx-e={Jb0hN$Q4zoBi0=*M9#
z%z*s}Wod}d2`57&`#?rS<AU3Mu+I?4h8PkIY3T(2=llljVqEW1!b&9JUY95g!eAL!
zG=MV*W;_xH!(VH~5l;~{D4TLfZz_->77%R>(V-n=CewB;cgF%QQv`R@6i=M+3I##$
z1W8gtg^os>M&v<82MtC26Ye8~<gc2O?063Z%RJJPWG_P}Ijo2-QI9SF%|^avCs}qF
zd@0|K#;SfpBRSzm@Ow%}3RX?M9ZK@)J)moy^aLo2WD0gKmIgL9$f1OnS}zySli*UD
z<sndLr)<a~wO<~_<N^6U6<-~cji})3@@qm~y(6m-)@k`>8maU0acuZd{t<-!LXHO=
z*J$5kZj*MkGpSwLYE<tv?GT8$TPq18wMW~5v<_)wK`hrN+7akawQV@2L2uTc)bo1W
zXi}^6928-Lz5&U+q)z}s8}&3w+}NzYgsN}T4+H(v`aHZ2@9F!fI_ivW;-(MuEr{?h
zdKcn^I<HT|)A6;Qolk11r6-uX#br4R9&fcIWRTivu>jOvmNdY&+wv9Fy{T$R$UJf?
z-Noaxmes)hf~62`cE#deOzM{9j)l~>miuV;XVkPvQuV4+2l~U|d{tR7UT6zcWyut}
zT{VI&%azR)NP4BZiLh6xx3Td>73odtm?}n5&!}&x>C{K+2D<37T7=OR^%eMfRW+l=
zQ#Vv8(EdhE0CB%lqfpPKMjhR&UNoM<k_|?eFj6lY;V925#$q73)9Bb7{5xn|PbbxA
z#HNxuYD^qS>RqEBI_5KD0I@_}GoHuX*TypJ|JFE%{XZM4@<=^2;?Xv<tXY|)7F%y1
z?G;u}oYG(wQKVk57N8eivQ7n^Hd#}!WV5wLSA73&x8@`JUDirT>X<dDjMPc%1?+#%
zx*3h~k+pjesgJEUam**yMT*oF>#+b*Us#J#tS_zI`jGm;8VL;VSx+XA`o&s~n`YSJ
zOG(w)4pBW-z3l}Xsrk0qR6>_})^-Q%T4w7H*!J0?k?&F4S`_9(+ucl37j0*Ik@~Bx
z6{>y17KPe>YrBk?Zrd8Vle%kbKos|FgNjH!wA~v)>KXe&oH@%r7-`S3?*a2ndl!uU
zWWNRiy0+NYBB%rQ>_Sq9?deoQ^_D#<h14l~8@yL%>|bY)I%l5`_Fb}X0%Nb*d*P9}
zX@4I~_}+d98Q!r6;eGwlKEgrjCwsm@>VbVPK$z}Uf`ZO;JC7x^-AwS}lFR*CFzL_T
zQvt$N_i7w^-Tic5Qa9cI3V?69yTSRr`|t=-GaVkdaGqnrFjCJs#)1&59Cs1#YR7E!
z!FtC8bng~N6!P8X*nnqgm*WDMu-7pJ`wlql0HM+0@^4Q1UB?U@bH>pRv0ZQkwj=ea
zV}Bs2&mA?O$5lsq2&wCiiGaJ_;{pI);4v6*E%xxiYqiYd)e=%GJsOyE9vO&fyGJ~7
z+2yex9N**dDsnmE@c?Mw@Hp#2eeZgV#=Sp#Jb`l6d9Lb6s@}5!)n4M+GaIl|XIUoW
zjZtsW&4#fY_gk}jHq9wZG1}9hH;lZ;eM#Cpk&=D$BfqW)p9=V6#|)?4Gvz&v2D9W;
z7iDVH%R0QTbLD*s!<Z)zmeFXwoQwzVMR^x*_i8x|LH#J5VB!PW7tLL#-Rezho;Ey#
z)N*Yt?rqR^P*7^Mb~BaKR*i5L>P;;Uu%FPPoWF+SH5=!(ba?}v@Z&(msi78KYC(vC
zG3`lKUdK@j<ipOSHp&fNqz=k=K+4nd9ED)qkyi<GeiPkD)6Yt&)Br}?mXwgut_Ou+
z#N#j0jD)|@ftnM4iEbpuQG!O&Af5WpNcKhvQkI~Z+8gNF4kK_~M}-HV(+CP!rS77K
zSEW6U+4NSWBs05$zJ0G0lN>k~G#_~dFXLEm5Msgw@PA6yV3N<sX@I3(rsE`2-UhhO
z$&bONb<(wB5b0Os32fLciz#1YujJ_WNe+L%<oFLrPT-*A3|^Or+Gv!V$q|WEnn3so
zr12|8?16tpysh2<p5f!7NJd-0pcoBrTKwW1lCGprB&ie=1V{_+PqNEw6s}u8ba~G~
zc+~p5P83u*_d%e7Ipx1z)j|Uh!570wMxGu>GET?-4wJf&?6wWE&v5*}Q1Ag7X}Vm6
z)Sr>JFf&75CbBBCPee1<BJ|=q`4AnlUd9884e|?s_o^J9L29c!WFxgro&vgiWg*zN
zPwofq`{kTaQg6vd<aShcg7a;;2_5-?3@9M=7uhzP)OmRXnO&1TK%g&WI(p!`taG70
z_hcB-`%%W?nETQRX3y3xjV3im>x%^HwbOV>R%jMf`Z;Y5;$5jt$|JQ=TMw{b*7_pH
zP1-_Y8~w!LhV<zt4z%}P?O_C|x3v(I{vB<PAF21W2?;LJA8Ns%*k!FX>hy`W8+80!
zdkv#&+B9OYx~X;bCv{J|f(WPUpLHcwrxOpUMfB!vNiEbb0*jTp6|8E|2V(mMy#`BO
z(sS@2Y}YThCbdIPLVXYGC9Uus*r>1QiAD5ZtQ(zcw5uh+jrbz!OC#Y4daMkmKkYLT
zI};MTF2<W0PQ|`TJXCE`z^Iur059GwIo*>~o&4J)q-M)lkY|p}#FBa$f!pWGML=tw
z3`3D!^JOsZTqSXxdQJL)8M|dT)E-#{n(dVpICP(U8ARPLi*We?xg(m?L3x@$pq~;q
z0>U@sb+o{n(t=_ik{NiD56g$%q#9*#2B{-5rkvDU@-hl?!X@kb()C|T<f&$9Z-F{>
z+O8g?W^3sHWsWv@B&m8W7Yv`PrK7y_w9B|@zIF&|fi^vi)Ix139j2buHevfBZ9N#U
zSla{wF40_wVyRY3%rRDLE9p$*1I;Xm_HzMUwL(ABj?^lB9T>VzFQ+Gi!M6K=Yo5K4
zwO9McNH&{TOwuQm7|AQ5+^Aq`l(Q4biW?y$t9Ry+oKjgt^68HVA@Kz**2NT(n*7<*
zLrD5XZu&^`%jn=#XZPyraTTQ{wG~z4Yn%mx2BaisP8wC#r)O3|Np-a|vub>8+4$NT
zXIAOBit3s&XZ5&AV=8E+`F%`QSY=6RRZYkCMM(+xot&7Ql9-m1lGHJ|qqDZEYFv#u
zGOmSrxwY-ze@o|@sWsxC$))Ol%f(qTu`+&q)%ddbvXW61^rccdZqn$of9lTv3w{y*
zX6&Ah3CZ~X$|Zd4{{XRe?4-(3&dHt1;w#&hS3Ad+OdRbTRZ&Zo99&a2vBp_iGI3m0
zjk9M}>7+_#;lQDTvYj>6C8cFWwPhuh&dlyP@tL%%Xh7BIN#n|j3aZL$pD3AFX0B=5
zvirZ{l*o*KK`0^rl2BUhtY{bSzw=y=){(vb*`S;~%SKHaV|tbU<X=>jms`+hSkaI^
z1$}z-&k9RUOiWEo+i4qfG(IpbDLFo=V`5@lSW;3#N<tD%CMPF$N=n}O<+7LB`OLwq
zLZ2Pb^h|wh-TC6-pDZ%ZY<N3YPB(A7{e-MHOWw()|1n_uJ5Ol$*O_hJ&5;4-)OT}b
zqIryDGc)j5t}HeySneZPZQ76LY9H-03y<e$_xG89KAt1P%)gQE(0;S;2@D!e<kB5C
zPSCQ0X8Oq-Da^SiapHxOx!Pxk%r>WTq|Kaqs;ze2YHmCgAyds`r()Euc>1SX^X{og
q+8lT~MlLhElgu+KNcx&fNM@V+SYA0D6EOX-5Rc=j{Povw=05=UbYOD;

delta 8890
zcmcgyd016tw}0Qg&%4h#Z~y@TK^YVQ0Xa;fVu>K4<^U?rp@Ix*IVCtWo*Yn|&7D)4
zrsCA_Wod|0B{`2YX@ilKnnP)(*<k8jzr|Pg_Q!X>=lSk)Q_fmzuXkGOw|?v02Op2W
zsK2yYUlgXLzxPJ7W74%HLx`r%hC-Cn$07duM;3M#LW>S)O>QNPbACd|-ZV*zZS)Yk
zY$=V%Rb?Yrn?`wXY3g(?xgHB9S8Cumc3FEAkSnl|Ts<32gUh03r;+PYqKkYvflJtD
z4T&M&<-z0{(P%SVHuZ86xfVo|YgFKFc3C~Ukn2<+xn>3<Fj=OPT@iwa<Z+VPOCbnF
zRtJ#1E)+4y<@sb+h2U`6A(rgwP#h`?TlS}i!y!0MW@4kGp*Tm5Z%g*+K=vC0$gT@w
z{}%~lUkvOlh48beQDe)5Ov)zLrJzCNQWk6Q1GIWAZJ{^xp?rk=&dk=Excs`3r+Gud
zK*-T_j^5ID5^VcWvJ)E4h8;mW=xu#h!7lAf_Ja*yhy7zmvNIbtqhWa^h3u|=PT2QT
z$?n;(9qjMp$nN9U6ZW(WAuN84YOpp2wtt{;5)TW^>w17|S}Srj4g3+FCT?Um3%Uop
zmT<8|1-fC2=2U7+iy(j4AvUs;Ly)qZ(u3?)p~zJZZBKUlQ1;)WG%RUh?0>2c*<I@W
zBi+gFTJJwgwXyULHOno(yQ=er*iSHcULzj7Bt3w$@O+sb)=Do7*r@uJJCt~%U#Jq+
zm!<v!yn*-I2oY3TRv_$l_b{svUR?$W(ZtR32a6C_>C+g7kZy4M5v4K5pIlApW5I(S
zLn2)81P~s+)-;&$=Y)9jh$daka3jfP?LwP*y1ir$F~T%Qr0Fsmxf(<W;nu{f6-{&4
z=X=saum?bBV2>np+(P)Fp}kdadI;r*M#6T5qW8+7afiD*LfmW6Xya}|6nY7fPFwjY
ziiJLwj`U!`e!>m&D~Nn>rO;S9#$9;QdyuG~FeR&gLO&YJ#{?eljq%{gnL-r6k|Eg3
z-N!yTr+&69r>SDmpYz9Kmh}^2SD?cw#5x+-{KufM=8!+EmRe<(5<SGb|2=RbT!^UF
zJ%#vyd|&+G*GD6KtAkE==1{?|)4*?k4$kI5tZe<H`IWV4`X^0j9^sKjpZe&ZplI|3
zIyUj6d7VWkA$rkh{+}~&Lj4R6tJ%>O)#RyW)P)Tsuw6y7*8MS4*c(Kc<+iBQ-oyw;
zsAuzhLgOq(Q9vER=&7(Eh$jc5g=iM>pb#FttWLr#yvV#@Ya@@E!S-%Vx;G{c&Y+1c
z9;I}K)Ah5K9(K^jXPG(O-cl|zx7x!8FKa181Ua?m%0w)P<v}eZx{&bsW5|7{gW|A-
zAqaOb>O5(SLDAjYQCCS@TSVi2qzHBvN7nK_dCqK$b8D{`%|^3Z97;Q$4#QJv4-=Dg
zi(MIu(A>JARLCu2zaD9$Riuwvyi}-HXN;Y&G+>{lUh2`_^;7H?<u<sG<~lTG{G4u{
z^k^qjO}l5bE0*%q1O5KzDvO}}m8d10l-L#zxsWbCB{J!Spu{=CSBYs9z7jpNArJaP
zb_#&h`$6udzE<L=D98k&oDvIoeyIj~D)0I95VCuTAAI1NL3~gml`>VLA0M;P7xwue
z$k}x3D6zI3q)!IqE0nGhPtgsh#5+_3C9YE<G{=-)0j@9eV1LT~@55lnQ*o7W<CLm6
z=#ISGOuDy}XuvU82?Ql-IzWEO5De%JJCGVgi43Zp5^G{0)A_6yIjX@8;0Y*zypaW&
z;VOZe&I=rTz)(Iik4me=HM$g(7}OQ=Nye!UA6!C2QNl3{(w8AP!$E&Zca0J^S<V><
zy9dLxk%RDN>?7&Ls>J)e^W8Lh@hUNv%B{p{>M)8f6Y?Vtq9M!8q44DOg*?TFea5+N
zWrS{Zfxio5KZ~&pL9xWIT*MgmUuDludSz1S8LbLFu{=?@$kibP1HI_dr;WH|eYy5A
z%%uLrUnO?)obK#-f{%=0<kk$wXhuF{brNK8BILL1+01eS^^+1oJTriidx!DfNj=h7
ziTfN^S~4cx<+!X|#Xe@dcYv#=82&h}+(2f@My9R96aK3V@(Q{uh>LVXD^bM<*m%#?
z!SHMeguE9CS;_K|DA+R?X~AsxfYWQhm?cGE^j$y5k)xTmyO`i{be$+s$5a~1M|w1e
zr<NgY!9CT3%XGN~{NHim+IEJW#e7P581@uK@iMcmjIJLgE^%4cnTbBZt^qmltYkPY
z^5}iG2hz1gNORGLGPMtLTU=w?nTpYIT!9fz*sXZ<2f~<opDT9O2lfkmRuQM?&9$oI
z2zxZaXs(NU@O#F?%85<pR2QdVxDO}%2)$^OxXqQxW;nJomaj8@KXa-pb<COHA2N}5
zSjte&<CJ!D^}b}tJo&7JT-DTG+z<;m(%pRgjbYg0f;Z$%KI|Zubzoa~(gkD(#^5Gr
zvzA<xaW3RK4&@NvVK+O$6CMtEg&S)DqjH$58o;B|>FW;t{iTCh>+A1|<kN~c%@3Pl
zoqrq1I$qI}Ygx+lxx=GbTp>SZz<y5WU_Rz&yF*^%(R{AQ8cuwU9ez&(GMQs6;Z=?4
z4XMOtLV{E<mobi8sCO@Tp5}60EQGy<Ni>#glgpf6$JCq6X*&6msp)~46&)a5NsyD+
zKaz=%!(>V2dUR#~9<Fg`3s+(~-&}(6J;6uDav6V(z(zy45>K&=;ry!Ezl3kP(H!X4
zI%aO=!&Y*0Hsi|m&V>Jj2js03$gW(!2iabn$yd|e91J|pq~FO|e#XbRmB9adH^?hp
zA%}3WhH*Le41s6KV8|aBv-OO@j|}y#c=(fePA=0*@yzHf_`TV4nD%rjvA;K5j}3+N
z;~KByKFe3|L|Y&m^8rg4z;b5Y#~S=!aVR^Oy(yg8W}c&kVRRKApV$=kWM)H<1Ga-%
zH56rai3+azkK98gOxE{#qZc^u4|r>ljb*bKSbTAzup%KhaS6(TV86+Pn!sD%<#KG~
z-Bt|5=mGBL;~ehVB6tpSiCu4SejoGH*zOp3ClJz~^Si^h*dz|95i>lN3$d{fbJ94h
z9UWmWcS7!Fs+Myh#`9fslJB+W*^>~1InVJ`kjX(5xWeITn*m9<l3c*#YQa3{)fgVt
z0P-nrxrTnQ*Kw}i%!c`lL=hu#hI7I%RZ1-F47r5a@Hp@D0M~vo@Ak+5j2??){-5Q=
zm-+aEO);P|CAV?jzTC|NnHkffFly(GYNKKM^47zc&x4p^E11aZ81VHxKQ=)KL!9MR
zPtqJi93spN@m)0W-w?0m;lb7d+ZATQo<u+y;sfeqLwwF9=){0m({_ef!LWbB8H9Ae
zs=2h*5bw8#-CRLdliv_U!(j*VeQ=0NJfCSkk9jbHctiZ3N|72u<GeqwuO$z^O<Xm^
z0j}RSw9F6{9M<%7*ol;-AwD6T43XpmIV=K)#S@l>s3njMVFp8Hw1NL?z5`xnT(45X
zN<`sYmsr*W4|BMpo}7U%;}O{p{xU1JC?#r8HYJeR6sRHQ5p4}Ip(SK0)3%Pg;|Q0j
zQGcwR;t6?$f>7ctNm4?EuBBqAX7eE<d<LNY&J;{Zy5dW+butK+xw8|=&W28M;3_&q
z<sAXdhP-7bS$q$CDcOX^8vnLN^0Dv1?<uV*SoL^(7|CZ|16|8ycYv}`j>qanG7}3|
z$N_|xS}%{#mEcmZ$h+v@ZE|52sa<j(26szO;J!yzqk?;7G?F_cixJjI`Bo~a(=s0m
z&d4VSYjs|}0y@5=eT%Wp+UHarwOu=lUEb2FK+Gy_H6q)gy@|Bm)rNvtt~zZe^q1OJ
zY_me|3AVqWhoU`K>YY%8O8o^Svq66h2yN8kDRJW!eFLh#Ro?;hPwI2rNuAPfgGRM_
zEl&DKUxx@k)}H{Tr}f8hb$q9%^(M90(hkgh)n(ZM9=~pBo=$3;<u^QSw@d<TRhDzP
zf;9bvMj`X?adZ|xe_&Yy+&{JSLYsYMk@=*qS#DWKUALrwQd3oRIH?L%mO{TA&Q)VZ
zjTPEFHKt$+ov!W!&?PF%6-auyYSE0;N~L4rY8CEH>WJ!(qSmSyH0CENGKtg|>NvHa
z`bwPxUoWVh7`v<n0qyVAh&)2%2ek(ETx`_PxoWks3sWkMC&EZ=G6GPZ*NjC#a+}fG
z7yR2})U_j3W2E4ndB7Msgw$c9J38i^F^5>9E*hIK_MI^Y>#rLhV*MTCxn8918R6|o
z&9FX@NotWbvN@@xRtt7nVQr76Rn}be!UpR&&}p-EJdk<C+BOaE-#4raP_*sVF_P2~
zYg93*<JMDHf696Zjq-{086fky^(wZhvo1tUzOots@4WRz6zf}S%0r}XTJsx|x^1=N
z1^l~pJx-ct3oj&9ZmXhtstVgG8>zXrnN&iTT41{Zc0F&K4cK<th9lntwmR&6#&#7s
zeP%n{nbbEnZ&drTtvM}J*KI+;q<*w5%pmoX?KGnJ#nx>Yse88X9ws%_eiVDouy;q=
zv+S>dd8R!XPh0F~K|t55_GJiaw>@nzseSeYs-fC%FGwbJ!XAeEs@DE>I;jusa|Nlh
z_SN9%1^a`zWUkr|4I*{JUWE*A*?n-o{%n8PLFzYqZ-dlb`%eJjS+@cdbh_JdOquCc
z3tpUcxrc|4{@UFM5H7fvVAD(P`@504>K+CVuDJ_1Z@4dQMryi4$ANPkBXIpJa|}%-
zwbGG<wq4_RDxcJP$A}_QuR4N|?^Z`8uBGh`e*jeN=z(>+9rp`J)i_-KVA5g76l_!L
z$UtnLI{M?v`_l0<j{n-R74*2^n2bO#IYt8R3Xf9&c%Dahz_rLD2hH)kM<q60?s1wq
z=kYW!e8VFgxor2?3Xbpas6;OBdE5lrmpu-<P~V?C2IJg29@|l_a?ej%ldAAsh-yFQ
z*{&;Kr_QoW!X2Y_(aDA}7w22kI@OOU%ZrKhY|tG>UMub!n*}M^*FNyi8BHGt{4ItI
zqSe#oZBS^2ta4GNMun`QH=CL*uTdDr9QkH3J<XMqaKWvXN$B`BatVU^Sw?_~cjYWJ
zce!@H3#mC;PCBV2T3tg@E40lNlv<-*YD4OEjmRd{J6b4UKc*E>Tks9$^&a*Ma#?{+
z(|3VNyoOq|e*?76twce`)M2Z6^45c-Hp)sbQhVfHkn*H#KpPmh<mZGr@90LFzAHJY
z0gTuIl#tOfhb|2x4*!s5I9uZyjK@Es8wsJ5ppn>Dr~WgNtSCY9Ni=w?Oee{d-Z-xH
z9hA1satc_reVHy^mAVO|?Ys*~W<Ck}b~}?#vd?VLd`Jj9Bdu8V*r(wCln45eoGPCL
zEERGxb~5E9fV)gK3MI8py5{vI{hB<61y!;?<!e++j((@)@OMd$f4AfW_DIfPuSC>F
zjpR(;lSri=gdac}zy7$q0>f}(<2%5!>6YdsBP?K0R0rH?aWk_?x)SRospMJ^Al0`A
z$@V6praEMx%R6<$rS{M^qM*wD1q8}{y5yfn1^j}0Bsicc$?*MsNJjq(m{J~XPqM>C
z$cF~u3q!6qc>Sz=4yjL-=P@!(enDha=0nXIxXQ87I(Z8nvR=jkic0wz!25?RN+<QY
zeAh;5t9%dWR?B5z-%hy;xbKqt0p)&KgWL|tHgF!47toO(NzYtTAIp&l^0cf)W*22!
z5a?Uk4n1&5*0@lg+cFI4{VZExn_pxEm_1Ybpor8gZ5D2V3hg9rlBHS(I%1jjG~!*Z
zJ=%-ZM(rHPu}Mouj+?cktw>dAZb*NJwi)eRtvwJ<>Y(;8E|NpqEk9DHw0}5Vq|a!+
z!0rpJ5Ou24ZZ;wHwe};PE^5`pV0Be{(x23A?JGq1tbRI;RJl&9qZZM7#gdw@2ZWJY
zuHQx4EA)j}Ua6O2$_Bj?E`&GqAVmMB9)<eu(^ogfJFrHd*9nv8r-h(>jh1BuxDnT{
zKS}49!6f5zBS|JaPDt>)C~s;w)uNJksA9&0QPX9=WKuKav!0~N<#oDx)Jz!y^30OY
zVoHS^M!V2Wa~x>Rk^U&MYp(RgnJXoZQ*TK>Fr!K~h1wyD3rSVWQP^~+JP)GolEZNL
zZh1X|)E?;`O=_=P1qk1kb!dTiq&JHFu53;BgW4zW;X6%@^i3!Ao(wJ_wO<CIAje$t
znQnCaw-R}(8Ja{E<=V>~NzK&S0hC!<_aUSzv@CSUY;7{iJ4gEvC(YHWpyp|N!${57
zDrhscKwFLF3$^uNz#{De2>6`lLKKU&M~FGb8f^jXX?&!axe<OYpsSYZ9&w~r>dV2<
zt@?UuU<TW61J^veAZxFfp(GoO%qQs+N{r+g&E3!;!$;%N9Tka=7{8?#$ti`yNIv67
z2#E}uqKl7di6-xOdI(8>$W0$<ej5=SpV=-iw=ezlOis$2IK23wPFceeorwv~#J~9R
z#*dyjV$|5uJacPQR>b5{W0R9G&6(g#N=QmhNJ&agOi5^+S2k|k=+eC5qsGQNon}RJ
zh`ZBCR{f8;HZt^YJuM))^zl;hcjo7x@V6cpV4iE?{{IST<bSfe>)+6$V8WQVvE#-T
z#}yY0AC)(1Y~kpMMa6lAv9WoHiOysq-d`t_jhr}Uc;2Ko#c^X|OUCDoESOM43@bxr
z<NK8sPbiHqESNBQa(t)a(nrh2jgK!285dVJl4g$^H#UCqxCxJzjxQ)Irb%Pt%8E<N
zO3fRwL2dr!;(xogaoX^SrSYSZ3jYsVw4*Kl!{ys<#CG+6@L#3=zei6H4WBq-TicFN
z;pUo>0CQvUuiL6h_QwUKB&NnCrnX9q4y&&~7&UcLLYu@SvCVvbLrb6YxIO6OMR$ot
z*HK&Bwr=}=v&c#_>tK%j$Xs%8vOH^g9Lk~pi!kKSWUa?~^Yo!?IogakoFiwL6G;}C
z2S{!={f<BuliY8<btFe?xyv+;W@|lmnf;Gu%QADr(HyPeZu2%jWF5<)GnO2qX?x9!
z$FgN#GvzpTEI*#3wc2N%KAtV}%!m`QT9(c1bE27?XHGm3rM&4qv)EjFB3!OF51fdS
km(1@;R+@e%qvS}lJ;_yOG0XWUqtr+Hgm}cfaoG320Jj`S*Z=?k

diff --git a/Debug/Libs/sta-core/src/bus/i2c/i2c.d b/Debug/Libs/sta-core/src/bus/i2c/i2c.d
index 8494bf7..f7e7438 100644
--- a/Debug/Libs/sta-core/src/bus/i2c/i2c.d
+++ b/Debug/Libs/sta-core/src/bus/i2c/i2c.d
@@ -1,7 +1,7 @@
 Libs/sta-core/src/bus/i2c/i2c.o: ../Libs/sta-core/src/bus/i2c/i2c.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/i2c/i2c.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/i2c/i2c.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp:
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/i2c/i2c.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/i2c/i2c.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp:
diff --git a/Debug/Libs/sta-core/src/bus/i2c/i2c.o b/Debug/Libs/sta-core/src/bus/i2c/i2c.o
index 10ffc7184fbcce99168d04854d71cbe4f57a311e..6e010e4346a0022caacb2c69bc7fce9742750241 100644
GIT binary patch
delta 8157
zcmcIoXINF&(q3!tv-UX$4%jFHA_6L?z@aFLU9lI8Vs8kF5euL|Vv0F2SO{n=+g=k}
z)MykjMg>H%CMIffiCq)D)<kn-_eRaV^G@#f<NKW_MrLNuUTe+FJMXMbJTYCr_r5;A
zp7zZb#UVYVt4>=Xf{z9ZQQlMthxq@0<mHY+XpMa1$*oJHotF@@pF6pl)b7qM+d?05
z-L;addF|nFX-d9Eu4e({O7P2Km-StGC38lSt9R`W;Ib&MR^+O1wjf_0zs2mc_75lD
zo`K|gz4m6fY-)BixsHU9E5ompUDox9<ccusYoRW0imt5-LKJyo7}<O3;&_?Yi0r*V
zI9B%RNA`)jI8R>D$o@JA2g$k3$Uf`G{)Wk9U-f7I?kKWv`E`*()Uc?G%v>Q?_aN6D
z{~_ekEmmL3S?16Yy3MO*V;t4fJf->iZS6#^`d*{qF?6ycYP|t_ula}O>w23|(OY}%
zfajfdWG8xs(0Q^Tj_hvUQLvv9+InxVmay+OA-kV<Z`e=T2x0NAU5UM`Vf*-<f^F?a
zc7WeS*beG}rH=nC*m1FB2m3vQ-N#OLi2v9>@L*87mM}jz9GYK?>~Mb{*nP1%t}bep
zk8x<zAQUULmSndHV*iq%WVfxy{_#m<cm30!??!gFKmBdZ-}R?0?@%X72mrU#RziF%
zJpi$A3#5lnWHr375p<Rr1cFyYyb#u{QvVQMZ;RPjWyzQ33RTC}cL2qAxQ#OpsHpI@
zlvAi@oFaxAA-#pD&$frKUZ8yeFNq#C@$OyI%Lr}TC6KyRU2U-l@iYDWMn9I8^jg%x
zLiZZ>5!Hl%LmKe%I~4^}1io^bc}8%PFkeas2UxML9*%Ge5@G;7OrRf+ZG>YxGCaSE
zGY=UdVR#OtXKg{Qy)$vI{tQA-TQJ3bH9?42<gG23Y;Rz?Sp(evZ!PUDiMH<3ob9Ni
zy2V{-Rb61%mC*tH(+#ESCR3C2hBj&s>8~vg6;xo>b_;gfO|zssG-Zr86Wv<LFw^B$
z&y`ETlqigZ>`5_|_?YHHi9rVB)fC9RJs|7SOepb*H>6u%$cr=$N_1@q=@S9@Gq0aO
z6QjgnJ~Ltn>~Cs7wjkh@*hLwW<S6;Bnt15o2l*xugfbv*D>0MmQz9}Eaw)M<i44M1
zi4k<+DA6bY@-&e_iLo|FvpVFQ!I1g9vN2&#9zHpY6AkVOPgZlt3!NeFRd+$X$F(+V
z4SOPEaHcEluL)8mZZbkYgu_0~$rW*;(})pNJ>61DjHe+~VqPj_81Y|;6b|qeBR84G
zQVE0C|Jn)mGEQihAzbvZikh#)1{xJ5vKf{Xf7ss=X_dIfa#4TSM;SUV#vq&SRV6$J
zLf-X+%%)*c;zPzPI|TM(MyMUv?c!AK63>+wP4|it5ky#*63H|tO7!O{KjiE-)P|=i
zgL#tWfKl+wX8(#Iu;)iX-e9P25V4dP?u2|?2l5hQu%DaQi`h`jQ66%;-{U0ex1g0S
zQH?`RW$2!cz~-65AQ#gmu0(4-)R#d%&;D$h5+%m)%HE7z4-Ph-n{}4c3W&j)At{i1
z+5b7)=NPA-`GkWkU3EEdXYNf1SF?e+9q570PZ;*obOk7pmkfE2L;lFzuFtg^jLK^b
z@U{udGL~-b;fdzd7jwlEIf<>I@CR}G@?FgBr3_0)x)5kok{}mx$WOV8BNRL{dGM0C
zbFKJoWL@}+nR-K+Vy~DDeF3cK$y}N04!bjTnn*ebGKMkOXoG#g%>`A9KH*AKGEMFW
z!TvXIJIOE>S>aL4k453IuhoaF&q$o(YI<?Adh;ES$^-TZ!+xE~xR<B@8B_Z(T~12e
z;Wmv*Wd2t%+q1cvoeWelH)1<iX>i^57>TXiluq2T){Ij;gY3@qe8d>^(Gg%%Kgiel
zgkr{cK9_WhPiXyTD%3vW|6J~Ob}wug&zZ(C9?h6;hpNMWjf3^#e&_M*Qe5)qF&<wt
zNxj;@)2a{T8ct;mvm~tpJSoAD1A0P+GUczJ-7YbUE7-#zPiT$TJ{&TEJ-*y~FAjf@
ztMuZ7W;DghN6Z+1?(2FcT5EngmG_Pcz?vnD$5SpQ!wsHb?tKkzkn1JGTh6Wp9L$Zg
z9>b_K7=R6LbFDqNug}>|i--R|OudfG>X)72`8SVZWA5(bhVcB%2@Uat-L^aAi&l`s
znK2)^_{CA~M>D2R5AIM7`v-<%X?1491HO9W8Sq9NawPY4c73e5!L@4Kpb=bs7xq8q
zF}ul$Zet`oe6jvJCU5)KnEyB0!F83pzL3KNaYyenM76m=O_?8oJOvS4fd^wYI2C*I
zx<a;L40<NPp2zK&z<1?&rruRPA&4=^;4jX}Nap{KgRx-<cl|yCzN`a05$p-zLwEIt
z$37HtY(2<}+yXM_?<20P9|t(Z_$^@?-sW?f@Ll<W_d2++fAE?_nmFQrPtGwj2nSU$
z8v;1r3j^UP=J3f9c1^wkUnIib%m>xtx_y{j6MDd3&cN2-^((jqL3|N?$G7APF0UmM
z_BfJuiB_GkZGC^pXg<P+^L@oV{wMc%m<4ag^U4hzvJM~Tslk7%1!QkdD2^F^kXLGa
z!WKTWF}FA?0xLZ^A<2z!J@<!eMGRzhc8z6<rSV0ymXBB+jJKchd=ms@*QpO#(h_pJ
zA7o%P$o$tJb80~ra;^X2#(6b>=P;A;A(wQS&#CQVFda;XvwYB2?pY;|Um*j2oG+6E
zZcQm~^JNBP@?}!Ub^pi(Y+-*D2b;?07+g#?pIj{tNi^iPwn>2P(ZdDxgg0nWLKtEI
zk4iUMWQdjonju2y2ty1dl9FtQ^-tNqjr}`ljty~)Td;<I4{)P3hOlsQ_ql)tJTF(+
zKb$c;#SLxJn)q*sQttO}T*q+kTm$B68IRBr?({usjUn0vA^aE$ufz#{TTWCp!~(AV
z9ol7x1Dw{=*07&YT85}bb72V28j$xxvG*ftgdu*Rmbnb!R|gL}n&QPH2V`@;>6TH&
zL`)7G6ac#^e^hocbeD+3hKS@gRZ;s4F{2OUu2je(O4JbXRHY$iH)cQ6HjTk|V?OCa
z=uDSb&a=3dl29U*_(@8rpsCah6*300K`cOwDn$yh$7_;|Us#J|VmLb7B@H_V7gG>5
zyhxH9amPk7eHi#Mwit7jy$5qLIRo^bx`dKdZ;eC4-rLRh-%NQJsLYek!0P#O9ca2-
z#t~p@y=>@1>N7bM6e^K6&||+`jd!K;7izvLlhx4oa+%VI)NxtWp42IMKc3WCc^XNc
zldB19bwgeYBlWQs1b{bdt_0kFyS2?R^!SCA4{-KqrT9hQOKmK!hl5&kBzjfb0QIAG
z62~mp|G<V7`a3D4R_Y!5lG>nug4x@sCjp^NdIA-0e5OyQM2($#bT@LI(l_FEIIVZZ
zn4Hn?^Zi$)2cV`O^a}v>tR59Y>Yg5fxm{@44(e{R96}3rSe6p2REfm`P<LA_fNPJ%
zo#Ou4v?ZuK^bU2JpTD;(1@0Fty8!$(OXp#vezmM2R;Yhj%Kb@AcPT%_D^T_0=>PYM
z)TE3|q0Lc~Qm0aM<%O;;R_lC8EmLnH?Ukws8`r4KL^t)7`W}^?QSZ`lsq;!lL$0X0
zc)F%e;0C&>*5c`|`UY9tS6+h&k>AwI+Vr&0a804OYK`GQV>TE|f&HgOPxNlPF$qwX
z7&W2F42c$08XcRFI%@cWy(f%r7?_`o+aTL5;|Si}Gb*wDU&c=Cdtn@-@l$^o$1yfD
ztoty$^Q{L_^%85bi?UJ6t>^H#$~p$Ku+e%97s6)iHjK$<*267H6<bfzNU7b{7NGc7
z*8EYVzOlZCEKXZ1Fem4&21ewP)yI?6RjU(&bj>;%;N7q`L9=dK3p$f}WGx4qpIU#4
zaFKp#wIKWlwrSw;OxraeTVOkFB~@g5Pb2k_?E%=e$aV{`?Xy*&-lMiwcsggB+@91$
zTaQFi|Fq2o&UbBfu<u{CkCD?uo7R@p6WbVM@!WQuZYuSMZTBGXf4V&k+03x7L)o+K
zE5SU|UWlhH_CBE8Hv6<Lq)P2=tCKopzlHfZVsDEv_|{&8tM-h2KpRs3uz!IOxoqDI
z#@@6~#gbp_I|h(?V6TaRd2Bxf)SlU!QGZ<OcY76pdS#yn5Z-qiiH_#GjX{dD+(N*M
z%kJlK$y|4zgL~qpyQ?3mJML|W=;{~uX#n_FcLUA`?&m<#e1``D7CI(lQkFWFfDkJk
zb%EMi$2QEtddFcT<J#u1q28U2RG_}wk&O_09Rsnk)X^OvR5~8g6sr@CojB%<;{wvZ
z;Fy5n_|efHJ-F^jYDem(BO;L09mgeLQQ)z35UDvH&!OgfL|`};c~lK2wanuLn!U>9
zF%$?Dd#nP$yFE?;*)KiHQOseFg9Az3^+-a0pLje(+!r1-(5;!CU7C_A@cbR!Uf_AU
zlORo#Wm$kbMtwjb4I>$Wt=nlkUkH|5Cm9Cyki27Sk+iv5peFmA7XMokTnPBXM-Y5Q
zzWf#(njue8rAC2#PG2_lp`1mXF$$$;Dm@j+eguuNM$TwJPiv))q@Kw&9Z9{C%`w|E
zwYMlYRj5^hNsF~Mh`U_##l5^%b9p2F4lNDwE3`&{{iN0+@_*@6i@|~Z82~5v0zh$I
zMK9Vk2O*LN#FCuU8%NEN%MwU!l4Y2_GWi&!JS9J;6pY8R0rim~AaKa2ehf7<nH!Gp
zf5ds}yb-yXU^Sv{(}|iB|A1;lzcY$FF~1T9M(ljFH*O$?scEAKlFhskE`IZ1lFhRy
zU)3TMS7E|?c-wLUx|{edZoVE?G`t^uiRs&z4bQmK=*#43l$1+Njlsio=?h#6WD<@t
zr46Snm6t%Lb<)J}Z<k-wFB@u)JldWz+AAr0VeFHf{eH>mmrBmROmYF`5?LFSk_$O3
zQOTbm4C_IL_i)0K?*C^96|fV41}B334T3<SFdtlMkq@vm<}7Z#IHM8CggGd)&CX^d
z+odLx?6ew}T6Y67$?ici`6Q8pL;3at5P|)JNQUl8BH3sP_BX56l4QH#{y3)l92?2x
z%-SU1m-h*F!XwLEP&dGJnJ^*%?xOYUWfTC|Ab;vh>T`JxgxVn=;hx+nv(bsYvMV)Q
z?UOM;d%sk5Nga__P|#7ip9Vx7la-jmD)|!G{2(_XwX^a*61gSUgEqHiEJ3C2$Y2+m
z@>DkUC-qDw;+W@hKknICS`_k}t=;e?RiH(o&Lx_OIasP~ZBA;L_Hi##o3t;1@Tb};
zY}l;51Jdr%+Mwnywf4kBwO4yHnA9<?I{JNFOZFmlTARtAhjZE-Ty$5oS0SXXYHxvr
z*R=qYeM|F3YQJa~vE!-s5*fa)cW*^%rXG$a%+Y6|ZFBX(z+#ym4lXU%8==!1^a5nK
zQGXXxSgcP(_Pg}1=;|T;g&#f-mHLbJIEVg*7g5uUh)*f95t&IXF``=14P`iw&}YSn
zK1)dOy0A`mtZq#ERO7CoQNE1DH8(>}Mu9Ws#TKMy$r9WQv*jQxDUfIA6uMv51Fb?C
zh$g#=<Ql|WDG^S6AtS4i+9MO7zLXUJeXo2QoZBb;QRja7HiDPRX*jJ+jtC=FF1@>v
zIv~4)%@xuI%|0l{VlWTMi*zBXN;wO3IxHs;b%`<q(U6la`K$|tzb#RxnxS0<b!KXT
zG*`rcZ|jkotvv_x3baoV;zKPQ?Jd;WB2tkS3^hl)2<+!-5{>*wtAXwFw6iu+^R;-K
zvOt@OEEZ}@i8;nvt<4ZpRhqde*gFL1swH|z6H+Vn>tN_k{cXA@goQexi*F3`N^o=w
zXNT<Ui5a6)b2G9sbDYWjd&k8l=B1@~@6<UeH9Omxn3b8Eo|&8D>^yp6Ms`lRGkap*
z>lw7t3=HjDZ&K>$tep6!DKSy_FE%<hE;=D5E+#%U-kF<~H8IEB8S2}f7LCiuOc#H5
zq=3J@7N3N_y$D}(S_AjLxsc$74gcl{)OM=F&E-s;GAS}MD>FSZJvA-EnL93TQkwIP
z=IN1>nvBhMj!T^~#+jCpn<Jb9a?+>dI7g>WnV6O1?36V+ZxWNP-=O~8oH^O4qtjDz
z(^Dro6FVeDCep5y-dSVvCZ?w(XN}E$Gj&S3vsXr1jx#4WHF9(oJ!NE$o|rc#-Pwse
zfB9^4OIT?8znUN&Qn#dDcxSJYb*)zgcloQwIXk7N<-K0ge`HN*wjJqPGB)LE6aR#m
z*vOdp=;%iEVq&7=qGIaNJjO;hkBJo}BZ?+8a=SzyH;pdj-;9#)caOBl;bzRfH|0cg
z%f3F^2Gjg~-y2%l5_8J_B&}+RSxM@~60>G$l3Zn`miE!^Z8CS2CTaIJn_5|t_Hwh?
zuPjN9F+VBmBWIWo%KB*AwwoQxlVmS*K{-8qZeA}>(k|~XV-H~2^aFk59P_&aeYCP&
zW=KV2X)}9Qgi`Ry6=CX1xDY>?t1Cja@<Ow+qM@{ycPql=yJn4pVRDq2Kys0pdN53T
PJkKmV*pLz`KIr>j3lHn=

delta 8165
zcmcgwd03Uz*5CU*XTRqhIFJa)D99in$brM4;*bNHGbHAW11c(+paP}V=TXsezT&GQ
zW@<TMIffz%j%k{eL)X+yZ7^rE)Jik;e(Sfq-yi*PpPuJF&sPtuwchpaz1Ld5^;`SJ
zZci~CooZUpK#Qr`7T#65>OL<-m=;dLTL`=O^MCS-c0y>4{F;#4B=t9ZgpgV8<cjm}
z%r5JRdgQucAy-rXY`8S_Ad_4v!Q@H{C}5XmJiU^6gUHq0e;Qn7<<^2+j}w}aFEd~<
z`z)m~<lESrTqFG};IgViiR6;x*YW~t*kvhC$6-dK7U9aG=-PXsh$8n6AiF9A$IA~J
zkzE~%V`aN6vX6$~Jb6(g`&cLrlFL%bJ`=$H;GSe(3S|FX2iaExUXVg~nN?nXk&s3g
za$OJXM=q1u;z2pfLOQ}^^{E?+qh=b%HNSvW?a3ACGYlTxM0R8ES7C29o@#!su`iOR
zrOy_4#<eCp-6x#RlZTVZ?&Rx$eVfoWb@yowJE}3+S-#z2-)bd<+1LLd_8PG31ssR{
zq$Alu0q0@csR!oZz^kywCXpQ$a1VB-jqLEi5l``uPU)JX1Ke=ve(JY5Ca@mt9@v~5
zf|}*cPGqNqqFDJbjqFyT?4R48?B^S>e@F(|9iRD2+{o_q%%5UBGX2*45_O`I0C4Nm
zLWot;0}u;0Z+duFK8F`pg3dgNK=27~B826AX_^JEua^<43gkUwnF_Xc>_zeIZi9@y
z$`P}ea*FUwR>V-<zq=5TY<mdHSF|rEEk=mCcsJhg(IcKOsZZUiqc)g@xJkc1)33QX
zy%xb(=<a13_?!@MNF82&ryMXv{pN{Au^tvT+>g@10T!%lfFnAF3ek%mM$@my4Z^WC
z8J>EIaX=4`#&dmo)=G<P(};VK(+NGTbiC~}0holmwbF66Aj8cP<o<taX>VnsWtWza
zN*y(s-IaFi1sFD^Pe%Vtx>6wvs7a<ME47F8F|%ETPB#4A!rb1cSu)u*r4KRE-CD@{
zhRdyi>tzb2#F2Q&t`t*=i!>if^wA+t4~E>_1=5FRLWxVhkfI0VHJSz`rbj{cB<d;g
zEw3L<6QjgpJ~O-@?9aR)n-TCzR8YoB{KQd8Ty^m<IRJ7D5k!er#BC*Br}~tLNQW#V
zHY$-vcq*|h1#(0X<Y6KM*;YuS4&=1HkR`lwBw??_Cwy`WC+gP~p4_I8CptjhuH%B5
z%(cd~g#8L*@G%XE5*AM7YeuLpbw~+2ho8!c{tq#N(xqEUi6JzEO3cWCtlu267YEqK
z$Zd{;N9XlFw1>Tx6Z%jWE_(Qik6uQjqQoYKWqBa%kBGENoMk!tCD=6#T@OxTlMg)R
z-jFvuAxF@#DB)tvHig5U!w98v-Nl?rR0#b2=w2a2iLfpuI@6pe(S@sYadzMN!xPJ3
z9$?vZ2t0?_zn~xN&mE9IFx2OXSW1*9KssrVlsLs0Y~?0)V>YbkDEGMCHM}OU8Lg!H
zIb=RVcY7c<zdiu+3%bOWn8=5EFv!Q*KbEFMiT=EDHY3-DgRLk2E8)%S`#ND~4u<@d
z{cG4h%Q)TS6ZW%o`EcM4+?#N&W*Kw4z6UnnV%Y65ut)cVY(!J5L@-yM6AU|@QJL2e
z_9&LWvlMOMiQ?41;EIQG64xT&&*t`(xR~2z42z48KA3^mr=lT$;4ThSun+R!b>_}Z
z;I}VxFW0xj+cKuueP%;P04v%uS0=c_o<^M}lJ<dgG6rj{u=l#TpuFi5u0%D{B(?$U
z-+7yrp_@Y&i4uSCp{E#$5UwwW!S{*8+gaSK*?b4|;Q_nEd(SZ$t9klUI0?aZH{>?;
zPG|mm@icGZYJOy(ws9kFa+T>^cOwSveQru~ZdnrJ)R;k*OwU9PpJ_ru%d;TY@Cn-(
z;{{yORX$-NPnn=t#QzfR_lR!T@G@tb%y`5x-44`&|11Za#r>YfvrBQw{~_aH;p*L5
z!Q;$?{5p<hJY?Utkjuj$yLN>PV9Ez#jZ3`26;v_EIW6(J9*0b0k01Bmjl)-Ql|A^N
z11VUU$YJVmU(1<j6Z!1~-un*Yx`gq#&Bf%oVOJRUK7$+NN@FPYu&b1Vb>yu3Gb%y7
zuwfF{+J^i3knO%r;Qy7W*Nj<xuLC?k@hFaTz;-hD(M;ifp75k}hP>MXvYauS@8TC4
zQ)4{$uM2mmko^XCy$-X%!4(%W;GrCH5cl;E6EKWh)0*W#uD*o*PG-;7oajbIq6^3J
z<XLO-BJ=-zYh-kZyMBW2{A}iDEZd&kpxAC$<IT5ZI9K5D48|PzM|XrwW(?Y9z@EYF
z$l<&4oI5<H`2=6aAdkN|RtNL{%f5KskGp=E0iWL%p2qC);zKLC!}BjbZgm6LC%FY=
z(9eCYtP=+~!1&E&8eZgc!Ukf^-TsiBxv+oonkh7K#Q(N@=m(*A?Zs>e;(Sl^hG#v8
z?<rwh`3Ah34*LopWaGN+Os<?R@IPt<>BZ~MatnO<BJvD?e*u@5$b>zDq+P<<9xuvY
zf{fxL?40j??(t>r@c=X44&jx{IAlM6csw=83w$-r=7f@&;Z?ly;UK(S$!9j;7H@0}
zkC_vC&<VCHH3;gg6H@2itY(U>q|1T+hT$a6hrxcA=bIoPyI&;a24?$BuB`rZ@JxIW
za;rDw6t4AGZd{Ls@CYX3Juc}2pX2%LYi(ybcn4z9D(+b|kKYsq+{{_O%A0F=+e^%V
z;a#!*2-h9V(|ncvUQzJp^Ev5U%qC8;TQdB?+}7kY*rqNns3hLd+98B4y7H(zPm6Ss
zNTBIrFdd<b7m1|0DC3p4*?)umw`q=bQOhk@#DI6CHM)4juwUi^-r{))jD|mpF+0u;
z4QomK*TpvOcRU@WL>6~0h`IV9kC5ctzo*vd;*C(O=}+P5+r@A95LI<?oZB~!cIo1e
zXKA&BeT&l4g`&C8g{K!}EH~~``UufmYMDzHy@T;^o3EGqb{rkgH{E=yn25=NvzaBa
z{86c3=uQ!bbrHdBI<3Q=lnGgp19_AZ)kPDkQWu9}+0V4?%iwopKK+jKU80<4@d72G
z#0u&(DWO7lP%~8cyO0fI0HWg|Qb;;dmt>O@-XzmQ(BT(WVrSnw6hvjukt7FRx01|V
z3cie3kGUFKg*h2F81$a7gpySg2ccn;-{<>ph7>^MA2J0jT_C?9bX2)aCcxBcIjkP3
z4`dnIP${1x=5F~8-qpw$C#hPg(DyxZc_UIs<gqrSj?2qUNS%>~vEi(I2jlUB458+z
zRhlmVuF#6paQ|)BuHcv*+C+d;r9Gr;N$u1|;Ck4v#Us&6+A^qbv`=wNxv2%%zRWak
zFsZjq&3cepV=BY!tu<u;p>?JNDqR1-G?fz7x0<3lk@L7|tsAKmrs)`ylcrc|l1rU7
zd4cj@n(CqKGp5nuq;8wSF}DlNt3ln3=ACH47V|t}m8vv9!qawhTcB2DmK66{)8?Y`
zh)dLIe*VH-2Hd|gR{;3$%q<3xx?^5JtWZChA7R?3x>Rq(o2hb=>EC;E)R??{q0Loe
zawbr8)dO8!tiJIhwNzCh?YGrYY+RvM5Z%-#>L@BZsdiy7&#5*TqKj$(p1xCidy%@L
zF5u~gI*2TORBl8&{b!YielFBqTPUttp?9X?RBQCpz<#~n7QNe~j{%gGdR?em{Q;VG
zP|r*yby)Z4N9w5F2?O)39to0M)lcEwZM_=Xf6}*N-yeD{jh}j|@4?tiw`{@iF0ed7
z)k`evU6hR~xA;VmT5cJRSy*eS#f4B|xe-R{1Iw=Fq_$bCsD8Vp87TgVW#SN0pIM5K
z#R<z}%*i=RI!5GcOFd6gmn;bwr0*=N0NxLlQE1jR%j6EE?pq$A`rj<|<6Wd5TiPO<
zY1TsUc!u>Xkez8gVIeigIvG8jZ@mU~EwV;n<1XuC4A)`n1b<Rzts~ozI&W=*594KP
z32?q)4aUBotQV2fJ?le!Jbtyli!2^m&-Ewu)cSrO@PDdpI1Zg|TZ*#ZvXz2)hHVO-
zHrP6VavN=hFOaISJzs~^0ow(%;*jli%+2SvsrU|@v~@*@f7*6nL@wA?fTLGzJFw)I
zZ7rB^*Jj1Q{9@Y))E?MUsXs3D$aWe)J+XZT5T>{dLPty7`Xj|R-3Egf7u<d8lltEM
z6SV1ydvO-2>+Z=!bal&pHvqol{uonu*WCwAE3umpaJGFUuAegdToB@I`v9P}(*7Ri
zV6}Z0l5uUcKLtOw+WP?Y?e<LwQEl&rjWzbx0O6qh9!;@2YF~$APTEf({jcm57>;l3
zrRc%;_V(b_6?+~My>34REM|Jl>qBa;#~r8z9(fp!MIOhpNiFr*i)Jr(d6WU6Z5|5&
z@OF<wKz64`B`W;LqpCNl8y@Y^-(NkhBkms_8R*sw&yo~UGd+Jsw@W<_w-=;ovdpEp
zW7Gr+sq38)*s_|o^MzpEmOzG1J%rbrq}Am>O}1&x{=Fn@HsFuxN$}|<@^f%#y0pg8
z(@dG#h@NK2H>flEY-!G+r#Ui<pwU;z0}bhErEG(w9>_)QNIj87nC%%_0p+G<Yt>-V
zVr>%QmTMkuNv+gekFaBlHWcyqX`z7qQ>{4u-|0M;kJo{N0Z!NnfRb<ty=YYwOtR;~
zB$8v&anxKnKaJEnS&Qkbl{Z1k<MI}zp#LI+sE-T*fkQ@}TGSACEC%2I#>c7idi)iF
zRd+<vdMyF}165BPH-tRSJA{Fr^d{PyY+#sDMl>dw>W*+tR^a|<x{>l#%>r;0rq$qW
z^Bi<H-3{#R@&tU#qAxLh8#hIf9Ca9d8COV2xzvPcJWQ2-z-6YKgQE=D0jHEnf82-f
z$ypfwP4XE1v7xGDO&iLnT2l5x-z7Qw-ICL<k(__6<O23cWUU{RT*yZfl{^EXM;9`D
zvj|U@3P?f3pdSHf*c7n8VJIjR-4mBu{533fo{=Pz(?Ni=X(+SRo>Y>p`}8E)-snKG
z^JBC*!{$M<=K&%Ihw|$LAnKQfl8mUxAlYaX_NS`mBwObN;+W2Jtt5MXfJvGnFApI#
zRpuI{AwjM$2qOaE8%mY_7H|N7HS$akQk&)HAk-FlANS-|IRc%imeZ+$YL|2Z?cK5+
z@H-?gqM*ZaH!hlw<-ah8r{z6l^QHVAshyFJkjPb84%%FkNd%R;E(f{Ll;7mIKvEB6
zI*xfLx8k0CQ;S5NZ)su3dZreMI+tiCF$ZPZs-~otYD>D2TBrSjX0F#3Vnc;iokXfi
zYlWJ3YE6iVs#@C~M(Sg&dwo(zv;{t-PG|=kyGWnars1Nys5M7(E@@RD;rCh)%D$>)
zA+=kYpD(H3w8zMBim7!AQZr03g4A5oM`+tT(_&z;)D!|Pm77N3ur;R1$Z)M`JZ^z)
zrVYscLsKhs^?<2aAU+QVO?TVi9QuiwN=?%nucyd*{BUZC?ntB?N>7lqPfzqFBzRqP
zdmC0apnWQKI%rfP3!J2;%grcohCJDf)SGexDD#$Fge5bj2cplC-vX`K(i=^7&5?@`
z^KFT6YKM%+*QH9PLG6?~0D85Y1kUY}eNg9aISIjQ<nBmPwQ^ZBsXfviq}wZ7gU$P7
z1e(2HW@nQ+AkWi<s1C|EK&Ovn4pEmVW1u0Qy5x^9Q21*Sb*kxF5UQA=dDC1G1KhCY
zE$t4NH&c5DA!cd0Xzy$-1(D`xeo%8YKagym_J9sk^EC^$|3f<i1}xAD8;~m1W+01&
z+B{;8zEVr>N9wd@tPArE2fAvBX>c5=w@v53(5<GOG__(hb;2Z)Eyl&L#Dw(b**#yP
zpYF*?>BU2HJGbvJ*y(U4I-Gy<WsiNOcw}CFVYVS7Iy8JOFF!d6%N&W0q{O7;#MGo@
zXKG@T?4p8#R|>O-=H(|i97buw5O;@ztY<$)NMt=@f4J@MjhK>9II&RtokjZny#*RC
zN4Y2dzZMwv-xTEf3y$QB9}}Nnke?f$n=>>oJ1>9OE5*ZevxmjSWjmdYWMbc+7Zi;u
z9y2ui)uy@eW8y}P%^sCAemK#r2%SynRhT=zFkx8E_*Y&_XrEg+x~O1mLQzOTe9<Uc
zT~Lsp@LIw6(S>7khUL<t{P?2W!lFXsVpLF*|Frinw+6OO7+PGIke4*<KgR#-Gb(pP
zclK%d-{nAc4lN#8`J}}=VaB~dewE)1^pcgf!I$C!Qk`k>&a@O~qXy4#Y(Vpwl-Sgn
zR4M0-ZsgXEMqi^#xsRpt)$N1KvfB8v`Zamf=)Nmc6N`)$yI$4&%Zz%vGql7qV+5%-
zWk%KR4EfMdHJMtc^+xZS46V}!V;!l!8;sv-GUR@vLv5z~)>vGdsaZE0S8Fq5g^{|4
z9<~^7?#a-aZ8gs9!Lo*XGv#%ocyFfWUuk^2H&zxHclSn6aNm8=sy*GpXN<P{BDBCc
s#)y4Ua)>c+U$i`D>>ycdTqOCkq4q~>FD@_~`=ivu?Ls6P&KmFk1#)}MA^-pY

diff --git a/Debug/Libs/sta-core/src/bus/i2c/subdir.mk b/Debug/Libs/sta-core/src/bus/i2c/subdir.mk
index 68852e2..05e59dd 100644
--- a/Debug/Libs/sta-core/src/bus/i2c/subdir.mk
+++ b/Debug/Libs/sta-core/src/bus/i2c/subdir.mk
@@ -19,7 +19,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Libs/sta-core/src/bus/i2c/%.o Libs/sta-core/src/bus/i2c/%.su Libs/sta-core/src/bus/i2c/%.cyclo: ../Libs/sta-core/src/bus/i2c/%.cpp Libs/sta-core/src/bus/i2c/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Libs-2f-sta-2d-core-2f-src-2f-bus-2f-i2c
 
diff --git a/Debug/Libs/sta-core/src/bus/interface.d b/Debug/Libs/sta-core/src/bus/interface.d
index 5a8a899..b66786c 100644
--- a/Debug/Libs/sta-core/src/bus/interface.d
+++ b/Debug/Libs/sta-core/src/bus/interface.d
@@ -1,9 +1,9 @@
 Libs/sta-core/src/bus/interface.o: ../Libs/sta-core/src/bus/interface.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/bus/interface.o b/Debug/Libs/sta-core/src/bus/interface.o
index c836beaedba5305f63966b9cf9c0a3f75d26b26f..f0888880eb122489a0d0770ca5f37b9b07165503 100644
GIT binary patch
delta 8373
zcmcIpd016d*Wde`yU)EB?iB|_KxGgV72z^DPY@0`FsM0?fT$Fcf@Xu=BvBkv^f+RL
zV^QV^IiaPfIaF$;W~El<n5NmF_L{!$`Ypfbd!Fy_?@b@qT6^ui*Z5oepdMbPUs<Y`
z1<6_4gRe;U(e6S7Pm2-4vz-tQ@qd5GS9%DcwQ59L!Xk~O-a^Rpo}>!*?ZYaYY(%O)
zHd3|s9R-!98Vw{>S`$)r^vh?Jb>vu5g{G4#*|!)fi`w3WR70ZNq)YW%#yV?SOVY{V
zq?+hk36)I+M3d@37^$-TYFK6M+LKf}d`UICDFTyzI?1I0h)6!_P4b!mgd%78ki0Gs
zG01nvki0Vh&gHFEB<~J{Q|V59mKMhX;7;DqNInq=Kk_Rwt)25@ecWJ@FZr{+pNr&c
ze!Zj+^(-nouSm#M{YiDhe>kZu7VF@Sbi0sD=-%~P!_pe6n(o`6E6KJTIwQAQND<T^
z4V&&By=W2Yory&~N<?qdU>f8QN<okEo(uT_5xql$HzBX4>grv*w?b}_KyspYGZ-Bj
zM{-ibNXW~nYkIPGC&;h0A$efKWXNl%*OrF9wYZxE*~c&NBo@yE(4w*5w~%wJBscND
z2Kkp5Gsxo8=M~Ds66WUt8|NF4+|u6%@^&1J4L~jA{k|l}1)>PDqBF@|16l7on&fUl
ztY2@sEsdmS)e4IyM<1n*9HxXlo)8k&NGB>SJoeIJt@Of%jrwnKB?#d?rM(c=_oZGA
zZNq`o8K1(UbYZu9UQ$9ddPwkac+~OynYK5P!t-I6d0z!6=+BsbMq_6LN&luDAsw`r
zU<BDxn~^hLpK3GP2$1n+snPtYs=3ee=7&a#ZALKd$N40gp4QflE1FV+>nhk!BP&Db
zkAi1mRGMklpnew!Lw+8WWU{Ft#6sFx`oBk<1{EWz4(Tn<mpTd22S;qe24j9pqlEBJ
zA+2YcbqN))@hfJHb+mIc4V5(tSEMb{Y;FsZiDoZb2+`-5F0}bKP7D{~C-M@ynHn#x
z&EP>aUrRK)>X2=()?#fEHQr)Z##tH+i*6_tP)WVhTiB>;#7|fpDzLM;-ZR+am2_G=
zG-Wh2PkMHi<4g}nQ};>$%C9~jwmhX4fwaUU3RsEYNYGN&cu~MgtRd%0Jk9{ErkPNp
zup#I@rs0Di2T?1P=-2{uGeJ`cdnV{K4fJjV=!%g<-6FU?7OkjGO1LQ*a>;Jav;L?b
zG}~y1lsFX&8byd!qWjZ;JRpytK~uuj7IZMRL5UKAlM<iUK!2zU`d|cT8C5`u0fC_P
z{XyNaoMqEwEKYO){jfJ^LOsx<oa>h~)JnX^F85QJl~~206tlB0T0&DrbyVUo2l{~*
z<Q8K=o6?XfQ9GV@`Fv-#e}pS%b8~Up@`ch~ICP0{Ptj2;h|)xoA(|~EzV`vW%26Ba
z#-C~R5a^e1<*soMN4%kFKMd5DEju}Zke<*CBm64Sk1NzU*^R}^97`AO=q!48l-R*7
z=tWpn;ybQT2nW}i+fgwB`gZ7_c%J*}WWA!tOo=cT=;z#&qg?RcS(8lTrNnfad?m8D
zi9<EvrbQLI=}o9r;%h#XL60jHoa5cZr7Ic$O&UEWO0=Pmg%V$}(fh2~#q<RUeXDVx
zhv@NF;yM?+BR4CT&+p*7!#LGBq<2%Kyy(Uz4zr1Jrg2Xld%;ix&Sw80$S*rV8x95i
zGz@eZeK?fJ;ATzZd704!ng#UrQsSBBpf^H6x3GLB0kRkH;TCr|<M|xKj1X)TasM9K
zA>ZaH_=Zg@u0a{QT+|G^<qGsH4_*;BE|t4JJplRvJwWf#3!+5QaL`3uS6{};6Z*gt
z{y*hT@8#_&b)Zu0xCd{SIH386r^7o4^7E|8h=F{ILHZoyql~AZ6*~yx;=j+y{1k<g
zR~Y8|c)kj_9j|b6oo>!=1_$BGdAqq!|Kiw3G{)r`&c@EPoEz~T*I*>)eUU5iML(Pz
zF&=a(&xLpfa%+a?Ja!+iL-XFVpqXr;l?UVBhjR+!>^Je4HQ}bb!~M=l!G(|Ofo|lJ
zo{W_`tnufjY~+5|@aV?Vv#Z2pu17j&zr7nYjWp1<97<b8Ny9|O|NLNV4B#T~=du)W
z&(b&p9~*XUY@%mf$g8;QC%KEsoa;HxvNPKm(iUgtv4t#dYcYT(GI{qr-`&G?okR5?
z{Ga7)?t0+ROm_AuclUX&L{mn?Ne0^52%LGuyFD5IFLACLxv&3bxw1XZRB-#6XFxvR
z8+19({Xx$A8h;n=At1LX=d#Ch|5kRz(cigfr&u4y$oPzlR>^}`&HCOUI4KzoTgE|-
z;etEZ<wqR!h*0Rea%)C1-Ot(kvAz$Z$6dmazQxcm*;#KMwyE69@&uUZ!j9A9An#;&
z?qdvJ=G~|i=r`~b9Oo=^xr#*`Tt*-4`f&|rakKKc9q0J<-0bFg4Nk?OV6MRq{^Vpt
zLerNIm2%g8_+-CC=tr{V0YAyN`0o5s(7zD`8pQ3m$?mUkVksP=#+9pOz?QR}U&k{3
zzZi{c>p3%TKD00Znw{)^Ss>(4M#EZ9mKj!Wa84s6G(m$wmoa#|bNj9_Ja4n*iT$w~
z%XRhT^SRuD_CAdNp?=st#DJQ|rgwAHXW87LA=quhCcfj+HOYi#Bm=fTXKCR|Eap<L
z^TqBa-VNoZT;as_ux13Gyqb<P8_6c{ACHB>*#4Pw(zy|@@{mL`+Uv6>gCSPKZ^K6n
zwBy0JJES`(Jr+dohJdCq4r2Ww_xA$bFc9=u1JEi?wFA)L7GH2Fd>M_;af}z((C!{M
zI+)QgiVcnCo_)uU()(QSF>P>WF5j);Tit@7c`g|=m>UtqqkEe5pEQR)ob70wjQc(p
z{}SVQGDGYz7tPKEzs?s{5f}|&<A6*$V~DHqpaEpU5JyIU_HO~xA0$AoWPPt_$QHIX
zfeZdOS)+V7I48F?(#;cpiY^=Cug);Bi#vLZ^oA%L2hAML<9<)b?=sF;GY<N4=r^b}
zhL{kDT`zJ^XLvW!0ewqu-($LEh`k(^NiV4(Mo?IW@Jw-oW!3{dz@7VvK0=1@uM0Y*
z3FyqWFgk$WfEhemI?u&McD#{M(w;vm@ti<7*CU176laBnZ8UOJv+<xiC{RO$QIb@@
zaKgVKDj2u(TEk5=11gUlTxXXLDF`JVQm2Ut73c*tH+w`aQOySe1(Du35z_?FYIhwp
z@jHAudeuNbEGeAmC?^^@ItlM$)+XR(!WU>jf%~9FZ1VHK_w@S!+l%jXB>L)E;I%|9
zM^P5Z>QG{3@&Oe`t&*iwFSTAS!;`Q{{(v@A$r_+)ulx;rHL^IG*gkmx4csr!wjy>^
z&OulwWh{z#P8Q>W`)m0b=HrUI7)ET3mW9nq&52T0Yu(Yl54Dp7I<-@~j8|!wHdH5e
zK%0s<FKL&-zSsT*E35R~xKOT_V>(ysIcUNLy%xD_)YsQ1_KrTB5;r#K=O|EPn_Ca*
zOWKoqxF@kwdR`E*)4Dg{bVfgk5YOt7Nc)_=rWdi>dR8j2C6>NG?gy41(Sog(I6{@G
zvV@|j)t0YAi0!llli#OJ`@9DUAvdYfy#CU%4rTww669`1{6|aUF~sgz<`68@T}vV`
zHB)uMUa9&$mi}5gU*%@!32lMOO`lHQ)h3{2nQG}vY^7R*s8_3cxc9co8&B-GI)lVc
zt2~-5bzYTYh%TzSSpBH(;RU*?7Plb$tD9;ThV&QZ26BH@#c1dfBO#91+r|^z*kD{h
zg6|rO+Y{St)S{GC#ze4vMt8KJ)+lX9?1)he@E$Yv()_6(j3EHYHNyk<ZW}gq_pYIU
z(nm&ZikK+W6JtUnTF$cOV|vT1k?F*iTbsblD(f*6;Z18TW?`fC)p5ist>-Z%o2=uy
z5ZiA34b7^yc9+DCTUTWg`^<V1*H2l8xQLy%E->%;d%JJK&lT$vbmzKtJl^`>t%?4`
z?pt4oAojP_6Yh#_JrP5R?ZE(Ir8bw1*nHbujo3n4eSm7IEeBQFWAj3OM{Ebth_7v(
zpCR_G?F!oclWh^E>ZVQN-d)>YZnWn&+ve`X{<O6ZCHBxZel)QsHVc(r&9rZZ(OLEp
zNOO+;43K8ppTX)q`)vlCy>Ak&YV5i6LaBrHB-}e}KZ|ku+&(9n*lD|fhp+5cyog<}
z9|J<K+Pz}X>s$8oLy6t9|A`F$u(ugS?16nA8u>4KJ%iX|`wJ+-YaXZ3!Ph;m;mB+c
zZ_MWf&*-MaE_)6kXsfH9#d!B_c-F-WcFR*o5$<>fLV3^g2|)R}BLe>BITjDWw|<4=
zLVH@ScDxlstimxLxL@zMoI&gZM?d7d&G81RUhPOnn|3><VWestbx?#_M{fjr%yA!9
zPCG^-v~L_5p1AKF-@^T6$6xWpt~yE(=ncng)S}dReK@}L3!Is#SDEt=reUeGYAmsp
z&P}Mro6dVE;&x{?3S8}6h&JzX9zZgOoSt-F-E{h*zkfQ5;P;Vp1-eyI$G0u9(mMCi
z?ZtJndkNw+NR~!;Qq-4p(=gVvf9p89&o6+*6A>8HM4_xT7zf*{$jN@9<NurpzJc<$
zoK593UYF-JTFjCel&MiF|DZ3Knk#LD9b=vh#k|j#@7AN$+j1IS`U-g#)B8Z)#oRoW
z23GD8tpNq6=4oRw%*(VT@ViPofut(5k?_A&%YgrnwLU2Or`jnR3l7*zN0$EWP@LfF
zD2gi<z35ujgy^8qSfaTik>~>1qBF5~<YW9OxljHIP@a@C;s}4nAM$6aIa~A~E>ztl
zBoRKBGBVoSq0So-ku;G;<W91vx$rNqM$}@OX(ReCs(}&HIe~7)ZpAFc9iXqGYTJ<#
zSM3^%B--A<cd>&Hp1zI^DR$MV37VVuF}-4L)%P0kHn0z1K01R`YEmEoF?kGXJw0;}
z(U~#_Whs?caov;^@UcS11rS>&tAYE?G7aZ<%IQ=&W4Gks_ehR@ujKG+B*(u`asvA$
zqIMg#k~29Zk;>B|4DC-s!?7r+-$Hn7YzJ_I<ADC=E2u~+Y%`LI_ys4Uw@IS08a}8U
z-AJ?R{dPpV&%~7XcoA<}pUdcS%0ws8L6ZqT?5UCNMkSiQ97r_eRvOV(SuoJ{1GKCA
zI+*Em+eUQIADE=qqz+)sl#VXMie(sqRjrgSA*5BZzm-_ITsn@}I{5(cub0(8{08|K
z>bOM~0cBg|Aeh`HzZ*gQSG%PTptwiAgdXgbX(;PqnTd-><OBSK^NAdeK|CYd5*pN5
z`56K}Cu0H6YqBDl*mc>J3aD<#X=v4bxt9<_U_Xw~9?EBX5}U2{Ake5e+H=UIRQrA$
z-k;@K3C3fErfAI6O6|=QV((}vDEzzH4&12J`o<F5slA1`cWJel_1)U~U}B$W*=WvD
zt<sy=DXj_aeXYHS=kKC+rx~$J+LwUlW$k4Y=$f_~q21D44S~P=S}_uRO}~bcmgod}
zniu_Vbn^{;J!-L1?*@pi()|H|4f-rZxKXb~_S^L_h<=AY5zRiR&xGw-eG8$GTimiG
znKjy2DR3iVGPT5rEEz`BwSvAiMwELLm4Xk3ZLpKj@(%)~YJCaldR-nz(PzmMNU%iu
zb|N-gCId-x<Q*I-mFw}znkzdY>v^&px;$TYhR@X!?$n2J6uvn-<s`6Oat;u;Tb_3k
z+aujR$di6Vg!3Ai25b9dSA19YOB<m0k?aYOe=NrXj0a>-dMngH8HNF`l_9{>A^A2?
zc~};sA)m^_N#y>zM4oDvHWf*fXvgA-&DQ=1A~r|M#LG~sy~pD+SGycT%XwNSc$%*@
z1zVs=fb0z|9)(?~?Zf>=S~~<<rj3S~#acD+zeM}3139eFD#@sEM&nw~*55>1OZ8g9
zud!H1xz%!gPdKsF`lV!I+w^*oWSgsRFC!DG&bP4c)ngRVx-X0&TK{{R2|f{e0G-KL
z)Rt&=0;*Q<EpRY>20fPQ)!tMxkxls0#V>|=JfuwrS3*HSPIhK`QFeY_p=;2y$+0ns
zQ!}#q^ynFxUQpml%+D*z$}1{#^~}u4E-1`$7355vm`x|mim;wRx#^kth3(?TMn~dz
zOjJy4RLAJp=yoyfTt)f$IfZ6QSR?afsO_Kk(xvdlLh(=M;?waTchT%0E>(W>fcWgZ
z%$%v?v;Og1f+xAsr{qTD<>zHZWTj_hyNV`F&CPI4Yo8U78$O}HH7R|{cvnVt5jAdb
zVb+vFS7!Q@ocuypkNnK3xeU62L!V7@6&9ptW{oY%O3!sACZt3p(yg({`QxYNWQ`q^
zKcVP_^eI{9;#U3%{|zgF@&AQT8du5I9u2FKx-V<i>;G%c)gvoo>cpzw(><hlF}+dM
z<BXjVejTG@BBI+xMYRfwj*g6tj1Hp7i-~F<9aD9xtW_Jozv(g1XvTx-k47K1Zr~0f
zMpo6^AFkvivuo{9S!Sw3soJq}bI74-^dEYkA4-*_X4Au|TIJhj-r*EkVD6{Ifh}g8
zBPrT}ZRQwar?;6~j-<#A=Hnx&a+sO?NveF!e2Zw1`3uWkkEUwdc9{#0;?TvTsbo0f
zSStCNK{Vd{oaiL8>G5!xYxX%FB3GKZ$HP=4J$6sbRkUtn?x%G@nGhSydj}hse;==_
o?cQhBInhFSFBT%sTuaLSC+f;1bM%QYGF5USOnbP`+;YO_KPuu9761SM

delta 8420
zcmcgxcXU<N(%<`>yU)Ehxi_?s3Mqt;gpf{v&@pr&2}F>R00HtKKoTIKJWwx43svyY
zTj*5<3}Og`5+WT09wN_26KPT&^7K(u@SET8t#2*=c+0ikTAwbRnKOIu*)zZS&AzC&
z7V4FY^!Y*Z)~?`N(pBC{h~ScVA;#7a!XbYDmmJ+z2ra_95xFhWIPWQhyzEY{NS{vZ
zvbFRkS0@{}8vA6xr7353a?Pzpt|Z@lc3HdiCzoFqxw`ti50^!4ZcZ*U)<wQl-$m@R
z&J8EuvtHyH;<E)Vo9Y`!u9sot%JJRDE^9(Nay|AT*Yw&*O#13%7X=_A`J@BcYXXpp
zJnTjGx<KS0SM?)%PXI2L;q}Qb4aB9=)$T3&I39rO<UNh-lYzKL-k{LhC13W}??Lu8
zKlT^JkbTFuy%eIFMdjob3i&}7a^3UmO)iVY`eqWHE}#&)XLY(r$g6~!?o*=$*|rh1
zNA9qYBdA6i7F|u-(??y;LHMXfh3E}xjD_t>CFrr9Ghsg?p*N|q67~W@S8wjQ19q)8
zWG8#pLC}Q_$?jM)8ulFOn%>p3DeUqFWOuLG74~B4wWX#{1<tmF?d2PI79Xwv`tbMt
z2KERm*|q%cz^<QQ23fp1?WH;_VZLsNQIo2%g!_5H-i56R0l-2&>`ZpUK!6|@H6y!4
zAp1Qs$!;0M{$-}i;w@##5{o7?%c&!kRIuAm#Dq1{38aPFPWo6Yt6;%K{kMd+5yEq5
zV<D{Dq`n;9n*FIWUIm3&!ftoJriAcL3@7HgdAQ%F<?ZBfPYgGossIK5Nz>QxcMc;0
z{YEQ7I%utp5oDWFhc5H++Gge$0kV-<WQ4wUg?eR~pBX8(vS3<o=+)A6x7PQ+QkxoF
zRUv*FMd?ZZDBLWJ)n=MC=*<hnAz!!K6tcD<#5`JA_<viRzcv-3qX+pd&XHtx!WNsb
zA(-#^SRwq{lGi=WT0{W)k2d#NGoANosI0L#B5lLXP+O3kWVW}3kQ~Nxp3TpHQlt>y
z(JgiFQ{$zz4sH;kYf0vn9I=&Y^_Fy`##`*lI7NeD(G8^nZqtbC^=#BN(kCqr6&Po(
zcMo<OokiacO&RXyS@&kLr|IUX?fMFY@~zIBEw80Tpe*r(5>}#LG-MHbx=_MOtf9-5
z_;DcQHkt_~cGiT9ra4q1I2|&ITB*d?dXV>tno9h}`^Rdq8*t3IeaUu-;OcNi5Kc;r
zp<?JtzUDIfEq?H9q9IbkL8&THj~J~)D^9428|*$bXiAJognW}Ysl-I0lM+X5kT<GA
zKI#KGoe)rBULa&DM|MSUl{LD;b*KsC_70G3szDy(T94CEE3uWYEFqYcxRd}no-gx=
zfc*m}SH_8cR0W<|{UK}6kSb9+7_yA_$8r39j9fbxgOkVy-fNFd4~X|lpdpkaO(X@P
z*&@lP)bWS?Ybs<_zHD1h*hP$72xFjeJEG`;Rl<iO>s)|uJ9rimf2ll1D6XpuAEP*z
zc<#^ydU%w0%$GGMt}1b!5%T5ahWNs>h{0^o7k1Vl$j<Elg*}5~;5oxhDQCcAW8s-a
z<E2C%O}-L+xruLU!bKlj`I-*IS|vQ`iBh5$J+4X=bG~aCx?$bmX-|)d5;^o^LDh56
zhwS;7<v0m{-~dR$$X#W?$8xi_aaxc0YzmiJNq(0SNBE;5hp6Nb%URaviwhaR8eC0D
zIzmr$Lb|^VX$yy(-2<|iuPkA1m(_yj1pRs`;R=NeW%+>R$u{sP@WUk{1Mo4KlPC*;
zy~`8w7dzxbo&qm=1<1qwJ`)D}bREd$R48$U2X7cRt{r#%GmhDzEmotMVJ&;Zp2oO(
zFjrpD4?HDj;~aPL@@NmZ6kptym!~=4+0E0@EeQ5-_7um%e!wIh!2CGFNCff)nLH79
zxtJgZJU9ybKWzf}F}GuMJJ?Pa*H^}L>%n#J=RW<wxi4Y1Kj&)Nvs})NxWgDMWuE)-
zHOJmWxU|8L!x^Wi3~~_D^B7~$TE}YfTaarwLWCRh--~Ms<Ld7*n7x^+E4kkTQ*hv5
zHOP&;Q}%=H!Jew!VBh3^ALr3+P0y|ppD-S)nWURr!sD$$j^<QGGfUi)ng7RwvCx4*
zE@4=9alhNY0l$|G@)b{TyQ;94G3=Gx#bmDaG*>yE<Cy#g9ODRmxvk?tG_i(PFZ0=_
zjOz@-gZO`nt9k5(O_TXD8+T|6BT<{#aF&U7jl0-{SDP{aCvdGRxUavly}B{tEaLY0
zGpWyZfM*WR{VT3Jgu#yng<WDf!`_JdH;=1~Wy*ZX{!z>fJ72uTi9oyAKQ#olWHxLV
z06U)n*Z9f<ob-~q@K4~@EM-~F)%RrobY_ohB4@gasd0`ko62+iKKF7ylc+ggyqaJ5
zADNyn7=z2aS}z6HEaxdW$W`VtiiMn9uTEI4!Wc~8W)0?coaVQ3y^H77I~AL}8G}#x
zC#N_Xp4Pmnh`a9Koo$lg@5`P?{3L(NXD4UCe=-Qti`(%%Uw?}WYs)EWj9e)bc0R|s
z)1Uc&EEC6WaAlsn=@bv!M|}N-K&)ml8`iqR_G4O2;hOqLzLH<S*-YMdV&S>M^t{QD
zGrPbul5zFn{oA+&g<j16g}zwc%Y>T5p-VaIQygw@PpsDA5a$`X>Vx3v%Y^O1RsPI7
zXE4;)eXzQnSN*st!JN=u_M|ap|H#6g6%-TvZ;g*+rq~Ux=|yLF_VJM9@k?jp))X_v
zp4Z0eZYG)m4vQ|WAnCCn*?=o+&pa6E$E#H!m-F+i_=(%frADWb-z7XkvD|~%IE-_=
z!ht?%%YJ6VG7gl^Jv&eL&@?mPEBG-v%4hfSsfj^Y9nclBAJ-kEU^{~$^?H!O9H$i*
z<4WMr{><$mOtG@2*z_A$T$c}AA~G7{6(5^Pdkpc9){uQEgdz6zft<-Z*R_FtoBdO0
zj1BQ~5~5`=;7PQ{5Kp<4I=8j1iznU@hK0w?u=R89=mGK@B4+?Rm0ZU|?(r(-`2yy_
z4Cc)>O4JbRnWT!YS7H^fCOhEI=Jx$arws9o)0#<-u_4l^NJGdJ7u29?kS{}UIEcVB
zgkM$29kn12B*Nc~-+%%htrt`=(T6X-$t;QDAC*R2KrrLcmfO_OiU^x%<Os9DkdG-*
zLxfS0gkL1_-w=zKx5w%uXdd@za9`MW`N~A5TO!euTtWqQ!I;)*0vXy7EQsz#X{z{I
zHApt93xXw|e}iQE=kWKM7D+OrGgy|{(M~e^9{BQ?V`#ug*I|v+s4R4Q{8NMEUss}I
z@0|i)r^&woln>;Sx}@gIhB&!Q77<=*y}W=YVY{sDN2)~b0zJy)zp%DX9*iTkU+zHz
z%O(B|Ssjz_BCWGB0w7+J<8i?CwLFdaxF!9-$2D4CEN;<sK)G9c2krYzt0dB?Jz5}|
z{JHkFPU?_09C=>TE<;_{enymK`oD2txjug&sTKM_G+~2Yidr`6>#LL6q^DBh#&-P@
zC2H(+>As!GdsdHhC-tSiJ&4pfy&G=2s8=Gzuk_&n^^(50J*kI!-&9f`T3Um-A6dRe
z3wBuQ<0rnv;s;Q7TRZ{R9*Z~K`?_gI+L94+of^&G7cA=l``;~@t~#W@wN%4z@INgx
zh!*OxWfC|wS&hS5k&30+)Ml&PoIIh;QMp;;>2`Gwh%QpuKBShatH^qVO2N6+YVcrE
zC)7z4c1~@_U|v>VV~DP*uK4;^-Ng%ZTb->({8!(r2{aArks1T${-6$Gu0Ay0qkGkA
zqZ!Sn+F)Ejft!sPjY)lMQ~=5nV+hoKBM~jAFcvi;^@TAW<UMYb(fp|!h6$3~F}!i^
zq45gpv7x}#UyRZeF+`|W#(Ho1oNCR+^v<`|#apr1S{-4QSyc$BmDUQ(!bWT108(45
zHG#}_YtQDSc3ERk{cdY3N$Q04gF&QDTd(8zmsT@|)Me`l^NF9Qs~*t0Wo?G;+_m<>
zTmPeV66pKXx|;?}{c7!q$nV>lA%|(UN8Lyj*<x&@X4__Jq~_UdAk{+KR-m-k)&=!_
zVS9zpU)$o|AoY#y8?^g7+cZqo_cn=hk8O=yn8$zF*0&<{Z(AX<cy8;HN$QpD=ia0y
z+wUXjRC^lAoMAr+rkVC8_}Xf}$%M1F?nqzz?78$psl)b`)G}3RuO3h8jQ!oNq|Vu&
zqE~;j->O3Div0i>dfVP59=(2GKl?VRC-w)Z@F#nn3{ubRv(U(&?bYxAytMBI2$S5-
zp@UQ0u3*b_w{GCU756+mM>pNObSHJ&ef(Rb?ztOy!5+A`1_=LjuL<W9_h!MQrZ_@y
z-z>+Bp7^a_;<(V5K36!tLBhq3$>9BZ$K`>fK611{y*nLKfckF7YIMHTF#;pC&tU-w
z6^;%_^tj_8qMUPdLu!9_w89g2-Qf-JZaN;fCUx6Ufkf{)-T~T0&Z~s4OU-fi243@>
z0?*Sz=hptDmO9r0i<Qo3<h0A#9{}%mPDPtPckV$kN1PJ<`QGV){{GuJ4EO%xyod{@
zdGtsmRpjvy-Cp3)pI!+Jxnc3flcJ8(NyAvi_gj0?d42&b9WjpvHBl(*bBu$n5H;Bk
zCH?P?;Cp~S{2hYNm?AH0^f6TyQ>8|cjEkVJner8-Va$?#nD^OoGaj_nvIH-Ev8;}y
zp2^3Uo0l>fv+SCt*(o_SOX~rGEYiNjz00&iD5_ZNi1FQlKR^q0P-_L)PiYSN>F0#2
zv_?R`1^_4cDnN-zKrdRHsYNn9D}iM0Q$(60Yc(UaNxsA%CHKoaAmv$E){yvT{3LG>
z<{Z(Dv`|%B(f}BdN5e@rxJ8{eqK4B%8qq&eL@fsY<<*FtK{IW{y&w#X__#K7D&e6&
z$%Zc*kW5UX!c`+X2EK7J<*S-F@bo2hk0RN$I+~mOE4_Oz)%gne*1Z#Go>@#THMAxO
zF{&T19^X5i<YYMluoTHU2xZDExMPVN6+mj8+}54c$1)B3_sBe|*C>^o{9eh~mq|{4
zpXB`aOD>>XB5RjXA-R$x5~aKbp=%d1YW4u2zNe6|e|r!&cof(lx`aSdVfT?q)OXk!
zw^Nc#Xaxc!jX{|$bnvFtI81rle7tF$E~CpSL(uy4A;cfP$@_(C09mz514)K_n?^FC
zF9Ia4L%Uk-K>IsAw2@4Y1F<K`7kEl1ORYJn_hlGfoTYLCQd%avSV=9Hvk-Hge1!bh
z%iUo72Kg8`ej<l~Wjka#Lhh93`%wQ?sZ0kI_sR+AL7AKjSS#fq9Q;B)!=G@D%Eg$@
zi!zefpuUp!AX1lPYm|9ME&`kG$`%Bmx+hD}s;BZ9F^0%~0;xTho!gO`t~EvWGqlZk
zl!~;k2H^c!tW{t<mT12;A+=QdFoo16Z8m`4tZl)GE!vC(QhT&j$oq4xl!i=|YBz#O
z9o06WImfiyo}|9idgI*JT0Wk?t6C&lc1^2-fw-wn1VDGR%Si2kHlil@_f&fyg-+71
z0McoCIC?WjPpVI9u6_epEY%x=V$1Zm5p9D$0U2)8OHutUeFd`rRL?}S59<dIyF%YU
zEaVo42T)j}ft3<BqJ~gQjOdBINXA^G-x?#<wTz(PjbR(?WQ5-*QmXp?_=%h%4ZMC+
zr4>m`lO9b;O_#}F(hM1iEk*JMezIoDaj1HhY=|z;mT|aqg~WC0Gns+koIP?V)aUZu
zEK;TNvXj(a=}HG{>5quGe4m_)X#3@aFjD366)-#?n}Os9<tUKxkZeY8g*q(5FyIx^
z7koM*7vj0Aln2p}Q?jfhU4K`iPBm5g6wH~X9cWEzx)z5mGqm1#8H%)G7uY^i3q*To
zX|cFzwpIgbj@A-WF;{B@VCQL{;`|3%BP2RsTOLGefwmj`|4_R}%rT0!)fCjYs4>>l
z^_6IAkzPUkH5TZATP@a~Mv_{gU+hY1r=Ai`u^D~)bPAz7zCrXVO*2SV&Fx3B`gNKK
z-cffCIy3NeBFUWhB1n!r2Of+spvO|ZH<ch0=ZIgrc*|;@2x$<L+%zNoE&97_LVWU=
zf!Uqfw(B1k9TyuN_d8$4$Pr_P<m44(m}^7Zg^tU~ONhs|=-BA^*!YCl#Q21`#Mnj|
zh57j-3Ni-f<i$isn|}=paF32A>-FDeN~m|^+^j)EbMmsqpLwhQpIW0=?4Mekchf<U
zkuh;`(FxIU|F0L<`)^Qm{Q*<5M(0N5<>zHbWoHe{$;inYG-Ax)><p?X<8?(Dzu!<e
zbWHBRjIoWgqjDqvGBRUm*66`Rw!#7`Jf=rM_UM9`L0O|mjEiZTT`;^be`HKyKz>x=
zP}-fJpBFPOfAsKzky(SXX;WTQVRk`bff*Fx*Z4mk{=>6@jsDZUe|XftWO;;J&F25z
zd8%*Vm?0(WTQ08S)xUpQYI>(${d;yw@AO8Oc0uv6u}xx=N?ciPvSiJ`JyEq1<C3D{
zk{ZTE1iglocErcWHjbk=Ta@I_k7(dKh@JzD{wac{-@%R04k0Q^cI}T;^0;~R@G<#=
zxv?Tu3twSAtr#m0nYl+&<vp|fNUCNlHa#j+<T*35GF1!OVSZAXq6O_TUy+L4Wu|<Q
zBA1%0zDSj&<|C3f%oaye>3>tsC3(ZVdNft5T53ig!=`tSrBdKCB!4h#A5WEQ%v_Sk
z&GO@s@}l|u@eujkbe;%Pi|B3q$xJ#CB4?VJ^nGr=5F5+|hijNCPgK=>%FRzs)Ki5E
fglK5CA?L#rRpl1*<%uu~6?!sE>s4;1ob>u1yLk`Z

diff --git a/Debug/Libs/sta-core/src/bus/spi/device.d b/Debug/Libs/sta-core/src/bus/spi/device.d
index 2fd3ef6..07b28f9 100644
--- a/Debug/Libs/sta-core/src/bus/spi/device.d
+++ b/Debug/Libs/sta-core/src/bus/spi/device.d
@@ -1,20 +1,20 @@
 Libs/sta-core/src/bus/spi/device.o: \
  ../Libs/sta-core/src/bus/spi/device.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/spi/device.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/device.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/spi/spi.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/spi/settings.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/gpio_pin.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/spi/device.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/device.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/spi/spi.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/spi/settings.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/gpio_pin.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/spi/device.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/device.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/spi/spi.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/spi/settings.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/gpio_pin.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/spi/device.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/device.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/spi/spi.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/spi/settings.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/gpio_pin.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/bus/spi/device.o b/Debug/Libs/sta-core/src/bus/spi/device.o
index 0ec24a8f42a8e383891b342dc6e5f29188676d8f..9556aa6eb23dfa8bda45c508020c1a441a9d2791 100644
GIT binary patch
delta 8900
zcmcIpd0ds{@_(N9J<og2fdeQzf^3T50tZkw4HI$66fjXsLy=9zi(rCY>srTsMblnU
z(aK!Y)XXrK)N3x8-ds=-TeQVoDlN<0Dz!V`@&2~Ie`OzL=ACDmneTk(!H*q!TmNaZ
zz93vK-5T+M=DMFDM8q#?LM%=Z!Xf_eAGx}R5L)YiWO6HMl=}%G$I>RPZD22U*$xJf
ztI<ZTl)yZ=G*#1|T%U)KD=nykUDiH@<Vq_hS61K@xGZW_XL7yS+C{#cpc?jBZ^w}D
z?6c$=5x5>Mo06gAdY=4RY0z$VS@U|5Yj6;`W;91)a*j^+tWabmQ=TOIjZmZ_dr)rL
zsxagr=M<2=Jru#^@-}4e3`0;U&zfK90VA_g$<-Kypz{5v$^N1lqRG^Fvaba7kV1r5
zRB3sYkPEZP^=-33<Wd%EU?<wOjJE2&-gK>yFAzq0pies4)-u{76BRkaefnat$jr9{
zxSHgXC*F59Jc9`oJ=Nz`*ogzke$00Z?CzOlXZl9sh8L5_e!?#f_Fig;p5@ySc3Ldi
z{rs|EpUn`$;um-TXGg;J4>|$+1;Wn~9P}CN^H#D$nzgxtkN6Js5fO9~cDftck<A{$
zPHIbbbdVb^eb)?A0qN)Zkf%c!3YH_OE=zhC@Q`X4*`34Lf2|+cJs<g3yOaIIBY)4j
zN~Ot;Zxsk}h`Qu!eO!n)qz7;oz6Xf{E2S3}Y}9K@Hq{(<ojPHCOX|zu4ZmP+F~Xex
z$ffPJeIqES?J!BrcATUx9Hqnp<l>eZXQ3VAfV!>Td|*U+F7_3oiCb?+H7(eCo3Ykb
zZB90)oqhdQ(gBCCK1mCXc^Qu`aQEMg3z`zr!uBA<e9;;%yPB_C!?g2}=05t^YJO!6
zx1EWk6ujKVnKoNzIl$~`i<WoI3R{p2HfP(yn!Zg)IXv9YP{-dUtlejryKG?!-fZ)N
zEtsv3%?Gw%pMO!QlWi1CMq$~*+y0H&*52IpH%h=G$nzQM>`X(5dGw<fVxQY}>X%2j
z=QJYcO7gz>KPyPeBigejONia%J^WuQ7SK<)<x?n+IM0hTDxcBP<^Nuu&C7f`+4Ccc
z_^V-lWDkw%N~7DH(vPJd4sPi~8Cd31Lxh_|upXYdrkh&`ArS2rE&G@`Za|>a&H3bx
zFd?3z-Ss$|j>JXuc)~blYYdt69au^Qc=hn?(L#tC`u-Ig7x2c`;g3<v`da4^AZ_}Z
z7v1Kxt_T#uSWl};+AcODVyq<FnN20!CZPUF9}V==?0#Fb#=WgZ>VSJB)Rjld&B0%B
zj)1;hVua|5I<$qw-c5T7k&Ak?g~LR=h1ykXr}TD{pu2>KqkT<3bAWE)D59wcotC!v
zu4IdZxwNgmuEtTL7oDJTb(@FMrVx8{i<i>8>9}sOE2F+QVWt~Og^njC>aA>4DCvJ$
znyRqE9#}hW@n)apk<?rJJlbNnD7Oj4wAZ02BgvfCq?0^i9&Hlp+CYzyZg*40AJj{W
zMR#*o#^*FpWa>?n`#<qa1O@!>J1v50Q{rO+R*662Am`A7rNk+E8kKlJKq|4P1acES
zYfAL@hdj-4*8tedXdablXeES8iHXD#C64fcX&UU~eCf2Iuz&J~#NaBihTdT%zTq(I
zd|>~B`lm!w8f7K6b%g9o#8BcEfuY1}^aLq!mS9w33YDisC=Ig`<C{R{66DGyHaEq`
z$3q}*@YZ?M03{Cd)rzb1%YkPA2WaR8y9uY&l5kPtCc&k|ZAN7$bx4WrG*?RWeiW=V
z>@$R;5>cG!Tn-;l2#>29XF7ERJ{IwT!5m;OL$|*j{9%0H%_m?#!_ZZ5-~;r_K?$E>
zkSiIL@?hB6^l&Os$g=Ms*gF`xG{#_sA3WaALTWC)+Mg?^CVnV!hlWv!QJIkKx$a6%
zC72r&%>ApP5mF+9W=e^Tj8Ioj?hAT4m8fJa-MD?7hQqU;{Wsa;8xPN5Mr&QM3m@$h
zAnTe#meTu8{pK!~FdL$nTz*7&CA>l*d$8w7PuOLQ+@2!X?F%4>Cqnx0ou9I28Ozrs
z{3*P%l9Br)UAV|Kk-N2o^SaK5Q@GYO?5}1!g0B#qP$OSt;lM)~zjEeH?|}%=-4pUW
z!#<5hT#4XkAa^mY{hhGAxzrAX3i1C!6kJnT_M(wc;v9p2lS8)Ril5{p(pzFRoBKDL
zx&1y*!7KDWP~A+fUK}#E1w2<2<aQoBcW&I*(eS*(cTNEFT;eUJSV$fgDjC@ROqLpY
zs+5?=ou1FDy}aOg1!E(=aEFZWfIP@7>D3;#l|7r;o?wILG3G}SPr*T+pnA3=)3ECD
zX29$C4d}_s^BDH!+}-ou*z`Cjag!OakK5FaSHB6yY5<RG2G`V_D=uUVHg?A9KNyLl
zS+G;NWqbR<*1JLe=3-zoIs8@~u4MXMLiFJ)b}-1B8HtD7*U>y?Qy%q?`@Oa=_Rr@;
zPjUDkc_2UMcV!AUr6cc8O2tkpo1{NuusDJFf2s>y=XvXo+zub6NssREdoghWAJK~I
zj^#b0xPsLTatz<ljziknGmlfL;ab=65ble>Z5#Lv$mAQ+@|gcwiCDPG%Xxgbp+7vO
zT;EQn;biW&C->fy8x+e(B=SVGG_c<l2icid9fM)7<XYpot!WaTy^PjjP)}G0d*Z(@
z(`_bqYX#T6EE>z>xbEkebP?RYmHbRaa=N?Ne}|J;&g~n^2+d{xW$t<&kEK6Xe2yD>
ztr$1=;kMpxNw!NI34!Yh%M7l58x}+hf5=Uo={;t~0H)#HHt_$E0=Xs=Qs=-klVIOr
zdVb0nT;|nMuDFV);4~Nc8%OEGWONPTUl^&qaQGN^E58u-!J&|opM}hO3Q}VXysWUh
zFixSoXB2n+X9j#CGo~wh{Q1uIeCLFGoVpwixtIrUJoDpmmj$kwoa3ilhcEa38u#@c
zr?PDr_I$&YUE@86L*ZG?;U!<HxDlOrQtolmn>c*$X4tvzX~=C%URMI_-?`~0hcW;2
zv*G%Nf$hgMu|>g?#4T{=E9P*0L-XMG;iPZzb@_wfX~{Pn=X9?Vt(5qVd;AgaZ1Ds<
z)r|C$LA;;KyVHsJ-;y)x%?y8@w;n3Srq}pVH}2vkrdTV^`cfaPTA48u`K9~ik*78M
zH+j}y<Rr2p;dv<olD3e1im}Y-4Erh-M*L51f{#x8KCkkH{Q}oIi91)uNZjN%{~p(*
zGeTc7G2i9EYr^l~{O&k=kZ+5B26g}^J&IAh$l(`rvnq11T7a@$Vn0_96Tz-lka>L3
z?iko_G5GhH&)vDNi<rrhv6;gA|4w8ygp(5*L3<3*j4(6APAbC?wL>7U^3Lt-&mx=*
zF)0z!)z}GP3K{Svw8;?n`05Q@K?+a&)M)s>Psh%V3i1^B4KcY0_8xAZA2)6h^L!rj
z;30SVE1DWZtO~=<IBsPvuYO5XHAJP0tN)&k86uzas_O!~9aU+FZZsE$Nc4sr)e=|i
zrA8P+HifiOrw!4-&r5&u(5p`S>DM<^ti%is9LFr#I}jc_7w|_OPMzm=FSNSwq0z`0
zV%-SHQ0frnOT0D2xweqYn75f^D^bgBdX@)ot0z1|DGB;pFG*5Dh26)?5cw@+)F&9b
zxD`kt@p~VV$@{^tOa~g=BSa_ZdPcS*mA5{M<d8-?$&zXiX833f)|dv3<a2$f7BwN)
zO7i(%F#9hRA^+)eAV7Ip=HT=Kc?vA8l}{61YPEbCPr^pI2n?!|7ZLM)xgTr0<sNFj
z+9S^vQT=MKoQ~1|Nbc-L>V({oMygTP;lw$)5rn=Z7lV#(XrE(kz1B$WQQNdR=-zwU
zDiCwK);WyS4($l)`al~5Vtt`)gZfhY8n@KyzvI9%eNYLh<@#>}F#l`xz9?p`{v04$
zr{5;#85{Mr==wW)C`S8){vlq6llo!mj;hzkAX0;V8yTL}Z791@-v<U>*WY-G)GL<U
z$4PCnya*a^vGngks?PEOzP4E=1GVjz71Vb8{gb-(0xEBDi8{^Sr!DUR_fIWb0Q}dM
zhr>wyXmP{d8<u0iq$aC1k)&p+k%X@{SB)+$7h1I%T`+;7t75RFM%4$BTB`0L>*Z=0
z&b_W$QCM|Uy@$f;T`H1>OMRk_CXl+IHeyb{R>x>`)n(NkYu~B<K>G)kJA@GVNhPD9
zuNVW8NWE^ni!E!6`zY{D!yWC}Y%Bnhbw)DO9^=!Fqz)L~siZzMDnQ;N#sm*iUm31I
zu;hv{4U5-}mvH`uaRvu}Hy&V|9vU&IVw!b6rgwogvzXLk>ra%7s<jSpLF!d&HD+P0
zwYrGZdTSn#*=T*LGpViCp{RbF^?5v-N3Es9NgcB`B8!vOOlv&pPpp1seVDJSvXDM5
zS!>artJbN#Nd02Hi*oN+2gH%OZ+#h8PqFzU&~)24Ksn2{$3|+d?Os1p^KEZ{O^a;d
zIJe986Nc$S+qfW7=WLzP=g(~ZJxP6I8-wnCXWNO)ZrG-|FsL_e7c)rRww*>6_iT3H
z`_T4D9;wOpw=kg7>?09=rac4!O?zK_ZLmAgf=%{;$Z5B|&9kKT+d}};A-h+5QpfGp
zc=+q>;fQd?K24B1Z!dm^)MfkSfiBY5>?;P7`q|!4OzM_BD4*0_`$T#z)o=C@2B`;j
zzZRq>xh+8pr@EcNmKknGkmz~$CCy1)bpHWaTz2=u3-qmf6cJlpbKi(Y{^-6Iui?+`
z!y`ydb=(?6YK|jz5N2VCqaPTs-0>9>Ug0P&Ahp`D67#yrF$1IZj$^--)HX*10NUyB
z#`)cj!D!?Ghd-Ee#8HM@>K#uYwND+pF%4fj<_D3w=$HgPTy}hdM89?H1{SkCb`!oX
zRqc@iycT%e#564OSPMcd_4otzzUt8yIc@crkG}+L^9Vr|J3O*b;X#it0rz(v!QDvR
z_9#Hy-#yOb_;k;|C6k)v`6If$&~p|&6Bu&CvelgowT>bi#@{)<bs?SS7r@dR85q=V
zp{%ogN!spVMC`A2`p=GtEr35Ji`r#Ol@6UgrpaJ>%#B&Hwl#gtmbWPlV~)H9%FmVK
z@u0mfn_|LO$QUGbS02XTJdn*W%&zHLBHpk$nyU+`8f_Tj)@r|_s1@2-#NVP(p+fD`
zE`v26Yny2-IAO1WxUkt+fD=&#P@Eciksbw{b4PR_IXa;`$!dAyF;eT~RWDL|WNS?M
z3AsASMfu&5HwiSp(d|YG8BLOgk-KdiRb;elM=2Pw_(wY<?hM_iIq|ROMtlKPXe5jx
z42;CVnRKdsY6!^=FUOKh>Vt5}SJBy&OBmzSrg;0(e!*(TgkqAJmBe0`dh#gv)^8nX
zKI8#_8u<$~Mm_f%_&?!iO!j2i5wOgX2XU1t+l(N!M3#k;S|#mh`DS??`?t#tgq*Qc
za`L+*XaBzB^mj|ne~;t>_DW>!G7d<t<e)?;k3h)DCd1DHjDpG#F}MPNMx1UzGAarb
zik^$#_OX|-GvT@<+5TM+AngT|nLY-6d)$hCbz9ntWG@Mso#06_H<kFqkpco;K%)88
zFp@3$<dSSX3>PF#OegvH4#-~5+ezlG$0SXXX9#w};{jHtNYAFEmP#8^s+Aisq|4;0
zB2ug5jgF*N%WS~1M!E))dRs2)LTZcr3a{roa?23vzuGC=fQq~1IrQLtISa5Jk`Hj{
zhcXM!!_rJ7)gWI(j%Q_RIH^Xt8D(CPYw*NfmAy4m-^y-i)g76EQMoIh#Vz+_WlvHw
zG+$&tQ}aeGv$R`9cz+ga;jQR%iM9X<FV)Tg_jOu30RN^o1t->Py%1u%)&@}Q(6-Q!
zshwJMB&oyNF|^_%ZHgbMliF`!*g37LH>nF+HCpzCHU!kXs9gg<SG1g9Qr9%QKlpb?
z3jsot^c(oqHC>NDZ>sf8`0LR;{c~WkRNvE|RIR=fx2@63uw|{Dnnr4?{%aJecl94I
zfBW?$+<id*l32(sjtQb`jdqI&a3l61HNl7*MB{8Y6X}={@3IgSyfHe_jf|MPnIzln
zK}l1kj@NIR+y&N5m*00HHA9x+y_hMz@QY}c?2PEMWgyU+BadNP=E`=6xm+TgdQbLf
zLTbD02em^^1><(gRk(APbRBL@`h7VG!FS7RElKT>dJL((QU?|PDbuq_?USFEkorI-
zW7_u1TVUP+nc0QZL79(%JR}V?<YRf59wg(cM4f7ywgt?Yu07~VYKGQVk(#Nc3?(&7
zTa$$lv$ZICSm+H*M5MWzA5^tA1XD3jI}BjwYd_=s%i19@V1f2tIH`r&Vr21(_98LI
zSfSOJ5i!9o0IL@3W80BhuBU;2@8~z;{sXf;7%cM~iF&;fz@sLE@c?;0M%>^=w2Z)T
z6gI<4So$;I8RPd9$qB=Tk$h=22-2Ij=wc}y(d6%*9zxO|a?_7AcgHkOb!LniQ&w73
zP*qw{Ug^y3pVdAwb6jCbuWsGr3dW3aW>%C}m6TUiI=dH@m5!+_agHe)H=>kwni;X(
z!$%hsRa7Q-$WMsFe~Iyl?c>uD+9xC@COfMtD#|L&gmwX4Xw%5j@)GfvM|!OC`O3dM
zihtT)9wPEDZpw45L%Wog7nO}G{_C3(G16Huc64lcMR`eVNkL($vufnH(S^?ODJ8L^
z+YTS&99b~7*jZRwMU5L!Su(cLSyV8#tfJD{t)gh$XeM62r~5zQtQ=ENRFYp+QZU+?
znUNivNvHC&DvHOImE`AE46pio!PpY>cwDoLKjW6r?i8-{&$ub9%b!qGa9z4H*T3#~
z_kJyU{C}@=b}K0yH^NLR{nZRB4XBG7<?RegOGu1ONRE$h9iEU7*FG*GoW?jYJ|!Ws
zZgA~DXT+O$Iq0VWnw}zq-V=>}VTMC{3DL3c)Dik0?)O)lJx*lHZf4Di9Qmqw`NRsj
z#+-gKN87f>Y&<z$yS~B9uFsYs=4<siwCe|w9nADoIdYmgkL3lDi_F;5IokaX%$H7M
z>+#dr+Wbt8c4@y^eg?PiJ(DA=OpgZIb<iBzkS$x9n;UXufAaxJi<xycN47IxJKI*~
zm`BgHka^}0XQS1PcuL<4YHXn$Txxc1Y^7|qLL4z8PWYG;8=D}5#%NVfz7FQ8<38pw
W@>$FajnTBC&P8htN6ff${{IGNQHtgO

delta 8963
zcmcgycX(CRvR`ZOv-T-DCyfviN*W1CfSfd1LT|y)5(!lUfrJP_NH75euXyMspaNTj
z0E#r}H3|e!1nEeJh>8j*9RWL_aNqnU_rCY;ANRfQ-S2ysPiAJ%Dl_w&-z@Th4>sxt
zHtBQ1<lU{|pJ<+++6obVD@BM70YW&%KmL+sX+mhRHJXrHNn?F=A!IRa(i#M%v&$xe
z$W>`0SJR+uxHL7ZC%J;^kSis)h+Wopx#Wr;Os;N0li;$bg{{c-eXNIk8Nu_}XHAMF
z-|^?kH6&;aTsGAzgk0NW$W;)$n_bo(oyfHym|WB9ATe30lRYB@8OgZLWWN`JROI9u
zWG@dz4syaEvbTpIxV%`O?46+qD&=wWvR-58bIr(A8H}KEOCPeosflQEbOPDegVUrC
zwJoZkaFmeKyOZl?&3@!k7OQu2+O>$b>H+?At&lqiBR!~EOR}xQX^%`&<Or*liN$_q
zj-`gj$RSTcz)W~D2^76qwI#4)dXe2CU^DFI?a6K*5P=(ZH75I+>TcNO)DXQ}Kq~Ap
zab)+X-VOHgwnA8{2kpn%0k8vuPr}|o_*rTNe+m1NmF(Iz>tDymh(`1g9{dyRmJYHb
zYCeTs+<@%pU<WR}Z-%NGEl+eMPoq#2EC*0smX@KwL;gW!SXza#|4I+CJ5~8tc#-`~
zmA_?qiPB{1dxL~HKwS!WLS27Px`49?sGyH!(gzDR>b0c<)f{@2I$>QW^+oW8-8MHH
zq46(e(RSO1Lnx?i4@u4TDM?*8-zOFz7e_O<g?79M)NO~%Cq{(#Iij<#ql<GkE!f+d
zan^eEorHxWv-&bR;1t%*wBVfFw(0_}z>T<|J0UG>sddcp)-c)3eAgPP1=ltA(#LA^
zvNg=+TbEMsacnbfwpOx>*~u0ye=v(|!LqM8(-!Ktl8|z`yv|X_HxbreubLIMPz7%X
z^J`lzw)UA%Y_+O=LZwc$Q7{>WWtYGG3$uZ}j%N)e;0pGhPo14^2=O}o)^oAX5sQ^D
z?^lSN%gDR>zgCcxE82TjHz9VD_t4*0ETEro^rBEMw|8h$A-<%gYyY`Clb88)6K{)K
zh)0Hb*d7w)sVzhuN<WT%b8t&n%E0o5j@w#A&~0hn>88U`n-GY0M9Z0Gh64x`IO041
z5-P;AwEHy9wnXA0dN^Smb1#NW`VPvW0({cECsWe%>H85j&f$%*fi0+Inbye!Nc}YP
zs-rY^1HCTB8d_D-7Fvslv5f5a?o>h&P5#I9ah`tHOlfG&_iCV#+V2$sb-hYCoc!f>
z*2o+mBSbsYq0JraZ|x*R7V6RF4ipI%YFC+^(%Vgf?h?XH`~1Fif^K0b!ml%(mbQd;
zWQ)XEwCzy&eCK>U&nt|wx4D!yiP)oCe3X_!<D*;b$~e@8Fw+gCLduDWdOaHzO8S_^
zPlfhP!`capKl?0IQje`xwZ(2xj>5sT*QqI^f%&>`bNR7()HlR)ogO3I?odVx>ZQe^
zJG_)}rZt<ouk!i>&qQ#I|9+=MP;E-=BVd(i5f3?m9xNri30Nhb5Rgi2%ZFS}&zcf*
z10j8CKyK~@xtiut3BPC|JW5m$FO~S14@}WuJNVL92Ecyc4~fAg*%>m7!@OS&_RgA+
zRvKj`)}=zG5iyjwO<*YT4n09iTp$>g*h{@tB7lZji7~#ASp>QAh>d>u*w-KOK5son
zd{aUvYAEpsSLT%gy9)<6mJZvO(~2Zql(<Q7De)_#vWYsR#Lx5&D$$mMmB+&N<?yvQ
z(ODecl?%Tol`|bT1Rte*Ad>@>GjvahI7)=_fp?yPozKt}ap1q!hsQn;@*9SCJty6P
z9!@3tvP|m-dm|$^hLgBd9Uj~BkeY|Dc5(%ih#yKM(-0{!usvif*ImG=_;G{$xPM!@
z1x;zDlvu_*XvWFa;&v1;mV(=t_yYDkr6-keV$ZV)u%BbJmJIgbV`L)agF28otsv)c
z7xS47wYUY<iSSBv4S{UIo{u}h&Sm7b<-v{}1i2y!GL!E-#hy7V-;wag@y;!b+{u>0
zL#_($)_Kk=HkmhZtykDTiR~JEh2VrL`J%^M*#O3`ka^R#H_mqShCIu#@1qeXp7(|P
zEdp{bQ#*r8eTh&Z{@1LBg-@a&r?Gv4!N18N^SI(RoWv`U*fWd!H`4)o7f-<{dLNX?
zW^zsAki+W2b6r9H90)17aUs0=1K(MgMt+aD!4&h)#-;)WwlkAuK0Q@R9OF(;;nj2>
zc;;bj#5Z1$;V#GuX2~>0&dQ$KY>%~JHHrCA%u`Uo6Xas>gHo{S$>451;5VRU)qpYV
zbGf^h{ITg(P9mP`{*&7j!K-1lvD%Zz^);@k4p+RCt6bI!t2-Hqz1?8DnJeWy7mpa@
z2Ob7?0*BwKV^c%=vxMlwSL|SrH!>1Wxv%SZ%=U8s>T|yrXJY>woah-2|2+@nSNyJw
z<)*yM``b0cPAZ#Z7UOX)k@<hP4P0k=YXeRtlWEeTBm7;NI6+mk;<|@%%LaD9>Iw!q
zgl}lbA?@sWol}{`wJu?*{uz$_*ZB>Yz&FHaGyhAIun@^%vib0_p77*weVdqu6S?2s
z-1{!vpka(e5>G^=f&F{jkbmJ-?K#-XxYl~y))Wa(Iis}))Dw^Cy&?WPm~P{_TbH=*
z&!e%tjT3r_NmqmWw}79i98R}_{mIOXi;P(@BQ%Ts5j-i`7TlA?6$dcjS12SQ%56=G
zBAe!)dsCNXTdw{`K0GiGTbFaD51ASBI9MYdHYfLT5tB&gzy}&*e=<Kifoy-pt2tcp
zFrI=VT;yYp(vHdK$?Ae*?sUlg+^t@@uqy^YzRa(5k7r>&><Z~)g&fZ~1@N9>-1Qp_
zcri1k9ebR7XDr`Yn1fRh%z)WEcw?9!tvw9Uc+T+)uEW8-zr%gK$EmCvh{IuA*&W`a
z^T?HP_*P+9ZO3eA&XaPFlU~l@XVk>%5}v7bOx`_w&yU>ng9ANS?$w<GFt9zCCLPfm
zQOqrPhOd~w_4Uk#zZxffo3HED51yKQ!>63?)qHqvagPu4&fsU@nZ!s>4~8Ad<=t)0
z{2#;_b@9SN5pUf!7`Dlm3hrXK8=l&n^_Sd;4*d93@Jn~A$`gw{@ga~UoJ45^>``qY
zX$#3tjAheSup?_R|C{*YBaz?dZv$YD<XXpY=hiY3@r=Ynu1RNvE-*2-@!)l%i<Fqs
z5%N>MtzKW)J$Wux^VzE${v0<eKLe}pqHK?N$`#}@HQud<g&us-!x-2%82l9Gb93%%
zDKq(Z9>~4C{{teUA)+{;{<OyszJ!?}Hc=Udc(XrbWHfHu!2VLg$q*kUL3%!Gj)lGq
z_<6d{5ce4NrCdQ=Ypi}khYfMLCG1oMd6@i$csURDBW|A;H?A}Xp2^IE=A3#ZC2ELo
zL*b9)R=&xr-x5^~vBksHU#4S*Si*U&Z38=ksx(9@&4nS7{2^CI;)=)BVM{;A4)kUi
z!mla(J;|elljrCJRZM?qao`u3CFQ;0`70y$Yc@`u<#x}tdhqd(UVaKc1oC<6kRg^^
zAOjjg&SBn8Xn-p!xlPaV;BEDWXE7zA#OowU2^E@>Kr$i<GU_D8&V30fB;Bq?vdL5M
ztG$K>r`6U;diu7aAS(M>6v_UTc9Qu=L6{fvFjyncYb0N4hi;F}vXUH^04QJUhy15X
z6QH~)XXEr7>5YSBvJc^<R>-&TB&?Tb(1vn(5ixhkeOTKqA5rtw9(g>E>Q^7h{q;#5
zmYX_|Iw_apfvS{iapH5i-j~$(@*L>+o^}RnYqZY*<p<hfbnioLA&9wM`wKGLp&db8
zpJ*8%);HQZsBg6^xTQ>QhCiGZ=^6Q?7V8gsVg6U@X((ou{t_U1U%x}lGuG>?(Df~P
z0L`sBsUO7aa7x#K|7m?ABAwUoAj1oKN8*I4)IS6R@9J+qOKP4ay)~%~mJ-l-v!yeU
zN|jr-<Ld*<$3ShnWj?*M`1zB%HWHQB{gOJ(-)Ai!0{1U0s{s5J%P#{--Lp8b_rArB
zhE7yhB1p|ps|a6hmKsq|D74vX#GtVhT`dD!<|`K-yM?MTvR<q{uSM!zRhz=9qiQ`0
zJMB?9n9PgHKu5k-H!;yy)c)s4T~m{=c1v{z+CQjt;<fQWm7t;XjCqYoy=&aZmX*d&
zC~&nQ(VmUQ93WY4G=bV<oJu9N-w16+>Y$Mi@*Xk9x=39%JiWk@>&9Fx-Ze(y{C(pb
z4*p^MoJs1bksm~AiggO6caAk>FsZk#*D+*e))jS0EwRqVEUdCl$|JSLS_Wj+TRY*E
z-D+JNM(P9WI7#ZLHRlCVpIJXc7N@KetO=wqT6>tMLjybox%Bb9wG!>QVI7xF>St>s
zp!S<}9{vFM)A|{%o@8?(&{W%tfO3XykB!tU+r1v7-mtw5Hoax*511-!aj5U0Z5ulA
zxvdfU{H4v=iPU$t7tq~Xww=iAzHJ}=jzs-ryV#c0uQs13QV(ru!1t-`WHzaZ_H`K0
zDfR&fKi%$+fTleSUu*3eTCl<16*=v;hdobfpWPoY9k6#zCUwF-2@n5idmtj5vriGE
zF4><0DX-bT>Wx{vW1s&VsUPjf0P`<)pBz%Z+h28(dTbwJka}Y8QJ2&N#{#r)vg0VW
zOmip<=q0c7^b)D7Uf&^$YhJ1ksheK4h}i0m*G)9?p4Vc$hCh0(2q!h!dAlE}QfJ+M
zn1uz-XTX5P&N_`qEp-kaL~4a|K|ZMs&Q~#7Tb%o>q&{#CK$~_tZ8*Q%xd4sa?+gTU
zjyQ91%V}pTr1pjLA*SJ5=kZ`tSDhb$57(U4LrC3pZUq)ITw4iWkDBd@1734n@tB6U
zT#G@7g{~Hew8S+OAZ~R{!4Cl+xcpJY4p)0r_^Imx;J)SZ>p<#PS0BXv!*v$Nr+Tkx
zLTZNh_vrRq@7L&=z>pi3tzKlPB^22(MsR%VbUM#3fMrG^83wgmDC?mBlD2yo5&OL6
zf7=nh8Suxnr*;{WrBkPmDY7p;=Ee+J8B1R?<sC}HD3!NC`B`#|KYhI`yJNza%6ugC
zyF7%!c_RB@m_1Xq7)nl+YNOkbny<ZsxMkXpC~B#8t|_U_8Wk$kUhONe=D2p7#)1>}
zF>ztdp#Ud*7(j{F(2JJ2AVk(m^m9aXN0PJUwHBn_mp6P!?UA9F@{{s%V-Mx`i@Zso
z@r{l@5zx26Kyo*Dkt#A8rVs>19RAYIaQjlqT0H*t+(_s{6&i`d2m>Q2vpt<k9$lMc
zqtD_<Hg1P-O}<8Fn}*ZRDyo?kZ(m9RMmjZmFv<2?Xv{pS^Iq_+$NQjp|5Qxg&|B0P
z_0nVTf9wrR_C%QqSY}9pt4tX-gwz7L7Ia!J|B4GX%DdRVT`nc$jGdB`uaKPmF3IWd
zmYn|{$pw5Qk+sLzFS(LWB}%CRp<{P4sz1iy2CqfJwKf3IaGyw$QBj~!^buqd_Z4;~
z-jyVi?}Gp-BT;6{@!(DCCum8BH_}O_|BfzqPxL04<tF}cq#E8HAW<hWjAY$*StMh7
z<ATP;ElIZC2$??4PBQBnCTW5^3Sv!^KVxN*^u~`s3#APymC3aj(nWG%9;xN>S}Lg(
zvO8c|DMw>;Hp$X9q&CaTHd0&Us{Yh}wNnlO6)WWD=)o>|5U?JQPjKl$*$vJ^@-(LN
zyfl&H1vwfCSIS)|^SWFFq;AMA8mXIdB3kvEY>QF(T|SRn9?F7Fq^4;OWIvt$p@`HB
z?RFmCpSQLC_2_efHVp|c)J}k#?`s7Bezi6hC)Q}K5n{VmA5iSjR$<n6YJ($49n$Q0
zh7N0ctCKpVHO0BlwP9UIeXSj>OX?eK5vX}py90o(YqN>W>W-Ec2>$)1)doTn^lPn1
zO~p?eG%xxs{CM=b9u!Jyp}wsrsWSan+_q95jxDQnHy*sLdJ|;7P5%zf-lrGi?)~}&
zVj;IU#)qyo8oot<8*#r-6AX6-jk6J76h$(@)0Uv%jnPRCGGcycPqO|auxqkxlT2!g
ztN?4K%FE43O_RA`(sZft2hj}q7rKU?onENARPM*L%#sm^xmY5c`cS6%lG-kNK<$v@
zz_^`qIqs~G9vyY=k`oYow~WDUdt{p!QXk1j!0=<4+?~{3c_yFKC$b?P*nRRBFmJz1
zX+!E$*$V@CK(<Fij>|orDf|tII@J{IE|@b_`?(#dX<DWtHC>AvKx&4zs2kWmQ_F2c
zs#J?Xq*<C5)NE}Luzy|K17P3KZs7cz+5s?Nj`mX+skz$Q$YP#WLd-FiYO~Dnm|7kH
ztKQZ(Hzc)KPXYh7=nV-_hS}~1mU$0Fy*|<4k#8p65C0a#4c-wMj^W7dgO{+t4R}U+
zJxg+I?|~#=y9|QhpE7juD;?3~AKoq@=@+@_w={Rh)QNAOnw`~?{_B>U)P8hsetL(F
zIf?GX1b5;;__9Y1A3da?uq4~`jqMoqazSBo61KS$+(`*Z$q9{<k`o&zG|3)SR5ZLK
zJGY=P-t9KC8-{qf-DFk$XC~IKVa|@V{aYi}`nN_4Oc4K8I8*Z)G>A`3bSJwL|6c>w
z`&Ur({4XpSR6HWCu&6LUE`LyNL3Tl5-tf_b^Rua<?5c{g|8c{pp`%CSW{+u_A2*`G
z3nR0K4k{i@L>pB?g~#_Q$uBO6&l^-c{N?x#`6VxoDjFF-%2O0KYAEe4Dk_YBxv2QX
zl97Y*@@Z3H+^GDLQ6=$R3vx^1OGXWf%PT6*r=Ju!J{<q_#{b)e<`}nk^Z1gH1^?oG
z<_qr7CjYFs|2dWNgYLq>7XR8=0x);<kn*ICS#<+*axycr();H0PR~kj*R^9<QbIzr
zgcS4m&`0H875K;3Y@C=9mzdHhF*dBKWwaqFDWPd%k|;OIddG)b=<U(y<w=C5XDknz
z{;(Yn?IXm3^6^LLAL}z$nm?WBE*F|@PiDvm=G>D@<wG;^REB0-WllOZMr*Uqe0-|A
z9BHPX&Y)doBxjhnNM1Bk&Opv2dDHyjOoo=Z&#ZqITgRQn)}v=Lv}XIwn&)tP!MO~1
z#H=_+yAGI+^WEiGv)}m)xyD>evak7w<ODPQLIb(M9DSj#++vnph*n(_g*av&yiivQ
vEHiIks3)^czshJtu8h_q7n!-0_3$t8?Alrx9Tanv{<i}>uz&mYck@30Ck1c!

diff --git a/Debug/Libs/sta-core/src/bus/spi/settings.d b/Debug/Libs/sta-core/src/bus/spi/settings.d
index 6c4948a..dd3ff3a 100644
--- a/Debug/Libs/sta-core/src/bus/spi/settings.d
+++ b/Debug/Libs/sta-core/src/bus/spi/settings.d
@@ -1,10 +1,10 @@
 Libs/sta-core/src/bus/spi/settings.o: \
  ../Libs/sta-core/src/bus/spi/settings.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/spi/settings.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/spi/settings.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp \
  ../Core/Inc/sta/config.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/lang.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/spi/settings.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp:
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/lang.hpp
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/spi/settings.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp:
 ../Core/Inc/sta/config.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/lang.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/lang.hpp:
diff --git a/Debug/Libs/sta-core/src/bus/spi/settings.o b/Debug/Libs/sta-core/src/bus/spi/settings.o
index bd4c05c298b5ee31fb4285853663e8297e2a99a0..ffe24eadbd1b518ea8196ba5f106f16c339c98f5 100644
GIT binary patch
delta 7916
zcmcIod0>s_(tn=!J<og2NzRENvLUO8EjihQ*dmf3N<u<WA(DvYHd`feb<u;;hEnB4
z(OhaPEozA+wo+6rUzKW$T574KSFJ6&(L2A<?~m{A?^fHHdFNSX<~P525?%dRJM@S4
zc8HAG7<yT{J-P@H8r@llq68rv;{X1U=er4^we(9Qw=NCgBZU0MlU%L+GuUM-@g-NH
zja=>gbK%mI>PxPrjmec1P{uCnLRyj|hLNj}|75r<YJ?ZLZbZAumlZINeb(d6$v5Cx
za*gs|4VO)Q=pt7L`L!_tJK1I3lnR$Wxn6II#ALEgc6AUklA+znelG~A$h(cmUKWfT
z<k2ByZw*3l`DzQY>w*zf%0yGs!`&)}To(cnL7tBy`&vMEDTIebjVY}Za#AmH-3S~^
zF5O}^+tIE`v{m<M&<ZCUgp2OqkU$jjYYW*S4G9Awx2KWa%%>1`J4#Y-({LQ@h{0sX
z_)LR+pM;*<zF`eMrqMCIlh1nCeUr&f^$DYxazq^2JsU;CK1ns}eSA8=&S_0{cB4M9
zuTXePBmaFk`zCDPfMc+KoMZ8Ghs2U2GyuWmdOO)+flpu$Y)N)xfCnzfZb){EKwsGF
ztYpUr0RwrwC)o+XC|=G_BD-@i`#U{Hc9#(LAIK!T$5VeRB8a8uQ-3VA!_qI<oNqbl
z9!^}s!NxNQ3TN-EfwUAGLzfEcPXrp4nyscKixEVrS)3$kDU5EzQq&h%>X?P4bNRGn
zxk6I2{F|gMyh_^(Ve4xhN4eHJP7JbTSg$A{ey2k!gKk$DENkc{VGE8I!sR^a6aw)A
zusjwUk(jUr1_;rlel&F!-*H&QHsL)plET`3W}2~vpZw6wFnR|sqlPtUfn{xWrD%lB
z_(NF;Sz|1#-E3@;O^#7G-Ak#UFhW>wZV<Mlk67#~xX7Gp3-wq@lc75_WehSm*g86^
zsYr{(q7(f+SDL@r!rZ@7bxIs>1Nl9%Pl=a(AqN|fm+~NMh@(n4vLRm~<}2ad4{~5z
z$l1*xClX(jxb<|u2KytvbJZZ&JL^McQ87xaq{b=nT}Q}lcLS(Y!bOP_)M+Ko5ucQ(
zAet%BDHYQ2fSd@l#Isbe61|BlN=&Z@dBp~KfjvGPYy;J-gby`YiMROX94<2E8F+lT
z$g}CN&wA4%L05CFe{e>n)LJE`^niSyQ+biE&ZQ11v4f^XiL0FG5)S_oy$4EkBLXV1
zkO)Jy^8S1daGH@jOAS}z8Qy<44R#|&?x-Q$^l_^NT)l|%w28q_41^uYVLGx5=?_mG
zL-#4;5lb%v1sebv%~v<$0v0f4jYHvoi3VMXOs>0-Q;BK{&sgFXo$?dHtwbxLloDqc
zq6M7YJO1#TrYTY)hat@x4m&v*(mEJ&J3VE@72bKB0iPNTPks}~i5(zUa}y^p8)kBp
zPq^Ltc+Y!igj)o0$jJ=d^`SUcIRvuK1zE(Gc4Cmvvj1h8GhzVme3p^3b8CvZS$}d`
zfi(L{<T4rOvVSAn1$@H;zTqfKw?79S%K#=Z#pd+G;c+y=N=#zd2Q-J>AqTQEJ!?ut
zaF}C_VgE)jDzPXWvWlhA4EAjXe*mX`hAS@PBpQcd^&B(lzMEc5B}OtVoB8VIS@7JA
zfXohs%wtLp=fNxB&Q0aj7r2+3n0g18Vm0(UDe*ag6<wGs7wL^tq6eqwH4t{S7i1X6
zE%J2ZV-)>xrV(PAoZ_+R!=C*N<8^veXxNw^jT!3JTxBiWJ-M1PZq~Ne*lFYN6Bzb;
zOvY99;eW!^o<k3n67{*QWvL>MKGrbX_i{BqGf;cE5q5@sJ5%W$Mxq7h-i2E>KNA;u
zb!Ex)9LnKG>hMg>hTI=v-gWxA{Wx+AU;Q$7cV=%a59YjjF}yCO#y)TOyKxI1a(C}1
zz(Y|;-s6OR;@ppPf~T_vY2(1(w}IUu1=1A)DH*>wH#6ML9U4YADf;aLGLElk&moH#
zWM59Dlq=gY9D8mBLr&mVZyw*UoqN1D7yd>Z<|{ty!RfB!>KpT_%@cbT+qlPe?#C%6
zQ3r1R8&7G)Sx58gMrQkSoZP)c9M&bIH`|YxXz9%1C+U1Ox2BwDp-Tij^EjamUa$i*
zAlG-~H_pujxylP$xE)IvwB<ZzN7yf!N|D_AKX^PgG2m@D<j0)!ZQk=1*SePFcCLOK
z`?vTY<TXxoKO^Bo%%?XltR)uKCO~dZhHS@yOF2x>Xm}1Y27mBsKjz0W=KLM5ayp~3
zh?8sC1N)O1gO!=E*D~Oz`K^@Ppl*HO|Gg(kw|L&bM|}or6mNQ&yS|8D?{cP0CVQIl
zr4GJyCO@<x9ymLWTkt1`_h4DZDJC;=N0_jC_?~Ef86P}{Q*F60cR$|r1`k*rhabdK
zzMk2zn`tthv##av!?^4Bc!WICaM20A=(Fyyy@x<%^@8+bT$}KI84k~9+=2uCuzPTM
z7u<aH1@1>LzRuMj%fB!|0ytm6Y%k(k$8voy^3FjFwKrcEpy5<nd&qH|&=%gmk9R6&
z$xKe`&o0<=h8gDF-Hng)=!Ezp5ONOB<&W&S%oM9_0{=3;qJ%lTuroaQ0&*skYY_8b
zeE>WK^&sc;h3v*JT05?Fa3(y%7>Oy2M5PDw{{mm+or+~IX2WT|XfpR~LqGUWaDZ6O
z+UIF&_>>IB>hxzIYq{=IT)+(W2Q`DgFW)nniy6x|-()(Uq_l|t`xvzE8SrF2(38k$
zh$tSF>$J%b^^zeM(-nqzLO&`Dv4VFVWPf}lJYUin8zP2pn>7r9`_mpnH00#w@=wV0
zj_^m)dtiu`D9J6(Tj07+3x-(B{SM&w;Q2K8k225C@Ca?=PVc8g=`fQtiNe#bT)Z0L
zfPWfSANm~ZbWUq+C)h7hT83ytb76?b-jKt%aqcYYgdv>l+E0&$Ay)H)+MC~iC!Bl8
zAcPshfgc9K4(5)wOM>lYJi@t6x2S!FsH2fH#C{@(A*v`*L-e5{4e@JB$dOFjBC_ch
zR5$l2jK|681($>Ac9c3zA3_B$#mf*j6EdPcK#VS;G*#UE1|$>nL9kST4tM{cEy+PS
ztw`q1mn4Vg*hv;8HX=E)Gv=!NI_BhsYFs{kJtgZ_FV<l8U)|A{<W!jeRA$K(u=H(N
z2%0XGVf9HZm(rKi8kq|U)yj*AxkJvt+D>_M2&r9Cpzpio=oX|tlWV(@Iwq&#efmbO
z!hutA560trISO=qPjm0Y;%dzTC^u{Gp?zDlFuV#|wd=@in>IlwwO6af?+zC<FA(fI
z?G~<Cs6WJkMf$6Gq~6t2(1aEGD%7%4ZwiFo*Dn%i#u~kx5;ZpHR!sIWy|*W+FZ2+`
z|G4e|7r)YfLW*DOs{!ga`k4??KkBddAvMR6PYhLSEu+zb^_D)wDphM)gRjk&DxkL2
zQjg+3ZCWWR5C5Dx&EH>I4gvQwmTANxb;*(pv~FA0Sup>1EOWuBN$LRNRnyOY`fJ^r
zs$@*5&}OKT{P7fBy$-s}Q!D64mRg{4!J2nf0nRN}+4-antB+9GadnV}PMucGF+}Ip
zXnb8#Rp9GY^#i_sP|K0UEmcRvbsKlp9e?_qV`NfXwb*!;hEuID9-zQg#;@SiI-?Vy
ztTis7*}IGh=)^u_PXeh=jX9W(L&heWKXuXA2eMr=QgH4^V;H)7$Kb!o{cc>L@l#KX
z>%OF>SQle>-EUi;4<$X{nuKc>S|{VH#=0Bhx6--|55j8eD?nzAbu_xP(Ygh*zuB59
zNgcLM7*6VctT%D|3+oNc$!Y6(AamAQf{D6djm98dvK9fn@2xdx)^+RjbW%SBS@(d>
z53Px9Nc~}5k4TekrQq>Y+f~!s-^cw3bed~B1DLkk7NNjTZ7zJBvSoB7^{s6%9`7r*
zbO8H<EfUSXW9x-Ey>GkQnbZT@*9iNIt@=4qPi%t-do{`462Yg~O_ceD{Q;O}+F!=k
z2X<d{V6DB}-JSGK`*3ekpV$k4{Q-Mo45`oUtMEP@w+A4^N&6|x#5sEwNO{#>jx9Is
zxdTYuvp2$o{A`aNOzM%{f`0yHKLTJL+dBaBi5^?yNxkObfec^wC<YJCd8RjUlfLYk
z1`w`#4$CHW!}A_;y6Nc#qPIPN#@OBS+yGX-=2(b_X1e1svUtal1_r$A_!Te7632QF
zf4Sozl3D90M!g#xO|7IhJ8H5>)j1A<M>`#>Q0_iQSvQQxA;;~8^m*Jd6zQLFoX0eL
z=je$ZTy}&fle+3yh==or<1nzOc6J27Gn_S0Z#%Ov4Rf9Ma!D<49z}O+oY??qqjMH&
z+3YMt5!;+KC~&_s4=>OU&gRr!w|d|lhq%8xEoj$NuVesK?R5g(p6zuaO^~L?#nK*+
zifT?F4dW3muui4(`~q116-|agMUl5Him_e8h}a*t`)fz&6%^j$KA~s4CZB*pQ)CG}
z=5C`}x+CdxnruU@F{VpfK7G9@Q}CiKmdEf`FOgnI>XB>&%0HG3<48@_swp=$T^kQ7
z&C?u+yHLABNvS2;9K>I*l_UNh?RXBUquN_E2ApucR=6)Pw>$6;tph5q&oTa;FM-xM
z17k^+M5K_MA)6+VdS5mK|8~jxy-6LD(<uexXW4?-%s0~SV`O+2qlVVIs05?UIcm8P
z^&z2ZMDM2yH5dNBrx8;%oIJ6?^zIvRRc^F5ULb0M*_veAMeRu@#tb6a?o&!wwf~J?
zT9tGIs~vLD-Bdr&w^ti9JX<qJ4&8yrZ*&C+@j_Q%J-&TEl9S}M2BfOx3fyGMvAE<N
z8QhfAGFhC9`q#-g9M~%V)s<4Jlbro_$?5Nqoc~VA1?-Ys!ERYaSsVK#SF&HCl&2sB
z;m32MiO4;m4<a^h3f_j^#tcR*C6H8PE*`Nc@eIk>OVUj$ehCPWREQ_Oa}*kv+#C%{
zTar#P!v>jI;3S!Io(ROD{89l#(=I_I!yOo|mKiwTb~(D0d?tZphTTpwrvQUAQC=t5
z36D-4NKKZ3n7{>ciW@mCl*&qKk^G$6Nw^#WA(qR-El919#{lF<awcfDUUs#S+8_s`
zZ*?-9XrQ*sc=TY0%mAzh<P=X*pUMq1HtL|fis}4H4n>Y%%UMYH8~G1Zc}?zl2K8T;
zg&2q%@-BMyP`-h7Jd&4@+As1jUf<WX7D)dM?X(}MYAqPm&)3dlI^NN`(3q(O+V0+@
z-q)M}ew8*K2Ucq%0Q6RE2h!fAT^mfQPU{gu>Yz5E3Htw;=7aa^3++y8Qm3@8pxb$E
zHF|bI3kNkXYdrwaHO()O)J^SO9C)ZLN1+pSM@LdqbwZ2AMV|%KX6oI6;R3x)Us4P8
zuW;E4eI+tnskcfbwNc+n*}K&yy=^c0{6v3DlcM(NC%fVv`qzFA+q}L-6YF(H;@<BL
zA=zL7q0Kv*eTyy>{D5H|^A$)`{yQR!UrJ-BUR@RO*FNJK^7SK52^F*s(IWnV=Phbh
zH#8?<B~tGA0YaqJp!&Sl%}I`m0Q4^!bU<{Y`gL*EFw=u$+PhN9%ZtYp=2wm>E3I(l
z^zRcNms(X&l#!MmonKz=N-Zm`EGn(6aHSU(k14Mxa+McXjT%Ec&EW9#kdpkuvWmon
zyx3^`6BiQ~ACnXtADbAL=&CF$E3Pn)h54D8A-2CiN~ek!E5zSji*M539wO{-hbnZm
zD}QWBRB2ghQB+ZW!5CNN=&F(e*SK~?Q6;TMmb*shj~(GE7*k1b4yY&^Tj46qA6r~j
z;YuqjtSVtDWDo4$(^XNPUs#k^S(IPmN=?a(N~KeIeac2u6&K~@l#Q(XXa3kCQ#K3l
z`d_%DahDNA1y!T|X6)~T1etLW{{M}H18WyW%yD{TWcE)?2nj1L4y)}Izrv_(-C>-s
zdHI!=wIB5T#v|+h3ydp`LCMP-&^<dPwZ9pYA7E}9a?qSO#IJTjZeO3;Z_DitvrT+R
ztv=xw&w!-ZxTx5~n3$F!v9Zzd(Xk;kt#L8!V&iK4rfqLg|KIcuY4k4G=s%4f>*lqW
zHhyQ(-kWXi+nTBEoozPQHqP9;)nd-rR;gW_Yif0wQkebfvZTMcv@T0KKF_>Qt`IY2
zdlt#rBxB4=Bo~;mJF>L8HRj|UncBrQ=9fD%<wP@dXO<bV(_&Wc>@B^`Pj+Ho{asnw
z-VJ8Ku1xL526NM{OuAa`ZY{f;QM<!sx!G@bq<W3svU}zP`mQvW?vB*zs?8(2o6BnR
s9xb+?CPadHVp>Bp=3{SJY^Ho1DIMmRk0br-HVW}iNl)KjfBx6}59xWY-~a#s

delta 8041
zcmd5=X;_uz)_$IM@8{in!`_Gr0*Z_xpfWpvLxM<(11MxpD1u><2r8(YGPkp6b|l_3
zOfyqc`;t&GR0J!h>XcIssU=Q1lv$ZM9m~$Tm*@QG$9HvI{mRSMTJL(MweEGVwY&V}
zS8da8T6ush-x_#HI&b$7BG8M3xw#N_@y9>%U@sxGaIenfHc5T3hY<3VE4kWxr?Shs
zrv<q>TglbMI}0vNJxnLp&#lOn;8Vmd%TijBBSw>Jp!XcO%&OFlT;5Sm@}>JMW1l53
zlzjc4CfBpxo8Yplvr*)l+?HJVKD*gvS(yx%H@OzHMqsk1iR>~zL?m6FBzuh?LXk-n
zo3_>;G02Zbl3nYE$K{bQvUmF9Q7JnZnkm@%FoRr;E%AbMM3Q~g=SeAqi&^CtmIyh$
zAGxl#98NBi*)pRG?V3$nO&-nK;lwDy#pK<bKos(%ne2e(gJ7@iO?DfPv9P;PkfsjJ
zr@?MDoa|_iMX-M+Vakecz6u{sI%ewbQ4KqxC)vp!LG-44HJ0qYo{_NYDQD9_kFK!i
zwkJEob0F-`QA1Dfy*OI}yM@nT*e5H@Ud}-=<OuY^W3t*tc2LVlus4O19qQwP3)T?<
z%wa8Cz^<~89p?uO<gUJCcl1Z{(wRVZ4}bQ@jv)Jq0QT3Vk=^I9za0_8-1o7+C6&WG
z*xy)gKJH8<F5zISmkA2Tfb^lXloL&t3d?N*4NGk{(UN(nABAQfO_G*^=r$}x9Kljd
zI+ni3p(XPflA8GfNt19J8ZU%(kR_X9ZF2BwvQsUWl@Jf<kV>W7RVvF>bd#{A#|aVT
zxaJT7@A+VP3N|7zVV&S3gm2T)R9Sq-Vintjdn4#+^Jp|;bT9ePNYw}US5m=z!?3Kq
zQX)LD8Gk4WAy?^@HQV*~rSBtp&g7<)UojzUYO52rr2l2MDgTkid~2Y~O6m-gT~m6J
zvBlcWF_V%so6RPozw1fkzBR~siL#??A|MYD`;_>cxUIx+9rDX;$O_`95*iVi_IN_-
zgCU1@g1poQatrZAiOalyl?J=91LPaSAdfVKOs8a&_$L)kiBGygj&nAHdX;cd;$y0`
z5_Te_5?MquB|?%Rbr;B4Kuav3gq7$-Tv1|m6UfU}$dB3M!jEmBoR!F<A}ev8Z|=@X
zw(Sqk??iGX_NPGp=uSg|uI5~?a72X!h7uF|K%OFME0N1rS5bwO_>P17iUY0T=O@uT
zP@+8%P>H2P7$w&8{(k(xVMflCvB~EBXL@6gCnNWnE}Zo71a*oMiNtv&Rx$VsTf%P5
z&&057@f197F?0tQk2y3Ml-N21vKL?N-~?tfW(9%pkEKReqBrL~oI{z}8lLgQEhU^@
zLO7LZPLxt&FGDn&qr2`6&td8!B~lsElrgZ&{ULv2&$rB&&w1xL2K@a<tZws#%<l^M
z3K#K3X2Udo<s_H8IR~)_Y;y_=KUvDqog0N?&y9q<9tF9KFO6l8kFoy+>NCoicWw-W
zJ%UTKii;J+`}<MvE0Muu+|T}vY!Blb?(hwtv2?oe!wVR|1g2QoU>sgdEv&?JhJ8a@
z*wLAg|Kwr~;q3i6*Zz#bjbN-EWI41A>@OMo{v3Kc&Nz>QC<wx;or(OjlP0DT&oeCF
z@YTNQ@Fek*>jGhCGbOij;|=4=oeF_}FJHQnsrO4ecq(W-DN)O99Lij|;0jMARa(*X
zgIwhX8N~1AxjOOj0{u8Eae`?Q<_|lEJ+~RgYcy1pD2|6LV5nzsmSzTj1!wan7wa1H
z{1!J@6~lg($+){I&Zct^muXN@dR(Sq$s(IRer2{d<$g`!oId12j9?7bGL^0~65ToW
zj$E=OX}IVfgKTDczRb^$Gr|8t2Bb$@<0nT8=Xh?a*<7v3T-~_?uso6D>c{YgFf~rO
z!ynHj=)?Pe?g&pJja4EYXCKVD)^vxbhsOK)VGrg+a1uPT0w7};zgA9Wcr{n358b5b
z|2`mF@f8F3$vg(R1&8tsXSQVw_B_ECRWVr(@D0_EYn+AEalCqh&yH*bPZek1lvk~;
z@T|6SjT5*YVT?pqF8)G(temIxXkOjOY#+hFo#iT;B(8YC)9L~fty?xc*HR!Ca%t9Z
z-b+K^xyk|U=Q5d6;i>G#Gp?FJd%z1i6X6Jhwu9TOk^LD=rBJSY2hP|OiYtQn$vqr&
zPo~~^&h<BzyEuC*`*rS-BOK^HMk0^iq8V2lj*B*PE#K$~yFWj?n&)|GBs>oogDbq+
zhxzdmbN)1ExtLLTor7!E2m8YqgOzEp*D~OThrv$d-iaRw`<uQbonnHHk0b_a6mMF}
zRWIl1J)9|%%O0IC)%eo6!*MFW1u~n<@jE~7!ZMFT%w*&~WWsLZd)n}1yfFf&@;EVP
z9&b9$t@R#1{|+~sU^X-`O$wjJfmQtcXs-G-ZlT-B@JlY=79J@&cS=e>4vTU1<^364
z0&gyXC;#mB;Pg&7`RYclM_g|l3t^)DzyxW+@!sVc=W(u6IKN!pnZ!`%c;l20H(NwJ
z><ygR`@H{M-uaM!gywQs*Pp;18&ms1iW46PQ3(;il-bLDd6GSGOffTKQ^`T>VGhsf
zf&DoGvXP0I#5@o!;hEM1vTP8f!4oZlb4^c!r<##C=>faMh56se7d>ERx-lEV`JxG2
zvkil>wT>Ui;l9XY7#sLhhCfzk^@qI7d0UvO=h$D=2L1%T=QvNyeGGmpruL^47V-aG
z2JH|7Ud{(fiHy2v!2zA4O}e;Gpy}dAx<VJf&`*Uf?(oj)p0MW;PP)(tIbHbhZSxuM
zw`q?qY#iL;OoS5I4YHKxfi9XMC8s!NhU+U@(8XG=cPbO=sowB^#5_OpcxG|zn<-FT
zJnx6qAbOt8@@fdRmM(U2`MgHJUd~}H>kfM?g{6xi>I+>oZ3<b<g>$Z<O6Vfc9n!-W
z@-&Z^F+2l);n-UY!!y14;Xcd~Pp)V{0{l}M4<9bmO)8%*-lLYIP>3M9I7or&Vjv}{
zi|}@k=}g;ud_zYk6Uv+0DUe%n6a}HgL#i|>q5O|wG6Xe1hFAb%WGzC7{l8`;J8uKQ
zlD|zP`D8^WlEdcGBPwgTBsnV6Mlx@qC&_Vf=&MQBG?J6caCvDp1?yD*xCwsG+ycJN
zm-B(jQdt3(mdov+=?dAI08{H^21dfWvI=FWk)MK9b#e{XcFT(+N!81{C}4x!6-Me~
zxeQ?)mQy;DIwi|-;7fTN?eUG=2|BLPoa?c;NxKQ!Y}byWeD7=Cm<qL8Jc_(SdlA#&
zLv2+TQjOX@sPmenim4T*wlSn$H<e_QT50NnBCI#Pfn44;#Q>oVrc(r({;p{r1*&f`
z{RH$6n+CX&I%1maM4ucr-9aT!n7&4cCru9k>M2vZKvLhEW(*`%VeUr^Rh!MDQG#l7
zXJVDAF~5bc?dF3(t=6pQ-N!{6ip+y+=`H^L!u$zvKVzPPF1u*%1hjrISDDfOKbo(g
z-DfLLyjP~8sX4Wm)WrNkp)FApb4uxTRU1xg%hVk&QkAL-QLj`rIJa8$%^~%vdJQw{
zsPdxbQm56^Xrgm!7qy_es3w4IS5#N5eXEuriks@ap;UkUCzXhTR_HV7UA0=@h&}7|
zMkKgVzXVQI>4N}ejeZBkuGhz*1bg)lI+8k|m!Ug8(GODpsSA2@kmRbKgmd5PeNf#W
zbpyvA>Sw6^)FV9}NzAh>MDse!E%iuyxg`qMtgsx%*DA{~wBOs7D)4EO<xl{rcP)c4
zF}7NCWWU{#EJ=N8DIP=WbIU~>KVtF53_NX#M2mc7nT?KWv_ztjE?R2w?l+d3DAqMg
zaSEy1einCtc-Jzn1F2sv0?*H}J~NuseCt<+ySIn)Cg}94wH;vEWxe4^>VS2YH>oeJ
zu_*LeYp-Ndm#vWi_FHQxiv6Q?C4%_bdZq`dJJz;nsr%NMBS<~6rV;jPw(WV`InTBT
zX)d(g0MiWHWPH72`<)4A8}59PK6l$n+(~_8>ksVr+r~wcI%InT^XaHf!xP7CH_%#N
z+fqQvE4DS*a>JH^(%-VVW|R8G)@C@Vdp2(r<lnY`0hr%xFCpn!E?477&2<roaDht$
zc<{CBa$hIuORil9k-FmgR0gT*u4fU`4cDVU^at1P&~~?6C8{*nz7&IIvHdopc+DOG
z2CTIA18Q&D-v;s5+3OL^W_vF3-C}QTA+_CJK~q!hw0{jA?Y8emx_j-zdZ9%=vG>Fz
zI%>~E_-E`6%((OR6{x`_yS*o=EB5a&IIr8c0gEz63;<r@sDLVWIMEHSI<94rs&ssW
z>aKFk0YF<FrO0KwV>pu7;iy1@`y4|sfxdM#q4GM_9Y+D)edrj1a?N)u0#Idcb*T0$
zZguoSg)Z04@fa$~m!8!1o4CMINauM1m=A%NIweKk1<grXkDx_t=ezuON8mjq9(JA3
z)91=ZpwK+|1|{m$%jD5e`dlP~s5JUw`DhG%y(EWVqOF$xXz@4Y6A0>_3<u?ZlgY89
z=4+EFHnmvGK{GGYM&aER+UZ16Z)(fXzSY_!y#IlAFq710+8$~H4!Fq(+}ASYN#Gy&
z9#Dz8i1zOh3!F0-#*m!omPB%i)DuW;kfGpTy|fG<by(I>2>LJ5kJ!vNx{wyiJr_B&
z-<CtN!xvO?J>nsusz=_Y3$-ZxyQdyKVGMa<{Aup%v7?<RZ`@!sQ^$SnNp_kWPqK4c
zbbOaP6tIfFjH#aB4ZCXws+&9>^z9dff@f$t$x*KGjL!!lCSOG9N+So8oGt&|j8vIC
zfzyUuizi-_lUkEnD|54uf0c~2(`T(*kVqlzlpOso$>G;Yj(@l01nMPc&>%-s)cRh@
zne3BD<uM3ppswdM#P0JVUTjqeJOg`TDuuj7AgRzL5hNq-_9Gc{Q94P*{R9Fe48Vx*
z5dq@#^hLpXm!*(Qy@fKTO>>aUJWd4Sr@RsXMC+w~B!e|HS9mPWcUppK^*n>}r`l{J
zGi%UDv*bB~o$v_hN@|XbL<d&Nc}~Q%LMn9W>vA8JlW^GsLadW5!%3}|`vK&8avEq>
zEfcMzw#Z(n+fJEDG*G)_9BNP}Uk9xF<veuC0l9_RMje!%Xv7mT6EU8Y7ZC6%`5dym
zD&Oyq{IAKeXo%}F2^797SE3yE<Ryf5Uv9(nU7-0P{DoRLk}1<Xk^OQl65a8d7D{cV
zDz%ycq&8?h0Q^R62@Y)1M)W6DtJNXw9opB!N$u1s14tdz4*R11A8UCY^m#<{$H6bP
zaM10X_5gFUQ7Zv8FKK-M&{b`GOHwzq?{VO+whoETGTi~B^G#ub)DqJL()6#s-GO1H
zDQFO>6{ZjnV7+N2B7ED_9Ak5<$wJXP)izUmaN#3U8t&d}s!zl{^w)L(+uY8gh)ud9
zaQ9a*VVhMF+PtI9K2#ys2gS}0!Ml@g;f2!IMv$C&pL&A#>0L0Oy@*pn`K`liA(`lr
zh|*qBq&nWk(Qa?ziQe;(efEsDB%gHy^#Aykwu*Nsf0O8CF;e`aqmsL3Wj;lJ2gb!F
zPtDCs?VXYx6B!d78S@8U)}(@|&*m2vXBmNkDQVO53*%z3EiyVXHaa#gx>IaiOsDA1
zStUh91;tsp`GrxDkx>QtxlzxK9UGN1Wnx5OQDI(0UQTX)R7^}{Tx1N^|M%B89N^Vu
zV$Rs{`GtAnZxK$bzXvKUqW>Oncp2`&E`KQ&=btd;57fxYFC1Gi^_je^vF+PuJ*G+4
zA2*bYpE@x&Yg(7Qh>7jTP0AXdGvyf~TS+m&6g8wcZ%T30*qkW^)1!Ll6;CKBniN&y
zR}@h)o^}@%6-G@jnlhnyQqI^s+Ef@(l2=?(Y|IG`?)?9q{gb0tf&>2wOG5qxk;lDb
ztZUQxF9ufQ6SCQ1ESM2cb1ZhP-u<s-M+oLleYR#w!t@q3E`u6fT4ZMrO3zFkmi=^U
zW@@hiDFLz3(ecp<M&!urH4#~ZJX})Kp6c8&AgG`qsOI@ecDwOidYIv|plQtqGtRsE
zc8W=eh)L)e6CUums&qOwHo8j;{oaV09c8=1nhvIkq|tvx(DYOBa?R|m=gpd^Fmh|t
zw15g@TkSMC#t7drT}xbMtlg1DAGda-%Tgn0XSx=>+^E=@CTAHJcczn!*_AHKjoBpc
z8^?B~Yu=lUpt>|IakDX{F3oV?Z8rAT4bT#+jApyj<Rl|!H#TnFovsCJHMIIPt?yPN
zqdtx9eyhH{tTGPO2g{?zt@=>)9SzcJM(c)PdCW*^2-Un78P7GemDi0|8bVd&A|W~&
klNU8NjyAZ<&y9->p|ZfR?Fsev-X_F!NxA;_&;QK-093ffUH||9

diff --git a/Debug/Libs/sta-core/src/bus/spi/spi.d b/Debug/Libs/sta-core/src/bus/spi/spi.d
index d075995..07c6a7c 100644
--- a/Debug/Libs/sta-core/src/bus/spi/spi.d
+++ b/Debug/Libs/sta-core/src/bus/spi/spi.d
@@ -1,9 +1,9 @@
 Libs/sta-core/src/bus/spi/spi.o: ../Libs/sta-core/src/bus/spi/spi.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/spi/spi.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/spi/settings.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/spi/spi.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/spi/settings.hpp:
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/spi/spi.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/spi/settings.hpp
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/spi/spi.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/spi/settings.hpp:
diff --git a/Debug/Libs/sta-core/src/bus/spi/spi.o b/Debug/Libs/sta-core/src/bus/spi/spi.o
index 3a1d7f4e49fdbb23cea48c14bc73835c101e519c..6256e361dd943c2a9f5d8fb41930f30c6fe4951f 100644
GIT binary patch
delta 12348
zcmcI~XLME7y7roDt-1EzWQQaWQYeAYLP-y#K<HfvM0$q+0V0G15_;Km0))DN4TL73
zpmafsAR<V!;XwsKrB_ADk)j8c?|CMibH_Kn@s0cAUUB4k=6u(j^L^*r)=u1$|7mW1
zWG<|rZ?3$nVzTZDU8-qyx@nqQ`@jF`*RnNDuO6HTu~S$bDr2^|1fXU}D<yL7iNNf)
zv4EtIo)qcw;xx?a!~s%5bCk&O7tYteTMkGInM#o<?I6tdGzYW`_24mNj$O?#T`&(Y
zC}cB5PC0WCX0<8L3O%Sqjy5<{Z(0*Dvm6c6H%UN27%kG1@&W6@Xo{Xj+t!z-4SL}c
zz}_$_*X<U7{pG1tzcCBoITc2A`t&-0Ps>w}-nTp8T&R*q&c^ssX(jL24&z&)&4s2_
zG-cMXd`)jK0irvlyFr9YtnG!_M>xU=EK!3eje*yUkdpN<_8E#by2k-Qg_7xfxG@)F
zPvyY=oUFw~jL4FsIQ|kBH(~>!S<_#@b4GH>RU99fj&W+>4vw1*#<)pfMIO4T3&t%=
zMRWWIqGqH8*5UY2YmD2MO5?a_pr)CnLXL88O^$;?zvMWyL2XRRgkI#N43fYsTlyBq
zmYrh;x0*Q|l8De^Jfe9ejH{In;`lgMCWO%yx;_r$TIJ~jeQ;ll>y=k>w~cZA3QB(1
zK4S)p7Q1hoABj4@A|O*tO$)x<Pt(>3UpiU~9*@bJ!jBJ}2*24DH>{G^1G9I9(S_2g
zQ|v2NSoHf-u-x5yjiw2ACQx?|1sYn(-bf5;PQHuP?vXG>bN^yTI>L)ztEg%IKCRu&
z;brrz-NVsI?6P+`8tcEewVyaDI6te4rPci_*yWrt;)<Q-4DNHW7DNf9Ozd!LKCMBK
z+08Vq$kMdHlT$U#w^7jDR4Dhiq9JOJpRV{Rw!sft1C#4xLEWIj1TK(VkcXeK|5*@~
zZ69-nSG@c>7RQ*eS6#SWZxO6qC6JuOql-g@rr)$JSEO$+l6iAUf259PzGXLX)o59-
zE7rVgoWg;6S!9b}5X)H8@6X3QD~2}3QmYl9%mx^ue?JB*DwRowz|WJWX(4{KobO>`
z-nMtSg3I(RfIP{Eo^zTlak5`hASZ4!!M^Tl;rR^7=hwhRk!e<0hDk#;ahj=pFlnSF
zZnI2zOd6|+znP5W^=qOgfo9YoOq!}mh&cga^=qakWz7;rm^4?D3Yy;>0~Yw@IY&65
z>FP*4$`2UfwBIQfEOh(hVo@T-eo(ARnT_aHek&ccC&Uau0s5^jv9Fk>l{FjNF+Np`
zUwH$f&Ay2~2$|X4?(Y*TLhL0zRXou=a=+S`Zss(^<Up~VaA8NY6w=x6h`TME($zfH
z7n7sKD`3*otk?pRW6Ht-n*R}0b(=wg+GNmcnl?nJ(=_>6yr$&}pUKc^%J{0B1ajh(
zgI97AhDmeHErX&oZG>>rc7J&i;m;SYi#RP%1|p2(M9>$oBqX6vcCO|(L6kU)Sy@>X
zeP@y=b`6sXa=1Oo9a{WsZB3j0a%-e~Y`^8Ms$Z&af8h=({@p@NTOxujUrlQ&ciO+Y
zll03`cBJp3umxz<et(u84ewg{u+6{02<QqICoq=B?eBd<ldmI-DvJ_1$R)R|oS|tE
zqB2{bzvfHXIjk(Ml2r5eLXUrI5e%c`c000oXvS37lrBm#vz&4ldeZA6kdNJ(MVWs!
z>`w0__H)N|G`g-Y?bqZsyfwNB<#1CL!Ta4`PTX>Awx;!XISG{c_S?m)mf1R5)B3y=
z#mb+&n%4K_Bw3EPZx_$@-IAqg0ge56L4A##;a9ccy=t0vTGHhm;1rPp&>SfPHSKpL
z9Q<Fx^DQ;)UrIRfzk~zqlYWE5U^~V?RMfCr`BxHW>}>xqaltMGPPVuBhqcJV)t_1{
z*`>w*qap&;e@&hC?tg^kst(Y!>q=PSI(pl4*9kr=4r{frZnl3wVB{@0KnR-q<lm28
zJ}<G(qiN493mxX=B}$aE(*sJ0uJ*uyN+Q^v6Hs0pv)>I!5B?%i(+*?VH~6XGZH4ZE
zL8)SPK#59aIrU(wFUr@FH=wOq{?J_wP{C`bmk2CT3>`o?YAwMUE#)`hi`}D2+%{tL
zbTnC~uhiF%#K0^jt>p-XX;@N*^{xm}RTrWR{?sfX%lEengTjjyq7n?ZF0E7czM#6T
zlHeiJG#u8;h4D_sCPXeDX*p5X7#a?vMu05Sp(eJL3z5!B5F5opUoJI#N=yB5C%bNN
zxR`7A3JwXa7Kg{x%DsFnV}5~;j8s4AGr*o7oa;G`4kfkAX$tXnmfFz>VqG{~YUR*=
zq}ClRL~5QY#8r65N$u7QVmRU>wTF#~cUu#OsP&Wac9GgPb><*ct<;jy`lNOo&XiiM
zNa8n2i^~(vNt-C*Uz3RsI}@*G5(f?=I^cS#Rm26Pwi&*cT3BD=zXlW6BL}25svL2$
z+MB9YmQJF?t4^NNo8w378o>%bMrBK_Nf?|VwSMZZ(MUWP$j+rDBXCkXppI*;lr?Kk
ziT^@kpDDz9A;eG65Tq8JP5fgu@vBnA7D~ZbrR)hBq15WD_1lMYe5yNfm5=5DooK;H
zX?z%v+G6FFz!;7%DC1rzyf%jt8;J$=$_J|}bG*Hf7_N@4+Mnb29AcAHh06JU6FI*5
zIxz*!7CxI!+={aIU^0f2xB3vL<q}O5p?Gyy_jpPMDdWx{<D|Az9U9w?<JHR5pRC}x
zjZzSanwHv?3}Roj5UFLTY}kn2Dz(!p+$KIbKz%QuN87LLy{TMhBmJdT2A_VUwn=S!
zk<M{<<>XaL{!FLjALwgHH|4n}DnK=qhaM`k8h7B+PU^0g)HSZDu}huc#amQr`3gO)
zl;S<gfom*2m@t!=qN12Om*a-bh%@lUmf9|KK&iEAON_xgO=>4=5PLKt-fKwAR25Mh
zeO79P%Jkmq#_N<34e^OXY6&WQzp~Mw%#>TA(0HV_ZVFK<mFX%CAGs(As!HskA~(D#
z$2)2h_o>voq*BbUA|-B>G28Pw-co}2D<Unmne&O&f{FK3)jSWdpO*3WtX1v`Dai*$
zN8<B(#PMp|1!YPeqovhS4j-j%5ZRuRYHf&*dJ^AL{a~&NXyx*h#J*IldPax}<sZW+
zUlT(NN+eG4DCfMPQYlO+OX|l5QW;T0C18#UQ~qSibCqL1Qmy8MYCCr&<*f>cN0e{E
z{W(6SZa>k@aqkG?Qx&pI72*byD7o>n2kcc&K4(+Z#7X=sgE&TQi0;lYf(slykGS=v
z(U}~Fo5ToZ%CBi0|1yM_REOwRne@5xil)N!)f<#g^(BrSpxM*PmGZPvS9`4Vd_Im(
z&ZshfP3^d#bfzkg?@r-Ur`kOzmgAM`I!={o<pU_`rNX<m6UWa~;y9I!3B@R>t85HZ
z-EFAK@cT#^Jh-UB=+rqrt%504xGJusq;wu}sLIui<v707gt$~)GhO9X8)f>g{**sa
zsdPfgZ!7Qnt7I9d9Fni(y;O_~EtRtUmUEk}QoyBD?pNgz0mn<NR2*@w!hfic8Vx8p
zrk?(s&2cr0n4z*Ryd}pirxX2D$~+6?`0FmjYbqOmR6b~urTVa;@?lsXKAxj8u(opJ
zn=1D{A4PdY0dblNR=_fjbCsc;Re-Lk6QYz4(tP-IRa@f2g~UqAXPJd+Je2snEV0}O
z)rSu&AJkq<ktdlLt-^6Y6-JJ_S-4WrFo;jjPbDr>2leoByh>$ns=C?l%7}HTl;7-4
ze4$QDR@u{|1SPXoHmrbp^x?;m6xk|GHmYP@t{VF7k(BRKNB^m6@pcPJwyG?tqnzKj
z3MDPn2|uZX>O7y4Cd%l5T#g^jA<j@I#42+ORRwqOr`!{$ZrM;Rb&sZ~R!!mq)uxB4
z8`M(<eW*5c9nPoM)SIXE1dg|LBaUrDT&+^oPx;^<s@I(DKzW#w98(!~Ad`}>R}x2h
z>X7OWB;rh9S9Rl2stMePqGVDC@u*6uMAgzRs=FqsZ1`4r;zebyNt{7U7sN1CL59i(
z-)Kr|tB}<X<#^|8VqR+%`=!c_F>2fMBtB?8kvLA>J6M&|QI#1J8&htmgGQ^{j8`VU
zQ2BhdkWc5UMDC{?zDBJdie$93P*o|ZNLWkD8$^sOME+Y^*M*!Is;0wHFqZZRM_bzX
z_Qa+t1T~bycjGuqJEYuRSH-o3s`!)GYiVyQBW9_9UWMG!B9_yjv+5f0D#Y0;&0|yr
z4TD~M4rv5SEiFdf`yT8<pHhz>B3CW#w2I#&Y_qiJ=EV3+;<qr%(k{VImX;YtEUeGH
z2N4KM`=BiGd>rv#T`BifML1X0!dp-*wNL2@kM^5N6RR#oMqlFm1>EME$?;*t&(i)<
zl4ff-o(4lL?Ex~}(nho*mLAQOrxJ)2l-s|W#c>B*0Jo1<W27f0nk>JPnN{&7LL#d)
zp3V42--`vtuL%bxcB%wya%2dw`Fw8e`VN%Ho(&9OuUJ1|=DsSxf$kc>+>cqf!$&i}
z$ME-RIrg8mfs=A(0B4APbjkwpc0<rYafVsCLd=1`<OUHILH}<NnM|SGVjr{W12Mln
z=%BbnIwbNL!4Jj67NC=2D9!p(G@=*JiAmgWUi{J&bVIan23n`*@!4kmD<<I{{R*S^
zzOGU4UVTy`XrDf*Jm`r2Q7@3^lJ3(Rd|6+KkjWKBY2J3Fv4iDVWYlC3HX41}f!;En
zaO2y?EM%Uw#n{52>@*sUf$&S?^8nBpqi-_kD`O`$ePdjvh2I(<(5L5&6T?CGj7s$R
zVzWOoRBrW{&1n7(^IPiOZMJ7t?=jz{+xD6_ru{o=NleU22N7u%#k1yAzGW_$pRj*i
zHE-FV`(_sh=z%#a1~f%}O6>)*4BV^FmDyRt@E2E^oiPU5<vng+D!=no2QQb4X?Brp
z$c<~{-Kn6{^6@OtS8`wz(06j24*F4^WJO<<4GTdx<!nB?E8EiBzsODf;E{*&awKMp
zt?^wzYpkbSve8<a3EE^u(b?Oq)x7j>>p=PL;6v7IhT^F8h;-a)IRJFZ+Eo&C#ky7%
zbjv!w2z1X1Vt5}|vzV*TtxqR`{<1==fu=id3<fQ9yq^kM<~VF;R1NgRGk-Qa`Y-{u
zINoFK?{XYN3CTT<uX&@>j`^!VpF5UN!5PO#%|YKeF4Gg=J5~jOE;-)fCx@$!6?E1O
z#~lXewj*~0=vT*MX75u+KpN-|#}3A0s&l6oG{gCU2LY4?&T^AMbDcLy^POL?G?qAf
z(oF}Pqj|sM&Npg;&O3Kzfi604v3Xy2?i~lZ>#S~o9ytHOGX1A>^FYuOXLtk9Z_YHj
z_b=zy^FdQwrXOg!t91%!mTQxTsb;(U=!AD%z3A7iu29-^&~<_l{MdDJ0q7G~CJW^Y
z*FnbYD_1{%(ATa-oc-VmU{2n2^<oG6*|nkv=#lH6Y{-vYztC&XTtAct{mWIkE9g&G
z0V6QE*jFX_@n%}Fi;FRxS*%tB=m#I41kg2~VM{<aeY&tv?)VHC1^U@%HywQ6=iE%t
zBcF#%%4zP7b3t?5AJGc0`zNX|a$n?2X{~!bJ-WgDY$a%`J7NrIr+e#E&>nX%!sL<r
z-5a^_pnFL>&{219T6)TDGLOD;OPY4U-MJO$vU?h1aLs*_>2cFNf`;C4PocXDeAm#y
zg}&G5u7$n^yVDZi7Rx}(eK*q=t9+->hr4_m^MlJC-!xvrv(I-H6XTfgig}>Bz6Ff$
z6W=iEeeT;prAhHcbX!63cI@4YiVs4YV3Awq{s0W*guWPCIn?hcg$Ae^fH~lG4AftU
zq~qI)7&~XuGp?O&U#$q=fKQzsS#2BKXH63~YT@a0aSS)L3dG>%n9UY{zzl1SNLh{9
zT=7mAW^2TvMwqP?ZE4gq5ycAlQ<PyU%+T|4L38vEnMq6amejjK-vOiKTD>Rr@6b0>
z|3~_0di^txo`vfxi~T0>z|x=R1H%Uw0ApTbEb29m2X^S$8JPVU-BT#;_5r;u9tVRC
ziDMH%Uy27X!Fnt@!Ds5gVqi`Br`izLJd5scMOJ~#in<&HjGl>ZpnGEYKZC5;nW%9q
zZWg^7pTRbf(2K=X>yOsJ+Rdph@%@Fsq)!;G<Z)OjQwrJu>wL8w*km8;?6t8_F55qY
z8rdt3lEG7%5W{^+0>`AOA{6)8oC?GSoaB+V_?|kv;!;b{da+?CXq))61Zb~_g6pjP
zLRo)6DDyuM%Kn2wUEq*V7x+-nYU`*_7da+)lb25Tg-KH?j%65HjkcG$PJf2KRu5Rk
zGmn)VQGle7QEyHF#$6l@Ob84Hrlc{q>s?_JZZLc{u<48uz*bIT+bZmO9hT31r7CzI
z9Z@bT30P_76kzp_#{g@$;JCs0ZopPw7YBA&T@yH2{JhEoo+3`9gQkj;WkJiuI_B33
z@uv@HrD(}R*NZU)pbcUe-Lg^aWbJGhXPIU@L;%m+DaJEC`$f$zpaY^`D(C|-t2XEp
zQJVXXi=GV332~GS`WxY%%Kr1MSWS!1iCWChTVfcq>9%NLg6@b&rtnjd&-gtPztda4
ziT*jDnflWr&@6pT4N!q@)6ix5Gv=>XkLd+ku5X+KdRsrsMA@WoLYCpPM-^(=tB-}*
z9(>%`yBO2`dON-uPUxKzKqvLdl|g6pb=-JfFV+I|qaMVVUD7AVg0AT`+@M=}n`qF_
zdbui~r+Nx6I@vhc4>ZH5#?TZR8@YX+agn}QZiwli6-M`=AkRjlkS4xmjHcIj8IgIQ
z_lzzK_Qys%&pv9{$U>D()e<w1Ws!Nlz^EXE#EOod2aGA+0T{d9`)XZ8p&vF>>%?lU
zajGqFn&^flXfStqzZs%$Z_rFpvo)HToF%^FngTJpA!xQZ%v;Y9zs~^86&ci7B!cXK
z=s?dhw$lA#8B_0osKJYUAbz5@gQ6UF9};#`(1+srXwYG?mHGdXu$g^F#GR#}kHyF3
zKu5)r0ia{zyVami#FG@zXX5xssJktAFF9R5)gClMZ#xJyQ@^Et|DC0~SWX3cSY6O;
z{cb1F9Q{pdnyZf@73!-KLG$!8I8DyiKcJxt^e`H_P%oVfTBNt56^r$<y`XTdJ_cu6
z-{{J>GmU^KJS#9l*{~KFbgx`yy!{&MrO0?|B50>^Che8G9jh4iGCN)eMx3UpHQQtZ
zqi4hcuj}Ew;4S?K{drGs$p}2qk9P$9Q~$UW=!w3P0sl?E&%#<{_;&>r87+}vD(-2Y
zA_lU@1=Ncs`?+~s|1#_fe;M!e1x+!(fb-PSE8=Zj(z+#*OG5CI7>K@vl3B!Me~6mJ
zLDTfg)j_j$2Txt5Pbvbf*FS6d>WEU!d2~=1Z3#V&9F|qC)dSXSJ(c>Km0SR9)hPt{
z+K6_qHkIF?V;+7q23T=btCv!y4YTxRIR9JkzB($dId#TY$pI#etqn}9;|olASeg3k
z)L#lr?ZlAQdybTs^)ELEHVC5+8=vA8oBYI1)3j+Gu&rwh@b!>^z#b=gk)F%O0*Aae
z4>+_;C@}XqQ+{{}1DJPc3UK6_S->&ZmIKG$Lm=e1r}Ob=Iytc(--J`eqh+A!B035*
zLmcGJS>pA@pgE!`JK9|FC9N(LL)doai#(dWK!ozOv`9R(v*OBlrme(elgP*dZ5E-K
zpm)U%_!Pf(&0->L6*C#6?P5(d=z{3QjJhS-)41Cry*22L=-dT#SM24ppTtUr^Jno3
z3*ep@`x@wh_>gBl6o0YCo{Fn%Rt0*hhqqp+-=>{w_20rloAgJl%ENko1JHH-u+pU8
zXG6QAC)Nc$&_~hVPxMV}gwORN`t%Ropm3VeoLN5I__;r5uCcchXpu3q5VXNq(-U;U
z@Kyz#G~VrLPmM3>8N!?WV07WpKN^<OXABXT{b`(MuY6%VWTd8;yXo?&W+E$Rx|zzO
z=bMfdpvC62VW4H^b{@9EY?lsNZ6+=Ntu@nYfR38!bngjsHdE$P(`kXeG(Rub7kt+I
zobRi1=K4s`Me|Fh(k1hLMLRB`v}Y;ZeAg^w;QunSMuT3Mc~e1)<W^qSD=#x=R?2iH
z+$y<s322=R7zJ7{LmGqLmUVdRcjPrjX^Sk!q}U;=vubw9$F)GaWhzQg?vn$Uu%~1t
z2J5u^-oxDbRDQy;|5Aq1C1+&KWY9OV18e3xxi1LxgUq3WuE@jVL04rF!+K5LKpn9)
zSQR_;!XRQB;;ULk;4Hc>NR@2xJp0wE|F>jWbQkmyF*xFi&UcLU|Lu>j&hUK8w!K)?
zL#|s()aNGr0bve(dr%x73pye$kxq+k?pM|X1kvZE_Dy^>*Z1(gl|Jmo4+&L<SHvWu
z4s)_b8(c<4R%e<=cj4PJwhY}DpTHET)sUA;>^c&dJRk*Fw>_OxZ#wczT|4bfdb#f<
zzV8=_Y1Fb(p9i(FNY7{kTBWyQ&8^lC&Ihg0Jr^c`*Xli3kn8m3jX+!Vy){AG^luo)
z?RsVU`hY%ySNuS4#uy*eU(5j=(m$IF`cS{e4a<!yto8SdugkqO$MOke_4+?Hfk8=C
zUKx4NI64r5<HjBJOWK!4N&u#3jTcOf^F~i6=$i3n0qCZ&Ef@5&@jWZ(zM-=!9~nJE
zL9@){X`ne~$9&K{b9WSIzPXBtxxn;)9kkFa#}={3eAo@N*lf()wawHape1HnZGK2v
zYQDwK3(HJzN08U#*BRt;Gk~60VU|$2Zw_H%7MZdSXq7pH?~v8zlS0rM^F0>ZTGKrk
zw9edC4D_aX>kZI)^Vd?K4dxgAps!_xwxDn17`B0L<ssIS=bUWU4}4y><3+!dn-f46
zWcf9qi}F_{#rJY_J<t!bfF1Zp*@+2wSr$^^PqJPj=%Fkc2l`WH#)BqX&s%_|TJO@(
ztJd?(SDtTDnK695Nl9Smfa;LqZ;+bQ7cez^uhF1VKh}7)xW{4^N6&p+(W~+zVDI~E
z4}FirZ!+U44eeKraq0hd2yj3M+hV4NcO6)PIXb9E5^%7E>XKRZcwlxH+LybXnuZTS
z>UrdZO1#d*bIpO14Blz7h-0{Bi1FMwSL|*IS|s*zombpsvJ{E<4xqK-Pxg=XVtaYe
zTOx^CH;VxcLGOwi%%?5lLJ?@IC_fjpU7V;2+93+KWTy!A(E0mCX`c40dB*{IVt&Zj
zFP9DBAo;$$F#>c!&dLT|lwKCf_tH(9evnIsgBDtI8K&jdJFrldVbscMXb!dZz!g?)
ze$&KC<X20qBz~8~N*;i^vQiFUvE`{Vnv3c_6TsBLs8p+-ITcv{6spc@FcUq%YFLAf
zsnHqA8~aB9n_TDxY&sbUWi{jXOswXf9>5m-dWqGN-zTx!@T(+N+BbE9ZT%1-tKC`j
z5-Yu8YvAkMP>xo6&#k_o4(kwVtK*6|V5gD@j@7v<io)vRL}FN7&vgcN3x)%&?zK=J
zR*z%zfIVYZ1ADDUl3Bgit^j&PxB8&vVk{M{5JA+jQgopQio_noTg!E7nxWMN>f(8E
zU;A)M_2igFxw%8L`e)>4<qXS<>CiDPA->7TewnSBHjB>4&5dc2Gb}%ISbkniv;IS~
za`Q4{a)*u_l!cY{qI%6LWM}lx$xE!&CoY=*#mB}c#HPe0#3jZj#^mSZ49&9})(f_e
z)N%g(T2k}I=4pTTU4l~nb`=%>W>;m@4QrS+tpCuF12X^iyMzyp$rzCxH7sXXW>jWI
zzpR-2!6UQ##f(bIjLNP#FgIp!#)tti{j%~AxK4SQBl2SUXN(w{lNZx8r~k-om2~a9
zbZi-umz&W)vrm3zMs`e-Ms1^-U{{~CoB<<;X7=fjGcbR2#)wS&hX$n^{coHS)(q;h
z{x?o4|2GE`m9=|I!>=pZt(S%F{&2v8xZVAit(49Gr=E;yn%QsUpxq@`{UGc=i-LDQ
zSY4xuGbJuQDlRcL)(*c~a(BYjUX5L^v4`O0)NkL4N@9USzw*#qqox?8KYZw2UsJRd
zvED~D#c0vjn-wYAi80;-qyn!i3RKP8jWovl&P)28RN!qDE!yc1{k$uqvESc&7gLe!
zO^Jc@JAdz-7)X=77cdorz13s6wuE<FETkdc)0m2u-q1Kme+%-y5eMmD?*UB3a<3~M
z(ksE<?(vXT@V<j74*H#x>ur^w)~o>Oo6CBCN)T=JBW1mHYGJL@JG&O1HuPQ~rF*N_
z#-bzTyyI%)VPEfQOmT_OL{J597Ae_#fRyfaC1L5QaBue{QA6Z=XC#SAc=%3|h>(>U
z<EzKsZz);k{T&khhb!KS$)YMQ&?;F(h*a-zQm%IeX`%OHP{`m)LaT?@)W84zd-#6<
DYAdk;

delta 12398
zcmch733!dy+V;EN_g(Mak)1g*AR-}z%n1_n5c3f894a9yB?%Hmi%m>H46(68%v5zi
zmDW_Pp_HB$r>$9Asx`D))mCX$```D9?|j#}{_FhT|DWsn&$;Tp*LvRduJx?vxu0im
z&fa$4obi*nw3e<#?TSp(ojxlx?NNlLIkbQNpMEh<)AahmjbXM6Yf2r=miYr>LOLsx
z{c=6bewYGC4auZQmuF{THarQ?B(y-8Y`<WC{d75?dq^=&rgQ~icDVzfN2n8zVY6Lm
zkLjF6fM-Lt(PWoX%P<>4dv54KWwN!!ruuU+fVp9GOn+GdN@~(0J+26_p(b6?3+daY
zaQdJZF9*C`lZWg3I|BBF^HBZrJb?3LO&+Je+7$3%IM31Z1_READtqL7jK8R+>@W1d
z_-1Gap=pt(%*`*-^hQ%*x?OD$Ot{2~p_sjgEsQ|_2Ha^KqGp5yw7}SNEY|2w8w|Aq
zdh+4waTq)61diZjJuYIz20YL4`?$D~7>JWK{Q)9pqy?<uc;{@4n+NXXxY=lo(*q;9
z>DL1=?o>6N<DZZ<qkCXej=$=Paqp_#IW8NeX=c@sqkK1l<Dk&f9EavK!lZiWWlpL?
z1ZItDH#tss6_~-Dr;dlEUT76=F}60w(ba-DKF*aXH5m&15hP$X3}+1VVZ$+Q5w7gI
z3*(lxlzoruj2SFi?7n5bCz{?tLS~wp7JM#S(>4e%23iXqkI6>i!v}Vx-)x5)M&%B{
z>{Ve5ptbH|*EOqV{A)9@+|hTPrU}Oopzg>98d|_?2!ki5-N9<d7`UQ2Zn$D?5#DyV
z?(5mr(E(95Pr8QK`iYlayKHUs@E)!Qwp#Z4&9Jn-?@(8mJwcpzb+-pUqaiMil&U7)
zaA=-gL9wp(npR<HTHqmQ$*WC}5Av$}TJbRT#-D-sQ)ROcP7NH^5(}CIy_v!Vk_!s)
zXUabo#JOC@>=BW&Hx?(DiPt@FyI~?&h3X-q;~npfBQ*Vr%kqfzY5_5C3-E<>G_%6h
z%A-N27Y1U@tHw!esQW`LK0%>M(qAveJtITgVX4&_Q2i7f(f>XfD{5CygTd#e?wS_j
z)6o7VCg$g^T^_;J`<K9;>dDC2%{kcFCpC~0hdIb~!=t0~2*l^p%7Z4;tiBSH)@oum
zlb^w)jhZ;j>fxBQRTEz`9^&;$SCc@q_OqC@Q<D&L0@CW!UQKG4_6kfos7Wo&XMq6^
zd<yLo>^SMdL_8|;n_zdnQYBbKyN*<e6H%^vRidiz8iXgSZS*I^w4nff*81<QqG>hE
z(XIr~y58rXgK3*rV^5^a?CBcenJBzn%RQr<b-3j|^<qzRMQcp<S9t>=>}ytqoP7>E
zG7yx3=KkTB9QCe+Nv7GUBPPd`ha)xLo2cq;&kCL<n|IN)F+%O8$@|HgHcoiXz?r5T
zSeKJPPV92nYEEim(m`{`=5d-fLD=cLul&B3rWFZ~%h)YYRzVtH5J4ZqlaQ2W^2TXC
zQ-%L0nAMQo(08VbDqmqzOYU$@cZ7OBf;wkcz8WjPb-m=MtDCJ{A3H+4PcPN9<s#Vf
z(zJH+yz6I2sxISQv0i00=b%n~o>ZHJ=vqba&9~76oE0HXU@Q;1u6Tu}U4n}02>${o
z%^|C0X<9u|hpo?7^P=rMR(dOuYQBqbj&D~H45#E4SFCqv);9RmQv^_1cKHK(QZEt6
z#}3V+%{Llv_v|P3@r_GpbOS5>*W~6|nl?zNfSa-m(H~qnamWI6vmup}K>3_&t9RY%
zn<i=6GnJ-9dCje9!z(9ga=h!7cb?bATut+9>&px3%UxMMbzA$_*R)fTA@75rh$aBd
zmM}`wepANL|80EINz;B;#%cd;9PIkQ=UFk#mEapHYPmZ5))vQIdA>Ep8CNNAtLru2
znjKf+>c3hn*%jXZIHEhM|0}iItN$>D)flO1H<Z!;5_;QXj}v_64R5uYPM5D=VC+={
zKnS|~;J+SKKKEbg)U=0|g$`4B34ae)Prs@n!!^pUw(xQ-@Cz6FU9bA}4E`CPjqhUF
zXZTa=P-k=x461f?`T5tb!Ko8dy{t$}+l;nm`Qq$oK&?Zrp8kRU9nk@Vt>JR4(V9F0
zKG^-d|1BdSx+j{f-An4_6EQHWNNX`tVH%c{HD^b{RM!Jp27hS!%kV+2(x8YcZ=w<m
zhc2ymU3-I?b&f-XOw+Jgl?#*YicOe2Jf+nhb&a86GaC5G>QiFyYFLQ04~N;P5?Z;`
z@T?~Fr2ejE!4YDYYiMvtXhsqqM~78DmI*fyBcr*G^c?J396Zi>@EM3rlNrQw_;i-q
z?Rvy!2)NV&(0-)W6D>q)FGUfL;)6nJSLYDpksqlAr4xO+5wq0#8TfRO+Na%#Ls7L-
zOA99+M=+%}IF|UkI>o~o!O4U;;x99Zai|NaUCJS5<`ZoQz0@Lc0jYh1*h?*NIPpg`
zN~vvv2Bh|U81YblVso{!b*i$coo5W=_?Ehcm%_cMY^kN!L@=b5t?pU}!h?hCTv|L5
zC$(SIc5T#QV>-}cEhYAwNxU0EJb;EEwK{pkpVku3RwcGj2NbBos&}QOrCPsbJjdto
z1xjjbJT)iiZbwdh@nt}2`&3w(CUAU4Irl)}#Ras?hp_OPiovlu9B(NlMyRc8jNmxB
zfSB8y*hB?iPUG0KH!%UtR%+$5iJwG6=$K6Aq~aOklySrcDnrrguKJ6#3{}oOfa0XK
zRc+e82ghqws1K~-ctS5?Z`8EZ&Sw$(qlG{dN)4;0aC}OoyFo*aH&Ja)ZHMyriVEF)
z$X{xH_<Wbz%j&f#wP{Zk<YmhKQ0LPR+{7{!x$jhhYN-eX^`w1tA7WQ^*U!{7E~@cg
z>Kbl?Pm2^fTd9Nhr~t0B_+Y|ZViT3c<b@oMYEOJ|KJfxNpwtRfz4S}w`1=OLnQe&v
z3KzEJI3|}^tX!Y1ZoE=CF$&)}q&7&U?`Jj|sfDSq^g-j1+RB;47<FU^CByq3v^1|v
z?4>g2ZpZPtM#Sw(dZv<CqexnGrI;;69KYsI46RR`x|kRpOuVbA=CPma*Xq8`t14U}
z0esN9FEK*-xDf)8+F#0*TxLrftOCA9J?*Uom7(hXRwkcrQ~hA3N@$&MTKcOUUa!q@
zOO=|R@;QD#f!G{f7>RbO;5?_K)J`21m(2$;Er_+00CQBDo>LuSlnU%ys@2?8_r4>!
zvQ-K3rix93FUQB!?WZ|7o?VYvBZW9brMS^_j=!$#0dK1yf20JGZs&tvvWV+cj++hU
zxV1*iTSWXsIXygw;|P=3UAYpP!SRhT#Gy@z4yB}{Dk^om&~oBAVzC#oV5H`n6;{>R
zR$Wb~2p)Ywy@$3gwQ=f=GwRH274b_=Xt%4k7bSAMR9)xK<s66m5r?YuUhT(mn7X)K
z`Iu6LmaOi?UaGrgFXZ?KNCtFPrO~c){GM{<aURDZO1Qp-9FJ96-4e#JsbYOlU9+ds
zRa@oy%c>J4tK&~7yO$C|V<nbRDj-G5K1=1e)KZciSk6uND+&Ciddfak9^Damd?F<g
zk1PDUN@@L8wA@iouPaBREn4QO!#Z~2xaDl3RFZiZ$g%H0qFptXY6CcKlB@dgZ__v#
z`3!M}QeYz$Mz_-5(dTIoD<Mu%$+E5Fc$A7ww?!OZREnytV$j`_mZM4zH&qX+9Y)KL
zQex;>;^P{`fC;J(?@=*`Sw_=KX~a4z9s5;b6sVg8s{>jG@#)9K#8S0UFE_`_lzOvO
zo!wJToM=w_m0`pOYPVrZJwyCynXlBa1jnNfSBs;`rDU>NiS=C-qR%JNzFlqov#Lce
z71-C6N`|Z8&yC`myjbEjC8%zTIZjtj+s1KxYXR{^wL@LyZgB-IeSC?|Ky}N;YN<Yn
zrol19d#X)ms~e0^4joc2WQ^z2i%KPJrgD5>5OIAsqDx6tsu(;>pv9*zF;H3VD244*
zwR>tc?G?_Zq=uu2*b|tcZah{sfhzH|OjjQg`;?$ERZBao?i#1m@K{A6N<|`e4%hb-
z#K3%_q12F~_K8s`YZ*%W*7?L$T~+Q6s+SYgYY|ETZImQ8sC)NSH@L0ro7?iW-^LKv
zwkK{>>1(d^e4&(<*-FR*Rlwg@>z8HV%dF<3DkT|$wY1!4iIJtyzolg?<)nT(Uk*mW
zSXyug;>O;@rYZ%s5FC6v!*-VTrV4wK%4-W%@!#WJOS_>O%RH6P3$R;SSUKN%q^=RI
zQanP*JW5s2NSurBA*t}x()y)x=~wVeYDwzxkI<^6S?cz;@S3IdRc=M+aQrv8Woe%w
zPL`HallW#!zI(k6#|LT<pCl1e2hr}Oig2c?g$f)jwZn{rQ>&TCNo+IXZz^=Nm+-Z}
zR4(5|{w(bmWofpK<5%FQrQL(VEv>vW(O1d#hZOD*q{4n;9>;xf0o*>BI0f<qX)=5%
zl@;mP0~nPypZSmXho3TeT?DZ4i?xC2Z!^Ok_VCq#XK;wjY-Iq4Ci(z#K92&9N^Srg
zcZ7vIK9BmI%)eL5DItx4({t$l98tocED;}3q)WvE1V^qC3lJ~4S+uLi_`fC=QbN1M
zcFOaB*wY(yP?&u{?}+D^!9!wmN6-f%n{J&Jsf^-zQN$N6h=BH>uf=5220fS0w&^Dr
z$vt`)v-g%>m*>8%Z=q*<_37cD!}?o8LC!C9F%0~rz8Wc$tBlsX?P}vCmS=?#F&DJO
zn8RqjWIW)DTa9T@p7olskx6;ONSzGhY2zb5&>3Sc%jB$ao+o`~oTG>5jBAYPdE=e&
zpu0vWW4_EB1cl1io#vQ!;GO1Up1a%ZL{;xG&oXRpo0n((SJvVv%-Xw<X_duK%x!Fj
zm&|Y3Kdzfs*))DI2iQRO%<T!Fnes4CFOh8!UVWj=%gxvHQkj=E8K+Bs9=AgN>8uYf
zm;2~;g&f5f*U2x7L8s)m^FU{1X*%eld_f0&F283*Uzd$bLEp%oe0E2+W3<1QYqJrN
zAEjhIms$G;fYw<xc)u;y!W_`cR&54*yLF7l-PZo_!Qgi+CsT3Mx<xu}wHygLY3&LC
zU9;@<KsT+A%RqN62h)4cnn$fZwhm7R{b{v|2F<oz9t~P*yV4xA(zeHyRX5NXP5o@M
z&8Y)=&9;r&-(|al5|VptpYlehY_r#ZKC&&~0cULApvL7zn`Bj9v8@RLePMfv-yE*n
z-ea)7wt2S#-Lj3E0Q%WhjlK0(TWWXEAGUMMN3ngY8#KrMh7$>tCH8<BpoR7;q{a4Q
zERE&%;#kmr``Wso<MyR7pbPe`xuDDTtNEZC_Satk-Lcm<K=<qq>C;d4b)!HJ>>cUF
zBYPn;@TdLMV$e(v(+4!$V|)|PJdd?bC)nj78H86n`Y^7qd-%|&gC6fNgGW3LLB;ZY
zkA*C^k3AkSXJ<XKeL<gkoaXGRhmD&2#$zZu*moXFhJfyS+-5`m#p4E}_R!;MIOune
ztbw2>9y^$U8CA{(@axU2Drc8rI=9MTCi1FhQVQrR&ymYP-*`@Aq1^Ty{5<G8&r1yO
z51t>f>h606@fNcjT^52CINqWcZpSqqU*QPmcf9qEaz=Es<NMX1*BxP#L2o!V6@&IT
zTA+rUa-U;0Up(kI&;xYTF^ry`bo|b3&N?2`{Y#Fiok3qZUSSTta(JeJzHyY((c6wm
z40nmwat656>mtLo)T=(5)N-#DD?#O6>llkQUN19-yS&o)#bu9IIxpee>$RQ2IOerv
z5$KNBbmsSgS0F?3*sGC}iT7!St;D<ii=Z;^q2nuy+%ot1!5}9LM^#xlJm2Pt2B;c<
zxu6#Y>R*VY?QtZ=_Nly*$N7w>D<U=r^8V4A5k6~{sL}{eXNx<ysZ}Btcff4E_z7-U
z3q-<N%od7QYGSrd>}`YDda;mBJrr@QfG1)gr7%a&9S2&V@1~Mg==nT%mHrZ(lI!(J
zgFrj=Z9M-yJ&#fUn^Rwc>no3a_H)B(M~i?F!%Bb&U6_j&qmzMsR`mzw9btG%#h1^3
zwu)bZLGOtD(?F+1EZ(<%5nT~8wP6*oCVi7#FvmPX_qSrBV6)<6JTQJLx`FOY;Qtw9
zB~C?+TS@aIFnIvmM9M4{Q^Uw^z(&n^T;tc40#m<by3$_2O4(!wpEf;F4ov@?b=IYT
z3G4k3$H<`rXc;}3f*9`^0Gyo89L*FzusM~8Q`pHVT|#gdw=k)(O=8sw(01{}AN01U
zjnG;9gz|pBQ0^ZP%Kw8xUEm#|E^tWDYwM^`7da+)lgc36plGVrD+7jR(D&*d)NRDL
z7QiUyB35#}9T0_#b58{(ot*?s31n!Sq*L21zGo9|_3V6LyB8+_JO4Qzm=RSK*k>{H
zqmByR&On4MNd?xPIulrb?_^-3796+wn(6QSsW-6Cu^8YCaea*wJX7552`UyJ)Bu%>
z6V%r#@x&9fTD0V*n?ybZv03CZEL+4@*3J%bk}}&V{J7^EVm$M+PmCS_+Am6)gAR!8
zl=b_f8s9rEGMShY;x;N@ekSx{_Mda&7(G5O+OR%uijh>)Ez!{g-4?wm;a^1&^Y>8v
z#%Mhfg9<=%^}7|IdHVYeKqdNoI=WK-p89p`QA0uH`f7dvZPgz!#V_k?p)!2;sLm7K
z)~CR2C%$gHz6{fS`b2&*oY1E-J0Iv<>wwPaC-~w8J+UL`bG<op_JzJR5%iVbzyZ3c
zPlyM7r>94Oe$|`sqBD#`*`PT_G*eS*e8|@q8Cqjdx$%(weU;I3EXcXVD5i@q8EYB!
zT}EUf=uM+LlYPV($i0sm^PxhO;^^2cs4TY73mE4>O04)gi+~9Y`v4Qm-A~umEA_z(
z(Op@s4SvV~&Js>6L4)yW2%01M4+G5=F>R=%dE!s5DG_U1gXW8`dFut@-W<?EF@R@Q
z2#3orKG0dpR=Q8Dr1bWSp1jxr@hwj~DAM^h+Ce+eA#r~a=v}di`hQPsp!yDrFIZhi
z#E~%2QL%vfIVMi81-&n-GXZ}S2PfjVTY~qJv-KZ(gXZY%o(0X-9nL1;dHP?JT8ZAS
z8EC#<m#t}m?&e7g^|7Q<{TPG2NI#C<<YN6A9bKZ=q@zpq)@h(Jy$8Kmruz@Yf$Q~r
zl&JNYu3|gaNR7j@5+jritIS|{<x1nDF07XdqhcE94dX%gr{T7(Vb-gk>jkX$9$k%T
zn+J@4EeUu-59S4L>TfficlG=f&^=x62l`1rQWf+-U&@3((!XY5l^NX!f+~zoP?*Yl
z_ru769C8WuqRDKX+l`23SNPLdKO8jE{275!ORtHoxTJMcqy@n6t;j@QLdneIvOh$O
zH)xjLr9NoB{)EPrdQk;vlYYO`(=Dp@;nqQc^d<B=Xjn$sTLNR+6!ZM{9!r3o`-K3z
zl=pc0Qut;a^N8CCz{sPWE3K3bRa%+O|1r8xw@MnzGn1<q08`dC0yb{y1#A)&#q*ms
zTmfwUB2(JpJ|r(&N{(Cc|M!<|Px6ZC-?G!RYg!1*_=`&H<;`9?<og!D%+e{qG20da
z$5syoj*CDp<#>MsSor2l;Kb$gfRit>t4z7eQh(v@Vy%lNr@cVA6^mOdL9<2QIM5t%
zkZ;Zt9ob73i04v43&m-AT`IEJb{30Vy1hiS;>S{%xarDGs_vY!8k3jBfLzcv;gbV;
zRh&ai@z<_t6w>QrDpS8hydMv`BxX@jH$^8pcS}6q6?9v;27vB}t9<sYSju#MCj#ih
zU9r9k=$^R2J%1E+SYy8mTU}6zp6z6zFV%0+&-MCos{CdB7OV1IeRV6)4SkO~N&lJ+
z?Y5rT40KOl(*g8A|Co*Nv3`Ux{X?%$<1C{&RX*FeJ_5AR__-gb%$QmV+H5S(1f4Jr
z@%Rsn4VkXu<N#+GZ+6v~#;rd${+J88WsDJ^C&tIKL4O%H7lCG)uQ24rW?^5@Y;y{?
zUTi*LhL)LA@<A)j&$!ttb7D`>S~GSDXubJ7KOv5q9T?sdrqd1j(6n2i)8^5z;owiq
zpPGZtn<ryIm(BMnr7z6D+ODLOYR-cU^BwaP6aT0A%p}lXW^OU4Om5<J-SQkYvs!kb
z;MT}Z%Rw8Y?Rn59*|IHYs~pZ-zas6)pw}dSm?C$|`mCB=vRWh1Zkde|lzZji$)J<6
zGn?HhdBsU>eJBsG>`zM{hUARwl?M7uB4zx`-`*h5Rhh#8U6XrW1YMUEOzT(jGU|w}
z!HVoW6oY!3kzds+0;jFQAV`&L@GRHURsVa*vgj`9<q6p0n$FJ{>tFWAr+YXbvu!UE
zBcOF_x%%FOe?WMHu{|gbviJ^*&q$}lcE?k1{2YvV)$P-s&h=M$-`XDz;+KRdcO)kD
zhEtOby5TZ1Hk>k#?>-%v*oGf!$@M9LhK+ft#u*cVX$zVFoAqXJTD%H<RW{QP80Fz6
z^;RaP@RZg1EF3E<^m*MtYxGvExwZPP#h`V%^UPH6dc7A5a)Um$4d`|KY7A(*{vq?Y
zL$AYF@7K$D#RK{nR^mbZ!2-}b`jHu+L%Khol^f?->u(yLhE=*_dG;CrgYPdUFlcDh
zQzs7^`$oZV+_<g&l6Kl?;)m%c#sf;@f{|$lePy^yK;Iaf$AP{x1SR}~5zVT+Z)Apo
z=9%%cKnu(+MW99Ir8v-Ha~XxX#BAIPwA4&zizqXn3<51P)2LmSnT+ooa=BRuVLIgs
zvtk&gD6hUCx5=L~$Z|84kyvHgmG;dn3bVp|%#~}*$@~miYkpS>T4%n=Vq0(Oqd^<Y
z?NvY<&8yFWHkm(H1#LDz_62<^J7j=9llg2r=j5BLC+B(DJ{x>Nw&z7J%F`*JOS0-Z
z&}A9g8gxajZ2`I}r?UfpE?=Yozm&y1@LM^eG3ZBG_5$dMT*wNXVMTNT6<d4h=ymIU
z&eO=JcVV7-r3V1}r`CrR{|2c^{jF|5uZwi3s)5`qEe$DQab)i0ilNoYfWy9Kdl>#5
z3p%R?b(x((rH$Ac0vzehwwUAOT}K5`qtDJv1&)qIb;;cMF9P$X(Z6w9c+&VRNY5#!
zcII`a{m}t9{Wr>RhRA2S=7^1aaiO@>4pb(ta-CazL$Oqdfqg*h#S`|AO=3ql=p_-y
zQ@4o)jM}T>GWGPDI8y<7T~u8N+9B?;Q|%Nxxa1At<7DvniPqfhXY;lV^uWBq+?UHy
z2#|bBUY-EDB&X$pF3Uyq@QO^PPgmuF@t~#FF4k_jbp{@)(8V2&MssMm2cfVU@s}o6
zWB#<nO66}!thB+XE33(VEVi6YCvj1;hXUAq7%J6j@jEnUwLFQcvsz6>53pL-Vq<D^
zycpQFaXn!AnW4aTTOlZ`J%49nb(lB=*pWXku{!bhBvv>6l*H=(doy5$4>Dx+c!Zo;
zJv(&;_Hv>et=`V7!$E!cBND6cdr8249!QSWKLb*?2E;=c*1!N%u{FpG0kj4;^aKvs
zzX+IFcP((}PKeAJwqg~~Eu1Yu<zhV#S|ytEjMZWqqfsGVMZUF9?V4t2>wvm=?Cs@x
zw@Lkk^ro48`r^OtDaq**vvWGPYyV7Ad{Sb3(m&ZU$Bmu%Y;JyGrYpQ@`>08|`6<a<
z7M~cOoS2-F*eE$AsZnC%%%XyVv4xr0x%mn4@vbo~YI?@UV^sN{E2(vGYF^fe(Yg6K
z+JE%al)@>6|IrhJ691#e1vecL6O)jX6rU2G^#AqXy8n(^od1JbvL@uk<rn1V#N}jV
z=Vs>Sj~F{~WKJe-lv#PB%zs``G<srQcINY`IdOS0qsC>9&YCb1f-7Qz6Z#eAOejnk
zku_oLq=a@kg=2~e#w8Rv3*w4KV|776e!`@J31bS!WsS(eqWrj`oWi2Qgl@Ung$ad4
zS#cu@Cgk9sjnw%x{L3Bx-!^nbwhCzcublfoZ{?cUD*WFG`Tt#k?oMj`ZSCg&o@WSe
z_QYp*CyiW|<f<_;WcT|kR!Nt0ZSd|b6<5UWm1`TMhc-%T5|`AZVN(5Cm3gd%PLZ6L
znv}fz^0i@YJ+`w8;p6T2-Zr(x5}TfO-~CAg@x0#YzPn3|$Pgv&RWV|c*yr|(6+OgR
zcNXcIdlzYjTf`}2uS(iTy5_zQ(mVOO+s5Pl(eAQ%SeLr5gY-l{cX9%(OWiXQU_I>q
zJ4o*o;Eqg$b)0*ABCH$SM?iYdV7Gq~tcTrMNwEIt-UV`RNEW8sOcve5WOuJ*wev>O
zN%wuykM1@pcvlN^FG~>_dPtc2E3g>uPHKp!<?flJZSKE=^pKkF$VPa$&po~otY_Uv
zNR!=ujX_J@S)^_5T_C+yq+3rF4a5a^T&k#zhrLooJvq0nrscY)(Q?nd5f;7Sb@zv<
eqAsp*A5*d19hwF@>25>1?an0~c9*4z;Qs}coT6U<

diff --git a/Debug/Libs/sta-core/src/bus/spi/subdir.mk b/Debug/Libs/sta-core/src/bus/spi/subdir.mk
index c3687f9..37b940e 100644
--- a/Debug/Libs/sta-core/src/bus/spi/subdir.mk
+++ b/Debug/Libs/sta-core/src/bus/spi/subdir.mk
@@ -22,7 +22,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Libs/sta-core/src/bus/spi/%.o Libs/sta-core/src/bus/spi/%.su Libs/sta-core/src/bus/spi/%.cyclo: ../Libs/sta-core/src/bus/spi/%.cpp Libs/sta-core/src/bus/spi/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Libs-2f-sta-2d-core-2f-src-2f-bus-2f-spi
 
diff --git a/Debug/Libs/sta-core/src/bus/subdir.mk b/Debug/Libs/sta-core/src/bus/subdir.mk
index c857b1a..543b89b 100644
--- a/Debug/Libs/sta-core/src/bus/subdir.mk
+++ b/Debug/Libs/sta-core/src/bus/subdir.mk
@@ -19,7 +19,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Libs/sta-core/src/bus/%.o Libs/sta-core/src/bus/%.su Libs/sta-core/src/bus/%.cyclo: ../Libs/sta-core/src/bus/%.cpp Libs/sta-core/src/bus/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Libs-2f-sta-2d-core-2f-src-2f-bus
 
diff --git a/Debug/Libs/sta-core/src/bus/uart/settings.o b/Debug/Libs/sta-core/src/bus/uart/settings.o
index 67f69cf08c66ac558db15287d5af35768e605ae5..e862daa002f19f9aba0d96b82988baddb2cc89e3 100644
GIT binary patch
delta 2906
zcmXArdr;I>6vyv^`vc@9AP<El5EK-2SyTqoVJcQc#z5Hhk&|wKE2JXHL(;K++W4wr
z8tE5OW}2pAzHy^5tRc*CEZxi)oz}4_RLt>FBQu$fsondLKh9pxIrp6N{hse#*w${^
z*KXRJWO}V7IWu_iFd>q|{DnwOZ<$+^@oKyfW^v4<><NpqyESE3;lB{9&S(6T{kg>(
ztJ`oN9HbmYqm|u>r!P*O`!bcCVpjG>s<NMQ_JynSHwntN%GPGF06UFa4MUX2hdqlw
zGg)~Kj8ay6PT89ym0hb_)yLT}%Kkk<Sx1Jlml)_?s5(E)Qg+B#W#47QI*RsF=pfPV
z6cv5Stp(Jvfc-H;pNde?1GL;goio5V7ei8Ghzc(!{1FJ2MJmth##2+Q-T?>i1S-!a
zp=@82vd3vNpMlZ=Fg-~53&9;kof|N;CQSM7L;CF`bx!4OJK*QRWd&m`1AND`noM<4
zk5w0Z*b_t5Ihdl&j9v|;<G4JVmMa-$fXtDDRenADH^r!P968yE>a0^|0C?-jUjcuo
zV03-D$|)GCtB(tm2xN<`BxP`U8a$nY<UCg3!yX6gJjC{PfT~bK{%|<{g`s;`-vfmD
zCky(K`df&W65Spqbb0xwG*w~)b3I{mt3e~HNq-}$y%1}MG&{|XQqGL0D_Uh*xU~xO
z`-UseQL61`xdu630rf4S*Q8%Ji$yfPGfrJN2EE~=P6W+Vc6kS^ZqSUesmx+T`X+qb
zVaHvJG6*n-iEgCkd#tG+F#pi_B5yEX`E_xLa$U%(2kAK>d<=F8ds@d{XCkOfMyUYh
z9`?GB9nWC&eul`V&T1NOX9z!Xa*$pdYh4R}dH|X%Ms5ydSOo4o2=8IIWC;9$5=$uB
zjY=kBP2BneZu}Xj8GMJ>`d?I-%xaQhdJCh+un4aX)k{IPo(5r|ir!8xSmc+VS!A-s
z@44n>xJN7{ky}3S4X}t4@Kiv{5b~db_+FT*GZcRj{=MY41sGvkf_|H37b*8O^cK_7
z2}Kz&Gz|_upu`%!32L9oll)^uufpO@?&k9@+POO;Lbd;b{5EP<v7i!$xE=x(Da?4<
z=+sj50Vr+7#>2`A5PK<+!=R@jyb`&c2jwlkCvwQ&1dEqhM-2=eBDxrcdU;a;taxR(
z8m@}&xm0V=k=_mjwUf8L19?WV*B&rE0_zN}`Ew3Js!51zK7%&lw~SH^0sycJrpp1G
z1bP#in9R7Z@UV>#D2<1r0;4Y=HtI_nKZ5pM%zniP4jiqY0n-C8t%T%6&{)7-0f5gy
zIfa_JsO@)#{)A@Zsn!nDRdhK_-%$+o7`2@w-$qU|L>ytc-Vk1MJfuBubO%n>*TIb!
z-2b78UQ(B%8`n6+L@SGHgX3Wg7XcFmD5C|>Lq;D=PBxF=3Q;G$hU1Tb>G$!>rsl>(
z0-y6s4y@RjdJ`+yZnOoZM9pM~7bv=y{QZVE$Pzlh=xacqX8ap8T8}_g`*`r#+zLkw
z2WeRZm%ZGICfY==0c7wP0bHZ+eK>1|to=mq@dnp2XFeN?7^JA#hIa2teQRP;q`z`?
z%djTm<eSn&kI^wWR<D#R(?pIGgC?rc)3<OoUh<)dNcipq*ljo~l0$34Mf=b&RWnM0
z*F+tjHniwONF|W6m2G?nfH`t>O(X#9L&PxT*<b8Q5}774amC0*YoeSsg4q*fV@-5P
z4aw^AM-x?y)t{x#4HCB|G5~N0sbry7hm6X9$5{PuQm>luA)$5{y37Oe`8ibJKD)O|
z!D?c&<UkWP+IPxDXu^=Gnz%04q=~zTI+7KfXH9Xkv{{UYxoRHG$DUy!SED_-BMSYD
z>A49WBXzxhxWj4BcNLa6oKx*CSCY*Wo&F>+be6r;Rq)bur}X4ZFh<&T8d0`r&uQDQ
zeg)Q9_3pZQYh`)e(%O2fy|%Kk#=Wee-dZ-tS!k_)qrB4XYH*j=So2>j9-CiYx6t)+
z?ZU>TZkMBWQA1OCo!e@6S2R|6j!f9<@2SYm&;lpfvd7wTva*cUyg8m*d5a@WNye<w
zCeuvATUuh8Ygo!kOw~qBnZwVVZJaC{VX86u%hF68MyMmrbkmrKo$p99A1@JNkI|PG
F^*`}CeSZJ|

delta 2894
zcmXAqdr(zX6vp=j?&0#5=am!#K>-EfmO4HNM`1t^F<w3xN|6C94TyUIP3&OW<Y<%9
z$tY9IP{GMay_!lXX4W{PMB0pnY52g=Kb#nC1V>EU`v-rl*>~-=zO}w@t$k=~HSKIQ
zZ3{Q$H%7#HHHQij;p-}d5!|>qbK<s9LYT!7ld{*tl-;W-J2ghxOJ2&JcTx6XW0zGg
zCH$b9azw`}`xBmEiE0*q#3`F(R@P^nvb#9<_^I>Xqm|t*OPj^(*tH|o*)c-d9_$7D
z*%8WfYP_;BFDm;4v^qUO{b-w@tbe4ki4&E*LPHOH)VV)VSuI}KGFq$#)ID5zzT);K
zxzEXJ7_0oV;2uSpbN<S6igP_U=b_<YC8)+*U2ov}A`B`5lxK_a++@{T(cnFc@@x{y
z-V9XsDrIKSkQo9Q9?Cx#-midT0l&dl`3Df)2PM+T-39qVv|LPE^C15bm@#zqT(_#^
zUM{{5Qs;PNZwLAvB#k0@GbI<&%0nW@d8&9j^G^;@=PY9K$EfojaPC2GBk{H9*MXwT
z*_X5+U4>o(VgkKyCuly&>FD%tl!{r#2!^mH;9AJCz3Z-Sw-P@ajr(Z&Hhb`xMZL>_
z?t|aPt)1IuU!lw78_^1)p1z(jxs$MwXwu(A=p(iv717Elb{RM`p21)hSxDAS*k5}=
zc@BZLm*M_K%y&>d%<XOI*Uh4c!nY==gssTyN9X}~mov-za4m&RxJ^Z7v!pxF<32O)
zpp_8Fv~#--%*~AH4rF3^eS_E(<=4eU;5t~VA6dOx3TI*GGN%*FHI0Reqm_-Y+{auC
znQ<(w-=T?@z^SM3Cp7Vx4GU!Tniy*f`ssb7Rk3c{SjHl$yPP+IAE&tp1ni{DN<cf^
zRLm4?GFdm!#+8QJ;r9(w?*m~qqp_m&30e<f5S}_0%VD;b0=_;9`XT-tK2vc_@eXOd
zG#7^KL1cBqF9@~z(J6_NlZN*I#t(cIrYHVY_|JpT<Zk$CqxBdVTmbGQ@@7-A7KtoK
zmyQOTfN0=LP{~AVh(E%u8_@U2P2pW^Bsa@nl|MlINifS9(AzZ8=ZzGR^w?q?(<1fp
z@VHD{{;2X9YuE)u9F6{h;5Dq<L0I14I}u0xCRDu2I7(2ch1+J3AMvJQ8SxrF)m%B%
zGeP@QN6dOQV-IhAH|v?sT$|w(2G=ao#<4x4ViZs~%k>(KevUtZ7at3OUdCDs;W@A$
zgv?CZUCYBZypePi5-m1vx?2OUP<RO0&(Zrc!^;w@pB`q+maIYKF|Y}P_bdpUg=G?$
z(|FjuG<}L<1)%kz^cPfVr|x(f@}u>$#8(jWAwqo1a82GM#3Ndf(P^2f7o$x-yq~fY
zzY|){-V{ty3T<a_r_p#O&Ap5gE7%Mto-4E-M@$*?o^e}7tt9;ZDE%d#g<yt^VY)5+
zc$4#by50egLq?NFWMCRiH~{Se=&sS_5$4lP>kY8aFa|wh^?w*>8xKB)EI*dvG$k|9
z@(@{G+#aP?H(CF&0FS6UfM#d-=6=9!AgZsY&lD!+@1~^rnBBcCS3(oh16-A>Q(kLg
zq<mAFIBp#FwCeB6WKB$!%b<yU>{IWsic$|v1fcgdi21N{nX+k37?k(%Rha3Lye9VJ
zX<`>MS)>h!@&nU21A#@dbxkaR*nU1e^N0Uq&y&nFk%ucp4q6k%lo^mpXd+n-OA{S(
zha|fE(?mIK{gtTB4#`^+6Cu#eswA?n8S>UFLK*#axv!e&k;rDzib78z)8mq-E(VzW
zYPo-!=#m;}!bbV8DSu3c${0B&P580q0gT{h#xznwn?)7Mt>DqrIzzp01t+D<NGPzE
zR@)OwimO-EC8U<xS2`-I5*(HBjuoZxZ&g-SB-B+_ue4Vcmz2twig-t<-C>t;%WKM=
zPa-m0d<s%?mZr_g$X~iNeClN9lBg}N&VlG5i?Q1lY?y4#&ZD+JU5s1NL0U$3{;T=9
zM#P99XaD4Nu0~4KXlLcL7|k-pHa*@peX`BioxI2h&#@etwJg9CWEAJrnNp3OoCT&V
tBQ|$|smNH9o98lQGk(n-Ybr4w<VKrXjnKSk(=}r@_6=zd8jX3@{{gE~f0h6M

diff --git a/Debug/Libs/sta-core/src/bus/uart/subdir.mk b/Debug/Libs/sta-core/src/bus/uart/subdir.mk
index 7e0a741..d142281 100644
--- a/Debug/Libs/sta-core/src/bus/uart/subdir.mk
+++ b/Debug/Libs/sta-core/src/bus/uart/subdir.mk
@@ -19,7 +19,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Libs/sta-core/src/bus/uart/%.o Libs/sta-core/src/bus/uart/%.su Libs/sta-core/src/bus/uart/%.cyclo: ../Libs/sta-core/src/bus/uart/%.cpp Libs/sta-core/src/bus/uart/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Libs-2f-sta-2d-core-2f-src-2f-bus-2f-uart
 
diff --git a/Debug/Libs/sta-core/src/bus/uart/uart.d b/Debug/Libs/sta-core/src/bus/uart/uart.d
index e450a24..3e4f32c 100644
--- a/Debug/Libs/sta-core/src/bus/uart/uart.d
+++ b/Debug/Libs/sta-core/src/bus/uart/uart.d
@@ -1,9 +1,9 @@
 Libs/sta-core/src/bus/uart/uart.o: ../Libs/sta-core/src/bus/uart/uart.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/uart/uart.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/uart/settings.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/uart/uart.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/uart/settings.hpp:
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/uart/uart.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/uart/settings.hpp
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/uart/uart.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/uart/settings.hpp:
diff --git a/Debug/Libs/sta-core/src/bus/uart/uart.o b/Debug/Libs/sta-core/src/bus/uart/uart.o
index 784c68878ba6bd958a900ac1dfe1d43547604c89..006a72d9d031f62ac79ba4d398c353ef834a91f8 100644
GIT binary patch
delta 8383
zcmcIpd03Uz*5CVm&wkH2a1M%q3@W3DBL@%>2T}y*6cwC9KqAGfLIRZyzB!{fzvY~E
z&8gH(aTdqaN=q$G%c-<9y=rQu4QPGqx9t0#=llM-&r|oiUDsOg+Iz3H_HX^xKHl!b
z3Hs6r`kZk2@}`JnX`V|FB4TAXA-X3D;S&G*Kk}0fLTHTwlgO=0<9UA}<O|;9Y7*3y
zU5?we$<@R`u9iVh!KJCvUgXNEORiSIMeMSlqb0e02)TL$O@Pa$*0(0t5Kl7sGJ;=c
zpWUk=`BM6mYgo`)xE!iM9JyYMAy;AWZg$yUOC#4JtELucIy%w9o1sW7i>VTAMHn(l
zl%j15MJgH9i0mC<NFmqvA^XEn#Fj}q*+;_=RQk0b`%EzVXJnFnDTMu*v1DHh?j(iq
zv#G+-r9!&9lk0lOKyvA(%|5v$9iK)qbpKk75o#h~qzCyCszNG7cDNtmA>@*Dvg`Zj
z!_J}9dQ-pWV0#9U9p{e_G7&+O{g%T1g-+>h{WrpXq8-_3{*kmSYd0smOF%5_Zr@RR
z^dA1L@loD{>^=cKU{_LlTR_l393Bk2cJOi7?YfX%C-@xfWINe)L$1O8EZ!>8Yj-_N
zP}yRFy%1uzAK48<YQug7TbqXh23fx=*@<Dezg*mk?36I}y9bl~L^%5|TF3Q38Dw44
zADGG1ib}e#w{IIE-jr@&EWAIV?*CKPz=DI?Z0k%nti74KV1GyI)8Gx9M|=z_Da{j3
zr*~@tGPpKfR@sou%Te<o?Q!)PKq6~^kRdyQsVkyRbO;sURm&A<6T<D=n|7N1wZ5dS
zLKrwv*F|}1dON+3(S{@RrydL;ec-=B{6wOz<jSHyHhidb5`x$JQf9acX|42s*1KW7
z2F@#G{JEooR+l{9VVzU{+U3U9T@_GoZ4li&xHgwAjJmWTbTctKks{Q*V?`QKb>6B+
z*Qlvbl#9Hz=#Om(5`=BGa*YVN)S6(l3~Ul6#8~pqra!*_AlBuR;p}gnG@?4-vmJeE
zb4x`usysj+;+y~8i6!TDYNu3T8L;~kourD-!mb9DB%iBnVc)9_vZ(#K&84&>G-A5V
zsSFpmqZ>+vmSC-cgQAc=YICcw8Ppn^{)x?peYVF^Z&c&)7N<>lxpHW)OH)QetA|$`
zx!9WKRnN>0pkp?hptMRnqNhNKM$I6nv!|LST8W7UWKu3<LmECMCeRcs@sJKHVN#Qo
z$R*}bglNdEGzUs_;Qfa**grRgd}|=&317(Pi3@agCEZO4cOc}HT9A8*M@sywC*-UI
z$TS)sB|_66zjQ*bB~+ETNx&)5izYycdFZ}a>wuhJ6H;-qgS@jlwMz*nQB#S0zT{lK
z#(gshu2UT$@9?pA_^wxJQj}Q77#!>jdjOa63MZ>*2v0Vr|D6kcu?9S=XwZ}xjUf@2
z@*wx|{(&676{oDp*yz0fdb){Cp$y$6PTY;=Ux_+2$x0k!@NaO{?Kw>r%iprFx}A|*
z!9}d47f*@T`$1mwfehyhyvUfPN5V6J5!%Q_+@T*EB|3!)lhkE;=9E~(EvO)dDRGe@
zdNCb#onXif10d5G(v{rT--F=s9R%r#g^Xgf+UCHnW>0ULB_&E)L%zUGT*Yj-%vtVJ
zyG<p|^QL+9h|_sa`2j=Mn%)8>?lBUHaj?&G&|wU6LzW-Wv{To!A*;D5R~Yb6ZdMuZ
z-^FJ)aao<%Z}0`aLS$2<aYex_M{(i~+?zZmj-wAkC%7R8_l2As19?6Zave8o9M8-6
zy6}`RDn>Ny%k?40u>A>x|0);#17G+M7i8u}VN-wZ-(lwVVuD2pNsovU?J^*{amtst
zi%SV4CBEjt`;;4ZuK_&MLm^jmfc%xu*7t+Gk8zD=t}OG0XEQhYoBpudTg!X`&2~@1
z_6dg!qrZPBF(Mvvza4TGlc5`<yMV8Bj_sLT`ArY@++tFH$HU}dj88H1cJrtga>i<|
zXX;~O@am8{IJ?#4(%mfYGV1w!;jPS@{e116+yRUGv#}?R{mO{ub1Ua@`dK>sF78Y{
zj&QCsJlpu%_c_7>9;tBdz&(DqZa-;a(<rWVAm4sHbM8=0__MeJZ*z02>F1Cz6Oc_9
zgF?Rjp|<e6%R5uJloX~!b}IY>A|Mr~_fLntl>0ND0?`|0=NYWSA%Zz&0mI&p8$Ffp
zT7&O>sw)oE;vzP42#cF2nf@&}%}PGIhk^Z^@#w^yo9%_O`3}hUxVilqi9g6gGkB7d
zz0HsG*SuW8WS_%#J;{A-D{=Tbzg2gcXN#G_4?4m>mz(tw-}@bA<X$dlxDQrGbLs2a
zz^-P@-e7+?m|=?33|bCDG=UcyM`3FQv%zc*`xbX}Jg0n<2PK8cn98lmVL6R&|B%l%
z<q<i<h2CT&Os1jP2+_7Oiffod=3VZ3IH%bgi{+P?!{>Q<)06P5<|(+qx6EJ|*KkvY
zb;fE-#$azx*tZ$*EBsXc&eR*+1O5!g;B^D`2*zmu?|I7Pu9x=1f|UyCVNU=Djpm@Q
z4uXGbIAkuj1AmR6mx&QN!6lw#{G7euzrt~fm>FZ3&g=MMS9s5xJZlFz{p>Ik2RuxN
zRIWFdX|;~iua{VTfrsi=8tl&8KgIW+$)V48ga024><Hf9i(B&qx1dWfRwMX&l^ogN
zqMN3}@9fL`AIl*IalL(Wd4U<bn70n*t@AnMG=5=+Y1os+O}WK48_4^2@y<calHl&x
zbNvZOAEx$VE-{`PF@a~K6_K6z-=1A{d8YUA<M1<wm>+?|g(;8(0m;vpT-})mEkoc5
zsR1c_L$33K^yRyb;l>@U4^K6}??GJR4;;tISSEuFrpV<$tGH(k`ryD_2K*VGi`N*&
zPx)AKI96}+%^Gnd#__lwW&iYOtd?+`su<X}8T>bx&KtO_BaB%;#(N#_H~&d&G{it2
zl@qkd5Wf&;hWLU)7~<3b$eKLUJ82>eF_dsJM9(<LL=N|02$JomaE2)5;xe<~N#%*R
z=&T`rY6Xv5L7peSA^zZY&o=oUJ-BmAndc$A(1vSoL6sUJHw?#OD7_L5c=a1^_~ZEY
zKhP;k%w?@^3ws=uWr!Ix7l!clg?x(}cZ3>Yi0`RohIo$N3`3+Onh5%%6LL=yr0+n;
zNyJq{yv;QEwJ$tv_y+VpcF4b?H$1`)`{xWuITUg|6>5kw8)T=(kSm$CHyHdT%%_Fi
z;$=LF59>1j1@RN{R9GO`9H~P_F9Zu>gYdQ`9IZt%=_m-67KILX+6VuDVoIW(`c{(6
zZj4J5Yy)4O2}H@oHFT2CE&{z@I0&+hJ=2opxJD>{vK$Lg%-M1SSUN|Z15FpnBmzvm
zCCAq$wN9Qz8!Dv^dhC*KVr{paPR&<UG828@Bi)TieIQS?Cv{ww0K_x$D2hBQ7ZcX%
zTe$#qd{bM6wY8c9NN&+O$CKJ>YF>C2wrLkaNp06wq2~SCDinH2s|A96r5#6@Mfw{!
zu~<KqLu!e>y*H_qdTppxdT$`KT3=4gGuG*od`Z2h5AQ<G<N7f#QYZA`7?YE_4>d`h
z*28e6&vnxm*FK|bk)&?v%X^TTXUhh4*V|$!n%ZdVOsrCswh{Q+V%r7Sw%NwfQ~S7S
zb8+*iaLUEspV{teWPNF?2Jn|{Rf9==Z@WmWP<L#dL8<ZTHn>o(HYZq-L4M{bK=`_<
z5kzXCT8uiEr~vF-rt08H|43;Fc2Xr^62DL@JftqF(=>DHvdRFxuByIRyP*PTX4Gvp
z6HL9UO3=W0hG<S|nQ;(XRvLG3p*6;*El6!JicMfwX#_x38AX8ppz&cMsl&#sfuue(
zM!QITZFB%Dt{L5M@Rrd9{k&sT;#{?n2Izh_`UH}iWPiCGsX6x70PB2vV?<eGUx%-y
z_OT%UD!Ui>v(~;U!X&-UKDafhP4-)8&ldY!aQY+rXSt+4w%^D36ZRn(j4$kSfXsP&
zv=6CE_R*M}%l4DV`>p*ly7QfVLPt_R+B@TIePB271MtxP1wfzRIDov99a#Xj++lNI
z1}hwA(X?5PXF#Xd9NB<vry~USJ?z+w#+-E|qS5CZZPG}6<Jg0a+;EiP+#Saw)bxX6
zKYlIlJ3=s0zc>aCCiT0c8MQ)<cP>NBNzQ9{!KONWdXlo7$LY&dZ#(~JL!axN{X3D`
z?M$sn>VPu~tvKYo7)R<8r-L3eb<&A{wWUruOF*{^P9Ko+sxvU2)J<nnKT`LcBXUUn
z<V?nU`m-|`{rS!5XOMd2%tsGi^_ql+PV_pDE#?%jFF=e7-Yx2py5e04Xs&u+?L+Fi
zw+C<7P49mJ;P1Uhz<JO67m#$Ks{{|tbk|u_vA|UqgjnJl8$fEgYcr<yEms}1aJ_3X
z=<%NGbOxy{u5`3%hpP(bcAKu5z~rFoK8>yV(3ONRCtbZz+n27!c;miu9YYVUxO~B@
ztFCD%^tx*iuqb!e1i&-g&qB>{AH#6G=1xG&h3;@*vDE!5Fx=!`nNDhp`%83ryE`hA
z)cbC;bAQq|+`j1VeRm=9R=dm5uE{>9F*)TvX_%_HJ|EF}Ou1p(jz>jR(@Del80YP4
z={UatHa}EgP!GvF#gC+8FDAzMTgyLpL@WjT4L>IIjET~0pwrhRIh}55l*@PNr%X+g
zkEje|y3Ed_uL{|hpfQ%o)|mL^axRMcS+2$)J(7nLNKMv8;BM2kF&OUGwQS^Fq}56#
zwOm_*{2R5Q$iGjU4cL!qXK5@@u&HY7L%@(UurH!rCP~j_^djXo{LExJkziC8gqk5E
zT9H~Uk74?%<g*~<aoLv68$ZcH!ki%>aLA~cLIYqlNyBe*)9yqnqgg@-$=EUqsCn@3
zbB(y8xhA>dI}-**LMGbVyb{Bd_+b;0EtVydOo|vtvZYTmlF5Vds<)~~#jDmEG0SNa
z!QO8DpCZ|(DQKSE0G{DpK!|4#fCw+VgC32SA%LY^-o|N5u0e_grcB0<&kDH!5jM!X
z^tTJOP3~_`7448*{Z7f{?~+{qZpjy@l6-?b5>*=q<<VSH?@Qd|F$l-HkrD7RY7d@|
zjCI`gNJa#L{m~r>Bo(u@8Qz~}dEMzF-h;=ac@+rI>JYA(l7z;!`v5ITUw}ugtAOko
ziq>atCjxP*!1(~8URfB)sA$Ysqjzw=#Ts<0-IYX=U5`6RW?l^<`KoLSUX7Rb)<O(W
z6J&J_`dla*qNYVMi2iD$7Rzu1T_H1&{VkaVSXRn(JOJ;?si4_L*#a@&lQ)3$4*5BV
zvQuWG2fO6Zd13x$9tQ8UEJ976%Ofc8j4Z*euE}ta=Q~+}TVI!{Xw3t;ml#6aE<`22
z$aQI?rf9Dav}&r>8?~2fV^G(8tt*CMffh$or50-S@W8Cr`T^%P+D#l-s~t9h>o(0q
zncKDPgGlYriX%uJ(MF*eA7~Z+q)uq{aqz4*4zJxs?bAq7m$Wlr;uWnk@VKTeM`<^;
zS^=aUXpz9<RsGl2q$cYP(TN#)B7Vwe>Qw+~p}wS-NqUj~2+>yR3MH=6HN0<|^hlJy
zS>FJ359pH-`=I`yJ>t-R8%9xFqv-|8Y&1Jf;f&Y=^tv0K7wNafh)W|RcwfvECwAW^
z3aZA}Fd!4<r@(xYJWlsB=`VU+lIe4b3<U;L<pb;~ms2PVy)qqe>*;bH9>fZngq%wx
z(y6VoF*vbJCP8hNfjOjh$k}dEJLO5bFSWP|$#=`<2v#NiVo2?gJ-U$EE9Zgz=03R+
z<l8R~VYm*+i}Wn2gE9&9d0*}V3lGT*G~}4P(TUQ3Cvi_TNqYsin5><Dg47i4`*2cI
zwP!I*<=R=Kn5KOYPine06`3lu5l}O<>QGWMwI3;%nl)5Af%CJqAXGX>>yI#VwQ^K3
zPpe1NF_vpvD5!B-W2~p>ZPC|q{SbA*n5zSBHDB-Ap41XO2aJ7B4<-yn0JTOJUmMoF
zi1=hrYH{(%!u-6_!lKb7p3JNs%@fkfh8A>9?--j`T<l3J8eLj2y0pa8F@I!XaY=!v
zcx2hILfUEdj_hcT%F8b*NlMI#kHtR;aS6@iTE#byPfAGglol0@Eb-)x8P#lb(ddF^
z1$jdY>D|m9S@v{+hmH*|99<y(YVQ1^QL!bZu_e~P$dtcYL&?~Zzn#ByRPzKYJF->L
zU&G-q=Lh!T|1PKXQgr0s>h8bKurw;P{hvMkf4@t_@c%=m(&1&JhI*cBS<q}$lV^%O
z!}G>G?HO8FN?q++QZS~(lb<(cWKoGHy(qtI6f?L_|Ew;alH$Dlf}GNVyiuOC)Sk`K
z=u}RRqNmG77UX0WJyZI8-k1VwZ%jz)e<Di#_WyxWLMxLR_V=$m+BPPl)87r}NiP^$
zHmuS<#7kQDvI8r9bLKS-ZWW)<EIuhNu2Fb=d~EaB_;4EIgt(UR36=XQHZ*eHp`S#J
zUKD#}+14VPcEPf)?R-wVWm!XZ^_2Ck4ZEI~SyuG!3^~#&Bl)s*m}FZkpejSounJgi
zCArj6dorZW>Pxb|wTk4E*8M#h+O2o3PJ4UO$Lo7>_$o=8)nZ?UY-&v=`IPnfz9ur*
zlKZ2i%ZlC~qcr-R3bA_AcU`M&e~iqv-XK}mI=nwdtE#ZR-`_yHTVd5c&_MRGQVztZ
Owp#`L9|oyae*XpeoCvZ2

delta 8326
zcmcgwXH-?!wq9%Rv-UX$4l2@7ng&skE(*jNED=TQEhwN8C0D@+*m9F&LB$f=)<nS;
zdy3D3U5o@Z)+pXs6HC;H=4yf_QIo4NcYf3N-Wd6D-yP$Q@#2s<*Pd&wS-$zrCBx-Y
z^=DJ{1;O&lwvYtrtZFSpNJ)wiFL?;z5P$q554|FU*2Jd;nRRLG@DxH$a3xc?Zx=S%
zn);9_+(xFBzUeS&>Wv;`T3DY<iGF!(vR2WS+&qL#slHQTvZyslWGanHAX}Q>61G`8
zHzr$Le=?2m-2{_O4T~nz?l3at`0Zztb#^kDE|_&RALsLqw6Qu6f#qgzTCWL0L|Kb0
z+O9x^l9^3ty(b7E<eFZzJ{AbyvV~6T6G3n)gX3v^!H?}zd(--wKid~X(z@EOlN7?k
zqH=Nzgw(r|>8}4kGU-l>^{tk4eHQu9J?l1ws|vzM_w^uDg;a{x!5)MM0n&liFL@5b
zI)g&%%{<0o9Xg2C(VlQ2o5N{>$8xNHpj&z?&n;|kOY3CM2DB}E$I<##uSl#@u2OsS
zRL>-Q90{j&FRxUrKcw&$FW*XB?uoUx-)XGlU!`?Dzpt=Pu+qA|e>K*%W6eC>yNgB@
zSi<~V;NlmegQc;*H`Z_CXj~v*kp9$oOY<PqFBc@zx^)oS_19?KCYbGCnx}OiS<9@}
zA3Gzd6=hVftMz3eR!cWvEL;y!_dk%ev0<Y&TUt|v-kYck){mq<3s#?1&4uvIFUS&h
zyK52w>F1zgl?B0EY;~T|8Aq=HB>D`Xq#pTES46#`{*;7EU5AfF2sdj_I_dPRdzp?3
zVc<r6jpEdCwY#3A1E14R02ag-*e?-35vU89`p}OBAF2Zh!TWtFGE6zNSMb04DcG-#
z`$`%AePRynmcBS)ex*FMz;N?{@(Q@^OO^Y1bLzsVPX_{Ph}q4_L!H}Z1EXQRZvv={
zItocS$Xb_vEJF|=sK(4RLgZz0s?pMCWRMUO$vU5Y+&59rhS9>l*sL-dzJkxT^r<Z@
z5TVHOGx`v>{^umN?7OL*QU#@9y_o1ERZJh8YE(vYR9U?BQ*BTcwO_Y5lvdse3%fEj
za7Q<k3fzjlMmF+7`h>+z1x=;aSoAL}wb*8PA@wG;UmUSpl#7-@XC0a{0?kyHm*oO;
zmP>%M#EY(3EP}!+@e@4-O1vHcIh!pB^tLE5&46r{2^mPkr^E!BVkHu3-jyh%CMz+T
zn4?5eBgh|V4wOjX^M^I8o3qbl1F=5i4mqB<poFu8YEvSG!_26Q^;6=J65n)(JQ)j_
zNaLe~XENkvJLD!pRf)z#PbE6h1SnCA?u$(}$oJ|%J|$)<QOPHZsa<rEsHwz2E^;Q9
zanDK5suIULLe}uLkGR&aX;PH<m@(MX8S5pSN<IfW))<x&>YEZjbE1=KV_iyvro?az
zi8z-9xs%VQvHvIznabGceEwPoCk}-(bk{iW%qFn7(<CbzK*&b*AX{*l6qXPAz_OW<
zyUt16rWa3%IsG83Ye9N*0b>}mDGgxh&IqmNByOj`GA&RzNnNC8PKgT~Yzi?<i7y$V
zF&(fT!0lMeU?vTOrG)$XGTW_#U>Ow&*^tqS&A>V#3UVIJk`g)e&?u41O<d1xxX4i+
zQM;W=_y%ITxFzIc&i4RA7fo-05_cGhH>0ukWv7D~Wc-6ejiYH-V&!1S1V-*sBG#{Q
zv$k_uPx$UePHP(5pYi%UJUc})XXM9n7zciZdy~b)dCuI9b%WEMeIYBuAkX%Oyvrf?
zGq*pj56f0x$mCGSK$crr9%Asvaney-@IFq$xuPMCF6RCnVQ!ZYEK0PYM?{JEG{~78
zau0WLIfER)gLjl07s<Ov+3C_(aJ~goEQ_89A|T^hkGZna6_y%q^yU6ow=-AP@^Qv@
z!@6rQWDx!Sp~S`*$O<cD(TjOu%Ab1)79TGA1ZUou(QVQU_NzQhqZs4k+{yhs>Kiy>
z0@rw$d(xSAOPSd}Iyv<emJb;9)m+lY%$wi1?7iH9S=^uX-4U#Y5go`}Ji`Ug(_z=R
zGlSSeRcBasaoLa9!#M_SF!S;b_x4sdCk~C~Ob2rHYnXF~>%gAE9jNB!+IUXe3D`$6
z9vhgE`&z-Wj!#bFR3<ScdbfvtNeHCk@Gd-3m$|p&$&nKGtUQD6?81*jW;5*lxY2KO
zt%~bD-US!ZnnTvGi&@;nC(Np`9A+Kg{Rabkp7ChKyYpReYnTo4dv5MxM&fs}&<s{_
zuxjpN0QYYSlYIf#`Z@QtmBi(1j6pT?YyngFen;46a<dHX?wv-kJmrK&*1~!?r~bjq
zSSK)JR<M0AnBf%e95{m^n#vm^8scagv!R@yxF!tvcn-Om2W1kI@tyiOxt!%Ju0E0N
zIbN`z;zaK;66H+8awcyjqqu@O<b1$gAIxE%as_)BgR{K7u^R{ADfk;#nZ_`#;HC^_
zibXI6JG$fKEe8A&Kb6m!dOcHN@5mS|;a7em^P@YTNq2JB-{^-!v)V&OvBj00)?=sR
z2El$f7_uL?1HVQn5z7c2;S{SFzu%dLm)K7>Ka3-p&Ud-6n|$Uf&)Oaie=5icN28by
z?K$6mOsfw#{3jB-xja-ild&#h&OhZBWg5Fan*#eL2KEg;|1P)SEpEYdKkWK&c^|T8
zgOhI10rubfF#q$|MGwxmYbG}A%-9k>+LMpYWvD;r7j}e(Gb!AZCY;bfKEIVu_F$IO
z?us+l+CX+?hF#<o!?+O#c}B+3ED--&uxTJu>={1}-?NJ^LvT5xH6%emvi3`m?U@G!
z{#g6hhJ4Zk@~#J@m1`ZzjkAWrlE6s#a*98)pWm6731EX$tYAl_+_U<<aG{z3U(1il
zS-yOhuN4Mk_Xbz?I@i6Qr`gJh9_3&;?B~}ooNUUTzhXMC<+REfvu=#{T|V!;Mr<@h
z8fSEb4jJMH0?iO!goh!H4}eVNnchMZVTe_1pF?wOh^FlB{tyKFjocaH4Nk60A6Q!Q
z#8=T>L;O7v7B>ZXmh6Uj#O*%i<T{eMbBhLHyAE$mVB&;RriNG%1bYC5SE4@e-g1R~
zG*^F@ZW&@5r?tEl)&-Q7A*Rw?7{c8h@*93pbi$I#qm~(>jNS}GOlt0g)1T~+Wi24B
zJQ$ORtA?m%n$+}#J%%etVLX=hghkMUV~Fq5AfIGGen*KKqR;|4ttn&))AsrcPH>y%
zaf?^-C?*Cl|63D3;ZFti!JIZ|2N^mKEQsujw=MQWU6L)Vo+Oj~(BV$cU>~rVf~fRw
zCCR}}QAGAn;LGc7NO??cynJuY2fZg$f@~8{wIumY5YnG6cL5aVeED~<dV%!8&1JF$
z0jAc<PrXTfEImP?GWjcF?vtyrw_hHm=Bskq1${ptQ<{)EDvz`ybz0^C#0#<l7cR;Y
z!diVR&w-AswNmVD(w>7gJG7!0QahcRz_YMR^Fxz&YwMA7g;t70uW2?My{?^xn`Qb}
zxKW}X&mdK*Z|+HIo$i2IulEE(8}uc_JmX`%$eq+yeaNe1JguK}A$3MykMXI}yCTpz
z-3yFAuRFT~)C+ps2BhxmOHxTKvh)UZKd}UW$6G9|iB+o1l8LV!mM4I1m!*Ja{zcPf
zqVk5`6pO$AW_h5|>ayh_fWKkc{u-$tELVvYs>V_TN=;Es5w2L(#F`C!J)CvW#wDto
zFR7*KBJwO%y>N1+a>v_pT>XMls#G2(@she8Me3?@$JY(ju^*}1Y7xG^Q?4nbzE{)0
z)CX!S=4g@8I*!yz<98fcXWT|X8;zs!q&6F4oWQQk@PaBgvH^XialSdJBSsO%;h2%@
zAoY#m^d?np^vA{fMjQ0A#wf$Rr$!>6dv474Ays4@+m_S<>si$Ko;4U=mRaxOYq@nI
z$iLnyz@JUln;}lpA6t7Sk=kZ$g6elz7lPBrt;aG+owDA;{WI2548|qv7eMA~YiKP}
z*Q~jioEug*fcLF65M;h%ozRigPu3#P_p!Ac{{TF*dLjH&+it|2Zc72M#Wsr#GdRa~
zQKQd!wsg>Gv8@EK?X~qsy+>>{@O{zNv>mChY%$5CZrRGv-tTOMxL0FK!aV+H+l7BE
z9@+XMi(hPMX#I0rLu!SZV*eUGi|kkMg3YvBx|1^Phw00yKD0l2nLa<Ur*<N>-`>6s
zsn6^wXvJZ>e+;QF?9cJGR@v<c@ufXqkh)^GfRwlGeQ@NSy&0JB(4L72`Pm*xFQa;5
zPe6bEVfQdd{bpYc5GK16p`p`U&f<u3hKm;_^or})08%$yKLj+lUBB){>aJ@j-mrVF
zVF2L=*Gw26y2gi)n&!yCLo?g)1+sYGQ5S?Lb?m}RvdXa?Q@hsTjuw96cnkE{>Nt@`
zYKLPAhG>stJMQgwI;H`WO2;D_TXoFQ3~s6%osipQ#|R9^b%zb;-E>&NtJ{vxk?38=
zd|*-RW&q&1ZX=);xY?pfEp}@RpG)1mfyHvS7653QTS*5}JKWCnB(>Yk4^QkNH)req
zq`z~sqQ8&aG7$Hv+YtnuUdtVGP+Th!Q?;<xLAsAAH!QndXrUg`O~a_fed|iP&M$za
z2gcK&9+LHt2T9uwOpN^j^^;G8EC>9JD+xVgnshe8qgN!4Ql&<*yw{k%X33u@4P&<K
zokd@BWM6{DSSiPc($^|^8sq##ZonY@CN+Fb*D_JtY;7cldx=(pxXUyf9^zG6F{;?2
z4MqHe+H}BvQuB;>k&aW<eg+r*iC|wyd~cFbH_(gLXF==UonlFjZUa|yrB5QM4e}(W
zuUwAkM(VVjNcWAOWd>o+1rj*4s1rv6V1!Smf{bSEiBv{Jo<GUR?c`94!vE(Q(G{6A
z|3*w_!oY~_g7(Hez<@VbnA-To2_#$i3?$jID<!NFdcI0BaS(Qs)?=2FEAXtPq^6VX
z)eJNrJPekRZ9s@OcY_EMR-;E#q(5LOmQCTwl;4JvdfzDv14*xu@4~}o`G9`AP`l)=
zc9hW`$=UCfoc=z^`R|upK)K`!4oGBeRLY7>Qimiec>%&_AdS~p<nH$+@~xK=Kr*CH
zLz1B#!Jx1oBk=x2^v7_=MBy=s`xOL8+=nt-CxbX`51=I--o>NV<uTgaJrJ$$y_pEa
zp?u~7h=A=uBpcSlj5S$}`|&H#t+q92f0xrXlD!-Fk(?}J!K*3qH`*Vdrpl)n)}^vB
za#|*Rt)xn%H=M4K9T9!4>;qWV$s{}g|0UlB&9=yR_}nV51L-}oF3~{km4nfPeR9>J
zAW!E?OyfD3jhxO)J($!5IT=+|OK*_pj+}$4@5*=3n#b}fF@(6CgG_#rA0(5Sq2&{_
zYNj^NmsGJf5_!F+&A>3cuQj5nQcE?DR8ku>6F6_wZs5WuZNC$^?$Vq{bGNn`qrFGl
z975`I?ISefsCLYg)EO-c7cXiBc<rugwa}t#ng{rQQ|k;os<kUf?VgtAMe4EE0C-H+
zYm!J!*Bhe~bM-gz+t9oEc7U{0U)Y1VO~1J$!P`3hDe7IX|AOkb=^03WyS^6aex_H#
zccp&69sJPW#(w12Xm*7n8xbeSoe{a4UUwsE_e&(BCleBUE^LM!r*C0!nl_9iIZf8W
zV^<_yiPcW}MXyZ)ea?`9z+k3~!<k}vh}_UC<3!c7WicMaIkFjImP&+EJ7rUFVwY?I
zwOhJnklG{XgLr$T8|vIA%MpCP90O<NvPT%H12XwlQlH9Vu-|!5ZUgx$<US17XYwjN
zi>gvK1APw3tzh9{ITsB%DX({;@OLEYR7Ki8FlV}UwhgHnS~!l()J9;KinT8gVwPr!
zB{f@n8<FN{nNV}J1PsBu+IQqk%^Rv6!TtG~FEU-AEe<BNP%B0ji!=|Sj<HJnh@2Yd
zG{$;{-U@v!)(=w`jD<SjR`2O;sW0?PXJ2%1tKN^E5Aj!OjV?M{&4(c|QOQZ^z5CGL
z)VSE>!lBt+I&{p4iHwPkjQN8teaxuB5jnZ}>1O-Tj-lgoa^qrgEHXMWHaa#gIzBco
zCO*1FdO=>^sQmPyIk{1hk>-ZbK-b7fTD|yd9&8Zwr$+OM%b%Dp{>=KkqyN-!KIY^`
zF8{wF8~rC8bN(BCWQ`pik(-yB9g&?iG$%bLci5=H;o0fK!o$;JVj|;+d4D`mFtTv;
z(DZRFvm-`_zdj~?WY*Z>M6m+2HmYxa_SpQWVOe8GjgRV(o&T4DyfIM)fq4-HBk6Qr
zUT)O*ys>}DAComKn-1kh6lCWY<eS^V{9FFZ%m4OnV5_LYtg!|Ep@Xt*VTGQp{#EAx
zcW|n3XyJ&m&{mB@%oRg?$`%i{%d#Cq7B#CMACnjnlh{0_N$?8<gJ~*bqg%$%D<jG>
z=4@_a??*GQ(Zi5i=Cw1=qP1FV&e%In>$cc@zPGz9GE?`BmpjZO`_kko(`$d4ykcgP
zTyE|pdEZp!kbOx$GuM+GZayMeWOh7|CO<Kk97xl;Z8574bf=H_PjPuV$>HXCl5@?_
zgK4tdEIb%4Cz~G}Y$!*WM-GOm9D0W9m=EcDqUlu;CM(R=B>!q=SA=Qx=bG~>8fiV|
Yn!73*$*tzqiZHc&r=b7$zp>xrpEf7yH2?qr

diff --git a/Debug/Libs/sta-core/src/can/id.d b/Debug/Libs/sta-core/src/can/id.d
index 87e35c5..3b68ea0 100644
--- a/Debug/Libs/sta-core/src/can/id.d
+++ b/Debug/Libs/sta-core/src/can/id.d
@@ -1,3 +1,3 @@
 Libs/sta-core/src/can/id.o: ../Libs/sta-core/src/can/id.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/id.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/id.hpp:
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/id.hpp
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/id.hpp:
diff --git a/Debug/Libs/sta-core/src/can/id.o b/Debug/Libs/sta-core/src/can/id.o
index 8e56e8eb8edf62b090a41432b326a07a0a4b2f88..a40904ed144f76d1640a302b7ed01d999d48880e 100644
GIT binary patch
delta 7475
zcmcIoX;_q3vOeeg`h49D4Qc?99TY)CXf_dvxUocxEQ<Sb5e-osSt5vLl9^U<#preX
z62(1nCD#QFXfPU0ToPsyjoI8{Fgk;pXf)9*PFyneR%V{(-rx603{};2&Z$%N)?24}
zXu7GL_(oe1Dg*b0O_i>sCxr;RG)#zJ<ArdD|NEcZ*-r>9$~T$Zx-_c2gpg70<cjW;
z%`V$*A9CHalB-vz@o;G>Y6!U=`;)7;Upc$1vqqC^<XCd$bead3Mfs+X>)ReAwLHI9
z*k`pzknbSnqD|>k50_1a1d?lMS8|p39b%WYq(8Z4nf*0iSL;Apcr_Ro%jYN)ZF2~2
zl)FZeeIOWDNqZ#O%^|o#{yCTImSDt|pJ`<OEd)X3)&#Q8`msMZkL*@|_Fs%9`<h>t
z6vES@O3JE){4R@JH~hztOLtkUww`o+GR4rnpXiQI^9UoolUEw-hjd&I^~#4`J%H?R
zZ)}y1=xV)(S2gUtBgl^PUIP0o5_*c)df2-OMZJ%A1MFw|ke%+`neLQzabyqjiG`hA
znnWLRyi@TZKZ@*OJ~^;GsHqm8PRDR~e=6A>{Z7MPnL&1d-$mF#)HF+=|25eC%#FHl
z_F6*966xoL2rW;L-Oaxv>`B;}7z`9-VJ6v0At+z|O0=+~g|L6YNV5Bevi}?NvF<Bx
zn;k6|q>uTXCDU;`l(-dtT^HhsN^^kfX1F<p=vZ%-E8j8Gi5nfZScE8~p9uP~Jo_IZ
ztk~!NdH>%Q)8YT%KSFrnq%_>FrT@14zm|xs+S<m;szwXiNt_}cso+|wNRKe67SeyS
z5Vh`gHC?t)x7EZ;-JvOCp82}%N!N={(=8U>X0Zq*=>JJns1m2Bze<duhAZ*V2Xce~
z**p%?{VB-dL@*^TdqWP+f&8ARr9`K2$UjkwlsLirClLpf*vT;yhyzO4IzYO72qn6b
zic-R}Bjj7W@M<U6KM#g%Pb5%c19eu3do-d-RN5i42plCA(IhLepOZf4345vy@~K{s
z>j_dNCi2ehL9lOf<Q6Wh%EfiGWMQFhAY`}pkS}tr`MqJ+Fe>9RU|-~LSNXC(64pvw
z;N;v1MkQ|X^*PiiB?fY$QzpO;=Tw3@ejwj?z8m~?o-U}}10Wk1y1jgHTqHc^NXQQv
zeA5qh4&zb8a(+HMGa0$QjKK~XMkPXqLB7DLEKPx(M~otzLLryaa4E5plX&DUT=bzX
z5Uy1;fl6%R7M$T)2Xd7oI60j`8#x?%T3Kd{hkeZ#awT{40L?$)!B8I|mMKx&1M)}!
zWGiFv2{$pF*$_y><x(Pwn5sk!C*i|gS;#^28M?Q}V6|ivWJ?U>G!7cXARlJ`L>f;e
zqIu^PZpuu)Y$-R(!utorVoxHIv4#DMVY|dA4snP>{Do!ZAZ$I#0RGDKyvW=>=77JA
zVPDl1c1<4S9Bx);u0EP;9qJ2zSQp4cogtU8eVf5g=F~H|U{@Arv@#5v9x#;(ncJs%
z3eIxqAxy4ueB}}DVii;JI1k>!Avo*c)k_?74pZ-4rdVhJRtGY!514?7?(j5oqnDYN
z96_$mT<}UpsEJp9Vtc(6JMZz?Y{vCc5<Ks)eUx*q;+{0|s4wHy4t%zrIrl?*?4QPW
z*_fRjxf>C@YV*fxx{JrMkW*jI?5W~nLYcgtd`+qcwni}}4m15d)8J`i_{Q?}J-An=
zbK#HW2+J7Cr@5qRj!@@=)n(kJUEI}Q2JsAT=S&M3*KnppJN6VY_62<4C7w`f5{2l_
z7~JP-f|=AhlUi{qSGr?QYG258A&}h|l{;Mbi`<$2;sTnjJcA4QrCHDpTL&}j4o>A|
zuC-x2{9`!K9v=0T93qXI+Yp1*xxBiB&rV@rD;bZ6Tui1L_H?m9c4PXFW+aZ1hh}g+
zUp9fW&f#UBq1ZZ&Ypv$K-eCKG65&7D4>FL!Kg6th*bAQ0XkHD6l%bH181~mQVRz&r
z=X1IVp74Z$87{G&LA%5A<;x4Rx$EC@1p!>~z(F{m^Ofn`*TFnlH@Q|jH>ixO_hNrE
z4@VOxx`gA*VHy@kB2E^!vZW7fR}EjhnHozkEO+z~WAKodkMPCr$ygo9lx#<!DUrrx
z6dAA|4uJfCn^nu>J$VE?CR1-}Htbr)V2T0TlX1E`9CnL~yZ)E~ulS8J?77H66FBI7
z4!1uT2ikKxe&k6x!<Aj)6o)d@N0_ijIgSTEiQkOGsZ=g(GVi&|vzE>=*Cn~I9LIFH
z>jwKFe}hzTU(+QY&VzinKjc{sG(R1-VsbTQ!5+%MO5Q(#Tad;ri0g#aom}1oChS&D
z+REjb`ON>9IK+L1?i}~{DEBypt4!vtPKJ7lFT!2sYYz5={Q@V{j#GE>&P!wAf5<VT
zxQS<(VW+sH>D-7O%$t)mmc;)T*cA|gW9=E7=Q)WBJXFV1;irO0TDY<U%yx$#JPl0P
z14Cdp^LN=guGPhj+sgZY;kWNJm-HdWX=P$s3_9f!Jvq=k?%Dku1WI9|#d6lO7{;A^
zY!)-%^izBp*B!24-)H}}F0k`C&hf6WKVtAhnA*L#t<g;6*^JG5yx)~cY&1j+XY@2}
zGDL3z%@CI<gdtuemKq{D9N{jqzld-$#8sMOLu}&~%w@p8pm2s5#mRlijM>Fy?4h%U
zSj3ne=Z0p{OJIn3OwV8!1)^7pJLk<@ZDt;H;oL`2riM5aggrUj%M-jh+a3PH)IWNr
z=#(Lj6LN$nHOmlxr?d>QhUUT$gXtkR#OGnyd6F7oh_N(Zh6trM!w?tZng4YTEKlS?
z+DR4DjPk_=Op_Y!=&KCfW8$zOCUBcRq5BN6i$=~6we%hs;u}iT5METJAp*KVrez>n
zF@vASe43UEPlyL(NdWV|g*r{2gbLY6%}||dA-j$Rh_T0zLc-$?B$Lm9VCe!K&Pq=t
zIXa&%QRBY?%_f|;kt|*VzC8O{KFNyR8p-EA%OpAbWlB~(9|9!*d>wRMAa?>3*MG}J
zIKDz&08Q7(aso_kk@N5*?34%5hDP}n?tDvLz}g}CAqM}jyo(OLE$>B;dSC8JBXwGK
zNg{Pt?!bX_(m`0Of5>{!@l|aE*6OuVAlamSitg=qX$t|)0c{#mds9o-Nxh?W1G8GS
z8mP-!D#EPMeVnA$>LW0n>+~6D!dCq=6thiV0ED*dQB=6GQ-7NhHTLSef&OWIE?$R^
z^i{#6&ge^U(P#QSWca!63P#yy^~_LGxAa}vq*hv5Qb_Hx>_ZD0EUyt^Riotxd}^}X
z0&E8?iFEI8O)Ep?T`K7={``q$IdH#V2_g=uE0!dnb=&fSh14C(_kN`2syJM?SS7^~
z|Fos5w4_XEFR9X^*>t<A$7A}6deD(nooYea>(o&k+^EhF-PB)I8k%}W<%E+uucBi}
zeW~tXqOYh6;A@+zz}nZU7qa+PB@?ZU@6<T-bEPpaj?_lu%W(QLh}vpo)7YpThG~A^
z(c5(wT{>orNg#F72pU1E#qh&~d}XAA71xX}uy)J14-Vcjt^@i9Mn0f>Y!o2t`PMfu
ztt+hOQ0FS^3A$aavHlaE)?4i$|2FF~@TcB-17oq%`W{}0eb(+Sl-p$OCQ1F(I%7Pk
z53SY6;v;Jt2IIUn6*KXLbvweeTGKH(SF9UHllq5s17_s9^{IiR?pXr?+E3QR?xY@C
z191I3+r+V?7TD|{&SKlgR#HoCGtsl<w)h-82rt_*fzv@-0O~zyTkA{eoGlxTzG!RT
zpVZ%N_tAo{ZQml%JGLFj>8{QHNm4)B;xSV9Z6A*$_1Jc<fYe<3Ld2YJFG1Oh>;d?O
zFzrL}>2>?G-lTTfW76>;9J22Q;or3f0JanM(U_D|_M3QH&)7>-NquS$$CgX>I*_u>
zz8tU0P5V1&{rC1;sPG5-L7?`teLDK{i~TZidSu@Y5azgDk0({*R)7o_y4?d;F1c@}
zN71FOx=#f(ZSFe|^oIMMbW%6n&!Vxn-TT1#y?Y?KR^xa?^QLMYMNq39tsulY$9Qj2
zn;a`Z{4I_R7}s5nm7vF7hX%Nt94kQMW=9sz9di7DT8=p;_9NwLaXf>OJmXl2>MuBc
zjU;v1(TE;gb-Vz$+Z;bprs{^{9<W&K@fHAn$-`p;sTCf>F%2(!oB<)~JT?Q1^&VBg
zaG%Ez)Y9bfat^6CJ=##qagXD}NPX=Qf%g9B^0)%n9(YusT?;%b0Mug7VvNyWJeLm;
zq-m5arFc}-HoDm`s&T({0iEX;z_Pgq83uhKZ#b^9%}FF_|3lAz?+9~Zp1O^sb{RGD
z1h_X}PQy3GVwc<yK_8dMnbaDiRzAW6ES1aK)2EGc1V((5j6qUA%ScSXBl%PusRddl
z<)&)24?(3@v?>h38to2>+NAZs{S6uwD%4TU53qlrEv2#GgxifnJbyoc;|i0Yl+(Wh
z$+W(}xuDufva~B+%$MZCWK!GZL{CzOWh}OxmPaTB;|FOaHgiO`j{#!){iq>&AQfcv
z5JV~?#_C5h_Gb#HIq^qEBW@ZMXvDV>21de?KHz`i1b;f5w1U1CRZkt)B_9G8dL6?Y
zr@Wd$vUeL+Q*+VX^o^kJU=K8W*nQA^!T@-t-bG)Y%b=vx?BTHI%3Q#*SiXixrYuL0
z)v`8_)Moh}Xz$uB7r2u?AU6<nMziGX4@yq|Ey?*Gl3c)H$rZdUDQ#gKlU&JhiBf(8
zp+CN!ecS<s-(cJr@JHYoRvbpM>jOK<$T4`+Vlpt>@jHmzE|vH$+S=QW_a*K91d{#A
z(UOeu14(9|M4NN>fItNUhW`61-<|*>=u8mFE(sW}s5^kErvuMwze+^OUXI@o3Ql2=
z=EzIn)m*t2>+|H4cBJZLt6iA?40LyG0c4wH2VA>FD&VnIcEq&okym<?YLGu-koU?`
zDqS_pQJ~;K8AYV0-xHdE=Lvbxjnqkb5*>L@{uo2*GdTqB`{&XEbyixy%WF~}MC!VX
z!XVs`qg`myPx3bI{aJ<}%zZhhKdFUU5b|E6IZ?%8tpmzlr9FeOSgkcDk*d?WXOr5l
zxdHJV+EN^-*Xn`r0j(b}cvEu{F;%nHh*#`A?IODJzE<l+>Lcw|6utw_X}$pPODzP=
zYSrd|lUKDKDEpdLMKo47wGMdce$vh(!#R3o3aJJ7YZ=Xn?jK2NnQlc(>hyeYYmNRi
zf^F5GK!)4&6R3Wlo`&q-(AQ>>dRHIoC&K78)ITNqF^!7Pq8oqsbsT-JCxCTvPMMp7
zd!#rAR8&kanOsy=QeIZ+EEt}Xn2<hmQgL=hW^7SKg)_aptg5)Is?wP`d3s4jWwEnj
z`phXMw9{-2$qX$mnp|F)oKzSei+>4m35jvN;}heP6Ox@(<>k{W&F4aW`_rbWC1u6p
z_r59Mcdv#1{P24h;cNEo?EbqKf?M3CI*VqM#*~$p6~`18O)7C#O`Taf$ywd2IHolE
z*$U^>q8ZOPCzVuH3g?K*;u)3B$wf1!msdJ7$|uh(Wl9ViHGGh>vZ82mabZ<)QK>V1
zKyFMrohr;Je`e<N;=+RRXRBrv%_ug<cIomvm-IL+xG^cb&8u-_N?iNK^@C=$%liLj
z?aU~iG;@j>HTs56VSZjg_UOWq*#+4Hhh&B(#Kon=^=@o8W}P$_4hn8OH8wWHd~<9-
z<Adjy*!_FQC&a`j$Hhg3#>dAd#>Uh3goL<W@d=`FLrrvq|22BaH2R64Da0=_{h{d<
zUu`sAeZAJAov$^^_Ec+M)tcA#<Z3r+&E$q^Sz+#O$kXbUnU5QCwdQ4J?%rHE+T5@=
zPpjWx-rk$5)o(KU?xUqm=JI{HGSvKXU!Lr5#=Mayr<#8vX){l;9n?r+wwq;**z|T|
zo*ZO)G(~H>3^TQ<GliVc6sfYh3bDmp($q!!dY-wbDMH4XpEpIy+2$i!JYOS3k~w$2
fm)U23d+9K9_D5<D7n#-jBUJP2LQFD?8od4mjrdmk

delta 7503
zcmcgwd018D)_>o<&%4h#aE=qR1A{1o%##Anf+!hanu!J}8VOec1IKIEBjSKLTxx6L
zkeXv=q6nEo<jsk)Qg4|<r8a4nsaa~?YuR1D<?VUC{`kJ{KKGA&bgi}5e)k%F>$hHb
zJp8TJcvY(jl#A+vilnQ5cOinV4G|)@jSvp;`#<uH-a=^MK3&PJOQXR<2pR59t_a^u
zcG)7l$#vCAu5P}0aA_*_VRChEN3ImVGIm)@a>@1ZNOEQQ&W6jP!jj3=CyJz&<F|}`
z*1Qn%9iv*balS9ZWm9?W$#tPKxr+Vvv&;JDKICdN`)EF{8~y0TI)5aVbzWqz4?sq_
zemL2?{gF!Mg_6A|04d~Ov&nwjAF<^rjqGCq2r8T7$v*AJ{!uw(Uuetzs7SIe`(;QW
zT3A$Z=_DcL0CHVvJAz!g%VPCQqR+=t4BfL$7lb-M80o$qJz?k2=X#*WVA%8flHJJ@
zN98Y+T95RY0(<i?vSU3L!2XPcp6sz2_M3#F-otYT?8!aIPV?+YIpx(@vIlxa!_J(Z
zNDo<_sd(5BPWBM5EZF|tg|K+}9>m8-Q_1%BI}Uq8I@#^~K8D?ahGuEs_A>0}%{97D
z<~2gf66)uM2#VUUgthgCJq9Ne{DFd;*q`jg0JJY#btAiH0Q+Y=Ms}}2_TMw_>pt>V
z)7x@R7Mb5$`a2?mh+A=A>q4|SYW7uOMt+PC-uKKh<uhUoaijGHix8veUkLrPJoTFp
zR-ALc+~>i|H2B~BO$ZNsDGj%u(jL72AFqh4+L?xns!Ho{pEyN4QvS`vZ#~4IUPvFa
z*i=A9i0QHgx-BMN>JCjArn%MD-L-fSWwG!vi$y3we=CUpN(4qg{)q;zL<-SfiD3q0
z-Q$q$2S64Q!N~T4d^`)%GXZjZC&-gDA|>|m`7y)+CGHbvln5gZC}C?2>GC3!C?z$e
z#2`+yk6)bk<wI1R5@U%3l$a)~goV(d^LEG#0!N9D;~<Z6(Pvt~F0w)9(!7+oL69mj
znooY&0d|-l<T-9^u8aFPmjTz-e*C%><TKoBK?>|DMrA@e>?khfM^5&B2t1LTzC9QE
z9j8yDK`Akm?h+;P^C6SClo*a5#Tg?Qo7xsGyneGU<Oj5sO6=ssRiUsKJO*iJR8Df$
zPdo%qIm=~(Vb5dap5r3EA{HwVOE-!VGq{x1$*@N=W`_e|uchTuVgnbE>LpzC@KJlX
zw$KJD@hK<!oO>P0T|ULd_2F?m{3y<xVwsu;JDB~|JW)ICKLN{7HxkQ~IM1GY?O@+v
z48G(crZF3$Xt`WUgcDPVXk0`HPvwvgJQ)mK!wA@;hC{ZChHT=X9t`p>_K&9ZR3eB^
zCNgsKIN1fB{ct|Nl)nvUGPdI(&V=m}SsY?Nhj@<VoPh{;fC2oK>3Nm8eb52_9ftjz
z&aju}Kz_(6C-c4(aj#2!;GYx>*@ER~EPrM2Bf0cSZrIg>D>@N`quD&gQOxb*t>Fm|
zgUn}g)p5#uJjF>0e&GeV{9(vZ{ML^d{v1=!lPMNA6mN$zu8uU=3GR@$dC+UjPaPdx
z3Ec1{MyQeBW-@ZCtvG368mwlrAMOZ`2RHmP*W4ThkChjD1>Mg|JjrqPGUsl!f@cfo
z>d)*f=4o`}xBc7V?JO4;y_)e@!t810X5y0ZdJv~cb;1r{O1#hX59kTcCk)?qZZ%Se
z=VCTwB}Z7yP!8gjrf`Ih7_wtLr6!)LdnWJTX0CJ;fvQAXrbJ8jlr#1<{J{?1&{%;p
ze_=cZarZGyYMn`)%cUen;LM<2kY@uRXD}+FFYFUM)iQ2ikCk_DIo~vMTjKRY47-C%
z*~GnW%7gy}4kWpVOB^DbhpTbuH~H-X{&ph+Tfunzz|Hh`Lxf-(<P09}GDhM6d1wb$
zbF!U0#dZ8T<PjYG6Zbls=X!<h-3joY?hV<7!GEtGY$p%vZ``*pgWoF<{$CjOef?pF
za+7Bmv-lS9JOO67#0>`R2Je>-zj%$OevLaQ<+T_(5Fh+wBxD-Tbv~0Zj7O8fvXr|Y
z%>E)zoIJvXF5oy#Ov61)-eN}a9Pgv6iWA?a!78zi`8k+vCr{`ECvMMMFpj%yNubdl
zF&SI)Rq135KILJ};`JUe3};NH-t<h^s~CfEe7_ekPFMIMecQ!TZ#e{qDw#5?*mIT1
zlEy)=bGRS;ai%?w<2G-~N$%_#m-q-nePR&Koa8t<Ux}YR2G3${Y%HIN=>Sg($J~<W
z!b1tu;RiR^PNr2Q_mn2#8I%M0K_AF)p5L-G*!MW}kqp=y8Cc2ZSMmt{%p)lA#oITS
zPo*4rBNy$<?QI;){C|-{TxaOsXIdTL87Fg>1NdkkhI%94trt1Xu_S~(&YiX7(rftS
z2h0-Z0K84*8Haa)eSus03lE~0cf^;-PW)fQu2SCVEWU`!xCn3N@TpXMObwIl%bhiM
zgPrLIxq}JY{4ng>Z6IIeUTb)8Kk@l)jKpzn={=5fgNbPY8(gBC1DQNCdp1I3GSMo-
zVK?%}+xW9aX23=6%$*0(N#RUV0OZ|Z$O4Yz&CNJCayip^ATz876L|sS?biwCUA4qU
zL-gW`^5~Eu9wN{T5l<luQT{08Og?&*{f+ETiiUqTk6<bT9!+NqQN+bvXT~&f8?rO}
zwT#&z3sMeGfoIwX*iXB-j})Gq8xyLIc`(`+uZyTsL)>M?KEbox$8V>(!{3tTN5A0E
zSB5y11=*U0Wr$l;mLXoDy`W}VLAK#RXoRI9Mz(~^r#r(Ck@3v`S_jv{i}Vt8Oh0Tm
zaShXCDNnSXp=-%_lu|O<2m>LSXyptsi|zwMgwlWv;Xz#*qBIOLI~^ydF!+mjOfz`I
z0Z#Zgw`2adBYx78Pysh-7^>rW$j;*dV)U;lA^v`Al3hJLNT#*Mgfnt*73XfCBq}cf
zlg~eEBUyNwdQ?yC8ccHHc8%oImq71nOQ~2jJr79EybHR{l~;mDx&A6Y1~@g+8(*%F
zWdxYoAP?Y5*e35_3=Q%oa_*Do@NU06IGofQ@(L!{Br~x3&9bQ{spB#xk<@9q2Ope~
z4#HY}CGQaj)H<yI?_Sns0?9@#1k-!Xr7Z_IyR|JS?R6~;*Tdhm6fo<8wiN23mWnVd
z^dfw*QXhovT%}iG2pjcFXl9c>7YJ?EQ>k%do8Cl)8awqjf&Ov561T$%{X?3LI;kH;
zqEosBjQ>b?Jq}P$>$3w%eWy3!wtn7nE}7J;mV-H@c35^1VO4`gQEb&{2?t!eE$Ni^
z!O&djJa`V};^z-6OMv@1OEhsveQxOjw60rb5G&LTOEl(LsY;NpTFs9o{%H$UNpY#r
z7O9egX_Q^v1ER}RvJa_Rr9hii>SsSvYt-jNH}#In#!yeHb)86^RWqYVomc(v^tt*L
ze7&R&;prPS5LH}Lk&hB0->X{8^LgW=SW;_@*v|CdAZnvAlGa9TG1i(ly**tzFh6KK
z6Hn@h;W3QV+lHTm)Mv&lFH)C{`*`=AVZl6a7+(YWdqx4EyKmHZlbT~agl(;{dV*sw
zSocwOwZhsJPphqVkbjf43jBH5+8I!6v!1~XQEwgR!ju}VVUpB4)}lO8?^!3HiWAo4
zNK$95Q-R?p*3AfW!J3B6`P{k`7sFT9kK2&?+M3&s)Q{E?0PT)-9)1A)Y|TZc*|x_<
zlA3F4O9NEZw!d3REwoL>%$C^tWzj&?Qrm3cwAYr4evjDBU=n9+BQfZYZ9#oVeQC1;
z*l%ptQ0NWYSE%U+TSRwKw{4~1$X#1AT}|q~?FxSIRoV|B<{bMdv_0P*iJuUreE^=e
z+GnJYdez=54Hv?G`*sliE&CM!eAvE?E?f1!{b$^*C+#yatPky-aO6|_R#5bkeJyU4
ztM<QR^f&Eapu=1C9YF0T`vlDApZ1Hu=@<K#0AZF}Dn?l4mWc}Ixn*EMKXt!Im!eC3
z;XWPETyo!opjX@vq>;Mn?g0?4yJx|9(|rV3S><SfgwHz4u^P)A-{MkQ<yhfKYOQ15
za8er_Cf4;;#|F@2r$YnWjgFT<<2{by_-?=B7J518c)B+!*V~Slu#zVo)ga9|#}M3c
z7aiXt{TGfIfcugop*^W94h!I}cD@UM7diEOQZ>#k*oLLfqaZ}Bvldvab~XdUdS^a*
zX>@MNBK5lS4thD{JT-*WH_mPt?`@a!3}CzG+>UY0ZE+}$RCS9fnD%om*7g;oX_YJ`
zxKz|`%4`_(k>C0Pea|<5<u-U~&=Yx+kjl0wfu#MJq<^0XigD0$*f>JZsFH`ly*aW8
zKQXFZ^7{~aTp-8OXpCp&kJx~Pa!D(CS|eW$rl+-X7K-{whGGMLkt?yybG65)HubD_
z9#mSU)ngG>XaX1UT5Sl%y+fl$g*u>h0qpN;7icZG;FfiW*R~75aRs#jrDEE)CfRca
zF+vS}Cx&E6SA<$5mv<$#S&nW&>J1r<W5;D{3SiulzYyje(XAOEw%UdsB9>7@Mr3Ou
zl@XQhM>6^$s#uG`e=-`eqp3k7?h;{O#INiD{wJ)&G9`YAUx1Q4k*;e!xX{fDKNyqi
z(@CZzW2aNoG2OJAxauC#G4LUGLG%2j@D%Cz>giOh*t9~-s8VJFmTGwmUz_qEQY@Fv
zVAFbe2DEo=mvh}o@0N8mPh*ed>i0@6f1l*~_e*Zz4apreNh(_y2PJoMNTQVoAef-8
zmjo1kFCt^R*MVoy`XG{>@7YO)zKWirhGDnkwh*~pD&Z}RHKlETl0Co0;Cj!(NYYFC
zk<2`eF=y9-KtqQ-^6ykW5dflt6PIUj8kQ?u;QOQw-AML+0Z}rS;5US!Zs7GS`2l!U
zDYxPMY&i}aSSv5sh53*6?yePpY`yG=v>T)X9vfvSwxv$~0DkR|x3S1O<xFZ_?UAp5
zf_r5+k)D1}xCuND%e`)-j>sdJ$Wb{E8+b}CK#3p8zEG!SDE8vA^c+a)YZ;D3xFVOi
zFr+*3I`aM`0}$q}e6A0vd7206p07>7bx^HY(e?}4>sX8B+Tlb}wOV&vHJi13AihPb
z#0M{Hdx7w7tv4`uUF%H5RC~1Vaf=<*d{A$**6cy*gx0$Yeg>S;!oaihS{{aVL2Cjh
zztAGl_GPV}XsoVk*`B2CXlGI3EPYNgsku7gOM9Z1gpyjUr*|M#s~3P<EA(mv+o%Vl
z!cF=~bYHL6p!!|<whU5l>C62@5Z#9QSHE2+h3{b+<8RYFDuOA!E`}K9djH6nwA8$z
zkJ8_)g!r_{V+u3V`;Ur?j*E?s`<*Xu;)KcLic2f<%;=#0ou?L;CdA`dbZm5dY<xm&
zQhY*OQf$|}No8ddD)Pn@m&Qa#o2!ET-J_$)dhpl080eiGQ&KRtsJOIH{Gn+RV=AUs
z{Glm*{#abitwE0eCZp^BnPfqENmOZBX<<}h!I<K_;?l7bCO=u2H#Q<7FD@=RfjIK}
z1Cxp-myF4q(ycJ6B;u)wc|`@~PZAj>0s5F>6@}#$F=GqLCrph=FRU0pscd4*B>%Fg
zNkw$JtgJL<YFYXCiirhd3+Yg4)TF|SNfqWN9fSXyw*E7MHmnNPJ$w9brTyQPQ43=x
zk860bTU;wMc%*;B=>cUe&GKAdbMf%Y4bSGTkmkx6PP1%!yM~OB;Q?mUR9nOI(<|+M
zNpUGraVd#$;eihT45ammkL?y0-w;(55z@ARu0D-!x|g77OZP+54d2GvP`>q9i#Bkf
zd4Ky9ZSX>KN?o>=yU;vZH${GC_S})9*_N0~c4TW|OUw&9vgO-m)Xp5uca1r7XSU|M
z&OA;kY@O*}pDk<5lKLFE(`+Jn)^zU5k<-k4l4s5ByC}>S^ZqUz%4*1wd(0ObBD7Ge
zd90x$g}l}fs^01>#0t}|F<2W}W%g<ek?YLD#!z|1T-+F{2F?*8(QG}(!+fu?m3+oL
X-x#V*s5Xt)LR8o*LX0tQ)_MF3!xcn~

diff --git a/Debug/Libs/sta-core/src/can/iter.d b/Debug/Libs/sta-core/src/can/iter.d
index 3bd57b4..19800ee 100644
--- a/Debug/Libs/sta-core/src/can/iter.d
+++ b/Debug/Libs/sta-core/src/can/iter.d
@@ -1,7 +1,7 @@
 Libs/sta-core/src/can/iter.o: ../Libs/sta-core/src/can/iter.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/iter.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/iter.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/iter.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/iter.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/can/iter.o b/Debug/Libs/sta-core/src/can/iter.o
index 6ce47774c65653fdc42a651047b48d6652a970f2..23acb2e52b6d718a0f830b392f05804740af6544 100644
GIT binary patch
delta 8145
zcmcgxd3cRix8M6cXTRs1<eY>=WFn(Th&Y*uAxLB>N<zduCInF#Dv6<AKL;&URmDqD
zTH2U;)zp|tm6jSxqNZwVtg)&-RYOtk`Yq3QpXc6x@9k|LYpr+fVXgIBzqOC2eOhUn
zUul{XqW${yrm#GdtD?OSp%+txc%CSPUHtcd<j6E3v?jhS$*rXR%v%U~#+_Wzex2E6
z?N^^%#a419`3;0iQ@P#AwJwlct^G^bWvLuQuJ?zKtDE0cxXdcsgIukgF7jpjFJPag
zZzTCn_a@g!zcp}K)ng~QzH3abLjPUtvP7hltA!uArZ+@lGRZ{tj38tr=Vp?<JP4`C
zUwp{^Bp5l!@5!TW4MK2vHHz%*!3Zi{^K$6pU=YGd9Ty!AMjW}K1=*+l*`L>w?DGNa
ze;7mdHUCU0gs)i@7MBaTx(m5(1oR`9GFvKI(dj*@LYV4#HN{PC^~m<~ZU_6knd}g6
zLP$vW46<E~>J7t(lR}%Cd5?n~+@I{&dT+y4bg8M8_fpv3(=k(Wy$!HebRaveUKlOQ
zzv9X6<kKAX!X&c0)oTNLVl>$~KHXqvQJc*^e*5@N*!BI7!IqiEWaaA`8%M5C|KH&{
zY$H1?;2G>?O~{V)cf%DOsr%-rfcmhnTF6ca0t&Jz0dGzWM)`7j8?xI4v%m8IvfGES
ze_a;YFTL<Ph(P8}FZ>@<yUaa;jr#hDFt2_>SS?=e)0Gf`UOn*9&{O_Gi0Sx>a9lCm
zErFKq)YZtK0wad(MZ~KnUOS9zvcsr^re1FwuUY~d{Ym?q1${>senpoxqbuU+k9jkF
z2px+t4ZbioS^}L<iE*LccQ^*M$?01~P06LtarEbPoT<T?dPpGNk!3u#L|85pkCVL2
zMq_JO%4A<5+WCy3(#`Jc8w$~$Z6$0j>ZeB}@z&S#EZyKyOug{&#75g=jz+m<+I}}?
zSVJtnsX}z}OEorFdpZWUrn<XZYC8!L)Wh(!#Y<&$v^AGojaO}9GQ*f}iy*nv77&p^
z<ocPec03_KauSx()s8E{WTqpE@X6MN_`~?q)`|9abi=7pEN8nVlYPW3!hsu3(hb_&
za_^1CUv82A!xQHonT9<({=J9Bpl;C@{8cLIyh|n8-K;_c)1SKk-ssp!yX;xmC48O|
zO;#97+*`!`*D|uTrXbtU!r>EywDv%{j>RvLdoX7n_A=d9UM20BrUtJOKTKAog1m@)
zrp7wmNBXeYrh*$A!#qRX&QLQ<c1`Ku8M8gxx<+SHC(LFOopGO>Kui9fe8l`hngyk$
z#7zQOiC>yQ9-whmVkA9dO3Wq5lyKxh?&|{i8<9eZag?(X<B0>*S$cAmNQi)3MNL)0
zpZCw#$aaZ?eCa&ut`hImh3rl+Dd9u)DKU}5bo7Fq?GL$=21AJonqVbv(-Wb@hBU}f
zH^?bO6(z#yWmY1YMoWqQo{+Z)Ati>^fxOliatZHr<pkm51HL+qtBigbo=5a7D3M5L
zDzTc6ZRc8-C&ROfQF+2CcHmSBIoR1qtS%rNl{m(UmT>rqG<Hf@Ing!wu-Eebfi8M3
zlsLiAeMihuB9ISs%z(Y21*C~up@f}x_Ms<2iKG{(1i-GtVH&agI2WEMPU{CwqBXZ8
zxi|dJJRpB;3+bK?SrqDm`nm&TXRiBgP9>KnQ;EIwd@A8a6RX6Vogfb}LS;lLCDzdo
ziW0LK%=Z0Y|AYHFhyAiYJSXVwSK=u{?KTwlspgPH4Iq=+3KuDFdR?ibpo6&1VK#BU
zkMX9dt>B-_`OanN{E5NT>4A{eSja7WX=euc2K(Qm5mDl;!I0HakjEJCx}mWBdH-lS
z>r%qSd97m%PO@FXSKMU#0$-HQfje?*+Hf`I99%TR0jc$ZJl7bq9pf>Lo7I7<{~-{5
zPevuV5o}+UYam@BHwCVI&i!fw*z-7Wbr|gP-jEJA$li>~k9@UfHawqj$Q4}ELZ)PY
z9=uK5xFlX(#H~zb>g{5NHSB}48yHvb^_lp%<PI6moqo?a=^gI!35F-1{(hr`M;s&`
zEhS!K1}tKp9}R~mfZ_dx)7|5Q=NwP@FG;X(^V#9)u*dUwpJMV(<-(%55tli+ZA|Ao
zoNl0t)gd#E?czF0nYTB&R&NjZM{`qLS+G|!if!^>zro>0nqXhzHdXKqZ5hQsxzsH@
zQzlL&nNh#o1N+Byg^Z}{f||;ZCNmpm*MX-I!>;jxSv;H+m;4hMk2J2nxE(x`c;|Bl
z{24!Sq9go2@~Iw7+m(#UxED=H#cEr|_;fPQ#a&OhKIBZDoJt?A^%_@c55Z~|e(7fM
z6>Ye$hX=u*$g6g~u09iRJ>wC@tM?d*RlGWY8+4p`)6s^rdngvo#cQ1PWL}Q%g@yTC
z>k00wuY_k`OUNnQzfnVB_hCNu;%3cc{$GrM|0pN4gd11h8J-czkTr~1E&FG2JNBb}
zF0qA2YYQ**WO79@8@BPg)`kJk=8$JO>p9`L?gOrMJIlL_TtD_#^E+6|iGFRu&RZNT
zm8U6_n-Y)$e`k*Cir_Gdn!}YJ&ytthbcH>Sr(hLVIgeqS#AICl5?1GCK+evB+{%Dg
z^81)-hbOulWG}{`QfCk2l*4-xnP-8n-dJeKl(Dd@gfG3%hZpkW`cEFwHrx(B>KVQ2
zj8I=ru_+^WlW91O@5$oVP-8l8W6Y9y&(?-G>#IS&&p(Hs`Y`{O^QipEso1%%W4Y_y
zdSdH8nZ2Rhza*}^Azxk51*<U(Y%K4u<QCL$3x42t@F4SP2ov@Kx1*YG+n9^9eY!CJ
z!#Uq(%=RK?Y#G=0D{rmgkP&=c66c=CO*z0VtLFXn7_%s5NfoCxx&s0{2gO7omz2bf
z_>mu<b3B%r<RSi#j>M)tJnQ@Uij^VoJP?os0ZAuU=E*$R<quCh5ACJyY<oj)=UO{5
z8$=^`W-$`4bBaq}hUbGc$V_I#72M+zow#RVFMeh?Kv&M%?1QbRID7|YKteNkOx%c<
zm<M07|4R;5pYL(wVkU8lZ!(>8xvifwW@(JgCElM;WYmT09v>S;n{@FSfu@VbbcHT9
z_l3-iK*(k(us5<ljG)s+2w%5%2v#4^b-M82`W`c5o^lz7=&UX-^3U-#Gj_gDFM%%3
zbGr+<jPtH^EF5B<|I8zFlsg?pnd)LBvve9?eTP>Y(`f19B=@iR0NDFDt?un$kEXPA
z;X`wwi$irF1vjn_H9{BXsAamS352XjMBKp+7u0nQ(1(*aOQg_+Mw^sa&K-^93PKo<
znf&7sVZoj=*^o!_A*(1+U1U*}giTY(b1&hBsSN&YZqp=g@goQPe$2MJ(ZqlH5-NBX
zo`$g1kP$@yvH7b=A%40S$(B7pu(SiIBr^xJB-ytM1yKY417kO6fQ@89WAJ6f7Z|M4
z3mVB+mx1vUu7hk7k6`vEg(CfF@^l!f_vFunjZ4juuYjhD<!=O-s+3iLVXYhm3RTHf
zpvO)*ur8@x@(~7qw~R;Mt7T0Tsc+;fNb8vFhWF{TEW&{^@;$;@U6FShlUlC1u(n3~
z1FYGs-9q=aXqCXmwN<N+CU4UwnMi%9EoepRy!J1s3tBa<S#0WrAEysY9}gw9#Iy!g
ztS~+APHLse0fbhWGO2KVt?5|@QX5Tqoyd92<a8%hV;T(nYfUW>=%i@}GCXBk1WZr6
zOwpmFe>IhKBQ?+LM-)|`nUA3b8_aj{Rb{RVP&b=>!KJO{!4&sJ(_&D0xHrY(@9)fC
zYGj=?-vIEJ%w2)jZ|1Gw{vGr308&%b(-2ZK)MA=V?HyI*Dl8V-ELD^@fugH*O=xj}
zn&wMtk(z_Fm#AVK{75|^x~W6Tio0voC=BNJYMhhQIpv10OX>mmdR4uHubWE4u-{h2
zAnw1ELO<u}*D0?0NPmPaEA++fT%=d)Yr&~?dNV*-r5{JLck4sYf_-|w7Nqv;|LjNV
zp#BZbpSq~;2HCFZ_ptV>9)|Yb(MxdriT*8(pL(W$QJ>VCmK)R%HOEp7l;5{B!Yzv}
zC-Jq^lHDBd|4Pfv!SuPtvKi2<wFI{%waIc1-P&yFBS{^ye40n<Tgz6Qud!%&`@gr`
z1TsHb`g)K$ZyBLTU9zMCyepRWXx4Sh&l#ldS&pFk2bS*5NIkV&N1&<J<wL;#Y1Tv#
zX@)fyzwhr@SEGlst%E_b`PMsrq;^>6qu%}2bbOt$YN@1tuzs6H>Sya$=*UfL2F~5F
z_Qu%$ZXM8`)P3uCWbw$lU;wFS*0X&`O|i8=GH=@UqiWY%w)0?~VOxjKPi;GyfVPX7
z^tH?8Ux(CQTRK|twQWi)siU@yc&=(~)%4`46SmbDk)Lc^z}Ty{UD$HVcCHtxyS7$C
zN&R7q!bm@~{eiwdwrO|}{<6(N4<@_Z&Y`1kxcMT*>24kv*q_{cG$3`^-2gII-FN1Y
zy5XLOC+(K|008`(`v^Gix-UoX->?TD;7t1@Ov*z01Mq2yJtmISGW%}KL8UzaWq)Sx
zg>pCAd(j)JHrriAVWhX)hvDEZ`xt<*&%Ozn9<<lN-L>|SNdK(ej3@7ceGqzZ**+V*
zx@upEL~qy=0rw2YZU8*Xk<*vd9LF*Y$9%_=L8KNrexq)yrH&5)&?d)o;Jevz*o8K4
zb38&ZUpX$~NxJE%P9b&QF&S~6IO37hG!J_ssTm%zn5wxR;lwKpy>1S~8>3cJWL=+t
z_?C2{2R{hr+u*5Q2cMP*yf@ZGK*shx^^<pmy6yx1s4{|2e?vY1hu)OKsZxE0^lD9C
zZ_C!y8GWWq%%`t+q=TT*Ka!=5=xdogltAjC6qta&<Y)1urfE;`n>tf#0Ddgco_dj5
ztgQ!UmucyUzd@tBgxaIE%yp4IqOGC1;CwtE;=+J$flg>WP|EosdeQE7AjzJe#*r+#
zg{x*sM;lVBq-aQLw|opz9+L%hUjIXOBFy+gH_}4YnTQ&q=SGrj7EPqmW400-^yULy
zl(Oc;e=OExKh7gpoUe&w{2sJ7!H%ejJEBRpm<cpmhJ}($x_~)um5WEdwFm4rv(eqO
z9T6nEv_`{o+JNSR2EsF{9tiR3ax`+nGIV^3JPlZ8NY@uQZpcN5u~25Bm`~(g@P3_4
zu#?&<2U5NIcFEcAkevQb$@%Y+1Cjr3$putPWUcR$T*y}vmAn9<0HpDGr5{QEkq8*r
z1iTGR2?PESpAt$cavXmAW1e7ZTs%rk(4$DUu7=(2n-(NHEJaJw9})Rf=l+mc<qncP
z2NQodly3!qX!v>%$?*GGB%4&?d<z5J>QIJTI@h(4>^UBT<eDtKL98kA9yUys77$>O
zoQ0GY%XXO359D(o_lazT==3)PFn)zh$sx5~#(`!V<OD0Jjq)&%-Y$0&ENX{*1wGg)
zOM&XwawN{}mp2rt1F{7M@uW+3!0*~Ac@!C+mJPtqYx3aBq^`>Wn1>tkB6{^eE=4;Y
z%A-i_kxT~5r)#-H8ugZT+n3Y~tp}=qUvptP7HT0hW@?ePsw=5gS`Cm|t?k2sHQEqF
z*s8hqA@6NkR5YpWnk$6V0qt#c=Nqj-JyJEA4?1>6+lJ@woc0(DJg+%H&C8k#0A16<
z14!M{DskX}HXVgdHhtBW)HG8RS~JV^fV6to^a)T~Wcmjfw%F9z6-Ii6X*N<^Y5ED(
zZ!+~o`k$Mo0`9#g8}8m`nnx_;7TX>Mli_h6P4rCZPqNM$ys%!igf{PJl#)V5{u_9)
z3fm%X=@kT+u%5<HP3qT}_GMAsCNau55fRhMnOa&prf^tZd0|O$nX_kZw}kk#iu{7k
z=^4%QN=uz-CB@|h#pPwrjA3I6OUnwJrDG~a7Sc|mPGm+%QQokUvX+TM;+o^%_}KV_
z*w%3gaV_IpI?GE+#*`V8qw1$RY1gR2;sWuvhid06n^^X@hw=UUF*8b<*#BRmxQ}w?
zjV+2PE-5aEDagw&be4~*D9U$^ODc#diXKtw9F;eAxHG@7oKWpmRxq~AIV^ANn36JQ
zddaYgBIZR-pWIH)veLX^1w+aU@`{{ksaY{;bZSVqlHnC&3WoG78BsnyZ)|}vt7&-3
z|G_1J^P=^?8JgH8K~>e!pZipOmKq$E`M=HCnO=}zF|zW~FzGX-dv?#xeTVe!+_Q7X
zt{EZmv9YaUTUT8ezPXuy>$v!sxR$Z8O+w=0nkO`mqs936*rd4ls&#Y2o&Cnscx&`_
z&V#0B2mhZ!qetKpG`%>j$fwa8mjg|IDVz#TKi=D*eS|m*O>h2R(DbJG(F=h8!r8K_
z$=<aVDU4GGv!&IDIFv2x7!`-c%Mj!Cp=C0~c=vF&>|~rH+1-daGG1F#X{<VuMVsy)
z$(E%?#<$tDbpgpz<0{J*N3-Q*W7^Sd?Z!^y^wBKbdMsPU8WqQ~wc1_Afn!<p;Zu_>
zhZ+Snw5!_KT7wH!ZMJM>^s0@PImVRQa5>6YSsST>=x<S1jN|mJ8TV@=DVK)FBejEH
h8kxr%Q{<xKkuuj<K(gGZJ|3xN>=k0Tk$2SlKLNE?*u?+<

delta 8178
zcmcgxcXU<N(%<`>yU)EhxtD~5bO=cxB%~KQ2`zLap@bev5`sh^2_y)<hg?8PkgA6k
zK~U);QbI3M1O*fb(tUIVDGDM*q<!D~hV{O+{MLHk`_}tI7nzweXYV~TzxmBRLFO#g
zpD)#ChiI7xH-u&Dt|3i?2tCtGh$~(~IK-d-lYP^K&}#eDBe#-9<0?YPv+m@I_HV~7
z+dN-#71+pC-#-g3O||btuG>N6Y8X(+E^Ap|a!v0~u8#f_;IgQUO5_?D?;>ADz+CoO
z=SGn4+wSCg-G3EaHdQ}?Tpr}t@&k6V%No>@TqFF+HMtrRll677OM{V-oYI=?kAjhk
zjG)}KPpTsad5k>TmS6;zVYSKLRvkg5tF#L}912D_Y2ctE)e%Q-s7v;l0QUFjO7^8d
z_ScCc`$j-(DTJRz<rkC)`C)r<-3;tSE@iO}X+XO-Hy1*$;uVFH+7N2GzjrF^OBS+2
zya^#8Wh=5>HLK*}A)Z3(G2U;&_UTP_LY1ko6&<QK@LmM_7;V#2s;q<kK~u8Rs)W&N
z*(jOpwmxyNXVfRVW0gj*w?vcO#it|emegj8kN<w`eMYHRd;^ZbmMP{q<>y+LNUqR;
z-{3l8Cp#?gCF~0Xl_es;4M(`V$&L*4g?-&hc5*OKkRk2Ju2UW5%Q20}POZ-VrhUk6
z62kta>14Ng<#!T+ENx%;=To~ZovWL^#>p^SFClDJFZanxh#*^MJXG_Lw+S%=PvOq*
zO?PXMb%u`+5y79Bv1HFAUe)$`Y-W(%pGt`G`pO(`4XSyM*2e@Nq65FA!(!-&B>J&z
zq6cB%Wo*@F=6Y*Te8Wg$zxO@F$e=dG`>m#?WYXiC^fLx~j$=<1B#`8sW<IrsTh9@X
z>w7gfYuUn@?e-HQ)n_P`ZgIa;O^7CJD`9t0KPwHaMI`Y!PbXAbL%s0vz(V^|L_@Ky
z?KjO*TZq-!T!^;*W6gE8uFlMcRCg!qS8as|Zex1blVl6Cg*{F_Fo)a2<OFk$J)GnY
zdtmqkBG(Uew6g)xyi4*TI@%c;LS{=u5k47)5Vy@g>}_d%3peZ<%yOn%3fbSdg*$P=
zDLO%Wuf%(W`NA#Ye|Zw!Bhs*D`#;yv7*rni1wR!D&lyyr!_6i{b^59N&xOtvw91i=
zRl?^v(c}Yjp?lrL|9OpUZOxEvX#T*_LfSebUFWPe<nG6rhjpOy-YA!j)_T<<;)iZi
zDma74r`Iy*Jkm!jc2&Kqnd=eic9fc-J2Yh+GG}@;b`8j&PFO5D?Q!3oOs@hwc#Gwg
zv<ON|iOU4C5)rYGyJ%dMSVmbX@g6~@gq{t#tvzHkkxhwmmcxhxO8C};EDDGGftsp>
z2d|%_k?j(S4=ttcDlx4xWG8}233sYbi7gza1>LktOb>uuPlKVv#w5reXfBmlo(37}
z205OnqQrnYkV!OJO7!-Cyh8|)-xKmePsoM5(lsj>4`=!4hFoQ62YBw%wV*^4p{c}5
z-nNZvotFa73P$BVr#OaF>CeG@Bk}e-!cmC>oM<73FQl<k;$;iS#W|24^ZGIuT^C9m
zX6QT^oFLxNpcVYP=t?DcsTE4J<CPuhicq42QE>&rHaJWm%lVn`1an$`jKP~Uql83v
z$d{EMPc(*<Eg?S*rLTz+JLqauqAAzy;#A(F$y8!1U7t#{p@~)EZ*3v>Fha#dDJ5>x
z2StgA3}&5Pu!nPBkFx)F_ISp@|D2%~17Lf_Lw;HnGPbdx{tG+Zv`UNw9mGWrvw{2V
z&Pj}J0RI%ucM3!2K@3)66n&qRXq5o@8;5DiAYWqtEE*9d-tGtal$&yZ0Z$Kwr#r7-
zNqb!snDbi77#v|ckB_*__GLb(5eII;t!c#7JY{Z|I&s_+hCMI>b~59!pPMy?sqI%4
z{?{0lw`#)9WO*IZCE7QGt0(6k#ub-x;HP2m2XX(L%<b-sihmURDg*LzEy$}}(|o4n
zd>*`&+_(~cdz#No;u(3ud%b&L*K)?ydl@tQsykc*xYLu&Q{FXPU8=*AL%-iB(IF8M
zmln-2GvGAW>c(~SV0a^H;O%qnZeR@TE3YPqr=xdEct-JfdvTOKbUi6Cm>Y49lY7W?
zj^TOi>Ef&pTd?Q}*D;8BTZ>Wgt_1%8Zpz4X*b5oOglyP*d5&J!VV~^+xsgw3%qafB
zrEcb#YQ}T)7B}b|H+1N0SRY>51vP;oO=338^n@pnVQ<PC%6K>_F8Q}G9^<(BfvND6
z@X8cUr7`p1adY@@@~)Xo+l7ou`KzYz+s2IXw<$aq_dT%TL(VjwQ|ZXHUf?R*h2ZTJ
zp7O(dL<0A9Z(sO_^IHcW*EI;9&l!(ke*1utSix@>aC0j$5-sdlxrbuWTx{ho?&jB#
z-SA=#*Ls-y>L=mZRu6I%_pjdo*d3Wq9k^LvbKTV#e78`%UC51lqaEz56i5dnQNjMh
zoP>tBF0q+MYcs!?&0UXVHaz6Zbrb{MibI~~tdG{fac8;KM=b9%a`V{#l;>y=Cwf4~
z%1EZ+SRT}_+!W7d@VDc*t{e_?Iu5QS%;BE=I)MpN%2Tk2t9+kfEMYRvYlHPuT0u@s
zhy08IFXP*=xdWcij*uM~gQW)S!HiQ|UQ>s8R@v1ZFJf9iTG^Gyhu-1MGkU|ngGV%h
z+u_graA$<lImIYO?lRNx?|e>6z73!B!QQQmSqiUtPz@eG4e}(9-whw;|3^G3_c#@e
z`#OTVp4Jshi<!OsnDen*w>MA9koI`{1_PVG>#uMN96lT-0P+jwQ#U5;Wo}0~pSB_s
zZ#%YU{s(ZrVcBpEW5yP9eb;#DK@OS2*J^#vJ&K#6b3(g$y&Gc|%q&^WX$@$K(^5b&
z(Vt6-<wp23V*;7%DdZvkuZ+N==RE5>`G{*F@H`ff1OdsRT$y4XJmJcccxcad!rMY`
z$j`af2F!-kn(!QEGLGRC-|qm=>@>*M%!W|hgD%m8d*;vg*H{iPl`oU#4C84IKZY4l
z#MLz8y4x@hUa<cK2XpW_ZMc}7oZ>#Fb9-*<D#olKV-p;XB$f~v4dJ@Q+xpQWLlhBc
zhRCHO4Do4C$ai>YSToqau)jaeu_1i<xUKzhP%^DCgoW$-l^OFJmtoX`|4bvSxxo#c
zPB(!ePI0?ea2cmu+~YmW^Yc7HZk)S6Won3J%+kN}(bxHHEgCIDRObHG>;wD1IIY&H
zum@0DhH$63FvMY+CPSoh<K|E!3~`ZKW(Ws0+7KJ-Agz8*7t}=#(2<ikPNXnI(;)cg
zaYw6h1-^{OxX$p0Te0S72IRgR$X_W@L!?uchUgmwd9n>wj%M(qLSUD0i=Q}QcVo82
z#Ss7LNvP^ia5aSe2pOIW5aT{a3Q3c_NY<MPf~D<hPO^39dL(;Jp&%;jQ;c2TK6a9M
zx!}v7O&F}A%NohybHVu0KY?s-*?{C&KcqiNdIOYMGK6^JQnTeM(6mh6#r3mPt_BQi
z<Z`s3TrL7VcF3&Cq;|@?S)_K!Nc4TTbkrvGwai9Z$7CArr!z7a8_vpEgthun#!z$A
zN7_idTczCwYc^?-=-y_n4A{7~XkC%oR&A_KYOgk}0jW#c4XDf7ZX8plPr{B5^!Wow
zEz}pIie>sE%-(X{34~VYDO9+zMt|6p)Ox)~TXG)L<K0Oe*B4eNRiTeSpi}xfWO!OX
z4NT9t^ueK|f7bIll6v1#i72W*vm8JR)>(eSQ@O<oP&ZjJ0oxW!CdGZ#v>K?qhMi*Z
z^LLiL!2P`C5`e#IX#uqETDE}u_be9!NsU(x5w297q1n`?sbQ}C0-;S;!?H(Hbafku
z&Q<&UNG(uDk@iBh1{)Wv`$RW&SiMAL6>2#K^PDP=Cv{P^!P8asGx&O49m3Ns^#ob`
zq6UJvzp57K=le#@WKxTbx-^?=nK3KXMS7+2F*vo>hyj%4#tAfgm(dL^*l!G~OX{Fe
z+>6v9<7=8fb;bAtWV>Mq?EBg9M|<xXh1mYg*iYl9UK-DQNlmm~qK2s1)~6_Yo;47s
zlvyi>ky>P(9*6sXx%F~CdR%3_A3|!4)d#o725SPU-(>9}NgcK>$tLx!^)u{0ZfzPz
z>YTL}M&uvXp7^?5vJS!^UA2w{ct2YIj%NL2J>QDd1FH=fKDN$?A@$r^6Uj`l&Fc^T
zPqIaUNTs$+eBY<pR-%V9ZJ8k199s-v+ip97dJo#h`;$6rd(w>5_qP3Mq<*k%2hO)_
zt+4N&%|uSW**Z5N^~kmfSv;{#>qF|L?RXDT<Lx7G=0y8WRPCB#KLzHQ_N91SZC}p>
zw4Z5BPdn`ao}~8K8=(~k>|Z31I%;2m>#D+DPFJ2fX<vyExnN%d#$LBS!IC@nlVHMq
zd)xq05ADIdN&Rkrh`v6xYq$_z*bf7QaW1!u=;%9cPNX>5tpkX0!F^^`QrFz40-5XX
z>${M;>D~iZ+8y@=0QjzZ7M%Cp=b`uSI6M*XT}KHfWxnHQ@M59kjYLvQ92+qQOC3E>
z_GgX`D0jW18{MI5lf(5XsIbk^3mbPjasa}9#|C72$YJ2@3P)e0f8Nm?SKejE2k5~y
z$3*bzy5kxWz3GSo+@;Qq0C>8yZBJ6Oofj}1bDa0_;aK4Ok-DuGIll)$8=Q}T?<VJ7
z7uvklc^Ace={(b&)GcQ@`uoWFCgMJGMk1$4mD<%IRa&VQeVEjHl>&%Y7<$7JggZuk
zNRbVr0P(Gjn!kFdEK$h7@Wi7v2ltI_CXlfoqki(05$bvb_#^WPKI0wv7#x}?KgJiN
zRN5NS(^MHxoiW~(Q91N9O*#o0W3gOIceh$14J7ru6qtY)@>UY5N!tCEq~6uMz>m3F
zL&Po9mQhk_iI!5A)H;pM5^9eYlj$P;jdq>pg7fjHg98Ki1D#MeP%8dI^ddD1ICs5~
zNOIU!95r3)jYzGKsntmBlD~qK$K)r;l-@(xgfQa+-AD`NS%?~<kI~n_hzTW98L<zD
z4Mtp<i&EC&@jr`=g!$RzO7zo7CT&K0liLN6tn)aUWZiK<qh9||lJ%>`l5Ef(S7E~r
znCV6n(cQGi;UwF~qv2f|f#!Y7;2G=&LJXgWMvk7_ndEqR#*0*`bUnj%Q=UeQ`SKkU
z^NIWkyk9Gm(VH!@3)O3Elbro_$?5Nqoc~T)hWvL)E?~Dr*2aFxg?uSd$tw{0fHXeY
zy+{TuL%^Uxz%%siFyJ4)nov>^<tQrlK9(j%qO|0+NRkc9VW*x#<C?yYmbAP}<WucB
zL8g~DNp{U7{%|P2ApoM<_F$4V?%;RP+GW^ZcPhHobR14;SJ_Uo>n046Yn-%$SmWg_
zESMl$QUlcjIUOmL$y7|~2l5e+`$PsJ`chdA#xIlgx{&%@Mu2AP<Y*hI^>Qze-X{Mb
zSk!ho1U=Xx*8<f8@^$PxC~qoKU&#>|#8WO=H-q$P=~kW88Ce_iaYKI5fz(g359Z;f
ztmaMXv0Q|9{4S3owI?zOET62kC(@`XS`>;Y)!Lx?dD<>a$9&DV0jUMrqSr{R(2fJC
zmD)CJSfzDCge{tDKl0wH<wcX)rtJzL^_BJ&y7RTxs|u;(S{HQethN@{-$ku{7^zFz
zP*C%l<^n)Bv;l#n?r2xA;juOug^ts=HzqYnk3?&x>&f`G&(IeDwFUZcFsw|^b>XyS
z`b4C-T>lQ$Z_wu={f+u)z`ajzjkEXbrNlyRvAqtGtn>&?^r+XHr03!+l3o>rHm|5z
zuNfIRdoj!Tqba^B`W^vBFQYM3W9QYPb$h68U7R;hhR4RIHOlImNq;&fC#8+d$!piL
zRsY1e#DuuSKl!qXhK_tazo0nF91z(md{llxauSxsCB!8qBqb-*O-fFzn@}&Sq_A*k
zaaK-#L3~`C85bSw9v4T}t3PJtNZ$tW!?JS+=NIIOzcj2_7@_{sLjC^IXujq@A|3xp
zMAyG*WcG+*u?2+%d9iufIr&-n1-U~<4$RBSjgHPrOpHq=iu`#&$>5R0a<bm6pBFnU
zdQef;;Or3ti3=sg)a>|f#d#x&<8!k|3>_8UGOu_@NnufZNpN9o$zWPtSXdB0s&K@R
z;-c)_JX%x`Tas5?QfwAQ1vSYTiERb{@{E6bMCgBl%>R$#<#Ev!J}LjIy8k;fLLq15
z>*X(+g@l<o1O4s&yS47pJT0?-Yx7DQKXX#<rSiWG+!zyBH?d)CV#7L#wL@M(9zye$
zlu$o0NtCyGuSR^Yn>6<tU8?x^1C4%aL(}ch1)8p+)zEbLeF;s!Ek1yzuX-e10h*5x
z?V;)Z<bSND%VsK`=>}X`zHjdus~l_&JCq@d%-tkMo6f_dWT`pn@DjPo3_p?~*PA0r
zZZi)a8KrqHGn;&qPK#!IlOfNU7fF_yvERaeo8?iGH_d8CGqg@S&4Q!pIQ3|TTwpqn
zWoQj{nf;EX)5F?h8S;?%f?S=xFw>9Yzz>gS$dAlljz`Nc&5w_Gn=uuhvcgQQh)}cW
zuL9qj`4u%}zB!{Jg7Vp15uqjQGcQ%tQl+L4b<FW!dz)2Hc*<R7?1>0@!R$uzSM%)?
Ge*X;-V9!SY

diff --git a/Debug/Libs/sta-core/src/can/subdir.mk b/Debug/Libs/sta-core/src/can/subdir.mk
index 5871b55..8c8d690 100644
--- a/Debug/Libs/sta-core/src/can/subdir.mk
+++ b/Debug/Libs/sta-core/src/can/subdir.mk
@@ -19,7 +19,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Libs/sta-core/src/can/%.o Libs/sta-core/src/can/%.su Libs/sta-core/src/can/%.cyclo: ../Libs/sta-core/src/can/%.cpp Libs/sta-core/src/can/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Libs-2f-sta-2d-core-2f-src-2f-can
 
diff --git a/Debug/Libs/sta-core/src/debug/assert.d b/Debug/Libs/sta-core/src/debug/assert.d
index 00074da..adfb353 100644
--- a/Debug/Libs/sta-core/src/debug/assert.d
+++ b/Debug/Libs/sta-core/src/debug/assert.d
@@ -1,9 +1,9 @@
 Libs/sta-core/src/debug/assert.o: ../Libs/sta-core/src/debug/assert.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp \
  ../Core/Inc/sta/config.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/debug.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/lang.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp:
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/debug.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/lang.hpp
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp:
 ../Core/Inc/sta/config.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/debug.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/lang.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/debug.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/lang.hpp:
diff --git a/Debug/Libs/sta-core/src/debug/assert.o b/Debug/Libs/sta-core/src/debug/assert.o
index 2a44db82eb35c6cdf62fd0bbda8860645de8adad..6e591b9f3050e4284ff06f1d60e3466a73694794 100644
GIT binary patch
delta 12214
zcmcI~33yHC+V=adwcfS&PIe-KM5Kv`L=YK82x5$(HPuveNeEJjgv3~E^E`x&otRIn
zsx758wP>qpX;rDyfevWVqUF%)phwZ~zTY_C`Tzg=ukX9AbH1;=df)H+thL@}e%7XI
z?hR|}b*nVWI2ZLw^e@s=(ME{J1`6R8|Mx$}{;@(B4MNi)c1ruR80_{11LA8wszuIr
z^|5<(Dxhi2!4w&4@jUE~CId3U3bn{l>cej2IzYFYvnjIFr4a0D^#b$=^Q_S_NB0ic
zHdz4}RdYK<PSxCt-GMAXUf3Zmas(7%w>%y&KZ1rCK?<-ik`@^=O8{FUX^Qbx9N?MS
zw80p&7O+2(%8mCs0bZ+3rN-Vx0MGl8RA;=C0r;Rc^%zeK0-Ooc@_UQ1zEDfc=k&n(
zN?1oJL`_TOjV%#||8$71)fxbi({cn2#jX@bnAL+D@}#?nnpv}2Cf9}o>!@mvbDcX5
z>zL}ph42W&2_MWx)h6=7Z1`*@SBGW7*nps!&8ltSI&VJKEvxV1Ixr9G_SK`I)40(O
z>&`V2x&C+v*4?T%=ekW-tb5hy#`VTgLRd9wR`A&bu0z63as5;p*4|*Nny38}Sk(!;
zO=(dTtfOl^;JVXztmDG`c*-Ajv94b$gzH@>7OQb217RFS0a$6Z83AKoHrAQ7wfy>O
ztXoBC`5?sJ>QpH|SrzNfmGV+#%<5Tt&sOVYSuX}|)mk}Fh;ZwX5iTJdPs&jJ^daQW
znHZ?^_qBJj-6-JAI3c!IJ7&Q~^_KS)yJ5%BRk-Ixa|T4lX{=o#VLHdpBO89vVRs?7
z{{#eohg=vXQ*cM!@S700Z*)U8(?%i(>IH8dM`(C5GVW^XPbZw}bboHDbK_R?y}cbB
zJS#Ur)Y?Unr4FFFU2XKnsTK{xrmfz%)xp}>w9}g)<y?YId%dZyl15{br8hNI7kKUJ
zpf``GE6BC0quxXbcRv#r6i3^ztO|<5RZ^8}Z>Y0|JmF1n#>)cl0B3CYUWClG&Ov)>
zs`JyZ*%+Mb6yg!J-CORg7x>;7h_(lO3sEDL>^<pBmbu;s&e%ZD1YCGcKlr#h=uL5j
zd0aUVRRo?vU<Rw}9kF>wTQfog_@V2%j*>jtn);X!W2AmkSYfF`6iNR?q|CD3ug6Vw
zZk*NtxKkt}xp7;45`-8poisDZitQytiF7T*Vb!hok*}#T<Y_<QJ?^U7q%XQ`hV(1-
z6C%ob8I?J+Qd5kTha}CZ+|;+m76>u7@`y&(8gCW9di5K$5@LyTzlbMWT5lPMRi#;N
zEDuzymZ5ubCCf_l4)JR$BfM+;R&|I$^}6oYibG)SXxJI>*?5Gpjx3=!JDw6ES_X41
ztX~3zs9U+QtqDkbj0`Ts1-F&s&G(P+w1SGDF7hZJT!z~3E~~Mqg!Nmf5IribwyZ}x
z2=RF36{l4X#nn?*=Ob=m^X`DX(YW4Mj)b9B)k#A1uk=t@cjgK)K<dm`*2Qcg23Bs|
z)<DeZLDK7VCx&;OEX2@Cd9t;%T!>+nn`YJxZ%=nYz$!T8-!6!b8XdeR-1XYL)If;i
zib;|F`0pz83P%eJiN9-M$UlWKj|y>D3*-MOZ0Jo17!}@gh7k9ie0C=<9Y$6)2*+XX
zo`AaYp7(4(q<qZ#TR^1e-R?sCqK|2SA)*yZu7v$pJnz_qne>~@R&W20%fc}sRftRa
zng0JNtkEV{h|5}7r6C62AFdK!qizv$Di$c|)uMk28=<zP*Be-)e&#G8?$~?(^Q<Z_
z6btd8{lPy3l65H@$GxWm>(=>TsSxjK=Nw`1?x>R&15peQ@5=L5uM!&=G7N$czv&n(
z(X!OrsY*up-!}^pOM8r!B|#IL3DK-_Qxuf3XML4%M!W~<H^TxQ(1l47<3@7Kc%>r!
zFlo(tZY?)Iu&SuqS>C3>b^ID*>X~js*&ldwf?LSF-c7-=k8F&GFd|erj|{-VuV&?G
zrhk|+QoLUWM>h>ahRq~LrTpR5n1@>xw<j4_>pxN{S4oQz8MCEJ`S15OtA;M{4y@MQ
z6P%3+B)TGTN<5A?9I!qy3gJ-VCp5Vd^`;YRp!=2R8AE(#0Wowiu~R!@L04kyjl>L0
z7$s`yGsE%DQ{pV<r4or~0wu;bBIal<+tcfCvl!z;iS?)qB@+4(zZ*%6Lk}wP4PIJG
zJclk;A{l{DVvKi4^-#|n7#~W!rRBrZx&BO_^M`ihOKtRJj7%l^p#+q;5=rc&9qWt&
zQ(_K!MTwDUMJ0aIr<Lh&-0eWg&XvS(wN(XSTtDF>)<aJ!amIrZP@;AS@jM0#e9|gg
zb>aH$n#4jae-l4Blql1Rt99o3@0cNov5vvrM6M?yIZABMxCT`T#hBnqTtyv03u+#5
zT~6GpPaZnL!_Ch+LX%o>eFsBIiQlymJ$rH8P^Yige6Gi!RFr6k8dl;q3R;OQ{7!*H
zr{g2->&~Ys>4=xB5&>F1LZ@$N4@#m?NJ{KmPu$!SKW>zmn#xTue(J#cQN&t0_fKN-
zDls;inBJHep_4MDi0ij><ldjd^<AxOn0~5PPf9MYB|fe3U4!f5a^jXw#Kt+qQO)t=
zN(qVITT1-3H?gDkb)JsFe!ae?j~;;+trBfD*3gRE=v>y(b<=eruTH5!yrsi_Ba7=6
zONbA2vX<#WKA1vD)p+8zHb9SPN)m_L5~I-I=n-8YrP|{XZN!pH%J;<(Kh%YMxDMCz
zF>#f6UFUUyR_SU<3ExLb?5Icd*NOYKJ=aDP;u2kYak|247p<V^g_*=V__3wLsbJ!(
zI@7Ja%R(bOvoXEVczuX1su5S|b$4x+OW(O%SNqW?dG&rr;%oY9nXaK7T`6g*ul{{7
z*IjiI->J>@o4SNsX!pkGY`mc>a&8i@PVA$t-ml~FHy!XT+Sk0{ygWvGd_ou9K%JVZ
zy4m{aSkBwXdmhv3dnvBN78Bcfr`HVi+=$~kOV?i$oy0XBN)~9dGISL8t)b+YF56_S
z(bV_18bmpg2Q1XiU(^=nkEG;FT`EO7#=~^#ujW%eF@rd_H*uLq$6&-`+#DD~9FDh!
z65d?m!U$rPo7h{c|6Vut4_fgD%_#3TfaujHEYq3%M92HKzIt0fds|2GDeYc`Ziwir
zd@4Oq`+BY~H=A@M-qu$Csr}yGjq;vP5Nj_ZzNLMQ(n<V6QW7+TcuCh2{}iIc?qZ^U
zG_g}8aYTFKr`qpxp<LTKS3iu<&A(mS`=}mA6LcM{*2&sdgSQGTKc-V$MW_D9a>}2X
zLA<-3xUvdyd~4#CWMV_zWrwu)-CI!-h&;goZRko}2DhLK%|Es?FZ@1_cqNbcxK`Y`
zKi5t4EUDFx>qK2o19Z#|4Ws0Qu7>D9uAkmaygQM2XAv<<SK+g|m$P+jE-t6sGn06g
zv&|z?{ki$3JJGj_cuZ&gM;-8p0!lV%$)53C57HG7s0aVHrj$(3DQKzd<F@u}k~VQg
z2(MamiOcmle=FnqX<g1MbeDP7=}g2n;e}M~QwN>h$C^<xBbeCEkC>$Mnwr3MSBsdd
zi}$*YPz~+(T7C5KX}p@I<2v2odY(?r<ygILMBJ#|tKuo;=9sqnV}0D#rIgguM^tEg
zdu^noQ4rCmD?pCpy7?sHjCkU9UAE_ka$TwoI->6n(=q!*S4rq}UVURA@k&>X#X3;O
z^;_nEZjx+0);`ygVI6qWA>GZ->-_E2HQZ(t<!|>VHq{=#l*4s&B2k7B$ImBTuS;B}
zef?A?E=rf-EFFo*gLM7Z(T()SSl)U{hq{YCC`sq+Eq&ZhU1)doFp00nJB5BKOIJXe
z?uC=u?`_(F@3s8Xw!HIxJ~2!?^SVx7%YKyPFW2?|mCm}U1OBUiV0U-?(iT;<LGR%v
zTTB>DY=R?f@#{+Bz;-<1cl3)bwrP1COf*~U(<uno0r$f_ws=m5{pJ$hKXU}JTYJhc
zbFO%VpRU_lx%y$<*~z_l)6cpZy6QTA+egW9ZS^G-tSu&|Q*sk#DREL?tyYcl{@VM~
zcnS)%SuseTEu!J1Ez*!~TR3YIPi691Pi8DPLn4SdDa6?Wcwsjrm{Ynwx~}4SzE*re
zS4oHFlsukI?4;vyegW49(ag43uO+p&aQz_+wZ(Xwc;ZoF=SjTtZYuF@4-Uo5(&J)c
zFxOG~!V%ObHbS|+8UhT2Cj0^abuTa|b`CH&7pn9fwKIEQ5#4|o8_X~#PD%!*W<~?k
z{bGRa53&Y2<_!k+58%6Eu-gO<@wlpha=WplMwT@M7ENVuk4vFplczz6n$nBYVMaVX
zoF}(3ZY$(ZtwE)-C&H)7WdcH~o|Q-AKrhK>S!8?UF4pfsnTEPhhvbsApu^Hw2YN%k
z+6nZY?Cqglr{qF9c}7m;6K7>%7U)~~fV9Op$ZOk;2nKtvQOE@EGmI6W{l*1acEE^;
z0v$1uhk`B`(@0+%;Sr#6b7Wu8I&%*DcfI)so!DyLnh$!;Tpi^BZ!?=OMPgnuH^B>g
zw|Q|ggs03~RY4z_3z~vXn^jqGpPFZB;b&$cgL=k1#xl5J9+?SRWo;M%+F?~N1-q;a
zMtP5=aJ1TM-C)%ATdU{&BWW2d-MWK3(518ZvGoz><rkL8GcQ_4Iah94U!ri-Evq02
zG)q-b`$9D!0e@axq6+fH3S+4%$es-CsuhY$tx+SG!!q?ctzNI{@wrXv(Yc`G>Rp!E
zX?26G`?>03fIR0_B)1pUiDjVgR2B55`d+Oc2Kt-2HXIT8QAI$ZT4nEU3EE^&<1Jfl
z-$>B&_9jMqryZ09+GF>R0v)!$;ya|m&f&GAc1|wneftM=sQSiU#3H$3FJUd;@Yq9`
z-dlD(7V95&)J)I=`}z8yxsE+~pi)OP^{#c~vJJ}}PjI)vaij+5ImZ!>jO~t#F`$<m
z-{yc`ak%OIUdL8?c-+xv6X-)nXDa;2vAhT9bH`Ce<|~KidI<P};|5Q==!j+XzI8Ni
z1-k06i$Om-QWHVHIc9VN-E-W`0L^yxqTYGVsz|6>=sY+Jw8S}kHfXtX5sPfKb6q3Q
z>&{5}d(^o-9(2~}dkXZW^Z7#1WoMD@|L>i@(b8Ma!R*`H&KF04es$*4ir<}|v;#eG
zE-eMka-9zZ&2<fF23p|CqF%3SBaL~%HHmTF;c74ebjZ~clUu#*8i8S?-gW)b8+6i@
z+#ht>)glP=iR(;1*8e%z3oP01Tp|*5-SsLf;V0MS^`Ku|e_`0}xSnQW@4B}0`TMS)
zT7YKyHK-1n<M%qot(xz5f^~7ue*g#ACI4>h_wW1<Gyz@nUo{bQ-M=;Cd((g0LeNkC
zq0RXIo8xv+;bQlAwu;Z4!h%@u?$Q^u+1;8Ueb#+~?YqPM-ek~j_r*D&z3!*jRIj=F
z@wr3p=a|?E_kA?6df(lJr<``5ruARAcd<FXcE8OWTyiI}Jic=ufuSCC%{_<VUKr4i
z0bUy5VZ2HM3VVT82YlfJl?9YD78?SBIDB3S@G`)A10v|ffq-9F7w-hLUIF?(ppg0f
zHQ;;d{UhM7WuSS1VFN%51ApX9T^U$^ya1!Itgosv{;C3_&9>`PzvJGR%8SZ6&=Y$b
ziGp-iU7&O4V4&-l?ho&%bC2P#KMc{c=g2B)*vyr2k72h^Ms&n(k^Bmou@_6V8M`I2
zD?(#$lGoZ`w^^QHDm{1PG<Lv!nb!|A&qx~wT5OzUDXlTiMT5$XwfUgUMlb5$WlW*|
zw~U4i`w8O=+}9JVibXGL)nIVyG+PWz`kuMSJedOQUH$~H;8liasZ8fE-zF#3r2mIy
z80nN80gLQk<W&SspXdk1`!0M9#PJI{02@ugB(oDD(2;gxUrYxhiT{ViPVR~xw^M$!
zfT>M6H5y-IgQv~x3T)yX223Bk3fMFS;Zw~n<4%?FYga06{v_W??K4@vkA1?j?NtHQ
zYRCb0-sl!Ah;fP4fRk^tvu8;!!?I8Y@hGnxN*z8K&l-D1&gQFSr;OtL`(<@R&VEg5
z<6oEB`h!xNe@N1Pk8xOP58jY8+pdt>lXoOtsSLu8Jh#SoG(Kz%Yb`t_6<8-5c~G&X
zC=eC*AuUN*JRO)abuzH=@K9hz50-Z3nL)tTacuIe@M7Sjn^1zPdu|Q(U+*p`AgwC2
z0|OE9YC5p4KYOgfL>}Ly*%n~ys{?_L?g#|-{)(M6Q@(<*BOYNa)!Fi?2vC{4(*{&7
z|LzZ3C(o3Fo{^nd5YNh$!Jw^jCR^uac_Wwc-zDz`fOgAh`uLih!b*Hy{>&U4lwY#0
z-<6qs@Tja$;V~J&(fFxcL>oVoS7`7V*^uRVMfRHkx+(=Td`%u<s(zC`rsIyhM|Xag
zF-4&H#^H_he}QqWA+`&RI`n?6(U}G8GiE&rDl_iV!fi%t2L5@Yfc|bb0;yuZ(Tkxt
zV5~utsn?9<8K7gv)>P1Yh7k+;$OzzbXN^zTj^~YOEkPFy|76f5qn?}d=Zdj75!>s=
zW<K$oF_@0dG@T<r^Gv)4(J$r~oj}XX=1o9l<}33+<z}A(&{p#jEqu=0p+K*g70mCe
z=B{a=x6L9RU13f|73vJ<oMMmWMe?|!W;3aO@_Tf9M!l?uw-~n>vARFe{g?-vA4+Yb
z9`>QVxs7bfI*V<AYbs&%SYX;M9@wHG1Cdp~0dQyq&Qqg;_?nxN24l2($6ItR+~@_2
zJ24vQiC-`tlo-SraoPAA<9o%Jwg7a)SepvEWkiI5ZX3=J(67ehEaTseH(5a|&D9)Y
z>&?@!LTl)DF9(Z3FLIl+oKtgnJgfhKd5a@wmgPp4^qt>GPZc4C*jMBr*2WL=ObyWQ
z@+|MWCrfzF9OE*bS!8tJZmrRXZ-ZwH{r|QZ?i%^*&5+PMVAx#V8rvij7{8AWbokJF
zvSGMqI|os;c<iCxeX=V3*)Pwr>JG>Se6_qLgArO5JqzWad<UlCH}mM$pu^H;EZ>mp
z+1PK&u}tk-@>zD{5jmA6y)8#Xf-2<8xuAFCt4z(iG7Y{e&k6Z6D%!p(UtbQIZ}v!l
zbfLMyh22VXqfRL#DW9U&RO%IGtnpShU3z!`Fk^fyuz7RpX=%~B%=;|ER@-T6>zj*#
z?fw!7Y(JK2v%V|_c7K7!_N+CE9X6;I9~+!H6*#8<3Sj;Q#-M04yJOtf2Cz7Ty*y#;
zBH-lX4Cs_I=npk@S1EA%)F*(m<(x9mT$xW7=E;R7Xn~BO(~IRYPJt!z0F7QMQ&>sM
z<-N7su8_M|fmX^$@AyX1o|Zg*yYwFkdQl$f0eVR;Vma=RhnVS?<+()A7xEfA^@@z9
zRafPwT|n35R?esIWm}f)4|3Q>&~>?!5xXHPkY;sDp5mE5%1kEUH#v#Dv(RYs6sXiV
z?V(AVjg8Tu=Z)v8g5EUVY6ZG%EZ3Th2JHT8#^mOpTgHq@pkIwt8uN!y#D2YJyw(9U
z$23@JbIo#^w#59oFKDG%6`5AgniFS$j+w3EK<}A94gsAq!}UA&BlEL5*nVujKu6D+
z<<xZEJj1TKYPOW1`)28U(4Xd3W^9(#fw7-$U8gZ~ttr&B+}cWGR#{nvptTmiTTtcJ
zGo+2yty0it>omQuuzE4t$E^5rQD3MJtZ@q4Q&up;{jrtN5_HD;rV;2%Yb0Czg7vI7
zBQe|)))kxYt>Y|!2i9R~|I_j>2dz}2>AX)3X6dX`+g+dys;C`ki)uX)^o%NO3)-e8
zg@RsC1<ct?>N0b-OWmcLuc+Eg-5#~5Gw6V_rhwj8AJMSmD$~PR^?};N(mth*&jWp=
z5?N}Wsw0f==gQ{U=agi8zELyTo)^_LCi#+juIORg$K_UmpnlGiz=m#?#~gW$JwI25
zHwMj<e;o>%FWsDn3*;lbWudI_v<5Gd@!dd+Wjh9OiChcg?Dg^risfNntGUKlo;J^T
zoOL|k2xtacV7$b$7aBvD-bF?|263@5oF*<YLP<-F=kan-%Z&RN5^A~8o0Yf1xWk4n
zHHJ6!fL9u~BS5Q+v9R9WY&7zMJ~jHl#sBX-QESax?1S~@EYfbXW%tS`*wN3?|G4+i
zv3dwspUmkOqDN$C{+fq({hywB{-H^IVf0Ue!f%W$B>%tC%ad)-(+tNd`3|bVUafz5
z;jbj#XMr7(o~fWCvW#?G`rHq#sd{BG1U39IE3|dS^35Dybx#h&J~o1Hlel@UfDQLq
zz()5s026mIM9JM4=+uz8z_b)PmHq+)+U#lOp~YW9fSLU}K0LVFP1f452xeuaY(q2F
z89n=f)*Gi-?;DI6tiO#$iT(@HO-99ZY&RQ2nA|PK$~K@K#xL=poyNLNpqCBBihJGI
zO&1Rur;|a4j8~U}4jZFqgWfP2@>-es9tY8@=ETTKb8P>3S`c)!4=|(!Qmwr|WWGC!
zKM;<ZZL33a%52F=^|85{4RY4}+5x&`j$_EaGslhtT{o+=0Npg#l72GJhk+JYvl*1d
z*2WUhGV7-V&~obow&x0Kcu!EN6_3cMm6jL;T4mK)3-VfZ^FdFpwkESb*I2(XK5MNA
z4j!NNu|KHH8q7$PTf6ArIxBoWXuZ{I7-)l)&C@noGdT=5Sxs!vX6wjc&=!l|PN=_F
zC%rGGhI=}5=zgXY4LqY}4F{c7LG<Wz^<^sP3-xCM(3h$eyYVaaO-s-@HEK2Jyt=^=
z@wFP12l_#6Yy$dG^?e$2U;UT@nrU}tzGvH8XwgOc{>X<RZlA-1bn7{?8t94B&{0`;
z_qt*c5Knt*#39LAIw)xt7K5WWIEQ?W8dXm&p9~yUlNz(@vjB6%YVXR%A)axpy-{1!
zfunD5!sk_ILl<14IYoDhf#W`l1x{N*<EL+C{AVb7FjHDA@p&>E-G*6X%>%8JgL{K~
z(isd|FW=^Fv)s=Y@H4Vo6zDm*kV?19U9H(PFUpTumM_W88$mnd$4fyk%L2ZOcF9i|
z$KA3EL;ae3fv5d!jbTOoYE|dNE>kJgyH8D}tzW3p0iZ8cIqUx`wW>Ynoa#FsRBE50
zy=8U}oT3AjFu;RI+Gz)ZfK6WFI-Osu*iHF)iruUs46`#(x592djQ6y7A1?yCCBIOy
zGiS{Kwi+D`Y<&)`ZMQj$!EU#`M|rygu-|U~*ic{=zf!R~@M9Fa<2IC)-HG3z*qz((
zPc?Q|esE%UbG86>UsV&>!@*l0AJYZclV6|Mz4*C_-J749*nMJ<8@n&RGO?dHP6hpz
zq73Z*)lm2L0DfU&59G%s_Mp5Kz`^(E#*i|Ul>KDsdZ156VR+kRGPDlHja@FwsAHY{
zu0CkJ+&CQ`2RMZ=#W{!f-6o06lG+v(<>w90F3Bq#Tb$IpPq)UY?I+~qKAP1bF}tWJ
zseR$tlH9Q+#Yr88=jRm_=Oz{9PZ*VlJH2(%J9rARhZh#7rwvU><iDxOsg08}QW~eE
zr=};B6c*+eCuNT>NEll<Ha8(RJ0}l+Odp;<VMJ~c9vhuEHdp+sx`!7QBo>z>7JD0{
zXa1`;6i+GsxAm74G*0y<q-PZVYjOCO^)vQS|D8^6myGCtE4%-_hWw_HZ64<If8Ccl
zqyL{`Dj7YYASY>J)7*rD_>o0PqqE14NXp48L00<~=Z-H<8lF8qzpywdt8n;)0$stq
z`t|9YR9uujJa=eGZgxRZ`?lQ^+T*FA-3muc$j=?xyKrR5r0nsz-pm#$ZT<%isg?1+
z8<ai$TY6%=%U9LhQzLt7%ARej!tIX#uGvXhxj7R??KxZaj`UWPh3qL`S2gRAjFi-b
zl=S4}22m*~iH#FeqR{B6$xZn;P-4$J7c$!VUB}cmlo0nF2ka>Mz#$v?RDC%~X8ESq
zmp$ZQ-$_!wFQNgcy03sV!uJMgsV|_RrXi#azMUk?cb^pF>lP2{>e~o1Zn%9n<7Ibj
zGaErV&9{tX`OcFX`4SR9eSFhN`M#4N<K3#h$V5Dm<|{~q6dFOsj$mJ4lI(8W2=+Y*
z#tA!<D6ZyvK=G%czV6B3do_KVz|!seTQVMw@nxpylb3;vtzo_kDY$8Gm@hFEH^um-
zr&3`p-zjX3bG3YtjUk@vD`<>|Hu&BE8G9e`1*SpT$TuWS#>=X{MQO4wT~3p6>SQLq
z=k$F+Nrdk{BrrF&iHtLL)b@36BI~KW7lcUjwT+Y2d`p|iAmiEv-zLb7->>+Nkw2{M
JyV*pB{0F)4lraDR

delta 12199
zcmch72Xs}{y7gN7?6uE1$w`1Dq=11W5CVjB5_<0?bg7{xp_f2HQ{m7Fop69d2c?J<
z0YN~DG(kYXcBM&Cly*^2L{OUloGaXS|2xM2zc=0+<6TFb^IPBEd#$hUlW^AEGpGDy
z&W|u^M(&7uB;9xF3b8Uu2$%TR|BNj|g)l0Fq(SYF*0Zu$eHZ|U4Q-}Xj{fDb+V}>b
zN@xaEhMF)Ht9yxnYGK2)%0A7DRmL(vdgvsoOm!m|tGev~t;5`lw9cN_2+P=cfPSGH
zsdA`94^~$j0tSTb*DAX$2diDNfN9}0%qXe=`K4%)F)9zRrW8#vByD@AG;J_?F9z%`
z#lwyJO#pjK^H5{c41oJ&DIRCstp+$<n&%jq-2msqwEp2t$k$3}{d=t;-wJCig$Om(
zfT4LfXB<>_N_2tBVcM;pSk1>4wxEED+$ka&a%f;J%7z_sL|_}r-G)Oh8<Z)8TNn=b
zV5<~3iWkPfXIo+rEEC281kF}8a0TU_(;(Lj+D6$N0J%X>6wWj%bcWotcs%8k-65w3
zRj1syCFFL+(<yuU31JowJ<4axP!0||M|pl_$esW*&^@6eq{y&`)aDd{997~a<ys>k
z$AtNCmq-+VS-wOt<!vYyGo=&*VSIoBFe{g41dPqSA=fIc_1`aqTsuPR+amU6lS2L3
zVvw5_>Zc)NX4}#`*O~9jawXtaiB(;NC~3Zy<rKo+Lx$+5cOZX`cz>P0Z#-kHN`61a
z2(dBngb5qfhn^i)#m0UMaL*>&c&LmMke$I{I>#%K4WFp6r_ft}0Rnt$<Box2aYvbw
z_n~kFv_dv3_eBoWYEPs+q+~f{+*!q!PB@fb7cPRhaH%bx_Vz~Z>8qfs<D|+|TT$K4
zx_aSI?p|2b(+ii{R~n1@dQnup<em-mB1lE|$D*NLgsOV*+Sy1iUQ<_)YiDD<h!Cz$
zHdv4wWx+Cq;&A2_qwEQB6qmnx;vBIu)6>NfUGfM*=3Hi{J)!FBx3E|lknIrSHFeIj
z)KSj=;2@|r`uzx1B~{LI){!W?d0slA{YQ?(g}wU0HtIW1k~7TxS8u3}`kzN&GE}i9
zSRB*VWC_1SbY07Sk~^DgnhP;V>L-O+Cs~Lb=^Kxfndbd+Tm*69Fk8c&99fDBm-$AV
z5F@06W)?MDv=bsvI`gqvkoht4^@a?7(?@ttIg6#fi7p#2edhZJ5n<j#WlktOsjN8w
zNt#@^C~syB5n@W=7M09do+3Ww%C|;tXGzy4JXzB`WFS_BX4N%E;)sPZWEZY9G`o7b
z`&5w)Jd1o5G%A7Wb-pMOgTPu*u+#6e5eQ?X%%eB&3=|?t22d8}BR?U^6fP`t5Yk>&
z1`NXmm)Y4f*f-o=8AlXtA&>LH$*BESGLS_j%*P=@v@W#TG>0`3qD|oyhnb1yZ7YNL
zh)Y<!+wXD|uD>q(!cfybT8Pet9t!j4DMECSIy0tu0cq-5xNw<mFsHjokHZyTvi=w$
zdKT&v%}Gmz=vBC=YTod)bq(>$heN*gi_%e}hUYU^xw>Cg5aN_#Qlu~bzm0Q+JqbhN
zPpu68r?Po7A)abw>_3$eo+Q71C7X;F;)R3HZsnx|$f^cm|G=};uZ(=?x!_ky*7ZF0
zE9L$>+U=3vrUHhDK2TB;)|YtR{t0H%V~efc;2)QTeR;AFH}o@||3g_kEnA2mw6aJ9
z2H!Jh9<T9i5&S3`DCyOVe=4K;K<DxJ7cZYOQHUqjuK(Dp$m(1n&RD1ap^&UgVL#;g
z!oN)9;n_lbqMfsc!Mo!QUi3#Xyt=EWC#XoYzpED%!9KYdEKyJ9d72cdR`S7WA);xI
zQIJ=3MO7iH7A|s%_T0I=$Z#X}0B3iYza3{`l9V-&99yhXr4q|PDCg38+iA0iDqY=E
zB_PtLOAPcbLs^GCeFAF8O`cT&(XSngg)%%uIbL8=*?d9^ceDA1DPySTdO%c_I>@js
z!Ct6;b+zoPrHZ+fh^ysaE7Yrm35blXrc?QD@l*|rl*>F_16#Qry)l8r2qaF4#(2Xi
zF{(T<0^v~NHkw?C*YF-xq6WHOiP2?=OQsXcW)O$eCwf{EQ&$qJVZta;SMOO2?>r?g
zU|uQ_k0!vgm5BNJl#OYTTx`eqP@({pp~S#W#Bci&!_k9Ed{>0H9$k#X5C|oDd%6dO
zxSwKtC~-*ZXQWYnruX?(yYYoK`VvN_66q)bC2o}>HqnmNMu90Y8NH%J23k>x6n*Yo
z9gc{`)T}KaUe;C(38UQ7OMDGIsl*vKN<fLy!NjjISd{3jkIZU8`A8@+TkAi=M-KR{
z53bgf@&n8e#Je!k36uvTIZ7<hI15#YgE7GoW9@Jw)VvZ2bBXKp&aY>=xwxw%w6X@}
zpE0DAxUY>E-HvjEPG8e$lnYQQN>m+7yn}*PqB=gODA8Z1<GA*9?VHrp#LE@&(E6@A
zeN$Ug6M;ffV)Jt1@wWJIqr{qIE*$u%1MmA0OX%Epz~oh8XcRFcg&3%lGAxJkhdOc}
zPp15fKCG91YD`;dE-fYw*Z7G+dB9TQi6+DfeTZ|a<HMB_G5EZt#FO^Kn%dVlbquy>
z`I_E33olwF>S^@V2iMiPjMQ~gKc82}7AM}+VGn3TIcXNLEXJY|J9Qy{mqfWrEb&ZT
zpj&h&i5vBZ!Dw(Le072B)*cVkM(n6X{kOVn&geou5J}Azz4djS*R2hyNvKKW`$&ne
z$`PeboR7X*K9!n@y7bapP%hnf9%=Oi;?MZ7rNp@a;zgb5RL`7{aQ7HYZzTqGAl3*Z
zey-&_ZB~N5bC>pbe-B<Qql0`+U;S9u&{r*~kJDElWKgcJlX$E&<sWqk_tx$e=xprN
z6}c&aS66h<R$tNa_*n=1g!ZPVu9yPt@ey5gZFFkvy4lioEZ<zoEpqhn?G)uAGl~5@
z<3dB+0s7#9y8dEy5@)%2b-FgInvUXTT>vL^*_P8MR?zpi=*BydJm4bjyuC8zK7EOo
zb*U`YF`lMVe|0eRE2<GU>0+Dg)-jmboT{yZh?#h6C@~|Om>*7T=pwe)$6wct{X`%9
z3tksWEbK!3NbfLNXYx-S?@)crL;Y-MBJb&?-P@}hBB~fQY5v;Ru#Q}O5<@(qt^P~<
zeJ-7vx%z7HIg}4+UxRfLFG*^w?!=3_o}9W;H{?>|8%1nVia4_Y@u@cGN(klWy05>>
z(#?NP+uKZ!qvbjs`*gB4=x!2P|C3H}5uN&5OS#38@x))26AOxHO&#J1?Q0v|W&5@F
zd9|spj67jvXhREh85Bp=qWKp#<%RoGiB|>?+vtO*cBb4-&yr4hsF&6C)LO@EM=xGI
zqN^dwpYrh4#9u}cf1W`M)>XJv_i`s4n+tQPA31?|l`(LOWM3|<*2Fmrh$nQ`Z|Q&s
z4xwh1*1R`@a$8*i=0eJ6st^b16x7u9@lbm<M4LD-m{*@pCQi}&{IG=ba9z$H>MnE7
z*Im;hl^4oupK9pr=2WF-d;qb&4>4NjwR0ThmL{>AF5Y78DEn%^XX~vGy+ut|9oKON
z<;^-Z&T?9=MD%F)lzToGC$!Zk^>)i<Q}deMVz0Kh=}KxU6(xFg1w7GrCXS|NT`X~<
zF59nrQr@joc39tEM91uut`fg-yn4DT(UnfTlB)xCNLS-kJ!)3zv35>trZwVCJ9Ia%
z)cL!tYdEbR^)GdO#A%P;?n6z}c%lp=_Mb*9rU%+&?dxfsxW>8+-;L(gHbr&)N9soU
zRafRY9qQqFqv#>L>5$%TtuC~1-4|_j7=?anpss+5x)*-ae*d5yD5BH%v>tc(Z7{Kp
zcIJ8<<*}WJeNc?3|1Wjc|I~F*vOX`IZ-r0V!mbTEh?^`is6VkAwy?y#0^$UH=Y8~x
zCC+Gl6HGKqY}P3#rURacdn~bBhyBM{+<8<MF}DHr5j4Ure01Fw&DIa=&hDrS>aNal
zeO>2!ynM{k0lx@CEwL(%njc}7636t_z(DF3Y41<qDGR?O6H6d{mI#HDmZ*qyTf$MA
z_^1}2b!SF%(LJ1)pF}*=g%`F%gE^%GTYmxNxAehgBIQBViH&;`Yw37=J)QDCG_xfN
zw5IqP$`4_vB}Q1pUz-tYkLH~bDa1W)Y^ua!JuXHCP;Q(|yoF4IgmQk_9q5mfgetPl
z11wsS9UYL3qx2o6GdVk=S`(uk40HTS8kt-x3YeD25^S)YHPE<c2C#Dq-xV1yc1(A-
zvj`|VmnGHr<BGtXH%#F07#cR_EgYi8j^T6|A4w0V%F~S7JQ-3KG+&NJ_|#GvhmfkZ
z@?H#RvpmHj+bP$xe)q|)s0+1UPFxH+Apc;B56X*8K%dHHZrXKDj;E97<zPN>K`v?t
z`cal`1X^Qk=e3PSAcMWj*un&VX#9b)RJ#q6Ww6Hxj{qGu%CYvY86!y7jgsM@rM9)N
zgO=IGvVWJ`ex(!ZY&WNY*4q|FxWOB2iL;TI&9+tW!rE@TFb2wVwg<&PpWC)p0exYs
z!jt}HJ4*|{u`Oay&)a@t8T@41Jpr`9T#yCYV(w)MwwXN{<(=j;u6CILd<X3|XHFGh
z{FF{$>6U5h##vhNmH9j8<t4KM_x#@6&$)8nyo|z84@?hd(?qqGr{^no9DZM%rG^X`
zDva4`NbfN?U1g!T)FL&LIb5Qy)9U4_C7)ZR>P!KhQu|nDU#I}IpSq}87$Emm)sUV1
zy*e@nbW^4B;$2nH3-q(PmWhb`q8i{pwZJ-G6ST^DhqtV==JW-<Yb|87w_0h;*-oo-
z1n7YECEp=Ot<Jo5-0GYSI%)kK9jd;wwy{WVSrb{yKe?^;Oz#7$9E<gt6+8j-(mGon
zG{yej0MLAUQ=Yrn-faPBsr@akR@e_02d%g7W<71R+oM67?U(z2cG#2Y{Vw}DdU(p-
zd===7y*3a0+`fx_a?yT|k@?o{z84I>X8(!1eQ$5U=>2H#!ff5PKOX`5&E7d4^w_>G
z9rWBD#QaQhH08Nd9d;yC<vX@d1kG}cnFN~aaI?r3Iu2I?edK6Je~&xP#eyz4<_rW~
zcB~u*`oYmx_y1kTV_N#aF^PTq(6Oc;=y%5gTJeYD&-$R3j!E-D6P;K6K~tQQIp3!{
ztMgos(?et4a}Hsgw>V3W1nqY=VT&AbcEvDKpEygfZ_YZ0aE5;2tWgy7wKK3Y>;H;#
zHH-A7Q<MVTb8ciM{OY{49Q4TPW!RoL-(+H+I&bp%7tRpoV1iGDAkbu=Z5X#|n$NGS
ziz~kFWY7)Y2JH8nzE@L0cYO0lf$sTcGrsqISLB0!^{rKv@4v~e7id2<)778kb;YnC
zmb>y_2d#FcGNfx=M^=EgxDKLS)OOc}$)H`X`L#fMUFm#ozw0w5_NeOxnpmB5)#EN-
zxK7aeORjI&9M@g9nS&dy4lIwGu3IqFt?szSGTixo=?w5}zmbgBe7{BQKnwjo_kx!A
z&0{Q9_@yz3JN#xaz`Ohc>BSzu60JbT{8HzE?)qgjzrXuk=ef`PK3xKu>ff;oDBu4U
zXKI0eDU=m^-ZH-}#`vqf7;TnSis#!O4l2B;%&Tp&wvZ@j-z@`ltjz#AOTbS(G9sTd
z{N+0$UDjloS{aKeGQBxg`LaP{tY*kBkr`{Ie8vu#C0imi)+*^=53AKOkVd(m$hX)5
zFXV<!ps7a1;h>quS(efw!{E6~joE`itBvVhLEDV6JpYgp!LWa3JV#q-bBfgCh9!I%
zoXGf@z=XTZMXleGfbGwB1P<BA@XVH#;IY~uM~Bk?1F{I|oO~O_Wj&Ht5j4G{4;b&e
zVvC@T-P#CPX&5G%71sbAX~nm|bTAV5FDzDKeRyak{bB-><2W@^{1btdH?#z%&gcb9
zYqtPcr4!Rt^#|Oks+COV!PPq~12)KH`8GervTb)1N2~5v*?IkwSP;YG1A$}iu(Kyh
zPZTI$rg1BeoXRu2vMp=u9XW=tmaQ^^_wSZIh@7=oYU4kW+WLJ`o4;Suez$QzY7Y)d
znr$7G+LL3Ft`r6#xH*L4-_rQ7{Rp-y*(n(q*$H`2(eqItD&`?AiJLGEn3TgFNy!WW
zR%^u4uJuDVV4ZL_dBbA4z-9|kf~r+^arR&PdMF@$R7ed5BK%?+u#9AnRT#zXQ{&eF
z>pWumn{Dw2wwINF6Xd%rtckJ?OLdYQ7!Fz@!&zTT<)6NwW%A5Y&^xmBOwd|c5CB>y
zN3nI@mp8H*|84TAA85M_rH^~%ZdT$)@;BySpA@N}Ph>4VcwCmJ@`OyO4f>mO)5dS4
zs|x76titxVCDX@)ZcD)o-;uYNs>jmHbUcyI>CPXrL=I@0@xe;^Ki%+;#WLRrq4$f8
z+ALtNF}eq6iSY|9++bug@b4O#^mn6S@`&9=JBDJ9F$+zm_8PmYfle5wlR=*v<)cBL
z8!3G5g7GKY@v89-$L2L7DG_wTDCgq*xn*pR$MT+WoKHM9GU(_8+sjPQR2$xd=oi~x
zO+a&Oy%>unws)t3mfD&R0j;xLq=oBkTNG%AZ7=itfo=U;pd+@$-1?|32UVyu+{c$W
z9MF*4<-||m`C|^!?eQ%ezPiN-ErWHL+jPI|qt&mpR{3&RhqULiR2=IpItkZQT#uo^
z%Eg-kYeX;*4O>+J_Pm4rR6mQaxv>>tj6U9eh|ZNP-wqgaq(9IdJ8lFhK8-Wt2jd6E
z_m(k&ZT6FKAQ|+)2oD22G#s2$zZ;EN#(x;QSV0B0FEKLkvF-${&?lrn>;s|OCNBHz
zq9>VES^Y0<H#u@9n#stLzVkcjE+RyC>z3@s+W5OXUmWy@Jj?r@%Yocyvf-=<nqk!7
zYOxXJ1-)a`MyKmNiZ6hqg8k6BDr^(|j_y_q7`vGcG&<@zTd}13Tms~%a?M{o^Pwz8
ze|AfQRkufu<Ev$_tcuX0=);(qeexJg!)NBXbwCGXCC2igEMQ}QEVG!}LvlMad06Jq
zq$4t`6zHg2mkl~5H!?M!$gZqN_h<4hD%!d&x6K7jvyF^{Hs7|wiB*B^m`*7)Nl#I0
zD)|aCmU5aeleCh4z-miam(>$_PR)w+u2vZih}!2^({+BF39SFNKd?a-k8SuxF0j>V
z8r!yLKXzERx_m67{2RbQt>ys-uV4&v=B5LOUpIic3GC&OSu=oR4l$r(&!a!o8|&u-
z$L;9|oFvCC0Zow$=)zQ)Zv#!2CFt}_xsz7Sl6z?MY#GB!nkyeJ=5n6gumDsbgFGWD
zMY)r?{YEMKf;P!ptwEcmo8`Dg?qH_hmqr5UlJsX;-jboT>b88^0(3`y-wAYA_T#m`
z%Z@8S_vF`%*iZ5f(ySiHN8IxlnaKn^mMhsi`9|76(0t<yH%(e?bm#zj*H~W+^s#ZX
zHs}XqiayCGorTpMV^wv~10!!V=y#(t$Hp_GFZ=bmajg+(vh9y)peeRPG;NkGkzp#Z
z*^z0r);4%N=!7jR2K1@zR(H@jTS@)S{oM9VB$i*<K92`ou^r+`S8Zq5Rkv+5CFq51
z8u$Lowu~8@Xx3otCz;>Vm?`G&*Fkg5Wi)1iS$!C2v01GRXsLOUw9>rE%&j&b)BB@l
z)4re+X5>;)UZ~UNaE0YL)4_0mW%lG?Ja1ae>t!>8Eq={B<*625(p{$|7I#gHL4Rp}
zz|;RS<x)_A>cKYis&*`$Won}nv_dVe4_c#AM}gi^i|T<ksL>&y_mqb@+pI1zXWP_M
zy17F&V(NCPZB0RY)KeDjNp+ltol==@&Z^UDAxrz5Iy4pZx$3}D`<vR$_+C^N_r9W@
zctPK(QEboe)mu#R4YfSyRolm87lERD=N`a{$t;h_(w`MDMb=9JO_iVa1Wl6$=izi&
zpSR@8JMKE*8M19UXr`>nAkLDrVVt#GUO}<E>T5N{SjY)7)o9E*o@S&}1x+`;<lgzl
zWTtn9k;(FyX>_59vkX7dY-1%}4r-3^8-|3MYcyl!%`={`q30Vjs<^=g#=~&X0wW97
zTdR#I59n`32e|nEoF{6rtvKs(x$RxH!**MrR)tZpqL$PDn1kq8JwStoa{2}95gF2F
z(W|@uZ_nKSI7wYH#wXyw?~Lk5{(p8ZcedPbGaL)#T~vd$P=E5mpCs;Af^xqc`3C5)
zoJ%?-y_hrFnqpTt%!*6Q3cWU_tmgPCbGa+l(GB=EiP>BmSn)#>Sn0PF!1%QcQDQCw
zo$Q(dtQ<q9(pEE|Ro`YFYP=l`tTn#ztBuoxnql3m0kcvd(`d#rV{RwVa^n%}eT9+7
z`deuX)PEpdW$Yb?<!Ylnle@;)Qx~+wC_!(w8uM3y-ZvC0?jz$omHUjxiJ<+)#@V0)
zMvqCLgGL)(TVgxNLG*!bRH;I9EZ<04P}F!G7+eFX*52>8?d!)62*+*pf}lBPtI0|A
zm2Ku&&;{FdJLrb3A47K2mNgu7&z4#Pbl-M>^sDV^7-+gVhC!KWdh$SX%n%Nox#nTE
z=R9*pThM&7Eh3`|OuufR1!l-%kjD%g4C=AaT*dxeWTtcmEjGK-O0W5qFKCH5sV-=#
zxt{(lGmA|FEjOF?0<AEIa<`S{sJWn3W~v2RZSKwhtuguC3H7#l%(E%Eq`NkU?l<aL
zF6g`(oe8?2EP8Yi|9%O&q@pW=E~_kd<G0GH1-hcTF9cmx0j#v^s_g*K-_@~H&@ZaR
zo1hmeI2km-8p_!+$=XVbzPEnsE5P_^kk5pqx9uAU>iD?AE42~DZug61z>25GzS4G!
zo``iu1Rv~v4mGNJOyR8RRhuXFZbd`;Job1BQi9$6Mq<(LbQ-XK0J=sE2x3DIanPKc
zpL2o3pG5=T`mh~v+;PT#{4-Y91X+<KK2=WVbF<`AX0Jd_qLW_f2mmdYx4Bv^ck>1O
zj!cgLt(W6@=tlWX9X8D-d6H$hSuR=$+9FTR2E8vmd>3t#e=?5SWj%&^ul$_5{bmkg
zMg4A8=fqy3Vy1#VR5`Tuk~-T3bXm=#h2N^Z4M0~^ixHst)^pms#2SfRbX4QqZbZ_m
zyr(EIm0w=5()eu^s|vrKVpWZRVOBNNt+1;1;ypD^;zeN9<Tq5TTB9ceYxj==*7*vp
zZPoo?39#Nn>g!*H{Z@mzJ%J7REfuQ~zl>rvUV*Z*n(#X)R?{^8R%5l~7f!77_!_`g
z3qpad<9KVE0*pqhEx&zYwd2=KtoHn>iPfQb67Y3?%f#w<hzE4~pe3+#8_Wf(%VEUN
z>dG&dSlxQg17<v=8{OBVq^us(mIJ*qI198yhD2iASWD%{JY$*kWdxQ>&p3GehC>LO
zXy)*Ik{X}Tpn6984){q=Np3K*Pj<70jd~`<Cnd%w{fjOmXYj~=1BT{ic#2hP6g_&t
z(3E7}7M~cOoS2-Fn3|lDl$w~9kvDAE;M|Np1BNEV$9qOqE9Dy>52^6SGcT?5zxA|`
zl-#ko;@|0CaN@u9xDZd9>OTLwN0$4aWX%0v)JN|TL*j-G8=4)L-Mi0#i~&P42an9k
z&d7|7%}7d$PeJAV>kWDRM-J(eF{(;-+>qG5IT`(XkH|ua<uSDhujgiu$W6%XJ!0_a
zgofF<gYt&uB;=JE7MIr_cMlsjG-33x5rcAbdS_<irlE0p*|~YSo}<;1-2cC4|MN!^
zS`O%wn~<B=J1%qBh;01XNt;f^e>3s&ztc$b(n59`HT##X`9CzeVRoO9{dP|1^;S~x
zRxmqn<cOgW-MS5ZC3f$=^Jzi2<te=^WM_{hN9E2c%ZfG(OHHa4msG8CQiX`ZoJ63{
zlM|~XCGX6<R;`{-XN(X-2{F*IXG3ZE(k^Fv*T=}wa-BE4ylgEGc!!YAcn^~DynYox
zpLn~Ie)4WDq!*;;-t>x~EbmIv6z|WZE#6wOvbE9D&pS6(w!-o%mhy@>u9CiW9BH=q
zENPcFJPvfmI|O8u4e)*(hbI<#{o<j;i6Fxj=zTw4wlZ1<dS8NZSb750LEcpfP*)E1
z-X~{-d21))@?h_rL_9pjdzEy?8<&Ke%@W@6Nw_Jfg!dd6SHqKeU`g-LWT<PF^nMJM
zKYIOA@X&K_caRYj?tMQ6+S%S0DKb`$_g1JZ%h2V@GDcO$8>_K*EHx9nE1`k8$3ccG
u!h656ET@953sKqoeK{HEt&}Q@8cnZzYp2R`M(5k!zT`>~-npqV`2PTq4Q<W<

diff --git a/Debug/Libs/sta-core/src/debug/printing/printable.d b/Debug/Libs/sta-core/src/debug/printing/printable.d
index 0b54d7d..47c170b 100644
--- a/Debug/Libs/sta-core/src/debug/printing/printable.d
+++ b/Debug/Libs/sta-core/src/debug/printing/printable.d
@@ -1,10 +1,10 @@
 Libs/sta-core/src/debug/printing/printable.o: \
  ../Libs/sta-core/src/debug/printing/printable.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/printing/printable.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/printing/printable.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp \
  ../Core/Inc/sta/config.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/lang.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/printing/printable.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp:
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/lang.hpp
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/printing/printable.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp:
 ../Core/Inc/sta/config.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/lang.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/lang.hpp:
diff --git a/Debug/Libs/sta-core/src/debug/printing/printable.o b/Debug/Libs/sta-core/src/debug/printing/printable.o
index 958fbe1be78dc0d0b985230fafd5996a082e4967..820a0bdf2986e9a6a2716b35225df9004c756416 100644
GIT binary patch
delta 14771
zcmcJW2UJzp+OF4JjZH5Cf{0>4K#*#|j)ICt4VKsy5m8V?6fD@b0yZoGx4OaJ3wF_{
zF)@j;M9qnwG)vS(jftAXn4+ob|GpDX?m7Sc#~pW!e<YFjnQhJa&F}l>TwAj9Xr)=c
z(ku-Ur3dQyIkZ2#Mp5dWsG%s++bD{Q@}K_%>qb^izM{=fR221}HQS=sRd?vUS5X>y
zSk(2xBgi(@A-MLpF=)5wlP4=m$dq&ptrS`k##%y~_o+JO@VT(&?m{iB<`fkJh1q?i
zqG<hfG==+>$R^9Tk!boN3{5Tk*0M=8b{;@ejmBtd>Azn#Ir#Fyg|DKihu^zw(v9Qe
z(R74OFZ+Kgn;gdMKvQxGnnwHOzzi)lF&~vI|HtgNIE*VtTQ;_9nHNZlv~?3uUQmao
zXn%034RvUPHfl7=o9c3LZHsM?Q-gjpmZIf+T~4Ikn}zbH{&Iyk8lil%mTYekf$~@W
zFdSoMqkOLx9jEObrYMfyUSs)e3f$x9S7R2-+DO|+PWAmKz(&Vt@AGW3G(<VR#toKt
z+uWQRxSq*FOAqgS4J{wp+Bw%uYqUsFoP7N)Y)QtBodW#5S>8MY<=VA^SPn`>xt@On
z%W6}U>(`2B`JK8bhxjM4{MKfaLu;k5JYgNmado8WBW<raHweBl6D?ip%9hsdC?^NW
z&8+9@z3R%%AG1Akt|_8yzAllSzTcxL4Gl$UiXTfWFGUf*Vq$>=QIs0XS13wRcBP_p
zMsL6WX~a`>&NyXT=u+EU8L224nYLXnje0otRFu?J#ftJ8o;mZ^b6%Ez&FsPvgN{cl
z$`$n9`HvBb?Cjg4N>Lu8!?1a{d7B*H^Cw%pYi(If-eDW$THDIjj^-9c8Eh)bDEw6K
zAjk*C%URld0B21_N6}xM{r~E0{s5gT(6QmK&YG~W`pK9=OnVR=NB`BSxcr8u2ycY$
zJlZ}nl^QSB<G!kUL;Bk+Zned4wqUn<4jdlXu#2sSTY$;3Z;36(t!6Nbp8Xdq$`}Vl
znS`HeqorL<*eP6`vTT)Z0p9Kl6eZHbHC}l9JWo;H!%+Rc?W$Yt#;+jtTw4omEt))b
zzJf}U@M8ZD_z~YSfE2~!l&!9Nh|jyz6~&udGeapXd1TrKy9cSx!)-I&8~H37jRE=W
zn@eHI<A&|1d(iMty5V*hCge?`P3)*BZjo+0$Xag?l=Edd%Hp<JoJJ`892F&6ciW~t
z#RT=XW-H2emt8DAPF9p1HQ22f@kw}aivtr>F&5h5J;KE~+enXk{;nGp#l1m5M~w10
zgrn-$^mP=Cmc4B2JbVM5V$1F=ocWl=Xph^;y@fX`E=EV&MUVK<kp5_D=U6>$5$*@~
z_OhZIFLgyFK~^lrC0mrIf7+6GG$qO=Z)0r}RFY)H&o~x|N+(&VZJc6HXITkSd`4$s
z>AcBKuxa%GbmV)otQc$JP?=<MWnD3OC;9x-w$n3SJh9#OjBV!M8{He7nqn_O#=3*3
zYz}<r!b7(K2i$#Ypr@;%gc^6sP}$+y6qN{Lm#wQ;v{+=D<`wMTU_LsIN`Ivoftj|w
zUVhdVxS8Bfx`krSAx3+ojQhLN%8`oiez>OlXmJ56=)Jq6XRN69wO*$kYPrIB7M9TU
z-?`CT;mw*wA0HuWby#!J_hVl7iNeAydFZPrqLwclnLFP4sI7QsxK9(lHl&(g-PCcp
ziu(-Vb=6H#YU`B?Fm#r1x{q3rKE{?^BOv^Z&S)#Hemp`?-HX~hQR5*-MC(fvQJXJ3
zenPFOUT!;BqlI{2dr;$WL`Efgp4OTU51SKVl<zcL2Y&U$do<oiM`wLxJSvKQ)ONu;
zKy937yXPG^>eo`3{E`U7g!)Bps;8*IG*a{o)?Ti5hOVEXyHl$BEc&5QsPz)we9T2L
z`G9YdRZ&u25$8CQnTGxW)q7BM=l-^_KB4`7%0lB1Vd03{dYvNFhE`ACP)}%$+Atv_
z6sotT2UDwS(RvK-R`=o6wRnBuK-AKzYYBS%INN=ne&VJr!MB#UV;k%nEedUmee2e_
zmY^tJ9X;p@?bd9RyLz5tJW6oI`yH{J^X)GpZ1rk}i&M59HP@?JvF%~aI--xw)vs>X
zDabRgCnk@rk0-8%-FQZEP+^qUZG$lm|Eslu7s7i-Hu@DIaDO;<VV}I<JRaC4`Nf8w
z$JzPCT=dr?e%mqq`{u@fH3;U3;?U4`(XXNFQ~2nVg$p`FPg~~iEo?R)|Gco|K8n)b
z3pYzycemAe@2?5vOGhnBaBGb8UDG@UGpJ>X{~xvk{=>unHCiiMW0k{;<Z!L5)GEgp
z{oD99wYrI9+x%K#0?*b84*1uzYFWN>&ZKclMp*SqnQrZEKhz2k={DDZ{~VQ<KT%0-
z%pI#`xo*2`JpzI;V_rba|20?NM(;_hb1~Oj|7{ko)w9ul**_8e&jW%Z{<|&7!R4|)
z5B-Xg-29%-HM9B2>`Plp?EoyBUAsASbL}YTM^d%G1}KLF{<}HZa%&+CtIgro@&f;T
zQ`P<T8&;b$2K`n4Lw{g{YIDY-|EGWJ*UAoAopH0&=WA6f+hIjm;_A>T1M7r~<f^%K
z@^rDu_FMh74WHvG(!zXjGk}gxhSODi>d;&)hS{eG1&goYTV@;7Al4eUAE!#!HO;6V
z8|iAet?P*)9{#dH*F0+(YP$@y=mFI&FWPI=t}Ylpb<5D}tG;OW4>WXZ5@!96(YmQM
z_B1SC;CyS&?uPU3XcSy)+ngH)hzqumhOy#^ZBWA?5pSE`FkIx>wnK;8K57_geGY33
zrISDPY7TXBKWb=wYVu*~&r7I{dQn>*qOQP=YbY1+MmCg&9@M;5)OY4lHKaUxVWFY?
z){I(QPCbI8H<U^_n{6k{tE{-;4dnwkz)*Z^QXj)~Ls?fy9VnOSk4wf-4#L-la$^#8
z<~r)C0_u7>b*db{KbI}vnbb`!s5j)yh4>4Ap?nMP7|Lh))DzOgm}R*94CQ(Us>57r
z0p8Bor8MPoAj^5uh@TCXPY<A8lzR=3o=Eg&OVMuXJ=ka{8JnmN<(PtTELTa7_G!*?
z?H<&ZrFU0&Dppi-kTZtTW+-)e4eDm;#-m{@Czn!3IZ_Mpaxj#xL#Qk2QCs82#x6Tk
zpH8H1Pp01ML|wIkdRlrV3un(z=E`tC*vj(jnTleCEnQd<atC4f1Z5~&<UWezlEvfM
zGGQ^*l=0KDSUxC2uutyws$B9pK9L*BYxAimT2j9pLA}0~dRKa`3vN6^S&DnoP=>O_
zs`$u3zfEP+EIGvhxts10Y_Sib@<X1XjF7pK(4FPO(m3w~mK#YAy(~?iD&u-4j_vn+
z<;Ym7?N#b|>ABr)S^h>QyY=DAtjv-Rl*&N#n$4E__}hx1OpT`sxxWcPEZ;4sI&P!R
zml<$TW`?Is((d^Ci=iaQc=wlQD%Z}I0ypZHax-J(hJTb}>R4;ABXl9PFol{VW45#j
z%N5f0nli;6&SA@78Na}$EYFflZVh4iyDDmsN^OY`6NYlKg!)i=E7X(a)iTiklwQ<_
zvgO1Qng2^oR=SU--kwaoUqQXmo7y3mTHKC0K)UYPc9uVv%fBW)<m<tfFxhf8jOCZ4
zx4w`@{7}r6jRU9=g1Sqdjy_Ff{_l{sJ6E!!mlL(sOVnpFhu@U3ca!0myprub*HiuE
zGM8mS1;`EDmRHT&_1J4|PhBpJ_*`Lm<wojNna)>aI8Gvn$bVaZb_|$By^v4+C6szi
z#`vbZt&Yl|%xu8+KjqXha?DjZX{x*#ue4$BTA5<KvRIDZLA@bOzr2U#mi4JAYp5$Z
zgH_oqubRFxiGnlPvAH=lH=7z#hgvT4<8ED+_wA!L%cCxnzRBOra=0tCIDwig^I)J1
zT*Pv=1mK-(D9^`G8|6|j$q-wAlKWmFbFx8o225vn<R<FRJE=RTQY|umxdT})bf!L#
zA!sjyQYmx7L+-DsJcJuMaLhji^^Oc^CwYG;eb}<wm)glHZQn0<*>4@2%F?NUGL~hs
zz58&s9ForLFB7N5YPRIcB`ahsuZ(3&heB#q7wQKx84EhHJWwWbv<zI`y=>_ugPRm)
zWkoHbD#NG|a(`ZpSpK|#+FnL?g-oL5ayo4>+n>y(wu_|RoJKt&vuB<>v@K-IPy5+E
zLmD)07Rzoj&>Q4ab-T*^kC6HAEg!xwW40En;jWeopO*gkA%ZO}<&qiFrSD2Z4ViAm
zJ=p6hud*QNgG(}DwRUXBG|)fgQ(@g$j+Uq3xuc@AG?X>cy-xC;`a(|EQa<J_A5&WL
zfv=^0FGm*0gtFTjHwm<kkzqP0Gdxl5uXi}dhxt)AXHeJ4NXLb+JhTn<fDHOtd6y)o
zvgHv>F_dj`hQdWG$H-i{DAPQ0Hd_+#sRuEU<CnEyd6snqu{MF)t}(USM5>=W(s#PD
z>^hG+M!LPO1Ir5+QhUl}&TnKnOd6E8h2;Y>WRB9%pQMSK<+GjTv$^#-CMK9VcC3}i
zlerQ%f#vd<)Tm_Y;g_gWq|byra-Yg`;awuzJ*l^3`|BN8-XxPceiF+E+EdpiQp;r~
z=}lOEe>BxodUQ^*%$^X$34>%dRLXr{mJ?l+p6J|@y<Ks1P35?pZWmfiWlLRZS9roy
z%0^MotmQ~AB#Wu6#T{cRN0CXUvU?8Od#6zE!b7IAU7AvyDsRt23)qpigdJz)O|Vqv
z%H>kFMAl?){5I-Hh5CWqS&S@?k-q6)$&rKQ2KpT07;ovPWeAX|yf6K_3zwm(`~kO{
zN)XPDsq_zpT9x!1R!%RaK91$XwYIWc3n$1_K2M<Lpv6!=#?J7Dl&((KSe_$&P$YXB
z4rL2}2ZpOjE?m-&W$#v;p==)Y+J5Q`K|MW=YAu^j)M?A1hRn}*WSSfv!<G&5VBeSN
zwy=83iV^BF8P7!AE`~PIa1hPNKanqH)M_}?jMiZ$9#xFG7s{aZ*VByP&VkU#Ynjm4
zubM-fM{)&g;^DbK=b;;*13sh~Lp%{*V`v2IHZts8p`#{Ef#!Y&j~El0?SxM4TmUV&
zWP{F%gKLesB9U{yDg@^!6_%Aih4{__Y!*K@0Cowp2T&#6;WhKRXt|y7KQ5kGQGG)U
zriE{coBqIAk<WL<2jUlo|5MSF23!_5b^%|C-{_$Y>L(q69qK+VaY#+$m2+6_-wAk4
zJ<%IDq8h7!x7CZmz)iIoYoDwCV2moXPnjv!RoXOPaJ81qi)f4H*#+3D<uSh7v@sZC
z?$S0d2li{<)kEV4+SF0NMa|U>xTFOR20qqeIq4_bn?=B<T4@&Wt#*QEeVLv{3wP^p
z@N(Lx8_eG-y-N+?P=f9`9eho9M^aQr?U5aY2K^B=S^rRXUxU(B{kaO<(j!Lz5B2Z3
z!SD4UwwbZ@t&WFLSz$cG0Wr#r3Kw9t@%av5ouN$t&KY%S(IsOPSG!`g-3r_=`cDFG
z8MEl*yT<gXz<uL6&Ykg{k&5&%9~o!EQCnud69lX?!x+^qX7)?KcJt2?V2|0k_I$9)
zbWR7}FrOpUjg#gs)=ryIwpMZVtsC-D`NPc9foJB>%|Nk3SDXN&)L|qqo0Sgxh65E2
zZ_feNI22|ATOIcBOz&{0yA9ao@Hy=~;Be9dIOI^m#&ZruxHydW9j<WIiw>{RNmm?N
z((2C~2DSulI@Gb!-dheYEd#!EC}r(yhwI$#PYypY!=E_BFbn>4XyF4CT264Kxt9A(
zkp-4+v~ZE-313o6ElY4!7|Sj5xY9Ap?Z&`qi#`~*Y;odb*DSB+0Cy}aDuDZzgXK){
z?=344V&g|kUK;S&vYWgA)iRvHeP+2E56p2KxDzOLyj=*)cl2xl*c^LsiJgu&`6k=#
z_;3So+|iRa!#j?%#{#DugA;&%I9441E;;^Adp~l#<_KJOjB3VP{;s3JZGYo<p7_Dh
zk8b<f@j)E$i(|G4{O&lw6?p1+W*RWt$>2&wP8TKv^PCDN0@t0}@Oa;Ley=ZZ*SS7V
z={@JvLBKc8!<cFho!jpQesEso1r)h#OyManacQ>^RlCb2Ct$Tp3&wE0i#I<;Y<78%
zZrknBwE?i-#hD3s$mMD@aMa~NE8w`xS=@HUNtXlk;d?HPl7LGte=xpRT|VHD&t2Nl
z`r9tknF)7Y7BB|)Tmpvy)&;J+>Dk4u1Ns1^uJ1+y%UySL2g+Rw7^gL^M-KuAT-zDI
zA=eHofFrK07}$4Re`^BVcManSd+geROZ?$lHWZla_G>w?!0i`?sm$$BxB}u&$oX#2
z(E2v+zwzuWREmUWQ=nM<MpNgCx^sbfVjEpMU%XFeED(cu#uf@Mrdf#?83rs8UNJb0
zs|9a+<FJU$0A3T1cL7Jlj+wwwv2+M<Oa#^eUKf>&+Hnzr=ZrV3Vr??`rU>5-oDkg;
zfw#nWyeQrlt40Iwi1!)+C&hOifp^6W-X5n!=rZ7f=oo?JzZQJW7{%&w27j*lg$0<W
zo(uuztFIOS3sjvCEL6vG6D8`@CBP!px{aGztPWyAFHtjdfu*X^8hBOxo=2`!9Sgr1
zW$IGSwoDy@;G65!L@a22tjbs2Jgt5w^exch5OuRm<J-<ysck1#YlGZ?{n~bfgx)vx
z#7YzlE6g!X>n)~~!yj;)42^y)1qE}~9=3Mx4YhpK9O^h4ce5N(FNC*4=xhYfEE0RG
zqm~Tw%>^P1&Om@7k<ey|2;yN`Bn}`5<~p%?9ct@EB%U*V5f2%zr=p8>4mejmEJLdH
zWrS9!U+xAfRCnGZ>(zR+VxM}MTYO73crjm4`@?K$j(aALMy-AfO1<}(Z&7V$L)%_s
z(E1ec5*ZiQ0lHYcNhfa;4VVsZh*0K%^#gHk1nm1+w9R}mqtmHg=<rzTkLK{Ub)gZL
za-dE4pTNw>>>BtDYZU(rxf%TgQ<yP1UeMT_EqE$!7w?d!r<|b8D%V1rf5`N1F_6g`
zzkL+6<>@ZaR_7K$6Rp#Dp>^}1_ReL;(6$SqnOpZmC){v=PPH>t=ZFUhzyh(bKVTDC
z+@)RA&I2}ycJ$RA;S~wICL*`OqN73@e@sa0Ul-E+<3ig1hL9V0Q&?%Xc~Z!oyeqgB
z=~kz=X@yUJM#A5T2^jEWJ7~QcG&}el4_3&v?$9Rpkr_tJL2fqgs{_!MW0^f|7t`tO
z9e5&=9CT>c)7(JMPZ;t(A!x@+xPNO7OGhcNKbspor|-ia&xbbK!{O}*c7%4l#B<qa
zI&YrYV!(1>j%dQj7mBZ#vE^brZ`ukm(h95+8<}65L=h+5EdJzWyhZ#x8`vvma69|N
zg?>QO{bCQNIVwV%0LR1<xDJ;@ZBBDaIPs!7EruNi&WNO9;A2tCCR*3GwjYSf6Y<e{
z;1{ug@%>eV7XkCs>3q%1S37V63)F?k8)K!KITWy~?}q^8>a=`do0{PcY*#&Z0z1^i
z8Nh35g)?wO?ar7URpZNmGim_mJgdIW2QI4htc=WM^&5uchFW0<ZmNMBfZOV2y6-D>
zdo$o0wP+vkL|wz#W@{%70duv_vVg_fbDpLpS{{#BxweoGRA`Z@z!oji0obZ_Sppo;
z-m?G)weMR4?`SJ?>7SEY={N<%pE_+Eq2U3%{v$lFMcL}mlp6{#<Dnr>3!veD(ovC*
zdqD4~AEp6csaJSxzg55IMfJV<fVuUf8d?{4tPbb^{HhLe0m`&s=HP1W`$k9{xk8U-
zK`0Eql@1-@>k3T|%7#AE#__Pv(Z%K$wtOLK;Pjbai6q`Y55&nfz^~$y3BaGicOy`w
zUYiRnRJ-u-tyIHV+oT2|(sD7&xj+<r-e#}W_bDUcAHmx(`0OTVc-pJbPJ1|i*XJJ4
zZcEV4M_;_4Uc4y&KkjY0UhVswu<qII(4Zn}Jr8cTX-OpyPP1O@ZvG`#YH@roG(MT$
zYB`%x?Xr-*PrjZ6?V81lwOjj^(3diqUEL$*LkCvz4jlB1&K=xfB6P@c?q_Jqc<3<q
z&d}_HVbF2ybD=qdIc9w18os!5jWMW9c!c}V$nU=mI%()a=;WKB&?zH1_0;i<VnHgc
zp1x@ZbjD>aKeN?v=qy(nZGFNEtx&APO@z+@=V(l^xK#<v6>qHo=7}#50(=gbMk5xA
zp-6gsa1u)qTfAU~F9jBhXIyZJ_-!3fDpHY|MwzhkU@Q}E%K)4Bu`jS({C)sfA!<zl
z>|#8PE*BqF0TrV6OTa4e3%9;nRQdz!M8ihFdQpE5ut8ksrC{ACE^(zz;sKZ6EK-^R
zTg3pr^tOpZJha<I=jFf-aU~AeDPo!XmEzUKz;5yBL12&A=nd=@dQD)T$jJisi*s~O
zmAFF>9}-J=Ob&}R>w(wA8J^N3R^h-{92Hf>>mo25I4<rd0&j?MrNEnF28}r(UTP1#
zBPyMMlOms4@UA$@Nl%IQcsZRGtC{L&#Bg8WJ>eb!oD&CL0nUre6ySpRl&*YV)Z=rP
zgmsw@_)p=;wERd6<GLS<bt{2S#8M;({%$&exp!4;9t>O)i+R#M69tU#bunQMa6|0U
zfSV#s2fh%)=(StoA54_nqE|9-M+9=+FU7<J;GU?D(`4Ki-K{kEfyiW{ek1zQif@Ie
z1AHeungid92-^Kf>>myMAey=XKZ-eRfuBS>UO>MHl|z0NC#M3xi92-V@8b77;17|p
z4ER&zGP9qFa}33E5yE_&tzM4c{WC{>6ao~gAHNKgsB`xNi_}<Vbs4T(V3}G{2-wuf
zbYQvaPGeT6TNs0tYAH`gxjKd0u24T?&{wJPy@A#0W3IbK4e|oEsco1u+ttm7fJ!yR
z%JaWVozN52-D+YdV2}DP-w=CMY>=Oq{>e-CfO>csa8SL@^r%vQW<DQM$1xKQtNkiC
z6t`3KA|$UFb02odi^qE>gY5fb7ii4~4lhPkf5?7uhgn}-V#ZbVAK0q-h05QqnE#KD
zqH-l`6!*GJOpe9i<?^Em^890F!Ev#WaerG_>FRUhr_>kLcxLxSgU?q`X`L#NrB<WC
znNg?*KkfhxX~aX=xE~%dB3|hVjck+;jc&|WORUaZZQ5oZwD}>H<EQZ^Z~ZfGfVSxi
zUQFEMF7s!2Fy}232jLxrqvfl>YIWOgV2%2ej#;ZtAI77+PBk)t^=cn^F{qv#x?A-N
z2KK05ZwL0OKib+P23R*Tes8K#OMr6i6+hsh=6&#mXPtBD6^|(qP~URQDff9?>j&2x
zr?m$`zz5oMM(sl_wgkAWsZqdfEx!+NS8MPx@Qv2t72u(Eg&FvRW~l|t*Na`5EhTy#
zX2cTx@N8hI{<95uRZklNl<Kv39Lw|`-1;*8=LEo}U*l<Bu4gm`R_OhBj92QbxjVbw
zg|~INK82H2=$lG`Rr-b)V6|Sg6<DJe>;l&6f$*c%Sf`JVMs>Zule2Bm8^i${_0gfg
zCVhA@uvuTtEd9vfS2~T44M#S9VgwZcpBhh+fXl{)UceQjgub|H_|mP{jEhZx&y2!Z
zz;z>#xM7@N#6CAxwF9gVjHZjgN5*-E_^IK_Oqp%2WZ(+Ty%T_2=A&T>h(9r(vmy4!
zNzk~sebDBIx%-wsjDxoNv;nkDX(MRcTRoud9GGV97eqok&Tj!t%yxq&1u%1a_K?5K
z?)6JUR0dBO4IR=6IcJPrL|<eFRYG$e8S4oybW7eJJoJ-V=+LS2xNt#7ULVtrbJCgK
zEun?NXFX6Xa+v>f#YyJgd=b(KC=nNVuPqX%Is=Qvz!g?-shG=nzADl-0%f9N3}6!z
zx#un7tRt{h?3oU16I-_d+eH%HvqM~32vmx>JAqvyp0VC70+NBfqC*yNRSf6WzY_0v
z0lpSKblg2LZxwJ~e6fl7_dxgzNA(-gnST3LeApBCUOZ+z9*MvMz!TA$cRl{9d<ZC2
z-(%$0tHsQ??dsb@ffMRO`s0r3I~Mp_)i(k6)Wpfa_v+gtfye3~#^eumY;)jG^&HH$
z8bw-#2dc%|F`oHF+M?b-nf5!AWV7~gHE>3I%21!xQZj%Kw6n3mMQs%Q{Gqmd8E{?e
zIS;s@#m)r2*4lLgo@$F2spr~pX5$=vc732w@16$~>q-t_U8>LKq|5X_2LdbgON@Vo
z{!TWqR<H5~*6YtY0w?t>+H^+mH3B%VXYpg)2m0@f!H0VNEx@OGuMpsxUP?dT)QcMe
zclGa>SzqZr`T$?+k7?6A{V1)!KU6P12tLy<GdZ8@p+uQ6tqEW^Lg~v@#;Zxd8Y7=M
zyTRzkh-@-Sm{8k{)f}?Z@U{TEj1x_PeTFaBJz%V~g(nB3bf;g>8{K$vJ}`#N2QC^e
zypKLM7PJDc7*Cyn>xO?D;0t3>8F0&}(H*#Lj6kgA*>jg~9ghjNmC0e&D)`Wh?v8XY
zV@x+_>{DN8oE_)QY&v5rwAnN4&}=>oiD0&vwI3RP6Q-Lj^H)GyofrjeeFt`!Z61X}
z+un77woAqq%=QI%S(*twy`UX(yrCVlkojifPDg0cGAoztRM_u@X#w~O6F!eO<EgDD
z&8$BG3({<}z7HNTLTabH7#r2c9reWf3`Vchc4)swIHGckYKy}txQca9pOJfCv<@!f
z86UC;<{3lRaE)QsyI9&7egQ*_v^7hhBZ_!l(%mbdBWt8VGkoakQ5Tseqc8AKX8yuN
z$f|-_#<-abRqnn1&<V$xQ8RkBhR&R8LT5ec1)VKK2ryUJd0-ZaC$ytXjG3m`+H~``
zzLt&ZR?&_xiXCDpPf?|KgEzx2QQHaFEk-jD_KI7yXP-!?5&OmPIN+!-ngKuQXL)=c
z>u)Uw%8h8+bJ*C2fZ!Hy(-*jA#Av{0#tPbZ-FVpsl$ryq^m(}%h@sMXO&%e`%%(?h
z8<@?04}><)gcW9s#u#D7M=%3go(qPyIyD~Jx}*`bO=$yY+en1NZ0CgSn(g=GK@&V+
zy4j%-TRK*5h9+vo(4;;Kpq=owN2_9X{+4OdMV$yu=C>Qo?)+k-+2b}MYW94X3Vr#9
zsnC?0OtfAP#zA`@s|W4F?>d@&H^K|%EBu<H*{>mdVD>-683w%56*`b#aWn@-<I}o1
z*oK#oIpj_xbm&<G)z2JOum}~qSVJSr#b8=iA;#DqycB4?2R9h*7Yd;sOT3|8E3r}O
zsD@85pE2V17--fED>QdiC3Nbyu+f+`(f`Fb^ZYK<YyJk;7<FFX0u8>o58A|iCba3M
zIB4sMHK0i$u-QmG!QhSN|1e;<6%4}k$~YWsO*v+<E$`kUKB_}*Zgy6BT7K5}oV=($
zeS5^kCQcfW(KV@4WLj=+RO0xY{EVFZyr@p;*;%=H8Bw{}lSXG@q-}ifPC?_+(#PjD
zZ<-nt$$w*`W8<P*#>B-mk8K{6KYn~RzM%VZorJ8M^z2C^GnBt~CC`+aiRt0tQ86)*
zagi~9|6&Q)duCS7-@mPZzd1ynDZVZLes@{_Pi&&nCXQ>8Gd?GyNk-a;tf>6VN#jOD
zO>U9VWL)^D+^Ed7i6f&%WaZ~6QLp4>Ow5Z)Pn(!MJ})Y1eEOtuG823E@0%Qzmz$QJ
zk(!^8HZCf$L(e9Ocq+BW_>q&cGgAAEAC*5PZDK}L_pA|lQF-}kP146tv^D4*__sT<
zrtML0mxTYV-8SFeLA{j7NSr-vqH9h%_wc{=MpZ?hgOMJooxAsqiye@f)U``$YEVqG
zs;-5zy*mGIEsjdc7%^#d)wSg_602-iGMZUh#>6&>X&xQD(oJ|Dso^H}47Bn$k}BSD
zpObj`I^##h%QKjCR}}t6QpKCS59x#dRfhCalsRNAMJXro{y0e1#rMxiT-jffxI|UF
zRaCr30!duG@no2yq>$lCEoCeV_yko>Mk`7c8LKEhM+Rn!F0LZpzHyRxS)|y1ATsS8
zCIeILWyAveEu!2WGX>aSp982n!t5VT5k1xYVfOk{!MDTg6Uj?q_LJlnVRo+q@KKn3
z1Sk~yfdV}3VHeW?KYK4C!M>5es>E=6hv`7By==Oef+3DGu+G~}?Sp3E`Qi4RsEPsh
z-`KjNv%T9)%zmY_eU)Ug{Q-F|+1_dvMyJ>p&cbNLew7HahgpGSdjX){d)a>8iZRJ{
z|Ji7rYR@7R`!OQa?l=cXunz>({eA6~bGVtl_TNGDb}dA2uDt?Kcf4YMP>9}3gY2z}
zIBJl+g#2}o{Thf#!iq6^s=a_%U_S?_zYez7nv2eId)8d8FvR{ks{`zg^Dt<(eIQY4
z-wCMuN7#R#ht5oU*ZFdW3ZmS8A5f2`+gmN*>go0p5Zk%BfX$=qjTh3GQTAyd9DZ)0
z2p1FVj~9vtn909HgcwipR-9_@RDzaC_AIohZ@Ai*m54^dVm~IU9`@U)s*gPEPK(f-
XVvkuQLj01mgp#b|CHmqY@q+&a{lOFQ

delta 14756
zcmch82UL~Uw)MBa#-W1(f}j*dR0OFC_O2LvFW5yas0i50Q31gk;HU@ey<zW(CD9m@
zm{@XSY%yv~j3q^lF~+FzpL65QxOwmW|9j((@%}r)oNKS$)?RDvwGVi1@lx~AQnMgP
z+}jiE>(ID#g`xx>FRv)SSrx@a`TPGubz{VsEJbV5Tv61|D>Ou}tM1Tdr=nEzu&Aqr
zhmUQNLukOYXy`3^?Fot!7BvJzw+XEU##*XB?6U72hnvDWtQ4&p6(*_}C`@ChqG&yJ
zsKR~cNtNYVBviL*KvmawB~_}idJj~hCRB-jyQRwEJQmliZ$s7I_XDbQBWo;FJE-dD
zcS))o25#ZRPEe)#j)57PZ}TiPM)*Btzr|rlF?4+zKsBclEz)|9gPdQPrf843)SAk)
zK?_WUye^QNYyE6}oT~K5SOm?PKrW=ModNlhpWNYSHOMzAN_}W8$lv?Ha7DW@6Y{-^
zbexvjUr`*r%8lY&N4Uq)xBLvsM~B$Ha0>CO2^$@wyv|T%sR}uv{MVG%+1#9~xLPxz
zY44S#L9@Wt$hpFxfcc8z<l|?drV&o;<nQN2Ie8l7fQmtsuVPE5V82?FAH_lrshB|d
zL?GlazZR4atcP5^VkgR}t02c#mZtZy9dxb|x^y};tplZ|zB}YLLGmz5xO?Y7dH7wn
zKb<RxP@9iSWXn4{6s4-6C~^3))GMbb;&&`8kRXaue%=yA$sW8-QCgw5$A2~A2|A}u
zx6O44FmoamC8fWu)TLVclkF8{KtYb89K@W{f6Xgr`RB?m9MNZMl%iZg@3(&&p~%i|
z&G#wFQ*;<M4>vE9<2!7(CAbDivCSY`AJ+gYwas3_AAL<l8HS&-69jp~c)3c0Q|O$8
zj_kiWd;Zl~=N3AbpkvKnofTkV+05uk8x&<PIu8G{Q*n6+RV^ok?hJHano9XM`|(_5
zy<r|Ui(7zrXbW`<cHr<zU$?Tgck?$X`!u(WajOtY(X;&mMH%U!DC6-{X0)^`f}O&}
zDa5wT&ELz&SCmK(*9775V2+}EjG_8X+f}!Knr=uv*ZM+R36;m-?r5|S<=FoiKjKFQ
zkf3->w*|U~c~6_FC|*38S)D-1BiPp0JxDz@z&72zn)h3&7?8!jTmmJJPi=?Yg9a{Y
zi|Wu{$V#GxH&Yb1NH<<&t&0cbEGgHvxUCm6Iw*>-qoPFVZkx1MSRlB6nxbrWDW$lx
zjiPKR&u+zd+#C}(I50sK!)i<L2p6+$Lp_51w6%)jUd6u|MtP6MRrQT~7ozb?C)+9y
zAOC|mvU^=;PO}*Cs7~&6z1VOuqHO0q5~|<o0aYW%vSk~fKDalQ4c*X_&}bqX7Gtih
zwx{2qsR>Xumntt~egqmVWW(3kj3jn%DH{RCUiP$-jUdH4Xau&-oZtkTy7fXwmM3M!
zn1_4nKHlWcx?-{>d4FWv>X{&ZwB7cMiT_7ubgy-a!&!oi#e30MU+HJm?W)G2I5aj^
z@^n>{>c-VVG`6_Lp;60NYfCB@C1%;ClnZtD%R|Ru>90=4rBvI_a=z9_{h&MPRvl|5
z8}UdP_Yb6%LlvJ*a80{Z@hNuDo!g;jlqmDHei?PZJzY4@z!tiGj|WW`UTj(Pezjz)
zGFvYCZmjE`AuK$Shu$p%tt{cl-0{+rH{#83pCWv0NHyQU0i)9u_i3WsRX0Tm(AVT+
z=nUa>AFUvLpe?PufB5)T(B+g(ucde2iPjuZ{%4Gc(pw`J-1CIT6SU&=&bGbf>x%WZ
z2jvgc>bng+uPRQ3hs_Ka<&%zb;2SJHrt!xIqca2<kA|XevVH31uYQ|hyXRGD*v|zp
z`7Kci3+l&ss1Bk$(@4>~vemK78M=Oy?(S69XVFIwL#wm!;xre<<OH8rNWo6s#V1_p
zy@BZORdxnNKh?uF%DZ}x?IWN}78Z^O(7m$J>Q}aWRXwskTK$ELP<8!RrsIIJR+JtX
zjn=@jR)XHFH(G<rT21uFX}0^`J;X&@6Q7D=g{`kol&Ei8;1gKc)<jXtHS?e=w97Lg
zCwZP?Jm#Uq`=;AI@#!f-Y{3=6#dKTy3ai!U*|wi6R2E4#SKq*-6y#aC-%MUxZ%>ql
z?U<uD9Dz~gZX1ko_+Q#87KHa(sq}4tz`by6%|2P+Jl5OB`^Hp1jJxy9od4Gp-z8Z7
zGjr`f6@q!9I8?Nq_pR!B5I#C(;f4<PCl~p7iFP(`zswq<tD-c<TcZ}XbL)n8e?@gZ
zI%;7Pw;-hNiaOC)K`m7L9^3Z#4GjP1XsvLCRSwUV!?nT!s~n&GFXJ0jY%7E<uVM{>
zxfMhG|2bDJ%yJ$xezcNOqim<)Zt=Fq75znk&DH<!qcXEHlmRt)Vzn^cZLO`ne<)VW
z^pE~eYjvykv9vlJYrXd$R^eV9s_mBj8R&oQA6n}_+R`SpSoUY4Us2lBxu<i_G=4I>
zX6qE-k8RTe>HyaV)CPVbQL9u1a#*E*H789TEv#ypIXqfsrGGtCS${~?GIK_vf8T%6
zU#Uu&Iit}3<X`%=!u?ifRF)7vt6Jd}E5Z_6nNI0lIb4W+xs@|@(bx7oq+!*kC`DQg
zZ&U`bqm$uu9-lfi7mHygWkay|7(RKnK2>6@HFo1x>AI#FWn&{<4Y!^hFvP=8Ds;`W
zqM<$;3XSexrg@_;A5bP3-rj}i^-<sG{VExHLJO?=x6!(()$}whCAi<3v%BHEEDC~a
zfX%t8zc^tFs~RKHZGEZ+iAdYjs^MaUZ8Ol%_C?i5>tR@9C@uYnMPrDy@xmBN^$=pC
z1H=ali8qnJ=-p53fQoA<Ie3u`rK$&U#4_TcIYbR9Zz!L_LPNP5Pn?2JwuZ6;NpC1?
z<Z5%bQtoQS2SG#0OCkDHAbtze4Q26cVmY}@OB5MH!HWW1I-Zz`kAs*znYctQ-Cd3!
zkxtD|Cb6I{aj9InK7Ii(l#TEXR?Z?GmnMc4;dcux(UkZqhd36mv!NtPQ!ZDcTuU19
zt3i1N9z;X=P@dIOdZM`(HIug!Z@@-F>AQ~jog5Q0nsS=-Xwy2Bzm%(Wl-^z9saT;J
zikvZ&r^&>{<%uQIjfZPcZd5=V=182hkEqI#OM)r?I*_=u74cvOabO$b+LpwEHN+Xx
zD+6%%u$m0_t&Nm3hbxNJP%N$4cqU_WdkW=c@*LT6%Z6jANnJpEiO0%Nj$)djY>^?@
zD9>6Xw>&(Z`t5lV6NxJa6aTT2xJr619u?0}7NJfe+|*c=bA#B}JBe6VF5xLpQ?C{^
zo%#^@A<t0!Wv)Dbi}C?!+}XyI1Ehy6`0xi0$++&1rF_qaxITtB_ibXf^ju0q${S>|
zTQ_%PBTY`2BLmTTCN*El<%T6teph;ET#(ck6JJXQPL~;QUS`JYdepbW?=Ob(T;7YG
z@=gu2Q#09(xKbXbiu6jU%!$g@^6aQQmsr0Ov7U_Cv<S+1()J26#lD+GjhBp{a~$O~
zc`r7GQT}!xF-RpQ;=_cY9G*wqEYqzz9xX%ZCXX>sdhwX_#Qudc{}-9;Hd2YpClGIz
z5SMl#HVq{<Y((^wuKRT}<+F184bnqC9@JEjnvZHweoK1mk~HG3yjgvEQC~|C*DfPA
zjga}jO4=^AQPtUr_@piIP)p)58T*f9IMS9<(_%HzS8ns6OelYOfD5wJyf5!XLSv3u
zERDFSP+qW>SR~W=iVVl$O)~%6^<;<V3}Q|e@mY1^1#}zAMOm$O%AicILd^lWbhI3E
zUM}j}nfk&8#2(VIP9rE++d^DAjd*qkF)@VLYK7Eu1*@`NmYQxdiEhXc6xLyPjWl9d
zW#S^4A9n&NZ`?)vIfGaveKT@B<#1PG!zRRZnFqaP;6fHt<F6ABk0jodJ~%ByY~3!;
z-Ad-<^<nH@E?r%99pwjGiGwE*Pe?!2=uLUHGjW7Gal8!58krLw@_cdS*xS1)@pD03
zAunzHQp)ehtlI8FxxQ7}zFVHM-72cu4k0?rSQbjXF_4;V(wXgL;zTT`W|-WvM8>jk
z6g72c6VqA~kIH0>X-2u6-12@S%HBJP^<{8d)UdMgyPWn;KgxGxmX@nVxp=bdmDh5K
zOrrL3x##n#|1p<XE0SoRLQI$0lNCexk(_&fH|2O~P_-G9-DIE_$yrz0$ovnH`F}Q(
z-S=h8Y}gI8TBg+u>5rST8rGIurbw4glYuzimm?dtC!Xm*^pS@-Efe;ryslUV`j>Ln
z?Ig<g#}HpTDoUcEbeHZ`WSuIJ+53x}<|U{7EbsT1iJY)SjvOl!D%VysqLQ_j4AUr?
z;V-9iOp|b84PRn%3UQT;bZi*qw`9g_mO<|!cM$`qe*{wuWq|b1B<bC-Qfl(0Q|`(r
zJ#S7;u^d0MF6Fw`!K5Bdh_z}GwG86tJ%}shS+zNoM@qK`I#9OGCAN^;yuX%mpfqU2
z2Fjad$ezjU*)C07FXy(BbJIgOCOVW@b(FL#Q|8K#=~Q)=KDa02J?1THqNLB>l~?Xk
zIcl8d5hr>Qm&sX~O(_@4q<$=OXk=q*ddL%ZmbvwdOn}@}>OG}L>y>3s7~+JDWi||v
zSM;o0C|`Qwwag3^No^`wa=D?%5>wd_NNfyGm`dAW#G@;@&ZnIy+fZXnWhXMpRMyR+
z-Whs4itv!BEQz4p5P`s_hi&<6^jye}V@oMdleu!XfSSk()I@F~4wd<oCr=hF<toxQ
z?YD8Hmpnkyevb5#e#%FHOeJ@moQq;;Dlg!66MvZ@_C)nGtx5ng*;I}!B7Pggp&lD4
zd*B9{N^uk7P-qNgA+CX;T!qF^hG@iD(g%}e@7FT%`8O~_StmDcE^|n&#})GC5HIW|
zPQyJil^LUn*1SB@Wtr8-rF&1vG#Mic?NWKMZ_0F=SaxK^sD5rd=G3~91B^II^CJ(m
z0oLvYhni8x;Aq&O7=b4Wfg!zUMrf-_z)0J0V9dojz&dwF0IkhSb3v`Tt^xL%&umRT
z!-)5*2)m7xPD#LFkrRRGpR=Zn3*QQy^m-C-@@X4z#*d?bx#A@=>uvEak5VB1<lqwV
zlLfS1{89x}D&A`c+9#%T1idS2Z)W_Dh(lI1kBYvu@R+#a2l_}vAmNO2;u*t#N&GYc
zbXj~+3i?hwr-#<4i<*J9sJpnuezhWN^8wYPCFr0!u?y&s`l1B%zIr|sbVCha2D+)9
zWsFL+&zLFJW!e-U@N%tAJZOV<rWI(TmdW^T(gtFTS*n#R2JO~<3WoBW7Cj7fUUPK=
zUC=J|0bSH$xagPKzHHDXEs4JUQ9I7NUZfAAh1>P<EKa-h<1}=i-nu+!e-r)86!1aa
z9Z69ZweRf^s(AEx)BcBUtbpRG{#pfnqu(6_`dQz^13uKfZPQ~ytgm^LCB`9K5Tn>A
zaRDtizT5&@WgJZhePUc04!U3jP6b^tVmE@mHaw6>#y7?cI{A(f$C%zXp5opaKN-GA
zK=YAtARMhC^F$D6l^M7cw80F03$)q%g>`6$*&rYfyw5x}7<ANpItO&p96AK_p&4qc
z7aL;jorT5=GgAlsX?9%?%5hL}1B?QPJ}fp%9fl7Cl{g%n1zO=ypXP3K7{)uj#ld?M
zsMO&m?cC#V(gU>LVJ4NII7~+2Fg|lQ$6e1m9Hf)3IE2yauN+z@f^IlmwzdU-<IuDS
z^qoTzt-tHAgvWj2u#Fl1n?p3S;H5)dZ_sSZaqg6Bxk<m~Tbj_q`IcSNK#MHdC>6$H
z%N*|Xj^#p4(1(^|%!137588mPSu$}cjc+aUnSJ*yTZ)<B4=qa(V&fM}Ee7zZC55N|
z-O_`>{nPSA0%(?FM_#TR$1Afzd5*8^fNYNSxy4pTdnRbR<9BO7M;skk8BRDRjsl%>
zywMnR)^Y0|&;`dwwD$|gYmT7nj+Ns18R3rOaXR4#$84Vdv7;N^_N(KSSkN=aG!yiP
zV=q_GD@Q9+a;DRZ)u3#roC%;gPW3ZD*PWm8df#@Q)eUsV`Kz9wd(OT*{SVF+#({oz
zj^7S?>^#35DBGnE%8}KW=MuLTO}onlC(v@2x{Tp!m$P)#dY4&@!FHFVDxlpif(f|a
z<)bLjVV5iQKu27Tq1qWIUG~t2AG_Ra4!YoSpYgrwa+E`Ex-_Eow_V0D6YjV)<<j?D
zF7*Rh^Ig}`vkP23yMhW__e6pgyAEPKDs~;qIIVEqxfis@wUGhZ?^>4y?2zjd9_<6y
zyAh!KuD6-gPhBIp#S7QATszn8=VDO4+Z~3f(Cr3NPhRA(Y&yKUuZ`!gnK%NCZ1I}@
z&JoXPYOe6k1<ery=-NDy%O^fxbmASGD=dpZ^Tf~^p!q^U@i&(XR(s=s_<<Mwp!lH_
zbVv-E4mvDaCxhM*l`4bY6+;-cBf=Z=jH6c3gNb=e1f%2{$Av-ny(fNRp?F_(O$D70
zA6EmN6q}lXJ`fpOK&M3IBG9KIsus4tEBMS9IcgSzpR3-ofaa(t!$5gzo5`Sj^^Zc(
zTy+o+F;5+{5Hw%4uHa!7sBP+k7OKJNphfBvhV5<jA+KD4+8cf|3e`nitw?Q);G3(}
zm#sk;Rr%D-(Y|VdzI-hhQ8x=UzIMh^Z6Im6*2fLBTN{Xw(EFyIxDA3a9`>82^>P6k
z4*OHyghtQkgtnQrgIc2t&~l;<&@l-2NCq$X)<g)^Cm?ucwpbB|MvkZh^UZuw0nR{x
zsv@DydEzS1JztDO5X@DgWEEPgMODl*o{7zj=qu6CIt!eumdcQ--58-I>b32l64jk`
zWVL#&GiaAu&=T~XdOQpCsoEZ9OLN?Z^J-LV$DjlsXTH^roe6AsjX~==mPKUrk4=CJ
zL@AxTNnGy>Ix4<liMO5;vj@YzU&U{TwOr9@IydxK<Og+l!$4rIxnqD4{3kFoGOaxR
z!djdELT*OwLMoZjW6A+zhHk*D*rBW;ai@5d<JYVN)|t=ruG^c*nlNw}FmVP#XViOd
zKCrnpodvC}N$gUC9sOeG0*5c(4IKBi18`C<Q+1YD&r{@!W<5bRF@UGEi!U=k>qH~^
zYKKrFK?g<Ejj-sjkjB3wr1kF#Y5ox*?LR8y0geeP%{EU8d6EwVk5cA@gS5iCJtN`w
zJMXW5DPQMcN17cvn-?q0)(#l44w+#@Z{cBMukQgS4r2B+Y}pjp`2DWH77jWvX$B9_
z;ZugZ>n-T96Y6h;3M?I!+EZQSFnwR+hdf~XFb;2At{E_CF7IX6ajZNuMTf<pSt5dw
zpDk81V~fQ=mZK6;$qHH~`Y^xNiOF1ay*SVdv_U+W3EC+}@;>bnIXyseyTuMJb6EI9
zfZh?=a2<-omoq@8#0N>B4@I{FpwpsW4(Ouru!;I1*5A42Z{m~Hpl2eV@%>!{XM^Ub
z<M_<vsejNj`D!!djj>b>?gz4~pM`;n)mY~7CN;$!v{`l73fiK+<j8|+i8JVs+Kw?j
ztVR}sPOF|=^CR_LPB^bture~2)o&P%uhqBhpc`uWHK5z-S-S6gbxAzv2X*o;&~NGr
zt~OKKzaNyVEgk_{pdIENSg6(FMK9JSazcrAw?Alu7RlV(s5NAv+M|8UlD1d-x<2TH
z)-j!KKB*;*mQhrU$_*T$2=`?9ujPRw$}DpDi3jrkmG>^}Aj?7c13D^lXM5nc>ij{V
z@6~g>wm+&5-9Qi3^~|kb)arqtr>bXD(C=y=7f_*gqakRy_OKcfNAA!*J_thJWkZ02
zeO!S<u8so!srBWiv-D@{-q><We1;-telO~=0zD8@`CR`l7L5bF6fSE)+3JN{&|I}4
zFCQYt);jenA}u$wd{PO5_d)hreO@sVeid0ALyut>BfRI^z?SQ|e$s0XVB73ByT5s$
z-aHilgSsvE3%JPz1CMP622Cagd+@k%Gq>^L#J6U5o$t6)-90;j34-2AOk`ABH=71*
zv!n$uX#@*v+Xy@l##_UgUF|~hfW6aDz>GeB(z$)F(-X;Cd7gfbV}boYZV60#&b%G{
zJ2hjxSZ&5uMNzdH>BpHv;~td<X0_i09N%>=aKer1z=@T(^rW$j;^YCedTKFi^t8*|
ze)^LEz!@5iw(ep<n=KY^0A-6$XiSc{%ttC$99ROHBT9OM@<ePpXs+mrq{jy*k+UAn
z`J%@n&;oIY8!i+NSAhzIFEZ086ytd@iiBPSvWe1epvB_R9?%l;1t-`=3XLunpX>vb
z2<Nvz%f#+hpygs49sy&Os9FuQTKMh&tr1Jwf~;%BY3{U6+~W4@MWZ;-M&UUHv`K6$
z1Z@@#7K65k)3KnfB8IuYP2?^BZ5N;I1?>=Py+AvKUIDaAgwdzF#q5EgePYE((0<Ws
z5a@s?S`9iV_Vbn=vWoW^ufrmZA$eCghl7rYb<IIX#gGEfF%eH=jtjjp=!Dqj1Ue}O
zGYdWt<GAQ4F^f0!Ls7_7KP?9OfIb$lxY#FRWOvXR5!?y%srZbp{7hV<X%~dG$Q%5*
zc+J3nAu4d+i(>Io(3c_y34-5EJ(+t~MRH%zHPMpxekCR|zSl+SEYR1YR0G`*gLKd>
z(T!gFMts0Txh<U9fW8&wx$k!(yb0)@2r)qSMKdc6ejtLGmOqHLyc|CY!8HF#{7DZz
z6n8p;9*GgDpvNN44fKns#|rX9JZlGfCXR5(?_%mC&~veZuKYvn%LKg;eVH>a#V{W5
zPcfUJcr7X|0nJoDtYrnyQXhqZW~&Ri%sh4KZqR(SI<vYE<rY+=&YTUhsdop17ONi*
z11(XD7=xv1K_IAD9nE8xsEg^@W$NS3pylch+;@c<R1UOBjbYAgR!jDSwyBO*-v3gy
zW(PF4t1s#29qK#FK|56(ke`>{O91Ur$Mgs7RnIV@`_x~V&->NU%!C7KyAlpXQH+|5
z<Tayj!VXz@yaqEld`epbD?D&`Gpg)E_L~}JeN)7YtLj-C)x4$huPf&N<D;nD$r{SD
z7Kx!T7`#}1G(nzUWELC|R>u8(kw8~}BDN2BV~uBMHz>SU1EqDUK$cpKDpvY3bZ1jw
zSO70!O?ON&YPlr=BX2T_Q9*oKVsz$eT+A+Do&A&(rm&LN-!T!`uy_8Oh1=g@{tUd4
z0xT3;;2ngc_S>N4>Wb~473x7cW~Ca}pI3R6dYrknT1}FLL3QBJ?W%7mXovdsX3$Rc
zo~=Q1f2*DGJEn#%1Ql!DeL;IQr@e1H>pYBJ@kpr!^yxhOjX6iO9&o+!q4ppMbWVHC
zsQp8$J`Z$RdlU(}twnSN-O;Wy6MoSCpr?M;&g}#})+`l4d3ug3vt^#{!i-p`m(Bz&
z(jVABZ|fD4K?S-8uVbNZ(xpZEjwT?Reu1}nvEH>NXo>F5YrIrn&ePfThOE}b`e-gz
zq8GE?EYlZ7gO=-CH-c8^V@p9R_44qe)mWwXi$Zg?Zs%%ibkA7OT0ONoXr1082ee+F
z%PjrE;8!}0i^l70(3i&5NuW!{E++Y9qjzV}6=NQKan*34Tdx_%B0ygm^=E*t8<(bo
zzBcwVVmFPhjX>51M$P%)N5&b3_?2<GKWL`8fPtHBrj7%BV{U~~W>|DF6)~mbfw47q
z0qcz6=@Yk&2G+Y&1=ygV8nEHA_P|E3Sfd(GU`U#cuM2FR<_2tWk<sa3%0FgzepVHY
zzEMn><od`tW7K5&BF$$TFx`={9`^_Cg^~G!mwtR*9XP2mH=g{0<zvbbE;?OJ1kM)D
zt3f#;jQO7{4m0=i#4UPhp2){t#LGCn6=;FzxWo!xB&IT+Z;PI5L4~5rNRUlr@XQ;;
zM~<M4V%SvBCb4`IXtStC_u%=O3)&{8ZUvQ!NXB}*xY!!BQ~ZH!MUC&kqkk`Qsk|%B
zWr6OAY0E(O#ie!3zX#$RZ|4u975(<3nBM{PP&{Qk9*OdMK);D-`Vqe>?*kR6vnGR9
zt2xZL&FbWSpyTRh`r}*mJgvX0{=u`{Q(rPt57o&-K~L54jL8eNcOB46^*xwvHL|r5
z4>WVM4Bq+qT8l2ALhTWgWWDy?a?ok*2}Avn=9mIHryXD{&TGl^^FOqCMWE|ii#edL
zwIBH5>aO-I3G_;v&q%%2_Anb~=`%w>vvngAl%v1Hl(8<-6S-)SexNsKseYRAFVUx@
zfmZ7Kyg;k<L(M=Z^#Qc$wC==^pV33O(>eVSWAG2%cLV5>-Z>0(O;6&nZ|FHyL3i{`
zsi5z5lR0-+e@dI~={srt{eJqCz2HCf51E{=bstipF+2ifH@=}Sml<tZfL0h0tRZWR
zc8th6qj^ivCZpRZ&{o6C0xC7O$ANYkKHPVY(a{#(#=nz6zn(EP-kftrmpssU<3p}>
z(U?#Vbj5h(47zSOGyvT)W)*_IF+O_>bldPptmWNvm#>aTs%>eT8rC%U(2Q!f9~f;S
z`OTPDsQqT_LX>qgE@LAw{#TsPtkZ2Bux{3FV8TV1ZYGXg0<1T27_k0|?!X3*sskI|
zaRD}}gCm%YWAIp-O*)hVHXY*yY&HOyZ#LiR2y9Vg<(4h$_jqHP|EVFcF|bNaV6ZeZ
zBo!OVhb_b#Q;e`LJH8oPyQ@3e&DSv)osZaoJpyn=%O0?Z0}x!Ftps}a+4)A>w*gmA
zo)7bke)G6Tf9oo2Z45ktA;zGhg}}ktye~tH65!C!1_D!@>FQzmOq0}{Ho)P#nFu5H
z8Nkt_a84tAZBO91EN0ZS2K9l{b4}okU7dk5g$M)Xid<fp`C=FCC=^wuD7FS|{j6h|
zqZ`FD-n%Vg5pU5pv3CckR0KGIwu@9I!cMVl5NMYOpb@)8hgi^I@q`9E(U0-^Jk<{@
z1{E9kd9DM-E(8Qs{3)Gu&4|`OUm4l7@4C^_1}ZQ;twX`ZW+e=j&WqTJ3^U`>Q4P%a
zKPmz142KnF-I^F-CWJ5p5<dwA)|);SSbttMV1t4xz=n6b02?{sxMt&FnZPC<Fx_lg
zjhbd_)&rYA&jz+g$_KW@*B-5k*=i%xq&2_oXtv?E8_jn7Vx!sq3L<KD*o?YncHD+%
z%IsukqIF)6J8yP*Cm7h3-*q&*y&Vti&aXL|Ju1QnX3x=Fq1O}?5VJSG;%N4{k1JsI
zZHGt5O#VC)*l#9+>TC8Ni>J%9ixo7oSahakC8CP$!CRHAYvBgN{lsjb$3ib)xurO$
zbX3)Y{PaKgUNmq-ycL*UunjnABWyHgWca-qXTD#Gc7?qRLgn2XfT0(60V6(UO2rk#
z0_$g#2e!D?5;$NYlPT4O8R|B<4VG6f;9_e^fTL}3ySlZT*Gul&4ga-|jcGo9a7t2(
zmII<AqoX3D|E5b$PaB^)VoYYTt!c-Wp%X`piH+f~$f(GesF>KO_?Xz}_^3L`S!2hh
zWhM_EF{XAT{)w)Awg1)CD?3L<VxO}AZ2dd=)UQ1xJiK;vbYyH~wDP}suK%=iQAfxB
zzekO$ojE!4|LYkm{5uD<{x_L2C}VWQn6YD0B2oqo9+5m^%#gJ4LsOCw#pJRmCjWgv
z*6{J82PaRcn-VcPd{}z&@Ie_vk!)FXMD6aGDH)lyhYZR{n^?O=O6I7nvFWw5DvyoG
z8jjIp$BwBzacst@%=AG+QZQ&tL{>^>R;F!v=bHb{vHph_04Zsk)Wx;V|INDp*0><s
zoi3jL{`89bI(03M-1o<<8Ra|&3~1G^TWn0P0WFeR4;T;>9l!7R;%Utr{ClRs!Gp)A
z?n}HfEZ#3ZIx!+TF)q4BP+7==P!M9G>PE*LddF4l>TM0jL#yI#<NwJ+#m^Wr9?g8R
zyP~Wn<3&G6_Ewa$WM4)3j*Q=kUXbx_c;nSj0~Mt<8Kt@{8O1Y&jQ3+E86|f)xrU<b
zBZn&$m2(vE$>{|-N>O}J{nQvmnRG}D7p+}Ifjw!w=qR?>OF(wtNy5ec>v++^KAcjE
z36Ks`S`0}%vR|EmvA^4EOcWherKWw#MA1RD)U=-=`_{BqoCL03(>{`%P}BY{xlK*G
z(`3;>^s@J!jM>BOTS@8m=cHnL(i9N3CmpumCw**BoGK<_$eyX#$2Z=tPQ(1e_RiDL
zx!b-Lq$;iLzd)--wYE2#PEN8Hk((shZ-cR7^bCydWuHZwWdEGB#vW|N+$Npu8CHy0
zV?TkWxM263DTfXs&9v_!72Cxu47GH(cbSD{6S~{ifzkUIYFOBGHjU_EFPe?s>V56E
z$q9Y!G1=fweeJWsSmg6;jJ{wG&H>%Bj{~WllI<sR(D}&jnadse*$3yMx!b-6O>xC8
z=78?mJA+iq5c|40=zQP)nA%(Rrg@-8_Ck>AG1PuLkGl`G$K+$s8vCq##4vrX(CruV
zMLRVi)gCez9mDP8=8AA}(Y|u7sDial%oSnAz+T8k`%l!IvwO}HVXBv#z1}=gO$@XT
bl1)$hJT%odp7y;|Z?Rv68oP-3qQd_H05tWF

diff --git a/Debug/Libs/sta-core/src/debug/printing/printable_printf.cyclo b/Debug/Libs/sta-core/src/debug/printing/printable_printf.cyclo
index 6948625..3b8b34e 100644
--- a/Debug/Libs/sta-core/src/debug/printing/printable_printf.cyclo
+++ b/Debug/Libs/sta-core/src/debug/printing/printable_printf.cyclo
@@ -1,3 +1,3 @@
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/printing/printable.hpp:26:11:constexpr sta::Printable::Printable()	1
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/printing/printable.hpp:26:11:constexpr sta::Printable::Printable()	1
 ../Libs/sta-core/src/debug/printing/printable_printf.cpp:8:5:sta::PrintablePrintf::PrintablePrintf()	1
 ../Libs/sta-core/src/debug/printing/printable_printf.cpp:13:10:virtual void sta::PrintablePrintf::print(const char*, size_t)	3
diff --git a/Debug/Libs/sta-core/src/debug/printing/printable_printf.d b/Debug/Libs/sta-core/src/debug/printing/printable_printf.d
index 6e324cd..7eaf47c 100644
--- a/Debug/Libs/sta-core/src/debug/printing/printable_printf.d
+++ b/Debug/Libs/sta-core/src/debug/printing/printable_printf.d
@@ -1,10 +1,10 @@
 Libs/sta-core/src/debug/printing/printable_printf.o: \
  ../Libs/sta-core/src/debug/printing/printable_printf.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/printing/printable_printf.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/printing/printable.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/printing/printable_printf.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/printing/printable.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/printing/printable_printf.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/printing/printable.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/printing/printable_printf.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/printing/printable.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/debug/printing/printable_printf.o b/Debug/Libs/sta-core/src/debug/printing/printable_printf.o
index afa25b793c13f71bbc3ab72b41d0469c5b58aa89..9db813b891f4e464dfa3d794ef3568fed05f62a8 100644
GIT binary patch
delta 13145
zcmcI~cUV=&`tHnHYu4Ty_C`QZ=?bEt(v_kj2q>bW*kZ#1h=>gou*9+z8^r={bz@g7
zF~(S;Q4@_xOf;56Q%sCTjU~}ojwZ)g&as@|`wbq?@BDM`bD#Ufg!ldCn^`koowecF
zzf_4?Ridh~@-$+P{{zMG%p%5`EDL3<Wp|sm>gnmyfid-)hVhIs2hA{gEn`icjp};t
z+|ZVx26|P7KyTD~j%6%x%OEV>&easGH8z{Gw@O{bt>)E?8G;)|C|JjJ`(VZtFAb`e
zjZ&n__<akgqMAV!)2KhG6!B<1R3k|h=P_EU3@P-WTPalOjb@Na69FTkYJ~F*Jw2+V
z$`D-x)%7k=<uw`)D-^GkGz{`RcG0}iV6K2}Pz+S_eaIr^N*?4gUou5mRtkB8FWI0}
z4uxFnM~5pn6KsDI{{05bhU%0b?WDY21o;OKc|?x@$X7h2J|PJ5O%Hg)l;C2>zj;#N
zln!qoB5tmM@>vAb*r<Li$q}{@dVt58(a?mu%_YsBJs`){x09T0+n@(n&g4Ur?iQ*-
zbHw(w-Y_eBCS#@s9!F`78$337d7L4+asp&;&x<6l!HK3O9yduY2!rhJ`FE0Cy&*UE
zcu8{lGRQ%m4zzQ{639`$((+$yT?_$%>n1{z>L)d4Es(o3mcE>$(|h?z-`}=X85;5!
z+crZ7ZnNDoBsG2$d3wi%F&-@#YmXnDMy%D)<v7IR(9M=+jJDp`$k@*a)kPy?OR#1Y
zt@{}3bUKZhFXOm@nT(NY7v?_v_dGvIo5^|qfpzm|F?aFx{F&GDpT1c){{VB3{yon^
zo_aB6ducRS$sqrC5*TyU8S}x9G=MwfXlA0x-~uaSVVG$9dh&0yyPORF5>Ix=ME}>5
zf4-iKO-N)c9}`nwPxeNPc`fR`?(xLWZF5cDsdP-2g~J$o7Yjdny}0zh7x%nsXY4Fy
zFTP%pKvss*<Gg=^Hnv-)K<kapjAe#G<6&UT4?of$W+Hvg6l6LAy7vFpzw(nNM`vQP
z2POu-o~-keCMR@3eT~7yq}P*me$wRB!6=9_Ow<^dt<u3&+AzB|o3ZUse)#%{(f{#>
z9xE?H`oF~NrPnL|m&dfCs=5_p_c8mA*DIvQ(wUlyDU3Oya=h?Umo%E>5zGNWaj!rL
zZEA08=Gd(J;#H`{4!z+SR_4E6{T`Vk_j5nHfU&*qST+r_mH)jW0=u!W`|Ys!kW-wk
z#?jZhdM#tl83s#7L~{hv=A34jjV_m))d4xeSfmyeiAzu&%H_SO1R_r6P$#;#l#5*;
z7fZRd(Y%RQrZSdhVyum3-l~Q|Xw)}{vA4{ZU`?amNsMi)Pt#0PcQE70%?8;b!eZ-a
z4z_kems=Xh+fOM8WX#FmV+Ix*N&z05d~uw%6e|L}CP3j*f?KOm>)Q~;+i6fo*C&}d
z4jaQ_<hGg!8UuZdBb{LsKOr!d7&jW2ML-A*ylCL;IBW`wb-Zt~-8Oq#R|nvg(BA5R
zT_bv8O$QULVdDEd3=-r(6Wid3B~cEH!UZX|bd&?L7z#fvNpj#UHb-HQEC+648TPTH
z$U!4<v?&Ii<iJ~e8jL|_IcOZpTt*LvwMARVg8U536uXejL;~(TONqQwG-jYX-bJ_V
zw#4#C+igo^oAR!h-snJ=P-F4U1`Ia&c%zb<ibM3^7M~Ohf<(W$7;LlTVbDsr+A^HN
z`61hEr$FmC+%T4dGH@Bf7v*62z~MGF>nqkdVepB00iruV-0p|LQKx|zWQx1!HOptx
z@)69n`)XVwdHgpdR-4`ljmGP;t6hp^tdKkI!I_$N192$iZZt4zlY?mBi-9e$o^$m1
zQH&LHlOyKbw7cm3H+h4XIK5HyuyKXVGM&4s^%(Qk9#3OzCU>ZhL1XP3+n9PDK`(KG
z&8>U1l{OibJ)hTag!yo-5#CS>xU&xit+iC!j(SmiknL){7{slS^HSg5v*5!E&+Uk@
zVG9m+eINbYs0n{U)~4D{I5*>+Y!94$tTX1IR=V*nutz%&yL<4ug44!f(6i20O^Zc*
zGwNoH8XwA7FYZQ<n3;jf(^a6uGWzk`w9A$Oh-jV7Ompvv&gL?(ns#v{V}t4jW=-*D
zY%qUAPPu8npgc0Ukv8zw!Y4B}r0(dZ+O%lKhSoh4r1eE8ht&<jHA4tv!|MjITK`^*
zWz`K5wOh7pE<QZj_Ai$t-&wdE>Loc-5R~R6kkecq84;W=h+KVt+b~ymzQR`G8l2dm
zkg<OX<dN;f6dw&>#*^z9J0+E${YSYSreBfDAOE9lWxL|)%e`$cTr=^S9aP_!huEe9
z7uag*`=-7h#@J(>E|=rZuQyMEH`nDpKfP9ZO-6y-kjnbUko{+-Cp0IoLhpmN7xhDf
zuAu>+=rMSe)frj;C^r96Pye@qQ>8KEBwHW1fF}15*w2mRjPXGMW5<j%SxrmpRt4DX
zZoL}~LScUgr2|(s;y8R*^swTIMK<o<iZ8c?x_j~@TbjF1z2)5)+l_@RzK<(o6Ky5#
z;ZpZG=@OPew|nnC_c2;vGt`x;aiLpsAs96S=9wDdP{*e<7vbmF+m_<#-*f~VR)g!;
zO_)r=!3jsJW`odkQ3tBgO*C+~Rd_}^eT`gb_@^q)!ZF5n%G1+3ZZKB(G!n)yydXHx
zYZYr$M^B-&Uh3r^*}f3!FttwoYO<-SiRSIwU?Rw;P9?%_At-8li*PKp_4R7P8`>s$
z^|gM1%UZCW8wjU1Bus%Xf-UMn*h1>PaODYhZx-Q-G{PRWgg+plg8h+Bco0P`*u_f1
z2Dpy|JB1hvHVdZ<_B5O@pn|Z^YQkE%+j#3r8nnRML$K%gpe0z6JK<@(cLh5ziEx!X
zrW`FI*b+u~0xt)cf&rdI!Uc<#TUW@fl|0ha>VzLe5;_hc96XjV5REOEE_cXxK^6qt
zgvQ6#?FpaYoi5k_ysQMvm8N`;s0+4F8u6YW*_J^Vy^t_mMq)Z@Lg2G5VE`^6!EQ_A
z`pGq^BS>>pMzm%=$wN95rus1}D6=k5r~{bNm#~@K?k!w}u)P`KwNk<=^t50f$pcRJ
zA$h(p;d{7^1T#r}qkNLJB*G%}mSEM@gbig>4$mWbKq}#=6^vO0doYX!qZ0|AOd#A@
zNO*n&;k)w4d$}Z+%V^p0G8Qa$IN@pO<v1J3(elVoCX#$!R=}m!BsUvG_-HZVUKzP}
zJCf{A6=P*BrK$%?Rj~cz33KEYtEBCHgGlqN7vXM|@bCQyN6U2lD2+SamNXyB2%VFr
z2cS^}>l8-lB$L=Tlw@DIrn`*s1iaY<v%Voc+uwx-P2>Z$G7%ea*~1hWk0rQ^kTYp@
zxev+HWw|Xt00moKOSni7c9%u^kvGYcdJtC1o=Pq!*$oXS*wEgDAL6$Ll)P0gqF*Ki
zE1piM$OhA^NuC)@7%Oeha3wi<5@8#ezY1yYZh2%U*`l3r9|`t?6K0wSU(O&5ljZhZ
zJ(Bm!M5n(&@|eCdqx)ykAXz7zAlqZJY?Tbz%`Li-KF*)8B#yA74BaU^$u2R3U&#n<
zcOrR&G{{qyZHbJQ_e|1Xlbux{(`}L_x-OLU-(Pxpe<LkAB=3V_Y5VvT(v-_OD40re
zlq|gu%A{OHI3tj7QV8J%nSyKKB=3=ZF-BI#nsuZ(%m_=C5@wGi9E)_I{w>mvwLMAY
zQAGH7G-0OPI#AC3AS1L(CS_h@n*Gp?u!}VJpxpFq8fku(@$i!+)^|8*p35DM$x3P>
zTROsz^s^TMt;}B@vt3rHtMs7zFq-~0g3vFAFtY*SIawdAWk?GONRyFISRnf%a2d(J
zI1+lcBTQEad&$JjoKN!4a^=n}l6T1%SYu?4_esAm52T4MvI1hHy%rm3HcKyOjVJjB
z8K(}tNNz8~8!t0mDwDE8`pTt$x14EBbbG>`GT$#`La)grrpv1O)+)pJSRT{Yo0b+V
zA^dm{VXVw$8>x4fciie4(jSpVualSS7<pufY^?>^G+RE2@Ju2hiy>?kPk6d3VH0U|
zf0>BSR#-`8mnm?YO!9m3diiGt$q!}d*2z%slG&ZeNS`XVi<QsT%EEN1B7IIF;dNO(
zfwF1a$(<9{lin^33YC$*rjcgId|Cg~lW349>pxLGd`cetd;#en$%7xtcsvRsO|U#N
zNrrTqOvHjdq<_0J;lsMSUB=*xYSMfv+ZFaez965PpG@+z09pV3CK_bP@HQ<c`A2#1
z6ZsgPf~HMt!g_587t57V9ZB99MYzbBaJDqPp_F4}A<qjZ{VG{Wn)JJ{IcdUWIUmb}
zY-KxS1#EyVf_0PGN|2SDEswwR2I=cd6Z7O22jpe)l`Nw3`7}GRm~dqW!rA=^-;N|a
zBg;8T_QC{Nq&cHV?=MR@QO3affedDlwD+7&)5oS0R>))CmYsdeMjF56gfG?+wv&eL
zktSxzXP?Pur^w0=mg)1%rj<fEHZPClL_1-njNDn-3+=5km=z;wVzvum#tgy^GK^93
zv5fYlG0}Cwa>fu=XAw4+9{UuMYz!v+YA9ixjOZ14%y3uIjFeTfPx{?L?(;xKqH(IM
z;f5Lb`vp^FFejvv?BGMV9Ffr3@gamiFQ$!3(@3sB40QGlN=#?}C?Wm5E`(hXA)RfO
zrZkg@U^12iXOaF|8LipcnlN(?X$HB=`rp5TR4^B~R(2;&hwLM-2m>;$vta2#RxRo2
z_Xxqhm`QrG^kYyC$(Imzo%ysNywQ~K%m~7bvkB*PqNl9V#6Am1GY^$v)!9Rt*Oaa_
zeOwkxqDt~JZ(78qag}{ZGfw9Cnml-A57M|#p*4S^hIG~pU9RKzKth{5I25tbnI=~b
z?Lh14k5_nUWfA_g5ol$BGiVSLB3))8h~d?%xB8Yg4jG>d3>}yR42wrV_3&aO0Lz*1
zi=PYh-$|PXrg#BE>kS7+zK8%uKPEXjncV5@R}CCsr((^#+Zi|{uMIHwPwZ<IBfF2o
zpwO4HGr?gcaEeMd-c-|k;LPjUz<GSiFwhciq)n=LH(I=sCm2DS`0ys6cX%poy_aw5
z0{W0=P^};0Nz|K%`9L!8BmR3s&=))j^(M~nm+o}_58OTt!}EOPYS1ryCxvK(QWg)|
zrf@o9pVB)H^u7|70NSs-q+A_P#?o8h6J<BjF0LqRX!NsEN;z7oo~#9}Qp>0nR;xMT
zpv|gVB4~@6LFwJ9PQeo0`i^=De(Jl`E56X4QSC!OXVs6*ps!VXZ_qjQcZ&G;>e<Pl
zAJo|t+k5J9KhRRGJH>m4HiIswUD{(Zbg%Yz7tlU!MImUvc8}qoOxlui2mt|bT#moh
ze6pz>FKCw(&^2x5K+t`yEmi&l?K@ldV1Mg#a%H)2%mmelEJx64v9AWSPV~zIofOAX
zL0^lzbli{P=yK3yQ91^6O;n*1#IK_Fc+hPz7mX+WCYqxH_20#>%`sZ4A49*1b^2J!
z>Sld@3g|687G*Bp)hAis1n<?;2Z0XjX*4>jU!c)3eITk-oY33SC398Z>j1i`#|D7z
z>5s{y2m0yJpl5oZ270MGEd$LpM2rAc8BQ+*tuPc10If7waG!`Zh67Y-TMXMM$J-2R
z<s14P!%c)t>@m!!2ij-&o|^KcVcIOvmxd6s>8!y<2mWa2Pd@!*C~gh9V(3lITr+$$
z7xar^JB@A`R#Ge;8hRvy9vcQyjXXDWsSheO9;1Wi881=L%Zz*EC)7&gl?fOwHs;R;
zEi>lONgo*9>7--EnN%a^jd@9+i^f2-thix(UIDsoOe1<=EaITQ8}E>#kBo1U_fL)O
zT7X^}ui}~!vrVDYd2>zAC<qHoL6IPvX;w4pkhe`Y^D*3E`jr~_kg5Ad(5I%bY|!VX
zOKm}4nf|pN^tCCS%IQ1P3u>E7rmj@?znbF6?YpL5i2gA7Qq=x5^$!C*F}0w6`KQT+
z>ivbO8&%LOhcBu?a~zgX46XAWex+Poatw?GU3Yxa9rUZ?@ANkL&GDoGbk}ir9_YSf
z^F+`ej?q;9bIc3Jf-1~ymV)f&V<ymQ^Jyp0db5?{w8<PuIoM(D)flwfytx##&%CP@
z=%6_;8g$5NK0sA=)V!F2c*1O@i}Y)AKpW5nvx(OHY<@yraov1nD(F}9LkjS3=Cl1k
zWtIgL*@c!>)KgWK9TfFtmfM{`HI}QCpEZ`d8$f$3H>t(;S%xnF9kA@9ynbe}J`M)o
zw)7tidSv;6j(BEy+7~p>X$d`F=Jb>*u-eHrh=K8c^X3%lpf~3MTTB=ZoWo~Qyyx=w
zDA4nGJ=$hIzdj1IfTt3b@wH{3a_&G?R>2Phf-1T7H$+2U&FNhr-skCL<9<GqF3SUa
z#zfFT?o8Hvz>QQ&AM!aA_Cx#yMe#8IXGhRSd>#3Hg#U}K)sJ~K#p@G(U?}KQK8QN@
zDBnPHpYb-upwIcLxuDa$s})Y^w>Z6o#9ZZ0chEc~(g>QbWH$vZQ2Yu&Wl9x2QLgMH
zFDjJ6S)fX#l$=?pOo#+6QcjEnEmjgKYfF@dZlEfqocgF*(Gx*Sm3MG$>FbsCFk3&T
zd^^Pop08e}te2^yT4PkL(z{TsP}7K3tA|#BcB>oIy6EfLL&~@~4|8;V<Q&L`3kbf<
zjFy-NK|isEv`4xEjdvn|raovRxuVHSdLIUThurCN_{lJwkF*Vg{dyUXKroP@z@->f
z@Sn-=N<JS+(AV+9OE6l`=Tp+3@X6%q3%<1kG*79PDODO%f|e^eboxr=9tW*gs>zC7
zN_GP1V<jB!i_^;Q=mcp_J!@fONS^*Rz$U|}-ol)yu;a&4*7{Ua!;ibr4!Dq?qbP6X
zTl#<w^ZHZ=XSm}anD-~2IPBGq4z1}x=eMUr-Et=^(p$AdZRsJA6M&%&UGX>Mu>A4G
z__T2lJ6QDy545u$>A4(_MIB24w*G*6xy@&bfzh802gd9O1jhbJZ_l`^iNLlm=>?Mf
z7F}pv2N3qIB>j+b94totu?{$4Dcv4ZqC<eQc@;TP#%(=8Hhz%G(9UD5`QTcfkO_L1
z*J}aV&-cO>{UDdtf54^rA988`Aub&_%%uk(ak5%J%E=S`Gftk!usS>^E8KslHu6ZJ
z0`$5O2W--ltPXsJIup&kIs>gC2T>X#;xsuM)oueYZZj2CynlOOLMe4b%4rmzNLxt{
z_wXlY`>cgt9@TIm5+Ho`mjD9_DE7g@(|~P8k-rIM>bkT}9e{oI)6FxB@175u&D%5v
zm0I~5RI)X^NpH|f?m}@{#Z6RSwft+^brV080ou&_&}b)LMgHvK7khwq^Y>|+gS=HR
z=mYM!0`wujOdnT1=XuGXV|?@`&~ZMVF4}Xv2U+($AL9i2f!i)exLYl~AV217=)LfS
z|3tZd%H!$d(0t|kLeK)`DMhJFaY7M^70TJZAiFZQDX2!-G8(j1`G*DcmU5Fyd7IJ<
z1&I%H6%L>SO0WVts2rfk9#=|f&o7i7WWrfxi<Q!JUTI9dcv<OP4!WZJOvYSS9Ld_7
z%F%GpU8Qgx=&>@DcAKT{sRhkbzZ?!)sNSL0TBOdjgKE^x^uS7W`x~Im>J1&VMfIW1
z*`s>W_4c0HBnI@U`rAl4_ozB_#H);&PJ2V)w5lJl-Y=AG=iTTU;kpi?mN{=)S_mO~
zB^7r56=+3a>MGzAf6B?stqotTGn7!cynLd7%@5Oc(z0hWVCdP-z#B^afuNg;wV(og
zPnkmje4xBD5%hOuC0X%EiH-n0RW4EMRjW5*L95l-0k2L-ALawa;Ch3B*=On6&pDe7
ze5uZj1kKhyw!K<;l}BO={U*254R(j0B=4Vc_fhm2<T<x2#c+-?pI%($$|DW5Lh+(e
zt#Uu()gJEV^-wgZro4I7Bf|pcVSmwb>mpz$8`XE(_Ikjs-Tr;9-%T^dO`77u7yeJ$
z)$R1^h4<>kW0h|L825j85y-el_`zBcd6_aD)tG7_I;IaW?qlRmw0%Y=xA#YEMEoI&
zaEGl_O9|6k0F%~HK#~m<<CI&ez#h-DfW00xq5KbCGZdIPmC9|*5lYh7uU7&KkLbV&
zUxfmTwz>dIo~ghoj1Hb!NX`FdPug@wT5Dh_-&7womuqx=%;Seixqx>b398_Ws7ovP
z4occWK8517n4hqgftPR(KTtK#BCBk?Cq-&AzeBaUg<Hmfw({Spz2D*+*MPQh^9;~-
zeiY?~U(miO1?}LIDbPE){wC-G?@O-V<hK$*w|F82?l=CoO3-b-4k<z*yxX7rzsqZ>
zdhYQW3e5w4BpviS&!>bx=7Z;g$`lW3xGH4;Rq}e}%ch{Wl$O*dN0dT}#|`BeS$|8p
zLFM$D5;_+2Kv7169w}DJ$ungY70z?TLVM0p`_`ks63kVr$iqt2FAh|#P9+aFsT~)A
zj;k%nv@g_&nV>W3NXo@owObYFTlF4ob4mSdHR!V1a3biIx;h#3LXFoz|586C2WM+#
z6yH)UFCR2lE2dIftkq&qD}K+b>4o76&3ig%rB;{&TC08T3R<u2i3c6kS~Le8*ES9W
zozfmt5YA}Pl!I@zGs{3fXh*2_E^6QQ2VK#oHv#>s-KWaBseLmabW1xyHvOi}ChKo&
z&C)>qUuyTMIRB+35LJtarXagGPqADju6F>f5q&7m8$>N-q*i=Fk=-h~QnSA;ev1OV
zBmM{j?GmeVL3>1!?MRH5HGtxJO03BPoe>MEEY6B1l-+aUvo@d~#Tf_CC2^D5`l|S4
z4(OT)=>)nihG33*PxsHGN^E|rOWjzwX%vSBvacJiH@sR^_d)hmUsGFK>7{c)*{)!V
zs|x*n<Nwy>x;3A!rls5+dDfT7*FXO7P^Ln8h>xJR%O^aQLUWQYN1)}+;Bvh?1b27%
zCC5sz8-xJIp_KZ-ZS8^0eP;t(Jf$~6tM`(Cp}nat!%vn2Bi*TOTL;Ta<r2xUQ@nuf
zPE-8ici~=;8>g3hLl~Yi1X#^IsFPMH_i5+VO5hsM8f5?lX075#2dxWK^kLxj%5Iw6
zpd6>AI}~Ss(7VcBJ7}lU#x^a^%la1C`jPTaDzh53yaDJvHEToN!MfvR%8N67UKb6%
z!k*HcL#iV}FOI1{`GC%-f0{tws^h6D&#QM^fUc|iyMcaH1yU#Os&7#4@2khwg8oqT
zMxX^+yqUVNLTf{Xv`Bka3|g#(P{}UQZu9|FX;Vu;)!JBceW|vp9muBrSq56B)ieVw
z*S_uzTA@uR@9f$`YKj`|IBm94%d7^i(h@>ItF;Ka$<}D@)V6E2r#aMx>$Fa-FkG))
zqTM!VzfhxZ)E-hd)N0FUw@umy6rS(IUKA86IEu>advSR@=m)WfI_11@?h5)*tfW|6
z5T8>XE{ZRMK|hJ)BG4sqWg_UZh^M6dEGp^JvEC7dGr_-$@s#2hqMRO_rC+5rrTYCm
z&^3K5lrr+k6RF~Q&7|Ua<0oXbuI^fFf?)An0(75<I+ohOd+0Th8E*p)IZMtB?Uo80
zzL=7bwQLqJ+geC<le4t~I6^N4<_@E79eH2^FfS+xIO^$8VEzO&q!{-PGqCVPPv8VE
z3di)Q0l*oIvNm%h1z{EsrfkjQ$LY?k<V^>Is`+#}*3Nx>K&$!A0ML4FrLQ63GiNSx
zfj7=4l=N*ptsZDQ*XfCOcmjoV2j53F?&R&s;9dNaj-cIq26g5^KE()nsQJwUJ<^_%
zEj6Mo8Tr0wN5Q!u-lND}6izDWC-Frz=#r?l(i2tsCNi-`e;-Mgu?q<wg=?U-KW;z0
z%?doJM_0lMJ%+yPqQ}ygTl6^kHjCc2)kt7FZ@8nkuW1a7pN7iUJDhL;CY;CzCQfPs
z>}aDkN%|aMatKODPgyVx-KTe=@3`ol=OW^IDt)y@??T^Y(Yqf@0H!ZOR`ecKxODWM
zJ5h3aMlh_@dmS7B?7iI=*oVH^qW3)<4(vx?YSG`Agc#`kAJYy4e3O9#?+*tKqVKZk
zg9A`ddghlc(0}@nU3Bo!ohU=y&V5`#HGIi5&`Q31G-ws)%|NU9`zTRXgix!@1E}z4
zP8P=T4{H4Iuzp3k6N|!fvL=o#C<;p{$SE0@JHEImtatyuUBZeAvvP8W73XG+3rp_U
zBP2O%;)r4C1(p#dV{?b~DHvHiIcs9B&ACI5*szX;g=6z`vWoKy#utV4>6;!EnOu^c
zo0ifkG^?;MEV*EOvD~#&&e;6IqTH~;u_bx=SZQ<V*s1Zjtek?P=+?s`Lg~NA@W`m}
zxQM8T=*Z}>;(~&)MYd@jeG~J?=Zq~Gk<0$tlV&G1ND0en*)l95A~Y&A;;%ogV;H<2
zm5)E_{N;|thZRjN`pb`L_!rj#GGzT<84AmqI4)#-!T8*e+^p>Uu;NiA<Fdmh#pH&J
zYdNwoY!nJMEIYp#ZvVfR`F~Y;Soi$wqOhXktdN`nn|B8{+sR~?zuwcm<tg^2dt>r5
z6kFr`hI`)~liIxV|F<V8x!EOodmk=!4%(Y|=wwr^drDGwTl|N<whb4wy{4-j96aJ8
zB10mg!^49c*R?@o^kigsOhn|~tUG?4U4rNy!HcCmF@E|Ss1E02jLP$8_Ls4|2iNTB
zaeOj&vmcA&J$a_xy)9^jJ(p;#{r$FlvT{zdhqmKAls`55OfWawziP*OD*JT1Z+p4J
zxb|4w+Wt`;S>iEDu@3<$JG|{X<FO{w{(`jA?dct$-Rx^$*8$oT``_fy&)y*c`=4uU
zUkt|L%L!OK*B+8cTLjo=CSvwdfc*@Zcend=lv|AhDW5mBAL$6KX163k>un!G)Ytwl
z(RBL@qJ{SKWI8q2zAhOX-3zwg2lJ-(_!P{xwl4xHn_Jkgq(GZu59tJLrhNvHX8(%F
z+wRj@E*%F_c7)oGbmlGiWc%&TJOGoHRNh=fcg7cD?Qy9*K>6^teP}9gCfFUuX4yB!
s@%r{PsoWVyy-O=+LEYNECl=~^P%HcH*k58f4h!tUn<Mz?U3kO)0n(5%N&o-=

delta 13222
zcmd6Nd3a4%+xJ>~@3qf4$;l{WCWDY5vxr$F5ke7DO+kVnVwMo&34)jt2Pa~l=c%ch
z)lgd6q7*gPP_t4+2SeZAy`rA4*Y$nR`(DrW{qefw_q*?Vt-aR0?qThdTqmzk+$j`=
zeoAW8j)13%{li&|`R@&5EG^sWqk4J8He^iw&b<L+%uX|;En%#(vr%2foujQOYLNGi
zP}q%H*Z{_Y^1EQ_My@7euCdC7(n7U_Ta-nN8A9A670l!Mh^~w&-Wp8RJrbqK__`WQ
zovXkU>(P-+ig>gPrkP}_<Jn)D41x4u#6*}{dW<8JCX_xfHN^gg)}DpZWN2FqlQ9{l
zz8-_%h0-{YluXZUG;TBmPlqip7N#k_<dJfqFXV!X<chL=BIM;2$p@u>cgQO%(dLRd
z&iX_IbjY3n)5%J-l2R}n@&!-1MMfax>t52H5e)gRCr$)6vLWC1qQEJ>A0r}eu0izd
zX#~{hQLZ-0&eq;~py!zWutd1!ljU41$hFJaNN#Lht_M17$%Lh)TbK&V66+b=J$?Lm
z#!MAFkI<Y5oY>^;d5YxzLm~TkT_$-9b~O2W-X(c{IOG7Y=OnxOK(6Zfj^xaFkb}MK
zXyvtYAV*h}o?o^$GXw^W8wN|$O44%L0dg}xd6s9idz(t~?8mHy26x`hy57)`Z?oPr
z#QSwdo;JBK#%l@2>f=Wzjnx=EADcMX^|dA&YgsO>U`&KCcG<|-9Ly=9d7opRPP;Ml
zHEdTql`%4H!`R-x$N33bOpf!;W#gwYcKO5jsSo4VMwg90#n{Wg$64s_-i%q_84VV4
zDB!zBjJfKJ`Qk@9z@4!*Gtpqk3=3o77^wSU@CmIh2P2;2$&WD5@x$PY4}-Nc;uy=s
zz^D&{Z4qO>5_Mnpc-$A(e3MU8+NN1n55~4&;(-s7C;oGC>o+#WPGj`)hZ&8?%P@MJ
zcdXFHde0POF*Ri@wK*)F2F5DkN1lh7$lhxnG93w9{lD$+&q;&*b1~Qo1D!t%mYtIZ
zhxSH&Wno~%hrzOQ(%`5GD2M_K6dRazhMlYQVZwx-jBSK*?}sP)|LZ*T*tGFT|2G)D
z`eDZZablWLxT^+ZKV$Td4>RP6<zb4~<}zlF%JIfeS<+~bM>0DErTli3(5g<>D)v=A
z$}d4J`nJW%Ff;SR>`%xYxnB84QyD9@$FwmRo$=2Zkywp|yVb|!eU9PQV*84gBHVt?
zDTe6Ah-L!P=A3L;f-aYfl>r@uu_!IN6D~ouJD2yS(gJZZhdI){r7&Db=4>g~G@4iO
z9XM~YiLn^XyjBf^;1S)6v32IF@WvxIp0V}iXqbsz4b6CRwL!Ls2(dOchgd43%N;7n
z+fP{(#F%4%=QvC@OayqYs)+6U=3+*m_fQyI+T+&psQCb*IGqf0t#TwY`yN>=RxYav
zLl*3@_Oyple22g|#JZ7U7RjNcc$4C6-y@gRw*T2=ePH&od=iLPLVb%JR&{QTISoxT
zhlx-7LTMxwO`O6(9O9&66tPKA8cW42y5pP<@ltUXC!?VxNX1R;#X1g&Qt=R%Dnn@^
z6(4ag1WJ-r{KA+^avHoHzJ@$#mV%LN7m}ICz`f^?BkvTA8R(9839xQ=sLfkhA2>wC
zY-^6;6?Sw9`H3%=Ls{kPgG#C_ZqkEmd=sGri=p{Y);sitQbUAUQye4sMe78|Aj>q|
zFb=zA;8Mif?ojsFJ-}k^#ZpHohs;wE-A>}G4p5Fbc7~EF3}{e?qtf%<%r$-yE|I?c
zJ`$^~Y=TDPW!cq~I*bkB_B*hrrkSdf;zo*5TM|r4MJU!FC+Aw9^<ylXo9r>>rWqD6
zHkwy>huuAD^%yvWIgI75suN>An(J7`#&f%JQ2ewf)+{H_;L34~<(EBLLmP<7p2Ev{
zU_3%=*pRWQ+}RgOO|6P`vr{zBv;OE5%U!G<&T}gc%EKAndTm6E4QsHm>n8NGhd=*~
zyscvW%DD=!Y<=qNYgsr6wbFt&gFo6^_}z+^6`W>;(z@)dn${liO(`2OYCm>ktPOXg
zN6gGX<>`6{Rh!a*KcH3eJ0YTFJ~Qn_D|9xOfz`A<eHiOfrkFJ)fU&OpV>#re9Zf^z
zxsev|(LNf<ShupRD{CuiG1k58p<pc<q3ltnL};O*_yAO<)YfXXVJy8&iPMf-Z@T#M
z9@f8H;w!GL$Cy*RGX+6O$bp>f^3sUlG(+Udacd9P@;t|y;~En8axi0mifW9ptr+6{
z0nGUMQpQe7<I#T^55x8A()h!_jP};+t`&K-^{s0v-)QYpt|CvijsmW-7MH8o^h!8m
zuXMUxjyr!?+#jd8CD*y~!RT#8_1%`na*y!-dTsiR#^hD#W3#?37Zz-&$=GjtEM8@0
zPL{im#lO*8{%zn?Y0Nm++RiP||62t13nLxIcxo_X$BZ;sL{rOVDOQ_XTaP>x_Bj~s
zxUvG<;lpB#1y5|S^71wKK5JNcFW%jnT;A7dUkk>zV<KzN&K2(zYfkwHY5Rg~jpo2M
zr}WeESz1s$>PpqP&>#1PVASxE07u%D@kz}^RC?IPn&=f!IS&U`L&}v6m`uX18n#x=
z2BA+t9jHb(Q6bVg-7CuRIC7!kpQ<<u`wG^RUS2*P_#~tHdI;l}_{gBz(Q6fRRC_O>
zl$+}v5am4t=5V#l{C=>qs)?#SV=xfxTV@jB_Yf4dzJst|Z*A}G&mF8IyxUuz;IbC1
z$#TL`?u3CEgac61g84~%6s|nMj1vg=Cle;FBz%K_3U;O?;cgVQV6SEnM&UjZ>?C3=
zSRQs4tYRc#qv?dnxN8JEm`B*#vXIDxw})U?@Igzk`0|9m;Jqu@xe<hi<Tl&TB7)6f
zgzNBf5bP5ucoqp4tgT!+PcD5E9VpmJo$y8!;X}D{-2o(PxE}@ksXt++3$h^C=V*Mv
zcH#vqSh-Pz*?3tAmLXj^kEjcFSvv8FAbD5{VcVI6Rb(W_q9z3UU2gA*OGq$LNI0}?
z4yr@26*8iqP9b?x5@FLy%mPZ4fm)0@5Nu+5!YXpPCAbO&i>yNUb|PURdRnkjxxvPE
zBu}YGScKb1u)k!oenY<rRxO@zA$m)&Ek%T{`VjswnQ(kl!u$n{Sp+-PgOtKJ!V5zQ
zXAL3zRxY<iZuxZvS=PvC%_<?;J&o|5Ou;lO$*FS7Wy47RRaSt4`a>kT5W2{jb7kbt
zH6}{{Rg8t%NmI6*I)4xi#LFcPN#92YljU+7!tE;IcO3`|WjcP4&izuCELUWNN~P<8
zE@a6HCv=oa934h-T{)+^jIpgYSu8Q~WLKM!(o{ZhP$pu3Hd*3jJa*#40CFb1p5{w(
zu`IV$2%umyRuaw<gu`T!9`GT#gUt5~*;75Hk;M%SC|HBGgbVRo1Dv+VN%YGE&NP-V
zST<Nd5y`7V2)j$)Q(Q@IJA$yQ%-?qD?ghDJs%+78+()PtPMB&U^cqjtL6+M&Cz7wq
zMA!J3<mT;VM$hJvlAsf&$o7~dTV;Uk<`mq9g4GEiT!fDUg7uZ5yK5skHkR;L8KI4i
zBu|$P#mTbGk<qFxop_r|qpf7RP141%nX>-J$y450LBl)beUL4EpO;9MZL$t#$hHiT
zrFXu7?5zt4R|OF+4kf%KQ(%ZBc}GRUB3T)8my*1nNy}Wq#<CX%ARVax5P6QVt!dzQ
zS$gN?<uFk$-B^x3ml66}CS|f8&D`rocw2`3d%5V#WU>eun|HD~qtnRZQB1gcD4}~<
zOIIR!$t<9SHIv(HlvU~~Pf)!F4gW6B@vbMysTByH$@-`%L)vOES;8|32g|-_Jdfl%
z_Jncu2wN(IZDis~rjUF?&YYD_@@yFcOFNlk>u@sdmo-^cRzL;mZ-|xbB{C^J29dl|
z#>ux0$vtIwd&x{Ml}Y(TMvKey-E*cnsr3oB%6tblA^D<A;&542XDu>}uG07RJ~TXI
z4&l-+gxw<uW2F5>N0N8RU|yC^@0FM9RJmoSY^^>rT5Cqo%olNlRbmO-HX!_^Ibl=j
zbW53t8w)ICIv`UJF_PpWdA(dpA=xgFaGVVFd6`|52P^~Sa%H`9P!?urA=%@H5FVD*
z(?T|Fx?DMC8QBj=ha6<2Z)#*2HAU9{%6L+`$@;G(AHFGb<{?AsExkS~<KZ1bGn>dQ
z<7G&@$VBv!<#sxWMm^<KmM>#)yNE3JWJ$sw$d}|(n-fTOMe(Bk15BjEb&@!Z@WoU@
z-#Uc!4;M~N!k8GsfpTW&#w33qO*qS$FipDdF6CG}DA=Y5!cnr4Zp+SEP?anZvYc0^
zLbkBYvI2I=P!E;a>ME<DKze=RV|t*RbTLVW?wq_#j>;nXER#mtWD|bgkT9(y;pr&C
zEu9HF%U-a_B8~4y7A{M;kBoukybNZr^!Iz6hHs7~Tr0OZCOcb|4%M4a_FtD0rb|aJ
zN*B}Rv#;f|xw7&@WcvO{r<p$TV7>d2oN6Q7AtU!Pkz{X+3}$8@QYN?%4j4z+P=?V}
zJ~pC0S%T=gVDVXmL*&ve<%!?O@(c?h`{wS1b!0>}SygGSWN9L+#4697B-c45Bazfp
z*8eLE=<Jp>*_x7U=S#Q)k<i(iZiKIA(?aW$NzOwIboK-#rnB<0&|F~`tPdijvy;*l
zArs*vW0{jj_O}Hz=bM^@xs%A!rM#^FvkS<Cr~r@3?!@kp6XX@~b|FnQ$`f>4Np|`@
z0$1;NvOkg$s?&?)UlDelB~&9c1rcuPO?Y4e;f5yk)FSEP;HhNUgvzk!%t>zFU$)s}
zSuAlXO?~Y{lYGlY+mmIW%<)^fac(QJMCQ^Q=h1{d=yDyu2NDjG8#m7(`F2a1nct9*
z{&<Btkm>tw1!N0rEc4weR34d$;2X%WUgKw4IJ9L3FwBBX>ft^Js2)**Kw||aDs|2W
z2FxNif)c%fVL$f(Mg>ys*E*jDOvt3;B-JYdb~-@Cn(Bh|if*%FfEiv1)c<{|4}>zL
zE@fwE6$D%4-WmiP6*L7n{%}v=WZse1p2NdvkwV^=CNJcTjG$FK%^$Rh4@?4;@)ONK
zd-(vW^?lqw8?>KyCI=7jXYQacxqk}i6n|Hq_P@YO$3VTvQx}2m@U0Z0<;vCup!Eu;
zEk0Fp>wtDD9U6f?Qz}zo>{1G5fDS2NBJJY3vYWIU%0$Z1LiO{Npc1u!T49kojV_|q
zYTY={8a0K|yH*{9DY|8o`a904Z&$BZg!Pm<0@W@~tDl=eXVejGLEo#-DB|bUM<YQO
z)HI6iWA%6?&|Ga;BxtjiN|)0%&4=o@RD13M`c%sq0{TpQ%<xYpZPPRefq^)<)X!?Z
z<Eb4lX;&4{O|4sJ(9c>L9q_64iS?t90Lyba%6###E2vnc+k+N~GsU2#qGn&v3Gs-s
zdPbb2?S2r~=Yy_^^eoU#v92=cClN_GeIS-k0zDBrDo}qW?1Q1r)sLay#8SPW0JK`)
zoCsQ{w?~<aE&5ywid&TGHM)TI>lvgS(RY(}OwY*$eWll>OXf$t)DCo4ZygAFtiPfY
zJ=HhTTj8}Hq=DY))#icn4bHtmg@$|d0$*Tg*9o-H5HbR^*sy>qZH?g+_2YWO9{Gme
zWVnlvi5-S<PM}W>zfe=2Fxc`y-x!j~r_%;2ZTN#>TvgB&LrG20bwe&4=BD9NKIo3&
z3~BcaxfF|E4cQ5xSBB11BX11N%7G>tkI_bxjb|z71;%gXC)63n14E(CHcp-ZnrG}q
zJMA&nqn(Z!yHSl?G|q|#T{dcHS#jIwLDl%cm@ysn)Hs}jo*PflL0=j>)9HUVrdI>K
zGyaHcMocg@r_Reaxl@TvHMOE9wwl&fp$^$#I+h7_vx(0I?K8!%039|t_5^)lQtE-e
zHN9L0I%CSDayn;vOKo%2G=%E@CsPkP_9K&B6VNZFx)ik+rg7n*-%Qo0U;Z??P`$r3
zRig^Zv%6ggnq;?=VrZFSXHVsL)xJe-&@KB5AAx?dKTU6w`}QXcphxy|`htG8Zy5*r
z#l9Am|0HwP0MK-E8*<xbK4t<fGJov|T4wG}aav_=K{?oLZsP~qZay>-^r`uL4bX0L
zi&~(47V|l(vLoi%6vVI0Yv>|9V@{3%T{4H$oEzrfs4H%n{~QJS$$XXqeBZpa1E|1Z
z97T4f!y!6Ep~G2<`aB1xBv7%#8_LgOhnvemI~<Osf<AQ^I~BCc!Af~O>R|DqCmuM|
zqW*j7aGSPx?QpR@XtLubdcMHXZ49W$u{PRC_I1^k6!G8%lY!Mz(twlrYKnJ0|AYcP
znOCP}rtri4KvQ`Yq5{6B05pwPp(>lsuLXf-aEl{e4f-NZ?*g%t*B~E1<JpTqyLjp_
z&~E;;9cT|XQYr1_Jt^$_cp#p`)$2!fd4PXGr#Q%iD0-jsB8t}`zMwnkFds@CdxRgS
zEB7dO%LaYHKg$Pw&4*ZUDE%I%mypO;PJ9HKtV9_>Q<PDaK~t4?)K3M<W_n_pa*|Fl
zU748&nxQPE!^~7{QJ`7Mx;~)UN*~JF9L1eFuTa@WeN?2>hy%@4re|TlWy-O}pzoER
zb1mR0s@e#H1?p^6q+X=byHG4pgNYWYJ4!&?)#Ykg^mXk4WnBCUcXWN?B*=!p5PX>#
ztxqxp{orD<-f0drI+JUrQFY(X@V_<?dhk=^PM^e|hGT!EZ89e51-v7IfebaC3vD_-
zI2hUto-qvCQvSmnXv_FYO8Rg7V>;<uek2DpS=k~}s`ycY<}00P_l3%14qB${A}_Wn
z1$4sC6(<~De65(_wshFZGQ<y(SHohU{}`&b@F!G!4JJ|6+HIkRANUtt0yFuabd<F`
zpUPoBe@;uC;txB+y%)SqkM}Fub)gNNkBx=7`c`<P*YHAZ>7g#T<n%CiSNsh*JabSs
zK5f`gNftfQ6YZ==)tZmTq8}v!Ywn?5j=3=#SZie(F!pQ^u=Y86d)CpBJ5kq*BA0M<
z1h9EFVcQ*Xz;0`>vFLYiDRAgqx;=7JsZuBK&*%^Zd{}Fcm48oVXyX+uboZ^~6;nZ5
zcuY0WXZ$pL(RXv{{T?pe-^-={`?x&7elAaNfRoqy5l$!3k8(PR46B{TI0)tMQX6^p
zrvmggp#p?|)_7o$e+;l{W4a_Pq1S03@*W*FI&wL%&LJwQ2F>aN8>Lf6Bz~;|lXud?
zts2r{+l_@?ZsnfU1%mI{9AMylihW3vF~FGFblyf$)OE>O4T0^>(#?~{znKD>z+?PC
z6D@o!m25F*Z9xn9v*Dl;ejh1ASRT`=tN4Z#&}u%Iw5|LQoo5^0(+aem@1$jR^R^+N
zJ-q4y&|bcuR{4U@N&p?>X{$iT`E<HyzvunQyYoED5p;oDuSJ%(Jf`(u@!j-Z_>J=_
zpx=3CdRI+R-pvF}RVvbH3X~^9Kns+u?LjtW5?v6*N`8OPTICN1&^kq-_FS(B6eK>(
zO}7K>QbH8aZsi<B_PDZ?*8EawMJ}9H7Fia7FDmt^qOK`}rh%?2ugRHPN>%dqu5v#D
z^hoJLW%WuKMXTkh>sEp$tDDk5Gu0E+53|$~8>m=4Ne?Vkr+o}st=`r_Yt%Os;~lD(
z5%h`LG!}GN{jv}3dqi!}`+Y`DU!!Y;<ERcmCq_|l-j1#ju1gVWne)o&6o#IkQ(<Rb
zhgA$|Py)>5l#}sm-QUkMv`5bg?}TVz)kSojRL`N{hP_Mz-d3J>0^L<CGp2(dE0ZXI
zPnGGzK+lzh<i$%RH4^l@vX5G?NHx^~EmDgE-|x_}hc66Wf2JDjdD<S>Yim#7J9T3e
zXo7ad`hMn*+yzVMcX=t@U=R6II{okbMPK?1@`i`Zg*r)DISMpQd8vUGD6yoiRK87l
zzeagw84MMQC~uxI<XF%OtS_n`nFVaJjp{pjqZ6=s-@o^*bk_{szd2nR0lw%dis1Vf
z-uoAiMZO7O{WmWH8TZI{@K!|ar%XpzpjxO^p&hW!Qshq5eN8*puY=f#1~)0f4UbSQ
zHCkB>82<$YB*8#2PIPDnY;`3a*ygD}<-hBg?!eUfRBl;!C`kj3Qy~vIr~`-o8U`G`
z7Wa$Dd94C-Z?pxDYE6M3-I^91H@GHnB41Swl+UZt^)Z>>BI8sZ)CV-3mr|F`;F~FF
zGx<D<*KB^rQUIRAJu88VcpQ0UrN3fO&p)JEUBe#_0IlU_8)zN3Ee5UU!Q((1`4N;G
zenERO5ww{vp+Ilt0i!{e_-H!%UG6}}d%O|_?mjnB`#s=$DRmF|%#L*aM|>q!&trbD
zDd;I*(h~HH_n?Ho;v@4x1&R|jT%i(6mAp(D8vt6T*ioMxR9aIaZY!(F`+Le?R8IF5
z2XgzVax)Y3QdvVed956x!g-^F(3+Ff_D=Lyf_!!GK&Ug+CRE@>>R>wIDz)1z&~ddo
zx%Q>nCKYr_ok_Vkt@bShomGug&R5kvbcbA1UkwG_Qx7MA-l`3#jQ>)v(E%rD1r*<j
zS`s;vueIw3nypR1nil+?H?j@X1zPQ~poLoNUZ5q~7p|aX+QkN-BU(yT&~YuVGw7st
zo`P^nYfCvet38|tx}cq>+Pkdn=m@&5jr9lpq<u@3bys^b1$0mQihR1SEg|n8Xdfkm
zI=<7~qQQS@8C0W1qFH5-O?*bNED^>=pv5AJ;=EiGQ$|*bWwIbd2sQf#;Yd}sNw`OV
zwu#a7^4KA|TMx#1TNH}xNil{x=ag7aWr43UQFgx<4`M(+h*NY&Uln($t$)PdGC(&)
zyC$Gpq8r9!#|HGJO04><S(z@}ZqwyeLH4!#GQ;~>WgleU_cgV(g<d+Bl#L47`$vWT
zzVY96xo(+5SJPZx4|&$-$=5&r@K8Wqw~yx)gAVa36q*w}8-bQLgUjKMAe4Url)4h)
z1|jfaH%fibsrtaGbteF;U8FZcjUVEHVUhiT5kE}>MwO?wtyxK4DpyIao$C#(w~^x4
z;A`9qa^aTKd?2I+b^{jim>HlF#cm>Kk>b4=v{;Fy0$HLwq<k$6QhuWJFH_di;Bw^_
zIk8!B4ghUYPTN3Rl{VHfb-XP{$=3slUofaxomK(#iP~{_*~Ys4ACq8kUPGf5Hure%
z&OX&1p%=&0E54vp>I)O-tU8^l@}lZe9dt{*+5+^GS{<nqkJK2-{m<&YC7@qa-2*gL
zYhb1>oUV1HI-I4s=YVEw$yBm)v?J|6h1z^F7HKW$=ySD0^*~n5nSwV@J6HuYU)$Ce
zv_P}c>1>+Qd{D7=D;u;>%Pj(xXc?iPMOsVxpt4xAr?y?9T|~cG#8NG*2GnJmLY=l;
zvkM2U&^&`cE4A&^Vym<pG<HsuDxmL0YbvkvV*en}1#z(<=%T3A9Q1=&NU^viR#Cz)
zi{~MrD<WVx=&Cp{40KIIQ&Mh-9dzkf9*UXc!Oz4XO7UCKj~>j^FVLKc`nP>SH}w`U
z%0ftJLlxJigwFr*Z^&v{-TAG8;81H0uzWG<SX#Rl(rY5MvlZCwC55W{(5Aq&d`d$4
z_B>!uOKYl|UPq<_dk0WOWsIS2?X!UHw7#w4f&DI0F=Y-Fz=405fkW1{1`hS6aEx{B
z1RUo>SsOo-f{@3Jl&#79aU^I4SG$6W_%Pbm#w+@Q7V%?&pk>@bUqixY&P3z_Z=7Y6
z^z}U13AB;Fp&)GHjVPp>`5E$YEB7XcxAD7;LEHI4>df6d*9iJmt2Y_+QgfRMDi)sP
z<W3Pu!MP-gC~}vDqYAnrp40+e6$dT!M4>*BTrAeV!4)WD7wXgx*Fa5<Zqj3N@T6XA
z2E5Q?>ANm^ZTfPHUgvNCu&#X{V7+J@N3UP(2W+qcm9IDa$`06QT_!MYgg>zHMw$~J
zFbSBDj1tllSB*jU=}qW6E_zZgL|ku5Uv1Hw(RW$&kLYVGddm&Sir#84E*-t~ER>v{
z5&|#vHn!ftwi_z~+tD{$^!B%K6YCx5OD+1xbCD0dqfZ>LQ(^+J^S5chF7#a%y{m$P
z(o>&TL;vaBX4A&qPmTxLxUVaym~R>bTFA5egGzW+R1ZEq?L>*P9}#MmO#v$WwW9;$
z_y;q7ctYLq4#P8s4G-^?K5W3q@WhPaS=ob!gl7*9&F+^GI&kpdLE$3@56c=pB)wM#
z<_rqW&QOPE54U<XY!#kRH?>`R{BIc@m5|djBRR22kI1mdh_J|i*iwfK$myFoXn3l1
zMM9IHk(q;{qi9-KL|9ZrRCGj4RCHuaM6J~9!Gi}3PwkmGC_F68DjHS!PgZaBKUzI}
zKxWVIzP);drw<z#I%x2qjL?kqo|)m1kzvtck=Xsif9tk*{|NRUobvy_AMVzramN20
zA#sl$K5F>?j;K`lkFsO=Z>r=UWs#aWsMmm;-WjRAs#i}fE0NTHPRQ<;Gq7jsh*)$>
z^*%#V`=t--jWW)r5dGg<tKz@ut+Lkgvvx{w`A@R_KWwjU@$RL*i3=)Q)hzeY(tat5
z)pDb1sdrXV)zbBIor3HCzdZl<j^py^nbX(0>9v39#l0IUm#)3h(9SC+vQB7Zotlv$
zer3V)L(@k^#70K3(zg#PCArL}O9^kO4aE34v@0}%XBm~WH?|UdFP8VSJ*dq`@?2Yb
z9p0KBvh5)H%Es%0&e+=2<s+5a!gjJQZ>4k+Hm`bkWQZ-Z9&fF97;Jk<?PoL9$K+yL
z=Q7$rwBGgyNOAVHHE)19hinTQ!1|-@0Z1`cvej(}>w4R?hNSx0E<;sn``fBDl9NX@
z!sPq56ClO8vdt?Fqj8mO{lR>@ZBLwB%G4O6!9lhzjbZI)+W?j4+5RBfZA*@qa~2Xk
zvpoPQ#%i{@30Nqlnr%9m7uYT(V6@m4l1QV~ZKD%mU2i)96%Kng0rj(G66M+U5Ea`@
zN#s$utxFQG#_!lBC-FcGZb;%)#i}I6M%&KAqWC_v{h7q8@ZL86ro1X1OD4Kw8wyf9
b9@$EoVz8g>FjSAPA~>5zFN^p8{uciWD=jqz

diff --git a/Debug/Libs/sta-core/src/debug/printing/printable_printf.su b/Debug/Libs/sta-core/src/debug/printing/printable_printf.su
index c8c518f..dd9089f 100644
--- a/Debug/Libs/sta-core/src/debug/printing/printable_printf.su
+++ b/Debug/Libs/sta-core/src/debug/printing/printable_printf.su
@@ -1,3 +1,3 @@
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/printing/printable.hpp:26:11:constexpr sta::Printable::Printable()	16	static
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/printing/printable.hpp:26:11:constexpr sta::Printable::Printable()	16	static
 ../Libs/sta-core/src/debug/printing/printable_printf.cpp:8:5:sta::PrintablePrintf::PrintablePrintf()	16	static
 ../Libs/sta-core/src/debug/printing/printable_printf.cpp:13:10:virtual void sta::PrintablePrintf::print(const char*, size_t)	24	static
diff --git a/Debug/Libs/sta-core/src/debug/printing/printable_uart.cyclo b/Debug/Libs/sta-core/src/debug/printing/printable_uart.cyclo
index 98ff82a..6c3d956 100644
--- a/Debug/Libs/sta-core/src/debug/printing/printable_uart.cyclo
+++ b/Debug/Libs/sta-core/src/debug/printing/printable_uart.cyclo
@@ -1,3 +1,3 @@
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/printing/printable.hpp:26:11:constexpr sta::Printable::Printable()	1
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/printing/printable.hpp:26:11:constexpr sta::Printable::Printable()	1
 ../Libs/sta-core/src/debug/printing/printable_uart.cpp:13:5:sta::PrintableUART::PrintableUART(sta::UART*)	4
 ../Libs/sta-core/src/debug/printing/printable_uart.cpp:20:10:virtual void sta::PrintableUART::print(const char*, size_t)	1
diff --git a/Debug/Libs/sta-core/src/debug/printing/printable_uart.d b/Debug/Libs/sta-core/src/debug/printing/printable_uart.d
index e6f6515..8c46a93 100644
--- a/Debug/Libs/sta-core/src/debug/printing/printable_uart.d
+++ b/Debug/Libs/sta-core/src/debug/printing/printable_uart.d
@@ -1,20 +1,20 @@
 Libs/sta-core/src/debug/printing/printable_uart.o: \
  ../Libs/sta-core/src/debug/printing/printable_uart.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/printing/printable_uart.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/uart/uart.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/uart/settings.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/printing/printable.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/printing/printable_uart.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/uart/uart.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/uart/settings.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/printing/printable.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp \
  ../Core/Inc/sta/config.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/printf.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/printing/printable_uart.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/uart/uart.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/uart/settings.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/printing/printable.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp:
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/printf.hpp
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/printing/printable_uart.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/uart/uart.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/uart/settings.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/printing/printable.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp:
 ../Core/Inc/sta/config.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/printf.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/printf.hpp:
diff --git a/Debug/Libs/sta-core/src/debug/printing/printable_uart.o b/Debug/Libs/sta-core/src/debug/printing/printable_uart.o
index ce183769c9760ed5b69a5db76c8ec5e53870f45d..d06cd83fc45eba1bf2d9cbad8974a4dbcec2d78f 100644
GIT binary patch
delta 14932
zcmcI~cU)E1*6m(<@3qf4G?8AEs-PlLq*@RK?ASH2pdzB6Gy!X(M+6ncf^79*2Yat*
ztcfv}=#3@Dt|@9PQInWr)I`l2bK&*-?jP^{^KO!#W2`k-n`_Q7*FiZo5BQV&yxfN+
z?(*HJm^ZGFB;S<-CF!Hyl4K+O=YNXLHc3(%yGFrm#k9`D(Hp1&g4{X@lW}k}^!hdi
zM7s?llgt<HMz54ivF^FTWN@N|_T_+Nw`pWjdGkE<szWn?-Q5=no8ga5=;_@7Bi%NV
z$;jJ;q4yh^GTjdelcDVr^!{oIm{Fe`Q*84ArC#Kba*z(G@*-E1IU@n9y~zh<ioR3z
zAAWrvnrFOeBW1Z6aK)X@QCtH6-*^c7{2;XNySHbO6rl3VoI*(noeI-KkNz-OsfHhR
zpx0}#B&kjgO=$J@1hm~8TT`12*Q2?gyZu<0LY-!jX=^{UV;q-LyN{mF{mn6jup~RR
zz<x^jIJA2?CsRAyUy``9+cBD1S%$WY`#EY~LR`3~`weQ_Pe!|*$9-xahZEe_{a0$U
z=4ktQyrFiG7utdDR<vj1b!a#8aH00_RcJT&(&%o=BHcstXGwaT=4xv-2LnC5MJ!_X
z4AUMk$3NRilJ%FabmvC)M(b6~e!V`(*wB0#{x%+)hQZBDse~4cP3k~7K?Q}WlC8;l
zu}P9VUdBoiondD*a!IP&>wQ3<_a)XeI#ZHl$zc!jsoFW%_+ylxLcHyq93EmT2#^+d
z#8lR<XO5j|ePR*<T(@1PZW60oVKSJ@2jbK^E{Y~eZ!jKA4T;&2ISNX$b&{lUuovNv
zMjhq~ki>Xb=$TB5F;@L<ydI4=qxG^apO#uXg&oBBiFb2+X->V2_3&JFvg)kQHu*De
zeY?qzAF7e04E?gnTXsp;|1f#6Z**rXZ&sy8TKSr3fnP$BByE9{`|w8#z((x8Ep{`}
zVB=$m{pT3?>fK-;I!X+N4#&!S7<l?_aNxVa7~A%6*dR#`_*1)W7J|+i!ROlL@sst-
zR`oj2F&)cLY3(tw-@D1n|8sKpDyS?2qXq9~INSaE&g?yxrFx9Dzd1Zvk_OeohC4B9
z-@j){CbFmXS%<5@_SL`bZ|_Niqhc_44+Br%4c6Y12FDmT<0?i39)D`DQhQGtoahND
zdSf8ODCsw>9fS`>ZdsDl7RH|MR+RkDeQ4RNK;$J2qXq9~{I46+jB<}qNt%w)@^>@D
zjm2duJ*G?2Y7FfDk3lv^wMI}}9P#e0c{p7kXVb9jysb#D-2hw-QzaBY?G3&lf5e6^
z1&bwV&&w@H6-NF3bH*GJe(1mAG5L_)4E=$PSL}CdB`F)T!f!5<Bzsq{-!@9pFp|v(
zS}K$%HILXSNzOeCHz9(Ev<$R68A|myTi2n^ol%^FnJ8W5UR#t-Gdp^8l`@oF-9pih
zGS*$go*)L?N|K`0y6crk*xKt1g1W(`l9~}6C26B04NH76)!$kJl{DTDeXng}b2gqH
z2N&^hE7KcElB1t{Ean>G0N(9=ahkpwGyFY+VQ|R6TkGZ!VcdWYU)=+iC`W2b)<Z^1
z(PCqjFUOnd5N%DT82L@a)FIl5IyQVO^5hWhNgaFZArqt+YdyuTUgYusNowHG%Gd@O
z;XmM&b%-<7`uOV@blQlH%FA#Qhj`I3@<e^RoqO8UXqXa&$%)rTDjgC<$BiEiL?=mf
z>haFO=(HCdAITv%6OK6)7)R1^&GDu=6xOA-#J>zjXRLTuRmso^CWlsflR7O}hMrz0
zJn~#m7^<!4Y4qVE_n@<;{;#(1ou}i`c34;619jGjmsX&&(Y7@@P5Eg3i#nlfss6f7
zL%Z;q7}zhO)PpDJq4w^*Zl=I=%+47x9K=tdvK&4WZVs26MsJg(t|QsUI6ytw1tX(b
zZRXS?_=IxEW7acqf~scGwey%0^^EEl`Z9aZ*cbRDbtq(}+gR+RK0ui}Okyq%>L7bQ
zL$dQEhYy*<6ZGn-(kzTkVOFou^HKfvpY1(^b|=ABQoFjT`o|9RW-v!)4|%H$5^|Wy
z>^1Zv)FXOi-Doyn&#oK8;`H@(E4)9Ni}BYUS%|0M19;@r2i5E5%f2LEl{Ec5hem9g
zKGng?T(STv=)wYUu-ddKR&`^wT2hY$q1V0kwyHXs!r7yC%&6WNfnHDMM9XX>1BuV+
z1ytFiFS|%P{Wuik@7MY+sb@({{h5fbsy@#{Z$NF&Mz8N!r|(~og2NzYq^0%LmBr|#
z)SlZwz0m@_!L_p+sVzx-Luz}WYB>pcXl*Y>_3e*dYHcrGP0@=Sy;v)~%CVhy=Xki+
z&Yl9HL>8glsqQYQ$0iKXb9PG6nUfRq(_Nf`%=RB(^iNK*Uy4E28z33Om%@5RSa<%9
zHLW46-w5l;|FO2pgY_q2z5Q=1qn2c#<Ba!c)we<tT3wt#+F*1ZouwajN-!@(9XkEX
zNJo#L8T97WLajH;N-+LZoG^pN$;#+O65B||1*I7OU5r=18>g0JXiXjrL6tcDq0x%N
z{~ni&WzeeA9jrpuFTOMT=@9K*v6piS^!S(QCmIvaux*_jeVcQb!x2>fb1mHAtt*mq
zmj2Y)ncdVimj-@(lq4M&cQGECgcD8}>B949GBqS)wBFUlJ3>KCUV>5G2VuL!GMl4_
zh~$%>o-MhwsO=f0`i~1S*pexmFw?eJU*+P-{-qysX~;g;Z@c)g6T0jg=)8X<GCRtV
zgik;%+m?Eqs}DP^4{`Ni$Ms3Bp)66~;+o>P76sh`p9EG+CjYIBYIoh!&4>Bwt=wWf
zeS1St7>!Sber4On;*+B7CRkSM^W9?V(0CAfQo>8%tUXuUYE<iX)l^}c#=Ua%MfICI
zCeDHAY!t421z9V`dfcU@ezSf!E7I+}8g)69gW0O0ICJak<1y~;ZNPq#T8oP6!>z6&
zG>Vf^Y2w5^O~cWy@5_zH>!V@i_ja1KKbI5rA}>FWDCk!SvHp)u8d$45Fke67<;tw}
z%U-^0pZ?ry1iPva_HNA9>ZRU(<{uj2*_H0?CaiWRw96%o!Ns|B*q3nhKEj^!2<P`8
z9JH6v)Rk~oUqXNAi%ZS%G0UY3GYAJFtX#Schq&}j1mXMm`v#Ztw-Fk|ZoSM~s1rv&
zeoL3r38P#I`-BoUMBun|7OCRWL%arDT7wXAsns~bJo+JAvW2#|R3Ntg9m?jC_ZUJ&
z9K0xs+TV+vZ;Mq9BgrxeACX)NaKyvKrKc5y-P;n*oKE;RK61I#U$}A+0q4>K;lxW$
z?G$`uArj)QaUv2!p#m-$w-X-NL-<5Ew_VIxnN5~S{Rm$#BrF$^yXz~N(RqQY=F(5%
zu8Z*ZEiT=Ka=8@0lQ6h3p<#ir;ORo}YY1nR6E+qJa!RH4Dsgb%0&3syK=@lCp^vys
zgoui-IDTs~*+*}XBr^`qpiWGC!c8JK2O%XcWsB`n#F4LrCT>B{T(WE>Y@JECPTbOS
zEw$Y`5`I%exNjz5y;#CK!wAo>B%E9uIpN$~Jo(%#J$sJ^O2pLsiPZjlGGTZU;o2a=
z+x-cjDukNQN{vXzeBs>0He|mi;_;nueQ!QlmWo^c<w9*^IH8A_6DMNa1)t$uGW&>|
zg>|RS9x=&Yq+`QWvMl?MaC9_bknq~whuXWB5Y9#bxwKg*;F3^Al@RGuFS7fJeD86m
zc48&r1UtfJ0|>{7sMMInq!}XLQ)bb?4dKe7YHAyT37>=!MhJ-&Pos8;xLLjC)UMN#
zFf@>`t58W@nc9x{VCIrv8R0M?w~2MBT_O@aRzxvnkkG%UsKvD!4d;&}Y%-p3(^A59
zy$FA8K<FPw_`DV2>`jEb#qpa&gq-ckvR}lYRby)Z=1mwcoERf2D^@6=J|p|+WkUbo
zHKoo;q3Tszs2wDHpVXP!CZPjQ@uav4>3!-)_OdF%x#Ib1A|lj6T;Nm$+57ksx(j7Q
z?xOYu@p9C|1Hz?#d4yMy4(LB&BX#-;8QO?=j1rGSme_ir7;Pyc6t|jYs{Vu<gshqh
zcZY~gzwSZy@gg>Lg~a-2lI5_7Q)eOSoE>C2E1Vm+0&TPOi^$x5R~qOqMARjN+A|^v
z7iAHSawB{(i*T+8Y0F8XEoyy*LhXB^2pii{`+ITkRG|Z_hGe-b>fT$Wc7xG`YeWpp
z<s!!$#J!gcqk&FB0l7l?HR5Ka;+B4*IIBdQjG`bP2{jB6neJqvwNc`(YsLNMIFQA$
zE#Wan=--9#wn*Z2p{h^JB8<C)?=wZ&bXrA|=BE+LB9|G$9zB#S*_#Pnml1j{C$ttv
zRw9>pT*b|<Or!R4q4WGwYCjQ9*o!023#a#qM4YU>_W_aVX~i^kZ3^LWq0*%ybfZM5
zkBIC-g%~xoBg~mY*i8sCQ;0EFJU;z|daese#)_SL?53IN!XaM~X$O($V+)1;hjgUj
z*W$U|TuANR^$BYh6DmCkKNIno(v;c<rW5uPAx#pAcyAzCUUVhw(~WSih(W*A)Lz}1
z5IzHc6ss~jQTtVZ(EoK4b&7`)I*NCyTpWB&EOQde8phCQQY_&WF_U$m_UvdvFOlhI
z!u2C{$udRUuX_Zwy(bgiokF<131OU&^X7E4&C(K~fNJ=HJc-A|a~-u?iQ}IPruG@(
z;s6o4AIr#cb}M09apc6Q)LxlDxMT?7^eDpF!w6ruA=Dcaex6TwqaUHah=Dm><S$qF
z8)=|{A7&9A702{gL+wREo_`6q>_jea2}di0iyOt-L1L}yNAvGAAS@SRJlBxgtH%&-
z-ALG9MDCe*+y<LPFsF!Gj1!*%g|lhW_aclv#Ij(a-WfveSB1C?VrzSGV^<-%1wt9W
zj-<6VBBDpdF^R|@J{^QgvP9|L5&JY1FGp^&2<dGMXi~f|UBpL=CZ%~3u0kY$BM1+y
zq>Vm66=;(GF2Xj&gwfN;zCwIx^;u7rVDX{VNF>5a#PZ|0WIrZeh>Jo=X$#2G%~k0C
zzy{i)uMk=nk*zS%{;(I>A8(<lzr9cGaeE1~gxp>uL7LQ3Wb{H7wTlsIO<IrRHR*OB
zVQCIw+<d~0;k0&{aPi6_vUHD!{x#`mn7A~tCt*2EsBDEWUc^8Z&P^UfmU9}R>l|9#
zRfwp#gxcF@5JvAN%tnD}(xYs`Rz-wITG6UBk*uo*YF{5kIH?9`mO6=i&&C$8N!&ZH
z0_Zn_wr@D4KCqcxCNTVZBrvKMElsc`H`{No2EIRrL^!BLGB9NY6=?cZdQV3DG#;4u
z>tf)TpEd(0d@>O@F=rug%KL~IpU%eHWq{|iD)O<Mnf0n5C-bDP=<H!C<@6vsOrkx+
zI!y%~W;%Ivgt>TtPB9zG$~k63^?Zd@mx8Xc>DxfxvpPmlmD~~U4&NxxqF#+G(c`;U
z-jN8}C#UoReI%ctkD#M+CRNHe@-s7azm@M&u$L$=DdkI*v83r`N^k^dt#T&`v`(2q
zd0MZ`#T0FeGK7-4Qz`O=@tl%30(4%nrq6{7%E$qrOG;1L^Rm(!S>sofN{Z_fr5Dv~
zh1!J#yH(9IlT$m?wdCm@bqCdCjk=nOY@aG2xwTn3UWtaktLxkTMb%>k4A<4CGU&G2
zVi@Qr^(5`}vl^+Z!G7kZ`_Ng$KOPRM<a2C5%XlSaW+l%b13JwE=<UA1pVMjA_{Zx(
zU-Li4f^PE<plE)N|2_fq1201X@gI3H<e)v}o<ZnUXnlP^E4AiSXlu2tok1J49MlQl
zruD5i6TC+=rGXA>cGNqjZKB=@?Uep$u#=eupz}ntqNx6?wV`AG(#ETxH`?j7pb|q4
zbj`~R9qA2OY*;)Lw8YS58fdv;Uj}HM;YTW@jfScXpe=^q5h1?I@WvigW3b)`I&JuF
zF6axxgBhUnh7A<5YlcNlnt*Q_s$xLj7zUH~w+&W0=zGHj>OC;@B?bRx2-BxD^EBH~
zJWGwu$d@u>+GNl?qlQ}N3ytGx&jZG2+VX_48)g5hv2#bz4db_X6!=|ZUy|7mM)MNT
z&&HX^EdSNmH5K&C_$6KQh4FYW=#8-<9s*uua==5xOH7%?pqVDs90k@*s~dwhnR*n0
zwwel8gASSQ>;ZjhS~nVW+%%isw6ms_yFnLBoP_d~sm27lWpW}x-!moA{T`dFx`2K$
z6;phEH~kO}dTuHs(f(=bXA635N+NAcwdz-G1{Yf$qG-*q`ZgbQ%lamj@g3{pKA?Nn
z2j2rdw5EU8=Z~$=lEi+penzG9i}eKuP_fOgB*xh`$H{Gr&1NgmGMhIP%2hU<azSfs
zjGaJRZ7%qMcG{dN2i4fbgwo5s-)49VbPw5dm<~E-vzmhVxlKs|=z>judW^2ybfhWY
z+O#6~@7PpQ&hOc5qZ~Z6`7{MoYCD=DJI6MlH>lh;vKeThZ9RI0Ds5vaP0MYID5AS;
z6F8{G_BBe~%s;X%8G!C*wr0xH54M4HnP;{Ibi`k_j|PFJ+nu2NmfG!)2Q9Gc7*t!Z
zntGMa<gFktP0OZYGL$v19pkDSKIORPyo0PtFQD;cB+$f=NKyX2RTJp`jbavJc`+-%
zN?yWRLJ?XiE5aFk7OO!_wb^XTB=pLd`xNw6vc;>=Tg4vZSpJ-i&I7$>HASH5ax;?d
zY&q5ov`Eg}4q77PmwZ?tU!kJfA>T;^eIl==(lq}|c7fl*pE^HNc0BHE0{SkZ8;3{~
z+SZW)z}}-ta@lL*fpgeS((QUSb|C05n>h}2j-46?_kL$%P{LwEt4uo3e$OnJgKonk
zt?4tQObd?t5ZLUJBjPWI(64m0(75q1g`I?;wD3RHVOjIXq~?f~q^8IfD}hlrGJ(<O
z8UbU@jsV7PZx3t{F$b7Xhf1pRx@o{({mGu9<6xd4?*@+f%>bP6C=^)42GAu+S(o=H
z{yO_)D!LX{SO8khu3Lk)u}YG|KDJ{$JlfBM_Xn78{~#0oA7XR?`7jd~IKs$l?HCgm
z`Hay`YJ=c28x7|_wgKHoGy!@phy(ggF9VtzhD`wlb|akzkDwY4TSu2|{w28``;-#c
z`fu{LjU5$aqO}U_be<M>dxbdi-i=`wN4XA4L!<t2Qi6XC#lCT3J}@#|tpB1d+MSwF
zUG*NY7&w(Vn^6M@NH20?8f!+9tz^IS2Q6W4Q$b6aJLzjRqu*2UHEiMgptUTO&e+a|
z?E>v!75zXvSx<k^ezvzM=m4{$xBDQwKu^qZ*0~et1S{GHI>~O8fG)8PrMg{&ulXwN
z`3JMF20dr5DZek+7E0#~dB}3mOnE&;rd0Nz3on*G9R#w-?*)P?Wp@(tdU<#q&<6R;
zX3$3YFwNX2&!S|0B)679`{m=1IzK6YzYKIrK0pi3%U<SE@Kw1VspxAtyAt$`oI}ps
zk)O;2-IwP?fF8>xy6zwHT-t4_a(gdmx^kCPIY${xH85B4+61apa%jO4<>Fw_S|yRh
zw@&$y9-3VW{T7q&R*tm<eX8&=6rf|u-t4zoY*dJyw5G%G8fw8Yxxi-C&cKj1Lx7=|
z@wqIr9ca}VjYi+nE6}8roG51Y%|RvXxh-fqTZJw745pB-XR>mVLMa=L^>|ov=YeLk
z>j<_PFUuGdhPI5+aeObcN(b#@D@d~+F|QiXekN1U4=`UZ&_QNGz2XPD8CZu0;8q9F
z5f<1C^fCLS9q1Fbw-@LrJ312dDf15i9b-dj>@(Jiv~`?4r~sM&#g+!)_y>&c$xGyM
z5Hy~$gA}J3a&jPOrYzGFSSo);D`v@K=@zr)%X2|xviE$@9631(G*`Yyf}JO?q)W_~
zAJLxW@+qpk1@gfpP=)MGAzmdH!ENnQLs`UnhBApB#!_Wc46F+j3O8S@oT0s!DTnm)
zQ7)tB(0f>?7fI88xf9T#1vD?x(O}*OXbejZ17=R5O2`Y^3Y>7ZFL27xX>aElwvjSD
zUy`qZrF5yFF^z%Eypn-;<@2ea`|>)yN3^FoCK8<&^4<}k1<LW(pk+!HA}Nkc{@NRj
zf#0S9hdEKs(~`1)Z<L|5dy$&G_U+8?m^HT0?z2~<mPahL73c*UOp<uTmahgC%i%LX
zv*Z8{S}bpwPRdv<??-Wp)12$?M#F`E!^qw1l4A{<V}Bkrl|C4fLKg!&^{5N%{Bq6P
zHQwQN===WK9_V)|zSjCyXK(YZUHZR=-~2ZI;{31-@;1EZIAHSwJAqM#fxuXo9AFFj
z1r=}gxFN8$6@@bHCRK79PMT~ti2{-^n!HKu*bUe%e>AY?#s<KFD@dY)is>B~{T(GE
zt7Z!@&rH8f;bVq`0}Ij|fn!^$zzG+qk|)Mf;3plVO(ze8Xz+rDR)I>`ZCn)v_==1(
znK=<Oo4Evo%2+EO&>ZGW@tVh`l91=K2b6*Z?8qpP&af{%vejl2cpck8wYHuGYy@p!
zr?-PPve4O}&Fq{zXbXE@4%*6+AZR?xM=6un+1GU7eYTgP|A5tu1wCZ#>GAu4b*0oj
zV&_TZkJ$qo&=dBO;`TEe-WT+g?Fu!6|6ubfK&5ivUQoGwjS6X%d?paIL9R~)@v$6F
ziMT7bq?kUCXCwXmp}d+h^|PE+2zn-;>k9fy?iLApCCAgA#mZ%SP>B*g0aT_m=>=M#
znCXIRl$Xot)A^*5NWPs?LefF!6c5V9d1Vd7`J&R3<a|pxy$$rW^5JCA17%7l&}(Hr
zW$JGwU@oXgb@BsEQ`gd4SfVz}0nJl~(4H0Q6#BedtOm>iEm7}N39V3%p}fs}l{%&!
zy2sS6bnTOB$}rFw^%&LdIduT#;G(*D9q5YsNdV}E`a6a68#S^4=$`7B0lKgDSp<5Z
zz9gR>s?W&#AJjM9L2uMEq|LuoPof399tGCIlPQ!fm+}V*;N?7t;#|dtv;?i@!-OFC
zQJS-fUyBB9;cJ?McJT4Jpj|vpU)j>re1ayP;RnWm&hgPRLFf4?dR{MaxdrGNe_#!|
z#iJ+_-*H#U%WXcs3+N6XgfXf;&F^P=ivvG^!=e_Q*3&EHBI?>z!kCy<`}y&|>e@UV
z1J~t`Wo+@COrKoZ|KpVvdzcR`z?uqnIt-H+iXXV}uLz$jFdkx2n?Xm}no*$BY#RbC
zys4W*H*&59ioX2H84dp@BS^muGui?Ji{}BG{7Ik3O&4_pHalDh41Gh7M7Sd@h&Z+r
z7`21iF*#F!Ewf3Otq+vG-8lKM7y3i%j{q)U`Ab1d<=yi^%j6(Z?Q+?P1hPW*rh`^C
zl!G$BtK@4mSS8P<saxgKB#muy!6wjl*`yC_jlYMIOpnN+L7+-ymm6re@_cvg!J73e
zii-Uu8g=;sdy0D=QnCzaolvIufX*q`tw0x*3R2}&rLY<3j?%6-=$<m78|bm}iX!!s
zGMH}qixTevnyF5+rAnKv)+Hg$RZT^pd1}Q%(0uhWm3Fy0lZ*@0B)WQqIy@evt9Ox6
zzEC~b7_>;O8UR|XMm7Xl)bmsnmFlIbpe5?#YS2>kw@}bBHDUv3x#~=1yFz`0ziOEI
zO7&a_x~tSTv|E)rjtae6?b-vhTFs-~)~G)>0eyv^-9VRkbqVM)UosJNg?CE?UFBXq
zLD%?jip6zaGzWBp_YDT!<WVGuTl@&+_G_L%N%@w?#(~U_`1&&NQ(jFee$97L0;g)h
zJ3!O4`uU*S+Cmsb<P+XdRC_KV@$_4Ttk&voz&<o=e_si7w!%lOunsK3bIu1nrbjX5
z7rNYF*#S7zmXeVAk`h16+>~^ab_=24!{u^ddIPG~5v}M=8)-#~&8Sae%G}R^*(r9w
zys7U2$AnNgKI}UbI60lNHf0M1VJed;ThrO3NKhI3o%~q9{-P^c*m!TyGPWZCw2GN`
z(0;4gO?v#+vGepcY-DHbL7Q1`TCs)wVFGPsZlvDr>_sYQ2V30%w3Bt;4BF2g(Hr!e
zTB3uVsUIu?Rq|i^f%bB%Mxg6Fjud!<`%y*T<N@@c-Qor_xm~XH8xE?}_5{9-UGPK%
zUW;(T>!(HfVWk$;4vE#G>3cR>41KRgi>2?;Xf5b_Gg?dfc8u1_)gRc}fE;OY*J+0~
zybu`g0N1s)^!*sET~kz)mO$Ty(GnMwLKs>SeX&JrU)CDffxgb7b);{vXkF=xD_U|j
zvZ8g{I0V>z6eOqhz(h&wStkeBE7=#=o4(4T^_dX??3+cq^}C6SY46RW9o}c1fc@zk
zE!qJ3GK)4a8iLXW^=*dw(^4XkYHjfMkfCN_HylBgY)L6-2{VlaEoJ^t4}N-j==C-{
zUM`f9phF43rc-b&Avn7e$!Iul!39OX-bT`sckfL=pJ_Ef-~E*Qi0<%^M=m3+n4^5^
zf};14RAS!XN<4OC7hs1w^y6yBh(utgZaA2Co)H7=(#{&#wIzwPzr%RofCf5n;0gqe
z4_Zn4q<o$W9PEM1^Q`ZYL!NyYS>ieE=*ZmI6~H`OgadyEqHh87!fP9VW33Q%K5hW%
zW&CI3fD;_a--!kv;0Gz>(1)k!_{j}Oc2m}pKF#x}7N)TnT3pNy(@za0EPpF#I=iwM
zG=mN651PrQrGsX%#pKs)_V-$lxr`l|2cE;)(_Q8=rz%i6E6D~eV7;l(E7;izkj}RC
z0WD+}dZZVzNxMN7c77J9lG*MBEnyX%K}*@^bi^`t%N?|mZEXlz#WrjQRk3<BrJ8-V
z3bfkH(&mHLuqH;(I(7&0z>j>JC|es?3e=8ryc!PL#5Pc1HnTtJY1_*BK`;2{ik%d{
z?M$Ii>|o<EK|9&bp`bnN5#6kYji8F%%dXSS_OUGyppV!chz^Bowl4r5WD}c!4zUiT
zsKYF36zB;1ot*iYC3OdV%1W$2$JjVm&}VEfZF-y~P*P5?K2+5w*+3W2=WJvU=rptR
z1)X6>Y5Bj{W(wsO>`!v-0*fUreaU9WZUleDzHA4&#Fkh<m)T8J8Ga+MVL9kJOV0(}
zV1JDP-DHy}zqi<{BE34%(fnuudbin(&7eE1h$L{A1<*;~vx{v&583@)pdZ*5(?O5e
zceL4Kc9o8O!k*O!{m7nCNPcFsdV!v@D<eU_uwN(zzcQcJpx@Z;uAt{EmG1I_wIl~$
zG7s}k@Sn^_1O3Ik3PG>fFQnx+>_>{>-|X%p&{R31DX2*9Ml?-!rEO-*C&{%k`ScFZ
z0=(s*3fZa@q{~gyKnvwaa%PeIkixZC?oQ=UDJvDACGxSMX7EzEcNfqyc^utoxjexE
zv|ipY2ed&xNwVB5t5ZQ+<PWJFw#v(>sJF@ID8Ad}><*wE^6_ZUF1bHmCcayKF$J_o
zZt4N5kvmZ8_sZT#54|i}=*AwvFv*M^#8YF`$j>_B=R*5S@o%lWSXCg*HEgsG=p(ko
z9(0fe;qelyf~^rTEi@NCYGJA!Fx(#M(wdK60*rW#bZU_;tASD9uK`A%oeGROy&D+Y
z8+YlcwfKGnIxUYwYFeugrvY1EvjN6+z#FHvaYOdB`1J^h*0#(E*zVB=U_vom!1GT>
zCMEWRJMp-oB7J4jSqI1XkiG@!`2`_qsrgyC1tE#KX=Ag~a|#PWdcD`DV@N?>YFhe`
z!t~Vakc76~f)i5nhYv~49X>WIeMs-z5ryMZ^V9Wt$v*n14$Wdh+UDhDWu~PTX6EJ;
zg!Jx{+&nyC?6CAsiAl{;^YTIxa&rpB#z|>enRx~2A$eJ2M`mKC&blV~WT&R(7DPo1
z32R3GhlhqY4~-3L9u^fI6;ha+n^mCy(%Cg0lQJ@M(xrd=q*etJ3;yv_Tw?$6BmDm1
zq=a?!iqFhR%NjfUpHGT!Mo4OYc5qH^PI_>9>afg^!i=%m!$QVIrw3;TjmQhhfHp&h
zW#Zqr{|k!tX#3yT#Z&K|Z2E5$nD2jM6VHlnPXDkTP^5c~cY71K=lZxsvVLrw>z;)Z
zF9)^%|4m3pV*0SLBll#iD{HzZ^y2y^dhW!4Jy%|hv38FQ3l9#93Jq=S6BgF2d9yGd
zyd2@7(P7~qr5RarkGgm8^vQU{>8E-buU_MiK7F4Ro8$}iEbWJ}aq_i#mXE<K)DoG-
zy0aL|bfS36<uo>)^{^xlM=#H^f~eH;BhgMv>vWK0nOjR=6WLpWM}Q_+CKFX!&VuBl
zaTc$UtQ#9@$sS4FHkOakm7m62>@r}UU`ffq<SNTHkbEJ*@`kKaEy<a%ZnUfb$=8xB
zKV`z&(b9U9*nciaKHA>$%_vwUOYmq|-7J%ddRWd9O|aC@0+m{_iK;9|K=Q*b7Q1Y$
z@Uf(1!y0PYMpR{aO%!iQ&H=q|SwSROek5|Uw9W;ETILdMw0uqEW(m#{#>qtSma{||
zmil8r6D-+8<(4BvJ1w^PEQlpqV)L0lrljPvK;F8iBrUVdf<?Y&ux!s~0lc1(NmDJp
v!<eJxNj|g3^<UG><uFHBzD$L=RROb?FBmP|3RnO_IktcWV)qpV%=P~O38ecx

delta 14936
zcmch72UJzp*6v=rokJB4U8IXB2!aTRiXv9*y@CpeVxfaI@z@YVtXn-;!3Gu-Q7o~<
z8e>di)Yvt~5=$(x#pq3pzHcs!_s<yb{`ZYL#=9Be`{tT!?X~8bZ6D-3zNb{*R~C4(
zqAIVAlJWQ|LGb!?upo?_DhQUs-~W@ut%4vma0-XooT&|lV>DO>1UScXm40RrMw1%=
zBAnw$B`SqGFxp0{NSAc3(!ET=sNn)YSLf-Zk`+S+MqdV}0K2;^;X0jRGe)0v2aI&y
zNGiRO9D<Qc55Opw{amGsUxtxa3&1QlGE91$2`F$Ui=>NmNU1xSB8?ddSnEMHNb9xj
zvd{2W^B|t`ppB%-M!-cEI!6ks2e?t2>vsh}zUR`O2|_(t8I_hJNVTRy^`Q1ZsLW;E
zkChmO3=ss`-r!G9pKk-%*)EFYn@L)P;_dP@2dZHE*`%7&4{}qxl_ZC1S&EO*iDtXn
zH^Y9C?KsH29J-R6>LUn>gY!{ZSv?1`qswWMpKXHd>T;Fjr=LKsQ~Mst>tKZ9<?@1L
zzfj2Dwcn8(;11c(#hmtRw*hkf+KwboErA^BuF~D4Ia+Piht<_us!mq*iZIdBgZrZI
z&P4S-v-8BIEY3R7o$K4^ElQZpQ7umIYpjO74f-IS7Mqz=j9k$BhxHbOfb5(E!OF~H
zshJ?u_Gl&ubcVHFuLy!|uK|EQ0|eI4ag-p4g5e56EL$5aeK4y$fxoTo4G*vt5|AFK
z-KV(bd1lv%o^RU@w%EqRb`zNGA~T&a9oed{<tV9w@DB5VBnZr!)V+{NR`!B04*F^M
zQE9-O00N(nK|YgeDdyIEoUcRkLG-+6r6eTOEMfaF|Ha2OUbLpp%raOm+M6e6g=Rji
zxwg&BTdArRgn8NpGY|3AaP2oUcXm*7F!x{wv@mloBR$|fs+}NgfswoMqt?Sl?4A{N
zGo#4{H{kn|nE3wVWFI<;PX-s_$-9_%_HlCX$H}Il?P0J^5DfUK*>)_P&g#SFn#ZF*
z)h?LV=|IPH9F0nAkA?j{E?)Wf#oZ4e%Th3#{c(kZ^<Q^p{T+8}O)Y$k1G)-ATvKeg
z9jkW#wNfx6eNx5-Tm`!C|I&ZBCrys-gUP#?c=mC!=AJZ}Sr?Tr>fw0&)Lf<Jo-{eJ
zb&Mc*V4{&;(5_k-xDC@@j}e5{Q1<-z#LR!*haQ{lhPWhQHv8j>|8Zklu^>8F5b`j)
z;NuE@V}6<9@H|0Si-{e7n`A|@1)Sm-iN3c^o~4bm^zAaU0^xl!5Ld%e0R>QVgKx+l
zzM<p%rGl{Y=@x_vv)+GSQACL!{5%?q_gjCW-M4g)e7jx{Qn9M>>lK1v<K$jzlOQBg
z+Kiw_c_s>>{@Vq?p@)uj5QHW%DUf4z>$R3vPQ#jaLU9gZymTcC_|7)SnwqXug|f5F
z;c~d%b{#WxL;0BtLWFEvCOyQ~?wiI6Lb+uziGw-{!bUrq7L)^2f9rKr(t^@m+hx_j
z*afY};K&=dw57fv*m=7|Vy&(vz@xnvPODst6+W(kP#8L(*E$=T=*uxsPNJI|!tF>F
zEQXE|BKXF#GC3Fe2n#wzubhQX4H5P<uvE?=PKF3q8rWD2ogg%|(BiG@gzc;+2z3oD
z^sNvP<s`bSp`}@kjc4&jFtp+WS*gNJ4AFd`S4L~wtX-1IBA{x+RrX37gwoKK51f@t
zei*dlgE~q^AO`LEz*8`E8wJA*+4_-moB=(}kYh`-puBF3K`w8rvY?BF$}m9luhopr
z)RJp84*Rty6l=_>HF_%XJ26=2_QDFbD|67a4IA8Qqt5Cp>lb0L(JBgqhDyHnO|4+I
zTl=$?uXVS4Ozh=e>Y;dR!8R_v_QgYW)Y<_)j8pEQvJA(#nZpJ9gsp<mWhDC?2gr{*
zV`dDiiJW`~Zzw|sv&hE@vb>0{ox$vBq?cc4D{NdNFJ(cO!_02sVS8CB$7m9Byk85^
z^BkI*As9YkhQ}Dyk?YLH+!SX179&r&mG;!eHQ;hP=w{YD-B5m9iP0=($83<^vL8~&
zkk4#XjGD+RwJ_TVwo6O3ZOYuVGTTKS-_OPTpS8!rpSsDg$i5S**V&7mC0lPNYW)rM
zS%Nmz;BG8kh%D&L>fvCyS3^A2jn(9md?x^-?lrfS<$Q8ykD58X{MiVMdNO-@%u>)%
z^4VWPR`%%2&e2Za48#0@8rucAf|6+<<NlT9iy0UVsu@{oZg#c$UPUSx;+UQutt0Q7
zfl++TxpifsIYvWjR@avkDEWrgjDqFel*q$sMonb_EyIvdGm4g5Xw&T6*#NE7F2*Ax
z8s^2=kRzm?(;&y%Rv~*VL*PA!mvI`iw`WXqv=1;oorKxn6-xW%m}I>Hg1*~wXistN
z_J3+8`9gbxYft=B>zV=WFI;=;FD)ZU(9v=FxAfGHJS9|HoItt3=sY@0J8a*^xCM1+
z|Fxcu9ziRp=hZ-sHG5`a{uw`E7R{5EQAgt22>PuBnE#c}ulYDnlAwzs3-VAU_P?q0
z#DTx&1^sB`s{L&|g{YtVsP?YJyXg+!%V7rc@ei|KXpXmGt6x&JtqviEJE;EGYGcC(
zQv`=a+A{|S_F7XN>w5o$&>rV^(Jv?8exaue&!fd82zp1Yi=#&q57gv&DCO%&Y{y7u
zc^DoMJhPHh1;=JJBfa2uDhHFznY0Njtu|>Tj;?I8w%^g0{i5A+^knNb(aF!jG!l^=
zZAXbuK$2C0*3!w79nyw6)n@CoNlwAcN892QZ+8j>-3)I6b0(7g=6ZRI=IZRpI%qAN
zo4R)BjfBE%bTsl;v}(ZL6s<QwQ>@K*Zd!}x127WW`~#S>^P+RLY%ydFZXv0v;$EmN
zaSOE@R)nOploa(T(pu8jQ5^eg*W4Pj@tU=J{mx}+SS?GEgJQ9FJmy_Ibl6XjYfzFs
z74w&HjbyKv{OuLj2T73KycGR$Hwfn5AC_78D58%x&E31U!(`|iS^RC2x)!qHSF9a$
zcVZ#h1$Qr2p}lq=!T!{Scr;*#wE_=sW32{gyTY{{glk*~pTIChaKgnE;eZ!m!fwLU
zd4#)q5cb+d*r*HPg1&@4$S+0cj@PUrJf1~37;aUBTQEow<S@b<{Jx<GDO(AB_--AI
zTWH`$AHRj_WWsPK!b!n|t>HLDc!^Lcf;GB<BCLap6v1^IVG(@@7amU}oX@wm;p^XJ
zkVfJM?++*W7~lCYf9g5<mm&<rD^d~a*`aYMf~7{7+nR7)9-%AF!6I(TIXGMqtoU93
zp^)4HuPjB_!tdIIdtw-}KoQ>Yn^o>4Szk(cim&-JmE?i_2<b(y2)p@icf1562KM|&
zbJR9mgx|Lm;f@_)_;$kHJU~7RNsdPAg7d2hH!L7*zytJh7|Bcc!A-JBwnVqYVeJT8
z;PZnb*kuw%EhaqIl`y|t5R8iOZ3+#Bv?na#H&`~A<RrdbJU{YUI%(b@p%r0n1!0|0
zghzM?BJe3o5nA#if1gJ3xqQNyNWLbK@X>0*IPSS!9Y~&wmaiCv^ZjYCnJ?|hV_E(w
zX$ElHPoXC%!r_60&m_XT@q|}-PR!@Vm9!!a;~qN1O<$Zvn#25-e>jpH)R-`w`^=5|
zI5Ubg#`iqi`*)|o6~3q;55%#lq?ts&BMJ*62zzp?T|7xXy^OG|oUoK<z<Hh-C-D0k
z45i;1@e2asP8Y&q#e@^A39SYZ_T^sDjC|279`EI|X+r2hSha>QFp$u|&1%9^tOUIq
z-r_fl2_-qKIbjDs!W8ZUTajct`h+O7oI_Z^(`}+H$(wng`|yfu5y$gCg4g1Dm8N@+
zBs3dO_yt~mitu$W!WVT3V_Oosao3e?BKa~u{yXj=2OHAd;66xfK=Mlu!Z>ck+&q$<
zc?P&KlJi&a{8#xc5AdvBvV|rBxb3B#NN&`QFk%*=6;Hh*-Xxdv0^3=i<Q^e}&G-eL
zG$FYUuZvbZGXkneb4DO+$_qOzgXBvH2l9XDMjABXY4~Ug$+5gSEaF>_=d=B}hX$>s
zS=ooMoTt?-?)J%iQ>iEESG6E~Hkh#KD8kF!PYrld53eN6x7@h#s~{T%Cw|OcCz=?D
z@GF9U3SmVUVa`~>(awbSg@kjtOKVRec`UE>RlF|P2GTUJA~cUCOyGH7?o0A}UiTg{
z$<i3Y>D&j#3LfKGJP#%$(nNip0o{1!pW!!~!h^ziaT>Xw?(-<xaQEi%NGF@<*<Spv
z>-qhP45W!{O?Z?M#&#yW#Dn;rXVoDicjLFbf#mbDNiLy9X-S0jc`Q@7-f<XdW^X18
zT|pSJlF*MIS<Fl8I=|VA>7+l(^L$<b$%YuhaDL<~p28J85Vy<uy?^8(SUrOl&4?#l
z$M09gT^Gw;eWwTMk%hoOzFlDv$)kB<=9QA%Z8BjP&z|=@C5Q5z+wUO#9BvRY9<qT4
z`o?0O|9Krr^^&*S**PTda3egkl&}F$tF_!8>l>2hLLOm1?$WxvGluhYbLU-QQa74C
z%YBfwmgJLBgs>U-gg-SumSj65FY^D284VJL5jH9&tl$T~<B!?%$2vD9{g_C?U3{fq
z2a>l(5W4e7pXa6@v?a|He!pBEzIQy6j`GSn?@zNWoe5_r1C7Emo&kI7k;=e}Ct?H1
ziTwDlhmd@Vn;6MmXU5%rj3<#NKXSlST64S&;e?@tTfzxPB@+5X6Moi!usn;){Rm^Z
z4~)}z{L;C-VLF;nc$r<FL-N>lgjGB}oytg-c`QY4=w5E(M*eIZe^&OUHMe=MOy|jX
z*OxTYG6_#^Bs6l*x$;_wGID3e^IB}l-vSHx@jr1lHsX)<ZcUG^T}il`C)d5vB!}}G
z|HjjE56_IVBS~+`J$jEH(-!elgjzgHI`h(f$M><|onuK??$X1UPz4XJdV?fVg(MHc
z{j&+Dj3B(Qnl@U4Do_QND#F1t2zyT_{W1Rj%z%fW;q6?<15pn<;AK6R^f!2ic*8Tv
zxR5m6oOu3UD5phz1;Wf$gdtpB+l%B|TWIOI0VI#z#gV6*3-Uk}YV(LzjwN|HT&)V<
z;CNNgq3~2;WE$b1`GjeW>DfKp#1~6QlZ(tSs)7YSzN9Bj?}iG^M<R^oKJetTadD(M
ztrCXvg9CUHmCU4#PR$|=+(DR%0#k*rQV9o4BfQgso|?^rbxB9^ULL-TYRE<*na8^f
zTVO^|Jc<?pz1z|DzEj+QK~GYEjo*g>!$auNHlbu@`%`Ox15A{Jal^U-<Bw5+CjUwO
zWW=}Qff?51^h|U3P?@lLB5-2iV&IercudJ-{j6#4`RoMQxPWcYN(1bTrCl)C$^0p%
z``G1;p#7}=RL}vYkwpiYV{Oov>`{NvX=X|Fe32b209|5}w}O6Rwe+A;F%5l3*(lDY
zQMFi)n(r?0LR-*oaYirD9`P2vf)0yQsZwr;wnl31KZ<wA*~_G-6!PU#F6HzJsdp35
zdP(0Nv_YCeaVnE$V2Qd#noL36E=}`-^0d@_1n4`-g5C>fr1pbA=cS&s=LKmXqNZGw
z#*YF$mU>amE|UEzVJqbBMlz~WK1G)9lq;zwtL16b*>}qVf?E@%o5c`(oSZ(4&&lDd
zptvGG6G69RmqgGn@?+ZTscf&wf!;>%-54xURt*OgD@B%|6-xDH&}yY;Cg>}r3-#_Z
z%0)WuvU0Ty^n-FC7j#Qm<OjN|d_Mv7vr@hg^h8NSI;hW-)&UqTQu}&>R;%49=IhmS
zoj~Pk;T+IbHM34Wc&GY+EIXk3)99#LkOcZdy`voov^P4}!{D)MPF{Vgy3?_LsN-eO
zJN52*&`e!d<h8OuH=KINQeEya&@$b~>7bRmB`Kf{Iy<`aM%{sO&=%dV@Q_laduIcx
z*7<D&eWiOl7xaxzA{)Nbm6OXZ>-PKmgRkjMGzHzz%_Qq@>FQ~qpLD;`=)SHAW$;T~
ze{D*Tt5GC>7U(;XEpzlSpMvJ;y;1ARV*Pm9^D})sZTW>hkfMJ{pV1L?RsT7ff^tWn
zNm=)^e#J7-Q++-ntGv($B!FJ&x6?J>=pP1x-syeO2$X4NK~zLD&GKe|^3D8>;b6_|
zWCPG9vqm|f3bO@kLHo@v?*tt&n>hw_+-y7bv~SH8?*N@K^P)ug-mKaTblt2OCG=gh
zF?7F2X2G37&&^86KfjvQ3I)A3n?p(ayIDUg(4S^?DL1B?XRR@UXPDn2Z_P6QJPUN)
zf<=LDTO{@Y-L+Uo)%n1J{#{>rWKlsW_KSsUd(d->GX~HM%d?b>g_bwTY?I|?bI=OQ
zAIOy@mi5y?>nwv}K^2x~yg}P7?=1jTTMh}P&b`;Nuo;H?EtB#<M=jTq6Hi)hZUZ`F
zX{2U!#WIbS{Ak&N%)f0}JqvW#vWQ~vz_K(RRA7}ro-MNK(i^nEYH$!}u~iIpp<=7P
z6sDC{<H@5{R&A(7R$I9&rB5z<tda&{c+6@8#p!1&l`iwjYCawDht*ecpgika6yE~t
z8_}SJ)@cDX1*^*6(wWKt4fUhWree}n!QH&L<(7EMDXK*!X&X>F>mP>!&HNBZzQW5m
zf$m?w&tg12gDu08%1oAkj8F?$InGdKvor9iTF43~VKj%mflt-dY)1)3B}|9sl-I0N
z2Ix<AW*R6@>_n+sC`P)2mWV^QftHE*BOe|R-}VGmiu!h-L*fi7P2<;MW7y5@sr8hi
zQ~TW}pjQ>$xY3Vv{irVWfW7lq0aL$<1{Sf4l(%K9&tT92Hewv;G%HJldB3tAC}F;#
z`FuLi=DXQY2i$^1YQysgnHuQ!2{7oq9sDmgqCe@X!EWQB3ORv<!oLKT;jvKL&cG(C
zDVxGRTMZ2VY!oo!*ZRPw6(fL==i39D^(X?i380edbYwcPmyz`Gl{i>Qc~b?<e5nIY
zun7T9V^ir81<b!c`Cnt#rebJfy|Y1U*%b@WR`xli!*2F9Y*F_zZvAJBo4=27`}Z@t
zfOvrM3mjx*wR)8CiyUKglNu+qD1_kfcq`DQ$RFsshu#WaYvurrzBW@pemRt<fkj9S
zCFBTQHuTFKz{q<Pz$o9=z*bLs1KV0qD~)|b4|lr;KPtWTC{%uwQ}ZMUZZ|0te6Eu3
z8~9`a!v@fOTfLxNV*5~C^&W@ZSEjNM;}Y;R7D7f$XMHGTi`kihpk?f}5wx7Wp$cBh
z{K>KFSoQ$WdiE)uv5gHN-&V5BexU8Frw?c^yVel&8S|&!y^mGWF2`9$Ea(e1emCd@
zdovSso+TA%)=j*OyJ^qgSi?1-*UYB@=neal!Z}Nvyb_czenXxq5dT4aYpGaDX=xJE
z{6NLxn;cM?IJ_39T)ej#v{76^uGuZlreN+7qeReN@#aF%2~nUuzZ5^C2fh=V84JLd
z#4O69AH><kpc`T#8FO3I)7(9AM-$K^@%?ttZ{l3qZK`x>7bs6UN?BPXMNtjRm6~k=
z6-$fhfn`$F5YT$5EhXOu=^JV^RTBLbQ`sRsXbw6e{ggotIw~zr{Sd|ay|I(pa0<Gi
z8t4S)t3hiVfQ{UT0)wC9z09NS7u*R#{XaCI|41@o1`7`b&1A2wKzVFGHPl(`HswG*
zOD8H|Q}H|+%ba<jLiQfTWJG5%1!M0OjE+-wv7f02?q(Y0>>g%c4MGV}t$)V6+(G-;
z1G?^hR)Ocx0K|@<gRE;1=yP^A26TvB>jgT@N=AZ?ux9l@N7*czJH}k6f{rtZj5mJG
z4hP`)`;6|X%oO|f0p*GN$WODx;S}Y3@zz98f%xMh&}?xb-J(!@J{L4cY(5`UBxZ+$
z=8DHNK=Z^;lR@*vhqUJc@d;JlLh&Z`zD44@T%1=TmUjT1_Z7LXXGx`PF<Bs$;%%rd
zl*rx6Qt2M;y+W$ez6*C8GlpI@wbCdxZC2U?4b71AJREgXDK`_dsl$w#M3s=?RRNq(
z(HA)7lj$GU>53>bT|FXzej}-`2bd`1gW7fl-VwJYfbNM$v>p+z#vx%Cyb%|V04<ar
zMuApHGvG;nWY-@&APoLI37BY4F;A*H7Wht@MV^=@&tCsw<xTbw-cau`=f#+K$nsl&
z-moZ2iMMR;TF?x!+bqy*v7Q22Dt?(qnXy(hp*Z<z4t6^rIMQDj6_*Gy%(pxCR{~bj
zi=kbYrNG!8w!lsff1T^m*cxLmXZTt1{yn;8rw@7dA>Qiwf9-zb2mkZ)LpqSPje{xi
zLMy2f!|zc+MZQV}HlsgKDJ?|GvZ!EkWy{x8$*lq?Cu2&<A#KKxHEq+n0lW1a1MIo6
zE^zQCl%jDZ1;8;XCCb>%TYwox`fG}knb#PYon!~hZ7u^RRMNo{J;?Es_R*%FPD9e5
zgLWwe&1AaPpgiUs3Cd?1+JXvMi$KsE*1{81#6rkl^VmvC<oQfm2U^Hhjs|HA`%;r#
zV>APAVDrX<%2>=sP&qra4YZMUDFkh1r(Hl>m>qSt3O0ruy^UR`NM2!55a=Ge)*f`9
zX~=oy0ZUu~`kAF5L`Z~fl;n@teM`_|=0To$%GyxIK4X`Hjo{zd=0%_a(QOxKf%uO6
zQzC}>g386WaiGsd59$qf#M<Q3`(hbg=7BhkBK1`4oCA6#{@MlfhnPc&^Hz+bJ!eQ4
zY(O(5+X<jKQjcDsg;FkEaGm6^ir&sAq_$++my$IS7{8H4Q!Kud4w0YFNvYI7u1klu
zf_{(&e+s%Ut&au$Db1%yy_aI<f~Lv#-k|C7jBL<MSxy7ZlUvfBi{yBE-z}A6W`mZ=
zUr-6Hl8>UijY^4ZqK0);&Z29dkXs~zPRVPiZcoeOC<f=`6B|Gm<%^ViSLN@?r8nfT
zx}dxA3rekfa>f$Sefb|`(*xO-UM@e&b$fu`$<HV^-^;Cu7Am2BAd}LNT-kiNV$~MB
zQmGpcDpm5DgVrjoc|s^9v}Tj?j#|kU<*QIorP7aDc$G3pTix8%xSkfCQi?M{r<MGC
z(058%AJBQFelyTz<-P^zx)M&2xT%CvTy80=I)iR2ahRjpQ@x*3FZNs0y=JV~=TVn(
z<aO;NV2-b<d4K$mx;Exv;)?jWh%Ii4^yX6kmoCfqFkYfeUc{b;VDV!9feZhNa8iPD
zKkKy_beK&a4f=`|!O^@k*mk8GIZOrevG~>jg3s3@D1UwDQ7!tF%meygq4#ma{T+cp
zD{_FrwU+@K+tC9}_VT7uNpjP!^ogi>7fQ^i3k4rG?s|Y;e#72U+AL)AmV=gyr}+y)
z^rEa?DZV7ftP<Z*yjJ^)<|*J3@ia}Aie<F4Li~zSW2-oS6KI?0s|}8FHP)vzJt+1I
z02NDB&Y&IAlN~h&s}{}_7n|Q{)^Q8=<oDb!jnzT=LYm?UIxSr>2c46)QC41(mIr}u
zODVlUccr3kphwa*^3*R<AG+ytDY`Z&U!HD7l~yQ6P$JEheW!uu$=eo#=F8Po+6&}$
zq+BT19RXS-7e<3L`8^`4ES7IJ04<S?gFs8=F1{d>{AdHHSbjDYv`p5m1ud6d5LIP`
z+@l<{QnsM7T_vmVqfuEc|Jn${61lEFs8n7_g}z44q8eE%7twC(WCwD<_xS7vI<Fj@
z3A&(6m<YP4<WQwtQrh+eT~>yZFRm!7ia=MD$$_A2iUTFYb!8>R_6H@Bg7Tv>v?a*+
zP&qmW{7hLxA^uZYFa$JJ^{E6+SKnrWZmHQ&a?iK<fxOytS23{Penhn<?|STpU}aMR
zbO^>PmTLzOLpxXEbnAifPIS2;q5(Keq97zV%mXGGEvT_1y`gLz?!Ew+98J|a!j*d3
z$l#8^l(!>+qxLGm)Oc%P#?b!2%tqvnPnrw^emae!HsvfiVJf?o49a7rVW2ted$MC8
zdrns}vGE?D73>5xtrBLer2W>ieboFmuvg7M8`&uv&}J4(Pi$eonSm;pGiC2Kc8L<b
zlAY`T+Rnyo2JK}wO+YW@QVsM<HZ1`aD`)$Gb}7O2L01&FKA@|LH&ygCr3*E*>-Y{X
znY};_8xAT~Px*cDUEqK$w1Fls@s?4;7@kzaV-Q$1g1%>?Hl^>?sFCzN8nqdHZ$@oS
z-;PmRIQamh0udv%<zCvM)lb>LXah`FThsSr)R>M7fo<r!FlyVa1xO6F9euGyZC@1y
z>_A^<Q9IJNSJW=_#TB*dK}1FEmOm8OJr*ga_P|0x?fFY8uvb?vU~l>=i`u6GUQqik
zqTTwv#>LeB)wII^zgXZv`bLX7h`!9C4t7LBsd1BoP=9K?9YU=R5s<N}iCwh=6|-Fh
zpk?eq4rn=xMWNx-(*vX^Pc3&x3Q54NHo%5Ua4oL2e$*9$!<V=qAJ;if`Q(wl3FtYY
z8tAo`g5M+;7Aj#!C|8W(p0=Qf>y#=@e@FvH&g~5BaO4wU$3bm@vE6X6(y5{;uyc$B
zuuFeR(t*#%0S85Ez`>uuaZ22A+9$p|9XKQ!msiFfiwCBzK$MiU6go1!?<!!%W4J@f
zG}5<#m7HJ8fw}eIb!FUC%9rtLY3m7gWbZ_sCvb8LGU$^p>G)5hDea~#r~EXgQZ3+j
zSbBH{J75W#$x<pndF;hf&@9$^ASj<DB!gzN17uerbKL+k&S6)m5Q~`ac+gxHTnbvi
zk`P?fOga_%BKGqlkj9GofEF_oHR&ZRV+Y8@9?b?7GieuS8Qa?lw4D7yN33AiT|leZ
zF<(##TeS^T%3^5A8unueXswYM=Y!WVe?4deJA(AUN4^q@Ryk`i8MKl8*%-8meM^qn
z%pB)}Dp(e^t*vZ3`EMKh2kl+S`jS((v-!h7JDEybSF?6hvAftSy4h}awh3qtJA$M`
z;ToS(*!Hm!f6#uGN*Q&4IgAD!WZ#o9pR+ODK}Xn3bI?&X&IxpkEv8M6Gj9sY7pxCe
z^$9lE5p<Hx4FG+`#`OiAV)y9ruh|K5<u~jKnRbQ^rCd78$|5&{zh|#wK<C*m6X*il
zhbqHg1dgo)U14q0L08$;OwctpiQ;>mIZxNtw6!y;6qs9V?Pkzzwu(~V4vV3aeqwK0
zfgZ5yRiK~QgFMhfc8E56#9q>|kJ&3X&=clLN&A#l_5wX)yGDYZv-=c+7p#30=q0<{
z1@xNb(_P-M+GOBAn2m8e_;=>1g8pECW`o``E86=V`-Xh@p1ofJnko)z2%0A55KR}O
zXq!Uu0GT#NJX8r<h+Ym_B-SecX`)3EXt8Kd#w-!7BSA~W?o<xNq6gi2nYd<{5xiWS
z*cr4!Ttw%t6ek!!W#X|SP`P-3(sHwShgNP8i>Vwc#3NMHTg8Xu-)*AS0aPhIi~v=M
zP0^W@9pa@apq*mF+MsH&1BHH<*c{=Z&Y}jN?g0#`W5f=;)#&ezfKZEnF0}bQ`h&KL
z?eT-UnvL-U?P1GoK>JvL*@yYShwzvhoD3V)5ZM~o*aq39hUPB=HgPEjhV@?q3>Ve|
zBYvI=Y<g%1Fftu?>8Un5hJ)4S>-qv)6i)|6UA6?aOhu1VTeU>=)aWv}L~T6>m7>O|
z@RHhQ224=fE~F#d`SgQ1^KnB-@HW?22fOe#%^LO1PR`11l$4M)c6_6@$=PFa(lZ+6
zqzC4tBnPIZr>8X<pPn@)J0l?}8Eeu4bCR=jvbB(|o?1?aphj()#r5uk|GS1ZZj+ms
z9NV_t(2$^z;GmGd>EbfR=8hbdmK~=Z>D115{HV0h#<VObIH+-O<Iv!+#-Sl$!QpW^
z>FHy$;}S=uH3|yS>UDOv2nvE!^S{=rqsM>sG^fz)iP^$`^L~!O|JCE17IiWI|9fJ+
z|0H0>f0G^wS*d|(>1oM<$q9+0;zp$<jm;gN9G4Uj5El{>6pF<A`+}U5+|<OlaS_Pn
zfDsvSDG6D_kzqL$+5dauyZ_tFuO0C(AO5$`y0%Kp&2E&Nkd^bF@8R{I7p<$dwX6Mq
z5|#hQqHWdDX=iS?cYY4t(zB9ta<kGr2M<pBAjZe<%p7MDwb5_=c6v@cAF#9ehQfv|
z{#6+McTb{ECFYJaS=3=(JMW&I<-c>`+f0i(VIh%$A(2f&8hF;Ef+xC5<KT#p#%Owb
zT=lGL58Dv*J`rub9Wj0;?3p-#%`g+4-AwNi*f`PC%``5Njbjr`PZC*o{6lh75~#p5
zH;IjB#U^DqMte<tiO!fd5WO+IBI;;rm&|Di(E!t3qQj=J5ulr<JdmhwWx6<mbz>V%
zz9VTEZ5lU{brYMmHk|-tu|o<LKQJYOMCZ1q-6_zXG%2H?eP-$l5<T0S%0@xE!1Ri=
zhfVE9(@q^sOGiW7(R3F>Hp~<@22^ayBRXulKy=3BI~Mf7lnWAryO>Ul#S<wehg4`M
zn39Pen065rn3Ob7si`kfN7DwPVWw9^6HM*WLC;J}h=!T&5=}6LWq=Ayc|_Yy7l;m<
zd^16pO}RvGOkZTO0H&FqXEGlwamZqRN)bLHFEq8zVm_jq-ZUbM)nmg=b1{Qk?;`ri
d^aDtAHZ!T&nA~Uz%*JDH1~5T0c_lNu{{x>T@9_Wt

diff --git a/Debug/Libs/sta-core/src/debug/printing/printable_uart.su b/Debug/Libs/sta-core/src/debug/printing/printable_uart.su
index f3bc589..ddf2f81 100644
--- a/Debug/Libs/sta-core/src/debug/printing/printable_uart.su
+++ b/Debug/Libs/sta-core/src/debug/printing/printable_uart.su
@@ -1,3 +1,3 @@
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/printing/printable.hpp:26:11:constexpr sta::Printable::Printable()	16	static
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/printing/printable.hpp:26:11:constexpr sta::Printable::Printable()	16	static
 ../Libs/sta-core/src/debug/printing/printable_uart.cpp:13:5:sta::PrintableUART::PrintableUART(sta::UART*)	16	static
 ../Libs/sta-core/src/debug/printing/printable_uart.cpp:20:10:virtual void sta::PrintableUART::print(const char*, size_t)	24	static
diff --git a/Debug/Libs/sta-core/src/debug/printing/subdir.mk b/Debug/Libs/sta-core/src/debug/printing/subdir.mk
index 2de69b3..e1ea868 100644
--- a/Debug/Libs/sta-core/src/debug/printing/subdir.mk
+++ b/Debug/Libs/sta-core/src/debug/printing/subdir.mk
@@ -22,7 +22,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Libs/sta-core/src/debug/printing/%.o Libs/sta-core/src/debug/printing/%.su Libs/sta-core/src/debug/printing/%.cyclo: ../Libs/sta-core/src/debug/printing/%.cpp Libs/sta-core/src/debug/printing/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Libs-2f-sta-2d-core-2f-src-2f-debug-2f-printing
 
diff --git a/Debug/Libs/sta-core/src/debug/subdir.mk b/Debug/Libs/sta-core/src/debug/subdir.mk
index 83eb466..0760a97 100644
--- a/Debug/Libs/sta-core/src/debug/subdir.mk
+++ b/Debug/Libs/sta-core/src/debug/subdir.mk
@@ -16,7 +16,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Libs/sta-core/src/debug/%.o Libs/sta-core/src/debug/%.su Libs/sta-core/src/debug/%.cyclo: ../Libs/sta-core/src/debug/%.cpp Libs/sta-core/src/debug/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Libs-2f-sta-2d-core-2f-src-2f-debug
 
diff --git a/Debug/Libs/sta-core/src/devices/arduino/bus/i2c.d b/Debug/Libs/sta-core/src/devices/arduino/bus/i2c.d
index c3d61a9..d464669 100644
--- a/Debug/Libs/sta-core/src/devices/arduino/bus/i2c.d
+++ b/Debug/Libs/sta-core/src/devices/arduino/bus/i2c.d
@@ -1,6 +1,6 @@
 Libs/sta-core/src/devices/arduino/bus/i2c.o: \
  ../Libs/sta-core/src/devices/arduino/bus/i2c.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/arduino/bus/i2c.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/arduino/bus/i2c.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/arduino/bus/i2c.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/arduino/bus/i2c.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/devices/arduino/bus/i2c.o b/Debug/Libs/sta-core/src/devices/arduino/bus/i2c.o
index 65ff9c1babc15be7b7c8761b2cc72099ed8185c4..57eb1568aff0f43ac19b4b44a73101b653b9ec0f 100644
GIT binary patch
delta 3141
zcmbuAi&K<k6vp3W*-yX)6cD@+E-nTL>#~TXqnHLN8j83}R$jIhRz)<7#W73f!@LaU
zCGFE<APsXEYtm+fB6VyuHAXAc884%u>8N<gbg~)EOIGju<4=gu<Hvc=Iq&m4=lMR@
z?J_m)GHtY(-q@5ltozzNLL>(D5Mp)8rqX<U$N(YC!RBs4{sadH3yY9{s{5(fY*O*!
zb1E*?RBRx>zq@)q7Np|+conaOshA^&ScI1eQ>k1YtTMY&RXj{4NZxJ{xegV3%1YfL
z@&~G4DrvhAsh%$}biP?V4<XL$t)90?)E4oC*hs!AQDwrDRZQ-$;>71wyyjHVk)~pi
zUBz#B{t`g<!&Ro%C8I7X!Ey(T;~5%jQ^zCJu}Dl(@eFN;q*N9$3O&4l?(C^D;aqu(
zIa{G|H&*3mSyenu<vs{}5T!DEn4iE*BQ?mXN7Gs!q7G~29xNg#M#a7$KM1t<2dPYE
zsETDMFo==efKwBp@()?b5Hwj0*w74>e;rkia?2@nh-O+(0AADMRM8XSMJ`Tf0lOLf
zBkVTPyo4(|XpZisx+2(oKJFL*>*3V66Vz!Vb3F7mG5KX!yV3S$imI6#qpN@RGhzzZ
z=TlTb^E@OQjEIfsF(OIT?}ckFR-B9RHc-Ee$}Al5Cysc8jYF6dg({DrRLSYK2%*by
z8DQxJuG8#rD{SO6dHNBh{Q&1cG(VR;B6ANA9q2KNt_Ij2@2h%OF>O7|{hFFjp}LLJ
zpJiUY0}t5KWLz7=hB7Gq7&bdWeU@wdu-OMtJ9hmAReop3I{-Ha_A5BOJy?MVu%=GP
z#PT9OB&MspF8rCQr~_MFjaJXCh`f&2jy6r~wHb)LfU*LXZS1uzU3GnhGfn`)%^W`$
z3%W|Fsl(2DS;uko)5~C7f!(UG;VyVr@S;osTo?kTVI>bkH{+5p;sCm?piL5hcEj%k
zFK9IrW^}CvrN0IG9aeKsN9q$`ya~p?U~rCxQGBsXlwPOJiG5}wdktM9h#u6sh)!o&
zkb`<3s@&%l-9f&bd<gY5-3*5ouUld80_Z+NUOQKQf<)_4C<6@=VN=GJpn{FgqP~Gs
zGo!zwH=Xw)6iN$G;tT38GqaWj?SV$S6;Im1m|~pK?0PgjT7gx~i1XO6oe^~~ZbR@N
zu$v2(1=y{Q`r2^iiKndNB>70<S|$gx++oC}k*abox7Rc6oQ^mqcyH%jKZHHA*sGlj
z;^A6ATN3Um$Ess6*UT=U<aJh727x22H5<b3!M+65lYsk9*H^@fq$82&^AAJfV$O2!
zbyPpX=ipg_krtAo4}w!4TvCt739uOj@1v-43zh?!`5JD!4Cn(~=3(41l&<BPliV8#
zATQ7lQ$LlO-3U>~a_?FBj8r4qbmP~M5&8`@y9e)1JaK?hfp5MC?iLpJ7>y?aE`Smn
zaK;5P)0wk?8aMQk(65!dmXXgy=|9N4!pz$V9PHqiX>8gL>fhiYjMh+lPBS2U3=J8m
zcK=h?=MLqrqQ`WgKQXIQ59{8JDz6%`VX1l`RpmEzeF&HqiAf?bKsnQf(zS%sIxu+X
zdWJE^0y>V3?M6f^r%~L#9Q?W9xdDcMm{usQqKSwoQU~R+Chi8SXg5xU#px?$vnKk7
zs<;N9Sy0p?b<)IBJQoMyNoYAyg4RS0*M~<aN?B4AO&DYrP~YlM`9+BJH(NRcfw!d%
zG?4?bhs<<!{ZHN?mDa=tQvb@;Yr@Ahvz_X>R07h(e(5baUH)idimb7SD*0v7M3v;N
zi5Li+z(Pg%xSdyI8*XlsKGwux_Ola(Mgr?Xkgg8mSd(8GSrdDt2AXhjeH_<6ki0c9
zPOeGHi2a9PXO}#+2$LKw*Nt*(Sj|)ELYWel&?^c;#0nK7-%_tekF`plsCt{M=#+oW
z!gSg2TXRM`iv#}3fV0F`xu7E8%&RC_ywLw<RlqrQnkU~GSmZ15d#n7uh0feDlO4If
z%2My7iqgdk{9bp(oT??hN`K3FYoFMb!S?(hqh@$~%bJ0!%u#MnUamL4(CrzU=k?lL
z!s|5-X7p;YrzVGn7v~ju$GtScBM-8(j2W5Rqb5xDWM_GEQ%X{8B{sX=R#4FLB(o!E
z-2X-9%=6D)Jh$b>(0a3ZT!F{%M#r`^4}Vb$8Sct-xUw@cS{}dnZnWu^vDm%D)Z4i0
zE;QMU98aNXw6R{sjm9NUn(4M-az`8S#XT(JrHq>mSFzpHVH6i9oBA8oGJ1?A8CM$Z
O#mSbvMM5;G`u_m#7o~at

delta 3098
zcmbW1i&K<k6vp3O*iTrlauG4*A|fDcxM-v$j)J0?rHpKONyv-=K}1=+Up}2CypY=Z
zX=<5yElVv8D`W67YHCwzlUkDIEpetX9hn++ykzhBIsF6e=$Ylb=RN0np7XrBVTbMQ
z9kzE8Y(ssCy@C$JDwSvtS87kR?~TExr?XOi{(fzg{`mX*D~Hnmc0VQY3!B7$I!T;q
zNL-UDu`x*Eal6DwPJegG_Z;2Cp-SjbM~4Oel3AQ4@fw+IJ>8*tyCk;Nm8L^gC(9o-
zTx$-K?~gl5tnicAgSf7}d|#zeJJfyR2J-JFN+v!<VnMvbSG!7V&Xnj(m*`EBxPtH7
z0n{2InR#v<O;rw-<6s;_(_RU3?3QDd*G1wPu3gnqIn-+~t^;&STgk*T@*;gcfJV0%
z$rlGpY@zZd1eQlg<~04|=xL?dgUvv$RtCu7BE1KPvPVhm1M+o1E9)kitU!qqP@tHW
zX~3BuD)~FC#DgZ=0Q(pnMx$yYQ+A@mZF;r^V1h}b{u$EZ0)t;-0jFqv0d{p<-cIFS
zphQMXeJGnBj5|u&Nv4XLsd4iC5PgPlcPpJ=fOP@d9>GmzQKpnO(xL|J6%<Y4aygQD
z5b+RtjO`-zd*Pag70WQ*F6uW^nU5o)5c(cA4xmp@RB>{;62GhuRi<v23zi^ooo0u>
z!bW$KVU*?o&V^_T8P<Vzw*b+e`q{*Nuz%D+?!HC0r7X7<%|3+cPn`as^ZE_k=q{xL
z*j6j@cBeE5Hs3MkEMrPx^Ep71u<Juq`I8-Q2HXtzy~*jNr=_!(HMKxy2oJG61TrLV
zsxetobRJt>jg;@_5cxCWr)bm6Ubg`;8Yo*~d6d02;huV+p9I7R`jj&G4j@KTGZpLY
zWgRzA)XYzpkv{CUo2RoM-ahu14>%_RCSs)`ny$npPGSkSE~8Bs0G)#6Ngk+|4r^JB
z52c%deuLGdn;aa0*>7OH3xi0S*6@pEqtw6${do~4vQOidn>Y=%!m0nB1r1|NUsP%3
ziLNETlzcbp=eMz3Mn|)NVJ^^ZLf#}s?nj~u6zYx!F|e7yFF`dMEvEi`PLpZ9kGmPX
zi|gF2LWxhPx8bKnEa)^eP6Xr0BrrOxGe(j*h<*PBEHA3u=h_KcEQ9e;1pfuQg~BqI
zO)sN<QHZSd0qgjdyn}dv&RtpVXyVK;sVrmq4!Yel5$7UJH`?X+AoeV0uZjVE;X0IS
z`M75;R_%|u#sajFypNUDLqI_(8^T*)KMK{m0CyelVoorU_Ccb?6#+3(cbR())myMZ
ze7uz&kZLBt=|#5w9wNuVrZ2oVLcqxqlj%8%hkXgq7a2B<b`Df&V$3P#h5={_&<|0+
z9Oyd{Vhzjf9L$B~h&I={81TG#n0<$%O$(lAqVx{d`x>~bSX@G~=sJ-VtU`%h0DVBF
z7k!qohlS9~N5A9DT2DR;rR}KxGCiM-gU4q6sOS48P(Or6g!NTmQqHy~AZVHihydQ;
zYLxS5{1~9$_Y;V2*1Zu`W?Ai=Y36W#MSM;<T|&1oOp*YUN;Hn(Ru!jb!QkfBBaHD1
zG-BA;6@H8V;BHU0u>kye;JFTlzv(tmTg6bJ5u^_2V?*8aml$jP=!`Kx(w7YtuU%rO
zqfkmg(ITyrp&sD5z7VcP%OM)Hq4qF7Bvi<hYf%h!jLbypceo_K1+n5#{U8KpXd4)6
z7Q_M&car(UANmhNeaV=|di91H$C#0s^1V(2GE}4XmhP@Uh8m7NDzrTeRjYX$DhdL(
zc{+vo_%KgoHf}zueQc;h?B`<?D#kp`c2f>wSkqeVOGDk#8W_sW_z=d&=u$(C)KVL&
zJNEB^om2FwL)myDK9pO`YR+jF>I3Bn{8=D`&XgE7MV>}@z33Csl%Oll>;HbrcGfBl
z&dJVuF4N;Jt?_1#A6GMRdgg#qZ)I)u<jmS?S8aKztE#$sQs(sPno95FapOyM%_LWC
zskheKa5Xr#U7!DVSI>BTYFWem&IR@m&w#>`{M>?~l9Gh%o(-dt>-`$;r1lB4E@wqs
zxmoM|@`n~#^P&?QVteedTUS$~8ro&A_OtSmJ2vd<?J)wLarbt)d-rrVg!G#oX***r
z9x>hKZ`q25*@CS?9W$(rI?l0Li_&eEtWKUJM~)U_i8auZWIJX}@TAy+ET4}3tZ#Ij
WY+doBwBJ&w)K;y~e;>VMKK}v?W|Ncv

diff --git a/Debug/Libs/sta-core/src/devices/arduino/bus/spi.o b/Debug/Libs/sta-core/src/devices/arduino/bus/spi.o
index ef18bc621b78e9b5020192dc274f381abfa9c0f0..b9694d8764ae8f5e35f166c7a5da9771a99b9ab5 100644
GIT binary patch
delta 2988
zcmXArdr;I>6vyw1`{NBhc!_9>i-Gc37LkD@9TgRA^8qMAI@`Leq9W+BXgZC*(PDh2
zGCvyAEZ>?5Q?iy8sX0#3h-QwMG3KMu@-;e@FRCfK_alECew=&mIp4?m?XqLPscFAy
zlf_igkeC)aqmK}YTZ4ocoYF9TLh6LRLYPI1NyP*GR9vd5SV{g=sCxdcn~KL9&c^Ci
z(kr^F#N<ILZX|OdPCegBQ?aL6#f~Huy*#%^s^^arRGb%};t*mUw`TWHnRen1^6`l(
zbLd4CAN5!9!9W#P={EK2{9qNY3{bHwRmFn<x)H9PpJl2Tldj@MAdaKyg%?z&h0|uM
zdhXzsgFc~fzX#~gd#ckdj9gEj51?^8hN3xP>e$KgS{S_EOJz!pXQo*F2pW`1fz4vI
zQ1L=<756d54WJAN3=3BIm*D+Rta|Q1A#a3weuC(o7WLeVyUmbypk*bne2_mv&v;NB
z)@jsEY>rZw|H7bUK(9v9Y%Ui9T?fidDq}-beIfooj8@Mf)L5`!0pPlzx0w1@(C;*g
zu1it%xly|MwT~80z&?+nK3vX2r!NsX4GY?cN8##V*@^>Ihu5eNLgSwR{R#GUv8bIG
zbd)XG#_0%7H$@0tUhYU%E!KnU0?t*(sEq6;qnpx`fXhL&EQWnZyQhF?f_)^nDq+7h
zUfr#y+fvM}r)C{gYdF0q^SW77G5F66b>S%TnkcoxW(ZzhWsC<lnRZoaWl3kF$5lLT
z0$d1W-s1EfdcKKGze45~gHK`cP?guk&$Me|t^BOsC<KoqF2bk9_&SY+>JOC3u-uHV
z^YFL`=$8PIM4xH~?*T**HTkUG8f>jWKRrBEvB_uM#;}ID@J>VUHo!f><8!o_Nz+EQ
zB!u`7*{`F`V+JpS-*#MoM2B>0l2Q6?px?uq6FO3RVYZF|B3uF5&xJ_&;b#^mN)K_Z
z6>xVjC5c<t;CCG(n$gL@$iJavMwJ^8s!u%mT>3OpUlnLXXbJiihFzxJLFBbEaugET
zQ7C~WdXE-fJ_%}YbPn~aIQ@Z<$G97ZX3g9k-cyY~Kz%(u%h2g%KztF#PDX?AjPaRf
z)o)_NDq<q4RKWNwE%E{SErQQw-7ezm?|e?=Q@;!q&#)i0DCFmK1`3_zoq9~1AF05V
zF?~4QX6dZnUZmT}yWYThn(?&_PIursoNIsZLPoNxy;!c90QFE~<&A#~??#l)fp7%u
z1KEjm;EtnDeHfC4Bay@SB`~)4E(YI6_D!HZZG;95(!Yn(T{z80<Q}kzgm)zbHdqwD
z40;Y`+s*@e4Z{-Ywgsi9GGzyI;{X%@^uyF!sacK?Z)5I>Fy7`wL`yMF1P#;IqD?Ej
zAFvZ2QM!b^@nk3{?_yj%8V3UI8RllAkp4Ua^ez-i;w3oEX*sikxEp}djbx_Lv#vh}
zyZIvpRdPVR0Umpd&B4~*(*Ti0(?;sI8E1q0g?9nn3;Sr}Y49LDmaW<vqCn?zE0Ses
zVPrm9c5<sPr*oOr#Txv}0^DKlZ8TesSf6rwjdySbIEUicZvkq`E_U~!O$bdy=%fzG
zV@=%eu3{SpfpQHr@di+Gq-C0zB2Cmp3i)z2>>w%*lnQC$mZn<ohH57&PLOxyEdV{k
zXtR_<6BT5ts4q{~)wPl6v>GG6hSPY-Mxul3N<NLc@jOCu)kHj*d(w1GxEP}WIz$fE
zM3WpQyUQO<<jWefxF^?N6F#YgCi+3(eU@iH6km;H^4Kg!u?^?s3TvXBt=b}0k^kro
zP_dISx7mgt<#<i3lp1KlPQF!Iqlp!=QWJNjahkZyns>*Pix?LoJIk+Ilq=^o+AeMN
zCxl&!_Gb<#>=xr*xX|hH`Mh&y)%iTNmaNRo+{`?OzdmVIKxA=A!DwgUq~ek>1x}~M
z?hj7+FDQI!!4&7%QR7QwCMVnIW8WD!equ>ZwsUlfdyvI#v05z-hj2Q_I!cU&s6_u&
z`<ZTIZBuJK-dda6<*llzwH4I3>lS#beYLit(vm`3?LwE^<Mer43v8oDPD~%|@>V!s
zt*NN1@;HlYX8V@7ydGPDXI9-De{1&E0DpCEsuq-I&q}xFWM&#WhnE@;CWo|)nBL2j
zWRy)=Vk$AtPnl$zVI&q!GF2Iiii%C4#y3S)(^BJ3QL^cn(X%+&^vK8~x{8zIzM3S&
MUW|Jlq+k5}51e<2R{#J2

delta 2934
zcmXAqdrXye7{`CFcwUZjlbZ(-R0KuQ!{I2H2-6ZYMHW}Dsd&Q+S33tYOMMe1FRg;T
zI*eK2D7=79J;iFxbZO0n<jBm~(n+WxUN$YX4a|POkN)xO=X3pjzt8g?nh$C9hqUSu
z+Jc&>@jlf<govuM3Q-kWvmj&K)}caJ#3@bL)<|VH>B^>#QTCjVvKRU(d$Xp^X3Qsj
zTYu%Sk5%?09&g#zBCd~DHqfGMZ;Y}o-mL-ZeKA7WA}?hpVoSr+d-Wh?Te0={Q=^pU
z+-PM74_8+3-eNe^e~!l~`+TIblg26A1fWho_3lYf*4M6V2@qeUX%CGK6TK9zqQ6pA
zMjt!egGMQTOQ5n%yesMR2{d{KleETHh2J3j9SoKQDbFVJxn?ttp}~A9utn?=%3cmu
z_5x#G29OT~QU)mh6nH!6^8|%l{>uLZ(R)XzcOtb7kk3TRrNGL8{9by7gX)oCQw6sP
z91BtJp)@@J^mmalj^fRXTnv<3WZDL*{8{WjVX%5nC1?6D_5O%H525!a`E$_kEQ+q>
zUM7baDz%XoVQjI8q!fyi(WxUw<-EoU?qa`&YbM8*=dGe!$akP|H=x^D-@hE{H5T+c
z{f`q}PPE!z7_#_ItZGpSuFGt$2{y8u^jDGEiLjFpEuUd$Y4;QmcSBWXCRKZ2|8qFC
zblb#ozbEH?s5TJ2BK?L%tYC0gyeim-yc(&s@Se*qZ!o41Hlv*?Gnymag&sH9aWmi|
zAhVt5c6x4RO}8O4l&|kLHc9yn@eA#mIV%sRw~E12UdYa#j<VNG4r&-sT(GQVuglo6
z1L#))5ksFc2G;@Nzi|rm5KeD5Ypp>)qnom&oLeQwm?3qS`$q87fP2D@e_+fKn(pnd
zat2}(sJe+ZJq$hozt7luHyw&tO(aS;0{tGV=`)aeEzGttK=`TFw<t*CXG$aWGG%Rm
z^Fj7-s;<DVA8K{HxPL}QkpCx)JN;G9LHHNpZ=pkpx9P7(7~wEzr(F~BMl*6168R%t
z1V{8CEnNH(l(W$_<nJW<7!^-b8-`|ksGS<9#vdX75Iq;7Qvo2p@#Q8%!Fa^{N{=?e
z;Bg*UHdJ|!Gi;;91c3gC;O}s5r(k)9--!w2zm19)xsP=ybcAR%ojduaY^=CAK!IDx
z^lZBAFc7nn%Q(olUc-4Nv)9kz<b#Y;DGP>o6sH=*aV-JpPW(xH@iqvwv(`xvPJsP0
z$k>6qjt{%a7fJn)XsOxZZ3{ln;0MTl3hehyAM04-Je-DcCB=w52sQ!mo&kXqu#Bf?
z9M{$k=q84x(d{>s-p!PH=7s?%6zE@)zl@x%2(g3Z{_V@p$V5cTFwa<1j5TO;9o`SQ
ziNmCpayPHXE2;OfxMnmS3%Dqhn8#%t#PbKx!^v3yz57H<m=%ZL3#A+J%%i7u7~5^&
zKZ|+0L0u1z7PEFhbZ{mhR@3xb8eKEn21NQ@0lEwJFPTpVj5YpYp>=%l@l*wH4Cfh{
zik2-@1rlv!))lIr2}QM+xm{>>3b8&Qs-gNea3-;_J6<Y(Keu~Vo`f#^4O}N>SQiia
zD|?!Nw>$$~yakjZxiVe2WjkGr!C%XTwV~oDsgN%I;@W<KYA-5g$XZ=g0q8l4PL^`$
zVn3b|^0V!RLbL&$j<TS$aGEXI=wc3B_ws8rjdzaZs*6|f+>=Y!#d5~<No{m7UJlkp
zvm7S7%YV8^l{psCk)YlcQVCr|Lf|yVGctrfjaf2m5yQELOY($u(P~wmj}fhVq<UXt
zOc&SCCCBUHjMP9EPW&es-ykz}(I*$Di)Wm9f0ok9;s(mj^6wzZE#foUEZ6FZ@Vy$E
znl{BT*InpxJ60}tm27mR7rKip%GWz8%Iy_v3+<)l<z<eI<*s7)`sFJNWlovBqR?I8
zmU$~StnoaKn%&QDZhB6^%;~f93kpU|O7!H!?DX<<$M#xH(-~^^Bz)>MGc(_;35oJt
zbYAQiSWu9cpPp7QD=RO5M!KwUdTu1vd6_9O5oUGJU{B5DAl;heOtw3d6P;$$)cIy#
zw$<Z1Z9$M0W)|jb)MlC2bF#E-)1I59Ei<>|=4qPQo*S)|n?1R)n#YXHi`BZ!8Q9Xi
PSj&klA-*slWe5KcN*smw

diff --git a/Debug/Libs/sta-core/src/devices/arduino/bus/subdir.mk b/Debug/Libs/sta-core/src/devices/arduino/bus/subdir.mk
index 0afc95b..7b36819 100644
--- a/Debug/Libs/sta-core/src/devices/arduino/bus/subdir.mk
+++ b/Debug/Libs/sta-core/src/devices/arduino/bus/subdir.mk
@@ -19,7 +19,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Libs/sta-core/src/devices/arduino/bus/%.o Libs/sta-core/src/devices/arduino/bus/%.su Libs/sta-core/src/devices/arduino/bus/%.cyclo: ../Libs/sta-core/src/devices/arduino/bus/%.cpp Libs/sta-core/src/devices/arduino/bus/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Libs-2f-sta-2d-core-2f-src-2f-devices-2f-arduino-2f-bus
 
diff --git a/Debug/Libs/sta-core/src/devices/arduino/delay.d b/Debug/Libs/sta-core/src/devices/arduino/delay.d
index f753389..73d46d6 100644
--- a/Debug/Libs/sta-core/src/devices/arduino/delay.d
+++ b/Debug/Libs/sta-core/src/devices/arduino/delay.d
@@ -1,6 +1,6 @@
 Libs/sta-core/src/devices/arduino/delay.o: \
  ../Libs/sta-core/src/devices/arduino/delay.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/arduino/delay.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/arduino/delay.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/arduino/delay.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/arduino/delay.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/devices/arduino/delay.o b/Debug/Libs/sta-core/src/devices/arduino/delay.o
index f3f7efd161239d7d43004c34a5d0dc48849baf66..cb455cd128d3ace9d1a0ae6017a37419d783862b 100644
GIT binary patch
delta 3093
zcmbuBi&K<k6vp2L_Y-uv2<Uo2U0QE|xS)bDFo~k(1yp1)Z_I|UI+BV44oyOzmvqcA
z2K?}nX6iVVPGrdvS>t$_Ov{p-(I~ZxW@@BXI(eH+d(W>wp=LV0ocFxvJkN8UZ>M#Q
zwl^AWbuQbS`nab%H}_B~Ziii|wS($Q3eC5BDP>npHi`B=689PskCV4M<otP%#Gbt+
z4(Tj$VMmER-Nmk!Q@OH(oEzgM-XN2x2iaA2lEf}lj_)t$a?VDioDGwvrNQ#YFk*do
zIUnZQ-9^s3$k)cnIc%WBseL6*93b(EM`BW<#5}je4>`XJpv-W|tV@wt4wM@}e3qUb
zmrpJ-xQ^>5=W{$e`jnjK1I`EP@F>ZIG4fX$eFcwhPRZ{>r?XW441t5xpR)P{In8M5
zw}nXMIwdhNMq*Fk9s$t$1j*EdO56zfeEKAV;Y(=TV-L9qu@;1($x{DTgv8@aIRp7<
zy3GNV!=#a$Xzwbe1+fy_XnhJwbv)ih%|#w(QaQ7eR90b$N!{c;mzrv<@&$doylsWj
zB;?CS(CdSwzAna;|FqMh6zruGE#q-LIt@X&UFea)9uC5_7PoE2Z68rzP33TG(Ag!O
zAK={-`V2;u2T<CMN!r7esf&`q(iL1mKsf;$-A&&fp)?h6FCtnk!=h-HPNoC(^NGh{
zf2XIsU1OJch~@r(X07x;$*of_)U>O+>}fJqjbTGGDcu5_cNpVhj2|{11JsR4FQ7^q
zp7@=bd9Yv2ZTk=zf0#90h0I94zP=EslDw(>L#3!g7m1zOQwt(*Af85>R`%Ki#OIN{
z5te^Ye`2t_-Jc+_N0`LwXo(*%Sn;ZanyuLRGV8d4qUHh^Z^dpq_+A>}y^j4&1zb7;
zCSs+XG;P2oorsfobqQ^90n`S|`%tQ(!x~nz9i=Y;y(f!snq0Jk@j4hs!{Et(8|7!p
z#umfyfd~5(BKrznWe~lnWvBid7BrnPMW~V)A$sf~-#|Wu`u96pNk*)h3WE`#yM?@N
zMz$c)YbfMHgE-hU^Gi_1M)y&Firc}ozRBC!d>5fm+KdwWsDDV$11#tOG#)vSVlh7>
zgRFCg+stI&KLM+T7T;mR)3n$M;}Zz}8Fov7We#@RO8r?>?1z!RCLcj;rgLwWn@6+(
zsEO&@=+<T;jt$<sgG9P^9A3y?-3%BD*DXBD#XT=z)l$q=2+(8XO;)x50ykN!AHu6(
zUySNyz}>@langaLek9tvF~k}Dn7JODcM}^7uo6Pz%>*coX6c`z@d6e-9~T}+lpY{o
zLd#XikwDE=X4TN`HbNg@$^*vE0*?>mVbm|Drj2eV*{##TgBmn@#riQM!@P!MPNYf3
zBsVBk*yb2;H?g;eNL<VYDiC5Xd$>bpHhmUSQw_amkgtVV)#PU*^q*v=)3dz~7kl_)
z1&gi)^>6S{R!gWmrU?-1X&S<p{#RG)R%mRPm$jaP{!*)3r+Bj>URM7-vN!N70yBiO
z=mx}0<y958#~9}2)jt?uEa<XWO&h<t4sJ7$eI-C^k@s4#%z8|>DcTZ-3XdXnQ(qhE
zRtJf0>r5x7`JR4ks8TJjp_=ehU!<$if*2|R!JRP6MYM?;w4wGfenz;ADb(x@b%@M%
zyx5W?`PWh95$iY#f!%uFhMEVld-R-T^2c^9siA5~4bdOJp^6wY*CXebH6TOT^)TIC
z|6?c<Se5!0$WWD<x1oFxxX&l@5{5mkdE3>S*tUy9YQl7l{@)%H$^_Q=AX6@~SW~Sw
zprI~k4GfjScqilUYTkw#r`Ket5%_!#zD?1$c9p}oP=j(!tmbcRH+`Y(p_c?g_-cs}
zhvXZG{6zGL3b=H|W&LlkvR$<Nj`S=~L507(!c$ySzObyqGp4L~*&_eq$_mf4=e*-R
z6-$bW{k}?n(IQXwsL4s$Mdc;F+_I8o3;n+QvU!zNMdkj$ImhU3fqeJ)Agek(Hn6|{
znqcc}YE)oYd~|47!I(VXxX}~5KA$UXxHV(w?(P#Nd((#dvIiB%yNX?Iw<{+{`F!JY
zyw=XHae>~$nuDhNUqGHQ{<+KM>#lm#RPQwFO!t_;lhm5vz^3#WMo4<f(4>^K<mABJ
zk;|iPzgSE2t86h=d;Sz#td;JaV#~B%)p3J$-kWH<YK_W@wz?NY+OxHU4OUWt+xD%M
jS1{1tD@&>2+}0ID+NN5&b#BEdrAo+M(z#~qc7gL>*Mg<f

delta 3052
zcmbW3i*t-u7{<?Te4pGS2}wgLtBXijYgIG0GAa?NxK@+YHC?JZ(YUN;L$t~_+MzCO
zDn6Ii-JpX;sh}pKrX!S6szco>TJ110C}ujEX=!`j-=9!3-Z^{DdwHJceRe17>l};g
z9Lrsf!L^<G#@tR*s?!ETsit<dua{X@J1AwSeGZA49VPBCC4SsZq7f_cq*G$<(-M2e
zNSxMMVnBB>)E+u4XeH+*SrX&YdDVjq<@ZQTBs0`S&Xt_aHgfJ}(X=8$K0Hf2{*;`L
z@a#^M^Jeb%c9L^Oro_q&i4(d?yyBG@-CbhXEpY|s&j6GgFE{gj5~l#=BoJSu=O|Y|
z9(+6x>@4RCl>PdQoR<J@5vb#n<R*iW*J<<}Jc?80ekVHJBr^rxhseKccXXy&QRJ_U
zl+49SV)wQZbAh`aK;_wTGcQWw3dp~Y5HEw_G&CNuhY&*S0O7xo-<}{<4NTb$`3Llz
z0IDL3MtMCX$!I6BngzAc`WloLQG9{SLqN$Tb8IyESYmOCoL7^x5v$yx&k$<QLTM=S
z6(Q&`EVR6>C1uUD_yFt`B(0&i7M)5_?kIYcv4=x&t-)=paoZL0w~|?i4LmOC+=6#~
z^cjIF(Y$_zNt)x8rIYf(5(6$LP$F2I?xtUFkUAQ0a}aGW!}`$9&rKfew-Il_zAMIG
zXh?^{EVn(cXX*cUd$~{53$+Y&r<Z&vU|SE7cP#S8z~)=VxEK?J%^rZdG3jGe$-xu9
zlQRc?@A3L`Pw9MwHQj_v7+84_sFr(6jqfc<tr8{1u&2w2{5f$K+BmW84j@iM_Or0O
zPyXQ^Qo9W3X>oFXCt2cN20sGCIC5rTy&J5<fS6T?CmXQaRb)Q`?_KP#5O973?1Ysz
z(R3v)i6$<l>KC*b4xkoT{t2Zp9gZS?ElN9CXnPh>V)1YcW=&wshe0k)*TLJt7QK|^
zbroh7vd^Z<N1TmXe)3PVpgAbiA60S_r0Nsy4|1PP{+`yh$4s{>8Rh}qJ>+#W@-n8Y
zK%oE{q{3!DzXTyRx|94<ypEvtU24bky|_i~YLwVXeg|a#f(4z2#^YF|n8DA8VP7!a
z)=a*~>BKOq{6*OrTGYV!8w9_E-Qr=H&!%h0KaYx?G4gTl4dQKjzQA(BL^mY&F};p%
zEf(Tjr|A}_NY{+RYuT$}Ksj93P!_^H^RQ|~lH`{G^f&HnS=llOWTA8r!rNd!7S%(*
zJ<j*yL@bg9k*HxsWNNaDdoRw52lQY&J2K01L1{KiZ$#raSadlq+yeeIkk6#$yU3AE
zPHV7j!c;vG<tFS}7&{I;Z-P9I{6iqWNVgO0c4#aGAEDW&_VvhqRwL{7BTX+%a);DM
zIPXi~u3~R4zGMp_vkD<jv4^(AzVxYK4SS(C5&2FsYa{pL5!#99uh4U1M|f=I!+y@E
zLH!sWN%p}gciSC+I6_k|AbctIy{Pm!A8S1YecMin&az(O*WwzoFQqI2Gq{+!5;2pg
zn$GJ#4D(U-1Oto)?*LX4jatprmLdBBfYu=Itq8HrA9Nd}En%woB(Co2XH(s4B{9uD
z7oBQ-uZvApq2)EzeSSXj5N)0o#8lY`-XCTmL>r<(o2rSQ{4wz|rdG2z)dOzU;l(<S
z+@C>}j>!8p1h(jXn`$e>B2jUT#fRPcgQ*TMre~y_CoyJ>SI(O?AX6E7nC`CsnaToI
zh4z7|sx)s?1t5@ySKh|3jheTi=3?8#SjmagIr`5Y6nYhxTya|RFn~23)smVjRRc1W
zkMVJgPt~cW8l$B))mXke6Yy=Oel^rEz6%W~w~y6a)^^hm%80rs5aQpGm~dFW18o{a
zpQImMI^&Z5AE6vS*uhwT&cNrrrQu*@*gJVr<+N&VK`=bEDm2qu74lR~33{f7LNmP8
zp~|V@nUf|5b<PY=RWMu?uD>3epOX9kYW0lQW|h}xxQm=|r3Iq`h51D#fq*NgPyPHZ
z%OdJKWF<!>6^$s#=@S^(ZE}`tvdisu4I5_n>%FD^VeiY%#6Y09q+noR@W|qlK?S<d
zSD%oxHo~6LCB44RUus4^=kt4f{yx6?r~z}69p~(Y#nldFKPevRh_r{7jC6FfH|RLW
zzE{%S@spicoNV_fZDaVgN=xm$Qn#bg4why*TH7D$m}?)<ahly!nrUnvrPOxG{||YX
Bmj(a;

diff --git a/Debug/Libs/sta-core/src/devices/arduino/gpio_pin.d b/Debug/Libs/sta-core/src/devices/arduino/gpio_pin.d
index b9cbef3..6ca8ca6 100644
--- a/Debug/Libs/sta-core/src/devices/arduino/gpio_pin.d
+++ b/Debug/Libs/sta-core/src/devices/arduino/gpio_pin.d
@@ -1,6 +1,6 @@
 Libs/sta-core/src/devices/arduino/gpio_pin.o: \
  ../Libs/sta-core/src/devices/arduino/gpio_pin.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/arduino/gpio_pin.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/arduino/gpio_pin.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/arduino/gpio_pin.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/arduino/gpio_pin.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/devices/arduino/gpio_pin.o b/Debug/Libs/sta-core/src/devices/arduino/gpio_pin.o
index 5544a8e08dcd246d6e4454f759a58b6bacc37c20..d06a90fd1978b64e7dff58a7c1613452d5401c89 100644
GIT binary patch
delta 3097
zcmbuBi&K<k6vp3=Wj_IdRS@w8qALL^E-Xr3#?m0cOWwFRI_9>(h8GlrWgN}s!%Rn!
z8tv0UEe);llG+rO4QQr0PBv0b;!Kp5m(&b%Mkg<grM>6ZpAZAbm-C*>^E~IgD-HXM
zefx~{Nk+wne#1M@@2OP38yQN?O5ISFZ)NpU$`S79r1V#4XsB{3{XM(4*iQ_xEeT?m
znqrsXZ|*GTuS3M1=_B?^gxJx#h*SBfkV)i<Q1R5JiEYGlsfV27)5Uhxk(N{SNtR!#
zNNab=`7lN2JLH^&%_A+?MLg};_wbi!^iFl@39)8hv5A}ydE{&i5}WK6yO#5Z0J<F|
zo;NbJwbVGU90g+@MXyq5tX!+RB)5^avA=i{&?5`bC%TH~66eFzc^4X|yNiELq}W~D
zHb7uejCg93#3oYHP78^&t`8Q+f-tdb^c-}_Sh2TgXajA|K=F9P#pa_xI3=&4Rc*BR
z?=g}PG?_*21$3B&sto{qA04h!vnv3PTk(?Ij&12C=gt(Zhv_y1EhD*@mLCD-4w2DJ
zKA-I{VBLclZ=%$(sFO<WYs624^-Q#FNtKv!-7NX1nG$`$KA)gLB<CSn2qFd<hHHSt
ze-76iR<WGLTS)v=BEwQ7<`{!~V95D8qf)4H8cNf+-4?AZeH{vx-rzdR441=3SJSsO
zg#OOl(h)6}X4imw3lPn55}82OGT86#C7xAOd!6Ch#B7J^E8L#ee*Fec>G$YV{h8Kp
z$m=3>0c>6d^*P!EU~?3pZr1exs@!D8I{`Nm_A9wPGDIp@Gp4JMxl7}7JjcP}x6}f!
z1U0i($5_2OM1BF=h&Hb=*VRCb14;=jKVYs~Sm9TJ{w*N9)CthI4G_bLsbKZqW~_(M
z&l){Q+D~TP3RuHhct3^U#ej=Iz{iv*r07PrBm!%YbrEeG0IG-Iex|;X3ZocJB}%^q
z^bSVTY9aLwn6=R0J`6r3Awhp$>W>mazaq`S`eY(|Az3bLDr&W$(@zX2lK5e$a+@c*
z2mb{8=c!QJ$xb)>SRFL$47wf2>!xKL68TXm0}WDOGmlS#N+vpo_^sStM#UrK4(454
zAa@c<>><9Dn&k{=6(Cw8*-1AT|F+vqw{-_eH({rt%0AYxl@b*&K8fI)SvMyvlbCb`
z@oS<)xgQzFPW)H+B$$svXL(bd81Yh<M3&Qi5!Louh<T2pjlA{ktY<89y$`2{aGgY&
zgY(m@Y7)!!JV2M=FJNS&A+Q6bvmsmz`zKL-0B~pWu$M<7X>TN2{$^Nw>_Pheit0On
ze%>A!mS#PI(gP?hMdL)sBtW|X{D&Z!Ov&La+b>|=O0O)c?Lz2sx*VXb3p`mMKTdom
zG4<%sz-(J1dCb$$Y^42j*eI(RX<DIum6bS5sL9%F8X`(>Vs5QS+!Jtl2(g^S*p0_S
zoiW6Cc>^)XS4Xd@_`4$X2|UHrJd()8PJYQom0VDN0gpEOvv7CpYCw#k=y~Gz+Bd@!
zqEcC#TG*%9-6PVhyflHkAwuk2vRv%KWm--^%W$$La=V0Hsbu}b{Cg6456$Wk>moaH
zn<uyeoH<PFnnSvLPc^sR2vbGJ;5w?WP4!2p*!%XGh<K}1kIYnk^)i@hF6-2WW?5Pf
zQ$1w0Iv~~$%_eBjrt;A~Dq7maYVxM4!c#$f9g8#tQO+=pFCj2PLpN0)h<%eRxn2JI
z54%z;YN`@kk2}fPPn&FyoTuwinyOjvkgl%3Of^-<=s)4~2au_PnzyOCL0~_tlEJ<<
zYTo*9F}C)k-d9r{XN7j5P#0jehgfoPkJ;zyg*DZBt%0dBY2Tp-VX9M_x2bw*skL$}
zbqphLYH<3~l&6q|a&vh!-|21B7s?raP#{Fl5bJtLo<Ns%qEF1cBpq>G|2UL!$qq!0
z7~?6b4pdcpO8r$8mDQfy%F>#JfknY;&-59E`JU><{?dRi81OIj<cyu1p5w17^F3Et
zR#Or16;!?$T;i_^G_^%OifeMY^Fz9qE?(^O2ZL4fN@{|E>LhPQ#_)_0lbXts*Ew7T
zg}FJt{3!*6&*u7kNtsPIQ-_8}73EIzjeBN%q4s1CwY}a(JINc@bk_Sr$hiLt%aa=@
zsVQ$dJZy`jsd7Y}88#x*o1U4Sk<ny~v0{xs?G*(}i~;sv1yhW{_V~gn#w2^Qw(r<C
s3I`b-c3hF$IbQ3w#U5ScHm=zIq7);=UaReF`(thE?RITX*hX>uzfH%V=l}o!

delta 3091
zcmbW2iF1u-6vp41oBL&Pv%9e-5;q|sH<2K<FHK0IQO&sNk}0>5UVBB87!1=dDOxSn
z@KsS;F=|?2aMh63P{kNyYbleKptk9t#@-o4-}CbyG{c!U=RM2wJm<V$8X9cN8*KGS
zwl^0i_iC}GjZ(=MyD4S47Qb6)mL@A@53`3T{SzD<tQ<=Jt8XWEhfVB-1hF#>v6Iup
zHntFZBuMPN_F}Jui|wzAIFyeHek#-ji)U22*q`yZba#h}@Q97kk)}iCrOGc=q%}p!
zxtXF9?Q-spoz+^-HPK?5uwUb!tI<2u{Z3-jI*9GYc}td@o4bfDaEl$=RqSQ}-Hnj*
z+-z-4)ekJIz*s=hkR-W&Nv>6^6tQPW+tpFd1JR=l&<A70bD#4L>a2!FSS#_5c8cA@
z?J)>Ui51U!>L*guN)K|H7c#^>DOBuyJqL%n949s!<Wqsx7cMzr;x9yj{*(*_PHm+4
zA2E^?G?@+9)96r!s*3<vhYkm+83VxQCTLxN_@Si~@-Tp{l-`D*Wh8$}%Y{I>M`R?E
zFEk`;K)l#uV!VlRUPqloa_18N3am$<?Q*thXiHN<8!0gu>=OwZPI3W~r6b~(=#iZw
z@w?%g$109v@jfShI+1NVOUxBE;vd%d2BYeTD$P);=5|e_GIeM?SYp6+ni=kajjpC|
zml5g&oCndy(kzs6e*@yNOCrn2S_S*_ZN)Q>YM(LOQ^c%=>UM6AX}^90`}BKssMbvD
z5b{P5dJ(RxY4aOx{IK~Rpl;Un6sp`}#v1@v4Es6U1~R2`HDkI4nRFiFV{C@_O;w&F
zL5-}{Ppn=8jX%VGfHu3C>ueypfHD`B8<}f8+v5ZJ2|(mf$4}#<fXF1Kh}B!hSesDP
zY}-}ZPi5WeS;i$=cZYh1hf)l<a0Glv2`@#z2$q;|>;SSZp^Y6tTj95bsn4Xs3`XNe
z>D@rT$!Nk&E|$Y=I}IMg;2!=GzF0OwuaV|reMTbtFtQxjVW@Qnoql0JnZ(DU%3Yr5
zTKtpoKchlzh~+Wbn`tnxfo?tWx@p;fL<3N$8yY0QW&&S=N+vp*_?6rSQ+hAC8N7=|
za*I*oTjK9fa~uQO1c>8KcG3;TChLshHao%NS6~&O$_du+I3>ow_%MQRX5Ic|uJKHI
z4Ds_LWI(?&jurTu_!6w4@<ZNKIwPJLC6VLkUQ4xOCSvYDx^+Qvy_WSXV6JE2lmORa
z(o)%;k~E1-V!1{EbOnAtBlAJvB4f>k@C?{{P(1~>vv}CEok-dai54vhZ54NxzE@HG
zAkd##T|(2%2T;mjNoJyPB4iSvJq`R#kW8gyuNUtc%zNooO0}y9y^=0lX&VKeAs|0M
z{1jpqqQi1#YjcuNfo5-8&7pnGWk_=e+Sgc#9|`@J&0CNu0xe~350JPo;3go%8W!Uy
z9w&9i5Hl8fJ&<n|y{hoXAoN*0uTwKVk>PIOmx-L~Kz#}x*R5S)?zq{2sG+DmRRG<v
zZiOX8I9Qun*cVyx;pt`yOSPEyKANm3cHsdnhoR+lfDYz%C%qhGJ!Sq~iF|}+`}ySV
zWk=#ry$+mtOzgT{kQ@O+8@&;Rij2jzPhT7Ab}-gD72e96r;`oUK`(=$HnL8S(5$=G
z!%$CHtyqZVq1iAE+E5nlBO;|ufhKRLZ}3bezLrIrgDCfy#(oIAp`jb<Er^|`=I|GP
zu<Nv<hWZ58^AI_g(<UQJ&NX_JhHBJ1q^s*6L%pVB^jB7|fxgwe4b>6?Cs~zl?CUbk
z+o49VwTD|s%mG$t6AI-3t0~Boi$~0UhTcCz9oHHdDx3C~^&kv&Q}Z@dhL+k;QLK3^
zBY47?Y`V0Df^y?|G!1%)+NB&}-wA}s;bNoSmnRUtK=g@Skfb9n=>K+QJ7@Wwy>s*W
zWR+I?tE#gq%Bv<%&&u~#PpYY$npIQjsTuG0yjNK{C2M+R)uigF<rRJ%GsRQmudb;M
zG&`TU`u)FL-DAwOae+TN76nC==9l<}zFg$>`I2&b1p1^dum{eiWrxKUz3R>F;mb>_
zNKdLra=Vj?i!E2qI{VOKuT|?x4&2Gv85HC5jr8W{`3gsj^bX0_1+oKw_58|irKGkG
zeAN46BeZ9BZ%=mb9@zocAT!Q($yz#cx-Hs@@Q$#xwnk~&%i5yteCw&VtL?H?J}A!W
rR~qdYsMV^sN=n_flh(A-&bByfwYG)UA#G<^w@W)awv{NgQR4ptOWB{v

diff --git a/Debug/Libs/sta-core/src/devices/arduino/subdir.mk b/Debug/Libs/sta-core/src/devices/arduino/subdir.mk
index 9b13464..88b204c 100644
--- a/Debug/Libs/sta-core/src/devices/arduino/subdir.mk
+++ b/Debug/Libs/sta-core/src/devices/arduino/subdir.mk
@@ -19,7 +19,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Libs/sta-core/src/devices/arduino/%.o Libs/sta-core/src/devices/arduino/%.su Libs/sta-core/src/devices/arduino/%.cyclo: ../Libs/sta-core/src/devices/arduino/%.cpp Libs/sta-core/src/devices/arduino/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Libs-2f-sta-2d-core-2f-src-2f-devices-2f-arduino
 
diff --git a/Debug/Libs/sta-core/src/devices/raspi/bus/i2c.d b/Debug/Libs/sta-core/src/devices/raspi/bus/i2c.d
index d603582..dd8383c 100644
--- a/Debug/Libs/sta-core/src/devices/raspi/bus/i2c.d
+++ b/Debug/Libs/sta-core/src/devices/raspi/bus/i2c.d
@@ -1,6 +1,6 @@
 Libs/sta-core/src/devices/raspi/bus/i2c.o: \
  ../Libs/sta-core/src/devices/raspi/bus/i2c.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/raspi/bus/i2c.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/raspi/bus/i2c.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/raspi/bus/i2c.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/raspi/bus/i2c.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/devices/raspi/bus/i2c.o b/Debug/Libs/sta-core/src/devices/raspi/bus/i2c.o
index 0fd8696659ba91cee37cea9c67b0ee7c576753fa..ff751eec56c737161a32288e23754ecc879cc65a 100644
GIT binary patch
delta 3114
zcmbuBiBpti9LJw!*;kGQ<dgz*aYZh1xg^PPLRkfkAY{>M)E&ePMUeuGyyk_{(eaqX
zSIZ+0G{-V5b+Z(0Jafv#(eW5jC-Xp?q-NCdD0A$2K2Co@JMi<}-}Ae^-|z2vv8m0p
zvdy&IW^%Q}4-Tw;L5TRp1BDox)H1nHU!Ng_+1K1d$d9kDudoRDGd@Py-6m!C$0<8Y
zQ+77~_CWRgqmQzuW0k!TpzKgt#3I~O$RM)WS9vOvm2JgyEm}SQJwVw|8L3;uvwrGJ
z9ci5*>iGagtIg^;3tK>1Lr>-D#BRbrB3^lp^;cHwqpXSN4u^WanWC(pUD@fW%6`c}
zcZ2Xq<Q82dr>QTSnX!PPw<**|9gB-3pChfYukysfM^u7(J{F4Qc^7ro1LI_r@=vrX
zyO`6}0GJV`JRjJU?M+Q1*~hA%fR1T?%DqVHU=i2Cl|4hl_ZV#$STg;UzYqreDR~R7
znu3-8A(HsQ$xw3d!^2y!x{LuA!ovw_hBDw0y_ZVv#O{w!&w&(O3esi>Eg*R;Emttg
zJtBiqzL4!OfjXL)%-*VwPMtt<=M(=bs9%EH4M{3yWQ4B%X{SUyvsV+8N^${|b@fv*
z;}GK>b}v}-S;Z<AuZH+6=)S|yM-lQdYkV82ZczVgPD?r65G-_A`gWpf@K?IBXVGvj
zXk<0%X(Y58-O?b<Nwc3Q_a{TNN2<s;vSx$+^B0w80o9fvu0hO3pw8p;r1Z->&`IOL
zsP!}Sh7ei|nu%z6o;DuP?1VtOSv6>Zk8U*H!f<hb`H<7I@}^rvJu-Cx<^he*a~%gL
zzb?jSs-Sk(>M*NU1L67D`RFtsT|Z^SNJg0i%B|=+j}`VX`YDFUq>hKizcWM(F(s_t
zC&;=M{&ZWaYG2H{m9d7E;Ld~a0)`8K!0VK7QFJ9+5`Z<4^()+%8E7f^cA$C#6^0;<
z4$~hq`W>X{(4l%S$Tra65eW8>5GUW4^0h+fQPOTPTm-aNla+uCgsuJXbP|EA#7D!*
zU9RXt{G;(7q(V~<BTb9d@6ars={7^Jot8CF<b<JgIEV(#RNe%&C_0h&b<Y`s#qY@-
zz`Zy`ZV^m;LHtf?Rw2+7hUl=elXhmjYMj&T`aLLJh0TVQk66PFN_+s~;}AZVb^8rn
zBT>49_(egAxl72g5C28p1l2Hfo;&4_#Ir(FWEI^@skTgq%)L<8%3a^cdWNIxB``e!
zYY}N?p8F=LLN=Cb0)sZ<&*8?~0I(URa{!zR`T|(*$GC5DvFBQ$GzN;?EBtzee?#A!
zu>KjNUolerlJ)yQdJLplaNHX(aloF#{QCfzK*_-@+f`;>_xz1TwQUexMVGH=8^SzM
zOn!v;3}TkT!)mncuyUER;p}DO7r!C;dZ_6Db{8vgfY3*5UM^5qq1#R<j$ybIh;XwQ
z+wp`^$4*Qpci;i1HT25D9}3ai@QkJArrsQE;Y$vzIGMT?9N!t=`rE_j3{)!RQS>13
z+l_AjxS&ARrU~@PMpQtup2AYKaNj486~Zq3K+Dl^+0CGNoHo)ckgTWZ{||j1!r4;D
zI?9gR<q9@4XFiJEGOMZfFhix(L=(YbxDLu=P5j}jY>;s}pqE}FMb|_hxeS_^!a7}m
zvn<JnCZ4cbrvT>5%8iyoYr;+YAfybJ;5AW)XFBmZi&O$BUeq`QfN^qkO~e9h2XCI9
z&;MYLk;pVL0@pJsu_h{LQ{+(3gQQrRXqP)AtILljUY9Wz@rGOjO*BZ{nuq|v4pt?d
zeci=+l(V(R169lsR%jax-3LskkFE|LqP<fttR|LA4m6QLdlT*3WT+;dN|_{cEOi(X
z#K=?mHkGC2f9+sy3YTWL6j8c_#s8QZA-GD}kayJ;=($Ak6E@8zBd*C`voKvYJk}w3
zj`Dg>UA?2SqHcO^y~9~sIkUzyqoLk0W}K_gQU6XwrN`aisi<+}4=YZ~uc({seyw)$
z%;_F?S?${mjTLns?*;3_NUy)W(8tKijrC4WSYQq*b2;<fg(YRK5l*+;mf^jX)XP7p
z+*#@#Iee5$dUCRjkj&PwQN^yDY<GTAWwNc(X1Cjlio82AFZ+!Azau%Eo=G#SylV!n
zHG7M4S8IN`8JTGrIqB)%?pNl9o30pB%Nl*G!;R}@#ij@&!&PF+HkzfKZ=7+Zn!1dq
zF1saPlD5Q1D7TwV8KcS*eZumLy7K;}LSs#NqUn9(aCu^MTd5FRC6)hu<Tmj67i@~2
AFaQ7m

delta 3093
zcmbW2iBD8l6vpo`yeA;5fV3`%BFHw5AQGv?1yDh8Wu~^aIz<?<Y6TgHS~U-%CPr&f
zpQIWUwbrFkF*;4FRHI^RG;yzMZC#?cM6K0Epl#IN`|E#D0w;IQJ<Iof=iFh<ZcFuU
z%gPwb;8orGx37O&i0;+Bg)k#mmE;*_st{IRYdax-e0_a|CgktR&dTn$DEnJiW#{S2
zj!96qvAwb<eUyFCMcKOn%4W$Tns8CUO@$g?<r$o)>~TDivb!e!NKrOSMjD!kk5eBi
zNV^`Q&NnGK-Kx%gvGd<j=gLrJuVXjkFYT^8SK^gT=%#Eq=i_#DK9;0xQmnH1$;$2m
z(DNX5o+6oRhUjKf9}F-Kr>K97@<gg@@i)nrNL$xKc?O|J7NCC&Q=TiFcTi^|H2kBK
ze{!I*8@N3Ufmt1t=WFUmQ`1cJ2{eu(#|%Gpxm3<U6L-Ru{gZ};K#PV;n!obrp+FWT
z{eV*)to$vEBpyv%<UT@&iKw~=fF<a#gPLIgd}DyNjf)>5R3RG!XrQ!-pjjj@qh%RT
zUJx0~<n!2$fgM$D0Wpqfb>2c93%QGl9|>z4+RkU2hD8`Ew2=}yV4qIVD3XUGSs)_L
zV;B)VRr~?C=CF#TEM6_~6N!8U=w>#ejWvG2s5DeL#;u3j`e0$ma)0$wMW6Li_GeAm
zgRqg+<ar&T!GN<N+Eki7#`8NMS|e5DM6x!({?|^*vxI6Z818vuHbHeCx2L6FzJYTz
z?#;AzB5w$xO>nIS^<~<)VY3|pV_8=(syt!FTLEW>%pz`2$(ODP4`XVEOd=1l6`P{`
zh8Ulwf*M(?W2{~+josKH=5&C$t_ETxP!_{-8*}xr!r4GS3y3u8xM_SF5MjimuzFuI
z)<fuLydtffbz8|YR!QCE3+16?0WJUmuTjE5(KWs*CICB-tlMZ~1yBS0_AvG7RG7<X
zs!;j>&>u6J0E3GLn605fD-2%XAICSAh0tcw+5ne<>>rcW8EZqWXXw<#fO-@E62{MY
zq6_iQ#D9kh)$L51-o;3OK@{k|Lf%+f)*?~&WW}`)8U(}U6TS(`nCN8U*K_Mj>BHov
z@GdrzTYwVZ5Py-Hr3`2pAkGA`ld)htWM0x^jd*xm1XdEN>|+hjP+~5OPayagtlLkp
zY|o^J62CM^f&PVY?8SeUZ-RO%xALZv8S%Uj6<JF6Vyf*m5VMZW*uq=i#Ci^AuHVC{
zD_jdmi(`AzS=AVpYZ5@$;m_m6XG7o?W6gl@hp^8=^`5|;&%<62h@_p7X!dHqsPHTF
zy@%>2fd1M{@=G)xK`DhLnTN*Fkm(BT_rZSyl5v#m&%3?_=EL-IQtci>ucu1`Z9~A5
z0P-f{XA$!`I;>^3mOv7Qq1i{~O}_!gXGrr5+Rd!QAwr+Bd3LDQF}JHooCUZ7gs5RL
zPUCq7^r6H|g<cf$8T4}E4@2mKc;2IC$7qJTl@HT7*MQm!k5lG%{;}b+d#iC*QuIEB
z9+*%3y9PZ3dNu4vnjHfYjdm>6ssI&VNLC2DaFv!L(DD>n8QgwLuZL{GE9M_eWDA-d
z<tukHx8bN>1I`>KcHgSH>|%A7$Xi_mcffT-UhCqiud-J2d_a^@EQhX(ZgLrPv5j?V
zL$kh84_*AjYQ2P5JerM=pmkx=K8R5cm*jP^9nVbSt5~E(h;o@}9EHFH30)T-K<o(L
zJfr^mhg~8S)x}I)Z`!GI5pA;V>O4V?QWuSKhh%m6ql>XJMiZmu8t9@@^43KJ1kSN4
zec0C>tVbH7KOy&37fr0t4it(6)^#64U9>R!xpMz>aYkyOi&WaT%0cMjtmLhW5Gl2^
zta%4U5GKKC!Xis+q8#O>@n~x05T#3K{*4Mk@FZnJW=r^5=yIh`hZQk0;;Q_!3d;r4
z9XKE(=N-G#<F4@7i;F5|&avmZJu@oH%I%e9w#sR4+oxq^v+Q%qDrR`fi;CScW|pne
z?Wy#5ZwIzSzWe`jWsfOUrQXXu@_mAwx#L{Jvhy7-S4>8_H$85-)q5c!!rwI0BF&en
z_1>Ln*L*s;T!oI@99Q0$LdVct8JQ|vuKdxCv5xWPh0qA^-F^$LW^`N^Z*gXw?$<9h
z)0Uc<p1ObVf^f@8b7A2epSB@pOW|mXFo!zESYpgNY0J%KN3!LH8Rm@DGNnE>W~MXN
s(r8X{_R?Mt5+dD9Eetm|I72Pz<{s%Q86w0Kd{3OA+S+kKY*U~91u-L{$^ZZW

diff --git a/Debug/Libs/sta-core/src/devices/raspi/bus/spi.d b/Debug/Libs/sta-core/src/devices/raspi/bus/spi.d
index 4a37229..e886c08 100644
--- a/Debug/Libs/sta-core/src/devices/raspi/bus/spi.d
+++ b/Debug/Libs/sta-core/src/devices/raspi/bus/spi.d
@@ -1,6 +1,6 @@
 Libs/sta-core/src/devices/raspi/bus/spi.o: \
  ../Libs/sta-core/src/devices/raspi/bus/spi.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/raspi/bus/spi.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/raspi/bus/spi.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/raspi/bus/spi.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/raspi/bus/spi.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/devices/raspi/bus/spi.o b/Debug/Libs/sta-core/src/devices/raspi/bus/spi.o
index ae7409e40126cbdd1a9da496ece4a169d01d1b8a..081134e6c5294f9325659028e647f12b021ce2a8 100644
GIT binary patch
delta 3121
zcmbuBi*t-u7{<@HoBbq_dqSurk}j2q*zAUgnpW5?5s}a&v<5pXS#gVKE|Up5Ulda_
zq7@%yD2g%Et(Qej$h6XqYAdSaGLteTb?LOUBaF*X^qikRp&4Fh-}By{=Y7t`^8MPz
z{o0yj?XBjNobGdb3z0IxAw+R%b9tWO8X$x<$l6WFpP-;1VH5Jtv_8sysVRFbQP~Dv
z*+uwUx~uaki?U}El)V<J>}#@!O?au`Bywqx@-(C=yB$wwFLjQ}P&Qgd8aDB?pZZWu
zT1TWhAE)SCt2$?4$C6eXr92(jPw=}_l&9?#W%a(wKJTyW6^YL#9uLHCSN6ShW%n^q
zSGYPacS>uBk<4<G8OKue28D*HYjKg}^Q6_itUQVE5l5TvqLrtO^I__20mkW`%0DAa
z*_GUG1i*qA<!MY-Hi?>MnkCG*I!HO@1rsj!U=y9O%Kl8lCPteA7FUS!=fOY-C2zu2
zV}$ZQU?mnf89}ZsQ~9UDYV(T$;o&MZqZzQxh*v=!*kf_(+?}FLAT=O&I?0o1xrb5i
z5*fkf^H7Hd>R!aSl2jdoIw|BXCw@Gri{SQ9s)`vCXQ+Q#DAAYM=Mt1o@>nRl)=$Nh
zvWz>}qhNI-#R`O1NxT!f|77SBEb@`2a{pjeozy?T?IdouMhHV*Kb6lwDw4U*vBM>x
zk=3NXj?ll@TLz?gX!bqj{$Yrg9x5`CtVN*T^OEwcpxSDdYZ9{!sPA%nTKeT1=weTO
zP;DplMiN>8nrZCv0&V=DIn1DT<oY3e+-Ao+8LkgtmT`Mzuo|L<HQfNreHvfjISx{O
zL-<@Os0CS_Kzj2ad=z#Qds@z34>Dp8Mwto9UF_9F!iyRG3`4l6<EL>uLpX`?BfSl*
zbtC*4+3Bi%A#y85hCXn=4&en17Yc!oC{aSub*Lm1tC4jTZmbN{1ik}oy@3iNSj`5Q
z{)o|Uv6^-Rs(%F8AsRdc!C?{-<@cpcXoP-C+I5DDf%YY21!F^C>li%!!h*tx9}Fv9
zJkf3V^YOP*p|P8pp(hx(XqLrvJD}H2%Xv^V6^1h5AQ3ck_$H`gqce!#%<b>6*h=mo
z-o-_73t-|?;tx`@f(6ZDi1sivX=ld!=6T(2+=bHh*nC)7jSSl<u@1y1A$%=zd&XXS
zvuQu^E5j9Yzp{>x@n7bfU@i=u<4tvA#SM`vvV!gvR9j_0<{7Bl&RgGxJY(7G9WXrs
zYXNCi&N)am8F5W#(0cqsc=1U9*a6eo03HT<FRb@t+_!nyOTwVE4-`#b8yp{dh`!fh
zeFvjoHU|c$84rQ<2uKZZoCKIeU^g@WSAgtK$sELXg_$?gD~oEoA-aMt2WcD0JaJ6k
zM!b`lCV1G$Zrj6n%=vKks`*>+2qOSB?ZCc)B#smMFUtF1uwr^Wdpiily%{bQBBmpZ
zJuf`eNg>9?8@R{qGI}}jM?-Wgp2^hQn#9FUK4im+hpD%Lquo3bVvjW#BA24A#P2n4
zha`rlAe%<e4={U%rWv`2s+srhBP$XuT%u(@Tw2KTa9dBW6tbSO|Ht%w0B22*)qzI3
zc!Eor)6K?iS`{@vQEj|bgf1dtaD6SWb@6wQvVG07q47qUT$wyeG3a78ayk!ZS&|Q3
zJV9Eg0cJsR`EqDocxfLVq1wbs@VcnRGoScn2&o8CzF-^Q0APw7T^9)e+s8Lg)Qex(
z6D2ZTxN$v~E7paNHV%h6XUS#hqD5**R+m4zm?&dxVxg3QE@~xiUBm(408+_BuRloK
z@_!<z_N3ISF4~aLZW!tUOozo#7Z2FIM+#OKYa|D{aMJ#|T!b$6%1~XzN~$Guh&qN9
zJY!87PazBDX7gxHNwvw&!WME_jSyid8~KiU0#U0JKQVKXWkjd^YZclh(;qe>*HK#I
zudZ>F`Ksqv)i^v=Wp$PQ1+_JfH>Z^3IcgUA%KYA1zpv8a9#xp(_EndACsdW!&G&nY
zt7g^K`>Oqci(wCX1VZe27IWP2gg|-!71o&I5|7)PS5#c`hR5qob_%c8T$tG-@GSLd
zaCoU_l6TDLaV7F1dx#nC+8#5muq1nk*PU9HmRy!>w<i}A1opY^S;qX|$s8X4%({xe
zXG1qx12c!euLlozx-y*EnVEsEk&9!st7c_!y(Mb2d9%1s>tzltDbjMx71FLWFO;Nf
zH%zV6ZgWfS)|hFfcI})wp>%*PK39k#W=e6a*;E>(6_{J3Z^<YjX5zbC8fE)@k`TMp
Gr~d%*8mF%S

delta 3089
zcmbW3iBr^N7{}jbcYho%EU>Or3Zj65x*~|Ck_CcXVdlVkr4rhDps~iTgJ{!FM=aBv
zz+a4Kc-NFiW7{}J8F-8}4(5rDM`EMqIC-QNI$7HLe*6z&^qH6EeU9(<`#kSY*X%Ua
z?ljfKn{w-W4C&PPybwKdQiU*_^=}pExxIxjTg<^i{#Yy)VHNUET~}qlHYxi{tg<zl
zvYupRn>s1`Q;@RvyD57$OxfYGh*gwP!9#_`7Udb6qU<3&PTAcmG?%hbGE%pS#3c1g
z6=~<~>U^1^6=roFh+X)cI{PD)J&)al-_t{R&h%0?xx2DaoZBQnt2oyOe}b}QeU;q-
zpnKu!ydX_lT?_(C0~qru8XT{#UFupqBKZtyt9vTXE9j94=)+OUbB6N{>U;`~&=}>P
zVpDb<x2+JUj8>j4)Q_X4krHIn&-PR9*&)g<lXI|&UmeQcqv0%|WxyppRQU@~U^pd1
zfU_t<`8ya%BAQGl_c1z5MAZ)fxBwmYQ!@&HPj%2n0OGsOs*sBT?51=*f|iiHoR&+0
za-YZuCSRbbte3keTTD!8oH}o&P7JxV#J>vbk!V}bHsy8JRcI3>vcX<K&?u7gkt_@m
zs~JXgqKe-K*Bn-H28;JG@#Ben4Ct$D#3R=D2BR{gN;9`UZW|+nF3Z`$5)7`>%<x;-
z$ZGO-HK8`Zxe#qS&2Hkk1Bi!C6*-Zt4Y0rTg7Pe-+De9df|!j^-NS9G^vgGJV}J^c
zVp=~Subt2qxV{JKHrjY#vjd<Btm__Bxy6jP0?sAhv{fwOc4vQe_A#dGkV)YoKE(D@
zeqD@9S3ymz)d5y-C5@+HtI=j3bKM3+Cs1l(xt+Ow$o7l}`p<w!r;dllhXB!=m=Ubr
zYR1}xe!8QtYCo5Ct792`Qg^F(lZP?_aA62|hZ3a}{lubT!muxsbp>tA0NM?|T}<6e
zh53wTB}(rD`tOV;Oy{BnW?$0aAq?*0AHx^RMCf(WIslh}>{VnvfnQ(Lx{FRfGNAs%
zcS4nWJkbXHbMUuQVNtN*(z@x%Fh~L27UWH!<w_)a5rqbzfde+P_!4-T=oI4Db8DgW
zescTqE&}8hqr?})pP=Rp2DA(i$879m0vJyjXS4*p7d%b@D+^V=VhxW`VmZ8zAow=c
z?ILrvqr@A;FAG-#y1+PA;XlQfppnXd@upH3agAL?&Y*h@)pqHKxdZ7o^VT=Ap83r6
z7@T6^T1;9J+f$UR3dOTrlL5LGe;zMB3j*zobufe{z}}7OiNIaR!+zI>q+OB7yDB8c
zahAT<Q2j8_pBQ~YQuNzU>c^7Qpm7{zVxe6L{_~JbqT~?Xbvu~%)5}e@YY4rbF1u-K
z2Tw1MA0)n#n2*q54YM`bNSK6XlZ?wDnR*@4+=cdaR^od?@3VQe{gprs%&iTHGXYnG
z5IT!-6pxiUImAqdo)h^R=v9J03ZakV8B5JBaSV4Wzf^Eu4C+1bXgBtTCOGB+!cWm_
z6uM#D3XKhaLd!+4FEqM@rRcFNRXy*099edD;WjOco@q(eFmAu0*AuqjU*>NkvIEUp
z_~h>8)`9Aa!I{Ivelsg+4zRk}aw9Ym5sj-^UTfmEMOmkDA}mH<Dw8$QT`q$rwzEzh
zXf{ylp^3+=)&qzoqFIpytqFtn;Ss7$z9g@S&+yD4zJ^6wf+(k%MhgVSN$8rG0I~gi
zc}6|^2YaeiR1+1ro(8LPIc<_s)!8jasfi}JL$bR3(ZuUA#ww=EHPD1#^43IW2pnfs
z2C%QqlDGW-1zUThlZrXW3Vn`34q%-R($z%=v!5^bPZP(a2AW8t{RKG)O|(khnn;pT
zYr@W&M>B#y8IwttmLGhSo5`cuE{7;x!Ww!?L5P^Ato<GJ1R_@`eWF*y%ZPLGuUVK*
z8XjBb;GAKpZl9;hmpZMyYEE@(uE#gq@12|K_qzNuJ+8OC-pbT!Z`Ewy-12E28B^)<
zdwhOh;EJuo`O^Q(l|81;n-OU1Sr`=V&K*;hH=?k#tSo+TMj#_;g*k9CIXcv+Pj?y*
z(i+Wq#ihmqXOF<q^wyxLva*uW+?=w4(IurLb7e+a;L@OVW+N`CTcBoWtrjvUZKx}4
zXhvGVnzhhjYBd&@R0sW&ZTwyGn#p1mmX0<h8f&HX8#hb)nl2h+vK&UTJJLE->hr!a
p+?`-*Hp<<-t>!EtGPvF3jx-H1_DJ8%Y$2xN`$PIR7^bl?{{fxTpmP8K

diff --git a/Debug/Libs/sta-core/src/devices/raspi/bus/subdir.mk b/Debug/Libs/sta-core/src/devices/raspi/bus/subdir.mk
index f693fc0..676f2be 100644
--- a/Debug/Libs/sta-core/src/devices/raspi/bus/subdir.mk
+++ b/Debug/Libs/sta-core/src/devices/raspi/bus/subdir.mk
@@ -19,7 +19,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Libs/sta-core/src/devices/raspi/bus/%.o Libs/sta-core/src/devices/raspi/bus/%.su Libs/sta-core/src/devices/raspi/bus/%.cyclo: ../Libs/sta-core/src/devices/raspi/bus/%.cpp Libs/sta-core/src/devices/raspi/bus/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Libs-2f-sta-2d-core-2f-src-2f-devices-2f-raspi-2f-bus
 
diff --git a/Debug/Libs/sta-core/src/devices/raspi/delay.d b/Debug/Libs/sta-core/src/devices/raspi/delay.d
index c29c9a0..9cca07d 100644
--- a/Debug/Libs/sta-core/src/devices/raspi/delay.d
+++ b/Debug/Libs/sta-core/src/devices/raspi/delay.d
@@ -1,6 +1,6 @@
 Libs/sta-core/src/devices/raspi/delay.o: \
  ../Libs/sta-core/src/devices/raspi/delay.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/raspi/delay.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/raspi/delay.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/raspi/delay.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/raspi/delay.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/devices/raspi/delay.o b/Debug/Libs/sta-core/src/devices/raspi/delay.o
index 945b66b7e205dbb96c94f0a247f70ddfde57883f..8076c419fd5b48d574cafc13462b0cf517829f9e 100644
GIT binary patch
delta 3117
zcmbuAiBD8l6vpqHVV-~>h$w26Z9qVzBd93Wt$+xMC@>>It5d|$xMEm}t=8vOE2c*9
zVJ)c(##+-jwb5~lN!^lajoNArTCG^O5^L1f(#2G*z4vGO7jyzAk8{sG=lj0%y<wSG
zYxHXM(VDX%W=O}n9zw)CjSyl{V#ADFV@{k9)=+B)AwPb8e!?c?&*E29+^4B{t+$GE
zbrqY)dpoM<uPrM6(o4mbKouRbiA@yJVIq}Pek!vyNyX!2gq&^@JyTS)%1Xl~M#ZZ?
zW^nCnh<g5krgN<7c>r-{clA6oRK>HzX7bZxRK}K|VtkZ}nSE3|;!rUvnY>-aT|93A
z(4AnFS(PfIA@ab|3dS)s^@~==gVnKk!R1q2Ym8NyVdzl;=!2bA#>U8F^jQy$quo?~
zVvvewsXPRMH^WqB8~r2cX(m~MjQjmmdaA#QYvdkm;!+nCA2Dz*(3bR7nYaKIhoV3t
zEp5Q5?4<I4vXU4ynatgr=#Y=99|Q0tI@suD1>k-|nnB_uejcu#`?7%Dv_1*DSzNAR
z<asXNrBbl@p}3>HtGYXwn!-r+yp=x5+<lAs5s4~40d24HJS5yuDK9NXfc*`m8O!Ai
zB<q8S<H+}jQ}u`8ItVM4V!RKiucopej<|^<o?zpvtV*EDuTWaZX?-VQ$aaZf=?t!~
z*x>?pD7(qiMoI$!7lml$3~M8E6A)h5hj6P2_NRNQyR~#P{MGY&)HFbKGp9#oUcLj5
z`>W%4wxzQnjneh7Sq$pajPbzc06^{7^)ME_!HzcqZW`=Ya(et#)!D<Eeu7LmFXHdS
zNR>B4S(+;HVk;lk+k?ofh{w=o2YampVh5lshvg>rx&;e2<Ba2gh@(#lgRcN$7&U9L
za~*3vgnq^p7|+LUqp{&9@Se(xk`K6N?AU^pa%j35Hv|&fk^Lsx{K4Se@Y}}L-=;$f
zHJecS0MJ`m%`pS1cf#x_7=MPrE-nn?8>^i$x4D*peNvIVgj-?6G}O9=P8V5FGWEr%
za)(!R8~NGf+vrf)!A#M68LbQ(0J=ux?FzcJFC{{uSWMI#HdFW}s9>WLsb9ybM(Z!Q
z8;NEvD2+gg&!|67&r)<+4~S#Ic(N-PdnTDJdaQAmO}tO6rpk*C&(os<%BN8LOZ;Ys
zrkzz+F!P;YWvg=-<Wur(?5_@qe&eO;!;a^MsLE2tZ=l;Z25Pp`bUQD51O7~7u}=}C
zCuB!(Ef)Js#j9bsYbroLBwx$UhC`qcsS{y531V(!?*`mOyx9wa&@>p0nm71IgkNIr
zWn@1A^rw+#vVWqX!7Kus%thr;*o46QAOtSMGJ>9cvD-yJA7NM#?V3<}HDj8Ys{yD4
z==-U+Q?nEy*0S9PL41$YAX=$;!~Zqod$f4~?<<&M52erW-bcXQ$l@NO@esg`L5U?;
z<20G^^chP{A@st~Zx6F3leePuJu;K%c`J&89sJ>9)9IkT4UZ=Y=AnStE_I-A(^c@Y
zZ#EwU^bYQaaVnvoV|EKnGCX`=tPE5JnaiyZ+@Q1RVTc*btpZMGGc1Q&&vC$T(A`6{
z-Kg~scSDhVIY0-ovNo%l(n7a!(i6Jq6h>;VJl4gJekw+p7Xl-U74ot!I!im~Vlswm
zN3?h;h%O#tt`LaDAlg_7S{F+h|AM`yN%FdAATy2nb-W!55ak-{I1Yh430*>g*duyc
zUjENErKGx8P3p1Su`bFOli^U$MRJ$A@XBGbyZq=PQ`XqTLg@otR7>8v&>?URuf$^5
zGm^JW)MMMj(y+SNkB6F2C=^&%ErvR{$MVaiV|B4YYM_f$#y^sa(8U?aTNi%=B?zDU
zu>yaYv59sT8jo_5d21d@yU7D#3%ITzbTU*7DOXyBzN_>JTN5oSTIH`*Xje>6(BM%H
zSCyx-%28fcIj^G1kzG+<GvBkIy2?>h;>>kaEi5bdxT`&7^Bq~Q7o=pBRnBmaub5FY
z&*Ltxm|0z0R_XD57j&<y@2}Wgi#ai)m#-*(pEab|nVsd%olxu?o$Yo<r~0&{jDTQQ
zcA+~bGtVhA=>yIDwC!Pe1<v$=?ySV}r0DW!yFEHT-*-Q)#gg-XAvv-=(`#n=E(}^`
z_07&$qWfp0rlq8&_wVm}IC60p?YcR;xYiPsY2Gd_(8A4B=LBt_xm?Co=0#_+cFTP3
ywA)5X(dx~3mtFhT%yT7Jx{NX_U467%v&og9EizBI61sZ}h1e;j{O=>(z~^5Spq)7Y

delta 3084
zcmbW3iBpwj6vp3sFZc6;tRmnpiwj72fq+CESKLxl2guPxM7eILFkH-X`z)8za=}lt
z+{<M~MNO}gqhr$IG8u)Mn&mbwrD>&^$|Pp*`S~Bjz?tu!_q^vk&vTyd>WT{6oC@2r
zXj`}Pm=5(1H&!af-AJkV5#@z_&G%a=<p_1uQ~Jlx&rdm({@vYF;$EA?y5<s#42g^4
zC05jzc)~6*jMK9L^6b`4oN5Ri=F!3HCz%-u60ea-)6<<QG)baESDH>WuC;t9<l4y)
zd4AeV;zWnU7m2GiUZ)xxD)A(7Bl&qTl8I_7u}@2hIc+3<>Xum7j(nWNd5IF&0qA;=
zJWo&2(NtZ*auAGtXxb)Pj+5kA#b|k)>KNB5W94}yjAsM7GE6d2jNDJ3rO<d1Dfz*H
z5-(AC2LhuSNahRrx1gt$U=K8}z98v5m&AAV9-Qh-xWrJ9F9F&xxU}+@d`A=*LCdzl
zDGiqVBUaKAO=bf296Ag@)p7uCK!<DebO7+a86}q+17c@Gc^<$5s%iZL?DDw0jgi}d
za)V06<~tg4D;d^B)OcG+riwl>+<l$;!8oWF+E()1p`j_I6|@)y_7O-kiOZQtHV_f}
zlke0@>JPv*9V-sQc)O@yLuD5nVMpj%Y<z)L#iELx)8+VOS+Fv7yN+O~2d<;+a0hI3
zH+@=3X(HfSBHDb0xoCG45Vs?wasamu!Tw1T$xNf0>5}I!sVRqQ4X2;$ynY9MO_t-P
zZ0kDm+9-9vW*uXWGsXj(9RQ8Pu0P?D%j|e1;7Z^(m($Aj(%HkBZbGInFJdGFT1ehh
zLsO-w0$cg8UJW8|C9XxA^X%0GVm+X2g5@gqYT=$)K(7KsEBXv&a5W%OsTqg$7P8h0
zC~9^{l<`Zk+uNA265b~J>jAhrc3ew~-ZWi+8v=;Q+`5W34;fqy%MEP3m<|(J&0>^3
z5A;i{rp`p_H89)9fZH&*!G#jOu^uqS4<BUmMr0%VKyJB+Ij9v({c#pFkTJ=qa-COn
zCHeQryQnX%XC)cU%qB2M0No1YjR0K*5{*EiSWFZSo7eazC}yLBsb9=#9IbbAw*{K@
zhf)`m*hc-I^c;pxd!TV72v0_U@o~I$)`&G5vGA|K^#N7i;lpZrc%Xa?#lOdI3Yv|d
z`;D2?gJiGYVvx1uFY;Azn9dE^ZeL<ih*S<^{ARk{Gf}68rXSnoxEz0uWwAdZNN31)
z;aV2<DaNY}a918c50GET&hjB}ioM3e_zj5VB6}ooSMy>_2}IK%G}^n|71i(|bI&3B
zb$rmgrIqN4Hy^{PKWi^S<xtp!Jby7DPz%c_dbY!ErvQDCVP&*ChtdZbvyr(r08Ie;
zKI%tNGaDfmvEArEF1&+iGpx(5PUe2J2}Yaqm|_>Df8o6)?M2I#EUpo+*>J#3K#BEO
z<2IRg^qIsS=0h(H{i>KXle`0^{~_}#JzXu??j}Ag<k<`Azu^%OZ++$;8*YNaqH9}F
zT(Iu?HxKg1IHk}ZZ$$<qm^~5%@7w^11>6e34UO1zXT<ysq*<J9Wmp`yp5lN(pu2@=
zSNPWbnY*dT{uV&fS=lcRnQ{^g-L)qS72JT-9(`=6D}E9qteSu*bF;o|s4#5@L#@J4
z5lGis3u36>F;@n}dLr7(8nmJIGX5ER9jnP3>L{6!)X&99pCC#d>!^Z2KMmbb{UN4M
zvFr1Hv$yCEhT6%P`+CQQDqxJ;Eze~dkfAE{Fx_4M7^;V^(f^IoKG3I{x1kIO{J}dC
zi(!vw-cB_c+aAz{HPk*l^brcB0_%d^l!IF=f0Z_%p^j(`43)z88+s9jx}$j;>K;(q
z<8wb&@Gon6z(Pl(+;HBSZ}bxNWaacfEf9jIN(>nzT7}LMeHv_!))i;;pF`QIEl=P}
z89h6?bG@EYuX{{E>7;4yERVOSthmHoR-9Be-jg)BxOj?tT5)NSx1?Z<N7qbAD)V^D
zyuOQpw<0?Kzq@+I=&9p;U&Z#b2jylB$?x5xUrv60bViylw)Fvr?{0jCzg3eOVWp<7
z_uWiAZ4b-O&(6u}ncsI%c22J>U76y0nm)&21-5SHo0Ivb;Yv@*OiIa2OYzyd%?P)h
zux4dXv)6XF9%a8`Q&z8>LAGdXrH&=m&74Hrc`Gb8&Y7+?Szu-6#@P;8dAV(!&$=p=
iW~F3@TWfPeZE4m{oh$6FR3W*$xuMPvhbXm0KK%zllbq`S

diff --git a/Debug/Libs/sta-core/src/devices/raspi/gpio_pin.d b/Debug/Libs/sta-core/src/devices/raspi/gpio_pin.d
index 0fbd28b..f8b493e 100644
--- a/Debug/Libs/sta-core/src/devices/raspi/gpio_pin.d
+++ b/Debug/Libs/sta-core/src/devices/raspi/gpio_pin.d
@@ -1,6 +1,6 @@
 Libs/sta-core/src/devices/raspi/gpio_pin.o: \
  ../Libs/sta-core/src/devices/raspi/gpio_pin.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/raspi/gpio_pin.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/raspi/gpio_pin.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/raspi/gpio_pin.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/raspi/gpio_pin.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/devices/raspi/gpio_pin.o b/Debug/Libs/sta-core/src/devices/raspi/gpio_pin.o
index 2a21d1121926fa2bb1136a5173d1a7ab0668ec6b..614fa4b75c5e2fb794146d55814a6f0179ffd98a 100644
GIT binary patch
delta 3071
zcmbuAi%->M7{}j(@Z&1TU5LxkBLQ;Y0H&eF)IdX$i*hh3?TBzB9fkqQoXejmm}N8Z
zr<86emNqpn&7);XQ`3x94pcUDmWa28Mw@P;nYP~d!}<$i^Wo)rpWFBQeBYlN_nUU@
zH*GYV%9}=H_^yl)V#MeXLR2L*mCx0eJST*QIBZh3BU;(znz9@4cl)YyyPLANqLdYQ
zGCkGVA^-FcQ;Dp1SLZE>${xk@a5%Tg$_5gd7N^eDoCgBbxl^a;q9N*!G1xarYZ|6J
z1K3vlZ^)6Q=XquOV~FQ`+osN8Ny<iBl-<txO9t}ySDp{kl&xiyE=GKXn!m(4)I}!O
z{Umph_R&b?PlJyfrtS??o&nBxDbxavzA)uq;iqgHxBCIGK1g{gj2O3YJ(T!$Udpph
zDEm*avUljRhk<HFD^G#9vQA(}Q|Ac;wE$y)J@lDX%q((!Q`NZ+F3-{BTfjf1W(rgF
z=;10T&#LU@5M^U2+6p`uEN&us5iQR$N<gTJO!84S2T8;L)k@4XHegU^Hn}^g{3`Sn
zLuhA$$}J1g)vx1}&{*Okf+mq%4o~4QSIGuEN2&N@V4a8BDo|TJ@lGP6<5kR_SY;oh
zU3cm{rhYGwGPphAFLW6c!7Sm-b&17o1&ypGZ|4wt0b+9@t%PRRDCdi(8$KqGwE^^P
zkt(;5YWuv@`72^}0JVwRKIzvz#3S}ph*Y0Jua(eMps8V(55VdK%?SpzAkr^j#T!kW
zVw3{Vui^GyifX)(HQfe`H?OY`J6-v8QIW2Kx+!rD>8*z3671J-^C^2h!iedNvJ8~p
zv)6Xi^9iHh8ysS=4vpQ&T0l%a(mTRB4#A&33r)^PZc7m37I4Q6Dw*NpAut&!y-U%}
z?rLZsYz$e~;l|8Bt>F8KSE*B>gw?db^ihD_V>NemsP1IOK4uIVs!CrZAx(Y{J%owS
zeIOo=d=jC3HCdThGetY#shb6viO+=<{{U5IH~zQqcTr)Lr;)5h>0Tfh&vYlD*FwwH
zP_zt&^5DP%nzeihs@UiX;*W7V0E^#|Yvo-$Aa@~5>?QsOYBsQ-_ZZ^5ADW!ZXC%<*
z(k!|Lj>C+l!^$pXc%Bm5Kzt6u4<ffnQ061IZN%?}#Ye2;0{%ekN-7`cP5p^&hMNYu
zuc6v!I%M9Z=uX~x8}f{2uYNQLfX0QSg@fCUR5KCRTn1f_|7}(_762z%>o@@CgWd`2
zQy6zK4|}U0lx9Ft(<ZO*kaqf-P~Ha&eI~|8@=DOHVDdvH&5%41G!wvm007&~YWFWw
zvlz8KW#~gRi=^CHm|j7fpXqC5pd3c;AwHj&y%2Gf<@WmV8Cd{n`NlP`iFyb7?gh6S
zD!D?a8@f5exLa7<4LBAIHwh+cQO3u3vZ<3n%rxNnz~2sf<={_&=_`0<Q*$7e89(Qb
zTsB>b=Mp&j;*D>-M}{0>3OiNrQ|ZT0qu)DfXeNto0l&Wy=98$;;d^lq;+sheKn{;+
zS^=9eWG&}*Gu<-DdWHm2hzw>ot<d!lnOsIb^-MaCo!uFt_9T*(ohe133I8BmzshS(
z^t&q?XLS06>$!4ins`a_tBFPwbpqB3B_o>n8+C~|RVV`1a^=vPsG<F6f8~#t=ryqx
zPbKlkXj}#>?d;<e0BYsJH8CDwJ=9Dd{6D)va;k|sTv77*Yoe4k<u-MWl*`maw^Wg=
zE`Kyp=&2enliwgs)Joi%NCUuW#FB?%J9rH5quZNOv6|@N!*Ujeycp|>o31W`SyPFW
ztR@af4rDpnN6`MX#H|UNq*@augl<E)W8|%eh~Y65!dxS(xh3@`FNBBp4K;#)qp|@T
z)FT+SUhxxDXqFK-<-Z}q^qb-IdvUU@xW-vsV=F7IuB@uDWmlCgUF>|Pw#GK=HG7V&
zW=Uz8(^2azU2MymlAoMaT3znQt14ew>2wrTEvT(4t#-OD`bC7f5-is}f{N_fS&p27
zBKy>Ahr^sE91i1TYN#tZ@u8b*lGRr;f~?7gBYk_&^nClc7aUm$Wr^l8v&CYbF~jvF
z{i@rv|2vB<+c|$}h3n2(UmvgWY3a#n<5E*ye@)VZO@A26i|R~K#{HrK(<oz#y}*=h
zG)cSJ=(Q)Aem8~|TRf&po|=uZ#TL_5<MrZrQ>;-ht=-rwZG&;4IDUBBOd)nl^8Wjg
H`{(ChJJp$_

delta 3051
zcmbW1iBpwT7{<@NazD1qB3v~S@xoOB0k43Xf;AwhxCJG&xLp;<#0A+xbDYn$Xp{!}
z)T~C+j8bw-Eca#1rO|9^)Le4GX)!aWNs~;;>Ab)GgB*Q5_nh~<@AEwGbG{EZ+v@dS
zw=KURW<c=1&Pv5BicxBNhlb(_=9Vr>In)lD#0Om^&NU>y8!z#Eu*5Iz62mxE>^$i&
zJ3fcRMO0YmC+lSi5?k0w)r}k~BUxg5GRu3&x`K6Un5-X~QSx7DJBew;)sM-#AzWfB
zaUJ_RG-QX0iIX^_o5YDdC4TRf=uDJY?UA^G^(O!d4V9e*DH2P8auSHcsM+1^lY=yl
zhjf?qS+4yUE9>zvt_Ah=_OcU0%N7c)fk)3yvOmu$@dlYUA+Rh$b`Dw5_D*In`LzME
zQ>!FCij?>iaMuE8S})nj3zS#_?XlG90fsfuXk`vr2+;&WTOY}<LCgJg*#`ML)a(ta
zD3e0jNs@ZOC2<6*pQ7|tDAjWLV>0&wC9H#FCI(5&#S-H>%6b|(<<YV}NS#sKT~Fna
z$Tt!}k7J=Cmno@xDKQc3r6iSdxfq?EN4cZu;bRWF;W`PoO~q}S$!{bx7aJ(IRK9PM
z=trG=RB>`zk4g50DpMclfF%T6XBgafu+i1@=}uA;05<~B7SpUh<$~F9kzYgH1N*-p
zm%B@;*2HjcquKjV{hHI8df#-Y+stVwR=tb7Nu-9r<`ix2z_kQ6p90i_Ngts~Af7l3
zlvm-mnA7XM1w=h#`Ux^ad3`Pj43~XVO-Plb^OU%X^)4aucH(BVImcX^fS3xD^{_m`
zTo2-&I-uVIL>_e((fB?f#*<Tn^>#82e~6j6c(M+=ZQ;EfhWC8tmkYQ!1oU8~a*D3N
zB|*e-+-gA^H-JvT@+7aanhGl!jfK+ZfPRb7#F-o%huJkSx<W*cFpAFNGi4*yjt{bV
z5et!h4!6>Xb5P4k{%Hm@k~W#B5*j8o-(&v`_LIn8;BO@xQRWbuc|mswc|Ekegz09W
z&}cO144c>Z5|lB~dF1crG=|a#xSPbg_=UUEP+}ALU6FkW13Cwd(@s2@$!EmhI%{~$
zZ07wtu&Pm|jccbVQ4ize2!0W}g~KxEKf96Nh>CwPjuY(r6ZcU$g5eG&u0oq7bl*y~
z2PWdQP;|Xrq}z`@i<zsP2I+8}#<jt?$Hb~nVy+1Q{hWP^k<~$<jdAyf@JFy8hw53t
zUCq0A$BCo^kZAu~0i9fT>1)Gz*ResDZdPJIycr9p;Y@uMB4@xR9o`!t&<e}J)GXv-
zw*mSR%_=BoLzUgMIYr+j096A08u`nZ#wLXLjNwK*xzK=UbFHfZ8RjwO?L-?pF1bkR
zeXO?!xGNc4Y!A`(1;D+H5?|rA8|<W0r=B@1hTatPJ4vr~?Ds}#KU9B?nrYqOv4J12
zvtA48NAPgPTe|{dT}_~9plS*z{5o2<1EWIH80;GOzhrd`N-&@0d$ASamvb!)JH*m-
zDr&m8RmSPJbW7vbKUm;J07o*LD|~ftakme;F9hi%X7+PC5u}xB!?Y<36&k_TWqoX@
z+kO(eSl<M7GC$Cl4K+yXYp5eQDiZDTwIYUkh`TajR*q^TG-yL@r+u$bX;ZA(8|n*o
zW{|%%S@zeViW_|oL!e3z+)%GTEC?A(O@3_CKMb{tHc<hxo=lsuURhUYK!!T6U8Jk)
zKZeT32s5-13{|Ch8!80?zwt;$<Je<7hWYsR2klrxUDK5v>L?0L!X_8(rW`~vrj^=(
zhWb@&pv%!djP{*%s-ebesSTBc(Y+WqL7zHQG>@SU<(4v<OWJSxKsf?02!zmi62sn<
zM-aYD^oiK$))^P|zjn%Y#wu|>(LX!gTUc3AQRyw3Trs1@n^RIby{c@sx2i0;>gAH;
znPp|OyftMN(<^6BE-KMEvy!VyDyu4+FFQMT9Q6P0>K;?7r#Al?d);A`_vz5w7Jtuf
zwWTCC|B)DML=1nrpnqRqc6?ESyU6YFxJQk$dZw;#zMOi&-rnaMQ;?JG%gq~8FeJz4
zbEh;v=ocIm&@W|Ra>~HIDa|37W~A+cRX3)_7GOCF@@(N&p^km5MjaPe_X-kiSFD&q
zk0V1%vfLV8=&_x!W){Xdf-{xsYh{gzv^E!p+cK>KdT(}?Qd8M$D-3sRd`788`SmY(
C8kl7O

diff --git a/Debug/Libs/sta-core/src/devices/raspi/subdir.mk b/Debug/Libs/sta-core/src/devices/raspi/subdir.mk
index 40894ad..457fd6a 100644
--- a/Debug/Libs/sta-core/src/devices/raspi/subdir.mk
+++ b/Debug/Libs/sta-core/src/devices/raspi/subdir.mk
@@ -19,7 +19,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Libs/sta-core/src/devices/raspi/%.o Libs/sta-core/src/devices/raspi/%.su Libs/sta-core/src/devices/raspi/%.cyclo: ../Libs/sta-core/src/devices/raspi/%.cpp Libs/sta-core/src/devices/raspi/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Libs-2f-sta-2d-core-2f-src-2f-devices-2f-raspi
 
diff --git a/Debug/Libs/sta-core/src/devices/stm32/adc.d b/Debug/Libs/sta-core/src/devices/stm32/adc.d
index 1a6e5b2..c267059 100644
--- a/Debug/Libs/sta-core/src/devices/stm32/adc.d
+++ b/Debug/Libs/sta-core/src/devices/stm32/adc.d
@@ -1,8 +1,8 @@
 Libs/sta-core/src/devices/stm32/adc.o: \
  ../Libs/sta-core/src/devices/stm32/adc.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/adc.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/adc.hpp \
  ../Core/Inc/sta/config.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
  ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
  ../Core/Inc/stm32f4xx_hal_conf.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
@@ -30,9 +30,9 @@ Libs/sta-core/src/devices/stm32/adc.o: \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/adc.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/adc.hpp:
 ../Core/Inc/sta/config.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
 ../Core/Inc/main.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
 ../Core/Inc/stm32f4xx_hal_conf.h:
diff --git a/Debug/Libs/sta-core/src/devices/stm32/adc.o b/Debug/Libs/sta-core/src/devices/stm32/adc.o
index bfd036c7fc6735c040bd88741e9b28c32c160bd3..f9b5fa3c0041e5d4b3ea2a2d647069db836f7f71 100644
GIT binary patch
delta 126905
zcmXtg2Ur!y_cnXE_wL@^y}fH<H=5XDN$g!?FVPrHVvF4rH5y|{xgw$<paK?DKu{?n
z0wPLPR74OF5h)@?ilQP#P!UDsdk??==i{@pbLPD7IWxOE<;+}OH;(aX9CM%(;}+0a
zVr$pI-mY_xI}$tgFNNLz|Hm-$Px}gX48t|FSJ*KU+1G#BBVq4d;OrQw>}3ljY`Xyx
zJBE|Zi$#uOYw}q;d#P;gx<9F`FGoV@&??4GTG*Mjvtzp13BoABUS($|(K6jtdfc{G
zX}tU;6Kr+mGC=L2WoIX~mrG^xixS4pUN4iGPbH(MgIs26KL<CTvTZu{UJ_1bsQ*cB
zXWw2SGc7*`<xlzl742e#|J?*JqO4QPTj+FA{!gM%$@tUl?CtDDwM;Iu3OjpFBQs6z
z<+a?tf4g6o+Qar}Lz}Afe}I#WQP$4gE8M=LC>|0}9L!i`9p`x!*so(Uy(UWsGbLU-
zq+c=>UgxC-+p|`goy_jpKT=$)i{-d}`;5W$c@jwif0W?*@;#4hNV6TTBWp-!O)Hg7
z$!^2is8qF*<UNBqT>rW%;OdY>*S){cwR-^R&;6aQInPPb*OTtA+Qt%~!vlL<Plr;$
z5I3SbG@XoXmXZPI5meedge1W&<WTKpy84YFea{eLSRYHMK^sWIp|xaoXBtTU%WAq8
zBIthVcw*>nChVeRq*=P(Mqaq)lkcV`GWMc?RMmFW1{c<mq{B8+T`-Cy=_v|aW1NZN
zaUp4rx<fh>hLhxn@pRuVgG`pLCw-=x`2D`1(!Tz5zo;Kw|6V~l8+|1<Bprv5`6p9|
z&aIJreE1)W>zX}uU0+L*Fjs=r3?|sl7?KEk$gQTfX8+ZP?u|>yxg+DKbmU)z9o*LJ
z+7`M`9Zfp<cwuCAXI<#JK9#q#;YpW}r*%oB6dF!S=PhI`v7D}@Dk|OhmPp6<Aefsw
zIhwVf>N=(~$u+O2@h`rhS~hiRbD|fOYAZ?d^M2B~x0m=&#uDe$&LnT$3LcwXa4rGX
z+@a!v7&2h!OOns)$;^dGbl-I=8HkS}@TO8~t)@BT=;0Mq>iZdK_Se%j$DcG4GRXY;
zS;Y3^0J<MFo2qdylk``fB>Cwoa?5r$j{q@iso;nk`SnK%6$CyZB}q3j<28-0^QuTP
zX&v2P(Gs0!I_V#4M-DBiAu|trNHRZ*bk_Ni&ev1PtygW${?UabxxZ0WPwyeNa@!?R
zeHTm=59W{)kIs{%!xVC>V;xD<ZJ*7U6LcT?B~iS&OfG(GtA}eS8Q$27=yvrbo^+8+
zmQnNC{j`a$<@4z};1y|(-bVLV+Z=spu@T+3Ix=?uCi!lkMfbh4$j9|<^>A+{olXnM
zd@l`|*>;79W_gn4smL~lwy$QAH@Wr8UAlTEkSon?eZ#%?bl<rXX;u``{lJ5yGt!f#
z_rFX_hI_R=xzt~&IAZ|$I3|jm=owB=y=V-XOsOREE^YNLRFlrSZ;7bNlkWR0qwAAS
zq+{nz*D2SDtzZc``l&ZD>}~rZR%TNhr{N>S`@c#}s+G%0wf#O)?ff&Tp4&o_(k?{0
zLr0R%8Y*4#H#u~3GEtmwp!)$Y=-&8|G>1GVwuimxK3q!rqgN5nv>cN6enOfXs_1%#
z?Aq+^Rg;o>M;l!UnF;=i>ixTfBzEZpYk5RX_r#4#vwITttt281S5oaik&|Yz8{L1M
zLGp}J;_UXn{<MMa<s31DY@?R;^&tL7`E+lKXzMH!?-1DEn^ctx>3+&fDn1oVCOeFz
zYoFa@=G(tWp4NlR9DYsjMCUmq`9V+DPZp88nw@l=c98TvG$fZ_CiAP>9_8`DWM1}?
zs?liMK@{cfNM!#LiPr5U^H-0O<m73RENJU$I@~9djyzGXh@sL43My5lkb%!<)73nM
zbPl#TQFfI~j(SWwTldlR%p+pnsw5qiFWG&dwo#@;L!Pd?Nus6#x_=o);H?U}&VEm|
zKbJ|@9S&3)x1QQ*MmpW!xIu3~>P*s{^*y<j=uDjMok-`#Ez*%VkWNh#$(gZK0j~{I
z+W9n3?|<-Z@@_XnO7?j~vHL0A&%RD3mw!gEge_FR+zgUW{+#q*smbKxon)YMSJG+i
zM%RPmsdUpfRM#!@2(@)J$@RSnd+tx-{A4CcW-gJ_`yX0QM86y*(WZ?AW9O4<hwB8M
zKaxD%@{aDGe?`U&|56QB9U}eW#nfhlI+DpATj}1htw*^VMm&Bah-c0Y;@{u)y%eR>
zeP9q_{r>{WW@qY5q$y!!Ao^>%dMQaMEtsxTrqFeMBpDbqnCOO<kohzNX`1H}kzLzI
zsB4?T{4|sdXMabv4E;d&e=nsL9bZeR)VBWd%45Rve#B`@jUbB6kpwswM|BO4r()+g
zGTeBO<nvmHXj>(jAJ$5+uEU9R$y(A6+(`PPe<J<baipITN&59pbg!(XYqC9Q{=A%=
z$Vw+3S=-D?V;f8bf3G6C-zC(5hZhmJ`v#J%KS1DrFsYT<ZJ$DNw|Kgyd_wYX+Xk2s
zJBaSH5yZ3lDqYK5$&6<l$v4iV`__$ANuvW{v;QM`<T7ITWsQxf`L^C|uf)zyZs%Yo
zi5!zHxm~$hiff-gI9wg^<m7fAL&>cm4}0A2J<sFntYdNA^exqXwl}rS6ED(V{1q9{
zJ|M%5ZEu70nFR7tMO4YD`Q*fscj*7+cIE~mo!-{nmcO8Tjh3!k>`8TpiKshcHY~UM
zd@a?+Vj<GPW-?&SlSAHIM*2(v-OnCMn#X@47eCG*r@!t^jt&_`rAddWg;u;k741e3
zLH{qe%km@DdrRpl=EjqO*=>`mG3}_i`k*h9+uc}4@&|1XYhpX17=?+N+^+5kxv~ZC
zw%l$ZX2Wv3S<}hnZ@z?jjZRu__uYM}ck@81aeCV<!SysT*V7wgvpe4Q=Fj$|W<PO8
zpb|ToBKRB(s^0yM237Br!8MIQGbCN?5b6IktPQKsI-faG_KP;X@x8a>{=3B|p*L?+
zBTB#j#}W7Q5AFr`g3#~4^25qc;QWtU=#^c*d>zgIRu87pXhW42&AFxfM-<qaKZV4R
zDH{g|-I#tiksM}T)4b#elTwFzcr)u#kUPr!u^GuRCIydHcAP0$0HeN4uR2)uV^Y3G
z+nitwrvdk84o!sN0A^1vG*2?ym%`Ok%!b|c{+(ueDj*GH#wfrY#I)OqB$#<b<6{Uj
zY$n*wFp~#>JCs>80f4j2oWId9VN7l%xX&>z)V+r@za@Y)g4vV+VI*VdfZTb;dKF$o
zG0R;6zrd^(P!`Q7_k;Q(^G`X=zb`T0=^%|^TBs|JWoCGQEsl9{2Dy0V{SBB;U;=}H
zPh`fPh43;{PyO%}rrj|(lf=wyhWA&QAnLHLG1t#R^Exxb7v__h#B)gQF>lCjHX|Jh
zyZ4!pMQH0BX3!B9?Vrm`xC%rbGxiEREnqAQ!2OUZPX@4%SwQ_?5#!JsNf~pm8U`zv
zY?_5VVean*;3;FEQRf+B{TdBi%?vvQTn#hp1B7*qFRedbGAo)<rFy1m4TKF$(R(DX
zn7b7)YkSQ|5>fbushtREBQtd_5O0~8FOh3vLVLi|_snngFxbr8evOKLV9bdqYh@hh
z`8r5Oc1GDwNt`D<bd}_{^01HppM_CBGwA*#K-T%tlxh9hi!iid*EE>@<HkDNZ=5v7
zhQ%|fce(dDRQkQ71>Be3$8qgHZ!qKox?veE8#sUlGJj?PR(Yf@mu3XPob2xx_`u`?
zc7coS`U;T%qLSX~j+T&L>IxFJvLmc<apxdW_{o|7X>?9s4A*;hpK6Ei-;tS1Ysy{B
zUJMj+XXew(sIm()0rNijUS>X4{xVl)NjH4keoP2Wf=@6zOQG_Xxibzfw=hF#lIbM5
zv;>-aB`+tznM0DTG@&{w>2LzM6B3_&@HRqnel>7O5=STCZc9eI#d;m%FTU_!H=v;1
zj^ClxdDJ}6^&7DV@{zR?XwFSV#6tFa&keY`F&*S^A&6PK61s`ZguhYAOlD9tI-u7~
zx8wiU_<Yh&Ak_SUK}6o`uX|{)-YYP;$om-nMPJnS(!ZRYq#wmR<hC!jj6l`;2bQDT
z8n9SEI}Kz?;q;*SzG(Qb62F5VU!S`UKL+<bizhu~XA-VM1890Ptdyoe;~jRPbm~{f
z;MklmXpC8Or5kkCyqE}{Ka@RDx^<NfatG$BJ1XbQ^xp(-FJ{p@n*SVO2GDnZk|~oR
zImdM2KzfPUumEnyGHu?+F>UV0Gj0ASFl`k`WZG(QnIW&`*O|78Br{Z#w)cP^`vHw$
z^vlQ98b!Xee|QF7cm6L9o_4>5rjYfpZR&uA>=Qo^*Z$KyfgJb|eYb3A#;<T@WNro|
zqoaO-M-$#Ig6~rn(L!scN(Q>Q>umP_GiClW3zVO3=#6aGM*0vx5Bdk!ug>;^@zKVc
zkWUGq<?GyC^hNGqp0F_Jz!cjKf@miby9iltX4PAeA7uvZhHJ-|>ohAk$vFK3j#EtL
zD*#V3F*KrvGw%o&!OX@>kG}4e3M#RT-($ezn9*U-jAzbMAm9dbe;WWP%)U#|yveX3
zs7ek~Mqha@<CIOawLGS_FYuL27k40@GUKQ+&zMXVR2!MP6yV=7w(c<4#LV3V;cm&@
z_R!oT+1U((&XNiPgoh>LK0$IsqB{&SZ%OujcpoG=dJ<&8lK$&a79y#f2izqIw;d`m
zlA6s@JpWip??jlmDY112B2`jFkL|7`y%kBm<Zw3#izRdDnUzSy?}0Cu_(!90D<!Mm
zAooIYK!xUNlnmL3y6mw3xE^Fq_MMdgxY>7fg{Hgx2#mopZ~O8>a2~bK>;lcx_J3}t
z`EQ{8`sqNNxA#kfr6~I)Ye0I<e&h_`uiFp8<iG80>Li&6P}h0Y$aY)S7xnI5yjA|c
zvT>U*A(D-+@Pe%g9tpUgbhaGV)%_&@_b#?8osar|{^N3x_P$ntYrn}~;5xvT+8G>Q
zb)tyKkXiKR4bNK($taJfXz#JBX29VIkJdqTx>AbkcO4udU)V|uycH>pDE-ZU0<P=l
zG=O2Fr2utEkiVySaiaXSGmKuAyG=vU4fz<VSh{?$3}xB!O}k*LKyI6*1XBhZwgjrL
z*ry|)<DmGx6?OGcoEi_+Xw~RM2oqF=Z(-R(^L!3+2Q}QK|9khtnU55uC}3hJa97Oy
zhS;mDgqerI4I|b$6NKeVkq_Rt3T8qul7o`uR2VxXDG%e&{zoKDG|}>wbcjWAOro)a
z&T+|zPH@^+;@*hFPckbRH2xB=?~x0TG{r&llw|f~RQ$B$+CF%BQL_C!l1q}+v_`)t
z>2?@iWJ~_I1)p;yX|$Nll`PH$E??rc0#$z?X+Hu&+e3-j6P^}IoaqfMmh6i{)k`E>
z@}OEO>AV5CGRZiK!Bt4Q{0h>?5`PMlR!RoFgQHI+(PJTeF0ua=Y*msO6=12BOdbG0
zjig5)sCU@E`VVCe_6G`)INIBN0>Cc&;05r0x6R(A4&Lms_oB&si2Y>xlF!&ztp+~Z
zJ}nlx`}Y2b63cS!2bRKMo_$j|gb(bG(IT|K{v*XL3hnKCA}O*Lmm(>#x2^*Gk-eUJ
zuX6iQOV9`v_94N@J+b%f3tXjrOCrdg+1t`{kbQ1{mPX|l_Fw)1?rM7ly(+c#5(=5r
z*~d0RwcdWV2{aA%dnr2i+P<I{gm3H@dLj4L{`MPGt;v2SjSBDW?-c{rY~MolZLv>L
zLi3}&bsZ|`Abk{v>h6?oSqGt$w2zHK%e$qjKp1qEF3v|qU8FC5M=e~X?a#uXo3syg
zVEd%EK7eh%bjL#gJ*01sL(@|_<ZqZiC{5Nt^N@7XD3l$M&KZEjTRLP80LP_QE<nXc
zdX{2)e$twJcyU77p6U`HUHiy}!jsZ}@iNN-r3(+hiy-NiIJh4o{gr}_XQb`-0C842
zd^8YY(uZFo7cQOK5o{6Cjuc5bFYPlLxG3rR(GW&U6LawjT$DQH0uU<|m&2JjX;6QV
zB}gBh13XbWx(igUNc(Cz^nXdx8Ih>rHR&2G9c0&~U!(zXLpqd)7b#LrPb8_*+u0DN
zNi%LhGhI5t0=I8VJ99|xNKcQ3N~ZKMwmD>3(o3Vka!=}h5YF6}aui+7k*>`~1@ojE
zhk+$usy6{pAiau?+9rD_jiJDFk@UL?B*oJ2ok8<Rs%k~mN~P|!0<Dm~zXO`b(rQN}
zmD0msLglG6qyQ$KOTX_4VU;xVA(9%Yyf-Y>N+)bUlf0A;(}1O3+W0T1Ur8^t!28$I
zL&Yd-l+HK+fbFgH*FVAbPHLL~)%Vg$Z0g89NH_h4_G*#-bP75<Wcz8+;UKd-1JF^%
zU<*aIOIF?)uI-jp&PH4Ak&Q9Iu8Zsf3*26r4=pI%WNUe7y35=a!oq%;q7W7i$hQ0d
zoTn^(8iZapnQuIF4$J%}!^9C;+G7|zDyz8+;W62vap3lm9q0yCUs>28;7`apB%^`-
zWlM%Y<)rKkg&j`GKD|$Gkj(Wc070_aNaW7QKAj3np|Ul!UJa9t3WDZ2nNJctjF9PQ
zVGt>^O`)&jf~@&DxT9q=XtcZ}8<qo_7}@V7up1`}r|59JOh#+$L|LaCs9csc{RMoI
z?8y<pugcod<SSox^e}P{WP@n2QYf1~7Pul=z-u^DBAYWEWshX7;SiQ#egb&8Y`Ts1
zP#(+nFletQviB5sdMf*Z#@uJJsp;@^hrIuFBo6W`qabvYzy1Y2?UJ{WGrQ&2h61oh
z{*Fcu7kPXdEbWzdp8;-nxhqA__Q{<ne&r!|qfyOMejyo#4#`CY0Egw>9O(P=mg@`9
zP)Fq}uR-UyJb+?+KJweNa?6t68;RUKdD4&2%#lB>KrUDAHXlCa%cl(o;DNls1-Xav
zXEbv!lyCYHn#FRjKFF2G&y9e;rSd*3a%FNy3Jg`qrx`%~Sne1~@#jjpH^t<h$}g-$
z4WG-WN5I7@dG`$fR?CYQK($70xdlrv<@;$2u9rtef#$Wm{cYgh$hSv9vq?Vo7kKeb
z?plYk5Av$Ds9}rTA5jNct32BmDm&QWuVG;)yZkQ79NBwKwEhccyO1=3-ToRT&a<iG
zVIqn>brfvT?3s&b;EU`<+E0mLD=2Id%f@rC8_&-B3p5F=&=JDRY;h8DSJ<v|QFfKB
z%K+y!wv=YB$*k)<sN7&#3aH;?eIG!W$~xYJA=@qXU;yl<vy**Ln88XY*mQ?wDSUI6
z{p16lVHP`%hK_8uc^q>0*&+1obJ-VPA<1KV((L~M>xMm3SphrF9*tMXCN{$RBDRP&
z0ZQ0m*lU$NVzocQwK8__H?UjIX4b&olkTjWGqRQJz;mE^&T6x%@!9hf9jjqGO@pwO
zUE<Zhv%z+cB1etv(ut70V;vl!@t%E2q1zVLM&J8KcHRV--NEf13ZVn%<c^#pH}^R_
z+r_;<1M9oF`a~pqxcJWiaN!Q!g=c#?Z-h}~Zk*4bz`1kVuOZpbeX|#u2e>VN1MbO{
z*usJE;$B`wa)`U(h!#1_=@Q`6b<Sf9>Y2<rk3({kbNv&-R8I2;%%^i-QvC5YcjE>u
z-Qh030%;~^;b1U}Yxo|*dtB2*klp77(JC;9dvXLU`CJ2Sm_6VY(6s*{cXSy=stdWL
z2VlO0+jxpvl>59Fa^>7PACOjX`NaK%`?C^dm7H=n@Xxr<$AJ4eXHT8p3vR&^RHmBC
z4uyxcT<{D4>NvapP^stU&qC6`1y-W$HMgY(-oN3LlOb&4{5@!<{*L>bW;xAV`*=9@
zfot~#*jl;wzaiP77(^4poeC}uIY)&Ly@yVUdfH6ht>~A5#91*S0F`i21a5*eu8M=S
zZRn<0{REEgQ|$8qe81x2LTGv@YIY;%src?VSPm(S4h+7O!-~cf*!5QI3xm#4MG`GL
zd=y{BgUwfQ3j66Ye}$Un2LX!mY~)TU9yp*frxkzX!0jM~j=Hd51?PpbGm6`fkqcEw
zKZh4#ihP>3o>NrwNFo&aXAnjzPEs#<L7|}yXj`;m){o%6q%gcd5~Jv_7M00U45g50
zfnpYI)I3x~CIerjxD<}0SP?iEb{{Ez?*~Uq6_Y5wTcMcQAGpVgA82k@so1m?xTlKq
zv%vXWv4%#!DuvT%2x}Bu`$MHxQ4@h&JzjAHVr2~qMH=w06=jo=yis6d1rspEh$<va
z3fUx7ty!^{%zsd9U5HwIRM^LWv{m6mL39T`)g5d*`3HBwy^G(jMwt_TwL8f6@T;#v
z#hG6l1l(SJd?7Sl`MIy4;?CQ?*#Vt>yqxyn4)7yrI_JS3-GM?cK6g5R2l=$006fgc
zYN2w3U+W7%6hHGj2ruwW)IVM1JEfz!F7c|R@Hdvf_#3>4;}_5ulfW;OqAZa&BVZxB
z!Y_6MOA;^AeDxY1XFCi_*ZG8Bk-fp2^+2TXQDdQ+%CDx7eH#B$EqqGnN3H?sZQk`e
z<TCkow5+?!Z>EjpY+gkM@AC_9L72-A*FYtYZ|(<65BPjDo<RZczZez@`QsE6FXE3@
zK;;qtS4Tu@WTpH9+I27IKhRROf-j=Bc*0+zsY@k)v<k^HUiCAC&-sIUK=XpXaS6g|
zzCA@qYx#?`@lwZsm;<tUzA6M|4ZI%>-mm$xYFK*1=OJb-YvM<{AbH2%7zlgK{L^ZC
ze19MKI+_uD<b^UITKN}xSaJ|HPylbIFia2kj|qopJ#t)FMsI?zQ1c5^{Dk(m;f%j9
zei*z65W1X)`BQ@GJ^-hMuCzN9B)qjp5-hmHLFJ4P+y%K%p`4ZlVZtyhm29$e!lX=C
ziV(tSMi428G~<gBe0W&8AjHrr@S;#T94eQD&0S$PR#<Zh^^Fs_B0Q!9VN*7eM8VGw
z!X&}7KQylj!)e`iUD!Y|&1B)r!^qtf2AxOCqzb)HAa_d$nhSfjbfL%|erE{pS0Z~y
zaPdR#u26Ifxh$cYhLLRH%a<U%FI=T(pDV;106tF$D@54?p=>8|1%kW-aD~DY8lZ~=
zDJ>04gwH6v{76`Q0k|^Zb`hK@7mAjG`mylIF}VH2CTzb8ou@(zMe&{qw@tuT2~%jB
z_Jt684oQoU91J!m(Q^e7PqCKflwM-F8+<w_ju{5?hs20-B!|WDHxM2XuT!wuTU>Dq
zfTN<?2!qGP0*ZF}i19jj;VTY44xju)n>ikCoDdh2H~!);g8&Q=yL3nHr1;?qECq@#
z?|=vrJ!yV_M!e_`woox|I)oXb$7`tE5r3fmHB)q@58$pCLfveZxM3iYd*ajgNV3Jp
z+mYNC`_kx;Bi=D1$rT6KE+WknCyD^(i;dr*7Nz1j1%zc{UL|V(Sp4KHl4s%v3XVM&
zuhU+4l{oAlBrn9NU%-5|IPEr)8Zq-vIc(s6r%VdIcDYpsNLPmkXy9(miI8+(bq{s;
zENB_L?GfG$a$C>O=~TeyEw14EqJbKt*XnCf>V1h;Q+*h!ZQsrn@T*@i_JCwxK4PHX
zfBXbc4EQb&qyx(-$UG=zEKpx<8VCKaPhLd@2Ct}wfguS8AsHIC5^Td9qj4QR!47OA
z=F%?8NSo^;(2aJ>z;(=YI+!%J`81Tq`C=PMHvT|ws7?qt0=K4BkAi$bRXXlhy9|cO
zt<Te7U?;QW8~EbR{9{G#81tnbY9|=CIbb}^g#HfU8D;}L!f?iPmjxRC_p&|qL(P@7
zl~O<I#&*wyX?M1T<`etaPiXMl&(1u6vIFc}ijR1(YbeU*$^K5$5iiz6i-Ln}9z_-o
zv8(@q@Gz^PQ&2}(V+|5-)^ZF+kF!fO;Phdqe+l6U_8*$H`Lp>nI}KnD+Nc#yvXQiK
z4`c&>1tN%D@E?2&W?REh7Q!~pK-n2~=O84Z?597&i?i&@m9QJe*0cxdId+f)NjU39
z`ymnRQ`$m^WaIyU@H{($B7RY9)*=Wmu<lY=h-SkCBp2B=ZnRRk#IB>cMhv_94WzN`
z_cTJqvAbze5YO@(;Y<QM?Fjr%WXs*)(`7dQGRm&7>za@xu>r9VUT1%!c1mW)=-}uL
zHiV|}DeSE=5Z+`n$G}1=8}9>W(%8@HVfGd~!k<<Ox7m!rFp<If{cn<7k%CswWJmP@
z{w_P^A%I!zY9(myv8#teGn?&`1(jSjh)DC;FDMqB&n~8e91qx53P2UG*%bSG$QE~l
zW+D4{32I-&UX_Ehn4Ll9OW2KfX{YWH`|=+&X({V62(>6<gS&#JoV`QOzJeW73Yy1k
z2F3iIu)DrT)hgL`6zP1*meI238T&Qaea;qAEVYUqH3wxc*iIXPt7az-MOh7Nwjfu_
z@?|hz$BsCR<Rv@cI_%l%+2ItnZ(w_kf)}sYLuPpTnjPQ{;2U;pG7L7d?P?%=%TDV8
zmG|uU3M9?!bvjG<k$rp=nyu_y+KS)732ke7t_KZePTYrUpx(oEI*7!X^I)L4mup!G
zxGR@a3l%pT7kUbX?wm*)oclO$v<YVE8VWNX;Qm<!QV;G&nlyWIObv2g+?6um4|2=s
z6*|Oi`5n0<oD+o|yg3!Qc9bhhhNS?mb_J4?T)7t<J;kMt0^l@PT#g0`<ix+B8N}K8
zi)h(kZs1$!gm7_c(467QY0oi~^Pp(hS*|DoK80}sSD|^1duIVYoJ-pXl?ZNwJ%o{*
z3kBfMbJu1=7{%SEiSz}|X(V#d+<@P}d6D}-D~(Isbvh{(!+BCfBbKw+cvLNpQ=NvV
z@!UxY{3mcrXy%c~4fz`Q%iMufAg*wgAt+1Y3Mis@m1~Va?i#13e&{+E{RG^}oP!g}
zZg6*c!kL@g1zPN-a=XTYERAd31eIG{6!zM%d<mfL^EMZjXTw*O!40SA-yLr3AQ;T#
z{K&<-+>Ip=W^qBaP`Ss2e*;U|+=jj2zR#sohn&OBm;%yVj_ZmfkDE^&MLu_sRs|2Z
z$_n5LxKB4DdC0MJ>amd1eh1DXE`gq8G52CE?G%-8>vq7?N8B?b%$IVry}@0^4WpwP
z<=kkB(o}FkbfDugxBV|@KH+3aXjXDjk;pyehJ{1(8Ry>~n$J0&Vi8r`>5H)Rg8Qv2
z%Bs1uv~Z~5&fSOITFy!hTgPeZanb-MmVTxANIhpf4@3iZZ6QcsaXY-O^)vK3MJGv*
zD7ycPqGO7Vji|(N#ZlTH^HEe#P}o-?(5|DOVvXmQ2HW^GaN(q)j<&o`DK=k*C#Mxt
zX*n0D_+}}RAjSMONP-oy%kdmS6fAvhXB2a(`wmsSaE0l!3idS0!WCxf0U{JJv^yE8
z$lZ<HdBrk%rK1#Ux}pXb6#IRVi&lgmfW3<fC)+I0TvBYIO`#aY1^RYl6+<Yv7^esu
z0@ZlM!x!){L6JsNgG9vwn!H?A7=D3IR}`J-%tDf4VLsqj6`cknxu#f1Q~K+Q>QHDV
zE2e#e<c8wMD{v-7kxE1HO~veYpiWgx9*1pT8HU7I0B<Q|ESe`>@%II^*=@yY>P<5g
zwKP26QA`YjW~SmhIu~(Q@irBXX5nxIXznSl4aK9%R+KCN_kBerg@SVw`b5~xRm^dM
zW}e~`3Z3OEI?#U21I4k9&@52+t)b5Rp<?%1&=e~2>4avHBGLnODpoWO1)@aZK{Ja-
zilUqFsZ?=eI&x)-Zcgy&v0~#Kusu=4&@`!1v4*0GPZi!1fqSNqMuX+K;>rxDR4JCy
zYxhENpEl&G6-&yHt5NjmM3ZSO>v{uNrzoV8ZZ8$u4?xr_eo8`}8WbZFq54WOjt&sM
zR{U9n+#AIt8Z;Xf-_L>Yt>W>gAZ=1a3_<Rl!by!be6P@(;6=0I+vO<xplBJ6CTUSr
zqyzp@F&`&&unc^#03O<Q@E)|}bKv*-fOIEce+E)VehDqfcky~}s5<d3`#`#z?=lxO
zd-%wc&~)Y>MWNa*{FY#7?&XJ7!ICR~pI!(z{^BY$r90oW4+i(~0v*KI&ue@DKfrIJ
zJp~V5ei1lN8$VzsRK55>ns6WHA1{ZcBm9$XDD>tBe~a8vKHvh9WBf0Z;LLHp2b}`+
z;V)}o(3j8Jhs2McHxI%S{JxoJJb(UuKfnX{jNgzu$<Gadg;Ttv1uUoeSXw3o^7kkn
z7sT80M!;?`Kb+2Xhwx5QkUPWM(W%r>UOolfXZgrp@H>oO{}poQcr&eO!}%}i8;js)
z&`G#RepwW9=lNqeEro@ydn6paz^|fdOf)~D2)T>=#cz<i#19?^cnp7;0@AU(%|@%c
zIDTsbT#V;G`~qnL?>-ZxiF|q>gqQg)=ODboms2Aq@y=B!yUMrF>g*cdvIL~p`KqDF
zCG+t|;l&L;kmAcJ{M3J8=_dc%S@@L7|JQ^hjZZuVXKwK=A;_iktJ_g$ew+8&3=^4r
z2)%)K`B@ZQ&*DccLqpx;7sr4!o0koR=6(LW5tefJ0vh>q`9?aloX6L>!C*eG79o7V
z|J?#W0e^fngb(=*c}NQR9)WPCi0@2Gy<&bWg@#J_&7lImzejwZ*QiA)KVubuW&A}~
z6qfS~=qzmofAlW^AM-~xLimK=90Sct{(L=Xp7MhxLgg91{Q^{;^Y=TUtcp*fkoyb%
z6&*pU<~7?;r5b(-?F`rQpDstPjt^Ug<R!lvrzC7xeMixes|NlDI!E@37kWeWHUA}j
zM{oEB5j2gw*C3dG%a5R)peDX2x&MyuLS68CKJzC4ntA6`lzregu7R+H*U~P;NB$wj
zEnE4<g=m=_LL6Ce5S;fSw^Jx$V8P}nOrcJ9moWbl@J>PjjYYeK>w&PlM_5WxP-kI(
zG7v6818so02}4!_;4TErMsA<L8bRYBJS+vkQ+P#dJTGA*?JXP@#?bq8L|8r({(1|G
z>46>>-r?sjG9O_99enk*39;Ld`U^2MNe>X*oMG^!5WgBN6ev{RMlMKLTn}Kd&{GAw
zp~9PGNX`oE1qj20JJm38P8d&twQ!-~3AiJKYqUg&6t>bS{`0~>dLmK6mc?-Nf)M2o
z&1hjnAXqL6^TyM*$tB@0isr-!Dhk=h3MD~6#0f{kk;DrU`eGA=C2wFUQIIx+`?ApM
zB63%Rla+8gNzhk8<*LwUHX8Vvp!WJ{aC;lG2)^7Dl+>Z63PJtR25Ca{0ibUQe@=#-
zbfGgv;BE^uhXS1;?4}O<j*yTGl1!nL=4W?>F7(}G3CWw_%6;MHMC5XWrU^)Lh1Kgo
zohJmj!ce|2^((ME5EjyIaDk9xTMhg}A(vJrg+i1SIz_^Q!7x}Xw9=qdBJ86*&qqR^
zQrImOmePw?CcLQvpj>dE-Np)GEk!XO3)KUGdm@|~0?ta|@(GYV6*kgV#xp@01>tic
z-xq)?Vc;Qfz7W0@C`?r?jPnI)jqq~<q_x8MV*u6(QI8;eDIBC@M)ksvG^uY8%>STC
zUJ2(6F!)-irPuh4AfW(Jqp)BW;BSSx-6(4kJbJ>zcS5I40K6BT(MqUUu+oY34??$t
zC~Fal&dc#-e-yU1LqoL+^JoWWhuDweOb+6=eSp|0&TK}Rleo17!rdZ1OT6%+Gd(6}
z@z>t~a1q-*grj@KQ3Jv4DlQrioSS%q4pzB~d9=3PC+?9$Wxp6lQQHGz<UW}95T9+f
z!<X$TR#1S+OU(HJh=Zcv2hbc6KcyA@Ve#{7*gYbKA3@?R#(xRBN5$i`xI8A_p8(-;
zF+c;jk62p*p|AK4O{4w94fI-_5chh)dw;Qy0P_Lj_OH=~C&jnRp>j&Bq}aUev{*m~
zZvw^7=v+aNSWMB#VDVKY3PZ#Nze0FM{9`sOg^CS!@ae2L>mdMP;#ah@cTT)W3$k$W
z$1_lg5c^JrFjCA@gXO&V%|EadCDyfrGZ(~d6snIFizsXwBUW@kF4iUvdy6KG6A!)u
zX}p+v8A*aTpQ28Q;_Pjpxh&@2hutgUiU_bJi9_kU*Hv-US~TJ{abW=9*TrbsUr83L
z4xsFYxNjg#q=>Tv0k|n<3_y}9$|-D`CVmr-vRk5r_EXbETf3g{`?i>S7c?27K-_o4
zW#2<JQxs@V`>wc!mVQ~HpF6y`Cw9`pwQO<fY9#l?JWu$WBQ_obJXZ{Dg=QYYTPVvH
zr_(_9KzuSB1`EVXe?jG;xP)dmh2pSjNJ_*Gwo~x?k@#6TR7*wE&qyl7ks=Boi{4#P
z_Cy>^UDz|RTNr$LF0KzoS(Uh$MzI>v;ZGQ>6(=MDS0^USMnxOM<XJHIO6+w3ny<xB
z>I~k9VQFA#6qS19-iq^S*85%*U)!MCEVf?+nh)ZBI{nfj)<|IKqxdP!xLU;zQh2dL
znM8432W83?<aR1|(YNiW)P%wAE@gg4z@3!G9RS#^d`h!~J<2TVuAG$)d1y5kWn3*d
z_bM~rq0CkJ+zBjh%8j?_K!LmR0Y#$sDPMO0e!nt$4%iMT|2hRvJ(PbJz=Wsrb}0~E
z%FhQt<)G3`r$`Pd<7w@6SUF-NNRKFoQh3^1xpFX)qskezsQode*IvMnD=(jgijQ*g
zCrEsiqk|#zQ#$vek@bY~F^w_)%HAhX!vJL|t=Ud0|8;=ylyc%+<W4J>(DqWGvY{Wi
zgOoGq2WP=bM>_r%qHLk1`5EP|m4JsTUkB1RqHG=sl`y3{J&JS6lz}J<S59~j%?M==
zI@T4XY^4s>c0sv?I^AgHqUkUgqfBo=MPrp-<Wrn7ih9j><w#l<CMf;lpqZ$Aa}(T`
zl|4G4?27W6FX2U!@>e}@SC#2oKzdE7Zw27Ga_|?hl&l;f!u$<oHW^G&uGo*d+*D4c
zO_x-g(*0}T)0DciNNy>oT>&Cpxsk%mx0O3v0L)NMZx2g%lst`)naZUU=ew)iI3H|T
zN=pRT?kTIg!>4TJi9x{KSFRt4Bu5z=iLzX!`wnR4DX%%=q2((hXpZ$jnMqAqsI(oY
zE#D%gm;^+zGAs-ROO)+p5I$12{|Tz4%CX5vDwMaj!nMcBUTq;+Wx-9b)hd7Af?Cum
zOX)`nFO~i@jMXdS3&7H#?0*fMuay3D!sNBGu>mS?lz%@%8#XFOcSj}ODu1wTgd0uD
z0|o%!DKjXb@?P0vGjh$!*R-1Ype)0&R9TC%aTt=1N?S3?T9xK^Fuz0fBm@8lm4^c?
z?Nn(dz!^u?7>bbYQca;=&q-B4r?7Ub_J50Hk1E&=HFH*FO96LLeJpAZH}<N2*aWGY
zDy0)>+*Qj5f^?tiqnE>IgYC&!WIR>nw14HLDyFkw2UQW@!k0s;VH7(!ta?KW(j%%4
zgJ8j1HIg=<j;aEFgYcMY68-$-xGJ(eSbS9J)RMlc88of;Q%&H&c|xUM0zds#%x*Mq
zfXZ2l+)34;vmiUAs<yQQ;<T!f=52whlhc3*Qau?9KhLN<=7Ka-mF$PySyit`@F`5C
z`4lSWRKFSl2v?Oo0$YUYr{l;)s+?$Ab6)j;&cj8i{^<fQE~xfQMJ`%ZD1qA-RWn||
zi%Y7(G{VKG;`-Wvk5zf~fHY3kgSM*TRqH7@kf2&f9aExecqs6f;RV>Ps5)6;K1ua*
zFW9cC#1%-csb<royRO<to4d)XDEjH>4OQrAm`G7A+Xwhf)qGkXrm9vKq1Dn<^BI)g
zQuPg?ZRB)S!~h^}t9Y94WvF_5i)!Cd&7+OFOx3f4Aib+9F~HF*)k79O-BZ0d2hD8N
z%I$FUzG~+<2y;~ZTp-L<4O$8ld8+c;z~!qprGe~$YAnspAFBG=;6<T|iw0SdDjX*d
zY_ek2&-lfMtV9({f$>Kw*WU20R5kx5RLfN3rlZ>Bs>6NYOoi$mjhByAbKWBNL?t-~
z(x<9HZQC3wLwg9HtBy<npi1TT7A!AR77YN^sy`|2P@~GD$YZT4m5#;LsU%+jZhNWP
z)g9S-RTwo*gKD20a&J`eH2OBGj#97jRwbpfCY75L{C=kr>F1m8Re#d)v}V=dsc`#)
z%6ljbwx~w#1L;TA-X*AgtExT($qw~lYBfjo`<}q<QkTf#laqR6CJgPisc$ey_o#O?
z!9{2FKeYMiqJB!j>%Hm?OHe0Q^$ZnM+|<LWLF2Ce`y5pEsS|02>Y)~Bwdkq-7y~c7
z)Ls67PY2a0k6_}EdTo1f9#*?$L3l*{jOKmb>e%n##ZmQxASB1sw$hI%Jgz=Z@eUt#
z9EBfz)h8Ta&`+IS1%oHlaynAtuU@qrb_3KQg=mYD>P(uNo>K3`p*7iQ_3!ku1gc{w
zJ|3h#^%+!x)z41=7oy(f0<tq|b~H3Y)eDXwIjcTN4HTxHV*3Vm&#4W5&<R&JP(wwi
z&%Ogqq`G83Oq^G@qm@#WdJt`cTu>kJhQHBj-E#;ps{f{m-z9aO7XUHpXY_i+s*4Z8
ze4KjykKl|~&zT0-68`7Y74=FEWl8D|boA}2+C2zI#%0&k8&)8DUHvt!1(Ve?`+??$
zddwbhr>H~5z|u{1ya^`K)RLdUc1s=iIlM?$FQ?A(w)*J{<TBK6&H{Hw{gPHSch#3B
zA(y4b!AX2EYVXg0%T`~f-$>q9Cs3RtN8SD#1-`$0_2d|M`anICmKOzT^XI@nRO>nc
zQK*hbtW8#=t{jW@Dpu?0x78);Qv;AZQb*DDR;jvl5gaX3FOkAvx!N@WfC_a@CCDDD
z-_erniF)lMXjZDXQUCu`eQ!UgpQ+W@3be_dtD|W<xJrGAp5Y6%Yc=Xrt&VI5e2qG(
z7)h;qCpHLWb?RT9gZriWBgMz-)$8ivQ=?jE4`<%0O%xStQty5N;XCy-YM}S(r5!=m
ztnN&6jt^>_Ji#}jo=<U|k7^_RuGZG7UQdV}n%%ze%|Ww{wkmdN>XK3DsQHv$<XxJ+
zk0IQnX{O(;IBQnpkcG@e(`6Nsy_!=r3w71JYKDhynhcskxN8o*fN-B?@()P%Yev!F
z>!}$%4bFIJSPG9H)O=3oLJ!$AooHk0ux2eqwvTAs=?smxW?FaX9Mv!sQaPp>I~SzK
zHKVSe%tw><9Eq=HCWY?(H5s(w9DtD#!jqclPykM8lAj`XTH|>UNuVZ5i)Rp|ao&t7
z1#2cR1TI9w1;E}JjqUj};6pVX-a>j-6Z{sn2-h5V0M!W1)okP<HOr<z<-Dea;%HGC
zpU<IrL9;=EmWkHrZXmg+89y8TUedVvK{G~kZy;1+HD{=sjnnMjg|c{!D;=dt(A+5p
zb)shYH29RH*=wU6xT~7!Noe3}8s{Bw|GFmXH{_BvzH*qqp_#h@c2hK8j{x^g&7=sF
zrD|$hAxziwq;=43&1Kre$<REU3bH$z?N1=g)a<6o^IgrI>i}eF9?|yJJ&ng~*v-}q
zq80dkjaMeEk8?EYH<0FP7M+BN2O58h(-deH=0NA6#`p;;Q>dxx1ALKY;a@OOtcm^?
zNr}d{Z62jLETW>Nnk%%FEz_K!t)OxZPVnG6&=k^dEh{yh>GOT6>5>B6Gfn+90G?|U
z-DrJWr5POw?iZTZ^d?kmvgl+>jb?5za<!Vlbn>E3^X~@;Uus@10%^UbgBmmqngb<p
z`;}(q8gReX=u#nks~JiG&L)kS)@|=JLubI!drj_nkTq-KWe|SQEV_YQi)J;(a+~a<
z<~N!GwQ77q;l)m^jaDFz+L&$7*`;068D&n|S{k8uYrpe?aF2E<P5Pa+dCyShqOIzO
zWUn@jW-_kYsT2`)(<Wp==&rqGkK6(66*_3*q1_S=?>)6g^WlY;_LTwv+d*yFbl5$l
z?M#Of4{NJv`}~M@P&9PBwUzW+xTD&U^y(hd?x&g1aqa0`sQ76+(y!P~Xme--&R^?H
z0ha*n@3d2SQXBLb&-Ij6dKQg;S{v34Nuaif=3_zHpXpdZu(qcJ@DQ8!S`FIkjP{cd
z7!1>{i-Gi<wsQ%D;o4#vT_Utup5Ttu9-tBPymk=njz?)bE&|&H?J665iq>unK-FTj
zo-_xE)w)p-Cr;})2Q2a0&&mK#(0)o`v_$Q;T;wimC%gpp6|Ie52}F|iZ92HGYPYXK
za!vbI3Z3iPU)q-0TGcn8xv8Cf8%e5G*AbOT)6VY;gSWKG|B$3>m%azfZS8#8)yvQ>
z>Im2FXs^&FTc)<81FCda8!{NeEUgpu7x%SMSCPxnF0`FP%jRmot3sRPX~nL{<!gg`
z!ixvmOY|lcXd~%wFg(-_aRpnUR<jf;McTh+0#K|ibpuU_Higd5muWNAaHd@AzZUQc
z?I>DzJ=O+z0{28aJQGQ!)=vw-Q*GAYpnj$ub-)Jh=i1@TkXCD_%tD*gXvdbpM6LEQ
z9bm81uIUApm)i9^k*n9Pp9Go)ZJ`qNeWe|K0D#xp%wPcCXftWEx>5U)&fLA#wo(n>
zYadgHyjg3v3N7<N`_2)#7Oiy~%06n3O{4FxRokN)+&gr+^Z_~OHd8Efr*0fQSV!G|
zb5W;Vx*R&^;-niwlNT3V#sc8?>XIpb;i_9e3vxGIM|!W^b!8g>-=~{I74^`qqm{p>
zu7aW&Ub^TnpmI<bOTY0rr0a%`4aXRDwPzqbqH`S#HgBC~6;zMv8hQhNOgCu(>>k&>
z%|es<=(f?9<Esm#EiOOZzl-7830+4zPvo!LOzX`6-IPb*KB;q|dFv_NbSc{Tv~JTq
z<N|fS&~Or@`-!HC!Mfu~NNgcGZ#rIdMwgumV5shS21w89bQE_F(<NviJf~YtTOi@O
zzJ5SN=nCmejnvKh2CkjgwNMy6O1GB=%nLfFC4fikis@%W7j=#*z%S|C#{dwcD=I^k
zVs*E^Kv|q_#bLM|Z_~A--^C~Be11ccsEcNyb6NLcAS_+c9ryxlNxIpzIJ>ILr6BAz
z-H;z)>AKEs3{;YJu3_N5p<8hRl}OPgD<Qn8yEq%%sk%@)#g(Qj`vcUsbf0trJYDzI
z765MRE~TO@LuXq}oyi^D!~oPcQ&%|^G<S6_4lt3WyF&XT_jGj>0L<34qeaqvozHhD
z%h7dhLXxZVeF#f=I@e>s<?Gs6Abg;k<Of`V&OZjZhq~?52^H%8rcLf5-JkT=28wld
zwEbVAtF{r%BVAV?WJ`7bWWkv-oy#}SDc6ms?eq%W{K-&xth2rZ=@Z@8H2hZT8jb_-
zRQD5|8L848rBmrIbU*b+%U0|DdJLaxbY19ZeyuK$qCR!HKj=*IOWl-sRJ&d`mwrRu
zplj_%<KHWtSqHY)x>oZ0jjs1)7;Myi_71tXy8nFOQ<JU>o%w#J^Q76sd!5`9Y|XmI
zQ(^Ff?(0)fY0<fC1NTSWe|E6js^e-<-yQn?Dm*&}eL024cIwyAZx9^ye=AV7OaItL
z#~7XTEi@n8txu7laF4zlg%h3is$$T%=tb(8_UgYV2HsVlJ|14U>9>3VO?UkXIyJFR
zZ`lO+e!cuPG!N+GsMS66*T06Np87ocLm6KBBmE&fsNX=-ltcP}Yk(itbKt}e&h!SF
zm3r$hQ+VyD{!|zc$Mi$!(D-qEB9E&1=)<Uo@zsa@4HZBAzjOfYgudw=5`TRfbu<C`
z6gmWSQvcKgxl?*Cs_$w2Oqyi{>UA5?%t89(6UYVYk4`}@ME_Msz-?#reMcY-)%Q&W
z{;a+oeX3#l5wxdvPJf2ZPKE1BXs0<sKk_5WBK0$<fzRvvd<RFP^u1_D@PfX16WStL
zzw8ybFY32+Lvl$UcNg#&{SF^kh}C~WL5ev25MRLK^}}ibPq69VUI%xg{u3o=F6;64
z%JAXoH?<&1(kqJqysAH&3`Da2Nd*u$^l7eeEk$2LQ~I0w-i5%W>L1bJvNZi38q06#
zS?bZ!^%VlBZ|e_ihusYQT8gFK(O>-+)S3EWoxpilZ|j$WY?l7F0^slI?>_){w%&!-
z()aa~D87}WH_+>qs~_<L5P5pf&dBBK56*$g1AWdws1)df|3vPge#A%Q3iV4Lz>6Zi
zGmV?Y`r|b2mgw)-z~4vukm<;k>W}^fdu4j9Z8oyy`Yc*QROmx3z(3aKR>7wy`jQ`D
zsZ#GwUGP&q`x!`|>HTT<`?>yKI+R?c?>+^%7y5&AoUB@Z>>H5Q=u5njtJRNffM%V(
zECOD<)c^P;sO$9;v}l9|{p`N5@JjzNjZQwi);}19!Z-SfbkMp{KmP)RZ}ok9L$yi&
zh9-dT^Z~RKf3N?(2UME%-_ex*gFZh9-nZzlO@zuv{U83Y+p3pPkbH;1gug!_b1?iY
zgBLpuTP_3OXjpL=D!UARbOhYVFnS&S;Dl_qA;%p$dkiya<>qWSMl);|Lrs6s>@{>A
z3L00#tvr}_Gf4Y^#@%o=3duf03U#{s4Vxw-IbgU+^FR;7&{&Xp8dl7NikD#}9Z@@I
zxc32NhYa)9A~|emN55%5Vz`Jt*Cz8eZ2ujqM-6|upe=n2MbroS8cub9Gk%7tBFat}
zw$Y(Se}fa9Ukfm3&O&(7@Mi<KPZ>JU3w7G?{Wf?JXxJ`-JIL_w40sW2m_!kX5QFJc
z*ga$TZwqjthNUz?IBPgfJ2AE}14k>(a|ZJvaEBW<UPdm$FyRSwA`L_6@XL8abzcCZ
z46o=2&ILmaMRcPL9L;nu8a|u{;F94vwOWkf2ii=CH9T`g5@(3+1I>6trVeEZhOxI%
z!9>Gl4#{Q1J|&VXHp7A<q)7%J+P=POaG;RvHADSJSh{ZTFvCQ$;b%I+bHgyN5t=E6
zE!08XG$ag!YpI4rD*$PRpp$q$w+sU*WS(wFq<F+_!_(uaQifsGaG1Yi2%>%1OvAWk
zV7Y6s{tA{XgY6v!vF;fbQH&+qz)@WAzG3@)sOA`Ax}s{i24xx=KhIE_j<S4%f=(|z
zFyI&jK0HG-t=1nJIxK-Rg@))i5EdDZQE;-@AddxgiD9K5Tzh2D4uxi^;er<C%M9A5
zC@VMk+ES2K7(#;J>0?6?#iE`VB4~T4(lAg5;8R26Rk-%d&^sHX&kc37ZC+()q5}{w
z4Byj_*{Tg5?_s{i@Lyj5Y7LWXpjl@ay9z2V4P&c8U2pJIf~CQ*Z5=cl4bP{dW^WCf
z$Jl^xGK}<s>N`Wf1QfnEB)))Zv*8sTKKx*iQm~=L@Y@&2eKh#cA?#LzFaVD3F#es7
z$~YMBtwV07akDd69F5MN$n7%zx(Oznj3+5Jv)eeBj-T!^N?yVlXXE`DsI`l6zLEam
z$X?@ZoPCnH8fV@_p__5tXqb05ex$!0w9gp$2)X^nOzPJU7~7FE9>xW<P2*{7pi#-o
z=uV-ugT{SFQFh2^%7yvE#-HgMIbu9T+t}VlpZPF&)cEr}XdW}}r6A#P<4H_7Z89HY
z27M&H#!o2b;Ai~o5_C=&iwaOtf8+MOC<`!#2ZHUS(V4!HQ^x%iWIt`ZMr;2-<9Ry#
z5@d|bgl4d@Jq4jcj7~4Wa>jVG9V~?!PtlNb)+i5!N|-U@d$61{zM)y6E!>z$zcP$4
zy3nJHG}`(iId6>E181U)7v->f!FXymgwe(?CD6QRjG++CCF3oc(Zm>ECW9^3*ttJc
z;*2-?02gnJ`UyTI7~gM)N}{oNC;*p@l3xM8V*H9!l8h@70k~>2)_)G)t{LBKMB#Pg
zWcod1vQbaxiEbEI(V_knV;P0lZyG<NMocw^`~a0S<9UjU-!ggx;u)kHcb<S3w~Z@$
z0+(Std;)+w#)*AFooO6HtE#)k=5Nt5S;i=TaNaZO$3vKHw9TS`(S2j{8c1`D4<n$H
zYs|4n;R9o=7c3PRvu>gh9vW|paJbMYDL`3~G0z3&i;bQOAuKVjqJ_mH<8ykiN{ybh
zVk<LFpjkt?@%2{tRAC%Q(fP+l$y(r^80UNqLzTv}w$T7SHM*vt@R{)zaX&Y98G*to
z<6S!A^ujpY4Jy^fjTZr|G5$9nY_&#)7Nd2>m45L4rEy#+0QJT&+8b{$^0cykWt=Yo
z*=r*^3oLJp44naJG%7Cw{?=F)01umtyBX?l-WdbF2itq&5O?I7jjw&-_Xpz@+S+e1
z=Fw~Y(YTCi(Q4dHYlt1DepcihOlQWRzB^6Z=%}cp>4XUecbN<n32-v)PlDauroIYT
z+GDD91+}xu=NYJ7OmFEoDtk@)zonCZuBO3$aNo_eSO%cGDSi`F_nBT6!tQ?4FE)@K
zFfDnH#KZJ`3fMeNU(-P1WlGozm4hah0uhHy>`@30o3@pL`-tgsJj{EWMg}8y)Z|U;
z-D9TMGN>FkEv9&ak7-PQ+JEphjiPSW&$Q76CQg`&8<F!jxm*N3z;v0`2`5b}+Twbq
zV)`>ar%lV~@O+@D{xy;yQ+;2U2sY)~p%Njc?`d22jA<HmNuj2-R;ZjcStcPDX8NrQ
zRL+@L+6@agEuy~zYKt&USPn#_=~r6cpEs>cf=-mF_dJkZFx?D=Fxphp8LAgeA+%d`
z$&~&EDlw)$6pD^FWiLjOU<#mke4=UKLzG=MHBpyz#dJl5B+0af9@<sY%U5XFYo-A=
zkX$!yZVxY#Z6?(;q&G}v3%p1%jrj`ro2H*BQj}`4&jm2e)a3=-zh%163AuFBeEbP6
z*=>`G#?K7Xx%tT5G4-Lta+#)7I^lBHWbsD>XPF$=!L@rP%NCSno0=)&a^Ez|3iCOp
zuq`OdHQ5Sj6`N;D&jv8xH0}x59+(c%uY?OsFOLK9(6o@&VTGpOT~StKN=t-m#ip}|
zV4}oS*9Evorf<{1Qfd;Hpt;ISXXrN$<))rL!)}EMe_{(Co@q8MCZCwB|3anGlu0w>
zr>0#tT1`GP4Os-lb5qCPk*hLoqSfRJ(`Aa?Rhvq9BsHd~Q9#t1&gX!%&ZMCIp_ir|
zZ{S6}Y1K0T8cZwNp@CkR9v+9vYg14TINzA|Q18)by4w?#cxyUA<4BXqj}C0VGktoS
z-tPCNq)M1*HvLQ|PCl4c8o}LSdQLI0kESz+q0(xab`E7b%w7LPnS=TJsi4_u*4M+l
zqxpL?a=Xk)YLq#dSJ4Dxw^^JIz#jA9E3o8jewhdJF6Q{9$n7;dM!{cKbMLM+{<)b~
zE&|Zq9P&GoedbBD9@=m2oeRVP^N?b2dzj0bQRZnj)6~t&yqMOc2hGoEpgv??Qvu;&
zvzj)bkC+$qh6!)8WHjJM&1)(A<758JAC>Smd+Ct#GhgcmzzK794gJ9pfAb6aR0GT(
zDUxu~JcQ0woH8F+0lTNo&(DA@&>YYUNs#%{Y0w0lx5`n&5OeDeH1`?vTv`!?njh1-
zxU=SY`7jY?PU6sb=gh(Dk%XI5Xyp}Qev=87Nb@oySk9Y|uZ9I%l=%sDvlq-E2jOtE
zxzHKOMYAvcg6op`SU&JE=1X!|iZx5Ope)Y(<uoMm<}0)mPcT<cg!x4C?E_G`Y<}Mn
z+*izX*O5yyKWc%>Rr8j$NUoW0ehWj_%@JYnBH0}O4{$eZW;JzbDdt8BjNdfZ4u{=T
z^ZpAcOfygPK<<`#!3MCUn?I!>{cZE7>F_(lTpI%19rGJMc$jIv=>+b(X8RwYnPsjX
z3NP-NUFol5WSd)ep}FpxGdsgVj(I6<80MM}Wde|Awq2**E8iS<2s#hUIhSFuz&w-U
zpAXFiw4GOI-nSSgip;t6=LCw)SLj%6iCGm0^N-ARG>n#-{Ttv@nR#Lr$jZ$UI`>#%
zJ`oAPWAkR}wVs$WGEi1&uKyXyQ?utSlsz+7+NQ(AbMpZuOjMbty#(-uSsD(~YV!bE
z_STrc?hi|~=H)mLEUPp7?n3URIhqco)SDx3L$krWZYcbHWqw36``6|Qiq*d{=h-7^
zG<(v|eBYYCm<SJ>%;y)t?mP2}aR9tG4<AInHJj^b_vWKHZYgrD=0)^N;vJTpPhrBr
z(ijc=PRo~c?9CCKBvf`;utvhCX4ym0vfY;5GLY`E>{<t*vqeYSOfHr$X-2WvG9eu*
zu9k*ZFz9A^O6R`ZElLYi_E~0}rTFK5OOIhNaljI?3_2bb?{8tk(^51N_4Ts!iiF<>
zEz^9EJ7oEXR=9^P6BMZS5zBDeDDk$`)8yf(<xU=O$1DXMQ0?QE{?yI-ST+mb^tCvj
zLE>kb*A8}1Sn}y-tNxapiM0O^V40Q%nv<4GbTr|VWeOejI&BHrfF#gztp~V+EH3ny
zf`Tm-eUXG%g6N3;8OviM0HK!3Kj70@OE2oR!Yo}`l%2C=ry~is?4yWSgr$;)Pmz`#
zbaM8*Wzc5eqAZU75ZW$SsvOZ!(UvX!;l)MEI69_r$#R3v%EwrIDB2xsxwQ>!aX6KP
zT)d^j1mqGdb##m}(XyNlx?Q&PrNehuEI-joBFVB$3rklmMYPRy&2s)MEM2$!c^4ig
zTjs5Yg&UUdKS5cF&2q>UHN0s#90~KOmdiY7(kywsKy%BIn-7EOmJ|CSylv@H4oex9
z<N&bUv3OB^GcB5vpt)=Dh=WR&<>3M3?pY49D9g48AJJU*EvL4kEXVRqAaJ>stOGEV
zXW2$S^~|?;&01!(X$}KbXt|XQYekll(*PG+g6G18QcFe{jFwqqdcx^)i~m0;tFWwm
z55~uqq%z>1SXLp9CabjUqQ2^>#g&c-KC^VELG!t#y**s0vRo@g?uEs=94=H_UV9^{
zvAELNzFJH7wm*7WXW38+?w6JxKcKMQGKPMA*<kTo4$@baT&l@yOFr#@zOnezo6=~J
zg(G=uk?Y`0lcf*+g!P@}8`@udZ~2;juH9_8O$+D`7P~`8S}aL!F!<5(=r~kbEhA`L
z-eGlFZv&}=^)3ZwcUq^@AJcHOHqm+NUDkg-0_bF2NJrCmTU#<vwLMnG8?HH9@2*9e
zi`9uv3GB62(Rbo%?XeA{ZdQNVQggR9^n#^*)+QP>_gfc<uyDZo%U?)5tV#5hds;`H
zq|@(S)<tr#9kj;L36(=u^-sthw&qO+%@ON{ry%vV&h7xVqt?&=glosFh4d%Ij$0k*
zx8pw6iGM@I*SeNgNPgCF(cnH|)%O6v-})zQO$S(Ctw-5OYvKl&KV{wg7#2=jdmv0|
zlLcBAQa2uC?Mg#huyqP;0)$wnQ!jPK8u15`Q0pQ(v3J(`^EzmTS#wr{`<(UoBqZV1
zRdiA+!rJ`@cpquKcLpZTTPG}oFv?oe1kMZAfh*u|v~}q|wBbeTj8br3vfAzdZi}%N
z=Akgw`b`$HaaNyl6vkUe(>c5Z>$5rt6Rl}~!0u(MQ#?qoSj(zmDaktRbNF=Ky0bmt
z$=2#yaQlX}bQV-ntOXfRxoPdUAI_v&U(yMnH0uER%5Pb(Qt&d}`Z^t&w{6zKJ#aC@
zI;;|HdB?hlj$&q7KNbUV*II6Y!&%nP==WgvtaE5TG~3!M6L#-g(*z_rR$mG#<XSg7
z!NWXjxC>PBt=F%E`+?Q&|B-avaa~s5KL?pMY?#Jp@4c5+YST<xYGs*LX4=lQ@>{9-
zVaS#}6=f=*2!hH`5kZhW1VLoTl09V$g8bg6-(Tl-?mg>XKF@v5x)1Mxuhw=2r2*<}
zCtJW!Z#(x0>}{|OqvPSOt#uPQFpajM6q7aCR;Pos+4d9qz-o)Fcq>-lYWo$Hq3+rK
zkJ{qeY-7ovZ?|1e5mtxo{uHR_wEcJkK$opIm1?_fmsG>-9@{Ue4%=%x-2u>NyLc%;
zzpd+akPO(Ka{)GJ%duuc+I`!nvjB!{&u@XIVO!k;7&Bt)Q3|1>w%<I2g=4mE)Mq(v
zd*&6)P1tTPg)t9oA1C%nTQ?;XPT9^xfbya3MIlx=ZF^3IMa<YfMH#b4w!hM4omtyc
z<nh}vVm*P`GxYnZ2I0VH+KKIUWJGNSILug2eyS5=)jI&rjO0FWxG?6Cui(m9)D839
z7>`kq?arv9Za@#lg3BN|!pQs<bDoUMC@Az|?5lt<Z$>V?D0~<rufR}WhJH0LKgOS5
zgT$YabBJ=F0gQU;JPKq?Jqr-TupuWun6a7CEg_64dsupuv58(S#~52yf-#g~_Y1J&
zjGp%aPB6MDZx_axmSao88O|qwMKD6?)ey;O^MFk!8Ad9-oMQNpS0BSz6%8zwF*k^E
zpm7XaN_3oNyugNSXBc7=XyO^CGq9$!j6YehDS>g2{Jlhm&I{N%hU5@Pk{H*%fN9AL
zf2!!8XRLGpc7ZY62XK*blwLF`jFat<lFHcl0|wI=jg-eqXAIm0xWwqB%8T_fW9uDA
zyTaJ~4a8(H9#Bg1D&y59V9aC$t_8Tp2$#UZEXLkD*ph69FcS;C&Iq7Q%wgnEVIr6D
z76sWi7~w}ina6m6k^=dR$_-Fa!04hpe<8y^6rzh5Ve^0$Gt_iyl~@@SI>1uKsUobf
zjG;aaj&jCgN}k?ii2uS|1!Erd?N&0r=0MXe#^1}JqKdJEvcuJkqx2ZwW<0nBz8c0N
zdQIM8-2ATy$H=GbZXM(AR{`o7S_&K*7>`qO>n>vj^({6stTn!vY+{5`t6?)kK$VFW
z#>aHws+I991=;r)oB9CS7`;cKshy#ryZ0RoZU;aoLqjn_7vq_CfORv%sPC$WVU%FI
zdl?_myQYuPLH=4l<7ok~0Y)q}0S_|nnt<JBXtzEI#vz7)-mSxoeH0*$Fj|+vm{EoY
zwVjMHo_hv*#~B7{QJi2jQW^LGW7$W*CK(GoA!dpp@`TwB8R?X1m}cy90m%$wiNEfr
zCDv24q4v!5Oek<*zDLJ}BXj;X7~#yUrEH}O^HYkiT$v1V4&0b2cOk@`IZN?|2XiZ>
zSB@};R)Noxd5KDuUd#&0G<!3LXkUGpC!T_RzRa~vnDb+LQxxsb6wz}Yz?`*)z|KHs
z0)2rih#5v7st;yfq2Fi-^9>4jjxyWmK|RJCP{Wu|rr{$fJkE^%2P7w$&tw3EF#}FQ
zML09zJQyOFE~~&0$^7CW7^0XLzW_rtQ%~8QlgtF_7CFTXr!y;t+0#WaZY*;-^|iz?
zW60G$&1A&Em@~{tirwOwE!07CmigBYusea-PN97w^A7d+oMWD&j@KmSkMzBoWTtvA
zRGeon$^*E-ym}VKTx5E5f-;5qoGYZHGLtDGna2E-5{l`}lPk!_zQi1Efr*!yN83Sq
zh56(dG-WW)jAHOA)2|iMGMTd%!FY|CKvk72X5S>RY~~XBp51lk;3a?@=ChArb}n-n
z1=Tm0ra2In$2>p<pL}M+50Fy8{G5EGLgvS-K~lu@LlcJ8rkL4Gk8}xhF1<ucnL*T!
zP{#a_$|B{=?e0)`lQ~2|Y6Y|QU652V@Ba!-x0rjV5wwc=>tkT3W*WCb%5CQGevs5K
z-Co7q9p;TzV71JT>C#pm^T}^OQqTNW0<3{)qGXo!E_00%>uqG7q${sY%vUHHXl4f7
z1lGbVC)uq`B|Q}Pm=5$s?>6Q<+L?Cdf;{kbF>61?U^g?u9-xOQ8p2>Nvy0kl`j{^w
zim>Tt+R`P_0cJ9##s--O9tX*N=J==Bpdl+$|1HpA=F((vj4=PX1)5Rj>ziTX81r3f
z_ZVmHp^JADOy?^gdBFTG1nMW5&%TMdDP{^KX&y4$J^;xyb0J(Nn;E8>-2X?+w<&Km
z%RK7@VRo$AE&zL02<5FDSPv<daAaA}zX970vyMCg*-os@v*2)M86U@>3v0_((73X=
zg#d1>-S0x7J4;C~6%Uq#g6bnI<6DsC$x`0}gBOcMLA5ulhYJ!PmXhiyzO1HZnC8do
zqhzu_Yn)1d0jzy27!$}kZw<y|5Nj(Xx`SCZ<d}!BzN2I6D655Do5xtI=qDe_s&av8
z$623!3cV*-g0CPujMaSss}E;&tN~vH3$J%Pc&wkPKo!NBKnl|)nw1v^aFR7B1>Y%_
z{U^X;Seu@L=vdbC{^ZievGTqK<7w89*I~sO*1U44k7sGOf#WP|hORCouohEVHjy=0
z3G5uJd<ASuVs%i;Cz-XK&Xn^k0R`0;So#M57g>UG$V_4V6bwzNtQTK^qBK@-F(}hn
z*FFN@CDvb+)MI{`b%h+&E36jEy=1W1RFS*NQc_VilNCqny~cX~P0VGnex`FSn>9?m
zE7w^9YMRbr*=)mLE~|MLY`VePKLYi6ti^b^Z1P!8P;gVk3U0t)F>5W|Ln>jpQ-?$;
z>j~a`Jbz`ZTzl}BvzC>D|0ZiEHM>->w!8|`N)|H^jJH@~>Po0$#dpApYL){%zqeWL
z{!mfF3Zj<NJFH#JSW_))G2LdWV+pQeuAU`{1VaNWg2LFltV{G%G_sC<3Jpyxn`4k-
zZDtja+uOp*V_{9LtmV^?c8|4!+SA%t!Q||>vlMGE*TD*>x?m@3E-kx@)k6&g-K@X@
zF!Zp(a-pf0755An`dF83VQ)X{L&~lWuujp()CO4v6t>@I<<QlTA=d6W0K-<+KT!}f
z!upt;!ckV@^N=>idTuvVjI(}w1{@Qtb)SRe0jqQoq)oCM>0299tZn2`KV<EB2r<(v
zR|A$k!+Q2D=zYXWqWs`2tH*>vJ9e%U80^`fMuWkDT{8&_9oc_U7Wy#T+TaDfPV9_a
z&^WV8gTUd!wxhC@EBg?oxZK!tHUYS^ol`LA!S<q}!4Y<m6__XcDBZpBVvkWw@6C41
z0`Ot`QdPv4z25;c{n%ZH0Q}i5lu8d^7g48BAp2xE)CaL2TCagWn7y_hXbAf(d;y!I
zY*R1x>lizcyp&LOfhRWMIJ;sR*a>#k2Ve+erxrj=I9o_xYl&e0I0=SGcIjMbiek&o
zLVYy5KM@w5WOqD)4LZe+h{jwDd+isPi)CNq0mQMZhsnP_&HkE=$+PTg>PSgoze#zs
zM0O0NXU?&AQX(~pJ#QZ7lG)!BgYrCkkTR$j*ztp4zsUY+E=)^dXOOdz%056oRvKGN
z-!DsNm(t2Eu{YJin9J-1-+|-`JBB`Blfe$$O+7wW*`}8uCX@a3LC{=d^LK$Ui~S4v
zEZJ;fGh|<9yHR&e4!h0^SS~xg7IQb)(l3GKv6oZhK|Xu;Q!uoE{XN~fDP-4EAW+2S
zQTDo+-9l-d686>eU?^pOF9l^8yP%kAEahx&1JIjnFG`43unRr}sAQk1!Qd@+*^@A)
zik<%gKsEct99VdpokJfwsbOdS0=;+G`zT<mW!KY-zK-olse*cT<tkte?7vNzyUX58
zy-<zpp>BXCcHL%xX7(>O5N2&*2U01#mA!Z|OuWY~_zN6u?BBLSVLSWU2QavU{qbq6
zqLcm3<6!J!&(ML~%@&1&zlR-_3QfK2ukM1fkNvGX*!$UYW?<m}o1+Cb$Uaa9lKbrK
zMqoqiN0hA}W>>8P!-$oAkk0&3_KGh-GsceLLiRX&&=;B}*c<5#eZYS5cc`CaBR0Z=
z$6ig<k%#OO%5qM#Kcp7f8Mb>C7V(H3bs6ll?6XwCu;a{7*P}g0P7bOAhy4d^a^#c*
zgXA!01BKO29BUy5%Xa4UlmWPK#y<pb<$OZNr5h)Vl7H@;o*3|ZaO&wr;KiA~hgEoU
zMkX-l!+GKe#Q1WKsKDpPX`ni>KWCgWWC0wJ3m5`9uAKluoQhqL63qFBLaY!@?G7yP
zD2HXGkmnf3AqtbBoS^R@?Knq5b@daR%t_FMalY6AES%#@DY6L850ux8<orpYcNAyp
zBVf^-{xtBN<jCIz!zs?>e>Y7yUF2uPa^&rpi{ms>YWg&1_xlibhI52M?|9Dj@9FtF
z%emwUF$tXa`e0ikXXr&3e2!C}296|7$4$&7b2_fV!t<O&x*vLhb2|q77dZ#KAv=Y0
zkxs2tPW4AnpT==CKxR6JaTg?)I8Rdp&SlO)x^{nsbA^8D8Jvs3&~TOW)0xNc{AF@{
z-iM}ZoZ5cyXK{X{-&{7Q_!%%>=QK9~<Zu-4VlbDpj9j-HoJwk$%i{#3W1sUm(bTz9
zz<G`i<U$V95f&D4=8?Nl%z5_@U?m)u42G6+K3s~yGR`5YtCe%UuBZ3kP0kRZ6`ZF-
zz+cJfr;ALtI4#tNP{m1I1liS`UtB?QoAWLmTQ!`rPeF2rbAJxzYB`OaSZ^KYeY$H~
z&q+T7$_7q8wIST)j8d_$k>j%!SQ9669hTk937i0X3+Gh@OtZFfzNDb}9w)mI{B4|P
z--L>GPDmnXIyfU{$nNCqpld>1oDFj!t(&uGAxL^Sr^F!X<(%J&!9I?WUgG_ny>&4A
zK8KZn!68n`fA2WXCEC~#&PKXjKFVQHPs13eDGKc4?{XG@41*^)2dKU50p|nCkWO-5
zCLeQ(Gf2MeL(YOtP&mzL?*y3Py!$&;JmQq%)U}!AxV#P$J8r4}&|gce1C?Mq%=MzO
zfD^ZbKA`5z-CqC-7jDY`pvRTFf)dScTn_zN-MNp;VUh>;{iOg$xUN*a@#MBpIPJxK
zF%EWmbMMpk_;9-@I`HLgBS+JZ`{ptz^5=G~hOhu`-61dpa+g`D%{Ykr_HAei=3cJ?
zV+glGgUO@ZXQ*(0jQfcCp+mVo^ei9e#?u;3aC=z*Vcb3BLx*$!p(8hfd#4UqBv-Nq
zb5Y!nXi3rBmnmXD$=yoL52v_M^kR?UHc;s-mV2@5KWCELM(OC&+^!;6dWIYI1x$?R
zdQgmWmb-ZXAc4DyzNeGO9hYP79CscyrzLUs(HlLP>rCxC=eg}w02jC~P~Gt&cl2pk
zk;46E3G}9NzdZr=H12Zxwop3vnGa#bC9YUY57TAtTa<gh!hQXJ(3HW=qiWSvZZ8Kk
zncS$An7hV3LosX?H>m=1+1xeXK+|=uH5aSM;l}O6LUXw#VUT@;>vaqydEB_SFqh9=
z@fkn?mqBe7h1`5<EG**2tcB=e?q9W!;bAJ_?urLm%I)3*6=mE_I*2LfHh%z6$=&@A
z?7qc4`~(zMaW8vfP1W27Cn5AUcO}KJHC*9On7hN>L+RvNE`tqF$9;oBvwH3>YMN@`
z+Wc2*<1VJFMvYwCBCt1cFH#@1wV8YMb(r76^;SZ5EB7Te`0sHaTZPFsZUUVJ?c7(t
z21y4uJQa+cTw4zec5#begzRqacjOlJaJfgZ&%InFbzt>z*OF)3&%M$FVFO&taflw|
z&OZc(``n+ug%v|w^L3C6Te-GhU~+^TP8VrMxqs8^YmB>u%pd0_e*$R}TxYsZ_kf!c
z0c?`%a{%j|;`UP?^+T=$rAeo`Tm=|rxYHB?JmS7Wd4yT+>%T&n9d9QksqA?f$p8*K
zdupzB<n5-4>|vgD$Dcr*c%OU&E1Y@e=fL5@^Os@Ll{dH#Cc5!T5+Kc;w}3j&Jb0;;
zzc|9<kqht1TS(1IUc8`lQ18u4r|{Z`cg-2Vm-pHCnDgUB6oA2>_d*u10N&w!*n~jd
z`sFYti1(6}YG=W`U+CEm;YGfJ$)mg^H}D_hEqEG?p}fyFVeUAugVIAMc*TdIDUA2O
zFF+a2^QHJWf>+f7ERwf}Rv5)IQK~tbmtlayle};0L2`<xp`1tz?`QJFV|f`=;*aB1
zDk+(An#Z>RIK%6W!Du}1AjKSKc}7acC-9chViI}QH?U9Vc+QmLPU8JWk!dn7o6<}d
zdAiGBPvI3%uUIN?A>G$c<GnBhl62mWJ27{OC#5IuGB2hbTX}`o=m*gmyz&)vVeu;O
z<zAqfJl79k_cdPs1*p&B$;tc8<}v8v#dY4oWGp6!_X-;zmlsSS{|(-vXP_dFH%O6X
zKJPx|O$vCU^sSRZUY0%Pig-t<bW+Sqp{S;WS6C0Ml(%>r=E`{M|E4drm-9Xm0KLg8
zr+Bl1_X5SDmAtp9?dTRyN1fMIy!$f%)x0-XK>cmrvIsEL@IKv()!*S2H9}}DuaTnG
zI^NPBfYtN<qNk~W$EL5%-{n0JLUbc9;BBn4iRTgwVa+@qB`mBhydPYlsg=j4e%X7x
zL0jxs8?T9OPqy<`tN~*O&$|R9ojetlM!R^mOz7?A?H>Y34=;k!Ouf9>CotE?Yg`2j
z`+2Xw1z`g`^Fx3^o|K-(`@BEtK_BA9k3i-yZ^;_iJ7VR1;Q-mAyeJtM$9SDn;27tH
z#ba`UR~!dT4|u+5kUhz3`w3u*H*g%_A+MSeV$-|^x`#Bw(^InS5%1v3Snn+F%~D9Q
z<3AP%nf83gn-J!}*OJri$QRPz=P>_U%91+qtzV`AI`dne#bR9eq4@x={H?>-AvgZE
z2N3Gcf6M`x2Y<H?j7RuVYM$`qZ(0j!UVKN2JiPhasIK9|-+vq=zWkP7q27=GE4^C%
z`G>!QO+kDXwJikmuhH2X!mp;DoTL0QYb8`1;}21pFqFS25&Xyb-sFs);D2g@-Z1_K
z5mph-AE#<#1pl)ED2(K1Q}G~*&!#TCXg-Hdn3Mc83cXM9ubCk%hX42mtSpuvy9dJJ
z_#apy`ZQk?4w5r`pI%6b=LdX27pBhgMN}+F;4j_*F^PO`EH>dBzmxo^Bz`e@sL6Z*
z9iHd;YpAF70$)V;fiCjzlbfExFFFjNsr;fXU`XTdjK^R)-*o}7OZ=@Oh`!8!`~jp~
z;d@ZYJA=QQ(nMGJYyV4TX7abu=rw-ZZ(z*g|Ir6&*?cEz{=Lp$YQbC%fABe&mdg*K
zT-^=6XE$W$@pHcdme2qFSCAC&hv>In$d99RPZ9sg?NC_E_oUQU3BLlpsWzqjb9D5V
z@e_P7SI&3X|JY-{+T7%SNA6e!f0~ZOO8!FXPPxU8p$i*T{B6fzQ#HTiNzC2m-=|b?
z4gV#2?cd?QPkurzzx5*Y*71v;gNk~7&0)xH;6G0x^j-cHI{X^>-js}N;&=LQw_jp)
zz6&Au_)DqvzKwr?9`|;>P6Y)W{DfA_b@EU2Vz7&!|2IH4{|5@NdidHyFr}AY^*Lnq
z@ju!D<^6o_4a^PjOWp<hAb-;fu>C&&>q{UR;&bR{IL!aX5mH9@=SH!gqx^UN`-IdO
zKT8Aj0smd{D<=6$YPOi-`*JY&kk3B@)28_*is)wegO0H25g&mh9xZ;*Z2&vL-dgCj
z7d%EDse@qIx7ZLzK?a?!hXtOgQ0OFBd<rDa0{eUTd$<V9W3b6p@W+4Y12@55%51s|
z!l@wVA&3@2%n`xe*TC;7a18^8m!OMY`rZQ1Gyoq#a2u@f6+H5RCO<)N9v12^kgmX7
zfZ!K;c?JrWF@OaL)~CV3V8I(1kQpMV&BxqPK?QjN#{}&kQF%O6(EU4TjtjQOWAcQc
zof?|L1ZSv;CtOfZjzNT=dp%5x6a<%pF-o9*99Xnq-3kajDPVg6J0)08r&Nq!TP8rP
zz=!&w;sl538?~ne-Sj6vBUoAjEMBma&ZV=0%h}W-ogi3DZ}db#G&$+#1dpGG&?Etm
z&dg-NnZ?+)^MVDZA@qWviV9R01^iann<5A-#9*qRXg_R96I@*a_H@B>&5(Ub@PO(e
zmjx5QVeX0`XcPD{1jolQcU7P=0Avbk#=u~`CRnY&?qvz`sWm%WQ2!oeUl&-&d(9F2
zGY4XF1(Nr%m>YtVHUN2o3N!TP3-(`w&;r3hiirvZ@Ba-@B>4Cogcb{0?O=9^;3INN
zN(Ia-kXa^JOn;_wfg=?zZwl64g0Kp!An!{^s}#&z3&vZ5Hz_S#C5R=*t6FfQ4m7s~
z+0?L5BY5gx*i<Jdpx1T1;PO6DHV7n{!0rloeVA($JlG1*B>1=ypjoi!eMo5$EZzcz
zt%4W7fQ9!2fpM^+O<;W%B<%ug2X&2f2zJqf*D0u>E$tFyCqrnrU;&-gJ%Zm)fTLG%
zG7WptC(ynGG5v!5AHcK$K^tw}py1;lvCsDfAN>oGAwm7~U>_E2plr>E;Bz`MM+F{%
zm>Ux;nG0-O;C&A^O$dIrQsDkTu=hRe*Q6l-RS2CDRMQR8hXM<^3DW}iBq*E_#J>Y$
z9to1^?Kdl^pxcsm!ef-^vlkw<!JLE8kO*Op!Zp;Kd{~$&fD|X;+S9<Cg`E2UF2W#6
zZn+Axv%ugcEIUW-Deg!DLX(HEj<TgkgipQ?%v1Oc{bs#{A}SDj3s=sALLcEON`CqZ
zZ_sPgPgoU?Rrm|@H~;~{B+9o33MB_H7bIM`6b!+_5V|%IA~fECu%p7y=?{8LXixVC
zLWP4tl)gJI<jjG>6T-LY5=WSD-aAkjF5F!Tnh4>+aSTQZKO6=YCEP*BR<tmQ3ZEy1
zMX}I(O1SQAEG9-cpFT?$D;)R{8x$uzunT;rg`3ovJ0ncxz@~WN9;!#46^7E`oFEKq
zp%$@3;gQ#Xo)f0hXC#w^bN+=f$--<qXgV+amQ1@Kv`xoiE((7?2-8x8HGB-F3b%a-
zE7F9HVXz`ycw#v;T@sd60m~46`8_mU6^2v3B2&12BW$`Rth@leEMe>|NXZs1z6oHx
zF693Jy*a|K?O<@O@Ev+z-VnC_18I3eRXR+|7v_-PS0Ft489<?M$62T-5_Sr~Uo7k?
zfzT4+PHILf6_!)-qfEGkvVY~mwhCBrQ<(1#4Hd$%c-UJhT*3t3Eg@VpJZV;;f_$uM
z;gUuuye&+igSAHZ=Q=Rn5sIC_SSt*s(q)~HxfPW4!UN8jYY?t%hM2p;&(C14QTP=H
z>`lTC{6Nwy94AMyMaZ5Hds~GQbo$&Aeme!wCj4m(8rp?7DB0Q}wDKux?G$=Ye@K_`
zA@xyq3)AS>>Jd&zu(V#`#qR<7gac_%(JyTJ9YP0$qtVbiDBN}v%f2tX@g4YvgpcTh
z9>c;neIR>8_&1#_qrw%GFB}uzO9M78yf+Cc6T+tL01t%UTc5||q|hlC=#)@*0YV=N
z-=~K7Y2kSrNShIA9zpgaVFo2XXN9Iotk6zmvmR#Ki+t(Yl7k2u@ZgC&*8@8&dg2*a
z=p-tlDzLNY^nbpjsEN)ZSJ7AZG3X}J<U)hH=)EcOxI9ET-+}Rn=oYyUo}v$X0lY-t
z(WOgoQLq`nM|7XgKwnYbZ<zBFjZ_2k7cE`}F#)1NaytV>Bf;3UAW_>BP!TNZq&#wn
z$d>}2qoObA@H!@1K~7buD3&gwgo*Ob(U-2nMMY6yj1cYNVlq;+^;sy45-p|VWwfZA
znnq5Fs;Kw&l&D|<HZex@ZZJq<MIo1=B2Ki6zJ769^cl6Ao)HD*1B(}VJqtt6issJ(
zB#1o7i%S%lr~~($XuJbbl0++!M6uc=i;mGJmd=Z=Q@-VbXxUzfxhPso<&_jsc^x=X
zMO=Cdr-{C=fb4Y9j$D{_Nfc!ZhRdQ?g^+zkbfO=cGDK>MU#^PUn_+gQ=pYsSu8F)?
zVS!nqm#B7;Evlr;Q`bd4PEc#j5xLEPKUb7Y-u4ZVG88m<BI|ZY%NNPX=PD4r_g}(9
zB>otTMWQ1sAiG%fD*b!X5>ej`FqDdJWCN6m=8M2rE()lG%$p)xYSXF^bvwX{N>KtD
zYi(|c6izUvN`$Yy<GHhnj#J6!wrKk-G}VZH>H*CiQI8obtQGasp<5@aLY~v6Ui4l$
zum({h1C)0~R&v1`Mefww+$0)J0@f^2&^x(B)J^ubihlVX4EID!DG}Qydh0XjZ5PRv
z039M*I<-1Q*2*Z@)+H)x21mC@L50vBQQ3Ro=oJOfcK3-oseid&R8b6)0nw68SlXcI
zRz5c2zR2r03=WB2{0m@MbbJmNMnvykhV`SOO**I;6D^PejEk}hF*hOdpl-(pA}{)_
zO^Uv>_F!~MB&BPx4@F<R05Q{|oN9m>QA-2{?ZiElqp%luuY+k0;vi}waTE_zr_f<>
z;V>wj#M>zNbQTM!yWT}S*bD|&@mY#P+{B+#4#-`6u?bdqhzly9{)qS=3Sm9Pe;=ca
zpO^UZHt>6kf97KMe8j9T!00O$odBtyc<~<0`HO{YY)OE)>na!m#S1Cp5G2;Gg_vOR
z%O>!Jh~J>J*irG=PgvS9aqns{go?LQYUH^10d;+!5PwgXkix`F>fZ?$&%8PZ&tHT%
zj-u>HaoGltMv2QPr4ucFj7&T!E?)`Rr^EqoV4q^dLH-aLD;|3bSe$t8StvX$?n=Q5
z&xn8c1vbTt-@bymv*O4mXi5+}(5aOu-bqEnb7E)O(IoL3pMo!0>{CVmllHv$Jk<a%
zh<~E*kz5o9ErS&);wPw@n<~D03Z!Y`W_pdLiyJ<I>`UV50}yjr+;I#HSH!!gK$0O&
z`X1`9ir48em?<9l5qo$|Y@ZA%S>iv>VJ=&|`x%J7F7CJkh8*#k7+}_1aYi1b-4NgO
z0b`!Hn$DDbakD+J0&#UI#1x8Ir+^iS55EIx#bO-`(n`dKI9Oq+co&6zW#Z9H@Rf_*
zRbaR&?u>?t3UNaXNGiosGLYO7Z=uRfm3WmcgjI{XmtkXXTg5Br7hEHD%Yrp`#L@-e
zs1-X@fTK=)HxJV4#Znmt8^la881IVH2Vrlc_&_@5n#7C&=xr5$PBH8~@f+l{w26Nm
z279~Mo{jD55P#zf%1-fIs)%=q9qqu-Eq>=SfF7~+Hg$>iihJ|G(I@`S9>(;GhpI3+
zAbv9#3J1l@EFifr{+QA>L*fQ<Jcq^mT42S9*ztL+X;l1|24GD5Y%COxix-{+m=M3^
z0J9&6Qz(%&DSkx3<dk@bvf>ZL>KKqri*H!xLdA^O?p2uhNIaMBJI#uJc?^?wk}fI?
z+DkrkfouoK&f6Gtl*GLO?6Abl0)vxemmUnx5+xHtT_pP$z+5GBC_HhK*wd-yF6pEX
zEqO>Z6lEWgG}BEzPsu}ii+V{IRg{PDmar@UK9Zj)sPvT-QJKR}lJ191@RxKrL1=)a
z?FvAkWWE?{3X+T*fY4yc$8^kwNMgu?Ix1O2$K5fBh^hynlI^}&_HoI?1CX4M6qQ3^
znB?y-Av0XE)gOZqk{2cP{)?2Hr`%VR<Ud~^S~8zD>ZD|lvfHO5mG3}yj3hP^HpNN~
zQlD6yL^=*|TC(s4RGg6*#vnUhvS%JP=&WRv+`0sbgz86$k`&5kos+Dh#-k*Op$ujx
zOXQSBKQC$em_E^RLE=Cq$cvJMU$H|elEGBaq)O%_Kxmpoz8`bx5;LW@E=f*}U=uD&
zLWY1{k+iRXg&C5)_kdlMWF%lNQ*wgR;nyTaPbkciaOg%ywxnVeq~uDNN3rZ1lE;6C
zhCE4P4uCaZ(iwrp6iC{ag0xWLSOTF%lHG4ZOtEAV6>ggni6<MTl}e0W&{QVbLhS+N
zl66w>-<0fY#LiSm3hJSvQnH7BSGObwDOp@4Ipq#1)e?^xh`ueE{0pE)GW!Wg?no|7
zgQV6fanFaeI!Oj)vg#%K|AdJRl08eXLw6;61(<7;*i*T#N%E%^bIp=X^)RMI!luvD
zwMynxVxjjW<%7W5B%3z?v`cQj1ojSz{AYkp36s)sT@og_-QAKeY5{sA5p;I;O01$`
z$nKLY-+|G7Nz!Iu1Ckm8Y#Wrk91m&tB~Ik34oMoifelMOrAE*ZiJV$WMkW3suy9P0
zRR(F}k{{EthzW@wIYbX63C#eLl5=!gPDxDU_db+p-M}y{c}ovPGZG}SA@q@?Z6(lI
z$(RW=cG7to$hMbmrmy-tNQ3D4bCh!E8tY-{DSDqcNhhe6%UQaV+6r8x8~?%|%~h(W
z`w(u@7e9brcj-#%rSy<S-T-z)`ZU#>J*5+CAk0hpIl0E(QuQ@@Ir>PQN`d-Ht0{%x
zCw+yIW&YCCdk`8R-Ab)6fzqewZ5SkdpIWPer5tZ)3Xzu8;V*JjYMTk6$E4|>gCSJf
zNY4Lp>GNYCIUy~fFe6O5*&QHU`XYUTBSLzQK5-N&9lu2JUzGIiUtvYGbfG&YW27;E
zLQJeQPXPWn=_|>QeOmfL4fLLouI6GD@lvS+NX|-+QtdrK+C}f(MCm{%7|uzbp~6*?
z^fn!Z$<oeUpgb>4%fiYoNdGPaxG3FA9&U>C2Htd5n^dXN9b(d?MU=Wom##q`(B_hK
z8)fb;OACI-+!g5!>bc91@~K>YRr)Hu2r{Lc$=ACkO`#k~mUI~v>awK;zXDvBo*n^T
zj`YAW2+NhOy8$b1NLdPOWuCN!F2CeU>uWG)Es#D%-L!>Lxd76Nr0rA#DVENV2Ua2-
zECffX^i(0RGU-Zc;wqP3JOqZD(zj_ZE2JCgk6tO&ybqFF(yfues-%)Lpsbem_QSN>
z(p8URu10z$71rO8&JDskYo!D90faiM^yqJxte5_>6_X9p3lxCel~(W|rcrv4BAF&B
zyB}NHEVT@PqeYrYskBz9TLZ-0lQ#K-q)obxeCl>-KSc{2Qd<+)JEg8K!q6`17&Yg0
zOOH`Wp+}lY9$&9i`!t00Nv(kt<@8Gv>FqxteTzO9H7Grijmi7cwX30GNE-Gdz_7GO
z2rweuPd?_T)TRSqO#0(f0OQgYH55)rW9b$9K)QAZgiT79-+`1VDKi+RJ(PxA2K%&h
z3zf-dq|FIX^hmneO0B-LQp*yI+R3(k2+Ur#XAU?VWE~!m?I>eVv-Dxv@XG*BGA?!H
zy2@%Bpvg`4E!Dl<WilQHJ!D4ed_5v-T7ZRm%IfvNyksY+&Ba^x2K~5wWH-dn;42fR
zgTznP8es+MFH60G$pBdxwdVxNN~p6lNS3n~1_#T=KgV2%Ot2puM`e#uPvkM#YgZvO
zRQBdxfa9{!9<2U^tn?&=g~?1$<A)S3%WsAH2w5Wq6p^wWQ;-=YtNjWL(XyY6z)s4f
z1M~^+Q?k}a5E>&Zpb}fGY)d^roNR9)gr1gtWedG$WStZw#ml@XI6Esl6bPFVWLM}{
zmMD8F1=u-RbPcd1*%CV}B3ZVY@=fPucaLG$F39FkPvb?|b*g)($k=I+k}7+7EyaIn
zvi4Z;r^`a7!Es6U`HR3V%i@;-yCSnAM=nFQ#~IjFS)w0o%9QP+{Ma>F2)*dDWZ#d2
zBwLpK5(cl!uAK#Yj%+D4)a1(6P+H=KYy%5?c`{8g=JI7`%CHv5g1W$NEtH)JgzO^O
z2h?+3EX(@>3oViTv<8!<vfp{&D3kr20{(K@f+1+SDf6LRR)x&>6!xi7=J6_2+>&)t
z-(i(({s`EsWqNuk-j+?7p{YjZQV6~~GNv;aYGu*$pr}rky%dA>R@uTNkT%HX(JS_@
zEO!I2Mp+|WZ)lRGd<oDj`-y(}Eizkj30h^@+py2~WXe<ww#ok50jym%8VU6svgPCw
zbjr3YfUq9fTi=4DR~8!zl0I2OIP~_*e(MG{AUo6ml0lhOe-DiJWjZxv56Rx1fx=<g
z3W_a9WI=Y|AC;Z-2IH8l&J1i^#v<>1Lgu^}8}vZ-<m1?xNm;@xSoW0c2>C@1Ww)se
zF)d>TK=h34U))i*c_g!=chsybih7Fe<O0eI*vq$B`CxRApQh*6QGS>lqr>t=6iYkF
z?;U_K&hiHGi(KSJDm=K#+dqX+H@W6AfV(_{i#ZSZuXeEhi2TciSemE&?<vfA$vHh(
zgtz>212p)^cTuq7EB}((6a3_9TVRF1Ja?@XngZmESWE`W|BL~DkbLjc;18CMQY|q=
z&YuCtQMoD$79NwYpcchYd0{{JkIO~mDxQ!(RRb(c9`gpUaQVnAghj~L)2S6Hul0u&
zQS#u27>t&)&q2yb`2~9Io|1pKggy}wBbP^EGFC32E0S^YSxPUQmLK;3c1A9Y1An~S
zN=NWnc{%kZB*^iy!GkBakc)awev<AtB+1wOh`D6>hs}_EULMd5^%vxW^r?o6@{MG6
zirkg@5>n+K&`U8*p1F$Nf9Z1kw-G#e@=_acT$XQI2>vVb2nIMZ<j)OY_pZtpP!2j%
zZlPN5HTjk`5R)Z8LViNFyk`V@ugf>Oz@{AeOM1x8mCv?8*bTYT4||v=w@`GHFQ4@V
zWr5t>2KGXE#=pR<CGwsIpr!IZ>9Hu2w@`(>Ty94VVmIYx52&b+i+Lcal)t?X9Jl0K
z0zpzGPox;4TK-ucG~JfJwE!eF@+IUw-;tkXLt(9a?*mAwlQ&0UuwMT8TA0=#Zytrr
zyYj9LSXrZ0-tYrPo8&8=256S=F9&0be9fm=Osl;4e-L_4?nQxAoBT`>7~ADbet_N%
zxqcmFcgk()zI>N_ay$6C<%18w*CVg(1L&1s-3j(Sxr(}C`{e@^nhwYX)Q2}HKd=Gp
z_vO||N<9q87rqAd!*W+@6&aDM=-3*SKTQ{I$K>U=fsM--EC=I+eC;-nJdjUxLiVKm
zodeJ`C3ho|hw@M#kW9;KsZn`GzCsSskK|`IW4mVMkLaMVQ-~^o*(**g1iOP`!b<+S
zqv8%_cn>R_=wNnIoFk{lSuuMFz(uk2U)b%c@JNAdH-(g53+{@uR6g-g%-sj<h$8#|
z*gX}0Q>UVr;+^>b-ioJ6!0w}1as--u6?2-P-cON2fu_IW1g#}N@lzz#9|9E%f*~eI
z!OepDV8vtPPKGG@zXmv}xJ8f5F~z^+UWF?Bs=<F;afLowd_s{%rO7bGR%+f1SIDXR
zB|>3o2NtQ2%z=t1#jA8^Mk_w#LD5OYrM&>B6uS<?v>3%g34J0WR#8nJcATPxvQMWK
z-_pDJjAB(V_~R8j?*hA^c<pC^i;8v^EHp*&N;5QFQXHeA#AU@x?V!A(_<lEpUQ^6c
zwk%8W6*XmLD@62yFIKomLvN{K{SJ_nDg3CYP_EdCA2-?;75}3@P=%uQ4rEs<WZS`U
zOCh9Kx=Qga^%PetRFqMxQH*{J$~%gCf!NDh#f$V(tWzXA!nArtbti;2C?+aF*{Jv<
z0GgT<g_p3TW(6Z0ThgNFrqHKVah-C(ZHf!@+O@VTHVDAcp}6h_X`Ko#d463AqdoY$
z6$feedK8NfgQHJTMqYHkVm)Q11{7&WF*m4KN_X+^D^vwAbV%_!Wl@I}J>*M|D4gks
zG^!}Ngt;-rACbVu6^RZIHlg_12(=Hair=VAHK_<CPkBnQj51r(iYh5&&nQ?_V11+*
z>Hz7iB7m;R*(p~FAjV$#FC`)zm5N-LeOS4XVp=EVAC!A@R<8dYz(r}-1(|Nj^4GCY
zcjeoZGW1ZE(-q?*%4>N5o=WSl6o7dtqw6r~tvo|X9be_PDQNOjuFHfbe`V5_kR70W
zhpP91N}m>hAf;|SY&xnOeHxmMDR2D-V?vb==!bY*soIIT6Us<xD-2Vb$t8$Xc4c5?
zQOaMmAc<B6ZN^}X^1AhLm=UX7Z^UGrlH~&suN=&S!m~>D_fVgp)aHXUNx7IBCzF+L
zP*`<d`75=iq$o!zv7M?6nE*+e(s>!M%SvN0mUKl~z8yAYD5X?lxTd_53cXp%18ZP?
zwsO%Fq+C}XIz`W4j<Sk8nq1`!eMBQ)`4n{k7AS8e11nT|oWxv_av}<{i<K>V!C#`3
zErc=U%C*#_bW`~R#nKhZP)aFRDn}@gxuu-H2Rl=xe0x2x8s$7{bGW0-phRu0@_mX#
z8k8Dadj9SztD9g=qjFmkWVa}tmO){wvVgJ$_moGeRNtn2_X<?BD=+TALOYac^imyA
zCdFZJP#K>AlKaYqbd(J#TdC1=SXoWS-H5V`Zu5^ScaT>&rmPOc+_<vfQ%IRmz7t8$
z-vi}!I(sLTyDXrYQf`ZY!4H*%RQ8-!%8CGHl)3Yv;*s(+^*PTfciLmnP8InZRM@MQ
z^kC3IwSn9XN7c@sA?&bfuN_F7RL)gU@2tvv3xh7IWl30)tE!qDRyURA3(Q&FRVU-H
zdJk30aiB+38(W~>Q`P1L*<Py2-2mRI5W11-r|O9XzrX5TI;;a!yE3tuKvjYpK#*!~
z4d#MXPUkTfqB^||3XiH@q)S@IR3*!Solx0QR28ObS_u%Y`kFkb2&+nwj>$;XKB`$q
zsmjj7ifGj{r0JyUM|v5bQjOCy5~Jc!+e@q}brbmGRBlgVy{A=E^iZBrt%<>w#;Zis
zJCUH8Pc5v8s=82sbE<#Sz>uUmdlRCQRo&-7a$dFPJ_b`%*3YReI926L{i12Ae@;P6
zx@z|e&~!<aL_z;$6`Lw0S5$4U!om#IYH~cUs?MLpmSn2b^t-sGntUEovQ(Ya-J7lQ
zeFZA6t2h*j=csy50NhaBp%PSq>Jv(M7OH}%Nw7#|XAOYRVwEKt93?6?edwZ8wd*W6
z%2YdwA-i1l;A70)R2_H&phERC`FfSAyJg_NrOJICph{({0jO3jb_2MrTK+Y5tycBP
z1sGGO+D45p^{RHtQ8uU!^h3j4Rc<5fZC2gyCjYZVl}B&dR@EZ%Xzr;-BEa9KS~LLl
z?JD2J03E7#azNRss^5n#?NZGT14FlJ9c5^HRGa!R*sHq!7*zDBT<<_izv^E)Uk6l+
z%@`a~DFrZQRCVh=S6&tRH~7X?tFP1bwF%XW^gWXYD%V5Up-I&zuS3(6>h2COK2*Iz
zceSQfyl@Q8sJ`C<O^;Mr#TcAb*^pc2p!VAZ;HX~W4TXo*^LJu{oYX6IU~pDHMjwiC
zQ9nVkp{x3jK*)4c8!0GsSF2Z3{O6$_Q9$Ss_515#l&5-s4)}f4t3HDYU-j7tF#4&D
z)VtxY&ffzNpmq<2&_MOalsXSl|MV2}9#wZX!TMur$6WxS>al4EJFYgk0Xw1I`#)%i
zP&ZTRAyV!42ds!v|8Wx<tkLTBY$!ab_9+B<O1<6>LSxi5&jE{7UpIjxPJQ8RaGX{@
zqVKSuQ9ts-dgIk?R93s7j@kf{i|W5A-JGJ1q<nm;dK-NgB2CS6fUtD+b79zvOX^SP
z|36<=FUSSS74=JW*k)MOH#PuXRZHpaMW%WyIRV$y1}|V)>auo_W~*PLU&3|ud;daO
zj`|rMq~)r=_JWEVYOyN@^VIEh^yjPpNBPeJ^(=h^xKRE3C74#EK24{4u{!2`NGVaf
z?*e71dK2~hm8q>Kzs1tZ)q8(|(3|S#0x?;kesl$(QoZ4IsJNw;G=Z^7z4ruGU#)(M
zF7Dq}t0~Q0qkcgE*>}{N3^24-{SGDR>(pj?;Oo^h6!SEwf7}ajS6%xx_!`xn-2hGM
z?ir|WRwrA@-DpwobA_f>b;or~-c!d>8m3MCIYoo*>QAVK)S*r~2Zf#LW77a#>gCi3
z(ycBm2G*ml+6e1=)m2_#?^8Se0)~F|w|dw#puQ~zHmDXigYv$*#SbJy>c=-g?XbF}
zhUyO^>M+VPkE%QQ;22XMp1|O^+Lda96Y89g!0|x+HC=|ARKHpQ$|?28Ns!E_Bgx%=
zq+a$s7Bj0>Q>^8n`FbTt95vq5({@<nH2~nGd8QpC&KlDNtjtC8!Osxps(G449sh2c
z^aWU`yXM6YK<c6SWEp6VXr87Ijd*G{egqX>nnUyr6mN|exwt+WjS`f;n!mpS@Y8Ip
z!v_0nLg_3D&?IihdV@8Gs0<&XDWv4$QOyrau(D&C)<jT-YMf%B;kd@_;A43HPH5KJ
zU^Gm#@e9y|YXlTSL}+AGl!(-<dKJ>5G<M|vMr+)tI(AZ1`WDPTrCF`QT#V)os_MmR
zT4WG<M)MvupT=vZ$zeUK8KqxBf@a>ESVW@cmobo>)4aGGi%8O_>C<!8WX-qlLH&6R
z{~%~CXuAFcxTyKE4E!mY#BIP*HThzYrfCA^ViVFe&J!^0lICR{_%3TKw6j+<?N5O+
zLz6=diB~ld^lAD`&Ep$j?={T~y-c$-w}vs7t&!8Eu<IH|Figv_YW^((W3FcKV<^0#
zdBO&xc^Z34ljm!$Q&Oft<Gcf63N_pim|vvn`5gSkn&ZAuU!obJd|;`jl|uM3O?wY0
z%Qbf7lHb&ny8x@uEIJClN{v@4gx%7FbV6U1rs-KQRBNn>8KAkX8J!2cHJa5+0q$tN
zqTEoe=2t(6sndl14+`rwwl!dE&;-wew7VJ=6-pX4Yf~`Tr1`K3(wa5DkXzTH=^-b)
zRb#gUn{ZFF_7!Ybn`Y=+khE)@KgA!dOOr^Cf4Am>H5w{<G`~|XcdzE1XMy!;e8}tQ
z*K9ry{sB!g`SOFBE7anAUvrEK%0rrW$)Ot7Y;cCXBbr_gWRGg*(g8K5iKmvWan05c
zSU90s<p}J7W?vO-n$$Q@m@uW;@g4XcYJO;@@Mv07Jp*(`<6Q}wM;e=zkUgv6eg|Nu
zHBd8-z4mEWtinP2zX%LEY7f2zg@?6^s0G7G8(R&towXz9AjL&n@DKF5YB|(n?51sP
zf_iuDJSq-&Xl*tE9MK+EU`d|ZtuIsk-An6Y0>8Jm^lKR7qkWAUh<&wOGZy2g4Icuj
zzt%Asg8|wV-vA5LUK;}l(jK<~U$AyQbw`G1kCACdwYSL$IHpaoKz*q8&oB%g*QO^!
z^a<?|YD@~#uE_=n*K)t1{<8?JF$)GqY9H(dh|&&IJv&<KMfr#rtv(JaVzqDW14o>8
z33YIt*0MeTc1F9K3zB&46eU2;YIna5$^>oUI$(*~HD*XTr(F{P$|P+86<CtB_H>?~
z*KW_p-~}y@GQ-x3+V=z)P0{}L3br&=Te%sNY1(DfX_~Hm^E-Ofv;{UGxvY(%oxP%6
z&4(2k+DE6M@T#_)E)r*I|2+u3*R)S(VA)yPpELm3+G$@<Ue`uZH9be0KyFp8HeeW(
zH?)6T#bBOQ+uIMJ`C4lz#1v><HbP;cHiU`EB5giZN{Y1t%6gS(w|xRos%1$qSEhA&
z2@K`h-9G}msoiXZlnSk(09d8=5xEk#v@eZ;p-P*?!(g>`<&yxnwY`+2sL>kEgW-<W
z`W&?c)@mDn07sp6S1&-lc02uc8nin-q2jJ~&T8yMqjvpOfF^BjBKD$LdodWGMSF|B
z@zJK;MUGgz_H|FF=+JIxgWgVP0@kJd-3-cZ?bB3|?a^-h5|q8#h#G)C?F#E4_M~6C
znhIhA+P^3?9@MU+ZjJleI*K-iwCf(g(qXNZYV#x7*;`;3)vlz_XH3ig7edFic635a
zXhZD*9%#R#+R>zT@C$$`ZT9Ps@=*J#8?b5ZNexJ5wAMwC@<_YXj(WCcwLRoz+39ll
zP+_l=Q)<aU$DfC#IqHT!1LI-c@s|Odbo#$Q>8z`wG?|M|^*+S7>ZU2P?568HfjM^_
z(-(Xmx>aW|ctoco^`5#r)nND1nRkN0TjxTT<$ZJ;_f!4BSGVc{jPlbB&>P-gSCb2x
z0NwegAT3b0KnG1hx~QFy7OWdsguxKqD*8_1QJsWtY#!6CqW<ep-P{kbmgBm=>0~;g
zdlStqHeou(QpgO~9i&#VDBUOYX`X1EH`#kqcMd;9t4*x#3A%n7rwgYx-_yEvA{cyD
z_lFi6oS^HQ2gXF*VFz%e=??t^P3gMaFF<lh=S7LY%en??>b|0josVT_=>DQ0>8kD~
zMKGDV2zpaq)7`58$kM&F9hBL+WluoSb)D%WNU`SVHfKXquI?qO@!ik~H$qdM?gfgc
z@^ub-VOoLiSQ1DIb#@CtQlzs;Af{L+pwxMZE{PaQbvHIbVVQ2P79{1m^-~zUsq0(_
zz6#v{)s-rBp53timQI-sW2$r>)L~Pt(z!edF}HPF5`fm|{`nN(j?O0r9JRVG>b9uU
zeflqi*6RfR*OHmmsMjI7S$B@^+_vcEP)ymXOW?z#d%AWf(6{Ll+(F;2Q~Lw!&>4y$
zvQrlw39L)!8wGXUx=PAj_2}|Du)bd1T>69b>2^@Yy<a!v1_K9lF9ks6pl+}grrg)9
zDF!yATWF=6+ptc!6Qm=$5^_{Wb#nTLt7E!SI$6ebagRgVgzm?)(DXpJcPX$*-CNYx
zH>G>c4#qsx9sU8}k*<w04zs#iJIJ=vpQY2)UO&GMJL#Y|1woOc{>@Anb6DT_81y;m
zBj2DGma~51I|y~r*S`i*SN&gf9n4KXL+?Fz{h~xj^U#0U0fk5OS5q<PsXs`?Eie5C
z2zhM0^&j<O&PUIA6GDCUk(8D9(?914%wM0qihlljwH+t}^@&Ts7o>070xN>`A$#e2
zV#o9i^o|JC&!wW=asB($S#U!CIkl*S=|iXyDqKJL7f2%Xjbe~Q>Obp)&?tR4iHX)H
z&@b<#{<~-xdP*<34G^P$DG+Ok)&H~>AWnZK3Jj<9iFA+tjD8NKD&qAGcqXhiXZ7n*
zIIv03cW#92ME!^4RG!m6D}?z;`sNqGk*xQp`rCPZ|6yPk^p9PGF&FjLr?Bi4eNYLo
zRQ;A8!I!3g^=W`~JxX(Uru1A&&0N;+-U@I<-!=r0q5pt_*Q@$_(_pt|>Mv1N|C)Yv
z0Y<a*F%&yz>lah+!gYNdRmF1jPJcjXu0Hn@tm1}Va~)#x^v9M%Z@zy1EdH<s`dG55
zP~X&vxgtHk7g(`=JLS_#^q$m8UaGI6(ovcIFA=bE{rde_^-ZgOa2a-}LjSe_E3DMl
z&w~}W^uynRze@jy3JR<B8>kq6Tfd096>9V!t;gUU{cigE)aw6t5Mt`|i%|Tusn>7p
z1Yd*RK<}2j`gS@B8ugi!GHB6<9Rf+Keh$57@9E#J#>(3C)?9D!x9cM-U|WZN>>EsW
z>i?kD`7S+22L5jSj&+dMqtE*Q{Jr|GBEit7x0{7c{dxoawFdNasGc;aucaQm`}#Zc
z!9Jw_kaC2>`jx|&8_~Z`&2yvryjTbu)9-x@`o{G?TB(P2LjM^Zk5hW90{jp4i>a4q
zTA$JkF*Ev?j)3%$p4SKUv-+p0GHGWx+X-NAcp?lc91O0j!RKgrlDw3|hS%o6G$%tW
z6_T6{R}Mj#i$Os@4_Ct_syw+F1}J&tZusKACSwo7M?Zt+h~c*wsPHsw{S?x?3<iqS
zyba4pjE}*CGL^oDeRQM4&oJ)|*z0c?pt@{;VR$~UK*Lx7=7J2XE5Q(KFw;>MVo16T
zLysCx(-o{^hFg@64mH@BfgLy8iK2k*gkh3i2VsV0a&5y6&QyJjFv$J|7HLR02iZ}E
z*fI=88+?DpUYs<1Pleo5hT#>E7Grph%F(fg+yIco862O%+-ZZ6?pU5Nyj2JgZ`idH
z+kDnA^d_(bL*)w)ooHCzLJs3OLm#=~Nrr>*ph-4NQlI&G!}H_Vs0)U#$f3AsI5UH}
z6vN+?B}+BjY6D4{!E+Mo(+$<+DPA%>!2@>LP_`C)R}8+?6O&=k<wD_A!@Iti%QU>^
zjlpaK_j#~iH#lwqX3a6oBi|+0(D)>1ZW!*@K~tXLJNi&pzTpTZ0tyTj^!3I<gPQWK
zMTR^od>0$;Q3pne;S=gaDm6q<uux{me+5{%p^OFgn}+9Khl&cr=o&1d(qN*h)-A)l
zFes`ruxT%<t%m2xbGwZ-0n`{|O04jXA(65vwFVwFZq*s$E#Rm(#8U;S!7xE*{#}D>
z8s-`e-&5OKli?@w$eRse0ockGL&sb&v>JK}Vc|W)uFVkLW)M?s)oxhl4$xs(RtLUL
zgH=mma+e`583uP7o}wgqkD)*Tj$T6^eL=I&@PPcNe#0`lYcpWTOM&b`!)N<o{(Zwi
zYBm}&{3U{vVZ+;NA!Wp1eFb3D@b6M+8Z&H62j941%m!e>&`n>!d|>#DeBeog#7b|M
zDMQKwtm&cQ*=8_K8^lx-oH2+8G55%Dnl2N~8aQ*nVP~ABzpuSf@)9ry<MC85I2x0w
z9rCd86M9mejH~RR$<?@Ci$OPI)q5auH|9{K&BLg2#FiW}zC$T`Pvg)oN?3Xsf7}T5
z-bPhE7=4Ty>O%81Ca(mCpK(}^L4PCv1~xdrI8M2~K;ygAIUHnsMvlQ?<HH_+5Mv~z
zWRDszlhb|7SVu=$sL}cv29F#0Ay9b2SVG;SVa9kVYzjB7`~QY%<Lgv3jWjxZ1Wi#!
zNeOI<HoBYy|4HMoKLa~ud_+I57^6H3jIqXO%8AAq{XJmzX=B+T%$+d`E@3X-c!8Sk
z&Ki5Er!2wPl!&cNG;Sf6;GFTRR`4YmU#2Qgva$65z5mV|<Eeyu!MJD&j2DfYwJ<ov
z_%1bhq#C7^>Q6JiP3@5BMke*bT{3Q~z+x^NKbXYa72_-P+Rrd%QRV8Y(HelcOyl@H
z2)kyyNx?#vanCDIpKY8^TY24B^8y%hj5U2Q#+qwfMwgjx7!#=qpJzNi2#$Q?3+u3$
z0%J!iI0}uOZXhW#Iz0w4#YSENNJ@+zT43eIg(}#4)0mhHk_uxDm5wTn&pZc`TgE5s
zVMUd(nm!;?ZG4%sy|;~jyn{v57(1TCs_$5h?~`j#Yy65x>x_%&dVakzYZ%5f7}-pK
zyT-Mtkk)8qtpiDu@$5Gc(`<Y(2b3+wo%9&D8pG#dP4|qOa<Ha0<I%g2-ELgC7@9ha
zH7;Q9G|rf@q%PwhDKMtnSVI-f9;0<M5C-=ezxoFpea49lVExAB^C5e{n8JtpL1We`
z4Bj_d)!-j8J}Sc8uu&p_rV%5Ts>7p3JIc(C89QTP+PHB!9fcFdQ<Up|V3c`)Z_@br
zTfnA_u8mOi&=~d<)K44ht@P!#8Dk&029J#W6jRO`_tGI`XZrj;#MqlSKLB$u`O(kA
z(R8;S;IJw0Cn$6>xhuivY${m`D_l&!&`Z(PwB{I8xS7hRmB8JkpzaqBlkIA#KVmvd
z9b2BJwd4$Ynbsb$LZP?G`VEBon0yZa_?q_7t#v<>l>R{eCf!5qUZ|;*k`u>Gudjrr
z6Q;m^XbLl#W5Ez^>iZdk5vFztNFq)9|HOKuO!ZXXj5gh-XzHXX@)qV!nKYCyjWcb2
z9PFn}^%g4FoiSw`ftYwxUkgajnp%DXNH9IW6(G@cd@C$HXZo%jBuS>9$+Ji{&3PT*
zyvg)3gkCURq``}(+6V|uG0DiqO*I{)w@RAnWE`wWH$9aE?2;+T8Q5jh96J22m^9hc
zFr8ug{So%$nu*(m(JWJq2+Phk<!At|n>gM8IVNc`gyxzK4dZWr!(<ggOrGgqN;Bn~
zdR+kuOx}wzSZHEBjm;}E)%Jm}*tC%1pAu8;SC}g`UCDxmGE;ma^p%@Fr=~3HO_Puk
zY856awGLLA>i@>%Et3s>Vdb`ImK^396Z;F0+%Z+X431jUCzK7TGc^@MZ@uYz%2qX)
zOv?f8ntrBhR*j}ZR3~XN-PU09noVAGiK4}H_%=YR$?;nVyJwoE+bwNYlf(gH+D%bf
zfDRM82@CBsT|EZ9U8YEK>$**Qp9g7=X@MFx^_sq<I~;wcueXAv-?W1+LkyT!KZUtL
z(_ZQ|yl?tp7J7$FnRHMLn^XrtGGcm-K6El_5>p4nm?@XS+;Nk2dI_wVFlpG>*(p<N
zI;?nT+UgH5ZTg@Fnr2KlP6K;nn&MzfXHChU1G6`W%mssk`B@769nA-*Gxe}pNPl!E
zb7>>=I-3(Jfw`C;7ho@3&1%Y*x|v%Wq1W9!mm+u%bE<F{G)K&y6xVy2MHC2mnHj0T
zyv=hjg2Tt`?Y}*1i8X+{-vIM4y(0q6uie0MgUs(uLs78#&_T!yG5=1PhNI@)ju3s!
z>_+{Xp`e72<K`Or+QSL6xDk@W%!}EO5^gTf0~TRkL!o-4dDCgEA<CRXzu#!H-5y{k
z%}<isddl2vT>%(lu3G@1vF68Jv4?Ty7;+lo%|d#n&zi4hL4AVxwRRYqXnv3KL+8x*
zsMR9Le3t=D$>tu4e9oKyq`d3}vzdNC7tLCV+fvLnanPG;PHlxTY35NX+@_mD=tpwN
z?74^9h_lT<jRC!GK21kaj`<+H6LZZUGNJy4IrVQS%rgfDfxp0<upa9zGzU<_agq5r
zMG(d27bp@hF>7~#q|6+h11aU^g#DPiX`ZICS%vw<mm#du9D4zZs?1STjjA^P_!Kp^
z-8S>6QKiQG%6~}(^I!A>tTi8?R*O3G<%^J3Z`OumX$|JeQmDUcwpy@?M)O87^fsAY
zPGN=3W;ZGYwwQld43bu}PaSsVp7}{W*xSs#m5|wPZvF{d*<p^R0$-=u5x$+(rpsJK
z|9`RD{HF#&d(6TS(Da&z7lN_Ryqg~Te)B$RwHPqxZ^7W8S#k>4ee(>t(nIDUN?8w^
z|9%zfN6hVrP;Exd)nxXVIfMLzar0twYbMOWT9`Iv-ntGlADW+`;Pbg@v)?_apE2v&
zF#5>+vtP~<>mv#d94#|<0S;S^FNH`aOU-lOcCnnHRuESUj}3Kh7CjX=-7U>+z&tEx
z6F}l=*>)dW=Vj@-07`F5F=gg_EZ_Bj#Md(aJ;?O4SlhtoZ#hRER)8h*1%N;clhVgQ
zmXEE^f-%^#<05E6EFV!^d(`4cR|k(-802M#TArmO>v7BBW-RlB<$q>?Fv}RVZG>C$
z=%A0V$iD|kq-FUiY>Kj!Tn83yN$Lc4(sGl$zEhSX;ZPW3sVf7BwQPPHBypBBmH+d(
z3~O}+{;CNUySFiyX!-VQ*mBNt=?P#-mY=CN;ezGIFs$>U<pUpBmSTC6@|mfY#c~*!
zW{IYHUb;n08Q05}KgqYaVp*;Q$gpgA5|mdhJE<)t)6zjXxGc-6yWq>VD5!XQ-7;hS
z1d}-y-6gCg*D{d;nmo(zey~2@5+4s^3M_^_AStwbw+xI$miL-LS!{WO3SuP|_x;dR
zYFS5p$z_%`)a+bt***^IZ(3fWOK%mHkLk)#rNtNvzFU^Wg%Dk3d5L_QYKwE16{EK;
zPC-~&jb$wt9Cs{5lsBuj?4gWpo#it9&Fd|1Q1YX}QbdmMUCY=#Xlk^~jKhj1%V+e{
zYPR@O9iqjuf<oO^i<v%pb<YxX9_($F<SH22ZYkW0ed@6EPzPA2MZc0h7~N$#U<7Hm
z<t}|wrq80F7WID1`_!Q{VCi`TjzNo&l8yH*J|d6|S&At%8L<p51>dM8U5vpo%j?ep
z8@G5fV8w*xN*wqmEfZAOnzHa00z9;&lay)8wiJ-eSeo#hSZ!u4E);{=Ew?&Aul@2k
z1u%!@nv>vnTz>jDSaEoH0J#`W%N?kK;JiG1F{HUH@1@ot*X1Ln*bBGiBZI))muFQ2
z^H~1Re|=rcKm9+Bt~)O4s*9UxRyNeM*EF*|%(nULz4t`R%rY~Z+Rn0i00osL${r$n
z$`TM{i|iqSf(%hWWXTX@$n^c5_~(4?J?DJSx%c^vd(S!d2VHsYj4%pbdoYfVVJ?m_
zVpgHklkraqro?ufvG#44IKlXa5|Cbu&#6Ado8e3`e;>w4s>}3cM4g0Behh~h!1y!H
zB2%+Cfbp>i{suA*-G$vC#^8@=1vA2_%H$*?g!XkI4D*xtT~9F*K7w8-<2HT8HjHt-
z9frag-`z%Ml#Rh1gB#I|V%lEDFwRm;I+n5I1L(&wzN9xyJmViFIujT-q|iuYcyEPd
z5<`=O&Sb`-^RS!3$fUPcDx-|DA!it0Q9Lw_vGWb^G8mnkp>URQg}ySM$&gU_T^6Hu
z2;>~Ywx7bB*^E~NAUTW=>GsWK{JkGz%42v?g>F9MJ{8^+FcPjp<2<9O3^P;2*cFV{
z1x7bz$%+}vD1B4HIM4tSr3_!XJjxhPJ_0W)7|$~RUCCG<1d%F6%u7(OW}JHpm^F+V
zn;%SEWO(&Mv6kUTF4i%&)6Z4UXxRjq%Z$1rXk1|obb!~uP&R|t$Pgt%?<(W?UXW(S
zLq|bc7%R@fL@VPEJ)5sF9;Kq3HpY)d=xk?1y$^#OjNwB7>tr-9$IRShh`*<=^>i`X
zj$stH7&dx-cQcmJnx>Z_rX+43Ba(KI{fr3O#N1{i&?abr@mMpQ8Ds>mhsY2knBMYt
z82*dVIl}m=6K;<(%GN^RE@QC^)W;ZW|3Yh=;q3zG3C0epuAF4VhtL;i?lE+qpgF~e
z^@3B=j3qxoW0s+O9WZl@N<TO}&v^G5MtGm$@(oPbGe2H{P6uW?EovN@9vny>V)E1&
zixcykPoVD1{NZOP9A>VjvX&#vr@jUBQD$@u^jw(xJ7Ld_xoj<MVBMLoOhUth`C~88
zjxilWA>+w(rJd_>=AM6`c!Ie~4C2i!_!vAN=Jc;n@MXSBSvEhW^J^gfOoz7s8pO;g
z14=NHLAAIinJH(`3Squ;3$0VkV@2>jlv%$N(-p>igSNr82xiVNkcni@?|@7c(-w{1
zXlBwXbjC2pDeNB0Or+7rG1auTPhg&Kg~(}UUjaH3nWy8?nZ*2)-lfS*1HC;{n2n*}
zr7{y~Uw4MtLQB^)X3I2q>C8bBMwY>Jq`M;1#{BsKxSz$mL1~n8%y$=J6xqy8v~S2^
z`pWTh<uV)Th*chQAzh>e%*ko!7c!Y5NS<eYL2;xa=1O`;U0^={3R=ZXqdi1Qm{VmS
zWz3dRbe1zKDF9T#+>dR`;!5Vke(<W8wsTwXt5q{SSdgh<jvfN3W!~`t^AfZ6Q;60v
zLrX#Gnf^uSyv%(58_Y~2(_V}bUS+;Z$0?eaH^(8;%p7QidJ8kt0iCVP=N^K{HKx!R
z<T~>PebMIz^B_%7JF~R|{&p~@Z916mWFDpe)N_;hAs6~x%$;|^>}KAg+rNj|Mc?G;
zW#$dh?ZA9#7TEnv=`|R<&0P2`$N+QW9q0`*{nlc-hM1=)p*_r0P!Qn`)16*bqs*K1
z5V^}7&xgnuQ}Hjn7-yzgY`~sio}vWRBvU~3Rri?B(tc%{xtc0iW|&Vbfaol9;Co2U
zF-PryJ<ptI2Jb#o^A>&)dsgV5AdW0&+L|0>aVhwBh;@ioRZgs@>E+_gx=c^v!>m0+
z&^yAa`~Z?Jtd@23{&QsspM?oGmiOn7ac4bz5;7jF)wDS{&f0DVa)KpV1Q9Qm<a?lb
zv(lHqUmw<MkHTMHR<RW#eypI&@GyY&Pc~YCtXJt_9mIOE48sm)WzbUOBr9t(^g>u)
z-$v^cYYD!QiGNDQ%BS>pIO|(_bwsdYABS&|tfueaMHFj6FMNt-ZScZiVpxu}9E)Y$
ziU)~f#n4kLp7qjaP)}ezv>YOdtjly}CyBMa1A56U=d<uPh4nBU5=v!Rcf-ONRts(B
z(^wA|z=AD<WnT$;mK8=HwaH|?RRgpvR`OQBoMUa7gJ>@6XR3wIV|`E8Y(C3A015@H
zNg{<TC2elcvuxyH5$o|o=qzS+HAB6G^#ScWN?FD;Fki+JMFFgwmGdd)se<(ft#T@D
zEZY=Bt696~tyaUzrrOqvEXVz5)w0Hgz`n%Vwg{bdtaw`1*RwuW!;8zTK0lBvtTc*L
zH?R_EciG5VN*^(8Vr`+5N6oB&H(|bo)uu;hD{JCMfL&u9phA*1Rv;aMzRt2;-wkFv
zt2zXt9jyOR9cm|Q{RAxCWPQI5*j=pg3lQmHZQlY%ds!X9=<H)DOE8#zmbw;_w^>dP
zqBX#(R6%5r)kYESVb+gS3vq{K|2oJBtMwY7M_Ir80I<8PuPAal##(4oLw}srOnJdc
z))Vx~xyK5u1lkm<g(^;`S=+-fdo!$27x+EP+CW>JIo4|wyqITgqWs)_)^3_^dv+gP
zmJVzi4|)gL1$}58VvjuyOHOQW%F;Qr`{;#vm_2kDm`B)Oo~8iOQFhNBXt=U_--C=B
z+ZqWpclP6NLdJvr8SMd&u@`<1krV9vXtcc8uYZ7+H~Se%vHGxIrhSDkyU&cV__5m_
z$5{N?QMX|!kbRMAn1a}k^gu6|9Z4SrJjs5Za_k}OpD$Cz%_(->B+x?HtLb?Y&JLyb
zK?M82G&CaFC+STa#ok2WnP_$sRXfJ8r?a6S%YKvA;&JRVm!S~Po(_Oy0^98g@J_Su
zZ^T%V*gvI1A({Qa3@oIu3p9{SWjE0R@C>^?iV`Sk>|l!8r?W@?0oqyi^cR?tO!f>#
zQnJ{opF-mtTkVOfC7azwPw6~%8HG9W*}KXhQo#OY6~<f0zD(h-^XxdvZx^xGd;`o2
z?ByFUq++%+?Pp8aS#jtrV}~q(NIAP&3=eG;?0Bj%tz@s+2$?GO7ACN3*mkc$@gmz*
z2VN~ZgUV9s*dluE*R!uFFc+8Ek5DA^3VUM#Tx(!|{2oXndtE=Uud+X)y>c@<@(4%^
zJGTzdt?VWLRba9cuK}fvZKS=!bsO6#0rLj?4LXwD!R}lH>`r#`LCD->H+=wJ7ki!p
z$G6yro8eP8``|`+*vIyzb7KAMRYH*4?8Y|e4Y14KfaD-MjBcDEw!sX^VfK$h0K3Bu
zrlsNtTfGJ3F55%_%`vuZ8QomtY&VKZO|U<sJliB&pAVQRwhvW6PqVjaL1x%-1L&M%
zODRh~&z8`Ic%MB;U!k(+JoGbu7zfV#2|#h=TpC2{Acyxppq)7U5=c68%G}U8%z5Hr
zC>-IOO@P}+Ijd~+igw{V;f8_Y?B*5t?ao;ygQy2*BpSS998Y@tdvX}`&_2#7UJTv|
zjyHWD!H09`U$lHVtj{n|KhENx(DLW#X^j}bQEY}nAm{UBw1POlQ}iL2^TatgbCRQ`
zWZx-H#9>;0hH_Rvhh`Y3idH7!oaTI>MQ~0O<EM<`{7M1fXwIHp@FIru1|>k_ICU#9
z!g$U{OQD{?nRkcVr#WBKA}x^<xB-$$oIVEBlR0nlftku#`Ug<Xa8|wmlE%47tA=#W
zcaKv7GlR41akzMv^Vn|mW^&$3!-a8<GeTRoY)*1I^m90`H^FW$Cy-wId7N}6I`cX9
zl+ZiRiRZy?5obpo)Gu%*H=|X|iKn}%g!5(|NGWFph5O1l-_TONoO2)sA{CrCT=BNW
zm7LhG0aL|ExeaDD=e1mnsfHt`f{BZqKf*B=wVW>k(7MENq{KiS=ePgPMsa>r!<oyR
z=gm;K!pR5+Y2XNpfzre=)4s8p6Hoj47EbkdkZk1`sciNdCn5so+c-0{S+QN`ptt}x
z0OuikSG9Bgp>S9SM@oULPR^~zpnsDS$${N2&Y9!DzQuWgGAG@ffjo?<hciu?|6b0o
zKVVAwI9v0f*U!oKfit%`pBSM&z!|06VVHC0O?YvKlXMEL5snXK$wzIR7n)%AE~l1)
z_hX#IH(+9%ld=(@6CB6i0XoT9F#~ds(@ZJlDGuKr7t1s!t^i)la9*cUl37m8S)k2v
z9CVPJ=ji`H>psU}FHr2cn_mN_1DDkeJxA`_chNe?{pt(woVhj*t#%G`U7v@;N4O?B
z)^L=&&JEZu+?65_SMFk(1UIgj47zh)s0H!h-hTlmj&a@T>h$DB%%JlGH*yBfcyV8@
zLCc%#F#<gwZu|~d^5w3phFw2yhdYQrcYG%d1#mCfXtfi_HB%Hjh}#kXW-xd5DUc9u
zDV2<#;?DKML@4(midKbjD`+1U&OJtzED_xF8gxc--#Z1nQCz2Okc{TmP!=hMTi60#
zESI+fB%W*d1YRU?gL=?9%{@>H*AlsPdaCM9;?67tN#;I4(YzF{8~tjj+~qD9;TdjA
zH#*a}udRcAI`?6^yfV3JT3lvvKU@oubKI6M;Y>EyV+zC0;d;{rk;@e=L1!Mf>}xoa
z&pk-R<OST#OJKf`%VtCGJhyy~-hUUk!@t1qVy+*3KdOW)ryN`<*WMiiE#t21hDJFz
zb1g^(_syR%&`R#u1}Ic<-=-p+YVL|e@M^dvPEfDqPL0F+OWX&(MQ0s%?;7}2&+Vv$
z-evA*T)1|H>rd6f4cv({^bZpnxv@xOF22fL-wMzs?)#rZrkNXh5;CpaGWzu9HEt*E
zY1_ETbOm1LhLoUngZtCpAnn}g524q=eO?R6PVS@M!|qM)w|CLm#SNra<Sp)Min;c3
zA1%g^`nbQ+ioT!Aq3xLMHurBzp$~9fR)P$24-LWLA?~Mpp*YOl69<hu+;j?1jc`xB
z0PIn&me#LhTqd1~9Ov$?g})QrQ2|U$a!siKy~lNOgELcHCppM8x0Vhg&u~3f0&JH1
zOfp2~xKqvG&D*$DJ3;MvE4KmLfw$=^h&u8fUk}iOJQ0O|4)GqOn4uGIX)uU0k9P@{
z4)X+5d2@u<Li2Q#=lCwLU3g!mL&S}DPlQf)9<v0NJa~R|@ZuP6a~u>rdEK9a9On(w
zjede>E29j)7tim%jRo(t7#co2EhV~qdH+(zCV=;a7g~Y5#~#IagLplZ=ndv^oj^|V
zf>|ITJf~%F`xGyeUgDv=taz9R<7LtFCY(3B8PgTPdu<YuQ9K20lA?Jxt&oi2McL>x
zZn3;4w!=gm?|aHf#PfV8c$UEX>kgbb%{x8|jYQtFJ3x|nqfbLIna4Q-kyPGTJz8gY
zFH<#98n2T+c$3Zx^oQLH-a`5q$64MueKjkScXu(&XYrN_Fzj=@pW^_X%{#W$2ALcl
zs}nMLysMOF$mi`yf~5jpd?!dDZ<H3p=XvXGAVoaWHvA$Nc+WP%L@{r_2S^F;{9fpl
z@;<x>pUQZ{3}9FCthD;B;{DPIg=${S1CXrYZKmziMcy}b=Af1ru$R90bcv_@6*6_a
z_hJE4&y!K@@@3v3DKxI|+=n3A$lFAvYgc*SZ33@}my`_bX5Py0A=1J#w?m|rmm36f
zjaNm7N!ob(X*+hEclrPnZtzyTg>km?deR}%$@`-X<R-8AD((Necq5fy-r`+Kgkm@E
zFIqPA@LYz_*~@z}5SIFQ_4FS{`gy!YDBk9+UjUH-p3C158RGr^7DR@57v6`ZJG>-c
z3}S@0gR1IAdFvcN?(&46LSc+Ib`Cy`^Zaf?a)Q^h9qP78-nUNBxW`jdv~7kLPkWbH
zUON3EbG+lPLuQ`0z7rz%d5!ex2z&niFJRDtUrZi4@;{9QImpld2kM9T@!n8(;)mK{
zMi28}r1aboeiN-!kMbX-eXa}N%K?(E{10D+Gj2A10Of7n`GwyC)Pw)^CJgi#KQ<gp
zPkwd{u#fYrC=BDp-%BT^y!nrsV8Vz0PdfB``8O-j>BnEU2mbo=Qx>5Wzz-pVf&AA_
zLobLQcN3VweDmkPJju5U!Cai;mxsfPP`<59jAj@=jE`nGf1VbX5&WD6n26-BrCPfv
zeqSm&qxsL?gh&j3IjzoO`KKu!AIJZW-dLyk9TXQ&<oDAyKZzejS%GAJChd7r_$#Rd
zIhCJEoAxt&2|aew_@xv=OXn}K#iN<QKTwb6S^nP_p^?SkL|c$^e8+N-Z2s%CK+oa-
zAb@@@|5tjO=JC&0!frmlfe&5*|5FMw7V;g|!L{@J^%M^*;%84oq?o@h0Id>!7FE=j
z@*n#Rq>SHANyBn}`}4H^tl-b&L%)*W;1B&O{=Qux)%^8)AX>xsUyU(c<Oh|){3ZU!
zkHFtLeiYRa)bqV5H*uLCOGj|7@Lf^?+Q3f`gEaD^sp|eJ-+TzrP5hO?Xf^XcXoE8?
z{GVh{XyXr0(EWFv|Li(=dV}9bLCQ{k|4(4v<Uji|M&HF((p(Pk@6h?0LH^IQyBgyA
zXTk0;{|H6W@9_0TkP*H+Jt0Q<UnaoBUB3ONkR0PX$uPii{#i#1VuHW#ceEz?=9Lh+
z#}{B^w#8HYG}_ot^UXg(e}=!7-n+B>dU~YI@dsXp#yo%Lc98pgk9BayUQqKr6dVMP
z?1PA-z`GPfJ1BVaS9Bf{eEJl|>m(>wV@S?|C47wKu;6hzV|YZcifTrW3c~3ccM(ie
zHqGWLsCfy)b`!X*f~dP7@C0By1hZ7Xa7?hB9&nxlBPC~#3to>x=Lx|sZ?wDw6;|-P
z1!+`M=p%URf8hBFVyu{aKLP7BQ2YfYYIFt&^63p7C~%@*IY{skg*bx+TuStvv<dX|
z5DO8wP=(?t!ESoBhYEfhfoPauGyUk{0;fiRMhO0R6`+xVX*%;0CD<DT{b<44UqUiQ
zV4Z+Stl-l%n36a_1r>J13(inHJwXuh4@6E2YENLiiGmMXF*8YmBld7RSzsHY7iWrK
z3ta-Kg5__(;2FVMHbm0|Tj{BnE;twjpE3k*mP6#MpsxbFOo3w>I<o|(LSUa0jM6$k
zTkzIyDC7uQe?VuxU?mfd76?|;Ubay1*&LiXFX*Idgd%|;1tJ#&gEp#WDi&nKLBB-s
zMj@D`f`#wEr!v6~TKSa=@+r7kA-GKyaFv2ds^6;;4AaF{E%<p2)N2HHuEFj_0e3GH
zY6Whzn7t%mJOuM~g1_nhs~5!Z(0N(#RTQAF2qcuCX%M`#gTg?K0`UUqUlr`?MQ@Yf
zRsuSk1rZWxv<ObN0j5>3gVM;?1P8}qw@naW1?Y7_CDm2m5Y*D?qIQ8pGf+ANyE|Z_
zQ&93FS~mq^3dnT{^yyHzC8(v#qg${@1YVCIBmBSopWv6T0MjSPqN0j^!Q1r0zAZ4^
zg24g7O4`^D3f$-mNJE0fbT<wQ%HBuojvychA|rxnT4;|7meIoVuHYBSLyrj#lt5%$
z(BA~R6N1{`;Nhg;=>~}06Re?F#gw2F1GFuk76e=Xb4C!l7{i_we3uHDIl-rK@M2z&
zL3^$Hf<shCZZDLF0n|bG1U(EKg(Z|OJt&N!BDq6C@rwX;68=M>17~3w)ifOzUicTT
z9TB#yK<lV*oa&ohgyXcncNO}pL2PcqZmNoK7yj!GPd$Z&9WZfR*fodF6GHEJjMqz;
zQwK}l!Y7wQ!$-)cz>TkP#seaLLgQ+*{Du1esz-#`O=txQyQ!)nNLWRSykMa_75bhO
zUZwj!M3|ig%u~Y1K)4-h6MioTXqfPybr^lPu&x8l2;nw8L?eYx$&iT>zWN44qJ?pv
zfy4-PkKhuB6+Zkp9E}q`wFi>%!i7)5`vhUW8oblOm?fBmMBx(3LM930a?nZ^mYSfR
zB7EQ;BvXZTj{y3N(B?UT-ZY`*Cp6QA?i3%$5Pm^hpR>Yu>BwKEu%CR&67Huc?m1yj
z5Ja+t2Ob75NBAX`O5_ShmxJU9qtp<|7fw)=y+HUOJ@tx&kA*|wg0Oc4b5Sg0sxUJp
zLIXV^N`<Fvdw^XgY>J0yxiFJTQYwT8^PpcTbUO;gDq$X#5mgJ9(pIfT7#Ix6i$eb<
zOlhs~i~*gOgwYQJtxovYN~m8Eej)*B5I#VW$3~%q0Y|S2H&NwJlW<WEB%6i0w*cKD
z{76grhgRX53cy?wPEpRQO_)g4MAwB3S|r{OF2LX7c46jLh;#_|eFyWM!s>_7c~iKQ
z9)(>(PYOca5{A)5-YsmPGbuen_fJ52g+)|G+b0xsK(AlOq4fW4VI3tg2ZW<K`r_fB
zFl-?_9TLvl!S1l|;(4_02pK#mjtJ9J(Ha%LPrt!kVG0G4#)KI$&>t7RP3!Fmp%>Mu
zObXp8@N!T12oJ3(;m=%%Obh?&!OuG*JWC<RSz)|8Fz1B2LX2}>SZMcO{#_V#48GZm
z*mOq3LA0kEqK=}1HJG-8qLChG91=aU06Ztr+>cOn7Cp8cyu+fU)95@RV(fy!qoSWE
z?cySe{sUgPic;uN=qCEI4C?NprV|*Mhv=WjpngnbPnAxdqN5rR+i_7z9+)RY`zU4S
zC2EiZ&0Ey95bpbkD&7RoSG3a=oqi$*dgJ+vo+p?9(f3zjDNwX}A0&fB1C&P#7I}XK
zFHVXc9EM1UsDKXdoDxku3rnFQFZx(fm}n`zVZ%kcsbVg|CW_w){b*4hJq=<+PiDeW
ztjLdUfH=_uVE~O6`D{jKg6Pv3ICEOmm<AJxqFpOsB1t4Kgh;aJZ>q~q5q)ApD^;|U
z!qjI(>-0cL6BW>gBwaM?4wMYhV-yQME7F9cl_|0vr+r+O=snu+o)h^lf=0GT{Sjbt
zMBh-VFIV&_73$}SQex4WFZ$<6NEV2WanLFh`MIHWUi7&W23jO)@&&mdD*g@F#iGvx
z0ahZ~LGjB{(c=f;Z<#3hBk;;aC6vUh5Iter4il9k=F>o{5`EQ(R<%fyg;tH|m0@6C
z6vfdz*NRvabH5}yL~G(Y(Kae*s~3d_V=$LRm*}5@T@lT$houHl6|JS4M1v(zZx-3d
zfV7B=N1@j$TDS+iYof=f%B@YbEX@XQu8S0fkhvjpq8DzvsQGP(c8GqbKwzint3M%f
zQ#7{?id~|o>AJcl3X6hI-J->Bp|eNC;eqsuBy%8rqOVO*=of|0qjg(Un**=`(c=^l
z9~9l911CeGtFcfY7A>u(6Nh(1wX}p95e+^A_eVv}*^s#_>MFp{#zY$_WHK&_p&agn
z$mvm-pA;oinbJMc?G{Ypl<1g06sAQ<FM~HDdYaDu%!*c1TwqR=Tn)W>5o-^??u#C#
zGG}{nHI>FYh;1SC{&N&RK#!e+;`vT64~dgL2AY$&c?mR}#Xgj&JS+}-0UAfdzkLY1
zN5yab4G|Zy>Msyi@$dAKaT9yI4)gBfBUHTLAx=?2@0j@8HgtN5z1rc$aq(p)Bu|Ka
z=rq2USU?wq&0B1vk|H1R%SsSm@g+KU>?dADc`bkO$!`D?ARc=bpn>8y=y4Y$o~QUt
zu=vHxfH^6iq$;}*u{TwGof5C0)Jmv$1FfgR#2@vc6)ygTGSCs?IB&Ef#V;IyLX_C?
zbC{2|i7!!hAV&P=as1lx;<dYBK0%!KF<Pg^Yv^U1DCS>6XOj3~70f4#{ayn}5z8M1
zXsY;GN?n~1XYfGM#QP$lmo5%_4fB*C9$N@<R-9-L*D}R#ZiU?}aXx)|<(zoe*MQCz
z+X4>&CP%!G(#yHx-E@LBPkbOBCi2CtAs_|f9UDOk#b4imiSy$8^B_gy=cLfTAg*5x
z6UE{U^xcdSv0FWOrQ(VUuv8}gjUHa*VlfLM72<c(pin99(7~B1@i))IUbXlO8wayc
zBYv_LCN7E-#xQNQ;t5yybV<DU6`<9LyXcI5y?Eg=kjvsNR3C9goWcQUgZL(81scV^
z^fJCG{+q6nCh@1ekZcxD(IViQSgS;5o4AGQL9UDMQ{l@E@wRBV)-E1eMa$R@@dFd^
ztyA1P4rgwPpQ?h3U1Ig0fVm~!PrJ!(u|F-gdc;>KOx7z7af73M;`>y6*)M*bzUOjV
ztZD-p5Vuot%b@sXJHUp-+frd+So|2(mfaCwe;59ah##7Vg;8<mW~zU=D_%-@+A*;m
zo$nqOcheeVLi`B5+9$<H8L)d#eBKY8Q{vd;Ak$*~FX)^RZy$ijtoVU?csM71hmOV0
zi+4=G?tO8A7Yy1<*53wkkoePb&{0xF%h!Vv)~j&)kYoV@kG9255>E=YJ4+I1V{usW
z=2m!dMDh@=I*v;AuY`t+<oRC#>MC)jAI3uxPWjGblIq{!g{S1D6sRAUEbBz)35khH
z7ri8pC!*6^Qg$0t;v-qH9D2SI{nvo@lic|m(EgIOuY+d`kleov6M+&>8fcKD{CBj1
zCHb_MJ}F7tjq!#`HdC-7Ok#TvCc-5Jl$(f<EL?^$MN0mnSVffN?=XNyOKKcoB1Y2g
z1`;bd76Gt0NigkY<0S$*UyvYSP$u`ZWZ*lHM4RMEU&tg$0+(R)$&zK?04+tbh!5;k
zN#K+4;*8`8y8Y86BeQ6wO9JVd%aFwX3(&KYglG&cQ?h{~=vk6~iUD>`Qrm@Awj>`X
z)E4JRM(Ipvt|XUM^m&p&CM@Jj=C44cKw?Yx0xguR-wT=Z5@))uiX_}{C|-~xPy(-5
z^6Y(#zC`lfEIcfg3{hmNOd=gYt6UPY0Ol(s2loTCQj)`kLY3qj+D=tV+L_?hNP;ed
zcTw{G)9|-e^3Oah)Je9}|DULr9I!0{y)1cD2IdvXs%>zlL6S$u+8ZTtT9B)fm4Cxh
zljKbrXtU%qiqy17exV6&mE?X2g=-Q4W%b%5A^!vRb;<8b;KdEe%17XKyX0reIp37r
zri5;nM06UGw<O=JMQ68U+?f`&J(2`}fc8qls6e()vW=c1{Sq@>mbWEQK5%V7!ub%x
z9+Zr{43Qy8sQ|5E$!>Ru+>zk_f8wr^6m$S(RC0<g#JiHLM}RUWNo1pQTypAF=uJpo
zjDy0Y<PVB?+>;!hr31uMk~Atco0d#dbYn&`VgcH$B*PVCPV!L=EX_-z{o($7$pUA9
z+Dpr*2*^QNPCFn+>0SzKAC&%i9}0)0YpLwsN&3TTU^+|t)4@9|jiO-A5$RK15IHIp
zP}bB%I{h5gpSenxY=sFo=~{{+xl0W-knxcILkE(MNx77)_LL4k1C8U-n-t(WA#G2<
z2)(485g^{ue+xi-r2A<{;49sqi}CtN_s}s&f9WH?!hC?ViLRhP=?;3b1WEs<>`Acn
z@hI?YC#CjuVk<;iO4VJbq_0!fHB@?(V&`Gf8H($LOV>3*G(viwk{XfH=|LEbk}mLu
zLbP<)1D!Eaejrd{rAI!2LYy>+-l_3Y85iCsNULenep+e`1ZJW%lODE7(lr@qCEKK%
z!$DJ|&SwCVD*ZVJmd;4eQxGdnT0oi6bm@0=!)Hi)9zg4?w47qenbHG=AX!pPA9&}a
z^R&OnmRhgFQjYXIB|~zh>+N7ZPrB_RNajmD=@D8W{hT8Ig;LcaNS>G4zTA&d6iG+v
zu~j17bqvmwN>?k<Stf0vz)iXIf*u+b()awptCYIdgI6Wpeh|EBX+|q}HPVig;9ZnH
zOrII5m6p;Sb4mIoZR6^sXAi?tz0`{;5id)-eW7<nI&cl7LHdEM2pWyj@iCacDz!_7
zMw7Jv4*YJGwpuXHEz$>Pz-yIuzX$zm(hAzGw@G_H2JgD`S6V&akiLHbdhOBzO80a~
zA6Nm*PU+SyAUCDGA3(B8+HnUS-jY5Riuvu9dQk~)k2LBHiof(qH_t<+Px^p2WcsD{
z6s5Q=eU4&i15)#UH=gwR5r_;)c~sRhEPaXsV|Sz;PXKL1dVsE^QR%DnlDR8wJOgLO
zr1cL1Y+Ne;60HeoDU~-(O4GTRynE7fbS7*{`oVq5zfVggBS4#xZrlRVS*egNs5xme
zJq6~a8P5RpzVtl-6zyfdJ_1k&*=@Sm9A)p)g?LbQ`3yP_$u2pd<s@528&zjn1#O8B
z%ijMJ13e-;Mz8&&G68)`%S9%?gicqP5$hA%VmH~>E1>T#OU{Ff9<r(HkU1v1zZIRH
zva+vW_qZ(LckoWgKA?@1mn>xtj(W?Ueil4m*@tv<_{mW2i#twMPd8V9Y|&<z2$W^!
zf&|ITuc0$oX7mU2N!b$)7*dGL@FF^Gr)2R|X%i~*iA6I^w*5Jfa9KRX8Y5(j$nQv5
z^1Cn*C1cU*J6iSv9XW}S{YvZCSlP1*OkSL<PKsg2%N*8&mmuTOzT~v*#CeD$%GQ>m
zl_Yy|3?j+0^#1`RMJ5Y|YpFKb@D`XjBiq>tW|~aLhTU}8=KV03A=~>ET4!aOX>*q;
zE2r&tmTUoK$Ii)qcn*5mvbQK&og;hwAS82TuaSv7Sw8K<@@4B@hDd?z4NtTRWu7$7
z^Rf@Atg1-X)&z1vX4B9)k7C&tTJD#~c2dBnR8~ge`7+r%>!DFD^P{kFrEJ3;n5dGq
zI-s*!_8TR#Yh>02C|s2NkM=yZGDbEGUXrcu!p~GEOUy&7Ue-tlL@&#3O3=C@<I^^w
zL3Zsl9Bq{Cu+gP=RaU`*`6gNIeZVx!mYs)2i|ng)Ag!{m_e0~F?3o}~YLgXdp?F<Z
z@jQloLne=b7wxjPZE&qa*1HH`owDp^=-rgPxfrBNc8qerw`9`?K)Pi^l(6rSc~fy^
zudJ|%-hX|v`&ls2FPo#l+HDz+Qcwdj_e&syvJQ%b56L#u4?8T2+XNGLWcG9veMI*4
zJD7`6nU-Q%cV!Lq^cj<}K7zuy%q0&B6SAo&*qxM_?nCmPtm}2~resl+{-2gjt)}?r
zjI5qk53{mAzJM2VvSqXao0s*Shs=H1Ypw9fUj8rMRf`?ujr%|j$@}Pdt&{wTKp1qE
zvwi?MEH9;-@`yb6HMEY(wb@X2k-wh;e_iFTr-8W1-wS|<yL_JnEf0Aef@ZeG$K(rW
zpY16(&>rBpywwjfC*(JN!0dU+vuRo9EnoN;2IC_a(d*1tzTFohe)1k#@cPSJY3CFm
z|Nat00_7sA!3~mgt3ZO~uX)3Zlk%6o053%TI4yxr$yFoZh033}2x1G9zd=jYaQVSM
zffgZONHY{EXFdcHCI7w$o<_@mq+-VydDRB!$I4xI!?iehp$H^ip8Enwg8bWKu#_ZU
z@)A&z<zK%Fg%tTqFQGG4UQ4(C8F>=DRnp`;<{^?UzpH@T88*3%YE{n4$CE)a<yyMR
zvgBJM;L|zzjy2HFmjAI2Gm|54+60m-ze=(GJb4P$dgaT%n?q-ToO2l1h4PTK=sYiP
zxeHPxkEUYb3v$;)h!o3TrNnHByfGfXa;e;n1q)?zn>&?al*?s~XjaH&JD^x8@45nw
zD*0x*#jE9c6vnBMpQNqcMLCBy(Y5k22f$pC@Ba<FI=Q1e22(HZ35WNW<tyUQc}2d3
zo`DVWa~pxuC@<Uy-c|YRKTvOybLi#NEVtUqF*Pmn4U{Eol{d7*?lrkzJ7n7Adh+zT
z{F*1wZpcRtL!({(<_D1Mkl)IINT)pBjLw_#cWM9ECFd();+A|f<s^IMH!>mFC*Nhk
zboI-BN&(7k`8om{khkpx8I%`&<|UeX!8TnBy}R;>S73cio|6OKxO`{;)+gk;VUS7r
z_f)WUPp<k4m{amY6m6cCw~T<y$oJ4W-dVYiCs5|(om7xCFAwyE+57TpCe-Z}eEPzG
zgW}<(m_kRzUo^`H6`wqbi8-X`vPDACN#RP9?yNXQ1+Iq`CmVo$MA1x3@uP~MCD3<K
zy!JFYT@_zb-HV%|n~hPsD~7J1<$+G<9a99+%E@0L@`K#~#aD|#0u`lH3=^bqrTt>C
z!tQIhc2e;_%Fl!-cE3Y=;8Timda#8m%J-lZrnpJ<f#HhpkHdU~VmD<GBNdvP(1=o8
zr3GBHV%Ki)VieL8j3QPcx(8mILPC3_c*RH~oJmkTLa*f0irRfpNK~Ar0Bw@ukLB<%
zS+VP5kQ9Z(pA>^iRlNT#nr9RVLg=R{a%u69uGme54H=3(RN;13ah%rvnTj|51<6wE
zq~lBH6bbKQFxiU2BQTMpNcV(^T!jnWaCwT2pTT^-;_c@#vI0e}J30#$lEoO{dBtT~
zY85NK-@IsnWO0ciA`rc$3Qt-+mnnYO2hegw(q8CSD5U>_SE-0o0j5gv!Y=Tt6(7^u
z@}fe_fJm)k)+=mgrA?6m%*%>Y`b60k#SJQlYET#`>))vO?i9#X#ZL@4-=w%pZ^mZD
z4qDx}C`J=-6}KvW&BQRTDbjui?}lOrJ!;z(ZW@qI#iK<~zo|IC8^*g77snxTOW`vD
z(ycgU2mg8$zP22|^eXmHJi1TupcQESiZH5oxvh{T!nFZK3yo+{vF;>9h7?s)*)pt<
zT?6PH#c=~%8&T}1vy!8VC+Uj4s}Qe6YfN!H1YqNemST_z#mZEWNyWVduy;?fnQogY
zMgG@RKsc@V`4%*06st-BI;&7oXk$*1@+Pq772ohNz4sOU6pnLHZl#5yqjFIMBo8WM
zDYoaVJP-liVdZz_7}^o#hQsjUs4`$2k}k^o7FcpscD)PYp)^)Q;h6HdWf1XHzO<VT
z*?K8gQGI~7@|z0C_$W0Jw0xC1`px{59SsomS8`TkN&}Qz>D*4B(n^<8kkXS%M1qyY
z6#YM`{AVfDLzGDrcsr&1i87I)%0*sig(>$^MO(OX!97SuC?ns1dZhAN57m-IDL2<*
zgwe`^Q((p@&(Rw>R{1`a(!?q6{tRBc@=?lSCn(+j%L*&6{{*x|<pdSaBq_t=;aak?
z=vg?EqFhhccB*ol4xML|UUy(AO<DU5TItGxFVV_SesvqrXO&%qY0FgdF2d6+rBe%J
z&M9{qFhkkOjUFI5%H^#9%~fuD6rcsl6gpE^sI;Sn;(4WU9n2RguY3e@K`DI?*u~0^
zQ_(6>F3169sj@2qj+QBFsR+7U>0Jbo3gtVAFjT25q?cxuO&O&JtyX4S2dPnZbD)1w
zIhqB#waR+>7}O=@97TQVl-?S6QLl8}1MJJn^gMuGQ5Mo-y+OG<9D0q)z*A^7D=Vnd
zu|-)+Ra~t~Lp1cRDcvrBv?*Eic)PBA@@<IRP})Af0u$}Z?GHk<L;1`UM%bnN;6b=}
zOS#+ucDt3QJs>iy-1-u*?<iMO^kYPs{vh<nlt#+6jw@fKhx>$bln&!eDl=MO>7H_i
z-g;BYl9g!9DxcB9?wry}S-*MZ9*V*{s9v<uX39}z`5#~osy0%r?T{*!P9{02qIUz$
zS=B%udaBmaw)(hg!Fk+ACsfSWVctu%ITLPstGI=*<fC$>^tG?5kV;bgR4-CA!C&<u
zO>BT_ekmjaRgazmFGzKQcCx{$AwM#IQuQ&NRSr>&(_DtCjC5gysUpkq8-%MmC}0tx
zdY;xXk*a|nw4zjX^t_2xdHO&vPPH~4ym-|*iYF(iPW8gk)2h#Co)T3>D`6=~)mMfg
zC97Vkfk=v~Cj$zps+F=On{kz@Y++!gsaPw4mah8qEy!f3exUH-S=G}v@G@1yo$x73
z_2nkm%~1vTbUd)q*0=!j=T*`4`G_Kwe-8vNs2=<kqb^o$qC)^BD$CmdDOD}L2gx#(
zhO+JDs@&u7tU^^s)ex1clHZ_LrCRbE=B`>*w+#w4D!DU6E~<*R0J>H+LIre}RL&-}
z>Qs9gz^hlq+rEQ-gQ_7Cq)p{RE9mR0Nh+1Uq547uw04!0mg*g<{Z#(csdA<heO;=y
zFTlH{`lc0<-KzJ<!yZ)?6WG0~O!~M<pDK_Js`abfXgP6PmFonBLDeD(^AD-&UEuGq
zYTAR+uy<4gG<PGaw=-aVRJEUS*>_cK)c_q+ZL^1K<ElT8p*5k(rBlt5D(O#{nJLvq
zI?_6=V$oY+M)k*E;LWPIRDd_9;!?%lylU)kK;Ku1iP)=MX%Xh2ZaR<AJE~0v`i{v#
z^@=~Ccu2jQY7(8)sr^uNR{wSzpoi7#e~0@=)XV<@@2I*f2$C-9c}hWesM%DV>ZuN%
z1om<D#YZs06Y3xKg6E~?I-=8CUDpVMKI%p)PViUf+`w1@)cYyD5UAeIp>05rI^k6?
zgVip%P&}!=A_56f@1fx3DfRtk{Mw;vCVkN@TwO?^*9i5#A&5k(*(ZS(rT%Oi)T7l$
zUV-@-_3C-J9jg}8$~jK`X$(-})ocF*N`hMbJQPl={T2cxQSD2I4s6Nl2almQMLq3-
zW~$nSKB9I;z3&J>)6|cu(aKO?I|zek)mtcZo2j<t0xe7ZWi~|4sn=6XE?X_^K`Tdn
zf(+)VlPFV^uePK5*#h-KDr75EAEl4woL6Tv;98M-1ueWU*wjA=V4_?d@CN3&Lj3^U
zVwLLuQChP~{j?s~)#_gsfp<~;F2xjT)nY0Sy`-MF3f^UPEPX=mirS?RCK}X_(6^Bq
z)r)AAdsRJ5M^c;BgA~bZQU6RQj$73-22if6i(dfmhT3MeVleIMfd$a$P!CZsu2X&f
zJTz{q?>-BSF7?(wAlj{#1wpb$y>A%|_Ns3-g4d_k-GCSUYH2QJ=C;~g05YJyHi1D5
zsu^_dY)JhlC7MRmZ#DsQRK1pVpm)`gN}!CXci27x_PF}WEifn4muVMsPtAA`b2+7M
zru5*n`r0cHnNjyh(K)N0*$M3X>b<3qwAVcN-|kei^eJ>YYQ7S|`-2)!3Opau#QMOz
zv*ztpkUXq;_aw*>%{*;6k7|l;fVgNLi=(BByXLh4h<a!?orQ^G8W$N{^wbpOLgu*U
zku4x6GzERo_tH2}O3Yi+(FhSgO+*qp{WUHW3JK7-(v~JrBc%vKkY)jWt?H!agX2&L
z(S)1_Ii;DQNNAX*ZyAOgu33JCmcS9399K+!q=vHt=A$(6O@N8kB)*7gi`8_{!J;_L
zUk|}xyyhu-8763SJ`g#r>H83Ri5f#M3?^$9zYK#Znq35zs`-mnk!Lh2s?kf+Y@q2n
zt9kbu%zCD#%>tAx&8=6c4Dg)hU6RSxq;7zIj%JGN=4zCoa4}C)oB@)r`H{+j3N#M=
z;1y~fn1(awHMKDyMVc5&?_bayr?T*3&A|*<D$%^W8N5=>lodZ=nZ``P(h5yz8QiYa
z@Lq+zDvj&gaMV_<*-iW48clWyU@mGNjs&w-qjrb>CCz>+@T${{&H$!f^D3QvzpOb<
zQPwM(5559ugGN&U(x_?efXG$N_P@|-(o9L=Ota<|ZM0f6%Qga~Rr9R?=C5hCYyoN0
z{6odDH*A_{dSJ9`ti>38hvx1xV0LQ6lqI>T(LMl6U7D$SjQ*CU?ql$}HTga8qDS+_
zf1l;jNTz_@r&&r7oPG_H@(Z^$;!r3IXx_Vxkqv70T}0=QX5cB1VU6k~kUJXd$3Pj?
z*m`b3@vi0*ddZAwP8h(P)OgTl>YnC@a*!#_A4wq78hd)l%xHe5$MdXaY6sk&)2!SB
z-n=G~BF^_Ux9C}7ul?x@@Eo*{Sz+E$TNDn3gW4+c;*fTXYV@46pFE0AXYFq`s(3i8
zWhcY@5v`j$m`AlsR>L<J?eYmsf~)p3s-Jh$9=D+7uFcJdqKEcQFR+hkU1)3MscolP
zpX1t}DPDd;yOmZTUfK;txaO_p#KCPJZC5W^zFJEY!2Gl_`tAL-H&SWo5};iYgJz&s
zSqJ?f?V$>21ZyKSn8cG>;X+`CXb=4ZkyF|ahM*9t?HmJ%&~^*qeWW&$B8ySlMHJtR
z);>frpBSz9HK4?5GwI0`r@indNW6B%QkYNB9_c_UQ5zUUX`m#nYXW+cwc`}APSe(U
z!*06P@C}^F(5|D+`C0As7`({TX1@x9S=w)^!8@n@gm(4W+D#5X%h8%LVK7&#r^_Qx
z`!*L~`Pz3rfujZ5?|uWXP&*S0-g&Jo512(-PwY`_i!W$*(YeoJt?6Bm676SYFj1;q
zLK<b->-V8iuC1+shZWk7JU}Y74^f#}mG)7(0;{zjW<aDy>vs_f7qthH;aaVBCA|$V
zX-^t4YjxU}XP{88t@;G5%Uanue7d5QHNb6KgZ6(EaA?$aIf7i(K1y5tCT+tNSZdZ@
zVF0Z~+jA1FR_%(tP`susF=N<m+Sh1Fd|m6l03tWER|DWhyEc~rUWfL3N?>+sAKeO(
zo7$3DTo7Ga0R>2IX+Ng)e7836QRwy9w00D4@73PTLbFfnMYXd1+Es61Ft@d>FF|xb
zyM>k_gWA=;7}Jn;;j{32SUa^22JdL=htV3*ZmU6SRC|M#Fn6^Z=>0XOUDyqO$F)-{
zKqj;r?9>)dYFYF#!D;PQs%x3i+PrCLFsro-1)0+p`oYA!_Te=Ey|3+l2B7vj@lkX-
z=zgL6tD}y$1|A;Ny-Y9MLpl{buAFp(BT#qNRqlq{hjmg%NFLFxnnmYPosF&w7u}LM
zv|M#Z8ld2&bCd$wT{mRw2KCTIe+`Xey3p;A@zgE91Q(C%Rvduc6T0FOIOC;r{s{)X
zb(<qGLLc4xlq2=kjd?=SPiLUDyT9)0gBVkQE`?rWfx1I$AaYW7lnP=(bqlC&B24E<
zOWSbWx+FkH=*s)){)^OI{sc}%>EuU2qIIv(!!Jg6mICIny0Jc(h|_&e>En3ahJAoZ
z&^;oBzo&KcsZdYUeV+tglJ2b~a5PyL=mzx^T|9k^BvtqK3?$F!E-)dIrfZ?yW4f-J
zvbY(#GzFDGoYk#dir!4!2tD(&bU#tu;yK;A7TC?!{k0Pg=jh&{EoH8*z6Czz=^mgc
zX})e71^5eeyQ<MysN>U-jq|!BIw4x5^Y;eI1>Iyhc*VL6d~}xR8ZQE~RJVH#+%D7Y
zL79ndak(yiBV;Oc(QiP%QpXyA7gf6Jv?r|AF%=k7jm|Lu8W(jAwB@PQ4GTan=|;_P
ztxoq6Rf5**-u)E{mvtX&fO18rTnm&2-2mMjjk<SSVfU&oiU++WUH>BRnsvP=p>Au@
zy|M|Ow(0_Qg4wQXS^$Hcx`!#EbW`Vd2)r(xmF}Zkx;=C*qFZ<G0hs8~1=FgqSLZ0h
z(E4<X=mcWF?n^Nw@95l;;P0refUf+zy1_e87}FWkATp_|c7=s|x(bT%PT6$24e)zf
z$0YMJy0i9>nbk!Np*5$o^965SSNJi=ecf7mXxr;uX-XXQI}~U+>iZ}-aZvx$t57(k
zU)+T;IqAPW3oo4YE%hLW^|AxNJfe@MJ^N98@qUQ7=zraak-6$^ZeGB4(>o~Pjl2G%
zAA#+m&!tk9WBQpT!1mNj80b8%kG&3ZLjMw75MKHaO89!~4_!j1k3RlKp!n)Tmteep
z`Wz9|{q<Gv!9;+5XBSAI-i<~Uqz|P$b+BHW2zw{>3vKtI5u*S6DlDDSU%dmxP<@vf
zpkeytKS09uvTxBDp|AXJ)1m)Kg;tdQv3N{rv_6<BhGO*R9z<uXeozSPIK7OD#N+kN
zpMxamGgiUT)B3|df+Xtgo`*9@`p@XrPS$VSOdI1A{g2+zPt{+12fb(X3|auD=~ouP
ze7gSQMDQ~7z8k<htG8r<m#L4x1HCMLn-N}|)Bl!(R<>TT6O)jmAJ_v+`T9vANP)ip
z7w`)8d)PoZuWw{Rp-68$jL~1vPrK3jvsk}09iuPNulX7>rF!>+7)6<WMFM2X^_MAi
zQlU@32a!tsV{{y(N}r&|(5m$po6)M#e@J!R7xgm~U8~g}UkCL|`b|_*Sf|f_6b9?{
zxwK!stS_Xz(G~r7&qAR=?~HOS9K+Pt=K<!b{$K-0lYXlX2AlOxM<COp-w*_tRz0Hx
z=CA2vJ0a4h&;JU%>-u&h=HiBa*#(HS>wQ%a>Ck`M3|^<ch_V|u^{r=NuuI?Q1HB&o
z1T9K?^_q1M>C>B*foJR2zesW6+xm^mAv2)&q73AqKJ^AbhxEB7$PDWPiZB;<^qd;B
zM)dW+qBW}DX9vl<`lnU{bWC4hg8I0A@1NjJ=)dj31WoFjV}No`|II^?oYKEdj!x@u
zP^fuE|0Bh&W^MZDB!JH8Kk0xM^ZGQ}<=oegQQFzw5I74M2Sem3bUGSp*FfZ;VPhaV
z4;d042bz=N9v(4^oedw_;KgBsk0Uyd7(&i~95vkd0+w71HcAP&8dg%c*3B^N02Ft_
zD-@yhFc`jl9nE8gZG$lAX?WiWmW~@XQkdX`;S`mtco}By0^8egU=%-$kKq8F?C~|c
zKM6^H!;}})0}SRjArfeKT<RCL;(@1ZyXmDIV%W4DqNfa5v5*NhY<&~ngc<f$qchy_
z8HN2L41=f98EN>40%B2yNJ=9`8?0305MwwI2b5UD3K>M=3}qoeIc><>1WWjGKP3y3
z40A#7Fxil`93m-(>N#Mh8qBs__;$wN^fj7khH4+kq#NEN{Y-=CI25xC`+_hh=L`$z
z+*z(+6Kx~&48HkrE#I(eDR>2j?R4oD8m@hX)_H>mO<R$nnxd~441?#uD>f`!1icbN
z3>zY)hU>dP$_&1)bhfPA@Yn-jRv4OJfM})R^&r@-GCbQ4Qf-hn!fuV>6fNm58eT|8
ztJbjjZAe}+7#BmY&hQw$P3sL0Q@rZ3VHrhcuNXLY&}uOF(rwsiNT5X5Rl^@FNH!S+
z-vg}Kkg<o(mbDoE3WH3mVaw|v*9>7lz_&KT)g+MXh6A)QxnWpJH687S)9*sR!>~aJ
z(rFMm0raNf#SbxSU53IvAh!&8`=HQmXr)APkKqEP9(xU+Q>|Q|p`YGZ{f1>Pq4T!E
zwT@n@1BSX?Xbu{rF>q?gz^3rRup!_>7`$T`7l4cyI_a4*YWU@S4EwI(_Bu$88HOla
zJ8t-w-Wd~ye##Y18kT$pyY~#s_0XF#s3|NsZ5XAB%o#(C3A|aulLDa386Kh3p>5tU
zL%Xc|h7(jAVQ)Ox0knh0<&{u8Wb}&!aWcM3xol_ST`eRJ8z-4)9We&9!;7QFOO%*#
zF|y8Lx?PPXdX~8vUFhhPyRrN=_~c<697XGx(UaCyp2ok2fO6dU4wZ?Wuo>qUgXv{l
zOW6}|<M00ijE^ynBA33#Nm}Ij8H4HZ<8SQz6OsYOcU{p6G=|Z`FUT11H#&ojSfb)3
zWvrwPc8GB&-HoS=qe6&;8lx$38fNs}36XH4(=>dFFiO9J`ADPfjYKe`jK6jRG}>60
z0xx2WpV8ta*62M2jX2|3Dn>qSWSoFTqEYfWW;V%KMB%+;qlI#6DaM!If}^R%h^Juw
zjB(Bvtu*6-3uvVq#ZSQCSz{~}H)I-Pe}!vV#?70dcg~n<+YE!*#-q(Jk!u{Chen=p
z_AE5=jXzv~`2u5%6}&>@nj|QmH%3#~so3cK5kyLiZ)XCu)c6HuBFl^iT+u2w{zA1}
z6~@`;K`M<2>)>{kv6cmYtBqfNj*-<Et9+n-(Wrdh27|T6ybVyiWDKJFpw9UA3{2D;
zf4d3&%f_S{Xk0O_DuI53@k^3yGzP7LYgdhY%0xC9H&Cf<v+>Y0JZv#upt)!@dVT;C
z*NofG0<6urQv%*~<1eqE^M)~C5}57AwO`Tw*J1pb1(};h_>23<So=3fkMY?MVD}oY
z($W1s<KKnQ?>GKKJJs7pKE)vijA@i#95kMK2CX5Z;u`dZjV=qIaL4#1h2Tbvt53k~
zQR9tPfQ=hBWI|-Z_*yBzCXMd6Z}Hz;jr-O@f6CZFLz_0f^%H)X8Ka{Cb1`fD=ou)^
z89m>H;=ED#BOJYNWKn3z-lV<(;%J(A3<eLH{wjgOA=9==h&Y*U{Qw1L)BpCv(qWUp
z9Tq%IH-sR^O-tJ#a>C^OJw$9?rlqH0(A)HL4$S+Qf|di+-;__O*8o#R7xV*7)BAuO
zWIAydykOI6JtR+>*mG!wn0!+Jddl>+8J(e~_bIa&W*Vcnf4FJ(CR!0D5mnqqnl|7p
z!Qv>>xgK;zoAeayOR<@PN1>l;il0F<&6IK-gGo2_{sOcN(~pDDIBW8zAV;Rj^bkmv
z>EcVkK4+3Y0nltyb`M68V`?seWUlGY-yxD``l1Nx`KA;mL<&rAQFyP=l)fC2=S?e`
zV7|!I{a^aRWJ{!dMzN`~0CQ4e@}t#9sp<4Sz?7L@rTXe}Q!lMLDolxS;8mJ_cY=PE
zDIfy8YSRn<!fuVJdj+sBn%<{;Zmr2Sjm}G^Aj+ZCnZ6@O>rG$ILFBTj01w^8S4<<t
z;5C?}HcE0entmd0u9^(Xz-%%((DtU;^uKwuT1=PkK(y5qOdI9vrsoa7zF}HikIr_}
zrJWGzFwOd54m(Xxxx%%ZrrO6rx=a)2(0R*r{U3PWZR-9Dojs<{95FM!rZu#s?lTo-
z*wEW=TFe5uZQ6Say#po%l}!$s-lIyzA=CO;7#uc9#$oA>$(fRuBPRcq80e@;`ZTW2
zyQU6%bdH%aTcAE}x)lw*2@{|8_md{k&*0rNS=PggDboPe2u+*p=mTyuCeaf5Z?3bZ
zF8Y+joavnhz??S;Y1eSyw2Bt4_U7?d;jn}G#Lp0MH0S&dk%Q&{N;(}fds4!~$$Z2D
z5ohxn5j;F>-tLP|7xU8>F$h=lwRU*nX3qEodhX_5!=UG3j;BZeG4q2z)7dglvpf_A
zkDEVu3FL%%H*MLx%!faPhPPSq7CL>*ySkw0Yqn4t&d;1S4W7UGlh5E&fO*=C!33H=
z&Om37+2c8oU~>`u_9xBJRFV>6-h=S%;#1}?DbW{d&N=~<F!Soa;Ds&R{N2lNIKtdO
zRo9W`4||~zWj0^Mn4--)&%kbs`4KxzcdU5<EqLS1zfe#p-rT$kA_?Z58_{{%>_)-%
zM6*LUB$Lc%o`H#E^Jo~LQ_PM<FrRAHQL^fcIf1Hz(#!%{0;Su`v9x{7FfXGZ*jcmY
zIe=!GkGueqWe)E^=Q(o@?Gv)iTLz(@V-7DtE7$xuE!pzSdCx&4-#kmls0++m3T_sf
zU!*BHZ+=k&g(CAf9YwfcuAl{Pv3VW68%xZ$XQ5tdw%Kg~Ei<#1VNB)bKMiPAn7czE
zT4_#;23nOlicaEJn-z4{s>a;<FU(&uucp}BW%HgtVd9GUb&4K0m`iA#&}jbnLm0ej
z&Ito%llj;<3^tpu?*dAT`K@lWTFp!M!ooH4FE-jJx0#<Az$9Kb=M6&UhWP?LOxn!`
zI+xgCZlZdkPP6|JNZvH3QNF&*e1ZZ4x6G@z1FhS<gl4wK9K8l!^qLp=qt#~~*baq$
zvn2-Pwt3$?BnQmP=>LEZnnh7S88WZRqFC~<d7g3`cg&TWVQIvi@;GEh&8>52-8DDT
zV`t3#T^;nt&6!1LO_+T`(V8^#uLJv@c_+o7r_BF84c@fbZXRGW=2(hc&YBY*gM~SB
zJAHp=-h8eJ3ir)NXisWyxin1m7!H;-RG;l=d5t34PL{Aof#z&^axKVVOT#v39I;%!
z1m01LAq2$5vVyj3?iT(qL_919DAst)A{qqmgvEm{c`wVibPn0uGO!IZ>SO7Qfuye`
za~eE9i)Si$ffmUgT7L#v{O+R}Y?0C9<D}(Z3ZR5o5;P#EEH$fu9ct0g{vynBOADBA
zOBoeUM_3-Ddo$AVGQ|#}EXD6YB-*0qLL|nLU5Hk!<(wT*;w*j&NXA<{6c~1brHh`O
zr!50(F;BKc%h_J&Cs}UMvpd-mZ~@pUmen`VO0_Uo0qu;%hYHZsEdRtqG2JpvyQ2)t
zL+f#sowf94!cwN?IeLp`S)wQ;b<SdMfk?KcpH^-;mVAnm=UT4OIxx?&fnJ#Tma%2%
zEU;Myx}Z^LY3>6#Z~5IHq{!kU0l8q|(Zi(J@)kYPN-PW?be3A=6>zQ0BI!qGxy9!>
z46VZQbP2F4Egh7;tg`(5-=^Q<M8TvQi;QZPE?QjZcBr+iu14#UrK%mI&SLw!9p2Pi
z(j&mUZ25REOkA<NLW`aT%k8rmTBAiwA?2&^5F$;MC$ECnY`INg;}%PD8`N7ZkJrJO
zYnE{nI@>H^|HAEd%QUSDJ1jRSE6`~P`v7`3EeZ-ncUhjMXW%W1$yN{jZcD~Pn2a9F
zUiv9|EmefwXDO#0U%%yBDlNWk3ET^f0n1Nofi`HFqI%XL%ehFP4O?6&qJ78GM^$Sh
zmVO1C8MSoffZVmPs7`0hg72Z?{;_;Q=e;K^$&{m;v@Cqy2E}`pU9<?FvN(8vOj~}V
zs?Qlq@E{atEfLosI%heFi*@n5<&DGO-M3t#wU52^`eOLxU|s(({B^X(WI*Jgb?0fg
zcF1~!o`FtQRv+v-TfIL5*kNni4S*f7u1bKRqt>xkY5nP9ec=q4uGX$+!F03QQJl=(
zDt{lAJgkpIz{D}@Z<Gl4v|g)&-Q(7qC($}#Wj+H-URE1LpS-QRDF)_at(-=uuXTA5
zB>k+%sp8h(dipas6JY&-b_;>lNve$xvaVV{-}VW%eorselhz|Iz+i~=`7X3hSzXw0
zCe-@mS#*Y3b0dKkZv8p{FcH=@r4Wg>t{H@DG1iynF{QCqNBXrBtPj(je%ksq9cxUq
z*3&aE#kz&w?5Wo8DQ0lSx`|@JY1Z|$(X^#oW%NkPu>L?_i^;Oi4Pa`{S>L3%Ubc1V
zV=$OwHPap-*V?rWygX|+EdcYaODW@5U@bWe>_V#(JzvjTd*yJu$XXzQzZa|;Ds?Zm
zE~TtbiS^MhAyR4`ZUe8(x{w0B<u>bk|AJXz9qt8orFB6*^sB79=-pavT})p{sj(iR
zT=zw5{Wu)1wTh&$d&#<f7^APV+9(`ZZ`D5xFD_fP-@wr;R%iOmZi96{#n2k9yC|r0
z)p~^vrZ-uyP^zxkx^)v2TCBF!SHNtwW{{`Xte*K$Y_sm&0p@jU(GMUutXJr|YPb4C
zf_Kwe9uD`rtj_dqyk$*)0ifO1|7k#atmgvYcCS@QyQ4nqvaRUsw`P-1x2@0j!O;P0
z@pEVmT21t=s3EJ-Hj7~oTQ_N-amTu?626UCC+XDCsI{IB*50-LAcp9e^*7oJk6Yb{
zH(?E@hwh|xIR(G&S-++X=ajX?2a?m)iWu-_thTQKJ!{P$1<IT?L=WhB>zh=L<zQFR
z0ZB)@SFY0f^PpYFJHU3fJJ5xJ9=3ak3(zBWheM%p)b7}Oz;?0QLiu}FJJ$)AceBf;
zg^j!25~|qpunT`2<d|LeC^|juHc+bXxZO8T!tM#XajGuyvO7$NCA{rkrq!g6T}M46
zeeK?Hq@;$Q-EY5u>2Ft>fZhPRm0Ljq?TWf#@T6ThB}zl=uDJsAl-(y(rxa>e@*_mT
z>^`7~OSoO-V;E?J-78z55NT(oBfL>|A5i!v+OGda3^2xSBULrV+FhbLlsLPgH_;hy
z_r~kA|4Xoo^#aUkyHm6bO|)D27G#p_<|r+YY=^5FH;~<TTzHsj_tcM=nKO13RI-w0
zH$zc^bh|GcAd+EM91Fd(cKC<_UPpF06A;O=TO5YYb9O&cZE?0;Ed|tb?ACn+y<9ui
zBAB)1*;)J`lW+Hbj;=c{%j%0eG8?95WmcADS=la4vof_TGuz6$_ul)p%<M%#0a*eH
zh$wp~C@46XB1?uKq96*$-U13JARxc*`Tcc1=iIaIeV^x!bIyI<@SAY>f|H$22Dwf;
z3NT-E68eFd=QQdLkniLshnfPX<Uw?_(CNEV;4E@_WfLr2a^hV8R_xSFdGHdamIml9
zbz=U4wsNNq3L;lJi7r6rRVTMK@UY5BNGrfKhf@w+OTO;3@CTTvcJeTTTI0lUg~Sb~
z4_*SX)+w6S#+y!=l*y`hdX4rl4Nf|$GrH}hrCe&G)3%pEY;s~eg862rr&GY$;`HpV
zU}<&App;pg(?hzu*X~s1g<<Y;s;A|s+i6oWZR>iRYJY)5pVKG%(Ae*kL6sl_PD~GI
z8+1yffc%hC$jbo3P7l|EbHwRYx+*>Dw00iUj5)OiUwsD^a<y8B?`GU*Le7Oz;0g1t
zjB@${@LtCAw0(7F9N&#0@n9_92h59c=^m_mGcLA((}(fG)3C6g5lH(-e}?l5un@p-
z8$sJa#?eLK3}U?cJX8lWey8a*lyO{#w!@5oUMLG=eCyZ)7|z(832Fr6M|xNy8B;%j
zHHN|e9at>m<P>zrF{+=0+s7EP8aQ*DaX<)=$k0)-?McSENqCXW_=-M3k;3?4AFx!$
zRU72e7-_FU%Nd4z83fKVHavm0bjD+!0Aw(Z4p4?9o3Z%+hi`_2N**sTI>X^i9wR&r
zy7L*cDJfsT_>%T`ml&=TK`&-Jbp+0oFp??Db(yjHZD^@x%>Em4HH=j>t>0iw(3z!{
zag1(d-DCvQb>Mo&-alctfssV<t=o)wKD3xNGDhiZWlfAzpTc}ILwpmUh2ckGm{vv}
z?Hbw`zn_DAJLC30FyFx#a0AxKNLdYo-HgIgU_Fdc12}sbli$GZ9YzranEDudywL3d
z#@Tu3#9c<hR@lAAXv~G`K?V;8O~<Su#w$8dhZ*`M5FB9$C<;5uSTG2sV~l(k$WJh~
z&<7YN8IeL5e8h;RZKN~v;8n=&X0E3iA{XX1N}ISc=hBns#{8Hvg?pK9Qy{uCvo6A*
z2Xp3U0G`Y?Qnrs7vJP?%FXq{4K)so}Lg26u^WC=~@5|gMg~NW#Ir{<jGc!Jg7yiuN
z&%qMFT=Er^1~Qdw$Q@v!&;}11)6oRif|#x;up7*LM*<MS+(`+}L(F#;qAiqpVh=cv
zFt5`ybCh}EI?RVVm|9ABL@{lHFcHn%H6Ma8%;%QD(|G3Hjj)u!d?^I-$C$NRXiH+2
z-b337rZWX<Pcpxw`tnoEIh)}2Y38f6VNGQkDUWuRxtQwk&oQ~*Ld$vPdo<l-GV9Nv
zEsMD>0s`4g$Gi&g<T9(MhUp@+mO>?Y%#8ogwL+%xD0CMw*U@}_iRriu&SK`1mGGj3
zIW!l<Qs%chI8(;_*#K>qncD{7eL3@sqp(!L{N@9&TwyZ5g|bTKqiyh_iW#g#+co9}
ze|T}7>EsB4wrVEhNq`#WM*39F4W>~E!CK}SH?ZDfmQhuI9dl$l<m;J3v}80eXNJS>
zZDuA#@EVySI-E5zFH(lGnfc{9IMc#Zr@}-lb6zV1+L(>uAht7EJ^)?J$0!`%&8*+%
zfQcUF6Wh@3KBk)X%l*voE)WNpD;|J&m&vAm;60}39e_dR9lAI<#615dScaJ~qwwNB
zbMKEJK45k)gun<hZWX{N)9o*SG3F+!o_olgQUe=jKJggrPB8y?1Te|`A(j@?N6c=@
zmrgO6RK?@W@)V#KyIEe?DbI3YMbQN1%33rRZEh@2Iy>xPby9W7Ue@%d(B{tCHV@i7
zSTpGN@nrS$0rs&<*MZZEB?*KUZ`Mo;yzpT)tp%qqt8XUy;>Y^Ue-_@q{VeY?_~y?#
zGY=qu_4{oo4P^aS2c82gUN$5SvUYz65X5qehniqk9u-N3u%4hq$sv|*AqF9om74^+
zhgnLB?uD_ksWkcst1T2GbChMJ6ni+UjNaP_Rx(}Uj%5A$6FT9DVhL?f8qIo-&ayGA
z7f+)xmNkdI92Ljfr-g}l)>Ci6L;_1e)7CN8-#_DrJ<b|r!C)dQj!rO1tf4v(Pq3Ql
zZox^GC*6@uX3cmXs#92lw6dRKSw4Z5)2x4K0ZC<9=!})-U={C!nsclgT3ybwrfmmE
zXI-J|g&C}120$ijj52OntUcstHmmt@=+0r8=A)w*SY<z;Pr0lI`QW_BddwOA=CN|<
zfSb><(BZj&_3|vR6tW(pd!|LKx9>sx63a$)O~ow7LP~O%u)3$vSjtMG>Yp;!Nm>Xl
zvqH9lwVb6q4N$?_QVHS}RxJ;9D_LteP<oZM+Z6&;tQGhvXI*0rZ9&(rv#fORs%E`Q
zRZcZ5{zmlv25Sf1x2|PvrRU-%>-kU7c8lfXcn8|*SZNg9uV?Y>u++f%c^`agV*O$Q
zPctj~bFj3qdgvh2%9=j`mNwSkVKC9oT9gT52kX~|P}<3Arm$QW>%>!N>t@Bdg0qKJ
z76xK3tA!r!JFFEJ^s|q(f-W)iV_+$nIKZl-49i`X-^cLc9_yk9SO-~|f5Pt}mV$Dj
z!>nIVqxbh&ya2fNfE7!doe|a_E%0!Z72X4EjO9Yf(}%2Q={z&enx})M305rquiPZd
z<16TV#Jar%V2Tw_B|Xk;{tr|kzMH)v0Pef6)%2sgvYmf}gd6*nnULSZW~_qlz3hrs
z^unEek?z5GumdRJ;K_ETNo*fGM*?v#_PP>?d$YHvL%@e!69h}X?3vxr;>UhvJ&60+
ze{4Z_{n<+>9UZ{->7!syAe*-yeLBEimJFVQY{5rR8pK|+7V^RDPbrQV!VWlrkvYUJ
z_!46g%09}6hlkl&hrtrY=I?`vBkXr6YkHJDn}Rvv>`<x{jbQ(s2)Rgh27OE`iv93+
zVA1T)X}XGG+aCjP#ImcXFe#2Ly$fye?9`{B<~VyD)m0_3KU)Q268nKSTuWxVK8bFp
zuy=e6e^0SL83j1co)Zg}Ot$znXvtz%P-Z2YeIOSghkby~4j0(-mH_0km%j&{7ul~;
z&^V9%72PGxcd*Z0fzm>DH@>|#tB5^Z3KuW2M^8Y$n4La_wi5QD4vbeRTm3Vz%j}{N
zaF(+R=yE{?yQmoEudtt^>milwZ3*!HD*HNRVyoEIl+3uswz#3A*V!%>v{kdKH^M><
zd&&(0H`opfWxi|KyO+V>O?KM?XuHL}MwOy<>}!9*L_OQ9816T)J*bNNHhaS$utxUt
zv|VUo?~R7iX7*+ZI=8SR>4$A)v%Z3O8~c}&u++|8LR+T}c8e>pPIhY~<ht0OdxNu^
z{i)+Opm*3JN}l$y6XU?z&t6>%Fu-0A2iNYh2PxWok3ISb*dRNc@?k^lsA=faFgxON
z{IK`g6IVcdz+UJCmJxQ+Z1^<Fo<n7;W9%BL(tpTSe+q$db|PIXn_$=Uf;h?k(wFw1
zkJvu$08{MFZD@4nl>Z2WuAJW}!{Ns9R>H&{&J0?`_i_$CgEn{0T1r-Va8^@5+mmyO
zCb)eZ{Tg(_i?ichSn}o!QWC|7lS>&WUryB;$oX;pq!)cZ=lVSe_;UspQZgfeGj9xn
zft>M6U_HP|rLxz9oV9fJ58|w#mm`?7NeaOb&UdR}@DPVj=aNv)=iyL#n6sQ>Utt_y
zI*1(MI8l&3g0qHd+9EkUw17l$>N=n-mJ{(8Kpdxu{xl_?v;8!^f5$ne62OzlsTD#n
ziSuDMbSHC)t3gcRIOtZwDb8<)(Wf*{fj1tHGn~CtJam?G`vDA|=kz}TOX-}nxe(9b
zyz?7OWO4%Nn2^QsSpzLO9QGS%yTI8-H<oibPf&y>kMqTCh%d?KtX&SJ1)S~l`xbIS
zs0^lv6GJ~&F~=>qXXW%)93P>UZ&n4ziT0RRI7fbgd?n|JMz~hRdF?)&xyC7^eB*Ua
zG-XYzIi(T6YB*jL;Jv}w@g0b_I5)TusN)#y@S>ixt_my-ocwFBcbgMMhm}T-8y!8G
zIQk6yAkCcG=h2rIPPl{S?jFvaCm_+wIaUmChx6qBuR(CGQSzmq1D$wQIf~hE?H*@j
zF|a|-$utbYFz5LL5Fg>3r@huFr;S$OG0vNdF(eN;e`TO;oO7CLv?e%TAA_TloZqIw
z{3A{`t=?0dpT44uw=*||o~zwl*7J~X;jY~VY%ljCT8`Yg=f45bgZmpj5T4vAiaPD%
zE~278FRp+Rl-^wC0POm33n?D%%e{3BgAmA_w*=q-ck@f&Jjl&`1Z6?o53!}670f+<
z3pzu%D~q4RLwbn&F`Xeoxok?89_IeK1!^L=BNUd8<X-p;Ac`x_hTUlHAT6;mT#qv7
zj^&=E4R0KGWj##9bN`S5ByitrLDx=j=NG}>liXF5B}(Q_%z?oaZuJ_NKgFGIgfpkP
zOApaCqEv4BB?zW*Gh3ka47Y7M44&t{|2TA~b05qD$l#7r1!N{S;WMbo;(q%c)MRrP
z{sdwU_m{n3xxg)phQVB}TO*WR<T5GkpT|vKjJAC4k^3MPb9EH_E#ZDnU+pU8`X7gD
zjxw%0l{H`H2FjtWoGYP8sDe9}st&Gj<DP)hN-n<~+N!x*sa~LlYomD44ekos^3`%j
zXQID1xvzIa=`HS$jqtFJ%c_8QJ@*58?HjmrC=b@cy+Wt5R_;pLPqlH|>4S~!4sJ>*
zU<Y^NXMj#_&`o&J#ZBe|baUG%Io`v4L|Oa+?qdQF?{Zts!0vHFBVlQf>q4QoA@1k{
zxIN6hPgnNubKACn^8weD3dcsc3uqO5$n~Qyv5a&5lHk(>_crBoC%F#IXVCVDyK@<M
zrno&t(B{m0c_lpE&3m2_oG!e2`c8@~?<5zx-FQJe0rv0~#(-rXFE1LH7jH)c<h*$z
zI!yZTemICWU*1q34Eph^sK94GZ^RG&`tx3Ez*q$E7ExJoFwfs{65S5rJ*0W+5bv#c
zXba_u4nyKF?=7mv4&yyTai$}@Wdg__<-PhFOoa0+Ytf4s-gbKQVtHnI^x}9w(W4j7
zE1{TM0<WeC;>UPD$^nk^&fkERMBZ{XKoYOA8Ol!avQ$)kcbexD1cy_3jlH0z@m{+H
z-Dh|&KZK>TyzFI=ILCAFpyoVJ;0fL7yl9HiXYo8vKs=jQ-U}>;H<LEe7kH1_A&|@a
z^(e$I^4|7<vOL}^bmK0cXLtjkfLED=?iTU}-lc!jDB>yTCd?&X^=6pA%v(fZiE>_K
z4b)WdMoTb2S9tY8SgPdxQ3gv_c}pm@SjAhyhly)Eema!a@(O6ByU82b3zl0vl@VI%
zc<mB!*7M%}5y~2PpADhyHgD)d$TjjxkcG$B{CVF~oVcC0-wtXA?*+Qf-O2leZb^6X
z(oR8XH}7BCZuIcJ&4+w1@8zEW?((*!;HSLDYo%v>kY}fx9Yeg;ls6dWon^xAeO|E(
zym-L-fVK-GytS91<sol11$xGLn?C|@Oz`q3kTJ>of?{@$cxS%FAWZRc=%nb*AKe2J
z9{f4SA@9l0rfk4I{;yU5FaEllkoV@#RDs2Zzug48zWg6<fzyxwaujs#=V#DI4gC2_
zsm3dS{~47$2J+{o!nFhZ_pU+ipo2d*3~GY;|Ajzl2)~aGNr(7T6xj{s@1e8*VSY6|
z@<;d&sF3(5Ka1)p!};Fy8JtMIC>?5|_&h0;M)QB8$ZQP1h7LKg{I{M2NZ_A&5vq^z
zzo+NoIKQ42_(Xo620D}YjvMs-#uI!gZPHHizoor+GGDKUU<%)drts7JZL~Q|<rmrk
z()b;3LGTQJVFbWg{-*Z;&hfc@=tMgIMKM@1_zNiTn90}efa)whUjfzGd?$(^<nSBT
zVwf-ROG@EWF8^~!4H_@<o4r8I<A1gTgP+fT^($yA;9sEvtU^As1E7e1f~KuY{6xAd
zSIm#5C~65`d>Z1V{Oc5eFXMYOfaNm(mD6A;=O6wU-dFG^RzdX@{?9nr&#L4vq@U>;
z|FNsEaGlRjb3m|~uc7Ln8a~GZ5;yqat!S*}KQ{-xxWzwm9&L4e&vtaQp1*k%pn;$M
zGURUaFTV}Y$PZINX*1uCPEIX+pSQu%%AdLotewBm56U|DZ&SvtlfOC~&UEpQHbZqc
ze`z9pO{a(dyB~Vd%fCz?E9~Q+dkl^J{KYls%m9BQO<Q;QKheB#kH35eScdqGv?m_s
z`#cA5pWi{7fCv0N3t(`BzhV!>NBPVJ7=&^Ds#hR4!N0N{a+CaG%3M9-|3?>Cr})*b
z^aTQE!Mu-v?iNH*39pM_yE7zQ1%VVNb`uoQinmA5AA+{Mf^7w8a~FuIwA({)ga+SJ
zu!16o`vhu=sd@>@Xr=WQWK#i$kHFFiIbXq=t5D`An6?pMzkpBWcK(9gPXQbO0uKq)
z1PbQZ;P3&#jXIb(C^$nww;;hM5l|W|XnYC85W!{<dU!|>+7I2Kf-4yShXwYT;0zNq
zn4sl|K=>uVQ9-m9<iZ89|KG3*Hm<;sL<;h}VIfKoN7=Y&L7F$5iE#+3G(ckoIX}SD
zIKcu6H^&Qp+yK_&g4xf(M52I0hqENX(rwUvLNLb%x=#wC=t!F^m_g~56v5gb(3w*L
z6Q%!73)Z{<EvbUxG03F}beq9>Mquwj+gU**<-gAfW>A^ld4c0y%AcnTwrenK8G;i{
z(3UCKwHkt1g1#20$rcoCMO%)*PBF?0f@yR*$`u&#<ITD#;C}?~^8||@K`vjAIS$SO
z!FCEV6beF;z*!{NM@1f&1a04frC9Lai}0dEu!}Z#rGl><G?kVKc2b4TWkJ+C;3*d@
zeG}#@1uH)SxGISL0Pa@_);$T9Yl4tx0Im!E_yL^Ng5qp|8o?Y&rQQ%Y>S3u?5J}mK
zn*!z(ytpO!Za#jrI)R@j+Uf;ER6)@oP|%crTi~d3z~M$g9n~B*2{LHiZ5Dj77V<5E
z74+4xRso-WpEkiNdIH-83LA(Wg0(Zi*(n%1i?$v?;~8MRf_N&8xg(hSCRq9eZ|s21
ze!*UMxOP{-q3y;!K`jMG1_k_`z=i}7qf~J+EO@K~y6+3-d=51ug2($HKPoU&B6&=(
zfC};-3f5DwVO(%U4ZkM@;fulYNU(?UQB#5q-$SXhFxv~jML13|4p(9KT3~L%&@Umk
zNBBV?IQI&#P!_{Oxa9(Xr*Q1-lhYoXwNLnYuxSI*HN}aL@DmQwcMbLn|9J-{{Dlji
z0Wm=M?-;rkC@iE0>VVLLjXnhlUt0z&SQs}QZ6U&4RNE3Jyh|s=Bf<w?gLqWv6Afp=
zg-hsQ5Fs3(`w~&YHagNq3-8oJb&PPR2+CrGBaYkXZ=6s;6^QY|bgJ!45a!TwbX<6d
zR^dcpJbiB>Nw|pidMAXQ5AfTa6m}kle2P%=B*ae%<3=HOT6hCpo0Tg3hw84=gw8??
z!WrSJD9D`^j<17Ux^Ss4bY=)|QzkZ3sBEAkOqTGKw;-4;tfKtG1!3V@bS780jc!U@
z6juHXVxBPRbr{SSE}seA1ww8X+KPlv(Ytv`_#(Zx#lq=nz)FNaQnI#GIJgi7%Y@ey
z5HA<*qN0=v;Ve0@E5az6b*>8E_>9suRl=7a!qaO)aTB_IT^K__ifSR7YH@A|SEmBh
z3MVKnd{ZcC2e>8NMkl^HVGkuN>V;KQi+Wplu>!gqg;&*RYZ4~Wn%XRM(A?W1{Fchc
zT7_#UDA_J7q?|;DFl#9tmpg^KDCpKJd_Y-{JHmPQAlN6oK^w?^;d75eVnE2IV9q^Z
zb_TQ!3d5fRHYBWM01OM~{0pD%3x#H24}{sYR~r$2NP)*OVc8q#=tH6DJ-9Y5{B{Yz
zgfNNXmy<#v-Lr5^3DZA?L1)qJTDZ7dr2QOTxQLvotix3_>WkjHiT<J<?h#c{lGsD^
z%~6=}6zvHF%RbRs+F5vste*gQi<;;V>?68$2Q0p#<LdzYMDNT&C-#fPl#}-tRaC;Y
z0MS)SCI&i0xpmNeKr~VS)`Oxn+8PIm))m9IU=f>YZ$m_Tn_%~lXfu@=g^IqdLVpj7
z6tBQwm`Gj%?1(5|k3Jn0)xQW6;iB2dYR`%g>7CIQDSCox=A%SOw9rP2dZ`d9M#QXu
z>R6GZk@j41qTi{0C0^wA0!$=`7y?Kf6Fv48JUuRo`T*`Hiaw(&-$|l9^unJIm3RO<
zDf*H&56L3GB6KE2G(k5=Pl@hsfWT={KNZ8Iig<L1Dos>NfvIz%{s0J^7rnX#oav(P
z{$Hk>CE`+sBwLh1zhRE(YbuktD4JG;vB(q6qLQn8Q7-MGi$u3*8+u9fs2NI&McpwF
zC==Du#gfaS`Cr3CxoA0UaVteHtpIjaWD-NXO0+2%BU3HPjf0jN(JQp7+z>stfohL#
zi85WmQzyDZby4*qm(Re{C`wC)e3NLL0w>L)#gw#d5qVJ#r&W|R4F=mp2WeZ^E?W8o
zSUN;omZEE&qD_U+(k05Jtyi~b><n0XMNM(=_m1d`4}tZGHc(uxU!>#HOgtcx&?<3H
z<f??=plHzy^l(V@_bezK7ERFSFYb%Z_rjS6B83EPBcfL}L))lm*Y_ZfiB2bh<)LWI
z1cT$E@N#%KA@ZPSeNr_40CYYQJyikDDG^_XHfQlhE6nc}OIA?rt&8}ho8Z|a{yYE%
z_lh}m`gIpCq@ACK_}hEX?J35Jk7r%{z7d>W;`dU)=`F6dLYuF+l(uDl;$;*H+b^ER
zfhB+O6OW@UKzxGU;z04j1z<TKe*H4QL2)F#?;+w}+tB7XBu=C~OsKfE1`<caX_MeN
zDqgn%oe3A0BmhK+#Rt(ADK^nl5-qM9hxr(>gUZxn#qIy1ElxaZ4cg+xew*P%g19FP
z*fFu}V+_}E@m7i&CyKc=gC~hMwn5;GSWdI_S%>&3dgIQC6F8ur7q96>f78XH@1Q0_
ztfd0vO!3?EVJS=OOoxYT@n5rm<%mC}qss+xFB>3Nd^Q+bE{b&&x5*QCOu_AZaT48r
zDiGhN)vQn)?+Noo;$}8jE{TuRPPJI<$fIJz67e_f@TOE;8-ypJO#D$lOk5T-1|d-{
zX8#Ogg}6En9$pc<Q|(cucuP5mSH(Iim8=p!Nl$LI_+2XUs1Xm+1a(8)co)Q5;%Ewo
z)QP=3AW$#<{33`AVjZREZi^2&sM@GeynZ??wTPdg^1@be85KCRi9hQFXcudS!P+4X
z3x#~A_;DJGE^!8}L*3$zLVzCeyPv>rulTnO!0w2@q7tM&@duw{5c<W@l$sn63vNTp
zT`_A5IPZzCmH`Zk$3iJxGbH}!U!cR{fm7hQFV3%mGY`aflh8IIo=qh(qvE${yvD?P
z>0?R{#pnA0#>F{QHZUP>r`+JA_zOxJJrZwy7d@O3k4S+zOBPGOvRk69gxfBXS5;_p
zmAp;UtDD4dlit5Q5(d3$dnGF_!>+sJji2C!hoqifE>FoXt6_Ja<X8htcu6+;g6J*j
zy$Yg_WYGm^^OXeBX~SRg9fgYnB=Ksn1WGC>lyyKNj)E5lB@Zb_9wdoSKy|R>7G<?V
zBz!kYmmZSLF#`>iID3Hgu;kcbI2<O~wFs<7B<H?>;896kB+Q3Px+r}ZAqk9tzmXCv
zE!0tx_xHnmv}A1&IAbK4hoL1_((xL^<0ZS?;ZuTSMk&OPNxmot%W=sUyC9b+`ACm3
zbexc+QXc%IWGW95$&yGquAi2yr0SAXiIwKEG|4z!xIH70YzKB$(xQODbCM@1b9P?R
zPis`V#7hCC8IqI&$Yn~Nr1>IC@)j4I*^;j*K9(cNngh-Yl8c|hUao{+3-cEplC-0s
z=1IPzda8VhonFoY$*+{=EtEv%z?mY+gbTnWi90R(#gcLgNtH<0so*S?e69s&nIwqr
z`CpdQr-7whvY`+rDkP==*u5eNq*GO;WFg%dyDIT*f<TpI4Q;TmNgSTlV7)GR{uUam
zCBOIstCiR(#&T1#{QqHY$!`?Rsgt-|0I^=Ol^)Ut$#ebSye*0P0K?rVQ7;FvNwS*u
zC(V*Ex--@yk^F|?YLoo^7<$$&38dt9hh!)gZT*sC7XSt%3mhk5_pW3wg;VZHOgX>?
zCA;Vf*^uPlIPeThR^35=?@Rv4gSH0}$JYQO5?`7o$0RXYv^|srZiC%%$?0?uCnSfr
zfjB9VQrPH`WD{M_oRS2Vg1B31qqB~S^w|~A;wlw9asb^c<<SKmcWJ|NP(7r@4Zu95
zug?XxPdZLFJG`VX*26V#soPRuKGGZXu=q-y=n(8DT}1(Le`ycZ^#(|NBf%0Vwb1v!
z4@hfvW1J64-%f#{AnB=d&=M?dTMi3{q@gji{|uEn(-VAHdYK9o!lZ|l@cW4LITm=r
zrOp%-jgW4n@2EscXV6A0T53Lkv5b+jub?enT1nscOpt~&qV1UUK1C-^OPj-CDOI}R
z0OZo7`{%-oGtx0yDbGsXro-)X()Tg1I%Z`^?UXCXlzu@muq^56ry-avU2zNMbEE@C
zICDWN6+w5dbjSBFcv1QSRR-lrkJE*eeChYJmoJb;)WL3{G=XX-E=ko-L!emt!&Bfa
zkyc#>Rw{k=eRxqOjf((hg|w0K2aYS!$7ngMl*XR`iff=>L0grykk;L6(vc>3aa|fn
z2ghn@>pBS5NdKiR&<&~41^(7b<0*1+QyLHha7)@uImtR{9BoDFrMv3kVS_Zk1ah~f
zi#`Tul)grXl_u%4R8!OJkRE;$Xp6Kt9+q0At7)&;CY{v+`F3d+C4@VqlaJt2r&P26
zy1S%tOTf}C4WhOlDf=0?)+_y$rj0w&pDqFGld@?`-Y<Qn6~qDQbEg3AO5dia{yk|;
zCbSGnIh5=jk~(g7!P2mFjvFNIOYioA=Ye#89vVlaZB(K*DlMZx(U{be{uu0`^lKip
zjZ2-VZe~Kddmh}Ll>SS_k&mR|bWE6%c3y&q&a$=V(dHrxp}5T+S>g9++bip(jfK1H
z6op+qWFI*w%I7J2o2upa$^7V>UtY58tB~-PB~jqiM`oyld0*LzKxp%mDe0Ru`(=eD
zwE4@pa{vNlMp|S7Wsfa_(!;Vd^fQIYKBTJRBeLhI<m#yGB$Y#k%M<}1M#w@pVh|!_
zGAq4*QL-1N!F;r=p%z$-EQ?OKv9hmdw-YCuMz4Rotb&q)2{I1V0v(ej{sDpGvJG@%
zOO(0&4VENXTr%2D$Z}~<ds6n<i@=g)1)1PXk)=<;{3+RQ@fgw5vQNFxmMY8ooFd_A
zG7c@jXJlgq0B2>aUdW%5ef2jCo|pN)3oKpMcL!=RWG(N)r%c%tU8c{H_0x7TTh>K0
zc#f=d9J(*a&MLu~EBkgWh!<t$RDhKy`-Ac&`Lg#rp|e1?n+KLc*~bT`;r%O;eL%sp
zV%d%f=q`~B(c@JrGrR-4WwQ1e5WFn&{Q?r@vOOEniwfC^7eKrs`%njBrL2Z#rmHd~
z?TM>oos`tOCTpfJ=5<*r#UpOW-gp~rwK6RQB5um&KMM=DWP6opbJWSM1OwK~ZZ^Z=
z2H7v~!;9Opr5dm{%3h>0&?ead$~`s9ejEj{MYf&-;;piGeIVB+n@>l9cG($<xOB+M
z>CDq9v$#M@mu%-Quyo6e3*dH-td}+jy|UGxqwS7t`X+!rhpdRAu>G>%RzQA0_8~=o
z@5)waf!&kcmjD}-ouR1Ykn9A#GQ+Z31={Y*n&}421KB@c0*uHqz6a;1j74{4#$?yZ
zVfUeo^9#VZ>>nzUoRFQLgcp;t$xdi_Br{Wy@083DcO8w+^6fNUu5#y-kZ_aljDngy
za)TM&_K-VMEsv+17Y<AN<Uh=SppX1lCjejhY9Dy-Cue>Smi=<XuJBgKedoiO0Qm_z
z#s$is*aYl=e60rHp!^2ikqeT4P20g>Ip6Uf&=7gkmtZ|4|9B7}RBonR!C`siFX(od
z{Kd1-eMFv3Tl%AN<^&9e%YUXIVTAnCnNS)jub>oelzftAwrF`MEqpQZInx1R<(nUe
zT%3G+9=a4SKSqI*1UdUJV2Se7FDMe8Brl{;_6hkmn)OoTtLH=8Dfukg6`q!FrC?vG
z{Oep`X>$9oP<lpwc`k@&<-X6u(Q|U;A`s8ZpAG~uU2YLUS%%#B8B}M=-z|a8EcsI(
z0LzwJ{{+a9AEP7f1-aEq9~8-zPf+^tqWo(W?B>bWmqAUwe2UiO0=ZiR+%J?z6r!z2
z&OQU;CHdi};Y_i7%@X{SCGywSLtCl*Es8vr$s=|HT$X#$Sd`1HG*4B?0~28Ps=Sm+
z+p6S^JP@zRd#+F>>bg8<CgiK-tQXN(BVVA0iJS62g3*gx@)h$ztdr-Q1=cNp$s1nu
z$Qyrw`CfU;I5_Xfb+nxI$v;iQAoR<bv;!NEze&Z4cjdEEAa_sB{u34k<(=gAki7Z|
z+J@y{&@|_`FQ2g=CLYK;qQE*Lue%QSN9D)K?=kt090)#?=TYUzxcsSH^l3uAoECyf
z`L79(b5_j$4{CNR)QPa`qS$x{a;}P!AQ0UYk)8m16d_{}*sDlVfyG_%BIN-*6t^kL
z=IK!A-UYf(kyH%dycCNmY~`)^qXVoyibP5U`6_Z~e)LoPK(VO(3JzV9^jC22z|jE3
z&3VursF==&mII0wN{$~?3|9gRQjF1y6Remy34suWfD#sm6d4rh3{~u);MHM;!-qcl
z5vKUa59kqv`$b?!6;9p|3|9oxJQ<-_%!1NL#c#C9i&8vB4^*_`aXRS6D02VAsKqLr
zzQS0<DL$rEEnd+@U(HBR<ZOneV+xlp*gdZJiZbSjic2#fo}{RvefkN-M~-h{;-um>
zO&`gMnk;}6#in~0np29|6#G7{I57txRdM$;+R_x!>)_}a#gcHCKdV^$Ewr6ed`*d^
z^NQ9_VJTfPln31z3d>=DOhv;U*v(SRpe<jvqU#%o=O{M$Lg0cTH<}{hxr!HpK)tA#
zy%I|E6r2AB$X9H*4N#zv(9yO~!J_NcMT&O%W6Vp6GyWhJE7npaZ;9e1sx>ZE3{%lX
znZkY!#LEg78t!t%ClubURGc^n?5bi~DzGX=-%TjHrr^z>a=q({os`C?R-F6@ovBeU
zsc7(q;u~-Dw^k8F)tomKUsG||Ek)4*=&n=zodROL!c2R$2E_|b80XuHcW86itk8_0
ztwr%%9~^B}B+iGjHbod^3fmRSo`c&Rin*(Sbt`HYQv9Vyq5cN)y^5DT;YGh9g3gu$
zig1eb+*MrKinbwzxERh1E4VKKyRRrS!I=k&s&@E0qKJJTZKH~o=YfqWK5&Nahl*_a
zi{NpEg0|fgifdUQPAY1ig=>!#u5l2UQe39WD~Gf4E&6|k-O4&TShy&Er+|X1GBE{2
zH|5|D_+i|YpEW_Zhw`H{5cE_^X+ri^{!4YIKFWQR@AOq}{|VxL%BxgauwSW4gn+-&
zuMq|Vl=-=^6sSBv>6!yd)<QUQQ28Sl;z17OtK~2etXxAWw-9CiQZyb?CftP5P^IcN
zu)|8uJMbw?=`;-8N0fynAVw&QonRtT8BejSD5YEh-Lc9g6ef#P?wAD-uRQt`+7gs0
zf5Ww7O3iFw$CVqe14~p6J`RB-rNiqFSUREH<bpn(RAzReF<JS89axI8k*Xd}DM!DC
zrPIpLFc4Ff@6lY8ru^Uqm^h={Ks)TS%ESbCn6BJT=j;sSi$9{jnaWW*zvU@se2<>x
zEALU1pg`Fl3oi<lJ7<Gfq+H;jgw`eH;%g8rR_>C*V2LvMV+fWiFH-4onKFZtR+p7`
z`_Wdeyyp&3p_~!{Tu~mP^{Z03WF^dBRsNC+-BrqCkpS0}e^FUujdBCcH#d~a=}=dz
zJeCRKP36awS-GWr?tO~C)G1%80;pHM@HCuiQ2s`-+1tvl{V?CGTy_nhMfp<*2BB3M
zM*?li5=w`+E6>tT*`bW5T7*vJ%QQe;%9j#=bt~U`44ikA$La1@pK{lq=x4w3O-fM=
zD9seYzN_?kjo!a|$`}@?gUV@2_%@{MFNeWl<w44&jwoNCP1C5dnQmH)Dcfl-d#L16
z>G8O-gx>TC<;8S}Pb#0I%DP9&bh@fKrQAyCLl@O)s&RHz`BI^(o9f?g41&Ar8#UTI
zR9E4lW0t3?mkur7s<R{T)JN4rubQuFhy%=DwSG6S0M*A`=u@C-Qzm>0QVAYMTd>N9
zKBp3*T1cV4!>VvP<%Fqb&=Pw@<+c|FV^m!N2*j%X$%B?S)jwx|#jAdxj81||mjZts
z$5c!EpzXNINe8DARe?`}HAxki1>y<SHah5@RLLj^m8{zK8dy?PvsQxTl<K`O^!~JJ
zpa<qtRhj~rPgC730Cq;Dp{Vg$RjwV_Io0BiVeq_aeHP58tGX!0k)isSYJM{vs#`KB
z%~I)J1)8l=z7B~TmDm&RUr>1x$W>jSbizf|G&)k}tA2?FR-kIT4}n6}4T^misVsBg
z(<PObX3JvL5lRS`sJ0J7yi^tRCPuwXwZj#ixUAYual~@f&|ZjFs2tv}!nZ4`!q-8q
zRK@Iu?yIV8TOnVi`cealYpUO=?B}{F(*g50RH@fMtW}vQOm<T>jUxB;sz$n&)}UHP
zQM%izVB&069jBdji>h-NZLKQiWngWpoRz@ZRULlN(xGy7P(Z$0wfZxF9@R8@^m<it
zs$uU}ZKja_fa)Aw3%IL_RG{si%1lK|gQ^{`Kz>M-eFVe@s&ER{ji@%g3NWg&oCX+I
zy-B;+3Dt8;!8xg#q7=Kc`Vswa;%@a@+tB8smKTzzd(?Yofx1_{>uczCSMO;8=AoWP
zv!<u|NGw?Psdvx^-2K&js`m*{zd&)HKy^+jSPrN+J%INI)kb=(gVa6KU@2IA?@f3g
zqJEh^czsA6dJmkT>Muy(u=>YmF?eC>S+NxVJfeQd6W$zE&tDC}aCOXLG)Aa@b%HaI
z>M&1$DD|fopgUT9BnoXY>icvgj#by{0OHgO>040o>Y*C6C8*>7g|cJnuBB)@uHNVa
zFA~-3C^(X&o;eeao=}%R4nrr^+fmBkn3b&l@HyyCQRh*V{*?L`x=4Cjy-EX#RP~yJ
zz|z!-^mLw4pPvV3&Z<kQft^#A=0Mwd^)LR=mabkF3okO%KZL=2ruyl05VO>h3W#T`
zFXcdWj(RR#8oQwWb2_kG^{h+K;<%_b{0?fKx`w)zua2R6s0HfzT406h<yqh<Qb+Cu
zc1hhH1cSxuR62E+sL$ttSgH>H9>g;B4a&h@R&P82x69QXcfeAi_N7Sp74<eMy{c5d
z83^o}`e#bFTvy*rf$D09`Z0RbYt_Skpx#uU`4Qlj`j1xl-Jt&ZU8uRO_Spr&M)k82
z5L?vGJ_Bv7>P9W>wyD=%hQUsCHXVYy)De`8=vK#m1D!o;xj$HX)n_SJeMkL0z1n?h
zCY`VQ)gMumZ9wgq{R+nGu6kW8)Z9}KzKEY<P(AZ`2o9^$dtm;)noTLY2kINY!tRLL
zV;$s2)uGE^a7^7ug~Sil9aQBpt}b7Mwh49cuOLpUO;kbrNPTWUEKRBJy@&ofYhFKt
zw%wZb10cF+zIM>M;HvpG7r;#uSP3uoXrg@4xK~s83ADLu4$-m5L(|m<c~4C`7tZX{
zI2h3FrSZ%I(Oa{U3-dmjOuAv=tEu6`H9yUt5s=%jY54`5{+hx_5Cb%Rp8yNg7?*+b
zfM)ArdjAe;gbhH0G>w$K3D#&R5f-9R9D_55G)Yf@B~<eX{e9J8&EPqh57T@T4ZBA)
zi)o*KR3oQbTj83Eh2V_Pge`^LNX<z%v_)x}=o=c*npv*^#Aqh3Lv^fX&w8ki(=0qs
z?_a#;nJ5S*XfDx2bxgB`!ivW=ztXawsM$($V3MX(25>?nDTeNonogQ1k~L%Fa3)3b
za~I5?(wwJaxYL@FpP?*O<CqQ;X_{9lxPL~oD+tb<)qGBYh;y1xXm@p9^JzX+LZxeh
zzJu-z&E6JJGd0$Dn9tJGz6LB?v!61nIhy+vFTSAhrN~FFrfCYgFKTLipfpe8g>CGt
ze2o{?Hx+2oDEwNeaheXSNb@YkST1R1(`U7cHFLRetwd8qxrI_q2Az`~Wtx&h=*(qJ
zYYYU-HLH8UTA}&w0CZo`6u*S7RcSVdf_P0cM)A|@8WRP2t2IZuAYY?7@c_gdn$l%3
zSgQ%x3Eej}R*E&=(#)lpU!6wn4ZHOkaRhqbpsCsl?6$_|X$UkrG%jgyu}SmJpAc-;
z9R31!TQnQy!9=U3nFIMY&1)1yZr7Zm<+nrQPqzp=HE)Q4b!kR-K%iT5j5gCfnjbd7
zM6c%HKajhlSr-jUeVRAcgQZ`y<6E!{XpT^r`L5<i$^+cfIP`yjI;bh5Qr;m=94)xR
z8h4uR?rZw!ME*ddrD)xVCh%#rjcTsaiDFDs&<Od5nu+b;9M?3^S}~!~(RI2>%?|p!
z>m!YTYI3GD5>oA~9b$pFTl?Q8^vq4$LMfF!+F*wO)V*3|JAk`(>@83|w2yg1o2Ryl
z1;Kq<;fHY8OB?<eSiH5$Lm>KSf2N<pSNq~>X!Fy4)du2z?Me#m`fI)DSr5?er?g3+
zR!b401KQ`T80Lf8suFZ5Nb5`K@L;WjMaQZT?SISAr$gFdIv0g%BgcUq*3L}@2-BLV
zy6cGc>ShQY)h?x@Pq;QH0VX1}E5CxlNbUU(;ct|7E(HmrwbMU`Ycbls8^B_<Rj;5e
zPWy<CWAWO+T4+homQkhIF>U()|JVJvwwr286SXS(kV2C76g_Mwv`c9!J*hR&nI~Br
zvk}guXwT7UKUG^z8@V*CFU6qGXuBJMoz>Qm+vl`fT;bt)?b+kdlCItG6m({2ljZ=+
z)Xt$VAY^GhzJoxvwiBT&$E+Of9Xc#s)UH_xo;+>kFhIWcSBkk8X=hPY<|Xa-r@>OJ
zUEdA)GVQie$Y0iO{s119Yd@o7Ri*YhHQKIf-=G=1N_&Vt$$d*JlY>~NeL%B&z4pmd
zP}ZO=se!<4?WYv@a5QQ+ucsG4yP7V6G;24m1J<J5OuNEX?MXU=w`r%MFr@9;Y0JUV
zp*2xSQKxogHdwl}i|JBDx3-?bialDvMYQ#5J*ar-j<%HQg8Q^hB6O)=yJ7$W1KPB^
zFn?G389jmb9NM{5-8HB^My0Vs+L9$uGpzl$46OIHoE8utXy?kIW<>iXZE?r7tLQ<T
z(C)qnmPzeuKKy;8-AN@0Q`+a#AmFU~glYnI>*nU7%|+*Q06y*2Ini?DuIqdUavr)T
z>80}2IljCKxKH=|%h2tmyEz@^y>&|{Z0w`E`z?rmx(s@t_UpC|fatGd=HmAa(DfaI
znm}C>1L6mCx6h;PpswQ(ECuOO3cwPqOMe}0A-dl;0EFrysZ#B*ZsT!y7^bVI)4~zm
ztBwLVbyPQ<YIq}bztO#mNL>*nvZHiy&qGa&Zb1UN7OU&0yk(qjA1!VPI$t^l9@8c4
z!N?rf)l<bvqAu7MT9S0lUBHrc!^<F^q8smqvQxTcG)<n?byAu(Rp%}ROPcP=O3D?S
z(P`**+*zGR2UySPss?~%=*+j#!%W@V&0x*awaf=+w(gVv$8U75$3eWHdx=inxw_jQ
zpc5B$6Lf6N(_N(d(fPV<o6uIE8*YV9g*xk22o&jFrse*UE`BB2ign>_^uM+xx)**x
z*GhGBSAeHX_uwOFtI)Mgz>6!o_Ywgrb<ZpU@v6>44f!fvrx^0rbh|0acU|}4c@V30
zkt&GS=zOR)^oDM34M44K&5z)`smnWuwmRJ?-N&idouVhVK{sKi_wTl@=_#mb)P0)-
zo+jOqCSc7v8yh?=x_@rL{Z?JJ8$4{&9pu7NyYBHm5Ib}qP>pn_?o=$~x^x@g1nAaP
zZ3nSOH%iClUR^g`@VKK}a1?EQy1}P__3Ki6;nRRF@+g2~P$#Gc9MU}_g2b?n<qz{C
zy0@kQjOzAZM=!>7nQs6*)NR^@K^WJ)OV8DWP9=ogl&<(6=yuj$SPhol`b{&@Lsxyq
z_aM6IKcr319{oZJitg3FPN!yfebk@8JoL{|me|vw|E3LU_UUg}A>pMzM2m&DUP!w`
zAAJzrwcD?sPr*rl{XD8@3eZb`2ME-s+=mwj^q<E7JE%`IKueH*KNTVe>(xE56rvxb
zZSx`hPMS+X^=ULqAJz};21}SeiVD4t=p8?J!QfH7KLhgNdf5oZIYR&ZQ;>+%bJ}4y
zO7BXkhG;!=6+pcH)iTH@=npnS?wCG#04&G#4OBaks2|UVc#=MqLKY|Va|=K`ssHUg
z$R+Emg8)+WO^IMRrT>S%7;#!Z%h3#NsrndC7);YUs3zfzzKeo0XZ3u_$ez<LUyfd!
z*Qe7J`E>op+YrdmOa6n2Onu8Vv}Ng=C|;YbPobSfj{XVCB3{t<%mc{Pe|Q=OFY1Tb
z=zX3(gwlBV`d8<JSfKw-;ecSFUYrj#MS2%1S-GUYO528FecgvJSfX!w933syH(duP
z(@#+>__BU(6FAHD%PE>up?{Mu>|W7tqf}p|KAI-ht9lkqDOGymAULn-uhG1GT|bZy
zE!BF)LO4^SUn8LX=M8-;-IS`;v#3n*roLenuv>Z=d0MCUr+1}ZznUhR27Mrf=Wgqx
zscN=S|GEoIH0i4-%Ga!ahKiP2^c9pOYt?gU7U<CbK_wWS`t0Y?)}=qY9>i|_TRgDz
z==Z%!f2h-|-$K9I9ewm$=x?9ig|Zp_`YYGa(E)wVdRV%vR~yl%d-_j|U>Vdeoq)iQ
zUb7U$Vf~+!=p4~+egT}L`qdq18`D2_1>Qf@KTGDv^@r(bI-$RI0pgST9aOmTNWX?M
zg^nq`HzhNj4QJ?Q-fak2fe~^se3uL!SHqn>z}yUPq(ji%AXyHghvDH-2zVMA`he{-
z%%|gxmm!@87H@-g8@%u_bkQ2+YnZkcn4jT=xzMuTaFh$5{0&tX(H3C%i=Ny-haqAS
z)EqF}ss_(NLnB21gAC=5!$h!QmI^+F7~ZTz+abftGz)|pu2Vh9VZ%lGUPhQ<)*_fV
zVwklUqjuC#LDgB2hWAdOEy}R>W5`7tRHQ7%u(lK|u?Af?hAYnSg+IKAH#ppB_nlxU
zrT6cc!TJ(-jvJcj*qdlr&j&Hd;7YT|3Bx)bI8Pe56eUP8v}^}<%3z_h<!QqX+TEoZ
z-cUhzn&G=Z2%Iroaz@)(!}RL_=L~x-@aeqa;Uic`Hx%W=rwoIe;}4+Oh8U_o&oQjL
z0_p|B#=XGu4Doz`e8c+`%PKIW$kEY4LvcGy6d5FM1G{91{r|qmP!R-{62najX_Xq9
z3t_3uz@kLfWy21Nb(9<CzYJv+h5&lTuNaIJGpIC(;%WW6YIv3ImsJ_$f57}T!>j9{
z`?|qMH6zuAvRBYnV@RfJ);A2<w9~CMFc+cirosPp4A3ouoNoNp85VzszSJ9@rfU!l
zh6dWe-8LkD4}TjCyZ(aRCc{#?GSF<;Pobd}L-8v5L!DNGtQn1MhCf^Z+6@!`!hENp
zma+<6h7~l2b{j6!>e6GVq1Ck4z@aOkcMNmxfY@jFvkb(3!@tkNnE}I+?I7MYa48*d
z&#>Vo_&aFGqB^c2!%7ywuwfg4`-bJZX?Xu07^a-inGr)kGL()Qq+`Iw42$U8`Oq+p
z%A>{&&)<X63B%hIy_z&^55hP-GK5}%?kPh93ywM)@9zh3w~;}4a2MmeV92=|k6OUu
zW_*cmTkbKI-oudWHQu<2Hh1G&zXLctjB}_q&eM4G2+)1T*B5}t%earWlitR3x}WJ|
ze3k+kzQ){iu=p7ZuEE59<8sQ=_!}p0pe?|-fa1M@#{HClJ76q{gU*9SKMJY@8Sm}{
zG1z!483G~3v1?F$$mn(ezd@+Ocs3L0VdMTI@HEW$pcR5gjAInSJ8Dec0Ksr$^&YTB
z7)vl;&5AUxb-~XRW&9`*x}%LP46wu))i!`wW5O6foN;w4IOC1S!{J(j@zG}JJZ8K|
z8TaGHK>7(2jmg(ROfovEXsJA5<bMODCyl;(fMnxW51=N+sNIXUQ$}+rev#A09Ll<;
z8Ush6JI%Pc4gEc5+)9i2d7~3moTVEdqnJa6QBI+yOk-~+1hR}<C^(sI^rpejF>YK1
z;sxV5I@aVGI~)`kxM(c=58mV%mwgT_-}o+VH4BW<w3{t7eiZ}OBBL@4@|TR8D2!8V
z+`I=^iSgl2kSjI5(+<uuqwN#;blF%E0#I)JITv;-jKvhoy<$8z16nGL-@SsitHzUm
z0#q5_E}-@Anz7Oijn|EDHi24gtf1nD8slG7-F3q#D}}*Y<M;`*-85dN7x$LYH3EZJ
zXIwuDV!iR)0bmWre<*Nr+xSf#K%?<bF+6NCuB|{@vvK-XIND--%@01c8eM;f&Nk!n
zziItzH~y3eo(`iYoeVmSEgop>G8+HCRvC@qkmxaboCZs;v5LMlf5&*>EU-SKPXH|S
z8%OBRSO$!Pm*MYS<LN1Qc+a?kp0YvXf_eCThK%mCiyb!pb_dGt8?AJw;(>8*2i1R$
z7`L(@F>35u2%a%x5!Em~G~S|{7URa1bP;F57)Ej1Nn^){F!9K^o@(!>jGHJD?rd_z
z!i(LeNvbw<F|l@{&DE4mVOuwoKkZ`OO#^9Q@i2|kr0Hq8PXC^?&-B0@UO2o=ysdE2
z+w}TEQ2k8fRBW~1w4SC*e^V9}FC8##+yb8tnkwFd(je1NC5XYMRT_X0ljnI551EEH
z1B9CXeGz>*Y<i7uPlcI+UH~{^avK8YQImEjSi((gCHfL&3Zi^}w8OM-FL+{17Ap0O
zHHAb2i!+T-okP4S_gC;7H}%nmH__z&Hq<1UIA5SG*_1&elVY0F4(ycaKMQoHncR9H
ze#VsiHk6$;ojwkhbEbD_zkS|xwFty?(~?23WSA-_0g!2OR8w76mg(;$Xv{Wwgg{M>
zDT*$(Trk;JfS6}GtbpBo)6Pp6y#mur%4S?LZTSPB*tGNpK#56Ak>N7a;u}zU+2rm9
zyXB_en;>3cDxu4sS4=nP7+7h_plRo->CIihs!VGfbX2@%iq>P;uA8_#P^(Snjqu`z
zY4v9Oc(tZgv=6*#VhEt^mI);gc=Ans6gH|ieL@+Q2Gf_H0=sS6^CJWrO<A9!hfSuY
z*&w!>vc84+Hq$h!7jHNH9SsjVOn=Z5*lAid=>Xbg(uu&+V_HXPh+b35DahY3slG;^
z`b-OGpV4pHsR41oWZ4hb?wWc$FeLX(mnl*@XgW*J)sSgkHJlkXt%?SA-_&6S%L9{=
z0!1Sx)r-JJO{r;6_Ry3~r{;0fj?Smv#nWw?PSfS2>G}PjJ~A1fg>O@)4}XP(vw7K@
z@M*W%6ukZ~+!ixY_1+${`biM?ntT3%fV=reIxTpZy^f(1Ugq2q81y#Bz6URS%#*E9
zw%`2I24Mc?*`Y8LV4h27@IbSeN^1_7e@_5*&^*HkECh2jSPq%X8qu>*^C-nC4x4`-
zgfC%csUrc6N6bl71bfun@gF3@&B2rfi7>BDgxyH<;brhC%AAk`pQ6p1zXXUeXHJI~
zvF1&25RWrYJq~U0=6A!;mSA=YN82%TzzU2^l6gC&x=)x*NicuXJZJ?-HZPGuXNvj9
zXDHiy%FOKnNHeFoK;n$~RxZ?>H9tosqUq*W;^A<H`Lk{~lWBhKc^J$x|3T$%*=AQZ
z{LL|cXn@iS=Fayao@-`kpzNaAb`oCXnZ1M2mTwjZ04p%>d=}z`=1B^Y7nyIh(Z^LT
znMFM?SZrRi047Sz))2^-nq`zOEi-#il;N^j{~L6dn^&ozt-^foM`*iZp0NztD$T=f
z;Jj+yMJJ#t^ETR<Uo%_j5L;v3PMhx==J9^?rPl0Dfw-IIFgu91%+KtjFLl<L@9jqq
z>&?nfAkknBqzKb(^8quoHJab2;chZdy9{Ep`4t+y7W2$nm}oV(cEP7M^9fIAYc~(m
z?9pMK{S`Pn&2HC#b(trNfpwc}E6|A^^YC1ByVor2$Ee*g@0bm7N1r(=5NN;oKpI#F
z%rl;XGk4AYG!+h--<plKA@jdfjxuZ>{}F2Ln;%g@)B`iC0M3k<^XX2;sJWVMnT?sZ
z(n~dN-e3ioFmKrf@kz5~76cxdKcEE5lzD=3WzLqrzXWl&!@_+7g07a?G<~>PmSv-H
zkEQSv2=28M`NJ7^%Tdbn?6aIY2+YeeMVEBEElU`X_pwY-nY^#%CJ%$)X9*jD+<r@U
z58C`KH9w*)z*0nU@j%OaJ3%~PIkXfO4q84=hRz_1V+$1+1zQwUo*!a)NcThzS+3As
zxlqgFRp|C%%SMVtg;^p>;ph>|-PQO-j#|t(J<kfa7=j@lVM%s@Pmz``0hC5rUVRJV
z(UxusvBX&BPy{{JBBtpo&JuYBTH-CasQ?L<MUF?{IcAA{A101lzQ}-!CoHM&K-)>n
zpU%*oY?+z?EX9(41lTEy^+m9pws5G#?2KgtJ-KHsH)ywV&f;_yZRaf$7MM@B)Kg(#
zhUGagn9sDd(q1jg^4dBOvn^3Ht>;)S{r`{4FIYOnpypZzkHN(}%XSK2<XdJu1*HX+
zvuELHq2&uIlPI!Oxq|bO#Ul=&*mB|{m@lz(&jKj3d{616%NA}rILj?>ya{53We<I9
z<cekI69AQ#T<XhJ%cE>yRhER;sapP;rHw)~*DZUTAW>~G`lA;$mWgik;)bP+5(l-G
zlp>7NO-n6Bfo@qon+f?k%WNvEs<*7W0HqC<%y%Jh+j8*^K%-^eIQrXUxtRjFW=kxU
z#<f`NN*HRj+^3q*4$E##-MFo3d4{f8cUew<2yHzU8&#h4S~{sH^p53EEzI{>q;yQ^
zw``)!%7Eq1-(c{rWpx#F-?Ky{LFu3+<QuRIS)Ta<;=`7LZ4ke2+2RcFz@nq?A&*-8
z?n7YA@+K|24=trL!RZ*c+@c-Lghl-ocph0^qo~M~<-j*^*x5Re4D-9Kc?`JbV!cW8
ztD7~f8S;Cq2~l9#Ykh&1ICra(Hai~HP988%tG^#O_gP1F0rRrnrRb5jbrwCVKGvCZ
z%J;Rd901YJVf~pB9{a81lmzv+en4+*fc4PV;0d%QQPBE;)st?L9kjO4Y8GVG)2<`b
zy6zUhVQZ%!K$vyHA8sG9zUvN_qt>OHARcZlrxbgH^<#>7L|RjW(H3Q0Ducaf>$iF6
zQmhrxO0dRRKl%r(@z!HhXqRBUz7ed)tas@weB4@j9Bql#Mdj#WlJ%uGq3wiqau(!I
zS~tbOe2R4`1sP6RU!D(^)7H>eFwUvgy)=oWSyf*`*%|AT5nwrM{Y8tmb5^fYz|LEf
z9lN0>-P%JDwG3-F)m3F%tG@zIj+J={;DU8~A<XAmmp=r{MeC*z2<BOTr2}KW^|A%x
z1=f``p%+>gY=S_Mwf$Gvy<|0+(6eIe*;T+wtSw5YF14zDgFu<}3;LSoW$WYr|3X{2
zHKrbDh4tzP8n0M)?}VjF>-%(uzG`i!b4``?uS&>Yv%W+3t*%=?+ydRz)(B^S8tWlC
zAKb9Y-v_9*2GdM>(<-KX^erp*12|e|ZTbj0>#g5RfTh9uG(EXZ*027h_pjMHotDEE
z>q9z`w_4wC#i+MgZNm_3xAr@sza7@c|HC+US_jvGv&&kY4Eb*BN3Vjj$C^po?p`aK
z9*;ZLPu2kRS(X3aWLaJ6VRyiq-UTgpt>N<l?pY%qLD`_SdIg;phO7Y;>>IWo3WMN%
zYe55)KCpiIG<Zg=YU<3W^*S99$E?1TZhdH#w?XN+HHXg76V}fzfo0MvpftiG>jJu-
zHf7aM!*Ds<@@YxmZ7Y2d0xq^Y??H>J?YXTWy4mj2a5?ta7SI7~udM~S<5`}zG`gg-
z&o=QoyzsI~SRi`aexiaVA6pqcv%a>{D*%4B#~+|G`)x&O@ZR5+P77v$E!GcMpw0FW
zCJxxf=)T24n-k^Af^3nr{07@tZ(z7WY^#3)@sPuo{SRQM&HD{lI&AZhVAR8G15`S7
z#J2cb5Rcj>i-3jO;wc{%VaulTYNYK+D;$lo{gDkU+V+npIAd&^3osV3HkX;e;%w{5
zi+Ec<6>=ol5@^moX4^-f0ytsYsRMS>=GgEb)Fj)s(n%!6Hk1O^Q?@TZMGsHg4yvIo
z)mBa$n>1T$Kd>{ltQuhFY*xA&b>23;9&+inzF#4iVSA0<xJ=tvJ9KB+23DZI*|wM8
zg25cyGBS9<_QGL+T$?`yV=mfWc2HeMo-O!4@Z{UJPzb%imij#!FWK}JAQs!6`326D
z*gm4;*k#)udR5A8vmLNhVRNUa`>Jj9A}m$eMwdh2nr+=~XsNMX;X>esO-bf!ZJR?N
zaMPAh1#ruDsRBCdY^}Wx@HE=|--p2_+jbVTHQN@Q18A|eyo0t@+uKrLZMIdk-EX(W
z(3Y>mcA2VKI&Ho?0J>~mbKz6B?dB=y?y(KL1D0N!CIbU|$M!)lSo&<PRJPM^>)j4R
z12)qa(0SK3u#&zTbI-PgDw+muezc()vgN!3OT)JJHbdKe+X;6FKCo3%z-PpEn@-K6
zwuNMH%vSaY;Gs=N)sf>i4b>@3*gm1VAd@yjK8TNOADW<Z%C>4FFlYM*`(SsseR={g
z7yHl8QnkFRJ#Yc2ZuWhVkaxFFQmE6zzUdE`_p~#G=*2$!3U`?IvS0fE+Pv-W(7hNR
z`z9I-Uwd>Hh<<j_5R~q>2T+*V-#+pa<O1x|C}bFD|B4pH1NJ0}{v5P-(Ge}ke%=Y<
zj$r#YR6ZACUrO1}L-uSsVuspd!hs#OuQ!4x%>MQU7(8OHKZmxXcJ(&^;r1b_3y!cC
z(5Jg1?W-vd5M>X`go$YTe?I}l*yH+PDc0^r3G6ugj0$uj-oBRp>*KiH#zI@7!+!Ev
zs7bQ>PJ_e=`=9>+J88ELU@VgD2Fk;ovOi&j`P23pOQ0szK1S)9H2Y7{U^!zCE`Z(h
z_7$@L((PhOs%O}}>mZP6KRy>&mi-B;Q^>Zjqg6P^zKsIu7wld`P@QXc*mi<iVBZ`H
zw9x)9eIT{S9$o}(m+U{&&b-+EOeG{r?6au=v()}26$+Hul~m<)*<NuHy(qW;Lxl}j
z?CC!MRN6Z!igVTO&48m-_MeV}c+LKh-tcO>Vg`sc_H??+b;IuEut8g`U57_u)=m2s
zcVM^dQFk!-b@ngiU~RCwY=-=8`xZJlHrf|01lDB#lHRIj``Hz+)MEdZa<{GaXDi`T
zyS*h8mOAX~s8FZV?%oJum;Ez(bh_=nbS=BbUPtvsz4r8M2Mmtc&(Y{j+IJoY&y?Mq
z0P`-}dtZX?J=^>GA>pz8KQ<)1w#WSm;JZDVO8FwTAFIWXByMk@)JV$qI0{LnZ4bKu
zmh;;q=*uaY+Y9NWnX|n#13E8mpH1sQ;r3b^h-KR|_R#xRw>^o6#_sJKi{Q-A_CFS*
zaeVt=A$)TEYmCmM?tkq|LYv=T4+>%M&|jMh03!d2oDMIJ{g0;i0E_DQ-p6zA-NG&l
z3w!V0-DP1l(T~O$qlqzzF_xHUqR|)=jU~nsONz!88?h`^dKC*zq=<m@E(jJBR8Ub-
zKoF!0iX9ad{J$r^@Bevx9Ouk=-*aa6mYFkWu3K&CD09Zv{Sufj+&bzF?4H>=lw#NC
zwyymMDwSJTQX1Lytxs1$C19J8hlTKM-66F8i``cHIk+>nZC?Xv?zS)rAQo>sxDY;_
z+tx>s@XBqIX+?2!TO-zN($;M;l=^XJ+Xg*cd$jHH8kl&oZNrBcuGib{DFAnI^rReg
zZ$}po2>l#y(vvjU(Uy{w_d2FiB2~C!uN&azIL85>Lp8y1vIQ(9JFaVoYMP@10W%#_
zoS>TH_=IwSavfdUfyi?_O?&$Jju8|dC~`DsqE_r!-435lI&z(WpK^?IN84$~A&n?X
z9E*R$m2k#U{@>Q1<G*(Bu+;Hi%7i#)cKm1>x^~|2-@5>oI|l6pqQWutD+n(-maK<Q
zmmFu&0`9Wo6lZkwisQYRP`T>pG6-$g9HaNbrz*$nrSR~EBijefYR9)I*ihqm`#Dr<
z9a##(Haq@!8Jum7A0r@u$pQRgu!l|S4<_{>-5SiwXn0i39G?&VTIO3ig;U3@rB%f(
zW~UY^jm$<KwI=3g9{g=gkO<*@W>FS8^qjG3MVk}*{sR<V?0~Ic31)>j+P=mgandJn
zX3&K+{Cn`7^|186VTfUxr9(cTY39((jre=)6k4o(zIp_j$Ibm1>|f;2hS~UkcA<5`
zI7;%Fxb8cQ)T9~o4X!U6dePs>{WR!by`)s|ueFrWJtcJ><Wuu`V83a)4(zuJ>!363
zybW5Xzof_0ce6|IZ}W`vK^UEx+wMa2{p~aO_pFb`q2Y%|1JJA4^6}`+kI^)AKNS{0
zXHE;nW9CjB4AP$y=Ye!yusvGmi}ZY0P~H!Qg%_sc-@lBEgZ`pH9dPT{<q~Kvo<Onr
zCHFiaS-SZcto&v!r>Fn&Er&5$D?$YTR$lc(^QwJFC6fOBCp~iictO$O9Tmy=+nsTu
zMAY4kns(AXn4jp9^kiHqfz^xQ3Sifp`5*?=K1|iSpzvkRKE+u0F|J3T62#m+0NiaR
zFCU&fU~0@WAbrRjpy%gHriN0XUolH*qUO#X9f4vuyW<{NVppEPV0yCi*1&`p``re(
z>dk)F0~#OJLrIp{AMD_aA3L%V1|!(<v`-evesdJX5q2LvhZ5Malvt9;zT#jgiA|kJ
zufn73aysUa%)X}UJcYfT2<}w&XNnZ0u~I*%q_bn1z@5RKr72D(dzyBZv)Fk}u$#?Z
zc^9=@_9%s%^4N-hppwrXpj5jYu91Q+x!hjLpvmJ#PzW=ht9b%vj&TFK=(IusH*gzN
z3%L+lL>=dxX&<ME`-JjQi@DZJm^i_W-UOPH+#CuNoZ{l?AmV9mB4whLaQQy~aE6;e
zE6B54o;UhZ%B>#;l`?J<9ceqq&0de%d2Tozr@FvZ3Gla^`{OHGe^+or>_B>v`?UrJ
zFLD1)f~Cvc)B<=~$z7*u$Q91`11w$T{09PfjT_huVHGD2gQe@-rgGT5!F}-qOjL6>
z7NMx&CXi+=x0W_#Z*nE$0I1{6x<a#_yZ;KsEpF8`STHwmD!Ts~xiNcC+~%fH7F82B
z&>#3_ZZw6uTDZj)C|WsPEoj=fKWPEo&V62mS_k*W0tWAJOKC;d$yJR8X%{!r7x24W
z#&6)f$K70pwr;NeYvAs4f6*T21MVoLr#v)sV|GCG5qEDW2H`QcoRZz1aD&%E_>?Q~
zfu}v(z=r@n<1SJ}<vG_tyCW~S&Eeqg<w|>C@Fh2!GRI$WV|8G0lAKtKp>&pvrb%bI
zB;q-68Irx5!I>#(jzKL;^57!?vL)sjEuhJf#8F5wSF-dWq<NBpWZ2D@Skmo!S@J<R
z*eWG=t^;^Q@>eM|uS$L>M^P`?OnDc#B+(R~Y?FMo2SvLimj|FzvW_x4x+Fz|f%A|q
zYzMWcbTwrLdr3Vk;i#`P!%VMrKWQH2v-(TdZiX`fQr*Y!Gz$M!BM`@=J7^J9Ag#ZJ
zqEPy7C;-Q$8_Iw$k}juNU$Jz{&oFU9s-bK3q_pBB?4FXYAb(4wsl(vm8R-Kj2+vAy
zC&5suG@ib?P$oT6L-FTx($4#^dmf)dhusU(i*&xBL6%6}Zj=qBIn`~MX9S8S+2Z$r
zZ<bx6mrsi<O+?Wu`>_dtHra<G>DQ7??}3NUWd1DL-pDS|r%9aTL-PQ4mj8GSUbx6#
z(q5L2d`<(!pMB+ZevtafAH54_{N=4QZ3~oN7>ThAk`L-bEm%JL6lx*zl19+%l~1Ml
z|33L_iWTjbXB<W?Tz>6u6cKXg1_&eNqn%L1%8wL7m@Svnx-dsxxfVsPJc`m5^W-D)
z{>zq@e~}FHh4SAgq4BtUDCL|M$;Z;c^kTV*4l<pPSKFgjCO=Dav2*fqbUU1vUv~%K
zf_&dN2+QRq9bmaAe@Z{$CHYdy`mdIs)WGc;`B9qI*2<S%fKNB&$0>ALFVC0^xcQd+
zADS08$bbG7G>!74U~o6dM^KEqS$-xJ!dCeopMj=LZb?s=4taSB0C(iw=b+LhpG7nN
zd-8~B(Cn7a{U3_^@*N_)aIsjj1l}L8NP7xgs6`9Sqr)s71jBr|#WD(wN0==>p~q#U
z#gYin9JFYsJ<=$PTdhz%Wbt|nbYd;U8z7CdxNn0V9=6z64q?1SHboc`EEa4;k!aEI
zKd>ZO<aD5R)MD3n&`h>CIUOuH7Nck#oNF<i&Jg5VETwnUF^h&`a28mYm(!(CXrZUz
za*>6cVok*syA#oP!s4$#L3+|+ogD`1ltr&2ge4Xes=;=~VkOOx&RPuE2)0s-if_?&
z&LW5d;Jn4!$6&c&@p>%UDlBrdVBw<0?-cpHWRbH1wN8t|5Wu@ED$M_7Dp{PM<wv)L
zI|Y#MTRbdB@xbEIYTzGP3^)hiV+&0=fKM&f&_k@pqUH)}{T6K$5Pf5Dh9a6yiYYQ^
zIxBuIf-^3PSc+Y`DlF7saZ_||gKO@Jk@V2rtyuFEZ61ng-_tVQQ&BnqJq%P_rTqCI
z#Yc2E?orHc05C-1I1j}>#lxKd?pH+9LN-ltidIeOidpo=%T#pJ+B{3~-5ii*D;(TV
z%Ta8j$V9H<Z+eO6DNavEEnhM0CPwC%BKI^j3ly&R>HSxzc#q!x#})4sqbO1=dIa~2
z6=}4>IiXnmH}EGFv-*KJr3mKX%xQ(gar!9~Mp{XpQ7od|hO>$-W58XiI2D1mGDQx>
zYR@S~&I0bdV*WB{UQp=hdMsBY&OlM2c!aC~v-Fa}^9FP-D^e&2tWwc@7;IM*DoO;u
zs`!omZ=7q2Rqha0DQ1e$ysr40E`b}0v}P1Finr%NvsN*U*2p&%Hz|RjPO*oQDe4uz
z!SMH%;)Mz38x(hbf@_V6a*8eAR-|SFXKqrgrFB5FB6SC(Eee?eKSiseX9kKk#myEN
zY*)BapE?weXaaag5lR!HPR05kVIoL5u@9~VEB_o0K$vnUoiz+s_S3v5Lg`9N^hhQD
z0!5Va<FOz+q#TkAc#P7t6a`L8r&|ITr+g}hr-zj<93efTto#Nv3Ca%!f;&-}wGu^=
z^5Qa(CMz?n(Uz*b@jKYklzt81E>P}lg=>Y%=J()Jk#f~Qa26}`eg|i%a_<drURJjH
zqE@NgLJRgQO5<q^-c_afeJeCxQ~o*tz$#@<3fQhI4`!mjH<Sy?pi`}kj)mPC<(HIT
z*{t-qiK0b$hn6O-%0-k=-KOlLJ;!z>Pp{t&<yDGr-cc^Eg4><S@gAVQt1O-k^Y@fn
zY3|dl45d`P`^sHrdSgCNhEwqIp>hNriF>3Ruo#Vxm2)P7=81A2W$rvxx&(o{NBQ(3
zRGuqM?}O%rQobMXUgdV04!%^zQF`brWy7y1UMs(&Xi1-P3MG>EE4TcK+8br%LQp$d
z4yCWWI9pl{H=}g1{EL<yu9iQoK+Vmvw--9@mX&cBsNI$YG=uZ791#Qey)8d^27^A9
zf79&2*K#IJZ2T?HZ9y%-vRn<<0xgGxLl|UPmk5?%%hz-_?Xi6I9cm$#l3jpDTCSw1
z!$C{u2+CH8vTTh6;*ez;J#Aww=hFuZVl8F#+s9cxrkP)prLGC?Kert50oa^W>z6>&
zS(O_FgDxtEWb$5hoW9NDrgABPqwcD~-vQ^PdVL=%-l~s&frmb-#f!k{tD5>30RAeC
z72SUUsvl^NHb_;ef;3pAI{=-1s+-yP)%L5@pQ7!6%K9(3AFBF@9$Vq6&;{U*P$?<s
z8L5i?7;Ohtr5^)uNVS0`Y0;{+a^PZAk0yXKRyFhm%pX>r`V7K&)y$nxIik8j>uz&`
zYS&1VnW`!D*^?~Q9!i|eR+UqLKSyOpFSlIPZpvNBQ}LAKldqcf5JiD1n(p*M)iv5I
zELI(&Qw}Fp>u5c5N@cYgcCV<a?qQs-sxH|;^P1{oIu=-^dRm6sbydedV7Xyd%^nMB
zwQ6iU@V8YxHK;YIhS3IUvntLJsx2xfC1~1IK}*rmPSw<E6kV#p_0YVl3Q2|ed#V{B
zP<f!r!<0h$Q1vdQX+Bcb4aCp%SQR%2eR-w|U4i1cDxBgBFI3%hUaePU&N~NBU#iAu
zz|t#KpcTA$tx`RJ`99TDx@G*V+-OhB-zuIWsR34fFHr<q)lGsh$f~yyMX=SobmVZ4
zmH9Hvhgc1#yJD}^S3IcqS$Piw*?z0>CxJU)wScaYP^(w8f(f(w#GHXL+$v=TR3of*
zHUfXp>Uld<qpZ{nibGazl<g92RYz;Q7_0Fm(2TXZPVb61D^)d$c&p8o7=$BM_b7mn
zV8uA0hly5G3=kf*@}G^4CR_D>17V6){=YDvYUMQvMVi&6-Da?*TgfT!H^WN*9(s{!
zHTp9Ev#h*dz;3qHRXWI&YxPb%3Qy}tCsBA=51tE6Z|j^P@G01O!8X_pvyL83eX-t2
zd4mzwU(zx<()tWd=c24fxx&#y*0HpS6>U9|zE=`sJ?AeD_g}2F7z6Wh)^{mAG{rjM
zDm=}xR&Pa-i#8zgtX=7Wk#D_d5NOJ+Kc+Beg>}V5&|I`$M}dUv*4gxKykR}+I^3?d
zuBEh(8f%*#2y3lJYN2w|`Y}C3>a2w@cvx?}xRc^vx2!{k!9;`goa-3;M(Z_Sz>C|~
zzpsO8lXd+MaKG7l*D@5X*3q=!Y_ncKTmS9WdkaC+VZDZ;;CHOWPyilVFQFj(6YJM?
zXnSfcr*oG**3GX0cxHX{JJg<AzekCCFRTmbHZ=EI_ftITrS&Ii0KT$r_z2S1);lTW
z&}Z#UzfZsQbh_r8)Cb-I&{_TZ52(1P|D>0yt2(I*I5+hPdSAP%-yZ`ncB{MBqUNC<
zxDJ}0YFj<vUg{640q|C*E``uXJz*xs*VnA}DT8@G^|agQp}+dxE&v16Pr@J!RJYKO
z2B}kf&=#!T83o}Ub<Pp|6noX<{+k!67yk{F{pv#ppmIQMqPJnF`nC;(Vd@1n7@2VO
zv|iLA)NxiY7^xoK0`mvepV4;NA+<S+5|pFWJLqg!jQUeg^fy*L{45&d)E?8(c38cA
z41n=!j&>lAs3#nOiA43vFVUGK_1k)=990jRia|(LTP#N{MO_vTmQ?lce?XX~en#tx
zboG%#;LK3JyB{i<>an!I%~Ibt4}&yYy{!>_%2l^KgleAJo=!sKt6%>M{4w=cl$>6m
zerGt$7pi|)h1zj7OOvf4b<JrwQ>xB>0=6>sqPYN^Q=h$naXPOaLUYrr>bbs9xu$Nv
zfeu!w>y|)xT^*bcvK#8eAj)c}R{NcV-5PZhJy>hi6Z3$$sgBA5Tb+77WgOM3zosST
zEwv;P!UlEXF|akNZ|?%zZMB33ze!#6IaFHIVQV04RnPwyJ!?}3^rNj^t#AjRL;bND
zDtFX>(95M$Ju-mqzb>^69q7HQo=KO<J+*8S5Z&t4_7L7z2MvJmfjZe8h==OdS~&AW
z%}{{wsruo0wDqX}J_W!tbpuV%pQ|}{sJu}7(~PlKeaamjeW@N92Y|DUyCZ}yHm&>6
zU00j@K-&LtvzfmRecEkvHxO(dHdXbgdD;x6nUt5!n?LB9wJCB!n~%-yFaUjRZvPKL
zKb!NkJ?L+9GZS_LY~I}kOMy1+6!Z(SiI@RP3AXhrbRx<2Zy7j~Z8sJGmukD$9?qoO
zUicRl%$c@dzXjE7+wHXC%eB2V5|#>VC-YFfVVj!|e6y|R1hlo-s^U>=wRK;FTAOX%
zT;SVnfB7E_cG$Mk+vSn%m$aOEY`bp+G@sdeX;HkeO`z@HUR$K4VJvKmC<pA7ZR#y}
z@!D(~Pmzc|+pttf`)!v@gWWf_8&kpNq&Y&nvCf)rX+q_qsh|`KSB?HV0DLt=L%{8)
z895d-;hHU!<r$&z+=IRx)VR|VJW8{%4JwB;`thhmYX%R6W~?UbGa3X<;1vMUH0C{V
zuzO5nn~tJDvuX|u7HTp^LFcUIF+CAWHT8Sw>ej^3v8HpHD4KYl*C=Vz;DV+n3Al32
zsa)VHG?DZhT-0Q)g567+tqV|G*2tbfSgHAeCcIZP<0+t9r#UtYj@E1RW(v;S(iE?U
zr3OulGZ2lMGC$OAYo=DgizZDRrNA_6CNU^lG#@_!uvNpnMxWX=i`!9a*NoT=4?8qp
z=m5W?Sx*~3otp3IxLcQ|z6Q9vntPNIa!(`q2rAv0-^T)eU$f&I+JAkZX|ja$q2^#P
zfR8k<X=CuQCg~Pjd!iZGiP}?5;`gBG(P(}I;F+d{PR%{nbY6qX3(bnlXzSG^UWevO
z%|||{z0&+s2otY0AJ86LpGLO>=AHO)8!(2>e0DE}#DyQxOZz{r{DF6%>c$IKptG0X
zR1WTa{4d{u`vBiJ8f>9_+OGgc@N+Z(M)EhJAw0-Wn*)ENc>f*n{t(}G8MSEs<PP9s
zcp2sE$MP>I020S@lr?ggAM-WFDV{$y81N(fSR@*nr3rjN7o>^&DVk0u@s;(c9pxP;
zypYTn(I!|5|CFLRsr+$DQcdIE&x2+<KS~1b3|^GL`%Hcd9W%({pRY$PoBzZaEIItN
zDHyI?ekLt@^Z3^^jm+osv!Qv65C0#8<^ukB2C9Ypu1`@t&X-YcR1rUIBJjn0ha(Ut
zcqMJRpXAL8&~}O+K`+eHd=W*`OL)%{fS=)4Q+nxH{_`y;O8F}k`YYoH&~12*ucs-&
zdH!>Xzg*yVJVTet`AZaUtuXUrX_j@7zjYIcOT6L|5SMue+9|H&N72je3O~aNs#keQ
zF*L97n^YK?D*n_hn7_`4lHD8pMm2=hyhaL^8s1EKthIdHMie*sJsIdr9siPMLiPOp
z0jS;L%OjxKz?<FDP&V?j&!UI7`D9wqH1Y2npxVrDqysB0`~Zq<welqnaIK9Wtwvir
ze|j<ucJL)MWxK=oT!OHZztRbVUHthhIC_^qLP4Z^{OBY&+Rcxc3E_Qy;YD=m0YAD1
zqy3OCHq(3T5#L3>!DD`%5+nPBzpq8@DPQ^(O!V;kXxjda|B8Ot=lpcC^n#yx0hW6C
z4}DO)<g@5i_lo~xIW%AM%YFj9k3Ufa&3=B=QS|o>e<TWUCt<<ID4YemA0TuQ&Ig!b
z-c{ge$HGlWqSHd|!uuEC@NQv)Gin~faY{?|6ed)G)Jw>_0H3^tX|yo#5lpEle1&gs
z!jhlx!4u&81%n4v0)#|Yv;_*4*I+3~ko~tB6eg{QhkFE*0{(^wGq2Ns?z>lrTLlyQ
zgf&S(>=*u`Smgm>1s&NB6&8D8yuyS-J}?n31kv_Vgy8cNEJX^d=$U;`7`+cFQNrwb
zuyjax`zrbpEx6M;n;2mReJ?0haMr>5I3X|`Du;z+Z+H<eOq)YrD?1_t>;gVP5F^2s
zC<IadV3IJN)@nzEhqQT~EM(KjrU->Pc#$eZ(^rMlgabV=kuL074q=9{z8fl;LOVUz
zvxMPapoiH)trHC92vT|q<O+WXP{|YQDAzP!7(`^|W5S@VFkc}2MI%%wIEBOfaUo?J
zYDL1*@jw&{rX{GI5W-iYI4MLg2H=$N;c{r67Cs-1aVilym%`E+q3R{<o)z@ZQ7aYh
z?gF4pSic*9bHW%q6z7G_6f(RZ?4muoa<kAGg|Vy<7SgGKi^A+gkX{m0PUzZYp&<!u
zm4aImYFC6(1A1{)SV>dzYXVDOa;XxoKZp72!rzqGc|*9f5k<9-brxhb!X0`D)e3E=
zVCkmt_9(Q~2}S*2sTW4l)b^HO9*_fr4Z=^9VA3f3aRJ3`;fxH8O+wsM)S89Kl#<mV
zjM)o(s}M<{hc;mk&HCGggB1Ae5KbQe=^eqj2yLChCm#UUB?Qq?g1f@(dXU`{cGDWX
zTR2V!R_+Uudi45%@XAcF{)a;U7F<`4gzx5~YmWt<0+>&P&uE75RESChO^@Js3&k_x
z&_D3^xv+-^;DxY()>FO0Lb|SA3W4-YcqQ!o0-CRd<liCe69f|s_6z==DBcJgvVe2a
zhN-~ftZkCg`_D!DAw|Spwd0H7x0|*~3RQRQ2tVlT)}Dz(n}_zDFCp~QUT*`pmv%Q@
z*52BAw2kPaEnv|#U+uT!&?i6bR!XVz*9Oy<Q3AB<C`BSr>q>#1AZ@7?ID@t0h61oh
zJ29K~zeBXADXg(qd*M8E_G#BrsAj)5<r#_t+N%Aq6srBW2EZ___Zeu0YfsUtJ3?FJ
zgSJTRA_|VAXbb7EQL1*wbU2!(UH%zV(zP)ZC(h71QA{UOYodE3OZ%Kw+u7Rnm?N5{
zIoc^Soy^sCY=)<K+K?0QEnkbwM7*T5?;M8R0&VCt01LGzOF?>Ed*cKgEz(9j2B275
z{v0MwXd@|g`=mC)1%OjpjSifrwW}zpy+m8P7qv6mjH{@f)gHM9vQq6rno^s~v}b8~
zb51*z9`@(8t0`0Xg7)vhFj1~8?gd+gcE)S~FKU1L1vHnm{j*@{vNnP4kxK0=dYxU-
zezFv<UDY0=^}#jmkCe$-rQN&+mac1+6G3)E`;5+5Rcp`CDzZjfOY65<vsRl16F0Sw
zV<D~6{(2hSuGemqLiLt*7oCo3&?d1^ZPcEp?T_19jR%S*tuzECnzf#Ed9-N#7sIty
zZ7HRGw`mW20+n{{u*Il#Xe%zFXLq!#=YXtJ8=QcmOPf^*;a#nH+H(N!X&3S^*sb0E
z0>yppF9~RTp#2~p#Y3%mAo}!38y^bS9&2qVcK$@$=nK0~wM!48)}!sqLG77#*b=Bb
z*Pd?!%L{G$D46fnwrgPUrPhhXAiUE0PKNNccFx;S>C;-7DM`IwoBkdwz0uzGhcixM
z@~`NcvpC=wYA&KR%_?2RN=I0769+WFlDpUzgW7JfY#z8h#G5p|@)T1jbJa^cQ38Os
zIQ$JbeMIkU6uzR2E?_^gWFA!f#gp`o2@t<{&x|rq%u57Yka(pBwP4Y5KG^n%#kA8O
zBKq_~xL14<44?Li5?aFS7dv&R9T2zDCw4+b_9Jv6Omz7Uy$=^tSa=vAhSxzeQoNS|
zg9pWzbS@%FbfL8HL*f~VPDG2r-_ZRRBgXi{;aKrYS9lR8M$tO#u$V(>gz@5Zig6wh
zQ#PY5L0qs3_(XA*1MDV=OFdB>6?J*gOcu-HpqU~z1b{4698PnHH1TFVETxO4p8(Gg
z*N=lUnPT%a0J6l#4h-(UY;iN)4>{uc_aMy`3+S556N^qkm@oQX1n`&`8348d@hPSJ
z6pE&=(V64oxAa^u68Tn;7K@2#0Gtpl-vEA6TuX6~QzA=Qt*6B?bjOs4PWw?iBYvQP
z=2=mcLuf7)9X|zWnb;hFuALMABJT5|cN|9jf~Z~tpUTC!HndfU2j~TKQ5;TN-j~F8
zDRgjI96(ohrC9$2ZCAu!o}qSC?E47juZeHZKv5-@ErNyX;*8ILyCD`*xT;!Alfs!A
zvp8)v4AzQY(RAgenDGKm)rpy-pjt1!vkCZH;tCqs2C@2cm}nF;831pK#-Z@3NxV<{
z=gp$uL$I`n`J2(TR#DXe6K&#SS_Za@;XzR85OuMza7Wb8Q@T@B??%xjnn!g*dRKI7
zg3dkh3@s(PMVqrQe_xEJDZvBr@_p1EiVC86B(_fj>0@yP%|V`sM`?lmRP3a4ay?=e
z%`BdYE@^Q4xp=%9wHM+77u0&ipXu1mOYzby;9iNp(~{@4c+dO+bo#`&QPAlZtJBfZ
zH)8aU&~efwvT)H^SH;7Gi!MQrnyW6d3vF(?E0f?;h%S@Xt9x}-l!Uxb=R6v1`*o{_
z0B}I}`xLZ=>MSVxAY6Ai5P%5X07^oR)UBhy<w4!k0rdWh(yh7z^M`aR*P#}ztI`7>
zqdQ0$KC!xOj_^B9_bHJc*11{&7_Zw#d4orE74M@+(D_mDIZ>yM10YGapC%?pbvJDA
zGbQW7D0G*iyGm1nR9)y+2-9`ug#cve?yRBH>X|x+W{_s-?&x7DTW3pqS2;R8?O^BX
zc6Y+3JhWlF@^v+K&^)FqdmsK5=!R41y-+8w1NU*=j(1?UNcSP_nilK0kI;5P*C)eO
za#A;m)^?|K<2#^oT9-q@5}j2b<-ecN-K7=9SzYiExL>OK!2#yWKnhFebXks|Ij_sy
z0%tDh#&x4J<+>}Mqo~lW`xm4ab^E@8`AfP{gTQ@Rw}4`~l{)(n6jyXZ4?%cUSGgAO
zYr5v^(5%vlhfrMCo!t(z<{P^28eyVZ_w!V!*68*fMp3Jq^bHzs>OSp4QKu`lfJ(hC
zcN~1WrCUy$whg+SdqCQ#+ck)82c13zq)j@f58+d@ZuVppExN_D+Hci$IKi1V-B4PG
zwd+b60O-(lWkPtztowE*bUJl2GQrlRyQGGtySg7|L3mH+^d*XJomdOD`?{C(Kz^XR
zX9fI2-Je<%k90}J@bIy2$zHhjMA!R02JflPZ#M?0NB3zw$e!umd=1U#y7Bh#@P#hd
z5_Wra!8BuhsWXSs?E96j*$z6dbtRP6)~74n2-SX_gx&{lbhj#@;-vS9f``uf)x%J8
z(O1)I!&R@MNUNKEHKiuH>)*No(%t&2l$GwGe@GX%r~V*iaCqs1X<OP`fAlFhee~}>
z2HaOa#9RxhpMF1Wd;05tpqF`oejX)s1nT|iz)O(+M~XuR>*JR}Wsg4P652xacMgMl
zuilk1Pxk4p=>FNS-&l>}fIj{+7!1|tjR8DNzbzAE7_R@<1eOTB<$EY1^_%TMc2Hl^
zYX%}ppZySsL;6AV8G~s3LTd<P^mB6ojMZ;Ei&~sMjCO<$>kZRTi`UElLG6fs1|619
z&~JJhJ|*fG)7Ng3^wI>79o36BU@2LjP4A%;y+6$nQ}tbsppvFvFdWqB`dKR||0P2|
z#Remrsn@rFElWS}S2Skp&GgjE(HAcSK39K20hK&GyA{HGee-qHj_G&oL{XsM;f7H!
z)UT}o?zp~^uHz#8p-nJYtoNc_kQ4g<rNP6K`Xw}Kr}R}3FmzfU8cp-hv-;{RR7>@_
zl(K$K|NTT5Jg@)X&v5^OzTr54<@%1(@Vi1^`aaq&>Tl6yc}f5CbEsU__ilwsrM{FB
zQLpIp=vu$3{|-04^qT&%8``S$1r#H>u75%Awi|jS#Yn343+I8wT%&jFfwWfdn}^^2
zrv8IKbf!+fY9e%Q=||I-i5m1Dzk#Jjy{sR-zpWqt9coSbkB))6Szo&wG%fmN7to1T
zeK@6sx9RT>2WPu}p*NiA&=00mq&xbVH=x<6x1u?1m;T!i0KaS2r>{lzp8irMif;W^
zi=cX6Kb>BK5A-YK(0QnTO^g1=`akGE#S{HvngBl451_Ql9{r%Pz&+EyqQvUw`XN`~
z?+g7s$|dO4d(iUarT!OJ)L!XNhr;}8y_6Qnefq65OX}B~H`PJ<MjuMk1}8(;Jg_+%
zKBD=ni(zvc3RgqKVtC<Zcu)a^yTO_g19uyO$HSn9;lmS9@ig3^N0OJJaST|z4Sxne
z=wmo~2V>!D_<lbCeufDu0Q?QM*U%PV`1HSJk-^D)9Kaxh`2nQCh97C3vBw~ego`1D
zJv5EoYnVZMeESSHIhfyXNTrC{0Yd_1%7z-^X{#^H@D-(#g&SfX0v=)5NEchA;nT_Z
zB@Y^2Qg9>6aECU|4;ci?q=+^Qn~GYD;p0!p?^r|px2VP$##4UbVZ%!5Q@kNb3e_V9
zGm9ZfF#H(-yNL$%r>G?v&QoUJQG<*Y-^qrKUFcehp;Lw;)$l-ywlsqyU4iL_pJ~>f
zVJMD6k!es-hFg~5$V7ObZ7BJK=ASu+96E!ZYxtEm5b_K)aVYW)Gvx5;n8BV7p%xfE
z*@qq$8aCyE`?x`jh20{<8j1-O8>%%J;1h;lwnKQ*kW6#<Q-&j@uyoqc5sASoF^qMA
zg);^>ClqH5Z|9(`)bRDDw{ZWJ8Pqg$JZJdY3%x&Y@QjDu3kDy5cu{WnrwHaN470vR
z?V_P%J5(+i`qN?QvcZ9tOqB*-djPH&K97VmR}F8rgZrAn;Sl_-GPp@$@VX(DLNqrF
zJ<iaqHfW}yt;TS$6L52_A-)%+Hx2$3(5W+=`vSFk!}=Ley=72YqiYR@e<;%0X!v3P
zfVT~AzC^9bkoW;Kn+*rLA#5=O(w0oC;qp5$-)0yv6oc@{;8g&h9vhU00eE8APWwYo
z4Ojj`(PP*{Pts>*!*)9C^xUwCW}Gh!_fG-eYpAP6?WJK&2ijg4tm0wmwP6+|?DQEH
z(W<Q9a3c;hDRvhrl$L7OM2Q0FcFx1miA*~?3$$g~?cE12vh6k%LYQN>(jUTHyG~m8
z<=d^MiCBT1*@HrOg?9V~=oH!Ar46EDJ2UNYp0Jy(q+isokzO*V?AX7-cG_+sCAXB=
zou(b7Gj_kz^?cTD$XLM3>^f+=an5dDI-EIg7fVOU%k5r|1)#!i866I}X!q6I5MHvo
zPDvA&?M9j@gkEXKP{`zp-FeE5yJ|Pd1e$AhF*MVyvJ0jS$Ln@mN>RIE7evXz)piwW
z0Mytq(Gb?!rP5mZrkx#yo$BoVqLHn)Q>;fPZrN?3BSZ~$vnUwbXxBCm!rOMUwD76T
z&eo6azdLplZh@xLZV>GZb=lbz!u(x37Yg~`v+JW<t=n#vh~mE8wg3Pg*u9(&%|~{_
z-vQfWyK5eRKe0PF4#iWu>%9>6*qzCQ$}_u-ui)=<yR8ZcU)WXAX_8($tNU=~rCn+|
z{ckC+?D{FI<+a`Vb1>0o_nHzU`t4rO8G|==vI(GZGA_E0!r8dS0c|eE=H0O5YW#X8
zaBfDA74XU3IQ<b+b{i+JMb|uxgOFS;^)!akj-8jWM?hb^jSpyt!^bGw1EH_ch|M*#
z)X(_vd-T`e_y^610*v*P>=<Y~{SQckjTb3Pa*uKJk3fVNCrME3HI^@diG9Y@2K;vW
zjRD?JIbfVfua!{a;OnpyW}LGWoZ&_n9&Hgu@mJs?jjj~>J80bXUwW_cI?WTzhm7r8
zKoe~oOIJ&bamh_^#~FJLW4sO<+vlRc@y7RQ1Mi4&$4?lN1Y<9SBa@8jcYsSamZ!o}
ziZLC@Jkm5{(oz)Z#-BDoCByhu9_(fs-zBmvqa7V5&Nez+gN0n9k)lU=W@8I&DCZj^
z=uSUoJmUo~3XE~Tfwa(=<qsE+8%K`;O_A|u%9$)SdeOao!kBv<!jr~qI|xr1f2Y0b
z)5dpaf~>^2b1xh{W3&r{@T^frpCBtWzNG7-%(#paX3iNet^&(>qj@(4UdoM;{U|Do
zfBOS*(b&Smw@b#sqfxtT98JONO5@j*Id;X^M)Rtd#=8k%^RRC}4;nA~7>aRv+h24>
z+kX46DRm>vehY==BklW^qc4Z-`5}PE+7BNO%>?^tG-`?VtISnUO|s9Y<;_w1^)gsW
zwy&gTev1A3-@uDh`&fGKrrB>;Oe1TbOnIvr_7iC~n`v*LL+e@g4K&=@_6kZh%dvMI
z1<pMC4;KQLZ$EcDgs1Ie+hMT8zLWAuF57$T0$HW~y<4=7yJF8Qh25+6zfFeDHT&sH
z;Y^i%|99xxb^E~-=)GYdK<~zCd%Hy7YwSlY1+Lb<@+6$OX@BSzYIXKs{teQ4d;j-<
zyJg?r23&*vmoX4F+HZXaxZC!tzJX6o_JecK)@=W@T7mno)qbrS+->&L3&G~<kkW}h
zxjCHv0Hp2?Z~g{ww?oAikVZIkQdU`{!;&P_4mvo~Tt3QSFzqHDa(MJ9YS9k2hX5Yy
zFoV{~aSpZg9*K9jatbVI4s`}tNO!pV2;I$akf<sDEYrcb6TefIgC7MXvK_vmFCFAK
z?4AWra~(1QVCjUzRNBoy>EPgowo?v04k*eUwx0l7g~RBdQCxKRu@Wkm9Nu(;rP4u3
zNlRB9{-&knHHR9y0vjCm(S6_O@NF?TZ#$@I|G?bjuyYA4wKz;$2%1(0L_F{ib9hCY
z>(3nOzJls=2d|sx(+h`y)%bmS9aQvqe&rBN*ZOOR4hk>yIRsgw*6$Fu6L2R}4n0tv
zO;^jH>0)|kI=pZ-t?@#eo2fe*LU+@m28_&Zv&oG%*F8;>XlCMNN~uBNZMyp}I^$z%
zcn5y_npWKe!p}5*7A*Oj+P^?8z~n~Lx**foP{4ytHTh`UV+yA{%n;K!S|98+VJ8RA
zDO1+_(A;nGFrmK(O#aK!7G}z$0CBj<-1<EbktXjLG#)gKr>J$jY0pM99x*+j8G52=
zHC+%%rojVIB%3NI<0aK}j^YAoro23;q??x0<RQa!d=(64n!2sQnPtkPr$Dx8bpbrg
zF~v|SV6N%#F%)^Gh08#eZwfH~iBULaT44)mp=o0w?4B{{wP-wRN}&DHQd0??vM)1b
z)3f`WDWeR+^QL)pU0g8jp}Ag#N%;#{E}A|$h_*|nS*Or;!!-I!6xF8CeV}eM{Ym*8
zw@v#8z_ljRNLs-(o1Qh&{nujZqWN~K$-No)Hj_JL61ST&)&t*Ra!!ExJEpw?@SUcV
z84z}vwowwpT~qx{Xx=lmZ-W<s14<vTFoi!uV>ZLeyU*x8e(x^Dsa=^ix;xyM&yS*T
zXLkO#P-c?L%s_fD-|mEtC)0WWU@xYV-Z|dP1^N+u7<QKAEm=5oiKg~B%!je?G?%$e
zF@QW~5^WIWGY9FSImT2`=4Ju2$rGG~Ov4VS9B2MKhoXq7Wq>PY_R@C(PcSp+@qUtt
zDW?3JQ%u=#=$vLkyn!!a#?zMH8D<FWvXwIvR=)L?tb;Mq+SZNzxCwZ7b}i-G?q-e8
zAoO70bppVX<?~SUV#9yJKzXy{==I>kp4twfFWdGd0DkO-bZGjsztU$j16ZZC4EKK^
zYbBt+L2ODmya;B`BE%$%Vt1cFx2xDftiENtxwmKz<;e}f`coFfU7iZ=eO$#L_#4h$
z)xcmnw;mhl|Be3G!{_mjaocXd$oPW+P@SNoIrXIf<-)++)3hi5%ct!C{r>1Q?Xqm~
zql?io=A-|9gdR%w_hBy6m+$hJxmPimr<o1!{NGP2+@(2iKli_(u>FQRsf1rn61PbF
zIDwKbYfuMCeE&r)T3$>?ZDQoZCxJXxzGW@=;^fCD@^)K2>Kar!)YBi3{rl>bU!bu^
z{e1;gU#nk^N6ppd8U>cTZGNGYv>+S#FmNBRY1xWelugSDXvW)=&j!sAn?-}*MS@K$
zZC@wa9Hyvvl8rM>caPfaT8UmI+k8rK>=YX>I(nFDbJhn%n$58w%0JGw8M_jyg*GoK
zQTw!w^jol<w;A#`Jgu~8{}K3Fo3Pg)y=n7P3TWzV`p!eM-lqO-n7?InlRhJQ-zH!>
zG#}V(y@1+7n=2G)d}Q;`8@0zajVUnr#OCCC=)_YS8EwM%*erXSp8wBmzM-v@=QdNQ
zYrQsn1kAs*aa#?YS2it_+4kBdm;%{-HYxORr+%ANodCSC`FRkyoorthpm4S=qJ4fB
z+ee<LdD#B@30ORBH5B9XvbAsp&f7NjIaqvb7rcd9knILatT6}Mmi>l~?y(K4#LpFC
zyC4~M_u4*g09%}GTMCV=?ZwY&NNvBU1R}%s$3B?Pww<#EJuI}fxd+X9+iyNb+b!EN
zB5kw{i9~VR_S5AkT5Lbuh;FyqZZ*MBukHT3xOAK}UkR}1Yu3!BS-ziU*i96nnrPbD
zIHZ|69)2Iu%$Gr!syTfZ_#DlOb+B|?Q~d*cD$y{mz+ceZr!=`M8uKV<)@UyIq1LE5
zKyk-*4MSNK-I`0k!tPT|m=BzJrKyaiapFf_K;gxkqiJ`_n-8HViVr{C9W=hY6YeFc
zAMch9gg?KF-eLi~&oXp7kPp3zS`e?IEX-iOsu|Ag;R8m)?GWC03vGM(S3`i?$9sMY
zvi<ynOTZoAM_+(2jz31ZEQk3eX8?%jkDD)3M|rOnjAa79kzx#q{Jkd7B=J{P!u_NC
zXChRS`2mS2QurG*gGuH6C|;Sye-?$VrSn}BU&`Q>v;xoMFTMqzviOi*7|h|h5NPJ|
zRkUxG$4@!~Kt7*B>#bw_AWu4yUBC<Uf-U6d(whA^e}_6+#9K@TO)>vIMMzHY`c(j)
z<cAD}<|)2*FD#wrcV2|BgzuvS-ZQ*{(zh!4nkaOsn(yBZ>IQzZ3jl4r>1}v;k58ba
zDkQiphVT{t%eRsRxVrh|Dya7HK_3I(&mTB}#y7k#Et8#ulmc-33Ue)>;wMa{*o42J
z`2;Eff>#Pi1BG7(qAf_^>4CRLxJZtM2%Gn-OBthiO%veJ!g$IHiV=bjp%yEI&{rwq
zgiTW*JS>FQ0uV2Zje@-+!hA}ZPY^b}fo77Ribn0I@M#h(Bnuyp!HA>?3*uoYRp_T&
zp)?`66PoG5_Vp+-gnJZ+E)YhmFldE>+}r|uv9Ngnq$dQPiVMQy*`O&G^jBg2qA>Xj
z051tQMxa(L7+#@+HNrZ|dA%u=Ccti;kVE%mt59qNS({Kxv$%F)5A88^2tRd0<&KcO
z2VLqER=c3qB}}HA;=977!}Rms6Q<C4?{4AMS|IKVAIf3rf$+aC;Kf5BB^I?uf=?Ul
zJ{JDj1)3*<FGZ(&gxGliJQLD1813i6>WQem5X$GE=oO9(Mh{;KhaSSwS3)K&e_jhG
z>0C#ju=Xs-`i0CyTHd}9f@wzVq}}i{fX>=QG0<_*`V@oIRjYXk58bqLPod3ED;)r#
zzxMYxa4kSvS_sWRt=B(b3)Ze!N<XhQ^%-0X(f&RVj_%bC*aW*V+I<uNi`Ax*N}P7@
zS=0_|UAo`G<27D;e;-JXXg5y;FhP5a0z-+~FKPfx(*8!@U_Gk66Nt8C?H>s!QnU-J
z;7qD^Xe(Sx(=MdNZo2j*9@a=?sEdM1miEdhaAs>O+fmEW4*LMLT<tH^mZ#mk6(gFj
zJ-HY-^D*r=^cpPCCQ>Z3Q2XyiG#=OP$JQ${7z(1{MX`1w<&>Pz*3&O~Qp?jxfm2!q
zCBmN8E*J>FW$mC)n6K1&Y((2t?c<}sUDLip&zT$A(^{xhYd6tQc58#9F<kexTZf@|
zW!BDhM&oO(T_eo*Y3=DFoBi6WKS20KJBi|9PNG(Tr_SPYS^&6+VQsMMDvI<nbrWCz
z3xn=r5QPSJi(kw^n}@jJU66T-tA>HaOWflLxVNY|h?=k1MT6%jZcsqzFPh(30APUl
z{SV*{6sL?pV~}Vn19z~vss?R)#3%)XA>t2?=+j<tAkEVEiFfF!wO@>P0qFs8C#~~B
z#WmkU7$(-z8H#W*cMrTz5I?4AQ=<6M6bO^V^$SruDthk3FOn=;o7aFlMVvSa_%yNQ
zIP9j26Q7|^8REyZ2F(<mF2ai}k)zDrY%zqAI1i0TM{1ZfbHt5*;Y`+um<q6Xe(=_O
zn5Y?<q=1R0k%vx$rSD@O3SRbqoPPwu;4%HQm^m=!dwMX1j`><+26y<FgQ;N49%H04
zd1uBfHbCd>nC&y6Q!yr<?(~i^_i4_Z@af1amhcpR{`!nA$<<-4U|%D?kH7!EWeG3V
zmfgYMTQ1PFY-?!%=(nxC3aAs)Lcs!Orm`M27iQWaD0nmG?17;1Ve%;J(2t3t`R88d
z@FZ~TV;bqR90wUSJ+Gsf2hXYJOaLVxB`}jH%9qIeaSOO4#(F7+>L~NYCm_vY?C4Z_
zHuK$fSUS!WFGsD28AUgFG4o3`a3`2KltOWynP{e6>I=*VwID5L#?hy}Dwq|g(RhQ2
z7!I~-W*)^VYnUe<Fj32#^M<gA`HuE-nwhu1LD9l=p9Q>?=^lk1wlNO7!P(AC{~z4$
zVA@*Ic85vqgWXPMLn7K9F(;qG!eb_PAEoy{VSFhv_LLb#8)-evL=9?v3{M*f{mg=C
z7@#*y$5D9U#Ll1>urs@qk``UqWSWz>vMVXu(2Y$c7I#)btE=5?C@n@k*og<B;>jk{
zZjl$uQ+}>D`v*N!ec1A;^!)Q>&(b@=kF~rDhy7XOC=>zg$`BNR><oJ11+gneq87{s
z)8t?eTfl=Ygl(fe`n~K*8C3SMX`jRHe)jmEXgk1;`xz!eSq-f#!q^Wf&pn*oy9Yi+
zu-obE7(P7llKwN0gY2M@0LHV2WKccAt~mu~(%3unJV|HkQh>-{%bq|blif)N9ShiT
zT@V(seVz3Cvai1acM%)B3U-UxmlVh^Wj|Slwla3PKQzy=b1A%Vo}IM`@C)pT@8McG
z>#_v^a|K(K2JSl6hVmTh*_jkXzQwLs1YiUEfcDs%*nlnoTiLz|K(w(leSmLgy+@%J
z9qa>&Jl<i|<KTTK`!&5_x>$QP+U~MHT}7J{=erF64{i+)6@PBgKv>wz#ZHDW!pzyf
zf!$bc@ozA3l-oh+y2)IYH_WGS=KrBc<!;a_GL3sqJBI1pF#7J#ac*KGOcZfBFJZ8l
zoBIx2JHef;g~~}z_%G(iIorZ~3HJrP3(jzRC@gW7i#Ud&lvB{EyNolBT@CJYT=z}j
zt2p&#cu~h?4FpXy*A;-aPOfVsgb%s3Wk5XVDkuck&mEl)z;4MOf$-i#GW0D7JtZGZ
zMa@ehxd0R1k}qgs?jtd@!wX-@*>6!hAPIO5e?uj8^xO!O3^zXlO}J##A`}slNZLb+
zl-SIG&Oynzl>i=+RMHb7T5^f@#bP9VlolN;X?TnxPLjV1ZHFaZY7A+-L_<jknUWg_
zTS<>eoG3Ntq~z_d;8U68{X>9XlB^p9&g+uNbdA?bTG;=>3zDy1L3&p*#}YdCBt^AA
zbW5J!MeV*Mn$}kjBtKH(+Czzoa%&z*UT*;4vE-fEFxW4-{XM*RBYE)xnoiQap>WMv
zT1bhiE>gQqaLrXZ?+5^H_@7?E=`I}=kKTLWe`KQj&r@om<9uGy{8+GgOWC(k_(&Ji
z)6`e$KocH6=}#1u@t1~Hqqbif=mwPo(rt9SCRD17hKVp~D)}2O_4cKqln$f`Po%Vr
z=7&+zmsZd`g#SJdEYVUQH*_#Y+JaC8KJSF@;lZ0Y>DN}EIV?R*o3N?UfGX&uNf%Kl
zEnONt0c{!5WXk%>l>VqdktJ3A7gUudr^9ZJv?&Vy=1K3<GAmztoRWTzNl(%KQi0U>
zHtZHkN75y5Tw3l0vLdPUHwewe(vfT7X_@rSD;PW{wWDp`^U~K8WxpUzpd_Sn>87P9
zDx?~kTwIi@YoT&UdSV%V!^_e`V*tM*eOe8+tI`XU7I{tj{1n`-lGZ$g@VeBy2(=s1
zb~;m4EsgmW{?<q*(?(0J8UN`axZ5!sMA0GLJQ8eoq<8K@wNv_aK04DS9psF*yEqgL
z?rv%OH^ASQ)&)WHfz*a(zz?OlQ4l_oUa5rUW9hS0*nJ~?>I|WijCF;h&a$^p1MVU-
z`+?e3_Wc&Lxyj6TJ_X)gmJtXSJ!G*1pz0~BdjM`PS=5)PdCTHx9_}N1{vk+xWtY~X
z<|o@rYuqr|W*KP0Wh-dn5Fs0h8KpE*c93qvgR+OT`w}JdTMC1RWL?e>M$3YH;bE-I
z<v6J0WE;&4s)uF&Y=HTAncHmGJtAwOO}YfxKb;uoMA@<+0Fz|?1yDIHn>7<ZY>6z4
z9+MTaloRm2LFU;FVWZ5SW+Q#FkyWspAP<QJ*%`TSAIzVX2l+!-FF!+Jjz;-;Kft@>
zuJ&~QJ(7Qx2jC02Z4TIa<<=3@dy7Svfbh2XjCQ_5EM}y@e3Zqp9Z<=z2&Y7Y;}#n!
z`QeO3I3+vQTg<x#NAWp`2yl8RYH3R+L~)KL2r&vr3v?-65l9jA9K}r$D(4k%52NEX
z7ZmqK1L&h%VhyRkaxkS@2Pj3l)&rHf-2etF{ojYfdz3fx(Y9B)h(4RMPr36M+zwMN
zrDTF|<!lG2L?{n-LFJ%wHDz;0DOcFTV64)Ko}_WgarVF+R=!Wuq6Fm-OG<A%s+_PA
zjj77{H-OJjy8FT5EM@duaAzw!H=-?9*?j;e@|5GApe<jSN)c^jWYaBPu5`9XaZxE=
z!5~yB2ddC^P1%?Q6W5g$^fiiV<$qDETBXl4kku>SxdLI6a?S&&m|ZL_DQU{h^3^$1
zcUxBe2D_e?m1{8E{+4a@^a`{Lp(NT6%fgYs@3ZWCjFAnsd`U0k2+M*;G#$hr?az+*
zdu}~#6#bk|S$y;I=)pGsi;wW{1z-7qe_{9=V1MC0#J?APcbL-4evP7hiN#mKU}=eo
z*4;}jS^T|hC+%JS*6M)2m-h_=Y{h$-aAW0RTDtzOrv$9c-P_RHEv~fM-YVGxhHY9;
z{M+%{ufe(f08O@bx_^j&@6ymlyLlxIr!%9WV3`ZEWea^?)|II-0_n%ZP_}?SBfAOB
z0A|Jr)B+h>I_?n4Z2AZ)Va)2Ez#h*0iI}T2jVa#-ukx6|6n;O!Sd^es_#lG{!pn?T
zi2VPC<rw8*MzK>Ux9t!+=oI*(*;f>nk72va2Vg9gHCMya1h(#LNE6xh_d%G-j<12u
zG}fXRwRF}`g|-~ll|wC;{dEe8Ja!$WTIaKllp<Qh{v8NFF<VJ_rzhBb6jM9HX0C<#
zv+UJOz)RWsa%h&b{_Zea!S1y*1963&V}{OEHt#fCzsAaG(p1I1vV~49>qnV#H`%3o
zP^)7HQu^F&_8Eg(6WjDQeu`!`@jbv>*tq{@!R)THu-nO2Qp~f9y%vaWKVV}|Lim&&
zu?K)2wlEd&XRL)IrFXnym;MiSowxz(p!!7NLFZw6l(vs)a|D0-nam>qzhUxebevdA
zI?(9M*14c3F0B0!U|rd(Ik4u&&PYJv&I(p&+s!VZ0IdhxK&w|zcH(}(z1W}rd&{!*
zv=QUOn!W45=F5IE6-NEoP4t5FXCoiNU;vxv0G&`){S4lQu@|$@7S2vAMB5Q|dnYU<
zvQuv;|DTuIhXdgK&vO<)cb+rdyz?C!0bd|t;mg9r9>{+g=nNMYz26LmU)2<tSZvnP
z-uRM`BCsu8zXO0}O~c^PZ}(`QYWb8)AYGyHgnVTlElO8?LZO!5pMMC7KYLw)T3hlZ
zjQ#Uu5#(D7DT#dBrD2e}F>~pNt2<*3glsp{GmHAfteXUTfsBfhEP|Mi%r@{SnECu|
zAi|l+l<^$FtZIeJk<9TEa3P8j*FzY?>?AXX8Fw2L3Cyb=2#+#eH1|$r!joa?G80OV
z+)Ac_GB2($59rL+RVJA7p06?QtVXSdnJ@wHTTBM6shXK(2h1qDn6n%jdzdkW0KQ}<
z)<dU{Df<9yZ<xj7!R^d$9}Jo(w#N^`T($-4rvLZQd1k~vjxn~Qfhk}fuZCNN%#c3t
z9cO+upsk46OnHXIjFlX{I>Ah)L+U3P9j&p?GiC#=DlahiOMx$E#?r-6!OW)pt&2<!
z2`@3bol#t7R#UP`B{PG90xgV$qEoGmJLUbfF`oC)kNZp!1?(O$8XDsl%snI8dKov0
zY`CyFdGNxOb@&D<ZmbubCGlfVn<;tNpPjq_b_3XfWl%l9c7&k_We-in;D)hVYEZ<o
znZYn0$4;lE$YFL1&1~Y?Z&}z)W9#Yhn9lz332?{QM@<kGurB$qRLGW`1pGMr#b!8j
zmd&G7;8Hdu5`Z#x?(g*eJ;(Nw!7J=JiiTfhZ@&Y?HC7yr9#*l<pTp8Ec1Z==8rXM^
zpskUeL09T+c4Qygn%J*C!~k{CG=~;FuXSj<$1bAqP&eEABZ~X17cIRWu$Kn|{*b*)
zdtQ&&=IwO<KW2B*zSt91OOKzY>>rfk)5A851lu!q^LDuQoITPGM_;hN{*A8nvMkM}
zU$Uu{sJ&uOQu^y_HgYKdeXJj)e))0}D6kpEMbb1Ynj5$deM#WNpWsXeSG^a-S#H;F
zbiBNl8?+eSbaQE&Aa#~3+5pl>i95Zj(<Eoc!kLqjbyq-oSu%e*+;5Pmw}I`6q;@lk
zSCYv&|Mv)}l-gs%OnOuLiIUW$rIapn8~^zpy51sn4FglVG;SN{yQIHfgU$QWL*_N$
zcr4xF2i51&$xGn$OX;Q|sJ+2-1#E6I6@GyKu65x(O0bwO-UZ)6mpU{qTC4=kVr!aL
zFWr@k)<1t*iw^(Qq{H8vKBr~E=1@vb-tsG@xo$oFIZ#fFQ!cvW%>3$1#~Zzv7c>L#
zX0qsjLojn;9r*V!M@k_KXP73`BAAJb(H6&iMEf0wnE|xBnZo@2Bb-lV6vLsJ#<bL+
z4HLOXa3-Izr8ng<rZfcb0%m4E;DwCrIRM9*4L<Oth?$;GpLZ)}Vz)u(1at5W4K-6*
zisBUWFU<;0GrmaxmN0$u!F`6gKoS45%$CKdl`<=62eXXX_a`*ZF&~A1^gOd;B8m%4
zHiM#^*}5H$RxmtWL>HMJ+P=NSByEH6GSfx#adRbey%y3d%w#pHR~e6LICGO(wHHHI
z$Joumc-1rK46t;I`H*JG4b1Qkc+to_IRcdqCgE*x-(gy5vD(R01_O=<8bt^1GUwNT
z`W`by50-8QOA~rXETh$YI=f{V$a2l>Q95ps&(6IGngX`%B~*{IaY0Z$$%^wavL$TH
zQgo)24WbqQdA6hyzzWup0wkB&Nq3=gjjdS@z)ki9?K!ou|9ZeRCob(T1*G_+jitUu
zuyLDFM6$X9Ko7F9ATr~bI*I~?hgdl!jz+WVcEOPt)}A&ZV_DB~co)ac=3w(MI|Oe#
zJaxuRg_R?0|DV7muq{;pB(lTkL7c?Cpn3XHcDD+e$?Ta1Xr{0m(x92j8aq%+V_j@v
z2m?U5OZdFaoNZ{#WY@ffA<JVw{spy@?42mkoMIg*<a?f7^Dq3qzz(T}Gv(~|Ca6@f
z<0)(YI(ujx%->*hDPg>tJ(r1E4O?6S+->&LFVWE^_7WW#XlAEQ1FnU2r-*SYyPiVw
zZDw}$XJ~9^o!0}{!8(`2sXJ`aLb%w;{zAWB7yFcA#dq0ACD`t<v*{t-%{qPn&HL=h
ze6&4a#~nfOoLxfG+ZSwp68!CD@6ko{lHE?xlvk|y6vEeRNf|Wz*iR;*=x5Egd(gO>
zdpZ!~<-r}Jhh_j*-V9(MH=JU{2e?o=>>bKYZALAc>oGtjhC8zgfF!Oj0zMt(;%VNT
z#TC=eOE%Zo4$b3S1?8(2aT_Qsh&L=PkW0A|N*ylaCWk_^l9QS3QC{JGrU=zlF5)Vj
zy2eeUCutQYp&R--moyG-H@K)E*sbQ2^i_!(ZUH4y)^g{}P`Sw+oepQ}xPK^CSkKjW
zp}56e_d?OYg;T~#BbQtU_-!uk7|5Eq*;^rO<<6(m{!be>niiGqoUR1sJGd8<&|iF_
zlqN`bx$Cb{yT@5xgl0FlF&_B)oJ$vqM_lkc6py(Di^2Vb8x;f1K5maYy6q%6N-43<
z65~s>xky?`#Z{6)+c9pEor9t2F7ZmC_m8Kfmp*#pCE;gcXnZBoyKu%&k`xQ~{UrzK
z3Jj1;q8z|LiPI*uB}&dvXf{hSzX*WilA#n{I3w9YnO_x>1z8Z@l~ht*MZa`+2fXl<
z1=7g)$|lmv$zSGv0xJ7t&9~md{TC*S%z`vr_K_PbMaVv<uw<m{5N+fil)dTz=^@!V
zEgX)KHB&4rPFA1-X}s)1j+~KodqS8bn`{fxqp}}pRhBHvY631r)^G;hPLoYKg(6+%
zeG5f~><m6N@&8^ZZ<f;d&!0$3wgrD%z~aIR6)gR7@fUc%sG0Usf9?7jI*V_Ai@#S5
zc?5>vXN2M3e~es*fBz|TKxbp@r_lfB;sEe$8c#EY&CB=W?=4-eu(Y+w6@PEv)(?F*
z=0`gkduIN5So34dg-d8in6p-(31CcdC<2+^THt*UbFLp(NhqVFFjp8;Pj`4Y^Bz5s
z@Is<%Jd%m(0ChU!Qv_>yOn^JciWv4i;7XW8I!At<c}(lC%S_w|4AXU{I}bkAG0SJ5
z*33AX+u_Y!#&8GHXH1?Pq)u!V&1ZtxZrWXpW*M*lKegnY0T2W-(XQYPVxm6)G?e+N
z0njjJ?gY3T&Wxrl;s|EoXRsN^sOXU4Vdm+-C{mc%onTL8-Z~0E8e>iK!E~14_djgG
zf3r5T13D$l<aID{hB<K${i$H)(L3TI(@!_)4dxPs)~cEB#{=KUu*s<1X1?5j;b>xx
zrNiZB=G`B_a+J;1KqZ+C?WBu<&7Xq4rm~|epqa+H(n=(qT}q#k%3zBuQDm|;W=ioZ
zX9b$bH?kYvg~2Fp!9)~?xE-s|7R}{df{7UJ83((u+_Lx4nK*9FM6?~|ZVd%4o~xrn
zphq~z4NytoJZTUTxvkD{CW)Ix`!4~K(4lAxl>A1EL}cR7i#1p>c8eJu-6Oe1vC9xi
zaW<UVE9s@JxqXr{OcSL0B@qe;4@hP-Ko}}<rrh{2$*mt@H(WBD<`wQT|L>{yGK-C{
zn<^`|LoG|zL38q4S+*?z`Le`U=)`f^sSKzT%c5vabW(O{E2UYUmW|+{`b;+A091YD
zwehf&EFYwYuuQ(|7-|>f>;Hup*X2_t{@<LhlO0U?9o=kjHoSbq&Y|t`9`-E7B6`_u
z3M_eWcGdLe#~-0*Dhz(LHW?%Goui0<&q%upFK5clb`X6p((+~2kQ5Bc4;wb4VYag#
z{{C2X7~o&(W`T6k7rkix^>^CUTb$mBe=mtU4EfTrQ{cd|X+Hw>*U1t1_v-5=SpUa=
zKK$QwI0ia9?$M_wc9u{YxI42Dd0bc*&Y<^^hne}Q7E({<A6j5}F@dywlgy}!0mx>|
zr=U~7B+#bUNv85Ew3RZs5fD}|?^>g{%4iGVdJQw2R*4NvZ#`;l%mNG4?lB7|pr<{|
zg0sN&F%xXi=E~*|2hNK%{r2A+1>-No(eb${CM`x{Y9(EWn<W<L_jAT=BfNOQc)Sam
zSIn?+Abrhbqyqnjc}9nJoY-yOLg>nR3D9(7xeH*z!hZ)Wd9o`Tp|XelG9APrY(GuT
zQ&{y%)QZ^EEpPqz)0i=pnodEs8g?3`IM=eFx50Rm-SGdFcKuOJ-B+CVeaROJM6=Z5
zTHEQ0=$yby0wh4)sufUMKoQWX-O|S+VrD`jA>x^C*tJSmTTiv<?VJjFjz5mNwcV`Q
zv{F}xwmnw5p<6fFqM)o={82S(!RbEN?f;%r3Gdu@f8X!-B;OzReqS;a{m~_ybD{N#
z_#s#L`h<HTB>yd9{H)q}G2%Gl`a=AeKe`viJl-x}66u^F`AY163g!pI<D7MUQC%?z
zuv#_!5vJFwkws`@v-;dh=ryiWx1e4BTdk$?`s%8Zz66%8DMh@@jVZmnRlBbAG^1%Z
z6enk8ZYr7iAfnk-cbn~93ZE~Dp>EiHS?uI>?K<(dcc8vr9OJzbi3BFLhykuIwTiU?
zU|Yl+%Qz3ZRSdfT(Ou$~Zn)nqUdw^T9^u=BnD>eWx8Uh5(cA~@pcv0}z&3I2COjPx
z7h^DURCG3=k2=KXcYu8)>|B%iml(-YZI{^81!JFxK_7^picbFWk<WyWpY-n*Z&dO+
z^pyCN4_TfTCpzK2M;sgu&?|EITU4)ztvcLa6&HD_dQD7Q&Rrt<Hp1a`(e`Z+Z;B-$
zNDc^<2irmM>RDjVsZD%%<$1N>QHZpvJGuC~TTSBQY44~X^D+N_sEs#Ztg%}?&2zv7
zbq(+8VroknnEz3CeF)JNraLVNhD@iPfYIHi&C`IjnLO`7vcu%;L)g8ho!cRK!?bc3
ztgSNl@}RZOY~y11Z_I;h5Ytxk96n~e(|mF<h#RHBX_C#-!FlGEM!AZ!^{w*pL39n0
z?py-fEhjz<utyH(vF~^CS3EGhDQ|xaY@Zx42T?@j5(5f<lK;dkWj-Je@Hq0e)H4uT
zn@s;44iCxYT*dseOtwP(uxxq|>VJ_o8}!=cm~s%`myMlm(D+aucoK0Rm#gO?m=0Oa
z#{)WL*Ovc}c2hRApvR|n@n(El#rGidWC}ll_tbC8K`Cy35iyh$@dvo{&IYJXfAuoB
zGgcpmR@qTZedd`a1>Ewb1893iA4gd^emv|n&ichFgf-j7h3y{=J`d43*E(Th?ub7?
zblwLwF#WX3$60=I&W0F0UvfI<ney|X=)10iQZ?b{kTmx5BV5&gKLZP1g|kHSlX>Q^
z>1xIOg4<kr_SIP+`O~>MxL-Jf!1d40+=Lhd#(FSnw`~9^*f|A8LnUX>O^Y7tMksZw
zuHZggHV*WLNoBZST9XI*v&xtvG~@*(mIoV$lqBRq;!5J<;?%e)bnFYoJyEL+d+WlQ
zq1X9?VXYu&L;~L0`mi>0cEwaJ9MTQ1r{1dvw8@i7GbZbG)t-`Ib;R%Wln3Y6H|TX<
z%IjBN&($V{LVlm2*ZYFCVXeHPB+EHDQstdiP?)KQLfYhDZT(%Vg@)f33VXGXKT_j^
zB)xJ;DI68hjbPZ7?QvxC%V~FJ+4CG(4wuuV)dz$AFg<%g8FOzw8o$nmrq=~BYJ;`j
z46k10(|omtKT_?D`=$*uf`QC%J^lk(P6Itbt(TOXZy1Dz*cbR}?>!iL?UM3?ukGz<
z>SbknFFi2dl27|vEs2!2M%rlNg80!?{FO{3`w8(~vYj<QOnn`4IBhOfrO8tgUKpKm
zLgfC8w)7-C8a+~~2E%lDalDE4q$Z7Ss(V+(Wx|D@+I&}z{C?Apei_}-A3qSIHT^QB
z>2Oa%^l;C8FEkU~FNe~hqsj5qjeLL9(~#(yN#D8^pF*AEEMud}2Z=l8P{TaSkmzTr
zNe2sy?)43<6?m&6H55n_57BoDERvpyB&9{WeMx`4VVhcB=$SRCxUz6muKn&`W%PAD
zdB}UwfpL}*6X^O@la-FYpO{7Q!;@0zRELz&h4U>VmnP&noEZ+6-5y<g+A{3EQ4XU@
zcj?tG-EMd1I-I&a+v(0VoJNk}sB*eo?xrK>Ex3k6kDMRsdP3~ILbubci<Jo!$*@jW
z3aFjIFnS;ppqji4UZS@cG?Q7gP8Y}GX_jU!RZO%Es4|*j42r4H4rYG>t+#_&OlN^A
z%P7YIV4@Wa(&;3FVoGxY)Ki4PGHM49*G5rF78Kz!i_zcHK1Tgy&StY;(yVNt8)+L*
zC7EJOJ$9RlazLFx>vBMCrn3OzRx-I<)>5(8LMs8`=cEhV3QBW>`?if1yFo3cc1HUj
zq?BBs739rj?jy7hsOW!$WFE)`RGA0ziIKFOQ9s3iDo;~kzID7(MvL;TspgccO57Ft
zHExvzI+$-AYc4)*iOZ%p)2;W@t$eFhSx%P6tYgJT=g9S#b&UDUXlvZIyX^l0RWZ%L

delta 126876
zcmXtg2Ur!y_cnX$mfQQ)B=#iM*jqIA9%G^=YSd`#CdOD2OEkGCf{K6$s3;1eNG}44
zG)0P1tsqEI5fB6c8#WO6-ox+z`S|SYoH_4%&dlANa%PqjZ^kyg8SCDesq*h4vOWJ)
zY}chVPh@xb24naC|1pfLysu!#Fl<dn&W;gD6<fqe<X2)@J4PaX+)9c3`2dj}!%8Q{
zBge`g7s>6!66xCYe^J@zED0s*I>t_t-$ia`$8@(7gl`0~%Fa%tWqPRexb3LYc%BkX
zw3Sv!0Tn~b&Q2nhNu;u$MU0(TFO`}PrlaUHnbahojhj#9?K)yl5i2#^UnsK^cjTm|
z?#H40DgVEsJ&f?bn?Ob(?fm*Jbh;}4C*f35{+|wFJF!A7l`(S8PRwegCZV_Ia`Au;
z<CcnHdyJu7Rq{W;X~rn+u-r3J+({umETA}uu}C}h_AC~!XA(W9N`^6op7xUdOn_&!
z#9%9EliEq`F7K4!dhfmr*DszhxTd6#WXI1UTw|MgTxYh};o7r-bmq2E>5w~w4YN^c
z^9quigIHYuxFX=XErqVmztOej6zTW;gRZ%?B$0T~eY|ZP0h)@$xcY>)s~#Y_!{3sz
zUnOMVmr+#OGMps;wvs~`m+0y{mh^W86T`rGLJi(Pk_T4O_kBt7v8(C6Ig;+DPap=7
znXrqOk!IXM8+oy{h<q2lBV*;oq<X%MRQ=YI#JHVQTSrr?oVv>4>bj38ic3ke*LBkA
z@HI&$O`!Ydxn$D+Ptq@XO8kHIqEbnF8w~o2BtNVmov9~9HYCDGGJk&>(G7S*hVT3*
z$93smx*8fuviktR(uWaj_r>;l>?OCVRuXpE3A!J+l$<*{o=S&oA*|A$P+TkBXO1DA
z2s|)ov;A}(n91AO@Jl}+Pis<0$v={m_F4$$Q9)Nn6_uLb5~=kIg6(i6N0SdyUB`AI
zdHzdk`~y#^mJOZB35VWPTJxABzaAu=Y-i%%7Ehd=yO8|tHt^W&{=G|prPrxA>LMB7
z`jO<b7i8wv6uPh8N(S6x2)v}6YW!|CIU2iyN)LZdnmzS&J$i~XgYwAyq*=r^c_7_a
z&Z24r-5~w1Pm_FF9l2#&Ur2z0wN&tj3;DJ2Di!Q_OiEX~kr~e!bnRV7k}2!yez}(D
z*5r`BQwMTrMgy6NJVBE0ZjsJczNFJ{I=PkI-s~y+NpgK1RrQ~}#8zyJBh|-2MDcny
zIZ+r*lBTKT*6T)+JYGljHu=&0to}st`VzTV&|Z(Np=5Y!Z=&1Kk9g7)WU`o=*KW>c
zx|YnN>u0Y>bJ%veKho}~&0-_EFLY!q<Qn;Y?IzuKzePT-YOlxg7Sb8Lh|Dt@GPCkB
z5$QZgbHzC-o!tJ`Oz|eSe!EH6|B}d+%k6zbb~D{y>qMG2%jkZP7wHV~kkj*jQA>s!
z{fI91cPh>pNInjaAtydYQ0=qEl1ZOxGQXs~-uY_MS^onO6?@Qqk7aaC>P$L?N9j5w
zjo6}=5HsgZ3`^VJh(&j(jeYSF;`tw?Ce=I3N%es%sVaXZ)ni*pa<40quG5j^t(r=Q
z>>!7(O(lxGFX_JLQ@ZCrlBTM*ovjbu?~#yx?^VRprGVt!9+T$kI=b4(uFcM?o|I(v
zBs%$k%=itVdiNKRq%fOc`46e-Zo5!v&X+`eA%#dIl~ntOQqsKdLib(sNPe)KI6MBY
zKYc;>VRB;lZ#%X0;X}lKp@{Bnju=|-HeV<3a&J;qE~5KR&#Cxe5Siph)3v)3nfYQ1
z$<Kd5X4W;)Gx7EZl6<A7>&r#NR=ta^<Go0KwT9%G$z*<1B(;|3Ff!l#jH;1mvnPs@
z4kT*%nMCWI$$b1Vk{k*k$;9@qhR-LH3wWYlbdgGLaa3BBK?d4p(N#Q+bbeb*I;XFY
z$w5`5v)YZWArFapg_3ltPLSOUwT&|V8uE1FH4;55ru*n{0)NW2d)-X6KX!wzTX#|E
z&OfQ0Cg#xn@eHcdy6;GH%1`80@IK;P-kEfgvPtKjJ?T7tNAjYv<lIjisI=+~PtX66
zT=H%aLrN`oiDFR=-H%Emle0c2*rBadzpy-#kL^kN-fA-W<8Csb>_$3IyVKQW0+nu_
zOm&_4BcWETCV6dd!XEpJIN9$=GIEKGo`3rnMD)`!5^df@u=_ueYEvqK`;I10XTGQV
z@F8TZZYR}X_F>X*{)O7CPbV_jx|QxHw)ZGE!-?mwQN*LSC;o%&@5{*?x<3?1Snn-B
z+3bot6RA%)8E_s-*WpT1+8;#M#;J6je2xt8!-!7(fXw?ENK-tAhzehj{7L(3xo`v-
zzC5?R<v!5;=B3o4)<#0bw)c--RfK(ik~nR#QAF|UIRb1*pt|l!q~d7_WVphM<jw6w
zv#QC=S8W9A_%)FZSxfpmHj#eS&!k^6p7gJtYi~tIx_{q3E*uk+=CI}DL|_i_lrA7t
zwQVRBY+gll%S6<GM-~(K(+wn9=uQ-4`cVu0GmYdfiFA$rgyg#R0Y=yUaDDiiczRu-
z>%{|PW=#T_nfe{wKix!?H0~m7@P8yfv5XjgTVo^YH(JU#i|p)Vb`#AckzukWvx`?t
zaP6^?B{_aMncbUEa%<-yG45wZ^SIjU<hWXXpxTe|rnV{YB>m|_h_khQX7#51X(*`?
zL2f9cN_H+HC+59J|1Yysza-M(?cHt3Q@UrhbX_MV)gC6IwqiCcvuj&JwUJn;HkmDC
zKw2n+{M94UZ@5SIQ%8{I#)ahKnVICYq7OOR{TnLXeS})*`=_X)opCt&f0<pNFR2DC
zrQahgkqnG#pHz+QK+PrIO{K@zlRR=5fjf4fYvpTdq0-0X%2qtvFpSx-%&ut$nH+zT
zQ03^PWp=&tsou8-QH|r;pN0bg#2m8_6|>oGY=82ncu=z+2@$BoPRjio0fVX+f1p9t
z^QCZ2Bc>UW&TY8le;QWxYP8Ph4wUWHt~a62Ke(U!(`o4aIPDEefBMS-_wx=ogL}UH
zT(B(o`V%<+^GteVmlrs&c>h=TqtR$XAw2_ITWET1yZk964vf=yIOxJWzl!7t^OWW#
zM;V`IsE0SR@+xx2m^FVRInMYz0nCSKnGd5UnQqTu)t8ALinj4%?w$es6!ZHe81`ot
z--YIB=AWf-^$fGxiJrdz<|7N~S;oYHJCJ$43rP@jfyT#RX5e>V3t?6c1a~O2cp?B{
z%=8^-m~bYn8r%`gHtOCZnRQ7Zjba8TL3oZae1=>!BfSDIVwe#J0FPx90?N)am2RNE
zz|5|o`F9-io@R3wnSAQX<C#&1z?Q(Ih9H;7yv%_4BxXk-@X3rh48luHCiTOY8SQa6
zlfrawf%jLK)zo37GTvd(Ok-xAg!yzPIReRT<~Z5C!<68OljbvCi_z8vOrN82wEtbE
z!xbP3nZB3dX))6{58Ne8MLK|`Oe^(&Wz6S&kUV0t>S3^w38q=tV<yEJfEq?Yqs|lN
z*$^~vJu~tQa1G3q4-h_MHrIpfIkTVzReHfZUjyMwrl1+gE9Pt^%-Wim7fC35%~Vf<
z^bON_4iImd$<L8{#~k?ro;EY%U%+4s<KKjeeqhweC~IT>px<|wNZ$ozyG8$az{3Ng
z<83_b<NxQosh=4fG6j(Jo2YO8^Y{fA+TcF}W;Z6U$Ni=$V{KSGlX};no>2MfIW6G&
zAN0X>z>mWqANUED;nG1Y4P>X7j#%Z9x=i942y@caPw|4uy6gd${QXPre^e5`9%u>K
zcAC1&OFO|DyE6h3Zh{Q40y5Sm?iaZJWsm80c>f)kp7hY~VRmDnknLl*OQ`aGW)$Xq
zGG}HUR{qih%#7}Mw|$wbGzs=&)|W%&Epui(TyAB0&?M7Q6t@JL&Y~w%;LKssHkwc!
z6Dj?W^Ajz0gSSzlldFMC5iM{8E>|@8E!OK8fANOT+kk=&<NknFmtH@D?yFIIAs?L~
zg65o)1L5BvAOFPFh0)94LLk#?C3KUSuXmu5H<;e%(E&9vHOK$2@%gZYAk?hIAR_C%
z<u)3u&jJiCvc7dY(HHfL{Fk*8eMK=3nXUiwQK;I09Tn)d1`Za`PJ`Y&gwum(okYVA
zNuCQohB~Cdk71H9{L;hcr{FqbD@|`k7SR-F!n{2woh}@QW3zkF7_-=`J9O4mP6E%y
z$}dp5ZIur4T}-$uDz}g6xf$G^Oy~DB|2fLA^xmIlE=rL^FpuRRjbk><huiT?yY~r9
zyZebuyZ=c{dj*o2_8MGb$ZJ^|(_WEuhHBFOEAxFnpb?DDMYvi+$(N2NL*R9nxe4&J
zhu^<w&o6A2&(M&4m;8w9fEgY@4k|$3Egf<CcQ`ZpZXP6KVt#{16Dt?P_i2M@q4k|i
z3c5KHZQ}o#GEct+%1<}+LAF~S4e34C?!<M-(XU{9jPV-e)3(y`b<WT9M%pvZG#}r^
z<k`GHw42$!7+G&-)LW1rV|XXHcAQD1S;1*$<4$m#VFF$O7{HvtAcwy03E`rc&tJjr
zIp(1XD)G!;Re&cj#&BpRGSL(W$Y4^o18|jD5eLm{%*P;9rGU9eZ~0wj;T@W-6*49L
zfUjn{x&l$dSg0~jm_sV4zF|tQ0{@oT+5-mPG1K=z=p?$?5t@5N^IKqWpD54(;SrJa
z6C_7P9}k1fTa=Rz?*m1Do(5TvXuzK+3l>%X2wa?~X**Odiqij<;P;OgS(0JmnrLee
zATmXT^t0U*#kC<R61jDU@V@9v`pq7Q6h8r9AzFSOjaw}eFa}GXidL!6TyI40H=-`~
z;<`UU<|sBP0dNslI78D_tiu>A^%mbK1?MsG=C05T5HJ0Q=D%mf3%>;-T6`o6mSV(9
z)_^os{PRrU)5M)I`EP%kItNVzs9W<>WV;XVhkEzO-X{BB+4yOg5J@KldcxMk)k(OY
zva15u)dkG|J&PU6=b`>Rw=M^1pQFXNel@xmt^;kEUBEHqO=tKwyazpbUl*>0<Qu0N
zwD-8#GvV;W59^`&tw@6FToVRu>7q1R;H`*$gVJ>_6LJ0X%a>r-q$x%nl4R91FHV*{
z-3OzWWXootC_^@uDwZSbCPmpD*|a^dRV=ghP=YB>9=-&sujDnOptFmc(1yAm;to!L
z>Uq_eWC)W~x8B0?Ax-UU<h(QwF8trKAITIvgJZ?aKQ3Up&-{wmtMmag6N4K@EC&;W
z6->+tJa3guhae<gqQp!XJ1n{#PV<kWqIWdW@)ms-kL0+hx($x`h;-B<Cq>KOAn_IH
z(m``dwDu?D{6+5)pm|0#YAPxoAc}B<mls5<qLIXjMr)vXThx3QUfdBa&4$kfB41j}
z-WC0F7q}wP+7+;HPxOLfcD53c+5?`JiuTbHdS5gv233C`+FA(Ja#00E@g9k48j!0L
zjrkp<RU#J(lU9rP_oz&b==L}WYemJsfvrw7u@WrxqNxJ`Xb^Qe3u=3D_J1hbC0<pE
z#6kR;8fcH$b3VLxvWb^GgExD{b7?XkEFMg6a)`KYHSl-D=i`yf7keX0EWIn{%3-ij
zTono7J@H~%gcghIC~i?Ient!OGVwbs>7)<D)>VK%6zi$?st^xdf<~wm2L~bdSiGhm
zaMj}cWRN`(+guBftrcg{sQgs?$wqM3i#d8!8pVxAk$WZ%Xo2br@l+FNUW#oLoof<D
z(Q@*&c%Ub8Z^izvQMGsC?ldYii!a>=u0@<r^=%dVD53dLTtcJUF3E)iRCl*z=6VPn
zCC_c|fpC(j&cfh6$xlV7=zdAjAE?Cv2_FW7E)pwsU~Uq>4`4ee`KbiJLy~7c(Daa~
zcEG%sBuN9!!;(+GLD^BsmjjV_OH{J~@R4}MLgj>H7sd8`CFw=*!cU^7y7)`RJhY+k
zv}8^koH{F6<PI+aCCd}wez2t9Hn<idDRTlMOfqN;5aANrP~;*dJv)IdN@Au+O0=Z!
z7~o<glg2=JUJ`p3kH7`VUv~kBmsBi+GYOKN13;D}@reLDSt9BRmCKUPwJiF-6v>El
zs9~x^`7H`D(q;jXA?d-xi>s0kGy}_&_}_srOA?;}%^b-H3*63?m{=s&CGKOOazo;X
zZ4T)z$-*&Uxh+}l1!wXl4+@}CAQ^K96)coY9SN2qNt+RXVoCTBtbe5?5?2aLmq~h6
zBDpV_v=1~7C9*bDtz5F5R-l!VTh~ETB}sEYQY~@o50x6pf5k9SE1B^ngmsdD5+n_h
zG8!KnB@;KGNuEmvYQXYBlJ_sDUrEAR;eC_j@O_lMk#uth!1h+M{4cP*mu#H~)n-ZZ
zb&!6LOk0QcYLyH)108$mN?LU6l3uC-&_UYpGidfmZ*+lcPSWb{(UyCqCKK%Lm+qGX
z=PcdCfyG7oBM(hi>7GTfa8SyW!h*YW`2yfPq-irC^t4I$Cqn0lbjwtjI4bq6g27|b
z;!6-7mmVGu?i12|-JyC?8gLkRKk36XH1H|ujNwo@Ew$0k$r<S@YT&cd-Nyh3lxCbm
zE=0;rhow;ITnjYArG`LgMo5>Wz{4o1jur;zq_$4<cEn0w)q?xHv>T0<anb<=pt&er
z_5gMhq{k^boG1<b9(I$ZZ}OpXN&0RJ@F~)yqkvzLK0gLwk@U|a$la6jv{)&X4j%_x
znRIItoOvMq@>`TWls=7w@R77<AmA0!Z*8=PQYBr?puHYTZ&BQ-M%tCe+$U0H4m`D&
zHKiiiC5!t8LI+v>Z}4f4EPxjLPO_sT0N5*gPou|vnR^y2Im>#?1h=cKKSj^nWE&}d
zbx7tyqnd|oe>w~umfd6lI3jDdr}xiW)^-mKbxgK06*@k$trX)sA-hN`w_CEH(a7DF
zmHiCO0@<ZX<nGFr&4W)xvKe0ka8Gt&KXN6q0-Cv(%G~=y^S;d17r6(rv!mc|xy&j@
z?vd<I3Jg`sh8aLzCEF27@#kvU`f(twk%g^94Qpjxqu^ql?9&YZ*2}WzL$yI>$%dup
zvOP2gzmWOHfTl_IA_utFvb8bLd?z#i1~1;rwmw7I2U*=()UZ|Nf~bSEO_oZ*CVTmy
zCRo@l|M@1$9OT*WX#E!{??BQhd8a0rh?ZAPfQcCSs$*a~FSlJl17DE)(|*cDc>;w^
z;^pov>?X>;-2$2<`J>Muyd*D3LGH5r{cMz7k=NvbGgV$rGuL$auRlU1L*5n*;WfF}
zJqR=93n<=c%a(ij!)}gz><JX+$**DuReD|iYA_7ml)t3d|1J4=8anRCPmM<|Uw)q+
z#Jh6$AxH}49}$9(-jgrGo~g80ZV{vLO69gU@V-o*MVkN*<UO(1Dt#!gSpe4_$>&an
z-3s}&2H1PtL%wVuvej~q!u+-Jn%mU)^1Zb0*dTv19l}QWJkJ4L47MPO9KDebodnr?
z`8)?`G|OWtblWQbk>2-@^4=3+)}D150pTuoDh2Z$*q*iUY!7=Y1lFC{%w!~cS@+KY
z*w5~{3D2C_^;8EJ*7GmmT-lAONDi`}I78E&9lir_5B9t*5(rQB+7%>+*$fA?$PxBQ
zB790?{~e2Zrn7&IM{<n~{tLoPHlJd=Iqa7df6QfLGhpdD>-h?#H`qow4BleveuD5e
z`)(4*^4ZR`3M^o69|cPhTSpsa_t<_k?Jr>+mmyLmEoFzg!~6sG*E7_jY#VJXR<I5y
zKw8O05cgwtZ8gfOS*a87PuQMg!ClKfquIt&w%=n^rk)KBg@=vozcT?q9DV>)Ua<3K
zA$iH}s76^6JF)@Zzh;$FA$-SfIYcw{_v{b9!(a>hf?|sw*p!}NYh#nvA+hHM)5LH$
zmz{~61Gi}oxE;An+Dvxhp64Rj$9?IKO6=zjZH6-kxOuN&!i8J%7>>GeZifIr$Zc5!
z%|l#+6LKD0FCVZR<_hf@yeUVxysNP5&CR0d{4s7fEjvzdT@t}|l3RiObm=MXaWPc<
zx%fNCo#7&Pp)vv7lmfUN$nn&L1##IFstDoItB?!jO1^{_;ancg$|AT&Jd!A`um-|&
z+-d41W4Y?D;f3uy*W+h!$8mLaNG@{xT2!Wx8$cn^Vy*}E1tpwQI`CzjOC*x}+>SZ0
z`;hDZ6&x++Mqvpqt>i`y0IrIgM02}pZrV2BYPh|#z*)<EL!)0Ew{Q%E4cv+WP-*1S
zqmX-H<C>{Qdda=c1ip#8J{8Gp?h*qR-*S&?k-XzVC!=aD++Z^Qf%|R|YVnaPjss~M
z_t!bVckw4(!M2;vxC!n({P${<Ir8B>K(?3v=?YZ#@qGe;bLOq3&^*BRd<7L(-Zs!4
zI&OR!ZH&6}tu&oG#Q$lJLQnqsw*Y$az6$|7!n<jqa+Lq^Bmgmd_qh<p^3SM$y1-j<
z&|Go6YAO7U=l$2giv<2}dSjCKxe}Bm^JWArq?h@@E?`OFEBXSS${(~Hfu%J5(C^4*
z@CrQ;SNWK6P|f5=Q^-DxAJ7P&a`>KWK$^?<pNrfLUPsHio4f~YB;Vnie@9t9KQ|k~
zyL>tAp%n7Bzk;QEe1sXlK{3DO7g#9e_tKVM8UJS`R37rnIw4XcE$3&^u6qUFL`&65
zK8E%qAM=qkb*bhL)ggJpS1pCGmY=s5G*9{DI0)<c7YKe!8+m`)czMP@nGLcRd_^$I
zUh;oY<fMteSPx6D`5iNnyyNZmBYDs79RzzV{H1y^-oFog70n1f@{h`aXya4$u(V59
zk__Q)L8FKJ$AuVLkN61kDZrl;(tm@Buke6|@>7C!B)sq!RM9YhMyR4WWq|OWHV^`Z
z>tZB9!jc52gb4q3MJ`lmqh&$3pcy5?`xhY$y#Y&6!p1bPof9f(9UCKz<6$XQaHUn?
z1>wQhP>B;}bc5Y^VQw7in;@`d_?eP~&3BL_3(md}rU=dhpm|03g4S(m!eokRrVF1O
zLGGH+heoPQ!QzKpwy<*!?AdaJEHV7f6K<_U_PX%5FLE~pzii}g328Kp+!1;_2Wh^r
zl79QU!Wnnq3x(aKD7z<I-;G?c@bXjON`+}OK$i(6&rsh7!UPI0KNLE}0{2MpFM~4`
zLd;T7R|%gShue>B!uL0!QzO(;6z_@PW&*xWP|!B*Qz0q>Nvm)y2yBjuH7k&KC^BeH
z>8ZHw0-wATeMZ9kVTDfxk|T;UuOU3Dh^An(w_;>A0LK)M4KV1Vh@xoc35B~3UYu0C
zqmIp2VKXPf4L`*%<jpC?vcUlQE4ubT?zH00Wmr0^Sn?i-K*fJ1co?GCb_#5vitukC
z%u}pxg35J82kKvMC>-boxTy%HZuXX9!yqKL6)w$4?kKAML6WbK(CAR0IAca~SHaq_
z;FlIEMk@d;QdG=EEy@)R9E6V)*Q-(cDuq4_$rD8r1;=U?3AEQ;rx>sk$x}t=UNB#;
z=#q=1L6P{E3^wq;a{vWjyIy_-NVj?S(7@eqCqvR>_HESR^VQ4X?H6adLvH)B3!Mt+
z*>nJWy<Spd^q!Lnr9RtfHPttR&JXlcR>H5Z{ICZk?O((|f54LopcvSz5Tt|RDabrH
zdK^$grj3XG&}~;xfng)-VPN=wUXYAPSP8a~|D4D5>;86N8#RM=QAXSBDJ(i>M;@+Y
zhtt8NaW4a)G=4J$^(XA?1J#NCN8#3t`fnhgUzdaX)k}uK<hGP77}(87sC#y0Hd>K8
z&b-n=&5zkL8;k)=<{uD-Fq7#gjAT?d<v`=Vv;4DzP&**E#Zf=%BG=x4X;*nY%_rRC
zEDe4K<yv=?xy!FpeB_XP4Mo{J<O^sz;wi5`3=h2IX%tyFET6Lz!Xxr(6Eu&?pVlMs
zmNy=QQ6Kp{4LDE8yY`3BPyRd2+D^%D((Ke<?qZ`>I4yUgh5K3gj^BX@l+XGPz6HtO
zhNCQ4o;MR^A@ccyk%Y=W{S{t>$;(#4Zn!+XBS<6Uya-98d;sl-M9K4M3*nsHeIta?
z@-Hdk7b8zz3}LK%xdax@%XbS%F37)ep_M|M{41JkT$GP~4Qaf*4~<X>@<p^LNR;!N
z;7pQy<WcyYEH80^PnYBomr!<DKJgur6#21u2-D=_sh!g0CLJ8jkpGv9va52xu@GL9
zZypN^nexCBa3)Ls;W^A^%LkvLl|rsOZx~GE$$zCC+3WJat7!EbazkI>Z^}EB0C-D2
zS_zul^3`8M<&OM09jCb~pFyOBauda(i{#VkAjduVUG%D$G6&OXs1kW>cW9Q%Z&3uN
zOnyWL&inFiFJS(Gd<a-<m_a|^i6$+V?;4C+Jd%5M15Jh8oqqdDxv3m9Rq}L-`8}5Z
zOk4QX@{}&HTO+?t%bq9lu4K1X9-RQvI(a26;hxIhP~+Fj2aG^jgS>%G$2H2!%VGYR
zTz3S?b9t{c*t5Nm52CRBOL^~a;KeKXE;BrBl7Hq3;A{DJ=`i?4E^C1Bt$apTs5Hx;
zR3K@Qd(&CMkMdi`pxGwx*$7g5_E95*yVzD5${g9IR8a3_EnZ0WvHvpAbY@#u0)BuE
zZG?)8jXiw^g|4iGHaOkbh19YKS(d`g?(FPUAU(v+rb)90TU3vnC%gO+@Lue2dV~(M
zTmL}rD7%ot4&H1mxps`rN{1zXwqym8(`>vad^*FP{04vksGxz)vWgwh3}kIh0$MhR
z<=#Rkn2l6}CWNh^J;zXXHATb1SidOv6wZ2Ifo25jYXLrz&DsQ&D0Yw-!gH*BFp_9C
z^?L|o*pNivVp+%0$em|rtpn!;_71Hy;@C(!DRq%uLlKR5R%7E)wFI{L3_ML_x4nXD
z5<8D(9?9(Rp}=2achb!8GMgNXvK00>MHH{FccYL?Wow7RQX1<_NAl9y@s23VVBNoj
zGuK!@+N;lGca8&D7JGLyRI=H>vDb#>%VY|B=d%8VHoR4NY=4UWU1!G)hQS-GGr4$^
zeY6C^TdYqbRBp3-Cd1MlcC|CO^VvA+kPFyu(?EKceb5z2A={TaiX!&MJaFG*ODlmZ
zW{rO%DPh}a-BQZ-n+wh|_D}<Uiu-KpTG}ak!2WCxPam>Rj4)r$j`9ZgBeo?TG!^VH
ziqcfF9(16iie0q@nvYqj5}MVl?>XdZ*cJ-EJz>2&LbH}FPlGdc>^~P^=_#x2hO&Bg
z7cCqbSciPrZDg&~u+P}m=Qx2Nea_CK`N#|Q={X=?vJs0w`ih<4nfjHX_jWo-dX#I~
ziK642`3)-J!@1M`*a@zLg2E@cx74xua^HCLH`u;j0~bznS82=Z3^(HvJPF`B_eOG-
z`(!DSK(6l^Bte|pa{La#+$$5nA>0`1zC*d9127%N<(xrTBv*0}NfcK=yOZZQZztrU
zx$o$aj^WmHLk(iN9Vd}H&+T!Cy$jq%+bqz;aWiRC=pwhD-rabvI|UaLIPc+5P2_Gq
zg@;L87EKM3xrsD+xy042g-@5cH(^LpxPe80U*Sd%Lz2oZqA7hEcP|v0>D;i%NHVxj
zFT<IuTnY`v*SJydL7mA>9gl5aX%<&_5x{INONQpj;Wo#j&2qWX)SKpU88kd!=O)q7
zksI7xIu~)1yPgS0Z*iUxpt;Sh8iAkc4p%rI-1%HGg@OyXHVQf1<-T-;W+BH?=&Xoq
zBF=l9M<-|&b4S)tXI{c>S__&|?k1hkEaRLGp-%U?iV;9O;QpnV#Y3*(8hk3}&V7sA
zBd%r-e5&H6Qi$a-caf$^)!b5wD%Nm&CIR<^D~Sb5E$1~8Ds|kq^w>S+LTE#-o}2Lq
zxdyHkv11#Sb&vZ1_>9Y^lWxzsnie2laG#{0PA|Eh$xwa8S?B;^6SuSsxz}7hO|;)|
zeP%=WmP`B;r0+P#;mEz`rmE3~&0L!iUbJvuEJxV~uEQuaNh^0V2k?*FES%KAGB9#J
zJha*K|I(6g7eC_!NO$v@A&@%oU1>?ahZnq|>d4!>fz*i~GY2$#`HiQcxsQJsgKF>R
zM+QODnb*)-_y8Y5hge+rh*fAxSH8*(2Hp6)L;w!*)joi`^V?}p;SisF9ykvh-|IW5
zdh)Ai!hM9VS`JG``QYs+^yY{CfZQ?OI~K`te%TZ_<HPIe6yOQoQv-u1`9L=$zWlf!
zA@t){e22z6#ozi0aDV>vI^<6C<Naab3_sZdmH>VSEfdc2mna?=$lG>|g54l~Af4?F
z=6g*;4tv9NDm9cZqiK5>f3`RL4(BHgK`w%Cp!G>4Ka<|EC|*M+;m+~HV~~sHkK?oy
z7P^k-;AkvAo2D`6`N3t#UEuvEBNxXj#{+(m521i`JU`Y(tGfjLkC$*Uk$>_Vq)EK%
zcOXsX6V5_-iC0BHc$q&#r&&^XTOG=-@cFblOXX{qfHaN2G6K1D-kpNK8T<~4FJI+5
z{|igk_;q3MDU<K^4oMb&{y3b;=39f2%i))Fpw2v(xBU$hH~3TZ1m5JED7t=&*DXUs
z-R1|=yLpFi9S+TWey<Uh3ix6g`S0=#bZEJdzv=>mMZ8)8;XVF`Rsf3mjbk7z;U^a&
zDdk%O;7l2BrKR3|UX+EpJmA-b3V8n>^42EQqMZM26@ZWUEeB9o!Ox<zw3Ymy_;f>B
z#n0aa;bZ>Si_om*17Coqh95i$Do^<DW1&*Zr*uYH9e<cY?oWBm0+7}7>~>VCfgeIU
z!;QRgIdaeVfMrOY^Syj%GWCKFp(9r>`AKw+>=plr`ran~6>WOI=4%w7dBYDM4D)aK
zHadR(j<2Q2)_Yz>U2roWun>S2enuwBKJdS+fv}aYF~W<F{J9yZeH;H~5n9GxI7=3G
z3HzLp+b#GpuwZi#I#H*)N9Yg-yrU3Bad9WX`z-A46^7nHZl7>49f<wH1KI#{5mYMy
za1~s?N6t;iq2Sjc;T%n$JcMjo<9P~0Xm8<&(1)I<qXJ8ZQoV)2^n>~cjrjaUdP3-T
z5`dF7!EHOzQ^G}>r27lY=!=HaLd<Hk&{-iZ7r8*83!NMe5<b!nMW~QV8(CpOP7H+M
zLP9-EL<m+2tVIenkHH-!B+wG!obVl;;*S<M`bA=dt-rw0SYh8OXr32zXTfqo_|Zz+
zCUL^I6wSFPh$&<rFPskqB0=~w5=o+PH49})!o1h8lq`IpLra$g^9AHC3sb7$c8X9~
z3zaK^^?NjMsv!4VIIN@XJ#F?}6DosYFH@K?0Bw*Zgu4TsEgYH(J2`@qB5=7v_Ypwn
z3I9<Ceq9K<3z8c`5zWtT3Yql5!!6<1X1J0sT$_Ykf$(l3lDop_^`I^k4j+J_BB3*#
zySgV#rQP6Sp}@8p_!1$ERwkuFs1-V8!o*=Pcwe|ngVF=x2l|}mq0plocFTpKeZcle
z$gKmQLKwdn{#FWON}yRK+#3YkW8utja8?W9ejuw6exa?5CqfII$Ey{*PXbUUyrH%0
zQ(?3~VXAt;auTEsLiZ#{8-;<#0emLxdkEok;YW(xy%1*8r2eJQK*Q!M!NCB7O+pDh
z#;=7&8n@mE{bm9FR=DbfvUkGjFX7>PVf1DInuRB{5^52!v4qE8X!b-|tB@5f!<+q4
z*wz6J)h3L)0ycXEwjuHSD-5)=uv_t}8D)-&6|E3DDY6=2Vy~hv{Y?85^VR{dU-6ta
z7M&Hn27&v4V(|pvTolQ4u*y|YNNa01#bOy$4k{u$!WnmklN-z*Qat(F4sW)H;wA-{
zJQaBhfbdc{e*n#4g@IP|M-**OVfUzF&ru}aiY5JF_n2ZMEiR8MLMB4!qj1##enOG)
z0K$`s(KL<rRjgSIGCzg0C%iwU5DPHxuh=vcZFpJ{zZ@!O6v-5uw*@GQ>EO*-#b<P`
zAW)G_(a0c0b~Orv72p33VTfYN_plVIxL^mL!W6Sg00>tIv{xIUIIsztk&6Cw{xC{0
zV>*QA6lrR(L@VSwVJSvY(*e%JDrQlr{=A}q!loA$_dY`|-lk}!y_W>Vh*uy@RAgR4
zlBAeGQKw|ZsO_M+q_~j}yO$L`qQI7-=vNN5D+<F}G-9fvlRw~T3TN71NmmrRqbx(=
zGzccHDzs+-xTe@R5J{$@tRDbbif<B8maS-}X;hBF_WTR@ovZM^37R~G9dTb*4F3tL
zHxzF<n7^r*N!z)%6o*~m#chQ`3)k)_hOS1EuPF3@zXgf}9A!h)=|~$i3l&c;qpV2L
zl?J+diu+%~V6kHR7O0dcX3*@WRPp%?Bo7o#w$t$Yq2j|MsFo`R{feYg(NlrKD#iM4
zD0{4ErY`J>qB#sc)hZSSp{!2v3yoq8ig|y*V56c#GH}lnOKGR;r6Oq-48BsBW1-ok
z2&K;8wc=0ep57>wdgR_JCeW<6Ss`h%LA6EkVi9OQC{~)F)2c`p!O}+sM>DQA#T^N}
zuvf02IPWf{&t>FxD>u`-?Vzj<gWWyKh)#ezD);UJz)4v~vxL3MK<cjcDYq4()%Gh7
zHiFYxnf@MS2b3v}U~y6Yno9=?T$Q&d678le{|xwpO6S>Nb60LT15Xbre<+3t52b%O
z5S~ioK&W^r#dM0~urh|eI6I;oya}X7l>;a|?X6rq49PL&h(^@@xN@yC;6BQ5I-7Aq
zIrbAICzZw^2z`~m^rn&3Pnk$#%qe99y*d8MJX*7zR?eZVm@~=&bC3&AcBSp5v&y=!
zz#XXUMjxC7DHqW3w_xSzN;n##oJ2<)LzPd@(mSHOJsK+EN=N!BB9y-kLRqA;_B}MC
zlzKYW6{CDh9jYx>`6qR{=av6_3xgMxr(U9>@yfO2Q-U%i25gDS(X=c~Qo1HUGg+B?
z4cwQMb)8UlS@}tSc#)zUrw8teGHokJQ<d=_0Z3DJ>jg{c%10Ew%24Kz!K=zIX!&(b
z`5A4xWZIO=hXS9ad=iQzTRH495IM@JbOI??IlmRaJf*rLEL~TY)5gvX<x-0C-BkWI
z4{W!TrIBE}txW3ypYACC9t>Q*a?)rd1<D=gP<B`8Xb;UoWrPEMv?8VBS+LwwUZbWg
zRoZ-L%ePEfLC@8F<sY<F_CWbS0^vjDi=Uxdt~943sZ?Ir2G^>TOnXRHdG#9D8kG~a
zq887TaXB#mT)BmYu@_4BVz9ha%IS-cSIS9r!lX%=_Yx|vl^dR*4c{oo^gt!vDu1wT
zf*bFYs|*0XSDvPTO0%-{FXUR3^|YG$pe)9*RB5ZSaU_zD${+8etWBwY5A*h_q+kGc
zsaEfTrQNE&6XA@5YB)tm_o&8Euji<G^E-r2s_-9>>{a=?pl172mnDGjSA8s_gNe?n
z?>9s0qVnks8duebK_GQgrF!lfW3VNSL&igOW<4t5sfwkuU|y=AAK=Sj)#nsDIHHP|
z1ASEW^<Y@=R_W=$)G?L+ItY)eKBdo3d{j;y!E!=%idyodY6MN|eO0w`aQdl)CGhi<
zs)4@$@K@POkUOpVo!;y-sx%vYZxx`*qj}p|)sz`P1get8!OsxY>Ny|{RUPw1E=<+!
zA$$r~UHAkl5vrv|03ua|55X3t8bE8RbE<!7S`)3hN9W;URBO7zi&)iO9Bam@y=W2K
zzMvZM6kf!slr+L!R7Ll*0UxijeF15Ls&y%xNmMPQ;6RdUAazX1s;@(Vzod$yLG-ff
zDh07pRIzl9@`|d0f)S~zsr1vOsaDYDZn`RzJ{`?a*$2SHRn;;#z^|z~(E2b_^-CFA
zElc$+gR*RuB$&35b5ubCfyh;r)03O0YNf&Ox@snE)ZI{pc!Bh$s?Y#OZ>i47;nQtZ
zY6LXzsDAhdj^?Z8kB6{8CEX9<UDe>FFj1&FlM7stYFZY^?y1Z)J1<ea_zzx`s@~Gk
zs4`XVWDfn)ebq30@gaSna--8S4^{Sk;9I$>!!@WrQuX^5)vi#v^@TH)s!KFpR;i}H
zMeecc9<6d~RK44`IaG>{5Z0<3CIV2WTJ{z!PgN2P0QIV+6nAJ)g;V6QQFW4z#XVEq
z>j}8+x$0*+pZ-F1hMMN3YK0wguT}0e`o2;9NrTc`RZA(#-l=vt!teJg34OlVton<N
zr?se*)8Y09)rAo-*s9XIf%Kzl#uC)NO%)T2#9qCQTFpWIl0FsOqt21RCr7p24H$B=
zsgE;A_o}zOgNysrvuX2jzxomdubtIvmY_}t)ZJ82aZzh%cfeKsLj+XZ)E+cLJ){=X
zYSBYoa1ma3s=IE4PhRTihcIzi{bNUP9#Om8g7B#NGR^zE)#v8Ii(~4{KqSZ2Hb?47
zebjqDfbE3(9|}L5R4>~FgTCrhbuj3sE^`3zl-glA?E0(ys4Y&b6KQICM!g<~)}#UI
zmGrQjRl8DrJW##rbEpKVQ~ZDnR!`XvvJmyFZ=e~fo=Arn!_>>Efx^|DY?EO(LS1wc
zI+5xuYN#mnuJ@ohr_MPD6VYllt(0QaJZ*!-s*ifZ-}7pDErb`;KhVT4PJPuAfQ#w^
zdOYIQ1zs?ppq}(II1|;=XTY_j|M_%T{UwXC6t$@p)K}EY194<rnyOy30@*b6dz$~H
zt4DqXnhdpRFSxI&PmP78Yw9QyOk}B>mx3)@ozN3r<funbXPK*Zp;O3t>PKO~T~{lo
zLGz~i^c3W7sY{*F2)EVlp96PCok-tE=Br~U&QYKqKAFS&SELp$!qa=|k+i%hRx5e}
zU!vwa15v6@M669(ramwZ?R8(x)3?<R)II}|JXFWf_Exz%ZZRBvq@F>WU=`}!NdQ!;
zi>pCarB1E`^<(wgDbTD|&!YanMxA{S)KAnhYz5k+wd(V<9bBi5q~GwV`d13p*Q-x-
z0KP#Tb{|QjdObD>rO(vA)`I)F`Xj~1U#KU(fKPAKyco{BRf{Mp_D;R%DTMFUGpK=@
z)k8ahtVOM)ImZWesUvFEs-8!2osViIeOGI1Q%@p<y=Ku#__j;4p0+A>YiiO_=%C@~
zLEfXurzyx@&29Q_WuN9t9I}w^*HqGk#96bQW}yc(Pg~%jizbPt5U!fvpF-%SS-Ako
zL5(2=4dkIQ&VVzXn(h=H_tJExbD@WAnm1xdk7&j;AUUcT*bAiInz22gb4*io00xh1
zM$7@JkEV_6p3wN#A~~t)PNDl#nuE0A?60Y1Av~>d4h7(h=2#7K0h&1%ket=*)8aP>
z)Y$)xDg|jiTLfIN=D{i03(?rhp8y}KX?g=`n8xodY7wc~cMqyjn(#ZwozpCv29;<{
zKE=^uG@Gc~iq$L<p=Hi%KGKHC1<lg$;cuMA!55krH9>=*60h+-54RIEi}s)_QDaX>
zX_7QoD?pvB(awNRDVp6j+JU>G`8EX&oT~YS&K{&`V%8y-uGuex`3z0Z4X}GvGjtTV
zuW6=4p)6CALC3;#GzMA+<!U@>6DLn|XFABPYgRpm@P=klID|Jf*V6#FrP(tZZE;((
z`g_>Dqv=d5@O+K!2Ca_^G<TXHy{nmf8Yb>(PEnkuSTnT%IwhK?v{PBCIoKEYGR@pA
zFmYcK{x6aTnx#?z9%|easA#!nc?)olG+wk7RH4BM9=r#dO#0TcT4SQuw?@<9DsWFU
z<*5MFYF>Av^>LlX?i{$EYI10cvtAQ;1O^*4J%f;I)F|oX#WT&E4-h`rJYNjb7aEfq
zG%q!C9>DEan%~!eyGg@mLikqmfxg&$rzxS`{`Z;zGhwM&6BZ4!7LB_U!Vj838OXJ2
z6jnM$^-(jPra*0)#i8(GxAsSxDLQCfw?k)-_M0v!bJSMT2<@cpMeF*#S~X4j_i4kQ
zplrYP%2!C7wZ1fyIiOul5m6WIp<58TYA=hCbJu#&L6bw;t&#BFL%XO5UU+J=IRI>4
zTBmPe_ptWuTp*5Uuh91SQSIAU=y+?BuK<5cJA@wH<Jy%p6Y|mia~CSUS_6H>=BEv%
z4Y*U<zbN41ubuD+Wv8_sRrp=cXrI$EEI{ks9m!ekE_z1-wZrIGL6Eky2=HK=HogJv
z6{3Ae6O?f6;){?*Xe|#QjMQe+=n|z3^Z@rc?Hn30qqY2Tn26DqF9KVvc9ac1o!4&i
zN7XKB*U%g!Ub~EfI0;&Z*<eZ3ekcb#N&6}X!es5NyU1PA_J0oQ%UWAG%{WuEiF6|8
ziuU_eNK&=eCD2LJE^A+AYgLm$b4@!X7fGh}Bdy}HwDbDGV76BIACesH&}OjYYWofY
zE>A1!1lO)>y{5t74Q=6PsM1aC%wZ7T(oUuRB44}t3UUS7xwZ(j>|JfII<!flR?-c*
zBJIC)2JW7AJB7-NwI}FrFqCLj2f$XUWoZB^(|Udfz<sU13uqo_FVXq=N7@@|I8&kB
zvKH`4?NC~GRcW_+0QXp{y@8}!J3$LTjW%-!sGn$ixzjPmTCJAOmDX#A%tD(qXh+cJ
zyN%j>nx#F{&g~7A=i1e~k$a(?GzBy-wb4q{_m%bwcL18S*Mb0etqriC?2Wd7&fLA#
zUZEN`YZEC%-l8p}Xz2&-O$XpwwI$n7_EGCJgWkV3?I-o%w%1*!7igF6SBhos)>-I>
zb<q7c2X)$`%Tu7tQP-a)FZ*>H=L7Goi{fGafNmx&$X#@=i(uDPcYOokZn}C6R1WDT
zE{0tX-A#&Sc<MrWLB&hwM&EcG);0f0e{kZ6E+Yieqq?obz~-&{uo9}rbVvIDe_S_a
zKJ5DF5^teNPv}O`n{!fklD4>fb^rbX*Zg!UI!|;;H-pxj{<=;N!F^iyH_cnm=+v~(
z3(zgOjoew?Sc=dG>bB8TF-W&D1&J+Kx1Np{h3JAa0SwjE=7BU!$5GrpTz5zVVT5k<
zGyo%Y5?>&qbkTHt_?&LaWVjZsdre{V7~O6fFk^L&O8`Hwi&etW3%Ug=z~gkw#{zIs
z7xM^Jir4w|LRo@t&JnnsXw%7PU6iETw+>0NZUL>CF6pea*1D{7?*+CLot747S9Jf-
z=0&Qm|Ie_LrVAMhm2};&w3(Kn8|jBiT-C)ZA-txG_#WJux=cF7m8H8*U$JECKIsg2
zj!xJLK(5Xu6J>ci+i2=cuIonmqrNwE$<sk|Q@3juOx)64ru~uIx>5=N-qFcuk(96V
znv1dmUB`Dw?&>^BV5v~|>v7<UbUF)!_jFTyfh*Q|Uqr4%w<-+qQr!=<$z7(KPJeCS
zzAl|!!w0%58__(}bvS`+xo-9?IP*xiWHNLrbYIbSdZljGRH#(xE<Xe5W1WJA-)dd0
z4*)f~0d!`hPUlFc(x2)E&{rk(y5FndQ-iJp9nEjl9isl?nQrk|B+qr7=!EhMT~GRk
z{H5;cS2X^;(v@hz)}(7AzhCRRUxL9mx?F1Rx4OA>n)scrE1mg%uUkX2hi2W&Lttys
zB~FLI4?4vesI=;qYzOy8-4;98ZPPudM}6(}g-ZN(yYy!%Jhodum%c%8(EmVRc<#|B
z+UOXgqy9C`2c7iMA{6e`XSWA`_2T=W*{`pt1*x;Xp$zx~`kV>y!bQKl7c^b<espTW
zO|RJu_(6Rcoq=%IM^mdG(t8huqaONj`a>C>`hx=?^wPW1H07|~H5Kq9`do10gEM^{
zb?@H#5DKpy({HC$-EsYJIyCO1_ux^r6Z!z^VNUA3cR<Bgzljc@`RQ-GM{-KPpE??U
z{XRMbbXp&L2)Q%*pQye8`tJUKpVfc-6U`i`Kjw#Aklt|`a>4puodCCm=x5NjY^c5m
zeFYb$m(i;lt{+5uY7u%Hot=u*`#XXyN<ZWy%FgL0Q3FTo#dG0kjJ}?>Rb%xno6#2M
z_20b$_XYj(?nvVF2X6v?QUB8kScuoZ?0{T?{)>}<C+angfG64XiD}?Y)~6~!b4mY<
zj=5geFKI=RqOU9k@QVI;IuPmlq)H$%^eG46+Esl6P3f=cMWw)H>T~IES(d&Jjpf<;
z`*h?aN1q^oI#<8yAK1;)kD*xVb$$51puV9W*cqHR^|p>zk-ep#Ukv<heGYw#a7Vw3
z*3$WUp5j{t`nuC-w!8Yl3xFupub~gji}WtDp>j_jItVJodcVJrE77;LB3G&(dJkTd
z>G#pNd0)RV7j8e$Z)<?R5B2|ji(I+haSQA{(%0B#AzPu(qBTUN-rfRyl|Ho&K0Vf-
zUjR$hdPnMlYxLngK>9>~iFUth_5aeL<U0MQ(|~)b|Ba55)$5(;kVAw1yf<=<dNaO2
zmp;?qi-H%=_5J&U`h~uO7LD*yKdK)rywZQnqLU9z`p9ok_*%~fB6*{q7YpHAy`&FR
z-|2H{0{C8kjF#ff`aWMkrA6P1rt}~55rOc&Rey96R6gpboPymped9;u><ywjFtN+<
zlN4U;HjKOkfP-Nqo#5JI`0FBYj)var@dqcQPKHod=<GF2qLte|!*QBn?>D3m0FARj
zIRZ2X45@`M?_wyS;FqhxfkNhP1|RBl4;rRTMdEHaLG!>v26a5hJPaehgNmnNB^^=o
zGF<wAvcrbnYmpo=$bLjS9W{ib&$UUt4d4F()nkU0`_Yys3^CLPo;0lb49@r(IxA4-
zXV^f89#0v1b;WPsZ^#dY@U+4D65MADJUvhWhCbWj#aY8D1-JtZ$7jNeAj2SvKm;4=
zKY`s4!?>-$g&Ky^1R>1ePCGHSa6^+7IuV9@6ljVx{BjAoC_{(G&^c%5PKRHj4QW*E
z7(+H4!HG4bQ$+W?p$E-$FBqOg0}yAZrB=IW_=M)I@rJMiND>UreW96XxS>N?lA(Vt
zDwu4zz#_S1a8e?<Y%|O(Lz-gP6bscWhItE-q#80m!cv;S$qW<ehVD*a%P>rT1I??3
znbbjDGX&9gSf;_l3P6^@_cVT=Yy(Fj^BjW*#UpYJ!9J)`o?+G3Fn`^!llEb67)CAw
z%T2?x-@tOqV7nQC^tNFTeYAha@ZdiH^9|qUL$$zgrW>ku*C5G4;};s@a!^)eu%pvU
z_Y61&ffvu<Osn-01HS~$lo}SihOo?Vkb;x<4Q2F{Juocxg=-HDH8im=H-u?n{*j@E
z_P;6&n{8K-RvOj@!qX~448@`z8ysnSsM^q52VjjM?+RRdg6A2ewT5T3ZC+=1Mh76C
z8v4-3Z1skJn_<4eu%#aWjfT$}p!v)&ZWUCX8_e~feqmTc+tx1)E7wEwjp6Qe)a<Qc
z##kHh?+k-Iq59s?F$smu1`pa3Y%x5g!-pRX5(+l78dmf|?xSH79l~xiJfe}--ngL%
zmDy$VT94dr<GOudaWKyCKyHt5-e#C^G)|$|jFa&zI)1v>c<&jU*=G!yiCXVB_BGNU
z9C0@KXTjkEM)frmx)>+YkqK909sTVfH{*_n$Q?8$QortQ>_E;OGESsz8V_R~jY^)z
zofJy*GP)f@*<oXG0n8sUb`L{x)Oe7#vAvC(=E2}G<ANWddEB^^f`mRsH%vHf(i6sb
zdPz<iwG?ykH5%if<7bR1Mnz8<S2?51-?;HC*iIX#9fpTzj7}6}4=_e#fcvcRFFO1Z
zXgqNPnn6Z61)+kC|2zdti19=RSPC_I(2x^md>I0jaO1|Gz!G81rCFgZ(&#~78AchG
z&`){J_#^EiMjIXX!kHN30U7MZ8n=HB;d!G>1kDS^ixi@XGhUz>%|&B$I@sckZ~H?f
z!I;n&xI|;jLim(qto{co$;SI50Jvnl_Z#4sjlD=E#W*q<fGaj*ZBO`?YRuh)!ZhPx
z`W`afSnG;hhOs9d>c48dNa6Ks#t%QCGMPrN1yIQ{MpIlo+qnNMeuEt21V4C@YaIC{
zaCydcegIrIj_wEQ8^+<Zs=8^c`2j6+%NTMBoVSg_1PJdKZQoG9DBsw!2GRoKwJ7M^
zHRg#?c+VK%2}{LB&ueIe5~IHY4wo96@1d;BShyeN?;F=Fg7ATHAuTK(8dK=GDmVT|
zE4D{QIn5d>j5*ujQ>Brk=zNt?v=+F>#&3qgP_;43HU_{N<F{8)_{5l64DMQ^Y7`3V
zjA!Y)ou@{v3smZjn=Sy@V4OP-Y>mcubd>R#ajq}Ce{Sp-3cw5FAGE{w(kP;p^(*5n
z5y+a1_rC+nYa>Hv0NxlY&jbF}c-<c!zBBG%Y~X%x^#2KL%|?|gaxKP-6pZ~~yi8mB
zt;RxntUnruQ!Uzzi)amDZ<1P(+hwwiMSXXhHqud12h&j#4DK=2y+fI!X=MuRI+;3f
zu(a2daRAi&OiP}CdcWxe9i4MF?frpH{v9xN^M(5^romDGT}?%sq3ULOUJAPhP0MT`
zbvMmxMsmnB{wml!Oz&y0+0&G?4Juxy56v)t*p%Z9;StlUa&R9tc_zZVx9KBwY{yIo
zX}x>gwBr#}d`yFB!g<29cmVA`oHX^KZr0cI+kTkvGu?fI+$qzN3&8uE?8N|{HjQkL
z>zVG-pYaJW4X2RQSyN^cl0eguelQVaO0`2Jf=xfswr+^23w24MrZHBigqa#ABNuL(
z-xVqmrjK+mKGO6f{T)zSlxgB}AkLY_(fU5x^g{}CVobN^f;852A{4^&rpH~Ndckyx
zc8lUnaj&6r(bVHt2op^?zaU96xl%kn+0>~7WtU7f)FoXu#i@{_n7*MO?TYEzD>Q7X
ziOoQghDyMTbel;v18IiIY=IY7O?`#{f6eqOMT#;_#RULnnI6}{{cO|x&dBAM`tC-{
z<eFqOe&(4R<{@|8)Rzv+-7q=R374CuMvDC3GVNFo*KV8CTTyn$R6`M$eA7fL%omsf
zwxaB=$(B#6*g})*9RQ0=7W$g)p2>9-xQk6?K0uV1rqVjB)HLA$%F0Yx$#CtyY1d(x
zcwoBP6}X3{X*pmiH&y(C=6Ym0yb`zy)0e-(Zl&oH9)K#-_q3RNY<jj6D%GX{TJzVK
zcG_q)`NY(HF%Y#T^B>67nWoWd@~P<p#qR1&g*=i5Q|A~U8co3kAbn<fxCYKVH~sV)
zUc4}kdIG>p6W0L^^vZPG2P#b_j{<PMHchAA<BcilOH|^m=>Ux*?@YdQVEetvm`hK0
zv*~;_OthGW(TS4}rmyMLTC1s?VqhOl{zstFX6h1wGJEs;%_!St9zPv4yUn%FVcx+!
z-i+KH^I<j09L>Mb1jEVPa~=SD&BHFk(mr!pA<XYLCoV<K*}NbI{vI%ky3zROV*YwD
zfUf5M{y^epUP0@jgJ#QJAl%K}?}Pi0`68W%^)NT2q0G}fnAW6T<`f#J51YTKgz$*@
zG5y`YqvrX2V8Ywn_zmF4%ws70bHe=DDOBR5d94mPUvu170Qi|R8|V*?oHD1<tLkqq
zph&`LGj?w=#+i4nfZYIdZ3x)Tn*Dnt2{cCrfF{ViL53Ozo3GfTxkJnw=725KoTvgk
z%-p*OCc@3TSu|dRIp|L$k!By-9*#1<z5$kV=AVsVi8k+D4GXpya}ss4v1TtXIDFom
zxev(&^Je;jE6#kV2>6TUg)&%*H$SIEOM>~68AuY%UbGZXGIQ9)lqQ>9+@W&G{IV0c
zFPqP$A(vvl&<d3+=9z1eq?%9s07Gf!sBn0ZZg$@ZT!ziuk^#1><~$0FUo&TX4ZE4<
zm9Z$yGIu<LT(;S|0c<(uPbo;BYvyv`cb>T<7`W@^dS7^W!+gRK+&9g^6d1c@t{MR^
zZkzklU&pv(Zrp?B$~OmefrSF|eA+O)YySNP0EK4TYU;g;%)y7DbI%-l2?mSJ-6{TA
zVveHiyi&8<FECMN4$A`KzB!JL)jlvc2f+M8a}5on<z|<c@ad7cV;#sU%vUeNQl<It
za{yGC|Day$vDq~bW!2`GUy;<9*JPvYiCJu$2@|#EIZBwQGpn8h_|*J?f}-{2F0|}z
zFn1jQOO58waUfXw%)EaOa?i~RXh-OUIXD-ZFU=E2z~5KqBAVGZnG-&sxnG;Z#Yo<m
z_tIy+Z_TDj@bH~^?|j&OZyq@wfM)Zc!Q@+u*^7fyAI;HAk!v$gqc4f=Ed`&##4bzT
zdEj?j`qQyD2g|!Q7~EsQ8VRqOr4L2RoGgo^Al+-(vmU~ImM7DZ+i&SlGYV&mGzTgN
zELpE$(8ZEZ=e}Gmm1d~8Sw@6W{PUn?;z*cqxBRyZI)^OoKfntQOU!80*VAG?2fw{6
zsuRc^wydEQ?h(r<4qhC!d`%lA-j*1eJRGy66#{qM67?CX?PK|zy4e$!83H&@T7IF^
zYrdA=9bnhbl1HDdp0aG8MEei^mKj-~Ic+&jM-$Fi6m--p!1DVBBxfzFz5sWiWl0e5
zL6(GmNP;cCbha$Sa?1!nsO8Q^_!MSgsMiX&bd;kk!jhVUB+{~i=IK$EWF9`9v#i?=
z&1g&Kzk!RfEI0+BE!OhL0S$HDvULEwxM1n$gu*z>qp#uqMT-|jyW=gX+rgG#`OpS@
zqQx{3xg^Vj<4BS%3uhp?WRcL}yUUi@w30}%e5Zxx6-yRvGo@PghQU&rW%^Bcm~I(I
z!JrJw_)k!F)n@tW0BU&6a^xJ$XIf%-&}3PT^#)D0<$4j!=UDze2w|?pTmegYmSg^4
zyKY%a^}S*FKr^YEmemPRxn;TLj@)g_Z*r8~vAk_XbLCsMZ$nvu<&(3(-L>4JV*`bj
z?ewW<k;QY?GNbLoVW3Jasdr$l%yK>e;QN-KIdGxek`xZ3k1S`tgwqw4Ejv+GY5BSt
zj8&GfN5DO{^t_KouD0x;zN*IZ4;>MFV$sr|S!;PgQ}#MbL^*O#Ezg$0g?dYlH<AX+
z0Xo~)XlZHxqo>a-lgq*V+|o)PB)qVQ=>+Rbi|=xfzOtlJOry!-eHm@_+Tub_${WiI
z`tIYcr9}&8-dTFkC#>%+-_ZVIv!yG=v05xwXaW7fQs{-G)so@@gC8wLK2T}1jG}Sb
z-a7qH8%TFq&r)D^x3wz^FC45%M%dkBo&6C&N9$BNn(kz+&qLMrS~HHqwSCt5wJ6(f
z-AJbdoUMiQo*b}#u^pr?)-AN9=4!3$4NGp;8+6|3pmmS}7Tm34w;(xW4WqZ*!#emh
zoqqSU&X$4A%evDB?!(qT3z0iw4W9~{qgEpw#rL*O{S0i!teyXYYsan86(IGo{xKVN
zPgp1IfXYeh7;0``Yrpg0_Ol9K0C38>j<%-#t=WH~?6lQm1I(YX&ZvTg0Bh?I`ugOo
zbq;mofz~Q&iy-SX+5`x;cBNh_#Ok;aNvL%Yo!ASr{<<ET;nuv>;Eu3*PC*iBolPgD
zqO2|R;r%&lPzX#!Tl+7AFvfcR9XMmH9Bp)+x6X1y8(y$>qdl=W>(=Xl+b&w83sD$v
z{pJ?33D!*&C`_~(=^S2?wfq@`$=0lmuzSh6F%hJftpWA0lwuv*6F#L`=XV4=-CCaw
zw==AHv!HU-dLj=h*R0Zma3<4wjZOe%SqIWvo^8EC!OI+Lc@8vlZPpWe;bNZk^J=u^
zb*qSuV&1S8+y~;OwZsC4Z&`CG^mN<$CGCgau`)McH{W_mKvH1cPeFyd)^(2Xu+X~a
z|8aEPaamSh+(lN7a%A!Dz4xj#D@*fdmRY7{HcYc+Wj3wMmnnjXAR-Eg3=tFoMfMU<
zWC{oZvbTtAWDog$Pk)`yx%Zs!Irs8D_qq3+b01tGQe_*R4eWciVQ)jP+P3~74A$6|
zG((}*_TGP6Nn1Bs9_nqaGTOj2*t*b}tkJe238GE58>yhX*_OQnqi?bOoYGLOwm*$S
zqs{i;^%z>at(Hz$_ia~En!m$#>^+bNwk`%VcG}LZfZGpkjg*J&vMsw0(rw%R97vC?
zT{c8|ZJk}f_1QLC(}C7+TS~VD25e)u!_uHFYYfgjvVG?^K!<E!oP>wNwi>Fl9I-vM
z5`ClSgEM2c`J_H>Yp;aC3ET1@NKV?i3Go-1vi(JcK}_4Wn87`^ee+ouoUsj~9lssp
zUpiykGuVGq4#I&E{}ra&k#T?y*-i`#?Ngl@a=I>am=Vzp4HrfP<=~Gn=5)e+S4Jge
zqudx}R1J8P@i-YG?u>-p=sU(ZNg-no#>P7UJI=U5FA7ga{z^FN#b8q*&<V!dUqHm0
z5p#%QpeGptRC(mXI7ex_Qw$s0<ohzVQMlzaqtqUro?*OAuNFUs_7y1lGY<R!E`ZVU
z4#-)?b&A^sG9Jh=CFdBQo&^`g@TONoFr)4$d^*o~ic&9Oj3czGzra`)3ND;6?n5!q
z2u2@e<}Wg4Sn%x<gKdILBqJydW4g?+{jcPY@d54kq8S6n;9(4da|j|=7(SoCwX2Np
zD5D?CSn2@o8Y7QVFL4ZKdeOu){M&(&z>t26#zaOX#j%nY_v=BD8I6>Av8FIK-ve4I
zL-i$K(ilAyl1yhjUIxVshR=GC>x|ze@Gz6H{~o3!i}6eb2Aa+Io+j}IBb5>pHyO5c
z$j)Kxa);zC#>_>S&t(*BhKW4JU5fMPGaUQ@UBGag3$Bo%rd6xR%DAHgz0LTi03$4B
zh%Z8;gwd`7b}2*rC;IL%st3?l#@NV#rE<om=V9V5;~^y&Di|L07*;a+%b{1rm}!QI
zdyLZml5mV`R7X_9_-YkMEyIQm4t0#Wdm!};9n~#1FswJc(AmiNlp?@Q3<hN;ni;Rr
zg{v0E{YS9d%8+$~v@x>Iz*0M7-iNSzpV86|(!tQs8Q}q=Z5_Byh8xvgJ!Cv3!E|>q
z*3-MDn{l7^Yds7b0k~d<cLqfI7!@XP{S2EOG>QSn*gtS;kg@S!SbD^8c^=LTF?95k
zA7(tU7<NY(Pg05EC?lBCz+;S_P2k2EvyTC0g0buv+@55_P^4jsA#;JqG-H;x?)&A|
zvoxXhOpgp0a9}Q^<-(EKzXMJjW(H8S(uJv{^VJb1gEj}Q%**uvabtG<i77bB+(O|M
zcjl?p&^yMwLa9m*W;jKfk2C9OUOky77Q#O-=Bth9JHgyTr)Y1ch@SJ4%nIvi`02wu
zLto%J#e9=Kvf|71qTlFgrkajBXP7DUp!zXys^N@3Q}G@Q1~C8n3nFKkZK)uE%<s>`
z#5v}fSSSQBKU)ojU?zJK3L(tPpFkm$In)8}JTr`{MZ%cB)0%aG+46wSxZ%u28PJGe
zZltaDMdlL`aOM(o#fOlIWIm<}n#;_0=};ZTOr@iJG_#ayd}5d%qDsc*3UeoYujVSV
zpSGp3%-cC2*O(VC!<jgyV+SPTnH?0fOkn;(0m($Bk^+iJOwX5SkDbiypkHMQ(~G`t
zl*(+TU}qZh+z=YmnOj?cmch)7gW`3jBV|=Gnc3suvY5;1dv@8(`?S2>U`|cL?VHT!
z=}?`+RLut1E#@~fu$0S;{T3*BOk3I`<ukXu3XuY)8;UTjHigUzdZde(bLb^{o9RI1
z2*peh8;T`NiyI7<GIQyWdWTv4KZuku>wbi#a^_o92zr;feHIidn93bMsbqHk4UsCQ
zW)=GGG1FSWRWpC4OItO}xnDx0mie&+Tpd$I!7OV%lc~gb8<?JS<+YLdES(0Ln0BS$
znwhDD-GVWJYh^mD1zH<(>=9tvne{o)d%&#TipEZ+uRX{^=0ralyO<fxK<Q?t(2evS
zrtSOa>t(u7XsnO<{u2=CXZCKz1Pxf3^LK+CWOiSH#v|r?<&YU-ezpxR4l_+u?lHnN
zCSdkPnV-^+ZH&3~G|Z1Pr`Divf*D0Ynn`BLyAYXTHe$<UGtFet_Wv<+Eyb;7m=4YW
zvtz|P0I_HNQ~{qHSRHhhaAa9y*T6R?)~+Xk?aZ2d42{FA5vm<?VXdRb@Ca)`K8P#p
zlmEe>8%szpm7}aFC%Em-y7vaqj<H1LQ1D=7nZX@rwQwQg$(r2(XS`S;O>pf5tCoVv
z-mDf%{hefe&w?{PtlzD)Up>XzLV<2y)<7*xoMwGM%hVaxy%d1@v6j(K-k){X1+E3K
z)LUWqENkpDU<b0AuVM7(SY_*=7sSHr9S<IB4JD{TSj!DC5y}dneD8Tyjud)ftU!9G
zF0h_k2<UKD1#b7^!DHQ`%8-k!kF(*$C01WC%tx|pK840*RwrFuh+@Ujvl-2*rLw~q
zR@h7M=?W{2vUOKk7FttcSz~ix_Zn;d7)TsTPy)<&)|bApl)&m*3PXvktU^d8vFhG~
zUNY<5GO968VO^t*YAUOmVlQbdHf7|}S+jM}$Y33!@m^=GeFJ@&tY>MR%VOnG?MgO_
zK}FLyShsed@g^&Q%7}7Uo9U%+i!~n)mrX8fs1g1auzsvVV<GEliVYXB{y2fg+pGre
zJUoBJEN6S@m#}(@pkK<`OvNsDSlU$(En^Lwgkm{sNftEjvO@2}iwc$lJ-?N#zr10h
ziuDnde%@oPYQmVRS?#ootYIxlM_(<A6AXnqmM<M+>siO?sc2w1Z-s?MmW>}!tWB&u
z+V(cH0$3PR3v1C7&{|n9QF&S$%a=C$?W|er(08Bp`(8NH!J3c)`vEJH3J5w`+w!3B
zkag-NEOoIW7DJ(%b%FAxJ*;&UUF~I^rH`rgv5wOE*v~pcS3?F^YiENDT3PRf0Ok=(
zPMg9Z)|RC}8)iNA6HJV-)-8s{D2w|sM8;U2PXle7wY>!*6Ra(?qn>2FH3^t0Rv7)*
zrdd-|YVep9K=HvD)_gM>?by!FP_Spe6AA?f_Q7#@=*ZqpQD`T&HP!=mo!S51gv?=f
z=qYHpu-~M#)e-iG6ykDaSG^D7#{M@RjYrvkQ_{elon-}gjJ;2cJ`Z*?o#~IW_ho{3
zvcI9Mh!=a6129jpFCGH%X1h=*{UkeqDusO5-sfQc6#I_#I`n<nuhfD)&33?Ez~&5F
z)rI-;V@C%<!=HWh7$zZr{l^rzv+PS$Dip{L$pg$e_A~UgmLT?*<4_1@|1t-bLfDTZ
zVLp`I77Y*2v(ui$1ckA`3`O4s_E(>vFPt661BqZ~4buMlB6}ViotN2>RFM+JUP*DY
zX!b!0&&04-QXusTyLt}#uCfJmbt0Bs`x*v%jqTe9^*HwTbKqJ$JB~IR3GAOK6p_eg
z()Y`f*x59)WcG$?IFrJj*#nVO_Cfl9O&WXePgLWR&gQ)Um<;x|gOIt-UPMK1nd}|3
zXUSp<n}D6ozChJEH`p~E;BK;`s?nFjmVO5A7JCuh<<DiWT?j|>*sJN*O+LGv4gv-2
z=O}tz$i7Wsog#L6EEI0DSJS=2Vs>C5<ycDC!?j>b*<Vd#qVBK*H-VI~?W)jN&Q4hX
zXYR7EEd!}wFT4Q{E7{-DYo&^P@(0+x$KL1;gVpSEdePUgcT=dKmR+zKTpfFp34Qf!
z71csDu;b_sawGf7HjpN^mKJ$yGkb3mG+Nk`i{WA`JMd3vw6S;Wgu!<9^>^X$efAp{
zF^Ud0>j@}6V3*T^+{tF1gZ@LdUji(3u|KbeWH<X|H>mfptLQ22We;h<^|61gfk;2w
zVgxt9zDv>iLH6AZP<Uize@nrbA-3)_$PBX&VokCcVaIyG(kT0VT0_U!bAN&PaXK5}
z!DCw}J2J`MPf^Y(_Btw&oo4UM#2_BC52QeShV4KZ3_DIaRnyvYIJ7}^;55($eMe4+
zFGQR;OXyhb%(2FEFzmyeN?P+>I4zq%j&KyTT)J`sDfs8c$-DslqnuoN5qNOQS}}^_
zoYQpc+LMz{5i&2%0TuL4aAIle<jqN@2-!)_vo28Z;r!MCa*ETt2PnRr{dB}S&57BC
z0iNM3x6+ZvkMl8oOxK_D(bqr=;7m2Z#j_myamWO6bi2Tv<9tIQvLMd46xR&q{6I(V
z5YEJV;6gdkiO@UGnW3Y17^mdFn<ktL+Gm7wX4=pf!KtLs^hM6vcK~*Yvx|=2k(}sn
z==r<MNj?UcD9-EM@GY8C{~R2S;gnOc+7-_IQuJNrq@}~dSdJ4thSxZkFF-$z^U85x
z$8+3h)k@$*(jDwX&OQS$lQ{i#5J~2=Qc-LQXFpxLPvv+~V;U#O7Z%bv-(Q-A=P!eE
z<Q-VL&I#y&ekSKT`pso=f)_(Eo0HH8a)YDz9~y6R7Sh%&hf_c$bGJB0lQ7S@oWH1Y
zCy(<aEy($t0S9<kz?n<ig+dO8azaI%EDF`$=4@Jl#$wJNlvgX^nDN|MZAv+v#NOe|
zI}QCZP90rjD(56p9l~9X`_sU#;CyuiB9)xgv}{#zZf%9gJ<hG!=&R-wbYQ$SoOkH1
zZ7t`@AxPG7GN=rpo>LG6kp_<E4seZ}OB*okCXU-E)SEd=6mZSj!r^$pw^mM81N7TC
z>NjAbo#PS>nfshZGq5{2V!9^ufFqd$v`)^<lMs2xIV*-p7w5<hG<I`_?10k4SziOU
z`#FP`(Kx^f`R^UaIY<-xh_jk*mk)6UDc&;7DGq`92;z2I;P5EteJU>-<Gex<(s7QA
z_Lvi#KHA$(azr1%;1nmd17w=R`2{8(b3(D|+RSiVUWbSsH`#mO&*j$oGN?ImzoN8&
zGdG0xLx;Kh^C02Ejrs$2j&K)KpxKo>)PO!W?jVJ3k8)pH0pia6jj}h#xQT=4^Wb(-
zT>UurDou|k_W_*_ytrFvqj`e6@_88Y=4QMKu#?;?hoIoY?Xl9za*F#(B`o=JPg8>S
zG&fv>&NJLQlqB%uKB9VPf9^qgmIJu<G={U>EEY&0_bu8(pX2VKB{zucUjr_fJGB;l
zAzU#HDU>Uw6Z?7YdMbVh<L;&x`vq<trOv{+e?ItcGs!KbF<s;~QWe4_?txF>VkFm&
z&N!F38+$>bxNocAVKlc$j=mUfHDwO2aDSjT`c>|y2H1_|Mo_8DHE!n*5Q*a!(3jfc
zx$iEA-30EAvrtdu3Ms~%#J%<|yh!GXwe&EhaBV5}p2~gc4_Hd$22i#to$JYgOa}J=
zg@>+lL+A{f$vu1reOX-Qm#~!0wcf-iZg6wH!a#3wlLCRA!~Mz+BDc5^Z=x@k`_e}s
zdEEYOXw2uH9RpYacjJ0M7jplso`r|0h%1Q%dz;(*GfWh7U)2Gogj@73NE!F*zu<Q{
z_md}K@GjT$7{*k=9Xk)uO0JR4uvOe~s?Wd2{g%SX)!e0QkQ%O<j%KyoJybMR$E~Ge
z@Oo}L)r>T7Z402@$PJ=8YHJg>=5@H=%-y2|b_@4eHS}A#-BdHu#&x8%pq=~i7ZAD6
zJ(mE*4sIX4upV$do&$C#cPnj+aJl*n=DCYIn<}unxoq0m_HeH?0<4$2FaXef+{u5T
z(9c!T_Y?-W3n=$HXyx{8N9QB1FI}V^;vS&a*D!Y$xj({n`4DKM++V%|_89kQ5V&#f
zmVYqb32r;pQBQKEn}IgPU7&!%G`EaS0FSxT6Cg9(*M9_<9d8Q-sqA@?S3w+jKT>hE
zBX2EbWSw}{O}~M4<|)2}7l(P~CD3r;eMfaaM|cbWfQzoY<556!<JEV;(ovp!8v5LM
z&1v9{@t&gMB@dnh75W_KdC>9NlV^7r#EbXQH|RUT`y&qu-n?a*;7;=X`5lws!+YaJ
zICF}($V$00U)~$EWS`~*uSDk=-hNl;`|;{&cjV7ge}KLKUfO%$&hiqSU@4II$0v|H
z$NPrP$3eWpW^lp0FKC1zJSByiLwRWi7(CB=u@)j>yp0qSxxiaPJMnN{1f}>Rcm+xd
zrd;IN+JIc*Rb4=9B<}+{b6n=hC>S5byGKuKG;c4Ronv^vP>lNu?{hktUgh~xm?@4Y
zOM!YkFOF)(5_rQ@Gm^-AasVPpyf42(Uox+Vp12g=cNAhv<;9%<bQ-VwCAzSf&U>Z{
zYzFVhyYTxu@5VKl&*VJ}fkqbZIz@1^c~4!%U~ceMQWEth??*cF=kVq%hKXCe96DL%
z^6DsVlE*7p4wBDHvPWM5&zVvug}lpjswv{d(_#5GZ~mv~E9Sj%fWFXP!h1&mwv-pP
z48Gmrb&dkNjHeq1OgWE5mDhK9brh(n;Jxt@%vbWB2!cWtPq`nXzsE~x0BAL@f=;b9
zygA>3tL42*Pg5Q5Q8Y+BuUH7^2Hw@R7-u8zS6_fN@m6mGXKm)adIXkQc+XP3Y%8zB
z7W37{tD@VJ?YzYlguKt&Qv{I?-V2l(eZY%h!fq$;mjQ@8<b6qDrY>IBlj!T_HBgAV
zhxgK(0PE!`CPDgm(~Ypy&-0=OeSr7VBVZ2lmal`qkE}eM1F(m9Au=cq^XjPhX@ut!
ziOx}8a0D!k@%~K&_BgNfdyolUO#sLwFOmXcQ#^aRhcwNbe+1Z%c^|xt@y_t{w}E2E
zpXCEgd;Z_00CV8u|MlR(<Bu<co)iCNijq3>t-M6g!~E)JF&G!VcP_{g{`x`8kSpIX
z22eMCw>`L{{IxnLy7P-{VDK1UwjO96{C#xtIL>F^Mx!Txa{xrV_|-qc{0aW2^lJ6y
zfATeaI>lc=WedLiuW0Q(&5xv-oHP9M)-ssz<L6SE(4XHF1^od22ecVI%U@%H-9Y|k
z5k_&2KSJ5YApV=ZFc{2FrsP2g|4|3fLivkmg*nepq@#Bj--ps87x;Cww+rWo{|vAQ
zzR(Kji+s&Fh+N_y>;g(8-|iE-Fm;(fu^Zk*@#pUXOf>)ba7;oBKb`hbSNOsI1I$&v
z?IFO#^7T~HdX4`q-3N-}x6?K~o?qYu&;)+ab|@tBSJGKBiU0Y0aLIhV2+%3~{86B!
z@*QUZI*q@F!bItO<A1@-4E~4IijRr@48=_T3*A7=;wz~5H=DoMg1#I4jwNvICjW;4
z3@wMhyA#;A_<o;*%jJLnBSiA}xiPSm&p%1wo&tXJ7cf}Jcc#!+5kDQZsW!LyKhx4*
z%>UUFeI<N{zh}+*(WaFD3T?;k@P}wgEaMmKgG@R90$td+%QyJJrwV?<0`yh#A5bW`
zivJ9~_V4ipv`?t!C&j^T4L@NCOw{uI=qrA8{0H;VSkL#O#jk<?4+SF|`RU#}?U!2*
z)dQrJ-%SaSHvan*dTQs(R4{O#AJ&4t4*suQXnepwdjO=9|0*4@9`bFdn7WIf`7yA%
z`QlwL-oqchiN0R`&Hq8Yk3UMGkbeHgWQYv#SJ2OJkpH41P#*C=9Kw7K@!$II6H>$c
zObysE{_C`_80Ryn*kXe3#X;jFzl~~Brud^YP1F1iNBH!ZkAoy0E&i!W5Ie#8YS^_G
z^aVrDLGb);Oo*evN~^1rV0QuxIt$v*L*%gF$5#A3Tm<}K_;f_@#ed-gSHb!R7>t|X
zC?({M3jBqDaTi>B4f@9fzXd|WLtwKLBF6>06G1!$$J^kAmtfcvmQDyhzJ-B$3)a4b
zzLSDC=;i4nSjYf(O7M0fJoFXl(tvqd5R;3(GlG2D3HS-x-=p-nzo7FM$OH&1k?1@t
zNTq_NK!F_<@thM}rHw(5pyF+~7A!bk0>u!4?GxZa1#4ac=y}0Y9^k?RYiO0aAlQ-t
z5-#|f>Y*Y8KhrmAFA6H?Pku=-rwCl6U?r_fmjxHHs6;wSP<9yujTU6mCOt+lOs~x=
zf){AbyehDJ2GbTRcpL%HYl2KlP{j#u(YI#f1@8H1Ob}%M4WAMPvCE;JB<P@bce0?3
z@*ydLzJ2IR6*znVy)?luBj`&P%rSsu2%?6eV7)GAm1FiY1qoD|oh7K<2<&XZcsYE!
zA=on;FgFEL8!?z1!QVC@w*)86u$wFR`Z_@K1mDt`C|~f>0gwWLJO-eJf+Rb*T_kvx
zB8#^Lh{EGR6O`tFD-rxdiOW&}I~ibitb$vg0j*5HTMxx@!3&?mx4VLH+IUq6{A(an
zDQKXAg(^YGLHJZ72&C6_t-$klNY)9a=vZ4XXzfB@gP?c^NTXl{-Cb@HJpB$(ng#Q>
z!(fYG_9yVLRj@4rUbG3eJ`0g{fi;a5yZeGw^x$;}ifKw82z;*sv{O*O2aOK}#<S4q
z5_l$JF1iKG7XZ^E*!(VB>lL^v(AOu}_#NiCU$E+5hztlymqL9|u#BQLj|3W8GKU0z
z`k-%E@NhP`5rI=Hd>R$(wbH?TOt5|<=4)JVb`?M;1gHK2=%heR+k`2>A6H;-T3}E2
z_8tq)(%WxF5Kj4NJK+fm^w|sd*`UusXov=wqmW6($xgx@0-!hx*%!eb77q1+xCnos
z;MNhLZzdF6g~wy4B*RVkJVla@3a?PK)LppX9dO5l@6vD9LzvHm$Z?^5E)04KTgG6*
zOXyGAniIkskr;)yFoOefQh1o+?LNXOx{-BC_?Yf#_zFGg+Qexg_a4B`2sQKv^%Jg*
zgdu-n&M6At1qhpG!QfdT<7IRP3M1CR;5niGHe`Z?AB><eSh!>mT!?T!EnA_&2uggO
z7bb_pZkUiuC%g;7Tq^1b7uI}-35pQDzXy63g)%kzE(zT^@F`Mgq<rLMp$jd}QNrJv
zsYEPVc;Gd#F+z9xjN}#J7zGip3bX8BDOM<%4epw-kCvS{q46MGix>Lw(U>6okp5e2
zqVShMc#$Oh^+i}p7N*|?mnJlR154?`a}=-05L(`cPuGR{*Pxdv{I?t^S;F=b5Noz@
z^c&c{AvD{;;hRDhy)ScwNq+(DmhgonxRxu7p?zPT(D@^feBt|-VWL3jE`)xeu(=4J
zMZ)b=jC5O=LBWq=;W~=`l?cP{z>8AhSvOd?BkYNUzh%N?D&#E}Vrzyc%_`*59;-t5
zupS00g<-U?RtewU0L6R4Nhc^)3xA~4WsPvz4oKDtUp<VzI^ohLz|;#hm(bTBG;yHb
zD17AvM4E&}v{7spJ~a>iwg_8k^=TFEm;h-L?iz-LcA-BVC+-Wad^)vu2sdRy<AE@Z
z>L@#fF|=$w6sAZpv@T&Bede%Rcry_udW40)0JK+F5DL3}LPIHr-7h>$akl{s0wxB9
zFL(m`k?;VmEJMP@6fYbW)+B-(5hjlVWmFiy6J$)d+PV~-<H8-jU?+r6Tm$H&P(TIo
zQz+aA+O%-qV_-iPo-m?sMkpW02<=2RZ^LbS(KmE$$w34Qc<@A*-UjC+8d?Mooka<h
z1wJea{%<cSYNWO3i0JKpG`foB(Tmzm^yUQZxQ>dNzJ{W^=pt<)j)_EFAReNx>C)wK
zk*^uVQ?!UKgn5Yq_Mz{DD8B-nx2SyuU`~qSY1`=|>hi^`of4Hk2@}4ebc!RN79FO8
z&l%AMTD<&3TlYcFU*t^}Q36G-G4!SDbE51JC<cl4aM2ko+VLz5hKQ=i@D~XcrLv)T
zUi8;?OhTCGD1EK!g6My~5D6FklmZhGqNnNW7Z*kEQMu_Q(MP%9B1K<43r8=DY950`
ziFCA!ixxdi6}T~?p8G(#A~GR}Vzs#{`uPpO#EOzB-f~U!%znVci7b>}i5G>{KqEmk
zoCVhsMXT=sJ4qzI3D=TEdu*YQB3dN`cB<&t9#~2f&8728y68?5+|Cg3pN7J9k;`ff
zFjHiv+(nisgDy{Hi@tV-S?djvW*Yi8MJ~}$%n{A@hs-U})}27h70vt!nLH8yBlP8q
zmTZAyf#|?Xz%CRSoM664l$`^G+aiDRuvk<>S*Q}x$ueM;ifpJ%>yGG>1H32`Iij%E
zrd%X&hBJ3XL+3HT3ajV{rF<$ymKj*8621NqGWSH8^r6pcQ41})HKI$DU#J!FOTg8M
z;uw&u7yUt7@CMOeRNLGr>be51Nwk9A$<3nc<Zp|}^&2R(in=NG)FxW>5$v{$_)3ub
zq9<w9>JVAI>0tXn6htL+ouXOoF#k|=ej_xxMBmeNcZ)7j{c?{eybvP2qU9f8XnmsV
zxtN50(O3J>I3Vi!17uLNW;PTai58^5`ytWWI+z$1%}78-L=O4r8x{RY)sAB#NBXUe
zi;UKXXq^yo=^E^$NJpo!Dbbk<kZDnM5E|{o%@m`s7hm51*Br#BsEEW-Ja`YpNqlY)
zlFs4}>F{}2JoXaox`^*LLE(t_GMz(Q#TtqMxrr|}!i%HgxH~ZKE`E=Wu*bx!{3zn*
zA&&hN`p3l|aWQ+IV%8^6^b$XN7NRG_^M6L4w|JaFj3>pBRFCE(9!mn+De?UEfbkWJ
zP0%|nexAZ&XT(eQVrYKitXHAnFWyO^kpOXjG*HfpS06)Ppm>0ie&@s?t7hZ*3lay>
zDLYtPycwb);`0>J2^Ck;be|Wez5?tp@yly4PZz{Lcmp(C?Dr<P2(gJaju*ul@fhJH
z@y;LMQ=}OGKpYRA_)j`zM~OeCRV!M&nUaPv;zKl}SH#b6h2B;1!MpT7X=BBKlmomb
z-bUXei4$*s9$v(Y8|YY{APx$HXrefQUZY83`}csIEFSs?Fe&0PKPaS%^%UMp6Gwal
z^XX!<9*r5|N8e!%uZusr3Y1Lo?iloCiS>&Coh`n24+=NL!56?;Z;In?0WC+I<_X1H
z;z(Lka>Ye-%FYv4+y+d(_{lJE1>#TM0$QP1#sXTA_*V`_cw4-Rj(x@Af(+=Dh}~3B
zC>39#kJaB1$5uh4Ok661NV)iZ%G}%)%WVNxA+C5H6I*E&FQ#8`mDny5-rN(j=0l@e
z{P7)V)QIbE0j*ZdlA*CqJYNjOdhwM$_}d`<CkcIx;{G1kZ4tjmXV_NpJleFhiQgQA
zdb?OcS<(CAFTEhyA)Z4S@dx7Vc2MXPvpxcOD7I!(m1vhZ>lQS+#jn`InI3WOU3B(}
zHNG&|C!TA8NWWN4VVePQENwgo#XmN~i$~&rmSRjp;(Z#BVey>{FgPMEpb+k;*wz7V
zkBQ?ckTotIp~K{aIF6#?lj7bmh)jvETIowm(_*_-aPhJD9^H+d5igmAPCH2xB?j#!
zt6hNYAX!<7Mn_4|8gNb$GYbmNl2v*r9G1*x0@Ovakpb?A<N_T}TqPgTs^umrrw=V1
zl?)t*h`XeTZt5MA^wV3^L(*SPafsuRK{JS_WG@{my(9^g<~SkoIDtv<mZUiY^rR#u
z6~sp}F2a~jNgDqFsIO!TEwiU32fu~-8HtpZJ3k4FvIqW>kGwGK07(FCSkFq5OJFci
zvWcor&PjH7qcKR*C8qaZu%v`yUm=pMv=<1KOwr7qm*gCSXqY78Ei_(`cn8C$aLET$
zCl(=@rlZqE$*dfhxFnGd13Oak++0l1Wl2FPNR)(4`J-sbQHp29NLEwf(G>}&7;ayc
z@F|QQD~aDipJ=%zdD9&laT3QLF+=f^+62fXNcw4$mneBiM}Z{Cf?oiWEcxdVCLu-g
z(*U?sN$N}RFio<)6<oUHL=^fmB)=X7xh_#0gTYM6idjI(lKin6C^sd{GZ=P`WRL=P
zw<LZyK&-iv^dJl-Pg1`EqWO~TMF1_3tX&J3LP<#>`idmG*>LT)<S7qWDwb$3qp?I{
zmO{T&@?`^N=8hz=7ADFhdin*HOFmcx$-9z&C^laqv6}{TrDWhwkSfXf4<T|-a&8JD
z)mF*QT%grRA}EqoEBX63xL7Cob~$FKUh=g7eGQVoC|%bm`OS*HCdqTPaHd)Es1DdI
zlCe7&XsaZQjyG)*)n<@(N!|-kzc1nM1?iB~(Wdf&WS|VBQ=+Q|c_`UUYiF0lYD@W~
zZpqk}Xzh_iYy;OTi88>qKFKqYK<k(6psnhFB(@XWpyXXD1brl#p;zpX<h#@Ga9HA4
z473r+)+7vKRPrKih{hz2O(5fva9S-VBr4kXPD*TCp)iF92Zp94Bi7de`dCu;3fLJ*
zj|nn%(rPuZ?WLROtNspBXL|k|r5w7(>Ld-L_ldK#m1?;TOXpBofs0g1+ms{H`E#M?
zDouF@cHN{#s--+C-9@Kvcc~5Kn~zER)&a~z`Y~;dk4xuXr<bFr^x$o<UeW>zA)Jst
zyAy-)mb$kB^rUn>mBRQ)#{%$YJ|%sr1jJW5M8Aa7(&8HYMb1c{%mApL)Z=3)_)Ftx
z^B*96Fa(ja(jq!$1WLELft-^rq)%`JNsrJ?u3%|VGM)cIq>LZoMW}R^8#*sY5B>(2
zaA|-5`Vmq&g+ne%XDVU$lGMV*C?ciP_7J%&^`hK+lr)3hyV25{{!oaKK0%4AD^lNZ
zn7ArUrz3o<^jIcFc1^m8D(mB<`)P+8FFk@coz*5mDs%%(qBMv?7fI4}hy&UrOSu%e
zOOa;&g1%I#Kh@l&Nn0qDnJ$&miy%X)62a~3(qM{_WJ-Hz^0TCYKZ0aSgC9ZfhV&ml
zfZddGbKpge^hpJ#@|LuD3&xo%t*t_zHBVYX=c#<@41Ic}Kw3{ZkV0uW?ZAqpwfWGv
zE&V4ST(MM^1+GN;=OHMRN>|Zb-jPblZkcr6I}j<C>Vv`El`g#m$qH#z4_vF1E_(uf
zRnol)@cy3ko)5-ZExo@KhH9+Ref!W^D^>JCqfYu8JuCIna2{Y9q(O_J-zZ($gDGv2
zYI>p3ERCX2T8s3HI>59_3%w!ICN<NZx?NgLr-l2{J|omSq@O<rM;}OssW`7w>Pjhv
zhtiX@<Li=27XhqWYW1O0PLI@&-u}H(Tl!p7pVTJ{o&D0UUWJJPY3g?%gVIJJ$RjCt
zHuQ(2we29o(!~owMx=@K#EeSA=@mOBHSPk~xKvA**(ap)ec{@q^rsZ4Pf4|uCZCoj
zM8VKw>2m98&>88%<!H5&88(5lmwh@L8V<5>Dh+XzU0(s>B=db4#96k0s&bFWO6y?B
zRrVg`z1?KXd1yQ;<5K0TyR2$H26{}Es|V*HdxOecj>}%6AGfE>UknRgvZb_tJRwU8
zvV!%NMWv$ir0h3DRc(A^NmSW+O4hU=4*SYRK1SbZ8RKtgoRP8hX!Mi4mJU#V*&F*o
z0%QdbG5WKz(DMKbls&x&KcsWAYb`JzB#Wa1MX+qs1TaHn)t^HlRJP3s?!1iEOP}x#
zlO;U{=ml9irP#t{+FFnZ+4_8dUX*RKh22XscRD0R$_~@v?6T~4ANUj{3#VUMv}|rX
zxER^-DsWe1RkWqPDqBu<w6U^4Kg`-SSrt_T#K}@9?;S5&m<W^vnSMQ;{}N?&;m}W#
z{WJxQWEt~0a49l-x<!~Ody_VDX|lHtgG-k=oq$gnG7G&Fugg5?MV~2Cj6fty_Vo*B
z%$6lwhWZUz75&z4%9s?E$dO4{(7PoQ7osm$CW?jmJekJ>s9W=8c0Rx^kO`^gyij)Q
z6AZLSwrd?aZ_CU)XcWsf#Y4YDR?rVirLuz*%eo``CJggbCi`*~Oq9#qDcF8jc5x8u
z6*4xx6f0$eW>~6{y`2xed$Iv4<E@tcH5Z0zWWFoVSZkFHQ?j;BR?PxiFT1iCT!XCO
z5=f&g_%o0u*%$Q7Z<ak71+*4f)Tfx|R@v+XG`7ih?*i8@iw}nR`?5u}CFqc8=L77a
zZ0Bx>bjiH^A<`|2JqNozvK^h^dSz?sAkrtZ&ToZczf7hE_JB+`4TFO+EuAeN$$qed
z{*dhN<4_!yjhexY$QtQ>z^LrdGnk+;Su=gsU|bfp62qR5?HYl|r0jAI8mDA+-hiH#
zZK07pmTjYV)Qs!^)fC&w$0#mfFaOlahoXbrO3$yO{2*<Noa9ZkT06^2{(&=x<*~Fc
za*-=3@o+@$wiTeR^1fscH~9%J`i{!?*ui^u`G%)3v}5v36X^4hKlc!WI4=L#01KY-
z_vx_WB{zN#g%k2)+u?<`ym`G9mQKo_2uG)neCGw|pOUXw1btum8OkM|mbXno<BWVx
zCOq_$>!?K0Uw)2u{Q+_o?WxboTPnc?$^+McJ11|P0a%dy8(Ou3<)z;6B1G;uiN;X*
zBMLH{m%GwyH%$K4a{5HX1^II!=nR)L%Ag-1@1pR+Mfu62;4aA-6#0*o|3*vjWqB^u
zB}B=mDee<3Ur1Zj82R6Hzu}5}^>^sIDi<{YJ68UEC(K`y$I_=7;^Z61?RfcbRF{w-
z7t%{HQJ%4y-hWB*DJscHmS@{QBSkKI3i_$?(+p^&$rE}od+G8=bOkR%zK{-u*X8Th
z0VY$vi}ndw@<ytr&z4JF;L{CxFMY}Qro5sJU^((``e4~DxtdN#x$<5wNao4;ZBWmb
z$NdY=S|qQm1AANkHa!-_^21A@Q6fJ;1!AT0F*lgFBVWRUNSXYV-=R@1XZS$mt~`{^
z5EXLuEm*3QYv)6xN<NEr&-di}*f3Zv|85K@HS(emG}g*BRLNE+4;=z#z5KyujI6;b
zkEQP}HOdz+0%?-(FM(pSoVgW)X^|KG0nk?YS9FkSlmA!%#di6^Z(;YoT)qL=9detE
zz<wYf-wC}=dF>?h9?E07LAvA@zk+(Vd=6E`_Q-qbXxb|uO9NP+{MXG;@0VN8Q0QSm
z-bm4cLHWi>n0O?gL(A5XeEc}Dhvi}P^BR$hUWDSPoc$?8#^kLXz#f;g{(+?l`4=QI
zDc|o2ktum;D4dy=>*RobEPrnsrfWw2kQNF%#RSE4>=mx`-!U8%NmkmgJ1U|n!t12?
zjTUBSML2DG4l72JL0l9o{)OL16ko;z+f^~02ZL@32TGqDRowdxoV()pf1rL$v5DTv
z9*QnH2pw0<D}uVGVwO8Bc`16RF5!eCo(`JciWC~lNrf_)@((_W`cr^8rC6K^^S+8c
zDm_1~X#WD_jN)Pp`ur4I=7IPtPE<fYKyhsg`pzo;z637<73-;Z^PECX)h|H`K|8o$
z1#>n`geVlWXoe~tabf7Z;_v++VT#Y3;MxU6qnJJs5w5sNJM0KWB1NArDn6ih^CiVH
zU+70Fw%3EZrg(8LNSq?o1p|#&tZag%WW{Hclt@wZ(r-Og@x@O7y{^cnXj!JhL`7Ly
ziitz`!xSnuhQjV`#T&aIQmoiYNre)H^eBBIuvEdMKhPaT4BZ<mQ#}3x8s&;{TX1(3
zFH=o%g`zJRXjO_cTOfH)Q9@U$s})^zGOkfvbcAcQilPpH)+tiTAlabUdlHr!73Y#M
zq$b4^=P)JBitBXrX;DN|EVxZ^iC(+bc7=q#GIC#W+7)OWieXAGKTs&`q2H<4OSAV-
zG3f}6ZpC?8mwOaE3ZC^UE}TJMpJD;s#qU?l$%CT<iWRiL4JtBeFa1byh<->zilAil
z4J-BrgBwx!IRI=_VK&0-m{qZy(p2LLf7&TeDAL{lH>D_&0()AqoD!^$6>;|=I-~fW
zuF2UcO#;B!D}SdzgrjoSO}Oo(T>T5C#98V2J?tJ<e)9{6i&Fdmn6Ao_*D+8x<ys0E
z9#xjm6=Qd0!Yz<vO6!|zpzom!twHB;<s}O0cqt7NuyjJXCIgndl>wgt`=pXZ*?S-5
z*UccOlux`3pUx;d7r~OBvTz@q@mIFd4>3SF=PUG`RR&X8VW6^xwgkb-i&UZ&qWoA3
zkx=ESZD_opbhbVLH^P;D26RR!>!}<!QdxTo1}`h0`v&Htl-gW~UQs?ltMpan^TU|n
zSmhonO^H`_Q(!wmxq1{LiONIIgG*69Rfr*_Dsy+jr!?g<N-<nl-b{eqOy&FQ;C+^I
zgzAa1m9K@-^LIm;NjsXG%5pyZ&Q;#NgvLDOsjJ}fm4BW`UxBhO1lWbj#Qo4OQg%HF
zXG)Z8DpD#{7E(Izj?#@n%4N!Y0nC>x`BcAgSIKxAT$OT?&a(HEaTKVnRxYC5S)Fp8
zEj@qr%E(4|)1Wk50d});|MM`|qRgadL95b>QuS@h1*tI6u8iA-f!<d}(@V8i`D+9k
z`;?(+5b0MIP)KV)nM8%2gUT#g?j9*q=r;e5ay#t`hn10Z^chj+Z3W7x@~L2Y{>GH2
zUxVForOX1E38f(j4o@n7VgYSR*-26BX=U0xn0TxVraI>trPv;gcB*6hV8ULt@F5x<
zRO@NG;iy`<7hp~*gB?ViRlnSY`NOJ{Z=%sf^~4nn>4@qyZCG7Zj8D*KbyNKvfzcmT
z-KGP!yGq&&^T$-B9>Dfcwf_WiT=moQ&^V#04u`(CibIR_N!6+h48}+0=n8U5HA*!b
zzN#Iu=sT^lehPzUR8P|-Ek9Mri{Q?xme8pxP*wE`$T<}+1s(=jRkM=N8LaxAa@HZL
zlvsEXs+y+k%X!sedKrhQis%`+pjxp2jp3^351=2RdS?N~dr?(N59KA*x(k@nNYw<r
zOruma%b^ghy5bKKqx${7I&{_PQb1o-U5|xGtm@l-pv0@JA5&Ryg6a^}izcf63Ij}%
z>g#2&l&lJ<f<}sJVHmhn)$CW`VVcT98_#sr@8>Zk8LECtHC$JvEd@%Zs+@u8%2Iu^
z5+<@$LqA|*Z>X})g5;?Fr4&@2>U9cu=BqrYNU%V)&3Y1`g{p<2&?r(pN&<IVwdyi7
zidEu5V3(+hx1g_7_5K==JE}ERAZ4nGV(6E{F34Tg5)DX&YQ8H-rE2VR%v!bT^=ojZ
zMr8;CSgk6RVw82N_j_QWUX|Jaf16adI%)setjeG_ZHsDV3<GUd#RWmXO?A5m=G#@@
zJOgrH#kv8>4%OA)F{KYwQ*@B(RIQ;1?L(EU8;xD6)3acrTlMcfp!BG=(E8e|YB!;A
zK=r%;&J3w8{<oD^c^`n@h-!H@U0)kj&7<#`jH!+s!VHb8_P-8G6RK;wpg5^A&=s{Q
z)kq*3r&X)B!_s3_Od%R)R0CYhrGxs=9uP-$l?MzuscWd9!dbmt2Zh7xS>IxyF6yC5
zm_MT4-~&uo_0Sm%&`m9VmCk=h)%gm5x~tc|4X2K&H{XE1r`r4xOn9kJ2SM?KnoG4C
z-s)>VgPc^``vTNQ{ThYNPpe;F2)k$09gXnbPwlt|#9!Sr1+W0M!4=$D_4+?xAxND-
zp@(4gx4*)R5cRH7Sg?kwQ?p?3yxN)%HcV|f0niKTk|p56)!&$)5utWn3yq8F$H73m
zq<(k;<Be3OEQa1S^?EA#jZ^QVaC5x+48`LU)CT%4M52131Hh8h9sm75DD~^~?+jAZ
zBR3$Ds_x~%?KG>}e=}&hdU_K`hFVXXfa~hvW8gB?H`*bZrJmCZE?fQLzd*a8p3B3`
z-c*}CU?NAo<OmvXsq1O!&sD!e@y|SU7kvacUu~pAQi0lsR`){n!FPaCq;{YiRJYZy
zQq5nn+WPly46Q`%@dH3h)ld1L^NxBX6{Jipc^xLo)tyvLb636pEJk0UE?I_wR;uSx
zn7c|n!w2>~_1gwGTCHYLkiJH(rU$-O-AQMjI`!85Aoc3%FQC_;ZlM3N(Wq{ohWRG7
zi<JUR&FYOuV5vo2pN-B|^&twww5d1KX|P?bpd8YD_5K(b>`?za1@b^$_Xy5(s@)2~
zJyZ|85AVCwg&t7vR&S@0`yTZUJ$&j_UlxPwQ%^QRvR{4g1VjeZb??FKpgN?A@(+*H
z-V|pZQaAFUF|7V%6pbV5jTFcjRo{3I8e{5hbQx}3z2pugC)D}pAu_E#M%(?z>bXlX
zm>Kn4I%_#-4$?a1sM$j`ZBCl6dO@5u6KxPVta<txM&_b<cQ3$>Xcn=k;@?$sWj+S#
zrZKz=(W4s0^N?}ZjBkR*F^!Zw_0W7z2e9KB58C2-YJ^HidTD$<2RWfxU4ses)_Bue
zbW-EA6XW&OyhdsG(;9ad_;g0Ib2&!lrzwtxq`ziII4lHcTo2B|^LJKbv_Wg2X2U0t
zIj0#r4$vS?Ck4NPHOp23EktvGw!fj8LzEpmuetpu+z-<%SE28MW*%kr!ZnF9fL_w9
zq~g;^&2?IrFKfE#mk_0?UV}kIYu*@!NQ~yW7cqz{8u8PRv|iP`w-M%JHKTNrxu(gW
z6GfbcR}B4ljnk*#5;WJv5KYwB&A}ujX+9l=Ysnh14tgmXK|2~#HK_|BnWnix1&QgJ
z-Slbt42^Iz{JpN}q?c)?<^XNPvNUqK6qc=7>I>IyST$P;pm<Z0vjqloG_$Do{Fde~
z3X|t*PE+0^PZPQeF!`EcU$|eOdH6B(3pGc)V7^FGPw~LpnqoS_7i&@<Lb612fVSkN
znlKk|cQj3>p;xAPKLKFnnx8sg@2;lsStwL!tWI<stkiVRh21KRWd+DRjfrAI)tXOF
z0H#Lc{|5}#YWganSf}}MF3{>VDoT_zXxJ2)YSgT31X`2k;|XxhnoQb+w`lBkVG>$3
z-7jOh+BEgMA=0k-bSwU74>W%C_;+eTtf4URQ1dyZgt|1ZJ`1i}bC7l&J(_o8q2H@<
zp}l;c#*0dv`!zpPLU};*8f~ZsHUB#de;;Y8IKUp#^d5xXu*RNBwnj8NPQ$}d%`!)D
zW15Y3;nTS0V>%{GXg>KGdXt)0n<)M{rMW!~c3QKi3^I>3Hm?ACM#KFY#7_Gp730`z
zi(N1Z2knnRXmr$m`z8!JX=hUjhO_om1>8QY?TP`4i#G2s*gc|crW#{cZBir5yJ@TG
z9?Vf~?Pd^nt(O8rI;NfVGUeYrv{w2e%5iNdoxD7?FH!-qmv(^}gE^u7eE_1~+JCO1
z@uYU^m*9M~KEoiVv?pz#=c}#R2otBZUgX*tZ82>E{Irf1nD^K24Mbyr*5fLm&uVv3
zVN#%$nFVrA+q9GF&w{kZOgJ2@9s3C+M4LzX>`?7j6py%|<wd|mxYqV}XhdiiQU%vV
z?ch7$E@{_tArh%Ar2xof?bokEGD>@Y1Gs1{(+rdtEi(v`SG0kYV7aROh}QF1ttA(Y
z*R&&)&$7m8`2w`YYj>=~lqP5+wxKgoJC`a=leBZGt}0m@XakWHZ3xY5s@B4X7irp_
zi!hk3P0fQ|hIY$A*uAbTrG0v)_H_+NmUhSslG)k=luf^(b-WDdo7(ROA(^AykdDS%
zR;?#Rm~ypy{Q;AwRlN^``P!eD=q%9YZo%voY8e#uD$;)VA;@j*AT8*{+FxIQLWy?m
zci>93+l)ZDqkS?DT$y%+wi4yqMZ-|It3Av^V}*9<0+32=76mD)w1!wH+|yd`(nZy3
zZRNMnsL_7b1yZXOQteZncJncqsMq$a##}ULE$JYQTEA$_MU&Qz7K3JOKYgFEP5T*b
z#M-qhj={uz?YcJD?SLh4548WIPdapJ=TS!Xp?1S(knGZ)t^(=SF1GezPI|PhAHk_!
z?QS|6_i1HRt<kS7qtnKKwwDffgIb%9fc8jRQ4WP6?Myg49M-<@FF;4McC<o_YW?j&
z#<Z_c?r2<_^9jg=Hu-g+Olp_7f}7Hwr$X;(?bfG(@>sjrj%v1Mw3W2WveTX6!-T!=
zISMT~=vK_d&>VHSA3@Pc_sh#5&N}v=kUXp_q%fI_ZVvqrkLb!Mvh1oWKZ`y$-GC?b
zj_Q_OLZiD*M&^&{qAQ^8p<D136priuN0;S2bsPSs{DYTn^))zkLKj1CcyC?QO~{<o
z1ug`dkFG!qOQ&=Pz5<%BuI6bpp4Q3fJBep>61uVJr;}6twZCrS9gHPFw~tn)vpNlm
zTWkV#*PjFCIo)eiDi)$sR0Abcw}<>auXDx^(P|T}YoM)pgl;F5`Cinm5y9chx(!-P
zaFi})E)=76pEy7xQTP2{u#}`r`vfA%y2BI*Owr|0QFp2?U>=5@rrSq{q;y>#onSI_
zLG-4)uB)LWb*4_c6OviFwD~ZUty8@R6zdJ0Z5Axu)b-NJn4=q~9o#M5GCEJ?>OS5N
z*Yb3qU4clxZrgl_6zBvJz!d5P6gn@`9ey7Qw{_|7!(g#)y%r)RI^F~tOLgf_LGO<4
zCgqjNbboci`*NKi3(nlt{Ye!z6)K&}0>D)2)<uD>((Ty_a!<GA0yL_1^<s>vMyLE2
zptZWi-q)`(tp{EQbdxTe?%X!(#xp@$@XLWqt-4goaJ1<h>6<U@y1Cxq?&~;(fb7uy
z6%6iy&MO4wI&~40(0QmkOIKODboT<mb?fF+#JxxNz!eVm>gJsUW}hyWzF*U?(-(pp
z&=pw+zz*u#c0=@$?j~(ihjcRmz#i6x(#kTTJM;w5Ms?p^hNUsx`W4{Db+%O3H=$G7
z!I??j&)<SP)}>IyVMdo@2W&h2d0JiV_2bo;NeBI?4-7f#U(SFtPI|{#u;;A*a}B+)
z4(o4!4Nw<-`D+k8qW_bwgSqO<>AmNsAE9qM9n~A}!=Sr9Jpp~k^dC@i%R|2oM;@Ew
zdT|%}JoPu$0Mtu=jH2=<^kwegy!F1T>F2K(+d<Mt??fl*Q~I{;@WNN`w4c5w=BJOP
zcZ9z_oWAG~pkGUs1!whZsYE4E|5FA$Jf|<A&j1AJ8^jO^)~mY#8lpc(FroS|`sJP1
ze-H{s!}Lq(Y<59E-v?s}*Y8>n5}~&Xfx<<-QysuA>3g;VI#M5tXToZ8S^qW?2R2dq
zj`x8btzSu-${2k-#qqA_6P|;{RsDyF;9~VRoWNbvS7yMOIQ?(*A*Xo#4@KY-^y|KZ
zUZP$~)v`%?q~`EU>A4h|Nzwnb10+@NIslTUf0+)i>H6d;s9Q7iS1GE0U9ZSPYo<Ps
z&dyo-c~rZQtv^Iru^amRzXJ58-tR+<B1f;u2Fxw}&o9Dmu0HoM{;+xaf3Jhf*E@Bf
zuRuRaY0^Ud#}rR1(r>1}{cZhSN*xvJ-xYx?(XaU%qb{}TJD$f3-O+dIF~Tx^?p%0L
zuFu;I{k!@NDj2NLODGv%sh>mD3RQaX+i1L}|AhWN)%qW)zPv_12gy&HTD`ObdUbjZ
zy<6(_5wsLE=uc9}pjm(F5JXz^{j>#W)iWwEvNpXn^*Hp~^}%=G+kJh{m+0)!Z=llo
z2l^o?^gH#NHURCRKI2{Jcj>nVL!n#0Z3aH|=sEP)>eY{QL$6O?N;P=>`sjI3AJDI)
z7~!B^KZw3Z`V~|>H>8gZ2iUNF|18)W(I2)_4eh92P0Qni{tX56C-swb4w}**Z34`+
z{sni4KGwg`4f8Yl;vmeEox!04#NIGOMU@VQBd<cw(a>yyf|KF7*>KI-5I~8f!v?QI
z0CO>{pr6MPLm1tDa5dCW@W{>Z!AJDMI%*K_g^au5n+q^;%&=oC&^!zVI;kBuEF>6D
z!<Q7P^fLTFH#$xjs$Yk{-i8{=%bqmk%>(CS=%)XrdCH(JgMzO?P2sWAhQpO`^o$``
zg+@Qafj7bV8xEMk1sLvy(1Go&p@d!sfrbRy+MY8UvO{N(;qgIm!G@n>fE{8uRgA_^
zgV$cn#d*UPO5}zad|v|E1w#iD-iI5morFk)Vc%l(T{I}^j^!o8s(g@0gTq&t=F5i8
zH^4<1B9;L<+OVjZHjFWbY}$%nF?<jSnX86&sxyx@JUxPmx@IuZh9b^jH;uk{!zzlB
zB^a(##x2pXdmQGI47X{gm~4omlt_vpWj*v#4PI0elV*_Jgu!&fQ(oxHFuZmgjah~T
zOQD`^aNG{gdc!bDdH0(J#|4ndG2E(wrCWy2S}>Qn1}6#x<QdZG>y7z_xfE|LFa#V1
zDKsQg1xAtK9jZjSZE*h=BE^R5E5Vf*yjV~#H7tD{Chiyt)?pB3hNmg3Rc^RRFXp?3
z=V&e}tcInubE`BQXalJ-JXT<Y_Y6)Hx~?{i=%H9+*ldADts#^$NOgu*TJ!4-pC_WP
z!LWtO)*213(~i8!@Y_jDWwYVv94NFHGV|eKt6|SJK(`qt<Dk%P;JSg_H_WYpUWdUd
zrDO5~L;6)X+-WGGH}gY7o&p+Oh79_GX1Af3_E9~C9{LBWy#|+fVD}l``yKB08-8;G
z88GY<0cFszc0EuY8LTToh74OMtvhUxCP8n+P-p`(YPg&M3uA`&Xb(JYSZa-ii3vmS
z7{)YdnBN4&DZ}Ir$V?lS^r7#u!Ah5jW(+H4L&MJ4MSov=Bj*Kh4o2?;C^#B}s2tMC
z_#r*1&c<bSuyn-uh8B&k#=9FK;%2--nYN?GIgXeTcO#2J^v8^gzovkthjHusFn`=Q
zCl`vIMg~=(c^R+10*w>KJgN!xHjduJ1fMh}QUQpMv1b#=DPtQ234D!r9)g@UzC|I~
zGsaljbo&|0XeskIT0cT#fN|6p2G1IksCqQe_>&Yqoip~X{I6iz_|m7)2sVEF9xR0z
zr>ICV)cD7F=$|*b?FAQRd`Lg93r1ch6vK_DDJB|Wv>t`q7mX>0(09pbn~c6lV<Z*b
zT{dPpz^5o<NHnH0+PIFk1Tn@fEzrAS)KHe^sxj;zdjG{5?di_hHRGHKD8?DLY2k3Z
zaRC*1Bp9dZGDD(~LFJH1#(}kHOg0+sU@$30;W+wIjg9o$PcxpP%vHK^>q+!w7<*d*
zcHMY^4hxyaPglZxma#?$k!<6^Wl*?bETT2rdehj$hDMIjkFxN$jKB0jBiFcW0|t|4
zOiO@9zA@buA_d0%vj9_Q9JvgUBIBQ0a3#j4RPeXd=yVk#cZ>(=bWvt(dln+)###38
z;;u1^J|I(Je1@XEmBtNkVGvcu+65T(J*!bbTZ3xjHWIBdHZ_5(HC`TsGj+zNm>~5=
zb^_2EjLSDbq|xZ`C19G2UD=RqHhxNvaf@;7T#TvJxQ2qEZN`1|z-~7-E{3K1#wZu4
zcNjCx7}5jd7x8eW(^x_o&4)(okPjU0GMfH^Mz?V^4P1|L(L7-H8iOes*=NjLjmCcC
z8*1ne81ELKZ_vmQz|te*0?G~#8GoS2?65IC9IlNR>u4z)HJ+td_n47;6nf*v&2NI6
zFn-<uLzBi+3t@iBc-2Z@ZkslC)7Idz@dlkKXN>EW@Y~L$=?9FxY3Lhp4kkDHc{rLX
zYC)V#vERd>v&l^fy~C!Y_3*;Q^ai~YkC>Q#FyU%Sp;7`j(=574a@4fsRhV}-U8ahy
zV<sbQhCNJdcPk7YH~sk~Ks`;a|A2UzUP^?)6DAh@fxJymOk(!@O*s^t2r#K$fu*yi
zy*;oLXi|qm;hgE-UNi=o>gi@iuxUSi^Et$HmGYaRrffP*oi}-wqc6-Prg&+DY0?Jj
z7fn|!l(4&GigO1{r0HHWL@%3e?*oZ4J*IqCwCTtWcp78+yaXawOlxRoan)4y8c3{3
z^)f)OncS!`&g4fsgLu<pdbuT-exnm{qUrAlc#&k9cLiLs>F{B2DW>tc&`UMV%c6qm
zG}H5sF(=ne%O9XM(^MqFu(M1_8jx($kO#;O)ASX9-ZXtUh`)V~X{!)0w@klNm?_uP
zdITiTwC5Q#=9>m7eNbSE>4sjRX_)Rp6q#Z^N8fGJrA$~THbv6C$`aFBD$25!n(`>1
zcE>dR3S`PmwFl5yZnB{-tW=sRXv17(%H9r<d#22np;2v8P&A~*R8<JOwWe(pt*SGr
zUIeK(Y3LhK4W>hsCuuZgYcP3DroZVDMYHMWN{|-QS~}~rnkwjjN3>Z@90$O(oBXsO
z_f3x)FwhQ@w;$|2FrA_@p-$8Kr4W5+ny-dWT_zsg;pjG*cR-}a^pXq;y{1<eqOZ^N
z8Pyv0n|98??ttlJ6hsD1bN+$IBa@OobTVXOPzA)W=?WclM@-h><?v?IG>;ac2~$lH
zyqGj?@dlYPJxjG=)28%`;2xX$IGEBI)5VX$*_(fw0|f{3of}YhG=D>tsZM4l{n4Gx
zp$)Km*c?^{&c&Qh*DH^h`{M!TYA&Y25jS(r3uruQjus9=#@&p!8y*Yu1pRXl4|6TO
zVvn11u0g}oeA#<v=5nh$?S4<1^XMJnV}30M!#!o@Pr;C{`Fjdfo;LrFA`NHEdmI7n
zXa1e)HT}(VasU!wj-szUoHb9@13A##&H~Cgv*#^vL1reE;|7~wy@)Y{n9tA=E!6zO
z&*09RN9kl4W-hY61bV@IYd%23&BOmyn3&JfrXkWSq-XlF**g>Fqs%Y1!_jE-8x$Xk
zF_$<&?~2)h0ZUiSm2~onHUB_y*=uGs{ea@kOggv4n`>$9N-(>(z?npI6D4kw%s<hO
zB-!lzGnEl%nbpH!v(3S@6x}d?OYg*+=1okP&oM_GfWcely{Dj`XD*<-i}_|dDmX4M
zAE6UOq4{Y#i5Hn|c0r`r?0*9&CFV1Kqp#FlMrpG<=I34pSef~In)<tD56VVWn7>>|
zg>9AQg;c0gWtRLGR4~6wKfr49KU8W_V~&jjTCJIL4nwOmN8E<_dh=cjM$uqiE{5Gk
z^JifgVUyXOQi09p&z^xui}~vs%uK6!E+6V`=BzScwwn{a$5h@o|3wMD4)b>G?W{Hr
z%$GK!v(vm&1JH-&aas$y%nzS}Vz+tiA~@V*{*p>9dd=6jqp{DtGz?t7d6>4+1Lj-`
zSr3|jUIp`y%yl@S+6<X*liS1Q2-+WvnB!<$Gir9%!nFyregiNk%@e=C-jXTvx2-Tg
zZGO~>*2m^&Puy5;&7#ABqb0K*#L4o-3P3trik3jz#quMSf*i5Dz=k<j3!9RgZk7rP
zB_6dnL_y@3Wp+QN&co7p4U)$#!4#SEwCs2Y5id&(6{MW7?4?ALx5b%uSSKwfmx1_L
z27bdxPFYr1pM|2YWm6nvPFuuuu03P<o30M}S!!vQ?QeOKf~*0SgH0IbS<6pmkU&ch
zm2I4}#L_|^WZ{1UkzmWBA@~$xNzDcqYB}5i?!4tf4h)7_cAbO43zjRzAmNrxYatS0
zIi~VndXr&|48mVE%Cc=O`l2oGeF0x$EXSV&cg3=sY7?$mz6-=S<1A}E;aR-p1&U`T
zSmI=GFwycCg@2PQY>K$1Sl*_+MXF_y79`E0T>!~+%gSXKScav6VsM$3W%LMVSrnAK
z&9;<VKSbvZ3o998xoNo{51Ct*|DAyMxfb6@IFn}?-UpF<%Yx^jSYUav36h1DITW5L
zvh4gDmTp@XQeASf<w-k`5{qR7-j`Zlpi6IeEONRsRA%9ZL$BNt`V^q=T6*bCR$=+&
zffcQlmV>7-v?|MbE;R00g8r)vw!B3V+Zsy@{mpAF_vw#aX9=PYT-RHY=vUNWDIb9s
zjTSZiw3;m6Q68e%vY3v#Efzj~^s3e391Ha}i_2X&+HT3(k9oRpsXPa>9TxU0^ug!{
zmT!y@?X={Z(AsS&X@R94%Oa{!>b0~yhDM*|DGE0BTMmjKGGGa&qsb#n?F#4(S<Z{m
zIBZcZ0XJfCV!(@0%e4sTjaynNu{B{?^c2XX#e-0$EQWZ9Ok3{aIkDQzSbn85nB9w3
z2iUcL@uUKr!;6yh(06?C`+e}j=|y+iVmQC}H)RkGzj*W+pt<~?qw9{#y88ZBnyC#d
zEz|6$4Xte0&}Z+xCu-WavNAKROdF2$0aR2JkiA5fED;n?L6j*&5M&DoDns@X5Rm<Q
zpZMpz?mg$c&$;*cjC;>H_XDGvN`sCut`uV~jx!$gq2<gtRE5?F#@_$xx)`hI%5!1(
zQ1IH7;q(}D;l?<y5S^zO7Frb8+!>i4!-NN8GbJEB8EdIN#EYS#n7=o}o9Z%s816yv
z$(ONy958;2e>OwGpYfFl{su61(!UP~Wc2Jr>oj8z9ry@h_|U%Y3}fL-_+5h;H#a~p
zgi%dju?=NZG{8_8L)3-N2pi*-$8aN(5kRTCD8@;ONk=oLKZkw{<2`!AoMTv&=!|7d
zNTCtO_=V0I#WR-2qw@k|W)|#TWW>{3D}fQT0-cGBl|Mo+iLv<u@Gdh_)<WS5Ba<SL
z$&5Fs{4RwN(F<~wVcSVz&Q!)y0mwDRyL9_rXZ*YeV@hKjpbFh|Mi&*{WH216p^?Q1
z%*V`RGgzn5y1}?kS+X2P>vh=8Wo)g2i9E&*x;*k3m!5+c1&l=uKo>HG0w8jWao`=O
z7cnAU1!ghhy3H3RZZmA1P%L5mMlO~yO!RY=GcJA!m<onhHZ&?3HI3j^G2W^L?+#=2
z1?W{Xj{gQy%NRNaa+lFgTje^&etI_7GoGfRoO=v;HaZ&^?w`Y8BO~!Jz?vAfFJoq!
z8RGvw()W;&<c3kSFy1x5;a0|F+F-RaKA|LT2P2Dike!UZw2A3rIM61joAIOu&h#*x
z{tqI(jAIm>dc-(PUkK=DaGT)v03&D#6b2b}RFL(U(Z3h1A%>kZpobY>Qg!7BBlHY?
zapno*olR(tGNL`<)EML4KcF$ec<X(@Ofp=2;qVmWy?Tsrn(_BGn6PJlIs=^!%o<wM
zI5L0aK=Lq?r^c|4Fr79*-HEwn7Zi>%XH!|rG3Kkk0Qxv{8|8_dnffN!JIQQaOdD7i
z<~Y^qyE1=n2bvpG76O@5%*_%w?9SXu<-Q)wg<=pdruSFic{5-C3kp8W)s$uPWjd_{
z@nf$47@&d7q<o;9W{$-`GKd+Sh}IeAz(cfxnftTheF!ss9;PdlIb903ZQ;zM-H<uU
zto#Nt5lp*C^hPox7oszYnc{=aXl59VK87ivwS6q}=MxY)&#cKnXB^Y<96IBfTzZ#Y
zU`pxjd6AhL0$u{spZ0Z$%sg7UCNVFLfp>{{!-SDtW^SOnBH6~=^%UGsVcw!N%2npG
zPh%9R%(-q5y~gCo@pD~g`X2;#8nd?pA{or$G3aM9Ulc(yi^-%oQZ{n|y`ye0hu=jj
zhq=NYBDu_xe2{$R#XNN0WQNe%ynw04wq;f!vuF=^x0tr8>+q`;F@I!1rkHv2Fh~hA
z&l}8AW(2Kg%b0)Xfs`|U%SLAfbI~@;%pK+)F-BO;e3p(=)G)6OL8O+MT?h5M%zX~%
ztYg0REJW&=pE`luXWphS`aEFnp$TeW+Bd@AM&_7J2lGwLZ+8N_nK_RO{fEqF2f=J*
zR?_X?#(YTM<Y;Hc^wRCXY#j%7Cv$N<40bVVDBs%6eEJdedYIfLn66&tUzE`9V=jFe
zn2(r7dQ}ZDOXwjo$h?vck;lxX2jRsKGs$8D_Av7=N>Gh3AASMm6Xw9n&=_ORe+2^_
zXFf9nq7%&S9gv)4-n0Yu6tlM$ylE!mWBelatdn~|99jEmYjTM73I+cTvlO(dI>LII
zUM@~7A9@lWWqsQVy<@EGFCgj6%3DhBzZ0xAZ^Fb$me+TXabe8}f{ZJxcO34!vp%;2
z@nEf;2@y}$r#pb=#d4kvf4x~nbKtKJE5Hg7UshlRJoIN-Qqc-vN$6o6$a*m!!#>SA
zK}(S!mg`#Roni62&<bWvA(@1KO2+b{^mZ6aNUx4?R>%wR?JTQwJG_WsjkLk1NLG&r
z1{1~FN6WEjR^>U67}f!LYMo<^Qu-&BRX-mhajXnFvlGv<G(ztJYu6R{dy(~+cHs%E
z54XTVBCCKl^GU238L(ix%-T~3dWH25RXZlLo+$=e3M+6uV6L(>lMubmQc^8^8cR&q
zY&vU?KNK=peMB-@J+!&aVu?LrKASb`FgkNsrL|DcW&QUF$2=A{5$5w*t0Mq*lXdNX
zn5P1kj#fE^HrDo0h!(L}^j0fooq8QGw^<wZpjE;O5CXfDwR$Ex%UJfbtS@JMs)iR8
ztPEd}N><W*pjENLXm@#s)kw#-YFHo96Rnozz6#FVWhLp+S;tD=39x$Bekvrn#}e?+
zy3ev*+5%<+E9VSE8(A+=9cmM6Xb6^?Sv!^j`yuPr4T!X{l<VMVJFD?DIy+d5Tnwg@
zwX6h^U91BXlIUh#Q9-1Kl|&KlKGxS%3-O4x<9(2RRz*Fa2Usd9z8GY2DRTOlRbx{@
ze~48}dBG9Z7$t?Cu#Oi3ZIl&66{lk?WhiEEoYmnBzb9BTXp1w+`acR@OtC(q{M<Cl
zMAL20&Y;WEfo;cw-XXR(RdgI?cf1BmN7!DJrE_98(hKt_`|eR-9%Hl5Qvm5WJB?yg
zC)lx{LFOb|cot|b>`_{Xxw1912XtfCY=?*k`&=Yip6sd5(eh&V^#j|RJ@yKG@?mF~
zF&1C;y%#VRKXyPDECsOhsD>$!J=6-l(`^42p%BC#rX2ejwz7f(xWR0%5uk;zXVdd0
zjO|D7gK+llF=(7+AFl<8V9%xSOeDLQsvV=)rK!-5X1`8r@fh~G3Miaox6*<)mi_&U
z;GJh@e}u8bvlUeTeSw`b1`8M2$r?x|u;Xa~n8@}-i8xN&v%gIM^Ah{s0ia!Bmwt~a
zNoJQl07+rT{0|ye+4D}}YDr}$(Nj8&ok3xabT%s=A{p%63o+hIb_RvNve@2~-_B+~
z`Wcuv*mFL_kaE~x(|$IWy`Nr+`E2Le5V^@N62n7V0o#XaObgjBeFT|XY&{d$#cbV5
zDBfoOqXVymy@zi9GWP5A+An7(Dliun>>=8>RkC~NiCV>;S`BiCJ*N}c)$C7buUyOC
zcMRk%+oKH7b?m`0@aow+>w$8Qy@K`*_igN7C15^ae?UjF8`&u{f!)MDeF!qm?4d8f
zd&usjz;O%vUrL3yviE-k4?EZ{^xt7S*$agrUF`Gspx4d5^Z_J$*r9ae^s*IZNcOS6
z=mpp#_AXi~_Oq9*0~utiD4_Y6ZEL0F*$~@6QK@0}ddjnnu-WN=8D%?<qBX`gYeB}@
z-reY&WG|*H{S^CCx)7(?E%X&Cdrm!7MmTVW=md}>C$a~vL!4JX2lNrnhq;h+;sl*U
z>nP{h=b&(m6Bi4&k8`?gc|ddKJUoGcp5Q!P3BO%9tx|}(a`Gd=bK_X(?SG2%0zI_d
zIRUf4^WdDM?<06~HXcOFhx6ID7^p9&ZYNrPoOfxB=+9ZY7778JwHMF|<Y+1SaGEnl
z-vkKauqfFV%n3M3UyBUk%zq2bP);bVOu{&2=|BtT9L&Mb6~R$c063Dv`vG1=aTZbn
zG=>xP3PyO2vt%CBV>weUaQi&xXIiAiaduJ;ES^)vfcgc_Q+!}1a2o#xN+M^@a*!m>
zRa!M%;%t9`5}21ctQX+o6;9KS=uPGfB;vxj%DG2dwp7lMOVGc@SwIWk>ztkR+E3#+
zGtrsOSw{)IEY3L|>}GS8mqGmoXJjo}IUFCln{qj?r-9^g+Mj~I`J9hvDSwl*KMEoR
zoHMxMZL<nFxjzHu7H4-Cm_?kou47EaoHwap;x^~^Fw8{>he`hotCX{W5(8x%4V6Wg
zbL4cGq=K`|424S0`7n?w&NDecso}gz`^H+15AEyka>BMlvW~;0ve|l0csR`8<FwIc
z#de>A;sV?NoT-Db)WA7F;jl)Ilmb~zoU-Sk-^|J4!0toNU+%ze;k-bZlU7c48phPd
z38uq3?Hu*5n34|8`gG`ZaxQzrnJ$jP2=#8x0NoCKoV-==;t?l47_EMe1AXygz{Yu_
z26hKI`4qf=%sKP{Obl`CJ_6`4XT#qB9pSXoit`EQ!U5=ya@N}8Vj1IjXTXbb&eS+M
zCph6(fHuiluY=?i=iPtMn&yaq1ByNO`IW$Q;C|8yJx6Z;09uE*E58TNiEI0URy#+z
z`ektV7<VNdYdFrGa}wCj+!-Q}6Wo4Uub<?8LIz#9FO-0|a;uiZgd6t<x;jsB1IN+n
z!QDsBcyi|#qvgfj*AG2!?shr=;lpj9x0x^ZEY-66ac^ygA%E^o8?AN%xN3@G2Xce_
z!92|^r-;oNZXT7426HQ@iZ+B>Kr6UVZZPe`!nkf!$r8?uEk@^A?(AULjo^lDgk&W5
zI%ScfxXE|Hi{|pa0XfHgyb)f+ay@80b)LJm1g^z#qx4kO9nUR$8sq|ZGznf@<nEzg
zErHucS+hiLc`G`TxJ7gV=o0tV4M-+)U!cWh3U?l*?yqw1{s?DMxlW@P_BAexE{N+~
z(QI_4aWj5~GwIy@R7{@19i^yVCU-s?dRg2vll1<(!F~Qu_?^T3mA)U9%k3J5Vjg#$
z3kI6cUC;`Ro7{a%Knl1|?ZQ9{xgAuodW*Z1igb#&bK<}&<^~>tdI`6MKBijAed-r<
zmT@;OhEL_(<U;6GaA$JiS|!(ys)eh#MTzte6Yg-gBau0)nmcqCpf%jVZy{654GDrw
z9XFpoy;;vqp*`(A?h(2I?{ojmMe6}q@h?aN_w}{VYveA|Lb8cFcL(e?bA^NGe8}BN
zugDheOp3X-a~p18NFCg5w4(3izD(OOTNn3FN}+di9T$M~aCi2?;a=_+zd^B&%Zq`=
zBW?%<sQS6zQz~G9%c1q_WA2NKAu`0}l)&F%?tKAFjBr;b0Q3p>$VoUe$~__n8RJIK
zVdQb{j|%`c!R?EO$Ru~P7Q87Nu0&9K-hz$5cHqtZ38Id?#J2!?h{vMv&tYC|Jz7V2
zMS&nrybnrY=_qfl8x)T5?$SIR=WSRGY-ip|`r!3R-V+fzU3f3%!jda*!&P*;@ji}$
z!YN+s|3KV%xpbp@@N7wx!T01H`fp>wD-c7&oA)+_2Yq-4DP!Z$W72270(ebxFy263
z1toe<^WHxK62v>k0y)FmG#_pU^OET$9>TkD4kki*uJpVK<2_!B=?dq)Is(ZE9+x&r
zk-TOrB%^ryZS-BSXx>8##>en}pp3*ho;L;0VtK|#aOOPEX#yH?yanHY#PbGTgW?6=
z=f@zDz<XSdRw8d~3hGI`+w^j~#M|iyyO()UR1tE8H$-2}O6EP71@kGqMm~mpm8XmW
zbSm%5^)|>{<K3s-Xd3T^3i|0hT|6vh@PeB_GI@=(7|!CoPNhECJk>`0A~$#gRWOmm
z)4PJ?^5TAjULNnG+wdu$_dFBWg*+jxzHjliH$kC@7yc9^i+LZnL*zDZ8=W~Q;eGuZ
zeetQ3C;SsKWxS=)fGOuKq1xpN-bPvkRPsLWh3FmLTq<3w<{kSIyc%A>1z^|mI_b4?
zmv?3tK<jwd10h+@3pHX!@A34siM`Kr+z*8ZykvTwH}KjnL8OWI&pnW4UTHP${~q!Z
z3&CvRMaDs~m1m@7LmThAUUate#{FTbgI7-faio*Sy9328-q197-8{{|AiccrKZZyj
zui<l8dc+Ix!65p1Us6@w0B_J9WRUmT|A6_JmwXjI4e@?$hU73W`fI4$MtJLvK;sE-
z8AaR1dG@q-nc#gzLEuT=T8gqy@#Zx_WSW;vpN_ES|M)!&I`9L?Lr4Bw(IAKTUI(Cl
zm~Za|^&@;gJIv@&{^9|UWBeS-*&pXO&<*R%-{t_x6a0BA;LJ%I-<9&VF8uSq0MwPg
z>PrmNjlVq%%v1dR#lUvw@1!t{Cx0WInDXMUG{J;7f5#>0`S42$(CN!xx)uKV@lVf0
z%b)K|1_Su*vCs?ThcpB8H2?kYfEmPJbp~@0%s&$bFGBdXAga&^<^RJ+GmKwJi_37n
zdlgKa<<F&>_6UAP0y-o41N01x;?JSgSv227#fUNdPw0(xo?lFH@i=}aZS&*#`}bj>
z7x>|A@ZutW9+e;`@Iz?Rp2(NbV<(B<Opp9a{Moj1XkO-<%F(>S|M@mFQuuRe3v!je
zfy&oY`7&CdU*m5PK>s>_4ZTg%_=gK&H=RGg2QP#Fg)>MdfA3Pbmc<{Uw@Wtv0PT5l
z_=A)&$mO4<iuyeMlRrW7`9+j8yvYw=M(fW4epx#73;D%<(7(ms`U6N2f8JJz7W02w
zgfZRbJLkcCDgUcE@VAWbPIUz3{Nt3HsNf$QflrnEzY_pj#rGA1+~J?0s{3mG`-cHt
z!+-uXTDAN+_u$N3{%bNQ+~X$>)BSg!KS0aT2mB5SQa15p{{XX@KkyDl|B(L{&1E;g
zp3c|w@V}wmRWJW&3hegr4^Sli5npZu>E|DzC&U1s9SakK{2l*;<YWF3`cDEw{F9Ct
z#4!J-ztI}uzrO$?PxuQlGTW?CelTt9$N1`<&>!dbpM>ZHKbi_8C;1oNg~k+r^VcBL
z{2!OX8GFIi9Z+x(JopVFj)IeU7}_DhI2D;57MNefc#jCqs4*lb!Fh@@92GS0g27{g
z=c#7&xL^xi<IaKs%BI;)2#V>8r6&cSQEj@5z{vwJu7ZB5UvLwAP7k<K0tF>!-33!;
z(di-B=!KT2AlM3?mmrC13cUqyzYd;{z|)G!_Z7T%9w>f-CN(<!1$Apc0tB1rR}K_>
zLLtu6f-fl17i1H>y93QLg1uCs7%bq>t35=Zp^bg0;63`$!vufa0cg13hZO)lD=4Ki
zKM{g0fzXc>Xnurblt4QSk!Zmei!miJg5VE8&I#62JUv#h_W(rB3-UcM-Z;UNyO^1H
z!7+QdeL-N$p%>>x!ADEcn;@9;0SqPzUS&fxNwA)tdY1%W1;VGxf?i5IToE)DfR`-T
zkc7?@!OBcvUlrV^b$+Vg<1J9QCV28II@1N6RN<Q;sB?r~reMt^oXHa0rD}w1!NQ9W
zxgoe=qiUucL1+y0a|O$(emzf6^9g*)7p$X|-%WuR1vd)>T~q;AC`h5=f?I+%y4Z>Y
z%EeGG7PQsF?rp)Bzd@lyaF`aerGgiph50gp*&piVf?ysxD+JsKKvxQ8Qi7&Rp#6rz
zKzFcofqu1s)sEg8!L?X))(Qe8(6}queGf2o0ySM;^@2S^uzOGNyA`1K1t+Mk`hg&V
zP8T%@_S6EUQNU@0i6%krPPCc@YzoLd6uf&03N3<bba}K2W{SXT6NHBSm;V!d`4eC|
z1pD7WZ>QiBdSQ17I4v;PE$E~YmL9=j`T|m~pl&am=@Vppj@Bc=k!uj?7xdFYdq6Pp
z7_C8pit^Bp1-o-0G9<{Xf!$$&$6xSpMDTPKM4kvTC{{5lNXGzev&IBp)0%o*;5`e&
zo)D~0fXt-ee=+c4N)SqWt!cqVsw1}-@<RdYARIdd5l3MzrArS94^WZZVPV^HfF2QU
zqtJnqFljqPjtWx`!nI?<yjRdVF6@p(%URe+>-!VJ!)g%QNns3CMYss9F7Wh}Fr^VD
z+=Wq-==2c&LdRA-h1aOO+DkY-9~$05J_T-kgz2sj@fE&Gr6_*FcmJy%5hm226(DS-
zs)j&eC@u0%3qPkq-ymTC-S=mNrzlGmEZi3Ww?k~g4RU~n3U@8V=);6jjbMfgH|imJ
zR=DW`WFmyGd;pP1q4&2SQ9{`qTmsR;885)m7~!j1A$d+%Ls73-;T1J_=Y^iLF$r<P
z>EjTI7kXbq>w+-R1oex;>JdmL2&3izI#Fo*cNo1%!VmsH^ODe!;sck3Oe%7{B3zjW
z>||jk`II93k)pU)h3<h6Nfq*+1MiyfYbuqvF6?|6Bu(h9hDf@wm!j+$!g+MEI$PKj
z3WXcO*nZ4Kj*zLs%;XB+qbEe3@Gsj|VCM_t&q4I2Fq}$K3WWR9pkFBbo>FJGg!WWM
zR3yAjVVGj!&eM>*E&QzpQ(7WCW<Y1D@ZaZvRwn#u0n{sn3JFM+aFkL=cZ3oK9IY14
zrOKZg;a!T(*9yfS1NyFTgO>6Sb;5f$0aGt5p`6z}p_!_Q?h6^TNPHlifxlS|LYMUr
zX%xz~!+evl=s9#Y3mYlI^iX(=f>15OAL$}*75dQzyG{55RpGV^Q>l!$L%6UJdY!`6
zl>YA$Mo|*8TX<7PUp(v)`aca%dxhb4u-hlh%R=js@KYWX`-SHd&>9dvN58?K(20Uc
zkA)|qpg$yBOzZ7op^fTPMuaXDczGfmqE7^m3f;I685920hM#v_7)Bw-38B9WFeioY
zWMZ6C!h3fA<==(--Qb(OXg-}0aS&NrA?he{T#RWuBx-Gg#$nL|dK(@QRqO<D5|zvc
z@2IG86bi>g@B9FR$3+TCyEuy?|A7}LMA7spJSno|L)}H>?}3rIiY(7V-A%NPDxFS=
zzSV%(+(k}lV0wtYp_HAcC`%4BFH!B&aNk?>+bZyUM7k5`^cAhAH=dtpm{wW-q8-(+
z6d+pjJ0t@|-IPZ=E&Amrco8J3rR??@(WSe<3>Fo=2}>cOZ3Q5qq7hn3go*w~6?5S>
zQT}G=M~Y(TX%HnEr-Vtg=vTS{Vnk0u0D4a3uoj)MqA$kb%z2T25=_L2SQPY*7x6M7
zazP|WN9RS+CKFl-qIDFeP81F5fRZGtr_UQ*61BSk<+7-$2(2q3Mi^SjBHIDl$EAp7
z(|-4=Xva)wq>9uV0CP>WnNoe%MPH1<Zki}68lCAP%S({V5V>*C$`t)dQOzuo;Rptr
zEz0)+xgomv7qD|gYw470u4p;kIC-MxeegG56u1Gro1(xmv<gJe+NgHAP&7`T*}EnB
zhHCkXMC=r_ibdnSz`iYtp?NM5y+kqhQqgW&6PJnPRM1u~+H)F%sSvpzhliD-a{B&S
zl_-?f(lw$Rxlpeat&0M=D-s-sUY)3h_Sf~InN;O=Pc)HegE#j@OEV$!Ky-j!xDBGR
zPaxVT`jrBKO(HWT_nJi&8=?46^denXEuzo}_|z(@qXRZ=qL+Cf?V?X7K{`ZM6BIf{
zu2X1riPEnDtXtH478ZI$WoO`auc$g2>V2ZIGCFbiNK`^gsD9CnH{kw&Xjdv^21ThE
z7}{e|83#if5*?r%?y%^<T$mpb1yY&P6H(S(Oya0$zaJFFM3L`;H!kX?#ruS45yb^2
zMMsLDHziuP6=2h%I67EhFD|0ecn9%6XXyRsD6Xb0$RTlM6PSm^0bc>_i1_wwXgG;o
zC{uY<9J(AD$Hbf0!0vJJ8~;MYS-fT+$O*BQUNR@ePVd9Ki}+(I$aED)tDxs5{{9|1
zPl>ltS+=`4h6zaz@rG0oPw~S2Fl+M?+tCKWTRcY5Cm(SsojdjwcTugDpV)gFVEo1Y
zZvr$xJWY?gK=B~OZ%&I_$^jE3E~YBGGvZ&U;wxC(PD|?$@oTi63Kf6SfmWFKd&)qE
zi)~(LofS9jgF=LO!*?(rX%l-=b|6apwmW|9bK)giU_MryMn}`mi(jFaah#Z6iq3fP
zeJX>wApUhF$VD-KE<h8+19ZbDicj!BlEgoqh2ABx%Sz1CWpTsPAXmhP?BQCnxO5%t
zrii^L_jFaf>1RNviftbI0dr0KG^LlXi@&B5v}s~fI!vUC6V8BSh`;;@BvZWV0Ze3x
z9kM{O#ji=Be?y$U2qtpGGw8b+xncuNNuJo5s#^2Ki|OHYQ~U`FA_e02DY#fDp3=dY
zTjFiYV6RBbv~e&C#p0IRFmYS#OG~H{amxw#R4T4}7ieYTR6Fp>#Wi%_SBO7~gr!RH
zX%0ZE#8)XRa7X+Vy^O2H|I$@bBmSZtlC|O%S_IUKwMul}6PHsx$bIoN6}~(WFNuU}
z4dT{?w2W;Oj}F1NCUN=@oM{$!6vD-a;$^hfYZ2?Ix};U?M~kgCaV3Sx+QrT%;b@1r
zimER=#S7?LpIzcL_dvSESE#t9M|`ybV7+2h0xa~2pL_v@N8(GX;cvgVei9Z2#7%3d
z{$)`74CQGbi|y!q_mH@b)*!>;2YQH(h~qEA?h~;ueSd9Ke9#?aOswCH&T;YobwgxA
zTutXGCdC6(0Wu~2au{}}#j&0+XfK)91>zt%Ov^z>Nhob54@vI72e%JPo_zHj?!P0F
zH58n2l7!R7;;3ZRdU$b6Qg8=o$0hm&&~TOv?*`}z$zSxtxJvd=9i^M3=r4G2O7idm
z)ZHbmwCwhftfbOKPs#1`==72#bzw@pC39bfo{vQTGoXDXN&f=cPcr*`@NE8)stTA0
zkes4{21?HSjn-+&IoeAHNlLe1ydje3DOeFIvHJ`r!Xz1#n+TWmQWe};iIHLz5fVWt
zKqDnN4lofVsXhr3E!h$duo%fMdV8OfETr=Vv62^dK=QmKn-aQlHc5*&Wa1?rvoZP$
zl8?6m?V{un57-G3r<dSGq9lpxI+7$E6KGwM?4)b%vc&!%K(9ywA~CdN$qb61r${V0
z0J|#jc!*Z2#H$f{*ChApOy_mUbz0G<N#?R(AzhMH36Ttm?H{Te$dt_c4Ki7hU36V#
zOD031ctheq&zl^{bJG}ouH=Uac$g>gq{vjhgxinSO^MG8m@klgwFjVu5_c{XZb?3(
z?NpJZh6!G=<c|vQZcCnf4gQu$woSo8nPe$_$*Wwl%r+CWLed}wvr^La6`ZM(#L%(!
zI}&d#NVVkoe_^RcvX};1D_KL4n!A!;XoBk`9+Wbxm#n%9$$Jv#*MWUsqMZ#d9!NUr
zN@$S$LOJJVNi!vMA4)zx56KqE<|XKCm83XP{-I6c;0Mrl$v^ba?T{>`r%0z{gdQJV
zlKtLrty{ubgJJhb@~Ob6SCS_{t534R1tO0mj>~}7FY#^!%7EmrCMXO_T;~Agv80fV
z&LPQPE1)+lX{KP^h~x)~cs!Bpo}dH7qmtwAgE=NCrRc`Eq{9NV2}#@ukV(mgVpy7z
zc>BTqX~~Tv0JWDoPk=Z`PtXp?QM!c!+lQooOhe(Y^gb<*jz}eofaxS{yae7+>Hc>C
zeM~y<Aw-T#7gE;LSz7uQ)t{Y^&R!1_C#C(Akam$OiXr1Fwa|eiH|ca8&`wEn-++d@
zw2lH?9?~nZ7@?;$B^<;{YRv%gmg;Fo;3L&v$9R3EmS~L7PdejInD>|F&=nLQwa}9#
zQ2GaDPfkl`Mu2AvlG@XWtuxX@DnSgEE}*Pyi1b^Eorg->D6SVKU2q4Y;Zk2pYMhmp
z_P}6-wA&L3k<wf`ViG0g2LL5n`sXGn#7O_3cj`Im5-z-tm1fbV{k-(U0AR*RFAQT4
z@zO_^(7IrgJ|6~pQTlZvU=pO;uEA2G)R%%-Nz!`Cj9!v%ryKsVwEiiyu1J5Sdevkp
zHxnd9`lubetI|r^U!+P^_hIRpG>(!X*QG;L+?*zzUJuE1=}+_s&5(Xak^f97^Drc{
zq&DLoj3QfllP=a=Da#Gc<Vj~L(U~v3NP(N1(i?hc6i8?Lf>$X0ryRUn($5cpS0ue$
z2VSu>IS9Pl(t<o#Dv_qs9aAd(nznIe(ukw5R4#R-O2i83bsy+eO0(-hs-%x?S<tv6
zz4aL8tEIXN(5R8dJ%Zo0(gX|U`L48Y47@t&{m-CZFFi@S^?TCvufV%6{f<`852PR7
zfL?<%gVH^X(#V&A*(9By?NqZg{R>DwlqNrdhb_`)Xhq*DwQdHlO&ah4#b4T`&r|-Q
zLt5<#nNH~ric)k*=TZ!<TWbFA#*<z;29aLr=Tz0wCw-a%V~?b!7lGC<-9=Z@fb<o5
z$qY(wC&HP>(&%RZHYDZ$h}N+5G?h1vNJD6I_C)GN)ghzOnkmY^k4c&RKpU67yAGlg
z(%0yMnw0LMr@)jn^bLScOP30uXfIP!4#+{)MHic+>{+@H56NN@(Ro-F>44S|+2A_p
zImv=)OMFx|xCaA0CUc|L{&CqtJvyCbZ<eC-gly<Ts((2t<G%uZ7uk_CxacY?xepmP
zS=D-Uo{}Z~1iS9Cy?=w}A)7-RDNkASBpmgUJ^dzlKC+MK=J1t$^b*|mljYOR<u8j_
z0}}zVJ=Z}3Wr~&PJS|({2k0Q#7@fd9Ba^<3PFt|do+@oZWZR?B43(LvkSk2)L$Sti
z*-Y~LtZdh6n23;lMyu~g*$Z^!Bub{H^=q_jfdZ2kBa4z^*ym)w{vUX;vR7$ea$fdx
z7DVD?{gj7`mz57f<bv${>p;0Ed-gP3OR&lM*1<%g?A<0XlVmJ5>|T<6yaxs^%QpUm
z))m=k8hFXFOSIiik<Fm&*j3rDZ$U3r*1Hoh*JKM0LGrq+lT4(^;%Fb1E?fF8L^5QH
zPN9`4`-#SxC0o7<DA}@t8ju?@+l!PD&XH+oxt}XzP{1comPFzCeA%r3gT_snD}{{<
zWv@MgiCeM+2Xq$6c2FX_SoUER6mH9&p*>HDjFAe1rLx{;{7hxCxHPoNW#`{Qt3uXH
zN75=~YiXNMB?~?eNAJiiHoEkxWv%p5u94+W1EyBiN*naMGVW54I@x!7piwXD3xK72
zGCwU8@5_E$hG9RDA<2guPgbxIt~JUUW&*59cB&S7&9bLvfjpG$r`&IgtaU#~tE`0*
z_HD9X=;T$q>`)E8|2kwNDKOC~o20;6m+VzaL3PW1C<W<}-JwW$uk3C5Vf$pEU&6#A
znLQmv@0amE#as-?-lkaApv)&9K0TJL+W>_j+23hU7?!m}!0w1_<uoLp$ZFpQZ&c<^
z>HjfV%OZ+@j?1EH^)Mm({d;&ZDQo=;qEoV}EXYjD-l~I7_HrxURkIxA{&W`Pu)Kqg
z*B+6V_`{%+d~65EQF$KSl*i<vm1rH8GgG1NEMI;R{+^J(o&<7I{+T~ST;y9NXt~M@
z5Hz#Ra+BYoefBB&dnF+5@;YD0c*rmRirMp&AE0HOm%Mi#2IDPf((BAe{<RN8eC6jZ
zg6AhMr=63(d_yTj0_3fWVLnhkNjb&S@>jj!MUecZ@4-7GZ(fLb3YPz0KX@VX5=ySw
zLgk&bR1K5M_W~_kK0>$ZS^3A$f<(wSx53j$`L|T;7$pz=5c<*b&0FAFjNC^Aa!&5C
z93)o0&JC90<@eqO$_4p%E1+;u{?a?>OpxagW}-ZR-YQA*<x>#3Bp+13?aMZ~9o4E_
zk>9!ik}Q8a5GGROi^Ad4Rk?aG^i$=!-!U`S<ndpET$kUVSbv&)cPwDi<)TS+X2@3_
z1$L(V&n4*0k_XXkm@WU8iiK~;H^)IFM?PUdD_4H|9De0I`DZLx$d}uGV59e@{8>jd
z3*<|_fnuRNwGtY)<ZI~`FOqxeAyO<qPFua(@|S57T_VqL08FV|{}*^=^1Ut?Ou0NQ
z4Bl7B+oRE0DIce2V3qvpM?kqF_xT9CYI(*1sMp9F=;c%^|Il_5Q*&27gR*3G^4JF0
zt(R|XfXqF)oIJfRPdo**2lB+D&}fh=zkp<;Jo*|$n&bvEI-BK#vtj<Be1Q@sTI8dC
z;I+#yCquGBZm?jwI^~LsK<SbXQmn6Ap7a|?kNnWLo}$s^w$c*l4a$q&gZ0O9_iNw{
z$y>W&eONB*0~wKTqJp(2^8ech%u)Hqmmo4Gzt|5lF8`L!@lMFMp90FHJY@nXQ*tLC
zn4OmAFrjX*_?W&h;GlRs7gOk{Fw!g^Qfzt&6LVORYC8+XBZ|#5=}w9*RN#74vAYV`
z#}v7=6hE%;oDF?v#UvGOo=~i(x|frRRyIcMqPSOymaBqK>tr{@AGC7vQ?Ptt*I)6?
zERX<29u>m`D)h8pJgpG@4A+7bJygkeM)AK-X%8H%xJ3`P5Jl!zv_chksXj1FvB4eY
z!xdX7i+EPCycrr1iV|ADMJfziz>88yFJctYir1fj7o*_N9_gGS{|=mqRXnf<Ij_k7
z9SU)Z^Aw<sSLj}bhZhvAuRty;_U@$^RD$9;DsE0x_zIz)r0}4{!zG1@3L7pfwo--L
z6~$Is`zI@=4}hd77<7E;s={|Q29v5tIR+Eg6qioH#C3&@Zn!kX)8E2;x?<)sj4VUp
z;eyUg1!oopn5DQyORXG*7^fg4vvL(40qD(B{6wqge8pG41N5fiFeNw(6x@U06)J2h
zz}!;2@B?^73VbvScY|UP10p4ga?jB51vbHDU{)yBJ%JOIit14~U!{1Ds@v}<M8P1{
z3Izks*C+<*%~-2gUJsDFiX_U@*D1CqW0>`dq`$#?pjb|i+6Kk<8jvPMLl)GV6>(c&
z{Gnp^5JXxO?0%3|g|8j_Yg4SZT?0(J!b0)r4#hK8pmi#IsNSVZ!Ha`y-HMAeq8`PZ
zAc*uTGO4nqPw`njKp!c#((|ETp{KKw1BxlihYl(hEkWzCqUsF5h7@HvAj67zR3<Z`
z2$}(VPZZD7Z8NI4^0N&l#uUmHXpAeK$^+<xLPVjBNrlrYU{5KWC|y6T$fR(bgVI0?
zMMvc$I%jl9=|!<UC#5MIyratPH!-wh$~TU}i{naniqAMJt1Pf|LYcZ6#8t^Hf`Xg!
zwfPV^rChRw4%vDt@B9x=c_{@2knvVN5~Jm#WYKTtt1PX8sGsuXMVL~5<$5}|6QKO?
zAPfd7f1(nR)5?n!{SQ)F=0W|8GM)l&!OCrvi40NB^h7IE`4d&Ng(<tKo+w<o?*pix
zRVKDkEm?%}`4WsUQW+ZzW|VRty^*7p&rvB&jB@^N@Xje4D2pAd{NcZ>u=36yK#Nlj
zQ}Il^a?3fmc0uX)CY-sboJZGof^xMEor%hAl!r}HMr=dtk}~^8v@R>TU4Xu#OpO4h
zEm^tdHatyHDk;Z&RjD&zhEkP_TtTiW+bCLlT`8Xn&<v#$1rsxst7xH^r8F*u`D|t7
z29O)d#h(E?NBLC(TDi(6sld!rR)oXRd}R(5LElvVk`0jp<p3?C3YC{>S#isz%+`Yz
zDNo!7DOR>}pnqF=GX-`_l+hHcE>(6=)Tc~ouYnik%0pX$U7-w518AkvVK1huO1UKr
zdUuqYg3+o~7Eq<*U1dI1an&g~k<hDG?zsVSPx%==-tH@3`UD~ml(w~%Fwvm2J_FH4
zWgk6}9xCTN0~cGAlXOJ6Rq5yokv`?b+rWOLOnU~TUx}S4E^;N8a;-zki5DR<tn{Ui
z9giqO@50g(Wf{HoMwJN*(3()btcBf4rIxaOQ%c^)P;gK^u^q&)9aVzY0dq+8G{xEu
ztBwwV98qoE0yHO8EO~fJHJi58?y3>Wop`92@58*O>b+#R?WLN|fF*C$2})o4s8XmT
z#aH#@b?Eu2=F!CZtA^)6GC=ioFnEC~2inP=R^|B8UM@&wqO;0pR99#&LsTp1!U$FE
zyNTZ*Om&t57U8O4N<N-dU1&oqLRCi3n`qTBZ|KFS`qRKWryBfk=dL=@4oA<cW>S<W
zPL;X<mf}?z`54j#ReKTCFRIcmLm@%+ylnPbT%{_zP%x8JpDh5|C6(c0$Xr%Q{)EgG
zRX4>wl2y4)@F_+0<Cm~|P37+0_|yX1?HQ2IQbp3|BeGS$wL$QPs+JO{IjUuJ2q0JW
z!6yL8Q%#OQGGE1@GS8c;1McvwKov#R5QVBhTDsm+P0=#3NENja3dO3~P7t}R%2@~K
z5>*Ek(3Ps3OlXy<cvaw)tL$ytp<ktnJqvPAl}Ib-`>H-Fm4Bf6o{9w;RI_QR-l*D1
z<xfp2RSQ}VRrkIJuSNAu9VA;-v&q9Y)h#Bl+f~W*agz>}2OU)FR2`<}M3*Y*2o!o$
zGbzm9tBQ7pzkRAPS4zV^Qf1TJ^{ZxHhWP>2PReBus*;KT`dGEv9<B|k3~p!*t77R?
z^N4EoADEd@)zfsObxd{tF;K=;zwZNYLiGw2;7zK&qKdsKRpGyYo>na)Vz1WIBFsVU
zPr(OA^-2SM$K;TD?p`P!R<EF%#3SmXoltaAFYW^9QT6M8!~J9Ga=NOHt1AK_>8u{6
z6ojjK1y!e>Qtui8w!7MW4o2vq-trrGp6XW|(dni3qG+<WI-80U{M7CbFcyEcp3(~e
z>YW_g1_Y{oSAcn1z4tm4gVaSLkTYr?1uuiuUA6eNL)0(65125u4~1UC)j#$^<g9vr
z5YQsjnvGD8RBPUY`6zYTB;1ZxFQS!mjQWcxpqx|B-V2mi^|ED9IFEvLpv0+n(4hm{
z1$8Yw87`_zUC~TXJJUzh64jfI0W?WHSB=(XwYdSHSJZD%=r&os{W{Q6)W%eZTvZR9
zgI=ooqc*gzsedMeY3gvw6s4<I-NUS9sQ-@&*)r9~>0>!r>QfB3maVRE0PluP{i^^b
zZmQisz&sbItLeyNq54@$Yu-|KQ&oGBdizZ9Zmaw0HD97;P<d#nx~Lkw3UxFe>Xqv6
zGGU@hJw;KPJL<c%hpJY$(UH_zbq_@{@2WS`iQ_tT=USlLS6^Qa-UGEwXvJU})Y&tj
z(WuU$U|f?rD+?OU>aI7T@lb8}2coU&&!~{DP5n9Lz}wX|cfjjVzw-cIbgE}x$INu8
z7t$lFTb)Q>fb3B}p`!@B>OUya)URGu1Iz*SY}$bis?REc@>spjwgK2f>b)&s4y$8m
z7xP5@&NG<HQS}9?N*GgDz6X(Ub%hk26Y8?fz@AormIq0DP3=+;2TdadavU{>MDYHQ
z<`@N@4{Nr0!@QGb=0b=Z)eN2nIi{)XgXD3IAB7~GH8W#q>Efc9?1HGPW*Ozc-86s8
z;NmHb_jSm)YaZBvcxW6upzo<!Pbo1kP4OLw_-cNNN2i}gLxp?(n$5JO3DC@@S7V?i
z;uUlTY38^?;f&@_TE+!y$|w>Vs_B@I;f85uRMHYST;qNMlYdsT@*9|s(Ad`iCQ=je
zHl{6FQ%nboVl+QJ3xnr0^XO$5t9i#8BIh+3YoHgWd8Hi&FKEua1A`YeECNf=@Msm8
zs1Z?(UXrGVzUFd8vw9n5Jy}y_0ZNMI+Iv(6cvbU0$)sx5Au2ZOnx>!ZUe_o?;9{C4
z=Q2pTMo#5G8JfR4!OPV2jKY~L&9x|yY>g+S_it#9QCWD7Mt&KVay9eUf|sW$vEnDp
z*O)0-TA=wmA8r?F)~tZNTbj+Ez)@R~hC}<{VofBSR=Ta3aTd%H%~}`emumD>;8mu%
zIS!a|%|bf+UZFWoQPxV$7e4{CN~0+NxuZ#-EL64T>wRd|Xhx-QrdHEJ8?C#V)>S~M
z(;OARe7$D(I*@ysKdCtOflZ^Cf=q*EVGc&$sA+!#%qGn<lqG4_NS}hGhnkXdjJ`$F
z`xSVtnj{Jhv}wA(gnql`*->D3Xy#D_r&IGT<rlg%i$b8#t(o10k@aXc-9~4xrsh?U
zKFt~m4Ls6lzXHmD#&*92ii4WB=q2-5bI<_hh{lOFQ%^Ks-2@rc{16W^rddZXnQ@Jh
z9?uh+(Qn}Pq-Mre@TN4UDdIe>X`yF{z4njq!E?|ySzz8#>lX%vL)v8W;;^=xYV?k1
zjdRiIq}^eoiie}xNxG1aX%D-Ad0adFI(&21whdttPG~i>-aV;ZOaFAqMeC6cMOSTJ
zJFwlf-_h3Sl(vRyecZLXC|>TNT}1B+Pwi_)xaOsOIR<WfYfIbF^3e)v0OqS*LchJA
z_HqI(UHrB8D7PD+RhB_NP`j}J8mF~;HJHR8E%Rw$pV4ll&0nx~PA?Qfv?-54!nLhJ
zcz;%ViXw{<+KJcTeWZ3^Gg?vFMJs_4t=&gYrWmb1T>|H{Q?v$-)oL2iiqkp;QW_{;
z`%f%-FKBxxVx6Ro@Pge-TEjLtb6Gn`Ny;nQzQ^z)S$kjw45nze6@hnEtDxXis&>R4
zXxFqWlVR|>RzjCYnsx;jVCh;deUu<WEBXt(Ol{|B@UpZ^(tw$*T_d3|^bPH%-4M;u
zs#b&KYS-n%M4t8@t(@|;71PkTsl8SV4-2$XSCB&OR1YL?X^ZI!EYiMv86w5nUvER<
zws!voxK^UArt;lV?QSDxtxWsoI26jYp_|aE&@LH*PnFu|s^GS*O4~zA(>vN!N04f5
zLlb<f(PmY`QmwX<0kpf?iXgP=w4eS4#d>Xm8N<G(eU+BP_q8rFAo4()=MOI$w9yRk
z8nxojfzqTMrrV)e8#sXr;-PjS1xQ-7GD^?4Y6Ip%ug#`iMe+7_?O+O;9oiFAE8D5<
zqL@*aHvb)nc5BBw!Ryh!<byHwYHR2v(WmWS3WJZd-hF8GYgNT)4QNAX2{WkukltU9
zwKXm9cSzg&3dpc_Id*EZMzk-{cNxdDA5&e+xYlM*OM?lmC<J6uo9qh{Q`-Af5Hk$|
zP<tKgI6574izxr<s9Uob9v;$-WdQWBPDGEZBf8pts5|LGw!rP9I;kThkLjM8K<9Ct
z9bFgBx<P84(Aif(;iPV#6wofZW?L($t1j|qXt?Q4ehryZy0#Ly=&qZyA9g)-N9oz^
zsSE!D2EBA66d?50Ra1`CM^|_XlD@k4(qY0+7xxUt<gYtTudx8#2NVzu(m7B;Oo*<V
zjm}WrK3dv_=@!HTI$U?AlkUH>x?7vzRD_OCWs{M*)|*g_(#2E2JX%-S0TVGgEv1jo
z>0bLCFtNHhQuupbSD66yINgSL@ZxpP%!Z>Ebem2>{h}_EK1PzDTRslSMBN1{n@ZAM
zq}}5sT`OgAFYA&NR0eTH*Etux$+~;=%umt%L3N8)b%V9Ao2uKj84h35eM(!(>$<|b
z@F`7~9R?HWy44im&(LiuLT9F~nc~k`y2ErrG+XE91(X}QzMJ6X=w|TInX5Zb)h2nm
zjf>%SzK-`ErD1RC&VK}%0-fdq=ojkV>xLJ%bcM7hEYiKGz?h148~mYhTeqIJJSDnZ
z0Z6H?(+t<jbW5lbv|RV*pHQgKO{sxWsrzyXP^xs@baUL%%{l?Q)w=yW=+)@%%mlAi
zR~-a(+g)Az7x1)B_xolr8+7qAV6aIygCa`JI@iPCJ=6);L!(8<qjM3hx}c|EqD|*T
ztHO5O1{sFdp}RW<UZ>6|hU6pN_wn#|KzE6*{6XD~M^JdITag5j5uMu!Sa_l<pcwC{
zO~<0s?qj+a$^5wPq&;LNbo+bJn$(GWz?;&Y{|aPU*H7DBd;Mmb5(oX4R5s<P&!FJM
zA-!S+6b|dhnlYv$`gK>}g_Az79OS5e$$nrS(}&TX{kZ=69*8*W86RO}C-k;GluSOU
zcTmC`7yXi*z;@MpP$`R>zHBzIPwC%apwnHy{XU3?ehFO=o_bG8_<HFTrRen5`|JdY
zkKTJW#_Owh7eU=m@A?@``0F=31PRc8Pa_M|pQJqXX}vZM_JZ^^wkc?w(XXwBrC@#B
zBPfRGQ_TPk)$jTTBuu~L7j%Z}GydCj=oKooBJ{;En9@l7u3J!#(z`u_&S-tD5ZEz#
z9u<k7)0ce*6046}2uIKBZ975Y^oy3knRxv=y0tIppI&Q&Qy2AeFX$)e@!vLZujpT(
z1z?iCn(D1C=|7DF@3Q`@55c>l{~!gtWW7BlbyM_?MtE^muepX+s{RXl@m<qDq(E-E
zzE22}q0ih6UZ$SM21=HGKNVzW>y1Y-`WyO=leGTK(Kpg2I#>T_D`fKYdk<k0`TAF4
zA#+n7L)9Y%dgmt)Dbznt$3brC!}S<ikv^B|?u+&FsIL3AzKo)4CHezPp<b$=OOMbp
z{SR|tuv{Na`_&4)LjYQpdeNIusM3FpaxEOg)EA@yrdq$R3ZzE=G3|M3^_z}C=B~a6
zuZdZ8`WNVQM!i0`2_pCOUO$0%Uq5NYTs+WMWJ9Duze5F)M!k?88%=sY%5F64PhWw-
zhx%e~=(XvaXi?g(Uryy79s1#yz_WGg7gJogOW#NPnr^*~GLSv`KOX?JSHIZ=nLfRL
zHs<1yexeAietr3$XbtE$*+FtpKTWkSkM$WQs1NCX+Y8>X{`)pe(1`wY6i}Y%?Vg3?
zsJ@>Z9n)W?Q1iHcC&jKNZ2GP70G-qu8{x&2KA3hn)A~Y6JKGyPCII7LI2DXeM??N%
zh#WG!8-UKkhC?p^?T8@=kC<6bhUGSRan!KE5uL{jn-f8f8z#PoC1=AwloB{$=%iAV
zlZG}2ptu-Xsbay^VEF!hG~EoVdtmUC;Vn86=Wgix7y2HCzbI_uX=ob+wwJ*)fFH)&
zu#68yAH#<ukn}UOdqUmcz+VNC07Ih0H}sXKUbVeXFXc0ap-m7CHbg~3Cd8m!1#dzP
zpVB0T8P-tPKiqKRJUY)B3|W}H2*W-~BSjiMq#B1PgIx?zq79$QAQEG^at0{p4KZKB
zQk-EnB@5#X6@l>Zf+6l@h+H(JOae2(z_(q8Z;6IYKckss2=j)_CBrh(Pd13$p_pRW
z8i+Z$YUnP8<aNW`w_qvFus$8Gr5j$D2VREZDY|qs4V6Ekm1S_EY0EZ*QS|kOA^s|O
zIfhmWG3FYA*$~My-1z|{-{5kB&X(OYG|`j1z;JLmL<<e?2g2?xLskb!kzw^6*ey2v
zMN9hIh8HfORbr^4`j%3|idoPrGc-L5Qf_#T;#C!f*440EX=vy}tIFU*x8WUw10}ku
z4LTMiYYYo_0Ib$<Vk@03yKDF(6f$*&H{J)SH~9Yw-|iVo;z8~kOtdk1V3<MCf(C=*
zYUno_W(Yx=46h#nXtUwTmzcGO2A{1UEe6luq0nlmphR(-!Jkr(?FKC$KShTjlg8O;
zXnh-<T?Ty_y;QpmQ9q#BV^|yor+N+ZDZJ2Ua9;z1j|@EmkbXl7JyQk@i$2G&2Mt+E
zA^F&F*8y`eWU$gZW7v>MxuOxn^f$2k#4tw>y-~wj3JZ=I2B;!)+>mPmZ^CeiF3U;7
zQ<OTiO&Qu~mo;tpnTjLqjbAka?T~S@0E&l=ht7f=F|JlY-^utu3(2F#5hhy4jK4R)
zi{nOjO3XMLSywRKCyXoUS$5L+9UYx=F`iiopInVM2GDXd{!8_!r;I=M0>#}pa0HSb
zHsjzdFg=a0Q1-;j`1k98@iux><kH93Op82Uqi8-%_!(37Lek&Z?~GP}@gI8l1sZ?<
z7oDe#Sfb)3WxPTg>@!9N-HpM<n?i_$82_cjX{ga>Gep9Se^9AVxN-4zm_KW@P19W!
zVN|yQG}4%S5ne<Y*U;i6+Q=G(MvU>F{otK9j=4i4&dB)=GaGMApzz)WqlR*77mf2j
zhNB5aw^w04(b(aGR+4e+4YV#97rh9BSBzd%+>mTM_$ORTF@CZZdRL7JwzV*rYW%hq
zCaxPhr=XE$ET<1Oq#J*|0rMF~trfgX<0HyYXBq#cuv3olmkkifH7-sDXrA#a%0%WH
zx1K=jrg6~*C=?h&mw^--9VqT|%b3rCzePs&cNkf*G1MFCw~b#ev%z4AG3G-kmKr_i
zJ}5KJ9EXW=qox`96~@EG(5N)d%!PiH(MXbajDZW`TD9>*%0$)}KcrIITH{7qSKT#U
zpt-0s{`3V*)Ehs)0<e2Vh6KF(M%8=hd|>>21eguR{w;L>H5%PmkZCr;U))E=l7B(k
zjL)3`cDpgI1YUF)&6&{eG+Jn<+GSkuUxwOv+zvzQG5+-iKzogfdg%2TKb--EM@A!s
z;QEcTJ>d3$@m3wchKwI3LuA-ENv94*j6bZQm+BLvYzg#7jm0#yG2?rG;FlRUIvOw+
z6GrJ9P@FWLS`Ec1<NtQT(P`sn6k4)32_AqrnnIq3!9%7$a-ne8w0Z<0M@%ihLcz(@
z^A9W?H7#_3g;S=>LJ)UTV?9JXOkO)6V)HaTa~=l0Oy69Cd2f^F%K-H=U7^&gzbW`3
z^aD&|zXLnabaW8B)25kvNCufcokZ)5X~#u?2AdX}(HUZTjxvj(rY?H>hndQo(F!-c
zo&%J#rnhmHU{-|5tqq-#rgs-&@-Es;y9S`2VET0&%_Ni4eGKN3sd6{aE}MR)-SZXG
z$wjb~Y*IZ7l45dy2iR9lZ@vi7RMWR@7{xVHSuP~6oBsG4B55XlHq_HiPE3eon93=<
zmub56G9<H1?G%j7HeLTOePOa4qJ2h=DTMZjxh7XyedL+W{tlRYQwK%FZ<-ot)lpzN
z8v|aUNqYqPw@hD$gI8pF;~?x7n_6E1_HEPWR*00C{ux7Osp${Op_G|K<Y>8R4n?~w
zOpbWy&Z;!!=YUsb>abCg>yAl5-c+03n-6A<X$5U>YE5@1(YkAjc?8iq(`ni$-#0BX
z0Q-Tdt_+<GrpV0@X*8AlVh)>39nNsA*%a{t$U{@nRdlwP?i_&kt)}by(Aj3vIAUhn
zO^;}i)?xCyY(sCSsg4QKWs<g_x7)Oo$|ieEpHZb^uj%z@80<4WI|NIQOb01>*>Bpk
z00SK`t$qzx=b)+99-WU(E_b0mWNL|o-mq!<AO<mFV(kL&iAnQ+@M6?d^E?#BOsk49
z+;P+Ev+2LNPMA{ZQxcP=B~O7lWn$8<VcPTpEnMx*jVs`=gZbxO5OFj|{SA>r=HLH>
zrNic9l<+uW{*$UloXn5trFhhA^+Bhzxw{yHIAKm~fEOptp_`!RVpfMj&(-{^6C~Zt
z%XZP(vQy?YbgIkUyy_hg5A$5wvU!?!{|_2oX2Hkk^ft2|Lea-;p){PYId%*@Kl5kb
z!Y6-osTqR_Fv~8ZGtj*6Es)b@Kl<&1%-&Rza>mR<_;yyXnH_=75OazLP(sahd*OvG
z%>2W<a5&tYMOD{l%^$WyBf`wD#+V|_j6~RtGS9KYbVr-J={#19Sw%sibLQM1AQEfV
zeT2^Q=I<%k9%tSY2FZAH;u|n=!Q2@N=!@nJ*)X4AmQk`Q(H!o8&LlH~mOz(m<`CMx
zUN%2RL9i=k##;bQHvhRCB*h%ih|a6#DB35anl(Mpzh-vLMeDk`c`IB?GhcoSBI)K(
z17<D5ET!OPruhl|hp#O2Vht3s&9~?%!VU9DTJYwW2M>UkYp$MvdY;*~Y8`04`P2Cr
z(@nF1>Kh8oF(D8wG{;5)?Uq?hC-IBSd^&4YY|cLj^QGpODE3xi{&p`+RGQzX=y8=f
zm(~e)%%84-!D_R6C@^cxTZUk;)*So;Q0|(aX+^8f-1sXj)SFc{if-OB&+5h`-Zy*p
zK<0t@8a+%J%$zn@YBa}FJyDbSw_}iOHV0F_{-OCG1qNEoy_<m6YM!RRO`AD#F}!Fu
z_fhty!<_v!6gtfxM1gdfWmAysHqZ8ihdt(x={RJsxh9!n$$jQw%56L{x2=Vxe)H}Z
zATwZ2paUp_=3;v6JT{BUpg&}e&qiz5ygdZ15%Yrkz<y%>iek{CX3=ZljhS^*02?<S
zq{!uj+2MIum^4?@_jjhuZZ%MtHh)8VQhUqIKB~uXuw=BuZ%50k6wy9naiIbzC(HO^
zkfWB^jnFt|$tVTyxP@~D#M#o$LZ^#m@hFI^#gAf*ZkCUG!1J&ipiAD<vhHQHye#e;
zF{9p=+fe}Xv78?R&)4#A0(b$IH@4FHGthEq8qL#|CG_|Rviw2;lrt7zDn1CdWG@7E
zh~-7vUxZr9w15e-?4SpFxMiF^#CF!wwi-i=umpSxkw^=h3y~<xflRcbEfID=iLtmT
zAbHO6qXNT@wWO8<^StHZ63mk=&Jx!S{dh|YJ-aVhHr@dCMaxSM&`PkpyAWuJ7Kc3`
zNfygFC|<Jk(eCK7rT#5kWmhb*$*`1cd5zwpDHeAMNnN!BSs;>XiKUg>HH#NT$*)@y
zX&snmnL#hibW7oUbY|ErH4mYYY02#X$+CP;=k&5I4ib<XmJjG*l4E&~9%;Fjcf8S=
zXW<pVwR{Vw6P-6LE^lFI1(t4lpA=fAD1CX$^5=h>e#<5bCKX$_RI_y3@*Uj{C6<?p
z&?>cLH-MB`Y~}`dQ*Ln%2eZN=`wb>4E#tSLSY?U7f}!29d_p1RYRiQVh}2kG?toWo
z$)d3FUCWVsP_MJhDuXlimRoe+-?O+Jgxd|4ep(eaTB<24&}5O*hf|v^Ur;Feq2)Dt
z2DVsM+RCBdYB}*NCZo-=g?@^5ODJJ?ST50*MmjB<skFGu67U-|x-Hw50IkQ8`YX_S
zEfHsd)@RvE5$#8o460h|w=^l>%z&l-8pxpKC92bTZ29cJui#rg+YOOnOCaUwMl56h
zXM^Gs3o8yo8?~%=1sSvaMOB~UmR&tioUpjnLv+%z8yD-WDa*2>;7wa{Y3*Zgy*~>+
zIar5g!(T`1FP9;5$olqqxOUk34ZRkQSU>B47f#k+HUR9Xwcr83j#<0tLOO0OTtVwk
zXX^-kyyb+o^i42NS{G5A%*8tAb69e<&IyMJH>-vc;is&(%3#;sdNl|w59_@}u;ghK
zQ?SCz`aZ?LysaT)==8D9$cCh^^#E1e`dJ;ng){!vRkT|Ou=Y`He4w>vn(n{T)(!Mh
z4YF#M!{8a~^AFJqw*JkAGa=Szub?y38haLKVOG9BV8X4>=0POVnnCf5DC<j8n9^wL
zUi!6Tt&bzYJ8!kpvBo%SG(7_^TE+BcPq2z9W{_x|OR?Z2>(Dg7Y?rKDdZb;puBNZW
zq*yDuF*R4MPf=Vi)!H}@GS{r{(;ncu^(o5Gq*-HV0hn%mhBAH`)`X+L&a`f#=WCX=
zQVzGXt;rJjd&BzTW1!?%Z`*_9S{rDen`eD^54?P94b^qrv{@fhokf8)w;kAp*6uXu
z-?AF$-CAU=qnuf>^&3iK+_pv!!S50)OA5QC)|_69zRYSz;mC3;`#E?~VSRfW9IdoE
z(Pwt6tSpM5-LY<>piZ^*+)nUntmo(mQLR<-B^2&jZSyO^th4SRPwTCx(xG_Iy73z@
z?_1-41$kigrR%D}>U|cxW@~a7+<$02NbklLtMhVzwpx4CAZ^wNf4JRlRnqRL!`iwI
zot@TG<WrY*n9_jV)&P2H^;lQZx1xHjD{K=OcAxc24KyBEmlVRcervNA><(B9>0s@k
zRU(GyW9w$x3lCZM5O3JJg#xxC*0#R@`o#J(WjIHzf!>fDvt~wtH*P)sGoUA|NdrKc
zv`X}Vp0d6}<ya1OfsK%Kv>U%e>(4`W#h(J($&OD)@{Zco(`n9QcFGWF9Jh1(4A{<g
zZ&2Fvgx#TGm_KQkNDCVmyPNch5?4FL3m|TG_Xp5<%I-Bv^|{+^ehGFx>~2wYiKpE`
zIxOL3H=kCM-gdR+ko2)z;YdjhU%MT<!Su6Bk43M)-Sg`~0_={o!eEeH7$r*2*xft<
z&|teasZJ@xE^Q}7Lha^k1$LNS#`73xxZSuN6wca>tb<5|-6{&-MA~J(jR8j4EupH$
zXuIoFhZ19#vkIN(?50=J{x8<<peJC?+qu#*G|q0u$B>D)tDv;N1v^~TxPk1pbKzlv
zT?fT>67ABdWF^V2jG_dW?7nw^$Yr~W(a^hMH=7<w$#(9;5J|D?4?*WuyPZ^9oN9NC
z0_xZ71}XJ*-R`BCFl$S*6Zk?V-Ojfb4rkbDDA|^2C;k~SS$6B){-2{OkE^n3!dhCH
zW|ozym8n^2S*}@Dn&n!4nHG27_kF)wT3t2;WETXKRY5^f5d=jM*%3q*L1af35d;@D
zMFr)1roZMl=gd4a=iGNWXJ*cO(U|Mh>j9GI<SqwHzLTXN11)fxo(#!Cr>{4_(q*S5
zS>TGCN+}Os?3CUF>?=;T|Dmtc=^_P@E1bT{0_HU*_ix}~rIV1}096jBU^<q3-D&cA
zn5cI0G^6!~)8}r`sB!veIvQ)8{OR3T=afO2tVX9ny5pLhexy31W~VijOTFo|U<Mjn
zoPK={^Q}%3PeZcJsgsH_+nrJ<Wp>M{g1!LN;gsWzY3_1zq1VwJrwzMlS=a4U`#)&h
zbDFgmo%fvr0%87v(@&m2>vwXYfc$`yVFt*c)6*XyIpp*<9hH9U)HWF~Pn^m_uYH0F
zxe6`RT^OxQ=(#dHykOpqalVBvZpK7fzIrg6T`(n{j1TvM^JYZ$!MYE_y$zDSjGk9v
zA%NjZ=NJPSf4&V1`xqOB(6^sqdl!-+j0tZ6I+XDpJzftooOS36XL$7hEQ0ZkV>f6t
zV{HanV;CQppmB)N^D{)_7)yTxcZ3l;3hbkdofF{pF~-UpaOOB8SqPHI&{47NDaPB+
z;6)PS6Z**0X~uiBr#!<bwm~nIvG;wTq%k=2pped(_6qvWGwQztxxlbJpbSYS<CXt5
z-;AwP@|eXq9t~%58PTc0&SPAe2M_ZZAJZD|GQ&s_^dd$HopLH>BvF>@D&w_}fl|%5
zLT|Ghj7juZuVD<*o~4$t--Rv&hCT$1jSSv4*ll9CQhckKQRzc3)0>RP#{tvAIJOw(
zTN#WxkT%A@6ozSMxY4TN7USb{(C=Ve*$MNv83pd(IvIObz~CK5_!V&7jPnLa_Anl<
zg5A4}LJBb5V{pAO><5g$UdJGM8UIqvMjxXr8_@lXCD>>>#t$(1v}he<$Y()uh{2#J
z>|;h(A3&cl4!A;pgfWRe!1#=@LkNS<8Gp^fD4dzvYtVCHeoi$+uFM6LHgRL#`UZXO
z%$bxa+{5J13)6#{m;-~J%wZa!7xM^#?Pa>JhMvQl$sGgMhxtz!9QI{Cp9_6I=2|Hn
z_Gi8r0208gSqv`%nLW!PvXA+2B|w9ili1J;W}?sr7aQ}(7PuC|G@gdtQ07z#NEp*X
z3C;t|XK$nLAoJvINJcWR(=`*tOuP>B(GI4R5*~+{KU2UpmZ_cs#W?1~dGIuzS-2LK
z5}1vl&_Bkk)dKAVGpi4MCz%Wi)ShB~N%iH)%(nG#JB2wA1C%q&b(BXt%e>hDy>raP
zKLRD4IffoL8O)S4^j&1W9Rr0-rlYbHGTF>Zs$t4uR#2!Um${1q5d}<c6tD}KtLb@u
znfc>YNER{2RKSa3=D=h$USY1(!I=`~90Sm<GJkjg?@O7JqhP6wx$1L>lru-x0IY&}
z{SSCi$<)&xxQaO~5MEqoZgzwKt(rM~0>};K9g3UQFpWwm)-t`_AzIHoM^*g|%+j&Y
zZ)6rT;6)R&pYk2e%oK{?-DG}6o3j??Ny<>RGN-JDGi}V(XJDe8SxFCyTg<d*G<Gn*
z@CE5&*3%024m0Hs2TXJ`$NYg|-(#u`uzR0rr`P@i=4X%4*vtHq)`5M@ukhv>-_NX7
zz?lK2-&}|cG7mh47Y~`1jc9ztY<&j`L(HhJKpr#yrn<r>%vY#-?kRIf4Q`m(OsUin
z<|ofVo-w~aLNC+j%ofU*jxrZg6^}E^F2E>USUa#%9`DLJKo2N4)_ux{xwC|{ci7G9
zr0SAAtbCd^57vU$f#%67D1nF<E1wUtmld-blHROegMi}0$|o;;S!XFl@5jn}5o7UZ
zeTy&VAeh5)FM)4?tdp;U>|<?c251oLj|RvDvzBB+V?T?z5F~`PE*>zUtld)}62@w#
zikAZ{**lnogDkiI3Ika}ita_Qf~deJl2vgKGZV!UQi?sAb%^fU7*;qP;y%RM_A>_I
zIL!Lc2GCg67~0Fmv0h9;=Mh%hF>ps&A}vhBvtIZJCK6cR(PQfvYyW2au*X?NEDSV}
z^*8NcPOyp_(0GznN@ojBvApPvWD+ZW0iaK_is;Rr%+f3ZN(yTmy+F>eG_=P`b+Ekm
z0_Gg6l-@4stRXwdc~%A;FTB8VqY9r4RtII=F0$5>qnWJMmw<hVrJ90)X0Z;@jhD@8
z%Y$SNtDc_cxh$7+z|3Q9+yE}0)jJL%1+3n4Kq+LE^g{hIOG<T3MJz`KMS+T0t)u9?
z!g75NiY2T_dJ$Y@h5ZiEQkF6Wq>Qz)0*&RY3LflMuwLf?^crie8x$&8v+z@nuVNMd
zf}ve!ZK91=HR~;^a=O9VxfY|ZVabQlSIe4D*F_y`%wqJ_vvxZ^0a^oVFGcqoSv)%|
zHL+f!bWIEE8xv$&S!v55(#FcBjZ8Z$jVfMlvA&Ifi4NBN3uwH}TKN>9ovb<v%XP8b
zUPa#>)=@V|cC+##(AdLDr;Gb8YnBD$yvLgG1bX*by%#B&_<)s68J1p_oZgCkEO$?c
z_OoiY!S4Z<f^wmQtnX7W`iHFd_rbMCtX;I&8Df3k1`i*z?A_p=und$uead=91+K%a
zVJ$3;up*hzd&Uxc3(V)N)L9^-tRO1sab_=FPZi=W>}mVpzAM{_esnkXpIe~e&VHH7
zba%5qr~mfY!!B&cC_LDqbPmRoy_XUWUTg+E#P+g-B~bTfe^v~2ANJ<+Q1E3R2!SO(
z_Jb~<__O;~qcMQJ^%o2`kp1v36!x)yyGNVJAokcFFs5Mk@F~dbXaD{MKttHCe-Hgo
z_WKk^3}dTKVrCAo^H*Xn4zfe|@GzY12!}`nd(&Q+h-80CS<@)?0A=i=*$1goG=}{v
zeNy2NyM{idb(mf88@O2ZY<gV9vBl#+97oufs4(d$`{Q1q#k03h1k7>v3JT99vS0ZM
zjVIVw>2p*`>|GNu?9=QIzJ$NY?3W&cq_fN8Ad<oU-v>as$hJ~uC6n!x4RVR?OnZkc
z_AvEjvu7^=W)Ayp3L59Km(p3%JO?|e9H0g4T6}wLd?EYF6}Whref}i$i`dDd=qqO5
zry%<kws<qRtL%&+NS3nm>2N_A+p7rX%h?m@ct{2Nmjrl!jeV6ev6bvZN@i5C1@0K=
zb+#*g&$pVLNZ$mx!5(slLJixYq0DzJ`(yfcOdb2en?S2)m-wQyfnBu?CK}m0ir{_|
zdm&YEH?tS^gS*Loi<S#5?0;eb+RC0qLFYF14yrR~XaDvs)Nirpo`R(g_QSLA;x;?o
z4O}O?{SfrJ*b{vqd568&u?6g1_U4BGy~lPr3eo%Q*J?o?u*V*SYrX7liZ=JL?>z_C
z&yJ>i*Z|va48}Cb&RmWk_91(u9F33Ilbs+k#5TSRpB}TvQQ7Jf_6e%ef68`R425BK
z>=ZPPuuo7)_%rqtKYCt0XG=XmM%g$2K&LaOU?U8=apwKElHwdw!o+S)JiW#DaC~1w
zp9g0dC96C+uc<H!FOJ7}3~eum{S5};&5?f!OFo=#N}~93(kTPw$GP$i^!z!W(v2R#
zIo=0_Ku*Csl+4)28Ga1KAWrvXhz4`cP}%E#&Q#j_hj40F!)_?&eF{W`ai*_;!2_J7
zv@bcxSr`q_aL(vr^hI#~p^Zo+=YJHWkKw#dHEoAD+4KTA%t^itup^x9J3x+dTE2&c
zc+NK|bpIXacqBk3ky9ar;t9@+cYvM5iK<59Y0eMyrGsS7x8WF5D#ybImq!|B4;2rc
z<y1X_!E{dhE3kB)b7C^oFL0jy3KJO|6>SqPa-`n?<q~J>Z1iPu7EnGoo6}5%s=1tn
z%}}3}$C)}Gp!pmv{k{d904jqi<OI;qRm8D|b}t({(=iUUeB;YF@6sBxoMZhT^eZ^c
zl=rLT<k9h%Doz3A8?STxDQjBI$%z4XgCnK@Zw*KO6B_F|VN|fvz*%dD7mb{+Dk0Lu
zNvVRpX3jy{tlZ>mpshy>hfSy4TRErR!dTikb_YGXyE#d(K%<8fQv`CCbCYre_c%qA
ze7Vm7CazV^cQ3=WKF-j4;QBf4shEU8PE8Qhhd6$;)_Tloq_^-B&dm2PB~Ljk>7!-C
z9M4qrjc`6a21lQ9z8wSe&pCcn1v<+4>RZZqJ98uGx^m%u@fI{(x%2-3w})FruOknx
z-zqeEayQTg;l-_{sMB8VeG%OE<~mV=(uceG0qpv6lPMnV$31-v-Uo3zJ^%^k&YBL%
z{apETfQ4{B!jgV`D0df~HVoswS~LL{=>hHsw1+sz-Ad`waPG=q029M)r?C7XZsHP<
z!`u~_up7%QqE~DjS5N}%BU~R^@E+y9+6WWz+)rd63EVMl7}`nhD~0g)6!$aA5+!jf
zC&A!pZuK`XpUj<Ngfl7J83*VX(HXA)Whka{1F3*HjaxAm2GhA?Ujp`d?$y^pE^y1J
z0y2a9?-IaV<c_D3x=ilfO=!Htox2AjS=_u>7|iB!ZUQWa`xB-8bGiQSp)ZeXeTc>)
z?vJ!IF6J($uXbJGIv<B?juI4cW4u?nYB|tKxe|H^m2q!9#qV3rjd}&372HjwK&$4?
zr+R@KTph)WYPb_<$ydvbd=cZV<4(H+(0cB~oA9uK`$ZYl8@V&-wr}E&qdZs}H-mO%
z?c5J(J#~wlK_6`FaB%lr0lm$w+zism)z!g^F79qV$Q|wlN{)APuTvKP0k@tSd%0tf
zs2tzN<<oZ-`nl^U^fthad<3@#xg}J7{g8X%7f3$hvgw@f5cjzc3_j(`Cx9E~{(AyG
zjc}VOpZkpK@K^%0=UnAH$c%DZ3xVd$dubUwb>Y252~JnuHTq798_%5!Y<He+7szhj
z3vm$H%L|JI=gl)ULC=Tx4{auWc}w=A&yQDp4+i~tJLoYNz`NiNe*<~%G+{3G@y1bE
zaVSseIE7({@ha#!b%6KuD9{e_W`{!~oc9q`V@L2_lLI@FH%yEFDBj8~FcHnue2-DY
z@ix<?cZ9crF1@3?59!j2=NahhK?%I`El@wk+b9P)&P%ERN+NImf1l~&1<^TzWL|=b
zs_#;Ge}%x|GrYq+Xieo!tp|1*ulEToo#i=Gkm4NA!2?V>Z<ZIZ&-4CDfx(MB+exTr
z@?v|yUE<|i(U--0*a3xX-bYbT&*8o839ww=%XH!{kH?t}lFvJO3BxVm1%FEarcuaK
z&`FrfyhMsGU**;508`2fy8)OoURg0FsGL_Mgry4JCnd0SjW>%@i<P|Z_%Kn$+jJhF
zwY-D$rmN$X?tw@>Z@v*I4ZIEsBpZ1jZv<Eq@09`cHS@X_LhmLo2U&Q0&7ZfJ;=~=i
zlXkS;=Jgz=3z7E{os#b2?M(*g9o{xtZglhB&4Ydqua`<`dwH8r<EQN7ou_NPpZ5!$
z>=@uZr8?O`-dQH>KID11!iz_|7ihUK#G85*C{KBFDbO>_TmA)zV}utriq>bm$rQ7D
z&h!2elQ7CVPCG>pe(!FW@Z`50gT5C(h_V5D`C2-a?alwJ4*EX)VI@R-`P)sf>&Jhu
z9+Lk2-b26);0Mr04FdU-sm5y`e>Rmo2Jt7KfosA1IaScx@8CbB_g^Ugk1&9S@o#Mh
z%mIEjMRpJJxwQ8W=O@x7AIa~bLgFaCcoq7h`CI5SIEVPG^ME<b=Scw?%iltg**Jay
zZE}wA-<trEz&}0>(8u`S(RFd0pF%JAM1GzIm?!v-vVYKelK%=V(oXSL(po%;FV{oy
zG+#Okqe$Uzrp4hIex@BHm4ERgD5ml6(x(3`|NR9Z=lC1$VG!r}uZtmaf&VH69y9pT
zzW{xa|A7L~nfx^rLAb;}^F5|HiywUjK4tSKIw*ga!$0SZ)?EI>KQZ}v{0X$s&gU0W
z0agM3*V`b4`~&pZy3BW>vvNiJaEhW9^XH^M{R;mo1>j5gwkC*N<@Y5+q?B*|65f~b
zEAhRC@#Xy2v9TXt!GDK-rYe3fC8DnLol+f8tmgkfQKTFEMN~Rm!}o4SXDxr?B#fe-
zFG@#W17FyIfj07IJqBswC(nRhGe7@hkemDn6+m10a@sky@ueR_q@7>g46cL!f<M4+
z^GBFy?Bu@|4QIOeL9Kwk!=Ic;U(@O4zu}Kj^zaYU#|rQ9lg6R*KL3>)7|a9y%k<dl
z<^N32jXwV9pAZ?~r_q{tkT0DI@{oTl7$T4O+&5uxh(BjH)F1OVzllj0=0BMMy%GMA
z?a+J1kD|=gbN(N6fOV9g=tf^4a29k>1j0q&M<u+j0=+Xd+yoAa6T1r{=#95qP#=cA
zJ%V5I(dQvpL8aZE0s&3FmtX=#4)+Sw6jSvU9HKX^k06Z-ID7?yPU!gw=3N7rzu@jq
zAOV7<RBjh22w4o`*eBQ|0Zfo!z6}ls3(Dy0LHh;X8(<<tuqXzgp@PHH(HJI}CBg^~
z2=?6v_Cdkr3n1ZwUnuSqA&4>oB~mbMB}kMY)*E`!g2?|Ctb*^BVoDAP!hB%iupo-E
zaj}9JdMm{_1Xna*j|h&hho?scT_Zq?7s%;A=yAd5n=p|m*hZVP6N1ZhknN;k5)Lkn
zKPB*^Ep3uuXd)y}3#P8eV3GwqO8=z@UVj@XX9RbjKrdCm+62iofw&ueX9Z!D|2`+E
zr3iYuz%h&R=jR2RHJG*w0=E{RWeDsmpm<S`*9MqOLB#LqyCkqvj513whIU8Uf_3=u
z#^(r}zJT|+f_|#b$P@fK49R@K3JNk52*OT4vQXecMIM(0V<{P5B+yKQ7sY}(Bj~##
zc*F5COq2+AQH9P`LFgxtDHY6^3-c9%&%Xe<Ch-3p?pF#{Pk>03AnY}e>jJ}iNLCA?
zGC^(#+71DwMzFmRmTCouD0@*SSU3tV>IKuM;74l^?D0Zhqo9i_D4GP@=#k$n__4tO
zhi?j!sphanu#4Wit%9$=hkl!2DSb7pUEoB&&n>|mx&k`{d>a~X3)-kGs#DN)7Jc1<
zm^5%bf`6zq=C0t{9EjW#4E+hr`}jrRTCadZ%Z)z4sV8uzU%=l5Za@(Bm?};N1-%`>
zeke#@2ACniv%AoLEZ|cj`HA4wPE5j6!RL1%GAzhY!|xG+<UNQy7yLu{s8PYRbpUl1
z26=<H3I{00;U>)b9-O;y&r0a+7Jd{2$vwgh%3^p5S7d>B3Cqt;7&C7CUg5-0(;B2}
zq7tFuFYKo88UzTx{{$uig<X@-xKFr^)&fDoOuC?gg#s#b4-vjI4_v4)d@TCHgmb92
zB|_LpJH<%h)bG(4CHy-U&O{5R(Z(P~c$>~k92VZ9Ep4nYw-L~B!s0@J9TAo~nlav^
z!tba8F<y9sYC98zY4kceE;Q0xI8hjK4lpN#nGd0VQn>jMe!Ek`%y8(R7JfYe>dC^t
zA44xicoIV!e@1Aby6aS-PKZfJ6Ml6VdS`{#RzvT+@Ubs2F9_Wz6PqFYzKOOl7ll(k
zf?}pHf$|So!sPEUm~7z>?}FqAkJ2xiD|G!32J?ioUj%l(aKlCP6$+E+-n=YaM)z%z
zF!v0&V&O(g)?N`7y#s?K!ea`kmkJNkeNZNBpnCjrVHQ1gt_g=0Q@W;7_~ui1S|wz)
zVA$7%aTKJe7P6@pr$+e28IW3G7Nv#jg!4K;>V*qv$JZeAr-VhL@DkOcHVZ?`fPGUK
zuSQ>sFpl1-twJYy_O=N-*Fv&gxR`>H9l~VFN!%9hn?u{>PNABDZau=Q-$L=O@Z~-z
z-V@f)0`k6abUZX32sctNr%xDk0cicg(5c`CghdRHL1FnW`1DZ7G=qC245GE#kZ>Ud
z9-j!aXJepGh3gl<wPE4Avp`0K#T37MCj6DoSvW?8$%|poS(I7}7hObamct8I(Y)#4
z+(ZxjFnV{9lt#E)lt4*hPtjXZFySRy9|V!TqN%j9@D{zh2*gKJLz`e<(doMo@e?_(
z2Jsh7orFOIh**@94-}PEz_op%czP5DIYcKKfE_F<&4=iIQ4B4OLquN`!M9M+R;s-X
z6Y*ML_kd{42WUJf8efU=hKnZ7guw{Wr^VnRMJ;-aDM}PQ4JM*RO_W=R5iO#ci$kL3
zKhbws<Vr8vSW!+fNStU(8K94d95J-!Ix3o)3(<Jd-*3Z2g2*a>#xc>jkKpNXk>BTV
zKT$M5RaqxQT)N>;iuQVfJ0+Szi-#nUybyyqEvmc?y<}128YrZQk|}+7Ml|+oNT!Nv
zDKK?Tl)n!O>7tdtK=QokTL+ctUKA~+3`wRafquhFqBrk=%Mslzz+B{t`hr37L?N__
zE))&XGW4?OdMiMSM742HC=n%(gQcsYDc`|FspxH5;#P>JF9ml^#1likQnV@wGgB=J
zISP~;qM7tosS!<FL$ycsqIfsRG>B^70%;VnmO$pFC^ZTCEuu~eoV1GGprmb^$c=J1
z?IPDPFnCL(rDa`*X!0u%xh<MK2Se)=EhV?RL~gY7x+5x2gGi6)&{6n%S2TGcxO<{+
zD6V#2B;(VQ_<@K`Z;3vUQ3=I<(Q7YYgaaZOUHOBeO8Wf8LlM6R&O8#iNzgYW%H9aH
z$D)7Mq49~x^8`emiY}U9a99*t3J*s_0=m|piAE@0^IY_586-zVPCE2Ci@&qNyo=be
zlxlBX#WU(4vs*lS9}MmhFQVPAhxqO-5Kr;Dlr{Ad?-qdDE1qVAq__B;Gm!KVm(oFO
zKXD8#%lyT|wAcy|kKw>lpm@wn=-VegNq2FO_%5YXg2j(YK=zA$>3$Cr545AtaX_r2
zHOxVA!wqOeiesKZCQAJF8Vn{{?2`ZzBWCYM-y!jOx=LcjRl_hJCw8K6)e&*i-{?Ck
zZulB~@nSh`k`lz(5#WxA*<WJ1j*C}Q)HqQ*hIZ>G#NXY5LYkOQPwBG`@uPpyc}^U|
zL2J7B^&X7(y!fl10CPdiqypp&amnkjbWzNp%|oX6z472KiC?CzOP2T*4oJ56a41l6
z#4L*2<cg1t!tFe<D?M%V#U-x+vp^j01@ndCQZ_^`i=%0!S|oOyqGH2h@zM@>b46TE
z*~=2~xce}1RXp4WjZ!gtGaAdprAOgmxp+I(9#x2cqz`0X6ECEjvQqqTDp0D$&u7BY
z4RH}YplZY=y=bf#@1t-?gV@y*3XS5~IcRJW%P2+HEao_<+UTbEhq18KCT^z!takCa
zw=nEm;tzU2I>eGeh~5?l9fW?TIFaU}OPoUQp*!O00+4R;bJ}$Dh&QYOcUSxdl_1>{
zzpxyWa9{ivr6wPU8O=cH6@T#yB>TkiB_RFc-h-5`84&;WH`qaOXEJ0Sit{Sr%p-B<
z3G@w#n<%&VSUjEP>xp<1WtX3dcijgW76((=z=$}5a)ZyrA5qfixp?)b7~!b6R0_^n
z(oZ$nE|N7BaNAWfL4`gy$=mdJb(bjW=>FR+`H^n5J(8tYVb?=4{bzXLDQTpe%S)nJ
z0lRx8jwYD!maO$dqmLx#8XA2i<7h?WCt=Klqk)no6fWK;iC04;ND@Z}Xo4jxXkWiy
zQb9TL5J{K<(4mq-%4&y6Hn~%}^nm0srNs_P7@iOfmpH=VaD>GEE<__G*T05hlq8v!
zn$eQ$ls=4+IH;oNki<$a>cf&b0WcpcnOX?RI7whQP>x8NKY)6?MCSpY5+t?s%s(cX
zTndrnlCS@PUZP~29&_k8De<B__$kRyE;N!P0kmCDk<6#+k~0z^J<C!h*XY1)n&j8*
z;Lb|g6fk&BawQN`nl8Cb@2K+<Zv{XvNcQAIFGF&Z4~2`8kGPP`l)Optu}hNFNs!Ev
zgi>@pTk>Ho%;z{HC!)}rEBSg16!Ro{x;gVDD=E!eAPKw#X9^{Qt{|5s4tnhuNn+`%
zkj0X%RQz*AGMln;B@$*FoVh9~NrgzMWEvgrDU+<<2fO7GHSMY@BsH`@xF*@z0)<M+
zVp?EVNgTpzh+da;)8VUX$=pD2wGutWSn4Ei{}<+#Y@ujQgJfqG8XG0Q&_&uLxkF*L
zX33xQwYHlQ@q9G4NM57$NvkA^&WyE5e%*rUx+T$%!^k=$>Ss{6Eg3k1zWb76Ss)K2
zRSwEa^-BI#LBCJ3_!78&iJFd(4M_ez3YkI46N-;Llqhn6_DG`r4rEBOlOB^#Bs;a}
zdn!@?0lUKzPdaTfA~FAg#%GdmC~WjxvU(z*M<om@?R1f<X|LldeMZkIH|etH^g)9?
z(y?@a$3t2?AFZC!q9$-&(n*uS?Ui=Y$qsMny#~1EBQ?zd=PNCzi^Wg+8Eu07r3)z_
z9w^PGy54=#orfS2Bo)y2zk{V^E|};2(vc(>3XxjQ0VPy=Yd$O-kn-bb{drKjgRbCk
zX?imhBcx^}{En1PWkDuds-vK2jC2NlN9C~e{{J8nE8P%`xr~#pD@R|vv|=UH6Qu4p
z(RWOG?_;=@B0U@pOJ}6hf}xix^_&bZ(xm0|raUX<jD_3hq@Urr>KK1P`U~X>GNh9!
z26j=(oCw8C>C$?bza%X%!kH}T77?(srSf$!m?Q0>pmna)nGU4nNxT0Cg?wpP1MC(^
z|E1cA%TlL_P$-hV_bMcdrI)UPyCR+N8N4WwM#Vs~OnRO22aa-SZ!0=0q#-B4UXv!!
zR=!diPVe0+=^I>d*QE~HI95v=RzvZI^Z+e^YNShC;cu-piXs<vQm;6WdTA}?BpalE
z(^8~S`g<chY?5XaL$6sn<x7y8(m{%Aw@5o9(bwvb2FwN9CT)$!c-y6~{RQrpw4oLH
z9nwTf2;Y`gJ%<;a(z$N}yGt5A3nF)<Z0hTlu6qrx^+>;`$HrahSC_%vlfFj>qVG$m
zw4?EX^o3-QUg-xE)$fy*W&ovMx`>j!15!s)7c31*%c<<(p|q<9GLNKNbI~~@t)LRM
z$5I~(6g`n{?t{ov=`tSBhNWw$Ze~R4@;cmpCbdy<<a4PXZ4*YNnU~?Av+VnH^ts9m
z6t~$e%Up-PJ+d5HSa`_FDD3Jf``AHIJ}=puR4u<(_Ai|p@s<T$gNBdHl>(=}vbA*O
z`^lCD0nJ~=pl{Ly$ihwN3zRMXZ=)((Cjl2EdqN?{aM?-vnIdHKsH!+p*8LOuqGYG2
z95Pxa*oVd#*}=7#ghMhHE8TyGQ9%pyv9dF@;NoPdw8K3jdxKUxM`d|*`^U@jC@GjA
z+eWoO$7G>fp>SOGHSO3EWg94fctRGHguauqbXwD%k}a49E=hJe1Cpm@f>D@HmVFzK
z8BLMR_eS3tnRq!x!c%37==GZ>E6)cxEBjv$^v}uOpj|_{Y|p3Q&dciV0_K7&{Zsgq
zA*-h1p^LKHw4BV8wa^p%lB{YN*jci}N=RnQR(_Ah9GS%llb0)di}EFTvay}O%$MnT
z5Gjy-xql4qze3py6g(@E$wz=)EbF4n>xxYA3G9~05?+AfRoTw3p;0Q^y#}KwlbPN|
zW4Ua)4viJE6OAx&O*Uy0NTsZbl6qCLItpW6mw8b<qDEFoao$=PlL8TSvhi=gLcNTq
zM4zKUb|e(EQFg5r4mZi>eg-d^Ws@}!y(xQ%%0OFWK9qZEl`W&Ra+~ZO3W&GMp8G)W
zmhAQ@xDJ^&MO<#n0%*_EDck4@lrGuUe;{&4W_%NFcgyN&fzTs+Z8`ex%4#TfcF!S;
zpeXEp*}SFDe<1saqQAYe30iP{vWF6I{jx(8l^l?{(JeD5JEcJ1L)i^F0rN-}x)Nka
zc3~YPAIsL#S(zuYW2LbBRJQ1UAj7iXs7P`|#(xGcp2?~@f%05trXt@_nd9&4=yaAF
zXujO!3@RCMmn-Rz+itnSjA47q8C1*TC0`N^OMB((Ux1>o{8uLsKlxKiVEfA#u7gN`
z9I-3h74of9;LJX`8*Sr)<gaW17cBpt>Yw+^PttlUM81rcgQ4=Jjs;-D<Y!kx^niSP
zKgdD3nQ{f;a$kDbN67C{iFKqrh?ewG@);vA7%iVeLBbgMAYC4Z<Z+b3JuI(!3=d=F
zCVKJ3$=k+&9Ffm@33^B6l3WZaUcR3KCkgU(JHRE%6ThZN_z8Idg|bh|7qr2d)AHA*
z04-VGN98Oj^7$0(J0t%z8(gaV7s|$`$#W*7@vPkMEjW5k{{6dXOqaLrL*se5MFg-5
za^(_0XULxy0rR5#h0nod%C*}-F3I=PDWWX7)=D1~$(C1A`Y}iTrV4g*<?oaLCQlwm
z@8o<rCkE~p$fX77E0nX-(0EzyF%ixb$(ujGPgyK~^#`C`kw2xUbctN-0&-O@rnxAU
zZ=&Z^ncO=8cCX1}XdhN7PvfDnN?un^nW*dX<1a$LTK>f}bl#A^sfUR=`NmL;qFz2>
z3K|>aX=lORkvDq7i*9+z|6smH?m?;YyK))5&hE)yPQ@hLm#?Q4*aP`YDpu^3kI=5W
zPrhy&EcDB($n61nDHZ4p$`{dN&hb!QO9#0h$(s&CbV#0j9qvDtJCol}<jXivd@2v4
z%8_AtOBTj7BEL(8MbG3PB|y(vG5QZ+TokNC*mYIRH~>92MNSAB-4zGCKz1v*PoS_z
z5vPKPhvFU;EqN-gP?XKfq4@DruzM9@MexmA@fL-xd=%?%L)2H{La87>MKC=d{S`}I
zf=Ga33muaTR4l#=NB1d`UI%uNqJ{^QU`6`Rkle4hQUNYRQBF5bsG^R}cZ4ZsQ^Mka
zB84KI2Nh-tUWF?hzw!VRp?KdPY@}ji4!9`AXFgDjR=Ck~GDgwQ1n42fJX+)(R@Bo4
z6{~362rf>My$!Q=MDf|Tn2V!|&Gc4_SNPHgz!DT^H^I^|#kwxoJ+5eZ0nmwx$QPh~
zLXkl0^plDijvry-l%km)A4!VRiy)^JOZzZ2$%>aL_MM_QISJ&9qB8}3sfzH`a5PQv
zkhYj-75!^~c24o>HK3#`&M$_g^NQkJU|&#d3<t?jMD2#%i;5R$$(N~USq1e=ilu%~
z$Wpk)QY1WEF)jqHIf^EF2IeYeQMxBjF|8RSU-2siWeOBugkpq+ihBBE%*%>HfoLpJ
z%%@7;V#V|ZU|&&Op`wctg_z1BuPWBjbeAfsDZE{wFzp9-O_4*%n@UAq9l)v-OJ1OI
zz3Ymt^eC=YxPO7c+)yl}qQM%)avzMhRw3UD#X7}zR2){XNC^gZgW}uMXlzux^DWSt
z6t6j9o|_d@X>r)9SU7~fHpQL)UJ?qIDFC~r@T5#(hvE&|rr%aP{R-S2Md>>ff9Y0;
zS3$o=(M$Wk`-<(fw|t<uNRggiMb_`=8&I%{;LM=n_vzpsDoRXn=8+<y1O5&vRG*>m
zu_FB~a8DHPIs^NuBB%?l4J*Do4U`c@7S)?RQ=E7Mu02=mJPL(TMLtztIh>VG>5Bv|
z%FDE|a8<rR0R=au%V{*aE4$a@hw)Ip(gJKx<-9Z~dMUp-i!u2qXH#^-SLs6ePCupO
zXQ=xt<EgSBK)EUr3W3UPH(_v}G9w$7f|MHicvP@*?K^O0zj7lN>LCv0q*9m&RlZIs
zw=iYW9CRK~M%MxKpz@DqaN)|)kKt2<^0Pr;M=F!)vm`OfC?}XWq>QFm)?uZq0@z2C
z`E=zURsJ;|BwiWvD*6(X5r4w9V@k=(;EpR7T?dz_?0g9dCzKBFt*~@b`MxX0bV?cD
zh0Y}9dv<WAl_OO3kgP2G4wh1srU*2iQI4T!QL6Iuw_zepIgM7>XO+4Hcz9m9`3m|j
zC|}=*@n$F=)BY`2S-Tb^%TuOOlptT(bOc@$D7U_h#zJM6gBA*xmHm}aEK(kn!eFs7
z=}RbHQJ!1`XG)YpN?Ki27T!l+sq(T1NSX3IF-W;GkltSv%KW7;e@*$_8DLi`!w!K|
zDRorVctiOOJ#T81^J!C8s|?FPW1Vt5Wmf8yHx^L*r9nBR5~NYt^D3NbQtBu++pN4E
z0Q0TNH>yC|lpls+655rKq;N|aP3iCs<zf0MZ!7<yT7*tzFXcqKln>&;-BEVF2+6xj
zXFB_JPx<>cjPt(o7Nsa2D3?(PyH_dwfbPFO<t7$d`<0Is@NGa@UkZbRN?*#Q4k^dc
zqUo`+ZVAW}Wdc3Ro+>vC18rEDMtAy%()B#lpDC|rfIL^8-U+*-%K4N&bX6Uq8fQ0^
zjGp=Ks@Zoi2_CAq)adh61&^cspO>nJHZ49XpCNeat7@fN%}-U#0T-xR;R0@-YCHwT
zf>f(B;8Tcd*-PjPRqdwFsf4LspwM5q%8zzA5vp2xVMeMrdtfk5)gpkx5tTU?C`VNm
zD!hzWy+;|H1l7XR@Yiun_4qE(j;lV?!Kp+QV**4^sMHtHcv7{1HoB)&E);}HQZ1nG
zE}d2tErm$3>YWITK1J2g4fAJI?0lF{RW;^=OH=(oQRB0!6LxUtRQ+GTV7lt-i!gs)
zb%|me7gV26&2NT7by^0{iz?asU^7*}e+Z3Bsuf;vKT9PflC9eRDKv6aIZ<#pPc=6d
zT)wLAAruN!c@+CDR4tzbpDwGupr>V#%8L@h#j4GNP`{!InTuI3QEhR<Ag-$Zq&Q-!
zs%;O{%Tx}@`|zz?<@q66D^xpOfPGE%!|%|qR53Nss8W4QWk1(de>-5lM&(t7##+?|
z3X|2T?z+O?M%7I^me!<to1%2hDi%q$s+?(M-KO%Pdd7CujH}>osV*%8*P*)T50u*~
zwu1ulcT}$}0qIuVrG0vjicdA{_f@MX<o`hB%YtIB%2$EDJ{6yemikqOnb03l9g9Tc
zBULB`>xNXT-v@cD(xiY4tLD-wc0~2c97sM>RX>Ak&gz*oBp3BZf1uA*{c!<#x?8<-
zJX-gt)!zZzL(QdhxTpGMdTM&91xFyVSG|&=ZGq~gRPVD--J^j|LF%(tAQG&8{}H_3
zuU<!&b%;8f*1e(XJ9FWEn0f|%@cMvyUmqk7suz($xcY-PFnJN`XK@t&j8sqef;Um>
z+h0L3TD|i<bjGMxI>DJkYELha!|K6Hz>Za052G(mT|!&pBkBWGGj&w`4t)zMUR`_x
zeF^ILzX5hk?K=m3$JI-H;YFf)1qDY=sOw&UqbJp|FTv0$wE?9Jj`2zA7pDUIwE7f9
z>66v{RPddm{z3zdGwP?o;8NAGbakew<6eg|XVvM|;LfRIE&(lFJvR_&=hg2WffpCl
z>my)3L*1H=#*6B?Wl+ylpSc9+OX_QrA(EwDH5Od9daw{EjvTe&H?-!ePtefv)Ztce
z`Rdyma0TjjFG8kJy<-o!%j%2}7%WmBr(Jik+AkN4SJd`(Xe?0=QV#a2`nzDbU8-)n
z3z0Ilj3VLX>K~}|szUvQ!jV<#uPNPfU0rk<(A5rgeFk7^)h+&Lty3S`2vV>9q#b@Y
zsYfXt-mI4X1I3%_N--MS)XylJ*se~~!tO2g@~be|sSct|aF;rh4KMDfcdY_uxBA;a
zi1es^=(&7Xy_jz8d+N=!zrL>?M^Uy1YRAhnF<-sv6-NNmr!Ja?pQ2w~M<q6c>eJmY
z|4{uUrR*N5^L~ZhA@z~f(0{C6O<U?G>NF}OeyXmdDvx1x?z`w4QR{z2<1@91Du|z}
zeFI==RDEXw#_OzUPeq@L=A8#<bk)4+p!b5C=A&#7ca3)iyx6Vz(+{0{H1`$(%|m0P
zZIP#@=^pgGH2z#TvsdF_0NY#hXD%9jG#_$d-d7V(CoKFlq4d`#{+hRApckNN`yV6&
zHG2-Bai3<}B5*+(?mS2aYaY*}`)|MImnN_wni7hNhH4m;2n*8)j=`A&nys%u<e=sy
z`unPIP0=}+kI*cPh22O^e>ohD(s1b1R<y>o0Fp5p%N*D}q;Ypg-(k&F`i4fVrf&vF
zoaWATKp)Zk^8=udY9^=C{THt(Bi|A<I(kqY)6Ax@;&IIY?XD6vCVF6;&~(Z`PHN^A
z0sEAuiXIe6n(|>db6T^e3+9tG=~N7tqA_d+*cr`^u`rRU85jeRG|lfJaOSLLIRzrl
zX+ELVRl4ToJgS5`uQ~G*urFx-X+vv<W>Y-OU(|$u04`Ibpv>weP3uy)pQVw}qBdJo
zI|}R^%_(1i=4za=j2)k+5mS9rzUBmlUkfy!jRjYz>7+B1mo)<vST53>p<<0<O$Ox_
zu4pdMKG{*CNjreST-7whL9tXbw+EtSn(4v7F4tsF$IvP@%MYTlO4CR2)9V@@1$wJB
z!Clb5p*j2rjWwDWsuHf%sCEInPNSt*W4-1jiupBY7Wlw!qedKq(Kl&!{0^>JBb^9^
zn+^>t6)v`D)^3AhtH%5_?6zqZz77-ZnmP{jZ)paD(AS~ypx5thjnW;8othyLxGqiE
zUr@NCIYf);Zq51)Fwvv&-3h(BnlZ7kbWbxxRRH%j<{u&QKx3sabFXG2<pKIM4*6EJ
z_G@yfly^Y$H@$ENH4b{*J=EmUj{K2EO3}I@jd~*b9&6%hNAX0He-rvoHG|tBIjpIs
zcg2WiAswfCrjgU<U7u?hRFgBRVH32o_9hFBE?Uh7jLcnIPbrn%S~rIPt$Vb;cYt_k
z`#wUer*?!4dTA?JP~59sz7P(3YrQEP;-eKDK%=jAE&UXJ+80*<&0o9Z78(PzpHXNx
zP`hI$8uw`fC~Xp?{lXXO!P+|(O!IziLNSIEqTNF2@KCLTMcb+{?H}_nrUTlR6)<s7
zyJHw!xb_yk_9L`Qsk$pt8@~yPQQA4Q^@-NHCcs3DcG<Tucu0G1A^bh8eM;)F+9%84
zTAa472HX+tm6_-}s=a;>KViI9T?>>1Z5~yc9n&UMQvBt()^8QONz|^|j?NR>NV?cg
zYFE>v^psXkd!8ii&b4snwAPn)`)9PJw2({H?xYxWnzr>OxU<?5<n}r3FK+NKU3>UA
zP|j<oy$Z|=+OSFBGPEz!7Z5ILoqvKtruH~OS&s3Sw7Ild%F)hS2AN###X*of?MD>N
zDb)70!Ng_l%oK<eX;<8Veu;MTW9VPiuKFAvmTF(2ZB>PKsv3RQv_n+(Q>iu10IAo?
z<Y;Wr-lwN~qxRuxfHi5OZ$P10`!WSS95=PIexMsb``Z8DX{&a|YH)4ZS+pu_*Sgal
z{Fe4U<(xaTHz@jhTf1HX(y1M~2$3#r&H^}kN1H-n#cu7g9Q5^QJ*jx;t~Q41g70as
ziZG=6+DDYMeW2aj3-i6&1#|`WIkYcPbyvUEL8Y++TEi^B3~E=GK=h$@Q5zZ`X>Z8@
zGo+nQOWa}Y9J&xkv}<!9@=W_0AO1eqDybx4RNH+93eLJusV2ZhcPk5huDZ{H;nN<S
z6TOZ+beW$(&r>({ziV9QSaJ=bdv%lOl#I9T-?1?7qkBj@K3`qek7)GQr7Q;t(9M5<
z#y}l28^7;9-RWb13DVUvpdPGCO-J8;-Ngg26rwww50Ow^@`vaP(`{S>a!|LP9)97v
z8OPyagsy~k3z53F9Qkl6N_VdjGZdqnN9QgM=~5_>eOPz&Ex^R-p2uToM|Aa+w>+x*
zg<ft6IvH&PkLmv1jhQ*FOIZSvsB`lJ$_d@ME^tY@!Ff<Wt-D51*ks)ddQ7J1Iw?(i
zM#q;zBvp5L8RZJnbe~Zc@~lp98=~iQ2@k+s&@F4m2s3meEfBq^tDgeNOx>sd#cy=%
z<7mv%eMP(OY~7*HF^C-92yI()b?)uZ%hQ=Rpf6w7(hi>rben#MLZPmAD=b{r<u5~D
zk#6lR`d`~(-B_wZy`sBCqbSjx{{m=bx(g%lqFmQ=9Hc^5L4{4%bOJT>D|O>2I8vqi
zi=uqjbuXr)v0Ar71@#-c-BcS|qkBec#9AF=BP8o|Vdv1-po^sQIE^}6COmA?W!dTe
zYu44i3YeR^cTYg3MYq2NT&wP9He}j#ih8);t~=%q4{zzTTv+PR_1{I~ZQX-&5b4x;
z9D!b!ZpK`YJG%Yb(b%mkqwR8!u6iCM@9MfD(RWYR{3^Knx;=jI>49!X6o{i=x2zg;
zK-VsW#-Q%EK$suWy*CErvCeTFqj;h_GaKZoZWUFn59>ap>uN-|TL`^TUDQrsJL}J_
zfQXBJ!;2W9n?8Wz@$UNjF_^sF`n%-J9{nWRHGAm)+y>55e}^{6UJm_Rw*a$Of6@vK
zZ+!s0EPV9KX?5tU_j?JT0s2utkU)JUeT`+G{+r)Gg7gUw;YG0iaV)s~`XU2RLiEci
zdl{-<-3?1&`XX93AJA{5XUReR33^J0>r-7I5~26Ifw_p(JHGdZ!6^MH2K1x#ydlhU
zjJ|sUG!E&vbinRmy&I((V)e|gK;reyRI!qv_i2URF?}2*QIG4-Q0y#G-<b#X6Z&Wh
zS)A10!un?XDgBlO&`Z)+hk%^cUrmHavR+MJj7ZTpI9h;qMz8dO!BqW^RFjaVzeK^A
zv--`Hkv*p$rQL73{`{-ZKd+zB4228&U#V&+L!VB|tBd-x6tB(HJJHJGl75JynOXX_
z*Fm!N(^FtDN8iK7=yUbHl*Y@`Pnd$neEoEV1BwOu6?uRu)U&8$<+6SsEgOpT4GUqg
zSRYF#9<JzXu7i~5t67k|s=sv;lBN20DVkHJf1M8Omg|3@R9}TYoF1&#^lRx@K&5^;
zrBtf)$LP6yU4J_dDAoF3-+?nX^os?w{;bhAWP+{LuceJeoxb`jaP@jNdD@`=gYK0^
z{cH4~Y0^6=JlCxMi>hXC>L=0WyG6gBqI|9T_Iq%<O@D!sWbOJ7=qYep{|W7RI`xvb
z(ATB+`2mf0^iy~c>DG(hr$5x`!RP^cS078&hWGRa%4XcxAF0AXALxTAIN7Tg8!@In
z{UReo`t>tLpfI49%t7Oz{%1;b4(VsT4avv)xwp~xL|;!Ksi*o*+8Yk*&9pTg(N|?b
z{h5B{J~;DSKaVnnj#0gYl9|p1@A;5%F*s3h#nmt_2{LYm_TAvz4YSWf(Zlfad^CC*
zGNYj2WjI6Q-D|k*4-?*o^E`<77}op&FMJKx=^f=~xbYo0e?u*OOfbNZ!G%wOhD$l<
z+h@?xl^f(Rta}$Q!G>$qklAk-p$K4zA(p;o9cpNx6lIuUMg{r~7~Z6(z(GSX)suu9
za_D;*5rzg@BSsqfXw4O6uucKkA;W@`=sRrK^d<CS4XX$&&M^N9M2;9_cQ9Q?4Ic%<
zi+F>>N~`Y#LnqyT#|*;hkU4HBr)_VdfzL<d3By|2o}4s%#)IT3!{QYf?`cEXc5umt
zjkLE+F>JBI(KCkWDqyD?#sxtk%@FB~zO#m!Dv)!AJr?+sZn*s%7S0>I^5D}2gUPWK
zY^EXn9z4Bd7%D?+mf_ny;BpP|e2_fDSc+xk8}`UC&;mnt2TT+izWx~8Wy7xj)<uT6
z5Qr2Tu2D$qilMatmP!mPN@QI%Y@t|3siA5*z{(8&(luUgSVz}Ig<(rPz5lKmnmyrg
zrQzGHFkfXDSOx6s1|`*uR2xh)(Rag;M8~Xa45_rztu<_U7kzbxJs)C%>J8t{gNX*i
zD?ec@jfU2@fZb#`LkqZOL;O1Ud()ua0lO`R$5hAFY6zgvP@5t3EBZs7cEfM2=)7h4
z-VLO~Q295^cN!`vtI%bbK+n)ShQsuB={Drj+qB29h>n2XHMI4h@t$E-2^#Mk%x}S&
z2Zo0fyY4kCrgT7`VH^#+-;h9cTmyy=Ss;UkABa3O%-4;<{rAW)<b=Tt8B|FCeQaPo
z0r$kPoc5hh4L7a>X4uf(3(yh6PiiziGkg<*d3tULEC=?ep_&CposH=MXml}tPI+)w
zV+Z{rZpIBa0OoFdK&$@U#+W`#$sXg$Yv}VZKHUQ1@HDoi0@TZBiv+vZSnvj9yp1AS
zPWl-A>3pWIu`>X~&lqwZBL2pMbU_6eN523GG*;E1Z=bPi8_Wk86_kJrHbx%>=6>TY
z3aW${3wNP0)aXcpLYT3<3eX3P?!ovC4mylGC~O>V^oYb@B8*qtp%`iGqYz${aW|#6
zqK(zNAsS<h#`9|YA>({k{7i?9GlGB}YfNWAB+j_n26DvsFP*eFYJ9C7lJQ38Xt<VO
zocS{_j~R0)<9^)epr0_&xcfR9PZ%8u^r}2*+_Vayr;I!GAW6nI9s%aGam^m|B^yNt
zF^MV0<CJwhV^lu|cB*mGEsXb^aX!7w(~VCb1N*$O-VJ>hjDJvQDZ^OP35AQspC~w)
zX_V09UotNG3XNIDQ?#wgHePg4U?9gB{x7`AH4ZNWmuGy7mYVs-zi2gEU|bRh(L&>=
z5zxPETuot|BIB!+)hjkmqg25a<1-3blo)?r1fQ-NeZoLWjcc=Ex6GJIvD|W_jxzNX
z#_2QBcg^TdzgDGjB#+*IRmRKi=)7*cO)rvaV;mJf+%QV1x~s<c`xO|hHC{T2zB=P!
zx^e4`#u!XugYm`3Xlyjb27_xd{zhIj8{cXGxoMm#hKDW2`DN&9HGc3r9BnhcLuXgo
zjk|sW<}KswKk5C~Vf-o)GPjLF+8J~juX&=g%ed~pca>2Y4UKN2Ed?Sy#svD({9U8-
zS#bA^(tWUW-#A2n#`3_}d=>uo8a+qhVV`jVU1j~ouF3d)28<i&1Nno-4R-<d(5Rs^
z6_1RT+f@HKWSq}}#$%)JJCJ!|Orsj6r^ZM+X)$d4oDSlQ7=tNp`^;Fm5GI}*$I|0!
z)c8I{!ktY{N8p8v=?+yJx|*i%LZ6%I7=>-!O-fqDdYB4QA>wJeMh{Id({=jyq`jtl
z9`M59ZCdg>T=X%0_zqhAO&6)yD!}yO40HyX_R;sEf=%E30-yGqE-V0Oh^e>&jiIJV
z6e0~X+0)T@z|^t{<e+KWG>j$O^y=quCc@<UHb|t2GXTjb6LS|tqD@<s7|UUkFXj7V
z9j5JjAQNX2Q>o_>lY1<<qoyIMbBH%({|cGorVd*0CYtyk1LlN@^ELXCOer)or%lPX
zz$KeB7GS5EOq2{sGsS-lu(PJ)$02gg^voCYly1tVc<*`B#D0ieFvU><Aj9OSrn;<)
zCeti*W}0kafVpJaKnGj0O!}p0%r%)Qh?QsBdKt5qZ+elk8JA7JYy~MY&8Yz?Hm#t@
zaEYm(cGg!-4tLlsHLYubdYLJj4ttiH%4r)|VY)z%ool9<RJBlP`o=+9#VXTZdQ97O
z)9*aAR-59C@S?`_+9v#XwWhCV9av}jRRFYlQ#K{#8%!M(Hfl7zL>ZPQ(~`yDnoZn|
zP`GJISd0<2m}*}}W4lTGBh2424PC`lc9?#Rg@?CI8|ez{G);Qu0NZ6+D1uD4X&I#<
zdQ1_?(7$V1MT?hvrZ;Jwao?oWpz(o85CGSDP1&B9l0H*9MN0ckK6G6Tm^!Y*nL*Q}
zSa1(b7tIiPWD-)KXvnl`8o0-%GpPW3YD%MB^RVf=&R0Lh)orSwVxDKFNdahmZd&pN
zd>b{r_$xG=%`@i0Cl|9a^oJcdEw-Mj_ja2FR0Xid+_n=69_9}yZRu&=d<=u|HYXLs
zppSVM9r^J!57MU>0?Z$-0T*a)Isila%(sp~J;=O*N^646A18p@Z>}|f3p3vs1<C>Q
zxtkc-L30_!D#Fck`r%82`5Q+9^drq-R0JDkzW6URqRlMIg2b3VPK4b<=Ae1->9AS*
zU%tdVYb9KZGygjlUK}yMe-!FR&DAdfE#BNi1(XTq&C%#PX5P0HGjqZ`^AmubH1kft
z{3&y@6(q?#O$N-<<{w_8Y;Usp_im6>bE+#e(#(<BfH`X(4TDeT&3*LZyI}t04xGs_
z4^D-_i{?iZtIssE+3@$0dAb3hS?12qpq_31RRgdbv-T9c$Tj~NioQHEYah6L^VT<@
zUSPgNLGnWL>09)1mCNS2-7r{WUi>CZ6q~hS(7$3{N$JuO^FI`2xN6pK0d}c*jtXdH
z=Dv+UD>v6t&bY#S<rXBbnboudsx&XS0j|oti8iq}%-_)ByT;skA7iOCTPYA%XAZKX
zvEJP7MPKS{FkcS92pi4cFM>vsSxph9X0x*yXgAGcX}Vj?H%idhYJQn!ugzRn0~76L
zPx`?2Epr^5wdpY5rKiVjbJI#lcAEdL0@r1(Dgt-Me7OvR=r$jijA8efm*2;%-8KL9
zGSnUS%zp-fy>Hf}LiB-oh%UrlvyvW#{pP1Hp>M$aH<hCdng=!l=Aro>6+}HUug!-u
zL*^tplkwP`NT<x6m{-$HHEdpJ1sO5V{s-#M%$o5~cy7M-5zLR8D=AmzY%#4wql?3`
zcs3N>ETa_Qa<>d$MCWcx_#!Cou|x#I84t@|%Jb~Cc<cw~Z5g6NIzE<Z4Cwn>vZ+ko
z&r-+3B=}n_L(mJbG<Tyf(6VbI`u15OC@vmknX?Ox!4~5jSlDlwnFP!bi$g^PMxmB%
zRGuGZxlQLp4p?k-R_>tXrAiDt+%kirI1!fZSKw%*rEmp)ktoYD?4HL*Th@j`J;oC6
z3ZD*Ht_uKq*pfRJ>amt;3bDjlCQ$_ah=oPRTaH?GqyZ(~5^@G4!7|1195Tl&yFP=7
z<Cae@z{Qi6#7}^B%JQi*u#+r9FMvC3IS>gh*`l2Wkrc}!T0f>)#?h5~)^f4~+&RnI
zv*=5=WLjYUyrqZ=120&n(h=$mOFOOAE?Qn)jmAvNpEUrxWQlap(=y9aDMo9y<<2p<
zm}}8f03***I{~2i7N4{5w7~Kul}Qv@F1bPSvc+~3q{!m-1<V&)vc`jySiYz9(pAg0
z^N=jH3{ldk%)%8wz1*_(6_5%`I*sL;<$5N#O3S|=Qnh@QrGY{;*DYKpXjEGSff&UN
zOXVGmqQ;U(iGx~8L?Py>&T@*PK=qbaUW9&wrD+GaM$3vUfHqk~pF*M85_%WprX}?$
z#@k{kpa5~JC6G$v+AMY@47FQIs3!Eb#RZRUoYu6Ic|oJg;<*rL-InQ8Ue#miq@vKf
zmY=mSf6wAf+l2d;_bIdT!1D7J80@votps+TCG-S9`z>j!ATnS{SpoGyOa32Fe`xu|
z8RU`WN2-^5Z1H#qg(sFLg_zi<7UPSMbPQWg(~4%qvgcdKJh!|}QIS!L^C~#(Y;8`0
zc^7LK1FpGRBO)N_Znd;Rf44RGFhurPU!_-^hgC_79Z%~x+TeOw|Ddl8?6sEu1J2vp
zNYNu7YeNV)Uuzvrke~I#2Wa$nSih!(M}YO+AJ7?SeSz-Seb!aqK_<v*q@Z=M)rC%y
z?YGv`+bqP&qgBU2>#}-~aO(|!kO=EQAl#0$e&_*_DC_0*P>;3-WI;W~I-VjPhpdUA
z=sRqkEQ7sR>$|xa(h;kpfxf+U)Y|tKMB}ZFTzHXSy}A~n$E=047d~zcI*z_X>${~G
z;R)-5IY2vUtr`#gQ`WEOxa4W;Y6>zWTW3sxNQ!mOOw98cD~}!`saDZSfTdY)MnmMR
z^&2`}bIvMG2A6K#?Qj9id22UC)Gk=7|AcRu)|_u4bIJPCWsofEH&m#aZ7riCFge!u
z!=RXJeS<cPdDg=gsOMWhqX&9{^*Kd-3#}Qy!tQ13Vmbv_WcB$9T(PxG3Fs@<Ra>A?
zVqHXE)4XbZ>Ax?um0BYj!IoL$htOGWb=d_=71n9AhrVWQq<u}LRayc4D(fsdZ*|>T
z`7^Mqtzu`88&)Ij4{EI6QlWRP)t?q(b=DOR09J2Z{5c$Lu(o^w%tq^i5r{Ndhp4)-
z#rk{~-G8mt+<yVnX04zddAoINJ7)csb;TeQJFF8ajB?xh{2$D7r!{mnB)hCRNzlJz
z9rr#YyR9j-?C!B{rOV^4_0w-a?pc-pEwZexjj;Q`>fZ&FUTg3akUs1F=K$-s<}9V%
z!hrQ(3ib_J10$gL(0Z^5ppUFeCPHS&DyG3awjQS~;uGr@F3dl*zDg_PVQVlI1B_S~
zT!zRq>nutmJhyfoLgT2FJqFX|Y|Efmx{K|~G$^>*au)!_%{K9OG`ibLXu2G`ZCwFq
z-D69q*s7N;l@96bwN-uyFT8DEv(V^c`;d-C`PvTAHS1@KDF^YlH9o{(0&FR%@IKJy
zPcO`Uwm^SyK{oYMm<YC&(|L>iwl$P13$d-I*Keq8=4?z?m~HOQXguJs9oq?d&?cD;
zOW`(w1hXDtE1=S;NLxQG@}g|nh2WxX@stmXv8B;|^^k3X6^<UZ{g4SR*7lnhB;#yr
z@-Y`jY^)c-9knedFXC+ze}tn6wqSZ@AG5h^2g*sCQU~so&9UZRz$Dq`(@x~Ht@t!V
zlWkKLV}vO-Up3Iq*v`|!Ce@ZmpX*4oCENga&bEn;My1<o8lZRH_A1pCUa$>*iN*|D
zM+dMk+Jcv2yqUJ9xiEOi_68ZuvW*P~$+n%MU`&p!*YQ2{b8UYALMG3)f<ox|wu*J=
zylj(|p|Qx;z8TIG+h)*q?5gb_x>ZVTO|()iv+?QbzGge0151^*jQLQgvVG<PlpD4T
zE);5P3qC?)t!-8q6zXjMR)W;qBFli;U@Px&K<1`x51l+{v2CWhs8(CUS&%kc*(d00
zw~f#*a?3V}miryHo%5i0+jh7e20LwA{sQT;xlM*ocWg<?!0xscd;*ako8|&0_O9&(
z`i$T`+gd8yxo^wa4nq%Y>%RtOudQJjeK)4h_6t=s_1kvQf@;7POh?@ZZDTe8?V-)!
z0mVnQqZIHNvfZFv^JCj&GWf)n_Z;M@jZ4*$!!`-kDU8_W(OHmZHhvx&pWCLJfH`XW
zVl6ml`vXb}xY&E+!MWPkzCqRUZg%yXXmz){9)iAy{St*bJ?-yPUdzkQ6k-&6?Grp;
z-rJt_InaFUQ|Vlcul;?R3qQMm7aINTP6Gf9u>VeB=0N+<&(Pavzwr!QkiCUoiotf*
zJ;2;=zeJ0U5WAlf)E%Mr<y1ZwX78X?{{ednZ7~npmC@kB?e7>N6JdXI4Gc!wOU|J$
z$}XmiU9|ls)dk1c4>m&Nko^nF101$nGGHRs{>RTCarVFO!_pDEJ0-A>+H2_yNxXeI
z{ny8Fdmsyai4Ob0Hvn_OE*k@lllE0R!JV>eA7Cz$>}x3xmuw$2z<i4Rg;{_(W4};>
z!KB)MjD<*=-7g<@)9sJOft<ImprrZ*`=1R^$gn$426xdu$OLAl{WE$CU$Xx|f%Gi9
zcmUAZc86#eTJ!C*4uUPPtBS!D+CvI~cG*6MR^~<aClod+wm0nt+7<i9R47nlS5lSJ
zReRhijH1-OlL{Nk?dR8nRM;~qigV4rnEo@M(!S<68msITbca{lCsNV;4SO;j<*Kpo
zaM*xWYnS0t7++^!;Q_ARF29S(Z?F&J6xaAByXz+CH``~^#_^`T;caj&_Gffcx7vM{
z!cv?4UCQ0I+ux{wPaXF3gRpel{`OdqPP@lVG<MlPpiAeD-H(oCciStdzNp83B+~(d
zPwYF#1MQhzc^opM_GJk$@47u_I<R+d-*+Dxp4+#xq2awfY8!~(c7H16i`nj|#grs&
zKT{6#r?)F9B$c||I}0M|+cUpIW5)JO+G$?e?t1~4Ion5RoCVt}Y-lXmesnk8e+}DR
zdFZ^eeNiEt8Q8w*J#-Flzf%C8+;%*nJ*mfz?I+OZzvF5F3?A6=em=;d9lm4X#jzco
zG2oJSd^Zl}Gj_Z*3cL9`-lN!c(GJcMh*a$0P#IbEjx+^C{QsOf6&Aw(%=<r0-vJiY
z@x7gU@9x4b3k!Si-NM3ZOrlW}Thy4Cs4-DvG{zQN?1{0)Xkx=emnt9~Y&1ayM5TjN
z0a37l3J3y95fBkXte{x%dr$tq?|FPY&dhn=b7uCInKNgu`)K`lY)8?T;7;E0H=R98
z-?51Th<Q7<EP_v$cC=9>ymUt^ttf8osKS~}dUwYTO8vOMW3vvfJ=u}70VZDVm@*v0
z^=8L8IpEF?+bIWqufqa&RQfoS(UUaLp`r|&`yFB_kt)=o#}#l>l!Nw5sKz=BF^8o%
zhu`l(HPPW2-Kr@L(T-3(?eKtdfzlm5z6V5x!y($!&vfvj@IbD^&nYP7ImF+CPiGxo
zQ3_LmLy#NV&N&zwAkI7NTZt>7(4lTOTq|;zX$x_|VJ2llTrxRS(IV}#!{!G77CU&-
zJfp;6&bO$%>X5hzK3#M8h!$|y9fmuhqh$_ve}qc8!^RKLcEjPwe)v@35Vss2-gM}s
z`AwBW2W^Q~JCwYDN{vGi1!0>UKE4jl7KgqF2w-vmzZjhOp!EmidYEnvX6zAoRK=t%
z0DlcLVK*3WGd!&->X<nqR2mp9k5VHukq3VZvs#17PG&?ZI`o2RrgwrP%RYkeWVPGD
z63DhAwfH}4nomZ<nGdccqWGb7Gc0}dE|s#?`rFbpbHHH=_kA&m7HeNF{}jz*2ag2%
zS6*xI_t(pIqjlV8l;ku1&uJK`31hwk-8WZy(BFw&ZK(M+f>Oc1v!sOXNv`uzKiQWD
zcFNUCV85Sr8#+@9tkL?zJ$gJ%n|dDqHcj^q!07z=8zrgDI97;%|1@YU8fISXgI>*w
zqlLii?KE_Aj%Pz>ZWblO|2*PDkj^_XAEfg?w?pfKjz_3p=-Ug1MXi(Z?_Ug2&|iFs
zE}A9%>G`-+pxFGf4tLZn|04@lR+`Sy)Bo31(HO1Y+ynqtmHVLi_k~C$lCEA$kK8p`
z9x(8)PaOVsW43nyu!oV*PP#kuvIPnr%uY&R^<-+YV0SOm|0t-vn3Era!kY=DLl!>F
z&f`!CU~U}(?hfOV2~Qp|)u!pFeasx9=jSV?kW!&vGg6wUxv?`ph1kPx?jTF-SW3O|
zV7F|52~YO(&2V)u`+gT_yx1iauk&VS+QJzhR$2;!VeBZ{CktoCpMp5f`qFbKmVGlA
zhEA}pl-GHZE&h>Sg{Rorbj%@+EvM@|o-H{6?gaJ|iWDTWx4of~#NN6C?qt@3rZ_3=
zxerlFWo;W_H;pa(7^QU9i9${p?D@Z;lF4q=g6uTsN|Ca3ZarntWN;jXFf+N*XK*Hq
z>u#gd3fWxucBtlX$+U<%!_B9CoLp`+<)h|t$5UV;pL_l{XwGsIC{R$q{mX#u9QQe8
zqMhd|X97^j{W2b+h>O{azFgoY4}{7^?gu*3c8MFX38l*%GaO`BxC#OO7ISO9rS*3S
zr?v&@Rc>xI3|`~<On{~9oE?2Oy_7pe(~vTbp9xFloNr$MZ*bkT0IuM=gJG$X`+-gu
z-sIFXVWNtQqho8;+&I##;fB+u>@6;MEC9E;P#0*{a)qxU>bS3_!h)%udr6^%2JZbJ
zh&$XjlttCZ_4Nh5iR(w9u4ZnYImBJ=VKr!4xbd`2evh-RK&h3hG>5_a+yYwBwQ(mu
z18F-q)En>zT=+_Gc5vk@(DsmX`VP2GZbAnDk2t5lAs(B!QIuW&gsUEaL3ql2LFvlR
zxDPj?@;T@41y8%UZhEA2bH_eF+Y2s@c1K=vD?-8D!-aLh;45xG9x7jRA8EnjD9K-n
zp>&cwzY1KEWZ4Vgk|q1Mf-^-DeH5isNzn)Z(j=xa&7e6g*;x&mbjj$)sLhc0$H8u<
zr18IGZ^=iYU@MiJssyl1GT{O=%O(BkdndJ$KPc~_PO`lOooSKigCOon9C!fQB$Ft!
zqg@j8A#m=}VfR4oA^qeieDak3Z2?EUr6)}ETKAFe@J6k#bkSBg<0sXQgr^bG$k{+-
zNoP-l$d;zmLF7oa^rN4VF1ZMNu5=O2`tqdH=fOn2v@#jutn}zv*e#F_Ab-zGV+O**
zLTQmBDvP8?DEaDwG;jvs7o`!^6o0-Xt?Y!|%lI5R>|T+c>xbUg%Oa`U4YC0=r@A9E
zg+VmRxIw@-$+GF?(<}?sK-`sm+z3F6tp8B@wPfSF;9<9HCyTasvTM7*>1bxm0Nly!
z;~Vh8+3X(eWqFwms;Bs~w^_0eYJJSwK87>CW}Y-{^EZneim?nZ>v@AxpxJ-|l=hir
zH-Kip**Kd2A29o#VnqkdPDG;=YF7LQM3~u*dQ^s+4RVAyW)_i$$~3cg^sGN^c4;F-
zy4lJ{7?}(+F5|y!X)|>k%;%Ubn}EhMW;`8C&o%pk4yNasou3c$`DRsiC|xvLM{}`D
zW}ngRaM|pt8vs|#4va-*u~~2{SgxAgp`Y-Y*>uYKuQEHJhTGL<2WeVcW47Q5e7a?3
zqR?rr*@=mOo9fJ#(Y(0cY~B*kG?)bkg1ga-qZoCQSz!Vy@0yJp1DY1IkLd~1YL*cX
zz<smxm!Q&a_7TnaJIunSLi3^7&mTc_nyt~m3up7b%i#SXbGPTf1)E<lMP-P2N+8UK
zntx8A@i3G5r}VfCHy;%Sn#1O2Xpc0){PJC>Mw*vzgU&H?%}tO-nHO54htcNWQ!GBl
zJdz>|vF4Nhf;eG*<Rh@0G(Xac(kb(~)1Vn=9`^%SPMcSbfEVfJeP@6=(|mL`oXIk;
z&jV++x#=gm6mrZvF9VTleuZAZdFFdgpfTSZ3DUTp%~#uEpbE@;98h`QT&MzDp}B%)
zNJZvf{ROrQ<|VXYd&zt*2f$_X;ZMPG#avGZ=}XLyrozHi^Enjxy=H#oH<a4U|D{tX
z?dF-L|1y=#_tWy@q4^dHAa|NK6hk~Rx1v|w6LX7806sPEy#nBKa~pbyb(t4Z1gY0N
zhXSJS%tL4+(NR8J22CgVyj(crEDxmErHlNn6<A#5cPLTVO)jN}?jHGy=V)`6_nBb=
z&_kZr2R-zcms9?HfZRxTV~~76J%Ib<2j)W@kYCsZ;6ZsXEo2kr@w946l7B>RycGF)
zTAQcJ-=|EaH2E_ZlupZM)Iy}o)$|h2kRSR1rA&E84MrwQ?tKoL+46;*^#03{52CmK
z8M!_WB3I5lf%|##zbI~yFYogQ@Mq;?dx0pByYq17oZS8l{S<PZR+5GC5tQ3dB%eMC
z+!y2pVQ9N3-$Ak3OLFN?z+INlTmj81^6I4^E0)ig4pAb%h^zpU^qPF>P3T;gM^g@1
zsXQ|pY-MsKC4!gBKiCY_8}hH*P+1}WKm*N6`L}cl+?2aDK~&4%{~4M!@=>%#z9kQ*
z1cKZ0d6Z01D_=<m`0M14jWAy?zdr}AHOMn4wtPn(od%q#QNEGZ0ZsCde^J{k@1=7F
zcjXVKL$t_~nqlys+=cqoDzBpn;C;C-O^Dj$lV`(3fI@r=*8&wQ1_KbHFw$AWP(=mJ
zi^3Ft(h@yfVet|oLZSEqWRVIn4)CK2&2k8wmX5UmFiO#822Z0Ej~!5ZTv0j&G_eXv
zUvQsLc&>stsW`R*q;ZNZR%lC5#8JjjqQapb+}Vn?ci~!&B6ARY%2h1w3(h=6#cFU~
zQ0%=4&g+V7nn;x@{-6bWnWFZ;kdealp(Pq`C_d{0V1?pHJlHA~hf~nsn+n^D7~m?!
z_G7SHtr$iLmQ9L(Dem2@sGz0EUBz5VsBTeo(VpWy#XEW*v??xAeDl8Iiwd~irg+aC
z)DIN5XTf}jVmr-!9xB`@Rj*Sq*F<m3M~cl9e0;3v^oPMG3X7#^e5#l}9yHGszLdH1
zT(L0#++B*(^iF@FFn$7>mx?-?Q1>YQq3Pf&#m+*oyjG+wfq0|%lA<MV6$VNq?Nw}C
zi_$yAnMI&>w0LU)*PJXG2bmz9E!NSp!^L9YZz#E1Jn4aso5jT_4AdSAf11I$TX09=
z{$2}ZHw=1Nd`q(jZ;MGZvGKJyybUEki%lxH=5JvPMP-1+#S>r&v^YX{Q;<dLG?eyP
z+}Z_rxWz1rIvloe2%~J32#eZqAR;Z?=xKY@VrDZ+$1H05z?mqEcAEJ$S|}Ug{tJsw
zhk(sdIe8g0os`=nV9;4<A4lFRlj++$uF3`H;i#L^ZW?f&%JNRA>{Xio0uQ~EBNv0y
zTRC|h0KUrmO1l62lsxUx1}ICFs0~y;JP4fw%5XZ>bx^7L9Bqe`uhzo-VC4XMY=tTV
z7J@rWIba4Xg)4nVqV2FUY$O1Y$|*ESJE9zJ2Ha8QlX2iYrhNMX=A)GbV^A5RwB7}k
z<H~Ea?l#3Lw+)3%QLdz?b*gghd6-XAZkh(aPb(j11DLLyO1Uc;N()Nz$y9##7$RHw
z8{O$S%3|6q%u{X~58PShpR}GSP+G2s-7@9b4vcfTGRhj7H<TmkSYU-R<049x%7(we
za?_-o^#y9Hl&Tou?<hNH65gmZ(gtdiay9MBG%GhKK+~e!wHzI7Q;w*DXjd9)q4_}R
zodEM4$}#((@<{1}DTVa0^1%?aJy9n2#n1FqIrRhdrCYg(!bvZb?i6QusjQ*%YCTF*
z#wB?AO8Fj5-Ciqyw}cmOl*}WTf2;hJZW$lTBa0z?E&ruRs-NYJR}lV|FaO)Gvb^4a
zwm{3?9N>a1f4&a$`z)D*u)E*#TOQO0ES(2}?4V_DK5&ODXV6s=Y*|Jtm=H^)DH$@<
zGJZN#!z|}e67pfotM{N9VVU+GM5N^+%62(onM`ZEqn2NvhvqTM5_(reS#nhnF_wRn
zVi1m7o}&OltmQ)rYMrqBT93+8mOE#mqj8okQ&1UinY0t;6D*x3KqOjT+hYP-lI1(f
zgH5*V9Ee_|SPmWoV5;SE`Z!LSWgZ=5O1HF%f$*@ZI}71y^=d9O_gZ=Nhfjf4LwCS#
zh}HJbs4rG?C=EW$>Kj@{hg&7lbS}bbfD0UrwECWQMUPkwpzoC&wHmaJ!~J*6N_rIL
zqpX@KJv82GUpYKIZS{H^M7ovcC=eM|3zaaKY1N0qe#KS_3UiiN6^;kZRjbuBxvaE0
zLGQ+!R<cUCU1hbK(mtxK?$Ok%#%h2Fm0MPq=pl03swx;B)>@5hqxe^y)xLo+QExS<
z5`*7h_1jnQ;*OQ;pHOYIx-=8+H(9M)0ddzVm=>HZR<mg9|DM%?9MH5{{YFvn`&J!?
z0C;LOih}UZtnzQ8?YUJQ9q8+_s(J%Jx0Ta0lwMdpq}-L4R=emnH1$|jP(13Dl`;{)
z*H&pGQ2WMe9EBX-TJ5FZr`M`4U2~4AU)}@INmafED$c4E^ip+EIa0c#t16$~*KVq*
zqu|9J)x(V_xvQEtLeoQ)t_9pv)xQdWy(-t`sPs||qHh6tn^Y?<!n}`a)E)HDSJk{5
zKtI*x5LEiBs%c0AR54v>3slXCKxL51>o|Uj{i+53&5Kn3`~j7NDsM{jI;2w2+b~#F
zN&9Res#(<-nNU?9`ZPkA%HI+O!&RM4Fn?Ipvlu=_s!ZFiqj*FWOlQN6sy_EXe~+m;
z3egy)TJi(hqE)L$0T`otbRFWjYS3|*IH6kd4LWmD^@7%`r&K+YFbHv~dfF?AS6z$&
zOM>d_HK<Hfb<(;bNwp>toXM&Ov~ilE`hpg?sj46oC7`FNW;CEr>8jh0p_-xM8!-r(
zs`8z{XQ^bAoSv<+8VvI}s{X&DbVgN8PupBo;W;>SLACH1*e<F@{0zV)RVaP4;<D-u
zrC5}!zVU|24b_>O=wO8^c^N7zRl74mc2gA@Kv@k{Dz~$+TdlfD57rvh;0z#cskS0K
zC%vs2B7m({WlKxUI@K*&Ce*7;6liKtrSAsY9o1um6s3)-Aj;KgR&CmV%DXE4PV}rr
z<=%_7d#VOk09sWFI&F7fHJDy5Z7QiB-GA*WYdX;TK=qU^lMdC>@jyIO4Y5OIr)qQ`
zR6bJu=?27ORdx-Wd8X?A1Z>Y$$(PaArCL}3K)32jF~kd1jVn}Ms(zyxV~;A{4IO=@
zl12gGWc`Z+DxIxs51_j)*2n#6|HsvO$e-xb9_u)oe7IYmtVPMg`t3j%^t67lhOSxb
z-HvGUvaSvR(A&EDBUJiW7tr>gul0o#*!8m(cEggtbvXt70<8a<4ok5%5lVF8q|LW7
zaK_oJ$ObOKX0IKbNwV?T2@9qa8{7Awnr1VLR($C;&O>1-+vZCisyA)oGl6fiSvn4F
z%{E*NN_TC3S&UMPP4dsc-?N!Q2a;NCqUr7O#O704PCd0*_$f5IZKl&^#Y>x5+Wzga
zL0THd!X}7vz+T(9*1?N6CYwNtM7*`xlz`e^oB2~=_npmW31D+n@1pD3No}MFm9x5p
zQY>85l4$^VtBw1>?W3Ol1!zLmD=Et}OuaM+eL1Y&MNjYu_1YGwM5?X7M(K!JKLDD?
z)ThSKAgKQ>10YdtS{ntsS?bnAh-~#&b73$?ePS4Niqx0riFiR>8$?&PdM6!gx}^4^
ziRWc?_ZJXX)Wvjctyt}v4qS=alYWD%>XhGM_nLb9LWt|?r<5LAs<t_YE|sa9D4=^=
z?MJEVwdzh2O;_sF`!>N+z513D5Dn^ZAC&H>M^(U!Ms*maz%;4HFc8gZ#WMi!s(W6e
zPc7<^_fWd0{&WvKY*oM00DfORnKpjf)E`phqFr594cr5Dz!a1^)EDWqc@Ndgz5u*a
zy=DsSzdlk&S)lf@dP^XHPt@hKG5A#dM;%;yrtYT5<#Y9s8KCJ>_tM+6Tb;EQ9==e=
z-GItV^_=Ty>rtC3q4`Svz86Zb)$4O$;*DBDdvI^n)s#f+$S<J4yAvPTgCTL|KkA|V
z9~a)gA5>lW_EPBV=YJ>$_W^$RG;kl{yFLS3FkeD>HDUY&HGtuK(GgT0=KIiFID&Wk
z7v4wmIoDA-!n^zn+)=(ZntpBm8U;Y2_!>$Ri{?jthjEJGvpxj;I6oYTh9+q&zpNd#
zC-{1rPM+jTYf(By4}RP-d=PDd#q$p+nv=i>Qj%&S&t{-CiI+*hoy=QF;C%{jP{aFF
z{?R6s()iI%U^&f?nuOs>=dEwSrwl%yrjePvLmD)*_{|@o(v;2bN=7k<pG$ddXZUc+
zjmqVxjt4%EuXg|<pJ!>){Vf0ULbMg|9KA5l@o^MMKhIC4c~v1lpVCW<`2O1<F7U@G
z^mmbO`ULPxd<snoF7y2<{&Iz%-Hk34^Vt+{Eiv)+@1gN3pLz?3Yy5lHfVj>-bAwJP
z|0BKJ%J?ysP%Y<+a-n&HU#`T+RPgC_Fki{Lk=>j8QWYwz`1=yDRP#Smc0dik^Dl^7
zd{8p_a+|+LGof0(vkyvj{E;wd*7K%CiI5Ha)FSlo4j)AennqryhiVhQjt;Ce^Ide2
z-{tq%!?hN^j|y$~_=Jft*vbbFLfd`5@fs@I_~UIb*v{`wg`*GnAPORN@cmB0(T99F
zE&4n8VOP<mM|^h`M*A_p&qP6kC;Tb;4W9Co6d2iOe2|FJb3Wx;nCRjU(6qgqA4@;%
z3w|_NddYuq1(tevGcSl&yeEZWUh`{yh2|SxHV5#x{Ha`M_VU9{p}+6=hzP(Pg;^sZ
zoCMpMsB{**{Y)_LBGk~l*;R0yg_4_KxB`dw2qT?Pau))J!6y$vr~s*_aO?_v+AAn&
zVc;b+(h&x4VdO1X@)16G2Ar>eSTEiO!Uh+#`3t2tU@1U&8Vi*`VZtVO7$iKWY`}fO
zca`*?`|cNZ{tgodgrO&aI4G>79F{}EVsD6GVWcO<D@5@20zOojOWR9fg3BCO3Kzbj
zXZB%1egG;F!Yul)q9TPCW$4Qh;TJk*b5s~Z-wQe>^ru&Al;9r<m1yDEUU(5B{63ey
zR(4!iMMp(qg%0`})(K&C2UJfAU(;Icl+a3>=W#+BjcmMdTnjG}1RwhNL!z*;3nr3;
zb-$uASy)X6zEXs8dakDm44t=56KWh`@U(E7UODN)U;!%l6glOZW(q1IGi3=qloOII
z%%k;kj_^$=%%2g0cc7FjEdLsaJVCJxrF_AC6~tK~Zz%u;!qb(|JSU9!4C8cOXj=|T
zg~G{Kuv;YLcB6DbsM-y{MPc$D04@oGY#}ZSffO>lB81W&U9m~1j=)%!2#e^{z*Rwg
z0;Jc3CW^~l7t&6GtyEZa5~VUBOpjia3$tiSenTi40M{ynt1n=_QdmWaoi~L$e?e3U
zsYM{G7VgtSs7A;sfTdf4ei+(r3qieLsTDq?CtRIix<e16dSM_Xm^29Eu0Y%ovSes%
z6n0KVsY#efDOt_Jr~84wEBsBNhZez$X8res!xZ>z6%HK&>3v~-F521z<q+W7h1GPF
z;DIop7Gxd5;+JT9D5TMWl}@4OHhTR?cx<9r|6`$G8?LJ-!siRnwWk740nBHD70nQy
z3tLZsrc3y#4x(FFK^tK&gta^XF9i*)r+S1%bX~m?{-tNaYhlh;(0n7rtw!ZrL1~1+
zUSW?1#5-YRDsYbCcqLez#H&(z|2d1#Gg0dz@_F#vRV<N0)lKa5hRz<*JsfTBqU|@R
z^bk+AfZJ32i!STE;<vPo=q38I=$f}UVJ!OOBmOuJEWTnOeHq11oJ1)S{^CLtDg(sz
zmf#E&Z3X}kB#uv`{qKEZ28A{Di;<V1b3j}~p_+qYbT`By@$5lZ3KkXB0EUPTh0qKY
z57MeTOg!O*ws7(Lb<m6#1L&|(g1F@eIGQLrj)6*&=u2_pWN`<@bW%i-?vYgS1+BKz
z#L1W=nxv=2uW34&F6M59ry1h9eE60rA~O*$DX}>UcC*FcsQ~7P2QGm0j2M>>M{~u$
zo&u03o__%o`JyMKZl4vGI0H~1DzxA{Cw@gq?dQcy`%x+s-OEub5)a=1*#*&_rqrg3
zVlpjnE{WslVSibiPnp73#BV=@iDGeI57<h?ezO3)DlYm3G}pxTpJ3^_xZ4qqmWpNc
zIx7?BEQf35qF*>lH^h%Ale0qHx&f9d#XIzi+!UMAL0u)f(<-uB?56cwjY+&oQ_Wjq
z+cDJM7MGkuw`;|vQmEF6>*#b;y%@nlwL!c`+aGtt`*b%qinl3p*d$J)%cEJ`vlOn~
z72PTIyG1-b8Y=h1c1nqC6$`JTXZOYVb3xW7?xrVkyLhS;l@CPIxEBC+h?993d?>Dd
z3DGIeiACchv41ASWAW#{=+hH1CK#?g74H?G^h`YJ4ZF|9(T7p$63?DSsaqVl3@R_g
z)0F@BQuG=I^F3m@8U|m9^H>bRYjOBQRK5`>ybqPPVvi{YvR8~91WWJ4>%MTtQRBP>
zU31b{WufG(DWh4XizdbamRvPWG%Iw|<Qzq5k0y0KxZO2LwD$MVxKQS*rzZV80DCnb
zyaT6~#yJhbTT@Fhb01Cce5m+pGU*-Trx`iO1nIBwIRUl+&E+nX0yQ5m09%meHf?|G
z)424Ya=+$sAbdKYc}6}R)Z}YXI;7c0pV$f3bPh)+LNw0P(ECu03kwg!H2(C23D=xU
zhQY&{d+VSQp>d|P@JNk2MJJAE0;kaZcT^MX3x|(sv@Y->O0%5SVbK~dN+XQXSWt}f
zxW;8G+F~^ee+T}A<~w`XJ*gS(0dY$6Fddq48V|Zv;x(0iAWP7c3MeIN!fRnEN%Nex
zQj;~4$HJKuP3BYpQZ)zd8QgzqnhkV6oYqXH?AUZo3|(^>nzRB`W@=Vm1u#pq)DLXg
znr2G*$<Zh%_vDPmNYC|LO&g7Ro+dI8fP4-24)C)YFN%W{XsYSbIj4D_?wIqMc?VG{
z)I6c%P(>Qn43(w}n$4es^rEK84_&*YnMd50HO^5O^(&edY>`NdHB%|eqeQcjUO-nh
z3~hN|(_E#@oa-7bUEQUclxJuw)6D5csa#|G8O-0%jGGQop~+ti3zeFFV}QG<Nu_XA
zmBvj9XR1w_QR`u_MkAx?$}P=_mvHK~#$y;%Yc=Dy0AHv1h(@+v6aOVlG-x~+0PkoF
z1K?Am<`(UrH)$LmgQZ!MxD{QytC7^hM2n`KmVx&)?g3C~)!aG?3->h&dP=uxdfgz}
zHKu2jYxh92sS!FInjBh6Jk;DPg!xWQAWaD#X`(w(daUX4N9l>Cekw?xYG%?L<e6q8
zEwG<!^68vhmnMQ{7TuZ!iE#UcCbkNtmztr@DD`MQp<_3%G}%7^_gb@zmOO7X)utiP
zd8;WH2Ay8bp(J$loyKQ2bR4xuSh(n<J;=j^vo=zPl8e@}9c`}K;}hW1KCK6>SNChr
zQxft4?H@?!mLAj&=?}mm?bnmg7OXAqh6vUE;}1ZX)`F6d!?lwraCumJrw_gVBD7zX
z!F;54)}JUH(H_(Re^eVp89v9fGaTS|l=c;EutsYaS^yZM{f$Db$F-TCK*VYtDENFr
z+e@D?JE>jtF*HwU<E-&B#c4ND=q_FxOH+ab?VsCGnWSC62!Ld5#RfX9o}#@&X*8+Y
zJRK~hX<KR9a9S&&9qe@NUv2OyLwiSu@ygUD*g`W)dxqjK+1d{%^q!-wqovCk?f8DM
zo2#9%9&LHr*K~j}U;9>utK_V939ao4v?E)ga!z}iD$i?s{3!puP+LVSiXyEOW#wMb
z_P2-mi`px+WV@t2<p7$?+QSr#y`r^wh|Uyiw|xmwqMfu8q*t{YzJ>W~+Gk|`y7qgD
z<>K2i`yk4+#z<6_YtK*u>kVyYB{VCv9T5<f+T?#=)^t<*Z39eHY3EU%L$%f?8lpz~
z$rLo+(tgkmaa)^5n}W4k@3HWyPWuH-4(qjRgFxD#o%;dZ4%*H*kTz<=hr_2P?Z$}^
z&D!@zfb6ce!4b~1Xa~?b?4CBb9)MPDO$sXSo3!6k@T*NbCIxKm+6yXJdZ3;C6Dm8j
zj^98$)OJ*Zty8O|)!-xTIZNOlYsZTaPqYW};Neqkzx{CSnfCe&4Bm6?j6E2jF7415
zkacS-zk}urEpG=8UuqL9V7EuRhGvYfw5CnlLHb&oX$ze<+C)lgd#erj3#z@^H_w58
zr%f$|ilc6O1Uz)oEgy)Iv#yF(8!kGABCW2v`IMUIrn^ZIh&{Sk%1U?F)zZc7q1!?^
z(4M+AuHf9OJ4T#dx~sG;=B;~UqP!a)ogZy``s#RknfvK}qJ$2Ao$poX1n54dIAoyi
z@Cv8|>7uWpZJ(|p8r=JJ3n}yDfUcQ5JgED=3gVD%+87uN)@6(WJVf^=edRh-H`54~
zFkRz7h;ZE>b|5>f3+^!i5uw}r7>Gz+4;_O(qWg(<?2qcErvrFQ_k9scQ93``5sKE0
zo{Cb8?%iJ~9oMa;?*PQ=HoOm?PUz;XM&(J}h2tPQrR$*JRh(`it!3kNJ86!Xplf&n
zl|-E#Wx*xsKKhOFUy^mhtueAGy3QuBrRw@FL1UWkXL{<L*5SW4!ELBJC5K9eu6i3P
zGj-Q0QOeS-*#(iUn@thV9NnrC;Lhku={nBUd2fNiJe?=)g5>M$6XD@m-834t0^P|l
z7&@o>^9ap9i*)g+C|=N|Q_A`!-Lr8pcv<)QXSjbwck>K@#k!m4;CG2`{U>O<s;i^R
z@|y0G7f`vbd$JuWrMe50h+3vgq-(ug_bqOG=?&dQSF}~={-GF2rS2}h+ivQ*DMhAA
zw}_G_P1U+pU8t?m{gi><{+3SSkIvlI%^nY(I-Q)pOjNJy`wo^GbhWhAen-boL#a_W
zC=1+8y3#$MY1Vyy1)aF73#GL17TvAE;Jl}sx);v0>Z~ah>Avo}o6v02HPgOQyKce|
zz#o`&n>V7^q4P_Dc&HmnAF}DxO{CZ0Bi&*%=seclr$zr$-CR0Q@k}?8k|&<)x}HIF
z=`PX5)~$P{hNTy}wo>@}Qddp61U<UHX?gNWH^l{|*Sf4=n17>tQi{@B-H$X&>eZRn
z-$v~_T>woR9QA(l!RDm@iRQ1)`e`i?F8X~-;f1R{r345!{oO1K!XEwJuVK(#Z<Y@g
z4}Baxl05arqrkFPKi&_OUiz8$F&5tX4{1Z!M?YE#fUmx_9BqDj%m0=|`gx`^00!uP
zeuUaU{foOm1nJqKaB-jBMAO*)`fq8E?|?pugZYE{5Q?ZB(yymPonU>SBUD24Ln)ms
zR6pf0;9>f8bg_l&EhplaJghIJ;6{W#k2cOD^#Wy59MQj<gwj#HVl?@EO#koqC`Re|
z8kC~-W2sLu`jb+q9@l@!Vn|~3KZn8Y34PjVluqjRUV}KL@1@yJoW5Z<x)!f*ltCou
z_es%~sNYOiV3K|w&DxXoc~KB4dL?DJrRsN$hxcjv^P_40d0Ov9XVBC2Q)vSsLthvL
zk*V)z2A{I@Pw5Gft?zdLJ<QRMN(c8Dz11<;&DBq&m{6WRUX20H*U$L}m1p&#G>0$H
zAHM)g=k)dA7`*fPHxx@M)K77QDAK=w8f_Q!-)(sh_uoamjAo9P^tPVp{bl{q7}&j{
z-|h=9iuF@-VZKB^b_PmU^}+u@<(j@b36`$w1zIwd>Q~wUP^Nz!24~9k@BRVz4ZS=P
z{#NK0Nnx;3A3`CToBCoWXjbWa>CIlP-`@tfsYV~z1JYaioh8t@tv~z~O11jQbm*u~
z-$eV-_4=t4X>HJd+y}rr`pR!mYSf#CK(k5j`Vf`PdbdyE=w1EwelXvn*ABoSJkkG<
z4WFLs?@)~YnSR!naOS!G_&SI#eG)xMyG{B-blB;I{s)?IzSMUX0N<leu0rXReqt-y
zUhA7F<MWMvG9~Q1)z76>S+71g3N-Py$K=pVu+5+>xFp*@2BQ-xwvWxwmTK#I0A8fo
zF3&;bY1@x|QJHSrNDIGA+xavR%eFQBkbv48+jpCwlWSW*8$@}wKhq9pzU@>6{i3#~
z=_ONO`)UK&&e{G%$t~w?57CZNq3vqAo{MbNUjTm5ww|UNmux>xf-{$G4=JEhZ2SBR
z07`6E(BY7)wqxE$<u%&^N}9NCD>YFFz0|g9EJmozHX<91<+hv=G&gKRXr^0XyPGx~
zD{VJkK<TFKE=m@zvOP-sCDpb)k*KV(EvB{fEn8a(JKeT*r;)9-E%_6jsI&cnju6$`
zj-_C1gKf@yRNk?jBEqK@+g5M7|L)t4t^-Y*ZI3ln+ilHqVE%z^1cm%NY=_g-_@V7{
zdXIJ5&hP`^k!|S$Xg;xJ`ho4KZLvGx&ukBjg?Mgzs0Wo@wjn7{>9$?^8veep{ZWp}
zm$nsjnxx0J=OLVVWgDJEU+a8r+e=w3Z)}HOf{C}b_bEZ5*Y+-*F?eTN`!#4B4I?@s
zoD2)>(dKNpwFj154B!0-oU38UZ}7>@(Dw;c_87k0h_1OCK0tD{)WZ-!J9eIib^)E(
zYbYv%1usKyAS%5LYHY5Vq&|knGtggO!#J7|`59^{+0ox{=x>k)8jewxWRPL-Y#{a-
z#z-Lc8_q9-i30}Ldi-_=4XgG-<&Z(7P)V@iRRt`C80IbqXQ*KTkG3#_)e_*s4GSss
zci6D|zw}<ifmi@ck%lw$PCsH8LRZUC!(2+QiZWzIW4xjb<v*jpF@{fQ1Mj$D%^VC#
ztl>I^BTpLk+y^esa4rFs;thK&!JTMuTn>?B7`PcK$%dEdu$y9dK(|V&;V~`6(+tWR
zu#j$eLc^6|GGx()a;D)gD>P;qLOkI`wjpXINOKHZeBt65!{AY%$u(&Ap_FHEqI)~v
zkWh)rvxbGXs4OsiO?%bn487AqcHXddKO8MIJPt->k>RNhow#7grR(CNVId{VTrw2>
z4wlOX(_a*LDK>caLX;T3^#$UpA&Z4?*9@;H)Op=dt$~SB!*`T9R%Xb#iON@ogjle-
z+f`l$ji=oXigE6>JLZJ8gLcEVgDk{uC57d~?cP%CI?|5s5BM>=@4tp-tlb0}wG(!;
zO%+f*X_rLHn^Sh843^^TV(7yI@pkMKc#&ZDJH2-k?WQcHk+qAXywzkok!G_gcBARg
zda7L-4R@Md1D!THZTIIeaAw$<EdnmnZt&NrJZBej4+hWM<tu@^ZntDN$V%<1>u4QU
zW_NBG?3UZDoCuv8b`zJwnF_n^Y3N#|ogD>wZ`!S*cVm^^<5=LU?d+BVS7TRt7S7zV
z^R7ebww;zfIa6!5XAp38cJ(d5)!S*0qO!s6$9}-wvHNNYd}_3_JB_v`yDL?4+<$lN
zzEgp_#qNh3u({Z~w4qO~_6b8k>Ska02Y`F*3%7wZ%)XJb%EIkuoJ8rcy#vkVBkZkd
zH!;$_jZWtrv9Ih8_%Zu2v`&t)Po(!qjQ#Nfuq4{w*26-QeZdoSH`)G{73H6$*qiOb
z@04o)D+MId>_4O92&e5A{{&Cd?IZnQDc|0XcJt5L%U#h{VBcsDQEdNDKG;g^Kbr?}
z)&66eykE1gd<d3O`#ZGdR&KwLmX<f{3+W?x_4d9&@UX%D^E`0gu`i|l15=~@oMo`o
zY(I4oXzto0;(>>leHm@8ciZ3i7OF4om)%02UfTPu$M4f)f88G9wf*)Vq4LH)m%<Bg
z?N?i&)N3EI3vfqcJUvjIjF&G$)7fbC1H5oCZtz5#tMTp;RJs{Q)MI4!n2d{PbKS!@
zfo3M2#`tQ8y~cu_=!}=~N<aARZCr8-2p{93pJ2(?c<(Ee{EUleS{Gnc(LEMuOvprA
zkTHnzF!vb;(E4D%v4a8G0i)+9&^&1T#EAYLGVc5pZ6U@)3J`}HO|>(C2schUipImn
zMPon{WAyrOd1HJ;GxQV2Z|H(JY1H?Hh%+A5p`!`LG>Qu(8WS?0l4SgeCJ)KRGrz-N
zim}BCoT<jc^b|-lenUBYr;SG`6)@cxoduC$+`a;2nZ{M7wHSpg<8L;o%`vXXfm4M>
zOA(Dl#(lJ3dchcM5BDz`_tLZbk}>=uDlZ!+({*vhIELnWCB{38z;e~t?=ae~8OIf%
z?WS??HxO0E-~*s;FpeJtx9=GJ`oOhD<4{_`G#Q&3=>BUqntcv~ca58yfNwEwrcB~{
z#uJ->Z#B-RJMO-5y#RchF?u>G+l`wjiQ$3q(k*Cq7?1CO7yf<19<eZmKLbLx!pg^;
zbRQ2Y*azQSm^!*UT$vH4Al#TaH|fV`{<vrY(w#BxLeYb{dkA1pCZFCpdzo|eBX}{@
zGbHcHLYZuu+Mj03j=|G(CY@pc8H|QDh%%YObkSrnCl8^N&5ZH@XAYD0FI3Jj<LQ(@
zE_00mE{}0q0EhFL>GXI%%k0Rb{F?$Md@yv*G3)jMf1VjhTYiPix3tSv%#2(0-g~lE
zhNrcyE8DjbcsF(<<=gIIt-Dd_&h~Kxz=LHoQ1WCq&%r?LWj~|WgBP3i4=TOcmTv&?
zVb>%<)0f>zpUw1RyRofplKQjF^pXr<T|(hSARCGhlPrQ=oR4l-umM<o%l2?DX}mqS
z;=%ZT6$7}7lfiv}JNg0q4dr6hFqp(mMilD5(f=a)GX61k#!VRc`hXu)$32XOg$b`u
z!@$pOlp6EPs}_J(KRHLcEZa`f#ptkO#D70R<0W*_i;1Q$-(@g^%Q2Yem?{1K_tOeh
zGzaeGUiXLXcU-0demP1uh2zKZm&99vIzX~xCrU@mOmx)dsM+_FsCmrn3rdBHGK;3j
z+Z~nN4XCuL9(9uaPSx12(AcH=umq}aRHa{|<YIk-0!w?Xf1#AL0P8Ch)jMR}yd9+o
z>-SbcGsZfDvO$hp&;0;i#9C+5_Vo$te<&(`()v4^?w+!qy9&LEv$mu-cD%JG9X(92
zF7kp%v`!A7{Nprh)hejwSm(M!oU?vA1#FkC)qlX#QtLCbfv>UN^aiB2tOv$}=C<|O
z%h0T~zVtrK*I8en&xm$fulfO+kF0;ag3@E_;}mIpVqLozrKi>n@i6$z+GP+r@!YzX
zwrsnsKYyQ||J~LKZ?L_vo<v>46f_LxUs?aV9y+hBJt(v7jddagvfo;}&@{Q%dLWX@
zrSGgKegJMqoBP=iPByu;&+lwg=Yf*D&0nLz;$hQEKZU1Fy)$roZ5&>J#mi>sdng6i
zOlgBK1=^&pL`Q>cHkIP%+GjH>4tDq3Jgo;?luZSFFgVtx{Yx5B8+9oV$u{C!m`}4A
zv;jTLu{r$!nzc6eBhgl86HcTJHtWJ6?$}uV3ejvc{4aF-uFbDT80xY4;{h%mNA-Ok
z_PkB%sWi*?QNMo+B3ONZb~Yl_Bff^;$JH}ss7z32Jplf+`nNw}>5TgNO!#zOea;#9
zE9zuQlPgni9|p~8b&(HB4eDPg?s!jqj>6dw)!9p6_qlqL7o2&mE<Hx$#1Fj!;mMnP
zXm@Ha??q7*FMgsMXuSD(6w&qJ7bOAV%WtK(m><7l1-k9e`<J5>z&FJ}C6K?|1ZRTy
zINER6$E)kmwx2KS58MIX@q3UR<WsHzcZio?L1h#ljhmh_feHbL;bTqLsiXX|W{hPl
z|2@SRPVmi*pgGA0u7dlg_)j%ZjpMswA>#Qsn!zOSzf!z1k^e9PT}$FmQG6+xXK4kV
z!WX><pHlgCJurBhuL*)?I)AVpxD5W2LI5&(7uurE;(Ofbuz5CbK`+=G{%2aVpW*YU
zqq+Qh6G4;5vlJo8=Ow=bc$RPL56uF;Y(FfW<JVqA<$3-sCGZyV4FMREQob+(U8>?M
z{sDD8zrh)R7XEx+c-X=3rlhK8eCJYBzUGI2FTr<O-tf*9P<_j<9tnIe@0X9pcl=6P
zCOZo8+2HmT2Af00M;Jk|316Xd6jc0#AL2pkFAVRCwg9265(5+@WRau$glPv=7Z`)d
zrV;QX0xt#iQ6VrArDMXnUf`mHA10wPT5zucAVzpYX{N`8?<i$HR?xqL=1Jitg%M5(
zmM38$PWWULMkHPs8UsTKLO10KB?`0JpqV86vk4+uNTfJ)wjftx&~k)lrY7L?glTlT
zBwuJVLR=BrXMv_z=q!WztHQ*u0K6u|eTq_*VDlOstQJO)Gq;4WSlGQS#M3=_S2$?^
zS&L9cv$%VL7ws{%3IiWP<-V{r2wiFuzM&hvUC>cZ@dF_$ntt96VfbwT9}3Sl0?{d$
znZeQ{!Tu|F@mO#<hSC#ZdkgG76-Mp`%`;*6Q~1;+gw6+`Tlh<j(S9NPIv%B$!uh!n
zJ;JUJ(Zg55uaDvAYr%t-KS+6?a~*GmMMWU%6^@*s<?TDcoo2+2;@WutI*H#Og^si6
zObPTZ;(fYEUBw>@(B>mvqJ_V&xcD7h^Al5OZ`fbl`Zw4DMJL)|4-)5e!?k^)lCG!y
zVi&DakBYt&06QiYlS-86T7*)xIN;%Xc)Z4lEeAk)T--Vyz*sSwe$f-6nvU|G6hEQ_
zrc>g5f3(GkYhoed#n}~bCP94L4A&CH*|gYA5=-&0Mk2%Q2&klr`-XutP2749rPE>u
zy;9S~U#KlZoVFb!nki;31<sTun$v4ATQpHDGe?|x6^&=audwxs3<m!r@FGuqk8(=#
z#R~dG&x-FR!@~kGVF)VEi9`DWa9!-7#d)dt_g`o$7cZRx?uPjCBUIiL4~bBz5`TDw
z(nE3g5e!$S`0GH3*CuhW6B^%$kLfVoTT!5oY+}28CMw^F8j6QGYAgkK>ZEx=3jk-$
zrWV+B(R5Jc*;R9YCk(o2c2Q_>kEU@B+T1n2e+)7Y%~y0>!BgYx0r+0c{cx1LHBB^l
zKAN?1RQhU6Rto|2)6AF&Zhy_!pQ159(|7^gftuOXXbaLDl%sN=roRLFv|m$1BXdBL
zw-2R*ntz=^dPuX2)_K92iI@svpS_IEP=so{DFGr@qo8Ti3C*BMs645eya=UJ8q+TP
zB5@j-X#=?9HRFc?pQwpB1G`C@!QJRnvPMB`&=k#vtMDRKQ$x9@X_|GE#2NYN)w$?l
z%BKf+!kN@hLrTEnG34cZn5Z7=D2Iv0q2A}f@^+*%1uuI?`W{DR;HU~(%p4k}q6bs(
zs9|aoxI;&6NdQ~gsQPA@FB~;e51pb>eSd^b$*8q-r?-x}MRV@h&-<5Iz*GELH-;|B
z^#OOmzM+P;Oa7>|fEOF{@8j=nku)vap5h1k9gE5Vb!4(W1FaKtrWPe<MiB{xy^JZX
zFKE0NAIduPVGhvzb3YS40UQUI)AU)6!^~@1HAFB)FR15?J0%~*GNUNUcY+yL2i!^K
zE}geJ#WaorX)5!0FLj6c{2y34!`%KArCjDCy2<mHnN`5$Gn*-e;xaSXM7z{inEo{&
zEoN-$V4{Ti@*Em(GT&e_i_dL*YK{S@W-hzKL=EG)7nS(H2JPiEG4D@-Xl7c90Kdze
zABG;bF!DX%yvL0G2yVABb$8KrpE>*%cH5XGC(!nUIq)17o-*+VD82s~vywtR&ly=N
z@Li0kM(HhMK^q9Y%)+S{pm)s4Q}Du(?ME+QCw4g{EjqJNG$(Okmr%B$E9*)uZtTmm
zDD7d>X))@~etsA#9<1{`P<yg%l*P7}9Y@bpFZTRodj5H{9`sJ|VPCYvVPDp47=#}?
zYafI^tLg&}1K62EQ3_;t)8rtC_2<F1kFBFU`u*(3GN>G2kADff2id^2XgkE(%!7$w
zR!!@Q5cWAG7KXCxgWyvb+n3Icg|muR^q+woW(`9DjA0{XP(98LEr2tLY+f)rlf)*+
z1Ch+0c?Ojfb`BkM%w}!cQJKTGwbAd(zWEm1x$K(XVK<M>bq4$b+iwNhF0x<vLh};)
z4TTpjvmb2%{0h5&23#v<7i<H-RKlK51ov(BMhAek?4&<Xs$-oN16a@Arbv7vyQ&?)
zyX=i|K(w$QcmaQp9XbrXXk}X|@_3(BjfMAZ>@a%4w6g_PXnVj;D@U6nw{iyn?%W0*
zD!$y@zOb;LbC`(AFca6%3%kd-kt<>16gQjFb>lcsx`N}mEgwN7aB;MXOyrtr$1sWO
zTZI0e;lu`*$mNc_g26m)a6h<~&n4GD<t&#)p9d}A9Bg3zJoj!W0EJu-g(Zr(pe%?B
zoSatO7dew^J-9D%=WhXD!L?k27q_{HzMyI1&ibLPjXV1nDj#zjF9Pv`+e{(2Ue0L&
z0DB~Z{o%d4q=aT89umo9lsqM`FT=!MiJBJXUJ{#o@WNXX`aMdAB>&JSZ-OP|^xO!M
zFs3J<36;neLxf2@X%8t}@`esD9F}~x3cyH7DLo;MNTP0FERITUP+IgcN!nA0C`smS
zv_(stR2b42N$*zRQY3LI_?sn}w*lg;<i$kzbWy@a0)9=h`U7xQN`}xiUMsoI{uf@5
zjD3yT2a>54(CLsk)&TKPa`gd9os#XezIr6#DRJ$wr0G34`b6@4GXPH|R<mHRS8`_t
zym%+M_7a+o()Gb`%}M$%C8|10)mz}2i}a`C0J!4+Q3a=)bU+Mx?~eb;iS9oS>2rFc
zc}k<`h{j%NXI}^}={$OxdQ0nfq0L7+hoUmR(myFl?4a~tSEwA4enH1;f~7r?FcBhk
zC4WPu%e`qRrQP(l3YVrHfo25G3PLjy|9u`<j!0*?qJu}JSqN3&^G^7V9=wT?enkh3
zqorB237a6DT>+g$X&;*KBuRtEp)DCE!ImN&Cx=LtHf@55G^ukE?4Fj^M8Mw+X(27M
zGNoy>g3OXS)BaMn^v^r6n<JIdC2&TX?Fq76sdObOO?gu3M$lZ8o_Y;~m!!8T(fqRX
z2}RkjNDuCTD3)$m4pD+H^uq2{X-hR!u1Qa=z;Ae6x@{ETWzy$WU@MnKeh3pcq@4wD
zyF$9_F)AyiPPr)El$O((sw!#z_wct`s-umT8k2PQI&j~^EE1wsI&CP}?n^5kK($S3
zn~Bb}OAStFdmufp0QW;FNBB-@asV_RN$(wp%44Z_1S+3M&z3^-skA!*cHc>_IHA%}
z*69pKon$X4#Of?t?*nQV*@xTE<|;GgeGa^vEY=?`y373fK-EK*{0Q8hGOuq?+AG^x
z4xpFp#c+^%%c3@-<Re=^YupgoIvHp}Wdms95GJeWfJ(S*3*Cl?Wshn1B|_$~90nt0
z@wCHvMCRxX50A+<o&j}~Y@LZgF<SQbW|)tWEt&<p$7NS(lP*>^wGHEZLiS+*fG1^c
z*-$wroAM)m*z>YLdQ6tcT=L<4z0C0;DjQ@!(QM?cY-k1S#+t1=2C_o49dBX2$SlAY
zm9=Ie6y|6!%k%-f-Rw_0y8oV-_0X>EOS9HAu=SYTr3sU#`QmFp>@~Ndo$r0--^Rmy
zgt_0pP)Ro5+>1dtW4?}(9}3MkQ?g^Nx$O-&iqAoWfzw@HMq4`j<cDd3a8$m^99>G1
z`%?t{wEThwDwpM!1L=6p75TZ(0Q6E!vqG(}qID}uehQYZb$`XthX4jD_Iv_|gB0PE
z2fbhM{Yq3GP|WFu+aZeSluQt+m}(D|FvW^?s2o;&L)qLBir?&D@R(vAJxQY!1MGl{
zR_JJ26sss!P<rDjg|G^Z35v<1(ZgiLFFtTMRWbQzaHlEq|3X{3qUI1xWGHN&p)FJ4
zN)hcW#Z9`!ixu<jAg(GpDE3jR5S3`Vp(sv;iAqHweT||@@yG-(Y7{G`f~;0yQ-;b$
z#q>u|F*#c_(yp(oMe8LL_gDl_(A~qLloEq|E$Zm$<!`Z$l4$o?1PlfKfJN6+jBKz)
zDZPxtEMlI}bP#{Uc@Fsd=S#FvG%t*@_~!f2IpqZ(kHEhd4)p^6qM&!c{_=<(zl%SQ
zru4EUTeHEs^lS($Ei=-(d-*j6f3KKBdzUM-?eX`oT>}C8?Y$JZvFaaMx~|qy0@l{^
zJJ8#0E;Mr6p9O+phtdQ8b})Vi&VO8KvbF1%;rRFN`x5Y&#?o*)G56^MOU}#}+vxMM
zE=;KbNFQbgWefN+m+A5E$2_4_8h@rd1R|K(Fajze%=$TC4`tRO<|<8O&hLO%8O*Eu
zV9RHo(^1ch%u9N1UuT^5nf-5AvM3KTf;CWXTO@n;EclMFPbn;al#MqXg0W-l`YL!D
z%ijJDwI|rgoghqLM^wXRB3qw}QW86p5-Cr!J2;fm*`1RhGT2G(5Si>MN)gRv7yAQ{
z$8H@66Zz~07yLejY|2KMFJdpJ0DghJR1D2xc9t8=mask+CLqe#xpaM$vx(>6`VF>@
zuD}Ym%mz9&?8%8J-C{ooLg_a9HKotpVM`d48rh8Z@l!OhCk6rD%!d6p3ufmQ!EPIS
ziDI7Z><NE#`w{DK7M0IgE(m}wc6S2c-K@C-rFXn$7kmV}j$9W#*`CS&rt`2}idO7F
z{dZmUG9L7deaB?d=s2<;(}6}O_M$U-;>-&DfpuXEPQ#ijJ2n==jeXA&ZF|_E6rgoy
zBWU&N!Hzx%xF<XQzqc$~K^rk%tZDgeuz9on=*!4H>=t@K`m%pNhCx3z(H=U%Y<U;F
z4PmdQqAipabI^92-P8t4Cs_GS#s7IJUg!hw=M7p2-TD3L=3TJ40q}*78Thhj19AMK
zb%G0v*(NY7DSw2TrKShJ!pCJUxnNtq=3f9-+#CpxR(8-n)vtzYApK3@f%;WDF9PuU
z5DK-dzB(KfYwx=NwQ<ciF!uL@#i-vNK(EFf7Y3r<l^KlV3)sq-;E%dJOz}_DCuY(F
z*z;#3lw=XWbeUA}D3BTPJ`kbI5XyKCV`krl%i+wKe7F$7u$xeMl<7xiqM1R~5V6d&
zE>xakJZbKoz-*@6%Ii!3J#tH#G|IdvV~R>)shn9udCxbPm+MffW}3eSypD0FHB}Sy
z;UPNS)y{-+XzXGvasYhAh_%pp%j6FM+dF3D*Wh+yXMG5o2=<{5D%06pSU3IOL#Nw-
ze`GP~BY??f>es`q97g>Xd}o*?dbH&-TPe>lkLi)2SNV)C0z_vSj@H<h8Pg;BHqI3$
z@dEJ0%tv%_lrWQNf9oo<jViA(Q=A~KGrv-@Nhvdif&$IV8_JTt%WS5+pB83XC;HLJ
z1W~~55p#b$%)ex+4QT6O7Bzs(nLV8WFI?DXG?#Z}m(f`gANG*R0n(QpvJiH$;c@}0
zhuGW@h+sByJO(#}{i7P<7<)1h=A+oYv=oVE4K%ZfVT~;8CbAXucuZp5Mgy0{rZu86
zn_Z9zOF3-zS-{V*A8&;-MXb+lR9;}c!vVO+ezTh1zn9nwGFZkQ{uSKi?6H18++eLf
zLk}z1rY~WsjvZBkwt7~79BmEkcXXxRVJqICt&zP?E1`DQg%)rR*ymcbb+8PblYYn^
zo(<8-E~BN_BR23uz#p^GwCDANZTg4q|EKI6+82AqTGHd^IXjM0e7e~Bp<wG~r~L!h
zUa&#;;OI;Cvp>+a9`;oXG+(isOHq2w9-!pXH*ENF0N%20l=|h(4Qd7;g!`MOSw}eC
zpXf_0mqX4ZbBFdr6mi>D((&>du7_eG54lZSQ0pY=vl*n}lFjt0PLzav0cXxiR+oYF
zx@5r*aKBz+wgYU>BxPG6UQ48>|Mv(em6}@tbW7SJCpD=%rOVvGe@lq2H%k|Wfa#ue
z^$yUtOFz2-o1M}_CdyfQD*f6AsxPENmci*)Qhk4v-buscU~`oz@dNyKtqX%F!D2xN
zT>*<W-bUl%kqXc(y*mZe%Xg=vb?v5&=<vFmTKv7GKP?ls{#k>6Z(~JpZjb#EC`V=o
zrJXo2bDijTqbGBX(x&$^sdT_0kcp&xq#$M;#lS+Dsyir!G2@q_Es7Z=12CHDqE~P{
zvuZY+Phc8o=QfeKU5&O3=H_EKlgZf7n=*?D+Xr|y^Yks?Im~O?k37SS@PaS7Oy5lU
zyjvdQumd{z%$9dF)J)g~hyrFN%?i#j-X{S(&vY#ScOi3*BK}3p#-%7-U>4I3=0#@1
zT4-Kko>74LGV}g;h%3xO2BMhx@gF!^!nEzg5L{)tX#4gW<G2Hr*O{~DfHRdcl{Kg>
zV{|GM%b6uraOM^>dq0NmHY1yh@v3Fc>S3vl8BVk0dZuqHyl7w=jzguD34b5l_nBH+
zthO;Rfq>(IM$y3s%;gQB?qG)N!19p6(u5uopVJc{iQTpWWa%dM7(GZb*}=C!lg-w>
zg6bJIDgdfy*$!HxoM(Ssj?P?QSJR6BGMilrU<vyZ1xT*5+ykiGV5@%x;1=uX0+nX=
zcRJzf$d#;<qZWTe2kL7WyK^f<IQuXQ(8Fv9h)j5<+EJh|l703aOdnw<(P7i0tQ~Dc
z9%Hu`!@DR};9xVFZL5T_81~L2SUJwNuLUla&7y>=6YM~G5T9fp(LDVWyI2X$I5wmn
zn(^$CL}(_kPiQ)r$ZoWOp(OTm%3Z?eZ6@qMV+uQwR@ND8-(OHV%Qi%Srhs*zknd%7
z;!gN|g*DW`nPPTzBUDOQp0egE+1x*2{wAA13FB4l;S`jr*}U_>-C-@iK}Q?eB04hA
z#EzH>Tr<0wBF1;wH58I>F|q5%pz$7icoTrF?8IU?b)P-32rjm<ztHd3&UR3&_yPO3
z0&E@ZfQ!(4$Qmj9-N`0qqU{ko=s3g+c0NsSU$VX@;cpLHO&8HCb~Qy)Ub7waVS+bo
z%0+0tWrs|F=w(fB1JSsLyV4iq<<2doho&Ew(FCAB$55>J5a&jRy@NTsCX|kFAr#v=
z%7y$6z)9{#7<@X##n8Mtl}o3cmo)A)eaZ3+ca-u~bGa!L7A)c<v_QVVB~t3}MefUB
zXqIxlCIe&{_X$O)$~mucICX;?PfyYc?oAciDmh0wlXa6@9ss*l9J3FWs=1kzNLj<3
zH9_ST=kx=dxy_BHSYa)9qaC7-EAfP==Q1f{rGaz44fq{yXBNmBxdGczd6$bwqWzy1
zZZIt>?{Tv8FyG4Eoq+zfb5Ci4^nkni2Bi+Jk={QKx$k3u@8lM=Lp<Tu%!hc&*)9e5
zGtTZPG~aS->1e*A#EDX3og_~v>(5ydO)4%D_bq61m8|^`nr;%$czXYMNUp13$y4%f
zI)=tu^0pn$_(+Z%gZsXc!*m7uNi>uL=r7r^1#KrJXDBqAD)}xKfHM*!g%=7X(@#L9
zL^3HAl@BDBD6gVdy0{fyc*y3^$au>>r<IehY;!(T4#=A7-oyPDBHN#e+ECdDS6B*@
zSyNatT(*ri@(;_(T0t5q`$dGqM`fAc!qF(1zY?S|vVj~qBTMo?<w@BP8<3uo^`})?
zoXoQkxOiDaA-bI?V+tUWWXtOyl4WlH{%>Y2R4%9SUoe=KYzx0Nhs8yiN?7`(=ofgu
zIC=oQUUK$3=qyeD9)JJ-<}nyn_Y1+l*F4^cf3LM@h0b50pF{uetUln`!qYFc^^1e}
zdz&BSt8Z^~!QcPP=!L#3GtQRAo*8l()_fRK>M|M<#={acevB9e;m?d|hW7!?;a*%N
z!Avo|M?;tjy2C>mJw1`a7?G~=aOS&KP$w}fa$zllad!h*F7twB(C3*8bdLNo^OV+K
z*O{H4VwftKnhf}OoB3ioN=?iv(>-|efI-LylMTkl45W^%!*Cc3U|VQ+@d#Vx@&8jx
zZ2O?XpV{sL-T=mD2%y2t_<BG?n89>}Hk6Um7I7HUcMNPsF$3w4VKj4vUO(}S!!EEV
zFdfL7$LrFH=7UKrGwk5wX8bp6A5bRsdFIPMVWN=P-+}&=F!Sjhah2(|L*-2-ib88u
z%$HvS-@sI#Lg^0k#byjgBeOFJE;ligW`gAu8>xm$9Q$V*T?DM}B=j|b?N<WLM0PT*
zM3UIi^cksSHi(X^rLcu2O7SaZ+fM<}z^?rm1|zsx;~^rsHNT_n2)E-JOdRD(IM_YL
zef|kL6U9v!kG5zobpUWNT=G^_9_N1A43${Ug9hOQ_p1|}ImvxT`!9ZyKL?=AUowUk
zi2)K<da(vdhHW#Uqd}4r6uaCfaY}<z`z0;3HFrP~j%kAQpyV$(Di2A<)T1(3vV(Ht
zLnNuQVK-FL_XWD<COb8QdM`8o3w9G^skSJk%5rH=o-W%?XF4-wrq}4i8CgLxRPtn7
zX-#xi7PXzyEYHa}9;)54QHP-FZB`TmOL1mBT2$i8vRNoyG5c&Myr?uY;C#Y=Z`L-p
z)d1~>?3y%q`GlQL+v8nqS`ZxSVfRvC$(?(AlivLJBNR`D!EYDEVMM0=q`|+ZyU}rv
zAD@|Mhhhdx%a@;w@fehuzFW~StG^EZ&aQ|C_?H_$fpqc69<(l5O1pYXW83iWWkJ!X
zU#^-22Uh$(8>n>$KE=P+pEAPw-@h$@|6BGQh0ed{%2B^7htj~^m|@7{!n$xQy^q{Y
z%(NQRdNAv0f#u2kPTMzeOj9lZY0Sm~=wveywCQ!0iTM_77no?u11e$qT0xXEOg3Dv
zW=bc(-+HE{7Nr)Z*9@f&X4p9Nw2K*91l(J!AkpT+CJhG8lO4PAzc~uVUntlB-zO<V
zjKt&^T2XG5n4{k>m_>iVi<iujk3sXAx%MSU-!PF0z`tW2(xDwk*8Y1`y0FUxXu7gB
zm%-%DUilZ6JlMqzPzho`O#<;gwm^YWJp1}LlyX_?=J)>lX-t?(jiw-5HQR?$oNL%W
z?||_ZyH<tqxXq4O1XL|6&<@`{_Jaw~Y-NiFq14VkxeC7?us_qS+sRI$<?<tzr3gt6
zn>`Kmuh=0Jb=~{_YPt5HsH!l|J$Lu=T-reMQ4(n=Ci?^ycB6*@sU@qtQVYceZm`Pk
z5(`qHVP&B?VjB95C4pwXz(=LtEO|(pk3=n*$uv;W8Z)pI5hpAAoyKYE-)3a??(clx
z`JQKX&z^g}a}i&@38)hHD=@uWeEJ3CSS^;n3B8IH;*$^Go|Xq5<m;<mVepHvbWM1a
zFLV2ZWBgX_y6|Z=QtKBc@m-l4!cZHSNIU26v?I&m6KDA>u)Bn9<m=iM>~J&GSF)x2
zUWu3=XV$XgyuMV&mb*Z$VXNozebBWms0X5(*{C?UuV?O9Xf&{?HHdi!%lI9hcCtl3
zf@)-gcpb2bHQ#`zFWEbNFmr$%F2fidV@r4~=s1hyHJMW^kpI-4W;0L2*!Qg031$b|
z#Q*t7C(Gnd`k!IjGx<97Ec=8XvOLE&pMd)=mNN)&o(1M3wX3Yk0r$P^6kn=dV`Jy@
zAz>Y>;qW@!JQ&Oy%+AXZzp?LLLTWde^9N9`i<JooW`SrN4v{*sh8KV9#iJJyOtW~B
zAM^iKEbE7{iZfyx{|)F77xBBgKCw0xoqvd~Hi*8VYN<sqq}ufajMl3XCxB{F*$+bU
zn9A=*gneE$dp#ukRj&+ywZ-b)e9~H>4&cS`_tal6LriPc$^4k{Ms?d9Fjq@fzD@GJ
zG>q>v*H%c2`EGrkH1H;dW|Ne{*CO>&)O~;ksfTZuY?WT+6T?T+-jkqqNi9<mg(BH=
zp|D%pwg^#tE^QbJg+0<V9YSl8249537O9X|G51O;E!4k|rVoMoKI!7!(AzJCrGt4$
zs%UM3Mw_(kDa3tLs(KE=9Frd7#{*7C@2|N%+l^aRixD4xfZvQy$cTi@Q^EWRyr);C
zgER5Hw-7^$nSX)pKfeprNsE6)@8ma*LMwIQR>Yh3D<(p9dg^b;J)@IHnK@<*>{L86
zb}_=562c4HQ}--@=(Mx^4Cb>}_=^6yx_p?<+V}%{XEcW(#_SGX7@B#5A8vBYzYb1L
z$UI2q&f|}8<uzP@1sVIuShRFSfs=o_4();uc<I@huYu&OTQO+Q4kh#!PKl^Nj4ta+
zbhr!N1<SK(9E=u?xPW1LK{|s_iXB(c_Kq42e%YW@w9C`2;J+$_J&8mX3Vl}CXb}Rj
z58|`c*T+Zn*+@rz7UC?4HbbUYF7_I79mR!Zh9ucLyTnsuDDmh@3S^zj<8d3xJjJuU
zMUGq<GHzXo>@D$9Vz;o(kZ8+F&%i4s+MHOLBTq<5&Nk^yM!o4jysV<a(tM}en?-9b
z3&{~>PIt7K%ju1Jv(X%Fj5SA_VvUxp5|5|Qo0a2q8}xcw+9Qm-!}h~c^?JCv{c;q$
zbZ(DZ*2#_>r@`sYEiBEGeeP_AVS)d+N6OMK!u@wT<$pU=T7MDNpQjbud_(-RCwsi%
zk!Euy)tz823b~~YQKq-Eh?gn!s(24Q-p(W%-Oh&7t}6jr>adG}O0!+e@Fx7fj}Ja(
zIi>lPwpJ0B3YS{3wMyX+1*K&qW>3k?NaJsmFvxdsWkI*36m<J`_t9&1ad_pdE<a^f
zm;b`*(DCWX+0Trfn3)`Ijy3-Mm#GAo1<XvNZ}XUz9&40*=_^?irPLn^*f5P`e=&q2
zTE%;mv=M<{B~#$4pa81+jQLY|1d?0YsFvvXNil+E^s4=o?ashM{j|M8R4H#eg8UDX
z`%u6m%Bs<tdlTrJDmH-To?s)Dep&NyxnHcwsxw(*Op5KCW`KXVHO3liG0M>vt0^Y;
zc}IMFylje#HkwR1d3kX$vZc~}NrNj`abLR2@&pU&rS(zTIYKoJ(`hFOtI5TokQzDc
zA&nkzfu?ilrY!*WpdbCI*V=_FN-=;tmufhyqaFZD@~20Q=v+rjjNrCY2Zt=unE(rD
z9*1?*#^DGJGXvVm1z-~&pe8dE;WC<&pU{kGko#y0CzGzypPal#DKXH=qZ$Bv@D^Q;
z0k@hSi3PWtmH=3WhB{-lb`}&&dJB4w&^!xz8>kJy282>r9JuSq6~_$^r6x``kS3n@
zhS7|8=q82HRv?Ds56+GXC%YBoKB}?8)DG&gYR3p4(-50>1gdL-&rdWKO<^X<Hti^$
cJcpCC6Tl)bQKwBiQk@W?_4$xYQQFYI05^%L{r~^~

diff --git a/Debug/Libs/sta-core/src/devices/stm32/bus/i2c.d b/Debug/Libs/sta-core/src/devices/stm32/bus/i2c.d
index df5f8a8..0069c93 100644
--- a/Debug/Libs/sta-core/src/devices/stm32/bus/i2c.d
+++ b/Debug/Libs/sta-core/src/devices/stm32/bus/i2c.d
@@ -1,8 +1,8 @@
 Libs/sta-core/src/devices/stm32/bus/i2c.o: \
  ../Libs/sta-core/src/devices/stm32/bus/i2c.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/bus/i2c.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/bus/i2c.hpp \
  ../Core/Inc/sta/config.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
  ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
  ../Core/Inc/stm32f4xx_hal_conf.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
@@ -30,10 +30,10 @@ Libs/sta-core/src/devices/stm32/bus/i2c.o: \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/bus/i2c.hpp:
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/bus/i2c.hpp:
 ../Core/Inc/sta/config.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
 ../Core/Inc/main.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
 ../Core/Inc/stm32f4xx_hal_conf.h:
@@ -62,4 +62,4 @@ C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp:
diff --git a/Debug/Libs/sta-core/src/devices/stm32/bus/i2c.o b/Debug/Libs/sta-core/src/devices/stm32/bus/i2c.o
index d65c3df9fa4a7e2154cb11dadcd7e6ee5af452ec..da81bed9acd505d838cac30a1d7768aec4d0b562 100644
GIT binary patch
delta 131808
zcmXtg2Uu0d^Y%TropyV-_ugC7*n5i_jj=?Hi8b~fW7J$hQN)HIRzy+64pKyrqJk&_
zHl&JxB2_>{5l~RScliB3AD^>lXXkxqc2C=#olBnkh<)xOT$@X;UJ7W*%Is}=%Oout
zbd^gygL%pS|0iRVUH=s&%-9nW3Dd#a5^|>YuuQ^qvJJzzjNx9*<Rwi0bsYNIrjbah
zxOxBzeiab)Z?L3Z#7=$3NtnyKSP3)H_AiO#insltpuG>#<OcgC5<6t<ieXX-(|oo<
z!Yr|!AvI3X?jw*}ydhfJAgEr%K374M`%*4pb~UN@D55Kxotu(J%wKs*33H|?xx)NV
zg2UNn<OB050Qw<K$v7kbEJ&EpX0R$@j(NdkT+=glstAw49N&!WFzj5ArZzZ3=lgyE
zIJ;rJJgYeb1q}u>5(y_)EM2uh!o-Lw2~*T?3Pk9{hQT07Y#@_JO@<DH{=7t#NNvVG
zbUu2bLLzN$982dt{uCtA)~4BX{$K0g7>TsAaTQf2)#ALn$$`$h*GMGNe#XOeKG!{7
z-pYP@uTmnNXzB@T%!QvgiFB%Y6rBh9DkU<r?G|Y^auOvnON0A#-VY42Mh%kayypVw
zG;Wwp=d)%(-lD-<IuH6skjPp#tfF(L<%~quu7Q*|mo$<}WbGSj=)CDS$a^)lQ_q=}
zJz0sYcQfiT^DG1BgPPUL2Xs|QWP_X6%N>UUFy?>q&+mDOZ0!H!UH8Z&vMJ5ZkTF|2
zuv44Yk8HqOnMD4~T0e}O{HGd5!he{|N`&<r7D_k^Bl^iO6bkneMd6SR2c!})2zBKx
z92CP2vXVARav&R3`R)IIkSI25q>}a=AwQCkR3r+uyPj>p<hyrb-wgFTj-Ja!7IKMP
zrc^1EW*%-E)e7s7VueK3RHLxW+=!DV+Ik(CyHuwzJ=%$JY@}CM-nmcW8n)it2EAx$
z{+|LbQwXcNql+p=p;V4Qzd4J-GRS=&*OPhaew(u~E8Nq$W~!raL|DAQG*L9mbC>a}
z7~Xvy-<P@Iewpvi3~<ln8=A&91x;J-f4uSXu8L;1=kC1Fvhk~(xGq9>1s8Qvj*}k$
z=f2oeA-(TDMrZ;Pi-Z=;LHFH4Puw=Qgy#0N1SQPb1}K`Q42R+WaYix&<^MaC%Owg7
zjU>9Q634ZkR9zvkI4-PWa6JEtByE;UacnqR#Ic+q`IiQy6W2n4<M<jneux!t>~(;6
zl&?7)lQk-dT_MR)t56vgO5nwJiSF(`I<D?d@{NIXKJZ@xRD6)(SYAV#o=HS^bs{;J
z(v}SL`Gs2h^e4#=20HKhjNE#;kM!5%62s2#ges3DNqjfx*d^<`@~GUj6QH<=lu||z
z#qKr)zUxn_*6ZYiT}FK>Z%RGrV<yyeCG|Dfjm(P=NHYr0oI>(WL1tE;Acn41($sz=
zozn3nX}XxsO@(C9&TJ;Y4K;~w_owF7cgWb1pXeC3m6VqHliXuI8NTUAF5asn7w7ns
zLwqP5$5fJ}^a`O4P9jujI7tSkkXua-61Ms+ohP0mhg#Nma;Dvv!2i?_`@CL6t*9Ta
zv73ov);T&B>Iqg<N{%WjN&izFN#6G+V+uLBKGaODVPDDQqd|mvd7s#J1XJsV79{^X
zh){LksWaho$%(m>aQzjMeqTtm;t(mV3nv4AXApJo?j(O1Ktw-VXh^$B>D-(|29lQ%
z#mCNc6rAW75J@_Vo)h+?ig-4jCX-9fQtPR?gnc`Xj*kjSbKeJCe}&|i#YETqS8}D}
zOzKB>Ej8zclYIGma%)TrA`&hV(PVrZ6p}0PBu|u(v6ri<l|M$utqPJzBj~)hjo8{{
zlYZDRx&-}9bbR7Rk{-?K@Bd~ONr~G*el4sY_C@X_dE-ev=<iKVY*f&*(EB-or?`?6
z>m($Zy`LQI+MSNu>Yti{+0^>5FEKQUAs4qq5JTP*>R#P2I&V0gcvg&nMY|-bet2WA
zlKJ6>=qNU%=Ei|^ezV@w1<i=A*)%fq(+l!_QA6q<ry!ki=!ZgbjVF1;aWe1FhRm4r
z$YlErLS@||hLa|0EjvMOJx!*gy?r4WQ`{$|+3l&vm)nx+0-nx~93iD`_vpM?b28An
z{>qgeCe-3(WIiXKS_2-_uzN2clcfxuE9?8cW;E$IO(mX5iFAJTBpnC$B^S5Z1E{!K
zMs$6A$cgv}qDZKJB8Ie}o|(6iPDE=uiu*~^FPStgPNeyhH%T7NBGNOxNm4$AT3?(X
zCkA@ZINddo{LzoZru~t|U|#);b;CkC!OBJvU}60;+O(X^9P3T0Vm;t{z2W%2M5KL8
z#{~*9S+jupeRLv8zT^=qzl=uiW&jz>m`BW0OGxv*ntK1&6w<tPfX-v9Ngmrtr2Bt$
z{R@?;e>xZAo34;Vy3kN(#gGAcDV=Y|mrEh3!fXN0bPl=Ob1t2`%1IuTNG9LRqvP+%
zWM=SgLRC#7Gw1t|{`~nQ@oGWGjT;G7cS1(*|I}OpJZVY|<~TB6UVkl17m@jxPBdJ1
zZ__bkEJ+p|rk+jMN9LC$l4N@}NyPeBP0cqlS%xnpKF%f7`r}Y)U6oG!v;Ux@%i4M!
za>6d@l1L_VnvsFH2c+63pQxwyCZ(sDB!BP&oo|~%j$TqyZ<5;61?qT{u<2Slj%h(U
z|5ef$1Uw<lF*it4+kiB;=hNK~G@Ue6PUMy$i1h7m7Ld{|8!4?hLrP2AQuCu3)Poiw
z)Y`6uju}dFMb(6Kas+bJ%#*RwLOLFrNOWP&)W0=lq%-*s(wSf(lLw!YLqo@tPM4qP
zsM|`dF7`3h*H?=OcFL6+?u;dH<uM{X_%}(WIny!zI}uI2N9SJa2_^fRH2+H>>~;ro
zQK=!P)sAHBs0W>Qy+itkJ<0X%)5+xhkopmICbs6+F~3Hiej}nIdq||He_+DX=={|)
z0t?p(_I?GC?!QgOI*g{{M<eN6383Q)%notk-je3{X~bsyT<=P&dd)4wqpN=i_hV*+
zZ)yE3LHker`@aHnT71PZS;P&+Q}f*V7i4}7fs4|JbYvz`RHx9WL`%q(caNyGE{3p|
z!bt8Zqw`Fb&U+7_ULIaboZ;8%FYyl2-?D&of)<g^&|s`@aED)}N<saHL0bPN@Y_PZ
zFE1fiRxKl#Y70@UKSFd%1`~Do?=*5f&XA<#4Pw}j6&db>@g$FqqT|pZB$w8IUoM{}
zw#nOx$D1Y1gXdwzE?NA78m2EIlmB{BFF!cegS|+8eiu>H-5@~6-gF);#q?S-cmYX<
z_M`LgPI4TRFLO8wxNu5INfx;^?TQTNTWbUy=L}_WoHvVlU-^tiblfA-x3`{2qzcS7
z@xWXs!=37+Xz0^~JY8EuPF(9osuS81tmF*2XlY63d4mbHb_k6}Rb!&g`jO0RbfC`k
z9YUH(E$OJ1l3Zyc)I<fH-(5n-O8a{9@$IkVb<}F|bn{{;O3r4H`9TIcFU539DVZ2b
z$F*zea<D06U}ODUHmD&v-QXm(cHK?#<ob)HnoA6SW1^;%tTvFNWrsza&&6z5DH$-0
zEEb1g+NqRm!&@4L3#s3VDb(Y0^>@RX3q(C`A@!_H{hgoriiSP2TBHVvf_HcTgPPqJ
z&@XM85w7Wy7@Qj(|0@5VMuQk1j85BYRP9)=H^O@h&ZqTFflI$S+WW%G>ED7-nQ=ZH
z<TH)*E|?WK5AxrZ(>=T3SrE>bB++zyjX?LnreK<0+f$Z8e+T0=9{%lP4nIS2gxO8=
zlB3LKJ@k$-4NRyVXFA6~^8{0hE2}uk%s2v<PBHV^z*D;yGkG3*eVVDh2K*T&Y7dNg
zGgphDdX_o;Cwx7}c+)q<huLO@@I3RiHHOHSarQ=Wf$2kYjf>2qt?0rfX8me#UuGV;
z0&s=t77P<tnW9QiUt==p?e53CzYR`*rZ5)5>vm>$Q&a<(v-G75WWGNHK8SgsM`JJ(
zei7U^m~&OI8^XlXZ0;r#Mz8WvCLkVcVa$Pe)NV0%Kf`=D6Oj*i1QVYCVI;GU-osIh
zZxNii&17joc8A$RFRZ&v##?AcGxnZmU_ORX2cUSy{AxgB5)&{Ps?V8I4j9B_ChZ}(
zQ<!NIj7%z%Rt!fo7}F+jzhH!iz-2Ov>HYVTY2FLPYi7kjjQSg9P+PF%Gk@LyppbdC
z6D&oH`CqV<GR=H}D`QUCd!iTR%oGhQy=Q*!3#Td=^KqztU^@0d+ehX~Yal9_uT`jh
zVjMQ0t%@1F4(6*F$F>mGFh7k4{0s9;1z{~Siih1grlcI2-x-lEuY>dm&9@w-%{}4a
zUMVx-|L$OW+lKU>>0K}bL%hmLFXz>r--C3`S7-RLcIri(ue&uA%W%5kTmCm18r`l$
zVMM#PrsYhJgMA_IIbbr3^*TxS?ipq!R(YhZl>1+YIYq4%&$@DDB&gV)z5myykWX2P
ze%Y0-G<Rn&&4D%UN+m@6Hx<GGWUa;1-SEBrzzLw*!Q|@EgPlwaz7tAkCM*|S-orG-
zyie)E9M?d7FT;$%v+c#qI{~uOOm7zGYG&adaQQ3aNpnmmY33i$bdg4Hhch11Ks(K-
zj!Wy(Q9Uh{9fQ06Qs2GczAZg*9>4^tOBW70_^(}Y81jbm{)SSEhW~-CTZ28258BWa
zioY}%j?S-a?11Aw#x@)-_%dTxK{tZw@eqA{%sh~)B+5#L&HcY25Q6Ra{wQ?Y@D)*Z
zs!T;UJO7Tai?Ry^Qj}e9g&>U7jbd5K?gQtcYd!YA$7`$SyPq&jy}}y7L~rIP2ENbp
zU*X3OOW(kczAa)gPW_s`z_EWd&2D}?OH-f`TYb<vzDWj9Q`sHRpF4Jd4D-*wBL73@
z*M^To^FJ32XmDUAg`#)P%%F21cV~8wg!@OCa(eF1GF~lETx0J30$~W_fpC>Fl&N<<
zjH&nj7E|wjI8*O`1XJIENQS&tMl<ytiD9TG7**I8`n7^FbDwV*iUvE$mqs_=!|fKs
zKEu^E*%%5%ySmmG$S!_!aqO`HQ8z`eEjOuyKkkJygS2!NhpY^RM<bu_0^7JkT4+t0
zHUMnD3^*nuQxb)>i5|R7Ms&t`s}J-bcCh!3M$u>OR2UyJIROphexmj3Fa79=+|G=m
z`M3i!6%j~<Bcof4+A$`{0FC2J=}~xgg1JSrg0qYX!BD&^OUx*I7#Titc-O5WoIf)U
zH@)IIW9)&pP$u>}d<$dZ62W4>#SElKz&+-|IrtsRbgDw9?=vH+(3fN;iyre7ro$`P
zO=W_o0AIj-rzJ!o<E;Z}5wr3)XjU;(D*&%%>~mnShS`|};V$X$#?ag?jkkcsS-STR
z2#-jazfc^N#@+(iF}u`{1HxD8@fvn7NK0wmd{O#!I)EY4MPAUkDRuJzK2#b_OU3)r
zz+cd{2h!Jc)t*RwC@_^KeK-}uEUB3;S+=y*48U`xTWjHAfz+!OwG!#$#u%<D>8vg2
z%XV3-<G?w|>_f%@u}`++8C3Vn{=_#}aZGktipJxz86BYNBOB|3+Id;-1{49ZMPFel
zP?ob4q<3W@E`UeNI$`o(e~Fu?{{&2{E+0^BT{;p2-6r7d|FsQofeDdfM9K@88Y!gW
zd`y!4D~crtx&M3PG~DKc{&(o)4c5+~4WZagT!QnSwJku{N1%X6zr+w=225WL$>61}
z&^jz)4aRBY<ZC$pi5-gLv{?}t)j2htz_!q<2^?RsXbE&yA6EjqZjA=5;mXvlO5Fbu
zN<|vfB9*6SgZ-ZJ4)rWvsqYL_lJejw05X)O$?zqSt-T7(k8F!UP;ub*s{uH~e_0OA
zV2yYe!f;JWFW5h%lT1VHux{kj|GW477<CU&WH61MqsU@@!v=vOo3Yo>$L%!}JrmMg
z=1e56^c$w|0gA)Ya~8ZeJfwFD;O$ZA@<w1hCY=_6;)K*N5xA4mw%y>uDJd($OE2jj
z0q&iV)-8t6TiTT-!RMsr<><JNbaEKHydkZAi6TVWXDaMHljhlz;YO15upC9QRI30@
ziuC0R0Mn$eDEO8xjhO(p7t$FNgvgYRpx9xSG%f;{Ia~TE6PmB2!zqaOTH3G@wKvj@
zmq3;$ZBAj*0_lH^V7^d#?>`8OrNLW3_Es9!6Fn=HI`*XXPnlGLa5wHr&J~Rgvd85p
zcF5k*2<?=4ZUugq?7Dy<*)5wvllhCXzq&(sNw$nGRg!FcHfqmhbNYcLMYe%KEmbxp
z8AZCRJuN~rWUVM}ktypj8O2MPVGoLI+3_Xx{>za~d<L3anb$Fl^BdW#%c$kc#;*gg
zKo*?^yG63a&Cu;)S?fLUsYGV-0C%Zu51D@_^QVYOxy;rSMTN{b5iB2M<CjCTQnrg$
zlb>XblTfRcjS?`TH8LOiDtwXckYoO@sFh86kN$p@d3Av5H<@M=dgvh6Cqvayp1&VL
zC;5y~FuzMa`XUTE%SU3TN3ln)JBnWHm4D7dZJ(T>_tydWO!`V6l%J~w?vUL3F^0rV
zo)!l4hvhTJK+{8hV>a53%I8c*VLv9{Oo54$@_rwo<0)T2!96ee?R<D~TAq!K6ot2Z
zRC73dRvw0%S#e(O<OVN%<;EQJ_oDnW1syNR=eq)MMeel;fU9y1b`%tT@;+Tb<}aT|
zfs_FG(ILPE%B_<j43-~hja%S`UH(J|yP<N<5#EH!S8W7axZD&9e1yEgDs($a{*?T_
zEsv))=w10VEFBcl@`54&?#YjLh8MB&K$?L)kQaW0Fizg>Jv8IxJ%0stg1pB_6p!Rf
z=R@VO-1-h=Pvs-VfaRIo-pm)?JeLQUVK-Smunav+m3zzpO`3dNKOi#Xf%F)@kk?RL
z`lURC;=Nh&gLgrbBcIa;#Vh$xT7kZi&(eS;Pku8R1`Fif|3X`#{1NVNMX|iWA_(8g
zV;e!GOzt`yhTh3n+t*@D-ebHlLKX6br(oivd}SxpD&;NSpsh--ega^%JmnhLKFba3
z(e_1t;WbF><VDxP_EkP37b@EoBWTg#pvWl$Zigak2L@rMV&_N*cPSQ}!cgv3q;`Vc
zJ&LB|fOAn)SnZ(Mrx?)#s{0kC9x!oG@uv=jt764A0NoUxJ5h62^eTYL5ygVV@bIW2
zvJLRZ6+37yenO!*2yRcsw%O1;rRW|94^Jz0JjMW@Q563Hm9vVTv~zM!@t(%_yuzD8
znZAm+c$)uQQsl0HrOS%lv|zoeczqwL*A%HrkoqeY(3<$Vq9r{XL5gn8VIo*Djy{$l
z3R5dwn45~54NwbH6ej_GOHnZsb|VxIP4F;MG4mh5Zz~Rm0)9s!&46Z_qRCCv(iIc1
zSg|WI73Y=$_)?+NL7J^lEJu-}`0)jVuN8k@0zOyaLYo44itAeVov+wKai>DXT>9n~
zDGr&?wq3cLN8zCCwi3b}%Jn{Qbf>a}7W})EdDFqUTRHX`RQ4zjy}=;3C<jggwSB*`
zgu-VBltC20I;2$5XU$D%OoJs4<&|kb98s22`0tqV@^{!huH29POT|g0*bFqDN(+tC
zQ{{itP<y8AcMO`zN)1hMQk0KQVi3}lP6Gf)S5AM5+6(2*H(<$BdaZ<JmR&jPXH>J5
z`5WNyE9L$UsJ&L+*@WVaa?$|!l&4%n;fw<1)|ntJR9^8wtysAz8Xmq?23-QKR2k*~
z%`)ZG$FTHXxre^N70TY}V5wA^3xNBitSyCRjq;Qqy!fnKXaS&3Y4^AZ_rEG%BkG{|
zuDnjcrtR#Wjwl@2K}~Uecd*S6{!sX_Ye?wN9{U0l0c=wTm<VKdy#iY>yDb$1e1qLG
z2?lSn!e`V%S$z}Oy~XP8!9qBDU;u=X>;P=KDWX_*8QSi!A$AHE++|PF)HR0Py#YG+
zSl@i~@IJe#9aJB%Q55ie$Zqz5-FWr`y-^ccBL$ltv5#iJ;1hPBfU$VW{!3quBsP=+
z0?*mjbnR2vW`j_qvaM+LpU$4HK`nz_t_L8Ky)(=XnwRW4n%QNuDs1X2a@b|-;M;5V
zzz*~<mzB1LFrQuh0JQ=(;t^<y*`$0Le6|PeJC?D}mqPfCwb9m21$#OMUVLD4d!YEl
z2Kj-yimjdxmCx*v!vK6?4^kxeE1PVU;`#f={^yJyZs#^(cU<AX71IP|2e-Hyp6=x0
zW8lm#Zdn?N-CSlL;P-G31UTcu{e2Fk`?wj=!0qSKwHU60TqW(9xpKif0e9o7?*ib?
z{hW-#gY$NRPe-`IFMvmLNq^DzFNVum1{d#h&4VC)z<E)~H=bKc;m8E;_ILE@5!X@+
zOOLsfRw$lwQ(Yl^#wCvi+jFiDtqPO5N6}zO<J@WgES>v{mH{ugi+dr=<jTBZKAZbF
z3%DF^{Ew*Ravf<JX@A2FB<_5!cS{;z&MyS`BF=LtxQn?OntYUS%RizsrCf0_RNirW
z7Xnz${YV2`!L9lk#Ro399o(+u*7U<zeBxS<gRq86Lw1GYGuL@54Ayex6ltvE!n%X(
zJD0H$#dbSC;TNbn^6QdO-NA3C`_hS*)8Oyor)HpV<~Jpx7kl{9qi|*~zilu~?Bh>1
zLT3)}H{Ah0$g3AY^AI2JjG7z&EEp^v{45s;kMMy7uzQS;3qkETzl2sHp8PZVdY|I$
zU40-u!}p~5f;YeG6>8`Bb9c~DAO1)Y{PyK{tiX_5;8#=V;u4?Q5Oy!~`&OX8SNT|)
zq+R2MF(~|bRWEQ~=U>oEGl-9z3NM2B37bJ3!k<^c;7xvn8~T#Ux20D~20zZ851ki$
zvJ7l5`IIuyWbp+HU^j>VZwuI7@xv(I`-ZQX31A+dnFX2xzStGGLjKw+a2N9(=xg|v
zpE4c7GJfzhsJ!DJJVdR6cST%Q@qu6Q5%5ZW8f|@i;tOfLQO(QV)BLlBH%>;^YWZzs
zzK%~m182VRBjQ2&onP=4cn4wQ1+X~^8K1ztQwVK>HYed7Z6)j$=GQ{SSy){LoQq(o
zg63Y~1dC$7@XKYW91yzDmYl0FmnL_I1iwRoy9*bbI6Qxch1O*7h|sDX5Jv@j91wxR
zxnmFp3DfC)bweophVcp!di@E1Lxm7mco8O)1;XEOq17({L<k;;Unrskl`mLs3y0SN
zepmSOA}mD<R+=Z=6ZT97AXaEI9GVY=3y9#`6>-9*Iye<C^xOy11i?NBwa3EiIv9K+
zB<=(vNzjtP=Rzy;B1LegJ(X0!X*4XQ3l`c2&k*X)!bGO<tT!}Y3Jw)e!7j~k)LseK
zvw_PMx=lmzMvzGX$QQ=ZOvYXyJfd%Ukzl8--(n%@5ok(;1#i(<Dh#KH={uqQCiJje
z=>Ip^DumscX!{`SqK|o{Q27OxJ_*qXVJm6`UpEw=g(7;d)(RR9mg)qjhS2;b6t)2M
zcVTr07;+GoSHrBMT^!yGIw!;fv_3g0uAw{Ol-Pd<biBm*X3(4wlg7adZ_y_e=Ff>8
zD*^Bk57B0ouehxliVNbyM5tU6Ck#RDvN)TT30K8jS~*=4H}k0Zi$yd+xGu_Q0vIUP
z>0l^GwBPTJ>J70eeSSm4y#BBoD!zM-{)UN%U*kH3ixp`oBE;Z_5Z)F$FNNkEF_hME
z(c*oI{>F$kcTl@8KF`C*JP>EZqxMj&Jqqf0aUf-fB#P57qxMKV5`)?ku@y~Po{CTG
z^jS#~b(BT$TnwgbpCa1Bfln3BH3lMGoN*1c4AEgIfSF=u2!Joe3AFE-El#0ubB-7l
z3EXSZs~W;wvEO;%@<iqo+|Cy>D3_p6{6I0iBGGw1;BUqCv};=;%IfGkeHAC(!azBx
zMr=gkrV5}rrn{==eRTA&Dr7#)d#Ji;(X}J0e|o^+QB~Unv>j7@ehI*FRqGiraZ)v$
zmc5>;!R_J2DOEJR*t}E|X%T!{HG-TuqiVJSIB(VTHmIFdh33e+NfhT*pG<TqRTVVd
zzohb`9rnwrTMIywsPeNw_(&D75NwZCQ{C@&HQBpTicgYi)>g1QR~hJYkgWQ<3yKug
zswXH?RSY&_6ltoYZE*gTN>1CcuT{f;z_XmETJjm4E>aC22w#d-UHd@zR@E+^MnqLT
z8m^S83QACvspfh8|FFtj+Hq*PtO<JG%KlFSc-VTtQ*^h@l4|(ZwlR{^6z$gjiRSh(
zbc1wg{{nm++f%H+lZ<vqJG;_is!Lu0uwA`rG`rdU!m)e*e$ekBp}0-Y&2Pck>mWJN
z+hrk8eLQzT|A)buFyD857o7LIHZT)K|0Y48`_UqU_XC=?LpKMe&@RfL5fm0362;;;
z^eWwY!}@-N=J4?p(;v~+UEAGiKRpcw{%OsF$B|h%36}RW%ccWyf=T}!%BPw0d*PH1
z^YsdZmzbAyf&7>cvj2+&yRd;-P}|G)L7JLkA6rG)Mf=$rnk*b(L+R6YkZqTSHdpqK
zCFs&2)=m*MH})RQHSF%}i4ZUzW~(TU;K2^?h4cu!ybV;3vU3=CdW`izBAwzSTR9q}
zo~+jpw4G)r(G=|r+olr=Z`Klw9-n2K9st>Swt`+7zU<6IxORc<{R(Xt+1o47c8T3b
z+gg{|;q&3e6+4^12X?QrPdbA18ar2q!jCPbO&5Q5Eo~TFXZ;)@3}7u3-wR}~?m`j7
zHf{hD!R*xLC~mOw1dL7yJCSA*H`zp5zl5?K=<^fCUi*gP78`pT&V;j9pTge=HZBrA
zMY8sv)6p2kzAyrDn;lvTX*8Qck53Fcwkw49*t0Zgk7Zx{4B>rt_E?yBz&^MOx8vA8
zJu$Km*@7hC64>`UU?P$A|KE&wwhpz&Y}^RIpRm1(fP2cGN4})u89Q?~+LG9V_J$}^
z*j_}M%8vO8(loYv0E%?>!cS1mU?aMtc)?Em3zjn3x3mNQlAYcNq*?47GM~*RHvmfx
z>--;v^cDMJKAd^YjvEb@T-KMa{TudBC0O#<o_=V{XSZ)e&kERc?d`Bz$Ts~4szoeE
zc8giB&lt<MY)9mqDoR)rZTyw8P3NGkjJ?qowRdb@EzFm*Vg4xIvtz43TEUK?5d8<%
zV=%n<$OaFFqm`^Y5V%il?>rc+V$&!Wu$r~Egvu8-vWS9Cwd{Yd(D;q5h=S^O_Fvj}
z-_G6Eq2|EJTEcxN&Oj!1b3VuhRycDNt<dJeZCe7Gz1*8_P}#@rNJZOzE<YK?0qzS8
z$w97^#npD@9{vYM4{^1((B{Uqr*EM<*RN25kN#nfqg%*>JG%;ON4ZfHV>re+7om2X
z`==O|yty~dD9&=-g8@9px&I1)4;T9$19YBqpm(1y_jCpfUf{MhfaXQ6b^<-E+~PZE
zyUY!y(AO32aTOfB%6+GK%r(xDGO6r-+(*iw@aIlW0{%J|OVRcKE`17wf!u{m0E4)4
z3bF=sPM1M?gEP}|GlUyXX;C-1uVX<P$|d(jEsX2&5aw@j0TksA=RT~1FoIk61K^R|
z#}Bw7QQX%;u-xWOQTXtVo$FhU>Rqk_y@#T?%+KJC;o=UU@g5hw0nXg#HqQj<1Mbsm
zu*Gqu$ShSn<Q`yW4U3aa^s-Fgs`Ow<<Z73pc*Je#4TF!lrsUxhZVP1@KIIm6MDdJU
zyAXzwI0xEce$Ls)>!6d&{V@xqDcpx1C{j6r-V|xvO`7wkbGs=aCxhGVhf9fd%uN6?
zIhR8azT|T0Qf6^uXeFJ^H9rqWbGX?Sn199fi$Q;1bAFVUk;`?akjxvdnt~a5+}#t<
z%;&n<DIcnU>rL~SLT&@a+KRXZQ=wYSElY(nZ@FQgV5x-rL^}Yb++<o7lyTeN;TCwu
z{X!#K&b_sQ^gVZkCL0ypL}W5!85FV|oFBOw4LVxM4PFS%Ph23qAsl%<rC=Q8--p|w
zdV*is83s@CvuSh8lb_rR#VNj!-g933peg9uY5rsVSDRNJ0N$IA_6FcAf0g#X&ha<s
z^XJ1ar^VcPzF-XsU!L2H;sS5F2>3<5Ej^8w_;&PmzsyHohig}Ob%}uI&yT;H3LSrb
z7421C=Z!S&4B%(bEg#5xwu0Y5yk|6O!F)btzuw?$Xc8L2n`ndRCcm1V?NI(?IfP-n
z6O!{4xA^FGXbb11bSFgck7?!-$;bW+pQ8B7Q7CTn3Y#FArMSa4-T>9RyaP?>qxp8J
zP>tcER-w4Z?^d9{v3v{qFyH6LG>7m3|C}c6aeQz!a1VK(sZfdM8y4ceNZ>2zZJWqj
zce}6cYqSRy!L_Hn<T-qL#y1>>YnQ|ib_3aSKHwJM$^0b>IHd4PX@@nHpFxqcH2&g9
zu%z=FC`~DY4?hO#7yR!1V9De!QF`V}e$Y8|B8y)^J<I01(7YmtKUWLQSA4@YsJ-Ur
z+Y>O9dHnRHV9Vz_(~F{juc4S?Aumz~i})rFKvT@0rJ2)PJ~sux5`GSaHcELt2bD5j
zPa7NW_~x_0UCujEp4)qVmK7=${DpXQ=>wnf8n}<V1LX`=@@-|nec~_Z>Fr*{UpWG4
zH9z7<AZqw4TT%PWx1Nnr`@;7e1l3x8B88mm_^N*}Bwu;^d$4`uJ0VdAtG;1NVSc-C
zn-+Ku!T?`zItp7NAlxC0r3Ls-AtWA}PJ)SMBD;i>l$E+$aKFmn?s67>3qiN{2=4D-
z*F{JW!M#^FNjWV0gx+T`7W;)OK@c7g?39ObP?$@BJ6GW|Z7CcQa%+Ke6PoUZrn`U~
z3R)kI4S=Pi!us22J0=8EK=-)N8++P{6T;VxaOR}&0-Sb*r*Nb*x^_xn{ZV)cZuF%)
zEv#FF;XWe-t_R**_`wOavqFzdm^dd4T?jTG;kyyVdBLy*-S!m*j)dI{LVL>Wz9_g;
zj>RQm!4Y_PS$Ig3^ee)ezu@*&Ve?eft_hB9!D;ss5|2abFRXO{@VelF-@GUSgk&U3
zVO`sq)+j;3P@2~S3u*(*-w^&?3J*hsMzeswDIBG6bf{23Yq>CCI3=jx5?UOFFkFzG
z1ZRYBF$cIvVQxBvQNphK(7Y|QqI}Uic3}_}wpjaq*a6aLVKc4XVuZ8lpt&cErLDDC
z;Spu$-4}fP;L`&k_8W>gVeuol_E6|^6}5Pw;}n=k5L%yxiO0eOx&xmGmUn1-Djf60
z7(Nqf>0OW{v|kI&=Ypy=3?&Qp5wy>dBJ81@<y3)kj}&PFvWM_+2`+;H%n<mw5WWzO
zR-?!ircMOSOCg;03$lbDiUef~cWThl96{L#=3fa-eW3DMXzYQuT;U^i^o^iBh)(1Q
zp|qo$FI2xocMF6q_AXE@6nqW=UnER>1f61G(FioY6^_TFRwAr80+mu>%q8@xOgPmT
ze!mmy+)yhQ_EPa)7@rGAD}+I>!SX@)xh1^#D0ChG%}U|PZxDVGbmPEMB_t1k`D!7a
z_JL{yw`6+$J_}Xnf%qa!S^)%ZW&;p)!qGzzeibgzCd4;k|1$LcyU^%&jLdfNI+<_~
z7g1iTqo||>;tmm;DR|Vx6<@*aB=)DE_%1Oc4|aEpEecR`7H`G@ut&U4+h6;{-aF-Z
z{`QNe&8Qv_?@_SpkQhQMe>X9WmUQmoRf?D&5f`~b<)}D$I{ZB*-l8jdQvBE-+@4~?
zmncq&GeS|E5ns}*-CG=a0tU~D2}dzN=f%@GsQHTR27>H@$aI9Gm&FPPIi9~OqVH$0
zT@_tu=66l}i{fa0Vqgof`HLfH(QsW1eg<a(L^WNJK=J++&;*Hh1ECo#=EQ>ShM0H~
zMTnT>53-wL&I-UoMVC7Ogo*3pP}~y#r3W@#Y~K=`5#m(JSh7co0k6=tDA8OBzi*4G
zKG3-%?pTjo;I8;)3{<1V^XJhPBgRsg=$@#cB)(Yj&m+L!7mtR+iw9z1Ka5PASQ!n#
zLotDVVh}GTP#7*j9KQ{?MA4!L;E@<n3+l&WW8~#2p77#QdYqn${oMwe?4#`9N)@Z_
zK`~7ny&14{F@pAlGsMM|R{27_NGq01apTWWc`4@7@+V8Q_@eLGVkm8V=7{|)XnQ4k
z(*5^ZY^+3Et{CSE|K5oED0G=8{xS!+eDT3f01CvD82}WDN%jt~R3sjyth{2;`2rAc
z#WpYDMTr>D1#P8be}9mci3g+rz7q?d16VG~Xyx!;Tu-@172+D2h<^}s>EroPEbR`1
zm7<X%nV-a+G>fVdJ>0=rEq1$rwi>a~5OnFYcp`wNI$uN;IaMnrV8d5YCnjA(<5zK3
z7HZ$b5*qsNVs;5?+f@@Pfp<{N-wc4G%7X$8PO9`~FtJPZxIcuuRS)U1IICPe0NA6N
z`3{b{sN~b3vRCzpcH;J_j!<^hewAr2<+mSDy);4Rpz6X*IOD4Nos#+vsXA_gT{qQd
ziYmFQdb<O0Smn_QH4oKw`luXHWzny4j;iL;=Gie-ZC}_uu38)gmJ_OFw4rcP<=Phj
zPgQ&~^!}7;C{3@uR8Q$PI<1QIkl<lBqjGEj^WLh2g&4%Ms?-(GIj35G7D6A@!V&P|
zylOEe7x=2ODFk^z)vy+A7gdW-LU>8Fay2YnRyF<!UAv;n%mLu4Dx0?VuBndDI?Ye@
z^&wRJRZhF%+I3Y`53mHNb~wS1Jx~=m1>OXyR#AXHSaqx?NN=iqXG1kqHF!8k!&HHv
zL3&G79*rVgm8OA8gzD%i&_t>NT4F4sR9<0VyRBLu4&fb@3uV~eRn0E~XSC|!VR#Xv
z>J$${_f$E50v@aC<qyDpyGs2d$_FafQ9#70^2^ZpP?b#6sd!b~Ncf$g>Pze4L{$t$
zP9CZLUJ1>|s^y(w>4~Zn?dd*Mb$AJtXDV$!40n=hHD#(lSMeBNM4mEU!;2J^&=Q)d
zDyO$-OH;L_&t1C8K7APsW~fF+K<9<3wj4T{syVArWUIQ|fZsVPX)Cn7QWbgu@kaIB
z4)b}c<2})quS%sCS&^zJ7Q$kcOCoS@RnGJ+D^r!b!~1ut26e!d<L*K~Kd7ev2YVk?
z*V3U`soG_yJ(^Fd*7TaHQmr<kR;_YNfs0>MzjeeQ)T*poK~tylp$wR>s;yR7`lgyd
z6R+>8DU{Q@U44auyAJ9$NvJuh=hL&jL*1?fc6X|O8wj|QT7MOQUFrauEbLY%((B1t
zJ-dw^7jKXH6|Jsa)Ny^#xL3WA^2YY5edzZD`_-xzU^}2Tjt2gq`ubXEx~gaU!qG$O
zb(DeRrhZE=19$a;-=K0>J#Zfi5A|&N+1U~Gn=61HRj0l{?U*`b5sKsLwq~fDQ2+gq
z$MbhmeKH?9p6Zdmpg5(TUI4pZYTasZpH}<Qm*$N6Jv}+zYByTTomG#e{g-oU$G=hY
zQO~43rSs}Gzk}OXy{|Vsyr3?p9Jq_>4UJG-QZHBq_+@qXN@!kDFP#nHRdsV*3cKQ(
zT1g*hKlNS-3V(G51K$GGf)&mLseh!GZm>F)0@gRxdfKxHRsTvpg{em|7`$8RCA3-$
zS0As0W`sJR5ZsY!W(6!osh`poz-{&Q78syAYUUz5ysQ3A0YlO11{2}EJx1+GIlcGP
zS@a5zRad8=+xOLf-v{u4y4yq)acTwKUJuoUZ-9tbhf!=fL48&PX`;Ht5?Feq&ZFI&
z$7&bKBYdLnwhNY?ss)NIJX5<4hfhiBiV*-jS6e5dNLF92Mq7$qtqp)`s=6=jgQls6
z-v&*(nxV1GR8J2D_e=E(y05a-1++nytsea|ggNRB$c$IKQfFnMc%#<Q%OFpEzdkOj
z9!NojcWPA##;IJrg@o_b>*+IAq4vSvlH!B<P%=0_s_k7U&!keVr2WWG>R(y|QKeo_
z@#kvwqO<U#Ms4Z{;AeG1inDxCpW2UFtvZ|*Rdwnzq^2sqs+TN9@l8Fo25sNf?(_?p
z?HXr#>p5tA-C)U4vxGLpcW7o&;B==(MK3)kO=mkrPj+dzgD7@uOquAKv*v0ixW7l^
zk_#_fG^V={?$h|wf@{BK<<B5Jpb2gX;X%#rzo6o(xl9lIA<fo#XmiuZ{y~@AH66FX
znZugl+u@9dW-o;pj%W`50^Cu}xV5l%O!H~29T(xaX3i~0PiR_v2I8bf+YdCJn#I|u
zozk?U$-bAyM+4H+n)Q@}bw=}?eiP!YdHf@4XEj&fg6*6pgnonNqe-I4+<DD`UjXpc
z$TC2ENwc34H7{$DuA>uIG@Z=AUDX_KMT@a(n$c5%_tPAw_p85V#0wPHHL*0U3D9Vw
z(6vC#$#L)^NaHmDwO~!dkuY&X)7AiCh(=0ZyqlU|7K1cY(}yyR!ZgP=!<k!}trQ{%
z*EktqH$t=i8sL$d4Em-<X)YnwWmnwROnU~lJDR^JC~;SFmxAum8t*E&AEVjz5w&|7
z-#0K3t6Av^{C&-OS~Wh<4C{pFFHSRM5ZWGUp2eYu@frzzT@o~>=sr%=v|0n<BTZw<
z$$YF??*+~$nxhlo=u=HM3w*La)5Jc2YLezL<&r+vcua*fS(9}Z!W7Lh%1BAo+)W2C
zP1CIyZ0VZ2lvVIT6LAk-WNP+MzSK*Nf;IxPG})B(o2?m088kVX2}>b-rFlXz-`AQO
zlpva`c}Pq4HyRt+%d>0FAbneruZgF%Z=uHi8LCB^qOs5^*1TH*#9PhDey~)c>DLp8
zQjI@FBg!;eo5RvOO_POaE7!E@5BPhHigMN~G`nbIK4?x2L+z7B=?Kj#&0KnkRBN(3
zqOC>~8wInUHTD&*D8Fb<QO;Ve=IvkbyH0cHZ}|OH6Mq_{-!!>P(EIP2PC+QPYfH=!
z?$9!S0Jl>+nC6d8+S4|;y-WLLI1KLA*0q86&f0~v0l7!}tOz(4?XCk5?$x&Z87lj<
z4iY%CU+ZQsh0X!(8wKnh()uMp$4#4*j+(o6;yU<rSi4Dy{(5Mghod;66;dHQs+E6&
z$}w&6et2<Q8}bUp32i%iv7Xd^rYMM~b{PdFPHCS#fI%;9#W%QpTAN2H8E3S8y<yf{
z>)4ULe`mEHY29^B+lMAEKHA=Nx187Br!cy&_Siaf?Si%=Ww%|_7CnLRk~Z;AXkOML
zj|z{I_6rTrRc)8K=+iZAbskjwv}5S@^4H$_5w+`D-&?Q{pf%C*DNws>2-<?QTTfD`
zJ6QXc-g-B*PiY<)qV=a-$eY?xbbo|u|9S)SVcG;Q(A?7IZ-#5(|MMwIE1!n8+uHPw
z5Z=-DzXS7kwH}no8Lj<;rh_qB6D5w{)7BgVb*#4aW{lH)?ZsbUAx=BMmA-!uwfj0?
zNaM9X(91JHd%FU)MD3(!06x-=*#*@n+AYgad#W9E1%vQRn?U>2N!r#!!S-Bxk-{Iz
z+I5tUlct^f4UVR3ooB;~4DAa_>U*K>FbRN6?F?^dzSOQChvCZ78tC`d_H6B-WhisB
zQ%=C{EA1bv;OT4aZQ2>j)k+0ipEuf-M&R?bA84VLuiZWtng!YiL2#x}tEcx=k+$w3
z+KRP9>7D&nyNxbki8hdhN~!kAFgR1D9U?&ZPW$x~YUNr5{a)$4UHjKyAS$%~e1}t2
z+7<obOtm&n3Y{A5@y`%`)=r@T`l1c%g8{15KKFrZb=s%*(6z7HTNLj3rd_-M+~2j1
z1lX<{9|gM(y0b0O=BS%dgSH*IC-ke_ojTWI2zTrLrnRfH&i;2C5PNjYY7{QIy)-M`
zt2^2Oh<&;TG^N<D^XZHsJ)pZwL5YJpFZvj}=~~T)Gw!-5PY4g|WRxuGq4T#vctqz)
z@$aL$&ON|+OsAO-mE*d8S0Oy1`)waMPwFN<M4P8B(@u#rr*s=XgY=B9ilPeMIv*{B
zXLW-TfH<d1{e+s2PI(8#dENG3;Eb>C+<AC-K^I5ii;FrZ{5cK9CEd<`@Zz%W8YNp_
z(Y2ztfS>ND8V3D!C%&Qg*LCS0un?eI;sljIU1UF6{RZitw#JYK>->sQ+|Whrhr=N{
zTNzYu>RQpPB~;h395i9NDKTifrMom5MYt~A24RHmpM&t}wyp#1)7{Z+xQ7A0tE-}D
zdbBQUC2BFcO<iFAo-WcEc4KwzoI!nGcPx;ezX!UhG)autjiq%_f^Hk_^(5+6(xdiB
z_lpX^$GTHAnSP@C^Z;y6b<b%R?3wQIVc1R5MbV1<xo%-4;K{n0A>dBY9e<A^T^BnS
zfDGLa5|F*nRnvZErp~)J;4gKXeChei(rIY>En62?Kd;jD8-YH((kbXir>}LdY0D^A
zhZG?^2fFF>`^y5ImY&~2UGZn&igcxQ02J%`PC(mR-R4`smFRXfKu1e;|4@2MneIEi
z8s6z{4Mso9bt+1Mey=mn1E;-0_hBGtKIryzfWsek&3wUKsmq}0Rkf~a0faTWCbW+G
ztP^*^(ife70`RrEHe(>H(|x9C%2(Zce9RT!bTXO(eb=Q1qvoj3c?R=4^j+MbvQu9&
z2yIUKA@qgbrI*qwf45!V_#q5B>z4=^y*>KMpP=KSccZDyUVQ<@N%!f~Dj?jij~RlR
ztA65mkRH;<1;Bkb{bZVmx$EaP1>ms$(KOig&^Ortz!CjX+EPEN*HN(en7&Ga;<$b$
z-MJ_9UNjRrskd)>4;?Rk1Nvp#X?@d%@ZyZVh~h8a`Z0BAJFB;g7}<0BA+!hKqklo;
zd|p40o)KUD%myI6pm(ILh>Q9;gYW=c()TNe@Tz|32MDj}&0Qe$)4R~e#b4i)-dfl7
zALxS_pbxOqCVHTL(;~11>9@GTsbKvKN~OH1A9@aLq53!q>V)Yfr-8VoUm^ufxIQo&
z!U+ADDzHWBo6uHMlzs-yIB)9*o1u9}pGpZWclBGFLnT@tUcc(r?{`DneZ8R}e0reo
zG1?Aboc@olF!)ga){Y`x|2h>q3Hp`O08G>uw1I1n^v`C&;A8!ZU(u&0`Wnh#f2#MV
z_r-Jlw*=IZ^=Yp#vMKrnonSXrKV%AOY5H!I2bZp2Px12%eF_DsU+CX^f-F-%?jVcj
z@1?$cF9ttLKjsK%vh~grVdAx3r-L)O`nqetztJ<a4$ISb^#L$nUq|_D1$vVWfI@vF
zz50vvO3KP9*3ahAR;oX}4&zj&|B04y@AQjkl2)$wm<pBm`pe;{Rp=dOP=413eWO+w
zwvYOE!9Y~%m(xo1lm2=;&{XML%3;1*KOqs8zUW(1;Jj8p)(In1r_c8U?yG*fBig>{
z)ik^NuGh9lU$z@ODLu@=(31k3j)oa@U3VBf=r=Dr4X%{?;$&D#a~Jy_!>2!hcQLf0
zXxm;xOIo1sGsIyVOtIh4>;y;;7$U7uIb>KykpMRXN3#`o!=@$BJZ#9JAAWck4$zzJ
zhylAsxaAE~egoMtLm&E+5yuUedI5gIFl0CEo;1vAgyHfubfX97l-+=>Z#)2ov-CDN
zZCD+P+8M*)GSGM%T73cOSwkIl?VMrLWFUMD6ThN%-r!B&6JNtLnkrr}toe@OqJg0t
ziA#n{xxigEv`PZ!6~i@(#$PqGrOl6PhK@^s^E0Tk0Pr{1)96vXZphsL-vSITDYzbJ
z_)v`^$Z+`&;DZfkCu1yb7-Hx$g&11@4!}*ry>j#^)G%cg+QJO6PvG_~L+K@SJKS)}
z6-9)>L`$YfLpxe)MHv=!1leuFTFNlIV`%&xwY!EN?0aA-+TgSeIxz+lZL!@mtPemh
zVhyjyL3rQrcn`QA7*bZF7H4RG1l$h|%bNoqZ+LM8fCNJY3ojB4KhnG8k>Oc6#_6%)
z^KW2zVh{si;i;kO3INXx*%S{<GDM66%X7o19d<M(8`gG(i4;R2{n4OQgX2{I(+uxM
zp)K9e*&DzN!w~vg6)y}o=p~eC=(+-SUm8x*Um(abbfPSQY{QR~2cBc_r=PvPGE6Rk
zGp`Mv)1i`Uh~WT#V|e>FiabNbCvfH)X7r={<^scigeWw~D7ECRVI!rgml#^nFHK4f
z*5>f3%;0?v-0uwcMxm|T5QxlV#d|~3FKDYUT%;h>2SY4PH9s0c=7Ox!kVkHRGDs?5
zu*$HKhP&EOdjmez7=EKX@XrRrN_zgj7#>G}t=7<jzT$O;Ao{Z`Uk&YPYvG$A{Ri0n
zZiuM=wWINn2^Y`7_!~vb9F4b^0=L81uMNgxr!n9da8AZSG#%V!Jlz3pyN!$b1K@0&
zX#?3FV<UPqxfoxy1AMRX*OBnTzR&101*-dvA(UKkz}TAdRSp`>eW2=UoJpg8$T(#*
zdgx|Mc1GcDESd-5VPi2(Q#_3FGQf`*qlomVaX!7?j~RPih48p>IW6i=7&}nn_(@~i
zX7JF{IF4R0r;OWa1IWv697;)Pr;Y3Y7(8P%(Tm30nEEdeXN{9iqIS+GQh$An2{g+(
zZ!{jpIQtrhhM{)B`1=afE*fhnUVF*dZZnF@Mh*QU=Zdki4koS|pU6?WW(=YfD?el7
zL>TfnR?}~2t{d&EzJeyexN0Fh4K$vPg~1?W+l?5DVB>&>z~3-7z^|4SA;!h;fxl@S
zkO>o^#w~qO3o}-y;`-b&I!M71ZtOw7uZu8lHG(D5*uM{OQO0Gh!E)OuZvwk_jK1Fh
zh%u_@&b?>+Xs7T*tWiD=2Jag!#Q;7q{;(W~IOBTym_IZ&ErP*#<NArfCm8#jfZar6
z8pT#08Gkzq6OWCi86bUPOn8ghQ)8$CU3+G{Mn6wTGR_@`+H+%n3U?(N57FI~V)Ue!
zUaGOAF9mbcjO`qtlWx4b2|5|ZXdl#G7#EL&YnjHL1@Pjfv5h-wS;k2@@H^Xh<s<yf
zG2WVk+ACwnGw}Ddal{{}<r+IuQ09%X^=y#k8U6HV%QyC=-z*duo#+)@X!Pw2&LU%j
zLlplkHrCRb_N}qn0l*TY#DuPu8r7=-EHlmy1n`~l=U!kdH+KF8FWwss8&In-Ht7P*
z4@S!rbo-;R-(#>;8krqv`(&I@hN8+?8v<dqF>@?5YmCQ-p!jUONlWoB#_VMRp1)dS
zOPbQx8ApY|{jbKE3!wAO_>OL`@5cEpz`fmMtwG^nnmr7c!qMa-hZj3cuPM=Mrztxg
zI49FkH>m6~9ZrPGZc{9e!FM*51j76tQ}rZpx|qJqhRR;kc@h2GXNsU75Zd>f=1~a!
zfGL??x(7|WW}<L4J*9czAyXM;bGVtj-Js%bYV;r24x4(=c8`ZC#u+L{OjX-3PDf3{
zXuf^S^kX12kDKmC!-S{FpWcC|Oxu>B&C66qchG5*JR7w$CQS!i18=*jtOC-rCbt@J
zpEHGegWJcn+y!2oH%;pWZeLTC3%s~sT1*j$i>8hJVfT_r6$#vB(;CXmzhXL0J2O{J
z?P#TW&2*LmO@1b>7&U)W|F%%MZu&;w<N%Wobvw}Hvl$kGO!k8m;SDzV&`kG+X>%43
zA*O{vaOS3|hDIjT^ivXwFw<a4Ke=V<PJ0C5ru9kyB23MOpretdRwGeFna)}vylwjX
z5j5|ZUQmSgu4%gwMYPF24Q(-|)Aab?Gd1gpTC9n&(;Mo($$_@V9+>{?2Gux|o&NU6
zL(^#rp~suHQamETwC+6mlxR9bzm<Aq%B9`e$ELd{VfTqCehXNhn(p2~@ys;S2e>5D
z^GM*Hn<i3HRI(|5JbIR5dO~leR8u1nUZj~e_N4erx(SO0Jb0!|TCTq^87VIz(^Ogu
z;Y-s-3QlI3Mkjzf+oXL4*K$lzG_!wY`gJVKzc%%w{jgk<B?HA9)86ZFG|$v%1We?c
zVpc-4z{C!v2hSAv8WxI7DF(C^n-cfY`tPmDohB$Hrf~Y9OR34Z1w1V?1<V2BooPl_
zsFs_~2jQl9Z<_W6+!dzf9iaKa^e^4=Ri-)X0jM?&n*mETrZ~z7_-smeg|;uIHMB)o
zYufYxWOb&&l(P5Lbb2Og-%QQh)8DuHZhB5%+U@3813Kzp9ukb2qj?KW!grYe%s_3Y
zxqudaPUe3pHnYq8Ap-c_=IOLU>1@uQi*D~R2ev}tVpdYp@LqG!GdQ}>{BjN)-EWSe
zzbACSTp&Sl(0qYj>#pW$<c$50+3hz}-OLB+v*d1GPNB5J=JlRv^e_iDgBM54gFk@u
zsM)6$_+w_pU$AuC>~;W}C(PC}sGT(bMR&KSxrCmPQ|27{sCk($yobtZvwtN<=8T!6
zKQ!WP4lV`RS+nspJUnMN*S&xVAM;##cb_+>IH2ZhUiAg47t9-;LU_@<lG4U5nJ;#L
zrORfAG>~2~52H=8tL8hugXWrfAI%E=%oBJ3{LSy^N?tefqhL3{>~<gUKy&l4up4CF
zy#&Hwb4U}Y+%VfqC`J=vZccNFo917ifGyN~Wejw}%sZC>c+2c^5k7^RAJfnLBh1zx
z0f;oOaRENc{D~sGx6N6p0NgRp{1dL-H7{^OTeNvc1^_YU@qVb?Gq;)#mRR#cimu-`
zAEd172j-o2N9e?vizzVv(ELX_u0gzc^d)$aU^a{bFwyLm4a6gJ&LVI>Hm|2;)f02S
zjp*o8^I)24J~R8Sg)qrHp5jH%&HL#m2+8I-ls1-PKG6eh>E`WGFqB~)OMk2Jg?ViY
z_?v0|O=Ab*r8#IX%x9TPHb9zf?m!ER9CIz*SFg-BY0385>_}N_x#r`?;L{uPXo}9~
znH`q_mv6Ssf~5kp&sN|H&F`P0t;pO$3+iHX;qPdBYyPnvs7uUg@lYu>_X-29%>3`)
zl#KGu978FN<>nFTK)g5qO@E27!n}rd{63f$(#rayxk-2QqS9Ql2sEF}8z?8B${d;k
zXR6JOAHl;K^LE+?_-r104n6#0PEJ6r)|^Jc*gA8a3xr?I;dEDjGqco*@8(rlLf94C
zEvx#V>R`F`Gy3ajdE*CzJ1px*!r)HJ?-U7evUH-qR<g^&b%&+h78mM;v&EwqNcUJ~
zP+Gc+r6uk2?6r)H0brk{5hY>nxAYE#<^juA`k~4}OQ}CpTrJnS!@?m;82t#_?q<11
zThH#6?*BsPu!W&OgoovA4unT6f4&3vQA>F;%pbEf4?yj>#fjFtCoBP-QJl0~4TL36
z%kovgowBT;*Q}Stcng+JTOwPbIAe)@0=T!Oh?WUwEoJcloU?T51uuN;mXRIN?emu9
zJal|5x*uTTf~8L@^x~pr0B!SLvV;Y}nah?5?V)+aGHfquS1p=RP`PG_z5`M}%N1ht
zw`^Sqz;#QjQ_u{sF!@jkv^1x`iV|e`ITFHPi~MK!bi?u{6o3$m{aj->eA5zzShV7n
zrD#8jaLavK;YL{EB`6{-sq{*Uvivd%#cj*awD7xQ`Q95|+_g-n^?9^qJZ*x;Sau#o
zanIsngBP(DC1ohzw**q4=z%3B7q~b}qaUF1&@!+cYVnp4cKlr~MS|rV1>F)YcUPhI
z$a3xkbRJtOr6`_QW>Mt-spXItTzh7Deh<PVOEN`Vo?8Y@$EYV;-dsRiie(ig8Kznm
zH-So;WvK+Xbju_9<x+;_>m4}r!t#>VVVRaj=V9oj<?vm4`(#<V(XTDCE%O$mGdUL9
zcj&ybTwRUvdTsG?fA?o2dsq4^GX<7>nhO_Ny6k{Pk)?|RIEyV^PNDYJ(ukIgC6<E}
zq${-y9fqRJvW{{K-&yw3FTu+#zfxMpdrQ0(xC+buIsiUc%9>*+K3W#jBCyhO;S1V6
zS-#VjRh8u{{XK|k%RhGdWYk#FDRK9+C665ZVzJXNLTfF88D7^}YH64Dt0jw~UEeHS
z9zx~2Wj<~1Y_}fYhc*Z6KP$oQXnkNnvBP?!KZ>1Ja~rfdS@UTovCHao7=Yc@dGs4y
zXKS7mEPJdue^Ow|#p)Rghxb~$^hB}G8nqF?{Z_*+6bGzBY2|a!+MEHx)%uo_T@P71
z&`yw>wH?jT+^w0k`aEnsMW193>&Vs+9<eqvp?1{TsWU7bvyPy|&g0fgiLl^leVPQa
zQ`Yq6v`qH0I#Yt#X{&1o6lbhWQo!bI-Ay5bv)0~}P;t)cMETJ^))w?SKX2X835Boq
zU>ayHSfl9oOc$*q=trlQtcjEld)XREd2v^)|CYeuRqOAxp>xeTKN5wXwKeSn`&(xx
zOYoYyZv9~dXacOR^h2>g>r#5523gnKhQq<u9ziH>SZCz`5n|oY7T4gW)uM)_Q0qBb
zorGD>(JbYbbubp)ig4=)+O3JO_B;WVNUNUqXQHgr9;0^Kx{7{Fb;sJC^0Mz*FaL#_
zJ=!X{j?Tnbox%aUXI)1xuUP8@4|My!wb?A#ePHG3Ph`Ydw+5j0(7Jgu*y63D?g5uz
z4WrDOL~Dm+;2v2WD7OFD`os&|PpqB)gyvK0T-y14X1z^62v4&1qYcXE*4B$)A=z$~
zQGRKP^<Xg&sn*whpp#~8NMWCJt7|q4W>}M(p?F~}>Ip=qHH$I^Us|ue0U*mdHxKY^
z>$s;dpJR1ghuSOa<_4&}w$7{pS*~>;r9Hl}Zl;98JnMCOKjmA?GtgFGwg0*dWubLx
z9vX|R^Jqa(Z0$A+h__bL02C!w`)iPvTD#B!x6JyA@&MmihrWk1<<@Ctz~5WD(%w&n
zb&~`tAFPL_!{3kAVKjxWw63G5{3q*oJx0CCx^FNnR9nmGkMh)5bM33q_}N;EiL&C0
zHDx&vwbscxkbblFJAvAFtD_qXZnuqT3KI@C_e$U$ZD%OoZHH|VMNxLz5Y5A*W-Fxo
zVwbIPLvZf4`LBl1*;e%@YI|(aHvn+4g``4duT5)#`F*w}S_)I`w>{|sodY&!ia{N;
zHQxjit~MW}bSe(n0$gCi&4w&+JZiRUH1{}c>-q*Y4_i59wI8ub`hw-C?GM@#IcA$q
zGt}cYE6sXO*uuM@+b3<!=zZ#Go74`Rr)-_*OXX#2)}8(g#%WuNhG;xvyF3v<Z=2I2
z(44g$G=Te@tuy6#`PhC4L2=&pM^~u$+B(Mpf5BEZ0mVhzKa^8;$u^=NT)S**eG<4U
zHh+3+U9~M8gtluoIW4OEY}08%?r$5=06tx}O+)6aT@hg0avZ=wn_D2HLAFLo7^q-d
zKo59v!)CgIwh&w7KfvF#r5r>@Lv6l+APuv{cR}rzEq*I%;WqbV6cM&QJ5fa1T2azn
zl&yf)47Y7lD0}UWZSfx{?%D>>4<e#%tKPyxdyH+mJ51cOZ5)BdSX<p;^zgn-9}M#k
zY?-5BH_leL2{aFF;VN*)+vYunFu@kn1Vy4PDF|$jY#lm*?XhhFO_`q9rhP`+Q`=dJ
zoIkU5Y>c)f+w$fx^xQW5Cfbs1zup8c#eM5vt?lV|pq6PnPrsgeX`3Ad?JQgCGqCx}
zcDVq;*S4(_fX%hF@<7`g+Xjkh<=KX4FaY_sdF`QDVEdh3PKCC_hX54W&eQj>*yi07
zm*}l+m>RVbTl{+1EVX%FMp0%9K8!xTv$e2q0b99kJpIb-z0Gwg8Y^r)Ga>w7lTzyc
zM_V6?R#e)W(eEEV**4RyQDyu6IfVa@qw9{#y6WPZnU)P3rqAAcFDzTya%QQeX~V2+
z*w8mCv-Pm|9s<hVh)hLfC?F`PpiC8zp~yzrLs{?l^w;^^d(QcubMNyT_nvd^@0nP!
zb2G*>xnh(u!w*($SpoA8S8O+fH?<;{_QumIifTb-R)l%O;Oq*wtB{;qfp;?QE5`9Z
ztN^uRj8ovso^glf%7Kx+2X-A99&f-4Cx(RugU$@yV!*gC?zW)Ql_5+*%Z>3~9(eAI
zAFsop2P2FYd!CGybU%ABB)eeAoAI+3Fnt(VOjz(`>~I0`W89_N+MjWFkV;hp7(3ns
zS|Fq30<eP^?jdL$VT96IgJ8zWdjJh#e7p&0p^Ur5aP27Lky(HqW1OS?LKq{DPMd@?
z259pW!6<J9b|mB7kDw66SV2kWXvQ8N@M0Jlb}%2y*e8LZI7Zkz6snD9boT=^f$^;y
z<|2{dPz|&sMmvonnZfY`InIz%ZC(n4T>!}wj1DRWPi1H+?wrQRX@tRa#y8;r&0u^|
z027&v4Ib#sV$42<)=7r#-|+VoBclwzPd3AQKHNUdc$YrwzBh-FHU#DwhHxR8xr~kl
zVCFHVI$<}T!Iq-4fZ<RGyJs1!PJo_cG_FLekn!|4@aa5blL6`_4CytvUCP+@2ShF~
zURe&2i;RLOm@i`-2(bO(1*^k2SXUTt`eB$AjOU+1tCF#viY%`(-XDhGHAejVFjvJ$
zrzlc2qn=WmH4OKsF|b-j=USMnV?<DRpq`OX3j@~~_md%VgCV&Ou$zphsXD8Hp`#6b
zBcomjy(UJ+f2%@<+)59CW`>qlC@qXVw7Y6$EIA9&Hb%}I&~7tcamR$-Vf^+XI@=k;
zRPc6}QAI2B4#tcQtxm@MLYU}cyzwzeH>2$fboMYlUkcZH8Bb6~wU6Pk7|{KU%|^8D
zF$SrM`#xhJ(Te5(V<Vli8f2_p1Tw_9u?v=l88RMR8)2k10(6vd;8hqLV_aT^);MGT
zXF!`^3`{~~l3^nC2Mp0yn5Tz~2d%I>#SpE+FEGt0`UAWfM%pH{W*P6QVQ-GX3PGnW
zvn7=_g?3DDs(-O(`qG(q2j&vmFFP_tv<`J*KJq<y&dg2p9a9%(o*Cv{nXmI;$&K0C
z3`_3J5vud^VE(%pBA(3f01VBG`3gmUy_q)jbr>I}h~5OgOg7cv`7y`8K+B)mafpI4
z0nE>0(F|mIQV~%Q^8h8_jxgPdFbToTB8r@ZFu#k2-=WM9dUqUUKDG_m$C%m#w8EGL
zP9WjTH)%&5!CXu!hDhcDDh`Wc{zT9IXl5iuapIVZDTxx#{F0XK3Cx%8pk+;Ddfmlj
zBrzQ+$DYjeegn=NXBN_XKZW@Y{x@df3FeFtKBY3Jf5c$Yn8Cqlr8AW|5XoTX(>Fyj
znTJ|oFpJqtj-F&DP!i=7^C-PYvYAWiT>WWgp$m99%x8DPnKR7$&qF=e%9K$SC65{Z
zJiN(gmK_F60rO4DqMT*6?}lsVn8rYmLZ%Es<b_4dnPyB$F*BDUp68hh|A0aX^B*-(
zN|~*fpm%|}pcaxBnQLi#U&h=^ONw%)V;@?Vm@DgH_cC)<g4PwLHHIEj70e~{a;;>p
zqFnb?=H(`6Tw{j51?(#3QTlLIHFLvbXw@+PrMy%vb9g6A)G^~I&|A;Uq1*5}vyMI>
zd4rik@4=hQ?Elhf%uWi_HZpU+0%>BNpq;@jX2S?bGc(yr3(*$*Kw!2qr4-C<V@_`e
z%x$LkO?2L2x-W)kJ2P}1$X#abO<;F09YSEYlexlxndxGFa{?ZAGgrE!vxoT=RZ#UZ
zZ%`?2AM-&aEc7#%Qrz<%Q%qap`^>lQLS%rc{fee$kXg71ibKrUK$sY2y3+=5g!uy(
z&WtkOq)UE`soMa%<IK~veVkwhQbu=@`TWmlJzx%;1<FI_uNUF=6f>S;2Gh*gN?^_~
zU4FwLW|^rDFh9p^a{{qty?F}?b}T~!t+wo0h4lDvU_G$HDQDIdibJ}v!e0coE9)()
z7Ib4Jt8odrvm&B_=E1r^ffG;Gj(4Ev#d@a?2EAFYJr4yRmho$d__FfX!CybtdM)()
zS*K}(9KbqCoAy9fNiJGJtb-rW3B4n%aau74v-Z<98^Q|Cf_^9~o^ITutl#NS&M_9(
z6$Zmt>q4Oz&g!JAB!cBjm7<X>WeXIdSi1Mn8O?Hh7bap@F9bp%mZhY)O&qJ73PIvo
zY4i+BU~%c`k;pnk6)V;x)?>7`PG)Vcg!$vFU;F@?!pcejIl(Hi#V?Y|`krPzjkPNc
zFzKw9_)y4TmC>KoWU}&U9h$|mr(N_(*5nO1bBa~Sfr)I^=tZEMX1z$E#vE1&y*1CU
zw0j_u%L<^2G|$SaWI;5abpRL0!UEQ>di0)Ud1!!kj&+cJm_k+o<x7fKPc8;2X8DDI
zcb@ePJ?=_ay_9k*WxYYW=nJfeT6lPo)kKS<GS*9}aIKsbbqOe!SZAsF?K0~lDzCW0
zQqmn>!Lpt`2ee97zAs>|vQl4$7uQ%TsA!{#^#Sclt6A?;Ay*A+$Pb{ktX)*&S;tyS
z-?^w~1<*WSXSJ3?<OXZtP4I5A6!b~U2G+kn!9*j=oi;5^Ea_Kh-D15!ajIt4wKbU7
z7S?tv9dT`CHB<d|8!KoWCT_Em3HuJKtR1a(*03+I@3Ja&(C=XNwL!6)^?M9Ddsx-i
zKzdnjPeQ$qrJz+pKdWyOytv0YLZ?FSvjQmSHNbk7KA14bI_U`WL#%)QLTi{6SxxW1
z5mrPOWJX!J0WdMfT1b@~<1D8c%-#fR*DZ)lvYx2HC?2rB-3QkmvOcG%%oI!D50Pos
zzgRLYoMBbhLS&YeLm{a-)*&hyv}JcIAY#Y<xE(&(vny%y;J_aAf@_ZK^<sMeIkCeR
zg6Yh*Zb7dL`@cWJab@S<ho~F-_5m1lXV1`!#DlG)U9=~Aa03*)*o){qjyL-Q+C}@Y
zOX;cQ%ic;E5<m7$`rfNQyK5Ak0qhA%>IJf2+6kY6*g>>hJ;FZp#bVrl!E7g5n1`@c
z^w<hze@yATqim0C4Eq>6(+z_OW54nv?1r;rsA4mM?b-!}NcK+J>qW5<A;pcyen_E&
z7`BjVCt}&nT_ADn!>^+=p8b$+ss#4X4)~PFew4m?o5b$>0(#bD_SZ9T@i_a@F_=$b
zyV7g)1p8nbuv6Ll>E29ZU!sb_baux_@F|1+1O);!*)H@<$zpG$UGzzI(UZ_S#dbvm
zWnngZtOJ%#vy~q~GKbyK3Emm@OO(aWWe1EvFOR*M)~Wecb~eRY3fQ}!gW_3s`$1@&
zV|&tg3)yE6fLFw>ro+F*>~&&vo@Xm|!`~A2XY?7IQns85gf6g)7lC(?T|-O7GPdiJ
z(7Vj;9)xRG*!B6qtYB|Fi$PSfJ?N0mRrV4Os9$4Sv+ki;#okMGEY)m#TA<XhQxl+A
z%XaODMjgAA4bXaaKi$9A+4n2Zy1|a8V$z%JHFN@?f!#-|%0@P461*n%TrJGsVpmsV
z5}Mf$sf?_Jef<xRR(3DN#oO4A7(s5cBdkXFeTTi{2^ef=XGcKeE)>D+U_bpSc%AGI
z{sym${WuM~n;lH00X^(R^)TPd-b;0feeB++q0rB6SPg&gu^+zxl>6)#e*$lSy`7$q
zgKSYfP=?sS&wvcGyUqh;gnj;HO3IJ2#SEa0u_F^<Vx0Xp)s0WE-#G-CN%oK1f%bs?
z!yrT+vb|`9J;k1T271%%lXS7ou)n1uf?0MP1qA2Vom2#5%UR+B1v`%45ESe=+<9m@
zaJEu>*^%R(1a&8lpo$JfICH$}q2a=bqlA<zC!1ngZk(9|AnqInRaAIzzSF~mC+Bh{
zM7%h!(W~8?GfA6xAI_8XGx>5fl!ox*6w?pu&r!RA1aJx|N*>7haRVklh+|L3wT^Id
z+MpiH@q3Xzx*5W$osVWH=Q}!mb(9l8tCnM&PwFrUVVo5U029s$ry`&T&Q^LRL~_13
z1QNx`(Lo`aqj?-6F`PI0U_O@f(hNL|<GivQ^Bm7{NChu}QxptdBFFwSkR(nT#ln&~
z-6HU;CpcU4F&U|xdP*#%ajX=NN#~3`2@@F{|K;Fia#qu!h%AntYJpC29A5-E#lcBG
z+-jVdbI?1@VRM0<!-@GFyfd8T%hAf^sO6ZvJkDGYMDjT=eup6yaONnAdzKTh3Kq^;
zIh!uS;X=;4-cT&!6wn%`n3LWC?DL#Qya7|f>7cV9rJP5oX6gcG)8}Yi<P7`*v@*_G
zIs7f>ta$*?OPpu;P`}J+6F~9`M}8D0DmX7uVMHaT>Pa|rm9ykY=w0J{Hv_#Yj+H}?
zt!hr==a{b=PW2>uYdJ|qI8(>Dyb7eAbMRRxUgw0;Yvl%KdnWX6azqKxYv4S?g~3M7
zDGC)dao+k71HHvzZUnEH6W|TW7EZ4j18n86j-l1Y3H|`B+njpJao^$StW=2H&UxJz
z8h1Irxxruu=lW(i+{rPt1G|fpNgIQ1jvcK*dN>&rPVMEa>4l{}PVXH^_H&+%gZe#=
zU<p9)bCTXcYk*Vx4AciX^ERM0#92mVe#4x;4Nw^2Ow%KOl(X5B)}Lb>1wE6-IpsHD
zX@ZkO&(KLuRtoeVaK58sW)C^PQQl*U^Dc!or#U^e9h>3w*23T{=l3S4&v8m9V`0l3
zWdOyFyOtKL_T1P1#;iGT|2hK^M{ck$T29=z*I?An+`duz(;XM?reDx><;K(F(v5qQ
zqJ8e%`JK@B;BKK8fj3t)hf(-&SIvUw%iSLY7(edT_o3&{T|-N!0PZ5%X$Ert%!EP^
zckv7G_Xsy87AV2ojkM(o;aU>mS}6B@O3EMQ{(GD5zhm6r_5&@9>q9B?aBlb8fQjI4
zr&wnsH;Q6nQCu$yWJYt{X)7MXeRd04vD`i9p%=&f#uK3N+{Gr41n$4I&Pe3GIs#r2
z_aBNyCvycq0PHw7iMHY?+#C-WI>9~S0~Bj2*CdCFY22l+!S8hLpHzmH!Tp-*gfhAL
zGvH-$U!&XbB=>L`^iOf`gaA96`zt-QPII3NgxwtO`i}s5hWphlL~^-&Dy_-mzDoB&
zKKD`TEZ~NnhlR7;7|K|j<BI-*p+YOS<|T}`h-*vNTru}?4iwLG4Rp-2gu7-vI!n2Y
zbgbY4S444zi`<VE;kPg2KI;b1a_*b-K)%FX6b273bK6{@aD{u$1FZ^fKE-A$xy3J{
z^D6gQN|{~bCQU=Hit9+NYOXb;6Z$n=X(4`~TJFzLuv^FVkwT`P`&2Guu5*{rW9tT2
z>jROS+}|mn)xgbp8iQ%%%IQ#T6L%G*TW@jAbf~YHYbl0E3->!p=C^VUzd*8$`-=%E
zx49Qq!?ioyQrbhebKkSxh5lVGpAM&YaDVTHiB4|r$C%45?!{}E*>3K2GT6gi`VK^T
zx$&Puq>r2SCp!DNhbY5ykDGoUZVz(fDM2*E9sBPc$IYUN9pSDM!TcyUh2k$`+_Sf!
zKF*DyDzpji*e-hCPjbB}Li&K)Tn+M&>q%?dDXy&#3{G=L<q(<SzUlxIv)q5F{AP}O
z!4o33yeEDKs2%U;Wf+7#Z*?4q1CReS^c;CAN((sg#+E|CnfK~){Aez`Dx5=D=*lxv
zpxKSLe}uAK?z}4$%Jtx-P>{rvCmsax;>l@6<IOumfps6=4!Y)id9f67^W)jj!qcC(
za5MZ3;GOyil7YMdA6N?FY3V_8gvVb3UNG+)O2vloM6ZJv${V62!BJkh79z)ZkKxwF
z7g~6q(wM?|l`4=3UaB8tB6-{B5gf(ymcU>%@8yrci{bT;Krxp0G41H%cp|EEi0Acq
z!$bn_O?ql2@=|HXm&8k^Atm#UQ@O!$-qbJfFojo7Z>1Bw7nC5WJSPgpTGM#8bVa1|
zo}x0e4Bl__hR@_3{2g9o@$7hLo#g%F1d&rbBO6|1^S*usc2D!3s)BwF&$kAa&hQ>m
z$S{|u)xnEAo;}rg<@1iGV-gB@8~K1f%llOVk#oHFDSA}MJ3?F9A_=cz7|dc`bUX~6
z=Otc(ehKez4D?HR4JE+7z}p(I)b<7Ii@!tg63;|6gO_=y-Urwf-hx)hSMVaU(W>Mf
zIu6XMycOG^c8zEAKad(;d@}s3<qfQdfjZvWNQ|MLr%!_3b>30h!`|TGJ2kkqcz;kh
zxq<iiMvz9{$RZ50iFfHFrr;LumX!*<n|Z<sSZd*Iqrhq_FC+*i+IXk`fxEYP8LNPO
zhqv*+Q;)n0yTQB56L~_fgEvg4mpXZ0<Uy~CS4J<aZk{W})O&bu)3T_Sx2O~b`*@SV
z;PvxFw6eX&yGZ9(@AEWiR$veChOR(kkT>uHycpuW^9W>ydG`Cj8{u_OHRdR<g)W3K
z-bHeMoEP*1&?a~(UT977jCp81;Bkwg_mF3M2m_ts{Y+ugY2N(z;O`8t^jGj^d0$f;
zVUG91&j7RKFRrK0)7tT0>xT(@{%3YTbKomm@l!bRo5Rs^;xGIKUO4j)JqryN{u-+2
zapgOn!m!===SBhQ&Sz3hnFs%`X7D`uI$FYe@n56D0B`<49nAaiV`zKr%YTeslz#jh
z-+|}P|Fnm`r4qn@<pP?4{5MMATM&QaemHZ4|0M$^g864hU_ONJ?+jije|Z4(kMi4S
zb##m$@+Ej-{5upb3g?GY>3jr#b0Q=o`3Gr#9L0ahfGZ)Izqt>XG5lZ(J;(CLX_pYk
zj~sxAHJ(2g4@(LBZL}0m<g;i2m&9L4w^1^`*$8r+|1^CTA%%aI_8cep<8&r4mH#;{
z#nbrLsqiYDzm!7W8T@^;GtJ~bPI>!N{A>51p3N6jL+>;{e?CNV_$_Zk{S1FyAb7b}
z{`1=blgE$L!?%2XL^YTN{FA?doaL`mV}j4|XG6g&<cHJ&w21#Ct$vI7z7)|tkDmgA
zDdDGbKuY-qwB^6Rk9-?mT;wm@4uvxQ2SS)H=bH>@UE)vWfp?kDYlAaa_|^lot*PLz
zr=?RRe}52|SNV2HXkFuLccN9rzf1egYJLpuMQiwRR8UmQuc7ZS*6}Y>pr)Sx_e(H;
zoj*pG{0;sUH%Q*(Z&(792LAW-E^Oq#LM1Ux{1CdEZt-pCYk$rB@2uYfyM^Cphw--Z
z&2${KjUP%8i`)F9BshGB|34~)ZReM)1=?MH0;Rt?_<P)-*U4AXKC_Fz?<lal`LUE9
z>EWlzpwP>Ifx=9E{01F({rq*b&%DPk_zS%IeBDY|7~n4u(3@(I{}bKmL;S$k;ps5n
z(GO&VKNSt^QGSvfievoSHV_%-_t5d?3I3t;ur$eE-VW>s{Ku)n>>>Zra*!$hTU0zZ
z%~!tx^E3Px%AhyPU$P$Ko#X$y7%f}DSHZxv6MV*d68E3IpqbJp4g!@PijIO23Y$6!
zexY-y&VuaMF<uwJm(w7w0yAxL+yp<o44%6nD*@BxA^77x=y?iUo`gX!fz9Ut^A;r0
z&cjDwr96kP;PtZ*@e}N)t*E~s@+o)`Ag~;woY)b;j<e_u7F5!+H$+fDRXCx7L(jv+
zQNcP6(2fZLu0lUd;CKk54;Qd@z;1-VQH)VU3TnMUq69Cn;9<02(dz(<5$MMO7ArVk
zhgO_mh_>GGf<2o6mLPbG)^>@4FDXW6O%mis06SUmd<<lc3zn_`Op4%u1Kd9$sQ(qt
zqzb&LwkA!`(g0q%porE{8G^-LfXNgHD*%%vxZMVyP6~qQq|YgVY9mINEl6|*=4rvj
zKcJ8!_^TJ4X9Vwv(8?8jY65hgRj~Xm=;sTzP>iua&_VIXvw~{6o6iY^)LAI_Fb#@D
zf{nvKD;AukvflH8Z@&hwMBuj$u9XU=C{}ktz+D0_E($n@FwioAZ8${A1y7W~(j|dC
zg?lawzKw(1R|LB$zfvKv2JeDKrNHzf=Ig4!nLcZJO)&8nOjHTJq~%z(V1}NEH3B7-
zqtpt5o#1bs;Oz$ZR4;IS6TIt!CA0#%Ay`4L`I~}xS{O74rpjQqQP69Gg(kr=s(-vC
z_?Av}Hw&JmT}g{TWu=gPtKdL2EVT)GU10aNVD;}HcLdIqOKBHGP=e&H;EAUI+99}1
z>99`08A?BQ2}<Vx(=E8=2GS$wdj%-Hf`<igtxs_2Z$S48!v2KbJwa0kc=rVncF-FT
zlv8MAP%zc92{J>1iUjly3x3Dud*O(n@*&KR3T~dlV8#TOv}jEV%(Sq0Ao%TBU_TVJ
zanU&?n5E*BX~9#p!<!NOFW?K;7p#rpuxBT1X@b1H@UIMjI0&=p>FOw~yaWSI!mJDM
z#aTFiDJIQD_%s#pxe7P^cWVi4DYEG<{F)MU9zx$;K=Bkl=7>%&VZ<d!dJ7}N;e(G*
zIRWA;jA25=Pw3VP3;x1sD^-OA2u1V&4-|6f?HMFoxC5;t!X^3eI#~GX1T;c~dz!!t
z72cwyz)|6s6#qUZeBoD!gb918)G%ClgesUKgmF}~6DjPYbwQMH$<J^tT6pkL=*0-V
z<Y>hTHyl7KPB@T7*^YQ&5Iv?6gwYfnNEH4`6;MgSHB5{*S?EMR`Eg<V1O}5L99ahw
zCxqMSOOL6-`SeCl6SAqcD_!V9>w*kn7(FvHg$^prT9)vw2|%9|j!?qtl<*k7HoGue
zxP$)Q_q1?+3Y~|{5$d);|BUcU+Hd6w&mkkSFi*H33g+{LlE0u>AbfENd^#)qcMU|&
z2|I0Iw@}!u$K(|W*A2m7v2b`3u+Ix?xG-2EY!CsZRQSYK(7Pa9MYTT{g<}-lDibc~
z17^8!;D5CAz9i(wpm|y7aUWh>5q=N_zbk~F)4HTm7+DC=tHNLDXSyc*hyu`6!o#&d
zs}>F)2U?AAmm~CQh36?OTqk_09t!oskTHl{7jB~^@D1V7^YFJ(=t^(vCSjs8ByS0)
zX3(-W3mGc`(<1zkKKkD(+@wIOO(=K|Ft>&K>D<m8;gCH%Y!^ml!Hc`X_qIZ^Ll{gC
zyH4RKy=S|Gp){r4!pA9J-6K5nJ9xc9Q6d!jgwkfrMZa+K8{pj&e*QHS?h73Z;0;)X
z2SPE=gTkI@$P5YJdml~>3)fS)W<(f7yZTY#>v`af3Aeq4*0@m5gUEz%9qrsFh2njf
zt_Q+jw*vH`@Hq#7P6>yoXmnb*=oSpl2+z@xyjkH&di%`@Gn%1pE4oU7K0A^1{_|kk
ziySh6<{-M=02oKn8&qZBBwAjAmb2)cB{1P4IzZ7aSCOC&3T~psc@S|ISt*j_Axfuc
zsi(+}QtDo!nRfW=EyDGQ8&72O1`PU&9Oq!cPxL4)Yy3r79WWmtI&b|5G*I;TZ@>-`
zMblxcBccg9f)Omb@+oE}M09x;XrUq%{h~)jpAW;*G0~41XoZQ^ZGypY(GVTah!8bU
zrB<Y<YB@TiMBUE<ELybuHMC+xw)B*W745nT%s5ffZJ3Q0efl9S=o3WaRMnFxdOiR%
zlq4#rW6jAT?^nS)E?P!U$rRCgN=Tj%<<rwSRpdMXOKGAlU!s*RYMy{dhUh*85i>;*
z_OO&C@*>wxiYn=`b4rx%1chu-=1=H6EgJY6UgU`O+@uBl8IgJ|Eai$;P_0CPC^rR`
z&WfH}4w!SIhQsiwP_*|ETwX<@jkf_)Ec&Jy<h;m-a_J?ajiK<jRP-6WFE5BD+yQn`
zlt$NFnP@Mar7IT={t0qPw7L_+zAQSRg!&cH3D%Ri|0+aVsT!$Lw3wnFS4F!i{C7?C
zE*qX!i58{6M72oS3WsY%;Q}buicpS#TTLXUHCDZ7FBPa<7oDL8>kUyRz2<L<UX6!d
zgQ(pWt~HAO3Iwl7lv@GbEs^*>P?|*>OTn|Yh*nc6UaKhc3S`<uJW5~R7X9<z_c%ng
z^z>;L)p>$<S9C@N(jkhV{Y0l|J?&DvL>H)Dq+7(Ll~a$XBodDHiu&mzDt)4Nsk*RV
zq@_6LJ&`mRlW<@3zq7DAAj)3~LxWaP+<qtyiT<UJbqtFRX8?Od<V25_QBgq-T4SQ$
zAH(F2i+*_;iW4I1|A00r+OGxgfk=~#)<e+~mEcW@>ZyWoTI8vQ+cTogPl7iq`kaEF
zb0Vz;(`74W(<hDW#1&7#yuH|pC=qTv@m&`%9mR4zTyzr8QX1G<{Lg=jN%1&6i(JJk
zsRZ0j+)JO}bQhP&;ID@`Fb;a2V)a3o@Dl&_7<k@dKYA<qh^s9izT(+<%$lEA?+Our
zaoCHn8zA0nf@GlhzLnOULE<Bqfp$dvwhDHG#ZNzg-yz~pG{6oOx6*e^kBXC0(K;r+
z(*T7C@tJYJM2chUp%*1KeF|Q*IGm2q$B0)`@G@4sVKwyP#7n=#{KkvF-G<HtaY`se
z62&(wVIfJpWtSDqWU)ULzaAGC)S{IlejtITC&ZhWa4}W<6)oe^#1Ck@nlAp5{<0xM
zyr1@anc~!~fXNa&Qh?>8_#6cuPKhOyUda{@PeI|dSVwQ+9PyG?K%Wse(s!_P#k=={
z<car-=sZ@wxO6c@3&cOs2Ij0dnD*@F#J840qfk7LqUl9qzhI28So|LCvd@dz!LVB*
zuA;n1sd&{j=v@#$|KCX)@gUWrl!;}u#wr)D{V!f3p8q%WE{m0)U`notf23N@3h~m%
z=saYlxPCrdyed9OwMy5-&)vj$tHgibgGRMj?+Ft%V%t9OYQ-nA;Y^*ly#*tz7fUGR
zb6q^}Ja{+6ehcBnO>yU8fHjD_=%L#v=FFh8NqqbnblwsdDd1DH*h)+A7IEMAfVQ@Z
zchEMwO?<K!Xt%{3<nSHwYqZO57k@~>rn};K&am4d{&Xiur+9)6M0JU?Pe8w0yo7ey
zJ>o5t2<;W${sanr;+JT;`^C;wuzXMaV?TKJ#j0%>*?@TeJtz!{r@hfRWEJNf0UZ`k
zFM`I1__O)Y7!~(_3ln4FMW2I=i%nD=JR$y?1rI01Tj*kYAU-gO&WB>23w)Xqf2jk?
zw77R1WJa7vxkp<`JcTIiB$Z!ag6t)Q{xI(#`L_kcQPMzl_)Ze5FYP{^C0wefcaezo
zxRP8YZnP0`lSt@@x4Yy=`c9dL<kAE*JS8vC9@b0p$!#cjOR79z$w%T&Un}&Ltoa0b
zeiFlZNcu}yw1NtdEL3Ak0wv29!kHk+qZDyCA{qS}D8Z5_>!(l*k({8oSg2%OGAtdH
z1Z;-JG09658wryfyaSkUiHr`qMo0=N>lZ2c>Me{uO7b`DvZEy%smdTm5<vGztmGI?
zcbsJDUO>l71nVK0Ad$xdGf|SY5v?T2<`LLSmWZn;^?6+KA}#1sBxf#wc|!6JAIwyV
zkRDrUlE)}(m@d)Nlx9edgo2kT**6cZEXe@n08dId`5>nx+rEMq*^(OC)}NNN_d_yA
zVtfsD&q&I506JG<Isv^r$w(m-@+BefP?2eYL>CS7XC=>kh~9IOgFj#r3niai0Zfr(
zYY%wElBae7`@AGf1X3dD90e(rI7|WUg2W*kdKV?juEJ88#GiKA<q~l%P%cT{xQy0i
z$#<Ut?21Ia4PX`cnJ|@=l5@XP>D^Vyhc!^VCi#qxWK>D+^}_FJi4%PgqekNR1{7;0
zDrYFxNy1(MTD@d3E#$6C66gxPA?c!jQn)D*yamt($w&QAXp}6k09ccx_iJ?ClANWt
zaI>Ue0+bd>W&wDul09^W-FioIjrOqZl2}@`+?CWk1<(%36JpF)r^Gz~qFoYe1bE$&
z5I;EDBT4@jq*t<+ibne+*KPx*Us6ZQ=6jMCd%(Ld8K7TeKob2qL<S`#bk1i;QbY^S
zVTtW>crhY*bv?+aRr2gNpktDe3>X}jymcC6Lh^Jm{GODk=wQ+V$>R)&Jd`9#(3+Ag
zCCO=tglgwzBzdpE!&%9TbdqUKa`G|oY^5%g7_^hR6hY5kYI7Hz4pQ--XgNxg*idki
z4y=WOv(&oybNJ>WeM66?tMo70pSVdcQ+mc-TC9Ql9@66L5b>05V}a)-9i!K%x720~
zB0f^-HV|Jaj)maHlNO7h;4giLzS<HX9iTduK<Q_6Rx(Ihwg-Agq-FFOgkWj)4Jd?2
zU$DADKUCU8uhFB@d6X|WCheomVVLxFTCs*pr=I{XLOS^qKqIBzLFkN<hJO#AqNS=p
z@M5Gcv=)e!K0~|gIO*RM-Hw+A(Jh`JJ#`WDlqmh99g;~>o0ZT@mY#YZzxi?Lw4PEv
zDbgy+o}ZA0w1A{ax6ldIH0kyj=%-6lebLI07C(UBnbI#Pj-Dkg*@rQml=e^x@|5(a
zEP!T9f4c*b)6&*Xc#$LhhPDD{q_KWL$(24qCsgyKUeCjseCe;Wi!6}VK1!+2v(h7F
zKszVhNO7$~={d?@6-j@jGaSXzmG1ziR636;HZDltJ_ZvPrOyt4lu6rL;eEL@i9Von
zNxHucpqHgvKLN@W>8nq|rwVD~7a*0=eQ7X%ReFHR1FlIAZH9W4RJM@zf7Q~m9+;?+
zZlmj}R{D_wqIJ@3ae%3pI=u{y>(Z|>Vd92#g#Hifru2CpM$sU>un5?V(!&(VYLdqP
z1`lsZ-+mLVW~q5M^jf4HbaS*yx7dN#CS5GW$ZksqC(wCE+Qi3iU~QL<KLLYxrK`S0
zZ-+GQUFdg8R~`fDlD<x>%5G_48%U2--38Js^{0ntpY%R0kNTyl`_Oq$ijSb-#*^ND
zA7BGgHYHmIrJvJEbx68^Ud_W&!(xbxNF`KKGAiA61L|W|sgMDu#-#(aJDZR??*iJS
zG>DeS52T$b@ZzD=p4Pon(&x&dF)eNW4y_q!{|@*&D`o$N)|~X+uOMkFduk)F?PRj&
z&}lEbM)#kCET2+&j<SE~b>bx3hh6tVXBmUa3S4B?*In_exyo|5P;`^crv#F_th^VZ
z9<s-1*X=12QNr0vcIjWBdCT_F(%46qKs!ZW*;+Ox(NDIPA_)GnBNQwPkTp*LGf?(E
zmBIwc81yzgB72WYtAb@8rNdB&Y*!n8kx<zS)&~GRDieGUjbpM!wD=E`>6Sw@TsA%r
zG7&P9CrG4hfX;D5$)2RMThTH(oluRDrBO~SR>r&upAuvNPC!YN?Rx_zl4L9T0G%w;
z&j9SW?4$SKOp5H)0EnEBRZ#LhRkm#d1(efdSq0EYmxU!mBSV&(2@{#J5Zc3M$;#$I
z<fQBdmD-<@ounmhw#=Shb*E(&d4S20Ju-mNpONML1zxV~=w(Re$?9Uj%a=K|1FS&i
zN~z1UvSxY_oRhWDQm;_9OicG*ku01C^Tje7FOc)H2?e|;k$n*kv{G5}O?YuZCf|ae
z>!R#)I{i{6`?eXpa@hu|uDv9)e+g)pW#4AN;1$_V^n+H&wvIueQnsoYt*f#~S}I<X
zy;%x{DjAo)R8lRwf#2M^utv7}Q^?fH!YE-~C)-2k-0NkfFMwQ^`M&_(4H>r>?%$N1
zufsqaWan4IQlrev7Q80e6y1NfWY-%Y(k%P%HK4S}>S!a=Dr=&$f;QPcF@|(omP?Ve
zJ2G1iyl9vCpMi+=uB<c+mO5nL(RQIzCfWl1E?M{v$aKq?doa)*Suf=jdS%tL<m;35
zt%AXRSrP4W?#cGh+yB1o#9lZvAUin*-k@ytU$8qQ8%hKjmZg3HG9qiFCFZDX#VE*_
z>=JzjdE6@N+W><TGI1nkc2f4LGteH$UZ;-;K9sc=!?h{dPgF8LEvwxHpJrr9MX)q0
z>)Zq~C)>Ckowo9ysdUFqzCjKJd-;3xTy~KAazGsA8`pq1$#+pzuB-eceJj;XexCB&
z?sDtewdnPbe@vyXo^lC=<Gtj|cA@1hUru!{KJu+}b^FRY%`o979~*{<zkDbQtpK@(
zK3Ewjf1JKG5G0RC0q7CADFgln%d6v|7b2g_f<mZV^)ot;%9or6<}vwCzkr0vovc)1
z6)wMZ8fX#neL`GGk@B_AU=pL`3u!kQE#E1CGcoen-Oz}Y>$gK8PToO>Qsd=AZ@_MX
z+=I@$B+5Tvqm?Ar^g=ILE}$CU<8tkz7=4P|l7iL=`QvoXAXPq27g?G-ashphBV8W6
z00uMU+>6l9l<%c@Q<nU@I4GW!ucH!xQ}Q1v(VZ=ipjhK+c?A`2<j4i%KszIEqx4;_
zd>JKj^W-1Wslj}?Gp*wa<cA~CIxC;1Q|ssCS@yszl>bWa`6BrbYiRvhEZ@LG?|JzX
zQ_wGwyVJE^Dwk1M;(|Q=B`98$57HL1On#a|tmX2{T#!q0Svs&U%X6QD$Q5}XE&eOy
zGY8>XrF_$m0J|y|T?g-)yo!!&R>@^^n7nFv(p^kfjoh@65<0c=&nUWHCl}I3@9X95
zk78=B%bR|Ji5v3M6g|Ev?<|EzgWR|R1{>wqKgQ6S<R10l-I9Mmuh?e!{9n;(k*}-*
zX_X(h18I|M=*qt>pP(hd9eKDDpxfo;W9Ymq|A)>&Sv%x6QeeJQevyJuUGh@8l6vJY
zL_?-e?sE|`{qmi;uzOEFuna@HFE`6Dm;pIs2zrC^%U=U~Nd5|C7Ki08(cW@IzNZlC
zqw=lE&>NFq{{^jad5sXf3Hh$qfHEmB7hq-{Smj--Fzko&W3(`ulKXd}cUo>A4(u8E
z<=yC<l{Y40Fmv)tQ}EDMv5(>cb_!ns^z0QU>GpL{<kPyyQNg6Gw3FhOC@459x@cYG
zqR2i8o~xqaGhn(YVoE{W70-PIo`=GklneJg6)UN<(n}Gt7$&?Gxi90__EGp7VZvAO
z3+-0?6uDHN;IH6Qo<Bgra>AGb6|YgMIY^OS4fP|6>gRzSta$qkkPyYjbr^4`qPq<q
z9#wFuMDdtnDXsd$6gpZehARx#KA=S?mLC8!Qc)=dOq7B}kF99M*LR>Fqwp4@Gggss
z4KQ&ETiTPxD}=PnNl<JmgZV_o>|;PnQrx8QLbBqe0`QJ2cGJy~qIiw&)DwzjuRtVK
z@eRd&(i9~TFq^K}+d=Wq3`J=Sn3)Rs6tJ@tu}Tc|q~fzvAg2^7$?t5%W-3fLt(c|b
zQ8|ifH(;Mpv{DI9uA*!WOynt&IZ)46{JIVb1&W>#Ox{_AV-vhTr<g~Z!a@ZXg?tN(
z6y3B=C{~=((f6p%EBq4SREc8WYG9WtM(GIP1%*F-i|nEzm3BvEim$G~!*a#bOMrGs
zQFI!u3Psogv?>(~=&rb`*s%f%*A&&eVZKTcS`CzHMb4WrSffazvm&*MyL7asPLV`g
zh<b(pfAN>=idY3?ZYYl42HH)9^Y<89gQ8FijYb9QDmt4KKkR^Ow-lG&0IyjwN2PZy
z3NQMkQmf*37D$`oL;7>{+ln>xeZe~l*)d?YD|Qyc(p|;S3()IO1kgUWQ&CD4A6*Jh
zIv{WDR(zHQW{={1E;M=-UQdJcDY9Ha`W4A}7}`BWF>OunD<-CaHlTQ#>LmviITU&r
zQe;xFU|5kwr6MDWr|GFRs;JKc_LyR{7p-x{f?uIGp@@ybluRnBo(AuMqL^as53Pzc
zl9^I`at$)mie<xqnZbC0J*$ZL9P>4&5P3qwR#{F#9XsU=1qtnyjkH{MP>Su~p`&sK
zy_KAl`LyV9Rz^@Eg^M!nU%2h6l+*LZP1%n6k%jKcKPh|Sp$ra0%TsAxM#qi3lpZ5M
z^HwH20pg>qod+~uWoHH~`6=zFFu`9rKs(I<Whf0MQ28D`wStr$6rnw$WKKaLSUEKb
z5~BPu6eLvnX%%=!l?!MseoVQv3F=|WehMXrD+7n%MTAmdrRvQ{<!3@Lqm<7)iGfBd
z`LDr5jFQm>(OBgTDJ;b)8~+4}S9YC(GYLwi1+$i@e7YDSNy;7_Oe8BUBWN90&eTIa
zMVUs2TTUwL<Is6Z`DZl7nXSA?HO0BguP7;zr+i9E>(6}UZxH}3R7Oy^tVo$hRanK!
zmwjR4it;C_AE{I-{2_8xSwLBZYszxEx~r7?==Z5so)`gkjk5dz6l#_CbZFHnho1$h
zSFWLe+6`s*Cy>0UOew+u8<bpnDK;wm3n>54q&%<^m+mcP00*Ki%884x)T#_`#F*NY
zvQkXYZDlQOeeNjVrmVtU<-iyuJCq4~;YFwNKrGO@lrdDl+pWybgnEy17foKT@^%sw
z`jsuTh`y)n_%9Hs{G=AV0p+7Od~aPis60iP)gk4jtI!`-3TZJtqV%ULX;k?{C3s`X
zO?7CEE5D!@!Gv<tA)rkvC*|<zfzp;1$`6%w8_=3oHc`lMM#-TB>#VZZ07vJPP4nQP
zt!mo`K(SLjI1HYH>S7BzS2(JCXiw{;x|jsJ&Z<0GJGrRV23$*EStFNWV!TvaK8B>X
zO4kNMKB_hf-}tHeC>!9f;tT^bK;`KSkU*6q6)6R&(#JrKsD7f_>rmBm8vuD!wTE^W
z$5iL&iVIV@CV>~OT2u$H2-P-v_eZNd%P@u*m2oRXVpXZu9q3I^?b(V!B&s}CftjRo
z2n9(|Z5@We6DsY0=bcsGQ@ANZ)gyqvnX1oe|CFUNPs6or)n1BVpH{WbKqN=Ci@x%i
zr_#`Alzi3ZqwuLfwKy4Ig{oZ?=`T`wQ=Mb6Y9HH*=6ThgbQmmA{XlD%Qq?y4&C68p
zW}~xQbzu^%ORBU>;9XW#)dTyAs@@*@6{@li;r2Dvr&NwqrRt!(UA5})O&F|EefcuX
z*Q$P{N{u>|d=FYTR12O5@1|;yBC-vtq9QsMaZ9yS4zy;~i}PWkMfDpMXWUlZrEj_1
zQ5h*L(5{N3ocvwYZ;#MbscQHN1MO73NpH{lDz5?99Z*>Z;o6|8pT;tzvW~*;u&VTZ
z@J3XL&tdeVs?>*27*hq&9%o$Dx_url&I#3~Zpcik{(T>IAE?~yA@fkxK<l9?)m9PE
zrd3BNJUyebrQ)+$)vJGj%&C&x(P^u`7y@iN^*TO0v{(1hy23%d>~DZMs<Yi7;-q$Y
zh_N`UtGA)kMLpI7Nmq5l8W^&=sYU;S>8@UT3HOGF`hGE5o@&)J%zLR%<O17U%_S2)
z>gQ;8;;$~J%w~W(&=w+r>Q%ECOpw}_A_qs*o9NpY!Rp-=;Dx9aKfz$A`Yj!NI;#GJ
zmVe=D9qpeY)F1o+5@}V}(qbt}y^j)T(dw?v(2r4na1&m{s{7kuDNfx=g>CWbM!H85
z)V6ETnW$b*rNv2V`3{UCS-oaHc*oWMB;$ukQP<OJGga-XL}!|MM>a^hn%xJ540S4<
zy~|WTauFg~YHOSnXxZxL3juRl?M;=TIqFQR8a<<yZ2&J<y_T}WdFrVawDQ%>f55{6
z^>ehuJgYv_hbcLy-bL3%p*s3=kRtVCZ(_QN)%*=GabE4|iHR*yr=J74pw6INQ@Q$-
z7?_vT7VCY$Tvo5H1?Uy^JK4~vP`6E@RjIyT0gbEb<YfT8rhb_|XIiE9+yYXq_N7H#
zjXHM$e5zH4&~CX-z3EesdUeKs<>YFgZ!v2P>c$p0)2N=i0I(+YHVQ`GQoC#6cC-47
zhBilS>N#4D-B$0Vcj_JWqqKHuSLYmu{$2Hgmtnp`{mmALbgH*60O?Y1@y3*PtJ7%5
z)T8e10qIpAUIgqu^*T04zq;mmpxjgMqX+4IHDfC}htwO^!<kXF-G7UAbxjf#hm5Nq
z-T`w$y>=lqCe?dwF+&g3@BM?;Lv@24cvI>%bSi6FJx7%VGwP!M!ThXx_%XER)WNg>
zv)8z|fjDRq>tWDQlTD=)PMU9jf{3%mpR%+rn(0U2sH>)i&iuJ)&c)Kl(%dx>^z`!3
z{Idq2o|@J_(DKqWUWdM~CY)k!ewwZ;@Y`SWi~~r3W+4?925Od38Do&<G=)JzG*4}Y
z-B8Uzdix&Luv~$1O!Jlr>S3B^=wo!@nl75PD9s4P7@{@v0^o%;MiajTF2-u!sfWQh
z&B;g6iq||xhv*VChpCn<QM2GxXe4Pid<l(YO*_@UAJ=5&V7w_BAqRRVHQpaX<dkMX
z8+^*v>{<`K)0&<r@NzUqP5|tTX7CoEb2WqA(96?2G6#`-tLEpg;dg=N5yZC_p4EIE
z0CG;FrPqC-=0Y7>MH+7b6pJ-4(UovsqfP``iKd!zWTl#ZibP+~{FQ~yi<(?|^p|ON
zQJ}M2Q~Dz;UD9-xz_rVo)%0|~qG|U9W`)K+2$Gc=Yt3@dtC}c#4DFhx^f*APG(lzP
ztk%>FfYfOAd;k-*8lDp7>onV=F#3AUsoiK@*HlxP!VOLK+rYl5>Hi*MYS8>q5A%(h
zI!X~VX+~*tb4&AH5JZ|a@>J-xXzb}R*{X@Psvy&*F;htCwnlRlmhNcYrh`!Jnmh`)
z+|~HdzOO^0rDRd3rZ*P`yEJ)EfY+`0h)O<sG)Xtn*{gZa2j2H-b~nRBzviAJ6z*we
zD3*F(^Tn%Z4QQUCsOzBS$J-DY(mb-C&gBl{iU1kW?4gMAsHXU1XpCvDGT`vI#{UB5
zYeKV{s=+2T$EQIaXzo6X&WD;`Tc9_inNREbSq<}L40KL&>?C;h+K&$d%t0GL)oYI0
za2<$~*85qE#aa6vJ^Wm>i*uI*>`Y%`{ndhAcdfTOG(5D!5->frwugY`rG4*bnDEwK
zYedUOd!81tzFL1;h5BiAVNmebcFzMZK)atFLV;S|VGJ}_8%K%u5bdI?up6osY=pv5
z?JIR~^q6)e7Z$>_yYE3gT$^Z>p*KRC8336`?VYRWjnev1d@EYpy9H=5+83$7AXXbn
z39vZrYm~2u*OtEtUV^rbmb8i5M_vNxaqR%rm!@bH^guqL4WMU!s`lt^3?fb2`8X8P
zwePRQATqQ*t09@Gb^4jsAX(b5V~{zi{f9OUr?iDDpr5Th{uf%OwPkb|CP(|T0s}px
zO;`v^x!O5eLgi^s)0F0G&ruw{K)dD^u+M6*ybtwrTB{fQE!1A1w`h@eXcD|)?N@Z}
z>%8{tCFqrCSM<@@=u++5A(*HO+ERMMU({~<7Y56;&+I{GxpqesU@mFPl419<_L*JK
zzoLErG|X3M)%5X(O6|gOw61DLRZzI5%`bp@l{Slx<yUL7jzh0T8%yWBYqhe+Az7!L
zGlJA>9kAcCF1)VIGr;Z*?Q?H~+|(YV=ud;Tns&sE+Nnb@*rZ)e7wIi+5uHPB*6yHO
zNQ-v39-Xb)d5^)1Hf;qPptrRLDUNVQdp8}E(5{W5*yLSprwe!;+I>IbH|W-Csi?O{
z>(>km)?RG}JyH9#P4A-Fugwld>z=k}9&W??+MfFu#eg=Fs+b404J&~*qz#~z)UbBw
zG+;)w->d=lsJ1-;dSlw<6f7Ip&OZhZC$!kY<HphYQ8Mp=_K92Y{-Ji)5$H{6b4Ssd
zwrWLY*qza)j6h~qJMIGPIjsX72(i^YNCT*y?pHt9wbwl|fKCV9nr~pxQTGZ}Svcv2
zsH)0Y=id%c7u{=r!LF-L_ZE0=x`Kx=@2)G$2egN7{s9nA-R^Ip;HAr34NPyH_0=C?
z-beQnZLWNE?@^7gpDy_`*!9<?8SzsD=!6~U4Aeay3B@4YRU333(cPhdOR%o{OPC1J
zNy)WP-62XC9MvWN36W#EdH2v6rmHRmbhxgBN{=FR^XYvXsXO#N%tz@yvC?UaXr1T)
zNQ`bHRVv5oDk$WTpnK*HOeE@V(p{0Ho8JQLWZktN&^oUBKnsx+orQ8_Cv?4kKr&Uw
zcY%j#x~`2tN!K|SK{7*Uq@%EzI)8eQXX)78=sc-gODU^UI*Wk<MA<s?XPDB{x~spT
zH%Djl4n}`QC!oryTpfo}1bMpUG_(1-kKTtD1-e^wZ1k+|2RbW!PPdLe;#a6!wE*KS
z(g}ZoPsO@dOCfn)_Zub5OLR7sfG*X=n!vlD>%W1{i@K5#D$ps@c@_btTz7CM3|`WG
zNwK8My0<A8az%IY4cM*FdC|XHRO%AwNq$w=xe5x`ba{4YRq1?95UJKZ-i}s{&hIen
z*6Qx);ZvRN@s;ST*WKZPT-VJ~7~+O5H5&>yb-g#KK&L@B6#|V$U8n#insn}T?cCDY
zWWhwU?#*v77cIKBZje@8d@<&tP4_813~uW-`N70p-J|rX>(Je&!@8ZiAs#xrbkEJl
zc)N97Z$q+27eYDLUfs8zknGbrKM6zqy8flGV7;gN_6s<5U#FnW?|`mlJ;<Q$C)#EV
z>3nD5>9FoCO23cjSacta>OQ7D&zSCMI;J$PYojN`gzgXe_{ya2@Fy_%K)3$~kcT?s
zexOY0M(EW#txKia?HS$2QlQN0woqhr&Z?7CU}&~__De8fr+<W^NA`Nw8yJOye%E(U
zbkwWXgE;A{qQG<3r%@!#Mc=v)Fs}N;v{!P|&(LWLcYPCunLPAQQSG0nKKf^v_tMYw
zK;2t!aDal3zW*AA>#NtEgn2)`^~`BF<*%3Lp*KJu&;gl1y{8FiLHZScV}wWa1AhZ8
zSYK{HXNcZ-1g%j0BXlV9sQ#Ign66{`Iwzoo=}YLz6s~7e`AUS|mkrEF{mWDh7NeJq
zLN8YTB>5YsKSvj0qW<^)3Ivk$A0$FFS^xJ|D4x)(4uYAgUrsNQH2r~N(8$qW2#2LJ
z`bIa1<m#WIkZPX(he`O9ua91hVHfBdXm@m0??zjfbNZ$9rYzK-r95<zem&J)7V8f^
z4MXSkW&Z%BMDM%U3Yk)U6g?R)=oe9C_(lCj+DMh@2YoRY<$BKvICDu~zYHRm^<TdS
zm@E426dkY72a-aizQr8|uj)(a0OU3O>1EKX(jVFgy=whV3i#LPzgY^sTD{vdaHdZG
z8Wqvh>ob?kljF9~XVsv2Lx1`Ykem7=_n^_BPoV?3jrx7w0BzFm4w%YeS%0RabesOo
z-{Adi{c_q&-qBaA19ZDSgK`*m^?So0-=V)pwb-5dtAl{-(nq$T)vf<M9$xq8n<zZh
zt5+-ruMbxMTK)PXuVZ5F=^vqF*nNE)9lIRRcWclZ)Ynld%#gmu`YM{k`bU0(=!pIY
zTA_~W`<j3~roTl$=(zrMIvPEpk4}fBNj+1I)&sqYO7|Y>hvHyxN`KfBWL7^zp@upA
z`zgS-HEg4A57`+uFN37LVSY2f91Jd0u<vM)EP_2JL)I30SUMZtwgS|}u!Ektu7=@L
zu;ga=p5A-zhIbl(=3&?>gTANX-#qZV45gI6@;02Kt&Wf3b2WIrhLrUH^)q}+ad&^i
zA4kv%Fz7ykWS}8E1Cl`oBW<CN7zz?F>R`j)L6l8CYOv5d;+SFm0%(L8j;i2AxM43<
zp+p!atKng!VLzSpk1{+bh52a15(+uT82%)fSi|anfgNXvroeZ+fk~UP1cTRApd=bz
zwFOBsyj}t?k_~f%06T6N{|D+RhCtjC)`cewuTW|r)iApi*lC8uS}@ZMp$a&YVR%Ih
zjZDL$^Jrxm4j)15q~UM_oH=C(Ux%5^Hu!d-b=t7Y3wk+*Pjnz>3<x*ko-)`VCbKZl
z5b!BTzM)_Oq`>ea?OM+ohF`<1S<e|3>EL3aA$kP8MTU21(_Cz@`vBPI4eyMDlo%?4
z0a|J(I*3tRFl?v4Si5L=bu;Xi8MGVVeYxSSMzk&&67GR_*|3fhp;rvm6cnj2oO=`^
zm4>J3rE=BKMJM8}8CKG_hpMcGEIN%`ZE$)SBdjrGE8#`0;SG8|)fxEf0aI`I@>2}^
zx<Nn%2{#One2>nXhQH|dX)t_s88D58aJqk*41YWV-Yr8py<3_MyvM<7G3>dB&f5ll
zIz;XmT4@Q;Zn(D$UfeZU-*16Thk<tkzI7UYJqBi%f&T%_cN-FZfJ~2}p6Wk(4Lkpa
zexIS2)+POhXI_BFJ%b1RTK5fwl(io)ETbszpy68vcteJ&Ch&$0k7>ahG4w14*r;KC
zEx^VM|C<MU<Ays{s*;^BJVTGihlXE&hyIjdKW%`f4L+1ynlX%dL3Gyep%AXk83rkg
zVQVZL1F<tMqm#z=#*6OIb1<gTD#g+G-7}ajC*%KgfOa-2A~1RvqlzvMSECIbaBwpY
zP}IoXnCEK+sE6^aJ7heKuQy<XUdG92pm`gUj)C|XZ<G7JMk|FV{fsN=(1yQJ?F4@V
zj8UjZS{P_Fyo*+l(Y755M~nxaf<mxyBR$GOjP`foXsGcm%6T3&`cg6FG2<Re)rJ|*
z#?xXY+}J^{g9u|q7)YeCnBJmM#*`qmqK%PMHXUPZcpRXy#`YgE7jec<?cjdAam#9;
zB^VD-!a33SGTm`W##lXg$;O8i$~|s;ViqLDXhR3HPZ%BlhgPa_y8_T@M&1AgOwx^2
zv=q-U2J}KE)2O)${Ve0K5TYlI&pnIQDP!*I@FLszZy(5M;|a>C<rq^JVM@*zw@`3A
z*XTz{k38d=1K{NwYpLp`z!)+Kl(WY4qu`x0Ztz2AvGENvFwYy4XyaooF*>{j{ZixW
zR9$hw*u{d0i^j`zuD8r6-3MN|@rwrly=1&cVYSP~<O?8IjAy9EqQbb3YK<z5b`-|A
zYJBN?w5}PwzQa#ZWpr8%6V*nKuP{M1#+|+Jx7K)yUd(ky?*ovmw;H`@<#yd@=>@rA
z%=j7RZyFz^n013u`92gIjjgXiqsgcYg)_H|$?<T%+4$*A@LG&Pn_;)r=s+v-He<ni
z(7SDX_i-rPF-o35tKInb4nW^ER@FnH!{~M#q|+Gu7|eGWtv<9(?l$hE%~6kWmfp<0
z#$!ro^cmlziv51$7FtK$GY(CH+&8W&0``FM7y35bpplagGGzSv6QB$mZwFx5BgO;H
zAfv_tBP@*>y=tI0ZuDS+Oc)EVf;VXlUj>B+#ywVgyF4_WphHMg#^)%qJ8iV1wBL;J
z4wdQ58b75~*_`o@mC&#?{X)O5ovDYOTJ|R0LMS+x+MmEr;b=0@K~X1@A{3TfO?SV6
zh?{9c2n@QL)=)Cd!!$wZO;1z$Jj|h&>3pmeO>a{IRU-J97TkfNugS0qCj3l&uR_D$
z^!GY+2AJ%qswvQ9M<pIXCNmWWA2I1DNDyoi&VhuO4pS^P)O4Q~-A7G3=}~sfbmU`n
zhM79fU=ZP^1gZ~>Fhw1NPm!kdHz{EdW!mn6fkvCY`39C^Oy5%-VytN|#fRfeMal3m
z-qcE$SAxlfDt8l2_b3>eWZFyF#$;1^5_rc=?eu|>6w{+rS9iiRFAzSZnySYDmS+0q
zI7HG-a~$Ypn0BlO$uu1(ruSc#$#w?KlctaLFnG$en?A*mZ7O;mE}k~6q8NXUN!x?*
zo-w`c2DDt$AHx_-p6M1H*vvPT(QCiJ6xWK@SySaH@Xnd$)7hFr(>w1#y~x!0CCnF_
zyw^hHyy-nA6iQ63OCVw`HT}K{8W&6lzr$cIn%WmYrp)9P1oP!4VKrKpOftG=FPnDD
z0CUCET?o($lVt~5*G#um@VCmevj!s7CNAwRYD}AW5UDk}XJRhuOrx(tvfi|p!o1f_
zVeS~j4b!9a_P%K~<(-FOgQ<-~8&Ti_FPcoD3~1ak{rwtR%_f&iKx;9jQx?3{#Q762
zZKmpW=-oCQzJyWSG0o8(*KT@m7OlIc-?%W*VQQf>W}POVP^fpA1eA&CHa%zqbdTv1
zib?jGtUE&BaGz-=2j29XN{Z3CXF5yeb@xp>C=5AZQofGPL6h%c=nt7f`@kDE&D#k}
zBc@4u6pot4DI_~)3Mhta<EA2d6i%2<P>_4lw5<Vp4@`A`q4m)8H4i>bnRZb{+O&yf
z6+>gjB&DUntSNwx)|}}9J%nt{U(N!?&iv;IwCv4oba^<Ke|i?g(cBjRgHGnpX!4!S
ze)J7I7qgXKimql2og8*Euc4FD?&eig;NoH4@;mfA&DB(s<z;@R5Ik@5SUfE}eauV!
z;Ek`jJO#wh>`n*M{mt*J1x$dskiJ=V%>4YT&<`^&+zm_N=FBNriZEZM;8Udeo)1Wr
zx#Kg4M4K(=G2R%nn$~);W;fbR#hLq_23Wi~m*Uw;=F@bNJ=whPUHXvAadXUB*iA7<
zEQV7j%y$Byk!oH<alAD1ACBluH^2EPurtgLSHPJ}bLDoBEc1^4q4T8qEn04zGKbU3
zAlrO`UT&w&U(${^$E?kV7iY{V6wApqe;0yQp7|4c_~n}~H&HczfjRe4C>EM0L~yal
zd~^>;vDx7Vkn`r2N{|xse2NyAn!R6uPZ!L#M!;M&Uoiou%<M_|nR0U_1@14IZ&Tjj
zvbkFWa>e{E?SCrFhxdb5X+Av#g{$UiIyrgG?0F45YnAzL3aC|^uTgbijroH=!K^j=
zz6EmK{J{`9Z<u$|iKv_A)K8(&V1AOKA&usQc|dD2XHvB4mf1pQ$eYbUbdsvYy!13k
ztNF+6n7lUghaW=kwmEtl<c@g}okVXpPyGXwyH;~j7ToVJ*MA1mX`Xn1fp(csoq*kL
z^KJ#Od(6%sLbTW1NHryW=CAtE>NmGiJm8+W|8*$bH-Gmecmw9QsGM-nEYtvO$n0DM
zkzsR807OR2UwgrsQS*K(au_pjqiycE+4>6$-b|Ri=nI|?&364zoHEy40GT!~5MmTF
z=EJwpnl+!LGZ=H`WEZsTEL@bLF0{A&Mq7Ue%ZF5Z>S%eKesm`bcLa8wEpCg@a<R1i
z1Qb`xn-ni~vwXP(>h6}puhHpYdDN<ajHhJ*2QXfie{jBIp|{1GUa>xw=!ekowR{l=
zyMC5=6g={`Y^8;AfJH`&;XuoEdSwJz4qry+5liDzw1O>LDQ+2J(Nf?c)Dl?@y`vV>
zPIMl#<UE5`n5C1x?+|Vg_gi5p!ooB`G1AgngI1KKlD6*A7H3+B#aPzTmMzv|7l>Az
z<w;t`##?f!ZY#lZN(<0L%NxZQM3UuYT0^8**3m6~!gBaF%%@rovcOBTT&HkRx+Oaq
zdKs2)1Td6od3?iTxc{;&kFSNyNz3#c#&pWEkM?odmP~q<owhWO!<ih*@07tkV+o{-
zCf5=g1<7K|w$%VVZ<(McQ;Fp>dPSC6idis!!4i8Byo(lD64c8rQdi93CCkJpL@ryN
z`32;PMSNok?!O94+b@v0YFR>S#cLM3I54X$pHlv;+VcL(K&!F5OFu=OWs=fT^%e;|
zJg-~2=^=K*a_GMpgJpuQ#|F!yHYhY&c6LLg$?{YKT)Sm4JPq|`%RBU)@)pax|AT9-
z7G@y^Xl=9fP)_i+<v4v&;*RA{`jAb#MMy!(yOyP00PV1Bru{*u<uqmbx-4O|*6X%B
zwg;rgvT6%Jdo8AAAbpm!mC)<An5a(Rp5^8cJiKp7qU_;-Wlt4agO+9yT0@qn=-}C~
z)sk@#=0_}v^nb^rmS4&5G0P=dFN|BJw!`3r<#YO5mxq=RFMv*2KBCR&v?Z5H=4UL2
zsN#3lQnCz^bC$^%49(8Q$U&#Q%^>X^9Bjtr=ybH%`6Y;xjdC-<Tx`};iHNI>mHi>i
zyV(R%*3;c4iVvoTO$q%ej+c!Y_4Et9ZT_N@#6C7=iro3yye<XL&t{Deu>Ec3mcriv
zo9naS1==hSf&|%QP<Z)>&G08M5p2`l3g{4<LfZC*+H}sM^Qg@gT7)07S@Q`6VZ&^E
zUIYoZDWkPhgpK0=99?%@mem(8%Z9l!Q%lVprJ33E-Fxrd($vZ<wW;Myds&J&KtT{e
zwlYM9fC?x>hU^WBAj%R!Q9#);e&6%spYyr*p6@y5-uHR#IOp7lWhezP@@OFlW<&;~
z6v9xf0zQ<HH;PgiBV!p#XBg^RP<WP6k^zO`4A(A@2*!kcV2NZ1z4V21?Uq#h$}x=D
zKcXp?vH2iuiDT?of>J!=_7<p1WEeuw%_K%GorEtkz9e_&B}VMWFz_<tBOc(%jGPW|
zrZVpBM(GOUnjGXRBlazDrZIMZ2~*M;LFA&#WbhsWca1TPg1T7@i=A%2Wit})pes3y
zUESch&iITxS$T}M8!#rHk$Dj;1&rG?1r;(zDfCjrh@^N~G2=O!I!hSF2Vf~>7%AJi
zjB#!bgq1UVw?IV&<H7$AH;k_+t+a|!EQjc7Mma5XHH`Js?2vYYG5sF8c9Y?=0Ek+K
z_y1Fa8QojJQ^&YVhm3m0TjU$L&2Xo0TsJTtuLR%@V?Kq(?lS(PN3D?&N@0p7#tJ$K
zH#6qvKy(XZ_9JwumEqC_L+>$aLLjV-F^~ge?lZRiMDt5Kqj?QjI~ZYKqqdWArX89d
zF}km#hmRSoRls*K4w5gjoAH?vEIo`#lymx&F;xIuFJrX|m3@qlSt#{0_I-^W4lur{
zho&LM?9b6Q%y6U(!)J^svmj-JF+|Baql|F8Hu&#_jEi(cb6|ew0=<sR8Z$~x%$IKh
z@60UR1uI;bM%sbwXJ%!C9AIXA3TduP4TS^_GQXtQp&PS!7I24{-@S{{VdfWCL5?te
z=)pV6^e5l8J97;M2t1f=^udB-%&!YEB=+M>&MK(zWEN3;(u=u-@<vWD<0&NI&HRKC
zGkus>@*(>q^B8^T+n4$F7648$i^Z_lkGb}3wD~jVY(wcZb2{Dl2w)27*cZs`Sq&*c
z%q2e18_b*}24@J<J`bf(<{okip0zVWrU4Po^rf`&2&NmktRtD<`~Z9uv!DW+&M|*j
zkIHB!!wJ9`=CK{%jAg!;kIFdaitErD&uphv>;luwM`Z$2PVUk~=0AlX7ny@r04_17
z(NXd;)43SGK{9g|og-41_PrEiN@e=|4swP03BA2nnc1f?vT4jGg(#&neJCL(gIP{F
zFxQx-8PJr)Tpf#2HuC@l(Q=q>6y3>X{`owlTxZtM!8VWi=QOA<U~b)r%0lMpB(M}Q
zXVWxO%<NhPnI%kyy#gvqnQu^9LK!oSqN^3mujuEhWVX`9kt*hElc2Dg`P)>m)G&o_
z1Al|LpaZy@%mtAkx0u2#kUFNU3M%TE3Yw~KGutMhvVl3d0hNu+U%!OHCgw*)fHyPe
z&cLX(Fh^6o?v_rpZwWys?lFI*Lu(uJ03E;DnH%!}=wJ@e`SJm?g^oB6nJ?0ZeL9)n
zOoT0um@6m~<}ovX*8FbfwiPhGhZ*+*N>7+k%K>=GY|jV0m-)$Il=_&@ydb)tIhoQc
z2bc^B77jAQ?SG><#H{y*O~cHcaX^eP`(^0-C^O~`>>Xq7nT^VEW}GKfIIuQ}QR&F~
zoAx+Ptc-8K>B36%fwcXsR$p))V9h*_&bzWSl<abl<@GB>yRot!19ylOGzxu3SdZ4C
zbd>c4i!xT-S!dn>!h`kieUy%|0_j|PoVCIZpeHL>0&;@&Tp-%KSssZH>ciSXXQGp=
z)TJQ4tk+}^>d$f_x7KOaOiIQLU>Vy`3S=$&1f~VCo;-r}!K}|#Vt_(eaylf3vGT$w
zDd`Mrbr=w5S&Qgfq~R<lDS#2I+6GicvIeO4QLHJn^N(g#MuX)%t92Om#;~$GP#Mem
zm6p;tR;V7Ocvey!+Agpb$3S5MYn(Q=iL4GTSdv%^enihMvV7^KxXe2J{BxLtl37z|
z4oYEV%t9|xS-o_sxWYPPz|VD+^%LE(N@F?Af=wB$19aZXWWD$e$Tb#&yi8fFp<oO`
zHY-PrQVwh5aj3{;Io5;Zv3%~MGM{yZcJ2kNnYTd-S+5;JTM_H4FpP}7n04VR@RYD#
zJquFCa*9A>Icpj1b}LveO(2!5LE3OtvG}K8#SPZT9`x`gYsq?;R?AYo4%{u)D*84+
z9jhY`mG!Kj=tOv%wL1gk4(t0Kkh`oKG(e54FX>ip6YDQOsBgBj_Bld!3oGnf;9FUC
zN?mPZsVN=dK5H`Vo!ePHZ(@KtSb8N84_LDYVADgE!3m_3)ksdrN33@jVYnW%)=;>+
zi?yFz4Be~)v{F4`?V&m3DT_}tQZH*p8m#DJ71|)WpJl&K;j00b0~d{htOr(@Kg{YB
zqNC4PukgS+!kYaDSVvip{{iP1%P<Y5jkB6;u*re_PZ)?3yPOU#&TLOguySGVqfOO*
zwv2w)1MF?I)p2F}F9Gf#`=?()4zY)1Xgkb)!Tv3PN7#cg;5o`pD1%;ib_AUjj<a(&
zq8FZQE=Bvi*qgk8IKkG;Lz_3-bvo?zVShv{C)sb^f`zBpX_VgV$KK}%fImCE6Wu<|
zp7b^<1K6wezy-2B$Q>5M-bf$G3}GMql+O5}>{`lO3}f?Uu<Z=H%^y~rW&2YecQ|`q
z9r_f(PNdCPBs;qmB#Qk7&06Q!dnq^+&91h9C5C-W4k@whO#13U9D8yz?2Tu)(i!~%
z+vI|_1oo0?FfEaN`w28$WGlz%{kz2el9C`VvzN9*S~B~ke_?kD+eCMDud?@i3}71D
z(G3dI*^7$-%wUHQ$z;3G(f1mAD_NMu_Mlw)9QMDIqLj<NND+<e?2-nQ^4JUR!t8u@
z<2sB}0b4?woI>`Fcj?A(F?&5NY9;J1RzplFd#Nu<Wo#!EWS6r~$x&Iso<p1bO7?H7
zVMP`DcoaxAyN~?XHSE9W?0JK|^9``nvNtjTxWz917V7KR*EXU{_3YVuAnZ1KN)mqM
z2KIAw3HlEE!~f7`Z)ESN0BaLlOWCQ-?9H@+YhmA|U3x3~_#N=vXD9APWjp(N5Gp&^
z(&wP?0egUUv=7;L*}!$OJtzV15j&Io-(Bp<k5TGo%e5dq?0UMu`-I&<*IS>mKTQWq
zFZ<#q!29fMKZ+U-us@|GXOLY?iJ3#}g|lGkF#9A0>z}dblb33Q{qP>TJ<8rru8lGF
zOBB5uXOB>-p99BEkEJ6g(h<FP=Cr*C*)E)BD}?RmR8kD@0B0wym#!Qcozo6-mR$$H
zjboRR2kS6rXdifvaCR0z+EEV20v>lx799yaIP2oU;>j7RK*@{q=1!DOaF$U3)|<0=
zA#C#D+}jF;CpinIqA$Ljqf4RJj}uB6PW~LXH$YBvvNWg+;J8y(Y#?V=6MlmrPP1JC
zy}_KlwA%>foDTzQ7-!-#kTaYPT4~R6wvqEDoa4V1_y|sEJ@Ap72HJ{8aok@4?i{C?
z_Pf!Xjmyz?o->`Cfw7#aw9|~^e5gPvo@3bqVHY^FX?v2uxfloai5&MqTK|$bheOfr
zOC06D7?aDKnqiP+PTmn9QaBeVLqC=C+}8l6aegKzNIHi@-tY`g+neZbCTBl6$F6bY
zJ&=;c*%1So*_>TJz_c9By(uW=a=g1i@;GB3fF+;9^MFkSoNZ~e2QTE*ZGxpmoV=eQ
zyM*)IIsi*KW7{FLjN^U_zzU9umi<aj7u{T{;&_msw3>66zT#2C@ngZl8=QWM`QPL`
zOowT=IF?Y5I?l!!z}0ic=+@_L&IY>c*TDJfMM$~B`QCx{;CDGM9YHUeILtRt+sv6=
z2t*6#g{`oul~YS@<$IipnJBe!F0F>b4$fcn|6m_*tVba2A!q3m;5s=OCU8FD%zOvJ
z9&?%<z}dyw%mzz0hetcb9!}!VAWu1N<nHX{oTts1y^rHbKC6Dt&<4~Fa9TScW{BfK
ziP6KH6_n`ljPvtbkT%L$OELU0&VTeEj&t<hXmjBHa~wa6BX`;pNO9u2Ov3;>bMq)L
zv7Z~#4bB7H?UbwI%C!jqILLjTvPRsv0d){|$j&`i2u+8%4m5=y<@T-tt2=jn3K~7Q
z@6hUhjJu8|?c?0l6s7UxeyxWXZ!Yg7N<LhpJ4`#t{nrg8Uv31s(NA%&$^r1>atcuL
z=SF^y(rNCQRu~h&jV%E@h#OS{D}uT9nO~w9!X5nqJfYkenwZ15D<7a2XSpuq9uDVb
zM}S0d!|Co_6!#W=o#GsK;49#xx%Kqjxbxhnv`LHME+Xf2EH`d7;Bnk4J!D?s246%6
z6Sz0&{Ym70LibCPxZYC$xX3+aUj!2`aW_Sw_A>W)8lI#Su6YIUsoeZL;IDB1c@Z{U
z<^E2~ei~P*LS;HvME5GLac7eIJ&T(;7sh0BKV_nn!<Et7l*`R)2D#4loez8SxM39U
z&gUkc14{vS^Jc&cxx2$D##F?OVxX~@8%WomOSs&nFs77is)61zZVkl(%em_)Y*4{f
zJ%tsOT-y&IRos9;;HtSj-5@pGJ+Fb(a{s1d<1Mb@F4Wg?=TK^JJvW4sYHxE7hC_V=
zw~Njycera%z{ZGs(5s?urhOu1C$w+_cEO}p?qOt$O}xh~A}?(lH<Ge{?{m2vh;HXv
z{=*n_aP8T^Kj5nA67)mvg}(vs<Zh(rzl*y^0=3;-uTYeFxP25ff5Kfh1;6!E?n~#P
zy_dV{cWCJ2{_;6w_H+NVyF%yyH-xsBgWTgjAVb{UDL@Q!KYIu(o^k)8%#smq$W4$@
zuGd-s#<)*?P#Wik?t~ZzUiuaYb>s~#L?@hhvjs5CnRlBGtp|AbXm{hv+emkr5AuFA
z1MbF)z68;Sc)xBYZ^U8VM%ths;T1hV=_v2+Fo-+PNdOfdya0L}kMWcrK#V7^a~3MS
zc!}gIKEeBC4v05z!Y|O|!?V-!b&~fF<+S_q!pVntinoz=H-5Zo@@f0?(i+irn)muw
zAc4GSe~PvT@g~#3IGA^qwrnB1R|^3Q<z>HzK@8*VppR3W;l(CnWX|%&PNIk5y!<f;
zjo|rxfVN29k!aw~@eXf*712BfZJ^Hc_V%GmF}$f>5FN|o$Ux$F!S`WBJZ}~4@-Ohr
z=jhuB3B0NEAuW*?zZkViJPAEdmwC_8ZZes7f{Fg7@MioBV^VpO$TM?=S3{X0S9wS!
z!MnjzgaV$<TT4mh8N3?u;$`yI(!z0#*Zvy%lFf5TfY~{`)f-Wn%d^ofuIs!hL1?q*
z@!aU2>gDr}`~qMBFXRw9TFARh39LoDFv=h(=B<5(wi4d${~s23mGdy_<-DtxQCYz|
zN<M~4Uj04bs(86lm{!fp-VPNtypSp=yuo8!L+@|$X3^FDTHc{eV7bNH9}JdyJMW_!
z(AzxOix{s4-Y@h7-r=oo1Mn_y*dL^k*H3r9n|Mq;IGcI7DbU-(+x-Qkweq&ons|?Q
z#{_sgZ_7>ese|_iZQ&pAG<5!Y$h%De^-i8t3-X93o{KSj%*#6fTo>=N9tsC_^X7hs
zUi9#GQ)J)??>~x7_3|cs0-iqJ)!Q(*pLh93s2Je6c^$hm(>^T{mObNDk$ZE5XMPO+
zQQrQ$FmR05{UeA2zmsyI9QmR9!Rf^Jc@ILI`PGye<-(spKEeHbpR*tb_yWp3apf1%
zwSt5E3>p|Wezg#y5Ao~L!E%J}OjGSq{&y46BX|C5cDhsL!QVCj#4-L1dH|2}chalv
z$)7-zju-#x|4$D5t2Ebn^Is(QpAX;s5yYJ0_ntw?kH6y`^v|Dvp5nZx`BTq<1n{?0
zNGXuNZUxK^;-8>ZI+*{$5Hy7FB{aW;@<;!mB$+V&bMHXYS^jZ428Hv7zXWRpU(^X;
zB;WlvsEFc^j{|s)ZzAVdG~ex0Sa_a)m<2!#fA2|1iREvc4O|>wd;=^O_}gkxO5i8H
z0ZobgU9@^7@n<KXbdmofC4^k!e_Twj?Pb1o87xiaf8h+FDSWqf2u<ZDuLsW+ej*(=
z)A*Wgz^C(h?a-9L*V4cC$>cAgTSeFStCLZg#Wzx}Wj4R78!B@6??-~<^4lmu{W^cz
ze7qWY{D=PlP{{9o1bs#P|K`wt8!P62M<@3Zeg(bnrTj2jh06FZC&8F<zU>TzR`7qL
z)TT=QbV^;W;%}l=zM8+W7o0cvYHtkCP5v*m<EiDpTm#v+_}|mIQOCbScZ}-!A%P&b
z`FVe0L>u@DI;Gy>?@R^2ewSZBGk7CEG8sJ0{1;k4TKI|dftyx-`AxLl<9|!HVcYm!
zv@f{N4<A8gJAYmVG<ERLMPj%g@UKu3#zVevDp)%CdHccgn9rk^sf+*kPiX4q@3@9e
z^zgr-q`D{kSN%Yq+WDDu^RJixDqRik<Nv(`w)OLc8-X9-XT||B$hVO<?HT_l9Zp90
zxJ80@g#QV7(Z~2f<Xao(*IoywgW&fAQ0ORVBnzDcn-V~r1uFsocM)u%6rcTqwJrd-
z3jSJ#AMK#PzOD&CH$gSMp@#&|hk*64AdNn#bwsdr2@ppG*W4l0U2wz!7J3L`JJ5Da
z&`<~2#|5`&2KEw6>Hy0LfwMaR-h#2mknJO|ccJp6AYc>h^%YECiqa{;64K`<_<=rc
z<}Y~D{yE0^v>^5jga!zHipN+43BIG0#$Z961*H(dwC_*~70jm4P?+GSS>QY)7;1)!
zvw{h^s0<hUM{{0;;9d{97AbHce|wa`KugqlfiwBNV+2Av$HxlhdZC|j0_IF`#tYUD
zQ%3Ivfd?JS69i><08A9DAtzaqKp2D4MZuCcAm);QLu+ZWz;O@oDS~e)dp%Xa!WMku
z6+!t<z^@95e@36u1h2dandySkf6<m95EX!A3jWeU;WdGT9DZ4XRykO51WhS)qa|06
zOBwao1=dp_d4joR(3CGorFFhQP)?Ud3kAE1fG-jlyg-TtGY^BaM8H^zK9vg6p9f31
z!1-0!TOru89&MEZ)w`&y668+=OSRx-I>*-tCj1I=L%`k*DK`c4v*`d)D@ZRz@s?ok
z7;LK(DD~(?gWxIMdA%dpO#98d0`6~+-7I+RU$nId4s+1^RzbQaNT(o-uGc&gOr_(~
zW5JfE7>h2!2lJr5TVQrWsYj4cGsF|YqatW{D%egbcD;fZJ)yzgCn)lQiT#4*IVcVY
zR(}GXK|#a&s2mbZ+5^^ML1Pr~&jgWys2maeK>3lQf~LO!7!&*v1u`x;^*JgXgr&y-
za1@T(!RaJi^9((67JlW6N*7_75jO1?PNeYK0pag*^u^UK{MQo-4+<ybLyVj7Iz8lv
zgxa3~JS=>E3A%kmIAI=Gj|%m4jnG|~P3a3B!bvp29TV~?7<*hOY(=G~@NqLrUc#7P
z(RM;O@pr(zg>!9a^AS4l!{DD3dR9P+uTVf?+fzb&DlN%=!qxOM`wQ>WRCrqGItDQT
zLO+_s0)<y!MO%<?AuZ*>LYL2Aeu(f>`q4v$yD23&O!$@>LeB_KYXCSa9PR)-TsR&A
zmI&b&i@_2p6n=mqi4s1bysmS?KysKz3;(cR1<!fmG|CEy5k7nmz*yl%C)gb)6p6qZ
zFASqc;DT_@_xKGGghw`kGg0_4&3Z{fC4H;wqA-jC3zvlPlo5GZ_)#?~lZ8J#2V9EK
zoi_5R!s7{GxguP79{SRSmngwEL-<tz9pE#CcG_KC6P8gnLY8o67kILTvks#zN7zvc
ze6CQ~i?-`R8)ePs2|ee*n0(>38E7jIZl<}nQ21*m`cx!bPMhvxA)9>UCBj1b!c(bG
z69{;ja4LO$rd(J;N5KlAD3#v7O5vQ}P+KM3ei^c>g^MTxQzLBihZQ%3ziDCjP2rAy
zRMrYdD3SA)kg*MbI^oVih^ZHzrKs_3q5e~}H3+@`M(^(k1(a5OS6H+MRx}FNEQ1wI
zLYF>hXcju8LuQLG2Oc;3#8%-Djn_S4G(8_}Ldj7y-WPV4pwuq3{0T7~!tHb`;(>5e
z5jy%%xNI`oI)xi4gXNKM!9OtOF`i=>(<Pik;iqolswUXfBdn&4^%G&oTmYU5Z~p>7
zuTU}!mOkO@!%%DQ7p}bm69<H|p8+u_TtnW7A>p^w!(m|+1#q4T{lw_ni15)3u#5`5
z&%=r_;d)9^8yDVP451F91=RpJimqJ*i<4;PyI^q^&7%d=MN~xJhS)E9gH9y}MEM?I
zaTR43L-awrX!<G?-9(gDKJk#~GfG!HEK2<y<cR12WkDPjU5tUH$3#W5@xvY$O;w}P
zQ{<Y1{(6bnH=*f-=wk|2dW&M+(dHv^uR)hiil$H|imzzWJ-|<iPSA(e{6yOt0q_@D
zX^(eWWN)C)0|khl(R&{#>aT>*Adx@i=md*C-3*~2BGGE}K2(%9g0?VGIXT|Xhyt^~
za#r+^T!i7GKxdE$QJfGKMv8JMi6TmLmi(3HMD^s>iWVJnM%#Ij<4O!dj3_b{EU_Y?
z{XU9uq8GLUA1~6r4RS&B{v60o5N)21wnUNA38f^FX&tP%C<?_{XW}JMHYKE77B!Mh
z$)Y}*-cv+jbaNtA^frC#;fhF3sS#I2*U1^5CYtj%Skgty--8tyqA;5DvP7>m(WW+A
zbb+pF<cN$K3{9@+FPb8*iyo45J5TfjP1^Y)UrIqK5PeNcY@z5+ij5VC{$2!JvFH@}
zSxQ9f(!g0N+R}y*EfaOofvsHhjN-->qJ3Pzt3?U40M&?UC`NQc^ouin^6RE(&d<<P
zE0UFh^_FPL7Ras>{Yi(EdXXn3Yu*-3wxO*-w3s6KcSKuhk9b$~9R4OYiU$3msY%pu
z2<n?f{jZ?1MHH=u%vMqN3H0}#=wo`u+eGPn2)i%p2tuh{^xZGC|LhPsOu(o=5Q!<i
z|4@|wHX1ucH+};Ck?5CCVCiGgleN&>C2FO_^KQ|f+aa_^WW9&d6VYV)4W5b)k+-N<
zRNMwBeWIimbhKYoN_i;*qC5s{8Wd?ZqBJD>mF^o4i>y;ovOg2eS`PIiqT%ZhIx32(
zLPy6$Y%lPPi*CoEPY&XE56E^Di>3hKBtG#odf_ZCprkq%u`jKL`^7zuz#R}re}^_#
z@lFcM929?d1OPX2-cRV#A@SVZu;Q>dou<MgV%G_PAGM2xr_nWcaV71KJj6UoZ8|3A
zZ2>thuFglBr&v!hIWMv5Pe?l<z9Rt8TfFHrwE2j;E~4_Jcq6TNzT)j9<&=1k?)LhL
z55|DgU+hMaveV-3bFd;ntfA<2p!n5UXbTeCzohK6V6pK5NQgL{_7b6DU&@#Z6aO0o
zo^bJ9nhYYu-V_mu6yKy5AWD3c?n;~!FIbPtXz{*Rq4&Ia`!H0*h~Lt{v{>;O$|#N#
zM@<B0ytp<1<brq!`Oy-@ZNEWEqWFrPP9#a<L&*?xQEZ$7{3Y=LntLycH_$mQS?o^-
z+!S#c9l%n>@0|s?B0fN|ysP4UFGFvdxU(OX>Efy-;LH#^(5=`^u{<25YvNPs7`!Yo
zyBs82{ACbC=ZKfkCD&YWXEv>W*TsvDKun(aup=7t#WwOG6^NG{hKfRQ-w%*hB$iN0
zak2PC%7iWv>m~tTDqhuqaV`^2A*Xt|_{SEoREXVk0jLzOtw+zQ#7v4?SBothpr}U7
zroD8nxS|mnZi!c1qyP3^Cl1a6uwMMv0W{tgizuzFL41_HhH*#SQU}(%;uKnN8^wQ9
z;(3#J#%r*mS<Ip6U5j{VH*l@uCG=d~6W@x2O>N=?x?gi&9JLyxT^zOmL)jr7*bTq~
z@q~paJroz>Rkcs-6dxj&_apHWx^VJXJdIYDE-`-!%<mR2q%BmBIO#i>|3ti~5iC!|
zz2j)>6?>A4q))tog0%f&F$?Mk#1|<IX;AzDefwuf%u54cSlnbm+cWV73J{ElM=1_8
zD%Ly#&ORodbQaRa#hWP2*+KFWAB~QZ4=AeSB$;W27-vaaH`-hzVRX4_zobJ7zyZm}
z6pD0})GP$xpk#b4^twr|27~30WSRlL!C}eRZ!r6a<l0vdc2qJ(*$M6vCnw-MBwOA9
zIcAqsKM%xlN!ebodP=hB80aOj(F1WpB29sb-je&|Zt{^l`xBZ@O0p<$<tv#N2K*_>
zK5};XNeXDX^Op?rVA^R(`g}+UkW3mvTc9M261svU=1+kOmaL=wREVTw5=f}Tex72?
zVUmF)G@g;Ha{=P4WYJcr50{)G_kV=s(p`{q5-YjRq9y(e0M1L^qs2Hza+RD;v64<o
zbBU8I6oAA_A}Jr|f@D`T^d?B|ID#ZfqMtxYlBA5Hx)&v-^nrj&l3n%;7<^e`BWFXh
zWCcZ+QX~#^#Wz*5GYMj@NNU|du1YLLz^6%iYoQ`t@(sBWGbHWgN6D1@upDjIB!jPj
zWJxa2-X&YoBZP_^$@@-_nJZaFLvmfRvJ8syBr|F9%9kYnKyK3lNf{+O6iQYfhA~Bw
z<ag1hV#y>e2BAdq>I0}KmAKFrs!XEDg)!xlqnpsD3Q0a)(XW(z^Bzc*WQZ<<RZDs{
zfU`y-j0DRK$tqfmZ%X3nDXEpXya1M4k}BE++?H%mlmDeb;z$`EcO+uUY`H7p)3@9j
zB^Pw4Y?2sPfHX^foCFmu62of{+A7IBj?z8Jq|Ff1Cb_==xcidx5zy2w`Rf9H*bYfY
zJET02%zFVndnhS*6{J(*PT4DuBok;G`dGqxNbg^lr1C2ux+OmUKz5JhO(Dn=$xF_V
z_EaLEKy0t1G6<zUNfhlt`Xvfl+6N?mra<qY#PJ3yha{WIL53x}|3T$5$(Kw3MkMo}
zqQ9e(g>?63Oj1jo7?*5IhCT=B;Ons7?kGJ)`#~qEm`>)-(%KcU+eP|4xf=INmE@Z_
zAl*g>3s-4AEhGn}p$kFWq$3{ya7a33KRR<*dLst_cj^6wD0xVy?t~S`q-#?FKQ8^4
z5^X)DQz<pkORBt#$`exM9LV&xOOq%=*GJlT5kgN&|D%6S<SSJhVcRKb<zuMulbWfc
z{!#(0!l$KN+H3_#UBb}cVCk7G2n~@|h@c`=I>ZKNm~;_+GUAMMG5IRaN}bw4!lh$n
z&=4X0wH_o=Iynu(qNMf@Y56`Uwb1>7XsH*)YR^kmL}H{z;?Nc={c05~jgvNoLt(tM
z;CslvApM5{D-xt9DRCoF8oeAWNz#4_HC>cuc)*xTQnyC*?6P#T6qU)+x9&n%iZuUY
zs85xKcL8@rI>Y`6q+ONv(xjUvt=J9~=~BN1;K`7N*8!L*eb*B#*QDRjbCo4sK>uhW
zTdJk`CP%uLX7XHV%4g7YUAl=pQ+d)|OHs;~4$?$XAYF7BG7F`ftN;{Az34bqEN%J=
zZ6#9KOj`d+rAL>*;4<mg@1ai>($X5JsFc=E0;!VD{}OH0(yu6isYd!;2v}}N=TUU^
zrc_Izm|E$p)X`hgSIARSCvB{QihAiBiizEp){x_~K|0EYp?9Q{Db9XZT0u`jqjcgP
zN}y<wK3NBRt90*8u-=pM)ezby{k#PD`_lb4VSc-mN0V-cw0|CCKalp&^zl&2jDTsK
z((S9z?MG5?${>0yWs6Yik`~h);cjV&0m6Eu{)-^&iS#->h)<;|ElR!8@SWs;>61#O
z0QO72O9Wy-T1v?ZgVO&N!<ZrI4|22(ODBE-yPrw@oFHvPYQ73GD)p>{rZK6e64sAP
z1;r5RAnQ@WLPyyeIsrM!&XHf+S(Zncpf0jh+8*tfo&N$d56JetfJNNyD*KoV*#~9s
zybT^V*#N~24#`YEg7vWMoo}Gxh>S~Kq@%J~6Tspwd#Mt5580FVA^Vu@!p8s{msOI3
z%Tu-`9h_dWo{JzSWOph-yk#0X5%|dTBN)n)GXD~E&{vjo4e(QT8EX-WezJu$wfM_~
z6fQX}Q$IyxfXt09Yz4{`lwuep%ONLYu<Q+*^Fw3-<kt(84J<(~!er$X#5f}pPe9vQ
zSw3Az50}MJE?9(YaR8)5%J$g-h?1?RHT9hA4+j9EWp*DrwV#(&Bmx*CoA?oW7%Tg#
z45c_(;uVm1SxOIBF337wg{B0VrWp7{*)e(>lVoS<g}*3k;-hp)X8!^my)4Ts0!fz5
z=t5hHOh{RUsj|Sgz;Z=)fPx=aW&cp}a+=K9{ykXJWhR<KGh{oz1R_)Bk_IcT$ylN2
zMV2g%9@bph>rpV~y6o^@sLYd{CBIF+tj-8Pfh;y2ZH2OpV`wXqEzLq(u}s{Awi4O8
z%V;Z=t*nBgGTFN^7|L=Pi;i&>vaU>uKUB(cDc7({7G48VEz6$|+iGO?5+H8KX3U1c
zH)Z9`K-9_-x%gpj$>#lpAGS`mVLsaGWe%Gm<+dz=PU{UaGbKOYktt~Rd{^c-09>Q&
zh7!g!$#%|x%x0OEK9$)b<4Ea}Qmafc89lrw^L-3_o9s0iO7~@(eugpavfLRkze5%m
z1M)!TNKT4}vYq5Z>y#b&|BEN{@q@z0vNtJhrAs#Td5~_|N2?*MM|PPWq$jeaw8lJ@
zZKrj<SN6jk2<wx*cY^#c{jw}dU>cD1{e;mQl)V{)-Ve$4OoWNUvMC=y+A~=PIn768
z&(Q-lD$~+lVoWxZ2chG#ZNC8LATOE^p^ox$df1%gJD*3%Ssqgi;v&E22@Chj*U>@s
zfc%}=D7ni2bb<!^L3zdNK)A`x>ri`0{-6Q1hvi+Lf*g@|E(QLmJb_Ld?sCmjuz1Kn
z`4g4L<eeVSdt9!f0J5jtlLg`>ANw3X#R>T;DcXGG)84})ds4nz3$uOY-t=yrlC$^_
z?I&N82jXv+zxfktPs;}>DJwvpNjGo<<ulf!GDz++3{AoE^Y>8-kuO*S5-Qh`uQ5!n
zAhXZNGxuUF&dU3kurOTSM<;>^xf^X?Bju0j>57sMA4Ip$$%7SWi<S?Plj6MmNi|qv
z<aQyx`#UjKK1iYNIQc<2#Kg<{&%(9~@|S4#NszDp2yKb-8Ec_8NxqmIt{3GS4xw~O
zzJU&Rm*obU<&))CuAr16_a`rVs@$*#Qm)8{Bfxo8K3#~mH2DHLho#HS<k`)TbL`|X
z&6IDUj$V`hNQqNf@((C;DO-Nh3`CCHMBDvb`5tokT$fKE?|hz|vkHKGxeIxX3*|4&
zMrDya&kvQw^63=FDv|H*0H9PJPG_Dn`S0maST5f)5yn)=YqC(Plz+>$!_q2w5B)OL
z@~w1EsF9aG#gN>PFQZ5AraWs0NUhwB?tR^o7t{H?PM%Ar=6ZQhBr0#qr^i53gM9oL
zaChXErReruxf40m8s(M$L1B}8B^TXpmN$^kuSFhDU*T<)e`%(VRNRxh(V?YH9#0Ya
z`|`!FqZjS+9gBhQkOxx6)C2kNl=AdY{tAVlI^_)dsM;fWBzeLg%fF-_woAV5H>l{A
zAEuk=J@O}VNO>X;p=bT6Tv!d8dgTe;0QAY<r6i$#`Mjcuc>f0Er{0D&gYt-tXdIG<
z_raK9`5X~=p2@e;?qNj!l_#til^<}2&@uV``(PQDKffIIIw-1tfH97WpXjcKi(<VG
z4Bf9d6$XU|6mxcfxGJLQr97zMu0+XA(M}%eLyGASV6XkKBI*(75yh<2;5n*z_%BNC
zinHW3^H40MbM`TXn$7^n6?^=^;;GQnMFB5GCT;6ZC~kiSL%kIvw4C`UGJL^uQgMqm
zyuON`8&P>mv3vw9eu_f68s@K<TMKepQAfMr0K4LY!)OdtY@#htkit5S#$d&#^&laN
z4YXAaRlJ@7X<>?7dQ;CRK9hi)RjgPH60Z35IgkiNCmZlcMU@Loi&A{O9^{-tNQocO
ziup;<6sy?zGo-{RHmyYm;}yAbR9;ZnJxOSSV&PU;k*GLGzSShfu@fK{6-!P6e@XFQ
zIml&&l%BF=1t$hJr6|&9@=H}Txng9lDE83jA+9R^rjbok9HnHgbVcGE;4&1)FF<sr
z!gC!euPL(WMbA=%{)4t`#YTG`fH{gq6q(IcWH(^cuPYYNX)sR_PpKFAiX(?nDo})k
z0$-@O+yy|9B8u{KiWMopgQY}qm5zF)3MQSQ%M|JaNGVrL@kU#PV#;kOtW@+T!TKu2
zMf!GYwc-%Xfi;RF|4)*?p%~$!@uuQXHt@BIk7;$frSNzKr8-3)t)}&gxM$FNTXF0|
zNNZ4V$<RBBH!eWhUBx%_#j{4mSAT)CNipLEurw<ISEI5;QD#M{Rbl=H8ty6HYJ|*o
z#ohsMb|`{(Oq`3COEF9X{7_+w2kBI3-9a8H-rnT3Z+xNsN(+Eb6%IV8?^Sr*Mq8g^
z(PI3D{R&5N<_;*zDJ5-C(Vh&ULyEN@f@N4y_6B~6XNn-Y$2+1}6bdP$iskf+j4AY2
z&^E5%|AJ09DF2!SoTIY&Q;eaL@&*mFvoc^B#@9vp)P4!T{mOMT>IamjHk4eIIsFiG
zP`Qit;%>?&K2#i1{!FQvhm{SK=yF7P^8mViRLPnS+3w2WaNs<YOK9ult86WR-c!m&
zpM&@*9h1T7uXLdU<7uVl2uur5#=H%Efy(ipX$1*Ves&y21uK;yD1|6jQU+kC@{6lb
zAEs<Qj?x+BwlN^iD&M0GT)6U}JK7?Y8Hwmcq%wwbi=&kHKY+q>%2^L#OtkVHT9eN!
z>w{1kqiiD&ZLHGt5jf+N>vw^~E7v8^C%G>ugWXU}P<C#D&_tz{b`MF)LzLNYQP~;@
z^_P^ZX!Czrd6Giy$x3b^SW=W*t>{du@`n_txT0+Ego>+5J-u*g%3`{=oUU{szg&iL
zZ!sz}m2NakUsG;t0U$@Y!%AsQxk_a<YOgCd()Kw|`G*&T<|{)f!dakHT}E4>vh66u
z6e(x9qODjtryi!2Dk~IVDO0}o0ouxy1#}spLit-MNTsr^9V)7ngJURFE7wpuRE_ej
zPhs{AWjpy+ZYo`E=!?Bpxs>v^ZYgIjMMvwDD=2VZuY8&Q3+HX+8@teUS6NKS8jZ>V
zimWy(!*2uMqP*k=V_KCjjezBz@^=c#w<*WTnR8#sxeh7q$|K~T?oc`eL-YgXLrQ;n
zsLX7HF`dd%>fj^0@^iYt^;nrpsV-g0fe9#eE05B*HhYvoW8itB6w?#@RJnxi?er?Q
zJc6`7<*)Q#z510q$59$k3SWl8L1iYLb%vDn<X{?Bo*Dw+nexIz7&@ZdORkPl<ysX)
zk12no@cp>b{vibi998|~>vvKu%}2>u_1QXDaX>XK2du8DvnA--LDhy#bj?k5|3i>N
zs+KL#bXfI=62x6~cK`qnRiXlI$5eB@A<Rql`_HiHgi6#37H`!nT9kZL68Z^Gsy=)j
z>U~ug?W-}Qr&NcRLWQ3yiykk3)$~7L_i0rCg#!Xqi{Ax4P_^O)Sb|h9lJhHA#q>rg
zMD>W?m{8TNcfc8@GAjT-qx$t#s5q<go(9q3s$#lO7@=BBD|Do4)*1+lQvH4b>d&bb
zw%S3XRo~EQ<GgBrG^E9->H{G=R%NG)LUF1yAHtY;)jbQuTu_~)H#I?}q`+*V>cd!+
zl2q-^(0fsJ^d*o>s%Nbbc3Jh-3lNs9;=YI9Cq-4g6BeebQppd0MP(%K?NwFkiiuP3
zcBoE}cQI2nz5Zm#i_gDdHy9u%M^#PV^2${OJw}JGtFjs(E>HE=n-HF_GPQuEK((+J
z`U_Rgw6iEuy>kSlSao~>Doa%F@&GSYeO3%rWhy(ltIJg%nxMZzweUPjm8#PxA-YNx
zHwe+ys!`gn*Qhjh`YzfH)w(DYZ>dJ<?Wj}5{{fzQ)i!KtCf-&pqmycbs_!%4@2KXi
z1j}93-aZIzR9&JA2TiK|Gf`?)ZIi*6dn(sx=xtNA#G<lG)%XEKcdK@h1EfcF=LNuf
zRl}6Z+NT;{PFu!))#p4k4yb;49<_t20b2QnR7;r9JEA(j2YN?U%V-ZXrrN3jz)}4u
z4ZU|#ZxaCEtPZ7Uv5R`v>uB4r-v0-L9Z>g>g~!xs3P?GwUPoV_^Hl$~4C=kquh9RL
zIHBJ0GKK8C)d~t>`=~ciTFOcF59CqsRliOndrBQF0jr-niCpOZ>LNPKo>s@w2{%Cf
z(=3z%)t@;-VX*oadK5y`E9h2!sQMrBS%j&@w3RudzV{h4oK=5HGfbp<W<G>Psn=A{
zf9W}=R*+9QTD@x;I&)r~K?4<|{#OgxvFglbbS+NpIve<S_0j@JyP%Hv8~6nENGjSA
z)l(!WC8?j^3Mm)WtI30SN!>yj;g{7#i&2@Z4*UXouc+VL3eI%(vpSSA)Gx0Ev1h7J
zuSD%N_1rxuW~nnKp!eD8tzIBG>Iia8<*Lu}A@sW1x)L_!sh3cuXTEx|KMXBU@2v)B
zp_)s(*&=mT77Q&`n|}qMM19l)ET!uDuOYfj{W5)lsazdkL8(H$v;}RIcJ-XYz}KiZ
z=Ylk-r}|(J@2I~OLepJ!Fr^PPstvj5MUz_h1o&pPoo?~9s>Sgj_tc5A0BBP?lZE%y
z6Ul?ou0BMcJLyo*qV4Ykb><?Fhw4XF06bFj$n*bL?QjP6cB$<XX@}pf-b~(+9(7SK
zq&-n<oPl_%E@*_%UUhyDOzTs>6oOK}nom3I0kxAK24P738@+ME>aEWp<(b-+h_(^+
zBrEJ4RX-G=hhyrU^ntE%b@mAm2hCfwEpyZ?A%BFEW`lh_@Xng93jn%kq7I^Vzb5lT
z@Ep+Sdmz+R!wE;X4{8kbl(}gR)`0Vn=6f-SyXK!Yu;Q5J71|RV*Zlq^dg!Tn7J)V|
z%`$%|JfZoW9L(OD^^~vRs~LF?ufr)#ANf)IG##7mknOLzrAOmw&He!Z12iVO(-)|j
zJ`+|1X?&hTTd*ecSCm3EHRO#A(|oiX<8($dMnUqk8m==~!ZrKodkGPm_4JvPNX>cL
zOh;+{p%C&p&5r@l8?7nf0dQWEIUQ1BH2FV}%Op<2p}=sw#x)qV7c@&lAtphSn*gDS
z8V5Q8UDV8`7w?kh$vY@r*34~&v}DcjJ+P!`qSAm%)nvYbzFg5nk-{`hBo8EAW22PX
z49yJ6ZOhbTe})mgrumK%cCs|zVlQr=n5~IE459g&;;(@(&?xA4D%6-L(pjWgMvjbP
z&BrwPm1?SKr7zR8%!jmc&D>73RcYGjqjJ?6KgtlQ(e#kx=7we)9jk6?F3~mATN-N>
z^ww#r=(t|5*)4#SJDPg>bcFq`=J-x@rctwP9uQ5Mg-?KQ)^uD4qD9kX1)^2s9s$-i
zjU^MD_cc=~EZ(m9Xa+btG=bztd7#-!8})~pBQJq;YE&~I?2+c1-O%({^A*LOdNh|C
zAoGc49-T>_YTot+XRlrJl`CZTX_ODq*ssZ>gUz7k_2n4ZAx)<hvWGR(Y+!k&S^YaI
zM>MKE7@%=Y+jQU^wBP>!z^e6FhDs;x`u|{)vvx7f*)H18gP{I^R{Aw$x@zBO1v#jF
z?=_g_rae6jz#*+YsvfLIwVYwFx@%LLpu$6Iq}=0UTGmbQ9M?Xgz?7#p`3oq7%Uz1n
z3GLVjSWara`ykX;8%^GkQ`+lv%JI`KB%g!7cE?+&4A3^610Yb#p^aRSc2^Qei1x$R
z(cMt(8v8UD9HxC14WrIz#ja3)RvYpb@Znn5Z!v6<+FDvhqqKFDSA0&}`#UP5wNt8r
zJFk6e0WL<X`W&XkY2BAYVZ1hsgk8|SLTC5{?Q}}pOVozaa9z@7T>`nRoq7~flC>|b
zqJ3eCc3>Dhsag~H$*ySINbgncM`18AO}jq@Bwf292X<#@zkMHiGqr>7!lrB52gR@{
zOS_6T8rj-;cOW}QyM6?EbF~k?LEClhj~k&OPkW~kQVO*7FQctc`xpJ7MOts|i&{M0
z+DUXYF44~KftXTl(+xD1Y3C&XU#|UU4-gev$LUaCseQ2nrd4V4DO6FdP5cEyYqa}m
z7k)!KeDaSe&(F2{{s}<6cEes6dRtpYsUHp6j?b|C-qk*$si9GuLUGF`ZPQn1Yt|-F
zgrr3~<73Ed)fPX3qI+7+Nwl?TeaJ6xU#oXS&)T)W%RoA`|59Gm1MPN-Ej-j_qyW&V
z&6<qTBdy5Z3;I~Qhyl{2eMpXhZf%k$%zmP^(w&B<+KsfF^lIC;p>06>8AY20wdGII
z`5|oreVkxeTS?2wGp!>{#3R~wzDEZ~wd`YP8`JJ0ck{S*G2J+G(D`gYo1^ZPzcGYP
zy7d3&AUW%b$qE<U4$9EmuiLFaFAnG!l<wfFThR}p2X))h(dMQrG{Ce&x=&w(!oxZi
z?QM_f_OHQ^9Mv5k1I}INNYQN%T^=2aj_LLw(P!duof|pJJ#{B&ALpeD*ah4PUG5c{
zP`!0Oy$RVqx(9UG`J~RMg>AmNm&x;gN_UQKw)^R>(+=BT_f`Y+p4Pekh(Qd{`LQ57
zP&b8k=0Q5i$50ro>sbX7rdvX5@fjV*3QcEqwK8Z3*G(pWPlRp*15zS&t(b%C6Qgum
zdIZktwtWQk(K^Q!0LJJdX!45HwU&d#>8jzbo|vf9#X@hAu51g8xv1-YjM61t4t*Zu
zvMz2LaLKx`3bdu@R*`2aRrhlqL|@Szr`tGJbyMl_NYe#vfv|MlIbW3Q8M<!{pfOVy
zbOW8arc0+uBul5K6G^u2&oHp&=v>x;<m!a8@QYm6_0paxPglzYK3^C76c!ffmM4M~
z>NravrAW7up1@+=r7o08bl)@sP^v3VfN5pAS83fV*PSA_Pla8#?Njhn>hkuWSf#Tu
zU~sjriK37-y3fhka6^|B3UX8TDIN1`bvK5g>6UIP3)1Rzy;&&L>zpXJ^tLYKUv#@c
zx0W8~JG!IKf#t65-zsQm)G5A4Ta&I|1u4zCA1J%HMQ6V^3AVNBTxUbYJ>BONoNv=1
zrw#9sZu1{tZP$H}hEj*FDhGq`KxgIw@KE=v7Mz{B=D#84kuHobl0DY-({j+I>$5>&
zx6Yq~${yX3S76!`-C{S4=u@4AR;pgz!296r)BS2UqOo6B_X@-e=(6d=IIMevvRa<$
z>S+@&qWduyWK^eZgS0VS*>?br>!M6h;h?wPM5Uwt5na@9(!Z{Ph0gjfXlZrPFS?1+
ze*N`1F!X@_-yJa9RlktF)^boknIepC`iw%FP!H+HsCZca(<BHzqF=cW<fuM&5lnN}
zzfTXFhu+%(Rvgo}{@)v_A1B|pr=CZ%w3og=4xA_SZ^fdA-ujCFCx_`nX&pJK_rR`w
zqOX4K0(9w=o<VtBe)=io4Gqw*aUvf}uwJ|YwITXe0rZCIH;q7OnEobBCTH{=v<p6~
zzfXRYaQ#V|{37%n<SdWW&z%UNQF;!Aj?d|hz97;1Xc_E1uYaFj-xz&v70iy+`>G%;
zPX9awX5;n0(U(Rp=(C@v4NZdn^cwIa>V4?kn56$!1pGz4iQJ%<^pD<0<z;;~&F;y1
zZ)a4d=(~H-wN(9(AMCxN-^>Nzs($%&l+yIA6eCa9r*MGF&@X=;m6`emaz0<vUs{RE
zEdAmZNXgcxkD?Ry9KG)v)aL5TJ0SGB-ugA{&eL~og2DOv`>VlIpqGCFe4&2E8|Yz?
z{@~Xj#rhu(gQY~jr51ov{k43IbD6%;2vV+p?FjT%===A=v`T$+0033`Q93qO>m&H+
zOO1Zk^Ju$a*Ei74{-$0}H%@Eynx$yGrN4d?_&UAX0hZS5HQUhEsGll<!e)I0xsO`(
z`ITsE)ko8NbWbm6fs{7=H?Kg&ef>AI|7+L3wE;cr(CcP_JkWoz5uDxn=tr>kiT+c1
z@Sp1K17kq+>X(-QKcN4l5-JAub1182NdK)Fb`R@2C?n~aKJ*k=M)aK&<{j0~zlOFk
z{b?tVas7KVXFC{@Xh<9l3pb+VWC$QfgtNhO72qz0@C8t~-_Ti)$^(Y_K@eBN6+2~~
z95nn){zx}N2%Req8TRi&*A5$O>5zTI;H!o)M-6SXKXErOUIW0xkh~Zwjv0jiqVl*Q
z<O2Xa4WaZvcp2I$+Izy#_BJZL4P~bw#m5j&k))G`Vl#~KHQe5Zwo`_Z&*?u)`5AUm
z*Zd9M6s10G2#ANm0K@Ad$PP5P4nk9q;hl+K2{y1#qB6w5PXh@x^zVVRFvG$BA1@3p
z-=cKZph&`qh8ym_29^jz^XsULG$d?*=qQ8F_vq(2!;E7f(S|>C^!}YUym=0G#~41Q
zTPLvwT>(g(p;QNj@rDWHzP(_$`!6aJ42^RjG|^yq6{RG@!c4SXG#uW6(j~*ogXrO9
z!!!!$CL0RAffXr+h#E*qHRumv5Uv=0C6`pX;qTob8HVqV(1#*34gG3}xn}66p~*6Q
z<c8j78#I&>n`5{{$K_l@(Jr)IH>{6DFY*kUSg_<9R=$VI0>jwbs4O(J(yfFdgJ2)J
zR&0o*r27)XR?6uvHEdr4v&#&VMc^zq#8Rok@XqV7&|Ya6rlV<<L3;+pYJ>DMAZiRT
zFF@}N!)*Gl{7u7JN;If7Y+eh6w+x?$f~C$dr5R%C4NvcZ^R{6!ZP^+Oui4Rd$M7v(
zhPrFePzrsc;oD!p(q!P%w9#z1N1=@tgYg>lwb~6o(9&_=aP?c*)^7OfbMSN+qVRT3
zd|=o_KH-OkB09lz8cIuH=p(~9N_cy0i2N2TU50CU7>jPhx;m7445QmodScN22hOL4
zZ5+t#HSowy-DhYak43*Ba6V)X82ad=LW2go^dqni88(rn!-gdCGe0xzCa=|qp)nak
zM-3zMP&sCpMCX}t!zqe6I~dz3?Z?qrR)|U`qo)}qXXA}x48DtTn-Q}28_S<S$^m0p
z7_4wLR^_AeppicW;%1BwhRj38MfO4<4jTi>H+#gm{0hVzHEJne!QHrZJxU(NsndWz
zW;_@NO~;L?S-^W5zb1!`m$CY7RGu(qy@Zmtv5Btr_!ws_flOcH+7iG|8Rr-P_cIpK
zhQ{9*Ku62d#@DWb1Q=Ix?C5r&@yJhT3^MvO0}*VTy$QC37?0mVWvH=)0svvg7dugT
z#(0SwV`q(t6j2H{rfmj^F#btjh=??9b^=S3@oX)moHsgu4ZShOEvKL<*0|>)EQ~Y0
zW&lgPamBl6yI^d;|Njp~8lSpCMWRt12c9J3G{RptZt(&z+4vS+&`L3S456b}jfd#?
zm}b0F0MpWq6_oaxVZ2How8=D9`=E5qSda>MmNDNMGP8|8<e)9bXp{q&Yn-zgEZ2=`
zULbkKYqx0snQxTPyk21ZaT!<(jZ?_OTV!mZ1eRhWYXVqHj6Jl$FEvKog%xGSFIR!H
z+;~L+T!nEbt*w>D1>~oyGQLd?+G^t){V3HK!=f<0H;gKZdEGSry$_tV#_qlJ8W~?d
zkCMI4_)<4`>W$ieKyDl30-&(LXrYvoJI2XVFi>}mEp&`)H2(At5KTs_3rMqZat<n6
zj5!p3Y&A}H0J&%U&;#n*jH#Z0-#5PY7E0~L_kMts4&%Gj&j&_38=Mb~kLE&Or``C@
zUKAf06H;K*V`JuAAi9iu=-AqA+`0>-$GBoH@K20MY;^mnv1A1}dyPMx$5`|kduajb
zH?~pKXuvq%9eM|iqX&Q+GNzF`aM)N#$(hfL-_v(BMvU7PkTPoQr~6K0MtcA`T*r-9
z4#GAE)7lY8b2k0c2cV0olJX7qo5IQUaKNPg3!JW|Pu>7IX!_$_^xn-hi9#}mOv7~Q
zJ#3moo5LfftS+=2HSM5e8h6vk=cx2BRnR8unCZ(mL5`b#r;IUA)1aMh_js8iI-%l(
zsbe<8c$=KaW9eh+q%Ge`Q!mX$z9z?HaGo-qJb{v*DUqf^f74G_P<h(a{UUGyrf=wA
z9cX%s-pwG>3pAexo3>_yCB$^)N3evN?#+YDFjH_G)SoelIw{6**5uj?q2Z>*6t9Ue
z1<_U}(o{bVM3m{N3);?`rqjn%VoX`5FtV|xpUJHkXX;JHAjX>>7$Nk6DVziK38r%t
z;Y>8$d5lt$Y3_0i!X*<k7?qbz?;M3`$tKsIfJ-seIFUm;)wJe5R9rQkUxC^*Q~6CG
z(oNp^P@iG){|;@Lre2CwUo+jJU1g5x*iNwIn&NLm=yg*J-RsUX>Elt#H=X_-fCAHg
z%ETx%4So-^i%c(XgT2M37q_BkB_`t~z)MZPDCr|gWhQ4mfaRv8^d3~0_&gvgO>29A
zuQL7F1VpuIIz{?xOyy@#x?!3+3#Q#P*(oMjYx<J1Zf}{2>Dot~$;|{|^(H?PO1Diz
zeZV!C<f~!*9n)+HD({+>O-8BFw3F^+*qcnh?f_4VNkjX=R?{#4f!sHJRsh-Urj?YD
z)M1)a55xmgAe~zunzobwvD4H`X>5;7cUGbF*i=OsXI-X>mjLKCZOw!gJ*K@y==KxS
z`d2WpeWr)0VCgr#Mju8SFnvt>i$S}olnMNhDS`%J*u)M2>oe21KgMFjw38A+MoopE
z061ofkA<P*rnf2F;$WUI7bPe2nm3@(+5Fy2%*!t3%`Dio-#q<K01lXs9)k*3^Ntv3
zIA-3l4&=D`K4rLhnltEfftT4Xx(kIT%u}17-rLMqLAI}XEd^munY+h<_cLEigE9W*
z?>>gY)8;?6f-}JU1$|>H(7d1mLW9h|(jBf~^S2aK3^9LCdx22%;z5+c%nb<QOgv+*
zE{Dvs=Ei5J3^#8eCttkzynQBs7tGZPs7N%&b)qv#=8t_*dC`1^BK?=lUmHO#n@`er
z;gZdfe}Xf`d|)wzrkWiep%+)o!Q>FTYHo=GOPYC%Qe@K2YmH#ZFo%&_FVoyl9=vO2
zCOKiV%u{H4lWmUZpzTVIxo#Yt$u%#ct;lsVhi=^FnQxOPJm0*M^cI*0DVwy=JmDnp
zMdqLfFu&Lw77M*4X4M;zU22Y_P;QyI<P!kO%{wWUQeloJLo3bEFTjc_^TK&xsW!hk
z5p6Z*k`L$~1>7+EQV`{)dA<d;wdQx}uye~SR)e+9-25pj>&-cIY`$Yoq}|<JbL<RM
zHkwz2gEW~llL2ow7oCP_E#@inKw8a(b*Q{&ZoUL#+RV=mqw>D_^$3hiyZJ^N+B(b=
z5FWBmd|*C7-^F=oE`JG)o#q*o^YO?$MG1wE%~$K7u*<wc1Y^3*KT_PX$1M6Dr6=YM
zd_0{`%^NO&rPo~d3_|<N^Und-Z+4>4#DG~Jinc+s@hjkl%-25$VAyPI$B;ZTk1Ybg
zK4L!Y3-zPsSC^r2%$z}Ih;eh|UH}~|Cn?{~(NcK@B`1q67%a|~mrnrbVu_|e$9_xh
z4zL`sNcUqbTrG_hD?4P_J{6_ImYm11;)vzA3vfp*7q0>5ZfU2f-^22EJo<UeZdp<X
zg~u)Lt_Jb6oTpg1mu15NAWm4CenO?UC3hlJ_*fDtvHqlmzYHpTEzc;4;gsdhW^~5S
za<>rxe@l!U<g_J_e)|B++)}^;EeF2<XOQJz3it(EnodAUh$WoznnEr1KntXWS*F(l
zc*Zhi33$$0Do3F(+%mZe21i)JLonQt7A|dnqbyG3Av$L%rC52iWq|x^=PjeVVMUB3
zji%68%X@D_MVzIm8lvMZ%{5Se!LopYR0)=k5>T0Fd55+@NfxEO1N5TBkz8VzEZ0R4
zdfBpE29j)vnGHmWg+Z06mYE;Gv?~??B@A4({7YN5G)t}yxO7W9-Kfs6yi2amOv_6&
zB-bpxq%h0ESp@ajmX`})c8;ZnQmk_=+69nu-D2KO0o^>yUL9oTTekm!Qh}xOK3EGa
zPPZVf$nviqvWqS0|Np>}Wjk%A%PoWS|In)}vIMB8wrrt<of-?5Vm~)5r7|eIX}R18
znYEVQ>5zHLlJ*;<)LCrLqf~F1l?V;DE&H@|2fD#>gRVo|vD|tFp1YPqG?_G7mQBUT
zHd%J2KuoixmOj<eVtIcTDqAg2-iH<UEL;CUXWA^coM6R$%Ug3{MZ0Bl1xg*3_J09*
zVCl~Td1$#z8?jD{e-kWxWZ7E|DUU77$LSw+bXgqYp|IO>{cmXMu^7Jv&lAf70Ze>q
zSvZJNuSL)aO?{R(>0i$FTV_xscfjI04xxjViOT^WvT%O{=ddO03#fl)Sy&5}5sSe9
zDWjGT$)z-AX&eGz-16u(5C`jv?}O9sXl;57yPd52$iKbc`Y)wI9k8yHfVf&Kc7yex
zwYnc|Zr1OzK@M40(E;wL)tz>Q?$(FodGxTpJre*=>k~S3cv%m9j<yrlWg9S}-q!h5
zX!EgNV1V<ab;eD!`B{UaVVb|)y7hfDp0;kH=_9~eL++G7>-|4Kf~=7iAcC#S=zI}k
z{f4%ap;kUk=wa3XdN<ElSCJ>-tab0-U<tQ+P#$xHwfALIMq2xKK}wW$vjaHKS+}jj
zkVIRLz5&kj)=V`<Eyij$voNHwRwsJL;;dt(kR5NGyb_fctY7mWEy21u6eQ7lq65Yx
zSySnBbkW-W5uUP3*3mIYyKJ@6Dw=Hlj~rAf)}doyNwqHB4`ElVR`Qu&wMNiBFwL4+
zj((<FKU;vx3~R3aH6Svr3DZHYSr@0l;4JIvpFy&%-_c}}W4%CATCVj$3M#K#U!ngL
zm1o`gF8Y*jJ^m#~ft5q+NuibH2o*)vY5#WtSUt$IRAQ~A|D{uEJwUHRnYE5wf92Na
z=tG+o*0krz<5FpjZ$@L4b+so-)z-bY0j#k;M_s#NHIjq*rnP-JO10LeR<zx+9#&&4
z>#T$H*^GK?$3$3h+j?sgDjTd$kubZ_DyK}fCM%nbwq|QH2e=mNK5|UAT7@(R-n0Jx
zl-|EK>!dd^827EO(ofND{gq^QSPu+C%meG!<Y|3q&7~bpr}Ya9q&>1e-T`Tkt+xvx
zt;@QS{M+5uEXrT&vF_V};d)|C?gDvgol6-yz1G_MDD_zjJi*d$o%R861J>JEmFyD-
zt$XNbJ7g78g8Q&_201>TSz9QHeZ>0Z3$S9;Iz$ian00jx+QzMgwD)naz48)la<pBX
z2TmuOGsV%IZT@s1ak2eIbKrj4?+aks0o&*%SmA2(cnQJ|+EzRO+|9Ok3jp>*Hcl=Y
z58KuYVbl@ZW%8OGwSD~`h`a4E<=c4J0x1A~%r<ojfX8i5;!yImU0VQ6UbYnSMV+uc
zy$WgGwg<1E&Br!*6nanEj3ZF!Yn#6d#+<TM(`muaCZ`#~-zKEnNT=<#(ID^y*na#S
z#Xwu|bnpb(jB8;`ur2gO{30PXzdJyL+U_MlOqgvS#r?u<PsqCwVRL>LoRPK?Is-)8
zq?KqpZ<Ejs#~52F&4KZ@PiSSoVEdPR1_?GV@(d^1&dvo%vf0C?L&Zf~(oEo!ZIf4`
z7b!LeACOerg?FLwitP<L16;MeFG7FQY?-tHOt)1~8cK$3E`|LwZ6!3nUbDq)hA~+-
z?q1lNZTmt9&Kw(`VnDgJuj!n7-Nq*8WS%XayuSIi3_Iml6xhZnPq5H-x&`<m+c&hf
z7TYB5s4TJVrJzQsZQdMImf5PeL2tQjpclQbu!WOzveLHfV^~pT8{G{<t8FjdLR*dP
zg)^}ChV3Qt@Z7ZJJEE=D)=PoATekG?0I0L|zCt;k^|nB=^tLTI8^8wJKNME}A4k_6
zpX2q#tF6+ZXwj<b&{pYCy0lbPTV1-4ckjLTo9_0F$dn+7EZJldA(Je!Bq9<bNRTB%
zCfOvB_4}URU*~i0J?DGQz0dRB=iYP9y>F9KXD~>!Q#ZX=x16dH(bnda&;WsUCkA~R
zZ#zY;1zLyGTRf0Xr?NA!u*>P_VsLgl{Ye*I^f>9rMcV6>MnS<lP6;$?-E~q1f%G|v
zHa&sgU%%6~A0aW|R9Opy2b~HEpm)e=dn_~!JGtxt>xh%q1@iZtoT%--QwB}CqfRG-
z(EBl`y&{N@JF)0Q*aN58_t7@t^lJjfdD6*i4ak(!9wwlton}6V*}E9+_rU4O_@S59
zpSu}}JAm!Mu+!;0PsVx<K)o2-jzYqlaef`J_b|SrxV;ZU_ZsAV83$-#vzO6f0Lwnc
z!;3)nGd^4md;J)XQsB>@F})R~0EWm5kNE(@UIyquM%i~z6vQ|^2W`O&aWyI(A&j*}
zprMS3CV(DfTy_TuW8|$vWh5i#7pRY7Xz8ZGXvSg6Pl{n&jseRdh70W-4l}yGLl0va
z$}m_M$M~Dlx8oVdTfmaQxVjD<O=SGG04zxiWd~4>Fy>Rj^-)H~=MYbJFqm|@=NRK(
zT85@Dj?&%G#~B~>LE;2s75NoX8GJ7olg8LZzMXVN38kuJFg8+hS0-cgZm?uAX6O@p
zlCf?!N~ahV>tReb<BLjE<}lu-EaP0pS(@wf7#ArJmd_}sOy1KB$FgGZoMDVU4fO?#
zb)8UA$XHG<auH)|A$n2FI7stG38O0=FlQNmYyv4|RMN(;jA3<yG3OZ1-$JRJ@ipDL
zd!CU$2J8w(^&YfUF$T$_T+Jw~0p?}KnNMM14a1AR09P2f4p#_XWgM|X#WhBT6}7dD
zFC!pP$9U*lR9<KNL*K?5jF7EpYhY}pHB2L8M28+WG2WrbYBM9_V^rQ^EFcF)3&SG=
zoUM$X1HjS-D^S_ac;PW{-e#<zGt6C#<s0#sx*7dRwEpa2^#2Try9}2SH1;vn$xz?V
zNTI1^h_T@Z2o5v;S`9M7Fl+(mC?lT^Q;ji#76WFSkxxFQNk&j5+NK!%=Ru|!#(043
zVqSJZn=5lwHH_KKbj(4?gXu$ySx=^O;p6!Ic`-L!$B_Ck^U1U2%glWjrM*n;QYiFe
zuCD=%Khx<eC=6hFeTlXpX5)u2JDB;(Mxcc--=f(zjQMgJRD?6%-3aUmrj63qqM64Z
z28m&wq*vz<(`o}}9Ft>0DV~{x0JdXx0`nvCpB`b(dk*qPncE`q)RLJoZ=x5+nHT9m
z%n4@SNtl+(oDPRg8O)8xVN)jaS(?eSn5(1^$YusFL0b-!xfvvvSxSdTPBXLrzZGXz
zp8!|^v!VkUikaeUluDSB6bE;lW%|>S?;P`{9=4S;^AcdpdFJ#>;HhL5eFpW{m_Zco
zsb&60vwR)%Kia}vXYvvtcZ0cz&i^$q&q<-Tk?BtEt|s&z0?o{|6ezjH+(u{gTA0a;
zU}!6In4B_g%tN$>Xm>DuFGKz|Gd&LKJD6jUD0MQAQCzE=SwQzu_Ar<J0oGook^XGr
z4s*~B(7Vi6D}dI|Wbn|70cM;PdIy;|CxAV~{F?Ti!%S}<RE{v+euCU6b5j7w81wge
zs2peRD}wkW(@}5+tW(UXSSXxky01YmTv%yC;Mv8hC5M75>(GC&VmB-Dd$hT+M&#(W
z2dnD^uz0dgO+uj;E0TKX&0-e-Y!B;(3VrcmO_49km-SjW?A^;+{Q<=Hv651Oxt|q6
z$v=Lq+nbFr!=LrW$KVNIRc?o-11vuY1Or*P=p8Q`>km5i5zLxh3%wz%7d=2iS;r{)
zd64y4$gFj<7C8<+gsw%i7FU5BX6^m}eTij7z7Nhg*0X$=mdLuw19TE=vI%WRSO;<-
zevB1J$GlQlYsgW1oK;2FNTjh|X2H;O)>2xqX0TqPsM<+Z%}NNIVr}LCC7adJ41qk>
zpXA-kXZ`F*hs0@?<$3TFvV`P`D`M&XgE7UdX;1W}l;uwTyfPM(=JRu`mL=dUXSLD)
zgP&)8G#`}}tn2iHy}){lQUWSj?=FEr6>IVgG+ksZd<QI-Snb~fteVxTgB3Nb*|Z0~
z!kSf0PTZ@kTjV{u#=7SOQp@^80M<HIzZ!zqS(R~My~%1R2WUOZgKj!&V0{>lv1nwq
zP`smwr6dntGs}}UXSY}$G7Me|tMz9X)5>b2EWb9^+%<r1XZ59_@;2*s6i64V<84af
z>1JK0l%gJ1nk%|}mlbG&-agh^`t0|!cF{!&1FZDlp?8qgvk7E~wUF|YhFSbCAUDE_
z`VcDavBu4)yw5sK`8uPlQSuXyvGNi@##w60ntQ;S7lzUVYuz(YKgqiF3<WW#Sgymc
zZJJek9%P2qY(&>w*#Egg{Vw*V*#LEAU!f^!H~TI{$K2R8w0Cf4FMJY)daz?C7uAy;
zupFRXY&kt2Z}ty|!MTV1i2$5F?8Vst^JTyOH>}vp_M&+GKK4KK8FTDsKTH#pAA9FR
z=%_#2dlO6yV1NBChV%e?`+e{PvLmV?5yU=C`76O}RT^MI*b)jYhO&Qs9x4v9-}?#T
zVeIr_=nZFglXowIeU#FDBH5Lt=tLCz7gvyIb_)GaW7us~P<zP1)@(yB4zpeU1!ye$
zC)&%#u@BNlH=cc>0;L3Y?QU3+$Q~s>QxbbK%~MC%gWeeRqwEhNp)i^4pdHLHcF&6_
zrLYrsLi{+JLB}Oeun$qPUn+YRIe639PpN^D&bH7OBZG~9;y^Kz{mx}Ho?>^>=Omk*
zR|1m59;yIOF1wG?-}2b|yI_7kJAn*6&3<wYu+Ol+re#?HyNQWD6|w`m!CAx}2!*}H
z>?^bjEMYTg^L&<VdKN6D>^*HjDPvDlkn0@#o`cey%GnQ7$oo7ymQHI{u*XFZyuj|H
zOx#NL2`8{tv0Jl1F0%inGuM~ceRRuDH9JQO(97%s@(|UqJF=ku3OhlIvAD{<L>sSb
z?9~rYS<B9(4Q?I##&VRdvy13LpBwC(J85BalU>LFT0Q$K^6odVqke;?Ms~&l*mR5i
zb0An+*iX~@+{#vEfTfMidKhi(Y+f5w+-Cnkk@^nyaSG6MvKQ?HXBT_Zk7(;=?{)`R
z58L??Dtp;l%2&I?wuEC4?y{p7(I&Q!9Yps6^|QBAgk^x;@;Ul6$bRDzScljjl0#sa
zeV$^WBkW6eFeLZbCE-wipY2bJol*89j{|LtT}CNA<LvJ!c=~`{s|J~1e;9<eN%m}i
z$W5`+9Kf7re<%Z)VLx=04wAZX%=GYfarUP}-j(A^4}CXB?*$1r&OKTnxO2uR;^4u#
zu@se_oL3e=-is4O0S9l+7uB$E4<~mQ#C<sReGvEMBwc~PUQSLUIQMaOQ<mU<PA3zU
zew=e5c)R>LSDpr^BY@-a35o|e-QS{5ft;Cg@C0#QqBF9=94Q@G2;m%~4Q?ohTL?oB
za;7(6EW$X`!7wJA6Wt1y2u^P%42|SGL{ZZy&UfU@iRR3wB%T<~!)G9Oi1QW&K@M}?
zk)RaINuud0&cXTRZP0j5Tsl-FaNgMn`9#hR7RXV~LUPX~bJkF1>M>3n-Ar|Yvzg9p
zr*c9+hP`Q=Uukie&3WbySn@ax<nYYrtf9!tY0j++AZIuqe~-!n&YmqGg&aQ#FpD@(
z(2u#8<Jc$wE#Vw^6r_~1j1u0;INnVFJ;!;Uk_gH<b3R7fdCp&RAYZ|m{0r(UIfWm9
zvx;+Q7kYS+^ZB!|_Y&u&CE%>)_|ZP<GAD~7u{9i53T9m4Ts)3`Ugc~mMB6n^mlHJ9
za&|egfL6yz$p!0m&MWUg;SJ8X6FPH~lXC`b^_-raP|?77lOAj%r>6&{Ce8~>f!55)
z2t(->r+5&cEu4`WyaKHp24x+zan4i3yq&YA2%2tlc(hjP;EV>M)X6E2gIpI!e~cE<
z-JI`!Mez>jQwpBm<**9D+Q)ff7^I&w&<xWCIR4~q9^?#dK(~iD*YY4R%=za{2#jzd
ztf;)lkzPaPea^T0ATY|=wi7muaT1g$jdQN`qGt~{&vGCz!TI7_R8Dfb$0>+1#pz0f
zrfJTKLm)Gp=Skj$EB+k{cXOL4!r{gh&}~=l-2L<w_uy(aqRo?gi2f4XiyKcLb8qfr
zi@>>u`wbtx_u(e~0!_Z$`zHamm;2ZzkbT^*)R5cHE%${YKkhQ5Uf@&+cg+Wo58yub
z3M3A2UwQ<Z0=a{f^c%!oM|=NZZXx|RLb!o{Lok%fae}}>?!U9q7RGJ94A5|H#&>9o
z;5N}lB$E3fIq74#&r*ilA@0X+Xgkb(m;z|=+$b-Q1nx_8n!u6BT}){uN4bJx@Fa5|
z-w(lK+%HC<@B}w}0F|lS*Uq7o#$8_q3p2T^XoZ}`Jwq$xliZ~Dp(2|*@-;{f*XuKg
z=W;(4K}8;SBkc?Fxf^~3${DWt7qk^{*HApTkozckc#0idSMsWqa7*=IJ<B!I^DX7_
zC@H3l`!7ANa_+^aQF)&GT?P!U;HnNmZzZ=Y9;GVoNy_%S$o-jCnwPl0>H%8KopTrV
z)^M2<;Jm_hp&;Z{?rU?Q{u-Crk5Vo7D;wnMxQ=QaRNUmgCx=8mx1FZo2JX^V@n9Rd
z^X5Zu6Za|Fvov#6v<11vef$=lZwq%h-QU^DeUm2i9<C3q+<LjX=OA~7Yoz00ce%+F
zk?G?`KLRTTxUW&#+aOoF9Hk-dHah+@!hOt95BX8<%4jr>asQ)l^Emg(A7JSNZrm(@
zPH+X+&^F2a{VEKd;+|Lm_0wE0$`qa9`cP(q3$KY@wp}~}6JV~qrT?Pj!E>f>lqavn
z6_sARae7O<dEb*OY7bA7K`$w<yN!}~e0huChBbS6pOBY)AMa=h2H^njg^xf2d2g>m
zM}v5CW&<slcaY+<Av_};KMduW<^ua5?=9L%gz-u!h8oT*qMc$4?@wC79OAh%Ko0X(
zHlY)-Ja1Z$#qnG_03FYJ-IKn52|V`!s7T~J><p5`du9NdQh0R~OF7OPSq0Nh@QNrJ
zk;*G`hu$>aMl%L6omWc7=rVX)>LHiOYn=jU7VqoVp)i}*^(r*w@GiX#lFO^9LR%g$
z=r^F`^Va_cl+(NiV*34^;q6TTPXRBEP9qfZt_=gNh_{@Q0g8Fge~Pve-g8etzMS_n
zxrER2(xV|?!85g^zZZCtHRx|8@7BLysp7pxGt))h^3R~@5>NUuFspfMh5>esH@XF2
zwY*=+iB!j1OzS|$bsn3J;oacnkqi4KZwsZU)$>k04fzJ%FAt;ljl5d}fNA9|P(xE2
zueu9p?YuXVfp(j>trw(&cR~l!$<t7xTo-TdZy?>gCnuqzhd1w2fc5hPR5`%gnF`E7
zUQ8D%ha9{E<d7TYJvIfqM|kUKiF=P%PFec*dGlxwJ<4mRJFFh?I+mj}!83Hg{7K$D
zit<kJf=oc0<}D}x*bJ|Nf@?1PUF4(O#kW(`)0O`ch3Izk*XRN5#!vPIap!NR1f4y6
z$K@;(efSW=i^%t(J>_2h(}if<$A95*^l3j|M3bK%e@`t8_UFI!EYt_^o461N;lFSR
zETQ}an!FD319AWs#_uKfDY8%8pgw|cA?H&he;4ftqWHnS&=Ac(>I{@P{y7J|dhz@f
z^y($>-=|kEkv~M9xFo)`1M)}sE=rK2`~bSzKAHb$0?>}}&(l$ZG=3VLyHDpcD5Exm
zfBj=rX7bf^m^O>QdLtB`<foIb;uJql0F-QgX#k*e`1$0x&*!()(E9T<f6+rQ{|x_i
zT3Q$IwRCu-kpFHYV2b#nB3N3?XVCe(68_%rK+f{NzX5?#{=WAhP{xnB2<&tGXUOSX
z$sct_WflK#y2R!p|DO#Izr?@18;Yv=k2XW^Wqtrfd29H!VUNFn36ekD4$$j-4t@V_
z@J~=s{U+Z##P192&;Oi*$|in>7REI5W0^o}=YLA>;@kW;GEv#VKT<-k9=~xbNEd(K
z1qgKWSJSGahkv*hV7>fzxgZ1lVM-1e<bOFIh7R%F=(xu)e<6hrM)*~1*mRFS-xt>3
z=g*^6!zh2fqZ2R>`1{DiGr@0WfK2jNQUG9zA40CXX?~LjU}pFkv|;oV96SjXUV`9!
z$a@Pa-$mOVK{=hv_7V8d1vS2cS3*Jd3f7&0-hBeMK5*_AgycbypP;!1C4a%hA}9(F
z1Xq%i{eZyxBy0;5JT@1lAi;ujXbcg2UI)-nLDE^k929)x2fM=rGI9Zg3wr1!j}&CS
z1(qnm3d&oH7F^#B&O?HkJ5YaE5GV&`tl$fB(8dYo(;>ikfyZW$Btfhb<c<i^K70!E
z<59sRedv<~QGbIR6P&#Oi4?)Zv{pMV_=%R}Cj=7-AgO{5nzPddowP>G5ZsCf$rQ}_
z5OP_9H^|j-QlS16<dop~7tod?Nb&>86(q$$JWs$m2k3mkXC^?O7Q6sQ0_I1-HXg>g
zK=A037|TMzJvvQWBxp23qF7LP29+fOA$^C=3V4)6P%0>)7r0FDJ?#e12|DN_Q7*_K
zXX<%Dcs|4{1S#Z)zaZG~DC8;yUr}yYmEetUVEskGGqk+9B-r{sz#P?r%k=raA}FSS
z)K$SGh2yRX9Fzo9E0|09#C3v~DfDz*ko6^Ox+zFUaC~;XAaxuaZ4g|iO<kj4?{{En
z63jS(Gz-?81ZIoiZ`we$3XXpS&Njh~ag=TgnsT71L$F_s%1(#ij{;cJCD=?SF}nqV
zS~T_uPKBZuy@Hpvfak7Yihg5#g5{IwZ@-}K8q^O6-k^zMQ1JO4unY_KP(H?pAm}}i
zdxGoq)xR%zd=(Uq3iR~s#{}nphK32jlPbtf3i3T6Hzja*w}4IyQY9cWf{a+my9gze
zQ@Tqyb^^w@3in-v#BSkMauB--Gw2)VF03s<$wQd_3?7B2F#mN3cnRxh@V$lm$z!-j
z_!c=+eS}8(wE7Cy=rA&Sg+tGR>=SMnMPK#{OC1zX_7f&&L9f5Cf-+PCgwtBU91tE#
zhrxluG`deHNLWt3w_xGoSb&BIBNVVHRG9k*dU#NH@pbetOla%_cDOKVAvhz1(|-ab
zQkcC3BueOl6GyY7g>L^}w+frI5I7_hULgP2Vd08@P>dCN(03?KxSd|sc;Pw|dYB+Q
zL~iCp;TAd%dQ@2d1ym#pm(U*Vm~aVYAf^br_W}F3u#|STCxow1)FoATRffK#3Cq%e
zk}eFS<y?mFOG?1X6t2^QGfQ}H$(;50$p}BBTRTn(w|oSNY+(;A@^XYV$1!ZVLhn~W
z@`M)^P?#@VGzys0!eyZ$m$%}|g`eng6$wWbKrI%&y&0?}!rR|qXwC{7$-Pi2bTpu{
zOt`oemFI*b)ZcPpB;7V}UU-&Pa23LzY4W@v>|2UnR0<Vxuv7^d+o7;psN#cM7HTMs
zvqq?)|FXCuES?8)RhZ=14c2SI$SIIo;j&D?)CoCsv;TEr_RrwCA^d$FDsKu8(p9YW
z!WcRe)gZjM0|JdgF3s{y!jH&*+AQ4g3HowNxHTR&wFnPyf_SU2FAr^P!UhWXwF_UO
zckZ_E)nZh32qWh@z}hMNYY>e+!kvXE^$NeCq?kLxE+csE3d=$P+9&+{AgmY={!B}X
zLE+bnQ8^^6q0RfSux|~-M}%(ApriMMKYa$2QQ@J_(1|hO<yT<gxbU0hV0j=cBrn5+
zuzD{lCxt>aWvEUIbrgx35x&7k4_!pMco0|7G<i36i-Mg{auY3}*~?uNUkXkSk?SeQ
zdx<*RLA*u5_hIiIk&rwmKB7;T!6si({d$nSBHvPo?-ylLJlRiVvY|`<qVHCqGC<_B
zfiiRsh@Pc4Do`}2K@WpP+sQW+B8u4r&`?p16rG6>ou?gRq^SQ-R7Qz(jSz?y<<Q~F
z7}1AxisG>72in@kiV8-79VhzxCcxrFVp=mLh{WBfOcbp?0r4c!pY%C8Dzed6*pV#y
za|kfUM88f#K1H;53mT7$no=O2Dth@1jB}bOi&lr}B0F_7L!|VCK&HsU3qz76T1H6(
zCq=JQ+IWtrn)b=Lq6&)0=800t3!5)$5<~8^sE^_f1)@D-*i<OW*Z@-G5INKHEfxj8
z2Zbe~-IUOARy0Zpqh+FL9$?Oi7SIp3TqL1j#(9w|1#K%tb2w0VLA1pK;#H!nE?~JR
zn&pPlCDHl}lrD>&rg^SL6#OPe^or=8_b^UZMS0|_xF*_8IVyD`N5w4A>!N!U9=;*s
ztp&L$s-Qhyy=Wy3euHS06~;7)`2E0c7A<#0+bz*4`lz;uzM#3cRrEZik+q42DMWZ%
zbem!m9inHHP~Rzfk9=>vqSzgfyCeGQO~~C9u~e|4PjuJu4jTJKK67C3plGTJXhS0Q
z58xRVt@Q&L5rq{2=AP&=x+3Pj$V|(#Q4yOQkmI6#LdZQ3E&mp#O^8Z2f=r4YaYf~n
zXcL{cm=Qf8hD|Qw)DBp<OFWOfbgtsZUqNZNcy}Xh?%c#xly&Pac1b~_m-wetsPGow
zi2%<Yv4B<<KH`A&DEW$WY1_M3{3_+I>=W;x^Kkpcvpzs4{KS#>0Ol|Lu@<HUh!@aQ
zctC7@7;S-K)^%_OiIs6s6fBmK10zJd_cb~p6)F}_0PUc7E2SHSiJK^kHC){PDilVD
z8_8`IDPBT(U{T_OGL)jl{uJGg5l5F{WDbcFPoeFwc=`*dh!wj~LR6gigGT@sFJ4J&
zt_1NON@GbBZ~76HN#c1C5I7?K<n@Q}`#UQB#0e%Qi$gAf^_chr`uV4b*U~EdxVVcJ
zyeGulC~}=DesUEQris7RLLgoI55)~L#K$&+GgI784yse)h+`1Q76*GlMUL2?e%krs
zJCCE=r^PIKglEK66gDXmM^LV#qgb3xsaGZ9IddUcCU&AP<~eakKS0aH=O{Pkg7}4R
zps7;)!)H)YB`%;PZnb#l2Pj<@E8HPoBMz8C53h;W(DtTQT$_zjop}GB5Wgwjn*^46
z@wW9K4dSa?z|t(9O>yj74)I4^ptXpXAY41UReXbDIc?(BEl}7leuS2Fx5bmReeDp(
zeF6(R#ce%+=@RGA+N)b!RSTA0aY-udy(9ke2bAuLt>ho;6TAB2)$14A=#w!h{=)}y
zL*i#XhoWKe4tnuN#EvMs{^Fk4ZxGhp7q5>&<EVJ`cA$-kIp3giT<lv0mIq?bldx$*
ztb7>Qlj0}o@{TES359K@#pWyEoDu6H=v|i_KL(avlD%etxk^fBz~U~M%7;P^$u4qm
zc}h0X%Fj!Z=%Dj--jeqy-FA=UodaO?k)$?()mPFI3$%R_XIhu-mpnr*F+a&0JZSQl
zoc#c80g`v=XM8}?Pob4SN!}fhAjwYp!G}sxyU}(~Qb}u=FiF9auqjfqh(1SA5;f%$
zM@tg=>6;NFxqS|3ha|J;#fX(SR-+Ur`R@({<0YF@P)d+2V*)!-a+m`vk|f9Ju9G8@
zxAo}ZQOP~pStm;l&<uV|^2-a*lqK0tv-C+xTrAp7NzQl!C0inX401UV+fJb5O1|}=
z6H<AS|CT^gzGNM39!^W@o<!-4WUv<41rm7(NTEcQ511m!`{b%AmMqwYCt4y&+6}a`
zl8-0}y;S1n1NCK++JC`vPV(X}kSmv%DCh9JWcn49DkQSokh>uHVG<fDCH67;{Z&aW
zg`)PNB#yF<E=d#(u)A6^kFLzTEV)c6lQojfl-YMpGPDkwY9+HML|G@veh%Y&Q&L6_
zka~%KEl?UHmpj1ODEWXwbxo2#>LA`M!D19Ix8z02GHjDvq{N1HN&0ip=eRA&ehaJ}
zl2zT1@018>EV?9%XuaMoX?Y0PJ(6_Vb@WOu(9h|Pq>2u0-j%HS6KH*s_n$>uzeKnQ
zZ3B|eq$mwaE|B+XNa9YI!;+3Hpo~cN-G;(@k}cO^%zeqm3ABwmB*7G89Fqjo(tcdh
z^&Dy+NOpY+G9k&fK+~k8#vNoz68a*#HZ6I68_0}gm~vZOq#C*aWtVh*6U=s%K10ri
z-O}%Aesz<UJq?@OrEBS@<{>p)hF(u;<{z-aOPWo;EpMsgdplV7NFNMBg^%=AKh*k4
z1L*|7UTG$+Z}v&mwB7KR9w4`Ifb>lrSPn=V$$J$jy;KY<f}|l7D-V{21_L`pnnBU+
zQ0aR|AbwE#CZ#@wNed~*Ib6Duj_O57w||4mNU7CP37#lvPX^RSOE*)pMvU~#1;`(g
z?x8RBVd+UqCWw_v9)rR-sUsgS@zTB@A)hEcSqPhwq#-otACdk&4=hKe)pW=vS=vV#
zD=E@1mq6ihscIAgC#16}gE(C}DuKNj()qpQT*;K~r6-ytJrah}NvS;(3QtMR6hX_D
zuAq%cj`T?iwdYE&J_^u0skadV`O?WmaGsV5HllP!`o{*SD3ER=FMFZ%+1JokBo&fV
zwOG1|(yB_NF7(?xEB%<Fy`|E~ar*w1N!RD2_MG$!`s|lWSJT$(ymX9`fGVWiK(Jnr
z{&^h6R7wRD3$2pAaSJLgN~dC>_mVV$wpG>Af9dSlW$DxNAXg*JruFs}DWAOaSEbXP
zXuBqzpj!j3OBc0+<%ZM+er?C>n^L<BU8|Qehf&)g9iqlY=>~GFHA#Q@9;8_s!9wLN
z>F=~YX_0>M5YSqs*|aWdms-C-*KSMeDahR+eftQ&`lOf7g7iy&r0~>$G?v^cgVJm|
zSUDth*?=w$OEZbnF(Q3$JqGHYbP2gE?@PZHfs9J~UIrPLK9q{Fcp#mWL+^ytgHD}H
zN(VwwIVCM2ztObxkxzj=BfUu}p1Wl0Y3t)EtD|{px6DA>DG%ADJJ94QEBFzWUNWaP
zl)PnMtVL;$L-xt<pgyuCJ+RGJwsI><du5yHZP_PFqern{R@4S;e;NA#)Cb7I%fNC#
z_Tw~q5hz<ohiZdl!hYxtmc3C7ln~je)lhLz7SjvyFxivM5D%CAM|lbnvLF9|*^#oh
zIADpEIXcM?8Y5de4f(?|HZ8<rWiQiBByqCmCeW5BEAoJRlI#b{?>!=0MS<vaS^N=b
z%8<>v0=Z1t8(U#Tmh1|BDNo9Bzl7dXvO_el=E`2V2D9^I5)V}7%bs}#a;Iel%}{?v
z*5+`5H3c%Z8}t^+?$9CRBAJv@f{JBNJ%-8>**aRwpOvj$2o<HW4$7f8Cp-Tx+RA0A
zFM;#CEOrQ`3R$ugEEi<IUV()dWswvyxFkC{7ns#D_fE83mhry?SdHv0N>jQbOOnz4
z@2bp`wvpFlPDTjU%I=dZu1=Ox4uh}Du9NHHhV0@H$W2)U#U|@zGqe<Gkd;jVrct(M
z8gfmtZ32*H*}Jq^xh1<sxiu{^p%`GTvZcxBZ=0-^mWu7NiAjjxmR)G24Al<Va@yf`
z%4P(>?viQv;OUnA*$S8**`M#hv|d?yCCtAg>$ro`U0EkB$@^saFM+dPHrRu<0a@!u
zP(LX9iL&p8WPef6cUbn&qp)H`_Co~(?#W(X0nYofdsXQ5sBGik<UAXby?+qJaoLW~
zp#Fg@A_zPavcL9Y*d}Eqlsz;hTTV%m)3VF7O_-6bAa|LI+?J0vSNSkGZrtS||3S_}
zzK9;Pr~Di8yL!os$jj#~pOXZzJ@SESu=vRTyA1(fc>?)O9ed@5Zm8cUR|WxXzx>Hs
z@c79$dZW=_KI>JG0C_%rWDdxO$mbX?UrCQCLjL&U;Ea@y(dox1`RYuFN6Qn=qAf=L
zgg^RnNZv$G^02&rCDg~tuP%jYaq@oJ;Ks`zrR7b6Lq1L(@kF^7U51z>Po^A-Bk~P@
zLE@;qVFs2a%by_+;xYMFat)`*C$gdUxcsrLD4mdVJHeSMe~7Zt(&QXk$EC~NB&f`g
zzjGCGnezHTSePYmYz8?gUrTqQos!=?36d>$1c`u_BR{$nXu0y)LEy=g{~C=_zI>9F
zlc(hYG=-m$H?06@fxMm)n+oL_<O?g37f~Wsv0O?Kk`nm_+8>;i3*5m{Dh~)jm&)Yn
zLU5MLZ@h$8=e+zRy<HV@XCc&Hko!8eL!wgtJQ-XiAKL<ni*l_5XqV(WC^4g2evM|P
z%W`L06W7QW|BA{h^55yZdsQwb??j!vkQ}|&<u8$2;)cBQ0}R4V`D)tI*2{lP151Ov
zosL^I${)~9u}S{gK5#b6T`rUJ`j*^02c$*5`DI|Y%6}n`c$>U70fO!FmuV|-TW&ZA
z&<;6|_B@^PXAc9WOFm7*)h)mL49xD4Z#)Z>Uip?CXuBgnD+jqNuO}~TpZw655bu}g
zP-JyL-cBpcK{+Rt{4Yat6}csc<yG{P8IgPc4suU^NR5HIFSq>;GAjQx0D@!k-#-KA
zxV)+hdLPI?mxD~mf3rf<q<n@BK~BjR+y|MKM^LiwjJ)_B+FTURe+AQaE4bwla8sPD
z0*brhFC?dYHrq=vpWMIR3U(7T?NOK?hTvX>f(f!u5l(^Z{R%AuHu)(qq2gDec$d<;
z0u-Nz{K>%`W1rE=FGSJ#1yDj2kFcTepkgzfJPlJUJ_Uhr#i$vj2nCChsv{M<Xz?DU
z*!3+?q7}CLsEkqYe@5w$qKyfChZRr3H8eX`@qj*Yaf*-TgTyNyTLHNQ#f`hLK2fo?
z6_`niF-HuF$%@xic*~9{Smd=%QT#xG&Q!&0I`f&PXr}y?bj2!i@?|JWdr`_%cnSfU
zrRezql_wPgi(u#}#q2jxnXR~R8I?JT+7y80DhkPikf)ew17^Nr6Bnh^ipO?=oKf&|
zX$4iFXrwJyq2dz77K;?2$Dp@Z@i&D7N)%;ujP|Uev=HW(DxO~e&@#mfIjB6RaHfR%
zaz*hQcxdMpZBl?$D88oo_=2Ky4=O7aVKkptDMq~jeNnNNuIRh0h@~A@jp7q$`k%Ec
ziWe#6>#E|Vm5{%t2>AewwTewfsJNkMpiRe3#Z&K~vR<*B4lH#m{;dIMk7CDfP~WRq
z{V+7$Q7oYk*ImUA=b*k%alH>+>Q{W8h{^%QuhT#oR0KOi!;qqg%pO*xJxXVMMie@l
z((WlfO@)g4iWQXVGOBR20(49<ZysRA6`THp-~+{WO0%6%yg-*oO)7>cm1s&aSPnTC
zrT1~5>{5Pv8v?G%B03MVTlv#@RJtj@%mr~*7Jm%^59Qm3!Q!d>o;>~zFJ&xw)V!5@
z*Q2;cIe!GU`6%Bc2bHgK;R=k*Uge`718tvj3;kgCD_?mREPl!ein{tMjSpaGfHIM$
zq65lZ2A~8g%Ov0oQf9TI6s+{3pGb)Ena{xzs{EB=69<(pYhY8DLwRFAG=(c~Q+`B*
z^1pJFB9&JvQHoN|i-LT#(nd34jPfTFU=As>X*qXTSx+xita2%BY2%ceC}JM3{DXc!
z3CgqN!An%07{DV;Qf{X`%Ms<@AAsekGW>BsCo7rHLHwA~ai5mtDN1*8${be;Xrefw
zv{JrYs`8cRQJJP(_c&nEm35SIoT1!JF279WV|4vQmU0bkCQm9KqTJt8$|X|}$W|sh
z12aeY$Ri-RN-q7eMxOHZ{m`4QoJ)(l)5>kXL;Q^LnuD%oC{UL5fVEKh+a=T%DLG#O
zv{?DAH%N&xU<l-_GL$y4rOJj==wX@i5xR%(oKj7xrRB<<<v=;FjK2l!3S})NR9sL_
zw4$<7X{X_?Qd-EbU9AkJXuxHq_%up2$^{dY9(6_Oz5o(em7mk3drkStR&=ITdE|3c
z)+seNF(lWOk5T^S4dv2ZP;pbakIvfEE48DjY*5zGvaC^gW;e#UNf}1Vz!s(POUSh<
zSF8a`o3i^QfVC?*FM#E?lJ^nJ?oft`$b-<WEZd3B^eAuY(b%ix9)T5o%I|3x*{?Lm
zplv{DrqtnK<!clg8BxCXElT&4_bo8yzH<B_2#hMjeuu&_rSdIUKd$`rD6Dv(tfu*V
zLK#I1>`A4j3zbvKxSfEWRu+uV9V;`+7)rKsQRN8%vr832TL@QG7P$^~t3IToByOs+
z^riDuJw>iYFI5r!LzA~EmL_ChmD4D!*sJ>e9Mtbqg&H8fU&W=g0YB9{<iPh=c~Q<q
zfa=Bw6dh2-(!L^4^*bF=cLb>ne8>l@ewhmsLsTot>l~_T{T_`6RjzbZQkbgi2?&O(
z#@~fa5i08vsEAapx(AjR)iFI(98xVzfrW=vAIAYDUbTcAVhJjEZ}2-%J+uXFNvhEZ
z$Q@CoQmWWd)z$|nB|B7izJ$av)!ZnUn4;nzK%b7Q0_Ow!gz5tilu}jfy<kaG#qWfs
zbd~>cRA#7hz5~fr?OO~LS*ks>mOiOEnGOqcR8KacEmw8)H<+ELT1&_7i&bxXqh}?m
zGV%wURaG{_ic*!M<2%%rsRn3Ca89+Q6N2TcpASLdc~$p&5Ufyn?u4ZmRI}&{U8$OR
z4+2%Ht7TxhsH%<vxujZ_3Qg52@kX#*R$aUc>>8D4J;)W6(+6OwRn4LKrcRaB3e4-O
zxcg|kq59lGpURu6x%BSTtA<~}a5t#pDYLdwRZd>mCRKPA)VHWsj)SzS&e4LXO_fju
zfp%2|EtYPpuF<3HP(4Oz2c4>gG(cUdwVe>}R{in|IPa(y(Ff?R>Q4*$*{2GjU_`%a
z-g5Gw52#G<LSj%=B}VO#$`J$GhE)ZW(=(!ajFyU{Dh2sZ##Dc6LB>^0G?zV4<x#Tn
zgzA?zsGn4QbQa=Ms#9ek)2akIoI0aQ3V}_o>UR3X?N%3xp~y}BRX+y7QyrE<I~XtZ
zB$?=~_Ph%;U-gP-Vd7r(G5V?PQ~zj#-TrFJC9njjKc};Z2h<&XuqjwQ@&ejI)TI{K
z6sj(vyIsQ7|MsF3p{}P7W~BNv%Jqm-Pw$05y!tvFs7z2VrBusAb#Dm$k3y0<Ar}T8
zQGY)d5=Yf(v}sRPzfVc`$J9^NK}CxCVcOCjSBuHrbV7Yp0+v+uY8SAiso$Y&iF9@O
zLXZr#Vg~9n)xP9r&Qd=`{^67AIpmr-rC#|XG-Rt6QL<BxI+%`9IdawegCUWp{`d$$
z^VMo6luoP1zl6jY_0n*dU!dMXq)`3+W=IsN&nCg%5_LsBN@vx_@p+hCs!n?k>dVv%
z*|6!H`Vt+fDpwCv?DxESU@kZ-)D^E`)Gw&NE`~s*dLDWAsvPQf$O&~(-Aj33m(<a8
z&s(+HFANfw)ocHOe2sc<5+tsuHKnlPs(Oa5uc%Y=7eU2!bzdepZ>ZA~VQ+&vj}D?W
zs{P0x*QBl|&K7k6Euvf1FH^E&n>uF+G_<S7K1AuZ+L3S(*d6M<<a+N`Z}|nJM}3)g
z<h|-pau)Qdzar;;zj`bJFazq~J!l(Le@YoiLuwTpZNut{VpQH&+sH3Bs{VKz$e4N|
z`Jg7$QIy*<sjd}*b4tArXEJ8HXtq<Ac4;;`7-)3WR8+%Kcg_EAJo3<-q2y{$jpS7*
z^wPXRv!=Jk<pfyvXl{jp_-pi(+7qC$oB%nXai0N8pvIqa4}&xpQcxMJd6w3_A(|#G
z#y3>MrexHEnu`=b3)9Tdo<CfZv69Y7MrfMqP>j^v-veW!G|}HcFk17^`)G^NyhZo5
z9nw6N336DYdkiqKniuHV$7x1r^Bb=@MF~*}nhkDfOVpGNqAf|Ynf!=HG?vw9JE{pR
zgWhD#r3E0zG~O>^m{T+>7Sr*V<C?|vb2_2<k^#F@HFC=4PSd1Nig&u^>oBxsXwF8V
zl&MLiw=+wV_%Vz*sd;uG2Jw`}qZw$~nwy7Vc8*3e3@dUqZ%0FYo@QGmD)Tk&^$<U;
zk&#RGj3$K(mI6)sYve&F)T|;Gc#)<z0=31Ooz%4wji?Bvvl{+xlu9+Pk3w&m=4doZ
z=QJ8xgOqE!C?tAb<J5@C3eCrq?r=fV`5(Y4HRWY6yGpZ*!sr(@uOz~XOPXX#vZ~gk
z#-VgY(>4QR99K1`$N_Rq^KUI+u4@uAQF}x4mk#8n=F>sg-Kbe-hcQi>!}}oEtZ~+&
zvQ^Vdal<yvPd?Dwu6cA8P&zgFwB7B}ETy<Zx5mN%W{)N!4J^HyloW{H(bUmT`>y5%
z+Di91G|jYO?AQE7f%gH;3_Z0$jh>4~F{F8NEd)n2P8-mRdzv{EoV&02f&LO>RI}?J
z$d740rOorWMx}wk1C8=IbbCUR$3WYp=4t>cr!;R<e$lk%YkEF28aBDPT(pxDXxpWA
zcs>G9SM4YCUD&OCq6NfFYnlxnckO#Iknqq>7=Y%fy+_+3FKxnVl)Sai*dez^`(iAx
zeY9><5b)J5aD!=kwLx!z?9;AM!nFO`ZFFUcpOzg4PJeAuGAaYKG5?@+KpW}!5v+mQ
zh83s{(l$R1^MkeV<o^uOzJD5Rq1s0pP<c@M)O@gnX)`v#!f@@H8mN!ZzDT(Qk=n*K
z7#gJ&eF)Q{wJR@!Ge$e4fZjve4Z&zTtbNf0%vh~_6G)u4?jc~tYwsH!pb6TnUXVoX
z0NIwLz5M{s;D|PbZnin94WivuvNnMxjAPpH!yqZzo6o@f<JwgUSa?Fa<vG}ts(qc(
zq0_Vjl=qgd&2oZVhIZ?FfX>t&TMT=%wDXf-%t`I<<Z?KrePR`*zh!Ihwn08ed)Ec>
zx!N8|y3f-tp>0*ZHeCx%r?r>1qBCc-c}&<;pp7ISN1=Aj$LM{LRuK)*V(p)_iY?L3
zKMA?B+D^&?E7jK1RrqCEA<Z-AwB6)GF4z7*SC5?6dQ0hyYlZfu<4|!yn|2nRsnq7v
zTvVl9@C-^9wb$Z-eM#%{D>T(;nFWx)qCFr(>8f@Gxpc2-KcT$dTJ7(YCSRvDehG!w
zwSrufZfM`5^x&J?TmM3!URxamy$#xLV$u6XZ5gFUIGVJ|HzCoi<zIw}x3n?)A=sjQ
zi&l57TFE*nY}0NDgnYZUsRnJgwR5ECeTUXJ4sxB^f8$Z=($1q>oVvCD(ptJlEBFp7
zdbQRJ$lcMdNP(ui+V_72OP}_h87%$UGIBKzIJ7QFU>(#x<bv8EZNWR}%&=BSAKVe`
zZkq1yY2TqE#rL&y^1(8y?OKYqG41@9LB_Se-iG)Ctuhsy6WU?=R!nMtNrS>EZPY;w
z(6sgk%Eg({en!wPx=XuIxl8wz7Cm#*IhIrO#9bHZiCPa`=R(MP>N<F+^wJfOLT_D4
zJf6=UU8fla`{@28cZjcUs1ucYbsh9;-luEi0Byf6@dK#v(<ReClKSg<=v@!cWyxUS
z0o^6?1qJH7eK5>Hx_v$9Qn1eApvZTKE{^>9p}J^Fq&%qmPYe}dy0r_y8m@b@43!bO
zFv{wR)VZl47^VA(wm#9iiYlmx(Y@h`wnMsAeAs(f7fRx>x|4dC7N=`@1eNi+gzrHT
zbn|HSoT$qk2TGFeMJ4_Ij_7*l;lUo&{qhZrN!HB^M&mKv8G6}Lbm75hJFc5W*KM58
zopORPsk-%a5GO-tr-fXmE`z+yS-O$MP<T?OAhS>DR=LB%Y~B27pycRYSP6k#UF8~-
z@^s^+us2_~%u4_Bds?^fI~338QfaePq?@7NSh4QNGJuxoj88#fna+JaG@aAETnUzP
zT|K?>7j%aybE{JKII_}aSLwFUwyIhePd=>6ItK@(8l6}Ga#L5Hj>>vn>2;tq=sX$#
z-KeuZM;TO2x*g>CXx1%e0sEG&hw|K8bPJd$wd&%NAm65&p*?uJu92e4w{<C$h}@xT
zatG<uNgf4umo9G|2CrM!e-ETb_d+Y$dUbCcLfakP+<u7P)m@`FNuO?#!n6Ill68P~
z4Co9L0~*xv-vb%awLgK{Vcm|EfEm%1EC%a6-N&z?^1iNslE_DOAJGzbLbrfk#7SM=
zT(C^({G4I$v~E^2Dra<Q!x$15z3LeHyGwucCfZ!}v6-;RL%)DNN1l3<4wzmJ{n0$|
zc<Yxu2GBkFI+|#F^q<a!dS87d?fCZU^?##szdqam;-~-X3BdU49i@1_0s4voz#Py=
zx&tLpe~vcaLHeV)U<uY=KM$4=ef7_13)L5yK*IEmQb336dEKxuLhlgV0cfQDZ%QML
z(q}vZ^JDa@-iG`k{Yu*29M;dJEoPklrz>cS*BdE9nV@e~047Oqp>5z1{f8kKnWOqO
z<R?znZwiONG5y>rluqbZtwbqR@B1Xc()9hbTu;}lC?K1m|HNSjPp00Dek)n}xKjW<
zsqdkKaHsTrQz+%?wW~2+dHSvQz?rZA{abLJ)~kO5IisI<8kGh5o>+hu>ihoyXOaHn
zwZJac=dMAiM4#-2wzK-GCt!W4K2rvPGW`<z+@I6OTK=Dosh>q>-p=d2jNqxzi>VhE
z^mG1({6+nvPoi{5FVBK8)%pq<DlhBrdqKWNpB)YCEBe{zF(g;@vu>dBntsQh5UAC^
zsf2}fdN!>Quj~EXL2l?DzJRuR{bo9A)1Ys9lsxE-`aOAghE4j2PXN=buRH^uTl%CW
zkZ;jvMWU@$|IRF!)~0{<1W3Ey|1W5|t#5u7r4Id;8L)KfyG}u_OTYDfkZ!#=AC*0N
zXYxb#>U}83<c|JT$_=}#-$CKOKE1h$zJL9Cmqyq&q@S|{62tocD5G~oA6f!qM)f`K
zf{f{J&Iil5K8OvQ9_T-$1oa91W_qtC^)E-FZARZnA0QV)p$ROz43<YQqPq=M<au{9
zETDyjyWs#C<6&^2*UHo2LDwKTybNjz2zwh|cmrgQA=?cSK8C&YvG6r4pm6J6L&IkP
z^)racIq7eh`##hM7-9k;aKJGAHYx)R8!1{FWLTC0V}cFclye+nctG!5s9}PZ%?Ay2
zG?#=KI(aZV+_1q1ED;Vv!6bMh4VD`KjWRqD2>EEk*RO*o#t^p+5{C>gyo$=hhA;{$
z#2WlR21ztbQgTX?VVp7%j~EOTE<I{kPQJ5bgRmbD=9nRqTox&Yigr{UH>`LIawiO*
z90W-<EUN=cn!({b0rS%hcj;D$48vU7w`LkXdJV>88Fqe;(n-Tc3cj8)WNbz+vJGud
zKt9Lt6$RjO4U>nVBF|u<<yF2RdInaUHpJ1&;*3F44Y>k?;~S7d!_h`4EHVswp=ZU0
zq_4qQVtC529<^r;BfnvsOAS-Bl_)d(=L&<*88T_vP;O{{7YffC96MlBg(3Gfn)(gD
znZa3U_+=K<R~cTv4;2>;X|zYXWa#MtsWvpxyn5O21f2k=F_<W%a>cNp=H;t~pJ=+d
zW_ass`u^1#ej)cno#E6V$aTZ}w6VBhSffDcrom2@)*INArQcvEq19}oA)VZFO@=!&
zsBAXWBmn!C;R1R2S`4cxKdIGFO5w0JgA>gH9fqb@$aNY%ScbMPLo=njb{m$u(Et4Q
z81(O;vDa|C4-$6_bx16neb?}<44{36!+q#zzkxx{$pOP?68bb~;F-ZPWGGt=3x^F~
zb5J>ASV<wxQG?eyaE=*HQ9ARuK}IgA2Zkt8KVdM^)^yS^LFpA!hFjtE9}Ck4)i2OH
zW7z%+SY3>pzW~oJ<4N*Nxf=h?fx)|t%dev3W@Md)pr>)xT2y)&8*f9v+c-Xf(jH^v
zA*k>%HqkL8U!%$fEA|?T=^M4rXyl@_-<Zh(il1@mL5!%s@gs^vIRcCy(W`sFxcX(l
z1R68xI`<%BDtQ2djh~QrFvPgs1vZ5mr|3?MgT@gS`Wt4vNSPzy#z!c|9bx>M)`*ct
zm(MY3QO2*I1K1(s->GOjYz(29G}d_KTY$wGZ}fvD-Wc;TP!b%*hw@=YqR~XF?<C__
z^!qzvtl0>jqsDsL_9h!g!%%t5sH9mW#kh>35yy=^<RwTo+9-gQX4KH$GTqoutGf*2
z=b;$<Oyg0?fz2{D_@nKlab*|CDPx)qHf0;Hz5%%$BjcebVOy@T$PR_4jhi>2hi8nz
zOHo;1bf!@+HfA0LDKS?41njfMF*kIy)Ht~erj;2V`wFFVM#ulxMaFHZU^#F6G$hR#
zC#%|5qEuz9Qb7EoQBQC6CF3ORLaU9Rw?O=|(T(y{YmB);7?~?ZAG);Qs_{`u2f1c+
zqCH`)F)$AH))`lS2+OV;U-$)WH;hgKjL1!6|3+x2H?}BXe1lQ>8lW4EQ?z1hGJff>
zV-T8+FCK#4TgG*nsBJNRNFmKu<33t1w;9{%Ti$LwmjagCM)wG)?=%Lvp|Z>P8BLnq
z#wz-p^cYXj=d;&XPWjq*j5{Af+g)Sd08sjjeZRt(e&bV~;2bbEuSVOTaav9<@Q{(+
z3!Y)453(g@j~J7Q+%q~EV8wl-Xg@kLYFtLw9*!9W9|30EsH2VM1LKu`z)To<vq2_}
zqjY1~l<})ZjMKEyPVeE2@tP+LbunG6L**{h(-h)%HTlvb*lpqz(x=tUlu7G+cT>*{
z#?r%d^bQ(5O><QsUZx`>0QEL4JB897Q}FX(@i9fx`q9^<r&Z`)(|2hg`%FVuz_Q=e
zP2O=o)87=B@i)CrYxn?@iX6NLOm>R61)6T%24;}yOL$Qnvx7~RK-7kqii;r;YKm+D
z_CZr;FnS+m;*y^@-1H({FCJm4c^xp3rcm<PMVSt;As1~*_XKB*DVgS{L#B*lcm{_}
zEtDq^Yr1a$OPs0M7bM=ah>lbwn1rL?Of>b<Wa&sUF+5?-5z`%trXMxw=@}-Q*o&d*
zm`U~&U{Xv`N>m;<WdwtqFeNU8V5%uO0VK_|_$r=Hx@jGSSu;#4=0Q`Y>C5+E?<v!I
z`g&)ZBIqLW9MjSu=*=~KMXsbglWq|@k?%0QOzz0jreietXG|A`fGIHjKpUAt(?0S9
z6q)=^!@^=y*w-kPn3A4?z*&=umanCz--n>7%=CN$#Lt<IOMqQ&^4o{fd6Ufxaup_T
zN^-hjddH3~Rho`9gH)NMv<bava>SAM_LAw!Pk^a5trw#4vgr|eTs0<-Iw-tinso(j
zS4}Uz4RX!o_y?7>rjICbtIiZW8!E1w?v6m<hKWNn_)U{vDHPV5v|mA>!KBSWsnOIx
zo{}b$WD;gKn~rK=;VskC|Nr~27SmsTfN3>7S_q@sOdj6oMY~CygwkzOEN#v@Obcl%
z&}mv$jJ7UQ=>I=XrlmDt=`lTV9W1@3$ULCjF)e98>8`0h9h&+~Pyc|y?>FrlgS`W$
zEsO9(22FLhpnk}tew|z%!=@ryw~m;0uK@Nv(_;@~@b8;M^B^&5%2%ULV<zEpu#B6=
zC_U+c=?Wd9m@uiALtxS*BhT)X=^sj3pEf1>gLB3-@GR_gF|R0t6}!wkZLrDJ9OQ<!
z-R5ny25>XiL{ezO(;P<WYhLDPnkK!?PFfhe$2@rrDtydeXknqR`M?rX?l(&*kIK)y
zScx`&a|{n{f#xM{up-Dju^phn=CWQ?hL~OH3`eMWemg1;npIYiF!Kv5(U)*@`_C{Y
z!hCN%{r)1&-A_YrlzDSJc%seP5On6SxrPog#+v!bV2v{y#-SqKoL7!gf;pQK8xqYQ
zhlAy)`BA#iAlbZd6BHgZ2Y!OK6Xre|nN+i}2c<M~emI~r%>s&kWSLJ0(00-s-3U3y
zDRXBfhBVteG7BWfJVxQ{T=PEi_~)5_rIf3D^E+M8blPmDlT~NTO%e=3fqA|TFvaFB
z%H%6CukS)9&YIU#_~M*dx&x%#e7phVy!keHyDpeZpTiTWG(VmNy;bJHWzcZZVGeHx
z+9mUM<nXCBFQ<g2%jSPmP^vLYXm5DMyz4&<+f}p02bI^%jiIoj&TQWcwCm=_Y2kOn
zd@=;a+%)%46u#c<LVltK^HB<^G@5-xC^eajeId|nc6GuS-ZDo}DqWk|@#hav-)=5m
zhIj6^+1?7HI?U}9zV9?|rCfwA^I0`mdd#10L0hl+{W{3sG1qd?r@LmSr=hUV{0}8N
z^_w^3!L$K$=wav`GzXGvbjZx5*J{}OVK+K4Vy-Ab>7JRt2Q2r^vmE558#OO{7sWBN
zoz6l&F#kpS<O#Etwh)u%RWw~rnVpJJIc<KLG6-kP3l$J>v2=-G(=N-~<SKEs?EDwv
zyDbGYhHjRF?y%n7;<*(p9+p>=A?|6pPMZZUOKAqW<YQ@jl(v?>mK~I`wb!Egzh}zQ
zLd!^h%ZX&@4Y0gHd+-C6!<1SRXi-tTGRR`yhf=8Jm8ZdS(6WtY#4yX8_kkU5Nu$Ke
z2+Q4Ev_)Ee-inclvN%PdGTQQ+GxWw-7E}JoA<M;`<k~rGxi%Z-$6BoaK|aoM`$v@G
zEm_%+Pp||nLq`)WPhv+gJIT^=7i~u@l^>vo$1IE204>FmOuLlh7DFV+3Cr{W7?Wyw
zk$jA4mi@0lQ>Mk=4FXw~MdSuKX}NhCHsx5}@1U(^uH}h0(5F0$Yy}kNTL#Eif7;^s
z0|uY5><9s9fhG5C$QN4V6lW>26ifo9*kUh6TZ!e)EtJk$a>&(KYT4oq@iNP2H0PhQ
za6Up?xn<}(SaII6<O0MiET^sL(gn*7^2ItTEpER8yUN1z2iir8DhLvnEU%H1uiCPV
zvKB5|^t1u0vAjtu^D7oF+Qimc!f5SMXSuo<ZPzV<<cParVU?irrX?>Hob{HpOHk2Z
z$=M8nM$6?skS0q_7zCOvPBhxL9F~k`)V5fHBT(CFsU3n~o8@R9Y-+chsRP<=%c_@P
zeuw1*T_o9Q5zj@b%i`XEQn%%aC!nIo@@E<<do9l{fE9Nvv2!4P*D{a+>-#Jz=fK%-
zdF2~$4p<s#VjQxxtU%ka#WA-9tRt4HU68+L`Ts>+_bqv}H667?JO?sn`Ta*oj9Z-O
zH#TAM3IUn4T%~p3lqGv3<fbhb-o~iUShg>QCKqd}6_vZJnd>39+bW^C#LcRxMw`3!
z(oc}{uzFO(7*Fe3$5%kxW3^mG(Z~8^99Vs=4qEc<wYDAy=ss)55e&k9YsXS>`dN!s
zg45sH{wvx7tkL8aKVY4c34uWC?sZTRWc9iV&S2}U3~+{6e=bEQLaj?b1374AzXG{1
zt6Lp<9c~TY;($biHS9JljkMnR8;>N)>hTa1MqAg=>6jSnx(wKK$lB-%(8Jb*w;&&D
z-Apc)IO}WVL65h-Mh96Etc{m|l4uR90!gygybZY{*0K%IaMb$2Jy@7x?Vw=oaqIE|
zK%cOduBG2!s@1&##Wd^3KZ7UT>Q5<VS=J5o>YlWI`hPc<wRQk)+1BO%Kz)w&k5(9y
zYaQ@~`aJ8?v{}iwwn<QV+Pdv|bmELP;0!Peto81wEVOPK16Z;35cw}ktOa!B^Q?8K
znr=QRwSGcr5@pu7B(R>dCSL$4w<@fFId65M?brotYd!3)w7xhO9j&tZD^YpT+VmSb
zddZqiXQ8UC9&5pJ+4}o+RMuFhWnj5ty-psQtJboEC|$E&sX!-ct@Fpwi8|{!iW@kt
zTb~_*{0(a_d4X<Pi=Kmgy>&LFRW(?j9R_HlmHQqfnygnTi>=wpoCR{r%4~pKi&aaR
zajn)lS?ENY^-?*+JFH*QMBZt&)9LCi>!X_h)?>}uh*Gb0A$gtdSi9n&{;tFNVIl^q
z&-yAwR{E{C>FV<V>q5%>AGG#90O*j_|8KAiTLqgTKVq$?X!t$rDp!#E*1tEQYhzaS
z3doIHn>#VG53FxJ0nQ2QvM97oTBUzLeA+s;0%I{_<<Mhtu~l_L{Vtp1Z53>DwdK?N
z>Sk+v7>(|>3+F&QZ1d@h=V`l1YacIL6m4+5ZLimYbC0b!A0;2#AbF2`ZKc;x+G|@v
zyZn8&c}rmZe%mu#wE5XaC<f|p%c37_fNkb0upF=rFGkM-ZP5;I*d1hBL5{p&n;)$~
z!ff7)LBeh8&%?wBn<ve$k+$=vz!GI!`wQfwZFA<JGR9UW0O%nbvjT00ZO?f@VXW=&
zHFPQ7HcIbBf-S!Q_9ohL9tKIWschgpVymF7@KIaJpaZqZwjDL-;W69k%|J`B?N|i)
z<F+^GU}UOom~zX~Z2SdaNw?*E3D69iAI&0}wi{}oW!YvogXN^n8i=-2wvqvqvTbJr
zfRbZ7{TAeMZEGW8+G*PoIatova_N;Tu=UNS{a>NY{1Ez7WSdh5!D8Do+CP@qQg%cB
ztgWApv6tH1O^_(FwHToHoXwvO{FU1(ccOIOR_6ok3R{>60vBv8lmu64TSH5yDx32&
z=)^^v_$l=Fl5IUL5UOp-w4=Uk`vaRC$Lt#0ANL`D#r86tth#F3xD(jdZ0+<NtF^V#
zcA?Jp%y%HyZG$wG-moQ6IQpio%>+a1ZQW}C+F*;K<nu<`?I{>~%XXfQFSOXUQgTVF
zZG!gaZMGfLkZZRIHls_oZK?z4?z<hfCr-h{PMd@7*XgqDsE2&F?b8py+G8ua2G(BN
zL0bFVu^kH8?g5uY`D$Pf*jgyHbkG*I0c6M)P644|+bdZRAF+LP2?F<QQDZ>4Z;RLh
z4WqUavVP1aqb=gNt%KsL4{YbUVf}<{Hf>fWZQ~PQnX;XvxWTk-XE7>gY*i}&?PCAu
zd!X#HZ*n{j30M0(npk(+-|<DQoBc2ikh?va948+3C~~HH+iy_7ZjYTo-yt8n@OM=D
z+AVWI_S)a3yz6~-pEi*F_QmVbB|rO*w_v@$efDk$1lSF^C>^jHKSl=w?Zb4IBFG-O
z#sO=B?Xwoc#1Q-Y1`JTBokIzQ2kk4PLBj0wKZlBNdwT*vBkZ1OAd&VA5h|nX&I=(B
zZQpSUB*y+aMJ5l~KeWTp!}cG?P>QwZl7BePzF-_<5pSRSGD->d4P-^4efmGT@j1zU
zfoAC=_N`|DlVbnJ52fSwms|jI!ru59EKRk)O}~RQyYCn1VY>ah2H2Zn&!?44roHoZ
zXv(suJ`5G7>@5LMk!`<vA96W%r7z@i?W^b~mS?Yd3Ih4|wKR90wvU)78}p2PB`GYh
zuP6j5w6~KtrpSKI3G&7EkV@E8Vpo&P{H*;6x_#oD{oCc3{L1Yw3t-H7`ymTJEA34B
zaa7rzX>EGZKA%Fjm+fEE$(b7aU1y+Nu@A-rrPiM827x;J7Beax*X{FiAaTQfb{OQQ
z-K!O#^>*3w=uESHyBZ2_*-ud-REz!HX^>X?0`i`=*<BM+YPUDP14D1yOKFYQVQ(IU
z!cO}ISCB5d=rf>n+ubO3+GAg^9xT1~m@^pIJNC`vV7cqCC)9)X*<G@rso$>u2cQG?
zKLt=RX!oWRrXl+ft)PbO-+c~EBlf#Wpxv`CqMh-5d&eZuM(y#mYaX-r&_a3KzVsuE
z#RK~f^&k`WNGDWI+IRm14O4c_G%Ba<J19~<V|TRvgQAPGAB6#SIXAbU<m%i<A+O!e
zNlvJAbCz9&yr;7~5(>SXzcNF;xAQ+@=-uP|SqyCQan?8i&DZ%QI`XpDSxsZH&-t~*
zklXM4)_c(F=UhpCWq;?Ve}r6s^DE>sJmBo(pwD2S^Br>k1UYBWIwRQmRV5ljoGWOf
z8tTlab^bwT;frVsbN1|jP2tWTx_~9ZxtCn#k<Q2IN{T4wN(#|MJ8P0*MU3-eN{Kt<
z97O+8bJ*G301dIu>og#7&RG-`k9U^*kEZtki|Y8^$8+!9UD%~8?7e$;mjyJ@s4*Io
zPt-(XOH4FTW9%9=Moo-KjHW0mnq=ukx{6YjrqZNK2LT18DF_HEf`A~{3q?fq|DJsR
zzvuDcI5X$G=gizTbIzGrR|Bj$Y4@@ly*Op}#xlsq+dT+`rUbk2j{%ctCs;$`wB48(
zl#=XDy$zORyU!@_mTD)b{oiSJOGf}D-Ol<N`jTNc>MFW@#;%V74%v1amcaTPyIm__
zOs?H57ASdk-PS1O+ue4cZ0G{JIrQBvw0n<S=V$Fg)hHF&aS<Tr?acC^snkwOF6=Tp
z109BT!7ha6;uq~I$!%0_cjze4D(rSpW<aIgbxLchvXebTC#vmMo`CwxcB>A7)YwfS
zxmr7i4KVbIT_EOh25Ft03ppDa?8+zteAO;cjvhAJT?qnOlbty&cCOjkB%*ZPF7zY7
z+_2N_0Ow7+=Yc4-*sZ0gcB@?jZ9=+bC(u*XW>>TXn%eE&E`t>vc76@8snhQJ3@GZd
zyF{U*J9a$faTvPoE-ptedhD?C6Ay`9!(>R@vs>8#g@bnOG<w5!nGIlhZFk!X#A)~V
zslayKUD^u)kKHW?VWHRVvtA&+yA71P7qR=&eGEy$?im&^EoJvD@<?UuKKcSI*}H@3
zP?WsgF^6%P3Jtpl7^o=T9Y-B4-TjOf4VAksQUG&fw{axodv@Qt2V<V?o<?UV4($%7
zqp_X$T%}d0`<{+kwE6A%{TdVo?>R+IzQ{fM$3Z-9&q&&(oVsU#CUALsX45YSpWhR_
z1nMvDiCqhpnmvZ)D^YCN1IHj>_CA^e6`^~7O~MF8?>+V%uv7PXhM_WZZ?Zqo3irOC
zdEmvpm!6=lW^WrUA+GNg<H2%!Zz`qUckjJTAGIfYdjp~3`QH6>!qUsVpK2lQWS?sc
zeFyAIPNCArKEpt-(u4LptuY9J_PZyMdi$$xkdLun{TGHL);?-HG$q>KpcA-~?Y|?z
zH2X=Z;5=i0f!;Tn_Wk!DkYyiALHum{edG`*upeKCQlWj<SlCo#e~c11itTR}qOHWf
z#R^uOvp3mKF2nQo*3`99`}OaDl-aKuMLo2ivlLw`w^!3I2vph!W<s#ae%nG+R@<LH
z44W?5kE0daW&1pO;A`y*-N16ie)K%F)!9peU{k&Q13y@J)qe8`R5sdw(g@Bb`y5-4
zYxYCqY0B1aA4i|FPWzWgaD79Hf9IHsw5h9(c{dy8H87iQ!P-W~n(nk~Ohpn9Z!l)G
zjJV10?}DY3>DHmt#(X;+z@5x=`X)SN>?n_CfEoD|Z4T_0lw9D+dQ#rfK{lX(Rt|4K
zzbN|_wvGBC9p%w$lA-GD`g-(hOaM(R$4;cR{Is`x&^rCyU(x!>zyhGpU>xyx<_g-W
zIm?>@m$N&M;v&wm+zPZ$XIbO#XTj4jc5{m<_xtk<N;&-^em9Wk&7g?M{07Dd&;OT`
z>9DP@!e^m*K_b1M7Um4#|BIrUa2dW{szS};HA+B#6a5S7m(;z7UM=1JIeN3~IgQ-%
z)wiH*#S3^~q$_tV1plgeG2maVABEO6Z`1qX+rF<*v-V9&jaav=9Q^B#&@OAkcfQ}C
zVMEO+fPP=@iK>ml1E|@&nzE&TSka2n`tkWx2y99AL+ejP^HIMwn_js;e^0@zzh#ue
z;mYVK^VE&GJQ6D0nKHU1J(y#ZvFgb*4WjY@W7Gg-FJ}F3u*jQf7s+Mo!<_8{VgTcJ
z1*&c_1C%iFh*=zr%E!!3dVjuPB5-R+hnOPzaTiy1^JEY=_Q!FgiDf9)#)FNIN6C|&
z6bMrfu%&WTda;^Cq=`L8ha>v1&5tqoVQdX8Tf*6eEg*(dtR20GV%Y_hN)pF5P$p+Q
zJJt(m3G8j!*O16I(0zWI6)poii9JZJfn+wa5-cffSQoHU*<709q_O>@QA%f*Oh74v
zZ5)SECR;>4rYzRI7?s&<<A(q{!~ILHu}lM(|B@QHXitD<b7RIsVGcL{6)JPN(xYI_
z<F-UXQ$9DI!Z-z7T@+vnIp;x?&T=dM0ZbA16}bkAxyzJ+UBdBSp-bnu4}2kap8JT_
zjHR5>c|ezO0Uv|q0;eel^hM6_g(HgP+%t-&RB%%%@u!k|HW#FdbDaUuYVM=4xQ3TF
zqc5T9GPk!LhSqSkG!3cclKzFJD_qS9wAFFHa1f~H66hzm8n`SIU|!{RY=nkJZWZlQ
zYvO!H0{R*kt3W5NbG-)IK6ZoiFM)~8-0%!Y+~gK)go+mKcY6L>xnc7B-r_p*ps9@;
zrkk*x%b?AE9bC*TklWm>7eMLcTxrGJ#jWZ?=?=F-1BKn3+!=B`+-`bk?{cQT5WmM2
z(U<H#w=ICO5gu@9iy-)rOML@8k2r5iNO{cNqxIbr&UXR&^pwN#-uMP_-~5isUT#$d
z?Cs;mzk*ypH*+i61~^BGjy&hSD+Bf*_bvt2UT|iuAVXZxG@v+0%oEXVN69LhbEZfl
zKBM<vs-$r@K+`1MJ%CA<4APE(3`vy|rk#=Oc?O#@C4vg_S(4g&(3>p@r>FI@B$po1
z8i~tDkXp&&HgH~%ETE%Ink8R-4)L23pIhMUl+3vco4O<$z6WQIB!af}-IYxInX>WR
zrTOHQ@{lf0gi)T-JCrKqEwwy^k@b<<9zmtA^z|{w`$?D57KY>S$il)LDZddUSNisA
zkUVJ>J-+!;vj-3_kQURduTYv5f-aqvhN)mhk@V*q&|55hgX}$r-?M;)hV#-J!Kf{j
zTG1q-49-Z%Uy$B21KLIDNj-SVahfvpR^UK3^u9$l<u2q~WhW1U+>#0RK-y%(lp)bB
z`-46{9Wrwo?%T5W-h%p0+4F65wPXS%qV>xjjz-&S*&&*GIv9*{X@jYw(c6^u;bi1N
z!7MMMaO#t{ktdyw=3_LPEcG>NqG_AIku^Dh1B~XHfE+YRtp_=5R7$@Q7-(cg3yvd3
z?^4RlQ6mRRehf8g3kL}^vZLRh2sc`I3HC-C?SG2O3?l=AaJbAyEyqAIjeeev#w;VI
zi3Zr{4LTko&!}k!+VYK3Dao|JD3SJ@7aGmq2xHC~EwDl9f>Ail#V#5-(&JEWv^x_5
z6-G6mpt92FE(@?~BiG{)zhw0GHuS#HNctwsZZev`j^?%3j7I5T+jXN_a+Wq5P5cw`
zH;s1Dw7A7+{|3Oc8ktuCyUnOgiOO~(bs8#f8x70{OsA2A-Y|EJM%SUO+bFIF3hx??
zIvQ~V4u;T~(CcKJwH5XT85d5$6$v(ue2K~s<F;!kg&OzV07{tglOkvjHy%|0@ngnH
zints%{*Lm4BaD08!4hqJ_y*L*7=KH77AK6~CU5&mV__83#u`T)0f{rN`x7Yf#=hpz
zkYK#oKnMIJ8h^MG#WTi#PKOnl#_qIDAlrD#3z(f_EISX-T;rT{u;dx5$bDR3Y@jc0
zp>bg%+Rhrkq!ia8<GFO=XtD8*{ir-=Y|#m@^Tuz{l&I9$F9l#_#vNaw?V@r1VhEHQ
ze>9Wg3KhnEyU|!>JcDvYtBogYhNYK`ulu0XV?2*Gn%p&>M2pP(#?G|fcwj7hg3*3x
z{1!!M9~pm6-?k^ldGu^OHID2DXRq;R^wR1xP9q=DD`OdblwKP<P~^}-eqtOr9p!J8
z&;-Xx?nwSgXZeDKfN_yuErU(2a-QC@Zt|(`qtacjB4?O~{N~r_p}%};5?BJ{k7)Dg
zA^F4+7_P(er<AF4L>_wta!2JmDZ@Qkz9a&gQsh6<CoWBXghFrW^7%UfmLZ=OPCn@~
z@`VGa&6JO(&vuslB;`$H%Uef7MUMQh4zT9RD_B(K$))tU&zEmC#qC%ipFDuEER=iF
zlIE;@=5B}=$&*JyVX<67)A$m3PZ3=TdCO85b6$Rt-npgnzwBXenf&B&v>7hQgUB6w
zQU2}@G?vR7L%>=g|DEo~N_imdS*VgnQ69i0dGY{QF3XpWN4IO_c4uKzt$f%G>aWP1
z_kpuc{`)ah*2}&B2hIlhY`O)m%8xz<X_6O4g7cc({6|=LT`u_?r5gsh_ax9}`J!4F
zd{f@L66#yzuUEjfR=Gd<k8jC8rR}Y4@`W_-Z<o)EL}iD(WGbw<E%(?D(kY)IMP--#
zXX?`(xev|wy5){E1L~2N9zh2K6z*EsbWjoYEd)XoJt8ne6^6YE7#ybXkH>8iuJC&s
zjmH(MSAjJ`A?boKQHt<jkZ8qk)6f>9kWl*F2}MI1Do-i4ABOd@3iqi%iBr5m@#%QQ
zzkgx45*15mS5uPWb9aCxE6hwFo~u}80!4X>Uw6Q!0>wWDN*OIwc$@%enWB|)V=pTl
zXzEm>sHY`*tzzqcP9jAyo%v9wNT<CH^@_($fN4<ZGST0w3PT+RxKWXE26~$mGlsy~
zuBau?c88*e)*`nRP5V&UsW1tJzAnXI^Z~e|sG3eO*>1(uN3gp`vA-JF_Y@!bq4K`s
zngHwviVNgUdZ@6VeIJh$tI6B=SaFy(y**JF(<X(dimW}rex{g0sXD!iDVf0TQ)uWT
zKA?C)(ah(HWXf(CR3y{<?}cJxCs2kI*Z-!|@Lwuyo<e?D;TntDSBkzUlwK<moq_FO
zQauu;Ihq813gTokpVk@9CJ}$5<YHns77ATWOlgCeo5^=HWpg)qrw!I0FiD~7>SeNr
zW((dXE&ky2HQ9ayB|no<B24o)si~#~Mu3S(%lCsO_4GI$GTE^UrNbsVKNuWtl1P4r
zV<zvCkN3EVZw*L<Nf^CtqfCCFBMG8SzNc#+W8zA4r8bjn@&gT+OeIIPgQ>+I;B++I
z7YBt-rYn=ldeiSlfW^i1B!|&9xSD3!L(tPyOY5%#rtj^8iC(5zy8!BK8eRYuzNQ)E
zYxOhTMQ_Uh(-)?IIcRz~6)Z<gGil$}QPU5d(H3O-;UQQbZ2FR%TA`-<D7Q7t)Y%KA
za8qOQ+8r}3*$aUP(>4lhMH)=amP0Vgblq%#Mw|X=1x+VRJ6%wD()30Ncutv`?}Qbx
zrrNC_X{NL22$OWvNi9&HVVXrQ{4=HxZ@}zK({+@rl4UA-f-~E6(gbkknpRS7P@bu5
z6^tn~{cRQGicC9$P+4qh`2IKOtu;N(!?r7?VauSf&NP*F{?(iQrUGd&U3wa5S4}^2
zMXAxWie5XnOfS={yUmoL5NW&V|0wX%VR~x<tnV~E>ItwO)9D-(-Zgzi3&?w>%663Q
zo4(El%Og`SnnFA_oo1j+%qOO$lW?7$nocBlMZf9Z?H~iDL*!X_ZmRzpXoIFts$u90
z(@D>vX~?wZEm-l=v|>Ee51XE)m4uJkCm|rdW;x_K^)s`P1JmEE{vT8Zm^F-q+(EO*
ztB^ZnHi4E}ht29@DJC0ec7g}?5wlAh(b1!3o|TXfGJ9bQ!C<q|7GMc6`{q1IsM-0i
z!5L<D@)%4zW~S%^=W(-DMj#Ppt0=oA(rg<o>Y~iHTm)yd*@yUHI%$kq7oClN(rl>|
z8cvyYlgA*|EIo$OedEk@bb3L8naw_QG|{Y(HX@xi3#6@5NoG=ekYuw251^%(wNbu%
zs#(+=^dikH<|oLdo5jmuT87y&O7P7z`>qx!9_B0VgLs-7{|3$j<}-h#-kU$qgx(PI
zXP;4D%&#Ex%peUjx1}{pxcTBukT`C>sTNlx!u;+V)ERRV2^2<|M^GR?+Ps%M#xdp&
zUx1u8k9!V7&zP?Y1<5oYiUCTN`8#idGuwRX??9<EpHF_xD)X5%MXWY&B*#I6`55{(
zUNwK*4h@Dz^SzYW(PTbiDong)&dmkSb@PYx7P(<Qa0`{q=B^T4uAAmt-+_u2^ZorO
zwVKE5f)%&S8!5rQ&3v0ZtZz4WIRJ9o+>Tb5o#r_d-0w0kVPVW2^W4cOb(=q?(A!h<
z?pmNcGnl81L1VA^;p4Eh&%F6#H1?Ypu0v_Sd<A9dJvaaI9IO~LzeWD17v^W_B!?mM
z%H61ZX?~mh?8D|;=@^Vx=D!+)#X(uJ5OR*nHK)Piq})Q^RA=QUl;7y0Orfn=uF7$L
zL6Mu%5Sx#pyV5rUtRBh`TcCL=_p8u&K&d!^N-yQ%KOpF><Y^k}qb#Qc9AD*qihTGf
z?<S(sU%8ToG(frMEwmj}dZ(iDkaANoE=8a+<G*>4GBp7#N0lCw*A=8ZrT}NK@+|{-
z{X>)+X+0CFTtkN+gelKYg2Hg+Xv$PSru5$en<A8IE0iLYeMcY=r4$aJztKwn8nneI
z&-+5|g!0ohkUOcA^n;vI+FyaDIAt5%!12mZ+CZD2%>4m_m#F-af+MGuuj6Qylca3;
z?-Q-u`a6tDQErO|XsXhr1w3iWA8AROuJoY=REBcd3-l>dsTm8<ETseOb;wp)Q8sLj
zatx)P=PJ9uhWb2ZVmwOu%2)KZEl_?!sq|&aD}w;Lpj@*HR$NrBZK3Vf<;piG9)CsI
zkqMqUr5~lP)hie6MP-9hXaU+)<>XuFeWNnE7Zx@ti|NIBO<CFwf$Pcz<c_<c45yr;
zW~D2wDQ_w-(lVh%`5SqbT9rXZ0d`AyzXSqp%C3LG(xH^N(){zbGSC@a>r{R<0oYy2
z`g4%Dqm(ZNPq*@O`nvQeZ^lCYuF{RXPWO~o=`Ojioc}Y>9w^8EjLL^fE7~CTNO`vs
z0*{q)%Kv$$ET)}sy~@p3(blJ|p?5;Ra{B<tfYOh4E*PFGkJ6NJP<bdG9etsEw*wN6
z7DEB3bh2<ShfU5FgXI`*7mG5=1aq@kMw1VB3!7Icc~~TGheA(_e`(fmz=An|HZO|<
z__RyCEpDwxrH@5pFiO4_t6QMg&!Qv>iu^6)6(9iy3x^+|Db{lT8uTLGay+F9C0cH$
z6qY2*HQ&OR6w5V5P?2U?CxA1<auVeoWm>+R3Qf6|LtlaOs^uOd+zIWL{dB@`hvk>O
z0K0AJxF4lXOKZ9!U6#Z1A$P~}9DQ7#SRSS2)Kg32Q}$r(x14u0A_l9$p%EC9A<F}{
zka%e+qs@uKmivoQ`O5MGCun+YnMh|)I;c3hgB?|${|yyRs@WRcSI(;GJ0Re#N^1wE
zk7^vPszO!4l*k#TntB@6A5-<yJNvk*g|g=(RG!;Vid5bC0i4mQ48tGPZB@VkB$8E8
znb4b~8h;KXSCtn8g?XxlKZB)IrK6=lnQHbCx}R0SZ=>y^DuSk(<*JVLAQdVDZAGh8
zT^&YSmFlBtR934#&wy!{RLf3+TvoN}FbFlOFq+}ks-izPfZkAr{{%~$RUYIvx~ZDr
z4^1s9p#~DIs#m8`x~1}0!r(U5^b;_qT@~^XNQWxe9BsE%-~11yPL(TzQkP0WAFey9
z!OalwR=uX!PLFDb0;b(njS+xyPxXS*JnpO1|B}1ufvRaM#^j;u(eJSBk;-8;1Rtvw
zB|`9tY72$_o~ok9q4Jq({xC|tsz7%r>{CV3=d)k6)DwCKRIavQd9FI5fQmuYr5<p;
zP&tv0aY&_l1Pw1$zfqWNShd2HE-0S>*SbOK$R~^hj1wO>20YGu<q{AVKDz}xfxMDV
zWIn<N`C(*&_@k5*8_eSXDO_KE*JKQEIG;hE$YcD(ZLs$^zrO-jMDW>nQHtaj({wJ1
zx9NmHG(VGk95MX4t0<k|8$ZW58BX#^>mYxMZ?1seSl;n5YUB9n6ef@7*V9oo3H(2l
zqmanIoC0G`^KV~<iX{HmD5yy0%lpBZ!hcI1tyI4G1E8ew_h~0VI?v&NI%x*aI|Jnm
zpT8ab%;dSZA)dw8(!?>_z)v^})*OD+FR(P1@6SUikKaeRYWaL5<vSJdJ+w8lkgvZ0
ziL-o&B}zqn)1PQ7=9Tn`Ea5kiv+W#TUjgy+{5@KEmGYJ3;VI);+NgDbf1jSai+orI
zSjze56soM?4P{z%t&%@dh+-A*K=Z0<KBW&5m-tG`e7np~rdV(d?@XVwT7JxAa9-j0
za&Xr1XX#0;=S_5IYv6VCrM$`?q%G@>e54L2P5gs!h+pGXl!kDfH$Q{1xWP9xql3--
zOv6YNZ}MMeg0+R;P!7_{YhM877C$opq>W!V2MXKyNwg=WgP%vvtJ{3|FX&7sZ#ETe
zUA+4iD7?deO-rV3KK%tMd-%;JsJzR+QwT%v@ngwtbf34pjd6Ow>sF%jA)jML8A^}%
zp0|MZn9n6Q!4rOTJ{q6$=P5q-jQ`OZrC#3aC!qE5d^kA!`EMeCHo#vSgr?_wH|;PP
z<o`?ndBNAyw{3{8N&)9fe&srd5A!Q~!1;>*ISJi;%`c_Ieg`3bGi3-m3Lh**t&_0+
zD%3j*DKt}d5nj`VAXj076eH^<L|;J3T`->mn>>Ve+C}0iEPo7}4hW5fX!8;*`arye
zi!xyQ2+!YxoUd>%0W5yPopQAK3yZHoQGoDiJ&ZXh3}F{Ce!fDmvw^{fg|Yu_`w~{}
zfr=x-S5F{uRQO;JXhFh=0+3+g(~AHN5#FQEcBqg?5u`97hH`Ymh52+R921_^gXOsJ
z^BQQ15N19@Um}H%X)8^Xa3~nYL<<V~n8pZp$G~DZArv$L=A=*(0KrqjTG|Z~E0`q%
zEl!Ae0oHh76D`gXgii)R5(RB4$Z6sFELf2wI4=Tdve2#pNfDyGQJE^3&?c@l;SRml
z(}kvG=wODBNjZIIgt;RDohevs1WJ}cU@3z%TlkF7a)fNk`p6Yd&<N!TCMTdiUvP{<
zsX$oj35h~sv<FIOg(6>&B4JG!1d4?-+rU{Ocx}QsofFJAL(_S|T12-?g)ze@l?hc8
z8N47YFNMHGVbp4na>4K@1++qFphTKV;leeHWtGrCp~q^$D;=Phgnh>Wb6Kc8k6zRW
zW|b(_3bEtRiz`CYUVzpK13O__y)cS)<2MK&QnKb%p*ISoQFu@RuqL6DUP9M|J_gtI
zy0Bsc+HMGo3_L)ag~)H9{-$t<-bF1!cLXY1h0Wynyd@NVhPF1r<2#hvg{_oz)gk0u
zfc$OY6ge9@g*KY!cL`_6)p<wwH6EsQ3-emg)*}>s4!OI63B}*;318Yk{e7W^7Tpho
z$8Q-R_)u7^fr>{$A-VG(3*PzQc_NH;MAx1Qt;GO+CI~b^=oQ|{2X>!OL8&DDLh;|Q
zcR+|;iMHoL_8TY-3bX0HdLgW&cfyeH_9Ae;6ej$F%3;BJ5zKxiOv(XyEm*vu9V!m$
z7b*xks`Dm5p_6(Z`MjOgnUw14qW1p~tgh<AN5JByK6M+K+|`F@+U%izIS6b|bv51A
z2h<->pwLS_#}?i8Ry&Xf!ACuJB~X0Ty(*~pQy-=*2!HjGAXEmZ#~^rVkRDXG(iVn8
z>W(b%99Db3k3k4jpT7;BBkH!D06nVq83lzwYR7zN3RcUyU`&YGl@1{YRfp3$J524D
zg0^tABe_FPtLJV*Ws+J+o|a_w_jbTcQU6Vz;Z(I3d2!OzITW5Xq^r#rLvMz91<eZ2
zsK1~IWTv{_4VGr9m)wGB+3GtEV98NSlc6_PtvrGO%2N-?pdw%W7e!kO)EzRALiK!d
zC!SSDd;(2H>JBdm6ssG)24;!cZ~>U-)YC7cbY6Y63#C$n+L01x%hW+Mi@u=tq6N)G
zHAgS|a`pQgQL0c6Ob2$Qy2S_*RqB5?fmEwY4g=<r`cHZQE~~`|7+RzLLI;6b^@DKq
z_lo+TLR8kN+e{!{uYNxlW;dv>(iOR?-rEe$Mz!G~EgYNF%K{;BP5n&{48E>@kG7rN
zP`h40x0}^h#)9>xT3889E$WzA;A~ZwP=w=_x{sdbHuX{R6}GE!bOas_^+Vb&b6b69
zKfpTGhj)UdOYQg*N_W(;EZVx&^Zx-@kGk4W2YOfSM_!71>M<XJ^}gDF3KTw2|3%xE
zAF7{U$5=d4SKkA9tY&ATPfyfdVKD8fx~d(eXX?3hut~3a^jVbp)GC^P_Ny0f1j~Rr
z$`mNi)nh+~`ayNiG?ZSbl^P7fkov0yH2-|5?wSjQ!|J#;kXP!CHPG~0{r*MR<RDJi
zfv!1<R=p@WiIp^~bQbM`p~*$mzJrphXivLt+{9=HV7rSMwA%L&>t8{Ir)Wbi-2<XM
zCBS)!?{ov&TWlgPxsTYpgARZ772WA0<0t-3di}+<6+jCRM@)dkLD7XS%puW|CLf2z
zYm-nJC_2QzrX%8OvgxSkJ_e;A@v$FRg2js~(1{Q+coBLZD&C)qu?Q18MYM&BWtFh$
zm^egx9gd5^NcA>IBgB2=kBAiGzJx@SIPoS*(c*|`SP>)2XytW6ygC&sPKxH_)jTCG
z3q)J2c#VELBu-SV1$MkR_X0?QxVi$IiDEqMZa6LeLO*?wBu45{N*4XcqLd<9{RQz<
z(T2WChBUG7TS%mf`$vN(L;QvwhcjZpG*o7aOX!}<67_UwU$!{*Ap~<oNiaBb#VeiY
zeV*7s6O(*#4ZYV3#ObdAS}67oL(^HYloq%};;-cSC>CAm)+rHV_W<*pD9J|Yyg{t~
z4y>i(<B6y(6ZicN&<mo;L3Hh+IEhkM%EccV0aGCsQB0&#lu;r_mAH>SK-HqZ1z;|T
z7byAWve?ByyhdDQ3@d8IIJ$&a#BqN>eVrKM2~sbPJ%Y*xad0tMu8M|H6z*&kf1{sr
zZ4wvwLE$ygk)|ux#fh{cxFOD%57uTeD-H5D#rZU{Euw+8%e0Cg+d%G?_{~_@)F$q*
zfIz$WlLme15O>mUo!g?R0EM06546bX5`V}?+a1w{PJ8VZ7Z~U@-6MW^7UZt@&c~3r
zCrZr0dS6VXrNjfVw-xFiifuF{cqI1Aq42R-n}^a9(S9#DpNjKn4)RP~Kr8BAaf}bJ
z`@~S1SoDjzl=n9vrjTp)xj4EQr9m-4fb}oL(K{*Kcu4%0);upor&W*`7B6oH&nwZA
zmIANE7CW#wXt-&x&{6X@1?-(P+rB}`S+kqA9J*-2SHr@?8lzz74b)twJmVvp`Kusz
zRI~9f2n1>TJ<%4dG5rjsP|fmq2!v@qt0Zq|xMqOX9>+BNe4riIC{-v$XbuFS6sZaL
z5fV|F4R6AxXpPSS*d3#pK%gfy{MX<-sZqs1(<#ltZ$M%-b8<l9G!JgVig=CpE^sDj
zlIbYQL`^O^>rQLde*yJLnpsF@F-TK1yZ(hls;0*uBuyhughaZgVk}rQG+s1qIHS2q
z9@<QeOvE^4Y4YcRWNVIp2lY7`ck;O8YBtd3n>@{RTDs(GR_y>vfyN~cZH1Z@8_{-F
zGnO_^6=`xPI8dx<nu>?YP@+Ky7SDsGC<7|aYp&CZqEzz-<=vKP{x<<uT+kHIlI^1A
zZX96BHG_1NWrb$-5Ux+9X8dO$RT}dgfL3evt%dqa8U;CHFKa$(21<>_p&F!Cll~Bu
zS2VQ;Azr6B^BA1<2F;-y&<0KL3Fy75S)~SRqo&~?SerCgD9&?DlTHis>zXX;{SA#1
zg#nv2t+aHxsi{4Nk!{hupAFDf&0BNmanL-aJb^Y%!VcKfuGvH(uMW-c{{rl`=B-?4
z=+s1Ipx0d*!-O{=ct^AC0cyK7h2-w)(Ohao<y}qGOlZ2NxlB7@?`sNuKptq!tf2Ry
z=4*N(Khl)GLyv<d_5+Y7n%X!R`c$)&7I)7yCf{T5dNuWa7@$6l>>9xOHAgmsb3kMC
zKUnx&^Pb@|=pEEdrzztL&9qE_4rxC92s|$}PbhP3So47wSYK(Dy$jCQ8aGQ|J7|N>
z!$L>xdp|+IN&Api8_wFri%@dWwk1H$Rr~f`V7h77QsTM0c9=}_&=yjXhNm_OfoSOg
z?cjKte|l->J%_xvc92qQe6+hL(CMrFkUr*q+A&SA+h2R}3RnWP!<0jLQ2TZ$SPp4D
zIgrEJQ4|0O)P7INB}cTGWZ_Y*UJDYW?VpX_2Wy{9fq014gtoqhYOhTPN|-i#9z_Gg
zwSO)L%rWhi>5w?CEqn!u2yOp87!#@8y8wNP(st99`DpDCDOh5(e^CtRg!T_NkdxXS
z<j6Rsjdn*VR_pZ*?2Xgjq!Vo8wcV)zOVG|F=T)M1JgsF<Ytw0tn54~^NdA{(?czPS
zuqoPw&frPaZuuWZHci_*3YyZj6XVgAp*=}&y))Vun<1a69YH~-EbU%DSeUKt7(yvW
zE0U8jR~rzB0nXFDPdk3|wc8Ityg>WGF(@q5{zPGqv)TxXOBHEDYEWq?*81Im-6dKv
z4``*@rO!|*(^fA8>qTwGJSZ&JzG(;b7234N5UkX;52I^U+J8PoTeVj23l*2N5j69=
ztbIQgEH&D9DA%-B`!olfSG3Z1QCX*5dIqFkE2CgjgSLRaZC4H2P;!zqY6qeL)1+Ny
zjnXx3<SX?4x;8Hoow=bswH1{&wSOE&WsCOkn-FZ(F4n=OTiVCJfV63A?*qGCt7rg9
zhc=8(5WB54w}us++Kj~z=+efYgE4osE|hK5tsP6@sUEFiB28-VYWLH*ard;fdtlpr
z?Ry0v540aUfc2rajONsjv?Hg0Jk|!$qW`J(bJ{cUOl#Ev^}X5|A}af|PIDmFugxG2
z?SR%p4`ZHd-6(rtP`iniCoi-UX&>N_b}^;$ztqYMv_c-%X3{k2m3A=&4qt1RPlP51
z9lsH1j=J|~{_3RrbqrXXb!k3mbI~o;K;Bh1hjRbibQN|`=&qB!2B(Mab6T%@>VDY(
zg$H!+TtcOn?yrX!3vXQ|oz3B+yG4(^uP&FTmzbY!{eSBs-4{0@7@+fgAC(7n8MM3p
zkgj<tEIh3Hji#}Ix-s+%-A8n~FTiqC_vQ{%2I)pBVN9@Y%?WUZ=z=L>EL69zAL3y;
z%MREZu3NAS!+cDaK+cWhx;?Zah|moldt)n}G2M(+sEyLiS`PKmx|}sA#pr&d6v7j_
z>C~r_x_U}OKBa4=l>AuTwhPc3r<*$qrFh-_8z2d~6%)~?MBQ82Ag6VcW`ZQ?zA;5x
zvhKs9JM!>L6E)5-J3}`-6<}v{Ev_hK>hAXgEKA4J<B+Y3R6~1??hb9d$kp}aqAz*6
z?joS%>mE_IY=O>#!gz(cb>q;9v$}%`s4UXGya0X0y0%I{m*{rh$B3NMZMz5!=XIH7
zAf>wYqsIA+nPDx>4KM0k;?TcxU4J(8Rp@j%&|azgau{l>bS1k{s@Ba41<NH}_-$yo
zto!x}<Z5&~-i1J|?%qilaYc8Aaw6+=<4a*@z3$OGC~DBvkrU>sPC*BmH|iQG!K_I)
zjZ&Yl>0}0L6tC-So`dIxZt7a7Xx2Hc2kTAUqEYBli>_lNDqD4zJ_YA3or*49n=XAJ
zD%*8`3Xtp2E%_CO-qvxWpuST#Vgow=L^pgMHa*qpvLNtG7xOQS>D5h42I<q?rFUh&
z?urwA3<q?t=0VeQok%OZL0!^QlwRoej|1zFE``!IU+UWFpp0SN5Usmj>6-7M?X=Zs
zTW}^>ouSPuDOOwOLp;sO^((ZcTlLezHp5DB2Ns^OdR~vpOsi5_*=1Y#R-!MtR`z}5
zamce;8UmgIt4#-iR%mr25v*se%s!?oX_ZHxkz%WqlMpPiS}`5=p0m0}L89|kizwTt
z)GCYu#}}-2KB6mWb*l!(lv@?g152gV<i8+SW!2gM&T1>!22@_Mnn8&Wm#z416#uHR
zid%>gs<k@y0*zO!tbPSdoz)bY%hp>}QxLJiYUU71SFIk;fZdH&oh1-xvbtV}%4=3*
zX-#(B>N9dI-LNXAk!`j*dIo0SwEEcroGn(DX(rxkH6{#|x2%j8!KO~DFDaB^=(d{0
zqu67$i9$bjt=#FT&U;qV$f<wdYGgC6;RCBu`cgf#N=}BvBdZ^N0p}Ad$1Om6YPBmH
z*w3t#zk>8yy{4?HKC7E_GIzh#FK@y60ju@};CybC>H-S~ttu#M?S+*$9ZfT2uriv2
z+Lu=C^-wWvwf<f7@RiljbO^q-O8Ocw4*F;o7sgS4XExfL^v+q3ch;{XM~RExnZA>*
z`T!|d-1If40P3z!nu|6M{alK|dFr<=MPCl+54A#rm)=l{N^gBL{lc`5-tZGmr+oDm
zH0ANruWg2)zyAG006nN**^J6V`Z5Pd9M;SJ2NI}X5DXPZ^d5sycvL?>3@kzV@9Db{
ztglw1qaph2)4&YXUw9LhVfqQ)kPFwV$hUV)pFJ5Gj_Z}=OpMU4H_%r*Qoow+mMDFk
z8YD(PbRRG$^rP(2-;?^|6k9u`U-LJHBv$W44##+XBL|YG7wPSBTK`ZFP09KNe}bgw
ziz#B2sy}`gdeijp5m>suw-Smn^xv36L#BQ+`G>OfvlHlzpRI4ECp|}hiX6(hdSmjH
z=jpA2U}C=B<p;nN=nKM8D%AVavwc>7Pyte;pZO*#i}j`<P*|eh5&*Ds`Y(!L=y`oh
zE-Fj)TRuT2%JieZ0OkdKa~r@e>KD;;s9c{vg;qS3`aN$$qDmi=1c_?BsU>=GN&nsw
zlrHPzY@nh>f0B~HYW1eiQTalD@ewq+Tg%BC?`a)OUd#j5pG2bVsI?cRV}w}uljA+y
zdJ}o4Bdq6-fq1m_=zS1~wLVN|TEtmzeL))>;;p@D0h3@|Lm!7k>(H~{Ic+_AHLOUo
zmeQ9s+4>2&T~e&;&jBXYdL7MI)2vmr*F4>NQ2_L2Sbs&?V`r?tS`PJD)_)zNfwewI
zFVqriB`t2wS&w)Na+j^cD7CA``j`a0Hq=^w`!n=jvA#kxr#fqAKNwSQUE_igYOwxm
zGRRfyv=@MBv@R=we3SLtE>LmJ`Z=99dfj>%!Q8MOLFdLaTlZ~(z)fo_YmgS}B^jt}
zwXXRXa<{DgykJwC^*QqTv|ESMjQF;}dj7k>?zFyi7HG~k`QuURV&g%dc~_fX+#u*?
zGnMw_gxUPPkA~D{CIxMd*<7Zr5XWuw6fTUg+58jQB5k7o3*_3oO)KFTn|t&fIcc-K
z87Rp%i)oifijBz|s7$r_%myUQ#_;kaSkrA5kjEjzCjJRZXKc<Lf)$xI429j#+I&L+
z`XZY{NoXs!5xxMaw23|sv?`kgt3j%5-lpmKC7X20ey*{pprG0noB6bOth4!uUYad7
zR%NiT)n@J>FmKr$q6k5o%{4<bG<DeQSO=KfHpk>3y*4u_VBT-D`fsof*f{7>dTz5I
z2iIrNri(&dLpCjRufMcOBL~8;%}+~EdS&xHWpg;#o}m}2qwTB*P~l`7_!q2jw*ATr
zZ7#NXKY_T~o_>nnyV*MYZ9um@Y`0JXy{GN87LWtBn+~BfUbYTjz;18bIq%Sm$~Kci
zpuV<^9#HRR%TVrJfbB5t%{^!v`W$VCY~w=E!^5^SXax{xE7BgVBepZ=g7c`Y#oI6@
z$ky2%Z6UV%==6(F+dcnK#4Fr(J8dmEW;@LeFeh!NC!+C`t#=GG#o6wo8zSEJ&U&;Z
z+Rj^tQj+bLwDwK5T|n>96x*kiPmyXn<7X&Lvn{3^`*hoV^cKjlolSXpXKYPpqb<|+
zMgd5c?YqYTmTfy{AB*QN$M&QpYV&Nj_e1Y_+bDWlm)ibBDd=Ukmp+8~7i`ziyZfT8
z@C=pZwx`G!T4DRl1eH~`2ex4>t8EvRqwSLIf|qE!YMX2i(rEjVRvxXkPbf#@mTl74
zFs;pYJ1w2tZDVB+Fm%{<(Tw`GtyGD|PTK`PVuZSEXU9YSj_pKx;<|0)S3$nV*5HcD
zySDa}rEt&Imx26!+fh!i!heLBgo7&l8(VM!K;tI)<L~%?PQo^4W)(dhF3gY{BwU%O
z|CYkcl{yF-+?nru!Q;V{heFts`IEjm2be$UB6u;ckoGMLW!BK-{R}gaPHf6#a%h#G
z#f+v9P&PB3ZkilsX&Oqo%neG%%44>MfhC`Ly9cCzshbJ8Lgv8V=-OE(B^li>V)WM_
zP;6j!eF>ft=Cc?S&oLg)(RiM@NuU2pW;gCu*&QZ?Ue_*cml2uIMvaC-H@5Qwu(-2x
zE<wP9JxmGlp6p|!)M0y<hCUBo?6C|GZ+6XR5b$B^UxCw?Z3=>%AA5T;!2DUmGRhhX
zVE@dA6$e>wIFV$>+0PK@kkzxTSYONBIOb2lcyOivW8RPjaGUKgmPfcxC<+nE-B|&J
zDcoH6nf@F7X|0#=pHJST9HyBq#bBManC8@T2CqWF$~ua=uY3Ok{N1X%2u{Q94RkZw
z_kQ}{MF@C^A@X9}cR@Uh8Kk?egjx3iJxcf|{PP)_UvbGZq5C!W)~B$`K@xJ2dLr?p
zZ0i8YM%oA+Y4kh;qESYp{{eWk(d~5L#TX@#Ywea&@fs|5lyCKs{)b9m2Q>C61580)
zDn~hiI9u!?*U<rsk15S8z~UwO?Sd@U*rRmZA|nc*CoR@ezQ-wxuhznfSc_>#AQxxh
zL4NOe3!wp}1dB<#(W^v@D-Qs6+Ttfqh$mS@Q4Vvm#o##%PKLoEFb=GF79U>%DY0mD
z09v`l*Z^2sV=?vz$X~OFn~ApT7R}Xwxnc3S0ArdhhQ5UQn--a_AP+5~)`Ihq#q~av
z9$V~&FH!o$;@>kUJ+*j06$+nOoY@VzUW?V6p|{Us;rkHiw=g7J0rr4J?q2W=T4Xgq
z{R@kOlqEi7!Ms4_OAC_&=+m&pN}49WviN>7U|w6eEC9BH<-slxN6Wq>a5`DePe;k!
za@`J~cvyDPrSP=0ISjc2mT4bDk(Z^DIZ6SRL6kak&@$iPhK?SxoYjKMb=cCk6?y|L
z|Gf>g7|U~aXk;zR_Rx@84%6ussg{3#3H2G4C0^)Zo@MtFa5h^8&qdo!%ZCKoYUxGM
z@>`bOJ3%@u@1KRhZOf-~plHytPzE^%RgM+(d8=;k`56j*RE|n$3Re9{v5N?m`xe-J
zN+nE2TaxNK+TeRe<@X0P<*Ochg7ci}OK-?ms4o5t>{?X~g^!z5-!`Mvs>&zNVwdU@
za#%l5opXfVUe&Urn<|js6+;211AJ*cSiJaq<bv_$my?s$hYzPbD_?#CZA|dv@0`GJ
z`SUy9L@9vJE&|Iz-p&>V9^!K;gm9SedlzkiyfsB*j_~?D06WSr)d4z)zjzasG5jHV
z%1`jl5`dlL_ZcY7<rIHU0-Iv_)Xz~H$1kCumx$+6cEH{Qe#~-UC-PIfK~D3$H&~MR
z`%^J$$@~}RA(z5WC6`eu|0ylC)A+HJe3j0RGKYm{_@x=(%;c*n6qdy|_dp<<UrABt
z9R5bI0W_C?NWUSL$NSOZJfHvkBvcgeF0?<Pkbgo;$+NuK0SFfHdJ5zh^WR;BrV@Vf
zGgO}AYu<s}c|I!v3Tt?-5?yNKc^^Qx@Fyuttdl=A78c&;J1I}<89$SD6%O&XKS{pD
z?abG9gLRnya3SPh@%@w^{hIGi0;_}2Q3z~rAs!!ZWQ{mp2DYy-)d})`!a3T<>o0sk
zsp0`bz6gOsLJ1jqSQvG5VHG?YU0o256zX(<juQ4nqZBP<m_i^%ShF6LCxrjK0nC$v
zbr-}>2_Nt%#R_>+K*tNZGJqur#rY6O6x7=>BBzBvI&meEgfdG1NfvfK0%nSE@=uUd
zVG;#nas|_I7_>a$Ujw~q3x&$fz&<PdLZm`4p_2zHg?snGS}puN1A>=?jg*GaC`69~
zXp^w46P(wDC3z6PA>5^h@U}2*7L4f>zN2YdmvD%}Mt6h|26Ekko)#lLf&;lU?g|yx
zLGB4i-vYfa4A6J^fgnE)!H2>HI#chF@ZB!RKNiLpp!7sAp;YmwLW(<Jo(b{fZ|)N|
zx}maPSiJ$GJs>o1N9nn+%Nb-)SokS=_(J&Q6S|VZYFh8S6pVsl;jmEq82Vlb{vGt|
z<FAF4GzE50zvl`;M?~4d<D~AP9aGNgNV-W~)Z6;d=A&+<mA<cf(<cz{Q*Ukqr@vYf
z4zz=6J*J|_La4LA$Q)Kb9s@%I)jqT=jZ)WUp)b+uEyNO|_J0H9gnI3>H!ztxskZL~
z=qYtKO}Jv!W#kEpQ~xjs!FctGUZ5qYEf1kBQ5}&0a#}rA4zwio;^!E=WOZ&3N-65w
z^ma~F7e#?3UETgSFf-J1@1t}^J$)Zand&*zmZiS;pW9hIlH?3IYDfC+<*JX3fu=n5
zu5R=<Up<n7sRinxVpvhA-biU8XVuMgMT^u;zrey`^*G9AEm5b@UY5)1N?MKAs4pEs
z+ZFZxD#+ET=T1T8RrQ*8!P2Palpqh()m0d-hw2?mK!yzJPeV}qQr$lS>W9_Iv?b=1
zI+IQpeyv`45b_S<r3KLIC|a+F`A*{LXVB{`ZVQBfi@1gMxwwiWX+rBJzP}!A?&9Pv
z7+??a@ob=YidDrBKOp*Lq2w)=(ct-rb+bWyMZ+sc2>OXzmIB*f+`A6y1H>bi7_Wn3
zngpdo;<}GO4vT$3=u@B=M<a7YoO%YOqvF9(fCh;tXkiyDPQly{q4UgiV26rdQcgpx
z_&g7laiZj3RK|<H*`t&o+EqeBqG)ZPlQ2$;_U}VJS+tO#HbvChz@}93D_V4>iAu_m
zOBYiqoisztqFGzS#CHy&hiMae7Z{U1@fQY_9`9`o0BM@EmCmngn>3>vBQretD)}2;
zO<s2ql?SK1_!}f>iU+-zf~U-%W&n2Rl!6C9%a|fe0_*uH;Zwj<I%O-R_*G5uq$mB(
zlysV8$9^QouM7S+vHEorMYy-gC@J{2v3nu7J$M@WvSY{=M(o~k3&MMRa{<5i_va9G
zU>=Znz>#sHpT}@w%qV020AuJL2^cR%G=~-+hJ6j7Kt`nWpd-wL{pj*BW_krAjx+0c
z$VV^>DW52onNDuKIOcQ8YKmu)Xwy^z^T$kprZbu4)E(wJ-5U9fUnEKe%(KlPh0F=s
zr*M|3CJ$UWBQa3mxq@*shtZXc`Ew|&Vs^0ry~=!o*((moC?V%$6O#}O71x+ahf&$a
zm{EA9ohhX7Ob3(k0yf=d2EK-coy?<nV0JNk7s2d1%wsD+cQet`ps<HIaS3ftn9Eau
z`IPyzleT9)W9rBi*2~<egM1(J&q!z*W)@OR;1%=70u0b==KNDgIIv#y0d{0tno#M)
zN-V(Q%>L^Q;==Y3iYqIj<&+z%@_|Bkwx<TBd9bk*0P<vuBf)Zj?aT-9V#5ve{_|#&
zDBS47dTGGw%a*Q&-G1!EvmpNLm~F5yfHkMegY0iKIXJ|YOaj_rR=X4efo$qhupD9U
zkl*wuJKhs*LF|a_P!Y_!(%$M2_95j8hO#TKz@{*E>vD`?IQu6YOa|#Ow%{iSo@8;A
z@fu`L8iO^N^-sVcq_9u#Ln4(8m;{o>ded&jTz0{`us4srY5`;N+28yjP{6+72EB#s
z$K_}%W8ZbfIA35#RYUF~n?W9}a(0F*#4Fh7EikQ;9eV@<hAK9#2kLLIa!OrjW<4nY
zg_%$Y1Y6h)a=o{)nRIx>ZFbvwNOZD8wC?I+<32(!?yydd7=&*2t50Bk59<{KfxGN3
zHQMg6lZ*iEz_GM5!JWHATef_;sjE>L$hm)u$}j^rZvhlWb4r?eCU7#!z)j?03PDbD
zpV2*=#O2bmF`4tAAYckt&*Rq1=Z^J5ZvmJ1CMpZL!C5fvEN3Z0Wf2!X66%Y&m9tSg
z$9+xTg7cgU`5{WVe!5y^+;6nZzQ7q=oq>Ikvv>*ldakA&R@~sO%m-*Y7ZiuK9<I_E
zm5;gDDo6})6U>19iaWIj0&bE|8!_DOk{vQsdPr6uK*>{5riFzEB;Caj_mX@~jxBFV
z-1jI2Nq)8kbg*PTy*EN6tp+-UAyhJfwmpPN(kUzyE?M+DDvwD%421a+63Ls;8!6c%
z06R*uj}o1uC37ipKSmPhfVLA7+j&rNQt~b36{JZ7TiBZ;`QRUrBFO@G$X$?(YsFAr
zl0?xh+aS45w{x>(?%R|;(jf`>0P^=Ff6WKaeaX(z7@-Fe*+d9Fl(cUK%p=Lp{pjIi
z$w6!AeIhZY%+RNj?{`7`m1N)>Sn*ooPAB&{NLA?|j?zAI7duH^P6OIm+DpNE7irQ7
zXmFMO)(Z{pQnwTI{CP+}=mo2%^aky^I3PVtxny2aD|(xHOV`qb$4BZ(ZWv$bHp=@t
zD%~6hmLTcf29$!O-PfTaL|QNb_J&G}6KN==rNJQK(z`T2JT6@;fHML=*aVbFX?X<=
zrL?u3!q?H#-6gOlMtY5Q3!jjNQCu}i`tAr+CQGN%geOHR*@L!Jsp&YNrAgDs<DV|w
zM^5Vu>Fr18(;2B3rDSJGfA}23l`S=+C1Z|sN-6Z_O0_h}&6DzU3*<}n6vr))j{gCb
zhC*q$4`41xRr8_gqI5+*B+8}pDBr9?+IAMKmC|SAz^{^iOOuOgX<HXqE=fxd;2K_*
z#xH|-t<>Qr(5^^Vd;%49(v_6&RWD7U5N3n)GW`_xRq4+y5O0(Yx&pdM>KuwexMq;z
z@B=)}(yWCbccg|zK<kzktAO1jb*V&W?n*c0qV1ma&<J2Zkj^Cehtjvw!1+iTk_(o{
z(zF&-K9O>!AWx<9)1ddY^lTAI4zj(c0p=(xAfKv}Y-t*-aF%sspv^^Q*fSsUuCf`e
z=)JqFWFA;OWPX<5@s#!dg3<xmo(B;0l6~+$fO^Y5c1Ouac9s^kA+p~;157A<EGUJ^
zj4-2=hRZI{V|YwvM7QN}nUf2^B4pMS%8Zn?m7*`vGHo}YV`No^k5D`zd+#jdPs$wr
zK%Y*@_AEzZtjuiy;~XcO-UPvTnUtbTC9?MYxUlDB<0xuVB{Qpo^)0geQ7E;_Drr~P
zu<SG?$;TRvI}fn)M$V%FR%#UHkIH7F?<oVX)kt>%0(XsG&7$Y;iBV!P1fLs?zX-HJ
zqbvE~@iZ=}gTw*j`4r4PY<zSG79KagM2ogm;|?8I@{Q*`hB4=jr&0c5v+*-Hs&S^n
zgkoU2%O6n;=de76CJ0gT<&$7Vid-lH<{A04X<#Xrf3t*6tE-S-+XEgih2eeF`YO`$
zQ1Vmk9*dH{Vkd>Z4l2g|2!jtP9=%3epklKZ(2gj=CD0q9coYH7P{r3Pz!Ii7It5l7
zQ=G9v<#9!$H55iG-lI2ZjAHFv$emF1Qmi;u;buwc%Lxjvf6$nuh_b|`OjUeQ1(L1^
z{0>8sq4?elZJCM;Iublfv0yUPXDjT<g`J}~L63N);?~C?)r!X3Fs4Q^>r1rNDYmpi
zMT6qlKd`A$QAJxluPJ`t2(V_w3c5+#6gJlAnZe0qG6j@eOg8jF!p&qJdD%ToyeQY#
z*W{Zd$ordw+ygmm@&(0wkC-fc2c=*Wc_tKwnH<v6cN_oImHY5_WhO<2R>^k4;MEoM
zVq3$m#Q(poCC}2@o+*%BcX|!}zkWvr1#`Zur4)z_cJ*lZetQDcZk+Np{%)$<0=qU(
z--N$EyuSvv{@8E@J>BvzEnT<zQV`J2I}2UeeTr7wdw#A0!e0GV{NH}UI$-XvqRG}j
z$}jQ%f0t5Z-EiXo{_n`VN!~FhMv_m#WM`&+86<s}d6X95%jDDR-;d!YqvX$o#ef7e
z*d~ih&2%3}TPPFx6MCA=u$0c0#e7Kq_Or}3+OK(m$*1@BWyTEo{r@*C560p@$5}0<
zt3|NCR{<}Q%_l#66kBa*g={qYdKi|*vI_$MAIBOdp)!ee=h3-j_9mqiq_7hxH}VYo
z&uo-3*$gL;EOuELNH)8VvOWvgq;eQp$o@|IPS3Il<U~8q-uxZvOW7@yI90~(eFDx(
zwyF{us@Q=~4Unj1KcM^L3Oix|rq{6-=nkxB%a?=a8YYP-U1yhFN9hK;kTT+Ku~R7B
zrH%cOW*zP9-{T?P!EXC+7R(MbL2nORuolpFSx3s0e8h6~sO)9;r$eBRJ>3WKe)gYz
zbePHzduTcII&hx!W_u=AXJH)s6d%0t|GRKsF*E2L`<fX?qvOCnqL_yx>vIY{abmw&
z0a<5u`D18vVaK<FxU!Qcq0NmQo(*m8>}y)RdaxC=%=Tn=|M!(;?^5K&i#0e}!xV2e
zjuK&f*fRP+`m(nX8Nd|y<U;TSv;3zJ3}OGI?FFH%;S!8F#V&svR>ZOGBTZ0?f9kJj
z9lR<q9B`}c=;2-CqJ}Zw{x}-8tUWjf80(f^#^3eJ`+@LX({%iQgTa!5;otjF%IU^a
ziO{zx<|iO;PNl%q53_p!`eQo9>$gl&LExut<Z9Xa75Tn@nOp#=9ZSA~vYm2z-R<$A
zPvc${MHF3_X+J>NmFc2vXE$c-Mu_+^vJKGZ&vZ+`62R0N)&cY&BdkF&l(BvfqY%c-
zHUSA|Zd1JOIP*y`N>Pl0)SO^$iXgGf`M01hff@9JcoOq{88lsHlF5b|rjJrBY8jKK
z&~$~lW`wpn#{U3HO-#%e5WmS-FTgOhGoSyLgL#)(I0B8>STh8{7tE}?;2CCKP)65l
z#$*NL9ofG>g!#wW8-=LMWIL+=-?0BeFW4Mr*>uR{GMYfxn#Z_}z?kPVH9E8vFv*lU
zSjcRD2bE`;rKtcaVjfeTS~+8IRY7$H^XdxZE1C6lb5t=mD4<o%lv3p-CWu10mzl92
z|JS=9atd@XGsru2n|V%&KAnsOg-stak>s#@#Ke6Ef#-|~z3m5?jkLYQiM^KxE1X$o
z16W+x-EI)@VH*txKz-Sd{()XUcAXJegV@X0pgx#w@xtJSuuJIJifH!fdFYK{|D>hJ
z33f5fY)-Q7^c*I$N_st}us>2*EQh^20dl!);T34gW8YLlJfE$m#X~83pdXcG>?~Rp
zUSJn^(f9Wv+eHd%S^HhUzQX42fP5XBLa)4f)|wVJH(Av!w6(As`q0+OI@6tci`~s(
zfZA9W+8S|}#WaT&JvCpT?LNDo+(Qr82Wvqdvb$;N^@xr81LBWaFA8!!VT1mm=l?1D
zf<mLu*mr3~)62HdYN?Oal1rqY6>?$P0PA1|^PjUeY3T1DYrYVbFIWpb(1zGwC|~p?
zTe1lP!|YF2f#S_+6c7mE{&xnPkz7(N`Vz}2*1?!mZu4=FQf?SIs0N&zH{u^y^MJem
z4{9AHcQb(&E{UOwmn`{n35+R{ER;e1vg8tN+-Z@d{6Y3g<|d<ZNMid^0mb-NBkiZ<
z@pWm#N@A0KOw;pQ(hC&k?~uNc0iiDG{|W(r7tt%|d?;OPpd_WI(hk}kH6Z=S8JFXQ
zl%I&wYw3aaf#xEcH~o$O!xy|Mqhig>*T7rL8l#)*KN<s=4NvKw+BiEGt-qX0M2CO9
zyaIoBnbI=B&Y$v)ch~8Gxu=x^m=4Sc$}@3fd@s}XWl!c!3TGW)ngalEkSTNk{vl?B
zB{~txjO;@xjQR0<w8bzF$@y}Ec}}0;(~KMWiIbRs9S~1uJ|Q1U7PG|^ZP|=3eJOL8
zH55(FWe!WAH;<|LAI!>Unhv8>z}Q}+^z}j}+Y>xz8CDO$A|}2KohfD#X;x6eoIee{
z=a@cs=snNO+Yc3`j5noFmN9cEWO;#UcLe7}CO90R<&1nj2;wG`XIRNRCAV)Cla>R$
z)y(x!fL&s~AxGY2#_cBL3^mNAR@BxqL8DQ;!X(~<G1nO#<qh6o`YD5_nF*T@g*Tb|
zg>+q+dv5`)l^I(NmOIS04JdUp&9qqUVZNh{HFp`Fyo2|c-tB<C&-^$WC=VEH*r1oh
z7qpsBVXr3vEYrYt>_jiJ*+rDHkjwr~?sYt^<nJwFSBIhU9Q%UOP0Cn%%1$U}!$;tO
zu43OL2gzl2+El>Qu@+k(aGjO;fTe?7lnB!tI2OtK|Mzj4O??ext$abk+11q$J;we6
zAOqg1Rd>K0!S34*D<j$I1?W!{J4l=0quE>;N-^x;i=pKNTY|40-a3|xq2(0&+6Qv6
zthX9Q#<5{~2*k5<DN!eZeP=N$6WMe3!FigkK=vmlH1GAHl+6D5F%+e+H;<xZNM%FA
z(3r+PrOThizC&-MB6in9z!bB`)&aDfZ9fRRE7(71^L-^d(HQboZ2cw(G_V#)sJzOi
zEypl6vO`Z$YGS)6P<)I1aw$66#wuvJ-Oif)2Ivm<;W3cgY(f?UIt{F!3mUuFCj@hc
z-Pi=9x>+}8sOVwc==$AdSIq(IJ@%;<X!lufdPzTEgQkG<A)EIMZI4)88^{2Anx?nU
z*@W}3caS|!H_;0=guE$3?0zNeeaUvQP&CY@?FHv6)^M!=jc(k69|7vlHPK7ck2@?!
zr9U^;9uh%Z_8gRgIX@0)k=(x{!4k!dOn^W<*P8^J61YB^H>Y!-QRF3q`_vem`J8Dy
z#0$7=atoGnPR-~`8RxkSZ5O!CN^sV24-ItcOf6UC51uRBB{SGo$Nfle(t57m18oi5
z>SbuV$|0u#1Iz`sLsJviN!RBZw;%;9*ST(A7;}UBntX-L+@9&UL2q(hjVQHnM`^m&
z$|dwb{1$h$4q$Cul@(08&9$GS_)jNSMvKZWPW1|7a)<kdmc4hm=QKgO$JviZ+kI}}
z7C0YpwndPC$i+z^|Aafa1Er^2>QBIa#%-&H+%Ok^0&NbGH+Tp*N<N_-Gft8jTfyQi
z8F3hGE|P?W;B=K-PoeLRhvdRinC~h1<qr&vw`AIzu);^u^#tmDCFkf4^pj-LljAQ5
zje#+7l9%L~O_%hx(>O~$rc{CRl6mLAQYE?3gvxu8(;0MqrKg9W-b3~)jf}U<XB;Yh
zWp8$Z<%n!Y#~XP5LS!@U05nvlbc3caS!*Cn441ug3FMgUElL`UkonGl!BH|34`_;!
zDJggGq-@}QGDf!aGAiR`n?D3-g6w;8ktWLGUc#8uvbl8FO|s0J79A-v&wC)LGRBR8
zCj1kQ|4HM&Mn_AwZ^w^@s<kIS#Q)b#41}TU8!49h-S7(VY<RW?e}8)aH4wJ;(yQm^
zC42GzUy><L?ys2N!N2o+%C*?_xD~B-CUN+?d(mB}*;D9>zx#tIsOiG|`6-P(BhZ$A
zAI4DYi%$45KYj~Ue$3jZApVT!D_9@EG|ooPf|<YRI~u|?(GwoZtfx0p7!zp(UE$16
z4*;FQRMr4Hi+Mj2U<FJm&7jXQqf$Z2nK9$Qa+#U%C%_t*-)}<h1{2|rQadwfps?aS
z=BYW1>SuP1f>92vdKwf4u$>fLjAU~{{$DQ1G)hMDXMQUIZUFPqD#!#gQYlCX!_uzU
zP^Mu4NEoyBW9W=wjQ;}X3FZ)eeoiy5FQEfT%(peLAep&LpX(F@bDP2w*^K>HDCRI@
zV=w@@%z8?sKF6G<WP$UHi~(pBlSf~SYNl%ethmaIBu85#!*2vyE8|^=(k-St9xB?H
zXSwJ=I}=GEfCTpLWUwT%MRX$7X|~N1&`InTBeW&6hTmvmlEQwy8?~wI*R&xmjm<fQ
zK2@?!rO?~T#;k(E<6H%WS0lJcKeR=1*Ka^Y6gNTzz0sWcSHO<p0=J^=1h;h-<W6!9
zbSIzUwmX3(mMftliR0cm31i|p6@^^=B)JC4MDUlC(3%mMIP{%8DCwnrhleDJ(~v(b
z2^oS-fszI%U>}i$V$vWzDluA!${<OV0s_GjYf6m|kre*|y`d804}t9}GxDb1%Rbx*
zy-Bjf)hMOQDrttEDO>&>G-S)l<#hk&%VwMbPob>#dz6Y~+i4S3i7b`22lUJSzuvAp
zAgW{QGjq%Cvb#u(?Wu_-i27ndP(hz1Dq<mmy~PTMl@<ZJE(!=Lc3`5Q0v1%TBdel_
z1r!Tdu_0Cvdqs?*zTY9dKfmw$<9i9ZcXrO4HnVqU&YW}RZf*%sqck-rt2<Rw+ycN;
zni|EZozZ+b3N5Z`{BSCv@(cBtH?ECgdCogsg_f^*5v}HB{GaFXsr<nc$;}iYJ%3Gh
z0RGp|4yA`VIiI?SA^GJ>BM9#^>|5Ztji>xa_YTnz(l_xgc=S`rUD)5U0k{t^Yy<I#
zqDU|ux!4ZZQF|%IH~L`%ydSgR4z6P_&?zyG<8-2T@)=jWpVEwC`+-OOp?^?lA#mns
zVS}2KxosvxKsfth6xtUue_Ea*SPB_)k!(0^w-&KY6wFCwr;ETSjm@F}(;+sQLSR`e
zjSlSPuwM%RJjaf7M{$Xz(D+<u2YNx@A~sV8F2(Gi6>85IcSlFdSf{(7`)pz@oPZk2
z2Y7*S5r2u)u0IE-d^;3znd^j+=&_ylm%%NyXewuKD0%k-+v)^1pV;zlU|PYJmxBB&
zTTqID2;mF+0T{|pw*qDu?`%oq&W~<^ph!M}o-4eXpSTLf(cH9d2q<=Nc@e5dcyVc!
zt)0)y4+C<Yhfs#|4L<(`INszgbfE7Rw@e06A@4=;z7k&H3Cu@4sV8brc;P+h^^{Ml
z%w^yqw0VBXJ-b1LKlnvDQ~i-ICm-x$$>c=-_hr(I<KVqYdb$XmjFuXiAtFZ7I9E;5
zHUDr!Gh*KK42^f}M>2ZLSj;BKe9w|DW01;OH}cVZU>7N-8p^}xS9bet7Gy^8J#JvT
zl(!)(H-?wK1@~Cql6FplM;DQoVFQn)fN26h;)hxy52Jxf;=RbJyPaR6Gdd|enjY<v
z%9~yTFpZC~0m^<ph%DhFT%m1GCLde_a&vg&3UE2av$7!~pWCS*zreFyKzEb7(ZYL+
z52OR*g?!dVihtbZAp@ae5#Mwfjd!?P5*qLFH_I@N_xKEYQp<hb<9iej_(lryz2SnQ
zdvE#TQWWp_Su#S(_|&JMd(Xe4Sl<U;vK*KndC~!B_=%UP0ESA(IzqKDsiZq<3DO&c
zg5iIaWJ*svDpe;p!8PeTokF@J9jXRpo=cy0qE;rQ4?x>z$xsKF;qnPO#V+LOV<93%
zPVJ9cro2Fcq<ne!N2vWk-uWEERWAS94XQ0s%rt4mC_N}N9;akn0A><?FAfq+Ta{N^
zfD^BdA+O1LbtSo-H>gQ;R3br*pa-CAQ_U0*OHnf@za~{(K+cn$s!WObd(<===#;K@
z_kb2=HJd`_2i28v&>};v+X)1R)lcNS&Qw!tfFMhCp_t||^)B7YCrqmQNN_u;#x?<A
zwwh1T%v?2(Qm)Udev=?RPu({X%H*qUwn5>`>b=sc*{)|}G6H+0(bl~8l(wLEy+jFc
zzdV@+34P|qLkG9b^aXZ*lntD|ry7H6zlrn%9sL<SC}O}klMR{&F75yw28DQ|dGME?
zAZ*C}i+~JWL1FG;-If7$c-~jA_|^RlMrp+C8DKqf+EcWSe%%r}j_Lms_>8Ul3J{NX
zb@1L(a~POj&vL+L+~YUk;N6UTM&qLc0GW`r5$`8H88{dXlUDQw>g2eNct53e5t@At
z(Y@qra}{vE$a{eJ$9h9dK+sq8^0&2m^m6JeBOrlaTyULkI}z~Nw>_ZZeD-0Uc=ejq
zGOgz5PovPxsxNYb&)#7A<0=X4Z0EkkwPn5|G<Ar`1`EeDvNoJ;XkF{E(+J98$|vYJ
zat(QGN6kEr_uixF)Zh5)v_}b;OuOda?5E@XjNO~SVP@M7xXybO2PMLpd58(+a`sP3
za9F`Y`=hpoISvQ=jm&}ex+yH`HfsA=wR6zx5X+|Y+zi%(=K8~IVlLD<!d`TQlv8X7
z+0A(@d=W4USi~Z<U1RNs0rMd%`xX)s`28NxWGg?WL6OGGT<M(1er}@$PC5@c3<@)^
z7K>hF@jUtoiz0rwE{69GpH7*AYou+I1G!e>>p>qU$&qN=B$a=M+Ggn-Wj$_@E*I)7
z)D)=zoltj6t|=hMlM2rRC10BE4uT8PnZ>AGkv7$*)Pk$h2wFS~r1dv}`b=v78j@DY
z{f|P6RCzf?1a`@3uR*a-enLC;G}%ZGoKBa$;YF!jh8oOPfn{@fdzHWOl6;Y#J##~z
zat-qC$*uRG`Gwq;exl>0T+0EYHD5_N0A7(MMblie;7b(WNq!bQO7ZoW0qHRR(fJs~
zONC}g7We=;aZ2xH5W8Nn%z-Ys$_CmzUr^kP7})E|rF5X&R$9}7bq`Nh26?e^XCDY2
zD~{vA<+(BohKu@2$rDg*l^R1kruC{RmW=gH>ht@kCacv~q1d4wScF?>pStWV6h5q;
z{Rt??)qFdM$W~X;>5J29+umSvSFKHJLx~!E6ToNcP0Emcsoo;L?<aN0Hi-YCt}6$Z
zFwH@lG*)Q7{{jtTHS@+m`!$+y(+tqZYwD5XakHjRdobOq`S}Idq-d@i(Y8mUpMWAw
zQ%JT$uI3r7mFF}U$PbsVnM-@%>zbMZyl-g+(e|%MbGkDy@yL9N<UZ8&t_3X~X}+BX
zE#7KEOTg^C#`iZ6RA@Z)CJ0=h?b#nV;o5gAz%)|3mU1VSXrDg^#WHPwTWA`stwlz|
zL2c*`6xrHzvhc2H7gGlNP3;wmpFhxEBjf0?Hj2!}m)d-?ncrx?R9bghPM)6+TBKcI
zNVMNDs6Ah|_6XhoVLGV~8Y6UOI*GYj*EA1=+jQSm&f_{gMYS_@9r8hVOn2@Z)K2Qo
z(pmEJx~NCc_kwQMSkx}-B7AT|73y|mf=jV3e>aqQs_XBJw%0n(LP&V0vuh24a^2QM
zF#D)$Z>IbIvrg`S#t_TJ<j)SZ{Pj3QEVO)=g<cfu`_6=>_w|l6vc-D8bhMS~1!WXH
z)gR4=q!;?>^whG~`h~s_A8MF>6$8B3F#jP$2*VKC%f=ZpY1!If_+kr`jRrGK5UGX-
z3(;oUZP>jYnx+{#lV|CGLG}SO!_bgYYmOUA)6jO>5d0E^7YuuEpmxLXnI3y|$B<5W
zlJ^Z(j{qz-IQ4*rrH11_fOn*EBU$%R#y%C$aD{PCb?6jr?6McV|J|5Qwo1IQMH;y5
zF&VE<Lp9CVAsZBC<F0<_%n73vx$PbsKa&T$%-C@a+CCXGXp0nXb*mRNjI^>CiDIRd
zCv2U{Nx<{cNhmVOKN+|IKM%tD84oD2a^5;))l#U5BF8|z{x-m9l1axjnkAVgL+zGL
z$dG=(AD2V<67D(#y?w?L$QJ{va4g#1@F+S9RK`P{QGDR7DX(#*G`TOR<D^Cpt5y%U
zIyCo>utk=X;#pRJj(Ig32QFWvHFV~1zPts@Dz&}KCY-UbP)khg9z2e4Mvi&`jvrVK
z9c8OvSA8HRlqXZLa}jSqc?+@Jk7nc~UgP)w1TEK*#ZfD{CuII(28HEq$GhU%Y$5}`
zOIr#s^{!nHSJxNK{$sIUU5P%{x>SH`?T<YeO&`$X&!aF^M^dUzh`^w(j>v_2m$!A0
zEdICiB9$ym?v&uWilySNR-@VI&d^~WyF>yqu)v`sS?qV3b#hto#Hvr^n-tR(G}KHy
zT?OE2LBO!d%)tQKPAx%anv8M*ho3rL2fOB5$S`i%k4~Dl+GUGYhZ&yeUYn&MXmxZQ
zf#GP^Iu-B^nNV5jbmD5&F3znRZF9$F(V6L$ER%fbYkB-T3T?;nbSqHD^KyC)<T~!y
z6OHS+zYBmH_>^v_CGfYD2b;<_)6RVdKR`3_PX5bQa68D)Plu>O{O}iaKZCoI&3~Ay
z3_2d+X%GSDVDtn?-z!Bl`ty^6i-_`4toyB?b7Hkr%wm-{MTWHf6ow;Ps#_V;l1jEi
z>LqFU4-jxo3d;h^`_j$<02WKnW`pxn=@JFNUr3%lC|*nPdgu@#J7<93V%g}6E-aPH
zAr(HdwR52Ra(Ohl9aqS+egn^yvV)0M!Bw(71#ni&C1jdK%X^mrHAdF015T{$O&K*p
z&ghCy=6CsQBE+weQ|QiLE3c%@Tb#UnB}Bx_LFBDnCx?6nm-TXZ652M%yAgR&667^?
zfRZSuRtHLwJoO;BY?P~yqjP$fm2q28Tv6O85#p+{fYRIwl=km|b4__$c{o$?ZH`ap
zhEnGQ+HNYya>Ih7Navt-p)w~Nz}w2#JV?5uG`xnfc%s~ngxar^Nqd3vS^487^bJuT
z(fqwY%@0G{JyqR=CzDi;y#3Xhc;ir16NA$_xd?(CV`<86Kadj3{&k%W&2>EP2;xpR
z$r;;u$S6R59!f*g?H39mJ3lJ~X7|h%Xm!_6#%cdD2Z$b#L(#O6iR6Ksa*XU3pQhw^
z4(MkC{NGFw(;zr-*%N?*2OS5~8P~{PI&*k37|m)=OZePI<hEMC;wS?mjJe$cESy#E
z2l@!skizbZS;Nuj`x4fVHV9Gd#h?DVB68R)XHg6UE7?-=Hm+vF&w$G&)?zD0X)`m~
ztw)!)utpIOoy^)PP<bnBCIh&g#Uucj!s^maER}6Ih1yOwstHhTupF|f@F1)sVDpG|
zAwO3sdmIelV-`Z4eZnfwem!LdS`eSHb+u8vWZM%l1h3eHT+qE|p{AGUW+dM+4@_6^
zm7Ad327ZdXCdquoI55rR9Vx}=0gszZlK5aUj!XG<N@{qC{8ylq@p}7!@`+~&)GB!5
zG?0f%g9?BWCM8`&ZHXkW1<FckI&C#JN|&ObOpbJSuXyp9)it#vi=$B5KLS0xEwv|;
z_mMO*0ps;q+VcS#ew8XHE-_y|MXtXEa@ufUhRNA604|fC7$9Pm>`(b2v2uMG1Z(6I
zF;Hfm91#XBHprI$fZXHqn|+|mkvmgd;f#FrB2e<=wWcO$yd)bBK*a+2@<-He%JrK<
zQjwgP1z@q<gXX*vIp96GJ(4ez6;&$F?*RJ8vdef7e3A7Z!TYPcz7u`g%1b(6A(Y`X
z<E~ZCjzAHw#M8zsL79~d@+4)@Y!GZw#t)}2;Wj1gHU>CFS(=A#?^4Rh8rh@7Q!IC%
za<2e|S=prr=4oXZg$Z(%hZG_@qkLV0wmik1h9qBcrJoADqO_vu>vg4=T#kjvJ%^%q
zm9Z3Zzo)#RoX`78lX+E>el=6&a%6o6mc;+K8vS4EkFtlIrQLNJdpH1^o7qEKXmE&C
z!`)N)6>o89xYj~#<&3DbYM(d-SBDbZ6Kd;SdJ|T;HmBpTZnfpeCQ%)|&f)4*9)W|A
z?YiRNxY~a3Xb}HPX9p9$!%Qn&JLcX3i%x^FwNpC}b1+z_KYJkdqjvcPi6d&)mbmNG
zZUIPDSDh2S!KuscM%*i^OR*hRq`BCqNEWamEjasRWwdZ+_=B2wF}tn-0X~zwJc1_q
z`vuw!9OTy8!8zE|yLWe&mL35CcFz8OLEe5rfp#ulK9d3hz3l>gf+tJ@rdZFoOG94|
zFaJQtHe>8t(m#h*4y{|Yw{LCl=-_A<<nQkjDC{|}-33?^C;53>{PnWxwfpO3)N21%
zcO+BdjsJ#@)D}l%uK&9PS=!inO!aNy=kMp;!rQ}hl3mcmU|&zWX-?iPe4C9Au$$;H
zbsX+0g*WeFH#pFHYM`B$$5bExK)de#UctVV_uzn`gL>Ho26%XRj|uYj@U?U9>fXW`
zWMka?#|8U%j~VDcK4`kfRPR`oclvKIX)5AWp7h_~^qp9t;qu=x)aLG5{`#>fo~y4R
zPM$M1HV=5iweQ7+G>t4K%+xm$yGo_n5j#sI^UhLvqPrM*PSuJrca-Mlc1}uzt)jrg
z(n`3$HmCwmbf{%saz`0;Dx!L_ikAj2EnYfv^<+y=y->F3>zIS~T2|B&Vy>~8=+aOp
z>-zZzHf-wPF!-P5&|FLZLE_jlV<&Ul@AWN5n3v4d&uT8}IVnGyzuTgJTes)`_j9)E
z?(G>o!9pB+tuzo_qI9;RT8^wWk36PN`cl2uK$kH?y7n3D(y(2t%D=(p&qoa>^UPnC
z8TWP)J)(8i!mV7@3*-0trozcmQ{SwfH-4R?ZEx?;!rrk}D`9lC8Y*1VtS!wxu2uzx
zhW1{b9*!R496egKa%yMq;L)m$gHt;%2d}nX_MQ%oj!qGtL#^<tX7(Iv{nIEGC6=aH
zPv<ASg}UF`ouBg-Lr}7Kv3b9BU;b>mcu&<D!X@3hFRL$Ns2C)QsfZG7&A>^WEf$(V
zdS$jKK*@rH?E!$V%n{QLpel=ORDoRcAfRa>V*Eiu4iV{8R)h%kP$kyjL%^CNHlyIr
zV#Irb&JivdsJ?3~Vlyf^7o*A=iMEGPM2m1L28pXE_{q7V@e$zE7r{pW4HMZ^bQCo+
z(O9uSjL(F$!f=s}l64o#QGl;RiXlfU`EI6a;WF`_s@;W47HES+3<`d3l_<#qbfjo|
z4Apn5#lmA?^)OZxpkzM6_BfE|h~PhqY%0*%6NI~7j6VUK`eHw-fGQ^eJ-k5-ISHsN
zHlqq@WmJq5F4-tHi5L{TFhP`LL&~!R;h0k?JUj>BibPRB)f&R~6mi-prkx^Pl0^=c
z?~+BW(`arkyibEyAF=<mbu%_!+&gV;qrB5|i={%BYi$Ea3mm#vvU^)uv=Lp?tiKgL
bxz^UaqPLirYuy-K+Dy&zHfxK`mCgSKkDw^c

delta 131928
zcmXtg2Ur!y_x9b}w%y*<*n5pN_7ZDMEQuOpO=4`ZCK^jjj8{}FC@4)pQHt0Q3!>6h
z5Jdq6X`)C`L7FHC3W&=09)ADN$7g5f%z58)X7=vx%$c(sa35FXKJHLEsXREe11qzO
z17(u-d>^?)_LPzQ|9>(@S-nM+Fy9=JNSN-{4v;g?JY*84r|oN;%NVX;4liM(p*Re-
z%_5Oh;pPH`UDXf`ZLz#r#D4dhlQ0RpSqU@M_792Vin5_l=za&H=`EZk5<6t<lCPx_
zX4rg%gjsI$CpAvdt_DcY0Ekw!2x}Ixl`4onK9x(D-L0EF%I<^ay=}-NW=D}y!uYo#
zSC|$RI0UvO9~kXr=wE9?#+k%=LBd3|g;fc2=r~N?ZR2mJitGWHliHFUru{;YX1DOC
z^Q|)h&TrW)&ua(4%NC<BNSs`;V(kVA6D6u7Oliv>AVMcxMp0i|$Rtvep*x{tmWvXp
z%{Yk8f1Rq3NZT2|p>uYTAdz-5&8PE4o#rtTX)ohis!VLed0&$Qog3>V66p}52c6Gy
zPm*`ENA6cjq*G1(VU3BK!bzkv%oFH5<&;t)Guxs_vz4PLky%>YX+8&otW}G2I-jx_
zI$yNRr}MdUA#dNJoX+?CEl6Y?TE3_A-&ZjbS=Sa);{2tRR3huvQbXsK&yWvjW2c@o
zBl@!v*}%5cWv1dW&PTRwmiO<YlE_B2YnCq^3&5oR$y2L%iR_#I$xZuY64?)J{mEGW
z9AIa(YaZEva+yT_(AqqVoP2yeBjHuwvl8L24ND}Pg%K~vFcb>+3Ps82_AXM17>2qs
z3J1mfgRG>pk{rlKRet0DA0&!(8mXikN5~oyl8Qvp)m_iFV3OT?vM<K$@<Gq#A`7`h
zE>o%$%6blN8`TQy+%knk)<&bStlx-}*4kzrnY&b{FqQ1WIJVL&EDznMaV<N!cSbKd
znE$81%M`+_zUZQgQ79GT&~MJ7ut?kwaQ&Hh_Zysz8S9?IwN<&i5Ml8&(^}E?sk@9{
z%XD;K&ktte+=KbPOdI!HzNKkw8_;y&{>Pgn@1tnjnC{LC9lprfh3g{pRd6{+al;Dz
z{?C1}ze4KkK1pcJEOB2dv}ew`?-BYlo86;?cJ}IICCu4|E82LEh2j5k#xf)1|2vh-
zB?=6U<Y^Zrj{AM7x?5mzT=1U3@kSv@TCbAgm^VShF`Xf~sU_(=Z?C{{Nj)8}-WG72
z>OwqCg&dB_8kNMZkYuY>s7#0;@b);O3q3%`WkX4R5I3koGW#C_JbNp{@nt<}{*q2~
zAydh@H(kg;tC`d~Xedeg80fsqLvris0n%UboERoG5$a7WNiKZ}9lK<GA0Cxsb^<&v
zC8ex!L}Bkt;JAyV+V2uM;Ul9y@olLG1I>gQs-(U?a3k~5MA8hvJ*SW)D9Ft6BgD|#
zN}AnkNT=vqk_=f!=kgM=XfOJk0I6ycg%73XeK*P2PgCf4VJj&ux=8YizmegGJIKY;
zAIZf{7s;WH5p?WPOA=)Wp*Bt<R75mM24s<2gAWq+bvd1v9V3T2G<R~n{S<-SnumSM
z0HRhj4_BWpL^1jV9fS1*D||(cwyh=oS09@t1IbuhIl11^Os&43$Yj_^LS@|{wqsYQ
zbwhiS$BZOYZ4-4SY9TqXc^a<2LelpGiB`Lk(t&6)aOg2n_v%aX{7@q5Vxb|OET!|t
zhh!jQB~iTXMaO=Qbleb2I`$00s@24^(T_~-3Z&NXg@l!VOUFYcq<QKsu0O8gGNK#y
zBe|lUL;X-{srha+$){D3TS9vx>UxHVCgI(nkeo|u?vsR!`Taqyyf+<JD@Y=Zp>wOP
zdCc-jKjUk<1T#!@OuRsnZf%=?|I#z0)L|$2^=<R8f8$P)PrlTHwgKeCY6aa3(=rJB
z_aSm(g@h#ioXJsnUplU7zH1Em)EY9F7+T*V7Z=44!{=1$-t({NeBf;2**y*x?UI|#
z!<!gF<`=lqv2#mmZgZK=FE)ERu`SWPn@MKIKWX;8CH1d^f^^299}3Ayp5%{x$o!Vh
zWai5vGFg#BsGCv5aKuEdl}E^}v`jkM$Ci+>yUh=Wjoqln&Rt0LKc3DHA0{QQ1Uk32
zBLgKbiB9QBsO>Asd_ys{CO@EIk6uhBpE7j*s`>IcO(Y%18N@Rwh0gCBrDLbT<l<s`
zC>3`qiB1e6>Y^B;C~m$ZzG_cBYizy=uXG~K&d#K{E|WC-I+EtH0Fso<CDN#YB)R<q
zwbmXXCq{VEIOUp1o-mBqG{a~NrZ+!WU6$Ahc54Cwwl&|Qnm1(T;6PH9HUsLK4Lc7e
zBIN@*{-+?5h9%VRc~ePJUPP$8N*cL`p=7M)7h+yrL7G)+>V3~2NHfZX&I{^DzPG1H
zzyD>;57dMa)I1sQbUdq_XsGLMk%5mDbp8w8Tnfp1%oY@qi3Q|t|AlnES5ESr6f*hg
z7drl!NjzWeA(U=9nfZ4R>CgL(B!}D6asEa^JwGC&=l}iZ1W0T{4fTm+o=>HrQ!XR(
z@jYp{yl&7j?HiK(=RrOD?f{wJl|qs&`6TJw{HQTBk;!7bA@TdKpw?MqsC8Km@z4B~
zjzQ~4Cxe`@OLQq@GQTYuh)X2ZLB&M9dLSvC$|d=;ujqWt0&>)@q~6@?Mi)pOPS|KI
z9T&AH9q(EigEOh5DO@E@Wed_gQcPVsJexGTIFehv!bsm9xtNsxvyqaMKPm0(Ld{`6
zQ4flmDay-9CtXRdeEfoR8U%9mOP-7=OX+xSD$#}RrT#fplFo`>NvDs6Ozuu2hvt1t
zI+Lc*vBy?wb+S*QzUC|?Sok4oxbzKyH9kaob`wd~?xkaV6A`UWp!4H@5vpb*X>Q6Q
z>}&^e@w1woPIDk*|9R5+H#bQ?)R$cUb~c&xy+-H3dx@>xCCsnUr@2J5Wgm$Y%{R>P
zM|A$-A%Rtw2o|=QNF8sGvGx<`m~A8-mryzm!|V`!Eho)kvxrUBK;{)4NmIR*czQJ7
zgr_kxQb;_TX9?Z^Zhrn}Vor;<I3|l2BA%KzH$Ncr>IwYp5t06!OBDKS8Wl$gx$^Qp
zwHDkW?5#+W+huhAj-~Sf!>N}SRuHG_c^aE-J4yfN#iVn8Dd~*4g7ppV+F+_k%w!;E
zJgIv8OTIf+kSohp672auBzHbcbjwB&b@b0Pa^LxrWW-fs`2HVq%k^85$6u%8ywM~t
zK20VQ{D`gdcH&vWlIF&fuws{Ne?ko-mXb*iUvlE@j%M(2lHb@(6d$h=VEjNjzaqu-
zTEZ+Q$(SK@ey*n+$LwGZ$I5I5M@2rlHSC-W=cBQzQc5<BVR0Ngmt3iQNFzG-KIz*>
z%^}jZm~G;hd5H{n{3u0(*qS`uUr$aXeo3lJyAe#${J8DgfzCgVBGjLwX*?c(LDY4_
z$jp2P>dX(LsWY!S(6OtO<n3&PTCSk;+~st9V*iVLy#FJ4?ePbB>b^{g<I+4b|C52v
z(=nY=N(MyGam6~i9Cevw;9&DyHmoH%-GpbEQexUe^5B07`+NZ%=VGF!l<YH*qm>>a
z&NpK=tdz8wMHW-9VcMybc;P9nl&mYEe!u&kdK}w4P5ARPQTJLxJ!{?k%TF()VNb6U
zsX?OPmnXuYX5VS_OPgwhYr0nq&JEXpl>bkoMPU#|r^|V&_Gs1{7w|96XZ?@`mwudM
z9}F*N+peJUlWz{l=ZN$yn7j8E$mcDl-|XTRv7lUjkEY{)cB0?F<`9}*+r3vne<$Pc
zE&MycY<`I1Ftd&3C0>lX9(vx4&V-r|)A1HGk1$2JvWlb3w!?7g7_+4_Xzj<D6~EvL
z`7uw<1Mkmx?1SL|Ca4UmfsEfG_<DlzrgusZv(XCSNv5(BhUgR%7=Yq5)0^fRXPA<$
z=)zg%$RFSiX6_#X;2hKM3QUABg|(nQ&!p4S{Q^^U1DqF`q}vc)vNL<ypc=}=(3|oy
zlXVaHFeX@!#w$#~8E{`^j=qQ8Ys`6?&4n`=^eB&Df|I}&$(%_-EsDu)fca>~tr+ka
zrYIT0SmqQxhp#ioO5w~6CQA#lo6Kr@V8t;P%b^+1*!%m#{4GWuisB(N#DK<h#%nrM
zGnjA(3}PlzeGlAOOb-c0CYz})gQJfb`DSoGVT60Y<ua4$`S+BO4M6dXSv&%x{(>3Q
z1uVtPzgGb$VJdckrIe}I0+v@y+f%?*GU4|A=*1gml?Ilon1zGkR5kOZ4^-bW<NKkl
zhH>ZwL@o3FJ!<cmqZ`onp80A$%-1o#T_CJymVFEO2PRGhVIwn=hux2iq6(T#OlP{h
z4$`eO-`XLS`NG5f(u8mS?-y+EGLW7#1M`2v5U=e=59dERSAq1;PW#}?x>;v%zCLOU
zmf`e+@33|vG`>7{9V6Pe6)k7_9UKgK{~xEr*Z_C>?fNr)vC1QLrQGcj%qh$^-0R9^
z^fP9;f&Xh$$h)pUzwFAHG<RpuEPyp`Z7oFnGZn%CWUYPq9{ApE#CM?D$vn}c2fLU&
zyeE`<nT+S?@;+t==6y;h#zzD7{Y<M#xVMipTaSRukD0~-UB}G&6)t~buF)LRQJVWJ
zG@YbRx5F7v>18|3sC=aFa!~b?zVw2-7o|7%gZqZ`%1Ho|r9r(p=-|J0w+G}c$8LgB
z`+?g)_hpNHkdIu_28uKFW6}9FCI=i3FxIhf;S|$zEp%g;Zuii~2h4S;N}{Y~lAitF
z5C{+Kc>gGLUU-Wrd)8*7o4pp|?V{{WffQw*m}>|leMzw_W#8GqplkgctMJ(BpD+c(
zG$5iCObl$5hJhcH@gw~BYUd01F_^uLaT=m|g5%KpG`kt*LsOt}hl9}iZA}hPGuWNb
zU)X234D-+5A8kYD*PR=W=D*Jv(BQ!Q9)aHNWqvvVa(Cw2@o?XZDWLm4ka1~`;ykl!
zCWO}*PlT(K5lpl5kxaAqQB1S@(M+@dF-&s@Vj1#U8P7C#<Q79c!KlK%Fry=knWulo
zP_#HszO?$M3U0TzHo(=+*%%5%*Md$M$lk6CaqPDNQ8&eaMd8%J9{b_UNG)B((Q6{$
z(fG>UV4HlO7FyHR4hP%J_TDlwB~e&wbl`10t{2Wb-lbQ1cY9qNib4Bl!1(Ct$!M6o
zjMlF+XV4wFo#{sNaR=r*L?9JAn3|=ic{A|_X!tNiUhwP)lS#9JK&B6Zp?Fj(EGU8y
zJ%aE8vz%}jnL+r`D=sm;`=Kp@x!MHZBAMqYV6jIrBPbG(z{H(^-?tg&Jvx1d8TKB1
z$z<-+ZJx!nFNED}=D`oZzhs(d2~omqrp}Zyedj^*J+rzR@H)n40SwkN|E5E@TRQd&
zXzr0lS-`SaI_*~o4@(me_f&XE3!*^gZI|BVfH);x^$d1TOJC8t`Hb|_YyhuG?Z=@L
zF5Te?e1!BVEfw!bQ)Z%TiPA>8YN^ue6qtG>eK7;VJZVKeSn{PEe**lubaW#;d?|Hk
zM6E)4=L-zid+CUO(U<MAkv_mV%Iu>i193n$@gY>5WpnWkR(Q)UNYUsc8`d4FL9*Y1
zP&+C6xB*3|%>D_MF3Sp5fHY2)=LC4XYyu|#&6l`c^b}w^>fWN-DSbQ!x^r^i|Fw-}
zF(Fcn^L_$T<3D8Kd{Vsq6N=^Q5nF7AxBM>%{qO!w09bpuw1nc9!g8GVZ)^{RK~f5c
z47q#_nBlWmK{D$1j%fWl`%jG1_|@leK1DeO$651ZFscipdxC9AL~A&{+P)k*f4C}v
zUGJnpYqYXzs}jHe80E)osKqM1=7T*!d6RmUr0m%XsC4DVV*or>mQRB(DQsg1G;7%Q
zBcbBJJE{S2<xQ)hc|{|}K^U#c902>SI>{{5Jaj$M{_nScfq6kuipNYo1@7{gx!533
z<TG|d5{B~`<2?t`=S);AuJj9rxr@R>dc=a~hNm?0CA{^Lu4)BFZ|STU6i1}JrUG|V
z+U85Ra7@}Hz{}&(DFWQ{m)0(WFhJUeCc!79U#>#OgQP1W;pJ7SJ`cq;sW=1n9!jI^
znQ$Xr>MTc*DP<L)$&x;O0^lR*9a{J2NTa_4+Y{+J3PR*c$5HGsPkJr}mpNbhE*F}G
z(#~5@dnWx<gW3zJ+gXqmNrzFG^rh6h70j1NE4D#cCJp%)WaZLJ{n4{m(jEP2{ZlDz
ziEuZ5lafPdbdcS7gJP$wl16Bk?Alh~cgy?*49OnZFbWo(k?rUU;aS;Ax>V`1CHbgj
z$TkfDOP0)qK`mRhDicMHtl|odx@;uHEplbw(SrP`tk*si`7)p7^!zK3O??QO=duWI
zjPnawVK8dNvUckMd?|aH2fL-R?rqWSGTC?ZQm&Bo@dWoP**-G=T6T{jCU0c@+n}hH
z^_~irx3bBrpjj*1M61bnvbPUWtCNkS%TzD>hu#VwWXI%~|0^106RXhQPcoP8Q2i{c
zrq`Q;oS`Z94tbU{gpTr-6k6UbpLhla_sW09PLE=ryoVQhv0whS2(<(9R`mRGk$+Eb
z>4WmvM&MlK(GM^rZu0YyFz+E>KM9(i@{{w?<|Usp9fjRnzK#MDN9CFt==jR#Q*iIN
zJiHiQ_{r<Bk)jBYw`vE61Lc1BF)L2W9o^u?DS7V#^!JQBhJub~<r5A8a84ev8GsOZ
z^+?n%$b0tz*+uyl3Z#U}y+#9fS+1Q9;T5@aC;SAi+U0k3up1$-cYrsM^6?wN7A>!%
zz(S1t=^AwVy1bnHz9BE7HE5iCFqRIAc)6qufCPD1FL-fVo<cLQL^)Fn;a&OUDrhFj
z`~3*&WO?85DDKO5{sxr?a@}i?rOCTY0?R|W-Fgb%WXSiJVK-CWs}eoTmOK6gnn&^j
zLx6ZJKTEga6S;vxVo&916z|QG?~MaZfqc^-6ovA6v;uu0|55{%BDr%s48D|q`#ai7
z<hLtfp-gUD3SqhYXe+2x$~TRLq1W<1?CUTlRq}4MlB<?)I|dUq@;yCKtChEZfwuSZ
z7Y_ielRr8Swg!2xztHwU?)MC&ALZ9Cf$fvL_j9OhS1hDOhl3)%61bg;x}6w=U5ex5
zA>6H4d<;XmM-kH#cK0c2zX8rkQD(J+=73^hKd3q@l!syBpyFR0ibIOs{{iTxxV8&5
zcg56~P&uraxeOk9Dcm~)@1r<IbMYez#X)fUD!k@H^O)k>yYSFYvFrf`*k2)A1eHL=
z6xumCp(v#BJ*n`aQ06Jcg(RB)oK<{W4NJj_09vqyC>rlT^}NDI3DS#-#k3~Aq%hFU
z5vG{j4koTB+S1GNnnLV|3lpxm)&jLig^Z%ZQHo58V8<x@Oz<#PG3Rf<ZzwKA0De=E
zLzAyZioxNi<tW-?v0_)`Dq>dv_*C&;3u(UM-AWV%idjz}e5P1*7Wn51C)yM!Qk>Dk
z?_$LXiaV7kHq$$|R58nhw(ZJ3JPHTp<TViPR5}O2(Ot?1wBX;Z%$yC*J<4y+LuH@R
z;ROc4NjYK~sO`?m2NXVYQQoHjma9@luQfNN_z0Ffm1}1Kaaehq!hhb%geKVaQ95J)
zQgKu%YYQ4*<zod@(v(YPq4rSui#Iegm7hPOmZdy#6oc?c={OvK9A%3%)Sf7hzW__F
z^7a~N=Gm2heUECsvS|YxE>xcGj@mQjlg%hzD1RRgpNf=DdFazi<!^I9TB5w|iCUR*
zVLUu6S6)2}+$&{<12ij@GakTFm2xk=gR7O(a==on#8VW{KxOSKXx1zLx&SX4l-n!-
zd{o*!!{PoXW#ckbo0MlM*tDHJ(F4T}c3>M^-<|AGgg+D)SSJ!*WdHpD6QS$`2bj3b
zPA&x771k>o1ALYBoCbs8Y^Mg)B3QmP>_)L{0xU$c+lE6J%l5~no8mfKxdLrB*)%(a
z3*y+LG<ChjZr%W$1okFH)bFrsyFxXQ^`L;~J$6eF>?X0QRJ5hA+1UP9+-FOEg27aF
zpn$PRWB;KyM>>0y0s<K<OV>V&mC~ayn;l8B{~Xq<9<|5pVm$!4?9Q+4pn1w3pqX7h
ztH7qdqJaH=J$!q{UfqcvK4-t^1Yt2dArZBgZ1#Q7l(9+0H27?H+IOsEZ>@mvHQRqO
zG^<&^Tkzs7`@A2DckKNOpnlJm{05Z<*2M#W59|zz<bGmPtWw;6pV?V^(ZlWBX6%kD
z9Jr7S)OK<|*TK_W+@)J^W;ZwQ5sE!r#vtJLaW@4x<HQ|00n!89w0Pj0xl}EN>mc`p
z_RJ1(Ub_Hy<KDyp;Ld%MiNcc$aD-2Xx!4bY$8)cKr}y72u3;ryyu*zQgEWy_bPeW{
zxSbS^Oy(k*(5L&Hf$q%*-0hAi(zw-!AbiMWP6S&9H=S06nOsRcSRQfbY5y#T+hK<A
z2^YT~!d$L60Os?#$$7vPaASv|_MFqvG}8Wp>qXqf+<*==z}($yz?X8qW58X;8R!{U
z!7Z*qXI^nP%AoR^Tek$jH{389;A(E|_bA?SPF>-4EjM5Y#^N2<X)=WMTy-d@8@Nte
zVX%?ob5Z-q`St}_6Bn})#dbUY-At(N;D5|Sbtk`UCAb~=kMB|2%@2BvVlVHSf?n+7
zmELe>KR;#^OdQ~^wnArI_;7c?5AszMBy;7H_M+y-hhG7UCqKdo!oz&ZOW5`1&s{^!
zhwnkF5MRE6-rmP}yFLg~e|`$h7XtWgg{Yn2x7<WWgLs!x_<f2$wi-innx8?Ti?e)H
zOV|zOe_M_IhVThANjuN;lTcjbQ~QJa690rAnqmBj8Svr?KYR<QukkljFc{7+bVFaV
z`7!iJdCU*B7enU>A1njgQ~q2fX!7{{#jsnzfBi4m3ejH(U+{*x02cA@@<8*FPdx-&
z34d%YxXbwV^foN#2hWDElAkjRDzEwT_fV_m-4K^myybV-0A9<lrLB*5d<m^L>iCy$
zX#QExzn_M#HS#mb{6{|6AI^N{hbMuwiC<6-yn`_RG}v|sHSfT^OSse;ZH@v*&+I+I
z{6?tk75Y~K=OifKLvz32#-eZ*)&xVv1*r#c^pG%SGYq*3r(6Md7vdZ_+<zXz2R{H0
z3$3~W;U)Oo1>&->#T&vfVJbbZt_n;O#_O6eU=jR{5Yi68i%3DBJ0@BfITL^w!4vTd
z#dYEBNwC}yR;~j)PMCWJmg0rVi>M_Cd#3|%Tj)F%nu&rRBKUU2UEz<9a4JcdasZ^s
z!fy*udmuD^guzsyW)~3YLU%HlA&mSCVV1DT0+noG)kIjz5tOtI{#Zy4go#|CVjwi1
z3R|k7QXq5~i&~+OMDg(F!sJ;fUI;Zb7RAD1n#tH-3MKSTFBO*3)^C~Mc^@<t!hhvx
zd?gH{i0Nx#>}K@vjWBZ)*s6tqT(rFv7CeS)wZf|pu=Gwii4eA;UfAb`qCq%E&(%iZ
zGYd-}g<UP7`B{i<59%gid3P9c5SP@!><+uw|4Zl`5wFtv<fu4vI`GHDwmYG7T<mNH
zjlY;Q8D0d4*J=0TggBn&m_gz>+N?Syu4#+nv>2BHm9ygT(WnKBJ7}2@B0iy&(|K_{
zkJ?4?98C}|iH~Vjds!^d!BCiJ_oY?gRdEQtey@p1Lt!^U<esCyk)p>lT&HNU`Vop4
z@xeU^Z-^6DK=Y=U{uH%%@p@+fZi$9C)b5CtMHrbxaa|H>_r!-@piUBJQ+7y-*ee*d
z`{JcrsHKW8jc_JSJZY!bO1h|}EP@Qti>`f^=o1Zmwz%aBAacZY=TUns9vuT<u9$lb
zz^CFk+V{*C|E6$rffx`A+%wUo4#MZ6<|J@MB6AFG7mF7um!L#c(XXpi{O&iv%f+u~
z*S13Z&`8(mlQ<y?1Lde1z7d6+DuCvg?y8=YK;fZE`wiwjRg<;o+F{k^elX~zYMYEU
zZ&meE0DM#*X2Zl$)i7H2`l`O_1}~1OPSS(zxN0gbg8fwE$Qggt(AB^NsAhLYEl`zS
zApcULIH@W&(WO+0L*e3C)jG<J2v+$o22G0UF2$4Xt32rW`areXJ+6<*uBQ~Abk*Fg
zV98L`lVYZ7L2ndUs#&QhvQ@3H5u<pddi5WiFI0V`naDHM(64YW7pZ=3K&MMp3r4_~
zGF9h65SFXjB+-bdN+!aUS1QRX6qTwi$Nzs=<wx3a=&+(Sdf(ALtpz;nG$0M#?d(to
z|GG4-ghyTfT!iLsdGrJ6-u4OjdUT^$f6vw>(CIaEEhN29Q~p4oXd2Bg`~Qw(-<d<8
z-|xkDVCcWD9GnB}<ix<BB|r^YzZ?2r^~r_#!IOLAe8`_8a#0Lz9R|8#Y8kvAKBOzU
zIpR$i=thpEu;}P;7RNDn=%@E}pBiY6?MpHJabw)IeXaI`vtZ!w4;*-QFyGU|*O^%{
z8;B#!(VwC0$K2Qtr-GQ4ArPKrQs@F*U{vz|iv&BdXY-)8pB0g&rZ~XrYGKEjt)|I>
z3!6@_wu5YWHrfucbC#n^uB@FRYHn;k%{A=q?3HU^^k8)q5%gq#JO$}tc5!E@da<(@
zc<Rmmi$prbQC35XPha-%XtepUlW2<O&yMbiB7p5n`$mDR#sy?2*+=xyIK@s+forGP
zX@zJz!(LpCwzKTkA5a9dV}FAe=j?3LKG+Rm6MKO4Jo}>##RWE%HeD{V`)R}A5_@U~
zgrRKTE~s5*@9ahq#+q8d#1;12b||j0Pm(Y?*Vw)^lL%*HbTARYwxHKfBzufj08#Ai
z8*nC?J(&i7W7y}h@F|wHkI6yfbvDTe#0_@dD@fzn`*i!<Vuv8t6?0%WnzY|$)4zxC
z4m;`_m`G%w#lh{ntk@qTi%ppf;F8&@oiLHYuBYwS`)nH>iU;h4ae$|?JxhU0V~-(U
zQt^<Tvj=VI><oKLlv%8WNVC~RpFsME{WcUu4(m4ss*l+#eNjANJN^z!xvZSxHBZ@T
ztw5T`_9yfCtXB)L6tH`@VMq(v+TY;JGj{Prusmm1Jc7y#c3&-6ir6U^&{oX;N&EFL
z+1=gjuv@|o`5UUGYzMMi#%`cscR8y@zNw;uRnf-ZD|W~Nv{ka_yP)=(&1{7EH>}@9
z6jkhR??GD4E}{_qTh?<Fyr^LxjDn-JY@5r#y<?{p!Qgwgx&>6~SbGPkd|>@cDd^P5
zdKaScGb`SJY7@JXM{PUzScjSe_n6*Pj$AJ?v4^{kY+%J+PV9s>C+@%HpxMtwehHNW
z+_7x5Ide^!C|tN$8j^#Yl0wRdxQpB1s4Hit8L=B@<6yy^YgHn_OCKpD^b_*r0@s4g
zi))pN-g|SaN>TIS+{$1nfcvx;MIiU>6#!3gTYdx}h>NYl0G;F<=-GFQbN>kjPjg-^
zpm~P-@EzT)+_IZ!3+DPz=<6Kk`W}vkaPMgzbDmpDnN;=*Tn%MVT;zV92K*&1hNA7E
zT+R;=UgqLxo*c%#p&;uOE-)CRS2;B;H?MIEC@m_S%b@s01owI{YLVP`_h3GX+e1<Q
zXii1*iWqMFSAfTIYMS?5=Q2vba)aA`2Ig<tIrSS<<G2>|9E#^M8o+&vJLiJN1kP~-
zoVmlf&jD#7r~MObcex^DmMZRXPS{z);$$8Lxs$nfda$H$A6BBc&;2_P1|M)k$ir05
zo3aekxWzqCJmeNFfuVHnZ`xtb;Ot9u(8=WH%mrx{SKbdrHuqr_bRKa>XwIL*?WTmB
z$K1XPxRhAOgaeSvg}OrcluM^ena8!Jm2^Hg>?9m5;O1LkzL1-73;lh@xl&%nb8aGq
zWL|K3ikua3xksQ`%zbI6e5jY)G@8$pa6d&rwUqmB22{(q-?HIMIcI$bOBGxW?Et*u
zCegB>lKb;Degdz#nKZI*IJpg^Roo?-Y*cd{k;#l@P}+8I)^O1pbhMTmwFH{)xXbi}
z*unRt6bvu^PP84WNBBLxVDKnEgEq%}`H2Hi9OIciU^~tmDTU0BuW5d3^GX-s1Nf%_
z00i>B?Ll*bKTof}Abv3|=1%hYf1)_WOSYgm&6l4B{0vqOAUn%{O;7h={?R44c8*Ug
z7jXYw;MdUW;Ud4E_9`#&*(s=n^6Tg)f0_5~2*1PlYw@UE;hQM?^(t@p8#LGWavGU%
zejnZ25&YFR5JvKTNX}P8@o`<z7R^iPmk`63(#$26kNpQeUFQR@qqxE6S_R2m#Z7+P
z2B^mI4m6>U=fBQ|>McHJEs6yGTMFsi=7-aZ`3}FR9fXN|22I-U@=kTY-Q$<ffJzcS
zumr!0Wd0F7ZBzKl-R|oK8}0W?;aVEsG6Oz6<UftUwM*ycxPdH#-xCFRCVz_p4q5z8
z+F{M+*QKNOh<BmwnjGGR(v%+aS>B+2!Us5mC6~WN>6uUYK_}3OJbpLzET5l5^NIpK
zwh@|z{J=j^d&YORCu1m!_z@IgDdv08gW@G`&;wt>ccu=O^5#U)l<|9MAzjXY%mT22
z-$bE}SA0(nDwRA>8ym0rVe`TLhWDd9w<><J6)M%dQxdxLmalmRTn+ydWe?W!V`RX+
z<DK;Mbbrq~9EP-xA21Avdfs6xY7Kk|?bUtYr;LPZBR_Hn+CK8Fw_r#<@jg{x`^-;3
zq7GJlLs!83cH!|9XgUaOPJwfW@K+3kI|Y#z;Jbu0+PQHQM4E~07UC%@b&s$qgu$<C
zuQ2Z#y1h@B{Tg<igkllg`vrH(VL2d7^T${?3%A1{bP;}|JdA_FE(+Wo5*lbr!Bsd(
zJ9lovkUh|J7fNY*eOUM=6qdY%uWq2tTew02T_2$*_Oum81nVX^b5y7Wr(NMI?CyoG
z9TVDLL~&dQp*NkMFlQ--+h5rG7w`eX7mla}3O#aR;)Ebu0=6I_o|XkCg<i|i?NdVA
z@vwVZXiJ&hXM|0ZV{ukkd>9@E3z0NQKPUY0JKPQtR?I-{yzoyKaM~{jWj>Hz6b4cv
z+$G`HYSco7Oe9NTT|1H1C}F}pn%7(rx*A~qs^GB#9$piexxj}Dp%jje5bn`hE>ifK
z64axF;T{l13$ml&j1d9~fQuD2=RkN}SaAoMH-wgyFM88145HMuI6<`wr18Q!TD{#8
z{-)S(g78}+JiRT1QFh)PA?N~pN)*m~MsZizejl#g69$E#mL!b-0Va}#QGPJ-Kv+t@
zz*M1uV(V$b+EW<Ahr&bJEKV23u7hTVAnyc2nSy;B?Q>)a+bL%`TNra51|JE?9>UEf
z{5lH2$3nvb2%iX{btrO$AEtulsgOnc1$n|@iUj2g;q~ZffzYlM%ohs7gP`(EX!1bY
zbD^9%`a*c;f=(0(M`=g5SkN~|MudOty`fqn1i1oVDh#_1oiaFuvA~lr3AGBroidPK
z35(96PnCk_7x4SFU~xz7jd0QpMU|j_4o9nnfzQD5R#@2qUepMkhC{PfaHHGkouHiz
zmiI#VaG0+XoM|7ZUf7sP_g{mcqlfMXVd82a8iiYwLjO?+b%pSg;7pqkpN0P@(%vMr
z`WYj$T}&bq4&qYEYuzE<n*zX2u`NAicZpwq0=J{skAmX6#fwF-yGLyC61BZz_+0?@
ziG{TNbwKR2OOE@`S?sd~RTps&1-o3u12ms<6Ju$m<}Ut0I}3+JyE|08#QwA4ueW%J
zuIN$m?ND(0idB^MdQ9vcfx=&WO0)I=al{cA3>1sKFhD0ouL9IgiRHsVc3P~a{fS`l
znS&hn-#Kwb1K2{uAe#A|7k{NV+66JRJ=iXa3u)1CNjySH{GnnEMX4@}cg}$(OpLq?
z%`0NVZLnPxUmitqO*})vn{Y9IHQ*8ApEm)B6zASW5haeK8#Y=T+X0+0;_80*1=(Z8
z<U(}qx>#QUzi)`C1EF(MJoXoU0&(J}Nl=X!Po6~EE%7LYi4sHwCGp)B|D_F}JL17;
zc#$Y34Z+CV6*aVbcTarl2=hr|@f=Vmi|zgcE=BCC2jIS#-3aOjq7iv{id0^lLbp?z
z*w$^7$v)B!u59s50u&#KUr_c{j+jk*!jHvelvepf^rjU{u6Xc!s5})v(()%y?0X7*
z&lmrl0F?r9h6Qbfq6hu{o{1_Y+MbK&4#B?{;wcJU7Kv*X09Py~?gHSY=<yhU67iM2
zJ1muoE|is5Ca$7X&~mYq7O)j!a&NS~68l{QX{Gps6u{SFVFrM2#Ksy3tHjxx0H_w7
zXd?brjG&iijrg=L4AzRhDU$h4JWjKy_u?vdaMp>FPou3~WJaS)4PtmGO?5tqDsrk(
zEXIbf;-eUG9*v*Gzi21^vsghx--K(0+IH2_THqa2ooRbvhw5(%G&ri>wuOn^D%YV9
z?oox%W!b9=rcVI&slI;=N1aq{W<zDa>OSqn9Z+4O>?&uKX+Pz+yQnfv&^f3&H3!Zd
zQjMpiK37$b&9LjHGSc+TT{X=e2oKf8j;ML6PSZ=}u&R!}%JEWdrp+^NRsLYu^-+zu
z4wfUTd9<N$R24iJ0AH1VTlD^zsv}LWkE_b*XXK}f^_1Xd@K^oQ0_Fo$#Y-@VfvU*W
z&^e)66$oLFYRNcwaZ<INk_%3$>M2NcT4iWN+ZomNqY$1|E&KzPf>j0Ip=;+<xdi}(
zsIJiV-g%V^t<x^3tdxX!Q5CWWu3b{;`hz7@wagKQ?3Yz3Kfs$X)p!cfUr}A|57Kbe
z$@x%?P%&dc8maPZ0BMx!O+1QdRka2xF{;pGpovwT>434gu5yS3+YOa-G=w)*e^Q2R
zoT_svIOA1uw5xJU)hP*v5>yR~0KcuWTm;~bT~##{Wuj`+1R(CJnkvzFPxYFnQ%S0b
z@$frY^?{acDXMsioZMF}SOd)mD#u>1l&YFQd%9_=c2A-5P}O}1hC5xgk22LWR6GV4
zktg40@FGjqsRJ~#Ret4Yd!+jK2xK`b`=2Xe@Ue=GfzA_^nI<{8s!eNA<f}Sgh2I6L
zoDOI!RLT8-c%h0!N-ly_uKm$gtn#4;S*hy5Z3xR$K`FqMtM<~ntWs6r4)0&9-ZTRD
zM&&dI{d}wXa~tf{s1kFaS*zM@r#+f?suBa-f3Nz(h+3U0BnvKnP;H<My+#$g6*M1J
z|4;_ZC)EZkEPYljrHNOQYBJ^YZdbcdaMwZIIvuqg>iKkU?^J&(huvN3Z$|*`sO}j8
zz;5*=nk?*52h!tduX;vjJ1*WnbsDX%oz#hg(70c{hVsS^sE^V21kUO%?ZM`v?mZFs
zgKGbE&^)A`e+rJes=uLFt(*Eeg%RA<|ILGnhkEt_6rSph5$Nb)b@4gCz0_4tQ1e!&
zEk)s@9z)6ON7Pg9@woqvsy&LK<E#F8CW>R~UN2$yxccQ<aQmsZK1I!6ok4d_fI5WM
za)IhLwEuEK?YjxJAayI+Q#z?0{WG{vskaV<ho{vAlmmB0y`&Y2v+9X!0S{Jpt%c?}
z_1yUohNy?(QrH#e)n&ubctO2Zg5sjOhJkOF)t#(xCQLnx9=cc5pD17*uI6daB0}Ah
ze2P?$U@&-5>gBXrj8?nVLNi94TmtS`b;2rGx~{%PTL3rIXWC<cZmL_IfroMGkqQ`!
zR}Yv9@9nqLcFO5ZP}k8T{I)tO3*Ek>UT_D%M74P;io5EH1QhqwOc4-C>QIU;C##Q$
zAWcyhErX@|>LhwkK2SSR9$~6_@@`m4Q{R6FvWM#JW8qV}x@;T(8EWlR6q)KZb!f}7
ztGkCnHCz1y?Snp2ce??a9Ca%i%Ut#B2yj1DFQMO6p86hbkmalS?;$Ku&qHRsqELN5
z55)_04|*6BsS7J$sZu@rEy!N0pI^l|y-|CTuu8p{USrj2U+gU@-m3Ryg0n_#*G)pT
zR^5*FBj2fKbOPeN`Y(z<*QxD+@S<L=>H%PbdLYGFKB#v(qt>X-qD9q5H5-89liFbg
ziqGn?^=NBSpQkTmwrc|K0pOrH?gmRcG%mCuzEkrT1x|Nqy3j+<Q8U?2(UaYpFAt*F
zqY-n_wY{1<J>mX7jni{@;e@<32oGpZ(}K%cvyk%dT{N3JKzLBI=Xa<a(gf2D@2Xk-
z3)<W?FKH9YU8DOC&Uk1RY=<+Rnv;|-aai-yOyImUf3AZ)Z%y(#J1&BcW<eCBM>P5d
zAdYI927|^|Gdmx(W16pNvVUB&M*~tnjWgw7`D-fan~(ra=`hp+H9P1|KcVrZZ?J+i
zXJ|5aQnPL*0H-t`D5P>$^B*N@25XWop%dpc6U@McXts8w#n^exgc-nJ(0J4H^`fT5
z6BL&;1@Z7ZRHM0$u3gq#oeVF+G{?U~?TV&q986r*j4?oXO_LJ~K)7bjGLS}Src<U-
zq-NU|I1{BgOd*13&3^{ijnVvd9`IOA4eiui*Bn5s%dWVgu~Kg3P0gq?DB?7^6m*Z*
z_`HYvw>17Ws3mB&zJQ6_nl*=jzoYqzR*i|8Aw6;b-PL?Q5^eW16?f6YBuz_tyCiFN
z((gD$WBe1s`<kyPC-Z@3_Hl5gYC^w*qiLG17Wia;s5zGi)pSiM<&tJ-oM%9qsks#h
zVV1_5GE%ZNK{)_E(o8M`TaG4@vI?GP><RE9SF?lirJibf(MDjNCV{ek^EI<6gQh_9
z?FtABHEtC1eWppJ1kvZ37qn!5q3KWditL&wq;D&VHSx6eEzxXhfNH5mIvF};8g2~`
z<(hRvV5veggWlV(H1{YPQK{L`4whbPYA9Fkji%L5z^gRRDIQ#{`Hx2Ct>&+<QG2I(
zMK9y`nsM}ws?%ikKwG`$`gNFX(Aak$Lis^+jB?f*HBWwr-yby*o8b2+O}rmSKWlC;
zNAH_7nlKdGwJ*#N?$oyW6}Vm6IW&KC)c$6J+q<=CV_|TQ)<XB+UhS~QVA-d=R|=ey
z*53uf{o4BJP&uI8B7rl`+TZQ3pyQ&=P{6LM_HHtC+_bN9P;=K#T@Rl;w603@*Harf
z7R6z$kPV@iw#_@Jcxz=Y@WMxXu@J=(tw0afquMfxg7|8uQc&WU)*}%Hk88_5!)-t9
zXG+QN*Uk!n*#Pa99`ybT)T(K!dO|y$CNDwSY4mG3sr98W`YG-F_2}AZ?f9Djp3$C5
zh48HQ<sxVXYui$0<2h{}4N!>IxDb6huZ=2#$_4Fc`gvW{9vX()CGE{9SP0b`Y58<n
zyKOYu!n9kDQmFfiwv3*7SG9L(9(Yabn2uVw_80nnL}-6`0rQdCfa9Qv(l%{@YtjGn
z>AE(N9ws-mZ+k#^Q``0?%*SajI>S=Dwj(VNZ)y9?084_l${W<TwWGFRobG5(&xD1$
z+8+<m`|qCiKz9sjlC}#yJd?G7)u^Rte}4$zeeK%aP)*f(u0$<O`^z~D!b5E_?Ng^~
zM~wknhSrb5ADLPoO2>JmZTA_D=4b=w!;8n-$CT9fL_2O80J++q0-*U+J9{#QD^J^t
zzPGmLYkyjavOxR85!fx%&RGjjpJ^Y{&e(Hp1CQ(TLc7NZe3AC*AmEF&+rNS4OYO5T
zI8&nSNzbWLZ4G_GP^KM2&+Kxo7hS>%Z6NJ$ztWa{4QDE~a|H-rYpvKcRJ_rC90KYp
zyY}}{KvZl0Y=TqowY!JHnL6!rDRk<!t_=`2Xn&vq`k?h2gaK;QRtCYfkJ?iS=-MZ3
z6oq>}Yqu{3ca!!X0&LeUxemJyy1))-+o4-mkG7q<GWsfam+r4J2>0j?(b{#d&OY}p
z5c_mRG(mCFEutXIeqCsHAP(qm(v-qk_fIbjsf(_Zf)WRHhv{YPrsIEuGw!-vUkE*P
zA1Kq$Q+L`1;bGl&ihq0QwEe*8tyBL76(8M<5D1UxHXH!wQC;7AX!F%&*eQ$Ym~Kr2
zNd0w@wCx<A+d~<5fx4fPfjFUi@D8;gUD*v3Cv~%D!kJUL*pu+^wC*N_FV5&z;m>I(
z&g%Z9Ar01@6j3{;8`&8u7j&U&7`&*v@)^Cqq|5Pyg;3p83a(w&T^&NJ-!NS{ZQWea
z-7Q0LRrkUf4qwx0E1?>$Yeln`2wlfFpo!FVy@j?Y-I<9fqIGX=5XR`H9fVIebmM5B
z?xt=-0tPrvr=$FXcwOEa)Nbiqd&7K!?!;c$y{+rI7u0uj-k0hAOVo{}Nn(=jw|+36
zteZ)DJt?|9bgSLhtx*B^K=)S#gsHlBiC|09U87yFhq@pS*iF~v(26`mw~aPgGj-9U
z!JVZ$RD~i(cY7fKk9FTmK=wrUhW0aab-M-v{#56BitfKWT{qf(%h&C1o>%E+&}a9B
zx>8!&KGPM_meF$^QiO0H=>DYdFJJ03bpMv<WFLSl)fImPpiK9}cW5iuEr<fHLicYA
zbo7<(PfBm8)D_dC;k7P!6#Dr_C#MwXDxLWkaN4VNs*#|1tDDjt4%g^LoC0^Pu7;*p
zb-KvK5Z3DoY0JMs*LgQAeb9L(1K+4?oCx7ZT^UVNKIt;>GFN=o)%*+-O}fY{sO``{
zdI<A7^+q?S?9%6sM4O|2F1?|5>q|o*++)|jy$geT^$r3?Z=b$s3Ur+Gf74WEzg~6(
zZ3pz#)et)C<42=*NI&6Qkh<#chQfU}y@4iT?)o3w0N|m&Gz)e;_38}(9M=CwTk2l=
zj1O?sTc1MT$NA{j(=Ydk{xHpij_U2ptDtjSZ=)~U{PaUw!V7=B^a~UL`oSO37O3|T
zF|sH0b7>DENMB3id{W<*?vYdaJ}p3cTJK9+5oh!>N8$!Jt8b+FNr-;vTL{nVRlOm+
zpbw&#%SHVVdTL$LU!@mjsNTy?o9LJI^Ok}wO#jy*ICVw;6Qxpy>${vlTZH~51$83z
z5<eiK^bS(cMC*g|A&k*Sy$4&Yey|ljUDuDK8Rrc>Ls>aD^&ynd5~p9?4l42btmaj>
z-q{Upcl3Nq_>`#sZlWE)yZT@Iz~DW7xgAB4K8HT{NY*c$1z?K)UT3&=Uw>~d3_j4;
z{)j%M>T~fIaTIC#_4K^R&_7E?EmL1jJNjArp*>+YTR-;))E?;-ln0li|BB-0kM(aT
zNc}`#>I<@5{o;cx?!Tvc%K;32p1#Ln(B$g_r^3WDy-o*bp6k=;<LDRqR<sT)(sv00
zuvlM9`D`!sbyfgM^jGN7U#f3MSvh6;nLOHF=_A);oGSIpXc_lf|1(X}-smsRfJ&7<
zBpS79{XaiZe%D*Qu_K19M$cUZqE_!nE7f=UGhIRRUSCg%cXj$cDX{cG{{;ok8}&mR
zF)|<Z$-cmS(huE%w$J*mG`nlkYr3H?+YQ$!J<P!{g#w&A4Abel?lgGPH!r&k!Ib;r
zXxQltFYNmaIllt$WEe@&w*7|ov_L;#IBtVoXT#7VAaybLQ%7A5^C%MFX6QgsVt2!)
z<<Rsnq|%2Uo`wzdWIJrgErrm_uxcL2ybaUoPe%9{4h#VNh+*y?*gb0aq7{bA*YLJI
zieq*|TiW<KZV05OfuG^`+o<^)R#t*0z+n6U(m;b{BWO+-hD`?|$gunqY9|fR^gcOd
z_?M=NrwtREP@FL|&<B=h4L;9-3pR922j@9M5Jlrd3~gxh<Gi8ea^Nl)UeFr)qQRa>
zx9TOs#|`i;)bO5y>z55GdSiwef`0}6is5gXGF~-A(`CA5Fwqkx+z|5yeTp!2r6@t9
z;d(0Ejxs1|SrlyuKZGL2P^X4UtYI3hwXPc$_W;=q!z@~y-83{&2sX~}y?q}n#T!EY
zgU&5OAKGF|FsuqiFK!zODSm&)P`VG?iH47Vpmx_V_At2b8CJCeKFN@D7=UC$A`354
z3_a*sa^G<G4aVt#p?V%zQVpFi!$O+j{W$<08tN$?m~P0P43-STFFWmM%rxxp0~1+>
zmu8sAHvAI;;3ES!5p6k!UI73;Hq52JRq@1-N)Mr2Lz~sG`_$l0e}N#+@S1MJe8Vit
z11~U~qR(Cn4WldI%rk?>Y^Xdp<Z*z%FvvHfC^BTe181>e`Vh)*erec9h!R61rQ?+w
z4pORmg`r^s`t-_RX$PMw4bdmS{o0T}0c~##DacG#R2ga;&{l2mry$f@Ljg@SYYbZ!
zf~?k1L~g$`w5*1~_lEDAP^&XMy9%G`4fBFgYcL3F=>Gd)D2)MIqoK|P20t2nVxaTM
z@HrgZpAB!ng54%VcJtSc#tkN1JO^WI3hM7LK3)ObPGh&u7>iv-FK^%+jX%+JaJMnC
zJKFXbzoFpbUgJ+TknJ;8_kaZ_<B6_-?>GK99$wfF7_a{TRcGThO0IA*j-q^(gT@NV
zl{jQvPowT?oIDXdbTg*xMd5Cg{tBUoQRf0uPh*=(zz-W8h}6rtl^*Zj#;Fu-^D!=_
zMcol&cSp1xHMVIB4}Fb`=>c=hc;qBhj@yl+DJjj*m`Cdbe`6gzN&}2O{{Rta>~|Ek
z6UGM=9Skyt(k$zwv9|}t`INCsBx<LPf3HUEjIoa5wP%gfwx9?$D(H)xb4Cr_sUgNY
za@5WnPf&{01!DniKVLNJd%=rKM*Gj7Koe?QwgjGDHtx6$gJH%l8!;AFj6b#n{;F{R
zzFJmXGj6W}KHR9!g^38`Dhg6W8mqE#eWHw8q+p3Q)=~;*jPVyESYnMc2LX58xT_Ob
zZWy0Xw&YEt-)8`B8RhiLO)!?*9|LjQD4z_2cZ`}c027VhuL9z(aW=io?-^?;H6_V7
zc`ES9#?JI-b5e|n6kEM-+z<#84~%_&0%@wTxE!@KW4Z!eduR-z&lA#(n`tSXVf;vG
zHkroF^y|tpUZaOzw(;R$3g$jCe(eCA9HZA}=sY$)4MOdSvHN7WmTT<s5?(wtc6LWC
z&p5FFe&-uqYT$2y@$v%H3XS9a;qNo!@Ly4TZX8cRnHR<n^FUT)ysJlBv9UFMv+&aB
zM~~nV<Gx<tEH#dCrTAx=v60ra<wiaI>8=W6l@VQgW$gL~fR)CtF9Z16*ku6N-WWT6
zh8I=FQre=fHmZ9=^R2P(59oG{aR_}|Qfqv)18wh&no1P!jg8kJtTQHm1I>ElK1#oB
zFg~QE_y^;al>+X+Mq~X9sD3n#jD-82jNdGV&SzsL{k)otTib(syQyD23J24?uW>1M
zn3l`o#ZFTqC3@{LWhVjWXqx8+mEES5DNxyCilK$uUQ@+onBQkAnFdZLlZn#B_M2{q
z=;r~G+j^L_JDWOC2;Ie$LJ!@8rfqXj95UUcd7!K5Rvp;fOq<=H;%;iS4Qw8!?`XTn
z(-gKBDu+$FZ5Ssn(-4|(dz*BZq3L6~5f2l-CO>)x9y5(uiMHdWTl5R^Gc{5|g1@P{
z8?Hfs-E^rM(m>P3dT^gGr3ZjJ$h6oAUYs<o9RTiArq=u6#c9)aia?w(EgcHGXHBWJ
zV-RebNE3u}rZC!>2{C<5E6wvJM+!7uFm)(H?V?HB1uB<Jw)s#AHT^@~zHIW{0t;a#
z`$mfJUNOb_z{FLPJMDR0Gc5^&GvTIa8kq=_HXTKzsS~B2M49^19zis|sRba$G;}mN
z8fzLk9>sN2fEB_UrUmz*dDC>0BD8U)zl|v3P1|On?Uv~`O5{l}wds%AZBv7tvTp8}
zj?(s6qG`#OP`zvNp}+lc&vcMN=t-s-6pu(Y{df|6N-_D<w^H{_cWHO_fhqSW?53LH
z{{>5$De@+Yho<#Gz@?kcQdls<G?J2{GEGh2qGwsAJM?7AHdPDo;*n`}e~Q24m=HI`
zjb}=x<@ys-@11Za*Ob}_;ZxHF3Qp#kMkRwg-_-pfTq`gI(agTk^v5?a|IE~v_QRf=
zG>=idFs;1=M~h6=6pJc0om~UXm!|e(=*BapJcET&(>Vj$%1kK-X#H1ia-s=Jh3T9Y
zjjv3B?cr&qDR}`9uT8!CK=qC3WEg%lRi-H)z+G*cPrKP~O&;`<e{b6K7XWppu0O$2
zz3B#J1T>h63(@w$<V0J9jV9MbkbN|bqLjT)rpP&{eKy&;(ciafGM%MwI=7n>4CttX
zS$YMv9p?2k3Eye%^cb~WX2~&_a5OKZ*vxLTDi-)X=GnAEx!0Vx5Z&Hq4(^D;$^4W9
zV88kBLpXZCoI-gN&gMM&dqOT|34`LGIgTFdhs?9c8M~`FWFD$+=Ckx#ayKubP@0GN
zFJClznm4wE7l+NvTabF0uQvkkZT>_V!#?H^ioG2%YyD9>YTiLJPG7TP9LSED^Xa8_
z-0WWk6+g3IEk?%Q+~F$P0?eCVfh^Gcp6-zoc5}@Wm<Td&rf2s_v$q3kr_6glK=riQ
zB@Mze=GBxocGm3Q9hQR4|2zWeIrDtlBnvU0_!%_k&0A?!c)`4s2jHSPpRVL3^BcNj
zLe0P50sON0{Uq28Gp|_=;T7|#)=;@>wpUP$=9+mJ%_YLkLsG#OVRoGaok;V}l>kPW
zozB3gXmcrj<{x9W4g(<8{Hqi2*UhyQ;k{wLpAEoG^ZG?_EzUgC4Q=t}V~+v2WnOXt
zwFL9aMPRvY_M_<f9rGR<!$k9O`wr;bHJ4Ff{GR!r99)AWbN93GBH1jR0APyw_k1Ak
zn;Vvb`+?b+mQ|_d85_~jH1i;uYCbgITnAygc^t)yGR)5O2|}iMQx;UR%vbuMEysN1
zIt)EFi<D^c#Jr+C{LM9Q(Aa@^Y7W~E^Lgfn8z9X$ccX<xfw_i$SB2(>v}Ai`o<P%v
z=jMIh@actl6h-HY%sW;BS8VP-7nWX{leYp_V$MiITd8@t7Sv^C<`=Y;oBMYKb%ptS
z5>#H92Sfr_X<oUBl2KlpqbSAkjd?^45LM<w^p^;$%`<7o@2z<ot*mRzgZrWvwdRLQ
zLG#YMfpP-go71!4Or80w`|z;dY^QyI2J@&B=-~%*a58F*<|7o0{b>H^1mP!hH2tbS
zo9n!QYcemx62h+7Zuxl-st%UR-=n`fEX5aKaHqw2JPhu#{M`!9I9giKUn|*d>ChLJ
z_E>(UUhK8Z8359KmSK80>SP(Q9f19opXvLN0~V2zFr6(wT!yBLWh;HCa?ql@1eHUU
z#J;fLYRRCFu<dS^J@g`RxAgr7Ivy6uU?4m#=L;Y_Y?=ES++LP~Oqln!$U;%`v23OF
z?h(s|UMP-Q?p%f?UyIvX;Eq{#(_{9yrFRr8`B@%yMB#5amkM}*<s2mw2U^(Xu%2bY
z0C*8(w~Xk4ZlAO)=Am=SQZoo9PFtpTL@&-*hSN6hS<AsNI1_9c*A1HIEY|&~g;=^x
zfXaDG<V}!Xu-qoLi<YfR0Jvmnbqt!JmR7}3xonXw1ZSA#n^*|1SlWCKpRQVpBLKK&
zvB!P^hr=y7h(#-+EK-`8L|Y1Jg&SijlAwsSq|zhlx@FA-6gMp2(8BMgC5tBLah6_k
z6!8}Ia(Hpevdarag2l-OFK%1fQHJsz%Vi1_C0e4N19#VwPch_smbP6{OR{vgA4Rv5
zEwL1IOR=0@i`sq5i6hW?U<s#;msHDN6!}lHoI4KJ9$JzTAWXNsrie?1WyEZZdZy*m
zX|!co_HIOxZRy?`DvvC4CBWraN;ZJ{vBeq(XP#Kz(>g5I!kmPmrxuSmdivy9Cezmz
z`IbS;(3t{DfBKfK&=T|q#_O3S!u|E4R`xFRS7u&XqG@?wVwtoP8l{#=4&W@aOge^I
zxy4A!#tO?>3evr@%=;QerR5vSEqra+LGj@?mf^G$RAni$0#|Ku{0P8XOIkY&MU7=4
zEdpyTaUan3&Js^sR_`s=@6pXVi<_NZ8TFPNO5AO*d?p7!Shmp@p^cV86TJRtc}Bam
zpDdXa?fPt)bPp;`mLasgv)yVxfHnuK+Zu51us$=O*lA6r&xv+f)t%AiXl<gI#BOVd
z2LOAlztA_jd##_PVA*FaSVVy-C#%P8IK1E5xj%{n)}W05I$P^0l<Z<%PAi{-)?o|~
zhpckSByzR3pq(H$>nABZbhpOQ>eIs-POoH7Ys*d$9<~lOq2^`n*$WoDtqUo!)5jW+
z0t>#@@^p|Lv!=D9W%6<Bp4BknXFb>*g}+su1-1Zd0EG+!tpX)foUr;)esqwvJw47(
zS~v7Wamsr35ok_ZbLe}fGuAHj(dk)h4dufIThI3Z{G4@t1q_B*+t0$NpSS)Ni{gUS
zGz4uIt@AS_cuZZgem@R0q1Isf<4>2Zi|BzGW_7v&hp$+_3qx_$`d0xE*Q~3$;2MNm
z8&t3qVU4BLNu)KFW+_qDudwJ=L|a$VZcU8Ud;}`7)}FLKbKN@l0ctm_%jjFGo7Q%e
zmmOz4^gC+yc&mi|(7-M0{Ad6ZtOw}fb=%tB6WzXJ)y{?8L~FrYwB5BH4n^&rb-@;}
zC0QpV0GDjdcmuantm86)yKnuQV*3xQSC4}`)v8?t%{1#~+WCEG4Wtjk)2;nzgEGVV
zVF@f`+O4fAzckBgF9Ramnm~`KM^+<+eR8b9`7rp{n$Q--6YKT<K;&BUC}Z%c)%OJe
zdDhKEfahBmr@?%I)ptE=g;w_#s6DfOUk|e9)+Wj-e_{QFQb3EWm+ARbY)yZRwwG4>
z5c+_u#5%VKjiuJzPUvWv_3a!W%B_!vp{TI>JOk+~YZqGJR$4z$9^h-MtP0M&u?{u^
zUS-wO-cPmFRRWc_R)^W}x5hf3rtr1al@yhKXRXs?)Zbh8(?`8^R{nR4TD|qI{SP!Y
zSSv75R(!C&Sp`I+wZ9IepRF^Fpw?vdr9I5;wn=SZ!ojwp7Wf@Df68~;Y5Sd`D7$Qk
z=HXVeB~e^#x6RZNoO^5+|A26>?dc-a_SxdE0^nrx$%e{)TXzf0AFw%SDNN;TyV@H%
zF1A35K^?SB+6)tiY#vDIRJhubonXSvmg|82y4w<I?%`ppevX=_ji;sTVOz_=VDYm3
zN?Rh{wxKjb^|4uK)_cSj)*IbEYHLH!Q(xPtuHZaon?Px6$8Czf^k*>qZ0%a2(ck7g
z6~F+S<9*Ns+RhrleZuyJ{?0*=t>G$)leTevpmNGK@h<SEZF%3JIAe38oU*gFg+t(4
zux->);Lh1j(^D(NwsR!f&f7jIVBvzT7fr}7+6J_MPnT?KkvVHugxWlP0K9B-x(sQU
z&5(|Px?&6M2QRML`kX`CHCxf&z=zx3(6{*!wlkMO8fh!)jarngXe(;bwgZ_cVr<iQ
zp@_9L(9-a_Esxd=H*BjYd+nxe`>!bCYy)U%7H|8x93I+l+5U8gi3Hn0nqc3y6?mYB
zcWnAAFrR39G7)y~+JZNO=AJD}1@0u<pa&2p+u~cJNU<e_f$hFc+Y@XLY)fg%lxpii
z0lYL@3`Nc#+B$rJwsf0gI~dBa*}~D5X`31jT$cOR-#gjg-h^7N?FI|_r?#)JLp#sb
z$saZgZ6{tr_{?_rJ7AyNcu%ywuzfomy(_ZK)nEXMZ5_Hn^QG-adN`HXZr=l-)OLg3
zhh;X`Hn>FPw)tw*Ds1t8!R9NQM=**?+Z7M=@wKha{twvR*oM(pW>vPmE6`YNd-nvw
zw>BxI{@2*1w}<&!o0PtPcxQ8`pT>LJ-x(0r+2%|`f9h@jkE833%d-07np&EcnU%hK
z@4e85so8Ke%t}kMEXyq0nhpK+vIUgAK@emw1woc5OHfo~E6AQITMz*e{C!V<ozK1J
zobNgJzRz>Vx#vFbvokO;xqRPpn18tZS2K81%d=^3{AhVV4aoHJ;~p?LvpniLBp)xw
zoQ(I1;r^EupmvNw3S8MUZc$%3F#e)Ny(8nR)$qcJ@c|14of-1^fH}g5YeA(8V|6@A
zu8i+;!E<9c-+;lRjN`P}JI0XF`|QqGy&aZ37$3U>)02_Ngat3g2S-4>88h@+`!IeT
zrc_m5#@080=Era@0k%IQEeNFmhAZ7Q2xKq^02;*j{av61Ga3uwS_or=;(MWtdfG1>
zXXMgtlQ2drZGOTT9j(AV!PxZ)6e1W#I&_X?eCP?@Nk+UK%ttZS(1&cI8Gdh3s5XYt
z+7HlJ#zt54MI6JS3TW|+8frxX;~8&|M8-@$d`e=l=|gSFjK`D=p2Ap9*Dp>ns&2vH
zX~t_|08M3llm`=OjBk#j@(km_lPIM#_8f-48H|KW_<hbY;%Ud4$=LM-O5bKN!ta5Z
z&3J7diaCtObHL1Hym%XS&oOMIsLW$H<iqZHhNTCf7Z_nHP|9aKvj;vEF^mSN7c-<4
zaQh<Tr@tUl!kBppBBhLs2$;Xb*z0S%?*(hv1F)_#B;IJ|HHPLHl*$?EPf)tfcxMEH
z6^#53V6Kwkqd;X9qlAt&s~NkVMZ;<s-S5C$EhC%419gnB8W_02n4budn~c?i0IO%*
z+XB4?#`CnHzr{!rLa&h#@ZYMC@rIQKfM&*ATA{Qs4$<zam9g+VMB5mr9s{kN@rfHc
zw1e@-$EfUNERvzr#fYVqc{gJj?Ui~MRdir~n<1pU(>siZ6tup}*!CP;>t%@V!I?fr
z%zQxiGhR2MG{AUz93q2^1@TrChZxV&d^pT_`YDimjGNnGX@s$s2iHa!-nRgHpYir<
zFgV6Yc?G2h4A-4N8)qz-gvbQr0R;&s8LM`qpB^$QT48sJvEUW_0*@FDe}Om6@Ou}f
z8HSA-_8v1>L8!E4PNdML(2f~T`7icN7rOKAz??(-Wk=>JT8BC@+24cb%v?v`F+IWz
zGsC<K^HUxyxiZf-!;%~G8On1w%KT$KM2<1D=<bF)Q;-LP9!zaFz&x3&XeRJtj{J*8
zcr%~-3MC)r)jugH<IDUr3PnHWFO)>&&-{oE-~yPg1?Yr8W&uS`f|&M^@H?1!hUShC
zX8#sohcflCC>>|sZ~_Tq%4tU(&J@xS!wKfyOq3#+M`-MiWai|-r)XvijlnU@!?bLV
zWiIYO$r{IW>_TV6Gq+RBB7qsd8qOp#8))87V!np|jhUCsY!kw#6y|+O!8pbIClIC6
zOm!ASQkhBgO_4O_cdamZhB;1-rZWrZ5G8||K@-VY=2LX9K9hO+2zXgc)n{-fn>qgl
zsOMOjYv~jvml?ej-kf8m{0*2q=2|*MInRv!60Tif8vQ`>nbY)@)B@&oGrFXZSwj)e
zB4!^tab7Vqkj@w`GS8MluY_4jVa!tISG2vq#I(|q;xaS552Z4uz7BS;Fqc!-&sC=N
zBn?y7m<wrgEoU0(tou5%s}UL%OzS#eS29EB!&OzxH=abPni)jrQZ>xWpTR^e^B)TI
z)-f~bHN3$bq}#qXnTa$H)-%ukcbvwYMX}sl%$nUGjZ7cf88k7=MnRgH#a3E~w%`W>
zvz57k0#$9ym*|Y4of%(`$_}Ree28{3y=Q@RF%#;6-Oc=rK1tHUY}BJ?ZZr2J!^1nw
zXWUSEm-)XR(6nCWB}&EZV=kq+rJwm6#XSd@uhW)zkhzo6dxx0ocT?94GyUI%;ytFT
zA54re?P&uz%6y*-XYMm4^vI7fwHsmg0ke{}kK@d3lnODyobxkElgtGdfbx*}Qz_h@
zVjicM!6W9La$rs~Bk4eQhMD33^N*QrP9V0d&zqoN#}YKqYRjH=l7<fl)>68#>df+>
zIOGwQ`%A!fVXdQVL049U8jp}0D?1WsM_HFBaB__G%3IKLXT8=3gB~mm9cFm4-u(t5
zUaZ{p@YkEQMhiV3RxE9heOV#2Y4>9_=b+@za^Flh^a5B7v|<iqxzaNm#7a8@{a{uY
zy|^K)cj;12C~Kt)3?65#42EJDtA(DDaMm8m6g|OuvjqwfEZKXgjAXs@HcXskY5kxO
z#Tqc86wT_OM35MkBaLCPtd%r+#Ib&%j1_A<>+WKhPhjmWhxtTSus1-HSQW7#$*crh
z{30nV2kP}xtOKV2bDG8CLm`!Qf&Q!}jrDIPK+mw=qFr=4>v?)+GFS~9m^jP2LgC0v
z)+BAVvRLUfYi6_7e+7{omJdCoxmMO~7DUgncHse;m&e+#N9}pm`x>BKU~Q!zCZCl-
z=OqQKx${8^S>DIND`M@W;jWl9R|2$)tktxOE@8c(gNLQ8F<Km5Vm+Gz*DkXh%79YF
zI#1beS6IJLdc{?ig5L0JEbI9TKr3g}c>(4+E9_->QNenSk~S(?YiL(m#rnV>BGs&g
zG{@Djwor~|E$b^86zW(h)Xz6qH!efuCad}l@akE7`lMw8E9NJdxW$U5O-mz7vKyr)
zmX_jF&8)L)(XlP8U#)b-wUsqa`P*%*(+^;xomEWO9jx|FlsZ`>Ucl~RUDH9oo7LC`
z#XGEnCsBEqb-4nhm-Y7|sQ0nf(JG;zb^Tp<F~AB418<OZl!9JEtOfMJgke^>Bh24p
zeRBw<5mrtW&3~h;fZLF{&ua69i7^(BGC3Zw)=#7N##slNATq(4Q;k+kvh03<YY$m}
zQB-D%HSP_ON34TbGR>Q2U8#Y{3@eL5Qjb~hQPQ9-`+@=@cI?fa@X4Nin>G&)>|uAf
z=E#0oO!J=;+jbt9&g?fnMC}pwUMpl=*mZ*-uI#B_VbG1ej3$|*>=$VleT-eR5en|?
z8TwBW54MSR(Vpy<tq}2IZ=@3vZ+55(U_R`&`>6C~FPQ|GAA7}T@X4S3DJ@q6*xtM5
z<NXU{pP+?#5c@3}wu0Fo&~aV}JLW8!9m-B~MPrV$1wX=W7(0YAHpAH`Z$se(dq3S^
zj$k7~iWiSPLZO6{><yGV5yeiw4HC`%@^w_kumwIS#j-QD!KXO(B^qGj*?qg9XH8)5
zoQ8{uZ0;D$C$WE~X*8MbPInYi*js4ddy3sTgVJes-6!xVmEA_?aB1v6X-ql8UPrs=
zbawV4=w+~75J8!DmfhbCOPTChpFlE;UDpF%Hv3CTHq2qCj6yG$y_eRh=dA1sinZji
zzkD8w=h-=Q+<JliJGD2Tee+lF3fLKR`L~e0MvTfL_PQ_OZ!vofeFo<udpRWtm9TT3
z0<V<aPfNv1?30V2cZJ<H4A-u*gU$i-8vDodXhb>t&}&e*&K{)LPzBq1Z2-keww3Z&
zs@R{>C4p*oOe_>@*eCm;QOllW1GJ9aPw(#y_U&sZ-DJB^GHE?~8QlPAU>DM=@)rB0
z3Gf=(4Eh8{6Z>)%I-!~U0=*S2?BTyaTG_o67jI)fVFYPsJ6etKyMz6~(=gb{J{t~=
zE_M|y_Pg2lcYxQ!UVj+8+iVdv`wlyeQUmU?duw67mu;Pdr9O7=vry<~kFJ5g1MFEP
zKpAA~e*$la&7kpdn9ZsK%00H{VvrH`>|&sdvg2Q-L;3q`{MQ;@Ja%LpOgvySH$!8b
zZTS;26Kvg9piQ!O4@2Z3+mTk-Q|$4@(0jzbMGxCF+m4b5X4n@fAo!U5%<rhQ<qUd2
z!H(l{4+{32*|Sh`;B2D!vLol$c&IyZ=2p_B2xrdjI%pi>d}jwy7fuDmv|Kp@zk;}N
zo}-M4qa1rZOdR7BmP5pyqoJwYgY*2$sPyDW>1Xod%%NilZ%*`4Sn}a4b^-C_<WrQ~
zkK?=%o$t>%MAx+fI8|*>59D~gL?7J@;uOzDF_>ddx35AtzO-ry<#21!3CB58PXH#2
z<4#FH;hZ07OgO>$=TDFbPL&P{k(}oiK;$In#Xgvi;^?N~VKm3I4E-F#*^>fZEa!G0
zcyS!Nognd?%M=Ss;9M1fXHDj;JcrIm;SABi(kad_6puO0Sxk}BRF2y+@X|OUx)gDS
zvypOv(mCNTfn;!S(+{s2Cyy2%nH&}u*jb#sgWzRzURs7y4o4(M=jC!30T4OI>HiK*
z%Hwo91M@s5<rP@CVCAg40*CWCyF8#+z&T56m_p9!ZeSO26qI*U%;~1PAQw5aDQBvL
z^X?ZYm2ygc2ihgh3OW3}%rQ&?w2Y(RL;VV;RRGDWoHs&X;u>cqB}SBUE-ivH*E#JA
zp;y7NpN3u~$NC}-TUDIuFVJ7roW2Rv)^Li9aHf{i^$JKG=Z7Uwyumq4)5=YbIt}{u
zoCUGaYv3rjFnEiTOre5C&dwjv&?e5TP2e?izNajw7ETJ?Id0|L3qh%kvwbs4?VNHt
z<L=;Wuu>v&Cr9iBjV_L-D-3pXZoChNdpOEYVBh8(p^d>EPAIKG?sDQNoZ8FT(F;p`
zoZb#d_H)LgpgzE1EClEv$Kx%OhByO@p+3y%*?`hLP9KHmM>u^Op)ksMX#v#lbM_vi
z_2(FeL1WSb&e3{U8s}uu7&^hpNP_+(2VqIPcpOhU_n6`+D6IL2(?;8|X--EC49;-8
z8lnD}6HF%-w%jWWpxANWrUk1#S8y1;=D_vOhKM8gA1{=gxL>SAtDU*?#^_IXj&S$<
zj-m@UjD|~BZaqc&+_*Qpp?{RSk0t^S?$XC-g(sIY1D+Rmi$7qzxj%jYJs+-tmQKFh
zD-;s*<NBpR!JjL90saPX^P_+g$o-bKTtVE0ad0h|`#l}Xhj2e`r}r<E`{^%0JI+m*
z1+*}3(wl$@=e|v`&J)}qiit&V-6@b6$&IG1_(|@P4^fKZzF7plXzpvr02;$>p;&Y*
z_aLn^;<)Bf@Z!0F6pK#aF4+gLL~apn#gn*IM`0+L8{i2PYYNvWhl{7U%2n|DG}n*P
z&{DbIP@Yg4*LxbgGh7S3hUr}2OVH2YmIML&EO#S~TAAECzOb9c-Tetbv$_A9fk+N_
zIi=R*a$lwQ;2f7rm3iFEB3L-jJxM1P7r3hq!BD=H>%S81E#TVHGgru+&4FSOS3%c2
zi@9qzpz<QOfvy#la92@Wp_KdXQ~2#Kac8>%^fLEl8j#Dl1EKKn3b)M#3Rk(&M^U=Q
z4X4;_Ik)g7R9@$*=*X;sTl5HemE3SDRdKDJJ<zY_^78Qm)o}Mjz-}$qDuqlPSC#{r
z8{DU9*t*GG?+KB5?j8zgHE^q*MPqJp<#egGk^Av!NH%d*bg8eI`#~W@TDW`ZFu#?%
z>32xBaep%brJb9!2Cj8*<7f}v$$ih-1^q7WJ615exxd_ji5_kZohIJqy3z%pJKRz-
zc$d5QEr|4T^FN13A2<9TRQ7YX(=0x~jT?m9!`ys2AiBpL_-~Hm{y`l(%Kcgd^Y^(W
z6n`1xW;Q|n0XL7b(8jq}x6^z-!979|(n;=(Dv*cVW3;xN;>LNx;3Mu8IYg$pW(Sy<
z;U1*)o5$ReV-T_Bi4OwQj`#D6XoNj)O*DuDkMS(@9C@?pSip%l@EjDJd8TFf(T?zX
zaSvgh3r|RaW>?;KqjcKk#_Og~?onO|1xb$aULOW==kaMp<H4(@z`7^z6?*2pcu^E`
z^X6&jBDfEa_dfjf<%N6#Nk86gPgwHj&82+e0NyK<`4!0fq62zCJl5;r1@kgG(UuV2
zB`rikd3?Ou_(BWsV`@_vuS5kB&U2tO^$FfjGz3TRK9s;<B+u{(cqe&9qfm_E{Z6S@
z(Y#d`Kw@~;Xrhnhy+NZ^9Pd{;sgLIsQ<D;Sk(6$b$ZP){9wzZ>X;w<+EmeY~@J>)D
z)_RJ!hn|SjylFZ*Nag)VGkh9v!$Ej)hW929rF7nII(W?BDcSJiEbre}VK<W}tAu_Q
zFR>byvU$xEGR)y=b?_pWmrrL6=XlAd(Fu9HSNVWG&)X(}$OWF|Bk=NhskEgnknnm&
zz%1nbNneUA;>DFgznB+r5-wikjTQsDg!iNGbG9#7pF9Y`GM?xKkSn~v4*+(RH>VZy
z*Le14Q7Y&Coe0e9JmW`DtKe<^4Wycvp8!8=cqJQPpq97#1lmx?)5k;a2G5)Jus3<1
zoC2?&=R@J-2A*gW$SvM8v^8twm8GK#nt0c&l<3{eV~)d83-2QethVyb_`^gSulav)
zx1AUN3a~qP-~M;&k=IJ;AYHr#$Dr5ETO0<F9^S58=-uX}M5FQ!ZxhAT@A6jBvZ$9Q
zxCn!Nyp}-l`gxOl_%y(4qx-9aJjp4#J~YI;a}^rHyy|`M;vSDhr@bS*e|`XOl=qmj
zG4JzQ=s_6cwLJy22fRc3fHux6aYt!_w>%f6NnU#a^d9m;{zOBkcpp;O^bwEs9{io=
zg&Y8Hh9{#q!eidPp8;mepIt|vr?unT^uvTb|4%!hIq=_X#ZTeLAOA07i$DDvym03K
zxda+V_y)@8ap6a1pxLf`yZZoj<3CS1Wk>n`&EOs5KTk_|cm66$4DjGDsDpV=eh6)^
zz4&)MLA?1l_k!ocKZx6?h*a`lEkV(bZ&M84{Q2Mh0%rpFUol`Jkbia*=7ab?&fo>}
zAJPYdLim-mItt}`eGT4mel>-Q!uVMUuoTXJKMs;7`1@#o9KqKa@FYa?-{}M9Nxlb#
zo}>5=XqOPp4;+GsHHOcophzr#6D`H#_!e5g#q)Xe8YS?@jUb79Ieiu(iGP!>t|arv
z=uTh?e=RlU6n~f!uTJxo6!K2x@1~t;8h?_)Od0&U^f8FD{8y`>m&vc24UsH<^P5o5
z=6~%6UXGRjfL^g&{?`<9JI6mz1!f-q)*m3}`CK(R_yT_>7`%M`nOcAr@Q0G2P{`j;
z5#1ubV+I;i%unHfT;ylamcN9bL)nz2{4v^DUgG~Cg!#*SkpZPL{&X&QSNJct!I`Uk
z>vy!RxyIj3yXA7et3R06`JwSBRq)q;hEgRzm-d@g{1DoUR`V}VLQxIBpT5Ib%kL5c
zrjCDjCCuO857Hxllb_}a$$I`b3xU$W-$irbE&eBz64S`{qPMAuucfd3HS=G$((1W|
z|GYig+sc2RuA{c`3n*gI&M%6G!yWt|C>6Go-~0~Hy7&cjF|wP#!WDWw{5NTzd7JMT
z0_;0{S2`ZK%fBpxLN9;(0y?OVKdJ+-pTC~=nFIVAhrk=;YgfR+5Wj&>Gu1HPkKXiq
z{B5tp(-FR-H^?ae#go9k&ySZwag5()1Ca;(HoD$C&fi%COA~xUC$J~^BFZp($md=L
znc|x$dF~N^@oJc#=J!&tY=%E)1KRtT|I>VwYz4amfoUiBn70V;pS_@%j!hf{EIkw*
z1!WXAbrM+U9;&mT;&rt5h~O|?$8iz7Pn#T9!P=L>a}!*PMRy$)?0pY<#{@r6wuHNY
z{RO~01Vyy-@DzMa=Nw*wPtQZdTksogMSTQ8&%g^`f#y#-6AKV*K9AZ!K`M>CL4u2v
zg%d1zZz)WK2-a|b7Ai=&4*lbTcW5yhCa`RS-Ee`U7_B%VsPO=a5NKKOFj63R9bhK~
za>}oZ5}d0=DOzxkw%##<cish9tbpMM=s3aG6r;1o3+lpwogi3x5;BPb<#NCz3EUju
zezKta0Gvq?#8Ym~DZxYoc&7!aw2n#@w9pDQO~AMYm@|T@Hu#h-NTW+k83N@dwD7DT
z&Ka1Qg3Q05kR|xA7nRupiwLD0!N(>*=UN4~-hlo&!9Fdp^8`&4e>^Yfqqq5j;5Dku
z7yNb#iUk7g2+#@z5tP<jB(VDiykbGpdboB`&_}Vl62Z!a@S;>OhmH>}2|_5Z>9XL7
zVpu8@9H(&46~U@#xP4XdH-)~g39M<`p;0b)=|}X}b-@PutZ9W{{18l33bxR4tV*!#
zSBO>%o}qM<8bP2F{H+x*8{ku&;N%<N-4IA<1$0xen5Ox9!BJWmGzdm7!R{@=Tsk6d
z6x3e<bd%sqy4Bq*m`l5o7QtIq3fZ>`+^S%y4Sxp*yX}HC2SGXn5leyHDL8;E`*~f0
zC!PUlx1fuT!+HeObo_i<koOoccLcSrAa@0guL7l4P?-nU`UIVa0o^aK{|9;lg0XJ!
z1_jx6&>IpYQD|gX@M7z`khv$g9*f!$!Oz%y&l?q_K7{%Eg8B?JW=v3~MQK9tJ}oRJ
z1wStV_CrA%7nM_jLP}0~B&eibn-(1P-R1IvwIB@k?1VQPA#X1{lnM|B;a@bmItok5
zV8BUutpvU}3t7*h(~bz`l)&dA-1Fb7CEQApO*i4cbU=4hn7AD%$AnD|sB{-*mqF4)
zm`9Vor*PIdh?g*r2@!9hZ7VGJ2wSa`72+%0NCUW^@WtO@&|f%r8%hDfh3DXPpwKc7
zjUeG?jo<|fAJ9@DMEEtuze9yD9DvAiVF#reh6z0=gDG6-M@c&;goU&&h!9GChHH^R
z_qotJDU6e&6eawIo{?zbf^-VA#t4tmFcm8dqToQBa64r{#S3>Z(cT2%3Hr$sh56%X
zOp>r~JxnAEf2A)yrU);N!o(@zI?C-jEwrU|L8>s5#>_O~eieG{jPR9lK&K0zq0i}L
z2>->`X6Kz1zE6Men<-=^(S67)q4q=QXA8H}ek(^<j}wu3xk63^%%2mkJ_N-);j;_j
z(|O^+wGg==%(H>rd|`neomU`Sdk+Q+g(L3*yGZEIg~4Lss0b(*g~MM%uS961+@Dfm
zHU+mX2|0bhyewRRJrTYKAbjN{idTeR4Z@47!XF~w_ch^KT9=dyPvisix^Nr)Oclak
z=p?gJ_<aq~s)QqnK&uwoIYO^Sm`h>dTH!NwP^c5Sj6vjv@SkAtZVGo6!QWfLFKD)I
z6rON~WRtLJ8YOG9u*n86Ekb1kWLkxb6)3d{1@8f-UFb^pb~=O$X?W`tI-G$QT|&_o
zNOlW7X|U@N_R~CjTj)hydPgXt^Xj|8)Pvyl3ZIOFLZ5I=Gy0-mxOX*p1Hw1Ifx@70
zj{&?PtI#bN{X8t3LpO`=3E%wyPK^i`QMhJQxR1un`@&Ci!5b4Q)}i!3sN+FoT)3Wg
z?i0cnen59k3b$_o=tJR{JwT^~cPMG}kx<YCgVVxHx{@~|{E%k9$3o|3sN0I}P@vCF
zWbIiBroG4^4QLLcss_L~iiDJ9;3S%+Y13I`SqKwHM7t=u<sxF#Lcvwkmje+u(Hj&=
zIx2FaXz4ML9UZB=i<Z$N>ml+ILc~*KSq+0;qVMQRp10^e&6+-<q;8n^6*XBu0re9N
zQNZ0_bdD}t1&AJOfkvRHn{Gq|iMnQh7A#`XFB&2ejKET;XiF+e$3+X@g~2e<O}d^D
zF3O`!trH^OWvGl0)h_{9r0CXbD4i7Trco+Nbl^HLqeYSJFdHNK_+who$BJ_319WjB
zjW2pAUUcezKuZugzXo2SXdaD{Nuot`UXU!RGr^e@(Z55mbV{`EYm`ol#>XL&D(a>n
zVwx!29+u9CHj``Vq9_`6GDJR3P&g|(@DnOCMGO81FS112>uEusEfT*2OF5z?lq-=Z
z@=SuI^P=aM0p@~e^l$i-FZ!Im09PPd*AAFM(HG4iMItMmr5B3~!SMH@$VBsHiD<|T
zV5OqV^vqonS?Mm_Wzo}zK*~ff_n_HVL?0=kepM93T7>uSn&?ByMk*K0rs&6Y(ccvQ
zs}L<<!_!KUAPFX_L~pjj;cAhs0E#stq$A)}6NzYzRVUg>2`V>4)iki)6diGg_w}N!
zG0<xemD$3zTOxly@ES#juYuPjVh;kPS!B2fp0!1^l2Y+nMTu7-(<U0Dm14Un@W1bI
zhz4l%=@bo8az&S@S_RTA@}T`hk7xt!Qg4e~C|~4`Xf~~!?uwdEz|mgO>EBV=CwiN*
z3;RV<igON#)&!yx21VP>!|ssC`#BgIwu+AY0>yixAo^Ixh{!h;*rOsR8d~m)Ze*b}
zCi>|~bp8X;56?nzT=XYxu_i=cYQdWnNfJ<cC>p*7-jryFG6)}uV%2baTJ-iJ@Mc7B
zZUpbKNMk{F*^1fpNh3S)NxG3_FSa5|gcnb|&;?9K@f&)$=p<f#9mH82_}^ku{D8(H
z7x9Ob0`4lFOEa^ZxSdjPj*8Qwp?6ID{C=2l7k^71V)PJu)2!qvuCjo5i4$lH^cKJ5
z0udka?=QiwulRKnB>lwmt#o7CUz~acXaV9cRInQ;esU6i2Z^_9pcpKkY(iy-xFiLo
zQ1PP%D1?g-JpjxJ@%cLFMTm``gBK|dqbu|$#d9cl872N^4fLYLqm*nLBUXNd%2;ty
zFht_SmF2JyFE($tf|(%pqvY2_@rfFglEn8U@HAQc8WS$2h~K7V+$r(W7L-nlKcl~F
zNEN%%elJZNvjs3`#D^%rk}fWwz(a<ZOUEl`#fvD!mnoh{vv8JpPAj0Z#bNXv>>RQ1
zTaaAwFCw~+bxxcyAEJ5UBea1zFHWO9`vr0SbI`~aGbx&0AkGd%3k${H(Js44{6Zk?
z7K_v8K;)wM;|l1Ni0{%8uT*^FFL-}R%%e5dW$}vt;w56%Vdz~Ezqtcla#g&WayhSw
zd*;!7$Z~PgY`Az`{2ApcRfwOjM|&&90Rzye5-&Xl6V>8h`@pLam!5?)wc@50w6IRR
znvQ&Kh;J_i@21#p9=xa*=lu<^25}D!y0^qDrcv1_wq1<MCULd`J~fLE(h|HyeEoYs
zTU*8N(>A+JT;2<`c5xj!+#%i`1N~0%yA*8d5;L7)w_AMhGmswfFkOhcEe=YC{vEO8
z3AE|1c<n6c^@<yIK%q~pr|#|-Z}<$*17hcX@CL=IkI=FqvFiX7hQ<9JsJv$tCkB9y
zh+Ch6#;BM-8yfe;Pws_@F|ptakO$(IC_8vu{4Wb0PKY<t!!{}2JAulF;+K!Wrz!Ck
z9Z(*L=h8?#Ev~IWrLE*Rg(&PK>ATQD_L6)bn0Ju;+XCV!8KpdYCy6zYcAw6Y`-jm(
zM<gsgo+KBED{VwvB@5|_x0_@i3kHu$I>(`LOroVdth<EU4h0WM?@?Itltk0=%1g3#
z2lTupn~EUmBeBp5%2zT?Aw@q){aiTXFPR>Ny#PtqH$VxL<XS(6Vvxk1;$p#)ZxdiC
zL~`_fXoN~uQf%b7#JvMBVUlS&*$bDPrc=KYlDF5P^%0T)+GR&dHc^(rNl6NYbfP3@
zsk@^k%5MQ3BbmDalCctg3^3y){+m#Wmn@-$V}j)AN;>*Xlq{zOeUc=!1k7Z~M-=o*
zk<6!I>y(5~r-r8`8>vfEB|ip(mnLzXh0+<x0y@r3m#jDkk|B9%H@rA2$);_6rX;o>
zl35bvD%j1IBy9t9j^w>$=;cbDDS*N`$&R-u$uv*0Arj`#OB5fY_JU;pK6GNfWbIYJ
z6i7DR1+P$2Nl#Ld<Vz7qv84Gv$VExm6wpc}VP~ONDtYEQEM1Z$(=Pk6L|g-uGRbFG
zP`V;{e<#4MO5XkmVAmvTcAzWECD8{d_3pal-D)USNOsbdj7mvrFZ`~O?4S=~R7-wX
z4aFMCTh36dm1MpOv^t597IHTv0rUjll(f)4Db!2&>j2syd8;1^w<OE10jyDS_Zw6;
zNp8|C+$?!g3X~Q}S{`_<lFy!iq_sm*N_*H&$sSs@bV-Vy0cf{mfX+pGByPSCy)ChZ
zgLg;b<qb#gO5(l)>6KV1X|zw0-wv35$sjG82PDtl1#eKYfFd(Pl5<}`WLOeR_k8Y2
zVrk(yA_-XrFGeL>H-Ox?N>qD5$0RpWVeo-Onh7#4>7ox_PDoUAF=<jFVnF1f<Oc~#
zQ<Bls5P2k7ErE$?N$#uga7OZouDw2%1Uw0ztu&Gj2JNJ_1<<pXYP(SBAbtHGlpLk;
zY$!NM>)wHav((zM6TTghO7tkYNWY-{iL11W#%?!hqXzCDl{(&l$T8_hEb!c=_h}mS
zkZvA>h^O?Wk3hVn{**NBEo~G*!AH7^zS`m|t)n~@Kk0jPSJGcv`W5s7r0p>f36xgd
zghG&XuGIzl!O{tuMnj}bIxh&7cF^YVxKuzZ)-dVV)8K_mhkpX-38{xaDkG%(zlTqe
z(k*`Aos|AbYk?@Kf_B-_(gPITj*&XiD;_JoUW$H-lfK^x$$06a70^qNCN0Hpo+zEt
z(~(b-G@VY*lcioQASu%IbVK!&^j8XKotCC}p_D3ZoP^(L(tjw9eny(`1KN}>y+%in
z8PauU0D4yH*#VJEX?+j8$dYbw054nW>kX6~>BDD1a;0%g;mkSdkF<--lMc+KqtElw
z!<T?|L2975R=)HsonIA5o#_rop_KU+U@l5$QN~7z^ovlKD3z*)KrTshTH*a=X%T%u
zr%d`?8$ho}SMC7HRq6AK;L|l}>MoFSspBb_zb<{7(gP}_-tR-bQo42??f<Hz`FCNW
zT53a2V2$)Gy6apkeK{I1byCNdp>ad{Z5mA6l-{8K!>X5RcxXj~H1sK8-;(-LB&$&x
z^9MX^l78_9O3hN!m(XjG*3rw+D*ez7yf*1odVt%dZR4oykXG~Y8(2G~Jx{}6mz4h<
zYP+Qu=qo5a(hoyHZc7EUs=Oo3Y6H0|72gKwm3~5lXP<O{mPh?kuOCo3AXR$7!$E1)
z2LKzAF5-g>OW&uJ>OJY`T#ymzruh&VmA*(RCHJL@n@}IKO1qcCsRz;pUFef>>G#`#
zHX(JVCGw<n77dpVrN?RAJ0-ny2^x>2<1{x;ORKlR-x;aRA1FPR?%EAWTiNtRVB5*o
zK95R!*=2hF9AxL{D9=&$KblUQWRAbVkh9E0X$41QRvQ=mYA&)kE)-p5T_3})n=HQ<
zqDN(SD^WToTSW)X?y}B*f#xCmmX^kzvH;pCddXgAqZ7SlZ&L)pNA@EH%Y0>Z<G}Qj
zeNU+{{xTEIh5@qg#y|pPznq4lAlddd{35}!XRMO|4UsXvheoKZnHK-YWgC`3G)(qj
z7G%O@reh!{WIc3`BSJQ`3qD24me<1kNtqv=iABkl)WfG(*-<B;#L2d=hKYFDl0HBu
z$Tm&`EK&B$dvGR6X7+_hvaE*=-&16YjTBHmCA*dfjnlI51Zbqnj;Fyyn#_y#@MmOU
zvmlZ#OQBTz3|TrYanH)$qNy%Z){_gEELlB8F0y60hrr8`?WD+Eu59omc;{sQ>jYSy
zY#$w6o|lc&L~ub?N=v<bnNCdaUxCb>2lIt8sXIuKY>5(H6w7vn0qvqJvL0TP$ljog
z?o!zobo=F!?7L?0F3X;w?AkKf-jzVRBC|_{!K<=w=?A?g`*92k<uYS4O4nsMv{bB+
z;r|x!;>lj5FO^iuF5x$~&a0NK{2VehvP?R#u9Y34d+v3zmKQ*7$lP84@1|^aA>6N*
z1=XUV4YH;+uyjl2WD8!S>_s+8O|qN@h&0RITm_UC*&uCXT4lE=t)NZjC`OaoWoIao
z)*;)<fft>!<ZOsoyJRiLVX0eYPuqna+0qZ8e_OVH8)WXtm|vlxcV(S)rqC-Zqa|OT
zY~HId*e@%fUCw~)5Y7IBvgmK&%#f^n47_34cZXp2p6uCpkP%t(E|5{#d0JxLmpykM
zWK5P!pFw_Ll{L~UGcFUKK+jIdwmJiCQuZl*MDU?(x)82S$<{rD{v%leePLx<7Eu68
zGqRR<K_1HlTTy8%-$SW8cJgoJP_UQlX<T-Y??=YhJV&{9Er^r+z)kR6<cajHR9ATu
zopZa%tzW%^+N1K{DfRW3d^LsR-Q~LND0#>q-a!jJ<s0bf_L8@lVZvKJI06wL`Q0-p
z`O3vl1I<s~O6fWN^6Vsl2FN$3!rwr7RSfik<g?SE5G>#FGb%&m3yXjmD*x$skmK?b
z)<w_=lh<YfEnNP!5Kqzx`B(IBbP@6~+EGNx_Y2_6N%_o|(1?<6+zN$gc^6$ujgenk
z4ZE>&w>>Du$)#+R;^pu3LN7u7D&_bl%9qSV>yzXwl2A&P&+39tDe~uT0P~bQU=Dqc
z<Fq_&4h*Ks+v%23n*0-rH=U7hiiTpkd<~@lWXPTAp!=*mkYbIQ@*Yau$dWIA0JLm*
z<uWMb$m@5Zlq-LQZVjH3Z=iKtp8U%bD4mzTln#*#a({}C<;y*2o-e=;L+j5%xrT?@
zBKhno=oia>qG$c0oJV1a68VXhP%M?-rY+_r`DqHVUY2)pLCWOMoCfw4dBXD$xhn6Y
z#s4+=vIB6fT)y~6fL)ibx&dB=-1k+KD&=b*qw}id|8}9fs^zLpbf8lsUqjLLTKPQs
z=zX1hdM>)=hJ5TNn7Apgr08+IJntej8sy65FnCLz{3)8&D377T+9tV_rr2gV>i|kE
z@((LPTICn*K-%PLdh*-l!?YymkY_mox>FuLhRQB^Al-wqcFS{<V7^Cwfr3!C<ss{V
z)+;weLZ(liPzsrT`RW|l9gr`02~8W6k4w>*A^DPf&>NO_eFN-!@=xewaYU}8z2&HU
zMLyK;%U32qZ%jT-$&e4^{zCA^<p)*)WkQ}UK+jBC<+oo!vmeTTqlM9wJh=z8kL2Hm
z0ee~=@g*u}<oDyyn8)(MDR^kB*iLZ)JB613diIJadVL)fb+j&WR1DK#?W8ys0R?Bp
zd0H18QB<UZ=c35l2~1ao(?t+B#htIgJF2iI=D_`9iVrEZ(p}*-A0|8$sW0Q#_Eh*7
zVZuvsEFWmz3Qx*U@KG$MbADgN8%}7GpJE#wHTx^ds-PaA$e<5V1uA5#L4p*|u19-=
z6;HIo!w|(vN>L0|%%@fVam5B&DuyW();^$xD-6Gac|vhp3YZAR$~a(0Dt2^0|D+;b
zh{`BMK?Pu<6?<q;8l!lPmN~JCJ(plUPO<zcpv5ajD7=uM*pdfcqGBt(97&4T=uJ&l
z=w5|Lief9peNHLPg~RM=#m;Vuf2Jy0PJ)@HSUv^pGm5{JXlS~Ep8=Ag_>lZQtJq74
z37LuqbUi9d@yHd}*@_#Kf|H{tT?-SribxLB&nZ0CLm^LbZ4{k%UJ>31?=L8NXnmir
zScycwc?F6Kv`#2gr0eK=R7HxUI5<_T_<9YnFDkCk6~Ge3AM`D<QbjcFjxH%azX}g8
zE947-R;DP*MCqC$a}G-7im7G5zOHy>ITR`seP6<SrQ-7{pj0WU-hjbsMJnADsZm^_
zt2MQXINCzgDfT`|@s}Hl^9sn^RAjURtzNO=do-;<(V&IKErsPeDjOBMx52e0#j(}k
zH7g!d>RpS%i9V^+s`!}&(x%u%e~#X+Fwpk}I}~d}f!V3h6~a=NBI5<<bt_V6pWCBo
zp^T5)idecJZ@r_~c?!(CitoA5=vBl$3(}{!<^s~M@XSTi1{8&~H62uxKLXm2LQeUT
z!-^^jJ={|yP_SS`@du@fj4Ga_QR}{9C>PjcivC`d9w?Ltpf|4gI|5xYq3C@Uyh%kP
z#o8ZQ6|p2Ur7%=L=8<C22w<iaPTPPzqp<q|{q<O}>KHU^l?4>ku~RNn!!>*5d0MVJ
zD4({2hmOk4G%GnN>uAyAtjwlFiX+NX|H5q-<;;CRyDF!VKQhlvxp@n`II2A2hte^n
zb;=j|?n(zrRrFB0J`Lij9GC?(FXgN>Sn^heQeuLSa)@@CzRCh>jGt0Zqn5uih9a~9
z%B53K2vpvm00~k$2ZIDF4_1N~q8z2wRjBg0MyMZGKIsl#m~z`acoD9A)k@i$CzLyd
zU`8kvi_p+WC2ti>oK!x48=_IlTq!I?E6@J}5~G|=A-Gtj(1KozQ$AG)k$7c;4ki+m
zT8ix?Dr@SXo}^5n%Pr~3p=eZQD0fAoooAJ$lvA9el&(TI=PElTwEjG&^b7}RzVa&y
zaug`NC=07lY4C!HtIExkJzcI`=L3=JN-LczR49+q(_N{2kA9yj<?&HqS1SvCg+h(8
zMu$?ZvUdqcopLS()NU%T?to;yvZMeFY*5anN%59)Fpth38kOIzz@yuw+{%Gyi*m^&
zSZY;f-9nq%lxr`dgW8o>Y3tLW{DMvux|BU*knC0-{uW;JD7RAL?`@^eYf!kOtVo0U
zUFApAdA-W1cqsHMGiY2MP(J=I5UBjP2D~BV99+J)&Kp)H)5+>RW#@J1k0>W-F+HkG
zrYGsX@`-Zr#*}+%QF@^KhbDq?rSMOnO(+}X@M%(MOAF<P%B+njJyMQQ$Z%S@f(}?`
zlqm){`dC>r3m)34e%cHaJJnJOL^!B2TTr>&QI$Y@S|?Q}treYBH)-v3M5Xkth-Fy=
zUPQ;Zt5$ppNe`8-4Td~bZ4|!oR&~;8fRAd$2rzwBvCaVTQyr!xC4W`i7)XF>9pzpJ
ztCnm8WQb}v?Jh!9_4LFYSA7u=UYP2sT7ZSCY-sL}RQ+-ZZ8)iVcMC+KR4LYNsEt*L
zx1bSms-Is0GhVeP7$iyc;|L5UtJVj?e2VIO3OA*y+UPD$n(8mwKb=v%Pe~|eRaS~%
zXR3;(A(Ev!@D@tBDh}O7Ij7ni0-y3!!UTZjs}4}4zd+?od5(oDM>ZW!7pdN)cu%p)
ziPkO`RSNpeFR2t~QF&SAGJ#T=>T(%)S5&=qz`m*~w}<{UmD|T~yFz88bfijE{0K;u
z>i2pWtX8dm8RlzL-lxzrwW?>oLg}W8vlP5~)zfm2231r6-HT{a&6fkMS*4#16D_Kr
zC^@5DHACNW=}?&|EYPXCKxgt@s+CXBQ>kj$jfVE9UZ&Y|P_=moc865K!*Fd_RY7gJ
zr}~6Oq!CpJedu*mRrowwe_s{-5DH_eeYM~{P_=HIg@<!owfGKXCR7JMfZa*eyY`TI
zsLH4H(3HwTLApn(|512)S`|XcXEUm;hd>^yj=G`JR^1i^Y&-SWe0XTD?x1yrgZi1n
z0CQ9axkAKA9r+M#aaNaogvul8L5g>}sE@COA*-u;)xTi6slO`2yKz)KpSIG+)T~D^
z@2)P*0k(&FC7JM4-}wxV`lt)(WYbsuk1a&})X&YJG5+d3mq7y5o1O;=RKG=MRY7XO
zPcRs)enkhLLewA8@-Ixif%Z?~>L2!joUp1hX|WWc{+bTZBGo<bL;s}uhkAGsrS5Kn
zrD$~#CAP(=3+Nq*RfnuaWt@69r54Al`{>$Cg8Jpz;3ca6mw+E8NnK9UW{TRDvQtl~
zSJ742(`uVOD5R<{(cQZ=^}`Z~oKagZP{8!8dTBmjGS%_#LMBU{77v(g_1cZ#<*2`+
z)8Sn8{T7tYsptL;5A)P&T4J78AL>JwTu^i9xyV<4^94wOn*Rp6t5CgsBTN*j4<AFv
z7OTrHfRw0x>8$Cp`nnjHW$F*CgMhiBeyIkaSK%o%uBkI8P%2l?FNel;^^Y$Cv_fs5
z&zV-L9X|xAQoGQiu3B9)2R_xP&(LnUR=tN#v+LAXazJjVfBz1>)&RHR%q=ye6kv_&
zbrg(jQt#5j?Pm394Q-Cv)OEBRYgb!oPVG?7p|wk=IwTSLUFy=6FyF0y?L&z4sMT{o
zZmU;#piA$lFVl|cuKEdz#rCSde+t-r>XmGees$GSpbV(j&_Ft<Ua$p~_tf8PfHU{i
z-~G2}SNF$La>xVq3!Pw&tJlnf#)SG?TlCPR`oRBCdZ;e518+*bgKlL#QrA&t!L&N|
zH<+JM_dSWyV|5xW!0a`Vt{@JYAL?MxQIkTc6HXeBpCIC_@u5@NBbt|J6X>Gpr#pYH
zn#d^nSelzAn?|prn%!#wdQ3C<7fSA$>KoAa(qvK0&09138vORrC@4w8SHq*^LO;zS
zN@MibR8kluNYnWq>;`N0)9f3fvA6&wRI}3r_2Zhw^f9_HO*!>igr<*T43U~)$_lie
z)PygDi&2_YbubvMNuG;Rj7CkD=wda#>!BZ~>3J0z@tRk@hDL&>lk(paHCMCH-Xsl^
zZZf26e)|+68JdR_S3avbK#})MO?w1*S(?;jfMsh+n*g1odHOE&ay3&k5IJYny!j3M
z&ePOW3f_6mE50BXG+dhQ^EEEDC>3bj1yC&1Owp52q<K3IXvLaJIwQNN>7qz<iN^m7
zDoZsrH1uE6tf4^XWlhVEuvDfgD~4-VG}~!(zpBac0_HW%aeqjbYpngtK(A}O?9sFe
zO?x6hD>bKSeNd(89|Eb?e6|@TYBU{`HdCwF8iCf=Y5x2Yr5l<uN>jM0sdy9E^_nMt
zK${vgd+T8SmS&J1%SO$!6tQp8eCH35W{o@rdM%p2X_#!)oVThV)20zqNU2>T34x^!
z&8u_~s#9}@0xn&e1lsp?YhIwkq8?3o4h-JboOv3&JDQc0@^M#lv>uhcngeu`p-;25
z87BHQHI7gi&@B5NJ`HN#ehsA|%{+>_4r_L|L*$-j<Yz1Fj%c2l1R2%rqKNW+P2;D~
z7}MNgz~Kj)PfE~V<C-;;4K|^Pd;~J7$z6iVhZ+w$v7XkjXk9;}F~5w4KGyt}4xYW%
zO5>D+_J9H<N9}$ch?6#c3EJYUeXA7SAJNXwS?K%O>4jDg3u@i8XWgK2RNE^7^O!c|
zPoTMLSN#kV9@@LNQ1a9k(IVDMdz4n8-r9GML%~P;#BA_<wXQS>`Dy3<jfMtlkI+GT
zkoF424}-O@Zh}IH_LEvT8mjHffraB*%K+5Fw1rj~YQwcxeIau~n|&R%5!&A=z7?sh
z{19j-wfY$FqO?JD02ZxXMduYU+EZ_U7psk;C2gGc;R=8zYVS~fX_B^|)}+bW6dLnW
zv~FLb5vQ~*3!rdX`@sq{B2}BP29jyo6F<`$<cu~m6f)`BpJ>yNp|xKQ{j=JTLnvix
z+vze)mexgqhGuKS=fP5rmO-}<a<!GzrRTJ#C=Q>eUE2ig^IDG&pngFc>kfbOwXHOZ
z7HDfHz$?`5rh8vS+M8w2E7ltO=x+2yEi(umRibU78NO8e)4woyN!v|vm&@7%5r8Sv
z<|n}J7472f(7&qvJ`?7zY2T)c_~lyOWt6UKuc)9<p*^1m^-8S^Wg1s$6BD6Vt=&WS
zylb>;7eKOB%b+ZyI_+oJ?_q<gtu?^zO|AM(kb3O~ivBccuh5S8mUik-7;MyTpFj(n
zwAo95)~ww|XCW=xMHGB$)iR%i7j4=eHbC38?i5Gp&~}|hCv<8ZC^p%pokiQtZtdnD
z@f+OHuBW8lyIQwqSg`hLuh59vryYA6#eQu?AW8$;wpn-$2etXMS|8FnQ5N&CHg5&c
z?rGg<B{ia5m<5<ot?gQ1-`7sZLT^m_6a~v3XlIAQ!*T86<ItPXCedNur1ps>c>hp)
zfNp9|Y18hb^vJ4RWrp2pZOJHPX0#8E0Q<4lfi8sD>Xx1csGV+`H|*N$CI?aJpxdzr
z1|4-q%Cd0M^-@-qvo5(4phtA84#BRAZsZN{Ty@D0Vct#Geh$z_b@zS&Ii~yKJ1Ds8
z!qx!OLucLkBg}j1zNO8Tm+m{t5%$&<?}S|+oud&yg|F_lZdCf|q$i;0uZy-pWq|Gx
z1zZAk*T05|ART8227`6pbYKvo`|s0Ip}O&YR36urT?BNPu9;Gg!gZ_;kQ2J?-@|-_
zZikg_TSV$azk;0987NaZN_UY$4zarV9WW86yG(CIypGiZ>;zr@K9mx5>$MO`(k-Mj
zvSi)dzag2Td*=u|Jf$n&1eDXdhyqBa>Xy@0*fgCR4diEZHg`~&u3JH|-wd6`Kmnq&
zy7zaYOEYyB{y=S(Zu47ceYS4yFK{tO_aYq;<m#4D&z{r$@&UZa)78<n(epZ|LFir3
zanHeSzHXWpVg<U1-{4cBZtF!z7U{mF1M_0tW?D~O)ctJ&uSC~$6P2a9*wO#~Fh>_l
z`2v@9TR(%rGTnMgFu0<7lg>h}>e5%k?loN;?d!{R$7m$KuA4;%^%c4ZJCrJQUM7fC
z=_Wf+s@5g_4ZAhEc0GKm)eYI8vQBr42XaIAfWi<rbtz||P_Ij=rvOod?!{ne+|s2B
zV4_j?-a6QA(rrEi6V1BM_n<FYbPw-<wCchN(HCvHk7+Py*X{R)i7p+Nrn+ujEnU{_
z(GBxZd0Y3yY_#`|uJuhw-qm^1nQO1k?ieKdbP<bSs9*Qw5?HVf=r-<xQ-iv7wD}#<
zO>6)e)*Yd3#y#Es8F)IPQ~V6<QJsa}qx(7*?Rmy@_*-DSYPvQWA;xuoIe<*)e%k?q
zle+Krfjrc``wLK}bbU0nKGLO7?)J29y%Z=jx{oL_`q-*lP0K4={Szx;!cNbo=#jmi
zxf-o-&~MobMMu481BjEpHv&9oeGEmyj_50X0E~<NOWG^B>X(&)=cZ4iFw;@}XfY~}
z>CgQP^X~ewyHNMg3ml-}sjsL&bG`KXbeQ+nTeCCal#hO4E^2-CDU|)@r;jxO&0pVm
z2rUfI*Bu60puWR^${_vn0F;9DPtc{z5WOND-4&`Ir2PHk`dk{B!t^$jz7nqA&j#iR
z{iAPCc~ZaZKJ=pWBiSI)dOvy)<Mey}OAv_Ho8lmvpbyvr#bo{L{a~i(Z_x*CPwBVP
zwbLwpYZxqL>+iclBu6i!kZP{pX#zf-(?_g9v-9+$v^zSlkD{&11^sh0Q|9Y4=p4F0
zzuOg(h5GH!!cdXEoiap=^&ic*Lgu1Ah(^W|{Qxc9O7)v)BXvpN=7qkvtp8vf&XnoP
zUxdgN{lD)4=Bj=xMaQq{|Dja!a{YuG3|`ltqYID~`q&qtSE+w*6ZER|Itut#>usNd
zUX9*%F`TK@Z=)odI(^#0S#rD<`fGH(@TR_!(tYanpAA5xL7zw$a&PIs_5f(3{%_x@
zESB|SI+SkHfBpx&Z`T`WGuff<Sr6z=y)&I*bm?~<hkUobm~ydu^mm2<d0YQS8%lTd
z2V>y%U40>ir+W44=7ZO#|CWA`e*NFCqhkj2lQ+>JgZhVb?Q%$;q(Ny|KS-%C_w@c&
z%Jm)5chl{RQN0tbQ19yt8-YEhKSMw01HBCkXyf|G)37w5pQT1=Qa_tMlKoJ>Fa`#v
z^uEVHX7pneYIv;wJ_*>ihK=;?Av?o+FGAAZaIpzs4u*dzVc*d(|0&pWG9-RTgQc@U
zX$9yJ!*73~(_IWB8L;GP_>AT~H^Y|=Ks#!X%b<VE@NX`7?uHCHzw$8D(^kjRU{-_Y
zW$@SlP;Y}B#oc`jI|5MhHSl&o($7$q3Q2#1lD5zRhP+s`I?xc{Pp8Qt1{Tc`p$7FF
zXdE|WsNhAI!Ae;u;fCQVczD9_3ElLMFg!1X`ACC=Le3`*{}4=+Vf(+pjy9a5z;}$n
z`~*s|2IuQQi8E}q1&KF&S`04|4CBK9OEf%3A&Ml!4|pf6^O6m(($PSQVP*@kPZ<hp
zz&vd@tbjAA29p>XX@*`pVLM~^EdZr-!}kqvCc|)iJ$m-6!S*&vnT7-I(91IXp##Y_
zAl!&|%3y<-%)DHK@8=-r3@64x@(j)!;OKe7<yGi4>ji^A2N&}V=SERmVEB?Y&4mWr
z&A=`)upWRE8+rl(deM-&AFU`cY^A?gD>Vq;huuqtdmG^WWrOJ!N@WJu0r0LERz3;I
ztA;)bid-|;Q6gWt;aQqgt{cvO2fGypEq!~a(rUOyw~?z1dtXKis|^)Ocu`}J(D+nq
zcy0q=>I~aIN3(AjUZsSDn}(6SsH`{m)9=$@*nR~tw+vbI{xll)J^@~np@Zg@W<$q(
z@LCLqC|1yJc;z%iIt=x+1n4vrzX&h74A!?>Ak%H&-GpyF29HoMZyTQ64D)vkhxb9|
zu3?DsKY9)O4@1At&`#@;e#28QKxDuWL%-Ib;es6fG-OyrQQl$0mkjXk8G0MR8!^n&
zf;Vc&Uk0%I238Hg#tgsBg1rZZ1=b)i#|_=TgZa>~;vn>=46d{RdStND;nK8W%pIaL
zhM$FS?XjVT!Wg#3tT7NfqmFJG+Z#*Wpyy!prB#Zfao1vWmy_{V9iW|!>%!6cBgVJr
z@o+J2rV9?P#s%XjxfyG{tN=Y~OmTzEG2^EVXra4tA`)mG#`sVWPh%Uo?`8axLX_S{
zEnV91F+Sl0e|?R)$VZyzXME~yl>Ci<c0wV*`290b2sD06Ls^jVpDs8WY}`p_o*~Bl
zluQ|FJVZye$BpM>Xt5Gzyh_tSxbe(!kQ2sYnnfdw-u@^>8o#Er>66Cl1ptjQcK(RI
zh&CRiv)UM=c@5BFjl1Z;InHRLH!j|Ip7JOXj4w>Xe4<f21CnI?h%RO)8^eD?DaH7{
z0??<7%Z4ama@v?lOYv0W_q~uwGrn^j`e%%bL=a6ks%b@$Vf1_*UYs?qrSMp$v6Rl#
zvWziLp-Zxj`)H+@V?02I9=XOHzk+wpSVLJadB!snKsj&p2?6hdaicdX3yq(dfmvjX
zr;U%b*ci4B`WKA?%C0Ceo@c>Csj-mm^<FZrp$Ncb<3E!CEi)EVSnZ0@S^{#_=s`Ia
z*Nl#oYgBFwr7*^I<CgDHsxWTei=U#>=(GkVs*Hzrql2oAAJVy1jWLiW=2~O?uaK;>
z8r^B-cEh;57v!eV`Dd7~H{PNsN`sO40Tgc;i&jCS(fDRCoM|!^)0p3EJXjB2i}CdP
zu-j@pL@V+(qYp)m+Kq|@Q0OpDEkLQ$cz7G2yNtbcQ0O*BC4%%A)1HL++eT{wZIka9
zH`C_muCb72=3Zl{5*mHR&t;J5H?E*{)PS*l0%Xw0DFF76@mLIa!^RcoK<*j;-2s#l
zW4kY!J!<^b8RWh(*$7Kx#{JdMdtk&DD)FWnGp~a;Va$333X{e|R+?QN8cXRC(v)!l
zMRp$<x6!fRwDA!O*fYj=X;t>v=(7SEwx(nB``Vf2e1MX@NjeV-4yLB3@l!aO40KV{
z$+S2amRw9Tdm!R!+86|bZl<+#n0C}uPRE<aOl7mshwi4<C@YE{rUJ@D@HCCKL($8$
z=@pppHub#*4Ik6j>rv@z`kS(v{7m0aiif{x86^h?m}Dza8E9fY1_?5KPO;cv(|j5z
zLQMN<C<`?Oe2U8BrpMW6M3||7@<YQ-yZ6JV6DFTG=)fSt^y^VHG}83$9#}eQT1|O~
zQKl~_J{)aorUdI4(<D7!v8I11b2rY^Pr=Z5lQk7?Cz#6O!AmsVq7RHDnYg<FmTa1!
zw6PSE-x$D7nQRjwa@sV*fnKU<>jscClc|vAzcZ$-(<r8!e%HfbhUrWC6vJ7Q!&11I
zX);obKg%S&i}q%ln3V07WAYh6V{%QkbYb(HDUqiAJd<B5O6N_tGr+rGVle@hZ(8*h
z)C)|rcEfz3>A*V>DKhDqP$)J{E`*5nqG``7&?qsv??q!uO^tIPbIIiD5A&Bz^Q%xQ
zGp(g(_KN9m8DOrO+VTN<&Gf-GlqyV3D)?Jz+FuQkD${J*T~wRi<Uypy6rF~?s5L#i
z3X*lEO%&$6Vfx(-jksx=L$i0i)l^#q#Rk(u61`>m_6c~=Xi8^5qsbJo3Z-U~wG3!2
zrm{aF(rTLX4`A9%eH3MGH~n6QR&<y;=#A?%y-iWjF4HD1Omv$v=#E*B=}0itZ=1U8
z(4;%2rF3Y2*YpR)BzsNPZ9#Cj&s38IZ~9Heg(wY}Qs@A9(DWOHA%{%L*HJla`si=y
z-!rB6fj44eeg;dUrswJW_rB@56p%5~--U4PfhmfH!f{h61-U0o8ylcEX&O9)(nHfL
zJoq$aI`9h2KQb+~ilH%WlG4&(#&ndA(qmHv4MMi&?K6O}GjC2t$=>{s9uEiektHCG
z=6Q4@-O0R@I^WrxMBl(WV*ZmRMHllNx>n+9-a$8|-OSI?U6G^aeFvd;%v?n|S?*><
zK6oDH#u!?7dYYBq@W#vBkp$vxevdAu`<UN+2Qa?oti=!sHEUjj{&6$!OIQjsCrrUo
zxVejhPbbVzd4WWjAMb=nq*+~r_MSA0X{{G!j-uUEw7Kh9fW??o+rW!A2QPwpg8A#W
z=|e7w=DhQ;n`F+O52upNk9?t#Vir&w@08ic5tXOSpU(w$s(EBNoJljMZv{DH{_QtZ
zrkh`-<wl0tmR1I5&CxWuWttDujyTIKJqItc%_S7e$uaK=LMhk$2MvDb%(;z}&7WsJ
zJ{OAl<_99USYQtR3Z&3%zYnCyoKX%^Y`%R3pcl>YFTke~^It~5l$yIufVpIjrSqA~
z<`N3rmzlHPN9SEJU(kSDHSePR&o%RJzkpY6K0O76>*hyvbF#u5TLGT6()=X_)T+#v
zC_Av)y!jt6Ys_BjKyH}V-$Uh1^J`y2q~3h#b7(Y}J181*%Um!EXpQDXidHq5KcKH_
zG@Czt6CK=Qel8QF)$F_#o!4gm`D5s{o6kK0=`i>116ZfI>VH7#vYLy|!2NFX&`yvZ
z^X*AA^tL&fz7cT8`~_tK-8FyyF+_XKw<xEi&n)dnso#8);sFEZ>erz#Xx_UBydm>W
zN+%pPzor4$J@dZ>5E(JMP{PKj`CoT9bKm?kB{__lf1+*f1GDuL7Q7iZ|Bt@l`OqBN
z55+0-U<t@0bEyEWm^S-1p)_O8qdORn&BaGhva>vkRMdI)mQQKx?_l|va!(yCBKpyt
zEH911uCpbIa-5D>qUZ*ti)9|gOI<C87ed|5Voy8xqZY1J0hwc#9@^KtTXr9WryiEy
zXo~f;eDe?*UY7qw!>+ew76p%dEL&)y>}y#|i(x-Y9!(kkmcOr{GQd*(97=(fA1Q7b
zWLZyvhhR%U74$+Z?|p{KP|H7yQ95qPdl}GS7IwcCmclKwOi(;wDXK;(!csz8_ee_w
zEyPY*R@0U($`a~_QnW=%%h(u84drdcTCQsW8fRHqh(^R)^t6UZvaF|9JlWz)Nn|M&
zcNTc3Eaem~I&G;)fL^L)g8+uoETWB1;{7{g5xoPMbjwThKxJ4QX&-mi5=diNrlsxy
zoXN6y(Ftz0<p+9baxCc)XnmpOr8NL8vMez`uh{Y@O_3KZg)Epav4oU@S8CzKL;bSl
zJs0$0nPmx`tzEGwaE*K3RSOFnbKEAi)c+2d>lO*E6)P;E(O_0uKBn`tD$55i1FhP!
zfPRWv%k$~r)mc{4;CaLH1f{0jw0Qp)W3UX-^Vnc{stpRaEc@?3q|x$Z16*seJoPNp
zn=M~{hDNkl7W@X+S}n8k(LigPWsWyw+ARs2;9`g6clwY`r{y&YN_JW1-v(&6<#pO0
z^jJ>ON#AXYAFcK7SY~#C+_ilCAwYXA@4X1pXSuurdi|CKlqWD?8My}!2Q5W(dN^b`
zREg5CWt>*l_bjppz#Oq!uIz{TQA;@e-|>Bm2l+i_>7@0-153+R7#z3kq`!4}X!+S4
zpi`D#XfyiAl13@>)0XXb(cT$L?2C|mY?(NTrrFsTIjFR^NvFMogH4Vcm5w&-uR)w_
z6z>D<h|MBO5pl7x+I$T2t~RIWmvOT>!3XoGO)!0R&)sGj^6BS!*!)g6i9K!96uI-V
zStSL}+h&<3uzhS8OW?1s&Gi}Z{A{KKApSNH6kZOnIlBWU0&SjX19Xs$KW%%1ZJK9L
z8Deva7U7{bJ9bbI_P9;LOCVu3?X-3Zw^>K|94Bo4&(U?qWnFdg%+b!wnORv`j@PU#
zpS}0qW!bbeN7*nNTKX_V6cClIf-G4of&#JxL6&Tgr64jz5CjAPWxn4N|D4ac_k7Pe
z_ddUI?>XoGXrUKD2;*u9xKPHDb-;%)vL?WVGkjNoJIxT^guw{L-77E{$q4NOiDE3-
z3z2BXd~bcxt9Dize&txkQ{SQMJj3}Qe2HWHunb&0V|Y8vB`^%37-k})oOZ%V3_XQA
zFENh24+oPOb9sQLFm882GL2EZ8(cagN)B?F5%~%vGZ@BC;7TSVl|pn`jE}p4%Vx}`
zr0!M53Ok*C%VCt<#!zw@zx6{VpYb$BvI-baP<i(?hI0}`3K>^k1F(p(@F_GFGu$a(
zR>J7;f~8W%%l9Bs#&|g&q@0nv2+ArL0o!4sl2QNP=7#Yrm6cX8isevU&A3J{x*Epr
z*>-5FWju8UL#t!>y#d4x#*hD%1~WRhL#Cebm^K*=jB)y{Z!w}%F*A*f3u^$l&6rQA
zu_nf!bg4Bn{-!iV3u77Wgj*TRT&QkiymTK!YG>@~gQIsCeW6g+!I+Z=XYMjQHqrB?
zlQI4UM7tOn>(Sc7aHSgc`;4l5jIftsSqFR{!+~Ov{S2KFA`cj&v~w9`tPlYAkg-dJ
z#vz891#Xz}?|O`Igt4;$mL4-c{0M!cjFWT>d5kf00kn)W%Bfgqf)Rn+2LHW~QBGSl
z2j-XiVb_t_X9nlQe6tRCXJ+i*@M1r68?8WGn74934lr+i2yL#+P4uOxgUm&gJ3Pef
zSOA<G^Npq8+?gL=2Jv9V(}j1Kd4giwp3DuDAUMLT{Sb{unS5F^*pD$^TL%+f%sV0s
z)SD@wx)C4d@01eoWooD}(~ntm4Z8iAKhTH11DF%r065Mp5yRgT%)b_+?<8~4PH=(D
zC+NgS5c6}|_MKuTZh)3xrq&O3Lzv6NkPKz+TLLbOX`-NDgq?Y8HV~1_i<H@mV(zAp
zbu@G5M&M(Z=PF_83{&|H8qYGnqHi?CG9CVe<ay?E*U%WpT%8ZQ@ysTAi(Ozc`Dnbz
zT(JYV1m^l8kR)cO6@W|3m9&*iX8u!x-yntgBJCqmnRY+QF{Lr%cYvfbSJK^knb{bK
znayB!7lF%U#!rH~!n{T`FxkwxFT>JRrsX`i9OgbsqUADoQ+6khd5F#j<umi>@+e?h
zX2X0T(|t1<i<nM{5GiKfr<02%%x4(TS;~ChUI`Or%=Z>Trkq(v+0{zsC-ie&XI9g}
zkt$}{GcZ`qJn$k!YMApE17FKr)CF7}^UY|Gn@rYKkb36FRWQ-O<kO@27V`-z)@fvp
z-$G+E)8!KwY+?2n0p7}d^<~Uj8*?JnyQyrZ{ku>M;ttb5o7N8IHrjr5GVKKbbTQ{q
ziNrl-18s4-nfGXm)Wh646TaMMDyR~smzhlO{C=j#YB>LZSvVcs05fzI0E5iTYk)sw
zu5br8#Jued)x*qzFlZTJzIPu3d&Kmx{|@#sv%wcWjWT`WfEZ_X$T0W`=C8Nm?<8~g
zLNrb>3%y{%fh7>5(UEnS);LbAxX&QDpOxSTZ7!_mjzjVQYr#1T-jyY#VwZy~?;oN1
z5X+?(I5*aj3E1;s<$MM1FzZ<sRjhilGG7Pc2upAm+)<Vv?Q4&*R@(veVueURd|0(X
z=<{WrOMp^8)^^$x`LoiNg9NZ1NTKv3D{ve>1+wb;AsNKl)&cGmtNVSp7R-9S7v6`k
zbZam{p{#FclN`=!38$i@)2t7|frw!73eXzK3X}pE#X8xD#%R_sjXs9;JgxlCvU=zP
z7Ux)vqwqJDb-W9W=UHp$RT{?%)q{&?#nz+m0*g<(zKg6^JV6pzSGW*KWG(y-BTHf(
zq?;m{6*%n)JcCkL%jp@E%1T~<QKYeoXjhTWay8)Ry3AUh3t$E-kj_e6VeO;+Ru=0X
z<wdetCW<m$WjzkTB;>FX#o%&TUmb&qJl5_8kOEfxT{K=}`OwO}kTruY$0F8rH}n;=
zJ`Kmr*h^TUpF*aT^>zeEIcrZ8IxAQ&(rUMowTq%I*IE6v;HqM+r_5z7YXR+6>sX^-
z!?hbM)*Rq&vW)a?fO^)s0yH+T_R)^;7HcPc1mrgB^9LYJtQwl2W)_Q1<+iYXJpuEr
zcGe$`(A~!J{v7yr)^}98+QE`gIl^7m^R#yEWW~?N1a+}qQUY<0_0$M_>SlfH1k%GA
zr6A;e)^z$hOfTyXN_Y3M_ELzUpQWZZ)d0(fo*{#*rSwF4$m+ZdFNRn}HmDwE+3P5M
zHNyIy%B~)<vaE1_lr@X$TgF&V@gO?RTKF?WCs?<4L2{C{bv9g^VvX70lLOl`9K?xT
zP8%0z_EriF?q`c=QRTw^nts;<>~*x%ab+hh1MVPu-;W?}?75Wmc4t3n{~SOM_9H4)
zI?OI9hh0y0FzpqNu`@Pf6kco&W&6C@PQF0+uq8{-=gZ#y68!aJze6Ja>{o8W!{h8E
zDsMi)KJ5s=N%oB%3_Fnh<YF`iu|;~|PO)7n92U&}l0K3d%KrI7+T(|@uTkA%ID5Se
zzMW=25eP3L*j`k}9m#IGi7`d7OKC9{&A!|Y62o3iPpvcT?<hHRmVL$okyy5a99qt^
zlj*AmaqM^L{BS&blJ@8q*rNUDyU2cRHe5?!4-ddX5_{tm-G7(Z|Dz(vWcI>NXiH%)
z{Re)hvW;vsUS@B9AHWRu?n5w`$>x^;c!ix#B#XU;w!YcykLzLnDmx|-jk#>!Ctxs-
zT}~N|eD>W&a0To|O>p}fyZLL(Qz3g1Epm$3N0-ux;S#oyUTUT6XE#7i8GB&>xN`Pp
z6?9jyf03iHlKnI-@~^WuZGab5>_agi)$AdPW7n{Mp}l7<d&^vi++cH=0NiAEd=B&V
z?5NEcQUiN*H<aCCzmSMuxslx_19zJ}XCM0P&FrI<5N%;^rs~vIwlgi@+SpCBN^fU7
z-iFLwcIj?3cCzz>(b&c2JpqIF*mL?}u$%pu4O|a9h6?cRv;8Rk-N$~n7hFI48!gBK
z_7EN59bo6s@zz21Q<)HX$c~^?(U6^eg0hAqY%RTV9<lSNF!M3HeLg%LWnZ9V{TO>5
zMXAQwZFey23HA{RZA`M4I)F^E7tnM&aQ>pp(vh>z5u<nJ)Y1{<{hSsnl(}%OQx5L{
zXE(hsT{&M<`QSm$i}?T?;@DrI2$nnN@?OYzaE=wii^Ck71u~wTTMt2wa6XQQh!<z>
zb#UIC?mxl#a3-l(#+S2^b`^e{n%`j1pYz6x7)t=hV>#@e;9RB(r<0uUxgdd@Yz-QN
zIQtGl@)YOA7W@XmoCv!Fc0)LS&}t)$lOGPzaLyYmKu&X}Qy4yivz>xBk(?7>0UyQb
zYydu*GeT8RF`Ve9fjh$)r}gex&L^wTcaBr_H*}uov=0Ih$LW=Wi|72b2g)vRo}%T+
zMNU8*%qMWnkLdlE$cYHUurG1m`v-H9%*h)CN#V430Flb^IS$b@PCq@RGdK<u1j*#A
zqT-V)oR0YzZx$z*f@9g7ZyrF)RgNweI&(N)8{t|mC;bI*d7RJarC7jOv<f2EIJ_h9
zsgUE5L2K|L&dsgxw3yTK19X>i{`?xiGR~qup|qT1rrW=g^De#iuXFCw$)zez3~k%0
zIT7>~j~dQi7Cfxwyfg=mb)3pfxOS7nqIE_+hx;;c4V*=E>g*Qh-Q}>`$k{prT5fY(
z9cT^S#F^!RQM7R0pNrO3PJJN|ZJbrV!KZf40ELzBa4P13>)=#ufWa=#7W#j%_c&G$
zXzS*@F#uc-=cWmg_c`-khq7MIxC12nIIGzZ>F0b*E5!$#vp;|ga>6Ox`H&OX2oLQ;
zoKGlbHO!g239TcX$u6jQ%<-hc=uwV>3O&X+4zEDl1m_dV;ZJe`Dj_n(+2V^n2kxe0
z_+cEm*B?NO6Zh0?Ot3RImJ$;#-1L4(9^igKwK}fcp9KIM<UV=~pAK<->!Hle&UGk)
zC3mg^J;D!j>%V}gCwD!SO&;O4<Ur|B?x*z7KE}0Bmd1<wn;vR>xo`P{^W$#wglqoX
zjfcPma1YZO@i;e84!{ZS(n4@2xgivc2;^qA!<is%R4L%W+>jc05yG{v`2=hzcW5JI
z!ng(WU=HW1?qL)W+zk{Sj^rMX0*T^g(b>BgZs8h?_Y60Uit*2K8|b@n=eUEkNQ>n@
z+5yS)+(P=SWgNFy51kjde<opo7rC``|0Hl{QJrHV*Y^bglDNn0Z^6Y&TtN(4lexPx
za3!U3e_RcG8aJx|_;jx44ES`J`xU+RGq_w88Z)^I=v+lMcOHe`uX3GVg)=$a51HU{
zxnI-Wl*esp1<B_gd=35<aDSkc{55XE8Hf~ew{8Qxi0c<gIi_OnPYiUHaDD0cb18Su
zayV1Q-ChH`<=j5X1y*oBrnEsNmo*44u5&pXL8`bxr+};GcJ_nRaQV-H+~9sn+s2#R
zZ<}Dgo;&Fb$p&sZ71iG29*l(fM(#6I2XUMG1sE)hxMALv_4Dj+P<28ZH}`M2)Xp`a
zT5RSW?j4HKc5ts!_3vHo>l~==<ZAX|4!XGZ9N_P9MeQ)#%`N^N@E-1Fy8ipP-%4P%
zpX(h4?g4l98|WM0N?yQkJ;+^p4%Q!XpQ9gZh^zSsI)}Mi?5<Ec!aYt)%tze6{6HRa
z|49X6l&kB87h~LSsj_68n_dSp!FB%%fJttfAGj&5%U@9A!1LJ-rH;HuZ(<Nmym~%d
zbLL&yj=lrDDO%mQ@>cwW#)G^KX21{e@-9KO8_#7MMI+pKc3Pl&@b26LcbNBh6vUIa
zQvef3c)!!-c$BwsCDeHFZY@BgH?Ndp#Xda8MIgSsJ3qjZA5XFXCj5C!s%a14ouU}x
zah{!4Hz#<#6w^M*b7)3iAnz^(Xio9Yo}_GhFt3%0YD0KiX~`DKn^pv17%%4?Oky~1
z2YsC4G|z_$h$49J1Ym@bylhG;Me&ZUL|-(|<1BDzct3v+FV6DbqXpDCp5G9L6w7P(
zg6i|Umt-JuytKRUBA&O1R{0lrKc1m)CtT#Mcn#VTc;0WLHIX-yuBT*P4m~tec>9?c
zZz}KQAK*+HZy7~q(s?OV8FHD2QWD%7yl=w*&*c3@Mdep`0Tji{;_24|m(6Q_4r9sT
zg<gc)xjfBgH0JS`bc!pVH!~Q0_5z**{ZqYbJmVGs3wf??7-$ji5*4r(^8%@YpoC`|
zLtiOx_`l5puV)Eny@Gc+8I6^^D2g#$=M~=pu8J2eg=^KkoIhZqhL>IigSEWJSr~mC
zuZI%(H+Va?LgXgTB?KZ3cHVn6ptpEm&%k^&^7M2C-sbJ<0I-QSFA$`e_uB7priI7U
zL$Z~ZmkPUWJmbgE*3R2V@5DR2M<&2KdEeDxOkKPkw1mIMTT1({Zr(5@)O&beX+iGu
zzMvd-FE920aDBYBU6c;$=dGh}Xg%QZC^Im?`-^f@4|$#MLuQDVcnb~>^D4iCi4op6
z-bZiGv#*SXXJfqLw}2k!E$@Z=1ka@j4o>p=zXNgL_fRdABj3vfl1}{H??8z&zn3bb
z_VY*Yfpg*SjsQ8p|BOy7x$?8=SiwR56`Ghs{1PElyYVwJA>zSzrbq2z{@R%skte^`
zo`cpS{B0vZ9Ob`E7vM3zo^EX~{t|lVc=K!j+d1&t=vn8>ANPkgKfd`rs5#E>ISuXv
z|L4~+zLWfX%JT;DSDXO};vb=u(kZ@SHQWy7`_NlDgg^QS7DD+e==l=HU-%0Z$%OM4
zzYa?g{G+rDisX-e0?{b`20EV^%|GxHOvLbqrvN;|H&JlxEdQGi;o&*H8w-F~zMns|
zoab*|2wWVWRSS^|{GB(zUF4sg3rh)nFM4|=@+U5UOXAC^AmkGN{SvxullePVz|$1|
zv(8YO%KxSlO4Il!zky6T-;cJN8T?H<fzRZx>x88%d=33;pDg}sbgC$u|78jqukyE1
ztz{0ssUIeC`Oim#<nf;f04|?D>owdO1^k!)0HBEfEG@5#`2maQzm1jfZM1VQ<zJ)w
zy^J4DZ=rI2Q39N);QxFYN-OyXsI=)izatI!D!zf<^3{CRLrB*0#lD!JI=&~Zcy93D
ztby*Ed<7jTspo&5g}G?phn|AuEq?MZn9)Z5656HS=IcqBy@`L0p5V>==oHAb@~5|f
zwDHf-2X5N=33ceZ!~dO5!*=lR(z@U-|I|1dJNb+&u++sr6Acsh_~}%H(amSR2$3HC
z85fB3@;{}UsgFPZS6J%jAI-)f9`IFER5!ryI}S2v=cmxgzlZ#iC!l7CuU-b<hWT%8
z27ZKJPZjl#_%e#7jq$&y&B-`_4h4B9_;V?WKFLp|*xD3-ARm$r0@njD=qR{B9y$rM
z7eSl_iXg!E3q)0by9oZ;4}hz{Z3TX`g97{Cl(Ro1Nc#ZZxCvejg{Zs0dmFs)5d69f
zh{J*gPbl>i7#-l@5y5X==sPONs)z1lg3I&-_7*Jbf{2gcj3)rTf{|Y6_7fcML!-YS
zXe;~;5Ug4b?zlie_D%?7^l7t`g6HiYVV(m8`%gn@kl@RB%tf%^Pbz5)5nQ)`3l&UJ
znPr$@Hl>Eb1)K$tJS`Y#g^38kC^be30_d3+C761Ep+yU}jKE-wU=F>a&Iy7j?j0*&
z(mwvYV463^87DB$gJitm(^0DEy&yP9+wzNo^4kC=2>wpMC=vz2Sa3;#QCfmu64>Zn
znj+Xj6%wfebsI>U;2SK#XQm78{RQ}CK^(n3GX%x-eSu8D&_C$AB3Muek|l7{!eF*w
z?PnOvRY4SOYH|f*sdS<xPtZga_4$Gw$3Y4N>&jv2nqV)z=L-dqbZE3l;8hHKv0$q=
zNQq#LJ0wd5YnEe7WrE~s5UCJ2KLdX&1^d52-*tg<DH^K;Su-J0EqIgm@il@aKZ4W>
zth=G5PB3_tHV`)iH_E`?6!=ZTw|c=UJx0+exFm-8+X5l2H=6|9pP;){(7OkHZGzu8
z7=63oG-XhF1Q~R^=DuJBZJ&At-w$Fg`UEQ|Qr<84@esHNf+BiC3<#bofrUZA5h}5J
zD45{|3-%#FjyGH!7QC4Yc0{2005XpRHSePFv0&LAh>i+cV}KtMgq%X-xZrcDkDL&k
z{uO{p!Ot-uQv&-(Xmk*EQoV$uaL5ixC*dDs7@4#1*8nu`7nT{}lZ&vy6GJ*6G|4d*
zSG({>FBm*1d|UuEhlGddB6kyR-UOh#aN05q+e3JV66uG9Tauy1Q+Soi7mf(~qhRo;
z@MB8G9uv-QN28bUPAfQXq4$sI^AXP60l2Slu?>BG!l1pFe1GA&N@xiXZl<*DaiP71
zKF4xG_yPUQCxuP)C=3+tqfB0q(19Ler-Vt*pf6a+rB``~a0Bh!Lxrp8M-LNv(^5EG
z_>me)PYazi07M8MbO9bITtbzJQ9{Gp5Q!EtS7J(HgsoK9bw=n&0rRs$nVrIU=Y%V%
zDj-&P{v80%3pYE#?>He#1krfmZn^|62-kj#-{7J!aw{YggzwW+FHyLWzSWf^{DBe+
zmxM)B5t%GhR--XR$b160RADqN<kN)5E<z+-s67XJnZiIS@Vz2@rI0r8S;D_)b(Jmb
zx&{1Ip}r3?Il>+{^yLbtQ!PiH@bic0%NOdXYQ8{tZV8;ZCiHk2eTBkp^z1DX8nQ5^
zV&Q69be9NcQ;fV+m`z`JDidxx1$en|1$}*{LYPNe!AjwVG`jz;3)lXH)+*tSWazHO
zuLd<W!s&tVqE`667Jk<We;!8T4dL~BXuK&j?F67+xP{6F8-!OVYkW(n`w)GNLYLn$
z`rE=cuL95{4BZ1SnuV4X@S;Wd?+`4s3LP?`vrTv#5jXqHcH!LrsuzWMbbWLPC5O>@
zSNLohxK81^U!bN-$l8p?d%~^77-+XpLX}ZH!mp@;<-U-;3(oWkH`3kMCtOSEr+%Ta
z1wK6x7SqCdKscQinuEgXEdV?eemM$}A>sc<;i!FBxHKIujtD;-1LBcTK+%ZD!ry6x
zqe8!DVRuY;T#TWO3!kck$b``M9K4tm?xrHODPi5)Q0gFJR|DWEYDj{JlW5*jh&YSp
z(F=3G=sbNJ!bS8R?Me=aT8}`)Rg_i&)d%gORqMbW60M;6W;c<J$`##3)jL2uM6n_?
z9u}3y!qcOoI}7o{9urln(C8)Fk&E$qi`aFr<Rem3veH*{-V=R(B6AIf<S(lD9$bKE
z*&V=-i`?l$YbQiIn*lf}T1jiXK#@I*J`WTm%B1`Ll<3xVC=C{QQ;klDNV^S6Lq)<3
z7=4&1c^rM=q6!MUpBDLDg-C>GrVb*Jq7-M4C{dvh9!869QxQdsD1zdZXGFym);cRX
z<BYy@qLXVd39+K9X%IOt`rLjOY@Fz|KY))HZC(s=LG=0}=)Nd&ehqyIBB2wwM3M1p
zc#$N!jJ?jxOQJL?NJ$n|kWVS1*>rL}RkXVvB59&VE9|C=zM;~H%c5o>NQP+b?-0op
z$=-n%S47_Q(7P(S-As$x9MLWw5V<0w22+zK+Deazd{HF@w+lr76hriy=pvP%6pDVM
zS8S0;PPwsS5#uf3N<?4gVlGQXe`i3lO!Qp`X0%+C=Z(e+(IDlGD@FcXz^g?i^a838
z^-+$fR<y;LKKWHAnxruA4H2&lqBlj)Z-?%B(J!<~X%Kxv#hSN7Gi>N<6wRVc{%z53
zv_@<aJ%PWO&7!iCu+$<db%Xg<(eTq~Y!e+*Lub3_S&A~<5e=k4q(kIL8|u5FE5YD8
zMSpIg^=Fsp#FLoydm<6#_q#=>7NfIAba@l-_eG8$z|&q)%~!D7Cz_<f^M28xKcMu1
zXvZCJ1ETRUNDhjArD)MZQCJ7G42jCxFwkL9C)K5lh)|G#drP!wGq}ehuiX$C743Kt
zoPA960R<JuMT7ZJIw6Xv!ayfQ-+Du4N;DjYF*%6+jzG7gc*6@oIEmN)fKfP$uTfFm
ze(_Oy8@h<Q9DzF^{`pJvxr(<?TIQhmPY(bNiGwy_NN(a+cf$*J@eO(udWapK1pKgF
z{1)<PGd;ycv_3i_{*+3aj*3@r2RSBAzJ@+8v4V1P-s10mfi@p;qX0l(v34!`{KU^t
z0K#9ar8i!Hcn4`YE`CI3drycXVj+1_e26k-f#Uo#@FGYoq3rc3@zV>?7c92RsX8r0
zyzL%HsQ3o0CBnoPsbVf%91skdNbzHO7(|KVC?gUren2-sjCentl{h12e}l%e;y<2&
z-E(5rC``nP$Ej@hy!a$l6vv5wnhD8x@r@vm3*xsaj&@O8`xCSzh+FNuz$S`Mr$9}T
z_?;Jkza$PR1(z(|OZ&JKu_JA8Q^onT0ZS9V69JMg4xwD$W$_<R!ET1QZ5WN2;^JkH
zydrjR1(zlMAB8Qm#a@}1ysP516(Bj{UxJ}JS1h1Iu6g3P9D4udix+!9O@TPV5uMk>
zI*K6`iUsa4Q6x^;2yMmUFR7%sL_9`czb_T@o&~;4ysi=RTrOTtLG=pp7i|!!6uaaB
za9#WnowTYFFQ&Y8wRpw%FjOO6`6VQ8h_jnv;imZIZ2E8S_2T1{gKrRjdjOrc#2cur
ztx+6B&y?HZs(OeviL2;^+bljzh375eXP$!>tzsKx@7ly&yMb#L3+TGKBfc38pE|^0
zbiU@U`1l5pPH_fB(7MEP_5g5CyyQ)A-QpbFs`i;Z;$JD`eP8^1E?RrVv+3>9CuY0=
z_xr_f(h}-{*zHTWKOp8cLu61~G=;v0;y)-vG9=zhN!nrY7c7_`5tmaL(j)Pk^zEO=
z;!iUG7!{9M&^IPlQ-WYzJVAM&3Gt@;z}Y9o%Ojv|O01<aX9vkFJ~|yGQpzehNuIYt
zjkDx-Kl=7dGWJ57i=<NuzyXPxQjxBbnl}MBD0$^;*gYhv4S|T8<hmZefxD#oC%Ek)
zY4{Y%4oh07I>A#C=mgvm$^N+@N9~f{X+Rv4MEna;FNw=E0KFwTx*&WcU!}rDUr8N>
zoBSkWzrd2e<W?WJ00|=;_~Vjq--gl?k~n(Yos^7Fye3fM_!_hXNuGR+zEhIjRL~VH
z5q}6=h~)1w*b9|Re-0!}VvnF4bGT$q5;{*y#QTAWkSzWU<|8FvQuseg659lFMq;JV
z*;z>v1Auc9A-#-aC6_7abY60u%3R_kPYFQcC0D5)=Yqs=7IrU65-F*bAPF0QmPAPx
zWp$Gzohv~uNeuQYa5!1Qq+mmeWC>-LQY9w>Fkfks-HA|>E*bCyxhzo^1D_#jzX21O
z5&?w~uSm)$j*=x=whDdOlJuuRu1bn&?UEyTP6QLVk_ArCnJ4L9g1&sooN^c{kc@l?
za!qo5BZW;1C0$hPP$Y45hcm^Jl%*I`iR4KwCZSaFxC<uAB&S}5WVu9`2WKiI-*3g3
zDkbOXi2ikn=^c<N$y_RcsFpmp36eFE`Oy%ml{})Cah)Wdu96#)UDF|QQ*xgc0k<UI
zt114{C~>BWkJ}P4Rkk!qmeRM}nkB_LG`2{#tp;h8Y<LzX+9b=KgVJ_M<S}q}B+Irz
zO^4*}8^GO_oQr~`PKnzE{IFe;mQHB7Ct*y-$hswM&w%tuc7+3XUouLE`FkZFcGLaW
zC+YbVh<?dWyP*4lq+0+oAerS1ZG)1}C=vTmay=N_kR+PcAj6U+^lBfG{E`a0k0k4B
z(fC**r~nz2?B0dOG07q(0OJzoAjUf(X{Qp8Nl66_VoKtX0(%b9mtThWc1LLftp}Z?
z%V}rsEKOexzxPY`P^i&Gx{6{m2c#a8@WNGkjb0=NrJLUbIV63!5&$>pOcxBsU0R+C
zfTy(SO>jq~Fa8BDj!H#ofFF}Cr$SpV>EzpR##_278I3;Djf<eu*Dfui3SB>Ga}t#L
zOU3lhi2|hG8{yk=>D6ACI3YFDKu=1S(OWoB`U&l&gQTJ17;lI)^D2~vN()6W5hi`i
zhGe*uw-!S>Eqy#6$|9ulPLN3HP&q6_Nxy3ViIxsrhO!u`{cU=EpOI?le8E}iHp<nW
zlfF(QR=P6|edndWu7js>(#c2|jF+~33*8r_o(y<#QM!i;Hxi_It00mnEumCXk~H}U
zoVg@*YR1Ttr9vqhQ>4!{L0PKQoeFx=q^J6TOP8*;e*kTlr4Q+$n<0Hf@wrUtS8qV(
ziga5&fLT(G7eun9JL$T*Dt(gv(L|2)LweriO8w|bo+qtZ3rqP@Ek&jZq+ZLxU6a1d
z1Syn0x&)m?QiBzMV(F)}ohp%z{ffR)>Ee0x{wtHZEQ7=4(%;^}m@1_gYGC5JH1k=I
zD(U=B&{r*8eF~B_(mz8XQY&Tr0a7R3OsSX~(kE%4H>I~JQd2LjtA~jOX)oP>x1@a(
z_-vFeq=LiS(iuzOMUym}id37WZ|tE0iZ<!<-vHk(^`oNEJJR)PDD99AmjHiP`b8bw
z@05N@58W<lDm_K+Nvmn?(=B~J3a<4?|5%4%-<P^j1yQe*EdtjkjiWQd{nB&;ls%CC
z_7;>4NHgg|9F)GU1@}-|`WMAthNK@!0UVYJ6Mz_zc2cpzBWb|faOSbpEJxp{w40(E
zW70$?Xd9RQco}3u>UABKCZ*Er@P0}<jr?_xB`V>eqwICs0XfM+DX#4-Ygq@8{j$BZ
zJaUl*ehi%lWV@#0C2n_>&F4b*K^bc?WDdz1DR1B=d-uODvdUin3?@8eA5j$Pu<U~;
zA>t`pdL8&9vZQyR`>4$SeE^QhdMLo<CHpQDlHRheBoH52?R5}enS^!(ezLd6F_r$Z
zq*4qpK$e~j_;I_;@)p<=vZeHBIVlrRx+G908boK1><}H;Iwkv-N(_T#w<*XNB6}=`
z!BAN;#r48uy~{9)a9JcJF;2_aPoghE)|!dQi<G%gEm)N7?I380migNOh>`84cj_6L
z%mIM2GP^JB+Rw?7699~rz40DKcwWXU2Nx$ho(>W(JMsV`7i7)Pz|uw8CJJID$YSYk
zOq4~?4WA@y=7YN=`|e{5G+B107$ikD)Qi4U+2>SMm?jH)1tRIP5K4YrmT9PXIYah?
z{ac7;%HE}C=oQ&tp8%01+nWI|vSpSqjN+;+m@d{l*$4&H^JNjgqOm~s55;Y+$?A;&
z6v}+!(N`q1Pol3_Hj$0K5}CLKeWfy4GWyD7bE;sdT*isTR946=w2iBjb!Jii;kqo7
zY7MJo|JHz1%TB!p-)dyvl>$*KTfGnt*U9d+0&zq3Cl^1=P1(Fn_+jg1dtXCegY3jM
zXt^c(gLdnUGBp)H-<Ew#tLG+J;s|ifvRWmaX_0MM1f8w2HT0>>HrZM!9a3tSF`mZ=
z@5qky0^cDUqub%GY|9UDrc;*jGTiTy`No3Wlbxg>MYrr2#n5_W9{=5VGS3q**ejby
zWh;HMr>24Q%lbcuvInyBbRiAM#Pp6ClpUe>{6pF2i=b>sCiJ2B%dqSs6)=s+X4CHM
zk*xb1M*mp$)l9fJDtrDtXd9DFcL8u*R$BsYLiQppuO?+{cu+be^VkBMgFNRoD0P%q
z(8cB?|799DXSsI?$bNaF7d&*4e@q+I1M&q6!MVyUPOxA<D6gCY#38x*YqYw_TN}~p
zF27C-6c2g(a^MfkOK7*@DVGdF<cNI1FK9d}pLG;=kI7k-K=zV5u|T}#i|G42K60ZJ
zeSY#;@8FX4m;bGW+W~SPy0?zYU*$vf3AvyE<fL6bZxdPr<^5EY6(p~x6S$}3bG|`i
zuzc4jEQQFO?t%-IzfP4}Ve%g+))+2VklUx_&i`UABIL7a^&KgneHwP7<c_p_jg~*{
z0B2(46$dfwGx9VA`p(MBC`fTmey<uLv2y!-eD`<ed3m}3YU1Q!a;S-y-;9877v!_(
z>2p#3+I#3rkgxs<b`#}`Dd3tU-|GhMlKfrT+$GDm(o;S~o}LaaRqjqv_B8p26s=B|
z&x?lSWqB1@$dE6heORX4Op)Cy@}+i)m}bd0&_J{0|5D-9Rk?H~yvUJnFawc`xrD=c
z@|_g$$(Jvo=zM{E={f+e$^W?qks|qP3(;6Ck3E6L68Te<$SRfp)&)SBJZm@l%H=yU
zVX#8(GZW5K%4@EIyDnFA?eMfp-cP?wwcMTd2{rO#gP4+9`Et7S>f~L2g4~dY)48vk
z@($Xc*UOXGAPw@=Xf)oEKOGB8jq;kKz}=RwTaIBj$#+vgty$i)4+dN0DlUfIDj%Vk
zUz<FH{v$@a{1-EQq~eY|oHi{T@+ivC-<7{Q2czhev)=~3OP)d%Q}^UMsN|_zew#}F
zdgRZ~fu;NMD2jyl%739Bwom@|PcYFhcc+u+59BxG&@v!DPS^UN{H<#E^iY1&7l0u-
zhl+%T<&5H)xc^4vhZe(|NAk$c=zJ{C8iF&U^0l;jACoJS(Ks&u)eBxs$ba&L(n)#n
zU5HG{A5n1AL2+gyoN-hvPXgJm_{I;8x+wk)hrt7iu|Ggu6=&(DJg9hm4Y)&!CutYy
zrg-Ka{I$C)!tR55C>8`l=CESszu-I-S14+BM6r<e*+&)Zd$4;<vF8LtycB#oDB!Jd
zre&RvVt6ea^;Hbg>&#DaB>*D+ia<JS9-#QD8I8vkvT=x<P{h*Fu#<{O$|(ja9?~i}
z$gYsOqw|#FTUr7IE3{MS3{lK$00~tnXsH^esLq78a78ZNsizemN<bnM|D*6vq+-((
zAW@2THsH~U9I6wIQ7FFwIiq-=3O~*&n2E4-UZJP*{WyiwR~TTtqDhX%3kv%&QhHIr
z{S96uD70!goTxbJ1Cpee=MVfPML-2evVu!jS&HJdSooBxsH2BpnxeoJGn20PmOc-0
zS#g+R{TT|=04!xH!WRK|MRE25RA(u+evQU##R0kvuPVHDp)W_FwHE-Gt9Y3*vw4cf
zM$CG?;z`;K7AQif^x~T07k6-lioe2uFH%JH0Z^=np*o!sMa&L}lqzb4Fj1y>f%eel
zitjH%ONC;>2Yr=_8Mk2Yx}rA`-d8Eg>D#T<iXHR}tWkLUS0rDnc*sR(okE`j{0+s+
z^me+b*!(oOdPVV7Oi+U&cno%LDXjm4wnoJ#<mhe1dl#UsNx?k^K(k^mrFmNvHBUmM
zRpGb+jcp1q+W)mH)Stn^9mTCC=<HNjMj+XxNc(f<tGKxo^D3dHTk&%|NRI*)Te!It
z6I;CZPQ7VQXajIi@dFR$A1Y#Qp>IgRdmF#uu;L^Ib4L_~RFd{ck(mOej}`j=L1a|X
zH5Wg{m?HHz^o=VPhe6APVln+9lZq|r=$lfk--1CnD7QTeoTGC5L(HL*@*GXGvodHl
z=6Aoc+kOc^7o~w_{eV){0nSx<dl+gCD!pheen>gShY2_3r&OBhuB@d(7Y}9K0Sx=F
z^23*)+fz9Z3EUB-fR;`H%E?05J+9<^1ad;@m;%X@N+oR=1C^UR;98I}VlnKUQogc<
z)+fQrr;ov@5aq^DaG}a~Mj;xeG+c)HaAo^3aHo~uO#%_26w(4NQW@rnz9{9D1dJkD
z8AP?kG0JJQNjjr^u^Y~uRW6`+@;T*DFdAc(9TcHGuN1up$vCC)Z;*K9w-@P?+!vHb
z4}ra?oJHI11f`T#4~fdt{@{|7?WbV=lJXr|{3k0fP^vve`DPJBQkCvj3?@zaPby5L
zD;vFF;<8dlH(Z7?m(DF`DmPGE?uybv3yUmeI6bAal^$&X<SKu#Qdv`;QdEuBd?lBb
z&jreZ-cWi?d4e*Wg-T5_`ihj74?|6{@&i}&l_=LzsbQJ2Pyvy0Wy=cmRVWMTFhHg9
zr!tW1$|t&DqDt8?39efC2bDwBD5t0hpjKH%v6VXIUp9=zenYvO>bGtx>u9-OubfSZ
z`v&DCeVyW#a_-;gYf>Ibgo$QlFdbZMRr=imzD-$i2+p)CyT%}LM`@y@e24OtBk=dG
z^0j<u=~PBie7Z~N5CYZrl=rCorCV9w3}<?j`82@$cBP&UaP=y4snn%UIcGY!e&t^J
z*5(7H|0HAvlpMN(2bD|c+|EPg#{1AVr2LNltJkpdXA0YnDBpSt1|KOSX|MBGIYa@b
zQRT760E{V%yW!}#(vLzN6H2`bswb6)D1ASrw96?u;HY|uR*p_8@ilPHDjfy;4yab<
zLey0iQHr4*RDGF+p&e39qkxT@s&G3jxvOkS5Kq<P5de;;N)_lks#@m@W!@^&5AexH
z^+7vCd{x~VaDJ*U=_mA8Et>=L0V;R<22AO3mHTp-IH9^lm)A+v(?7%SKvgoO1A<hq
zE(QLSYIQ9{f>p0m@GC^c^aU5HdMXSC!&HN>Lo!??Rseol<?;+nM5un84b_pV4hp+Q
zsb<j|I$AZp0m@=jZWmzwjB4b+qNlT}HMH9}r*b_DZLz9`Q_y{0C83htI91^P;7q(~
z$^tbPR6FQSy{OtqiP;3zwDaH+RX3brH%Ya37RV)4WjmB5t3H|zWhtu3W%zwkRlR?~
z!!%Vj#o^OcN{ZfIR#mT_`2y|^)gFp2W~n;r{X=I=n`;*speI*VP2cj$Q>FG|!1=25
zMyM-LEt(JI*HqivAX2Dmr<GKZ%86DM#VWZ6NQr988)z(5Ev0Xul&Mygz*M>F7YbKb
zsN^QtuT*i*fxE7{<PX(Vs^~{hU9D=S^?Hp;W2f(;)vClXU~j4>=<cXj75xmE29*bv
zG&66hB(zg)RL!O*+-=pOH4tf1`3*s7v#Np)9JHwZm<O(1rINv!JF3vLu-l=UIFH6Y
zRnAJN?pJ+50gwl(+tUGmsG7GPB15XaRkUOrRxRM6b42Ah4Xuw<rS#@|tP(I`cU+af
z2X-e^5?aGdsy1o>a8&1HVDwIE4*>wq>VuRm-mjiD2YoK;tv^HA0rhkATtBL=Q$Wix
z^(XZ8IWP53D`4JRJ&pdSgpZp26s7EZ)rw5~Y<}v!RF>keHh&CYfcoz1@Zz{SO#;yq
z>M{zUpH%14W;Rg0pLV!G>U|5qol?(thQSaupDu+^^)fn@AEstf%pzRPrlrhjb@W<T
zh){n>Pnc-+nrl!NqqbJkf9W}+UP3YDvudx|7|c0!7)?~H+E)wR=hgA87+RcKvk>@r
z^&5rIc0rx}JMb6Pt!d~>P%oE&OH|kW3N1-$3q=qwsSBwhJXsz3HX2jZr#^<=boKkc
zK{8W4RuArq`l+u#>{;qdYtWjlesvGntLnHXG5Q?!MsJW@bvA{j^3*|mD9u;zSOcF5
z)B;MtUsKOI2}cXne$|jHQol*7*<y9-RXAFrR{sb<sruI=5GhkPtcU7y^_y-mRG|*C
zfU8u$(T2Y3cJ<Tlz}Kjq^FSKa>-;c@x7EK3VW~+SLgfR^>N)f+<QDZ01HiYcB_E)%
zT`i6Wxud?g0DunlKjh(E^-PLjbgJFxb0=Nu59n~(J$3zCAl>TrDgf@Qc@+8YRsV1r
z{`RTuGiin2uQpP2<bgW$A+!ysH#q|_sLpPN(ueBSV7NA<o(usutY**(dqf?00+aAq
zy@~F)QMHZU3uEd}6VNxVZnnVR33ZtWBb-!!MIY#zQpfm!IB0HNMW3VQDT+rpX}++3
z1H7~5!36;KYdj93)kWh+mB$A(A3T6kSB)(a!#=3_kgl>r8pj$)x@q=^K|D2{U%-o_
znny3g!(*BcKEVjRG!s$i^VYn05(a%VA5ehVSF@Yy6#_I1C_!^v(?D^Q6PoGU?a+Nv
zGpI*rpl06)fI*t=dq7TUI_AQQU`_lJ=nK*K{Rl2hQ%cd;aLwvfn5Wa4MVYW0q4~ra
zB9R&qeJ>$OBcacvL~FcgF&(4PPzw2s=HDRLJ*&y!0dP)}@)ESfYO*#`$Rti<qr`B$
z#!eG_L9;vzYA$M;E<$O7#(}m#Nt)YtFc+6JNw0%T)~suVwiM004v3^`LNkC%)6~z!
zSkg6iGMJ%>;(=spbac%AiiS<KZCRR}wa}8Skx;?TRSgeoar?|1%~^LSy{73{4}76!
zHT_OS8Z~7)i#1CrkWr#huSH*(CYj#!<(k&lpshkPw+DSynhyG?T(#y`st~Ht^i$xb
zR`VTgtLiir<G|h2SgT;SUQ<Hb^#;wC0%*Cd8KO@|*qbzG|H5FJHQy}(qD3=8@wrw_
zS3VGJnrG;%3+<ZdD2R4we#(O6T}|Z|FxaVCP5*PDOXEjzlzW<wr=zi3W1I!jqhZkn
zabLsT4NJY6&nWlwK$F}EodX&M?MVkUi+v&a(60H_6}pEstGdxStO=rx%_GhKR$*oz
zYuYJeII3A`gUFa>*A6s}Yu4<+1WjpTUIN}h`~H6$R;}v_G&*Sy?1N9vT0T9q_iGmf
z!~6m5E9;@tRa@Hza!@<}Ik<L6>oE#|o7SGw0MWzRwWARA)K<5^#1ZW_sy#lcT~P;_
zW7;Z8OnGVl`4|ShwGSvu=A&IS0TF-gXG2gLp!KBa$Z>5T?Q%|N+iA;oQv3NUXbjR8
zoB`mJb`>q;g0){Kf`n@SM**KOt<6q{5W}_e=^c4m`-LmaM`-_g1^7s9=;xTWXzc*K
zMq{)Osjm2p_C<O(p4GNd{pmSvn+3R7?Q<W&wK(l>t6(r*n{gJ67qrE+j=ZQ{MP+*l
z+RZdwm$X+efh22J9EO$@?c~R_E=<+VA(=GoM-(SZ*FLcUotL%mg~P=RtqbLAGPUYl
z_<cqD*}JftrG5EL_>`@kLDA={S|cqqa<p@ALwBzBt#R1R)6V!DefioAn_;0qd%GE0
z3bhxWLSK>AjegK#t&4Vs7FV}+l%j5>TIK_&DbtSCqO)AfxCnfOR<j3)O6~5KVE(#x
zf=Z^Vw5^n?sMaQIfzleS3$4OywFCY?zcB4p`_I1s(4cku7mnW24pZqzqqcc1UcXJ+
z3VJj&YXd27*`jU!6n(8)f69=wX;;4wo$cDo_hIOc_BVg@b!dGlE^t@-k|Rdesr^6(
z(xv@}>Z0yxk5F!*TN{xIK#%s;^Wg4lH`pJ7_G)<ykUs59di(cl%e>(BfL23i8V0p1
z=ymc?`{eKF8`0`$BlSpoZxDljtSzCB6O3w$=yfutT~80<aqa8hVt^A`E5#@$wO$l%
zp3=TeC(ayne&3_dQTJ#krqD^}(_)9i&bkirV!!Ta0z_SOe=E><K=&Sf_{~+<N0;nD
zoku464(ZwraLrA(as~{#>nyak_0Vno0#kBWw`CGIPu<C9q3nn*h_*#Xbv`KcnR!fi
zh=S!_y1!^0=dDZr8#o_bMmjxEeRcchL${x9#uR}5I-wT61?U?4q3yUXmlC@tbosQx
zKB=422)lv09p7ORgLH{3=su-ePAl_Z-J<tlFhp0d4kTQ+jNZkkbv7$3Md$`(un?(x
zm*PE9x-S^e60M8EGsr$OM)xLN0%vp{@4@_8ooqFLvAS$}c%9cxR)ECmdJ(RknV?&H
z9(EIT<=f#*lCHTI+$CMk2XHi5w{s_ODZ21V^rh;I6q!oXtt^1*blo93jdNM|0$m;%
zy43AZmZ_@@0B66VGaW!@mM)+cgUQyNr-#T@-3MAsRF3XYI7D-Gr@jWs(=is{7s=Q4
z(3+`0SH}hZnl5b+9v13k2_Qu}+cIb=);(~5GbOsXK5(TvQ!4;vx{`}<tz1{~EBY#Q
zhbZh*Y1est2$}1;<UL@kbgLL}xLS9bvXC`8JuOOWb+^Jm>U3|?HvfjMe-xH(>Rx0)
zTfOeZ9B>V~V5%*>rAz+@!*105MVIq!-Qg!7(xlr}1q;o(Z@)!fi|&>RT3U7g?14y|
z&ffSed~4VJwGbxm==7AF@6e&94fm1G_%lR1bt^N#b?NTsViNA@)I0#Xb#H4S*`ph$
zyW+m?1RW&n)s@iepiejZ6Bz8*ea%7R1D(s$aBV<0>kwviP-mex)k9tByO12xZMRch
z^04mV(@-;_i=iFksO~+gY8lfF(IQ}6_b+|*WkM(EfVN3p#Fqe0>2gdk;h@*lq0v!a
zK?gOQ^#4=ALudW7^lII&=hcC8(Kj!GqX+cA{|UEU^>6Nn<U#$rlwmxiPcEVds+)e%
zGO+IYea}LvhhDW8<gh;WEx6{Xf0r({Bl<W8cyUx;{a-XxKTNT2Fa6YP5O4k5cu4x_
z$0<7Kt55u|I81+#-Xs2cSFGA+2I%!~U`WUHCaU8)q3>S`$sqk7P84Ga(SPwhT0`}d
z0@w}He=`oH;rdv5n4H#6r%I>@{WPkXjMVR;hhLO_I;}mT_0P?O(ipvsQpacX+X6t&
z>d(sH?>YTA-M+E<rYg97UjMTS%Hs6xzJSN;zo##aT+l~OqXo@H{iQD;lc0~MePg2j
za}n@KdJ}~~FX<cKMPstQk)G};dS7QWrs|s?VrXglxhLUox_%oMfXjN>OW-o}1(YMt
z)W>juyP}s(Lt~aci-OPD`p7kCysBT^1}!=I8xt6WJy(B_&N$@hv#8c2UvF6tzYFwv
zTjB6E{j@J2Q>b6@0q{lo)pIezVtp9x221ozcZihgMK=H_)2Cj;JeTWl7(puZ?|8s&
zrGEHdxOQEi7X(0+zL~a-)%t8c#!{nSFb#dRc6|=5?CbP$I&peKziBx-Z|bkq0bj3w
zo^Im?y<{i)n)U5s7;M#NcfzMO{gvzJYuD$|eRM~^h7Lt^=($hB#9jSPTK{$GpZOjm
z>(cWUfZWqdH$$>t?|2{n4(LCi3x7~=@0$eTq5h>(;79a>l`!#0zlf?@9_xQM!|zdj
z3soeI=?~JOnQ?tPrFkdx%xv^c>MuEgOzG#-Guy%7MpNQwn6nw2lOdS`5zYp;b%5_T
zM7#lmE{0jR(0ITw^a#Y&5Nh{^wu1%-+N~clgwwvl&7h)F=<bG}GojnV5TJ%LhYc}F
z(Cukh^Be$24AF1H#8Jcif6#c$uxTX#UWUsj0QWZBrEIT{A!aceeGOg5p~cS-N0}sl
zL#`Rl1Q>$%qVKpN_apkxQYQ>w)6h;D;wVcUXb6gj!5{<b!0~o5gg%0$V8eo$5D78N
z_D5r=;fV~8FhlPiXbU&E{<pm_{QEh$2*b)m%xI(`={bl*8S3YtG1^e_JygdS;=jc>
z&lpx81vzUtsH6MuoMGV^_#JB)_z_N>H%JRX;tYv87>qZJMgV`o5cUrmFB&c_g3<)T
zoM*r#8eYjlUy{M_C%8+7Mha{v8>VQ%nqoNj8N5g}_}4&7nqi9@CL!J6LP6Y2!{OZ^
zR}2ad`cPz+p;rwx*@j-4nyZHQ4q@~;1}T-q<{Bz!yPRjp`5S%thTYK^MS($c9wOHa
z@4kb^Lc^k0(O6_?kA@e;hR^n5XeEYVD!MN<tf!jpGK2ODxLs~|R|Lrl!+zo_4b$ep
zL;H2Zyp!;)%CP1%*lNSdwLsJuf~Lc6t>H!bu6&)rMui493>&|K!JCFx!XQ#_sAz$j
z2Ez*-ki2D>PD{2%!-IY3yKQiw!%$6z7pR23*`VG6kru;y^w?-M)KF@p&9F8b_S)@+
z&*;^0*HBCA&rSo6iaojv9=JPa-ZMB+Ot{<N`6Wbp44q|g^uA#S6}<Ht+&_m%pCP*d
zbJ1@Q*MoatnD_(SfMN4KNDdl2IMDgfz@sqrkfDtt7Q=>=*PwI6kU}37dStMF^&UhY
z8~#V0jvCx3&OBz=O;M|HLrw~mP8i0PpmEZ$jP^5AhC{Uabud2p5!5&uyNb~0WISgE
z=WOgR!Q}5Zs*KR>VoVr-mIKDFaCqTr^t*<}gT^NwgB&uJhCrvAk!LRg!ri!^VzVB`
z)#*@k*tmx36+DgZRGM?dxMDW&M~z`|uyoA0mjVJ_Mm_~>yp6q!(dc7Ln+49-m`lfc
z{EVxYL1%#R(^9~X8`l~DKVgie1<grg5N$03jn7>M2{Jxl+cE4@#$Ps}GuU{f6^Iby
zg01i^)VS*=8pDhklmG}f)_0@vv@w<fV-d!)lu?Q_CT#<WGOq21PtnGsP7sMPp1J`o
z=Zrz?VK>&e{WvV0H-4K0595r_8XyvHR4hf`1>=*Q|9vRZ*yaio3C8#1Ad_f(n()cS
z?cM;U7(b!|TB*jE#~A2k<F~YZ%rIsb!nI6eHznS$7=!79Hd)4AKXBQ`;xxdo8dIF1
zGsh^)MPIJ*9XW7$#<klZl5ec@1}QM6+@$sAHRB=)Itz{R6%Z{lzCaP)Vq<<ENQu$%
zBt%P%U9`Y2GiEozi*h4t9V9D^#}vR-8uj#Uy>5Ji;#5@_A?#Kghljw`7{g;QzqQ8K
z>CsSURPTl44P)oObQ>A(o&{&GH%|0Hros5)E|6Qs!XOxIH2y>-C%297zJQ5pGPcq-
zuGz?;D#aG#%Kad%#?~A(wi(Y*`mx<OU<bKleDw&-cNnX^0KaP-qnuZ#QMeIWx{Sm0
z{<>$}%!XvQG5%H9>#-YW{0sKJ@k}b5>P0IMeMX-hn8bdg``;iBj0$?f3>f{{81|qs
zZ#5(z8uy*UTnriO=>;-utfj2ch>__DyN`?uU4eUStfO$?sIiEOGsld3=(`%@#?KVc
zGGTm)vWSyLdopdgri{l9!Z!z#ejM7IO`byl?l<+6gSeO?DfDo_^!=}pbTw(_f*dsM
zSc=gfGTl#tHaF8K?Rwo!z4T=BFa`9X@383y8GQ0IUH=G;M@-$c$U18JWj@F;(+5;B
z=4BeOiy`W5I@JRcKBlgPP~&R~q===TX_g}_`J3wKSrlMep90C_raeC3PMFTpqwu7O
zla9tfQ~wO$f=oMUV|~grMP+2crZE#lLQG2fnL<tJ-$5kIG_?de!%ct2!Tf2{f*#uc
zMVRalp)}I8nDRAICVyJWM4K|FfQT{G?nmD_Qx$#GA=Y&3IA->|=^F~`#hG5D>{`5O
zh6ze9n6fx9f6<gn8O{XLqh4@{rsq~+5-yp{A!tlC%{UC#QcR(A#4puU<3s`NG?Vo%
zOk6hQuSRQz>0TWWnI_+BFn`6g?@RP$nd&K5oo$Mva8s_y;V+2fnTlvFk#9Qv7;YDs
zw#0+GX8NzHtI)KSDlv*oW#7W>V$+*D;ctm)oIa*fYT9-Q@G_I5l0KqTZVJ)^SYdj-
zA8IO1b9q2qH+}K|_$t$u79grk&rqhn#&qp8xLVVT3*cIv>G)QR@P_FVs=B>tx=hDD
z>P_J^7Y!yi6S!NZ@*&_FP5-0J&TZ3E5;QiMmOc-z*`%j48TJ;F*PoDSGa&_q`^dCq
zAIM#kt`NFAP47}gQkUuJ1|aU4{Al0WZ8}2n#~xD=m9gD7m8}EUYpSA(vp!SeECBjV
z?pg5Sf$5K8412(|`)N$<kf}QjBEzP!W+)pm&8PLnBfBY+3H)PIHci5)$r=jLG1JsZ
z%*D9r7!`s{n2J6CaMDzI9*$0#KBkb8gL&Gk;GE2YxiIK#UNR5Q<^5(M3qHA+U-|`r
z1Loh4!i1~&Xe=xoHUIE6$T4#URk(SXuh8KFZ?k<v6Ab#8SG2&quX()+x&zFAQ4;pJ
zxp@ls6Xv80ICIkc#rrTAXg>HGB!kQ!(KohEnc0-S4>r5d8LkksnUad3=Jm7|2s6L>
z2wb?i6iJ+!r_H?;&>3OAF^0xSGn;~Z@#cK{JOD44{S`2gV2<j+U=q#h05m3<Gbz)5
z$^4rUB-wm{2a;m`@fS#@n)kg8rD^6(_c4lebJ{3$UpC)~gGh#XQ77P;W~mV(SIh?}
zte0gTrU+iP`F#q)UNukrm$oqbchOTb*Bn2E!Q`1=p`}Q^nMWsX3(Ub33BP7mk=;Ub
z-w3!O^Qa&2#pdts!Tl0*#(CH+HLK=AcbPekQn}^kyB`2hVb)VFrP3Tuj$Su=PKOs&
z=5~7MR-3zLps&Upzmon@K&|;8c~fT|G^6!~c{*)&ZklJPAzE)v`4Ei_=3Lq~-!_-h
z>aNMWpQ?SE%}+*xw3zEt0B<$t1j4m8^UNh6?dJA+G~O|{UxG6o=0SHf-ZlR(3NzDb
z?x!VNmw6P=8T-t8W)BrQyUq7zp|i)_Nfng$%`Yfnu-9B$4}*Q?J|UdxH~&j{%LnG^
z-+~)3@8#p_95nB}0Fj60hhtDWWPa@oaKq-!l$sbZZwW)+BlEUTfqQIj{s@3kv#=9W
zGG^|53jq7L*(U(zC(LiJK<A|SChZ}n%vb*f(7|$n>g^mYJ?Y?_EI))m#Mv@J$)^35
zJW6!9SepKX$N|eME|?2f%P8f_+$`D`!MR&5_rePg%h~<F9k!Hb1LtWuOOO5|mZP+3
zKWewURu6;6ESwD>UX~-2EBChSJphD{Wo#1~eJxE?xaMa`pu&28%lZ{C5nvglB8KCZ
z+-(@l3CrVV08Uy8<RF2TUG&=rS>}}ie#+wTF(iX6W=i;lSXz9bCDgL*3Pi#z_7n@W
zg<DqL0PwWs`DKuau=G&0I@0oP6&#MTM22Fzqb;A%@;Aov8AXWBSUM?Je%3OFz9o3h
z(zY93#99*R5qjS8&SIE|v)rkM>Uc|i4a{G#uqjD((W1PF#smwCmOzP?jdrSqNV1%y
zkk}<lGi?x(EixHMilty75UCauHKtkSu7qppmd~hQ;IidMTC!zWnsmTrT8imJ^%V<;
zLY-Nbo~>{u+w$Umz^_`?z6J9+mLgjI=33I}-I!<D{06k-Tf~1*Lbt&3j}E%8SvLO+
zuFw*97otU$z?;xkZ24Lb-6fW!|30u}IYNu+3QHgTKlCb#;v!5`TeefdPK||2xu04~
zz6=KIEQgz+^M<AUCFs0q3Hb?H>MgQq;2JDF7h&O+Wrvo|KsQ?Y={Uq~OXV13nk=X3
zVbW}oyoi}?vFKBwrqwb)pK58di2g=nyXAR`65O$@--W?+SO%To#a+uQufmH?%XgLF
zx-2*T0pOnHrE4JFmZ(=idMsWo@bJFHuL4?nE%ztsA9eIuPQ=4tzvce#u=K$4G8OL*
zSh56ganQ1ezM1mSvZe=?hAhw1znmSmJW2&OVhNps(nppzRssIlGPx0wqm~RRf*rHW
zxdD-J%Q6GBOjzEckkX`O^f3TamPXp4I#^$S7m{{IYi=+6cCz~K#F$*HzElczz^amf
zxLUJ!L-e4vcNl$#tbbCh(arh}ZQu@DqiI#>X?;2tZXdCJJP!abYd38=ysf7{LZ6TI
zx$iNfzE)-x`uwc%3`qK0SJ$EMg!K<v{+_g3-QPuLpw)>UA3@eW3a6a1PWuHU*cxR4
zBE;I=2hmXLPFhZeS(nlSJ=~g1_vUHqqkl292&?6Hh(uarHbErHn*0<RqpdGd$UnyF
zOr^MIte<_2DLHHXp7NCEto3TlTCCNsVqr?pTb<}0i?g<rL3g}$`WiG|u>Qt_wu@Hh
zFpvc6_AWS+XicTvQIfU!JzQm%tXcRCXC_;B&|5Uc8bAT6RO`}X5J|H>>jGuzRxQQM
zFI)H0IxxdpT7hw9T35Y+#w*q)`*T2KSxa65$+q${;P6%Jt{*^htbfwOB-dI@kF-4N
zj5IXnTc;MnwF2w0r5MvS>sgAl7Fu7L2``GQ-#EfVv32EtApol@MV3mf<y5UyX8n?G
zhjMErh5jn6BkzM$TI;4!#O1p6Kr1?{th>CxRa<x60<gxKGXbTw)@@hOSZB>#1@4CR
zW;^<BT7RP>F!k1#=?ZMHPM-xYZdtF;ecxyejE39IRvuNVwOFlG^3iI|;{exY^{2pe
zyH!Zfz&lpgLAw7stWVCzWZbnrK|e*O)l9m(tRbUNbI)p^NNcw>k5)82R)YoF?prJW
zgtlJma3QqyS(j6MyWe_|>en7v{r|*t4Op-Dfec#bQiaY#>%d)bL)KI;hzwg-t^{tx
zI*hlHedZ&psRyHfY+YCiGHQL90-s~n1}b77xBfC6UQAfa>0+I<nrqNEWi6z&kAv;$
zS@6lx7P|zJPBsPQ(VT7jF2S|^HVeHLTx_myz_kOmp{?-3)fO`g$`0C|ya)Ipn`Juy
zb~oGFJaoF-b_?N@hiwl<%?{fZ?*s9)^-{gf5t|<+z>nIVdI7*=wtI2lylki6fF*C+
zzZ8q|v0b_hZN9eFr_twUn>hiy{<dx7Fc@H){x_UCZtG3KB%H8)Lr;j4wkNf~1=?*3
z>7^QEduIpOQ?|61AQNoc_7$87u^pd*UnJD#eH(}{Tk%Dx3Ag!E-Y?QtL(z>WThLNS
zM%!{}4{+A@)phipvwgV|B-WNm&%k(_hTiNKY`;^?;G)f$BEtzb-&a8rZT1r{!9<en
zuX(_y*jnGiC{k^o`hld`VwS>Sy6rjI16;N}Bf@wyY|gX*%(Qh=8OjygI!gOz*)r()
znr$oC24}9?KA}419NUNhlDW1gC<l~h<I_Gj-^QZgWP#0(qQ2K`PWBvh7TT&;f)v><
zwE<sj+ez=%65AqAG?v;dl+-A*F&3e*+}67jb}MZ44>9^mTNVW;uiGT=!;320&~7+d
zZJTiueKod@aQItmTS^h0I$IW<QNLm9p~T%y+l?;)sJFfN4Apox{GX%ij?23G{#uz<
zW?yrp4J(^knx<)`mfAAg$+P#~`@yC?fG8Uk*@%LG;6MRcB8Y-40a28pECG?F4A}zm
zd!OH5=XLKr?{m(*&*yW;Ip=;JCkbt@>YXz40c>#cr?7IP)ASIKCZ|*MT-|Xhk4Iap
z(~)`r?mC%hZESN2UIl6QoR;!H+MVuPfQ21SCl-LS)5$^~yy$Y0k&Cq3sg#0(_ni*Y
zto6W27zEPe^vR}Y@&5HX{qQ3YeNJbpVQ|0Gtz77R=%kB*rU9ove+TQJle-J>Lrz9&
z8+O`B?%NTkV?pTssFR-v@G+-f=tkHhr->o7jXN2RVVozNJXV5CIvJP{{n%+SWo5ZC
z>W9GT#@O0T`_J8sOTR<*UdH;50Q6wI$AM5!#>x{wcri*=L$){LISPXMF!sC!ye}h>
zHa32Y5(8NL8Etd|+Q;~L8SLH9SVDon1B^wKZ5Y7##uGpDL58jnq5~Oswn0%4qh==B
zf*Gu9sC0xd-n#@E%2+^Cco?IbZo7mt{#%X8NXEHep#Ct!oi6$xVeFy&q$oyr6j-7e
zN;*3nWwdWY4`Ub`!(m}8LrCe{ag5?-upDEQtwu-V8K(b%C4u2W`6tI2Gb!Qv1S9MV
zz)w0D8|ik>DaKCPh9)vD(|+zW<GCIn&M@95zd{m&?+Ig)85Z*Gq%iU*Rpl&W4JCJ_
zGQQjmmNdrVo4}<rR?k2wgAuhJ#$+<MWvD#I_<*vEvlxvu*Pmw;QXnjwagj24a~O_K
z^1yR}G4}<i&t?2Tk++MC1@s_aVu&uH7kP}cG;icHI#M9!G6UbL#OuVkM+d(`MwmN{
zDPnwl2c=?$a1g>u7^g-d`wC;k8*Sx`8uBP#V`NrB=5@w}&tPFC!;@Bk8;lbUHvn%k
z^6gMj#W-t4Z8hWlLqOCpUj7c1wTxg|8*ec}zCl|(LqvO+2F4W~df3Q#n<A@CjF@$(
zyu(;d4vc2T-m~CrVZ0pxmR3fWH!ANkUVIvyZH!mw4s!=%+6Megos4IW)BdxI(fczH
z4;X*tqp^qa^GT@hWfalW@{sZIb^r$$)@2}r48s<1jxeezC3ckY=K_csV^ot*X@U_{
zhPFute-X%IhG!gvxiY(5(B{VMu7EMSnPD?g+RJpK&8!FWhl|hP{qtn5uEmi0FssS4
z<;&c)0wq7DbTJg}XRfM*m;+4XS5O$h{9!BFf|%u$a~RD0d;_F~Fu$hRHk>&`7iS}w
zZ*PF?Lrg8DuN`4po&bqr9-~Jmn(1o;XDsu36H0N+cm%K=GmbGAk^l5KvvncxCz$F;
z{AwqeQSYG_r<sLxA?6HoRt8K<Vh%^ZrnAgVr(shn^GTY?)0po`0mx+fFGSlp=FeY(
zWHHm|@<<M|vK_b!%xh;LESKqb4;u2A;!KqCnYonz<+#i|Nn5@m=Aa(76*CVXgE1w{
z$4kId#*E(x^;JwZg?p-*Mw;bon4xrpsbxAJ1MU{{5qXX4nYmKvZD2Z+yQ`78?gju&
z%vBU9xx-Y@9ld7eiTN<Jg?XQxGObK^+C$uRFs;{tZ)29lLj65vV<bxLOgD;abu!Pi
zq145k_yernOi%i=iTlicJA^)9j+8)JFLMzOz35{GQbI>R^Ts%2KV)vCbLRl_FCSD6
zG7tX*+z68u05Zx{J&(#Urksx16HLd^3t*jO-iU$1$IM+T(F+$==|k|ivZ~3U;KuU!
z4_54E1yPvDoi&HTh<jPJFN4K{l{5i`o~#V&p%-gIE`)ir22|*a59<#3qI_9zMZjJ^
z)|+bp_h%&}LFPV|KPCU{XU+c71Tzk>-k~c10j!kYpy?pXCIK*zg%7>sVPkFh0Ib2R
z*Q=p7gtcxjNGL0YqMu=`7el76o<84kb{e{Ng!NH5$Wa!D9Ii2}jE}(?%UZ#QY4NNq
z9z-XwavRZhoOSRV;HOvzS3r9rYY91OPqW$uFguy`5(|c=uzH)&c9u0puJd$O(7OO+
zu-@T7N+xR>O*iLRzmRt?oAs?D1&AEh+C|{G$P$t#?h<Rye=sJG)$D=36tIqvKd+F*
zr1`vv6}u3e#jM-(|KKI8PhLRf71l#~VM|#{DJ7tc_1!`M%2^9@q3J4X?uTHhU=@82
zVb@s2I#^N38rqAt8?2fNa^l`()sXk7ik0aEQq6ir0M;5-uNuHw*1cG;-e!##LueiA
zKl;*HJ?q&Bj70<MHpM#{SpxFlHL?Dn!`U5HlnjH{%)0$EjA>z=dk77!tWug8?y~MB
zqq2?Fa2TY6)%XD=@pQ6^Z2)$$O5M=y2dqF7^!Bi})3V>oilDswK33=-(A&?twh81R
z>jTP98esjn8Mr}K<XWg0V$HLla+p;^`8p%4xeAa`R#iO680!bhntQ~0FC3+D*0L9&
zeu7o|A_XxgS$_?{w#TgU5|AlYnh{-dVTZawy(^nF147-{S7=Jw&CaLjm^=GEeR6LP
zd+u{EbT3=RK${2K`!xvlWWPthj~Dw5x{u?{eqR7iANEIdY0Q^B^B-8@$9AE3y+7Md
z%a~&y`_*(b?q?gOp`!=bF`Hmw0DHp<4Cz7kmSOM&vIDOH5yVcT{FPw#_GE|&VZTkG
z#ZdNU3Y3JgzyAsFaJKUR^hU6sJOe3**heYdCz5@y0G&9@*0_NjVaL&n8pWP0huUZd
zTk`{Yag;6F1)(u)6`f^c*=OmX8^<oWg3>W|_HI}a&z{SJiUjsYG*2C8FQO&#1pApt
zC_KqF(Fx`h`{Ju8C9*H=0Q@wYLDwbEu-z%yFNs}4D|<5gT{WbnuzhI7ILmh2`xM1g
zcJDPbX0RJ+Imu+F<b#}J&!)8eEcPs#WzVyZcfkB?wig+i!+vfiWM5zlzd%QG+0{(+
z=_317Cpa&$t3zRL9y^#0xcTgjba=kZR?P!T0Xw!8QVQA4!+;mDdmNPJRLpK8FHi|P
zX9c8PVONL%EM?!J6!<ds87Huovs=<YuCjO1o$CtrEMIV5V<&4N^g7$E1b|BRH2NiP
zu!FT2i<|5?I(SvFzj}nqYIYqRaBJ8Duc1`SPNom~++q*zppDIK_H72F)v-5_cfX!}
zcqcS9u!9f6raNqPAXu8&?^E2Ph5gf6u(Yy2e*$fH*-KiXqK*AIMe6Udizz_U&R)3#
zoE_|WKccOZy?YOYb+PwVpt762*@VjbY#)l7KVa{hPlwnZwl94bsF%H-A}oFETVJ40
z{p^mbV13Bu?T6h1>=KHF4zi2yV@QVB$0DG9nEeNBc1GB*Jp*Z@>~u=$8DmQ+c>0Ll
zrv@2k{~Uz23HIv;fSY7{I3V*e`&k*t6#M0ybdl7BqoyCvm2*4=csI_mD**21?DYh~
zo$~^v=kDP&Qp8~|XJ9cZJvhTJ0Po4kq=17LXW=zi=*>Cd3b+qvs0VOgPUsB){5bzM
zfYYB7Nm+vXIOR-K?&lPR;ORQRc`yf@jsVX0pQ3n>Q}!MD6v$~S22T*@HM%1k%=y$6
z_z+GZ9dJWAzh8u*VVuXGV=Tfsi$Y*b1V`EemP4EwX)rXBGmWCAhdEMm<{aU?KuJ7N
zoJTppMRUHRAjnb9+Y*#wIC*BU#5y>d4?yEM7gC_&7^jyK&*C`?SRf}jACP<QB<Cs0
zOg+W%rY}>S;c(WYGfA9(*1_In&NkW{W^$^!!E&B6Ob*X%&RjZI<Z$v!K`wB9{T`LM
zoY*ZO7da;+ka>yoHaU&+I1YvYG@q0B6i5MQJ|(;ra$FlBw1~5Sk_d`9Z>~dI2`6wS
z@K-ns|AG24PVO3TmUE(A(Zj2p>GNQ31?SU+;Jn817)I$jr-CA}l^it%Gj4D?PNSbU
zIh!t`t%`HU2^y+75soxStKpo<0&6Yj$q%9M7N^1qow?1qL3yKfoUR>EQP0^zKWqc1
zybGm9&f3M0*2Fm*j?x{@xqb+3=FB0da|_2rSqH70R*IP4<-B_dn%X#9Xs>jS(;J9V
zJEu4nxDL+VQ?!Zh<ZSyD#rvEc6g+(Z6T#ZUdGrvZm($q<)A~3k$=lq|>Hi$ve#ogh
z55NE?_&opyIr;Q4&>@br3YEhgi9Y}%oH;vS(<tYn5~VRtc{h6Yh_iwNz&MBd9V#a{
z&0`cqndDrJho;AzS<xU<oR10b!u|UXDBR7hrU-{S_iy^z)gG>uR`I>u-5b#6!40Lq
z1oz|ykwe>y`<Ny;Z?2e+-urMb{Q^zC+|hIh^W(m;3B;c(Py@G*d)gO@_H*YU^#Zp-
zxJ%XmAHaR%4ImD3UwRUn0=fN^^c%!oMrZ$EZVbH~A>6<J0Wg&Ny%PXoT;~~R3+Ikq
zhtLRa*fz8s;?~eXB$E3xIq9Rgoiz{^&3)A!ZAZC}9sv-?4fX^%#$7_U2^{g<+EM)4
zC%9kbf#)Rmt$hHV;(j^;g=e@veW*<0K3#-TGWWMaSeVM~t^^>Bdx3Vy>D>5_p(2wz
z@HNOe?$M2aXK`1HpyE7t?n~gz=DzVOq+H;7|AMw$?tF>|U*rz{jZWk_xUS??$>&Ds
z!Fri%qTjcG>r6>8h1?MOxr(_(b5L2r-F6lRU*W2vp|_0NL0^<B=lZIFyULwQJIxC2
zW<7*n<4#d9u#)@PI5=-`T_^~7le=ja)K_tTqMV6p?qVBoHC#uR4k~VQU!*jaI_?#k
zg6p~edlNrw1NZ3{ptq4bht4cb+~srxxx;<y4u0Qe?gILLXA5_db}L=npK0gT&6Sde
z^*&cf*TWugPf$drhkN8nSkcFwM`>^UT<vQpJ><Sg*MA1NC63#`k8n31LE|Vll-A}k
z?mOFI=_9UcI)sjM|ENOS1or?P(<iwlOQHTTS4WwmQ`|VpOmN|i(!=J;`-%x+ZoD<S
zP}<95(;DT$%Wy-bCvRRQWP0&r<cjj<?LJEnDeq1zCGq(3=6?Wd{CK~Um)xJXKOci|
zkT>lUkU-vB@1vtZysoDpEtt2T;<F*V)$afo%KK&(WQXzIqLV~8uYh8x5xhD&DMs-Q
z(iSF~cZ30Ql()GNorvN6Mf<T>p7kC?$MNQS(E4|bx2q2-;(3qkAPKx@`=BY2*H5vO
z)4YNAVcHp9$j{J}#4Fqby~(@{W(;BquZgbFo#lO22V5$zauPz*c*3`#Fq2pNCN!Pn
z<$eH?#mg*5+j*XDC!}Qa9yvow4)2bb-oFdH_+#M7<z1lL2p4(f1CVx!x1N##@_4g8
zLt8%Yg=c{;=6y>p;SyfT5#X=z)OXR}Qr<r+(cdy&;V!V0^WLJF=_+qv12k3e{#^%|
z*Ld3oAgqelz6HXnd0KKJ)$pFDeW0V3w}GzV-QuN?3;Q<jDN0eR<N3`2zMi-33G}{!
z_oxqIT6oLV(A3K7q9FBM-j^pKt&OMX2D!&Oq62B?aVSx)gV*B>(#d;r0xG(AtrXht
z<$bjim3=%jMKAk#vJO-}bnuwukQ?B2PQdO#-ZI+a4)IP?mi{n$0W!jSOy972#A|#F
zrE#9}9?YNM4N;VLl9x@Vz{kAx<R6>jU83Nc3qOK<l&*X`MLpg4uTh9@H~(EdM7#52
zd_nf`b(Emv&3BZfq3FYZcN*}%{1hWt{rK-+M590d*=NwFef+I7`R(WbR1Jd<@IRdg
z^#S}*E&w6?wH06q<@?g)6~^~I2Vvp-tFZt?@Ta>&{UN@EoKKN_7M%zV^K*Qm;Rye-
zGo-}wa~<^P#qnQu206xGPLEzZzluC@3H)#F0e_tDq69g?_o7eRpX5Jv4AM^Ved($}
zGQX7W-KX$Plu>(@AF&RVseBb(rcL8deGY}`d}s1iWbk7Jkdnzy2!QBw{8Vz>XY<D^
zY5$qSpFIucU*ONAt#vM6LYGG_@}F#gm`i;2C0LrrH}Rk%pN|{Im?rt3-2$M1Z}|v-
zLVna$$S&e{(6x;+{%vPemh-Lj5u2<0;LicC;CJtaqHFvK+E`rY2T+u^l0Ojs%*&V{
z`OmjOXf6LsTK{hG<0+_qo39VqzZvIq%S==@@>8@hriq_}xW|mU{2k;jZsTuFMddwy
zem*^V{PJ%=I{5Zd06O_E(5|D4A6^Y%-TZgBAbtGj@8UV`=P#oD<3m1|u6qpdZ|X5X
zgZy$fY#QP}^nvxm{28=s7~#L?Xor|b`~>pwjPu7BAQSwB6abjydywnyF+X)L#7yza
z>A>hAIGYX?o&x`D;JpM#DJbAAXrp`CK7u&<K#i~9^H2~!!Riap>o54X2b}u^yUs(=
zenCwaN(TfB7C=#eU|$(I*$)c5(qUVm;Eh=*1qqfHp)o`-pVrn;!I8@l6DC-;A9jZe
zc;o_z5VX)k9w|7x94v<gGbnHEh#=xOa7GIjKY;q9f<QTB#t1f(gEm$$i!K4i38KCP
zNe~=$0`9mVVeM?pk0%6!w9uav1pfnaN^rguh(tl#2M~H%prS4L8NuW+kR(AF&Dkk}
z>9j{YD|i$Kk}8;516-QmHF9;N3&fv+WC%Wf8ExkTdHX@K1bMN5pBMaE1ku@o*G&+e
zBUlSZ0_I1-1|G&aS8)4TjO9hagH|+N5{wvu$P?_ofXaNqpR^8L7W__01O<XDdVmWB
zGCB<w39@OCC>GoxXKIPyzihy-2#UxLUn+2V3b-=CV#*CG7d-bZtiLLFg0?pmf>|F!
znB$t@IxXKf1oae<x+z%L0brGYK}kT>f*yKgYXqNB=&4pvu@yGm7C29#txk|IhK|+?
zuF;{cK@h(UERBN2bkb`QtW1Z@W`TqbP%VOEpMbMfP%?&6n_%=D6x|bes8QMO5Co7L
zr$g`s-Nft^{85d@E<t!GdeJRdxCJ~91TRspagSjA1p3=62(N<rKEXRQQS=Med4pv@
z5KCL*LBXDnK!yYnbzm75On)B=M+6G`?MDU0KSRT~;Hnb12|=m{aFYUuYcuF$L4pKi
zN>CmHyo->t2_;wIi%BrXO}OVO5W9sUauB-<y=aZwBkapZX|M43i})!#gsE=>;3>?a
z!S@m>$Yba&Tu#nZAK}-uwE7CS=`b>W!rAjd{Dn><=*vD~lY`>P`-KH*(0f3bMH#9A
z!e%YR928zifx&^ogym2XB)mwzw_xFd7zhm!iWIOZR2cOqdKf0`cpE(o7kc(Uc7!mP
z^6C!>oBx88NMXblki$Y3+&G$XM0oiB_pQQFEdbHNwWZ`AJ1X4xFN!h3C|ZYNg*tjz
z<Agt$(8FWGFmf};3)OTV^n`F|GgO=uuA(#ADd89ovJ-`!{*ZlI*hDAWGs4#?>XIb9
zEJI(Cg?Ex6B}M2<+qttsJ|$qK3V+apGfnuyOEcHwl@WeGUk}a@uBLRoOkp!^^3Dkp
zPGi`zgrYY=&I>!p-IXnzJpwT~!v2tu>)+s$3o81#E(zz-86;0Q{Y$Xs3lqM@&|DT?
zB=<sraBDp(3x%^=P+25=#Raw%3p40z10}+E+QD5BeoK>Qsjz1;dQm2n%fV7EH2nsJ
z*MzQokn6(Tzrf&1p@#m;;)XEqd61jJ3de4+RtasBAl1To6hy5N{z_l=uN7wg44zv;
z)AOjjEj;iJ2C+^ULU*F-h2_5k&>*zaEZ-;`rM+I0aQUa`%N^nS^o_A*;n7Wiw+MUA
zqpejqOaZ^U!cXa$YZETYL*+f8%Pa?2+l97%G<FHsT|}u{_$npE+!vlSg6DxSJrqKF
zgzLg!MW66z+EVlj*DgTiLt!Ny-Uo!UJ_3ADc=$zhbV#^rBczN7LpP!mqr&btVBwfh
z{2Evu32&2^VO-edhsp`zn`+8XeJtEVk*F!*bA0sBMf6)7h?{7U7ZAHe|2m=ME?Q2r
z*B()B0XX-H4rKuEDVp8};w91#!(MOETJoIuh(3D-Hu;L`)`R$otObDY6ID_?dB5mm
z8@hBrw0S8i14I(6{*D<3MJwou3KVrxx_hulN4}vD(UDCM8Y(&@MQ09)TIs|XDO&h9
zDi4d~4FDVw-B5u<i9VoP6h}qd>1Z1xIx_;<u_D`T2#XW_O?#$eqF*~v887<w4B!bO
zGc89aL>yX$9VbQBhY)j0w1#$fiK1V(pz*Y*IuZCJ(F^ZjoRdX9pP_3hqV3etvmzG{
z08&L!o*0re(JPchkS=<(8!YEU>2yxc5+zbZ_Ppo{d113f4PxMOM6(7^$`!?mVbeuX
z`R5>)93ln%zIh`5kDxGL6iEpkmql}1&{!yHrkArww4PqvV$s(W%qS7LQPB2^sDTZI
zrJ~j3CNCF_(_3*>)V~|03X#)Ul&*{JI)kNBl=L1(^oGbrSt&O~=gC)5CEB(Mr5cgr
z(sa;TQ6`0lZ;6(y0=X?pqBCBd=ouRPdeK%ZjA<0@?1k(m(UWdyyCb?zi)ypzQ<{5Q
zMB_h#vsLswIVamhQxu!HC+bi@eY@y;^1XG7ynYAnzDV#Ma1TT*6|CqH&2-QOkzSGe
zOc>lR8Y+jhha&5C@C=By?*|za2`)j*kZ2ZtB4${mZUW1Qh)oX2F_E7TxJRPrzk_Mx
zqO=Vl6QbpGQ({uIj_zAbiQX2&CKqwSJy_@}9{2%PxQXw-j?!-N-wkxQa~HQ$*6kj#
zG7*iQ;%}0m!b@Cn2t3|m2JI|-#Lnwc@)al3vDZ($cse-!#oOsV+&=LuYtV`P;y{Yc
z9}xdo4buX|(`YI@DE55<ZGqxnYQY&Kc8P_eU@?yz7$M^Lx9EmcsQA}$NDC8-DBUPr
z9Q`W9M2IWjgu+AOC~{jxir1V1;;@)6L+Ob44~lL_iKT@YnP~B@4742;4{wHw81bK!
z5EU!_=}8ES6F)<Hu4Ce#D2*jv%=!_P3F76405~rG^zCVQ|4xX1r>OWz@!u6-JtbaD
zuYaO=9__+Ui?7n|;fz>8k?SOJ^LtR3ES6{iND+TYal^CXeP4nzRoqJsstmE)DF8CX
zIi65)PJEJH?QHSW6e!6NbLc0$Aa1A9C2>0CIy&;imFGb7#Z$D4E)-j6#Visx_Cjc}
z_#)-Tl#2W4f=QWp`$niJ7vG{S?ltj_H7H#dJN5uxDfXH~539uQ(($HRT%CzhjrjOq
zfZrC!CxE3+tXL0HFD}~xmL~BGieuk#h=1WiTC;co-8XI#4^S+pRh+p63h#;sxafA9
zc;QE2xhMAi6c)CNC%Yh~L;Nr8y*kD1)nMrsA4`J0_r)J?N9lpsm;7Tr;zQ(t?-grl
z$><jc_yG4%JogJI8W8J0gv>#)!<{~VF(kJ2!<u2SQxqCU#It{cv{5nVTU3sTt%YED
zB;KA5o5sa1PeAsBc$}W~NpS;(Z61rwH^4b1-gAhabxG1Gu((Q6%@F1$X_^Ad9?45N
zP`Fp}*Eo9bA^C)Mex8yL$83o4lDtRhw%(F&4}#T4a-|WhzLIgep6xH$NBgpUl4r>!
zwqNoN51I~08rPsLK(c~f<AahW3atc6s_ugXNeuMDhe{51qAg5vhW0Swl3UNgrbx+3
zT8<7&zMy>KBN9z7tr=00sUk>=mb^j_MvNqE8A`E|o#dg4lW-DIIwpCJ3EA<Ia1N|U
zkQC>jbX>Arj~<?oyg=ULlaie@gP)RUUWTSLiH>IJbjgJnv}H(Yy&xr1^6S&Uos;Nx
zKuVTGvX^d1otH=!LQ}S6866&SBw5d)bU{*74cWO8pAe9Xl3m#lb4l_exoYwxH@4#!
z&6kAIY<pR<f|Ae+B<?;?UnuF@1(qVoE586&Eb*e8!xG8l8z^0oaNB?@m291WhB66j
zl-|E`Nku4XuSzaZ)=`B-SP#3eNuHulW?q-1Qp#kdghQEqRg&7(&{QoMqY0`;Quz|b
z`L-mN93XWP&uU1imvr9)XM^M?3e`1Acr}1GNw68k!!3D8d04HI4oYmeD=B*k`W$VN
z%H?3aCwaXS_;$$_8jB9eN;(sFN^Vbs>@G<tojSTDZS*?bmlPa>`UjH7e?nT1WcfU_
z^-BJnkG4L^Qu2!QOU{$`>Y?Ock~tvBPJ@&|NkSVG4oSAu!kA&n$Kz-laY+0r#yBbo
zqOJXy<m5}JeI)t%Gmvpfk_DP3Bv<x;OiEH-Mb{onKK=n@O43TXEiTeu=mRLO(wU7g
z+fDi*IU9CMx6=ITF1<4cHtmsar&n#S)NmboJ)~FvgcY9BOnSGxqz<zktlrXx{ZQc}
zeRDr*eWhBu0pKUSdKc3Cr5~tZ%mJw{xs3y)@9DsDP<nPFSOTS;d9Wf#YM@wourwtY
zvO}ch6x|M$et#VBFzJ>?REA4$Q;u_lbaoo-JtWnAi^@o;ucHh+hovoNq5g=JLt(@y
zX>BR+(Nb?(sgFt%DVZQfy8dY>jFpCELrk1>)=$94OV3<{O$pL{H0K|e{`NdrPDroO
zC7YAd%gHDuN<XJ?_-U!@2moiKkIMi^kq%2>?^)@xZgQ@qO83w&nkLN;M=4!uPldt^
z=?;pZWlA^F!Q`CuISRFBNl(z-it|!eBLLab3A%fhBV}wr>4G%ibEwFbt|l-0MQQa?
zv|W<^Nv`)i=|)Pc%9n=IyLnmqD@A(?q`_mf{uN3;%SLUHluOHgv2=>OP$kkA+X1{H
zwFiQ=RLVaMW6GpViiMU-7u<o0tJ0wu=&g_*reoDLshIALU6;Q9JaCoLO4@JVkp4*C
z`J2+=cC=MVo9U|owbGU3W4R>_hhN(<<F?c;L)Yr0<^j~!OJ~zl+8|v{j<rVVm*0al
zNz+-VydyQy{-jy@)-*_Kkyg^a=&sbV8C`3WmM#M4J?RI>A*@Gw{W3_e^dkyS^+|Kc
zozgFjpo^6crQvjwY(SbyoQ^^1Lvo1?Nmr4}a#$)9fs9CJ(L6aOtv-XXcqAQ^L+`jW
z>NZqNNDD(zIVn9)ext|I*FJ;nDQV<<NO6^|qoa?Tte@to-LkLfIJH-navz#JWVe1q
zrKilP6(uhjcNI$B4%zR2fcnVhbip=X+2(Ih@{@7sY4MkN&?$JIER#Mda6q>0Ak+uQ
z(h9+HP^Ns0UIfbK(WTlT+1g&{4VKNygOm_i#xke~lgTLJ7cP6E3GfJ6DCH>}l70Or
z%#M^T=YZvi%rTwPQlezNbO1Xlv(iQ^MmB@KL=r1oJ&v|`*`>X}C&=WK-+NrPmE034
zGSB1CbXHbV30$h|%Wq&sn(Q2{l<BhlTcI~Y7ESYNmhAH?n0;Qho_t{0vZ1-a<;ZfI
zp#Fla&fx-Ua%EO`=)EX=+6WbwWZNhuC{On8)2Pgs&8NNmW!d(*P*EUjd<}piS?db4
z70VKqfU`uF^AM#gvH~esN@dy`u<)wv5Je0sWY=av<~7-W?P$9$`*JIURmxtbG^HCd
zAM_uOr!1O|kySFI5x{EMJlX=)$jrqsxK>s{u8Ui;f`=ftWd|uXSto0wtw_D>&LqS%
z$YLJ@*C<m6K$>Jv(qZL}toH)inq>kpgtf>PpG1FKWv6JXcvsdv0eG9tzlAbX@5vU>
z3AbIACxGk@nVJutPT9s5i0P6Y{0OFX%TCg~abGs=0ZI>KCumFFBRjtYoV~KHF0}Q@
zCO(1se%aTQefLmirJ(PCtnW!!F(`Zf3IId0FP4IHSXN8lTN{xv{vqetsBA$Pies_`
z8=?M@EIkN3<Fdeg7`6#nK4lM0%GPH>_G8%<IwnlXMrT5ri`<rtHaB@UId1mIlm7#5
zue^(P79MgL`CUEbb$<irC4Vyk!o203*TCW<-`NI$uRNIirVc;3q7&-<<;oyP+b4gj
z8a(^uZ+fBefPCx?kO28nT4WB&`^o1RA>T|t(;@j=&ww*h-bl9}56hRO0)9k(@iN+?
z<j)>JU!vvX<WxN>e}-bPG4d0OVOp&G87HvB$tNh>ddwlurq@4S?nxg*Opq5)4#jb~
z)89axkl&nwr6=W8w9!5#7ty`JMEPVU^q!W#@eN96<o0%OCdpf8Kw7f=H`>Rg$PY_U
zc~;&_d3vexOM$R3O<vvvk}m&<zKND0Pf7>LlsnFdAnly|@?uEKl6Mp9dAaroO4;&-
zksvwpQ#6HNkdH2f&|LWtB{p4@my<8-l023YvGU~aP=q93{=fI3@Ur}mJzy!22ZW$Y
zh4L~XIE&>2OYrEF$kXWQx+32vgxXTM)IqoM%H$uD!R7MNEkInAuaH1mg<Kzm%4_m+
znwhT4*|aCFlz;RqDsRXS(7Jn5{w;YYYUD8#l&_V4N^Xf;@+NZT-j?5A2`P2*kCVYt
zFMmwets3NAbW&`TZ}JCcll-si<h;Hk_nryTEa$uq*)8&S$Rpk=&prm=UHQ;vl-lG9
z^1s}ZFQK2JUB2Qd#B|8-27#qhe*Hz5-6dap8B)6CtA9t^eR--J<bgbyys$m;u&sdi
z%9ALv+9$84oo2tBlSKZPhjLePOAg2j=#?3iyZ!+(B#%;KpoZn)e}Ih0KMMeGRDNJ1
zILG8U9nkwo{<a)sT&|?-$O(B1U4opH&l(1KEI&lazEkr0A+)(DKK=@(?N)3q2Ebi$
ztsGMJC<2k3vT=r|VkWtNy%Z}Op~+ieegZ&0g@Os<uMpBBv`-;rz^45QOsIG(6n&JH
z8K7W?{KdgH#+bD83sIDBhLljn09{`SQ*h|!X}DrR1^^L?xiqaGQv5<m)scz_+PoiD
zeEl7y98u_oQ5mIp{b!V-73Y}HcT~|rb6AYxAuVySiWM(_#3_a;UU^J0@Br4wD@5cX
zNl?7#h(__G;tLg?vQr8cd94!_pHrYSNl`~nSF&R41F)nh9#5cyXBAD|D5WYKLI_P$
zbZ$pwx}tAB49!qXzKhCCMf7!4o>NpOLRgmKHhB=vD|%ZYGh4ypqLia}!xiL$VrLfZ
zpmG&WbmY3I$Q=aFC57=6^yVpkdk!RDah$HvURE?+g!u)Ex)&g{Q1S9PR2C`rQ9^yO
zBJLghXeEkCDTG~7Y^3?PRB^={m1PPujYYYl!4smdDz?`_?{&pNI&oDhmN?V@tldy7
zpp>thicjAKzDnV-294E<O-87=rMN+dj@ya}3iH+}w$X*9PQ_+QQ0P+VcS3!)V)hfz
zbYHQG7On@1twm7ZqqyFKF7+zd@u=)meD@eq`V~pe(C|=EM`jNwN}r-TK7)!qJHRuf
z*pUPk!-~a}>N2AEqXj}o74JO{F=GnWe*ivGd{1e%<BC4I5<H<u+W^i<#d9UVxhP{!
zLyD_%a~l9|%J>xYceheif=YKKKMQ1!a?jTQ>{Whq6f7RfE#&cccq((qqvoaDvmQln
z<uXc>_fc*k2bHh#e@mgsPuWFLAAjY0^uq2_eokJe{mKZ6x*kv}AHmQ7<t}<y4l4gL
zKuVzUlmwhX%EY@U1uI?X6$w#xYywNDavsGd!j$1FVN<w6Ij|3!B9z6HA8|<eM=?r~
z%Jedn4l8FI2L6cBk7mRu<r)*jL@SeMJ9kuBN)J?waxNWdW0jjIVjibdvoRLOl+EP9
zi&qBp;U`Q`>gddJT=~Tsu$)l-_Y6dzRQ~)D;HQ+1GTM?SDvyv;=Co2k6U7;&hVtc-
zl%Fp`WwLVhGZ2%atf7?Sv&z58<(H~_gFZizrhJ$3UDK8K*pQZ?Tr~+mrqY!>hv$^H
zo&d>GuDT6l&MRl`gWhcAEZW@VC>4JIenHvm$OIx+>D2|+i%L@kYA-2&`wBwylwW#*
z<SV@&f?QUn&>^-!Ih=tW7Al{h@9-5V-6$ckSZOGRloDm!9mu|-yh;fbrOE}Zs4P>i
zr{OMFI+0)dnvz4&fa}Vya!{&NE+41#s2j>%{{!NtawSc=RmvsbpflCV=r2%NqZHr9
zkkl$mD1Y;oa<MB^+*T&gU7I@PiV;-SE3;@@)}XB2jd5;NrW(-JtX#bnxEAH;|1Ss1
z<|PnzS8010ENx2XPhj>vWr~PA2%XA;9q3G#a!`-PZl(P=tmsj`PN&FTrC$`<`jp<3
zIy|6!nL;Cj%J08JX-GM2fic6%&S?OQC<T8&;iyu$9M+F1cbtF~kCeqUpN}i;w85TG
z?(RV4r1I|_5dB!0K1knKnNns^vXzVKq!40URata|a8ren>tMI)XSzz_u4<%}&O<fv
z2(mp@ne-1$UaAP1kbPC_M_`4Y%1EJ2e^rVB@O>&fr48&?y+{uH1F9b==OREgFbG8l
zRe#aBB2aZ;6O3^LsSJGJgH_vR!Nd^N1U);Us)_H>7^eD*K9v-%dIHI?Ga^*=D`3+h
zmG45Rh*WJI0!x%CKo1qss(Fd9@Th7>ETqJ##^}jErh@kd?}6&&Eoe(n&5Z=^xata}
zik(o29-(y7q3YfW#3|LR!!R*X<#Z5zI;}eW0%V_2eXtj$B$dMtEXgXL9nh4b@;Z&m
zv#R86AgL<<1yGTuilx1Dx+*LM7M@c**@(6*)#aTq`@CuuUAxayP4`02@>O2s54fx<
zXo3|5Do6G<)E26qjRC$$^;tWB#VTDi6qcwuKLYTIDtZSjEmhs6X|_yN^$`H&suP7^
zxvF|_7^Fh=NfI<&Q+>4oEZ0><4<Nfz<x&T7L$!kv8LL%q(tJ~+N^614T2<sQ+HR@l
zJ1B?ZwyJa|jH*+0y@BDbSN%howGFCX^1?Q%($b*5S+#i#q(zlT8=_WKWH|tLRe7{o
zYE$*nPkB#OPdPR1s%L0`I#f@$1Kz26@fUF3S3U9o?tw~UK|gy`e^W4`S9R@G@}T#r
zR4ah!S0#y2`%o1Y1=|Kxw<xD)Q1u3F6-QJ;@}G>Vg0vuGs%V<a9;vD**?3%~p*MX(
zwdgY7ldAASkjJV>x|}+t`Y!}Fxv3jyiQBEt6ho1_`rTd(f`{6iNGBLibuO9crH-cK
ziLd&_c`(sW9Ye30zxrbv>^`7YSAZozJ)eAF2i4PhVN<aB{>x|!Q8!s&Q>eOuzU>mB
z-r0@PA$948kP@k0OSvAg>P7wl#HlOjLgg{_8cMZ{SJ#Em|0pD=y|Q5NarI}jfH<M{
zpsPYB)kBo<c1k@_4Hb#%4vH<DR(p`U>5SS%0+uB8eHy%E^|wXneTuqeF34H6a0=>E
z)yK%qoTh&G6L9J3H_0`Vp<ehSG-Rq*QnJ%I^}i?4=EzbX4+i4AdiHS$%~rcPp_HSZ
z_Z1Kq)N><Xey;j6A{W&keF?-Rb$kNs%~vO7qjXuFh~;5Mfx48u+=c3!EZ9_}4xrhx
zSp7U*(<)JS%mU{X^_90U>ZR(J^8hGQKSkcXa)<gIazb5I*HIo=g<49vD%aFI!-2T2
z-u^G}mFg1-K-^GE3Sh-ebqjsIqDKAke5j~Z-%JJPEp=Hu?5$Uyr;BI}YESaVHL5QV
zXR|tpHqkBWCn#C5RsHWmXt=8$U5iqi+VSsI$iAoEMXvWw_3B?hy42ltBJWnGkh7pi
zy_KB%z3QunAf`{9<c+p|^^Qw0?V(!9M%#e;ZXPO!)qdoc8&UuI1IVcQ1G<Pdu0Bk;
zEfeZ0Avh=1dvPaYhKt5XU2@fIa4^v5rb)a8OZRC0+k)D?np#S(_Ry?<6AC>wU(&4U
zrIDQhi?=2}9OQsz>nCUn(0oT8o`aerQ(y_yoTS{tAWd{4DuXr8(Y`lCGs?yIhHBW9
zj2fotpa5F9W-$RGG$-Gsdy<DVqctc-YKFaG%wbK)w*Vf|NIynfl;&&tUR$*0-BggH
znw3vOOpIn4{r0h%`*iq?(}Yt()G^KH?r4kGr1zsOLGvZ~5szz}mZ9y0#;*{1Pii{<
z2XadD*AfhKqUPlVbUo&@=A#~{KciX1fZa)&|HvPotl3W~-YFVkINHu?;t!*gs<}i@
zXPV~HIvA6#nLQW7m7$4hg0xIc<x!Y@PQxC66<L}OjzIl+%~xfp%+{#u0MF6vBA4t1
zjhPFUTus?q<UzQodGiT~xuoengxWmKXVkTP4f7I8mo-~=qg0@IZ3KD?HT#dCRHWHW
zdyryH6NN-eG+#HM@`~nN87fOPb10#rOw&>bv&%JqQW*WJW)WS#t<V%ulGQa$LM%!*
zG?P;>#&J`VL=KQDje*|uTFs?Y)ZWqr>OgL5R`<j12F;)i#x!ce{Q+#!u;GxO(W05L
z7SdWZn|z@6u4c(}NNLxk(s8##vzg)!of;McGP^YC$zbW$#3cfLU(>%8q914$(^0y|
zp{bz*W3T3K3cUAers!Ae*WiC$@pNm(DVt_c^TX%p#gOI!O&G%(`5(|bqDlA{_)*QP
zba)=qY|;SmNaOMnx;?JRVxVn8b0PqhlbR1Gzv!`MBmF*88Y{WET(r64Xmiy%98W^1
zoA!NL7j|pkZU%AJdd&dO9_@QkK<w2nHA0$)wv>)Vp4zx&D0yi|X<qi$z8VABKH6QA
z0QhQ`yTdd;?HRgL;jf*mglYS<bLf*L`?c(Fa30Y5oJ3`SR`xGS2elcFAHf=^&0UJx
zAnn*QFh5wEOa9Lg?T<NV3)Q|>kIFD@?;Nm%YhyOS!U*mBN~k}iT|l`6k=m+O7<yPM
zTnp2VXrH+b&M0j$1+b&F9|xoDsCFHFH6up*-zJb)ZT~dLjMM(l<N!UUt>^}c*WMu8
z612sS@EaW07R><b3GJV>?4Q);(}ZzKn|Tx@Q5*Rp%s;K&s(^)Ow5wl&O-b6fC>=Uk
z+edkCDcVpc;Ld7AA3=1gHg*B*P1DXyfHCRXKgi{fp`HFdrN3orXWj+=oOZq|@LAes
zO1eL<T}59<$<{h+p(#fjM={h3+A1b&%GKIvQ+rXnZ5?`lNh>%4p?TUrX&0NXU6u~q
zW$kpDI}5a>^eOy8?bkHV6ltIQ3Gia=3i|X&iPlp}cU-S%mz;)*Qf=vFbf!#OO><GX
zcKM4aUDcMyL3V{U?pJ84)S7dFzoAW(p>$KbkzBe}+K(u&w_3aNW2mpu3b#UGt#(Zo
zO1HG%Q+n`i?W0`))M?KKL2teG+Zgn|L3^CiBOHxd=6gUiX}4a5iFdR``v7d#E~VXF
zi}s(@P}r*F1p<Fpn@aBDHf;kfzxTAq=-yzvc1Ija9oiW_0CZ|YXfNHR6>NiwZms<+
zaQC${5~1mVcKNSh>CwJm0ZXs;5P6jQ99owIu=Z<Tc0uh!ZTg4k%z&0j3+|vclBT;M
z?W=U9cv$;pHdscqcNU{<R6Fx^kTLDAZGb=0s*}Juu6=$8EEC#~lc8`@n;C`ydaRXu
zqHRjMhD5vQI$cresuO6@Gk2Zib&8(s(Pem`cCT(aB>{Qprtwkfsk=oAy>y9j_<g)}
zIc6B_qdQ3M5MNzqJ1YHj)99!0*Nt!>ZJ+M&8mQQ>J4*jZdO-Ko7pM%-rBQ(7pe}%X
zL4i7x4~98Nm(YbS1?!v~6!{L(#gaciR2Q-qeG1csilHK0_x}ID8lii=5S52?0?O)&
z)Y;Vl9@hOtN1r3QyX8<3rF+K%ZPB`|eAs(bmqPFu-8DT-i`9)kiOM+L#qU9m=~`F9
zig?}4F-S?!ty9wbcU*UuKHhOc_c5iBp43eSq4AWimL9f5U0yKSPU}YL%yUL}#tFtG
z>3*vO%UPX2ZRApQ<>YNn)6H23h3Ps0nVq3~e-A9o)GfOPDd%+0z6(H>?%qn2&g=RL
zU~jhW6D$4CZ;tNfcPL)a1=C^al5Q~zJbAkOS0FTBr<@Iig}NgzKvR)!Mj2R&b(QqU
zm+G=tLSdP17P8W2l<QuiW7RcX9Qm-W>lhrADs}4wAh&hJDX6T|HPu2&y)LRAq8oJE
zUZM=DM%{Mud^G9CnUH-)cboFun{~sqbhPOHNdUf8H$rFdySi$MF1P6-DG~Xe?&=<p
zcHP@gL3W4k@M;WRr>=bnq)WH91#R8BccRgDUpK86@CUkHij(x{aw$C9s|#BV(T+Zy
ziDE$gx}B7U_E48aNw5RDPu_)?LEYX3U>(xUehZbux(rGpAJMI(E$+B(IX#FIy8mW@
zWm31(8TLNbz0!orDV@gvhQvkhdJ6q@)ra3ko0~o-6*leF|Bsd<5B)bf$n<pRFP{gG
zmwwgL5bCY(r-{Z#|LQEL_tmG+iO)~J_a9X5)2GpOul;)Mvk-GY?<m0U8=&{=gP4Q*
zj6IMNsGoKNfFS+lEU*OYYfHcqqVM_{ZK3))6G*uJq7<Sd^s75z;UT?)c^^U}^;SwF
zJ*+Q(66Qzg7m>FuTECf&H%Ile=!hAsSKUBcoZgcnl*jZ13W!P2e@Dl_<N6OnFfu3f
z?~<SRq<&Kb0H^fRCQ&-0fB#*SlJv)(gRo?M4{g^|^ePI-p4G2%(3Ox>{b71n()1n~
z5Sp%kY8F^C^!FxF%F?e`hVeSD-!ufyZ2f`nz?q|W+X-?(KO+Z~x%!!O>b|H?`4gO%
z^y^kZcAkD0dC>FqmF{S}tZ#o7))(kc$p9$SKTXShk^YK>c1y+jyPZIk=#NqW?TVgF
zy(raR`5XAF`iW;zs?dLz24k-2{V0X$y8fOg@Rj<iBY@w~zg~hNxv78U7AmXs+y4Tf
zTEB&ILTmKD(H^lDzYoYQ{i7>rtJ5!~ct^cH`YH0DH|T#lkKeFSpZ+PtH0dv20M8wL
z9=*-YdY?$NwdlW{4%1roE6#x2)w|Nwsy6-DJe2O~pPB+oyZ%lFa2@(hAA@x2-^xa1
zm!3y{$ZmZc-QKvbUrebN5A^yKDD~*SEvNObSI=yKZ4dPg3xF8V%l`yoP@j?yV@C8(
z(W!k@f8zzPjOov?Vbdf12b7>buIJEmHKE@aiMA<y6)iw6hTA5vxEd@^VnlZv3dr;B
zZWuU${_ZjSMaJwkgwtc?VbIfOkQ|<dFDM}FW$1ew#M_YM4up@vofZpU!z>E7`Wc2d
zLg;=2hn$lK45h1~KESXu5P*Y*MIWLv(D0Z%ctM6w6JboSp^S2lLk#n0LsO`snYPVg
zhD4f6!VS}DmX0vI<^z^P4#O=<>W(z1Z$ao`!|Fibj~Ik+gD1-H_YXis8y3Hb%A<yG
z3M#}H4y*%-H#AXlN`j$}G7*m(^b{^VVOUSTvy+BDd-21ZGF&B>MWW#@ZEsE+mM#bG
zjN#KTkR-z=HDF0LIE>>kKgH1218HXsr4>+^Y8a*LgEYgk?@>xOtfk;<h9T@r^di&H
z`YiD03>zrFD9f;r5`@khG_<|SHaL@GI>+EaJBtej={4YT4PoDcTr^y6fWk|L=e*Ff
zJVX4~;LJC?>sXK4%ZB?qG0p{s2XvGuG#K4raFHQ|whhIGyDOlu#IW^u*mT8^{1#39
z2EG}bWd_Z3s4q9XHVhS44W)EOt1vu8LA`5+J2bCeH@r<Z04fb$6jHfiI8O8OO~cnT
z-BcOA{+iamYJ<iPq{eW)AEegsBPAr>GHg?zblYGfOY00)%F?eloTuGvgQ1MvbB*Na
z#2aI{e+=Y~!JoW*&4xEAKdHsgMB%Vj!%H*^+%r_i0M~9<_zK!O3~BBd*iOS57y6&y
zE`$6-G<F+`dw{ras6k@kj0XmZ3_^Ph0X^twui+bVPWBnb640l91J4YWhlV@LVBvs4
z$U)_xVKap^M+|?i2Ir{ZI_+e}44=IKO^*!0q<-8Wq@(GCVVu${CJp%!^dAe44X(dH
z@08)aU%={Od}lLwT#bK`bH&XlJ_mz$8|U9d$=%4Jf7|dd-u(!bp2ny)0KAO-<0yF>
zgQB6r$Jj{MkbI3S8?5j%*3%m0Zxm7{;6CFY97x%3+#H4xJz)HWB2kV2<63%j4;p7v
zQfZ*^Bz?|3$XHGuz+mGX@(zX=*So-`P~#wd6C=zxhh~9rV>xAxL>Ql>822ILTG}H<
z8pCPNb=dgcOAr=q{3i)*M~&Qnpf|>N{5uGXH4gNGCC-@jI;0$P7+=nY8SzFh+I=S&
zwe<cSH{Ra>o)gBKbnHE8oF9S8Q^xP<c#>%RgrX6rjV<IQNHY3Gp_FWt(AhG@SVg<L
zvqp9(20zv4M>()*#+wJwmTp|q0g_=%w!x-MW6wLloij4>pM`B%#yUF`<`~y)LJuz(
zIg3%5Yt+-I=NVH^faDv`k}vDBvBMo5Eif*86{Zy$hiSWCWK{hBzR0*b2`nYX9U;li
zxLH;IE=uLb{R+UZ8u!vuU11!gQ|LA0`ewkd8&#C2T4~%Lgps*n{D(eTaMQSi(m|?>
z>*-8bZ48Wsy*0)+*21z{<Jw=)cFVX!fDyTEtfK3Cb;fZ8jITEe--74{;}GrG8jXC1
z9fQzhTt^YcJH};nIiT6NmO`2>#su0gw;CVQT7K8qoCuaS<B>y9-)=nPj>-<>Qkpb7
zjRmxvbQw!%`Rq1kQoi<m;}6r&_P{u+A5waZ4}OI)y~d~LLQ9{qW*OT0jhE!~06#QZ
zyTLPHj6=4>j6q`oks+g#0agqf|JsMnj2J(m&mN8%`JX_{n9-9Cnvab6y$~~Q+%W@W
z!Z<%3m6OJ&8!%3fjXHV`r;NQGFx16#pazw$rl%>y?PjvlPq5n*F_%7{<Zil3`}{qo
zmMM(oUQ_seG<ukNlpvla#~_4ynWkr;<Zb$E5m<aoL9~DLHSuW|>SvNBgZP_TXj`?<
z)J)#-{U#d)W)7IXpgnwmX%jhk51P0XaSJr1w?Sr*i4QM|V@9xvMHvYprmQ?5LQO%<
zkR4`f4@U39O`FJ19ATPwALDe$lt9a0q$!1bc85)WQ9SF2Da8YvQKlH0pQ26Wr|=sb
zHH}lAK#Zy00G3!&fiFm$>8S-U=9q~&0?v5T3<}md5={Skz?$Qx`xH$-VcJW-;Yrg<
zTIWxhcG23HXv$Qg^0cWu803s8WG;Y7rh;Q2$)-6s@%yBhexNYxS<}nULsP10#z(L>
z!}J=h-kBx`eTe*=X>JhoW|=mUE9tyx&wO+u+hO{Q+>tq^SQ`8brVb&*<eIk7cLOh)
z_L3*yl1Z5Z3-e3?U!#<7%9{<qWs@syUkgmehtO1L8jl0K$W$zW>|&G6AEgpgxF>K|
zOfi(?RBC#{jxLp%Oidu=rhmy{dDY~&K;GL5Q}9m^bItTTeX8%e=~ggErRl#KD7;}B
ztwh^RQxmNmRi;1wMP;?=7fRf!G3}cH6}6_MK>%)<exn)uw&_Fx6xNwmd<8(g$^9Hk
z4W?o8lr)<DnSj|%CO-`<ykmO*|NlO$*%ZAWVp>c~F2bl*Qxx4xxoi460i`xm4js<!
zncB5b(QcZbhqexr@&6Ym(;B+Z-DP^a7A)N++j&U2Z(3E4(gV{FeaWN8G-o>ozt<Eo
z3VZuZpUuZF(r>D`1N9G0;<w4=F<^?Nee0kpaw%jFnI<WCI&Avuc_2niscQ6T)U@R_
zu#B1dXF|mzQ!rhk7&p1S2Ec@A7ddJtO~I73{@CPw0Gv~%!g;XQ#k{c)R=AoCHrV85
z{?i?8yUhyP1Gt+LA}O@tVNRv=HBa-tuRy%aPFfi3Z62tC3Lo>kT3G07KDZE-`^?`^
z9@TzxEzOn(%zJrg3pB5ChZRBQ1;0aRusOXOl_6#|-Qfr|FT0D%Fte)_B;5SsyXZ@V
z`SH&%=8*Y?PwD-OG~b#7y@$=5IPe@XyN94NN6jU4i802!^CVbf&B`&Th%;9eqjb!i
zNr?^d=5-NZIbmM%3jin0BO9UclsWKIw4E`}S^_|l`L`~VlFii-5S?oNgQ6d4<`Mzg
z(#_`@fOBM+bILHJndS%6LC%?9TnwHpvz$Es=gq%T%2l@ctqy3)F?;8u?SlD|1cQ)k
zUZ#VXJo8n`<jXhz)`3o3Hm|4fMUh$hJ4mtlbUjFkd5XMUrRE46rDv3x-%5kta&zA+
z&~VjZK6n?>D$G(dYOk4JqlBjG=8!~`D$No)8{RPg^&f`qrrE~_l~v}EP*_o8-tGr!
zwdQAN<9Ew^Ed<8gHg`RPQk^-R{6zKUqZCqUFvp2dYBY!X0?=eW<b*N2V^04Bm91t6
ze>>FQHJ^J0&s>{%dkc)ZXRf0su-*L17eI8F<JDm4GJm=SZQbS{Yk<FRF65w356n(;
zps>drOvz5YW~cKot<U`5QRwYApC;GnL-TfetOm><cA^u5=DYbQ4VkxkgJszKii2E3
zBj%A0Q5-ef=`Q3Wb0D3Q$IYL7j8UI3zd_UGq}iB<%E#vGd{j=EM<_4J#nLW<O|F)u
z<SKEq?AQhPZc8qWp}WPj2iEVg?EMBTdo3GI0`6fsO@{?fOTt-n$;VRv6df&nEn6vN
z%g-YIf6tWVI&C8lSmIAYZ-8aI11twE*)&@RS~j(#6l4+mqZDdcGzTnU76r|S;g$yS
zRYX{#De>}<r7a6>krwqg7@5Ns<6%@Dv2dKBH_9@H@=u~I9XrUibJP+#1LntAw*3cu
ztR>+`l;SLjnZO^j_`QOT##^pZs$_zt_5s?CTguj;ho>x~6zWd26woQ<w8bM5<cwue
zAdE?}tRo*|vgP<2(3EO9;0{2VrDi7J>6XD9*mTY^>mD5~vn<cNgFc<N@RmYhw&e!-
z>T@inKVk3%i#`NGb1hjP0DsZ)AH`WNS<)vUCePxZhqio6>m8IXTawAuSYUbE3-Ce<
zlji&)%d4NDt=KaAdstCoSyc-76-$g2T`INwM!r}_nZ^BA$S$`yAAq#07F7@s6_!`X
z$#>229AzzBx9p_@P^IN1+L_<5xX>ZC+9II6OO2&x0orOUr^yj_%kpzRDsNk&W58Kw
z@u+}`dQ0+`05n)idO#X2_rn2bvMi_3zT>c*Y(j0bCFu}qTP%eS0c^GS^}wdPmNdFn
z(`MO9lgT|x{C04*TmGJfQio+%JxZOHC!d9iF3Ug3sO+|^_#dpeZ;6=+_yfzc<V)(Y
z#1(<F*YY}Lqx4zwX<~e6xxN%_0~W`uX0Q%g+FgMkvi#W#GHj`$qv?nx{Uwl5i{M8f
z#w<p9$Hpy3LqH}hJ+u#;v{Y^Y;IZZO2N?A!%l8YQ$;Eobib_{&_<G=WTmPZC#N8^m
zhPFM{+@FBkYvo^qF&@_K4hrFVTfe)BqL1~RSg`t9!)VLrXDv7lq5jr;$1w=|tkYfw
z=YH$OcfonUTJ$U00<8PUEq>7YOez3@)_+z*MUeIAO>hQVC(nX2#HubpCqk`jHiCp%
zH@pE{xYfM|y^gT@Z*c%|$m-n&OCzm$|KKM%Z2f*36dtiYMYm(3tUsKEP0`j7HwZmy
z^;!;mjFm$!mRRds<Ux<KzDyTcj#=|7ASK@FQVx<}z5fAl$E_DWhlUf@4~Jl3qIDV*
zm8Y!(7a;nKwP_W-e@RweJ&MWJUw;NqiuEL=n59`K*TRZ)>kj(fQ--yo4{e#&Y5zj~
zIcq=*DzmJ8zEFSOI)@G`+15!3Ds!xFE<z_RSk<H=*E+NZl^3mRM<FcF8cP0)eCrvy
z@_E@>dyT$)Qegdv(j*G47ZSi)WGyHKDYkB~LQIKuIUUDJtrK;yyUaRo7CKsPRVh(<
z)p~g+I$B|^q`OeptWm4La^0$`MP;S+rVK1MtQF*;xoJHVhEkQa><T(jZJjxaPSjYN
zDQ@7XwXS#w{4HxMd4X<Q&r!-(opsU^rF!d%0SIldZlbenqqU5(*qW@LO$WJSHP-{z
zY;~v1xEAZoG<2fXnnvlL_pDoKB5${{=yr97bz&ogby-6<pww-hOJ1k@)+gei{(-~#
zTRa8|A7!S<O0RWl7ZmncKcLM2erwAk2z_YH{0A%p*3Dl6KWMF^X!wxzeK(L{>u;1V
zH)^#m1#Zkb){c>VWPScwaE@F1$t^cw_4*U=$JXAZ7>g;ZjeaH<TVW^EyV@LYsbHI%
z%>j?i40qee6KLFHYbyfTYnwwWo`>x=?R`9L=fhF*vb9%%)7uuBjgpV;IZ6=nwMA5+
z<Y${hr+k0gdkbOxKHG;}wC%UOvI}hoY!&pv2H0A@0?R>L`U3PU(00y2o}M7vMsnl@
z+q`HG5^nQc01{zaRRR+a+5V&XHPY6a0hYtIdA|UE#CC;3>`}IK0fa`|%vaEM)VA6a
z3S(^HRp?TjZ7!W8j@cZ!us7bekMisiY_2wN9=9cxVYE-!%>543p0xd5i5{M^C4LEM
ziMH+Yfj@0q(g^iQw*N)Lm}DFOe_%<m-Pj7DXKgMti=^5H)R2~Dt7`;Hy3IEbZ5g((
zK9n+T*#VGp&X%(rxGdZDNSKymTO|j}1=~$}<Z^AvFOX~XqHV`C^y!kVfnNALTO(!P
z<=f(R1Ap0eFAp6pupKc0QE0nvfZigToi6+p+p>3{RATG*f$S@`01*JCwsA^=E3>Vn
zty8&e-;3zPRU3OY`deXJPaA}5wgNg)U$>cX$Z^c5v;_<Uf5Y}!Flukwmh6D+Dq9h)
zW7W0^Ixf`Mp4bLbYkTfASZ>*(C>(v;cFqJt>ujAXA++9>Ny+C8wy8-NddKEV*B6>?
z?^AL~i*10;=dHG_kAb^ud*e%Vsm<np5ZzsI&o(;)Cbrw8^nINUo4yYCPTT8iz}jWY
ztO9Gd?JVtm?%U3X{I(Y^i^G&()MvXxsipn4u+Kpr+R`ZKI$--e4e&vmpaOs)oBt@J
z4BOJTK*NZwffj;M8;_2NW402CuRgM!Ag}tk?R7e=OxWg4fMwDaMsb73HbWjNr)=#@
zA=<?rOpCayeUoDm5N`GvG_mfsf9s1{cY6R0&>njTIZpQ4Gs&6iWxquMJ8%02T8Dh>
zKmUPBU%O-$h@br}%DeWr?`{RzXYXEzF73A~@4)&4_HJ4t1MD7IC>^vL)}e!e_Ex$}
z5oFI;>3}uC_Pg_8Vu*c+Qh`G4HUlcd?3<5(gxjb7Km2abItHPK?1E&FNPCP3dJo$_
zoeRJb`|lYbQT8t=&mh{q)(%6D+P@h^DaL-2{KK*K<zpC&IQuB2p&YY+Mpnez-*J%3
zBEjB9v-ENM#>)_sXb;|x(rNn=7l=7y&!>|}l6^Y82g!E#&FEo@eRDnRJ!`L~olL5I
z`a95+X20?TRAkt%2S7!p{qity=j?vIz-8GN(JOY|et$Lq+4gxfcjnkLOq7jz!M>Rk
z=Gr%21i5IRejJEP_CzP(^X&d*uqof}MlSQq_SN+Di6Z+KuVL~lw!b8RF(vl%76>h~
zo9X2!x9_99=~a6hJ<iwd@0CMSr9H_RQf}CvBd=|>y}%uS8v9dbR61(y@0|nUmc4NR
z<hI?V1w!lWyB47{P4-{aP<Y4gM~P6)_P$Aw7W;DYp0?WA@hIK37tn6M&7MPhynFVV
zekg3WpLPT3u>Z9YQabI2DR$arpS2z=-S(&p7})#v^<!Xp;IMnuf%e#$Y0%Vb-}*0v
z_Sp{#prYUI<qZ=b+GqEnG+<x(1vCxX8<dbXWFOfN+_1fbF7b}obLrGPYJZ9pj@j3I
zg0XmH|EdmT+@9ft$_cyMPtY)Fmp(@2W4oRr<x_UY#J?!IIPakJHCN}_W|Z8VXKe%7
z?fjn;D&3uT-2~pl`MXFc^mJZhhI%jOf5p)2?YuM!Hu*U3c7ilt=TGU%i=VTY#=_ru
z(*of3IWPMNdiOh@A;0ng=Q%$D7vQ{zT!sgojSgA{1D&6ahtMErFWP4WJ1<tEF~s>2
z9aKY|U#D<qn6uzjw1qowzXzKloIi8{%OU3(a{Qu^&hhj~io?$LC`5O}dG|?J5#{_m
zrNl)$`_jME9Ch}t|38|(11zfJi#PY)E$mVj_TIaNh1C?JrWg}jOrl1UXw(=rvBefO
zmcKDE8iPopSp-24q$ns&MT!E_yEG9IL8_u)LqGwkc2Gq0{Z8I{-{;41X3qJYGjrR_
zIcH{}A=2T^jUZ7DULOG^+F`Yu3D%r&=x#?ZPCD5B0Qoov;Se;Pa>)7=F!2r&J4hrr
zd>MsOqQhCb*OMHUQ{XMd;ceRgo$4@u2vE`-USC6B(j6w%q1zb_-4t-hc6f6htUvAW
z+X5Jq<FJGUO0Gkb9ZGo)ube3xI^SU_MQsWkz9rZB8HWrJr9ub$aFAk$;knRs-r*B+
zVV5{;r^C=LIHaecvecoK+(u;%UWb8p(ZPc<1Iit4P+C)k!>t~4qS9euG}Ko+EIJ5M
z<1m-xE;;<N5{6!O@WwpOB&~J$brO1i)ghK5z;zBu3iPnvp*sj@*BnOBop9Y@LOe=0
z99B*M%uR=vzk{>E;dvlRw;e{)O0m%)h&CZLIn?8!mNq-!X8`f2I1HSJ6?YwcufnEQ
zhi@ozvCW}`LPz%;c*^52wL9GT5xwYez|K!RBo0@`LZZvzkGoLV?+{I+H|S7v6)dkE
zUU`AIY_}Z`Y`5((Pa)v3{rLe{=(YX27l_aHV9MPK-(J#<Avv{OZ4J|sx1S@ARQh(m
z7huWWUg!i3x!Vh9X<1;}p2I-J+3n}3qvy9<Mx(ZT`+LcNxw-vzIOIFFzvzN7PqzO^
zXDAMA51^y5T^;La6}s1P@Dkd59XDKu!eGZ^<m5Z<7&rprv5q?0rJUk;gC=mfjv{T0
zDs~K-2lb_nMN7d_<7oO}A&OTWGyedO?+(ROs0iILkM?s$?#NyN?35jmVW`a9ancWH
z1v_ev0;Y6FJ9)xub`;YR;>M2AabRiLv6pf^+IO_jNA1xLEAp^D-?52KSbDi*q7LFN
zPHAS)x6kPoJ#hP-PMPRcdcbMC9R?xL$?qdl?^Ndw`6#EYe_}{tobuj-rg*2zbOKkB
zlOqYHI?YT0XNFTVEzC2Wu6IEo%gKv^_}Na|$RUvL^mQ#t1x|UxVN;<~ASG~|b*d{s
zTai<PEvz`_^yqJL85TPU)V1?Y3r2#JIDPOo_0Z|<`RH1ilLh^PK)KW5ObAvueLowO
zl}@(<U{jToZa7p_J6)v*{*u!*cd%S`nmiqCwN8>C*mT87?gtC&oOTXDWxdnFdT?HI
zsx^XKcPe;~rfhedj??F?)ky;v0K$7Pj47o}UA2r&Hq5)qOlX3&^~`v>)2=fuG;g}e
zJRAj~2Bx1jA2c%MdX$=(ZJz<Sl^IIkg!|0zl*jXo(LF|+Gy5ea7kIK>l(%$%b<C%g
z!yC}A8A_p%x4%h4`5iodZ%BvTzk+_fdx|EO!)MT1e&SpE(fZkYzoPZ?hFL)W;+`}9
zPTEX6H7B2-z~z+I!?=iFzP|xzQ<u=*|7m^`F?L@?QSSHGRrkU3O~`g2PajJWlNk>f
zIiCM-->1X2W@b%B^Q;njKh3UvhW~%J?iwz`oK0%fd~Z+zdT#zk)Xys)g<j2{_ceO+
z!$TUmAGbC^*@7B)V5AFuW`lpx^eFHzens)5B?F^@^HcUr)GYm$QX`iARtEm%PPEI~
zv||2TG^{K=3DBR*JW;i3R1egw`JS?+f0@&W(ORpX0D*N$zGz+VN~uE|vgwukziAZA
z+S!qbziy10GEd!^s-aM^mx-lY(t`=4j8#u2u^*NDm^ZHi*^Bw)H(2D&yu_{wlXO3m
z*$YH}#^W+nH8Bs$VaWsL`(RW)WVX@!^97Sbxz7VkB+b*@*l)&yxU;{EAWiHeIyljT
zy%2|zCp$9`rtV|&6{z%Ld&ooQ&7Pyf5%;rw4>9;*Y$q*Sj<D<KoCDKI)|XyHF{~w}
zlEktP-h-w%_Iod&onjkkUqd{5p6>Gmc2qU66WJZ)8c1Rt%fXV&n%aP!!tSCePAc2?
z4oYb({{c$rZ2bt7GTChMF=es;Qi5+bdtnT~GPu>`8p||s=`X2~^YjF0HuvRwP<Wb~
z@(PtXT*hIr=5j8yYC@7Qg>mw^+6cfDaMSxyI>Sxa1(-ta7jg}p<t|VLb`kgCOmyiS
zx5Ni>#oS8Dn?<G<ZTBqUJU<1?1@7ZAK$mi+NxM-j<H{(Wa*-QPi9hAsldnK3xMN=c
zw2~V&9M`al>!dYBHTS<OFtmm{OVf}`T<O2ibeT(|h)pf$%0b`?7ezn8b(Pz14$L}k
z{VHgv=f0<XYS*~^LjirA+eAUw8(fQtwvXN9))&FVTU_lIkZ9mWuY!u(oF_ehjhwas
zq=|b?SyRp2Al-y_xCGklcb6-e4AR0ac>$DGZWpbX+qf;gDBa_}(?Vf8_qHqKI=JQZ
z&~|bbJ`nHXZqS#kn{)H0Y=j;z@H+_J=VIRg&jW4`C8Rv$x@dj(h>MwpK0W3RQ+C@E
zZtfqbe9C=r5%%_SZ@q$CAIEP%+cPedq9e~aM><lupEFQk?FBcSQpE?j)QLcGmRQB3
z+q)$bY0jA}`DGft|57CN+X0#?In@D}G)V{T2uPQ-sbE@$WWy8KlqngdhJ2RfWEb>i
zO9JU>t(K(FBU&SwF%;yIWO6e&FH1ga1Gy#n<!gvHNZgvh*(zDu37gs^Z~hF<4vG68
zVCj@_|D$ZYz0x}JN_j{>j)zg6Qic)+y`}FT#K`WKGKWy<Bh?>+ysvaVZDBYDr!Oo#
zE#+2$<VdHy2FaD4r^h!>I=lzs`O<8f^%Y3>hoDPmqycJJQ7Bz<6MD}|&kcbU=kTKu
zu+UU2JsXVL^U}d|XeyCv=#UB|B3l8iR9a{NPZ>^AhTe-fmkqtYE&HGo@{O_+2SA!+
z=3OAovZm1xza!g6AD_Fj5j5N_GRa#|-zs~yiLRE6r$n?qnb|P3y_OxMsi(6^o<bW;
zcgsb}`f!m)P%z6&o<)7~mj7`QmHXwB$x<JAE=}9~<N`T>{pFvVgB*~@UI7V^=h1Hj
z2Fl0M{Qr>rElQa=EDxdN$58nIZA%Z6|3<$*aYR0?3id|I10SO@U2gJx4w@l<eiS5A
z{{ClZ%#s_f(E!WaC_OV*{&+Lm^5o@|WSTFJr#<Hd^7mH3m^1QO_9$JDJJVdOR31u?
zLz&z!69O0IHJ_uhTz-QESf%_JUBW8)luhV;y?k&e%)TaHy^Q9y*X6c)*mgr6K+e)z
z@)?vb+#vU%Y4L6OKPv&#D3@0NyIDS<LggK~n2O34`GXmNX_dcEZ<u@X$+c)}m!Io^
z!cO_5!{LYEV91yRy)I@U8(?pcS-?14kzljjm#7Rei@J_ds9Ez(poE#V7ef0Hvq||7
zKWf%WLD6GojyA9*+^l&oSR%~=ZbEI8*?h{gh&Hn)Z~F<eQEx+Sj9JbhkXW-r@bgRK
z%wnvd;gs38rZr%VH=DB!#SF6rpTUYuvlX;WAluCR1<XEeCMyPLj#+IQSaQu+av$fL
zO`|VvfmuO3+Rm80q!iaevlVpW=vlMP|Df`mnOQ5qip``nB|2{wpA4`Pv%53VR%&MY
z9s*@%FTS9-!bLMX+7(}6wuo{?E6t{_fu&VuPxqtLVK$OBnsl1YBsYDx*%4ZA^q9RS
z7x8^F14U>bn60L7+at59^lUvg%k2Z_Q?p_8(&{y<ARo~yvu<*EzBUV?$f2|1%m{Gq
zR=ib26C4-C-{hZkRm_|Xm_3Th64>OX=>HiK?uv1vQMp&ak~7Rh@oWxy=%*N;2o`^Z
zf*!wv3T_C7D?p(S1m_`z&mqViR_vz?_aw!y;n0+<SWcg~RK?B@(Uzu|unl18iXlhH
zC!L}A{26L96>|D)XDPfXZz5X}@eWj+R(Rh9YmTCbMP;r+N}u~Y#Yzj@j`<4hGmK?{
z;yZE_oKXzj4)H=o*-$7vtKeuFU!>?Lq)VZAJ|D&uE3)aGdtULa6YMQfoH&Ly(*?yc
za>te`44ctdrg#(r){BZC=zc6$>{tL&p$ORt^Q#nP&%jcx*z_K{U87ib1~y$%47x-8
zWd*h&;}fS?codaa6gxiw=T*f7x&`VKz7IjJDGDg}__|^QEsAd_E>On6O_O5oN1(S9
zZ(V}H4GOD8P=8zTdI4-}RK$`0xJmITrFu6jX4Aa?j$-j~RNhtG8V@U46cPV`v?>-!
zQQ4;WANA>;;v~)Z+7-?;1L{zOQig-S(oqMS4k$B!f<TC}NdwGKrD=;228Su*;&7WB
zQN|8K<1yuoMPLnA4$?{?LYWl|5~*~jlX;?)9HrkyE9+BHc~bd%0IZKu{yrWkvC6hx
zAaTm=e`2`emHbk)B`U}61z3`DxH-gglv~W9C|CLAX4sUkJZ$<NwFS!PXn>X|Z&Pk;
zwQ><noobZjv_!w8ob{iRNO|)sD6Ca_u7ThcrSdvpt}6AJ=x?2JO)UnvUKx`Cz1NiE
z2EchoSwo)fyGo8`d@ahyf1|QhIV=?V+LYe(0l23u|BPa??aFr_!0ry^<Vs+7DOdWU
zvRipw0CtbEncPYDm1eZ><AHK3c^e-p9ck0sBjsDPN#U{bk|VI6DCbhD&Qs;wOknpa
zU)%u8Gvy<SW<FP*r0kY{WfIN*UMT-=1<HW(;!ZjZ|D{s%81jS4V=<_GrBp?t^jcZs
z3T$Wd^Fv|UZu5Vpg1DH^pmm0;x%*C(_L%z)he9`Vjy9ONn>*5!ZLj%jS`F<pkD=@8
zWxj!C3*P3>X_@6?zTyx{zUDFwO!G7EtfU2ozxildz8^5pqQ~i=xyN591(@6T!r&w3
zCFEx~YW@xRc#oOK)PRJW2hiI#!h9DUNf2rN4PE;v^J6quYBtXzKhQJt@#Ls>wlLcQ
z&fOL(VxiE*Vqp?lZ?Sv`SoT=#<S^PMH;YS75cIULruEl83nOJRds!U$3!vT>hw`Dq
z$D)dSt-cl$=xyn5@xlTy2Q2<h0m~r^C)&4l*kX(;+JY?R9EA1376ate3bhFE0Cbo|
zoEJ(*EZ!oo-BF969S{h&$fCg3ag#;O4-ky7ST+TqkrrMQd5pGb-Gj;#7DtP~bJAkO
zHdqm3@yP~|REu@=vQD!YavSQ?EkekJpJ8D}{;Nz2<9f(tS&a4sXST(t55SpY;X_Y)
zuEo$rFs8ubheePpv}g@N<yi~U&%Z(MC5sC@Y`bjn=MPX=YmpL$#w!*dsX?w<{75^=
z>nx_Zp;T{?O0S(JixQf3H(R_xA<{b*y#<iFYw_X(Sl?=q;t8-0iv=7Mc3Sk(0<z0u
z<Q<f{E%c|s^1vdRrVtM;UYaPU{gFlfN4QRpEv(61(Py!Y97xYB#P`Aa++y4up!Hik
zs)V60EFM3DrU8r6w_wFfi?a8ie$b+gRucOymr&Ho$1;Unr@oe=0+@c51OJ7jEKd!E
z+yP7fI>;TgoK8!v0L$_iipd6AM)SZvWZAw79X)LMTRG%|Ec=Z>3%0bg21|(LjAD>b
z%i=lU46`ge3e%2SvXq;5%yOa}B;4|Q%5FJsIrTeeim+T)3eHH&_wd7X(kROYIvf9l
z<t8aKoU|;UXC%h5GK$iDV=c$f=>?}OC;W|$##>&ajYtWWhiR)+qU8`LkR;1f9zaXB
z9H30s6ibgU(Th~eg7uI~vy70zv~<hgD8V<=((w{dJghc%gLqoq-vrKmRy-wi9k8m(
zgx(OVu4&X4s~98-nxtV?Mq0BRvHIU?NF1|TatT)?+^X^o>WtMe97!ULuyUs;MWj^^
zd5oj1LcRe>usZh~hGtl82?fct8i)c)mereYf-~Eye=|_Zt)`G)v%+dIO%W@t9+BhV
zs?{+1Hr83S-+=~Gz11@Elw7mwrK#6-EBmj&bHl2*89X<wa+*+i%gRB5%hh1DVI)-C
zwhHV+snM$7FIdrJ^)vyT%~ozsu>OwK(S0B-R=%{tY_+PT;C`Ex8w+FZSzQ^6QoB`2
zJp>+GvE+4sVzP307mZJ?ypO@sUaOm*qOs2^a~Vp{thAJ=_uR_-9IWWKx<>w|7gpD+
zAvj=ld^;*%T3w(Fv_Y#4bPUETt2Jg|aaOs_hTLw|DB5@IqB7Azw63a!l;5~Vl}uZ+
z+*EV_gd%s9DJBoay{h@?VD(V#G6Kz0^|u<0`&3O)sPs}LZh@e;%ABU5`&D--0mnym
zmm(j&syp$h^iwUMA@x`JzlF8~sy!*FJgAy+7MCJWb(1of52>n7fgDyvP+nJ%Dq9K8
zVAY!@^7@CU{<egPp{h}I_(7QJ_D4{7M0M{&s5q+HMgg*L)ip{%KCZH(jkFOeVITS%
zsoGY9wkTDI59Fd%%a%aygv!_la#D5hGBm}i2IvNkQ*EUUw5L>YzhLm<Ri9CCBti8$
zmR325s`LMSqE);9fKkb+@8bZPqN<|Y+EmqATGFPew$K79T{Vpk+{jdYOuM$TRF1UQ
zAzS4i0?^Z{jur^ys94Il%T>9=p_He(LT}rA)j~?8FHvRm1MGt8+rJ=Cs`}wJZMQB{
zwNVzuWz}FNcxqMaD0S_M>XRL)ys8>?8)$W^_bD)4ugZT43$LjP>BV|o)p!R2H&koM
z9d}a|NI6BfRLf{h*`T^Z%Y@siY2;aIRQ-DxU`;9+4SusKkJ54Osygu-NhWEFYKJSj
z)~fpD17NqQ;?6<ho~m&kc-mER`nq(e&c#5!Q{_%xr!LiLx=XrMtN#bI9#zi<RNhw&
z4nySwRYExg9;z71|9PS+q@8e2Ro~R1tyk4a?}R?p-e(}sRC{UXg6X+x7fl)aRS9wE
z=nEBd7ZSUzoBdJgVtu>}Ho00qF2iu|vCgDSFn8;5H2K(TJ>eBf9@cKZL!qa2Py|@^
zS+`Iq*~>Z#pLVIY^^4`G+;9CT7$qO;t+%1q*ZNij6!}@deG$apWWD|uXo|6!yac_7
zv$3UAp?I71l){o|v-l?%lWb!sgo;#~asiy_HZv*jDAT5KJT&Flh_k?1XR}$3JK>H^
z+cJpXwVCo1U@bOV|3RtM=5a8@+ibMoLhhc;3HrD^vPq%k)MFd7U!B0(XQMbA9);E5
zlOY(B0h?7uNW8QeO1_3cn{8)N`O0Rt3pBm9@kJy;>a4y_0oUE?u{)u{MLk7}`^r_l
zU^4`~)v<SgxnDhZJFE{?r<I~IOl_9{>yN6fH()G|sjpJ@e7HJt6H3R`ZNGpsQjH8r
z>bCmSGe{(<Lo%WFwEC@cAUSIPASldLulpZZ&a21JQlLaV<q+M^>OY2|tyG;uZtpVn
z;Bt_QYDe0NR;~`FsAPqDek3X@)nBK>v?}!vCqSyz{geP&qc+hD_mbNEYZK^AwJT+#
z-%_t6w^4)I&JUVytIca5(WurXqSU1JRKeh8^@3;^b4Q&%0pzaQ(+X`Z>W!bE)T(x1
zP-;^v>BDtTowo+!?doR~+v!lRr!8!q>R|#<y3`Gn=FzRbwu{_NJ?h6aLig2*EwJr@
z`m4nde5n2;9)ge5D=75$SiOD(DxavQ(0;zB>ZH9;*sIQ^&u5={sweb5Q-5m&%X77_
z5-R%DC6ti)Lj4c<7zflJJb;Fm>a`SR8&pqlqYKKH!nJOa?&i-A1&j-S?p^S>@~!hg
z_VCHK!4t@jq!XDB@tb`yGC_O_CB+8wuCy5>jQ1If0Y1Vf&?oXJ&(nAJ82{%*SP{<0
zbfR>ex1s4=1plN30+IZ<H=#a?53WNgny>#F<77I)mo9_+NxttQ^v3XOAEGvvUrk~1
zIDR=DRdb3zOgReieD^pQlfc_mLq#G#F9Ir(_+x$GOy=j4M=OQz`xq#xe6<eNr}6eU
zpiY|3^R7V2;Ol-zKQs9fTIXi*0W@*UHu0)6U_H(E!}li5;jibSl*`YfT(vxYFXcPs
z^BnE^Ea1y8K;jIaPUm<Q@&#Mbc9xgZC$flNO3t=(eAY#X7xPm3Vx8w($-`5^x0848
z0{?{k*`<8IU9gn#YI3+-<V{UFbgi6ECZB2r{|n8lD*5nUNL2Afl=)W8e@|NhYWQ&a
zoL%C-91G6Nd|xRzYxyjCQm^nzJ=(7FV@PiuA5UA>>-k_kP_FTEN&vXdvj;$K@KzZZ
zi<^89rQzJ-Cz*z#*uam<1nX`7>oSl={*xDgY2p|AgEaH&zJ$U%{7l-Da+e=Z&Z`!F
z)kbutl^;GHZEgJVbx?SZA45x~cE0ijDm(a{=BVuCEec?07eAHUM%}!!1>@Aizob?E
zecsoSGL#<h@oxd`A@4_Sf=9eO4~>ucJc`df;b+*P^puZY542vMKLXA^eq%V$p7Brm
zq3Jo#cEP58-s=>|3qFS&F9Uo<GB{uIpDu&=Apb`PIA8JqOGI~H^P4EK-&rVLLm7g*
zg^%Z>)<qan2lcMPMVcw^5v~TJ<R&bZVr1Qg^%qduE6BctO&-Dx+C}0i{QeL&?Gr+1
zDc~j4(k=yW;f@U0`-NwtAm<}UDNgJw#Fe4VPx$^i6!{CwuE3ZB!T@$5<L4`c-|b;=
zfMEP@+m|rM5h@M|7LOotSeV@pv>;((K1i^jEd^+Z@GX6|Lxq1Sf)pkcP>#+KVG7*|
zM};!V^*kp0ZwWMo3yYtiFUN%uw3Q}8NC<{8kwT9>td9~Lj)KJ$Eu>!q%n6~xAA%=^
z(X<;RMnE_PkD(Cu0<3YuYFeC~5<ck%i5GM!APK_L$*>|(IPx7plZ2OAkYpj>8<i;n
zOPjb-1%~F!X+psd=wP~#NjZHP!skN)ohj6k>pRON*ii;)wy>PgP76Mi^^qf-p%Kaz
z?ngm=o)8*=Qob<X6A}f&WDk_i2seB{3I&HS2%HsyHi5H9h+d6xIwx4Ifu>@?LW6Ff
z7Zigil?ZJV8N48jqzHVe@YZ6GGQnh#0(wz+Nr^P&Lg96cWrc8+LXVZg<}`p-2?56d
zQ!Qi_qZc*8@N$$c3E?Bqi_5~}9RRHra_DrHE5f8v5WgzS84WAy1gl7pdZFhcz^)1B
z=_PbsC}(h8ZwQ-LqV1;ewTTDlEg^g^)Hev*>0NYNs0v4AqwoVcKAVL6X=rN}Hm^YG
zj<A8UuI>u87a-pv942Q&t1v+G{5BzjT%GrXHE}SlU08J+Z5_giuOZhda1?**5{&jx
z-z{{~qPs^>zHNfwePNCkDjo>=<j#L6%*_MOBVp=pbnUUwcov{fgiaECD!iEo>|UXW
zQc3!RsGYF)negvIv^^I>-$1Efm_ql}3*irXCkzPo-+}X`@WDn@4hrMHgW0cynWsTs
z3$^{UL&aHaP(yIHc=ZD)bb${EW9cfMpj6jAV%!+8x`~d5z~V0cN)z6_VggN@J;bN|
z!1fgH(QUm?oK1m3FLAUH-S!qk$b+z79JvrEKH^g~)ccCwlm+1@jt@emzo-ys^XCDv
znzk?;6z^t%CqVQf_iLb--U6OO;=ne59u`l&4TV8sXdW~Li?7JZ7$W}r8Y)7?ZM4n~
z6JwLnc0>#%cSwS$--OCUaU^+Kl0<h0U?z))$TOTGMw1sORZOPvtSL>j`W|}I#m{I~
zm?8d56Ua=l!X1`oiN7|%v~2O7GgwZG?Ub^eBdQKzfO5r4GN{NC*U-rZ`Ql9(NP)PT
z+=*wzoX?@DP%QC+z*+IZ9AFlSju(J=P8?H>Qn6UohSGVHxPuaBOT=X~i@qR6(}Jc{
zw5OMSnK)||N*Be3&wyPn*2y7JA#Ps{QYqdF08EwWMGru=I654L)`&mrA#h1l9z}mI
zi-!wPSu0*Qhxiq7bPmkED(2A@sS^*}0%yHwN}+}0HPI;$64%8~C@1QMIP5VhZ;Eag
z(Cu4d_i(T_h@%!l(`_+wGB_K>4vKIziRJV(H;caHE4(9)qTA!HXch$1TEvV00IXHa
z-3FF6aV;GMbWbc|(bg`m-UYA@@t&y`v{Q^FFGZI)Yz$bt#kg@$*duxmLEC*%eG_Bx
zK)lxl@=$#I1^V<z^a_J%kHxk-C_NEnbg;=&aq=0Idc~_RQR)-FUj>$DVx9$1o{P#)
zp}t?_C?Dd5DA!^T2E-3$(fsqJ_{P^zI4GWL26-h8E`g@k;>c3i<g9sTGrG20!#_pI
zMdL%WN>|OgU})N-xk<A^H_buXb>ptdcLw%e&Axhc!b4O13MxD`0=abeX%12XoR{XS
zc0hY;YUl>uueq_A4uAF09H)<ruf~(~`f2{U2sD4qMB3DUKy!*N%t6g4ntTLko_vJL
zK+TRQ*mOwqoNPL*F};gYkVfkVmSD}D1?WVGCipw_K2%fm6~-b=)1pD!5lwtKY&xnD
zeZg`}6O2@ElQdj2iTn}AHL>49B0}>{14@yaiIK1(O4AVxOQSVa<Due&=1~kvCpFUo
z(H5h*PQM)ztFc)M>^P170>~-NTsqz%UbCMbl?2VI+W<?{>@lE}r1^0;O351KpAb*c
zaP(C&rD}S9f<&5T<vZX>*G#9!Aw%Oi5tW&mU+JF9(x~aszHH6Z`w%>>xfcY^98GyE
zdY`Kqq=`wMW)!{G^EL0i255n%YY>{wXc}pOTd46T&&OGf10}8&X^I?yc}`=@Myc4O
z@mm4b^BUzS)Rt%h{s8C&jrjp|tyD9UQdi0}yXpaRQIkzEk#bE3?Ru-w{7E06N{zEM
zV5&56l*3=Gd4ulm8qN1+u;P;D99_c8nz>t`zE*SA6Xc3!>LFBK)iiz&mO71T5`{bK
zHOuK}<ZGI>bY-q<zNYEQ4b2Q%5!}?gH3O`-G*?m~-=KMqM)tPGk+#b;YDU;Yu1Pa@
zIBaUxcvwT=j>cJwzTDOPO1pJhH17&f*s9q@i<~yit~|8e(=<_Ny<M}`M6c-%&D1j>
zotkb+r|Z%ft-#u?iJ_%LkEW#&>hEg?XiD%v)24vJhng<hi}px!a0fUaYgW-5<cY?T
zR@6^5FKH`WuO@>g7JVAO`!M^N<{}5q=b9IVDD`V11z7(=GkF`O8xLrLXwCCd6SfEv
zgPOkI!ShP<GzT4ht$FSM7H6&fL|C|6JB4N~E?T#_D7k9=Xv^Uqt?Ob~7@%#S^=hED
zl=6%ZX;&|T++pq8e?lNgyWSIR!P@GnD1~Y##z7!VyS$vdp+~fp8_{@F`{4|r9n-ej
zpcJl+3PS0)cEMUmL}*vM37aCdZu?+&l=cCIRHL;W<aa%x{U8dOPHN-lg2ZT-lDj!p
z+tvUp;<R)B0_Q31F*=GeUYknJx&-aCZ=gO=I||7xCTX(P=U+&qXgPn7RPA-jlu6ST
z4F_ww)|I9W8QN#$q0Q6|)nJ^mv~|-#vb7E?p#HShojfi%+8ql~nXA1>OP4&Yp1h&?
z+T)bFT%g^&3T<b!!)fDGp|**F1823><MB|LinIv9;(5^CNQa7I?NeG&oY!uoyxS7(
zdmq4x3tH!4Kr7WsD5<YZ%ai-{qIT{8u1~qvavDg5wj~>&mD*KHp}tC6N$RV$qi+GF
zM(b1wa!DI^AC;H2T?ZgutBrmL&MPLZ(`nGF+BDjqTBqG2g0)_I^#E9}Y0D_ib6s2c
z2ik6EFH!GrYQrcDcuSi>OP2<17p<;tYiDHxv{9@6k{$=`wGv=9YcFqxO?R{&6!N;O
z{p4SOwP@eTfreIXL^^uirZr7}1A_OoYkN@Jt}P&USBJK}9+jQiyh+g1rLCr&u-)2%
z{UANsyL#xoul<!?$Pcs`Bk6I_27L_jNZS<)Lmz7eTHHO+azA76o@%pvF+jcAq1OS{
zr*&Tg&S%=5k740+?YE|B(A%&5gr<xyw5m*i4ro7~0G^jx^Y4H*sMUIb^_BLw_rdvE
zyPWP$XI*MBEZnX8a6JTEboXhs;i{YS9ZGw21C)K}rnBz^rn_$R76|OsX(`<4q06Ks
z4NqMF0@2caI{tl{e|qUgK8L)wu7gr*_UpD&pwma!M^R#5-Iv#3x1X+*HnI5YwB&g_
zpqmm3mV>%T4kSP~i2?wDx^a|Ta!BV*79Q3;BBy4M?)nt;K3Ml?9K=I(ENy)a)s=k)
zlrUY)bczNZ(Ruv{n4`KF@&zB$Wxj$$xUQ`W#vIo<&O)Cebd9uSK2rCa6f9A?trP=_
z)*W^SIicH3j*OGKi+fRu(M8XNy|KDybb@W1t~>=`r*w<Sc@?j-q_u2<u9D`6iMq58
z$^Vk1vvI_QP1b$x3Z4|5=@X1>s_x?3(3Gb8Fb-|$x<mBV%g{BffqbTJ;s;>K(yjD`
zh1t5n0hCVbMw62<N9P%c0nXJ8ryaj}y5A|yIbS#XC=?dx)>GKyj4p@bQiZzo8dRFj
z>ek(a-9@^WIY2wF8~y~P5?$qNu$Jl$({X5JIvWS5zo@Ht2*GmQ%|UdnLbqxR+A4Jh
zAE>C(<<QKpS~n{OEH%23lxuoP_w+P4FYAWTX1!Y7rVNlPx(@P@T-DXnx2?{k%OEF7
zz3y2gV6N$YvqR~+ZtW}d{)R5?I68AvcXk6R8+6kHP<dOI_$CA!b(8h5sY%zg5u{ny
z)eY=BI_4@+?&|(jg0n?uWd|!-byegZZ_`DdgE9AXN8drIU1y~5REN$qj3%|6y1?a-
z@6x3^!nSUmO+HAE?gwYE-q$tJoce+8vvD8~b*Z%If2><cdnTUf#@>bcr@BQNRQBrD
zeF?cfUDZrzdZwFgfHBW?;gmhlult9VCogm}Vo(~;eM71IFLgsr<oF!adDArMmF^n~
z9KP25{vk9u>-&BN+HU<qn!mc}zkC-guKJ4oXxpO~w2*hxkEYx|cYTWk6z<jEdIe4o
z{YqM|dg@(QLg7CB>q=C5=@;I|Sa|DG=xmPt`WN)r`{@06dWre!7yP#_(*N85L4W;P
z%1=F@KTPwCgZjSturNUHPSe;xy*>Rx_aXg*ufcLy|M_NA2I=ow!I)tEpV8n9(Wh+%
z3DvLYgLs(!{kyRDh<@4+80Mq;NOEo*)Biy$f^dER(Kj~W8PktlgxU!Gs2`y|QlGK}
zr6~QsltLJ-w|))tPw1~u8uCef5vAnE=-n<rZ>;{^$tcC?t8apw(r^9{eTvt=lMRxf
zpE(I6QU8er+LH8h4sXuIFHM|qh1u!)!SMjg(5KTD@=U#qf&*Fl59x8p)(4Bwep;Vj
z0JS-KE*E{t)t46nB~P!YLtpasW)#LN(Em6Boj9Y9KZVLdeeVV6JF9Ol2XvAC*KUl+
zIsK?oXeib@m4KYr-#KiS$5@)?)7-FBe>4{TE7RZ4hQ5pXF{h!uTyGqN+6w)x?I>01
zmxO|)N}tsN4b}R2k04j0U;jP?F6paIz=+HG49bbD)qi~+c3#n+pAJP=^*!DYuhX-1
zka@lS5ha*i(~qXq=j-~RCOZ^w=qEe}&rSWiOQGVH{_o{rZP0)HHoA0MUpo|)jr#Vf
z;B3+>>C!dpBWI)Xj^0av++F?LUtwsAo_ibWTlEuHqVtdRO~tV3vEC*N0#EdRQ_Sb7
zo=XDh)!We9u}|OcLLb9t`j+X?^jxo@6<)voDDBIBp`SkjtONRsl(zX&f1QQFgL;vk
z>{t3@U1&?NwKIY<(YBg`|H-x+W<WgEcG*m{rP)59g>Aa+JNIB=hHdT@RA$;X(#kH|
zHl`eX$+7*Smpl%+wwpr0lW#lY0MH6-Q{usT#&-CpbR}*5=`(WHHuVGqi)?@V4ECP0
zO`;%CvF&%1?Q`BXlLE&VY=3<~SJL)H4U8$XEu0RPa@+6!gj|Jf<5h50+DccVvdVT5
zB|=o&_Ww%puNvFqvoS)KZ2zKkx68H-<V&r!olA4sE4KG2h<Md@@c>G7w#rGcyWX~;
z2m;q^pVp%Cy6yM0Cc9xfjT}oiZQJQ9bjx;W2Fz}-#m_t9654jqOuW(dWhg3}Y~T70
zHnrNWNr0iIcH1R9iXFB;QRt`B_Fp=xv&(i7IrY13Eok!FV;e(Xs{6KONsxG8yKEyk
zAK5Nm2eikwKH0#2VmtCzkf*jqU&H!d+pBakcb~26Td@9_ZT2j1KDSNT0}K0YTWrDk
z!q%-5Y6ncV@{dsa()Rons2H@}PB{;+Y(?@|ytX|t2QbctP!<<vw}JT*Z7zl*S&(-%
zEF(wB9>X^JPP!R9rC@P4Ts{fVy@tfE(B@%SK~XqQ!}|H?#6E*pBQ$s!g3qJU+fYlt
zFumVkT2Ip{AA=c9d3+5^=@1V;!_b2OJz$t~3zY{AO?1LWfMMt-Ac2Op!BBC?u%jOe
z4;!Y0fhEYWn7$jqhDZ?|4KZXV05jBZ=1o+F8K!$f?ubE2zP+P{?6J^r%<woB#)KQD
zndqy1+^~r5mIy<P2ohx|=mt!*VUiR2d%|#xVrwT2f9}MP#2CWJ;TUJQz=6aYEa~l$
zU}!TyQ<7oYR*+;v3Pr3^45vGxH`VZn9+fo14O(oc8@{!IhD^g!@(*Ph#8dRf&o*44
zC;hZx7de!33})mj&ovAlhKYHGqrU(q-w=KTr2<17J=<pt@k)?F!_YTTdDiff{0~Kj
z&;0>*&hT>~3@tW1&q3vRgXwd0qQr2I?u!eCzGi@x8rIWvsLW6|j#fP72LEA@s4x^z
zY^~BDu|Y4Y490mVRU5p?JzZlsLCIj34DUWi<qLz?18CZ7$C5YR)9w#)M((p)cpPnq
z?V@Qt5MpO7r%|_CP2TBnyBY67JkoCV-w=qg^LmNOSi9ZW&y63fwL3uzm{WFX^l^x{
z+j<5(33d|}!-_<^QaT(y$*zOkF3EOR&H*OHZYs@JQ|%_wUh_1&FZ`i5-R>949?P)%
z<wvN`vitTZ4Xj-ny-<tnWVE<BXQzD&a@BSLl-gBemn}iBO_%Jx_#gCMw!2I-r&_xs
zzA)yBUFRN*&{aF{u^@GJ74-G1w~H@={588Nd!XXF-ShJ>=7!yG1as3)OXtSivQw>r
zK!e>_JCNIU-=?Fo(Ju2-$Tium^MXyyb`9k9xns9Yhf<5lZo>P(ZndjA12k9r1Mi`B
zk9`Dv=H2Y)x<k<2{!`kM6J~$tZyHkj@f5T<YTxl5$T9nI6fO+6-?<)b$L%Bj3*_2Q
zp_Ooy{ayNwoUmVU3n)qU-_tISWJEVmnPUH$JxHp(NpljcY4)Fy$06Om_z_AO_Q3~X
zMW+1=@_C)HA4dWDLi>b7w4Jpd^$ke5ePl7vD(q)12C1|cX?k8|U#WuGHTFdmRJ&}y
znih|>_Vd3$<!$@1C9ts3{)>KKHra2d2tl)bk|`3J?%Ho&2ACH6qY99x_G(ID=(FFt
z6Rgkd7a34`Za?cZu1~*xEWMrw?9=I9e`)V=7Pr8l{TGz1@XG#Y%I0u3R?`c0w{d(A
zRJa(E{)82-#+hDd+hfdK58`HwevIC`8@KE<q1ztDb(BEwX`FZ)WS?=yL3GB;81fD5
z_BKu!NiQm61BF0+jP)K+?`ynA6E}aOmY%T##;woMcF=e(1U(EeE}|7cpix76v<?~H
z{tBFjjZes*6=XcJ7i}TNfbU^psL_8HMZAs}=h4=JqsCPZfH`6OA|8z=jowkv6l<JE
zH$<GVZ8_TFjdsgWN;IyawQrJfD!oIKjTSU{NHKo#KPXH!-lQD+G-Ck01=5W_-Gqf1
zMvEzE%QW812gx#idkkRN#!vrd@%)`Op0Gh}u5o=I^cEYB)7$#I(U~HmCC2nIF#m#a
z9=*Fujia8RvdkDx_r*nHojEEij4qonmX*f!WoWB1e)SS<b;dF$kb2`wT6r`YFHnv~
zld*ITOlvm&PD|%I#v&O6Om~fze?ei3afk|yt;V%$F+y#|sd13MXXNRLYd1PCf_#TD
z*bSAP#)Fil&}EEaAm442xxfm)AyNqkRroi&J{mwHX8Pgpdk!aHn=7-0o{l|?xEB&`
zOvryrVJ3r;W=(sUg+Ac%V9G)v?8$7TZ_Yku8(jo1=04KCWueTUG<nZpI6AQ@lZmBO
zeioyo5KuPr9^EvjnF*;V<uC=5j+M*o4g*UbGo=G0pSe5<as^D(PIT=IlbnR^7c%D8
zA#m2jto;@|Ma+mO6wfiH=V&ZuUeM>ioY{`MRd$a_r`I)h-I$U2Y{WZI=+3r$43@p@
zgenMlu=^i@#gi>TN*%U$eN3MRFE%_K#G73*4Fdbw@>k&WVP6M9&X;{P7GQp?X%=M-
z`LkYmu;Ku_22Lc|F?Klu9kMHI2G-Xych0aCFdkgYC(Ii%e{QD(#_|yNCPg7ax%>rC
zn9PlVpXtBRpV(N1|9t*TgX&4o&w_RGbedCt$=5@{!b6npvh2xd{N1201*d8IKXfxX
zbx-~8BAmL9A@X8Y`~~qW<`La>Ma+*M)1!oc!r^IXe#He&g6`Mc7j)Euvn0KgdLsFb
zvaS6kf73?j<MNy75RH(}rsT^=`N=fkMafIawbrD1=QUXFsieK6|GsLiGa7qU8!SLx
zs`__>xLR)@*U>)fPxpbx-}(&s?SibAIH7dR`cecyPgws&`5q^&e_0AEVysn%AQx-B
zlKkFr*7Y>qJ!L(7J9-sw-Q5GQ1nc#l5Kpv@pd98TYrYtRlWwx!6bsf|>jBEWF0y{)
z474)qspS2uu^#dZ<gZ(sCZX+ybzdc5Zd%I)7<0>7oC);})-`S*_pL*gg7bm((_WMw
zTCayMQToU_C<CR()}vFP@QL+~?T~wFy>$)r_F8{68UlURrp=du{meRN2YC9eldnSk
z3+s5w5+AT`p=`C6)}QP{p9Zbx&@}m#^;=^B^V<68EMPm^#J7R$w&_g-r;E+%G?ez*
zIBW)rhs_)0#PhTf10c80#^X~c^0N8c3MGFVKT4fBU{hyuM@J9ZjHmpT0GpUb=nb^_
zw*_cXHhK4GWNmsJX-I8)>GX;en<?KyeY#Dm7kZd$Q~n5?w`}~sLR*7P8-X_3xKgyd
z$);%=$X%Q6GZ1L8v7qHszfGbHa?a{7Tj=vvzjFK^6z*4ts-P)Y{R_n|!qvyu!S0jl
zQDf1Ts9r!Dd^6O(Tc9aVt=tFBbL#iKA%9Wr^*>-=Qg>4L_?mj&EtDG7Ch{z{sg1c{
z=}|ZAhTf;@S%+6&M1EJnL_qK3^R9r!i^q;8SiyfqPTKu^Amv&4@C#{Uf-j#Rjp6d+
ze|-}rfBtA8SPt-i8DZc-zL`P@0etuSXba>8ipCt`$2kJ*FfZr<9mE$lpfZY2pr<^V
z|49O{6MTS)cI2PrrBc`w!|x@xK`cLmeqJJuKe!q8p5ll72<&*?q8%iG@1QA5B7bW<
zMlFf|ncR%YyuKWqDf}{8YNzs3DfudmH(0^K41QBOI5T;_k+33*@9Tg-Ha~}=&Zqg>
zU=wH#-%7tBmdpFn;yjPHJpmQ@{88GUP{5m$)8h<3d>;f0`P<~KKg&CoLQ@g{zbB|X
z$JdO6Trq#-6cpC*_T}hOJ#W4r(6{*`lqJ^6?;8#ayZKzolX}8WqFsdpyw!TiPq>}=
zvUacz^7`43f5rDue)Ma;AQ7z2!rcO3dkYcxcq3~hv>MnxLjP{a`wAzr0O}`9qEvBz
z;Q+ni4hpx(&;UVkcy<Lm8f9$|KQ5G0s!xRA7>QD(5N`p2C}Hw)R7MNmy#dS<LSrk$
zPYSbnlwyRVQb5NEV@d#aN;sVdfq3Dg-!UQy!t_>LiA14^(tnbKMGt_PES%U1k|GSD
zU`&qilJ?)`3foQerY#VTuL1TMVG5Cp!Z12{pj^1w4c1Cw=NAyH5~focLcNeb0-)Cf
zk&L+^e47jLn}VbXl`X=LlVMD&;7HT9HX(t+M)!mR4CLB{S7ETXL)bwsjZUHH21u7M
zm_?VjTd<)`+C9SC#~^rLI74UZJrErKg8W0lIv=G+!Z1n|e=Ho_3z#Rue)2c>3V*w!
zvQMyGiP3&0^!<*~bHT?Iq+j@aDth=r_~3K8lERD-lwJyN2E)QZq3a>^y%Id{(yx!d
z78cMH*jfD64T8JH;0xe!5u0eol&cs_H|ZYHtru<k#fV>l<|D5990I=L&Sr4>iN+&9
zJ0O0FsVK4#Vy!VU0b=dDFf>ryMa$9%v6c=IiWFUlB}(*s10-6U^yCdprcQ`kS^;`e
zY^MoVjMzk;pjdHNKLq1M?Ngwg5^WBmEnW;i1(G1nQvfYdoc<hxmn2@HV0p55i{8#D
zVqpYW(!}VUz)Tn4?M5j>9Heh(ruZebWr>&mb32Qlk(}wYxR$<qIpSaBp3D{3wxhp!
zB1e<Yd{Hcd6$Ro~lqPaU?4v7MC_df@3(tz?l+9Ws2GL%YYVjPc#%sj(Luk7!23A0>
zR{VS%D(l3_?}MdY9H61>5${!CxbBM{^FRhn;_wjEz7#8lK>eUtMq6TDiD4U1`C6QF
z0P@b7_F2%oTVuBz=DTR3pFppxW-6t3?a`QMpNpI3Gx7ntYxw18+p8I~4g>6=sha{6
zPtEzW5Z|Y9$U@0m(?o-}U(+)M#7AS&xj@iYvu-}H{WJ%bLA}4`CmW2{0ZoMjrGpxW
z2_ONQ)*$pLP~%M_b4W8U1Es^79iadX(nQn3E?6@Rb3cU6v(tbbs`-*~8e%kRnkU6-
zjQ^rCPP5zzrBj;U%Ap}%Gu}ieVI*jrMngVHQ_G<?S@VfKY)a8grA23|W+dgvrD+aR
zI%&ElnPzR_AI>{~9;SZSM|s$3AG$KA^ceNGKghL@7Ss84%^xjl$H)whtt5ZLtFaEH
zs5~&Pb0<j9xJ~q83Ldw5q6yfc;|}%!Eqz@5D6kff+dmFG=f}-j2%d^@-_etPZ(Jo!
zvSTK^fnOK=Z({Z9YKm}g8l*Ehf9s?G$nR+r(U;BQ5E!w2eG`NoV{!n$!;_N8oS6pl
z4(w*aIMlf?4{3kXKE~8O6fj;)w<WafXZmTv8OV&L^q@nG`X6-pD6`-qB#tq&dB}$|
z>nNWnhM7oiy;#Q92)Q`s1Z|o+#r!x4plOVE8FhzwO1DNH6Mr0~eCF{Q5X`7)pTZgD
zDS6<^7^8^-&lj0+D;QnQym|(O70fIapmmH9vsWCF5k$_(YfNM?R9t7&0jO+dBov;x
z!xT_><}Oq90yecU_vXODRz`6Om~G4fioV@rlm<YzGZ7P^u!A{Mg|<gb^f+KXW<G7D
z?O9Kla&m<|WqNBN-^(}*g{DDf9mND*F<WL~fL=3uA49^KT}>b0-R$jasB~eC)?jgE
zgS<iZusww0#tsgk<jzjq4~2VK?h;J%V1p<C<jI~q4wijvIgUQSWIxM9?>}#LD}@{P
zv(Z|x`ml|QVYe?k;|z!&+d*$Ue|7{_9$?*Ra&VAM{Rn6Q>?iXf5Xk;DA1sGhW*hV#
zW^Fyu7Q{+_hl*g<jrLZDuqms+63V`R88(Hnvwp-F9%09RL+O)8*?Rhwj}t7eGG2r1
zMl-M`u^y)|2+3?|HzZP6zmGst**&ydF^3)cKJ3k9A6mnhJoYy~2;{R5-JrLC9UzZ=
z3Hyy3#`yx<UjeyNwu(GjW$aith+kwq*TJ-MR!ckkOcm^@4yeD$R#57~E!LR=Pz|ho
z2n27lRpfeaW)tb~h!%F)a!9nY&9v@nW4$M!7x&n(-57*+cIM}>zJrYpf<Py`SVUVF
zJ5vs5XRh530(-eC+Op-t&0CDhK<@XSP#I?86tkc(l9SWa^Ay+pC2HfjeFY#1+*G<}
z6S;6&HYRZq6a-A>%6Z&+d0ciM^yYIVZ=$k*>zEAF&T#L`P+7=14~6=(+#gd=I>%Yl
zx1gBYLw<<!+-bU6CERbc%)Y>xHn{@3lzZ<b<gak0cVNX$u6qVR?{NRdqOF5F=ZeaQ
zTucQdo^dKmV87xHJ3_!+BB{r4@0HA#q0&S0;Xaf+CHXp7xKC1b7UEu#4dmGJmiYdR
zQjo;O2<TwRWZFy+BI!5LDGZ?!JKFXTCaJuD#v_vTf1vWHWKJN=50^;Zgx=$lIRdaF
zB&#UVIZ`r)68EDdfzD`)mV8P-&v8PsEd+9@5(^{jJuMlz3#3pobT8yCNM7B>P*zFu
z=$5@Iku8CuTap#SD1GFv<kZKI?~-ht0iJHj_;)ZuJ(61=K=8ig#u~spkSzKKJ$xu}
zv4h@6lD8rN^H}2a7sOvlp3Q|7uO%i+nC2{fPRsh;(ralDaFMzv0NPb*bprx>q~+1j
z;3oa$DKzYrhDX!$=OG>W6s(@oUfOlBPn!4@h?jIMy-mHPlW4-TU+PJ27$4~`l=pR5
zx-%9mLDI^rC<RNKZ$L$e^dQ+AD!my`Ln+N52k#N7geEh`q>}`2hT{jDfO1^weUXMz
znsJB1*OAiSi(pNZ^vPF%iIyIuxN4&Gz7ds4_*FoVWU0{+Z7I@sM*uBVT0tKFH0iJ8
zv`&}iJV2i^q|ua;oh4oNHHIr&I-Hh_r=_~{(3>M2XocQfY5z)$OrBJrIBvf5y<bpi
z!ig690dqlmbviVaN+;w&qD=Y?<(plU-Z%r+a;aqqNQHD8O)e^>*W18SC2ib?YgjD}
z`2pgWq|OaMyDa_ebEv45en<IUSEL6ign3n3LO+FFCv~|E@p|b{3b$O7{zQ?L>n7=t
zC}6iqFU<zIC;j6)ptWO139vh)JIm3TPU)%~v~@|nh5)-qy4DTy_oZK?g7bm&Kn_?Q
zN<HZIdL(^m4)Rz!BNcjIO9Lra$ys(F0bsjj3FK3Ck!?za6|S<=>1f*{GyO3G@@}#*
zjp+Se*{$hd^^nEdfX7p2{VPiQWE*-Q=q3C36M%ZljC)bqFLR+qZHR31G{A()7SO~Y
zOxF1rEJtKV=rKGhlhbW^OcqAI=WtmgCBPq--8hfFM9MyC2XvII%|uJFXxS)Q@t%-v
z*@8Zul==UN#u(YZ&oIuhvO#*p<76-CaN8o;%YSfT&&l4Ss7-}TS_|uM%j(`nsZo|l
zvynkr0wu}E$fp$ptXO{J9e|yehxwuMmfVRl@EYan3lQj(>!#52_ek!07J|>^Z<PYA
zU*4Su9#6BPT1f0Ov!`HofSJz#EIejbLW{N(vsyh^^2}CIK0~qD$CST#%Pi9#ERW2l
zp9SV#g@WSj0gAtAf)Jtj{UcbBtPl!;nW6Y`B3Q~48|Tq!br%&$j^Oc929HLqkJ2F*
zC10iAaFqO%`)vVpKsjwK3_hq#eT}w2<xV>6=8!T_0=*$h#c^<kDmN?uOPF%$I9PF1
zSxpJr$CUMy!4Rnw=uH}>{Oc>oMJugnS`?$)XhZ4Cr<7ZFp)pbUs|y5Elm_}_r73r;
zz>uUXzwts_rm~8T1kX|q9Sil@%DLpiKCKL-N4#8F^C?KBvbqJv)F>x?i?&*&sSzr!
zDzkUNrg~)sZS}maT(}Bgx0G`%z|yRoV27TWT+EdeP}*a@<0&NE%}0`#-NW3Aa(#Ww
z=O;qm&-`E)NPzkK6!Se~zHTH+!RAaR6o#26=;*tRe`5LH_`9%X7;qL1-3Egf7txDt
ziQPi{|EDhUEG^~6Lw4B(di^f<z;-&5bj4Xpfmpfu3L1X?{S?%$dj1{$u8v&?yVh8*
z#@}CNErG3TA6!OH*KHnwzZ-lg2<WgT3ticMl19#Pbp;T1sO#{5C-pL5{?kU2tzEs8
z{rK;2imaQ??!*6gGta(2!G*byOTlDU=Kc?m+|Nv=v;ZH*M6Z8erfm#LevBy!B$yfT
zD_BC9_G4%ZWsbwiDotYSVqsMlqac6#8OH5CI(31mqxW_-GaUK-|94n=hT}iSSTjmj
z3uk|*0N!ynjr{Ntte>e7vXQL*6)cTmXZr&_mR<M}Dic|E9-T{K(<r4NnSHPrZ5iy&
zDJW&KH(fxo*byZl*=zu1ede<#%V1;y`vdJeJ;O$l6RntS_yg+Cv&$)Qs)Rl82%P1t
zZ#gtnur||7khsKtO!voScH%RbUdtY#JMap7>__liXNyfJ-C)HVDBWcLq>Q*G)|}E^
zn%M<3>$t=2d=KJxS-1aY!R&);(A&Y*F9mcbyMZz#AFu=TqIk*%ra_>W-O>y3K6cmN
zbePHjoA4v_I&*)}o9&6>qb!VLuX5xY|IdZ{iWy7q*w@Sm8Xad=vmGYvW>20(Ph8lI
z3n1&te)kaC_ONf?0dZr${|IgFY|j*E+sode)vE`4mX_I`tlxiMSyn>+N-x&5*bb)P
zJhRPEx}Pnf52O!!3y}d#feUAYCz!4K5`rP@R@z<=$~soTn3L=e!(c@$8$Hw<wfHA~
zMC;&1n~nf(@e+D?mmH;3#Gn3s2evF-NEpk$rHyaPXZHbNMd)Yv|4I`>!SJ6wDCKn3
z*?8z%9l0LJYf>mM^~*;c09{*2@%nX-Z6L7Tjr^S(rjqY_<A?c>+B{|^lx=&PLe`FM
z^l9Aj!D`g+VTSwyVK=6XGO*p5A*&$b%k-^)K0k(~tO|c7z_bjY2bfVyPz+_pkHRQ~
zF+b6PBS)APiq{=u76zjf!Ss9!m}sU@0}{jBehcbOG5x*}Ph`F+fu?GvjBKc3$|=?2
z5;N>EG+kyc$<bEJIPXL08ngEsh&M2gX-##9kvG!2r<3`72pW5trWX)=!Hn+&&mbeL
z0NQKj(T|Yd&Hgn8<{x8w3s9NK-l+Wl!@iMTu&0@EpFt*v`8W`^<}%?!Fy?tojUH|J
zOcJFI7BG89qVfzgGX+3}jFQ&aWsJ!|4b>N!=F5;r^n`AX3g!j{v?`exs;pvCDU@5y
zO#Sq~-ldXL;4ZU>yi+ZV+7U3Vj2VSZ?=ySJVfTOurZIlb45PPwKQo@Tm$<N9xv;{O
zy+?ETJ?v(82<&I8P5VH7*!jDl*O&cR4%Q$x`a0AHv$wr4xFPHeI<_K`wV))3D0U+)
zMWWe{X=ZbRT|v)b5<8M!kIAeTC7PXP6Fz`k4jXkDnsQm43gUU}Jz6}RXaDX)WeK~a
z1_Bq@wO;i7EoJja;U#wKU%<Z1?%E9bTJ|En@~*IUw6JMll}%{7%`WUkTO)gf?$jps
zCk_MD%x<8q5uGfiIkf2M{042^>`HPE^{_QdLGH7gY3cQV{cQ`xAF|OD<a)#g?V{)Z
zG22APl00F*p%u+jwwU&D_p&;2iS)6Zr(xPNHpCL<KWCq$puhdB<!n^GU~6rGHo#7y
ze9@O|(P{_`vd(ot@#a2OLLh`Q%K+zbE;$B$iQ#(4m=x}tV<6`_ZI~IpKi4_cE?CpU
zRqsOWZb?EW(2ht7=;9?w7SDq*g_3nL$X83MXyeXp$)PP|ujHE~R1Qd*2b55Ze>GC;
zaS*y84O&QSQUguTo1|wb%zszfmIk3VX>UH@JEaGoLg#(yJQF1;J(iZx?x<(d`L4Je
zFQk1Rp!8ZAH5zDpWYa%;<Nx9d-jq?XWZY}uEwwX4H<u587ceWY(Y$)qlpM5fY>G#R
zf2~@8zkj_;%LIq@w$Qje(*R7zqFVfQW+qae$!^B2nzk={GSBEK+{fJV2fzU)(;4^&
znLF0#L@1-{MJbF~`!m|27&8iRL^JL52~J?b$xocfY@maQl9+|$L&;(mTA(eP@u4r}
zX=WZpQ*#(c3H0VN)t|tuJSLZXDEZ8%*C~CyfJycQ&l%>iEd&dhkY;q|EE7hvf+D6k
z0ea6dDi7!_W>)<J73Y}~G_@;XmMT%Yz?AL=XDPGu2tdo2?&%;GnP+m4a>jxZ@G2M&
zx``^88x*gtVy2KIubSE3069|)v$_$rml(fyP`u1Ub-|b$%$OVu-A%@N7cRjqCUXW9
zHZa`<bX}Rww}95jOr_I_?=iowM5&$Wqs3|mvoH$coy>>i9qeMB{toDF=HDqm>0z*8
zgI*Hv(;Fa}y^#p8OcOguZj)^GEdvHIhxH`)dLCOz{@z0N!!T5yV;d;lq=el{*$HKA
zzz{sp6|9~dB-QLonr_yz*6Sc}gYBRo(_MCbJWO-uh9G(W|9zaOuVL&PJ|IWfxs?z-
z%Kil)6W*z9_rM*_2GH*6<E(W)`V+zS(<b;x%u`T`VyAo$EzztSzIJ%)Je>nACt1A@
z<YL%0ltC5Ch8Z9b$A0z_ET`Dlb5I%2=5~WKfo(zdCnhxS_M();dVLB-$!y_aluRjX
zMi?4X**gXdSr+>hy^#vpP4@wFmOZ)*pk-|70oZ+!{X>8;<?IX!YFDtut08ce{V)-g
zb!^3t7{+?`(j%0vv27G6ZeqWjkB&C83@x|su)}@>^j+5M7)T47KrZ=K6YIMNjcu$|
z5(MwDUtNPy?QFO!RCKWJbp1NnEnk8aFE$;}y4f}KlI~&u83)e$Z2A+lJz&+%AkWwf
z<3OIX{>8AjpFK@C(F-=6yeR|hCKc>`$u_c3G{{!$0Ou>#^dujR?%dF|0Nu;w(o55q
zOH`oJkJCCqB8a>EB}&0uEC;mX-0GoViQxL;AP~oOC&H#vTrbU=)41gnc}eG%nSnEp
zdp8c^`CKx&1<!LXx6qdoF7gMoUEp4qgR_P+GtC0M#HEsl>N0o161LTHYw1mTg}YA=
z-BoVV4`{37Izphgp7Xu~P1m?vbbYRKYm>opgDarJRBm$Cn^1X++x!`B&<3ud9;Mq{
z0i~!ka*-VnZ{kX70oKgr(X-yd-8e__pH{Ak7L{$B`74acJ#OPh^tY4Cr3q3Ockn&5
zb#o7zz}dq|3L$@=3zkCu5$C-brN>;rdSE}{+$teA$Q4JU%~|qX4T0T~F|=dGMKWXq
zSX?El0JQCqoSzL&H_44;`u=!Gj?9Poo)XtB7#eTMk8i??{gQ@9Q12r-M|YsFB#fRM
zKS@RujER+Kwu2>2Vs)3sSz<-00>zRK&Vi*u(t8b+U6Q19y1vrr0jT$oeMlqYEju{^
zl|Hi1TfuTjw)yTGc>Y3Ui|zq5RHkx=rZ8D`AWS?W`>G1$s7y^sgW<B6FJN$lteJdS
zQ8GE@4xW(Nd`!m3glbgA$##wb=qcG^a*@W%f?vXz1lhZE*iDk`4_b62%XW8xq{v#_
z7-+&j;qX=(|0QE+$@Y`&J5aT>a18#xY(^jqT^>T4qF3}T0ME*<CHT93#A_gI=%!cC
z|HkaV|2LkXJh?v${s8|rC(5<>tGyAe4qPn$ZvUtgY8(sP@b@1-3Tp0Qyr$CFGow18
zZ9ik`@<AtjnBhM`l`k`&_Ko^6POo6SKa(&8Jqu=jrtfG7^O&CSP-Y>$k;0f<IdmOi
zX7&I&nK@Sj>?~#$MaT1*VwyppW4=rQDP!Ip0hVfp-3qX)jAsMnZZg~bP`bnLCLR)9
zjD-qD^)YMThEdM!bDGciv#%+-c$`fM`Tw~jKT<N1A2Y28xc<z1+H4lg43UChWw-z)
zhcdadK*E@%pF(F8^U<H+jAk~{=O=-AUWE=MGTUlkK@w9<pX+23!$hDln{k?n;%R0$
zrEujipHL$8Ic5tb3luZ2-T-I?lS^NWO6Cn(mDDl1uhHdt=EGG$Yh?Bmpwz^4#z93h
zQ<sAd++j*71aOL#&~DgxHknSON?@}*0iDRMl%p+)HGM=2lVtYo?Wj#*-=^1gDqDLJ
zeJW=Q&O>h_Td)WUk8v#&UJd7RebIKD%cq?E2u@2+StR$0GLoXWqz!0`=H^U>+zD<A
z-N`4pbuM6u;fiQTV!5wQz?eABhC;5sl2j9ABKS#iXw8UB9Qw{4kaW?$!-JA{5+ENS
zS%LYLG*I$@0(FNZ8JILk4@(+mp)yF)ri4JSgs0T_5Xs4n&>Jd|j{&xuY?L?kUN&YM
z^d`zqEk-F#mO?Z1Oqpf{G-S)pD(L>tlYNl^o&s6f&nOkjzM@T3MY34h9?&N%Yy+#e
zd=zDM$IHt<MCAqfs8*CN%FmvG6<6h7V^_j|4^#)M&|+A6*u_`>Pjgou73Gobsrr`g
zhHk_?<DMuoBMO3uxMmcIQNewUpt6GkqJU_kbQBaY26rne3L<U+H3-@&qPU=76gO}M
zaYfvNdyL@wU1I*oIq$rglR594;m}=Ox9(Q;Raf1rd#f5+R`a(so4?|poxxN2l}FPy
zQ@m7OO?CkO8<~xz%bZ+qokx=lKHUz&-R&9z$KzXye;hJ;C4>ykCExn6wzOS1{7EZt
zAEDn4;t6jPz|=F{9`9b;$;UUbmOO8hzNx_b<a|0M=KWv^sHPkkgwInM`Sv3=(^V#s
zbIO1-=QG%#MrH1hDG;!Lz41i(LKZ~RQ#>mmV=jS3&~hu0Eh1-5CcAwDjB;26#p@kl
z-sA#<z4jH#POy=e06fhu_eXMp6;S(JVe4qkc!RCbfy+IXY>C`s_KqUNU$IU%L04mB
z1G)h<mWTL)Fp=w1KbkC!8qxVUH_;6(@x@YFUq;z!QSUeGHU;m#WvSi3<~KH@ADF&p
z2~{Bfz-CvWA-?6o!vKus`#J+NjyE!=cIQ{OKu`joNcRe_;N_)YypkIyj{(IF-YOB<
zJYHC3_WQFr%j?sY+ZDc+BAl=C*-ydo8lOZ5`mS^HtspAnF68g4<V}2md7m#IfZRh~
zatnGr;<0tH416suo}Y1-eo*08e%>A2-|+<6gIy%Wbff+EBx%A?@Ln#RPedhGN_|Wa
zu}XS~de!xk#${w}y<pAK!09FHMMm!{wksVnU$a>k(MWGtFzwO2WjS;USuBs5S6A)5
z`H;Do3lFgUo;#71yNYwV4Qw^9rj?W6D{s&)LkbTehiNL$3qx)r-#`tO#(ij0_eZ{m
z&gf+DDRi|<Cjay@fH{12TcGUWBR>OO9&b%v!9(1w5#*lWy7%C6lA8)3;w*2Vg8Uq>
za0A^n9!L}Kb>4&yjF<71o5=rB&I4$Pe}f;oh{6i)k%q#X{2|3y-s0hOQ_F4s59;}M
z_=<%P@tkLockcyHuR`*Y-y<XB6%T#{y4SoL`TE}SOG|+Hj?dZ$4S(bHXts!zj`V_R
zagv!Ea;Z`^T*26Xl}>g6;bEx(Z4+FU?$arx3aNx<geOwXPUK!mdq<$GMmpORm<!}B
z<hvGf;ADu%ke3Wc?vVVA1W9M*;qRdK9eMf_G}jwBvL96YPB~A5)+%LkD==H9EIS9x
zH2e%3BpA0T=39Z2tahbclMQNy4RlLU)99!~sv1ofplnyqlS3>+Ev5LHOm!TMeLK}w
z6qui-Mz@7ddsQ26Xkk(_$Ys7?O<V^pa#g3^AULQt_J`a<>WM}m$X6$kPxFZSj=J(O
zquP$X_s7*F8xR(#56GKYq@JXZ>oe-aV2CePvpu2AS#`*ED11>(ulhLJ4QNS5;Fra;
zG#@y;E9eJ3ruE@qIT{k&qp;pkJPy+rcnCWIoT0bcgX^$K^aCBk@9u-XBVvqgQ9N>T
zPv|geEvY%WwgZHX*?b<5u}jI#J<d7_sN<_XfW=qso}-l}M9czf&+(5?I`NhrbeuG`
z1Ncm?p-?ApOFGHuQ=SV<-(4rb$M4p2aPYUKJ)?jr;eZ6@Z^GxGGb2Z%Ab80@piYVD
zh0jx8m!mi&i~3UNuO)zo4Za1)w1xf<6Ylo`wVa+~fm+VEX#gbRsT<y-ErJ05<_(=H
zn#UR##V^&YiE#%<ecA;a`uIg|o$n8(p9M)^XZ_C?c(;4t3{4$37J!9wF<Bd~ztXe)
zqR;@!aaHf2qh~hl*m})AiqHPD=+s|8F0E0*eQ4D@y-_qi&pMS34zsO$;yuPZ8A>c*
z=f@b4E@7?|;INdfACBA_rXLUXn^*^0>t?W_RM%{#o`zlrSO$gX=CY17)*oc^=^DK}
zR@n<uPO>k^ZZ2jE5`lS%ZA?VjW!8EeFz>Q@jUXYF7tq3c8&9W&cMh*Nn9hmp;mx(c
z*~`}+1ciy$Ta8-e^8)$_iyJ(*8Jf3(2U4Wq8Yv_Oyw^(iXc@mwvQ0o)x^%52a+{^f
zJs{sAZ7<WAsTooxDxv-)4axvPv2+*~5q?Br<`58^lXfgZu0#rKL7@euQWQ;|m!wtK
zfcjV(Sq(|c<>7~+MW*ae9)VqQW;H0XWqB{ka%2NtIK5Y%k6o0y(YN(*6<BRA;uLRP
z{(@|xyJxP-eJ?}aEm@a^;-|7x8|0qJmX2txc}l@P@JcW$PZ0OSzf(ek!_4?%CDeNs
zq{A>l<yR?l$y5J>a_0^Bu2TjkLF@+Q3Asy)l&B$KdQJ&6pkc2l7xn_BT=Ad@>lUtM
z2KhauA{zt`lwkqj@<f>d!$ti?$q`U(xw?y1OdC{V5*h1QEzkkZt!l^RNOq_f648aS
zRlgTd_@KJ815l2tXYC=PK+UAn7lmr`fnak}ZAx=PrMl!AfREJ+6e0UeeMS4ezo}!k
zLwv0o@djMtG#6>mSgLU$C&p^cs7cU%jb?#y7U+{TU1{TSv&OMIm~PW_dkQugnkxpB
zWoaw|k>qGf$#y8xsB3|FT9ZxtaA!4w*1%UZ_5!@GYusu1cSCc#4={0MK6!HQYV=K@
z#eGc=atOT81XP0AYfb!g5WLrXWnqNC`C9Ygz*(TZycA3mw96=V;ydjzig!xV+E_!=
zm0ANC4g0mRbOfwGn@kqoWo<e|uwT<YrTEG_+8tiNe4vdZbMcvWIoZt5wV(V0l3r<B
z(9X|W?W4n>tJT^vs69`YlSlnOPS?^Mh4H%ceZgjhu5~d8x9hsqjpI6NI+m8J`}8ab
zkLW7vBX?Yv6b+O!y14t$_ndCVWaKXDqC?Q3%5*0Wfy+JJ=AWR<BV8j`lvV5IltIEv
zT?2Agz0oC6fX_Q!cN6vh8eOZNDE!tuk@mA=%|{-Eh=t~l^HGa3i{RPN^tOc^wd_5M
z@VzLjvdE%{qDK~2&qC5ui)DErueO*O3h}Y}=u$NBBK`Ec5Fzy8w3fwv(KKzP=$~2x
zWs}}S14O32W+BRqKj|0Jk*Xa1INDj-r*9PkXs*6Dh1ML^XXK!)P`~6E2+!%Gt|E6;
z-;~z575a-5CwW_cz7oKDdiyV+VU>Qtr{JAnNF(chu_53+G+b)PY5<*98rtqg?SC+=
zAzLNcFdzq9vW$k@naJiC>KA~*WGEVj${aKNown^B7@F=t?v=rJ4a$BqlsW;p!1C3X
z&@jQWnJ1EEmJ?v>)P3oFRvm{T!Hc&7H@xvEe4cfJ0xM%83?HXL%@*1iXg;hhFl=_x
zF%8?b#wk$St}hwVclgaWP`;A)7=zkA=Bcz7^Ni1#jI!t4ht2}M;`3dRyyZHIYg{Jz
z3<dQ%sm0xovxkQxjr|ioKZUCKT)Bjb`P%w{ORbbmXAbAd`CwM3?M)VV%FGO|eRdK%
zj@XQB^AsH4vO{!~?L8|AftXmHLe9=a{;C|g)!d&(<TP&g!yisd6ImQhjtqdzzlD=q
z-g@F7yxV#+;JXba2h%_YifkM7#P$!1y_EcOO^V0?+qC=(M#Bg6`28r%$0I2pPl&*v
zu7X9Z-sH_4CA0tQyht4jWBrNXxtwL9SF0<TS0Ct*%`T9DT&8zNMe<n~jXFhaaL~sm
zQa{O9f`Z0=g&zTYQ6w<hULi}wdP*fKW8>up4jmd?0lSX*FYo~ErjV1R^Hyt=IxhD?
z^_+6PMX9sj1T=?>Z6@G7)1k7`JG=DbD$c`^mbsJn(V6LGILrf<Yx&-n<l0`xchT9+
zWd4-yfn3j>2cU2R4|4-Bg-`8=Tq-xv%$&)$(#m}Y-$x_yPVTx5-1hVAXoxz%vujcP
zTpmO=|3Th{LB~8^3=!BIj0=SH-O|Q(zdt$EB8}owtfnlbb7D=}U=*wC6uHv(C(#@Q
zQq6fJ#gbVDq+XEXKZStH(uRDnye$=u0Pvoq&H?8~(jF&ZK9$@;kW@>PETBWY?3xRH
zi)5!zRN;HMzBTBQ<eWLseTh7awjGzslc$5{GTGfov*2=Ba{#C-<f30dxKciy1XL{M
zlYz5Z_M(UyAusETC-Z}RZzII7kvCD#Un|d}#oIc0`!a|~mS@s#?Rwd_23$7CDQPH6
zkt5!NE>+I{1SlKj6AgfpCNJI(E}LZTN9Xh|DluD-lqi7|2vMpeQ<&Q&W#nt%Tvo2u
z9nMtz=vSDpDvrlcc1=N)8zvm(>d#QSObJ;4V7YR%7?LU!=`z~lp>iw%YX71v+zpf(
zrTQ84{Z?fpe!jW~%M1K?PMdVxOj6hK4yBFp!SQWlG)|WzHz3&gCmOQ552nDf9?#zc
z(yPoF#Jyh*1iVkU7a*SxrKaiUPcCHFyJf)af29*jhiE9`bofh0h@Oy0-Zal2Xa{cU
z^*vBD#PT?(!oO?_{OQK{nGhTi^AMn@u%lo)E06X|XGhS2<LmA;h0iq~4aj`9haw>2
zSpVyQEnw!uKp)ROA-DS?c#Ki^@7R~LKv>MQbl5eCU7`(}C2S}I!7?_Nb{ki)5vRZ<
zomp)|D{W@Rfg4ceEv!#GL~msd3RK?4+++ZMWV=!U%wSIak;`QJPa?OIdD;NwDoZAt
zs**jTNU;0Nh4#6s*x@JuAFybu>_b*}_UjRAPZQ!}W@?J$89TlaP4EjFR0O)$Y`yUr
zG)>?oF<`osXHb||3cp3WCR=%eADABEy(q-!4v(2alDI7y$5p(Lf*PK2>%%~K#hYgX
z<u|@hAorf<&IEa^6m|(Hanic;$bBctYk{&%>Oo75P157VQ09bmY`1t?!<rfG$>J!J
z&Q3rL%Ow{wdGAa8Qqf*D($8<9;RmTnC@AL1Cu!?%zFa&Wm~nE&DgcvYnN|YJ<-{7~
zR?E&Z2-e8CtDww!IXVtnq{uhvRPa$*Pm|sWc^vr_PRXY8Kq;2PjW#H}ARG2U#Y^()
zcgS6nE9e@v8}i0{0Po3@Y0RsX7rh3z`|@70qN?QCJwg9KZXN)FTG{#?cz=++d(+ca
zba5aMiam|EYn6=?kR&TJXknJBe7zOqX-e2PAlRae8Bbrr?aG{TG;oFzfpG^hg)hk(
z$x>$Q24S|6ehG;Qzmx&YLS-1a35t|jauJ<UO6e?7u@Xd0a#ra}KNVV{G$HTn6{U0_
z2+9;cy5{PpGK^gAx0Htz^LbmTnfr0juV<{Aj;zw|{|@+HXQO{L|0r2(C#|k?*qss3
z+{DVPp}_%G551@EE8eMOyw*(Z+z(!9)gg5%-W@B^C)6$rER2}toC*=Eq;_qAeOuLe
z?rFStyB3dwkuDSPT~fPGn+W0_%pN9u&*_$U@0D^LEPA_OX{YuX>ZmtUKmSHj%+!Cn
zB5*|QYlB{=_M7|`6Q}Fa`Z#sj-v)g}b^F;KGty10QzSDicg#5Z&C+1jgW(Tq;>BEh
zc#a%}e~&JXu2DYz1N*y8a<FsgZ0GPNm}huMRA6vegr~@oxZ9BE;IJ-^glE^;&aty&
zm(E=syEt_1?CcpiZCXf#r%!O0y`7zXNU)E6ps%mJ_l(d^Vbj9=JNbM21lv0}*mbdU
zpz=TdMGEIlT<k-=eS?C-{LTJbG;*?!m>u!oqD@o#ztSw$|JH*NBPHJcFY*8X=m?^t
z%=Lds8=rqs+duU~&)_iMkSITYPhVSG&)@r`=bsTGgQ7xxJZE<E?-Xhq5bhb|J;Tpa
z{7vB<on3p_kB;!45n=D^JtHLAzQ2FO)W~V!_L0*%MFs(T+O#nH=xH;iMudC&`U5Ad
zQ>1@HWQ5RbcuUb*<rZRx!W;jmTz32i3_kr!?fY-`Ci*s;Zff}R2coirp`mD1WNvQK
zKj+%lz5ZImp@Ds(0)^3C{zQ1(Q_bVOsw9(Fl{|5Xn7P@)#`MxzX|_$|Ix9}AFLABt
zS!}Ko6J&iOlUIe}a#CpS%a)==h0-E^)fN>m4PIKjbf#5X%zZ3O^>&-TZ_@C~k#3X5
z^mQNY*2b}G=eobqCYvJjX`{pdy<#QKy;dzm&}qZpO&42Q*i8_da@G36x=LzlVzVv2
z?kL`5nSWwhzuDqNGx6-L-dxP8RvL@WLEPHZ{D{SmwPI<KRyLI#)*mhwt6N(17FpNi
zhNhiKhLqmoLN)Ip0t<OV(I!@-Gi9DOe3+x{>d?KDLw6?!kv-6ItVut}@`k=mcc<=M
zojdz?aqjNm<Qw4a;^N}((5*{n2L~TNziv+c&hh4BE%B;nG9PQz!HeA$U309Wd5ZwC
zGskKOZx<kHk+PS<V~^EP-hY<Zum{-?@dQ~GDSGckk}1BY<gO@3!sR)_&IHnqb3_bM
zc3PY<0o-w}XtfVnPZ7GW4ml4A*UuA{`w4lTm`LfUd15D0VAbpgR*CR9Kw?*m4F>=%
z5l<-VZX^2S)^Ywm7f5qNIVF!pr-Mi`#atx3MT{su2%JdKG7r!)5lYEQk%xqjiWQcJ
zAkAr^n23}miyemm?wBZQDSKLY97fh@iP&(suJj4AfcDM@wA~7kln-c*D5tFZN?~^d
zta=F%gOnW?XN~~5M6^6wmxNMsSL7k#?kU3Z7;qwm*ReY24kWx$s;DKXr|>uqXtG#O
zNsf3z$$Qbe060z?MN$Ez^xr6MAVq1X69A7&6EP={4H0K3+bCVMI!U^06JeCPZxe@*
zvN&NV1g~`ARcK`kWfBXm+A3q=Lyr?#_{gq{(n2d6-g=OzEwpOSM-39~i>%tCDjr2v
QHj3wVE3?gl4YF+bKka}w@&Et;

diff --git a/Debug/Libs/sta-core/src/devices/stm32/bus/spi.d b/Debug/Libs/sta-core/src/devices/stm32/bus/spi.d
index 3be006c..e4cfe16 100644
--- a/Debug/Libs/sta-core/src/devices/stm32/bus/spi.d
+++ b/Debug/Libs/sta-core/src/devices/stm32/bus/spi.d
@@ -1,8 +1,8 @@
 Libs/sta-core/src/devices/stm32/bus/spi.o: \
  ../Libs/sta-core/src/devices/stm32/bus/spi.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/bus/spi.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/bus/spi.hpp \
  ../Core/Inc/sta/config.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
  ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
  ../Core/Inc/stm32f4xx_hal_conf.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
@@ -30,9 +30,9 @@ Libs/sta-core/src/devices/stm32/bus/spi.o: \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/bus/spi.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/bus/spi.hpp:
 ../Core/Inc/sta/config.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
 ../Core/Inc/main.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
 ../Core/Inc/stm32f4xx_hal_conf.h:
diff --git a/Debug/Libs/sta-core/src/devices/stm32/bus/spi.o b/Debug/Libs/sta-core/src/devices/stm32/bus/spi.o
index 1827f55b1f5afbd988d05e8628176c9cbda4ecc3..28cd5faaa18a390f7e99eacabe665ed26807b2fb 100644
GIT binary patch
delta 126958
zcmYhj2UJx@_dd+I?X=tb)g+dv(U{n4?1@Q?CH5r78jVq7VoB6!Ome{r2#BD71u0Ub
zBcdWGpdcWkAOfNw(nJMBY}gR~&*uGoYke-)nKOI#^Xxry&zZ7k4wWy*?|(VovnwMD
z>L#(De_!g*ZQ?`LLEOYU{D1!#M$xUG=)f>sOK0AJk;rdtlp<k^PjU{7O#b{GC9HXn
z#DU@D^OBI`Sf`t;gH$G8wPpjAJz+^G8(Pme$kuja9UPb*4x%_#l&T#ZBs!+2+JM{6
zYOQym<U9Kn3F9C&$mJGohTK8=fkJK$pNX6IS>PNTq}~!vZrnLv;UMkI%gu`qLHT{*
ze?>bO@qagAj8fip-%IFpSN%`ItL4Jioum#@rADsMvb=+o)5^_L`-%?I_jDa9vj4k!
zZ<KcFq+TL*kV(fG|9>UYV8$fxw9h+M+C`~7Afh;&vC6v)_r4`v!z}flBpc5B;q53J
zz`XW8Av4<lX_q_59X9_X!`1PQ0@rB|7+klcktFCx39irI2)L%cb-?v{Bk4SEqtesY
z3EOC=(%_#-{z*88>)+`jt~=A{>hUXGPX&^G&2MxqeMpkjeRRLwK7jzSH>J29kEDXp
zZbbLnR5FHN4cES-skCqeNnGBMLvPR1HF!Mf`y3~RKa&VGVjW4MY@{Fal;o-vbgzk{
z`)*$lLvIUVe_BeK>-O5oi!L|G_sExI?C~v9?dd>mFm4S=x^E%XHDgI~?Gle`rZZ7I
zC?n0NJkl9IiX`_wr~Ak&WU^%~>AN=&|DlhmG&O+kAN8Z_2S1aJ-Ctrya&jb@KmHBT
z1-FooYyM+#ZQVuJolPVey@z0)!wKehh9sKZ<d)lV!md3+_qHYE+?vm+^!i4^W_L7u
zQ7heF8Am#Q<AISojB=stpV@+g9bQ+Er`yv=DK?grCRoYXq-wghsHxQXC6U(kBABN;
zIXY%9)z#9C<i=;z_`VHP%hs;s#D{&U^w~X<jMz&$%Uy|oP!e%|)s5sAH-pFS5LHZo
z);ua+b%qRB`;p|+CuHW#*L45UW->52fxv7f)wp#QIeO@4DqYfxG@t9~S{g{2y*qvs
z{d8ih8%VCqnL*VkzDD{lf=HfRPj1=cN(hj$iV8y9$gka(s9@+lQd0CFGrm*kdha1g
zrmUg+A|25M<dS~BPUO(DMly5n2ubD_kj}41N#}LP&+60B>~CC1vg$Xg>X6+X&e>0s
zs(Uz5l+Pk3YEF=(`#0p)hmT1T(DB+#450h;0Yo9Dl8YX}MDZ$u44eAWy|o|lxGSk8
zLa2EiKKPTaq2JRr>nUkUw$T064o91<cA}fBCu5aa<U3nH_v!iM<DVV%aCu8QJr<Dp
zYnl$P&lAyXFVYN%?_lV7Yd-KJw;c27+AD=zY47M8mcOC<;ay4duX4H<_LI)_eJnly
zcXVX9f5$I3e>D~F9Yj7BoggQYV(3?2Ii5_;tt0ccj(Q)}kj|GgiKxko?wfz2t8-V<
z@${wZoeRWvXE8bI>Prlrf{1NZA+_;pyo7lE`HnjMy^K`5c#vw$5>lP;7fFtFCsL)J
zBt5lM`uK06$elzKW1iCeum-xfwUK7d12XLY3Ed~iNdHF1D_VAg<OA-J=7xH@P9?i`
zhvG(3GB}dxg9<V;YADrvy@Vv5mkIXzE;ZeHH!3~Qo2VD2k#n&ss(n`lX(qbSeeM;K
z7gQ2w@Bj6uPwD<Wju=jDp_U%FkN7X#q<i};3^wRouM#-Kk5p^t(|zA&D%OUR$;i=k
z9k`3kEZRi!1s{=_L(l1%cz+g2<{Idlwt(19I?;9de$sc>l3a40%(ry>l>LX3dA^yd
z@y6~*6q`DcDC<WOed$W(=Nu$SSO`fjd64;pLNeJ)AnI4Asq`>UrJXO4fu1wy8a0V@
zhA$+YJLzQd^IFpR$AhkEcZpf4A|1Uy+5Jspr%bh$JpCh!M6I{zzA>7>9z0!ZUz7Px
z*XX*#iAv9}rFNQ`OZRg!=?S>=Eos)wCAVfc6X(9Jq?2=*bi5o%$LSTxL&lSHzU!#8
zXNW-0f7BK7&diXKZ!uBm@6-MH3uN+TPlDzAMfF>rM{=<b>GN7LxpW&DIMtnWynE2~
z`!A?;@>f*XKj#ukxq{@!`Vw~J2I7pLMw0493VQy-o)A%+ABiUaK``I%NVV@p0?!{q
zp3Zws_m75>u`~Zr4c_c0{i;ROW-mV=lYKYS{lShN<z6)L^czh)D;<g7yW@Q+&87R1
zVT4__2`IZmr*1@A7)=J^htV}cMM|0BbY1)nUFXM>fy`k<cli#P&oq)|)GQ)$dqVQy
zt#lnUk_<1JL$yqArF+d1YS9~y2sOW>e+;Z8tokT%+ULg+MRgnjPMoE>rX*AGj<aNV
z*?y9*en&*|Ix;Y}onU7^BhqE7NI&5Z(w{q@^#AUd0hGm){=Yj38}x{-*;3M!Eh8tE
z<Ps0lF|#t-hf{&(7ouA)p$7bYA%V}XB}sY5AnS-pEgrXTNFJO_*O~7T>9mdkCa+@(
z^YLinS)EST^?S%n_p@Zi^ex?c|3Q^(bR_K3|42T1DKV^BX(wtQ9c5f44h{;3ofeYZ
z8BX_qXk@rHuj6pF<Cjx7ctw(1!}dvW?{PxF^*ud{tIJHP{Tx4Pn}^<{Uq6I6Lpx?x
z$`~?ScV7be=jBw%+a=^g_t)tE6%Mzb5NYKm@-ei5?nAV6-6|zjA2U&(Qj(dxl~kK(
z3u&%>O9o<!6_D?(BK-rUbYDAyG{?>-7mau=6%L<$LXPH*q0$T=YN1#47}_1GF`L5s
zzvL*XUR^@J;__rNP}?z=wR9q{3(%J-99FC$d3nc=^-U+Dn1hL$!eRS8a%C%?ZH2>S
z%!U;X%cqjb)+2;+MklRs7<Pl|y=O4hcu~jG5EMep>;hEG?r^;0$)Dpz&3-IGq!I@?
zKRgBo)#rXkgKGYh!!>OH&5-nyM#%oBVQcvXt<!5eWk2rF`$GCR?&mxWg5KP}T2T6(
zc02CB_j3jJ4`Fk_GH=y;aQ?>~^vEt-v4-Y<D@M_1v~CkU1Ann?D6qG`56O1s<>zqF
zjp>_(#D{rB^AcZX=3~^ukNM*gatE1>8<8Ah!XE&3n5q5&M*W$lCRjbn%o~Qb31GA#
zfCn-Mzl7l+W>qmXgPEC2;Oa4E!!COMLYN*rq@hd!2ktN?(g{g8vyH~b<IJ^bV2fa;
z4gz;1^V38Cq8QUwG)y#ey$;+lj5~GjvCOs<kj61<Qy`3I8s10l1QSC8WdgHe58x-6
ze?^ofGX5T*KE*7mrup}2=2tzWXBc<t%9EIx`@nXV*&2adGUJg6^C?V381Uzq>yZ$i
zXPl@XPGvqg1ZUEi0dL`bIulGC)&(Xj3Yr(0W&SXq!4%S?f1MGPC@W;bN5Jk4X2?Rc
zbrF-}!=n9*nMvtDlrY8T;pr{r`1jzx&AiG0u#8zl{a-ob`w5aNrnnIXYnY8%(A;BI
zxB_sWIZmU_1Lpl<Xy8U>#xdX?F?yQwKW6$gf~=WY`4&}r!nm!3@F^4U2FWw#Mh(o`
zpEHVcD15<e`x4R?=JqTgUNX97<X$nuK7yxjnAT<(e9Oc<M@3tis1%g7GbZ|dog|es
z-`XZQ<pmG-NXps;*vJ1~qp6=6lK(XzYd)dAd2QS&7+U8%1!mXpUW5BTJ{WIz_@8?B
zpZY+h|8rWv4LEWb*MXm)50Vc`>I!3n`_Vua$SlArkJuHmoG_S^YZ~x^DTeI;7yHpO
zL;}dN>}pT6gd+Jvkg)Y#V2wK;0|}p~VE(7kZ4pL3dGA*AsCLD6W+<&GcQ7Adpinq7
zuIEr?7ly^WPvOdZkCnfC57Y1=-tD7IG);m7n8$aa@{(EjIb43nT%}3oPKo<sXu3*H
zehp_1NIYmlbx_hh0J#8(p9j2+lZ;sbT$;qN6Symq_7<$#G5+EWf4LR~oqT?WR=2`A
zpzCkg4f&Y=B+#6lfry3t_o3@>bz{0K;6fN<Uk=@K%%rWT<TYkQB08YwOz*@0*Z9Je
z`5@HF*P%vz-L9j-K3R#uMe%93f6*89Oa7O0ko2dRhr&KUipiZ~U{E!>twBpgw9{aD
zC7d48a0CrM)O!y67&hi2{1~1ZiC=nzJ`LBAp)|eutd^!gU+8wAbn?hUaBLRi1pS3S
z^?=UG*e}7e-v1+%ZXTnD+=-dvj><VRm;L~^H}lhLn*aDR7wNqZX4cD*#4x=$ke+6~
z{sC?$F&*BYWjfqXW;*;&VLB>sj_Ihud4{}JTx2>blEF|-I-Ucem_`VbcoSFKM)IX|
zMFhO=w(TrD?OB4Rkbh)%`2Y?1X~A4v2X^-Ya<GR#RdB&-I5Vap50Y`Ge}zXA_bi0(
z-#E}h>)Y!x(9PD_rT;T!*<1k1_rLxG*$>~)i`XafA6$nH?+@eS`es4?%|Ked&eqZ!
z>BzigVbF=GvhN4cHs;zwWc`?y7LXrgChUT1hnVkZRuIhS{sG4^=Er9MhA>kw$f2)$
zN4Pj<4jy{+b#^sWl9+zAfS+aZqoA40I8z`XlUcC^fJ=<mX=r9K;&D`^h*>`yD#eUb
zA<foGn7{i0U&p+rCB%K^E2_)`rce#l7H0b;;9oMI_k_V$%=bGW+$9O?49(pV{aYAx
zmfSZ&=p*^+JtV#o`vH*oNq)Hj@53bi!5|Bl3|)(|<C61pfjcePzXd91B>!%d;rCCH
zq|;h4OJe8=M7HF=Rutw-7PTX}Dfzeugm)z0(Qj5EsUdu|BqR}yTPOMF1#%4%H#M58
zMe^+*sEec2Yc0rjN_(mRaFc$x2b%8E4=@JH{iM^&z<E$w+Z~!AQtoe>|AtDXQ-L@k
z9h3u03DRLJL3%+tVH)rkr8$`VcRWp9tzQE4;p#?Yd&v8t-aXfER{XE*b15c7@-Oat
z!`8%ZDY*Z7R5h+EzLfmmv)HNjd(^+rqGcfc<kBr%`%nEC*FpB9-M}&QJ&K5oxQkhX
zd{oRTNX8zxkM^GMbSfO4ShEJIQ*|<2=XBo=`2uMbO#M8s1*N}zG7;CcL!N@+kLXg=
zAw}Ua8#Owoc;yVE=M~OVP?V{#P{nc;S7azFRG4?b)-8p7whBynZ2V%VK4ViyL&u3<
z)sDLE<A;9%)kO8&a}cJe@4kfPecJR{$nDqqo%+9LKbDa+!?9aT3I*=&FzXO|l~*ti
zF}PvGI$?&en)&Srp0^sNC=AJdNp?1j9gx&Tb7+5GNj^=q{3Jt?kQ|Z(w!^W*k`Z0u
zw7+C+3zDOf*%_b-l<fTuxgd#}Cc(!f<zJ)XA(FWs@bZ*IeFDj8$!c1oUzhaufft36
zjhEqbktC89v&E7P#lYQ^48yu#UMjJShR}Xn5=G15GKm{Kp?4&%38;F7#JvQnm6GA>
zkgJmXKry%)Nw3u)t(6R+Fln76{S_*6Uy?Kd!iN&=YOvKyX4ZhEQPO1)0FNXoA)t1|
zEE8o;(m%?OY?sR317L@A@DK2QmtAUm3~zQz_tIqkxU@(GX@vB`3g8Q+Lz9rZAsvFa
zvAkHCb{7Uqq|0L=ER`OmMd&T57sV~gq`tHuFP8=`Mp7YdUJm$OX&>sns-?_gG(wFu
zH5|EnQlEan)k)pYf$V|Qeys@EhtfD2l^dkz)`7cGT1n=cq-!Z;@>n|YEmWUK4Q9|h
zm3mNg?zwaoEhk?{mv|%hQX2CDReL3!MWezS>DW8Ky_Mdj`o5FSRY9{&+J6ly=p<Wv
z7S-J*W7j~qQ#Q~}q2*n&9-%PkEPGmlin_?`zoQm=WL=_Q&`ov$ubJFK7S#&2y)xx(
z0QbrE9EPTsZ1h%`-!I#xh2{a-%`qtRl~oT!;wKw23xLD2izlISM3zLcy`!>+H{nHq
ztil99knH!nb`%E7RHxxosBEw&ya<!kQmY@At)-x2gv_!Vh$vaxSRkTh&BKt3l}+yg
zwm8{IPk3=cCL0G_f^79T2oq)L#drix$y|y7NRk~{3TMvBA_syjMOG36_&M1Z-Jy~y
zd!psg|E0;QXbpNn_8*oG@{6+MY#=gamw0$_Np^&0VA-<yg%IY*mSjRRS2oECx39>0
za!9Vq28@HsHQ6C-bI1#1dE>xxU3O?coVg)WQgpRQ_WC+1SR#{r29}$$022VWWS{zA
z{VTsM`<kM}<+93ZBzI&#I)mn}?0OrjRw;W!E6^HQ+f~ri%9^($sgunc0G0bP*IO|0
zQ1)YQ2<v5qw~;)OMbP-zB<s8mP0}p8rUA<n*{**<{Y>`tJ9z(G7Ig<@EwY)O0N7v3
z`fUK)YnfppRNu&Qu7b2x_SbJ{uXnP=$DrdV?@WshCwadI0B)Bb_z^Ta<ZHUYwO#W1
z8EDJh@){HDy2#J4z`4r(XhGp7f5$`9T|RvQEbNv0--ZQGxpW?IUUK&-5PI9?1CycS
zBOfpcCVb_2wJ>;4?nHC(L-K>4gZqelb`Plf%f}x8K0w|n0}UJ~e>NN{!Sa#+0C!9t
zQ%FyceD6U3!sP$OBNri$_y(3D<*l?{jh0^vg=UOAFby8Y$$QhnAYN|2rG)gPJQaIc
z@<jPe8ZA%D#}<L+jC_3s?4Ff>PSN3Hd1qQ<pOg0}g35V${wCnl<QshfPnUl{ldqfd
zK0e5m%16**rA%Hq9=LM(z~^wLLS8)uWq0M?u@F|t$Atl2EuUehJ(OB3_RwDU<hv;D
zbYGtOA)I+2|27w%Ix2=<MB=2FH5S6{iZj2$ryUB@EI6}EF>@pUyA|(f^l(v3&VeOY
zMe9^>yDNeydgh_9^@72Die)sac`4E}VCaBC%LCw}=<P)BpP$096b*GyvGoFU4l5>7
zjPHnIaXNqniVb6syROLi5t>DcziN;xR(O67pKdC;j{=}n(c*&KZN*#)OP4AB8UW2Z
ziY}ibSD{!p8va%)&MJ_rQfMeJRHL|S0Clax5=rsrI>o37Aib~ndO2$NP%$qKF4ij^
ztOc-9vHl0BK2r3%3`@-lZyJN2D7qwo=D8v&7q}OS{}Q12O7Z2d@Zz<i%VU(aDw<ZI
zhVK+Z#sc21DDj7iBir^27Phe~@=>;(-T#W#f3fU6lE$%~&tc*Od*ut5NMOScf-R99
zc?u1Dik(3FDQDO}Zz7k(F63Z0nVq)@G%4)i4<J0xR;3}A%4W?%SvtF&q6HV&TAI0L
zu$|{ZC6hf&0rf04s1(9%c6SyG*)Ow^L9m<4mQ#<K$0{h;bd~j{@J&8zZN+a`!2Uo(
zM<J{G0=XOPxAY(uvkY~GC2SHx5b{#i8GEMkTkKdV8n28^Z-Mva>^hp*Rj^~R*DAlu
zCeDLvRqUv*V7Hpx_Xzgx^<+Jrk*#AhqCxYJeRiE1pN*mD*dsQ6GK5WRckhASjP_!R
z9JR2`6Cr!edTfWr8}>PcZr`z6>3wfw=S_rJN6vL5gif4`J968(=?~%A4$d_K)^~AE
z=aB5?PWJ-9g*%uJ&s@3QR0lUMa077e+<zC4?Bz;mlgyKI-wL=F*I<tY!kc@Sj^qG$
zcsp9ehcl<Zr;A)qdebtv_dZ9G#qHeyVK!%65A(TP=3><I3YU`!OINvR&p>*OJI=yj
z0e9*<2(NSbUxMrgmrkp|B5sQ>SZ;E=Xv3_OtEC-=+uWy15vh`wald=Qd<D1Z7_}(Z
zvoCVh+!&fS)^IC``yRKs4rO&*&`#hVa1P_a{gB&BvyBFB&OKD7kt>OWhfUn%X#hOt
zZVrIT6RzKMBu}}BI+Q)<wmyRQFSy#TA$-LR*he$<*PJuWa^7-L6kBZN27C;*c1}y{
zR!3f>iQzV0mV?}Oe%x$u@8loRX7Vn+Zypk7z90~laN!6331{~3eza}q#=otFqaOV7
zeSq)fuTWHMAD_7kIWNBU5LgcIeVrJ*DL(wJOR($5yGBFjAfG|Yjw5{VS+M!@0oY-e
z2l9t+K_!T<C`9fUU+#p;gz&SA;C2`vHU^f$d6_rLBKXB*H<IW2z>8?UjHazIe6xTg
zj<-C3FrH7MUh*V=aumF<C-Qgaf%`NcSdZikpRf{@DdDe1faVr|mo{o{^NAV2m-ET7
zNbc}KvtjoxzrH^lt>mXre7A<L9spb|pLGUq*YW1fz}@F3Ob6#felm@I^?dJf5I*8%
zv~}6U{~L$g6FYwifmr!d-ai}o=ln+6>v+LqV+9j1epWq_SA6HMQMI@HQZnDl|FZzK
zXydhKK-$i`!~^ameD4mnZNiuN;NBr@(x7aoFo!l7b_=W1q2et39tNDNaN{;K_XtCu
zLB(CL-=-(fL-3)EQBPqOP3QIrVU8&D7W}3HxL?Sd51@}QUk4Rm;oT7c5`<ZEAUr9w
zQvY;HNW6^ZIxXCzXi1VV;Wv13R#-r9Op4GfMcFywQv@vJsX`NlvC{-C%~vl7S#}>-
zx+tWrMmAIEYyjet;4%TK*}?`2+2;t~H^HY|;WC9;t_VSMkh><tW`i_e*g_l0g~FlL
zD7zsv(^{`sm`QsmCBo7Euv99nu;4eiC4?-3g)-qI+VU$G4%9&9t{~}xNR7NwSU|h(
z)q*E2RcnObXg~6vFqx(<b;5#rBoBlWOCWqG`0WNwgYd&?2pffW2!6|(gm1n@lROrj
zXMyaA@ZWKiJr#m!@P01bX@sR0LgO?fuY^%9NL~v$gJJKj@K>W0?_aC%jAjIFf~E?H
zcEQ5{OHSej3gB%MbM<ilka&>RBZtM!^d$I;p1(rnsMzHSoCy@ieFiUr#J%w_e@r||
zbIK6$B<)UxiMypp!bP96P>B$ScSkN#tfOT?v^We)CA&OEoN^78;=}}+5yXpHn(-xw
z2?8vg6jNxg`ji+k3M!{X>xZzLB(|PHeb0&?l;dYg5nT$AoD&Bfg)mK=I}n=bVtzbw
z7excbG&97^1IT5GIq_(jY%!fQFN=}0Vb7i`u9U*>Jh5##vRB0xf8_GT%FD<Vh|M&N
z6pBNdL3%?hq2In(oZ<<5i5OpovQly5Hso%JUhe}}CQhRPx?HS#jQUoHA5(bwuK43g
z;Ht#=<#482tXu->T5-@JxP8wq{+AD(`=SdyUJt~4Gw}7|G}@+Z5YNRRc_$WxgKeiW
z;AbRW%KvCi>8-4DgHQXFMRd&LfbxrKBtFW77ZCa?vnbf?r(Ay-fP+ed2?h@<iz(W9
zM7dB8FZ`8*55uRUO8cj@>J3nCAa4SdpAG>qNcp-4a=}WsR9FgC+Fk<@ru@JR4<nRk
z1Hl%l+%gryJmve(p>kEZmipIg$}aR8<}2;g%@!!X9*pF=^4%LGh02t_k=#&TCtQ(o
zodrp;@}fNvX^HX{jxNb>DqSf`S*e`CLs+G}U5DD&D!WD@d7w;_!?lOXEZXa?SC0J$
zNrUn>#djN(WwiPANV#-_0ygl!Ydi&CyI-vW<ink%Xy6{)c}RNRC_o*0om&cTKT7BU
zxxIHIJurP3H}HMTQLMjjQ96`9Nv74*r*f)ozf;t@{YQ<2lLLYo=ntGX5fp=lm4I~c
zALPW4nG=8-`q$^sA2ui*6&Sv<5e7!2?T2LK`Q>2yY<D8Aqe>|THTwQGu#K_ry$iZ=
zo_V;AFQq4OLVF05J|9m({V#fa0>cwG`@*d$&0`_|!Ql$-SJ;Nb<mN{?FtCl;_!WF{
zXB=(F9b$$UpccSPp9RJcCiZs-BNzwz31gYaYb?<C@5=Vw3$;D0y_Wh>H`ePaOuMtp
zC7?W57aIKbva>u<=E**z_{ctX97V~zScaw}-fY+bc(9*cN-@F%?Axsn`mjnm1?9`W
zY((P69zO`9huQ90a2{bN4S+C!b);EaAbaRJY9GY*w$olxFgu<W?xF0Y)j))?3;u&|
z;jDKw%8s+UrlBl?)ek`u$v$5KFQV9gmcwo|`>-=eW7q)_B(ZET?Zd>eTWJd+p3Pnl
z;R&{&4Vnq;&kG?u$*z^bLLxg|L~@G#&5c$Hr`a990eFUeNo$%UwvI-qv#gmG1<9=X
z4>*&;PWOf1=h#hd@aa6e;ylVy*|wKR(%7L%5ME?gQafd^1v)sI$&R>!vP<lx@epRQ
zwc}wSoBikroXKH7egd<X*@6ICDO_O-hQmZ28~ndX^8HI_^=oX^C&1^kU)~0=fL*2n
z&2@J5C}<Y40}G&1%$_6C64ti_q&M06JxEH~w-kW7#a^S>-)*+42Q<sr%@n~YXM+{s
zyu;2U^A+r-eA=nI%Vz(BCaq-OAA(v`v4gQGfr<2W`t57j?v<daWeX_gcaJsF7JeN&
zfFhmu+23i|^MJibb|12LDVAE#&Y>k-1N$lM1vawRN1*HxYp^2M#2%`I`NwSD0VK_A
z)&<zJKVkDJZ2y#%jD;7^*gmwZea@!RsgxHimjQz<Y%CoQe93n24wX0Tyc#5L*;#2Q
zYhz~~gl0QiLtF8VoNp6^PF!Ca%64*|WMVg$=#9jgd!K=(D_67}@I72<6I9&n+}L9%
zbmszTgVTdMf;Pb{J){shPp-=^Al=6`xgh7o?Q2BNn=7gUem^ItN9X|e?eEC>axN5h
z@Z)-rYX`Y+GGHl)`}=1k!Q3C-@aY)$>sSCnxLeg|pir)cy2CKeK2(X84d>EYpmUr%
zuK`U2_lo+VNUj@2!=kv#IQSIJh0^)Q7*1mYK9&pk11fRc1}TK`oI3^JPjG%SAWYzv
zB?EVoTQCN>L~ht`;5^0gv;aNLeMcvy&Tu{y(MaN=?L4Y>mfLy^o+fi)6!=f!o_zt~
zIZiVS`14#3ni-~Y^~X_`#uZaUF`bjfBX@y2HVl?7az1n<FN6DcC(1Ip>%HMj7B_Av
zII}tH1d!!$$_-Gt%$>$w8<sC;sQbLa#h2LeR^@TyDEfDmvkrm5Yuq4mF`vs>3}FEm
z*#wpA+}N*RsgT>?3ho=+q8g|aao>Cc(qc~bA(9gA{#2;k<UDCrP|DTU0C$V4q&U!R
z?l7HtEaOabz*){sp@-!T_jncU6jg9<Xcl&tOEbZIC09!;r7CV19o4AjBow8o;Xb2a
zS}mv81kHP#Tm{WKt_#h0?sLOpq4|JY))|@)IZFndsppQLf~5v-+lMG?<ics;@Q538
z19qFZ=AnQ;=0clsyi4B9wbOj$31>S2#8YnC0+2rAc6eXtZ|pmmj$!!nef~w!A-?(r
zDsh<ir~R=b{Cx@vV}(K;+fn{EuK`B8VkKM%=IylQb&TIeLtY5~6)opN`OlXi3FCiW
zi6opqw+z3-asIFw;0XRcb>ETvU-TwN@nQ(dV)@S01H|zuv^yEk-`a)T3BG9=R1)}c
zAEE{)`Bv)A68W*7uy=~L*{6f%G{2QLh0gF_(7T(&=Vd^6mLEYqK{8*_01s360Gb+{
z;~Q!6a-Q$@D||}jKczDZY5bC#fT#04h9kMa52pV9BJUUp%?$qTmq;@CMX7M+67Nbw
zaTZ_u3e?$rm(Q{7E6?F&NdR8vc^1u+%WF=e&93mmr)c>+{wWR5SNZwT(7eXap>q-W
z{B8=37VyRx&|K$lj>Jz@$OruZ?i+kPg@TLta0)pT^VPH`S;EKDNu!(m1>!8_7j}W>
zEq>5S>dbHR`c<GQ;}1=Sw46V`4|Tf3yHZ6f_%@nZ+~wD0!KX@o25rMs@x6D#r&``b
zA(nf*2lWeed@Ds2@AIEfeIM|;M6f*Mf0_oBdj4u0a1H!2ifuIVd6mdL;y>(4lj$bj
z=@S4S^K0p(TQeU-TWL@D@6%AHr+j1zRG;x*(E-Bed=+h5z2FzppxMIzI19p;{D${I
z`ieg}0=d_`iw14@h7UKvi?@6g1)W=YW;B}Q9X}%%@HW0d2Se?A(GT#@?kM!6C7+Y9
z>j+4<32hOOZWor(l6;2{?hDnOg1ZMucL}{_gJ!o79Slup;Y9+f?ILUqho-BL^$?c!
z2$l3exCxtoK~uU5%ROMwLtyD3#$LgA1aMDb25mp>6NFR1dD(>*)1c}t1kr@sM|iLd
zmVAYWTTtjHjGBquK_T=cl0!n<S8(RAu%Aee2-CDM=r1hsKyp;5qJb?y7)Ym_0)@8z
zfCmX{e?u-<_&x|0jtRT1U<nb<(J~=aSWfY{Fu~q98g|2ladfu(xN!Iz<RXNd-f%He
z@S$mYl#tjLen$)KG@FSLl4*SsD-5A`EKZn7C*k6SUlNczA*`pP=?OwNTC|)L-q18A
zQ79-w?vya$E96cKw<*MUMwltUe3G!$POH1K!aq;pVzS`*E2JsHzHdQ#PPi5d;d$Y7
zG=!-_1vO%t;8u^abU~nn?ghbRF-R{8bt93>5K<4qi%elCZLVDs9{mGLS;Dp`_>?W|
ze}yDRm~jZsTow!w$mI$jccRYxity1!n7Ag4rYA68SWeOP0%818G}Lur=^2m~3OOU7
zc|(XX!BUYBPa}V^@P-a8mk4$@7`!QHln|B*_ICi>68esV@V4Mkf}~7169Q+-h1vmN
zxg(6B&`^c2B~rxucUQRZ47I2fX8r<Tm2hGY3af<$be6V87`+L=S|R2S2=58ir=eLV
zoO%M9`@)DXq4GcwPD16Ou(&JA>V@ePa&Hh`(h;OaA!IYE^hlUbJHt)FiKWOrM$M2k
z3#)NT!j9GVX*zQCRCx3T_-6w92~?j8L+CwvA+#t#(;`F+f%%uhc-jeiCG;ToUkj(H
z3w|Ty&IjPF;FgWDRzX3*pm#zd?LxE(zf!EdUAVdcE#oLoqjLyO;$m0iwuzMtEZDb;
zw=P0whdBQ<@H@pi8jE&`S)s7ITl~BbIcG660|*y!7wzD?i8((5;4TiGft-gZnn1Hp
ztf&OQOZ1_&nzy)#_7;4^qE%4w6}Nl~fBnRz^n)H2-{JEY`4Mpe9enk-i|4i=4HP|o
zf{7sUpfd~xi{Gw53x$fWuOJsDE`0)ExR^xycah>w>Qkab@g#)N;!iZsixGQLU@cZ`
zxd-kzaV{+p;zjNZoH-$8P}nL#+`0&ko)pspp_wS=g@EOhIQIsf2s$nPP0^e)qMkzb
zN#dF?AkK<?Vv!_^3VLHx#AnZ8>71DT2HfYxv_#}m#iTm8ohDl9p^`41osI^+ARhCc
zKfJR&lQw&@#7@+qWsBzqq78DyNwiUSS=>Acc5=m26oI=U&Ke1Hp4f?A)T?6eVvt-D
zYiWL#FOH!1ra=7VPq=bJ^rrxAk(fUbNwK(L4X8`R$UQK0Q~Y))SW3kQv>SX&EVZuy
z{<gTh48SsRqYXOcVk50{?udJLLZ?FXqCL;M;)T1gTPZG}2d_%pSr0(9_%H1?)`%}C
zidic<4hHU?7(N1=b>f8pklh#CXe;A^$R$AdP`u#}K)pEp05}`OI|5CR8pY}UAblh*
zPl2>a{Q3}pkH!6WA#4^SDO~$RY@!+WQ?c_uXp(2*7$Xcm7q`)4{6bty)1?-1!F0f1
ziuPS7dnFF(4G&+7J^lpXjo3&lp||2L+Uji;6TMOPPF#0Ffj7HNoZbly)h<3v1Dm5V
zjp9sB%DJBcu}%5&Ta@io%HBb^OUXZmiQUSh^fNgt+v)Vbi?WqA7G0IOgTTE<`O_D`
zxhZ$k!76v<ZCYD<D7P!1vR8SYqPCvO@pPVVpE7Nu1Kw;e<zF;S^H%!K17g2&5S=GE
zpzKB~dLQMf2H5pgj-`DwKV`uH*gdEWpvC1O<uck@IIJA11^kHeX$6G-%FQ&5KB^qN
z5M%+$pJ<2(RQ3^JK1it^hBgdVs(yybG37Ig&D%qi@pSMeRGCcY3c{4DR>FL^vbYX~
z$CZu0LKvZBX24RUvc&;DMJbox1|V8Fl6LlDlox417OSj34wX3Npve%%E0=1(azeS_
zA6QCICUk-`CzbzFs6J7-P6p01%KIN6mt<FteTgPLtBiaG(q!eG^GH&Z4OOVqIc51~
z(41G6-GJRx<&rqCr76eId9QS36&<d<pj;9J_(kP~?eHQ)+2o0`Ol9}MFmXvaH57m>
zW%VE=*~$ny1(Tz^eHLYxm6vE5m8-Nzegwa-C~xJ1CQqp$?yE}qcTl~i^rb!Re5I7O
za|@Kg?(pKeGLf3QP+9Q{k{ikxFZf%ed~*o!V&$-QXqG5FQ&DzPIfDkeQstIWFnCLu
zya_6|m3f!JS*FaIjHE)@*M1Cs-&KBG4b@6zr=O72C@+gBtX1y+5M}q2qo@mepiGQ{
zPY;#lVJNFtE}~KFky5t-2Ah<V&H?vWd3^>d`c(P-bQpZ5^y}F5Q#w&+@Io1%1C|zL
ztsc3T%7zGd_(qxk%nsGJ%BTgPX;pgD>6drPd<iVIDNoS({C4Fl8N6^*6;qtoNmZDN
z+%}anz1!PW#%S2xp<2-e@SUpuP5|suHP9?!x2lM`D`(Zt6119&>YFBTx~d9aqim0=
zWhYqNRGY5QfdY5cVTwe1sGL6ley?icEU<a1+>XK1eJcAcnDA1?R083xIzJF9`&Cg(
zksMHcyBjzkRr`97`l_ymBj=}jO%M4&Rn;T3(;=0wE8vG!7wBxp5taBJ5`Wbf;Se5G
zx%H)yH9+-%#+X1=?*P;=NcEc|fWay!CkT(Ju2bkcM74~zmqJy$`hz=6b%!GF;VJ_K
zX^yK5wQw{-b!a)@k*Zgr^p2?Z(Akb?RX6%6VpL^=Q5LKE@eMTNRQqp(GePBDi8A|1
z)o0Y{CaQj#3WH}<(N9s)B$Y4ubXIkmdd+0j7+MylsDjTz^PFmD7P!x=`gTQGs_G%_
z2BfK07=TMxE&2<j7gT-P0l28j=mSd`s#!{y&s6<F1}~{r?nPa)R8wiwCEKnVFbwz{
zRd6Jd%c>;Wl+IPnp%X|~RR6sLFi$n3Gb~+I9ikEPnraEf`SMkY@4;4}dM^%a*H!=Y
zginR4!$W|(p;|o#Ns;PYJj#ky-5jA=qMExMKiW;zxKOZ^s+LkymZ|IkwB=i_vZVoW
zM|C_J1}juu<PhFfrTz%jO4ap?NNQAbsWYfmrF4X3RljF}tx2{1FVy0(Y8?riRRd@k
zd!jmh3oK7nV=sX7nd&s1FnO-p_7o~FRCeq!%3D<Co~Xo2)g$|QxbaFg*a+Zj)dC8r
zyiw(DK<=%|nO0M+s*UTAyi>V;hNMlUq3=1`RZ*{C-ch}gdOaugQ72g1rZ!H5Guzct
zijeM5E2-DpslG#}uy(1vXCm3Hj-qg|v-%f0)#jo$-l3JHt9s#|kh-ZabOnvO`q?0m
zdZ;C(XuZAaieI4Osdl6nexG{d1eAHHU#&r%yw#3$G;F{6i<xlkfchGpmGDu&ruC_>
zy893q^ixlu{iuWL(BB|Dq`pbsA6Ad=43;D6A2Vp1#$R1U=T45Qf8;<Kpe|VizXR3o
z^gT$BdI}vK4OSnF0^2e5-cG=WsNc{uE>xW~1%NPh)daX5q3%Y9G$YjoN0EzCr&YkG
zXmzjmp%SBBYXTrveeW*F;?#=|BNwl>VU}Z;pHMfQMb#42+V1e;q<Yb0<Pz0)CGh){
zx(c5@$WN<B(TI0O{ZBvOlhj@4kkMIn?h-hYtS+ZmL5lhZ>Zi`BXGQ{kUj03dsj2E=
z6w^vmKX(OLx?1})k_+lu3b$WWyV72-JwyE!eM*|Cjtzl{OX`sxz-OuF(|R#my}BID
zmZP4}pzN|bH5@g}Rev!EfGg@l^dRS{&(PR-RsE3m?XIb7_k%QF9b|-~1?mzOK3!LD
zje%yN`pFhJdPDu+=MWaD)0`nJwyQ@hfr%1z#T5W=s--z#D^-u7+4^nuAUnJ$Q!5j}
zR<2H<lL&XzPy7L_P*3uK=3VvPPav#R&(DHpmAYgKs$H%A_)|Djqh3e`Yt^Qg$lX(G
zV!(M{J)&dRLw&pxgb&sBz7v6{S9`t$O@lgw#_dKmM@M)bskcxhvPpe~j>$b%xAg(O
zS?x^6)t{*2sb!w3y&RBxp<cKOnl0)+G)BEtb5!<9?YR?fzgFkdsew1@DV}K9x9aR~
z;C8F}$Vk|Gr=D#00BM^#a4~A%u6}eJiKE7gnr*x0d~X1EXnv&$<W9|mYp}FSlfxj{
ztufO3=d5w0y+{{L4aKruH8MK8utzgf4HY-ddyQam*VtpA;-Q&J6V`p206(aBX*|xr
z3vbQqb@cx2*9^J~69+W!I)T(j6I=kHuV(WN==f>2&Vd&PHRWMQ4ryB2P<B`|p%rXL
zG^Z#U;jcO71cOI4(e*GGpz)#88G)K#m%(n3Cb|r55v*BCGu307$8^{@M8nX2Zm1^Z
z36J+LOcUM<I^miv0RSG?IJ<x?LgPIas*##YK1iZ8Nz_2mn#M0-H%4PU3YAz*6SY&E
zChj#X#cTf93lk?aAJD=nK{J4MMNVpB{NQh*#{3Y%Q<}eM9(Y>w%o~6+nhkh7?D8Z{
z)qa>itNHUskS1&DCd0Rs|M`@vS;e6&O_R_H?sU!jwBos-k^PL^Ma^flG|bT4?gtMu
zHPd#3`;un$cv#BPq?%zON8_^uWS2Fbec(l|<{9l%UeUa3KrT<SGzvKTRn2o+<>YHV
z{~Fl>%>h?5!gb9jy#OrK?Bv0ALz6~vk0MPMdI4@~rk;VLrJCwN@Zy%Ha~}wAYr?t!
zP^L*m=uKX(X`O)Px}z!X33!F(mqAGGYFucyt5Q?G5RO)98l<pSZP)Bg0is6ZR0p<N
z%{yA6-P4Sxb0l>dp2mawn&o@J{Xk=&t-*(yT-qJ3*G#70utC$AV)u=jiS+0^(#*bt
zq)B7OexdxaX3awYnl;4~E`Or=^$C1x(G*MI%uCI73X;9j*ta!6`dZVSTIh{N+68QH
zH8Hd-YSr+&P_=iOe)RQmn<j#`QQ9@D3E-$T`@=OS?U%H3u}!-@17+K_uJl3f4(&vm
zk?hv)p+&2+b{WoG$X&D}enH}@4W~)z9_{Y8@X$?LV5cdCyY^rMq#oL-^N{S-PNBir
zOItk|&UkA@3YYKKeoE&=4`?N{&*h_iP1W|*9-|{Qe%k3hp>j~WZx0L}(#mFo^RV`_
zRFoajW<EsXuN^><{6K91?LP-;f8-$y)=rGH19427b|2Xgt;Z=Oq1w|r{03p#_co$V
z;o6A{06ebs3xvT4?V|_4M`|5jLKvkT^%Av+)%GZbW}J2oeR3PG{pA~|oX`eRSS>;8
zN4?fbZ7XfjBx>y$NKR?Lo&kSPYdw!rWao_b>R{+3X=A9HJ*#!yfx=|%UOHNnqW!5F
z+~>68rog8(?FY0Wm#$r!h6cW%wbD_9i&~f8kju~xRKR?uwq-5sUebOx8eU{+7sjD1
zTl-%-gt^*8+SI(Fy+C_9dD=C2)9muATJ=3huW4OrGM%rjxd=po_62QsUDqC%0lS6T
z99ogz&^la$W|7wL0>WbLPr)!zs{M<?Hn+6RH=uG`t9uW1DbqUi1H4?@Ol^2aJLz8}
z722SVX_a=K67{Uq7SYPqUZp)oTSL`aoan)Opj}JfUe;-Q())W~dpZ-q2ig}GfOx3&
z{}5&M+EMY~ZqSy{lhCNWLkC?RX=|u!XwqhPLz6t#E^dXeS)08OoKLg~YOp-j?yrE`
z&$P2vg8I2OjAmCa?b<OE@O-81OzXJU+SaMC^hUe<1lZncQ{@o0Y9D1F_fGpS4d!jy
z*6}dWuJwyVZkx`H79`tsKW>4_4&AG+DBG#qMkDktU9A^{yLDq|4dAR>`T%7vy1)A)
zan-G+nam!Y{acEVy6L7AK<ci$Dn-symrMsw_UYVX;l7v7|0cZf*7?xkf&IFdQ(^aj
z?!+7be01)#o9?R{kq8w(T|IpocTjhI1I!=N9if@fVcn2os2tUONFTKY=$5<$E>LHD
zjU-6-&R&VaVBKf6_+gLf{Ae>GL^qyRUZJ|DG#?AoEvI7!;kpLelQ^!s^a#xrq3e1a
z2BUR<oPjV#*Ruk`SlwhAE8=uZyucl=+fM`L30)>_mM7?jE(F<0-Jf>&l&EtKLe0+T
zy1Up>n51*2pw3y{?pdHo)+JN|pQ8Ji!fNMqd@*w8b)}ENovMqW8E2aAZ7#Ueb^rZ>
z<brOu3@R6OZPe<Qbo#HrlBJt-1xdCpj23k{x_<p&@UpJ<UnIG@W;!)+MR$J~9n;Ix
z{n-V+UDYLj1B2IeK_8$_`MT8M5EkfMsKdCSi%mzaNY_j|_r<y&>d_=6y1?$p-PA?(
zh8Lx}WO|Tp=_XQ8=C<z3Js>O7h0v6sT=)040Nl})yMd)b=S-glROv!B4tW2nbs?*O
zuhB8I4y)D0dI5M(_x?2`b-F|y5chROTfzN6S4czbL*4MV5H{+HzeSTg(iPLPs!8{N
z&a*$(wSEkhX5F9Lkb9zA{WVyg>i$!qzRz^W_X6--x0DvDFLb%IcWrOcNiyNvOWj+l
z;Tzo(I?(i1=eZnB+NwLU9l&?G{##Jirt3$uyLMgQMsPdoSJ8~qNzYSgbDMrT{jl5h
zb7!N0cj#9tQMOb6mU?0ref1B3yXvP4FuzB?fY#@3`VZ-`a<}U@t^?jfzmO`rPv1t7
z05APtD<JgNCw&Z^{rX9d;l%-cHuY>i`lk^P`syvi!RDtASq{yEdhS!e59!NjQFvJY
zwg4@9ME@_nIR5&TwBvPDKW7nK3($Y)hFqY23oSo`^!8g7APv^PKNU2`^fP2==MX)6
z9l22b8yZi-^owb(7_JXULvmcdpH3S^=$B>#7pZU018J1rOkwzF{UX}+h|#~C1YE3s
z&`|*5^sDJKalF3fOSpDIzmKBo3HlFcz&xp6U|$S;qP~hgD>|j`r3U`A{(b6U&ge_4
zP^TpQ)sInjR=?5*ekbe0cA(lR`rdRB@SHxEh01xo1Ff}E^(#IGS(^SATAZcp8z?4w
zL7z7dmM-c&$3rDU-<kH-GWF{NP>D<WY!$6*vh<s0fIC|sOQ*VW^uMnM_htRFF2LvN
zFKq(iiat3TWqJCSMey*d{+l4w_nN+XGHCMk?>oUnfxhTC0N3@~I|5YtuwG!fp&u{@
zWkvcrS_2g8gKoo6iQexJa5wd_7TQ@X)h|2>;4S@-GtjxMS4W}o%k(0hjw#oFR}0lU
zdKn!DsL;o~g34X}M@NvW)GG_%OqG7;S5T?e-z)>JM&Ix?RBHA8o56WcKZu6kI(^Gw
z0PgF*rz0fw`cLVQdV_v3J~FY(8})zJ!l_64d#jK%=|@tB@mMdXGs?~SY00Se6a92K
zfKT;%`lC+I^quu!d#*PHz{CrE`Z*YE(T{$O+)KUs2z+{_9}$k+YrO|e9^U8=?E~3c
z{e#K)C0q4b^aokq>D{-0+TNz0-~hYr`u&ZlucP5>HGVuNLtPG3w;5W=i|q!HN7)X;
zZt5*}8urn2aF=181ZBGopHXzt*`U7z78iq-dL~yxzdL~MF$8@9FWd|w^$G5VO*4@5
zFhu_W_+EqX9GaeX!!&C3eTLLw@YKstLw`8K+t7C)g!>H}Xr6MwFqA&o^)V=k)YlL~
z-MgP*CPmv08seh?IAj=2XUGp577Ot3h+#bSF#d+|wDoh;;M4;w0fyGsNCFL+)XxMN
zF4LKyV1vD8AF{^`zEs~3Lq#C)p@ySt(avFp*#XFf8+v|&+;PLmF2F|^28~7%X&96Z
ze3T)!04Aah<7ta6#xQaST#GeS)5de0;rct2#T&HLz9$TQ=D^Ve!$-71c+yb#C)y&>
z&|-fI?o$S74<x4z-{b>-#<1fEOe7hiJ0W-0FxnsZWW#$+z^54AUIh0!!ypxC&KvgX
zflD>8?~tS!bmhRM8{#qm$S`Er0FY_O+XL4w88T@`pJnJ>23)q`PdaOsWALA9NA|Ko
zq%JMja9;%X6+_p*VK>k4`cEWR4O9OG_cg=2E+EY}9LYqkz~FET`0Iw7rQj|!yx$qk
zeZw$?!d*p%5PH0d4eiwHl^BM0L++-b_bjNC8cGL4<(6R-O%QGy#<$Tikut-AQg~5r
zaHE0qj^Q|syA_6qkKpiKL&#L*Dh;1*g25_-Y6f!E25%|2YYeegu+<t?QH<oC!D${W
z)fu||0Pg#S_j`f!fgyx8!yg*F>5Ou{;lU)}8Vo&NL9@}&?<@MC^pRnWAF@q`FP}p7
zvEg1Eyl6Ho8UXGmh9cU(erhQH6egY-jPzN_b3^%9l)W%~6NaS4@cT&!Um8;TLi3ej
zC!NH7Z5T@9?i<68A3^1<;Rl-0w;F20;Qc$p%rBwRW?<-9v$q>O+K_cLZpYuFkUJTd
z%i+Z~<JR*)Y&Slq6J0xuQFJ7Hr}4_~P}yZHb%)As<1AXZIUD0?hV5efm%gHNHOA0s
zkUhqQ^ktr#k?Ri@cVlJ(5)We`b-H_vYbPP`G=4|(z<qY(7&_JAWnB3!bi9qD>B!oC
z<HA-H9x&cpiNwbkI|q&LYdlMxuAlM0-=TTX__qt%@`&*_>I40a;UA#vsPS7R$^wl4
z?nN%pc$ki}1sRP|5C$7vpMv_BG4daH7-C$u1zv<2?P?{s!;DVT;6=ExjFyqdjbZP>
zZiI2$UjRlLf2KqFQN{tZGZSq*VuMPI(Qp9Vu|~yt<l>Bz?m;Eqm`P*u31f3V;1Y}u
zt6<`!(UStaiAE(&bWa&QJH9(Lwo|K}F)p;z=0cLOaSxKS#_#FiNwP7NHVIOUUtU2C
z&lw##B<GDYRY+2e3(AqC89$-j>~v#~`A9ApZ?wVEMdJYrOk^0B?*dt-ab62FFBx}G
z2bE>~dN5qeHZHaSkYoHT7{AYDV@3=0sJX^;3P@Zr)*MEi@{D6f!TeR@Fxr>BW|S`l
zO}??$YS0uI6|qRJ8y``OrO>FP;q!)3xB<-~;}lw+6dQFpX#5gmZ7#}g8dY?dsnj@>
zRyVhd6KUCc+ZeeB&XgH*UpV0XD>ojc=;R%vAqm_S#@GJv?XEGAX7-iFO*)vbGCrgI
zuxexEB_uV*kT5t}YpkSL)IH-Y+AXRxX6t~vZ`_p**B%%L6oT`iF^hK5>y52+9-_fm
z_Y9hi#-6l?|H!ECN9(^P<J3n`eQf;l7w9w_$25ZbiLpCvV?Q;@*Fd$!`0r#??WNH=
z9{5+r3Et3rZ9I~UvNy&_v_<&VxO+d$w;Ibv!{9rk!^g<A8OPC?>~^DO5FB+h*>9pQ
zPNw2D$Za!iaR!ThyUEQ9*&U{KTKMfWB~fr@m+8tL;CGwa9>W=DQ~oqm+r>1Sj#apt
z@^j$t9@FG3l)0JO#=^Y2$(8<;kcVmDUF7zfmeN@XPty}}W}m5%c5S>&yJ%GMHtnNG
z+I~~WL6jY^n>rQ4ypL%)y(GRSEp2Q2nf$(orGus(bD?_3<V!)q!=`@pbRRJ-=?pf1
zQ&);P95sD>8Y%&%-)^CzfhM&p%7RP@p&$!3?Vxw$n8}-B?jfdr)OClNPSIJIFw?|q
z&<r=(og*PVZgQdHV-co{onR@_6i!1<l<5%dl0}=UzXMH-X(!DJV@;FpBZ)KF=tyt8
zsXJ{do-m!<4QCQeXBDt}()85~2op`|^e3`TnLH>&bK10!rV?jNjr2KYk|}clRL+`m
z?4JUdY&tz3PNkSU{)WyuQzHFUsPiVTUx80GjU<&c)AJM{(oKnd;MxV#&OcCg(NrD-
zK!)j<J93$(U+IkhCDT0$uV<OMQyXTRM$dyvjwzes;+IW5L-8Brn*Ixb7gtQrKce_c
zp6O5k5LZnch1ai{ifCDtZ`wT*EmL4R9SG9vrtr@pEHurgc+m}0`$`ClOkc-ArP#Dm
zin3DERBu?iWh%--BiuHvQNrIclMlsa%1tpYFn`B1bOD4FreA4Yao2Qj8vQ|=N>eXd
zvQ?QT(X^r3v|}@TsxkGa@O-W57M;VoXR4qxpLM3VaRA;o?Y@Mv2d0I$!2Qq^I|^m>
zra$O2o(9u6H>fn4oKFGw$fW)rWKAX<pTH|-T6GlOH=E)j0C-|Lj;(UL{Hf_Gt*oD!
z8W^xWH${F6nir;08}KbA|3u(lnl=W(!&fF(+6Q=T3jGdjZ%m`zk$Y=;<qx-8O&4jW
z|DCCk9_u#K)4zagH*KROgrhmliky=<bUc2MZRXJ%VQ;&6uo?F3JIsM}6l15kOB(F%
zGGF9iX}9_59&kIG10R6f#jFxR<7)np_IdW0L;T^so4JWr-R|a8I^f`8R+Pi;UUM7$
zDNavwcRGHu&s?7gGB5LIG>&+iy*5K-zgeU}!~wHNUu^o=%^NGh?Q5Qv4D){Gk>SW4
zG#{b$?jiHJD(D<GH|>L^Bj$+%VaeZINc%KL%?diZ9AIAGf?S~4b_(zy^95Qa1e>2n
z0C3D4NPpEQ#Jq^k(ubOFJVz2{X8XfJxcMgsRN}bV{u^!cMwq8lpA>0cZi7yg`Ms}^
zi#ETaPo`tcBJGaFn!COOTb#M`G63Sun`wQ2!d#dNl?3zWb3uC2d?OOVM6**jXr3}h
z+fmWe=0z`{a>jgtLea_QUlt)rF%PA9{5f-={T2$(n_H<*N;NyFk))Y_re7`H{QMc}
zd%--6*5?<^TROvw46}X;l1y`x1zub-=h1hkS?0eeP?T+MF9I&d+^YfJUp8Ovid?Sw
z4gMmR{EGQH1>N$@GrmXes(B!tox5hfl0q9i`R3yk`7bbA*1)&x=J)<WVWD|1PVvfb
zm}lEyzQ{cOFO(IV*M5bh#C)v~xSQs}TCkOxe;5t!Tjqs_0k~~$rgd1E`JF4u%FPw$
z;MyJYDEg|R!u+f|aCgo3=yRG%Gq;%Dzbf-k`sSh9{K-$STVuwb+`@}z{)JYP_sqTi
zMU&Q<3u%UY-)yDT<O6f&0stPGPyU8nz1fjglMQA^IwIL<4ib<&GJl%@K$H1Y5jY>4
zqv^0lvsw89UOX{RdH}#v^WUB5{d;DvI1HWVW<wE3Uzqn$_t9cr)*H2WX&y`i$t&|l
zI>7zfd?FVH-<UJ%VB)QLIUPW0HFI=`?Vb4%#lYIkV|<{}Zk`^4GDl0+pD1&(RMQG(
zn<bzb=C@m_&B*PrEY+aQzSGi&CK$Uc+V6qbZJCw|OU{-ZB{1(|*|!8aSBqx?9NuH;
zO$RdEEZjl>-7QmoN8(|bLhGTumh>V3JT0N+;NE9h{}yFlmd-SD^R_e{MsB}lBMsCC
zEWg!2=wmtj1UX;3rT-@|;b-v~3;aRLCJO%?u_One7XFsKdgP8;F7*c@z*6!Ejs{w`
z(wiD&@t{aTuw^tIvp8mX?`PNzv9w2kEYz~OFOo3J<PflgTSh5>J8m&K;dzX(d`~Na
zNXrH_;87O)@S89ZZOP!!dNG!$wMb$ub7_A#&LZZ6Cf?Fw1kDM{NAw|Cg2kD-*^`#h
z`{8e*Wvw%kQ<hKZgRaw-qc;IRW64v%Qj*1w)+}c&nKXAvwj|S1JjK%dCCs0*WP3v8
zyv4&#+cv3|hKtCiSuVVTPP%0WO<XTnR?UQ^i<V2#@FK&K`VWAamSfbVU9!BPxOkT3
zzfrK8ZSg*dvK&jXCvul9Yu14**D{!b^j9pdm*IAvW!rJ!u3BCng@@NH-|Yl-zQs0=
z)_(;SN7@m-ZV94K#0xD_+PA!6DeMLlMV9A&C@Z$~yaq&xrIh08H!bH6K&903^LZG&
zWvP%Nxox@g1YVR`ycWSkxn+3{0Cz02=#*`RB{&4;?^?Ehfn23!2(5anEEDP(ynode
z1)YPevGk7zqSms7x~+SboIF^nv#?8%+_!YUjIsxo`l&GS(6V0z6ZMwq&A>HS{9-`b
zXc<P!-ba?)0kG6$SrLJ<$CiORkZZQ&)}Sq(SSDV9=2J`C2>AQV5{!wxUH;s1iGuYn
zEQL}eEfyd8?DwVR^hCJ$$};B%*nMqzPR9=3SlR}|#9ND;KA~*0{IdkPcFPm$N*%3H
z@56+X^-Ut++pI(A6x?=eMmr4duwspbA<pVg(Xw6Em2z<Iw$5Jzq21Yfinf_ttV3u@
z;c6Y93!OdI|DM61n{{h7xZSPs7N~ewt0IxxYwi0POn6#H&<W3d*7-Bxg_pH*4C?D`
z^`jZde(Urj$Q`h1vBH)6SW7v0;cL||fI&a&Bbq!Mv|cX(?vUMD`~j+c*gBND*&|lD
z2vUEml?Je*)>pJz39y#YXRLwN`Y!<tvi_6<nqceX23R^~okl0WLafp2kc3)qegu^;
ztBno{gj@gYhvc|*6&*E;u&y%!5NZ8;J$#C?UZWEy(N=pMy__-Dl3XOQRxgCa<Z;$&
z0Y1fBjdYUsgf)EwfC*O5KnPD-o3^8!60P43gcql**XWeSX=~0Xcz?z^fX28atJ@Zk
zowfS41D<TH`U1HW>$5{h&RKg+L2}+Yh|c1rS{K`CDUoJvp_pO1b=`0z7p$pKuyoNX
z%ZG~@)+$<pWLoQK+I`8oZx3piWsQ!9`E2V20W>+*+kL@u*}Cc`%;#E<?S=4)wO2JP
z<yi}YKz7wSjC$#7))1OV<y#M&g-U^SjVF;_w{BulSZMX7LzXwJ;hRxdWS#9jYH1&P
z2z_B&W?fha>T>Iv5GdZUM$Lx3N^3zhEL2&)=nV&}tzZ0uvKs5EH$c}~XIBAt&-yFH
z%<8Pp)G^(+?xo{_53FZtgnVd?lE7TOb#5hc4c1=E;Af+iIf&$ub*UHX*JSO}@dr;I
zTOBIF-E94E9txjWC(@UfPp!erK>E!36U8r{TW`>I=L_o)dMsM3f6zA{FRg+e&b+c-
zpuOVP*4tG`-dHc{Q1;fEPpjottLy-hcUB)a7;Lltc^E3~*3mQuJK6%)Qvc*+J3&F%
zZMJ?Kyx4AQrL)vKY>sUJ?zA=22)WC~Tt(G(+weI8hA-QVRVZ_@*=WDQ)%HD|kKJQy
zqxqkkZ2-N??zUZhVadaGn9e%wwart)f~W1TO-T0HX48pmFWZD*+8_0{{iFcfe%pDP
ztQ@cz<|F50`-Ot+zP4TWLF#9#eIINGZJ%y{Ylm#Bt3i6$rlP}hM{MtHg^IuJH7$pZ
z+DcA>JHQrB8~lMb?k#dbw(V<C7Hqq`4(5;9w$#Exi0wm!MD6lW+Y;)t!)zlR(H7yh
z#T4;BZY!r+MA*iyM-plKiB9W9*_N+?X0&bP3UJ5R`cou2*7k;uMa9|r%!Bvwwu%Ut
zIAJUO3Bm;1?N{JDX)9R<e-mv#d!P+Z*>2Gq_O#7#6>$3*+v*Y&CfRQ1BYW1?yBdYb
zw){&-QfyI=Av|ZxTMxVEZMI~PrrPc`!cv-TdLQ_7(blsw;2AbaF5J$vZJ;liF4^wn
zK_$yJdM}*Gwl&gepBx)cuk>Y`FGVVIZO*ySykfWA+zl7=Y}aU$_^RzsI)-`8R(S`A
zd|Rj$4j0%))3;#PZPi`jQ=zT@HQ2pj%M+0l+4|7iTWs616CRe>#=1b|rtQ0n;4Zb9
zrvP`$_AM>>Z`<Bg0Z?Z1+5>;fZG-+FN7o&fW%b1?voy6~n(^+v_cAS0D_fS@P)i$X
zWm>lUWo4ExOWCqyh_XZkWhf{^6l8BuKtx%xH^@eo{=TQb&gb5H&i9;qd7t~7d(OEJ
zv=ubiShtY3(r6>K0Op=eZz@=uY(Arpt2WzQ*@oG-*qABj)N1q0BqZ8wV#s%Iw<)31
zRENzUNl?*gvv(6nmyOVX&TgBRt6_GJO+Q6@du^OMK>BP#mxA=$u(H82V6)l@t@}0t
zD_zJMw0R*DWXQ(lb7&g2$(?{PBQ{QD03EgYZW<Pj*@RM!<+zPyCB`OfMoVGL1Dj_^
zeA4CvB@|BCJRT0tX`8J=%y7o$k_wZUwYgwM>!Ho;b5Qum<{Y{Awv6R;ptfVAAEZJI
zdq&^4SZ)VK$QBSsMkBqwk1&eXfgEKd^+CdkVMC6AGb5x6=DRSSqyx1pBbX`y-53kf
zz~avM_#2FQFg8$p_!wg=eLBXIv5DRaUW|#AFw~ooz6vcL#<H)$;>*~07$4l7dz?{2
zWk!CC=P5<!&tQ^AAHYykRY@Sj)ee@PU@Uzant~WJuR`!7<IR0&onpj&020h_-;T}@
zhL;>m63Tdq%E!VOU(tIYobeaMdCoAFQ<^1`@d>%`XBlfF(28O_<-Y*WUo?YFQH^tq
zP!?=E&*&l_Achfl4ReZRxUyhV9OEx??&2A$V`yDqC=P?=B4gt=n3lj0=0ag2qm&H2
z#5hc8mdgw=Wf+ne(d|G<W;B0~&J@Oe3R<Ny>>EI?Fb+|g#hS+W`VP>pGA4Hb<{D#$
z;*aT!)k`3l!8q{_$aO}91Qup8obF&rvKT286U}BUr$x+RY<-AUF5?|KQ0Fls+`*a8
zu%!q<0b}<js3>G?&O@t+5pWXF#S8@%29+?Lq+P4j%81s1mN62GF~f33Rx~7TFcMY3
zzR8%OuUb_w+J`V!$rxcnQx)T%Wl(X8@iK*is~N%c7~W>MS3$0Z@hrU)?=U+4OSmz%
zQ?$31vG7%pI>vQ6CDb$g?|?KgO35W{WLSTs)YUyk0M!*XG1@5$(ah+KMQ00Rm_BvV
z$}shTv@!0VfTnhaf$rURFoYc-os75WK+wfl{5D$M3<cF#^)Pa%Shtta8Uz)6j1F?n
z`WfMLXdYlJp#$}O#&0IH1{ucf3m`be$U6k1h8gyB7#v|dSO#N88R3-k9b+tg7JA1S
z*>u93V6;%q_W>hn16q@eV0XYwF=QSvdzx{Lq6#yNy-r}6Wkmbxepq5%aSj}I%y%=O
zz@GUIZ5IwqukA46D6@eglTOU`DU3NYhdg1Y3-d|?KwO!=e_{#Tm>i0wxHF%A9daJb
zbjnK}WA3EFY)|G9T30V-_(Is{&0K#EV?Io7JH~vOGJ4LBGd-<=u+xvZg7O>w%*)RK
zCV=@4{YC?s)lQH<!OW)zHHbN^hA}6ZV;i9G6w`PREWyl>s~{oFz%x)0%3PZWfiR}S
zDhPx#znX@?Y385XAP~VcQzYjMb1fC*L^302&pOLI++{^Giuo25u|zYkQB~AArc)G*
zInSJ>gIWx;oyuimnG8BX$1xAkD#tVT{R_DZ%si@yxyby9zEzXJ)c*z*iOgs7K`t>r
zqTk46CbtuuNzA3rKuKoCQS>o|*-mfGROTzM(EXPy%<*QJn8sAMgY_!&Bt<r_G2=(k
zna=cY0a^xg`Z5HsGt(%AlF96vL@SH=GJVS~n>lg?B!_v1l5n|9H65Vyn1zo4ET8%G
zBWNmMHthjQA@fu6k&2j#*TGWE+>C+?>)aA%8$Hsc%%|ujTE<jR=|MTOky0Qxm_NBf
z;Z3F;9Y`yf4ex@blKBtifvTAMsOs|;lRjWRx0*Rl>wKFz{x?`^n4zy?><+W21+BZx
zt#o0lmRU{*mOAG5613`>g=3JjHZZ#sm~SKVg=T=>V-`n4Qxo&?n`kv7)&!mwW?(v6
zt<0nJHSad&)3h?}%z!+|buk+@qqCcN#tx*1d3g|>z0BX6fzroR(utv;$)*dU1I##z
zgWYF-`4m_NnXa3$KtopMtzBpiGtXXx#0YbH6?jIOZ*75zW6b(qs2^wkPM7W`m@m<f
z?E&+LK&YQ&o>_~rDdu|=k(p+8eF&Br=3L4m&ocGo>px^NU&cB=VqQD~Fk4nb7l<9}
zcr|RYXE`0klpI*r<h8KPk;R$^>?5pwk05cBwfre`I<eZffybHUUI^mCdg5IubY%_D
zi^GkT><F{nS?|3GG!K@(3IfMi20B1{vf^l$@?tIOgfZT%)+U(d!y2T>u`lbJN`M__
z9b~~6KUT6e0E7N44n?&CSSQFa4`dC$4W1LMc6x0FvC59aw3DnDCzy7MHT5a<2D3O{
z0Xu~CFI~b8W&KUJnZsCN^T86%`jE0wr&-e!u8d$6M}wSU`A8ub$vW~WT4z~X76Lko
z^^z~Sw9%~KuOWDj^;0&iIM4dE9O`3OmGs(-WqH%Jg*cX&&b;v~2dXi=!1|g_&=*-f
z6yHf;4N@2`k;S0{^d;7d4?r%nUZLPg66@yxXi8?;ya+`ptV1Q>Ol9S4gxnR@)0I^J
zl*Zafj_Os`fu$hVSfejMFrB5P1Z)Ot{bop9XEm+GSSHJE6|Bf&`B9xpHmh9<dvjRK
zFVLCG`jtwC@>pNcOCg_CNv>f5>(o8iTg*CGkIoX-db)#D%HsH-vy2tUeG<=KIV+O_
zLpNAarI5eL8vGHnuV8)oDp)I7GCv4bv94r7;udRl2dt=OeNNBsZPqbgsHkE2P<`ng
z)?T_3aF_KW-DIj|NzyS^$4U!>Kt1aWomm@L>*%RyWQjLJ!#x%=2q@MjRw%i>&8)pF
z%&CQCoB>)Z>oqDxYh%Tcv)|4tdkbS7tXRqccCzwl+Fh)_$$ji*c^5*Uhh?Bj#a@>6
zSqSv8Hc*nZpY<_CQU_Qo=v$EYS*3JFA7tI6Yav6dA07u8wzB4*2FwU+TmTiLtlY&w
z8)M!22`a`}|9ch^6Rf+GM0miecm`;bENcr`rdT`3qn>7cJPnu`mb(Gdo@Je(x`KzS
zx2i!Nu?9@&v}I==fq)(R^9Tsov->Aup#%Fbia0y6t^1Ba?-6!tE_jZzEBqnh#CD_{
zl{5QUio3h8y*~nRWxFP!(~T{l%Np+Naw}RMY&pHkkFi}|K&K~r8U2~O*nX4(@n-*F
z4@@8S!^0rH?5`+pew@8UipBS1M~6baKikcE9r6L}^>t_lvR{KQF!uy|q6h00#Lguz
z<s`e*1B-Bq-8q9+F#B673kqQiX-^1cU-$$hjIEl4KsdYg31~XaR>eYn1bZkR7M@|_
zOBavLjbxvSz}Q*#`fV7CV(0KcqS<?g$-h3wKETFcEc?4~sE=dcrc_fr+d`q33+%xj
zkc;g0Coq=4{;~v|iEM|}nCK<;>iZDC%>LmCn3lxe<N>*4wv~LW6n4&sU`b_H(9Eu|
zx7>v>Y3!5Vf#oXuya-de#(w2zy8n{S&RhnV4E8twfaf|p>01b9vVSF?C5yeH3E0_e
z530n;VJ93zE0=xkF2?fM4=JFO&wiDv3<}r}$=*WtL<0;hVuy4?Q!!gaq3RO$PY0l(
zlwFkwfim`l1f1pU(vtaj{%){i>d?H&{*{8C73|y%AeHQuHR!Bj?^*z3Zn3w&2vW_q
z$$^Ep*>~w9CpGNseb9S{jn9VT!DIhIFZx>cFBB@MWA9#tRy~_(!dL@)8x=k^vd6kX
z?y(!UfHbjxrD|YnGy629y<6BPpM{C7>>vMxL>qg~4k&DA`+o?7JJ?&#VHTb2_n(4b
z7u$n;kZ!gt6!JZ6OENU|vVU&?XCHgS1>*heS$c{G*jXC1?z5k(1<N3NjuEXP_7hb3
zH_VQC4+0}r_Ve^nmQi-;7vLFVTd*h19cPbtL(>HNd)h-Eu*>O!-z58Wx_CCluKWX>
z)9e-sY0j`erh3>}c0eX3@sMqx57azjU!-h>E$8vOAa)!zIjHs=<Nsij1LunXusCu)
zpkwtBj&(B!(>}`CN_)N&$9@BdGsi;Pr3>dWMfzMh17{)c#`%R_1jjh;t(b);XZ{0>
zd2ybkic)XR%PPqEaQ2bw<ja|&aM*E9>QM;zaaf%o{+#OXfD*uYjgDA>oQ7SP;0ew}
zs~nRF;v7AV!IPZW-9S6VNo<6P!JO<#@Pu%BcA^!^35kSFVVu?Un?s50cF3LPRBS{m
zg43M>xicK~yAX)v%u*csET@?Kj3|z{9b?g){S=2j$9cFOVCOlkn;<cq4d2uA7t8VT
z08AWbV;^jb=NwrIgD-G?p~AF_oSB;#OW^dR12mE2MUUYn&hE32zs&j56WB?dRNA$Y
zId?ZgeG2C}129uLXY0Xog)^V3ZPGZlbmjgk=N;<2#(6gY8qzto=c)c8gCqI?nyzyi
z`XQgmSwp|MEKb3*5X|Oe-vi0vJpL{^b2&_M-SRlQsXQ*96PSv1F5npV0<@5`ls4od
zPKG@!EaueGr{YRDz5CHB<rrizw2UKu37zGf#gs(5!Rf7~_uoy<5o%U&UI>JIC1>cr
z=s#zGY7TC3-hKwy)ttwi!E&4P0c~3~9PiDT%pH#H;~2Zk+24uz)^db&&$f>90VQDT
zIVDtc(7<sF14|?4_;$4JaXx+z({AFNn1FaQr%?{mtSy|+>CoKDscD3K8)wNIP|?mg
z6%U>cj@1n8PR?$+64b?MB8A<YXXk^ZhqH$+xAbz}*pALV&U^F{@8^6{3$q6~v6LJd
z;uQY(j^m`$!j5p-rvWy~iKckV7^n3##K+&|L{Meg1jkCXWDhtWQG|4ovx<DoDb5J_
zw$q#iA4A~`r@Iqmma}<3R6OL=V%MGfh~u^fEVkUweTV*BVjZr8m?PJRasWrTh4k^X
zquj%V;Bex;M~|&Dw~+EEF5JiH&+5wcq0p@x_YMU?+___vs`23F3}fsVH<E(rp4>iK
z9xrYmoesRYJIK-W;m%zKMZR3O*8z5%+j$rQeq5%Nb{2o`ooZ+b;AT)ZHjrDU!Qct*
zV#?A7ai180;7P8Cp5;^ARGLFDx03}D!u_3m=uqw=+H%9V^|fe)a|P=#cAEPMO(}v~
zMt;Q^?tOBgBDo>-Vn53rF2`RkiksT?pEJq*mF9Gg+gA)r&vVypgNZR*Pdekoa<>hD
z#Bn<)_8QMULBD_tTwh8PT;v|4H+llsm1=box!t!wE^(9hf#ouHkiOEE#2us8Kr(lN
z{?|zg_e?AlrE*0ZV8s>gjD{YjG;YTdNL=O4`2(7+ako&BKsxtvE_gDy>t4gyb?#3a
zF_y_)Q-QH8?t43-DVyt;i&^AwW52~jbGa)*fSt$X1c4==Ykd=A1>EPhf)sMkZ$W1f
zck2Uy6?3n>1LzX2$KA*9FqLw5#-Lfojr|oW%DIhNz}(>O`w*m(`@})mUBz{t2Zgt|
z1s<4FHTT&_fZpb=p)+g^SNa3S?r@*vfb%Xlo&{3Njc<Z@9d|DkNY!)wsPemkyMXQ$
zHFC8SSG~twLp9UZCT`XmnBUBGQv$n%8>@nRE7$!s47PDMQ8KulyZUReba0cBA=t@1
zM``jd?v16u?&khLZcz{SQXtm3ms@@qV}0E9<k|LfH{Ju-0Qb#PfWFV2cNhYLT)S^z
z#SnKzHduzO+@;$vIKtgUmu5$~$LRGn#<e5!$GM-<$z_7eAot<{cU>4-licHnFyASz
z-Mhe^<_1!jbcP!vhrlfNF-itK<i1XEgh$+EKLN~^w}*mMcD&345PRNIs-$+{J)}IO
zBhNbiKQxc<cJ71~M|lhBAmPLl$}s568#w?IU3fR+fac1ZLse#Oytl7m%$>&~7v6){
z#D~B!-W<xIdGapP@!E@b^(crpPxC#-e0aJ-2>9~knP?s7IUm3x`0*AkhcW&<mX-2k
z0lW?LYzOipS7Pu4FV+R}LA-#45Io8I<YSDT;{CA^tzh0(M`#M+{k;vGp*#;dABXYo
zG@}*H`<-TZn)eEYnj?6=1}Hqkd$SHKkvs#%M9%WQCr><z_b$0_(Y)PC3Z|UnCDHdK
z&htJyi{2RCyk=;M<t?XRd>rpZnoK<JMLIiQ;4vu1eUbM+I+-T$KAOf~<T5Y!3dECm
z<`{@4^Zuv>N#QLU0!u1ymLj-Uc&q4%OXHny$5LM9wfF$~8n5aVy3Co*Th)tZ2G9LN
z*nOS%?<J_u<cZ1q&En}Of}73bCSWo-ycgIYxx9mP<j>=kErN=Co|R6P1-ySKZc@l|
zTmn+W%eBK;F;9IN_LlIj(5a@B_az;c%XpRBF;>oNM12UHN!~I6nm2h>bl$AsjZFZ%
zl6Ug~V5)f6gqX}No+AZns(CiAK>ckVGYkSXya&Hx_IG$+H3IZ5uZ2#nwY>8bi>c%N
zkDjJ_o`OE~*T9<*0=khG_!j1Qk2gwpj+%HP3Rqa1c@HRV-@+49acnEk!3OKq#`|9(
zNIUPfbr9^}ap|1d$;<o|*j>DTn9$qJTQvlh9^NSmGxhR(=V7dmm$V8N_VeaY0&{@3
zVjAQ=Pf1VXAnz}F(1&;zMu0ht|8@g=N36UaJ7ACU4$2@n#_OGe#5nJC3<f87+oPfB
z0Z*I)>`C5VKY&c}>`#GA^S+~Ux*6Uu-8q`&nJHNIkoVUL%=Z!R?J}U)@@wc8rXAnu
zCcy0Z*C|Wlz`yh&<Q)0mQ<U@w-?}pe^eF$p^O%eiUt0j;%)dW`6>{P4cmPmWzPlY-
zZv2N@2)grEQKf_jf9!3b9pf*fyELBs&nU0q#ee1$SiJdXeu8=*{%`bZ_2ql-hE4u_
zo+DZT{A${J1NkjffOCRhX|05cApUVm6Q1M;#X<fQ-<O=xV1Ba^dPDe95oQs}FQaT@
z7{9k43d8x1lsq`ix1ox=2)=-Jm^1t`I(kR)cTsxeEdQBJm{}A*=2w74^BWEW`W*i)
zx`1(>FQO<_3}3d*3L4ATQ?ewEU%3-7@%&3?u?QFVf07?{k$;0c)C9hSHqS(UA{DS+
z;-{{M+-3eKx#>y#a7Tb9^S9B*%TxG!V$hk&fB9*&uJE^t0G-Bv<^fQy^0^dZyvE;8
zVWM<?-Es<MX7C3o>wTTy^$P?u`7V7x%i^CL1Igx}H$x(apZEey%jHXkFtt3sO*gRf
z`QLwqRssL1pTJVce@MUeBK~U>?kVO!w*v}G_?sx7Qp*35>QKx0d9?MH^Ao%<c7y-<
z-;X`^)7+c<aY}kr@UPRBSjp#7DM}UpJl)Q?#orMGo2vQe7GUf)-|+x6)$m#L+P}lU
z|2fp(<=?*yy|w%;lp?O<*Es^ap8qTzp&R(YwD~piXDAqXkN>Cd4!b2*2IWdx`3$PF
zZ{vSSp{I8K2&KC^_-k7**2%Z_qO*&C>o1UQ{sRu|>){&@!<1hBj?aMA#~<Da<^B8%
zxfmPZd(tg|`}{pG!uCOaX)0KT_|2438s`7(0F)7a-YC{{l>h#JpN|^j2WZfIz+XUq
z#Ux)#l@(L`JsfmS^Tp?3+6?~{I?>JY9UNfOLp~0Yc(nMjw?S+LJ1LfECwP)PQhNdO
z8!U)}Ad_}iM?p|B6dn<To`Gpc1xs7;_iz#vjlw2p!PEbR4_pKXD6;7)P*T{?O|V-C
z7<WPQYRG#CSRs%&Cg`J=zNf%D1;k6BY=afvf+xJ8$w%OukBRyUl&@gyxZohYJpBYr
z23r1t9VxIdK(Ou_Farf01sFRa_>Me*AVK#=N{^ouWbOygDZx)M7z`E+Q}I%WU?mmo
zgbMDFV-O}d@IFin7bq!*d|Gg2E?N<Sg|7hgjNqIHT9JYcv`d{8?8pF#5*VrWDO&I{
zJ)q|VTPP`WUU0qytr)=$+LvMl(k!~ZA18Q`-stgyD00#-2%bp<=tV*68z2dSm6X*?
z6f8Ig&`W|n9LQf5EN_9mNrDqa=u8%T^*3xv5o9fac&cE8-rZLOj+75c6S)0?v8w{b
z$B?@wI6RKAbb-tOk|C%YgMjtA;8O)wFH=xLb=X;g#Pz_=7OW)iHAgV_alqsXiq>N?
zd4i)<_meNEHbZZL;MwZ{EfhRYXQCoO6Qy&C1zRrwv_!Dq7G{?U){|ROCeU96X1QPi
z{h4kE-lq8TO+ig6z$&bQ;xB<#DR}xF2v!MRr?BuXK{`2J)q>5n;JGcxqk@GR!SnyZ
zrdmNMy{_v71qZ-cFHmHl)gTb{VXRRwvmNA~U@KizZW1)pT$%-ypFv@Z;N0i1uvOq4
z4J+CN4$p(7U0@xds*w)CJM`dn3hHP{y99X&0PPkmp}o3C@N+OEdIc|}U@iItIm-ak
zFJONN(*^`nw0QRgoqMp(gMzw$z%nGbw;1BXf=?-0Ga~qcw#-q%gX0(*6TJKcTH^xW
zR@gKlc*9Bu_XmQ<=~O={_~BK6P6>MHw&=8ACAkSR0?tJ!oE1d94Pzb(*3sMVk)WEc
zM%oI$?1f%Cp&#9@vlqS_4=@K|HKpPlg{1<Z91+&gTl1(ep00p82_=mn&cgCc2)GD~
zFHm`ktMD_5B)JJ2DO&0-eC`9ZJcQ-6O&t@iqy(|2aLpVj^b&qT!B21DW^!wMgm+>v
z3tyoN2jsZ$6RHjO6DI$SF@NErmmm-zRN;=q+(2Pi4ZuzayQs=PNO*+q3Y-*L{V9BR
zN+@_73WJ56uV64lX!AA{h6?wWfhSD3a2%cC!jFg1IxYN*wyg-^TU2CoMpzyNy^+Fo
zZ(%ZLh4bi>bWuY4y;z`VA?G{DofB?QW9+=}ZQ3+rguhchGFB+1%{fjO)J)~8@xqr^
zqj^F2Hhn_!qHylNFeX75XbVk=!tcqnOF}l?F}f^t{s*Qd3G4XiOcoA)2rE*AP9d-&
zRd`}KG+hx^-a_k|aOd~XlrH>(;uRUf#!ay4y72ZT$Yly6s(_LuTyPV_nk`JA+<A`h
z30oMPD}0~cmwCeb2Z5F^JVC#?0^vpxNTE=?6{JYGI~FR6g|kA)mk0++0a_~DL&ZpC
z!YT@WlneX6hQb@dt_oOjQ@GU?8Y+Y?F|fB%s6fJPZj}(O8J;w&P(waewQ!sYQf>>^
z(#BdN{Odgk-Vr7_Lh!C|C8aKFg^iS;s}ov}Vys^HN)uojgk9$_)+pS@f%rY)M?PR_
z5>An$*epCpiTD<w8|^-=!ih<cHlcb98rp@M={V6Lv@WMpYp2kY>O;DO6I3(VEnH9A
zR*!I6f~oZiQ|S|jeZuJ!sOT5|xF4VcLdOW`y)WEx6Vo0P*6oJekkF?ADu#uXp1>Xv
z{zE&<sIZW}voj{_OhId0m^TTO31Qt1kO#sE>kAm16#4|9IVH?Y1n9J|o{9%&gm2FU
z+N@CV5ZDieUsLe&k?@sC%+OX;Pr*++kssYrvKJvDi3d;Q{XSZbqT`ET;StgDXpp0#
zRsZ>tqT~<2;w&1bfVYb%BL^B>MfWDj<8l)f?1rGb=no1tc!(N%K#qx4(G5#a(a-cr
zXfM$y?SbB+y>x}!M>J85mai!ECBPgPeMxSopU5cytL88Ibskg%h>9qV94PXmgU<<3
zaWXoCM6Z!kbyD;yRaAwDiZ9Uh#Zb{#ry&?7`kjlxaFOA8C_F7<Q1CKBw4DvXGoqf)
zu?Uf(Qu;L2SrIn?EK#D!G^mIc9ilH?oD*%gLeqJXPXSsnBK`9)G*)!{AxNAkoV>Vr
zQ7)ZUFNmf(fO1iE6G0SwK1$?I-&0By<x{-nlBkvf50^#jDZP>;+FlEZWRZ~G!YQI}
zDuA6T+MNs2u87XsKp;)DSP1N^B6UABT@$6#`6XTSF&)`6L_U=CyDkz^Fg;Vm+6I&?
z(QZ0qXN!W5K&>@L6gms}T+!Ni2<C~jC&80166^q4fyhEWSD~oxzkrG83jL6aMK9A8
z#S+nK`q!kTqQN`}l!=P6K*~i?RGM@{biNXpH$`z-5U3Ef+rx@V(JEBY&aDz<IKr4)
zqWO`SV6|1Gqm<8W(HoDTsYW!_4W2uq0W)TJS2RSMZmnns<rnHi8*iXhFREpLvq9uQ
zE_kEp7!@+#6Fs<yR+A_r17OXfgOu-T5&il-1X@LlDG=Kxs@Vd)?V@z5(diJeY1ir$
zS<6quwl2|@CP;LP(kKzyBPw1GiC&QxEq9-&mx`79MLSEtG9c>x2vfT+T2p{U7!+}S
zLFbSt@(++<QR3qe7!iGt2J1&fOLb5&CMuSIjEmBXFg79LlIQn8<U_x;Nzv!l9`sI$
zu5N`<)1scmfSD0}QVlXIIzYKcTk!zJDD1@U@4+;C@lRe*?;xIsXw_Ut@#bN09uaft
z@Oe}$p;CG$@kkQ{oW%}w4sj7rABLQ(IQ1T^a1)y=px#|PpN_B|;(vlD;&)8EfpQm~
z;z#6Od5K3phoHCE`xIDx#1XU?`HH!0EXi?kUpfT*#EU56;4jX48!!RlG9%;y#p@_6
zc0xS)1Ev-v?tC2rC&k}VXylaGJsv2*;veb8QHVH(l76A$7hj|D@i6ggbjl7FS8f99
zY4KO|kVJ^RXt~dbzj+PVk>c}fu}){j5xxM85-*_qQMC9#EEJv-|CNLpo);_0!H*HI
zxr(t^apXN{iW7@z*NPVpN-&oTVg{|~Me(}LkV_DYaO1%`H&Oihrx?5>uJHr8EDl-*
zE0V-9bgWMnH%EdsMO;s>(Nyv9MqpnNdmREyn)s6-2wWBKp90G@@&CSu`gC!%4xJg|
z;=NeI>*5y@fRZWx>jK8I#QUEGbhfzX4g_+<@n_Mp=88Av11(Ry$_s+|;uhLd3dH;9
zlwBz9EdxxE*yRjb#bPO)vP;AxOrVvD?KzlXnRwn;=qwjMejRc*#5+|GxGC<9fQkxn
zQw>-u#lbSLREb%Xxw$1SdKqBV;(y7HyKNO0{)~055qo69nmc0U(~!6;UR(i*TJcCe
z(CWlW89M95QS=sW5Ffe^dmF{xsTjK_p6Q3)7V#H!hHVwEBd4WJJWB`Dc5wh@MLWc=
zc!RT3{1j!xyTo3$5a<@au@$68Z2f_%M0>@D@*&YD9w)!KUtDzyg9G9V6q>m&jxmE}
zP`s7GHbY`7IiADf`OUCmMEv$*%xP4-QUfw3UKj<1<6``$dOT|4ckE&I1Mw9KWKD{F
z=rB1Y9;2xEv{-%?EHmPdtWQA2tavNk*nKFDq>HeR#P*M2&{pyfB?j#zA3FitUb5ph
zIvpfGu0_jHvXBLVBa(S~2ppAYnE-W?yv#t$S+b0dCoYmjv}?Ia4m}0y-6RG&WxGpK
z7#Q=AJfgSgG0FKVD|kF5v1Sl2$&YlX^p<=z1Dkv#c|KSKU&$Xw0D4^V`&AG>$viRU
z<S%hL1keD<UfN~@C6+x9KOuRRw!0unDrFB&O1`DD;VH=?a#({U<u{-(MDqKWzzmfb
ze9;*uv60aGFI<vLv9HsT=V<qdkOb1oo{`K@bURYAiyrZ_k|p7=DN15Xbz;#H<v7SW
z$)Y@{I4`k`0Xs%=bPg6MRx(I#U7SQg`J;HrI(vv;kgTP`ql=RKGMJqpN&gEP5+(MZ
z;6L@wy(BqIDagx`grBfNNfL)-@FYv{|2**ENml=ju~bRkZ-BWXF^^yo(j=lGw602;
zUx9_!B(p7OrAt1D!&rtyO>wR3lI0#ym?>#~1Wj3z&Q(CkmFQ1k+If;7y1<Yxc_RnJ
zS|I5S!(<92(Jw(^k;JPMpv96Gs9>W+GK&oN+){}*8>W>>a;T`bT=FHA2i%Y}NFaYx
z($avHsgUH>K}DrxAN{VXBnuaT^OnR+vH5C==PaOaORoJ1QX^SPSN-ltR?mRtu2piZ
z0BE(6O#?uylYI0$OstnYNjH`nBnJc-Ym~f2>AHK8^;V2ENw(C%m}W^_J+NCO_#a$&
z@FZW;@up2Oxe=sY^6kqI?~tVb0MaR0M&Y<F$ue@gyCqxhg7iqv(B9cAvC4*l-6#2Q
z7kc|8|J#DrfaH4vY`ZThIuEo#$x?Dvha~&x)jTZeri%<Ck}LFz9hC$G!oo30ZaL7#
zC9`xmn~+44L-as$t_fsP@+R$;Q<8~MkZFn01p+gYr}R)XE6K600q8?X)N5!ylDJUO
zrmfUh4QxAUPaRtJ(ja>N9Hauev+5{4NAHs(Qa7sQIx0QC7{p2X)t~sIIZLyifSij|
z`62YWO4m>=rJFQ34=s0TIF)*PNYmB<?3nZma*aKu=^1o=-%ILJhNidlE`<<$q_0!3
z%vT!N3ee-y`*bhPPkNBvhW^qklx7c*#vg;GKxtbo{vs!&><oYgNiTl}fs@h}a{f<A
zLq@?8EG?yDMu=4H3KA-{q3>;kNhj%hM&Z(<SLpnATG~lDvIyxSR}7w&Uiuv{QPM2}
z$VW?GPXP8gsqJm(Juj`Kv{H=JWDk~DshV7wIB6ffcjKjpPeR~=wBi>CT$EPQR+u0i
z{SKUo(yN)6*(K>e<sg@(?~;d`BrU?5&N??)dff#uDbjKZU8G7`hy%{OBHcleyEN$+
z`!RM^nng8t*Q9Jpm#0e$=tYnrog`oHx^ykYNHV2SbcZZU`q@t)+0uO@kjs&J2LUWs
zx+M=*<Vi2ev6T7JcDnphARVf~n6*&)JXO;cNlW=aE0!Ll97u_Dl02|dsY4MY%A|=!
zXq8KElB;+_ntB)lH>K~=T2@G#>5pD1ReS)JDrs*RTDPQW=fGJlwf4ib+tL+JVXQ`a
zHW}96kv`>*dES-UFNUI8tMu$I7_5`pZ^vN0^a35g8l*dUfN7Mjp^}n&Qhq;{v`ISI
z4~b@JHign!q#pHvX_bE93zjx%!+t1immZ|kLWlI65#pUv_oXnjOIk|BdEL?wN-6Y6
z)5zoNmF6r2SfA9ok4`!LQYO9q2c)Yv!<hS0eHI1>rR!gZiXrLgy&%KV0U^kU)Qfz~
zQR(9yAY)SNLXdIkZ}h}WNMq;~`#@T?6JV3lk{X~)NiX=rv}x(7G>Fegzoazzth7H4
ziXKW=T33NSlCE5WUR&8`8_=?oJ^45!>}4%<Q_4Z6qhe`C*}Rn?M`V{`Fy<_4sD~yO
z*?r1;yUMO{(di~D*bU+?JN+~!>LL3@kJd5SB`S0Al&zy5x0ftS3=Q5gX)0KJWcS0Y
zX!^?1u43@G>@=0<_{lyy3Q&Jp!EZ1)KsNOm#sX#S2O)7n_9WFr2FW(31N5ZK<~NX2
zGFz&!3YOKL0a%EvW+8q^p|b6C^Da#GGaV+wW#f~;JT1HU6$Bz=<5b~sMy4E~&v!@4
zIvxV_tgMt$Y*Df=>p-Gqj~4;-oQ!V+z2{}KbV!Pkee@ezu`+u<*c2z*NZ0w|WzQ#}
zbwReg2Ca*-mu)eL1X($4$ceJML0Gj*vR0}HxGdWejK4^djGqFOWLX)?Hmq|~WZhAa
zPnF4LAaO<Z#Zt7=WE<$l;8mF;Ida!zj~zuTUG};UY|4<iQGD#WOm!P*nX(_p!ICAb
zc^RGAvYc3m=g1aQK~1h~ErliWWKB%S<;x5u7%Pyipa^TBOwk2#YmscFAFzvM4HRf9
zkp*wVL`!84-@;&-><=C!%4PGCAb&%)U<jIS%4R8+RUz|>#5z^VoL+^BD%mX69o~{L
zMj&1-3!#_dZCSb*nrdWjMUcBA;~s^;UD=U2P*f|+dkLL&R@onvtgV+lO|RGn*``fs
zHOki0M=kEj)_w`nB>S0u`OPvmxdbh;&0k=hTV>j0bhgPB>_V$uHW&`|9Wo=i1f8-k
zp9WZu?457G(kpxQBv|@n`$D0&UpA*3tpS;RJy`C`tm;+>4$4MUz#fv_A=hhI_8Ofn
zM`S^^kRO$qJRvwHYc!)ZF5{8+J|SZ~hXr~dJ2@9CGbwXiiD^&CyvQ$_mhH|%=ZtI_
zU3r+5+2KC=+=ns`dPhByIZ{ortvr$90(Nqvl`_`$@)h*_I>=w9`T|G!vvig|BLC$O
zj5#WABEQH<USN+gXZbXF4=!>=8i=brlZ!Do`ERzc-d#RKSw|1~?^75%CKvQz5}tA`
zC7!+Hl_vn^E#FDy2|n^mpTi1YdEq-&XgV%;qExe=eBN2e`^%jcK|VnK%qt*)a`7xA
zPROrOon?@`)E!owl*f?Qe@dQ8u41r!;5J$z@|A1R3Y9xO0$7-Q1MOPj@&;d6aayjV
z(wzu-90eK9$hXjIH&Wj6B7MH?tla-U=Te?r0r_aT8-*9n$#rgMotI0aAs-`mpe;C7
z?n8A6aq<+3`^3xNBp3C9{3zXTxG0~u7h?(X#(Tg{lm~W0{U!MbeU{;}yq(NWk}pvJ
zI$6GrUWzI5>{aysOO?;3EB;sH6>}kxCLfyz`Kxjh0}|Kd(gCbqy8Pq?tW1XdE;;zu
z<?U|)CR6T3enOUffGTpb<;_Q7Q;vLz9@x3^Iqd+;lS_TDhWYZ9bUG@K&!OmGp}eRS
z;zjbzf6=m*%D2{|Stj2?k43qBf->wk00Z?m<tyBvqC%d)1xuy;=>w3cl5h3{%Pn~#
zogu2_+w-C6w*1CZV5yNuC&AD=@{4RJyel_707|X=_tWUClYdIza;%rPjRLbleti>W
z)@YS???LZ9xoHtdll<@v2sX>BKgDEP<oo^rXsg_Z4pMFM_+kjQ%WLSM+ab@RijPit
z-21@plF#mdT(|ttG~{~Z-}Qm?%HR7I;(hXKVVGIJJdcj119Az~;oX-%M>m%S<yJF=
z9){#|S3~`<+?`5AM&vTuwnpXQbo+Bmo<KjZaruJf5S);&{{k!z<Ze{7HYvYN!S*Tn
zkHj)95A_1ejJzQN#>~n~Wq^Jt&)kCLdL;Lujlx#Jt3=CAA)gO%d&P*A{B;M#A&T%i
zDqLt|KB9P&oSvf!Un-<<QuO}=yPXxDNx*hdq)`2ctKuT1PuvtfzoX@@c;gVnJruuF
zrQ$Kg7f*tCD#A)2?xhHGgC=i<UnA7}DBS6w>8l8*xg1yQ4yXKspCZ5?F#ZZ*Ce#Ng
zo+NiNP;v2VkQ0h;E?_K3v54xRPAa0SA%9A7_!Eo;E3Q&%GDOj-go;qbWAvS#Fhy}2
zTHy-C<4|#0v6?o`2*tNNC_1CK@f%2_Vv>@WXBBfL^!bb^#a;5SqZPkVEx<X&_w;T)
zuUH!Z`548X2DC0Ip7;^uvf_XfCYq$!)C5ge6d{z9NK>%rw|-SIO^N60ia8YI$W-j2
zqO2^1o?h@JilY(GTc&8-36^q&KP44zDE8pTjq*i>JN<zw6npOgyHX+A0f{O_KHXfu
zrC2wMR<%M$5w#k{GoOO<j^a;0tmR!rB%O?F6-f>-txj>b6QK2q=}K@mDxN+LP4^U^
zU%`}`6i!qO)~sl!qfd)MOG$+`MGC!kt?i0W1(4`aeCz_WPQ?YP-|bQq*h0QrVN0vm
zqd4gRi9SUodC~of+W!K9imN9uc3;7ud-sEi6@@T#NO3a`;=_so@})-<4EiCBDr&A^
zY)tWVI9lV1mG%IeP<&&A+6Pv}5lT}{DiX+3o>HjaL~BM7AO-fU;vOa8A1cN=!1_q>
z2VIl1Ro>(S#!k700uc_%v>cf2sBEV*?Gfdl6ni_W+^`?SN$KAOOc!O<8cftxx$O>G
zZptdUV(hNW$p`UJTAyDF`D4l}wHWkNW>QecTlxAFH2EkS(xJ&$`PP@fKCYBe_TEpq
zzZt||X?h<volrhl1WiFoe>!xWR60@>@hPS5TZ{!OQ_2ArqFhfdLAbK*8fJD{`9K4f
z2<1;((0NvwZ+!}8L@9R|F&M3U*$X5_>5vbFvC4$qP#>pUR{++F$``3{GC^5J$Erl-
z<5ZfGq;#ghcCs>l0xT&?#xk_hlsUzi(p9C;4%l=}dG#>Bt}EA30w7cQ=Q>!QrSzw-
z7iTN~j-=-=N4fS626L5<(=VYwIgcs;3zanqXcZ|RL}08~=|(w%66L^ekS|rL=EIm9
z%Jo#FbW^#I&e9diPzotmD*XjeU!|P)D^})~vXjELHOhc`h~H7-pSt3gt9+MEBK1mz
z4LyGi%ANOMO`~$}MPN58Uswi(ElM|v7PKnWl&Wu2esC2k+Ldm*FwqX>ReGroC@)8&
z^S*NRHLwgS=h9X-r0k$V&tc_W+U`b_yLtgOs@zRp;h6HSAI8R&p__p+p?p7_p1%jm
z4BC4qm3uAVnNs$Vn>4MwM`_O)rKlKWR{7bJQ1MW?>I0BR%D?T<X{$2-0u^?u8oDT8
zulkhS4F}b4KLX5A<zx$%BdU=qs6VPodlQ{bD&|E@$ys%m999=q+UFRvx~fdkn7x~7
z10As4Rn1LM@1gqZ7_g72Jbni8RGp$5sXnTKD9HP&dcOzDan;@oOvX=@-~!^Wda4Fv
z0ji~x!3tDGegTCiR5o-;D@awi9IaqgTqX<+QT^{VkWkfj@}R=3s^zH|3|Aebob_qd
ztBJ58LbaGQol#loWgMwGLC?rpRWp4UC`$GI$B>U!c`U$u&#CI^p**kJeilm_qta9D
zM4T#$N?7AnKb!=)pn4$%0vA;_HvyfX8czgEqRKdk&Loxf3n~jvRx#*cpQ7@lTGCXN
z{zYiIqGFSyou=YbrsS%s>s45IO;!0UIMY?hXRst0Dn0!!uB&Dj10_>+i0<QNsXSIf
zMYbw_9~L%8b%;K+pQjq26jY(AiB9W9Dn%MlidBx*;{YvDy%_<CQWc-RYEh;di-APB
zYIg~+Z>UB;!PrgJpKC!XR3FxWRH}X}hkTXlGde`yQpKr3s#OurAh%T?evMVTtLjRG
zF}12bDtxI^9iSLxy~^4T4GpToM%de=8to?kvstx`-n1>MXUU^!RoxGRe4Fao0jO_R
z`8@~Hp?W_DoSmw}2e71Fsz5qOb*mbZKzdXyz3A*!ef$_y^r_tM0Ht4LNBir5D%6C|
zA=Pz0j2TsZ^PelP(oz6&TveV$*ViUgHuUY12db|RV}&MFpRIwWDb-KAAULg>rJZ<2
zB??97tm+vma(bxBEkWlal{dL%_G->|AP(x6J)zK1{ld3cpd;!vItUz9KS>{jaZ;b6
zuQ55R=g`Fy7qylSg|6x>Y+ly6Zfbu8K;6|%@4+Y!wNnn{z0{9wg$i%=nlK3Zs0*le
z!&kkXN)C^!j|BkKPu)qukwEp&3!(RfdiEZy4^nUY4&<adbp~Lk)bm}?3RW-q0~*5A
z^%QytR}20JD^9Ebya^4~2=#Cl6rNEZFG4d?-RKR_v+AH1(27#uF+n0){pMScIHz86
z8ffR$Kl)(4G3q8tt6fs3ZUW0?^*<DDPEvnM@%Uu*UivOXiu$r0z*5yqL$DTC)LGe(
zOH(h%1<O@6ix0D}S=B|GK-1Mqx_gnK?yZ5P*VUF|Xl1G^+rgTpev^I)+3I`$04+zo
zm<P06^}b_Jk*B^wcbxOp2WjgsP}^*Rc%j<uJ!mRY|9l0e6{}yO-MvJ8{sW+t;;#kH
zGId7}<jU1n(>Ivf4fTP20KKV>B)6eL?Q<2RQvJaisHjpa?m_UD+9?>buU0=#7x!<g
z<rL<wQHSz@eMi0207LJpZ>K?ht-6R32X$(1I`h=4$9@HAP&a%HxkhzwH^@Epzq3%^
zq+V;KKvT2Y-Wi%&)IHf4Y*nA3Fie}ekA9`?>b8pj?NG;FfWl6-{|rc%`a>!N=~m~_
zZL%KqosVFBulmk0i1(=_6i)0{OZ2d5Kz&e*)_pa<37muKb|0_|sr@%X?Xdcb8p=P6
zs83Uzc~pI#4~a4L^AqSCSG!Yga6(<M5fTs7-^7DVs#jNlb4u+%5B02CP450fb<7Kx
z%p<j)&RX`GZ(ak7gT|L?+8i}L10Y8<r`y1CRI~OHX6B^%=tqD#YucDp@$aJf;Au?M
zRb%rZSlu+6mVw7z6TSfw9-8J2P;pGNm=0i`n(xTP_0kxW;Plq~^A(7XCgUy^*jJ;a
zz38~+qaB!UfaY&X!v|{0D7bh+qg;ZS1!*?MgY%@uCkh%)X?DP|x6TdLR6U8_5X}-Q
z?+DdM=nN625m8biT+_4?Xs0!AlKUH>@u2M38BN8TFh5e$ti;$^%{p>;qcjaNfS%WE
zq~g;U&11AL$7-Bu>yOj;uEiwcH5<mjazWE)!6Ytf2Iqs*nxMH)rFDs#ghSxDr1^_Z
z6qhwS%ORhndHoBtk~OYku%>8aPhb&JHTDxQ?TRK(3%N8+F|F)X%>fG1U(?*Bg2Z&q
z8Tt%;hUS?~u=l#gn_i}wn(kqYWocH^rLb&Gygy9Kv1%3-Loin}@(C2?X-?6LK40?|
zg~<yv`4p5X)VS^fOp!(v2=j|IS)W0^L^IzT>Pt08=$3w&X5(qJ$~E0R;Jl%6B$xcA
zrpgJe3eB<;kgL@ABm=BUBkF{{TbduAhd{N)ns^O7w>8dlptnX-xfJA%W*5bV?rMIc
z^Kz|b{~u6Tr#W{Ug7q5TIY4XB%%Ma{qo(FEI`3(&HUh0l^MKsCX3gIeWoXej?!qFp
zYQ9{F<!aOX`wdvyHS*2)qjhQC=!MzcniOjURP<<`BKNshGyi$C`ZOZ)I{G!+5+OgJ
zNg`kVzUHfUAULR5MG560%?IRA4Qtwtz}^wfpB!M1YW!(~8q>T=k+gA*ArKZ$XqxCc
z7rfqEuxV1`NymgK%{XmB)0+32=y)`v37kc9R>Q3X&qK}p*MR*<Bis#QtIeij96RlN
zXUxK0`*#>R9klb_ghEH{vs8j{L>p5LvyW<>E&#<z8+s6WowWk0F?P}Jr*Md?);9<!
zZd$)hAnw{Q1*YVo{cQ#1-;ZhEH$mQ0Tl6)I@zPf91B|!!k_nUX(MAk`)mOVL0iDOS
zukA$3Pn$Ca;;;RBF608VQB)lns0|_0PH2CiY(kJW!2<OswSR@6^OQC(0nou(7Jc6?
zL|dH+5~?-tr24Zk?R%LpI9z+<XOPocKgwrEXk95DaaL=NhKeX{6+IQv+UWDZKBtZS
z0Il=dAGlzN(LSUANUT=B2Apx)viH!6*LInJazR@i3eJn#AAdqCLHjT5=ZV_Ed~{yY
zUZi}M^|JOI0eX|P(<`u~$=Y38Fqoo^p--WtYCqdekD4}jE?CmE2We%mYAboL;+pn}
z^H7+seXS638Ctu4p!d4=g=?60ruJtINS4;i8=To%17*{5w5wtPovRHT24|jjPC7dC
zt=h*a!c?H`qhf+WZSY4>SfqWGst<~_C6p;C(YDWlrcy2UQ;;(4b=uI&wJ%Z{|AzL3
zy=dLks*OOY&}P%sqDrmL`_NmZWsO1Lmi7}KI;*w!o&mY7?W7<@jrQF{2;9+Hmr_aK
zUG4rokf_zldO_;6-_mcVUOVUx6%AUyRalEgZR0hNd)kV4tVNSHD*&WfTSMRYXwy!T
zBi63H=?)bg+E3e{w^Mtl9jz|y&t`CTYhR#@Y>&463vl*oO*J5W+Fa`Z)}&wiDJ8@P
zv~%cad|z8g)f$7^pXszQr2YB<EFIQXQf_`k>sbYXQSBN!`iyDC{{nPeyOnl`3GIG6
zkO$gblslT#_HF~2(r#V@lxgj|E@;hY4{5+Mt9_2D`5$T-wp6qANPC#PEL+`fN<rD_
z(mSBuUMHS|sX6HSw?fcS7q|lCh%S#l33*g^hr(n|x@+qJ<E(S1Ba@5nP%y?^bzE=A
zx#`Nzq0?QLyBg{}bZONPKc>qgZ^KjPK$qpcbW8rG{DZgdlS?qlN7qAdcwgQ3x!^gj
zdwU_!{B#R+(B!XM_bt!@boS4nGf-FI0CGY%`xfMabVXEueNvbA0p@Z__Ydt%!MfX3
zU<uLbUIJ#Q&X!8WPV3qz#1f(7lD%him+(Wh&W+Lql4~BVJ4t1}=X4E17#yqnQ;P+T
z(+$pnV7yLBn^=nOnS;=js{4#`saJF#?SaBH-LIw4bX6DgB&K~$w{ihG({;Xdg2~XG
zp*Q7qU1tSIrmlvnGP88*c~F$CE8GASYmRPP7BuDR#FXR9)8&%~m#>r4d8$CSnDYLG
zx{!-tDboG(G+2st#bUse=q7n!Db;=Q5d_L~&L2Txx$Y+|SZ?TQC((IR*E=6_6}n-{
zD^=?F-LSq&r_F*fw{*+w(5hDHoE8A)wl1IUBG%~UZU(udJAM`tcXfSY%&Atl>tBG@
z>EeB_Corw+)&ROm_a>4zbDMR3bf#?4t)=5dtFHS9_}g@8uHbLi>3z}a(1jKQvQrlo
zj#ig0ihSs9-7ZS#^yoh6!2Ei3J|SrJ>Hb=dh3VIgxxl~yU92xK@9RcdV9KEGZZTRz
zx<yusxee=9d<)hQ-41e8M|EoYXRBkn3ffu5b*@hVZ9->_g{B9(B`={hse6a&`lfUx
zRv0s_dwvhdL){QX93JU@vIVxSeoYL(?DX?$v6A-sSNx&KLH~9JjB(VDJ_db9^ucTC
zg>_UPv>TvK`jFLNb=G^(bubsb2fg=P^&xRUbJOqafI@eDRWimr^b0AubxhxkBhOq<
z{U^N`^U|B%0I0WKO;LFt{UQ&veDxo#qMyG$i}JvJ`j6-&?XU0p999JAMZeMa#Derz
zdPkhpzf4KFQ~Kw|z#6R23j<7uJ~9IqhU!nzX8^+VNn)^s>sxyPdRiYrFcJE-8zFE;
zKSg2jNPSv0$XPwh4|9pqtKR{M)~`GbfpdB<x<`Lr@9{aHWAsgUCaiN~^&5~lm>Z|h
zpi01a{na=OUeHT~F#n>yekmjp^q!P|OVm#}qIF5{l>uWe>m3$i+DUpzDO$<;cKREn
z=nEEtr0S8H!!xBH{}d!mzivCoRsGZu$TfX4{kqcioih-(X6XN+sQz_*WdV9K^(*P@
zoTYz}Y8SHgv6L0d(ZBFNfadBy{S>pv)4!Dsn0)=J<<MK8pZ5rV*h2mC>u43}$2u`q
ztWTgcX^DQ6Vk4z`Zz?4()5lQis9b+Ygw_rHhQBfEn^t||GOSRAewzU^tknN92Ub++
z{l0<xE&Uu76jtj$pk(}QeFz0LYV`NsL+2fR9sPao>i?#XRMhH2==rJBH+Mj;UY}3z
zmIi${Z3T_`4UrIN)*B9krA0sY9Q3v7->t^X+Vs{!Psq3HQz~Fvhdz}qX?5yfS^=0Y
zy+8)}Zv8kFhxF*TQGI%^epfgI`t-XV!KQwFDE+kt^m8enbYI^<HF$&iv?n1xq`#Vk
zv0?q1VT_IF->QMaQT?_kfQ{*Ydkp%<^*>puhIT@~owmm*y@LYs)B2Ni4w})gYXZ!y
z{=OSnAL2I$^^f%PDKlwni0%ZjGaLwp3VVb5>yUFW#FLleXn6H;n0CYvLy4rLhV^te
z&B>5VKM!ZahjjbF#ju@%N3I6;R(fH%8Sec69(Ti>vryq-_<A$Yju|X;Qu8!03C7D1
zNRdi!!@(kS`WT*G3wwPH+sRKpZWw<OEkDELag6yJ-l&8?fT4)CvOq)ZZ5VpOu#Xa=
zL56OMN1rsjX-4amVc;|!*n$nG=yeccaBu(#HMmmtG0af%4_e`dgbTnvZHOsHXM|zT
zk64Q{hLJCzH_|X~1<=kK!kMr>%20S5EYXJNsL0}+p@1T~=M6Q5ATfr$bc;LIaO4fN
z;tU5~1a!Q?*h~)N1%oHK;uj6JbX6e1usa&^iH5UdSg1>e9&#uy8{%g%mSp&cqGZX2
z?<pmcVsM#+`cy+8d5TvI93EO}hF$MK?y6xA)x=yg<mNzOy5TKvjAa;J@<eBrA%^Zt
zWE-}9j+QmY5I}kNT*K%B@Z=drYoRIM@B@9QtH7|40s)1F@2JqN$e^cqYq6o265l0;
zPO88tHFVM2v&>-n7cAw5?JLo`VW?z5{HCFMHB?j>9M@qIm4=rnt5s!qL@(xBh6GBl
zR$C1+^4xA4y4yf%3@RmNc*l@P(UiM}i+Tvw8nP^qs5AUb8KioHgDuQ&Fua_Cu|~r*
zm95<~{7D{plR<MFOWACgc>)40hJhkj*lKuf3!vK!Np!YqH{5jr=`h6Hg<Pk>I{Z06
zy9~t%Fu2?BJO#;n3`joVQ8R3#D-L~zljKMB8=~k#G6RO}Bw*h+^!^U>2My1=f(#i}
zihwd~c=sKkj2IkNf{Yp#QCfG*(3}FfaYM~qkO@P71~fb{FevjoX-Kou+hxk|-UG~O
z+OVVvf-?p=<pgI9R|YWl(6EBMvPXvI#~@*A^rgSAow1vCEqh~FG6WoqNmLH$XjHnx
z>?6h|D>OM97irPyV!X2+EUw18lxcG_>Kw2n?#9YSV0swGzN3KUG2_@KsP{Bp%ZH$s
zF`KH;yp7JULBhxAM>V0oMok_T__%SHVtszbuc&g^-}sCiodL#%9*{s|3Wa1(82_b>
zBFGp_TiHqDmaXVKWlRWw!eHZ$rvM#dydZ^5p~kOY{jXr!cxyW(!i{38_B(A<l)|P6
zquUwCpE3USBU+J0ANqNnHL5cq7-fv2m}s<-OS#B%#$A*WId7C)!B~v(9V)tuH9nx4
zvN&UFJeD%v*iRQTE*N*UK<=V(6=iu6j2(yQ{g-IGKq=fy#<EEWUN)+=FgVHh0Tp>9
z8-*0=Pcg2ca>!I8mulgz82jjJEonyWB*v~9H_>bVnsHMutWP&ScN}9GM%Pw=T{o7}
zVIkA_<VvW|GDhjZl5Om#i<~*ex;_|V%{4}`A(3ZXNuMvxHy*wZi2~!Y_b{14;~&Y8
zC^G&@zu97=&0~NmF{<OhQflOC(Yj%5Qo`Pw#@7?TQeo_;)KR7JnHRuPWjtjID{dM0
zE(K?`vHmlF-8TODHYQPH>{)<W-?19&!y$OrI83ayM*k+X>WrTb!<c&GIR;3B@zZ3W
zH5xCz3zmDvjXMF;WQ@!PXS4AEJ;p7@q&b*Vt8q&X=G0~kZUA<>anW<o)M0FMf_SI#
zaZ1Q^8J|vqG2O-=DKyz*w3hh6;9lddgOKPmE}}xHeq#X@-whboQZ(|uF<=!s2aOJD
z$PXEhQGjRI*iFH`5#uG=3P+7g>;XDv{4)xsjT=9tt#HD)M+TM$MwJ`nCXLKD(V8;4
zH$u_0(XbHeXN-rf^yRi$V-C3n4~<?6(0XJ%K%0=Q>C-{L*qH=-(6Tpeo`Qsf={Kt4
zbTn=I0Sb?pcGBV>HGTFDtZ*{zp_ihw>AfJRa53##4;ELGhN@rOO!cdv-reLt6<Z#r
zI&y}OnQGkVQS~&vxD%jWCh;K<Z_`1#weDk5(jUmzw0Ih;chclV!HH9*(pRA=*yP<0
zO(CWtdSQl|{`wJ}VWw!hnGtR}{5$4*+LTWD%?Q(*$1rxr6j_C_NRxr$rO~E+PeJ^g
zsm4MHyYr?^?tqCgeclY#Skq6xfW(<Xwt>W(blYL+1=AEING_T_B+nwjbY?Y3qG{q4
zfL=2BQ|Dz<br?XCOeOSkOEx`EC*l-SLNu&MHHA?u=ZY!)C|YTzTnYeOHDzQ{!Spqg
z^Fyr3b(63Qy_u#u5vHAGD$syrn*^R9Ii?f}8t0mx8OGl}&vZx#n0(V33Nsa$tdyoH
zG`T&8&LR_U5f-o5)X)dH5|ba@g(x*ue}%C!)AdYfC^u!rL*ETk-Z_j}Z<<z6K&`?g
zq|(7kQ{rD3tTNTV0dm{aOb&C6$+!(HcT77drgGQx8AU^CP5&!_-a6Bd6s@W^O;|u0
zOux`It45PO<w@?De$Zg?noJBm<eE)G)gUdV6W;)=)ih@%INPkIG&{hwn=D$84pUqs
zCfaE#4uak;QzW@{-KGPJ!P;YLRKccR(@wg>(P!Ge9W4E(xiSb0m|kCqvHPakBTzAD
znt2GlL#7hiD27cp{szm4sp=baj+*3D0WoI!jE=eEChOv*ux7%P!NST;nf^$H71O5s
zJ|Huuk7}T4*7W%~v>uusa<HV2OzS>F%g!vLI#qk~LOS|8n4hD{R7Z0Pxe`ar7aF1W
zsCjKAT2AI?1Xv4av!3FmF6KWPq1V;?6rJGR%m;<T;Bhxc(7E2jT<|3<J!XC>87)uq
zQ<ov(W%l*mk-5YwBk%XP*^k~4e&)@2n6AHBJp)An=EW4K3^YGMk%klI{SJT*GPCvQ
zJZXM24<M(^b@a7|U^BlF$RXxL7EnUXCHZKDnLnnZdbs&IIbNsDyXlA)VO~gSjx*)}
za$6(K`>d~ko;CmcG(e-w&p2ZZqs`~ZX^1gTeF<Y?%^y-2FwR`n21Db`8!0|?!TgIO
z<Sv>=7|@hpJ}iKEqIo&RWiOeFioto=oI~ffB(opwUCHLa78sLa-bsnuRP!mi0(HgA
z|CNr9S>~U|(9AaPqpc{%{5-uAbIoEV)aRMg{({1M^J#y`7n&2^$9#*-GRmnHn|1Gj
zl$e*%Nxanj+Agq^o0pSsc*DH*Z;ahE&(B6@g}Lt)fK{4fE<w>Pv&9)>)#lj+RM>Xg
zeEB$<HRgPJsP35mM?b*3W^XFBs5Ni647574F%(m)H{ULU`Udj?3pg9io5j$3&%7)W
zGi)+{K&ilH^S<Z6(qeY6#mcmrLwOKyGnZ8Yv)%kFod-J1p_Jh3G<(6fv(D`@-`s@3
zZu4VQa?xYHKzl*2`RIHI_L=w7W8ZI{Po)+E=Ix)O^S(Ll3|fO`?{SbJv)wHS44Yql
z73xRK-6gPT)V!C>9y4#EkiocFOm5AD`J@)6O_{%b517;Dp#9MI!i@R%R;Zsfo7&L(
z&}`?Ev&8xY1#%oLk2iuiTEboe<Pl5V3y^lQ#8WAVv!#^<buN}X`a`%{+9;IhX1N##
z77xq*K`h-dOW!4MdRhu7GUsLap$9D9mU-)e>0^13(jmSUZ}PB?Thd+x@w3GIj+yvd
zwpyQuV1Q-(5_keFpU}DXgvE)j4hC6X3c*xPTB<$)+9}J+O_*k|<ry<bh$WTEHbN~Q
z(?%a=>DvvKaLcQsu<5krW;R+8mdl-Jov}2K*B5DFQQY~g<%e>RD2vToV2QR|RrxN?
zWmvxp!(TPd@;v2K<1G_k!Ile__vWE>(emh3D7s{^hG3qTEgyNovLwsv6wgeyh~+Ra
z#qu_Ve^V`2DB_xCSw_CaRZA^>r|_C(^8#?DTlP>{N`~d!i%^?sS<wKwEX$g3U}jq$
zx6<Xe97}L2=8|ifP6AK9<qscNUtn2H#odJ#%dcQ5vi!3Qg2k59d*CdwtfGWisYOkD
zW0~bcs!J}nyhp{(H!OW)u>Pjy{vN2Pu(bYnda;C2QE8PWaXz4LS;XYiR9hHb6o9&I
zaq-90YAhTsB<@(sDQ<SxvX3IRwU!L}o7Y*kQt+eRvMmtU4VKAPXlk@fj>C$3mKF5V
zYO(}S9-`T@j*hx5mLmG-RjVZ^5#nu@wYOksyXDK@uudJ8t)WocX~}z)zOm9}dCmyd
zZp&U1diyMEs6@Tr@-9^<4OrqHLgGGNF9031utZ=PvTUcL$%w__CCH6h-V&p8%yR2_
zw8kyI3|KK?*%%GENs9v|wx%p`^FXF8mkDLYvLgvBvzAsoC)T--EKDf`ZI^GchhDqo
zuPM;7U!ENSd57iKe}NT_%Vp$Z99jMnWe|=oS3U<cr{#ZAX^`{si88E(%W|jtXt^%W
ztwzgj`M>|wbuDiXfuSDDBPn=&Y`Nbk*1~i7@}>Xh=sLryJesy9QPVZX6k}{@nnX?0
zoZfq{BvBI+%@<QG=`qD47Ellr1f(j`dq=ADqEzX<7ZEHVA_@ZEJuiRe+MStuX7@a0
zcV_khou?Vk(4xTR#`s_pOt>>PP(8~T#;8A-9t<an`Fk=xpt?*i28&|ZXBo$)0prc6
zK&EDa5956i{PktLJPx~ljH3N$`7=JG10Mm54{2X_j`7K2{I2I2@t;92kYQU6lnadB
zZWsz;>>EL6sEtuUr?|oxRw^nFXUJR7ieUJC2>nRLSM-L7Vysc3Gn&ySg+?sn4LWNS
z$7rJyUh#}q@?kfDkwtH<M8*$qp)-l`FU3QX8O*oAOJ)4>F%&K`zN5Wj8pBBCcj=78
zTOb(>+tU>0%w%NnL9!Sux_z@5kN<@+U1GSqp_Rk<i3)FW87@uG$Y->dVrB{$`~A@>
zWb{&&tcVeq4ZFpR#S}a&VZ23`M=9gYC*Z{uM#{&4E@Q;|LZqA#P3IOX7_#SqS;?re
zorQ@i#=2oBRx@5C7i$<_(a%-O_+c|(>KF|L(5Pn|>H)8Tp=|-Lks*tRUK7K*7o>&p
z<Oz^gMo>CTv@wp;v$>sdt`c@T81o9y+0FRiLm2E~j2{J9FC*bO%uF9c{u6zzr=KxQ
z1sVekPkMe2GTvGSGQ^0#0FCR62--moGZJVMGs4hQ$;%B!U^AS#$#`ouL~b$Ge-ARs
z*g#(h7-QU_Pn6wZ6s~~6IO7Q?sNZF*{~N6d#%U)&-(%c54wOko+&TK<%zeh_HZ&hF
zY-ixq6yvF%q4AK>ybdrkjH<J6c$Trb9V47$toj}%4l%!&hfaIuZ?vd6%v{BR<WZ(b
zjj<eK?%57?2j=^~K*5puDwVYyXAaW=+!M^GaOgQPAMb^|lgwo+XanoQe0vfauFS`V
zfOd-M5D1ymOh?+ex-t3xLD8LggRXTCX5m)wJejk<LBWf;h_Y;FnP02}@n*iU5ukod
z0|l=9nH;Lc4PZ)>&^pKbXaKGA%-0LxeIRqkQ<$y`%naHF+k%;fUm+91eB?{WgfbV0
zp*M^vegU1~%m);9k6<R!=p&hWTH8l6Uvq{?4D)6#I%Am$QRs|g{zrkfc&3Hko(as>
zK=2ZoBHGs_G57u-NHVi?3cM8NbrVLG%3Ml!MVgKI%Y3+>&is`EK^e@Yk6;v;OeXCc
zvY0V){9M`0)`P&l#Pqrjkz8iW6!i0$Z9+)qGw)mkOab#9dPfy96W&0pi221Kh!isy
zQhK|T`2%HGFEh8%+WZRh@qCan=A#F|D`(m+eS%-Dg1L$XnM&s2qafAH8BZ{;GJm1<
zYz^~$imTKzLurXs$4vPSGt<bF&=-N4n49T1MKkl)35c{X|7wGJD>KU;oo&n>+VizD
zr4AsS%s%>}PZ!gXCa9Y^)&qZgn6ow=%=a?A_5-_*Sxi?_Kl9IVFbA2}>Gr?IoGL<V
zh-tb-w*zzCLtqax>)T*(gc(Zt)*H<9+t9noj9r20y2X4iAFbO=2?Y^GnQru|y2CWm
zLu8yemIINyOwB=fF~M}Q*noYH`Q8*@CYg3rUv;0khW0B{%$Vme&}rt<c@TZbEc^+Q
zGt9$wz@B9~wSYIr?Am}|<PdA~0g%HiC)%1EVF@Ytca(L!1LPPhihfrIRuesm9a-<(
zg5GhK%SVuOV(nc??>}dj^i`NR$@2aRGA=BCf5^D9rl#S(8|yPW5O<dBF^HUDHT?)Q
z50=*=`0L5yJqdrkSb0{6oMk1}!9yRGQzlxztas>P?Z-M*f?@l!5@{(Cz}o&X^v<!=
zBWRsxJ%w*%+7?`3?WFW}5Nqlu3@w=T<1_Frg!R*p@FJA;*bsaQV{JNv!GyD9l=F^Y
zU8h`oBrAoUT2ZVLO8-Q&o_r1>v8-=rU@(sLRS)#yS+87#zX>dV+Jz^w`u`6Wl31Oz
znNMc<=fHw3m9>oa5f@pZ^ii8M)+I{Eq_a4m0w#mCZ3d#*tVgI8{u1lJUoe=%TIK_V
zT$VGDJk}1{+~%{6kcS1V3rEmd#4@!&y_i)>Ig1ije<IA6vSgtEyUcQ@{mvEEKeWmz
zv$39k0MQE8_$M$?$;zSH)+*N0ztE~?JtYG6Ro0Hj&{@M`)3UynWv7N0b*y`oa<6AO
zQKY(ol}NkGMwZ_syl-Z0qmxH1tc~x&d@Jja9-VEhr>WY%on@m!k`7h^9fIy;+3ddo
zvzztRIf(YKT5p5&vZ84P*T<5q1a?2`7!{RYV+~O<bci+SkIw5XZ7~Kj%xa}I?FdUr
zA&DETPpH!FCaZ@c+_zaB|NAHg>*@9A9AoWk2lO4*i&T6u&ia8Or*~QIHp&J~ux?Xc
zaFX>8y>jle&Xob}0jskd!=7S|QaXN`b<YWYKV&^kTbvoz@I#=@vL@w_oMY8CL+=o~
zoGwdy_7NWRj<5|>(Q%Z0|3z3j#`dNxodY|DUYL&T!;Zi_&b}K>0i+Y`k#C{l%)apf
zWKOd4sm9xdeSsEYuI%y4Ag9<1e}afR+Z=}08TN*c(DGofq!g<sdkyU?yx0fK7|U69
z$1@m<H#>3!mVDW}UWB85?0`Y&`LiSFqksYI1j@0WWACk_0PcBq!z9oG*{{;`CWyV6
z-Uq?##Z%A-VShk@_E7fw6rKrVw^OxaINK=``VnkzT8l@r<#kYqV!Qf4GMfGBv*5+B
zAEj_#9Q*eaD8#cDOv6F~+oFMFBKtd904A}kLMefg%nqceeG2=(|A2Op9k2^ilE!xK
z0!e4fzJNvsTTZ3;ne09El)l8?PGOE5_BcJ4bJ^+_Fy1`2kiuX2>=(;H3fQZ@2WBC=
z{%s7Yi0wrC*<yBfBsxpk?<|7IW%gAuJhWY5^WEWh8GF?R$dt2(8NjY&zf6U;RqWL|
z@T%DvRF+c1meFg!mffttT-31xQoyTcug`^R4eWg%fHblbDXZVa9tweLE$q#-&S+)l
z)d0GU?KcHpJ3Fx*C>?Aq?HxL8Y^wy!F7`Y+lHJ4Zd<@vV?2aRl>0`Hl1YSSeodU-L
zZ08pEG{}Bw13bLW_N8-T!|dfkkP&uz2lQ^RKYtsNH`#yDjdP3LXM*Hy_HVZUHp=#<
zrQ#S{{t3u9dl?^KciFZ;TAod?Pg7Lt9{V-QvrV#lF9GHO+lMNkr`RjCAk%E#4Rp@1
zO_ZgdWjBSQHOEfa4&EV-7ga{sb3Tp+%3;puH_<x6>88}fF-~m}Bpo=PQZ<evr)Cip
zj&m}j;r0p6YqnCLIdPVr#6X=nFW19w7f!MiqOP3TFz`-sJm~FznzNi9+HRaM%EP#G
zKBey?cyiVqM9Yg)xdQ_|%Zb>JmN#dN0_8p&$;VLe<&4Im<;VGjq7VL@pmaDBz|m8(
z?>r~mk=CDqoVJx{Uf`6{$|Q)hhaSwqoVh~$T%nx5C;%MB`SELb5ze_pm7kHEol7yo
zD9-0kK|Pw&K%b3^;Rq<`7|S{L4kY6^zcZj7&soO@W+G?tpFm0Cyu219nRAU+4Jn)-
zpP>Y1Drey{aPcB%$v5at<7`aEg^|Je?+NH<a<b_QmRX!^I?kKTd8ZwcmpBP@ur!Br
zloERR9D5$@7I1deK)sMt^)XsSoR8^lD&}}+gOqTB=EL7o&K_FIU*@=lL*xo47FWD&
zK^Z6JJHV84Qbxe6;JllSF;#NZR4`G+d5R92RC9LwpmmkwK#74G&H^gjspUMc2C3t`
zVTM9ICnE@?fg>#fN;Bs>+BddvUdn*^R?fa3A=$?1kHa9^IT^t)-@!RWn-yCp2gL=r
z0XV+&uIlDkDIC_rS-}G7<@`+L2z{IgI&9F-x#$M$0ZuA~Wd}L`(pQ?VahA|wogt3>
z9!$w~{C3bA<`mG8=n>8}1JrMDuF&mpn{$RLWJftg=g}JDtbGXeJ2p-#MY_j1UsLe@
zE+_GAn3&*{Yyjvz&Z$2DI?1_9E6)3zfB%F21CIC*E|w_{FBe`+bJC~L`H=GkEkkEG
z|LGt(%jx_BtvSxwy+Ap{Wv>IKJ(o8Ky~ErO$I&{%{dX654qRI`t#%x_r`EvX<6Ipb
zYdFD8bOyE)H$n*F%ypyn`blnM4q7hU)G82H?y0pfaf<6kSLbOiV;Y_A+|A_78E!fS
zhdsEjjX}?oo3{g&ytr#CVD~I{zy-vc`v?UQeYj_AwA%6I4pJ1`kK5@3rayNcoxeZF
zZTH4Ro#)P{jdCFONs3lo;5O1eEQq_CDp`WL>6PdV;pU%%-B9j{ZIBG()=(BHoLkfi
zUIbUP10;(34SmrdntT2lS~1+AD!3NQZO~IycN}-_5s-MUXEMA<;J!@h%tY=5%9<r{
z_YR^nnaf)V{S@xgba|z5^|ZK5=N7*LkqmC)|G}9|?rRS)>@02+m4ak*k=Vkm!gZpu
zupF+O@=dv1_9B?i<Cf8TB%fO}L+`&r?)b0pyNJ6^f!<>7=ahph;kvkBprzckgV4Cl
z%~}C+g<JJA23p3wPZg`>+z+Wpr-J)pEO?b%yJJwV=DJM4`>WgqKcKUQ`v{$ZspbA$
z2E97&?_9W6&)rAW!VO%9B>IO5jocU{G8Z&)UvC3wGgtW)WLmfv10d7J?VwL@wsZIP
z0=t82rYo?MyQvthF7Et)LAtrKTcFp&ozy_Gm;3Bbu-nJoJC4qN?mMMW7~qC%gik}<
zmx?f?>)gL+ML*0H(00r=!WB@Z`3<ga8OTlU%eUb0E$+O%P`u6kEfN}|TqOml#<;<2
zfqjQ-r1k4vZrgH*OmKHr!{2+{g94bC<k}?y^gj3VlW^t%_j5VO6!%L<I6BRBS_ZI(
z+?DYVnc*&`!1Jt)8?+Pj5bxz}z_#ZVeFM?Myw_I)^a!tkN~4bQ=GxIZ##`hM;=qfl
zh9yUygeq^2^G0c&PVf%C4{Rsit`vxz<W<vl*@ed~h9y_t89I1zipP$G!fD>{7a(rD
zak|mndA9BJOgh7R_a_h!UV<1Jp1iG;=<?#(Z3K)DZ{HcTe0lLtV7z|3Un$Y+&$~>S
zfdJlm$|;@Wy|4sspXa&KOFWR59R(8?c-!fD6U57<)KV}n>mDRSc^cXzh4C_}vMQXn
z#a0f*2;P&Q!$c%+KV>AMcs>+7i{>31g)=cc&xg>6<#l}l634spA{66!g5wZL<UL7y
zo+REvswPV2{Xs9c6y7`Du$#(znLfsGk@r+7MACS+1u&n^TP(n^GkAYQ0y>iy`YD|_
z%;Fh(A#;iMqYC;tyj^jyl*@~wY<nK>9xaCRd9PEcPXTX$Li2^Zm<E_A;yvyPQp~g4
z3%wE^s|r4q@(^>uJ;KYU)pt2>Q7;rKc=7WgS;=G5cB+aeWWZiEFJLcy@#!kBomQMR
zyy9@c)bdnRyIjXxM~i@ZUN99TH}XVOy4J+ow;8-<-iml&xA4;FwbIJ_t{Wn4yjnky
zcHVX)X0(I%FKx#<c?thOp^LYEBgWayn@NF4FVCd|q>tCpMEk#f-pw*F2Y6r6Vc9|6
zAGB<^#&fuZ&LQ5vKCpD1*GT_yWSD1ZgyINq#XN}I;068*kz2e+=;pf3EBz3bMtNc{
z3}TFTs~oP~;pH6y8Rv1ofWlqg{S5dt!Sm~b<UQWZ=TNsz@@9`h<36wTBbcA&#nIm7
zA+L;nkr`h2ddST3k}38!$NPak9dU^N*e)2f=jV}!hxuFS3%W=6`v0JQlpp5-^<(_a
zc9>B|{=gW>asE$~vp>O)eFe@q@n5%xq%)uO7MwY0;|EaQ)`hSA0idq@pEhHlr}!~J
zV4mh*tOT|jzlXvwXZUS&V#<U6tO+JO`SvN$^Wqz?pz|#M?r!+&&F4ObmJk0!GU&^H
zJqCJy{MbHV`tv{e3YY=>UFR?t=lP#eNn;@2RwzdE0{;U(nnC=h6446g=QhAZ2!A!z
z+J*A(QD+!Gf}Vll{Lo7nQv|<&;_;FEee}kP;qRficr1UAw)t^<<=+@+JYRDSUL^2e
zrV`{tekyI+llWU(pqI=qqYzpOf2A!7%~byXKJ|W)zl7ec>HH>2V`T7`UIxkJZ=eNw
z7XN(#^t1U+^ftZ3FD`@K9DWNQyj=cH3Nq&LUsws(^7-*>I9kBZnSw|WKbA5E#r!w@
z;9&{h`!|qM{%^rBbeZ43hSr}~_;WeXFXMmj4gGTdqhEtm@S}G_w36@fGR9QJKVJg#
zSNU6?fWI~T54hmf^1UfHQO6IVBRKW^RkY1-;0wecjeNEmC{6rNjsm)wAK`~q3qQ9V
z&b0C!Wl-qgkKd#Fuam!q4%T$>^L_w!FMl2)atr$SxvyjN{rr&wAUF75(D|C1{4S~<
zzQy;aL;1J)Cn=IX%74xXGRAkKC&V58-6)tC=Rf@gB=7Q1(0>w`;1?doAnx&h{R6E@
zelLYH?(;bqnQg%XzTgvxPVryZ5B+KWdV23Z<fqUhZH7Pk1~g{*-+T@-$Nyj@oH-=e
z`V$oF1uyP{$YH_y5)AE#z>kVdj|z4^kMSN8RH!i|2f<1{#^NXl_yq=!3zq*4loNt5
zy2hOZu9Qu)ISWGQi=`(8L6k{%5iD{CjH_TC<q%H^Zn(hUX@QlJvu=V7q3CoMeCvVM
z8Np9h@H_-gR8#0F_~0e*yaXI8CjYD;EE*`@f-7ot`Unc>4ecv9LBFz}fK4Gze}Rw^
zeE~MX7(K+!30$c{@w{N72%ZKC4vazcf`CmwdXQjwBS3=%kG=)a5J3Q)`3V*L;s^aO
z!H53`$#B8Y1VkbPTVKJHL<)+juq#S%nd0fug7E(!5+nH99pjA^u-Y&)ae^-o!R>f~
zZJ1u134(2O2_y>Y*TZ0vAf5%$WWjcN>ZJ&t_k&NVg7+>%<f7oeE8wLGmL{V!U0|07
z><qz|w9d~IeDDnvvIJdw(3vAhqYB?#!K<{F%@b^&fiwAnKd2g^Kp;tgNTFcNM%7G3
zg4ZIUUo5zk3ucL6b`yLm72Fv>>#{&S3QJc6^Xb`JCK#vsy>h`gU2GMCKVE@)rQmKm
z>{bb`?twzJV9jBWtAgbVVZKK2v=7v41sona>jb}s0=izXl@c@!f{%7k7^qPop9lRW
z!IwkmZ5CXQMrVtFA%RA#U}Fbh+62RtMs624PQY%5;B6~FI|U_FSKTG3qtiv*f@3W}
z=@BS;V4_!WWj|Vdf<_9+^$R*_x&{Pa)8#QJcw7YDHGwMVfB8SbiQRy?F36^$ieZ7Y
z1Opur^!3Bw4Z%GsVYw+-BLmDWK?L26w*}iNJvAy=m<5qB!7MGb?+8NfqBSnqM|tSG
zg2lxUnGpQl47>LPb-%;INx_kNh};*vPqB&zf^8U}ZNZcvpb*SyLC69O`=OvY0Wvd!
zUnAkgtUyIoYIA}^R7ZYD*cu2>d*MH)A#zygPwCPl!eA<rJ1YF_HGm!yK1aJ02chLh
zh&T#M55l$M!re>JIw5>O_03K~ds^Q+3*S(K*iH(EsVc%n_^b;&JuS5Mz=WG{Xa=3`
z!Z)HY-ZR3Q8d&lW`YnNmr%+6R8!zFUD@4u;tuLeHE$l3Wx{olY87*JoLt0$=39D(5
z=PwMVZwCbk+vvVOCsb3G>bx+~7j6gIg!gGZcR^^s5~B|i?(6|GShzzE(Ga0~JY+(J
zNfbd06K?quBwV=U30wjZLVqejixj@}EhM9a?iBTk7TT-9ixF}bVG?46ekULjC*)<J
z6)!ZKpq?Ofq4TVX!pbKAog}oqLCeBq;a5MSnId$f_&}=g4sCrd3OCb{zck_B<Wsuv
zX*$84A<XrINT$&CICxpY`&7=8Ep(t*{Usqw4UrsS21VI(g~jyLD-bRTf<mG2#u(<J
zNVr&qnJE@(=m}9G6x+T9cB$|?dT3u3YN#aTitr_R#g++ApMYYyFrUhZDujz^t5zv|
z#~+eaLXT!lX|?d80i9QcL5~BiM)>S9sMiZ`(+j9U=t(K0MxlZMN1KFA6a;P-K9>c_
z7NKb)pj(CSX(|8ECR}v|Fzvz#%6WAN3tt3wr|?-?Bz6hs;cr2=FzZu@^a$rD2Hh*H
zcpRO5!nh9s+Ap+F5NbdeN*DQ{u!YW~Tobx&2N@C`qcYm-!g4B%92N>F{XZgXpd{uE
zp{I_%cz9E|<q>##OStS4*u5>>m5<h_aEc4XF`+UMtvkYkZde)@3gbcU3Nyl?KOroj
z4@}+@uA@-cr11YJ@N!=mz(wnU@DDCTri9O4!_PY{6jR9Yp)k$`m@~p{c^K!cu*mLz
z`FG)#Q}FGOsN)Y{+l!_LAbMC-_zI@&h-l&(G>(c!=xumR^dwy+4x%N`f#)dldjN&w
zqVioZctZ3$rCppv|NRLsoJG>TaQmd_yHcpTi0a)jGFQ=or=fmIw1g_1PK%aPVY1Cl
zlz$0KchRquvO6RCUJf)5(a<As-&54}E_hy|2`6-(6}>@kJa5sf1mhz*+yqO$qF47p
z(oZx>c{G2K_ilI*AR3_T_Bl}@9o{)Fa(ES%0!6Q10l6Uhi<S~Wq6eGcVX#dUw-fqd
zA{9Li!bQQ9Fo_VYbAo83Xu$=5Mv3137@g6gt<!KOM%0=N6S1N%m%>DxNSz0fc+nxM
z%T5q|X+kSe^bLinlSHvPpd^b5X+x4CI_(0KRM8TO1z!|(T|g^MWLtR*cGE@mlorSk
zz4aJ0GDZ5&0Fxz}p;TYCXe$-!UlOH6pfg9bW-%mlMQ1o@<%!l&R5M@nf5$M;0#Umc
zNTKMn-+^5u8l^W+v1k{?FH1zP`~!bWMUv0JyDSQ)kkS=VkZn6ml!>@60<By$)qqxo
zNRf_Kr6~0lu&YG5G|$zdD;Yq$DmqSU;u_H)MHg#DVg49Qov4ETDOkN|-WphH5N)Tm
zbhGHcVyL%>mV|?}imWG~*Cuk`4PLt_kgD7|L?KC3SluaV%7sjqXgP&ix<&q*Alf7P
zn*xEoqN%?i(kF7+2E~3+6un{xL}{V$X;9=z2W+m1%DEszqUwhr*F_JFP#6|%nni0w
zRF?&?8=?RTh~E^M>C;EIL^mU#ep|G-mQEawio$3KH6|Kc4)^bf#%V1vE*i?k(C&)F
zTnueO#GoARJ<;+fVSZ91p`&~EMU}0X#0R2>XQ41962Af7v?zn}2M<M?C@wG~5>!BM
zR>b=jU~{5XROWn0989J0_TuM}bFwWsES{k)$Pw{WFPKNg?5#jMChk}S4F~aOl&N$S
z|Fsqx$Hh-<f!!10jDH~FByKnW;w=7~UNR@eudRo97x6hNUT_uvs)F7r@hl~sPK#I5
z)5lHR#Dt`~*e4U@j95z-gv~>|m^KKW;uMNLd5OdK!qQoBDCM=h#b1377$5PI6#ViP
zSJ30mPyEPyxaKc@s}3*$;&H07J16$0im&tHpk>et6rYWNYZt`*Ludtw|8xLKu$bk6
zR*0DK4-`Vh2fu>(Fq^oZvIF7b_uTMnM~UxHC@or?zZI<*aU9j1#fq(0(HSR>rZSj#
zF?$^d0wqrZG*P^UQdddh3?4|b_}38VrHHqz!#t&mk3Rx(QJi=PuBC}ZpTcgsSWmg9
z4DsZ*fX)=#&iw<JEO8560@>p4=>+X1@l!c4kt6<*!iu@#`5Qp;#6NYxM83EnAEZE>
zM60tx@$Q#lqDY*%3!uf~)3xB0h>HthsZ{Jt53kGOMkYkAh>NHcqD(xXgEQq~;TqVh
z5bv;YFbkF9^HnfWB^J;Us#-kd44<xwpLi2!HDX6PqhBiyrTe~4JQxZ~^<pUppbg?{
zUqhr(>`O1>Cb5OCl4kMEYmjUayU-$_UHrNdogLx;st4&5H&WqCm-v$~xYjLBe1Vp+
zJ>sGX_|_{fn}9QY;+M+dV!!z2Uw|19KTb6PgW`R(*t#Ze-UdrU;&)EM(d*)As=gc+
zXVd;*MBLF1azniT1oUo-i@O1KOS~fy7H*5ZKZ3%jxc7bdJ0^Z|78dS^2S29zmvQm=
zcVPamcq^Uno)8by8swh%8G5x(ii=WV_rAFJEIJ>EW86Td#BctJ&S~*iHz4v*>{bI0
zXT%>-HRY^Wcn@~x#2e1Q;2}x!Fo?b64O$K!mh7dC`4NfXEx3JDQi!uVwgtx|VH9k4
zkO*jF;V60UQ+RP)@+7S~PDoZzIj@ssBYlO~S>i-LjH~1v<vUMFf`5k>rzNWspzbEQ
zL(6V=NzWoUb4Kz+EIK_T+ea`Zo{|Qt*!7Z_zXSAH$=!be?JbF?i`3>LIaLP}zLGE+
zsGsCVdJFqY%(RydkfeQs@diptE&%j`<ev{<B1qyzxrtzj>tc*4L~@W~6`_(t7XTV2
zsj-KNa7q73kO;}@V1PwR4$|8@O2VP@1<?`?WpZOAqd$Vg+9c;aArmLrv<Rb*mn{1p
zXbF<jJYXkEHZ6u1Ns>2Sg<`Vg*h92ZB<JXwOO>P@1n5Ocd>Dq7CfP(0^mNHHMF7i?
z)b*p4Daq`CUY6wGGXTq$)Y6Lnl4Oht3ptWUs7^0eVoN^*nkR|g1DSluQo61RB+MWv
z7E1K=yeX1I(38AavWZgOC6dReJh4==h(b%3B|GQA{1u7gUjQwW?BGJ7T(XC@Qx%e6
zI$uyJIbR1}m1NV4@V8p>+$=2ANIs+gKT#`jvpoh{Cs`;1vtF`%8=Ps7nEu2-8znp~
zNRuRjGBeGR_h_IklCNul)++gvCb&(K_kU1mm(-<0vP1IDOTg}we6|Q)bV)*}h_zd?
zkaEs_k~m7}_DdS5rgT6u^9ni#B@Y~EQF~1i?+wr)$p`e%y)M~7Pmy8CcXU~fNRm9^
z+6~FlEg1GqiTxW8xg`k@pmkfa(*+`<l2vPfHYO?T0m>bTeJ>QoCD~5^<*p==jm`<l
zdv8JSo@7-d6ecB)QpDrFWW_@|K>R==Sr6uvB!HqD(~@HrpgokRoIz$Jd+C2J%u1rX
z;r^WDF$aJil9p2ukiE2mc0h-vzffTNh?F}Ag`?8dRCa$%I`a}R9i+EXz;l!;-vIP+
zX?Pz*PDpzxjo>7mT}Ab0&eG0LVB)0oC5j@sNc$=v<0^fI4kVqD3MpBATIx=*emCi#
z6yS1~-i*cw&q!|vgLp`tb3r_%ztN7sOZsm%#(P#;AC3`vOP~1-=6$69HwQ3Z=`MP*
z_(=~@_QYTMTqt<90O_Z6V(XlA8<ilQmwHmxHBh>NV&@m6juh7mlCEupXt1=Hk{Th>
z_M0#mD)pd4IAPLpS9FF;t-e5skS^N}g-GeU^iGYEs<`kzT6&c>?J?4RA7I8x|GtMo
z#7U!4(2BQ7OD=#WNS%@ZlPLWo3zm|krfBFVOA9G8nj#g`4WB9<q4(}ZX(z>!)1-gq
zfuu`!UI#Bj>eK^;OzCHxu#_d$Q8FZ3`nny=Uy|;p&q?G+J?IgdD`imRKToPV3dww_
z?LJ-W1=7QGu@+-6aHd2Wqd;e=w37lim!-aXXk3xzdx2LbU0n-ax%8_e;8jS=+rX=o
z{u}^amGm+C%uuy-+rJp$Rq6d~kQ!;GBP`WQ&r&5~opjg>diB!Lc8~_?d$s~-G)nF7
z!hDnTdK@&GrME`mcZ;;if_ZM0o|*!$O&a+D^xLJCv|I0x_HPBRQ#y}U&t1}z0_b&1
zy(rz&BYkNpFngtYXgk#>?f(dp{nDRD;o*RENg(ETP#U=tylc|Pw<-QIBz<`nGS{VU
zXCN~yy-87u5veo9&~8ZI{@;x!9XSq>TT&5KwcM7zM1iqUsr$1)8<X1TO1dLW`T+{#
z(jVwWe^;9FD8MG9tzV;cPx=WJ?M_OSv^l#ky+mii9!OPllz*R+D#m~|EzPro=tHTL
zE~pu4GCc)mrK05kos$;xp?FC466JvGW%DW3a9FmKF2p0Uujwm)M`a!MXdRQSrH!hC
zteCdMjxyx|4D`5cH@)^x$T)g*I?2TJwJvAbZmdsi3r@<OS_*v^nSk=yuClgH$efY|
zeTvT0vhBNJ*G={jC6wJ|g)2bL$bOxHqaL!T72tWvSafrom2nosZEsm4-CRDhS3ZUb
zUs-ZCh@b3}b?Ee$ec=u00GThHz&$6kyoOHOc^R83Z31OJ5olhJeYFZCNcJ(s8iQqR
zRNWOKOMV|FLS>atz;2i<^#JUK%j{|W8X@bFWAY+p4N?p{O7_BP@S<fR+Ly%0&gVlU
zR<^nXtvK29^r_!?neru|BtQhNCE8>q^z=!RebWnOvaE##yD2jEUoe;|oB9T=i!wHC
z?$TtR(^EcO_84WyGGx+K(94ubsH!YWmO|fZ$(FrKCN9YeXdjj%yGxPXT-nCcXywV)
z&^YsDSE#J2K=yMpNTJMTpmQEYvTd~7FP814fKQ2RJB8;<WwooIaarc~H$=*0Ik#b=
zTz1eNofWbJl*q1>ecS+rDp@q`d8%c)Oc=Z>3+cnpR3j_AgjTI=_bRmNWSJ7Q>SeX-
zF!}~rcMKeDl<l(7rPm~@WWjv1?CUwew8#Q!gWf8;N89E$*~34f(Jp(-50*M)C0ZzU
z%DUEI*j+MpIK1eVeNTt|dSua$0jyUhZ-HK)EQ|KC{jwEw-ey4NKzo)!*&RyQUz7bo
zC$ENNMa}g7yDmFJ1y#ec`4TWkWFksI-H^Fm1-U63pp$&JWM!-1+HKiSn_*&9_US1M
zW=!_fdzgzmG9|^b#$`41^tmhJeFlXI*($0bx+mKm3cHiCo>@rVmkq54?}2P7rEsTY
zE-zF3b6VC&tA~fOr*^@M8Cml05S^8Mk`I|V*}HA<>5%*|-c<|i<*oZbj>>PU(0NS$
zq%RCQ$PIfy9Odow1~@KHT8GvNc}51*o#Y=Uz+Y$ihGdYFa)l2>T;v~0&~lZ3gP@sh
z!72G^+Gn4ZchMfeO`dcXGVbzydoX)v<T<pg^N@Qzg~52rW%N4pl7Hj{k+bp<TJU<y
zyJ+X+BcFE_BEIrZsRq|i&MXJ<mwV7EI6$7Z6TEZsCuj+DUM?F0FHrtu6^QME{7qV_
z2FV={04-R)kY*@E&Rqx+D&J4xpD_7vRO}coFMS945%Lw3Baf6DMIcdf?OKp%d6O$F
z#mS#~9Vqegci)0Sf;|2;bSBE{==M*Ni|IoY$?{#Z5J{0wD&TgiO}_X~=wFl{qYpc$
z$+yx~mM*sh!>0`SFg^S-<*)3+%w);`*$k2`m(t8$lBZCuSB`x8Av$yA)egYUlLxIp
zXTH3XYFrBBA5*b#p?pOwM2h4W=_`N5@*kq`E0@TFSg=qkx2>dP*=4!tFq&87svS@)
zlmAu^jdJ-jbc<KWb$W<Y%0GA+CaUBD+C*2&x7!2es{HZa!K;xwxL`1~^1DIszD^z#
zfzEpQPxK6Ike{Y=myPo54d6A&=N*K4v)n{4rxy8Vw#%5BR{18%lC{ad>4x2QxnDPA
zI^?~PFwrUh=`_%~<To9m(Jg=PBS`khuV+D|SDt4^XP<mC?f?4aY$Z$#$k~*W9Fq5?
zLGrr%wi(kkET5kMlo5F>#rkf@_v{6^DR2JrjOf8yTYEM1#^pY5!unmgCJVd?dEyON
zzb9Wp6|s}@{Zz1aU#|Nbm=EO37DHr8zIzO0TK*0Tyod6j(?FS#|3W{=tbCCd%+ATb
zVnY3pLQG#6uvhp$i77m+I7qX6MDgKbOw3Wmm@Nc~#}q4Q(j62(Q-Q0aVq*iak1O`j
z^5leK$0F!EDblEL(^>Ho)xDfl46`w67sZ`=v|JUx(>nQ-;$2!fc`F*cVAn@6MIZ3<
zRg_UNjGy8Z?HBzOJ>SB$0L25U<U6NW{~qmu&nq6#gDp_u{4H7+6xXOeFi0`a4d#Ot
z-^<VnQMC0!BUIr_3%D@FB%LY<S8PkbC?XU!RCye!XqrZ6l%lQ?&O|F-q*ro`;_H1-
zh*cb+0BxLN(R1)HUNQa|NP<FofMQUIih}RaOi~D_<SJQljusCoiU)hpN>%(w6>b+5
zYiaGDrpTa7d%9vQ9wHeE#`_pdrowt0CbAUHr(q&n;Yv5$CB^zLVLnIkA%*2~6?rb`
z%u_5}fC1(!zKw@Mk>cSNssSoig!`hmMBzcJ=TgOky#T$e$l442D+=X7@X8diD!`O0
zVt0X8q4<K<mQ@Nq10vOmc|*{<stBcXwKWRm6_8p*8y$|UQ<UCEt6uRdRYx@_?obgx
zqhgvuD@}^|42;FrtSEZ}GA)W-wAyb~+=|9k-KO{}4a06%IQ;=$mtq$^db<^;H6XnT
z-+buzDRlIL?pO3rKx9A>O*#2N#V$Medrje<1(YGhG=-<HD;8M+HmnGx@|O`sOAK7Q
zp}0l^ylGP;`a|ZHqM9mQZYz@706MBzOV5ij#Wp%Sc}MX)UBTlD{tC42DtgZWZ9>sm
z1aeRDaw5p2;@SBycwf;%dz}XgGX-y_6xIPKOe+o-1M{JxgCZR>3gNqeo>lDOW7g&r
zwm&F5XRjQgQ2$}&&p{A9qU2Jn&q4WAFnEqi`^y;GapfjQcyU7cImK(7ltC6)a#lLN
z58|rqFNeY@WzS-WoK~j&A4JY5-=%T^59I?YCGb@4l%VCMY@wg<ta6|MlHN*z?PW}<
zk8%^8<MCDY)8*x-JV_-Z{>sk=AsV1u^Az;YDT^o&cV4-GVqbyEHg~ixC_kVIw;-j*
zBqW2Co8N|di1NE@AfZZjHAWbw+;ASeaAhjJpd*wG5`aZ2Cw~DiO8IOkt-+&}ZvV>?
zD=+*Ev{>cSRAnEh42yzm@yeW6;Y@-u`aQrTDtGA6nWS7zdD&!T-S=pvDF6LGv{IG#
z=*vwPl|z&%PgB-Z!qIf)iB^bYC@1uopiE^R#o@D*;}pEjRt`Qvd*EE9g@TKD%B{3;
z%vY{k3G)TY=+8h3mG$ofyGXe&5v^jSM<zf^ltaOAv{YF~MbVd)Zxle}it?jaSSnK%
z(Mz;k8L0=UP-b+3R4OlVpkAe%ONZTR<t_?cUsbxTr~kTGqg<oG&}x;dDJof~Ouq!s
zdSxRm-W!zv1VOP;>2)5h7G)q+KDH{|sj90@nN7=^cIATtkPc-fJ?=V{gH$)xr5vq;
ziEicUM<LmxjJ%Hl_A42W!ovY&=pjtPppxqf5!-F$p4Wjrs@z1;kTE58rntzJ{hJ^&
zp}hDkWbP>+-vZvG^0ii2y04t0x8MV%X&G7%m9Z4#m{AVVKewG#PSViqRd3PndRTSs
zMW7r}Ra55ps7f>ea!i%|4Zs{!-_%3$v`rQMI$+#XkLBY&a#t;05A$bK>@@i8p%Ui7
zlBenvrL(<MRw_|Bt4gBig13rAGwY+ue+rVms&j~^FYr@&(azRib%(aQ0jir_=sc%-
z>TehfR9We|xS&eBjNc$gH9+x;V3qAvTGxcAMz5h6s*0fJO@!(VPbfyJ*5`m1rCLkz
z<!IGMLvS=k^*hZ|tm@b@Sc+2}D8-oKRd3Td)CAStR462>BBW4HQZ1(4eX^?Zd9+eg
z|80aws_JiwCSFu!90V^-HU4ZboJv=5Hp6a~YNKb*{AIQu=0PD}_1|CUD^RVch;E_k
z%&!=Ak?JzVrHWOCO+YD8U7mzwsj7=Y$Cp*<Zt(1iYA2=p%T(XdQnp<6)bE(P3RUGc
zC{(J%4iKqQ`F#TDYSpoAP`|4B!h}|h>gxvZYE^98kI-*WeG>xGq4J>>b*C!xaSXRh
zwOa(VZk3Xj?meofsaU;N<wPg^`c*x<z#CBQX@lgTY9o1gO%=oh_K?c;U6AXlFX-Uf
zu*yKoixE}cF(}+rwNcprmTH$1{JpKJaiz5EsOn#uyfM{>sW5*>#i88xxN5ippm$Zn
zHn=vSayW(7Jyjl^a-LK*@5jtMP_gKU>y*ksZ-r?U`)}|bs)SUKH=`0#1>dad?7x7X
zQw{tBa!7sZKk)3;_4ye6VYSXc-!(a+Zukp|N7esOjp8wN>M#@?)XpOSbyO$+4)>3%
z*U@ElLOtXMNhftar6gR{RUg8O)9MYhB5+gJK7kRstKZ)X-Whcl?cO}p4UI79ss4eA
z6};7oE{w%T{W!f7ebrBMXj|Z?7Q6+fzuGk$iUI1gB9L?HA1Ro5Uj0)Ge(gXtm%i{8
zq^>-O@dm4Zy#<jFb(ufVLe=A2p&q6_`6kSVt2fQU?FjY2UYLkf?+gb@lscS_`9`Z-
zS3@C2edZCM#H!s*Ahvk*8G1A%s29-$C#qfPqiRX&N9l_W$?9j-Xr-#VkHFwX^|pF=
zk*2<p1+;Ya{S1g?s5elIE>m4Uh*p-`iws^;C(Q%NQJXq2Yq{!$RM?iM{)#@Hldt}Q
zs&xv~&(cD?(5C)b027zh8{ft}Us1c!QJXUL3QBX9tC#A5U7=n?PrEAh28uCMtL0QK
zdR5)r1YVswh7a|6wQC+sG^n4s0bZlpgZ5NS>LaDlYf(R11-q^4Kj;K<n|eC~D4puh
z)`Hiiwsl)Dm~QpI^PthAzC*#eUUgGGH2TyRUxh}$dgKp?4yu!UA$d*x>k=3oQeSHX
z@4EWEE_gAlR%T;nM%16=g4|I5bPt2Lsn+d>rCaL%DDgC=7BvI&j`}ziq>rm3lt8(w
zzGM3o*c0mE0Wj~Wn`l>aUtLb=tOx1_s#2Iz?|%~_)9Qbu=zOR?w-eZN>R(DAc}TNp
z6^OkijsiP}H9v^p{SnO@^pHNP3Gsw^2hE2sK*UkAIRNCi#`QKNPiV{(qHxj#M$q>{
zTr{uWfT*kHaw<%m(!3~xi>Eb)Y{<B2V(dWNHHFuqe@62LrN}%q`bLPH)r7~P(_0fr
zp%EX=Dca)rYLpal@YB3VU#|+#6rP5{InAbgkn<X6Uyuu$Jc{-NX<n$OC2_Du<BZ7<
z(Nuo{^P!r!X267L_P>T{i_rW|2aO^%3m3v*l%{bDI-@lvPl&{54q#2YAXZ};g28yr
ziZ@^|K{HMn{Y1?{T16&lI;c7+S+j|z>!N1!_n7rGO`ruR>6)H5sVp!<Q$#YEn$mZm
zpQXtryV;r@fpGDXrZp8LM>CJggK{;;hQZ6zcs_tL`5G>To(nV_T4oe#JgH2)NaL6a
zOU0UmE#Q@CCam}gOEurM0p*G&q!ezKX=>;PE!V8r1V?QZnh6TIRciFbfT_~>2ZLFy
zX{7wfRn5Ot@KvL!p9V~==AC$$uhYCqQP+CSlT-=YpxH@l@J7ug%1Sk9KKdK2X3dNg
z&a`N<Y2($ZS+)TvZJNCTm~Yo?`vjyzV^77hT{cZNJutd8#v+WqM>Dw`%w7$jvL=0+
zZhATOYfjW+^aGj()Pyb=)D&EU7uPf!w?KbLqj&)9>zc(>DmAPrqN9@|n%eVFxS_c;
zjFH{cv{$0@mgcYLL2hdrUIQ7`yo8+Gf;$@9$N&__HDA(8=B{Ry0nACwYm|VxubEFL
z5+7)uiUXO_{7WyHY0V$>cz&q4x&v;{Xd)<VIjdn(A<>-XIz3AcX_dRcv)B4tVE(YS
zBnS#ev`o73j%tq|hU78rmrtV8L3_YP6%dYEemu+{*RF8^^MtnSCHUr~edZn}!C5;_
zg;OWB;TE)9w0SvDbk+Vl1ng5<SK2C_)&{=^1vjmV;^*$#J+zuTqs=kEH4m*a5^j5H
z{~AKeOPkjOu(R5RjZpX2_9fEN$wzxO3{79{jvDCuY2B_s!(S`cU=jngk3ItIbJ}IJ
zT0gI4+=4=&cJMApuy$Ao??bfAcYz(M^?niFhiQE&1{AL4uLDYiHjAE2k=oLCL87$h
zo`m^m?a3arVzrC>Xh|HWy&r|%c<l+=NhE8(^nl$I?OWf&nN)2oB`q&%XYay`G;PjX
zFqp2jRe+bFy-mCPOfAzMXj$4FX)u_rHPhvBNn3!I+kzbJN890OuJ*6r!OPRm`Gc3Q
zZJ;Mhfi?`A6x)JA?c^^IEz%CW2U4v4x)df#w981NRNFfTjmugtT|!s1{VpJ7+AB99
zS+0GSuD}W{D-|M@+5=TksM5N{!?kMd%k(z9s@-VBtkr0*(T9*~wcEF&Ri{-=z^8hx
zssV1>8nofGHf_}Yb{M2d>q}ezX04b~11;KU2GCly)&R8Hv@h<3V!L*$8N=?-Ce!uY
zsl|~z+(+6rA9&HNH8Q~K(JuZFD7{)QO274K^B>}Z=+{=$p{W7w&4myd)cQUNy=yk@
z{ZG(4q<ta-&Fk8A?(lS2``kthW<<O1b%@^3{zOZWo7z{sFs57Dg|EWz+uH1vFgU7h
zyp7hFc1I;zceE3<gc;Wg>HT$AyKoTxPH1PAg51+K4Pt<k+IHGRPHC^v(Vl6oZOs9=
z_)uFw8@Cy4(OH<7)js_SK<BiP%K>^wCqIEsd))~-DR5X<vm72C(XFQ!?onL_J+6-F
z?CAuUgRbctxb3K0aTt=vb&=EPJfS;D*M*bL?;%>wx>p;Za8f6e0@_7)$2JJ+s{8Ld
zXq?h*pzo!g)?KKEi*C9X|AAe1-Q{99b4KU%GYop@J`BMKJ#|XTnR@At(%a>%?sHnZ
zd+WY^6l3zyNvX8USLgc*L;`eLDv$}(dC;d7FX&{nv<=d&jRSPBu40((zYyKGR2&tm
zYo*vqm~JgS{K9o=s<VmE9i`LNk-EDxa4kxgvllSYx^9ZG$LJoR<wC5kB^JCm-3N={
zXuQtrB-9ghapf?PsB@o&WRlLngh;aP2iiTR=q^!KH&vIWpt6XIx{xQ)o2L7ZuI_Z*
z?^MT_p^I&S-Ao;CCmhbwEu=kVwr+PTe7dBYp|p99Zg?g1a&?pC=*-hu=?F)@j=vP0
z1v-BZpcLwyFN0U4%jBW6Sht%Z&n3F=UxC}Dx*t(?Vq0(-a|xL%y6m^1U#6=Zffwbv
zU#K3pLdR8LOqDtZA81tRTxrWwts4=5T-BwT;aZI@jVeQHbw$5Ip-#6?1C)AQ{VPCe
z(A}V$qfwVj%l#(Z1s?R8b$`&=jTYUF0I1tqb#HHmr)|2honUtB+ULPwug;%BN_{%N
zqu}-Hy6HX|&`r|*Yf$&>BQSAI_dcx(hjdG27}|B6#}s(Ox=|4%M|G#;;O`w>Azk_7
zy6dA*xU1_<g2<%qsxvIy*9B6{_km5<Lko;4os7&+>$V<(%tM{yEwpBI*FC|T)mdqU
zJ*SJNhxQ@;DVh>{{Vh3KhxNZxaN>x5&s$J9s(+#%V>+g9N`)5=dPOaWqkf2rQI6~R
z3*hewy(4Wlob-Qfz{s5Swl$PoKB@nVig#S}pYI2@tNt97ww%&CQ;ErGy@G*GH+@Ve
zh`WC9E9jrm2T=mpLx21#Iz9D#+7Ef@Ll$AYXZ2|!sC(<HKY$4z{Wtv}zWVoQWPbV$
z+u@VHepf8)1?U&r=Ady-KiUXO=k*z*Pz=-$nE`r1pZq6Ckly?QI)n99|J!uv_o&bc
z)juAEDGk#HQUy`CKJ`&_M(7U+fgP!D`2Yir((m~SBwGL13ve_>uig(5tKYf?&cx}z
zrdvB+U%kZ!rxNu4c|bo=U;7?<lk^-~04D2SE`a$I{q9)sQuV&?fOk><X*zgmdiE&v
z()Hs;c#)xBkcC#JzU?baLY6-MTUg4`X9_`b^)A1Hm#6=l4U~NS4Jyzs(64jE=nM6;
zCu#jzr1zsubg_QjcaSO3FF%4&l<L<<L*}x+no=oO^uqfPDbp{Z<00jGfgVGv(AQEO
zex<%R4JNAea}-^x)~{R%^{aX&)fm?3>z{<dTD|dSxK^jnraV%;{@GWd(4c>Dh`wvt
zsBgRkm?phr14y&pqJzN}{R_t-)2iR(2beZ}X%Wn~>tlK$(xKnE8@x_^KmD7VF8#7X
zh;-}UQbD9gKh+Fguii}Ajy`?UMHuYYw|YYFn*Q*|aBWC`i_Blwf4c-c+pvCsl6fQg
z_n(8z4gEUGNZ!<^b^-L3zSabp+xqwd%*CjlQHj==KJquT?&u%2gXFmWJk`S7)fbwe
zKB1Q#0PmiDmI^#4^&R0rxv!t0?<GCZe@Ko_>H8@3Jgrx3g5*P+J}3^LGx{%k;Ki(7
zLA#te{ZU#IA2NJFl|c3e=6Q4;Hn_h6kt2pY`W(qoL*g?)J7#$HCSV*4`3K>JqrvAe
zI*%KIl0Z%v`gXyRli~TZP;fS+QMmS`VcZ@lE{3%fqI5MFHm*nWlwt4&44yWW&=EN|
z!}}B_a5so4Zga+PY8==ehA-~mhw(JH(McaKL&-fzdK+fWK;6gC`3^*U4X;bjURXN+
zdE58&Qa)!;e-6>}hU^H)1RA!#3vVtMeyBiakl{9^0fG%<G3X32d`<zeP(vc6mBI{0
zs(A=Ectrvw!tkODB9Vsjb3lnPs5Zk=tfA8j!;Uk!_`$<?L-unJNicji1I$Fjpe+l&
zB^h4$4$Wl4=bn&BF>E3IG{ehoP)s*G>W4YWFnCl#GTXqUZR90`dk$R7F+@`BYp&rJ
zx^(jl`*)+2Z*Zq+D=>Uc(bq!5^$hTe49gyaUa^70hDeFwm#;xe4ZhBF*6gxj$$T)c
z7;dkHXqkcU2fO8l4~Ic249yL&TWRp4C4H44H5sjHgLV@nuNtfipjTs9LT}SrLzfW>
zb%sES%+?!Bqi8i4eCal9G{jTltI6;W3zE$S?N0z}F=Tv8XU$p-2QNUT&9H4fNV{Rn
z9{AQ__>t;PIt`0PfYxPLOf??ehJ^Q_-(%P$1nD)%jsdjKP`nwl)^GUwTaW>RZXXl|
z4f`l@e9d5)LFbU+1`j{Qb;B)sV+|XUUqk1J;ZzO1RBsr5`x?!g22(hkx@9PvL+iHT
zbK1U+8qx(IV}`x-Ou1t?@gasiZn(A*l6MV<?J*Y<hP4#0x@Y)%D?}y@emh|IzM)<R
zy$6O)3JXpd?ooy2v|*<SyoZK21wffG1W+o`HfwOCK<k{ri;5)<8K3U~+7V;u6(}Ax
zz8eB^%($6y+YUyX7Lty}X(n37jsJARixb8QO3XMJ4Hq%p&PF?WmYp=Z(orfG<7eyO
zldEy;4qB&-Z*Ty1+PLHvP~40kQQ4Tg&G-mqmCqPgQ})EesCx-8o<<%WSobm>p+(+V
zV-h`nyp4kgAn9Y=;Ea~9F@PR^e#U@*(dln2c?^01#vQc5K4*N4?#A=RTSABg8lxzY
zdcnA7Cq#mb&r#`6uu=IV%!e3l8)Lx?HSQk-Xqd4m0bYa~f1<@pgfZ#?G$M@^RGb`R
z<hVm4*0_*fs&U2=3h%`muQ_586O0KP;Ao<e@jT2Y8GrCXE7`cX5Umtr?K3cV(YW~^
zbfy_KzrnS1W7!tyWf)U!AH!g#@mLE?WE&l3p>fH0@**^Hj7JJ#KG%533SOQuiZa&u
z#wc1x78&25OkuIn?;=1;jJqi_S!!J5jMio2399Y7VqE&ayU7^85^k3p-C6Lr!uZu!
z7+IxpyC>AEjP0v!Fj#F=(KG3)@jTrJHO3F8VWQUfb01*pjHfH1QEyyM>HY@e=-ZHN
zH2(4eTx&Ac3ZUL>oKK~<EyiWEu4*+JHbSJ$xaK36Xg7X!5nvt0$0)zkX?*lebaom4
znFMCHarJJx|9XsnuprZCTr(dq{l>6=L9Q7S0)RbatfQm+*Nso-L4VkIfOe`Q#wv<K
z-Y}-wVQ4pv?=45`mhp>r=-oC3&V$0Jv4%o$W5!qA;r1QluWbOEFbdNka?hAXrw}HM
z?{A@(>V4zfE6{&n+(VNvWz64?UuN3qV8C2FG~S>D|BUh5_n|mzl<tS4bH;~sZyqw~
zyFd<`o_huckC+Y?L*b}t$0S6KnX>ml!NHXICoDOds!zhgY12L-h?{9~2SnUWKmG&}
z+ZogOXc+V`b!Ec5r)kG?0QEMRDHZEu+S(6&U(@V9VEdW8#=-M9h3Fs|VB*i9b<Xrw
z0zl83GU+5&plKPU7B86Y)7wAD)Y*qtu&JgHC?Tet0APli{H~!h%w&E6lb2vKt-k~P
zL{r=}n#rb^P7Ef+^xLmMOErB&yXT9hPhW<mG}E$$AnB&s*MXg3y8aA6Gfh{oVH8=W
zJro$rHgW%e$R$%X)yd?TEKG>xnj{q7%QHDY2g!WXT?)n)nEv=*`od)6(LSTdRF#W4
zDK`1h>Z8Q8Zy#VvP47^>^<`5uWv8#05+lJYGaWew{c=-4FnATF)c;_&(sXGlu&YcT
zQ$n}eB&I$5RnvLOq12e3eHIpKO@Gfoq|Q``hwg%U(?k(?4W?~2N^&)t=94!~Cd(2q
zn@wkFd(&cCF^g8Ksc96VZKfpJD0iAtXg$|udZHGc-KP4T5a}_UJc~K(HLY=mYkj8j
zXF&Q*4s<wXz|{L6ydN};|BcRTrV)G0%#bOHw$#^6)u}f04x8q)Kt@bc{ph`6(oh-Y
zP1EC4xp>Qz91erGO^OLv8a2IAh1QtKe;EdP$JG1+uFi4O?}yNN*Cc6$`h;mZ40`uW
zR@&cBni_rv@4o59)$rnh>Cn?qm@*AiV7Sw!nuYY=T_2jp=+hE2rowq(&YB*jZRDIO
zQU}FDW_v2Svp1jr1tN#dhCd*3#QgSeuyoY?21UD%nU`50;$U7Sf`^XgQOc1ynO~{G
zAe_z3-SFb1S+yN{F6PImX5G~sN00tf=0(5IS+mn-bs!A7neS0F)!qCLWz5f*S5So4
z!~En%bb6X^Q}vpc`5j8boi!`yGhp84PrrmuKIQ;32IFhKnSxF~^J`QS=5H>c-#)+`
zMI|cd%wHpXyWqU}JIeG0nos>NM{R!fZ+Kw~GS9sZhl9=E$3QW}%o>75s5!S0V+u2m
zQN?k%`58M*cZAs^2qKZ@KPe~_W&Y-Ch(wzwD54f)evg9fvF2kzkc=~*SPn<y%?=j;
zonSsy0P~6FC6ug6G7G3mDA`;`3xpJ#nVSllY7U_w*hO;_Z3)uM%hrOVn?LSBXNFlp
zotfrsH=&<pUQA^J+2(+6;o2p$X%$3r%u8u|lWXp#^4dIeu?f!Pn+M2Xfq9IMCKQ@0
zX~A1$&Z9!>V)LJLFsj6C8?XZ{HS?EXOqb11P<_J{^Kc+U%gl-}pp~1m=wyC{Swm;9
zD$U>0^7*RyRf@gUncq186ZPh~XEELe^A%brG@9+Uz+jU(_X04R&8sJ1u*H1$YoN56
zFAbp8W?sA(7TV2^+9<N!VU8WaBzBrJZbGKZ{3$(5y3Ku5XV7DAr~0B^^ZMhE>@zDU
zRN8M|MS+0<bJljC4Vud+aC6Q4-z)H9$ov@9rC&Gy`#BVb&3zOw9Wl?*LhOcl8U0`I
zo8|^u*W5BMPp4S&ZL>S&Hb%`=AH&j^IprD1+%b2}pfzr8rN_=)^Ym5dPnfd`(7I=S
zGZ3vwb6E$l@0%y4f%d?B_(kxh%rDOZY}(Ac1d)g4_@`lE#@rtZ-mF>G423!K%d{sw
zWI1!2K7wv<d7tXF4_lJ;7}GJ!77CR*Sc2&*J&u-dwn5{#MR*mw6PD}%5GP9z3!N^O
z+FKBDwb&@uc*@dn13Y(&J6-Z;EcfVKvWMl7?U+$d%OBy8^s;14fp^w2lK`HtMe!}I
zKm9E4&Y|gVsc8XdfaS?g(K=^gQ1QWeOU(<w4zysQkJpOj04*njEFDx#9c(F~53_|>
z)>G^t)N=Vfh=f^sX^|Ih$;m@2!Xl#}f23ub0+Lad4-^=7v}K5%oiUa}D=<&CSWD&*
z^y4ho>De7`@hk*(g5}jNv=S{9bb2?*^7daK$rk%4D5h9uX?K)rd1N)NvWu1*X|R-L
zNusxCx`joPkYPD$fk>uh-oF6LvXoPlJloPu>%dEv%y^75$1=JEow+v4Av)8ZXW4Td
zB;V3^7No$kRsvFJsaXlTMV5Seq!n92JkVKUQD1>;rIv-m=)7$CY!!xf#qvrqu*)n1
zl)fytEcxH2-(o)s^OY7A)htz6T<LbGw!B(_)>TV&H%N`e_Bhq~)LPPm!K||k?171T
z%UW9WG+1t5#LyZo@&4#+vUFUBNVDasCh%G;t`s(IwQ%SPY_nXr3TN6a-gMu0ShgI5
z+ufE~S{3$Kf+#D{Ye}PTlJ!~YC=}gqxk-Dw0ZWgq2Ks}R#D$oQYnET=rx>#ACG6{#
z&#M44Y}ret#v_)W_d?@_W%CN4-Lx#;3$$C7w?cq++u}+Q?NQ4Cs$v_n98|!WJC?t)
zK*lXws7~jurINm*HDMW{^WXO@9Lmv6T8dZOpm^W%EiJ+ySdO`ZOj!<473j3(;7uq#
zv@B_d=#1q8F4hIJmW__!%~|Sc?Q_W5xd1-dTjxIxe-B%uQz3H1`b7*}J8FHGUJJ*p
zl|!)WU_JdAz#OgWE`S}kE{}$x6W050(fZTLx+w`vXY2k~!8~c*N^vq5tNKG&a<#4w
zhKW<wpD7W3+S*+MyKdIe0JPk#`sJ{6#(IRJPaf9qDF)_gEtx{6m-U4LNS?L6Nfo%>
zR>PNY#>ZMpy9HlsCe_OOS(neFZ~gdN=g~_wz<P2m44$*5^r3a$`XU?71X`cJh|UYv
zybz!TS?_xTCfFKB`M)sh`xMUzx5m>}KEmoizjn0MKMcGW>%;jVvDRJm3{0>N)0;if
zdVpdEN!Fs3=uEc8(?-*lVpY*2E!FxneLW`KI{zl7Cd2w3#q~0+aa7}#W!+4BfNbl~
zHt;T4hiL(rV?9q9zg+89M_}h!UzmktzV$ab+%B*lrfTLwtAR@2i>!+&>r-rvrG0LR
zb-V+-QmZ=!dN13oTMmMG#X3&af@Rh{m!My6y-n3<71k%{iz$`Xla%YOvhJ9G-__Oz
z3G80AZn=%o*H{-fp|jT7y9i#?S+{-<N9(Qr^a-j4>u(f8YqU;!L7~aovmd->>s3nC
zwOB_!f<mj+7E=din>B+xZMTNyK(WL6$PO?&t)J`x>9RJ{b=7T+4gs&vS`h^I`>n6g
zyK%spuoj?$*5@@K*Q{^(!0jRHYT6xLw?6$TI)|;L<kN^XhSGpHta+=@x@p}(-;TOv
zwb~wH*te}uX`nG`{iF=Ojai*NVE2yIlMdRBTfY}W^saS2?S&_-YlwHx8b%M@N$Z8*
z0easmpbX~&Ypo|Fr>vFX;7wbPd<W=<)`B}gnX#tm0X=KYrE)BLyYL=J9=2Q5MC;EZ
zc6+FZ&cV*skAXVcdC}?4<90^^p>e`)_XogsvfD=aduO}V6w5kkr>BLDi`_~p*>bf@
zrybBKyU07}JZ+al?=LsI4ODaJZs$#P+Gp&X>F|VyUBa6%<Z1VNEhN3{J~~WEjk9(K
zeg)IpZW}$qee5DW0r9mf8HB+Ay91OcJ!iMy8KCFwKBYRPK)bE9N4sFxNWsk@yQ-%#
z&|tf_KY>Ds-FI}PH`J~)79wGGgRfzL;dbvgz?lfU|H}kQq}}kl=!~+fSV#N6XglT^
zz{J=E(=s&HE@A^@;_T+f12o<aS2b=RyM0`Em}nPFv7IElN-9}NwtM^{U{dT@_7F+6
z`z!)_7wzy-1-y>za_>PT-OeWvof&q&QLS;N-F6D7XW6~88+zGxD;|Sc+a<eeUXaPL
z`=|vD=h`hmBx6CI-2n<P=i80DqO-v6Bt16@?T&u~m?FF6I~ZuOT^()wO6*oEV5!vZ
zMh;q+?S7{`_!YZfI)Ghfw_OL`|8sQZaaC1M+$Afmw9G8qG|Ox=wbHCCt;}q(owx7%
zzCSg~o`MS?$Sx?L2nYzMfGjGTBAW;Zs3`lc?1-|;_WRE7uldY5GvAqW-@WIaGc)JD
z5+^r`;+8q-vw>Oe#Qh8&RyeJtRqzdm(=Spe-gJun4km6n3C(D&bQ*Pr#%-rdFQM^{
z)2H-qta9?*guYs*GxWsOIhm-=sNQKS<x(4*T4@j7=+rp@^G!}~BtWv+>4je)(&F?B
z7bvYxLv)s}&8hMrE_1un19}~GIDNl?mUW#@XSYJ5$LSMyboM&^=mYb8PF*y$JaCGp
zfc!%z|Cd1qoXR&sa@Z*`37{iRf6fEUsMGeq^5v+I3)Vt?55tWKJ!eLt8_c^fK5wL(
zoADAYUk@<O?7<~*Wvp-qcaZUCKdgH&@|q#($$0K5Sny^9()!VdvET(*@MX9Tqc4E*
z;Y*M_%t)jNPava}rq`p4GdlDIGY)qFEQGPyu@Ce(V_!O2!x(qyW;wy|`w^m%j2>E9
zpJXIW0XvG(H5+c9VyG(NOe`Zv2olHmmWpl9Fy5Ge7iSqU^ht^Y#-Hxs&N2LL&`V})
zqNzKDp<V`s^NcT_MBfF*v{fJ%86Wmhh9r~W_W#W{L$Mbc*^I8^a3+V5LSLD?!gz|3
z^0|zB2CxelFH!`(knwmZoVm)_Pg$;FM)fkF++sYn1A3K=d|Ec&W_Z({<ql&F?Ov-G
z%jwi#EyMW_*sWu%p9`Pr8P9vt%d~+pmy#ik4BKj$Z(_)+K$;nT6ozSG+|k2QE2A+L
z`fUu$PME*TaO?$lkCFT-40bS_iokU;<{BZ{#qjwGcDos&6kzIMxE;i>`xqDJVG#Ej
z>!@a<pV4v&&<_|aY&0FS9x~#nN^yWOeK8b=84tuDBaHBVfQ~W>oS{F?_?|w<IKen6
zguzM1aau<1W-g<J&>rT^ci@vVb65@q7v>zg^Y${+zot8gxqx1n2bh;G!=NiOp9bj0
zY$Pyu<_8oBa~xzAPXp`0{3{3!dotg83;KtcTcmK<i}|cKh&MB9HN5a)=B$B;FEi(J
zfci0av7zVBM4=6CHl|A>TszFXe-?HFndihHK}-iFIFB&jUx>b=%)R>{8On^Kd*&GP
z&zmrR+`*ipghx1Y#{-y%V9usJKqRyBEqEHu^xFhWG0fM3pnr;4s|8v-v$P+5r<u=E
zp!N*&_9uWzWIp*l+)iS?K?~M%Oe^KlQkhF?p_j&-{2D0dnHOogNoO{upf7{@a~Kpd
znU3d6A#;h@PBl!InYv%$Ob)Z`KMXC8IrA8>^O*~2J}+Rp6hpF*`AiwSxXLV|?PC#h
zmJZHbW3mlED`vJ+oVbKp7z#_J%ojd@$aSXv8-SHDPy7WhDwxY@4}6399en}dCX?-;
zs)t)l&TNoMCdUb)x0#!jP`tzZZZAZunL>&x)-bE4L%)_eOs|YO<`c(Zx1O0z5xfTG
zeX4tFWNxJlWfODl1~}8q)SrWi7UuIUP-ta#A4g*wQ|<}U&YVW!_ztG-FDgInWQNdL
z=^o}rS}*r9->27pA9H9BjrW=30$}$uXX4E>>j85&RU|!RZg~?T1I(BacrnO)c?%kc
zn7gP#XPEi<T96UuOWQ$4nS83Ad&KlpgBxQ$_89DrGe4dLnPC2Sl3u2h%pS^@PBFPu
z#j~6Bf&in~!y2grab`u)1m(hdbuRk$vR<fz-F>WkR9&*4HERy~4zPZk2Q*jK<MjKu
zu^#Y2+*zCrkUYq`?h6zT)*=hM@MP6~3CTmO>oYMHFII;4EIfbStR+-o;KTZ19*8gN
zuX=#`vF6r5#-F9mghl{s*9wrstliOo31sC{kz^1nXdEI(SSuIeA{=Gq#=~wfYmB0M
zA*>>*jSgk)IEpKCjP(Si*pIUc=(!DJz54&Jim=}O5rc4qv+Op2MzB(8FB{3)n+S(b
zvO-RQi(;+N!bCKy<V~1}VGU7O{uJxqpYg-SvW8eN7{^*mJD7OZa19zyv-GQ=euj0N
z&P<+Vz4Shy6Ies^W=~|TSp}3N)|2!CImcQ<d#q#!tJobdX{>5`yPRh|whiP0YdzKD
zUu3;WlWsc8GXw5tu!70aOjgt5z|LYlM$58nR>5YB=@LtN1(KIp(KMguuySaFdxiA^
zZJu*k3ui$jj}?>#lzi6ueyA6)cBH_3A<OXrMS-rec1@wPh?PLqKi61E^dcx`8UKW6
z32RppNGa>rGBjRi>3FbP##+MxXgO=23lu6?VfZO$-C()=grVJJZKsXbEmpt{G*+_2
zn=ty@tXX5|yTfYv3Z#k^M%SsD^@d|P&}vwRDY{?F`q&Ojb*wG!@TrkiWrR!<>-RMf
zX=d%DWA81jx5pvU%KA41CfZmr7twf^RXqyOdo24~kZflq&Ou)XYnKZoJ6XaIG<LD>
z(#_q?Dxg$(59<n@V(4W}WKc4(kM$pASnjh9u7nr;tUOnUK44}40ly!zzNCYc1FS!i
zF#16j%NMQ<v9`ECVVITG1P@18D?7oBvgT6q^bsqR3S7rn5n5OpXQ`Obn_zi-0nABO
z^J0)G)`Bw-+0ABerV8;r>~bHt@64{Gov{o1+h3uvmwlGXboa4Gk#U%{pDk&@C=Rgm
z=pc+M`)!KQy0Q1tB<9ZkMFRDM?D#^cd$1qB00mEW^<h{##13o+iWfU;0~)>APCsF|
zKI}M3NBgpUdMKFV$F^+5nEcr(XCM>6mV5}%!|X4=gnl49lQy_P?Bl0#Wsb0eKgYE=
z$`<qCVKDnrFhoMw{cbQ3%Km_|rpMU96wEo!HdCc&7<*qF^iHs|jKB<M5B&x%f_?RS
zh(xkyKL+AB$reyyQWRTxA866+w5I?Q%br2uxj6RPwP=iI@2AgGon^l`8^caud#!}O
ziR=$XK+dzDJqeL?b`J$SGuW+9qcM~1eF-Fsy@Vps+3eugK`ybo-v#DncH>fz9QNcg
zkSh-MPuBsO$L_(m*k<Lkr(c7M1?+*-&@W{FJB7Zh?8r7;uOjxuPvDB#MZ=IRVF%OU
zf>L%-A<SQAM>n9ajLnLH_vP$B%Jx*ScTh6p2K({780by*ehd0;vCB8XLM7X8FBERG
z9os1LeTN;m3<j&%?el?F%~pD%vxXh}2TatmM+)G69s3wnao4kN^@D3*chPOx$aaqa
zXcN0C5gs<PSM-3iu)8T^-pb~jfu%O~Sz0>XW%s#&yT=|q0ljv19u-A*u%C4N3bva)
zFaXdV_7_nQ?PV9-2I*rjjDl<T+51y~*3TZF1owcQLiw<V?6njg7+^=P!4Esgo?nK>
zA$HYY5E*7CJOQ6Z*w;S<H_EP{D*Z?7iB(V-V;i1D<2bvb3yl-(B2SvHCfTnY0GVRP
zlKyUvcnb`=aDJi;$6k)N5+?R>UZS`7e$Knkpzi?ZYf4tRati2W?#4My6P!C|l&atk
za-N~}m<MNwk|>@W7s@~#;wV0Yo)>43>UF$1sr^v!;W!pjGQ*b>F#<(D&Qt+J{W)n=
z_8P$Xk@o(FIX}?D5y<J3Krx7OV=W9G;jn36a+GuR7(jzL#jDX5!ttezNGPX+g7jgW
zFR7;O1jmzJAmN<My8t`MIlUbuiqlGeq7u#7nMBWDEa&SO$i#7ULMX;_-t7SPSq|$K
z8WTAGWPnTLw9tDjnN#S2+arY&LhI#JPV*29p65Jx5|%D-w#<e4Mb4YQ!bCdfFl`eu
zIIBJbN*1SQ3Hq`*t?}S4ae}B&HHWjl9_ov)aK3&Qpt+o#^!w&<xKsv{&snz`1`9c^
zft{aBf5q_;YWZfBa@e%Syv|v%75ZhI#~R>T1?Q7NICFz@mGX@@IiJ=*?-r*t3|uA0
zivqm2InR8H#%fLv1(s_#&)MNcE$7<`h}3ZkZopnWM^2lS297IjJsLUH7x05Lac(Za
zSeiKz4w}0=IrpE0Mi=LFAxJmp2;~TRIJYVJ(#ruR?p4mv<8ZB?Q~D~n2b`p2T!aD6
zOa4$F=4_$0)(9t>-om4tGzuj@;{0<FePf(&lF>KLDT{%l6P%hUaFd)VdV5cC>OZH9
z_ipYcy07+dc?+Q7%q{;D+<xvRdL13$W_*Q4S8fa45N_Oq6m@dvzIll5N3Mhtlpb7e
zAMAQ^*%S{y#MPXF_kP@@*FpTb-z~yG1Gtrw06WZGjV1l8KyF4gFoU@33TNXcJ;ME%
z_7F$8uTr`+nA=QS#4xUmRx2mCKYaue&h5{D-3YETExjVSFI@xnN$zHPMxwY2=>x3M
zT!9QEhWmCihIX18Nm-LK+|MaXbe21fYMv6fRiD9pBKICGMw7UyI4OsJx8dd&Krxy7
zQ!_wQxTfhac%GX+3)mO9`{#jN<hq_iUphDbBfw;EH@^p%Ozwpr(3r)o+Xs<st}p@y
zFL4zO0K3d>p%RE3?hmh`?+Vv3h{i&$ih{paxu4Njyo$I1v2e|Cjr$4(>x#K+X_HmL
z-9eL3DR(|q9bD&r{v<%lxJAW4yTxsJ3uu+xCn;WZo4b;he0R8W>7-p1_pJ_qR&#%D
zfQL0)9_1TrxvS{0uj7VM9;}%wrCnJI_XM4UY~|YNxJR3VyRiuLF4yB{kbB&>tKdaD
z_YXcu2REOR<DJ|YBS7opMpNT`?maWOe(tdou=IetpF(dBxpRl%_5in^j_?n15Bvnl
zA@19>c^>8-^MJue+>hwXEMr{1c=$BVO`&}51lM8s2xybsCnyv)#qG@p+HT$%3P<kY
zb<vv1nb$ZEA}+jGF0l9VBK`r{$BU(MJ9pmo2yh2^yXv6l!IRNu(vw$BQNcqzmmV1O
z;<ZzOk2i133;z1>l4@}+e0h<d!d@Wn4aXS_JBa5_^VAXE>S&-H<?(`{5zHH-P*w=<
zIf^rd^4=9d{}}I$Ut!`nZ_Sq&MI?_!x86zKe{}0b@ix<~7tL#+m|G05yAkTAc#GvA
zvAm4iK#Ak6`2T17csH8>mdM+pa=?uw-WwG3I>&42LTfT_X*IA@c&|T#rBvSKWl&7x
zF?fJE&*QiO`vNb4V)Plj!FZ@=^3HaF%i=AfMRYcA#$6~};{9<9>X&)%xdJSQca~1v
zUE$4m10<Ix%EEB-c(dN6f7i(8{Yxid3V2mNz<e?9Lkdfj@J?0&rj+M;6&L6_PbGw<
zGM<3e5aqlfO6XSb-sHo?4PO6wfZpN#MQ^$)-eU(KQqB91LKZc=3_4L#%X@DN!0LDl
z9-^<FH@pIR4LlEI;qi5UUQ!US+j#zVwBF^N45u5Bcj+CFcHX8$fOhZ}({iJe_v;nt
zckvef2y&m-PE{fOynA%7Kj8gMCp#YUzM#Cp0MC;NyMw%3XLvEh`;3+g!@LrjHXiY=
z(VRWTt6Kr$80Y;#fs6@WA;s(_c^AIHMVR9KNIS&?e2;xF;mThW3w<~K<!+d8=l@{^
zImo|p2l^iTKqW*x`8!Rpdx-x|H6*?Gu_u7(%@3iE9Qg24djRIkUrQyAe*Cx2!8Lz=
z7CprQ4t{trU;_EhK>!Wn_tPfn2!D(syGQxHwD%9@H`6U2%6~+K#K-s*R7ZK7@BKI=
zPw)rM116mRu@s;Y{68r&8_BPxP0mUFy(d9p_!nLT^eO%iZRm^T-=P<L9RCp&C&%+0
zHS|5l)BL|_k#>e(*$lL^{8f4=Ch%7+#we2b?X);N$7kC?lKIVVK{18@W*A5+|J(OK
z()fMd7{mpB991q~<loXjJ)Lj*8_*eis{+uO{H6`K2w8mnm$=N?{E{O0bcw&(QHjpW
zd^4@ta`<ci#>KzFPy8Hcx%?YcfR)GR(*2yzf0?#{1^lygR<4l$DMeAQ^7%<nFXF2x
z0Dp}?SPPM2{^BHvl<>b=3GYk!9<;8x&i@S?`&niDm+5D^!4IND)J=Z>IR_MP@eNe{
zQ_1h7JNP#LW6C+*;a5I|QB?C!oJU^`U)zR(*7DyU0jc9}eHnW7e9_w=4g4?_K%4j<
z(ax!v@AfuCTKHb|;M(}HhX8h$zmzg=_xJ_J;7mI|ya~`9{M1<bx=ttmXD^JRi(g0|
zFYMv(d<>nve79Q|Odo#>O<VW*ztFtVj|&8mhkRoaU<UZFJr6R-@1#Y*5dWR|FgVQr
zlum$-@VWDG5ytqRzXH8+e(g5sP4HtWb2Z7|Ne5V`_;MHevc+z}Qy+reBUrl+o;nM5
z?uLeoU>e1V_X>*WjkizW9E8680#+{i4hZ;E+U+VhLKojn@F_(O-31PcsU8$ue;S;J
z;P>^oGM<9R??La7AgT;tUIGuwBYO*a{Nc8b;J4Kv4qw4B31IvL&)VRyzo4cDCISSB
z-^0XV!R9c41`1jhp)p9%EyM_q2>89gJ}Qu21PK<HXF@VW@X!R5P=Wn(kYj?K2cdUd
z@R<}MVS*<<#w9r+$oGJSaDke#aS?)z^j3;=2m<J4Jt_EOGdztF42%OUTJZDN5RDZC
z&xd}TpqJjl@q%@K0sFL|#RJ%91oJ44aaQm+rCSmNCEsB%iGs%{MxP{D^8!%L3DQQP
zmn<0B0?8D?>`wHh3Qkh~J5AtA5%lu{#|M-@zaZGD!DYKBNNfaJy5PA_p_n1K-VB&b
zLD8S+%M$!eG0JSg?Le5nB$%R8SC<7#XeW{*STYH{D}wAXNahMG6lBN~oQa2IzTglQ
zc@zlRzkx`hVE&8n;;O)p7I#I0PaQOsUK9L56MC^AYB^*|1gT45zD!WK0;F89@&mYE
zA=oe*A~ys<&w$(%IBkaHEkSW6NTpyArBZJTTxwzIj$j96FRBE8PQi<6!QFZI(P{*K
zZs@BO48H({I>8N^^6LdIH4Zr3Ake;o!88g|>Al+|nD-_0n+2cJSHxNbOX&A$6%+-+
z?>2$PhQ_;sKW9Mlo?s#seVu}u6mVUFI4X_l7R-MWB0Yk{9l-1r_|fa=zF;*iH~Iyt
zQ8@EJ@X0^m9txx*RB<vO2x<fNpkV15zzhrK^gw?^FfjrBQ9;yQT!cr0n-pvq6L8h=
zdt4ClDnup)i@eY`C1|Bk@^0bQgCNerEQ)cs2tB?8w^#TfO=bIpmwX|)U$~w^hOWZ%
zSs-r0iPYKC9-HMZ{4CJ)HPSV#IB0kY_fsO-Tln8{nD7y%JdH+Q;qFlk%}?k`H<Z6{
zFB@YzEKH)9P@ph&I{JcyejIooBK-F=V227Htw-ZAp-%*yIWBBo2@)oJNarQOg^#Xd
z^bx{;YXKc8oK^s^lR_6qJ;oa)94bL;v@nxuJ7a`7^g4<azDsZ6IAL5GVB&=z4nhC4
z&~pgC-5KFPF!U3I51xd2qA-@0ib=v63~kmq;g`QaAz8RUh>MUS{5c$YslurZ(7PZ^
z@&x8Z;Q(b~(}fRfX$zAfT>KUkGli0JaM{A&zr<iJ2^;C8#ATs~e$gCZ%n}&9BJ8Fh
zW3I3;9ew%2CG>0-2w$P+woo{64%}7YVoKH)35OQK;5DIC0re8$9x6&H6$Vf}{&is#
z%{t}6Wgk(xrb2jT6rSD?${R84o5Fu6NO4QZr&^rb!Y|H&+!0P|16q|(L8MwZOyRW}
z;WWDVwL$^aEY%BtF9mjk(56OTqi`d|x0-}vntPjtEGi#s5tdBCP@C}gXQ6OccxfqZ
zm+uKXDd^TEJn{t;yM-0^q1YolLkq}WVKkiu=@arPnA0yTx(KufLdo;s9t!;!AOpf@
z|AkM3!lh<#L&73js|^buqeb+n@cJ7V=p*5@_u$%?u;O))abW_*FDHc37$`WVggA(Y
z8(CC+2QKar&0Pa8oJEJJtiwe#eh8!AE1F3o+$WMylGs)B(=nKE6YcSXh`Z=BT3H+v
zxvc{65Vg`K*i)3z4Ut2ls0|=qqV%UQ2yc;`a`HZ+R*J3oio`S(`Z+`^YJlx8dMpp3
z0iunxG(If)wh+DrieBx3YeAxgjj($}^fZ+j9Tjb^z<7g2|Gol)AtLovaG|0CJ;roQ
z)c7Jy92dndheDXhyc>NdL{C%Ae7GovUbGRS5h{d=6m^vV`lQHFLu;-m(O*=*5-s}v
z1(=8taRksfC8~K7p2mvSQZ_tJ^dTMjju*W^5BzCSo-4RBq9R&6oE0smjCF!&+CAtc
ziuQgDg(T4fDuy{Hvd|%_WYJj)Or?qb^M%5B(HlQO@`C7b2bJk&i0<8kex}GuzhRcB
zkn$y$MfyBkiyV=KO0KSm!f6$qFRG_yXo2Wa6F>_^J&{njCTgIACB>q9bn3B0lu1k6
zGSU5yz?F-}MNqF0{d5*r=9Z`=3MiGL#q?IWEvm%dRp5RWeeVL98qtmgAhn|ZK7vex
zsOT*88%16eIB60sp`>lI=$9e*+agMs27|4lWwfko6Q$B#_O7V+4Gis`C^;7>?V?;-
zdUc50QXtYLs*Qrb-J-$|!1ah8a{^eeXd0hp;y#gr-V*(ydG!6U2clPJV1y4vPt%=0
zAUggjKnF#oU2tYdq>-R+ShV^FppA(B`VNhwqHib)^hh*eg26G-$MnOFi(Xm`OB149
ze!!d*Eh&ZMl&D{ezTM&{tT4YvtoWE}Z=J=#cObJ*eANdA_lwux!{`r)M_NH##T8Vg
z=q8R6fO8k886bI3oRtJg53$+`v_oPJEz7*bA5kdGTYQ@hOFrU|S?Kc>@1>{MPaO3e
zMEu1G*FXZqbDMz@B$l<J&v8V2nbt5z#oH^P5h~tDFQ8-MZ@<Q1j*ClTK*Gd>{^&a)
z9;dq`LTns^`AG3URHlAX{P(};ixLN{LtnJ`;1BR3M!Yiw+$phYB`#O2xPi9Wabh#g
z;PK)+G&7}$-=SGL)geCoA3D>->p5sWFTP5V{|jQ?w}81Qp5nn$x_JGwu#_S8q|HO7
z*mD-REb$uJx@3#{*dUk0Z&J<RW%0;rkQ{O66x_ZdUQe@at~iLQ<nzS;xxswCSkHz?
zf%puqR13w9m9!?fD*mPo-V}*z593a_CVsCMCW^(n2hb=H^M6KTsaQ?bM%Tp$!y#EF
z{<Q>+<zf|;N>+#isG{$d_}VM5R4JaK3F@}kdLNC|;%Ewo)QG)Yp-?Lhzl6p*@ia=&
z)r$ihRBhBC-Z&kWn#Ipid0~rKxB$a$73b5^txddQ0HSxrVMn2VPy8xfi+1s@nE>q&
zcjkd~im%b8qf0#hYjEA-EmVTkBVM%z7ok_Yk5ZF;;s<p=xi2335t994G3`koh$oIx
zy5^zywSU15h+PsPGbpaAfHOnlfq3){i#sT{I3j+BuGgs8y#%0-#2LLHW8wv3V2_I*
zP;PKSoJ&cgNpZt+jBrYPKniZRBwGyiJrZRZ+;*0nqDRa{@*YjEdnGff==s|x>7>NP
ze#sBTuzNs~@&mkZm7Jr8%T4n8r?BfTIami12PLl@LZgSIuN;k@l6|zIIV1_B-G-0k
zdv}2PO8!$r#7|N|p)7w%KUKR2NG4Oj9hQ8e0Cb?l&<DLBNe5;f$E+igAQRZ5l4o5Z
z8Z7xN7!HR>o};pxP)YhaC?1ovpMd$}5*wut!z9b8qUeO=M|x3*OICWre1zodd`L!0
zehLQ4Ny*OFp&l*Sa{xZYNahtm{gh;V2}EKg^L9ZmPV$i+*U)iV5-=SG&q(}opmA1m
zlD6wfl66#Fa!%4nb6K+FN%}=oB)xWUsgk=27)+DQqRiQONg}<YE=VK_fL@d&=Rz-C
zGK=Pm49PoONM=gbQG6^*^4rsp%$CR~x_(I_z60}@9g-~+V$G3!PxVw+B(qz=<w}~5
zV1#*+s4O^>FPY{7QXu(}Ui*cTatcXZmGmS*vPg1O1IcR=UpnVsENM)JNQtC87bZ$2
zyL@5yy2OiiRb`U-bY`qvva}Hj6_Rl(th*s`EV>2Jo04a%(RoW!=MC<TWOf3ut0bA<
zK(t!&Hbrx4Bnz|ASSz_leRYxu3bWNqKB5V|K{D|U8XF~>XnoQonfC|^&5~YPHMC0p
zeGDUOle|e)G<PMlqtMqY$<7AplgxFTf!+I(msQa3m*}#<J&-&{1x61gz9c#z`MewB
z9hBU=474H1Q|m#7B`^Pfoi2&dqVJK!>o3?HlYDal&WuZr|Aod0iRlU&CnYs>JabAC
zScJws(jBzdah8TseAz`RnRI~NFSXDCo&!=f9qe+I*4Ke^lg2*-&Ru%oPmqJs=WF4b
zhxFN{;5?;Tx>*iM*|Z7vl73DBaUbbUE6n>!$HE}uCw;sEgYcJD@4<BrkiM4yLx-iO
z(|{5vO@9{_j!2J1()#nLbT8e(!P3v_p%@~KQNr&~X(z?9j!PF%IZBvx3w=i=TzY6L
zL?Wcq{c$ZLr9D)f94);`-}{V_&T2s4DXAMpCz7Of$6@K5^gDm(B}@OD3olZnZuF*1
zmAX!c+iB93m{%RME=p%nt{`2yo?>7b(!!^pm?{0C8s@X4<3>1>E$yQ~;3erZ-@)Kz
z>3IrT=SbJKLhp){OKbUD=_fU?n<tH=+KB?`;2bCvN;@d}dsVuj7+jI`=6mqsn)LH9
zNR~=lD1YF%E;ZBgw@ey$8f>|A(HB6gkUI54@rLx7CU|jEI_(HVZb`RqfMTU|H!Xo~
zORdiE_l`7<A{SNC!;v7>(l*LT)<}O?3iVp)>{@tOCuLrRUcEH_Ly!jPQrfIEN>7BM
zugM`j{wCOF>2NeGwMf69wPLF@pb7eI(r!u!-<6I|!l!#u*?eHPOJf&9q(gd?`Z}d;
zPs6n?=^r$0bW79n!SzV_v?TA9E^a|%pY+8<koyQ+z<j^7Ivpqvqzp>-K9oAt?XWZ;
zeReN22Bqh^ATuQO$U*0@)WihZh_rwLMWa&BeuzAhPH}-YChd^prx=&A=E3a=>9bTE
zIVp{xZNikas{kJEmi>7iea<p}iregyxqgSf{jxq<SR9b0P}tQ~mgAr(pPTIBE}*%~
z`~o3!P<Ff=8XmIs#c<72rm2DXL$W!3K=YDm>6<j(GL;E^KC;QDKzwEMDVgXed-5fK
z2Fre+pD9FknW~CIWoh4{@0cu?${~--9{Hd#Om=J&F2V_!%1X~)xa`yv1{xu2x&tm!
z_S-VZoRk&NY9~te7(M>cvI<HH#>jftpzoAy!|(7nR`wn3*y3caJ0KD-`<x=fr)9ac
zradFer{bZrGFCby6J*z?U_Mcn5d}j@vOIV6os(6pp-6bLY~mldm?CqdSu<6}qhro#
zvJE?6@VxBzcfehc?V(WTMVW=-)9JFAR6LX+bJhVSQ}!>-;90VN#(<qI`%wwWOR`D|
zg<Y1lPytqs%!%?PS7a+`e~>GCftFQyvd06a;rYv#t)k#rp={PTu&>I7>Gmp;tzHhh
z*JK?tpja$hx(*s8GTzr1MX4<D1vFllU8aJJGFb)9Oy#m&v?i{Q{X<E;8?wl!p?*`w
zpm@Y>*{5%#?~d$_4?L`rEqD$Vs%7sg(dVd<2?IfEW%?#KTqmoetzy0G423)zWUo*e
zXrt_%3iLI}YKPI-EZal@@fO*659qbZ7SL9pO_p;2_sm^cIqiAw$!1WTs$KT_E{Jr<
zHqVFKow7b!AauzJK0#l%%x5!5k3&{OQP^JDPxN;LeX`XQ{k<>Ss0G(A8<l{2AY0l9
zyANfj=#d$awJFdyC~Kn=FhjEcJ_i|=Wqk+95m`5_+(u<m3THf$P5cZpCYwV=lH;<{
z33xFf8@&gVN!b=E@|}`7*4{+tZuw_)y<FtaQpw0(`8+!0wog8Ts#09#5~}5KlZ%eS
zlDmBK3@CcampOqPl7Ha|@4e)Ieg_e6Ibv6MD&)S;!Wm!rXB~j{lRy1EIDh%q8jt|_
zPFjy0mY30TFi<|t@gCS9x#@F=9+9W_gB+C~pj<()d<9MRA@a9UfgLK}N=y1<a_%?`
z9+!VeLBcTknwbDSA+MkmZn%6p#fu{3(e&brls`Eg<fOccQkqfnIXM_ow0vO(Fk|FB
zblf6N{{1?NgvZOTQYibhyp?9X1o;<q0yI&6gjR(~awY})&dJNN!6nPhzW_8vUN#qv
zsdD)OIGQGxzJ$i}@_Bw}ydd8u0@y|Q%#Q$_E<axg%nbRl_rYb#pZEhLOTI7wUS!MH
zTIqu#m*gIle!MK-sDj-b`KD`txgvj|9oV_@1z~VMPac_vzI?ec1&syrl@w4Yl>fRI
zKjl?<>;|9}$(K;%@tQnj4@j}xi)Q%}`9hkfO6ALAV7FY(p?z3|+?j{Q8}i=kl!>}2
z|8XYtZ^_#iqO(%op@WGkxl<rUQ7ykhncy0EPAa$#`D-5VqEl|&3iDm^kugYi%cs%n
ztVjM;GA=@|oJ%XPK6%<UG~SobPJmv&yzO^bcp(3W+<qumQ-RKayqE%cjzPJv7fcMv
zJHsJ5EWdpd?vKc~lHa59o3vSaB+sJCkumw)OBmC*d<DG-Cgk<e(A%vDrux7=3Vj^x
zIxB9{=@=IU|1cW&D%QAx>{En{LSetcsDj7=#q*R0a8+n1%I4-!sNMnVuGm-z-wrAg
znxWyLaH8)_c`AOPRL~)Xn6@WgifY=Cdn*KVOwvce?1rPhin@8g_ESvofa0&%N86hK
zMP(Vd!-^VuZ~_%iOh6$>A)$oD5ydalVBx4@Jq53V6^;lVU_ulhd4Ua8xLgKzOd;`r
z;&H|MG*5;pvY7xqq4<dwdEp9wx}hQzGiak5smT2USM8*tjh>$<#mDqki&jk1S2JQ1
zf6zwelwyB7?8Yj7p9$zV#i<!kk5^REI{maF$3dZ*Gm2)KKF%ttGe8m)HMDU|R6Iek
z?<B?Pr$Nps29nU1tWa!#qbZ6Hj>CMaBKvEgr76lNv2<Q>Z#67kPz>h)`=Vl7Fi5(h
zY9H)oD5~h=y_t%*ub`f#sPTkCwjwuzBH@=5iw>jpvSQ{Z0L@V_c7R+_yjc&DtLUYz
zZJwh2Fh-cK=%7E!EKn?^nY>U@9s-!Fij`DrT%@>9MHkl;v(wO6tk_SNyF{^>!rNtv
z!~k&Rig8NbR4D$g0@w`&YX+6;-Bdh9Q}Hdu?;m0?m5M*9Xz;e;8xM^4jv|VxIja=U
zQ*l_ef<rm>8pXc}XslHnptV|^;?!Tb&h?7)P3UV<7>3c;taz~pj<zVGp9NT}VpR|N
z+7yZN;r3lc_*!rsirR$~f9X_Ad<p$7MJ(<AdKHnhx9n3yP^9O+f=h+O4;Au4I5VK=
zqfOzUBHRRLh7^)E_&cmP^*;JW6#Eu{8&zDQ+LlL(3-p)4V+su|yT=vE3^YzCs-J^v
zlZpdTP?%DPo&lI+w=$W&NU%q#q>Y8M@@EPtxG2A%gC%>FDVy=b98l&o0NYjhQ3@2@
zlqQ;xJ(Rvwcj~D;META`${9aG-AgH^$^viYNGue5lzt5`=&NL2f+as?5T$GUmECk;
zJwUmb3-!Ye<r^h15vcr<Qf@&?=2CPXQN~vR^r&*Y4qUL(v>ZN#D4QMvJ5<T0&ys{G
zwN5Z`LaCuxR=85F0QO1c8VZv|DgT}Y60H=^L0^n={SLTxO1a_*aIwn78{p!UL-fg!
zc%{SZcUU^D{L2|*I-~rRzT<pW`KKLRg0h9G9uk$o>tQKL86ASgbIP}AE=pF;d;um>
zlqEIrDODLA0}n4KU1*<uQ5p9=#+$C3OH1k;<>TLBWLK1f6eY-2J~#<4@|2Dz(3r0b
zchEwiKsi|f#X{vCDGXj!?q3PTBIVXqaORq_jFMKx%7I?=l_&=ffRrj{ib1X`SJ3;b
zOu6P0m@ilUeh%0b%F`!6ZYckuvc^i~ttnit+sX~Jsk@^*osPyT<;V1<tX97GKE+>Z
zl&@8Q)G8M}1*htie^P9=Ug_iw^G!<M3Xo=HHLa3bl(D4Hs?4Kwc$@Oag}}b6jH6nF
zd&=c>f!dX?#enNjzVjF)yOmpw(Cbk?^9RP+t6ZE6NBfj^3Sr+@y1h=%U%&Dq3#|{7
zR}}E=p^{qyg9FNUX#qK`Ttthe5oP2@Afw6-n#&$3?>z$An37LV`nWRl0@Npz^Qf|J
zQkh9dRi~6pN*_9_QmMw-MdeO~s(V$w9k>VwRNtu4=c>8|4;{1IRICCR^iXXchNqsY
zUV79HsSb0%`KUJS0q3jwxE*8iQ`J!N^{{H=<LC=i{YIZt2~xQnhI+6nf_6C}D&J?}
zTByorKMY2y{uMysr0TyMphT(Wrhto9Rc?n!j7pUNe;ub(N!>t;Rk3w&DozzR8=~>5
zH#5+9TGdJ!hchY_1)<KWSg%7QK{fjmh$O1AsDvU(<<bfB=TwGVm`_&mDPWVLdgfE;
zrK*0WfK8ez{zDi%uezBI^A}V*e9(7M^?(P3bcd>52G9)E%GbbVsva(eMwZIp2KTd7
zhlyNLN#23RW!3mGIDAD_7Y;60)jkM?JeBrIc#*H#_B4DdP#I~qEL5$ggz!}rYXIs+
zDm|qUuBmppU=YQseH2G5Q4Q~hda26s>TB@ry6Wl@w3ey9-vjJ&RXcq$vqJTi1{yb1
zd@B37sVaBC{B2d*4K&_SO{XwfmCC~z{?@8e=~!Bw>J5t0)vHdEWRvO)t*o0>69edL
zQE`jGwW<O>0oSJL^a9FV)$@)OFyEmnSPjyt($hY@OEpR%gkIHF3i<b`(&<>hebovD
z`ubI~sA%bdYS$~!f2evd6pcfwk7-^WR@J-;GNO7s31m$58LeW+RWB}u<b<ke0<P^=
z&!8dgQIGwJK4-N!k38L{cAJIP{p#n|1N(s5jnd(+>WFN>xT%kvgowM^?gQeZ7E`^C
zuX+*1ef-pa6hXvaeS^vq1JqW!tq-g3PJ^XDb@H3=K1lsKeen8-n%@t}qv~Rc1O%(Q
zp2furQ6Gt<_-Cm4zAL;rrhfWUC>~dT|0+7e)XjgvnG@<&R16-jUXu;%2=xm3?IYFw
zv?V^N?$v=rsb8jVK}D-wD$y6C{_kIaol;LOMPICXizmE@Q{SkD-FUU%3^;mPef4n|
zI-{P0r^zwvta|nHz)n#ALbctAYAGEgO;Q)Bp>a;VCIDQr+CX<_iuz~z-^o;U$t`ec
zYEBl=&Z{{-K)axR_awZysOE*he7gFj3uw$x3reA$ss4llwOQ)<bZ9JFT|W)nCG~8I
zi#sl>Ex(~PN3EctT~Wu-In-SBISsfx^@<G0<f~Wj2UnoB(;B2uokqLvtLiN|Xe?5%
zq#B58>Ke+y7OU_0!R-=tXE#Jj)xi`uy{>Mj(yKD{DnD>H)E6k-a#LNG0O(r|wSPKb
z?x@9HXsuFzO;r=s>a8vCyH36F9l+G9kM4qEgL=6Hjm_$lPXnz*ZPdbUtGfIe4Bk^;
zpiOYQ8b$cHoz+{u0%oUr&>JFM>MNA1?pBx6qurzC(*C+v{RKtY`qYm4mvO!Bt8YXC
zre8huB7TYoYCkHm8Bk|-!u+7RgC>k2we}a-9aej6fc}U&VHpgLs#}&p;gNbLr3%K>
z<rDxJR|o%s#tF5JDu^f5x!$lerB0^c*KW;QDd^jyS=xt2XHBu=cUW@K)Mtb2)hsWA
z7yC445216v=H@D(9ngf*w#Ze}-2;6$4UY?F+%+x?U?0?Y=Ah9-Q^<jNPtC70K@MrU
z`Ebok!w7?(x909vNcw0lpFpFp#%~okKh4Z#ko4E6U!~_SK=ZH`>|u?TqN0JCNlJtT
zX&%v@>4+xhNr)WPTv`GTgEh`+Fdw4%CIWUtHIvuj=rN6&PHi36WadFKOcS;gc28*1
z_o6RcqoZ$VL}+~I1E-N1pPPU_sadoU&{3M$G<yD`HM7H^7^A79iRzT*b_*=UYGm}<
zkJB(|!id+D%0NzQ6otS(qxpv>inAKGF*uW;`K=x16E$8^C?shbeg@b%&GXY?B3Uyv
z4I(KT_rq`|Rr53jBGNRU(CX^E=5h{ILS4`trP_dt8uw<jrfX)>wkktY`#QKxjXz~p
zvow1?hWptXUy6KO(nL%F`?99Z6QDU7FDzqcUD3P}0KHtz7MeTrG;Pzs<!h4ZbasKp
zj{?hunzy)c?W(4TatlS8EZQeKu4(ub>o3-9r#rAjbB$hSrJCRTfqh+ba1n-9p-H9q
z=M7E9``~VB>L^ZpOLL+f`jwi*AvE6BaF)T~9nIl?fL*0|;z@v2YsxpFuSO&HfZbZn
z_ArdTPSgG;xO&ZNPeGx<p_!iy7aKM2{{h7&P2f7%ZPt{`g^3nTBnSGfnxzy(ZquaD
z>-VnajlEF3r&%Tj*RGkh6AB%gFKIE|sd?>tnCQ~5c0#XP^F;(K^=Mw(2$5dRGv7d@
zPjiC8%=a~dlaTD!IHv!O)(4vFRLc8MbB<oP1DYRcx*OE&dJ&d}G*c9<8`gL|g}xC@
z3GFCGHPsE!f27IY2FWpvnO4~28WkO<o6tOC!WEs=yzwjgrZftI-mN{rLgOCoobNHR
zz1q9Z=-a1#-$7qF*smRH1v#M2cnhtr+Mt6#bJJF`py;lZu7JY_wI5SB#6zn+f<{m6
zJo+gPX(QGG%}cwX6^-87brjn5(Z2W!8hy1&N}Kp;jT9mB*QQ!<nFF*EDy%)Mb*FTA
zpq9a+ZB>wV=Q51xh}QK}m^i9+83PxredQcTh}K5cU7=d>4^TX&9W_GXxOQd?OoVCI
zeF1|fv~DZlZ@4y`)FZUHpTM<9?Vj7<PHGi&EFeldgI3Sc+Bfe2B}OZxO0!ei%>Vz-
zd#rZqD|i#99kHV`Ui&(IHSV<bZJJ8YXf3qoIjarZ1ZNVo>9pHFr&ZHJE?K*j&Tgh?
zcQt@Z)t)D})3i%n;Nf}go3TK-pe>&b%!}G}6eUmBK1*Lf$k4v}Efg}fT?l14W@Tyr
zr4p#i+B|y3a<no!xpPJPBgNeFwMUv^qCk5q5h8`!O&!p`rhRb)`o-F<AHc&B?ONJa
zm1$p8qpw`MjArl(Z76+`yIQM~qp?Qoei90`+Ry}m)oDvAp-`_~L4glPgSLAEJpkGQ
zDur*--lJDXvvw=33R|?^v<Gk1&ZOzCP3uk3-@DprR8n+LyDk$V?b?s%P(_FK4uusv
zwY`_n*QNEK;-PMBJk<sFXmuhCsaN}H9~Anu=kLS(eeGJh1N$A?avID7?P)5FeW-0%
z4447!?rRVo)C!u>IHY|=4wzx>SG2?((-zSzKd#+(86p$fY99QZ)XqDH#wqPf$xzs>
z%l!wKdvwRL(dVpd^Mg<Ob!>Va9nf_xhn}l0lpZQKouiaqIqtgKG|?Q?^-YI)4_yxJ
z_&jyzzCojxZr2(RZ(U0-8hv#7OZa_#b^WIR<EOJRpzg0ToJU`PZrc%9I;_jjg-D=o
z>k{+@=~`*BKdMWkVyR%=mRNWgqHCnxLa6QyM=qQ?rZd#y3Wez!=0g93?ho4DgzI)u
zbTLvF6^)^t)Hze$GD;UlFSi(-FKq))=~DLL%EapKP{m4|&Oj&5<8@cs!JXAzTLvyc
zcc24ciMn@bnoQDVQJVIg&R+_VWS#FPlq*QlDd==us&2tuh^FaE`@mh)+3PXFblsCp
z5Y5n?q;p=Gx`%WEAWP>Ri^go-YqaaWq-*{FgSf1_LEF|GT^^l}zM^A&kG@=;YYRq}
zr!)Qug?wEsz3vNiai5^CP?yq5|8sj)cZ$+#MY=f@0>7qv^dZnnb&ccj;=1nbIFK^k
zb1$K>T=$Y1`W3n^+Wp?py+BdEo4U+2G~UvkQ9->@_uGf?@V0J#CCDA!ms=oNrMsSn
zz8c+J%7WDDQs~aD(@on(&tJXHHU}^bx?kfV)2LhB2(C%DgAJKx-MuQf-=h0{FFb73
zEu({0ZMvh~XuPXiMK#j*bXg~%*RI?6CP;^_5}>m>b*>bL?9$n(@}yh0_!#<nbpOo(
z*Q-lD1fTkJCy#+R9_S>uKp*N7gwPn!b$i47u<ktV+DCN$H!+G)-G6U@JktF{RqJEA
zjKvTc*Xe}No6_B)7tn6K^QREmqyK&;M(CnX{SJ+L_3zT6XP-WboY}9Br`zg){yX|8
zlB@nj$`ZRd^xw1s#$DfPg~maBD7`E^^g3D{dg|Ga1Jql;fP#}g`sb;l$ycxZ4a84x
z9fTMD`p+W41?bNjfO1$L^*Ia%>Idnb3(`B&viXSKL37Db{T7;~gY|uTAQGaVSBYy8
zs(1W&5C)Iw0~pXht{)k~u*38(&4I=Vy`T+t!}T0WHALt?TniGdUvv%nG5RA-&^x6+
z*9VbUy`ExcaeA*SP><Iyp%Bk${jn=(Jfna6J?Nd)#~%hs(A(l5lBoZWz8I0DpYCV^
z+BtoU8w@7vU8p7@Mc+-qnN+=)GO}s<V%q(l*I%F`@)z_Q>!EN_-@6MY()GEtyvoq`
zP`ox%pHC}`EdA4zMa<Tpo(FPCe>o8bFY6DmG5Q>R2&M6^=o4upldJzt;ecYEzMr-d
z`TF@(vQnTgp=Cp%K4}FEUe&kKiH9P6>rIer`fwH`i}gnvAX%bcLD8I2eH!i2uIt+`
zf|Ti_X<{wc=h2i>q3`O4<PE*_GRRH+!z)0!rSE(J&Q$74{$GD~TfaRM>>YhKh3BjE
z=C$Ce^(ykTMjt@WO09kqO*D1-<rJQ)*RQ0i*#>?59++s<S5lO(Nk5y4mYVgF5j3{w
zg)|G?)eEQu<DUM;0`#@(FK$F*hdzM|kxu>o*XR#*y7Uc{n(5Z>d<*04(a+t8&R)In
z1_s)v|79aA-PeC$#F+Z^Pte={fj*TAz#i&XEJfph{_aBfJFKr-0Lc;kwKnvP>Yuz0
z?;q)3C-Y<a_i1Z7uJ6c(`h?z2g)5W#lI4(eOzFL!fm6E;tal-^$8h*#Tp?$}hO>}y
zG2Gt=Zm;3f3s5{@*zqnJT@91Rpx|bx>H+6&c#XC<2Myjlh<F&rDA(p`_?H$-hYa59
z!Fd@L%>|0LA)E`Jd<=@q=<_xFLwBy9!;tzCVEhgBw;&T>XrTz;VMF=jFcD~op%i71
zVR;$)ju`5eK;x+44%L$c8-nJ-V2B}r)`+17A6j!AGqh55)(OML)94E~xUYm>gh5AO
zk%ri-5IJd>)`80vWhnNB7tsdCE42EKF_hBtcgisJ5@ccxt+efpGi>6cG2Y;yS>&|g
z1{acN3`~j=Bp9}B1D9xU(B3l1@TwJ#o-?G-si0)T2C9rrG2GmZzEnfY4UjYg-vXb`
z8xBpv!UaRo75H?~@T`L}Lz#vcsy@#$th<iZY{QoQ;BpLce2^=K(zU?OHEfh)pm_#f
z8%*RI9?){Xz_2C>eT4?WVUVka5I)>4G7RUz(lx_MJxH<P)#uPxVp#Apz)B5o)8_fQ
z;a`dwlo@2v^!_V1ETZ#e6$bV1Fn_~v`YT}HG<-xgBex7qub{8ekaq%Tw+)wRrF+Nl
z@=NHeG6XEa1*$eYNhkhl3^CteEVYIwUI2ETp^6r8^@eZ1gTD=i=eEOcqhTc-8E7&@
zQD~^y@Yh=UL!B1G2))`{4Q<XKZ3d5jVg8;$=LE%e!<Bu&?l2V6+ojW>p|@$5p_5i%
z-G<&SH1-&>i_q9>*u4PG^cg<bhQ|Ab$>*WhZ}@Hz{C!|}HxD8Y4VS2(V!+TyWY91T
znLfv?Awv#TqYfLEo(1TLK{*O;)bJ|pJ0BUmZvtk_FmxZF<A(RtXq+(YJdEo!X*hNr
z*i!~G3y$tKj(VeUk5Ni_aA)Ij`bAuf;TDMOHJ-W(=zYfgeq56MMrAqr4j2o51#!3<
zpG^U%oAJX?u<pjS^C5H4xSy7j9>yPNQR-<tL4k}z#@{YL#LE~(H<Y(=8RcnwjGnjA
z=WAR@@m@dU$CQBcH<m;JGr%~02m?KA^!o>mfyUIcPzW*(-T?FwBiA3l!BK}XDIILE
z(LWTPh8Q2UKrz(lNg=#r#y=>%b=(-g529hlJj_?KP8iGg;AaXq2Kxd#!nltCkx1jy
zHjtCXb#&4q%DAWnlF`P`kHfVX<BT7HdCC|>8TVM@a{3A5jOT8mG2ZA9bVBB|vHwee
zo-r=fgPb*98w5;(acm#@5{>qw_(hV8e^A!-oY6i4>}2ECR*W~zIP^Ot&l|O)z`kI7
zj$#fMjcN)lr5hdhppao~coAdCG`iBo&obUwgT`!QI&Et%86P?*FmTy;^*?x%V|-%`
zxGTnt2FT<ZKc>}eo^eAYMDvZ(5a<^e=TI1@(D)r?^{yHxX=p{pb5sd+&A4L~d@44U
z1c8(o8?#}z)X4i2VAqYOX8@(l`28#BD>o+n0a9W7IG5gkH;gy;qVuM4c_UhH8EdHc
zq0;!&btv98s)}Inj&bTV`l^go^x#$-?;poStTApHL1V4)EvgW&Gd@mU)EkScK^lxI
zF+6NE#!@z+$vEpzINEGXqHn3S7&re0%vNLOc8b5W8PjO5cGu`hJA-@1yRPVLH(LMy
zt}@O%4vkLZU?N1ijFt4I`EKL%RB%1U*L-2A*H}t_#?oipUkrcm8~vx?VZU)D-DMAq
zDRc4rJT$t{Dt5p)pZ?r((72t>R16tkzDxC=!^U4(&=@gJE`-dev8Wj49~tZEq{W!A
z@GdmQjjJfoJ7L_p0wyMn>#6pB%J>sS!grhIorD*AOm4rzCufu4AN0AHey1hDUQ+<A
zVh@-c$q;ch9ef+a%@n7CzwV|-2jGR{plOQMgC3?~N@#hRhN;-f+q8+MOCOVv4*B?-
zp7;qq1(+o70rarRr3{UMrYbt<5oCJpJQ|OfTz>#LYTEH4#u99beIL$*n3lc(5^7rT
z5R%7CQ#&DY+|;AMSi((5Dc>LAFfH5<nMl(%D)l^RniT;q%JfVsoQXE&{sNg;(;nJL
z#hKoF8!+*v)$7oA*7VCgG$xpqwt-7D&9?wM+4NE;)Kg5Bw*i)F+8hg!G}HUE-ac=-
zm5;^?rgQxexoE1O1VFmU(M5Gx8Ky55qchX=DxLVtGM%R{ab=s<eT>E&(^nM4x?*~&
z09P;9RJ{}m1*WCHgA|(9-3Ga8>Zjn>HPe#Y04+AXvKMwsOn)^(z0{OPhdr;Gv|ppK
z%;ZDUPPr+Ks@5w^zdC5Ec*B&S$7Q=|>f@sImg#3Bytr-p;s^YAcTCUFI<U&LNC32I
z6G|X(=bQFW*r?VtpE4|UrqWg5>P>E2pwM92vKk|7G})d&V~eTc8<=l3Jx2B7ZKi)C
z;Ne}96WxLLOrK9Uz_y#5MUd$<eM@PGF4JptuXme9zQCAzO!H}-(QA4_gT_A7<FstJ
zZ`$dKOVV!=`GR|3+D!M=LsS1vI5S|%4+l4Bax+6@$n+isiiS;3y$Ei^bTt`Zk4(SQ
zu6fL~>)xDqaCe(psF-KM6hjBgCQa7o;M<g`Y%4T&o8NsCKJ78v0yl2QX)zmB@9i_|
zsS04f`M;e|IAH#nb_=fN1E(;EgXY|;Fz8`kLv>u9=IQjl_BL13GSbJq;3y3Fn&;CV
z+|S%k)3d+%uNZIvW?uuiAoKVXP>z^|GzA_tk5jB7*j(EWUqZ|#M-22s&FiQL_LzCw
zf6zE?K22GWF!L92uzSM1l8X1j&GA|ADZ;$<bC5`L_H=l0()?Ex)T7Kzj{_~*{6Pr%
zV$AI0=sRUre~c>=Z}y;6_i6KE@i2eJyx$6P)_jf*bS9W<pLT#InqTh(Nj4vJhDM6H
z{t{qP&AWr((*^V5XgGY)ytV_*q?=z}0D~E3C6&KrnxALG-z@WGddFm&v)+gLC37d`
zSuUG*oPifP<|TpXyJD96g3C2;e-7$-=I3`qJ>RTorH`u=m}Q+XSZE%94koUep9q3}
zk@*QqmtHe_P?VwAyy;h9mzax`Kr1y5ZUNeL^W<AVD>LtHg=D$;xo6Q=VQ!`J>l^0X
zw27@W@1(`|ZL?P|#&X9zKvCZ+bC?~C)#gw)`ch|&dC(gptTjtlL8H!WrwCKM`5iOR
z8q6!{ayOcvDMn+H`7F%|&1S#bFwtTjZHG^-=0rE3wV7RM_PA@F`2{5JnO~w(&35yg
ztKd4!wWSzDr+Lmi47<zRMW5j5Hvjzu)EzzMk0_YbYd(<-(LVFzbKuN<^Cy%odSFg|
z9DNVXzEqAfV9weCm_hT56p$fvH*HOa%}gq-88Poz1BFp@163K0nM*7n<K`M#_)VDC
z%!0zC`5Q{GOqoY0SGL>o#ph_;<FHIFfuf5gn5K`tmX9*gxzFOX3X1zJMLuxmfaSd<
zKy$aG1b{ne@v}nG!_rJ^JWtCQmB}Bn)bVf;ye#hwL(kjN(}_MGOZOJ^`C1qh7x%OD
zPzc-K60j5&0xThCfO**B_|*>3K+7ZAGz3`=QMKU_OB<b)J8F5g0>cirY@}FJh-Fm~
z91XP$e2QP>n8l9W^Q_|*OCZ$4EZ;iArxO;N0HEQPkKclNgk=|nSRySgn}KrDBB$vp
z%Cb5IDAAVR&Vj^O;vEx^Ib}KVK1{?~)?b8+r!C(v2ih46V>htRTKr~!ORyA#f=jfl
zeGwu_mQE@$OR;=McW$ah+6FGo!cIlsdCPn&%wMqlkO5~dS~}ffKHYMW)@m7+*ssu-
zX^Em~J<D><L9=DH#Ue)QCCkt$xR_(vNdb&27T?(b&9!V!g{OIz^;9O2ZxOgavcNKU
z5~R?Q_#w<+we-vaxn`-N^ir`!cma|nmSu0EvDEU80P5E*yk;nrS^lE2lv@sEqOrmf
zzl5sgZ&=zXM03;P<^+vf7OM|NQE3_Jz$k884pHLZj%8Cmu2YreCPjg&Eeq%bO^sy%
zl~vVRZe#(p&Qksk6zVOR-5?E?WmL-7Xwg%ExXH4bO5>U>e=A|A#j=lTLho7vF?Hj#
zre!uAvu?MXSpl?8i#t`GbXo3EQE0d21ue|?Sd_F)=(XIYU#-t__ZJwvZ@E?u?0!pR
zJU|~<LcW5?L(7}%pgv#;{tN1ZmZiHvhAbxf9`cCg%|R%PTF&L;!alMz&V;06%u-J)
znsJN%3&>1bmQqw?%Cdxhr`^_vXJLMiHH!h)oUL^<zwWiZ(**r}))&GdvfsLhUU3Jk
zUoC_sS8Ep!oSQYk3zF{Ev0dN}TKN<`^03aPd)3oAMHlFhwUDMHFNgIGB|N;XQ<Mbt
zv1ZT{>uWu`9x{H`1PWUFTVLZ~yaCp26v#VlHPfo&sP)@wkYH<<7f6V88qKev){OlS
zIc8n=J=Bj|%PGYkX3gFJ%oEn{1JM_5JtKv^2<xvo7}80rV>(5jqO2e7glM$&G!@##
zSXG-Kddj++_QJ8&o3ZGNvwm2D5yo3jEd|<X>*y@#pRxWF3G)fow<*YwXziZ|ktFMf
zui!eLvo54bB-uLt8NgDk&xAoF)!Ia-YtpP<iQvv#GaP#WbHRF<B5D_{_8sso)2jXg
zGFjFxy63X3JM&=vl63<efw^q`DF})=)<0;&c*R;}fqJfW9Zl$Y)+qY+K)%)f3+xtH
z_nR=XLhEMwZpBrrfzD|aS!KUM;hMFWir|W^ujW#=sKmOi7Hp~Y+%P(?TUr00vCNuH
zd+2g&2kmPrtgY9ff5VzChvZG`w?6^<mNk{$W0lrrRI+v3I!FtIJJ$E9e6-5?Z6Cm@
zt-=rBXpJ@PLtxfgi^d>QXFX1LZliU>zx4bySzn}_akF)ZcH}MA^k!W3R_l%dD7IN2
zIAOeZt#kgvb-rhPaw8<$t?IMT@359rT}7ugo0i>O)*f2ybX#-Rf%I6{{{w|yYfvrh
z_E|IAfpXs(@hnKcHF6St53FLOhwyP*>)Y-?8?dejf#RU`uR4GZStsT|X4pDGuZ0n7
zDs2%*t&x;&ePsQo6`*6*Uwkl_ach1)L?)~@N+V2K!|8b1ly!6pWVdbqe4y;Hop=!n
z&bIdVfZ}4S`~!`9ZTsGbh-05^F>S#1+bk4Yb+a90LDb!LoZd<YZ4a1e^srS^L6fKL
z4&AedZ1LAYyliuZFc@zeCmG)R*m(59^tFBF1<ud5;}J~w+uVxL7+`C93cuZ9TiRTB
z7--|Yfy)(SyYd4Xk2q{U>;ye(d-V-i3buJjaMeR>52<u2)E56W8jsng7l1o%i=%v4
zm~A)hS5Md)Df$#{bIJr4VVmOy$w*t>6<mvxw)r!`McFoy7tyu{RLBuydm##jPT3C8
zrvOgdp3s3iV{^RpA7IYfhA7~ZU>i<=XrgWHYK$<+_U`{HR%~Kg*d*Jw(dRl+Y`;~4
zOS8?i!o+!-PYv`g*!q8g-bLG)m1s=2dA0#N!#0a%(oEayZ^2-eEm4ccY@0LXA}`qj
zG*Gx~%XEAR{Ty5He~`IiJAVtExwf?L&{<$Jm!h%IHhU|axoXSV0=vbwMf9kY*aB&#
zT53B;cXzpM;4&;#*v8+5!VTNC-9V|dNh!K_+omP+cWhOGP^hx4s{pCCohk)pjct3E
z12PS^06KZlXxqsGT9fV7G>~T7Hj1XU*xr+ZYqeD^grjY?uw_uZYb&H`mV36yzd_n<
zi|4|p4x2g=*qyen<q+wz?Y@W$+iiQN3nD!>2bJyg+WNM^P@m1V4w(0CE}zhMWBP5s
zQbp4P+nc#C_|PU^4od^Ji(7y;XghTPibFOl1$>5W7TPtB*kUO+KWaNP3G&EhqUy*o
z+a#^i$8Dd`S&#|b&S;#pU8arKlx_4|aJ%iR++lZ*eO3%OXZt*?cOA1_?1A&qy4U{t
z3FsfNk5Z`9)qeXon0K>(D8wk-?N=!8anP>(0B9ce^hdbBp7w9)S{$-}+KxsqyX+xA
zz3qo6%<N+?{SkV;_VEdDe)iw#rRZ;8zaN+Z_HJ5q9JVJrLERB(|Axxvg6wZo_VbAS
zGHo%B+GCD`3$|}HLMFtXL=p5*dt(~<j@du>3go!`z;4(Lvq#lJ<b?eT$^(SkKS+m(
z2>aY0K_cz3y|8rB&ZPu)l--xkkVM<3y#n=E`wkZR;vDvGo&!w0{q<?kIBmcCH@GwQ
zwSBl2XYG?|XiT*G8(==kUPYf0KW87LbWO6oJ{%$`_TXIDJ#YVX7RUuVpOWeq?W5ID
zNViAL1(#tDVFEML9#3VbS@w2H_Ga5(d<f`EcE_}T(3)$n`hR4~-cblH-yV?<v;uoA
zMPmx>C$2-|s(k?!U>4b<qakw5{?#jRrr2I_2BRpk|3`%l*X@~`LCWmgNw3@<&VZv8
z_FrPrc*7n_v4&gre`lbv(!TX3yuWRK(P0DH9s5e!`c&C(Q{<xB9@UMDUt|AG4$(UM
z{vV)UZ~v7xjt%x#7lLcFe??DKlYR5Yu+(hdOu5?@`*QjYM4R1m6qfGV-<S?^&mP)<
z#&&!D`xr!r{SY0??zA^heNmVF?Mw#@j@r}d>P^_^#X@GvZjXU^=WYKi0`|UbGy9<7
zy6tN=G!AZ4)7*V%+ow*D4BK|_4lYUDwkArABy0<(kW})vuxyB&-xf(<PD$U!mSLb-
z+e$A2^YXSL8fV@%oehoGw*9h?p1+!H2|RRmY)kxqNO@Zu)mMyd8_I)EF5Am!PkLbc
za2y=<+CDQM29Iq2D;MO%_BGSt#i{MD(^2Nc?WZ4u`Sk6dOu=sM_V+1vUATS5M-VC7
zuBI}wTifR-A>y^;?0i@V{vS=>0T$Kqz3shscVU;Zu(xajOpF?1G@7U}iAjt})M#vp
zF|o(Q787HP9aEMnz1wJlbWn<*fM7vH5Nrrir6ZuA*aZvvy(j<Q_dGltX6C%_IWv3r
z-kCFJE<66&P3ynd9jiYA_mLfHI(wGABas4#r*_0FhEL~r{CWXx<vSMAilTnUW~|xd
zH+CdYCjQMGU+Li5{T(aU!$kiM=3NZeiyb$WfV(*QQVzPeqs9Z3evVCaCk=KKDM@*c
z<Cm0374BH>2DmBCvF$^sCOKX<gQdfcn>(SJ?wCqn)lA1JPEbAO=t1|JY{$?}AaWeP
zRiiD}F`B{yCmq$9D4lY=-U*)y9L;V4e#SA$9c_h<Bby=4I{x%Cu7n~-;lHgx$8839
zSnT*OWkQ@cIes+*T`P6`w+Fxrj(h$A;-X{G7pT1CICmp_y6o7jf{81Rb@YY5>X<$o
zDiw~_Z=kKxamOC`bj|Ur74Wdy(f<WBYaDmemT0Zx7CPNl=cu3{Y@6epE8y&KJdbqO
zL2~?@Ww3`$>ksDB1N7Bk)*XaLHH>K?`0JPknnqn`+-OzN$h;;(rJ3>MQEFwnHQ?`H
z#?v#QmsyvE4)rn08)$Q4N8E+*V%xTXC76wirR{6{NEau-nKxR}@%PZ%8)0eK@hr+#
z8(v7$%r~de(*8p`A2fgT$7nQ9>K_O8j~D)e-=CQMi`GxC&_3qm&0k}rKCAr#bW?tP
zivE7iQdZ*^Hr>E}nT!-v`P5Ho-ZE_o5A5`<Rlt6={5o`IEVDuD%(d5n{ko$Nf174q
z3c~2jw(LRGoEt^>dv5VZXqb0rFnaZk{U_+nw~;h-^GD=C=esV7$1JFS1Ek-l{s7V+
zlI+mB&_MTxMOR*eVe#c@_<Ko2EcBOt*af$it(8G@`PUSi|M9E`YE~$Z!^+R5D|Gi?
zxs%QitQsZ&usYcf&1=GtN+e(V*<k$r%Oi>o|9$>2e!DYnl!&^E;b|w`gF$XE?hcFx
zC9rxiW_hsd%@op;%!jER0SaH{n@1Q6KgJ^wDnZQM{lK*_MY-_gF4JI|h1z>e1l>QM
zG3#+{$e%OYXrkuMo*50Xi*>q9me|LqFqod~lJzj*#n#Z3>CKLQ3>qKSM@5#{H!1Vf
zk3D?_1|!(3w1|mhuT#i2ksV3*p(OSbN-Rlc1Lz@;!e-8<N8urMEgf?>%=%KGB9)z;
z4DK|xlhXLoS*0ITGT5)_-1HH)l%_bDY$)w4XR%9KVfQGTGy<h;HkU$9Ic)i6sN}LE
zv>-diJ*J>bHn*KJXmYr6I)s+Xg+GKd$2qo}PAlYb8QY<n&+Vs0)Cta=_Hj;fA5lK)
zDeh(_Oq}LsYynLH*Rlexo#A5WAYvg`X#mYx?!-I*inz~d1$mCk_eNiex%F>BrG%3u
zf%-hRd?QMw+!#7eRmL3>;O_-)@)xxJzQ|?jL3)Y%sTKw=bAhzPxWZM_&R99O`WxV{
za_Mtnse)Vm8i1ADVOjuR<1E5psfyb{rwgmO59Yx{4Oc<O)@nJCH0!ucv?*K9&8NWc
zb*|JEnho58=MasYat17znz(5C{xx%@!4NH6qc<$Ia(#3Wws8~b>|Z<gx;exRE|GHW
zI=I!eP2S0sRif0zJvWEJo7^K>(cR*<)0eiJQ}_bj!%h7eoVU3RKcVdo_uxz5dbwG*
z0l3TMQhLfg6KDB1RPS>;-ozk0;MP*I+e7a8@2Gslo$`UFk2$-006yWaQbeVX+d#V`
z{hTr!+)ughAH(1?uJt4;pL6FVusF%iF2_(h%f`^8GeZ{L2iy_a`mNy1ly%0SlqEC0
z2f$I8sih4x$7JJcL6a@JeHXPkvQvj)H&>>kuj>`rd*NU!m)))c@T%<DIcQeMS|}RU
zAX8GRLZd8=;*%Y+c_9#;vOFGuTQUu0c67_m3<b_Z-bpbkPx)HP4EB=q7I4&8zQsh3
zbw7EQFKYee>{d7vAn&Efag==Vw?G`1TYe6aC;z1pB40i#6o3=*refev%Gc7Y@05J!
z_b_o<F447GAYWPlyJzITkiTc;pT7kUi{!yhs5~ccNP(eZ`FnE!FOg5GrTFuC`9Hm|
zTPjbcH~o~!uhRL3CPgZByIJuz&8b=xz7Y_uiY+67Z&NI$hflj=5)Jna#rLfMbSNf_
zp-)RO=P^8dqA;*%d!>l~2b@l3Z`0cXoz2=R;Dw8sKka4tn6)%g{Mpy+H$T++nYoXE
zGyZ1JXxbKNRy+n{8Dut?X3)WA%g>;++pMG+G<(eI>3O`@YyriJ_L)tMM=9KF?e7o~
zX6{X>j5M3*1QBaCiDF|%&BAG2c+70o28e94SV~*WF*}+4U$(T_MatI9H+w!AjVH|V
zC&IUrW;S#%{gl~wI>>a|EX@w360_^Q5a-Qa(z&xzvvuwOl$rfL36&Sj=68YRl9?xc
zgqO{3Pe<=-%uZ<FcCDF?5;f|~R+qu2db0uwoi><F{Ty&pqge~hi<`_wF9S`pSz0i-
zTg{GBjJnONJ`I&O%vOB>nhrBH-C?@SK1c=NrrAH|q0(*EoCk5+Z1W6g-Z2|B45HV}
zMuHbE=39S+_xsJW9sw6>zP%ikVdf8mVLse^!+CH<n9M(-+hwHr-EhzxFz=>4(kSyk
zZ$LHLT)7=OvF4+yK^kWsL}yIm%}p0jnPC1I9_v_0b^HmDY~D5uEGgzQx==b~{`%L@
zJZ%2mOt2g?pEeF&WSh^SGX%NjtLPbZ-2BlgaORnt`aGeNZ=O^N#7T1tiZz`wk4Q%2
zY4Z*1Kw4nV(QWpOdATDh&zgT!1GXabzi5VZ&isu{U@JC{r48Hj=6mSyc&YiO2Vf~P
zA4CV~FPhKHf`v=w4=JK}*?h(-lx~^l>;}Bse1(aE__xjHhN1U&%)Kap+-v^m0>oYO
z$G-u8-`uwZzz60DWzc+N?m{=Q$L8xPg7ngSD?OuLnSVzciB8I^a%eg$*PnzlF3LoT
zUAihQ)nIW`-q``y+?5qy0kBKC@e$fQly$RB0D3AH4@M6ImDQ9#AEYe41MU#zf+hfW
zEC2ZcVy`mf9{~3$S5f|Zx^gzHnlhA2>4}%A45Y2NEamn2AUmooa7F2u(!2p8Tj@#<
z@f;<Ngk$iPqw6s;$CcA?PC%ZgT-{60zkKC8^z=WW9DWMoq;eCT0zIY7q7}|*<(A)p
zFHl||0OE{tFArx5mE%s(N1<#oz?mZDZMp@YQ|_Dq?qX$41lmfJ$0=5OUU`~gfu&00
zPtYt=j;8DJg7Wk%h>OaX$O<sYFDrG`(7B?V@&es1S8j?2+f}8_B$%&I?x6pTQ>lF7
zhRSQoMiH7-%5`)JR4Wg)LDVXTEr4d7vg$JoNxia(5(us<_faxMgEBA}{x&M}9bmpm
zd792>H7kFhE1^Z1c@#KPt8yx>1KN}y{f*joWf+|^xS{l#1<|2g(+-23%24W4mvT8x
z0B<TIX+m^Mx#e4!2vS{n0oQ_610w+lQ@u@R4Z~F}G%t!!X=%nDsY>jFh*A~N3(cZc
zBM$=}qiX#T0;i?Fv;Z(p)o%t*<5l^Ns7+K|n+}>J)z!h^PF8)t8X`qi{}V_LtBzTt
zElss%E!fgkuQ!1^Pi1=puH~ybN5ZF*s%LaPol@nm1!u7;v>KdOR5yK5Dp&2K1^ZQ%
zwh)6?p)%dIL}R7ur@;VTQ_V;PTb1f)Ci+{gT2KO=8dX{>?AEHLQi5fh%BLQpUA2WK
zfHzcwDWSSU74$0%cB-Q2dC;Y*rugPf)x%1-eM>dP1JpgL!f#;ywrUQ|eeS46kAR_G
zm5+&@n0HlgQ}FSg>Mc4FcVCsY42=&|+R31Ks2WL`JC9U%1Ht`Rb?*{X`c#i;ud`nz
z>;wF%>RXx)K2wb^0?TvNhGh^hRC6g>GN7uWCE!cdhxB%+SE^NXuE@!vjNbC%Y>_t7
z1nFWig_a$z7Ee~9<YwXb6gut}*WxfxyDVnX49>&i-59v<ZJ~PtgFY4mwAl2uXr)z`
zzs16BC<R!ws^MCoMP3*xgDn0?21~Go<^iZfECRkpX}5*#zko+t+~1789Iy~0C|f1U
zVn-wp(H1ARp)tndb{k5u7RmJ4$64%}hf=GBu@&z3S;#1i?PR(BM`$`*W=6rFi{-e(
z<h^A<J5<~(cb$c!?v}YTf%CHL?}duDW#M9Y=wrz&1*fm2{jUJ{TUuMu_b<TmyK(4f
zkYzc&6(HC$aUXQ{S~eZUr?$_MpNO{omNDz#eyHX9blVEI9K8tK5th~z^o+EeFdl6O
zEX&3N5N)}YCTRyPH<<w!V|o5laK>6@^}&3+<+%?~nPB<NKTt`u4E+dXrX<TLV<0mv
zXVBd`%kqu0Fn`ptl>+?7EK}&=mTl=xxhpxA)pMblYdQZOM4n|lebe(T*V1O;Da$V=
z16N?VnbtFBEN@T`uUh^>Y26i;6*kbUwETdM1zxl4r)YAOWy)r-RGTape2Cf_%Tl`S
zv{*i+NqDQ}=x#K&StdC`wcXNE1)2`aVJpzlTbA_{0PeON(E!aJ%MocXf7|kS2vqJ`
zPS1hA_bf+In&y4Wn%D3#J+RDs1ATd7nZ635&+<)kX!ct=(|NV0mZnSR;psEWDMw)G
zx#c)3c=5v0<}S<+Sk9!cjGvV!?P>X2#ZV+Q!0PEUh(N36&rlg;HP8$ZY?Yf2T!@vL
zR$jZUKA>;K9xDS6>b+L8-vZe_s}Bo++i$guu98rzK3c(qS$$zT0vT@QHVdi|R?24J
z4_H0ygld%4Fa{#p%89aF4q7$S8ZX9b{#j_oTGi3BBF@UD1|q>qS&l(Sw7N$Dgd{6J
z3Th==)#*@q$ZE(p=;&c9cbX8TTK%;X=F_ZZeFl+k6~Bx2e=@AfUPtkWRsLJ(MW$5=
zo#n~0+SL!cN3GUS`fs*Xc07cqwR-`CmvzZ^(Db%GJ{&#;TQA!IyJ6Om<ESsz&XhM8
zVXdPTOr-Tfde2al^>|k}8f|@?Hn9#`pS=tVG1h(SIDG$Ntqn0SA7`CL>7l9CBF)E+
zS%+_f$hIC814NGXa7!4>wO;WCXf9Zfr7-73>lHL(ykyPM<g&^-m!6H))}yN6c8&Gj
zHz8`Rg~zC@vpy?8rQZ4p-9)Zi>%!n+gLUssihng)|MnJ4G+E!chQV*P9`iB0XtDn7
z52&_UZ=47B+pIM|LENyOK%uz~YrF5E(rF!<51KCPF%$*AX>AAv;DPns46r=39@K!g
zN7e$JyL@cj`2v6^)`?%E)Mxz;CGPcGpQ5j!>8bTIibp-OE=~jRxpmunsC{AWNFj#-
z>!0ZJd1*b3t~n=l#2^5j)r06%vWt2YJyc!Q?{@>|ranv0Yj^e73GiZ<`u+x#Jk&$~
zfTpMVO&#D~>IpRfc&js4pwdTOHVfnHYf|qofq6f5Bc<o~tMB~_V1RlMB_Ri@yJ$#*
z)So{_Td>+Y3Y8)1sfqX~_NXWSH!o8E{5w?ksmD{A*M4<oBSfhBh7Bsi)OTtyGU4jk
zPf?0ckF|oqNcEU@m_MMNL)&H1YEup+C?8Zi(b=#VwY4Yu8>@cv92(=)J~Po4uQsE|
zRf2jW?La1~D-vKLSv_J3I+LOvri02Mb=Fi2!eO=LN|aL7jR{~$Q}_M%gjRch1}`$y
zvC-f>q8_ymDw%4V4N%Ea%S^PMI;u8rMxV0P3HP9yqkfG}LgcD_cY^e|dO9Vi=c&_1
z!hF8^yEQ1CP%CJ%byB^a677rCWe>qtqQ3nd0O!>e^v;S>b#@jwE7Z4qpi-&su0{v1
zssH^El~w9jIUuW6rv_10Lyh|N0@$rpchHTsPF<M|M7??p!gKQL>hCDys6qV|EioI_
zyCYE9q)t5!wq~{KzhG-o@24E2R`r>Wpwh1XWIZZxs5k6H&pOm^yhK~4+R7b(F7*d$
zsN7Vqr-#ce^=W_l{&lN`+3=!Ay^=1I+v>2%K-^LPVTa0Ib>d)D-c@I~194AXTnA?!
zs^t_Qe5AfzinhmU<_rK&)SE6q^r>y!q0+B*aEBL9)wA8v(P!#$aR4~mjBrGyi_MO`
z=&q~Hi9p)_akIHed1AY4x&p!GVY8wEB~P2TX(r`mQ}_#Avo@7ZX!EhzLXUP|o7iEf
z^s`w;+k^f#8!}-xz~(5O9|^RX9|sX+GkF#)CE2!Eq7x~$19EU4w%wKoT$*jD9h}Lq
zy}T0^OqsUB2SN3ytywR0vTYxZfu%fKIS<up+q_)h+iZ1|zus<ZlYr6<TX88$9k$I2
zfbX>J8VZA5w$JG4a^JR!mQxRG!$w2%iLIXq(Qj*_?cb-iQ5F!-Y>!h8*mK*=MtJeU
zWcwaPA_i;|(@^`;cE}9aePz2L4Qx)DL$n*~tf?h~E}B?Mv2fMI%>=+#^Y(6V`)S5~
z2%2zBJ0)X8Xmlay%K?p^_Q0bw+d7~UtvUQLN(VI~-h^hXX4?le2%3R%0Ma$4=s4It
zu5rkK$kY7#9Sr7cwv2_&IgLvd>=tXXLg?z&B+;>^^P0D5;#sQM`yoV`hCKw_1<ko^
z;4W(3`WKa#G}&ul_p;`%MG#jsVGmGQu9-y>-m9AV6wtk{SxTwu4H`QW1!o#Hb2h?K
zlcviVh-S?XekiqQX3|luR?XVqAlft>1JSN2dH~=JP0@4osYBD-fl{YNwhJD1X+F~e
zepB-;ZT#HQ%%tOP-I|tK;CeLdS18@qn7;>=JDTS-K)o89>9qfPSJPpE+IyOJf&sj*
z>8Fjs2b#1-xb{%P-a_e-X8jz{Jk})8)AWgE^E!Cgr@2!Jm43}HSJ3uU<5LCAXPWnY
zP<pO0%ZG^<nvt{zH=r5)H_SWnlmEmRI`dyW#gMr0XZmUX$CV#71gdVl%~j~^;bj-V
zy_f&-YjE%93&w#hl+U7rBN2RyEr5}H{XtY7;BU`|zfpYf-|#+~-+Be5gM887z{T(?
z%GZzOA5j1#jyI#Mk$B$nON>(j??#7`6ZuO>h%w2N_;L!|C-diMI+?<EHlTEfPo@Nh
z!~AU81WV=nDVmeU&+>$cbbf3OG&A^7GH@T^Q#g2^$@|hVgDl=>BT7ekD`&7A;~T%k
zaAot~(6Tp&A7lheE`RhWG>`L9!%%6;<8zOon9sXRMDYaw1La1Y<X@W%{3*W25s1_L
zf$JbG;D;<i+Zp~XdSDjvXDE_>mUlZ1coF}K)?w%P%M|`8=C@GjuY`YtzJ}-dTAC7+
z@|S5Jvy3-?f-YU)e-1(EqKThNv#d+}@AW`j=B;R_>I$Fg4xMs-JU!g5@-3E7t>6cp
zf@UQ@$P%ByHU3;9%vbTF>A6|WzqCeW4gW|6mRep-*#UL@_)QS?eDV?W<vQ<AGoc3l
z9BnBy@=GG1*~FWKbjW7DqX<20;Xk8DZ7W}(gK8VEpaU!Ie0nETZtx}caIJ$cu|``b
zKj(88?BdsqMB7c?>oO{D@yl+(U^jm*3y${ilPHLEo1d5hNAK`o%tmD|zx)!qbeEr4
zi_yNv7n<lfcAxL0&)@<7n+hZQke5j)J>tKmEuP1G7){%s@HKzHnLfVh5=i^`#!^^%
z%AfIuc*cK0VVLLq`jyap!Ec`r_y9luBs5?0(+;7(ulPw(fIA6y#z8m>_bHv#MYt4T
zf_YaVgyzj|LK>YGau>!TbR^#;Y;{J-L&&AHR8QffYasO!hL*u6Z(%kq419zkX%N0b
zLme#n3GY1w&R>Y9P2>O})fH`lLT4o`1qoqEPze^k+z1atgfr&wcen6O75#JHJ;ISS
zFtJzIm;%H;;U!Hc_Y3`WWIt5+*$d+pCXA=2c(|~KwwEG=IrCvDQrJxQ>;uBYy-<k~
zM$qeZqlF_^(U*gQNat)~gj(9)jurN4;eDKt5Dt}iA;TM9BnY#=qqmhM3L$h<BuRK9
z5^TwW-)*R-2vcaSc1U=X0&!T#rIAe)=4#<ZnlSn;kfsYmAHzh3pjnB^Bf^$DP{|bL
zUqxG%aCs7XcvQ%6g27_~LwA8}VZ8vA93hQzO>>1Dicy-53vX_R`8?qzjZnVucR0+S
z5T@)v>7=mg6Ch3rnafc+EsR+WQ6R)G2jGk_eI+yth0E_@oX!dbD`2TeSoI8c&k67J
zp;RoG{so{!*s=?N^TLM)h*H6kLWX663+>TeFbQ{}FqRjEjdW_@k}x|Nq?d&VipyOQ
zHl%>9To6)Fx+)aX+vqBUr*lDCDJbYoF4u(peK21oFf2s1@b@N&8lm(Y$ZCbtbQ7u*
zZk>Updg0g@v|SgXUV^1T7)MjvM!{q}27^sPJ0+Mj3;h%ZZ4u5Z(AX+WpN3MKpr@3q
zcA<1P@Hd3fv~kfPd{49fPGKtrKD&e~`$2kBu%%s)TSDDv;JSs)k5JhoENB4PZ9&tI
zwmX7}4y^PF<_+leUE!69V*U37b~~=C`$F>%=-LC}Eec>h6h5XI!Xx2uGH4zPOBx}b
z2-%zAZ=bM_2cTc@p!L*KVIy5v&jdTVCp;G%KZfQD!F4Sv2ZSVh7<?%V@q~CKY|R4B
zNzAYWi?g^@PR~CVaRNoeUByc$;kTRkiyW%%;#+>u*(IKjM4N}0O|xiEF{cCEUZQ3z
zEP0DPEZ{!kOcq`96)h&APky4|Q?U4p>ohPQAbvwB5`p4y6Dotm1}ks|ix-9i5F#!(
zO8eit#bOF;>=75!;O`Y#3f1frr#yk!FHYG9OQGV}S^&dDe|lj-xOk3M-4WspAGAe^
z_b51$DxQ85j;4t=6nIG&*M0z%4Do%66CV+Uc2s7HL+Cq_C0?f0_EC|?9ML2{CYsZ9
zGFyDK6`tmZLr=rET(On%(vFJ`@vxgGMp6z+zF1TY(i7sE({S{p`0oP%PKiHKbn&$K
zE~Rc4i2GdtI3rd`;4Bn3Q&Rg`v2hPdMPf(=O6SBwl^`n?m(!HmR3d&u%bW9J{daJ&
zRP6g0r83cGC`?=s^PYn3qWIM}0A3P@EdkACF_^vpSHusT;Apw%L65Vm;zujsT7@_x
z5~WIUJY{lT6CKyXQk9rWpGdX1G8@!2;(1y{){2d^eycNyw&^fYFFuJy?R9Z;A-dfl
zzLY_=QPhlvr6w_rg=({SiMBslM9Bl9Rn+W;i8j%fE{}Hco8@rrhS;zPWF2C}`%vi=
zCoe~-OI&dYJ-aEsnh&yD;&8gpbc@p|WYHs<X7>SjTkO=p;2lv-N1c1cyNPJLD;DNJ
z+!NKWp-=b46QOYJff#)TrH5j>FYG=N?@@mriww;_pNNBggi4>djPn2b#TR2?{;9Z=
zk|myrKeHHw=VHv~sC*%|yats4ai=LC@}>ACMUP*JH~is@la#a!U2~S+IF6Ewq@h`*
ztF*!qmfWN_nqbLY+8Tq>E@=sUVLhZKnqGNIpR~h-mvr_l0NzqB-64D=hoca_5=$4b
zpS0!&sQ63Y(c?ZqDu2ra87NIp23wG{n_d7AEU6cQEkr7$o&Md@oTsSVBMqWJ?Ow^8
zmN5II4lPRirN8JEJE4;QyXZuiwCHQ}K3qD&!ovtD>N+$drN58B-~nmZuTY7S7JUbm
zXzBcQs2r5mO{ec)jFjLHhhwFyF7P5w3a52gymW-p2ot1f6yr>kKG}-4Bx&p#;FG2K
z_OP2Gt@4C8Bn{1h=3(h<95hp<wg8Z&NmE3W(xoPfgJei)w3T{9;_0cBDK*UiAWJfL
zVDSArDml{k;h40ZvSYKQIdskCNN3KVGFP&@1mJNgGyrUQQvV_JDPKyViOC6R7TwoR
zO0hKRr=-+$08UF$wB9X{Hc=epj1)|lPN7sf2bE_fn|&x1N$+W(c}_}Epwd(<eLNAQ
zCDQQ#bnU$Kgt$v3hd7LSnPj&fK3$OVI?#4e+D#9jOH%$L7`!Zf`WAe;B4u5KX1R3g
zA=<7=4o^_3keG2WUnvcn1#wOCUJ46U(%p%`RZDYeeo-S$rZs7;NvfhxrcRnp)0KK@
zYCoL1E-e@f)dp$!7T_DD6*RI<QsqZ5(JXz=0N5fu7!IFWC6{&p+N9U-fu&tKL5biu
zr07PN=#X~NDyLH#69knm$ruX@H>D~H``(iHT@c-pY5X13_DH%`=-igh(^BG&6kP=K
zz0yY%Lcc5hNUv$RCq)LLbYI#z1Ede6dm~`*p_EPw>_^faIw$v7njQv~C(^ETxZNks
zt3jz>TIPb%Q|VhecJoYHOou9;OV3{i%L~cL^bT|eq@=OXc_~$9prfy((cePHNxPnf
zi_Y3w9wuD0zv)nN)xO(}HaG2-&*0N;Z8oh}_h@S=33;#93JKlvecC^U1F&EF+f=lL
zYAyR9!nG3u0f^B0#zQ4iyO{!)2eh7p>G>C>{q-u$M{A#MK<S{iRtJ2HHij~MVzus$
z@H<XBiAdwM9u@#5Xk`>)P1G(N1(BqEM#1M~El+0wQncYTF*&4NV}p<Buy!wn?ozc|
z-+}ow?OT-TlA*O&48RfXmi2U6JyZL78%VRXH*~OcRQr&o4ac-`6tK<K8g9X-9PQr}
z%+1v{7@&Dvdtns(&C{M9j>>%PK3ck*&^ir)-ILl0v}<}wyYF4Joz~)b555lCFKKOe
zMmwboDuvo(RC!jrGl25ni?k*+Oq|p1O@#Z!+FAB6U!t|3Tf}+objtWE)qYCB*fQ<J
zJLt>>ZP!N-7qy#rg7lL1!!Ka|vUdC%;J%_=MzP#-?Q6Rsu4><oMrDO|DJ8I0YByCu
z^O`mx3ZhE8=r5QxRco7@V4_C5cp6k|wPEoPb=qsw&{(g%K)t`NT}+#T4cfd(@TpPz
zkXBbs+U{VGHfyclps#~A=`cuJwQldir#9_^&mr2iKhtXehPKBE&U9!$p><fNc5V{@
zUE1DERNgdcXU&GrE$#6mVC&ZYtcIl??e}w0d0Xo?1>%m@PzSbN?Mu2L-_`zY1^hkj
zQvu?>_R~}F@PT&a9=P^U`*;op?~&GP7Y69D_5vkFJkbVx3C%ujixD37YaK0M_o+6D
zW{l6YrUNwley-hQfX)l;4@1E=pk2NRsxP%AkAQ!rZ7qk2ldk^&JapFm@fJ!hx-?pC
zxaw>u((0yrMH`*&x;BbH?9x?JR=S7IjV^9aT^MC>c<Cn47OuB$19AH3KBa9jUtP9|
z@^1Wei)q`_U-un7%mZ{ibn^?;#a)6<kghEgt_ADX{REW|-4qJl@7DcI+W~uY9+Y{q
zS7%G#pMAP*H4yuCCq96|P@Vq-z{7NZXJQP)bt(t2MCiibf{4_8U<a}Tx{{|RAfj{`
z_kf7jWtGF3gSzF`sEpAq$_6l2x9uECak>MvBNVT*pMg?>u51%ZiMn|+QA*O8)6FDV
z_xf5?rs$X?kR8$`Q1I%ou8f{Tsk$M*!rwGq?|rDG>z2I@>I_};O3HsZqPwcb$Y$#7
z+QF8k8@ddQM|Ent>mAcwTMT@*?rSAfa&+<AP?@WnTZPhbojHXZ^K@Qr81;PJri;Lx
z&|RbJ_@r+978pFGTS2=Zr*+3^m#RSbFb<VxbhQyMRH%FFAk9C|>8@v?SgiA#3Dxtu
zRg+<`RCjCv+%MB@IsxDXT~8tWzNl*$g|<t&R=O-N>)L4McSYy79V+FzNJ>P#s>`Qq
zy+YSaoB5Txm2POerpu-nNtMp+OZZ!@J3uj#8r||Az+$S^Sv^K=oh~p3pMAY<QXo2W
zUH9x$=rrmk(wm8zbOkSAsadyo0KIR~U7CqftFAZ~+-<tXU7%^#tu8|+Zs;~qT6l+U
z=iA`y)GhahGhMn22Bn+2Z>phrOQ)ncZMUvrG~hiZUGWAKZ|ll3A@1m|EP-mTu8HQ<
zcXj;==-kt-qecG%-3!_~eyHoE3E(5$p@$HUbsv5R+!Ng?4J`HPMqY)#{kk2LOYl@@
zq%6m0x-J)#p6iN3Vg7|~69qm8bbrw->7~xJ<2q_z=|;bTs*`@uLa;gO->3Pji{7yV
z!c{+ZIlOSwKfDNpyZ!(r2JX@?_yh($^b<})#Z$kA)~jCn%@e@lt^Yj$l|K42H!&8z
z`lh`A_~{wi==ax)m1qml>;GF8>1|9W01VQ*-bHP&{ui2Ogy>`5fs4EKZ_+e&kA5EQ
z@$J<&aWKD6|M^sy*sniKnX;k!_ne>-roS>9B3z$)5AX=RA|3ul>c@SKPx64?Y%N5T
zzKk}`qxB;xlj5L$*ff-4^hFcM?^u1zS188mFHwGBynY?^DM6nihiamJ4~rp5(hpF&
zU$TDKM3hqW=P0x9kiL{=JBRf>|DtQD`oju{G`(DbwsgG}9zF65{d$_UAJJcngUHmk
z(^5K1e`qqiKdKLVpXQ&(^vCH8dba*PW%%Ui*VC6ISO1k6d^)aw%?Zxr>0|exhxz)A
z+2B5*Pl<uullosMCUi=_Q-c9Mt-reyl?D0?n!}&bpDc!@LVZsp2Jfu?6Bk%0(tA2V
zoYPM{hPGn8amyfl|4Q^c%^c6`uX&>PrTRSyuv?}d><=$4=(nGQ`HTAY*(hDo&;JW5
zm-WFJuyjTLIxU&X^`3SBT-CoH31=$w)qjDzQtwT#)3~Phl*3?^{&Nb^RO?w6Xx8Wt
ze1*1JeGH|lo9guMQ4V#ze#k}WT-PuB7^MdN`dLtI)Th&abd&xMinKQC&pQCvqJKUG
zrB?li??AInKk5!D+x5F?OXh|?VF=83=-Y;45bo>U^Wf71y*3_zhk6t34?WUX{R;6|
zzmM*uPfU6f9d_!|YiY*Wub0vK@2UQ`8kC;tH+G@zxjr%;mR{)RQ^L-G{vNH$Uh3=P
zK$B|NsDx&k;ZHjEl3@_vMkg{24(4dfGKB7h7e@`|`KUZ*Sm%$*Y{Nga@XIyS(nKuJ
zVDh05UcMo5BXmw0{Aq*el)?2ERGv0;DCrY5w9`Z8jN#mRuoW7XQ*z5$Low|r6&e1a
z>-n4^k7BDOh8~)3oHul(!<kY;q6#V(45vQ?;G$tW9S*r<nEpB{FB{fT(!>=*g^5Dw
z<%R(|wSLubDG!YmhA$mJQ)zggX1do5!xN!eWl+&EziNZM0e;sQ>e2zIHSCE-Wt}0D
z*3$Kcu@rW?ZrDI0+hDNTh)y&boaqQrlcAmF>CJ{)KcKS3pb_CyhvA?vegAG6D(Fzz
zEyG~i8R|9&`7qyO*hL}#+lHs~Rl8$YO)=SCgLwb|cMVS#Li4_1%n-0WFs$_e{Gs8!
zNf3_=bx%?G*l;xyDo+fG=kT}B@Rt&m{f0v>^zj-F-hngE44E19-%_3%swk`Fg<<`9
zm>4j4Qi8-wgD(%AR|fV|&^Q@C?S*hQ_S>P&#kg%3EV&wuvw?FnYFEK0cjKu0P}yaa
zZ$Q^PjL$wto2PL!?bvx4p9<)Ux3PzIIDCv@!Km~#4#wu1N$zKSGzb0lH*TdFQGoFQ
zB|8QhzugSdU}HUHNro6p=;a){jn`<aVUN+DQn&URKW)Nix6c^i4VC@IN%U9=HIAr)
zr7+{d72pgv{>!5+!kDrYxJct_3jG~0E*K9BQO2t@PcTIrz37>K(D(^mEiuNG_27;(
zK8?qC#Tz#*Kz|dA9Btqw8f_?ok!19uaAb<{Go%m54;!zf!BVR6Fp_!X>BfW=5E;gH
z+Rr*-+?@@(nZ{8>mSs$#rT9_f>y@yOZ5*KC$}t(cXhS*IIN2JF$BpN`;6<J>>1UAU
z8`J&a;t6BPc+i|QeoHx%r;M}S1pc&fW)&(6jAaH?o-y`ObfVBWYBtEu8g2K$(IR6?
zC@RkxgXtAy#m1L(U6dFfrvi807`O&3rACv6N8<(KyDuRw8V6|S?UJ#Xg>RRQM=8{K
z#W;h4*X2f|fI+xw+**ywXU4lpVDqr+E(ML3T>`~8z3rAcqivsEIjt7L>{RveBGQgo
zg}y}Fbq@nP)^5xv&`h$MO{11<S81w*YKq+~THYM8+eMF#!*<u`o}X$rVmiD?vrDAs
zZo1v?%V}io3Mp^(h+Ug2hAY#~o(`>N*=_g}c8}VHQmWZ8JM~y_=GaYG3|y{V2i;H$
z?Gig-@T{G$C2&{lcK-{qa=S&1w2r%Kr(FTN6?SVrhfbwk(~ofGn%$YN(X}eOt^t&)
z?TmGxsj*8*0>0Mn#E-z$*>x7cnR+{`MwG7G&G{Xq4R+s*1g_C;X9sXic5`A-*=%PR
z0$hvTuhZdEt6eU|gxc)-Yn1r@-LQLU4ek!R75QLuwLfwTeR8v(Lz4h^`<UMW++`oI
z4WtqF|9lN#r2Wbiln&T`Nptxq`&<f|MccbiMCqXYjp2aD+PB<7Wt@E#Jx3Dke>ww}
zbo)#_EM(Ys-A8wi*bh=u{#mAd`rr7Rvh3|CAaT_G`Z<)2*?Z50r`h($0$}O1eKjo}
z3ha-#qV0^mmp#M<`=HZcyJ)Za9^#UH8*M*cw)eRMmU4RqB`sChGqkj<v|mLhESl^`
zhQPyS`&p;J*<wG8_76<0_Rc@TQoH?Yi$Qb49uW`R#Oz<u=K2%+19Wb*&)%;ded@Ol
z`3;}XQ+pe_JwLaPr)&L%eGi2f2JH7(qx91L&wl`Sa+pB@5NC(#5@@<OWY2&Xt`1*#
zq0P<V{y|i_JAB%Nk=bQ(5GY&G(?Pokjb09CYazTH{CA==J`TSQf#1Fkzt#ic=P+e1
zEcrWhe~eOqgFtzDK@O$+0S|U)$VFR-!x+lL-0hHb4Y)lH*vY|t%HjJ_(A?(`iEx*E
zzk^{V+QJ-mYSFWB2h)x@Ktww1ib3N6hba`bPH_1CzvYd?Lz<x{JN!WxM2f?R*B}l%
zlvBn_n!{3B8K*ns=RhUHp^tJejyQy@fx%1%XKQd~IZUIwz)^?i$Kl~I2S-W;%y!5>
z4w2)q{3np*Iz*V(VHA!#OtM97zQeYBI923eC!+D3!^h>o7dx!6hx;WC8FcSH?=ZCl
zm8A|#=(;F#NS34WqJv@ySS~q~MWXGp!~8R7t9E!oIc7Bu8~1{`+2MD}=V)<wdoWyU
zbr?r0m^O!%&Gh|icj%@0_6-L;odxM|u$_X+PKPZUf$ws#rElC#hfo3dTMip%p|aay
z5+yP8ILxSr=52=;JK#m&;H0}OOyTFv_qW2z2=5j6J+hzT)UJ#peLLKk%PA1<%#YRd
z;WJ4kCLleS1^=Mv$voQ+uov@$o;lu(AAJZuOz<4pAVoOyGfnM}F%x3pX*RQwVgNZz
z`&9Ur%N(VP<~XxzKT3JbMo)0&Gk9Yq?%mAO5{Q#bBLmzi=Jkbe_%t(*Ztn%md#5P>
z<_z-#y$PU@8R`xES!N1t`4urEX_xH+Bd#7aNYTYK(e2ueJ=g-gJ3E!~ZFjMQpP<r%
z9pwaoC#%gt$%~Dm^gD0%$~AP<hduWfDt*}#beh7C-I@VSfA%MOZDs&_z)FGde;}(A
z(BB~T6FPwq%$6d=q=;fAY=bDSv8S>6R_x-=(s+AvA7lNg2;x>w1NUC;k2m0NI9IKK
z!3=H?qEP>h{)hRc_+!%F)iCnOdjU}WbSTZKKRb2|1{M_4p8S$YodB&hJ8OdKwjjC~
z9S^+s--qz?d34c-siZgG<uKn=U@!}r--rC~qZPIfM)OPVJe?+f#ks2Bmy=9K7ha&O
z*BaD8ve$N^bkHo1j@rbSjrk1Zv1U6rfG^H$Dn;H})I}9g=~Az_OZI!!>pn)~WA(Qe
zq54Ao@)ML?ZB|lX$=l{VN=XZ{v7m!*`)%^JqZDP+wF;UEHa}7}NTSW)H{eB*%}v_A
zPPR#=sCbHvJ56^F+4!tRuMXRkTm)IF%?dhtm}V0}`OfJ!vx6xA_^8b%tD%~2^U?#N
z(B}Mfu$9_mu7{`PHf`SmUuSdR1xV{{+7E-~x(!nX%?6u|ufu$!&4#5Ay*55Gp?TNF
zf>u%YY<{9h<9!=9Z<HR`JWhqdhc-nc(TPVkVYCVV*k;-5bpL;1^EGXy^x4=^*PhyF
zBVhiSjqW$-JhypDnQbp@_RfO&0h?r+Ccm`#^%elHY`TYl+sQUC55n2DlJ@ysY~3jV
z%ER`P_rc<6n?N6hm#yduoVRUaA6R^B7Ysrv$aX#@)|i5A=l_h3hS=^c$H%qX_Rb;L
z-D7Ls47NDiTlB)<B-^VW(U96Ylml_Z_WJ>tKWcm9H}o*ycKB^*HrReK9&L@b$wb<0
zdoU8B#rDgU5bd@THlf=$Y&lv!J+*za2bYeMW|07Uz9vn_S1{<OIavo0s)@IUrD#q4
z$M8E*bDMTT(=^3Bz#r30`U93uXu{^fr?Z*?+UP6OJfJkWs~UbRG;1{#eke6-A}H?I
zsTrVf_8raQWw855ljs9yo@+W|X`J|}We{GxX#(v|dGq@zisHjJQM|^Nx1orxA0I?X
zS^m5WJ;eg}fS=IqKt8epr64{c0V=_KZ5x~k;X`P@VK+ax5p8?;zTv>_<?X0v`}l{K
zf!oi2R))$rem1`J$OKwh1V92m&vb=4%8PW)B8lHdF@|LRUMpx)_^#D({}BJN1l7a*
z8_5u<d_B!z(s+A{SElpv2hg<)zLVlhNB9G@0?*_F2f?Q-e%n(RJjREFKr@@KrG2v;
zKJ_dBxqLEhQ6J~WdeV{XJYGi+*nIvsTC<<vZ&OE4@)xFn<`jQ|R+gvvxYYm_@FU-Z
z<{AF?J+M^BcV9&1S^gR&@D}l*K^T&9eti_WRKr{R4eBP|(FK4Ge*Ek3@HT&#lByo^
z50<0yIo~r~wis78?|%)d1N`{$z`x`pPNVS^A4tn&C*f=!xP66h%%S2Z)W?F`Uy$C1
zN`T;=3erH~hu6>+Bxvb|7a}ZL1D|#aa=(2x#f-t^(hB@RVXz$BF+x%_O0h!VO90~p
zEj>Qs1@k%}5`<5pU@%d*-Gfq+;Qb1kDS~4(N{56mQ()q-&^I1Kk}51qfTc7cn39Fk
zg~D6V%n-ia2ysNXM}g=(;Vd2H%@@K=ZNQ%r90#NJw4fzXCLH?)G#7-Vt1y2_(0>fz
zWx<h>7HWjlXXs(Au$hux>xIfB*u5^yI1EcSgqcQ=bqK%HG_F&4lj8PW!h}0exhZ6X
zpi8%e9WE$!3v){#dW7ro^!eTvGU+*eM+n#eM6bY`!O~sf<|KG=PxvGjrTfC*4%mGl
zc>N2She8a6rymOwe*oZ#kfp(J_X)2)MX6u-@jHm8!o;EI;WHub9vpoxd``K#FN9f?
zZZjaTG>3gDWGB=5_LZ=gro>L7{CfbM#nOY&aS;Pffz(xeL|3Vsc&h+yexh<PD*eUZ
zUct2haU5+92a5Ka!4@q3vVuNevFHh0+b#a{8XVmtrqePtMhv3}Sge>yDsf`yIh5kX
z{dWf8{+b{@*bCA`an@u2lf>cli6)B|YXD3U*U(E?4~eG((RNt;HwhwD?5%_|X`=E5
zTuT@2X|<anKEd4@nGE-%ppqq4jRogXv9lAUW8&y{P|6nnq_!MUw;dyzE4nTR&U9S-
zf}VqUVk!kQ^F`GqG@cMs?NNDBoOuvloDvsMQpss?BYmO;V$?Kvct#vdnXrZ8i@^X~
z5yytYe7VSPLR*FCatOFe(SdF>)#7RqDmCKw&rrG}4nK(D>J=^Cf_QEc`<>AELUd?`
z`2jIw9!$Ixx6VW5D{;0n5KdAp4^N$?%d`S;k@j}LuB&9Ar>UFdxf2H6rC~I|-6ehd
z9ojskts_9@DJki^f|s<<6L4=SCK4rI>0g@o_(|iHsPvai*$V*-kcQ0zcc4@^3XMV1
zkP>hQOV4P7GDI3jVW!<u%MSEukMurG)Avd{cB8aUn&AS{{Za@m^g^W<vr!o)MeGE3
zxOA4b<ddYLFjOW>kLhG!iZp03N{1xhfAEPMmSRlw7)_O=vB0NGT_<2SL#m{R`w?jh
zEkZLT;S#*al0qo?^r$qHmQm58k0Liro;mvVPB@b_`hD7C_I&5;4=_<X<|8Fcw2rYV
z1k1qq0E%9|9RF1!DuXBZ(`sh_gqd__3Y}1EOItwU6JpZ9c67pEI+Ry5p;rf;a}$DQ
zL+9dz6#AxjP1s43?xcz1u3ErT{QRn>OY*k^H^9E$Fbcna|I-3qY*=y=zqb|Bylng8
z0MPHaPAO+j%;s^Rb!I+kK*@!f8Vv<+#^m!FXndG_N;~vpVrc@phxza`aO`DV=)D{V
znAihgiDFEB)N|$ydgdlEUs9ManOWZmTneLFfuTCYeEU8~vls_DmVT6}p-bZgQ@9eP
zlgxPflAmIJtO4#cvygHqN|_5L+NLgJ3Tr`nfw@3uGA}Z}6r!=3$$T4ZHOvwURw6sY
z6DI1IB5zc-GIMD&r;Qml9ip9aJ_q;>=AW_XVF#1!4$e-diT3Kc7{?oEyUC;u!0s)k
zDG6=&nW9Iq@PNtNOZoi|nGF={dBhaZPTFH;k_M##rut(bUNU26V1QmRJ%`|h6FZNd
zz|QP8%35?`KdT3~D?5VH4c*v4VsU4!XnD1ZjilA62U{5l6;Jl#??LUw#(JQG-fVvi
zgb(XKjqZQGY$-hx{Me{&IPA}+kAVnapN2pLvh(PU7sU3{K724coMs0h>`WePyIDud
zOWwn-Q$S@eyNMD9_OY|pp>03gv;ZbT*;}8%(J*!bCAx>Rp&{@of(@d>W0CCF&*;B_
z9AG=&0Wg7$RzNk8-FODhq_dCdev-j9rvh<=z3>n!nXEURbj)KXccU_&4Wban33kwz
z;6BL?Sp&PL*q0Q^FJ=o@psj>m>krNIY%4{$O4+4b054;Io&(n|u$pZEm@cxl>EOQ3
z3Y6&3z}ozdQX~7zQUIISzrF&nmHo3Dz#FXJr$BVDjkFHyWTVHT7hSCDxAgh4ogcyb
zTX?wz0Nw0+YP9vRU02cO#EsbjfCu*l4;6oI@N2NJhnw~}DkDtXYp-B8miz5zm^j1@
zrhMJQT#h%)r*f{tAksKT$}>#od}zxsgByJg{XM}=YKDoE+>B>1c#7+I9j=|`7Ez{a
z0XOo$pdTmN!u(n8GkO*jar-DPagK{V4pGdt&~{)6XKMHr+~+yRdf=~d_b<bX>)iC$
zK-0$U3_#m0u5S}6?{RJ=K=g5K6oY%oO<D-RF4_7(c<&+mWDqJnW$#Tx$xCKl1{2=0
zi*yjkN0v%~E??O%U!k;L_6EK4CREl;_l+=Fj_Dp~!es?ZAR=V%M!;^QEaGeE9FSdE
z1z@x+k?s%&WfinB79;bcyy#fjh6fOFvH;4$i<iw(V@MNZ2ety2DXT!-N`74CN4Yr#
zvSDAqrxMxNXuvPaxHrIAC99@uyg~K{`(J!Prl8XTJ+g%s(77!;QwPKy+4CNhdS#Kc
zz`85@WfOXMPZlu<j^39A{t3VXS=u}pd@0MB12105>iePTBp((E*PP`!l&R{1ml?t}
zS9wnY0B-o_uHbZ+k554FJ@9X>==<j>H*`YPOFk?XY~FJJ*C2dwz7_~y`8b;J_{rB%
zSjJzzhfY@SliRsLWxsq&DN3Po>w_>6CeI{)!{r8F8cKNv1$-mr<7qMzCAYDLX0&|E
zuV6VS4{$>VW8__kRp9+jc<CLyiIbaIfhJyFT#ZtiJmea5(&Z~CmX;x3^(oqp$Ul&S
zEmPiP4v~eojl;xIc}5289+PjS1nwMpH?6aB<@0C>d0c*yHkk6{F)gs0FRz%6kvSp1
z;svsk@`j&KX*z}f+X9*r`R(U0cpmS_0HRbr=sI-D<cD`bT#!#(0dWy8fQH>ma*H~s
zT$a!O37_E=`Pd17UzMvU#!?~wo$?|p<<HN+?Q8Phd#J3E`=3OqT0TD)@EUo-SMax1
zK8<!->P+$(zk<6H`N|Moa`_mr-IV`Llk8jaZ*tL@Zuy(eXzP&&s=$3m-aQ@oUioi9
z(7Y?Rry1})d0rGM@5`&oq4_{=NpDelCGU4erITW>3mkP;9HAJii^9SW)UJwex1r5V
zVY)F9cz4CIK)C3km^c`!o{F`1!R@6OHw7hc#rO&UeH5491*xy%&kZQ~DMD$H8>Vnn
zfF@k=3r!p%6jL#ylt(IJ=xcaDQ8F8)D21MGh0%&$XH*_k?D2(%u?pz~sN)n9Obm+g
zitT^Ge1byw26ht_TWOarN%6-mjB~PLbr66lir_q`6e`+h;e$P^SVp(Wi;BF{@V-g$
z^&M0;E8=K2GN71x4R({vhQ@-d$n3QNm_KLsi$5wG%)YyX%4V}met>tIsqN_dci(J$
z4uJh;4#&Xu)a(ESn!L<6T?WG2{A1es-fccF73QPNi)qz%#Qg1-7=#n%3d(*cGT%qp
zjt%BZ=(G*q2N4cV59RO6(6(E7ktPT+N-J}8DMOh+A@pO)H4;=xmB&WV`I<82y>S5g
zsCwuCqQ7dyHk1NXF_hvOsG4~Pz+lxkqu_9eswo$3dsO%6(%Y+Yd;+(_RJZ?vX1GeQ
zhf0JhrW+~;RDFHuM3ich9Sp{*Z0JrJr@CSUE?!kYd&fztk1Z&_@sO%@6&ll2ORIrD
zqVn>C!&$1F1>ioa^4)~CY}MlZFp;C0{19!qs!R%LA6Es^SNwv?)(+y5s-J=%<*K2U
zXsc9h&Vq?5RRB#oYgEN1cu}W%X9ma`RKu^LvQ>4n7b+$f3pHg;xmg69M{$=$=g+X~
zX>n~mhTGpFX$w>XEruR|iQN{<#{j?AqTm5WHq^o_4hADE=G>?0Ab!Nrj`+P`BkdG@
z|1qWU{g6dBwuR^4#ovo+DAKfe`72<T>>G=}m*&P%e%Z1yd0<^$6$VQ`4xxqj3N?%0
zKRMIp<<B?m@q1;^TY#;~I|4UWPq4)AwRV(&we|iE^mdyEEw{Iuhk#*+-V=X2_Iv@(
zzvRg<{LhGY@%O(H?X;WBX*iu3iK1mL%+77}epy#0+z6x}bAZwX{25g}Gy|BQN23(T
zSkZZhP-fzLPzhuHm=E@F=Cjr4X*%=c4tSNrjG*}YX(pl&oho5=(=7N3W53(%f5Q^^
zCjN+GtFFOxG&`7H1$vNuMREBUw%4>D#$wsq)$lZlZKkPAGP|W0glX)QTG&iyEl;78
z!3J5P?HKF9p_I-3G!-I;-RuF8%gTQP{3QElAONS>PD(sI&Bjttt%&v70Q2YA>P*0k
z*%=q0d4UafhuMqlLJJcRSJ}7e`lw*PE`;lqtOZS)uCcFdp;N~OQL0=$yD9{w>+Dd<
zpKD>CF(_ePM6-@I)@dZ*?d%8t&4O8<bFh1h4WXcCH@h+r-M-6a6rl1Edomb+$L#4e
zz@M<qJ1D>7Is0fR>^gCUbZ2|0H2Pv3AFHe$(C!F+UNWZ>0e;1tpwV$+)pVlKnO*CG
zp180X!+>>VtB=8&8#|BQ9O}+S(-Ev)?5!cN=D|Lq)vG7_#Xi8j*n$|ed9xd7C&q_0
z`CkW{FIzShM*Y~Y=>h4_n(o110Q<E)bV6DF3A_zs+q2LX&d$n5TOw<^1xv~7%xcyD
zc`1g_I{5pAi=g|%KKk-5v}y)?Q6K|*i&Gz?e#ua0xUkf^4Ghb83QR0F#jk{qKklal
z)fKY80r;uoEqL_vS=y*tSw*YyRSC3zzdD~5rEAJ4{<-$yyP#M%;0n}+x+yTW*@L#Q
zx94D;BHt187V6!YetOG~JM&i{>UJ^r=Te`TSCe5ckcqwm^&sYblMOryW(H_Z8qQQx
z%5wzstQ{^#G8L!cLKKto2P$Kj5Hb_bgxf$QF#(TJd5H1*0`N5EZAz}Z!i=U{ZaLFN
zsTWrnQ#mYEFk2|`xsu8J6{T9{yH5dcWRB6As*PE_-vrssEa1@inE5atz-P>)2Iveh
zOWpz7D~9<5+|KOwp`eLkz5Gy_&30kk^nW*<OGf;0oOyE`FnP?b-{4k0llcOCCz$bi
zw4G#TO@KJXgeuUh)6Co`5EU?oXpLRUn3A7>zKrQE2L1w*Ko`eFW&v$*U1E+<<z<GU
zt=%ikD+&XYGc6PpXlF_&I(385&q1k!@$E%FdYKgzu)E8|&=~hKPIR|_%6L*_!-c(&
z120_J0-DRav3uz-i648#<Ou1{US0^h0qoEcsP1Qb!XQG~xXBpYFm`7xL@Yavk|N^R
zQM43^XMJgAlfcemVK<%KNVmrfcK!Rn9cLf6qB4)w<ib)uTT%e{3AUUT59iqF*HKx_
zj-XXx3ER4cp1<c=HXOjKY!!vWE7%)DfT(2a=$3blJx&XoMt1#0v^BBA6VcYpw)_Qr
z3p;fHZLRF0cQH=gEH-~>(G#de+ii9eg@^92>iH18>|R=W-DN9>0)CJEkzS2;pFRE;
zeg7Y@R<tqpkWD@V;3L+8a(o`M$Hsu|3G4V5T<c>eb;8kp_NU*`wWsV}noU1rGs{tW
z&K6Pr>kD?v3IGP!*JIJ<%T=@i5XK#(Y1Tomosv$HxKZTH5w3C%#5r!t&vd@Lj?1E$
z$Q|z77SuY+R{ROlNSWRa<CQL3`yreuka4t-yCPdU6Ye+3Dz<~|p)6u6#B<rSWB<Da
zl;ceq0M*MsQjwaxkn&|(<WFeZzg^CUfvHoTv;*|r@;eo<*(+aZqNJq<@*RFq?UP?#
z4yT{Vy@#XpO8%u1Y;KD74+o)R_z@V&uvpknSHNQFIvSVuQmAM75t>)8*qx2mbw6xC
zhkxzR;`f$fSI}*Zr0nEvn<>wA`@D~Ua$*F^J8@=ya;Ec*Ud#)c0eCasbiyH+srdu^
zA<Us-RE9I{Eht4W(sH!LF~xEK<C%1N1gA1%zlHN@jMdxFOlP)J3?+vNya#7;8Ihip
z$C=9AfaftQUjm-bsQLgn!Tjz6UrsXhIrM(FQ%uGV=$vNWc|}9bd|wQ4hEdV1ppc14
z0q`snv=H1yjNj+LpJP;%a9PasQzWm1`EVUH&ol4r25Bi1JQ<>lDPtfmFlK+j(Tj|h
zE}~0}MJUKFGapeP?+UZC5I9pg(^H4qt4s$a*i<m<YT!&g{Kn8-XVNI6r-50jhowel
z0?m?}m@!@OqM2Ed2$e48@ay2d$?RASm0L_>FyOeMQFO3}iCz!t+f1DnEO!_zP3R^e
zqdPzbyYnZIWt-RybR)@S7f}jB9_vWq^%Lx0K~ODV4GS@{XW85p=u9!|M=SnPwxk@u
zi|j56kX&KE?14%po4yi&dN$t`D($So1Fku7S-&b#iyv_u^)-T>z7-;p9hwK|0X7jt
zCfrja&p<nx4gV6R53-x-v}p|ca2If~tnUSQ7soE(U^AW_iKiXzI^Rr#l|<Hi9dJo(
z*EIl=*+Fz8PGMirJpB;sZ3)f8Y(Wz=Q`x38Xr{5+E|k()$rgq(*iDqYg!kLDY)4}z
z`+`3H9JXLFN(JogDA1f?=TXSFlvVFUTNyjD4$fR)Z?-_?B75lzjBynk_Xo^ZvyPN8
zUc+9@M5&g&b{4o6cHDoNkZc8=8E9iGD45gE+EQ5X2D^nq@*O7jj}Oq;$+~X@u#5fY
z0-U<Ze!3Vg-eTXQ&##-!p;&Pb8>+&v-DVfiP5KTS@D4P4*`i#u-DM{yLiDjiXnNbv
zew6}$pR$Ygz|u2TP0^I+Y{ElSzF<pApgF)koec4kHN^*`aTnMB8pg|myFxe30PX|2
zc?EL$i_pXU+-N;iLb-}oln!zh6x)g6&aVL=g;UW+<{>VH=FM5$x3u$el>4m{nkTrW
zUJxg_`4kpB#~EtSmtt=27*LmR)%&4Y&V`wbkXN~<v?Wl%MOVP7N=~9X={0VD4ce->
z*>otYnhOtt-5SoCUMo?{Eu&1zI&P^6D)n6YOgM9$+fK2<2Ck(WqLHiff@tERC}pLY
zOS%qt3pf5a$XdAt+fjLgtIjaNw+^m^7L}cx@hr@DalW6Szunw8njrOX>t3LAo6}u_
z<{ger0KS*gbVJ<dCj0>Lfcs-PxF2#w2cbE@y+LR5on(oW6YDI~K0}*}>=~)J%BE~V
zo14s*LbL9&s8o9Xc*+LottVcxs96{qU)lL?IO8WvqwHOO*;cv&17z*=%?XqVThNv)
z^PuGJEZMme0GyD$P2q(inIah~7iGnnsO*tl`-?tb`7d4Y!c(!EM#fjc(#pwS@!%9x
z_A2@t2jTk{rg%3Cwc!e-8!SaA%C^GANX6Jxhyx0rE|5kmI1vuVC^{*Y6{pCy1Zjfe
z981n9?t7v#MRC~%q=yvCC`5W#@kJ|esfzj{bUR(~F)cbW6uTNBjwtH!u8IG9pgdne
z<G-+ymgtKH%wTcx3VN5plE5YKerYFdrY`IJ5<1HpzQXS{Lnt$B?V>RJ{maxp@b@}h
z7j!nQnF#&Oiw1*d%S@UnY~8pIzqbwQfTiuZuK4}emY2|XV>;<-c4uzV6u^%$&Ha&v
zgekQGO#m|_4kD0w&<5{=n2RrQm4q@13Uh@qQS=QDXWpSZQUr6MgNBJY)&=SeX8%c8
z%VFMd2iZwRF%r15Oe!5DFJ($;{dI*&8jWG9Viwbzb*?jOXQ9-_SeZKEO%IdWh1w^~
zbQ%IDwwvZNL98?FE*@m9z5ai0Nwxzj0-1PM@CGpxC?p=r6i{+s7}HPFRLr2qK}0Zp
z6Jaxsv6%qPc&2|RL@G1xAF!t}zaw!TkISJnAIxAG?Y?{M_&;mkbV27VQ%zf-Ma;q5
z=+8xF2|Xh&F~N4ItY*q6v{u8^e++yxqdtsM3nTjz!_mqdqf~-6X4E{e9AZDyK;<y|
z)-AdS*b`IH*EDwGMQEn89<&n4U{}$5q>iv>EFd!3^`?K&nG0;(At0Jr`3M+{;_lFf
zYBXoF25kqqtjjPF!#&_&H<r8qHaZi>-K29M@to6}z$I|M(Y2e%?fMfcN!*VgpohsE
z=L~03xcRjI5+K|2CfWjJf6yW^NcI{%Sc7GsY%`&wA+nVeyWA}+JPN1w$ov+8d#~(=
zTvYCpMN@|IepyQ+Dnn)NlpG%>bNUu`!)0S=Ug53?o<qG?H2(>^X^KJvN?8hTnv-WM
za_N8E<tpNzqZ20-HAkRwN)b+Lq5?(5cFMCXRFrF=`b6>heyIAI{hk0zhs}z$s4Owl
z97n0lY|Bn~QDrt`^8e<1x7ZPs;Bki?aui<PXK&K;`!QQev52Q^E(Ml6xRh#o^5aLi
zKMe-IxPAyD^7U2;f6vOQfS0pFOq2mRC*@b5=jI*8pv>F46%F6))4|_wyW;^~a$qh<
zm%i#p>$2ZyS8w^|Tlo9Oq<GY?D5X<mKh6FYs9)!e#^1lyIl%hncNfC{Ey*#^`TK90
zb^h}M<$=31%aO>1b>TdE9(kCUE}Fi1GG?^E@?yq)57c2M;v@h^8CTj;%3}`GrdI*8
znSv|DOdcfyU1WMFY+S)4)A-afQ)rdg#P~I!)WQ5=j?!)B`%lr+$IPuF;0BlqHQHR+
zzupGUiyiXwe{&R!zmT*ZzE4dNFcQ;N(28=a%pCphV}wocqMvac0h;H`<VhfX!5m8i
z{uT3#PVG3c{$HWemDLN-bYsoRz~sSh`Wu!!*>%lO31QRHLA;w~>0LglZ1^gaPO{GJ
zgZ}$yOqfdL(5nP$**ZUP)UkV7z*x`9>A>H0_Wi{`HL#ceUoTg}6vYvRnV#JN(bd)9
zNk#As9<aLuE{CQf0>S%Oz$03&v&%wO7j|Vq%9GM)FlthfsLxUquu>)-rBN}HcmSd%
zYCI^^qRO)XgNb51P*L&7*O<y5$T3^9Z{F+ozV~`+cDnm@_ww{`13Uf!G;gyN1Hs*4
zuXxjRmpyD<y}<7C;qrZE<QbCZnCb%j3l_(-uB*h)T0p)KeSQFRf!J*>>bOqq`YAl*
ztru0)>uql>n)k1ogo<1sJr=I;ZtfGo&4+4Fg@$#gTC-s0S(#_Tp=bzEZCh)#oeSY}
z4cl)9?&qwG_iNX)v~rklU{!pqM64$l7O~fSeyNx_Gr*Ow_(ePqx{cK|LUkwG7zy{g
zSm6*@>}DBT5OXPe*#b`o*~SKNM_D;<CCb?RXYlkB)9@t^KeL)#+@lNZ^&4<itf@UT
zudoAspm~**Tm{%QR_288I-55Pb~o57zH{OxE5#qg=ApNChp)1%WmOm9zK&h&3R2Hb
z@@c(CEKGs>CN{ki<T1O>yB$y1okBQ#%0_pC@EP;t(-AM2FMrv#upr((d?L=|i&vJ5
zRlT56Ebgv>`(0uOzCNv7+{@Sb*N7vU0hV`D%=ryE_rzpAs(T{Nn}otw;+}I*U7=|y
zLNKK9i~#5^P3b6bWg7b_XkO3+G$8DH&F<~cY}WJ$0NQG;m%p^uYq#G9w^{pUEn?cH
zy~o!Xf2(!QgRoFa=V_9y(ovpgF3OW^JX>EZU3h_8vqQQ!2GU*9*+7upQXqf#?UCN)
zOY`?hjL%PfFPWwx3RMcU!{A4$0j-qwu$0&X21lg6p$M%^s<;h@6;eCi@jWIL^GEr(
zw7NUYPe=zl!tSJW$O7SMDX*ps7U!ffeDB_Q$uS+lT##-rf&E44X31Y~yTq+UxZ@+;
zd@w$0PzZEJ@04IaCOQd{vDK>(!?<ex10Mg?CYVl``~amB3(mu8((yfr*YYJEacxrG
z3)DS%2ahs^4FXQy<YlW7)|3!Fu|2hUIaH^uya<Sof(}4+dQCc@XLN5s>CE|^5TkXm
zFMwt_??9rM`A$dM@Ws%ym+?JZsnxfD;1GD0C{52>{`7~%xc)d`Eac94I%v-J48irB
zWJ0NHs=Ng;W~6UGLFSH45V`G%0QFq2$8DOs=LSN_3VeiXZ*2(VxwrTVm4z*QU(r(G
z_XJdArSLo&7!^WW<UxGOkp9IF-IvbY6=H@PQoN2VufeWlx!hhuyxX3W;mFMP8Z1+i
zM;g2y#qO|XJCqDVT<rMJI3+99I?kP%<8oM&+-cdlN|uAZYZOAr(I|BOSD=cb46z=M
z%V}4#o$gGpAt`xWxEz;bbBu~l2va;BL!3J^yEVWByUXeEIt(6HPP!ACwB(+U5S*dd
z-ClEq)fC1*vQZ8<Mw`M-X4!1WcDr3(QXU9BhdVRvuAEed&wuQz>JOpoe_bE==tAZ9
zg*N|(BenQ}u)Ut1<Z1$FU7D^x*)Op<w5)fVE)?{uRw9Q#3igJH{^B_A9QE8K7PWv1
z>->7FaTCN8FTK;ZZAkv*N)e|9r&hgODeWDQzo}7DH#PdQr=2ayan>m*$rk=)o#^%k
zhZs`^<R7i`Q;*iQdA^Pkmq{ITNtU>`WwM+yKs}x7Kg&WP19k7Kt~37MOjC#UZTm~Y
zhyV1kHpDw@Iq9SvW&u>*k4b9K?6xnPJB>_AuuhI0o01S5Wo$iC)E>5W?N6zWfx5t9
zl(b6Qjp`euE~H<p^&{&Ue;r-k%(|#mX}W$3{i02BsL5<J(yLnC6xC9vtMCgp*=>qh
zNi{1*V`P*`R*VsHWRzXD53!qUve_J&FW=SSY_H09JD5iZgUK1H&t;`eR2Qlr&yF;a
z9Ht*Htf8f0`U&ishN?NMp<V|41fd<x<s_btak7Xy8bJz40b!V%+;4<xDhVdewjqlN
zfRFuY8z__?LM(huu`(~!QGtxoMjh30`nWyG;m~r?(s1s!H&wr7dqse~b%3%WTA`1D
z6#}T^5Rm1ha1u}ZKv=0iF*9`9(IhjZ*;K;GV0s9`8avR4NVqxMi3&i42&#>Q_(W%t
zqgrv7Mu9yWNY$K;pkC3iO{KXY>_`w*MngK5I>vy#6->4mKwauX`(yM2S*0)Ch|%}f
z<~IpGPf0se-$z(X1BU9~W5;UAGF0E6J*%Y!pu$Khfw<d@etIADasNKh6KXyF1UTjL
A^Z)<=

delta 126956
zcmYhj2Ut|c_dd?udiUP#eKoPhL}QKJ*fqu$HAYQLEYTQStVz^pG%g4#2qH*V5JW&h
z5JaUnyC4E00*ZhFB25t+pa{SB@cI6q=kMclXXng0?|WwU-nlbp&f?iT>2dQUw;s&*
zCwmI49-j(rdXB4=+9c&LHviv0hLKba<ZT#+t?w$cVFcpn?LrjNYZq7>MkKENNQJcF
zD}fEeif1IC#!7b;No|B8@%qi%sI68?LJ?ob*ofBll-k%ZpV{#I1YW4Lu@PvPK1v-v
zc2%l9f&@QWw+a{=p-wC|wOtY02)jwdMvwXU@TnAbHa0>J0V~%3xkO?k>?#u*dmMxE
zr`-RV92ow8AHo>9xQA0Sbb2ZNCy^<|+^1cHHbS{dED=j(HbPb{HmdsbHo{LdohqXL
zyLxOFcJEU4tI$RyoT&f*wFrY5gSg9Dk8{HAa;X=O=F^N>++E@EK)9Ki>oG$#iuuFC
zRy2f3@;EQjTi11nZNxTn_lR)aSSrD_cMXH<ymXTM^NRr2`1c&Ht3KG^n%Y1*kK3s=
z_%7K-TdCFccanEK&EooJ29N8Wbh^6!L09J>(oft-*W6l?c)HW)-PXxu;7}yQH86r2
zI-Ch^<99^%Tu21WIBLxwO_E<fl0$b>=^8wV^!J}3gpmnkHF_&a>@1`o{EFn2Yv^<P
zIr`jlDj~ER$#&&$r1|X;D|x{ek?-EkL{{~HRI@rrwf|<4Say-BZUT);$aNX6#~cZw
zw1hN$vPs7{w$rUC^x5_{QO0i}{Z;jZzx7LM^$euXR|nDc%_`Da6d<so2pmK7K{E+%
z`a2?Cvsa4in*((H@&!q>&SbV`6q)(PlSFcm+}gRCY}feH=aDPOxy@6kHFG=J26PU4
zb{l=ZJ&|<2UqJ{OC%TTj$=O)NHpyk=>F#t=3Oz?kCNq(BtDx&~CAAK0CeW16$;^6~
z9PM|6`fBP)@}gHX_?zmfmrXs$2~~e;&3sCd(ML#U*&)Jb6A1H@o+MA&2^_19-F-56
zlTFPN<B32qh$Ow5h^AmVeXje52ztbl@#}KxaoZ2%X#DTgy7+U_Y|zs6co1poJHM2g
zxrCPg6}i$nkGgR-hxBisB>As(<d*fXLNX{`PYwUNkY5L{Qv?5$lrno0jn8blCfAZ=
z_GbFLOG9wmvq-;77jme)foPKbN%BJ;>GVHAI!&El>&DJuPj({7%8k@j?jWI+TH`w5
zP7_4y59Gwd^CW4RL2k9aAj$U5$EHgleO^6;Aow(L@%LbYs0t_I`Y-9TXb|D-m(xi2
z)9~6D|E6oePjroaMVjwB<)=Cw^)g!tuD_PZ;%<=dS-JE%A(wpoqq85sejuI6ONl;2
zMKt-T1Y|r)nk!<cbynw7)6JLMvdyKdHkn+x(m6LQdrzMqbtlbLkLWY!NjjPCQo8>y
zXo&b#Ai+)FK+Ok-lE2yK$qCme`qmdtBFg^NMBmu?{ducMXWD!MDm_Y{YgW>Ac@NTA
z<3rcX%Y=5}S3=(5LkKTBpNJLtG{%#E7t;M-uIw~eMXD8tN!4!!sSf;yB*%LZXp4p<
zA5_$O{a<n@YX(8+UeV`)_4HZUPMRlb2+eB%eRdR)etPF4dj1~Czj#WT8|vuVi^kGw
z<J&+=oGppCGNKtag8DsNK$10?WR_b_L$}O@S`YUn=$Yx{+&KmHzEVt@7hULc+-;J3
zJSNQU|C>*n=<{VMAvo`%k?!YC_&!DS+1eK`8+@a8$at+Usa7qa&&*3|ZVMwy?{ReP
zdw^($?;!b%FNkLA8@eZ6&nHQL9bLVa5}K18UBC4t{Z(p`UrizU?9Q+9i%~@1-bmfZ
zv)U5G<}M^k`-Mc)4iWu#ekAb<A<21HqCb&Olx;GCei=ut9x`fex<&*a=F!z>2I(l4
zk<N(>q8wF4IvZT+nqE%GEppPS@h9HJDl1h&)#T}n8=bv*K%b)`$#|HIu6eCQFUg_n
zZaZqV-9qCuBa1$Nd5!LXeRD~(WD&VF&XF+J_8^_~Oww6rOFFw+NdE66a_*O{)LL_j
zqx=8ZZSt<chLn!nCy1JA`W$|lC@cGr*@=Ise`B*rF6>A8=Tt=b^FAUt*^6|npV4*R
zRBD~|E%kNgBC={(L-Jky$+pin!t|d*lAPrdy8rhy5m22kiDvypW}AK_RptsAe>I*w
z9o$NvV@43!;XTxYYERN{UruAz*o`Qeo%H#a&Kc!tB;kn05l%l_!uRNWUi`A?bDuD>
zU9tmKR-4iu1bQZt2o8*->s$pX?LSRd(M-C|iXnnyBMC0Bl<1G?Nz>;C0{X3q<U4oM
zb?6u(p0$vAxw?%$OIOf{hCe5(>7DcAjw-VK7(kfT>Cps{6HNx&5~;85Nz^<ok%;Gc
zl3e|ffJ&Yc!LSZ8i~gEG$E+uP$G=Gb{V$}yrgH^Q5<~jy_ml16=X4DalIFwT$cd3z
zgj4i0S=CubQiF62!L1R{0B%}F#^<+?<W}cPcIqG+q4_gO9-Kti@t+W=vhxKK+_{9Y
z8AmvSGUz(pnP^%%U$ymf=(F`N>STj0*^b^z^nHILgw5-$1ii0wb~_}nv60x!Fp;Em
zROe@v2$GtuEUuIA%}HzyMUY!^cOgE{KhNQ+*Gh36G@p7u)tAPm*n{*7hZBK&=gLYR
zMZ_u31dy8_Q72;x$%!tlnExd<`Ar0xy@PxVsHe~VYPxO}lImC^K}X4nCU_n7#@9re
zOFj^R-+c+>2cM9>T`_%rG@3N^OUT8<Ipnl@06Cg4o>~uh(+E}7;eobEz-kK5|Hu=h
zdTIrIA7hh<Ag^;RYwAK?hhZ+0*o@yy^4L*i+`S83Ti?<MZFx$r?8dz<vAKlRu*8P@
zjwti}$!Z%WX^D;e9`$?WFzWHF&b#4c2qE8Ef{s~j_IBR+vyalS9}DNH#YQYsM1fFw
zaT5kqwNMP#)IPLA(smmy`k#hHw-%%Gxjj|C?9`ho{1=}W)}4gjqB-x-`Xg(P&p#bG
z1nk9o76RqxiJ!pvUw)xmc2%)Gi|2psP<k6}{f+K{e@bb2ZN2g-B=(H|6gcR@G+amF
z%{0=w#E1E!5&iIG)?Y`>kJ-2##WCi;8kiktIu?U8fT?}~))UOMkr<mm=I$w&2Qgcw
zf%qgd@jf(znfWW=>M3T!0lNP}nD;ECp-dPH>@ddG4#jC^F})wpFgNA^Eu2|D6xb2W
z%5PwBmQn1+z(g{qtAQQG?4jxX9J4POpwY~bWC&xJ`cF|i&-l@cGL{+d4D$<2FCJ|d
znZI2DeTf-fLF?~0Mx})`o>@gxc>*)Z9cYQn{BYEgm;={9pUhapV4uRAj({+g`HAM?
zG{$fY&ZIMv5AZ&NSw$1pWyb$3G_NqL0ziM2$){WYE)zq%`OJT#!F!MCu?%Bfz+`w!
zG5+_NZW*vBWG<(|(+AAnpMd?4X}Jo+5=KY!-y>$+02EJ{>;@24GPBiydCDv}1cPTx
z5WRJ3nAamPzzxjzr(pM-;b_g@$aK*D<0Z4~1G?12IIM&4731?B#cL+K613Jg%-du%
zzGeQM2I)H{<_B0bGqRVcwJ^QDfT!=7{Ffm7z}UY*N86ZF$!P0f82Wzg1aY+9+9%j?
z6dpPYPIPeK$N$f@G|vnVoeq=D0-Bq*oVWy{t)a6)`=@m?KL6Eik`-HJQtvgYA5;dv
zp$*&+kK?$0H2`yvcxX%ykPQ>ji!6xgj$Iz9OGHj#pc8+n!viMi;{Yt_$5*odL5WWF
z!AMB{qoupFygS%f+bBq6KT8lRAhMpb@a7ZuZNrRemDn>p-SiHO5ibgfBeNp~U3OwR
zdSVtk#QcPvzu1{6>Wydn1d~aN;6SFN94gJsuqkl)Ba=vr%>9DHze4kn;Oulb<0WvV
z1(lyb6Np-%;AdBO8!hO!7Ix`^S_jzO7Bs)Zt{v}RJmHmF(9q?lP0;F@wh(ZGbq66I
zzfb_p1%5-}-zI)5t}cv80vE!VNvolo!c5$aPUbL!FJc0E!_*)9zrp85EdikVBVHns
z{w{YhU;~!n<suo_ya#j9pxFOd8^K_Tc}T278pon*U;R^oX=~_c9^*9ZeL0*SUg?j4
zAK|eOevH&zfghthBk)a+u1Ujn%x+rVd|g6IpsCL=35jQ^j=`}X7(3`M8}%7<)`d+2
z&YypOf!3YlwUFB}lMbVEj!f!b!1iE1Yo+y%593SEeK0d!j3SDul>#)5nZ6iqCorAf
zCo-MxCo!G=Co`QLNMSmAkjjwPk}FJSN3Jr|lg@9MyG(BgLvtanmQCbK*OTG!y656V
zc-klOKaA%W)<NAckOQ|b!u6|OM`1ba_W<hP&<${Ae0??~6XX7XN8kLj48G4Sq>a|x
zOcCG~JliY$AC+lt9w0xRJ^<C;dGt!}w`mWqBYF=8`NaM=AfG9v?dyVSdLnI^AX<;x
zF?m)`0PSOrEJM|o$$kfLKgM(bt{r3M(yAbs`M4Vxr<ftHVHm=U!b=WwT?5%gGhe<2
zZw#|R36%s!R0Z=yCiE;clNd(|1YBbl?1I5{W?dXKZ!m&0=t==IeF0SNGe70iYORo2
zGYIz8Oe<|6o-v<LXKENPB~;%rTdu>tnfba82wRxB4iFv?gms1HK|#%X5IPDX^bmRr
zWS^k$5p3`Rn6F^@J$N4`_&XS2rv)RnpzVwxbrJ011h%`N5-(V=U4-vHK@drM#Tx>?
z4=ip9{%AvEu3%ONiXuU;&mb%n4506<Oi)So6@s-FF}T%&o_Gg~>jl3lF<kEis=v?|
zTjAa<0NXF@qJV*mu=)@*4-4PqL&aA(wgi}dLZ@EP3=zJ;$XLap!p7OKI4}J27MNm%
zBi8}+vT*qv*k2J|#Nxm6Zt9Wx4UBrL8&LhMWFY$8XW354|JtTJa6^4+ga^33X{IH_
zbWH`WYwMW*yBE7u{e=Ga+r0{)1CBqyb@1dbaUE(s(GwUWUiE-~qc36AARZgF9+C-%
zo?*Nvmwg9^zp>c@)$b%CTo-o1OIy7325s<upY{%|8_nO~x`lfMgug<H(T8NozYEZ#
z6iK5aNK+-tXQSzw#6%s-lEjP9mM>|r2iF6MwVwh=+0vL_q54{yHV!&=vWXq&tGlfC
zRH$B5E=qwgSy|8wW_NYQ52$&nH(&a{d;c6$+z7|;;&K5}DYF`}S8*Bh1TQzdu?`v`
ztYD`2<9@4TBEnF33es+Z%u8@TlGYzSf?Qf?`3i<7pg1Pj(E-Pf3zRe>0fK4oP@E7L
zuL34Wu=+>TP70K?2tFmaH60xf5lnW4mzM<ZV^G8iCaa-&SJ3VSFY*PyXTs+Kfh}!j
z?+dowhh33Cj(xwlSn!-;cGic2Q?wl}5xCGDS}K?wi>{Xm4i`f8v7m*bcuxc$pQBbO
zn7RR=Re~NACao5Dx1cl61otOHSSzUh188-E8I?e35Og03gXe+^A%M0O7Vbrxop448
z3VUHI4UmJd`(k*1z$$Ef0dEcpzo*6g8DWM3(s1GBwXn|@_Dn$So^Sx-#^U=zuW}F;
z3g@4LuvoZ~HlYuMdns;FBDALs`6HpruPDldFIU67T-c9huL@!7atuPHFzqyIPlX!?
z!LC}kDg|IQLaTcLs<pywdMnop&uj&DgYYrYzYs2=kV&I($Oou433(%6UJ30fI`>96
zu|I@wg(E#sYZltSMb}z{ed(?6Uif7x>^=xDQGY)Q`zxT?E__LEH#^a^M09tbsB{yA
z`$cc8t*|&C`YaTLj-t9kbks?-VH0}cEK;5Yp^GRAkD1t2WY-3?Bch52FmxB$ABW~q
zk#;xeJw<!f(DV{TjYpf0DB&v<z9Q}i7#tV*UVw_f$dzJyCq(H*@FGxDXn?^<(bRG)
z8iPfZxS7SFqG4|EB21J=qkcv-bSGR37Zo3X#aYq239yJ1d5uKvoTyKCphb($y1|R{
zBGE+H#fm0Rgz%y${yuJjOQN0kVUQsD>o+))D6;(uV96q%D43^+B)y=LCaP7lnE%p6
zcW4iKS=1X_2k{k=+f7(p6P=gAi|ZmsT7lgZeU%U4Ezx(^pqV8aZ-(2qMO|1FcSN5|
zgi4Oc3CA4bJkg&MfpS;0)f3L#6IB#Ir9hN>7ac4V6^{W*k;vHqg9jpuH+F{NhoVn|
zAbli?t3XjIn&}9ba#3bGy7pL9O*_y^QNbO+REcibqo@|m9|DzUq7@H7Q7f9)7s5Kx
znTIHzi>&>@^g`5iD~9By=!Oa?O`@g$0s6IQ;zxM@Ms&6mZSO>1xWT~MEc$#K&{{?O
zH&A^qI&lY}ZK63FF<u`<BThlbR^0Rg_IBcX&tPaTw)+Jz4&q;W!nFh9y6-WT2gQj7
z@H&YPOJR3Nyjcbm7jdl&nuo>HmxAGl*y|w}+{BIa;2jn3pADghRs3lZbiBoq8KCeH
z2Umg6PrQlN;>W~(Q-JL+p8XkA1H_}fU>_(hxq<->5|@vHO0ZZ(Cnu-G_W5)Ni4XX}
zAWXb42DNap*Gw=)h-+xS8YvD5g=Um^RXRM37Wbu%L5$cMEr;}iI1Xo7;)~)h=xrG%
z9#H_8c=4Jt@Ft1}QFJ&-obf$)Q^fD@K_yk3y94&=;@Lhh&k(=ygRn^4;e}eUSV^0e
z5^?q<*gX<U-@utNal&l0m5Z(CAbcX87zXnS@%L6bL#Yz~%wW8pikCiv&NFdbZ#YvU
z)?~p`TS?1h6n2tX6CkvgME?Pw93)A!;Xfexf^MjTl8^NEaFX=61*Suiw(o#_Sn@4J
z&s-(q&q3%eSw(NPqZ03{Ao7yjV`1PeX}6{4&sVas7z5=e*?k#0$0c1j!1zmMXTUH|
zGHX0)cO{R1fo6eZP9<vhC2M|yPeqbmV_{G%NpwQ(p=2_JrAs89L!enI;Rm8tCRsNQ
z{yvt3N>F<u`LF;*rR25_&{Yyu1jV1LC7Q_qeI}W>8a=F)43372b&|(hVAvp8wiv3<
zC4(}-^itwT@8Bj09}Ac_61yzey_IZ=g=UMS>mTr<Rl+x-txfV`J$m?2(qjV5J0#aB
z*kmhx_ZkfQq|0;BW-oPVq5a=EX(>sgr6b;e;=HtGDkx&5fA|6IqEvMW1AIw3kj_)$
zr8A3AOOOs@!J8!geg|NZrGIvVFjZQdj#`@3{|B^XNOx1T;Ig!eR<2j2O$(uNP3l1b
z^&3*(VhC?amr=aankkJq3EnJe0nMn{(oCG7itk9R6u!xozM$BDo^&z2I`XA)Q&77n
zeN8vweQDST6opb(TKyMGm*dP-{6MM~V(?0&_V3{RBk59F*p*2KCZPA_(nCMPwI|ZW
z--5S7>hv6ZPy0yMIHFoD^@{{dtu*s44ZhT#&K;ji56pt_g|v&uS3ULCvlKacC%y3v
zWUbQQ?V<5r8c(6ykJ9<{ythjSe*;=u_Rtsz?bz=qm~YSasfA|_?22%(A7Fn<L2;0E
z`5XpLtYa=bJH)o{1Eve>vki8K+3lB69AP7!py|fW-3{}j>}BgYSa`7aGEjK2$L%p9
z-fTk>e7eGF=t;ZEvQtppU?aCdc#|!n7;hGv@+<mzn~lE)raNr!*8t67_ew#S$431K
z;axU&8o=(ck+cgeU|0J9rHI{22WG`=5}hzSWG%lTQY9{7r@Dc@j9q<-MwI>VC2AF{
zj@FHp?0CX{%5JJgTQ%#qANDn@%_Lygvb$;0t7pG_iq15!krD9l1>1vygN<y_5U4b<
zgXW=l#agS;_J*DC9NxcWtENNP!b;p}rQXUe-vGi7tX(3UYGd#B16l`rcOwd08BYtt
zeX{E}QL~pB765y{>?$25ACNWNM&T$+2|_2FWS{;GXPjkAUW39#_PPp=y2@6&!~BTM
zWhpe>W!Da%c2t&h3@Bc*23rPCinna(b@2MiW=BHDPj-N|9sV-cM4$!8R^WtP93=ab
z)(0nL7xPg&C5yE~XF_EC3gC8_?8JC5ot9mvP(`@xC*qBemGy-ek+M8ml|{*(awwu@
z51&C8BTJxJ@`B81EWEH@lwJB6*m1HQbtvLxC)S}eg|h46fO#OhL<cnwWrwc9{*lb>
z9EwueKMTNHE*m}=jy{%6!WLXyDa#oGyDC|1Jlw99HT(m+XEM_~VAjfd(A%$0);<Bk
z=dzbWpz=btAR4tMt1K0PSn(^F(@ogFk*%b&j<>Q@+F>-ynrl(C$TGe~*FMNb6MdWP
zho$I6yR146pdGTEF)+8|1|A05KJKerU^{T%snE8cn?#2U2f1G|pyJ3434`4sF8m=h
zojLwBR1S028*~S{avSMj)Q!_^29rCt#}<tqoZELW^yGq<z|fofN&^)iuGSw0v0UGU
z5MJP3)BJRai_FAu#c@w5T9UvG+z2lcxn1<cBy%-Fw54zZ5wH-aan~q}oz7Jcg!yI8
z-|7vfE1cH`RIhPr9W1VMPLrW}lbb~$`&-<=7w{>IyF_7@+uXMcQOn`NZUQuy^QMF3
zeD1&owB6%sXs>sldq-y|h1|BmU@GRuoA4bx;Qn0>h7wMvh2|q}LnTzoxfk6KsS!Ws
z7SO4C1?Nax)k<y(oku?9rqI%*np;?hqJ}%T0>WBu$w9!>bKl27*udRG@LT+X8!;C{
z(#UQ50botsjx%U`#qFfX$s6uM1DM`&?uc27Tevny6s?@|Fz|ig<}?WL{Izj4v?6Hd
zo<4>}2lu-UOm_UL6bSe6L0Y(fjE|%J$Z`JD>97yr*ZcvM6MO}|%7b{r*YM&bzdHu>
zr}%BOrVQboY*B>q%Y-OS^BWVP63#1np%%dlzXMn#FCQns^B2W`odc$5e)|=m#qia%
zkB#Mj;=pu)cc)$8CH~}CsKoIvdVx2AuepT&Ci2}L;cH6fo$^tn@ZC;8n9k4n3Yr;w
zGVR;0@U;}}y~@XUp>~7Mh{4F*<ReKlleb*}K5G`gkkUc2`GVD`-r*|(P|M{{WulhH
z-=Nn>KHu*pK=1Lp>ASzrk8*>3A%CC*ZN>b`eW*R)_kIey5`GT7pdaxmjp%O~Kb^wM
z<$Tu*uzSLP^$5;X@Np{uUBwSQ2DhJD`GvXAdB$(2+pC5@YJ`0qucl+#dj3KbijREQ
zX`t<wZ~q;|QTakzQ+mknyTB(;c?P9<c*zG>pzxNTehZ<G{1OG5edW_LVc;jP)r0W3
z{47N~{pG{7@FGC|h9<TXa_d0a^#;nfkvBo|KEq*nQr`L*YQgf~(!dldZ)|}@n4B}h
z!*KbYAfQFa=Y0oZw){24kM78a(EOSsH_>C5E4R`#n<t+>48>h}@Ou>b^5lO}+>@Us
zy8`*QCKUJOzSfH<3*~o_x+E@=@1Q8<WBKQF9Q#Cmw;H{#lAF$=sFBBu;aaUcmCm~B
z<RkW=sF%l3e78Y<o({jB%ja&BfCK+~9H8K9uPaYr(tAlU2KckG6iE7{=b;au|Mwfb
z{o?dzkX!p!(GAnD#Tj^CvJ~s@pOFEj0sql%YTzx(9~g9!MtAVAF>rFoF$VfywNC}a
zP<bIhhs_`-hL4{Ns}XaiKz}5gfewtC&;Wwb`#d2Tle!vcU+=w$>)2})gBn-94`}19
z4ipxhXwAlT(lxphC%+4U(i9^F^{1)_fcTr8K5%RH%L$M#wz-YZYa8j%a_7}sAlS!r
zq3QWBv)zK)F{W7ywLoV24?qlIZf}AxoGGNQ@EjAIBZW2oACmSu0ySr;HHqd?7wO(R
zpgt^pN$Uw$>2`Yg9g!N`(B>x1r1*%tbRtE`j!K_ThD#pOJ+vwCl+L9Xp_la8ZV0`l
z6-H?KNbfYD@RjcM1L<*T7d0^brQL==7%1IBtF|EN(KqP*Nofx&oh1cJjhlfMD($ub
z7Gcr_d*Rz@sdFUS&PbQeL0h=AhK{--q;FQhi?h;otHB#7P45cOD5*q%;+%9korgqA
z*U}L}j5Od+2+vDX+MyXM{eBsQ7o^ifV7Msl!=tz)o#H|}g*fRnT5H5h@6etmL7GBu
zs6=T41>2IO%D>=DvUGwE{7#W>c7ac+(($QiOOqBfqe#a}6v8Xg2{cYurC}O4dQGal
zjkfF3<C7q~A$6JrhMQ8IKb*l^q6xH_(p!PFQ@Ab78wHAN>1sNWy(5jdj#1B%#t(pf
zuC(hz80JaGC;)R;x?wC-@}+Mmo#wuDC4m-7?I{*rBrSACQ7pZSSrtp>5Xy#nD2@LN
znkCZTDT4Dzx>EwoQt1~&UnU&`6f0KHH}_yjA4?6x(TgY2?l_ddLfVtQ`$}m`Ibf=!
zH!0@#R9d$PU8|Pf?+M;#(x2%(yheJCcx$DX5&>E#ZKW+-y;S%Y>>8x0qtW(UT5Ce>
zg>>s<&^Jnhy->WArd<Y~wMlxD!uGGEf(h{AwbVe{+Beb&%1U`FExQ83chX~&9@s4H
z)e9=`rR^0cK1lnfqpe*!-Vd4`(!}QgwPiPT?&(?P37px_IugY}HqrxyBP(N|d5A4o
z4RdGq+zY6<SlN-M(0G{jr2|e^_E#F&BdmWuYHsY?)c|#8tDR6g%C2od&4b<b1oob6
z3GFAn*twff^I?Cbu!Ap~Nv`>^Bd&t!B)jH!6v6Ba4>)>?okYv85H`930~E?u(sUTc
zT3dLG>}l5P9dypHu`0lXvn@0aMX=3ZLU@)v6%C&vS^o@ZMzI&ous_EJ{son2c9amp
z7}kLT@aI|I?;(t3$0Wh-0=slPY8TlB8-aO=EvKDE96N<FrQ+F*6wydvL##4%Es<S&
z3Z5phdtO5|nXR7+VG64n3Hwx5O)JARHscK1(phhcC}yw^qEWld?xK0<3cHa~@~*NI
z_M`0@>)991++h2U0On0rJsDuP*owcQlF9DESsS)5ODXJqn++|r;;G7JhYteU9o9S?
zggI<Caxs^E`YVKaY~Ty1+-3FOf+?Tfa0uA<*jbfODPX(L1n7PCVJ{SgZ0dJVDPrem
z1G|_luY}zLwwU5T4_Ob&dMsgwE(GQywkO>zrR??fbW&8tR?{l1oJ}`?{xO?JJEbRV
za{^#0*!R6*U&($>!L%y&)plq;WyK0;R<k^<c%HG%6n?8=mvn_@E&H4jT<X}pm%vod
ze$g9k4eWokad^(^?t%9O`*H-#8(H_4NCOqWWb0`?(!@5#z~U7<W+^~lv(r5;57zgW
zQ5uGitYZ(Fj>#UrMJJBSJn4MQUsgsz;Q*O4O>8G*Q;rVNTie&dg<#ntI`TRtTbv3{
zLS&!xM-eJBuRswd`+6OU)3T$h@I9Q79W=r?Ty~G9?+Do{dXmq|a!#S`oUH5!ifCCe
zoleHc{12dZUiNSmRAOZld!q*zWHmIMU6kqFz;{U|w$1}goNPWF3dPGTS0PQ1C0vCt
zQT7?l1WB@c_3$uR7D!8j6j?DXUQ%Vv>)}(HOh`Ek>9UbUFwc-p9);qvY#7b=S7aL_
zpm|kxdm4&svYu&h=DKVjy^3$h@>&3WQ`UV7j(x?qWDnzEm?_JaV0f}*(hC@~+p@<r
zn`X;y(d+q+Y)K?Eb7TuCFCtgAj6$P%GMgyC+?DMagRd%I=C>Hw_hcCq3NDa&P{`rF
zEP>8g3uXS4X;dWh83@c`*`n^yd?5RB9ZlvBW$o(#QzAP$3(`k24|nvbRJMaUS|+Qb
zl|{L1-3|EkST>H1VV=n99pF=ytbRVwp2}QlUZ|G6p{U|BnVI@qBYSoMD7CUtbD&Zu
zON@qHy=)A{HX39Jk5PLrYenqXif!Gl0WfTot))!2m$H98z@kZJPDh_!$-I-H`dao0
zB@n)m-JxTvw=w~}G~daF`~YFIY}Tg$ZIL;RMy*x$oeE?4Uglwd7awHtzoD&7)@>Yy
z<fCj{7R=jal^PIr$RZZQL#r*Pp)H>sH{Bng`?!K|NbR}LX-n?F1^PgBKj+{I&;#7m
z1%NroZ3>2_Blk8I-FD(8oQCEh&c7B+&RiVb5H8%-H5kgn+<aFMx^lOYU~q)1I}UR<
z?t40Za_8<`gxygq_k0diJ-FX!!R^h}tOAn{7r6_KzTDXPsQGdJ7f>AI-hB&aj&rsI
z>d*C7gD`*_>5Ae6cZXhVft++M1}}&!7!321+_a6T1#{n?1j8wAmKi7^oRzi-q1=3m
z$AxiL_i^Ao&5fko?lasZ%CZROiag+A1h<iv?Pt00{_s1JyFVPYD9(*?F3xfD=^2aW
z^ppt~!;OnY?L7A<rKZPn7TUC2;HqgEbCJ7Mg4!i+;J2v7aWNEPjOWI4pikh&S)D+b
z$o=^WE+%n%{(v-@bDs;)6fQLs!c;Ce62detkg{3QIr}=aWpIyacXpZE{wqMQa4BO@
zyUKY|@b?<W)8X26?&=;e-Qf0}g-<uRF)b)=aWjs=nM_U>j#?Jis|!u$w>jN*P~>pK
z=?={0xEeI(amL>;P<Oe}^lavH8Ka?jkFz&`sep^2H~)REiISEJxkWA@EaFsh2#dKz
zA7Su-V<tlQkSn~8qJ%pf0%sm^kA?uHlxwHZP#L#1g2(e$&PBaOFCKH7*TC=z_m?vo
zE4T%eOIyilcfhcU+x!=VPq~~pXjXF(O@MjEjh+UT8t!o{RBE}|J<wLi^`Ve^J*WQ}
zU=5uAPIT!x_Z6KCzu>}uL#>e;O~p%Y&~aK!HE~gta`lRP@E-QBxl)>Y-*C-z=>3+f
zmjmV<H+MMbn>it!1hsHa$^BL?n5N+OT+k92eBkEYL|Ys8YAu8xxkGdc(auexSbGO|
zXDLR;mLKy040imll-RnDKgEE-YR^a0g2{pJ76<$Nd<w<I5Agn>;62Ej>A2dF54{Qt
zC;l&-Q;S{r6TidYFyHfg)Li)-3Vyls7by~Ol;8Lrcs=+rbhhBlXRL>c58sWFQhoW+
z^o1VhU*YF3Vt;;U01N`G{Lx(~gLv1Kpg75IaRgy7|Lt0gP$-{!8?`XL4`mLY=3VLh
zE`nb|bIMshCl<m;eh#hkqWBN@pm~n3e+ukqehzIBV)(K+ICGx&qp(#hzk4|xy})|~
zLGvOX90HU}{GxEm2#Vvsr)W+*FC7AB68LYzV3EjoM4?FHGjE|SnXi8XrW8J%l9p2W
zvlmfI<Cj&#?R5TOEmSi2(0Lf(%lvVVC8N4pQ|Peg2LJL5_-^tmzrq;Y;wRBTT_*1}
z13X#$Ns7ST=KGF;bvCc12lWoGzYmZczJ%6ixqN9e2=e%Gf5Vk~d;kS#3;5h`P~7Kd
zZ3c89@8=AnBK|YVyDH`j=rs5NUu<0q`-lA45*U{7n=H_I#23>(r<7m4A3A0HBKkQ^
zIiFY#-pBmV0YH1gFR6n;1wY{+{H^3~Qxvm`-#83*Px;fMfmzMR1On_CUq?q7HGBu<
z<JIz>0WhfJ-_zc;p3mfHfz-hF2>|GGzHc(5FZhwiVA#n2K|6$({Dw`iXyU7B#r=wJ
zqSxkYUZ)4)8-6pzG~e<|Xu0%`A36`_&HSPRXlvoQzVNV>pZqrr-t!H#6Z*jaMMu4D
z{2>ptedL#(m*B~6=jV07Ky~o<(}89y_o6tHo!m?(3;X1<4`|yjf7u4%0eSWdP#ly`
zrLW0RUQgNoPV)Q*aP*KoZYZ#w<twMc&P8se#Hz#chqSkLmH#Y($`N^NS2*J)H&Q;I
zyF7in4W8_y@>R4<^N=6;85W-MZj?{rB{$QK-dpZm4_+U+p3cpD<=g4!6n^sUw7EPc
zA45kA$K^fMF!z_=DuXaUK8BXjC*=K?0W46yl3o!(@(vF4C*_in7{g$B&MK&!l4nwE
z-Wnp0nF5_qc`W4>gvl4tD&w^LY&9Cs$gBQ<FkD_l;ob;&q78gHD_{K(29a_Voz+Ik
zeQ85>PM&cFD$(+JvmlI-&s72Cy!_KWV2YJTbb&J$<O?WNe^I_p1k8B(qi(1rSmjJJ
zhBQ$=?=?V^<fW-7lI2BD(5Dpnt(|~LmFM3BZ<@SkG|<xJLmvYzLmp4bwU_0+Ps03)
z+=tFruF6Z@&~{DUWf&-~%N3z8xFJ6{6va)sbr1}0$@3G@mMKrAWmJ~jYWoHJzAg99
z1x&VFMA&!aC5xb%Be$nB?Ogc-+WO_m{SL#6yYe6!?tFO`WvSnjM;(Q~1@cs+vLWi!
zs{@*a@;zy2E0TXsFS=s+pJPGzK>ptjs63P>WCF899y<#~nVhkng5TwGn+m8tmXBJA
zqEdc|M`M-zkKSl|DsQJLtVVw5EPSe!-wH!poqRdH#h%Nb{SCqw@@^@xYn1Pxldf0t
zdGkQ{TJF$!>L<6O$>6R0Z<?Oo$*Z)eHOq^_;o*Dv&DU0_evsQO1x%ZKJ!QXql!pqy
z)GiO8{QM4ijtE}ZD*mN7ubtvd8fyC#|Io8-uc$i<UI)ea?l9l4=xPUp1B%DAN;s&9
zpy|p{v8NED=A`IOX(NXeH(Sx>tjOLE6c@$n+mujnSm8mDXjjFyZm>V1=<);5+!QXS
z;HkS}(F0H%RoFj<g@+>iE2wxXe11dWrTF$B?7S7te*)A;as4!EzKSNg$^8^}o@1Pj
zDK;H~`Ef-I<!1ORgrA@YP*_ewctY`8e|ob9D$?j36Qro6C+DPMu`LXP6+h8Y%qc}G
zg}y@+pVRSDsABJ6V23F#P~`ozqL$L%&L|Qp;b^#G$!eHKC>lfQ8BwgH+>S_vg}#a?
zh3zo3ol|tQLNi)n`w*D13g^dYvtCdPrAhaqVlTz6;}!c}p`!_kP2^LeA}SVWNs95b
zElgIpCqgqtvE&A@Qxz||qb*I5PNxCsit#$wWhj392cVY~IqfjGqKNJXrmKo(T8Up%
zEGNS2ivG0yx}oSrhb}j*3du;=-%{+1K#{2kp+o5`#g~+UbX&3TBMh?@x~^clqu5Gs
z$Q;EAiu2_v+J6LEo}&C5(C#XJ=mVef6@Lzg-95$R@hA!u))=(iS6FPJS*Vz7k1wrA
zVF(3EvEmmR$`XY&kdAyGDH`d%Dpjnfqp~tZg$TlOh379&eXKZr1x2M|GED|m3ir;C
ztm5YzKzpH>{ttT5sQ8wIFBKAcjWsD;9suQ)LVp>UuN6xu!{m)(@hhmjRcyl<qxhY|
z*aw|xRy?)-2{&34GCd4i6+<bY@?H_N4YdynTiQ*vDK>3I@lmnwYZUE@rxa`NP@HN3
zy{&RK&3bmqZFXSVr~K+0IAgE;Fdq~SO60rXsZhSBEUW{{nE5CUDuZ3nGe_kQl-1^>
z)R)rE@{n@j-;lZ}eR=@qurhNfKwXvBi!gdelx1t6;-<8v2i{#ddotRNDii5A%R~9&
z?{LObId(o=^HL^Ju7tNTMG7z<<;3A2^i`TDf67l8x)H)-$|(9Z%5kN!D^UEEL$1;>
zO@Q(a<(-^Rc1QslsLWXozk`&!==UHel~XBoG+4QXp7c}7)m>m8qRgXZT&Qx{Y#4+o
z<0r%IaAh++w-L&)6R4e4#+SjTNagKMpc1A0-2j7g%7^6ui&l=HEmn+DgH?`Id|vq?
z5nYQ_w)KP;7nI9qp>|PuNdUhuDevH?58^nbhTeGb%58&SpP=L^$tY17v;xi~DQ{7%
zAXzzx=BX6r{0Nw*DyPyrHBDJUF|BlEJf&4;D61(paas9@!tGa-E9k7(dQ~}reoA^x
z=@0^n>&h{%u)m?~M*GE^%HJMg*lsDmXV8|Z^gN9oW+}%Gg~4s*R=Sb1m50BF@Q(5c
zo!jLoLp=eStMt>u(L80O6h7Tm&ZiY(zOr-|9KEMpI0eE2rI#aw_pQp&D?m}G47?4)
zBIN@L85ApZv|4|te7hH3lqf$?s?;N8E@dK=DsNK4Z<(^2H#EzY4g(;3tn79JnopEh
zC^xi1*=r!2sZ`D+!YZYr8MUX%r?lyPrX1XP>Y)tk0%5JvYWfBib;>o(fT>ry(R;f=
z`G(>U&z18inEgU|lG5ZFl?DA^|5CY}($$-kr)gwfDc9Mc_EtG;Jv84bJ7^MVR(6!2
ztwm|w54T&DHz{l2y>hl22KIw8U?$vdQzni9-$!K+t1Cd;l`DTm?>m&|&Y-YWt)pSH
zS6%80LkHE5w1C{N66JvDfa(N;;-E@S&!3~}M>>miQYBI>`;e+_Ir`+R`a%g67uBnJ
zpd3~$ih_!(suwL--BmumP&umlJsw_os9Lwu^XIARRt^d;Rc#l5daHu-AoNkqy$2m%
z)!z%@g`etn7>Z-6<211zSDD&?=C9g8(TD)m8aoi4Q0=P&VW4UwWtar14z2?4N!2MD
zi(u7UTB)8=m3V<DMAb?+OQ_1dNrvYyO!dd-&^fJ|7YM^Ms@aqt6t1#PfNF&5JhI-z
zXH~msfFe~_rhzv~RT2P|bE<1JPSL9Utze2#Ek6Q^^C}%}oMKfHIu*H~it>fO7gc;M
zgqKuvcnITEnI15RSFOP9VHGE+iakM}sG9i;K$BEuv*26u|9nbQ4Peohu8L>_c82OT
z-SU@JFDZ%his~aR2d}Db41$N(RJ{)Z`?_k?Brx4jT`+>;mdbSnz%o^C{oqBGDwF2U
z+p6Gt)Us7`&%(}nN2Qqw)m+t}>8R$ZHXOnr+*N({ISlhv|H*)MPZdXTj{?;=dH{-4
zs(3hBtjZY*FCM7W{UCg(I?){lC8{)p-o%eoCnsaLN>z9Iz`RVgd?<=?l@pzIJyyjo
zgQHJWMMCgZSXBp-VNt2tR1LH$RYo1KpQ<KN9!a&T{3x7xrdoCc*flDSjs|O0S#&yF
zr<y`%^7X2wdi1G5HH2=R=c<XNC|;-pI4=}8s#e#+;HBz5h0B{%lbYbuJJlTloM~2V
zp&(g{%DT87(pFV38lm^92i<`7LFGr=qBd3eest}lY7qVUxLtLUj!`;PlgYqV-QW+`
z?9|if<YJ$C_f@pnt9Q^3avjvQv?4jEUP+r)NA+jOxez<4TWNiANc|rzN}bi#5Ae`M
zoo=Ni#bNc9dPrT>>wiXZMBOtTBXm@qFbmFjsQXg5+*AD-<%xQ!i-iz+t8*Jr_^4-m
z2~c14H+`Vur(Wv}!ei<-Iw3r+{y@C`>SL786rh$+BtJ;)LFdmW)g3H^!Rjs%R#==;
zdp$!nL_O~kicqzS2H!!LTE88AI<4-q6ozNin}a|YuCA(qeT2I39fW7q!<x~HbLvlu
zp&6~7L_fKWQLmW^mGkNy6jqB>Z>Cx6g1Ux|XfCQZTt#t7{rmUuH%@)<1Vwh@)u)C*
zCqeCh5q>ACS2&<CN$o(XHOcCqD}bG%Hq3@k>1rb#$YrR1OUD3TR=*(cuc)0iqIOmN
zsRZ=b)Y)6WdtLqYICybGy(}7SH`NO%OFT;*M2DKU)jn>3&Q`C%lV%m)QNOQ(G)KK6
z64G3C<rP@usgM1DvAC<=@I83*)fZ_;eox&%hp7eX!Z#4!S1%3*MX~xH3fnwTKe`8%
zhw5i^a9N@b9SHMB>KYouQuU<&P?V{E7sH@jJztJ~K34CdovrnW+Lw-oD%9BG;W<z*
zq2FFstGm$i`%HcA8VqaHRhMB=t9I&*wmNki?ZfKTk#yqOpuXS@!sqHl3WmH;2lT{{
zG^$6mLHJUAa~Uw3)DcRcyi)&E2De|Ux2yy78}$iVT{T<PHWct|QJ2x_f2;ZpW#+tB
zk3A2x4{A>_gl+1pS5f<@?qvaQyE=aoC_2<XN1(P(^BXN3?KMMoLB&Cn(*te$HUH8Z
z`hX_sD1-+!I@$v`YDU+f%}Mk9U=)WmlW8U6tg&vO2&s#vXC9=7HCKeFxoO-e@x)zo
z_#E6ns#!q`F%Qi~N*?gk_<sjpFU>*9QS{cVqSJIA&4&w6@zrExz}!!hxefHkG=I@b
z=(vWv50w)dGySM7P&2X_c0n4ORum^S_pFc67_9l6Zh=!82Re)h(F~xSSE$B^9+EK4
zSV}WEt*N9li8Gp%=NPVVO(m^QA~h@HA&k;|QU>8U%}9DzL~BOUtQDjAiC&oJHOJ_%
zJXZ5=DZnmhW?JFXMUCT0^ekS};%G%<f@V1dbrLlPe*jF9#_=)ilQlLJR!h;87oe7^
zxz-5mG>tv2IMX$0l%SKLS-1wpWz8}XRIX^=(Wqb7Xuk!@4bAM^C~j(w(x&c~X3!uI
zW@@VbLy@Jq(F&B?n$(e$rkAZTcZY9xG;T9Nn4|IQhCbzLR*ix%PxBp3822<=GEghf
z)X>TOea)ac3`wEJw-;(f8aqmfE7tr+H_`*m5DLmX)O2+QSc%5}SExMF_{@btsV2Y$
zC}kR3`f0!uO{mHS&tHY+-}SJs)U=u*t<pFgh2c}pYf5da*8Hr2#WT(A-N3HVq|qz3
zR->Ra(+17uxfqh?nme?udZ8(zMOve#=1Zu&)NI&?T9an-bfCP_EL5PsuQi@WVDLus
z3vE>2YJ$vYv%b?5Qx0CUCWU(VUUQQ|<{va`R%1xpG=JH{@T2DCPPDaay3p#bL(`)H
z*tXi0w1}|NzO9FFpSBNuvG&?U3oyVA+7)uN?bp6u08J<D!No8?q#etF-dQ`J_UA6z
z)*{dzwrW>yg}tj5e=i8PytaTM0Y|l~C_e0=jrtNgp4x7W@WM+QKr@@S_EtEAK3d@@
zp!sUuRzuTI8#Mst$F%o;0`GBcS{_E!Upt8&oB-_#I`KN8UAP>s1!}b}s0C@~(f0GC
z)*4*~&|t0XJHVXM>S*H^qJ5o*TBtUU-X~$&J+xLlt=*oE;*9nW$~Fquj=l-I2yI6;
zK+kFw6o!w~4yRL(DD53O5jm%2Prx8rJDG9|VzedG;M#eu6GhcywMKejUeGSJ{tEkx
z+IR&#y`*iU?<r3EdLk_1wdbCoPYK#nU!pBh`;#~PPSPHAK(~{%dddV$(QctFQ>yk;
z+H0k0*M14GbnO?kIm^(x(OJf2?X{o5bVVCA2`X2$O=kgpO*=ghow%+|QP95ThIZ@s
zz`m)yO<7&Hv_Jm|>`d+J?y%3&9^V0r+gi7qXv@~#DS(G}w3AMvzd723S%Asa8tg!k
zr!6=GgS*--odGKC(a(W$Puq7P+6uH~v<JAa^?nGVLha^buq)DrndoG(Si9^53?FC*
z#6#zy_B~BPCE6!+=>14LpbDy`+MDzkmT6D7K&4#U%^$VL+KOB_^F+JkTc}iMua>~B
zQd>D4DplHoMqobGvh@0`);>QDgJ;@-ltNOcwNR3Jy><kCWMUOJXtz|ssps0#^(bCw
z`_P2ZsBM~v;-$7XWh^&o`-oxqO8d`X^y#&>OartxT0<Zx-f9z4K=@Akgoe9WTXh^h
zwP;6E3V5sbcUnBW*B)>O*avOeEPRt~TK{0EeAKSm1!!x#c8m>pJG6f^pue`d1_i!6
zJ6$-1%l7GNC{x;A_k=~8gKinkmiu*1v>ZI3n<hZpL0x%gELbNk1&Widx)z{^bWM+7
z?yNgG6<)aLn)^ZXux<w>QMl?t{(|`t-D66LaI@;B(WtxYJV(OQqq;=;!x<jB-d{oJ
zsdJ}wikGhEW!QV`atYK&_b*NFzPj-gZS&I|pk3WD-8jl2Kdu|W!9#!DXqsUHbOY$<
z=Y(#@XFv(m<+q{;((R{t=A_Pra)N?&))048Pw9T4{)Xr-2Ejg5cW4X7IZW3t5Vg}f
z4gD_UjBZeO*oW)p(J5_&uHQ}ApVb|sCpA(xijLT#bSgT0Jf{oY53p!m=0~)}=vW%x
z^SX`&a5Pp|L#M14boqZ{EH3IQtgnE5N!QpLMVzjCF6`rVzxab9LAS39YKgl30kBWf
zy?PG&WL?@7V5jJc<bX-l?bgCBP4}8&=IOd;C9uoTowy2vtGa+n7+lj`b%tx#b=PP`
ze?!+!JH?y2U#GyeTe>OVSy9c@J)snoEL|!O?Ay9`yTF^R%ca=r9o^{vfSsdz+Z~{}
zI>&3M<>?xVVSiVbQw;2UouMm+`<_lo;jRMRzjS-u*EQ3uSE%EAqE@8q@dH$fb?1gb
z<$-P(Ef5~+gzc0jQlcAL3@;w(T<FDFs@qHN-7=l)b2wbC`}aH49_uVSK=?#gNq;w{
zLgy?5cBRh2474iUB8rhb)&2A{n5uP_#lU{1yV3`kHM+}m7+$OMpd95o-QyXstJl4!
z?6L-3mv89@rO$QW_@eqk*Yy=t8+DJO;l)ec@FBo%(nZku^()=2fuMM;(`N$ajV^Wq
z+TQBqVJP0|HeG<QS?Adwnk~8|y->932GV=?y>7@CQ2C%6L@W9>T~Zjl|ET+78dTbK
zMRa#rJ9PiHqiU<)g1<*0w$uM2h8O$v6H;Meug{{4E(g6`JPh~i<2OO&fd1TJs2tSK
zq>Y=SK89A<PWlD(E4o8^KgtGi)-Ngqy^Fq#f?tRA2PuN?sy{=M?h*a887SQJ185!S
zZq@4&fOb?rVJ>t$^y4UH%~L;<j(fcH$?H&f>yItO;QQ!fXwvo7FWdx8KmB?qjHSPR
zN*+86(Erg5Z71}f$<Y?5-$pr*LHbF(@Ex4g7ezoAtRMUe(5Lj?d*ES+e#|a-5vsSo
z=YbujKQRYhoYvo@ZR8pKo=?CVuAlY~3?uYk(*ohF{u4TxiPSq<pc17opg_|({i_tz
zqV?ULLM28YL+|AC`Ww{kSbZU7<Xq6Np#bkieLq_0UefP54}&;;2aQ_1zK4|-t_k{R
zXB3J0fdiqMqz|P-f@J;h+vs76ekY3}RX<aKB27R45sGxZ-~u!=^zSJ`ds!de4yG&m
zLncsM)%QIBuxt9c@1S{I{|ik}H}u1X!L^(E5f&KS(hm*B_mipjdq*>Bmfo8J61Vjs
z$I+*3{rIt<zoVDOqb*1OaV21K^=*FuCQtt;3dLRhRf@6X>nrxc?w<Z}J~RvTqiB0_
zU(epc;1}wXvd~tf7f~`(v3>;YZXW2n(6;rV-g`NmDba6vYlG+Sk=}!%lcoAvy35M+
zO#$$&Tz`mG_K)?OHK2c@&!qFP3cc-h6qWkbVQ{ocA4jpMr~1A>LbF<*u7TY%{n8A$
zR->2X1G83tgHF-w^sgx&qF$f!8k!Ay4V~dX*K>nt|Mx=Q>p4^#_0!fs=cQiP0PH4x
ziySbo^i6cjztgXug|0R0UrdC3i+;2RG+XtKNoaeo?^X}Z4|=O7=-c!q<3RXP-_j4Y
zcD;devODxo@un5q8nzXoFLnms&8Y1&Y;^>R)!s1gD5?&IdfNEyH!P#z%mKqyXV@P!
z6g0vaM?>fwblb_$kJ2g*8A5NtUuOe<18pvbf(f8MY}i46O32k9El2H$VJ_uLxEY$r
z8Fxc5o!T5V?4`GohryO2X`Y4<KeTyS4W$L3_cruBi^9jyRscg^!{(pB<Y)L~5mb*E
zHc^o9xS<Q(-TsE}x&kf0V4#@834<jLDuIS6575yd!+R&RoiuC@1z50Qnio7gWjI7J
z_YgxDnz};`J1G|?%rGPenx_rcZ4r>3G3=%Ev2cTL7cfN_yy=y5)^LDM$s!F0e*{dF
zVF~R!&l$QsLlJFgq^~l@&_Ykld4tnII1_6)A_4CO!zbTEc+ud^K=YEpl|nRehMBaK
zh&M!C1z3XN*bt~B8d9wTVVGoyTLPz&4gdZNofN~xF|bHAtosA@X@)_hl5WUKhDC-U
zvL9T#Y*_La+O8OGMZw^zVb@{Qt{DbWj{kK-GKJS~7+NT6_@<%n&rrE#xJhyGOv9(4
z_ztoR69eJJZ9~=<6v4<gYz>6P9fJ*p*K-Wnw5`fD{5>BdlV^wu0_a^s;1me+4O1vy
zbkESS4#EP%uxO~<H>?n%t=KTy156JLJ~uE34-MbQ;ctn-m0~lG3{g&?FE#K>AuKce
zO8bg(L-HK@gEo&1TH3NbG4Ql(s4)Dp6FyZM@FyMcj2RwK9@bMs7Ug_a8?q<D@R?!8
zb+pwO7CiuVt>M^MwAC4A(9d}44F(seG#DH&!S1=C>PLXRFtkx-W20g533&g~a6B9a
zO@{S2@Ux0v8LrdL`n92w0oogb?OedTH56N5|IYCDMc6kRR-S~1Ee0!{1GE}Ke+1fl
zgZ40L9}LM9jBPVqp_BfPh6cK=+YPt=fnA4TF>N7ijb3Kd?2Nl7;Tzd!9KIcV_Qw83
z@L3&<J17-nzwvDvcn=uQv0yrAyyXmRN8_p*U^^LO={GBfj9uxR$Jyu>0QX&t*J#&$
z*jVy6G+m97N8mkTe76@WZpJQ@e&TK{yauqN#*cLL>|s2*6DpoY8wx~t8FPFg^tKvj
zKL)msv3C;aeU0yFX7e+8(0=!r(fR~B$BozA!Q^jT`4yM~jA^|9dcxT52#P@C`gf=W
z85=Lc{G`!A2)kfoRyYh!8GY%m`h*yVQ%EY*7*2nVC(IZ*2n?r<b8OIwGe+x1I_3>G
z_Mtf`!Z_9fowLSQ-=Y?2tfHSxM;QflI(E)z{s^>aW7kzMh%wHk{r!1kS{hVhjnC)@
zG#8BF5fEN9?&=B6OU4i@IvQu3^%g4e#zYE5CmEO189}nKC&lAaj4sv(XiPQM)0~uM
z+@(a3Zv2|QwG3kxt<WzU<=0SLF^=mBFRmK3vr$|#zA(Xy>&687-RTYEKNKjsX}n(m
zyIaQEI(VOH+}s1TEMuM>M&`CLlY(y9#?OC3?T+y)%ALzGx+Ytpnrqw}i1ErZsy4&7
zyGGqVXv{b6Mi#I5o^gf+^aaMz|Df%@aqYJ#3XSghuq!g2sRCND@%wSWeqfw=90m`K
zk7yrOV!U?<ZI6s)DR8aSsPO_rnK82$?8=R$^mCfW#<Jz~{5>)Dq~APL7zeBbZ>8}Q
z4i;6$HME<2YHZtsA+0u^p-ulYqndV;HO82wFsL=2-H2M9@kiQC)*E+Hie!V)k3;d?
z_*pCrUKk?_fZ1r=N68v5jTLX;MU$~x4GdlxyLX}I@3ry%ap=4;cH9H#TjN}sKHeGU
z^+hk5jos-*(qi0B3EZv5@GKC%Hzrhr;)8K4C7`q!%joR(qp^x&VC}{c-cac<_K8B9
zt;zpywAq<*Xa}>;wEZRM?M*pG)ErEsRcN#BH}(7tXa`IKe}ct9)0{LgIhwW>g5JsG
zz5=yFrZur}*xA%h>EJG=GMdB=n|f|S;c8k(`=KMI$O0I+ncN=%+ubz%1KN(7ny#SD
z!*q@Iq@JeP^rH4MO{s*?+w^A>YCcxe-~piUHSL=Kdq2~66#nry#Rj4m0jAYj)J~X^
z2E!uIbo)6R4KmHAC-tQ1_ej_Wo3xZ>amvL04&D$`M>xPjO*{Le2s2Fy0m^C9FbV9=
zm<nxiKZcvO(T*U(G)oEdvnH#e2o#Z~11v@_%5-)MigTv^bUqwy;&TBLV|t+n%z2ZJ
zen=K;T29mK1yf&7_<PZ`#1X|MlaPMU6=(7)f_c2@PYIY3Ob)bXNi@aK+9k>4MqBY@
zlY-80QcR9+P)Ri%u+p(jnkn)Ms_7=5kI>05{jwg#Wz$4TT)twu9tkh5nmqTw@S5oe
zO=;Inc@!7FVOlsAyf;njFQDy~>8u-SnWn*80hVPNMnU@9rX87ZJKMDR4D9ZhUY>x5
zIi>;o0iA0~TTJ`EJkw4(5x#5smi}5szUh?%#_OKxOixf0m>PW1cHi{j4lD{y|IzGK
zWQz2HO0ntdR1iKeU8LV4J~Uluf)^#Gqsu|@$TapA3`$M2D9g6Y<Qf9{a?|dqs696I
zpk411lc|ou^H*WYq^$EwlQ;$zRi-~_+Inho$_7)l>DEdV&rB_ZR%4RR0Y$CpCj}_#
zOxl;Qt2ent0kpx?hqk@XO>slO^uqLIINBObpE{uS(zJz6gqlp_ZbS2xsbDnxeQi31
zg}qh$#&o<5!~NEDMu_5_$(erk+iVK{1}?UkzFZ96R#O(G9lSTa8wQFGrU)5)YBz0L
zfm(;Dl%`T!^Vv^9VQ0>}2=jgB;gkhuZ%*z2p@SKFB)sCxQz%+?z&t?=%!B47n<2D1
znw{yG$;mvNmK2A~Ocr#U%?n?H(8avA0@#Pm2TV|LHQ%Ag)DiQHuR-BvR#JwiyLka+
zTO2jVjYoey%nr07@ic4wQS&mlQI@;6Igf=GK4$Gw5c-<W(c;0+e4`L{$E@bF-O%mh
z<}YcQ^*5Jr01Ys|ID_JZIfr&Df#$q2s0NvjOoQP`^U7O*2{w<c2h%CDnlisa%v-ji
z2sQ8d0xDtVM#^nIZJs#@#ToNTN;L~NFEzj*!o22B_;l7BLbFz+*;+;qXO#JR7K(G`
zb+k~AHYafKDaLF=nY8E4k=tMxYhDus;RW+kdyLaX^W3lC#U*nRWog8jpN@t1@#ent
zj!Q5*>;hP#*{uWSN#+MrQA;*g97B;}?lv1ms+px+yfpKVR@zFWn=2@0m|<Qz3dLo!
z=UFgaF+a?Ki&xEeHiP1txsaCK*UdjTqlY)lkujjZX^!InbITmiA1ImTl|`V>GVeM9
z;cau*3NU4x!%hP1j#*Br#yMs;T1e%ZHzYzO&-{xUf!;NLCq-kv+5RKO>z?_)ooFmD
z_wyM0TR*EC{ld1yyeJ>gkIdhMK(W+(b^-Vvo6{q~@Wed0FC45eTlS!>(me4!tgFlu
zpTO>^d0;69wAyT?iRqbnFQo_8m_z9eS!=cvfUeFw`7vts=C<G9XM?%O7sYe)Z%5I;
z7v_%6KX}?`E-VN3OLHsz7@^55^#tfEbMPvFzBbRH_{AHuXBr0Pt+@x?7Vpf<qfj)P
zJ2Y^n#hgfI#jWQ2Cn(;V&(Ytm{9wLDyX7|XLr)YR&E75`Y&UN>4wVk`IC=-$T2^eK
z`N__5kb<!LEFu<O*jv&K;B~P4*bc+}mPho4JYad5jjkQE-132Ij+U3}(dJ|k(|N@q
z%T&sbb+)wA`p?B8p=bH9Wp95lxmy0*2FxRt!E!LTS?26O;cl6@9(G49ql4*u)Wh<l
z1ZbWXTUxAmS%xe@&D%1Lg6uw){?7pFYkBl3(EKc)ZG&saER!n$dfd`VI|zTvC%d5%
zV9BNJ&<V?x3&0Mv1kwS2kj3T$Y9}o}Z$VqIC2%X~Pg&+wfg!}wI)Z+A5^DL0=Ik)b
zdm4+=mR~92f5s9^y$H7${zMUB8AaK8XDzEYLo?E{VlA+vEMHJ0`kbYj(xRd*9gE?8
zjOAiDD9&51t%NYv64L_A3zo=L@b{u+fh)%Fk|mn<uyGdt4$Q6bmdS-^Ot9qVqMB%F
ze}cv&OXzhJ$(B=%5T;nN{{(NUMVtiCG|QO=Fr{0*=?9;#SU%7}<5i0w3vOStte{^q
zUAF{fL*<4=dj!thv|OQVpIa6gJ<^#LABt3FS+-?C^S0IEdk`*WTaun)Ebmy%l!lpO
zi7SOgt|fqutnw^RD9&`(l0b)_`4;^C2v3paGLNFbVxXt@zGdrvcvxuBJ3*z$GUW=e
zi!I5sVE4fCx(<Z@kEH94uc~O;C?cXLMFewu@4bP7iiiR#VnYP6U;z|SvAkBiX{0w&
zNdoDW5Yk8il8}%BX{163=?y{(Aq`UDd&cjt`R(q^Gqam}_RP-Ap4_mh?}R|J&3<>-
z+hW6^t)SJ$sv>Wt&E{DPVA^d4a=_YQvyF<mJ8jZ-VfI}%X39Br+dMi2i5?rfO_*A*
zO%a`@ZrZG-l>RLnR8Zl;vtd$(@V3put1!FYrih}w12&)C1R1pX?KzMkn-v$qa>wR5
zXS9ZGdaV=(ylc}yHw8v)Tz5j#s7>m97&B(GxeB1;Hfv{K;e^dbs<FIhBX|*G_iZ{V
zVa%jW6^T#TY*a$wv`u3KIA?6sLd<a1=6@<oV$SA>8LbC4^-G}ep-m#W_qL3u=|FAA
zNc@uuG3*%^zs7PqFn*;IwIidP-rh$TnXiL5F-{Fa!kLk;hI$u9U?0qPW!#|DlN%#|
zDk0n%kDddI2jk7JFy_e+QGD2op{7sAcr(_~Tfv7>^&$*C%1C?(EnmjaXJGMTto;`s
z++E<$I7Veg0gTM0Ab|`fdGtXHHC2@yV|-x;OM@9tFNCHLM%`KnhBDTEkJfQU?AstG
z7+-#Z&M?M5l!XXq3?4@-g7Fc(2O=3iQJg1+@ie7bVi|9d3m?Z=6^&LrV=mw+Jbwv{
zG0MUxGTd3P?Ifdve1IfIOfKehilP0lzK`(^Id`WSL!PiOg(3JCEU66fE|`|am@0z8
zbVd{zn!)&x(ky2f%P7N;$q4TSN){t~A3C!c-zi{B4&$#@kh6?mD9vI$$N2C%(9Sce
zzW_`wV}#<5d5lL_Kro*Xyb0t2<4*}JEMPca$C4B>qVq7(i;Sl~hd>cy+XJ+U8EiUG
zmoWBvfU}hGJw*U6F+O`2DlRi#EkUb{;S>t!a>hz3460x}M!Qy}m64zWtzx*8V}@54
zXA>Y%&2UixyM{4KU$v@boFBnh9iyEMP4$fTS3yMs;|?Vgt}=Y-F}%ibtcP49V?MnT
zuQP7`mvCcjqG<08#^j42&5Qs#CA2WUzYfyMC?=P*jbYtEsjGIz#}w}EV6;*eqLWci
zm#w-Om&c&DoAKlzNDreV7@B$+PkacyHyJm3L2fZN(t)6l(f2x9w;3y`#;TtYOvSnb
zjOGxi7-Zn1Ab9W?!E|W8!<a`0>S4yWCbaG{7JWjq7-59|4WmXGA0LLMF~*5iFlL<b
z2L0qG7*9R}z4sW$=!AKn5lcDWNyg!K(3)ZdcmQUavC0!>&oDA5sxZq?IfG@6;qRyW
zZiQ8!2o5_YhoT?$%qM8OaA5xP35;-JMo?tZnR$L1V=l}QZ`kR|Ol<{-8`JtbmcX64
zl42<y%u_Ex&XakD@{(T6)s)}xW*%A#79VEdV%T?-xuG3nzRU?aGW#)Q^ql)Mzp);J
zodHZS<u?MEJLv-}K}<INMvpNIogp90JWda42=g+1*d>%X^bQmrXD*@~(Fx|S=Rv}l
zKg2*qI8&Vtfe7Z#mmm<y<j+7LiuvO%2t+d{Z=n^#e1QsbVwr!^o)yRZU!N7tcqW62
zSQ40f$gfUh{t^#kPBIxEf+vajD80&0G4Jk!-O0?iXq8Vhzdj7P6y|qS5tGXNn!Z(&
z#vCUfG@V&n0+PXeiGCwzn5%AqGm|+$0m>}q4-|dOW}c_FW)4%dhVH+dWe#-0#B)q>
zFIdkr4~;`pE;D)@oq5ciT|moc=AMDz1*Q+BPzsp&Q)m@3pQmrxU1av31u0_s%)#tp
zrkW1WCCq|(04rsVk#ls3nYAA%mzmFzk5tA~ybP9d=2jaze^fA==#j2uK29&uD&|Tm
zJ-EU=Ln)AI=4)<HSi{^w2hv(*>t?XjG51qYyq>v%a(NBRp@(Q)W!|B6zQ!E-3oMPy
zjcYM>omtR@Rul7Ay0CSFSxN_%X69}QS}n|i2`I9*GV>LfZyR&212FB(2=e?pm_yZQ
zbuzcj15X#zF%PY7rqf2C^)P400MpAnSOU2|X6trz-e!i{f%G%o?xJ&m`6hV@gUlMb
zjXuO=zlX6qOb3dC4Kt1Ot%SQw`|Vhu5i9fLmuQYM|4D_!7*k&lo^j@$k6_{i^D@<T
z++(h$OLzB~gLM0TlDYF3)K4*eUd7ln^Hqw-%rNt}f@PN343}xa9Fs@B{sSiSd93q8
zrqdCC*|IYFK<rrGU4>2dtY4fkB?p!@>s8q1$QoS;>?5pY4<X^inx;ZAXIAYl@VK!4
zxD4XTy0Zxi-B>s2#o^BKaD>?&tUDWk=E;)PL%@sGXhzGM6-&F6538GUCP!Iu9Wc$8
z)lQLPKi0N7fcdk2V8NIG)}L1LR|8oqDXJaBIzo>5F;?3f;0b26&}%b<73~kxLRm@9
zFzq<2=0oT`!5aS**kP>S=n{4~YcHMiB3O96<H2JIDH|2VdfosP(X0r{?Z&Y7OCcA_
zilT=qj%BkL(DAG$-0a1J$2##j1QS`iFT#qGtld|jK8ck;ugz1e!*p#SnN?2D=4sZC
zRAZRJGSdk<l~q8QxinTO?J4Q3@kgOIgLV5p$Qjle3Z7)Lz6pY+EY|RHD9UENR{_o(
zR>wBTon^JwQvK68)+TaP&$A9b2a?MgUk1TE)&d<Q@>%@tkhs9Q{wl@_SQ6Uj3Rwr9
zLFYwQs}%MYv06SsXEEyyDj6za8R(@@$|@(<@Dj_V9rl*9wzZ(Mg7pjqf-6~1`l7Rn
z^#k`YJbzbMc6N}jW*x4Cd=0DR0A^pyGOh({9qYk=-{oY*7C@qbwfZKkxXRi|&+j$X
zVLzy7WPLz&p4VBgbYM<RtlQ*8-e5hKhp}c>dISVoSfO-gZDld(sc2&@+YSxwEM^E$
ztR1Xya(g>judpzuF4m%1pmnp>Q7KvvE18`AURLx*jNN3}AHXbbvGQozeXMuMeZ0+j
z|1t#nSqiFD9AH_WfxsZ^MM{zmv9?eo^$tt_GRB5k-n2j7WyR68kP+7UM?glctoBI2
zjIk;OP%+N>b~(@{Sd|B%;vQ?uGmyB?O4$LHNtXYUK$~K1?*hv-YX^DMGc4H*U}jl~
z^kbW2`A}WK1D5V8$V1jsW^~%J?T$dej{R;l1nk+qQ?Ss1y^kW!j%@1&FX%nO{<9c7
zPVD$VNI0`MQI5)m-9zy#SN6X5K-}1Nndo$9KeGtf9_$h;TAu8OB8+*le_Mu5Z}xop
zGx@L&PzvNId$m0<ec2cO1@U8lMsah0_68{yKY$$+4)uZTJ=P154`Q!xM)MeZIedWy
z!R+CFtXBxTn7ouwwznr1;W*o47OfNP7q>znjJ<^Rgm8A~2Otq_(G&zC*)ESlQxyAA
zDrAjj_nn4?G3=Ztut2fwPopsw$KJmSWAW@99!LUv`zZO>iEIWNgQwVQBcVQ-eT7m@
zr`e02f~FL9X+KCR`~0IAOJj5BnnXJLN2(6WU@M0qeun+sqcAO#z1b6TS?piQ$I51>
zYz0dWyOd^jmc6wJ#++mOeFK*BY+L$xO)mSHAL#x|9{bcPz~r-c{R5s0?8vVnSit_A
ze3nA?3mw3|$UaGxI7RF<FSLr;X-ya_VLzaNQYm{G-Q&N+ZXkOvv#aQeO&L4zHZ+y9
zZ75V-!QS~BG*q(d(;-mBu9ATB3OlM|5uU$lwp}xtHS9O$uu!$^kas}p*h?GHS<ill
z$^#nMo1O)^%3fLo3$L;NrPoR$``Gu;d!5}(2eu~mK6=sLV82eGf@bz-FQL`K9x-C9
zm93+~r#5yD-9K(;pZN%+gKeZu-rC9jBL@;)Z0BcSVmJHM-yzY%9{wB(d)a|oVen1%
z8;O|3EjI6Q2==kRA|K>7n;Q=KezqnHng-avwt{nzUFHh$A$C1I#dp|28nlMl3vYns
zF1yKq)(HDLh2}@uNn0Q=W@XRPo<Ghm-VL4!_G0Ww3+}PAjzZIY_CDG}C)uTkpni(|
zGF?2IW|#jDoHJ}^3Te)=w@^Lo9Q$AaCh>s%1id03vYis4!j{uWm9usn0XeAloN>CG
z@4ztxfyI&YG##staICL#Fl{H!YqaM(bAEUS#D%k%wo6ye8H)6|af;(0@6P#zUIbp8
zFS{`dZ_a7DaqYt?p>Wty&SNUb`EoXp>*UADqi~o%C&mc^0h}jpfdq0!zX3`R$3#c0
zW1NgHF~ML?f|c_0A)MV&7!2hc+zYhh9G5njc!G0e3Or$)f<0)3bAFA5O%a?|=r<S1
znfD3gqBynN(2C}q%!XVHXZ~gg#B%B>4jspdAU`9XGt+~y1kQI9hfd@)yalk6oKf04
zlQ=K#qv!7w$Hx;e$()UYu<bPG&~q?2g|m+e(^5IJbQ>m(Q;-MHbk1IS3^O?ED8PA!
zv&I|PnH(?LwX!%VbpJY=GouG)4(Fd1u$<+zQw8if&Tn+({yc|Gow*!S5H#d*Y)?}C
zMLvi1HZ)z}L<~W`fU}-{bA_A}&p_}Z=U6*P5$BQ3=q%<eCD*Nl^BI-Lm2$juu+En_
zi@pWuWzJ&Skjps!_OP&=bAvt=SHUU#8LdiABgJK_IO3J)yux{sl4#YO!W;DdtKl4`
zW-aH5W00@obkMD(dQLIb95irP6c4`2nREurHO{NFZ8dUSw}a(6=c7k3*2MYj7Up|{
zBcyw_&76&tfNkMiq?&_P&aMcsv~m1DL93nf@)k_HgX2YCrtjpOk;61=7l+{m+qyZ8
zZIJKb=r=$`FUS2fcy4kIn1OwZBd04teVi;(c$+hS5m@>;U(n^20nYQEpmUJ(B)!Ck
zIPx1X`!2_xl0ze$u>an199vr0F;49az{WZMQoLn?Qx^sCdz(3-RGD_4vz=<mCOPXV
zLOR7!k&ije86)3zh9i3)3THVNZh_2kls`ko15PS--31Rh?(4x~%YEH%<o6ZU&N_%W
za`#gX;0QO2{2?dqZ<oR0%zc#}TNiE^1(jX7*V-`V#{HK<x9;3x3W9iWJ1JG;$qgRG
zm>2i&c-ZO9O{V4X;SSR2;3#(oIhwxQxs_1l$KCTX!2G#+|3V;uJ7T4sC6HTl6`F#$
z{*;Y9#*NlsFqnIlG6Eso`&9fK%3Vs&@^P*g&EW($j|CFOeUp6XaPHKT7>nSB-#{yp
zJGl{KQCvAqDVlqh{E8TEGdWPP+|TL79>*QMg1=lm_wT;{oJsC(no}aTn@SE&a+$ke
zViMPp&N!#I+wOoQbK5BPdYbzq{Q^?B-%^?&mHQLD(bKqJ7@#+udy2|pGPoXei{%Wr
z^l4a;$?c@qKo)nH{?|!1*XI-z<#5Zk!iuxpSq(i*=eW5mAaR~MLkHtru8N8T^0;vv
z@Z@uu>o9hK`^`3t6>wM9VyuwM-2+V*xdFwPMG?2`YfQA5D-Hv833oggETvrQYZ$x4
zU9tn@GS`-BD$2O(Nr07e_iO@m1=q7_9v-Gjt{@4`DsIeAP;rG@t_4gr_v5V~b=>Jc
zV0S(DvnQaifqTLebGpiXCKjOAxU1<5+sK`xTKwzWSqdjNapPDZH@G2mG;8L5O9fIb
z+yhkk-OBBx`j9rRmg1`IT-714SUb3F>tTK;caIX-UECNI<h!|ltixarS3=3)UheMC
z!E%$EnFYaHTq~u?`?$W(0sA(0C%Hxa-0)*q=K*fazZe_j^2xIu;%;gO*d4CTaX=4q
zA0CFlUG4_@mcj^k2_<?*t=xf~7#!p7qD!;mTrYZkO>hsA`S-XAI=S5EK2Gk%B$pY1
z))aTg-<a<-_s`A1p5eYkVbWP{kQ@SY+-r0Kc))#x;s_79s}2IpmbZg~RCc_SG!T2<
zBUDN4z-yp9q$AJT^$VIuc&qoo3MbxTI!HM4rlc5j;Vu0iOmyY>B?HZk*E9f4?mSj5
z#yohfxoCOvI`|Oq;tijMdT*W^9j|?O|2Tmh<!Sa|%$N80WeE83<OOK?^Q^yN5dwG%
zR>PP;-ZCrY$%1$y+Om)FVqe5yFz=u%<U@D|7eg?VCx0Jf$9ZpWL+b?ZHAiR)<NdV@
zoZ-B$=zJW(tL{WAlJ^zOFp8(8P;)fT&j5unJey{)#PYW7$6VrgFOer6&ohzxmcaW=
zNx_svUNU`O;v{cl9D0*@Z5_~bil>r8BAM4fPwZ*l!}VCF6yD<$<4)y$Nhi}Zo^%F(
zku$v9vk=eZ@sl8)#ryIGNH%Zr2v~A>6BNNc%j=>i?i}wRh1kyXa(n@u%e%XVE_3Gb
zo*h6lpXad^c3<FqkOB1tyqi&wDCAwG2<}B5Hw}|1;w__$X)$jb9r;UmB~L>|DQ`QS
zEHCl)KLokV+qD9ujF)SNv2vcx8Q5FFOQlmyC2tEkPF1|}PcU|ccMbI+a3*<61ZdXq
z5}$=_wY&;Ci`MaSCjnE>OQ0(22HsB;sJY6sSp)Ugcuz(^ppkdwC(Qmj@69%VHu0M1
z)Ov##NU@k^-WGbAT6ptPKw5cqLO{3iGB;wL?Ys`UbJW3ml>!#lPTmz~XzJpvpyJqW
z-rqJ@uO8k3N`Lk8mQxV&CU2qwEVp>4egbwM?|mlp-sYJ{z|znAl)_8{JnIt}8{}oa
z1Ph0FGaCSQho_kV8Rk7gPvc!)06pj<yr0K_Im&zfb=W&*<rUZgdz|;D41yE9j%i5T
z;{_*S@IFtU08Nv;W!b=<;(h%c$TaVV;~+D<wNy?w%L}4AM{~TVT!8(6_s$EL??axs
z3MjVxM!JP*$N#qmVD|g~a=IP(uFpcwk^d4!NssWYqHItn{=ub~j5A+)3B-lpJc1Q+
z<y$5J>c;=W4lQ?ngBF4w{H_I1=*h2m1883S`E-}Yn{QKvP9J_pC|Hj2j~|43U;Y>L
zYW3sq+Y6fl`AeuoA&CDM?Y+nNIaGiX%ule^K}87vJ4zFV@_$N({BizA<cyx+R~ex<
zj4u^o7UBFV$~H#u8;77UlK&4S52E<Pw}2MSUq(Aj48Mww-m&~OlpcxWcaU!v&rkXZ
zU<v$;e*vAy-$)lQPV$#hlq!k8VwV;46n`NlOOpBJdjNBqpA?5hNa1fKKPr_UOCD+(
zpZzaj()nRjz?#92c?)u9__xVT&*Vos0yK-S+X;be{>w?|%;Dd89Idl_wFuDX_*M6T
za-P46LX5fmZz)Wa$G^0if|>dJzK1}&z+dna1Pl0@L7)}#*H3_4<VTqyQN%yF45k(H
zXDL=!!XNGfb}9cQ%DG(PKlmOjm-!9!TQB3wDBM%d@BJJKEBKo!pHj)+LUpKBd?(ua
zuke5M!B{naCqA!ta6t{fl9C>^{A}71>-Zf%f~TH;@&%aKz_*0JrmOtOr!aPn|IcsG
z)X0C9Ui;ViB|D+MiC=OCdT;PIEQ5+>ei(hhuZ7=3_q<#AztHB_#_ywGWIKPW-xqc(
ztjj4^(#^k136LJXaS|N8`~gaL-Q>T}g|S=w?E~oS<DdKk<Tn2b2ln;z7g6Q(0RQce
zfi=j#ya&pM_(zH{c8Bjww*-dyPd^LW@A7kUz%s&bqLk7of1?9X#`xcjV?D?DZ~piB
zs0n_M2F*$SeDW)%_#CRNnC9>2pmT=bmk85l`7^XkbNs&@VABIW4w87Z_@}Oc*a}ut
zEYVId7700f0rM*?h=ag^c2`HiPgziSMDSY-Omh-E(v81|vmkREHn|AKM(FtBDtL<`
zn{I+t6gG4hd?o~phameE$a@N&2!n)|V9^&~@fPgM2JsOHdtk*;!ITd)`3gQP#YFuC
zo7Z5>U$Bi{o&kcT4736TUu46=Ab}|tn8yUUmoOGA_>??>5W($jlpYTi6#NXH<AT?c
zFnB_6nTnUf1WU^>r*J_gIR+7eJ#WIaNP&=Y$WemW1!zSJ9$N#@7(sw1TCsxHX_tx<
z?8pa+7c8RMrv$-c^nfM`Hc(RLq#&>Ytt5ek_N7yTXA9~2ezM@&DNOXVpqQNW6u}g|
zHd6)7v}dLXmM+1vr3)TS1ZalfLk{H62wFN}Z>GSf44qkmkN$#9*@CPU5YG{m(YyPs
z;3vw5oD(?wh_Um6mG46?SMcFIjO7U)=t1%YX%i5zUJy*lv3do9b5w_2C`f+`*cSzJ
z^{}Z(FftD?#e(p+Fqsm;ZmRn!6&y1|?<K)>K0q%EW;cVB2`VX_Q!Y@a0JK7|*%oG3
z3Kmmju}Yvn56mlq$`Z7y1us+lxkiwj1F%}Fp!`#y)d@tKAXqP0@fmDu5af~Lbyc9e
z0iJ7uE-F}P6x9C%n{EiA=ylyJIPn`eTLkm+(P|ak8o*eapzafpb^(JfDt8DvX)c|D
z@{gggOAxRV7Iq8XPk<FYf}Kmj(krl*eFd1C0yaH(w*+;xq<w<WG=Sa~^nZiSeu4G`
zBnAX?Sy+ofLCPw?3<<{GhG};M;R=im3)=T%o$m@R{R5T}LBn#0j|x`ZhKezPfws(X
zL61MiCIojLLF=Btr5iTg7i_T7!F^KD_$JnCO0a${K&J(#{sicZKu>PMtl-I1D4Y`<
zegnol5a{Xc_fU{T`Dt6>_5tX%6CR-3b@sx|rvc_5OrlhrqwtUbC`W|J^wx9|I?@$T
zXW=Xbw_JoV1rTr*x~EV{hMSN{ktBEF8H$#A2$#H#mZ$I>ZBt&tb|zT7h35HC=p&q*
zgo>j=CAl@e!b?e*g`d!l1L7}~?*?{&(Bm(R1qvTs34tJ?2zMkF920sp0xVdVPgVXQ
z!p%ug6e`>vNa4HV!e06g#R*~F8VrUB^IwO;aG|*hJQ2dK33NsZpBqIhO30>dD_XdY
zifm$pdGXL2D`e6MFHTrNMLqGtAE@*tK{)<3<PwD<HO5W~S+r>;30G4-@|5sd+MJVx
zKXp?1>S^I)ub`PCWL*PKs&JNqh-t!Ow$PL=R6K%KhH#9woioBM|G>0NVHh8sS;D@p
zup(Rdzc5&lBm8kSG@TU|HlUR&T)hvP@`V4RctyUj{9V{|L0FXmxdP#z^*|{Uc2<K}
zFAAOaL2r@pI^Cox7V_wQSt2a?6KJKvBiS(Rl5njE<g#$t4v;e8_ES(%E{qaFzCzer
z3D8R6r&NqoCA>(%k1N6^ivCp#lWJi_jZp0d4YfkMB-mRgtVY%Df_fobGdyWlp^$v6
ztHR1wD7+?ofi~7g;X7L(cwOl32*D=d()}>)hVU9C=$eHaoG{iRe5M01t-}07jI{}M
z9Ei6I*ZYE{Ls&zOVy7^G67gNa-)Z;h77qVcULq7vKtr!kNymwsLhEWewcZlGUjT_d
zVGh+y-WI+_+g86YUxKL(2y^HYhl9e}Y^WF#?)Vv?cZ9p5p?6qlsll}G3XfCVZAADl
zeZ6B;nBWcUG2uV7vy2PF0@0cfwq>JrPZ&A{l>5T8FF+=RRn}z~oD%L2LUURem=4ex
zVLDa6&k79-fHo(b_W;-rgl3AwJ`}2_Fhg5W3k5&zL<i`OlD!BKNj!L>({G~XD6)MT
z79J4^6F{6q=Kp+2QP$gFaS^pqz}r>iUjz+qqQ)umxZFiOdm-o{dYeKGo}x4TAYP)E
z=!T`Y=m+{Fw2x>R-Tpc%dWEiV`--ZrqU9(0Z6#p*MO(=23=mm^uxf##-A_P8kSM$d
zQ#vMcqk~VdD2q0)5Yf&bAr~r=Qbkpm$TNkmFNTXgih^K-=v%rU8Ywa?g~BLN>m>dn
z(V|Uk2*!xKcVZD@Mc(vjsyGoh2rTiUzt2HMf`~_7x=0j#V1=fWq7N>il_XlY6o#G>
zefIz)S@Z^Zai>KgbXrXjjobuEs^~I;DENGo==%+TNf+f&yd^_aM}dbkq8BN>k}1+7
z#J3<zG*t-GvPCb{0y{?}FNSGnMc>*$;GAf=5ZLEM^M{}*SL8?MmpswSbY#yLt)_by
z7eq`7rWc4_pxi~F=zTh5Uljdv1Zu5CqK$KqFBYvj4Z#u-zM_o>Pc%ujCznKv$>+K(
zO8YNhB8sISa=GX+x}sPivN%G0rKq$70#%}Lvha%Nun=<9qLX#NtPuqlLZDU@XAdjt
zM9<b>tX`Dm2xA&VlQEd!RjY_aDW7Yi=O02-qp0RKc&>|z=_8*_qMNko-Vj+RztAia
zSEJP;N@akvRrD9R;BBJA0f1>24X2{jAv#I#<WA8x%6D~%JoiDMThvFfryf!DN6_0V
z%A^{do1(?EYuyrAz3E`vCsNTV`?ko35~2N~h_@gyAlggIJt#U&#mYmX)pYE;BN})Q
zQyUhkE@2VwipGCH=ZNU<|ACB(c02-sG0~E9uzp<hv<@mJL>DC>_eB4eVeG!>Df0X#
zMb7kFn-XcQ{pg(*W$b`aGopg!fSDD^uY$~p4pQ#XR@_T53On(aTVR^K_@EEeJBXh^
zv}%E)SUC#LBjQzb_;eD_u7O@>aeoH{T*MA^4sjLNQVhsVoZJp8+{OG_sP_=J(_B2o
zuY^#<&rAFU<u1I%1LR)$h{vc%?Wp+haj^P|LuoJa6Hicx(O;ZG^=JX&*&Lt+ii6$&
zOpy4j5pu`GObUwyi&q}N)I!90FGC<y{56F}j*A^n1LcJHRZonCiS4L<CtRGfmdeK?
z#3njrM~ds-1#6VpL=Q={crTe4Bi^<S*s<bmuVS6z#DDq$G+vzg8d?eBHRL!Zir>k^
z3{Q%M<lrZXA32Y)Q{undp($BBLn)in;uZ<!k|JJCE1D{1Ziif&cqwi?SQn&=6(3?S
zLtGR9az^~=Dp-*zwxeTxmN+IBtl8ppdX46YgSG+ttk~smz?{SCLEyaDJPnpy@qv9%
zpC>NVp)+4x{w>z<g7{V{PzuERQZQC1Ha`RCi{j+#5GWGI#-U{`7H=*ET8UWh1Hn>p
z4(%zI#2?cs`?7eT3NU5j-(t`z7tg&8v<mS66KIv<-#M6JmALIwbY2lR=0mPpyhjCr
z8u4lRP<^d9s}U@9;$LK7sTZ%H%uRzh^Lc<>6@N>9+%>B>jDEq5V#fklb6w0^2#F?f
zA3dr!#ABsEYZmil=xh=D(ObAx{L3)xZ4)2O!C1SvZU}n2#2?TZwp;uJIW0Zn`Volt
ziq}zA^rm>tQE=W8KTa9(KJi{#2;3GwzXPOSZ2gF;L<hw0l|o`rTuFZOkT|gcgLlNC
z6q*?p2bsZgSFEP6&4_sWR&b7rAL)b@W8#;WV@~5@g9c<mTong}_r#?X!o4qM+r#Wh
z@mUIFO^My;FgY#Gp{V$bxIY#wv*MSmk3z+qcn96seIWjuF2X((OXp$GR`M$)2JIxT
zIs@BYV!4J+2gz5jqU9)A%!0rXNt+G=PLc&ofI3U=P_?~_B$tjSu99xry4@uE=&MTZ
zk_q}~rH3S&zSQd}8K<|Xm&CT-3LbBXy&1$ua)1t%M<s90!X{rys4o`5PxAH=fci_`
zJP#5enG<17fs$YT256AvTiRxiN$^ElJa`f%ZFeD(RLUNNN<KM?X&;xQlf!yKl1Kk|
zFHG_#Rh@)O41Va0kPM6I{TC^zr`T7Nq?dewXo(N4Y>cGN6Rfe4HS~zbN#;eurg+Im
zR40}odE_2QqU5m>s5mK6P5?VeqMVNfIwdKs0ZEqdDSvcY!nB8YisV%)JW7?MSHbKw
zNhXES(<L8&FdxrfhU66wNSu*4AH)h}N`A}&PnKkyoV;wwyuUD(BMChOn6r|n#;^$I
zB-3;a>bxX-4J^!+)OVqkClMrLEMGF8;#wCZ8c!%JkTgAnrb3CwOF$`>=z}rs5{VOC
zU?`Pnia@NFB!v-}%w<UgWn{`Edn*B2F1hs@U@9c_6&S0O>|?{UDoHRE)n1VpsXU-s
zQYL|XjpRxzR;E@G(hL=K5;gq->m^;}-8D#_qS*XZiQ^oguSw4Q4$>$&_aRuWOO&%<
zX|hVbz67)zl67~0)+~ANSD4r$nSB;^w@SVfV608Dj?#7QlDDiF>yX$q!<bHqLkqCG
zB(t@cXt%^n$D1BW^)`@R$?oSNep8b99mp-ob#f~EBtvx|w<W43kbcQN+B*j%RyO66
z1|`pYiQXZ}fsfF-BYDXH+lD3KCxLcXGVl~yBa#jDY95tz(nW?bi8sAs$0Y}k!NLiN
z^A(`olia4m*?q}Ya)>4+)((&<$y(YirzOMVATyFht`L}&JfL^uoFv$~9-t2-;p@<R
zD6ylWO<U==YGB(*yPDCmm%7sP=O7i(omEF^BE3(JNPnkOx05t*If%2=^gI4&F47>n
z58*1Uc^i7&q^qfx(p~x)ow_}w!Bpz)DNTPJU|!PQ<QjWR{qpJ1;Ul%JLi4Ef3WX4S
zr7OO`Wc;K*bOY31+D!N20;J#2+b~cXOKJ8XsiPM(9h3IZhopn0i}L{*B6a&10-@3z
za{iA?f2FH}C#02h%m|aJ-9W;nOX+(X5z;XFo>8Q9_gOmsMM?80M;0x8%ngHaQrBMr
z6E9T>AfF&rQ#d41`u#QNJt-~cU=~TzC+)#<N-8E-CRuus-n*xzA5yqAMOyYF1X87b
z@lcT_EvF-Vy7XuPW|kp+pDOFmNH>#*n<@3co6fo*OPcKpm~3ebg)VZWEW`m9oRtbG
za(7Pp;m;U5FAbuayIg4-r84uR8T2B^msXRncR{Lt1g!$;VY)+BDAgPUxhVa5401)%
zqagq*ma0l%MTzt{6>yhId+GAaCFw{b#;lj6^>m&plSc7@RxUk6IgkozHF;o_(jUtp
zQ6+ULL+gq(mt4ha>EHiCpho%%t!1q=oBrr^(s^%#rCwSXfmVYwE)kqpr3Z#!+BNBt
z$1&C@-IoRHuS;73FwZ9GU(2EBhE@8{j~Hy0=F{`nBK?V;l~(C$9$?y}s%IeIE?qf<
zCGC)o3_+q(nnt0tF6mb-fa#X5@dHbbwCrby_e#H^)51-u)d=xh(l4Kbp?%UyD$ctt
z^`w+Szto33z5(g^#Q+<WTEC}L&X9B=z5VY<pW6;&hNbdC4BnOQe;F!9q!+#g8I^Vm
zLB^zJ@-fGyjlCcfQqf|Nd(utx#N3xA(JOXRdSMU1rlduUK$(_?2Ew!%>CfjNJ}Wg+
zntV=Llng}=q)V+Yfj*QjU4dR(nTASt>|}T6LBd`Z?G9`Q+0~UGj<VzzK#s`5lQ8BY
zYiNNcS6MUVz1?I9Ty(n2GWLRa$U+ukqMou(^k{j>KBh7kZ`nHfar?-E#L#e5wvzlu
zUs*|n6-_@`+IbB6%l<%AbwPk^qZ2>_Wj%*raFA^JV~ib>wf+f-U>RSJ&Jfx5Jb;GE
zYz~1OmwnWa*`JW5#sDl#mb@50q;T0Lx_K8N+enAWNLkkuFr#FtpFtp6)@48|M#j5C
zpYM*9<vsvtoUD*iZ1FN<Gf0B0krIW8G8-G{Jt>Q#LsF7#%OSK*$^Hz0P06ygC!ylB
zY+)u^DKcRrTB)*Ta;ei~F|;A4%R)l1Y8kS#R1t7S_Rb0XMKWbevw@N&D?!<YbwReQ
zBOdZOvIjGeI4k2mht@fnh;9s?mu(_PE?0JqoPa#p3SZciFMFHfV;5wiYd|ZIY3_lg
zQ1;LB=)5R9cM9S~vU>Wh7t2;rSfWIh#e`g`OkRPpOEOtH)L)hf`XFvClPwJZcDXF$
z9!Q1k#4b#<Qg&}62CHN*@E~zT)^-N+)v_yhp{Yi8n_^kDvIDVLr#jiEYoVfE7PTA-
z8)O$oA%0cnMlZ!{vP?5HHOk&8gWPr5#1RNI$v&A6MK@%jE793(m3^54))rYS3(Z#9
zx_8lPldYzYTC~g5pMrGAzM@}#r)+UD(7I%=?#4QI%kb}%@Zibr(><tOSz092-;^yP
zm*AGnxDa6dvai1a%YaN83YJ0HhH&T|k`4Evbw~Dk3s{C_*7@BKyek_}0eeJNOs?0c
z%t&X;G1*VHkRO*l=?%dN*$fp!-jj9H{eb(j<x8+Yld?k#urgCJ#}_f}Y1v-#i)Li&
zO3*ngyY2_*IoS@H*#p^E^p1Kc+jR@XR_;P^0Xw<TN*QZ=`4W159pp>@1gN9Dhj!~D
z@=yMTF;4O<@{6417wj?SB9GV(P*?fDSr9jQAQxlq@^5Wny@$M&vW}keH>WY?CAaCv
zB)sKX12p)^^Me6)RKEH<2>8lfcftxkdG97GH2KSap;U8#d^{HNfpXQ;kPnilP%iP9
zyl)l~!E#@!vkZ|Jd%%iNxgB}^$K|QyDxQ!RUqdTQZg>@~aQQC}0Tv-YK)Y6?yulAv
zM9EiC=}xrVfr1P%auvOHW92uVrO&s;$?gAhF6F0dA)g@sox%%=a+y0?C*_<3$S2AF
zpe^{6+>PoIlI5Nh_c<-MAs018zMJkhq{`=gi?KBMnRZ~O%YV2H^%?Rk`Ygj4c`KQn
zDW9hRbe3F4FU4&6#h2*)mm{A?SNzY)OBX=moV<dPkLTqo1|)Ljl|xv)Jh^iURwiGb
z!ob)CdF@8P6v+3IpHL|8rfT|&@@yyAR3z`G&lVTUn|c6NBJZP*la<Q#bUL~uA3X}r
z%ks=_h?mK84x?qQl)u)3W|dq;kHr=F@nw*xmM^9Pu^RcT8&uTFPjJCfCx7@WB<kfW
z1HjTCkEb)lRk^+tny$&uKMs~gxql`My)OTS4TVi|)g(}E$iIj}XR};Em255Y_;Fyi
z$}hZ&nYCHv7w98P?eZs|2I-LhRt>>UdD4fNOqcxQ{{ggHzMl?KJ@P~45bTv#(?R#9
zJdY|qZpnk+1a_Z%?hDA>mhYQ^T)%wnAjp8+{58Y}<-QS^*^s=1j;43yv$+5pmM^56
zOLyf~HH98V<joW<7?p3Efr>Ht12$UYa!<PbIU#qZpVvLPY&8V$%lW&(GAaL^iq@v&
zrzqGyEq|3*X5_#5fMr(R5DjDI<i#>TKahX(5ti$r{NFDDW~;bIF&#U_bBiEuuQ+2R
zf89ax9z}Q^6@Spid_=L9oE|5II~7tmD~A4o-7bo6GJ)-?@TAv*o5G3GC+>><zoO-#
zc>ZsQdn(?fce0n_k;g#16~`(d?xXN<ho++nyEdrzRd~=r(@&94bMaS5BPst7pg0%^
zm_Wty0;msCj8W<NF-5}XAi;_kQZN>x=qC3nRFQBM^2Zhb`v7An6#t%t6=8~cB~*kf
z=FxY0A{1FYXhkZxk3dC~LPMKov|<qtieeN#hd^Q#Bb3C9Q#6a|^BM7q%j97vC^k_o
zK%(L!dN-d`tO|mBlH$`=v@#Ua-+`P_yyc9EW-8w8fTpvGJ(QF<rx>N*`gz6JL4aOR
zlv1>;K(U63vI-Ro=>=b**c1)DRf=nSz;Z>gladP63Z*-JKCwojr$11w;uX3#R;QT$
z91``4<8+p8P%!7vx~dpE3$#W>$_L=QuJ|edYuTjun_h}H6v+-StyxiX3!p8E{5o*9
zDIWSkQ@cWY7E|g_{6fWGor?2x^yyMCDXGw-I8CozYp+5ffW%FO%oS+26i29jw@-1w
z7V@_hKho;;E1Vr5F{ntOeR)Wc`d=VWaWWWV!-^$z@BXf0$z>QiqKHd|_^6_oeCaX8
za{3{SE0WJ*Y(nvnqEGh}5_^E%SG-_^+DR+a!>B1m8hOgoin<MG%__X5z@AeyQWE}w
zBIhPpA1dCaYjU>A%Y4AtDc4XS!a?a%1hXBLwREOEqV)d`dYzO9eg<(?uI&S+tFnGQ
zChDf#bsa5tWj$Rn_E4TH1@Tl`Z?1>Dm-6fl40<aID5!H(xndfce3e)8pvh0E`xMyz
z$_F>l8KB(U2@<G$@=e$jtQ>k8nnILbbm$0G{zO&8$CZzNjj<ETY$_`ZQ{E+)AW|7i
zC0bF+9t~Kcl?OjUXPna2`Z&ypS1vGOFhSWw<+w@8A4{R|lrnKI)F&%nzXaA)<&#u6
znWl`UV^z9xih^dDN?QtSXDL6p50-4@@>OV^QwEn~O6QesU%;kZW&FPYyP(ul0-!*-
z^>tWZsI;E~%0=bcSbF}7l<MmkELJx1VfQ6v*-3O>R)(aZRi^BT##p)1fpP>D%Hl(i
zuT%~{0b{C_d@53^QC3qruU6?rA>}&d_X4P|SBj~Aqd}QRVcSNfcMHU?D}SdzZIf~l
zd1o!kc{cR?wJKM)!<shbE2+TlRL-r0!Y-u)MGLx>VoKHbD3_dvie9Drmzd~HWjei7
z?<jvyK<BV>buL)$DoZJ(HKNR=LeEj<cG~X7l<y1xY+U&%d4&_o6gv9cQ-*H`%6;Y2
zk@WmcD*a!9-YKQZ0-kB*MRJp7l#VQ*%_@5-YCWfX_c5q=pftY?@=&?f4xP3t{*O>$
zr>drl0`{u6$lY*IZ8`ujN7ZIqupCjf*F(LN%I7t7I;);c#gtrB$H`%JRmJVZnAJ`7
zWCCXIu6mIU*dD6v4ygB3eeDHoFV&wvfOxBZUIhtXRck!t{Zxf?lh9xFN<JnNpmKHv
z2~^Ec%|?)FAPr;3RDbV=!eG@ibV(~j6}B3!6ROw(7#gNJunr_##X1KIBdn^Yb1)dG
z`hjxRQ7UOVtcX@ULYiV!B6=Ces(ySGpmD0EC(#+N+VDQ)6IAa$h506`(&?c*srn=i
zOPZuwNVOBms>4*mdRnzU6eLBpC>sK)ss%NGPE%E;gC$+1yo=6Em323j1!t+2)4@Jl
z<xRDuIV$<H&~#R{h#c*6s->}LomVYb2Mcpm<<EdKPxWUEmLy*_PN{|qs)FS}DNyaB
z`?!UwuU>?Tiz>(Ov9Lv|_fCM6sQf4eby-zOr}Z+G;2coORlBVI0Ig8jL_?xdbw3BK
zDpf@iB(A9B6~L}mm4AS-8r9ZUL26aPMvywyw^txvuX>jb(G99tHON&}s0+w7)ia-C
z)tXcd=`iMo>LL}sG^^gC7-frU`w%p=sxGv_-VRmyZSp@mRqxZAwo5giJeqD*Y6Rqa
zRJB7;->W*X1mvcQR|L*mst<p|lJ=>5=pc1lbu|;DUzIa}&H<Hd9#jmf?5+c4NVS9Z
z*E_1;Oz0d@CGla*xax)fTzQq00+9DqF@<z}?Y`;>`gX~r>hpiGLQ|^W)<e^@>a{N+
zIHQ`Nop@F?9fr<1RmaEB^gxwSfzF4j!{nCPtDpP^#6jKc1%;04TU1bSME$7_0#543
z_G6;XYL{zJ@1kz<2d1m~ZZIb3rap_!%euf_{k;O99_s5`V3eo&(;~?Gs3$2BcT}y4
zfS|8BgK9VY)SIZ}&|iHd2%rJ#dJ2vlQ*T@hy}|0ac32;x-t`Sgs5*5PV8_*qT+uqA
z?x$6YP^VMqAyPg0GpvYG@2!CbYqa`uAr!`_9m>#*RhJ(HXq?)28Cvn`!zM^1sBJbv
zB2m2}3TP+QJA5(UBz4v^kjqeiN+rK%)W1-;Ia9rx;_+GPSG+Nnt&Xq*SdMz&zyAfL
zPQD1abL#0Lu$)(q@?dtZRUQ5=XrB5Js?W<;7dFDu3+gFPv<lRhdcj(#e*6wv7u6O2
z0If*9kcX8mR&VfviV}6KGdfGvhiL1+q#maD=VkTpTcD{-t))X!x%yGs-7D0#Zv&-L
zy^?NFRjKRxA$LV>eex?zty=B-JwR*JC;Ty3t9CmNQl}QIhl+aj5LMGOsGUz>_E**Q
z&tjt2)DNk8p;7J52ljRK(*_vYq&{^H>TjqEDRI!OK1^qx7Io)OAg$`w&mq^Q?z#=q
zuKsNf>O0h{tQ2VKRDbLOO<n5Fix})y|3zV#9(51>N_*AkD2H@YeJ}+IZ>hhZ1?f|d
zj=`AQYNrac`qdNf!TJGpwHL$()w2g6Fr?<_VbdM;HZfYm>ig~BysK{U1<Q!~`)yD=
zsx~xI{$WfVL~-VEbrc^G6Y87y(0Nb2jRG0>)t9zGVp6?}F2hZ!pQ{Duw0b8!)N^VZ
za`zvogO*`357i6ltYxpUrG3gl^DWi1IcoOb0Xd@a>H&+BW>p4e=B#<|0Ki-{Jxr?j
zchziMh>5ysEL*|qu92()kB7$d9Y}a;vfqIUFU^C~XnAYCAs5$2BUOU)s3!O`5MRy7
zCM>X@MoN2;zef56<{PA0OKJFH8Xvl<AFL6sz|2B4YpF0iRI@)G8jfqefMai6a6)t8
zG4zIM7E^ggxMtQHpb?s03VuauvR(vQlxFP#j74kgDLWRUseKLR$7-^b7>m<9L0P?c
zO@<7hCp9lq@oAE#i1y`E8e7`>lQrMIib<T-h$g_2q8YSc5~-TLMc}liX`0`J`gD!+
z-{8s6yhA67GaAtq$Y*L+>_#g~V=o44wr0hnScDwS$M<2{Sxp*UO*p5?qLn?bd5ba*
zxtb;_NX*mhqtDRiYozbO-V2(;^fE2bc#$JksCk7hg<aId1;Vr<tERgQg2kG$51_C_
z<4-U8Qq4LFlV8#tr@Y5yP5hUDDbqZ94Ca?>3O|N?g=T^xmX(@AbW6WVvo;E?E1C=a
z;H=jCLoRuZCeazKTFns2)oHe80jyp#eG~c`G&`0;;Ht*zLdU^t8r%8M+o&mj4&=IK
z4aJ6<G++1v=7#3y|3P81#(E8cEt+rV1FcmvpAsc)n&dO+Y}drM0j)#RLvCHC=3R<1
zbZH#F#3FQS9(@tZ)uZ|LE3oux9?~U-K8=P-es62ytkF=>uNkF{bwKmTQnUs&OUdgP
z(!7@r`8yhS^5us$rcDsMt9h2nU`8~rkwZ1AX*mLW$24DYfIY6UrwwXCvy38X_cVrM
zu<*Vni>`A`YMSd|)0E~LIwnkO?$9PQqv3VX@n}}#Gl%A!W}+564>XI`0sEmwxEI7$
zdyI;4?6l?1n1#LePy{+1wBs9~&{2#3XN!kR8*&w9J87*cKylWF{|UV=+Fq(LcGYgC
zaEP1s+Yq3*YY)5&;-L*tU`n3al`l~K-AlW{1bJ_5IGwzFv=!e2=BPH@gvt17{~Q6U
zpLR(aI{mdf_n;M^4W0lA)b3aSxghP~x1i#fHh@eE)_zIZgb=N>1?oe!KZc?6xHdEm
z&?mH`RG1W|O)3Bh*WUYr>dzvyTMA%sq_+A8kSOhe&wv)K{et2VaavIVRK#l&>8VK2
zMw|q8qSpRxv`%W*bHS3NZJ+?iDXn}xIFq&gThKbK%{KuhMVk~3&Q$HI2hmE?en9(q
zy0)|wof%pu%4b>6XxRevW@>M}fF;e+uK5Uq+1eob6iSZPhU%)$YC{%)<(&3UTG{j3
zavrS6)s7@WVV+iY8FKmB9sfY@1#JWQ=>^)28jwP*%TaJ%)IL!QO-0&gPXW4E`@<+W
zOSDb7=q$Br<0!&(Nqe1&2`+0lya$D4+GR`(mTN0M!0J_KTjxVlrFPYaAXVA`+R(3P
zAFhHxwe}W8E^4%DBT#C!$LMNNo!0G5=&jc-qr_~3R?b7`Rc+>zAlI~c6r^a>Zcc~5
zb*=R}T~uw-ezzYIH?+I~kY=rvYM)xPEgn$Os<nFwYtg1H&jo4M#-GMobZCQuKsvSK
z^fAUB?Fczyz1lbrsJN-!(gVG>wD0wz)u-J^pLDpbeS$Kw{o2;u;2hAZ8bJoNA=W!s
zlOgTY4j6SuJ8TDq!`d@ct#Mbomrffa+Q%kg>8Lh=a`R)_Z|FH1*UqP-&xDqB7@+sG
zJ7|Zvul?B$WKz3^az|6z!d)QK+O6w>GNa|VqBX1iTLYFkZSNwWJkTz;rJAjW+V9BA
zvem7l6qKDV@g~&U>lpJfH3wbM4hTBxes}@oh%W7a;B?YeQ<%(I=ld35Ty$U3k;zrJ
z?*zu&bQ2VWa@R#CqSHf{`wG;1>U^$3+)Ecq-iEhsBVCsF(JlUq@()LKA7sENUtJQt
z;r(<k6@$lLXIKoh0NoWWGzIFIRL&Ws`{7A+9@FK~?Z05%+(yWS=rXDPI#ieUHs*3%
z_Y3VzCv+F<!4jss`W!IBb+1vWSd{J@g;=6>6Ja1RI#>J<tqbCHKagvlpxaGlzKOc4
zLKu8Xw^fS;PS$12hu~@5oE;>xb@%>&rX1b7luJFU+p-@D&*^qoLeqI&#ABFtuFmij
zI`eeybb`s(#n7Abg078{)CIaCs>&?X)h&dgi@Jh$fMPAuu?wN8ST{pEV~OtgyU<js
zlhb+XlCJM3n08sWClxGZy7w1?rCgUK226!+iU*cTo%}rrROxKrgTgDi*R)`%)}>CN
zvqo3A2y(T$%am8D(>;9~*4OJKg)pW;H=llMS5-RarvP(Jmri#P8+9X83v^w#BMuTx
zx=u0XbVIl1FhHAiA$}Lqm{#U`KzHcYB6+i*Q|C!%$}XLnju+j!3zXsL(fQCfUwU;5
z{m{Cpb1w(vE#2WrwEA@M<U`-qt#JZMzfMjs!vWoX`hyJW*c5Re(ha)8z&pBQe!v{o
zWp%-nySkEcv_^C_))6#Eb<<ygbxij$IjZBj`Q%_v=;CQ-xu^Sr?oHp<Sx-UJq^|!t
zw5D`ys_UE9Wm{p)jBa)x$OGLaia0#f?X(59t$s}s!0hyMO;|~L{Y(H9Ip|-?hcS+*
zoPfR~`d?n97nYO$r@a7m)(5@<Ru{b|T?cd3e?{*-H@#aj(A@Q_Z$hDmzCH_Mp876I
zZh7gOC|={Omk(gfN8dz6T}Smc3K-+7zv6+GpI-VB{rvT3DGwZ=m(oc(P~W!`Rs`vn
z9-{Awh3L1_J0et{Hw*0J`h^o<J)uvF08E(vZz_Ze*Z)kP0f^9Niop`8KRW=>D19`+
zMC)JJ27ws;O$v+0>f^40#Oa?3z+B?>;!Pk4`lV42NYw9b0oY0XpA@P{(r4kBur4^I
ze+P+!1<Cq+ssuc(k59&6ioSy4c&YmI=OB@$e>WSgbbXB@S{eGi`7q{;{*T3&cBX!|
z0<A24?S9B*>oXRE<mi!_!!xD7_aVqR{p+8AoY#ksfaL0{=+~8p=|bF^um6>z`WN*1
zm(W|FH_+L+Q2zwgE?m^xQ&y}<KSxEv#d^hum_><x<3+%f>YrT=y_fVA5AcV*tbh6f
zT4nl>TNo?XJ5!ppLO)2ckxKoC^tZ3lCsFF?ivB$jTGjg3|H7<mtooCyutK%^hkDGg
zPXEb#SW&M(@D=16^i4`Ays8&aGX9!Akb)YG`phlpysp1Qf1f7(p??5#Lmx=bPqRMz
zCgfW5>GW=C)t{oRpiM7|g+QlX@h@1q^yB0Lbn7`+F|!`M^@2C#d-d71u<fQkbq@w_
z=?AHFzE3|Xh5T)O7Zr!}>))sP^a1_ONC*t-*F1zxLwa}mYu(XL4?=EO-#|5ZclADx
zL3~6XpNX+iy?GR4V|oS^&yDNfhzHn&{?I(=yQg=vQVs2Wy`HwmY5f}t$j|7V=^Qkx
zXLbN)PCx7p)(84#dY3-bmq%coYz_b30<kmfIRO>+29K8^=U{LoFU8TY>=BrD#1KJ=
zBqsx(?xr~#qUh)0Vt9dWKe!q;QSivk@Z1i1VYwSJzXOklVI~$TJPn_32b!0`LMJtE
z!%~9rG5kQ0%A<y#=thUHp>;j%^)qZDKiS_<`50OOhP(b43pD8KAP{6Iq^<0j!TuTy
z4K{pD3DFRP*K25n8rD)G_qgFs6dl-37=9+7Hq5Zo0VLdDPua%^L*zebMH+rh0d|xj
z<O({Y4f_vZEn*DqyP-GMkh}(HafaWSus+_9?GKg&!_3ndOEg@d%Z4Wn)t5n%3{GET
znNJxGZ$K;A@Yb_{K5bakNe*L*;Tv+rQw<*_fhW!Iegfpv4Pg^ls0>2^ITU9Mj&m5x
zG`vDlvMj>~loH7{d_D#BIR+o{6wexpxM-a-yt4^%=MDR*CMMUATLgu9h6P74mTy?;
zjm|<t5Z#x!XxK${vDPAkH|5=n4Z%-=r^HZx1DZ+=d+0-5mkgUI5OCS>9u>Nk85UB!
zwcHTl1X5whqY8{lLkGP*s|>uuV7X%W;6=2m4FN2O*BEZU0u{A}U9V#jb%sH58tM%N
z^kQx>BvN|ys?{JP&+VGQs|Tdf@Td|qyl!xz&~=l+Ne{srhP@U@G#mC(2C2pHqb<yD
zHQdR<SexM%m94cKwvtEQVR+0ROWA3Nd=vs*hT<|<*lk$%5ukev?sT^5HKe$L+%yC=
zLGG5p+P@Q^eTKp`7<}7MPjBXa1Cmd8)C}*_6^B8?A@ZY!42S8i%^ib7Ca{MM-M_;8
zyM`y+Kt>D(5l}`An>PVv%;4}M$he{VIcS<NWM@O}o*{Vw$bCa<J~T`kmQ&_;$`EIz
zx68D_Jc&8Y7@q2Y;H=@{C*YYg#NNT!1H%&X${re;=0U>NXr;feow1X4Eqh~776crO
zF;oueXjFQ@>?6i3D>S(n7iiJxYP|jySlo<FlxcG}KJI`e@h~Q|0n^jCd@ltoy^Njj
zLcO=qw-kat#?w@VcGT#y4idh`1A27&86PXb0{a^?r~o9uIDZ>Rps|C31VP4(evo6v
z-4v1yHvUE%MTjwgwz5#;M?27Y+~`bSc{yQx`*A>r8Gn|-rf}n9|6ed|to#HLk;a*K
zpef2YuM##z8~=)de2mfS09vuef9dBHXA~7cFy45aVxkGgrzjVhXncoKA}5XPvlvS<
zzCuNJr;JyqrYzYQcN$B1+So)FGg6E@x*(ToG*Ff&&6xN%z5mjUN9a>38OD++2%a&j
zwJ<o-xP*#4vW!z30F!N8N#&3^#)*ySJZrpIgUOsTE}*+7=ZzEe+RrsgieY`8vDXh{
z`9}M0fL$;~(P5#$c=rXUFEk#e^4g0=-)A9EWUQe*+gfZq%!WjXQ9_?DEj4~P42es|
zRa-Eb%f`2}AW>%AO2651+!zK-g>il|SSpQAY0;`Sb|_(Qjd4X9SZa;Flsc+2b}R);
zz0uzmRx}v5KL^gM#&nAIUNdfe1CwYpwm*egU$+|5BO%yi>?hV6#_v1OYBsJPg)uG0
z00u~_QIQ3-He<qOu(TV+djQj6{QDv}JB@egG43+%nvXek8(*hjXpixiR$%uUyPtuk
zo5pj_5Wi(CHe*VC#xc4yf7|#Kg(mxr)`|caJYZb&CnN@qPg5b(knsd%hwm8G6pb7<
z2EByNyT&)vkRLIAU5>F)V<!do#*E>#6^<L{*#mUKxHTT8-7}8TR(Rj|g$yi{Mxi_8
zri{<NhSs$4%Qh&QF)9{A{jBjr>obs;GZv9+@W8nDDYPCM-=a;()}*)#7(3G>-TksR
zZJmaMgXvqU;&e2<@f{Q%G3}wncQS3<1S_0PFVjoW#l#JP3RlxRbdB20^cdYFaW^%*
z1oa*!2ddceG+iQR*vpjcPLHa$=_yJi`<U2&gB&%j%Z5T<6OaBtex^Q3UWS@nC^&K4
zl(QC^PMG!$K~tEiFb)FYrmqj6Gr|->H!~tlzx|5&Mw$HRc5<{y>xHoxlYc$NVoh?2
zmnN8&Jr40iQ?i8;b|+1nJphwrdc6~@r%XG41W7iz?E*P%VtoQjQ%s|jAW1a|$+Ji^
z{q+h+x@mX~Kr>9=Q|B2|AbAFvrbv3ZWtpC!6LGf5IRRGWn2u2_=d8)k39WOcTnYf3
zH~AM(!E~-k{Qzrn!Ss9|dJ9Z7B22r`l&b-`Xqxl_DKdFd(74#tF@nE+iRnEdU`kDE
zD9m)p^gE?#E}Ql&L1&ri9;FY;O&Nobt1#Ko`KQv9^clvgOs5N=;fks7H1t)Q(h@Od
ztueK|0K02VQ|rJ}XG;GAgY~AC4ItM{+2k-cny&8z%XQP+6jNz3X($?U!*rkmdYetV
zC|cEG8n%G6nhf-fs5X;5<w@F2A8D|79j3?ikn1$HUIpng?V__zx2cK#QACf`lx_!@
zUXw-(a?|9{hKb%XMT9_apDBdOgl?POS`OBJQ=1Al4VXl9hhxyB{{$>Ure-Mw?wDR)
zjIm+U?ITce*EIeBdPhu=v{8(jV*dimnCZe-=o~k3r~+cbw2_Xv_e|F86|m;M$)AOl
zoi_cD11n}sw|qfnO)DCqY0mUsB3chjV;n5$L(@wiqh)7)@CXF#%~eGZcQDTkLa(Da
zg<Odv<|A#;>tueR4lQSM6(4KiVjj-~n5+5AHt2OTmpzY8ck?0PD0n=~n^ywH(|m$1
ze|VW2=@sj3F3W&~k2%%vi-Hwa9(lk1<^z-w2{3Oj!E^)7^Jk$b$ozn=4;(XJFM>(I
z=5HMU9b#TY^_rpP$4dZm+?+;VdpKdf-wNa~vkMC-;bxCgv?9zhD#wj9Cz0b7WnM=|
zv}p4rJq0ml2Xb3u%^zFWfX113Ed*%1dCD1Um|%`1ry<Ea{V9w&WfoExFxgzu14B=n
z-=O$Viun^q$fcT(F`y~U{G9;e>1Hj(Wi!l$<={MHPN8#KruhKvU0LQIx?oJUc`GGu
zbId=}kL0Y`<|jHn7Mk@FXkIjbO<Pfsd6wd{#bz-R>PyUNe?VcW`Hw)zUp8NP6Z0)I
zub`Y-xtX;Eq{93Roy056%fAH66|<In!)mkoFO1cg+bL~UYaUz!usZV(wDb*TfeXg2
znkSy3!nSMX2!Avi&FTLI70g@c2iRmjN~IPz%x|0lTC-UYj;XbnPgOyEtNFeevuHCv
zFNWTB^H2<C*kRtd11z29JxjpSW&ZL8R;Jq=#DjQ`Il2y*z2-OQJaE(e8zuN|nfJoC
zvo7c}$GwZe+vY(vK>N){=&sm+`QJql95io!8U_!UCrV)99rFh}(K&36i$UwI+4UaC
zh<Qf?1V+uqwNO81?x=uG<K{hN_JnyIg$(YQ%in>*`(__4Oq({Fw*Yg->_mspWwYit
zyP<y0e7_sL56lwZq7~K>IvhAyid#V(Enlq!<Pl5FGDtgH4pAwHi=~+bb*`2)`a`%`
znkba$ZgENmi>GDPT`ZlKr8@(h-j)*-ne(xH-Vc_emNqI#@wGhchMb>eA9+~*7N2K9
z0xWhEJ`S`ntV<ynWa-KP&oPUf&b7gof9dLAh^3Ld>`+U^2S7V+S=xbVp0GS>1_`sI
zQrSkh<z@PbM_79Hf+f<jY#cU4SuR{eE860A3#}MS26=t4meDXMjI*r20upaowh=4|
zmZK`a<;4u^+6eqrlPx!2!`Nv{_h+yr#ln38tyIhXwNR8{v4&xuXDpk2U|FVR1;sP7
zEafs7m~CNE_&3LrMiJL@mZ2}uI&Vp(?-b@*luv;(&+_uKm{`6g@>!@Yuq>fRxX`jb
z5||e)jn)q_SY&a{!CZ<h{h8n?wY=>M>n~Z9RNQ^pGW8=^$}Id<5G=REw1cz4@_-Uz
zm6rLmH&$7eQeE;D%VJxQYRkn5SYKlq-VYVEmb3qzUMwC|R9bI|Uj*m|%M88Au38@N
zqX5)3i)|pL)@b2yA#vRj^Iv7KWdlWQZ&)(uZ{BQ~r9XCyMRyF?t(IK+6}4Ha@4<?8
z%M$u&byyBk9-`C2q@!+^C6hjS)opQ2hj@==RRav|wQN6xb-HPJEgWiZS<=?hH&*&A
zGX}8Uwrn?{chJ(?1x-ViMO2}5#}fMh62q1S6l}a}c|ru15sQ8$tQfQWxDs;X7M&QK
z6PALdXx+28Fkr=f%cca#O<8`V#MZPW_z931iyNWLS}d7hnX_ESb7Eca(6UepLEF_I
z*+Z}0YMBBp`_<>7A@8u-_D5LZxSB^U#*x*}PzJ$i^{OR6b6)+`|8aEPaa~s5-%PVC
zOKq8DWo2rbS&q-%drz`#YMEJS^=)ZoABKQ}2(qU#WQmBNfb1cAD4;As83H1*l%*_x
z@AKoI^E&s;dq2-}$2sRdP|W`@BeNP~afI>P5HL4}YdtV`#=(6U(W8tkdh$FN!4$kc
z#&8?OSa>oP(ZR}#aVrT!Vmr=gcpoOb8ShX%iw~nD6hvQ!j$;0PjI~sk>Cae2vFrfG
zXH!rU$ne+!fgr|45&R8i%o~B-5Ju52z(N^M(uI#O#(Q+GJHdG6Ie2lBQS}Mr!Wlol
z0xc1Y#&#HrWXSHKG1|t6q+47ujQ3I@7|VE#K8X;=@c9Vx@r;$U!klJ|(+NL;F-Hc8
zM8+iLWX>{@>4sMlV|fAWo@1oYs+G(TzKg~b2Jc(Qoo6uDf|klqZiPS^!%AnxbjG_>
zes_`KItY-#u+5_|XC@<=50J%JL$7Z(WArcdDTm>399S;n6DqvPV|>#Hi2}ySQjAO?
zLmmq365}Fe$%+_%Qu?NtF-5n7N*L2Lz@?0eC*ego<IGm5u3$I^gQb$;@HWJ&7#}_l
zoz;wdTL4U4W<1{q!7Gfp<YFzuj()B>hHx{~TxA3nLgE_Zrw-8S8E-X%*1*`D1i40r
zb{{}9<Kba|>x}&uVWNd$qq(`2;a?5AHy8~CXl!S!_y`6&7-@%~tdntW2}b4?L;e$e
zt*48TPX!v?3^pB0dl;2;!0Kg$L_p#WqnJ*ReGC^m#N1`P^C`6TGmg?f3?5)CeFH3m
zj2HF*3^SI^N8>$4SqI#{&j@-I0watzD##jT%pL$X#xS`-^*E#GFtkiCqEFBlXC5$0
zwgY|0u=&8LNyeIAAu-K3yBca{7{>$P@GN6(D|+~dv2YJe*fTfHL8AlnC)(6FGDq3q
zJj4{K(HCc?+h-7WVXpZf1YDU<Q(4PlW*=R^J;K}@3pqFD%?{W*%IsTC2Urj0BdXIs
z#+<$lZJtb3IC#96Ur6BaaVGyD1ihL4^sM_bgFXe#kNN5!5b$R%pe$Pe^NZC0fy~ME
zP#VHiP~a+*IU5hoFeWzz*a_x%7qFAe=L+F{I8*&JhAV>UNylJY6jSjVcup~!z64J+
zvzwxwF--Q0XpCiM`=c?A8AH8~XG&;qpTK<J29`6-);u&OGF?ui@hnqFYiSZwNvr2M
zW_dVh$;|iZT$jS!PT%M|&%7`R+688w2|Y_?_HKcebQ|-3kHP(m%&#aAl)>zM486!?
zKI;kAET&10pDUXg_8)ZTFdgrJC6AdzC#rmAvJjjF%rc526*AwWHR=-6<sD!}%uV)S
zDQ32o0+cd^lwmDnZlt|=IrC;dKn1gTKWLRqTh7P$)vB1I^qshB<|l^$t}w6qfmp*-
z(tfs<`2@vP>X`o&qVX#8%=Z|X1}2BT2-L`2NY^Qvn5r?bG&A)r5Wmj+&jF1s%w{_C
zwK6xk0NiBOr2(`t|D^$HXZm-*-wx)iO$YOx%%6UN?pw?d4&=L-uZ@7%!)&70|2A{7
z2v{$ZH%PAovu_Hz`<SO&VDK*UpFIHm%wt248(^AW#c&NW=NAAQV!pBjI)|B7TB`0d
zxipE4FjI2DGRj=}AG{c2x>;<{J<gmz2{jYUNveB&z#Lx!iAm<ECFtlBbHN<2PBSn4
z1kM@eCw9<1%XDl8?GdwbJ$?~;)|&?a99cFxnmDmuqTt^lmWFm!&MbfWU0qngG!whB
z-Wr75VV3hIaJsR!ub}nMoyB?$CXTWKzXp#7%QqA}$5=H}aQ`@KgB^f3i%t1FAJ(NG
zq0N`|(*pSG$Lf3v{`#~0tzZdYC0~VyL9DMcfd#V^QV4{w{wYDXLs_o06$xW~xD|3I
zSa041c9Jz0-^jGhk6<w<y&cJ_p#sGy);Ejb+bPz!Kf;S>*3@nI6vMhlpQ?#v@hImV
z$7(ta5YKX>S?e?_l+r&5tahrwPh?qUVDKz!TL<KlSWl$E-*c?PbP7*qWqu0_DXeNb
z%%5lZ=E8z4mGumrBhpy^P_<(^%clz3F0xi{gPIJMVFs+(tfr+9%wZYmnayQA69j=g
zmJ@+|*5lhT2n8&;56l;`f}GG;#NtsAQZXx!auy}5nq-(SWo?dzvND!8op;JvCfemx
z*jSG!c3H(Lr&X<*<@++!TxRwD1?&pzoDjNeSexgev6i)%w)J(ab!vEVl~ol0aE;|g
zk?ML@44p0;Sierd`zF>#n$enBtJcB%b=Joe7;Irx{{m&LEE^S)++f-9fZb%-w(SD3
zo%P8Huy(NOh5$NQ4r8!%izQhB-CeBDsHprl>zW-L?PX1bqVW!kQ;g2^vCh$+_AX0E
zA&GvLm@4fCSm_ku9%7aM|3@)c4_2e`9&2|iRNrUy{{&?tEFncsM_J$7C>u1!8lt@5
z1Zy`fIS*JKRDt=B6+soJldM)s$4{{a+~D^#tFso}o?&%PL)$ECNDj_NtlTEZ*|Q_)
zv2<X6%7dH}dlgl59AXc=1WV5BK+4j&uusu~>B`>c3Y~}96$unTI>IiX7?nFa=|k`w
zWhYXNw+GvUHe$!vZDjzS?A9N_;?3sA0P|tb-2}{+J#r7a{n+D6;gdhxU`Ag8*f$oT
zFM;e6cVQ`*z5OLP8p1x(1G!Lk*s~A_W4lm}{RCTjl`3vdvI8feEu8%{%{P(k^|T&D
zu@_82;uL#DGe9)^2@21|uxqK>F_!&xCgkJThiESz&*oo+z-jj1LEuba-(LjU8FtBf
z^yMsDL-pTD?6OH%ILFp#z?sbE)BYrd?THd`+_-0dL#6E(*n18_TN?YfofwjI_Kr4y
zi)`K(kjP*!@WRuQ$(FDnn8UVEm?M{6PV;geTm2&Xo6lZP;jaSr+)98#_UQM}d5K-M
z7F{Z0e@*AvVz!MI#ZvZ53&2vwt`WmSTRHnZZ}?roettc8D%qV3=&oijrb64x?5B00
zU19%AuYWE3Ra*Az*k=_Oi>vG-6bZe?zC$x=J^KYpKsK<$D68Md&ZV<*GkYQJGp@7!
zYoWS@?K%lsEBp6WXt}|Di_Q)=ZR}qqAhxmR(3R{C_Jw)S-N_Dj0?#e>!%d)dvHzpM
zaW~tZQsF)9=hnl+JM80hPppsqiV)x~``8W0^|O_0!8yR*PcP0OyTt^~AvR+W%7)qd
zXsdXS{o2O>BkX7RP&Uf8{aFYX$JiE%N{zFZQ=V;teK`ke9<q-;1UAWjQ427|UfYkx
z8TM+*($BIl(e1oP?6}WBv*-NuD}ERU&O^EZ<jDDG0GJaejZzQJoZKRCx^Uj7Y8+Qi
z`2q+W<|HS;?IWBAwi0M_<Mg_tqwbt#*WkAY=ZF-n$2iwwK=b5mqt)MwGel?T<D7pf
z597@-yaY9VoSB2b{5i#6qN4$v|9$}$$SI{jc@XE7tq=(2l$-??!ckK6A(V6MBAf~1
z@F>}Ll5@h9_MhRLt1Ey;aKdP363N*`6LS>j?j`(O(HuPmfMYnKZ{S5NC!Vg}#d8=m
zA)n^F@ifE}IQ1TI`wT}wLB~YS@9%;0EN2G;;z^tt9&{#iy8nch6wacR0OvV5v}?G)
z`Ed~?FjG0L&%nhrPS3Y!P3H`z;K9h??0E|EnH+EWf@Kybj;`}&bLO;yGl%2CL}M;z
zJ0<iAI1W76E#$1Kh4>}T<*mSqIB(J0RLnV)4N$__PvO2&&PLkGmvN5Af~A}ji6`DR
zzk*Z#J=9ck{<;fd73ZyN^r@QjCKXIv<~&XpO|EdbLBMJ_pHpI>mebM*FX}jVQ~*~w
z@0cNQjdLy%pq{g!2wIvrYw6tB%y~Qm=C5;PKZ3J`Q*#!bXys%?!Tb%*KUC>pyU9Uu
z0bT%(H?39e94m#xIykSg06IBeP&vXaPB8~|yEq4qLw7ePg2J*r95a2T`8Fr@BUtL?
zY}<<=xx?9;3%Nc{h98`{%eiWRct59{UWXyho^|kIm{W8T*gejoX^7vqaS|!gJ;M2n
zg7>2w*R?P)#`$qQl#X+D{RyQLoC?};KH!+?VSC77+v8!G<gCqu7gL;LR7x_<*+kpW
z8IDB<&RNcdKY=~se6kN(?753qL#G4xqaMgPa>woibK>%Lg66`tmC|m<m1}+z4j<;e
zP1hQZaKqf8+l}ih1aRjbr2YC)ZecDk4{pR|fMeWUD`CQuyPKX)FYX6ZX!PbTBxiiM
zrzkk=%YF79<ovh}U&4|<w~JP@0B#)BvIlaTcEC^&*WE_DonY=wieiUwBZ5E-<u*{n
z<^;Dj5Ce6R+elTk;oNH4!9{S-&^auU`yExXL~)a<(Rhj*Z~}ItxiQ<p8N<z|EK)2t
z>pEz0T+x>Rr@0G1gBJ;0f7(x-;a<B8*Alr2daCL^%dMXaki_*k4=>Jf=TSN{nfn)I
z%~H7E^`P-Qx07xFUEp511kQBs653o|<c2H<O9nUjTR4-+UH%Z=&f*&Afym|}v4vNK
z>-asK$>s7X-;~Flp{QOyH=Ndy0&egOt$&xei+_jTMcf%VT8p`lQ4X$z`;7-WTFPD4
z1Bo*3f3E_Rb5H$>j#h97sA9E}yON4@s<?|1L96DjbB6d8?tw9QU&EdM0~%|&gRj7+
zI<A5)fnDV;=fbsX+@GmhxSsoY3jM=`2JX*DWX^BoKD-X4P28ux22V3LEet#@+#B@i
z%~r0o6S{A3*U%GqlRK{%SR1$TAAol5t6L%0!JW{6vy=PmPq2H7D;+^&7k5r61iHCi
z6m#w64qQT)?r`_gj=qokA|1zUcexCzH1FriUH};2&KrcogWLwHQ61u{;~_E3-Mk5n
z_qg9tD&Rg>K>OEGZZh489OE*sz~6E14+5B&;I2!C(g)nnkHVRU+|T6zliV%z6}Tzx
z*DpZXG<W1ISZ27-QQ&#j#*N$oXwO@=9l9NO!Mnif$SZptN}YJsR2p@NSKkWEnO7D9
z;KK920!ywuwkHG*^M+}hj_|A-q1%o3Hhu8=DDMg#mpyn(i(%;)&q^0BJb53+L%@sI
z_XWUlUOBz!-aMOv<|H59%Rd45@~Xv<@Z)_z;X!|%-TP1z#FNoyzJhtqPocjdyss$H
z8_K&tnSn6g3zSnj!Mpn$+&;-WMvHhj@BC?)h~Rxl^Gzf#ol;9tyx4JYM)QPpNQ&WQ
zQe{;v?`c~l1mk$^6pWAO?WT;xX<iTo&k}gnVK{S!=Qa(AL|)?;0B3pSFF`PgxAibs
zl6ed1%#*@vorU;$-cDNFF7W0A!fq-rhbltScu$vtC7t)<e3-w;>*k}|89Z$~RA=(k
z+ic*;;*HX2G>5lM1^HZ_=`1Ye@uDc(p3m#1&2RzlRVwu<<lUgq{3V`aJxmnwZh8O|
z^F;d~SHjzP89tTr7Biu{f|p3U?@HdI4hU57oatO&&HJzyESGsg2JBtoeZ7yq_*BEY
zMmx@0UUDqd)bZY++U2Xf83`n=@sxvLZQ#93rE876qnkl%;w?ym?q;3`Ei2b~k^h6z
z7G7NlI9quiQc?L0o|z7@H+e4qK%k9RP4js>Z{`A6I(Z&90B-TFHPZR7i+8pH#BSbJ
zx-8qn)6%x#Ht+L6H1_ho4}zsTyaxJ@BYiwe0|f8#?mYsnpSR;*fI;5idaw-fx;}!X
zVcrIRbmAVbs1mN-=lR<MjPRCz0iC0~tPJ=x#{2aaILCRppF`X>!RtE&i3hxMn_zy5
zcZkj|)4ZQ42t32nQj~p`camank9Z%40NC?~cfg<n-=92m<S(Z$=sNM=ISBDX{6oGF
zcjm9R!-%@_Z`=bo%>N`6a!2@1%i)Y0|DioN-TBYG3ulhn_}-Ma_24sqfYM|94>qHt
zp8TI9LG<GPRSn(8`7RWO@!^-!jVWLLIulIz@qf7hIe$L49E}0|(eL1IAb-s~U_t!X
z$zU+QD*<vL{8P7}GnBvnYv>H)Gf!YFPVzTUNn<$Q79<85!C$}!8p-dV&1DqduO22&
z@t>ud_Go@pG8$v}|Ir*6%MZ&zpW^ttsTeVy{}HWNXZW8|Ts)DVO~?GR{MY|RN0a!B
z+wkHX|2Zl_PUfGYLwgGU(`Lw>=ijC&{{nx7?KIF-zFi&AH2!ooBrft3cR)Ua-%FEc
zCSOGx^ep}w0pzp!8d^<r_=hWCH<v%o2Q81!a0AHaFIoZD3i!?x4=m(6(3z)*??f4c
zV*Zj4cv!+e^gBQ)|LZ6iD&xn#N&C-oetj<FEBHGCAz#U#+6hp_5BLtO)%+ipp--3j
z$4X$nhX3hP@VAz~f(u$5--B`!SNVTWz^7~cg>=lX=dTk3H1I!CLrWun{UNAs;)jO-
zYv%j4!kO#*^)d+D;HQn#`*)K+PTSEoe*O>8-N`Tb6~tS7zqir*E`GrQfPTK}I1CQ(
zE2(;Tknc{H@`v~i6iFZEKV<~C$3H?d#C?9nX_y${KcE`BQT`DbIylA;azrP_`9J&#
zY=VFBd9Xa-FG0_2^B?lpeGJw~{-R$XKgFLt3f5`98x=^-@Xx;kiCO-x&jB9s7p#CY
z_5#^Y5O5Im?*ogY;LQ?r%}L<;8yXJ@K7JnkbrwXb(Ipo_Aw?Nn1;70d1`i7sQ_biR
z!5(_X-2^U_O|!WRPSF=jj|vo2o9-bPp^hFCj8Xl9r=XA~I4^;QlC#GJbEDDdE%?$G
zn2$hg1<hCBMm2?gf_GmA&0nzEiop*Mcqc$hprA*M#vno47Jy*ESM)1~2o}$UT&RFS
ziM}wKpp+)D6M}<Op?FeIN#*w80s|fFBLr*dM~@WDZ-CM$!4TznP6>XaJ3rBaJt2^f
z5g5J&XRM%o3@mYi50+y{;sqgV0Zt3{Qan9DaPS~l&Ims9Mt>6p)7LRFX9Zu`!|f!2
zEuR+7bApX4(3&i$S_6YAf>;(<&kH`IS?_}2PB45*72K!9Lz>`^a?sKRz1Y0WzbIIj
z58W984ej$Y1t0E$K$c*7FB)?N9#r9*CunnoT)yDL88}lQ*hkd}g@RYkf#s5*)JD}z
zMS^GJAzv&=%>%JSaBTy8Di!o~11l4}ISfnXg2!m?tq@$G;(|)SU3%E61lr{guNK^G
zh26`7vb_+vB3R}KP$L+klVYu)lit5N!6qIWuL@MrP<>6XoDwwk0^^qy25JyIH3#yI
zf-SvhZ4%@qps`u-fdmrQ1&`l=nifF=rIA|&|Bk`#4Z$M|l-?A$QeAbMAf9d)wF~}j
zhL#S&iVm3Q6qNr0?3Um%1?0K}7tTYVTVSBaqet+h2(;UREs_79{}ZUcgPJ=6+bd}8
z6G%(Y(Yt~xT`<@$sG<^<0l_jE)C>y#qqlKLV4?KXu;6|sSndhNXrp~!;57<tL?EL)
z^r&D#F<8a~#wOSu7x@1H4<`gaUjxenLH$P9dnhoYgSPpTg0E>$JtYX5k8V#3iq3&&
zM(|rayqFbip(?dUf{$N>QhQ-tIFvdFcYA@wQ5Z_;QYYa7Dv~=SoLLE_&cYcA9k>Vu
zKZ3<onEM}GJ1jIW1$IO@90SZvxR>_#?!v`t0NYVvB2`6r2)mBLQ!k;G_6x^_2{UN)
z7EZ>azdpiRDzEkxx-N!<pHNJJ8-HQpF|Y&(U#3!&K;eb|uO1PmHUSG3PSfTxL>Nt*
zyilQ%3Vp+bC+NLDA$*gvR40Y5!Eig=ChVg9T!iq?73h7WkkJ8Rl<-SESWgMRPXbT0
z@WdLh#0Xb@1rRHIl5R@I34N&qEnfKYZg8F!e*Y}IPY@nZgLX!^dI1I@QRs67EN6xI
z8V+7HA>Rb?bHZ;Xz?m$JdJ3vjgto=BEj%yW`YX^2LKlh;qzcRE=#wT~M_2yRg+}t}
zqVNGt?-@eB5U^wl#ZQ8kB^;)5o^0WN6syk>u2O>~SC~vu_B>$-&3c8xo(KqB5+>cl
zSQH7LQ(<I^g)3=>C=o8R?S}4BA)hAgG9iP?G|Pq0(GpuB{Ekv*mBK?*MpPxNqcBXh
za1P~XFAINY!jN7O9yOq`M!5e;XsZ=YJ`eG0!WLS9>V+PZLTV5y7;v;vm`Fk3CgE+0
z&NmC???d%<;RjmEKePxt%AlrISV=jr8^Z6Yn&_tRS=uDF3FqK%e!KAaHn4OE>nR4^
zDXe-Djkkn{=zF?dLJb9>x`p4<L*63{r33bD;clwJ?G+xRGTJ-B2r7*16K;MAcJB%k
zD2drG{82|=JRA_dKNp@33N!3rcSyLs0NAkbJ{N-bgu-NC_l1G&urwlkiE`GXLeE&p
zj|tDx2PVgb&r>LDLijBOULFXKaDhD(`f$NADV(I+TT{Xf6mpyvhIv5ejBsN<`Z+7?
zu>1e~yYOkchiET4|0i@ih;Da-)luZK9K+@$>bnhzL!ts&4V^{pzW}(1t}X`6RrKpa
z2pkrr?}Wi4A`PWo+(ZZef*0;0?moDERJ5%W;vOPDZ}jY#$nXrrJw-ivu;(QjQUlnI
ziyU)6^cL-;l%0>rP7ZCpq8oGJzMtsOI?((@9d2k05KUTOFi>=#c3D9p$3|ER7O{Q?
zXNYK+@@S!=ec!>0Fi{p|w@-*JUWd+;qR(H0rEt;1GJputx3t1WitcTIhfy|B<qpWl
zh_=vd5G(Segh`xehF*Yp(R4VJo)*2h6^#j^52oPE8By4Im`D_Dp`iC!ktiQ5Ng_!u
z8qbNoG672#ZKp7GipWU^E$2n;^m(HTqJKT0B~{cz^~q_X$_QZTBHL5WuzOK-n$Ei!
zqUpyWktx!D0ySBpF-rAii$0)2{Txw392#>)<IjRKPvpY^mM@xd2UZ}mIHRM5qDp^&
zOCsqX&|M@d34*d>(JFdzN<_nd!{1WT2cLjeCOS9?tXvdq`wS*3M2}vCwo1|cdSF!|
z{zYKbBKJY)zAVb4alRrtnE`DzqQ7WQTq~-h=whAd-%xbss>tIAJiI1qpzp8Mi$0{i
zbd$(Z4Dn`BPYl3yk>m*ET14M}2U@ErkgD8nh`ds$u==JbF%LX#q9qh+X&3o!0BeWn
zR|*7nihA~g<(BB1?GWq|MbZ-6ElQ7uPd%a^*Q4>aD1r;nE6SP%xFhN{LZDByd=}VU
zQDGL8^^1O^fcSujPoF*-6b-~dd`L7~OE(UOMKQF6x+f}q1@7M$wb5Q;M3kF{u8oRr
zbI`Rh(IU#>j*FHog!u{42XuAsfhg)a2JxY&Hvj^YBKA9=O^G}ye=sfDKyiT?(Ti1(
zn-y)}4P}o+m*`@Fy*P?W;~m6LBj;qB?<l@XM-V4*O(%$l#P5CzZO-Dl1(0wN8!1!i
zD&D^m5{JcOn_>5eIQk#3xQPo60Jw{dw8$J4FJA-m9%2a<WF8a$sDhlQc$|_>UgEJf
zcyU~u$ONai`14EvAMsoNz^u(z+)cIhequKTfWJ7F?i~k+|Dn8Ap!kzLP!l9hdJRg0
z#gR1Kg@`98eiJIbQwKF+;&Q68J0adj6<;UC`(J=uxY&t`AtS_@y}%;H-?>0bl=wMc
zV5h_n{)Rxb*!nfh$JoRHlpTl_zk3|N_G$5b3Z*583+QUv8F38Noh6E`HE295c2L56
zl6diIfOF!<7D8#Vc${AN6tO4eyv~b%I0d;2;+3m0PO0MG=K`dOUG3poy13_K*u5xz
zhjLFD;-TG8ohi2Y{{uBy;%0gTvc+H14cZ)WM-EKnibWJw%o8`R1IQPD&;}C)V&?*Y
zLh)&AUglpCo0q{vk=Sb|lopFEG$bWr7piJ46>p@;t4v(T1WUO%n@S-n#B=p<rcx|?
z6ZWdan{6D7Lbdph%P?_SypFa|SHySR;Zu#c?Hy>V6@Os|TAlcx=K!vXv#CDfns_4z
zO6$cr-+-k-`~@w>jbaNuB~9W>x53#gK0up*R`J_PG~N*VQ9Z~_aRU{;w25DifotvJ
z_!ns#+ab;#gKwSU@G&@ZOFU2k7rVrl_Crm#_$Hkud&ED}X6v@NX*(?SieEYkNAHMh
zsrs@{97pGayW;XzfPS(32;>IDA?;8$DApyz!jSmTCI}3RFK&dt_r&cpuy9}8vz6*!
zM#KT{!ThNBQ@Y<hCT^oW$hi2H9;_4MqEy&@AP%ALuRRny9tW5dulfy*Q{uP#!7?r0
zT?-Fq#N$)}GAn**9Cjaxm-)b;z2sycfP-W)Z3i7CQaYGBNk&(}?L(3*+}*Lwca~@<
zIO8H=(80o0^1(KEaadB_0BuJk_oy7*P4YN>h1gwkfPR=`lHaM0(o+)k2fXl-v?oFQ
zxTK7>-QJS)1#rekQgH^2z7oY<42hqlnkshvCFbv;IzW>CFH{FgLg*p21xa>Yg^6HE
z40SX_BBE6|RKlmtR+!}4F7!8C5*h)e5famfFcB&7r`$x8<nQOur&AIu#VVpDk_ae`
zk(4>WM69IcC_tQKEE3A%C01I!PfM22{elF^lApkNMp8lv-9($@4?pmnmAtzEy-$*S
zxCh$KN&e+Qcd}&pbMPWXQvNCg&r1$Y1G^ykou0W=iN}9XnkG3BgRZ4Z=1~OwqU08(
z$}=SXUBEIWULBCjlKend+Oj2ew4=|FJj;TGTuJdYu;fW>|4`jPz9e8TcnT!5?f`|7
zhY=9GBzcGCn<9xX&E&<BcPZsvB8jKSRH@_<eKD#`^64CyFPD6=A4)4Eo4F9Elx(Eq
zRFx!z?iW-`{<sR-Wy!pk;O`a54An=}N?xHadDTg_+UV<qS0$}d5U)vwK7}*&65e0v
zXoF;}7NAiQPMMh|$?Me7W(kWTHP<EkXn<QJ{**FnmE>In=MBkAFGKfD$%X~+qD}Jm
zlW@CTGD~rgTap+`=ypj8sHU`AGPWFzJ(6q}%0JweI0r&$uVevDx_2ZiX%^{|ETYHq
zuH>*ET<e!C-GXipNVZXd(V!$u0BlI|mIqjdB`>`RZTBQW9nf-LvaJ&WBNFeYpk-8Y
znT^IV$^3UAH!f+TVBLgdh)NkANES@f1>%R2SJr?yDfx|}8&i^l7HFH6h};2YB>Spi
zX;u;x2=^aJN}Zw9UV3aAz(MLsCm=`Z9tvzbNjE=&z#(ZTZI7I#S6_xs7isqe&|Iaj
zzXR2Wr6+HJ<%sm+L11puYp+xNnY;An$1rhJIzS0&4{1vkc#cVLorAom^zl|`^OAl~
zvHs)IpDDoQExnY09{Na&qX2xRJMsYhq-r`5_)E>%=x=~DKNdX<l+ODd=7XfhM^F|l
z-9|G@i1ZK2o`g!Dj0VjXCf!CiwoXXpRDyU?>Ofi7aOqr{^CP6cQCu%lx~u`LQPL1f
zYMhd$48UNt)SfQk#7N7Jp)po!4ThFD>736X5HEd<4*jR4Z*bv#g0z?p?PsK!LC~2f
z{ogn`aaL-70a%hv8X5t3PWp8U)FeyyX2DX5baevc&r91WGkQTPrWZa{+Wr`@G^rES
ztENkt`2ZKCPuu}5L;7_G1Tv+%o3NB6Wl=IDTl$cSn{%Wuege*1=?^r8=1Cb8`OlYf
z4}r5lYU`qBy-@lIJ*>s(44f&E1}e~4D!o8~n=)yz9uno!0DsUbq)*p@Rw>=;1X`7}
zvIVqisUi%t%hKW!Sh^xL|BD{hNQbilYNhe6uv8~?p-RN7(tLl&U6Yoy0@O=~Z3U2M
zkZv1=`9^8SSx7WVlZWAVvoz6yalS77XA-m)X~c(+Z<Tt{Y5j&Y^Hb1nO8XC?qixdM
zLddmC{VCnkA<bR_ot@I9wBFy6W^Mv!msBwf54)ucXh+{8{b2`ax1}f6Qv9V?IyeKK
zJJQ`g;OUb#Q<UPa^e>8`^-I_O|BELrI1H9S=~k+08InFhfw5t!-LuekPx>c4N%y5E
zet^J;bSEwJqf)oWp=?ZA_YJUd>H2Nx#DsJ+9nKy|eW*I*p>%MT^6!&U?mcLml3ug}
z>$G$^Jy0{!KWP@2mA?N9ls=Ls^C4(28+Z~*9b}JDs=-m#OJCb_lCe_Icu02M0hqIF
z;$z6U$U^8y>?(We06KbD_8l$zM`TO%Xmpb;t3ji?>}l*zZ1a!GI+j4*L-r!&vyaJ=
z>GqAMZ2vYiddU>u!R~R{Q<PBlmIcvOWgpp(GjP;b=Km^a{<4kqas<dWJ_ol0WtH@D
z1<CTZz(la@_iTU=nPxQ_LuH!+p*l?FLN{<v$dqrP(RNa{m?~|;Wk1IOjgZ+<Ay=gA
zt#`o_C2OJTu2Zr<H^M};toSL|jgdthfZbTxHrl_&$r|Mtym(oH6x}{8d+ZI+5@ava
zx#W!Oj{>kH%El-UcUIOg0+uA1@MUN@Cz~4z*OG0r5}JKdWNSJ>JTEI|!R`gwhx=hL
zRo1f$Sek4m2efpVl4kjfvU!vp%aBQ5hg_y?9!0COWZ{nB%$5z3i5yunox^fvqZHZA
zlfC8zEMGQG^`8Z@R4S_~lzq_za7kucN*UoInSr+Z#WE=cd`e^r3eT6y;$DYDnauld
zuvExS55YvG%<6!~D%mfT$gY+>QxAd5vH&{sT#@NAVX#K__bvQPwX#b&!0Ke&*MVJ?
zWlDfulU1xn@9SkzXW(dqY@3Z9y+&CdEy_)@&mKWdv+Pg0igaC8MaSkA+2~)8Xq8O|
z!_o~|s1|}ZWryBGx7%c*Sa{Jcv!ly?9kQr-P}V7Xtr>E+WXI<LbjcQM0Igg0KRUDY
z$nH?W{<cg@H?MkSu1&Q5-I2LdK~<mZF$suwWiL|-s$aId24FyTog(3bvb5LX+K}wq
z%`h=6+vbVR+>>=|z*yXuy-u;L5t(->d>WN){{#YKvV{}~9G97+VRu57J`2tVvKwna
zdnlWw^#7#nz%q(|PRY*D?qOQ?_)d5+BRld3SZ8J80`NSNz10Gr?B$<et(xy352L#v
zhvWk)G&;*GgJ94_zIZQytGty~fWz`_tAQPnM`u9XO}^?J{B@VVdLH1YToD8o5BYl%
zV8`TNAZTWr?<xO|&e>k_R5}A3m!|}P$6GGji_!CuJJ7bySMK;UI^!qj(sJf6-{cRL
z0Qp(EZ5}9Zpp#ROy#ESVg5}f8VLn9ukaCKla(mhZhsmRMfObOO_9DjVr2N%;poPmT
zDY<5gkoVA5HBzoV0Buq7DSA~;$v=DoAX>hQ!ap(cZ>ZQYRvz{q<m2S`sEjmT{;mk%
zwEV4=015I-$6)EKyyGosNs_<)E(FfWL*7DTvb>CRrpPzYhbYd=SIvUuf_y>&w^MEM
zZkk%s<ew!0q{}}Dfr*Rq7oy-(hP;6$zfAe?K8#G3+_V`WTfUJ-Hb?$f0@UQnYp2ne
zC(m+$?tJ<FSJ7A?kD%AEQ2q=R3ty7oI|G&?`B4L~V)@R~_?1iK3KlGs%55W5icuz?
z>j<=5{>GOOtdOhewoIjb5xwG7^0)P1sg|!;1{0U%FVZ3UirnG=H8t{^zk^mQKj?wZ
z)X6I%;r&(l{x~#VlP}o{o%M3B_0ZBF_g)WLqx{lAh&Rc{Dc094-(V}l&|H_#qbymA
zoYM}wt@1D1!E-}?ol+Gy<zg>rYm=XKg+#kty9t~f@-tar>6Gs>qw$t}Vgbx|$rmeO
zqFX)_2wJZ^BORP~<Sk|lSD(C*#`mt=iDG^Ia>+h`0eR3@KB9*!Z7EkEHzNOe6|9fS
zS7w1WCXerj^>O)=R1rHN|B4FM9?0MR8#*7#`<?~Mq?}9lX{Y3Gu|S)a@Arb18M%^v
zkXiYNAIv_If5L>gz2Zaq!hnO~@Inlsqrys~?4<bUISkApMXBu+1f3Q4=p5vtP|zJd
zSH<J?(0y3(DQ!=VC_Y{Qc{haz6>hpKKBKyqql!K@dhMa;xCZQ)LPPsxPsL-ja|%>c
z`@?RK;y!)AFIZ7Q#V{cXGo2Sh71g`pTA1Pr<!4SP-u!^hz$X<~XkrUjIPC@&p}0x)
zfsu-SFPM)~?2!RGrAY3CM6|-2HgGYDTXd@+R<ZpYdJ(6Hod7Lfab*gPrxo!Ha3(>~
zZx3)r@!8K1NK`mcfcC87#$tGwq$vLc;GBYcfMQU|ioiWUQxxl{<m$ZQciKE$P;~DF
zma6!XD%{c(6K{hhUExWY_KS*A3I%5<-rk7LWGb|WVIoW6?gbOs3MYEuaul;)!hEjc
z$v4rnJcYjp8uJyiG)WgIzDj~Xk)m!3)c_SM{DaY2qWFP!&!vj)eNbAaIKB_^<qF|{
zpj9ZGR8Ui?2-*o+m12_}u*-@U7+|@gXt)iz8bvhStF2Wi%K_>XSLt%(RmD#afL&Ak
zNYzpGiZUt!Xi(HrXr)onxD|b|H7P3I0Z+4H747z~E0QR0-=g?A9o=qKxcv!Qn_?AB
zz3qzcGyt87UkV_9OTnTAx=V3n3@qIWBjx0K6x;3K?`?%83tD;=w<$b*N3p;PWqpcZ
zDu21Fs67MM`V~3U!2z2hEEGJ0iXy6X8B&~Rfzn~c1ikk66dS4T^S)v(J;5W27hVN6
zs%Sm|ZDWf1B7kwlb5u4np*TMW1|KMr=&bWlp{C&Nq~g792uvyV6+`E=qMjlhGm4ki
zLG`S{jk5QT6gDj-2ON~QDAez${2~&pPRcb~;FF88gX$Dql@4X-+F|7iS9ozmX{C6L
zn{vMemfV$J(03t@DQhYr;HhkW4lG{Eq;J9EqwN0zKKUxIl!3)h`Gf?Rzp|Kq!T{y9
zdT<6RU$ia5kOnC?tcHnTWhOmdA<CUpG7_qkQvM)JIZj{8JE1J1K-@{?j2ODZl`Y=D
zB9v>X!Yxv1KLO4t<-)ZPKc(c~28dQJzJeacD3_fCEmrv_Ezohw1PPSID_{5xwA0G2
zQ?v(9Q11T!EU_}^S7=LAK0{UZXO(+S!?h%(?`v@8oHF18s7Y3C)}b*)IW`0n=aun$
zfL&0UX;Dg5R?(N6(v-QBDNk3HSHsbZN-d?FGn5^A3{a->48`HIl;sq>%~sYuMQ7kV
z<ys0Z<|{v-jbnjw^$M6TR3>}^a7lT3BXk!je@+HgtUQ_tr6tP7C^%ZGETf|6GUa3e
zSjv^-w5_U8X3#dHQdy!0s8V{~1gKW#a3FqJS$`3BuPB)mx~@?kTtokLu~zwv23@OD
zzD!ZctIF6MD7~f(pv`-|@}EcuHYm591lFt!r^?6cN;j(NYEj0~_NG<YT?lYPSxnR2
zO=S<&jkPIDuEIpS^5w_D*`c&OKnJ^&iynuE-OA(k7=#|>(qmw;4Jntt4c)`atB(WR
zQ{rTbhg?~+0X$>Mqcqu%D--GC#}mqDufx&<Wj(Ee50$(ZfK4l-sjhxT*}fQHR#{D5
zb5KqHhi*HnuD%2<PO50i93N7>JO<#bI=BnUTvVKE;PkSoeBOqd<EkmjrFg5JTLbex
zs<r9x+gJ5?J}mjEJSm;+uhLS9N`UGxMHd29&(X*RsWP4hXRyj2@$~s2DrY*`hN{Zw
zxErSGZbRb<RTT|oxavK6E+SN}W%vyuRdE!*h*H_^Q!?_D>ilh>(W*F_Z{k$1`9UyV
zHJbz4Y1PF4pX60<^up0Is^t_lN>m+u0hZ3H45jE(lB&N7;^$NqsSrq3g-aoxqUsI@
z?Yye^d0-b*miNJusxneEF-_(9A86^S@@G5Y)I}9%Gwf!mR{3>2_JVEa90(Ms4(>-=
zp=!1VoR?I4enYQ|R2L{NRjgXI0a{8_`4iwQRaH{xxJ-56I6Ny?F(}<%q2kk4wo*0s
z4~$)vDr!3fs#TA>faS6(<YTD5qB^)8;x(!-Ou%YYta{MuREuptLcU(bIR$V-l}0=2
zo2ry2(cL!HcT_yku6mlb?j5RmRIJ{q(scvtQg!SEty{IT1)M#q$H~Lnsz@eu_o|Mq
z1GuBIql;^ODg|vX?yAzAAuyn7p|Jm;is=S_hg7x4C@njzGE->ep6ba|n7^;uM7iw|
zRelwej;iu)aBWQWxhJr3RTABDo=_G2f{}TsdXBERPO3&np=C<-(chp=t6rjlycyLO
zRKYi^+WRk5KT>7=17NQ<)27Tp?MJ}~NA=qV`mTwSx_UnZ52?9Sqv))5?}MO=dgEOv
zbyX+)0rwB9d+D({qHYWUr<*#1QWD41nRK1nOFfr%1jp5WPoan2>NWd7^HHbL>CIOi
zNYQ0K^~Y3F9jIPG>6sw)O$wp}tLJg(SP-IK_b!N`>Vw%33{!iG08Xey6wExS{-hbd
zcDQ=!8mNg>NBxKXMybCa1j{LPcqp_*tJ^+>c#PVx3g%<gS7+dMoH~nk((!6WEVP_f
z`|O971ogQ$AaF*#XD+lPs=qe@*pk$HXlgj8zHtm_vig`E)TF3~T%q*5`dKxwRQ31m
zP@1M*L807qbyF6!T~v2vfF(mcmtu68>iiyHS?Zt2V2(PLGDo@U)i*F|dFr>Ruq|Kx
zHGMp%K)s0p*9z5F96-BdQ~xS}i8A%7wHW7e^=`UqQ=wi+Y0gS@FIBl$sUJNK+GX_s
zt@BsZ94Z&BQJ<w-%2(BA=#z5S)ZgaAM7?@$KWGi=ALvZgsQ#xEa?R?;FT?J2^)9-B
z+@hYtfR>wT<4Vxl)V3-MI@7K;&w)gTx{QKzo$AH{NZeANeGL*_>RW$;wMTs-7@W7&
zTPY{rt8Q%o?T&hW8@%XKKb?({xvPF951?Ny9!Dnz)X&mAv_bVBlz6(Q7BxZVef95j
zA{|l3DWPRl-Dled-D7IcZV<=SiFB%YpiZZB)<bmyRVhrWzh4EGDfMnC8mHC2?||+{
z>MbSUwAb8N0pOrHv=ohw8dnj#chbB@lk_3YE<c!e(LDJgSX?y|p#X<9-wuKEh-M9i
zV%#)=arC_q56#27U_GX}kO~u?nz=H#=%rbe4W8o~M>_y-jmsU#`)DR9T<WV~H-IHT
z^TSy*25NRtXe3Cpi;g(Knx|=L4AEpQMPryI$O{4|H1lX1cT%$>7$8EEPtl%8&Ae;0
zC63apbjRSI(qw%B^U<0^O;8h~`Ti{oTbyPGT{Mc<+@BAFr!|+ipfN$S+7B#eGzRQx
z=O=1j>V?51O+GDc=QQPRXiV0KXcw8Hsi*3s^O}3~b(b{F<~<nobWNZIS}tnRS5aAD
zh9;YMGBrQF2l*_`1+ts1`7#_X=4h@{vL;v4K;=Psn!o!%%hxzOgfj)2H57U-)U2j$
z#wE>BDibf#s8eC7SQEMhv=U9F6+dCA=6edBmTUelh1(UHa{56lHTT|!qqZtdC7p|_
zHSA)jxvcSx0`ZEbkn(Od8Z#Aq)oM;pK~0_Jl_Z$Is#!r%*K3-ER0&(J*+F~o28|D8
zr5ZJx{sz{hnUTVoW=%F7ysm5d)<H{)#vSEn^IJ84eGG6zv!9A(+iaR0v*2mhEGa_o
zJ2d^TfY_;dR0iyprim7(F3neU=zX{5{->bzXwq-Pi`$yv&5-ZaEPM#vcQnsYsZ^il
z9OWDCYT`~ppkL$Dhn@{+%Bs;gsQLDJfFVu6TL8nF=a7?|e_vzk?1tco<}F%eMl}l!
zAWmqOQv&LNW}p<{p=KfxU{YhIMP^E)rRjNEQ}ZR<p3(SH*m730kqU_(Y3|TmVy{*1
z1kFMFKMTw|YC|I-;G}(rUc5tEdq;3OYpn~>=%W3_MimgQ+Q%rRcv!p41H>cR!k6Kj
zoA%Zi2Ekq1Muk&HwOR`>53PSL1dnOWz0mEc{g#eOUfPfkAaGo(qWHPDb_1;yKHAd;
zxaO;UJsxiRX}|3S=C3`|2xS4<1p4g*wHe8@B@WW=jR6|0{jwJFA==&LkO<YjrokYF
zX{R28?i1R+f5CE6yJ!#s;o9s`fGBOB5Z<5CzOxRxqqSZy!TT7k3&nt9wJ)rOmN@Ny
zG&99(!{`w>t#w-n^9fo*2e3r#NHA@Q&uY6)qcutEKqraw+AY4YdqMl|9ypV#b)v(1
zns#IqUZiUs-i5)7T3Z!p8QK;)<!5TA?4d17yEz>Ov$YC(JaV*|Sls64YK`=ff;_GM
z576?pgQ1`mXcK5=Db#9kNU_boq#gPnSc|kbJ^(1zZZCz25^W!Col3Qhk04Q|T|<vh
zxwggwph8<P0M1HnEj@u%+BK<Qsn!}UL*TOZcoJN@qHUpa-Wu)WMvPjmwv9f7RHyy$
zGhkP>Z;ZjGYuab(;kK<_dyw{~4O+D$K%@2-I{G(hH&AMzS&MIR;04kO!+^DDH|>L9
zt5#-4w{K`q((`;%iz|6}kF*s*@S<JIWq{V9?WP-vomxjKIKHI~n8pLqrH!UbQ{CF;
zC&1F94PFSj+cxdxkI~wzeJTU!9qk+5@U%~Rn_@_JwV%BW)_(00+KLQlpZ7<f2DPoU
zNDOH&tboB`ZO{;~ds<yJu>0CH+QN)zg|vQ+YFoSE@0j-fQh;%7Vh=hvp-rJf<fJx-
zuJ%l6ZO<Hli__Y(ba0!|W(B~+thVzND1D@jcm+!Bb-W{JbkJ>}e5|9c{1tfUq?^ry
z(nGp>ny#F6d+$NqMVGh>ZoBGUbp+>Oo!=B1kLY&NbK$0Qod)Kvd!ZfzM|C_YRD0-d
z+j;<x=?;Dm2~XWJs^#|5{dEN{9@j1U2X?)6?lgD%=wg3`L0{cS6nf~V8=#U4f8BOk
zT>^9;<-$aujz>jRLAs4p+7+x5P=GW{C#3?JaGgCHjS)H?ZEYiU%g#b|lrFN5-oI12
zuReoQ(YiW{t;Fa$Y4VHJiK)&ePPhFIOvLNjDV=;;cbaaXB<R{H#(qZElnn7iU2!64
zXLSn}z|kb#wxbX~r;DbKlO*dHQ{YU|ahPB^uM-x+!wb3`%Ic=-(iKz|k*525AzIUQ
zd+6!DsQZHf!3>>KGwf#Sw(NkzS-L0aOqs3w@;ZFV(d9<MM6ND>1?2K{LzQUE*FB_o
zbb;=LrD!bF`S?Q1C7n|lXhk|N9vX{vT#7uG=)PPIw@Y=RRg{)3(+Ssur(CyVE#xb7
z8F%4DrS40r$F0&WRiIDRy3d0kaas2*9eJ+k3IqT(x<oTvtJNh@WoVu5+;0%Ls(V2L
zE!TAU%b}%S*H14;gU*k(`;EH4c#vz-?VJZ%v#uo!;<oF${!Q?-MfdLx5ZiSrb6~Jj
z=Sv}_TRQJUpmpi0=soJzRnz&aM|b`)n7FN5LucS#U9S{fyQBMI60|;Ds|cLKy6?`y
z-}}0Y^yH7|@`fQWs!OBv*@Vu=9Tpzw!YSta(59=V4aTJIRWd)N`@kMN)4DGPfz9aZ
z{Xm=532BG@NasM4w!MBA4T*!kNDj<VuNek#(o5cjz#;wYE%eD*e<>ASxac?40l4aO
zsTk$39-mgi>!7#MVZ%+&S&yE%>ut|aa`~wK6Dr>E(7*8ubRX0IPNglL`W;ka;-z1~
zK;v=!&o=?Q^*6tUypKMB62QKCO${3T^zYGm$X_3{0R0Wndx#(&sQ3O5CW7>zcL4<J
z=Tpx@^vgbjPoesqiLe)@Z?(-r;)K4W0hUhcJ%=F}uFo|?X@vgIzW^fjYkojul>XBH
zA3F3B6|iW1c|3+RM*n9e#AEgDkE1b8ze@<+@%q{i(b3cTU0(wv=zn<;j-Jtre*s9;
zzxF1aIji4JuXd6?dW#KCozq)<A)l=G`v9#e`X#ghJg;w|`l}0iZX#%@`Y+xCElvOa
zMbOgqi-#e1Q6Ff87a97NOkkP%(yuWHS^C)Bu#~G$5d!4tzxfTcd_9W|Ed~1HRG?j`
zU+s$CU(yd8rTu4-{#QCg7wczsgQrA4-wC}a)vrkaPnkZNs!7WAFFgQDg?=$z52@5M
z^ypfZzMSgttMwu2FmYL5Ptmn2`lnVvyhi^lO`)~=0}ElWPS5=nu3gn13<h>h-}Nd4
z>h=97-@>&_eRU4hH0uAW2WZl-r87^n{;n%{uIuk%nV8?A4=aNCR((__SZ?SU-+^{h
z|CkA5(WY-K1WUVqS_zg8eN7W+o%%IY%ymm2m<EGg`dUB8-PZ5h3fFq|MX!P7j{cd&
zpxOHLHz-bgS3g4MntuKBl#v|J?{9<BLH%DQ@C@mb3NaSL`Uh3O?&;%y2X<dSL{|((
z^zKv(GpfI2g7}zTb^x?-{WukPPUyp9q2+=8&U|n_)Q^#)lllw_Jx}Qs8^Aej(|>ao
zN@w)e4tO!E-$bXJNBZrwC$=}(Q6-Rr;hmFcbTqgv2aA*8B7KhJkim5kv^g8jV~UyY
zVo3ZCUbq@QcSPf1!>$y7BZfKOz>=Hc=>Q108$2jnd(?2(0a`o^om9ba%wSlx2B@bY
zyB`L<3@LO)?zmy(U&wnKmQmcs$MDYxbo&}M-Nz5(XV}VzpuZt^9GroMejkVj87kfb
zOR%9#5)iTUvFB~;X;D65c=~g&o-`!HfhXKxTnBF=4C`nRBMrrr28c40o<ZX&gQWnY
z7j1B*v{H=WU8;GAHGCQmEpdiTGO)xOGEYFu8N-&%u#{-H>5p!oHGC5S50ebZOTco@
zAf18EWJ8^e?g6A2?(PP9-tdthcrF;;A^CK}vf~iEXqXDdm}D62tHGIVc=mNz$}w1S
z;aaXCVj*aGhL`El%{P4i9k2p}8x32b;UkK^UNW4{0IkT-M={1?!zMOZN(?`I15j!>
z?oM~j$_za;lb0KOSAw;|zz>1lN<$-6u~Zp~>S4Fq@GEWUFB>Ax1G{3lNA)f>hWF+}
zuGY}=1VEjk%?N?3hCeAXd(ALD1gzc=Os`>s!I=_YjRq47oK1$eeuA=QgXeC#Yj)l6
zM+A6U3@g?Ev>M*u3*T-SzM;C4n}!>7FljT)qZ*HPgUd$9cNpdg0Xhw@Iz#C#LkQ&{
zy9}(|0NsYSe}+JhVK*g?ZyVOmpt0A`#KTW<$52H5>@ysB3ypUT=2}`*`wi-EfDRZ|
z$HJ*WL--?LLk24yUxy9n1OWF8Qkqll8#a7|ZjTspR)BNVu+ITwF=m*cHDlah{1hw`
z2A?ls_kp2G2f2ra3JMEO8pf$YbIS0k3AAZL1wEEC20uzA+GY*EQK0pa;U_AVus7am
zhc+kU@p1?rGQNBYz}dK&a@#J(AGP3gHBK>s9X6WU;l&Z72PJ0QjD|D}x4Us2&1FZ8
z-_lho595Z_@adSb^gb|8<6^2$^)gNmK+AFCxHCAtZN`cDAo>_zqU?#UQTH;`_!-xZ
zfydwYGi~w$jN54X2{dLO0B4YKzztZi@i&_MLX5xti^fo6$vnt~8P#;aK4H90#bhUq
zMMAKI8|^8P8e!bK11yoonTPNx%J}+^Fn`Kudpr@uXrsIbN@I*!=io)GQB0ecIHTbq
zB;t)8|A2PJIC~rtiN@KlFtTTjsTAHzGPb#55YHJy*Td0d<J-@}e2Vd7e_-d0Q-#1T
z7~>YfV4CsGf6$n2T=_d(yJ#%j0=W!hs%<L_W*R?hhKX$Bf3uLtG44!*M6S{463pir
zcUnQqH`*scu)t_fVW%SFB-IWT8(q_&w8Z!YWhP6FBW}RTj2o!7tK69WCP0PJnc_Z`
zMmHAxtuk)?8a=Bve&`4B%f_-dY%qAmxP|7V8lykG2erm0r(mMasJI3BtH$rDA#u(4
zB&GZ7jje0J*<k$Ni*T*cm@9yIlkqVsy=^x3J%oqXjhy$v(qbI{2qs#MThpNIhVi->
zw427}chJ~oG)+KfyK!t6y?-4>9~O9S8R0M9BV)|J0Jn{yVbI-cjHj#ocZ{8Rknb}Z
z=%jkrc#7hX{YDSUHx3x*zXEK~_(dz^hK#Z~5EwS*Pzdgx@o8_kec$+13zUr+h3Q}!
zH+s-5gbCvlTWC>zV60yb`G>|&X%Hrj8Nc9{nKHT<Fc#CsCQ9(n7<X@k;H+`SFL3mc
zag^Rody}LMz|oZU3=BG%{wRjPA=BmwusEBt_d>wM<n<RUxtgMn!h)AcCImQc>TU&#
zx9P{9z+&?;1th?ruc<N<=KV|`FM-lPlbTYoL8cG7ARla+{TaGLOztC~g_^u{;0!Zu
zngMpgG)+nTlcpHD$rWzu>%ss<n1*Qek2GDl1uV)GdkI=jnbN|bGurg)Z8XN1)=;qT
zoXs>#3HxNzuTwzJn;dVVGZ#!>{|0TTrge0BPBR&n!BV>EnI`})n*82|?hI4jA}Gx?
z{c#(;$TIDsz*x3v^PgbJF=bJmOs;7y6D)bAUJCE!o7|Uxv%pkA!Pr8R7CV~xmrS<j
z>6}qyIz?y1Vv{%RK1xixe}<Y;(*Q-p%S=)8ft8!$;z6r0ed-MPO4HX-pjDX?55jJ>
zDQ78kUp8%}gzgm+o6hhxravf$QfulWN9#;)P_+B1$pw?{{A;GlBGBqhk8E$jw+2%q
zB~uzrYZrsqWa85CrrC6J2H15|;xJfSOeu6wzG*r``?)q#TP+&fO{aH&rNgu{0Atu`
z8h3+hw@eX>0J=<{XP~j$bp0T_?=hACjmF!iMhA>cugRW{)OSqLsW!CsnHre@cTF{2
zXze$xq%z6@)00%WIA}_Ug~1`y!ZBDHHZ8pj?4IeX7tqoBrlJ?|bdH$z+M{vQ^vZRJ
zkC~=oAUAG$k<RxMrs`iodtiF@4S4a;^wTpCm^5Wop}SM2*eB?}yH1-*>C+N3rldI_
z&YGs^)bPj@p@X2kc`p^+Ihg<WA6OjCoIk<hWPU_Rr$gq~DBA68o?`)vi+Pk5MOSk#
z<;dL3!`0}7yZLN8yf|v!@)_hj%-6#qcg*~&3phQ^@BEMMnt7R7;V^jIJV?=0Z}XdU
zWb-jEpa`$8dG7mY^fMPz^_su=Jxap`m<9A1ut4+sU%{s!^KWK!CfMA30gWN%XQ?JE
z)Er8`eV93jN>ommSqR_GKWXMiqcPm<`Tsd;bK3!UVT&|RybXt=%ywrWc*?w?7ZTCt
zga-5}#$1{VyRqg)b{OtBvwb93;>|h=3Y|8az5z>uxq~8VXUy{{*q&(qHxis@%|~8=
zqe<rfBB1)5c~>FKC!3$7WL1ipK~+NM&6Tu4xL`AHP6bRghf)wM&3uWD1nK5ED*-N=
zH*}ye!@P+aGtGtp$Y+_SihyOCf1@p1j#>3OSaQwjbgeqi+(hNI`Q{K4oGCEhAcKYG
zQo5RO$?QcN-XgO<t&PRzZ|GuFiP@HA2Uu#}v>1IVGq>r1m75d8!CGM!#6Vl6`D?nF
zUu724-K%P|g|^Q%=I1H)cGdjW0hqXEe)KH*TW>C>eL{nI-4+;ZH2XzBXOnqs6b75k
zsoy}$b+b=5uoiRoURY=~H{0l-e8U`c7lU}y>^T6QHnV{ylXmkJsx#;?r%-)Sr+L;D
zoVU!IC{)^IUPys~Zu9ZapsmMTNP(N%=7Y=OMXz~;vNw0k=FcI}XU?F2>0NU@ZN&P`
zPy4{b0doQEYX;4&=@d&IGP_Z3W7vFmD=ghJ|FsA__sywvA!Wo|OViG%xwZ!KW9F1X
zVB_W~ids*Y!*4+M1M|QXv^_M-UIJ~>ym%JMrp(XgfMwe3{0uD2m|GG-n>D}D1c689
zK}xOITil1}Bj^s6`d;|$XgR4zpPVf#DOBoW@mvnzYT;~$#9_<&8qkhd;=%yjEc;n#
z^svOxuJD*8lwysZmV$oJye$s&$op72>0Yw0C3ZVT)X%ar7RvlB=O#f5u-rKZTCios
zZrXo_SYCbvG}IE?3~gbS@sEL>u)Iyh2PZ8hFG6>?WhtF6A}qUTI~i$lqzOIBl1m?E
zJ7u}M5nYS6ocI7NF_z1;$&0l(<O7Sdd`Ln5c#By9&eN6!3UoWcl3NFzXDs_)#W>j#
zEy=x*KWn)|b9a*E<4e$e&hmU4uw=`{7oaW0^5TAg^OkL=A$Y+uLZ_otOVjIk%F--J
z>9CY;IZdnRMawE0gbYiB1uU7C0@}G{St2M(o^45^ePE8oix$jWOUYt1=GiPibwMKE
z^64Fb0?U;EfI`b63BV;w&I;HqvSiSdR&4R|MPrFYR1VilEwgvfSY|Q4j;@tkhG{*)
z{{fc*-~;LZf9SVtqhM0CMMyPEmo4AY>u|;Ld=;=7OG!IGt;Kee^1OAHV^JVpwbbr~
ziEEaL%Mh%$q@<y14VI8lG&Wk!-vLXLrK16~X3Mu9VJxp(me3Q}VhO5&Gp&|=^xogF
zto#pdw_C<&SJ+_*o(m5<EuYheRBu`GC=}gg8KARWw<X<1_oR9(u1{bvZd>-yPtj|U
zlI}Ye<z=Ypv+SZ$<GYq$_d%lHvi?<Q8?e++ee0lQ=_zO%vK*v{_OQjU1j_DN{#3x3
z`<7p_07fiNQ=QJJrT9FsF-rm6{~oujegbk6mYg?i5PV?a(I)(%<+Eb|la>Qi1v+K1
z4nT0)GTj2!8OvXISm)1L-f;!(k)@pWKK54puP(el*2V?!*U`E!6)aBH*U!MUL)OP=
zS#Y)%_rk7=^}A1?%+<QJ4ayE%hv-2%V!iw>?LXbD^HM-`w|@Q_h)1ojQJl=fy67WV
zI%a(%3MM?Q3QB}~S+CT>?s02L7%*?^$TC>+vC1h};cHz_F)%-C=p-8bt@8@O8DL#f
zgE0)WuKEhj1X=Uwv=D4fp<4M6YwII=|3a<(e}E^<YFG(_C#>POfSt6?Wy6_p>%ufN
zMp%<hL0hEtav;=1S%WG67h|obct)%>gpTrY)`RqGCs+^1fOf{(`xro?l}U5pIco#0
z?8#OG#SBuc!7I>s-s(&TP1^;lkfyX$>t_0T%tdQsKZYj5I-lZtnbt#3gD1<nkj?<v
z*7=m7$+0HV1~AteKpDS0tBlhB`PREMzZO`(mc#8r>)%w(e95|W6k3X`b@l+oRwp{=
zmRNglfL3b#o&vpPHtPebvnaQg_d<7t_0t^4S6W-B8m-FOMme);>rP5zT()i=gWp%I
z)e_jPv0fiU?`y5y6ppO3US0q%u3A6X14pk}L+KM#_0}yELu;@O`9q-5nobwho2)V8
zXl%ANZi2vdtL@ZP5L>MOlBccKm|O_nunyAZ<EB--7og1=LeEvZHQ^L!x2#!_aKFpC
zl-9;>tIJ9#?Xlib1KhSQ4T9Uf);H*MbjRBHF&g`<VdT?Yt0ScW`>p;oYYkX89|9P(
zzGs_8w}-4xYalUfeYpa@-LwAX3%mEN9(2)m#3~Sjb<{dQ(bzHTGejG=?xBF~g!QjK
zp!9)NKpD=5);K?KPFjm%L7TFMe-G8u*7W<(GGqNz57o2QbSlSkushfRPDi^N4YdDs
zvip>Z=v?f?bVbkA?k5hE9=4N)L*j_tcOOExo81b^-@DtrOtGw^c5>R-c-Y;fPnI0B
z`(hD*r(MK-G<w;cruFN%-8)os=xw*}XZ*}Qc8+v;!q+Zz6%6^=?X3f+zukL|l+*~Y
z`{g$f1MSQ-g$LP%e+&?8cccdf!|V>|Vg7{O=k8E?(ry{mDTUja=!_O&cZPzSk#?7!
zK}VzP9@#<Ql-;6jV2QTNO9V@dUG`h(V65F6^>8N6&X@@;@pk#^(0JM|ay6a*66~J!
zftoXR-n0!(wDVmLp0jq1lom*`!xaI%Kz2WK;bF4f0gCOU*cDRA%6Yq+6eYM|$8rEm
zs+}|ra%pz>r~;NFJHK(TT(olzM`MQF?^J7?X{Vr{Fw1VvcaY1ryZ1QE+WwED>kO;v
zXu_JrL=&TlNlf$8#FDOQ#*$)5F`A}{;r8Bpznba=q!+0I3J8J<V!=WYr6?dpn)Hr<
zAP5Q~A|N8)JNY%w?#{e3yZ4+uyEC(Uvz)5Kz?1Ftej^OdacZWW!9}O7D)3x#>feLP
zTqif0H}agk<bcU{+Hn^hz3g=K6gUf<zWg4V3Y~JZQ7Up07Xhr;X>%*EuQ>hjGuq0W
zgyhA&>hw(xFe{z7YhhuP(<)j8S38`RN+DR|6!#re)H(^xsI7CVaD_y@)45kr+2FK<
zzKxAe!QY~-#mTK60<BJ)D9@<PX$i$ruQ{EkJ$SoQ=Oom3IK6oaoSjbnl$3ehX%mIa
zx|~W!@xydGUG~K=_d12s=jf)>_b+)tu+J&^XGq+3TH=Go0jD>DpnlM)o~D+&PXCfa
ze%ML#8pu7T$_?Ngbvk+mpkq#Ba{x2$Bn_{88yRvTT8O(a>`chHGJL(EemCQ-c6zuO
zb7}eN$#8SQka#hc`k>^?c$YT6ehjZpaQZWPo`!}%h6kN%3}VcF2^xYKKaQepFXM?<
zz!}DfCJ#?I<0?(B`x$OJv_&%f`vDfk_{!l98pGIp0kyG=lk~70WH^2R>mf$oR+J7i
z5~hHCgb_FkW*=p&tAjB~j8q}WF~&EPY<rS1O6Opb8KHC~#VN+Sw5L4F@UuZKh4C6q
z-Kh-0G6<Ywyg=u<G8lCqf}CeOG3dakWijmkZN3>!l=7IvI2i+Dav7;9z|LcoFN1~o
zj5D;xD`Y%Q9`qtcA)R_EW_VDPtCVqS8Bl5&<@7bHV?@!kUeEBNJxc@QP1?OSGA7AQ
z+`?e}2EDC}d2?V>8>7yTKBm_gb0`?n&d_}f^&JdOBS<I1mE17b8T)9}(8WkggM2qb
z@E6qIfT1Y$Fnm@+;Z4T-S5WF>R2ab7&+uLcy|)<A<Y2nZ5c;CqgN%RYq7!!*b0}wH
zh*5PB(03Utu+enP7-qOomf}6eIBknY8GT}qF~%Q503ByUyF&gUV`d7lCmDYWq3{vI
zz6iZ=W=>p%oD1{fJFv->Stf_TZf5&hw7D@8HqsNs?89U*!;_hO2@1WK+0;RA=0O7U
zVZK71Fo!SGJPk!Z=I;?O*q`}e3FP-MH%nn~0Q0FpkU(bh$FL%Znfn=7f|(JY12lxW
zm<_p5CK7G%urW8a!?ZAFOEUC^Gh@Uc5zHMF;M~WYJ|AuSnQrdjjAkCAXXXHNeGSyd
zIGCdp@Q7pnau+J%nIm%{c!*iP6qY71)!#x>BC|al@<*91TA&?g<_)3k1oOsQ=>17%
z-b%onX0~mD*=Lxeu|PS?+(L1*H0JeY$fYxDHUi}wGmxg63(T}sv}H0E$3h^B>8L9M
z&qZc0<uF}h%C^FoTxQTNbnP;8FdEne%=t8*7cw`Mg0qPE#8p^P%)BxOl~<UP^!k=C
zKQsWXlvy(X>&uu2qM@mr`O*hqsbJ3g8emtMJAa22Rm@2R+Nzna2f>OO<~Bzd&}y0g
zn*~zGoFczzJ#&*1f(^{q-N4$!{E@6^W+qREd<(OT0V`UW_bJ}d#!Mp*-Zf?cZO+=6
zYbiq6!JNGw#&j~jISUonnRPT#bTM;dP}$A=!XKoUSw}0}o6N6&r}Wc4X6SZw`!;if
z0eT0R)9JH6$Q&3!<sD{~0N6v!#<xK3GIf-ZG|XH`XE^RLqsL&y2=mF!sJzd#&xgP$
z^OIE|W6bAvf{Zg4Quf>frmq^M31$<8QXevBJp!3zZahpM(?`rMikD6?Kc*}mXV!E9
zdf~$AY6Wp+MbiYen{}7sVQ#Gc7U*?n^-y++2djui&6D-kT%dWeic7%a%_`!9_^>`&
z4^Cg!g<zogv6{#Vf7Tfa(eGg$rq5UaD=}~e-oHTBE0kdn#M(F)B$)MM8$d%?T}|K#
zWv$PG#9r3+<sf0KjR}AWXL&ydmI#*NAz1dY-ky&^*w6Aj4!x1AVe;-pv0^E~Cz>VO
zkC8dR8fJmSu%hX`jb+XJ?^Y4kyFZ{4jyTpT8$jb(ezcc8#4??R!G~FvqbMC=J+6g{
z1lHvxP?5+gCAa)h*1n(c!zQsxSx|V4HJf%Y$5~~~s64@9e+2Q9tQa~onas+1574Jr
zrSxS#&078uP|mR0?m*xyYdP()QXH%RAHbxuD(UNTjx}Ki$zZ)h`S|Bqb7|7O!1^;2
z=4Y~aWM~$v<4Is=vmVlL<*=gZ#k<Jbng`BHtbb`f&t<u%12d1+zX_#$)~zSNa+&3p
z4wM2`#~p|lvXrS%U&L}$k{76$WuHRh6_&>W2$rx8(ubgwW!w(dGS<ImK+0L`uA;Jn
zCF4QwRn{{cfL5|L?}k7X%MU;0jA|D9M|7=*^)qd}YFRGTsH|h{q7806Yv=*m8dw?Y
zKpI(oG)_&dR~>Hyt(m1G?|uvGQ#&-ZvSv}Zrk!=!2%Zksme0V_$=XK8-mkMtDC4Dz
zwVo1AyIH%=qw)r;U>u-5Ed5e&_Od*mM%zu+zq`TN$6`jIvY(Yn5BDwBSqhckX6>U>
z3<IotnG{SMWc^MNmOCsleHDjTUS43m%WC-zb`P_@qJxz8SR2ov_am%VgJIfz*23Ko
z7-c1Oz``-sj6RgcSr0x%=>f}|5?m)(0a|E!$PzIjH_4KG0nA6NbBjQxSkq2|#hLx#
zCdv?ZVJ8H^d{=fZ?TmM`zt{>1H+CeY>AJHk5OJ8{!RA~?FFe_ibP&diy^uV#-fRv{
zVm|DpbZd++JE92Ue(aWW5b$S5he6XG_U>Mw1h7NbqcV`~^dq_(#CD-@bTIq(+q9Vs
zVZXcqeF|m!o&?WcHgg3)!`Lr;1^ICHQQF`}u<a)>GW*z(pJOccv)O!D7|Grp36>~!
zt2b0cvp=Ay=>fJUIdfvzX37+eWpgQg`yjiSF4u}<mu^ETo}KzVSPrpA9tUw8X8+(1
z6-U_b-2qwx`>$sJlf-_o87hvkXRku#aW;=G-A`uEorP|nVz2xV_MT=xHU@HzU3~~F
z7ub#D@XTa;Q)DHJ{p&@LZ1!yOMCY(Q7lK@5cfAYDOYDZlAi3=O%RurR>~AUndYRpV
zyVzzFu<NhD#6ouJ3CI_*ZFCn!G5fD>jMo+R$d4$MvU5hkS;mf}!v*DR|01ZbV8_t;
zkgM#iiLkzs9YE2ZD)uiF%&2DH-Hndcus!I0-&%IUx6n|>_H~0mJ=<ZR$ae$#OS(&@
zk)1scXiaRPKN_3aNxwlw3%jcj=C`uHp)Bq;_9aS&yT<OP$FiO65)aT0cJgUh*vWqU
zHpq2$7e&mw*dLvQrf#-7EuC(#FYiXFhdq7}a=q+GN{YV8p6S?%;w^SN9s9V=e*Oqp
z2iVc|AcO1~M_}3=_O4W*4Y7wFp>&s>O7XB^_F{4m++$z*3_t7$d)`%4-e*_-4wg~2
z^(oji#x7ie(l|Sjvh*LYZ+--U3AW-nR6b-UQcCzFJJz4(t4Hi%50EK#9LYO#*qfnn
zH|Nd&R#Kc3N~mz>WNn0m2j|Ua(dNlnL%}L9PBb~Ry*ayQpld#yZpwo5<&3`#O@5pK
z3ZnRP{-y}j9*$rw<N`P)l&=%W@f(6b5XWgg1v7#<0b>vh;S3alHI$Q1X|H=ZZ_wU9
zj5Dwvdc!#vB@m3@99;#4`#2xczGOe=(gA=*a^gNlTNKBIHX_lS4sz1Ra$caEwu2lg
zeL&(kAvXYan6rB)$PrH0SJ05a`3iX?ju}aumlMHrj3X05@Hl6RZtqOytf)ohDbAOf
zD4ph1(043_<LigVBb5_H>*X{~{e37r$LW~~O&OdGb0B`6GyV%yT;S+vn~=$QaxGA@
zIo)rdEr)ZSPB35O7${LSm-BHO#24jpUVay#`5YttzLz=MDGjE8v-D#qEaL18?^`(?
zcV;7(Z$>$10j)7BIFJ7f`Kz2Jiu+Y@8tHgUHK&;3jWwJl&5*0*T#iMljw2@rZ#`%H
zYg9IIPI4j8%;}-YwuSR~6<At1Y1Poz#^KXu<r?Ql+IqBe3NrA6ba0YhL|-~Ne>!OH
z?&F-D35kBrp(2o59ODRJZgWa0_%gt;)290lr}RmfHpD4kfYM!#R|*E<9;Z13;-j2}
zwALEq#L!oGoRdth<OiH}bcxvn=am$+J>+C2!q7=h;S@@bIEN?;bc%E3bBcI7b3dYW
zz6<x07a`%w&DxHV2lpm@jy$=+>rm;%ZKempn=2--lMi?99(o?RYzk2NakmXZuRr%Y
z@`vx?Zusv;P_EZPbRv}d`m5;ZUhdzI02ao52TS@H;amqDH;mxUDVl|cbRTyy?IHGa
zU!-tpB)6Qlh_T#lv|2gHUHu729JeqNdgHk)T6!Jg4$!vfFn0mHBS*NmnxP_ryHW;{
z$bHy>uASgUQPkul_d|*jC3EX$L*XfI<65Xc&F!JZ=o#)woRq`A+i;@_A(+B_vlF1H
zT;6mjJjV^10qhJeZ!XAruHY=%E^u8x0Zb-$7Nyi>aRauXGMjtW9V|IqW;_&L<bHV#
zV3)WRlmd~<U9<pgd0eLvR2Fg9(bBk>yOwV8y25o!f@zKt?o;HfE9K6nO;#EA51NF^
zxxEkY`&Mv2nF-LV+_X}l)p9c^U!aaVjr>LR+!?gwYv7)J9Q|$NzJ3#+P29QHU|}=&
zlX8f+a2L^Q-^z`kI9MllEA7gzbN%TgWEb~GI_}Z!;Lg7SdV?$Z38aVnumM)|a^K;D
z+~h`4aJ-M(KvDcb?!Q!dhx-Hql{1F8V!C(XE_VyL-iEnn@5AhS+(Jsf9^vvS1OGnv
zAtjEDa((=u@Bw$`ER-g=uE$~1LvAX?b0@hD-%o({h&#L#JX7560-!nb_LDo(h1XAO
zCRbi9-J7zT=gbAR8}HA*LEL#^ly2w4I~<RaFVEHrIX|8YZ6^JB1>_an!(-ou!T_E>
zO>=>~>;Tvs#7k<ySOoI|S3_SoZ`5%D-HzaiXr9`~dny5F`+5J1ghV87f?QcqyyxY>
zj^<6#;{O0|-BzfG;Vu6Py*R{M(E@?Pyx-~3JHlJg3AqHG8~NN4c@^ytKgwGq2T9_c
ztq006-tzyh?c;^hIfB!?l`03!IKz9EoL*;nNBU8l!h5+1*r~jG<It4Gb0a53I*-8v
z%sJlc-oVb_d617jlh<(^;#oZRew4C#O;)t!@W#6#aFO@U0f=AXz3K(9TwWxdxXa@W
zyaAHWTa}IOUgjmeL;tQ(!25?z!W8n7$-i968`J@&j2Bf0m~x(=7z0$n`&|f4S9vQ-
zpsA8~p8~p7ybXM)sOGhv184*9Jx_o(@|rxr(!^VD1WGe6lTMVh@ZQ@DuvT8*U9`3F
zZY_u0HJ%%y@VMQdcOU}T-MrIw)ZXCzO~<)=cwz5=^zvRi4bYps5jy(T$6J;M`F`H5
zEg*Mz?aBBlhj>}^tl#BrrIQ`QyhoHLdynVOgx(RJyDO}?&znojg;8F72~ZyJ(!YVd
z6TIT(AdZK;ccxG~$vZ$kyGOi$uQ3Qyyj8SQ^yIs_LxmTA@F?WH`Qa1|@ZlTjShg=e
zrvdVQ`~W3b{P};Gpmz`dQ6o45_|6A`8OXQLB?m$LxZ3~=<}ag^#}NL~voI}`pGI%-
zUI%|qBw)h%tO$Tc@OyUvW*<M3JiGh(D%$%;^3TyDAI%@6MB)Sdos_T^!{1KV;vD4P
zItQ3I{-;ua#`Cw6XZ8@km^L|w`PXKGB=S$b4Ctf$4fI?j@lVnR{uuwN2AIeBj;eoA
zdxF1^7HKE><()uF=D(wd;3@u-i_nWR{B~L#p5^~)2T9?dTMEHc{&);X8voVzK+^fm
zx6p|UemrF^pXZlpAbx?b{1ecb{FMqoXYtF{V-T|W-+YB(&f&*jflU|rPdO-lcZvT!
zt=V$<<9}fA^Z3!911+C_g%YqX^MAVmQow(bwt<CwcRDLq#Q%`IsKxw+XCQusFCqtg
z3BRKSET#OB(_ks%zxW}nFXu~WT~on-0UP@nSNX5e&s5EKqd-&*|K?c=b=UI0eF=?q
z{EPGi*Yg)$M`HuO{2BD3i7z{cwr2juZgjMTKYa|OmH*vqkZa?!-U7MCk5vJ*gFlmY
zPMv(=TVT1)m$#wR%@5lHup9g_CMtXQ(Fb5mFF(8k&^P&UNp!nTAOG0^^rD}CfG#h*
z&9^*(#sR*)7M&U7KSR^j9sVygZw&Eg{|T01{&!~pbB{kvCl*HdCqlt;pa1B2C>-U#
zMJGVV_}k`T5GMGOuR-o1|I7}^P4b;7a`lM6jSjF*@xRzjH(NLhI>-azB3SGWOI-zK
zXGrW8+@jc^n;@3Hc<us21ll|VTl3N8DfpC9yS)S)8hmfTv*bDS5je=F>MJ-*Us^xG
zmM<|f{(`$VAh$;ld=+2;f<GvZ94N>Oh1o%Zw>}1O1Pg=`z=Q~v+hB00psE=v_6j_|
zhl()4rdWW63y!>s$_PQO5Ix){a2f#iegXG9NTlF<^7}*yQcOUJ7QFU3$N|A$zL1L%
zd@Kb^tYGRB49P)3lpi$23B(kQix+%AU!_A1fj>R0hXw04!O|mwE97oY5UA-uXp$gg
z9^{V+ZqQfwxS*8|vYilI_XGAx!31q-lLZscfb*0f{yTK$wBU{hP|gURc?l?I1<B)(
zOA&N!24|{Z<R;qE1W^?KP8X=igMLonSW=8)hG3fp!**Wa*$%V|f?2B}m?=2i379NF
z>~^$e3;rY@Wsabpc1ITlwRGz0lHe8EiR23IQ+7t4z;yzg`GQZ$$#7Y4@;EpP1n!jN
zQ7D)}XNijhkLJUQV!@h+XuBeK*6{;Wln8#K3B6Ph`8IgU1Sc0m{Z+xm<sg-U*FS*y
zRf6@iz)~%Ucow8aVA%xDT0vYENS$EtAW-TBf3-kUgWwN}UNj2coq`ojg3P)2(V7K5
z-e_wP+@cJMRzVI;`E7zt%?=oRO|bEGbf#UflfJthg1KKozEiN8ZV|gKc!hqSE<sv2
z?CutbZK%8<7^AeP9>J|NwDk$1Qc>y`xKL`$EkW&Ku-q1S{sGJZf!Y(M-4T3D%Z(wy
zI!emCD_HqAO2Y!~7-gK?6S#E)dqhyU5-_8J>9-+2Cb&5X`EkL48yJKKf{WyAm=Jug
zhTRVZiUnYKBzQgmZBv5t<VtoHF7X9%6{eAoW4BQ96-sWx*Jvtp7oH0Sr-$$zav6FF
z4`qXR3#-#+O?zU7k8p0dX(PflD~>@TK)8zn$$`R+Z$m|p(04W}gM|!Q3xo)r>46Fr
za@goom@tWaLgB)g>1c}(uA$tPD4}XCu%m@9e}&2eLg#oG6C-T;5F}REN9QHtgbymv
z`*`7REr32GtSbQ6VIkYmhW;KAmX@J5LD)pOor%H>`Wz(*r%s{rm~ekOV2%r`M<9Pf
zxa~fEyOY8zk&r(nESd@N(?aJl$ej_MM%QMX6@K;$1X6_4gcyWW;ZJdpOB2?vhg^ox
z%O9BMh5INHdqG&-LR*+j;fqTlm?d0OiBgX6tFO?Ri^5VmDRD`-ihj{t;jTBJFi+S;
zPR4v;$_2C)2rtvSStwjX?`@GV`z%Vu!bKFUy&^1~4}~Sdwd5Wz6CR-Vpj@bxp;RHv
zqgkg?IPo!sYpR4t=n9@{A+H_Xt`YuCPKsI~pK@{Pg`b=SX%Oa7Sh!L6ZZ}Aiu#9$m
z&BDVJuxJtfKsifo!nezTeNFg-8g1>uHRRvw5U!@Vw^KOzEjX_WFH>%FxA3dyAaFw%
zwwSidJ;FM2y7dc<UqJAd@X8$s-WHyu1>}G*gwBEt3V$MJ&X6$nJkah6IWM3zEc9i7
z+!I#+4Vy-UubEN0FN~$N+NkgeT11Zv^WQ{A9|-H-g=rJQ#DyRag=OTwoD}|+2m!~G
z@H;wx<SaVX025tAT`OUQtLTeYQQ9pU-h<w|i3Wd$h3=v?6eRW%y?FpCyhUG!fW=2N
zmsS?Oq7@&3_=%cn6YMVvz6F*&qJP$d1c(xzK_>!5Jc`K&iMq(Q5-eIxQ(=fh^eW}H
zgo>K-!Ma!U0WFQgM4uGFws6slw_#d@=+-sp-6witAu9KaW>ulTk)k(Whr%e)2gN8w
zi@Nma(*aTZ%TN&`az<2pMyzNh<y;&Tb^d|2IMFWp(8i0(i$M;Fu9pG&u*eZbYpx@r
zmvh0IAX@(tR3wUa3LtS*)Vu_iCW#hPH2j!okg~Fli~1>N<Alh=3#F5ySXw+Ji$*S^
zGp9s#Hz0RfWZDRUGon-qAD$Jxyat>pqGWPRrHg(KhQK+|x*x%rA$sJXcRN#*)dTq~
zk(PeLY|#OVms}FDFJmlnMFL8>$`k!D47&?N6SNF16kVnLZjq?v5Clp@sZT&tsi@}*
zs3;R1r6ulF(Vb6FsucB#AYLW<IvFEVD~dk?lseHO`l{56$~RE%QIqJ?-QZ~!$zB9$
z5&ixNc&>@ABtyPk^fx(9Iz%r~(6&>w=|1eeF7lWLg<YbFFJWl6D312BH$?ewqH8^(
z*nFV$iacrQbyFlv1xvpu`Uvd3B|7i{O1DK1$uBk_8spJSJSgJRS7Jysp@86B(esa?
zhr^<=Cjfd+WT!pAh{)OxWA2MQC1@KJ)oljanCSQKP&qDog}guyL>Em^I3aqUe%Obi
z0eaRaMd}b>J`%lA4$djjO)c7-#ZwljcM<RYlyYxf#hwk|aTlisL7|6u9_@ZT#pPWf
zUgAVLIp-~Q5uoHFjyHhQSDbVPoPJ`l6=-|JAJMWbKs=LNVS(a$HZ%o^Lua5ZSnNh`
zaftYz=fM&x_9y|_D}F%ldxUsa7up>A#ICf4*)KNMK_XiG0eyfDh+o}^&cuiV6G39d
zw?ol(P+Ub%NxWD&0riK(zmmJ^u-N<$+Kz~|YtWV;7SkpvQM@e*rK4j0hZwFTaS3Id
z923u{-THCyRhpSn#c$9oo#qg`?m}a_cqIq5=fpAO`Ogr4@(p0li~D)dbV1xP7n(A~
zQrbLZi9eZvQnvUR+PdV3XLCR<isw?!;3aX_#~``l6H_odPdtxi+kCNslFu)TcX>m7
zftbw(OQATPR;oo}$Lq8vC>F2ohBa5j)fBxf5l<U{ic<0OcOg+G=KqAsa<Q1QjVi={
z#ewsxcvBfFE5+~9OIam$p^Uy-@j*H%SSPNf394Q!yo1UnaTvKnn#CSo5NHwaxroYE
z@z@oBwTT%H$~L+t-Y^}SI>kMdfOTE`<BRBam-tK{NVj;|J+R&ohwq1ckN6UeMX%WY
zI6!ZT8!v<Oi4W4IqhI{=MwD)e7g7q+ZSj+zVGstyTnbGNiu+oDaz|YG12~7ot7%Vq
zSA1_jg=>bz!+)cAPyF|3@QjEXt6<E1asP3&jf!(9wm2sKAC1?z_-BePKM*?xKqka}
zB49rh7g20*QhbVnMvufLZ=;7(Vm{@xI7{}5A?_mi>MG23mF!ibZMWoAnqJ)`4;twG
zbC=Z7tL7ouQVPAEk`r5Cg_q<ky<FZB!)oaDk%(KN!dLS89#r~CE?1(`Ut*>e%^nHo
zbr>2XS>*%JV972uSVAO;bbuyQQg{$n?3L6|j66*8fdbIs63!sxA|$n#bsRJHN!&~*
z?w8!~1Z$*ZZX^tjlFXvCn`lYH8VDYcWYbbJMk1o{VXWi@$|yQ0!7VhH*ClTSLVdjC
z<pOXXlDruSl*1AW<vt`xOrEeQQPNFw{!z)iGO#2`=Kc%0W0IMAjG^O%L^~Y{PfC1q
zA(1QzrS19|$#TjrIV&lpxhzG}Mh9+FB~5me(j+$&P?#<$2*Qw_lN_aQRE9*N0O)y%
zPd?->NSgT&$dtUp1!tCI4*AEjC7Wl1Ge`0{dDkyWmNr2BC5L1Kxma^0Us66*o@9C#
zO8JuVedyt3$=+-jQy>|01u2w#O`rWDNdnyxSuE*31I{awR1G*wB-;<cm{Lha3Rub{
z3HeY_F4-Ooy%iEU?W(Rys%d{vDVfs_fhx&8O027vI0kFLS|hnZhp%cSX9H1ckW4=X
z>_*Aa|J>Y?x5%5*ESZyo$`;8rYHOAJNp7|_$xNEiuSrJUL1nw-HCmr^NK(cj&?#x6
zby1hZ`~-T|Eg7fa_6^CbBWN3t<m7-1N-7)_m%1aFr-J;DWO+79cO{eaVB)YOm{{*g
zCdofGBB{OvwEL3LFF-~mPyV+~m+aD_?SVx8JM>OSUdezl4<+{BQ8_8uL~f%;l4?4h
zIVIsxYNv}-PkS9#sW<tTcT3kiq6-Z?q%YF}9#5$g9qjUwwzZ<<Esb~<B_FAEJBY9J
zW;0CllRkVCC4Z@u9+o}Q4`~w|ApMve;z81FbRr~J+7k<w5b51YbRtw*<$`hEE1h-<
zio&FZbfAPwFT4v4`=sJSwEo;L{hOZPNa?aR2u4YFDPecCw2ypQG16(2juI<fNcX73
zN&ljSSiH2J7Gj5_jg*|6Ag%cv;)&8B5<e<+A@9T)>46w%IxBrW6mlujALqb|RH=}@
zlxb4IbeNqk{Sfo2W5#)DGo9zYAe~1(uuQ4`83<-cw=_Y0wzSF!V{)X;<OsYd9j9ce
zOVT~$w9b{z?t)yNbQ-PY^Q9j&L+@qjUz9shDD8L}0!7js^8OY}-!Db!inR1SSWzPV
zBo>_I(gunjI4Y!k`W#-B?mvNIr8Jwi@>SCJhagxjeVdC?jr10MBx<F`^$@I+M$;0g
zUb@N^_BKf4$aB#s^*;pCByFLXWV3Y9Vu-g$uQkKMR_WGa$hAoitpK?u9V5SXyL4wX
z+BzK4&?P8#N=FmW-|N!n|3s-vs_lS$w=|go!Z)N9k6=ZQ^zC`T?v=(Y0?SP)pW6DQ
zm9t@5zjPx_8@HtK1t{H?zCj0~2c$1vN9CaO$<rWrq-UOj`XOoM1)$uOen7$AVX0$%
zFErhgR#V!+i1b)Lc<xJo&PC&>l*a_xnAD3LMdQ+KLtuFz9pwUTLRu@wPw`O7nhUch
zr86lx@{u%{wh2?xONFq|S+@Ng+FWHC^4qw}oWDbxhwL&fEIegZ<aYIvop+Fz&s%on
zU!eKOT<O$^ugqQv2|wAqQkdp1+dxnL9@*0&Knsv@=uVnI**X*2f@C$%fCS5W=_3;&
zn<STGq--PoOi{87$|{bQ`G1491G0Qdhm4Wk4MJtC?7+7ego847E4_blvb|I2XuK@F
z0i{E-&C9@ZSQbsIog=bBdi@h*g%lJ_l-;1*iKDXje}%nCvM*`Jc1-poIS`M_J|WNW
z30WqsX-~?sDS0Sa_U#35o|4(7p#HQh@dy;1k!AUy?W}C)XXFV_kyX>@H&rI2Su;)c
zYd_@EWiQdL;hb#CJ1Awy^yKP1FWXH1=?k((N*>CT{iOp;mdr*oc(zPA0qh*vDkV5C
z%F4+Vc1h;tgu%;|y+ZMlJlTvMVCKuF)3WNa?8&{;@ctFZo+Rg4k!)xJ*u}D2^mtv7
zz56!wmdK7j2EkI<oHdXrlkqm97v(bBOQ@`nouGt_tFpuvsHl`J-U3o3Q&Lc`S{5}M
z;x)1l$RANJYau^xgDgJ?7B<ReJr4~{vMB}H9L=)N!a-YP@(vi>Dm(igtZ0+%Czr=H
z+0&E;+Ae#e3T+*-qES?K%3dRf_;uMHKge~-`le9omPL@q<%TSj_B=hZ1{a|8%I^IG
zmYcFo^I&$Ltc?~3{j%tlXuBm-ZUVXOkj0W0c0l$f{T;!e>>cv{-jU7MqBJBMm!Nc4
zHm4nWhh+|WW$wu?D9|<{YoZe{_hpfvgN(|uzXRu(tbtZ;<Fd8n&UhfJ{t0A4*8Uqb
zJ(O7|Va24Zq6a9CWSc3;cS`1%P1hMY%Ri>^+AY6v0upZWiGzS~mp?F}+g|cDl*{8S
zUljvQKJrbELC{~m%n4+V{1FAP1LW_12bMrNd{=lY<WA4Qm|*$bn}80H&;A~zQ29p6
zf8HzKMz2bkyoi>A;qp4iyC_D;H+>G)ee$3oko|H`iWNl4U!}=DO8$UStfS>iXi0xS
zzVIOw#>k%_Ct<97j2@4J@<a;Z#>wl)U}3!cU;6MJlDAC*IV?}6kmeEj{Y&Ulg8Z>e
zU?$2Ncc64kzJ3jP!jH>~$(4OVex7E%Q}XBO1n6nGJFN=O$d{9|@2osC2c;DG_Y{p!
zm0zBN$~3wBMHrecU;7Fw&&j)kQJEp%Ap+QW`2@KYF39&30W(t`_C88k@~K}zvgMEM
zg%vsS6;`@X<f2^C2%byw`6}qmmA_U3m^}G;`X=Yg`(j}JWx4V)+6v^xR8$tqUnhq`
zk^J65{FKG=u=PN@BEL_wbcvkr0#YiM(^!<rZy5nyE?<-gy_NEhXdhN3XYo*3EpM%$
zNK}n{)#H$_m1oaKW1ak_4k{YuKZT<gP4ayd32v5Wq@i?E-tG%4`sBi&p}t=pO`-Bz
z^063T-<H3af<YLN|3E9SL3#2HRNj$KI|aERdF8Lra96G*vxntkO3=9{&nHKoV??eB
zfQtL_jySN6%1_k5{4x0wnqSA|7iqKfKpwgl*c0-u9Q5g-{0=1+P0CXeAm^+Iq5MD>
z1@9R2x+;<)Ah%oL6oyJS#d2>DcZF~q0v-yb3M`(Ao0PQVrC^Yk&D)_^_YR6aiVuol
zo3A3V6B2%kALyPbf5lP?1?^F+rq?(?Q9!<^K*e@CCK;qyehY>ME6&aZc8H>y2b53+
zm$o;1700il6s9;$FHX3kmCkoWD3(#cVxM9Yc{=wiR+957QsI#C028HnGXTYC#kZGG
zI-pqN2f-M{%QR2MD)uq~dQkBuE%M?N8hW7O6%CtFI;6<|4Wo8gae>~SBZ_VGRZCFB
z_u+?0RQy02nWKs=z0jMaxc?ZSk0~6FLHxMlIIYu9C{8-aRdZ6&Nz+HNqB0ZYl%kL}
zj;9q*k?;GA;>2u_vx@#RXiHHD*2B<L#bf^k!W4Tq0xeyUNr9zvimZ>JDML|~3+(fX
zpCUmnDE7NUZ>FO09iU_>;@3euTT$o_fgFWrJbA(|DrSbE_L8EJ=D=LV2Y-O%DaL8b
zm9J=`t?gw+b{KkCplG8%$}CjOp_#l$krf4)V#SBez`mj=cohOAijg!_mMXT;aF;3i
z$-RA5VcUyRr6P-hH&u$QjR31wtayyl^=cFy6vn7kyuAXQsZ+d5NrUx@wSMStgF;Q&
zoQ;YXC^@W2v58{r&5HG>P}!pR;0vI&Dh~dRac)y2(BiN|@$o3yIu*D7`$#DMeGXt<
ziUqgP)~$%12eWS|_N+qbrlN8_`Cs}JBVR$jU*YTpD+UyQ(cW@UagjVdcNE(xk$70a
zD}pii6g{*l98tuXV9b5Rnr_%Ts?fcUwlM|wMU=)B$0@hvfg*sCjwTcvXxaTxu{{%&
zlZsQ%!?Z_=T}L1=rC>b^Fo(0!hi)WrQEvYdwz(>wC5OUp<@0o~#7%i(6Mh&^Wdu1O
zy_D~!LeN{eDGhz{Q?4F@75++hig)f&4s3yVfO7Ro$OS6PlOPbJWL$&7VCB|}&=jIH
z(B)B~$_6^HzE`=33-K_A^0_jo2v@#9A-4$SH;d7@PZ{3`(EZBZR+J)@FVR(HQOfjT
zU`H#zqiacGl^dO);-FGug?OCOLjml=$|id9k0}3~0g|9(KaI9T<vV}Cw4=&pPob2g
zjIKuMn6m##2pm^B0_Y;56Uz5o(WjHjFM83KtbEsw(kbP%ZQwbrG=B+AXO#a&q4KQq
z;Tn(><>N0wMXEBMR@iAuRU$0RP_nO}?YuJnd-V5$at<x2bCoUMqGx%^bL1t+S9TnR
z6_=GxPoc6v`G<o7T7}A*DhL)S4@jY~Sn2U01g|L9egtDmly(YQl`5|cpsh?<;t5i&
zd_xRUp<G7audB+YPoch2x#29ZtCUd(L8_G|N^7iBmQ7)}>XqwhQ`ex3x`4_?<t&P<
zG%1_jBmYaY^2I8U7Udx2*|sW8<eP0%ZVZI_4&|;YkWS?(S|wdq9wdP-Wh8~eyOpab
ztad}`Lb(V%%1Mfe^eTrFP`at?e;k~*luPIXbX$4-SM+m0*-jyfLFF29Vc$^-7t;GT
zq!hAHdslfu0o#U^-<Lt*J>{FUfE-oMq(#%1GKzwk<I3YSmpxEcQ|j@AatkFuKUD6@
zfcT{H>IINT$`m@PI;C7r;X_x|VajpdtrF3k@1|OP6NBKXdPR*kFIB`7wEy!~eM{+>
zeyRndu+(4GO|RM>m5zf_km?H;l!8^W$T1e8s;1y;m}>r$XbV?urt4H9RK_rfN2-Ep
zmlLH@JqOdGRZ0&iJfyM-AaGb^&jrd6)svKXnV>qp6D*0UcTd4y$5EBnEubZ-KGeae
zV=B%pupU>9UqIyv)p^?Jo>aM$6DnD?g6>^9r7HatET>gTltOVvW$c6cvnqZ*)TgMn
zki#Zbb$u1&(o}26VUw<MT>*vXRHYZ7K120O5ZcbG`gjny;83N=0Gg?K`+q2Asje-8
zM7HW%Z<wE>(h<3+TJsJhE~&B(z~DU9**KK)RjnfsxU6E%gcSv<wX<PUq3RQwEsIqD
z^F(E_YQ;T>Us35Pj8LN5z8jq=RsBPL#4^<l4~Unm9CsJMwhEQs8>qdi`kxE1D^)dg
zWoDI%tARwd>eDlTsZj+xpuS$^UyaHJRsDW&Hmd$`g}p7RG&+{nsv4!lq&Ag-I6G8s
zw6gA0#Zf-vb=AUBl)6-VSEAIdx)=bI8>*WQ^55K4MSl#^r()ASy<as%E`$Nq*W~ga
zR0Xjhct`ardFO{zLwjM`U6ti^$PcULN2Bt->V2A*M^)7eK*m&$$c;InT1%_ghpO3&
z!8xf)pM+`7>P6Hg7xlz;w7IGmUnWc4)w^b()<Zq{1+YEULJEg_sUvd$<E`c#28)k+
z6?xl&)T=4qCs;kGflVRmAIOUvsy<5TiF?&s=&=q{XVSViTzz~AtdCGHqzkY2shx(v
zxnG@6o`6X8rROksQR<*W<o}FT-|>Pq2h^RbAQ+?m-vTtos>^?eF$dKPC>cCXJ(dmZ
zc=hA-+aFRF(w6wJI+=2&j;LRwyPy)(>^ih1s(1YZu%qhu#b`@Xul9!($J8ZF(0g31
zehh}5P{%w8MJLsd;carvNLD}f0<cf1KYt5jd0IV_4w9Zx=c*xbR((Gdr4+S-p3YSD
znz=A0O`TbbQo8!1Y@nS}e-s3?4D}m_Va0hhFAC}}s0YrWGE=>%9O7B(H^@<&t*)H|
zmK^n!X((M(j}-vLaY=32hT2^9m(;a9b&M6Ie6_a*rOWCCncyi<KSk-xh3X$^4N{~&
zNxSZ1^}<|KUQy4W#Y2gDjAF2*>Z>6zyG-423oPYoGkL-*)HRfPbyfXj2ujuJ!xV0*
zQJ0<qbge_Jp*Ouj{c`|n8`aAxYobZL<T~tbRX_d?VA|BCe<65H-77|Ar#fgh(5|b$
z(?V~Ty0`=id(;863GP*2V#A7?_|bvcr!ENuOTT&_&C9pcS@de(R&S&I^?>?$^0E!8
z9c`~+yzZz=4gqFJUHUS9io0s{3lO}gPU(aC5p@nt828o8U!ZqXeRMtK$J9==r5;yj
zP$KaIwSqzg6Y7Fj(DqPm{sonjY8zz`KT_`xgr+I=adLh+YkE@9=As!JK&7iD&OzUW
z-I|mf5I4=DtFXdd<Gu%t9-5(#faa;O(zeJ;({UT}-kMLiFvdr-n*nTJ%|E%Q^wXqp
zpx$5e#p57*G$;5lEkN^XEaU<;H+}|ZkjC{ODuXqQk5CHH3@!y{sAkRrdjIxnuC<^T
zreTs-G+fh1fv^b8UD`A4(<o<xWxpou4OkedVWmTTl;-1j=#AFYRKU;!8UdZ!iqY)4
z49-~1j>XV>P!r^awm1!o?$C(W{7V;{9@6|<1L(t==QjZQh$b$b-oFIR6|yZ+<4P0N
zQO$|#(3GT^MW6j+8XHX*$2I*jkQ17Bi-3Jnqx=#u$r|AVj5($Gt{3W0YXYPYIHPg<
z31DY6&rFAk6iw|ku%v24VK635Gn*U{>6-Uxb#+b?o=cff8Jcv;4LGlH=|t@XP2&-$
z&(y>$L@7(7p~z~sM*k_y&(Wx8QF~DnIR)%XnhX8_&DFSJ89O6SGer4K`I-$hcV5<9
zn1)h;#)o_?g&GGrmWwpSl&n##$)VW76-_qnlN}|RE#&Jj)fnjsEYqaZ=d4`wRw%G5
zG`n9#*Qzve`%qb}NqHZo8ci`ddTTWiy^ycd9J!Cmdd)}6ps+!s`y1Genkn)%Hff5#
zMO(AxEkEdO(d>*x?^`wg+fi!M3_lHlYYt5>B{{ciHva~}4vn5xcb%GyIZ$z36UBji
zmu4&kZQUAQ`uyI|j3R+-MvrDfgi^1jnR3%^YCfaIbf4yb-$O;eX4_woyQO&;2Tiv%
z!;}RupqcSCSOzsa$<2I6BRCAsA&p~v8*1-r3MiF#SmR9}+<Tg@X}TNHY=0S=?rTQL
zTQ{naKZCY0O+4)=#x+gXApby<z5|>S8a1u3A8OvE<8+gnaU(|bk>=H{Xq(dT3EEj}
zWuekVdw&yp=B90<kczwZWrqN@9@?HR5KnE&Qq+2B1AT$!t*v80&_}y=ISlsIE_wni
zep<;sRQhY5qMu@qHeeOd0<^2TP#LKGkX*Y#+Q(l<Ww2IBVUrN;C;ku*)%sa5%zL$K
zD6uw7`y++J!?g?+ZL1=*+m@kE`?R*zP_bXjo<J#5J4B!TDD7&>?uyo~-U7h`+HoTU
zVzh$^P!X$L^92+h)VeH(y>Z$-Bp$ELTnW<-Y4!Ce9o7oySili&!)^S83EFWwx1OkF
zQl{Ba?eQw|za(i7t%EhkwB>Y>!g1}>bZguR?Kd=)p46&o&y%d(@hyxwr46Fp{#mV<
z7IG=tISQyq)!MJ2l&0N7W~XZx?}mlvv~!bylA%qQ1<do>rQ{{QpnZyNK*-d-_zeWI
zv?t-pa?Hrq{zfTKm$awp9m~~jqmw&%+Be9XQ=oP4go;A#vD08F(tdFh@+I22V~{V^
ze*FO~EYr@WZPiun%WAY$Y9}b|r%G#m4Wvn{lB2R&>v|XhEn4qW0BhC8*Fm67`#3p1
z9M`nD>*)p1MpG($hc=5o9i7@Gv?{!=RkVSpOM91M&fQuCd4F$c>*OFk+KEiC^lIzh
zgP}LIC&{hYr_H~JwtlT2B@f-wx;8=lww5JAmj<*CC}=yV-E#-(?`T)h6FB717E@>L
zYIjp=?6B5t5n%3VzbOIhh<0TsD(`EDWPlmfE~h2#gf@+4`G?xgm%uWqJw?8(N7@NW
zNtn_OoP~h1F7t0-y69{<XmizF2!Tx=IyQZdJaw1ehMbpfFTGUWI!6J0a(r|ZG|~9#
zLZ?H$pDu!SeEzy)U!yWWXQ#tofx3(VR0iqv7xDWB>r##aCPb%WKs;3U?K!mV)%~;&
zn!<Di`CtjxefI|1B6KY@+3(l!X!48HElh%iQMwA+Ekx^Hapc3O13C`n@W$#==Rp3T
zZXIoJ;&lI#ckz%eI00QdtTRyD@`z4MAGbuEinf7Ab-wNxnIzrGPe6|840PiBxNcuB
zO3AvCWhkA}@yQE&TDOp<$uqia3e%p|X{2CD(fO>TSV5}pZHhvs>H50Cnyx!Eh|+o8
znl|+Cg08I{teLuKI_H(8>!%X{**ZlMDsyz7)2{oX?(hfb#3fxdZCi77Ue_U)r?Y>L
zwtSuKI(l|l_uX~~6zH7kb6=<{T8XwI9jA-_=eAh4_d9g$imsh{QKHLQ0km>m+Cx}T
zq3cNkxvHz7#HLE!fC}<ex|!r0sn$J9UcMS#NIEKOb#5w%*XcG>ZfL!3dL2lEj<Xq@
zjk?3>XlvG;rSmu~x<9gDVXH3BPVZlvPWLomuIZK?2T!~1-FB2Zbic5{)2XX&g!$KX
zU%A1;F5LtNn!0r!w@`UQH=GWZ9$n~R$o1;xF9Er!+qVOieL4a8A^UY=$~?KH8;M5S
zZJp+6lm>J@dtlR`?(YL2j=Q=wwV=Z~4<RJ(>AC`;epGjgcI{)j-8JaNxNgUrAP;n3
zQ`Y)~E@cr|9_qY>kekvS`wQ64`oC6##YO-9<LKdTy&w7G-SmC27(93VKV*!DK7t-A
zPyOq3DUz4|Hf@l-9r{<g0OO-SZ-s=fK9oKde)_Lzb?C4E^+|vR>K`ZPWRSj&Zet17
zf3*!HM6Vrz6`}fvbO+;JeW?K`Vfr5_dKs=Sp=T~a&!T1XKD`soCHwUoXqJxDpK<|9
zlzxH|y`%MxjlNKLK!1h-`5673`{;J8eqa_P4(hjeLvNg(L!pLv{fbo}3Hm0=SV`0e
zc0lf^K5-B%N&0WdcXmwwcOJx#>t~aT=Y-ythsu-sx88$Xvi^7&$SJ+(7+6m0^>kyz
z8GXH@9cX9uT5l*!(Ql%hgj9VlIcL)J+bANNu8*VL?>T+O(~!^5&u@dkd41ErP;o)O
zpO#md`aJU2X6d!GvdGp?gh4Jxe|Rp)Mg57>P<To2V59fB`XCD9<>{koBa^Rx3+`CF
z9r{ArN)+gOB`~;9zb76rMfx+#p|Dt=Kqnrq=$mUmO7wrQz*(v{T?1#CegS!N%JuQI
zN2}1+oCmq8kD-aRQh%DJlq&tDA#hgf*V6yc)#&^3fKsdPd<n+X=`Z6X0^Sw9F$={8
zeFM4Y8};f{C^hN%WNEXWMej<B{xzCtTJ<lGd#+7CgR*9?=_6dAqFuj_ynG${Yqw!`
zr~a2QR9@FFrdi;Ieq}J^dh~z1h_+sR;09FQ)JJi_(x>PBkN!}nUtf|7&|CVymZHD6
z^$#eTF`)mf8XX<fFWmr5cl1k*=+lt?Df;@~)t{sUuwnhO#i+ceZ<`N$NA<}sf^$rt
z-i@|#eH*!?9_a7U-f%)cowlYA^*3`MKB-?tN4_8FGu{TLV@j`}V5YNS1x2D<3~X|)
zxEiJ<gJ-v)#~md%!|DtOdK&&mcY=BuE**e?w;`GO>th%WfC^tjAP+2lhRW@*!r!2x
z#nK*wg7O0c3@y(BCD4$=g-t<*-zX9lY%tN28{#l<Uja<0p|%!0dkxcQogZdMpxdm&
z4ZD=EDZ;SuD%$oLYTtmwenZ(4V2LzD%z?rvgO=8a(T0C%&2_-w{T#p!8aA9jTb$wN
z4<Q$C_?o~D8N!Oea@a7|i{UzAI2Q;j5)6)~X!V_F=%@GZsG<KA@FW?kY1@0uAm*d;
zxM2frPfoymaGo?QUyc5rGDvoyblTuVd&@J1yR^DHYdE0<c8XzI2n13MNzQ0XGh|eQ
zq#O7a*mTbD*CS}iF!<-ert^k}j%_Gr8Dc2=Jlil)j@lf<dJmLx4afK(d4@ye%gQ&*
zr&Y&g!|&ZtQD7*d<$j^znKNiBGOP>(DK>=iVfGcn=w)asF?^^8DK*?BUq_jt{#AgL
z8|KmGxx(-pJr`FE+Y{*fS7~VSg27dW^}j-WwPE)<VAmMlqnwdigU9P=t210a2()^`
zIa=v980Ni#wnl@`8yKJ_LmQp=Yc_;_jlQ%PT3-Zqt09>daBYS!zJtBj43jim?S>g~
zXzMT>A=gl+VZ$o=L!Ik}F8Z{087f^tx($+lpuWc-bAn*6VV^s&ZyFBJ*QL+Eps#7a
z;UXn<-!kO)qw==l*cDU`80;^?m_fs1J5YJYQ1b%hh72>Q+jk8wQ7Y}Q;W#B!+%uFC
z88J*lq|Y(qzTvzRIx}h*BiH?yfj5rQxM3~rJ0BPnlpZx<D7^#FhlcOfsGKx>6^3zo
zWY}8)>?wnq1w);UnSrQuF|MUJxU11lzsPRmkMtFGGdhX^?QV=3!jO0vzp6x=r!jgf
zh{MZxBL$$|#wVgt^f5L+4<275kCu~u#znL!^*8P$N5&rGTNz*pF#baiRG@KU1xS!l
zN=y1+<E`JIKEybS0&t<m_#?pFYwX>Fj)oc4f1@(o=$8zE2xCb#p!XTMq4*8<JB(Ix
z8%G*_qtTft<JIdBj5fMca@hgnI~3lEF&=jZYpgL6^VN)l#w-{7OmRlfU|`1^xeTxz
zGIm-)4jbptNsA-KL5fZ%7@woqZK83}55PQXjG%~nlJN!l36B}QYfyRI=vdhYo)gB_
zuK;?|I7bhXY&=Lup-&kr-O+a1DBF)gJY!t<GuqA?e;fmLit)KF^f%pD`YSlk8K0w!
zvkYU;ZnT{@vdFb`!Km$lK&G+&W%MP>D4@a5Hs*hZ${gbv+SXh&7CXo>aLE|63)bWs
zM^~bhXH2{Xo_ymhTFqWIt~vzP0^`ys$QK$PBR5Ww@kxs66&qitP{9?WH)TSV7=QT)
zHkBF!BS6ZG4LQ(TZrn`gsw<2piqu~<{_l0PRT{nM*Qzqk%BSyNwXwtvjWxzT`jFHb
zPgC+kopF@1yXuY1D^S>A%sqj&Mq@I)xJ|~E7z|>w@u@LXwiutI4DnWD3pq~OjIm81
z*NpFqVPU&5jG_r0#>LxVXs0oW?ozvMT(=FFUB=X%^!@8L#?xNyhEYm8gC1k87aDtw
zTmJi287C;YrO()L8Z7<B<8;&fE#vJ}lx`b`gP>`^SiTv9KWMa+!rnVZ%@iygGR~l<
z?5@#w4t}3u<F|A{{ypQ<^yii%MgyIxxNm&&2IYT_8keykF=mXP51w&j2IVk4Fdn3n
z78AycHz4uQ_zpRGCyk2bQ1Qq(=?Ts$<D29OcQ$n&f)y?%`&QWGYWnbRwCy&1MN0xV
zla^Moo+hUhuy~ooZ-IE5j;Ua;k7>vgRycf3wX`1eGmTO}E5LM)lC1(wPrZi5Ak$}b
z$S2e^^#g3$Yx?CqfQFgaS5X;mN>+nJm}Z?r<vx>b3&?)cFE67nk*2WsVN8^1&PyQC
zroOx2JYeeo3oJ3FZUy=hX9}Wtf4sx=m<M<cndFq}dDt`*htd(#vuQ9U!Ib|Cc#=$i
z(nji-Y1&(WId1xR4cd}Tn|e@r%2Y^M<fl!K%)m}DJ<$j8RFmc{fTfw%C4nW~G@aJl
z=S=zJ@69m941wjmDUkvI7fg<R%FD_$eYyyZS*DqE;xF68r-LmyrjI^FWv=N(a$@C~
zItnm)`KG4D5GXV){uQLiw5A@U*i^U|Z6&7rw6iWXz2FADWu`6d5HB}H(qYdElXN30
zubP5r+Nm@pQ`UNwX{&>_iq$3$J%+8u)Wbz>t!WMUZ|Y6YZ^4h(V0xC;fsLl;1wd;u
zU8JCVv*}MtBxy1A4nwZhRPYf>Z6@Jn2wXF*{1`oKH|fX+cHOk|YpCxsO_X9NyG_5v
z!@?V;pXdqfF+DfwK(W{KjR-t_rZp6X=r_%xXZ@C`{0sEywrL)%GX_k<ln^y&x*Gt~
z?wGcDVMvBdKLw+7*R+71t6@`N4UD;Gii$&N#3VF><-Tb#If_P29rIBdGZm)*?15<u
z?V2Y{8+x982T!*tgQm+#Q!E`Udt_SmJZzgX9r+m&&gO+nV3Uhk8@^#DPK*6O*?aD0
z31tCzn0NdI0Z;Q{3R`-aHy=eOe9dQzq0rC#4CQh8o5$$tg+TKuT1Ez$`}RRmu(|gr
z#6!%5G(Cr!-%CVkuUTb4DZ*Se1(bc}A888QZ>}O=MWp%65NwGuZ*n9;KH9u=F~;J6
z`KMiwh%p-|3KDC6?-=wRG`~&BdvRvtfAJFYlFwn<A+zgrSaI0=-Vul&F{eKXv;^}Y
zB~T`sx5c3Cs9F6fM&`Kr<F^5J!hDBzDJRVqD@d~W7#-+5Wv-d+06lG<-v^Rn_H~6s
zs`=nWz@(XV5wI!4JVGD7^XB(&!k7!@J1;<Crg`>T0L?PrWWnBS^9lOK<e0PHhxkQv
zC&gJVnT;o5MXq^vINI{eykL~_%|Aa6@yq5Ka*`LAzwDyRRSL~-_d#Ki`QGzTQEZ+H
zhx`?DD;s?(F}skLq162CR$!Nz)099fH;-%vT7|i0DbTK(IbGnaG*8kFsLFi47Nu%4
zgEp~s=C5e+U2pz-0DWmNx0Bbm(Hw3^Ws}+JO*eHmn@a-G!xr<}k08-%{*gRPZRQv0
z^}lAGLBri{zFvaL4s)ahm7QjFJycvbALxZmUFJk@pmm#_Y4*5bZu}gaJ?7^qRkPRJ
zUWC$3b4fWm(PvJcgKqbmFVPh|x6FS&1#!o1^GtFk4VZVPfOXJ3K@Z{`^V1Y9x@-1%
z5^clgU`j{1XHMG;m=W_3B}CmfH_+B})cg&l){L2d`3wT%<`R0TCd?TYkcZ~ewD6lW
zFP{N{N9LZTP(NiZr&yV@<<rkm>Ef`|yaB=8mJpgg+$=M*(CBV?|04)`SYm@<jHhM(
z8$k21`0ho?*Wzmhr=O*X)_DGwOiGjAV`=4K5CSZZ?n5rn(%FZ$AWP6@v;|u}cm|ar
zmTq!khg!6Yp<%DZ>m)G4EDjwd7=>GI(54~6@)u<r?z8yNS-Jg|1y$&Fq-8#NaiT0w
zUV)*}mMg3AiyW}5!R~oRjAe5;#A7XAxWcA`7Lfp;ah8T95RbR0$;EQWa(xp}4qJF-
zu<(fGsZ^jOSl%KZeWK-%V-h?^Ej!<biX_YX=V9Ur%lfy0cGB{JGq95_zK@}F$`T!o
z(rL?zm%(zza*<NZQY|y-$xXAY{m;#1*_?*9bCzlg)Mr>eqr|}TmOdY-zhF5}Yqd;E
z*g8~ZS^lX9ShnS$gJ#Pdi$ILpi<a9*VPdYuOb(1Zi;5h*`IZG~u=KL!Q%aL4u>7za
zoQ0N-!yrW#&lON#Y{{DeQevs3@KULTkpa#!%LE0D$}NxRvXKhQ=1vG)wfsbVskF$l
zP+4VheS@;)t1Z{aMN?xDIzgh=A_+n->MZ3q(TjSE2L%oqEFTqMoEj}j<OOQ7^gRao
zW=r2rlv*q$*#K>|?05$PZI+N*AlEEc9-zPN7B)GEJ1qaB)VNN|pGqjYZsF23VmB<|
zn7VOV({jZd61^6;<v{DRd`Rh4{gxg|3cY1{RtxpFEpD_;7_gk6Uv1FR_6ro=v7}c5
zd&m-b9H4hC8SB6@Y$;j|@q3oY-yuF?S?mmQ-?EAF<;E<pk3eAD;!U632Nw6o!ReT=
zq|l1yp~dG5@I11-N?wsE%WV3coUNV7Q14<5WxzC7Yitxa-K>w=A@6RTP74bU>m2&T
zd0N-ahbAxUOxoajTUm75fRDBEUzB{UTgZFlXT27NlE1Z<2565pg{Gtchc%x99)Z>c
z8_*bJ4W>6X*!ugI;0du>$!Q&GeTjqq?zI}okr!qa(W+y=bxjjUq_rskB+5D(1hb>9
zDIQ=sU~Sz5@fd4p4#Z=vd)EW=pmjaXt8v!-Qs|4fF3Uxi4qF}dbobT~>&TyAO|b6H
zg%ycb(YIhdYGu$~ILR8GgtlYW6=mq*ajRo7&`ww@W<dU=_47kef6Dre6mqAnLvz7$
z#`@ap80WLrTOWcm#d>coz*4Q(W5AMTEu+&l=~nq^l+Ia$9WH>$uwEjM+Ig$^57?Gv
zb)u|=Y->F|b2-+pC{gvIwTm_+m#l9_Krq+(5^WgstjQLL=UYFd3H`D)coPH)tUvw&
zy@l5A=@ej*b-^l>ime<vr**~p`Bn&&So62Trc&#Ie2Ny8SwCt)vE1rCipB~n>u*$E
zwH~8AbfvYO_BB=3s}+#1ww{%Pv&P!{1F&nYJDox5tP`|9sJE8T0-?dWgwjVFt*;IO
ztjYS>2QakRn!W;<E!H&3NN=_J(v#b6ee554|2nJ<y8zQ^Eu|g#b!$*3M!n1W#XSgi
zTj!D+<%adKT^Q#c>xuQ??6o>2L;j{Uf$}Q)tZB6D?zeW+V&|4Ma}CIC>&m|&Fkp>n
zf!;xDNH0+CSR<YT8M5wsgtoiZpAjCy<+j#&K0v!?T^0qw5$k)c0KIP=c^W*U))D$F
zj9L9?i#TqTbD{o$^$l7fPgs}IX62zZy8tYc*3T%6@W}cH9Z#FGc29vg+jh+Zii_>w
z%Mft2WxofM-L~@IQ0Zplz7H0MyKRJ``5v~-<XiQ&`Le+3W3$s&$=8OvT=C}EPEkUW
zzwIPFvwLi=6(9k&_7QX@(6%WB)(6=>p$}%TZ5gd5Lu~p7P!VbqmZEa6t?U{6c40Oi
zeSX7ji{8X=Mc9(JpmLwX_Ss*c`)zmMfTl>BM1oO|vK3S6RJ6@?BPtKr@(WOku^pp$
zSgh@j_kexS)=u81INP^bD8<{_$z6QNR-1>hIBe^E45cHswPZztZSL1FG|@Kw2oxQ)
zxzkkuCv3x7lup_luj~R$vaNI(EInl_I|bI$w%H$}hi7bW{+F?0`}sNaDaB@>>pD_x
zU)G_NZfmqa#W|a@8FCr6Ia?uj-sVPc+y&d8-N4SYC4GwiX4yKHKw-8mniS^P3>1sJ
zXgfpBm`k=0$5)WgwFU12PoC`%xzO`%HQ%AJ(55O!Ws&XLPcWv~c5*ZHmfD`DSEbCR
zr<H2CO-xUBr7iUmG*#Jh-i1K5E!`O?b+)bK-K)2)Sc=L9TXHxA8f|l`K$>iha$q*w
zr2P)?T(kMm$%A&=Hp+|Yuw6?7>9k46n|j?gO^Q;NEt!`4-L@UeAb7)efU;S7Z1O)r
zdTlSyflW7U>rVr_&vxl;u=LxU&tqV3*&g+Q<+g1DrR@yZF7JS%LE8^&fO*GeTuJxF
z4B56)M$=u}+<Yh;wymb4?)Pkgn}IfB)6mZNzHJLRd`4{=+BJ{a;wUyhZu58q^1vpf
z?8ph*eOjkKw7pAbK_+eDJXAiioiGA($~N>3O3wCS3JSQ`?<Jt*YJUprUB`^wcKtlm
zy4mL+guJKyJh?i(>?gKCy|;aZ5WVoR@1wYfuYLOmK=ZRFJiq|^+h3)z*kfPPi^>2y
zdl;aB_O0Y*4zid30J&g$)g($G_WSfv47Jbm0OnqME-gC3>^@EqcZA#5Qu<tk{U)vY
z_u12Ei@D#fjX^2WzQhQgDEom8P#A5mNJrZN`_gqFF?Opn^v2r%p$xf$_D?7d5NChv
z0#wA?yS9KFvO5nz(_uT80@z3FDmp`wU>|!8;z{<sEVLbS*jGFcnB(?)Q)oP4ulf_E
zllB#Z7>i_kO*&vs+no(if5zTOSBamsr<I^HDfYTJu%z09^P%^g{lOC;8TL;psD9qw
z-2{OP_J8J}lxg>30yE1VL20Mi_8JQI=GbrF1@uL`;}*UC`S#@hJX7}CB9sd3`wM_p
zXg?DSo+7({1tf~?eeOWJVh^E2ffD<=*I`VlJ@F)ZQD)yoi47I@tW6+S?LU)TrTu#b
z46U+%mxRh{yOn$mwe~kDX}-?>T@9?Sw?FQ%0j<IQHf?<x?Rn(6XtJwsVep&n&&$Eu
zYWLUz`8NA9+BjabUwa9qcKdXCt2*opK82=E`vQvHUbnwZ_ds;pH&Y_x4g2UckRE&V
zHB|Q6&%BRL+_dkZW7&Q78p<!~x6jLRK;gK3*9@Rd+9!^JXUe`N5$auc{Q4@e-FGAo
zK*DRsS~etncZg~3-m_zg6F6gch#N2@$9AMwK>ev5QgTV9><GvK%eftwzC`7P9ly%Z
z(d->T=Ye@?M=tgA@(!5|l_fhqcc=HSd4~rNjW>5h|L0QP(MtIh6FY8ShE2P7UZp*$
z=g#ZLU}(V3#>-H+Z|8gYAP0B8IUQCU-FYwe|1`Y^SX9UNKJLADcVU;Zu(#|k3uugq
zJ;oT5SQ29_i6!dC#Ap&@iP1!361xz~(t8&hMU*0_NbgkyMHCQ40Sh7`peTqHMZy1j
z^85au$A`0X=A8GOnOkP&%$X}nsoNLIU_O7l>MiV+Z68Fj>vP+?#zLfK`!Y%+ySn|t
z8i)is#A{$7+~K=WTK~m3{BI(#Qyom`>{*t>E(#zPIXL_TpUye_Z~=8S4t=zuxbE;L
z)@<^-4m&CJ<DSDeI=J@OVg7oUc<E42OQtstMM|i<IPRbvbRWli^u+l)UZpo_h-1Sg
zVD5FCOo>$Cjx}yjH^w?%p8(MW$2=2QN_1S;2GL|kS5i!KoZtk}Oh+TVZ?YV}XoE(!
z<1jVqavTFGJW%M^N^iX)$J93Xbjq=xQkY5{_q(I+wBx`gkW$A_f5n|p=Gd_tuAOn5
zYXfrD@q5aIIA?V1q(xeV<JJdIyx{1+3mTP<Yo~!(<v3{re5!WLq{OC+j%VnBzvLMI
zEkrIm_EN~A*3n@ve7fTJ<qCLM=lJg%NY*<#QLv%GaRr@jyXIIyLD)NvLoNcd)iGnA
z0vh;N%HX2{wEkd(L-c4cQ;xu+dS?3);9p~|&@}1>Gn`fxjm!%=i_pZ3=22>9>NLP_
zWmGgKbTL!X(V!ltiN*vcw!aI+o4vjbC?V{>F|>V+e^SnPIP>o9Wc(hY+z3nW1*TKB
z+WSc~%^dm>E$t`R`l5Q`Z=+E?sd^mHCx7q<{(k;+7izyKr+v&Ro9CdXzAT#txT!z9
zLVLe@bswB*nUo4X{RmP}<ue4Dx6B;NL-*^ISE2jOq8pHzwa5y!v%k9m-8qe?@!L2z
zC>Xu-?Mn(X&WkU@@A*X&QL&(OAX@dm)3gv+xS6`{J0TA;-xpFc{Gzk(0`!NIivha$
zTU*pF>3#(Mk0Jd)`02q+{QlW12J%a9(M|Kq2zoy*dxv84%S%1MS;6GO%CE+=^!8u1
zHV(b@n>Br{Wc4wBRIm93sYLSMzZ{6)e`I>Wz)tT({B>t`P$H@aV@f;eo{S}-dojBy
zfz_L7%!OSaCXYrkUnXf7ApDr2&(IhC%<g!I1T(h|K<_pamIF^7F*l8K!R=-u=>6Ht
zEWy1Yf6W+ZqUO%784cpWZhc6W*b7DIOfS}9JxqABrF3Wdu-tRN__8Z0UgyUSrOZ=*
zcJD<Pj9@Eh5fjPQQph%*9Zc^b1lvZz&@pxg4Fbp6i{H{vc!K?bjyWW<zfz#$Bs<|4
zu#?z=3>ZvioBSY>!gk*Vb}H*fQ=ByR;1HD3S^H+#&0rITp_Ii2P{=8pE#C~09JXHq
zSSA-nS*=;zxA&-yJ4%Ppa=1ND;Y=>qaGy>q<Z&L`A)3!+(juyW`<eD}3b~1tk6Of?
zNP~%DPPGLvr?|=$aIJ)MV1Ra-yI=#DQtsLUD3o!_r+}Q{j{Bf3XSuJ2L!_L$PDk3#
zaUX9$se+S_1=xA+gaCgpa8sty`n!@lqz7mfx1<3EtGV%C!qP=9k#@#vxJmzm{v|Gc
zJ}h14Ru6(=E$7k<<`u5@AS_+w=F#cGI?i$dOw@A;bZo7G6G`$KH=Z_SuXDpG@Oy)c
za)sng?%ZpTMy}}_STNq={OI{>;xZ}ndz-uJ153?Z58Z@!xc4d4)xzmbLGE(98UWME
zO`>h`HtujOO6}YwQy9F*J){-geePR&XgfHCAJiXkV}AwaLvGDV)OB+Er$euc8~hLo
zkGO!%Al*jJd?!R7bH5EmCp_Ukr*!3~-0Q!<e8z?P!qey6lSfc|!NtFex*l$N9PGa2
zo`(VZ6*r1D)_S?@LNH%*sS;3}WTnf{mCmy6D(I!iR`ozHRknUBFw<nmqESkhE&2!w
z88Tz#9l+pgLk)n*lAV48Zni8m5q5KAUH>I}%Z7&otwxr76^fT+HD@4sS(Zi7u$wZ5
zQWY9yZk1?EtL*(fAZ@Z;JQVKB?k$E$hiv~4=y}QuC`RQaA4VCZ-txC9IO-=~Z=_+}
zU%tf;+yG3F;Y^^siz3HS@(&k6BUgTh7D0LPFB(De<p#Rw1@iM}p<gIpMzg*m`GOx{
zqF8<{737rsqf@Y3A|FZqmdYm%hlgeIKb*ikBafuytFv<Zc~CExk87a#^Evt2F4(P*
zANvt@&&$saM(b}WVyW3pijg#@x~*`H0BKg}M?n9MV&=QhZ&3`T?!K!S)eMDJ#fUL<
zwG`8y!^0N}1&g}3ia7c-iId6TY^Xb%<XnaqE++rdUY4&(RwKoq{Y<9%gX?dyYZ#mf
zFo~jRTaZb_81!YZ$@4cTg_wL?f>NkSQ4?VHnp~#wc%R8!iWTiQ`8*D#aFgYKfkc?>
zyai^Y$p=m#F(%_EHkM(sht`FeCQJVY$ue2<2tAW+vM1}mY-y8d%GS&`c{&A^1t#&7
zb6RL(MF-Q1Os*}4`C^kKTa?O8oM<j~&g2E1JF75R=?;bSCVx!=^Mc9ncA!+5Y}pF+
zYLkYq(fWFm5DnaJFp*WDbj@VxdH8hQ#Fav)H%&hO3hKs2lS-Nw-!d8f3t*Z|B13@P
zY!XN@>N_Ualfb-dGVwFOw3>{fH%z<9kdsijXY$=Sh;*1_=7Bsk**pu9ohGB+1L-n(
zBf<+8(@&Pe`va!l&!BhEbX5(QVWwFjFduF@okHUgM$@tMx{NeE6AqX|rl)9+G|Kds
zyAVBW+C-TLF{Y#H02*uhJLO%(nJ%JO{87_U7}n(prk6H?95ao34=Be?$G4+&!n9{L
zBoj@)oDGyr(+3~Hi!9S2^8lS=Ix!E<<eEM!0%o46vBe8A`KG%opiyXAO#^U|X~Z#9
z7MuRP7NDn0U+d9PC8jlwV3wL%)dQ`}bP&yu&X|6=320|cV`#(noaqt{3Kgc~p8(~&
zsU01puQdH69Tuugn<%1KZ94upl<u24&?%G-)44_p;y*NfFAS~kG<Bc=a+hh#1&~Lk
z8XD>zn>v(3@rh~3c}PAp9ZD~;=cY?2g4Az1hsLP4rX$Ls?xZY~L(*Bfz7Wp1DECq9
z(pAZ*f#RmT>j2l>l?n9H^-!*UhB{AW^0!7PdMOtUL<@tIb(B9JtW4_!_8#TPTTl#D
zhAjr!r(C-Wiu;vIDgQlLIbjDZr6@n55id=-MvJ<1W$JeT%TVs4&$nhOZ&73-OF4`N
z@oeQJx*|Es?rZ3oT&3-4NaiUgb<y~jul#^U{{p355lEp@OQ%4Kl-p>9Q>+~S7xYgl
z%ln{FqV(nA%xUGg0=g8+I$BAVDNoZY_>6MFcwnDZ)<>YOT)C5Cwda(3DHd3v<X1xS
zys~Q<z%D3%n+sB@yn?I%qr6(#brmufl@s2e*)_^<;(&HZX+??Pmz5JXLbO&{=?3N%
zWx5E-tI8>K3)Cr{?|?KY-&+L9Ys!)@(IwZFM<{{dhVmy$rnsqGLkIX9mFe~{e@j_R
zXSAA>)96mPtvr?iJ!7+S2CW0`DBs@+Zi_O+6qn+z(s?dOt8y|WAhanDQk&Y9vuOf&
zPZ>fJqWj9(3t=Ky754_Ng{Yp7fI^sR@Hv2ntFmZb6rtj1#vZAP>H&#Tg?$FF!zz6u
z)T33`mV@B5^kg$A#;Q6^;AxyH-4Wb))s?RSlc0(p2<&63QL90Yt5Q}1G*RVXiMk}!
z<lljotg^TT>^xOp3tY=r6^wvSg{miXKNYDOeh21RRX`muFRF@YB2}Z>SO)b=s)qkU
zMk-^wIVx*apALlL71j8YK)b5SNJD$;R8l!QxL)NJ1G^2Xk14_Oj>_peNQ-I(O#ttz
zw3JZYs`6e3gKa8b8V}l47bw1YPgPM1x9_WDo`8O!YWg3{KUB@5xlgA`KMaPtR4a`%
zVm?wa6nyMfbp*lSV^!2IsC=SQPXWwR)nLlpd8WD%1nlRkR2tKJRL^Oz^QEeTCe*J~
z3u!vot5TH#<+W=1FCcGJUr@B9Pj$i*rGC{|`a0BG)dD(K<Yac3zVhO1<~G6z>S8vP
zmL0BUm8(#4Gjo3h8F#Y_vFIodvq1^a_cSw!hWkEdUH?sZ&1%Pj>1TG0R$T#RA8bP@
z(9A;(*MiK_!oUnR`<WK=A!gb1H0?3lF$bkkv-Vx^H`1(eGum><%p!uaRiex`L_*`R
zSqQytqs{K#K`F+}NY_5rZ1)0`n$4`5;eL;qjKbJX=3gy`q_g?vC>V4xAD2kpn`gE_
z#LawZDI9e-PniupZ}Vzejro`#_z52Rn%DmfOh0qGbx;T}ziUp<U!b{`_Gp96Ys|q7
zG2gWxGW*Pr(5bHd=KQCqJ76BL7VaN3A4#vRaP#+m1a^e^$a%07Y5vZ~s5@kS_+uy>
zHlIV2v?J!@O`sQTe(nok#+ZBez<iwfna{vHYA)=8NW6LQM1UC+%qNTiO*3CZZ|ijP
zSClxLVeT;perK9H(cqS4{w?LMWSdvdhh&cVH{Bq4=6}$Wo^QUKHVcc)^;4jC%6v1e
zXG+ZPQVTDce@|)Mm(3HbAX#hv8669}VxC`)(pB^5%|NL$nlG9FZoPRFy>@P!che-i
z*?cf<px!b6lXhiV%wH-2(`s(L0u8-yewG5j9p(dXLh^z6pd^@oXdbr*B9F}NC}7rY
z{^$eLJvKi%2$$)J`Em+gyfEMJ8%U2iZwkqm=6}5hlvn1)s&nwP*IY(Zx7X%M3wZIy
z9D@&TUGv}Rk@2^PTM80j;qU<Zffg5gL4qva{I_3aQQL&N5Q~6(=<Ts+t%mtf3(Nhm
zyVt^o2lPIR8N&g#-=en|dIu~P(p_@UqKZ~9VHSF0DrmTc+gyl7STs=<@F9zeHi$-9
zoF4#k*y0Dub~$2^No%}li|<My8DmjHV@0fmNj=C>3#JC05N~mo0tg8fjug~7W^qXe
z<_QbS|DmCY78_|obkbt;zc8O<G5t%BWQ#Zt+W$$hIQ<TasTRS*(TX&SVmix{Zn2a;
zj+0@rkkWs%ETZE;yev1K0`azt{2r1%mVxiXrx43=4zL?$xp^G5#d0yF!ADr?Xay5#
zIi0>U6lFQm6^<UZTt>U1M=bNJVIkVGYAuK7FUC?C4fC;<M=3q@q$NZ1u}n+PZ6H~e
zqoSdaZTW^?7&(^jz6+QOmI?}UR$4Bh8Do{@YYHS>wLD2<W1S^?6>isChEm!`gJlOz
zy{=j23lO<(SxGOE8<sZ?!o!=EW%nrl)oA(WaG1DdnRf-9-()#-GQ7BL>Gcmpn=O|v
zfctkW`{~xZYdM-ibFG%b4-jdyT$&G<cFUm@1;1z6O&fDhEYG9><*8-q4b(le?4SdE
z&n<7ffx-*RU2{<Cv3yLqD=#gb=`l3EvaF$aRIg=35)@xs=6nS18_S6la_F;MN!O>}
z(w6QyC-w3HP;^$;{Q(gd^$;3VUDf84?&zj2rSaNb{q1;o;h}!~H%gxB_P-(NrLNRM
z-CI4P9tu8cuN7eWs<Y;zfBlT=zsq6XUtK}zIRWbS-B1iv*M)%@q`paA8myl99Cab;
z6;WXBQ5)iMDfX(D{x>gD8~=jHe)S+q^E#kD)Ch7=eU0|n!qlzx=$UZ!yRT4+P}^F-
zV5IuV9hg6)R?~LbVYTt!izpsZN7C7_Xtkvm+8d+3SBA=1^~%|(i&H=S7>Y;LOKAr(
zUR`t)CXT5GO+{mlt6$T4^@Q4c209^8eTR0hPO2M^0wqaZ_1_4scKH%sq^N&849ryZ
zBicAkQ(OHFk#zMjBPF0`sBhguo3hl0x*?ja*3wCc9QCjN0yI~xqU7{Eb=U})&sUFF
zgHnO|CcSM7)k`SR{;c|+r$8%LpZ*>S=hO-G&58=OUpg=^tFQV(q*i^364|b(zh4gK
zRrP~xfYqsEgDI<_Uada`yAA5=^kTiHF3y6+bu|{rxLMUB1fbni+tU)WQN1n#%v)+#
z3N$sTf7}hU+iEw;F=|%tr(B&DHNPIryXrCjqGhdW1AQR6P2J)Kg?6<iowmED9z%o6
zef8b|dj2}p!ng3^f!dVv<{zp(ra+@p{gEx0UFx|5!F;6N><*1?b;LC|^HkkC3TV&N
zCo53*T-{0Ugcs^%7eIQ{ZEg^GseVQ?##ibI?r3PQS{VxkXRCe(FkP%R>_c;1txg2d
z{*Rkg(cfs3hgAYiK0K{HxrvgO6+<&AZ>zjN=$^F-bwZu5)p{D*{j9>@1JmDX5p53!
zSpAd+yMb1R>HJ8L)s$F}U@LJhEG1aSn4=NLt!w4LOtfB|2fZZg09!bdVjcW1EEv<Q
z-@Jvx8P<)o;>)r=Fb0<Ltovx=w$3^=2l{ucyFN!<i?zv7l<rzT_!*^E>r6@)X|t{!
z0)y?=`82vbwl1ON)D!DpMnm$2^#a<gcxi2<?cZ0{QDz{$)`64*_S)L35njA8THBjJ
zzt4JC61e@=HnU*&t@W5BpgC!r>3(+BBrSzO7flSMSh#9}W<$YGGdL93{+b07028jc
zNXZxxnywHu`;f+(_Q0bwf3-s7uqJjgN=GzyLm?TX`TH~K1kL>#C?so)+hSoiSMw|x
zBv13@_b`~RS^ptq&S;j<!r-hXeGlE;n%#Gye@>&NiD!kzWdg`~O#>ZUyP)x+Ez3%c
zxEstWP1YLNt=8=L5#*xA;|Z8G8jI6t(k0DH3h3U@d_<}0H#JX;G+k-b4A}rnw=}n$
zq0yun?T^xJ&4erPqFJ+?Qef_AUJn3i(S%Xv>s?L3YqY6VQ`U-7n?~jV58E}I7V7sj
z!x%8{YX(u|qC<1F0eTNK@n56#P;-Gko7bs%N*&atc{7vtUms}_%)sr|$f)-oYpNHa
zO;0o%8{yhhO#?+PpJ{%Z2bkxY5E@NiXlAX2hdr8<T8O;VEWU`kSDKYqA=#^W&ljcF
znzwl{@kTR%_Tc(7U6e%Z#4n}5yEFgsD|CqqpZk*be_Z(?gCXk1x79#qFMs_!u=nxf
z=K%WvpEC|<2l*PxtBK$%t)UpnR~!NJ5P$kR_#4H0?}Yb<`8gL+I>LMIgkCg%JC3e4
zf1Uy$v3w(?iN*2e)6q{y`JHqqIi5d*gczedf#2Ez?lJxjO(&1@Z8uRm!SAI6hD82d
z+5|hvKcZ+(5<l1rCX#tYHY8JcRtD@;KAMB~Y5Z6Xyiey{H=vZkTQ~zHldqVL?#kkY
z>+mU?FQsW@4!<=6lDYiW_rNsf@s6n|=JQJ^udRR|O}SBp{Gch&FXHbwLZg`9cLSiO
z_?L84tAu|`U!^+Dr%)ull%GNKsxtlot;5dnc@+LR%g-jsa=wkC-RJluni5p-d9;st
zp1<`RO}fC(+k;Z2k$*M-l~w$->(Hp?WwcXuk#}{6Ob!1(8r&}Nm2|}AGG9^%$y)v)
zJ+N2!yhfP6%Ij&|tm8W@!K~-c%Yf3rx9)=aHD0v|<T`&W6>Yh}|4TEWoBSEtQfTDI
zMnLiwZ|tD<Ht~&RXyI-CGm6wU^NBi$-r@VdN2!H(Z-dBP-p3BEwesnfsB7aVeg%W=
z{Nxd+yT@;(%>MiQxce~J!F!~`(Fgoc3L-t^-#-pVJNbLG=<nh`u0oR@@xArv?QZ^n
zk%9(~`FOepPxz@S^z2jqn26Fd{tMdTdCrH?wEYEt@gF$T!=JAL=u1Am0+wF!`+Y!q
zc|C<;Ui0f$LGlf6`yJH#_$h^u?B{2mKzrZv<D#JMB(#nLaTXp^I;)Ei6ljEbS79yf
zShxvp|3k@L7<e8IdkCL7qvR<BP+F>&V08tc-h$P6_~av4(Zax2Xr&_ze!{tHu;ecc
zr3`=oA(%Fi1BDH)s0$L>YGEl@@JN72h%kKvJlrGfH-*2U!Z%mxKlj}$c&>qoeZsio
z(AY1$pjhPrp_`8E9~3_GMt_9~gJ={F7nacWQiL$`J6MVoX3;zQkYGW1ZBfFo#jtc(
z@Vtb!91$MO0f`pMXn#9Km`pRUSm9_mMB;>aA9!(8Sob}Btt?(xOGiZ#gje)6tYgBe
zhY&q3Or^Ej3E=^4o+k=9)UzjrNm_W3B<P0&G+F4SjinT!pMw0U!k?WGNfV}ALS4EL
zI|(h!5K^3AFjJ_fAty^1BS0iu2s;Rc93e&mG3E+=loOICbWjiF3!jI>e1S090i{CW
zx6h$bBpjk|8WanL)gY&Y)61YxBABj%<Z0pTN9d<g;nWIPDibF5!tNQN_6163g+F&g
zp<I~l0flqI2R0xT!afQao)@BMkM4p|xEY1MtQ0oTsevlN@)$s?g-sNfyC_UQ4zwDf
z;}}Ypgah>4Ulv;D1GHAC7z)>}2thqCe^q!zd&+gfmQ5h_Ld6+?H3-G@61pZ7m%!3>
z;p7<9-4M3Y*VAtb!)R*TC>U?j%jlMnO9>`TLN$d!ZwrMAR5lBCGf}!D=qV+uMJNe{
z{#}8ijf+-c9?kmOgsl|#Y!~7V0Q8>FUVys$Lh@+nbqKSbf%!lfc@tm{g?qFH?-aJv
zft4<y?*>}^NO)$XSbw*0W*hFS$HIlhXxbBDI0Z1D3L2UrJQG}w0p__dwh`oouzfT9
z?GgT>FZ{d|M$vlem9T;Ct6ssB-U+XT`I8~}MsWQd%s%0;9SrshHeMiah0oHV=OivN
z2a2<}QcmNai}*4JTvsus5PrLfE94M$7d!kQ<01M+qRvxHqFJ<;=-&!#Z?T_lYag+m
zg}Sdeh|<0ML~at=<S%wpN>zZkRs-{a;!sMF2om4WOf^_^wg6^`c;tO3>=74b(EfL*
zm``Diz2b+|`TN8!idyd%C%gbTAdcP-O9w?o0~Eu=UG%|%a50=#-4Wt=U(`j4Hz_!B
zQrt_2jgmxD3cMtXZl6IUMI20V;#ASR1<W*2PtQoYSWT<#4DtRPTK{E=186##C7$03
zPqW3|BKVdgHd9_&uGka{yLn<H<)Gw?VP^qaAWklZqlM!4PoPjFE~e;Wv1muB+o!}I
zU7%1RR!P7-EzY8(_ENEOFG^+N+RG@N5u<AXc2<0crqsrA@pIakKPO(MmwkoUG8v`w
zV%xhgaX}1v1++@h{(n%c677BlOtrY19)OFYr4t;j5r26Ba!Fjg0<K*a2S%b)E2=1y
z^NQ%W9+s|(u3rGGPMn_w=z7tYR*?;2FRkCM8O6&q)x0it#(;Z6+<Y3%zA1LdAlfMQ
zQ@+(LF@}X`lh{GqAGgJa^fWh%_b76BN1RW$M~gUX8C<(7MpEi`tC;%<MB2mw6mD)8
zmsFu;_rwR^0qnl0q4!LOIE6wM4@BcvJy3ioUe>^1r}&yOCc4D-cvL<T^Rhv@#nypn
z(_^vVAY6MQZYx3Qsd&^6cAtr7slCs|vP_g-hy#{Gq(_`Z`F}6PBOk*2D{&1aOZ1AL
zQO@>j@$0X^d?Qv4f=HjZ#+VP<FHRl-OK-*60660$?fwN#bCxu@D7i>iCG?D|^ob)Z
zxk+s_D|DCUM5E*(eN7Lnr<6f!e=mt|feCLZuM`SCQX9P?d?hIZ#7}CVn7O|+nf4?D
zq`5TQ2TJFL8$p94J9@zdOMdhLfDmca5}@sonrQnYRGRq;%)L@w2z=Tn^^i~drF<<)
z2c!cFA#zaqcPttaCjB@Etq+$xS$G&Bh0+@)Qd*b_gNLL|>mU*({rEjZ4okiioj4+`
z{hFS?XelxP4#!CGF7P5&T1xA%ILVXJ2#-o86yuDS_^qf*kUm@k{bSNMcCdR~n&<^`
zLh8+eWTNCokIG5uS|GrZq&5MiWa-FFSW1!HXe%{Ux<3)lq)8dGppY(|v}5r6Wk?(7
zdB~K$qU_i#Y2s*fX||M80%nf%q!Nm`(ocav%ahtqpiTMGKAM;mNQ3FUUMM+IuNO(N
z$xtYk_S1UzloUvDkP_(+%4$6=WzGY$RBGFYQknFejzgW1_9?(Lo|QiS6rkl&ZXlX=
zPP#+b6_ON-UOz8A!4`@9g0#F9b(PXO8i1;#;Ab#cEwxZ)&PC}&B_wO4(5I-oBuOt&
zx-8j`gZWzNtGOUoB$uVIa8)|<DfH^3uW5c!FNw4!Z7@nDbY-qdDw?ibmp*?9r*23i
zKZNK_Y1$U(H%jkN&)$-bO@xUiNyk9(w)EtE_|z=@-2#O>l0`RATBP)?Xxd%rKqE}F
zO1o*5(<T{$A<{10iiU-IQWb@L?@O!)NQY$Xp<KHMlB^jr52a#SN_0xw%3!`rdY?k*
zkEHQkD0NHTK`1?zHq8R)6Y1tK7<?*iq6PLdsg%yiJ(tE&PQVLkX)@gIktWxp^imq<
zg3>E#7#+Lmm1feR%Gc7<cYyLnT5tRSGJVpS4<XYpg{GjPZzcUg$T(?#W8tE+Hk^kE
z7wsw?O0HVF4%E46XMYKwLbZOhUfruLrzGTk+E*W;Zol@U_n~k=J9P%?4r(vH014Nc
z1wkP~>ktQ#NbM{NTprSH8A#(_l=jO@Fn?Iv`Zr2PwBb7FM{D;}hEI(4XGi!QtL>)^
z);R4iW>7q;?WTopymtC1kOXZT1)q;;Svm`FT)S)-Bu{83Tj4S#YS&Zf?xc3k2QZ(c
zeM>tPDcYVNp^&Owv7Sz=r)lp}8cn)3PX|jG+6tOBWNL#bV4I~?+=oxu+AS2!&C#aW
zKr&Z*isCPM+U)ni%-8-!OP2!ew85}js9pFc>WZ|1V^LSE?Ni_`Ii+1mYr7KdXYCL<
zt<5B6sdh~u<-eC{|5U@o8Lc~I<(}0JwuAX{Z8a^~&S|GO0;WPcf`YN<wHBRd%muCA
zM374DtbYMorBzRZ`D$$snZKx=OR?M<tvVFsl6LT6FfVJrp#;`i?Kf8;c}2T33goJG
z#txV@)@kc+!9>0GC(3hZ&<4kWT+^PKiOTERY-;@t?LyiVyr~VE1fLqU6_k5@OIsHL
z&?fEO!Spz2cP9e0S$kwGe7d9E^c6^p_Pvh)c30ct1ZP^cpVK<5P5T}N+1s^^X<*(n
zYUfh$>%KNF6=)sWpVYAQK>NddFdu5&rh;^8yBmPkr8UrM@R4?*1@ybM7X^^V+7U(Y
z@QL>Qy>RWR_QE`L-ZSlN4|LFTZ7C&2ywI+m4#^&EmH{5V)NV9`-B;SJG-K@58n<i*
z=xgmaHjsIvoi+q$ecF#VL9}06{0#bUwb?ZganjvA1P`5czYRypMVCaY4Og9<BCT$^
z2Tss)*X2+I!b6uh3eI@yHqg!OrQ1L`(B3*T3ds5B))1zzu7$S6{B(Xs%DeH`Eu?MF
z0G*Zw^FUn-z5If7u~m=>*5#zZwGiFPl@QsZn?RxaP~9K29k5sT3uT_{)3uX_`*m~c
zK@R9veg=aFbphj{9;Vw&U%3v~-L?Ztgl^+-kVxH!wg5Y%i+p8-MwHH@8ybgo-ZgOM
zi0(T}Fr#$~vY;5Fn|lVOSlu4l5sK4IoQ2X+-RVsz#q0i}?*Js|2GGmom`?vYn8$Ue
z;{kR;x08ZbiMoGiEqhXDxeop&q1g~g)(sj7=oDS%D$0LJ)fKAIvuU~~cYv0z8}bV(
zGjy$;a3)jd_!IQAbf3}|RJLx%HZXH^ljxj4uI?FaS?B4NQ^Yf0x3&^`1-dJA9~bHd
zQ7Tc9ZUyav6zfuHm+F+RDHhBUT~Y)Loz}fQO!Ln(y3}+O&+7asW&NB^IRyqQbiRw=
z{(0TH0w`Y4T|W)KD|ODJP*<gErrWYwmqRnZi#qr15UJ5cQX=XlT{_+Cmv!~DnP02>
z*$s79blWLLa#gosI{dBE`B03cUbk#9P>c<_SI@w`ru!}%*Z#WBnogtK(6xO5nMR!j
zeVOQ%F0mh$nsn>?(E8iDnAs>b>xy!KeMfi2128SRN$1gsySh!37T&5`GZL6>x^I2p
zOuH_ELFu0En>t9|*EP|;Qitx!XsACh>OB8O@uAK)4Wv_-|1(6pbagbRex&PGK&D%_
zh!*`%boXfQ_^GapCV<a$&QC#}>u%A__Cl9M@!B3;XAS&)sr!vC%qyJ<WjXfhYF$uz
ztt&hT^KW#^DDc^*`yb7c`gO*CZh-q%_ugBGI_cvU1I=0g9nD`|^z&OmT=m12!3#Hi
zRwXpt^;;-0&_n<2=P>B0H!FsSmwqy>SH1Pi#{<PjKP?bUU;UbU=nFr6#y%+c>tE4x
zAE1A58FhjBNA>9DAbp#W&I<(Ve|!XPh~9$c8GG~rAHc;>Jx|lvz51_dk8dABEHJ-c
z|G^BHIH3QB5_Jyh?VTVJrqBNtBwYVXH`F8a{dBWM>Xl!?#36kn1vjGfhhKmk){me}
ziX-~hGf;}whm9w{WAqN+pct!<q5Q%){S<1`QT=f_MC0`nS#(K){(d;@9@C%y1f}D8
zk7|$;`VyM$B<fpsqiHAgu?mnR=%FrIFUQa$PtmWZS$nGfN-Rj4zJ-?3>3ZiW@IFHy
z_6f~DGxdRV20csPNEtra`X%&`<ml~9;8U*t1-&8i^nrWP!hHSMEMOPtqoZNBQ2zzR
zgo^YFH0a=Befz&)p3+Cr9KJ+fcovpU>+eLO^GfvtTwtM0KgS8=jQ-P1)ScBEwhX}Y
zSFTsl%<-K5I2~cC(EoW9cF*h00^r33{kMfMU#Y+NElO4T;X5Ewt@lZRrHgtUEtzWc
z%WR==N#7FzXD;jOb^yCpzl}bpaYesO4ue<qAFP6UoxZ^tlJ$C@Z&25uKS){A#%p?e
z%Avllx2%NB4gCj`QM#%BiVht$>fLES`j&nMMOvHm8TL@Tt-mxCrDnbQ14!P{>pH<~
z(R+`Eqj&X32g7`;{`&jqgva`sdGP6pzLR47PxXr?!kK6K6YD^p>oe$0`ogG>pu<i*
z`pz-1^inUQ_1`P~)OwV9^)uU1_gcR>4wl~NXJ^3SKK(sfmG$c*V*zv0W~LI7Nj6{8
zeVk&$j6@^SY@V5*F5Sj!AH2x0d6oxerp>4TFtcp7(!wvtri><Hc{av*N#N$&?AZXB
zLYv<lfmUSmBkgb&+cYZairVDTAX8#fxE^SyZN8)AmQtGt+EFUA*+uvB8JnXNTP?S_
zL(`3OHigM>rotvd1(6Fj*%P2pX|tUUhg8{2eh18In?;l~anUBhNFnqZo7zd}p-VO~
zd8oW>V`2}OTAL4OrhCOk6A#g=HY^?UtFuws!0&pSWZExju<<_(<~5s(w3fbZ^C5+u
zZrJ!z&)&4D`3H??v{_6?h;G?jq<MOiP4QwdZ`-Iu_|$5%-H)EXdp76kP}zN(=T;Ey
zurbSr`3E*J6!L#)GoGf#oi-{7m$J*|Rsa+p*;Fop<YOE8V4yv*S?&q-r#2%dfjqN`
zcm?KjoA@+{ys&xF3x9iT{zu<`duemRg)Xm+e<z&jwK<YPU+a8rbCt4M-q?&j2NQiZ
zTPQ)I-^PK5%v+m=&jI6P5V}B|4R>u(=VJKV1D0G3hHs(gX6Rf6pWF@XV~BVd`u;-G
zJPo~Hq0Y<j9_`q98@dEE!pBf@2^M?}At7M;86<438Rh<lXY<hB0K*)b5d|8aP_ko?
zVc2GXh8R*POLC8)m_E)CYN({GhP?(4O5NIL5NOkOzhRRPL=G6NDO7UM(0>J%!VF7R
z05jb1J&(EwL-bPUMH(hi=<kqW(Z{e5We7=tg7L6nIgRN@3?I?m5^Y#=9oVskf;jY7
zoMG7_wD+iiqYb=x!<&WZk_5x@<8bY`K|=a~JkfAA36@S8Tr7Z{Y}mO1B*l<R`&p?5
zzbx2IGd!Y4CEegeOYsbYRV^%J8EUD!vW<p9+EC6hh?c0#H5~GW7kP$+UjdqL*bo30
z3k<~{1E$cxhoV$um_8Kx#fGo0f_cjDj}4e5hAN6qoHnrE0<6@~7Yawq3{D5ZJY(2R
zpCCJHD53kJ+|YRvdglyYYk*Q=F!od6<$}SkAEeSyOFM5>hD;W|RU3RL)Opd+MYmp!
z!62X$E*a+3f!S+FO8}au?X?QPc-!uz7^jczIA_%Dw=JO6LYVCf3d={@GQXiMhiyCF
zgL;hZ+|MDIU^|_9?U-$`u@<7oZKu=n=7jA?1uP}n9;XivoV4wq2``dt*U`9}Y&&fk
z^{nk_%3Dpf&2dF{rP)rTL+k0b(>KCyhV4I;YL;pHdJHhLZOwjyUXE=(y--iv9%_TZ
zQrln6p?A@C-EM%@*v@FARGCY*4a;HovhA9$AX95ww;aw~vCW->rd_pd>O-l{_A!l(
z^|nq4&~LC!SPs2wwr!{2%yrvWH&MD_JA^(tbJKR#2<SE1Zfb?zE!!c{U^dxyzXQG7
zwqJe?pPFq`C?<5rwz^)4=kKoV6-!{Z+OEh4nya1XeYDBVZX!(r-0d9xf})3==Qe;w
z*lnEy#Ynq_$5A?DH<{-0QFgH}A$izt*QY2QvAgy@)MM-_?}Hg@cY?-|qjsN`043Qj
zO%Dqxc7>18+*CW{%Ha7+vkTve>y&QyR0c0H?8?uelxeqOK0M8`iw%UOV!K3IJe;zN
zbVXf>-Bvr03wFW9K&!M<{Qy#BmqXi+)pjds8@<NvCT+Q0w(GQnWUbu-I$?3kZtxy>
z*km`U2$;9++J1$IvDt3%a#(7y8}t)k?%E;ZftQ%w)kR>wu-ixHMtkg5T}PW<+U@xh
z*XNa8Ep3Fow%bAX`Ww3v3NQ58{b`9(zum_F(%tQ+QUJu+zN#FOF80y0;DxLGG;ct=
z+21<?rn|jx3q9juwC|wJbuWAEkEryvFKqzvvH$H~G{)Edhr#gM&wk}~X!zSNn-5C?
z_8pT^3bgN_X<e{=)B&i6*r(;7Zjb#?%EJt`54{4tz4qA2!F$Sn)F?>qxBto>?LA<x
zScSSU`%PN3EZp9>VIDLh?Z1vj<stiJp8@8m{k;E{H}+3yhJMU`2Hg<H?d=AEB-$U<
zp`l6k-_Xi9**+~BA}RJQlzWkCzh?~$rrA4M0yEwIqrG5e*k8(phne<{lnR(-pPvho
zZNFnBz;f(28P}p0a_uKsgPU)^Iv-Az*;|XKJYzqs2Ks01C)>gOa(fSYcb~H#TMlN0
z{cO4~&f^#Zn3eW7e*#LCeO4sus_nljL0z4F7v-4M+i%zh=qCGVl+SV7{@sCat=WDY
ztzhoh&u^mVuf^W%Qy9E!kAn?(4($6Vleo=({RZf_+qYA?(LMWr1nA$l|6?wg9roiW
ziQ$3$`0J2-XkX|6FM<Z{e#F8Q{tf+LE36E2S%JSJszc$ME3=WF4malPaS(TAd>vhU
zW^K6<nx4$aT_}1ny$7J|%~aBu<HNYqMet?*m?s;c2xsQe)IO6ji-D(E%uI>_WHY%l
z;9CxpK{rh<Gw}dQdCXW!-O6XC?}SJJbFmzxkh#o2uZXc&0*8y41@wA9#h4aR{!Ixp
zn!W^Zn(6h1ekt=AZTXckU(+tz1x8#wV1S~XsiW7m8|!}?`tIxu%D44kg%@CYvhO-U
z!HZR7qvXwQrSv-=w)_ej>dO}H0Mm~xpwkro?D`Z)2C%#7vzdXckA(uye-PV5gJdwv
zhr^2yHVPpoMHKrG+aQW7>|U(C6&_qZ^|u$-Jdzop2<CpC3G98`jCbL0IG3n_!4$6U
z+W(z2oRD7uW0Mxv!N}($0wMZEZyYRq>6-}yi@Yf{=I8!aDE)3yYJ}*vB)S<Lw|w;9
zMVNOEP4s1s(U<SCnW2}_nWvd)ga7Z+3abX9x}Q5lr-|QkJ5=z?NhYHkFG!YZ3Fu&%
z`M)R~G1);!ZK6%)Qle&z$>)>`7i%*1C#c_6r(A|eyITH;?02cBOh)B%^{`5azENNK
z93@w)3Gc#PAFGcjB`w&hnxc9Ktn#*_6lEn_4auWcb0`}m-b(u}yhyMrqV4NrRz`}7
zAGi93rn@JsR<1^?60IUBj(yT<1sy$1vWoBpNw%61O!>zdR{Uy+=3A9`f}FNG^)=8c
ztPZV*r!`hN3!#6_YRemdUbo6k1k4SqvI<Dvv|9QO%r{#7v=pSvYUON5KC<emK&jj6
zQ#w=k*lL3hN>8kwpM=4uR-Pl!h-X$Iv<d&*YTP^Y{(oU*=?AnPD_d&XD=S3=%=cPZ
z{Rx@ZR);9F?TuAB1+x3Bj5JN|w;FvP3U96I1_Rs4dM8cqovmwWpWnrLBPBq2T95w(
zC|=efbSb>8AGkoz$9h)}P<*XN4nQf`diZ@1V~F*XU(wJ#*6V9<xk9a5Pr&Y8Ytts6
z#acJe2ZIx=yCzbXT0gr8jZ|xWAIxW1=lzKm=38HQ0Lh!y`j1i9Xl*3WChP5yAh)e;
zR)MrwkKcr5-?e^Z2Scx{`#NyzIBELnD6OAS)A$Vx`fD<;fgIF?*}>9b&DqKDJ6>~_
zc0!Xhg%6;gshRW-EEQ-%7Qm-cO_2-q&ucO%P41G$>_bR4Xe#_sYSJvHxMQ29h{D;O
znwh`A?la9UUpVtx(-uSh#LqYn;>{c1q1`DTK9Hg)zI+|UYy9{&JWFza{`VAU1n`bD
ziUsnkSEAWLeCTDAg85BHArit@-GMWE_!Qc22<4?l)a~V~-iO{kUZ9rk=d-GzcYv49
zgBi<Dz(bErpb2GAILc2pQcg@f|KJY#GJ&5<F@|G&doy5;^9gkR{scc(f@mWDiazRg
zl24%-OcMW84~1ktm|~JCd_2XMQu%$f0#D<;C{rt)pZf|1Gx@c9AeqI7--2E?f3Oq^
zIlPg!sB?LRmk~6NSJMES&;Lnl_5%JiHMEc~oeG#DK7>}5#eC3eD4yaw--l!gzj`k$
zo#yK*!7SykPy%lm|4%Twq=sJ-g(lVW%{u^ni{Ib^g;xIBAb9wYccG-Jr~H#;V7}%{
zzLx!jyPN;*3Pk&O)yL59=l2w&@-4rHmdQ>+X&$isgrTMo@fXg<06RdqHXb5@!pxHZ
z4H8BVLS3-Xc@-VBN0_k&K7|T5{PtU&Wo(Q?o1uS1cut8y(L%yulwyQ6{ZNb*I;Vpf
zCp>F_#!+EF6b!}-4G&OC5XQWP<Z)s3VU$h?HpgKiQF!z*y5yuV?kFrJ2|ko8lq~#y
zACf7;!VMs)LOKPa^Mr$Rls8}SG~R)JkuZNCxWz)JJ;-_C<o^J3LD+o>=Bot#WGGe(
z^C@YeUWn^O3mb$_DCzaOa4Z3KZwONpVd<{$i2-1(!fKkvwFv_$Zr?7LbwcExuyGHX
zbYGZ9PkM*&9wik&5K`ml`aTp6(Ky{Hc>WEIF5$icmL3VWC&7zufsaAyv0&B;yHAAK
zy8-i5`1%QadM=Dv422iMHVwMFN9g$irI*6u??GM(7DLd&Ug7s{IQm-9QLgSA;WNrh
z=o7li0M;+W9i#Q_Tfvv6#7<)0A}BhGnMWYwB6?5;y{mYh?ov0g`4sB>#Y$TF2Z$@)
z!nHtgAZ-o@iOS7D3lZH{(DfD9Qff=6IGApzy`noUQ=`QYih#w47fB>m^g4r5ocMX?
z0K8w1iud;cG+vxL1&RrxhOX!_F}fa#$Hn24!E{0_4nkd`xH|#lq}WyqXOhIG7Pyuy
zinQ8I5i9YwMkd4KD2Sws2R;O5hUnXdQl{8VV``STk?OL=uK$A6;*Mp|Gv<mi8VB=4
zR|;n4i?=J$-38)8?7bp|VbBqHQ6x%~R8lPdL09yY=sOc0mWX8^fO%THJP-;OMa4mw
zuMyvFMBQa^$qDGyiqGByvre2OLZn_C)r(T6s5ye}>Joc~fxI?~)lR5<BR;zY^L=8%
z0+{F*=PUs8t@thl#GIrW9-cZ&)wBX|k=D1uuB+5dp=UQ~%fB$_E?LtA*F)<04t1W=
zx?uqGlA4AA#ar_5g1V375Q&nXw2dY{{?aHVm;sV8dI=N*rS}#9J4m`T3YEc9>serj
zNNu!1xknmFVWv<i%K>fLE8U=;*(c2lMQOh@&;_6eq&>9IJ1AZL7R)dylnzmZO9v?f
zB0&lZ1M`^FNhbr3OLae@bV737g)5RMg&AoWJt;{aLO)qLUI4o(Qt@-NDOJ+aA~a1J
zPz5j2rL~lNnj!U8gB%`x>3g&=ZS={1;Y|AI4``3s>x2BoFwro^N(mFqV_ua2rSD@8
zieC1AY#$G1$oSuW0XZ<<jNVKK$Cp{t7Et(jha{k7jK9+Y^JU}9bdWhS{*!MZQ#t-G
zdeYm+ubB$8gil9YGJ~i1w@yvB<ez)*0)2fW?U($u)(l?!{oOtM-4;Rfvh6bi0q;;w
zDQ8a1tZ{&KW`@&Z*o9FXhJX)a^c@5kUnZE+4*i)hnt<+Q#(oKmeasU2F2^Az@DNa<
zm_<F*a>hVoZUQr*A8kFxeANiO<IL^l=&BP;&v<~QGtYdeIZP?t8U;+#DwGPD;q;If
zG2hoiubA0NITRI4wvo1}&og-q0KLE*xd{`M%onFoS;s8KY!=_!7;B0SXkh9*Vd5I&
z?gM5sGm|!R?lA9t4bs9mo`L#Z=DQEk!d7OlJ22ar^R!pj&TPDkx_eA?AMD;|&L^Pm
zF%$L-7M?Jv`zXKvDKnj7J<phZw3GInvDTo}$5c;-MnCi6EOgLYCg}vcaAM!55!jjC
zMp=t4>}S`3?aB_KbVE0G4WYQRZ%(1)!RFCw6rY8Ngoqcb`2o=0tfMCy=)+b=gZQ!@
zGwJ>3$NJHj;LrMYz~KNkd<;k++qwrNh~)>u!(jF<?Zbz#8k!yKVF&R*3uQM_Uh-ac
zlma6A*maaRu%8{g7Ig>Mj72bUkiGvU91UY%Qf6T|`_CTu6v2K%hsPpW%U=55Kn}6D
zK7is;_OJq?@$9$~IFrm?p!Z1%n|Tr%sqCqz5J_WK&`HNUR_p*XpWQ_vi~@GRbYK^<
zFIU5E5nDo${IhJ*3e=Uep9etl99u;Zt_t>}El@wtel`!TU10A~%8Id)El&pa4YvLv
z6mPPo6rOBk-Iqe~7W?}*P;6$u?ttQ5cGVZqXl2uVpx?&M_z<mVXLl^5>&v!Hg!lK^
z0y;U^!PZ-%?g86$33X1K+yM%n+%z5{0i1RaEbQfMzXCJD$hGvtZVWf|SC}}#Js%Ek
zBIi$c@JY_$J&+`BKIIuEbK7alFohd(2JJ22teaq>kQ?6%gGF5aJ8-R-n?WJ9Q`|-R
zK4=MNVGZ-897kh88MmL}5@)#mxgck`+q4~6&Kc9z0s9;`|2p)qaOKtT;s!Tv5Mb_b
z3j$GhpR3vgW;f?n4vikplVWiFob?hYc*w>C!Fx~H9h!}J$xLUW<Slz!0TVv5Xj+;3
z%Hk-{<tO{%8<Y;n)Re(>P*z9pjWC(Nu^TYqvVA{;M9AzSU^i0cH3u?>WaYm>@vtnO
z-VjG*3AN~pXxS>ti;j^^e*zLK3#2T(IN5YHy7Z{bXDjs5WC?2cn=4zj9^{nl^;htz
zT&6e-^=jE`x@E7*PSZVpQ}#3aUwlE<-wW;o*|%npc_?$c28~YHr3WZ=$u`ph>yd2u
zCN#TSwrKzyeJu0Z2!$uIumv#KFUy_>FW$;hUP97I{+gEg&T<FJRCU2e5aF7uyyYkq
z-0+{J0@GbS@+eyGiT?nLo<A>nH;riCa_bnN`N;nr1mY|2P(i~_{%jZO{N-yYEE6FA
zld{D2%T3)NazH+w&et52_Z^0bFu51`8!qqmrLL5FID$mV2hn6EN}g!}$;0w3>wt1Z
zzR(Q~jFuN7R)Oz3$+Nb=n^^f<I%ymyFQi@AB>4|lAd@VAmnJ+Z@}*y(E>%864zx5J
z-3LjRZ=xV}hTJ0sb~ELFQ37|i{1mOTa^&C85;9l5n>Lv8<nFg&H(#FcHF~B%UgQn1
zLix>=U>b|?U)cbrT%P<I2G7asDbu_{{+z<>=jGuZAQ$9gR)AE>eQ0t~C2wwkNVR;*
zN?gN>a>aP4Uy`dR#&TIcZ3s-%%Ab_L?JM#<-C$moyBDHVC!dl7^?G^fH}JPXZc95Y
z*NpP1>ww)R&lN!0<u_>4?4JA&nq=RX56wYiI^+YLQTIT;Mg{Cnxe4ia$)^TG@{#;$
zJVd(XK~Z2nmY3B)@`>D>zM}M2UhNE~lfuOXjyfwmDaPue=<x%zt76zT)VV2)d7nbx
zU6B|B7d;j44uq(e;&b}UiML|lRFr%as>@LHRaB1!sGs8Nzftm6ETu(mnBs2*V8Rt6
zY2px}=y(W`NQDDEhKCg8wEYsLkkhO1up-qN%p(dnKX@3UU<&{ps~Bx$P>fS--w5+Z
z6&(v;H(s%lcIgrnGw!3Gk12))L-Dx6I}akK6*uPM!j>u)(QC3&5mXHCZz-mAg4v{4
zO|y|c#f&Skn_$vQDUf9*=6x`K#^jFxFmIZSr~<Req`)8Q9VV|0^!z<Gc~0B5FHN3h
z0PU5@778?Zn{KLxhL5R+w!TA6zdi}`QKk_)A(Cp!^rI6BO#Aa;x6Je}%67bIYF`US
z@jZxeV0tQ7|AM+uWi(9?qLr^q(4-XQQ3|1FDi=x+sZbsnM(1nJE6<LDqOYo+4j=}o
z9&AM^P!&Kau0g6#I-wY%nl%az?@=A0MCiS$n{?~#Q_X(?x5HEoJ0KaZGPi?BglcsM
zL=LH{D4jb>HOUqRV^nPc@HbYKZ-8E$Dv|b%6I9JA%5OZO%Ki<NNvheOpoOWb<^FIu
zUA1%(urpM@ZbDs_YUTl$$X1C@QJ16gqL6m3Y7IT&7gX&AkSbMm4LYGlr8h@it!jBX
zOk7oY(xkIqb=C+kuBl|R0CrO)UIMdOb-N29Mi;YI+V*ub+i?y>53_iRx_g;jSr2Cd
z%nomXXpmViWzmM3eN216`^<8lpl1)7HPT=lVK(tGO$YH$9PNm|i<Z(((GSBYjc>6x
z9aLVDF&4jnETu@(Pd~hc?$53t;`h?nSjsQ^1s{0Ar?<+&U}^baT6nLx%;4|J#k6_(
zYmpuPuJRrZwcmnL;l^q+bNv0?mNKxmmOG%e+dQe~w)cbp!NJN4za2}a0dvP=nr!Xr
zr(DV14`skH-r9)Y&dfvl!jcQ~`8N8#tShs}08M{p3#AJLFje&W4`fV6qZGtchk+bq
z#(V^kFy^1{fF90#iJ+@InOW=rud<o`dq68@yiTK0<%}QAf-f>+sLB6zOVCjKh+<D%
zf$78S?Nh)z!oHxmd^DSCJOE=cY(pJ9O<<d7DszmT-37oT_LBzKOlI#CqLjjZZ;rZ5
zb|;5Y7Q1@}NH#mm6C{UyybkJx?1~^L6tTX;VWOCIbj9^4W4-@|`7>-)8r09S<1aw+
z0=vi^W-HkRW=3dSVn@>bahaWV8m`x}&2$G|VXs<4<{F#y6-w9Hp?gre!A_<8x!Y_F
zgA(RNH0!v-I*ovO3;W@JvtV}R8Q8tg`clxdgPlNmm5*4DQ(!)0_k=*<IqQ-H^%rcD
z1Lb$TW*-iLT_^4Uz1f~BP5jW0&s8nhg!=Ek>Sy-SJN7M8K)vI{j-nHd&g^%Twd2Aj
zya!!Z_Dm+Mxv^6cK-^hBbJTgT#gzKz$!5~()r+0DAL`z0Vl?V}*gt3|#+Nnzb^~aB
zY!;=>__K3pfDB+4b;DpFJIxL<2idyk@HUKXNk?5cJ2)S8@$8oSuyl;Is8jtvFU7UA
z4*ubTA0fMVGCjOY@SekczmtKzpEeN2&jx3>u=H*-5Pqq91kN(!4%!@F?nw!%E8gsY
z!piHz;nA<9v{AL{L=`}PJ4E~Ut9O?}Va;iZfBs%E77%M6x<c#k-BV#~vyry2xBJu3
z=-@pZd^e^V=NGV-F*yi452k!RwTZbp1@?lN0~aA4%)BzH;ZX?loaUtA%xOw_j$qna
z;Bq8$xfm`)G5h`jGn)B~%)~KYT7e`mp3lKN!T3*udJ@A>a^*$lJ$mKVFgcWZafw+}
z151~g*_8NP%XqCrseyU*In)~&Us_Y$VTK(rf_5+?IaEGp)cH{CWvp*PrjPmV1E9TS
z>L&x+nf-PMV4_%Oe=xJyTUa;!zn4yx0Y7q?%8#Iv$87o&ZsjwF-T<$F`B;y-LT2uG
zkRrxifmRhW??nOV6tkb!*cFV?_yX|fnG<KBe}M_1o1>DMO&eTQ%qC)1GxZHXyU6rV
z7@&r!q@X|xQ%upRyNrAuO0CTNF0`YI`God+9x)Eo$1j=n^tOM+ENcRo3wt3OUbwRR
zXfE%@uBXE!{%oAl5j23!TLQa*Z0}i!9$-ttKn}98Q_#6#?8XL=81@TFiil-dT8hN6
zV`*k{lpV~%ZZi7^y&h9oZ%RwcWpkRr%wz9m!%{w5bPDPPYymAE&aiejz&y(iqE%rz
zTeXJ9-*apO8N9@vSOx6MZ2Vwo)Uuc8m3M{BrG-r+`&A|CZn1XpsB2;y=uW-OcDzAd
zGuuxqp$-<CzqIJ_(xUDmtEGd|oovQJkS=yTExjJG`-VWhn;lP|#(K==?x5%Y3EQ$C
zPCaFhltA$r+f1va=WON}puJ${?|^GP?9eti`jY+hFEs5H8$h$^UUq8@O0U^4$}WAw
zZdn0^K2{%tIzO(60-IsncA91#;conmwj^+u$eC0wbT7ymZo;p0zWf^JO)-&9&SML>
z&a!tm0yI)4w?%&?%RZj~XRwH%q@;_orL*DwE!p|)Kzk|+-3szrrp)}mS3nKE&;h0E
z@;)Vr$z3U5<~IKCKs3EYe*Ykl+T?#a0KP+BdKosm<UbqN1LKK&f<Hui<ax{Bbgz8O
z`zXDYf2ahSo1$gH05lB$1cov!mQ>Rn@DqCjl}pPg)U(W!=G7}gvrxNs%in15y6al}
z-IC@CxUHM7;rBM32+Zx1Cqm1KF{iu}XJ&~rop1DJE>qsL593289733r{{Vjv^Ebu7
z!kOILC`B;RGStN~MRF*{G43=3pJawDg!4&E3vJydGyhNwC7W5(4QFx~kw(f~=2$4y
z^BB{9sOK|pX+yGr`M?*x6f!B<^nJG?#=`+J#f<DNbu}~UEJz7+I~U|M6MY<trHuCy
zV3#rOUqSy2!&1WKS*DvJdF70HEhNt|k0`)g!F)Oe<UI2a19E|Bq_A%#)A=vDpo%d&
z2(W6#iUN5TnFXhzXRKi!Tm$zKlW&RQWo8N`US4O4L(z3Nn6U5AUpJZW^{~{)jHg-h
zEoMkNyl7(P#zUl?Ir0v$?=c%zL*zb_9s+f|&?q|ifH}M#&<~k2TA*|?SenpF;yS$~
zQrLf20xZkOuAvu64m;*LVDi|F6kac2cLYQ96x&T}lv37l1sZdfT}3PY3bv>Qik0kA
z3Xoi6O&&m`mQ7v-h3o82SBSK*Pdwn76IZiN2`>JLN@{BaYqu37lI_if>LK<JfQ)#j
zdQ+hAFzY!TrjM|*=(K4x`_uz^G3<^D@Gh3saj+T3c3y?CqwI?ruoBO1TMNAewvaNa
zj<EyiMSPrnO7rv+><V*8CbIi(LGmPfJ_(XZY$r_zlUddphEmvZl)QxR+f;5xWg2^#
zE`K(g_!CN}*p?{3l&}jZ<XgeEI->48JMbEuxxikz4UtMVW*YkVDqHdo%-69SDPz2z
zjZQ<UfxS`+z1ysEDjM3%R?wM&J8TgJb6VIwN07VhdJ4(68rgq7LuDHqy#b2t>=zf{
z)ID~@PjK-*`w?Bg4mO!$#ShqjR6u*kjx2{{C;Kslzq{D<9MnBxKZpnEVQpx7`;xUk
z4u4;<Gxow#FZ-Gnb+6f-Pr-b{W|c#-k9|A^q@OhghoI7fs~&{@^5nMAOEZugLNBi%
zE|_A)2ROYRA_uvIW|WR_DHPj@<_@ia!g20)1bjNd9jAG7IyakkUNX3;ZICSBKJo@B
z<c3pN@C;{DkG7oUCQ<TJIahrEk~Lh2(ExghySN>`UFHHW!>L+MqBrRkE~p-LSGjlT
zsBj&(G#Ga4IV=Ov!QA(hNqLR?-UyNFocnAzbAy{mvBH~NeFsP*SK|$Giz}d%l_qZY
z4XEGdRP<Okb0fEdd6!E}q5Yp$u9y~;ZJeqU=G!@kFVWr(?gdSd9&jt)p!AUIqVcDb
zYlwq>7kBSI$YaiIF~}3{!)3sJ%B38EWFPm+4b66v?V_AmXIUqu{kh2UNyJsA-GVwd
zS>L;mbeBb)r18f~R;z|3Z<+60bd8_vR0o{#m&H-`Zh&kn-GPC!TzYbXWae8?cT8ra
z<nDA?Y5^1qWP>TZP$s)csb7_{v@|du$SQZx^_73o4lleEi>YV)6upn39-z2Y1d)A;
zmyHAP{Dmoor-K`=P`bfVgyJxTB_kDzlOTr_E878jSn)`J!_kU@X>c@F;b#ueql!Y7
zoKa+Wfq7h!X9ds`igC0mOH}Bap?6XdUWR5TEBa1>q$rj)f}|?KcmChZTDY`=`hQ6=
zEzy6hHG##S=9<IO&t5;n`=!T*!s}lOrbA{~+Bf*S=4Ce!ejh_$|M^4l4}Pyzw?k&r
zvQHtuc?RWPY#BsXYU|AX_`5CcF50v`#}$8f%<hN08*`cNW_PBDrU3qo@$2Q(C5)d1
zU;-I^EJzS@?hd>UW}^FXmmFluX&en>_R|v{&e+i#DS|oDO5Mc#)DGwr=I=sS%VrGj
z04ro((+s+lIll>{f~lbO*F|RcXmrz6W@a{gyuo}v7o|Ix|I)VN1Lj~mxGxwx>H;S=
za4ZZ4vyQa8c!a&{_5bIVB-w)z#O!bdZZPu>g~SgsiH%SVW2)&?b2yVY4kUu<`4l!|
znbG4R8OK!9@N<$;?gDxe^CJ@HF<cIz`Ctmme7wKA1^>_5(00g_GS##NTE=XDi1t)6
zKhqdd#rW8QS;riv&{{onb~5yvnAQ_0-DciU7F08{Ed?&$VP-7=$_aK9C2c0MZ|~7f
zz=q5~Ta(!LD<PT8&Zd<}3OkX$BbCbTr}JuQ>=NTHH0A>P?+Iu$v3>N-wkWQZHdGID
zZ&su32)CsgCZf4>9PGw$<s;FUSndj)1Bv5)7z(|k+*G=E<GH09A(Fr?{|qfW#yxU^
zGsn4aX#XWp_UBO41<7X6A~9H|qk%O<_VG3&8oEa|!4LYOGWQHPwO8i&Be3_$M(2RJ
zU$%`hln=-%8^Js%+eyjsVX_|<!fv>1NDrFku1KCotyeT{gxw@Xwhc<@iWM~6W+`^i
zq0St|j@M{JfucSYB1MXgv?e;GNZ3w!mZud*H4uHFm~a51ekMO2g{4H32rZc9CjB`m
zoj3XPUwCoVWZ;zloAcdg9~dCr$-Yd7myg-oG=4v4bN0X?%u^|_<jFbJ(a4W~LOG?Z
zPAflw9+@*o!tc4>bl&4zqmeQo=j~eu?fGem=#&K^TT$`9$vXJEup<u2Kku6l(4{>u
zQTxlUw5zx5&-?hje19DHE25^uftBkPLTlaoqw)LCWZKQ&Y_bIYZ#fVRnVk!1*12o`
zBxt!aA0v?q>%u8C9(fv>CYru^F>n1qycy*W&`M-B6+$6{*+dz8c}xs#dYxisQE=rf
zbBq#!Dw!4wkju>8T)5uAw0#MGZ!wNHQEFubQ<NSuqrN~(pEJc}(CcH0)Tnc1H;;s#
zH#_Cm|K=#@f8oq}_&#HwfS#E739Tr%%1qJj9;SoRcV99;4g<_<=I%s*zF}gMp#PS6
zOs967*m2*0>B>H$jVU*_u>we*?6RG(<i)ONg2)~=EE&L|>=_kGCt1(mP%32KZyE64
zr7>bE6|*0#1~%Cr7}wZ8Zv*i<+ef*QH`q^pg4Rtob`0v;*#EC~s}G8*isJk3+kGr7
z3oi*PGeZqSWxrT<VV9UJMYBv4L@`L*g~c{-7g=yED{L~btfmj)lvb!SDu#u9`LvMC
z!jBxa1j<q|LD3LDNKw*hrr%|prv9yQXWyQ8&i$R=Irq-)+xyvYKai(c&KPLjtYts)
zI?H|=*uB7x@Zs_WCh-}PKiC_Ofc_dw;IpnTi_cw$cuo9T0ri{W`4ZG|g&0|h2o=?0
zZpw|va&$ZIUtJP51;KP#IK;cTeL@Z&s$CHpSD<QFg-kvx(=V)dz=&$Q2C5yu7%^XA
z%k1ENl{N8xZ8e+o72IpsTYRiUY#2AzvR1ynw3>P6LtDel&+vKBwd`OIpdYZ*B!sVL
zr8anMV!7`j=g-)g>xlF@d$kMNc2>{-C7M`zKO*g78~Z@Bn;i(EjnIsIE$Dl8HUh|B
zSS|mnJ;Dl(fb1yS;)U@To5IKR?d&&xa^g6a3VA>DSGI%ivOK}ow;+56TXY*lCtFpB
zs{PJ}xDfslo3s<+GHc`Ajy`tcT?D+s?0j{vpSAmeyvB|_g{oa=eJ7#4AkN{NSC)#6
z!vR?>uHlQn_2Qv3NaicCf$#JGNpxNXS;cYDbq1Jo;uJor>k}7FN8z91g8hKLsBWx9
zGNhjPAV}-gvnNAqQfKS|@}Ro=6w>Zg`_}_`RXyldur1e2<`1oE&HJaJt<to;ft=QA
ze&+j(>ol%~Fup6L@@bOyrHy=^xwb-b^V#~<(z<JCnvK%Wd<m>x+IlC%CaITCmwY5e
z^R4+GOU;L&ZIOP=Miz?H>xRQNsqrOb@ug%P0*6Lvr~#=pNt;e1;0~#u9~J&udYhkJ
z{YG-#0rzjE<+s4ES^9)8U+$GEb~V9czcl<|<b6Q$<RF=YQp<DjZ;{rnx$(4{R9%Y}
ze<+6!#wU-B1Loni68s;D&4gu2-OI?~(I)-_o?5XIuIW=RqIB9z2jDe*=|{*n;~6{%
zHJMr0Q1=;Yc$QggEO;trrY%QWv*P%|cJ|h#fX*&!0mWl|yhoq&;XF|1Hl0H0ob*A+
zG0z(UqPY>>u(-ncNk{kKXMxOro}b|=s5=P;59X24Y3YiGWnS-U+&{66FFkvU^guot
zZNq)hZG_U|?9uNb$N8x>DDV}pgvsxi1k#dEJJC!FR<<LR(%xR&2b4J2gI`R;{o>R7
zT+#Ewi8NGXnec}L96JOZ=0Q|Az@rjXky_e+R&d(KJ55;uPierE?<y@0nkIMxMP>dH
zQ<>jT_JqeU-|zRCg8tH?K#42g1B}m5<_VMqXi|@m`agW*sHaB=n#MbGGiTuas5N1H
zx!W^&LRy~1XfYct|FY$l6qnEQ`U1H$=e&>>8}$0D2^?oM8xzb4R<kX^YO$H^xn+KT
zaUj?2^_h&un)AY_n@c}zy3vS0H{Pz&`39fg=P`I(Zm-Gf%P%f3@ThKT{f6oOj&3wk
z@PcsnO|I}i<0;mQLSrWd8bSuqQ^7DDjc#Q{%Ar=4^faCHhey$clbTT4+{#7}JIsbC
zY3X80;J*L%Wy6=!T|TdB!%h*G8ka`duv6MRIy_^>_`F$JGcx!G<yGpUtK2=3;_eB#
z+DD=3;)p7LhgR`-g!Zq9dMGn3Z{`D2veIG_Z03PimhwU{Y;FdXA6LsXZo3ph;|lfh
zO3Zg*8)nmzonoA_d!%k(8ZCJzJd7S+r3qDfygJse2<~wG9_rj1mP)rYsH2qOWAxhl
zXlWh0l_rc5qv+firln!6Oh;9(gbb$01v*JtR;a&wvDRjB7%YxN3pJe3&!VI8vR08h
z^jowsjzoveZuVI14ohNwp({B#*<(qvnk^Q0K|xZY$6nRdt;ZFibahAC9~2hRT?RSG
zRF|p7AWvo5%hUxa944DlPG@l%sx(5KMr}}qY>G8OyiVm@?4f2Z&QP=&P&t$e&46yE
z&j-{nk}Mz`r=yvW0I#zEe3AMfm>fY96HuBQK{Z^Ci=-|{VJq3JJnTrSv<|3kTs412
zqY?+G%M-ydmzufwo}z6KuagIYsdTi(223_-?6B^jEG`z&ItZ35(-k|y+#W>}lK@&m
z)k!eRgQ<(Fo5_|8_4c7unLJS11{Ky=2dvr{TIhiFZEEJKc{mMrf-2@7Ds;+Y*d1DW
z(<zV8v|kcb=V+T#9x3djV@~;AO=O2&l}JCt%TY8mMV8rw4l<_5ql6Wdm4f2BSXs4h
Gp!hGbMGC6`

diff --git a/Debug/Libs/sta-core/src/devices/stm32/bus/subdir.mk b/Debug/Libs/sta-core/src/devices/stm32/bus/subdir.mk
index 94ddc8e..851532b 100644
--- a/Debug/Libs/sta-core/src/devices/stm32/bus/subdir.mk
+++ b/Debug/Libs/sta-core/src/devices/stm32/bus/subdir.mk
@@ -22,7 +22,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Libs/sta-core/src/devices/stm32/bus/%.o Libs/sta-core/src/devices/stm32/bus/%.su Libs/sta-core/src/devices/stm32/bus/%.cyclo: ../Libs/sta-core/src/devices/stm32/bus/%.cpp Libs/sta-core/src/devices/stm32/bus/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Libs-2f-sta-2d-core-2f-src-2f-devices-2f-stm32-2f-bus
 
diff --git a/Debug/Libs/sta-core/src/devices/stm32/bus/uart.d b/Debug/Libs/sta-core/src/devices/stm32/bus/uart.d
index 996c85a..22211fb 100644
--- a/Debug/Libs/sta-core/src/devices/stm32/bus/uart.d
+++ b/Debug/Libs/sta-core/src/devices/stm32/bus/uart.d
@@ -1,8 +1,8 @@
 Libs/sta-core/src/devices/stm32/bus/uart.o: \
  ../Libs/sta-core/src/devices/stm32/bus/uart.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/bus/uart.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/bus/uart.hpp \
  ../Core/Inc/sta/config.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
  ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
  ../Core/Inc/stm32f4xx_hal_conf.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
@@ -30,14 +30,14 @@ Libs/sta-core/src/devices/stm32/bus/uart.o: \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/uart/uart.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/uart/settings.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/bus/uart.hpp:
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/uart/uart.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/uart/settings.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/bus/uart.hpp:
 ../Core/Inc/sta/config.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
 ../Core/Inc/main.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
 ../Core/Inc/stm32f4xx_hal_conf.h:
@@ -66,8 +66,8 @@ C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/uart/uart.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/interface.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/uart/settings.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/uart/uart.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/interface.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/uart/settings.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp:
diff --git a/Debug/Libs/sta-core/src/devices/stm32/bus/uart.o b/Debug/Libs/sta-core/src/devices/stm32/bus/uart.o
index 1d2adf3a446ae67b0a5eee63b2090e4d61ac552c..7071de6cfdb8ba006c892e186eceb4fa71077684 100644
GIT binary patch
delta 134273
zcmZU*2UrzX)HXVE&Y3gy^de|PQEajI*p0pS-eMACizP93lN?19#YRz4QHlbhAPOiJ
zP!O?;(nJv{_5v0x*x|nG<oo`6|L5k3vuCw;t-WVvm$mod#EYI^%X<3OX8(?Jf30yu
zwpBCk=Ug=mcT!{&=KuarV6`r*WQJY0lVMbis(lYB+ii!MQ8jkyk9&a?=1dkDcE~Z2
zQMGrOL@X8e$WP6%^D4mV;5y&Q;yaZK47+|k&!`5wcoIv)J?H{MugebbhPrNZ^7ykq
zsu;H26pm5NaET(8!0oSq<?MZ6&2mk0viR`^uqui*jB0I7XGF7GLcGq6B4QUj(K4z~
zHwuM)`y5g4twk}gZ;nDg(T$w5gDWLQb)ptIWgV6f6{EW3M()^JSpuWFQj7esHKzhJ
z&(+EAJO;)^)t&rhwE_CrwGYcM9vW`eyoC(A$f_`^r`5-UC208A?g%frx|&g2%`FMZ
zZJx}iT`XO2FVBGvyJ#54sB2q>k+4&@=@O&%u>J}{x1OZ2z)?4`EGFrp&$w@4T~ESD
z66Snh81)a9-6S*wT-MfgFq^fEda$)4NxKde81)F-V7i}uK+9-sE@`A`+bA;{yX$qj
zF93q3hU*==um2l#zN`M2?mLeI-`({M-9P(BVl;KCSJHj?Y?je9aFqyiQ4JNNX;|G(
z_y2qYzqOl#8iK9gmS;3=YEcWYd?D_;)N=BtwO1HT*V;~g>5nkz`yc=0dy&!f`;WhT
zqngnSujOp$AqB7<QJWgt#bpA!Ly{SbnqkDABbbS7JkS}7XS9Zy<h<92!+soLXC^xd
z!7|8&W2QLo6-x_$!Nu^phRpoTrl^4RU4?2#Km%cjBk~V5^G!uaE{yAZcZI1`xxoQD
z@}-*5W>up=>lp=Y2y68HMP$xERNZr!nh9lf6dzMPy&=zpu?7+dcs(`IA6TaTh@Cv6
zJ;<uJ61PFE5j<n1cad-K>i_|b$}n7`dUVYUmwATeCbh&H#|;mt5?mbf+i^@olC2O$
zTtEDvFf7A*cIFwrty+PgMhl_kGlRqw;$F4UCNe@Rh28{4wR4Mx5!yNljq1r&xbEO2
z1l79tEF*Mw5{fF{re%a~PQs|_s+Sp|hm)|XlDt_5BlLDsE~>k=6h;`}B)(I*_U9O3
zu#>2*+SMOkM>q)&)tDwAMmvdys@bg(!bB(0gkkHAQZvF-RU1U=tiLeh=xm9p$)R2k
zFCb#hI1?QM_uvnFWZY+7Vbq-Ck6w5YxFZ?pei(MyIfOb-^$Y+yGOM<Dn#4>Me2i~E
zsN%8_`^H*y&#0<(gRjkQ)G8X)OixIB-KZVgsC;iAK!3MJP;0CDbuT1aYkdImgQ{mU
z)Ns4IsAZVWs{RhB?HKE%x~tl?;u&F=ljx=T`~a2T?IilCPF+D;20MvCs_fZ-3w091
zRMz((_PWu#G)iS!3Y%~@dNSiw^?C)AN(~)02GxmDHG}gS--*o~9XZAmzE!hZ%8b~;
z*=mexRV|JY+c^o1s!3Z&{`V<*&CxL8|2{=LD|`h`HKQuzcMyG?gjKbutHg-?orDX+
zPWfBShy&Ht;m6^82;!pGKe5bp(A=SxJg)8Da!hUR(k+Sc;7Z*Y#-01g&M<Yj;TbBX
zE_c10V?w!oXL+WCVNaX~n70}o45K3i_AZBDea%!$T`?HdrrUX@m$=Oc{r?`27+8ny
z=>a)lywja(tWh1f4a1;17a*#wa{V5}9(U^OJX9@Tg9vfo2BN;I|0L8utj<-aHB>FK
zYZ-B$Q>}?AcOuV-5l*#cs_>Sm^8Q+-fNr7s=^1Pe)X9WR8&%!AAflbb4+iIZAs%w4
z_oA~ZIv_-GWvu}x6?fJpp+HeskKMBbhSN|-We|)UzQ6BApcDLV)HuAQ)|TkgnQFxW
zvi=A6!HrbRV2q7Jp)&#hv_z=K(rBsQdY@rl2Taq~VW$Lm>+3bUR){goAl<o)@z2QA
zgLWGJW&9s28UYw(58eURDzyl>qjwXXCa(O;t^ur}j<6zG!?3k^*MP=`y5jF0q1S-_
zu2H~PLtDqwYFfr<646S`2>f%S8@>A`4HGv+WauT2lNcr$|FnM~HZ9eR(UZ|a9m5bS
z3$nZaD_1XfR)FM#Dl|@cIb>h|kK94>rX)8R#kua<0NGgE;r*kAF;#OrhXKwD@~#M>
z7ydatGOE=;FuB^PF%?Gk22`_iw|J)cl+6qi2{pxNQ!(Zr?LP)$2sUb|0xR)vEg`HY
zcP*AK<r#A)`>HTBqsqvU1{?B!#Eh-w!q@0uhw&#jNKC7RGc@RH_?`hN#_x>1Hmevp
z7pi;#E{56xrAF5l4!w$LDBJ)8gEXUdHi_X(Ajh<FGSMY4YLco;aA6F;1hg^z%Weut
zFx6!z1l%$;@aQj~b4T+v#J@VR$!ca1OpMM}FxH$-_f78w)G^m-M6wZ}Rep1%DBL%w
zMUPtL_q)_VB{B_~uEXe{@|)J?Xuw=^{TlzT_Co3C6PBs%L2tdv?+@uyK&-jm|4;7P
zm_DBW<S)(jbpK!bsDRp*dXxSy4*VPH|L6ZNrtNY(j#+xtFAx`JB`8qifG!x0#O6Q$
zZ-rQ~&;L|N0)O1^;4|$e!eo3xn5Cws`#BlY3(1B!@J*`~JEu($Fh8+W<Ep(Z#gxX)
zg|pX1N2spp>eNvOsH$_;X5N^f)ZjV$-hj$#)$7G#1Xb6m`JaNQ;iS@*m?|kMPTRDv
z$fyN3&fehPfG#dA*}Q=HE-vhifORgll(waq!KnAM^|)HO0SPYi*zkZluI<^o0TWzX
z^xZ!LGmHPC(r7q+^&Et0GjXb>1&Bps=2Vkb;sI;)oOVTR%r(?niF2D*3tsE%{tM%Z
zrZrb9At1}O`*&ZwRH$QHPWU%igPV5$!K&r<oN8@A)9N)@-++PD-P!zrxz$^-I|4$h
z*OnLDz${Ab(w%dA7jU)ucaE|~T8w5bLugFf3lAJ~4g)gBoP0o>Ucakw?J!8j^&m_9
zPG}5{S?<B%%6_G5-76BVTYU-V)dO@=%-U)Su6}m9Hb^1ciRpwk0FwZYiRwZ81;^+<
z$niHB#8#+rt<I9b9i2VLqzppu&xB)O<QRVp)f`js196_4>3&NVg_RdT(BmHw0?*NX
zRytk#;u&$woK_;Pk3H!=yOeZ_dl165dSrVbku<Fd4vHc~OLfX}ry4YLC9`)N)%CY+
z<i68&QWbj>=Yd4Q9o$6_?lnj=?LFzZ3?xpMS#+QHoLnwhO8T)z;#71X>9lj?tIJTj
ze!zHx9`K0DfnxnMa@=?g#pw5yV!Rbk0eL0SRr8KGX|ZJHg4rF%RKtvuW5VuISpWKw
z?bSDQ-*ztr)WliKoC9P#*V*i;Z3(%`pLBZsO$ePL>FQfeW*i*Tzl<X7{(%f?bMy#q
zwkKzmT8h2MO47C8$Yn>&V>qV#GQoK!lC+LH@qa*{$}!#yNqb`^$}t;<lXT=4s&|4f
z=_H>ae4o37Jh27wmmLL;gK^ZLCf%bU&=ofcqGUcnl(nF1&GmHMnMOLJ^2oT%KtSEl
zKXXiGBuU#$C0oBiblqJ>n%$fa#RD@qj`?mJg)(6*RpTcsNmVJtZ}^(Ra-`KKpub`W
z=t?lf)#wTd#%Rcy>k^Wt2h;VoK%9qZbe~j>;QlTm{ZGB<5p=}B!!gqj6K7CEYQ>!W
zP95iCo$qXR_W<HN3!w_s2&W(#IP|1?Bae&&w^9(Lr>P!;{VCENZRx6Yel}<CleATP
zCukal804(SglwwcteyndZ=CaO=uHR{sd<@S4%78)0A0U*N79o{{t#!NPuv^?=RTg?
z{Beh3uT`7sx0ok`Y0i2y7l~iBhunXyPj1p5lgqq9vhq7c2%B9<YT89%MdZ@8)pK&z
z&e=E2Y)m!oTc0%J6uSS0<t)d%xyaM|-?TP4cw0(vg9FLz<{WZA_8F;$W>K@JPA8X(
zIl8a!toMz6q_br>0sVS|?wbYEHRT5iG3F>;ue~O;$|yp<afT35onOR+@2S;$tyI(d
z-`-iLIa^4zZ$7DB^Cs0r`-n4b5`ngFPn_~GB;B=#g7^?b?R2La@wL4OPUuQ)ki?U;
zVmeuw29o}H=O<eBh60N3;&j}TuFJ`<gDL1jKud1Y^`by7drqf%Cype}?x$on`2{sy
zVgfmv^$S5ScuAUx80I<V&{)!R#iWH}GCmW(5EC{8idhXl?4ES5(G$XLA8P5&7YYA$
z8QnW7oSo&7Y%>1gA;nu0=?J`^964@tgIub9rE4-KD(G&#$;@LoxiNGi{Z+pZC&rzw
z^Ous998A}R&q=?~jrf-@lKUd(qijEu+$T4u)|%!>r$QM>tkmsPvvC{9{goTUnRSmi
zlC!H}RKzi1Oyrm$FX?_u50ak0O%9e%rR#;iD6A*WAl_ajm(S`Fe&H3;%y>x1i`tV;
z>k{H;c5o08_6tQCEK_anV=B!tPZP;_v4O6QJV>V{W~`|3Ez&feBFzg}kYn6?O3yoU
zG-;N4Q&>VG>6gzWo#sxR7W+tNaU+uU8BY~>?nJ0~CDHpoS)y3_)h4AiI*L@Ukh7rY
zbWIsbaJlQKeva3qQ|x>LvTfw@g)^WPgGguQ5W3F)mk@6Dp}JQ6Mpl*n#NR%UY_|sy
z=If=zIp(9K_rFmU0VQ4}*0=>^7P^#FZ{8&1J!`2RF?x!+d>z%k04X(mv{?S)I}WAL
zFODOZ&6DW<&vk^>_b}lkPa>SoSUch2I=`1Ox9EPwO|sn|4=V@LbRmK2Q_0!rK6Lf7
zkkY6)y7~{JtJ@25@EM6MH1$_<U!yK*j{28?8aY40!I%PJWa~hV?<}WU#;C|Pz@M7^
z0@4#4v%%Rve)pMdpWPu$M|2TE%)ycmW0#gf8G4<>N6wLPR1)#Ws_8ygqWh-ZsFuaQ
z6R1}_wN2P+(hvWIbh2lX&Wr>KA}xmQxm41xKY%m~|E18Ezobw$%_gfxj+G>sf}9Md
z8$C!haxxiv?<0=;ae`Qaq$V8nC%*d`y7uTn{6yyfGkY(=%~?Y@9dxAmXOz<o(hc}h
zX3+h`A#|<nNw!QF@h7e)gqO(<GB}I84*G2smNm>TvxxJ!J>5TQror{kLjtZ5c`U9y
z?@?H5Vv&Dh&VQ3|P3wUb2eV}y)!urOnsiDg>DQh}nDuzlpXYoV62Gdz|FaGSy6p=E
zp>HKPz$*Tp%&gAt_Mivd5BQPH=J%xb_~$!<-iSq)mI?QwdMxQdkL+kYx;Ev={j%z0
z6-0|4Mww05my0Px9-pO_`LK`z^`5E4b?kj|?~OE*mRW?^6u$qzlSp;)pY%ND-X;fm
z&bjQ+>eO5f(U)nN1^uWt<<5uo{AYsbiHVw)nThoU-V(gqTE>dmu$Eaol3co+BC9><
zq_xa%PpRI=MpBI<oU??3k%YYNS5(ZwL?Y*h{`@I5JEC_!B2K(<1%c?hA4I(jg%)TS
zyVDHG{O>sA2k;O%*Cq$hI`#3=Gu-!1y`FuR<9^iK+X!j&^Uerz%(COSAKMwLMQ&Ux
z>I=sEAW6kdSWB<$ue(l2`2J_eG#dR8M(@CqnMh!Ajyv;Vu$nFHj{rBazht4<&PEAP
z3uG5qp|^uQ`W>j9to;f!cd<*p0WXN%vkM{ZVc#}Dq`_>@pYeb~*w8~T4`q*RhT|}H
z$8%`zW&fUvQ1`J_1@!)fvm2^`8^Ja}@`H<H`-P*}&mN)iF^Y{r(w#fNu2=}{gY3mX
z7(}zz65%3-o%#;ghuD|Yy~nacQviCH4LT3z5w@-ys5mx_2FiH$k673xu)mogJIa<t
z1Ns=7`hn)(iR^F}aF4SY)RmuLFJu7iB)f&ue5csvU*SH9{pC5_C$lH7gL#?_qJH=c
zyZkjkQ`pr;prx{{sKYwTI$l9Djhzz$_vhF)M^I$3Z^>^q>pC2oIjn~l+Ax<Ll)<C@
zZ?gS4G)*4+p$w7cvvJFSeTV($5)2F2FzWyAvg=!+xW`8HMyo$yPc;C{BX;Zw7(8K*
z(5Um2o!=VFGIo3f>|U^yZBU6<>;Mxyy=KRDLQLgsjor|E!)|B|*;}^f_i*cY$Ikr>
z@;%#b34|5wgN1PafweaR^CP=@Fzi3Gq7lq5Y^DeoU)lO^p;^UNO@;eas%jm;^i&lG
zA;Jx++QX5Vp!c)>olw}c;l|;~&bviZrunwF!2F}{CdBgRD|)jRq<3>*bx!JaM)ikE
z^KIwRqAfm_<Jz(<`XH{=%;9j>`V_sqq3mnTf9P7xxFc}Kb*_PLUE4DiSp4n|$lnl@
zX4*VdOq;P7AiUvccoWuq0!Q4fAjLr%?kzF$aSewKK;BWinq5b0N-uUV1`6#ucIG2g
zc|Ch<B6=|&_9rA1xDD(N1MqPMvwMSq7Q+53!TbYj{S_g9W0Pr;xkh#3CusVp+O0+~
z+f;LCLbX%%tpHSrDkTun9#+lY4CoZqgecfuRh2eJz8&K)zVMoX5LCap2wLtdRsybh
z{dM4XIpPk@k@I?>@^gh%xNc;-^+5=c?3uaHO=e>=QOWD<Bw1m!@7UzW|I-B0bWZ>p
zb1;Z#8|USrr)n|@gNwE)Wu3Im#-2n{yE*L!X&o&_{DP{r#7n|xTbW0oom$7#f{Qjk
z=b+)+7LGz3?f!X;INHy@gm(JjRw1q(xLMHbIKB?v$DW<{LpoqWA*@EUr7>o5L1*a9
zY`F@R|I@E8q)VHc!C%GpN<!t<v3nwc9l%Bokn#Nmvaa;q?`6+=pg6>~oq#$evP+TO
z)Sh6S(Vt|U;h$oi@h7p)3M8}68k}Y+YHb?ptjIZ*YT|s#QvdpJW=mpmb&W+LovY#Z
z9#Olqm58+7Co~1uz_HT<4cXK>8P}F~0$|ztAo^~u!}tT>bh(@bPPd_y!|2s!Js|pz
zqJ`Fw&0SEnkpqH|C8GyeZIB(nHJ>)deO&{M5{-VlfNR^iqwyTNWzdSUe<xbLj%-O^
z<VyB|4)Ckk84hgXah~kozk%Gr=GvgLlWn&Hq3vQLXjZV7RbxL9ePyl-ig30r208R~
ztI6&#dl@f1`nv6{Av?hiRm1!wd;A89Q*56e@S4v46p66Uv!$O==?m<<N>nA6UA_n^
zH`(-JTL0y-M@GT^F*}o%5Kq`l8$h43qo+c(f?e<q_UI6Pg2RvO{d_Rjs)}kr(_2-$
zI$+kR4o?SjyQ)664!J;8dNROvs5&A4#zm?+J%-=?s_W+<i&F7pV3(*G6$+K(su4Rh
zc>X6;*J!PHK_!hr)h?>u&||xyI!1}9TPpX_U>2%wegjOAswvsuSDj~o_E`1%7f_|D
zyWgR?DpWU?qb@7eBZFYKM!j?}3^uBTJk({AI`IiqcBnscknL2zYY0uOzxUJpH$vTW
z3Al0UoGN&VSMQt&(6ef03+&U>I!ykZkGOWdK`^TOyd0#*_&#_E>J5tcA6btPm=JM2
zR~N%quRro}-**y=mYLBM8Aqpe^{&x~xY5=KfHrwo3wq7({*L=rjsuiIY1@)AB0qdN
z3DZu-+2C}Y*Z|@mBmY7}^*RxU`#~IbpSV%YQ_!rFjI97SZC`B!KF4b|bmn{Tuw77L
zgfvOpo|ZMq+BrqgI;}l35#Z_C<y5gN+CI%8%hvuG3jKVo%04RKY%_}^KnEQ^QJ4qe
zQT^;xs3z&Jw}(eRqcjrKR^!2(|9RVE*(L2zgM2oWQgwyw<4I5}V&`Hw!x)t|8O;0a
zwp2901NP|^6kAnYv0sN?@xU{L7pUUt?b)G9pgh(tRkxuu3<jwNH%AD2RQ@so3s$u<
zBKA;KjTvBusWzR4>ONJQd8lf*s&_J?Jf@mbf+A7Xek>ejsoe7sMYc*7P~@t1(em}C
z>I`;{@e&zUg1W7GMOnH#szh4<7O3h`vanF~cQT%<qezul0M!!J3Ci2uQ{8$C>Vc~0
z5YQf~rcq+_v1*1J+&@tbOhlcYsX|u(?YSza6RK9G8r}*9FI4TYCybY{t}kS()Tdsf
zSgl?@87N-rA?WP6wQ5BVb8odA1xHcp(pF#|aHu`#>13<#mw?PsH}3?Po9ZzdP<iSL
zc_?nH%TH3PtGy^wQK0^bmf&~Qe{Dcfq+UE7=EZ8B`m6iuYC&k{2WtKxs7LD6OJMg{
zomT?CPu0eHsP;4UJQ{{e)#qvCDN{RolKYqHqm(3hrM_JoMY;MQcIde`>M?&n^__YW
zEg;{kXXJtUpw5)gq#xDsw9Ngie!?S)FY1ovsP8xRr6$m<RC_H(4OeNF+=8a3W~ncj
zYcz`o!u?v!%Kh-SPIE;M59>95I(EW-gXaDdkQ+6-@nLbBHI*h9ZqdA|grT2?%|?^>
zYkoQd_ggi``$Kb^=C>)31!`K2K(Rx!gEA38nvWl#vRhL`*}Py)_eY2#M6-zM5~kT*
z5Ap8R)XD{PgyxzbqKMQ)-=ilJrMX9G#seBRUsyzIik875Mzf>~s94RUW<WcvIfIQ2
zE>08H6^8Meo<qSrs)=igSKydtr4@cpXd=82%t=l7a)2divX8?&Su<u4s(nVYWB@Qz
zG%c|o$(_|~!CHY!(|j(aZZKWbw>hFXuX#puu8SJ^17I#`hQ5XB70sFPz`m-P)DK05
zX5DX4!Bi9nRk%#eX6zGjS(?O11e2pFsSdxn8n<%PFi+Ea0#I&gygR`lU$fveiaVMY
zl!?BpIn0A9)clq%;QK4qoNf=a5=}Q+b3V|lvjFCyrt3vGe5?tX4cQaT$(L~POmle_
zn9nt=J5*k1zR`&IQq$-UG|6kt!tQ9Ga*YSg{@!YqHv{!f6MP@C3eCbC*nQ9}I0CRw
znv07d`>gqT515Xxnz&;?`=<Fu<Hbs@Gc7Y#al2o@a5dL;EgHd#%j^s0T5e=G+R~dF
z*%W@)b3KN@&WEd_CB#N<dK+kN;`;A^i!Iy}GYVhMZ6)mdIiokI0Ith3sBGsx%tVBN
z+~~$I-|67?(d>H{SG5h;yE*F=sP5q+u+7DVaQ&~NfkU~%U!by=dqataeOxv*a0GX_
zHvC3%_UoVyaF6H1(?RYctx#jQ`<J14h?}PX^DyT_tKcKtAo@5GxN~*j;VAd&5vrTW
zIhr@YD|DPYSQF$)&WrNFr#N?7RVQ;FT@m7G?%QJ6r*KD-V4uo$qv_TyuEQx%x4H6X
zpbEIS-(h!`8)gBshzp&IqL|Al1oIvj6b1A9oEL4HJmeA$2>TJ|Nr|Q>+%d-}RP-t5
zRvp5XTB`xYD(&I<V6N77+mA@Sv^8+tgj=iKIv$|j+7?HlvR*sp399X*9Xc4;o3!gG
zU$$9$k1|$%+6%M5^w-Y51y9?wwI;$~yVjrbeLJ)*)KJ-}EjtgDAZ_#74#4cz#>&vi
z)E0~em8D&=8>+e59V$4ysXZQwM!2Ot)Daf9wFSAL?r2+6BDz2uumGBc+R-CH6=~}&
zLA)i}PEA1F({7+t&;#w*u5kEJd#MCfdaQj<Nw_CkpB<o{X%o_D8Tec~ECz;U+Uj0V
zeW5MSfT!2mBQ)xkYmeRm%scJzXE1!PefSERAGOmH5XC3$7*`m4)q0;n^xw3vkZ0hk
zv~iSPTFIw3LE*{2tB=RKnqS!xR4gA&%)|U|pWz{n@3%(8_ZQE1dIYqi{N8-j_ZWYW
zc2JJ<_OGB$@NM1T_Z0t`mfK1EUtPgG&A*@xwln<g-yuuoJt#kLmj8$5s^@r*B~VG{
z-6(~AflqD$&5L{jWjHVM3H#vp3O|B6)NA~=l`wE*@RujR;SK%_W&1PvumjM^=D7iQ
zqB;C1dJ%8(>pG*z;~zu<`!-+s0aQN!rwIlHd~sjE+~xnKsaz4i5eMP8Vt(2pgm#Y)
z^F|xq=eO4f^AVqa71U!sIuj_*_y&(*{@lS2qn*YV{0y8U;a>771EE^ZSEeC~H@tUC
z6z_RWU4&o3@Ba-dpZI%QVepwxpxo^@{yu&FmHZ!@pt4f<6GzCnRf6YjP^*RW6$sQz
zczyxFtQG1Opzs#V?O?E87^p`uK7yki)oG*f<7F6b5`0|HUR#8`NT~V>-+RH{U+A3%
zivVGNE{bi!4KKvBUD#g*`!u0sHmZG2crgdX1!4VhFfR%-lHmS|(2o+3SA}+JFf)WX
zW;nVoRMkh3DMb3Co>@XIM<1Z&2#>ep8RQCk7ooT%6w;R2ZDBY~{O<_jW?&ZxUVGub
zNSIhc4J@qc2<pBto+geDgtdhINT^>Qo*oO0PQm=C5ZMjT&xC_C#FYvU-k>gJ!j_j%
zc`2-(4!c)EaSJTNxpHCEP!w;3K}`|&J7HB<w8eX&eLpZi3b{Cv$bAxA{)WRZg1QLQ
zSD{V|pj8P&Y2mt396bV>o}w-n)M|0~9AK{zf2GD>E55jmVx4HtL?zaXn|C3Y4Pr9w
z8*UW4xFHS5Z5CCu{MsT8ng&%r@s>9ze~~!>m~CPeC6Tv_7jWE)+aaz^1hrG#K<kd(
z;;j2X+auoJ2WF_)wGt{}qI(IbeWEYr9KuD<X9zn|R8x<(Uu?D;vIFAMnvfk7L;j>R
zSd2KFW@(4So&!-F7F{|3`-o_z?;t_^c_vhkicePnJ5dZaz~ON*d@CxGC;m%)O1@Z1
zJ2iL2%K{qjuDIe2PzptE8vGWEquzp9B6gz$?*p;^MA$tP|DvhhW3kRw*g2kv1O5c|
zGx1*<4xfv$W5InPb{q?xm!d5LRJqs`nON?PxTXU3??hkP?07GtVKJzRsjpCc6o(8!
z)xL;z$^BO`I|6<y#qcY@tP%%N7JZczc@SWplJ6%#dr22+Lbk>seMg<PxAeXeI_o6Y
zH!$>(ay~(IgH%sIu}Lx>g34y;xCVjxN;x#U^OHXL!9GB$u?}`yB|SOZE`>IPL7-Iq
z8Vus4WqZI(kOVpva7-G_LNie^PDQ*Yq!|H-;-uslL!V5NG<-BHlBFd`S#W2hmr;O8
zkuny;{;c#d3ZBxWlB1x~rB<V0a9(QuBQ!5c!ga_lNqJuo(-r9p<yo#uk0ye;E)Au1
z-3_UD9SpLiRDZ~FBtHgG+?42aD3>R_arA|!+tQbIs9L`Cc|TkfNHg0*^{(^@2?efL
zl6r$Gk%ap|yDxduTJ?dni8dr3NtHB}c`W^07obliAKL7FCXLMoN~sk40<tnG1KDrx
zrL=w-D)>s$ECX1%bh-$#H`2L6obTh_Nh5K9mU}N1k3#WL`o$l`C+Qk8-`p2zwhT{S
zrKN7rtdur30CtsB_B}kUk_#w<=P7q-1(jWLj3-or<Y;;m_Q*5WLM2#M*8obWT-hH{
zgvlQHaKBF;LQ~9edH6ofczhjlXdRIIWh2hkaR+4g9-t1&5wuQ-k@bVXJS2ZpKpmF-
zXo7G=?p7O7#LK&k@RT68phe*^dCFpXzOsKO_&p)F4={DHI)-MT)+ut(?+~TRwP@Xz
zCjZy~8s}ss9n=MR;8QfkMfnYBUY4_V1M7+`)A^5Ua;?LlGGxE=pl-<DT;V)Z?r;sE
zWXmEQ6UdRPPeKeg<wa*;o+lU6%=EVW`7o$_d9|Y_3=8Cp(=fa%=V{=#NFGlK<zjik
zX&By<Cw>9*zRVtk;X}C|jx2MJWPuVPPvj(eou0}uGhzN*_NRT>Qn{H1Z}T_#`YE)_
z8m0Ln6#h!@S!lBWr3syo*s2_y2KU>PhGxoOZ&&_o3x|P9r|S^zP<rF!9k)}dKM5{^
zl%J=A+N~rtLKJ(H#o>r4Sc#!UZ-_F3f(ccY&VyZ;^2GzxUgg?-c#2RyR6`M|Xgedq
z1Ij;i_~D=u{~J)QDS@tFW+<<J#lczbx{^w7{0+sQy46f&S!)zo$}<L@vK7k;P&tZ3
z!$Gd{wi$|>N^UlaJZ0536t|Stl$I<}8rA}JPnpyWwSTDi(}|s@%HLf9{Y>fC71VPj
zJc}Ag$)JR8nezUn2EFSG<)6_1NtV<$(H=vch3;sLy8GP_vB&OA)V`kE7sOkC-E2hE
zz<oNT4O`JMfJQ0zfcL#OZG1J3e+Hc<8MK&cnotVcX1mO2+~&Vx(}!#ES4Zf#96S&R
zt$r&7X6xT5h&GM`Gho(s$p#p-`%nb;?F(Ds{)dSrxOU)90j^^-a;RLVe&3^-orlrB
zNtbq%2kq8F#<lwjdJ}*A<qI@>#M3F9o}<P<v)2;*)_@!6L1$~m72Ux7jG<%Ua_NtH
zAbYX}8)3Z3!B*fPCNg?or$H}-eYXj5hO^U;fO&u|qGuS(PSpx9$NxTj|3^^Uz{|nF
z*vKEKfa^{Ce40OO=7-T>w}nqFfXtV7P<q6VUq2dl{(Lq~KLYr~lK|YxFQcU3HvVmt
z7SDe>zpNfq1NkQ`g5SZXC!z@AN76ESH-EDmWFh=@nze=UQ=6g)<Nc@+_VRJGZjaz=
zd&3}-Pt8GS`}vIzAdBKB%!lj%-+2^@gM6)@5k)i~yAgh4_=@j=d5HhjsKWD)<$Y)e
z1an^66gt9R_JlBwZ$LS|cwR@D)dXI_DNRg(ecVwT<7eDJeG~a}3t@+OuoW&&@Q-Og
zI?1=EHNh$V@C5{u#HZvS-elg4v%HuUi+7=NhQDivN(#T>6_}1R{vCZ_=lGs2!A<9T
zJ%`SDUOODj3w&f>xVXrtokQH0_>lH!*~@&NJQ!Z(pZmbYHGU^;!DjFpJBsUk+ukt0
z!83;dmdPjJcLrP*KVmav*?j-nC~orq5@sHs!JuZh9DMTxVBh9*s29!WAGAPmho3qZ
zo(lMZl)<^nFaHjph5Q9_U&L>&1(;&K$3JM&629JV2<9HYvOiGn^WE-3<pKZCd!Rhz
z55+<Dh_6X|_K*4Ql-hj4KciL8Q=TWc&v?fa%6LELC(shEly6SEe`S1|pCEj}pQ{h*
zB_CD=_pkWp@hD#Nqdx((oZnA*`Zs(?7ew)vfA=E-eaEYh!tOoa?+F}M@Gf*7@B{Br
z2P&WW<xf$3;r$;#R>_y8LbHm`bI|7dO5ubB<SHSG#;!F&Epp*4xL!fAPDrf}nU64m
z(pVdW!EK?kQ8<|o*(RX|?PzWmj#86s5td1K+P=caRS48i=uLBEf5D4J#{l8|W0-Fh
zy3-r9O_($nRG<)(L!;{sp*O|0Q)o~IPhmpL1{8aR&c|W6Pk22B7U4n{8tNm2PShPn
z3MVGR;eKKIchHOydJhB20pWZKWCsN+CBveHr(Y0gj1Wgtn?r)O7R+OXLkpmCSU5Eb
z=0}9rm9)tbCrtK%i+CZ4X3h!1r_RthD!hyZ=rQ3}T3RFuzH~O~xZqA1jT6HDj-XBo
zL094alu)B1m`TEZnrS2pF704`T2N>vct+S)29y+GIAs)5g~GR>&I<Ws;3!R~z+ndm
zmL~HyLzpg9tw2y0ghjMFe^K~z0njc9{2I8wEDWGClvjjw>OZdvdtbo*n!r=?FGJ{G
z42Rc+ITYay;b9n<nZo2|D6$0i8PLoYTuNY`BlNUDC0B5a2j)%TYfBW4JRxEpbZ!YF
z@_~I@@S{^X`GQ9r9_1aOE}e5M5Hh!cc~|I4FH50dq_uUCVAzj9i-i&!+?NPbE}*{m
zgkR`v#(m-3WSBn?eCPznLt(=nXg(6|(GL1!;V2#Gcp`K;0nMil;qxe{J`>L7A)4m`
zOM4-uf`20j%Y^5}C|(G^&;hNN!l$;de<j?-j}o}oLd)wY$^{*M0fdE7m(>7$D}-55
z(RV_PU!nP4h@l?BQ_P}c6@g+T9rxHJMm2-KAkj?wW4lGitj;L+i2bOa3l_VLLDfRU
zrh8zI^D~rj3KM&U!(y*^gZ9AoiS{f68ZPdo<z0lB{RfIj@!e7s`^CZ-m`91z>1#Y7
z7Du5tC?>}vv}p0}E68HSo-{ff7UO~u%n@;i11IUZII%Xp^6}!2b>TNb3`_@gRJ@-6
zhsVV6%K?)p=2FWX7gy7_eL_rn1LjFF2)}XTPKiewLzX1Q(##=QOry!oX)$g&Vmc!>
zrb7%VVw;+9lq&wX44P-fDN~`DCZ^@nZp1n9+8-#=#afi)IWJD6vHF78s4kcn#X_3K
zUlJF7h2dq<Wjs`_i2l#<UR)KYP;Yxp6gL7pLky3F=5?_JZ3N#CFP0+EOmWdoM3^P6
z?v5v!Ee34`bdES81z@>i!gCt`Zi<a)*ELUkLuZd}iMBofy)DY)p_(tA4T7gTVmDvF
z6o@s~f_YcW-G@3Aic_hgMdDqWc@&GLN@$jdn!iBZ6QA5bOb^8dl!199KBn^*kHvp2
zFn=PtQgxq-!!OeJ_e|VHbF1g#Sb8r@#etOkC=(~j(0L*LKsz5V#os3b`<3_zBMbLh
zJX{?r<>EyAqz7xhbq`_pR*ax?MDIi&E$rTly=hFX5LX3(`9W;h1qL6*ORGSA68rs(
zHvB9u=nhTC7x6hIrN4?b{zaR76KlQ&TBYcRvpZN9PMrn!E2V`rA73TCiU6pm^fejG
z)si<Y(Y>U`*P*#aihc-ct#ofIP`stiG0<Em#T-Mm*GqG0jq4+&>jAw%`Ysjb8>Pg(
zXp2n_>EJPNH%qP0!(xjRN|`-hDPblI{iMb$K>ek;>!BJTouv8rcB#b)FaxEGa{%2T
zg@=RMDUFu!8SRov@S_VZNXjS7-BN0E)NGHWiANDEO<n<Jh%|c!>JloIE`@oR<oInJ
z$h}hMBDmNmjhqd%a4DbG5fM`DS!kh1DWWI*?w7{VVecsE`Y=!jq$}GH;X!FKP3xnj
zALk<M7^%@{P=}-{YOYwxK;PJ5X*3;;J0cCJ02L=Kr?cwuQuq@Dnjj5#&@|_$6kvt>
zW75t!2r*IGIsx{_rBjr!J|XR;#okG&Q!Ch?l03JAnIxSF18B13cOQ1ArPl>uo{>6U
zfM$v`iB9dLO2M>PJ1a%41!kHQLCd>yQt@4&q)Yv2@9n%~+DX~f3)0m?2<oEbUy0(9
zbOFCX;x0>*qCs7e&W?nOt5T0JxVSDw(;Ik0%6S1<ru1_(8Zk>s`U22wX~<vD%#o^l
zz*DX?nD#+#N}cEwbDqQ<fx}x;DSex_rHY=g%a>06M7tYzq@>Rf7DySx0drUSo|b}z
z(h$lO6-lLZQngt6SQG9`B=0Dw+>>r^h3vl6gbvp}kox(f5)Y+jE5LjtZ7D{5A4>~c
zLi33fyaVm@R63Ojm1ok7K9D_^o>0!DREpn4+0`;BEe3UZAw|<(@k^;-8>m;(Y${$$
zRX8_+)p#zQ!FnULs)s1vO22l3<~!-_R50I5{RhKSh18`J+<%bbX`|?))RdzCB*jt}
z{8^ei2L@lH1Jz*gRr(kJ<~PZMHYpsHQbWqcS4rB*XquI>Ke<>XFW3OeQ?5rV%GI(f
zb-G^iF%_savM;60*UAn`?0d_LDNDLe{{9jS*317!!hEBgwH5}O<V7n$ZI+)>GR#k&
zNV6+{`39{41LR(`^|0L`U)TnnKzR<%!*M(0)$~Mz<gzZn-Yx%Af?|(coQxt=K1q}K
zFxjyS4)@B5yU;)p^1EVCk@EB&K-(`jZVJB#<;~QkM9Z)6`(z{tu6_s2L-Hs}w8hHF
z^#FEQK0`~0BeJ79o$HU2C(<K{mt*4rlOT^vfa*~>_Yz=^$s2=FB+5aQ-8n9o{t5dN
z^3`)NI4PgKisF=9mp<4ed2&5~Cd&z}>8p@GKS0gS$l0X`J4LS92`Z`bq{Vmz&dMDI
zKr>A)c7#KCPOhXpQo0=G3hKOkhPH?<$S%~+U6hCYfR?!=kEHFr%W~0rxW6KQngHyp
z@(fSdU6XfHzn&q_ssi?Pxo;Ib-H_YS*OV!**@6gj<QKg`<;u0FxGA@E06I^8ebE8K
zTk_xk0_L{7g*K7%<sr$iza#(l8HNS2Lf;=!6SO)il=En)Dw1!}R%x*u?E+beoI~&9
zJ$b1J*?rl|7x6xjcTlqPq1=B8>>kNyH^AVr9C;T8Pvn)f0rFHnAt?C%p2?l*wCHm=
zhnBph@=q-wER!=21N4P#5@7gJ=5N99mHg@*n6Kq$l+`Vl|Dk#M8+kR2rf=me{D_u&
zCoiPb=X+U0d87*Y_Z`6eAip{Q*++R@cU0+<tWJc%XIYDw9NZVVxd4l=vN{gJZ}Q#}
zP?fTGbu?6!TuEp2Rx0y9z<!l7h&CiVm0|RAqczHoI&iU8(RByYTWLj)X`NCY2!r)X
zuU81vM`6Z8WrK2YJ5)9*5*@(Wr08i$zFE0%g^FW~(wdUHzRH$pxc5^YE`ncwWh*6{
z0u;Y(u-K|Z)(5ps=}mcn?Mfc~awkw(M!Ri0lxgkZcc&tr1IjL?I_*FNDLXsDV7KB<
zTgrQschtVYO4FSH3sF31<Oo%KUEw~=q1b1j5%(&C=0InkBGJquT$x7)bRv|ultPG9
zwr_#M{Yu0a$fA@v!7w<WNDJWUpwejsDif{Dp-Fg*qN5$&LrNSi<6@P{Yfw3??AU<N
zjws9803}ZOL|Yc|N`IR6CMXUqW%Q3KyW0ZvxYBAWR8J_A`vLT%GWruhPbouat0hUv
zG(ja<SsMbF)5^8RXp1w-h?77|Q65r0Bvm;{hj7m-EnfgLO|fo66z7!g8Ss>@d_N85
z=asv$Fu0&B?ttQ=^36e$txHPnatJRg{b+i1MG5YUxUVYZw5q$NBocOpGGjh8uPd(2
z;r@o=L7TvtO6misWGOD4(A?QdCY@%_QRZ(&yt&F|>bh?#$sW+mQzBkKc1!t{#=qN2
z*c|xFSDKu4K<AFK^9^(gl&OEBC{kjNA?{*je?!Phlwtc|@jy|nhWm%gzE+SuQfgH}
z_Ec$i8O&!2a|3qIm5#K&c%dBLj_6-1`3zKEDYwR=qHmP8tKjgh(z^hf@02X+1>P$e
zF0}ruP~OoAxDQIxe1!N}*+yG{UzDT&0_Lj{PG@GmDRW%lsZv=x1S(a^SUUE*Qg>+-
zuvh7tyoJnDH<!Nc)w&EiWa_2s)(z%sbk}2HuvT}FCJ)}aXVhJ-(}m*KqTG62XC39=
zd~|0!K)6Ad5(v<Zx`y<VgH5_nN?32!b?XQFExN&U^wU?jEdqi1>3Y^hE&O$S1q=do
zev_cGRkvp|ify_)TCr`{t&D|vpiZGI_6{9Ozw6kkb8&&nE?r3mJOt^yo<ha3TURg|
z<sRKvIz}6;tGf^(hUmn5ph9)wv~CU4t)ivgUR^2e5bx6sUIr>$H;Xo*B6NRD1$LzF
z&-RFLzpk8)$wldoxS=?p%crA|2Xzy_LNi+DIt9!aUDZk$9MaA22wAK{cZ2qn4(op6
z5L>+NA6EpEpvxM8;;63nW;i^q+s&haPv}n2Xn0aLT}11h(z)u;7D+n4y}(Y^oqrDO
z)4HyIfjXn>(hmkHx-;%*pj6%8(QtTH_fZ2!X}W&H5dAq_M>D8&onsg|Jg@V;gKA&U
zrPB*_QMY>tic7kYmrz{RZGQ}lE4p4BsH?gt8KBp6edfYbhOQNjo7Z)i+TyFw>DR+k
zrp|*>4_UhDy%AHku1_x*<mh@1Mv<#~`xUaAI-jG^%+uX*96_~j=~kx!=C*DSwPk_s
zhZJDn)t$?RMWHU7cGQY=8^(ZHtec0^^IVDUk9#N{=&FJd+C$w<WOBI|y3y|e_ENX#
z6x!*P&WD(<buDNZE7#R~0+ctpr?f@-R=1SSrM%PCa&f@^y{>mdSXAg->Y)}Nbmt=w
z#YdfAV;FwY)u%MfXWcVjP+xS7Xp!|**E1Z&H(fma)}m5p_zGE-E|h*nvr@mFdc9Tp
za({U8)cauzom;JsqP(h?ejg2{YxLVFx3X40B0$9V=dF*vkE*TH-)n~O*XwKCM-)E#
z%8Oub)aTIxY?HnxozdT{Z{85hE&6FQpyI2aL?67LzR53;`RkW0L7f8h<5wb>t$O#>
z2xgn!jWQ71^#UDS4b%@`48J?{&FIwCPJP$2H2&?<7g6{@`ga`xvs?d(T6T|q08Rdb
z^*!_e4bhkFLfoPH>=-mxm|mbGrhD}x=u6+HZ`}$8;rb;syNl3Y9sz?${VvM59MFGH
zhdB@GXT_ls(fZ(Ou#3^Rs|%Gw`nO|X?ugZIr2h4=eq|AgBYF?#DJK2g)2Ld!K5rnR
zNYKX(0CiN~wLe@O)Bj-uGf|&PGu7kz*R=n6LO+L&CY{vp`y0WW(l4P5LXv)i8Ge)X
zyJBE|TECFS)HC{~lnP7H=idZaszcxM5X!T9g&t*^o~eNFoc?SDsC50Hr-<piK5q-`
zFX-FQGV-E+cpH3wm-GXEgzU0D`zmU9ML+OY7+lpC(R+MNpGsq6hTey^_pa+31OxMi
zzUvSKnyK$%M@(6I3r!re^^Vh_h%`rkb_BS&`jiN8Z|Yal5tcmtBy6B^xAZ;BfOcD7
zLdOv9=wDny6b1SPbinGa-i5Xf3-!7r*cIu=oq}eue(XFjOY}=AC45hBr!%DY_0}l}
z=7F9ke-HI+3z$FB4|Jpg^ojnUbGJm_bs%(}>A%i{#dE#7D?F9z_gnyWnSMYXm@o9V
zDS`P?-<S?rztT^jpAWy**O~{aT)&-K=8gVgA5ic0ZP!4vLLW_?$Orw)){uSF2c3oA
zPx?|iT<}@{(2sWazv%z{9dUovhpa%{-}Jph0a~daG6S`*(&xsbSZVlV19P>(?-v+)
z8Oj=?7HbUS-B81|275m^^frj}{jD>E(eb18hE`8u=VSQI56le)kI_)sXi!)Lv&ry7
zIaD?qx{0*@^E2paQR#1ZT!1J74E&#nX{+I^i280bT<VQtyP@nRn1P0dAEC0t(AyVL
z>@<WtK(Whki8|IG!_XR#?KaTgF5&hVRM+4z*zk81!VWQn(;1FXLuds2h8g^+E%q8l
zVWx`HU4}Mv^ex=5m)@2LLyI3^7-_h<3{~52s72@Dq6~9$!8~9nod(T=28oVBMjNJ6
z1H~9ze?pxO8DgG6CDt&SUa!LjLw8U|47*Pw`Z$A*mQ(SD)7>CTFof<xU5*;=Qm5xQ
zW+<YGV4~r39?0W{HuQd+Flez-=1v-p?E}myL;BwcE$P3Q&KQ<bXOd!g)D+BA!*W^(
zoi$X@(a$u4gQkP$493wwNjLP^3Fz~N)hp0W7Yw7v!NVm(^#IsiHnePnD6TjRZ)tn;
zs^RZ)kk<_9IWWvHOz?r~4a2UvpfU|LV$ld$hPq>6m~B|r186yh+msH;HLRfnJhu#y
zYEZWgiIWjUzQJcUn0E|ghQXk~&?O48yM{CU&|HOv19V!v$Phytc*O>XA5C#f432q-
z^qyfe?WNr}95v$sJus}W!~UT`-5K_e3|IR?^RXc(5y3n${Ba(#r-o&;qxj5_bq})V
zhEjTjr3SqWl`?~YUY!?)^K_>7rJ*Hu8M#-6uJk7cUK<v4fkC<9mZK6uRTv^WA({_{
zCX_t;X!!UM%uj}jhS2$J=-3_&^u>@CiO{|p#$HC%z8T!NLsn^squrM(!#y%sY3z0u
zepea$(uRkp@%(4VRvTN>d+cQ#{0vNQW4mCetTTRp2?pzpOXfLH`WP?KtaO7hya_Be
z8ry$FFq@2e+K1e1tQ`c|7UO#wjQx#<X$U63*nqO^Ta9jXx^$Z{#1+i##xkmQpmAFZ
zVD2!Up?%Vw#%hPb#5TMERFILq4B2jDM>?Oi$LRZ+PPc^`ZL}Q`X6!*{^!6H?T!+Oz
z<B<2D!i}d=P(&C#$03+VquT*QxZn7M@)=Rah|}<Uz<BycL~+nKQUMih9M=#kvBsK4
zRN}C4FAM63F<>`5#2L3!vMt{D?gyAB7(*K1N0!`C<7C=)IcC)QBg90b+k2=UH!kf7
zofAgO8^D}2-lnsrr;PUpphz+ftN~`Saraillww@?3NBKOIp@&8XN`$_5q+95a1N+*
z#+Vjp{B)y;Kh4FRH@a^D^aW!|9Ap=bn`w^dxMIB88t$(eAJPfbYsNwJsbv`V7+`qa
z*z+}*H;gkc!XneyVFKDB%NV{BezT47v?9+jR{H?+Tx0t_z`kir|A^wY@yH|?<Qu!H
z0d~je));juFiLG;e%JVh+OW{Lo;K%-97f$(SQHxr>6iH>##CC`-ZM6)9i{um+4K{>
z2gbF*@buW2JQmC+#<5>v_|)iNKs_@q7!28SW7AWxD>eQ_`=n(?!vQ#aVeFm`>ZQ^5
zM^yBcF`mv$zcw;cfLU%F*9|Cdj1En6xPNP0cMxdrjD2Z(^}#4o8uX*Fj1CQaGCJr0
z&u8N|I>-9O*nbe1Uyc0<^qX-Z4d#``gr7lG868JKd78S>ySmymn2rZ{nKHXWw#MW`
zBlKER>my)#o7U1AV4Z2ILx<K|Z@MxRIzA=?O=UKi8d2hOqv`QGFgKab_5|f?S~dWn
zex_ISt2uwul?I3~z_g0a9BefSv=G{6I<*)E+f7xp2_I-0&p>5|sgy&!J54!JaKFpc
zmS#dhriJgI5^OSeasWHT#MeX=p{69tzl51I3}E(}F6+^<`%HIeRTgft4M7oMx<m7^
zNRzi4K=+%HX{RE}w5<<5fCDD;J1}ERsqeu&Wa`=u%vjSF8e9&WYEZ9r#1umVW}K;n
zw%FrMiPPx(MS^L&FM>L1@}t9-$4zx2Av|HKqNL7A)0GHVoHF(20Fz|mDchE8O8*43
z(<TG$M4d6Mr5R_6shCdarkX+yBZ{-8kh)MwGijZxZj<*;$S#;J)27o!(_~uIT{3aa
z7<_-1P2vB-?-kQ^7g$_1)f|iBnrU@CR5Zi%dORFnH~l#db-H2txht5Nrt6fI%rT|Y
z&**ba%^#v=Z<@ZefZse*;7CxnOg(UNj=ODIOD|HssU0O{?wEex1F!;9Lpt?%*VMrm
zZSN>FskZ~B$W&_>T--C|84%2U)A@MVKQQf}b=X7G`EVFMG7Z0v;;|{H8VsJ8I#SpF
z)by2x*k`6f0kSgF`bB7`7p4?iRlPI~p-I{+)45Sld2L#G22{BzY%Db2n6`VM)!sTx
zFA`z#&J<RNpx&F#G=Q+eR855Y4<^$!c=~KwLz(n1rYGKLnXjgcAu#-Ay0!|kO4Gc>
zz^*c}O;DMYW{C!%Rp!4a<LPN$K+koxIb<ZN<YoTW8O$~2^IH(bdUK1ZF!wP#vM8Ui
z!CZqD=o`%+XqRl0dFXC{ZZ`L#iu##(`b#wa=2?_B4lwtd1I?}GPI@r6neS{sFx$=1
zFTe~m&zKCb9p>%yXC-!;&8=a+%k1U@zd`1}0I2LXAEXawkJ*bh!h+449Ml_xm}gxA
z8EWqM20CHpl5YUrYo1IK*L~*X(Xa?Nk7fW9VO~k&Nu+r>t$_BMTWAn(l({w?p*Udf
z`WSWx&4pQzMVlYfHbjhhA8m#lGM}N1l34Q}w5~sFUbqC*5p&=Y2SDS@NtA4lH*cj8
zGr{cr6YP(g!$$%8n7L~`*e9BEr^4d6x$`U3>4bUOUyz+Nr)DGUQ|8iWR6EH$BmhOS
zIi7w$ciP;X)>>!G!uJ46F+W)hW~%u)<z&yAZ5!bz&Ae|Ft^dxM)wJc7ZkFOvi}U8{
zLtuEpTyrC^FPaPKEZ8OUl^wvoZ02jj{)&0mP8eJ@>vf3Ynz=o7CK={iAJ9(M%`Ovx
za>Km#7+hqUYtkl4miY<g1GCL<2LUC=?6DTITyr+o0Qixw`Hm}G<e6O$!SI%OdOrwn
zo2Q4uFyHJ$f6n5LdDtD;7nm>4gWtR66Q7`2XdXbrc9A)#B?2uruYLon#60L0!0wp~
z#z5u1*`&byf%)<>6c5d@?}7QqyqSjI$L0}a;CNzgPA5;EoAXw~MX7oGa@48J?Ct@W
z7v{Q=z<z0d-50V~=2SY${MuYp30b*0mXc6!%x7t;`PO{rSD?K!yM@8Udvm9Ea9CmP
zR0ZmT`FlEp{L#FM4$OWsx10;R&*t<LfPHb8d($ZX)tr+8op0tNwAD~)Hg|yED)TYt
zFCs0?t$28=ENV*fds;H+mkg^dzcfT!cv(_|V7JDyo2G+nExAn~^R`@f=7KE)zXRBM
zO9J&wK9-41VZOogQ%^*((ULt9nwu<+%fmo!ws_HTmMs=XN2vN*_ED?*S^nvRNc}CZ
z)}aWnwEhLmt(Mj_P1$Dgcn$mQmJS3OXqiXd`wq*!^I-0@l%>F6m!&QpH4m~3sEr7B
zTO8EE?6LenJ3_&h*S`TJ#4^c2>x59t9qLNMEUBwtvDcyt0=3U_)CE+yrIcn_5tej1
z03K<XpA2fh<)8VWqAXsNuRUNH^e>8omIH41;-W2ItKcHWvPuW)kmXl8ffZ{B%Y>uD
zma=Au;)ta&3uc^U(=-Pnjkk=X&DR7=$zN!Tqn4($*LKV@3_on<5-p3~LiM<1X)#=!
zuuP>S#YxM@d_1317DbI<k}P-V%xAKtI{k5u)0TWX8+*pGq5)7+EZytCZ>r@f{^BQh
z&eDk9+;of2Js6y~RO`p!`@3LSLQBPqmR@sVamf-(KYhAvNvD%5S1f@eV1L!}emDGH
zvjlEOkzwf{4j0!g(c=-t4a=ezpfW955mn2wyrCa7WLpwwDV<~Sq;yxVC63;%o0d=1
z>*ZN?b^vwDqV=L*7v8pf_!~O;mM%0yxMNu}6tNXp5*{InyB3#Spb9PfXxuHb%zTRm
zDz@ZL0##z^w-@o=v-~m@)P2je&cJ?PQB4KdL(4}iWREN@7s1nG%QWhOpICY}0p?T7
zPjs5)nWd0UGCQ7Ie)oc5sYO){RV%a9_!EXNEI!9z_|kHU7Nf5$W3{N$Ys<i8pvo<M
zTR`)T#XJhtervgv0ho6dw{?)cx4g&SE#xXJgA>90V2K+D&5xG(Jy3kIY^SC8XG{5f
zsC=<_(2V}8!*byy!vAIwrbDOFqNkUw%3`IY`AX~cFDO=7J$oZyPiq4SZL!*FPJoJ+
zwcAzLt+AGGh00p1kOdWQ>k?YHt+Sfr;eNd}V>mE<tj3?9vccL|k9uyjzNh5ZCTkS!
z4Q{qNey2`%i#1{#3SVm^%>(_chrR;M-?}6aIsw+3e*<l+wcH&r+pNEAfXa63*p+Cf
zK<gZuZ||_Gk3(~(b@zF=*lk_&3K8zHdj0`fu+=mYvJh(!otzA{MmNMW2(w<S0CTUk
zt>YuG_gVMv19rG|tq-Dzur6r_>_}_(Er?>jHIkN*QPv5a;rD>`-B}nOwEiZbh_(*j
z0=pRNj9ySVWF13^rdVt1dypNrW;I4}#A=-al{jl5RXg75y9^!@tS&<l;Zf_8Jv9G3
zW=*3#uSDwxYPRFnA8B*pgf%M<#Yt;)Z>XNK9-}>iB<lwe2FcciKcb?it)6{QoUv}J
z0cMKzE^TtBT5~Bwd)C^<iXzP_)2{>1Sv}~SPrB8m9jNnGPwJp9SpON1KQh8yw0>y;
z)l1f6beQh4HH=c|SF9H)A92-MKLT~SX1&xA?lY|YZbI|AwP!H=-moUF08FM;^A4I>
zR+s&-%eJmh1C?WKPG_cat+i=+a?`qwe&m~H9biNhx2#*}cd@sv!?3z>aQW8uv~Im)
z-L(b{RbV~&1)lC&>(FAS(7K=AvLfsJT!dC^tv?)~CDyO>Q^|YQbF?3J-@5WIXg;vE
zIf6hRTH8}D>XG#*?G`<@&ZT24PplUn!oyRm#s#ux)_mGqe{Q`-^Aks@m9s!tW}WSU
zNMBgLQkw3i^=xaXzOrsQg_q{FHQ^Jm%dOj*K=X~Y@iqinVXfu^*$3;Xaq#rfIvsz$
zmHTA<^#Np`t+Qy0@QbzV3c$Wvr_+hPZ`KbJKvi1z&`ItptGEIlRyu4a><E9AO`u=!
zdfG|~0khg>C<5hWs~&=w*4WxpZf32mb1Lk;ZN|l**4Z>uQ2X_^)Ve5qY<1~S@dn$f
zECjmIw(%zfy2*B*{^ZbR+a)!MEw-K1t^3+4C=KIhOQl^Kf1Bex4NC#GQItyCY6}bk
z_BLA*Z53{}xqJX<plvv9Ywxgm%!H?%wwIK9+hy|)1r=obmu8&1ZH@Z?ZI5jW<s5=-
z{~SdPLu_+Cq6oEB9)~Q<HYXFZy|#<=jqI}pP|7{r#yhC*j<B6v2Qt#O_#0IB+n#5G
z8D;y4PL&<7-Dm_)2W_5r;5XWK_cl~wZ1txA=8&y3tvh3Fy%ZQ6w*5d)@`!CQ?J36D
zzFvWOysg(@R3gDPZWfqFZEtEr<(SQvQZ$LSX1~+<v*WfJH-L7+=F%TJCvCp-VR*{6
z;4orJvaQ9R0^pKur#rynw2j>a`!hC{R8nj`@4z6{_VibTcGgyR8)RuVdm#+Y+4{zT
zO1Jf$36%3TEe)R+Y_W7G`=afU7gR3UjE89ayKLKDfM;;U_BjesT(v!=-Op>bY7bzM
zVf&lX>(^~pX<2o{mM|9%Gi|+Ss+nc0vk=T|+m#Pc$+0=;Hw?M9tXpV{o3`LKklnU9
z&cai^t(;QPcWl{pU|wJ=q1?<}TdEIze}%S3OTaC%ef}K|i*42Ey(+P}(30(*ji+hD
zecSjT#Pq-xK{=s^w$8KA7LRPrCc)EVTiQz4J+Yn1gzTwpzX{mSY~Ox{?78iDLqM0>
zI^KXvnQhGp*uAh-TL!R~w&k=Kb-c3mDuBgnTUiz?%55Ih2ybk`w6cC{b8n4Wyt6%^
zGh6R%MmiHvVJo~1`wzC`nTYVCZ6oaie6m#?Kn*|Jy3kwp#kP@>v0rT!eqesH71LW?
zX}h=!c2%~=FX3UOedG_IRypjChoQcn_LXsPxZ0lI2M)dLeJK;L#{RGne%IO?w}vNg
zd-io;ud|1B0O)%Adm~_c>@4l`Y_NBuAE0csccn9$o9ufMp}E<vqpai>`-}vr_}cY!
zD#g#9{}y2W_81yR0_={POQEyX{<$M8w%J4I&+Kit=f41UpnddhxZh#FOg-C9yNcGk
zyX==+p$M`cI0jF<?Nh1q+hgB92%y3C&8Oih#Qvr}icovw9GHjMo6`Diul;TY4EEVK
zwnY@-_TT9UeuTZkAwnn8zN{@=?6*IuhgwA07tuEF0lVi31ar_nz9Cej?X7)5#n>m%
zpSwC_kD=YMSi8~=Xov0Ne}%yjdoZo<<LpPCKqcP3mVS4WV9z=Y=23gg5s2xSePt31
z675m75btsOo&Z|^ow8r_MUiB0fP_4kY#*jUaoV0jUD6qQd|wnP_Dl5CQth*7f_~OM
zkk;pE_W864dd}W07)83hz6+u_Z&yu(`wRAbN)%nR_qq?eOZFy|L%wX!uMg^qeFXk;
z7kAaJ>O;RSyk?L717wDM3Z1FDZeJpxxM3ecng2}tlQ4vqWj}ot%xwDw%DCj%FHb<L
z=h~-4Lv|B?Di}qc-B=eYx9o4#u)A&7E%|>qy6(6xtMBj3va&4Wv-jRBOLJtFrD>X4
zshL@}U1{|zGwZ_?1OX8lA}E5gK~NAGGDH*sQKle!$`;uI!tZ^)f1TI8=bZOB_wsq}
zbMHClKEUlNo6#F^=An(6&SBLy&%$A-#%3T3uGQMC#bpfZ>^hsj_FypeHb?39TZ4`N
zub8h!o1czDvB~C-B!D*Cu;)Uf#pY5JNUO~n4~VqcxY42ik<CkVnryd8bbvyKjU^bZ
zPMgay5b3g+NtKh`Hs{_4>9H{nL!s9uj4qTvwsE9l4Qrpx6*d%~*f5_#qu=JB5HmDj
z^9~&j2W>u^1aHVDf|ieA8_gz+e#B-sy+}rF{(BS7Jhj<01K49W2kB<%xXogCI(x$A
zkQUg_Y@T}?mL_dN3gOd~&GVG?v1PP+f@jA#asbfwRz|}cpbm_Dx~JsGI3WkqiSZL{
zFpe?`{Gs8@$e;og7sjmT0CS9y{ta5LjQhFp*NySE8RR(Q+9Bw<Gu}G};=%ZV&O@FI
z<t!+iV63MvP<Sz{Z2VzPGPtyJ^JdJYGwCUY)tBDXK8zX_dVLv-7-;!1?rUJepRtkZ
zKTk9I3SlCUVWevxL5wybT4x!js0{5K<CqR4nBhQA>UqYW6i5hRY@{-aP{w*Hs=mNj
zP1(<j3>IOAF>)UQC7dz390QDCbXe)~Y9!+|Iub-N9#Q#RG~>r^n22GNP@X52@xe`y
zIK~T0z`MjS(kE2o8G)++lfc+U_s=df+Gv@*!ua(D{7qyiu7V^n_BBD_DkH^!zd<r1
z@g*3##wesSOA2EaMXgd9JND7}FOBg9C2`UjPfkPTI%7GdZ88|_BD69YV!D%+#aKYq
z+}VtOcB6HJp|}Juau`dppm&pTl9sewhA05TzQwq=9d>Us?u>w!$M`!DtvigzhX9t(
zxR3+A0>&1qw<%=Yd_eWrcNxwU@-Jc}oCo$j#!ufs^gbhEH@qljDCrv;C5(BLw=89t
zcf&*(<2y<imNQH}P^e&hOpDh8hJk`Xm5d9GFj&PH5raHrY@!2HH6!;jEYvU#K7v9m
zqnwIw>liJil>e(|Owwz#fw6~+Q8Y4=DL2x@D0>ka&5YYrU(v$&gqE#VhHDjgZH(++
zKprvl?clXDB0VtB4hCZ<6gnB3-vjAlJfNUxHzR90cs-1Hbgj3S!5)G$j~V?G&gf%w
z(WMjX6GkgNK>dvOw!z^6hA-{x2N}%QfIY;R{TgO{nBhvdgGU(i_F&pZ8HESId&-F3
z1%)w&em@k(89kJ|nPemcqBX^6rj^u|+026pJLcx6P`76W_`)>@=A}gtab$MQ1kcIJ
zbfR$CQKpmwP-o^Z`_b#dZ2AtZW6Y>@Xt**rRzSp!IZC(9k2AlaYjy6-bq0udFeMb3
z@?`3dz{CmWdsO)8#hgaf7AKivXN=dIDW<~qQ_SW^X!$Uo9e{!_vve^~{Fv6YlqvCN
zN@?SInmLy?!vV}D9fo~|8BNP<AoGwKpg~M6y}-^g15L1dj=6vjUNCcH9rVsKrE~}m
zVfIjELMXGb6_zeAr&2*KGN0)n62{aOKs}t9vmPXZ+3f@mBbi&ROW<1+^Rpl*Ml-dv
zY{f7`-vu)ksePD;V;(;Ym`ltxEcg`9e2EHd6PUa}=v`*2s8IC^^Y1FmQzG*V6TC=b
zz8(wSRc6z_P)}wiQndRT^Zg`XrZ6*&Xr(e$RQH+2yz+o(Ix~{$-mWv#w6K)Hbflw1
zCi6=wYRh7NxeFwlnVtblH<+*X!owWq90~^AWG2zJJC}Lw6h?T9x#$Ya-)1gY3%hyD
z;{Skhhxy(sfX-)@l%TVKc~=Bd$owS{V0W2e+L;DCc+581N!?>Ept#<Brhf)n#mx0Q
zSSn#^B(PM<%ufTaj9KBm<B-bQodbz#rkSo=)i49IAy~_t8xDI7Oz#eKHZrfQhguW!
zCx7sonGF=>YGE##kHNPxA5zS$jTuS{(<5eMAr#t~122Nt!K@YG&(q0#=T)@2m{)&?
zpWRGLG)NDVO?7>}%;o?4FzRFGoGD=UF)#fB<`ZT^Jxug7JClJuz<fkr4>C(B-8sa}
zp`XPtv$PzYBg`3_F_cl}F1qyklzEd4GREwA3%qgWDmpDsFrQHn^%-;A9R??v9mQ~F
ziun$`gKb&DLzJ_%W9i0V*PitpeSX7%RrM3>I<iVWfEP|I1s?{FvaY-c7-!b$W^}r+
z++xr=#(Mucc&@B&dMMmj@BIzX<E%$?j&Wxl_zIRhSg9v~>B-7s!@>#HZ_XfItW`eH
zJIT5*N;QMttp7d)+9}rH9bo&g?gpae%hFMh-H$cc4N!kp+<Ks$W)<bZwE))f>ENAV
z9XkZOfvi919$OGgL(_ehHJ>V_&#}%@f<Krg(}J954SInW!V0v5`B2sjie_A3<*lMS
zD;HTUg8&U<(SLfH9nM-t5&sC5H?2sKtXgl7C{_Vg>qWCBZ$L7Jbw2>0v8?$NiH>7^
zOl47*Sf7RfG@eyMh1LnIXm@m8X4yW6))m$zD<&b4m79;hPZI0EEVzA@l}KMQu_m+j
z41sx#bz%;hDXhBZz)WSmLN$14tav3l(^>oI2IzH`tOKAKtgdBfWwPpb!>1dpJCtY4
zVKo%N?VGH`!w|`34RIlIi}m(-n7_^P+zXP&nop1P9oCW`fSJ#7dkV<{D{JxuhF!?o
z@hX~kSzG9LRm55{0F8UBrIfO|&swK~NHHswlAk54l-DuPQkGyH%$Kn?PynHvHLDs1
zD_B7>5P85_^#ov*tTj}>RmJM=gWZR$!%FB?vrb09-x?N|mV#QA^%iYb>R5l#`Kz9_
zI~}48tS0;;qS=iswmT-ciDjjnQ!{Hyg;ope2JPKjS<~q>)y4{;l>Q^uuUkOcSsKdA
zcCcPq0M|NMEXuidu^e9nbT`Yg5Un0o+Ea-1vZ5#r{g~Bkr8r<8tDY_pJYn6~221^{
z7sOx=u+}^T=pd`+Js2EfS*XTxnC0{h&_-Az;}98T6_EN<)<v4qG1jCXc;l?%B^coZ
zE6NJqGZu&HA17G{3@|^%s-W$?ExS4%Ej#wV!BjJ7&pz^hm~IEQnoiV?>^Epn>ckf9
z1@9=^i9Uwv%$B?f^DgWX5iA{JJKhD1D|@8}T5fFPe25%pAMwS|+}YbHKJ3AEYXz7m
zdl9`9POuj{Vh~>JH>l|6B)k4FM7-JSE>g_w6nh1g8TqhBY(RY3?U|SaKXyI^di>eS
z3-I(byM$gN0qpNSgW?(XqX@JD*+v(TAofx^bDw3uwHa=oW1Caa3T8LbYv4S)BNIMd
zVCT_te34y23SsQ}HnhUonr^BYj9^Dl7Cw@FVkLZwVlSs{dNh0Fb&M&7Z6}6Lv1|_I
zS>o86{m{C^zMTS?c=pyKa4muTQZo!*W(Sd@SJ>w$&63DoOD~lqwwmthUuA#o3SKh%
zm+f%o8v9!tsHd=xQkun@%Jyf#n>2O_Rr{s07gC<(I(rUXGs$50P{=%!{SJkhv)InH
zn38OERW}BDgFQu)n8W_f0GONXHFTiPWxG6p<Sq7f3IN<@e_#(@9$Vjw)*beiO4!Y3
z-&LYj!2XI>twJk1-Uxb^?OBHr7O|(*L*pL%ISQ2CXTSRwc*X4U=g=x)M^Wagl->U|
zOq8+nD49^s?xQzk1^Zk24CMoM61@{E*^h&vSH+f7wD%!9_6Lw^cJ(!&)UbU=Kx)~8
zv?Z-$TYWOYtY<$A!pt_Xy(tUP$QIS0vx)r%9jKexQYv(7VZTbXaINfZL9pA#mcEUd
zdBk?7oM1a!<%!M?w*5W~t&<%~#kyVWZS=0`W@D|!gU8-Thvr^(KNSE!X8%paMt$sN
z>qaO(VL$SNiGKD)It&i5`+0C?kR44q-y!zTl*1fmm*9jsdxZUp5_U(~aR<<P%3e&D
z;m6p=?!fJFwwR&{6KrJ(FrTs8DdjuKuC|ByDfWtfblP$b(frzRI%{Chp7VPqz5g6I
z(e`laDCcjAR6278SipASxOzeH7^h?*enPIC#TS6)#@R)omE)X{51{AHVGY2b2j^WI
zD0p(@KSJaLXOI>~FV1gtUOdTJF$+9z&gb;ppW<9gN6Uxv>t@*V<v4g#&7dFWXZp?h
zbKH}lf0{E!4{iYG5?$jt!`bHwgMpmqDQ6VKSyB()S<YKjOL~s;dm|KrIom%$=Xp-(
zI+zII9Q1`kDCaGT>|EfyPX#&`Iqa1H3*%g-)gzo!N!M;8I2W+Zw$6^^+@zBKD9$xH
zw?%U}(I7FLeh17@EXRpvJ&seJ0GLahbgGbv=lo4y<VxT;rUCRaM?(kdE1b+IIFrcX
z3SlCN^K}7Gu5xPV+?C96I0ckz9PxJ$N#O+1k2IC@D<6{9G)^i-I@3A(-bC+pPN)TF
z85{+z>zSO*lu^mzc+3IG=GcXTcZ0*E<t~RaPD#0&oU?SG&gFEO;NdNfJ0*K=bEaR0
zYk8c{XwP(qbDIj}@;Tk~HY?!p=m{_6gy#b6u9d^}222s>B&9^|aW)6S(tXZCI-nMF
z=2EFw2`7Z|LZzHED*G<u9Heh&lymxMo+~(C(Wi+YaJH@luafgVWdo`>zyAgk4>>b~
zAX3e#_zA5V&Kinj)pC};kBP101k;_^dXBY@D!dyw>&9TBkyA(5O`JdJA!+7x`vJR!
zbISt#R*r286x%spQE;$>V|W14$;o~N>RlW$?Hal{i|7Q=!#PU#NP9V{6c>BUS;&Q6
zALpbq%s=78{)bjS$D<5-0~}XtJ7fkqQ+_Zp#QBhFJ%%|&GoU}h*<TNtQI5JCqj<{s
zKl<v%7-tzpXvR4U{4l{2oG5IeW<TRRses5NXEOz@rZ|&%0JG)V8X#iFt)ifnJ-3h!
z5)RzXQ-F5l{;mMD6L-mMdj5`bZ*D=aGj|$2hA!NLPe6`wdB4M;EB7FM&d`lJpAOW=
zxy$HFZSGt#-PrNqrYuFvle?W(trOf@%At61`%C~k$=yPghu++{34opA-rND7e7GOe
z_SKg=hl1RG+|n26AG7##Kc;2tG<Pl~`~tXs*WlY3ZiWj66Uf!>hut7<Hq~^V<xcCu
z=+AL~qH|v`_v{N0InRxws6q%=P1O~lTnEbaUf{O9i_VMO6~1VNajSN~r*Q6NT3{l$
zc~le<$sIw}n{{>+H*FN=qq+9<8jay@NC0*$_hkyn#&L_O=I|2NXDfV)=T1?)CxJVk
z)|AWKjq~Bt74DBOLoboLgMukZ+&ew6bd{_95|YVWXZixjHLkrEyh!0D4?{1NyN$j|
zlE&qH2xx0Mw`D#QuXDMSkj>!!OXJPtF8&?NEbcqB&Si6RsBYy3H|1MQTMjqyJ9OUU
zPOgEYx!iTngLjMj3q4%7xpuEWFP~fX1SSf&*Rz0G$X%TU$-CSGbd9Hoo8Sudd)(|k
zwC-EEHdN_S%sodNloIX-;ZQ8)Mm&Z_8F#4wpyk|QdVVXoGw-AIfV(XZ`jy-^ITWh6
zCumpskn27UUNv{;1DLPj8t4pL%N?LXvpVkie?aQF^8$g=z%8a-a3fdnCfsh~TB}}w
z!Dg<NO4C}nZpC1>a>sUn*~VRZ1iVMw(=_aMZrA`E?%;-$!F(sTbR3qtxbgF#(9LCi
z0DpV9tU{pla(#aV?=e?E>ti4Ha5+$(a8bsM2aj8m3zPxw0oo%Da-*$Gpbc@iM#01|
z_d}{IAK^Cr4Vh8yXI}yBDYu!*gvPjC578RuUVIgb6WlcVu|4DdAC(zQa$_hsIK}P#
z6P>oa1P>_K@zS3{!JgMmbt?|MB@}^n<fTPJ-HG>@l0-*&`Bjv&b>_LaK-7hIIT3b`
z@dADaape`fgvY^+=VpP4<2-XYMBI6=)2rQsH+?BOJ$YLCGo9f1QcA>&_mdkyPx3;X
zLA-f^6h}YB3;hI>@56Ja3thgvf@Y}u@f_Ju@aOHAP4B<cya@@I0ld4kYdOOkti&V)
z@=9j_CWyD_S7@B&Jx^=GIi7|-_!7)xnxSx>SMWSULU^r@ffma9j{d3F1>PF^MB+uB
zHWs`vo`4RM;k=i2fkg0vDJ&MrbD~QlF}&Y0=pQ4+@-|Y;ERGjRp_xm(-dA8Eo@dX*
zL?!U5A3*dnZ#h*9UE%%70!idK&48mxyy-Wfca<j>13Q^F^KbC3@#a$gI)%5C{=ZHt
zug)JLX*|_F3@M$br*ETN=lLvyg$&*u+O1eKdEqCZn8homJxn(5qgG(w;H{&|oE+Zz
z6KLJ!4blId%H_Si1Fc&;<sqQm<{i|)-#p&r1VHcbLd8(e=XJ^;S-|V3kWL}bH3<rL
zdG>F>nIhgh^PzW-mrJF8_j$z>l`FRLo>GpigjYL`-cnw{LO4^#D_sUs&XcjBSix(f
zPo+HI39drFk~cdNidDQ&deJ}R6;l;VH7{pB23o^&UI$(+&&?Z>b-eL+Fv5D?>|nGS
zcr{<3)yU&g1iFcLnJSf=dDg$Yq0z#taD%~CUdJbJxQ)kd1NI|cIUNkzc|o)X>EK<Z
z$Z99=IDKfYi}z0xB)fS7VNmbkDP9C<FYk?y(0a_<_8Qdtc>C6(^@Nv3q56K_<Qgap
z@II#O#UM}T2{Oc+XQef1nD=KbERFDv(;7O;+Ykr+r##%Z#e>J|i-PDlZ)OKt6Ff21
z$3Ek|M|Zy_d9HO(pW^*O*$Z2~L;w^!zAbH7?fHpxhu?wkmj)3>{$@I6JMlmK0K-1Y
z51}RBng7=R(fQAX??ubyG5%i^`E%umcS7HducH@%2S0WO^ga1=sM_xYU*iK9FTUL-
z=$+)d(bmbE|AfM0r}zgFq2R-}VZdKs{)-Vn@#AOGk;|VyNq6B-^TR1^AHbK=0qhLF
zYd_WO2J#P5Qay-2XDwjP@&_CMdX6u;2A_iYhbX3bp8pFS#Y6bgPtgkHzi|UzT;Ol@
z0_a8lZxojf<A=~bBb=Yu4_*X+h~m<b{PcYQi{dBKQ9PP&OCkOk{*(t$V)-&Hz5n9)
zpRR!4m-x9<s20!vkV=UX`2WlR=w-f+9>XjA!}-up<e&8ib`n3K3hrO!xBEjRnZIf)
zK(F!Lr-P*M-`xtgQ~4j#bCAZ@Q)fCqo@&{y^Y2jhB7;BUKN!m7H!sI<tyz3;`psqY
z89XT7;PZw+a`>OEM(0hwD{b9!`TMC{?iPQ}tN7dB=EqajP98s)7UVm8n{)6mpWovQ
zg#!LuN(dG5x9Z{OUH*qQ=q%#j`U~p!_=8i>yU*WADYjz%-d?DeSoss#_yd*lJAz@i
zjGv-{OgY~r9WoVspKoFQ0pHaNB9;8hl<%+NPk#-AdC32L6|k%MNtYp6!!Mv3gj&A(
zCPeD^MoRbB^Y{G$$p-$Ow}H~gH?M?iO?+EALpSqVo1xyqw|?vZW-EVZ7fiJAlPKT#
zh`+WBGuzI8jUs9t{3UB3(#c=C6Cz#wwf~~Co6n=Scn|*!-A(V~pQ2>Z6aM)B-f{dK
zn%M#VHaW}>@-I;QWr&|w5A|Wb9SYTEkMK)(!ony&)JhT4r~GGSAY=UBXm2~tzvT^s
z6a3?P$UNh3p$p)X{M}TbGsVyJhKQ}8oI-zgf`J7Xg}vZ#D2Rigcs}$T1zn>cPJ;1Q
zp>R~tO65Avg0=J%y9mlC&2mhzeGoiX!Hf;`{J9CTC`fW#aD!4g?t&|GAmbrOp&+}b
z;C1@Voe;QF2+m8ekv5(u1%aQ!UvI(uEs#7Vm`k<MK7uk@XnX}>FN5bNc+?0zf5Df_
z!8<JoYsXju1leYYoDoFEV`c&ctN)=pD?x%m4P?#=-lSFYoZwGdf`bJwXkhTX;Lzvb
zg$QD3OrZjQ+Gku4h^Z3dqQH}0^kD)9ty<xN6gu%m2pT9_9Vz&hDiWduLsYaEEy$y{
zQjFkbJxHwJK80rE1U>K3`|pyVnbHXHg4#0ZCkP^`mgllSBSY(oAjSpyiGmeec#$O7
zw;Xn_3ig#kKUwe`#R{(p7@xz76hWyTUZe_ggJ2>}@X=*VLb_nT1kl$7^QizoLl8sJ
zqf9|79ci-!)kEM}vjw~9W0W@p>^soU5j2HC|E8dfY7lY-A7w!1mSEZY;N2Fi+5(a%
zxN-=ccLWQm$S_~<cs;NS1nza<6$(}-p><cVAQmQy1Pi_Z$~}Sb50DapFcxl?3SQp;
zdu4(f=P;ylt6+CH6e|Sl=uG=Su=)y^m4YG)H&+REegg7Pu#C=X)q;dnOi7L4U>inJ
zE3g}er8>dO^fknK!8`si(I6<ZgZGVsNACc;N#MH!>dk_dUEs9{ex;?MRj~a$MA`(7
zDbRZ)utriEy<HGPG4~F^2HGZd3ijNF!7jlZst4{C<k3#IN3fU)Ua#P09Izh?wv|Gm
zPq2Ltym%sbXAVUA1?P8zHy{wuo!UXc75ZHa30@`dhXp_G1K5b*CE9I_3N}$~<Ws>R
zYc3SW1UnDI({aIB3ZqU4jGw~cXM!<05ljjkD6TLiknIDStx!opEIXl`J`HX!%%DPR
z2jTK2{3#rT^MlcH5<WQyFOCW)UWJ0Qkg*y(7h%se4EvbS|0ytCg@02Knw!wG!3ySa
zVe@S?-Gy#0V0s9@r>Y-M;mme)o)F&f1o0AjQIY;h;Q_k8>MaboiPkBhDj%--2oD~F
zGrq#lc`)H8jHGAVUwGUdywk$clTZ&3&ZTm<Gs5Iu-~|e;2hj==21Zl-^Q`c-IEbDT
z2GDsqShxw_KA3%8_;xQqLxeXd6dfweHN)Tqp<5qBE((998%ANm0@|5}3;T-E86o_X
zo~lS;BYk}$N_eOUgNPQMqa#R+@QsrIixtkIvBU{m_F$ea31=Y$Zk-)3?4+8f1mRA~
z=_d;3K7oFc(61DVSB3A*hG??z1zLiy2^D_er3j7m#H9+O--6p|!v1pb(uI|WL9Pog
zn=pqN!jxd}GKJS405eON6a$59A%g*OLl{lDwH)CZ9*Fg(FoHq=xxz`Rzq}<(qLb!r
z;S8#t$rCc)MC*?5)EiLD7yeACl>(tHopK6=ew5|9D=hSbUXgHu>PPMgbGM^)U)V;+
z&tl<fI+~UU|Dp<{QsE0!gk2`ArnpVHP`n7{E3Cq4wa|DVWVl1LQfNC5Fjc~3^m2SC
z45ZjhweTK2PBlVD`g~xm@SnZFt`oj-6yvQIF3tdGgRq_g7>&Z+(eSrP_z~64HVauF
z1FS{3fU;w)!p$DgYZES}bLS&rKp>#og;t>jb~}VC)sX2F=4D`@UBU@7nBBrnbnfgC
za{dFaSEyV96OV-v^fdMf-RMbwA}sv?j`j=x^9LCarcn%fQ22=wdPBm8??7Z&xL^i;
zK_kMVTo@V^e$xi%r^4O7AY;OF)&kIR;Y=#Gn-Kaehxup1|0sAiDSUek#yce(eGx5N
zQNAxg?L>#@pViunGAWDVAev=?o}-9Cv0x`r+Dv$HRK$4?!*&+kr~7X%A~~ITj)}6C
zL&Q~-5P|7(6RrOgddEewmni<?E)stOG!M}WUJ&&Zu_^CyLS)H;jF(7BN7Iv{PwCz2
zEfW0&pL|8SEOh#bp5FjTf6;fb=sYb7W5Ps$XfI_E&xq`cp&lsOPkYlK5#vkPJu6a4
zF^F>_Gi?BaMW6F2{&HUQ-U^_Fh&+dY7Ak6bfYt?3G#$k+ii$n~T9}A+8rb2Y4=89C
zA^PV$up>pE&;^Ys(MApi8Z9bzg7-0^>_6a4tmsv$x``7lppwu_qE6aY#f!#h!<ry+
zrM2_2=<jB_vw1}{N(Cf|qW{}~5hjTeod9}O^xZ$uNEV6cY<W%eD}Bd4Mf9Tu*r}qo
z)<8c^^dW^D(?xz1j=V0)rG!?7h(Vp1qU)ETmnC|>A7I%c*Kv>=qRT&mmm^xV7OveC
zSzZOEHCM!#hpD+GVo*BawkVBip7KOnb71L?$d$rB`66Q^{4NlcQYfrY6iaogcSVu3
z^cRT)^qJIqqQJv2abGlb1fazt$#0M>5d~AFN~y@}IQ%UW*--$$T=eJz@G3+{DKh-P
zDzc^5ex>LfZ4|0RhCJAPD6*pza<wSn9<Xaf|3~-0Yel29_|=IXQgE_fw38x;4Wf~w
zu-hma`vas&^pXv*n?(t~La#*>Pmh1AXx)$KY!hiXAdf^FrlGT4G;$1J9U|-f<$&oF
z#b?8}F3~@<AL|ws{0o^L(c^aTdPT3%rGm$z4J-_%PvqSQktZUjNObm#vQGhKKol?r
z^Mj(SG>m0Pw4b&jqap{|XFL_{d;`#9q9c5Cj*BX(Ze>CgMzi)z)NM`1EKG`KQ9gW1
zR9+2YD^3rFc{_1O9rW$R-z5XoL7Yvit)p0<4}(tP@I1J7R6O<?)Sbm9E?O?)<^Oxs
z#7qi&x{4hrf9EDv>;TGfaU;Fk+{KIU;#cA!em(>~d5Sy7DgJUo`~eR#USi=Rm^dl+
zqxunV@oHMoPl;dn4F-M0Ufa>~6&q6Fp`SQr3<~~Yr)uy{i#O2DAV9o{!sBPeMZZBL
zP`rnVEP}-Lhe6JYKWxX4&WRgnpAam5<se);FK&E}Y6e5ZOEhSPiVx6_=7P945v_~j
zEc%Q?n0PbA4#LH&s8%XMY|q1ZBgJo0Rb-Snb_|1w77J*diV@H5L}#qHdK4z&#Jf(x
z-%H{Hv`>f^kN*pjAdb~zo-T{`Pr=bEVgash;?A^q>mxXvB%UUMrK{p2aWIiAuK67L
z*Tn1TIF=$#rG!bUcv~oVY2u^*!fv|w{EP7Ey14W`h-8SH?4gh;{?LfY%M$YkVK7@f
zdmW%}h>u8NFh?9A2g*(H@b}Qm6|bZ!A?q!16$QU;izU4P%@b?r%ydVbM(Lh>v1tIH
z1>#pj;di0<HHtjm6;EaWv`D;?{!I78cPP<$UtC`Sv|{nY1b~%@_qjl?RNP2W<1%p*
zZN$pOpFf32h1i#N$PdH?w=ho+t>PMbeOHTb9EE6&IE{|IwPH1;`0K=+JdC$qd|QuJ
zgZNDvOryAvF8(x$H_>v}EM7yOv}h4;*aE#)u>&oBZQ=lW@E(a*(u}r?yF`%e5MTHc
zyiV~0O7?b%GwLxH-D0c9N-%rGU;GG-UU4_g-ed8ffw0>rt_+3D6Y($=ne>Z4r)bWA
z*qPSQLGiM5@P@>{u10HE{Eh@7BjN;F*GI*fdof*4#WkCOIVN_o2j;kVI_(-J#QW=E
z@0mF0e|t-@t(9JfQ{vZ~pl>VLCB@L}B!jQRQ+r8NJkT5@0kwc}l+-8z<0RRC3$3G)
z^YdWBS)zM}mW$+285E95(o-PfD!EC4CO1jK|31?pS$YmFcS#JbS{@RU7$TmMH{XZ7
z6Ov6+R+#XTbkJ+`q~uIH%zI0=Z3Q_cnRy7<K9X<gpL+UAE^L8@pTuS-X2xIg=?u7i
zTGBoWkpRgex?6BY5_AQvK*>*=U@%CsjqZ1xmB>GV!E+K<9y)_1gS2d%mwfR)S|O58
z#;9gKRFYZ@&<hf;7TCQgIrA9?6DGOP0MKyBA5<z6AsMj+TBIa*DR@zmG5Q8-v}A;$
zRxy$lv{=VVCVOEiPIBM}v@S`eQ#>zTvZn-=5+sFo80Te447qki;y!_~BuZpXl>bYT
z^!|a~tCAusyhxVps)iTWBwIg%r4-4X*CCoNv5$wP>ykK%XJkm;IRc+DB}eHyrCE~B
z2H4G(Os@sGA<<K+JxB6oApE^4nMtqDT*+&00J|mmumP^!mITs1Fi+z3FNpPyL`79r
z`I48_&@YgDCk1Gsq;4w|?@H<@I8r3Za)ZHpl0Fd}y)UVag^6N`eG~jGk%&alE0tiY
zhDS}pqdix-WFytDR7k$0b@hQH^d!8mluXd2o+`;}R4e>YQc3x{YO7><F_<-yz#hQV
zO7`3avrh68746kaZWTeMK{DSHB8`%D|NEea<jw!!OtZvDcb{7%13HjaNgf4b+a&3E
z@ZynV$IEcEU6Mj2mK_onty-ND)nRmYN%T~Q*e&rafQ253HSaWLp;vM_3w9q%I^Te$
zJ_-9*C_a%Sz6`~F$)8t%Js{afOUt07G8L^MiSiZ9)3Aj33iL)Kd+5kDD%ouU@2TWw
zBwAyV1NXrjm)xXU!wE^Y0d7B&eD)G}lad08jZR4v*2S1FTdCn=_-!X0e+B04rTE4y
z9z5xY8+eY=Xfr%?lKycY<fycH1$=UrzCb}U7paPB$d5@UAHjsHv`h`2oAen)9*;}q
zba%^LTKocd9@4eHL%~z}*FumJ(&PxtnwRv5n-wxAr3D<=^_E)Rg6Jvf2HJ-DNM9@h
zny<892fKdKRb%kmU;3E|*r%m`(drc-olm>0Gt&R7g~C~B$v9BXNvr7USFkkm8}QCc
z#dHb{k?#B$lNTyo_dfJ4NEd&L`MoHu-bVFjVbU&t$b?H57r{h?)NUJ?ky1k%T#S-#
zDMc$<dYft$W27!Tco-`c(zY&6`f?*$m!wDNzeL1KQ|bJdAg$U2l*`g36o0uQ-A;js
zMCm-rz9dPPQv~p;R7!8*WNBC(J%87v4h!I0iqvrrNUC&!1lVa(;Y$!rmm26mb6wgv
z7bDD&9;T#Vrqp&nEM-ai&R~SuQoD2D-H`rBpS;VFy3K^hO{uB`db!e1>mYJV+W8N>
zzb#!!d#*fb%m3mh(p~gBw&qJ$e2qCNkmgg)tWY}pMfi4Cn*SU~kyNx4iua_058%^%
zX<#2Tilr5l=P8kX@ff^PsUii=lt~L4F~V}`D#{2|NJAHZ_dwe7JiMrsa;*TXlD5*K
z`%wDJG}x<_RxLnhjaB+c1*dAIk7!R`C*AT3u<NDvbn0%9mi7RxQEE^5uqJ6(B=no5
zyC@dbBCU6U-BxKL)%3JUM<2rcBk9+4&~2CYP=#HGw0b7=I;GRTf<l+H6w^JsTe_cW
zn|q}HJO-~<YF)SqLwhV`^+BUg>PdBiPo#%WgY-)S=0IaW+VC7S2Bq6~!^DvE>^C68
z(xP(kMx<Zx;o+#XmVRtcrT0eAIVPPv2A{^IJIp|tkj@(ec_w8)K&P$DlR_4DvXotz
zAbZ(!){`*rAbY+J#8K8yCHqb?DIG?S%9hw;hMZ-~7h^75WWIDRIVO9PVnVL6odOti
zli7|#;kZmfXIgjJt8Gy5kX`bCB~RH^`ZC4|nf6QQdC9alA$d}Ekk%q^nO2J_IVFpo
zOEqdfGDnI)_{!{m0*s&Rb-D=ZFT1}UXs2Zfv9J^%%UlnQGqQ<TC<Mw1S^*OzJ3}{=
z&dPi!DR@p+xDulemX)jl@4RdY6(NMk!W+N~l||8XUy#lE2|itv?OhGYFj?kBihqX7
zrane9LZ+mhW2DTr6eEn1-J>NUTDCVAyck&-eSI`m=1I#|oNO5-6)(w7&@F~|+1|6@
zCCGl8iPmLVDy0ao$hg-*5@mn=0xyze8|ajORp$N#lF71PmSHT{WUXJ&^Oquvy9C8l
zS#LHp(qze$1xc4Bgu?uF*^67ynIY5d#w2FSB8vc%C0o)BUbbwAen~fE3>8R@Z2mKl
zo3ba*0G2DWPlnzt*`Kte+?ILKsXI^hv;-)3WRZnv<;y<X2{3DcEa!8e70T}J#9ZE$
zUHcooMY8A;DBhFJ&_d(BEd4S3E|w+oKuTm!RzRdwc8)STWwNu&fmSYCP5ZbC*<$(u
zKaicK|I|<^Tm2C*t7Mu!C_I$;6acJR7Vrx?Yh;7;7Ou6*Y?Xkilf6onm-Vvl84zuf
z+0mJ{S+;|AEiJOS^8wl_3#YVco2;CEvX5kIC}Z9(YxaVp9kL=SUF?+YqoUF-+4rqL
z>6V?MZF7%oMkjc^vO)TbJeK)<1Cc&iHC+^XBC}qjjc31XfCVoGWX*Im9+buX3^F7O
zjEBKt+4QR*BQl>{_&q9XqsZ1%*%3NTj>*InB_EfiT!P4iY!F{zn*B`H^bS0nl+8H+
z=qcI8=fJa-m-OHdV<+E{13i0rax*#|<PO#&XgbP2;6lSm{?!_29F@22f^W|9bgIsG
zkuRd-$uYSNEnBYgVI$mklYdzak>m2mZ1CLWz4R9KkbgOf@p{TDJ_k7=|Ao$!Uh)#k
zf}E7s&}Uz~<;7ISa!Q_41>z(B>qk2O`O2;IAq7AA6<TKf<yUA6bz1%bEq4L(>+}mg
zBe$osVW9ja%H{{jZRde^R?eXF#X0%VDRc(Q<M+d-^YVlK;DyNTX)h2ew`XI37vv)p
z?Y<~qMNfE`JTnht377NR>6;-D^0P~!7%AVt#UDLNK179B(enK-V1{Dk7Fso9<?W3y
zA1AlD2>na)a4JlSm*1Iy+X?dO7<%yJr}kn@SL7FcppYnkD;bzc@{Cr9T$Sh19xqv5
zLq~yY^6yRoB}KmSHM%pFDi5=PH)-<V)o?LgUN{G>>++U-pk>H)6z9s6f8Gp(S@OG!
z0Fy1Zr>c~ja_JciJ6HZk5KP>XoBBa+%YSZx_j&SnDM52bezO6X`SRsEfKnjeGao(`
z%G-YcxhwxE0bW>(<TicKxF^5(DfI8l-JS<2mMc48qC`GHzpGNYm7>RG@`V(uFPHzf
z3<?$UX^AlLK)#Kx23E>TMR2=H-t-c%AIektn38JwPKt`u$fG_$t5%-y9rWtthw0&{
zms@SYYp}{4=oj25j~z#ElYCf351xDz9dBCXFaCngR{7X!=(ow2odtO$ucBRLyZllk
zNQXSO4Wv`Pm)6cM`6JpMb<0`1(b*&ao}$jZ^5jhbdn|uf0@5dUp`Gdz`A&K@_sgvr
zb0ISzzd^6qLHUVl=nu(j`0!~MzkJNai2N#Th(_fv)A{15{99Tr$K=;(-#acpQV4|!
z`MN!5J(K^i4gOBbzxoTUDY+Nbc-ktOKLNCzB6a~f?G+d4`EyX5kAwwB#d}r?y*nww
zsMhPKLQG``&Wdd=_^Y`n1}Ob_OtJJc*mYF|_CwN5QFb4#<BA#Xz;;(Gvjduk;uG2$
zdn$I)N%4eYl8z8wib0AXoK)<j*qOItY!sNM6kDiL#z(P$-iE%4Sx+h6<fqtl8J7GN
zUG?~roK}QS05m|c;umO~Q9PxvaiD_9hGdXpcp5~`Dpt6GoKw6>-{%NceDn=`I<N3}
z0P`V=T1uIPDiZ49Q<x$S#UiuA6)RT4LWE*EB^4qSSEpf|Q40GF6#tA?ID11TMj@rG
zOswLs4KNs|2+xGZCB@<xXv8aaCBQ_2!jaDKmlf%=A#z3W9BrWz6^m$#o1_S%h2pBh
zCIcwRiU^8aTvO~k3|@+&pa_zwiZ{c+OH({Yi(k6p17tR>v#%=_ti{kW6u;A6FH_M%
zL6R&*mKf%<6?Z&AZYa!Jc#)%Uq!Ox|ifL8wB3JRnW{l#N;)8J5y{%Bzf|sYbN5`o<
z3gbHf%U3kfb>RYq3;jV06<>}*;jZFnEm}p2Oxh}1?<s!IgT{TucQlv93XfOecZp&r
z?b%8dUX;%+Q%ulB`EtcA21td%e*t(86eU?0MWte@5(-rc<@>PoQ1Q1dc-4yHUEtLy
z4$`Ait601OD0PZ0RB}?UC_~x7>;}c897AffDpcd3O^S3eyl7T<r9!4fF?tr3S{1wL
zxX`93-3<LlilDC`(ykcUiGg+~vM9&UsW6VhM3-XYGMMjH9HvuFkK!A8`}Zmeet<KN
z6}_Y2^(nrlwf>3X%NUS;#f~391{Bsqw8tD&oEQKZQvCE9$gm=t9+?qEFTG+%75y$i
zd#boex1YuoBRApNxI#At{Ru?^<<XxhRN1gJsd$Ylfu|IoY)7Z9(w!=M?37jw6zr8R
z(7NoPWKeCjqcU*?h?8=*wHizpWe$C9^_cPj<-uK*zf)zOn=<7j$Z_RPiq5+$-~S3N
z4`o?9M(C;RpkMb1C2t{2cq#vH7$PT?E?3a<R@PG;<te3(K33qP42lJ&uQD(Z{`x6T
z#z4<s8AvzCPAi4K)0_k-cV`3ij8btBBvAPuRbT}vcO(Pttg=;tU(z|{3W~G_E5D`F
z<ay;1DVzyWc6<$mP^A`?I<qe*>*)UKMdhMZup6fQY7biB%HtxmB9!m-Krd2xZ4>N9
zDLd$p6s;_YrTAxzGQ0~;#VWn302-%!lj`0sDU+Xr!Fc6{eCQ`AvuQ!TtmIyR;uU2n
zRR|<13n>qtq&!Bk#;eLpRM(NLTsH}@Ys$AcP)JcOro3*dvRDs=H09^Ck4sl>4?*j?
z@@W#i|1y+HdMjos$6f|ZmeTbjXk;sk_~^W$TsRZX<S3VCqjgicp28Bj%2P{#eM=cm
zN6g#Ga};9DQ+_Q1xue{A8QA&Cv^OA9psb+Hf1&d7pK$H2^4RZyE>f<p0`H#km6d2&
z?<->|mQ}1=-+}omQSMv|6Q#-)CJdG-b4Q_HuKb8ziWSOv2VmlXGJ*xgO69&gP^eOh
zSupreS+N5{t5!~{#Gj%@`8B;_Yn2cGM5|62TLMzAG&zDaD5JiIUZb*swggR9<)kyP
zo0TqO=xtHf(Y>iwrEN6Kw<-H62=z$WPQRp1<-Zpp(xp`AL!?{jk`B8)%4bXrtyg(T
z3!fe<z51Znr(E|Fu%9T`QKqq98B9mZ0p%>Z!!@XMh=Jaaa{Mo}hLzS&=sv-SGV5Ky
zj4HdNn3|``S7-w{rkuG9cE^=r9q61;zDHLio+(4VN9UxnDiVX4Qhqi84{cRp6c?~l
zEf+!0UUiHfUkBA&vA}dxy+TK6C)KwhP&lfJr+tyL%1C(!7uCDg9RNM1`r;;tt4jDY
zm~N_7>2UwJ>PrjUcUQ5WhY1f=|4RI|JyqYDVd8{pA01Y_RQ6P^a8mUy<^8=?`ePW=
zDOEV7o_$mwmqXoG_3P_^_EW_!2k}?!UXS6PR!ua+!vNLK*%b3TqdG&o{y<d-?G=Mm
zyl$YKReApg-Z|BX3NXPc$7o=mSIy{zeu(OT44t7WpAx`aP<hgs^rFgzwmD&{Eq7o(
zT($QFfJLZ!DY_7;vd;uBO65uqN3`lKdQxLl8<x@Y7pq!Jai2KVa@wO_Ql++n#H&8M
z2>k?A>m;x*tCkos&?_o=3P_^LE*oe`s(-0Y;i{_h|Dcep8a@H+YpOA-&`DACu7ZhF
z)m=(Prm6BN6P&IJ8^GjUS9R6F`wZ2;xH)H?ovB*32QXQx1llNMt70usyrJ3{1)p+M
z=T`vxrs_D|7|c~|q>q{1QthPE(QVZsiVo(fw$isX@2GarrKCdDv^i+qRSi(xT9K-b
zGVb?OT&f?tuj12Jkcw3)t6;B0wU(}uSW8v@XCYIjI!|Yaa+Nd1Un*1^wUBwBYHk5q
zrONGB46RBfG(qE`>S{4Mt5vRB;98C9`47RXRlTqgL#tE$P2XgyS2=P(8dNVT;Ao?&
z?oW)RN%bTMn9ZsNI!CprPO_obYE`{)0ibQFP^tiVr0V%UV7IGQ(We?ZRIkvcwo`R<
zK1i49A2*P0)t&1YT94{SI-2&XlBdJp$EqGXsQ0OSDfI9}RZGEwepT^0pbV%M(yBG6
zD!2~lAyq>cTEi;k-|%8YWj%ip`lBi~6}3H8*-@~4Ocg*f<Ek5_keN`e7z4~RRn9hG
zPpW2pjp>?FIeI|BR{dQ)T6XGaJzTR_JJ5mALA{wGypHMzLl~KpnnRnOqw1<Y5NGwz
z|H5q-b^B95A5)K5yJ65(eT32{Zt5+5XdPE?quWUC>Y4OT_E3K?7sONj-b|pKP`6%&
zB`<aIJfNLaGnN3&Tb)6JIi((sf~1c+oFcTo>exvr_^CZ;H|ei#Jp*!Dy|xs*0JWU<
z;%C(T4=Mi;s9sI6<RJC_VR&&?{plu{IH#T=1}|8>?G+64yqfhMOoXUsbV4#z{f8Wu
zE~q~}402Ju>l&O1Q-4b@<8XBg?XV-%!yAASsZOF-bCmj>hft4JpXY*HQHLFXLZbSs
z3p4TjC8@t|g{2gA2xTQw)fefvo~DjJ51CB$Q3`TosU4_DD_i{;Rk{_ZZK$~VuKIcU
z)Mb&nnz9P_)Su9=`@Z@<t!TySUq&#8CF;ZjP$*UJrlWM3I*Se@<?5RhP<x<Wzn%7<
zmFmnKjIc^Qjoyk6)i*LBQ>}JgfuC-TdYJ^Gb?UwOuvD*3sKvB3sKvK1v_|!3k6@`u
zT|=?p7B!oemR9wDMHow)dQ%v{9;uz*g+ja9NFT85P`^);*QsuZf<m{tls3`U9`)e=
zB7y3ED!_cKKJg`Hs83x<nbjxiYsJv-SLe}YdO+QO5io=5J$JzyQpZq0Z&<yPUIZg*
z`y)UbRr^qu>Z$qyZIs8<A_{CxsP}ve=x6HpDZe_Y9)25+PN{#K4i9au8rw~PvD0j&
zK!k&4TN8R6HJNm#b<!9p_I6YwNdj@!%<2W`G0mJ)(0A2*N&9U#&E6cej%(hb&n3ER
z^63EPp~<3yjHl*Zis^W1yeLO-QnPgkhP*XBE`UCzIY7yLAC0we7}Qtu1Jxd$)~uz{
z<p9lOG@Lo3>7gHDpk`w%ctM()QlOpH4AYk2yk-TJY=vm_pF<>66HaN9FirVZI1{cJ
zTnt`>X60#+Xw9A>7>v=d{&#6w^Mry>@tRq*N+)POveL2YvL=LTRgyHV6xhD1iFpQ@
zWKGsbXr*fIbpSg}b2|_|rE7AdftIQ1uY+Ee=I-b4K3lU)fYuGoTsp1iXr9o9=BDOb
z`o6|(&ErIL=4s|lqIE~Z{9o)%^IR363p9Q9R_GUMmTZUL_cUKq)zW=UCZ+R=HHWKV
zutf9f5|}U5)KaRUOtauSv>s@Vy#ZdO#*qTGRhmDtV4_CDR|2e7GddH_)M;|4f}>IM
zbSYX*ntN9u*{oquroKfpItTVzHCK00{;y5b(1B*J=BGi}eXL0xfNy;o9~#UP&AYTv
z^=oc@2Ht>Xh~mtHno24u8q$=|(PvoG@j0ezM8oNU$fzc21MEK4>^la`G0jujC5>w;
z!~mPnEUW-|rg2;d3zHhofAr1BDb0FU^xA5N12AoN+8Vk@V6T<Z7v&tZ(~khnQM>&Z
zM4YtCC}?+7`)o5howaoo26fSn(uVbzw%is2b=9se#1rGD?Z`pvxVC)?=H0a+>45go
zt|tqg+8{4<p428#y3^{d&2d2Uly;0V-#*$g3Mlw$-=&Xd_-S+Rf#<JXy$=RYYxgdK
zPXStI+7$+Achj-ztoF=4kaJpR+Cc?tw@m{%uRXCD>LJ?u58*|qw!9gZE@*$Gm+?jI
z<}ZO6rmcS;o#9rkk_wU|w6E^KC?d6m^i)P^lOr&t(b{Z!o5pHqYtb2}J$en~lJ=)w
zD8y^O9|LxR_N`kGxvX8J0$P&x8Pz9U)wZmMNV2wzN=vV4i`IdcqP;sEqfgbgP@*JF
zJL5lin69-RqK)Tut#cnnpP{X#A4aA&_j`~m?T4$Nk*!_#F-+XhzClOv9PNc{kX-G)
zeqiTm9Vp^?M|*&Z2J^N5J^*Ne_Er)U3bnz{(7LOwy$6LN?Z+Ho-qUXV9=!Y7Ya2m|
zwMVS9*DKK~o`X}R+R2rGDbxCW4N|VvTnDMpj{k^htI|rE;LJm9H+?&<TH8-C${OvU
z1#Z`B8|nMt4O&0iq%~@T=}p_DeYObZo3-E2OR+_};9Zz+)&BeiMB21#p9guQ-M`ri
zyY1R}Wzgu*S|~)@sV$!i>@KaN0Hj-+%K%J|Hkj7eUhSRF(D_8`v=+_`YA^q9FR%TC
z0+7Snd2Qg0XfvLN!l+h2uhys9JyfSRrv1|qym4(Yt;7@Buc+MMnKtzgdjCyo|D22F
zl=d|3%j|WZ9tUyIt#}B7j=J+yQQ@SkjDq4(-C;`JI_tP}HgwU|T?6Pb-EW~7p{tJn
zD>~hDoh$JxIj+n22Q7D<=>gPF=(yfc_tM$lgWD%{2dH$zTemQf>R(RjI_S!tk1m6v
zBmO$mX4pNgdy(GB0lG0)z?{)tSP1<<9oH3|K|0|{m<ZNwqR_*6T^7|2hUjFkU=X3Y
zz;YP8pi|Q%T+}_E1<Wv=kizQWy1h%F5TP6U9tx2<-UWbJqjd2p7;m)BNcSJE=rXoI
zCQ%pg2tFn0rqfUNs_uLGjzqF<@g<;L(`{}9c8cy?7xYqff6qWGO?L$0?%C<ON~+Vl
zu6xHHBtzFV3`a9{Uss`(rSq3TGF!KXehD{pEs+4rvFf&ei{6{MpMqf`S9dT8y|;7%
zig@1EX(;}gr_1{lmhR{Ra^PCN?iMZY1-d!D04>yg>krAhy4R@&ut>Me2}8T5(_I4Q
zecjvwbQbGgrUkV`=l&@yl<EQuFkhxSaSo#|*I6rnK(j)(w-(qBbkkSEQl)PDUJScR
zS62!14|M{1;H!1BDUe^IvwIsNwYpamp;xC%qf=SEE?y6j1|5q6O^v#r17N91H_QUB
zSyx42m=@h!It{k!j!+7zO?Ng0_8#e$TIYh<t`m>Jn-1OkmFVr%Inb5!F5PeoOmyqG
z6i@8Y?WGWFuWn!&T90*3RIbpcn@MkuC%SV7VYgp5MKvD-x;lz859+pVhr*C9nG1i1
zbvbu1T_ZYUC=^C@<+EVnsqS?KWoE~8E|kcArpp#WbW$f-ih)k)zP|>Zz5ZWXs2ucf
z8PIan&shlKq<3C`!5r1w(c<T<@5}_Ki=InKlw<lsi@<Z$S9(CtO+QTzk>mPCx*g}P
zH;;kmq2EOZFi-tYVtW6b(7#6MM=!m9Ff>l;_s;^;TVGCV(J4La2*&HDf0xqm{`%u3
zFn?N~_X!jN^zjw&_l*9JRG0|V<KGA4;n07sM(0`mJSy)vr(Z)yh+zF%3Vxl}Z=#B%
z5dFPy@Iv*iU(@q<LH{;oGcM{EegI~eK94rM;rhjk02-x#r4pji`WRZ5WAt_OONiBf
zybIG6r$0Cs3YYXlZ(-Q+`j(ZDOwb>r(z?s~ug*f`ihda#C=&I5Q#?IM|IvSFUDbb0
z7ip69q4a%k>ovV{HY}y+$7v^(s=q`to2GB4D1EwqMh&p9>tCgcrVRZZFAOGApGI%f
zEd43kh-K?%(50~(dh=cA<>(c?(7UN;2VtIa^?CH7zooxy3xl`yydTk-r_Z_olso#b
zqhL1Qsvp}5{Q~{^YcOA^&!l+ZUH!ZHXcg&?o1k$|??qek`+9Bx6pQt1qM=x#@1{%Q
zrF!8@kSx<XE(9spzfY&Z3Vp_#u=_xN=tGc7{qGbSs?xX7arvP>_)plY)_+gG)f&C^
z)_kDV>gQ9Yq)yME&{Vzt`xoFvgZ?;e>l*dDD9X^JFT4ta&H5MK!=JK6f5{cRR{i$<
z_#3qAf2GI2Lm$`x6P@}7EUdG;^zW=et6M)sdAJ_^T>4jcy?RgD%0Je-eFMEd{YvZG
zKzpLkpbb^Oes3yZ2J}CF0PI2i8Cs!+^cD)G4eMnAfEm#*ItRs3eG;Ymp6c~A@P16c
z_%!s!^%X;CP3Rrpg578Odvx1+Qs3tRx2N=bQbBADkLgmMox$h@v-XDPN37^|Fnse1
z3_2Q4QwfHXA!GquJZhLrH|U%VP4rbI7sL8B;2kskP2mt%Lpt4yaWkC#4dl4NxEBiU
z2FVJ5dKi56!@Q?q8=bsP7&cQqv6mreC+wayFc;xZ;cW<LN9QTSZ=sa`^D+ED`9EI+
zcR3XO3}sXv>2J`Ez~E_v>l~N}Fx;Yr;*4Qp5S@XB*}1?DGGtL<(pkeBtsv(N%|F9@
zupyPMW}G+F?gt4mtfH#sP{TutM}!$hY0DRG@TaFD!mzE8_Mef4-TTpuGW?~7OtfJW
zWzb>_>VF^_Yp}RsXmN(ms0#d&;h!8x#v8sphE{?hgBJA524fdGuNXopp_OPjy%Sy}
z89x37GkVpq=MXxR4ZA+V=&u?4_JfyVkWl_0)sRjTYfUrQZ^UGz8*<xV@VY_t1d17k
zj!f9iG+cik<IOT`{|i248_wK@<PF1GN~h--WcPu6)9~_Q@Nx|otI>JOU`r9E+Xm+w
zK*=+NZiT@+hI#~=X6GB!;Q%WzTwe~6LPH0g`R`f{i<g60WN2RojeCX;3SHbc?6g3p
z*l@NDtrEk5Bd}X)sHVhhnZb1tI?D}g5lDsMPYO~zFia&vq0-=A3umef)2V**p+P5w
ziE2Y6{d8&!3#qQR*6``in2S0?XBSAl!8$;hg9gI@m5enSPWr$^i(vz8#99saBVnS=
zFfKvoBSYXUjJMsebQL5!42EWab{anPgk+cDCCW{78(Lq7i5|oE^f%}=DCuPU*zg7w
zYxEh`;j}UPiDAbi9PKv*)B|(C@UE4fqd|k2jy^*MH>y?~HaO7|F=7a_2N^Z^Z->FB
z29G@;V}`hcfEhRF&!9D7*rbQZGlM;q_fHyn)8NIFA&Yidw#NL$@ZQe2Za!M}Mivzx
zIT-)`8G4S!Eo(rWj88+XU>-I8Kyfl><KcaPaWO9MgfqvC{)OPV8sDpcqMK1iC*0#k
z9+`JHc637D!&pSy4Nqh0J&gB+v4D~qUdFjs;nPWD4ZY#Ljp6MOIc2=`7QlRrz4jQO
zuaR#HFh670oAk{{f1@WY3a5>qtb$^Iab6PU>x^+Vm3IUhdue3~GD@kq<*bpx1?V~B
z*LwgHVr-!pOQ>-Po$)RhmGnalH@@KpgAvAA;gF0pmVE}j7~}Vcz>770^*Qw7jMlSI
zNH!*(qx%onj48(<lVbFwKwzrzclxqbnlbMK3_IPp=mT_KHyY`Mn_-+wZ^}$#B_*k|
zj8Sfo%r?F;50-8i!)$?)V^q$A$W3E6EsVLwO4`8PGCI+5>b5c78?NOU%O~K>9b@ww
z5V7VPPi_EAfpHea&I^q{P@(x<qs|=$i;QD*d-9&~8WW25jb}cEVzKdGN(Yn}<6nnf
zsc{Jt&XgIKQi)Bu@w*p+Qejk<qxHaO_YX*=@pZ~&RvEX`W!{HICl6p&8`Z?C@ou|q
zV|}z0HXDp1e_;fT#!YmtY%+fD1F>e~+mz*KF%|`))oL7|{dAkrZUDNEjH_C~Yd6Nz
zM!Lgzo#I!WM)8Z_bs6K*(CRi$EyLvW7*E$@R(g%~bZ_&qaoU?`^%-lZSmudwzV&@H
z`;CY8LUh0w)(`W8#`O)r9x{GNf7D^)E-uhUjCpaeG-~wIq4m`GGZpuZ85_c2aNKC}
z1er9((O!AV_);9OZA~TpkhC+s$AYB2>1rdu988O;q~Fn$Lv=Aurn-$3137B?-5#RO
zCcnd&co!3k){|o<Cwlj}nks96=4R^DLjSlagsv{So7j}$@-Qu@V~?jPkG2XYOlt$6
z?q%|&$oxsuo4zpNZK~e^$x|kEA|!oGmozZsYqF(EGCvdFpYGrVm<;ryIAfYcnYlny
zxehQvrf;ZD<*aEd6+@jfMR-Fb*pw`T`SYe(6qF7zEg_gtlYrvS7fee_;OIruJG0RW
zGldibCEOHm4-#Rr+=3U8rmiOdi!wz}xFXtg7Z1k9*)gVtlst$vJ--RqaV9QpEH9bf
zQo)&c(;6u>5=?27gS%|X@kQ&3$xO8diKdEmnAs$gxeKkUrq@nDFWK~h_nLf;b>|4M
z(oNxXRK0Hc`hCn#hUsSt;b)pshtZj3vZa%9wn<Hu3O7u%$3b#T`vU-S)3k$v_PM5{
zTR^#G%H041w@sgX3ODmi6J-33>AN2A@=X^gCt6_IxF2AJruXJT<gTgKN{ON((-_^B
zyJ!089(wPa)@+3NVpH!T45h@>se>1#ru|feTV@(w3z%|~-B%c2g=zf;pgl18?m=gz
z=}-DYRGAv+lNAq5wuiv0HqCeryc$ypy-8|KdGz4dnReYlXQS!NWy&lynetj;u-U|=
z0^b%>TPtK*P1C8)sm(MT1l}W)3l++@n^F!yq{B3y?q7787Lj_FsgE`x-KHEWC+#s!
zqd!Zp>6#Yv^w_k53hw$$TiD<|G5t&d!G6;e6~GLbn7q08RSlW~D}Xj+LS7k9kx58f
z-4WAjS`5cb3I9TW++?5}$AoDeMXH{eK68i2q^X_WoKvRL6uYoBzdZzEXMQyolJ@2-
zFX%a#*|a5bH1DS??@s337T7&%?g+-{oz2a77KO82%t3V7;g~s$LPf6T#S{c^Gk@j|
znd9a^ylo2?SRb09cfuTC4-_wRgAh;VN%I_6IOuJjMZ4fr=Fiun<zwbklG@iSnhym(
z^HEx){LM34;Mr+&?vFqYFxOJJ`HVUBSF{4nBeX09nFndHKWmPoed{^%*OXceHb3@9
z>%2L|N+r`F<{d8sG}Iil2O1a5%?@z)qB-?lpoN(~r(|=uc|AQ#5oS5nP(+%4o`U%(
z^Py?zj5eR6JKHhlX@8(I)?BIvcAVLd%7reO)4xG0-n^JD0wkD2??e5vSs{ny74wS=
ztY{{h+dc&|$@~e$z^<ByDW8^XHq614Tr<bhJ}||sr-VnU`QP8bOEYh!ikEcrbK`)y
zZr&dNUWWNNh0e3h6>kCahS_@?L~_hctDt_<Tr(dcxn>C!1KcvV&<)?)W}m&3e#|rf
zJOR)<W;I1q^Ubg4gA|w#QGG?Bd5t?v+%+$bf=H3sVGmmO%nCD1+&6o^3lqiWB|l<<
zO3bS$XH{zcncll)=DEK^vfNxx%V>qUpS~UPz?}0t%vYLUqrh~PdD<pQ|35UZrdLF@
zIrI!XtuaT01H0CIpc<fc<{T<Yt2Za#1a^bDfv$Nrnp>WSLX&yrD`+*FkA4B{7V}Ug
z6k5$YV?o-?tuMg*BXhS8Fx$<$pT~GR%pX02LZ^9!8VX(J4OFae?KV%*HmS!PHv!UX
z?#%@DV{=agn0@A-GC-b~$9Djx-y9f#U*Ldww>!w7`TRmy8Zr-*LvPsZ%>fxPD=NSn
zH9uGig{S60dTorEJ;Wg6<|P!poiJM|;rGle5deD9Y984Om?`t+#n7;|#L?f^&SFc;
zl)a^q{_B&2<tHk3bhMnHN7Ko&C=ixhEOx&@<d|jlIT&=cETxNkZkGRULGrl8iz4vu
z77g7)@UU3_Ld(<QPi1!}EbmZ>nV04DrBFC&v39IMueYVL5)*vNvXII<d@LJL7(Cn8
z@*{-+{4B9kApVxODByb9VoxhWfTf=fs%I?6x1cl7GCduwAWJpXhMu+59)?fnEX<Wa
z3AQZsz(CJi-u@YeLM;ANf*5L9PeI@d7L_#)E?%_w(a$T)vY4uN!z~RI@r<y1PnpI@
zi#Zy+D2oq$dnDSjfokevENf4}r&vqZ7|`M@l30jbvb-RMUcBYRCm;!y{9N!ZTUJn5
z{fZ^U41<Z5SqAu<Wch_EIIdcL+)S_jWQ%7zJiTUliz?kxEY3q1Osd6x9vn`yELa0x
zx@B=QTGuUA$>3#J{@?;F({hlG0$G-a-@|;iWqdV6Zdl4#P{^_TFb^U(E!&qtA=h$}
zQtY=Z`)5Jqw&er*tX`hQrHsO_cPte#kjb|kQv;^J@=F##3oYMmL+hT!P6LPUTUM7t
zq}b9$iJ=n9mjZ~CT4qyLugvo13P_e)HvA6k3X6v)2JyhMjNZ$YmP@(NtFmk-$%hu*
zY<N*^apOXv#`50^+WyvB((VAQ&f-A{@Oq2#U%)h2S}B&?Xz?h-D4HxmFJMf~mWJs7
zZLt(eV4~I1K=;eqEcvIQ{>bwG99?%@*46jV%ywy(E6Ykt+oe2v?>))Nc50~&%U@QG
zZ}upAh%9A^iXc-NvO$@G>?KQ40TGccTV%-ZefsOX&b{Y-&bjybjC;>H_wy{Ed`q{T
zj1u-ecD0nR?6u1cgui`u&KH5}w_8nBP6KxBv>F|>i%`QE+dVsm5UoRY`ws#?Y!^fE
zn-ROfuV8o7PPP!*#_WPA?mBMQPz2W|?7pE#;e9*77KlvR^|k}|z|QVpa8q^{-h@xn
zb|nIspRo&g3xHX>aasvHw7W+e#yPuZ|AfdvM!_t!9I`Rw=fOHKq;|kNGDcqnabg$(
zV9=TIC{4Z#BWWi*b!FTi1Hz5*Go2!KXN3O^5f8>kRNUgp@ZAgCVa7$O$MRx4Ux>aV
zjOG{^^k&@ihciA5c_N4}<6j8?evE(h(BjXq{kRA+#~DTnJ%ln=(w8z$FcwY2(n-c8
z3N4*tob&?;WBl_yL{2kaE5mrh8Ov!E7r}6&z0w&*=wfJ#WLUb<7sJ^2Ea0(>02M^y
z82$OMdzR7t417Ar@DBhWo{@D3B!O|w=7QElMiQkzk{G>I%5<KgqU}I3BXBnwQy6x%
zzDQ-LXep4!c!w6R>5Oi=x-%Gw7hocjv4$cwS&ZZ$aM_Gw^zggDaBPF*MaG|x0hh<<
zSqBgE8M<vC1q|<9AcYL;6)Jzb#4uA#xQG$G3{Dj@JT^ehWybpyMJi!DK}ncW#&wF$
zmoaWra-f`HZwFGrc!9Psm5ec*US3ee(9Qu+%~*3Dzd;S-(JSbyW!#a#d>v!j0QeQg
z_+IqYGeTq_O$@;Z9lvO1IBbT@RmP?7fVjp`Qmmr||F{Kh*BM(V7IlO1)&GIJ$w;MB
zRIQ9hb3ob{A)7FH?F`H3z};f3qng$Z#%?;5ew(q}5n4JKYtrHU9meb5gLE-cXEDyZ
z41GMD>1J&DfIk1!!*KfoqP+|o)syrwHVlL7XFR0c{s7|(2@rz}e1;5fC5DVj35OWV
zK8Cho#uF5|7-4h;KxC9r><#l{j4f2)FwXdjHn9_o2QR~!`;0#XxT&TXx9$Nq&Cr&C
z%rO34he6n88HsIRA2PI*S)F6JQNHC6^Ghl{c3`ff5&=i%XH<9U#Pp^g-I@9H80@+*
zmp%>7mHFylP~*n*q-dx+Gw6B1J(!(8gY#sH--F0urUz}>y_kFU!O<g3Sw1*#W-r2$
z3w&(MGI~k*GP|OH@MAJ)W$e#<oL0X_nbGvlIL5qBU&aYw9((~@AoFR8N(M1y6juml
z&RzvBgt_@EG#+PuzXV(;lP`wu6HMnmSUSl(PG34a#oT`dTo`i&72lp_&d@?EoM|hf
z>p6nCArR~tW)bZnBbhZ+vlYc`UJs?w%q2w_MGR9%i-@yKJG#ZsF}*rrKAyQ`75WmG
zJ1H2H$V@#8ToSYQbyzyjR2TqHX6~RUYzp(|M?q4V3uuFu#vGwXSvqsdb|2nkFefNa
zo5?)y0Kc=C_vnmL0n?8Pn+lnm=*e`6xrAPkMa*wj!hA8az6yPpnYl55momABF^6T$
zMU+4*XX<GOQNi?Vg-9i{@(+kqGvg`oP{ZU#qpy~k(ul@7<~WCPgjbl}^jkDA2PyZ|
z$n>L!XA|=-J;a)svj0K|%%#5qag7<&20#n*Odmw9GaDlza)bH(i-6x`e)Tm5(aLn(
z3%hO1uL?23cIFO$cz=sIW`>6y%<ELKa+_(Uh+`-7$Gdd@-C?#J#$0wWmry$IF0+=_
zdfm*oHiPsqSsS6Wm-*>QkUr)i9)SH!CKUq=Fek@gevs+viN<@(nR;+T%*E@#4Kvq2
zfX)%-&|fe=%KUZ>e!DSd9=ScvbfM+K1amo7IkpA&nLqy@e4Ao=&>`7r=6yPkI>T(5
zg!x$}gBGq2nVXluwK-;1EQWT7RZV#w2iDUR#&Kl*--l>)Vjb84;>@bIhcZ`I4i$p9
zu~I&Rd3RPQ{V*P^xHr+~$@*y+#EZ4;5c+IKSaluH=FR$q0&_mBkKaY7FYCvn(Cx>X
zd=U=&vo_NT>?rGn)gZ@MyC`}bz*@QmCIVUO>6<h`tShw54Q9RY1O^(yve6>^IO_z3
zSVLKl(%GUDti{`)>?A9PYBo->_R@<W%*J{*0_<s45)b%r)|d2#k6?ZNA-FTFomA%@
z$to;_!6;V12uL(*Go`F!SbP71NG$7YHN1~w4NzkCEGvEq$T`*@Ir#14StXQbO<<LK
zz{5mV*g9}YtaUr#MGDI;43eoV+wWZ%MH=f*igBj1mVE@jGg$dT;4@hZDGHm-8u|y^
z1=fdZkc+H~D<GM}`X805<g!#0m&<3J=moBTrKQiH6|&x@^Kh3~x?31w5o_}(L@u*j
z8ZojG)}a<SQ_6DBhDaG}tL;?)%USBD(OSX!fwE+kECoGLt5~b3Sh<>YupFd@<-Zcz
zYFYL_!9*P^<i9-+>u^3A>sbqQ(A~g#nN~uLtk}g+*2GHa$H<yl8(st8D(jX1iiKGV
z>9O9z>ZiTOb=JiRy8mvl9BKJ{ll3?gh*s9A#~{<jI!;$$JBv%XiCe7Yv_bA*9V&tD
z+pI^1Fs4q{p;0(`hsC6_tS;6FRfXMUZQBNsZq_0s_ZIZ9PJM~Se%5BHS|4DYxr_l0
zvVz%w-(v+Vq5E%$^^*=V!>oI>p&4bFqyUbweD!D?XL0!8CRk5>jS=2w9chK72dq#^
zc1^K9qN2lT*2<-DZHARag*vmWWV)N?Shs28c98Ai2)l>a^EZNXU<+FScVtWU!V4#M
zFcv1Z1<vd@D68PYmNB5sm2IFrfE#-uWenZfxhnwlU^l-7&Xc|L63Ah;CtZ(T>|ly$
zA7O8#tbjMWg1*$`!;Y-Nl=!kE7%<_-UKb73{_GW0GIEq%LwSH>?1c_!3}Amo;cZ(W
zdq#>04r06f1Vk{qNdkvM*ydN!d7OP^7r0P%1XZ4#V7t?9@FaW5W~e#E{y7A8!`M0n
zBu}&5Uk4Y??xZMSB)e}h08#85+9XA@Rg>^3h8?jL@K|>Je8A(_#?5FvYh!EaGfwgB
z5B5PcfxWu|t%+>UV%SY$t0*6Kp4~|ql4SM;ijStS-!2D9W5;|3Ksq~|wwM|0@=E*$
zne5Z^A(_Q)Kw@b@HhU>mIbL92dIT0OvXki%n!|pg8ozxm`xPo8$Ya|sQvFK-`@u3;
zDr65QfV;&0gHmTjY#F6=irIVU$k1hWHeDVi?B^E3d>Q-Vb~Ki=D>5Kb!G4#XK9y{5
z4op<BKWl)AYWBvLAyUJ(kcV~bjr40>VIQUXm3nsSLfC6y|7d#wGL7utUIV^~{bWCY
z&Fpu7gy=Q)5;|bg!j5Z#iR<jy)p)YqU~gQ2#+&R@?PzRgZ{Gxix7f)wfOoLNUcju~
zX1C=-cPD#ZI0kWt?M8dqF7|V@66$8}qT1{p_V={y>}4y;Y5&*9e)uP}^|Pa%gfj!|
z52*}hko_seGKbjFAHn@$cFg18M%cCQ0x-(9uL6FIt@i{s&d%_M?g{o_B(&UT3&vr7
zk{$LpxCd<6G59paZchPVhFz(~=x5nmZo}V)?42tq{W!;7bPOgAauQW&J;br6wT}bm
z_pc!8#QE(6v^jIu(Kl0EIOh{EdRI<01q9qU#-E|vofA3=oCoK~ao`SfDz<?0;)Du8
zj&L|{0N~Bh^@H=_lvCZBFQ@AOaDJRP=_9!Rj&gd#(RqwBnE|B%94=+v0y*EU0}0~n
zRbmv!IYSSjJCrjx4#^Xok{)m;ISdwDJH=T%4DZ7@?H^-;PIETW<~f4X^%b}?90r|0
zjpVE;M`IMHTM1k=$EyQcVmQ4kVb2!J$)R8SEGH%bGUqsZ9>U>x&QF7AOyD?EcrKBn
zr<ZCHC+{Zu&T}r)ZZMhiy$?tV=To|UQ#qn77+M-fLw7|6Cv+aX&*bpwA(X}0y$oJt
zbGBcBmJ6IVBYv%moMUwAD#yn0Splc=IPcRwET41W3y=bij-pS696NeRUE+i&z!h;0
z`ocspC-OQ-2`8=>jisE;w4^WNI8%haoU_&gq=K_74l`59+581WsyJoQAT^v7v{tL-
ztfp0P9cKkaW3F&)<|ee(bL5n;Y~p-%03&SXJW59_u5$cd0`MB=&?A`37S79+XuQrj
zNjt?G9CIN^D~Cl#Z`wFEnxJ;hVmhgNi}T)TnD5~HbO@?%b3XYRS~@waAE2*`^DW)}
zcR4m%Qg?IQY|Al2J)B>SK=g7Nrr=Z`=YTUvKj+#@usgsx^9JT?kn=kwx$klODfBSJ
zIY}9u5zZs@6dC0VmqBEVQ(6Eo#yJh2K=%aaxfKB1=k)N<H_7SW1n;Lf_Egj|&6y{G
z<P4|oS9<@=ay<7y^dYC=1^70{S@=1W9^}3s1>(THL>n4MZWxtUIdLaHfL&+qAN0ez
za0BQ`?8^OU9dK^k`kf#i+_xy#?aB522DroAb}Ccy;x4X--6LEhZ6SQQoj+m_eq64C
z?mvHSSs)Ncxxc-N&STuS7Qx{Fu7P9%xzktSVK8@9HMkINv@?_*=kB<NnF-}Ce;JJ@
zxVKHfo#ej!2*@e!GWw3@Y3>3$aN*p|^yY}*hN|G&8E*eccoE4>qtfmuZh7m|xc{QL
z3w_WT!##HwB$iuo8cO51e^WZ>EVqg3^5ePNG*FYkZJ{qAByvB!1AmjaN>`Bc+yNK#
zC371W!?hIdvI&?-<EG7nvUKhes({SkmQi*llN)^iZf9||LNs3F{<Q%(TMjqW9R_o`
zjx_-0ap%>7<a6U`OI*NxtqtZ2xld=Jv4}g53X_VtAE$u3%w2j5TnYEd4p=JXR(ykb
zD&v-wLU%cL(;D<ua%ZUepo+WrJ7}rq-VFg)!>v+7buBkXhsHV^H<lLvSGb;E!i#$D
z+f<a(z}-*r?MCj*chJ_v-M17XSGiTR61v76OM>neZq{~;={nbIAGF=zj#G8XP3~ux
z;Y=&{%R}gE=QcIK(OcX$I^f^IwWkH#ZSMbGh3Zc3n-na+%eDRc4_dpqkDNkl4>x;0
z4EAy#ABDj_?g|QI^m9G0fDCZorMUP#Zs8CBL)?E%Aj90vOVBsMeU=I`M!5}z5E<iY
zDQ7g!&80NqeXf9BIg?!ZQ|NoZ&8M?TQ``-;7{oL;)ke{)8Lp%Y!=B|fF`?}tcfSM3
z9M@q!WDfEo=(0S-D|W%?9eFaU@^In>Ek>g=uadHMF1(khT-}w&qy3v3@9#47x$~Z-
zz?LVk#t9;adABNH*NeA<7Gg(u*YAUP^VX%=Amhh7+6dO4r~e1sQJx<M<QQ+y8}KQB
z=kO;C2J-GahrtB#Z0}(dA-pHmnAzjJz@;Feyk}{1cY^l;CEic+(%SKhoZ`)+#a0;4
zw+gO>^PZ)JSOjnJdmv|cY>LiD@(#XA>(40OTU&sS=5@3JAH!QmYw=j#%4YzK<Ecu)
zo#lCdfWC9QDJmCA;8jlokjT@~@tP#w`UB8*o;O1az+~RHR5qT%Yo=I#DsTT83_G3o
z_rI8u44&UZkW5~bHvn0@UBR^f%jPA~V>*X-nW7`Pyc&8i=kb1_olHKjhN5N#yh+M;
z7xKi(P<n~?<PUJIi1!k0dy9F$(@U|0ckX?Nl=4^s@TrWqgYx9%ysn*aw1T(zC#bIC
z^-~0|n)lsa^wsbLxcwK{>Ue?l+P}hkeiPjQysNaGYvA=Y0nx~tPkG8Fp5!GoHuK)6
zE%h}XBNC*AcXSzW*Lm%4qVEQ;mCpa&<c-XSmR6pJ6YRF}Ui8EuZt;XKqOpUgp)=68
zdC$<FBy{qgdk?rfHeS(kuwA@)-@srG&y)U6wwGu0hqgZ6i=zPc^9Jl8I>1Y!J7<tr
z;0Vcky!~Q`4DsHkrQ$H}$~KTuUKxc!$9Upf@Nk^BnL=3;y#H-O<9*&^1JLq-=f;J-
zDPEW>8mD=-=vSa^mUos83q0hlpbK%17Z-@mgM7wO{4j_3Jrhvlz(24U6YR)m=%Cw~
zUoZ+u7yjq5;9U7fBmlVa-=|s;cYZ+&lzH$+s$t2KzvUX-_TsmH1IZ)&_AK;y^Ud`3
z_u=>0XlL!q-$L0NKmMQ@YL4;sA>ab|ANs<zKz_+#a6$ajv_=f(cT>negzr`f?l`~X
zdvKxrgu8I&1piVk;HUV{-^9#>@y~t^?lk`uT9}0MyT_p{f`7FigNWqsqo{Ed|L{4w
z|DyTNQJOTC-#}lih~u}>-(H;ME4<<NIsPnGX$#`{%-xVo;1_=bd?J6&2&L!wPi13-
z$^6Z9|D^CmKSCsxuckXSjsMb{@GzafJ^_sxd}R(Uq%8g%?bx#UGbMmu;2(X0j^AJ8
zzdH@l9RBYbwC3^;P#Um+ze)%-h5Vo2fHRl)%`9+5d^@_Giur%v0lCa?cpd(h@C~$<
zFXgwyLZpoU*KdHA^E=`|D)`v~^i}dL^k-&O{QCFdOf}!-D(0ewZ{1D%zgm78r4#D-
z3;sJW#h1_llY0L4NB|r7uRH*0<ga-F<SM^s4@Pl~-%1<%7QWgQlGphRs-?ZbFN}ow
zoBaE<S!v~e^$55&{(O2>wet^C(CilfO)f|WKV?1OxA}z!;GwOPZ=lEY9sYw&P}9Y~
zNR_~M`DeJW)Xf+Diz(^hw-!RAmw%Ts(0zQ5zk%=P&s&AYd;Gg{crnDUIt^}^pGL{_
z5q<)dgN^bJCBpm|U-JhBIL@!#0G$(j4_D~C&sWoebJE5S3kH3_UwRRUDZc$6yqM-+
zei>fO@Y7mAX8FnA0P&EY5)5vRznmuFprGz|C_N<D`8Vu32tHH5HAjKwXY{!Ul(gD$
z6@=4qXE(tSE8y;e(^*jMA=vi|h^OF1nuNmwTOZw(UV^)`AV&nLjnL*T@T1GqN3ijI
zsPPlX$QggZ1qvx26@0N0<e1>MZLky|;JyMAfr96*0T3kcqgZ3GpomsGAp$eSzK;w3
zxP!h>!HaYz|D>RXsz^@>$`v4Cf-)Pe;7$vEE(b7Nu!AaFA_O12g{$R^;N}I)Or$^>
zir*<pAbu1iS`fDZeKCSRlYxs9q|#>&&I&BFpgJe8dw?;;3pxW~DM9e979>%yoML`S
z0tZ_4pBJp7^l-A^m)GE7iom$WhSpR;-y&$s5d4o8mzjcnJji4T?)?B~vIWa1RC7Tf
zq6^}pK>P$6a|ESlfX@|-eF>5$(0&12zTmkpfh!OUK7+Ab5)7on-y*@_b~F|X-k1gM
zvcT;W`bq>5^sjuSg7Z7+^J`^-0WS=+T;TRA5EX(<Dm17RxY5D)DnV!r@HK+w*D&j~
zf|I$hR41sSn8Ovpfga%M1t>bkts*$^CrmU7E;j+tB=Di^XS2Yb68={O6WbwjO^`>c
zoa=%|=~uoX5I*r={!j2XU4gBF-{_Qgn;@GCx7!6P_rjT50-XV(9fD}uQr{Nbreds4
z!Q)hwc}LLl38uSSP(UX<dIZ~PN#83-r}S2zfJ@cq{eoT!&kYD1R$&eY1rxMNx+nPK
zA^<~zsCO|4?XV#IPv{;Id_?QlF@bG8WX1)b-+;ptf~Fr~;=VvTj=o7j0VTj62=1yt
zrUZ3yaCBO5Yc;gZ2=4m_53aOH-O%PBw0jF^M_~%pL^%n!QgF~&sEY(~5suSE;ws!s
zl{jv~2Q(w@!e=B<;vqbe3z5S@FM8y939V0KC`W{Obn3!ecw!C!AK?^zX~kFQLASJ@
z@Yqd^!C&}l5Xezsm(3A=9ut~^pe;Z+K?$8;p=Ttx5Mjt`7}#-P1to$*h0mP>IU)3<
zl+#I}+edKwl<+jYuET^M(uZeH3lr(V5-warnWqThf;V6yQs_jxp(x>FpF%QPXubzr
zj4+;J^RdE3Puc*C6K<d=*;(Nz3of1$IthS?7hVg7ngrpzWdJ4$qv#cNUbvAqH_5{7
zR9%!JbfC9bs!){%E=~9deTgGo7+(RA4B@=@;Ap1M>IR)z!jA@^Gh5h0Cy_4*chRmh
zN9gh=6?5ha-|B;<JmIISA(JnRp=ED@@P0NL3xyw2rR61I{}@aZ2|qszQY>6br{XRP
zFVkILB3!f|fO26JEwd|x!!H9@DO^N5_$uMkQixOwwQLxy5!PnHnOb2DEiLPWPc+kE
zhAYDJdBE2TH`43ALAZJhqD?}7s%2~z{!UAutHOVpq5GQ9o8BKS!oTl8<ht<s36LAY
zAO66U-V|zRyV@#TPRiPZ8|*O9cHvY8L^^~Q8_;-LI7xqb+$sE}8GUzz8agOz>k_V{
zr0ZSbf*G`S3zrqZQjgFt5!2l(l)enoCsaNUk$$1j86ty14&6ofgcE;4>5$N)2y-zk
zoa%*ZBf{k;Kt_daboy^hc$iKNj|-o97p_eR|NQ~*`@-~O049ZxZG`!0oA5q`nP-H3
z^pngAt3HIxLtzjF+2(}1%OQGDw8k9<4~fL&p@Zm!WDrMD|0&>|MA3A9&RHaI1;ADG
z7^UyrMA4nVxr?k+#O)y}h=8Q0sP;E_aagqVZ2-JP`+TAEh{(3f6)t*<4h*8xN3^#E
zx_w12nLzwSS$&W>Dys4W;+W{}FmwlqUL8SWpeXn+m<STJy#p>-w37^mh+azv?zre9
z0p>YWv?mriPl%?IFc+sp*30lBO!PPfv`&liz6BR9(%UF?6e04bV!Jb<4l2Ei6tRlY
z7$w?+r`>{R(d)DhixI86j|qwu&8K(MIZ-wRz~e<m+RrD5zN7GeqDZ+6l1U;DT2r1E
z?WNs$vgnIe;8H|I6e~*=Z94}pP4vlfXh|2zW~rDuQ<QW7_$<+?yCB)3EwmKBAX>B^
z_=_SAy*6`1v2-Qmiu!Hn%M-;>G%;Uv*$9ILq7izH6pH54=B7y0M5%#dQ9jkvUlxrY
z2PqMyQxdUMbf4buWg?&XFkddZT1~6D3eg7vP*W+o=>^d$kzyUjR4rmIfQees=TE`m
zI*~h-8C((BQ$DI*q+0-y22m5`DH}zLc0zZPX!$?T(kwbt0+FktRad}W6GhDfu0?dz
zfI-|8E!Mz%t7s1`JKIF#2u9i#bchb^N9S!3SAfxXiXNr8>=%X8;hF(a0d1oOMZFWS
zbWdbQA@d<om?yYl(T`NSJ|enNjq#3(W~c;jO!P1aCdNfesoG~k^il=5`yx9#h)jz5
z)}rx&sF61CQ=$Xs0Jlwx*3cVvMzmxJ?9Pf-Q7-bK=(8k{Inm2ZG#(V&{DC+m?y*7A
zL0mSAp*e~tsp!;6ymupfau&Zs={FZ~rUGMe74wh5pqqFDm5{oN<LDaq5C>2;%~Kpj
zUn@N<c3%leFPqpvX9<spYpA}#Tg;~ioR8Q@$y#6Woo+Pxi4XUJ^B4cS6MaX;dA|UE
zOdP!leF5T5x`G15Pc}eHkl0FT-C%Ls9*_|6%k(oJ7dO+RFjSoUI4;W*;xc-MofJ!+
zgUBhdjY;qDF!3N8qNl|%kD)bO98AT)5n_u0O3#R&G5`@Nt{#RLQQ{p`xfm_}iRuw!
z#M|D%l*EeP;DW@7FHq$CtoTie>YWoil|m$5yzM>U62$(8;C7;T54|^&#OLV}I4_Q|
zZNZO_EN=c8qABA02@p*c3+OvuX=1~2aOvVz6qw2o+c%>zQ~cQi0JFqvJK$QjcwZJo
zE{Fq@U@%uKw!qOmv1=7X^2N@yswxn#YlrGWF?$Rmm&8x{psz^$T^-=X;{Eq2a(-Ft
zNj38&;(L^uFBSi?1f6B#AE-dCT>M%-##A9Lp^L3jyo_SyRpJ)<_*1pm`841)Vs~1$
z)`}ZxOIRmn=D^V_;vlLmt`|>aKy`ySh%zyaVsjY0XcBu`;dZmQah(24?5a4NDm|}>
zlc^ZAMa-bG!s}u+U0yfDDkl1FiZ}cXrLE!-DyVJ~che@YUHl9EW8N+C=?R$V5N|1l
z(%WJ&Mcz8atNtr)6hC_qmq(Xaa1?!a#h!KGy2YixK}(M~<QMug>0WVHIR@G%{$n9J
z`^DA~Xd4hW{0%jO;=E&U=AL*fC8CDJRkz{Ou(*>})Fa~Ss{j}kPj3fcOq?_Wk#X^>
zvv71myfz;m-WL}=1YlBJ#D>8K;zk<al=vT7J5P%Xlo*+9M!fSHWM;(|&%%p`VlOIU
zn-dSLfzpE#8+|b1kR(3?A`X(I*C663382bqC&`Ytq10JoN81q>$v!H1a+SQ-0Nrkq
zBsMsA$=9>sJS5NT0p}^n-34-3@{}5lUXtV_IO=1Qh-kgwEBU~TRzFE&3C8O$S=kIr
zM<pn}z^x{UIflLf$+{MdDNyn{RjLF@R&@g(EV)MCU<;AVZwKJGWE(B=LM1Ay13n>X
zqx=4(<ZDVtosw*z8lEtT<yYuDEvft#qYszZoF0Li2#M!uh@O%37eXddvf2!pD9J__
zkZ8$cGI$sxSuey~#7eyA4;$hn3qAzytmH8l^qrHOp}LcJ$w&@F5+vGQaEX!|H0&e^
z<5iIJ62@|<PL}-kI{H#1b`IcDB~>;G1f)s!(k3Te(n$p?8Ilv^Q>H{j;o2-oJDr)x
zmK^yKb}vZYq|%9tlJ_YppCkE{-om+(TneY>Nw(5cuTYY32Y^eGAsGNgk}X=yOtB=I
z1A~_(FFRr`N+cF~W|vAVarE>mllYB6Te;*~C4d!@!F2#uO3EqVQYHB$AEMQgzB`!G
z8cA^w8fzs_ErYf?iHivE21!1>fEp!y6|^)-HhTcxEIC8Zz^jr-3d3KMtoR*Vi^PF8
zC)XwX6%e^0(QkYdQ*%=i=YM+YC0j=rRNs=+ghHf4QvM{!ZOL*y{Oyz&DZF$?GMNXF
zF3GGM@Vk=wGvK-*0_#1JEmSGlEBRFmLw%CRUPoWQq?$g}Iw1MQ4xSB4HhqIJ+>@-i
z0+As};vVQ6mQ>Ke!VyWCjjHKKC08j-G$#3@4>IGD*)Hgwko?pDa$mBOLMoGzP20ge
zkof!yktxZE7r;$Rir$C$8OcKUy<k@ISOZ4=P+|*&$eiR_GN$mLw8sys4@o^10pK9b
z`W1t4lwP1JJ141Oi4C33(wme4a*@_hrHHF^9~~lcljhKegWRQ!lu+@I=I?<Qp3;}X
z;rC(bLs}+yNgp1^(2hvkX+7jEwNR;(kF@z$5MQZVDf;}Rn<y9OFLnAqC_5^>Ap`E1
zv~E560;G2`X(tdUWzj1xNa{#xf~8q>ls7~=d>*35r8-KHg-Wv$;l&AQ<9tY-l+MsG
zol{aCm8*qGw+?`umgdmfAzXU<J9ro&?Tmm(l=L>;{n64^%7ny7<LQErmHN|Ri8$$t
zn`tL-Ryy}2?4Fb6&cQ^ybQ{(2CP+V{65~Xv^cjdINlVXwoR=nShSFr|q2Hk<McTd(
zT&nco1?Wzb{<|3Pbm<#);4-9JXy2A8EvKDqmUKluB(tSmXQAbS^f2Y{E=uPfhgn;W
zbQx_JbET%W5Y3bBKLRdax{l(N1=8OOFnfhkLp{hP>F(3eT_jyWXIhJ;uhN}zSt>jX
zH6_x1NA#6Sr|1(lWzzXnOI<EqLA6E|($ePuuau_Km+-5kG0y>BEuElguCYnqplEun
zRNn=eI_b$uAg)OB+u(4$bkq-X(IEYP2P`#8dua81Rl2PcCay_$Qe|3;^lwVOUzaX)
zN8b%;$E)CON}K2z(kcyYg-DxpDFsp5rHiN#{g$+dLVO)kSqCiKmf8aT0kBj09lcZU
zNMEG$Z(UM10~+s2zxW2ETe@{M=CVh+=^rTVm8Px%*C*voL0iAHq5viaqyxoh9F(%?
zZE{aKxCpw3q}OT5G%WSo4DUyz*|c^Tm8Mb+=$LexYR<={du)`Qosho7hxz-`rJgV`
zDP1yzDSaT7<^eG!<$j93X{jHj24<ve3Ixnbzn~9^Ka}o{g{3*^<5c#1Q1+n!eTQW3
zlumMxNoddEDEpSawC5!I^dOWu%U;p|;37LoDM(kD;~O?0++?HQ!LGaPY&c{*WFKzC
zZ{R6=f!->IWh>}wUS2Y1s!KQ`n{WcqTQ)@LBp+G&V*vQd`VT?UPo{hVIDgsibU_@I
zeMcLDW3vD4011$#(JA9VS=|V@Alb=Cz=LHgUZJ}35E+XecgJPJ68IJ>+pz{}PRM?u
zD!Y?1{)f<gO2(q3Ntmpm76wntI-UawmpK$dO@wTICi>3E8XN(Lls*4{Fdrq0qp*Lp
z%y<_hPWJJSFn?C|MLf83vLLE6i<kK#yoA3sm0jHo^NF$}Vvr=+EWP*6%cM!Ln=G5A
zY*vb_X$rtp*({}V(`55M07;jvEP}roGG~e|WXdW$;6;|~7piW^mc5h#Ef-`AUyzHk
zY&tHRBa6QQ3%N2^iWla|K2?C&@?|$ZLT7>OG#$$-lx_P9_)D_&a+oNRU2=lbV%e3|
z=({W%tA?c#*#UZbmCDX-g-Dr9-3vgu?2I>@sgP}a9RsbzjA9b1WM>CpqFVMhEtzU$
zl2SNRD+}9+A=SyUena0Co2;Jh`+C_F9S3WW-T4usjj|`>A=4y_rMGXh?Ate>^s4On
zCm?c7HnAQeH)MZn(0Eg}DiKOsWtXX>rA^jFNv(F7hVm1)WF8-abjSvthK1X*1B;-u
zQ}#*;;CE!pDZJYyvpLf0>aHwl6@cBc-&63z_Q-VI;Cf|($1$`%*|O(A`enPKpk_e!
z8m&7AWp4~Z_dQwl7XS>&D)&M6u<UCE$cU`h9d3`x0=@!nOqNL%yW_I8TQNZsvRCL;
zeqUCQ3A2;3Tw4oTAIMHpsANiJw;Qd~vTZ^jW@PVAV7#+3K9x^Clx=+m=I3Ppmkoml
z<+3Gk|Bzfq>pus%GwmK7<$t{ox1HoU$KaZ?Jc+{SF7ozAz`4rZ={@2m#~&c$PLuC@
z4*(DO+s?GN^OV<?K<0>ioHCi-^3uQHg^&D&Y~X$62CBUElXKR=8GreL3^X2<yRF2~
zj>*+J-~!|yP-#}6Jn=Fd4U+G%!nI&|DxD||kw?%#kIVPaTR2qi)Q-Lr@_}do!sNll
z^taxp<!hxd5iUPPX@>}TB-OW_k=s*nB2sQ00Ev=+-3-5@<&WM5iIKmb4{fpXHj2l^
z$;;`y!CCp&X^=c8e}PE6JSQ1_3Gy#Fa5Pb_I}3wJ^6srreO`Wm3onx8D_2uqGew^H
z0c29;dFKF3lec)onRNLdw=uK~xw8h1neqh6f@jGasPHgbzUm$fUXUN#0BslLD=D~<
zBcGsnT&`U47DV#o8{2@(m)9MINP+xwx~vN2rS!4VOY%(0%oWK$d=rhfV)@II%)Tst
ziz*LG<j+#oX{mez9djy^$6bKZa(VGaAS&d^w1KLWKd~EqRr1{{V4_-n{7v{<Bj52h
z##AT&sSzfw$oD-BQZN7dQ}i{+B@vKplz&VWgH7@Sdmz~?zf3uot2X&a2ee(2vne*y
zBHz;i6W8Up=>EGQZ=*=(P5EL1w#q+#6<)N-r|C*)mv>U&<F?#kGvJ-_b=M(zNA9mj
zW0yR$4)DA3Li$K}w_HyT-5z-uJw$rtU(#jSC$El%YyEQDN+yOqApeC*hX&<xF}Qnj
zw*bft$*V2UHY}IC4Q(Ux+jJq0%73+h8<SW31Ks2D6)NB+<O@;&xGxW;7{{dCdo7%K
zAZKgPHzjwWXvVaBpEH!r$dBiN%*qW{VCbRzXImrOpOaszh0=qHMJBj-NHIoP8V5xq
zEleC0Z*w5xgoh<KXN4~tN?jC->D#}qib9IsxG8+;n3KEWamt5!D8AhexToT!&tc-Q
zB8RF}y%bK5LF9;Hya8};#ZJmX`zStKPwP)##oH!0<)`S&g{Z&ck93fu3T8dXF+~M!
z0Rj}y&4bcF#S8QT3Q{DL0w1jCrAsJ8agw$(#}$hxFA}Qwa~gdo6d%$Fu9FH^DlR;w
z*xe7wFvUTNm7i8LP#iB@@!p5e;{J<J@TjKwjH2>UbVe#l3NU+7iikf!q7`b|7{n+(
zasVP$k?RZ+r|@(J;H<)%cIoF7k7NKBuh{kxMwp<ucm-UdqCOWSNwIGNBIgyy=}XVa
z3T_QXpQ3m`InPvu9``%`R!Y$(1)Hwurr>dg!m9!#Q&BSryIBejl@n$wd|!pg1w|yK
zIW8)6RJWX?IQShTa}{3n2+dO*+6X|t;>&z^QJ|<l1MdqJ*XUX;R>;o5nahfjKhRjB
z_=*BGrHTO)0JbtkTM9bM6+7o)qAC;#m(f|NxYCZ!Duq`z`l=OWS750|aXbkkwTj)e
zZ>v)jUxKA83gtoo>J_)Ifix&yTLae`70N0AniSJ3;BT`+(*?j)#fTI?%ryo72mG!r
ziZ!pJ@48KK?-!`Kp{S!n3^x_Kenw}jLP^W#HpQ1y0JbaMP{Wy9iigXfv_o;8_EWbN
z-f~EGD#90Hgm)AtCjjqK+@jmzu7djuoat8VdlBCEDB6=idKDkeL1&+0pdO@OvEje_
zPGPGHfto?Z6I8EqPvK0Fupz~g@1bp2(Lq<zh@y>x)}x96s%9KhSXV&XxZ<%ua1)B}
z_QBwNMGw_dPbylel;(kA`2u)2rFeWjluav2DM&t}__Ge&tYVy=0uL2S#n3sYIB5F`
zz=O(rtDy9d@@dK~I4B>b3(-;eVl9Z1@?(E^=&aPxM%6|6KJ9^Bm3I!ogq!j+dhNR_
zcYTXS52f=>G<qsG(fZ`D@~3wI_flrkZsUlOMTc>`l`sDv8hw;TKbZAZJ{fF-`+mwj
zd=P)-cP#uAN0oo6&>5iI_#v*@K;<Pf{0>rXqnj&Od0GJ7A<Bg%Ajg%(JJ1-a^rm90
z6Uw}3jOnD(n_l#%l+uT=6sENA2X|U|_B)VprK15N5y}cG+d88RaHPCuq_UI;7o(K%
zQLr1WJVWc(808iRI1{Vv_rkE_l$9FvomDbvUvf^VrDG}aN(OxbI6=u)VoDR0gKB6=
zQpQEXwe!lE&tM{1`G+0)Qj~9h54)*KI|{I-Dc`4%ce--=X^MnpC^yklK2v$35S>{{
zJ=N1@D~t9)%?0IyScqO!n#n|tas%zda+MPl%gs|p)3P~VxsC=}p!A`NsY2x*stvxR
zyzw~zMan&D_*<+jr2x-m<p~PMmnbi=04P<aQkd9Qt{kV*^$KMZ<!~yM?^24oO8H|i
z5Y@^jXwOrltjvMITIKF1;Y^*9K~)A<lp+xvtydP(57VG5+XTCf%9u$^Nt5yoy7Zcr
zwf_UTs{Hq3^j%Z7)Be0g8ArS3>&lnUq49=I8BGDIo60o-0JbXc(V59MWjuw@+Lca+
zVDOf5hY-W=Q1(!e@3yj@KFQmuv~EP-9pzryvveu9Q&R4(vW)5`yOqOl1Ky*2NR?8(
z%I#F@)Ti{OlvBU*$E7edpiHI6_n^{th<@06%8cJ&Vn}(#2SXcHey4_-5oID>>!Zq+
zdiXS^oD2qHTq)@XU_$9q1-ti^jjzI)N#*B1qwj(8n+Ir|Qf{Kf`?T@_Egoi+%wzCk
zR+;Auoe!0aUWm*oU$BF}2UQ)mZSdxh>H|9F;iP)`1Uz+C86#lOMRnva5LZ<;RRp-H
zu6_XGt~yBDNDtKmszCQt`O*1`!z$i!xb3CV{R{4h>KTfXd8-_0pY5aSqdkDHDmxe=
zeyVnFH2SN&X;pVrHOHh#*fCWXz0LwuYl9#Ys9H@WX+f%4+ByZRHq1dJL}hvd=8vn=
zn?XWV*Ju@dLgnFwzLToIX$f>nmHZHWVX8{Xrkz&3K`Yg8)i0NzEJF3yPne4{sxMR^
zk*ZY`{)tj`%%{56Xw@1X@G+`guJA2Z^~4sCIMtg{kh7{+(qSn<<xL+nO;pW&hY=>J
zMm1<Wuac3{WYssj;YErnnqsM`D*bVgG*u@Rp`@#J)`MiITIeFnRNX!YpR!bW^zh48
zec(x-6~CamOPPj?s%L0sb5z^!!&0v5saF8ZQ@N%>cfM-ZRx}o<9;Mr`P$i}^;7h8M
za^Q+odGt-cV%5r9nDxu5d23*zMD;x-$4XTjJi(QzPDKM=u1ck2Fcm5#735T^HtvFm
ztx7c`gNbU@M%qNzsEX2{rdCxIh|W6I8Cq{&QSC{C`}L~yN;Ed8M(G*Ys9H~H`zDp0
z0DaA>3nhSGRUM<3(>2w(=fJh7{wcu(U03}|LB1QRnDtP0Q{_*oiB{F3R48lvO!bm4
z5bdgO|AOc()v+fb)1i9oOElhA$!Y)BsoJ#(Chn-JJE62&C76L^kLs6wn66$`4^42N
z%9;YwuWI!H8Bn<dZdo{QwQW%+aHFahMKC|6ifBXMxGMcE{Dc##B~<KsUv-B{(I!>9
za-j2p%9X;)Q>yNzP(7_`qjmO-Dk~gXW>p7QqVJ)~kb}NCl^azm9#oG}KIxEp0TWZ`
zpl+aPc2sX&h>3Ah|7ptr&{_Qz&AN*^vJ0H6y88jtxT#;H^@+QBCDr43sP%MY#8W*&
z6)lI=bzT^?m%8Ug=su$MrG>J$`bAng1*yNNg56;CS{6u%dTSmekE@T-elb+tL`Swx
zsM9DRb5dRZ4&7U))SuCVElgeZ-|;o|7nG$9SHGKwz6f<Ir47%hXXZh7q}qiRa8c?W
zAM{15yOJ@A7<D4m6vwK^sKhBw{b)a&IjjE359FMBeFPfg)rToSo1otRF(eb!Gy6f3
z)YGZ-&5ZME@nNvZ>ZzZhG)2v)#Y3vPFBn{!Iw2C~)78(=+CM}6c^F8h+Pw-QS?Zmi
zVV<+qH!i}&1$7r~<1VUa>3y4{&iozbbJcznmdjHQ)uJ(9eTg2@1?pZ}YZa;2en#KS
zC{}N8M(btuTeNyEQNI=drKRd4wCgQX-^oH>x%#Rf`YP0wl<u!oJJH&*T0KkU2{q~n
zivHB9)s!o$Q$Isz_^zne_rpZJT1wm92K5fAdumh%Y=GNM>SY%}n$_&jF&5iZb>*8t
zTvL0~a=%60n1-wRx;pE5{02AFnN*S1raqPhHSOvF%A|Ivx$VH;R@)B4nND^6G(_&G
z7f}+vOZ^oEbMC4Ki=m}kJwV~<9`&|psP0v_QoT!`dU+?D=~rjd00(U9>I%pVs&lEd
z<(~Sh$H5J$-=*ipu=?FO$c(6q=?WfI>)!=8rrt$oa>mt<(;s|IsKe=y<bCzc$6;_%
z{fQ8+Jy74G0MnE@bqauK^;d&%bVl7yp^jO#9eo+-q52@D>*v(A=N6#zkmfg9I67!H
zmxFWEto<HdxM&_LfvBrSQH7zoX}GkOcGs+?fQ^SH^;cN()Lf_UL>$rFodUpHvzXHE
zKAI_7clv9t{Rp3qY8G@u<e27D9k>9^B>jYenk7qMK1kzl`wmkYtoe8yOoV70=<+(Q
z`RF(J9jduY>3|cOuigOuq~`f1h@8?Kq)c6y=EPBOr!~J*?OM3z!W)o`(5%w}en#`d
zvoH~<DS8R2qckOSk}z76OE2gc&7<EyS*)fh4d&xCCEYX&XEo2$ZsVM0bpo`-YnGgZ
z?gY&j6Tl~GD&B)LNt#=qLd|*21-es{H4;k1rf9~J!KG@P>C{4+rspY;bj|4=D9g~e
zE`YL3P5Qg|wX!tK{qQhblSFa&3mQHJZ!c<gd_<qi%F`UA;9|bUNDIdT&3CWDe4*yX
zCXh>-H?2@wq?t|uSFC9n#^^6=s@kEuMDr}A7)muibU~y{Gfm5?a*Z7=Gb%JYd_XES
z-EX3?N~7TeUai?z3A;6#PbqX=tNFs7atn2u?Ek}Hu4r6Cpu1ipn}O~I&29(GSEI)1
z41i6V#j)V7X~L<du|+en3nJGwH)wftL(@#PFgG<1n1Huxaz21an<i`$CfYSad`RBX
zxGn?NsR^Je#yc8C0w$qL(|#U}wtJcb??CsEW+{b3hBf#`I4*L{+mvh_*Stdy`w2}b
zee3wXX5cY2PHJ9qfSL!IwLI9J(Rdz!-C4~MDab>O+6cfQZA2kP@1RYV0^q3aqExYy
z_WPI6=d7LH31u$YCG?Q@v1!M&P~)pzL|>ls)4uRF%=>HI#^Lu-?eov!$2+EdyBH)u
zJCEW_fm#(Cz##1on%Q9OoC1;|+Lsz({<!uu?QBD}eYD*@p>19c?xZ$`rZP<X99<Wu
zwU!(B4Z^k0QOY(#Yuiip31_s!9GHmIHqrAYM(bVyZL!*mb?A%JZgqj^S#9BB4Cb8n
z8=9wh?P?QrCul$I!q5`6(pLdb(tbr>KRK`cnlj|c+E;SXm!jRR0GF!e{S7T?+P|D3
zlCB-0Fi3`WtL+`MW@;4-*u9|jMHTacT<y&kaCzF1uR!v(zU$Fgpv~V4u28Fe9HYOa
zT^|5aq<xag|BJOZgiv}}oBA<)D$&048X8Nr9U*YEOnbT+lI2=gTH01<&y~T^O6{&+
z0I1S#4WisawYKgvkQ!~*VOXlwMq9zvX=6HozoJd`0=`lEZ7Il2?ZyyHVyiYm3QKL;
z5Go#M*V@W3h+A6MalkvYo^+J2Q~OQ^$Q^Ce%K&s~v&qA|+Or&}?$&<v9!QV&uLJb{
z>(y?g<wl=Ye;tSc?Fz~R3~IMT!{K|{-)OZzq;;pc9M*b1fVL5Bt}_6m+EurpbWH0O
z4%f!DCr*Q#(5@Xq-+gUzC??^7HihoEDXoZJ64Tn@H1y4ApWOt1XSEw86x)2Ly+GgZ
zn$tc(<e*MRi?l<!-b#$#LFe!t@Q%8}sQ^0ZK5;{%vu@LRh`8vU9)?m^U0N)L?WQZD
ztIS;&a}|;vx;#0^5ncE<@WMy;G%XN(b+^940R42Sap?2cu}{LD?WnGMEn1K1Y*eif
zq-&jz+aXx@CgmSObc|o2`?&52%4vk^#wnk5LYMdt$Vr`;Vw<OQuh2~yrmNotE?hT6
zk=Y2{+7B^LXLO^KA&=CBIzuE%m%SH;qIECRM^s{TlOC`TYty|<`Q$jA^%U%$)g_C8
zIH$Y32x{VWcQ=D1>e!SePSQO}6MSCxTrAWi>n@~0X^M_d+o3ewKpuQb*M+_bE<;z|
z31ykO$9f==rF)k`cG<e>r5MWvotf<A=uT52DOYDp>xDOYI)M||e4QVCU8g{Ihd$6(
zsGIXZ-z8n7AC#8r-ux2yGMz^t`pR`{DeGCGQ&Uu<QfEgGziOS^WdLe)18+cCt?r2d
z^wsOyeF1OKc~f~%qwY2Zahh}sXc643d($=t;5FUb^|0Hb>!Q8;bzO%LYFc$q(w~X6
z>Av2N!L;iVUIXHm?iK~>I&>QPlHhHf%Vz*|>Yh3a$u6C-5R!Lw8@9k;x9;_&knGWU
zP*9~;H%5#0KHZzog7oWtSOR4Oy6U}DGd`#rO^2Fco%AM@j_B$qp=MOqNSmZF9n%B4
z$90eOp>IMLNt>KWor<zs4|MNsgzhQb_Rk<Pt=sWC8fSES4q$@jblyt=Kd9gS-{w{S
z?7L`m&>wJsPmcOW>6z`Mzk8CZj9m1}uc6dcU)l}gra$yNd~?@-@el|PeOoI;z4XBk
z;OG(ke9Dn~>wlxdV;}u+3q*YNt(2wm)0gpJ&|kloQf5c>PLDt`Q2+ZBbO!0)*bjKH
z{x)rSLiE$LeLJq7T~7Dk3H{;(AWrJ5+CWa}qbX8)TAxJWpK$%Nw7`$h*CoKGGx~6M
zD2>$Dt^z(vzv^quT8#ejPtX{vccZG}IQ=?$H=fn&=-|mYeZ;50#p^e6;aZ~py?5b7
zl71g4JFl;!MWroS|L-hDn4;Iye5LDCb3iimKYK$>re4Uz1ZU}gB#~@=*2lnK&>tYX
z7xml2;bD%xITIvT??~lAd3yc3u$!-MSp%O6^xxOOr$YUEwCcE|Pq_otMf#X|AjSGe
z=nE&8ZTdq$!bFMw_jaf$(@#DNr^@xE^ov&Le=)(+N_{!)ldJT?F{r85FKa<xjecb+
z@U?nh8vu3sbre*&q934o>3Y4Kg0KyGpKZ|DsDG1|<W2fzlpAQ)|GgjFRsB}l)?Cxu
z252MJqObcCYOd=K9fbQg^h<(3ZtCY#wQQR{gWeA9de<6^{+52{SLo}|n<<HMTR(pT
zEOqJ=hGG7WKK3~Jy7X=oI=HJ}?*<dy`olVq9{pcbD%Go(Q2L=y-$r|Ye*J}?7J?nn
zk4}IL>I*p__w=i2Nid{;;TQ%pqTfje97gp4^pY9V7yO03`+70uqbBt|6PS_*dL@<4
zPwAf$VT9BA74&$X(XY(Htj+2}D2(|~pAu+UHSZ-`<X>oXF#OO34;>ATbf-BPhSQ<U
z*^sP5ql=-NN+4VfDmpIiW~eJbpSxkR6~1^FQs_vWr$I>T-NS}H+JSo+tn(px#IT<d
z-rj~R+A8@NdZ?1Y*APkpbU(w>^m6bwJhag=^r%5arxuPG{#Xv(0ft?4@Hx=%7X8>k
zhLUl35o|bH4lcwHL#yuNh9BueL!pM<KVa5Q7#eucebP{M3L>Wr=NK>;X84K^5@A?H
zujDg^9iKvHq(MaS&M3o9iUCC%@GTdpi7{+{3No<<C;H9f46lC-zt0+iH=r@z5Khmq
z1jCmU0Z%lf&`u)7aNs=brW)LTf-`A`uuy18H{>wjXojJGA8?t5Z|cyOW!OZ!{A@#D
z1yo-!jFdz2qTvy`9&!x5zfw_gu3;b)Y@T7a3p(=+Vb?I20>hr`Fi~g-(P5%48ET?n
zx5!ZQJxH;kWfgvr%Z7ynC^6KD0WURtLYGXL;hi*)azpi6XsIwPrc18UaB2ixl_9<Z
zfNI0&dAL?%P~r85BVq>DADFf}L%khjt{8qe0IuH9N3+*p`1&p28x5b++O)~w5DC(3
zxIkO~s|H7^SiELPWkXww;a(BA>xRB0ICI1B=)V~DO~Wi*zpVxwEx~<bINk&c?FQZ!
z^xZOSrHrPn!|?tA$lNw;e;U4Z8g9M}-FFO&DPY-U2zna8yM~{3LA2Z8b`e~UK|{r|
zy#_amA@vy)Mo9J>F8mEG0|se7{2eqj&|Bf2;qd1$IAmy%pmEr+=vlZnVko0E%c$Xe
zF_ewj4Bm8XZrtz^)h16E>Yss{`-YFTFgRscM};oahH_d8%ox5Y0hu+tHVADG4e^_S
zn=?p0fr*30Uiu!?A!8gJ4RA1S*TF+a<HwXTb~0|F=aaKBb0s(z<MzMdwyV+X2uU}i
z?bWqtbvM3VfmRRW!gb(0jZahU(P5*P4aCbBwid1(F}Cjj!rS<YBfRi2x(vcYU*kWu
zu<K{MvjoK7_+2U_j~WZ(F~Va;9wki!jP>!53^b<D2Nr^i2UlZA!A2Xsw?d4*w$~wZ
z!dT-3OJPPP6;hlwa%nLeZuF<W@rW?~PEU_B#!@egBGR}e2PDe4fu45JMk&?V#2EKH
z38k?{J*AW5jJ6Pvv&L*W{5@yvqT4s#$ZLYz3C4>?C`&Zv90NSbxMmF<syT1`cOKYe
zWAe9<NioLJ_A%ACmD0Lt#%JiQpKe_CE*dk8h4hfmG<tiWG0PY~iJ@g1|2P4EFBpA!
z09-UCEe4lk^rEn7uJNQ0xIAOfd^F}8_tTk;0^|AhXe=}q^inG2lJWgV&{<^EP^nh2
z@ehhUUpBVUW4*-q=x=bi)VSdr47ALc@DcFk#?O{wgcZhg+7nh9Kk<P`l`;AT0M*9v
zQp|IW@mUK<t?|nvP+ezC`X5}oVr)AFK)rDr#X=j5u@X8W)@WQh51mcMJX+s38}}Ij
zylQOshtg}tk`~}wj32mSyw{B^Is({k{8Wv;4&z84e7bF1+k(DMBcI+zcZ~DzLQ9u%
z;t6nfjbGC;u-jPnBSzL^{9^@3uTirDb2wzQj=*2rh_U4p&{5-O6bK(P`cVGtzA>!{
zCMJ!k6!m>zbfp!=l(CVjl%|d6Lm@I_+(TuBv&QvB=zD0Kbpn|)PSbYxpec%`<d7+f
zw*C&LbP7&5n#ySH;ABc#gGOhQQ!5%>Y$m@MP*>9&Rin6>erCa8caw;=7apeHZ5W!T
z=@UvWA2yxUz!@)7BBdRUm<pZ&z}wWZ76yGxUmrxHujv&kOY$?Vqzl5|be$5wM@?a`
zqw$z&?l`mrn69hQ7-*Wb!kHkGE!hd3!KS<PW)CsB($J2Z)DG||)KruRgC|Uzl+b<B
z)J<wmnPL|}B+Rrh6pg1%Zxw=sn>zMGTZHM*f4dA*#24TqP4}q2Aj<Uo3lNDmb-#ed
z7*pLgsE#$=+JbS$nTBnCpl3}B%y9UeDVfe$#G8JlqbCWbGP<`DO?(p!CYgexfIn|a
zb3kLVX(6rnQcU-${wmcJo{zpXQ|SS4>86qyj4;FW3nh6oO%FbY7g?s~u0cz-Dd8|C
z;eu%(0)}!;SN=y&m^{-tZ*=CHR_maqz_i*Pq|n53!{{%WzAJ-Bk?A_^nu|>td(n5<
z^lcnQQDXYPc!-pm1aG0S%yjovG?tqx6X8XL>D7Z6S*0nH3h%2-&5f{7ZTjSUxLsp<
zUJl7x)8X&wJKA-oi}X>DE2ei(z_)tS93_$(OhtA;G@95?z;2VN>?NpaHtqcY<f_Sy
z&g@<@E&1=PzNxSaO0S!q=z-)7(^@`6Zkl)wfVY|==s;APX>=icYBvr11d&^&sr%^b
zFdaj>!?pk)7%70kPSac;WbT@-&@!~!)XacPkLhFFoC|tQ;S?wCGu@+&Ouy+TN=Xiw
z-uf8apy}!+h}<(VN-!5grU%!+4VyCl1UF(jcMy`Jra!3`X3QjM0$|+awhw(1rs>z9
z({|rfLthx0H0}Kuq7O_jP{se0=}(G1Pn%YK2+<i+Y$lY>njWWZ+(XlH+SbgOzMw_$
zL9><#HHXYUSEJFv{LV&jj%HRZCf~{Y=SFC8HhYagi;Foo5?;8PAFD#6o7v?dh`Y_a
zA`(hH%z>06@HDTdc<o{HBe_uHW$vO9h9l;ATfljnpI8jMkNMwZSn@UZT?XFIyp7^E
z{^rZCqVcHN_yo9P=J%Dr1(?<Apfkw)M=jvNX0;XY5c4uU`i`6bpbciI+4l1V&=cmJ
z^ol-duGossQ)b&8Ai~Vul%+jwexIf^+&sSljS=R!AvB&b@1XElq?tiUrYQ4`pFpC`
zTKZZ<jQJlIh{T$st^;t+Z2J;+<IQnFFqB}9&4h=E=2Ux#B$@kdtI>JhJVM6+lFfcp
z4w+)!Pi0`K=0$|hFsJzem}%Zuhrwi-17{$4(Hum($Q-j@8C=UXpW&k~&-^7_$NA<w
z`oEq6^R^to3(Y^eK<6d%k|OjKnRnBNS&GeDe}Twlb7%k^swpvVx`ok~n%(KSUS^(K
z2hnn~n(7)V%whLHD$SedoKcneZCcS+n}<5!MU6R^KEzgQZliCw*O`ygyY-6s9g0@f
zn};m0+hDF82iIu!OoD|b^ON*wXg2#$!1Aj3#y|9lkZb0aB(N>!XD1<Z-R$;1kQ?US
zFc`dPj=KZWYF@Ai^VDW;q}^P*Svv>2x6B{91J_~pFGb^R^Lis@t<%h>V+(i8xxO&p
zWez?D_+7J_5|iC##ShTZW8O~V>@|PDr&MO2Iq(e_>^B>!tZBe(myHn)nrBu4anD@;
zJ0@|+e11R3uzATU;781_a$$bdJoY{$$IL?%y&X4mC=4=TcKjc3_sugtusdlsxC8gV
zyo#cNQ)a&e7@9VV9nm*q&ZmpiHfuIfYVo1Df%aH)=6EmocF^+jBT(aL`DYS9C(F)y
z5NFHgP~crGcDo_zYSAtQakK1w6Qg&xq)?j1!}3oDI8Vz2J?9Qv9LB(TSqy3@J7U?!
zMWeT+m=;++7WHxvUz=s57Oj4k*C@&CZ;2R#iK7<hW%$*OSzIY_8DQB>OTIwM|L9p1
zWO<6xj=`2sj)DuZT%kwdam&m3XbiR7dJMP|78C8SPg>rld-Ig#BYM?^Stcp3dfF1S
z86x49$k(7V!eaX=73R-ay6CQow9Jh{X_Uo8Ih<%qJuPKoEU|My#9DrGLf<({?o9yV
zE&Nc-Y=XswqI-#!-znpkWEl*C$azbm5ayFDiInwBu{<0GmugXdfJsQVtPMwFhUI4;
zxRz<TV%r8_mL-ddU$ZSYx`4lEIsFkDb1a=LK;&AUEQR?z%e=4Amv50(09arNrl?bq
z<pata7F#rJP<q*NmCkmTSPaSFN-cR*=~ZS~{ombWd7N(83XA$r_*-ci+J%u-S$@f~
z0bgzL*TTgbOR@#PTFVD?AJkc5r9fP<G!8*cy`_jks|^;{`LNq)*&Ye5$>P5Rt~Fb{
zC{KCSvXBaKuUSUuBuI<J`4cF+ZVC7neK#ywQ^4J{tp6I`w^{}$dD&*EewIE%&~A~?
zIgMMEeSvi!U`Jk62}HN0>;~-iSn67V=(RMmV6e~f2L&GcEv=Mq9I#yCfE%>@a0_<t
zS$?OC+mPi~+OG~<e5*0g5lj3tn96a>!fc34Si(A??7k(G?$k+33J>rHmL?kYl*RiD
zB&RL+Y~dLFj3tB0L1rz#e+=M5%Ze1ZKW8ygEa{+id=)qc>x0EG=xEKSyq}Y`P6(fz
zt>rrbaIs$YhY45f?j)G-v98?=;%gPHfry`V->(qyw+3~<;8APTZJ0l1?WC&UAZue6
zJrRSg`{x4@Vht>UGsmr;+QDF`b<>{^Jz@Po2=1iyd8&#$Wo7L}W0>_%N-dtY?x(kZ
zxK;81T!eKORp6enGU#kUr1h5>G)7r7DHW4sEnWuPdF!YF7E-K>`Z1PNYh4H>z|yQ7
z+C8UR2Pw#rVXYH^WLoe14bd#?ytkk<+bSBsC@xr^r%2dE>%nA*<XGdWP$t(}Y=KCg
z_1zUvns5Ez3y>_ZuA%5_p*8Toe1%m@yNn`h$YYq2VrxFFJuX|D&pwGKVu|(hbzn=a
zJIHRCb<HCfQ@Pa;2z-V0w|hWTT302*Zk4raF?3g3k5NLm#`+;`;cKmL{RrK4*0tp5
z73;S7@S@&YK~LERe0BlwM(fX%<7%?5CTE(huYHcjt5$c~-Po>Kzo(*<7OQ~{x?Z=g
zp~!Bl)sNP5ZPuI1(AaJrj{~`7y>S8f4lCmXT)S;u`3gv<we=<%?^tb=Detl_J&eY?
z)<v<HnQm(@Ez)|dEXoV@TJ!0nIDOW#r_k4L4Ze&YX253MM4zA-w2s__!F$$UsK#-~
zT1(l>Ve1duz>QcVB)B?9t*xmL8MCgPgVJ$~0`5;(->3ckeQSIq`X;Sin}B;@?O_2h
zWgYIrluTRSrcJ|)wJQkbXRV_5(D%^Fp-sb_)#gf9;6eLps=7O5|4JS>2m7DHA>(LY
zLRls!`?Yasbhh`QY7!UwRUViNSNl&Z(dc1+hCW>7X)hRr7l-XfT!8bkk1GQ1i2cqw
z^m*Igpl!O3{YN)p(APeLqNjfLI@+=M+ZWl~fH-Qubvs&*+2>OAT7bPTnGdwry$2IP
z_IIh2A=p0g7YruE{_Rfm9k;)x1_`xiy#o^`>_4WekdyX#3`m}`e}gi8VfO0(a@6*Z
z6hS21eqtk(Mc7AN2kwmh9EGGJ?KjP{fsL}CZiK_p_J?CI-7)q}bUrKAeuV(QIQu{k
z_;l9(t<TVS&i+Y?uE*PV(?c`CzF-A@yF~kWSD`z}p4$ZT=k5I|JC$r7lZM6=`&n8N
zq}u!SgQVG4QbH%)zLa(Z8TRk1|DU5PkE^oi!fsTqEoz!&mMvPJnOWMdS!tPB#@+XQ
z->*wq=2cO4P(WElKvn?-1w;@;L{PvTQDjHikwrij0sWrSU*|V7=RD`k-1nV#=A1Kg
z>HRz7{MI~3WI2C9wb{<oKZ0#%om)Fm%5k1Yi?m$lE7X~D&QA2B=Q#`d0dwB@t{%qZ
zJ8S8v=LP4V7eal3^B1(>z3ALXH?b5tPo))Kk#pCdK)K}X9s-uj&ac=|Dt12maLTwv
zP9@G~s)1JOeEC;kUvakncfXRel9tamoCC=BR_5FgwEI&`*6*x^{9R`eo#U)<UPS@j
zd(NL4Ay?^KI|-#K=ekU&uXbjTH?zih&KrQPb^c-mEOpL9qbSuo+h4{|HaI_{FZ+FG
zw<K^raCRftXrpuf2T<GOZ1@w_H#={np=@!^n1{}{I(s;1P2A?ZZzm+$od-)mI-L7x
zvGve-c^iI_PUktd0n_EYe-cXF&LebZQ;%~8T|o25`Ev;>d!0Y|5f=72|4Q>rzw@jf
zXnO2?iT+=9z<GHtN`uZPC%}p!=U2$fJnSsdLhgz4q|a&lIO1GMuF6qoI|DFd&TMiU
zJ#~IK3M-yDucuw;E=DkAPVHtK>4M#R7#i|f?_(VK45qm<%xgj180H<|bZ2-yL7NAI
zQwZY8XyT#Lhw;q<==EhV>3HLQ#v5}W;LmveCPhmF7%#2_>p{jJat!Gq#+f^43}hsJ
z1=b*j|2?#YGPJb94P)&20BwgETb=?moUx4@k4G3cDcc}|!Qwz5k}-j{5K)XQI`43l
zaS;(2r)b6kdKqIFQ^{8l%gFc(EO87MHDxQrGrTD#pTNlf2QbGNHI#vy$Pi00BuR{%
zxnNCZy!tE5KhE%^8&*y*wDeM?FfP);s8q&^&rx}j5wsc#PcbINf}}CN>Vh%p3@;N%
z2IIx0c*ssO<n$9}GLq=Kd4{ozd{B-o#_B`h$!3Jp>g+5dg8bq+jHR?B&t)8?JhyX<
z?-rmkkMSa%T0hSioe7f9SeyrYFEF<2KnfV{G<#fRyiapjA*1aqDvKB=--2nE7*pRt
zmo76F(@a{-_?SK*B@FpKXef0sx@fk%!sr@<`l}32%2K+<SVFJEb%x(NDBWPpql-0f
zG9o4c^cI8Ng0?co)I%uUX3U{gPB~-!M0D*A;}`NF-(~Dt1{D<yc_Z5HF^0%bT*+8S
zPhb^;^8&1>W+c*!Uc<miRM=h5uu_Iv17kB~cid-e_zHp#81uh`L?a_M0MA?#!*2j%
z(ae}T8)MPJ_?~`>Rz?M3w=sOjfYQ!zyACTl7!ET89x_U4E8WRZZUa~sW8D>ibu)e=
z7j_ThA*HQ7VhA1E(feLTUoS`><9o`?>1S*rzuaSn$06_xFmfpjH^|t`gWwS3tw-qn
zFe8KV+Mh74hC<;8!%V5`ql_#{wHjkwpl9_dBd;25&lm-?*xAJ#c7jd2nfK;{a}V<h
zMa*27ywemd-OK!zJ_P%i;}=4OEAtK73%fDzO$M4f^A<fx9?bo8p_wPsT!=O=rtEvz
z<ju5^N6Ux#(LNAg=HghW*w2iiNcRC|-b;}4V|t{b<j-8Y0Ez;ba&n^_WLD(^>=4uV
z0&O1ynGxf_8pPy0gTi3uoPS_U2=jN^5ri`1R>Gz*rkD;P9cI2xpRsUe#1@o}Fhgd7
zC4#A<H1kL%lm3n=is{k-fuqb>r-2g945tWR95aO+81c;b*TIs&9HM1@60^3P-oIq#
zpG&}VoN1srFqNsIkNHXFXgcgZ#r%uBziG?{+DxW1Su~|(FxQc<{tR>5r|3l%lN|<<
z&78gv3ePgNw9L<8?q7}m<}$}<#dnT*ff7#gm@iX+|2%W@e1PRMuNYyr;{r2uCk!rN
zZe9!4i%c`cc?y}Xw3jVnE}4&!xy1A*&+cVr4<%9*GXp;cDPeAChI}dW6MBNKFhAW7
zg;$w;id$S`I?-*a*O?w$(RPEG-jCkjWS$y<-doHK%V9+svu!&Jz3pH&SD>++nMqEw
zJIsH`i*uKmz8j4d%x!dv=pHkNwjh<v-BV#`6|;s6t!B<CfLsl;oC3(T%%3T@vW~fY
z0@~`C&&Q+f0rO-X1R9xM^f7E=7A^x=Gjl!tmp}_M|2!;gWja2l9Z(xHm@c+xXL865
z+QCeuz~4jW)sIl>WTqYh>0*|CkFIqy#Ty{d!_?e?y^omZE<kTDvn&>x`k2Y&c<g6J
zEdb|ZCWG1rm>x9g4l=g|qxVD1zr+w9W_D42>l5ZO$5S+pFtZXd&ZErT%R$DN@ho6J
zWvVCvYd32=MS1tIRz3uAVMViGnk#D;oyl`!wFm&}&g!RRG7pyd6JUF?7E*-Xixv4k
z#JyR?cR_quLdwzdWkt>e+0U~45B45lE&4AL-H#>u8AX3qk{5pF09Fj0mpI58+W<|6
zSiej`TOjKk9YqXc&ASW|%wo_K9>Pj>2MJ|e`W%(vtSb~5J;IV^q1zEGF+C8GtVOgd
zi(;jaH}fd#?TzSQG;31?ER10#iz!<nmh~LDXyRD4pP+~FtVOfHlfbgJ0p=KM-Pfp0
zWWDtr<dax#sUXQLcUpKJXI0Pw?gXof;s7Zu#0K#Gu-N-y%t_WPe~ip2Rt_blq_Hft
zTu*12_JAdW6?zwPr&(A>;r+{GEvJp&8CKPG)Ml}!Q+9DSYug_5{wyn-f?YYRGnB!b
z%lfzwEazDNz6|wwthMb>ah^4q9^`yhOaVG^fi;V!jRMw<ETCLuW&QwC$T~|qy&~2=
zcNlYtwd4Uxmsz4gfH{g;+ed+2!kR}%iLbKk<hH%RnnTCnZnBg(Ear5J)kR-`G8Sha
z1aGs%e?mn$%Vb049o9t}uDdMudQ?`his;*Tj}`YL+NxQ9&=RJG^}G!otYz({;AtHz
z_)ApQvz*9B(coYmKLytNELVzNK47I#kgSn)*a@X3)*F}6(N>l#eU92#M`&5s&YD0!
zb0;h8Q;;rJ2&H;-v!ZEg>1C<O0pG`p`T(S#_2+kB8DxFd4$L9er?Y`F%sN4CqfyrU
zD`*>IIflql^pv$I0h)HRm%E^G5BvCS80^9>o`RAq`&(MRy0PaLqNDEYn{^mcFLpUO
zue{l}=%kMi`>)ra@Bo`r4irCj_F5?PXUG4HwnOX-lwBCe{$Lfrg4hz8Y(v?tbY3=$
zt#<qf?8EGv6oQIifARuIBzrwQJ5lVitzeB|575#&mK{Yw>Ns}Ui|EBM_BU@pK9QXs
zg~}xMT1vJ(!QS!;#v+B?c?PDXvcIIDdK$YT6*i@_hrR(y2D?HHfivuwSJ9Tm_E}Bg
z`)u~xGtijJ*8I2mW)GeKS{^&311c`CPi3N1!2Xhg@)y}cTJl|Dx0+$vWws>_#uT$d
zDadt&&0Gcb<?MecqH~9x{RS}avWIEUQo-gYK<*xUZ5mjr+0AmOtzoBpL?@AJ+0!Z@
zQOD*`Fr=QHZGgcI>?3nw>3#MK*HL=Fo<oa>Mt1LQ$TzX|@lfB)u8c&fg<VXct2VZ*
z4W)MW{y)Ll!S1p^??ZMHxs*EDx@!RIW^b3F6FuxTl(O-NZF)w|f?jq`CnWmVulS<2
zpMCOo2oAE}piR~gJLM%*4zp*|&U%!+`5ZXM*hL9Y_>`SYtIA!R^N+!@o0CHxggu-a
zyJ3Y3r+7Wu_Ht%Yq|lY~E`2`TIKR+$-kmeeh%R|>rsV<5;mK*yp)+2bF!DZmbAAei
z!9JW%KZU$6=K!TV?&mCR206g#+zfd?PU#A;_;WsEKvMvxR0_F+9LySc*f=I++d2hu
z{;q)DAkHm!kYLUfdb&b5--uv#C@07joZ+0~^voP_aH1xnqY<2~6!198>HGpb(VT@V
zAQ;0*6vNVZ&Uq0)6F4UypzRoE>v^ChbA0Hq*Ky7ya?PIL<V(<rlblr?n0<<q*NC<>
z&I59mpXO|&Jp4?~{{%oe!+CNa0%tj2l0Pqp<7hesiCoVA-UQEiPIo<w%IEyD8^&DV
zY;i-^3OR3G1$GffNALY5PS_jZyvzxu{{%1QjLbk~3CE9K-%`%2^f+JPEO-q9S2>UJ
zq3IguG^K`K=X|mrU^h5rCRlNc6XSulGR|9$A0T*}vy-wO$~ihpr@X^CLY~sQoMRdY
zR&c!I!CJ}LL0-iw&R26FU(I<l5@S)rxla*}TF&_SFs6?4fL^0|PAo+z8#pt5hcWj#
z(Szvd1I}BY0lJa1kGk8$kw$>Da;7gKgWEV;w?VL-b6_93-O2gQ482{P4`>n4&B<8`
z6+N8fzoGXLhqD@_mt&_Cq(08_A0XGy3Hkym9&=V~M&$tK9m>!d<b1CI8RD!=0vYDi
zZbz4%aAt<1G{X7(6{sEM9Gpovag1?}kHEI49L7zMXPn;6=-Mu>(>|!*&5e2ipnJHV
zRH4m<+fDJXz1&f{X>T95iIPiPxwC|5bK^$N2dF#uP5OO2xIf2()05jOfrVb&S=kWq
z=7v(zo)0&jBJ{poBR*;lr~TaVG+!Oy=1)LJ{kYw$VWL0Rv=T!az@6~~{XNJXy8($q
z+<wYf3FN+X5->sBeH2U#=El7a6(QUriU5aly@#MTjH@K?-eGRxJ_v+!J?Z;(gquns
z_6Y86dT%4Syc<yKh~n<}1&v3!13Lg3&E?V7Hir9JB^qP7PV~&iah=>i;<>&es7T=I
z$Ps^x`?W7dJ&`;AC=@1fkI{xEnfv}il#X+w*$_X$P0t5(3U>+}jZNk1=sSOs`;Q(d
zr?{T<0ZDUkpQ9~TI`?Eb8Z)^&>(Qq(+}IM3EUxe>c(S=!l;L)k8`1&ubGUE(3$$Er
z-E+V`$4&eW9nIs8vC*gV+%*runa_O|2751Xzo7kY0rz_;N*B3XXM&}WTh<JeB5u?G
z#4mB@*HU8BW$tqF0u^(EmjSJW`@9OqlyY-}UR*o=b;nh@*5?MdLJ#?y+#YfU-QqT7
zLQ@%cjS1bp%?+k4S2?$S43&4dwY0Up%ME!8r3$W%9)Ww@J2WJf+_`jOw2Ip{4K`JC
zxm#gH4c8I??e*MefnaIi@+hQnpBqR!m<QZf923yk$bE@&Nt?K-6{v+zat(}W;Tl<B
zZRN`TKwBI4<X)h)bIWg`vV$AF1(grEQ4|#K<VMYb6<yq)C=A}s4L<;s9`4-LKzYPX
zECXjR_wR!+yN^4W&P?`m&vav89&`7E(H3!lyEy_9gWQeNfHuTkI2mZe+#e}2`h@$~
z05ZZo6oj@>?%n_hj&ZN;1?W@m_gau=+^u)OvWu5OKhtiWcLv1w@CIm0?7}<i34y)5
z4=Dq8A5TTu3a-3g-$11s@Augh;dkdfrDd!KZ`*B{=*i>kg}fKf?-As^c{A=p!iQ(R
z4^6&2KS}}I&y#Xdd4RX)2p$1H-j$cZ>CX#Vg;D_Tv!BqVgS?Gbz;cN9p%s{cJcld9
zgLo%sXB*6`IuAobc<&=4$l(;q6NJE;Fdnl7JcoG=nXojR*O~&fBfM|m#&L?^rT>j#
zi{!abYIYPa;1ocQ@;1m&ism)i!4kvUyA&jr7fmThaXiBsh{yB35`iT0_E7>=5^n<~
zpC<EM=_0BW-YZ|BFOF2+_?0mDB<~ij3eWHwdcbp*S4+Ol9NrZQqU7@8=mLXtJkzhJ
z%;S0g2y&kHmJ*=(yeM)IU*O%6fE4h?KMzvKi<k-vi+HuQz`Vrk$%Oc2p7sm074tSv
zfp`h8>R+h8;^1X{4%Vx@>$}jyYrK}ZF!(yg8LT&WXK4d<lXp1><QA`e6YMVIT|9}7
z-sUa3gvxT>A{JEK;f<aF+Fjl+xsa>i<^B%}@9{=>=u0JU?gg|}@%o*ip_*6I1NAk$
z_;!?Pd5&ps0IiNUaUOW;d7Z-mZQwm9$0Kl`_Zy`YJmAeDCvYQgM?N$)@$zYv)Xe*y
z_KhvP2{C|a<!wlTKpRi+J4z3Es}=yWlNVe7&Mw}i0g!Iqz56h&hgba&V2^kmtI+FS
z-e(R<FzDm0_!2z*yjwJ<Jm!5~j>-XE^Z`f=^74479OC^z8LGp)l^y8X6W$sDRE+Q<
z)}wNi_wz6+$9S(L0p%%gQVhs5-WC$y#b5n56uR)I{I_P}7afD%ef-LwA>hit{w?{(
z-1ukdPr=>!Ka%g-gFkH+y5`9jO3-^Re)%8J<joJDc!>}HyVW4Rd|y4}_VZ`an|^>F
z_Z)~Hf96Vv`}12DLLh*D=s9RQ$nOY%^@sTLY0n?XpGq%B5Wiq21cLdKIkZF#;Xfl!
zKq!B8IY7hsZ;{vQFu$S*n!@=r15p{t-$dzaQG6ABD~|GgMj#N&&vFNe<IklN1Mz$@
zrHmx<j}(F>iQno6xnzFC02HS1gZojL%D-EL(n<cUVpy2YKYo|~geQaFL`&n-{HT>s
zafZKOJxCV6YZc_P`CJK9oaO6jN07rm`Uhan@x%W>TONN$2}<YrQU9Xb7x-Jrn^M59
zpzYX2zK(w1LVhphUl#F`=-0Z;cf5kiV*avh*jvJniiFyrH#dx*>?k%t=o)|XCuq3N
z?=S=K2471-zgzrw=qyYbUw#p7xA``Tn3nT}gDBnM@AwOHclos@z*q9Wq4bn0{xUz9
zRn7nGL;R*S{BxwUmVb;kDs}vowC$+pN8QIy+ra-H-OYKQ|CNI#^LG9-K0rJ8v&gUd
zkbj1v1)cox#gOmf<A=u6%il<$sYm?h=*(R&e<~gC>F1}{L41(k9EG+aekXl_hxxK!
zVdxY7qUV7*!rxPYwo(2o6)<#+FMAK_pYk8km-`vtp>m*hmtdMR$Zml}0JJ@Vzp2ty
zu#CP>Zi1(7sB{<b=n3%<EGGw)r$C!Q52(P6qLbc&86U$KA3?~Ukn<Ik6k!ko1Ys*d
z4hp_pjE)`>BuoNWpdgK+ut9>h4<Q#U@SaW|fe=A1HY`q|0x5+`!vqVr0VYx~Ob+@e
z!EP?dQNdS8U~q~Sd?^Kq5xm<D>{vkoEq3DswntDAFX-9=k|6NxhNk0!wG@6mA?REJ
z(^3Ql6oE(;ocD&_lY+;z5IrS$?>hYxMw&oX1;KQIaXip61Tz;w;Tgfy_fX0b3@-)A
z7JP9N3eO5k{{c*nU<;+w<qDeRs5~dwcnmCgg35bPcwUg-53qc}YZT<aAQ<}^Z3Tj(
zQ^0vyu$A1v#eyAi5HAsMThLucsbKFX=<gN5i?qSID%g_^+pY;bD97NsV8xdJy&-6L
z4775=)gOU&M{sU31n&yIq2*qMU|=%(dr#0$e(Op>&d0#65;V_*c(tI&3B9ioyiPH&
z`+_$q8{vV#(E+eV!N_rdH8}+QF3@JdFZATM2;Qf}*;c`X?I3M}Knjev3tp2!MYn)M
zl|6!-bbvk*SURDiSD+&=T%Vw96lV7ew6u_YEJ&y9`vF1Zw;+Rp2We3FL@;FmN+SYx
z8>}A{eD@Os#srS=EkJuJV3JepnLtG`v|YkK$uYTGxO5wM_6W6`z~Um@Xax3NVG)Im
z_X!`~0*j~6`7}yiLd6Qmc?+HC%k3kaUVt`V;kIe$(tcs$I#_=|_)Zn<^%KU-hI)Tt
zzX<w*gp(b&z!NMSqnRs2IFnM0LWL1AkO&igOqtk+g*<XOg$o_D@INA~KLBGQgza?k
zXpAt89=%xMjIAJX!bE!X;)U->KoW#cnjn5mC{lqW3h&ar^-03QWPl|L8|VnZNuh4P
z17@5O>L^t<P1yDgYSV=RIxL$ZJoFtDo)&ihh009fej#Aa2zUDfJ4@I@?)n_z+J9h0
zt}tR8tUo6VrImi3aPKN;IxjrX0F->;ii=>mAaoHyLxJ$#FCZ6%6KWt(C>&f$e!?Q*
z>TAHhB%Blgg;#{8t$?{IJWm(aToa!D2J+X1Zmux&hLBeWy*GtR=Rx3>@U;l2C=-sg
z0JK8*HGTW;35O|mUMYM=?usg5iyWNQ!kuC0M2&FL3t*`g=2;+DC;SSL4~J8ua22_X
zn}oh+P}?j#QbZ4;FpaL;Y86&rgG8IqkJcaU!r?o>?hyXU2k8+STJTsu653|L>|SBl
zS0H`D-zbF8FD&3d?_*(x7pxc%3TXW>D7;70#uMRTa`KD_r*lCZqe3}3F~)>D$bI)z
zc*6@Y&xBvmF40XiD;p}@MRRf??;%?GDcU?mpPYuFUZQ(+H;uPwDxF~W5zQ=wUSE;5
z8=U(^ndhMCfT*+sB|lN;9BA?vC6UV~Kvb0h(+-LP$p3rDAxbJiW02^dDu4!y{7V57
zBARdjc87|7r)_kY$jJvJTy%UXSdNHHl%5tL`jrdLD3PQG>W_+S3V=q7z9J`WjHrnY
z_r{8<C|y56^f3=|$3&&y;s;F>?WDzKlF0KPkYtf#Nf{)Liy~;*c0zRibx5R$(vN|p
ziZq|27pFu;v|LOR3F!1@x@gsB5X=ze(1!oCDB??yOc8HB+OkA$0U+6;E%6XPEAqGo
z=p4~0GoW)tUy}FWoM=RZVa^kM`Vxlnyl9)_0UGl~gC|gXK{T%bwFM$)6^7)Z$dxh&
z3Pm;aJQs<EXxh3Ynm7Y2mqo$kPc0Vxo&)g`(F5|umx_)&54kI%iIf6%RpkE@tiL9@
zzy|bn(H~y`?1m_fzU5`2l4sz&EfOuHa7?+#Aq40hQ9C`scSUn4{8S;DwHCdo6s>TA
zM3tzN(uk@>JEw!CM)cqpu+)k;9FRKETXYhxK_sHB)O}IY3UEFU1&*QAB)XjgP0gYc
zT2!`(Oc!8Gt7tvt>$Zu8?$M3C?V`<;9oHe+yaqg-qR+pD-Y%Gk{&tJ3l`ySG)J*fn
zBN5LNEPbMsJAmmI9as+XSmas{mI09~-B2|s`ksz^4vFlPygwpZW`f+P=&l>&#zeIZ
zAWuctWgyQ)o8u_Wd6zi&TNHPTyH3H<J>r3KNVtgilaF|>xQ)Je`@~;eLdjLEq&S<K
zxa3_3xQo4L@IAy_@)~-IcaT5TOYBcyT5s`o6Gp~IJZ=t%ulNy#?)QruDWrTroOuRj
z`-vm}0CD(>^?JYrh^J)2;Dh3Px=QGfxP=^Uf#Tok<Y16E-vFC}#p(Y=5XJIE=wYb%
z*dt(viDO;{=V9>{as-8o-(CZ9MC{`Yxd^f1zZI-_Bi#=hCBAeW8jgy0Q(P`uypO(0
zF%I#3dRSw{t8M6EocJelHOGr3bow(<yygd}ND{ZvS2$U`LjdgK;-7tieM0;(`7lz%
zykEhYD&DI`XHJT9(t&bHe3VvqY2xVRfKC^0vVb!~ypr}gr^U?_3C|S2Pbqq5#Et-3
z@@0v`(lBh<;-!l~&Wc~tf;C6{$q-<2#g7i7@|^e;@=xZ8>u4K)UOXK?o>RW~pcX1F
zi0zc9Q6QeQ5iA$QA>?)_6faDHF-77uO82-Vev{4(Ul!NUMFYj+|C|pcVv~cW(o(S}
zW#?QG&(?wGs`xkq>Tifoi9v3PgPmdiEiuB)cyq+=(?M>F&$@xLTr8RZy?4asdVt;)
z>*z-R3UTR1u-p^>I~~xK;#rF@qE+J0DZEfE{)dt&YQz$n@@vJZ|8t<WPP~AYN%i7k
z`tCM}lfQxdeesP8XnP<|h(iw>#XlB7MU!}HF)EwIU%vp(7V)Njw6%+$KaWy}_*yQo
zABx|j*lefRH4K<tV$Wh|>Jf)f>ewUky1A(A6?@aEn?CXHpHQAizxdzT=;&kd>HqF-
z5Ld26FNVY}??7-^9K8T4o`|oJ_hCfregKuDViz-1JQbHvXzH2xWifiVOR_NmWRGN{
z7X(}+eJqsrN+!`%wofvz7@V$>-B}QKmjt$ecu3eIlkxs}O8y~_ikGCEKC0f5-JgT_
zNGdNwe!rw46n#1%N&XuO{UinNpweGbzZwDok}dRj9hAI8{;NRAF>)CNNs`w<AXsvr
zmTZS5b+nNTm&|gY@`z*`UB(e1Sxno6NJ%rfj2uTL3uwz5E!i;w>=;QzCD39ed^rT;
zBoinZF<#<NS)K_J1$~?nCHeGCPLd2i228SKKCS$YOOk&=+X>0m6A(|8tY3_AJ}H?(
zhMtmqhK@R=NisYjkS=NQ#E@i2ShRgV?T|ck2Tzt{JZ+$}B`p-9Ju9gsM{JJ7R|Uab
z$rwc<@+8L;s5~#p_!cBzvVwl!3zFQAp|C)bOWwwdlDI~+6-kuzre2aPrMLL9WHv=N
ziY1FEid!OiUJQMul6rTDUzIqX(ra-|a>NzI>yk*Cgl<ZHq*?ElB>F=PX_+MU3k=k4
zNg+8g$|VL$TDdFfm<&=O8NU+Uz9-QTsg%4*`@bs5?=<+;l2^9Em|BUU7tnQ*U-zM{
zUh*ONzZxWmXePcdQ8_4+?17|}f`&~JJ%uNlB~uJg-y+#gKDiFbR3-!;O74CD!A{9%
zYFN=FSxARMx+O1?v*(dSd<|&5l4rkyrBAZgAEaN>UkH@PlIY_o4M+-U<u(YLAU-Ua
zO1BC=k@T&1z_t-d;wq3)Nz*yhj!E8cg2XckOAecMNk3_Zg}bGHZ-f<lq&^E!a*@t!
zLVx#4Gb!(OpY&uZ+T5j$loH}0O*#w~PiY-_7QCb*<l^#{meZElN18kyoW9bX6hhc9
zeRm~&{|-nmj{(h3x|B}v`b!^ETrohJk_d88dZGfXhor1HXbP0xBhN;V^li$*4VKP-
z2DA`qH67**mAWqkN|<!>+faB|>iQZ=;ZjE`1dd3DX+$HWPgg@AQhK8Vr6}pgIrRP=
zl`_^qMYOb>GNfXpQBFXMmENZ?dz|#s7XcG5z5N?16QtWBfp$z<^9~G6l&UFAo+MRW
z2WPT$HogAGr4Q)>vJ=u0T1uoyB^1g|l}3LAg(syfBLq%Kl^0M-lg?fZPDi?Q!X}_)
zO0T9s;*9i|H&kRvd+FWIkv2_3w{xZa^c$X&7E$CRU%HNNNxC4-q+F~5sXwi$i=?@<
zD7_>V(-!2iG?kKNN~NndK+_ee{cC8rD(&Pz{SE0t3NYW4zD_Z;TMlWi6MmU;X-XD)
ze@A)-@iwQs(k|LqR7$-Q!BZvO_!UUC^n>rgQYT$Pf$e&!LI|`5>5CM;y)S*Y2AUp7
zKlllxQJO}Jye8>_<zQ)+I)4QVTckdnKxvg0(n73Fy7x!Obx0k?R2ckFI(H)^I;Gdh
zan>c3?Z>0nEuBK&j7QQnz7Xt{zVtmL`lN0j1GHbdh;{^zr5hi?m;q^I4B7^z%1r<p
zlE$n><*>A}7%Weuo6f?f5$WwofF70h(4#&ky^syer_!~KGO#|A+9K##mu*M^&u-bF
ztw7r&+b|KD_R0G4KwM?hXfNz0<JUulyR43~7d>RZSy1UIt2qQTFWGPdIK5@Uc!2rJ
zl(b0OFZ+l*Wd~$0@uA31cA1Vb;tqX!ivwh@eM0ZwL0L&R$RSxcz3{;@QyUsXWZ%<@
zCRDa|25btK-ChV4M`S-xN^yj2S3gLkj9&`0DA^NwN}^@nOHhiD)sdSrR+gQLQk<-m
z3+Q-RJ`YwT$fD_*lVh^aZRlX4Y{{>bRGTD|(iEO7yFgP@hAfh%>C>`+Sb%2A!o2}=
zMwUZ?fh<`B12EaL1WH9dD|31knsQ|GX)BQ{+d37cbF!thk;#)4gn^uwY0m*AU$&II
zI2U9eQ?^%uY%NW;7iFpMQk<+%=I06ZMKbqY;JG9#q=oBc*_J$%ie)dnhf;}bd?y4;
zWydHv_KIxI5CpEuJR?wfO;$;1NY`c7I+%S!cJW<2&NpR2ltXz-R`&%^%4H8TP`V=v
zJ_$qb$`a?n`byciG?zH4WCJyTsg~_(18a>eilTM3vYB@wQ76OF6i>G-oiei?$Y!jD
zV56*$7IICpz9rynmW}p6yhYYTSs1Od-)OtsCgV;5cDroB&v*hmWFPK8<wKd0a+5k`
z;++8Nk~PmnTem}Y^HntV$QCP6d?Yi`7PVK#dj!xv+3(qa>6bm%28EAh?@&h9fJ{wi
zLk4B8h%!12$yU>F4a<(shrkn=|7wsCS&R*uMrEB8B^;9(7NBQOWxxLh@=SJsl3jMm
zga3v2Zn-0|26pd}SJ6A>B0o=KvRD2qCF1OptLRm8l`pypy>9Y=e_(~Xd?Kx+Jmlu>
z;PjL?_d<o2+;cxFz2yaT2Ea$Ip!JQf+=uoaesUl3Ci}}9=t_hD`TFm{a!`J;5LO(L
za~u>d50txv06Rz?O9Ad+`O+lFhsYfbs0@|Ylj|@{&Z6^qhvkzcfC-nkUIWV!`R;V6
zkC0FK7o|u!k1~y-<Ok_PeN?`Yk_)2c?5R)~Bj1t-g|YJ2DGMTA?p*+z666nSXoG!B
zp7;uQ66K!%LNH05c^akT@_|>O@PvE{9kEQ2&$|JMQ}TE<>`jwr(Oi};f0usI4Eg48
zlupZqXQ41t{&5%t&d5*GH!4fsN^g3$ym&G&&&m_b5Xg~Vr1NIE@`GPfp5!@s(>E|G
zPkv@S6rPv+E=FU%{M>C+UXZV(M5_Y%!udeEC=b1i9u~@%jiFQ|pPmPDN!~)A{mb%2
zv=1wmTiYR5B0n1l&Qkfp6ENnAd|fYCuFA6?K*Kfp!5CO^U0#Si7Or`ae@O?%Zpxp3
z34*ueU(tHIOwJ>>{cX9U1#RW>C6tX+A@?Sa%RRa8e@<`tALQGqlKTyyvRbZh1*wq-
zlGCkL{vKW2RwwW0p|W0HaTN+1<TJ(r?7qB=ZUSqRr|&?|98L1#TYzbns}exE<jXFC
zbj!C_L!w8%+#e(RNNy~KV6WVRj*s=pyNI)2{@u42r^oU_O70nue@(B^p!@_)lf&}j
zbd1Fl`Rgj6jL1W4V9cnzC>)hz@_Bbr`BZ*~j%Ge{$p4uKnB9sNEv(t2D5HtWMUhVX
zDOZK}LuhhSY#j!1SNyvfDm)Yg%faHQnD{q{m*UShnC7kU?E{LBV#*VM`YQgWpJKm4
zLhf-t#oR!s_gAbLg7pCk=6J9iR9vS6%ZC(>cdCFLsJNF8m>`Al1C&A(7K#LhDvr_<
z9HzKWsS1Y`U;G8T!xeorOGhaD&SMZG758WZc2w~_EySV~n@*xKMzP>21mYEEeITBo
zctj~T#}vEBS8+<QC>6$}Dc+EwyXlI(j-P;*p?JFlf~OTpl;N1E5Yoh&tyo(D*0YLl
zyil2=NPQU=<|>Lg;5?_ez6+pviWzRudtULx0)_bsKXPGTP&iFSWr5;1TFPHkoSq2{
zg^GU4qPV2^a~aw$D{e0UXR(6)*nwh+;wN%?mnu^4z{G2cKnf>ZSB#^t;SGhk9r8C7
zg=>IzOChJcr833q%@DY)5L5J|Tyet+xjPC8ErISTYOkQOLb0m{D()$UpP(<53RenQ
zRw<6tQlwhZGY)EN6hq@^|5vLBlt8{tv1b(o>lG!GUelncQUdM1;=4p>dY}+vt?1OK
zI5Q4yO^RJD;A~dBLp$6S#XCx1w<=O7!=g>Gl-k-A)l<;cp}0gozlVwg-B8%6SV7UR
zE=AEofORV>JIVjqqwso&#z%^0bgO-@VwC)IeTv)UK<QWfa}8*Z6=&WB%z)zTRSd$Q
zqMD|=A;rp{!7{Ay`yT3_D29W;GNP#RgNjjw$BQs~Oc8t*EKe0I+9o_xtey_AUCLW$
z(Y8l9{yivi>{C|JuFh52{oi3FWeRy=-IbB#^Yc*NxsEnZ<*lC~=%p-cf`qs7=MD^_
zkMde8jPX^L9ELIbmDBD){Q;$$H`@G^A5MdSzp{fqG6Bk+<bVuQc2H{KVP)V{aE2=z
z>BQp^hjLRIY9o~6OMo4zoD>X&QOcj_r#z~B?L%}XS~+n6&|;K7v0+oJQbp^VIOP<2
z{o|D%Erxi4a)5Fxjw!=-Kp;`683*hn<r7+HCo6NC(RN%Jd=`37D2+d%l%iC&gELj>
zIN}7flghtnA$LmomjbnE%0f!qOII!k226(1PP67|<wCj-EmJ8!3vx#Jo*Zad%8oaH
zmaSY*oM)ABM^VaAPKX4_Rrb;heooo_9x(Hi-vof1SAI%=X_&8EB!b!t$}b!gJ}FS%
zq7A}D<vBO-6e@=U(WfHim=vs+l_76qfQyw2$a__ybdo`DsnVAXfh)>sWbakwgf$Sj
zru5YS?7A{72$eUKE8C&srZSb*#J7|`P>8QgX{7J&ZDlTbC+;dmOB`sdP|hd6#69Jk
z<l3!NuAm&~DrM|rl&X~+I&oE_yzvVJYn4^x0I5?((($5trS3<FHz?nxu=9Oo)^gbN
zKzW9892%ACbtp9{6GDK}to(s~iWX&A3{YB?--m#uP04;`9Nxcn<%&x{>rg&oqVb_J
zqZpm(R92Bswo5rcn~rW}9z|Vyls9Op`AE5j(g%B$C&@?Ir~LgnRQ4;k{t5C}X{Vzx
z1Ipd>bs1EC8UoHCWhSlMhLx6w(ECKWQVlYqoVk_!pQFm`iRi_c5(lX9t|-}*{`*YX
zJOpEQss1D<u!}086cT$?f7}GjK2;?pt+=Z)rlHb9RdXM5o+|iM@m8oTED&GSXY>T^
zR~=))rUNS6>xH*M^@kkB_^UpjfiVnFNkdU`98^`F13jc-(7O_-N}=yqkc#;|O2Mi$
z+(h9NqT<q#)KHb?G+@G14VzIqtnw-bcDQOAE$NS_BFXg^p*k>#%1G5eOq8NjO#)bP
zR3#%fOtk6``tZf5zJ3uTR<(=*oN*4-a1Z(vuj(hyNrLL_Xq1vv79Dz+tXiK7nB%JF
zDKeU>dY%KAld4&?Dm<lX9gk9)s;LX5bXA-fpc$&qe#cmxR&AXHLo-z~7oqZuYQY^;
zW~t7l11wuLRRQR;s*5e?V2;Y+E<`a`)#L(lP9?~J6?v+^X&-i8<xRoJe3k4ZG+j_7
zQplh{<<bf4i>mAb*i@*>r~8eHRK_!?yrc?V0b?$!B=6w|EmlpSh(n3$7n-F@RX(1m
zyrSx+N&c$p2b!m@snia-wC|?sDrLFdQZ4@rwPmWv88G;^s&g^q%T+s8qV0}q&<GXx
zRH?KRsZ_1}7?oA3iR8>}Q%yiRgHyXI?JubBP&JN+riZF+^fl{L?Yso_U8?*?=u)>T
zD-o4Fs(<KzWFM(yf6@1^SJg;%_o)^<51xKi0eSKst5(t_<O8aW!%#S=8h0O{L#lum
z!7{AsroGY=)xVTkGNP)S1ofk;Pv}E1rs^$)+%EMb$`stKUe*eMJ?fqe^vp$l;R-7E
zs&jKe_Ng0wp=*v@)yHGN<EGZ)5q5G{;{%SzT7B_zlswgo2Vt6*I+OxK-s*|(V`O~P
z`zSEvtKLVm-hMTUd{GC~bN)b^pZY2##Q3X^(F7Hsjx+(~p!$>ooQKp?=mQd{UP?if
zAob24C<!E3{j?6OA?mGkm?l*H5qYn|)bA<*b66cvic+{b<O)hh)b2+hAECZY(`2Oj
za~oiy)OVGrJgSbQ2P#_q1#NU=)X!6lJyyL~fU$^Ee?%X(c(t(yKVgD;8Es^asolN=
z%SVaoFDZbYq+T}{^2zEBTBsja2av1ggqlOsM~eDga+Rj4UkQ52grl7?<oZijucNCc
zGSr2%sXVRT&WCuW`pt2`KBI2<8z@=oq31!e)j_pTe^y=M3q?8V<MhSKReNoR_&Igy
zSt!a=AELwC=haS$K*?91_yL#~)N&7y0`<;5kc;XszQpfRs2*};qfbTZZ+-#jCAH=Z
zYA>t1N&!=>URe+95_KabU6iVSq?E`j>V*^^x~i@u_x26-h6a>ws%Pb*bW8mPEn3Rd
zUN1r5wz`X=80G5Nb+F=&x_%WZ@2bb$#~4(oy(p3Mp1RCI7vWZ_edrKQl{#${wbknH
zz6V;3I@}e#uT>||a<D<|L+1qUtGy{|`anJSCeRwyp%f`>QjdHNvzyi4GH|x3wUh$U
zuI5|N)}fx93@f_Sf6->LTYZmQJ3Z>(DTlaEz5F!gE%mGStw-^(I@Jne2GlN-ATg-k
zyAukB)DQj#^M};~$pC$#{+QB`M%3bdz>KOlQ?BWlI*tqMr|R}m2s~3iM+rx}GzJ+^
zc5Cv;^}R>)4|xz=H1E(6lf9ZR_TblY(-c1?mxa5AO@G+rp}9*_u(xJ#09N>D;wj$g
zt2u0i{C>@P$}Bjb`J4RsewvANC6K>n)(|uWXxeFeaZr;<ht&^hxB`d=YRYJl7Nil9
z?>SgA|5vnyX#DAxq)^S9GawhH3H%5)ISy+CuR%q)CjJu$Mry*%P!Xj$L6hcDO+*4<
zVl`#-tjB2%;w+9+yhcLl;0c=MBal0$X<v;}qGogqr6kSFpCFK|8H$00$2IW*=+X&I
z?JH29qWO(35=_+`^#jXE%>-ICoN{Our=T`X)ATb)x@P8VsL0Ty)0+CUMsf-!W@)6g
zXv@}kY=_-vHJoE$xuBWvi>?)DI>;|@QIl~WRupQc{D#URO=>KL>yjq01#*`)nXyn<
ztnvLAawQrUO0g}~<WNG=6^%o;0uom>t4hIhP4i_m$aPI%8Z_O|6w{HKo0`lXVBgaC
z*MgL3Hd3DB9nI)6u-w(GyARL`&8#PAyQc}DZ)2sV_g~mlrI|r)>S|3f<=xh3Uh#ok
zttOOGf*Uk7qagP+1CDfz!UN3=ijy{KZqx3nNi%y5#;aMgf^rdBGzk<1Y1Q26fP9<g
zAPbxiHBv9gb!uMSf{u1+Hc(KaTa&pEZ9Vv5A@E4^f)tg#n(@&vtxsbgfWm&wAG8w~
z)O<~Dlp#&K(E&QFX{XuiiRPcTz%!x=rZ;_5(^dfaF^z$8?Vf7hxdE1Enw=Cr+@n>#
z2xDBdby8^Bs~y*kL2%P5=vsJp?HV>XJ+$BU0L)wa?yIoSN6Vtfq_1|}Hkj?Fy?zHQ
z{@OcBDP=1_`*tsk3e=9ij>aIZ(-zniti7BI`7o`z3#G$aC;Fy_Yh5WHBt~0v00OaE
zPdaHCr&T^gDPEft3YG*dKO6QQ)5cCkDN*}(25d^w#tEP>S!=I^hU3~#X=i&vyANI`
zhf|973|-ois-5lzo|D>3CFuPr?JKiE(zMkR(9v}5N^;R;Xb;f^$)~l)XqS?y9sLa|
z&S-z{gZeD(CGu)yYaa%~-m}_g$AOunea1#9S39y60_U{MFj$|b-9hBM_VjlUaO7+M
zN`S!y+V(sYFKXjgKw+WwHhH^?w8J9UbV<vk>GHC+jRL~O+J7d4vqWp5z(J|Dv<L!M
zv<>7rysDi*zNl;38+4HAy0&^VDsN~b!Xa=|>$el)x3mMv5Gd1z7s86$4sEPE)Zf*5
z(Y4kU+WBX|dQW@u7!0n~K1aUq8to49%hhTZd!n*In@4Nu``U+3(Dp#PnNBh^YL9$|
zQj<1Qic+&yK@Rvf?Hp&2cJ1EBkn7O)kk6n?`wjW{yS4YDfYPINNPN)vNV}1emU^{)
zLNxYi3ooK_KwC_E(m}2FMvx(`2RSZBv^^QnG^%A#&}mHjJvlyi>9VO$yLD@sXxpO;
zzJV_7)5WbtrK|1~rCz(~o?8Tk?mFopP&{-Wq=3a!7vTs6_0!#<d>?<^SLEpl(DjYS
zARg5HP3eh;bO-6N4%EFyE8QU7RuS5Qb<UKl8lsbbh*GG|L;_*DWs70VVco1Ms0i0h
zBv14aUFkZ=Md-#pMO&oKYZr`((oM(&IjWmD%>kHb-B<M6$LLt({)yFnv=t;y_n8;k
z;&m>M(Uzba-T|~@x)~p!Em3!@7z&egEOLh=>k8k-I3L$7n+;7TbekxZAw~BiA7-cO
z!YJ4Kq;3NpDLtk8B^+&Oy1$N~l&)LFA(uslF7-=Tb6Phx3*(ik3#GG1XLPn`pk?X2
zM_@&^PDOtXaaQMl1(i9vx2hnYt9yl9v*&b&=ts}f?S3Dn^STHppycbSqEUH4x0!lY
zpj&?#rHeW*SCk5M2Whq}(s>`H@82ceK3aoZ)=i*TXtA!P9y}$wW)&(+buYUB?TYT(
z64-rJmrc?1Yr0JGlwQ|mQR>wV-A}P7mFaX8V7aY}gdfDIT=(D}P%3nBr(x4QU5FW^
zQg^ZkX4mM<|G=19U9K<WHr44Gbf~?roAEj1AL#D*KyRbYJ`pf2y7{#2ZPoon@rO3u
zH8w!obs_0s>CpX1^YTO8J$ko0b#YR#bm>Zi8n$6o_lpFB->Yk+oSJ@}&kr#BvF-~B
z$_?m}wnNdNE@Br1hIDuS2Mxozzs(SMqKl_!z=-ZAKH5fgi9x6w(@m!|qo=y6qtN$E
z*Q$hNyYy@6aQ<%nE0ch^M_;}fid^(>HiGQc*EneHzfYeS2?<wyj~!@k`g64Nao0zD
zgp!AT+Mf{g)YlvXjF*1ScvO1pZLToQM_)pREPVB$DwwukKM&WHI33W>i~^^h{*NS7
z`s=s3pcJ65_zj!~_0ol?Jfxpd4Yh&#C@yV8g7k~eqcK?jWgYqyqEDOwo=|=8cQ7$b
zf3O_t59=3E5<$3rc_R!xqUX{Ptq6TTy}pt9c0Ke)>GuYr?Wq1aJ20d5>hC~e^mP+~
z8LPM3K;rb{x<TUgA!J&D{?rq41RT@Hy#Urk{U-X*C+S~24(w$8q<E0ydY8E{|AhVx
z4J=I22hD>`srpwbMf#-vDrLW&()TbRm!@C89N6i4Df#a+^l=F==CpqFWw2!G=h1rV
zjDCCz#Iy8s_CY*bKM7gM`0FhF9NIbM=rgU*l&kOi1)Vvk&*Z_TJpJ>uiaoF2PX{UT
z_4N?|y`X=e3;6;)A_RC<^s8yMEY#0=3n)c;pFL22Nk4ZJ#4qbN%VAov{!0x6O7zcV
zKtrj1HhJ@}=zA+6=eVlp)A#F|-bnX(Ue_<A{PkP<Kk^}8rk|}w>9*c=GFZy>HcIxr
zqqnXE+FkvRYoV}0KZEA_d-@5KtW>FAy$b?WdhbKfTdm)96c*O#mk3a*)gSl}0(JTe
zH(_DDzBvFW4Guk<mUH*@jh_PMf&NG!<Qw%L+(l!Pezpd^Z`S`xM+RH;>k?6F)i3sf
zK%4%-w@}!wPoRX}4*iR#A@@*UnhZ^ydhsT(bm?uI!P2ddB2RLUK06+qkMwnWP}!?*
zrPSR%y(5G^vHkja6wH6Df0>d12K0aAfoD)Z@EY2N^z#>h4C`APA^$`_F%6s}`lYm_
z9@P(}LgASHS{MfCsXoLLZO`<-680{`GCCi(+aNcgXL}8O=g_v#@YDm9u7>(q5O*{D
z>!2f{?uN<dQS>mFDc#P~@YXgM>}5Ey6s+EcqHa|B7_=&I`WpI#K-+J~r~6?K7)0c}
z^)o!AXWif6Pmz%TgO;2?2My)E80SNVuP9qK&@hh-4KlcK!4hn^LoT-vgI(@`icrIy
zm%tik5EP;Iup#SLC=55uHDD}`7@nuSPK4pR8&DBxSm2AcD8pvT(K>4ImP0(+@S+8#
z#TdpvkIGoX=mwBD!=InQig-g2omo#XXehPpnBnltFecFuO1Y#-hO5D}t4cOx(ZhD!
z@Pv|%P8iZ?lapc?V8WPG!~1kFC(V#YE4OsREPp7>Flgwo&}qZemtl6MfxQ<No-ypZ
z1(Ynqj~_rF+wk`%D4jJ-z6yJD3_)8Uo@-e48%pO4Pib?MZy3QV=5V@T2zwKt1%@rt
zps>iW^A)gOGVG(1zn2ZOzK1cThKZj*;T6MdGc3GnaHoCL4MPyQscsq^l-YC3uu2Y6
zX-LgNWtCxszU<Y8&N@KX7^2=lTdl!^d>eHJUoN2Q4f`nd-O*q$QE217!A$GG2Zj#X
zbvGJX>!7g7;6mxh&4zy|YpBK0I2qWjhIi={MVmqM7^K~>v<Yn;hN%f?duZtIhIpsJ
zivlEFhOfUvWw+s@&jH<I_<^3lM}}PLORr%j`L+5ShHmm&^&6D0gY~hYYB6dD3`tu7
zGiXSrHSLIDEj@^%2IUN}j2S%tg1t`-zuZUVGlOjiEW3>NQ_$btMnx^!_83z#VUw$|
zw*Ufe#ywVGx*Pk?fyKkP_XVi;G`f<r+RNy;`#jWp8$X~uo{zEgUo`GF_R|A(z<6gm
zVEl}=6r1xm#ykd0fN_UA1P>a2TmpeZ#)w?71R6Jx^ESvhwh3*)#&7K)p~mNE@(VML
z?}CMgjqAFB8E*WDa!HRE=R6PVBaP0ErI3#@HdCznsL_WUh%v_2J7|nGYF+|NobfmM
zxFr~?N&s`rxHAYNlW24y|8SB~77Br6W55_nDaNbsp_FReM~>E$##UONpECYP$DY%S
z?`{E0y0OL#D>967Iv;o1_+Scs|1ymm$56~RHZ8??oi)k_z?x&6@(WmVjR}8&oHP37
zqB76Opl$Yf<2_mp<{PVMqk6%3iw;8<7|*$*?V@qc3|L=iEK@+B$e2do`%A{8ZD_k}
zJl6(+Vq>5cEG5Q_?<o*mYJ9XC^4E-c6g#?ZoSp$=ZWwEHsJv-B<OTU##<$5GQfB;{
z9C^2mv#U{AZd|n;0(XoTDH-&x@%!0esW3)+fZQ`GO3_wjyb=Y0YNKolz-o+)^Y{sC
zjh3%bS!djsM}gpa<Lj?MzQGuA6pi<drzXL+2gb>#KpKrp|AnR|W5cT`H5=n50j9;M
zI|J-i<L}Es+KfNvL$2KzlYs}K!+3#CbUZYkp`@@*<G5ugbr~CP!lrKHg9eaZ<I2||
z&}aOM(s~{J#=#<3Gia=%ZTgVWYbJPxjY|Zu>4{NK$%Z3FBRyB6M)xSRJu?o`2WXe6
z*@m{=Ciz4Rsf%eE8<l%aS&10DeWnX!jH~H8+9tc1I0ls5O{*vn>|r|fA&94`Y%c`7
z9H!I%ogp!e{)wWG=~eQP958Jq|D&I279}nDo3@2OBEa<JQdAx^O`$05A=BQIFecFC
zOaaOuQy)EZ!KNB4l$}CMku;ZtnwHZn9cHR07xZD%+Hn}eaMKG7z&v8w6b$hQlVkfL
z@I;y}Z-PXW>D~8Gd(;#|(S&Hz=PN<tO+l2Dl3<!iM+T3X)D$L7G+jx;50hlt*$dEQ
zlYx9X$4#}gzBysK^a12jOn(J~q?%4wg5{*?g=et-lu6YEur!m;ZRkrkr8+3<Aj9-0
zd1FqS-ld>xrs=IU=*1aR<`l?hnPMpLmTl^Yfr_)H_h@;QW0H{XIoC9WRu<<>JIWxJ
zXR7@f<h-e`9t!hKH@wiZ3#PK4VQ+zH_E)I9XsX|aVJ<WsXaGu)>Gge-2zALMIu4l2
zCXbJxu-Mecg-s=<@+CC&o1}KIUNL<#3F@z!4h}=bHB&t8%C4LG+dyuZ(rIG7X)@EC
za?9jSQIj%LG|kJmP0!{5rQCF29gMkST6zHFuBo>lq{77dFA?#cX}bo+N>c<`T4mZu
z$@<l%=`_*Qm^wEAwAS?MM1a<rZYF@#n_9@N*I;rVf!X&>@e~JpU^3Dy&}`aDSr#p(
z?0INwHD!BXoZ3vKdmz_t3Rr@+4%4+q5O`?X@$NXhf1M^Z1uVKudwbE*Zj%$aBYR8-
zlhCI}rr8z@Nw2AF2`ub0Rnc3~Z}R>Lr9qSFGjI->QYnpj*yK+>s3)csq<+M-g*Hc{
zCO%EwW2T5O81vM0=nv?9W@0eGxyzhPzp`VuIn)()?=gRp1s)gkKUFC0HJ{Fbpqp9$
zF)H27$?cHvFmtKDp61VJd*fv;7J|jwJZT#=`Irak8|7<$Q-sof^I-{44w!}E7*Rhn
zi(*aw=B4!H2AE%&4VHuE*8egg9Ol>JP#b6#ZiI>;^DY+{6>Ofn7{6MG*^7_<hMFJ$
z2$nE&@eC+DZ2o}Oh~efvYcOg@%%zl!7G*w~g0`b((;n!JHV^&^uo&~7y<mwof3^@P
zapr+@up-`Eb_pcG>_P9}F|*_LD)1zlH;jNM$t<PCTC({?+MgUZ?{EX_3G=Hzp}(nS
zr+SR@N%J_`OrA1-y&s0AnLh|aWx82M$*&paMgC|zZGNQ<B-3oL!=^Llro}+XG9P;h
zre&K$|Af9=^Iz-G!E@$Kjs>XAGndh*Uoam&2~uEYlk@7L`H&krT4+A<CQK_bSJQI;
zlDX->b&+{T8d!?WfgxxsF^7~uQ>pn|6UY^_jGP-+&AkSIT{G`r3H8^_0pujOVP4b-
zft%*<=seji^MOzY2CB^bwFKC=&5EDUSZ=O(8;y6&*P?-T*Zc#WAF42)`~z+G%(aw2
zQfc1vEmTyQ$LY|SYV($NfL&vrND;SM^WZiNNu7Bug%s<}r_xc`V0NV#=6!Pvt)3s4
zYv{|~Xx67vB5;#=Z3NV}n76p0w$=P5&7p1PyYzKwHxEw-Oov(H0hWj6+Hq*>G)MIT
zrpvr47S?y07rBA6$1EiO|0DA|)a_pLgf6i3nV0MY={NsM<gs}M1@i{XXZ_HZLGu*c
zhUjn_GPA!#pN7r1$usrDe4`IABj#o&kWsTV36*2!A&Q<nHUE!pX?bQ&_k^LlEShRm
z?zV6#)V;@&OTUPV<p;_**=s52guVML#%CBxS4-nMbi&PYPYV`zi*6X09+qFSQF3@%
z=F^>$UY6Okob<LlPpeWN%UbeW_*%Gk!L#2|-U<~5ET<?k<7Zh$OL~9Hx8&drut+J!
zcF^M54$woEHRMJKv}6RKGRX2$0R)0A-!uR^#PVApdLL?;L2lwO%iMk#de~vn)8{bU
z@=`ncbi^`^;#m=vJXf$rT5i#N6=h+k!2F|@`Yd2aTUsn&iLw0e07$Im)wwVx&hpO?
zIO8q#G<POgv|cdgm?e&4>WP-q^b;mo+~z@1vPDRLXm#9@tVQJsi(^&@Xo}_0EC{Ar
z497rDT2|b}4|K}nPl44m%Vmlirdxhn0fRFwFVM&Qj73kEkY`!SN`RJaSwg;~vzG01
z(1{#N5P2hWEmLXm&si==fs$t#rESf5%X`OQXuf6L1z32&((U*W#R5yzi;%cz5z=b5
z&~lWLhl(s$Vj+LYvWna|mn|zPj8|-Nr9|x#%N|O0Dz&J#qfb{XvPO`rmT>Y|Ub8sS
zrtZ3>mjRR;mf3WL-%ZQCFpyi8n!C_fW|35)?Y8BMPiP%kZZYgY?H$Xvl)!b@GJP^s
zR9G$zL*kyLhhE%Di`OM6tg?8lhd{MOM@ir{mU42O)LM=|gV}YKSIIqAZ^@_lL4)P|
zL7?2XDCn@t153FVI?-sUN<yj0@>&^Knl0~I$*bRDd2|ttt(MLIeXA_n%fZub@vH<-
zhlOz-Fb^#!YEkO6RAfL?m*wsC82oOF#|Z50u{@rIU*wTxTRqhGS{}TIQlCXntJr?a
zoc93z*s^E}27kbE>?H^cTB@|@(vYR;4f=b#VatxGQ1Qf4M~5j!EQJdoF>1L<j@mIx
zA_o#rEecAne`Z-guJ2vecZy-fZtIe5uxXEV>Rz<DSl7^!V6QcYR<Ul@JW677w{Ber
z;$fYkgT0<sSq(IJSzk87LT~HbS5fKMZ+$xi@&~M68PVux^%kM=pw-hA>JM2zU;;GI
zdbk^vLDrLWmLu4jq5)`#m2E>?sCDuC=uDV(rZbE=Y@PBoNVxUwSHN<_Iv5X@2rDZT
zBYM<2HUtgPR>5(w#8}5sGH0yA`d%rDan>nWuqNL6h<ta6)=&O`M3OaT6%;00zxo1g
zDb@{dK_b=qzjl;PS|8FyFzMF#Ss)qKbyBpQwhq!aD$^>U_4XO7fgHS9*7n!Il5HJd
zhSFK<pOko&V;x6Ph+L~9un3LktZW4aA<w$g1egofIpoADux{u;FD_cE7eeBa)%XX<
zWvitcq}V#1T*0N*e%e`IvF@eIK(1Ox7C^-{>l=*#yKcQm+rS&vy)^CIv<{`Bbjy1C
zGD>Au(@u=qZR;inUB**xolgFnyH>S7&?>AamVoD;b!I4xskGvB3Z8tcgi=MStt%*`
zQe(X%L#fu9?gxQ7>rM{Fu-+Q^1u7p{i`GMZqjfu_gg05|wZNuks}nteE!LArK5%Na
zF4Kag-HL+%XzZ|_x(E4(R#zeV)M=eZ>x?ezXMU*cwl1S(Lyz_ESm=FZ^(0SeuXPzc
zSAEvE+R=-CYhDpbkF5zlU>UHwkfUhO>bn%BA!`wxk9=a~(XM&Kx|22(qt>-FTaH=N
z3hDpeo?4eHQ2Wd}Sp$h(HWg(c?zVk>1(kbj(<z$ZVtYRbWUp<DC(PexJ5M)exY`b%
z0H~X7l=cqpHgg*K<YnW(fHrU2VoKcdvAO)`r?UCcqSDW{E*X0LZKa)H39tnrm&W0A
z&^G-ciid0y=^r|RZST(jPl(OvjZ&!1My`u6TN~wH9=4g!qAlFE<7bS_5!<XNR7Thy
zZh_uN+tU_wJIeMxW$PWanWn<}Xxn}lh{xC_(Nq{~TbTv%I9t{m=x4m`d<)tf3AUEU
zXgp@yeg|mDwo?@AK5k=IVVqCcq9Q<2Y&C%ZO||VIm*Yv>JMTbKx-HKILy}=jo(}QT
zwz@pnlx3@+&tSG~bTP<Tn{6Q!=Gc6e05jM2#y`+-&Xz`BoIIO^?om7Mu<0q#l5cCL
zTdFVE-04cn0-H-KKrh-Zk>|0{)<S`|BHId@^Do)-U!(1^Eo1|%D7JZBgLsK8b1V8(
zYTH1r*(<i7-+_JAmP5IJ*K7+9L*TlNPd>jJw%CcV;-+mY?T2pJ9Pd7cV3{qN_Oy3w
zR$7bSwH3`pV})%$`Q`4}*3j))mA3FWa8}vo-iC^5ThD3;)Yx*#-&AXxK$Ah8%|^pr
zZ+oF0l?}F%BdEM@3mAah1DmD`HZ|H<bpUI!<<MNxY^!qo0@fB==M)rMZ8s_Xy3OW0
z9V*&wuco82!!~Uutaxbq^Lfa3+D1>q{4QI=C2)4zc$AIOW1B|NqF&q7_tDm83#kWZ
zzirK4h(ESzDF=PPRz(}tL7Oif!WgnO(y_8(+cZD&zl_*E3<Vjr9i(;On639)NIbP^
z|A$e3W|L5?Y?r-<V$Hkl@-HFiVy~vjWUsyG2HN)7V>dz0)m}*><7QvJ4q%@46BQ_V
z*<Ito>20r~C7+Mo>jW@;?blK<2>b2V-=Kpq2kdDdg4NHyU=tes?ZxCK53t9ONBf}N
z=M$(nWFNZ&&_Mh8GvExepCS)_u${LWB*b350CJ&r^<8v3%-%uA$`0GVX@jBR_Q|{P
ziyW~}ehvyF?1oB+N7|E5!=@;^5|<6&Ae#M$4<R3IUqK$17`vGq>aq4pn!V!eKa>F`
z-ad|e_6hcs-(b@*``A}dk!X(|Lg~1D6&GkH?B@%BonkNk6s1&qYduOQ?N>K}<&@o*
za>_F78|cYBZC^eGeaW;Z_o2;k#vbqw)MwcjHK8`!KIR4WXYH41>6T-kph9J?{qOnc
z#X0*5Qjur(b4TTQyLKGCG4?OWpHX0Mqobb}?cCciw9p=T8<j=&=tOW{vd_K-a@l_5
zPoNar|Dw%VseLX5o31$Q*Iok5Rr@gmYOmQVwnP59eF7~RZ`eJlGdJzas!@5%K1~Of
zGW&SCO7FHk^$1Gk_SUQD#T~nO5S_Sd7gHFa!ai;R#P8WZB%e^F{UoJ$RoUO7w5n?R
zZv()rv42kwORe4U=@SUn*<YsQy?T3Y9RwTf9+V4r-`;%|y?9`se+BZ*_JcH&x7e4_
zDeG4I*WUuI-Tvm+D0SE;kQ3^mJt`jRJMH1LY3Q=M(T~<`zqktud+e{#0f0yLSLql}
zuRVo6Jbm^e$12G8+nXpH{`mhaeFs=n*Ymdb?k>wNWnuT;ySpr`J<V7WH73y*HI^jC
zXktk$QBzGc(Zt<VNz|n&O+Zvc>4GS|OD`5snxbGsL_vxLEMTX8@BF_1^W<@I=FGe^
z=j<)#%*?rLUgiq&V)NZu7}~4NexsrBdh^o<nAx7q<uXY2ZkEKLuWz&G4(JbTR#A*(
zaPzib;IE4zyA$SJ4PUN<Yi@>r?m^PSP$EI!E`x*?%DW98%z>V#VGFH&ybR3|<c7DQ
z=mtc64BJkj<!gweVA37~OBbu3!9)|}Zy2OUQh?#DAJDhgpmarFput2p>^{TqpFw25
z;eZa)b-=K558MtixKdc}pg~G&kPyRmEl8;0t7>={X3*2)HQX?}fZl%*h7DgsKhh9s
z4Q`ZS%UXaQF;tz0ezc*<2L@vdudiTCv4)v+T^utArSSK-Aw>!jXK>sC$#}zri<s^N
zgXaq{6AjjMyd=r6e-^-!4c~K6Pchgw!+e@yRV<uIH|%Vss*()D>p1|;H2g+Sku1Zg
z4M00#@M(cewxN#B)8rW3pQDv)P*9arp5do=fSqp`8VT2m405VkC^pnR2PrWG^BBZQ
z!}K8-(ka7iIu&=?aFMo;XAI@;P%kyqS3so9aEjKC=Cg+Ff5YxMgOtwwl^eD%L#x6N
z<qzyiL*5!_R2fcE6<oF92(6vY8+tj6;)20~wna6DuK&QiXgEq+>Pv=qY;Zx;8piiP
zz0NRj2+YfdE#CtAiowSl<f>uZ5cFL$+@l4;b+h5mbjZ{jCQ^F(hQZMUPa6#W;{bZo
zuzEN|8x0SKK%~hq@+|tA4JSPTbH^Z|3aA#tO$IQnhOjvpQ=1_<7~^d>9M6M?cMX;F
z37&g~yjvLPeM9~vSa@J~gBIZ(hF4|4>@=7=spR;fVblNCT!zSI*nMnRO9$_s7*>4)
zv@XMb`m$HIA(%3<PYpsY(4HA$YN7Ysu(A)JFATk(!Qe~7bQ;SmgUlAp*M_H*f9NrI
z+y`c_fu*fWpJCkqMEVUQD5)@D_}p9u?x4Xu8rUwzkzWDE)mX2FhMRFVJ!ajF|M`RI
zVca$!lDmu_&~|LMF@qwl-o`>o=lK|~eh7oU#$IPI_ZZJxf%qBSu0qn^*wg|NVB9ec
zL)vQ$YJvBG#!2+T+-Ll`$c*NG<GPPA!UM*j4se5v^C@+9&=|?V#bDzmBj)Rn@rS>`
zJZ$8TfP@&I{Vz9fOil!7m~l}yNVxImpI|q_s8>TF(m0#y%cG20w0k{bd_=LRXk#IT
zxnhieP^sln<IY~X|6+|}Mxc4jIFY<KZhXrfB+fXQ9@_E7@l}9HHjdqoR*LcZPQauZ
z|E7IOnz7><B-4#&W?+OF#+C;7n`tbgg-w?6zc*p&gz=&T)16~H5(Epm#=suv<r&lH
zV@mnPfrYgGEHFCKuCUN}_+#i78Q<FqgT=;c`(Uud=yV$7q;WwqG)@^uQCY`n<6s>`
z&KSp<fL&^I@<iV`<G^TK`Q^sxKfsv^V<UY$w%T};Zk6-K$+S|vVEmjeZu}u{I!;q-
zd}jwx%yq^m$6?~C(VBvN*Ni*K{B`5oh0v%s-g^OZ!`OHSpbf^OIvBid9Pt+nHW`l`
z0a~+hiwFvLjMFK$+G3oa1ZJyo6)pbTjD57^Yd3z^1%r2uGu=S$8Ox>v<-XBy1<()7
z#(7g9(_tJe!pwFWBVIw~p>Zb7<s;+$JXm^c^rl6`6XRcNV4}<DP6bWfM&(nqo*GYl
z3QNz7u73dSx$)v&=)Evz_5tjrQN?2PuZ)Yx;A`W*Q_$)$F1-cPYka;8%s!*p-3GMZ
z*vG)qfYFWiVS~n*X2`ghcq(RdHI=ub<z@<^e3-i_VL6x{riWIr>uDMp4uf8%rp++#
zZCXyJG<{6^81(s?f|mhok7)=Ugz+;)(p>nP-qXNdfNA7J*xPGzF;mnz&@_BL6!)3l
zpcL?a(=&Q09xx?QFeu2hj8+{7O*4K&U$7~H_N|9Z&uG<u*!24_^o5v~b-<@k(=Zo^
zgqh^)@Pme%#=U^Q5hiPAkVw-TDexl7#883U5z{=%3PhVcZku5u##FWe<fv)rWWdCl
z0w|w-%oNdyQ5-h~FM)o7X<`U0C7O;+1x%7@(NHKPn{FLLE5$VREr_I=mfZw1-IPzK
z!ZS<{=_}%yrkv{-OO|PQJ%)Y4G)VVft|^8JFY`>9ODO-BZz`1lroi;V5xy0g=D4F(
zWO_+;r^Tk9DXv~(^3b4l($r12f2oNrhNUu7KRt=hnjGlsY3EGGXk}h*s-qxMg{hI!
z7nP>g8Yonmw&>tYwJE6^gE(&zl3>2Z^aW0$;2@}}cq)c{$<$6~lWI*TX<1iiy7?^}
zzGC{t63nZnsn+oOn#mXnwCko5bS2cA98=J`VM_W0Xbq--zaZIY%B0QCEmP?Sz`SjG
zO-GZOOyAH=)ol8EF+99u3aEq^Ev8?tz$bH?$v+44+-`EC#L`_;Vk@}!OfQyV6!%Rp
zzJuZe(}fSA(P0v|!{BSvo5buleNzvSLDL+65VtJ~`i|GGEpE@C?zLrV5IpqVVoQ&1
z|1C`}5Q*B7{}5A>xMc$m*V49lQ-CVVyycw%$mDJ*-U$;0Tik;&?BXr|N@3#EmPNG3
zE8DU$4$P`87MXx)*kW-E`uDf^Jc2V%w*-8JzTPb#(kHXsw~Fb~@!Y!nGWr6x?yrZz
z!&?U^=67Uk+8C(EZ_UX>D}8H_9OetQns?6uTItqVOJTlz>s9)?!o{t(m!oxM>ld3K
z6R>URXD|`EEi@ey6tgXBEwIzK1w?|Gy{&RD(2BRU(yFk0o9i?5UEH>lHWW9u1tvqJ
zb(?My`tEIW(ZIE?ZA%Zq!mDlH&{vrHwk<Skpzr29-5LgcoZS+@^>g0v1_raw*@=pj
zgPi|;pUgYA?1KJL=V020#W^n;3rk7P&*>vwsm@NMm*Jd{1<4c6W9fO5?VQ;Gg&gNH
z%JAnp|9lU6Mb6r*Xcar}91EXLI$xVffA9O0bLJ^@o_4;ZhZkp@Ki-LfmO4+Np_Mti
zzYTKMxt9tf%ANnCJz9nH*R!El<@`RaGpe0)zXbEVvnd!pU2y*P9hj(b-bOe4CFimM
zcv0)T@(c9UId7ma%4O&3eem$A^N10&|GVZKL22>p&Y{DhQSYpN55vCWJo_d<+nntX
z5Ws>7eldt%0E1ak0Qasi(l$7IjhRTxzItX(1`r#VgmF-6WcE^V#BFAi7OiIHCpy2}
z#^j6z^AQtIMLsW?L-bB?Va><;K)u;FsH$lnTYHi=68KMWq)f@kKQr+EqfTYQ)acjO
zFs?Te$ljYj(ANH=@q5tw@sv&Io%+jHK%X|j1OI+<EdjmLuTfU>)2IlHX2yi|K$~el
z6#veurIMP@c0Pvg?8oLV2+f&C3zxZh??8E8qZpjeXVdq%z7WmC|9@#`0l4`ci=gn;
zBKqLRf>0iuuNhkEE__7m<wZT?Fsg5^(njFh{WNonAK!toB~cx4ZfWWQ$S;#7LjJqR
z5$OFsfSwP_xkVKJUNOlFLMsa?5V~q{C(Qg%w-o%<>!^lr%~daO*2dGV{L`2&@PGb<
zju8CP^AY5K)dZmTx7!QAU$<l^{{MF!<+iq$X5-&o%o3_Y-ObdGf(1{;oi0f)<{W+5
z$D27c@V^f+F`rz=2z;4M|G=d^OqCX}e$0b@AO<q2S754%nO+S~9y78iFrP4!==s^h
zWKkt_FSDA~X}j2}i6Fb#Hz&b_C!61hx%6UHsj%zKHqn*o!!DA8>B~-~V+MQJH4cz8
z`>`EQG5KNaF51O}voXye$Jr(H9ExKn(fq`-a(W3Qu>S-AEs;G>ryP>lLAuV9S)WV5
zPGMiw0y~wJUxY{+yPOV6r?W4&Lp_5H9fejV`#XJoGK<|#2a&Sb28uZ4nAv~I!Odk0
zKLFYZk&Z%T*`j&<)G2zr2cWs4AK!(+JW=fcnE9ezA&@K(U7$@=p=dc}b&5ppmYC9F
zQS|^?C8EmhKshNI^n`1tL|3RD`?Tnf`54j}(SQ4(S1MXcMYUxjGjk5uXGP^7Lgt)E
zQw{8L(R;3FRfyjH7ig8D0uByWiTY=OREs=61?YLv_6aa}LG<lBSgH}-qCD9}(MAK*
zFNyqIVX0Q+LHV0H(N7joxGbu=3PV>!?RLPtD)L(k3)e&@GaXdBE_!<yu<J$NP>%M7
z=qMc@YY?f=!Nr@RKWI1JDEi<hn7AeKqWkZ*s9^~tn?&QOP_bF`8(oBVMB!a9(IUDv
z1Ef{-Wj|2bM6I-cZWsMa2TSjYep18UJ<&bd(A^ic%r^t{foOvt^gBeu=~dP#`tkre
zABqO&L-CPl8UvBXqT^Jq@<bF%;ovS&*#eBITXc#_-=2zO8^L@ginsuOpNqVynCXRR
z(VyshDRQG+$t%$-I)eUMWTG@%k7)QEkX}*pG<yEIh+kx2Fs|aR8&FIWmwb*^x;W4T
z&<t_TBfw;eYrcg>mbgp_*G`Bhy@XHMVjCV_<cPOEf!$p3B)VH`#Qt=PUK9_G2Dv0|
zX@z91xRat`H^r$`h0!R!(*(&j@!E&<2fNzEZofkGzS!p<$UG3w_zMO-B`4&-_L97$
zOuV-wi0X*;NH)@I-A{5O2uy#8(-Dj*K+-=Ejz&s;Hp0U^d@}<iU$T&eLV=`{Zr?&l
z4xPg<k{D>!S1dUa2@55XXeGQbpOg&04ZEi#|B=IIBp<DSi=~nWVPKX?&Sb&TSuEk9
ze@^m`9ni`pcl8jdz}L!Qw^Cw5;rd$^vTmr~wpiQ;>?VtQ)M~c)Z35KqSRAL9Pm9IK
zX&|i@b#FqX%|iSS{aR)V8!A(KVNvuZItMKl&<4vz`X?PQb(Kn~B*aa+lTus0(sMMX
zJ<@zSEa)fQPT$z@mrh>|6MLnLDI6Rq{lW@lpVX3~B?qLB=uZg-NnPlDd{8=<VnxBy
zY^sb5l{y{)36q*5D4G^7&AbAKW2D*7!OfC3_JEv_PNH+|+0x@w#h4@I8)$;1Usu3<
zfpp0~=qr@QQUz*}G<yczE|$(-17}L4?T%=jldhn(Sh=)-ZifnKR~{59rLR5)vr1~T
z0N8nHjG2DJ3)0yeF|=z^)o}QIUE0=#R=xDbaJY6ux`bk<H>L4ZOx!3PL&2$A(%*gn
z%x&q&8elg|Zz#dMBb}BGW~+4M=Rj$bj-V&ZUFqQ~=({H^>V&}u(kZt=I;CeRf%#B6
zZZw^0d?am{0WaJvN3MhWhb-Ts_3&ZK_(3p3ECX(#6>4ciq46-w21@UTTWU@MCc^Ro
zWlSS2mvL|{%2MnFkr>N>24Ehwyh<NHjJ5ptHkijO&r*OP&T`gaka$ZwXP_ilUbm<E
zheXS-e}QO{<=-Y4JYjj`BY2T*`9m<Ub1k3aB_+wT{Phe#^DR@eAyQzObq@+fmT%Du
zxY)8S5q%|=kBZPbX?gfdICIKU^)HxbECVSOS8BP5R!C)*ud)Dk*7C*Y=qtBm@RBu4
zDlE5r2E|HC5gnbcw%kQ^rROc@Q{?x8<<z}s-M8$aZQcXRg%rf^wA@D9kB62wDS-UQ
z@|YZYk1dl^K)Njdc>=v|%lOxjd}bLy&#>o~`4m7Ju>6zWQG=ETI-u?%TRaAmW>=Z(
zDR|>1Ti*#ZciDl3fbo!7T!2rzWP?9KW4CPlBrrW?$(x|)C6g}#+FqId1VjR56X<T-
zFY_3M={g|$@Gv9~%5vyS1HrOd+Q+8KK8=Q@G?|&+co{O)c=Tn;T1^1UGRt&PXr7Q+
z_JU-~{OB#7Bilzs6}hq%^uh8x+3t3T=F66fz$}oRrDaT^Ov~fyERtP&0q=`tXK9C1
zBFi*E{iN*2kuZ2lmb?VcoR)oll70%Ai8hj@vR#x+DwD<SguiEH=B5aAo|7%0U~ReV
zEX4vVWQ)QfS}AMz4Wd=Di;F?3W&Ttoa6wkr1Cbip>aiI1MOpS~_;gA3(hufqWv?lQ
zSSS1D2$+{;|4fGD71>F;1g^>yPe88Aj>bW<UN)BY$Twso&G<%vq(OFQGRRF?)D<|~
zDD(Xu=5NVlOW@jVSt<pWn`Bq5Fy3a__p}YTBYQUn%obS?ojPcht=kFGCYwy<2<@_H
z8q!_a=oYl@$^Ly8nD=F&RR0htZ`8pjWO?cMe~3JKD6RiP<su3ugvl2q<Dv<d|4F&2
zNV#-5M5E*nY2y$r7s5bd<PWKI^{9M2mFmUHH=h9Wxcse9cpoRXq$pgxe7q}2f_(jE
zOjnZp!?oy3k+*mQELHv)9jMKhN7=$qfqaL7>K}^a33Ndf%e&$MdRBgk2dR<YuK~Fz
z-%a((m*ivr7c-I%n+t<=@>A<Dn9Fkan}E3@-$3WwuF4(iFu~X4?`6a8b$JbKEAPll
zDem1O51|EMt9;51Fx%wz5wO=T_r&|aEV(N$n+}<KaxoPi-Iouk1$Kwrbw8M$^3}BV
zc_@EQ(WOW7<8*-Pv3vssAD_q<hrnQ${0}<O&@F#SagL|*WIB8IOg@Ruhd-BR&@26=
z{NNa%ypqqQ+LzbzCA1vuksI#;#oR03N->Z=dH8ea_si!cqBS7j8jIGT+-5hhU98?7
z0oPou*v~-Rtd`KW!`-Te)-E1aZtuY0E~_cMnCIPAt7!q}X;nj;BOj}&^t<|6Euh82
z9;>4Lko312dl;<%s{|gd?KN9XxCCyXRr+;U+Gn-(C9wBf)oelQfYqb`I2>;EHH94_
ztbA)B8EN&X4kXGdhpN7!t*+|eXpB|U6j(ZH^$Q&?X|_5|VWF2+4OCC+V%@h1lCIX{
z;$hIudV30aZ@q3LL_Dm`p_Z8LUDgM;L($uMEA7U7tgE)eMPKXmtpMF)Z8!-N{?;)R
zdkL`ql2WvR)=AcY*=K!*P6Z#d9vlK@u=Q9UkVDo7g5dpO>*o~X3bkJD3+OQG^R##m
zx9(ewz6k4AJ76}-`gij~XdJP2T@Dg${p)mq##pa#f~8pN+rD5Pv$j45(c{)%o8U#9
zb?hG?8P;FX!#dOYbTiCnS$9)_|AaM5FSl%Kmp`GGWBn_Y{N!4{H35?O)(@y~sK9zP
zB@2tK+rER|N$aRc+FzWq)^32^OV+6Ze5<vN_zni^tdGQ?@3J+o0l8xRC>3Z|t*7ll
z>zcLA8R$1zCsHJ|+4||*Aa|_yoPl18wf}f{-)8;F7hw0TS6IN{18dt!xQ#lj*R`S5
zX+4k+k;m4N4RrqGiS<aT+U&CK9FO0r+q&{?4CaOPqd!4jTE|nM;g$6l3xW39dhdBS
z+GD+~AC`Kp=Z}IHeb#5j!F<29jP4jeo1GCL{x+J|P!F()v;^i}o9_SRt8CtV1A6;x
zq;$A=zs*!^yiosOvz~5?Ae(noz&>cR`ezI@*k)lB^bgsH=`uNN^Nt-vLTubiK|*b=
zeFe!do1iGT7GdM|43d#H&n!TqY_7F{9I*+YJzliU^>dJnv1y}s#Zj9v^v3{>*_23O
z;kb=I-6Q5Wo9JVJiMQEApEgLe*-4)=O0sGE3(RDj_bCaTV)M&?AgMOFo<K{p*|rj`
zbQ{Gij3UG4@$b;fw0YM8u4UQGr()o2n^%{C;$>@m4B~D3`Y%ZO*e=>cqqlXTFByf{
ze*PJa#cUf#WrSh2p8miNx1IGfG$L(FuHzSpvW*==gRynCfWc_n8Y+K^u^prU@=@E{
z^FWeq*Y?5D6Sl)5K(cKo9|cN|tq(mfa%~M;fKp|<dkHL6+vfcZ*UsBI)7tWiZ4JE}
zuiBdbxdRi|Y<UWtT(|Y6rB}V}A9Emc!}dTsWEyOf+Q7VN+bqS^-Dqq5HcZ^IjeL#P
zZQIr@@S@3fMg}CCZL9x-_jhdD_JFk7R?&vD&GsPeQrd0jSi+gRwmOP}-?JTi6AIn7
z*UXmz^VD|iyXbsotB8W9&uy<vL+1<I#+7Kjv^7xi$}3xEx(#33O5Xvq$2O%FdcC&H
zb};*Fqo_Qs-!{kvt_|3BN+IH+X#NIzu8QFq5OGuVQD)j*F^Q@lJroK4=-Z{3u$A(!
zyA?iX(DYP%mj_WV#c(~)ycHV-^!X_2;=%M)>@+}ek77y#u>BOLsb0}vv4qm>0Seb-
zF!w43Xi5VWNu$xXPcbqB%>9b!Qv4J_iXJL=KB#a=0|{27oW%qkQe3v7{Lf)UIOW+w
z6zvMQ7^+DA6b8c-^WKNSaK*GqFcG2X`vpElDQbqIbwsg*PT58)hI?bYF^bg}(RWl)
zxF344iceNT@0g<CHOO%VcNLc66*K5lm<bB!H4sTutp5#@m!uerT!~qdtoSG%FewV7
z54fp{7TQ>(DYyiHrYla~fkuWxPdnU9#S1D&&r&D`Fs5upB7GV;M-f7&k#iL;SHa9v
zG~f*?$ycbqf%yW3DHW|k#Uxs66)9GB!I`s)NcyhdImPoWuxBn;q|!GlDips_w!T(T
zp9h&bMX@6^E-U8J8I>!Fq$Z$URaD)@=&vbmQJLp;MLs=P>lL=`P`IJkMA5khMIu!k
z-BfI%EoP&lh_(s06z|d+{<h+H2*8>YN}Bv;g~$UUEoQ|;FK}BGR_+*Dn_~KSV7Dt)
zmP6yN!fF|0?kW7}?Q&mXn*_-RikVSpbtrzItE5x0bUn}>Di&@8^N}KFG?<SSn=V4{
ziQ@SqIP+9-ej~u1Df+LV@44a$JriCiOg$hk73TVbka?wWrX}NR#l9pAv`2A?YUW(+
zbU|Rc+4WV!CwDtrs<iO1TTW$SyY1|0@!@GVkAZ@h-RaFR=xsNIRt-LO$0^b5Yxm$H
z^!C_oT?3|{U1Jzp{&rE#up3~PPNzxs+8NB%pn-PVeubqt`=3{16bbfAM#DsseIwPk
zq}aFq0B6$dGbrbuVeiR9GRyugDoV<>|Mde{%D0cEyzN!{x2crmj{ULKP;ap}^Z~5Z
zUcVEqHhT;DMcVBr&4=Dy`;RDD(Pi(KP5IYu`#=|nzOY|U*@{>8Ih6i=ZU3JYNRPd2
z7$&IKzIi0{`|PtQ5Yca6aSF@<`&cS*8nid%0?kEPP1#siWiuIcQ#MeEg}ZY4KTz1C
zT=W3Ye#!;^VJx9a5rsO#l<U&y4^~DfXHpJ4Qu&H1?W2_UXb*5i8T>m$W0W^G(<CTA
z?}bLHa%2wd<|((G0m)YehQnZiGJicp%9Nkb#^9{-SP)&^%J;^guUz>JEj%lfuh)Q7
zDu)z9uSz*o1ZS$1Z^Y92^Stui0yHluRmmVV%1e%zl8efpXu*3)X+0aHLAjAC*KaCA
zDW=q@EZGN3x0IW&LE*NtHw~>O<xCa)ZB{-#4rlHtFMkBmqP%2}zE)-0B(&O;3JF^6
zN;SR4?kb(=fSdWAGLsTN_mxj%@a=(8s{u@ha`Hmh?NoMnK<1%x<a$idBjuRQaP6`3
z_aDG~qTG=Ry)LB(<psNydOExJR9Q=b%V)|~`k3)^CA$L(FO*MwVfUqS{3wXLQaaee
z!fRzd)o%8fmD?!**{fX84HJFJe<=soudMW-UsT0qLDW^{Hxe*zs_eHR;;tIG7{o)h
z_!dNhRQkujKBy`@fSEa@ve*c)!>XD{=!L1QreM~?RVDPoj8F~y34bG1uP(uhDAkHb
zXdO|R%~VtotvYib8ZoN*6aYD@8bW0wv8wjZFj2=;b5=wDxau3KG>lVCr!V}(t338X
zBti9%3MLX&<0-t5q-y>U&Lpec>7y+vs;{VIHC5%^3&}Lq8VYx%tC}VOB|~M<!23+q
zax;C?E=x7j4KOEEm76foY}L+ppr509LF>p|RZ}rU^Hd+ucMtMa2?b~ssDfS4DpWnL
zf{7y4tWEH+SS6;<MwY0CacG@X)f&-vO65fPo6{;+io~5!c~wHaR5hI5UuCNMN9g`L
ztLmiC-#L{7-G=2VCt5;PsD@DdrBaou!_cZ!L8s8FR_UeaJFoidH54wW+$iT?qk0yH
zVP8~rredI%R9{SiWUcC4IV9^;Hm70!vTDE)eOFWq$?jDZKM9!ERDlk3|6NxlM?t?{
zReJ#BhH7#a=AuF6Lp3`$RrQopXjE;@gTY&>q-v1cs@;8nX;L{-ptf1%`xy-0QQ6Y*
zl@`@Sy2x8q(VH-qHq~|toV2Ts{SJe7Rr$1JyQeDXhr)f;N?W@B9;h0NAk%?qgMO!~
zryUdZP_<+Un2%KVl<?xQ>X)~G_C)oB-eX;=>+~CRt7<8C_f*xPL+hC;;SZR2t`Z%E
z<O@}748UHhn)_hsmFgv(MtQB8mjcqG`k2Bny{fDnNSgap1uLN6uQGK)bU+o5jPVYt
z(&-R@3-|mN5La$C<$m0_=Ts)<&XrKY!h^dKg4QnXiX~=tH+Q)TEl+OF4EW^5xzdRf
zZ?3BwKKXF((Z;}+dq4*o_Hcq6n0{Q>`_S_@a}Sas6ToRMpmQ%bp&ph3xtrJE%s#HM
z6fW-P4(s9Y0dCg+PK<Fgx5C6hZsZFn1apzSKs&_!aT4S(mskzZ5N;H`#6!6o3!xsy
z4GF-EhI2vm%#MHsh(vO$zk{JD&ivyG4CV+|_ZLVsH#rQ>#BhO5aQ`Tm8V;FQZb=hh
zj&YU;p?I9Lqmv_X+|g8^#dD$_NG5PAX{(mV{l?&WOyY**qLs`!%z_swT>e5}rgBvd
zAZeU90L*l5Hl6><;3CZQT+ietFTn`2xK^tFJHdTJubgad(r<vt;eMlH(_GGNCP*GP
zJRj!sxf!%wF5pUz!h9j;7>iaBH-9e_in(1rXq9lo13^x5r=p;6iW|NGlBc<=KVzQG
za2;!5sFa(frM-U{_mt{I&T<PAp>dA$B~s3%u7qL*_x%ZwO70$2*;H}0^x=?du8;DP
z=ebFl0KLF{91WBjZfH3MagpmgkJcqF`z;Kjmivg7<aOL6yiFySIgbfYzrszK2rsU3
zOODa{^BT8-j;~$kp3+08o_k<{ANB?pxfU`F+z<|+H@PoqZQIDrD}ljVTxATHw>dFo
z6`HuVx#(-=jBC)k!+l95SuNbSDyX+|J1F$f#?7Kte>+!BfzP`flL*)DaVwf>|977o
zI~R%%xPvl~4$fl)%y)8mv<H94dC>WlN8C&uOg!eMQmp?8XFLUwF3yVzHM+U!6u*4R
zZJ-6hGcKVJ*w4A_Zjcw;6iS4><Puh(?-gelg4S!!nJ%jy&PdM$b1(PJR}k&v+Sh^G
z&u#u1eh&Z!WRP1v2t^nEkP?cn{FCu8=*Cw_FqiK9CaQ|{;17HN$zA-SgAm!xucGCz
zC$HEHrWdd71++K6iLPoN{<pDE_vN<_$CT{hPf|R=&&)?rO_e|Itc3Xh-i2x;_VQ~&
z!3^X}RRG<`pO_1c{ruz{h#cT|O~NDu@xM_F`XE1xA~nJM={I2T5Wl+^mJaitZO{wh
z`{?rpq5QMa@F|S<&p=-|e}{r2$^5dv!A#-JkN$&VD(~?xMALW=3KXaF0~FNB;JYb#
zo5>Gf0J~ZISF}bv!QZ5}VK)DGHyq93e`$ehx%?4|<LB`yRNkG>S5gg10sq7bCJOm6
zx1d+VZ<K-*^V{Eog%bYurw}>Gdz*csaf<(w>ZDKenN-z&hF@5VRw+N`E?Q-L*cf<m
zmUp5x^*P>?wm0Sco!x+`;1~XkRweH<4cJxuTH5$k^Wi^&oacuI1LXo=`!B{@!(XL)
z<RU-L5ek?1WziUJEx-8`-G6nwr#191^U70j>Iy%Rf-_fnyW0@G#@l=g=5_uM1-9#X
zQ6Bug!7ry1Y7P9Wvl#YG-sK%gHuAH+gQZ)1^ejl;=9?(}(ZsKzVw+}u+%fochaX0l
zM+?7>PS&*YKm1332(XRM+Xk6-{vp*w-sJ@eI`8pu^lHA(|4vWh2Yf%pEIRn1Qy|&N
zPxuf9AM#7+;PWGX+%3$-V_x$Z<OzTGQw*t#PYs1@-F#CUT2J|#*I@S<uRV>{bABZY
z?_cm^)(pY@_mb~a0Ol3HcM8nE=DVk%)x!^}F$ul=!7sq<<L^;Te?R|yE64ypbtNnf
z@^h--lZ!BaBZlTGguFz{O?dn}u-%2pVX)*O?59=XE@9(Yv~~+(x?w$qE?QlA39DH!
z&E7%{Wd(hN8}x|q6^tFg-XkohE7(uC^*6lm7oO8gCO|kxxxu}{N_xNr3M<AzVV_V*
zKg@pNUs`+|5I%k%%pgHcf!c$@CfdOS3qfz7bx8Q&07MQ8rQcx?Awtr8Oi-v<u=@g2
z6DC}DKxeqX)xcnckQoS>NFjzI@KM6^F&M=W;j|7US}1J=i4ktc!i%Fq*<m;uE7(kd
ziDSa)IJAxn%0uXj6S9AUdb|*^8qf(saurCTkXs4KBw;b#D#?O*NITF{gturBkt$e?
zMJr9np<HUZuxl}#$q+dDV_}(sW)wuSg!ObgoDj-C0yA6KN!MJCa9#suuJAz@^zww0
zhaj0R6j0>8Kwzo%q)=EukM$y<lxDqH7)oElEfMm~wBJ1`Y~BjrP6_L0p!2jKqg&>T
zFsuNrQlaZ-_*5p0eh<vELexJ1Jtuq{h@q7WUlVqPaQFsLDupD<kW>k0=zv_c;6*Q>
z^TG`kP%a1)D0EOGED=NfqR?!KkzEp6$5Dc)R+wOd`8uK159G4oaR|&SLjEn-y($>K
z2lJW`FbXi&1$G|{)(aWuF_;^|$Fw785aK@v+D&0t4kR0eC&{pMOGu=XHMa%hFz7W2
z&)$Gf&B8hr6z&M$J76p=!Vi`7A>LNOEWlu!kV4zQc42u5I`0adlz6`<_|RkezMwx1
z@<8}_I(+I7`t2auDU7Q{>!IM?0`rfA?X)C#EPQJNgHMEW#b|X2-_zr@Ti8Kskf*}?
zw7-5PX!Zg6xiE-@g<0}KSo;)yzZ5P~r1q7NSccYXA)PAbdxU-y6nlllZ_(E$q<s(2
zexY<TL<WSid<=9@h~EYg7xgDo;i0QKijw(mYW7>S+|?)PbfSk^SPl;ls2gd&8l?WI
z4}AyKpDl-;IanP|$<RY;H-B^<R*(4{tx&Z`GBm=}N#`LGu9j2eGD7|77eI?tPgkQA
zrOppQ>xla3dMHGze;*B>V$^XyaQmqG55kO9Px%&-$J7i(SdXhueG3w&{<HujUahAy
zoe5@j1+7dH)%D{sZAt2B6faIzSJ09mMLj^NiZt~buFyzVhfoc4hI-sYC}gUyzX{1K
zwLmpJC)9luugz9-TFg_9TKNS?u6oB$FrTO1Pw|(0b@q2)7N~=1>r$xRZvsk@+WasX
zoyF?NpU_#N?zO;Wa#Ag#&D|+=_oui?PODLNh}%J3LPxtx)h!=k*k$VFRFr#Gz5HEx
zaZddqJt4}~zf#3th5Af5BrDa~v^K3$@1F@$tv*-;%=7BsR>AxQ^*jpA)~IKhZv*C{
zI_M(EC3W5laBJ0WLC~*LXFP-GWp!pD$QAWBaj<(;U7?2LHFf!6NM2X>_kz@`AOC~C
z8|pF|eS>-_B?WJ)`zXNGs1Bss>s#va6!O2Vel-iNCiRR;U^c5W4HW;pqxPke^A`1-
zT|jG9mlVQ8o4SGys<x{?5kc{;ddU+o@2Q<B_;p|X^$jo|s4Zu}Qir-E8q7|0?g5a8
z>S;q^_mMiA9>|Z?kKcvCCu+Y*AYE#I`Z#d6dXPSi{8atU8mhm2rrsNX8G5dsb`xkX
z)N_A@=u5TNM7a1$?Kc~CU#l-AV4i!_(X{&RRlo5uMEcb4ehsvK^$veX4ygUcLUK@j
zLIAdlX8&1u=&Bi94+S?(EA2MiHMxt>^3X)2KyR1EzJtEMvs<&D%F;bG`Q)3Irj$xJ
zyfu5H0P3TeM4-N!`!AutN0a>$Oh1kN2{8RN_b6u^pjp)bxA$t?Y9SJ+89{N#eVPc$
zAn(__q<8rNO);edf;3{Pp**N*BM*Z$Upj%94{6qXiqRj|1W$&3h~{1T%5|uw_!Gc{
zY5czc3D;OI15AYG%^A>$)Hn@5AxcwCH_#Ey>8~-SXiW$mJc-fx${})8^UFJ6#%kPs
zK#pm4P#oj9CfgUSI8E+1@HbwwCI*-ZW=&u^&=NI2QuHcGlTPoUWDR!^4yS06--AY~
z=EI%%Vbe7Cc0nXv^ME$*8JazB!&0V(Pe)&thNY+83C&14@{z4MKMo=}n)H3}Fjup8
z5Uo6oghGz_nuZ|EZ-M6SNcdZ*G2fEGjUvs$C>Si()KC_rM5AekizhXcY1&R{x^Kga
z)0z*8fmWume}&drP1Bc<EY}Rqfx!w*@m83x)I59&y(*1~is`F0?eC-SyoL{ghZi*7
zwDPObBql=SqGoR})GuiQ%yg~SYLw%^t<zNJf?U>AQ;_6}<|e(|u4?kAMCO_%Hvur$
zHQx<It6pOvM(c*=+h`1?L382{FdH><4`WJhY37cC-ffMKBYbMo`2Gpfta<MVpzmll
z-Gp9?CQkv$R!xGA*3E627K)a)YmT0UGj}zMsTAp+=Ff4Mq5GOt3z&GIIlCJA9h!Mt
z;aaEWP9exc%>y?`KGM|Dn)<P3)Q2EXH1nT=*{zAC)bUfzII5j^rWvgT^SP#juC*7M
zl@zaisd;}mz5iZmOjJzpT62*0Cq0^X6VU3_jG#jQK21>%TK$>}%b_@+SxsfBgPPAL
zz><r$#RV{~+Qqbdb<?u%VodJZz`f}6&{{b`eV6vwHT-D1weoF{^wgdeLBvZdj)qU(
z+8@@^`_D%kRttS!?f6HSi#^)DOlbINKb->&f9-t@Gy=4r|8HBQUET!6K<z6!C$LZZ
z53MuyYp*YXhX=ITw2BSVZlE0BLG34BLL^u_{%<f3X)8E5b67j?I3z=~?o>?{s&%5u
z5p$T<n=ZC+?Urvb&k@>Sif%+|ooGi8rJYEn6i2lG(Lu&&?W3hIAEUkgJz7V#e^Y&7
zthR^7bWB@DRl~=%JE&eiPHRyGyYbqjPtZ!xdNzP0YEO*Ekdm||`5?*KKRyLXF>4=M
zp)*xGgRa0d?HXFPr)wu12g%SnQi)rpHqi?vva~TDpmjo<M`zHpwa=)+Cr6u72a>Bz
zrBk|jS|2*Ak*~d1h!GZO!%hOaP&>LF&_&uyzd)~8d;M*UtVC;*3g$_z*`5~hr?hLT
zfPGrK=@};Kj5e$qqNUoql^|u>NxA4dt9{!Da!$KTf(b6yPE5k+E3{kbNO`4JQ3x-p
zw3aLss<k7X(K@dk2#3f8Eq@P|YP24&0ew*$GzJQnw2{Z)TCH}Ind&L)w4=|#;mcap
zSJ1zrokTI3tJ<Y>+V7h71=Xfq*KVe=>3VIw9<3YN(Rfo!8no@JVB)6s$SO!SYR^$V
z`j*y$mWsEv7iUAVNjsf>*JiEv*I?e!8r0Bh(XQHrd1}?hjriaFr_ElAN$Aq1m%^!T
zZAcC@o@!6I!<lE=7xX8BpKJT+QTjsLwj1Q7b_1<AUujKe;r(mvh8Jk{XjS7N*{e;b
ziqAgnR;t(O*UqI~*?>0j3Hp*9J|7Cn6o(2b6i9Q(m`mSZ&2WhS8l9OAU9|1ZazFqE
zKeIz%J($@J6D`5ab$CS!v3!TcJzy3%xQ0Qb$RU>UL&Xk9)4?opX!@9bQHQnkk~!t@
zM?CaSJ1n5umNO3KdmyC_yXkT+bJ+Vc)XzCMzoh!Ja)+8acvIof^Ce`e9E?UNRy+Jm
zQP}eiYp8nYg2RM0(5P`}r4af>hb!|jL6;m>52CNuVd&rZVe1??TIpVP_?;4tR~!=i
z(Yor;O~u03941n}<hsMh*TAfI_=|RIHyq}@f}Xj-;WEwaO^3Dl@Vn7ri3>z;Ih4~v
z{kDT0o$+dNxON>rwK>e8OvgQkQXZ}Q4x5HT@`1xg^a;=ohiD4<cRCc%t@hC2D@Tw=
z4oMkMc<kWz2PC^30@eep+u?Bmpr1Od_!H!r*+D-aZajCeKMR=`4)f`-)Jq48MG$@E
zaNC`JUk58aM0*@e4`H|0A!!_#eGWS=!$iM>oL+SU4&v$18+5p_04OfHaU#r<tM2|R
z^ttH<@}cgo+el#)58bfc@M)LM(E=j7b!P7bfO_h3skqup7jqG!-a2j>2IHd}cN->r
zb<fJd+@teXV4!}w;k4ND*Bz$?QGiZ&6MB1fPl5otPj}=dnEQ3H^r?;mI{9RfAl;cz
zSU9Mg(+`8eI=3*09MUz@Tjj8>&+LGKhUlWQ02->hLg|k%omBu7!*yp>(1_5jo&*z-
zy4(yn6Qv8Hclr_CUb<MKbzxeNqq^8Gpv3AP{fF@$(@j-F;kYhuC#ED$_s<2mmZ1BQ
zst1yEGwJD(tn1UkP^#{Of6Sn1x+VM3nXY^A5Oy<k{dBKn>SobaJWDr32@~16hcsU~
zI?FWl<?6m0jaHt{{yh5fbx*S4eSz+3Fgz^O)%*&SB3(TFBE`C4KVtMHx({tYPU=n#
zgUBgeHAN>*>%0$A{n;7a>@yH8)zuY&Tc%q#9iup_`;4xObGk`wKr7c>h=zWJZWRSy
zs&rm&L7`fABpnLpbxL~-;(|`R7_A!J1d3f>)Q#aV372#edco|`ML&bvo{laQtM_)i
zLLp8c$KDu<e+E1LV!&WR9A{HpKHTvO3SLJ!c8-RAjN`(WFc{}pLSM&-chnD{mEd^i
zb4VsSZnTD_B**Ec08MsW{T;kWaV&9!da9!x)m)`HPNcHcbjMGkU?IbC3LRR{bhM^C
zOO~S*RhpSkIL=uH&>Y8AF*LJ|h9AH^?f5orea<+BjD%v1V@?3jE;_Q781^N{GAh%p
zb*!d!Rh{Ec`{2xF$Jw5kpev4bAAnqSET(tkHAknjP`~cjup1WY9ltAsGdCQwr9f$L
zw4yK2+%!Ax`UM(|j)i)VTaK5qz`gCb^J6GBIlAtJPtA^~=)kkvv6>dlt&acDfu=Uc
zu_ZurcUm$5Ob;gyS_JHJI^+$#-A;8G01I<kxr1iZ>5aQ+ML5Z6DIe+7PeHRNr{v$!
zcf`rO_<w0$r%kj`KI$Z=)2qjvhBN^t)#-s2Ceobz1~J}rr$tWa%W%qyhh(PHU-Xj6
za;kiW)(NM>hu}rFlTZy4B~I^AGXJF0rgZe3a+)y@q{@jc1z5Gyl4T(0ot{zp@q$y5
zSqZ-{I?bn)TdmU~+FRB+eMC>qTTTHLaPhX&RobpMISsCdNV8LP94xgsEnfkcRwo1k
z@DOu)gOcknoU(U9@}*PZFtlDdy?YYB&uga+N`&<~T{;M6pVLQYaS8N0{k{~f0VnNF
zdjGlTD=C5Qs$Vb^Kf0T~)(9`$^~-$F=b=CJE66VW;ink=ZoLx)Ouh7rXkp^5Khp@}
zqmMm^!T9P^K8M?T^o!mHil2T+AT0UoF9pDSfd2g~hy?1p3!%PGzp@{F`}L{elz%v&
zzfYHSkRH)nJgD>uvmqL+Po{9!A^lfA=nK)?e}kcg>X*6DFRB-k&=;X!O+o8p`fDlZ
zJFZ`l2utyLC0!5+`hR{zUy^>*TC`I1%V=kus_&z+{xp404+fa7*COJN?+@tT{1ly;
zdVhKfWa$^*f{Q2g0+j-0>pw06$<ZH(0a~v9-G4C&dHON-U>4{bU&C&xejz=q%k&!u
zp?+4sa5B6<r+-S>>2m$p7hqQC3u%#6sSl*3UbQ}c15nQE?^dJFd_mthh|a5e+wCCN
z^q~}Yy{#7;;CGY0VIf>=)~}<T^&Ne;3>qzZD`yyN)eqRCuTB34RT8)BZze(gu6|<~
z)bHt&Rzm&0{wdv*5A>0nK|1st9dqr}A9jTodxstpi!ciM{onjB9!PK5?#I9HaL3`C
zJ9C6?4-aOQH&k{p{vGt=Gk;NqttYe1A1yEDVF+}+nId}U_%ODqu;I%bM)8D2DDxGT
z_L37!9TkveGc6PY$YJa#L6pm6(M6NTxST*M-^>J4?N$NvW+Y?^nU6X_iWu8nkSS)S
znK8B!<`6yKPcoM&;c|-kay~>(Goy~9b%x2L<Fcj9T*|UlF^h4rTHIwEX>aSnPOu{H
z*?ClNyPLf=86uu++!cU%vF2wG@n+3usr=4|EwU!}*{L}od)S|5Lc@<8q#&t3s|$x>
z04x0vXnWbURACgz{#F7n_Oa^`VzP*2mmv*eahbg=M{Bp}O#@K8MB}jkv<MWbw_z#|
zitbN^zoDZ0%V94~Gz3v7I%sH?e6&0qfKwMy!P6(7ltFfSO)fYyY;M59(jv;qubego
z|E}9}4mw-T(Y5IO#Vp8pG4r}GL%vLrGqiJ<1GHc`&HRdQ=KSvzBWIq2?g5eGr?5RJ
za;2{{xQHjyg|}Dy&st!b1H~HpNZJwU5jtuUEuBS`nlaMkTmT-GuBFHuN~T!2bysow
z8DJkN5_h5Rx#FZfNS|VcCy2Y<g3sWskKG(9Nei_5XgjbE+4XNlE7H#CI53ad6>Nv0
z<91D};6<FBf(p{(&34@s7EiECrsZy;oo)+;m1Nia1Zc^21~2HR*rigzbE@6<=io(_
z-Rcxb7T6Wlf}FOS?+&yIyXzDiyl6M~XQ<cP@t>jZhF#S~pfuPGP<h==yAS5We50M(
z3*?dADGI7Twlm*(h2|5x4?-Z?WoOJqtK06oG#Gqpcc=*1&+MWp3IE(~^8{$Tu$w@s
zl$UmEXlSqP=GLIqV|OS5BE5DOUW3_Zx6~g7`|Vt5nLJ?k_s5uvLA#Q#0PSKQb|1vm
z-Z2G|ZuXy;v(fal_x~G~yzC?Br|`D_{Qwkw>>Z{9+t=R97Og=0k#zcRpZ#WU40OMJ
zeItIY1NQBAU^mEKXa(9)`=kdnv-Ta^X-4h8ZG}R*edyOPpJhMa9|J6~kL`lwP5Vbw
zeA;O5JV5KO+x8>UK$`3?8$ep@ubzcQtNpXjVCl8JgB*%3${7wYxJP;BUl{aLN|ms5
zSowr98&S%jb#VK*QZog8DawO%Hu!|{i%qapsQh#fB+n=xQJ$|-d440HFDbDa#JWKF
zq=n)Sx0U-S?%1w;O!4f8$}c@&_nGoM-4?yd$FVd~s*yDy-l}9uPWh<bp(u*4>bE?=
z>`~cKMAuK%L7NPJ)oVJ9AD~K0z~t>!`O{yP3RJy51Cf0y^9cC6Uv-+&4F^;be0kc8
z5~9T)K=Gie#~EnBDl00nJfw1>s>GwJ>?tr9tJ)?5+A)>e01Z^tDust}sw<Q^idU`w
z7$y=_Z)}A3iK@EqfSshe*$I-Y!ift^iR#ivn8Q@n42nsnsro3ql&&gFfjx7E>PITo
z%2ZX@!o?G+A95g?t@?aCyvR|pei(MH%9T>oc`6|UBwsZ^e@vr5WkXx`LX{0wy%nii
z==D*ol2C-CM0Ir!ES*$+|1VHZscI<~e_F-70P~E>^fvTLRrgY0@1j{1aRFnxrW)r5
z>{}}Fb!fDyX1@s+J5{nEU_Vuj&IGepmGL{U`&32uA=$5r`U?63syG48pk9S`$u8Wi
zVqov#as`O^agG$5@aG)7p&r1w<^Xdq_a{}E2XY-cDD3Afef{9n0d7g~dp8-KIi?-@
zN4N$DU`KQ5(P+hR`PR@l%FSL4W-OO00_ZWW;{o)KbGa+PjN_I|fStf`<p4|MW)(pp
ziQ7n3QOTU}06#?v7fZ!LsoaFez)a)T{tc4OmEM7RKKH>GjI4kgG}D8(n5(DbB_-Te
zB9+_<KfqLR=bu3IJa=>|6fbb+=b&|sOB(~w>ztIFxxrm3fO-Qrs|CzfZt6@p)5g`(
zDz2Tgpt${AZZr$Md)$pM_<NtLq6o(W?$Hg94sLfY-Hn~x4th^N<kmz(@e$YI2#v>F
z_!j6t;l4bH7CzQWW#--78=io9$}M;WpPqA{dV~3b`|lS__e*Zo-)Oz!7E_}9H8*@V
zM%cr}&7@zFQ&VK7kBbk5hy7gFQ`j5eoZIPd91U_3S`oYOHeOJ4<?|{a<Hm<l1-&~z
zPXY5D{IOT)^W$4-=kL$2_!J5OynQPq_wpY`0&O4fK^gY_JWH|e1H9iGa5RWta1eH*
z`Hd6-i{USj$WdM@28rd>Pw8!Vj91f%jN^Pat-s><Qxq7A=Qs61F@YcV8fc09s(t87
z;?E_3B=a||fR@5<c#X+R<tNf^H;uQV&&H+mJx3st$>+KQGm9V6iPi~zlq*`<{J+$f
z!;jjJA?5OiDJ5^t<KLmzU_So=1v3kHp%a~je9=fSi})v{@S>Q%`X5>){6hLgPx3GS
zgomg2z{y~q<|on_s2cvKM3}$G|9u#Jwfy=T=+*K6P6qQTf8||>T;t<uDj)K{U&M4h
z;={fL={56<!olt17f{JYKkx5`c^=?B{{VB4kJ<-)7s0duc3lPOO1SSPjD8Bc?!wFv
zD0m1<j=<n9;VoL=?iLQNM4zY7`UfW1OZZ_XP`ricQmFd~#rbIM5&oogkDu_?ED(Re
zyoUZ{OMtMA>dp2FXMTYBK;ct0=4+o&D@AL+Fpk1Z2ZR%$7*miimsaTqg;}|11q(+a
z0D4FemqGooaFLD+h6szZfgOr`IlPY(9u|WcFZ@iQ;{-vr9j!#6krJs%!U!{cR3ll?
zPk?@^uwMpln&31HKBWu4&>l2HQ1_vgDcnhgr7S`F957L1H&JO=##nEv;m#a;O$4Ub
zxZC?du8$9-592kD?|6Wj>7T^Vl5Swqswyz|O%A5r%%RD1>B)3>@}g;GV24irxf^I%
zlh@M<v2?N<)pV9k_Mm#e>dD{Joql(6EiJm^ri^-<P9fpH^>LIB-!P0Si2t;wLp^^v
zOv6|<1`G$t7FiRNw|W!-e%l*;P<3I#DO%vlv|E7Z#$?mkC?Ce`F$^%i%p4W0_%UOp
zfD2;wQAPeiX5~%{IfA)z9vYF%4+8X~n1xh*6vs@YFkd_qIud#bOvvAuszj!K8bC9d
zVHapPOa)yUh0Lp1w2GLRbs)veApxX>QH6k1FjLKxrmkeH?csD4Q`HND)yyAKfL>*e
zz6Z2xOgqIYuQTn3VWOVt*biniQ%cF4JB)J(2HwJqpx9q4bAAy#Y-1i#Nqak!Nx8ba
z%swYT-($i)fx-KX?h^XCn2+exNjG!5lP2ydvzkIZ&zK>UNqf%t4uhqB#&;_e2N?G+
zFhPS%#7k(nu&MM0c4bdq2h)x9p+$*1dxO4I;la8P$}TpTc2~RERkR!RWWTr!*Sy#{
z+W_s&#vFx+4~s7)VA5H8H+uf<VSlE=Q$M!a0iyow)8+6xfPMEg$X<5LKkzV+okq-k
zYyd3|_OnIr1ML9&_hKjnv7^6-$U*i^sv8JqD}2#+h_%}U6NlM=8E`a&RZ^XMC>wPZ
zK83N--(n8K*}aH2nI#eIia(%ujE$hA^Ko{eEksk<H<K_4Y3!jcXr!|~bg(UhwaErE
zpS?pH-U4<QMKB84--4k~#726-ZZZ1@)k&OXn>{hl=h)y&&?{%NDZo|1ezyzim24<|
z^|p$=OC>AjYBsbJ<{MZCDs;HXKB9$IBl}qd6mPM06p3$UXAVNKmDR0*MjP8m`>=La
zIR&G*%l_zrNw~-UL#NE|vt#K6^MF;-QNs>4oKk%*qNxX<;3-;6$G!YT=a+*SBr>c7
zGt4adbrB54h<Z1}M54$*^}0!-wo@R<qVC_|MT+PcZ6i}f$0%c%CfekPORrEA*$ERx
zBL7if7K>_T!nG378X259DH=WueWyePGtoLD8cFYhQqfL|OO%P$)30?_R7dH+b0Txr
zZeW*-Rt-Y`vS@S*yl4>VzXa$VQAHB^?u**p!F(c`Pz{ZjqDqRv4Txs{3x(a{8x5Fl
zPq8%}Me`DW5rCGrcn2M$_YuEMJ9A%g@KOw7k2vT@v<``_T!3;|{3AU#Ld37kbW|!-
zT(JXaVdAeTi4-pWU^AEzV&x&YA0^Hh28|=)V_INGi{tYE6C?i59tuar3u!kWE8g)r
zT|wfJRE3Zs9-)W7d19v>AScDs_CW8PIJpI0ToCurC3{8eumXl|ij{BCcDqH~JrVjH
z;>7uo=@dVD8#DA!{P+7%d?aRm2Fzpe{eLmSC*li3VYf^Cdn{nO#UE~k`hZxz5MB(5
z$I^P%MKUuR#8ncJ2?aOF@H9ZXOWtXOf`>$%01LY$!F{mcDfu*x?msU{JiXDpC3EPE
zhL7anTo7LgN4c{-l8d|1=O?*W2owI2&Q`R7B|j!Y<d9?+ov%48dD;lc5Xqb5Z>S_H
zm8Md%ivqsklIOHOj6^{;B%|<$?|^bd(sO~PQnCwYZp@Mx$=V8db5!ynoivV>G*c2b
zMRH{nn5mMfwBSjT%yvd!x+MP{pk+wbQU)MXVnZ?PEXmPl7}E(!#}$k)N0LjQx6hS)
zPdmsw$$iQ%<xA4qV7EXrxE3>0DCsH#Sdm2f6PV^=$%MUtIVX8<0W6hEEGf@hA^C`k
z(<&u7RD@I|`7;cpTGD$6cF#+GYKO=L$s2z74QnJTC`EZmGS&tLYbAH5!9<-zN`L+J
zvScwOJg=af94&lKw;Af!B-WIDxi0xD3X@Q8mRvdp>~_iOuR-ogmM#R^J&8mB_I*iJ
z6$bM_(p!kW4oTH8U_X>B@`nB+$<Py!d@Rw?3iyd+3SC}ZIBo~hE!mh3yMvOsRM_NV
zp-TgptHq)wsJmG#%7Pc}7GLF|&%?qTGY|T^Eb6Ez&eP)2=MeR>@ZuojZ6W>>Egy^J
zT~PG381g<q_gHxNpyg+Ai#E9-76<17Ce(tXg+rJ{X*Wc|E%N9#jIeO{8m&l+59v`D
zWwC%VoJTAg$}yH0ixC}wK5AiM{us?z3k_|6k6AbwFs9=cu}jezXVLZo^BiwccN2;U
z7CH8q#M2h1c4D5-STs|zt=i(3I(UD}V$mCD-L{xXtC4<-fO^=ClRBLPSgG{Dn*b}5
zO7?<zQ@WAr^=?bYRYKu`bjU2a|GK1WPeJjObagq<UQ5rFK*rlLxDFaVmg$uGK45v8
zzG53`d7n0I>6SyCAW~@Q`V`KTTF#?t$D5YnBQc0B%Qw#e(^GbVQaT4@y|h4xmTh?-
zUZlwk6hc2C`+6EgDr7sprLSRB$`m^w<11$;g6l8;?<86Q@=<iH@0Djc0cM{(;Ws$E
zU%r_Np@ZaS=+ZkVA1a335cw_o*h8qil}c8^<Z)9W5+RSEYVJt6!4U>y<ZI|jdQ=`V
z7kaVs2ZbPU@=^Bm*9a2j`7Y>8kssjkQ>M%FE`nsrdsksfvgC>W=*yPpl>jYAp7jx2
zL!632+IjL{=@ze&mrVsZFMqcU&Rmpl{R(|`@{~I;aYf#5hELbzJudK~UcT}tfZdc|
zri-*${_RkV%<N|M4OLBf;2b<Oc3Wjo(A~@GFDeZ7x9X&)*Iq04M<55RGUh@5pw;d%
zXdSllp_g%()h->qxA7nUw=@1-dX6$h%WhK@-*>aHrjdL<K;@^)&rzUh#g`vKcVz=T
zepg+`Nj$UUhbh;Ax;p3@I@T=BfZ4T6==|%CRqNr`PoMvWe}DE`0bhS9y@HYc8b@2#
zbze|Y(8LvDC|i8J@&8+Q)Bs_dOC$c@SwnwQ;lEk5*xIrE3;h31(|q8V-=yhuW&CEL
z;l^~Hq->ZwvtcPT{g`ufgv6hjLT8Zzm_H|?wU=3R6yz|o<4=f$Fc*%YFO=E&D@K~i
z>_~!FIZV}fpp`JbT^Q6k<`Y^4*D!9C(*K*5eQ)A_B3Yhl+oIUX)xbN#Zlu&^H0x$=
zg>DSHi-B$&JLeGK<JtT4{k#<RUo{4o%7(LOrLi1UQl4P{`wYx%_S|le9Ja6$B$w@&
z0kk6aOf{S=X0KD>X$kv+Vrr#q@J5&~V|P=P)me7TGfYVp`^`mQR<p}y)AezQ?V#6a
zE&Jd#T(4uN(xT}yTlGC;>e+MdXkoj48?6R*h5@Z6_M6YqYG(hSRmUB6_&ZQ<Ve9*#
z-pYPm54-o-B|iZA0h>W(m5<pKm%)6-dS*l6IqOMD{TJ*AXQ~G1WjmHa(M5EHo@`HL
zR{5BV=kiSCp#FDV4KPLdP#$DP(CoOd+<$PvmE9AMk+`wPmqFK^o%R&gJXlp5$S(HI
zd+6KE)=}x7Cu`b{`S4;RXq)ZLrd6WPhkX(bJzv&bG#sw%VRNW##*cNO7o<PCNdiv-
z*uDjjIn2I44~ik|nQZihvP~D@%yD)OeSsjJ{oxHdvx)!s$|=xUW{w8jcMWv&e*coT
z%gZOe341F>(FT5H>Qx}E`uimieo#|jVzoJiO3c>u(FxtPBhp~+N7Du%|FmHz6n<`|
z-S{u#3c>&NI&DgSJ45l$brCZG@rRr~6R|P$a~Lz+^9O&cExj7IMgL5b!OX6p$zWos
zUVAq)cP&%`nC!K%x0hK))%AhQbMub?-Nz)ZKr@v2hAN)J7;jsUaON}0-$gPTLeYw5
zmXeuR<`)4Zj(I&A<`S8w2ce$ABv-)A8pfX<xfhvGD!sVGI6Q}?TILrje6C~O^h4`9
z^LRGY8<`mkF->=v*DYqy2h7G1=zPvpQh7xW6L}vp{mh&-KpSL!UkZI!cK1ZMAIW}v
z8q92VK2jS0f7&JVfX!nHK7vj@vn?3D7BF*1V9pDfKegy9VwO^!VKJk77t9joUOIqI
zGS7!XvVt-Hx(XgtGKXuSU&S1xi=&$Hq6F7@W-T!<Fh?o1Tf_8F7~mq4OF@AaW;;cv
zTAAfk_|wLWr*fP}j2{K;9y7~nj$bkJ>1qF($)U)G8~bGeyl`h9(puhw4crX{KepRU
z)x-YmeR>ZDu-mL5dWf~Y1@nj5>-#XdA#4zRcP@rqR}Q;J***%2$Fg0|fp(0Iq5CkE
zT}O|{G}fES((+iA%7ydUQCDH9fUQ$Qy^!so%|jVGuLsPtY(yOt&ao<gvRlrMB!idO
zUyZ=7WnY@0U&jvp3nRSD&Zdn`BfG8%eYaTee)QdD2U4Nm#J(rO1U0h{X(#l6eK!_;
z9qe#=J#@0I6droWE?xohhz+Ez*JHMQD@2~Kk(Bf5V!z!^_kTD0HYLWMvLDjp=NUUd
zyQSxB(RkQ>!G;yXwU=zA9o&D#wr69!ui5Vxg4x4X4g*>*dx#=#eQe}fDD<;o^+4Gp
z`q2goA)-)PW*rgDPlQi#qQA+RbdeAVf-eC^SmOOtFDf*{n}?#Gc7W?D&MW|0xcFPz
z_oj;LzkxF+#d%bdR3r8d2lJLVWHb3IZb}EUSG<n-ziaWLL`w;?8<GomX|5!7mjT!$
z$=r!ni)4Hbl-eb`Vj%KB68;i4A4#NUT1RzDBIzvEOUc7s_&ItcY44&nC`q0OQ4fo`
z6aEjMv!@D+@5^a3x?+(PhPmp;w*j;I)>=TX{W%Z4f4rNH0k2=V9RC`vXq#ZFrt0J^
zD|Eoz`fnZnbz#<1*@-LDd6lve-pq7LZ}~7IDWbEFNpJ!Fex_W&SVNglUZ54mEL@Gg
zqf9piUt*aNl-^8cu27sfg*i%@+f?S19a=d|Z8%6S^F6&O^O(oSpq|ex6vJ)-Q}F@Z
zDr62EK&yy(|0Y#~6f<?+kSSrN>j8R_`Lqp#ImIYxRdAZ=NP^un%w-?gEoEYN0K1IY
zKn0g)nRbfgon!2GL9(3rJ{+JG%#yhvl}rYm+O1+TDC}F!d`uV7d1ip}w-*=%1@dYb
zZ8P-D7yn;x-yK)Q(e;04W_K@FK(WLUd+$<Iz%CYIk0nNpSO8J6ffPj(y%vb5s9;+Z
zR0Io15o{Ml2^s~lp{UsCiqb5oDE9Yzh=2Y*zxR(f&y(PuJ9FyH?wxYZnZ2wm7qz!o
z-F7Huvfy$U^N=;9e8NX;68Xon+3Vp@n8UIz(d}nB?I10W?a2ViGgj<`QZY-S&1wmI
zdjRaEtT}lH%UIk3h%RRb20_YmhL9u;5|%Uq#PbU$A?%c%x2Az4k^8qmC!XPdkbC_s
zZ@3MlDcp{d!T#p6=b|yGyn=T8={%8ssqh+4B!_DTAJG?LZu95PV0g%50zmSZkBoz9
ztHgX{`u{UZX68d@D4!h!u!kpJ2kTxQ3_*H~slS(kI*j|f!OH#o)p@ihoGTQFjNtui
zpmczT`~ocpc|Xi{7<HzPhL*$J5D30Vo<s>%QQWpM7>@8ol(!SjM^8Xy3~xgw$MOO9
zKpDpm(Q@!8U)~3b;`uHWB|UsQdx1R0yV1_tz#pwfDTOb82TkYs`rjZlowuWOi!0o@
zA&j}oml}ir8uy(AhP!;(F;r&p;k5d`$CKWnbe~VT48DBsH4Y6e;5})(UC2ARLG)vu
z69({v4<na+k)E&L2;@`#+i@^H<Dc%qsAB%i4=PIdK)QdWJeqvPWn9w;(#m-h4bsm!
zqw(zp@ADqGmz>k#i1)lEEpMy%hcwvxf$yb<=p#=Z4q>18r8=<pGoPkF(HH)DIVit!
zeMSn9e~QVj5V}s-SwrX+k!ym=KymSRa0H90!6@w#{tBe+7rX^X!bQnZFdPvZkHV&C
zkwfd|<HA6ZmlLA5F(}W9q!_TD6NAYucu5S-Mq5&a-$dZj#Lx^--V{UhqX2ISna12q
zp|1_wZVNjaN$-f`8-cqk{+a+>mbkPVdhdzurO<R=l+pcpATAvT$wOg6?;?04X0?Ot
zY!N>gk3f!Ckq44oah6h6@`MRZ>iMECWk(kXBl@mC5f&FI{!=6l(x&pMILPQ8h-vfD
z-cn&h3#2mfXIJ3L#i#;MJ{L16tocI7I`CHrZih~MEt<}T>^DNW1->t09-Yl!B`I~m
zuv$8Y92<F!6iFm&r92A9_)1SlgVIl8@ihPVOX<JD{PofVPnaJdU2hGco21%w;Bm7Q
zM^E4u=_P%00;T$qFeXasOUd2GrHCTxXNghfz(wf<{Z!*M$@38^%cKzoy1%mRXQ=mA
z4tqdYfD%p)_RY%8XCT?BD33Mx{_R#yU?Yq@d=o!t3RU)zTXK)m@D{*cB}M@VQ*I1^
z!Qsjm@?{-Rno=&|A>~tdGDgX|jmjg+vz`zdt>m8sE=HNH0bi_An_iT2R2hE_AYLgg
z1xQeq`h8zn*V|Z~jX1dzZP}*$(jF|orCa0k)D0>Ob*M)Nm8SKb2#M3{Ou=>b7CMMA
zXCwJ$=cX>jXV-K}oAbCrXXHE`Dfhx_Xg;vs;Ze9Q(Uqc2OUr$6{e3S5HGNsa5bAr@
z;W@NzV*2<XG-5LwH3O=)FhA<_KvtIn8N`|mMay=v2IS`2&D`i49>Vf<ct}Fo?i$dw
zhqZnV(ebRyEyy;o=+h8(j_srs^xrJtBtSa5O8c)2=CTCB@DlBO@I7J|Db8ESUh65W
zSjPI+fl=?+-geNtim$YV!XSQ;qKo_aTg0HNN6~t-e?~<hdy@*eLCj?`cy=*YBY@p(
z#;<rlLfD{D0HI7{3zh@Sj1CzdWQ}S1iDmUN(SSIXkqHZqvNtqc$LrbXLqI0706Hjs
znibQTi!<zPSD5!VJ4VR^7g-R4&}%G$W{m5sFYQXQm^V4v?lCK8NXuiUf1#Am{9>V^
zfE_-A1{AWgAc&6Uy(k?ghBq-n<6`;k%@7^OOK4y}%JtFq5E{?d{*KxNzIZ&qF~0Z+
z+H{q-qh);_|2!G|`@{$euZ9V}6}bJvo6?TMMcX>i8zG*IgzN(%!WFoK;tpmy`H&b$
zPx4{mzXl|cVlH(_l;{u%dyj|<6ph&;Rp_mO43rwto-s%|Mf2=dDfbF&+9s8dCv&^>
zScB3I$(n}bozhV(8e~=KJQjuqOS~o+c1aT{Q+~I!bw2clNX!PZ{giQZq%B%`z8HGr
z6k7+Bjw=RQp`TKg(h1K*Wu%VApR>y56QD^}Ud=!$Maen?(hEwrP9S}!?0Esw0PWGc
zP#>dpGDl^awplSsSG1Ea!iu}v;9j%?#9s-IrR~vk?sOkkR`4>K%`18To46|<_`N?s
zy-pmd{3j7guGfANodz4+?+&_TWMLa9AGNL_XhzQ+fSNI(JE7#~4-{J;>y`+c#sxKl
z^zrtQP&KvdMhJB%v&3~;4&@k6_i2UCGv*iKI&&2rDRVTU^S|@LM&tARUKHE+j9Lu)
zy*B58=8rB|gX-lKdP)oTW8WNs|C2qH!Lp87Qb5d~C7uUvJ=;OSoEVl}06{01sRkrx
zSj#q0n!>^yfJ<dlAAsQ+Yw{C7COb*}bDs&?Gv=~16G$mylWL+=&bp03Ln~S4WAJ^^
zGwa?UUCZydfN?#aeBk?%rQXb=&@yyuZ}fzH6+MXF+z9P{&yG<tZxze4ftXLMiq0B-
zW<F(L|HgiOg`2gCpQm^EtmU!YLFvn<)}nsrOQWF3p9j(_innpw`w+aH>-`+S5zDV{
zMDZLCFV_5XCo}lxWYpZ}D-s~%0srtE5+CwtN}PPeZ^VKrn>V9)-&5XrHYlHQpAjgP
za?3*4RmT6S&Sl{7w0VBXqke)3ANZ4zkp7XcCm-wv;nRow@0&%J3y{54*la>0w~Kve
zpkjw`AM|~Y{=uGBTW?s%0Z4kwF4Lm7lKCEj&UY;D9y;kgTR=XVDz^Mcb+cRfRyTX}
zCFl&`y?=(-O+1-axjT4kdXv~ru5F11sJvM&IezwW4FycY_|k<a?dN@|qr!Q1TWC7M
z`}Bv<XnuuW1QWwMK1AgS?%ob0C%Jt)@SWowC@PrDCpCcHRQ~1@q@?ki*PtSUU#C2k
zo4gH0XdZHZnt0KFovZur^FfM#<nWwdU}7#-i9qJ@?omMIb5n|b7w`t;lq=-dDaZUV
zAG97SUh~oZX#E@Bs|?^Rw?Bb4RdV|`;CsiLQ>?FwFWU;rkG#`4Son#*(4lfIG7@2$
zudo`1QkW>JPyHV)%zA_IFOk>-$a|uj1uV@IQe7DHTm;h|uTrFp1MZ7Rtv=!<Euh%7
zDz$fpifHNCSd@~b545h!kV5HKKOakOuhCuarIaBsZKHgZ2CW_P!xj)0BG<YL%5Yid
z4GsE8dHxa5gerJ(Elv0XI>EMm%E{4C7^cKF0%Mf2p8{gh$~ilL808Q-PvR7ZC*Vs^
z%sayRQ;L2jtS~5VDP(?HxfX)XOH!H)1jAWn#T@8OR?aj4Ly9tsVw&d_dpgPbw_fQ&
z-}{S7-Hu?qq{LA)GhK1~0*>nnUjX$tl)Y17Oombs4TEnh@y~0Zh`*n@&?0cySK68n
zFSiE&h%8Eo8+mdWG>m#m=PpK{p)c^5HR+)Fd1^;U9oxJedT88l?VxsieLXE1C%hYo
z!Y_O-&=VubnfU9REYwW$pfLC3;!SAUlq?R>ztwz?UYa_`2cjLimjOGy+!8j<_(sm1
znfEBw$uXxfK0BRD0i|<OdP&eM$JdbHviBiOoPFIJHFG|OgK}=$33?!0(?^4Jp41ng
z=NA_Oz2Fo*OABW{K>ebAPf_F6X)e^bf2D=V;+r(<cyy?Z&z^UN;kxvlD@6Z(%Nea)
z%@(XiJN#Kby|^@m;hO?g_-o#Z-fq=uoe{*fom7QuH@9Bof3f=GGGth9qvginpJ-yU
z??HR%$(bL)<}iv}w$tvP$7h#wbT)Xl=Y3e}?nm3^#fO*Rvyb~>NLcn`e_U6#Kp-9C
zc@Zs7wy>F$;1I|XCZM#7Sx<-b2o~EG=0-ESLh^qfXG?Fxurn;>Cp0&S+0bBrmgQW7
zIp<j0e$bM}>Z=fagXsf7nZ;%Y0C$fan*z!wtY!nK2;*I8=N-vs(9Zh=?=l9JCwUxs
z|4#8Me}Tckm(ZKyQaJwznYsLEGy4AJaR<s3+$Hps6S-TQqJ4abXb=En4v3ZXy+0^^
zqJ`ZdVO^lpDA6Jdtx)2H6>WNMi16zm$q+3jfZ?Wa-+<B`F{Tx8cg1m<JhMd4LX^tI
zu(wdORf<oB6*1EB>WIKmsY?Yoj!W-o%YH(7a~Pzjq#N<y=OLW+LYK8p!lB>lyO=5E
zhoDIhq)2+FM}hSDB+xIU0c}uvDYdXd%T~*2Ns#3)`*sx?zENK2x=6zV<b{qt&@K-o
z&;JfNK?lo%WqrhZ$PJMP?||C9a`GkEk}iLw)RCLAy&3xOzTAc!&pC1=ZK4bCJ~!|e
z$!TZ6P$I9Uto7&eF05RXS8~p7n6_03r!CW7rIHrw2NV}N?Ri+KplrZcMH_%8=(sYb
z3ih5==IT3v=7Qoy&bCWR2%W~btb~t%n0)2d3RFH-jB-&~t}LdE*_Vo0JBazD^pA)7
zugbK~5aX*2rconMdw`-CJGBmU>~fd36XgqsYOC_0@Syf%Z^(?)c76#d(b~PHz$Ivl
zU1<Kn+y80tkgjbK3jS+a`xUS$Lz_mM;QLz5ZpeP5jiOyeuC^)d_zJYkD3tp|E1JNH
zXIfi|2)xmHeFDilZHXrsK5G+R0<19#m;@3(qxe9`^f&5Bxf2_Wwo$&*W}}i$^!#r(
zDt!r>(?;{@NZ2K#?zF_aXLN;9+8-L_Q2_n1(Mcz?sl>=fPn}@&f)>rMjf}fMMWs=J
z3Q%QaPg~QkMydp}SL^ou1wLQhlrg}q)19W1ncH-Mcfl8>YhFE$>wJ;8hhL-9?au_`
zdENMWP<T;yl8&BV*O@+p!8dicXQOmm*NPI$vUQOu5L2WJrf059=RO>`3SDp>RJ_#%
zTY=%dZUbfbeAIPL2JVY)UO(Vg)vzId_Sza2m!RR#8iUTG5!uG^zr#>{q47rQ*&<`(
z(?Av*H?0d$X55oDDKCuAr+~l0xTQPPuQeHU7k6ue$=ja*RFl$9pbRmYMf27^lMdvG
zj4(-{0V2l4YCUlACc7hG=n0ci<XK8InYIX(NhZ#F!EnJO;WTiU^(MZr!FbbTW-f{k
zO#0DAH_xPb1ZWCPa>`IyWa4ZO3yV$qwTEnf(@<L82bg~N1`7jCt?R&;?WQFOXnnA0
zb6Tu~nzlATN`mPa8XHfTUPuRn!Bjf|ZTZ{Om)v$GralyFsWjE=>8Qge)A2T_^{csN
zBuw<LsnQ#tf@(Tru~Yq}@371c15cOg!wy~Pq=(Xt4qPbabkaewIMx08ir$#XU~FTP
z482Yw9mc!fkA{4AyD9kW6IKp!E3ei0K7VSpk#riU@!<9#X}>fFH?H&fd1z|4SQ`Ex
z^LljB<0=0*89h|a9m#?7lD~EW?lm9v1x%Iv2#wiQTt~@}L1O36;0_T7AAesvj$TUh
z#nhDR=nkjAELi1iM2^C*V%8sM?`p|fk5Ex{6Z2V7x<;csW%I_uj#Ad_4J1}EyEZ6&
zW(A9(W-aePuTEaicbdSiom{0KH45k7@CB_F@xwY=rqu5}0y-PTP%OXg))BaN&ZB(S
zp_iaa9)7wht|OkAe;;1;^)e``SKlTV*9Jo|g^;N4=V`v5Yx#c61gr3F2zMy?ocjC!
zcj%;Agx-U)f)Uz6R6*I!90tLL<1An$6eO`FBhio))_)H9chi~w!tb}Fwmtdmf5=3x
zM0JyR=`wUf>nT@2);8@a8q<Ek5TH6O%Z9iv1@G_>b-P578H;mmfweMnLGyYTe1Wx|
zIUU_$dxe}OeFpSEKlbbR;QNCzn$zBRrd@UZa}bls^S+z^AVW|HpHm0ip**fFx_1v>
zZ4caD9yuJ9`?$9qN@2VuP3JLu5N-Ek`7|26<9J~tG@a&Y%c1HFe@1zqNxUCz6wdOR
z5=5Wl^Q%w_79Hk6`!R90J)Xbn&NB9+Y!)-~ZJ?^(1tVW|>yyOvG<3%$aq<?x4G|Fw
zt(l@mYbdxU9{&yELXrIoDvQM4m5^K}`t$(h3vquwK!q4u8@FJc6n+NsHb{*;(1cA=
zmk!|DEPbG(dt3C<Byv^;N?u+N8YGROnRBajnmi`kq=;8w+%DA&0_hH^Y#&H=N_$!W
zs1m0wRj@Rhwne+7d-UY*mX^?tFGN~Ib6u!Zn_Rqmq|sj>Wv?{!AaMJn4+z)DVba6K
zAlWbJt>|cVxHOkiG9si4vq5uPZW9G?M~<QB_+9zNH<YquyAL3_Cyz*l`ulQK5%?d-
zrm4U^l&{em?~#0>C2-ktV}DfU$iC#5%afDndsixV3;^zxoOuc@`yv;;g1xJhg?bwF
z*C=1t0a>7=9+Dsjf0n=ffU8wnL-bAeR|QaPeT|0sULH>1>z)4%HGMymv$>zeDAe~K
zF#|ONwoum$N~XB;VA~u}4moZC?3j=A?woNitf6|U@WE$?By!u$zn(~;uLZ-%UF|--
zH5eA#c|)<M#S7GU&%FepKIiF;WXtZ*E@gR3n)X+$CSTVYW<_ZezU&DtuKZa4v0z`v
z_EW5W1N%zz<wkbB11JO7^?#gvJ;}?nh1Jr6A&8A27o~n1TXY>_4zPm5=%$0LSs0pp
zi21FD>ci})5loI`ZM3L7!ji*L84Vu;N-?bWRg~h`&z(W?fNePig-_Ypvyk$P?I7n^
zF>6j<trE7I8e7V$50I6y+9_Z!XMg?(@KVp_9e^3HSmSgszGKO+(M*4Sbq$0D@@a=*
z+CE;NTrG$B(OD3h%xhC#(qpcjN1FIVT2UACILd^0$>aV4NhKe23?!d;jbM~M^8)e~
zuNBK4fW%i^xP#J0F=Q7=f`mTu3iu<$hAprrRjfY-p=siezChj(ky`*V#DuN@nc_D6
zE=aa`JPpmx5nZr&hOfMT1UmSOX#NRie-j#aNLelUN27z+NQF~D=_}0%M&)M7y%zLt
zl`1u;+$r^?DE2PNRKF7@?vdK8gKhhyUd>?41*w>hXr)RkDMWEaYMu#_8<G{dBr~NM
z1{jkiH6f?mLrLulkSl3YP+24;(LnfA+WrB;o=JgEQCTb{_5pi|G;KcEze;uKMYP|f
zoWb-6$T$AfgF}^VXvMf&j+zM&Dm%~~FHAmh2>jvl$ra!@B-eL<&?vci4mv1Wesc@W
zJ}QUPx+Xz(F@W#5yqt1T4YF}9P+pc#7lSfge%=S{SLBL7;BLr&P?u!LMfBU5cjO;E
zs^7*dCyfF}w!FMOEX|kAD0*KY=TiD;p*&>m_o<*(^%P|mSN>1=|2akdZ<CUoz!XQA
zb%F&=g5?G_L*E_^Im2!(rvU_iUB}_9pklEJ0dB=I)*V-?8oMzecF#4#)YoGJvYwQl
zli>kYtp7#`N3mJB4o5C+Ti{5#(#u-N8l|^|Iraj5^f*JO^zD)l3H`2O9i;U4=wqT$
z2K=UgX5d_;peS}@?ijVwD1*9w#&kNkv>pz04oOyl9_nO?c`5{JbfL*MQT@z#Z(DOa
zclQOZ&W>KLZi_t4C;T$HyVYQCCzs(vhIVswcQ+sGw#dt6k(a0WQ0E1%?w&5@?hCx<
zxPns6sLhAASm@~N=4styhGjSU-^#+OyG1X{?v~b8*5+PrZVNos)wOx^|ALMNeLa_X
zYX0+Wsjp6~%e(!j8}zLnZ>ILH$GiNe72)nQPzU_LjsIJUYRolv^jO$+k=r7dt}c#F
zuI65Iy%#!}FR^jyy0G(Xck{W99<$7yT)l8FCwjVgc$zyqdMt4BG#}#T?7gu1IUGOf
zmtp3f?vBnbGrU|J7n%>Y8`E_#xMqxYo8`U0WyS=z*<MQ>JzUh}2K-06e??5=;ZEM3
z=H8ATUjK@?rel}5I=gt9dwMPGZe<S9|BBScL;fvEmIMEdzHh1yYRDb_8_$(tOe4O&
zR9!Mo)Ke3SOxvkHwyIgf@Kp%*PF)sg+(B(s*QCL^2_J=F!bfSuSat74u2XNml{>5c
zhh-DP)e-XNDD_y9(#i1Yt!zkLmz|{GpBDd&@K0yRPO350SRH@XxS_!&twy5;DpD@%
zs-;5IFwDxWv0<Wm^ss3^gJlonVGf4<fyN1))$kE=E5p3A#*G@=|6jY(e29ya_Z)TR
zSpK6S^qz6gZ*_)E7&_xuyHOK|wy?FR{%@k;W|m3bO+)!%)5LzNONwl!e(i4DU7ZxF
zt*fqVuGJYn7MYIG8}+iZ>S}3iVPP2SQgeq{3rlAwM{CDf){YhyHnx^ljut(vY;2va
zoO?Q3I$2p;+pLq9)WpA926>5Dt*IT$Of(vJYBi>qJvgSyHUv@EhhR;O#(`jMjb??R
z-z~Gwrfjn6nrrqm^H)z32vl`>0Kw`M0x4<~05A4cKjxW@VH$OKK5A{%UHN89d47Oe
zrvSALRmTF<4pS2d3{+VmK%hE~K%%;zK#E!cz^lU5L65;<p$0uh?O3&dfRAeV1fZe1
znt+dbi$J8>vIxLJT})uIdY*ufTKg$LnCeI%QcWPxLS@eYppZZdbw7b%wSquH)vg$N
zFK<@27DKPCT0q6BU8+?HigVS~B_K*sZxQIAwk!oQKT`E51u{%Mk0M*8)-FSBajfc8
zhFTvr0Y%7V<<-b>0K7O+4KD|>p;|$;?yB8$0F4?%AXqIR;ICS~05DTm{{wCjXrZ=z
zS&dsvAW=OJVEQW6OyiEl2wqvCIiY?jG;5;vdS%w0%~Ty<fhtf<0O0r2R9;c7b6f>#
zE!6!4eAEg8@v7ZxfD|=|fQ4EBz;C9jR&UJ4@ZxlJ4Il*FdIM~t+VU;1morq4x2V;q
z=TU@ZwJXg!vwdp6O0(Ad{!P`X(yX1_1m}8E)lF1YI7>Z-D)iceN*HIPvUdPxYDWS?
S)NusbsLKe<RrkL$Yw$nyogAtF

delta 134268
zcmZU*2V50b^EbYG@7=rg_99rZm)J|}n%GM$u^TlpYAmrQF_x4oHY|uBBG{0wh>D7!
z0*bwWAc`OzL=+ne7O?aG&V8QW@BhA^H=nrY&YYR=%$(glWzJbXJ@0?IyuY^_d-{08
z3XQ|Fi<)T|<Emi-^H@e<{_p<;R-3n4X4s9p7)I5yRx8x9O#{@7>MNI__${!){AnV?
z&W{xtRacj(#8Po7K5B*?Pz6?Z*Tqg2-?>s?*w9TpqZ;9|hFBV|q&E};Z#cjk<?83;
z@n^nOG3@9cIYu?d<sh*HE~pBc>q5br=bGST@xL3uG8StX)rNXbkJfcS^~U<-5$jo|
zWmG}+$rU#1DZCD8Kt8ZaEac<rlX2GgMPgK^8<0`fA@5f)s_XU19P4shU{uKs$PU|e
zIzY2ro&44lpj=qn$zSOP&_}L=ScYk$;pQ#+gJBm~6-M>A_GGXG4S)R`xOcL)no(QL
z9SG_ELYYy!SbF2PyZ|!nw$U7;cC(D8%AU5_5~FTnoe4s>iE4d-qi${alWN01;CFlL
zCaR2}%D8HVQFpWKrAn>u4Q*pbZ7(gO9%1c4wUb5(jCzc11pQtYsbw@amy0B6^OPBl
z-8GGVp96xXj%zOc{^l3R)UEx9e)pOLenZz+^gHPviP1Ew{e^zt{gq`j&0QtJTv$iN
zXj;^^)9+=U!S7VxK@Guv(}ia=of}XKuni0FyLSU8e@a({(e!b1^3%SB!r=e#x4jh^
z&5-}_r+cay&G!wQ4Lvsxx?|j^p<P^lV5dkjV^K4V*nbQ&g*^du#<Dj`!%TJl)`+9O
z9b;#vISIis+l6C(bpBQ>!?p`9hL}1s^D~>I0#@BB)d}C`!bpeb5;gN#MMy4;>+FUK
z^F>u32H5^D)Qt9aEpoJ}QPA#ZjoW63%sEumo;zC21hG2ukEvbQf@gwR162rkJT;-!
zEYobkE}qdIV%0l{+r0Z2p0U!i$T$CIn1DuQ7|yjRU7v=@Ji~J1I^c=py86}#E{;uK
zb4&}W`$H6QebG%}Sccu(i)Z*QY6TT_+6x_$3=&g-->UUCkr6s7^dvB<P1`h#(8Wn;
zRAnhJ-Q7tDs?~2<M(E`v6xC~+mJ#|o38RYD%Z$*^Nmx~Z9;|~A20AGhRYn7a5r#R5
zx~fh?IYt=aB-~WHhQjI?C(%STzBP#PPNIeChfZ)|ij!!~u<|%HBTQFyhNsT>g*lsl
zm6&=Q;wrrgkGZNj=oq-qOYo9$mAt~JImhAwco4YcR1L#1tnVebx=8f|06J2u_1!Fq
znJ#QLz5<~-cn7|FHlW{(>T@61@~Tg*qEUUd1~uOGsU173X5WH?+v~T4SQpjI5Y+5w
zPz|D+sz+NyxU-?CWtd*7B@T!MOmtG;s780>8DY1R7@)G2BKW;dVu)&AGTJiGNqndB
z`xS6OPGYo5ehVU`K0Qn0R9~%tPFQ`qGm}&w`};nVS~%J<2<M=xEsWQxE4JI!gJagf
zwyI4BnGxGNTa8ieX}~e!*G@vCdf6E@|8p1rSfF9V|GA5}S9lAYVn)@P`5*>439D*&
zABho%ItdqayML=0ak#oR>^Ph^L0p#c6U(H5=B{<%aUK1dW8Anc_avqX_pBkqG~|A=
zGfX3HXsU{7%ssB;m>}-#1)eEJ?|cPd9%^(jjE)f4Dh|$in<+|N5g4^r+j(Yy=x2od
ze{PWI--v$G4RSzvS3`<eqq>w0#XXI#qRLIxsTGKQ4XLwhq8eTSVt+$F5Y1G|RKy?L
zC<S6IRNL%YMhta|wN|~D!ZTvHQ>?9ORR@H8pusahw^vPg0-eZ4>Cow{s+|ua%1LxH
zIG+pgNJDxqda17X?pIt{+4qdnkTu5SDGJ*pZl1t!8tSMFf|0}fS9c6L!Mfun;VG3n
zpigINz4w*%-5L&TsbWT8Y#ardAMj60gnA;4miiqf4D;A`mc9|Y!q-FJwC&{rj9~`p
z*bR(-My4sGFXCV7|7y_)z$nx446s&dm~XDWzUWkO<%Pb!tf7(Mm#AS_H{R^~m7%fN
zwg=>z^RHU?PBe6Js9dy+(Ildkm@)WQpMK~~TQ$tFks?D6`EiM167f&F1ioo0GDc5I
zf9M#7ShrD^|3CHWRn7pYes-0{Szn2|Pybu*p!zmcZ!(G=4Yj_q(ao{^TMc8XRX+g(
z+&a|vfeQoh&uNiS4FZD6)lQA6FtP`r+7{g7nRY*VF-!!+6v3uq%-`B;`C|w+YAFEB
zFPII4u!+pI-@bxp%suTZgVBsCBS#YK{{O9JY#qER(7%r6w{4M_j<e=y(AV&;zDdTq
z#$H}3M!pMCJ`Wc|58r1-*Y?ZxDyD^S3k(d>jM~{GhHQV1>F8vlOJLMgt1iZcF%0qT
zZ2Ffy;2UFV%ntLtXKLPLrhv{J&DR3|8tq6_Gs~c2bhd)A-fa3^QS95u+^8khjRCFl
zSs;1gck>2xt5rVprH(3*Y2IcdMhBJ8tj>ph7n+;Z`TwQ=kPerzj9U|W>Qz2Vq$1y=
z=BEEoz3W%>^8Ba%g}JHj|J3*Lb+a^``hRg?-_Yzo_J3!(titV>r$>DLxHy9#M~$<3
zV>lAq{ro=xvErcr1|)$$X+HSO*HfVKdrYvUp5~hZ8Pf~N20!pls}(z^-6>#xVyVT|
z5}sp9Q{RQN_eMvkuIK8MQTwWDbJigqn4r|*Is1CwFSTkny^ax7-KgGw1Vjxd-R^*?
zlA_|Ytp|&YTBy(2pZ??9+oc1W=)2g(g$?)J=+Z!G{R}f0^#Qgi*WjjajLRbSoNpu7
zu56X>53cP8Z=Qph#eclgXgIwk18&+(oN90$e9@RW)zsCv!5TfM{oM_74YgL{>d$Tf
ztIc%(aU)sNiEFUa_qOXdbziSjA;vD85D=)rkFWm&tCqV0#kWoEdhABu;k6sGuYDKR
z?#Q0-4XW)Xd)~q<O6~FuSO1i6O6|H1Z7VHCv*G(`OiP3Xj!D3P%rO}ch|_Dn3fE7=
zWn8zi#2=5w;FujvI9%&|qU)m@60S$R3Fq+xbW+SewG>=8+UeRniFB7;CbS-y1aQp$
ze#H006qjRS9e<NTV3itI6H67PSp=8#9eRJ}90o>?S%IONWAeHYr^HOZJ#Ld*S-u24
z<{=>@Yv}jw%XDpnd&DvGJBqm8TtmN8o{>yZKSJ2rlyoEGNV08=gS<GSrI?;IqzIb3
zlG;6vVs-eD`HpEM`g{O!&Pe23$Zmpgt3#6cZ%M{DoH!Hb(eH?-Wb%g<B!AsVoEP1x
z_TNintIa677GS*Ln0L`C2a3>HWO(3u^6`&P<YVOtawsr?u4S)@lYf-dzKkNZT9|Qi
zOh7)l72rd<7hlouF(KqoYiE?@k)-S4Z1&tPgj}<oWLo@92n{3XI<}U~I5_6p=j7=R
z)ud31qg!yLD;aa)$@dFZs-5?lOuF?YwWl`-Zf_jbHfl)xkNpYS!BFi0%tX-!-&5`I
zj}&)|H_2q3BmA&@LLS?m_<x-Qj)NIrhnn=1hCqMLB#5HL1o5mrT?cHU>(q-RvnY#{
zwMGK!i~gBo$|I<D<aE-F`i`zYJtxV@&YL35CA6<6kt@9?QW#yVRQnhcVvdn3$SueE
zW(4GYn1C(@l3y*8sbY|ZjOG7HwU-0wdR-t+=|%b-Sc~BPC?t8yK)MCvYSHz_XyWv5
zL9G~ffMj+$Z|itxvuk{bqYk0~*f4UUzC%x<PqIk)+zxW0{4B-Mc)K&=E_AK(BE$YA
zRBP)>5Px4J7u}Nx;*UEN->Cldd&VTfc{q>|rcv`Uv!dym=S$aG^{6(%$sgo&G`YTm
z;HoE)nYp>-dr1Rld+?+%#TiF)k@$53$^4sUWTx;DncP)CT7Se7!d4fmHSH$1!tc`c
zyQgIAy|Zsv^A$zhsu@Y9DD?X?ma`nAT<7WeZ|X({;+_%Q9Dh=Kxq!?seL|w~w<-GE
z*<^AyN52(k+)sv(%(m|dXzDHcJtUB>;oZo^?I-E_sDjY$9wg)^=LjL!`9^%-idwzZ
zYBfFo?VK@f*hZpK4v9YUAkl51#QAqBfqvhWIM*gn?a6)QMD-qOr#H2T|G7WG@qMTb
zqIjw`&LOR`VI*JVd`0tLkwcNaNwTL?{x`DgU;=v+(4tJb-WSN^wAmE*%CW@pd`xQN
z%c<$oW60Rr83gV5f+XWG%yZ0=i6rTYNefJVAbt=gY#if*Sq&aH=gV29b0Tb}mY#5p
z@E<>?-;R7|XL;-nDSv!G{?<b}0#7wZhDY8alXYj(H3kzEw1fw#_4%I6JnTX8D`yZV
ztRY>;uOO|;eRQ4wl;kt(6aVlvGXKtbE5Dyh<`ddcYxQtkrlQ$!V&(3n$R=$e^QE_l
zGvhvSnmD_f+A89R7!&cRzM$Wc{iybAHW~PBI$eu@C%00aPGqH!$;XWeKP#CeQ%ebX
zTUU}1i;4fVyMu^XGsx3FWQrySQ)xV<ail!iK-d0FNM<-@tmu61kz~dhl01tAImW%m
zbiZT9lO(s1+-ej@^4I2)Of#p<uuzimZb`MRCsP1N;;Ht`ONpNU2@?6z&5eZi>&Vj<
z3K@%iO4poG1b1^I#kZ@1WZpZUfLI%uEOk2M_Z`Ws8A;bo{}MvxAd0p67t(U^CH{ut
zq<d@+VM;5Bb8EAfp8tk51eAV_Sd)GuHSZN9nwm+<zi%K<!}R3!$&D2K1*FtCW-yk&
z98)`(T)#hwOmYeId)!7s8yrnIho=%w1FW4m=DhQL>3)xX`(=`D<Oygwn2O&CRC}I`
zjTl7NKP)8F^*CLZjizg@ax(A~i7fzqBJ-BUB)RBc0_yL43Flx6gjcIO8Gf^hqTHq;
z-6Pwn+2fF&K;Pi(AFUrqw<MP^9ajnoVgr_ZSQBf>mBDFL?R$xoFD4MbhnjxBkmz^o
zz7*yA`2_mI32K{NYf0W?2FX01OEPm}$cg;J^gAz!<Ub81$xHu|>pNbME9-wHtr~}e
zDpnvTgU7HRiAGE#<={}_^gQJ>?@n%o4JCfVb99~BkNCTs1I)S*g6p@Qa6Ty{Iq{&=
z4AKo8(-~O|w82Qax~(DI+QGzMwuum4BsxeT4|yFljta{frs+K5JnBlnGuvu#{r!l5
z>&7e=*J=03t@%fhe_}R%mT=AQhZP6&+a!u!mq|@JF`eXlOd-s^JjpL|J`G1dslXrH
zh#ZanNKUlqC^*1+--^`QI=kD;P3ZTmZ=GuWsXeCGCFoIDbZME*>nIMNess&yn$mSJ
zN9KKNlU6J(ewb#z()I42<l@tD<aFvE<Y@3*Ev~go$b2x;Oj>3Na%Fh`XC#p5_@#6|
zre%|X3g=vQRBdW5eIV6(4xwnSttRF3Khw1tCTdz{4b~SNa}dwAmT8OGu$GxTmP~#*
zLt3ZMNu$jkQ{3TWDdHsOEa6ZDA<v(Qz|j9A=Z6W_V`}!#HCWeSWz31O$#6v9?-1fL
zWLh9${DEdj=0%f`A0P?Wp^<2vW_aisu9Z`+|DaX)J<cN=E{#9m3r<e(J%!&BJ7KlR
zO=?Ab!Q|;kQgJ{0OONc#mq`NN|2Zlejg}<PGq8L*5}2H0-(o1NWz&YjK~HwzZ4^7%
z{Q|`NSx+nE0@$d!pmwpkWJvC27k>uc9`^EXxU`SewScFA?6jY8gZ8s)k3c<$-QWeo
z!L0XFNQSU~Plv0aY*ijTe_`y}THuDWwUGSaBG?&WC=Rd(X?#4$UPaQKi)2Io0QMpF
znm-hx*t9s9ILuCZ1MDMg8FlYR*-=RVjb{J70_HKcaeYw7*?bx(Pq0glLNA6LVnW?X
z_D&R_W7*TyH2;ocJG+2;iY=qA{4|@C3bZq9B&GS{*`c3cK7sA_6y_7zj5ILMva!?;
zpJSI+05pmH%Lugdtc^OX3+(upki5t)*bnoU*v`jL+-9@L?j5!UPaK!Q_F0EEyvxo`
z<<b6`Yy%EWlf|0K;b{&Vyb{>C>_69`n8&W8{x6?h&=JLbcJDy6`UCbvbHF@gm!5_~
z8Jp|@4<EDRJAwI}og5Cma@K|B{4d#ACRnOqC-j6*m28*2kbK34cS7B3*0mMPI^M9e
zKY)D8j$V$+DmLQ}n6GBrw*>PYyKe;aKd|o&V18t;i!kwt{pK|!YgkvhzwWBf-N0O<
zy0`}(Zc#lL{og0J*_$BfbpAXMcXm-FO_>(!UjuW=qOI^{X(c_`zg_O@VBjwPZ!};i
zMB4dXL5sG3S&3_hF6e`}j%&V$u}&xG;SFMAu*xHGt)}NOnBykY!Mm>Qbskv!Z{3l<
zAt+6cMF>pmO;dMX|1+!!L*9cUIuxWhNTT6zjC@>+QNxgT)UIV$)0%P}n}~rzyOCY<
z5Fu}3Z%sijwwe722?cHoJ7yT(?Lan(Cc*pJ014{VtY#)${>*04By+v$^iPo7tQx%*
z&iJVo(1dE2swxlEepQG+yp2|E@&a^{>W_oaOHpy{k#EQNi#NQhKPqaUUIwX#eyai3
zuGvQLdj~ay<k;E$5d1>M9am4b&mg!E!3HmcY$6+;jv&+6v9iKw->{BH|7`+k^%?*g
z%Q1*(zskx&gSDQ5!A0AKvQFBzlg}Wj-HvvHw2t-*W+1c<pI@Te>iGD3v{R?31~Ae2
zuM9MNmx6Kd<7@v%@T2Sa>u9HL*9vg$o=4N09-|xKdF(&o0BVP|FM!sVE;PnWyU+_V
zbBDVl_@(ZHQM;mz8GLv4#{>kokv$awY+rWXFd6TkKP%FEAHp7Qg5n7KZZcwuV^<)%
zsXfg)y+6Y`-H&IT{wJ``01{be1ZP?DT8lT10=dLeB+k1m&1?o^woDdR*Xu~6b9KhO
zh1U)5eTJt^E725ObI0FJ(2#Aar{dZn*B6?dyyGdrUXkGRzHu9zzN3=h(SVVg05P-&
zEwn}+?2XXIw%>y+8Qs8IjqCuf_xLOPZv2pj^p-8I;@ZVyJnlo^R9aCE9Z$>GvBT+&
zT+Lpk`M5hf-GNO!ZVmg>FCYWh%QlGYV%rA5wcTtI%?d);de~1yU-`lXMHt%~gB<$0
zzez8e-H(SJeciE6s5{N}RYUy@d;1oOcy>@fSiQ`yjDXu$*b5&J^i}qkF9_u>`|C1@
zWU`4xwEoLtlgB~-5j&Tb5M^wH4WN%%m+26#Vm;qLA05I^F!+wm$pLeNs;~|uJygcp
zfZ3?}Z8n%YRZp;W$oZ=Z69E>W8jt)N7ojpeg53kEv`eTvsNyF;FHW^62qLFc{Q@+&
z|EE=tXsviv)no!fyQWf_gSw@<)e^-$RnPHY7O0}=o)xOvkba43BLlQYs*xW-JyYGS
zi{`?f*($`cTD@=&^wz7FkAQ-wIwcdaY*imEgGhkdtVP`}^}QC53{%%WK=a>l^|a;S
z9#@ywz|slzuDJlcpl-em`WMyBG5L4iVmIMCC^b&41lgqTAUp(3XNUi{u3tAyh`9cP
ziePKN^c?&i{2hyynPWu8(Wza#PZT_Ec|07Tt&<x-u3g@I{O;(8qzp=zmXs0cb|13_
zuBY)=aQghv9M#{R{~ZlAAoDnWf2YCj6Sm_pXme9DXn{BDtQ#C(5cn%(7T4vW`<u~(
z+63+Qw5&<g&Mbt~S#8`DfM3?GqQH{1)7zo$j&@=Y<a4yD=VN^@w6!?4=pf@GHd=(r
zllouJLo`93+7%XkjM7+8JB;2L|9#qzvLn7m1Uc+X?8|Tk?8B)LD`Y(|oMDU#m<DDE
z8+{%P@PJjNpxB}6g8e%5iXl(np1+Exrzb!aLwT&-s>!2h7~G>8*bXl2Q*D;vSfJ{y
z0lo*REOWpNR&6~C(NNXMMF=%a^;06ej8&~DMiHmdO@zVQs_JZbaYv;QP~25*r{!y=
z>Kt~C@esYGbX&HnjIwmOs`P7cG*8u(l7$5T!+muWs^an>TCCbbdAs|nc*?pxP<=cC
zv{Kc-lo)-aa<32bWvXA|5YrP?z+XUns!HyO(4MQl?+Ar*)oAPq;~}i$jXHPri3${J
z)hnj~Wu1C1I(u$|`jZao9_kk~dq1e==+%vMsGHE;xugD63^GGKv?pLP)k`#>ved;{
zD6-WjY1x^h4x~&)o_ZxM!SmHyx1cCg|2Z4#MQWb<s}gmGJ!t0#YW@(Yhw918q4!8#
zQ4G6})fr6?_7k-q4a3jWMKtm}S3CNX`4{RmN|L-(zj8xSslJRIdhV5a{1S-1QGZ7Z
z$hYd=S)i)b*CjORJM~5y2R^7-N?d$YcdSIbpVg;ZL-LDy&Yy_TT{Gt%B-d!>dV{%M
z)17k38#JpAz}`kpsU8+KX|_0aL4S)TuMDK8CJrwa=cTDKL2;W#tbwABrp_HS$#zYb
zb1=U{b9*Qx{WRl$M4i8;(HIl~8gI%(?9rrELu9Wei?Vrvnr;u_#eU5;iX~X{TT}QO
zqT%iWI$U$p2VO*IuH2_Pb5IjTX~swm>kW-4&AXM*IIQ`hH>jhUaczMXt;xp526tQ&
z+y{y$G(AUwc~Wz*4IY75%}Oimp4RxSgEMC|t5yLlK@)ol>WLcHWeEG6#%CBXlQhGz
zAIV+N{D!pxcTr<~PTk;T&Cl)N#TAWuB#LXArqzJCu9^25qRE=GlYyP0nKA@LswU(Y
zh@@%WR{$+tvlRP8+-=R#2so3WiK`8}cQyJ-M3|-N@&i!rX@Yw~AxGnR7DcXxrzBXu
z<_0Br3p77ore#2p=3ZBz6>BEbn)89?M+;y|HP&k|_(*f+SJahhj=zA3Cz|W?z<jE?
z=LV5-%>x<{Uuaq`L6cNyyuLvLRciXs?C-T^M_W*DG=U|ktI`b1fL^uck7EFPuerYr
zbsscu?gP{DN#hX<w9lFh8ZTCJ6KI*?&N<4VxR#r=0gbSZdpa1*4cyo;w512vy$$Sc
z;#@{TZ!=d-O9)SHb!SL!<z@!J#5Rt#pz!9pt%lxqu9XKUUvA<Pi0tIb=E6gN?yIk$
zzRSU#eGcw!uEr18d%3nhLUbROgl#TvKi4`94IIQ(&wxk>r_f$WD0h(>IGj7+2D=g5
zr&Lgp$i>0ZA?`k{P!DsTZb0$~*MU~$(cETQ1s~&j(aRCT6*Pi{liZbu2se&%G;57V
z=oA-O59Apxkn+LtoQ77_iCmg1Ts+Ht{uBC1Tyg^R&vUi{NZ#Yd#)Hb{t~~*j$ED1N
zUOxAY1<XRudm)M<uB-se``n&`P%q)u(WXf$chms4A98ys(NxCWa*RWukGcD<s9deR
zhl3ZKyY|LnFxP4)AAqOpv|q@X4cc{+0qUV`e-a{_w1dhJ_Gay<5y0N6T|oIVFYQOl
zSovtL&I5D1cE&we^3#_50EL~}xs>k<&<;~WWS92&6^QK7Hg}``d9QY<44HK8h4G+n
zYeV)z^saWJ3I;Q^TZ7OD_q0cPKqFflco$Tzb_6A&^R)55L9#%*cr2(wZQteaw^%#A
zHK_aAa7qO|&@Sx*gQeP%VubWan@35wGHqA@s3+Q}i?j@UsvUC}iqEy3*Fm&gTbT+=
z720STbt|=Lxqx}2J@5pIZ?y$4A^A?*D+XS?*Di5|!Y8fAIe7nBE6xK|qdi3FrPX|4
zYZPnvXU%YX*YdkNfI7-wA!al`<O3`m=NGRR@&29Qzmx*)B%hdrcw_m?w1aYrZ~qC@
zX}(Q;*p25aX}O)i&+G%{S-zAu*v|3i=A-UB--q%87x;f@u6l{LE{Divz8j^`uktbN
zA$g78L>bN-d`u|pCi4rZL%qqLUkwFED*xaI7`(;DQMNyw4~~S)9sV(;05bTlbni3y
z`MpqN@t-4roy}KOgUaFOnV^uzhYSWxKEIQua)tbQ9E9VF_+iW7+I{}I2imZNKh_M)
zhkSGjs7L&jbf7%p8$5#gQwKkUb{fn1i8x2Xz2I|(L$s3rauHs<;ypT`c+2Nf>ZpqM
z{{<rN`J5e4_`v^3x!cctF1`L=_(5ACvRYV*BV?SrFfbd`TH$OJ99<`*UxhOp1WO(Y
z4?+4G3Y&xhdN{LLaEzvyJcVvIptx0VcR_n?6A~jJ>MiKjL4Ui@`yw=ah5dI?_zAbx
z!Ka<VKQ++5D17)8VP6vXg($8H5vRbsCbUX``D9@RB_LCTc4{zFg{fv3N)ui-Ly<0=
z-;OwM3k@8DfR-UJG#cL(5|^R4CsfmxS++2rCjPlXV=rLm34e#ce4#L|m>O7E*#lIG
z(3d8T4}?Dn`=QXZ87w^#`o}~4u@KQ0&`*TRG{ij<@?Ig9=fW>9Ao4<(Hye5{g`)OY
zhI5sI`zREzghp-P_ZwkAAGF0=q3aMZ-w7{H0{gvS{2K;83iS#>eG<6#K&uft(!zDM
zIDQNy*N7Dvpw^0A7XW*`IE5O2gP5L;Vx!nP9YJgo5AKFDTSUhISnw1l)<+tU^Ac6G
z{MshAn*~uH@ty~$?c$?TfbkPcD2cpNEXHvwE<l_Y2Wpo%lGYu2#kD0s+b3QL1v5yT
z^aUcpqH8gzP;nFG9Kys^PvCZhSdV(N1EOg!>LSJM^-y<6T((rg`*&CzO|!HkV!z=i
zqQ$&!z&<8g={<-M|C$TYlVbK?z>X778({F1cy0%R$r1yoPstJUXs0Gu+%KT<^2P68
z0i{6vJQH?{#9FVxEEfAvg7<;=%@pXBid$)__ed0WK+jPo_E-w+C*q$p96l9yOa!-F
z95)d%FT{^GK~;+Fkcs79iTkUd|3*ASn;maOG%N;HG4v&hcVdT;2<@Zzz7m!`i3h`B
z_lvkU8JIQVK+2-KOP+@SwnjSi9?<KgbM;WS-XVQWowkSc;tOOpO8Gb$!)=x>y@%))
zsh)shtJLZUM7*Q}8aV1L#nJ4}N2>IJzOU3}BlLDirD4$9DFw8Eg1^-HCKOIcqxOLr
zBh^rM6)P=fAsHtbr^DaVlDjXwI3qcJr&lIHnm-;IiPCbUEVy&h-GhKhl0yH4{spPx
zAS_*!;!c9PEOi(Mg)36KZy|Y2V$x7|T}t~1pOPipHh`u`*QbC=ljhO7?v|vbo#Z=G
z?sn8=NKp*D$do?QCQ6o+?HCM8+0wJG5n7IvegG!&q%~b3nlDvWK&D7)G7wa;)Tjh#
zB~mc0RUb(I(1zqg$>mQ_kEFjE1N5=9gf@GhNVV?(<(YK79Cgp7E69FxFQib~d3h<-
zUkR{E>0Tk~UP-$O9PsUpG#m$Lxwq0qWUaY((!lK~-b>q%`Q|=KKgh83Nm^bXl3%15
z&4FDbm9~N<clj=5@Ycv}IznW(oUsNXdt@(q686a>H$Ws%zFHe7L2}hlco8i3$$|M$
zc`i*c!{qs)n#p)OWbZ~G56A+})^U-tsUN6A@=aPN9G11;fq6u(Qb0w^<7jbqOt#Sk
z@Pz!25td?PEiDRT<rRO@{gqergx%Bf_r9jyR>!<lM4cqZ&PUaGxjU`fF3R00i+M?I
zb{W)F`IpCNifgix2I_`<U@x$e<)(E0<EH%fD5z99>I$e^@_Cx1q|1hzaOI9H&@q7w
z`7_<?OnKWmsAtKs4WW=NTaSUtk@q?JLorWIJqyKrIZXq*h4N}jC>P1&&qDFOJp3b=
zCGx#UD3;1iab%f$C>PRkfigLh(sqyK#dD$lR31<Jvd`qE8a&OP<*V^%m-R~XWhk~Q
zUFM<9e3hnjLSlz<c^1t3DgDfp!QQDX=>miPO6N3G1}MF8@{Zf3e3}9idz8tuLG4vy
zTEdHc%H%Nk6sR1gMelxP4mlH~Y+nSuVC7>IP$9~r5?BgX%4(sAP~3XK!${>DI{a`*
z3HSvlH<jbAV5TY=GjVX1OH*>`iNB?6r*1V}S=kB2ZRI8dOLr8@U!XFS3R1kQ<g`VR
zsl?wwk)_P>Lvc?Tu^Pb?D{c)y-B-r;Mf9c0COWb6SlQVJ&`*@UeLy``_S~ihQqEFB
z_qk$tsX^~ruJ{N2H(BB)(jG&j-y5Pe8vj!t9yi&Mj_8|q`v`xV&BqCDuDRQ6)VBDJ
zjsdicyAQlp9<=fG)y*f6Y3)smsWyK;gKpcCW;AZQf3WGpwcpwU@*Ua_2SUeb&w$x!
zJUP+XacK_Jx{TNYg|EvBVZLijNBr(qzZlo<Ts+`<gdm5?^_<ZPVfOl!_Dy<sp*(2c
zo-(fA_|cR2?c|S;>=!^;{Qiq3Kytuxd~3iBZ$f8lCKcYo?>T)Z!sLotdLXZ1RrL03
zb+B)75R)=`vmm#h)qBBD?0OsnGm=fCdw7&xr4^u#|2OmBJcQU5{yz1ap8TaMnBL0I
zrTK#w|0@l4+xWG4sPpERQ+mXQ-!vY2+xh1U;F2$&eg=R$cwfpa`0=_(E$;tLerZ#P
z`twCBoDbj+#i7{4FQjGkUOu%i>h|;3Xx0|QuWExLn2(}H2;qZi-5$<sJ)jW5pUQx1
z2l$8ws5{6HTa3C$zV$d1hxi6R!;2{Xx+m-&=3le|<`I61QHA?|lwU|YAkn;oHVuyP
z7uKNiIR7o>_)hT6H=&5(H8`b-3GkYRC}R2Ew-9d}AMpqDPVrhROq}MkXh1r{H>Wj0
zJRf}(&Lr@sF>&G&`PMkgi&^n|n%|w{Z`vV}#D~8G({Yi1PA}LczEcNqFY}$BLgotp
zWi*&q`Avgi;u@cS34UMamvu$U-r%QaK{17Yx)~;J@>6LGHkH3-Ly^YU83^@TeC;Cu
zOXs8TodI{7ALE6(JG|nCB9s4_FthkF29e!!@IzyOoz16EFPg*WwMUW5f4vZv^7vmU
zgOktyRu`ZJ{9ZC&$ba7eFhzX7f6%1GeBWQ-%zb|MP@t6XDjbUC9`MWF0;QC{b{usN
zc^&Q9KjIrxYO{=2{{_j%d_yw(gm-lQg0_6h_r@0k+%vv8?fyOINB)G$az3FMs299X
z4a~pf(@&tN;1|CKXeEDv^7OCx{k`GEYhF*Q+BbZ?lhAw1&nSbzD!wC~2dw6sG=j(n
ze%fOcANj)%Q1^w`UVvl`f7L;o@2iD77Le}3zchBO7rK)P51~^sij6{UGt_MsexNkg
z7NKz$h<FMaIjGwzbfFzhFJU<~$u_}P!rk^33f<wTkMI-Ck+%zf(CFwZWIuxX4xt-8
zL4Ly2g`oU}H5oLz1_&+4w_U=w&tWN8xVi;Jh%n(46hnoq3D5`=y3kM`F7%}CFhcli
z8Vnu~R@a5(L1DmXphOB+l2CU@&`>fgN{IRhM-K}J>A>R=;Yod{9~F-L29aptpK(w>
zCX{`lO^)M2|IILQLdc|<bByr57i3Nfax_3=g(<YOh!YOc*{D-O^$38T7B2Jvbw-Fy
zf%$l$k}~}X!Uam2BnmEHL;bAKjAnx8gq6>Mk|cCK2=nKKnAe~#2sb9c&_&?|4m&uo
zH2K~Om6wH!f5EA%!ZzBSzb0(?4QSVe8XP0#ZU{OKb;-g3>OWJ2#B%806ttB5OBIF|
z!C;!Ofjqn=upwZk3sc*oxGk9GK=O`YD2955FwFvyyTbCxz|0ihbU@+A68siH=AO_c
z2iVzyH=WAK5t<#xt;`jA(>cdHq1q43e4#BpECs?NI$KdFv^)Sui-cku%ohtQt|H$1
z!azEkQ6dyfgZcv@j81Tr3gP=8`B1ozbHG^qq|t$nGQsUMBp*8j>v)Jh5zb`6o2SCP
z_ptO#Sk@Ai&xMjA6y?GgI-vDJc;5y3FNG?6l)zO8!)ZEFDLi-sg;&DFwE%rB%(5cT
zH$t76kbEl~rXFIA_>7KK_=|s^hvaVYVq4hTBZ{;?wpVma?}c)oID`7RK+!e<q3svj
z?1O%g$WX>9So|>z8X;m5?SX}g`rB|cOx#V&yKpgi35p2u`3e*V#F)cSKPayL7GRO$
z`-3PBiCHJ$T9ml|CF+ifS{faq#WdQkJSI+Y+y;4E>_LzG3Gv&;up1*DzYOZ6_$dYk
zW5wTB0VYm7M7u<%#C`N`pB6J;fq6!Z#W!wTycqKp>Jr4GG;>H4^J#K(R*YN)pU#Pm
z=@3JbDAj|Z^Wxl<kh~!NI31D~#rz!FjkqK}T7u%TSRx_bE8;R5tFMav8-saGETC!p
zb#d4yDBckBCP5@wJp2^TMT$6pdfS^~5sludV%SkgritxoBlwnh{}~)j7q?}?!`tHQ
zZ*V8?h_O2WogubJ0@z(K^(l>inPPw1b<GkLO0C@!KN4uR*mN>Pv3A=7OS$4?Z@}b<
zT{nQ4FWwAAOa<a93batHqM1jL_|+Fk7K`<N2X$XObPGO}iaN@`JQN?%`HM$l03{vE
z#7-3MV{zy;djFn?t7)nIR9s5W<umaYN`5>Sm&uSR7u(a$#|v@&G+@6JYi^;a5ckvG
zTBX<rpY&kO7g7qn*WzDvqVSCvM*CQA#TGQCR*4h$fLSfN^oGJaG0+{<dr|%wZTLa-
z{05Sak76z*r9X-N{zaR77Q4O%+7~ejXLqnJoHP&SS4#_MKJG5v2?yvJ=}jV-Yo%ed
zL|-QjOoQZlDWnwC21%ed)kA7<7?K;M!?6f^lhmHpxSORyJ)pNp*7H#Jl+r`c7F!+C
z<ydgNBs(3=*d|@0%$~OtGZ%_J(hJ(m+b(%*f~c>wm*(R;rS_-6^q0IZ0W?4g3j?)F
z`cA@Yv|IXsk1n`9(rd!pD;;Zx$o5I~PoM~tmeatuUm86Ju>?sMRzN*iatz-HGDPZ9
z2os@_{a2ucNqcD>5ia$hd|iaJu|Mn{kVesA?}O6u(V!xwWIuR#NE$)Y`Y7p}g>d_@
z<T@VI5viJ*>!{S4-mz%Og^tD@liaF69hX+oS@jdrxiUB!Bh7cvH0Pvr#0vAVQp^Il
z7$>dz0s5z;yOgj#Ev=`;-WjO}9a@i<_U;5TK{^)<&_ro-3G~iNQa+gHq<U8&nIw&+
zQ#<FSowQiHAYI%5%!|@KTHalfV)KD=S(=#)N3TfL0hC?6Dy1BOQ`e+rUr=0^it!B+
zcSD*Q1u9v}8w(RD($rv>NRzJ66L?FCD@R?r)HMo?cw6%M2+%vy+}|OYA(@-N(p_l;
z?So`W9qANvmek-F4BnHT(Yu)~-Ruv&94YcA+TF;NGC!a)PrCU%VDhB_v=l6mI^0Dt
zg;EKfR4tOs^<lnP3Ofjq`%=OV)Rjn$2cYhO)OI_9D3wfqf%#C1EJD1Gq~AM0vP=pL
zKs!B_g3=-KL~<X5x~EbqW#pepIXIK#!1_D?Fk&i~LTRt~h4j`B)Jtg{6&2D&oSVRE
zJcZ6+y^_A8gJrL!DLo<iMv9vb=38mV2w19;+<L-%wX}>jirz^^^8USaox0!;(k~03
z@KIV&3kshkGbM*UOA>8TIKD_Ol#8#CwA0WutL4LF!d?Dt3#c{nV|*UPt(7}br@KyG
zp#rsD-biWl4f1$O?0d+IC`-CgZgm|Bo8*89sC&v6Hb7ykyzMVgUUC#A!+hipG`rd^
z$I?>HSLSK!VW&eb_JfSSJZd}~4v;6)9o-{8>kaI^@>n_wyHAcyL=hyPp-FtOynHtd
zhREr=(Lmwy^CD0Ya?5@|J0RC-1G|Uhf2m7}l273KWF!b4)`jE|`8!Iq9hDQB0xVk2
zrX|EN%zx-y|8e<Sx+N#%qbC3pBae=O=t=p-b-={R5rHV;<fW9|IVC?`3jNda@k>xR
zBOgdX5idV-fnI{VyeU8v<<w5}R>;;;M0QS&eFnFa<YIh*h77}>f8r6iAdeje$%}H4
zBMg<7<hztdx-18~g1RDS(-zTH*+~7|HMvtaw9IvRA#Ly7kh#q;pDbG_QI{h3UIV?G
zavb&Rsq)$yV5iA_YGCP>>`HG_x;%dyJj{^G2ZFjQH=rU@Zs`DYmi*+J1B&<LG5-Q4
zTaKhn<Q#cqBJ^|R@gJa=CpV+_FJG>p)lq?5K|@ucyqmU4i{vXVs4JFJ=y|*^&lOQu
zBG2)LzYoy(pi1SLKSJ-Jd|?X|9?ARjp-?98rVWtCa<rh}{d*!ep#A2j@=jXvK9g6r
zN9A+*dNe@G<-0r-U&zcoD87`--hf#l-=wT=rR-1h^jGp^8ckoz7w{1+_eS=jr~9p3
zpYljm^0xuNtd_+?sCy?b`UWArm)+u^@IltXCkOXY9!fjJpX4XUQ2AL-EC%&O_Na}9
zs*zn@f?BO?s)oM1Vpt7l)+n9mbEEajiAFH7K}qimriWsq+q6-U1E8=;>GcwhZdPhf
zhR7D>+D?dgDoyAB)>cJNOL8wI*9sBGHl-sacfFNmQ84eLlrDqa?aEO~OZh5Me$d#V
zoNoroPw7Q@fSpPOeYxYW_|k4$fHJr%?Cw&EE&^q@BGC@S9wnv+6!t3BO%VM)<sP+f
zpfY$D!1gOmXygb|HoC%mutRA-2aOn_v|9j~P(?*Ei!fyo9nc9^UQ-GoLODiB%LB^3
zkElDSYzTxxr1F81!iSVE-y@hPWdTjX4=WF7Kk$eWNz1sSic2a)qLrjAaP64l+Ziaw
zm3-Q=IHAlO2WMgwM}BK)oK)hv0Q8j7VLC)lD{eyodPeE?9-#5cNZM*iP@b9~lBfjj
z2h3UJ(pPAUb4r&pKub~{P(I|mvY!s&UQpgpvgx9t_`!=yN_RRmd081S3+h*tq@z%{
zs!Z;V;+pcnF$fyhl^&I-yrImX=~c4gH5h)UC?{!EcT<Ta>{MmMVo0Vbo!Y_tEu{}_
z0;emd9zf)_(y=F+`;PK-JBkct@ecTVSNWd0?o1`C2_&<Wq;k~VQ@Ydmm#ri$fV~{$
z<#{@gm8-<yV{9%@S+x{Jp%M`bzl)TATA;32Sr`h92g+mmTC7yr(-CzKl@jXN9xHWk
zfcZqJeG7U|l^(RdC|CCHg!eC$Xa*uLmH3GW^p!Ho9R^=3KjlI4jdGiMfwzjc3$6dE
zls9w&u38zK0~bFi(X<8lQ3?AOFrSoFbY|wWGRp;)z9>N>AyT7^qGP|Sby4Gh?XIi)
z8g*-Qv+3Pls|%$=rt5U=`a*rZ?(tD5Y|us0<iSIiMBUX!oj<-7<u>VB>nQ)WS$DoW
zD!1rP`2*Bb*N{Fr*s6=CgteD$@(}26)AgpKpWZsZa5(Cto7NanY}eILmcdsSH5DQ|
zbf>&f_~|NW#kNzo<|x$tb<HS?9iXc-7sW1JM;D0f*2Sg5!XDi}k0IjNt9wfeuzk8a
zbc{Ao_x^XdxL;R9BTtadgVwFVx;?bi3(;Mm9pX^koRy%$bggL<DqOdDI<O;jKX-+P
z2Xy!8nA|~KP<<4Ux<on(c}O?r6C|T_;*Ve+*16KHIHDWV19e9ox)Zdg6s=py!M77S
ze^)pYqkA?6#Yx>@FBm+f+rguOPwTwMr!%@~B3dtA=c+?nB<OrXfSsr-dJ62bI+ngz
zIHzko1PV#IxQ1w;^SYf;FnB?ir-7l1x*4P4{Uu#JGpNft$FF4Yif(K!!oI3IL=V(8
z-5NTSe_hx8I*J>*W3-i>tn0;rO3?+$0KKUb=|o+s&V|O!G##e4cq?=*Ho;Q5uIvNA
zZtErtgim*LeFi`wL)UWzio3cvd=|}R>cUP!GE4WyL3!|dx_K7?ldYRgZJDR*mIUm4
zUBVq`6zDu?N3Bpdasrq|x^Xx?&lT&Y-$(I4=SrPHsqQ6xw@|KI{1#v@bi?D(PA_#~
z#H`S{(J)r2t5*h;SGr=_B7Lo!Lg!N6=(@W&p#N4kpanFlbS_O1MYXOd9A3QBZTbp|
z?{(i$8s>xUmN%%6y8g7t`lOo{hT^mCCVgx1MOQ-^`Wjt4eMPfcA9@oC?)oR&VQG#2
zG`7&Wwfc)&(ah`gXK659uRn1V%nkaLz9QZ~4}C}pLffeS*cR?@($^`07n}8OuYu{Q
zPoo9cR(&Trqwl4E)f~)i`dM=z;;o-bFT9Vw?hMpz*H2xJn0)npSHqbd`krgyjGw+6
zWgvFyQzk>tU%%o{*bUHY=+xCNeV+?7{_WPMeS*dweQ6KC?A1S^mffeHMU($PeN#O^
z_v^KEYAZ<p{4km;Sl@__n1<+E(3>8rckKv;F#QOc-G%E9kAXsj-iI<Sk^0(nnDdbS
z=i>+>N`JZ*^bYG?8$;xX{?!DiJC5qNQ2!dOpHPV6n7)tm6qA18S%h{%UojkB#ORL?
z19ehwrB792^_y*A#_4lurg};*%>(FZ{RTP?en!8EHn`&TK9oU7(62SaZlZqoVW^+g
zd(oJBPH$`g^GW)>bo}zXL(d;Uc|qTdZskS&ySJ#kq|d7Yby?r&F?_nB&)Nq4tNQ9!
zki4cJ(i!jHb^Xw9QFlZCJOvRZ>wlREg%tf|dX8`EkNpN_sy>Xi_tNxIATV#~Cyj)o
z>H02q_;g$UJ{gjC^p1N$@H9hzW(>G@_2J>*X6jed5tb}{Uu>Xq_w>`A11(#hO~(*&
z^~bKmi#+}ON}%QI`)-661^U<V&@0sc77xiH{e(qe7VCT3fpTBpp3ab#=-d7XXCCMq
zlD$$r{u~O%5q*Ehd4QJbgPpr2`bonf^F(i742`GyoZhhXOuzOju%GK^QFfwSpH2zP
z7kYLc>R#%{(C5Py`nQxWuGDX(mU*R*9|Y>HzRr3`R_T4H6RFle?1Z{^`W+Ww_q`qo
zQM^?8QXksg|EOOyAAWz*U;PVyf7bU70_YcghdGG8Mt|xAiq(cn8<=YiQ8S>p&Y-0U
z<a$Hh`iO9Y;rU<~^e{B0_iv+NIUPURWN7smdYcUnA27EVK8%Bir$NKQnXLvr?Lm7P
z+KIIO^D(rbMdfw_Ltg;<8u+E~X@?<CM7(~6l7T388lGo@>2K)w4k7`DpS<D4E<?Zr
z6uS*k)Uoa{^sR%sy#_V{)IP(N6c`LN{80n9_Z!a98IB;s*>KnmHf*A{2r(?eOx3}K
z8b;F5w=hE@JuTq|Z8s=J7y?!zv;&6jm!Npi(Ecu%kp_+q*Bvr6p`(ydhN09zhYdA9
zBBmpT#ZMq|)G&e`uV}-=zMzg7;?BbR;|7J6Qzs0ueNh)<2-=NUP8#y4({sccvS=b0
zXGqTidCD-7o{!Up&rf0gjA2VCVB!shf5Wwe|M+yy(38$fB^hekfO+09ofbkD3`TEQ
zx@hP}3&u-^R^x$k+0bJbpsyJA{e^bAY8W>O7OopQ`$F%Ap+ie}k?b%$pw2VJ@KYto
zn})&+D5e_RX_a%!aB?B2bVHY;XoTB_-V>pC$Kcx!Xc>lEln%LTI7|n4?iuE(L1i1#
zr@@OH!=_)s%rz_-4TU^I?}MnzHv|tsa}^ja(P{BQ!&TbAE5hSJQ`}<1@<s6UzTqJ4
zrIi?>%(y`h41RX#mm042g#JTA%3w%7GL*-`nKHxXE2w*HSVB9BPYk#3qwc8z-|69v
zF?^9A^4!pp9-VSS5uNFMVHl2GM((Ad3;l_K3d3)`p-^eK<@f@psto6QLb2K~h>~aT
z3>ELdd~c{~0htd5x2|ZQkB0mRxc14=<_1FhY-qR>bzclAwEI$H$RUN*#>p38*WEan
zHaylCi$0)kt#JfB$LoykpMdFM932RejYi#dC~PwRu!s)XZ#D+ftaOX<Tx)1}8r#2v
zGh2<N9dPfxjDz=}Zkw^32IK9<w=?04uW<l<T)D$&qtm5+Mt@f@cN+6$VEY?av<GH@
z@ht6=?lN|W26MOZgC5i#V=39)YwSqpv-TM`exTEBLB?#_w+=Qor89aV#zAS&2sI9(
zo;b|7F9}7sand9>6JhKY2@ek#izuIQ(75F+>_!?-ehV)S8HX#NqKv<_fXGo}S0jRm
zHYT#5jv0OT!oqRm-;``SVSL^V>M_PM&GC^Xchb20Ia)T>*k(Iij5FHaLiChzNq@+k
zHY%?GbH;d-&YH#>?+-(fVEm;Hn2E;UcEG13qZjStoi}D&LIYngriZ}$i$?zipe`A&
zwnyV%Hon{fyH|`2w*mU9G3hw!t{MNOIie%k_^=bqrx@eu1nN!WY<ksFji(GyOf$Mx
zfO*R}_Zl?Pjdg!OTiiCT+6B9Jj5ldTo?+}z4fVUm4+DXnX-s&BBHMUuDim^zlhgpq
zHQK*IEP2NAPEgM`Du=)<Fox3RT%p65?wnT{kJFd=#l}!t+TJ&|q8+6Y<FE7y-veV%
zAS^vHCQJmg%((Ou6dxN`Frc0oJx8GKsnHk@y=TVxwGrrZBOeKa<;G^0LA@}p{uY70
zG#;We(-lVMM_^VOf9ngBS4PLRws82hG5iqF-WY$T=~cDyCVlDo&KOPWxcA0gbb#lB
z@j)8&KN=f+2j(YZcLM!voJfQD7h~wpplXaWPJ&uv>PpY*T2m)F9<a`I{u|V-H-*s%
zy}{&4t9%dBR9XXUG_7*z(0ZFp@uMKK+4QypDz}&hQR39o#JmM_tLc1yP~N7c!vN}I
zdP!f+Z8vSDiI}fxC7n6gVR}ZVrTt8Y{)EC#)5FnV`kU%f@;JbBfj*(zWhy@i^Se!L
zXePABH0upS0!^l#4q)#$HLM3Of=ro|e+f3dq5aMf(*r$PHq`WnR%KzPb|X=Qo6gdF
zEW$L64ksKiWzkN>L6heoya17=OiFVfHl2A3<`GkuufaTOilo6M+SG-5tz)LeG+-V#
zU8ODd6Q*6W==?>D$;%r~oizE-;mcDdAp(`BP1TgtIb%u=heo_<CI^@VQw{xDi9}Q3
zd!U^)wWOV>bEX9}<4iJz&^ey-re)Fa;(}>gV~AWdxj9$eCXZdHyJ|X5n@-nE%V|+}
z-NdzJ@c!K}h5ZY=$)<BI&`2@qCZf1$n%xwErkWm4hQTz`mPv@|mT5pAFw;#w)L&$n
z4$x=xcTGb}(XyGQ+wEaD%XEA!sCy<CoSfsbO+zW4o?{yA4}-a;nfm~iXX;0%9`jAp
zz0vlL0@EWuz!aLgkA{i+rYr-TDKYJ#J-!E~6SNL1HJuHE;zQHW5)_Y2|JH&+nW+PH
z{f|xdbHILL$`nxd+!VSD?Nn~cp;grj(_osUy)+e!gGhyG%{fq&rd<;u`O4(g1g-Yk
zVd76g<Bchy08YI%#WhD|m8qPL>Q$TGP=p^$|4=6Vqv@UpTIQ4K$bKk(HbuLm?u%*T
zpTMp$F|85IYI75sL%5r_QpR(Q`B%EHYt8$|BBXWZTD`$sZ!X#fFE*Ji)1kiE?081`
zj4kHcv_SVXr_wIjR`a~Q0QE9Ar$Bwo)&IiocJo^LR^Qh=cmX7Ln7`74>1RGqJ=;#R
zdpVf?X7_0T3osv}KP$1z{I(<1cbmIyhTT2pbG{JSYhFk%&OUP>ZG;7yw>qdd*l(V3
z9b}N%_zE(?=Jd}14KXjLiEF6YF&-LW=EV$P!p*yBJc%%`q7~2qvsMFt51L)*2t}m1
z?IY+NG8f!NU6i?iwjmCi_t0j@5%W>nC^>2#bRQO?&9jz+I%Yn;+yT(z=1fYqpD-V#
z5i`c@@e}k<npe@3G1mNbQ|QN;FHeWYDRXCh!pEI9_n<7n8S|Mta68_N^YnN*%yWHF
zB%1x``?<5`3AENaXBJukEXkZqM-tDQQz<8V!Q9RhhAx_u-D&-I$y|@N+%B6{ClJLI
zv+GDGUNv|11okzvW*MmK=F$LQ-!SuT&`&mR-UWpebEyI^Zkn4@XOe18t42GenT=C`
za?2bP3lr()dbEjh+srx>RAwD5k}}MFHlXgV`8n1A_{i6s;|dd5X44TU-ZQTrg34_3
z>>w!Sn8WDLS>&33&Bd+AGoM)myZPp0?;%-W*3l_~LUSyg94|7jdIhT3+~^*_?wd0v
zK%~U{l>+q#<_9ZLl$w3s0`sAH0}a2A%tJ}RQD$yVCr_T5E7roqGjluoHs!h5tqEYt
z&AlUl{lY9!hw;*!OGlY2%qPE~uF@PqNvK!mJeq30Ht(AWv^VDZ!7%aGJpK&~R+;P9
zfT}hd=?wBavpXG_eQ$2L5PBcXg-HPW=rGrzQT&tnOcG>1n>Wx_!xwYw?yy^9zUBNP
z(qgva=DAz0Qj&j-rHsC0SZf*60&TI*60rw*>n(9K9o%4f(HeCgmgCM`uw__XfNipD
zqMm89rG6WzZ?XK;A6|G`o{xp(R*U1tXpml(KswH{%`(0RM7=F%snvZf%Lc*I?Uu5Q
zD10p=W`McF@&ip%{49Mcpuf}dsWm|TEgPwO53qc^0_HADX%ZB6TN=|*^F5Y+Zt!rg
zWfyfY`z&J)LL|`g@)w}&w{&!T1A{@9v((W9Th`K9q7X~PZcw3?<rHt2<u=W-!Yze6
z(asT;@rj@gSo{}*I%ru-`PxX!@BgAWWC^N|H!jLzr#JPmWrYsZ5zAOQfpyd}D;<WS
zE!uXdJ7%fFf_dDseirRRoUnXNo3AmJ;@{C0CoO~P!Npk1uft#>&a&+_L{C{p7Qw`6
z%V<hcoUv5q;Qqv0G-^1LVA)4!J`*jUDW!GR@|w=Zp0oJTx0*>7JDtowZz;1u{gS02
zJ-L@H?)RZ^#Zqes{xTGI)v}nDiq|YZE`-K)iw_OvH!Qp9<Vvz-;TY(rSRU?$-J2GV
zohVW*Gs9pa&2nWjytrlARt_rN;wB=r+m<KvLBkzODlMfmECVUsb=TrgPgkbJLh1Z0
zi=#WJdlt8K^mSpjCG~H}<X9%s3?bJtWE6bMvqU|F7x@;K-Jl9Ady3$9p=J1MG*FS{
z_Eb>CmKh=N_rB$a>7Yt1|Mmj*155T#04ueaDM#|qQfnD3J+k~uU2vJDS!-ZEwrrq1
z@+X!8I?3#KYFWPyiq9;s><I0-rOQ$%mRpv@Lh*&gn--%lEhDvvslw85C8$bE*Y=Qn
zWobPQVZXNAO9jju%Nq~Wy|tXC)7e#)5piHvTY`r}@}1?Uekk5sj?q&5gXP*{h<vns
zn26$&!*cEn-2ZHOM;jMkEN|%Xs<E`Cr1@&=<BurZt?mQi@EYq=5pA*7`i{<lt+RGb
zf!=zn><5tz*1~j%cvu(F!fm6~d;;b-S<ikC%+1zTKS5-Rb)X(`dRkK``L)$LpEBrP
zR>w^0bhlaeO+w*q-AVI6AM4srK-+E|;SU*KYv$iT+hLVyyT{KuW(!1iT9>XyJNa8@
z(tJC>niB`fT~@y<FtOLV>?J(hXC1f%b%EA0dV=;_x6{eVAgfmk+=F22<|;5ltS*js
zzz(%u2nBYS_213#BHZfpHLxSBbGE^Y1J?7jj67%^)(dtct*0(P@sPDAO%S52^S43o
zu+@D4M2=XyQ=;jpwTkx9qOAwMLUGL6mX63Ax5iM|C#)M+!a|Jo3nh3@S~Y<*|BSWf
z)1FtHbqh7yDXXRiqNlApvQV6{`V53<yfv2g2okInA`}v>Uf&|nv(~+XP@J>wr~_t_
z^<p|C&s*auLwmv6+KS?$Rho>tOV%=a{V!W<eGTf0brp3`SFQe&@kd6uYu5YiA$r|<
ziw@J>u=-F6J=waC@)0RkF&r`7v|jH4^QqRhnUGAgP78$HTh^n00Vds=OQ*_iTRR?r
z-W}^tv=NqJZ9r$H?pk}$@+8yhXn^M;%j#x?7x%0i=)2f#>u9WQ99)jIIjviBttZ!`
zq4KPIKf+SJwIMBb3atC-DJ!&Yx(nBetjhNQEw<W+!~A_~0_}&DSP%RT$p_Y2$KYtG
zRW}4C9$I(PZqXyF2OVQ6vlf@a!eeW0Ez~`+=Fr~yQ|l#~pE#ab-_oZs&#mj4z|(T8
z{U>O=u=;m`=u7L?csw)})~NTuuC%Ui4ary5f%M2%S!-=ZU9~l65-h#5PJ06Cz4f05
zsQX}DOIw5=t=bfTeX`D`6MdhprYWGlSpDcEca61(2HMpQ+bKKTcekaS2D!#|uK+M>
zZFdSlt+RFB51-cCYEy1zgKffj=zG|Ve}dX*`!o&FZ?c_kjAFCxy$%XnY_o2|QBT|7
zKf%$hwomjYhrDbhY82aSG1RSl+j53L#K)FPyEfZxjv^YCd~G8rmA1p?zX#ZUwoKY8
z+-b|Bm&D&TzXnu*t?pb{+GP`bAi3MNISAAqTL8^C_u2*y0@^;C7v&rRZ8J|I!u__X
z?@$EUT<C9+1l#&i4-sNJMDIwbZ8N3Z!)y&5)OUy5{-!fB5jOA75ItbiP!j5(?MFIQ
z7HPZI5|$3x{>p{jC|gxFL=M};9|3d3)|%FxM{PeUP>8m*uz)&dn@W3%$8C3#p?<<v
zn~qGz*!s)^^Q5iB4I;5NZ%Wa`*@n!g^Jk}QU($ef+V+LEZO+)XErw#e?YC(7lwb?O
zp90_#ZD+ef<E*XH6Z+?D42dM!I^{y)yiGL=u3fNM{7`q%*1iA=mux>D2X)yd%>~L8
zTRvsiui7H$Q1&%j%{qu&w;7Mn_;<s0ED!e}*;a56UZmKvY4`J{t-J&pskWVSft_Z1
zNXx2Qwp|NhFx}RZrkb~Hz5W36j_p!4L^5m+`i9}I?b$uFMW*d^XVhiec3ps_9NS4s
zMd#X*8$mtK_JMLU`L^?$>HRCPr7Q=x(Dr^l3>MkUKf=XgTSr>5-M1yvF}4!h&^_?!
zfo&h<gi39_=AkVf+J;PprAM|WtD#qB3r<JfW7`E2u%Fm!%|P8#TXYLRKeHKcLFBn@
z{b}fx+xV3LdtqBji&4i*Tkkw*RM@oi#|kTLJT<~A+i6-^zqa-4geczFZqS*nw>Bf4
z38=DFXG6c*b~_y&zO!wieSr72nn*<W!DgYS?4xZIC1XF?s(irwY%8Lt`it$<Zs^t6
z3SYp&YJ2}~pxhny!qJF#jeX5=7+h<AJqQNZ*?*=?z<T@L0@&SPAJ_?&JnRS4fW6T^
zt2;n9*|Uv+*=(;v`#f9hlj#E#PkUQBqq)@{9|uV<yN<Gw+wAT!5b?IR=mZNs_Sdfg
zw%xv%#t~n;BXb30cG%zdfQFxaMk%;E?YGN;?Qb8L4f6r^!_>3wvcIQ4=(5}H*%8Ga
z`=wY|+H3cq&TpUn!gl}-v>!YROZ)9ga}+^#6aFd#7i_PfWkQI(iVg#W+9SHai!l34
zI)Wc=f8h`z6Jej)1tt#I*=C61pnVx_^G4byQI~Yc{(TFGM%hJgP>1b*(4V_HVh^R=
zv7`28Ujr@LK6xe-j@ft8`u?~*xeOvF?DM7qGsb@7ESM+l!^gm<So@j;D8$(>Hh{mU
z?5BKb{TFY)?~NkC{w*CHNwoi}L2=f8n!2QO_M3xIB-zi?T{~~@OB3`9_J$&gi}sGR
z33|!iHxR{Tdove!am8MD3d~=%=TM^Pn!Q&E^sd`qQV#isJ+T?6WP3OK<t{G8UUv|E
zU3k;(vjk+S{YN@emuBxFptxn9OPT+4I~xMmZre|$fO*GWOc|F9`}H5t>UZrcqEMHK
zKNXB3%bw8)BKPbM)X>YeH(w67bL{3za3<G2fYxDo_6G-GDBu42JX|ZV|ALP(99*G&
z#C!x(WDlaR--_+ti_u>9?e3mXEV2I)3(yDl+7dKM?a}`qN7o(KW%d0_b7Vtp@Y#Fs
zr43V4)6B{&&9ZEmm8F&q>zkVS5tJ<(WFv|S0?JT8l&PYC$VQfcf`IJ3*YACPf1TI8
z=bZOB_wsq}bMHClK172w+pKnnNQ=#Pbm(ujk<)4NiA~`#D74vZ3`eWoCOQ@(9X33w
zob0qoeFvn=X8te~x@|(~LV1tP9xB$b_S)QIL$S|h(G)cLZ9WxZh6Zd*bT}Ne**6W|
zkj-9NK89`9ZN}(FY>v~5WYp%!5;!wv^UEw?kK6oCH%ljM7Q)jxlQ!RIfjwn2MKQ2x
zo3sM>G-FfW3z4IYyHpTm%Q*QvpzW-T@mE2QF&@)BrQ-}IIhghgTiReaF!}?a;mF9K
z0u(0(e=cC08EHGva$)4=z+YE}!3=VO5q1E2ZVZJph&$s1orgRaYo39EC*$XN@Yjp+
z8ykNZZ$|$-c<96Ey$VTRhBcnv)P9Ua6?#uHHZ#!jXB2B-B7m`%>OTV+PYPfngz-LI
z`v_&!3(*Q=_)r<zDTb2{B%HCIp48I}PYNWQVJN7~B7*TV6;+>Qyhqv3a|{+?o@X@F
z040*~(%Tqd6r;dOmsc+^-lQWzG^3Kr=VBP&biza|!;kVj7a41Bfm~vY(a9^0VWdx}
z#xs)F0VaX5pYER}GU{oWz07dF0e`PBRwsibF&rDAkj#iT;BSz^@P8hLt}<Ha%#zCB
zQ`G7jW9zSU{=3fjkCHfPjPgLpq%*cr+9rcBbq}pf2Al3=Wig(oYVK^tcYDyf!BE7(
zi<^waS<t)1h@~YhhcQBN@!O2d?XY`?acTs-T!zmTwDK6G2LP7OIC~R%cNu?By-fk5
zzLM&%?=g;0$iI-`e;U|DjQ4jyw3u;Y54<R0JV)QyC}qr}yk!|<{vMbpXZ%MA!wQC|
z3kvrcI$FFc8A=KURWULi!C*C`RSZ(YP|^XamXVVP3lA9IwL+ne(bEd`dd74a<^LKO
z%)ilm$gt;P6pt8jlpASe_&*1YCdNgouXxPZM9Wq)<JW5NS{P?{gS0aEPr!S^D0as{
z+ZZ+9K%t#svl^s>(MLhiPDbj};B_&SR4v%es2hYcJ&XzpXY?`(>C%a{k1<0JP(Q=;
z1son=#M91xkg@0`U=J~-7Gu_j8P00}Gr~~r#k7qw68`{ij1jyO3ge9T_CaBSQB293
zX~x|Uv}PDnw2~fWHt}G>mZ=(px*ap<BwRbj%zFbO$C(|o!LzqAf2MGm1Cz@Es3UXt
zKJ+><b1BW_%#5Z=L>K0g`w($uzQlt06U;+&t<H^UHbBIkxq>279?Y$WVZxJXqQXxv
zCY!1)yqTj87_Sd=ITg11GS9c7<;P^u0rw=c>rJ5eGp!#`rX+wlk2bD>%x7sc9K@{A
zVc5aUXj*1Nm_Mrl8p?c^USMHNI}_}lV!q4=FPvHPA@oi&rE~~B!<=UW><H%BW>`AQ
zym1ZW9P^<LBIlXw??OG2dHExdDCS(MG`qn3)A|;Ci)QW%g<=d-O3PL(Go2pJi%eTO
zYh7aQJOr3H=4uvvif78Hz&3&TdI<CqnIbAwz0CZ*8uN68`I!k`Br$at!AoX7ON&qn
zvyh_QSDEXQfSJmyHllTn`3}{6UT4Nu5=~>?ByZB0URqenVE#)-iA?5S6f?|X{<RY%
zn|UPzmToYg>V}6mnIZ}X-C`EewmXLz?28fJX1;M5=I=0H{s4A!nZ8GWlE>V>5YYL|
zs8V#^Wfq7)3Ygzr0oXm}3GHkH9z5n#C4ebnwoids%uJ+!dI|Gg9xRnI*GXWhj2V6%
zymDrt&({Z3*15MJQOo?0u3J4|+GRtqj=3Nb_8u}%w4w76^WH~LYh-Q=0I!LeOi`}K
z%*~52_-1A(1>#zmL9{TnGHVK;@PzpSy&>C}_eA*fv@<_lgjNUh(th~a$<)MvbTQdf
z*VoN_#d;KIJ<O45VD~a3cZ1o-jA%e-KeIgr*aOU`DSk1?OwPl^3^D5{7&FZ5szB!m
z^XV-Z$|&<N<%-9c^=y!F<~#~oO)%HeX?c=aMnTjm=7bvzPBUkh!kHQ7GI|FeWz9Z7
zIa^znY#es&Skp93$5<gh!R~QZ)LM99&sxogK?hdsbAWMVeMR3+c49@vqUFr`IvqS0
z*4%0sbY-nR2+$L(N;=25v0T1_C3jZ1Conx&SJ|-O$=c%x;>G&b4|?9L;8Cg>^kMz?
zF3@~gDS5#5V-1F&b&|!SAiF=SvJ;>ItlW=)7RbuUg=;~q!%u@3%!)VwyCJN<=pI`r
zi$l{L#?mwa`xNUcCHTWxZ)-tLvmSeacZTI_3-b}ID*7bkSyt9My0dbQRXYgK^Q>Mc
z%ta(?1x5U$SjT8Zy1=^U0}{<TP1Slatmzw&jAgY`x%fqvh9c3ISU=RmU>r++2B7h*
zaw@b=VCA@>Gm&**E?SpaepXDv6;?(*{ys@8muKL1GOLijWMWNWZ65;jDl2*(nyIYO
zxnN#nsi+3;IxAm^&NSAqbOSV<^>!OTGgy~apq0t0r^19AtT;2&Z?Ya1!tGnE!b1?r
zVO`}y<TlH28s_h?9Df1HWi6&hI*+yWM_}f&&W%Cxu9fx36T>cG{j&(od#pd`cU8!;
z3_zoZ^%<qCidhD_K~}<wrsQWS%j0DXw2a075a!ESyD5NB!J4Rn!TYR~Scp`zzU>28
z6-!I?Th*+hUf8W+eXN9DE$cuO{C&WBjh2EsmNkSnEA=cdI)62=_M}1dA*&kyhzMWl
zS>lEXZe&?0=hVbvsnL4O3ZT7vGmAr~sTP(!rSw}_n?DD6!dgdp**4aE`a)GZ%Q6UO
zI#^-P0lJeVS&CK{t6~fy-K<+-FyF&EZ(RVtds%1b0zn_^#uu>E&ytA29AIf{06NG@
zTn&RmESqI$4YN+|0NMy^@gzh>S?;7h#>%8A9cM8qu`<C*c?%<)Wc_LdZ;JIag~z5@
zI}9*C!@5t~`=jikc(iQU{^3+JXvhBRZ%p?wwwO-T$JqwjliIW2`UN}(_F?)Msv~>u
z5}0>lcZy)inf>oQz__r#a!1RRtym0^6YP^GF*G;!YKjlLvyU|c%!9p|UJ9P<g~u@n
zFSg+aw7l6lhalp^-gS;*X1;6*l^OZ5YivMHvY%vP68zcu6zB<HuQ>}(1KFMQ8VO==
z_!Nr4?6xShLfG#+frPTfbmk6Yf4l{5pJFqwp%u=apx3}@_H2stoMnei<1ccK-AfAR
z*-0&EMY6@6R5KXGK0;ae3+(7M@GY9Xjkf7A?CzH_rdak5V)%5C{W9fQF0o(pM=Oq<
zmkOA8_IronS^|5r5e5_4Ddgy7b}FS=uCRZkmr4>_M0fR**&n%pm%=_qL946me{G<i
z$_}SAi}f1Yp8;>Kv#(OMUmAM}<yq3%`9ETUGuT}eGS6f$qA+t7+p!K)lFc6I#6WMb
zn`shnvQJPJ;uc##2kIR52bGY#&8{qg`8(`y?7+)qzt@dc9{b}e*v)6RD$%;j{)$$u
z0xLV-2zrn0NZIg0HoE~DMeNSCz%FLL{SSC0?0a+3DrMhV54&aT+;3o_oE=7?;0ksR
zy&><j|9uYFmFz3@POM`0ghQ{Iy^5l}HS9Y-g4D9J>6Gw*?JxpT$9{1y4Arx(ag@4h
zV5f&-W*@RIQWoM7`>hA)Y-GPc2kIs^mkQk;vs)ejyP0hWh20i*>uZ>qR<;}E1fQ^H
z+|k*_4*3;BYiEa2v2F)@e+f)<vawd<!DH{GLvuI#c{)({uzjf5sF$5;{RE1A?0fz&
z(a#R0!{7kBf(K^?+3r+hGQ|Fga+t&HPMk33jIc{7=R3*{`yH(@_7=JfKhCzxgWD5q
z7G=>V*&QXooMO*9fI&>NYwciuhCRC<okuy|G{3f-ng_6F$N4Oi-han9Id*W$fwR0G
zGLD=k7O<T-E?!V{=HxBKPsoL{<t)%#IX_Tn<pjrmE%e+tiw0oOonxSMhX-fXE{J$?
z254dQ;_Sx1*_-3dF+KyH4`(Yq_r9FcG_?FU&RbybBxk=5)eQP`?C3Wez==$Pejulx
z9^4>~{r})hFvrma217Wb6toKESSWWB#(AD<Nl$Uy9zh|Tvt=VXPjhyC2oq;Gt|y@o
z!5Mo4t+Sl3smSRZr<c~S^PB=&Jt8^9B~XasIAWV^opXUxUj*~foCZ3##c<w;0g2^Q
z9m5P=<eZ{ezr^XG0-rd}DXNf(=lo8exJlrwzYfquPWP*@beU5f4QH-!UK7GZ5@*R>
zpd@oLDHxf;+3yRKtDNQELnM`hf8&N%9LJdtN$Yh^G(|eoIKM1GZ#rj}1!x(Z1+=bb
zaz3DpN*2dq9!NIFHUhjGoQ1U9-Q>Kg1llc57#*l{ICISK@HQusHcNLnl?iYym-9O9
znesSys6Z~CGnWdc?{c{Ggcooka{zYF%6ZKPFohgDN{JM4J_v!OVvg)Bv`RP&sMM>J
zljaN1GR|cx`!46W(zi1zI1BuNcAv9_B3YH3x7L7H#aTw#fND<ApD<Cw;e|q^mQ(Q)
zS`Rqi%i&=iNBj;Zww`m1?!-25tfK|6^pLY_93~!dMhUx-<4INWO`J}DU_a*MSfJm`
z`Ta2zpK!jS;9wg^UJ269NmvN=4$gAgHFR<~bb{#OIM6-PZcZY_#d<h8F7$div5qj`
z$MHFWRzD}I9C`yBJL?n3407ZYoEYNlpjwY%j@K;ck8qqCAT!F5RA3Zi91r^H#yID5
ziqK4O+D~GFCpl-Zg_<+PX}=GVY0ef3TFr3Ea{+dg`<VeEw%ig5TG?@1=pb>7+wKeK
z<J|8RfVSuI=g{-#z;*l_y^dTqJ%&zP*FF$u?(6$u(1q(tpEGpjj)cSS6I|i@P;le2
z=*EsaH-x^_=E41&RxM9%1?5n@xR*@;^X7g`m4`mu+)04>a&OYbC_nBCw0%9v6@3q$
zKey{S`o}B*+#hJ!3gkXb3BMq2!d3Vd%*}AZU_!Vr?StJ=ZYtGuhH=>)82u@(?eB0c
zoc>n~9z5=OiYlDpenMZ`iQs-gx!$wfg16Cmj{DO|w9a!wzJ^bc+`nmoiQ?u`QOE^u
zFRI?GbE3Hwqc9)C{h3~)vE1DWz`n@sr8Dp)ZU@yI#&PYp!KZj`1!d|IxKGoXlE~da
z2kOh*Z(e}j74Fv*OiAKqb-_|Hch;AXOyT}RUjVtvz2F5eQn@9=(7VR{guY60oxAj1
zKwHzej~7ERo!fr^8X4U0X}p=-E&IXD;__&n%jRCEx|JK;vhOf$H@VjD(Rqu@d>@YH
zaM#WU?>6@sZ58iugBL<CpIgue6L+~svw&H^-I)c+d)ys#ji-?7>jL#6Zf!4G#a6D7
zDqTvrf71q~l)F3<ie=mzbXBgL`<Vcs72IKZe(!T9i_og%F3*L26*o-|g=+3D+EvzY
z9VWo5<sPhr`3GD%onh;^FVIs_&%ORHNCWr95THEdme4Nv5qHiKxZTLLmOKlCO<XIL
zrak7mmVnvJefTw)E!-uC!E5DSreQzfW>N7#8`r)Z=G(bl6R_05jeijeom|UW_}j%@
zQ~;E2Zv1cH^>7>M%-+lWvjQl6T)%}N{oLUkpbT(7qdnpv*WJnl+7S24XqXu0a<@Wb
zgj;$LGNW9^S3n!%)>4_!IJc2@*c05)MNpjNHqwu6it9mT2GiWz6dau4zWNV3kMexo
zp<v6qJO%|jUJ=!;9OEsa2=sB@=@_Wn^Gb^#;=l{9rkt%K?*k`@I`Il9zU9nw*$?8v
z!=*Poc)W8Km^i^xRY1gzH=ADV?mR3wc<^}d(x1tb_Y0*&ym;@s0@Ryl?+D_<3!yl=
zFE4!~Cf|?eKo`1B@|v5V?$0~MhC%>u;~aYb1@dg9U<UE-(XJ(!mr{jE2;n8q0!%1R
z`5QFCcw$-;PVv?q0tx4t%}_YayEGpnXL#3pfEK~~lK!dJS>9>}=J_0N;YIMy^WLSy
zWF+soogh)XYZMl{!26jljl}Y{WzauHy2#s0si#Z4Knl&o@$g?K@u=|*F)>jIyo^eS
zCi1rJf#PMJCkx~X&wdshP2zEGKrfjm69YSi$2$n#Ro=6dzfR>@=>O|n<BbMD<T`KW
z7Yr$l_X>R*C7l<y0v0lOS+rZRX7aK<p_s+Xr#(zIZ+$bcZ}9e0WzJ3BN1kZi;tev<
z%Hh5KHCnfM)0BR{!~0GHe{*@=lK{=*rHi4S&uf!G@-FZBP?#v-xg<g19`E3*aHf#A
zXfgDPcu7?HSIo<!s9cGa*GD<BQr^e}ddqmtOW{m8uWJQJ1&_;y;(cD;2bhFP-cS<s
zt9TuBfUD-E(~G`_mq%4FwY<8080Z7uuOEU}$NSC)lJ&fdWf)-tul5vL4|%6PL+cUm
z6^cMN@(L{Qu!(2=+6NksdA+VM*vxC&2!~sEFSh`@l@~(?gD1Qc+Jm(5E>dK*op+u-
zG}poVw-J(^yz28%@8Sub186sIg0iJOy!|ghy_dJ;1GM^hUUWgDpEtb$3In_!C^j?5
zTkiof#GAIR1oklRP0CS^@J`SgI?DUx67<J-U(iLgaoz&Tj7;!aD8xC*V^MwV6z@&C
z`!&rwTMzXa-rJPDILaU61I3nar46ec-=FUAALA!nhsbgMYjn)E=kHjHVLR~CXvufv
zfBZL{|D5>Fv|Kv#|DnjA3;(}%=)3aQ(~H2JA36*A9{lzx@I3i1Qh})#KX^0ry!rpq
z*2#x|g~DULe3vUw@Z%d9@b@HN83h!7el;Dr0{G>07e0`m{Uvxo{PAY+g87B}sAe~W
z?@CGaP=5aVfC=L_9RuhoKI<xc3g;i7nC5BzF*=H$;Y&Y8D}q0o4KL2}^<Dry$A6FF
z(&za>w9km-$M%C4#b5XY3K#gXzXB|pUqVOm7=93i_+$Aq?m)T7mul(#cZt7e75t9l
zH&CHkJpWxPB}(9bG7F%Id>K84m-)W=(7(dB4FGl$-?19*C-XA`Ad<rWb{jyi@*|%H
zN#(yz#W&aZ>*zVS&VP?O)A;#R%a+d1qwGZnpL+y`GWq9MVz|~Uz7PH8viS>nP`tr^
zl`ewb<bV1eI&blvY3r85ciIV!+x+Q;_}ky%hf~!~F5jOP<UIZ)<=^u8U5-$=%kOnZ
ztAPKO9**AQziWfeLjJ>lpkBm(@hLb{%s)sewi5pLxQITd)XE>q#viDR|0o=G%lQ{n
zz^>q*NrTLNzVCN1U&%j9WeQdNGnDVI=5t=cU~2gL*8#hhUz7;R2mBjUgHXp`dkZ4<
zd?Tg%8~BcYLGmGg&+9;W#AmL7YmNNx=?vY(Z*GG6W4`r|V_-J(w{^fo3%`i+jjj9_
z%Q3T0__HXY*2Z790V3`E&%T972mh`A(Amj<ir(T~d>^`--pjv4$)Y~~!2iGF_zpC)
z1N{ARm>=Y4Q2b?xpWOiUVSX?Q)#i-wFHmXOC_ltX5z{gLa5>00|4-W6PVl>YU~rPZ
zQxBOb{wBHrKF!}r1v)eQOdp6G74#ecsI6e&6^z18a3})gm>_>K^o|R%M?vfb1B;;G
zAb3FKI*x)LqhZ%caEsC`&Vnt2;JFC6o9Ov-71U6W<b>b>rE=T^G4mkfE-0fQyN6(y
z=F3yyMj<#a!F#mv^cEyjfwzxfgubWcE0{&K(SCwxT4+uRvR(ksU(oOfdI5sXE5QpC
z?0$l=1PQXt5D6CCjK|D`2v+?|cUD3Lof^o52^P?*c}n0(OK`ZLKn;VZ1;1|v?~K5X
z#uOn)q<zL&!E&mEI4Ag%Ui9Y$3|h4!1&1k@A0-&4X!QlbHmXR77SvMFUX0)ly_I4G
z&+9=h3fd_&dr45Xn%;kLf-*`Y#0$#Hp`ReI{tGV>1>I7#E(^S!pnpa11{Yo=2^?3#
zZnD6!4EiYoA;k)>3dTQ$7pa0WJ-oOkSWan&>w*o5n1nRJHxfXn3kIbS$q;x`^e9s>
zLr2;y!O#$R)@;G5Xc)X9VCO;qreNkgT)ZXdrW%AC!FL&uxh+`n4tRG2>plm`6+|3B
zXP!XD0Ld4Wegy2h0=Ihb3Iv)YwC)LPF2Y2iK>ry~iUiC40x1<Ny9l?-1Z^L|Ub*1f
zDGaH?D%cYV#ruMH=uBHF;9mx_O7Mij&DDZ~8$oIWpVL{bR*-NFQ}RIYT?<B0Cpb6^
zOZ9>m=xc}#f=>fr;-O%|7T!M+G%N#lqaglks5c3wsea_KU@PT{n*|3>L!?D;JQaGa
z0;>n5(Vqx@qnLY};62(VwF~U;z+i`<D+s(!K^X0Hy98U9;B^bqE&;no@NpRwdIc-@
z!izq^B1#1J3j+6mHz0VE?$iznF4ON~NT4R~hXo)03a}A@oOT<df;ZC98WX%_&4J>$
z;NT&6Iw7$A9B7k*_dkZiQ-WeD(VP~%OL2u6f$UeH9Tkcwh-E7j^nln2tEkZWm~dMo
z{uIZBnsBu2g>8Sp3kTukA}BZt=e-A>lW;*QhV3leJ_bw|;U83l<|@4K&<f@W;q5zU
zx(UB?0@Gc1gsOf#gcEe!_7tA;0PzxfQIWp4(4`X!KEj||X!#0-`Eboo==ukoIVt><
z2NV9n)AVcy2v4|y7br~jhI){2oHk3r!nmE_g$RG6?@fdXlVd3U876$`5=2i4z3IFh
zF5G}`AIv!|G<E~@j4+i#(GkKNGYp;;9_xk3IiWq>Fgh>1NjvjM;gb?{MhW-OQ*}W&
zL0_MU7J3(A5HZ43y6X}vG<XB-qOg@7*h|9cy_lysAs-=d>zsID6V*H=2scqq|B6uB
z2mK^r0@aNr3%AdKXo_$?Ex}iXtNp=C6~4R`FxQ0pC<J$1m|Fo}nsDY2NV?F;ggML*
zriO!;DXgpnW|lA@77E$IaSHI>5XMk$?WS-855#&)7)~L893hixQ*H~-(Mj`;kSl}v
zT;cpBXypn2c@>KJLOV*W+!g*qr<?*|!gFxup0I`DAcaDkShR|S4cpNw7N*hhvqZRx
zj;5tTFRDN)6H2HEyIeS=07`{W{07Y5w+hGTCtoR?IswrtVbF_!sTMAwmt&1EnPM}w
z!aMXhJrEwI&j;2CKcUTZy>Ph$#@is=k^#_%!nqW{cqBX?1AiNZtEhIiNoaW=V2_1*
z%8oS)RTQIa5pJP#XRGi^2%w(`t#d7~+a~-<4ViXfOa=zpA+(`0Pp5D*ojbdPOOJrp
zEmXV(6FtHs^fdMg6X{9s6P{cPNBf0G0zd|Y6%>OW6mC>PZ%A0Z3?jqA=Vsv-G$Oo`
z14E<2LoI+F6COVaGA>ND-UXcy4){WGQg~n`%ufkFrQq4L(69mHoe}muht^S1{z-t^
zihiSiR%<6ZN1O0tqCxr=@^MkuC-BK$bc8OhI*698#;_el?R5XmNwkX2JkFw%D<R?{
zx*LV*auu!o7<wl}_+}0ax{2oR0Ghi<;ssF;(G*n%c#1Y=LB>m@rlYC1Xal`leMGE(
z;L}NwJPV!vq7GVn14P>|qBBr*m<ba>q96DG3l@cxKs`icqP=OT$n+)bhKW>C4C0i?
zOdG&((QkZ;znm6rUj?)?BF7=1MTlxE(K;)Np`-XY(UpxrJ1^>?y<VhfEd}kOM1H4%
zeL=L5E@(uH_Hr=L7*U5kypI*7{sm_)iquqfb4jG9lF&F&4Q;F9Ma8sXO%U1A+L<Ww
zX`(xumqjnp-JmO?zcyinNun$E08JKc`4<`~qLFTNUKM>y-?2{>ePaRkHPP66(7!I)
zVFGrV$eqHG>7oWoXk~~@)R`%&NrYaOsG|>H*`i-3KyHW%c7b<Ow3$kNZ;2#}fN9MU
znO?-y+!jq8#6a(eDyZfuSM>2sSjrQfrSMO_Xzm60eOJ^)p|Aqc9ja5kCptk(f1#+6
zK7v>z3ONK5#iAa{iIj*|{0YfY(J`u2DHC~}fWPIU&+Fh*h3M&Z;N2I6Q)IZ(D*A_B
z`&A-)+9*_u6uGclBMN>ECTc}rQ^n*1(XVt5yiU|hi(kEHkb;v9qJ!nI^iVY70K1Pw
z<9~rPisY19X%ab7zT~keiXQ)F(XL(SY!R*FfV7I%KZVXGq8?{}wTY}*bO37?Ib_4P
z4v`=2$2vs`|3Rip^lTe=-6AbrD(DfJSr|;O=;9-Y^oblVptE0;>I;|w(SPGGKPbw&
zj<F1h_R&^kR1`}4j4{!+R{=dPI?PAsgeZ6ju1$(|)5m3}M02fIF$>e8XDA;&BdVwc
zIVwIA4)eC+#(L=6iNB{b{4w!yT5XSu<@qpZFV4<|YYyU9UWU4(Sj0ukNxbd<A2o3|
z?OR>Mp_IRK6|eppC?~`z^loz#Z@GtGiMv>K20nR+vnDA1;wk=y2N^FhqZKB+#fPYV
z#7F!aE$F`Dr~iaOKe6X_v`&f**WjVQ_}n-Y0>uB-f)^;>O*?}i@n#B-2a5~;gh+_^
zdn&RB6(2eT5+;7_35Ik^oJ{+KaIxwSxOQ4RF_&rv&xp5b(2Nkf(2wS<czzOE=fo-W
z8He-Y_bGM|Db`S}RFpV`hw)wze?&=~Xz`tK3?@d*pmi!%ENDmPMRC|DOk5H>`@-Ki
z@ow5D#EW00B{V@Cs>eJfihrDeqnE{R;wBdEOpD)Yg~LhW5g{xki%(vHi4<||R_I?9
zze~rlRB<^aOs<LdM}T)-9R45drilZegHP$=yQ?9RA%2z)GMQqP5tElCW(>k$ws_8m
zfW9Gqn>MpI#W&<Yxg~z^1N3sl%cx4odRrVq!LK{w72N>M6|bW+Q=Yhj(mna&c>@5w
zD^^Fq?*j1<ZBy=vr!xRrD3;NmsYu*JiOyni(S4wmh-(r6Rx0*&f?k=pnxe+#;zrtt
zRfyM(LFB$TJrul3vHNYzQ;k)eNU!f&@ihmCJ`j7+vA0g#wHz?@;-$G5Z-dx{?lnIY
zFQLIa61UKG$42olwA?j`wTbZJu~_yw^qR&0(&E=5_NE7~Rs5z1Gx|h4htk<?;*kG=
z*Dk(B$=(ieRRiXtQ*4b|17??a`7UU5i;HOXdc>X~u-hx{kAO^{c!-Kj`o&C&<_w6x
zrZsd>{COI9L*jMsp*1XiQv#6@aRRODqvE(<FkNHf8(V-mF5YVg%n9)*Rh>?Xof=?o
zO1%I7_m<)yE4>b9#BGnDe^hdq0)e)Y&X?h-og_LQXvZWjb$~f8$y5TyUh?T}v>YT}
zFT#YQgg1qjljQeuC^$<_r9#9-;z)reSBWD9Q%^{ipF+z`a+_8ycgZVah<HdW@4%j?
zWa*3*CcGro7NB`ce4oI)k7WNg5MN0f#pC@X|I$D8JSmCz92))-BVDNoknEWSw*w_r
zqYw#_OwiqeV9Bw|XoX1Bn_)0i@;2S?2$MX!5e835HuBIJE_pEzV5cRlchEW`F^*Hs
ze1xRD1fXXnE{|dNoW$o-4CcJ#r-uNIl(<u=Oq8VVD9|oQ(wBo5EorB3pvFk9QPe6{
z@+B?S7bU~puyje{@*`St5)Q@l;w3vvVJSgUV2g1kN`52PE=#_j#8|FK=G#;LFG-T{
z7kZN=PpE!5MY6pXUR;%YydIWPB{yD%XqseOJS?S4E>S!qL-Ofi_>?L6kG@lyC24#J
zyV;Vl2Ou{jd`h+7l&lJYzqcgS^!m(^EN}(bZOM*@aP5vHnf8IXl9>NMta%bKRaxar
zda20duH;K8Kno;w+n{()Qc1y)LP?D)3>HZ)i{NOnWaJ`Dlt@Av;cuzr84>i#B-pCq
zQIl|K&s8DWK=mv4C4bSnS}8f`4ezTYHc`;4mW)znvqsWSdD2>|<mnPHA4q(=08=OV
z<PMnil5eSKuR)So2$_eHR@yl}lI;5b4|+&GIs#{!B=38G_gM0R9;8`vmChF}lC)fS
z(JB$X07sulLTDq^Cb7_})h_8gh|Ug)J`JQ(;&>Mpx+K=dK+Hn7Bp?fRdn8$}!cwnf
zY9AE)B!w?Pv0vhO8Q24oUukI>l=NRiYe*uXSk$m&(L(5rNWP~d*Qn%66L@2iv<qmB
zOFk<GZ$eT}wT6?DS_9mkl6?3)c+-*uijB@l<kmMaUq_{e_u;p#v}7U7+ez__Sv+`B
z{t57oOLNTd&|d0Z4B{Z2S_PjRrO#5(%t`tV)sQ<&nNMKCMcPdjI<8Xo1?ZiSK2LYI
z+@#shg6A&%U_TT*r2i}h@sxJb8t5h6>1u_HxAZgzc73Fh*C6UE-A&t2KdGz`XeXu5
z>tWYlx?&uD2S~S=pcp9iqSY%%s;6C6u+*at3Sm;e380*k4pc!eT$-^1ywg%KokGt@
z#T46&knVa1dS|8F?=ZjTq+wrB{n>eGM*w6ZrKUodh?4&B1(+A4rtA2_MoX8Kp%o)d
z>4u}R(gQqrcu_jL9}1VGibrV0N%y~vKSjK>oX&p<(vr<UNtBu?{&HFRH3cHBNas=Z
zB}uw%1`5g2@wsp`MH*I5&)-$)yRX2vRO$M?AlIa?NPvA^y6Aa`rb#!@fhJu#u>d2?
zkbb=g&SXl1_Q6t?ltH<TY-#W*@NP)I@rT`;(tWcba!dM7DfDur@_LBemKOgD@9#*L
z(Vi<;TK@m>6X{|49b5CIUw(r*xhu`4oLPaib^(05Ck-bT3#IdxL$OFYSP7qsrOCa}
zD3PX8o~Km$ZVz~6($%SOrd*oy2qUbJeoGml`_kZ7z^jzj&4(9N(*7d=tCl{dMYl$J
zjKZL`(zsX9`M@e|P{FA>X+7=9>!r(f1G_<bkWSqXrCnV>dnEmn@?nkAoAkSCl730C
zsK?SVC)jP47E(=5i?pu>=3Aw!>7e^WI*(4>ZPL55q1P@Q-42Bg>0M0soKC6fTNvt+
z`t^X<EwwJ)jG^^NExpj_m0GDzuur-t5TsxF-#lmxNF(M#V^I3{9+()CUflsQEKR5Y
zZ$$b#A0CcMAJC6&OnPSoo#Rrb3w)Z8ZluH6q*OT$G9_I?smY@<2MSr(%1-UX1lh^v
zTD@WZm~1{pua3)}XTl46*-AQ$I>;8=VTK%KOW(v?ILS`Zxx`t<4u+zO>>B|Ly2^qk
zpm0LAg3h#VvNEa_c9-S3!;*)rm@c||%CuiX&rA01El7IHTxl)xkx8|f5?|Tx3#dlT
zPxc>0AWq8u{0T7rG96t64UnCuI9Z^q@FFY)$x=RoMzC!1A{0Vo&CP%bmHk0Cl)_~8
zloUKAi(7-yhs!!QfOlH<78N0!k!3#wFG6;Uru(dn{}X&VC)@NMB+tuI&Qbg`Qr1XG
z{U}+-2n=43{a%I<M$1Z~;8Toj6J6(yl|{?IyD0mcmaR*&&nc-GCyS<A4DqrxVc;dm
zPRvFtQC3bV!ppMP(m}4smhFZYNwTGM%1@Sk+y}`N*>@{2maDSd&*=F}mF31k@tSP@
z4QO1K9r^$oX|lT!FrO}yeU8oynQjjzF;nJI2$(F{l1}ilWmoB!bVF971i2}jKLv72
z_8gtMb7UbY(7P?$M@z~bSqz=Jb7f<tK*^KcEI=z?w(MJgS?|i~wgRm{R`4z6@}4Y=
zj)8@;h*BsP$!2MxQ7p6e!0!^73lF4JR=ElyWwKPt?3Bx{t^`_zY$xsG?#op41Fn>L
z(tm2GlC574%xW2@7Ya2pzq<gdl?Cob=L6Y`A3(3pDhpBqre3y)DlZ#kk7q%&QFegN
zv`sQ0?OGno#_6QmEOVi>X^X6aezL8y4U{o|BCGX+qiwR=RJzzMbEKlu4%w&8K<SiS
zqHS}RY`hJ;ZrO_zsp*l$?SM$HEP*Zx^~tPZwDIhhy}*VS1F|VP8V|~He+C(nS>s`F
zSoSyxWJI<%2Y!#rS}3wLCOb)|$#GdTMad^*A#o6yl)Xr$byKp&W$<uX*7X~pXJkv}
zf_GHj*@Zuht^Bi_(6f`rHKFsEJk)v^&ExX5Txi(K*KB}>gFI~~d~=kaq3V1mIfsrX
z&T=CyTQ2fNCb;h^=h3PAguI6ho}0Xj-lFdEzeX`$5Bcq_AfEEwbf)x@cTyI_TV76|
zeesc}oCc<^{BkvjpZtHj==^t59!MWj@RwhvWi~(_L0hOm`FFJ31<8-nFF06!kj{o7
z@}6mkgvt-T2ws?cA)PNy$%lN=87_C&2cJ&M11J=BM*b)51tR1jG_hypJrwOeCtpfW
z_<4DCF2)imA8e&>hD6E#S`Nhv@^`uTqesgJsSqnh{>ihLp;)<wR?Um@hDR`eNp3s`
z{Wy6f6(+^Yn<n9Qf_#WVe~I!#zhF$4<xYN3xFUZ(1(-?ls%D5J%d=^Zmm<%kqrg@9
z7K(PI%FQp)ov~~3EE{-pT^{frTuhU<%tI?(o}Ul24Ef6x=gO3S*aU-F^42#1lP&*|
zs#0#rrNJ0>j@&&ICT`0==m)tYU-=l`=gPmJ1Wlei?IAGp<<hT#a#y~3F?=eJXZ#3q
zPi~t4FRX>~PAVTLl4pJl{bKpK`5+~7VH-@8${Xl+RVM#U3(;~phhp^=^8Z#q;l6y<
z6_}`$FQ==4Rq`$o+^&{ieID2~@^U_=q*nedMMWOSZ>>eEP9Fa~^y=k%=;3IPTaSYG
z&?<jdgP}c=hfbikQQoDZ2T#6+jyI3xeLthKS^f&Gs4eo(!$4Z)X|$_+B9El}Qk(o-
z3rM@%K&S2wc?)fiI^~n}7VVNBp{R4WJaRL@dgKNPNU!_=?Ns~Zo9NZtFSk}LfXskA
zkzTQb@?EviACjNq!>3{S=2pzbh&+%sM5FRKbiNpq|4XaoxV%yay$Si|0w_$%ckM-M
zO8&tY@ON7Nzkkr0k;hPt=TSx3MnKyt?!1CdJ4F~hf5#N3DbsgcvD!+ZcY8(Fepqr)
zET^&qN5v;j_^UZ7nkfC~tPoIs$wlGQ4@p-=N-<g|6kIo8yD2`m1)95JBW;a66r1Rz
z=&2Z@BZQY?fFcOqilr1g^HKDV0@GLV2UW`WDfIL<JgMN1QM}1t@k=5s1t>Zi@FxjW
zgiiuANb$yQXap;YX!9SUFtZ^Usu+F>B4LVEt{|rr8u~s*xI(=HKAlz^sf776iknU#
z5sIh=_;g-z9>pSaA{E9pun?sf?*jA%Me$P@XS5<@6U9Gc6jmR|#41+OR_3B&<0crq
zq{z;MMx5fUSZKs6)+NA1g5ofp;S&|!b0BhA@qjAvuPEN2EpC!xH!T#&3S$OPQWQrh
za&cAh?IG||74C(Qyr%f*Jb2d?(~SU2Qz(#4$A1J?=;=+6q4<LKdYOu83X)_g;>9qZ
ztw{9%xuN(_3omXej#CNMEyZXRyvR}fz6GPWtymigyLS}II`DE8-gKPGQ`js6SiWNN
zG7R2T9Hl>Kf#R=GDBM#VsY9z!QB7M#Ymwr$Txb+4zNEP<Q8+Gw-=&Jrzk*DeB8KwW
z<qDf>h*l^bGC=MtJYNB?QjwH}QB)}^s-RG<So01n)hPZr3SO<^%1-beC_be}rB0z*
z1(bTlA5?PEpeRGx!JLN*rUFBHWL1bKKpPd_VtCP{h`9!t$BLI|Pu;9IPRE57#mz0y
zZ&mF73L;MwBUHWDrbwk6L%Tvb3KJcQy(?h8Q*nq+IbDiF^!D#o-24&F^eE=jm4jY|
zJ+1Y9ihp83`W0XO2r{6sZl^uwpu%YYWJvM;OCZCF1bSpf6y5ZS9aTK<474#t{X!TV
zS1itfYZHpuGti$@I8q*cN+HUIrD??issx@<NVcQ%sM4M)du)|~8YtK)JADCtOgYX4
zIj;0y1!AuhSZl#_QeLC4tvW0FC=c$UblZSVS7n(u$O+{^iq5+!zy1m>cV!Bd!FVVi
z(y!Z7`RY=b@KWv@hKRTF=w-Bgl=rEQ(pNc~K33qTOrgThlgiX9@Yi4I9SgkxWf<Kc
z3skP(PjeEa+>;H^V5Q;@kPv0SLTH34x26CsOj#$vFX@!>%a<^T;mS|wG<jONRSIX$
zDBHe)LWJ^NRO-w*tE{8@tLKz2u7ln4%I$m6id60tp%tav-UYo2%F@lS8?7v$LsE>g
z{369aW0heYaO$EmhJIz2lp3mgi&K`&g~52`OZm`GP$tlVoT!|MfZ}E4U8)ecqHLi&
zc#_hNVvWhlJgVzRQNA+`u&YWr2MVdm$z5n&Q>N&la9zoyeO#Jy^%=C%l`kjL`!7TJ
z9K97Ym9M-Am@MVS_0Y&xCh*aDL#dq&XKpG**=XHTzDr?=9Od!1fPGsTMn}v$$^Z(n
z<|+?}K=PC;6M>ztjCmCzca`^P^IxDW_#a%mr~Gg~pbM2dtHCQ$maaz2TCBW7v8)oM
zv<>rBs{H%|m?%@;VZva!GHMk170U1ErFdVd{2eALm3vuGtWv&{2Zd@Sn+1b4%Gj?l
zv|1&*3V(_R$|dxQty2#E53PFTol=kn<p;+>9x5;V0KG@bYT6PsT9r&EU^gkh8AtD9
z<tW{oYF2(91M@A)b_znZDl_Pp)UFIV2ayit+I)y~D)*(qZkLk5!qB>ve`?`VkJ7mp
zdcDeBKLNW>xr;K5{Yrm2S`H{{ZbE%fxjPnmLrU=hw1$<|MYMY#QP#W-m{Db|6jL*%
zTu2+pab-2_izbv=l!lm8O6iKkl=8q2=$uv#T)<#vlpjvQ!=tK`6c?~ntrS7ePIZtT
z-(#weF9P$ps+ksRd)2>Zpx~f#pnZ{}>irb(oK#}#*8p`^y?G17MK$~rn69ezX>k99
z>MzPdx~X284-@XHwl(-`d#JuM!-S{GF&k)Js%=!R;H`R{^8P-mt<D&euPU2T&wi>O
zDxiK+wfSX0`>Q-xf&{2^A7QwGDx1gfFi2&WO)<Y<l@IOuLsV(BR}59X+6lBU)x|%-
zJEdBz228l>bPTXhtH#=(e@5jZLuZ64t`sn5Re#f&^qlGpZFA16{>X#*NR`900E<%1
z{}!zas*p_ZqE)u^aKxyV(vupi+P#9Fzl*B3DDHDf^&0I_<5Y>wAn~dl=b)dUs+b0L
zqH3`b1HG(jy9#ne6`T#UB$YqaDI}{J|As<}YS<IlS5<vfp_8iWS_c!?R5_H4ysmmo
zncy^)^8h9<T{VYd&>5=ladXZ(CsXzLUch9j9BHGFt%|ik@rG(|G<>?L3S0&3TdJM(
z{i7V!l3+~YZPjOVI=Z9!gQA1Esz2%5nt7^k=~7aGiaigld#VnqTPsv$GoVnUdX4JG
zidBy)fKs9=TL*iks*QA&#9F5MHw-f6s&G0(RH(jw4l?&ud$o|MR82hwT9xXf-!Qal
z)iM(_YE;D~=&V)QeGb<isP3)<uTJ&sCm342>JR!RQ-kU-2jrn@mI97GQWgFWV`)@9
z7Y58GRWhBU9;>#pq1S9x8O{Q<MU_q!Ag!u-beaB%YF!eTZ7LOQYTH%ei$OY6ey$*$
zs<?CvtxL6wj;7rzx2NH6k7}MB)O%I&6nf}WRZy^?U*-EDPzF>wTD1mM&FO$1QdM=J
zHLTin5MGR^tpA*Y{-|mR6}642f+^TOuJR_C2~|KDWF}Rwj{{~(Rrdw3r&X==#LTF|
z+@Ww(y}bb~TXhZv3GLLo=)ibP{U&`4;<&na2qUvsFQrY7gL<GB#8Lh8e{kDLoiPSz
zXZ2z$y%${6n<;(bs$TDp)(Q37bQ{S{JwcU>?rOyX5D)eC*+BDD&m_W<m%8Ldpn0nq
zZvo9m-Ase=RaZwt(odaD5!#dL^V3l9S3A;fGC(~O3=*jRu?)N*wGHjXgVp^tlz#|O
z@1$6AsM<t%gfR7<%`kCFJxdH;xO)FW4D_^`xf&+Us3&OEj8K0rho!S>%OQ|+>cf=8
zJg@$OUdEB?I@)1JsTa}1aY22FUd_?!MKw^5QHOIuE~~SChr$*0nzOU<{3WTsX@;d#
z^^cU5xTgM>e(TrO`KKY1sop?Ajx6;TRHT)y{*Wr&?yAQq%yv&L_Jc^FI*hUkMe0TO
zAyTZqOn;ve^%o<U!%}tZ?@%aHe@sW|a&-+INGjBh6i};Fo3_*bvr1ik6C<ovx6skJ
zMtv(2GPP>kRru*XP(LMsXuaAYAC?-_ck3{157o<WV`z`mA5wu(qk5QP!H?C8X=!Oz
zA1TCGTGVfx2Ux56AG&hzME!me)Z5g{+X3CK9*>4Xr}_e|%hoRSixfQTR{wP$%pSGJ
zmzbembundD`_!c+;PtD+Xfr*aex80wgX-_^fj6YSO#!`O^+9?OjHtIA2HL3l0A;Dh
z)Msg<Jg$C*0$Y=6`|kifrT&`otJCV#*Wu`l`kSZW;Zdt5Xft4JHGfhd;+SSbBYKZ(
zs_9H?ulbN-Zw{JONg$4z)-HfLYv%bv-$nB!?YCVuzuZLYgvLalOLWu3(*ev~lSKy^
z56#;Y)A7<cQ;xt}^XCu@`Do@j1KL;fGbQu=G}c?gpeHqNQSD)%=KYUgDM<4a9Xf(F
z^C;^YqETD~FI4lO3}|7RYT6Q<)<`H9dPei!R)|Ds+$e2wUK6kl&O~Y|-vlp8BMStH
z(bx~cV64Ux1oIa)eH4U>*G#D4Z-VAKD;=v6HE9$zOVZ3xU^`jkF$I|vP0f0=u4yvc
zfPG!_C<H#GX&PdHmZ^E3{^(hnoUQOaTl2X9ts9!IOE7p-^W1ER+|s<h2X5cdlwLt+
zuBK!PtvrqS|6^|&VKt!dYM$6xp<kex{t|u{X_ipcQnAL4;*cep{k1Sysu`w}Oqph!
zQVr#r@ttT@Y9d|*uSyd}f!b=#=UFiEKx3l>Se@pjXW&e|<~mhyJkq?p0<A_($z@13
zX-t%<f2_Ga5B8ch$vY|k*P^MUmuk00{r{iT(3B6rw_eQw3O)2`UZsVqUlZ~vd>YUU
zQk;2EQ$!_2Lz*Z$`V4E@wqm+QH1(Yj8P%NG1iNDzqcbqaH4U^&n$V<*0XC^&-Upe|
zge`@IY0c6j^v%c_jmZVQN41NBF>SWmVY*0Qr{&NW<&J5`{sr1`?Mi2e*lS;=pq+zu
zXbU<WwUrbGb<$p^4Xd-Z=O_m1qTN}5C&pDfn-16~v{f@O@1{*l1GKyL=O7Rd?J+NO
zdTXO8-D&mFUZ8xOueO*n-+tO+3Mib^uB4A=_-kW|zzfi>`V|HPwco!1pMtbj+7*Us
zkB?#$VcMi$K~8D+&<-kGyZkAT(^`)$P(Pz>uYng4+QKGSI;-74FXMCCH@^htdF|Lc
z=!~>#*HA%nl(vj6+g#AzqNg%in-Ya7jnSsk+w`J#N`uZz+F!1M#A$82p%AY<G7jtn
zt^PJd61AIEKugk2QGHUfcKRcTq-Z-LfpS&*<U{aMwXIKM^w+d?lqk8bRnZqU(zI4@
z+IXgG-|xlfGqmCK!^qS+{Q#1s-LVcD+1j=5!^92k96E~M)MjLZ<Y+(c2X?MDQ~@vY
zv@TRMn6KSZ3DCRRj3g)&X#Y2b);;Y=5flowFK~car2Y5@@QStZpMaET|FY6vuT;Bw
zE}SaUGU*Uqu1)v`q(Zwc9pt{Yeix>#TDzhV&eUi->DzI&+D3{|KG5b{;C7w1ioT8X
zQ2Q%w(jIBA(VMnWJNX98H)-FYm*Qh><w}@u)~@^vA}w0ce2`YH(-tf2KG7=alZb8F
zjTEA7*XAq$c8B&a0Z6Cz76UL{+W*n|+O19f6rFwAQy;*YL2bbQ@8z{WQ2=sSt84*p
zM4K`n3Zq&9y;{e#-c+YIuHAJUya{awt;CaBb0a#ZwBdiz`)^wN+X6Iaw3lgLW~bY8
z0_2!(b`1<3*9B5Vg}tsO8j23OLzKLA)V)S$LnqznRe(C{w$h={Mfb*U=ycT;ufeb6
zgs$pewA^&6N~nA4UZej};-w2Ig4^CY7kdyN-KG$#fAQ5lq$_)Vx+;o}1nA~%f!#pe
zbM#IQ(!Jsem|$JTQs{^1xGv}n)y?&WiE!Qf6nZ$Vi}!;UXLS697(|55w*m&w>LfG?
z=XByMV4l}4qp*6UZqr*(h|;zH0EG)W-dTWIqjmYI7;lVDN%tQv>rPV%@D-g`D||}Q
zap<R;tow?-Bax!p5(l)aIu#Xbr0P;Tpm$C8=Pb0Y>oz0YJts|fiN2eZu3HoUlA)^|
zhNGD}Q8ijwI)51?vvtqE4d@%X=?eh6Y1MuC9eQu+z72<o9Gz<tdT;CAd=JCEqg%Wi
z`nkHs-(V?E_uoypmaltA=heHqIzNCG=>83W<UO5^Y5)s$I(rPQNcVmmFpG84yXY*@
zDQH10)!Bax3uU^m4KQD>^E`#oSLm$4KcabG_d^}9D|MXrV5v&?_b(WBwXU!V=4*6s
z(gR<s6Hp-kfiC!Uh}7v8U4dS`E|E@U4Z3_iL>}s%r9jgo-HsqwYSeYHz-!W#P#EU1
zPD-c2X5CIoA+_jiQ(>=Fx5T;t%qO}z<M5_UC$B<pyY3KOIq%SQJ%))+-7JbHcIg}_
z#M-T^UV&DR?msG5=+%usfk>au;}6*F*Rdu+26S~4XCBo3xg82ax)Lt@9o9MIVY)_i
z#t0~k>I$BLg)v>5jTOD)x-*o>p3>C{Av&#Fu^a=P(JiC1mYx1AEmX(!&l}J>uCH4H
zVy{2_3I^k#KS+z8qrN>8piX)&B~hI9-fw{CqMvbxo~wRT29Xo`3A!EUrvGppJa_%!
zdbB+BKZ)u6=c#{=(vM#Hq;P0>>z$qf(?{R42BN<D8A@II>&29Y572Kah50~z<3=b1
z>GSWy-(dYO*I*(<UrX07LiN9?(HW*!QhCQIy?~Ao;d(tKB~I(#po*k3`nE{$BJ?xg
z(DQdz|2kze&gnVy&4u%NSK9DK>P>F|G+IBu3ZgOk-)LQq)sNCI;i7)oPE6M&{q6-&
zh|>?fhGEC+r`JF-K_5Y-b&2}_g+b)9UPlLtEBfVps3+-PKY~`W{s3L1Nztd%_r0xG
z^};!@l&XLAGbmou=h4hw*H=-LK21OC0kG5cWm}=2q3`v=U^4X;^ft}X|3e$GZ2hcz
zAUE_M-h<vv{pxP$-O~4lV4iaHjr5|wtuHtVgLm`;6qL!;*PR7Qp8m6Fn9aB9$G1WM
zuKwq%Fkhgrrg-2z{TKOY73z1Ipi!jvp)Gl_zCRy|CHmDdP%PEQ(IxRR{j%pFS*{OT
z3R0nG(P{9$zG?~VR_eXq1*y_+pwLjYzJZR*HTv-X!CtNY2-PP&&|5PW1FcTKm@*~x
zdJ~1F8uUk=g%=O?=V@E_NPn2342}ANWEgDHcdo*p^07Y81-xec>V5bdJkdMT<KL$D
zdk7Ql`f)6*b2{{&Za}M3KSO!AF8$N=ukO0_KhjpdNB_qT==JJl*4Kg7r%$2{RlnZh
z8ej(Wc58t>s86C5YDh1kP};Cw76h0PJ^vIGNA*RN>KoI`AHe%@{gy!JP3Q}U(3;eT
zy#~8e`nF++OzV5y;r5Jv?=_I4hG!FjX=`}d3uf&MGs9N&9y1);4THxGo>YQiZwP(`
zE;<;b^kp|kLnD1v$;q&I19;Ac-4qUSG2EwnF|G#pKS53y48K6Z%`lf{#@!IN59U1#
zpU}z6)9@?R6MGp_zJ*<HL-*_WQ}`IJ(B(W|gGU7A|NIPZQJm|f;kA`e^fz3i^2h*#
zWCR8S4Tt8zM35nb7K&iQz#uw93{$s&9crkd!lW>Rp&8_q;r7okA8xotS2Io<>h^)0
zF=!3}EW%Jq@rd(=KHBm{8l32<h%)SdMElPRhA;P_8EyDY51AN)k}_zqhPD4f^rGQQ
zR}AfvVHs6{#~J)?LNea4-Wja~LozMsiH7$((0SS5LkX=bhQr^&izLGjJ20ckhV2K?
znPND+9;3f%I7DStsRj<^53U)~Xkx9`4I!UkGSUngbmuhP@KzrbGYpxTu$yT(Iv?ZB
zGMN5>PuYf~JCM9#c#G2MHw|wW1N)Yt=?(C541TrfylwcNB20G-r>T}8*Wj=X2J;L#
z2sF*fH>e{4cGr-;5+VhL*`Ba>&uS2?1QY+6kJ9)>h9U}G6dS&^K&Hgt-hx)C!R0XQ
zmKka&F<Wl<{S9<h7+w;A+&Ao_#6hKD<_Z+54BPAAOtpbS^_w+@^-`FqHT*(9od<?Z
zS74#eu;*vYMZMt}`iM<~!P-HYgNKHW3m}gSseUl=*sz;6V$Fu+3oy}Q7?+^4)o|h&
zjQ5FQ$vQ~38RSg>Z8z-jfMkb3PPvIr!_3Pt(Pdaqe}itr8af&G7z|Xb(QDX+)5e@W
z!zxN(_Zxn10Oo+<3oAWGgNC62_&sE>qiV%rgFP(~BZl*KAfpD)?JziIaM%knZpi%u
zFcSuOFj|v_%~a_<W%yGClxainb$BsjsG(ifQDgj@@ZQ$AYcX1OM&>&(c+B|6&(J$=
z+_VA2-uQBa6-)=?R}?36H17EoFiys&+u@9}F|hzV7bD|76kUxk(+T&4@pUrqW_;8R
zeRpF9Z8toOp+y+4r|}*oHN1=qlHrrLF_Yf#KE`Y+jq^3;y#_EpV}cz9c+&XHQGody
z=PadfMg|x!B!C%c+_(;kK}IFjUk4j^Qh7&+v6)t;P~%D}ZV5Ava{zkEDB25{Gsbd?
zu|ya}bjCYtoTeXQq;ZZb3`QAS&qMNpvHMf##Tu6#0PmtvK<|-D#vj9=kYX%6MfV@B
z8p}>VCe?U>0)f|zZWD0ky7A6h3_H!Zc`Z8AjqlS7H^aDq-jtcfB1%$c8E;WlX0~zk
z1z5Ua%sL8`o5l_*eY|CSObcU<F@rX6w~h96oVsHS_knA<#(+sUlV_}b6(ZJrW9%lt
z+%-N!vGW4s2UKW&&$!+V1`Cb-bbGSM7{!EQvGI?Op;%(vLg|1~WB$v~D>IszaHib&
z8I{;n7{7lGDEEzPD$uGl2LB6EWt>g9%xdG8beXrt_@6s4YmIA(_rRy+j*a!+HrRY<
zTzmi{cx3#A&XtYEulyj^WPE|L9FL8+L(pnAzCaf*Ta3X2&}}txn!$TwjHiusn=#@H
zP}+^lp98PM=zATlPGjQ=Oiq{4vjMZxZ5$)@9^*|5TD`_$DwgRpmRr}L*>Bwb3q%Ku
zS^Y3SXp}w#_K=bLCdN8!{E`c_5o7KpSQ<6{r$cMZxRQ$d#*O3WVQ|9u0aa~H8*^!|
zJY$q!0`^hUjebblnpUwOX=gh42w=xdMk?t)ZaO~~_UujfKcN_igXs%9h&q}Q4q@V*
zOe|VYoK1hzyU)ec{{U#NrYtS=Pngco)kQbc0?Kf?o3_!h$HNpxTLn+kk3mrPGR0Hy
z(c8p02@^i1qOT$8Yg&5+l76O0I!&K69i>V#f72TQbO$fU^eVk5f=#Wnpb=u~(E%pZ
zbcpIy!b~4iG1MuOyAMRdO(`;%KW*YuQ2LDNErN+Ky=e>Vv!>5V;pjQjr*qIcZwf8}
zN~9^@4kXI7@ix4;U~1|EShVQ|g)3rA5qK~@nG<VTO38zZrumzJeaZA1Z7kzVEESxI
zH?5XJBf%6#Ik-gA^^<5_Hi@a$;EJi@L(FWFN!)=}vPtU+y%dwgXG1>6x@H7eX{KyC
zs-~Nkyo344FxgQEKhsn`jLs}m5S^5>O)9EXxM8ZL6xdCZQxHIInKn|;KF5@F8z{F;
zF`HoEj%m@ya5LA`NyhU`?@~Z8-{ea<(YvO-`v6v8dS(Gc?wRVWlqf1R75@UeMW%0x
z&|7T!{u7ulF_pZ5p_H1Q(Zh=})2CE~TW)Ik05BD%gI{5M_f0=<0$QcXVJ|wXOrG?I
zs5Vv7Co5`9LG+;1n)>H}_rTQI0hBtE>x<ykn-1rp^N}ejkupn-rtD@IY%=w;;l*Q9
zT{C2wO;1yuQ;TU)7<jFweV@Sm6O+g95NR`M=>A2!X)~#Jm|AHQ(rLO*<)mFEHvL(;
zO(|N;Q;+F&D!A)4ZDNDhXR@mYuirFH1uz4qZtep7ss>HT_klKKLS7k9kx58f-4PR?
z7Q=DVU;jaW!nA>M9FwNy6sejred-30Y11qjT$?c+rr5<%vtbCt)~wEfq@6j-3wp=Q
zPtlg-xOo>{dAB$3w!p4~dG=|H-qAdTXHhuE$(%xoCTDXNg^FCvTPO(NYF_IGnG<Gr
zpQ8n@SgYwmxTo3M4k%vcO1c8$ZLV{MgFa?H?Sg&Hnh((OGrvkn>XT;nVkr2V!)cKU
zFi$kWvp{nL-LMKWXHmF0*j)Y_S|R2UT9!i1HMH1=nSE*Bddj?mQj6i{iU71un-5#5
zWcrNxvljpwVGi93jkD&dV{rGJIrMFyoj0$eWOJl>Jv~cN=2cWfalvdi1M|^l@2Aii
zV@{(x+p%W$U+BDOzN-fIC9?;W3&okw>_98typW2l63pqvP){_kmP7KgS@wz*%`4{S
zkHJhbFQOP&vU$-$3_HcFn1?C3YR;#9V5)gBB|NT~{r?2-x_KK_yrh|h6M#uKe?tFa
zD8qcX5tg#ey{`fDhS}!}h}<+!u7mn5bLL`*<e0~VuyEU4OE-M)nB#t-^kc5sZW5q*
z=BFr{ns08S1^=%3qZyC_^Y?BranHOZ8X|?5Ahe3itIaS`Z1#8?CQ8hjU6`O!^9ssY
zm6<<?gr#z`bU!33%nh`R-ZxjYfmE6U_rrXZ`3Z$es?EKhQ2M{dtf5y#tvNjyo<1<&
zhy-?>*`*es_2xP%N^3C3(SG}(Ihj8B_sD!_J`@_w%!Oz*nH@d@_G9xxIyp6)4_*Xm
zG0!{;^R4E&bO?T8{%$_T+h$%sA@FwdDm4^3%)6;r-`Z(zrfpJ}IcyT7+gy?f>>l$x
zx*XVRw#@+PGr#%`VEWA=LHGp@nD@AW44S=`!qSkrx&nH`W>*f#h?##Myis%Cawv?M
zU#x@o<K`$a$b{KU(c4M$R!aCynO6t^J#96&{sNd8bHSU?IBLnIzpt$&h?XfkOBMas
zr(>2KRP1=%;z^IDy@ekFOHP*H-4JoM%sB;vE|%rB;JI2py$#6|mYCU?LpRHN^aT`m
zOW;3fd03pN?9S8jDV3OcSzcZa1#gSBXajnEEX7pO<ZEG`#pwMkOHdd*=cMHu3IX_A
z&dq=XSXdNr4YY*No;t|#d=1<Vww(AJogo%Z8d{;2AtSKEEa8XX(<#fuYM_K$Ho0S<
zr!71x<vU~9w-}?3u&k#b@L9{d)=O~loF##NUgs@Fs@jdTG*HAd%5sD<jTbB*#()=X
zIk5=57|U*|sf)F|;|rfIS}u(P?UH51MTo>%=8K^hZ}Hd&l3;Pm0WZ;FLt*vHmNGL8
zUa>r5fWJu=Emd$NTfW&sul^K^;}dv#)$%-5x}{o94`DFZEQel%!`Ce%?}3+QQ8l5J
zZW%}cFT>)_1zM(MHys7CEQ3G5e75D$dl0!{Nnt_Zro~FtEVnEltbjs}C6-d`w=KJ#
zfyf=p+7Ot}wd^aW@N1r>Hx@GamIx{|xNG??3!nv-|Gq%0$YQI3!^M`J6%Z-06jEZS
z)UsIskur;bvU=r~k5)ml!m@Nfu<u)b@W3D{Ez9Y>TxH42fnK%cZ<4IBtfy-MwU%>S
zC_JzPtfK92o#k>K(CRHwlmKtAy!anr9$IE7mi)-#Sb$M9T8=)8F*RALp9bh-%NYqw
zG+UClg0xs}1VX*llIw&qJ+XX63HvrnJLN0eEgAmsx5KhM4SJmxF;zKrS&C^l+HFZ+
z4`-}BmL)6D+iO|ze;i$Re9l)FucFl|ZB=P0tyYU_)p+*adxokGtx>c_(V;rL51E7@
ziI5>X5fYIpgM=g^JCQ_?K_(GdB2)JJJ^kx^&b{Y*&bjybjeE~I_xBtG{@JQ5ir;jv
ziu)FJdscl%kHX$n2{9mjtFC0jwf<ESdK3<<TDu7%&sR0n12?$J_&;z%tK1jDr{Pr%
z0+=6Jb^K!hMpyOGN?>f&W7;r|uWF=+&_PD(D6|~1G2V>>YtQ(074Qy>X;h@?$k=)s
z2Avo$(&Rfc3U<L$7sk_GAPzGm4=|V`jI@0aab--Vb0S9>QTu^A#z>=jEH}pDEc6{`
zq@Rbu6O30*!I_hc^)Vpsj5QJfJQxS`(BjFkt*6hK`7yRp=;17bxe1p18B>N~DS+{S
zLQ8>+6c3Of#_0_Z31-a7$9O{+Z_p|(lo3LEr7(uq3}_2ys3{tHp22<%@C%INDu_ff
zUZPr&D8`Gg!KaIi=+gj1Gj1OOxy0zPIiod(Q9$XBSVkk2GQ}}IqwPREBkngeCNP%L
z`XZ6Bgq8xA84GCfn#6dK_Pfc9h^sJ>!VprVCY2HC4ekmfh8})b8Nby*GL7-oB;c+y
zS{A{>42E_qNG9X>9*``?qH-JP4F;29!r6?>*>LJ6!+s^y<S<keMapF?pd?Hl<2FU-
z^BJj>94KHcUIkLfSV~)%B1QpDFHbIJ$i@LEVSE&a-{2PGy>j%GGV&xaU&iP$0A9}M
z+mF863||?@T?V6@j$hnkY}p8zO2&g9fT&{3rC3KbV;Pk@)G)rKSk!&SAA7+)VEjp^
zsA?H6ri0Wm64zn!>KWU=0<M7}rJB}8##%a+-o)s%hn9y7VG_K5#NcfJX=a3tVw{f|
z@@P2I!uSeBK(@(G7~g*l(N>0y>PgxdeY6N@XY|u<zk?x`0MW_7XUOnYVthxXgk6jk
z%c1QVW1Joo-Hf8s5b0smoq+jX#zrb|=wtjro7jHF{W)-EfU!w{n`($L{1muh#^!vG
z5r%XT24Ndz<kx{6V`wO|I?f1j1$T(4qtau0<|xgq19K16ojNiv&?C)>`C>2ZIy0A3
z;j|00{&%Q3%rsFn^awM4I^eF%i0$BxGQVC5kz>qVRC4LYT>lpwJ<j|%1KbH_G{TaT
zPuiHx^pbLCHlG8+gUO(ku_yBbTK%44y3sqsi#b4F#yQR0|0cLI%!L${^k#lXaRnb{
zZzXWP%zwT`qaX95x51rdzA1)of98QUSPEbsVgMJ&Twe|@i1{WJ-v%>hm0>DFn6@;!
zo<o_2GhoA*wX}x}XFmBJ<Q(%E9d(FcPS3_D&NHR7h=^jYqFekTGlB}pqM2XJN8csp
zj}#1wVU|Pz7t1XE0G8sI-x~mrXWCN~Hi7B*B1j_hecGU1W>(UpEQ#4|8-O>-%r|NP
zOkujvMU%>WB@Cm_WPYiF(k$k$^kllh{DNMQ+06BGVg4qwpcs8Q%%t;x=P@@N!yM)_
zKcxg(0douOAPSlGwGb&{X8#J25@s$X9&RyLN1(5i8AVC5GG-r#a)jkfJNhjum{XF_
zd53wC9-eoZ6R0ZX9`n2ZLI}+1JAtTTde;F^&AiqIks9XHaERPzvfcvx0rL;~gn2Df
zwI6otn9?kau%2m8YyJjij~N~|GH+AGN)z*Eia0)Gu76DT-y`O&W0=ck<}^y@J!a<7
zTCasUZzISPrezJ3wla59=~f%lj|X5ob1D@BbTDU7VMQl1m{NpKnX@Xubum9%1nwDA
zKM0-O%vblpd=K->kMP^|GONh#K4uUt7y6mQUsCza0Q2X)@NI~>fey(IGvB1$=Loap
zIn0kTXVb!UjH!4Vu8lKOFJNegSS6I_v1b+2-ob&zScXPNmgFZ8Csw%~l)11DQX$A;
zR`FVxKf+3)AI6n+VIlgCvc%6o+*m6Pq0e@lRn`b?Cs=w4%$;O?@hLjpS^QJb?ZKKc
z6ApW_zNQt}Db_0=f_SkuQ1tjTt7;=moMGvkpxc{up0>F@tSNME(3iD|7U6!ZWGbsV
z%X;r!5P#NZTcIp~b&qN`0$CpPA_%gv6ro^)S<XD*Ls+Zn4Ij$-d>Obf)|M(53}@ZX
zg28jF*lv&r)<2Z8KF>1!0g(%=C@MFKWOYztHi{MfHpoTRx^(>Z(X3?3vtD97bcKg8
ztdont#j>Qk;6(!Ka1bODS+=ds7{z7QPKt3Rv4)nx?_}0FA@C`zB@~6d!n*q}xT~z0
zYLGNm;=7PcXIa02`D?5V6qn0jd9?zU$<oqi(6U%#{^+~G`mq5c%w~Pl1CboocXu$d
zT$W!ooXKMuu0SN8rLxTfuz<DkRkRke)RZMFVtq<a)M8dcCuB-kaw>qn#fqK_ZKW)`
zpJAem<@(>AhjlIkjkj5obkJSFnn5d}JFFWspzJOyyd5LE$6EP50F|unJcv}WUZ%%-
zHS49N7+DP~u%GU~`z(K2K0jdPGk~aNotXrgI+iD0f%UA{DL2u;dV@B|jV!-h=x$;S
zKE;?GviA1C(MK$EIJ7mhUdx3uk68z|LZpTDDUy4WpRiKDL1Q~hK~?J=ESDS%u#=U*
z2K*`O_}g^<b+H_Dka@<cqYX_D>nACIy{srb8v9swd~p4&Dc`~U0oM6iSQ=y{QL<}@
zrKO_7Vb)u-;Mxf51QqIxvf}7&8fT5t#_b^6)d6-7vFEJ;XV3ns8gK{pNBiN0BRe63
z(jQK2K4lf0+21js&4s;{>V*!o%jx9Z5q9Of0J^e$KL&S{J?jR@F?Kjzk8W&lifA8a
zucoZP3HDV68c(v17Gp}>+0G1@@L)?LpxTqYib_UKu{|gc;Kg1-rJASNdnmkZJHsxQ
zVuHQdKhu#RANE}d9QI}ZJP)0I?D9R}&ayqJ^2DDVO1r@TcI5`B31qwb!fp`zM+GE<
z*@r&>7s9?mQNVC^%?tp}vG38IG=j}~4xi4m(>DWtfqi-+;F0WA8_^hLWAAYWFq%E@
zFNj`Ze_e>y81~Vdup7%3Qa&t>T|gO<cy<8AM-$jn3qUTjz1ISe#7?8gWHLLe2){uJ
z+h-yqQ`wzJEKR<`UcLw9Dm(23SV&_R(IYgS{Q_knud!KFL~xyLOQiajOm^CASju8Q
zxdiS8dpo7hve_#srE`<*PDh4v*pYO3<g&Y_!+bvb?lv?Qu;Y>;QpkRRo<2qF3mljz
zW}7QuqJ;g+9EjXvZzm7S*sJN+DrY-V{mO0jpRdDS1>1(dY{xCbR=f}VUG{`_0PnGv
zY=LMMd-_dq)okCpFj2$q{SZ&K`|MvPqwxXzL_Heo*@xD_U<3P)TYxvRgWklfHL>e5
zp!*?vkZLv_v3Jm3wwc{UyRsIxE7fK{VIQDvXDeG!K>NQo_QT(yt(~1Q1<rJ^HB<)E
z$=*$|%r1837jXX>JL@HI-R!(i0q9{bE(X4rEk6pbkL~LT-Tmx}aA+A|uj+&O=WOSF
z;0D<;FZeXX9!&sXgq^0w=ttQf(^t61*gNM^`f;57sTWKf<T$C&dWf@=);{)}AHIdC
zBj*=?XmjG2=z9UqoP<jly$dIo0s@CQ#_iC3g!4lWaIT#5e!v~$1aAW8#`#qUa-3tg
z0Du#mY3<-na<Zsy&7ISH05}g$r1S;cf2TMZA?WntyqyB2r#W28yq)3vun5GP^Su(I
z@Z-EX4&7%taea{V=QKP47r+@{!nHuoXV2h$5NBvPCMcNm3vHf5IWN#!AdE9-58&Y(
zVF4P?abBc!cm&7N2rcJ1Pw113whNpz`n97tS(hMlk+WwE4o7puooKwo(a<Y4hNGjG
zYAh$^0s7)N^|Tv|=lp#VB!RP(Zr?->YZHccnZu#GBAIh`0=!S*d`S<XRL+js@Zt(b
zSPm^$Ia%~Uk~GdbI(3z9<3!T=iR+w&v=7VRZ2lS~lk+1*pRzcs=p}W7<Ej9c&Drk`
z6E`{jH6Xd1>{c}9ajdkY&*vPV2z>!(zAH!}XLclJrif$x8Y0D<rU;N*oHuE$R?3+|
ztKc%uD-?|>=h)PD(R!P+o)VUKIe#3$2=8$!H^a9|j{Qskt2llyU@ogU4+_y(!%3l?
z;(d-L3#69w1s%Pq<NS{%sGif;41XIqOM_v)k+bm-R5x+t-$Bbm&g4P#HFLhA+y61g
zMoa1zPKfOt%+M3g7e*jjIoU&Ss*SVR38bCVGZS_@I4%n?U!9yIl;nQOIZC02F3v`J
zRdsXb&{L#`Q;`pmUQR$Jyy)XptcLD>&M4)q1~^6Zw=vH-S?l2a5N9V9wG4A!kU(;T
zQ?`@df1{j#{)Fflr}IttHqKe{6_g(2s?LGfbF*ke<G|fVF+)f0)z4wqiF=HGSZD6n
zv;=bDYUw1~VQ$AR5Ld34a@|L{$JYaQj9Z@w5jXB<bW-U!S4mq4ckcZy7=#CxqoDiG
zliPF#h*R9H^U&$Vo$>}8KFw8-%o*-*B|P-u&ME=t%Pnz&Qa`T!Q_Rd+?i+K^=+DhJ
z0T;lX@d8L7cRGDXGnm^(Den-jmEIho+$0rT3*){N2rt697pb)S9M`S(Ros6O+$EF<
zKhF(+403^cgC1Lv-0vtI6ve&x6^0$nU8{kbOWZR05<(1j_apcl%l*LxB#!&Q8GZ5G
zk{NI<fxDs~CN6VtO@Oi_ZrcbNlewvsok`(l(g$Z!xf&rF)3{q!0%uF-o;m`9*SP+-
z0KCqfTMClFJxN>QOl~7woSem7n1aS^?p!KNy2;fgfXm@7ZvdCeozMtNdECPFn5TSh
zAT4tWxW9gcz9McrRUZ^{TfT>u67D@;aJRUzYN#&ddg{<vX5;$M;=i2h@D04U&HaFi
zaw@ogQ+)dlclZZryUYD~7DOt!p|ldJ;!dYzaWyw^8^%<_-SZc;-RJgEb;$#+IS0<v
zawUh*SI_OLfTIoEK|0{y$lXZ`xF+sD^Pu`6cP0hPA9HQq|Dv^p`$8aEpKuc<!eA@+
zgB}=c<F2AWMmyKB9HfK$0#*M!<=*cCpo@Fj1oDjg57j|;bGr{iTMsuf3nIN-F6E5+
zxYsC6IKW*?ubk&x!7Jz+<W|$!q#>@M6oVM%M%gHOHNxdIW7wnIE~;`I<DRky8Rwp*
zGVX&sKe{Xr@%)@IdI#Q0s`7B;ot%M2CteX{?VNeDq5yE=t)be%!@TeE(RYN`7z@Br
zo`)kuj`4;IVb_gkPYbc*yuJaD6THzx8)Q6qm+pY|<SqCY+$r8q91t(w?gjAaH1F5n
zVeky^(KHOkoA<w^7=<tILp5gBj~6!!<ScJ0ZSMSe^C<Biz>BWOFA~Vh*1&EM&$Sq?
zh44P1g;*%>Gg|kC@vIb`59jTlN9)gXyoH;9kKm2e0)L(-rM3749&;*yk-QCg;G%f8
z&(U|0mrmtEmv~{%0f^yEqvJKPJpBP^i{rJ^0x+H@rLyq^o-f7v6M3h?Fzh7WcmKnb
zB=hXYKvH-aCjdz0t@fe)-xXdEJ*Lxn^%Nbs#=A}r=Igv2w3Er;J(&vgnY<ajP?N=b
zJ041J@IL$zu4VIDXMnrOTS+g)Twcy+5Xs}QPQ#~so;}r_7VsYJf}@4J&whsLV%|#|
zfh*ztwI6-Ac;gR%vz767(QCh)_tHAL0eIcCovYwYrn41yc+FIub(i<eOf=r(&7duH
z6>m;BNHuT!Y~X5mLkrP&pBGH${~qvKCqhdtFU}Em>v(S+#UL7Z%(u|k$eUUMKof7}
zKJ-20Em{iPBOC9=J7Al6bJxS*6P`W&oop-5=m~9Yys13^w)0-5bIu*SSh{mMc{L7@
ze99AwA=1VBfR>8Scm-QQdU#C~2JPj2(EtzocnhDwU_Z}`l5+#R`SdNDL7od2_J(*@
zT+leovt_;qZKJ$UIxH~8TSXV*I4}DQIuG&}p281vh<}kz1=;h@%)kUY@aO2D+lgP(
z14(DTkScUs_~#`69Oi#SwIWCOsnt;C%Fio-rK9{!RdCylpR*p4$N811=sUrmL2v()
z{01BCtljzFQ1-@yKg9wyUi=ll;7;>3?r`l4Kl&IrZ@vqy5q<de6!Q1w|560bkAHmw
zxU>Ac$8g4<pH>QZAb;`$%uEpf=2zf?`7>!@62gCxp39;9?sg0!oNuP6@j3pci*)}*
z@E1{<^a4M71;!i651~r@D8AwZ{JzK^#VT!bG=J)Eki5jNTMv8;f4~T(as0Yej4+<R
zf$pCK{!A)wOysNSPQA>3Z6Q2N;=g<ejmiAQ>9~+m`R{%K_!WL{F5p-BmtLmh_i6k&
z!w^m9Z_}Xl8h<sV0W<mYg;0~l|9k<Qxxv530+-D<((QDUfASGX4nO+?_?ydro!0Vs
z{OSu3$>;z63*ZI(@ko$D{s95{iuh{!GqYm;h0owj2|uV3b8(Bm11Un=<Wl}oN+*=@
z`}*NUIscQ*Ah-G3!U3${zcmPQhu{1LNF~4MPmH39|C~1V)%?$0AX&pVQ7!F#epWcl
zKj6Pfl@GQ2Z(jgc$Dc>9s(Su03Ys<W7ji)w`Nb;$Z{j~W01s^s`38DSKjObd`Ict>
zU8)3r%y;3!QVXB;KTOFJer*;+TKTn<fo|i6?E}7@KVd!^pYn_4@S=-f91QLm{}v_F
zyZLz(9`E7%#lU<ofBvr+U>`qWC3N=l?OmXAfG?&6=W`q1*#~rx|4teZL;Rhc@M4&s
zGzVUc@NZF)ZImCm9*8l1s1LYt{_sAiIVgzO4W)+!yY|7Zz2IF1TyqdC-HtwI!4I_B
zaS?2x<IaZ#&Q`#W2(G3=wX48$2gp&u=QIh&1h&a!&`mI54CJ^V@eZ_|5d1`!=SjgY
zpFxd>U?n-@DY!!+<x_&+=7M+$tXpB}v|xk|Rh$u&Rs!HHaHUwIkD!)TJHCRSDfaCr
zU_L_MS-}$u*aQe}Q59*Rpg;i<BsgZH6<n}jQvrY>f}g0eB~-BRV_Yp^f*V&cGvR`t
z&f<4EC*ZsY5+Mj)iN5oK-{XOc6r7>Y97GA!w4k~uFb-l&(Sj>yVCj;8p#_N%tfZJ<
ztY8bR`r`yrN)N{ioZg3r34-Mx+0dFOxI~v%vOq+O%M`)SJjkR9p8g1Dt_W68n)s?<
z0bLMj0`bdeOcykU0e?*}ow8Kd1+RS#T!vtj-XocU=BXIV4Z*9)@HbmfyA6#u1(QaB
z%Mlz5L|?AJm;RM6Pw@LL`utkH;I<nES|D)Q2}GeFjtUKm1U5SOUMxsD5Bx2`v-dIU
zrGkKKuv8{^OfiRY!LBF3-4?tlhiesr1HZ$>9YOtF0PYG_Q}*+oVDSQwN<q~&h*Sx#
z(<-M%@FM-n_XS_Q{9pc0@Eu)&wSvQR%DYZb5dcyzknM*v4Fa73qK$$G+EO<OQmGj0
zp`f2$k&gtubULm@kV+>!o(Q(mlD<`NjM7_eg4L9GZx>85fpiGY&c_^f3ho~P?x|pV
z8US5_j88EL?K8n&ltAbfET;8quVBjx$n*)!_u+8Aplb_E3<%!uL*H{jCMCcJ1&>uA
zLxQ$QI65q-qM+!ApxD!=bFOX0VYJx`XMGH`gRq!tq8x?aQgF~o_<1;pv+#AQMR5_X
zqe`5^!a<smBf^OiC~+0;y#|qELN|Kkx(OG(ilH1AhR~^t6T(yD0Gt#K(U(@-g&XLW
z_7KKUg5Oif_69j6oMxlfu9r~d4Q;1|{glx05juo}^A&o$kAe9KA5kLstZ>mq5PxAf
zrJMqU`@ewOfx=*VT?Yw2rVq~s3%%&U5+W2*<|$P8{sNc?7dp^x=$vrUmynDQ{`?fU
z^TKe7&0i3{JjDiJq;Mrg$)be$EVy`4=pX<hTG-<QHJ5}FW&;=_^ru%;oNx_oZsLVM
z%!H)`;aPf%B?>>g4DPb9i7G~tgwcf%Nfyps3P)3fiw;9)s&H}#bY2k_eGieV!qxPB
zsB~e_?^MirO*p>|maYred<dBgVK6OwGlhd!(3mCEP^IM!;r(8i$QBBtKyC_`)2X-|
zVLILQxkC2e02Bx_XqjCooH`e{BH<L;!50fBNFh=p)Usjlme4Z=&XfwD(9*I@xZoZg
zW+)fBTnGNPkVmik3gP5lh~5<*rCP>&!qc?$sT7{R2i;Y|Kj{5YEtKbCE^34|{*b&c
zT=OfY^nq|bZC7iBo!0=U6TZC)1FaVhB}1f9=uv^jCgD^1%j1Va(>?S(5^kb{vbJX7
zTa<KtEF7f_Zi{e5CM-P>dc?p4zF9g4q)jNC4v}`@2Tl;_6xz{U^i(+S4=C*thGk<e
zo(Wr9;aazFj7mLvg!kz5U$4+ir-u844NKr!zi{J^fDZ^u;{kXs>|G7>!!}_t74M7)
zOXw#V6~<CHeM}fnLAG(BTLDB5iiAgC@Q{c-f<AjuFMU_XLG)4(@Q$JbbbiiBwAKXx
z7twr5-yIfZJ_PQFh)p|MS5Xap)9k3|+%NFrm}t{t0Ng~L?$CK$WLxC|7f*;Jo#;F%
z`nDRn-9-cR==BucZiCDzQLhIOUZVPE(0y9O?ndJoQNkZE;Vl|m0?tR|LI!<BFD3!!
zC;CKyc|I#LUVu)2QBN%9B2cs=2VMk;#_Yfai(<Y97b23|D0LJn`gtxy!$dWYU?N<!
z>?Rt|iQMtDn;aqH^<ik|MXwHEf-Z=19zyb>sDc9E(IO@7=P!wr6#kD9{V*Gnv7$q?
zri>HqrQLbF=<8bG5=0I3a8DF%y$J5IXvsU!k|g?Wl!~cSM5hk`pDLRE803oR2t5<7
ziaw>X(lpUrdTpkQcG8t_P4w15^j#Mnq-bJ>sNM*JnWDyTFqkY+jvgY}qAp4e+!R$)
zJ$;Vo^|K(kqEbpC=83M*`#oQ@bt23ch`LK?HCHH7pN5(u(SRF7i$#J(7*mO8*<_d~
z6@B#z94-@uQkg-y$V&OB+alRyh*XHWC{KAu^yx0>zAIY!FSOhf{hbSuN)e|VT$Lze
z0&vx$KMfef1JNBd%-4#HwCt=C^&uE(o7^b+@o#iCiQX4r^bbWXULftFG&)?<A*!LW
z;Z9LgKP){Jt^5GGyF^!xf_o;~b`_*s)L(+}_K0RVLb6vh<_!~lqUlua(=VD@2yQ_1
z(JF{M7d3r?#zE0j+Q1KqY!?By4U6W|8+JrA?QPf{6*c?`#F%JpEXcU%1tuB~ihVqR
zI3#YcLDF8_G>V})h-dhr(NX;88u;WS9{0qUoW*_$jKxK~)C&d=i<eLd=@IcRy2f3_
zv6M|aDn3VFD?KLONp<ONHt|+EOL$ydLiG(N#0%&FcT%jNWUagSY6}`Y#15_CJjFlm
zLf<Lz^&P-_iO;P=-)Zp}T|sBWA67t%w|GCLb$!Gy(W}^3-1Q=S@)O^pN8wrVg_m$y
z`io=e85SVsPJ>9G*k-18c#t@o4bfn6@FcW`h!bc@94g*!fYLDWQ#}yj;+xOl#W}GP
zRW3$|9jG4hy!iVin34<Pcex;u;sA=AM~R0rAaYS0kOz@y@sg#$T@rg9g4;3T-Spm!
z6}!+S5GT&EZNiTbFMhTiq6y-GOAt*IuchyJT^7Io4!9&ShXPZ{;+^-<m?HjcGJvUK
zNh4glBK|8CB3H$Uu`qZ|{ILa&UKi_%A(A0JK&z@uv9unlv&7SSA#y`pOSMkf;=d@D
ze^Y#FfFkEPVh5_3&lSHyYrH(M)7$9G7yn2Fas}cSGccw?aXwvaMdFT)z!!_l=;Kc%
z;=o|QZ;3-`*;*<trY&Ka*qjbW%f<0jTYOvGnGDqx;(sU;b4R>02wvP3o2+pAp18P=
z{!FY=yq_vPtHedW15qtrI07{_;*FG5zAsiX(f2_7;XWv>72nB(nmX|{+62~%H?4pd
z4Pu{um}nGlx(TIC;;$+4_E5~J1mKbQlY_WCn#F=s=zA;<F9X*ij`{^!o`~1)pg)st
z6*m`Ppl#w~ucNbFtnG%j4squ`sOc1k)7|(~e1H;BUE;@0@adVjhE~+w;=cI+^oV=5
z0njTh7=cKim^})+{o*Ir;o*R|b_{^$;s^>#42qx90Efh4T00MmGn5#aZA9!+1({KC
zS`@q(6GzadYFzy2BPcy6@u8r`AxU*IMC>K8??c2v5=)iUjuQQ1D0Pw;DM;Wf@uZR`
z7s-be(0y1^zy^0jvU(JptK{Q9!5x)U?g2R_DWW0?H%U<}96f21teb-$)?LzNLaT@5
zYA(j>DVci@mQG1ZC~N5@Iq!wO(~?#?lY2(e^fNeb38w{kA4w^FgUwemu^s?FiGUV)
zXC+Ih4%lB3Lic@uL`LbTK*^_6!xJRgz7slwC57K(^dS=4?=L`2sN`rcM8hNxvmg^L
z5tt!!PV$R0NQ7j*3?81B=!KYz3lg`hkc^b{QFtp#GT#|}7bVxI?j&0B8l@XANjA5F
zi;?uxuwx~rc_49;&)$LRc*)@p(3c=tY7Z_^Qe>k*z-5UCZE}(%HB_*YEO8^BQY7mr
zT$?IMqB9d$B-U?W_o_s66eiLnDvHXdOLo&+_?o1W!s*u~tLdqiC2@QNzzs<Pozcja
zY|>(8Zb||<Fqk8G!2xrTE7?xZ>^#Z#NP2qZOD^_8TY)5|2*5%~+#&#rByJRNDVFTY
zfM|)N=@F*%mc-8+jir(av!Sg_5+nk=LQ+jHpgWQ;DOq$^ve6ardy>LGp{!EkPht2f
z$veBjRZHw?b5bK2qbJLKiG0nAn3@L?H_zaqnYNT5sBVzlIt!6TNx>A5CdnAZjvh+3
zQF!T*<SJd&&5{f`;EyF2!oamiR_bB>iR53Zlx&sk(85rgr22jIwM!D|Q>`5mr&aK*
zQ^H@5F+7zFmO-RTlK&@kK9fA6gN5CaR2x;(_eic$n5b8xX@g9kWHv3Z`y~!ks4^hg
zMIn{vl3%xh8<Zsf4<bX7<Tt?$OKLxZ`4Pz!_&s@4GIATE9+R9q1Cen_PdujZp!Ajp
zR3DOty#au|^xvHrgoE@7RoOX86>r<n=_I{F86an=$0l^TNPnh;%wg%h<3JpdMo~h=
zRhsc9yf`Xd76QMINe5_|;3jSG!_baPD``D+Lb{zwolZ(~cY?S}cjTeZLu#d5oToHk
zFO;2<*2sYKk|wS|-)ZT13he~WNZ+GZoVWBJQsW~{rK7yQ(&_OK^^@u-MRrztA_iXg
zON%E$GC(@~F8TtcpHjJ6kn}(YNU-!CtsO$7qd&mIQ0as)h@6v-(%l~+eNLH>^U_?p
z;4esB>99nk^z)6h6Nr)yOo82t(nI4g5iQkf;oBvtkxGnXq?4vXG*+4y1`;QY-Uy}f
z(!IN(CPDf#?LZQxzE`39vUCkad6T4kde|mQ|D}CfiZqsXvZ>Oi<&eB0ZH|JLtI~6n
z!%LG6yacnhbm?^3FkX|YK7r_U>EFk}Wk{z{yfRbzQzm9FORBsLazpAC4Bgq%Ro7tt
zrnEj626Lp$V^EVTeaR7hdD3qBgiXG59@SD8NbhfhvO;O&G{B3b(ex$!VyX8uz)Ph4
zG|jhcQhqJiQmLXDGG$V)A|T48r|aPGZRuSP%teKi^%E@Jkyg>_xl+3JAxu<BS5swL
zwRATn-)p4fw4uH)9ijgbcp&YfXGpE|SS>{Aq|50ATQB{T3eg*+S1H8TD1E097Mi3s
z=YIiwDE*7xsgI;@(fPM#>3#zmA4|1#9I8cn;6u#i6X~!2LTRhC<Rfrx(p5vy)-H|9
zgozI6%k-h6PAQAtCQqf0-+=BeX$>uzo=JbAmv^_cg4PZ_Qdg=}?3LEaFtR?WyN$B5
z{nBN8m>-ZXKME7irPI1FrGwIMuLCh8UHv8chNb%{H83J&Qy^ee`Wt-<X-s<Z0xXS7
zpG<+agR*4;^c|9gRsdix<4_XaLAI8@wC5<>eGtl=WN&EzaF(S|3erX9u)qeyVcE0|
zuzN&yGXyfOvS+LD8yuBA-V0BU$yU+Vyxe3zQHADl*&9v(o{+sd3*@A%bP@pWvaCap
z^pH(?88}bbHo72A$^N1ZftPH@Pavmdm+6%88ChF5IB!`>IN(0AH{YYWa$nhdwAAyH
zbxGjcS=rK$pvGUek*e$hWN$8m?m*cmlr#yFb(X?luxw-+NQms8ET{>U%}YUFm@L@=
zfN<GMdtv^ZY!`+7BV>xlAd#}=TVOs)_H{J4i?VpCGmDnFBfNyaHI-f42=g(r-^C!Y
zve|NU#>r+=Rw`arM%k<cS@95niL%*N%+qDryw5?BWY2EE-(=ZO6kSM>U3G;QsWK<3
zZnz?wl?*LcWhQr!G+7)Smra-X--m^3vRxD}ye{J_Kx`SZz%S65Df@9cNS5s2AHd&`
z>E$qyElY5O(wj1`57Cz+yH^5Bxv~xP^vaXvY=%g_Y-1|`1+u~uaHdeU<^v40NVZIm
zNhp^2b-+Z4>?AFjZppZLaHdqYZx@DCCJX!pedRV;A>H@4Witz4sX{is1)_IkwHG0C
zSGJShzV~F`FM!fY+1N`Esgk|15+e6y`!r~LAp0N&N^4~~RMJu>%crDPy=;>ijSaG}
zWgv~RN3X&{lWg@H(D_it$_4z9Y$b(vn`Jf!T3tPsdCmv0MRp_sKkO5ktOZ=FZ0$=J
zTAOUeG>~@L+H+9TA)8I>&Q95!PUwCrYxx?0E?LN5(EUudQUTH}Ydr$Ddt|ZS0@o``
zIR~y!_VH#+P`|93g02Iy%oLb?E<0tbM(d#LcM6pZ$yWV_)?wKaArK=nRX@f%DjTEP
zjxpJ{Q(=BwcJvAi9+ZFgHrziX|B=>z_VOLH6L*lW`wVV7%I|r>H7B_zh0&emLv-}Y
zMSg_dBZuYnpMV^Z?_COjtNa5e+S?tK=jTG^xV(chnJ46Vf53~A^4?V7-Q^0Zy!DVT
zrm93wc?-oFPRT>&VrX9SjXK~?%hyn8)*1P)IdIfl?oJn}k36g!CVb_gG*CbJdU^|=
zl?T+L&tLxPc>sds2{-9)y@TcRr7#g952Un1sQfzBw}r_UQ*a_&KC=VloP6~?_#Gi1
zYy>$kpOFD=7v%RS9v3OkqVon(@|Bk%c~Sm25hPk38jrq9^4~ddG)BHH3I=24Fa8MC
zaq=@<co8ojL%|0A)=ggiIb;&$UUbb}mY1J^GfDCtO&D6T{96qgQ{(}Z1y7Zqp-P@B
z@>x$|@Txp!CA6i<=TdMZT|Vz0n7Af?`D2J&m(Q*PE<@gS3L=^Ey>wY+$)o6Fr8ndO
zw7SZcYZju>c2mxvWOj~x3RNEF%0Hp1(>%F>jydJa4_<}R0(sOLAPVJw&<3hVzTh|X
z70b2n!bFMOb0Pe_CAVLUF_p;;cVMDi{@tq}x8-ZTL|=t`RwyLz$aO*(yemKRCnWF5
z>nZ0_X_L1#LR*!58pUR+<-gDb*T|Ej!QGb+(n9Qk{4)a9$`@0Dy-wanS3<pfi~=7`
z^0SnyeJGdKK=P41T93wN`9EcVKbCvbN5Wg=Tj-(tM826GBCT>EU6yU~oCvtqF1O8P
zV%Qz>Z>e;sQ!W>Sdy4BBGF|c(3$#6x&sq#^-SQf`5PRe@3%Fi+_rK8HCx1l+T)(^}
z9)JOP0>wC<%P-Iecn0N*H0T?W@1$tPu-wxL%0}duuY-)r4dpO2Cf{tk1NX<}&ZSU#
zP;uJ`7Y`|tY0G1;D58algF?oEh@&EhmPbyCLu@E@R=h&r{&i8Dr|8XLMHC%#I-+Q&
z1c9r9@!!W;6*IqriDQb(RHf>s2$%$s<BHes0DeNToU+g-6*E`R`qNz@Gr=hjMbkBi
zdMdUjft*r&PODij#SPj5oK`fw0P|-QOX&sVtq9Kp-bXR%V{pC-f7;IYDPE_%$XUgX
zVf6VcmeC2W07Wnr7X~Wa+94UF*h;bTU_~dz@j?_IE_)64U#Q{@s%Z{WWWR{ca79BV
zX78LL{dbTEg_<@7=M`FeATB5>oj@WL8=U}%QXHpU`b9-^5^&LqgI{2TmlPr8;9?Z1
z*Fa(w=6;C8DLm*)&+&@Yw=nty#VooT6BT;g@Az9OMXeNUlA@4;$H|I4g&--4_)geO
zRoGEE;T6Tnc@Vj(xK3$~G{px2FrTj2`~xJfDK^t1^t$5E8UQjBt25w5rlKPZ-e)QD
z=~}(1SbP!A<R}_`MPsgF1(jdrDLPC5*zy%O6VO?paG8LKDpWY;ptDF(UXRXV#cx;8
zSE9IB4okNbmt!GPs&J!yTbbh84Ol8yh+YTawj#9(q(ag6AzZtoSX>OiUB%mT;O{-f
zre**t6_=&>VX73Xe#Gxutq^{Iz8ah2m7P#?UvY}|=MNM=ZAWLV;s;tj*C~D<0<d1O
zKn-Ua6b-YXv{7-2_ESv?7da#!Dm-4t2p=iD`T=iNl+o?*Si#u=XId0{--7o~6gjaV
ztqRRJbhas8rkGi~V&#ALox+yy3pJgJmzDzYRPjHGgmoz@e}J}UiYmI2x)p;IwC+*7
zOfULgh4x)&>r>1>1Fm0T{tE^N6ccH4_FRz|htUrzhUqBNkYe%*C>vHZQjmN^p`-oZ
zs3L`)0%MBhV(1)K_}YF3@SyVXd?-Dne3fzw_R66N;2e~L^i4lU<zi2G=%k!a8&zlJ
zLfQknDDw`%#9`%HdhH)k{`5T>U6ltOpz)}ZPwSIo%8g3^cT<+rZsWLe86Czsp?qO4
z8c!;>dBCi@^0~JS?t3V=(a~j3<zFoP6sMFYROmdd)Gxy|dq$aMhTq=GEp&7FC>;gR
z?W^pj`fxvG_D^U$t8}4aEPrKH1jZDgJWenAK;?=tSPD`uZU+~vjHC*!5T(BXBB9Dc
zD%%QEe(gYc&2VKS4=$cl=29VFgz_w{U(YN5wTCkolv!>VcBHadgT5%`RN9wZR7&Ys
zO0@FTspz|;9HN|djB<(wT4I%M;czWZIkFZe;+4!*=u1$_Ho$J8@>2@1URJ6o<ej9v
z_9{ifl9j*GQ$9uMpM}m;C7<ePuP7t_f|{$!w;~~$rktTfU%GNB?Zd7q`ze-tUFk;4
z<_zU*8fd06k}9UMl<rgD#SLZPR{&%y_o?CUO=SiJcyg4<6pqhT2D1RjQ$|sk*jAu?
zo&FlEP?_eB)*|HsN>LXp*S7*uqFg|Go?FVIbQmmEx=n#IWl9EB8I&uRiQwpMWhVVF
z70RY{uzN?j<2k0}uJQxA^zJDK=$%}t^j?m>D&-LE&#RTbv}>+WGA^R=zD*fO0jdYe
zK`#JnmF1sc*mcS<3Zd020}jDpgVJ7zVK*u#jse)Dyg{GjeW={A27Ql|9<*m^R(?-O
zxyQ;(s+(+4CN2j2iSnH;m}pgQqf)0f<rYdgwJZ6vV5mcxK#}iGrOl6i*r&>}Utpq3
zS$+~jd!|&Xp{83ILDzbZGW|Au>Q%n)3q+stn|1*Dl|jX@JD|Kd56(PSuHBBlLFJ#6
z*dJ2<N{jbl<t<t~j3~`s@M2UM?hc(}N>eLD#+6f6!QX?b6x&vKb4b;d3gW1m;}1`r
zRLetQ&{?(j4-glXKc%G(tFC?yazy1z+elYcH&vh?RUPdDIi}+I!EHCykN*RAT=g+U
z$xf(#qkZ;CRSoR{+*Mb6AmX7aJ%L6~l^w0>PO08yQ6$Vu^?+Vyr&XVLL*|U?5q<W>
zTh&WjCm)qz93sA|6<DlI_EY&#7V)gAhgQM<sxUY71*m?ZB~YL$atwVzsu;?q1*;|{
zgM_G--GH)C)$c!JF2YpnR3PE1c@+LRr>dDqb*&Mqxjf*{t2Vg6w+pI)jUbV#nNpA_
z6)OprE~&QcfSMT9yBjdVSk*Kw8sk(_QW~%N^EY^rpxSPRzlkcnAIN1@1r?zrsa$S@
zB&*8lB1=)_T!c@lsw#T;T~WPtls+qdRaI=j45g_)rkPDweL4V3*HnXZ0lcmXPK53Z
zm1;8@GgUX~PR~+(L1n-<R6Yg3WvgQ7n|?P{%m&PQj_TouFp;aWP;x9!_4ZM4`Kmu6
z054F5(J`1pm68f_id2d{5U~}jX3^DBqWY9J(YI8!m!YOqm3{`DWh%cW7%W%qz6|$o
zt4fQ|SfRR0&%isX6_mEWt6C~R-#yj;C>m3#+D|X1DwX{-aMdb1%8J#fz8i<#`>Gu)
zpzMJvno<+Bs!tQ4tZuDp;3N?BDksY8HmKH3flQ<7@z-c<QoTg`zlW-y*1^Ohl{+ON
zTU0YfAo)b)^cSY9RW-2!YT8sg5<uEjB_}~TR6n2D^!kJkZBrfs*P|K~!hEkPy$*eS
zs?v|~6ZWgVpkmhnRV|gGJy)sHp>t66=Q4;4sa~87)x)YmT4#@_;zFQhRJDhGkTKQP
zbo7m@La0*lpt^(dNr%+$Gckqs>PVVq2leLHF)@znowj5Eoz!}ob!WAIGdLIZi$hRz
zSp7MzPmZXW5}0sR^O<Nos&1o-mSgHNH;md%-S`%CA6Flth4KmY=d^V4R{vHEyFO|O
z3&dBw`8p*1)az)!cvjs-N4EUc(Ug!0P<Je$dn-`=*=aZxq;3j@?qIcrva}&;#dY+B
zs%t527^ZHY0Nvs0AX>nkQ%`h9Uxd0j9-}y~4y2mm3+m~#M~YMrwZWMv^+peni)wu+
z8l%<6C_sBjy?r?(W7O?`gT$&w6X}~7acX=G4EKn7CT+J9)T?Omkf@$al?<2Fm%?E_
zNj)rwNV0lw5J-x8cQHg#)h=r>&sWs_X)tkB{Q?&xO+7;I+jMp8ZkWHO{)xhJ*VQ?t
zXv|PQpoes(deUP^W~*ndrEg~3RByP4)*SUPt)6q$Tsq5_r*@`YZ@&6*D*6i4mpsr{
zsBWfof06ndT3eQ=`=~tOmijM>{*<cKlq)JzPo*<_<!XI9Ox#vaqU~;l+Mep3?x_D=
z3AgX6M=7>)Prc|XjKx-|E?NjgmD-M$`_<}{%ebm*)Ung?8{Ai?P(@mudL2D_>(w{t
zAY-F?Nj>mQYM*0p=Ak-i7$T3<J^dif>OUx$^H^PW6Ixo-FVi{ZC+e*cP~ED2@E#_i
zO}+9VoM~6b(*Qec>Xt&tbgI(@=zOaF<0Wui>N)hhc&7ev95UVNYjg$osO6u6>s4=~
zGdX?g(Yf%jU+qJOBnQ+PFTvn*HJ5IqLG>^Nn1<9BhX5E>|IrCYN7O?U>KIjjL|+CP
zQ%BgKb6jm(M9G0en!``fX|MUG0GxwHLa{z)&HP-5x@Z)|7}{aYN?J=F(FiDD<Eru9
z2}?&cne?5A<C+OnPj^D|8KvD%YG!&vnWrXg3w%1I>3a+jFAYZr?zCoxD=eJROn)2Z
zy){4Ee!!IaXqGR6317`wy1e`}i++LMXEhVvgi?Ra>IJ|DXr|wVNT9}-GIc>3|5M<C
zHAkp+Ektu?0VG2;v$cSSY5w;bOoVHEXF~NkO#_8pBQ(MEf<CWl`3}l1XnHQge5A&|
zg=Qg2^DqPCqGsVGXp7do9RS^zH1G8TAEUXk6wbtIhQEZGIE_2qsqva`C=r{WDToJ`
zsQJSgb}wtHUI9tc{P_gRk~P7Tp)5u7*QfZkQZ?qk;o%ic0mb33YF1J3Hceyy1${2-
zx@Ic{7c(>;(ZVrP^TRxt&(hpq2XaF*(+Z{8n&AX+H#NP_F!~%#PCazzYNk?(Ay4za
zW{Bi#uF<lpK(msT8HJh?Cqard*A}9&Sfk+sUZUAs1iQC1N(x<<YJRh$+(MbAVlM_$
zt_k*q?%Nvv2y|Cy*4ksf?r0pt0KBW|I}ff(6GAnO)tWc<LZn91Ps^M8nrBoC^FZ?!
zJ??5X>7PTSPIKisOw?;$rBeqDnm=cQd#Kq-Rg8}`-(SKcG;4<9&}e(A*{}q<yEKEZ
zfIQP+KY@!}Bco(%pXOb9*!OE}eDn=yUY?A`=bBb}3l3@|JlGx4gj2=*sOG#BWK6?0
z0&qzCR~ANZuPu@S;Giv{RI#JhG827H+S*-E=B)i<5Zp<dcDfE~+_f*$m*+gRZ!U&;
zPwk;T_<c%S_8NXXFYRK=U!T_AQ^W2VEsG7Hw^l?m>!W>F2}xh=vO6&Er}d?s?OAOm
zZFl{(&)xwSpgl@c8KiA$L1VC1b05D!h_;mC7ol3)9;#0W(<X9YB3yfyo;T;Up@q<P
zL7P~HzDO;X;>%Im`!g_@i&_bVjiR*z6LeqFDw{F1811BafX8ZA)7MYpwEHMS9<P0o
zw)Y8IHwCyv?Hl``<+65{6GW1<l~fj<tmWFM04qhSV8HHGZ4|1QCtuS(s0Mdk+x;y_
zhBj&i8Z)&S`@v;txi4Y#H?#{*gJf$zr1Jlp+6p0*=4eZn!>3%W{Cza$X>a<%(R}UI
zdyp*9?xLk_p*A!hjuvTu+5teZcC$C-7D}{bYe8;lUvPt^Qf-74T$whg5%_X#m>ckS
zwEOcw9%%oe1$M1APYO$QT3;$2sMpH!F^C3ja3A1}S`!P654B5@K^|$t=K#>GjVBKu
zYoj<&-J<<sDaaG;i39ZhYt{Zj%Z)aztOke<?Yoo*=+tT=;P6xJFSOe4((b0Ye5Tzv
z2yNZkN+$q%w6hwZv{xGv0@wPqUcun{weQn%dq7)s7LzcjjiNhlNV|Yu62sb_%jg@?
zHhu+vN40DT#Wu&Z!SwyEac##Lkb}Buv`9OoD=xz5?R9_u0K9|lcp`v~I@Vz{I_Z|J
zfQYlMqYFx1bhj>G*oSoybd?>^1y@4SRaYekIj&1v4=+yYhTevU?z*sVF+dMpQY893
zb@KvX&vr@|Md4;Ioexzjc<Y`|#O>gtdzIdizB<!R==Respd)H$b)A&Y^4I163lgAv
z`(1busAEk+Uy$y?9&jPL7K+S<>ONkEc?#1_%Y@x<U6K<-&gl;9hoK1F=tMYrURUc1
z3m0s<u2zUf>UIReZj>%W48%p<wKt$9T35FbBt~bYEOD%EC<t7fZrTN?iPzn^45bM=
zK5d6C>-IguTqNm!SO_jz_wXT<rRe5Afk>+ELkihl(Y4INSgz_mZiBsaT@WRbuIX&i
zR8V_ex7iVFhR%b&u9K-Nq!09E=^9<pcS9HM0i}65(Ko>7>-NykRG@pGvYv%HF-0|s
zbVernN_0CY<Zw&Zz5vQfb>r>myREBt2fRYJh025O=o%@Ab63|#d#rmpk!>8nD&6AS
zuv@LGqrH2L?xqlGYIPsdpNZ7z_Wg~))awG?2ckijOu@QForb<7*rW?u3&2C&M^TV$
z)@{pz<YQgmMi^|-y*~?*PjvPaRB6>E)1tji_n30U?YcE|L3HTi_EXJxr>-vvYM$w&
z51_PL*YO-`dUSValhms-yFz!L?r|&n`gQ-%Cg-_s17)`cbsw#P?jhZwwGbKB+3!Z<
zh;ID>OwhQ_ZWiDN^}_!)ulh-!qS0O-W)Ghn^zYF#+fiQ-KvhQ0`nlghsf+$-3&>&p
z-s$k|h+az}3s?PMEkxb)?t^gjxPBhx$WQ1GQ{nMReM2=w-1XU%rSi}p<H4Y({(DN9
zoze%q0Le4@l|#_!t)E1Nd_MYA+Vc47uhI6+PhbBI-GBc2=g~j}=+o;!0`+dmAi?@r
z3jc)YC({ByRNr<9K85MijzDR+{@i@v&*?eeVb;#;KcEvu7xW=iRUE08?m=Ue{sTIA
za#8R3C2-OD*<835qo4jMyol9%lCn7cDOyz8;`QECw3nctPV<$dPfQ0%);penniM^g
zi3v{C+eqY!{_Jw#uj<c`-8B8S5O|obzn21XP5*N)+`g{YeG0o7`reP=Q>Om!Tkt7M
zucTGS4SnPzsLs~!m;iE9Kj%C2<=FIpZGnkg{qB0G$=8>>2B!-2jr5Ba>c2I?(<1#9
z+9wz5zv_jW68(y5^xe`k6M-+)Z?geVrhlJ;D&_iSs+Yd4Ur#~U3jN8g(0NC{ke1|k
z^{-QI;GTZp-{30sn`v89rMGp^Myy&N@jKMi=+7U7`}g$%Z;%K2AwJ&8b^2s_JJjp9
z-@@n{^gF*rU!#5{B~hC6^H##rLw&$An17@%^+R8?-i1O3kM+GSFwvqn>p-69|DaN-
zR{b}WerVI*Oaq`@f9L1d!FK4U4S;m&?{h$&>ID=!=+ZCs!eF}fKhgn*9{tz!lIhjg
z{DHm!{nxbDdaj>HXAcMUKTzrXkbZ&)BOKO0T@J|+Ju?-vHmXmgFy@%P_>5)#gqb$4
zKhS7z;5EZT2ZKM|X^w`e$x!BGh|{6b*-%F%5H5ySD5ZGV(3Xk5BZhyh@Ws^-MMvU}
z8or|S?lD8jH<$xA!=j0hJZ?BO4a!a!PS95Aq+#NA0Nf2{DS+-_=%7%nr{NvjKLDOG
zi0IUUm*Lnu(0$tAN(Z0M7~ZBI+uPvZ2QPdKH!0WaYdBA<Za>3%`q0o>!`DAz*8B~f
zJm?NEJPw3NpuwI2gF%KBe2`GXe0n8^8SKA=&TzvzH7uMnxKIoz!r;N8J<oZ=r>{Wf
zg5ewb%_9xG<?uVo@ZCx@MjO)T8FtC=`)!aILor3L6AYW<U^mfl<Yzc@+2DN^T9OQD
z3^<x>i1`b+6vO&5^raeprCt6N!#8xk{Hmd~0Fr5j@lPO`ZkV)-ii)opX8MD@ZrI_B
z&J2T36$X=O*j57*S%w2TOw<j-lXI|}ZFsT)<ffr)K7NrL!^;H7HI#}0&ok`mhllwF
z`DKs-L(3=7QfRnCmt2v-yBl1wA-oZQ5<^cMT)Sm>1+PCG5i@-9E2gc?(6I_K<%Tr}
zz}+@v((F|j-v1c*JBGcqHoa>&8xC^M5Jg-6N`pUDELIs3+0a&Pc;zOz8pD)0ICJ0d
z-v2P{2Zq^PG}an$v;_B!;nZDNs5h+HguVuYR)+!F8V#xgkZCgf@G5+JXegco-H!~P
zQNXg<fD$&`I0o|`h_)CGr-6H7*p!D!Xf+(97*d<zdm|*<4R`iIONW8e4u3lhk@Qx0
zYB={540aj(C1`wRc;z*?)@`^*YnC2E+)XI!wHdb1vAI6OTU49eZ|Il`H3NoOS{NKM
zNL%5|u;C#s1x5^i=7NkGW_3c_n89HqaN~w=R>Q<WV*`B;>X6Zmjt1Bp59#2cgHcB*
zV@Kn!^n7wMmd^#}Z2Vy#+;%aV9UytwXk$~_@rd!ALbSRXmn;Hz)VPppkB%85=wm=`
z#z4ASjvMQL0^)>`<p3{E8uxX=LwDnErLgN^JpVR`r}5uJNS-o=M`MIu#(9)9J#9>-
zx5*h}6n$X9+qmaL49UmnL+>qL<L|Z)AmeX*;s{GYM)MZ51{+t?Vm8F+N`K=KYE;tV
zF3i|SYvFL?zv&?7jBnG^F2eXN)!CdkZkqz77mQmdog8WOp+HTP@roS&UNolB?Hg@e
za~E!3GI|)HEXEk*1$eA+&PQ~pCeFBV0@!$C(f5!^FlN*CG10i0(z=(8Q|YarWPJHk
zG$tGG(?dSRc)}HpsYZYL_RAIHF@N}b)#%OxAkA1X16;as4~0#y8IKEryKao1h{g=#
zdOEX_X$)S0#w=q>E2UCy7*#KzGuz0aQmvcDO%!|1G1k&!J=a*d3l8TQ4eK$`e53mp
zz!w<z%)$r@jit0FEHW-R36Wysf%^cI7(4PX&$o<|EFh)E-;YCenKAYsxK?f)3<Th|
zQA@GV3gZn49TB@@oHYTRca7n+zQ1SOYXq>;m_$YLRmO~J;H!;Y&KPfvaoMlvt2ZvC
zeP5&TH3}&;8Ru1_@1b!%y^S6jduadFY^-`2++*WDS_ZZlQ@3DbPmG)11!*;I`U!K`
zWn9z^e{J2ys@0%9MiT|XdyV@_fgdpLzY7!3jfoWX9W(~hiekuEOjSz5#xrLjGGg3K
zWrd?geKz{WjI(J;J#K8H?e0O-zceL>OyS$1+TK)3!3hUbCaoPDO)(##(a980i$-Ug
z>EZ~ei|G+nqZ~Flvf%I$lZ3VxuBMeX4DG0C7bTaEnW8js#?ACAeO>CfDRn9UCrss^
zz~D*K%7bWhH`Ofzz{A9(3&PV>O$p#rrp+Iq(aZEMZGcXjswum4#?)nnGu|fKACBns
zG1byJ7+=#a8k(PJqdj~&Ys!v+L4VUSC3FXvqDW1kDR?qOf=rM6&=_oL$pi^8RsRib
zp{9fX?J`V$UxN!bl_y|E&zT;+0g(t({hMe!Z))2L)fY^|n=sBu(^Q)$Xq4%FGaSBX
zN~CiZ(WWox=*cBh2Ho2+rUmo`j98QVIpE_=`|Z&fZ+bKjN)t?1rh`i~`DUQ+vgzmn
za7iYAighQOzNI8@is}AW@FLYTS_v&zOnJvJ30F-o|98aF)c)V+#;%(@PM|ZxG)D(D
znWi~*AXz5fVT}HUX<a^i$~N`UuKA`ZW<UCJO#34-id@s)Xo%#Q7$2iC-!x%98VgKC
zG4P_$#6F0T6`5kF@V?lTeg_sxOiMPv?OUeBa!8h%Hf^BqXqTA+>7yX!CWSwIyKQQu
zL{fz*aupDFOp9KI-MglYnNV}jwEJ_AO4C6)vs+~v4ueRw$*CDiYfKC1c*cFxJX)hY
zFnwT;zFJcO9f+zkCA|)x>P-)RhDd{{bpU;hCMTpjY?GTz%^5KG(A3`sna8GfT86fm
z(ixC>VtNZV=j2vX8pVm*O!1o_(r$8~lw^mg<qL3~rmO29^3=r0#awim?pJ|(W=j4Y
zT(>FbAS8QC$Eg;k*TlXHK%eRGU+C*Mz5M}n+6GJ>^o614CXeM19W+&tr$Z*)1T+qt
z<}ZWji0N1gl#ZGv(>89*w34<p<0dUFf)AQEGoj{?*|7wT_GbASa1LfmDJI|1tXl&u
zPUbz`(Bf>a42Ksk=G-DQ9yV*oK#thVtZ*oGHOCbLanwAU;<d-jFJ6NhH*-FfFdR3}
z-30E0dBF_ePnx~sVaeTmi6Yq^W&_1-Jk9m<(0IzMd>NdV`E@05r_CD|L8rHQM=9Vw
z=8aasea%C(pz$;RN*m0xX503wp#J9N^okBJU)qe$K=b}bKm?f|Q<gT^{5nl(h<Swe
zqM_!4U1$t5|3KlfaPw!BWIAWA_!%U^{2F~N;=DQ386p?Vfi(bJH2Zu5yV2%IZy35{
zK9K?sW6TM55Q#OvWcvu6apu?B;C{T>-W5}tVBSDwV2S2e2%l`e>;Yhk*|Q9TNj1lf
zKr+qz3+*D)&419hd9InS@zHnPETro=!(8P9F4O!|I^bF6FP)+DhWYso^ktj1^kJ5p
z<^ww*l4DLfO^0f7&E^J-KF|CEJ=gQijf)^!U{+IIL!sH>DM*p|S2|}@Z2o{&^d;t3
zo8ZMQb1;2~t<-#34_ujfFTGpK%}Xd+b=zETf!zvoLLaz0=A(2->#n(W7{k72-f9oY
zN^`}(^ofuvb8IZwYV*YBkf|~2{{gvgo)ip&56sz*Kx)nJzkzwGGgr`VuHGyihusGA
zq$9vJnt#qiW0QHd5wrHtyubnEk@=E4%r~18ya0b}X1@on#r!>$(mgQ?X`HR*xA>IG
zY%_ne00!I5tEjB0!@TqgM%Za?pAW=SbH{E>Vwbt_Z;)r^FX#!=ZGM3Z^F8MF&mh@r
zel-Sj(Py4dVUT|FZ~p){V4md;yU)#Aj{rAl=1^2{$n0?mhK9{wJD_jG97-3dZPfe|
zr54A`owUaqH#@k&w}X~f>0F0{<@9p^9W5@mL7Xfb>C4j27UOS_bg^un1#;N(=R%DB
zh~@NUXmhpLQHAzVOA$Tij#<|Af^)M7)KGTZBH*I&gr$xaStl(U-vM#ASuU5N)x$Dh
z1yN6nZ!b)ovN+AgujXY5roiQCiyJNZ&RD*uXOXw1E)9}C7S<_nzLo-d6#7}ZuA}j+
zrC}0q{+6F;e;r_%PWNV@Wf8sVf-EJJR}Hp!Z-hvQ<@)>38EUbK6Jb8gl16t`xMiRR
zO3zu8l*5Uz6w*@Wyye(95Em>4NAz8^9HK9)L|eW*i<!M-u~Bp{#&U!*Zn2g!Z-~TM
z@`W%TZ^@^uXM*LOZg7bf=I5A%B#R^jjmZ|vNw}6`X}4_!Fx8Su#jjT^70tk>S+0J8
z#&pYAH4xV<Q}ST`y5-@w=*zGyE(9>svYVn#*_L^fH@s=tR0pLwmRoeTJJ+%`9$cO!
zgetxAEtCJdn=JRY!0kfI#^2#@k)>r1MpkTbO0@xBVu{wm#aosl3xK7Tg>)a3S!_}u
z$}PoRP;=XoMxoUT%fX4Td&lxaIJmnO&$r>)Jxj!Pz$-1UQz34ZrIAj8R9ga9Ls^X_
z_Ivc*x11OP?tx`CWqWEZ52$dl&XV&QeTJakGK<b>G+2VplzomJ`D6NYVv8m7KI}fR
zWYz-FYAI&HV4LL_1s>ZiiIi{buq1H6by|LGfZeASJIc6qS)6IV`pn{5f`N8ha;IV{
z`z)_tfk?mQ<U=SMu-Ma``rH!A1ANfZMWY_FT%hmb4qKkuLNNLfOBp5jM=iUT12|@3
z(HHi{E!!xTbkN#6ADq4Q{tOs&uqMBUK{#3?gz(A9TCfWMXX`~zm~gSW#lpl%>#U6+
z?$((fLBzxQ*G`CdTH_mG@RT*93Ff`5V^kIFZGGBIPedQ<_K86FTF+#|89(cqRWNwg
z`s?oy^|yW|1Q%dkOiBDet7ShLgRDC#wHR#OOK<-WD`yZ~sC5HX;D%XEbhaSex_JbR
z=d8ym6%%W%qkMgwHOT-A3Dzm?7)zqH&6g5jm#ucRdrq=Wu>(oAw$WGNQmp6qK{VAm
zxDZOOSQm6)6j!Z_DH4`uwU38Lx;3{IO0QX?ED*VFo%Sx2W?27u6Ox(Mxg9W{Wp(*4
zUt#6aE+gBzXA-95rZt(?9y!*ks3~|N=33`00-I;GC%gI9IWJ&L1y;ow;0vuQo&r&1
z<;25ov9)*xbeCAYD4~1Hs-Z1>sdefW=q|I){}`m)s+|ZgZd;GjQ?|ld{|exDtVYUl
z-L=jjXYN`1)}pb}x|4P{wkqpKW{6f>KV+k|#`+OOc5AH{X+2kGO_+_wdTU`MNQ1Ti
zD)5cg&-~$9ll86lKptA3KS1Ln>mkaNH(RG4L*rvB{tz2iwRIBhsGnGuQC_IknxX+|
zvo^hgzIN;G9Q-gHHtRb21VyLyH43yowJxI?$1ZE@WN3S4U9=Tkw>4dYtFy=YJP{(j
zR>?S&_E}$~m2SWFb=uz#SaZYC_uTrz*T4;0C$a$;vNp6~N`|fP(57L;TI&t-qt<mx
z(KlwbqfNuO)fP-w;6b|<s=7O5$GQ&A-p(-uG7fghlx1?XlSHD?$u5$rNu2F^={4wL
zx4Q_9u6BRF1@5RFqZ3{nvwO`2I5)fOY~YUDEvFLa6Ly2NO+RV3_yG*M+m%uD)Why`
z+Oc`s)!GgNamwz%Hne)#RZ{iZX}c&gf5z^|r7+=bS4X7`K6YL^Fc@Du*+caC+4ZPF
z&f2}U1Sb6LmXrY=V3*8*WT4#uW%`2b)c@tE?QYzFNQm7VUqV@^U3v|0VRmB_q71kD
zb%G7-IlH&-!r=(JW9Kp5=k2=6(0IY_DaC{$?cyk79%Uz9i^hv~o&Um%XuCRkXkN0*
zd>6l6jNRNy=#I5paTn&}?4l_<6>pby8I1{cvrmI0+FhjG>t(xUO6VlnHPVhC*-oXV
z`!B_gHwTDRJ3DH<V)xqrIl9iUs*WaXjA&w_i7nN{G}As~Vl<{}s-~DkxxM$^uO%@t
zUWy{p6cOnlQUz3$B1MWKRS*;fl_E$HK|tvU==V;3&9l2R@67H!XUoj&xgWr`T<7VO
zHgLvyHf_@KoGYm_`OaNz3|oQoR!Xlebk5Vmn6u7qbk*~m^EYomeUbA7ZFtW+S5TsL
zvGdY5fKuYz{3lRKon1n}Qsz9}hElon&bzaxz2j8je7O;57o3wf0K3vz^WXQCoOjap
zxyIRxd~dbRZ9%RpF<HO-BjoFySJFMsYtG9lpnKi<IV0q5IA5HBQiF5GX{c{>{+_&<
zP0lM81G?GyqY1Fwbe>PMM~kx$B^I<gU!{biTh7tR;B0e_rU-qzbHjU3+u^+FPgvjS
ztf8U2?VRxvI^X5&=D3359p|k(A<^wT?*d4Va~o~8?mEAB2fs+K^NK5g>2r3Tfl|No
zB6?%)InUn?P4}H2h*3G<JnIKoIOzO6%`-#JGwwmtuya2BzwC(f3wbDwI$xL$E5@9c
zk(YVg`3)`P9yq`HDLJSnoGZvxIqCcp129w0zmePMq4UfsSn<gDb2^2(FiuhClq<uv
z4|cmTT*+s>n~}8&rg<<te+1dX5bpq|CnN3w+V(PR<WBTrT;-wCm%&~Fy?zWEIT!aa
zRzDAc1B_{xC|Vl8cyBdW4>DHCF{FWv%XMfx#5no|Sc4cT*U=WrSVKG9Fh=-$XbWff
zQBGzAV?Q|_BN;uEZ4kv^;`0qohZ)5~;EZO}(tU>`j08kvoMITC)5{pkxaf{<$1%MB
z0!ut2LQUBU35-AHpf-`w@DE^)GDax_H;M6s6ho5CIPd~kQy3p@fceK5uJnbK;|wjm
zR3{h-bTKNGvFuY+o@AU{3x%f`uf~C-F`n&%G3g916G#SQ)^a>#nT)0M6P{)i)4G|(
z2qhnsBb%WP1Wyjbg?4ATj3DxhpJB|PEqNZ}3?&lgGd^2_$^yoF&p@J(@!Ud?vyATw
zVDC9bfDWXHafD`%^Neq34l8Cneg>5#jKtSqS}9}co9I#*<2x=$Im3xQ+*85WyBiuV
zI2cd-cg$yWPC<PY!<Dj>E;6Rm>rl<`d=sS_#ytA4<|Rh<41iu{EW3@iTE@~ql&&zI
zp<T{Z#?z0ZYjq6ec~sUj*dIZ~H3q*OZPyvi<R`wt_==vu28QhkSkcJXPcM2C!?7e8
zcDFDzl%dwj@cj~vw;0R6fM6TrQ*u7HGvWg9%ylr5M=%zhjAs{NEN(MCr=OyWkx$rn
z7>QFr>1OP#h7~;whZzEQ869+#?q#gs2CzPcv=U(bjP>NgzQ<^!w6*(;ZI102uK~uK
zL6AYl7nGSZ#L)MkG|bo@2%Zr}J%!;$8NRd*jWI@OpFPg-ro8qCjH*y5oM5Qw4#gy+
zmQt;z7{T<cK4fGzqU{mm9Bp=7nBz{c$(4EO6>z#S_dSL-cji}_6fNDwe3KS}-OQKY
zfC>-hLOKiYVGceCG*4zCJxP0+DhoipnCfD*c{Bg{4mSBPSCL1{mwAs|V1CSZ<Dg<6
zGn^vb`<YqKLe8J*nu^i^=DSOvD1f<?oD&C`k>vCWWGbJa<KrP_@HDUnF>Q~aFqk>@
zH;f5k>gYre$}C(Bo5Gl{(<P*E<|nj_MKI-CP>N)xEdWat(?MzGhnc_9-!VlqceFy_
z2=hS(P-2*;DZ&@eJU|YN1ZE^<m?bj%X`7$S9J@;IUkcNI8F-E{1vCeyG99#-pJWcD
z!|qc|EqQ;_n3w1<na<omQ(6Y|Yx31+F*mG4FS41-$dQ-Bbb12{bD2`w=AU8O*P_39
z%tG4n<ue;8;iQ21KML>{GRJ9pJ<IGg!feMmX8KMTT*O@cBUsNfS5Ta%m}#W5Yzgy!
z<bW(?{zabMGG-bjQj{}|AA(dcRh^K(!2Fe-pi1U*`=GFj`4Pn}E;5(U*Ho*SF<a4A
z!weci?=LYcC!qH-Q}r>dsAaZphoM&-%+70QyvhuXfqWe^ki0nc%oJBNUSpc+7SVNP
z9UVb#FvFgLp$*K#WN0Jv`69?QG5aZi+{~1RfZSvb({t6roRxsKHfGXI2(&ZfXff<y
z=6wXPPUg4tUjnz84TZ3<i|P1~PC$2<`{~0L-ONA84cfyzPl3O?%;FDF>SZPdg7h(?
zzeCshnc`m|aF6**9qhf&ymk(H2bjHa&@{-5CCB3s^Uo#V9A=uRZG^djp3YIGIvBkl
zWBw(E_&BqZ@>?G;-*G%d;{>xV3FAD;bom%$is{7y_CuzF60lrZ<0D{oV=brL2X|H;
z3#NInzNb5Rdsy`XfO@j(k3wKC%e(^EUaXFBsP|^&ybW<5RvUd*!<V&|a<u$d?h8Qn
zvG)EC_U>nW`w4B9{8@kggyI2~zc+s709F{?mpI6Jp7xJ{Eahyp9b#qBRm33HyfTnr
zmWihD5LSgJNGQweQ&dK<Dk(A=$@)7Rm{F{6>47-R`j$>*(X2r7W*%X^_8U4F!+JXk
z7RIvni78tlj`bS3XyRFQE6~FP)@uvFlgRSA1DK<%HD97Ki8b>Z$S1Q*sURsVSK4?U
zV-3&-?l|it#Q{#R5F5bz!(#7)F(+9w4q#+Xv2rOXC5@$_?Rq-P<OY@uR(d_;GFjM1
z;r%<!dV&sqS*+n|)Mm5hP<C++Yrh+MpUXN$!LBo`RLbDZWBptVmV8#wJg6^VN$4n0
z$a;((<g={&B6Q*$YdK9DMXVb7Sj~CX-`|52v#!!fuY{H231doG>)KE%WBoY_Fh@B{
zHwo+tj29ZKSX^@3*07$TYjBrXN?aCmy3FdM6`+>2em4ZKu>SfJDz36jHdNNJ@@Tl~
zS=OIXd5zVw0HD`d@jsxgk!6^KKohIUiViljwo~x*Cd>14RJO2|kdLC(!8&#dthZP@
zDSFw)DyJY>JL{kmN*%04W$0)ZOGnGm9aa`?>$+Lf>1Xa`g{=hXV>yn)-hNgdO)Uc~
zF*)D|St0L%46*+F1}vkj-@Ac1#(HiMP{vth<TjdQy;6y`DVAf597PXV-zGwnD|>@G
z8r|5|D=^rd-8LH~5B4hBzV2c7okvGK*=08|q~7d)a$fnc1L>xZFWdSe6z*qlyb2V5
z_LU!@@Bmx?6WRjVrzpGd5c~Tz01IMor^z;yoln<h!`LFn55Nv*mr)2Riaj(7<S_el
zdUm4Oy<5Q=%kHGDbsYOJ1*zlNna`jXN7?fiLq3UpDH@f@>>nxF_Bh)(A7gQXJu4fg
zrLtF0P(6)(BNaBKv%9_mN(Q@L4S_6n_;YB>X7650;rkr+yt!!1W4r!$_-2nD2U-DJ
z*aH>k*r!gTRK%V{tlQ~4dmC-}O4-xNgI>mVj)yVj?9l(NHn6`~1NB$g-<*S79Xp9;
z`Fi$(OpL`f_LfA*U1$F<4J?i9W;xV0v7<hqo5;=V>Uv1rWOFDO(!#!CfWfWoh!<e#
zE%sy8D7CR4Y=x$F_O&aJ?_lprfcj2$;bD|+v!f_<b%(v_4ocl@`=8+KVLxGo-n;B%
zaw+w)*IoozKl>{gI&qJ^f>Ji_v(=BtSuns(?}fx5d%7QLhu9bXfZ!;5HThk~*ip}-
za-7{$4EaemJ0F}=?C?Y=e8`TaU8M`>#xPi1IcLa&;Ks>xg%$3cvp=J47v}?t6nbzL
z((<{7^F6Keo}9Po?%`feKY=;CIFFI@%bT;4yiY!y^`S7>m-D}skoV*4r<BKioTZ&0
z`#B4@K;EBo;S;bN;Jn0urU1@yDdY}vFl*pp<1py<-XYGxYtS3Sx$6lM%z2ESt`N?A
z5zG$d1bKinf^&?XnMemG_i=PIinEUb9!EGupMfWa^VKI1jOCmc!_ov!ya=F)oGoo=
zJIdKw2(%QA4_)>;#u-|Nt{vwzNYIIsoYfqdeToy<j<z&THpS60InPoa{%OuU0Z_6y
z3u*Sr<vc_FyfYj}(<w;gar!9TwUE=_0;A4yl&&!59EY<9T`T5%Q3dQ0j*i~@QjT~r
zILkQx^q=76oQb)ptl%Wm>wAGSmmcRz&gU;epo;Sp{SnJWP9~*>R&y5q46qtbwh2~T
z<{aFMwpz{?4$7*$!r4k$4_7(M1R!-BS0PyIIY%`RyvB)70P79TA@V9Va6Wz>@{OD!
zT0xpP4HV&M=8TaC?<S{~UZWOH0YxZVIWzx&F}FC|N72zXP8&@W?VNw9yB!>E6i64x
zX&D)OhojmC!ER2{Zgjhs^Sc>(`#9gzCZL~Fw;U?&aSqU~@IL43wIBl=p93&vkn;xJ
z;TYl^`V1<DIe%<M<p}3%%Fr3*2sI#MoQ=sK<D9eG(WM8R4<b;S;CwhAY9~293+PK6
zQ=Hfd*!Ga~%O#LUoU+a6nhSTyZm4(V<~{*XH}1O)XmjTlQ#@=J_c=OB?B;e*a)}4G
zo<?mCH~1BRdU9J|Mrkki)dX;Qaj!{Wp*MGV4g`F-|5DPPFE@oE^nP3=7Bz>{KJLp|
zXxz_jn2wJ6bD#VMCLZ7_S7S&6xDUtC--F!Y8b}0k?^4FfA?{!*V1l?mQ7|!>d+24T
z2;sI+1UQuY#~Ad6ad(n;FPxjV8v+qrFIvAMxfQ$6mnd!}y|;(Cn`@xf5zXE43mT7b
zukQe840kgfZDYABZ=f-b+rx+Ycy5meNCG!e1Qm%~9y#KVa^-#)^(5|KG!!OtL+C)0
z!kv5_rDNPYHpGu})6W9>1h@AiK&Nuo(mH>V8%TLvr?|1SfTTINuhEe!ox9~K8c%b#
zwxCa0-0%vJZ0@!y@Z@l7DZ?$7n?^CVGu%gHXdd_GOkn48&(m-faEICGQz2Jy7o2Cg
z9bvHd9Cv~ag+<(Vr6`@}nihbinA_V4loIZ)5r~&^U#X|WrZVm#a{ZNaPkjWm3T~4U
z#$4cL1|bglvg0;=)~AMBqlf$@Zdw)EE^{B9hNfEX3KP10g=?lG*H!L=DOA>RohW=*
z&rN#`rE6RnJp$Lc_h?9Na6hISqYd2Fr(shgm%9~KG;y5+puL6rVh~tbxtl4Zaf`cy
zF1WXGhaHsL($1~D4HX^S!xV<^<WBn*#@yz5kPEJh`{^dM-Qk|x1+;E%|7BG6aJO$k
z<y~$r1;u;0{?EgTKJFR{gZFdY_XFh~_t~{Txz9D#f^&cyeGq03a-XC-lSAB-{TP^G
zt}2X<h$CEH6eLEunx}y_#+^?WL&mvcii|$sK0_y&3GRs?v`um&10XoXjok&%hujzF
zy3`}?zB;hD@Dk`}a^=NmK-`V@Ed9LhysKUi*v0#SGH`eEex+;$51x84D);b~E}{s(
zC+`Jv#_r{9xB?Tsc<XmT-kX<vAM!rDhjozf<*m2{O@6#&N&(!*TgOG^ex6$-9sz$|
z=R9y8;PKa>6u^6aJ-T#|x3Ur}fxP#uz&ylbc|bgfS4Jn>U|ww@3=QGEjf^0NQz&n1
z2&@U?Jx{+uIB()KEREoGod8-Sj}14DQxq@#Zw%XE-anL@9nDKU1<)hB?`0^(@E+R1
z63dHR4id-9qZFig-tuoDp1_+Df+X>xD1j=O_c|q?rtpmPA*vI+WnZ8#j#OUzCouRV
zuYz`kS-jYL;K}8Uk#F-1?*s)=@_2jc0|xoLJ#=U&;Kly{Qpo#43DC2=TyhYf<K2~j
z6!Bi31yallehL<r@amd@S<0(D4e>Ib+h=Gi=lRZtcm;3xU#PEi@UlJyYZb5B1wFjT
zOL_qYS7V&PTEja<2dGQDvNIr;c{LkhcP+2^BszM9_f9D)ukx0#prVfVTsF|^c^mQ|
zca3-We^7XxcZr9-+~9qD4s8v*A!lf4<c;2g`X-(iC1^ME9B(fM+D+aoFM+3p*FFx=
zR^HTAJOa0PT1qKs<1HsAa650yS!n9uCD1OZllKLk8*lTb#{#B{r#b<FJ3PT3DBb08
zmjJVux3dVGeZ12nApN|{w_w^m-pE~m-RE_$L9YjRs~nVIFvxrPbMOrD0?CIq%=`2z
zDo1#E`ynyPbK{|Mj3?5eG|pSzgRVW`2?S6v!OQ*`m6N=0#!)%Ndz1u}hrI3>kViZ}
z5_jSA{)R&Q#mawsCVtyd=-tiF`w0Rb{5xM$G+___6#Xf<Cw~?BuJ`h1EJWA5_}e7t
zy*Iyq6Eyko11VnO%jd5J@#81zA-9kJfHHIT^CM@1`12oM4e<l~>6A<z!1tR8O$Yfs
z0kA%hzlhHKhxmQ#pf`wrbSDIY`QvQbqK5EC$rBLD=UoM87=I>ty~6pIN}wr%{{i{q
z5A)xq^tEXIuY1sTgui<N0&)D4o*?o37wE=70{?YN8A;;rDh5k3fBFH)rSOABpzs9W
za|o5G{G1Y$PV(=T!@_jF6+2^mtb^Y{TjNar;nh%)#eel@kZk@FYayS*-zb5KT>dw7
zA~?hM+yt0>{^?C<E8xp3P%7m6|BG&)<8L8vN)i9K4V>rsTKav9`A?IVu7qDqzg8Ll
zulcAf=YNy~dn@?ShoLs;)n6Zb(h+5X&_(|06=<mDH<$rf!<SOf?=pWT-G!;;%g>|j
z3g4R|rdRolQIzWV&gAQ@=Z~2He}lh70f7eobN(=^k^jH<@tZdBPm|7Oeli_YZt};w
zA<)9ly@j8)mH#GvoAVa`SqDw#-TZTWfcEg8BERZgej-H+dimk+LcWiWDIHHQ|7!|O
z-RIAwJ9h*8)-kjV@&CLD@lpOXy4N$tpG7B(asEFWVCVyW_e@|;@WZd6ZIZw28VsG{
z|Fab8AM&rzM=c)lLsaCaa1p%i4B{&IQ2;bI!9l9@5G<Guo;`vqdr;{q*i28zUcm-(
zKzRw=GUx#n?4;<Vk6_M+FveGq_9x{01gRw$gaCo-YLJ7174M>>fdX&(h{qv85=CKy
z1SxdYFjyd;LyJI&AQJ}`r%-{MLZxAXueJf^uwVi0RH6l8T#zFICK4E&Vg&C=L1G09
zyMY}iNTbbeyg+v!DiQ>pTR;*8ZvD`7Odz2E%5lNnWiai8AcP_ise(cu=shVIrj6(+
z!P;v2CyX?Ki2hnET_B|7<qW|G??7ReVB#&5vITdRgX9Qay#$51g6Mw$b4KtfrPJjJ
zD&?rm7if-xr9d!r9SREt*+T$3D_BWE{&RxfFVR*c2%QbiGJ%QQz~zD+@er>NY`Tr^
zIxYwzSD?R@f?*f%R0-U2VB1B3gmMh31%G@F&>F$SFwm|F@_qnXo#5J&5UdxhqV3)_
z!SyH6-|K=N@>|~!I6ee+gW${ph&SSsd+2?W;1i00-4c982eLLnNDsi;1&fXYtivJL
z(g)fp_=2AN+k)rDU`3ap>o1Ty0zV3jcMB$^P|+{=dOIrb39hFD^uFNZUZ@xlEF&-6
zpdfP+W)BIZw2>Vagi`kXh`@t##zqBGX;An;FntM16M{eP!1_tSH|rrVC2*Xlv)@C3
z`B(5f5(p`V<|6bb$E2%p`8M#l2{jwR;x7Er2<%<Ld<q-y7S5#18!zE6nJ9S+`JX_}
zN9ar|x3BP>BDDDl)lZ{K`-HwU@$DCO-hjRS!u&;0e?T~wGKzzQZ#pi6Cs^1<GgpZ4
zDM~R46}rVjB24%pWnza5dE|165VC0FA1R#W4`ZT)GyVchtT34#y*S~_tswEjBlPGc
z2xm$_5`|425I-susX&s17wNn8$-?3kfTajy=?cL~q5D1u%s3@<r&QTAVaiviO&9X%
zvTTOX@C_7Z3Qv)P;<Rv|5HMLn<pE%43%kf&e?}<z2Ug?>gQmgyeBr;efi4jKL$^Q*
zh3ZzIoE0uV50-Pn2oW?C2?u`xIWHV&gg~+I#&Yr#mI&8g1a_(L2HnS~6mBG!M3wL~
zeX!=Du;wesR|}&(U}%kS(@p5TBwYRy1TG6#M?poc@cAx)UK74fNtf4!_bGOMLwJka
z6%E4Ma&R^ZcZQ)8O~Oga0&EuMTOfB+$VBAB;nXhVlFPV5n4E>$PGMFFJ&3{>`rKBR
z@Z3d6+!6js`;Ttn{W@Ux2!G&%+!OA;jmP@FaQ#A<Js>>)1<0Uq9)%Ewghd?a9To<A
z!-^3hgZ2-j!g8869tbnduy;cE4j05RDRd?$#+1-V?z@M=cyGWw5;EzOxJR@+2P!;8
z&*VXVujuKOX!8>No(V&}MT7Kh8XwV8y20)%T2KtVej;r@IQNMn@}X(JsHg`ef6***
z%^eWMlFKJR)Q|zw4vLPE|2NPfDy~3dkZ4l_K!ZhlF90S))Im<(P|<oiMu&-}=#h^Q
zr7Q<aq-Z0hr$vdL;es<-wEZ5`9}(FU0F4oSK~CCOQ8QicjS~%1x_+W)IS+D2Md!Z8
z51J&}Mw`uKk=s8YDI&+4wU9U_a-(hAanX&JA#p;Kc@!j7^xLQC#VJt>Z5Pu-Tj};@
zx@h$(2xf@V>A;^U3i=%6v}p4yXv-EwQ_^yd$S(onxgwW~fIcG%Gy^(M#31iMzNklp
zVJ;9o`7DOAP-J$rq4BI}9&O^ziJHj8RwOd2FeK+i|BgYvSagM+=MvF;Is%r8uFnBW
zndlVxQ_DpkpMiLVXo`IC7eraJAXh26P8SQRM1QS^^%q5_*nqAUE&L2%HKH_H%WFmL
zkHC3F#Cn6mF;_(_y4F`Gs-Y*iUi2}ApRS3P|A=1P5RK8sut8KrX+({pZF9iVB%1mK
zEX^Vt2jr&cHM$AcD*B#|Qny4+pMbMX<S~U(hp6uiG<AyNwWz!;+C#3JF40evuX{%{
z{|0@rw_C)f?6@A0;al+ZiZ*=>y?rnd{p}a6q-pD(sFUW6`=U)=U>OvZ*8yfo<nl4d
zu;}L&u#AXy(if^mMPJf&&oPmWlJ_S>gGR_rimLZOZc0?w3i41?Dg${W@{Ol7XBYAQ
zuTgXrKamDY-Ne0DA>l4QIvb^3;sRRnc8i&%D0zql6ldEbKKB*`JjG@j{JrAk<TdmX
z?;wAww^&Ont&cdsgpu(Tzw|tapZKW>^ktv;A%&Fpi!WutY=80oO(2c~;@|Xu2@t<?
z8U`N}XRU;aK=Dm-xE&JzK{p43#JdczDOeo(4|*6P-ti847%DEh59}~;_&jiii#g;7
ziV)BE79>*a>jSwc@xTA=V8t5xK5Vo&q8b{Gh{Gr@7bA|MRVmgX{*)fpI5E$L9>$B;
zlB+pE>_N9blf;7Wp(0uQI33qg#1cw0JSP6h57@`WKhq)igqXVloT=h1YINqLxGo(i
zr^KPOyGs-2eGKSyvEBmC4Dm)f=VXeTC=z~J{2Zm|Wr-bLwB^ed+tM&>IpP`bfaHo-
zYQcI&{N5N~^2DX#sLU77C;w!D_$D3W3&ro?$8$O>KCXp|bK;*UQKLv)x&bWb#XHFD
zP%Qq6@?T5DNtEtUD*ln~4VQ^W=|cnMVmWQ@D#R)WO{EvaUX-0vDPBmQAgU6VGN8Uj
zTqy>*BtGQ~^Dm1LZpND<_M8K9MSN=yIIoIVPKVw)v1bcF>%~&~qW?AVh2Ow(UA%P;
zpl^tueg`AkAYM-4g+}q;luXei-cD0~vv~9W9H_l1eulP5E#gL6cU#3NUqSwsxaJ(%
z+QjGL(ZhDJxCAOX#M8@B*(rYY32@#P|2%}YZgF=3N<HG(JYe4ycWnhruXtM+F#E)@
z<<N9b973sM_r<GUK;?kghi=^righa}Ph?0Ov<Mv?7KeNZm{IYiAJL03am1St92e&;
zfr<y>F7iH1h>z??<)nC>87dx%+bJ~lNIXhzWEaWGL=ZQL#v20elItv#c1d2Pscg4o
zRXI34Bw-Z6@RX$92H7iFhMa4Mlb2)@c~rb5S7}l8k+^;e;wvdEgZw_p6JhAneu?F8
zDD;=)zKO~MlFYRb2$1;E<8@H-1o^KHNs7p26eLOh76QSNVj21pE*YnTWQ62P2Pz{a
zmKF#^NxmaT-C;=+xr`h~BunVX8zV7J06SI^bOUH{k}Yxw#!Ck7qB22pg0eglC45?(
zk|YVVCMQb<h5?fznMOOmV-m}Hv>lh2jzc_E^7*?M=aZ6_H8Av)WHu$2r%9^!LLgo8
zm^X$bL&Botd!|Ej)e}6~lG{lD&5=~FV0W%$i2m~AjKo(3!92<HBS0&V6e&<yD5?G$
z<g8>V{l4cU86QGnk))oyjprqW?Px2Jtfx1%RKlXSxJ)vZhf=xZ9g5;sNSY{Ga6wYz
z3Gph4W9e@2T$K2Epja)*qe<wJ<RzN*E=%&>$B@=a!au`6U6B-%6XU8xPDv~El3P!L
zT$7xqc=2_~`>R22NG8es)*$(q2ES3VY%7dumh2t?^i9dfyV2Gn`GNdjtrB0FiEl}M
za!@8&n`AoqCp#p&C_K?AY0*RdZAk$6<a#9cDIRiHa{oOD_DWW%VMU+hE4mcYFL{ET
zJ@+N-i$EKYy!abf1|^XPK!zlzi-9sMi93eUh$N48ZljX<<d__n%%-mjK9IEi?0{_(
zlF&6Elakzg)J{p3bU@;f#3F}HF4FfpVWF#3N~ytaQtJ|w+@<q6(BECsOO$uJTN;##
zHcx3IrG)I2`h|nVOIlB!1#fBdYLtAWm2@QbmBu~>PCw~33L)&1u31g%-+pPq6wv&o
z%jpL10ci)t6$7N@NgxNM@z=l_D7C~x(;?|)@@xc2zoabOVCkGkKnszM&}Gh0>9219
zB}~eG9SXyxKfj1lgfu)A0+G^c1I8js+P)S7hou1(C`C)1kT36WIwJk`Td0VUR#Apj
ztTfjNXmQeF+JVJON9Z0^g0$~<R3=IT4g>9|wCPP4nk03hFnO}{r)qGfNGB42eN0;I
zkJ52zDs3fBNViicJ5{><11LNxwHP6AO8O4%a?+$@YryG9mrmaZwA0eG6OhP~*7!h0
zw)AOA*gYeC^fbDiCmo^RFkjk2k(0AhDWyA}lU~XNDUy0U0l5<C4ce5JO4)P-DU%+h
zWSI-ng}*{mrPTf<G*n4v(T2B1`UVA<FG)Y47}{lrG~Efm%vEVZHhNzt%|g7*sb2cT
z4#?k-#wUTNL8|!zq*40%cVM|GT}FZJ7U{o2ptVZpQuy|k^mZdOwMieX18JAW&?c`#
z`Z;B!bV@(_0v6tuCiDWOOX^7*u{%=tA0XEwb^JjwkGs+*=z3tUw2K^PebRsS;nC}t
zK1OTCeW}0?f&<cLzJtV|H2On;4oT<GiC|dz(R~;*BF&3M+o*K?Mu3e;V}C^DxU{ew
zEDxj$a$(biv~LEWC#5a)s82~7bAb6!`lF*3tdFGLQS_|KememkSJ|1ZKy#C+9*3sg
zvN?qy9<mv97TzOsZh;C<Sv6%Z?v<^xpwde=8VEFR*@9c(^pR~#0GOX_CvDR9$(E9*
zY`^STJ{0-OZmmY!0oiPNivwg&uAuktpsc+gBv5vmUie_y#ye;Xku9YiO{h#V7dA!6
z`rd$wNZE^C=uDLC`yr6SvMm>Y7A;#y&qa(Zei=%!vU+k;#>uXvq7*O7<pMfEmd%3|
ziL$&xl#a?)+t9%z*}4ssRGTdOo~G~=StCtN8L}LjrZZ*7;sAPDcG?FpS+W!g3}nlK
z7=X!<ougFbTv^v5XgVWXL`R7{8TToa@?|sVAX6agriH6e=9UkXv$CJai*rskun|9K
zk?a$iY|qOQ-=a8KvCQ8K>PuutT)<N*J5L+eGMQfiO69UyOHrzjjopRd1z9vD$5zT7
zj6$GF<`sp?i?Sg~L#mePZo=#uS?*hSoG;1#rX0%4vhmM=a#dEHfl{4p|4A5HFFXGd
ztiK^!O>>E(LDt&@m_}LX9k4dZaw%HZEE}OTq?<BqP4RTgyeKoPP4@0u2)4`SybOgM
zvN<1svr{&B58}6FWi%FDGVNEWyd&E*1K8a%C;H}CkL(9}o9@bll$+EmTeTBleX`~S
zXzO>#dY(h$J=t6(iuYwAI-(B9Hr@y5ploRlV1{I`-GRbk*_)KnH6jzy-H=h)PDB}<
z#$;<~xW;9wS0L~}###$9Aq%%b)1<6}qJ&ej-AmB3hceyoAdh4&l<eXn-}x`ZUFD7=
zO|aWdK1}bJyF8o5WS3k`i8#CE4tmu*<nLU9-aYbT|G)}Q`Qx;c+A9yFL}4#^^8i$M
z%f0rY(nlUbcL03l|I+@(PrlIvWBlbF<V`*xZ>3Kn1jv_s2bP2K=3-b8DF47g;qpWB
zh!9{0$qOjJ9W4JT8S)|WkXBTN%8ST#7$*NR3kHYFpOgS5LOz|o7ZNGoo(}a<^0z2^
z<FI^lHN>Ok2Wg=`BL9Js3u5HUo`S+yxnBVk#>qdSEQkd8?jqQfC~t3~1NKq5%Y5)8
z$-VxCV6xmd6QyJFzUQFuxV)DlC@16#Y9Mh+9<PSIY4Tc{%hKhG=@-qA`$nLYDHrBK
z;c5B&FbHJHYiNzimUq#co+FQ<+ZDO;!)6Gak)NmgW_fa-FDXwlU;gMT7*!yT{22-h
z<(u9`<5~H&E2umt|AZ2)isWCt0<`n;^fL6YSpMD=N+t4V3P4KbkI}MUCZ8e)Rk_@&
z8*&x$tB1gOLGE-M##GAJ4uGXfp40{n7v(;&u%cR?hcgyF^B`YL7sf8hUw;;Ym*q^_
zZ`aCyCb#_+`JcDZc2z!~vXQRI<H_T4U7q-#(_6lYd^-*D<PlUh%6D~vG|4^4>DDY?
zL?3RuDWA(nWsAI~3JP20_vyaaEqM{$L~oZj>_E>P9rE(asO^-i5<&XpADsv3m)ja4
zaZkSC07mw{{Eu>2F(8kj>tloRKH?mbKmIkwX;^-fl6ywvEP9Pb<z+NYj?1IcF%}Qx
z3sgXvkf%4nm`Qnf1S+TG^XpOhP=1fDW<GMr*SrK6S4F25*0?EpX`*shc+q*vLt(iK
zO?wpFaS%^M&}OLEt7!TdEMAIN{s!?@Snj|yAI0uLp!h1@dH_&A#YQ?3?^CeJJ?^h~
z;t<pyPzc6geSpIJ7+4M}O6bCJpu+KH1F#P%&YT5IkV5z#N+F7mDH0f}2%#r9OfgBR
z3gL>6{({{RiaGQoL@E9(#2_A4oS*~P5rvR8Vlj%<Cs7%z`1~OR5)`?<5KmOxp_H4W
zics=ZoKk$73S-g~FU!!~bVa0NJ<u`~vnn8%sW3kP+G&N5Ce|E<<QiCW74yj>c195}
z4;JPrPH@1PuPAi^Xo2G0J<waISZIa9vx+|{N9del$&;uoQmmk@{CP#q0%#~!+@&mv
zQicCVXe(1xE&*q`!aD3gu|lz)oZc4{6?HK2q9TyO3Dt_1Xf>=+Xu2VPNs;(1&@L;S
zDQ~G(@sND0R}`x#dU93KZG~K&Vh3%3>J`y+tK*u&dJihDEABl&Uv4P=rI2NVB7n9c
zjf&ZHyl7I)e~iw5&5BeB<ZmjtbXsXqw4a5FR>ch^&~7QdNrI*}#VYI-o!S+Nbo;YI
z@%?RZb}C+`6YgzArvlhrigL=ZxTCn=iMDRVmDy<PQ52HT@2(=L9}0UFe^B(RPf`2^
z!1@)nz2yJAr-&oZ)_uhYebs(IF+~2kK}8=qP=*w1E&^>>arrI4j3^?jFbJcH5t{DC
z6dQj6%eaF19n?QiEC>e6gksnqDkc?spMlv^ic`5@d8qiEjtP$xi^zB8qP(1oHaF!s
zd2t-Om6z#M=b<d7oy8tyC3#^zl{w_|+pDaqMw^#1@h7x-D=&0F!bka84+ha!S<(e#
z{FLqCFlL|9={nT!SDJj#=C7RgGz1PPFVP|sp!}B{kYUOmN=*z`ralGE2xWy3ZIKS;
z#x&GMDaXr!eONgo7z(46O8O~}C|ACZ&crCMzY4TirHl=m;*=uV-^44c$XTAC{NP=P
zCn}$%te~UHj2#e2Qc9))J6V}W8|@TjeJ9$EDMNFi_qftyJxV8(JG;S|s&u$I0qvyH
zN*lRT$^#12rYSwIK`>qE6bzUQrJQEXOy%qJJ+#xx&vHSslxyWc%T_v(<1<J3A#vs^
z3y+|5M!EPfNS^X(3Yq0ApL`pb1xj`RNTKpK`b)#J%Gn~QJ*S*-xT6<E%0xOKoL64k
z1D;~#_#yPEMESf7tYyly*D=85%3(_Nt57bHLGJ~nk}l>|D&Ho1tCZ8fg}_DSCJn%<
zl~t6lQKMYm4HcJ^0kkK+tQ1j*uU6?n>+Th040$K&mESCLpz)gWQ}Rn(S3XCs-5biW
zRe)(wMhv6WsI<|It0raPFA!{24wD1qrZR-C7quui`~dM*<(F>&`<8Ow$FQkQ8A&+~
z?aHs{DA1ui90HV1<xKi1ZYz6ZfzqXXHv}wql<fJ_@cwlxmzM&qN7>3m<6UJ&IXcs;
zJV`#;K4l*rI{KBF6m`9)ETgUFedV{5J~*JfKt9Sr<@%YZ98#M81Q}M^=xWS}GLcr7
zQRT`IaE>W2(avpLDIs^p1La~h$b|Cot>pilR7O0GUQ8*2D9rRw$)@z*N6KmAFvdmY
zPflQWmEQ$O>{1yn0cN*qh;pwzRmYx2<z7|VEy#JP;8Vq0p|Y?*{8Xcq`ngXP&4Nw)
zRrszK-U`)1IgB}=+B6qq7@(4dqU1QJx{(hWsQR4Vl|!m>TE~J^UwnsBuqp;$qHqdP
z+38AZs7jLwm@w7EW|YEJ?)1h)sP@yAK2oLl4Jc76&rwt!R;^*86s^h?z=|WPPsv{t
zqxzW^zF5`DXF%dquPudKyhF9%KKhiPn%e=;MAeruC?%`*>d?a!)z5i=Ii?z=Sua)9
zM9<tw)pFVuo>JvMhEkg9Q6Ea_sz@<FGgK@8z*uCewl0LBr&UkAgUT$`@Ksc1tMbzU
zmZMs#0CcV@{WdyyM&&pnL@`hG$Q>kKwUzD{6{vR5Ijm5%V+=fJRiB=OrgJJ63K<ls
z)V;tyuewqMn~GJt76G(GWu#Bbm8wpC0%OWl-z~)tTCQ455r+!ZcQi|1P+7fDS*a?f
zNxn+;9?er1RW1&?OL|F_M_F!{RWJO7+FDh}To`;sHS0adUsV}bqpeOgYJ`gGs)SxB
zyrFvgLsT}X9?;#CJF4P3fOe~@{(|}*Rq12UbXT>XR<mB!wo<6?Q{~)8m-<z;NvOQ1
zveW;_-dFwe7p;E-s)uCvpz8Bk;2Baiktc6hwUItTKBD?z912HOW32!kQyqH-EaR#t
z>8}JHsJ2pO$%HC(2GmcghA8o9O7(Ol<XqIRQl_A*`n@g)xT)*t+Kjupu@aTL)b)8F
zyVbG3&}WW3)TOcD*`t=?5q9!aH<FueulmfVD0!*B8-;1!>U0VW`KYJAjgj$H8z?a3
zr#8^6w@+;$U(|l}bDPlSuP&y9m;-7DJuCt0U=vUds)H5a3{+321>}(WZ3?0UshQtX
z5=gN6EG037sQ1xjno#w6@?M3hXDI;_uJ*ZrQiOU(B}$QMmq^G*srzV}Jgk1j2AF7d
zwGx#_)cfgyicx<=2i;ipEQ+zmsb3IaEaKI_(4v;0{)0Y4nyCJT4l+m8zkCjs50cc2
zDS)1=Uh@LvQ`Bc^qkc?%j9fLx)f}2WPN-idS81wxS<tg4T<r`a*I&9?N}ry{Q0LL1
zGE*&~jLOsM&!z!8OMUuppk%8r&H~9%o0_3MSAEP6iq5Ey(TbI)j@u6Le04`I6cwns
zba}f_-9vNdS#|vPz&xks?*%DRZyN+TuXg?%ze}-tz9ScXDp7y=3qVWNu34xpQ$JA&
zm~!>%7GPJX8!74Hf?7-|k(KHW8s92)9=W$`)N@-=x}+YZ;LT<AYTC5as@<Q3z!i0~
z8l|gh?{%=EPJL|+D(lswtr&xA>fb4m^SZj$;ed)8>IAxk)1clqiP}c>o8JMgNqyP_
zy>C{Zv!Jb2y^-z-+)~RaYTBmme-&u$>U3H#JJgHlVBV>Ymx1$++HD0$w|a{OZ9VEY
zQ(#4(`gb}^_Nzz8wR2Ccqa5Nv^@dE!TN+YF{fy$UI@JneM%0^UKw?zAekT-;sT=+W
z^T*ZC9s}qD^*fY?G@)KK1ei&+FXfs}sdsRJ{ZQRH34urI*VX{cMI)e(5x8oulk3|}
zBPI`myXI@UVzNu)?1o=!k0$#exhy<2ztJBy?bTG%6zrq9F#;=mHIWqW^wVToA-_+f
zpv;2(8Y%hl{WT?&mvKO|d<>cbG=+4$IH<Wqm(>F`Tmi%nX)0-x7Nq%@e9ys}PdA_~
zM6;K^k`$`>Y%b)&G}}LbO^$HQ))%27LX)rpf`>KkW~hkPq|&5$L~|w)Fmakpde-AL
z2c19?G}|d1JW(?(3UWs^GrmD7N%P!8l#(^`*FzvhGZqUAk7=R;(52&=vH4JcLbHxO
zB$%oxr=*9Inl2_3opNYiJAv9XP18>x>6!(Lpdv$aaT?GvHQ$|riP;)%Gum=AG23Bx
zu7-0IEax<XzUW$!<~aEU&TEd}f)&M@mfuiWqN#|(aFuHOZbPn2b0rQ6%Qb!<Lass+
zK`FKuG*J|@s?<2vegcUq&B6=dxu{{sfK+Qz)1awFlR{T&E@@Kl0sFGXyBVZbv*A;)
z)M=ih38r4N?iN6=Y34jY+jWhO*2Wu}jDKNMgT{&6)Qy@b%DZjSeC`XmW=%S!1h;BN
zCqZs$8Xf5vg*J^7#Yx*Wm2|r5(0oW?wNA}bl#6g%bC{waU7D00$luX$Sm3;?S?3M8
zUd_xc=xCp2Io*=z*ZfUR>w6l%4<K+~(<4FUfac{Gm^P^K8G*tfje$-AqncIZMj6x0
zFgZZSHOFZ7dY}n>4LlQ?Q}m`!YATB$Kc)Gda_t^!UZT&0J<>2KeCVbXJp*Ihwe?bH
z+NEvl!yxR@etrsVp4u5~aPHM|?g7k4yYM+!=&Rj8kx4)8vTZQiUt3ZKmIK<9<&?4&
zp#5?HMjg@)y^O{n?UF69DOh_e5AtDJNgqn#+F@EEBeXk%p)giEx*q~@T35Ph8L!=W
z7o`MkSSVN$wO{AJ-lN*Ur%+1LZp?s9$y%KN3RAT58_;k}`y!oek84xlb#geJ(E6#t
zld7%p0MAKnYXy3LO1o?kNSgNQbaXUbyOCTp8QOpTfMBM!h)yY|wReAqiY%>e5bCqF
z$H=RZqn#N7dvmo{j{)<H_C<;&<Y^bJgFwD^Ll~?t&~718s15%H0*<p<K_Uz;($*B9
zcwQU-2^1D<`^ei}qCF#mO{LoBX}T=aKAwTfa_#0P!C9fTP~hN#Ho61?mD+3MIjqu7
zoP)xP+CsX>RIQELjLI7A?g$86(kAbO_+{;aV-Tp-1{TALD-NxvC)C$#WiLX-HSObB
zV7;!ra1;hNYG;z~yGgr+{Bq6O@4Qgistu&Q^et`m1GKeiS1*Q&c5UP;lsdG3OHu07
zGROgcM?1?Iq+1(F31>ap*<6fMpY}`g@%L-9qJeTx>)7s##`{_gB`pnT2ZU%G)ZRRg
z$`NfFok>Tv@xOtLX=BK7IibCm0Zo%yX9_w^X}=)Hr;DyW1tnMAk4&_=>Heufmv-yo
zenh2*u2K!?J-WuXq0m$J_b5>I>YhFU7B8KfBNWtMmqPhI2XxPprzb!+XF3M)pza{0
zCkE>D^jII#&7+-ekZzv{ZNWNc%2f@~?RX!hP~D!#K*DtIz6)c*b;}!|B0~2#d7>kA
zMe86JrE6P>w!^wO7Z?+*TYMVih_2)*2Vi1!uhDNGtNV@IKXJNew}Qm$R(Yc>LAQAr
zZHc<^9Y8y(yZ<iQl5|JPp)grzA$LfMF5`8K^D*7Ki=gSaPEV-}Cv-3IVRou6gL1u3
z>Xy@$(o;HR1lrPcf=HCobzBa)EHZQzpTn9=-N-_W*J)k)EudxTbTL57*11o>iX5Ga
z{v0A#=T(WyGrGqcAfKmOMy}a>9hZLe0$teKC>830oq%#y*ARosb2=XNtVs6_-AFyJ
zvw5IYtn;PWvP5S;LhE0tE-D8K%XH%u87<e<w}7WYSEoYd1>I-vK&#YoDqwe&?j%Li
zFX~Q^r?gsEOQ}~iy0vjA)#}_Sz;Z<w0zZh;RbB0Mpj^`xX2PcHx->J$4c*auFuO^&
z;vX2(tjq9&+{T-_^E%Yt(!KjB<lA&5zR=sQ^LZRFw{?r?*xRLxqWHrdT{;_}-MX}N
zu=MD@qIvnQZtzE7_v+%LVCmBp1+{L&uI@Dn27f?z<zsLT>2`e&vxjxBQc!M0SG*mH
zMs+1F5E#>CQ?AswZlf6j4|HcKtz$yBj*qrUol6iZr*v~D&FG=7_6YPn(oI*vG8g?5
zkD=04KYIo+-Sowqp~zkTSv$xs{iuWX{=4-@4nx92|NLg4?a?2klaHr9@&lCi>IY~h
z_R=>U1&p`;*~d`nqxbfJX}<b)x@6&}|5pXm_UW5?Ah%z?AR3(h`c=uOJfQ!aTnz#G
zf#1P-Q2+fKs0`H4YJ}QD`dls@M1u6+QLHOi&$x*`h3I|ff+tk(`3+1A)Bk-H>cjP~
zwLl_5|9(3Rjns2KgB4NwdU|~i>kBDx9j)JS2yI97ui1eaqj&iRBvwEEI56Y%J~ohe
z{Y(8I3HlvmTB1Ji0XYJW>I<I$Ym$B?E%eFyWi;!h=wD9&Ii_Ft0?a?IU#)?KC-i$>
zf=#LVMU*0aQeQ>cZ>RLN49KPF6(0jTUC$-|eTF_V5yoWdC+C6Xw0<7#r?T`f--dX$
ze$8%(=jbPpgO9(?(yyS;q@2<JZH1;hefclwOuqgS4>lF(o5;CQs6R><DbDJzMFI4j
zekm97MS6UM5wD7#M;_K<{jAr3Qlj7N2KA--k2gZROwX3Xv~vAt8VFSAXJ$ad1^tKQ
z&9BryO_PtKO238HuZwymeb2L6{}lt8F6#|vAz!QiP>s?R{oyCUa#gRTWZycyWi`<1
z^{ak_!fX0>X|BJnUrZ^(H}pIg2sG#|fzaEicR2zJoAl2JP-@n@ybpn!`b0`<Zqd&<
z2$WWb{&(8W-O@i?379s0)*;BZ>mSvju|wZO>uslAO;-kQ>lY`X)TMvT8v=LqQ(r@2
zw?2^)dVBQqG9h<Ye>?@6diCs$VCmC)Zw5=h{!j8G-_z$Lfb+h7+zpij`kR!xJE(W~
z(-J$RUq#FBu>LVh0vOR73cxd}?|Tt#WBNr)K*sf5?T~+<cS-~2g#IVmQcvm|QlW54
z-xY=ddZ<tHLfa$#_k`_Y_=WDrxf*tu(6e2J;e531HoV}4N)N+>g%ICk2y)PsP*1~~
zg(&Vdm?_=P%P_JP274RImV?#Dkk^k&UxORH&3=YCBB1RvWYPCw_Zyhxy!AKC{1%l5
z3<oGO5@7frxe*T<a{VyQfd&p`%N{aJ(J~ff*uw=&u;C)P+(HaKa>}_6HC%iatYHR5
z32MU)J1Cti!tjIvV-abXMQ5ET1HT3;4jY#Ep)K0rOF3Fc4DoV^#~9wTz_eJy%d=1!
zXLxP{NW9^<Rj?w#&@u^>M1w1(mK`+&&Vw;YhJPuSG}(|BOsA?8LoGdQ#|*F2+<DxP
zM2DOchCU{YNi}>!7jx1K*J<aLZdiT*3Ns9@bXh3V@c2BKecHg@1q-tbQI~;|ZCLdl
z1ab@qSD=(@m{tXQ&lpZ_fq0%_ki1p-hITp}oi!}t)Ax?g88Ti4XpzDAG!&K?g6D&^
z)L^IvPnqGV?_kUY!z(MGu+p&53=69aVme3F7=p-6b;-aIqjcG@P!4j#keZFk2E!tX
z4mTQRwE()w@aJN*H5**Xw{g?3g$w8w!&XXtceEN96xz6D_<{C;ZH6{Fb+;Q@DXiRK
z*i7ljody$S4c#^*JPGVB!z{W*amOGT2I)5Z)Pc4h!&8Z9yKA`H5Aj|@90f@F3=b(T
z+i!UMQ$XJ{{76sWeM3F<Wx#Of8B`8B4427kHDq|_Wv~t#PQHuU5kt&Yz>FH=Xiqy~
zkkErTX?TZ{Ql<>nzhLh}gOaii9vRk;fyKo*c>?`)H8Psf=4LEE4VyfS14R(nW8_+a
z>1muxFV$XS<P%WuWjsvIYHy<>hdwjrV|<1@!@kCjf6=(lIM)iY-&isSF#g77ip?D`
zYK8$5U_9gr!GlJ19Rvc6*?C|&Wc-z!w?W3|H=!-q$gzWj8t=#e9cHZWg@xh9wf(@1
zFup~(q>;uIvta#U<9CkbkdHP_qw~xWqc1rSV~x}6(HLiRrO0HwaRn`IiN=!^fH`X1
z7KD*WGX6vU;bfyM6apzm?<tf{7^{||lxmD3N9#%BZQ7roGX6l<p3{trw}2(xIBJF!
z8O9$ex|?a7noaB9Y2%OdwW1tj;&O~vu8}_i)-%SpegSKq@f@Z6=NmopP+4HK(lNWx
z7*4yvv&IHGsGc(hlIOh0*x`w`^Tri(VSTajf&v01#u!@fOO2Pep{>jqeFp;N##9QN
zRTz(bM}goA#&lQ6Uo@Vk*ip6dUOJ4aF&@^T@{)14H{>rH*N{7;)_9N{c~^`dHlp&X
zarJfx)ES#88MNN`<sz_LGgj;cxo#9(KwE>cGa3So#<ykztjYLXA%4PU<K8b(dDHk~
z0R@6vjGw#+`BvlBBWS#3tegSc+Kg|W0%<qC`Y$wf7$=@Xsne*Vr0Cm5Sr)LnjO#xJ
zxnq3lEabY4UgT=*F*eeTj=RQGN($>WzVs1Fea4(iu&Lje-3l^beEMYw3>w9h*6SED
z&MSpAqsH-%K*o%_7Jz5mxK03@9vBsrY&c=`*od}CV_Y=a9vSb^0_0+vW=ET=N&Yy7
z)ZH|Ljmll7@FWc0Zc`!|<6+{{W3|WhwE-nh(?SXa?=^Y858`FIunPj-4%4y!?vR*<
z{zTE&^wC;??l+mq|LAY3{}lZ_VA>D@i2xI0IVumDs>o*-Xo@}wV-A@<`4$R;OmpaO
zI)Y6_*eE-Nn6}Ye5^CB&vvioLh+NR&Cdo96VT9>X3os*1e+EN5%H#-m2Rw&OksBcq
zZF+MlYLA#=DVh*t`gAo&g6Z#i$S0a+)0M%aCKZKAlT4k-_+gSw!2<wIG3}m$`eUXs
z+TR>EmA(hL6Q;j{K~haMH^6ez^w=X<f665416Z1A;}z&jH*I!M)<K5px8G6BG`&JW
z*VCq%-=Y^;rqi<_pKS`Kz*~;Vi4ucyO|Q`Q>Wt|V@;&F7diiL}H*KwjT!CrqCy+wZ
zoK`42YwGq!&(4`H{{(xBOdo!M%JZgc+c3<<CYM&Al$f5{O^HyYrf-e`rp&bW11Kyv
zWpZItg{g8GP5q{IcCc2Oew_jJRVLqYsJLi4OQ*7G)7);58dD}std~rlG^boP9iga6
zttpS@<twI<mw<BBl(Y`U)R}%FcSODE>0yv-Cd+?`h}TU48WeAsBFWMQlZKM@8%<6$
z(KMN6kwdQ8^wHx0y=m%61ZgoPeFO_zO)e8K`<Ce}#lhN4AJQz)X)?t^?zSo7CA4*!
z_S3f@@0dE=AlGg3UWT?FQy0Zv?wWSIH4X1yugQf17Ja5I1L$bKX;=#N_e_V9(Wm>S
zMHURnfT?#GEF3fq(_1lQieHb?s7bU6oMWbnMJSD%wB&<&VETa6PneW+IGQx^Y3iOb
zxrM=)ho%#op!bpKJtjC^%m?UKcDR~F<V|riFU$syyV>4=(k^r683^t%|Mnp&J<XPG
zNbEIlr2cxDm(lUY+gvULi;sB-;WQ^-^E?U<`I+a6P}*mfNPx26>>hy;^*3AYq3wYA
z1A1};%+nWv<)HcIf0+;t^Xhoi9x{JS{=gu!+8ss(o1b|Xzgmbnj*tF^numS>OPINQ
zE)<5FU!*-^ggKn{T#@GE&%vf>^N|y1J7WIG4SHkDRT}^nYxW-iOPu-lH-HjvezpKs
zB$#_kK@!cW^!^<+JNnjuC&~Q71bC9o|I%hH#XLZ>$T9PwJzza<p1U6XO*JoR!8o5Z
zj~zqll==02Ff`5leHbd!%^N8BHN(8*0NOImv+sbMHXH1)Da-umU7%!}jnBfg9CP}g
z(3fYntV0L$%?lh$P+MTGpiw_(4nGM}Wd4erSLe;U_n@Q2=B!s?T8X)mw)>^#3;*ql
z%<?p_l$%q@hgD$?seq;n=C4g4m1Z6}H>%7T27p~OA6*Ug)n;#U64aPqYlpxk^P6;^
z?6O%M>cBwNn*S#O_7(HLlofK-oclT&>&zEpfL3q*g6<DpGhf(*w(I65N+7vm)_x5Y
z4d$10=uD&8_$IKM%oDVMYc|jO6GL*-ETNEMi#aJBm91tEiecU|=L;dwW*()Lz1_Sk
zl@ftF%#tXmzisy0gW4|h44Omln5$`Z={7H*)wIXV*$bAt=DKNU>ow;N0;bQrFb>xD
zo0seX=RGr%{QvjOoqBY8z`VE*EQ98CJ3)rbY9hntxfIMBF<<pZUq;Pu)lwjM%*^^6
zeHu64C(qOabKxLhCd|!FAd}{QlTkTk&ZX$dL-QN-m6k{5i(W9)#qxe5DqSrbDb(#|
ziJ@P_-Qr8D@GeVJFYMiIQ9i;@dRQK=LnroF3bbJHw5%Nm%U;VzIVd^2EYs+llHQg%
zw4L;^jG7?mYmt!W!q4(kJ$Uw6s=A<Jza@zxGyaxeXiI;<vVa`C0hV<XV>@UOb^|of
zA|N-)Axl^gDuXOf6hR=^vWkL;A(r0{q4%Md`^6}QS)LifIE6bb-_UXxVR^qBeTuXU
z@E{mvDewU6VM_(gSJ4*h37CJx@_^C>Vk}h_u*6#C?FWgo%%rOo@s`bF;7qVQpt&>A
zvd<gF9JRz#Og+g`GY8_y7ST&klw#RNE9Egui58W|Eso_OpeHP?3n7?l*?kn`q-A+M
zexOs96bh`SSqdp`m~NT(2@F1M>C>Z>W%-Sg%CarJ6+p|eEG1u3t|j1kbmENVBzYtA
zERWOR=UW=3Kq;^c(y^w{^2$*dde*Y|94tI%x$XD?#Ue}YGmtoM*+#qBVoL}m50zL>
z#6iB)!c_vh%<>|I@yad7C{eq@68<FgUa)+*9et{_ywwg;WjReA%ZrvJbf~MgWH5kI
zW9gxD$tBB)Fp$fZtM$-VYhm9&+ZD^iN3@T;YEkS!ZJmWf30(D-nNLE+HH+6cB(7V!
z=*7KZi7SP|2Fr$@A<$@XrzG$uOFubInk}V|VD?SRxE2<+SQ;pP&}z9&=lffhf9bMH
zo2B0yooKfVC!^G1Sy>B~PRj!edG&8wy3eDr%kuMoYn3H{@>jYou{XfeV|lL-Fn29w
z%_#L+1~Q<j&+_`u82o-q%mnPcXX#ytU*x{U+yeCjmWHJ$4O)K7KxxRbVkw}9Ew9eT
z;Ez~}o`t}urB;hBjakYT)8E^TTedz06%Q;&=rYBG<>nGdOj>%#Q9ETh&w<24%Q{N0
ze`Fbc0Yl<q{kj}hxLVh3gH3MMK6kXaTLrWw*kwIHyVyO}>y*UiX;rNQ*=wDvgS}o>
zZWA<kTSsX-=wp51IaE6KS!aYme!q2!rb~aTU4+Ji)>sdy543*I1n42FPd_SytU+{_
zBiI_H0ceQTYC~J7^|iOrnK0`I&M+q2`qq~q5!QM0!4hemmk5?9t0fd8dc-<31`RRR
zt;fI;YaO42hB$|H?FAI$t+TUXO@j44`R<aeztTY}+3K|h3RA3Ke1^6YR@G~eNVU%G
zM(Lz=W+brFt!Ed4WLTwAv}Ic7QSR(%>k8U$XIYix;LWzqSPYgNYyD-Ea;<+-;?)`J
zD0wyVtd7(YH0E1BS6~ndtidM0oU=|*MqiOt)q`G~w>G{3iBhX^6G)lW(g;#+eVJUr
z7pxU@vaYm7W<hV2^}!OTxM*G24zOx#GaUnKth;F1xn!Mx5~a)5D`hCvT2(tSYFDg!
z2Yrm^s`VZ6-_%>bIsmk5*5k{-bKUwuD2%yb#qAV4`PS`}D$;2EfI=!w)_asB)ok_h
zhrms1Fb8AUV$Jysm2K9eKSO=H)k-Ph9oBoDu&L8JNzwb;);&l*aO$!ypjV~aD*4fY
z#vW_sb;#efZWE$Uz1Ej#pV4Ri-5-_x)?e~r+C8f@4tnofW64uGV113At3m4v-RQ-T
z^?C_P!&X0Eu#8wE$Wb(E-Lf2|F>49kk9=U=OsD1v>$jg_)F-W9(`-3qttzJfdwXad
zrUao!)_%%Qa<M5X1JTv?aV09<Y;!1@;BI?62xOP-7cZE<+g9*1SUhZ*#{s&>cA3r&
zp0-VC=##gN@dVm@Y%fsamapya|NK-oSBi1_+t#E&?*UshoyY@hCy`6za5`vfqj+VY
zZE!z$f^DzP1y6`g=z~(IZ9Taz!fe+m|1#XB&P7{<?a)scnMm96XjDeos<%MzVcY0!
zbUWJi4Q1;cv3>LutdFs&+#w!oD|JRG&bB-o;_<eVi_y;nn>%GwIudQo!)QEe3#bEH
ziY<_0-N$U!28{D@TW%D{3ESu)fTr5Q$>n&`_Vt_4lx{0<$B<;$EOQ{9X&WzqP1&~N
zv<&9hCf)_fwdvk~!ZSAOGGOM}p8f|K@@-YL;uP2<^c}TAhiw-HTF%;9XW;obXFEcl
zq%5-i-38F|wgU1z7TYQ)@K$2`gXa8F+Xr8wt<0A8E37ED#a)DWg)L$$`gFne3%O=1
zZ9#tkyUJEaxqlaJZ-hgj+U86?zZzTM<FMkAZ6BS7F54Unhap&N3!^h_ooyxU#p`V?
zFQD<7?I`)>uG>DVK;;dadptNBY<;y*(P-;h3xOtE2Kk$sZHwuvP&aMsX}DW#(^^p3
zYHOz%;+D;Q1afV*Unun3ZrgAZU>&wPnoBxuwT@rFdfPVZDHOYG<&=JX$F^q<RCL>3
zNJnLl?d=7y;;s$5I=mdV=g76xXS-es&VC!0vQh5Y254d&uuUvQ+n_C^1)M`R!7hjo
z+hml3K4KfDgX*X)kuG73*(&H-*|_a(fAYUf*nS8FnY10Jec+Vs={1meX#17oEsty*
zij}$8XKzKNtNo|XA?R)&NyVt|vgg;JZMQveBjh~nsaIgk9{UCg;d<G3T|>#+emDV~
zKK5bS^7-1$$ARf*znF?a*k`}9m@dNXx1V|+tp4`t8_{^co=tA@0DC-nv=7>MuYig`
z`}6exJ!DsBfiuWnNgn)Q`{uPEA@+hLkPEe|>(T8ndmCLV3%4)314AS1H(l_HMA|Ez
zpfJk*?G1<@wwGkWrfB=l-Q@o~Vt@O6$j8|KAdgF|-AoSkIQu1<z2fcf)dD8L-dO{Z
zXfOXAHXXGOe*qOq_V6*3j@h{stvzl(R0Ql3_O_KMrP}jbP&#S9y%8*@?1^dUQigpl
zJ-M0o4YSdg)AqPQv^lcu+x~(2Z2PyA37BJ_@`n0cdl_xr&e#{LP?=}n_zHTFZ-0tZ
z6xfqJQCVo0Ortl({$VRXi|p6mg^Kg`HCJG0u|4PtDogBnN#HECe|Qn3%)aGMpp@Hx
zr^DF=`^OY)s&v?kp9M^n-C;oOMSK2s$XDAJ)0VNu9!s6MWPgpmTXETbOAD4-`xrTF
zuGl>yQMzhxtwJyA?CMc;qTc=&g%PgVUs?k3>-IOuCv?Mplv2DJ>@QGSRij-y0?a1+
z3-quw+a3RV0KuE~p=ls3_WGL;Y_-QwF5E49e=d5_W`DdA@}2gBG?U-9FQ8l2UG|k<
z1FhTs*q12v*r$^d>aIOE0qT40Ido{~vzsW;(r<5efx>(Cm5+hkx6h$#JOlPRT6hNS
zM;&w<aLC?4;qYNQ+ZANQp7$NPHfB#)3W;(199o4R*pn$=ZNmP4mc9cls_S_>_b$t_
z%fiCmvb!v7G#X7YCNY-85=&xYNi;EbjU`5nCNaj{RZ-(oEPxb61(hmT5R|4ONVOqN
zL{N%_BE^O%il8*VcYfdhdGchOb7tO|bM}^VX69V((E6r(UHpI0?_H;$7|Gjpfxp9F
zH)BFG%)1*Wtb}VG#-R@(xy@K5Mc;PgyR=Z=VH`FQdOMBlY3<`>><uS3yp3+RA?jnC
zb^+Wj<3$Q4`5G&$!1)>frU~*l>U5Zy0OJHof9y7X<&M5R#sIou1C3L^fyiFt96hFM
zpYeb%+}>{t$pr~AzC&w}L&nWIkPzd<B6t{T6zK69W?Ym`@4s;4v}w?fF#e`QYou`n
z1walP8?Qk>%Gl`xgVDy;TNu+(;{v)ajv1>i!QbP?ZB%C$V;sI7k|&HJ-6OHaDeY*C
zGb-tL$w{N<1c03~{=`E)-YBE<k%>mvqi`n4IJ1GON|KEn?aodcXVX*UjPdI~fp*ro
zq#iOU#;0_i=A3cfD{!es8C6N88Gri-*yoL3MZmR8WB(Np$ud5D1(I!?FJKTk#=dkt
zT`)S`f!;;qUfMohGUj+f{j#wnA0k(bcWC`+$u<797Iv>1A8&+4p7F2Q;PQ><{efLz
zOj-<$LgQ_!f-5o}rnS>Gqd?!XDK_>}9rAT!>t-~T7_(?geZ$z7DpO01lRKeaX4KO8
zs+-1nGXQ<d__sGmxpC4v=&LYR(gLB<V%$ONvMS@pl%BqAd|`s8cZ~jn0eaWCu`fjL
z8D(_o)*74WWO1D_nm%KC-`GR@^Lk?u1DFQmV)}}Bqw!`i#@l2(kp>SR7*EkBcpe(d
zsxi<<#>k<t@Yv`=i|{8#HC-OfMvL`o(5J?K{<r2bM%2OXGvjbNc=z16;Afz<8UyLe
zUN4MEl#zXD{45n{ZN|(}=)E#d?FMMOQTP@HJB)K_EU%4>JsRH_%PINVX<YdTm|aF^
z+PZWb-FqR@W0X=-q1X7E<qBHg8V|k?Y&X-G9{}TSs?tEi!!(*6v!15?{%G80`eQ02
zx0?pjc5H{Kh$5}trVL8w`Is`kguz{=C$4DpHD%g@_?b49L(<<=Sq~Cm`eihRwA++W
z5AXMwoT$7a(DYxX1?*naijf%MKGXImXx(pGPN}mXlLrqMgH1zBn6Cq-4QtVO(DdnH
zkVB@1|K;XQo^b#TH4R7s2{Zlj8|;Rg>O?3+n7*a@@<>xL?OqR?S|}D3Wjae?u4t1d
zm0BJ#9q6L_@2E-t9@t~1A>_qz({xXe7}IomXrC|*C<M$Y)AxJ9#hWU(0w%#UoAxD%
zrVDM5Ofsd9!w8d2ckaO7)213)*qkx#9|%ilO^>CR?sKL+`(Yu~<lYIrG*iWH=$$vU
zOsDl{x@kD=3NuVwMnXT+)V3Z5vrMglFqmx`aS<fPwE7e@E|?Uvp?}fTP9LwiWcuC=
z?8~Na>6;W+O|Ra^m7ixC{wtixH+2|+S!8PG;l(x6bXutvn+%lKy<vJ<1Vg2!r(1wx
zDKjZ3rdw_rK*7EW)A$W&tu%d;0gWmX+W~Uhbn8Aq@0hamFj!;i`!@{Mnl?~fRGsN7
z2^8*|=2C36-qiOb8XHU#Xz|}@YNI7zlWBS@3_dXR_W*fls-d#eM<%~pfPQQ-jU54*
zC#JWVnAv7i&}+y%HT9>tY%yi0!O}C+Vt0T(H|<;u6RjpsDrkCP8uSv}OH;^LSZXu<
zy9#KpOs984uiX^X4X_T=CsZBv+O(PszA^0^0j|?Dts11uq?&`qZj&X<4z$Pgih-qG
zQz-4j-kKIzAme7Pq$Gj6`9cFY4|4+L!#vGy^U%1>+-M8CJI&T%Fz972SqJmp=6Q5V
z)5mNTjlNyxq}c%TH9Nfz;%5$~x$rkn)xutY`Mob-Z?}1wg`&=T%zdXqG0<$F2;yFI
z1-%sanR6)^wBJ04Rvkg+FIS*1*u4KaMt{J3j#m8#%`5w$?~qwXg)bpyts6u_&HY#6
z2Mse1Y=^($<^irC5$196@FLRurWGQG&0kYiAj%wGV}Xfi^VvT^j+kE!1<X-%0Ohlf
znf;qFisR;_nb40l&p!l9aps&+fH`R%_bwDpnO`3R7jK^R0YnnaYww~l$$XPeg(sVz
z(pSV!n-5iDEN9HdDh&Iq`8C~tspb{4;eDDpZYJgb&YP>HfJryEIK#IL^I}hMnPx|N
z3ul@Cqug({Ia~`a$E=J3xomdMf~70wT6z-anjPuuX;;lTDQL_yKkbD=zWElVFAB`P
zbYQm7yj~Ayip(A_Fo<hrk;)vdn<wKW3J!vr_l?4^Z<zDxY*MND94+h0%<VJa@GbNA
zHfSt2&r-tg3bTI*&??Q>=}M?F503|T+x*WMpxrUA`x}z?%%^FyQ*Ayp9GErc3_6-r
zYv$>usxvS71s>ivFE4->_2%Di!6!?j*>n!`++^NFiKPeTxCXR7G&|6>^T?bw2a1o)
z*S>_t6SJWS2H%(;)9m$_|Ez+@Tk~Rn5Rdh5zXbO7^~>9!?zMi_et5WR{Ri~u_Fv!W
z29e11$xksQaqGtma4m8DUlgD^V_Dy?7c!~q8@Iwl`ueb73_EN67#U1lSihR~cvseY
z#h|fpeV@~SxwHN*MV%k5KhgqcUamj!1Nyqwf9ir+^W0!Xm(I=&#+&F1*s!Y#1`lp%
zr<mX24Fw-V{ltcZ)8LXeY*fH}`UcCwi9ox&Vf-wZ&)e{vzOGQRp?V&;TN?)b1DSx0
z|9k@zAsgMP7B+fg@e*JsZ9EZy#*~d0cLObJ<N0Wy<ZTRTLtn|prL>{Ay)o_-L>e}>
zQX&4sjc!`F*1GYZ1F-OV<9PZCQ}@R2En4V%xQ<Z5ppR>4EL#0se;a_o1iIGt#U$)^
z-8Y2HyVh@q{t?$Cs`-s^UHu6xopf!ck8~xtjv&2c*UM)hdDiuNdfueC20ekoIoGq4
z;ZJp4_z-%Tu3ykDKg)IIC-5o9wRk-Jz3&UICoiD$qHBo(UR-kRvlRoq?D{DU?TYK>
z4?%KWZ%|=Gp6epoqvg9!{1$qJu0v^^QREsj1&!BS1A^gGvFildzg>3?q#OQ*YfLY^
zD0MYYMqiohpA<&9>Dm+s56fLgzeoGO3fHBS7O!+Y+ZP&DuD2<<ci(mNU4S;aeuRJk
z7EJJqLG%I`%(!&8cZ<1))uXh6`H_}=Rm|dKAl_m821Dr{vwjdnYM2>1aCOWUI=|e=
zgnfd>7UnP&`E)S5>7C%lS|YkZz1a__swt37&7qA1{u75&rlj9r$@q8w>eDdwK1U(V
z0hh_%zzwvu|LRj;^o|_<4|+#U`2pyo#clZinATYIe%(r0&9RZ;7|pmTtARHD<9G4@
z3Hek~^Ucy{(EV0!c>$q`BWU6BUD8KT{=UNsEt5vk_qZmzjK{yHd}Ix{sZV}_!Vla%
zOx2HPsbp>1WggJeZT^DHPcH^zR6nQDMqtJ+nz>)(^)NPbJ;j!0<^Krz*|Ipu&+&K<
zy>pk-^I=}abc%n^U*H9y1?3b7T{yfMW_}Hth4w{@sfKTHxffcNT%ud~xA$7nzHIn?
z{QGx)B;=QC1JJu7iVBNX&U_dD{-c*-#aoW2;Q!m1sZ@u$gQ@Hf3p<$=bV+(KSyaF3
z&8+GD--no(Ih7c}E@tAtaLJcx)B)Cysp|pa9wz1%Ow}^Oi{QyKMjnaA=gd%ges(g&
zR0-Y1jHh+lb~gSCkR9y6p)j$NjlGAt^kP3tfL(94ldeo3c9H^(yI4m$X5h;%c7mkE
zkCnDz@<Z7O+Qo#inROt?*){YWieWqGXv+z<KfMHE*#iMUi(_-?l*38(8C~b6*dsT9
z9nV&m0y}}Ny$+E?c61Z4li2gL#7SmD`hz>oeoSAVJi~6GgGecC8AY7VS=c}F(3;Ag
z91gUzl3ohBq)5j0P^aXUFF;czn+L&Qnxvo?jprriLy%0DJfTfghU8Pq>SRhb*<ebu
zBmuqPvL&as03}DFqd>t0$u+9Sz9{jWiXmN+L<K_cvSf=J$Q6mDlg>BfN^-u0%vH&d
zB4Fo9K6D3{FL_JZl>$jRRRtAFdM1DrNe+(%=rxJ)GZ-wE4Er9Iu1kt3PgWvXWQ6(+
z$#HjBDwV9H{7so;i!~H(N-mef&@D*@9VaZ8Y+nKk6_UR#bWp8Q@?jrfS4nuv(cYHq
zqvK<DBu{hU;$6vD+Ku0nIHS-+S}lp9`>#e4J`<9)lF3w4RVP_N7vX(LP%BK-OJ0uy
zX^{Nh1C&O|UD`i4N%p-4_dqgV1A7l8ES;EoB*~v@0qA4NpMKDPA{j-mvS!Ke`_TDR
za(^lmTO>mnh&+=-P`S!;$x#Xiw@PY$#F$=4f~oZFr9{34jcpPW9Tk2hai?OYcFBOh
z(AOaerCiBtiMjyLZzRhp&DJRybswZla&<I4|J<zFlQ9@~tDCo>m}uoO30#uZ9y36b
ztv0m)=CoDz3}~FOs!_wWvsV2(;8Tj#KmlHyv-<Hl?50``qPz9F)poi?ORO%w4|2n*
ztO1gxR(B~HcGoJOsxa<Z-L8dXqt&LT^as0|tR^mp=p(DO|3c=mmH0Od?v!3v0NYD?
zI}Sd1OB1M$$XDt`uXR6Z=6*E#OGg~Wm;$6d^kJh2=`SXDn1+vZfSi}EVxf>OZKT^b
zLwe&GxJ>D4TJ>c~H$=cfw)Bu1URZLZjy14*LHad0d`bGte7Ja7S`v!JE7D_Bi<K*V
z#|-_e(p?Tf%abziLL?twD~H_zsglC=*x|l_dX2T%4eVO$8sh4#Cw~U@`_>oe<x_7x
zW;95H^@)KHX|$I7OTU)IS~(1~-MV5RI^SCVNE<9S*)sZCpu4Q26<&DA4p3@qm#mJ)
z<SUDeMWdfAXdb-qm-Sr)6T4+oDIB~<Hr^HlFE@&o?2|RppAy_JJ4El}AlVp-6$Q&m
zsO&gIHvBM1sLZmT{xC(DEcO;0j+T{BVayp>M<>Wx*)%%Wo+4X44t?ijpWdMfmJQ8^
z`E=Quf6<pA%ccs{Oj*h}xSb^%NC%m+WlhfDuFA&HS}ad?i*AQ}neBNf6v$qWL}Q`s
zcWZ!MlVw`yH!PMdT7#ig$ZY$<?@HO*R&Z6a8-3y0ZJEXz=I_cbQ8Dp7*+g0vSIbuX
z3YZ$1^L1d?$=cLtye}J_gvJJ$eiBd`Ws~U%^FVg`7Wy8_Dw<*NvFzs>kY-sfB`}}L
z2ER|I8e3$q#=#2@8|#&D|A0;JNc=ztZ7#h<;~|?F)!;&Gq!bztwJD_!N`%=A$pK8b
zO%7#DBW%`EF>$0#H`O6T+XUPJ<`J7>`T*iln{_p4JZ4i%0frcxg$F@S*pzJqO03Nb
zN2-5_vl;q3L{HlIm|^g&P3BkdBE{y5U|^@(6yhZ%O|w~k383d~@>3v^Zgb=z6f$j|
z&<i-rrZEnE*)}bi;BstEPk}QRY`9Hmykz4|skqBFGiZf$#YQ*_uw0w=N$AV7xr}F+
zMVfE()i+Qqu=$9N&KKE4P+jRYo8=VwEw-7p8{8wCd$i4aY_p1j_{}zfwEcK$bBhAV
zEjAGf=smM3hzDu4+4UTHFKjNofn=M_I(mk^vbp&VeCoBCLGP%yHt|oO?k4~HV@O)u
z<?a{YjfZ?$GtfNcd#3|to4n^5eA+H=TnddH^1(yVxKkeX4-~!R{eJ@5Zn@zsME1z1
z7{Kk7&+m`v+9zLp5RyUiu!GPGmN(NrHbFj*c1?-$4fMuKmcOCB`Dyu0Gr-PR<V+;k
zv+~yznn;narMLJw`9><LNR_*M1QTiU$R>!Mm;We1W4b(-mN6M}2LV@Sru=+6yw8$*
z(+($F9%P1kj(l@J7`z}qITOxYluyc`pF$o$8_CP^KPZ`WMZR?_{LPhHYQxcaRqjB+
z+B|s*#RBu?tHU5#AkSI>(L(v@UqFiFJE%yYSpKvVBG=^`Kf$m|<e?Yg(+zotAIz7^
z@47;=Og`c;8gI&%4uj+^c`983<#O3`kV^TH7)Vyhzo$L&ZF!T0>Iv@17YqZrD_?&L
z4&Rd>oeT5Ta`{ZSRwK`+;Bu|}nk~j#C!b5(fcx_AqS06{PoPr=4RZIbAdT|rHfU^;
zN70ZT$j8zG@S)sw5HKIf|E2neJ&J33_!OvcqT~OE6bIj>^?!(>ixx(qij}8u(S#{>
zP;M$h(J>dIk%}hTI7BHv3k8W*$VNl)h+;66>K#>>&Z6<S;)4))AERg)0hAL8fs)s;
zir>~@x=t#(7Naj-QRWS>1jVoRP(QCYZx2K1ieHRW|B$J;Oczv^!af$Dxr!12<hml8
zR#GL3|EOO1hQi?*X0KE+@;ewTQv|QXU~VeH?gHkP;!ir~R<7tNg-C_s!xY%9ROHdN
z^1k8{#l7nlXJ`S~p!k`}s~Z&`hr?cz;xOI^7U=`U<*y<0P|-&9e~%QGZUFm<B4#fd
zn-z;_?ekQjngL5KiU>MD^-Qsyf{)J?!w<n=tHRS8eJ>P_n}GdNah1;AwJE02`S4eY
z{q#!jPy~Gpl-G){srKcKVkRvII~D#9fnw=WtfUx7w<72j^m`Ob<G}SQ_8bNGRxxk~
zu-$C?z6aObZ68hm@vxmq+YV3Lv$S^EW*hnu3~sj_+=Y4GVY`tQa64^}Ho|)!+b<|c
zw99r3EgpPrEA~Rt-`3?IxBy!}0j}+~*iN~D);+d`m9P|OJHG?idu<=B2e;35Pyieb
zv;Bj@4&k;(OCcFyYjYDM(l&vfwo$gv^>8%WHkW?;Beq-Va7mr*1qusw*xsRfQa5GW
zKag}+I-Y<*59OA4@?N>3A4Ik(E&tkJy0<G6w?NTb`48>Je3a>1;NmW2@CJbTD*wuX
z34diKg<b=cc9f#sqdchuOrY`voeB<8UVI0Q!OBm3Kn^J5_rv>x$~KB|g(!_w2OFwv
zqs4oeQlubWxU%>^n2l5}wmgN#Vdb~;K%$h(zXoWu(&Pe5N0l|Z(0ELFJr|<Km4BGw
zMT|0g6-ctuNDu4N%H%qjKcl=w0sgZ}XL`A%D8Km&dgqiDD)~uO4*U#~=ar}EMo(96
zq-0^1vTzRca+Hw~wEw!G)cpy&H<bAzd@EI&=D=W?@^CczZYnD^Ah(py>6m%Ba<nhF
z3gt_B?9?h_DH2+zeDNX3edTn@%G4`kK85#<O0_S*9w|-MF!)$0rEdg3QMxyRYgTHh
zeCe4o?GBwkd9G}72WYFZ;ZyuhFO;V~#9-Q$H~s?YP+p=y!)xWT=|Fp<+<gs>b}C2p
zz*3j;oBr^kTX}IX%=aiiqdUgWE+ibp-_GF;)C25-ZGgGkPUnHfJ$5XeEDf~lsDj>J
zyIC*)SN~x58{HQB?LOjw9b~t083r0`H>42y2kaztnH;ox&jBKb>^5Hp39+mA0g|D1
z36XFu+-_4FBqQu9tU)5}uGfPcwp&hnyePZMtB{PgyG!qiBX;l69|JgMS0#gm<95H(
zJz|Nm%Qyy@6L#M8X@fYs16wfAlXe|{qw$p8P)b6_+il$pl3<s*6KIKcfeXMT*}WQ%
zQ6$^RS3&QzU4Lu1cE)Zw6$7W(sc!+r%ijMPh_`*s-;ngNAMg*2-hMWH$>@;%xNm4I
z7W=JKMi^?p(;wJj_6wImBf>tV62C~Kz1KT582i1}Fc@Wjma_cO_OB^`e8m3E_aLY2
zH+93&v-TsyK~n689RbQYdk=bEq}mUsP=2BP)|s$WWM8%xu3fX=OKZzp_QmvWEVs9;
zx(^c-_OGezqtbpcg(9o$Jtsouw*6`<-MM4`Pa_)d+TW1j>c(fZKZJ>D`!xDcPmO)=
zdU#Q5|7$WN>+G90!~6U8Z|Tx&uy3RdXQO>0?NXZTZEWDo1N&hV1%GHSxeJ9C_N|ti
zfO%>E{9|;s*~=o~=_~u2qtV%Je`^7_4*TI$$M@QP^i_EA#{MmZqdM*LN}<<fU$GgD
z-S(aoa_F(&?*`X;?HgneaZ?@n8G7!jjwFb9s6=|Fda9<W;LJ8vEFI(8u9~xf@~=Bo
zK9|7mR5_(V)JtV$0GhYzZxMYysuL&BxJz}w2t{Ajr+0wur@Bk^ivFspH=!4xa;1{w
z-Krj%(mkr&_t6)q(kG*FugdE(ev197zW-YnsYWD1Bv_S~iwQcQYO$mI&p}lv<=GCY
z-l6SHh{|&;42G(f4uQci)!Q#%B3xBN-(`tZ1-=XJuxc}%6pK>z^~QLkRpU$0cSIGq
z7kWoka~44FnCjLWkmIVs<*;-@HJ?6(8LOJU7$R}1`71DaCsh*UN-WY-s;^D}CSLWs
z4_XscJ+!e%RCUnPI!Wbu9~#Lj1MP56tE#9R{fz2u55|<Dx<a2uKBwA4UuI5K{Tv4M
zG*$Q`D4bV){xi&{tEMJ^%TOt3v6ZPZx5AlRl?Q#-@2aYCJrpc?s^j#{ihR`%l&vpS
zy-b5lnQ9-^wcS(=qBAPDRJpZ4D_327fYDc|UU$I5N>v&?SgTYYG(q9E%DVz+cT~|-
zadcNTk+zukR28&Ms8+GGhObfi9RgUbY7k9+ovO+cBJ~!P&I_##suoHPHLB)*3hXA;
z=Xub0psJe%nTM*M=<V`I)fNZI$Exv>;GU?)(N)r{`e!xJo~qPq(Ac6n^gbG&sfLt5
z@44z}3!HhWDp~`uHdXB{^u1Cks2IOp70?ONp|acvg3N2xVp=l3QJp-Afp)5nKY)h2
z1G68E9u6X9;yoQ?RB5rzVe%e~X@^7GL7?q)Sjs@b%i+K}81!~<qE&;BgO4}*b~#wl
zo88x8&tf$CIdp`A^LIE;heHA!3Xec<w}YRh2y~CbqUEp@<2YauMiJ}yE!7d7bS$U(
zmUzedU*SxmqxmvSBs*FJNS<+=Kt)L@j+2JN(s{=W%G;JZ_MuXe`;I}2pkD8|x*K2(
zj`mx@H9Fo6hkBFaG&-L2z|onK6|IiPQz-xX!f~b>MB5!dp=`x#$8(haedD;<7NpaW
z>4ORCay-`$`rVGj6o}|?yl?@Hy^h)2VE3)#+*F{ssiP<x>#n{*20hewsKmlkJ@;QI
z_^Q8u3}`>KX*0$WqIRKBXQ=weMEZl3;pzqS2#-)dqe}ZobtUZq4y%LyfM~S3jZQhm
ztAFc)MuJ*@4tCSjYcGMESFa3%!F2V_)eyO&o<kdhT=lX2baks`AEPf%{U<Fv^VQrE
zkOKAVOz0J=@3U~GNImW-tv|1+2c?58R&%F7uB)F=wP=ZYA}x4tsGm_p_l|ldRj%Jv
z|4T8Yd+LNhSgKa9s(?a`T1Wy{s~*Y0-#WEj44k>IZuttNUVXt4eGTe@q2L<TZ|QqI
zO==Cj#vZ6^|A4yXp*oHdKabQ8<?!vXTB`-j6Sa0a>^7_8w?XEqdJGi_w5TVpgKN*!
zAODKR=jvq%&}&t1p}gP=b=@aue5o#=z-61dmp*3vO6~j~6x!9byI{9N{h}X4UaL8K
zSa_pOrrOO;i`sk@qFw5h6bSEDucI7XkNVU$`bD|V&p_0jJKhg49$d+X5b@;3`~tF#
zn_3N#{oI$&fE~mI?!(L+;QFiq*g>v20(zm``y(*xVO%P`FvGcqzu<2K_v{9|h~%cU
zfIG}tCeZ3GiaYoS8qwT06aYEGl~bMAQLgD5Ow=)M@gnFS=l-Nh!x*kFec|T>7q=TC
zvD{NCn26&hQ+VMdcY~5(r?^e!FcHrUp_0`EZgCeR6S+AQ?n>f1hXN&;o2`ZSr#YjA
zzG-)c8}9*_vs}YJ7-$MNp0>T`xHMWvrgE3EAezQ0>AMH#Ilpvp>D=E`*OtNEDujtl
zZXq2&&f>a?p^(ju<iX`|sV4MY-~@VMUgS1WB<>RTX93hNbED|}b%m2e(fyapl~U;M
zDtC`oqj{V_OQ?L#iQ+E>T)rMdE94R`fGgq{8TzhqzrKM&G3QD-|LdGRC5lTpIlbI&
zaLYzOvXqO>gJc;ey$JI+xgKZq-Qre}-E!{Jp}?%*yq)O&tK_amLcfZ;xDVtuH|z}N
z;tuyC)$H8mswk&$kNY(Z2CKQiB9Iy`vKuh9+;9ri)^SI_fx-LS2XuU;p39K}rGZ=i
z5605SEvCRp6PNP`3_jo@X#@3;yVV1QN1WN7?!U)eP9|iYVA`PH%)M;FL_Ot3%tT`g
zm!*am&$xjf0PQ)KOYgB(E}edZ7hD15?p|`mdT?#r<yA28ij&ayoZ7kUXn=KaUEQ$s
znsaP{Pj9%T@gSXC9}2^Cac9m!($dX^&xd{w7tjpRUM}Di#`~5lq(cC1ylOd!JO3@^
zemwY8DiibMtFUgCZsX$)f!od(+hAsQ@WF-PcJgD!!6z@?l}?;^^R_SHlMml^5q-P(
zQ*@xgm;X!wOh5kl5a{_^cq_^x2k>{Up>sF?Srshp;oB?VOdx-czNfL5-(!Ho`}nW^
zcVdkHY6DCJ@lA9bIharD0@?xIGY8}#?_LDZL;TnD5)a|Srb9iHcM8CahVg#%%ns+R
zs~{4=FPZ~Gk-TMdI|g%@zeLAwqWI~da3-2JxxoD+d_ovxj`CA$0dtK1Gzf~v`6eoo
zi{V2PfOdlKqHRVjzks%Cas00guE&%7JE`DK@k1xTi+KL#bYLd%jZPqmydeOMN&F}}
z|CP+ATIjicn%B?72+!~hRR4FDpG>cu6uyJv;^%lbDmG2!L&t-p@f~R}f1aOD+vRjV
z>Ilqd@WYRS%jBo-hC&t};R7z4AGHT0hp&!=!Uf*yPe@+mpD)8aUE-fCfuYO%5FPFP
zukhtmFOtizii5^g{wR?=K7Iid^LaDH3=4Rb7f2yrNFNR<;=3s?d5zbc252!qGYTlz
zc_eOd8}ec?xEp-@2N*;t{|hb2%lM8>aP1}^{u$J7@jrh7FUt8f$7uao!T(9e*DCp!
z^bo4zbFA^h-saPmK;{nrngi%velo3X@9`gH!(cU^NChS}d>e&9Yx#!n&{xOLUkvU(
zKZQ!N>iJ29P;cP>rqDwpzmQh_O?(~&J|FOJV&U3D-c(2Xzehax9TXq){&ce72|xcm
zm~ZCGXb=9B52y1hE&Mn=Og!U9Qmp?uKjH#JTKOm{)Of*vP4UZ@{CHX*wDD0Hz<$NY
zzW{0HohT93!Mn{z-)nyMJK)~%u5?*-^8WNpuypa0e}HH=-?S2~J-qKU_}$B2&H#DK
zJHLgZo3L38MR!5*84P*|zEaGkr?8l+Vz&wL!y&m{_#y}*JA`*>`MXp2a2*=G1XUNH
zy#;T&s(l2vPoTa__^U6b#8<dY@dQ7Mu!Cx<`~_Dv%m)Y?sYYVAFfjy;dxYa0Km&!N
z-$7%qFzg&e_6ggDViNWXvuW~!goPBT2^Q`SfWZSoWELzP6fBL<J0!fK&liLU1@FVB
zP$4E6ePKd31xHQ^gVv%kUa;6~fntIXw+W(&LO2DAlLW0Zd`lJ{QS$b*(Dz5!JtGXE
zHR4&Jo!*8i!h;=f^qjD@9<HSdhbfMqChVc|?(;$c)u5ycxwbHoA?T~2mnp1}fn*6m
zAHYJk5H%JeIl^C-UC_87?Dz?w7lpX10KFtkDg}30==T8J6=Cnk@FG{Jy$-ai!eQFp
z<O$uBz{?j_Edy5|tQ`&PLSZg#{ECGAOF^y)Uj+lDSZLma@m?36(>+omOmc?84Z#?N
z;g$-%7wG;g6D&&T-xSmr;M6TaN5PqL;iDReRtP1ujjR;1X#-a!G|^J?w(wIY8t(|N
zb203@!l92Kc~4k42bQXZ!xJD`Bgm*kw^kTN#Wr=qfMf9KzEDqL=6b=MPS!LC<2KVD
z0&Em&H$tXKD509j2f}AkbUqX=(yRHA;6YE~$AZQNjZXvveNwMkm_na%d@8J=gU>C(
zq-xB?GhxUxkmo|hSPZFENC<&zFNDrUa4&_33fOHEzPJePm0+OtXS?w6;&*WWbqLl}
z|Myxjj)3_$f|9BwI)x4mCZS7kos7nAf&Cr^dxUijAict@1+es1__`22xryJb!O+~r
zy&d2@#AI4kdW!Fd!qPTzHhs}yyXch*Zii@~8+NC7^$rH%B~D|}Xz><vDJ$qBw$USE
zm+1cl*uLV=bOrl~m)F7ze^Ev6`v9?ya)Y}?^ED{$5lw@k5Gc0N53^ScP5{{_&K!cq
z{i2EjwL#(^w1Wv2{RV(LApW`!A_v9lIT*wt@#IuYP>4lrnuMtd6)T+3876iX!(h00
zZ4YE3#Au4ZM~bNwoj5FR*Mmff=?x&!;+v!J;)obS`>>;;bOcNs6OYD#J1(*Z&=(`7
ztbqCnF>Dc_V@1zGkT@~10Fo!g;dHB<5-lB#K#Lb`X%Uei77qfKC?2O=YLfWpFK{MV
zRMH;{J1utggUA_iDcufd#hkCum?9paYwnzQS&PP0@uybkrHRo8AbDOqLy`M*(V1#b
zGQ@uLSkDyC(5z>PB7F%rTfAwZ{cetUa07h1AkH6$&WmC{x@9hjBh$fM7SAk$PglgT
zpQABXJpV61uZlDFU}$;bAB3GRp1uu~0`UlCND9ScbU?01bfXv0HL-vLO0mdM=-|4z
z#tP~sVwDX>c0=qPObMb=agG`0%S2m$keg!o0W{tcld562TwFI7jTNG$KVT|FXDUmr
z!X<#g+!kljj^K_MFbQaP#WCj~c~2}m1xwXp^c0w{5r6Lky;`wt0DP(w-8m@S7uPvq
zEcN2d0{RedgLqJc!A3EUwt-EeF&mu^!~{ybKNOG9WBQS(xd`%D?4eq_C!)p?lFj1#
zrQn{5uJthAA_mct;F&nV4hEl#by?tA#dVt@`9ch)HONcx744kb#FjmPekJPgS$d1K
zT^#-res_qEDN_4dbiV@bjd+48<~v0Vow4i^ugpMSw^%S2pgrP~br9(lW6oosZ^cU+
zA>yW)GYTHMYnIWX#Y5vf1DvPkHl0q~rs<|H?(EZ?rv2)E&4O<91!;bzdTvXwW{E2_
z4ru23qw}Dq<$G`;n$@SE5vs|(2AMETE$uzRHS;C|EkeU<z(s0q9s+k*vvM^QqBJYt
zhfmR(NFTU;L^Fsmk812@K=PPIPZ8GRnmaQ<Vl?y8K~8Aw=}c#=MdOQozBEpg|0$;J
zq-H3^i%)41Xh{&SX`xg_qGp^sG?FxDs0KP&(>eqSr!^%5A$dk)PpPZ38j%v%DVo7L
z%+oo|pvfSqnqPi{`7})+#b3^AN~q#CU9*$6E*YBHW}swhEQ)w^W@*xXLua<8%NmzS
zj^-oU++EN-8jG9cq6TG$xE(ZAbhP`jrspdR`-)};73Jn?ejWrbu4=ky$CjtDP{m)q
z=3W>i3pDYa_<agB>*)(6MVh}dfq6~y!$O!Z)+i`6dtEciQUjP0jeiNq4NYP@T1z#d
z`=MW^iE4xBP0hg!kXxER=`3rxrd|Wd3QgWYNLFgvx<INla@v^R*3{7G?`Zy^q~Kjm
z={Ai1o+gfJud6ka&jYhY^Kb&VTFrn0VAg4F8!7&IUz1EF=Rn>Lv<A(E447!t<kLab
zCe0iP6d!1Qe2&J48dnN_J<|Mf8;y@O?~Q|{Cz|XiG&XBe_kldssNaR%7EKvFke_L4
z2EpKS&3{8dS~W2z;phv^#af8G)V#Nt>TlaL#sJLFE6wb?Kx@|wUk=d@&6+RZ;%m+E
zZ(;Y1CZCp!otlm30otVzM?$1q^W8L{^=Ov)L$X(M{1ZsN)$9_1?WR42su8KXws$oY
zJhTn8+wjz$`w84OZE8I9wrk~2==(c6w5zBreW&&&`R1j~pb`#m?fOW7`e>&S=q_zh
z2lRcl$2!pHr{&I~(O(-!FY^HHdMfDHt@S8{$R6!zibDo!Qz?VISL;ZT`+eHVn}FW0
zy-k%TLE3ckFj(8i1;lbdJ7FwFe^47d4El$({pg%*h&Fx<U_!N9Cxe7(-<u7XaBa_6
zXhdj*UMNIrGw237ti3P|V~W!5p@S#U+NBDJ9MLZO2#rUzu|6QjwEs~Y<GA+TE^sm0
z(x2h)39T!A?Kak;H6;NpPP>_+S0}am=sk2wJ2(gq$7@f14vhqD*MIn76SbAwA(EuE
z8ituo*8cV(ES=U0N$5MHeW66(S*`VNP*2f57z~kf+TcKVn5vC^3ocFjE`=P=Ys>ay
ze$%zp{orqg*78~oH!`)WB4IE~d!4c%+1epZa4|<aou=)AHm?R=T+}*e0qu(RK?k^8
zZS53D=4tOwgu#4m{05jW(8}7NSEyY>#q>qm{2}POrWN+X!(weTt^BTQuf##5M7ui}
z>Nm7|EOf1xY6lHQYniqw738Kifr2ErwC(hAE7z7$iA;qyH5M?H+JD~#SEbFDfV-`o
z5{1Fs(OzGL#(P@lgP4+P?UMe`tI=+9hEKKH&3}Q^X{SC1^nLA$yU?rG2B;v}ppDhj
zy17x?L(%dkZCEaxd7%B9N|7FFm(gE>exyBa4HJ*GwTqztMElVOxYn$_k^%BmYvl>a
z7VT47Q$N#w{UykA?Q+`mztCn=>iDI064g$$X~$Ak<tuG5U2E-HGsSB=w6FTm`|q_j
zAR3)-w28Do>C}D~3$9D6qeA~~ZAB-z9&OS*DE4Y+QCaF+?QfsKlAEr_4KVJyO|*RV
z&{a~z(^D6>8-3e!#m-RQt_!NbkG4bCe<LJ!>Ov(D@zNQh;FGs*!xDP``RLY_LVuS|
z-GaIB)!jc04L{wyiO}%ZWz!c20(9g4w=L2cYoWMDS3C@jfx4Nr&e*GaF%ur{)0L>;
z{eInVl;aE1aZ?}?ted<RjR$nTRH$=MxAZt959z{8AR)SUsB**-s*9$JEljs&2Ie_j
z7eLXC2%SJXf=JyLR7!DJXQYFSQM&3`FdwZenG5cS&WGv?kLpTjOviLrsA~AQZVA=v
z$LRVL!tM!Oz!-3`y480;;&j(P#gI<wE}REBrSlvM5^vF!*rGE*H=nM+MBQRqwkPR6
zI}VbpbEXov(>ixAm^h=09uDrTE`ZLUr|9fEVd9)FuM8wrcU*u^X}TqJR^z;m&BO@P
zb(S1JXXwUO0XkE6{CDVO=}JDt$g*_<6VRBWvnXg0e?hmn5ZD)WE7~womvoDZAbMFB
zTL5xJH#8M}xw;QcAXjx;q?q75-H#_R`h49#bfmmM_hAOSDAZLmP$<%kaRqlxrwxZl
zvF_7{uykFw`3;~;bbcR0;fBuR7+fpW{bQke$}-*9t8n<H?$K1}-_lK^7)`nEM>_3S
zp>y~LeU-XZR5o3uduaf7TQ?SOYUv$a`9heut2?+5lJ|7kl#i~~wf93~jqdTckgU}W
zr{A?s=Q<6I_jP_6=+)~M{DXOF(8av>zxz*DvILXRs@r!NPQB0to`c3qU9cydY10**
z26?6HPY=&_osteab?APk73XW6ITzl)(Jg2P*QtB-2_(C8h54}5ty@F&Iz752v@7e?
zt$B{VQ%>XFg=D-_JrxQhIwgNc-(O93vP?tgX{X1u?LFf(_%U2O>ol_pjVVq)(#9{<
zNnMP=oOcpC(U|TO5(<$_r(KjE%5vI78P05{&XM$sIt~8-+y$pUPeAXY(+^bJa>;4d
zLy*f(JLq!0;uO0K>Q|lCc2NCUp3|c;c$4q+W(s5qo%~HuEOJ^#QP^uvi>P|2*lEgQ
zXk2$Hpb&bA)3vFXpc_s@-=eS7={`kT%bW(&O82Id2PGVDIbG=iSMH=72e&JnKBjz0
zrPIs`G*&t7qaE9Ar>|c_&vM79i(XQ9o%)@J-}jt;aD!;I(|uZ~*ElsrqOsPgq!K<g
zIxS9wqYs^`1#pj?R=x|#$4;NoCqSP#WmCw%*-1-F<EKuaI^&mYamr1G!ZW8$t039x
zw0t$dUO34qwDZ!*M0N9R7N@!?aO0JeJQp(UPRr@AREN{u=@5PGRO3m%uhaVmh;}-y
zc?!E-PA3PWvD<0MO_=C$>QAq_UMIuX(0l7t`Xf->^aH3;&0R0~27MlSZ93FF^=l}M
zvQ6)>13qon^VSgAp||Xc1?WzFDiv3I=`%|p>aFKyV-!C60W~nOOK+c#MqmAQ6$a|3
z?@Nm<e|-ckhywKbyU^RMuiX#OK>fkHXxyvMrcZV3)At_+vR{8M1Qvqy!zgJRtltz0
zkpucFdaE4Nms*@K&_nvjGXM?IU!(L#sQ&!`D2C~?DD)SuUo;dZBJ?52a3)f}ncnG#
z^#OFTMCn6xAV>6nv;yU*-ewENdrUt{1BK)IvaOhs82v5^N5<-Zrs{!{`Y-9}aZ2B&
zhoJ=h;D0TkiTZE%qBBWv)dIW8`W(7fPU}Co4oheBZyaGFMUR4AJnr<>lu%C9Pk$d=
zn*ITWo6qZ?r@;GkeOfR)%+Nogn0coD68$1s`jJa9`fU9SJCGdxkv<T)pwFP_#6|t$
zAgVvRq+fIiqL=kgGtqiQ@BTGLk*l|!3ec<iX^lY3(?5)Ye!hM^1zrmEQ6E5|NS{ub
zw`+QZBL-2dZ=+D>bv;M1>k|FPJSO3Weo7Y_JN3)k;Py^uSBlkpJI7Io)5lpjLh;XF
z=P5=E=8*Fuipz&NPp05?q;vE8(2sUr)d7Ps&MEYDj1$gZ_JWIb?w$n6IOm_0uyoRy
zzYNe*&a>yhi+E=bdhaGU+fdC_qVpG2wwmPJFA^4#ofpxe_0!JXG}~vK-=|75%US2e
zvjKX}c}O(Ptn;#8(R$Ij4{d!eIS2NG;&tbQ0HBpPJKJE`H=JXrOt;jzh}KnQ&RYWE
z%uVM-J264GoSzN{DR-`<cVmUKBp2$H&aZaBLY4EJD{$tvbBPQncbp~k1)94S=ZN2-
zanHHj08;Ioe+I2J&cBa@Vy*L>-SDZ-`GaPdxbGZA3+4vrrGtUp==@1G&^%o}`V5WR
zT*7G)u-#>=H}rP6+)4&msEheOno*Z`AAk#Y=}$}f2p3I1n2&V1`Um<ByI5xYfjNnG
z@urRP5f_$DuO4%GUIUl}m&ZDoNOal$7UNBFndE}LWS8O-kUZ`3E5#$uxHPnZJL~e#
z0eF$(qAG%kY!?kB^K)FhlhAj;W&Zadg)Z!6fEBsSoDFi#rGe6q#V)xPHT*7d`G!(%
zr7o*!Z&~K@3mvhjb~!=!eT~a?+OF5S++PimI+u+xuvG6dZ$4leT=2BRL(HX{lI!g*
zC0ilc;S$&f+-sLXIrx3vxWv=rxy$8v5E{E(RCK1I$K`7(Z0L2-ZKe00o8c5iHQf#0
zzKb8-!_aJk7oLXMKIq$KIItXKyI~J~mv@K3jsm7$hM#C*;%&He55&i?D+q(xWyqTZ
zw|x!Y4*`mwVc;HE@;BTFfcXG}mg@BO7?gC21sXo@LEm0Oei-E+_8BC!LD+9V^cD{)
z!|rb(8f@6zA3hy0tnfkKA;ZT%V`w3UwQlr_8s5aAFWj)5g4V|jRq^OMZul_{mQENR
zeu|;R8rCjF-$_H~VsP<>wX`!%FubI){zL;$i-#nG4iSHRf50$)EILmcV(2Mw#_)GF
zTs&(KsT459FftS5oFOS1XsL$&n=lD!hL0W5m~JS41G|?E)97J+#o+Z8>bZtt!{Gf@
z!xPF*=NZ0lM`OO>EG@DM3?^FY6&Viy36yIF<{J7e#fI{?=qxvUumz;Tu$SVlHHO<%
z&{1o6H65<i8CKHH`o2M_fJVJxh${>>7_@5iH5xouVuG3s)hD6;z%cU))E^o=7C`-x
z!Ojbfj}2+-K%N)|(=pd(!xndVvHRWKRuYVYe*b|pP5|kH5BB2!A1RN+IZq~?ZjWuu
zdT*#~XLdZHAD{WD44ONcwf^9|n5T!J>&={{ca9I^K=p~c7;h9$Scfnxu(X$+Wlm55
zSqf7|F@SSS`y%+3%ABE#CXHEf7TkFYvx#cA(wXrQkjY?vX$Hw;?6*TEi<xb~*s_@e
z^nA}@E>ptg0yA<dL@qLl<KQkav2<MaGP8`bY=z7(xLB<pFvDqYyN#V<OWw2JQ@!mD
z_TDgv>|`Tu0nCft*ai`A))GqPcRp-|lH6y<oCEP?e;W@CKenBMr2g!LFenDFeZK_S
zZgwtJ80}%*vf)J_I}RZx>j-u&(jeA1*;oa*9g^`zpm<3fvH!H*Bl&zIrZPx!eH8o+
zkz~(<y+q0L*EIWd{eAUw7yw5Npn|6{bFM)4>#M0~88`4YEX;DF(wGHrhvWY%eXl}i
zeFI&KuHz>_#*10niW%C)>~)3qImVY33>TSS@y#3pm+}WEqPthZj)m>Fl8|rUmz&k}
zA{vO*&?UgM?6Deh9PDA)Hacn(C0j*li)h)}Q~(~4ZKB8<N~T!2^+0v84VWz|_wDF=
zr3!Kc=~jt5K|CGCd;@QN941mp+8&2)3hEtj=-B`+!eQibU><Y0wFQQbJ9I9D7cmZv
zhoE=D;*dvS@mPnowA_tz;MQYUCmp(;1MQT9(F^+V4hdB7oZztTD!e%3Ff<;L=?-qC
zAQv5$djc)r;RVG8OB}vl2K6e3Clk<j+o7=pD0dussJ!m3!%tIT{+`3<ULY+FX%tj{
z=3wc54feUifI|>%b?{FG_rhULA`HHCIFt$OHiwMgVfU58>d&Cj?(ni4*c}dwX=ra8
z<k!J<IwXffq{|`c4H~;0won|q$HA4B$-NF=jKo~Lb*TCQ&~A<?k3ifVo#P?t;W)>V
z0(Pfk%vxCTa!jS4!rO7lJ}CM)J|6?@U5;+{;PyD`>GWTqqpvpxy4Uf>J^Whx9N(#j
z-TjVY1JI5*9(_zR>!_yJe5~V?1}G#sE}91OXB<cQV}R+7UagS4>)1rar}rHH?WOfs
zjiXZ{NUdX$5v1O+JQo@$+@k%{8%Ko#if-zDPB7@JzPAYm{nUNcuyj!Uj4~UM>V%bW
z`?z|@2=v9P{pf7)S@q<9U@1dA&li%H)Hf*4SD@a#2GBRu!<Is_QvINw;tw_ISrm6{
zQkPOZ`>Fc(ZLr&>zCyP}m-^XJnkcT{br5gv>S$Q<;rdb(Wf$j`1{h!N9g67sarLyx
z@aLY>Y5V|gM=U09H@BVsveX`~<`P5#xvlTP-@V);N;mA|x=|BtK?%{+;ZO|Xcp6$T
zS8M?G0ZyQ*#3NkE2pBxdO_Kxd7#G@01Lb;U@Gyppn~cU2+|rRS5zEQf!239^bPljj
za>>mgr?@+`fQjcWe1$no;O0|IGLfsH@KO?29uIq#WNtH+YMtgT*u%xM+=g=yP2p@m
zg%{^I)(^u@<y<L6oyOT80y)pUqCcjQ&e_qHJ%g*Kfo5_&^!mu+-lYghHuu~YmU1{f
zW&JO3&6JD3$m!eBc!@KA2))Z(aXjpmSh&<;jH!Yf;0Nq#u8V5Q8o7Z3;bJpaLseBT
zx%W?_v5SlP1K8c%*+-D<;dcB0{a!9YgfnlsowQ4K<0oVR+m}xiA>zjmr`Uu)f6oi*
z0sQahfVrFhovO_D@E7z@*vs1-^@CIU_>sY%-(~cc9Zk?b%$GR<JBm+=0vF9EE1_|O
z|A<~6NBL3-K#%e9kD-5@51)_57=E-A*s=WJJb=aVBQv3JlJ}yjs8f71m3GDR*;Fi)
zz;n-lnaD3$3zEd2xexX8{D6-!vUI+~LJ!_7K7o#xWb;1~Dd0_hfGOlNpF{K-e`FLC
zi}}+N!By}D9|N?KFQBadZ9YF8>Ua2sbW=9)v&O@jM!uO=aZP+5irYWnU0CQn<TFFz
z?<4*aMK~VwO}9aw@LN;qZfxd*={^0Fccs&REquK*G@kM2)<gd}|5*;WR^C8m<}Y~p
zPQbk6KYI<IUh(t1(b&#^{X3?+gI~WE+-v@CN|e9h9lym0JNZAy(=W-(!swUeFNMIv
z9^RJLu)X}cCi)vkZ+R<P5xWTky`bnWl;uOlLkOe_dQV}j3g)*7Ij_;@Cmdf3G=E{<
zSSSPtA2&d9w=g3DXo13E%CPShDh15UK4I+uIJ#dL69l_a!di-eMGH?z<cRQ&706Mc
z^98*Pj|uj4BICI5g4SO#!W{|>oe;dcp%^Q)z6M&HurLsPCxxrAAg6?OTcE`Y%idt}
z5`-UVx0@(P=(BN2Lg!(KoEA2F0`rVe{{-Aw;Q_r;Q-n>_cTQ03#gI~k)0C38qzQKP
z8ayv32f<RhVBL()3?Y(IubG143cSb?(l&$37FN+Onj<*UNr4N3X&4$W3Of1{(RE>d
z9L$#pK6Ko$RM>VMdS$}8VQ4HD(g#7LLO4uQ`Bd;I!F06<DRjW7%OVU9Lu<Ftk4iRr
zgcv$b(<}VF3XN}t1A)+Y69ayPU3XEo0PcH;E-zu%Q`FGgbep*5Fbr-NCs1r~hv>Qh
zeLKbaRhVEe@f$j?;4Ow+hPsb<<UBZEaR;q?{KN?pK>S6EEB(oq0C6MLo9!0w{R;DY
zL{@|O3KW}V;P#4>D9p4^JQ{*A?H50!ReF%PFcn;|xHBA}2SlqYP(LW<&~d>-;;a;4
zhlmxFl8+H(v~D^f{zswXSn<tfaB<>IN~E3?M_cHl8mC0VXV6a&XUox=D30g@pOVCd
zv<FQVKko*2TFgs;r8A=X6<{Ji38K=l<WK(cgfpi<X_cVSYw(-BAeEoG(}(fuK9xSf
z%=8R>P4S1`q3a9L7&vSv?Pd-P`;eYY2Zya5Z2@-3u&-VK?aZ)cv_iZ*Y#r5fUKzHM
z>H&*}>FKfaU|2IPx?@J@KcrJg_-}O#<-`BfPzCW{H|e7Re-9mvv8*}K7a;4IS}1P_
z&jkF&aotdLWBh&rELP$&w0STGsoLI$v25!Dm|cvXgB3rfzYK8unUhqJAH<B`iXn$H
z&uH5a!TcyfKayER)kiVR5DN31VE*j~y;vr2Ev71t$rugL(@gs{8V*xWmqrF790Qlh
zM6CqLVuD4GY-Z#kkbGvAh0@do%m7C?UC5+&!C(<HRtC^=X6NTXt6(xHR$0kZAB2f2
zrg$$J>zH&(=G<po4`JZ-%xH@JH87b!!NW$z<`giSm}``)d%&D@0rW#AWDE>GVusy7
zUn`@cQztK&@@A?(eaXzGP){4<M47Z#jAtKM>S2y<fMPG>IT;i5mRZ^X4L5c>y@B1?
zoJur$ut#W7;>otrmnycg8wq7QyPI}bJ6KQJjqYTZ-Gpmi?68f1_GZ10K*WcAk`1zp
z{n&$^f4=MhDm?XLo17r(&)Ut0-vR7*7eRKjE%e0O!_J-uE|5Jzi-W!FsUbky$NKyN
zh5hWqIS>hA$5Y)vFq^gueFxa~H863I4HySU53#paKqQ1+Uk;x_+3hnhhhgk5h&NfJ
z;jC#D6pyjtlypAMs_h|~z`lDDlaR=+X@y1->rDsSl39F20*@*-l_DVN>`01WWUwoO
zp^(W2c)@NKJBaEea@nq(nCGkP-#4I_$CgllE1#Xd9qI+F`%1W0$W~CvilvC%*9`M_
z*n3pyaF=bQh1NZGNjMa%*{76buVcS@3&jT3b}=*>*-Nw!Yhqu~Nq`6J=53gShwQ&}
z%KQ=gJ-uKav#)scJz>vLs?SZ*cOMjXN`9f^UjC8?^U%0oGH(GILoJdIeuBYh$;)*x
z5hs~P^|~h|g%?0hNm^IHi+G9eVsHtP9Lg9bN>(`I(#wzpH^W4xB&I(avn1K$;aaxD
zRSsuzBvyUUcR_M%Jh)4eCJ$J+EZItNi7S#%=7Qu($|xOpRbn}`1K4?z^>3knQ{qw&
zFYZXboC47Ml7y4!dnBp$MB{VGXGPHHkes3zT(4y4CMfK%3cG{p-f8uWRwG_k?*@SL
zwldK%dLJtl?aX&s1<k@Be62Pw1$V&8)(t2Jt>)5m<B*lwB4WNmtkV7iTBy|@ltc=%
z`e_{+!>tA#fcueF$$g-4*lLRo*ilviR2Cg=^`|2gj#y2n-TYCj;7N1^S&gA8gk&ox
z1N=?168;0pu~Pd&@2Zt&J-jHk;%5T$meo+Y#_w7U`hd3E^;XKE(0^hTI~6j`R!JXX
zhMrn|Hw20;R&Ra-%rmQ^O&H;GtE_inx7EtyC}3V#&Da3-UMt0Pc=6WieOk}DNe8BY
zxJ%tnL%~DZFA>n5(r@oUVViVlEG%r7`gg;^PU*ZDy8pbShv|*xEnQ4!G<>9q-+}Cs
z4yN3huk`c|^!Z62X268Mw4ni9uyk`AL=H&*pz}2crOo#sc}UvxIs6Tgo=>2ul$t5v
z8zxoJVkQE`<&ccTAHD<1VQFSDO{H`J&fHj}(b75j@aBkg#&>`@Dy^g>Y`pY9e>5iG
zL+Buh(nYT5OOoFF2x!UDO_TvRE$s<}i8InoZ5Y#8sk9s;JSR=0&)cU;*U=6#O<F|x
zrSsCgjj)SvV=TeUWJn)h0a&I~_8S^4S<*hc0drN__5&>CNuQ)cBVYO@6{i(Q6R8NP
zP`V=&q(~~z;^LZgeiKBBrQ`hY8(x=Ap%mo}>GyUpSSr0X8Yaq+x5XfCN{3Uz^OkfY
z{Z;L9sZ$-)E2Ljg_N7w#4JBHtEYc^(fZZhBI1S{1bmDZNJ(RvH0{fBlQXvNOSlW|;
zz9-U4eSrN`y1^UzEz+;fLh_lEqZROTsU2Njt<o(jkQdT5NwE7?>P&@AZq~yR0p@N!
zt`_PZ)~nCJ3s39!($Kff+7j|T^tW3VG-32Rt!*Yl)XO@Ghm5zi;V*DL)|2U*9J{RF
z83IsW>(xHs{HzbtCijr_{_g-2VqIYaF4X!sR+Q2(>j1h9!>ygBfs3%7L65>nYX{13
z9=5)jhp|LkkA4E^Bi4N^Bf%cE*3t&}n6;e|V>)h~Jqw*N*7w>m&nK*d?m{uvI^GeJ
zc+vXKR?PDy>v~GI6<IGVgZI_es|SFqvF=Z+ksj-SD%g#YjkpT1%d+@^0J|cS?ndKX
znO7?sYh(ippzv7cG=c8FR@pZfp!ixgI}d1YWOdn)@wN#rgNBdIPD*|6vq__`*hbjY
z(WWiQM&$yL44aUbaOSejSgLlsYqNw-+qBw@zXZ&k@`set*(bk23xp{7?ji6ZQEsFV
z`dRrOqal(n51v6^!zhq9Zh_1$h4U9^^;dkI11>=EHC^kw6~!)q2~=EO0f+Z0hDl*!
zzv3QUdO-?}73>~Tyrz#mgeZEcWF=Jb=O~DTD^jVNJ3?V}hQVmXM0%1QQJnb>dPfyj
zv@D8I$Q<df5yUAX-Ow4YnC1<|Bt<|8e$ms4>V=q+Gm1U_=u1(QWdrS;!sjcvmZ~VH
z>ncq#i*E5k#o19H*A)F5;Y^8Q{SW9XQ{>%;iCYQ{EjlX{oo?`=N-_R7fZbJGql>go
z@fUqm#^PZ+kgBG(+3x9p#tz&46m<8p{hJDd{cT(5>9yN-OAE+8+XLT2Kgc%nV{iv;
zJ?Lc|Y8#=a_cs0$*1F>Vv+5{QH2aMi4$m3c2C%u>x%l_IItnz+|NTqoE_g+c--R!5
z63-(2bzmh>7x`D9WAUtHm|dcw^RG(}uZCa08CKx`%cADP*WaseVWi6s(AIV3WJ(H}
zAE#p|>vz%2ZCHOD2pc!t!@pg77XowhLRxJ7_uFLrd+St6v|H?GI^CIN6fN^$5^^XT
z=E-cI1x-IDyAIy^GoAGK4`8N$0d6<*#SxH$Oz>Y2Im8qnLthB9bvZ_wzyzO!SLc|+
z6o1cVj<#Y@SD87q3ck*S7Rdf@S^@{+9})QI7EDL7+9Kc`W|vcHGm4#PX@G7t8^J&~
zhMjl-@F&=8`YL2R>#D)v5?CV(E|IOEO3JhBrf<-g!nW)HImZSTfTXhb#{n&q%_xGC
zS!_BLo@TQx6jQs*2CsqnE9`$%WtGcLY{QfkvU~|Ji`cc_TA*=*eL}C%Qr4;yu9vZn
zv}n4?9-a%CDz?QF+->$!HMl$MN+Y;hcHks%b?iJ^b=+tBegyS;_GLHJ8`$rvVD}Nb
z=2t*JW)DzV<ui81O*FQ#hf|>Nik;F4^>+3>SE>f+V)3CiS|+8_lkKJa{qvZMSBf~~
zp#FDV^)hGAL-{T99?gy$J8CmraA%L5z(_pU3#9AG4x=x_Y-5#;AlupQ&(XJoy+oyd
zJK4EgFdts*e%fYxvjqj{^I;Vfzud)I_V$G<zU&PuoAG1a=mqJ|u9U))09Kp^nS<=B
z@1S^yy_AB!5Vo=y&KzgI{SaQ9VEYWP{r_GHi6fvhdsY<S=48>$JJ(SQXXgDl5ccNx
zrw#mqW92|v_(um2e!V>o|6XJXrxLTp;#HVmGCC3VmYV(q@^61`g~GBMv>X3@66Nog
zhtQ^U#l8FZ_sXF0fLJBTfq^w!C&8GJrN`X{YkD<q%veT~!HmhL$zZ&wUV8`g^%AHA
zFvpg_-fm{C41If;RLfF;1~OOXgAHN+q>ATICfXh(jQNK0cM;6?5O7h<mt^KB^SuZX
z!*By&E{=H_1oe1kZ$8|-&cu)pCCtB6dU1mp`U;jxnT1sNT*hepz*RD(-$MN!BTmOO
z-DfiDEufE?Mem{W6%$G26`f4*BgphHix&g!Ei-Kv^xfI5U%>qccIHJirmz!`()j-m
z9VtCv)0ptDpmUxH42G}i%#!yo=NZgjI`m~Sv#8E6iy1ZujoD0X5`c0T745O}8Ox}J
z@SuR%QVRV-CXp_VB4#HgxUMnZP-8KZ)dTOYGyJIkjjoh}0`*J~MW-4VBNhHMG6Sg`
zr-d<6!0s6{ndbO4vz(sxZx}y{Y<RF!(&2?CTSja7ZLIeWDEP6DEmS@1&q~~2H-Md{
zgy;eG{ymsK$W{hoau2b-^xe5=);$k)kFaeN6hF$|d<C>)tSjAz39LIk9uwI_Doaaa
zuTZ)0c~(&lOX+NZ2I?6sUj6hK7}1HwTsE}~3Rl@r{OSFh$G#zhH`rfIz%FIao1tIE
ze)Ts-c$58>Ha7Rz#kJ_GX5D(wSHo)QO08vi2_~qHEg1pwm>qN!eNWg?^m=G!uTpsE
zDLZ^VNDJ#tTd!yAi472W&Zbe$tCgLxh3@|stcnt2FWDJy0NTbj&~E7!oB1j1wzKQ9
z;93XU-~jhuvl%HE?;Cc`bToFdetm$}#jc_1(rz|l2^4zR6srC5m29?y!Xe4Ow9Gmz
z`7sVY#Ylc3XObju!a=S`4u;#{{Zl15X@NISB@_QctGm_ubfAS<3I75+!7BS_IFn;l
zMm0&-t-Qm~SZ(FDj{LQ{pM=IPtB;ufyB15NUr@sAwlwzv&6PCeCID-taa+OFONDb#
zYLZ4oL*%jaTnB8nNaYq<N4=1G&{?Vusf@}7I;DFDfqN^x`UOO{S<65BKYZSiDlF#a
z&}MZ0YFi9*;m;oeX3^y(fL^jJ4ZW)-Ct<*==g-6cP4Ck-!5l@^$?M1Hfw|$=GW_3-
z+4dC5?o53-Wh1;9p3+-BOh1a~1Ts->z~9U45;4{gW>`D8P-glf^c`W8l<+vps42a9
zig`wH;&^705$Xxd9S3mdnC38$RAw%{Dbtt-$Dn?m8Da&y=}g{mxRt?d*at3?`Qa{A
zgJdy<-jK;=1{(mH!+hF^!CYWiS`}Pmo}7f;OH7Lo>|SQF{{!|FX8Ue%xy(Cu;I1+q
z+aQ_8j0yv2J~QGwkOF2uo!TvAiYV+`#5mAJbdBky{B1GwmNH-08F?M_EG5j7YP8;9
zYzKfXWp+2incK{e3{2e}=3k1B-DQ+hVDKJOeuaL1=I;ON?YhIFO0s=d)xEbHX%ta0
zJB~RMMKR5&7)CM77{-7B6%|Dc!03!RZ2&<<1r@IXA|ggmK|#!700mJ@1QSV7q7lsD
z{SM>%W54(I?S8x8KE9?;SDjdOZ&x_y)a_P~mdg^-LGqM6oq|#k%b?9_F)ND%dkM2A
z?_eoA<Ob1Y>}(%MDQ5^t(jZZnMt~T8As)hx8F)_`NRIP~l)`Y5Zz1>kX<ly=NE3P8
zov6IXf0~KLB=ch0@u%>^^h<?lJcb;u>D;6T#N6iPQ^9bLZ}11nBkpntrY#eG2Ps(s
zuR0g<pfi*^1_Es7G1tHv#y3Ea0b^=V38=$)1RcfR$&=5cJrP`?K;$mor5Z|+eBwxG
z+08YW?J(-}9s(_U`ON_E?c;%zP_>_TZ3u<~+=cRXqImNWsEp=~$mD~3Y!)aF@i1Br
z9_E|7Ls1N0Ldi>pSRNS$<PqM4cGd~Jayd$geEu6~I?q>+gU}SNr*w-{KBXRvxyl2L
z!Jo!Gr-31ZZ#ja>Og@!X-&s8H4NBR3>=p3kakrn*(0ty3w%Y~Vfzm1;@wedskNF^S
z$rl><>a{>V;R}y~@hQ*Af>A}BQ7UmU|B<d=2~Q$laVdXCr=QEXfd=Vv{@50j&$#Vd
z;GXl3j{x5CHnhBb$8#^k-uL`C-9#UF9&PGA@^~}Y`-zWMpy)H#F9zioZYWL!a+T=h
z3ZcHD1^JXVh<AEa28cNF6>k-04k&FC5elU36oub`Bto1!42A<@<zd(qB_7hc`KY)_
zk(W3z(ioJdMMgB(&xr2i7EBU-AD}JCV#g@pE{jR&pv2=#4UT{}MJa^@Ziz)TVcTud
zn?}+*;@Vo^GQ{o?z-5Yk!O)u}+Lb_4wkV+Mb64aZ1<5^8unET87k{>b><40RU)%x@
zg=a2Ea>OG_S;-X=P3n1~17%0&i+8ktdo0>qqWDjtI7gexCnAi|H4qDDqrD~K11*qB
zMR-Tx%7jBcC^1M=So4{v)Pet{Xw(~>_)2J|L-uRY^d|T|3-5ivEt9^Ofnm86j~p9$
zg|wDPR!Zp<j`5Z><eK%7SPacSe$tN7Fn_f)#{=g3OHZ3a=sHP92Oif;hv*L6AZ5@u
zCqS~?2V?e2qZfhXsC1@~`dP|K0Q)5=ihimwO<H#!m8Ftn0$pF(@)OkiDYF(pn7<N2
z4)*m*$y1PQQItm-eE))#>m?8xqBQb>rch-Axh1zN);9sdlu!jATq*hi21h8j$(I$W
z)S+C$JxU#0GDg{U8<htXW(T2BN_ISO(aLBI_zo%+>1g(0rE?lUj8aen5UY&y`L?pI
zy|OABaf}0P*~U7w2FtidcKAF#QiY*TSrkm2U^@yDCsrGa_vyZL5M#zl^3BfNzYw2Y
z6De(O!DBij=dqY_FFbqZ0qYgKAMd}F6{AfH%e?WvcnbwJz1dZ|n|)ZHa%fw}45@)=
z#Cld^5>#zqOQ_QWnBYJLvI+;ZY#aMP^Jp+zP2cbkcGn0uNhph}23^~kQV!8Eti?^p
zPGCtC9zVl^Xa#+d?T-gYVOMGYmCm~V24NZO`#kX7XTd=z6)?TQ92})=v>A+g!`8Qg
z-eugmD-;Iu9EvXP<YkCKSB;{zmkmQj082@R+(2d+1D<VcC8Y=kvwov-gM_d)jsT%d
z(-ka{tjj`B?q)B~032i{x6pt?toRlzILuztbRA=0v-SXaocYs1@e{0w&Rm>isgziK
zk$F+_z$LbtL1-G=MKi`VHhKuG$YgWK(U!#=r$SmT!+sB6FXnp?D)QNylW0HzGusH!
zQGCQAFhp}beP<5x{p%t65HFyC{V+GU)8;0Ik6nz~SU%tvfFpeE0kr8V*VD2-mz$3T
z{|+&Y!mHt;(MI5QiZS=0B0@B#Z`m$!XE0<(iZiaj?G`67)5&{;CEdw;#j+J3*(YXF
zm+TjP_QBo*;yguTHb}(=J0Jt3nzUyOly3Y46&t0DRM@mh5;5T4EbY;t6eJDzf$S|(
z3Kk8rDzV`(bgR^;IvBP|j+7}MEG?Q1y@=9vfovaT5gloZQp)E;?;)j&6G}&w?X*Ha
zrgWndp2wBGMl}AMR@TRX=B!dQ38h3O`Xop%D6QIo^o_Fl8A$!LDH%{7tsQ8A%FEiW
zMJT0e8(xAH8QLTEG|A#s%mZk9RL+-V!^)Rj?f~;Dd6yfwD)0G0ax?jg;L5)eq2$`%
z{Yt07`u=(cT{8Gy3n+J-P!BXiR{VgPp~tpB$*@|FA!E4zaoF^;XA?;OrT;#t8b4qy
zggVLAc%N{GVtf-fHpAyh(+coDd7cXlaJHcHzq0~{;PdPn6x;XMFdz1N`sRXWNq?+C
z4f4`$ZcyOEGMs^5#d2k^__Dzi5c6ZV&I7laEuIUmX!a%_g5uz+0Le*KuLYDQvQ^}2
zNoFJOf+3CB4FI^s(y4#4*^>dVH;3ixA*GOYtBz6`Yc&)Ntz;J-f$y_{4etihmHe3t
z7*}(z$Zt!Q+Di{ZOTXxD=!yP0bR&9k9oqetMbJZ2-m$DM5c84U?+u}!*!)tke`P~n
z;9@P~k;72Al5e*Gr8l>#LH*7H_d}5%_oYV^Z{ojXL-1y980Z9!gZ$}Q6wh#<BF$e{
zGM$@~%PpI$v5;|>zbuEudpwB}C-3v?^x&cgygJ4Ep774oLHU%=9E4H{Z(9JnO8MOg
zP(I_Sw0VBc4Fh1pd;WMZq<`Qm$OpSdEbLDH_w}O21<2kg8m~hmH;WS|!5Ab)^!YYO
z*J(?ut=B9*5|S!d0fnzCS=b)ve8b|i&`EFECi2m|V-pTkHQNjm9GY#K1fBl8=`e_0
z$IsF#H;DIq3+Y>UD(#$9-Xw<{KRb9P1x&;F!Z|4I<fEyhBKVt@&~$(|=>?%tJe(c`
z6V035LuDLa(+VW<ydSNE&+tAJ6+Fua)P>$;p7{|{F7wN2P?64KC^B?|_o4{RJsvRx
zl=pdH`>Osk-$U__hy3D5n3#iAB9OV<W<QX59NS@9yVW44Tmg@14Dg6suZD_Oe1;!d
z|C)~|1*qVY<Itu`-t#s1-f(-0^}XY+6rA|LH8k{o<T{!yR*K^8FwI*yQrd2~cx+Dn
zA0=+vgYld=ZVP0V7-$Jgb48O{Fs57t(;lx<B>oKCXR*35D1D@16uVZXx>KPdN=l_4
zh&U^~qIF%mw26Lq_K{@$3f=Wqy5|7X*2;x6Xa&g?O(85qF1!QE2)VfzG#K{DJ_kS(
zs@z931{40+cCc-S5<dhA!<Fsz!MI;JMFFuWC95|;w6cVpCx?{ZXkds{UeSYkjww?n
z!-@pu9)-+LD3?Oed8ZV+AHi^1QD;E!S>;Y$FeEB}QcUx_GMP@YUNk72zW0|D<F;T-
zQm%NTHboit864M?SF@r1x)L@X#-uC8(J=V7;!$1=MZ5+yr$yjE9Qni#H{7xV|DYGN
zKOCI?J2W`v(7B5tcjyZ|G&BV?!@Sx;>TvT`=%Jr2TS4tFmIhifj!63vg^`VB0zGOM
zITJ^>%S6qu3n<Jz=IS~$ZR`sU(c>P|`hNVRMG);|UJC5Q2Uf6gQvHsQGx;Q?Iyt{>
zh|g0tC4zElUMl2F8~X|pT-M)%iPLv^p=QPhO0=4(8({##^~w;C&U)G%pJzuE0PS{=
z?xi_)cTw-Id4ig`4Q4{kyl1p9nO{P)&VqV1@!8|jK)f$};0n=;OQ)ih%h{^sXonxm
z^M{N?hHnZ~;q_hNY*aLxpo6%U4Jfat(`tM2zgTa%0vUD(X}Qt2F->g!htghpO#BD1
zIZY>*?S$;}`0SEJXM?AY&W5G)meRI){+i$LdC{7^knnr8UU>hr8v^MV&%e_0WCQzy
z5*z~9)e$IdWBQ4ZzKiW{33H>ER6zdkqs;v_3_Hor4M1~GvBosmpJs2<V9puVxF@t+
zW{L{Y*O?&zl$mUqKX6%W>sU}eW^L+1ML0L5o%cT8hj!j^y#G*C#`8Vo{X51Vp94bz
z|Bap$m&iZ7hs+#)s0n@la=9br3T_j9C?_&lY@>aAi0I`HV<Lq!eeZV*XIj|p5&C>1
zjS?lI(F!F-SktEGy70LMl63Li2r%3bBi5jFN7QTvT!y$tiD{XlLjg)<VoC)RZIoip
z!is2VbyY;*u+-uuIF3rDCxDETUhf6zF{w1>+dTALe`9o6^HVtVTXhw0Ny#B-(p~9K
zdZtIdbSoa{XHu^gC_R_zS)*mk<@{5S<tNYTC^USnJjc~t!~Nws&WoU3?n0jbAUtFn
zmTi>{tKLFxh}<^_YQyB6Nw6hFu00G_>xMkp6n&U2w;;#!L-_)2qVtiq3I0O)@<}ih
z%ORAtUM>e><)XZhF9yT3jml}-GKDGSv{;W+40PIauVNeoa8UW)A9v7ErNukgds-Q6
zXa|}LiYGbSl9YHljd4Zs8w4?V%FU&ye4;eVL1mfZN*S}ym3HL#{iyVcf%-3s%_oTQ
z)*hizBS3qWq8MAW*3-}>+qCT{UpQ3zG7k!OYxBB6=00un=a3Sm4Ko2QR$Jsk^G}>M
zlNJvtT01)Am!@sI6gH)6^Jx>Dt!)qt+4r?OX;+b>?Ls@geC;L*<v!LXH-r^WwUa0!
z@LKEk5hQQ4!V?Uiv{#=4tk4ak<P;y>rU1zF({-TSiM4pDJQ&vN&b6caf3q(CIcQGk
zX48?dBwc-4;$`U`Q%d_i-Fr%~e56}D1#K$U&7<|=b6qSgnqTQ!c7TdX-A5JRovs6I
zO~2@3C78Y3=maevyp234gy3s*n=*?x8Tn>_Z@-a!)i`bxhQvMm8l92vEij%pa;pu6
zmy8xsF4Z+7c$RPr7;Tx3(rqI%N-TR|bRiL93XR<9o+~x7`3bm}Mn`g?qQYpgH5lF+
z&7%yT4@T|J0{7X-yC-nVs@aW3dskL#OM&-Q)w-QWBOVy1E{36o0^^m`vxUYcCx9$6
z?otb&)OZ+eQl1&#PXzx<<C^oJex=?q16ON}zG47?s+Y*m8=~(<-u@l>dgO`RrH`cn
zB3kdb8n_t!yj?IfPCuPIOULyK-BEc;zl>6AF6cc^0C&Zp4|@g18~WxHU%IRRl{UJ$
z`X0MLQ=ktoMP;FWe1BM2q}Q~DY(J9_THgDc)Y5=5z{JiB#%wl8i$&|Vns8dIgqrkB
z04~<VipIt`ldUOWNHF<+1ln@ZB#hj4#U>lcgI#H2*s~qTk0x$iQ0r4YbTCZxs~$^F
zd<v}YgvCzPm%h!S-WYf~R2_EcNGCm%PITZxv7nO<ie;$Hw-vo{Lm7-M8k~jRDalu0
zylZ6?<j<=+7M~ZbEQ7c|Bh0?dpW5&D(P^NDeOiO0^^AwOaP3dbLQ^|krs4k)H>Q&w
zPk6}~^iUahCI`-QuAd6rE8grgm@4^x8nfYW+6MW7V*N01hluTuzO5aH1k!vl{@yio
z#}toDST$8gj>0eE&n0N@a%s2$(yE%6#|l$48pMx=4~HEkET0xI@0fiHls>V%`B1Zx
zH!XmO)qI^Ec5UJ7=|_zsc>R$7j&$y%Ws3R8LC{%0l4AKS*9^jY`)ta0?Uzf2|8%=C
z-UmIg_%^&6YNu0F&%9F(-s`r(6hhW~J5TfNT+6p(CRl|_2zMxXocjC!I&@Mc!qAzr
zf)Uz!k4v<fjqd{+jxzs0q2Lr7I~WZ~WMgKKe>a6qob&CH)ND(>hB`sWm8j|!p7=Yu
zp}9vY$XcFzg2uFVa{#K{um=#=;o}?JM4fUeGGiIv5?JeIw2iUN@dnoJkBR7xt{2Ez
z(!HfE`mtyIyWeh<A+KmYooru~{~X9<^1KIg3mJk!_+&G1hw|Mm(Y@RG^8Ubu@x4Ex
zatHV7jZ!%8PSbfbccAV5K|X;-??e3FK4?0@5B>pFCwUGX<vGQFrH#UA-bR9G>~G$o
zv{lrb1?@*fW^3GkRh?zLgR)snf7%2p^Zpq5s#<?a^uCPlND^Cb0$dko4npfK!J9)t
zmiT-T#0BEbNK_Vz<9|YOsc2H=6&0sug8^BoHE{`irHGS|w?_JL0h+K*>fZ)@>!n&0
zdfs4==99BBKpN)>p@Gs&nmIR08^~e5Nm}&+jGLu4fglZ%Zteid7AdGHfGTD8$CcSC
zEu(GGHYuI%{9tK1?f60@zs*n)D%Bzv?{>-ZGo*w`lXe5QLpqIcjT|mjGz7^`$>2yw
zt0SZpry*vSbYwbcZp*#)1Kg35$;1q~=qpN@^7!{4$&xLTp*~wSqgnN?+&US!dvY4B
z@$Spf-vjqRHugj1LwNu>=5pmQ`rehuHT;2lAwNHcmVK5VzJR^U6kh`k`YV*jzCh+H
zd3z+t!OLn~9lTrT*F)dfRHIxDyC*cv+s~qGv~C~1qNazrJ$QQ#azuTvX_HX%gD-VW
zpX|D*?`!!Gln&P{fgSpRo}Ke^xgAuGPo@x@(-Csp&3<~ELSJs3$Xz{ebaODw@9hP}
z9!;O2#%o0qgf7}kPbB;O8SPU3_@1Wyr8CIawSqZP+JrZ|Pm3!bW;Yz{zHA%C>esM4
zG+(Y|No_#s&z}C}<m*UYo(=4l0){}=ja-z5O>D+Bh>2vE_M)41v##N2@*cKhHB|3q
z`*bjQAM2$><pGu*fyyZO7*L94Bd?-#hz)HIlDo|17!*EXJ5EE&Q?`zrV@0g;4^$Sj
zKx%9Wt2#hd%GxJ_y^Mu70C;X--jOil1^aRZjBi->D>T!OzghvI0es<Jn6`sklB;De
z-#ZOL&+?j-m-L92xRNH`o>tUFJd83Sp7TBDKvK#390AEk&bOlUiGL(-@k+7jE=at^
zsXHjG6%N}#5-1F_X@jy$L~ejJ$-?ajgkBa)dH{J{?Arj4E=F_&xFu5QcR?PA&lAw>
zhoU_e&+wJE*o6-MEbKqR?60E1JV;qC`9-0FS4f}6gVI}Cz7>`0r8PC6ccWCJYK<n1
zrYQC{Nj7YOiQA>xzOZeFRHF%uxgc?xK9i-be}E%Zs(TA0*CidfByUNR5@1ZGl=~H>
zd(t?11~QJ1CZe)X%AkSpiFD{agguo!o}jWwis=saV##JU7`{jyKST6aDZDS;0&>wR
z12|OKgjS5fvSBhnsBHZfO$(Rf_JBV^PG1U+J+k5iq5I{!579wU^4*(g_F;J^t!rZC
z?&N?!D)*#Z)C4>uACy<**dkD-$l4xYPn9nR0C!#9LS2$BKcL^vgx76B)zf(8C`WKS
zkQcOurFpW3qWAf7CZ&%S$PHG0n+j@FO;M)v%l<0=uT#`Nnv~>NR!sZ!I2Q0LEKgv+
z8d{?vC)v$EXaK>h<7}K2R4n}w;8v`n=i%MDS}-O=n>bTUeYR^Nj5SK<1@HhXb`KH4
zQMwHG#gWUd-Ebsbu^%pEjnb`+1@;2n7vc<^(u3zgLeE232PwT=yX!T|51tBWew>UH
z6s7loJGy2XrBCBem`?lNtBnJl4%sTu{RUcLp31`-U1+{HQGHB#H;caAoJNeqYlw|?
zU#}@HKRNW9WYx*avXj-{)H%&_^P1u6?%|}atH=AbT<Gd<V@-6OEIV0STH9E5wzjeA
zY-#7@Id`s`htm{ScZ*J))Yw|QiE*b+`1sdLy<x`9yIRa~o;uUj-9_{Nt=ZPX<9Cn$
zZ><jh;SL`3AC~_=FQ9s;HrM}4S`Gi;wsBrCr=$B^cbASX&Qn~ST-~R-c};V1n%cg-
zla*B`8{Cn9OW--vYt9s>-@3SToYQ{#Jg1q?3#Q@D^Q22`G0MYbfrrIZ=LK#HEgW1t
zW_!+^XW`joZb#3Vpq@L|-D2U~1+zWoIZt%~k$Xo^7Y|PlHLnhDX!rM+|1ocaA1$VM
zd02QkFYx@kCj1jp)Dz~s*1uy$cQWJOvcRV<ulw&<KuxHwO7-~9|I&T(PYy3Mnk4Az
z^ED-E)@@x4)wHvbq&CW_RxKe-2;(<B{<SNK+hvN^4Bs#BMZ%Z&(v;!qkC8^Q`s9>x
zGj;hEqgn~kgX9<c)yaco+l1r_IU!jMt&rRKE<L5-UyFYo{*4lro~kz9IN?Qdwfc2y
z4II&L(&*lfqxv<q?rd50H!7iJPPMh8)JcUVeG|%Uj0ZZYGrI{hwfMa-Pv{(A9NS(k
zv)Aj?+FD_npgV0`zoGi|yj)*>c2IAoCc1O28h%S_rcTI~bO~`;#{6qSN~S*Nh8kmI
z+%sYCUX$ZJRr5?<Tiqi>EA{OPV{<ikjI2#KS7<WCpzCa9-_gq6)+(X4OZ6brruMe>
zo$V}LZ0zi<Y^P3l?%K7hi&YmJODn4>)24N?b+PkJ@v4sh8VM<0rZvX5wZ!BBhppxp
zf|xN~3F<YPWdy5hG&>2_)Mzdwu$!jsP1t6&V~*)Cc1c}IAWgkS;Evij7vPgR2Y|Qm
zQP1X@4rM)5lRVUVsuS`|7xG5y)XY58j#OLbqt;vXBCteFB9NxmDFCQYT?l+q;{mws
zE>(F14mWkwBh>n<y9vapl>|nr{T^49f(SfT3kkTXoeKdrt3Cwc)C>X-)Rs>G9;;pi
zoYW)&Q24Z}<U-(%8c$%PDi=Yov_TzR1ihZ>ZYtUat8b_nsrD-d(I+*Cz%;cGfH&H&
z+LZwLK=mm>?P)awfVViLwkkz!oa$9tB{zw{X|+xnAy25&%YYoI#-qrhRk<9XhdPSD
z9d$Q>OKK$nN44LxDiB1#Ni8IBN$va`phEQl;2kcjna?3DRBibJwP~ss0Iz*TO@2|O
zqs~jzx~VP%;?#HoWh$N{Kn)p1z)jr^!1bx>n^&eod5cuF|7&ojsX?!StxyXAxO79c
zt3YiJ)u#frPHIMlX?t`jt2AxSYu{8`RhqVvopGG!jQTTGHE~gYLlt^yd!=b>=Ab4K
da8%0)EK}>e0hp}z1dt<dnrh6{-UX(${tIoG9asPW

diff --git a/Debug/Libs/sta-core/src/devices/stm32/can.cyclo b/Debug/Libs/sta-core/src/devices/stm32/can.cyclo
index 3ac09fe..42ccf5d 100644
--- a/Debug/Libs/sta-core/src/devices/stm32/can.cyclo
+++ b/Debug/Libs/sta-core/src/devices/stm32/can.cyclo
@@ -1,17 +1,17 @@
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/controller.hpp:27:11:constexpr sta::CanController::CanController()	1
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/controller.hpp:27:11:constexpr sta::CanController::CanController()	1
 ../Libs/sta-core/src/devices/stm32/can.cpp:10:5:sta::STM32CanController::STM32CanController(CAN_HandleTypeDef*)	1
 ../Libs/sta-core/src/devices/stm32/can.cpp:17:10:void sta::STM32CanController::enableRxInterrupts()	1
 ../Libs/sta-core/src/devices/stm32/can.cpp:25:10:void sta::STM32CanController::start()	1
 ../Libs/sta-core/src/devices/stm32/can.cpp:30:10:void sta::STM32CanController::stop()	1
 ../Libs/sta-core/src/devices/stm32/can.cpp:36:10:virtual bool sta::STM32CanController::sendFrame(const sta::CanTxHeader&, const uint8_t*)	3
-../Libs/sta-core/src/devices/stm32/can.cpp:60:10:virtual bool sta::STM32CanController::receiveFrame(uint8_t, sta::CanRxHeader*, uint8_t*)	3
-../Libs/sta-core/src/devices/stm32/can.cpp:91:14:virtual uint32_t sta::STM32CanController::getRxFifoFlags()	2
-../Libs/sta-core/src/devices/stm32/can.cpp:99:10:virtual void sta::STM32CanController::configureFilter(uint8_t, const sta::CanFilter&, bool)	3
-../Libs/sta-core/src/devices/stm32/can.cpp:124:10:virtual void sta::STM32CanController::enableFilter(uint8_t)	1
-../Libs/sta-core/src/devices/stm32/can.cpp:133:10:virtual void sta::STM32CanController::disableFilter(uint8_t)	1
-../Libs/sta-core/src/devices/stm32/can.cpp:142:10:virtual void sta::STM32CanController::clearFilters()	3
-../Libs/sta-core/src/devices/stm32/can.cpp:158:10:void sta::STM32CanController::initFilters()	2
-../Libs/sta-core/src/devices/stm32/can.cpp:172:23:virtual sta::CanPendingRxFifos sta::STM32CanController::getPendingRxFifos()	1
-../Libs/sta-core/src/devices/stm32/can.cpp:182:13:virtual uint8_t sta::STM32CanController::maxFilterCount() const	1
-../Libs/sta-core/src/devices/stm32/can.cpp:186:13:virtual uint8_t sta::STM32CanController::maxFifoCount() const	1
-../Libs/sta-core/src/devices/stm32/can.cpp:190:13:virtual uint8_t sta::STM32CanController::maxPayloadSize() const	1
+../Libs/sta-core/src/devices/stm32/can.cpp:61:10:virtual bool sta::STM32CanController::receiveFrame(uint8_t, sta::CanRxHeader*, uint8_t*)	3
+../Libs/sta-core/src/devices/stm32/can.cpp:92:14:virtual uint32_t sta::STM32CanController::getRxFifoFlags()	2
+../Libs/sta-core/src/devices/stm32/can.cpp:100:10:virtual void sta::STM32CanController::configureFilter(uint8_t, const sta::CanFilter&, bool)	3
+../Libs/sta-core/src/devices/stm32/can.cpp:125:10:virtual void sta::STM32CanController::enableFilter(uint8_t)	1
+../Libs/sta-core/src/devices/stm32/can.cpp:134:10:virtual void sta::STM32CanController::disableFilter(uint8_t)	1
+../Libs/sta-core/src/devices/stm32/can.cpp:143:10:virtual void sta::STM32CanController::clearFilters()	3
+../Libs/sta-core/src/devices/stm32/can.cpp:159:10:void sta::STM32CanController::initFilters()	2
+../Libs/sta-core/src/devices/stm32/can.cpp:173:13:virtual uint8_t sta::STM32CanController::maxFilterCount() const	1
+../Libs/sta-core/src/devices/stm32/can.cpp:176:13:virtual uint8_t sta::STM32CanController::maxFifoCount() const	1
+../Libs/sta-core/src/devices/stm32/can.cpp:179:13:virtual uint8_t sta::STM32CanController::maxPayloadSize() const	1
+../Libs/sta-core/src/devices/stm32/can.cpp:184:23:virtual sta::CanPendingRxFifos sta::STM32CanController::getPendingRxFifos()	1
diff --git a/Debug/Libs/sta-core/src/devices/stm32/can.d b/Debug/Libs/sta-core/src/devices/stm32/can.d
index 4b1fe5b..c1665c4 100644
--- a/Debug/Libs/sta-core/src/devices/stm32/can.d
+++ b/Debug/Libs/sta-core/src/devices/stm32/can.d
@@ -1,8 +1,8 @@
 Libs/sta-core/src/devices/stm32/can.o: \
  ../Libs/sta-core/src/devices/stm32/can.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/can.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/can.hpp \
  ../Core/Inc/sta/config.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
  ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
  ../Core/Inc/stm32f4xx_hal_conf.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
@@ -30,16 +30,16 @@ Libs/sta-core/src/devices/stm32/can.o: \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/controller.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/filter.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/id.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/headers.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/iter.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/lang.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/can.hpp:
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/controller.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/filter.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/id.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/headers.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/iter.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/lang.hpp
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/can.hpp:
 ../Core/Inc/sta/config.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
 ../Core/Inc/main.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
 ../Core/Inc/stm32f4xx_hal_conf.h:
@@ -68,10 +68,10 @@ C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/controller.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/filter.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/id.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/headers.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/iter.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/lang.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/controller.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/filter.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/id.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/headers.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/iter.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/lang.hpp:
diff --git a/Debug/Libs/sta-core/src/devices/stm32/can.o b/Debug/Libs/sta-core/src/devices/stm32/can.o
index 2c639b3a607335d2ec4711ea921dc9e5bee09dde..b9a3954cee28dd45e0e512d18aa6bd7eadf7c51a 100644
GIT binary patch
delta 135351
zcmb5WcR&<L^EW=TyR#EF?+Tc}oO8~4dggGZGiT2nPtSZVW)Kss2xe43P!tsdK@@XN
zh@c`WB1r)i1E8qyr}pmoexLXE{`K>Y>8a|fPgVEybg1sxyq%o`cXr<5!G;~LG)%27
z*Q1={Z*`3d=3bVLu~Yn}T>NNKSvr3kr>W9reB6|BOXJ2fRhCA@s|!_QPOdt}L@pZ3
zRB`R9w21FIs#vphPB+j0KipF*od~VQsw*><7ESqC^y4RUe$f;GXrA#76F=GU7jIN@
zs;ZevgEd;FjGyT6<*oMOfilDX2w)g>EtlF1!?1s@Q8Vf~u03!svw}+tkzr?T5*c+1
z*OA0haaHVUh8=qktX6Kboh;ttj=-?<r}K=ukLyZeX}F!PP)rC1tDl>{lf_?as$$sO
zt{kJD>>5TaftzSggyte2@TR)OIeC0)0nf0TuWK0f+6qpO{L3QSt0H;C#@^5}>Y$3`
z3Tw)S*ZbYc2R3OJ<WE;5<Lrco5~GfGC#$UM78RquUXjeP(~by?`ldUXVg0)UGubUn
zOT^m_j&PxZU7IH}>YTE}SSkSjsv<m_Dytcd)!c}rUUZZhjjN>{?!_69VSj1GF&Yoc
zZ<JZCy~Jp$S|`x`jKM6UscTt4_uC3^-_Yuf`|A5h>EK6((X_PeqD=oBAhxwe(*3Sk
zb`YJdl}SkNfKYc^eYzhrSIcPnSX<M5Xgz_^46yZ~`$rqJ3}<t_NXq&#GQ*W|yG!?x
zFu;{_drJ3z_JB<JvRQP0aR~U8+zRP_&|rz-Dwq91_rFhK8Loz##7+cJ+n{2&nq|w7
zfk_{b(WGKmx*uAGXSk;BR5h$V9{26so&4?wh2h$JIQhQqAm8mD{^7eK!*&0MAH7)3
zaQ)q#k6^H)rc}}1Azj0uVj1nA9s?Nd6VnmEGO8L$9HV{eBs8iqdqJc+2|?wy3dA!f
zp)l-_Mm(cUQ{PlEjMb=pUAUWPh7#BS0?YgtY~W~?(PsS%Hmn|q?0>=LSahIr{)1M=
zktj7bf1MyQ+K=jqz^Uh<)_!H%I?Bim^sAE8jP^%G@=sCKcMOyp)><}FX0&Ry;$;oP
zcqp%jXc!HfgnLg`(FURN*w-MAvC3LUgj{pv7D$UMJ$ON-+_)_<68jIBvI9A?Gsmb>
zm^VD5ICHEjB^Wt6XO62%Y3a@}dS^~~m2wn01~wK2_fRQbj)uyp36IW6jMl`e1K_#y
z4dKt9s>(9$IEK-UM|)><SHf5Z|3#=3hQFw;gbZ2G+<(h5jZ&NN|L6!cqH7Aw-=uTj
z0QYrs*5Vb^t*@$LRJsL@_exoN*J74APXgEBDx)(Hq^?(4Ed<u);C0hA+JGjjo8Ab|
zone>tQ!!!-HC}6`I%!$Ui|v|R5SSTw-BbfVvW(bXp-N#?%U6Qv<Rmnz0Xso-aT0>+
zuihLZc6Snr%D$YaUQWuWx)1AOUkeq|s%lU{V8s4T!lqjD2K7D2Nt98=NeUwlaS|>n
zNv&bT;ZDL;Rl_JU;wUHK#;~1NgBq*8PjEHGNhjvY439#pCay#&COd7~8P%F!AvN7e
zX;hX)$eQgW1Xa;*Fgo8!D5|g1K`eF>MwRg#d|T!utg7@(c(Bq*xT-?>Kx~bZD6blY
z7Abl;2@h4L*~sy65>**CxfduuwZ|gVoYhqfOz0{zv&gyPgV5RT6k}8`GaLu?jhoG4
zBt{H#7R$=8{8#vRRBeGY>i=Z7MjZ3%e>6}1ucqG6*q+UzsxCWuR#n}<0e#&`xH4?w
zXq5YwdI?lr+dbx(n&N$9Lo_UvIRvgHdeA+is#{;ph)M4BfHkV?VNgkSzl93*P~}{M
z*kgBU_Ej0)3Lfj-5cvga^z#hA2z=gg-f)fG>sV*3z{-vgV+})-Kkz~*jTA2t*zs>1
zsmAK8#i24)>G8({4dbe-suUncJA3>zMpwOD9o#dj+&L_xtKlRB)#@8OqpMkt^o^=L
z*%G6xRgOAsD<ejL=bG2sG0WsKq>`J+=qp$$2Nm#<a)K(U8CQK3Wvm1PQztU|YPNw+
ze5Y)6n^RWx*AOkEuVJG`Y*Y<xz%u%p&KxV#%+iT<JTtkolO3g|%4}1IySZGqrJh>G
zP|KV)OwE*-80HDEU*k{1m@$OC1BWsA-{BZTZFB$OtW%^E*}VLJi+DIzm@BXzj=ko}
z4G&xpnM#&yNEmV+;L^ZlMTVB?4jK)RK@<K5oT)i-JHs^AopF3HSF?X@FEB04Juxbi
z7bhVU`#*xJ6XRIM(6-D!@1^mm$Qar=i=<KYM4cPjI|;mnGvS$g@D45GV&LGud-cT<
zV>3{-h=o9Ff$}qkuA)n+ijk1dmRC@`y0~Z@{uZO~^$yP%y1O=W9I-U(;I!G>{EtmG
zO=1jvOoW6th3damxSNJ)sWR4*XBrr03jSKt4a2%o#;X>NO4hO*-TF8>TFW(aZ7MKz
ze}t<TYE*g;kCrS`Z^BBAlT>*a`fHf_Ps%b*QZSI3O5*-@Y_XQpMtez&iFF*ey12E=
zXPJ>Yh8d4PjT;KURN66EWGYT@q+8wCV8=IWU3ELDuA{cCuHf^CXH+BgTOFfq6@<YT
zB=i|lxMP*AX5EV8)QswHX;d~6Bj=6M_t7)VQ2aSD)l^8vq_K;PYON#1<{{Wnt*XtE
z?D%POvx^5<Ms-BDco@1&2&#+%A)JHuWkTpgUP*iJA?KLxj|Tj|LLv!eKp^*jg}hVH
zMMvq}ng0k$BqX2`_4xZ2DWEsJjCT3bNy|{JtHv4CBvlU*O-RaF3vB|c!^6E&{Szvt
z8@PS`Cr9->KxT~7D%68p8r4-7o-t0Z&<g}QKf-BSvrxn+S<d+o&!XYEc{z&9xO2qT
zIm)|~V{1BEy13UTnoAX#5m5aI^b)c_1k-Nb44zp+cdYdLY+P%WS>ssaQlIVTIO+1w
zV_;jA?d-^LsUT2c*!ETCJ9MrU*ujoEt_|wb!(jWD*@KY~4})4zsS$4%JaNMR*TZ0k
zl!<eAxmI*O4t7Ktt>dVxn?R3)o#^(v<DP5P>bYj+KlM#Wen1H%ByV!BJ=Hfm%gyR=
zbE{-sexGMdzws?6NK8i$v_4Z0evqTD+u>j4)fJi9kmsp3x?ucg4*VuCd%?MYzsi-u
z)r<i*RgO0n@G4cM*P}}L3K;ymHgh(dG6{}0W!+iPF`{f2^fN(an<-5_(c2HVFie?(
zL5}pYR+ojRRm?t>g+_Hhu+{W*m@<DklyYu%Jw5!(;L^W}_+xjy1SOE+ijY(J&M|g+
zE-*2!)E?Bn^R-MlYE(u4s+4i6XsrLLbakrCXUb9QEC(+A`$wkc|0A<k&rD)E{9i)7
z{~sZ0b`$=U8456V*Y5ww{Nvw@@-*!Hg1_2RnSE42D&P6#VV-G-KjR6tiaFqr%2#14
zIqH`$<Kp|@5_SJ0;c$#7U&Z}@3q7Oi)QO9jwN0JxobPleikD+|`AYwf%->D^TgL84
zD_^P2{}*Rs^M7SrXndI1r>(P=Cc6AxQDG(yrw&-<JI!fhlA~3HO7L_<g(~*{MH%Em
z<5s(WEe&+B?c|tt-C8(Ndb=#@EHmwfb)|vWx4Y4%6PPX)oWr~CNJhT|eb+d80Qk2B
zf9$SMQ2+IK2RYHIwr%W0`^||~bx<dPaRpp&CtS@6&UuFKSYu~jk!j_yRU{W%RHP~$
z;k?=_mM!-mcdKl#h^|oT=xk+O%`O;S949NbG*JFn7-71P2QMV*TSXnmZgGfJJ2-|`
zH9E#t71)Z7aaCJ`x2tMn3zix9_utowj`XTE>}@qHqqbN%m-P>^ZmVeH%FG;#n+pF(
zsvRm9&U$7VmWJg7u1vEX5UxN|IJDi>toEOqP}Y_6m?~mHTG{O%j>vJ6KSq1CqUN+u
zD`7z^l;z6s{jmxxU(P9_`S<ErSIxa_<W#H$)g3DQSB`o=Tahcf&5=;eU3nCb^_%)2
zTZwc3)A6?2ELFy7$B639Sr><2^@d$*Pry3xA5D#hbM^9uHFuWNUa5k~vq6WOrnnIl
zPV2G=UJDXev5pb0RhOMg>YJKIocnr*P@|GvrvOTAGH_b&{_senQEN>9Agejd=<!dZ
z!6Y32uQFo!$9Q-V>Hd!HGjp*<V^-ZJPSHp#SC}Ccv2<j9{Z8_=evnKn9fxa|S9JX|
z2n$8#<2>RIPY`g8u@{hn=)CUsrTdo=1Xp_zU5}K-f{+=so9^9)lY-?HmVb=-F-ZnR
z5L|F?GPc4@1`c(m+`%o0^M{)5gD#L;>|~M;#hQU*QZZfPn93MrIHtq{(FYJZT4x-c
zL-)h4lTaf10*;yPM#_m^Br5GBC-&!%?-K;N*8W72J6Wm&79AtUYzQLB$d1GrltGy9
zd<bFC7m{q1Ml!G35y!JX-H%IF+mVc)M+)^z$UvKVl%0E+?(<sG_54h7>k6#~nMd8p
z@WAl|_eU|gczi3C&rEl$S~=$4JK{udBdrP@NGmp)INy$vTWRQaIcE74x^J<RoO4GZ
z?Htp?hm;GQ)n3m^(DEb_DmRTFg8k^)DVHkE^pYHXl}z$Wo{@}eWioc@9bM-bDYsGy
zne2xNJjZkhCA4mPsH_(}h+nk~X{kR@VU)IT!p;n9P1!r%63c%x2`vsH168gNsCO0O
zmu?}Tc+99dM)jI<w_hLwQ9X#WU#9EU@pSzZNRD1QN4ir#P>H$4Wby{)MjZ1CW~?0Z
zrZ!!xUL;BT>1SlV<adJ0?MU}!22wegd{X%9F!8(Qky{gsNnzO<;@{g$ZY{Y+`~~kw
zrnm>0xr(VWn(#;BEcU1SJ{CgTahK#>>ySf3zmt_Z&IcM||4Blv_mEJq^SQQgR{NEW
zPR<G{>*_58w<D7z^)UqTcqTb9V286-rjT1>bac&HNagMvN4aAf6T)z3Ve}D%@FbQD
zZ)r^TE!q*z<tlc9Sa^Uks%)V9OLOR2M@`vned*rf^mJ2Mg4@@K%xpxo1WoS)-G9#_
z7vr79DD$0UYAhu4&&!aRv3Ci%LKI1QAEVqY9|_YlkZP{h1BTjv_-!(_#@RXaQV6b~
z5{cF?Ab#jp60H|T{8tt-ycAPow3Q{4+rKBl)yMjbV;aO#>DB$n<hJ)@e!KJW{ZWHt
z8uurhbBF1^;ZnM?HPzJqlY&T8`;g$4*a^DML4x@82*E{REsM4~i)7rKWxDkzNuD@L
zlI>=bq-`B>{%lR413ic{w*ln_tR;j`v*^M3;16#WmM<KWfM_N<qC#NWnZLV`S{3x%
zXp?^tkmqwUmS`i<9_8pd(rMVoKtPWV()COM!IgHSa#yHMoau-zaZI&zs=1{Y+|e<2
zB;;E><qpOePAfvXH*KW*qGx2w-b_ubPxq-}%i8EZKqQFk%ZRh^AQ=csqx%R9ZXDD8
z9x1PgA$Rjf(0#~f%8fchCbL@*zk;*F>9LsjyPK04$wK^jgNQTEM%S^E2(6*rhY~AB
zJC5-)Q^uZnGC$M#EZ_Ga^IIjVE@d}eC)Op-#d%b+b?eFe&q(6jh$qgy-Q<MrHJQAN
z0T1$bDL2f6a<5+}{G|ivdI~FU)a4{+|Nr*|G8yoLgz6lmt1X?NH&q~^uhC>U*PZUG
zHX}z3uZa^Q(xZ79LAs($*Kmns!k&{8bHYh-{T3?s&JwyGfORj&?CnpI$y1$92WqMP
z-|0v~W~Wfu4J0&7qU;Xcoh9(4+__iidNY%pyD5=Ob{@%W`b76F63JxCW@P^I5-Q)Y
zC&Vvtwt$HyGTHYKIq{_t$s{$QYyJp<+W*O}RMs0qNNv;t%GlqGlw(&CsBRQ-th4B9
z{zyRA!|DF`T+(_tjwJ70A>Gtb<YJAVbpL7u8Pl(&0-OjT`Jaoa&T^Vl0XlA_du|ob
z?2Pvj0<v`_pd?~3@y-_}`WD^Co+0J#n@LUSMxZ^8k%5-2=vu`<GI0oAq2>3cYv>J<
z+})ATI_Hpi-i0L7#u3ibpTzIEj;^PivjlsY2~^5%2wro{+WAzaaxtkbadwas-jH(j
zGX#1lfgth{NZu`#${Kx+a(Bg$;Us4tTIj@C@sSLCL^KEv^&!l;-XwqNFOpx5U@{8q
zoB?dNA1A|MTM1PAgRU(rlW52ca$-;l0S$3Zt+oy!e&wYESG@v3FBnC-HP#R(%Q?sn
z8ALS{(u4Syu`>b5I)qulIlj#IA+$py38x^Pu2;4?+rQ;1Wke1plLhVQ`plD*rS-(W
zJ%=D%HWPH3JKfJi%vj5mwjs{g7Ig2A@Q0RhTQA@`1`kflRJ=fL9o~VEH<Ox(urgCp
z1(9~9&mby&<KtALF%g0tto+UdS~Hib_n5Oae9u#XKj<r!vJ*n!m_Fna#0rtrPOc@%
z-fFsEQJKs%tVoidTnPH;Foe{Z8GlkSw$&ubrV3q+*;?>}OGw`J4c%Yq#WQv-^8#^t
zEtC8kc|E8%nF;Pq*+FNhiWYvugJEW4I;CYkAEay73G@_wE|Y;~&Pmk?H>#~Z=*qOr
zUkHq%!yZbyWm?nKrI>0c^9wl<f~KuyhF~_VWoq<;MLRPwl+;r0lS$hXD)+>8RN_m{
zX+qXADp|uZR5EvG%U9y4+D$14j?uJS9C`+h==adxj9~^3*Nh<<D5JU3FNnR9gj=<h
zz^Fc)$l6Z1&bt@me$f1Al%E@%ZH1S=58Mu=A;u_x4=w#2FvBLb1%G%Lwb=>Q&A6Xz
zq`_!TJhg#^88p4N@B9VwtJr{F;ok=K>QyA$Sj|f?1K2X(QH((L$45}x*~z<*>|oF3
z18yh#d>&ld&H8I;{;`KW_$$2M%jP38!UeIt|A4W5Z1+@%?q`ROg|7$Lu{5RxvmIqH
zL)fb0zzk&@Z-j}1tRD@JVXWsk6d{~_&<EIu*urU0IE<JMEJUzVa{zsWZA-oTQMT|b
z)FauE7kTu*$JkR9KptmH@eH^VY_ca5qgXS-=-f%x90=@FY^5C7J<VRH+1wd+Hg)CE
z?1ylm#jwh0P_gW`RG5!r3ogR^S+@HbFyq<3s2@JZmc0bb^Xv}>U<vGY>aZ@b@^umQ
zf02#e4fB`S1xJxQVAqh{M7C*1h(2U5Pe)}Zv0g`j{fLcC19mdo`W_s8!oD64?5FI@
zE6_`22T=d_j4gw0J}#X-Q~{4FgI(hSluY(B;;URXyOTzp9Ja7Bn0ai-0qEKD+36OP
z;vIXF)*tU#Lm8O(z$X6<(L%P^guIXJ7Zy+C6Wcl&)MxhWP~?4K%Z!FX5gW~eS<L?3
z9FBfvzkCJuH+C>~3%FADTOuTXvJ>d>u22obe2ZJD^4kUveN-c=Pz$!>ulj3mAT^!T
z6FRe!XwEeI>s^4(@tOo*<{n#z`#<#^7>MHk%43^AqCpld;2H*A#<fvobMPBi#d4Kv
zvYN)RAoel^#UZZMoDYRLZgMH!FYTE)-17mZfAToZg<omDr;VVwJ0IH`)`U}c!4Vq>
zhyjtcN?T^a_nN=;1k@^4O^tpv>yL3l>%|U7jGgmllUt$JThIQW8I}**xC!3vJ?u@I
z1n*^My@yB<d$l)Q{?2|$1lAhWwlR=guNplT<+A&$zTO47UDeYUj_+0d=?51hRoQ<*
z@x1EH7AW3Qjn^YGL+%)2mV;mR5jH2dN}7p)YhYdnemkQA!GZIe0b}Mc^v`%3^E}`}
zD0^-SWY4ls_oIw=+2~j3fIhL@*?+6RE~QQdqH!KZ5pA6&4^hmz6)?JJ>rn_$TmPxQ
zz^EEboi(4)HoVyrMQgMS8+6*n9c!bSnhgJnA~YQug^F+1ZxH-w-t8XzXi<C;_0)3Z
z4P0BL)9j{o{jV_JdHZJM_UwBajt%(W3Hed>_jMpNW!Pu{&7IZ=*^6=z%i>nBuXdw!
zUTixrfIHZ@^3V@p6U>m<&rZR<BHrdHb-_H%{=i<eHkx%hAHzDmk7b?i$FWZT&$7+}
z#IxkJ_9E*n$R(CaLh~<%lWx!uVY`@(s&L!$4%c#LZ^G?LyOZH+wOmvMSEHi`Dze_o
zp}00$<p-@MU(j`Pt&Z#kr`-^GiXE;{2%}5<450N`N(-&NSIVJe17~|-N0ltO<YTLe
zs}NZS_f?h*kzl`8!Y-I<*1A2+cBptA89ffs`gP!OdLupA1vDRD!JfeWE4PyUG8R-I
zdmWn^=v8NU!?PXiRGJm+XHD25MOPWdA_->i(tvuDy-RwL>}521bafZXBQKhrT>#%=
z*sjrbz{IkxDBN+G{pJmgE9|z1aPca;_z}vI#2%s7{1F@T5O$N<zuQ4Si~XIJ5ZUZp
zDohS*Z34+JY(z5Di`c5|V6d3&90BH9)tqvWT&LPkQ6w)_tyW-eQ)T1u0~errAB^{(
z3smj!hD@j`{v6N_s@%6BGfcI3Fqo%ROT1w4jH=BF=trwM-+_s%s;ezf-fOBqb)fF4
z{-D5AiYl!+m}#oH^vIs8_LBN5)zwERc9yC`5vaE+Un8pPiz@anl*Lnhd$|_<?;3S(
z4QOmouR9FUjp|<>LncuD^DXRdSMS93Hy5m)z8)q*)MG~=Ij*kz0+vpwM@<3f1$Cz>
zP`{|&h{?b65qm^;gHDyl`5>!$HbX^M%kla*@0UfG5OJMvo`k6`-LBC3v)i&fuqK~Y
z|J&n~ef2lWUn^)iQ0t}?;o86#o5ft?$&~=uYzzfNT6UwB*XG?+aM~BJ$n6w30{(V+
zydL+xuhMjA(6*g;4kM?~`fj3`hvPG@4S>w-qeVdYv(tN&Ax>*g7>}H@+BwG|7O(x>
z2YHvZ?WtrpwTU+5C2A*ags~^uNp<1$ZC+Um$&dV{HV|1MR%M~!D|!ro<VpR!crfGi
zYt69lYg{$})K=s5^Z&N}qilOUAfB-9N06kkzRhX;d(MW_;FivgXb$cx)*gl@oxygC
zLb6q5DuOkCRoSa3OMq$`_S?{2evd)2Lv^ho^meM2R)!0^Rhcphw?~zXolq`Fl{pm5
zeX52u2|l1&`8)E0RbThO%TuaR7m=J+ouM_l{eh~+33!{R`a1(Al2lc{K=F}ENP%LC
zDuse?k5w`4!F;OvK&#<Y)dFguX{z}r@R*;gxW|xusX8zZRJv+E#o#hj*=vFMT9r-_
zj4YL&hxu&P`;lPgstRWU?2YQQ1tWBxU3IGwH1bvL;(+a`Zh}(++zR#NbR?_P)o@;l
zTdmeihW=W0{}MQ}PCbSu^I_^T^d^U^b0$MQQO(`}^-w*nJWw8~Tj!(llGR<$gZWrJ
zofe@_)EN}FNL4>>j^vp-kydoi)pnOj(0`%!zk}qJ+HDakAw%6W3{<B2WnU;}sb}8+
zT8?_v7f`wCNE(#is{h2wk;_x_)KUu6Mv9ocQ~QZXKB&$0fl{ch)f1AR)Kh3R`B^<P
z5>%0T@HdpKSiOlxg|F%qdp<P2sgtO@-_?s;Ao@c+VlGO!LgRl4<z1=iyBN$hnyuKe
z;?`;+LSWEK(;M6UoVO-s8A{=!8F(26H)vW?|Fuc8SOvY!nseFE^VJj|hoqn8?*N$J
zs_BEHDV)Eis2lPEH0f=q{|nTtr@+Kc&4K%n*`>*#;NBjM@d>=xt4XT|jeQ#XcjWEY
zv`YYXh-M4+LAX%OO{(=UP224#Ot|LidMF&${4oRy5t=CM7js87ew6?gsVNDC7soYk
z+d=PyhWQ1|lbZINg8uK6#^)V0qBW0a!kHLN(*Zz>)7(4){j-{8*o5cKX>OC>=QRy4
zpoAAR9kF!aE^2n+s1SEq^QSAkxT49R8Q3+={TE<f*LXjI<W0@gCUE<f=3`|fcQm*9
zK;*6_^ESZlYouRTynhcgra*Y}P*ah@t4W$Y&rrf-O=@Srq-cJx3XLb4Jt0V*YW}1k
z@iWbc_ejz-cY^@)LQ}g8l9w9IUWjC9Uc3d$YmF)hNtUKucjRSjCcS`#T#chMm~S+%
zi;?7Osy2Zkdx2)<Y}Cnn&814Hp%0q+G#C7+8D#+VNt5*)d0#Z%IAy^VX_{;VT8XC5
z5afN;*b@O-s@byv)%9ItKMxU4?qw;|S8%bp&|Ae_n~F+U&BZr_Yil{Tg{aDP99IE$
zy}1e4faccQxs$Y_*udG#LUbe7>o1tt%r!2Ai7i|by?B0H%ZXq*xHY#RvW+`C044%B
zK@I)w+&qeC@8D`rMY4;l+!m6%x%9(O-^)F`gvS)b)#?Vl{aiYQ9S(2<(x?S-6Rj{C
z%Gtj~0w$d6Hx!l*aapurjo><=iEu}_Dzr$C<Zd59VUBU7Wx$N$vZ-cHa&u|0Jk6cO
zK`ibJmsSkBG2EqSsK;_I22#`En$r$=JlA0X)X#JC4nRGDYeJK+6pr5y>M{4XomMNU
z+>L%ve8$!J0pFf;+kZ#q3-0!LFw?nPq0oQDMbf6gYp%T-erIy3&k)Jx=F*s(!{xk%
zqn_I63?wVGv-*R%N?WuFKCRY1p#}e1ZEb2#>$JmY^zhbJdk918wN3lb{C}giJcZ9T
zX@^q)%U2sh!<wJA$`3I8wFBxwW1F`1Za5mKZIO$5+OC~&2_ieSc@*Q@rJe8+cJFIH
zb^-N3d*ClfCTXMdK|RubT!6e3ZH?AYc&r_M2-H*UJ({_vYD;^Gc>mJ0mD_@Ru1y&P
zhhJ)2*+8XhuZ>5Np`B6{KE2i+NI;pgv;`EB%hnFZ`6Vt_`xA#3xHnppH}vwf2PQ)@
zU)%B)EWOu`a)%cmv|ld*<&$>&Bj|nB-na$HV(q~7@S;S!`X}PAT&Xr~3rhH1d)*C>
z@~5`oG-N#aNivd^{P7>iTg4X{Kpo}#5Hpf*^#vx5^I4-|;sn1s7HB8=HWyLBr}%}m
zopOeMN>P(&zEBUlv3#%HK#Aiw)dVx1_b32$j!z$sJbMD~P2qwI{70I)UgC$0h0JCC
z^K~$<@}mX#bd9e{0nZ!!&wa3alkaf?dAIpAob~1I@Y^VQbB_<9*#CY0^+AXv^2aG4
z@Q^ptvwy^&YJnt~??|)%$9$DMP)`7X%1gELY+1lO<3HX;?LFsv-~=!Cf*(8qzNPc7
z<6!p{-;x6}lQ)Hc%Hmtc04A4rNukQ;)uWK)^Zf^dS-@AKt(_0NO9H$o<XIY8Kl9lX
zNBY9g>Iab$K6Wh>zVgi}lKY*v2hi*PgI6Y^5<P`!bo6zFkWUkoRl=J$@N~5>JPOXN
z6;iJvStoR?1qE+mXD%$Q7mjTL=mx=WC-gQ7@$Zmq7CJZ}xkdQ29O{08FSQbfu<tSw
ze_`e-__R%E^cX%}6pHPAQS3_s*B{AMVeb}juL<cC^1Ugvp>X6a;r?@2x+8S^4$!+o
zs0jw|3t_Xtd?4KU6=)BIm9#2M61I*)k|OM&{j<kHV_F706{g_CFPADTcfkB}A?_^n
zUI<rdoAH&fB81|98NxWi&J>aus$e01C-ifK_w9k5D~zQ+@U0M+g~H?s<*q@bKu8$`
zg?GX*9FO2W2+jK;DHJj_aQl<c$cRe#EVS$nX0dP@N2$3IVcIMh{3h(8NMosRr4GP;
z3jOA=c>g@b;{Fg_DZaiA?kaKk2w<-fhtaOaTCv|9FulaGCr}D+@xlr?<0C$&PIrUY
z>^mIYBwqD}`eyMH1<8EHOKU;-i8X_P;xDeDIpQ{PN+RqAipwcjzg^^L6|zh8x=HWf
zZt*Yd@N+?;j^+#d#4<^s4u}QR-vo<|pTh4@@#1fQIVh%6=ptO)UJB}vSlS)sjSx#Q
zjpdGrC#xZe6t_#jJ|=dd_aI7a+!<b+6wCbq=+k1wVkBooHI83$$>K2TQtVGeFWR_y
zDz;9C{xgxkg(OWZ8VtKH#O{NE_EKajfSDoMIzsWa=yx5JkR^^?0ljRoF9Lg9uK4N!
z6yAsjyMmc7@*N>kAnuC+^+7D44ysUm^BC%%L_2MLd=^u7A+N|TK7R{Oi^cRFDB3qM
z@+K^mif+qLv>)P!Sb+W%lWstNg>-luG*(IvUjTcxwA6&WHIjc*pskZ;J%xyuwEi0O
z)=MojA?YJsD~8BMsnZsSY?4xFpLC0agGP8vQt>L}IV5`kO=`DFgO@^an>5`ORDjg&
zC^Sw;FXn+6CAFdc>Xa1w67_XjDxl~|w4`1NFJhz_^v1+V9a}@;tW=zcymQho{y;e|
z)u!p|1*zQ*Sh^_P@d0&NYF-}-SER)qA$d)jYo`$Yb?N*&l>VkPZvjAWNe702x+^6-
zhrxT&@8hA7D2-f#yob^kTKhecB4|$~S#oOuOOK`YmGBInNS&6$M5?sf1Cr0A2d^RW
zLh4^1)Jy611?at!CbdM8AswOZ$xLbW5Ie{$={Aen%aI1q)^Dy<dJr&grE@si$mK~^
zikKEip|lV4PU<)gXdk2p=a5$@ouR?}lhhWU1#q9GqX=Ph#gcX-k`k!^ad7UN^ye2~
zmP*x2VBv=}bs?yq(w?$NR>)z=h`)0y<xAz^{to#8txtB!?R!Fhx7=_(WcJ80d2l93
zPHzh@_Q}&O!2AK(@)8QcavR#L3YFb-NDj)Q;vo_)*RBidkeo%!gb4XDt(=a?%W_~o
zQf@|zvtx2)ngE`VyD2pPjFO9J@A{N%q~Z6pe6Tj`M$5gfp}aBjurxfUIJsdGlC$!%
zNHEXKE<GTbAXlVy+(o$x#W*j?%R)h2l`GT0bxoFzfx02LpcZsf&N0F5+w#pdpzg^2
zM?l?^uhFE%eqWwT!%Cujo^}}@%8%*UKa$@EK|fi(SOVr_`LG|TC-Tj@P)wDp(0Kh!
z9{U+ZdoD*(xcP<LB?@}!azYlIc_l}90{gW*ZwK7Yl*8#PLAKn4T33$TmG({E$R*W~
zytT{2Q;~j`yB!AF8pU-o5<f*6h)Q%Q{vjynR^<yF`|wvnJ|fwsv^4@PK$&z1d4WpT
zJ5boJgyO&tw^OM@%idkeOgDJ3TM=;rp4+4Jqebvu<rFy+q)5G?w@<lP71VykzU>w)
zg(z=TNJ5oIG~EwZ@Vej`Dq8C0Z!6PPVBS#zseiqzRHN7Mp0b>}+55`J#z-D0t4on2
zDub6Gd8mvgy(A^1B9cc+;W;G9N<5A_aVg5#2`I!%CDQ<Ay0Xmff(gcJ<qRF@$x)(k
z4v))Krj!BmjdK40)sXUp;=OswJ=zP)SDviW!Uq2L*g(P9%9Tr@QYGLE>ZB@n0i~}t
zE*<Vx&;JA7)_B<g{F+Cpz0`8xgfdsVHiiD{^nC!Cx)I%FwEubnohPX8@(GSLDBl}i
zHaz4Cg+?V^0nym@44_Tsk`qny=xjl=FXJKKeE&_DZxJlvzUBT?xVEal0R~$08MwB2
zK{2VewP{nO-D`UHIz(pS+HokIQ|dG`5i-Br!KRX(>)g2wM7!h%z^`5n|3Jpj8Mkpi
zxv(QlE;^Bg60Bs))9bX6-PaV!4t7Bci0x(HPXlByI~&Kpu<wybkMJm)oykKR|F7pW
z&OpqEpF1DkZQwng!}La8d;z6R{A>(<+-BbX;TSTv@I8j1l)n5o3gY_lZ+?SI4u17M
zAa3P@DbnE2kKO?0Hol)5Bm?*fg-8PVy#1(!oqTQ$fbQZ;8iTo)_n}E#5dW5DtNZxr
zR0;d}b+n8R;d7{43FRw=!nK3^Jo_bNhVi3^A~T$SOFLhO`0r!k#bLhseAtcP>sAEl
z5x$TX9!L2Wv^^5Z-=HmpWBl9sU>@fW8bF=kw^7_RijR?C;v`>WLUM}V8;06B&0m@g
zy)*m=TH!?Vy=Z`n;fLhY{3n)Yw!@n^-s2b?KFgoo51-=s3)hf$j=#^sr}O-wdthGV
z&(RBZiN8?}%**^cn$}<8hj#|^D&Mg)OkCry9){c3`5gvS><zx%Y3SYJGe*I}ZGJIr
z(B9z>WFzk`Ke8#E|GLM|NrmElehPgq^?;u>4l;>+>IcX?;#~<enQxH|&=h`!h!Q^L
zcXxo~6W)YRYPhHTqb`t4<quIr=NT#pKBe&&$ozBOgHT@ZtCyihU-Hkp!kKh_Nn?P$
z;^!Pk{F}?*U9tf4nqTZdW+wmJI20|5&#nTy*?hGL5Y6H9cOc2-zb2zD-|(*ZB#nE^
z_ouDFJU*fu^78rL%YrK4^>1PR9dF!=<UL>X7?>aUZWP2X<a67?i;uj87P+7J>vTxP
z{+T!5hrutrmW~S+@oy>0`IV1+jpQ3Y@;35*@J2d5^^-40JM*4GOXnJ2nEeyZtPw7d
ziFLx@LrA=Y-3EZJ7hYUL;v-mTWZ57j#2{~@P&pdOCZQ`;$!0-|Pmj1Qb|GOlKz#*O
z5J*2^0}YoBp>_t$ZxxPE6Y>|P&IA=8T%agKps<8o+b&$f*->tvP<0-X{X&JkaP)wX
z`zsWJ1se_hA;RC(9fk@E8{&Z;6m%RU!-PGxff6p1p-|}|!R|rPvBN^W2XHDvcuiBC
zBf=3nY;{!7{t1~#p?nQ6j|tx>9)DcOqapl+Fz6ceqJ+*=r6+}=bpSmjMAA~@w4f_M
zRh|)kp$JE`@Twe279%7@!F;Sx#tdehP>*6LX9YidGw8<)b7^XLPH1oiFz1C3iZCV!
z{<lG05Sspg=tZI3TVP)jT)dHYS<v)@GgpOQx&ZW=&~Ok$t_%IB9p4ZtK81;!!Vn6B
z-xA)w$4hlvcuGh0?g)RU!romWHy`%y30X_*;NBOSiAWv@XMaPP5{0}Iz<wwsP=}l(
zyzB+LkA&LQkR%IxhCn1mI7zF5$3h1>vhzg9q`1&iA$u3RNEJ-80rpJjT7-H^6TZ{Q
zi{}DjI(QF+zBZVDDI5(0bh^+thSndiga>V)pCNcBfcsk5uo|M7!d3;MS;E%@P}xGW
zqcE5wOltzkTp{i%oOvTeB*M~Lp;tBJ<q0onha_KkMe&^iVIEcNJ3(TB`CjNj(~%Ft
z&pS{k6w;;v^P|uvi{8Ia!s+o4{Vaq~7qL=Ir9&41;;QWs-66W`U~s3HU4pz_Vs9%3
z#@*rr>gV=|=j)?rd&Q+Yp&lgGnF5i0V%HT=*e@=i9kK(Wokql9F`JfqA!6KkB%xy0
z=|~QWUaO#P4-?na09v@%le+gq;(mJ54~s+SywOoHmPUt2@d@o_9uwQq#Pqlr_$Ne8
zh(Z<EjS_c8fI2A_)A`s_;)2mYIW5|03+aqFj9%?%@pBTGF`|V!idb=s7I|@E%_dMk
zYZvuBkQpzkXTqs-VsIpq^WvYMA(J338i3@2*p|kFiz0g#l9$BSgOFSnlU~4?E219_
z)mO!E>KLzy_d7xIy6FB0dN;&gbx<WY#nm^_E^diyn&QFS7W++r-W~C01SIc@c7&|Z
z62++$O1&?Bj)#j6#2;<&C=<oqbAkO(>=FpHB(XN_Jv|cFZh>U7*oZ=HDPmjN-+3(7
zZ2`$A;x^hfe=43`2$WRu*9l-g6Yp+Ck<!Enn#4U97tze)g}5jUk}t(C_TeDY#SI~F
z>b2OALNb|RP3kwY#2XZZ%oZC_d2_@oX8@Bcexte78!?5N<y-M-G@Qv3dwl?vFHWMJ
zkOFaV2k5;M%N|4WUTnlc<bzmr9z`k?m)wTrNAV0DGWsO?=1~;?vsj3kIQK<NnG0@_
z*trHYip3_wK$VEMXmjtY=vy6Ld=o3oLSCuZY6z<2yBPiy>OaKmIN5_`V(k$y?<q}c
z3dt4H@4JAxQu^x%n5(34TCuN|CLe|58tGS>n5>m5&!YI-I%&&(h<Zs;Q7E>z6nGtW
z*GpZBV97@sLWf>9NYQjqWTP~DHw<o)`o%$Evvi#zeOsi3v<KlU)lG(;pX50Sk`Bp-
z=HuI>Ve4TjK&rU|d4bY2iU4nyj;ABpA&nkR=U;Y8dkA!w)U_-O?v}o8N3uuSP6OXw
z>DFLWcaYTmH|Xz^3=2T*mv+U%!~y9?TfhWM2WTA;BDL&;Vuwn-I>7EhDV&aihe`I{
zpu(kjbcXeiRGDV=hoyeq;C6)cxIHNQ5$PtaUye#G=pBoc7LI`8F{v%Si06(=pISii
zgtYV;sx3--K+~L)QuIeqr=&ZB;NfX$V-KjGksea~I$G*Vi@zA@g97zfDSa`RaZ<v3
zV4jsq&%y0@$^9Id=cJxzA$i^|jiW<72@+2W;R}-6EP!5=ylA<1NqTq+Fqfq;3P)d&
zx~zqztCF7HoNH3OuSl*-@zlz0NPELU-IQwK6C*63->-&=yHYkC&AcalpkVxcNm+?{
zdLT_o0wxZG^@rp`$^PC2mXf3Z+8B8x9i>Cg$<ns~7)+7&&<T;plBGNppGcc}fcaFK
zoPi`&`i##svB(ak4TdzS!VMJWxs;It^%qig4a~okJXb&@U0Svod9S2Kbo4euT1zv&
z*OJ=;Ff%2KofgtrQf;cQZ0QERcEmc|JsvW-($NN}i#O7|SWs`JkMkgsCvDmUg?wo&
z?IagS9TtLmC*56u<h|4#rz)^GpA`p`Lg|DIFFs0P^&$C5T0pPSXDOEUn!iZXn!|jN
zq}xvCPl_cCxnCl=Q5XDG@)!+`Z_;o&b6+YASqSELDY-nn_#w#@n*S*!k3`LQ%4P+5
zE98CaL9LWG(28=EoN*5#tL48_puR?STm#rzS*AGuI(ZTWO}*reSD@f6mt9ZiPdCV#
zIndZB`;7tGCV6}-!1&7TX?o=+SE2sKA(v2yeVbg38dQMXh7Pd?%Ju1q?v#UFA-PNL
z5`$#7{N5i)kUV)DOze{{`@rCSIbazoC`9gXA5^H^(FzL(<y039-oHcg1={yIETa|R
zwUA@J!^9C;LxH!W@-zxbM#|gi)WtEmC7t>|E@x9%>x7)L8Zc3EyI@G3l$#s}$|-p%
z?XsMfy(rpqMh@r&^=P^MF(|~y@)SJKSULX<^5Wz`e9FVw&&nQVdM#xARoFczzt4u>
z=jH7RuoL9K(a^Xc`__TzMY+xa<Xw_SP+aM<tf5nXSL6iRF}f=IM!<_}^50G1=yiD$
zZTH=f2jhnTDE!a?(6{77>QHaX+0?Dykxyp=`mS9bkPJ)r<Od}{yDwi_22UT#J1MT4
zB;V<R<dOXQTwo{5!-8QcMb4(5TX-xt=b`^ZUbqSBPvx7mph=bIH-gABxph|<Op}}V
zqAs4xpK0gxg`8XjyD#PM)E?7i&reWzCEM%zz~KyeG6g?h%b$LMVx}BB8X8%$HU?<f
z@^ab`$&syetS?tSup0_*<g%yX#ans38}jmG{~&<o%XglESs+)7g5EpXI}^<Ja^FB;
zevsWM<X<TNMT6-_*;*0yKFJU5)Ve>*Jt?mAMSe01`bBaTKV%lmkqzKtiCkqfG``9|
zX?pZccBg~yrE;y^$onpzrx4H&`3*gapK{9wpgfhP6rEb3)TRB2mCD;v<gHN#(D8t^
zO125ib;=leOkPT>r8xhI?`c2K{^WY)PAACtD223_w?S!4=d(5{Wob#iNtr7^WV7<T
zIh@&|oC<(>U#0qA!1hxvP*}>LIR1pfR;4<fO7U0r;iMI!HNTg@nE<6N?Y;#nzKvmb
zyK;OdP<ANkeKmOhb}A=4ps`EQd<S>8(w%1Cdz1zXfVNk;<A8}E<yRfd?^Et|M<wo8
zdQXPP0YyVIi(q9Oo!$virUoJjRV+05IH=^&bUjR|;R%IsMLz=O4=MYr!l%PZ5KY1(
zlwQ~$v~x$4hqR76sw_PPnMmcyM0jyb39bN`<H{vFES*qds9%p#Vkp9YQn_0Opl6h{
zR*;NV?6iRsqtyBg&{$>2c_eX4ABt6-RW7arO1#p5b}7#(JtF~jUh$(-V+qO%I-+a8
zphR2*=tU);_GK<9o5GQKS;_bnCax&8LZER~InWfzHKl5EXk1rnKS16MWe!cRZYqc9
z(AX_y6|L%SD-#L(jxu{RB=0I+XlMMMa-9~8_m$zN;phXUQ6;#Ri26nH(5|>r1t%#f
zanOIHEY(3HS;@JF%oJq}jen1ov3+6iiLx#LB2SfSH0eoIW(-5}TnP__+b@(!wA_BF
z44~t>8OqH$F#lS4Kx>vvr5SZ>Im-D{VCE`z`cUGHl22n>zG7cPClCsh2~VK-PVpaz
zf)*;`1Q`6N%)129Pl}y7gU?C;bz5JQd1g>W%8WR8_*H2^F_v#i_GF-xD(#v><hvq?
zu=GPIq*MMsl`Jj1@YDrRba;hs!9`Fjb$6nnw@Nq6jx(s-YTfW!&|jn5<_nFry0JPi
z*Xafg2b!1e7cCy1w{8V3zSrv(Tao9Zt3(ISHt786gM^K`UsOmo=|<Ow`evQyD1dFz
zrBiR|tMe^_f}d_q78D%1_q2tvRaZ)zQvSLfyD9#?O;^(g`T@G~6kiS0#nM+F+jU)k
zfZCyRJqZ1sy3cgPW0!6b^#Z$fUYEe!qx0+q5BKWs)5sH~E2bA`pKc*7_4ex=w1IO#
z=RFQou+EJ(r9yPWe*tu;?j*(Q59%@*djG<7jYW{*x+io}@{n%QLx>*M9qtBZgzn*Z
zXdKb)YKFX{x`ktrMCvBJ1?UM~STXXVbgih<J*gWv83xbjs?(-Nw9ZaG#po_lrx~le
zO^eAmUGhUnp4Cl$2<Uhn-&Mx@cTP941#0%ZZk`Q_3A!2^0eV5Vk%6U)x?yEe!b`f_
z6!p5STS^A6=mrjg{#9L{)6l!7yVMTJb=|X*NN(sF--T;8b$34l?3S+oPw3s&@pRtq
zj_w?dn|F0BC^~pgS27J?_WQc2_hI6Ju15oaChB^(fZ{_P(-BFMPQ*lwd!(DV4Wh|9
z9|xXVitfu%z&zG9r@Bnl9i@HaXS#T5S82Lkw8QpXmtPai7rHSMA^B3*=?;<%9ZQ|T
zYh7dt4CU)$Qvg<A*R6G+qTcBy68AkC6huGhK0gIaq3#v!nSRuL>ICYO?mohr+-IFp
z4TUed7gbS;BHbVB;6<^nb2;dh=y(dleAU%h4(glkE3MW`bs6-9#CP4|K1hD(yzwIn
z+)v#q36!VauBBdYh5r3&SX!xXFb3GG^uZKZU9Fd?*IT3CvkuI)ddCbT>-6?hD4Lgk
zCY_D**7u_WD(m(Ac7VA-uc-o*jrzj2z}%$2UxLcptmh^}WQ!iZZG_iB|F{?O{PYw5
zM3Ef&O7>asW~<)z2fXpuSD*;QHhmj9*BYQ-)ei;(^*%J+*sg!*0CR`FKYi4)Q{SQ*
zV0P(mQqAtxPoT;F9{nQ`pnLTN3*mN<KAJu%*{AP72T=FxpI-ym0evog#1*U`PLsP3
z{gS@ay@%>&MFBfpKZ=fe9@6*Sk5U}gZ~X$FBJ^n$A#y~2sv$Iv>RVI)8mXUu2GlYA
z7@FoB*Bfbr;e@__BX|*|KY_E-I1Bh&CAfV`KNjClaHsVhX{LHcKe8*-qxF;Ms8Wo6
z`ZS7v#_E?+2q8{imO84l`m{sPkJs;`LG_$Ii9%uL^+OK>EkXZ`Vip(lS13w<QD2$%
z=P&6)l0jY8-%Wr|SM=L9LH(+J5v?Mx>Dwsiysqnw<&k$o-|r*}cvG*T!R3~|e<a1<
zZ|g79;CM&>jkf#l>YoMz^qziOU3hw5Uns(-2l`!SP;H6&TXY!pq2Bf@m`VDYeqcV*
zhtrXkWc|6@&`Z&0QXt{6-a*F_p6c7~g%_#%A$I`wOuw0qGo<N<;WHBMxxP9b!Lh&4
z*X|DPOT9}DMAP+6=!oen{SR8hXXrbV!PojlIRDLM>etd*I9q?uxmf}aA(E@N4urxR
zJyQniZ}nL;Z0G5{DLRp_uVjX$0{t8^_)fpKF4W)am;DOK4|-3knL@k1x;x0v`tLLv
zf6+IkL8?gqSVm^CUb6>wOZ544*x;)^j1Ikh)3+KAg;IU~Ah`WqKZ1^}|Ij}ekJA6t
z-ws3KY4D_4TV*&*pP#KZys^TkHHNqEptsi0$OFkbL!Joly$p8$(}3|dEa?TA^@gSM
z!1XcAuLqe82Col**=V?Y10tIY-Dt+@Yv@UfN<V}BGHTCZ7&`|(Z8aQ!2X%i#Hho~b
z%`lU;fddTrG!G0k{4o<=Y&S>=NOl-TQNOy=@PMKsy9{gW6s6d0sI?yk_ZW)b!Qfs)
z#m&eJGDIwg-F=2-R2TaVQ8ZIMU>Hj$;erh(>E#G9)G<OY)Nr>qn!rIrFnzWiX2=T%
zGu%+W4<rv6CWRt7Y{;bwiZCqigF+lJu;(Fi)F4TA7>qQyyMjDsa0!Bm<Ay6PuzSLg
zPMaxF2E%p~=A_{u^?Iia4w?s^HZaFPoiPlj<`HcOjfeRdL+N6m#2Nxe!?n17d^%@1
zOnu3D!*xBF35I+$dG3N?@H`m0XvnHc`(Kv~Y3%@W*|2Cmu&)>rhoYjc8eAL0#C3!2
zFDTwH6xW0oHw~Sr^Sou4MrWIE8#<qb-W|gOTIJj`tfHmqeS>Kmk_QG=E9fN}{5$~m
z&`@h1yht*Xj)i23A@DIAeQfw0iw!&X#4xA}xK9n{#?VMLWG{i}GsDm>sIN4`89Ge<
z+)%S8k{1S^rnoN+&Bnsfbi;JoOM7K#{RRpdhKwSV>9rwB2P)HWs2e1+3@7)%nQX)1
z5J2Y`LTE!V*T7Mq{l+jb7iF=(HI$){f1aT}wViwe69&-&!$xc~a_<bC=?4hj8_rUc
z{evN)5I%h|q`ASFB14lrm@hU|$Op5;5Kk5K)v&BOz`hxxHzBXoP;Ng;_T6xk!aqL@
z)4Borr$I{!p2kk$aBYR%sIQF7l}4YZ$XsQtLJfJfab+f$>x@lkG3#agNuR`e8y8MR
zvfg->CZ#^cbvh_)Flv(E%tqrQ5mma$*nK|oHXGm3VC-j{Jpj%)jJ1}4xz%`BgR=M=
z+tKdWHsdEMb%4>{vMxXajb0rgv)!npz{?I}$aH}2G$x-z-Y(;qw@7vyQ|MdBAmc(h
zm$T3KNCI=eG43=J4j6~zf(kZnIE5s{sA>dfLXBJ3!^4Bd9Td(8GrAsv!EobII^}lA
zc()YH!$ympx`Cs{W$%zg8jok7){hxOX2ZmBW5)&1IALr>-By%wnGrQ}(pW;<E~kv$
zro-RU#=>imJY!tm93s)iV(MmNjJtx67i%0y2Xf+!3%&yStnuYE_;lWwu?H3sjCl#D
z-wVbqB@}<TXbheK@{+No3o<Vo0~f>Y6=S>cz`klMcMN&gj7FLx-ZXxpz0h06k_cem
zHhR#jcE`B!GnjXc_h>GC&v@%H6z&^~Xp`)L(L4th5{+eOMgGvZiS}TVjKf?3{m6Ll
z9=(5$jh+<Ed14%x37MzHLA2kQYFyC(`p=A0d|)EYIG8r)o*QS^g5nF~mMSRdOXG;|
z&`US2rX8hM#_AeS8OB#DfRbgj({JZx8_%UeFUMG%3WZ$b^Tx<~W2|-z&~J?%GL3(E
z#zAyICf^uEL6QPvY#kKzov|JrqJD3@KMJ59j0ZgcQ)nE@!2Cz!idDe=WQ?X5c9HQU
zg+YsrlW7@OV)Xk1mcAO7#6kU=ab;C7OO2!Mg8FVOR}OZ67{|~Q=%;bvAyD>}riRp5
zSDAuWLT0t;ZEa+(F?FUPdaY>~9a36nIu{CqUZ$6yk>_n%+zQEh(-oS^_?Y@r+;oE}
zAq~uprj->zZ842(2TWg6qeyt~XPQA1F^8$W5ei#PG5uiI-;_TF3ft_avK_$<Fg2zR
zMFLGDpF@AUsRuRP9j3B06WVEd@&Y1zOgC-F+iN;X`*=a7@f3gAXPQg<o%>BOpFkZj
zxzQFyuxSOYyh2Pf=^Y6*E&Kw#gQkzPQxRrbjUVjc!cFaNz+QyOKHvekM@*IV;2t$S
zqR}PNBvZF_%+&rpWR9DJ12A#IG<q!1qD=lP;nPV|8lA;FWAdRnNVKU|12AJuTNdF_
z#G2|AKt0Yh;2xM~O><s>iZ``m;L|x%Uz%{9H~G`Co&;0RDr=EmFuCd>bJ293YW<2S
zdIn&wn)ZA}a?P~Nkubw*?@b?w+%hH5p@iF}+VlercTD|z!@^yYUvre<p6OXDFz=h1
zQ3vtR)R#W0Pck*W49G{Otpe;Mn+7%mm15f49n@n}qjr#dVp_fgo;@|q*#xjuQ#m^I
z_{_9qDk?3_bb1R=o}1R$>63zVldl1#eq}o04gCxgLkq9hrt|(#%rxaDBFQq<vp^%;
zG>Q899MeJ?Qgcn0OTo-DEggmG%{RTFWmJKw33V6mOf_0V<h?0-2dEDw6@7(RXj)`N
zHGMRl*aL-6rm%Qgr+zl+$|3WM$%~Ha6`6KY3BQ^O=-ksc(`^c(mYVW5K=Hfj%rfNt
zF!>Az_D@p;ZFzZ`m(mP#g?SuBI9HnI(t})OHVs6PR-1cQMBW;6<_vh@Z8nXB`g(II
z#V>r!4;0!b*<fx)4QZqKIt8sZnUl?s@in)e0=s_Z>lDs#n7{uDk*#LW5_sWno=QF0
zHgk)sU<R1Wb_H6X`SW~8Za43x4@GyF#Tl@>)BKngH@nQe=}p;fUON|F>@klT4cGRX
z6A^c`b3x{-HzBjne6c_L-fvz)6V(IeinP)THaC3*D#W~i#*a|*F`645G@p2eB+UF~
z2o%E2x<oj0$UL1slsjyGOWO_+=2^7)am2iec1DhxTf{;k(tL0%sAJ{|!{FL+vpdDu
z?I+CDX@rb2|3T;fPMSZ_*GQ+#9yaKoHhcDj#u>9F17(UfU+9Uv7;~#glp@yrz=2}N
zncplya@PDSt&!r*<7jPl&U~*Hz|NZ!>4TF5^BUUHxL~%<f}xA%>mwj?$?Qj4Y?tlk
zchnbLG5gd6_o~@#DzLAaoAd>B-E8#)_6>8WJM?dwkFA8pEweondAH5GsPnjEK714P
zbl2Rk4^Zxz#|FT}ee+n_HF;oWoDnH=elwsvG*_8|yd-lE11vl;Kl_9v*=#S`4aF4m
zsanW<Y(B9EiciczcR@WhZ>C-+)qHUX>^?KQ(KwxEj-c1@x!G)l{tI)ZE1+JQ2hhAR
z-CVv0L|&OU(Jp+3xz`Awyf!cX0L)DD!#c>zGPk=4uxxWldr)u8W9)Re{jE8-KWaA5
ze2@0s^Uc-hgnxnAKw+PE=Er@Jyf;rtfr$_1cJwKFp?On#l<A{+RCAdBWS+JcCO(^u
zNig`uoJ`eSWF8QL3Mw{VJ_xGB{F-J9U(Fr%1MHjGn?~(YbJqykwfSzoKzj>6%sX6Q
z_ounpSGeeDxnRJ<TVc6F;jxvL%zjW@WieZjx7w14?=HDDmK2)*t+kA`Aa9-Jn=|-p
zSzZJbZ%c3Lnbunhe<1O(4Co9mHdvasg5*ZajNd?QvQ+h=@5DD-meARWEtVLnbzjR^
z`Uwg@%ZnvQ9G1M!U~aX{r+JCLWppC+w^{BJXn>_3b?1SWMs(_6yQK!L;&xcd(^2!C
z7M_ln?6Rzlhx%^I0UwC$u|#$N%3jM1S{4LZCZeCQbNehoba-gLCBYx%Jz!Z*<qfus
zrfF4(W$bd)bEqXJ4Aeo(ts$VoEDc%%CfqV@2$DmVbDyDp*piwK6A_kAuR$HLnA^j(
zqn56r0E@KrO#}2X%T%i0;}$#p48RG?Y}#zKM_F3ULuH(_j8H@Wl%;1Am^f|e_YC@H
zEHk2EBHD7GDySGsGx~%f*0Sv*^y4hc>Cop{ON1UU@s`gX&^u@OMnUrPmMUMNmtZ-O
z28BzO^|?^EY#DtLu3fRX(gE_TmNw6zcg=1Y*&iC$En{f(zG3<83KVZzuG9whEsIPa
zjo-G+q*&@5%a9E)ao2LY1wijv(vv{lx2(cXK5!2#Tj_&_M2lPx)&0;C_yFojma6pg
zNRKSvsMkxj9IXi|#llU3$Yaa+K@fRju}67>d}>Lk1m99EtLWRXXO_k@L8Vy=XrO&=
zY4Q#Zzp%LU1NGAKWep6bTP6$u^~$odEU+^yQ(6M;wI$~(e9E*`rmq~bEd8hp&bDOL
z0A`LQXckJAYia!uU~epranO5f`C_M2XnB?<g8`avIk69l1(s8^`g~_Oo(3=8Tf%+=
z^}%w7wy_H>FX)?=kCuw`HOeQ;$T7(KY?(yIv%gpdodmPU5>H2uiY<%iz;1~pf|lN2
zEq%K|<eMe9A(B$dvP1CxyX9U#s@Wfw72&Y^)ACROwx`vEpRwRpSQ~i2;g!}8&!Mr(
z+Hx;MR$Dj3L2-?B<1&b>wVDn=WS#YUE*$l;&Y~H$w{=+?V6L}%b%ThH^+-O<Z?F#N
z2b7K0a}SYhvi^1eD4VU?UMjqQTdad=;^%7}`Uq%#*36lZaadiJ0d1@Guml)?YxnsO
z*=Bt?0reDM?RX0Y1FhFLLUOy6+mE{3WyLp;c-5?(J0ow8wL=}`?X@<G1{Gu-P!-Q$
zpSAE7nES2bCqN&tp7NpZ1cI##mcg44>z4As4z;eB0xu3)uh6nF%(@%1Z!X;0FA$1{
ztjRBtci8%r4*W(~*Vcx}5v#Zz*hj72cR@v3SF0g;%zBN+<m1-XRO}PhS9CHb${NH$
z{iM}EGuu<v7qrJ^KW&YtYCB^cLc0mk*54wK#8?xXqA;=6rnD&#XPrpl__NlH?nvUT
zORFL|XTAOf$$4uh+SE?4UZIfe1#6-P$wljFTI64{-k{h2vNeNF7GJS`i-Z?ftv!E%
zYuBttJRo`9Zaqt<=Wba285H!U^-d&2Z&^3)M44_|e`yW#cdV0Wd-ksN*QGFc&nnCU
z%zf+G+mL)<{flBMiPlN9^YzdgnFh%u>jqknJhF}`Lggo0!*h_AV*QgojD2iXXgTx5
z+JV-oPp$UWGvQ6Dbt8Sq{mlBBqLFFVPt?kuTPK}_YcH&wIzsfNwSO&`Pq#{W$a`fS
zasx?*btnA_#A|C03O;38&(ii#mNl5ptz=ub+<|L3){ytW%(V(Wu<*wEfaWJ}tuMbr
zGSB+Pj<379d}~%mXcSnzWWc<$p56ez-&=3fg8qZ`R~Nt(TCY))|6=tT28AMPR5$1s
zTTAFjK#6ra9hUfN&86=^zFBM1SAwP1mu+D1yEUmTs2|pTZczAX-97*oJZ-TbP?i<8
zm78guy3*GA7+_Y}evbmR+O}XNOsuh0qhQQhTgg7?ud@xHElDq%?l%<M+qTUG$$Hz?
zEELVhmU$J9Zm^B(0rMMe)%wHHO}2<UP@8Sns9WD++d^R%Uz>X;P=2=CG%7i4=g-r3
z0$Xji9l-Xt-TMOb+iab0BMGqW$plQGt$+>?Z@1}Z!QmaYFp3K9v^ApEz020KF3@({
z`cjNxkL|B}5ZP;ckb!~**=Ev&W}nUS6eZhlTSD*10o!DXu?O2G(%FR&+aVl@v2&re
zxi0{7&^9#=pkX$N=G5Uft^#BZ+0N6DbJ$jncEuuWg~I@I#Fj&|!lSm!pO8e_EOhku
zm~D46B*$&qV5pz4P5XenC|kXuV4k$imqDGf4WW?CX<JvCN}REUTn3mu+V+1qy6(6v
zt1qr4O*2b*_uhNZvMkG%R#uknrDj?-Y?!63mnlp3UNQxdp$ypwh%6a`ECEp&vXmtt
z8-CyO`|Etpz2|(-x%YjZJI+1#d0*TBnOy5Vl*pK8onr?V^R36-AX8xd%(KuawC+Cy
z{d3k$TOm?p{Z2U)imhWd!?hCY*?&=Y-uks7D3n^iKv_l?tV^B)N}2UsHWbRO4^tmj
zSReQfB9+!Vl7Lxd9g&X?x@fU}ClYQ{TTjw)XN`3TedDjzdf+u+*I7H$w(64g+q=*+
z_0}v}YBpGReTc%#*3NY1)M))S-C1g~ey<oJ&DQnS;I3FV$HG#Zb<6;M$#!e*I{4dR
ztsO(%RqIh#nD4Z1*^9z!)|S(+!QgdkDLq#=tas6tt;;%@($>1Ie|CgVJ=PTz1nRY3
zu^);zt-B~Sw9mT#GwAhOOX$%Xu)agsgVu-MMBR|JJqy^ktbaQRk=xckXF+e+`pvHa
zHe&rQZ9Ye>?XuzhnDq~qJZOwtAEqO|JJ!v#m7cKPu^woX)~|j9m?`Unlmu|sI<f@%
z)7C}l@NmZZMGE}SS||Pkv^ncTiQwj~yUxMw1?zk0WPj0GPfzudb*BULmaS8}VZoLW
zC;?~3c#bl=?HQXrDgDfWu~r3xj*OA};EWT)s|t3HGOF0H<ji=8TH(TwJPc4*M$Br!
zxG|=_fr2~Zl@ur(V`S4V+k;W)1xZiF=1$o4Vr&k8h&SW!$6&#Sv5vl>;mf$6<`F-J
z?l46B8R^!v{|jIY<f1f?5#0ssAjZK9Fdxh?C4dWI7-+v6$`G#t31c`$z*0D)Y8xy?
zFxJs9dz|rBBrHWT-gp2cit$Df)T0?*lw2Ic_~HL?JjU!gcoD~lrkCmj<L^0;c!rCK
z)}INC3v1AdlZ+BN*G*(Bc*2=ejFYq_PGV&51DDMB(hQLl#v<j@r!tPL2ij@IB;~iB
zVZ_q@K8>;M5=7D&uTn-&2II|C6lOAppMXzi8T~;}$YNZJhDbJJ!yy#rF*<((vE(z3
zQUJby@$nEU3mF;;=bvLF$w7)3-t?;#Grpk(dI_U|_UGprCOY*jWxV$*$OVQg6JC@t
zF41+>at4<oLluk{TA)|SxJp6eDu%5D+(pKp?&z6n#ykbtY8ZJt!PQzAyC{jSj`0FM
zD{pm)(MX~GdWN$Dd~0B=L8hA3WyU0hSQ;6>KMC_qj0ZhX*UU(yU2F@(VG??+jCG?x
zyTT~?0N8Deg;Q{*osmHMunxw1{;0dkSSW;RoeXv~EL>yU^9uB?Gc31m0Okh6Za4a?
zi*fxR6uTJ_&am6VNO}+&y^K32L2fdhwS`C@gGrnIe#XPJn;c+#@B<VE86$S!h8Wjr
zGkJ@_pj64*j8rkmFhh0;3L}gsC`>%c*hc3;V~o%4h2A)0r)3x#cNi=ldT4^tegSqT
z8PUC{oMLRD;o~kN?isXVnh{JB$qZxW2{<#$$nJu{ImQz!fj!Uo6B#GC$F8AVwnfGe
z#k`gn*ODQ!%<!jE9$TjLU)0$#UFbf%J=13io#4O>kyD<kBl9-~DxH}7X@PN+x%xL~
zI5S&|V9ABq-w(U4%+Oun+?Y>i!C!agUdq5Y#!TD?JrCxsKR`U04zwTgVoLj<;LZGS
z7|=e<m2@EF%k-d?n;+AL_N4wy1|{zVFuhhjv;!|5b8s1K5Hm;%6T!^=Z$m$X`9dK~
zgfo>{Xhj4wjIQ+`XTJFsU?Q2j9{`DBM$?-b&BV7I@TxHjK1FxMGRuGSTWPz_Qj-V0
z1m<&mH0dPM&Jq2a$lO7DfK$vM78H`0j80%CGp+RK^b}@5AV?~68yx_jW@gsImov;p
z1yItM4TsQ{bY?J(s~OD6I5?Qe9H9KGv&?6zp^(M={C;$LHgn4ZFqFgm(Q*`(xlA#|
zsq&cfwE50w*6xD&0%n{)WD1#cW?-LV#+8CAVn)!dt77K9A0b)7-2N%J^UVG9g@RHh
zD+GEMm^IA+D`Woo3))%E-1{2rRxp3BM_ncJ^Kfug%=Uu-yT~jowm`9(+0zEUYnb=u
zL9v$kc_ms{$Bg#`_9f<43We1(cW;9i4a{#gfV<56GXmY!$n4q-6HUxWIudMVUcCZ^
z7UriIuB=*_o~aPI!aP86j5g*kbVsqB`8MsCI+!DluyB?6QX`!|cQTVHz4jXO_F0&}
z&Mf>0+zn>PJ>a^SSLyJho9RmVk3GyClndI+%%pMZCi8YJ>iU=)=&D&ibCJGjFu)w5
zG>}1Niy0<{nEG`fx0vk|1-;FDmiD>B%*7W0J;HqLBIW;&G9A}Ke~c-jGoNwho81t-
z!)$#S4o@&o(^7tt=||D{DW<;_di^f*ExHao%{;IJy*9(F--Wta=9k-`Fvl!@3kvg0
z+lPU<#LPGXZkhS=VHmV!9pb}+9c!rp>h`QMN^`R~uy{<!II?o@MWqvqMe(tttS+1l
zSUI!)IDkSI*2{E|<jQKKTthdOs2U>fteTZDe~i^R0c;P}k^mx}tgk5)<;D8vLzwVp
z{Z5&kKCA@_mie-FeT6>sW5v)C#Gj=r1Q%doS<{v_khO+xsRXgObQBWIa-roy2x~Ph
ze?wU;`i4pv>mwRh!&xe8fJU$q&w?Chy-ue9k*qbdkc?uvZG~Pm>xYX#iD6Yy?m;X|
zL#bVHtRp@kCs<Kxh{UswWk5ZFW%+Fb=t<UkN+wHWElZ(sigm^oJ|(fPQBp}V>n6RM
zDXghpkW?0rR_3Q!ORM428P-WxNT#s_4$w<yt)W!Z3|4y*`YDrDZ-N(RS+kUfk;Pg;
zqfRy}fx_E4ta2ZK<+4&OkAcl&{rLshd{#pSNCB&XoGD}-plrKyEM@`FidY9JNLb8@
zr-P&t)>E`cJI}JB1zagB_FtH|z-pp(b{XpnFSM|n^?e%5SFoJquv^JWdk-j8tkMzK
zyU6OmlwnoP`g`F;SgK*Ya{_3!tWRiMu49eR(&-ZGObcY{S?i*~HLxCDgSyMCVTv;~
zvO4@x*TiZ#>37jlW%(i=A|0&UL115HJ(>#1PFCg-7`(w+RSpYXtP~_2S#`5Qolw`q
z8l%8gFYD|b=-p%)mcjM0UZatzpJk*3zya1TG$#(SUcffcYKWCR4(=8!axeV6&Ds?X
zGR!LVMFU4ziI$I{Kg#-j2-st+BcG#koTa2InRi(0DF1(g6;Bb1N!HIr=$R>220a&d
zSv$^wOtbFOqb)P6itF%xmNhyHGRJz5!c_CDG1?z5u<lI*S!7KdgTW=%jWmcXv#M#<
zwPinikaB43*uPWQ)t+5S{p7&jK?{3F_If_NaAMn1Li$m*s2@#pW_RbH(1q>q1W;G@
zxk%Kxv299V(48GjE52iFKRP1wV1Kp=mOR-rG$(qo53PX(Z}!(mKz!J7^iKP-4_DI}
zq90o;2AV(nl_+2bu%`}z3uNDUA231e#|Hr#%x0N@7Qz;W!L?9!GJSR|j9o^1hH!S)
zUl564Bkvk76<b~g>`3;%bcP?ret=GzquCe#LR}1dn7%F;%RYM#48^gNHr#_T>;yZ9
z4r1fkCmhfh3GC`xpq*r|qAbcpcE&$YJjFgp33*9uzW_)kv(qReJcaG`8AvMojbcci
zW*<8Y&@=20Q(z*E{SYMyrnA4D17-&M&!6CLCVO21`tU6KgJEE1vDv*)w`8;HZ=f=V
z&Flx8%Z?pIWga_?KKhW)e*b=G6tK?)!)_t_r)q$nV~0Hou88eIsR!rT+aypgWv{M*
z+ZWgkbcd;o?K}c!%Gq!G!kG&8%QQ7svfb&Ou412m8JHK@Q5}%1wy<N|;bIN@?Yrp9
zTJ}@h!PT*wd!TWN9cO}QJ==;di8ZjBHSp;&d+lx5ZDe~ZK$_UMC}hyg-kSoSTG)C1
z5NTyw8i9R<J@+>B+Su*4VYi*Vc?EpxVE6rhrO5t{#)3|^<;Y5uUSn%s1I%^yBY6<L
z!IoVIS{IxBGrFXkJ^nrld)VES_14RN{aYy9WIsXsr#|-YbZXzv)>7{20K4~96b`aE
zqi}nOJwfr^TkKV|g}%-HLkKd=e!C4KBkcPq{xHf8wp<6=7~8)KWSsrdr?7N~9rge!
zC)i1K0G(vtW}|M3z3VA(ciD?u;pjA5d<`NqY+F*FW$Rvn!8vvkt@P&EeH#2C3v9Rd
z(TGL%%P)XiV&7%M{4)CrE$D4I4Z+~-IKO>u0c+3MOE>2oIFoci*OBuItwNnRAASI|
zqZ~K-8mcoV)Clt~oR3z(k}Ib<5_)c&O_b~4&dC}8cZ_p`4x2nUbxAPj$@#klU|yW-
zG%I*>{`?${`f$Wwz^*SR=R1h_aX#~)Zy5S>62gHUz;UHRxj@ddw1yAjtf#z@V9w(n
z&<NqI7r;^|=kHgb7{+mN0vFDCWiLnsM^D@A<DAe9a66LoUp%-d&V%2eE}9chk)1fs
z`>l9bPH+ZEA)d3l2wVcE`W(eZPI9{FpgocEyB40F;+&#IKoZC07TT1|QT;!Ik5fla
za4P3MUwC+$vo{bTXE^SA;aVD}qYehsIUkUt85|)UtYmWfX;wMQd6RDAXK`LVh{9~n
z>o35W9L~p6Ai10pI#{vfaYF9^EuRzmJzxqr-%W!n<k)S1`E#864}cVLf?kJ*#hl7E
zbV&(^M?=GT&K2s!QqE6n0ds+4mw+~vaqdrnWI5+~+VWR$ShR(%<b*bZtKuBW1oTDD
zsmH)obB@!fRb%03=&h{fq|~8>b)5A@(743WQ)slFV@IFAYT)dgM%`sjl^%8*IlG^M
zi6+inIzDLT?55YSg>!WXdaay2^hJRyoQ-r=)y8>^;=ApfUb>~&!MT_A1y?!q-5{Nu
z6k3yB<5<?lpz=D$gE9wia5A5PeivsuU9;-uM9;!*4=0LJ*?KvvDBJBOr-(jF(Z|Vn
z06o*ssZWHZ0Zz(Z6b^E-K19=oINp?wdyBK3=9=4_vpb<a%z5NVa3dT~%JCiL*ib&v
z80RqywPKvZp}F-AC%_h>6P*2QI5WxFK#%+sr%eUBcR5kCr<~@Tp;O)&PWq?dW;s1E
zfSKd8o`Bo)oOdXWu)wLMtDcJ-t1r-qB~FkXJY41^JAl}7k5T{HabqfB&z}3*S(^VG
zxT5dj)KP9R#U`D(hgJdGh5L>-G+en^kKhq<<F+{i&7CXtgr#HLtuH~(gF8$olb+ls
z=zznE`{kPu@#gMT!e1ZmNA!oFzT923Y4+oOOYgluHzp2}0o>>5fFqFm=|7ai9mE}=
zty(ZwM4O!u?hw7Wq1@G!Ivd8d{T2qpxdJDML~xJNY0YtNPBBbGa=lBT5XEJ^gu-ZU
zi2x>IxCakHA(or{5V$yQE+vDU;A$upJD&SAjUEZyLAqIclKTwS*%qrr?khR)<`j39
zHf~AW^^PFP+`M1mcM5k0^?E8dno@X9bN5gZ%o*<ZFtF3OOSC9W=U(gw$>3@{;Y=ns
zh<1Tzx!+NUGK;&9;*Z(fPbq$w!#%JCBDvhR=poJHe!B=vOFlP%Vw(kA>7&pn<jzwN
z=p1)86N*LL4RnZ7%sn&@u7tbg57eFK9;e~1l>7G@pk3f*(-yjnyKWuO%DLMfL0c-g
zBQEf%k~>C8U{ze?kKo1Qeqe^(YVLM=!)v%RK|rasaQ~*{gF0?A9fDlq27AC@J@+u}
zP#d`SQ!>|O?k1Y!8o5CoKx^VY@E8=Dxp%0aTe!PoAkxZRdI5D;xCV;<w{fr17P_5l
z^%q1sxKW$IUFAmI4-Y%Jdu-6$Yg})-_IjOb`JA=_H@IFmz;<!JC+u$S<MfjBaG5^<
zyO;aV8tC8TzFQB)0q%Vi4jklqCxQ%dQ|C~4i#tkLGq<_bbZvc@yN#}jj&R2)5;n@c
zvl=2}+<*7O{5bc}kKpcb7Ym>;!F|rs2AN6jOTWUz6!%HW?zqbhY(?))bMLQ&%nWyH
z8d@>S^`P%+%yFNmn9MwPFCAbla6PbuvRdRmN^AcmZWe{9mbvGn0cOi%-wzQx-en3?
z+4Ir^&?E<*^>=X1k;i!)&`!MW74-fc<ta2Mb>?~Ohl~sF<`ocE-cujLpc^lQCK7kv
zeV*|97;o@3D0uLk@K148p1eN#IGY#m9~!m1c``aR@!@T~7ht|TSrZEVc;j@?=g<53
z8Tb^y^P}Z!Aa6B=wS#!uhv^PsFz-JawnBK`bi^0RI~oPw!gv+VXiPZo$uD6yg7@bx
zU?1n*xro+B@+@?%If{qyFkU>Kn$DwQc(!lDL@e*oGLSglya9zLcy>R7i{}OZ|1%1_
zSsGwY^5S<wFOm1lRmx2{#ap@t^GUpeG>s<ny8VEi!i%C!a4N5_2i$4i2HH`d;r-GD
zv^1WX#*}p4jaBd|gV(hPlF93;2k2Se{$eyDi<fKzOW8b|7D(psO23C*F7Kb~K*{5s
zrgdvR?|mhRrGOXt7!(V6N9YLl9M6f`Tg03B0F}kO8!y6(65a{QR5{OUq#ai&@70|s
zyueGQq@gn22;CVe=QYq$v4XcW27fQ|4s@fin#T$PW(}{D=9pTZyBZ30yw9AVeu)>>
z2Cm-1OQ+nH23{vEP%iT#gQ3{S>u!KX6EBgXK+U|D=>2WseU%Iotvmz0)K_>_OK4LY
z?_*k3w(~w~MO_E)qinc+mFG>H*iK$Cy%pDZoqJ&6I`0dLmEYjKWd`Zu`AgBHZl0xh
z5okTU*A7FYmq&jbZFQ4pyA73nJkJAgrk|HV%^u*{(sFW;_iGgthIr3Wa^fxC4{M-s
zo40|ENr!pgQ!I6a_u+e}8|8)2_&CP<y$mShJo&vKcX+!~fil5!qBY_qPhwdQv?<==
zQJA>P3)DknnrFQSGBdn&Mxf2|k|;4~j<=0g*z-KmN+>Sy9(xC^U*vhb2fItWgg%gE
zo@hG?ZTX+MLcxw-Q4a-szVkdhbl}Gq!Ga^di!T2;@%Pbj)=_?ax&_pk|HL#LcH#Sn
z!>%j8mKKR_{7t>kcjv1)z&^(JO91D=ziU99C*R%=#EZX=ekN~z9UUL|@Yf!NU0?oQ
zdk{bVGkajypC3WjB?9=vIWQl{52%4&5I=hgTrmINF^XY@@Q>3KtWZ9iRxM%tovG-A
zaQ=ZMa1s3HKY_+^{y#J(MDoA=8YGJEM2SJs{0~;aQVjpsN|=x37hZ*jar~u+(9b9M
zM`BSI&)-6u$pn7mMv#;II*N-W@^wPgCG&5dq8!o`{#pu}rSd<e*vx7Eff<l9d=cG4
zOXI&lHzU&dA5nf#20v~Y<}>*_?tyD(`GK*}%i=fDbe7E*(MQg5_%G0jbuND${lQKi
zKlLw&<nxceiY68C3;zUWA^#f%P|oqEXtiP~;@?L(ZN+?HJQPd#UR}UG&-eHN4wv%R
zc!9gXpPoQn8UOw-!Ikr!=)k>#FJ{2eO8&0{0IlLHS3=|>KX?W7s`(QX)2ZS6WI&;o
zf58OFI=;^!>MrrW90XU--$udE1`GclN{PG7kM2cjBfpmmXPWrEQjli;C*yFjg@1&m
zl~(?057@oJ|1<!KZG7c2n%2&@q0m7G-+nu|tNhfBsO#j<?}y|y{-3L%ex1Mh4{$g5
zo7CXC`1=c>(9Q4U!NVTD<*Y3<dihWN41+iMb#KGrKK{4o(U^Yz8aWgP_&?AZWRUMx
z3H>2{cr7g5;-98O_}lz1=yR3B{Q4z$IKqGaX>g<bxN(S#@%^6zH_qQesegC)%Wpto
zf?q+gnMwXDzd~e+ueQ*bbeCV44olPgwGEJ&;ZM84{4C#^?wZZ<!;V38p1*-YoC|y<
zrNA!oH`48{CBC!*>dX8o8uM)h>!v~M1mm<|wHHLvHGK!cXLNhkQ84cY&Pm{*N3)L#
zZqktNEKq$(J4P3QmWE4L!8r>3xe1;qg}%F>m?i>GLG3VF;U$QfMV+_c62-@S1n+Ew
zp08jZEuH)X4HO^q7u*{Jg#f{SGa!M2RdzrL5?rP&SFj+_9t{i;IMP9Vs386v>cRxK
z_R}|H!UZ4FF?xhR&IinKfr0{`kpf;Ke2NlmrJ!cC;5*ui#|YZq1s5w=nFBB41eLTE
zKOy*u0@Lw=osYno1i`UB)SVR6R6rq7aP}jBof7zTf+PuM4#DkY!LSEVQUvul1-DqG
z3Vv3=;nRW+N=-W>sGtilX@aS}AnAhY2LPHOXiJBFrr<q4V4oFar^Ed$!AC#CZnog@
z%>d02d@=-)TtU>Ea63;hxr}D#3uftAFA%Jt?6pF{YC4rZCurFTLq!5Vx>ji^796H$
zu0&9?7K-Nu**8H-1s_rZ*9E}`v~(*IC@HQ`F7W7wMui}d@^mT%D``Nk5^OvM4=)PZ
z=$mrYf~|B1zD6)lf!bO@rZo!d1l#Bs?UEp30DAR;o5VE;R+m8ivPH0$?kP12mMQC?
zNw9xCWSRx99fwSd;0qeIS_O`jm~ch#Bn7zI1mn|aZ@WPJ8n8PA50*jlsvwfG4mt&=
zlOb|V5J(67*9BjEf@a?kNFN7Em*7(~T<aD*L3`*Pf&K>6dj*zlU!wA+puYkp`ULiL
z@ZB%Cn24So5cre9LBVAyM1}-!z5tP1g8%lR@V20w*7?JNtvBHIm_V9~!f}Da|K~Wt
zLF(BFK^xthn-s_>{xT&{6+r#2z?M?erUlP#fQ1>sxaA~DX9ZkZW6lY9w6>iW-2W2{
zE(qlJL1s~Kgsylm2?~A!Sr!cKgNUv0vE6XgPWan;w8CCkP6_1>!pYk}aTEs98G)0~
zjh078g_V?`<18$py9h2qOB*`DRXEj)Iyd3MGxYws3%z6@$As^+gLnvEpcRd$kd+C)
zy@ch|U*5uN6oT^+X41mbSGdXuOMb$KUI&`LkVDzf0m5B0&;$xqlnoXnTxf<~u<$=K
z>OzF0bYc)H{F81chY3HUS36u7`V-}bMF=%Q$Q&2O(Wn_I^r9g+N*J{OE?Sto1$8mP
zkEu<u!faY+#0d|_f}9X;pou<S7)C3<1mSZJ!^4xpc8XRf3ZJGNgj2%4J@7C|I8U=u
zvhd~uKuHniQD`<*xE>FL#p<-smyQw62shCTpC(+t19sDe$0<=JL--LLJ7x-}9)%ZY
zh5yN5H%s_U2K2LqPKB_PBkZG)VXp8S1H8x+4*vlY`N9XhV6Z^g{|KN9g*hUKoD*K4
z=uweyhPJfD!n4;<XDJa{+riR#;lJh3FBNvsisXXu3S}LX3C;14DHobvL0yHg`Xi7^
zVc%{PRteSjfLs*XzX|MWVO=}wYJ@K(fvXiZyTU}Buxk@gE(st10_3vrwkO<f6s}Ri
zUX!rG8%=7q2m?<*u|;@+_Oz|Sr`%9^MYw^&&27SP14z42PkXfvVLPQvT@}7`8Lj9P
ziYTMtn($eQyIvRe(}Q$FIQu!g?-J?^!0r~>z6kXm;TLp2uveHuL&Htsmw!Q|PZ*vJ
zy?&u(ktVPKp@L%WgTm9aOd1mYn}~kCCEQNmI=C%NqLuEj@EcmBjR<2RfjuhBI{}3;
zVevk+cU+is9U^yxKYW3@3E@X{ZFW-l49#X!!WHEGUE$APz|gethl7Bg5tdOl<gBpK
z5{CB93A-qbdS2*AAHrG?YMzD0qVUc4P`4zErnthg(B>zg*@|ALAeNoz;c5_j(H2Ur
zb`U*K4LwKEPY&RmMD2Uv#ZgiAS|~V+q&BE?5iR+^LswB{9WdQQzLa+6E>cxdZssvj
z4qX!S5G9JC;VJ4Zf_X2|b=q!wi+-Sq(?|3n-9+{kJ>CojKT&rHIDgS!;czWL^vJt#
zCQ#%u0}>>9g+}mT(aBw?3laV40rgN(9xax_M2R1uE?ngB8Mp|My&uItkBbi5LNroT
zPy6L4(KGm4bE{}k(M6!eh*nW3I#%?e4GhMKHgrMcglIQiB8nIJ(aJnQwDLR(Pl}$S
zw<=MzjtO!~)R=`vB#9ho3z97Qg<|z7q7-^zQ$-7uoON2X%ARsF&xjHlVJS`2MPa8*
z(fS7HpA|6*pr0k$dJ8056h%XDj>!Em>T*TP^v30ho}&<4zGx;Dbp@hF>E1%2=*WZU
z;B%t<gQzPK{ZtIhV$t?^pp=LbDZqPP)R~61l!`idAeIZFPbdUXCYq*<%W}~tw9~8*
zl~5d|QuMh1T$M;cUktt|`iG8IsznX7%c&8qr<GK#sP1>@)rl%8W8{*k?^$s5qJ2-m
ziw03CZA~wW1a#e~QFQMUAWfprDQ?p&3V#OXTP&hoxzK18efSq1$Sb17QB<~xI%yZ%
zE}Ey<OowPay-rs}_30p;qA|)UxhBfkiS}L>1yIv&h(r{?=n{QT`;u<anP_14h<>F{
z-}H)((<^pUH2Mwn`b6t!-`Ou(N5`ZCB1<eCpA3q6AArV?D3roZw?v_o7Ij+`P9gAN
zQOM`08xh^GhKW&;JH3r#qBHcSkBg=laP*ESks>t{qTeV6Jt<mG_bI1DzNBzh^lTgI
zrbXIx7@86NUJ2+~QPmNUIZ=ou1$182Mgg(~(c0%=eo^E?!Lub1=XtbuS@dT=%-f0&
z1_0Df+^`HZd+|D2ggc1c_|S6{zeZ71CvnOZkfY-FC1|#@c=I(77x4$Q=W!L+(;aI!
zagaB<%U!(qEcA|vbMD^{gC1h%cYx+8{*HDcUgCe~+{0VUKM5HhaTRS%eZ>c9ZuJvy
z*bkoq#s1;og2Z7o_6CbLA4g$`STzo}L&fSx0Tw2HED!48;&*6m8X@j|*-sp^&hp+e
zEJTYB(P=`AIBgK>vEmgpq{NAzrM>qF@znEBj~6@B;x0iPKvBArVkb9%C5l66hj>c-
z&jL`A#Gma4Nfw{l2kR-~$0@NURm`Qd&(q>iT1TA`fBzj&(!{rDuuK=*TdL9e46*g+
zP|OrJtKsiiag-xKv&4blKqFh6Lf;z55i=eGmn-&H06S0o78m;Y;-?-5c7d2raiT);
zV-(FiC%%sgi^QGo&?^?-9R^s5_^WA<^Wq=2qOMfzL0P>Q#G-k+2~s8wx(n=b@dMw1
zs}TQT51C4FTm~#viTC#a^rAS~0>7)p^A!845$}2(Zr6%eeT(j@6K_vL-6iqF5tyhK
z+t6~XL0m*b;AOEp<)$=>-FCvmCh;MP*f)!BNKn@zUT~wEAg$uAcvM~yd(+CGO&ps8
zyY1o#Axw0LU!<hSt6~l9p*zLCG}>Jg|3T5n>*6{J8Qu{0IKgh0c*pM`-Qs)bETu=h
zW()Ls#o8q(+!Qy`aaf=DqdC;|i>t>_I3Vu-n@(E?#kW*|84`Ph!na#u^S8jhE%y5X
z&J2rv8c;VPer`APN5$n78yOR)(;wB0ixu=7-Vui$1=@u80R4@`q<GK+ZJ81;>%q;4
z18HF~EB<~AWKO(BfWmq4y_65XAa12zvn-0wgutmKaR7zxmc_CwAhwb;516-;ypaz@
zd&x0ZfI3LF)9~sj`8y8=oh0|A!L_53KPU0~I7>3_1Lq?7@&E6ZB#joTZjx*|uydC@
zwGk-CB)fN^&_lBCG!#4~5B-hidRZg^O`zVAy_C`FBgxB!317*J+koaLvFt#dzvK>0
zp8=BRp8^*s*^&bfgCs{<02(aut43Xj<S$wZgi2Tx4-b<le}hQ4q&F3H5t1g#ZaOZp
zZbFkHCGXt;N|c04AN+}ySib9nVvOY3^<ZNqtG5F*PLdH0?u6v#6`;jSdT)ayNH~-o
zbyD)n65LOe)YBtyO4522T$1D-8kmwL(G4g}kvvROda5Lr7VW1cAJW3$jN}N7nQ4+Q
z*=Sihya#56WRt}J{Y;5R4;(%#>6t-kmSn3pe9D$EC@nrmGC;F;uEhCyVCP9@9Z{Dr
z`C>Qp3M9`gpsrBT_9VzT$y@7Tw@5Om#Zyu&VbsH5iDc+4K%bY4PNA+;;`As`E=WGw
zfwq)MmLI0~uUv8wIoVbfl7006t(0(RlT;;9xPV-g6e2Uis#-GV4!>(8{j@Hrl|&Z+
zv`!LFi9MGj<CNi2FIhYfum;J!l#X>-(z_dajgp{UaIHzQk5*pIlDuAsv`Eg;lDJjE
ziJ*VXYnOD>eBB{QKMc{Ul1&}pIwkFE0CP?9(Mh!Tx`ev|+zknP8(_L5b-%)3x1{4c
zc-SNP>Lk4Am0U8Sg*PQX(%{!8v8ETVUm~A{-hkxa2Ov2p$^Q<8Ly}DqP`D+T|7Qi>
zzuS@&6)J}%r#^shBN8vVLO&`o{|CEcl0J9z*SKU(51;NxT4+NtA(^IK{-k7o9O|Yd
zb|P?hB?F7_X<8EL0S{*+F(0D4W+j6!19MLD{=dMSm%LBQgaye@C9t<B+4KgSu`Ega
zE5R;H+Vfz-R=Vn5z}QJ0=)#@7^mZ!H9Hdui=j14LkbyW!6KLK%Dy^9Xah66=w97^M
z8--t7rJ1K8;wDv4WXWA>Ho&!G(oMgC^N?<(N7hq%g%1%g=@g}%d0V8zb1>l})zP}f
zSGu|k=KZ99Jq_Y7oumMKfb^@Qs0)<tFhe6qx?(eWCRqCM0MJ6DZ__UtD&0fZ2g0PK
zk>J9mbut)?kp7+rOUI?Tl*Sb)<&8olO1guFjcBRK8X_@Li<pM3SZP`sK;xtflm~o5
zdi8ZQCSH1rvVIbzjfc@eC#6LPfSo8EHKOj6)S3p(B<UtPKS-7ypusvtTHXyysnU$M
z!JU?-^g!f{v?dOg(xfi7FqAG`CkK}y-O!A-WJ*UZblh@QTDt|MS<;x@@FH6pnGG*;
zq#K`urCe##2)F{N-Wiq(rB)2UoRfaM3qBP|ySt!QEWO?YloIKl29Wd8^>nsgDz&)6
z-wRSNnm)^<_xua6a_QbmxK<$zq=jFl^xZ0Y|Ei>+)aw_e<&;%YE#0sH&>E>LWh>Q6
zw@@^sPAa5u;3esv33yR2Z47{k2I=eP;qPT>CFSupN^vHDS54Zy9(v8vTRkw?BK@1j
z)mG^`+DTuLe(DXqHfcK@WwuM(57JGL4rxz3Dz8evp-l8nX-)<zuSp|B(7!GnKLztQ
zqycoC-6d83|05mJLK=N~q}%CwbFcKj)gU*ehiOC6Cl%7JwO{&pHxve>Tv|B|N^@z{
z8j?!hM$2wVKc>vX+tRD~H2)1t=WWp$BT{(^?2by^N8tXLl=D3l$E9Xk{oaxONZYUp
zX`llXC#CT*;HIRhec<j&{g&bAwDbd-Bxa;zT-41<9}ELGCv7eO=Dc)A777=nZ!-Y4
zD80E1=q2eL3Wi#irPtTNpsmdGCj7ROeKr8jUUq=)D>=wE>;>m2YvIB}C)orY3m=u)
z{C_nm8=<ktMfULufV#?>>S4l7mi;gq>MpxWp~hn}<~K0mA#0li@s!2UtmGvde-gx7
z_K6dE&Br2p_y{U}We-k5!%y~y2r&M#R9bfi$hM>cEl|d1!fuf47zLJtWe=@}WQgoU
z1qwrDW?E&1$$l?_!f_e10lgk6yFs_RqGaDchq`E4=c6zfBm13)?uwQ9>7W-UV}FTG
zI3csF(V;Y6<{t!^1X;{Em^dkW@k3N5$^wJn;whP-5?qpOGhOaZmOb<UJWP?T8G%Bo
zEWQfdX<0b^@xvKe9Bug0Wct^Dk}g|I0hbKfy%amnlpUetmb0=)2B4573!v?Jwk+Rr
z8Q3{8ejohKmGL)0BTv>rH+J%6s%aQ3kQr$QQz&boKi@qkQ_@w8BH4=+T`!ig4gsb_
z)@hH{pO;m-z;3Bbu?+PKvb;*Dm&snuhDf=rbU(NXnGM!lR+Td5*TAfj-P&z|;zij6
zEhnpG+GLook^RvFjau18a<NYKv=)k&WbZWrv|iS7843+D3mxoSmbJ8_u2FU?6wWls
zo;imWHp?t@1k@tiY=yd3+0+Ec6`Au#XkeQxUI5H?+2a(1?U4O7OgBNU%J{U+?v!n%
zW#~28PD*vYF1v6I+zlCn=HxEfS#r2r7HJRt9vPD&v%Rv5-^1=rnGYrL^vRy0QLA5;
z9s}0~WDUbm7?jPA!2FPG(>qYOB^x{ia$Bai0rar!!z=W~))Cp2_t3OanNuq|VNAA{
z5(CF&-u57OWYT+qHX+OGfculO)-5nGB}?7}a#t2{5p~nD)07T5BXgmLZB{mU3x#vC
z!5`q$ysU=@lm%H{H^`#wv1}CD%5PAN!cKnAdvMKSFTY4xB@Xg8C|u<zk6i&ToaE)S
z`#dU-r|f!Xx%4qSUM_Nb+LyS>KXrkkoBWYEh`7s3yP$APzKF(HdB{J_hk~cP>=#(_
zk~h=p%3HobNo+oHQ!*rd<&Qa`&QJa|g&6%U@~<gjEkM4RLJom)!+U@UlA9^g87!|>
zpe{t7cN9$vmH)FD8e#IUDK-)=KTl!i2zeY`LOL!#ObI@b^4~V0^-*#SZL_20D=F(B
zM*b4LBe8Nv@-R-m@h$jtLVn+?kc^jGI6(kSkSDzk_N4riS{O`}pDaQPPsx9wAtFic
zl8?G%dG;bKrO2~r*h-Z@L#K$R<<4|b;f(z9@6bz=JJUC3(&cyQOfW;fl|Da`DSzyF
zcyU&KnYQ&=@}+V}X3PCdFq<RKw7d`OT=`!<fXS2JNrXneyqS(Y3gj8KFkdLY@*)b)
z$ya}mPArlu=u<Go^3qDwmB=&cNjfi2odam8oYw^Ig8Y+CfR)L&L_)7zew~Jt3i+S3
z&90O?Ujj;%ygL)zMS1SqH2+o0zogx7jr{PlXko29@mmzu$xl!a>5{yP?q}4?pDBZh
z2Kk*Sh+LMlOb}_5r|*Scll&(o(3<7n(mJk1{wO`bt@4@?ICDilC5A$qJc+Iex6At~
z0oEb^<`ooPm5)3@(XLLp<bJ?hlV{|j^156&0GMw1{j{g;k&lkRZm)cL9{M-s@6b7E
zpFG3|lKt{W>4<zl-t7QK2j#(^f(*&+JD`3`{zL;5Zp;5W24{xl>FuZ+kv~VFnNd0a
zHHeJK_aSU!u^N}NKZNKVxnLIEHX(ma17{}XoYz67<oD8ju)FeE3gS-7KRph=XXFDE
z%9@oY&~9>0o=aizdHH?u5Lu8n(1(>4<zGAp50~VR?gaF*ysie4wu){#D6~_QM*`Yj
zal91@76--3&%in=TDZ_~QaEgY#!<!N8v*L9*hl&JE{dOMd*Z4nqOsdeVb6s7?uv#p
z5ILrJpMyFNMLexKJQcz&h<GWSUIg)0%+a3GNAdn6Q1Df>(3f5O6y=`4^jFlCfdp6-
zPt(DBpkl}!GC_*9G|UDoLTCvUqIiLZyHLdgbbb(~;N_v&;fe%Wutq5A2jTW{MeR<2
zMk<c`p)gAE$m{SaT9Hn%uNcJxH2TCUQmA9&6blsIKB2g=9fk3Vu`}qW1cfE47@{W?
zVYGEhRD?{x#3@A*WnLvIhE}16k`-HNj!ID!(1#3C6}1%6I<2_;J-9Q93Cem+QzTFz
zJzWv;Iogz=c*7eCnTmNj9X_kLTmg|R#k1w`H(L=;TY((KvlQOSRTwRc(8yDKybLy9
z;jj@d7AOvnfh$z}l#RM`3Oj$0BE`d5Fj%a3jtQ6&h3X~1Tu{V>pxI@LdJ5f@D}HDK
zsZb0R!23!?f&r3M3RMFzFDfp)1(a&Vc{=f~QCxTduGK2O454Uqog#+v1uiKBPeZ?6
z@%IS2ra{qq6(%k#_Rw?Hs4&uf=q5!WJ)O;pr|Bc%EsAJwaIFd^-Tu3x@OTJ%ZHgT?
zQP-}>qQF*%BIh7HysGGuqk}pXu`i(Rn&J(5Ij$=<TIe6!Zzwp6@TN;K--ps}#k(sp
z*!L*jwMAjC;>O1)ys3C!1N}b5j0L1$v5{7l1By7>77Z%?Z3h`rgwxo0OMySi!i%T)
zZ!Zdm75jdMha-x8&%^ssMGhUlj43wIN_AXe#HeMlx}$h&2%r;+DVky@73rDKpHdtc
z1KM51<|?#eTJbwAh-MVcv_hU$=xMZ^Q*5Pm@4O=O1QZq&m0Q6rD!$qZf0q<%J_NU{
zc$1PkZI!;y0NPG@c><iha!nNK9F%YUgCEr5s7#>w#7P-I$z4a4Pe?(Wm2dooU(H3i
zV>J|AmBa7CuA8!RFFM#=xuG1~G381+fc8-C{R(KF%0Fmn?4^9B3g*3)jSJv>lm?0*
z_$oUncIK!2d=Qxa%J(TXCP2xe*)Y(e+;SZ>NVzo>mV%YStN6J>l<!>uXsGg`&!G{f
z45kQCxbpTrkc?2`cn2?@@@F@YNM#G%^N3Qa=w4T}GPxAyW0cNxMi#4dN{1Km%BDYo
zlAwG;2MZ^at``BFs1)@B?3B`?G6OqFdDICq$;y?qlu1$UQ^Mg?rB4DhPAlhJpm9c7
zMMGhlGK}`{=}P@IG%Z7!K&khc$_ZNHo>jg?Q(cy_F%l@*N@fKVa+FyV7R*&%hy!Mx
zvdI~B`O0O=!7ETsTYNzam1~}aH|LZtwAL$9mQawSSothHEhWmx!yxCCO%K6~Qsw1P
zpj}YjTLmx5lzAJ_m*vV4x*b!Y+~0<}O6BhfuvDddO%1S%$^yC(T&+AzKWL4zs2vKm
zO6OW|b;{WWT7O<ro<9zadZiV8&ZI$kkbd;b$_QGsH7Xe?;F^>h^C8)+>|KOwElMSQ
zzr0m>E(_jYQR44g@Zu?V%3!HodGR;Ybtsd*LfutmBi(B2RDM7=6|O1mc~HNuOuioq
zH<VFUwEyc;-lb4lw=xpLwN;Pu=NQQJDnFn#^-X0OZ5R5K_AfxcU-|S?aCAV~OzC=q
zN_7nMhLj)PhKXCsC;`mhRyNWuXILqx*?$C2HJlk$dS5}^n9|`>SQuCCaRRxc<h@AQ
z4in0iw8orNe%B8&rJQ{P<gW4;dS#}SnKZ@DDEIsVv{|Ke6fkqjZxi6!yfT|o=oges
zIyhfcev<}EOUhP4SytB4af_`ga61a^R1ZH61$$KrrHVMHJXs))D&zAY7AMt{g{X8<
zrO+2tT~+aP@a?8LV??35ibcmQ$5ei_KJie+yadiu_25mk&`VWFPq(+~Efq}osP3T^
zr?2X#IB<Tdy+f$;SM8&8odA^sWqJmx3OwL%kZR^X)CH@AzQ7Ezs9d+9G*or)96-ZV
zw!eUctCptG`Uur0CxLcc)vyjvQlzSI0_LMs`)M~Bt;&B0T#PFBD=5UOW+~+(PL)N+
z*(X$g(M6?rmDOwD5>!9Wf}B+K&_Q9MN<=xor&Nx#NlH>#{&EAGtlDx8PNk^o=_yN9
zdG~-jt;(a7&>7Y7D4?aOZd1G|U3EGX-Ik&Hl2QUPRi$+BeOC1&#Tv6z`p>{+t3Gaq
zdX6f`3I=mk8P9^tQ#lBrp0BFE0I&kpb}w*+s<Rf_-kejdqgk;?^$$(-#j0dBG)h#5
zI4C@?+T9MWRHexVcR}SSg55GzE2SfstNx)aW`)X;Laddl?q#S~ss1|-?2D??D<D#>
zivJ7^tx;|G1a-Bl_g{xXo$8_UsJo;ZTxS7WugauYR)ea&1RZr*rQQS+jjGQn*xsZH
znS_3`>KU38TU1eR!&0m2w_9k%6;&ba!P`{D55i!(>gT6X*rBp5M&VV}b2P<vsu(-L
zT~q1uL9VMBegL_l3f}}nT`KD=T7Pz{oPR(k^r)U_L}{<;g<rwlR5eAze4ncMIXKg=
zdXRP^Ln_z*AaYCfelkREt5zn$?yyQV2W~|5`VvG&Rr`CPH>PTQ6^@RpYG~<oN41i+
zmJ_PvaHvnJ5`&>PrCR$Qy?=LABXogaTJ@+HJv5{8eH2|Yt8#r7&7M=OutwdyYAap7
zT2M^}0eeyP-}5M3QWg22G0UnjN;0-pt0*pDr|uL%&tAQOUS9|GJzl_cRNK;E?WF$M
z4GKrq8c(P@s~@6S#p0rVm_F~}s@7AG(M`SZA}Zb0$-!{{n0khe9X-@57a-!Po~G}&
zdZ|0iFyXEKl{PCr0EL3D`awGA_fwzv8kYRk8%@v)P`hS>1gcj)3iTkh>N${L^$8LB
zB1BzY1ACzs_2ZPY7^Y^@=dHrkwX{}@P}g1scU=8G<@`pfJ=X#zO6@`S0HW0a1<;RC
zk3EdSSoNxWz{IIDX-|4WT|~>Ac(qF!TuV?-41hbS-nRu@qWZ;XaHrG(^l~Jr*U+1q
zthOBGqM<2jPm24bs$Zcs>S^^Uy6|vDz11FdY3lcffSs;xx*rYAP)B)zWU95~_F46t
zl$emEUP+T;w)&oLfSsfEqd#cKRfmaSB2Vo`r;qt+i4F<{>R(6Ed4=ksVt9W}{e*>f
zg+=NJx_n%$*3+7+M7?JX6wj;Q^My~P>ar(*eL?-=y{IcwuL?vbmaA_Lz*2=e_7ps<
zRBxSxdX;)U09=jw{$X&nY9D$l>eOF<1G|^h&98vet0R(t(x6^pgve#}>i>U<qfz}9
zeJG|${ptTBm+BdczqF{|MYf?;t9rT|o?cOJdl?4X)IpEJM7#Q21`0dWw<v^uRjpy6
zu2Y@79ZkEYuBOi}T~|L#2|72_l}o7WQa`o}ZRu9uaRg?MI_@|u^s2Ysrt^oJYNj1P
z`_zAa0T=t#4}Avg0rdfAC=RNt9)!k_`o1~n-%?M|pQYVaKaV_Ft6{ZX2ZJN(o*Zza
z>XJQBA5$mOL@=%nrC`Aw^=ctdCe%OBs5Pm6JqplMYHxbF?y7gbPw(Hfdf;#L$&C7;
z8DP(<|D*R{PW>jy%&S|I;pu|<tp>m>s$(_+dr4hSZ_Ki~hXx8;%_oiE>@+PDB(&EI
z(Q@5E!~G3DIcoMdpk+>)d|LDz)%4VZIBQPf+{4O6<98X*7FSIO%?oat1v)-)*XV7*
z9n&0hguaKSqYr4FnpP_iFHL+m^u0CJp|Iqmd2$TqeKkJM0nJY{g~nL<Yu=<$D?oE7
z1}K3VMLWy~X*SSmGFa1p7$iiKM{i81CX!ZHVHVBvt<VqGd`Ge52u%o`O&-_qDVsA=
zQ$^`7QJOcVz(s4Wb73Mz<3<~)SPfSKOL3Zwhd@qf6cmDs*LcxnoS=D|R@f&sV;i8C
zsQK+OxKo;!GN7KMX_^L?q1pRB6f!lIGH*2WtR}t-mU1=!(5Xb8<`a6>^EE#>K&D9Z
z8U;CuH3rJcD$#U$0j65BCl+>VH9!6Vkvh%GbgFPkQ$tU8y(XM~p9W1`H=r+TBEE)C
zjhgkem2T3UrwvK7CYS<ht(w)Ak0E+RV~j^%wrQqlYuv6;Q!YV==5H2W<Exr8^sSL=
znv<ts>AL34a&+4bjUp9I>(a<5BdA+5PxDZ(MovS^P0gN{q0pzv_XSwLCPoc~0nI}}
zP#@G(Q|Aq7%6*}5Tl4BQ3mP-5siV-;h$bW*m7|)CPoi*4(?=((<C-mbsJo-FtwG_0
z#+RO?NljBB>ZUZY6wte?d5tE5Y0dBs*qzZlFN06Bnme>mp3~I625v#)^dg`aHP`7-
zeo5o>ARJxRbdOWEpRM+Jx(H{dZTS?H4q8ne{C3oG?a(Do+6@$YJF0!f6U13783L%Q
z*5+I2yJ^E{z3r}D83^u}_T4EE4{a%Jz&y2+lqu$=?al@9(XL*BLSL=E8HW6{fBXn&
ze=Wa@&L0A_PxYfQf!by|A_>tJs9-5nTSS|VFl`<^h~e4=2h>Gqchv*!xb`9~38J;z
z3(>R~?feT6iPfqp6)#@<fEHdPXvI&V?xc2#(sPrv^{p_NteyKC=2NsAsvvnr`z<9-
zTGF)Kd!e7MT}R0&XSH$LL9(=4W+9WUomPR%)Be>A_w%(?N8nR|_O2(;inJp7(TlZf
zw!-@oZSVcy&TBtD0fVL58CuX>(5|H?p+eh#3Wb$gStGbA?R)=^y=foG1$4DV`#2?&
z)@Tpt;rAu&HM%8JuN|f1yasJHg_JLA<r<i8)GpFdLzDJPircnoEtAl{qE$Qykv8ov
z+KF7%{=@}Xr}pY?JTup{k7k1F(pJjhOt<zI3KsNe^V^`_tIec8m%6F7d_$iT>eC*i
zNp(c)TZPh5tyd$k$F$wlm~rh;1MJ?>GW4jM&_+?5c~ZOB28Ai@l{9d7wV!_olxc0?
zd5Fwtcf1U{v)Zq|fXJNoM_MJ#YyTAhY(cxK8e~zM#ejt+?WkoZ=(2X&5v8`epZ`P8
z+Ud5egs1j8HGMSBLAT=o&>VFW4iItD+4Z6^M|JPf38k}cUlk->bQ}&Wx$2I7hdMW1
z83m8sb;C*Ej_E$U1@j&{ek7nhbrt`Dc<DO+L!qyZS7L#_pU(YPu>QJ#>Et^=XA=(+
zsM|b_x*(l~j<AAtE-wKzM7Mn{d<xZlPpiTR-D=ua9oK#KE=Z&<HV+;~=_cuVOSI0P
zj;v#Jj8b?Jt9z*!U~#&c$02e;x9tsJ#_LAJwEs)cDJcW_r0x>ku1VBwy#wr1y8d{;
zB<a>s@<fU*n+uIpU1}W2Y2CkdP&lJYxB=`m-6{GyPr9z1qNrze?*s!SOZScmBH217
zq2%bYJ0X&*YwCwWp6=aqkj&SKKBoDvKvzMZBQMn5Ly_rox)6FWigYhN1DImnUM>2o
zL}z>f`sa01f1(pgb@7QHWxCJl2&z)Iiz1#?y1yELa#81S2F<S4mBd4#M)!ORxLVzh
zIZ&w6tr!OMCEc4Jp{`!H`c)81gHA`jUDh4D3H?UhQ?!Y0(%I3c0h@IL$3a?j|9y>a
zYtub*0nW7R_R-R~LwAK@lvj264+FGQS4N*dx}h^Y0Io}Sie}nw-B~(X?9pXLLA_Vk
zPf6f6bpv!L-=`~}Jd}Qmu7&nv13LW0HO6P%D-@y~(sfRupKs~zdk7|O>ni9z_OR~Z
z51=@rJG=>n<GK}QI5Vlc^8dBGj!gl`ySgiNsGHV_d!aC+d-p#$I;->k9G2#Ei9exk
zUU!Q|;su>FABBrLOVZb{w502~iPB}=4FmepUSD|-#6h2Q8U`KpZj@2sq%V658b|f9
zba?BmU+#x_7kxn#Kwb6t7jr!M`c4|W-1U#y0P~pM_e*dddTj;Nz4d}$V8KW4mIggv
z{p@!je)?1k1wj1uuEhWi(C2l+V6c9t79>Q!gXZK={p^o`3DZBe9{S;Wxho1I^k31z
zL6rVa3Oz*Y1OI~;G5RAz5Q)_Xmcd}0KD-Cq3B5xMEX3;%QN~$<KICaAoYa@R1BFEW
z{um3;PU-)OMthU=H`hWjL;ueX$YkoDq;T_D{T>Yzv-E$_ha<A}Lq0&u(R1?97rFY4
zjnK=}uek=1e7$xv+%C|+{tHN<{^S9WbNcPH2q@B5rGhKgzrF%`C3@atfIhE(*Mn|b
zmg?`@h|&xCf9b+QnSNC;OqA<CqE9JS=vRCK{Yt(06IiO!AI*hp7xlF?yjSbr`VpWt
z`ko_@tkrL#9KbsLFF3lkx}<;F1(@~v*OO4!pzpp6a#`O+17o9pWChGO>90nt!28#%
ze}4nm7QG#1FSP1MOu)XPZ+!!8YSS-VfcbX)Q}n`j=$+{P!c~2Q2qK;OXOBYfn!cEJ
zW!Lq7k3!^z{z(cnb?H;wVX0fM9*0PezMH}@z4{h<NN?(A^MKi>52RETOTT_21^Wi{
zcc<`E4C+tRpma$8E!{D{rT5N;{%w8vA!rQi2PnikqJKaSZdCs^1!Kqb5%~}q*T;Sa
zyLa@ZbZKisUr%x7N&OMZy`9p3Wd(ol>K~^##<c$KAt=n~jaNZtE&9w+h|cN77ooVQ
z|C^TkOZq1zXy~&38tqi=4Ph9ltQ-uN?gQs&s9O!<WLR|<B1a8VH266icKHI$#gIye
zD6WPKHX7<?V1EZacY_}rBF79%bREvaaG?!#o`&7D0rN6g40P7*ZMZ~hR3Ag=5oq`t
z4h_KzKf`Joi~J3D_M^Q)1_m9&2OG>MVLrql(m^5AU@C%SnBl=Bm<Tuc(0z*t!;W<*
zJZ@Nf5F(L=uV@PqWf-O4SF~a0%K(cp{NjkZScA9a6}S;+_?k{LP8hy;0+sOwXIk(k
z82-}&^prtQ$*4(&?`T|3HcZl!kYc#|7P>3daCZ(Orwu<pjYga?EQ%nRW(c6vx^%;*
z^miv2hIO=|$TU1m@$|EXzrF>RW%!Y9&SV>m>*)2*F+4g8-*OF=bU7i<prfA6Hw06Z
zzQFJvB_tLaepA7xbB2e0Kx2vwPt$B#Z1|2AVkL$*E`ppl97us{rG~l|=v^?_9)!U%
z!yHZY<%aezVX(q5OF@}RL(RWHsWQZd(faeE;qWKWuQsrvV7|sMLh-;_!{&5wbp|<Q
zk6$v(gh9XFprAbD2E!lWX!d18Cfy2eG(=6pV3Q$50EK2lZ5u>d3}e=?+iEzi1i4~Z
zO`)MS!(&N6X*YBqg1rvIT0E;3tE+|&t$@~P_?}Kmt{K`&fOg&R!6?vf7+!w>q|4Ai
zi|}s4lnXkc$KXhj%U*+$HlsHUd+2`hfFYD#|3Sk7T`C$fd}<5smZ4q=?zZ78T6GK?
z_T7N`h=EH>`B6jDJJ7R?8Gg0_+PI;I7F2f(rf@hsVK}V^_N3uH4=7F<lq+EVuE9ST
z9!?v+r2Abnh9BvuZ`Sa94ZNQ-JV<NXdBcl+;1&$yG*~Yh{I5e~$*`LKdu7?+Pq#&E
zjrRV)v@<rj!>ql<c(n?p4#wE`V9?Pxmjuqqm@*3eqsFdsfI1tWJp#Kf#yymC>}u>A
zgn2h(d_1t-jWM5t95ddeP^X9S_(p(w8kO6i?qz(Lc3$4bHIz^6W0b!NyS~PCYw=U~
z8Go%rp}*1c`#(?&Fg`)&e}TpwJSYYkpWFcx!NwIAVKBsa>JGS2qxoZqgc<8AP#A9f
z;ViHtj4fd>f82Pz79`TR?;DtpGTw6@{ze;z4uHfMpZ*T&u|_Y7N5mUnD}jXs;{kdr
zP8y%Il)#Nd<DQSfo-(G0A(Lb*?S)Ut#^6sNnqvI@8*r({zbOm+v~fi;B+nRM>PKCg
z@$pxnkZ!!(h{6nG66Km?8p|%gi?hb_ThXIg#^bwDmu<AuqxCt)AWCn~HKtQ~VV-f_
z5t{$<jhmi;7X`-0O95JF47dWtbH)z(Z`UHD1I@|B#+-LRN{lTDkUVd!rsMQdV<xSu
zE*Kwp40UD3FDp=3ZhVU(Och4=Q$VRS?*0G<tBhYuP<PSTbOfDOZM=UIL~4u={zU7~
zTH`x3pw}6*70|e3Ory|6y|In%moylEx(x2J@zt+jx6$ZB2eVDa8YK#wjn0pOv>4x^
zkbkT3KDyd_#dw`AuC^I#dr;VJymSwm)L}eFkIq%&To^2L8h_e`zPM)GT}S^|b={ax
zc@j5_8^X{hUB<=(Fwtw=Nei)?Mp+<C^cfSE0Ml<QpwA2p7=;@kIcU6j7NA4MFMfsO
zEu-fM$Zg}^1$4=<@te<Ke#E$jcE+Q|M=4oj%qZFgk#XY;?d|RupQp2V%Y<<iy+@PA
zFKO#DWxP$<ig%3_G(=1rzqSLJF<yEb24{_%zXX{x{<H%y^Tvb6z%3YiDARk<XtN$D
zOU4g_;pnoll2%!^rt2!0urobB4fFP<c0O9>V0z^<=sB96dmhBeVhTA5(W55h0^?OP
zefbe!TugpNaK_bCmWnzz)0WdvbT>t00PUFRDn(8_Od%c6_cX2i846yem&(vyZ__)z
zFz;h}EE7KYnwn^a_cMJ$CsF>UN*=%hOlv=ap+HmLPXG%tSypjT8f=o#pb%o3e-(<M
zrbf!Y4l{jD=^f!F=Pw`{VS1L5TaKGNnLvv)P1C>4#F*abL0zmV^CU=|NlFi5f@z*s
z<|j=*L_jjp<oz`KO*WOhi@FrkIVJQ`O>yo}$Tp2xoM9=)lyd+wxh5Y91m>9{I$<f_
zbV!J17nrutWr0GIix%XZ=_#5ii%e!Zq%Jl+NLiUBrjrlC(s|QgUjwDo)Jdt27ff?B
zFqWB8XaQGlI!ha&3e(Yl;98~W7Uk(xnZAF}0-1}Zho1sWwJBBvnHtk`pF*S7r2ZZT
z>r4V0h+Hyx-V4QgQ<Vye4W{FCuyolJH4E<>O$SEdQ<F*J4X)Y5co--xrUbf+*lH@=
z19HWbRsn@JlYBFp)NVRt3(OAFzCBic?>4b5H|VqGH%$M23irEAldT}#rWc$c(_@;C
zhDNXHrU$s2rZ-~YXrF0@u7&oSDhg3IU|NWQ!9i0x9qA02E=|DETP7v_BDYN&pGD6M
zn|?}%ha;w^;-Efi`os#{m}#6cWyVdnEbGDEF&+LEq7$Ywv{aomS?2<K%Cwn&(Yq$$
zBS4!rNmF2H#`Fds+^p#f%IupnwRpmrc~jmWAWNnoia9Ksn!JH+Ykr%Sk#^=+CefAl
z=H)DaIhZd}KEI=R+dZ)7WVU&geuJatjlTfY*=$9Fu8aAtbXamVAEAlQ&3u0m(A>=t
ztDt|(oR^I{4|6yjZ+V&*Y0u+j_M&xyxB2Zqq3&beLt%Meb3Y}5_?ds*0!e@Ksz68v
zn0M1wI?&ulM^8cKY73nKg_=b)ON5ytmw+8^-bJYe5oVt=fH`h{<2*c!H22v;B+C4s
z93s(X$60{Jn4<|M);vLvUYz;WOgMVN%%{y+ym>eUC<*2(J3&sGeN&;3Xm;ub*eUa;
z6st%wYqnDkM6!AF9>AoSlPDE1)f|2fm8Z?46v;bd7P6p`W=^03xOB7J1zd*tp(;3&
zY2HGgb~<bBYyp>L_WBcg+2$v?AUWpG=t0air+)yFXMX2%kbHB;+i<kNETP?Nq4{qv
zdd+gqe4WDjMP^|eN{h{Iw0kZw8;rm{Z$3lEVx{J2JAhs=d+$Um%FMb8Kr1(2+yuK7
zW)}&(uQVr+PgQ2SLDXF|C(}7;wRtW5J~igw>9?;ne@wGVo%!ci!Cf-vL_@FMVoo!{
ze1n<$BwBdc{KtBD(P(~}MyMw9Jx{}6v$=>)<6F!vCZM&NZ9hQa6>|dpK5gdBG-kJ(
zm+1ZJFiXavch&p`W*4hY^N&5Sbj@5sS?^uuZ~Y<CZMHrSdp+jQCeX58v&A+C`ZvvA
zHNv+(^9+3>soxy%5?}_*jIGcgG_RmL8AImPl%Rgge1R4wx6QjL#dO$gOTX5L*_#ga
zN6l|h65g13)x)S8HwTuZ?vDBFYSc}bKceipNpnXIz^2T<u7JI}=6K7;pws3PG(gUo
zv$jKj-aJSfp#^g;ojom@w;hAXlG%+eCoG$XDV||#^AcTFv$I*B0!e$D8ajJ&u-Qz@
z6i1u8_n^C+Y(#XDbkt_T6|Hx+*+q|si%mG)e{i)Kr09{G&Bk9S2Ig+_<R6eZX7hIe
zTIgZp@;A^tZT8Y$&CAC75x{uc6#NcQADhw{6#CjY?}opAHj{KP>u>X|6kLGKxkA(h
z+Pr!jm_arwijM``47I}15SwjuBpPbt`Z~BUn{9NG8*cMTEaf0Y*sy6)d)%gxNTf{}
zO`}mZlB3|FZI<eR9b<EK0EMwOr+z?R#MwB|QSJ$wr)b3)Zxc-C(Fryo^v0dEd5_X8
z5^dTjq<hMy^Eyb9O)$mUlWmGV1eapt!~t}w&CYK6;@D{$t9QYku_>d=0%<mqT<E9U
z{C7V@Gi*-Nk|NXQWgfgZYg1VUl4a9JM{e0RjCq*Pv00{3EBAjKU3Fa6R~Oegopb3z
zXX|v~jBQVMcdvBaq3?9zbg6q#R1gIOq#LB9B$N<Ax<M3FKvE<GRHT&h{hsm9`J8*t
z_ndR@^NV}WIrj&nVGX!!hW8ds@Hxiw&%)6hMpYBEoM)`@Mqe)DH+MAVGw!VdynwOr
zBXIUYM)O+Wix@vq?L{$T9u*9fFv{uJZz*G;0exi*PpWh)XS_uL*9yjpNRUd#BiBHx
z7`mTfqMC7%b_+EO1Kr}ajCbiNaFNkSYrQ(gBUE;Gi7`s6hRcjvdNtQG%HM}%gPqY$
zPunYuXS+eJGFBTg!fT9t3a2zOl7#>^F%I&8Xl6wH31_Y|+}xqNh4FY1`dS$x4(zru
zR?w2Xo$)k9k2)AT9|fS3k=6qbZ!qptfVhj1L7S_aj1TDeL^tE>e&Bi-_S?Ilw3kuR
zhHIyf@!2KdZ!sQw1BiYGg9`cw7%!~H?=#3)(+hH&VLuAM9mY2<=)22U7X~uKcwB_W
zdyKO?p=FqH_)CxxM%OA>8f7dj0B($7dlF=v;T(&;`;4b4_4|Oa)=qDi3C8nunM^WP
zQG|DjQ9?<<X@+GM8fO?yA3)7RMjsXbIWSA;_ubFzrKi>b=KD9H&5@bW2ks!#neNm>
z%+HR%k~4FVsz{G8AKL{H7v^C~wH;+DLNO)Bn0qKl@5)@apRP+c<~b@<aA*Ed2jFq0
zk;>3Kn65$~Jekk((dfl&F2e+$V3tv^&zrgWT@W8;JVgn7nd|R@_%YW}OxB;djvf>N
z%%fCh5y*Uw9xy@7BKq!2F!P7SP#wbTq_ZHQ%v>>jaV3mt`~?FIXFf^gei6(&RHhio
zOgaxWCz%W<a8b-h+yIPb?x4cn7-lC0MPr!;N=C*pgQ@Qna~Y+j<C*idP?o?n9EMMc
z%(v+FO=7-JOM+x(#uRX;nX@U)lfrx@h~9sx%!($kY0Os_qBEW8y%`RlVKVyxJj=|c
z;|v+h_pW2SnaoSyqA`p4RVxOQ&77uVX6KkmD)i+r=hwpf^UUl}^yM-`C*egN^L^Sa
zTwuOR-<-^6zRZJ20n_**0ENt+L5SFkn7_XUL^1OorQu7M_eX#zWp1Hw?Uga3F91=_
z96kY&3g+sCP*ce~c^V>B%y%W=YMHwKYNVMN=OI$ZJWTtGOU!4Uhsb4S8?8F(neV*{
z$p+@quc7P;^SSRah^x$`S25~qb|#CK28~QM<p`UY3vYvKW@bGC#C2xPbKqK-^RuC?
zmH8~?$lI8A{|7bg%;Z}1buh2TV%9pDOXgxsH<%x_fa_u=PeS)i=9imcshjx>#RGeo
zW1nD1z056?)9+(GNx{imO#2T$aJZl8;|;_Bb3-n;LFPx4AHK~zPT|Nq%zs5_yvzLf
zJ>Z9!2d<*;9y61|d&5iyrH4nD22Us*WolF4+8FauN)L}Sx5yxJpP8Em+yiFHC*UTS
zAyY6k$y~G&=BJo{+Ft}>n)x#=4Q80U=fFK=Zl{Nk1MAcf)a+;7b^>>Rl|+|^BTF(2
z;6YYAomfA_DyIj<Vb;tC@WP2Ti(ZP(tk3D7@ex)Y)e^X{!l?e`C`-8o@MElFp9A2^
z`j!^MZmbR76v}pIx$J?`<E&?>w$y{=_7V(wvhKVBpckus7DNJB2Prxc#PTx0QZVbm
zZCDCnDMv9Ep)A4QXbfYyNFWl<`XvzKjbNoB!#OvSWe!H)Nmk4t`l493D6SpL>Uj+C
zIM!c$ih-SC`9#2OJnPyJL=#wV{tJ@G(rgDwVtxHTc$&=O(oxydEZ+riCWR%XO+zY6
z{|=O<vD&FIofSYUgEK6AS`{}A>wmN*&S1Ts0539G6BNwJV)Y&Ym(8kL3fwu?=1ThF
zN)Ahq2{w<l_YsWu0_$-ZNIvUp14seu<9LulRuzSfi&!7df=|V)%vYeMgym0xrczcB
z<!Q=T#}}fpoW<OT$*W*3c><)8Wu_fa70dD!`l?w4RFY7`+Cw!ewXFTwAoh!_FDar{
z$10XW<`T>FCw`#IELR1{71kA6FkfYT{TW2Av4j*=X=FuEIHZa7S10T?vvyLr>N;!O
z0@A`NUyccGWo>W=X=5D`WAfTrD`dcRuspg!I$77ghq4<i$B&_<%g&mn8}BA-fdZtP
z^;#bW+QV8O0=vDex8`H?eXRMEn7zf)P{~O@E0J<#1FRGZ2n@0u-UQ$_tD4r^cUZ4`
z!^B<Ia|@wth^3&i$a}0MRL?QYT1VeH8DV)-4a6wx5bblvSoU8Q!JBc`nOAWoO|bfF
z0i0wViUXNqt)}9zX;xt#xEa<6AI>~vIZ;YxKl}F<a0l3aL>$?>sWkN<dm;Vkhu9~(
zVD~UPn7$(K#GcY(E}Yr#QNZ*F`$ei8abfSHE&Ne-hy8JQbBsNk$}(Nq+kSwjZtTsJ
zP<Cg}Y5?LmyI?;|c(9LC_{fv(K?`Lsb`ynDPO$gVE5n<uD@CIZdy>8e=*!-73?}^8
zFV$g4{_M{wsu;kw$<P?cp6G_oAhvNaNHE*nMn^zH*ez=T3}wGl3NDQO8Wre<v;U!m
zSOoib+OkEmYv`^x$(GYHHj1s)f<&|Tyac5&?0^3&IblcB8X}%Ohi>r%_EriDCbFNJ
zhNDUBwN$~M%ntAZ?ljwDISi$+^WLT$P%3+dBDHDk+75`Ov!9}U+!^+F^ej8e{-hVq
zWUxh)%FSdir;8?w?S2T7`Rw$UptOKpOi!jlwgaueir5#H!hA7%T^RaG*h>NcFJu4x
z9p<o{y@x80E7$_sP*k$rQ|OD+RqQk0LZ*f-rL|%$`=kpxFR~LUkygk4nFno`*irSc
zThC7RLtg{CV+ACyuy;g(yUPCezbFH{oUX@4c2zR~O>Cb^h%~c*Jpz&I?2LYxZ(%>J
z#voeR|1-k1Hg-)C254_*|BsS`9c=R(km+P+G-GORu%Do)WEXqrDwN)27w^GbcC!VP
z@#|r8Xsy@Fe)T<&KK2|c!MMeqrbk0RJ7*bi1MEZe6c}VPsP^JE`|wUQ-eEs_7TjI-
z_W9t3*u4~byJu%dya)5cZ001K8eyl9-=pjdS}%;Td)|S;arSD;eon9_wn6D6`wiNR
zPO-UEQ9sSzP6fd;?BQo2`H=n1UTE3R`EofL4{)p$>2c%~KLk0*Su8}~A<or}Q0BzB
z`vy2?j=i1*^G7(dDIVg&`S2mQqny!l$hdN(pM!JbENO!_cg_lm-5uvlK8ijMPTc>X
z)RVJk6gV$V%N_Kc;7q>=;?2=efZ2!R&w>eGj=C5kejF`rd;K}@wW2YA(@l%;K+gG3
zcECgsXVZNQJD5{RYo`#-7j#pGa$cZIK8&-`0bDpI{yE?yIG3-3i{#v$3+^Pxg-YS0
zINEp^jOP5(3=+dh{uCmyoCdGZ?q&9yarl)JIc^qoC2`jO1YeRlT3T0}=5$+NE{#(k
zg7Kwu9?ybjXE^Z`?>x)Negh6>a2hrOp2=BN4asayCM`YAaX#RH<Zym{3X<nJlk{}V
z<%Cd-?gHn#R^akE-r>+$z;UzhMrR>sdpU+u#L?73ri61W2~$|gxsU^A$~bd8AX3h0
zqDN2#hkF;2m7Mt$y{Y2-;Rs9B9RDJS)NpDkiCD`KJPMJEoJHGVqK@;`f14Z5xmYw_
z=KQ`6s_Qv67r55I@xO0J>lKbA4@0}ksapxeHBLK))fzbkpF*aIQ%jqSW=`xq^j+ud
zJc*fU;e0+1fL6}o`|zTTGeysUcFtpzr|95pr=4&o$14ur-{9P=#E`l;-K}u+Ca2*r
zly!5~Cc|tGC)hyGmtKye0-}AK9ZIwgaD2L8X^@ki1Kqbd^A-VrhqK~wD80-1h6#}&
z4r4XE80PGJ4Y(1`Q92+o%6VrExG_#T8{Us|B64Br0jGE+`X)FZF9w<9TqG@1oNuYR
zaGJ9Xw~c-7L(ZqPMRVY44#4hy?hkx$2e_(i;2pUeeuEbWxm#!ja)|pWWf%@~cdmdo
zC+;%J2{?1Z?_k(RxC0Ntxp4m)2X~Yk?~MsM#(kD9JXh|=D`C)$yMQtT?%bzo-*ue(
zHmw=#9^BM7VZxKkUxR^qahFm3$O&%OGT^<rH>hsYhwGRGpM1GbE`@GC?)0|+_;Xjw
z;BNqT-yHM>ayR@}oX`D>4uk}AHMH#u;rcP5C6pWg8|;R0x4!|&a4vTeh9bD}6cmiI
zb4%!yS2TAEZHHpG@f5R;<$kILK8{;VpC~%T^`QVjJh$fys7d60`86byxKnfjESdXA
zA-p)vjiI+#3iknJOH#S#C|sJxEy@Eq!`&(a;4HT;7v?j#i_haX$mDLIeMA=5?ng<c
zY;MClAm_Lux_fiDZig|K=edki;BvWZd%@*#ceDVJ&n@hOPX*lCP;iCZPre2z;!c#n
zZZUUPH%ydpr)h#qxnT=nzMQ*957iai;Yf&7azmAXS8?OlKxZ{K*?t-(YPj}E0BgB+
za<Pv4BK=&KxJoK!xy=2r3y6Ad=RNc_a6cbM-xcohGT^Rq_c?(ya{mnnY2udAPP&<U
zX##U`otxDKyDi*bs?gZZWyxW%gS#~f$~w89EX1tc;O_RK2x%90k_tF(a<|g1wVQj8
z_Fui+@Dw2WxZ7!id5h~odz^mm9oi!eaM#{~GlSecR1$NWdx>89ce%_(XdL41yaTuI
zap$cBV3_Md1zRIr;XZJq+)vz~dW^f(6I#Z(&z8}Dbh*#<_!jH~Zoe0tn&8f&qaah<
zYi~o%G&epI4$pAI#xTN%+@Jr12?yTLN;K~0y-E?k1H8FvNFL-l{DQF@;#ukYDTjF<
zQ5eFBxAGQ<GjHSnp!x`}v<x^G-Z%SzJH{Iq(Eiqy=TCL~ZoHg_Xm#gZ$_ICxw^9R#
zJ$Re<0qDuQPS^Sg-rIkn&ztwO2Tb_z(r8oU%X{@T5I<fh3xf#ceMNDtAl{NnNCxwc
zl!FW5`8@{LLV2dk@IH+9#8OOGIBzrUlI@YaQfJ7V<c0nVL=^8pDq5p?t6oE64DU(?
z8e@4YXiXZ&+bf0LcwUGPL=t#+8_}4^8!bU&60d?b^2xjfU9fbTw<;TbDZD>u+n37A
zqm^wM@4F=sN#{x5$H>m`#--4bVdw3d4fiv7>6B*4;w_wyQDpOep>4%E-Yz|Ut{h%h
z2!Q8#=jbd&9xsMATo-u1>p=2(HwvMqfM=(7R3R^NGq@t2olgB0^U^9oN-=CSmhtK-
zK2*;86T6zZ6}&}z(O1c{=hKRyiZ`x+Of~P-;~=%X-Tvsj$a|iayLG%?`jq`8p1uT)
zmw7Yv<6Yr3evA=b<t-M$wQIbc4<XXXd!rBVCZ0S3jm^9U+7e#pWrl#X@-|-tY2!K4
z@}ixmrBk~dyiNAqFyG0`{tdcs@Dk`s>f()2=|ng02;KfYyv`DEy}YwCbUW~3RsnE}
z$EWj{{XF$=AOpO8)4&b#j4Lo*w|V>;aCdk*iZR^fjZs499`7-Fhz#>w>5(+Tiwb}j
zqdd)flw%&_<xv7_oVSPyu<rAAybbp!ct_S^pp(4Pr4XIsweEoAG%xo{NY3z94WaKL
zZ$^k;#DQN%tH=ZVF}g||`BsVz9^{*7RdtBpPrvJ7{t{a2IPvS|Ld2PGHG;VCRh#Jj
zca$&S!o)HD<4%xq<v*SV-ERCc+AMhRljx9|Cx3z-NnZSg|3KRb{)VT~=grT20{;5&
z7m<iBU)=x?{rOJ0-~#w+dRPbY>#tzgLHuf3iUji)P)Z_%??dshP`>*ht*^uR&M%`i
zf-k36M<m~S9eg{<k8yw(QT%AC^N!{(Ovhki_;2n+Uo3w`5l9@rn4Vgv_&;m|Jf6Sh
zEr=xYcQK$PiJwPbMM&mvFNMFS`8BjjPvNir1%0XfcG~Nw@h7R^*?xw<l(rRT`4<}C
za0Y+(RcOoPKlwfU&f?Fev%ER{$>ji^=O6nA26Op&$pGZ>Ij2D`@Lg%|o6rBAJS^bX
z_@l9iKc9+}iunt?!Ikitg)m>r|1B4G%lLuxUG8$eE3I-W?EGtwqqB<tCcV|F`PXQZ
zU&Ehv1Xs)dK?&U#`L!=YcOBoIR{59sA@l;f%-=~V`FcK^0@)4x7}|VZ;qROck!$=4
zS_w7sXG>tdiNACUhSbdeb2pS-=dX0duiV1Vi-0q&eEZ8kqqCh~O(m8c{QZxiwUhr~
z4&1-Ne`*DEckxH7A=1MS`xcG8d=o0;=JxU5Z-eA5emgB``}sDCSPbx|wnAi(&!PbM
z9sbKyD{+_qI~Qb#zjXu_?(xt54rRl9>tbjb;jgq)vS^flB?Ig@e<!_i?(?I&pzQ%)
zngMQtFG$4%P4b;7Of|)Si*`KId?m#;X7~}5zI(_&(g#Tg!IyMd?ibAY9HVy>d`%S}
z2L;d10XZbNMoGNGf(CkFIti+Mq0?FL@C?P5jtDX+gmqLfv=uVP1WTz1+*MFT3o$o=
zjP``?f)|cK#8YrN1Du!OES2-05V$@I;w{)n+X^4Sna?m5U%|nrFcv?-8}l#;0Rkyi
zsRs%kjsq7Y*s&gs!Gh;^Lo!5gs-EJzp@K!U*a{Qm#KE@+K?1!GA_b$g?ma0;r#Ees
zfKAbxXu$wgL&gaHDFr@Ou$b23ae`PnqkT&7;VDSQ3#2chFG0}sE_5ad{-XNuWWlzT
z;7$wXegVl8ft1!Kse*WvklW{`2?i;spDu7d25n~rk{y_m48cPRv}6i$egz^+u=WJ5
zoos<d3E+9bMT&yt3PLCxo+oI00pq<O$fM|3zToF(kOINRBhXnWD3D`FMS>q`e_JdF
zs6b<>;M9u{DHD9P9X{F11vjV&wL*}kg-oTO(g5Anf_YK^YXo~gMPIGJF%7^vK_k8P
zFA07&U@k5T258?_FX%iAK!e~dCOo_%cxwW>uL?qG@7yQ|_5f)Tu<t^3v*1fQm3CdQ
zX9ikY1O?*&wAuy7K1XMpK;eQ>bO@^EL3gJ>eiAY_1lK9%)g|z!xbjUw$uNBC7WC6y
z)hBp~{(I~#!AIX?6#at48;~3je9wdApg=)4&TYYk?;v?cV5W-JyMl$ZR2&ineF!ov
z_=n=1BLe%gbaRagu2axzOz;S$;l>5pTBvy-kkOg12|?MnXq*&yPor^KFrEhdjNn7M
z5FZK>cB9WhxL_ZCnEk>Rs-We7aGDNeISN0a%)}w#WCJ7*3*)`PISC6^0^lrshbr2R
z2y5*X(B>k1BNmp93KQrN?kfD=1W`Ak&nfh|3q$Dbe_Z$-J+wW9tDZ!kr*I2>K*3x1
zuM;>Qq3Smb)K@t7Z*YD>Pg*1T3o9wMA0T`o3tXVE>|Jm{!m)BV6D(Xwxxi52wq#m=
zh6$_KV8ewgXk`*1tfB{Vq;O+Be#$7}tyZ`eE#%TElNjNXlpl=~eoPPKQ^F9c%8wT^
z+~9VC@U9#rQRr!aWRmbt4dBVb92s<`2$y<6ORDg75lEVFDU~{=3n!kW{N@?qtQX+o
zS>g4AXw48VPQ!(fC4A#0;IoClWCDLqDD8vY9HBeC_RkC76{0a$=t%j#eBm~VzZVEw
z?g3sXe23~ii-dBzn~H_oszFMGTb_WwrNX<E@GcXspnqRnF4XC0|5qVwc7&Qr;s2h-
zV5)>2w?L|ehaZJ#jnFj{b5SdN_5+ZMLO;qI)CvFB2`?@Q!`=b8EZp=b0QJJxE`l@&
zCvO6GO<0d*-P}guH0|q~gwIfoaI=s}b+y-pPoISO7U4bGtk_$Hs6D_9AZ(%Zd%JMu
zGH@Nj5Q=Mc3R`KZdPCU01$MiHAEZL}O<^xZZM%hssVcZfSVx5cy~1yP!Ibm~$Mb-@
zC3MP#GyTGn&jBA0deQB0NBA@oUfdNf2?IAI{CNTT?%9P;-GSX<q1gjuL>Q%qiBaKa
zo1t_}`1fB>IxZ}j1>k+*Wy&}|5bpEC#WErEz6dWS5psqXQ$h<ZL#Ku3tN_di%MXBi
zD4au+;2_$ph0gt=WGWjwAX1<PXs)9u@jLV#7THC#+Hn&7s6nf<sFP|2kBFo}(Cs4f
zu!0;FNoW#|i8hl#S5aphh@0rZ2AFUc&1u8T92aq)f)-Cv(W7Ye65XWO@d=UBY!GkJ
z&{weJBdVkW7QUiClR*4L|4>ZPUv%ES4uc60t@i^yP;@REok1cmCP;`#;tz*IMPk}0
zhlxzIf(sXA&^|0e^d=R$M2a4nM&n7*mRQV8lxX`NI1??ZrzBI1X#WB{pkhVA2O)Aw
z<VJ;N@gg~`rxHZJw_!+$qIZ9?LwAzsmo*^Cq6HM(J1u&VR{bfW72X(3s_26mG^UA0
z=!j6dsE{tN4AFD6xXcvgtb<6F$mLr&lP#K90LgQrAL)X~5n)G*TSZhsWn;Ob7bzW;
zC)&FK&Rh^h(t9Ld<ol4`e}$rFkHhaG(TR7^S}Yp94`7MN^*9DvDk`M^$yX-YB?GWr
zwBa8Nv_j;g0iaSehrR|@B}#8XU$yALe|ra!W*%n!qUZ$=G}eg*-T-$=^m+qumqqmw
zxK=N^@*6BPh}d~lV|+!_ABe$R6|pI^e@*n)H;`!*JwY3qX3^m~kn5s8+S9g(;^+!&
z6+L?iT$?D)38Y>0);qv;h~6|ovQs4Tg54XUR;tbF5;f2(@}?+;zE9dKDx%XKeWFdv
z0JtS8p){7gUnHbb^Z}7#BgmlW--mGcw&>6w0NxSxQ+nvGD2D=6Ln3d=6x<WNOY7GW
z(Rw;GIV#G!2!F>!ODr%kE)v#2_kB?oWx5}TN;Du7qB>7FIw`7N1Z7hq$4ZDyi*8f3
z&Wv63&sUIf5HE6o?)~Cfze4nYxM?+%I*Oer{BuyefntV-#3_Lwhs8XqO>q)W((wal
zv6|-Ti1<w=bi0VZOozxZah?o~uHu4DSaK7`)4>dPaqJZUj*HjQ_2?n)p&Q*(Y(GH>
zelPKN|7|S9y`KT$Ek1Yz+I+<4DWT&p?)Cu}Al~{c#v3T!@IK53iH9ju5G<ZUDW?$e
z(@WuYsQ4ni#KXj|UW18n@f8LD5#l_`JVlCkKL$fl;tbj(MT>u@!mAkZdiym1W5r*7
z4ij<W9c=)f5|>i&EMA=bG+ay&ix$JDL~--)049k)Tm)dUc-Co%q=-}M!KI4lQn68*
zxPo48>EfTl!JQF%Qo+bs@eF-dD?|M7c{rLWcK-r8v&83$p)*_D_c7&H&WWRFH+o*Y
zhw=`&;>1!|$`j9-2Du=9kxn1wi$C`TDG+b^3BO38_?>o`C=&1U1t}K0?*pzx>_`uT
zQnB_u=&lgYqt$n%c=-eXRpO+_AXzP*q}#tnTuASzTCu^M&UjxGzkdWWbz)5x)Larr
zQf>2Pagz~<dhsAtEMF1tpo+(<;&3bau8F7epu17Lm0l}N;@l31G>g{<fm|1F`vf!E
zA}*utSgUveDQgqw(eu1r+;s*bo#L`qkQ?Fvd>+R>w@X}2#}03buVw+*EuNueLy!3O
z9W?fem&L(SpZFU6i;`R7HB^z>FTOGxA_L;b93XOAJeO{+J7SXsmhOrtqA`deaTFEZ
z-4lylK!(Npz5rlE{3RVM9u?=#1{o8-`X%7@ak1VTi2LF+G0abjXVczgO1zqaz|-Pi
zD9Sz~esLHg55@ZvKpZ3|eu2ULlGpE|?||ghSP)0am^0u9C5d#z?vUiQ?U+#~Ni-!2
zoF(T<fIA|2jP|)MlK5kgJSy3wffvW@lFf5~aFx9N7nHh5JW&`p*IjbI5S_;*O*PQ%
zA&H>}vX|t8%Mdvsd3px`-jb?n==PDsHKNg1vW))WfuAJjIdJ}x{bVpevN!>_K*@72
z;71RV4AZkdSkfMjxd@e<PJ$O<68pzgz!5Gvp#vKsNl6D6DXF94yOWYPsT40t5=8l=
zXvx~U5Q&kD)?;X~lIMqEFiv8kH&%iqo#Nt&l1H9~WRk>_vI5DH#QX5#v?Q69nkkY#
zDxgo51T+DcCTXHae!3*iehTav$q22`&q~DfZq1bZ`6KXIl0hnO&z5{k3-ogm->tys
zNY2sQ^t|MY0ocuzEc_UKd6G^FGG36(c@wVXOPp13v_P_k_B=(B3zRV^mK0IReTiiA
zI*?LHF69u*Bv&-F{w$X~e;xP=$qTfxuatQF0a7LTU=KvAC0CbXOf{02c9_2?dH!+u
zTPK-qMBgRJEJ{aRmb^_zbm}EL3!t<?^7=a<S0n?ULCaOiwlJu^CV4RxT%+XITX3dH
z@|q5S771%9#Xnmm@6mF!P4Wm8&vi<6>_O)ZiDd&u-z8zwTn<Qfgu&pTgh#up+maYM
z5p_q>F#&Q{60{9uNK!>lh<lPBGhkv^5=13<Ba%0FV1T2N7pdB3O!8eYxN%9=3W(g7
z{ELy<=RS~()5d;6A~^#5q~vva?@me5=#e%pnM=9I8HxP>$V17e>(J;RUG@(E`=x?i
zkUSuLs|7=IlrBGj#)Hzmn=#%)(w&rkJ1qTNhOszF7t$F-XQ?BVlpc{*(KYTOwd#Pg
zAC>N0i(wy=&Z63NSLvc~sBx19Qh9^B^ecM69hZiL0^uS3As>yN(v9cAc}Y`gTXjNO
zMYHBDeV2hgAL-6-F!{bxryOYUlX_BG*Iznf0|}4@H-iL9_soaRAnB8o=nJ+>J?J48
zBF&=$#!%_iI(Ql;?Ry69hf5Xoqen>hQps?n)WC+)lhU_@07OZDDgr)Q`js6@W26@z
z!(d{iLCY~EankQMf}E1Nyo({lOJ`HCFF~3c3z0<W^b}MlNv#fWJ6UQEq!;IDsViLq
zDbfNN45mttn;@Dd{fwS^>C#tY;L{oDqFWF-D|Ku~UxxIN3uw%gmQsB|mQ-B<*RrJ%
zM*%n|%{YR_T&YS5NAsi+k-%M$Zhi=7@__@qKzgSNB8Adp_V3YIByFW!ez9~pmA98j
zli!9<rP7{haAneGW?-pYnnVS171AfD_MlR_nHJ$yQYAv@bE~CA^nIursf@k}Q7iq1
z7PA+np0rb}ldg&a{E~F54ULzjL$Od@FZH7YO@s8Ezi9TZNK4kj@2k>rst>v*-CTyo
zM(M9xfM}A&^gvCs^l!>4Uzbi%3adr>-4{^WDs82*>o)0oTj52!R6+kmuS2?^2PQhD
zX}-{TLpmn_TDqh)G+j5P-gJ3%OMmzQeLYgIwEyyd(z5MP(<fz0(0WVCr5AR;^y^U=
z9FX=?h0CDy;}4<cw)EZsICDq3oYGTwrB^B;G9;~`h4wuuYc6yTON&1OU_`q3Iz&dL
z12<uJOd93`567hoZvt>%I>dmz2htN5pndLy^nF@WPfCAUjiF6R)AAuREqxdVFJ`2B
zsfg{Nv~V$$I>>&{fYSXkmr#ftkXctj#8Fmy8r(tIGgOd%NcKC04i3v+{2Pr<vSZO0
zlC!L8HMk?PAL_xm$h2R8J1VRA5X62=wqXfcU1hO;@btKB`vaKpkZoIoMo-xj=@_q<
z>`y8xIU#GIWTv<5@;3DO$UKwbwy&&G1kO)3auINU*+2A|wg4ITIsk#PLR#bn$@1yr
zLcy}xpFlE1_ICkvhRU9$5}q)->>#b@!exK(F!~5tLq9qrWv&#KKPlr;tRqUcoClF;
zS@BMg7}<)|xb$LW4lChkoa`)xGf&CRP}D14w(%SECCC&nVG<H$$)ONQl3l0*mn?hf
zOTbUdn(4r6imdMms7{sHTWGtGCOfzrY`QF*;sa-7Khf6btW4Gp-5Ijm<Wr{X6N=(y
z$?EB3MYb$|Bl^zC)>7$2j_ezX)t{HCK7vTD?8|xZB2UJrr(S{Vty};KWfd;~P$c_C
zkC`c!4NzrhiLBF3Co4*2ZD%1`CObzZD&_c{pshl-klt#QvZ`VLt7J<;F_+acaV#Wj
zWak<&rL{8V&uF|T%Uu9%bu!;|fY-~e(F>?Swu@3oS7e6I0KY2xm4d+6WKZWovQajG
z(8Js&*$*blKQzncQZeUs*)hs_waC^`roUC@L5svT*)06cZI`Y510o%=6@lP7Wryd3
z+>l8HP}(K4QV{B<Y!_YR-Li}qVX#NGl!|nFWnOQ=nLe53Hr&1?n?vdUepwGCF$ZLC
zen9`xb5Iui0zADfTlW#{-jQvj+|ymzSM-(0Az4Hj`tHd%^cxJzzNKK&h-{`1BBQc-
zwB8<*#ZukMxU7c_pYF@{7{NV|C2fVsgv@muzxJf;4uu@2WS>Pt=QQ9L=Zx&aFaPD=
zWwinD%|ZT}19b0~|2+oL1M<J67=@$ULh<;6@>}#aJS5*tSIJ@dyKMA1$*psMbCxgP
z1%pTA2Py61B7fu$cyUyoPLIN4@?Sb&&{dw|gORz(y=i&mE?-KOPsioiAAs0B<e%lD
z(^H<A1yL_~&<D_VLLR&VcD?1FZ$h7s+%XW1zH%uY_VSbSNR7XI;u<Uk$QK@kWT4#p
zHJA^Qe|s1tSpLNbL_*{<BhVQt-$%u3Ve+|GK*Hrtw3LXDSIgmHq+Nb@FYwXwJM=V&
zk>8_)Nvu4QZh$!X4|JB|l>84h8sp{NQ*b6hUSAIriSk)$a7pqbRB@avA8SM7X}Q}U
z;8Ns!C`_FyKlCBAq{$c4h9q6SG6Y)A$Qy2fJ1bwG1};Nx*PVdfO!-D%v}Vagv;oVO
zoBjnkC)fT97jxv@6R>n%j{h)$n@j%IB1}S_+~+HB7v%qVgUgp+3&ubT<cY~3h4M9r
zpu0#uhfcv3%Xd)xvP8b=Urb4<e9sT)E0gb;1zfp&iJeNTE971RXseVP2EkRyMLpoE
z<%9PjQzPd#VxDW|*(K0+QSL`;;yU@A5QtooyJf=d%W_{=cvvqN$zZ8Lo=a=#YjQTF
zEgR+Sr$L(JZQ;N*%WG(VeO=x(1w$?J;X*sSX_ad$Ak!v)nnEq@^1W1;-XZ^>A0|5G
zkDr5y8}jn+0PK=4rR(aZTpA6Zy5%Q0XzY>qYe0JCE1tkq_R05r37xm(zdZ@AU;fw?
zC>xMVC?Gy4AENUpx8;A)%jJ%I;Q*a6y({mfCDf2Smk;;v$s1`cF)ZiM%3?$wP9c*~
z`4Y<Ej>)adVSZe`hsu=h%M02ur4Qu6F#t@+M>*)5lz+SfmZs#6!O%G^XEp*iBj0fV
z${xyl6M=J3#0t^3U*V8W@4o|z6SM_!RB*ar>7e4m8IVJY_?Lk=tXN8!N+*SU4G_+X
ze^kI9QDnKmpo`-8tC*mpil68ub4+nx0Q0VjDJouYQ>^?NICn+&2pW$o0tVrQhhpnT
zkn~i{z7FE0_<}A7`w7L%v_bGzta%s2M^QirlYJHOl-Kf8gdKnyf5jDA$^<ArqsLvK
zB7@>LL5k)Ps0miMQPEw9qJA#8P{m&>feTZ-N9(C@#n)rtA{70UfsRykg@QY&2>BO)
zD8)FX1ETGUeYA{?QS?xC*C|CMh0@{`d9*J{P!!&W`-zHGm(ZA`SYw0vWJTm=kkg7q
zYoIhmF+ewbs)GMHNSdOf4!Cs1?^IEAM&bTE$XP{U5d6(h9Qqh`GZiUx05nS>qcnQ9
z!tUz@HRlwYe*(!-EQ<pEyyCkun8;PkqOf9~VlTyQFDTxcjlO(^nqt@miUC@k6)J4&
zVWLPewi8N=6>6H262-qouvDsG(8H@tabF9Oa>e5n08}V$Zi6$GieXy2R4HcJC76Y3
z#g;~xs8Q5D3ej3c+(|fdQ8BH8wmL;Vo#DTvI79dSWyMFSuvD*DZh&NiBFzyZR}|Oj
zWqegJy&6idDK_7OWTWB)Eds79{?MVZMbSp}Agzl1RQS@SU`E5WcE#yUcC>aVSSGNY
zid~a%=7!>WFI?<WaA~b~Q}GrBfx8tilfylVtxF-<t6&A<_w7?WeI48_g_OPp+OIfq
z8)QJyNX0FK3g>PpyRC?;fQ37XKm`DI6&v4yze9?U<skPIeV@|)Z&>l07*jK%`1&u5
zVpK6fYmhO8%TJIQSHz!%-TR87G&DX?+)D(RP#oKZ#!1DZX8@Q|%xlAxOe-Af0GLtq
z(jXoxtn{T?2PI<?WWTbTq6-I<nY5X7RKD~&+&-wx!_gl5+(Sw+1!oQ`)wHp2Qf}G@
zrOwK{`_Ohoi7#;BR#UF{14@r7`SioMDLW|N>8@Nr0rlg`$4>+9p*%y&Zck;~LOA24
zoTkvj31!+8ro>wr^g3`p%1WvU@Kw$PLA9UqE?uN{e<h1b^8%EvG|)ihe;L^zWjO7n
zgO%M5K!hn*Qm`Uixse4E5y~ZeNJc6zQWe}u<#CEtL@BEZpfp-}J`Uc;C^OH1#41A*
zpgK;ukKW#=l$U$qQ@m17ncM{B%u$d;yYfZ|I+K*%OECIm<$DLA?X*&7g6<Th&nkG4
zsw|+ojx=T9(-28l{*SJ?Gs=qnaOSMCB@aW(Q2MS$W2SOn4U}amd5^(-wz3-s*yf&7
zURVZYIm*u|)Nx+9>3vwpRc4F<kf*c<rh{Hk?%WHReC2Ywt_qaPBLFN^wowAFNI6JP
z@?xda^RQH+{FowBrOKrF;L4QQi$Thj=T1Org|bBnK&5h!wo_Hgl;_}YwQ_U_eKpEo
zUxL52%HF3jq&g+90v0YQpR~^dy{rt@qO)G<MD<M#%7?GO;1y-SClI}=^rXzpHRWeC
z&_?AoiqteIjWof{%43u=yRLk#0+KDt4#Kr62cLo$ZOVw}@T0XWGd~CXhB8PBc$ad^
zc}U(=_R|M9yOp2CP)w>v*_95Zy~<bUq1&f?o}MDNls)wL=vS_%TA%@?Hw(iaRPNpk
zk=sgF3Aj5-p$A0nDqR@RHl%!P7I62JDyjw@RtCHdZbaGl0aTAFr``l^OgT-#x^d+>
zig?^tKJygq{~jon40KK?%P6`rsr>T?Xq!@g7!ES6Y^s5!8KrXy+<&Ot77e8iD&uO5
ze!uDq+5sI<wbR1HQRTe|A_rAVs4D-Es(uZ09#;Ky1AR`as}#&}R^`yCrz0vpWlddF
z0x8v>9aRNvfr(?PlT^&=s_MG|88_9p=Ye-uJxa;y<Er-6KzOJ;DZu5a`ZgIO^iu7N
z0Xd<1lUB3dszBNi_^5mvF<xKQ@l1@+PxUYW=KWQ1Pk{?i?V=}3psH965~Q+ULZ3ZY
zl}87<LR6`f_+>&>&rsGiOcld`!EjX##q}aot#h%fi&U|ngEJ>px?vcMQmr@%K(xw}
zg4QuAZ~CNRtV(|kUc{*+^iDmcD*qIKc-6<x!eD~x^+@PURJA;Xc}h|><$_DLt2FVT
zr&T}JLMBDEhO(cjsxk^<rK#>YqA^`nOv%VIs<7qY&Z@qkdesco;(U-y)!;4kWvS*;
zf+ky4bRW9Usd~+DJ4bbTH_V?`g?<9bT$L9+Li1F^?*VW@bt(vw`6|1_8SWRT9Oz;#
zR&DcxGbO6FEodxN@hEUpri!otQLdUBhQ11w=?3~LRl7pbSEZWQg1%~1V>J3|RAF>L
zqE_{TCw``jDjjX(>QtM<VCj;|pDGbAtNK!bt5-cT3DTgdwHE+!MOFI<9KNbrMaO`y
zsj8mGBs8ivZNWS@saocvuUYk@9{B63VLH>$q7qPXbgOCut)AOd1C7A7t7d88OowXE
z^U&F;+DF@|8!B%OB)e4Z6Y%h+YF9bn-Kr)k;q6g%swn=_s~VYu&OX(=V31p?e<(`P
zui8N|v;kGZe>a|L(J`pGttyxcz#Y}9b~tlaRnLI7A=MyVN%vH4^pY7?B~#7gi0aPc
zP&TUC_9wV8l_!-qjjLAE=Ip+z(iuO@16ATI%KuHMa-M+FNmUvJ&8JlRPJx?NZKJ2a
zjOylVQ2J2iX9mzgo$w5l?pJ?EyU+vbfA7I3NA;gMXgsKX^ANa0>Vv-ncUav)TVf~m
z#l0A)vw9)D_K&FlvZ2vM9YA06I;wsO4;cI0W9nr~fOl2@M!O9+^+h_I<F0=4OEex=
zC+vY;5B1P~xbLaXeg(u!T}8!5C)6i4qR&S?MmLAAdO4lX@Kf)m)TF<<h6@t`>Q(1K
z0@dycGzO{bsbniy9YqIpL)81lXtal_lc>@rOx;=pHe9`h3b`WG`zY2JsXk2AT_@F<
zTQI><>N&Lfj#fL?VuUg36SRJfRl9rvXX4b(-=gu9x_>i#idV0veMy2^Sqzaxb<_=T
zN$QUlLrb#ymG#haTD>p`uBF)32k7aOs;+nxooVVY%BQ8P4^qJOjQZqmaA(!0X>*sM
z4x{aMrkdf6zASYIMcK2}$-ANEoVv{ek~!*M$;5fJ7wyAx)#oX)o2Ra!W%C8~2^wd<
zdW6cV3e+QgAcbnXgwA;ssn^kRzgYbO1$;`>Q52ppRZqVHM45VS1Vk#-YiFUcQawp2
zohtP*%4AimUu*`TM!k;qJhked&%xkD^{OGbR;L!{fxD#s=yh<H)fef9saMC+Hlaa%
zjs79V74=m+U3yp5E9ot9P5swGbT+C_(FVOqJ@_g}v%1?Ajn~zOLSU&y{lg9bTh%@<
zW7uu#Op2(rs~2v^=sVP*bZEI#o!JfC4YlcMkS_H~I)8IheVFzv-D=S^06l8eBN#-l
z+IfQBe|_rt7h&R-+LJ1x`qg_Q;LLz}-W`xZwF5=MZ>z)ThrOfLn_%LuI-O3c52+7x
zpyr<XTZ&~3t5eG0(}<e?8vvu~@EQQd)OlxMcU--7KAgF)UZX<a19cds|0mRctf%+i
zq<VojTBp?hzr%}Z_4L0`I-|Z=2bqWJNeXT{XmTZRbiXF%ILJZG#{WvKHSPW|cv$21
z3y71(Oj#;t%|Giwj%Y$@7wMweUk-ndYW}DKIi|^^iUwCr867os(<s)`{?A=gM*HmJ
z8XwvNcxc}8gN&!<?4NMhOS7O522W^ST8_bZYq)`!ARkSw4@7)5JgQss)A(ki(O<Kv
z10n&M(d957sClUhBuLXktKeWw-!JG3(U@on6siflhrTe)=2{SYxMoQrXoRN3AKD@{
zQYGf%q-Ne4kSI<0Y>;Tp-ZnTKquI6z_*l(WDkF{4q!~d@X{1yL60hk9hNUFUQYEw`
zYo3w-a9T6=HX2hjPm<15jcFK;rfE7Uw3@Eb{RDExu9=`(m9v`b=Rh(vnRJz9YTk;3
zPg$D8*MZO0<ot=5Ij4DA1d^k9gJ$-;#*=Ejay3Wi0hgy)N(GG<G>3#}%-5`=+ps{h
zi;9H{HKGjQiZq2EgDcjIQ39Yu6T1=?N;UQ|D#a+%G#>(6uIb(fe1&F78xWP6t1B?i
zRhkb!f=IPy8Ey4yG<hFFq*fC`$1*Q!A|23Ir<p7P{E}u@G`zp8VV*%_z2;3G8XGkC
zH$cl3&1Y|-@2X}2MPsgMzM_{?qh^J@8&lJykx`bcS<`q6cCTw@&4K$ZnxDwiR?VwH
z(AK8Oq;I0NYtkvr+oAcS1!_7q1s|aChURzL|8;5V3@~w1vzT&{y_%kSNcL%BzQT0f
z(tMZ$E&Up8Ajp6w{V$L~&Ewzr)-Id9#y+b7z+uhnbb4e&BPv7ZsOG~*@f(h5GANik
zu8~p2+I`J_A1HmG;Vyy5gvS3N$fU-D&iPJh(!8K$TJs3~A~TvlqhR-;MsCC)9JH!F
zi0s#{T!uM3pk4MaJap8qd<HXfQ2Vo;k|Kw+7ic4NSnEv{u1?w$olxVfO>+X`h_;zd
zq_}9^R-y5zR!oI2$FzfAV%V<Qk=x+hv;%&?xoab6>Ex&NPJ~^5?T3p&0<?`(4HKwU
z(}pofdz3y06s+AvQH>Doe61b$P;CG`*}}Ay4&cJI|29H2LK_th^O4$TD2;ehyL=Fc
zDD5<@;G(s<-RO(azLbJd#A+j{^f*p?^(h!UrA@sKXX3Tn4uT|T>kgtZQ9F+V$t3Np
zWspqPzWFW4Y3;ur6og9AzOn~ws`feBZl`G*Y4wn<Wm09s8SQQ=aXYJhffoN6+OOz~
zDVf?AvmuhD6-Y6dY^{F?Oq|oMSqhS)Eu|Okd2RStFrTaaiQ;m3+6QrHyr7++r*ytH
zpVnGM+6E~V0TpWxrJ=P%n@r2+Qti2YP+F#K`xW?dt)mb6Dzv)oP*bTD|BAjU?JZhd
z)@a-L5UJIQ=7GDY^`nEfb=r3;K`v?6R>8z&Z4m8u>$OHI=xxyc@ix4_qCHNrm8;q&
z894hjt=Bpr8nv&|a=%Gi9goYpSv!^lOV_m%w9jtSK10vmcJ13gf^=#ZQ~`fOJN_F)
zy0kIl5V@(HqC;}s+7Bq0)1#d^2Q9r?6UC?dw9o#HIlQG^NGs%i?Xn^`GoXEfQn-V5
zZ5ajTZfk#EjM3lGemwxCceR`8fia~0mCjDy(|$@>lws}u72rm+sxoLB)vlmN+L*SB
za;f9m?;nA|``T?A;o1Z3S&A@CXeVz0FsUtVfX*px3WYkRwNf@z&uF7Qg1v`Y`w+$F
z_UqKNay+2>hQ2Q8s7s<?-(lT1$>?*^9j(C7oOKbQaQ}!d@ktOD-T6;o>8S1z9*CQ6
zA(h>^>tbI+-*MgEzo5)Z_a4;?oY2)@hKRRrwg#M!Zae*izPi<SA?c^vZGRiB{<`s3
zVIn|xj4rQ0-A$?)3DRAqbU?7KY$5O=I(Lf1h3cdf{0h@)yugL)e%%i>5jyjHn2*#k
znSh_vb&Y^T>AoAp2%~kC^h?I*yy*=ct8+F&S)6Xn4SlC{`g~f1$Lsq2K@xNoF3^^!
z`-ZA%l5_{@98t1v_9{4YT9+h&niSnbx>HkiUDGg;rt3HYE?t-TGq^LlA^Nh@S>2`r
zD9g|d&>65yop}l(S-N*WhlklZ3kBlO>3Z9tGe_t35`APVPghQd>@Mi!v~tYX4K0WH
z0^Qdif)wg53!uA5w<#4|v97BQN=tN`&co4C-P4p~DAR4Og-E$>Lk%od=%(q7SE-BJ
z4pOD7oC2xV6$k*Y(Us)DZmsSsid|pSUE<P*2J3VsA7N;hbldhq_hsF{RVc03iT7c?
z8gv&U0KB66J``M|ZabAeHt9Sq5NXzN&jNQ{_Z!v5wCFa_<E~X_q3`~+>9%&jM7!=a
zI-Jm<`{xmGUAkDRb-by2(gTywt-IonM*AHd=N0I_tBacpGNi*k2p73-u>>-sx<<+^
zj_Jzjbk4YL<Q6R5*V!qS{6N?KGPo(-7gSh3tt);RWJWheL)))+2*j`t=<8mC7DxRO
zioG4w3+bfNA^qewC_AjLA`g$-^|u*N<DpmH!F}YZzeXp@y!1=!;P(lAVFxUE>;Lja
zpO1by1)6;IN7ex7r#I5f`s?q%49Nif6K7yPP(Mst+aUcA?RSIqk5CLbM8AusGEDED
zkH&EQ=T-O(BJ_V!03%Xw#|Or7&FXh8fQcymOTWW>tiCuNz&L$%KKf4S!#{&)ygv0l
z98J*QrFlx!|4lWEN&0n{Fs5Yv<=YTBt&hzDAVuG~74THO`ziFL=})}^E?w_yhR7Lx
zAcYgp>V2-lUWR^=eKuM%^|?&gJ*T%(t#hvaHL5qr(-(XKazP(K#S{7ZNB#s?px-_O
zrG@&(?3jci{VShhf{XP9FT%AF{f1}YQ>p#{W#h~A-rjJuT>s7mNLJ{JX=z)jpQdGG
zm45AK@S<A(q%S2wYxG-bBUG!uNfmY%^@exA)#<~p0Dnn;;&<R1^yg25wCKHQh25$z
zT?I>R`eG_3XxG<-Vh|nrPpNplQ@?aR8oTuG9s#+jZybeWx4!Ew80^u%Lg9>F{n#5I
zefr^#>HT+0KSrMg>enYE0x_shr#!%I{aG(Kd`G{Tmiu@0Q#6-DdJY{QzNhb|6vwds
zKpm8h=sl0ZwNbsVC%7^F6SUqQ*KcsZBs|d1q7y?C`se5+F{$6}iM}cQF)GlT*4GMY
z6Fj58eF(ZA>IFm`4F19B+;7-T(TM|wqwfIkXn4j0z=MXK186*C7@7}}!-o3<Q0ipZ
za1_IKHn`DMcEnJU4oMe74W%gD44ra#aojL73m$qHUf7HQdKx~WgE(G>PmjW${e;1V
z!p+`>0;*o{GZfJ0m;4REG3X3144a`l(BQyEUyz}I5?aBAO?3V*#E?(H%}~Qyx+%j9
zZ|R^V!q85k*+|38eDs|(jK)G)l;M@_fJYm`sh}ywaONT0jx{*Z$~w+&h%SWaDT6E3
z7seZ^*8`DY_~22fNi_7n2a;^qL|Nj~hL>o9Qw$mZKuxM)uOF1A8O*dFI%9aBZoIRG
zXDGCrVaTb1vP^@i5+YfK$Ryyh4V?Sn&Ka7?-g(0hlu61p*!Q(!+VTt%s&u<xc#;9%
z@(s5n@U6fQODpq2L&|qBQD&Ge!d#Ra&L2cyg~6TDo|Oh0g*B=S-z`F4jlnMmfLcS~
z6#6b29H{EyvSHv`!0QdO=rBct!EGMM6+<)av921t?X3Vd8WL(@x5=QTBgxH%m3*ja
zH5Ac@CfW>sUqem1;jINgbQmsEu&&dPR|vojLktUmE<^e;NOl|EIR(ic!x<I~_8MLu
zLSLU@-A#CS%kU40^cx!6F+l@{59xv!G-UloMX<LGzf&e^$Z&wtt@jLzXp1^*xJ0|8
z5yR>o0FD}7?m^#}A)9tN_YIdQz4gGbgQ^xL3>qFpCJhenp>fI}{Sg!N(6G4|k`6}Y
zf4f&>E(LlH7$ZJ~_m0LZp965v7~oGqsKdrq7DSzl3v)r7jR_ARdc;^lF$)*ta4tk$
zjj4lh)XliK6eiq_HSfX0<HooWh<F&gDNE&PR6hxSy^NuhGCN_s-3<|6V>$(F{EScT
z0o>pCK5cmdj2kEd5op}~0^NVXMqU6AA;yqOkWgbSg-XMXKT`N7!nl|g_>sm^AI#TD
z<LsR<A7#8S1~t(}sQ`VkMmrCUamK?hz~CukmKlxlMjM?^Nie>PCGOlrV*@?ilZ{>U
zraNu?nUtj%jkKt=ry6fw#|YDmw|c;yH7+;~(F~)@4yegA{`fj3ILlZ?BH6}IHv)go
zc$Dns7}LVw;dx{JS&&>~Pa53LGcKYa;RWNz3*b|}v5k)L6&TBd!4(?KnNVG1jJpCu
z#l|!h`bz9Z<5rj`HAYg|P`PpYP2ekxG4zX88kh3mX_c{^_Q}=8KdwMcjd5i*`f82s
zlrOnxoZ13yb;bxfvU<t5rwp!LHa<g9*m~pJ-$Q4E@kd&cUokpRmg=gp`Y&+TjBY=|
znMR{MmNsHd#?2<EX*NbvQR#K#mR~_yjNQ*80Mce$I}5{ZH$GJi(qVjwjlNFfO3I?#
zFm8Armb#3aTVVdCv2Hi|x{b>o0qHTmM@3J)#&G)XQJ*o4N~dla_fr0$-}r7E00Ty$
z{XT{^X#8I*T5lU$*MQtHE~h2IUE}je(#^eRbfseu!^WHRk{K~he}=ws<I9wgx^J{J
zVoDwuBYuT56UI$cyf<k~rN{G>vGH?^Y})vM!k9BgXNpKaG_I#JYYwJ0U!!lo>DuS?
z8a-g@raC1@Qwe!-&{XLM(L<)Sub}a;=_jg)a55de2&K-Z?<3K7#8mz!Tyrrwj>GOz
zQ^I2~am*CA1)Qs?z8N?-)5IuLyPMY2&gr=6J1qbnrkW36!P7KKp;<4}vM(qIb;6XF
z0KdIWO%I^P$Mi=pWPDBaT;TmoSvAn+Z(5KBF2FSZ8IVBJ_tgLdnJ&MJNenhUu>`t9
zOgYZz3pM@rBn*a`wmc6KY0}dh`lM;A0IH)*dtQh4(WWYj3B{Po)>9E|tm*Amh{l;Z
zj3B2>#w9QxZyKUNM4~C09%)IY#&aOaCN^y>(oB&QEKfIW+m1;*V|thN?q^NEQF&s9
z>81&|OjCa~`m#*F(xyM#lp7A!=S<Rba688oPm!hbrZ@|f*>g=V(pL-eOyB&8&I_iN
zGZ;+1>CI9oEih?l(^6>q*%_imrYr?WvFXkzOq7_`5unuMyA<#;Q$-6rEH~W_0;w?l
zLWjL8O)R<st4s%Lz*U>nmjS3TSx>{YTGJ+a8(y@V1fO8q>P)idAalv&`#reJrYxGh
zdeaQO&KgWlQ#|5|Y04Gks;PMZu3a--?1H66(`GKTHJOGJz%`qmaDg+|O-H}Nuv<(^
zXocKra-9W{Hd9tAEVP>rYtYwWa^XWur^#;l4l*}P`WXzg%k;%un7C;gSqzzO)A|Jf
z_L#o@0;0X94cXxOOpdf1yk$zIm{Py#Gy{?Yrt#0AWzf`-i!t3c_0db>jwz81gLh5o
z&!KV1<lY1Bp6M$`7#cRcPVcV~lfq7C?M6*6QR(uS={?%HjhnX8rgFkmehJ*9X`VB5
zPnq24!!gsQybI7aV`}6B_s|skHk3M;b5qc`-`sWsN)MRxHo!wivz{`@2hCs5<LZ#P
zdp5Yk=6|=rZ71^+2O#Ne4n`6dx087%T^KHA_ou)eHSZVz;+VPlQ|NXze@$15oB8B6
zAl%J4|AQCD&CDiv=wWuC@VKYhPLFOcvz@-4al-t}NsQ3jTuM1qAM*o$Ncx&n9bv)G
z{NPCp$=~cnudx6#Z#ljHg3aS!!BUuczaFjO=67jr8(|)7hVDr7{KujDq`CBG_!MPc
zMP-%I=GpY{i!rYjf{QiVhhZYlTuJHWQ|9{=w~05mD&cQ}`5N86iRSEFxSeEfc?HUn
z&F_2-a@u@<f<6L}VqP*0(NyyrTF9iCchhb%-JD2i-ZSR?T!@}Em%f0;46_qm-I?Z#
z6c^7jKi37j+2-AU!{2k}CuobAW1bv>Pv^}Y5%4hAob?)TdFJU(G+r>Tpd%gmW-gr|
zEiiv|9s{%&nmyXkS!8a~qP5t(q7h0<%r5klFExLmhWRq{aw$a0&F^dgzQW9yf)|zM
zDB2=cnXi5ik!o|`831a`3fckHnjI7%7tLFKgll!?dw;{VOJ<=X0GG{Plpm@$yRL_p
z2D=%HXxv=p=TE@yRWnBh;5G9Y9p-2>Kbir2liB()JZ(0w`WAid=3iF9V5hmO5<cB9
zJ0+m6%j`$D(M|Iu+KzRb?Q>wF$LvO{!d~-nD@N95UiT=-E%Q+uB=4GAD&X%uv%Pf_
z=&)Hzf$<UZDCN_}&8!5NxNp|1gliAX{j|WCFz0>)^ONQ)M<6m~o=s(j)8_DK^v#$L
z)Bi1cXg)>HYzNC5KLEbp^2s~k4p;<KMDA!Ar=`R}%jYu~(jiM~3A{LLX|Q*KI$0RB
zsCBjk(H{PYrR_LmTrAdiF|?zWxJc+eW=Wu89#_kH59oHYY@LEOcgqnfIXP}Ar7Ca_
z%P+G4@U*O;3&P7XLZ25oVPVkOTyM*tbf@`PcD;<@`dUmX!2K-sTdCN}-}2atc*O=-
z5@=|FmK;jy1X<=K!C<f@U<L3YmaSc|6l!6P0T^caZWkKEEe?Jl5f;`?G)7uJdK|h>
zS{^lli?Z~@VMe1Z-}Rv}#`4EpG{#z9utIg5B|wF7p0af9ehl|tyk+MmIGkYljZR@C
zTG(_RHOVqc_ja=7YcYH}Z5i<eKE-nN12m>u%(MVZvjpCN`E*OmY4n}3RNK&Z*0QSs
zeHoSyCxFYeWV{D2vMd{l!DU;Xq8Hye%N>gI=33T#L`6V(mRoz#dBHMQ3^n<d-)U+J
zEU!9Y^o5qhD2NtWj?yN&*z)*~=qs_PJTZz=OL{y+$}G<<L1VeaZ5|pcEYBT)7nPQw
zuQ0+Yi#yfjS6fE&VWGy7#e=`KmU|l@dC_u@ID4IC`;&0-lI1XMST9>V1Hjc=_-lb^
zuxz~ta>erT0F+*}%%ybeHH(K81{*E^dZ4e#@<a~QG+W~8;Nf-4LRzx5SRSF;>Q+nF
zkC=-#i*FZ1+AXQ?L8Qa-#SQdzS~gG;^M>7W=PV3%SwiX6(PKHJhHt%=CF>y5XDL{S
zzFU??3LE!ZcCjHcVEL6Yl!KPPs3z{V#piv9+_Cr;VJ_}kKA}@vLzZWEgS%&8e+$WB
zi}F?I9I=GQ0x)W6qd3Nx<>m|~Xxw6-D1&eJEsxS0?}6nEc{*X4p-}XsC7EJbQ<m@~
zD4n*XPr{2C%UiU|d1z74n%Kd5mMVkxTMwK@;{mG&1DvDv58A&Sv=(iIvP0H?ZbQpq
zYn3a!aI&t7M5D7c=rYI=>nrwuVadgMnNkKvtr`m79<%-s05z`G^HkE{W?d!&=WcbH
zfWhO|h2F5_VHHr6z|-na<t$#-kvV8QVZAzzAI95yNd}ycHDo??`dO<J0Qa}PAb|M*
zYauOY0<B}T-wd)ol|}KFV5^p1(IM8~zCdTFwJINoFzXm)ZNsf@)o6^ceoI@^NGqot
zjVG;v6fKLgzDY@^XlwK*ATie674Rw6`gR0F;;c95*_mK9(U;v4t?&85P?ELoB>YXb
zX402{PFtg&p!jEsb$d13PqqF@<&kODun@?kTg`;eu>R!%V5aq#6bvTIn%@e^9P4h{
zRGznP&Vy^Y*0$y7%d-wX0q%k|>>qIX)@pyi3#@)WLua9tnT@_8>!Fu{E4D7Ds78r(
z)}NFFEwye;$6(5=C+WFfZjD|G(F&_K)j3pJbNfN6tim4Ht+twIfnQ^Nv>05iwVJA7
zE?PU+0#|3vp?B*gYn2Uv%hpf|+tynHhrl&h)9I$XVojs8*j4K!#V@Z}H~$P}_D1U=
zC$LS{_6o=}TU{+6*R4?p;9`q4ycnd_dWd!@ZPt4)qOaXLVFRGUn)D?|r*&&Ml-{s@
zNEym5>zrRfZdy<L4M4Ybn$pTW)^bXV^;(@w_$m6V2WXtPtco`v*>ATl7zR6FeQ_t)
zL2G^<L~mRFeH`SD^*h?k-nFj!5M;=jLr<7{Rs##e9=5)*8t#u+GbxxmYW<O3AY<0E
zlvo<KK1Uy=xNrU9d*B{eg%l*5u-<oo_mfu1cj%k48s*S3ZMCnbOyi8ThPGS}t$He@
zaIiV`Lz|<mgTDWA(6;9c$RXQrKLdZ*_R1%abh1s*Tg}<_>O+_~VvDD&jf;(wf$2VK
zdxjQ=$83UX%#5q;mA4`3X8UR(8r^MEw8%Pc+cN_#9yVV)Rh4<#s^|cam+g;Im^fj(
zz6ff(ZS54t^szlp$N7A1Pdx_{ezv8Qh4i<LyMYU^HPfRo&^GRe#vohpqre5*257q-
zV*7;d%}|@85+Y%?97?l>+cb3KJHqzGeCUj{Z8>U(`IEL?bXP^$=J!HrwCy;hbYg6)
zX(<zHQ%wR9XJb;NCc!p04S+<O_%94Q$##;0eaW_sA(+F{ws0?qq}VR3h51z5C?!GD
zY`l7K>9*0un1r)7mJ1p)Y_a>`TBhx&j^2M+w#-jqFx!^U1bmJy=vinxZ`)T0M6T_}
zVwlgf<!wdZ1zRQMv-537DF{_$`|=xz6x)6;h0+q+G#&jewJ`#~mDw_>@~hld{xV2~
zty2uQD{T+nfxlI@MykKAw(-L$|5szX_$FMewb}UqUbM}wgqk{A))F8t*%GNT{j%-#
zOF-1y*0cfNU@M?g=~ryCUxaH{ZBZ7$ui3Wk0@r9eNhd>^Z10Motl1`4qVKxx+sp8`
z#g<`!_pLVfN1?OLrk{oud%Law5G-}rO5caf4cqG3P}61mW-myOZ6XQyUfTw$TI#dy
ztpNU(ZO$72_S?4opQP)KtLkXl#z<niCB>3xViHaBwIngc6g5#}5{<X_-uuOvUanY?
zqEzX<NfQx75D)|eQKX8Xf`}jp2+{-*knfp%f6Z@qXP%ked(M`b*>lM&d3XD_zd*cq
z`x9@X)VDp5lG5&NfAAOt`nTKZ^g6ITkG^I$xc$9efZgA|EE_B%+ii45Vbrm`m|olm
z+ehAl{Mhyw8ia@2SJ1~Y$G4yS1!FO>{R)NuC%1R4fZ(I;pLxL0sqHQFZth~ljDhTC
zxIYhtdl*j-LtrnXl0K`qkI`U(z<$OI7ic)ZFa$z_7o+xj5O2mC<3RCYIQE;t<I8Xq
zL7^Wbjjq-CGd_D4pn;4Oiqi%$g8LvJ%(!y|*ddH(o`+y4<9jhU!x*<IY#Gk@heG@j
zjOV|E6_JcwiaSOzB(xWZW<+(N6vJ3g`MI%-_i^*UDUNaCE-K?0{*DmHA7}hJ4QT0%
z|1E}!3`S!MU@{qx?EvUW#x+U?$YO9;f}CQ^d<`U<QL+V`IgB>?e9UQvxC@=gW&A>J
zvOLBchryE1*isA3GmM-6UBzTX!P)0j$XGKQoM#!;%}`&&I5psad@*CV5u}9iD&4y{
z$B@%jq?8fp3Yap+7`eyKGa_C^shqKx;wBdu$6O(Qk<nFxwhBhKFZ5nw{5S{Lm5i?`
z+FQj4nGJzzM$t5|)G%hg1P!%}$H@0x$M}lo+{=u=Zaszfub%NH`30{qHc)7#ff2C+
zjg5>C=&*B@5ke^|*BEnOK;?BtFddt3Ftkc2Y+?LM3BflRkuGR!WkkeaxNb3iI0Vz$
z7}YO;v@?DyMdfYAYZONBU_3#2Yn_Y{FO19`h6m2q4yP{09-3&n88K@?dKkYBLgFq%
zLP?grj3?+b7JZDdd?>uf@T3gLe#XbQQ5s;}_!Ol<M$u9{okNW5Bd8o^-0y_=ea3+V
z$c-=xDPS?m*m?kM4;W8=0xQNC(_e$YLq=!=y6YHcRLz3K1mjgVsGnq9n2p9qjL+!|
zF~tzkHg*^D{KqiZg?Tj+rQOVV`@yn@8AiUdz06Pwf9zvcP_D^-X1D@lae(Qaf=V~$
zcn><^&YW=zR(LS~GD6Oixgr&EhnRB`z<JogoS;*?7xQoq6nZnyeGcNoteXxAU*=Xb
zB>b4&-=fl=Sxqk1Bh0T!eE@U$vrrMptfoANAZE4@ZNbbhO3@a=e6SoOl-WhUeHinv
zREUQ&dzXPTf|*KTz({7l4+bcT=@12jCz^R;4bWnkwfPW?W%`f<Gma_iM4#fB#xpQD
zfw_j_9!HrsGQg6^?3@d^B<2e{z>>^-aV;uSnAJvDk;)vZ0_QR2Tl1kJjoI3P%Hzxr
zOQAlUnM<Lo6U^NK(3infIDP}oWbUm1ImvV<msl3_h2;P}#Z;{X$!7jAhRPh~S0A8s
zntA(4n3l_AQ%*r1a~f^g@|nL-H2w_pG83a#z+6eL&O&C20D8|dz35(O5%Z&$p}v^O
zqU~=9^A%bf&oR$E?Ep+E^9==H%9xAa2ljd9%R-dOnQQ1;!3AbP9?&i_Mc)Ctg85hv
zx^{`VgErIE%%k^Fs$;6Xq2e;L=XqFB&zwmSp)1TMK83;tW=lRW8=3Pd_Is82AzgmH
z#(Z=SrRz+=A^HeM6LUJbxtp0zlNiJs%s1|Vr-dn_$>b(eNw*kVnX~AU+%0CTFF4zn
zu~KlhGsEYg?KV@a0a^$17aG}4=DY>4;tul`?U%cl**XYxGr1WcJ<MO81i8zs$c2Ty
z%*9z0fA3?uTt!FkG3))Iu%Eev2~7jckyYRsWd8gr+J>0l(X=zn^t%pC_n8m-Q5s>!
zkq>*6`F9UMA29Dz_Rkn|>~pj|WIDeD_2Wz*a$`;~Bi{$gBy%^plpZmU)5Yj1<{CPo
zI(D%>e-f-NtUSu*-pvw_e|sP6)B^NyKg;udkOQnJx&i0Ps=SG|gDg=hh#Tv#Z&2yU
z(oKWjL#&<Tc|6Sed=hOwEc^Sw^ksdy7$rZ}Dk(<PpEa5dup=zxOW+J(HJ(LVu!A+1
zw!a~))w9qT%KC<;k1$pdxl_Vf&6JrC!FpvCBqCYM>3k8zx*`H+G;1wQ=rOE#dN*TP
z%X#Qp9BU43jpJFT>55VUYyB;hj<P0IKuKgd$-$Y#O4x>OC$qky=w%AaVO<XMQ(1q_
z$69raHHY4@G}g8fU>|4Ae*u;0tgN?zc7kQ2boC5YX(<FVSwZy8ypybrZ{R7*VzKEb
zJjL>%RWzFwP7bOZ)-EepPP25hbIWB_kk34iHAwrweAaAQFwd~=JLaIafHgG?i9*)h
zF_5#Yy$K*itULxtF)M*4lM<GarnGacmts*_%JO>vL(5pdK88M>XKh&nQqGFJ1?&r~
zX)=(DtfK#10IY@qsK3OTybXa$)-ie=s#w}_l&V=%vmEGQ4Qmf20oAe^3(#1{O86Tp
zF0=liuN&2~W;dd1S6JJ~!Q8-_PqB?gmcbR|Dr@oQ7|Uy{Ui!4gb=HkeSlGmJ(0kv^
zvLAxkH(CCa%+|_Enhy(av3~y;m~E`j$T8i{+U7$afxFG(wm`mv6)_WI(aHLdeu_J+
zsm}n@#X8smm~K{M6kvK-9#%Z0cUfyc1X?d^ErnhBSdL7f-D8=_zunK;K`CwntQ$fY
zGsrq$3o^v|eG#CCSsTb_cb_Hu7c3*JTtw^~PNOV8T9zKLQfL!C#yXP(@{rYOfx>ZC
z_aFo(ScP|?Vv=Q{XY~<lej3`QSbxm}=Pve1C)nh|KJq;5-Oav4(X~BnMhZ;Z%icuG
z!anxCY0$8r-5~_n0e1O4fVr}zWe|59WZ&Hc2{-m-`qYa%dm}k#JlKzu*UXds6Caum
zv3JHm#bNe`6czVk-|7LHH+x$YN<QqnbS=)8{RDX~{Mc&(LHyaQ2~-|o&uao_0Grv0
zF$`q)>tRd~`&l|I1hePT3=!gB2hokCP<Ht~@Px7d-HcK=`{ny6MX;N{gE5ipvUXHP
zvD+x?D4P96G+<)b4HONGXNQq@BY{2q3^<RnU!z|;nf)5Q=_%~T=YpiN!)XpY&K{tZ
zJ)J!o2eVJGeV3s!gY8h!Ni&n}N>kcN_A_^3em48dXFzh;Db66L+1xo$n9Hu9Y>Pbh
z)5w}|%4avx2Jj5Kdk#8Nz>fVd2bb+m^XpmmG>UQ+vFDKkznJa+3OGyH{uBc`$KFQg
z+)}oTa`DR89S&a<&$GV{M`JmA#giZx*qxUke~}&ZU$!B;=^zwdV%sRFQOQoB@3U61
zU!WA5YPO>vy{}>aO3ukzcGo=gu#Uaf3_~xoSJtDgp8Y*J)UL2kk%y;&?L^nu8`%=N
zaCDWe`-Z%t*Vq&E8PV(PDYCSQy|NI3&FqgXXuHAo`WvK${g9rko9yS}(ALJDod@&V
z**>&3-ewQI3D6GquB{-Q?Ea&$@DBUfi{R{HD+Q?RW+#$OJ?!^JVCY@;<1}mavJW1h
zKiTPH-&p|cd+cw1fJ8rg%|+NY!2Tu<dI#C{yP;`_J#8Z-hS}Z}{<zO>r29uB>|~mB
zN7*tLfIeV<NAb=v_Ld-UK4h=0N8332#2!546YNi(1DRz1$^i5ucIXnA?ZPo4AdE}M
zoDND@-NUhe1?>Ht_9q~Cfb-8rfVy(Ni-g2M&YhLOcH=N9n(xjTeG>8>obFQ~o*Xgd
za~<NWegWh#XZF*u*Nd}`0)O5d?oyO|IG_K4U)h&)pRQK;aYjFaB7aUz7sMS$IE#}|
z8^AFIg9LJ3p(#9w6Ji7j=5U`vWf;e08`Ot$9)$ojg7c&sG(~dC_JJje^BcK3qd7jy
z(8Cyx2b~6EIVnQ0#Bu5<Koie-_HA@9fwTG^j5*55rmU1ij{E;mndIPXUIF=JPHHGf
z3g-@OLsL0rw4Xc1(Om>+8mInos6Wm*K_2OJPB-~>PH=WFL|X<Yk2dd_oOfNoa*}g3
z2Xa}Q8{~*M#aThez-&%iIx2HGdngh4G^dBW>$#j73WVix9Ned&H=h%c0G>0P^ZhWm
zfYV8lw?dAH+|6e>pT(iFh|?GbQp_212TTdan|x8{IPcM2xl+!A0>+eaMlPaso>N3o
z@p8`HPC#Gai0In!B~B)Jl&d+ji-B3gxj~6owVVJ4ZG-DLZdM3h=Ct#nqMlP~N97ex
z6^&N|=h%CwY~*Co+IW@Y^)1?(I4{v2rkSJu4n4fVnNN|`7S44#gWu##BL_w+r{y>}
zZ*hDqU}@tVqX1evXU`aZnA@Cvv4FnA$@rMo<}OYyZR@%@om(N%%Xx{C;rciQ!7%t9
zXH6hFGsxLO-uWR;!>b^}oU>npWt1~QS+fr~=Vk$AjMGFur3sF@9Bq@FX!^s6N1XF}
zp~;1ts|Ct#?gvRQW)C-~ADsKSmECj+`2e>t3?t;qjXQxMb?5G%f-xT4_nc7j<Su^>
zFkakW(gEYm9asv5KHTyJX!GYfEdl2d?&og-JAm6W2PBwV?*SDdT+^#qMMJr(DW@%h
z+uMZ7NbcglAP~h37l1RC`w;tVhf^F^M-l9Ju9p0#iQGSjQA*-w{RxuHeU|bek8$tO
zrI|GDDf)iJaqhpKuqlHZ<O!QHxpQeIKgo?=2Z3y^;AynwaMM?VoaSoBAeYa5{J*0(
zw>T661>C+u7*oUzJqc(>F?TgZ>`S=+(w47`JB{4y=ebuxVN5yq1B!rEa1C@jpq|@E
zi`y0M7c|Q^aO>y@)5u*%huN!KQv_I=xQ%S+ZRX16f#nAGw^RtUaDypOa+AAe3)HuA
zBZok4aX(B3X>)M<=n73ccNT?6ZgcD1puU4!<%v=!_ai>!ySUHd1$64>{<#C3J=|0V
z^xoyp_!*$R+^7U}`yO}VLv*5_yHg6i1Kf^lz#io8ZH2%PcaSm|hq;zjkQ?RhBA@I7
zZs<5L$GDEG;gFx;Zp;MhBzFV(10Qj3(fquN7mWAV$%UsShr(`NpbZjxcqw0?Z7+|z
zogN`xJY6n2z$?BEg|0kT>fu4&4FYrHO>ISA+<9-&S=NJ>6$pDhd5WbFKg7#92+YI0
z^Nws#FWxs>VTCtu<Hz9f;jP~QO}@MoF$Dd1JDx$MKkv?Ta30|e(zmw)c;DEeK9Fak
z=w}eG{$rRO%-gdMoMF73^vs0wvTj3t1W!K%h0(k_v%nI=`(Y8}VtLtLz|aKVrXR`w
za+LQl8;yy)r+tBz!u#e~7?a9tUWu+9<8ApCFzLLAEr2<}TTlDf4BjCMvSsnwCn0x=
zm%ark*}M{(eR6s2l%tu)yAT6`d|v)NuoUv%B){BQ-XawSzliq<xh2l=wx&`3ODS&~
zP48vA<&;Ewp2wSl73I9F=TUiqw|XBey~tbZ473W~)+v~Oi8qu8O_jWV-Umw+@8Y*W
ztLCMNVMQ&^Z3o)wc<!mN;xcbh0l?~cq02$8@Wgy@Ht;Mu$Tjl14%7R0jh9GH#_PPs
zCn4X&6aES-nt6+}q4x&w2Xg4O@Sdl$+D+aa`qF4C@8WtGbBnjF8Y<d&ztcp~&NEVf
zZ}T)>Aa{7*P}X`E@2CvMbn_0=z3N_`$O^rEyhO?jy2tzQIcRY7^TKFbIKVUi4`h&6
zL+MIGytT{0GtB#GE>zs-ZRMeIgeRo*ol)NSck~4FT0KC<c;!3Mr-!`Ce^DCel~SB_
zg7?A<fKBqUYhl_Wo+AciiuV&G`0V1xnb8RszIPwUZU^6oW~e><ua~27FTaeA68rcV
z13caQ&6KcufX|r?P*;93t-A;LhyMYm8$W*wINkZL{*00be;+0IdGejtf%6dmX<F0{
z^Djm~g%^M6Etuxb|LP48A3o!GOpLz#pKpW3kMGc)g@iwU5#<LT;s2HZm;nCFkD)h^
z{|?1Xg82XY9|kIzpZ8zZAb+JFU_$vlzd<03zabeT6VCsP;_ngsr<b5IlHW)-z@zy8
ze2-2<^ILxdW(@zGPJqSoWkqO<<1f!bDV~4Hu@hz_@I%)^#Zmrznzj=8f9o*nNqoWY
z=vp#=1s!No_)k4VWh&qPHRO-+^UnY~jo(U++T(mJE%fR9QA+YU!Cy-YNCy8)I&x+5
zS0<zF6rY)aE@ksaLP2u){y4Nao#tOxJ3w>!vnpYJ9{<VTVQD@eyBzEV_+vC)1$-&J
zc!m6C%JM(Ue~Uu&Mf~^Zyj#rwg}j3${25Pz<s82>57?!A&p}j{@rx<x={&!Wd_v`X
z-`N1Wz;F8kau@kaDS5Vn|2~V(f0y`cGaymPXV5k6Dt?<CtkryXF+gkh_Gh55mY+sH
zWgY)5F1mJ^{|%kP>iKU{3e*+;-*nz>;Ip1Wsgb{lo{Ove7#gQ*{L#+<cAc*#Uw;!n
znBv0C{J9joxycXtm(G8!{5kYI-{PO4b4?pRm9k;l`GS0?xXrIDL1hR39g5d<^56Lc
zoOk$#kr?IF#qUJ?(5ahWaRQ`=KkY|U-sMkH7`>P8KOI)|@f*oqb&r3Y;w}CBFKAI5
z;J=#)&Ov^z1!g;j_$MedI?NBdh~D4le|!YCjqn3KATi4Sau9kS@ZY1GC1d>A6ia=`
zf0pL;aenikAQSxkcF0ZgpA`f25r5G-kSYHCGvM4M=>HB1T?9G=rkr*QR?v^WM^LGQ
zz+OQX9nSVS1Rj*&uwU>SeIMa~puZPJxeCH5{%}xmfhI9Gftv;L?gFQ)koORLPz(W2
z!KqWwbVx9rQcMpE1e;OmCGc}bf4v1iK7@deVDl`Ld<B&o&?P^?(QL5z3nsS!^N1i{
z0`UNW!-vkhfr6LQVQG*c@-vJ@ut4%FObii(<$)(ua3C0#h6(;hLDX=;&*a;Q5IjRU
zJ&}S5%I%I4WViz~TJR&~i^m8ixL}DD%z6nVPM{BkhIqloxe!kfjI97k5~NbfRk9!p
z`(M0Vf@}0Gt2DvZh3NKi!K_s<I9-rKd&O*lxD+h8g15;jnkSG_pe0|h@+`<1f$n2e
z76|I7tx#}nJwVS2(#VHgB)It{NU^}R1DNLo&vv3zDtNaF7M2O_q(c0>p#EhCYRd($
z4`IA62-4^(ONGFB4mxv5;7+mmN<n%z)K>}eM$uL+D5YanjbPvqNUgwW9n7v1@chux
z%Yxs7P+2d~Z-$C1g2G@3GzijzprKJ9Uj~I&1%Isu*fl{aWszPNXqoi>H3=AvFuz%F
zt^*2h2tJ<<v=+ht#zAfh9#jLgRlqz03vUT3>4$9-^hJZT3r^9Gc3aR=2rD`S3lE^w
zDcD9ghVBT~2Y{tZFzY9j?g|2&0M;vb<~TU}1RvZ2xhMFxfbw7Z1$W8$JRnG)k8TeN
z8YnzAB>0lN1;c_X+fjL6kXwVw5kav9of#Djz7Lxo2-4_dU1Nerl)?W{uyP#)#sweK
z_iiQxie6Ms3Kr2vOdkm>ULaEfKN8<1JS&2}J;Gj!cR2P63wA@rKH*MU#rF#rEk@%3
zVI=*@xU2BJpV5nh!VsF^+=Q1mW1QTD+dhFN58*0`sdx%^Q$XsFaPyClJ1k_<o9-oC
zNtqblLhkDj_Ys<(f`G5^$y?y`6TVC-vHn8q&tN&?5XRBl5g>FoLoiU7vJMhK!VdBe
z1Pj-k1ZaqGGr7V-h3jJ=A13_mH&jLncbtUTQNrcFpe<T>xd&)*!o)v8;)QR~m4gJ~
z&N}?sNy6DDz>+L%qo90>u%sK%X~M}CR2~;PI`dFW7e1tQEK~RaZJ19A-$}u6X9>--
zp(0zD^(IJ;@XOaBe_E(uKt-<bC>;~>glY5yo)HQ@L|cK-iNeE$!poGzS|mJ5K9*wP
z$6J6|B3wZ~?>V86Qe;YnCi=C`3*8*OD3%Ka9x(WVus0lfD}*mNP`V^sO38nf!ZWn-
ztP<Yi0km4U@+R!96^@R8vrd>nG0DrqzPmuH7p|lfiYvmaKS8cRIKn{XHQ~!L2wWFh
z>HblZ(DO0;uFb-7QhP&a^rZK%Md(f^lAFT93;2Cog|EDV9^MiL&~~L;xSF<ZJ;KpZ
zkh?-(iX-$2^^c=7eL^W6%=?AI6u}x02GYg7L19)6+J=SWnGhcp_Pe3&fza?B6pabv
z$lLr-*mfOl<HB#x&cOROA!M9}rIW(1o`?EJ!he^;;3;7iB`WL^?W2dyMRe~&NbD9p
zu0m<Q=pwCA2Si`UQ0Xe#PEW}}(N*$HxrvsC(L*X)MnOyuQO8p-##59fg4`j|=M=&6
z6*a#N;wN%lNd6ap(U;Sp@QCOLg=+&uyCwh{D4L{;070TPbg&2(xm7_$i0Eq}U?N3d
z(;g;Dv~4{|w5YBeJ&Y0Ergb+~R7Gc{I8h?)g5yQc+`>>Mh#IsYM@7swC`uKjP-Nwp
z=-iXg;7AkAr8KGIq8u3vP8UtLp=&2ZiZt+Kh<?5Z!Ay|{r97V$^}hgx*`gCK06Ryt
zp%!hYMPd19%N4C*0VPlL$9ACPi&ijDc}C>o4bB2lYYxB)MWWjfI4kN{3zQ<!x}|6<
zc8HdZqxQTgnLNbhq78pQ{(`8y7~Q@oT0#!J3Q>a<XqQC6G&5C-f+#bgN@QOE&}tE%
z^1kauSLlB9712iWDK&_8(D|)VbkGU?y($_bhxRqmEJ|3rF8cB=y4@uDv=thfMUMVD
zNZb;w*#=E*qJ^}}Y8MUo1MRlxqXv);(KqzucZ%F8Z|;t0NDI;>YNh~sw`j-9Fy@}<
zI~^+fMNOW-9uRd?<ZMvnPVTuOQNjb5JuLEB0fGCX7g^vO5uKz=vr*Ae2i@X$C@Oma
z#c@&DIT$q|TD%z&lcJ%mKzk(GM((mH(VzE$woAN(GAdle_FurVTYUCCu<Q{}lLC9M
zIE%u|`^3YPpywvunt+nK_%XUr<{|F-5uBc4AMz?568}32eTT(MH<16uOB{S0278Nx
zhcOmD;)G357$6Qj4Z%RMkY=wSad{HZg2k&tAP^$%A$M1(csKc?!o;O?A_y11VT6hZ
zaVQ6!h!t<8M=wr1N{?Q=cn3Xt3F0>?E9Izo!!3v>iXW(H{Yw)6fv@2^C5zvuX(vVe
z*$j|$@gUvQKOw#v4}&wrLC>QyQ!Jqyw<pDM^Pn(GeCG#Lo)XK%K+6`t?FsB0F*gee
z^Tb#3A)YT@IDpa_@jf~O6o_N#DoLT3cN&JC6^BRC`d1|GJP#GcV)jaq67jY3=<hjk
zFy%^@iuYdxcA0pm0SYU`7V=eG5-XnoOr^MY0gR~<Kd?YkwK$e`7BymT3i{TH*Z&R`
zb>fW|fY~UHrS<Qscm;*nuZg?Kk8xe>Pj^rpP2#_-=tZ+Q{s9_qh<#{#)*=>BOr%|G
zAz$)sv6*tEJH(U6=s^@0tOmIw7UTl7OPumGNVj;1!plA4)E`0m#T&}-OAd(V&~9>2
z+%*T*4~dskY++cug$KR&#nSz-V#FanLYs(D@!l(dc__|g!r*c7#1|kF;&$?GOo|K0
zulGpID1}W^;%jt%JRoTdfeKfNS1QC0N+zF%3O5PkFci8=xZM!<klg$mES?f|0Q4S`
zymk|uhb8YNLy?!{FLFA2OB@TyY3Cz(g0duiCAa7#;wO2X{PF&hoD{$WNWwA!8YpQC
z15A*lbw4<RC6UgM50TubM?OrlkEYph$wVbe5faCH;Ea+Os(}(Mc~%9?7ztO2%2>%Z
zI{L&(h8Kezm0WYIhG3$khZ3NZBpTXrCQF(ufJu>f#z7)gvVpd4$0R)uftDuWkox12
z#HHxP2}v;R7&9a_ZXlTw^D@YtlthsyAWPEz0mv!I=11s6j%3L%U^y*$iQJL7l53HG
z&Xb%l(EFD!`J4O-XC$7RG0p`NANmMmp~TjJwzHDnBd9Er{1Su#E|#btp;RIfUWEKP
z$s|3`r4m1ywaO$r>2}?DNdS3T%O#snK>UJaMm9<pC5L*!QX#od*AXsBa_HkZl@jN5
zwEk5|ZjzV1S~7!vr#i_widJ2g#8cF#UNVndOIIW;Z<HD&{=;Z%lsxw)dT~wi)HSqS
zm&~EPPm^Sf&Unp|wI4v?4apih__av390q2qWH%kBZb|083zjy?Q(Y+Cmi!b!@%IkN
z?-Z8nlnf@JYj-50l;+zd`6LgTx+O~~r>;lx2YvpqS7Kd=wm!*o9q7zG$@Mg-@0a{Y
z)5d^g%imxbk}N6!%CO|+*Ff$|E}aC+h~(4xP&g_{rr-X7<k#gGgmKBh*N}5eNXq_z
z;G~58G>VTT)pUfJlJp*e{4Qw`xg}hrF8(lPx0FX2%zLB`@*eM%vT4QJC;c%IZTqDG
zgJ?S-jhqJoSLq%a{DacV|ANI$swGdWyR`6qlsu%L{)Cb7l<FTq?vO+JQ7h06OP4W0
zyrl7w(CaPzX)TD4v`PaQU+Ho$80?3CtH-bHFa7R&s5l}Gi3DhXRQMJ221-2*=wXm_
z#uMmaur#9vDng_mk~1h&DkBe3m^AbYkZ@_9JLDpyW&iDBrH=CNArU2=Itmrh(kT&2
zG1Bj8Rf?6???EX}%HzP&cxe&&pcABf=?ZC*^!K-*B3b$to!C;OpHq5bs&pN$IyoJa
z>gk}HCcUr}oX4d<Y)4<xr9TA#<%INi+T3MGXHj-mrZn8a1M5ktf(|=bQga77b4qF;
zzk0UxSBkOcNL}49Y^SBOr+}6#t=$5Jc~YM{fXSEgen#6FsjCk-3#1%!u@*`X&~JBE
zI&BkF6iG8*1xvB?>&0Lxk$y?8hjUV9DmY7}oAPM%%A~JLfqh;&u?$v}OBXys;{|CY
zO{Ev5z4K72khW|9%O$DdW2mo|hOPstk!k`Wm5;sXSWVHFdTHl1kSo%FILI|fS@g#M
zjnd;3)3}OLD=M!^N9aqg*QL*#fZ8VMmy}o0EImY%{0-^mNf_E9RlW`DZ%XB~(6&lP
z)<XQ2RO1hUHmRI`kanrxQP_D~Dh@$qhqUDXZ@Wmpt43qDbm$}md!#LtCwo^qgTl1E
z($KvC?USCN1*l*8{YJ<SNMC&%m4nhsI>`@7OJ9Kau=L>w+U`r+)&ONx+VUDY@j$xa
zSy(tG^`xBrhte^+r#LQk`W=-M(r?$(`}asHqbSvsRFej@U9u>;&a+##MGw$DvS&7;
zv{$yBw$%G%3lqV)U-m;3<XvT}t3VFQ9=i;C-DEi;41&AtQ%d6Tkd3ba@sz1fLj16-
zhGNZLvh=Oc=PgT{i%K6^|0|S3<ST2P1x<dkYa;aUh)hF{q5zrfRe%P{iX`YvsEqd=
zG=<4l^HCWtyFww{2w5!o>>_2q(G81eSqz<XV`S^;myDIAUI18}toD1z#miDDNijio
zg3>>a$}(v+N|JqrMcCn#EK9BdOp0t^6!NLE%K2zKCSyfF{<v&x4#qiMw%`?X?S!m_
za$z%M=d}>Xlx?zNNKVS4=+K@ebI8GxBYT2Q&8KBq6s^sb#gR)kPqy`I$mPo#C?-)L
zd+JBnR4Cg^S1TN6Wk1mGTO{it|7Wpmm^_aqvcL*7mdcjUyICe<(R+Jd)|r7)xh#qT
zx))@TYoPF=EW#P$mt;Bg8dS<^C}+P)mPNBpjVz4`mRi~VXE365vcG2Gfw(ODgbDF_
z*>?J?*#?Jfb1VAWDAPO%a#c1$<eH34C%)^l6*TxwvKbN>b3?ZAI<Q-0FaC_Sn=;Ng
zKwD*FH8A^@?7?Pmw#nKke0W>tOOc8WS=9!p@01zH5!WM|_YLIk%Kn&%4))5bG_ayi
z<~a5;2JxQk?+(-s$jZ(DZBX_#r9chI_S-;)Wj}=i=DzF)H<U(Xv#P-|Dl?Hga!l6p
z1v>grHuWJ)8<(AX2V_FlKnZ7)vY*dFU`qBpU0B*Be~dD;UF1=eGQ3;<(L$8=$TJ<M
z(BHlCM9RqBC%;cug<R!{QBZMEE)4*Wo4l0#3GVWDR)cuRKb?+Y^OV0sxh;p}Yd3%#
zmVfywI^iX+y9_XId0H(@^O1i_Goi0M%?HF!o_-#j{_-CVLD3QU59H1WkQdLOGjyQb
zts6!K$tUU3XRv&H2>lI_FL(_KL*?6hPzsYr97LbO<-9MTB0~N)1->KYqmgKflCSee
zTeMt23vG;i>=H<<{0T}ljgz~R<3C>BK-aAj<X<d@hNJS||A0WEJoe51_V9AfT9}_K
z@1e}C6uE(3|5Uk`2TI4}AJXO_P5xLNdU0I-g%e=X<(BObI3X_xL@7h=^*J~*<)_G9
zbxJ-I0)cFKw+1S5<T6?-^5hx{o8-$w=_foR-!y{KS^0^2@*x+=+hQ;##qvdCu)9<~
zPTSBj`BFM`oR=>=1Br|B?Q~D1LVovisJJ9=q8)CvJajcmHF6Id#B1fRG-G7y<(ed*
zT#^5eR+R?%mjZ}ilke~W%XRsaZ-O+*S9}bX7P%|MxE(j;MdVItmDiJx<(52^z7x<U
z|8_AHw#zrtuI{!xpU$!!a^1V=TBm&MGGOk=6<*-%lCN3}xgL34JW6-vWosbNEAJz3
zS)cqjXZ!~D<Tuh`%z!-S7sw6DYiME{lFy|Ff7l`afX)E-<!gIk&4@hZA2g22M}Gj?
z137aeD#zriEU-M3U!d!Q<MPkw<46<oXWoUTNqJ;6Kp)A=tH3!W|G<Twb;YwDQ17DX
z*#@xP3T78r_9?8<P`F>gqQmb2#ZQ-^!Byd?py=2^#S8^%-4uWP16Fs%b0uK)P_()N
z?U165{FjFnuaSSuOL0>GP2P&f=b_C<5l64FuOfotEPjgEMi766C%y22irp&M8>CoH
zTbN))SuX^_6o)9;DO^!ZxyBKSWJft@q~b_28lx0{(qj^%usw%TtRkTWf^mxdJ}AX2
ztQ*jlpjbjH`%#7GQIrxDz2BpUNs6W9N={aMM5px>MK8@vClwhqOJ^yfJkfSa5o$$c
zwxWch0Xd4HjX*iASY@UhqFhD5Y-q|;*y!w#ubBBHN@o-w(b1(q(X$hzP*D;On6rxU
zbs$9wBPD(nD}JZhwnX9cB0$e63J*eksp2y|SjrUTv{OB=sHS|xaz)k@jJcqQDuCQY
zg%734Rw#Og=>5B-@YsRcN<}MWBvmP@bHQ4z2%11;jp7Y@DQgwuZvduV(VmRb6~#Z%
zFtkC@I1SccQ>2kQ<htS+ddiv<uhxLGS@8q~?rtc4p@gIs#X7o~aZ9n4a<tkM%io4v
zyJFD<?cr}LMq<&}p$IL8e5c|!8jCxMeRM$XQVh0$bSpM}f*$rLj?(LNS5XiM^}UL6
z4$%4(dnsOdPf>Os3i}nVOq2!`^XN!As2C&6A%)x*V==5~J`a}rid~nXZ$#m94Q-B5
z#ak3`e4zM-#%oOR5yhMzDm1gvIIi$iLDPg{SuONVD(1{Y*B&Xhd;&71D7IqocPZs2
zh`T5YYGC$mC5t={dz7nbe%-4K=!e36$^i;y>{p(=1ic58IteOWmFe_u9dsz;C}-GB
zxvLGD+?Br{Lam2V-H%F7<y0lm4k@>-gE8L9k!XPWC=2P+3BJm!pQF-GxrNU4{>tgJ
zGdQB${1>nTlyy^(3sk=73lgN<MuEa$<uB7<VTkgdSlAn?oJW~CVM>RNVnE?aEp0p_
zlpjzcN2Jo3vW}vZ-&2%0TG>f?1~JOAHmHbIN)w<kP8qWjZ3)Wz5wPi~avB{y5|xip
z&VG`zf-c}BEC2SyP^K#VC^mjfIsF*arzwA-!}<wjc@Rn&%C{YugPk&!4*Eq;DtGQh
zDNDJ}6ADi$Z~22KTgj*IG2|!@Y5{s$`8nmu<|?If2;?c>a{*_*@+#$Hol$<Y2sRZc
zTRw%tLgg5(2WOQh>C#G(a$*7Gik0CEkP>A|5;}NJsh;CNW2tgy2vn3Qm(j9+UTLM1
zSGjWa1+-mIE}&4|MWrnk##AWZ|L=1U%7ax<QK>xS54}~&rF5#QRyNc5phmfO00Onj
zFKEAAr#wTx`pe3OMKH8p$)vobMx}~eELWBBj3+kY1yW8aVCi+`FIQ08q+Cx=X|pn%
z+-x_Lt7t-RQJ$h{_NH<@?N3^jiFB{*mNL2)EbU69VzpWyTi`fQfyRDi<sV=jP|hrX
zHG|4vx=}WyT$BKbVP!wL!tN^-wO|=huA*0FRH>&aaZH)zPEWq_HWw)4$`9%C$%OI)
z`ds6r^2IV#K2pwp4FXfjRg~%JqDrS@&2AO`AqS7VYQ#Z@rTwa;JJ57MwdFpDt7-)U
zqi|5ww-7vTs;`wG?y9BDFwH}yEQK+is?e(dJ)|0;Q9rDjqAv@0tNQ+hdLLE%HCXSf
z`mhbePqmxwF#D@44S+tPI(G^v0jf9OMJY(teU8#^f>mGSKt4oO+XqddDmNqS4pS|f
zfQks!j8u$Qq)L1pc1No|qCHoP>enz-#;O+Fgo*@JgB;>VRg1|Rlc<uBBjSYWwLln?
zp(^_va+#`s-bR;Bs*-3?%u@ANLG3A(bO)t_omM3sfHk?QTqSDrR91Sr^HoKgz<NgY
zIz^2NR1PaD3srO2P<U1)u%WF;bz%T2idC=Cw!K94*bwxdQzg!ZK$$9fJ_OFIyk~*4
zTy?1lr3)%qHWXb{C1ioKQe}Ob{*$Rn)jxp7YSl<7Osr9vz64sW>ZfrC)~QtFIK8aO
zrO-&d>M#?6S5yw#?KG&yqEXqXn$`r)tEw5b7=&x828u~uR~6B&qe+$91q+*1lADmb
zq1v?`q($XJF6^7CibS+IT2+_60@^Lro}<vzrn1qtuwC^O1pscV%Jab5p~{?wK6R?%
z*8uyD>R(E%=u-VgZQZJU^dXZT)e@Q_?y4rPpf9~D2}QU1R68e8c~7Oh0Mf5Y;R16&
z<<$+8K~)>M-i911U-FI&t9Hf$?Y>I*I9Nwi8;j96s#>oF+5^?Tcfm5IGQ9}FhpO?N
zU>R3^{tHx0sJ?vxW>2cbVPJWrDxwp?l<GLeQg*3-$wAw0bpyF*_NhMzhxmTAm44*|
z>Oya@xT+mH$)R^p{TUrD-PG-`qtRVmd<7C7>LFT>Jk|d+!I(qpi+f<qVfB`iP~oLM
zM;Wf(>X3H8_^2~zJ@Hk)`yomp>eUyZH&i{l2hd?^;}2*HSMN?oWrTX$X+TG+SD0W-
zlv?-SPZ_N~PM0xa)I;={gIM*_PaznmUQSz?c=c&|{S(x~%OHPLokqD6iRx@Q1d`Nk
z{Xk1rbI4biqV_9ATdI0002Uro$Gn45n)*6@%k;Q<BVCY8SO1T;Y$wzun^BpeUU`h(
zzf3iAA51){UQZKbmb%#qR-97*><5yq{(2qIa@1GpuFh%o-^7`#-n19kdFp)HIp(Xo
zXtqA1wml1$0(Ho*Acg8d`d!behbRN9NG+t$NU_>PM}ZRcW)oP>siXaAD^sfO+yK_|
zYSz;j;BqyOJX06ci@%26i|XfBK%zp;Cxb7ke_V$_s8r9SWwc5?PP2Tq`Vq}cHEP9=
zAhqf|ir>|#2k6q-Wp(|xu(v@y?H#l=syiv2@~ZkrnkcTRgOK>_aJsIJi3CrRdiNNt
zXjV6U1i>3>J~=yD)MIq3=%)Gw?1h|K)fqE^eM`NIeBW*AXOBRxU43*BO1IU$ZUF62
zhtu(<Q|;ynlsoEQ_JgHMJ$nw!?pBA#0IWwH`4!sks^^uV($TBlNe<UO^#mO-?x}q#
zq}s1uVnt~{ZKSNhL3I>4Acxdz9>R)YwTA(1_tm>LW1L3R5gd?Fwb~5M2kI-dOB+)!
zAlJo1wHq5`T)jyOg%fHH-G!V~dv^ilkvffXey1GjuvRqg(%9dGZF@AUvLUfoBgg>E
zKFyz$mEx*dNsiuw8d)whxoHsA!dszfWrG~jL{I?xu%>%6SiCgwXyL8UT>c2g_-Ibi
zk<C~0rv)WH&311Pf6YRARgP%lXc-I8IR09NVxVTrw_pvT;~&-ojWrW6A(}c7N}-xY
z%D4{G$Z7W;uDMQry$H=fCn_T~%}Y^=(rD;|cF`JV^0>rkekem*tfqK6NSvmDqL=ZS
z59`pS1WgC|NRDdG(w)L&%{z`CU`C2&2YIbiHGG=&j%yCkGncN3q#fW1%?|PnWoQ=H
zpp>ae+YZo^8ozf@nWY(?3qwz7;uoMYTl01rDswcQ`vG=ZQ$j9;T#auXF!MA!zCtNq
z)2;zIqd7pAiV8GqJscSILd^h08qaE;rAt0Vny0z|Q>=;V0(Ob!>lB!OP9y3>Td9Vd
zg~~Eb`a&3UUh~8o_$kXZ8@B=Ng62BS(ib&r_Mx&uGexufCCz0@MXJ>Nc?NoGG%PxD
z)oR|PkY=5xzl%P{d0BH|HstFy1+Sy=ie`odDz0j_7or!}G<o#(@9Uah={8fB#w7)y
z-I{7K)c0r{6cxX#vCwkXs~J26^?jQ7OX$))%?jFv_G{|tfIXo3wgsg@%_NyUq=}~t
zonegwK0Algea#0UP%)z6Q{v00=A|nz|AA((4?JU<NIDli)W|6ZcU&WG#>h-)o}q<c
zQe(@6+%9dkFF0MaQ6<p3TRV@E%Jyg<rJ!=J_Rk2AecF*%A+TSY<^q-jS_66fUA0Td
zqvklMed>J_-L#&RL+`FVM^PUSZTd85^3;}5)aQ^kn`XVk+EzM!duhL>Ta(_}4$64(
z(Y{L$i?8-8`h>Edb`G6n{Iw73Q97bcq!%YZ8?q2Af!d7}n+VeSlUFlXyMp{wAr5VY
z3^1YE)&vy8v~L!n6t49=48aJkgyzXe?YnY-MrosHlNYVE(E}Bu4f+A4SnZ|X(X}}3
z8G3)>wS0GoCurU1L#0QxGw9HgsGa!?Sdz3SXP_-v+ddQGDOxdY$y2qCWb(=!)4J01
zk)}P_19Duu?lDxRYvBsR3!wetS&$6vH1hdnYA^9%=t*r7ohGxiJGKDrly<Te0@+$;
zavkPq4L5;(TI+raBv<=0UFXTu?tBL*`Pw-oenx8uhd_aLmg5{G3bozGP<vLJxdxy`
zTIOFM#oBr8ASGJ%68ui*w58GLVW~FtEr6D3SJ6y<Ub~PodCRrNCSYICe)uW`E^7G{
z-mTCYXt*zFpZo;stF?YvDAi~?C{9zW?dbqmop!+t2P7_Q4^qUUUR&`oI&(!kgR%x2
zw3jo{-$w1z$q>A%#lLsrb<obCaQby^c?~L?v>mipYu1M9G0r!%g)FqSYSR`#?v|GI
z3|QK<DRThUu63oL;BD<IbRzH2_LD!pOS@(@T}SWM&SyZrN4wMyR`hA-(=qa%_BJ_n
z`nB6AlXys*HVV*TZ8IGJ?`xl;xqCz#a}V~8YSj$1J<$3uL}^UB%nR5LwG7HS8rQyj
z2`CfV?n|hg)Gl2Gn;vQJ*Fj)P%UMkC-!9!NKR~aG?vo#2+isl``40BzeCWR9UY%Tq
zALf8=4fz^fbtl>&cu@Bi?O{B0ZG*7FQ}-Yem4|dk`4B&>%cdj(FWuwh!S~kj9z&at
zE~^1%`|3V;4eI@LSC+yUf89GGh&ztxS}AKcKvzc3PM|Ju6&izd2KtUturA~tN+G(>
z-i1w}x)sx*B24$jDhNdC;v`TJrL&RSDq0ulf{w=N&eD?~uiNeflAyD`fwrT%qWzFd
z)P1lBr6k?gl*F2>D|`b2DGuG4-(X^@E`A^SbWB(I0F7xnGtF1Wb#0X3kgi)mn}`!S
zF`Z;Gbm!NCGgIgDB2=8zIcSHSrQ3NF7Ut;wrFisd-7_MH=jwv#{8psPp>M1d>r%)e
zP@;Ri09KsSy}uNdr8>uZ6uT<ZEop?{d0p|pP*|>;xdMV0blWMV_M(nQ;i(GU%I6?)
zN%vhWSSodE{|2ej+5MrZS~o)1JZp5J6~M054W0(6(>YOE;}u;GWdb+o{=5N{MqO(?
z+OFziXr;WSb9LN<-s?IYWob3(M&CtkvyP>O;0>KR0_t0JueX8R(k+U@AhhXh3Ft+;
zZaQtDZtFgx09uFc3Z>X|>h@Fk<Bm>Qf>M`mWEnW`>hApxxnA8C3HsTmdo2@&-qXD|
z3`PCAir4A=8_;!8mdK#)@m;WONY_OfKEt|Mw1FJe#gYT%flf<d%Q2ma=CX&nk16$d
zT$e&``h>1N2jY{uzbLcrk#1QuSf+HBcR<B%eRenG_ULaip=hsuQ4a>;fPVWyw7KeI
z-l6l~L48;Q&^+|>9)pRV`cEkec}V|>8g_f@S0<w5qqjW)319vDwXo@kKId7q1?cf{
z3_P;>=gG?#qVJ<qPN?2}0Z_v9c?Y2|RzI`@0&)8MexStbxfLiS=+Eu}%TYb^IDHN`
zQJ*>jv?RUG11ggBS1J81MgLDJDpU0WI_MtL=aIiDP4D*=SdQyg2*HxBucvH@6Z+}n
zP@kdy^#;^u>Z8fed{Q6$738w?Npxm8rBD783bXZZQR-8UzL)$Nr}cfmK){i!PudI6
zJpJn*qnNMXumTci^g$jlzd(PMNTI%Y1tiYuE5b3r#d=8!N+tRovtZLX{f_ytqEw%~
z5;m3T>yiL=UjH}6e#`YY{egKwzvfMh`bGWW2nbZ@UC6z6NpFfkTctzq)eNJm^l_U|
zTdgl~19pvmffDky`l)@8sM9~51uHJ=zuW`$4f^K>QQ4^9NG`Ff`T%d(+oaE=TWZbv
zm&qY_LqDH5TlIX}S>MtZQtD!x-idCTwCm@6gwk#Ok`$nH=pA!D!O(Q+OV@&Q>&NMw
z-lMM~7eb$YI=P?j=@-$pfPQ_$PP7f^^C>@RP#?YqZA1F<6jYArU5-OwRA2r-kOz8s
zImozvlyX}p^vk{k=cGRWaoD@dP)uENF`QzdZMR{<aSoR5Gq7Gq?S4bo_rN}2=z4^b
zt6@6Lng<QP#(~Anz$C|-x1nYZjPWrnBfpQYf!_)iKf@a{V1>WIg&yl8hA7(i1{n6N
z#Q+Byq?DQ(WSH?3O2LL&@&tq!#$SOkp@xOI4iv)-&yo{5+;HqO2u2uoyott0!;5Md
z6J<yY0*N+c-voAyAvGCov4$CR<cc#ar}U_J!*VH9BpB}8MB7orT5=>N8p_^6TasZk
z4tkRfk%Lf_VtAWA$C+w4H4}=C8H6?TIixg0$!cI9H~5o7KHbnv3Ew9SPGnk!;eGNs
zW*TJlbe=SnFNQH$hMD~+oieED{!zBU<Oj4ILjXBIP8)WvgB7`kmONDE8Fp7eJl}AP
ze6nW@><__GV31N;W1(R-T;L9;vxcZ&QCno_psp1gf`d^iF|c-`bk3l-0!^g`m%}KP
z8CbLjIdABsm}t2ny8@LL45>e%@}gm`1V37Z;g2MkeaTQjar8>VoFG_HWvHPft7=2^
z5tQl-b_%UrHoQagg`?ikcMdR(22(g{uNpeJAlD2B+hKRJ;pc5I=7u447X(`je98{F
zWmra^b7?bV{R+M9h6eK4cN%WfFLK8aNr8thL)k`Pb{qZ*1xt@%3C+uQ4X@Ly-D_Zw
zN373qi%yaE9ELwA^4@QFf&ys+hVW1DQw$o6lua{i@L7mn+&4%mIyYiCFM-}sLx~Xb
z4-9`$meiP`fpUf)8fqz@W85%E4v-1MJS!?E4N^)Leq^Zk1@x35dIS2q%ed(Z+FXpG
z!>HVCbj+l6VUO`n1;}2bx)Yt*XDswa<9?&yN1z=r2GX&})%e>?lnxpvX<l|S9{3yB
z?nbXBfO;4o8lc|O$bAvyknu$YOgn6hJ_|W7<4Zfi>1~XQLZy!}kc*P9@!OBU>1TY>
zu?V&PMk`(ZI%2evS2VyFLqV@V<JJNg6J-4IX|MzvGv0%RA;uGQZ86k%fRYKqj7w;r
zA8wpA7p6rR`K92DG^TBU-Y8?o0klOM=LmrrV`NiCU#xNXHlX8-t5|@JH@;j&4|#&I
zmux#~+)oo#qLE2%#Ux`7ovxCN^Y#Nf#W?8zNi}Zm2KF%{>j%K38Rt8J^SCi_I@;2W
zddhn{VT}3-U>Qc~TtH_UA3XtkPZ}Q!hA~;jQ?tQx$~Z6+ziYPfVil!><rshb4UMOb
zA5{P**Z6A&K=X{dzQI7{8=WYKdd9eS1I#ZlR+8tV&^YljdVkh<+Y53<#xBZgDK?H#
zIHAP2i0007#-OKBDm8NKP+w-8^BKg?8~>K0RBn8HJp?WoR~#V!%SGcd^6OU^$4*1=
zlJR?5&MJ*%0l=;@x~+nyS|cYBm379@Z&12y{PiA6^+qM7`Cc)uoei`G<FXY{*l2V(
zqwT8kOG*~LX4FX_aNW3)qOMKGib(Xn+1SlR>4tILOAv6h7?+)aQ8$gtEP!b>enz{y
zTgDe&15BGS@@L4m8&@1h+il|jEx#Sc#KREmG!E=S>5g&UKM?3Lu3ij<-Npl(p`yp=
z;{&<7#(6Q&)N4Gk0W5vSl^n3#Grmp{&VFM@95@FY#yT}>2aOfap)*6q8?@jK8`siw
zci+f<1DZyR&qsk})R_Dn+8!8d=|nMRT-gfwhsM~$;2bwr(^@fMlqEpnq;WGvC?6S9
z=;G0oaScK5GUez{>0&y<LC^M@gcLp5XL3mBqX+v<k`a&tCU?3f>S`(_g$GTS|HUKV
zX8LC<40bntPVNv7leP$zo~C>BHXky@Zv@(5Q|pUR;bm&;LYud#nx1tZ(>f(A^flFy
zhse(~_iqfdzv<g6=+Y6B3q`&IOwT#^;0ZL%cn5t7GM(836~QLPV_*$2Rnf8^YHB9G
zPnfBf1rlzO+aM5OD#(V4NYh#c6h@gOl${lAY9#R(Q`C<zE!H%n3#B*{n{EKao4$G$
zRwS6*=o<S`)9c@(GSO6Um;5hDrnlF_nq*TJeODpHlur*^s%Z&LrN>NzbmmDjeX<$G
z95?yrgC)b1P8+#Q)6e9CK56n9MJda)pUggGnzIKMW}9Z@0wu>ZJQo6|O>qlQ$~6fi
z0G4Osav_j!GQCdw&oib2bXYoTI#2Idk!g4aK#NUI<jpBHjSrzzX6nub%X!oM1sLax
zraxbR*%hWc<N>^7x<E0UYEv)yuxd<wYf!2+89xWPX1eN*%Il`-6eVsl-8~DiW>d>B
z<ZhTM-=pgYEv5r>mF%YJU&?xKHEB1YbjviKc7<)GeRKwIH+@Ib-EGrhN<{83eL>kn
zou*?qz;efQm69L2Om=cBcAFktLR*jN<e$)c*A#UV;=QH`ik|eDUYdi-d#2&%A=ht8
z3I?WQ!1NI%at)ex+<{R;rXz0vX4tf#7d-b(F4I6pOhr1tjG8vl7I)lKL$myZX=WSR
zCQW~7Vecc8l(G+|Ot01eWtaJwH~Q;he*Oa5cALE-VAFo{H?$lbFt==moU1uK5-bND
z=4bAJx|!GS25~pbABTDm^Lje*d78I~pzyGH|5gw$^Fq2??``H3;rI11S6u*%uUTh=
zoS%7w4&VOfgK^Mw#C)t2ECJ@6)o2SePtar^Z0?W%I>hW*3JXKc@6+wWFtbBG2&2Ny
zizr<;(mb8KZBgb(idjdSpQR&ata(`ux)x_{rx0bl`H3YUN6oim0F!9G>57p_G9M)8
zak9BO5CSRYYrQC?nf=~I>A2Zx6qxDe4BD=rFyE$#Y=-$c%F@p?+Z^<+oHPqlVOy5j
zYY42T%xeZvI&J=J8cfSIU+e&Dp4m+Iyz<RLF31`4lgCh5VE&O#-G$~HCOFTUIdp6-
zGQS7Ex>K?FV<p;3%uf!ZFXznXI1nf`cZi{(%-sAF+RmGsZj)D~+<c6}Y8TA8)QgMe
z8aCuB&3XzfRhgYAd!gFwN;yn5=D&7AzSg{)oFjGSEb{VQHXkcNWxd(U1o128m78E;
zgLy0M5gW}5RN%a7KAwxV>*l@R;74mRzuyAVY`%1aQVDOElU@Z(i@7unJU7jo9-!1}
zzD~RTTjrc@nBQg&^@D}&W(8fex^14CKxKzHkS^tRn!iYd+#T~jZ-aE1V**gwZLXl>
za*sLhBXHg||3k@Pz2^5RDA;H2O@dAL%t@yy{x@jeIfUYnnL!!7!{*fqP(Ny}q*MC?
z^N~LEV$8htGmwYoiE5B>^E>ohO_<&Ogxr+*4lO{tEW3X~n~P=T;~3FBmaX5Ra<An%
z+F0zfbdxdrEf49jI$)6tQF67!QYx+EphYts)Xj4LS4g;9f@!hvu*{_xtfz(l8bG})
z#pImyw!}Pz-@wPxZi9fYrQ}&u`dRjo2hZOU>jq<vST0e{ae(D#dgcNxwX|&xviv}E
zNwDQrnx#W52gyGjYDw#WF<}l%6Wx;zw|F~4KEhHx6FiZYk#`^wWvQKlifGHr9P}y1
zlKwGBf@O@dQ;u35P%2`g<tqeHosukFzEGHK$-a!ADaCS(To$R8%xY8~vmByebDHH1
zy7qhAaz76&=@yr3fIeYyEWZV`49l~0Zq2l8eh6~XQuZut%Ce+TMD~<rGse^@+wvX7
zHgYUxiprg~jCnvsuBDi^S9zA!CRmYgIZr!_GnVEw$Q4+2E(0mF%qoV$vz96gdRAmH
zz6s7^%l}?SWr=0fp~pC%vnVbBrqr^HvQx?|NwjS^Z&|P$3d=1^--j_5EXo-)^;_Oo
zfV0B#QZG0!Srqk9QEAy4474iC7ZmENwk)Kjy~dKg9DS*^d`2OaI*X+e0+%hTX}YPm
zlr4iXS1jM|p#5iqrR*|Dqs96v<gZ#*Q^xf*%Nnxuy5$*qSDGv~nrNCWdUDU*u(b97
zt;KT63)nX;Yo`OW)#6MEO1CWUKLwUHO9_1?p~GVHhg_#+)yrtRWBHsixVkLsjF9WL
zlrN^wA@x{h(yw;c^37Z5Z?7ehq8WXb88^_;dzSR?p{d`(aYdg7EK6whAGBmquGf%d
zg5HW@OECpHM=i$}f%Ac7`6$4~EFbp5`iGVkq<-AOrnAz7CHgGHCoRk)Fy@ivc|-~w
zPE(ec4`9?TYaRW}F4jB&?A~pCHw`>{tWBvX?X?O{L-2t0x%W}&YJIE_0tc<@slRU4
z|IzWr-5Nxfl02-R&<7wqt$S#*bjW&q6H14zqSZk0vhMvAHhEhQ*P_kG`UE|>4qxO0
zgU8Pr@?V~Wbq?+Gk68bC8!7^<-#NpkK&$f<<b$j!pQ69P*677x39;^_?`4Eq&9p}h
zvufYNsD)c4b6``HwLKMW(N+ZqaxvDG1Qu(3{2Ex|tl86m5^r^mf)xo4>+M9)qt*-b
z{v}#tmVqb9I<Emd$yOy@YD%%HXckGeI#D#@n01W21jns6>2#ECy%CPm3F{xUyUVaX
z`Wuy*)>kPB_M~;`UbJOdi>`v4vX(f*rfjR`1)$_uU2ems(^kh785HJQ57TMojP+JO
zY749%9fRFP)^mG6imf8@WtCX}wxgrxtVbrnS!yky?S7f{`#iLrw?;>Rlv@LTh1nOZ
z-4t29X#Ji7Sryg~=ArG9)%`1gRa%eIGhSu&B%eXG)yGi?i5hD=<*n9QJM2(jXPvbL
z*q5zh${DG*I$lHD73+d%pfy-kbaANBI)5eFu3F>PVt}q$13rL?>(*}==u4CJd%E$^
zZ1tN4a>M!$ANICbZ|{fRo7PlH*=n_VQh@W8mA8?yyxOe7K{U2o7y5$SwtnOa^_^Ck
z0fKj|b7>CkvN|n=V7Ikv2m(FUtvkSS*D4%9Wv_MKbyW6Q_x%Oy?^$2@1C{;O=V?bW
zV9omy-5#_?Qhx7{)teG3hOOyD?pqg{DgHiUJ!wT}My-G30`!6P`4`crF>5n9svcTD
zrc|hLt9=CW6IR1sR8CsgpMs`G);o`YJ!Q=>!_Zx}z;sl)*bY$~e7CKQevv&kKT1d0
zYctZWf1hpj5QcKU?eXR4=K<R>9;MQ|+Fq;$=t0|&cu2U}{N{qk-L{CflODEdv?=wp
z1(T2DknPuEki)ip^gwypuB-y_whgy~#mDAL{$5{OAp<OawmHSX^tU}hPL(6JJ9|+X
zU=wFRAkem|9?(IyQ9t|!j$qp&avO)(?v}#RP}^&?8iv_w$%PkgbE5E8ge`d=SR-vS
zUx$2@?MWY)A8kvD0(Ok;o)j#xHp4$4aklA{$PsUAx&zJxn<g2i9knH@VN9ZJilR12
zws`splWph7jhW)GHPKR;YAgQ{g2!y)zd_P$=ca&m+!o=DwsadS1HaD+TbdYc8Mbd8
z0Xx%nf_7P_Y_n-G&$c;Ha#@b8{sgd3+cL``kZWtD8%KGzj(5?QeB1CK`gz7yNhxXt
zHd{Ny3vCV~IR?(!-VA{?MYh^cP%5@9qOE3$Z4>Qg&)HIIz*=hiFck7-wg>BhecsmM
zic-0)j6(JoY%2!AdC^w19fMb4OUePcWc!-Vq?NWq<jbwHt)BtC)wcK6qOHcZf_|-9
z+f7Fq6xP`aQ=sCq&4U(_dRsmvKU}eWO4(fvHhVi1HrhrjA#v5#O)u^>TV5JEdfgVj
z5CTm${}_~-ZM(^Fa>Mrb9gr4VkQx@=w0(L5ZLPM)=-Z&TY!6~#Q=6@ZuBo)!5<F@B
zyKM`kvs#DEg-!;YHenPR@7RXqD0SKFC&AKft1bddk8NcTVD8$QN>S>yWrRUfpKZw&
z4E{Y^Ml<Z~xA{7uqXRY*<w_6Q&b@@vkWERu*kM}^r8nKT?V(WWh%IP@{*GbP7AHiX
z9@xb5z%yp+q8z4&HY@$B=D02G5!6rE){vuj(iZduR6MdhNz>JoEouP9?6U7phZQb%
zy%aX>w%7lQwmtSva@+2;KcHRg0lUjtu(;a!D?tw0YxS_#&7PY^{ug)q0ufB~u<w5f
zwTJDO=>ndYeVnFCZ~L4d(dK7Ap@L2RcF)fMdc^+fbyNn}|DZb^fp$eXDue7+4oI*)
zcRu<OV!!!0j0v@;zX=j%e|{32;dZ4vSR(9eXpxAv&!l+2BgVeoA3U-4q(-QSvoFg)
zDc(Lzc@7EoA@bcN*?Vcjn{3aauac$MGe1FFn*E6>R35i)=|Cyn{+$c3GwlHnA%4=%
z{t94O_S!<QoU*HFznyJwzKO~l`@HGkJZ*nE1(mrDdm`m!<=G?2t&wl<IEuzI_D(Sd
zp}_u-f=)&D78~>y+k5LUdL{OlB@igHzrX-FZ$I7$Qf{w`Lfb|A>iYn#uzwc}y_f8X
z4<TM@f4mW3RrWn>R94%U`$M3{UgCpNt=;hn9Tn^BK6VV-WxLjn+Isu`e_=&~{fZtx
zUZee&55RKO{?cziyJlap38m|HDJ7CL+0TwauGt=S85Z8KzeNHq_8-<^5N_J9&j(AJ
zeaA+qZ?|uw)bQK(&;nT4VOP)-*lDkHP-?;*dxi=;-S+1w4AEnMa2E1+?JXP8r(S!`
zb5Pi4Z=-~$d-mi=nAUG^qZ=Lr_HUgaH)x+r&()B<`WlQGwl7LU>At<=Pq2*GpC+H(
zsD0fclpffRp9I)L`?qvz9=AXDv;$^L*yCxsoV54Fq4tse<j1I-vKu*&*yYTl^h6hD
zk8o7(cK+!v$nSBkqCwp2JWSikea@@i0?U49y%)p}IKM|hOjl=ZB2064u4sdL59g04
ztIN|_`=6i6`Adp;dprLeM*B}6XC58NeVt#WOdCJvAPQglJ74_+r9kIXkHNGcXXY;`
z1v`KG0<c4zuZ+XAQ0LBMw1qi4R$*kqofo-*CBpfx4SFM;ZIq4@<?KYMe9_KJZbB}`
z`H~PM*4gwn`V!}SdKX<~iFf|>IiMvtKb4Qhqt3bK(U|Cb=l@vx4zQ@M=WX{c3+z%B
z_Lkjc0c$i-6E#L->@g;4?6D@s5))%IO}3~c#-;ZTB7z74N>M>NN>gkgASf!JAc7#+
zuwn!8d*}E6o+nSnGiT<VIp^NJ_netImlB{Iby`80?_*A$#hCSUr+0238BSmB1n6<6
z%Z?zKPC+7A%5nPF4O5cq^ivy9@|>omz^4;VztC&&q|*g4NTJhO0sa;_jr|aq#ZHTV
zfdylUQ!l-8N}Yz&x7AKLeLzpd(@wLS;6<5JLo)i#I5`xeb=GMY3;lCWMtA6+cWR@j
z?FFYdv{x#3>ZK23RXANphx$dQl%FxAN+-b<cB`BgECzJ7lV%6NE;$YS8wxc}J|h5D
zYjir-4bjU^L9`*d;^cc9tvaW0+S6Wl3Zu1nz0-?+45q;;oZ@ngPGS4Oyy0XT4#}HN
zA0LB>CMRw@6q=p3-Uhklbl@5$p~WeKru(+jvRW`(orcrowK=_Rh29+}&-?JH-O2b-
z7SKAJX41ptuG67u5bbpO=RR6pPAycMeb3429)@<`DL(|{fm1*)hW*fKyczT#IW-?Z
ztJ`Ts0VE$gU8EcFiPKejFg|n2vO(W-r)nxrdEvC>C#d&0Eu>oXmrndOIP=P>$T$G>
zwUfm(XuNUqrQcYu(^^-MJ|}lt2flOq$Q~N~P8O7JdGB=B9F|<P3EzR~s@?G+^xU;6
z^f2+zjya7!Pwn!_(DTxoQZ&<B>r7c6KW$DXT=Umj_(C#3dyQ6nf!c;7BS3?+uiP*R
z!P@N-h=yo)OCTDm&6<zCFs(C%$-}iH!l4nNEgS|Dd$j+RLNZc2KNOOCwPz`SAEn(%
zwTJt(?sQ5nT6?Ar!;aBD{R|5GwVm{Uiq+~@<BA;6Hs1h=(>i5S{Y$*oD+*2>)SA$D
z6%w?4A3#4*TTT&|B<(^9s2|d1(9`R%_NP+7Bx^SngQRH7<j_mi&iVu<(zM&I!oy=)
zhsj{3Yk%7h*D|!d99qY<87I)n)J_-!kt}Tz6`bX2T~Kvkl;mk!Xz`M-O{zg>fp+(H
zm_MOaSHqc;+R=1)x==fq_AW)*uNQ(@tSz9Ye2KQ1)=Z^ZW*eBNw7=BD!!oTURSlid
z?xV2pS?%^yaP*v3L`4(lwZ3$s?1FY%9!R;icM&GRSfR}v23n~dT?$XDw9C67TCM$z
z0#%o^74(^r8tpSW8&#_<qQP9&c3lATinePeMC!C16tKCf6%1%y)3Rw8#C2`>0}P^G
zYos(ngZ6s~rm|7{`&`V^4eeqn)Ng8SsK~0xsQr`<Ff?md(eLP%*1j8xE!v}f81HRu
z5ygvJwfCqps7<R1f@^oQJE=tUu68#)$vd@I=_4Fn+D&7Dc3(SxB3ci$_`%^fqMb$G
zK6s=(>;dR*?L)d~kF`-7Veg6dbsM0cYK^mQ0Q8ym>i3X&uKkiu1-{U(S`Pglt-=N5
zrPhSrQLnY-rcivN-9vBTx7yO1(CgJMa7JIB_RvbG_iO*G2k3ikAyxLd=%&*u*j2}U
z57*puC+YF(p-b$Bx~I;J7Rp|_J4V_|d+VxsSn|<HX}{~M`;5Mh;-^~?jh4Ue0R@u+
zbmrM;1?tw(1O@3neh+4_?k1%_LUf<6L0_ou7y7}5>8xi!BwY6`g|H)Z|NRBG_vnfa
zgGB0_X$=ys+fAP}iP1%;Q2t@RuHYmF6RR_)BK8Bi{&~=k(=Bg>e!Ol71wan!%;>?I
zpj)kl!9?Bja~RVh-8kAx9M(BSLo!)6kjm~-bP1~<nX21EJL5E6Rweq5=%O!SfJb%v
zM+5AbuG0+a>AJs)ss8i0?l-DB%G3=g2FcQ?Mq?7Qbv!*qa&*lLfR?MXEJ9zNE`@Ro
z`8orARiZ#=O*K;|bRUfb_DS6uZ#Yw|`;uxHN_3MNKuUGvsBHC=u93DUr*+@vK(9=v
zrtRYy-F*Y)AI|DV(gXdRu8|gy=XEaM!|ny$GaV+OTsLYaS`|7KozS|do0bQWN?qw@
z_*A7cp`}x`ZqN&~F6ms~!I>J}cv>LT>ITz}`m!#Tb~#sc+S^dC(_Q)pl2>&j76JO2
zZiokn@w%>_whQ&T7qmiX&`k=5Orx%t($hC|&I{n_P2Ipx0NSKeQGt51u8MBm+q&KR
z(buYTcLPkDZanSJ@96p-V%FPrB}&-s&~<Oac<<`Ij>J{&)crCGl3lujQ&7LB>!T`*
z`$nA$R^gHdy76>>Jk%YcdgMnsYl`i3>*|_89_!vv@zE2V2i2WE)qPKAPM-k{&OF!U
zQ0VW4E;<W(J-SPs0DY;G4S~T|IvI`Swa$Y!jBj++>tOz^E};XMy}EWP4d~Mu8>sx|
zo$lfWboT42scQbc?ni52yXZYf0>)K8RtXI^z3<0>ao6wo9ZV0s#{@`v>c`S{%uDZ6
zi<Yl`7G?AN^eTEQ`RhOV8O#9vH7aik)bBbE$sm30Rghr)KOBY>qE9uRgZrWSK6+z@
z>2Ki!A(C+YKprEE(9f&~bB}&IrOqPt<80vJUj3pun64=OmepYH(+~9piPp<U!BUKV
zwHrY9>!$^R#Omb>z&xO@=|U?`9~}a{c>Q0LwmhhxqlKdhdf$5b{Uz$XsPZyN-*E$T
zaY&zJiPmBL1B!zr>qk;uM~Xg#9@?pTmsr3Y(^ve1R=VDNH()aKp0qDHu5Ye}WTw88
zmLggDuWR9Nw*D5aYjX4srZAMN&+bGkU%z8FEEMQpcA%<Mazg)f3lvZ4k9`4dq2BT(
zu#5EPsid!1Z}Tk-mgse4uv9-d4dj%5CDjC+)=#A>k23v+!w@;6Urhn^v-*e)=)0gV
zd<SN^e(giFD)d#WV7E#yqMu5&eg>^nFX<2A<~B+$>m#V<_=<ka5@^)vuLlF>x_-}A
zXw>Un$b5tTVInjd^~YL3Zs-kl7~xHQO&>&B^kXRtd0XGS1M}RfpWXn{rq7><zB~Gt
zbVb_r*0lKV(2x8OdUy3>I$*C;pGk`yW0#&A1gGxl+bFYoUmt*^q~w7<p%63sP=Dqj
zL?7uBYe2g7Z^K~evHk@uBA)1b=)+h~^}$r%^i02i7F5sm7wMzAFZACm16Yq<?+?9~
zdhgc&d!^q=d+68txPc&V^qoAe$Xla6mx?8O^;c=3-lrcx1*h-yhGsDP^}VzYd#?}v
z5iJ)(1my@^4b2_!+s$yF@?q|VkyN|nVK|u&b#KFU3Viw)+SkCmui^9cu<K`FL*SFY
z!HW*e2N+x|KmrZbwEPV+827zFGuY5*g`tHQc2d+i)L=RvieZLN>3mDL;ct2=Mi_2W
zFldjVpH>}_2H9%p?=?)PV!9|pDy{nW8H8T=6m2*{@#z?YlNKWT4GR~;-&n)#%ji2`
z2&epAoS~blgyRh{#x}?tH2m`vFbM{Sa+pXoWGn|sGTfz<`60u6%4Z)o%xl0Xk_~3#
zp`T{Z>)^!^L+N0^95q~#LgAQUo*!E2hGx3gGYpR@E0<|lNvFfJ3;~Wn$u_8~F_s*|
zh7*{sT*HlLwErtGNIn8NVR-QkoH=Qzd;pC?!x0;_iVT;21!%EhGQEXM439aqN)4Mt
zXq_?)@B=w(c=*3Km0?yRTIUU8=(}kb4BoUdFE?De4TTEB3@XRGX!yARB9#Vn4V<Ym
zOsb^yXSHG1ZfMjPex`FOwT2<2c-fHkJv_Z)D4=CsogwNoIDF0Uh|<H?4Y72xtKJah
z2DAo)jJ7_F1||}%8-^d{P`GIb{tc4NhI6#pxn=ODly{3kHyN$lhGq1lYBda;MxUc@
zGwe&mT;4G}y9}o~40(x|=eveMW+0u0=eNP^GIUJFDDD}8L}=YNc(G7;V2GzB>KlVE
zP2M|0NFhYt8<Lzr+_rx=6oc^GzVHbYe6~;1!bAV<GJ13eZQnwLeev5j-@=p_k8HQ>
z2HNrMt`wol*`C-4nS$+2tH3PWE^)>{OSVsJg8QepdzJ$2-1c_bLsV|xw+Apcw=dj<
zzI)qWUV}5wx7Sg%MelaE7x2k_$0^#Adhci`LSOKX;}tNtZ-=NH<lv5}3aF<VckE9>
zGjqp>rZ8W)qnt{_&+hnU49u7BnD8ZJYIpdJN9)>-d0Qb8yfa`JOvLOw9g7J{+&Ow4
zurqgl>k4Mx&I&hxmFyh#4^YZ?zNWZ%?asl&p?72F+F*#Z?`)&G{H~pM=%w~_r!n?l
zn0UQ&z!c0^-%b-t=({-=cVZI!oZZ5}40QgG!rWobA@qffJ<dldQxW4_;{p97=Xtab
zOL6{JfTg3(yb^2i4CfDg;98cmM<gV3op;gmCeQhDClvCX4V2+8aK1|6fnsMLV+ooi
z&PoZePdVpPA=YVU`vd4Kb2h#KIpfUy0kpHub7*MioKMghhx5({2ha$etruWu70%1(
zZx2*D=k9?*mGdv(fLZM<q1?hHXNLA~HO@0bG0w}*8{Wc;E6yuEMPHpW7fJc|tInl*
zxOm;UiPksu&O8Mh8k|2i2WfQvono?W&WGuB*5T}efB+JT@Jr-Pi~KrKT{7IeCi11l
zW4$PfR^W{y+Xw*O6fGPHrDoAAdx*4%?s90giga|ixkI$Y0nBcr$RQsCdL`OMF9jDS
z<Ozr`b0HWb31hxKM%irqC)CV_YeNql$G?ZQ2Efz@si!cm;c{ALjyOTVzc1F&UTv~$
z9(t$vPXYSW*OWe+HY*6d(?jOLr5QJ9(Kb`}9niikFr)a(ta_@c`D*_ID9?U#8A4zG
zvk}nW{B8&3ISqHAJogj&64$(9`uTmUd<f<FK}+!O1%G4#ZlQlKIE!NL;@^vN7Xo3)
z*dZ9y(p|I>_^yX$Zkcr@WR{Pn*wPBkcwnwP@*gJFxau3KKwQ0&9uVIz9s<@6M}C6P
znjQ*-{^-;NGixV&2>!aVeE?nG;tkG*3i>H;tfZ&^&nYGN_b)j^Aiv2p2))1B4FZ4j
zb9&_dR!XtrT}4One^1f(RF>)`@}|7Hx9DIe<$rucu~g6MD;iP{yMChC1sH+9sA?`e
z3J}FHfDIJ&Tm@pNs5%phw?+O`T>DsLp#$@YD4HIhZ$-l>R@5tcA}32srZe=sn1kct
zgEzCO0(0rZ*!#eOFB3?2rXO?dEv^6knJpBs3t-CVLyCdSxh72he#T-oyohBsp9V>0
z3U-2|FdWsHq%x885=djRegoPOCW{U|9Az@-K0n4tPXarg5hzfQ!OTj9$Z_Ui8=y0p
zzQs__Vm4BqIh#2pM$4GPd_@P7@|a2rIps5D(cl&^?*{=bS6o6tmppM071ZR5Kc<Lg
zfmmz-gD1plIy!Mu9ODkjLh%jSLluelQdXx}+|mM+5^-A{Mpi1$-2s$S;%$G!wbSCY
zV(68LPmjis&KSi-zeD4!_#djOJty9p2<-D>tI?3TAl{P$>~gW24y_8Y^HQK)6i?>h
zZ>9LjERZVk$`1irEq0`e&P(Elw8f|q_fej#R(z0(Z7z#{qQAj#Mf@NJeRbjykHNeu
zzLy0<*TlwYblC8^IEc<i)Qj2mAPwU3fxvDQe?&Rj8{)|n2fiu383)NGv6mf~&0^yc
zn7Ac=M8EeI@w5>b?``qJcvxx`FQ=QZP3%S|0q=+v13}uwYC3Y&A+DzV^Ih?_LlEf{
zD~%Q~*d^|y9o;>#jDEHE#Xkq2^MTlfUS$u(9R~D05{J!!Vz;<}Ql5{+6;!SAMBGWc
zy{F>RiI{|E;<2B@wdZ2tFEC$-uP4Lb9<i2+nO=&|Q9$LDxRr7xuf>Dt=)@cGlJ`a!
zd@Fu%5!_z!t`7j?VlvPZgK;%kMvKnlCard8Wt!CK0h(p<=~=*Jo9vzng&dPvF94Hk
zvX4HmooABy4$OQLaRuxam;}?WwZ`O=vrw-!Irs{Cmrb&2A$i4Q?=_Gnle;6R{=M1c
zo68XGFiETd+Fg^r&!KV8B#18TeUseTQ1q5;d=6|M$@~QP<SRKvbwmM@ZS-0Xlmv!=
z86>InfO@cG2mRvWB#~>Oa6)3BP0&e+-2;$9iHt6Kkz^>HcPW+}#-h(CDZwfQCQ2pa
zOyR{TNfp)1ot8L|!)GMIR80O^iJXpQoRbu$!P0qr-xT^6B(;yxS1!5p9(F4v8|V{1
z7bWkfVf435Q)$>OrkDQ!xosMA4y4soIvVP2rU&WebI0`AFc4$AY4m$&beM|j;bM>J
z897=nO`~nl`QCKTe*kqcYw3W#tC@E*yl^ucMq6HgvoIP{fLSS>!VWZBGX>5BnaO^D
zi4e0LpJFVbX3waEEX<6dXi0?G75eLfd(3L+eH>|4Cq`?p(X6--%^0(Ks{h+>=0<<4
zBG!ycfx$$x=xbo+m?hG_FxTv=J4l|Hs{(!bX6a{O{)AaQ)ovD=vCGg`WcKtMxK?a7
zU?$uyF`G@tno7-f+M{*B>;qbhm76_w#5Jfe%Z-7;MKhyzGPspy5l;bAZMM`C`j^bY
zR$}z^X5}3GZZLDAb#0?r#v9nZVfNuoT$m=a->8_l+3YV`7T+?PxE3faW{ZvhyVdLm
z3Q@P2MP-25Ze~gq%^hZQ=mFDdrY?a(m)ZJj5V>zwYrFvZ(Ch+bFdv!q(37#-?Co%P
z;bwk#BixTNAIieuKJ%njFr&?{XQLHkuA$KQe)G}vw2U=pQh;*6d@H46;>_!MAQ^A|
z!Wklo=8g5hOfo-6Cr%ETpQ{1$uz4Z{7*fmwT<A@ZYA#&>m^Ab9S7;qEPp31qN6puN
z513qYGuj8|nOFV^>;iKmy`xT;?>+_4ljhqf$ysPVhhCM%=4JE(E;0Ww4Sl8NvuVSB
z%KYgl%+qP}t<GScG5?8Dac9jnv_d*(t_q^{|9SIQbJ1CD{xdzqD$JMgAQ#P-u7IT~
z^L<oTT5TRgk>5+^(K@v5nIDUS{(W=bt7ttm-*_0Ke`J1@;>X?QETwNBo9B5${i*q7
z`l&rLFS!ZH7v@9g8P;RIj{->j=6)qq|M1>?;#KIoNSAUDb(Q*+z!^8`vvR<=OCNm%
z7!T<xI%DZ6ol6g0FKLH0nBLON)zI^io*#!1hDhglLnKt{NWaE#>E=F&L`a>rAd%Ah
zUeMbseM|e;4CzAJH654!O)orSmh>EL&a<UTDqPBu+61DNEB*5>NS@Sg3>?mvKBJ<F
z0_oFUOz;Wmk{U>!l(syFexY<Uz5R=%X%9h)rDy0&Xo<9(b~vTd>}^m#B^_i5gQumL
zpTL<i>C$4l6w;1Q;mld1^e&Y;oRhLEfqh;&Iu@N5q>&V?Etg)TSYU<pyMG{hQM!)q
z$4aT|Vvs87Z7LGDBsJcFNR9MMYfM6|^rH-bU6!&`7JfzAP9G7glYSEf=2dCVKuBJb
zhR`i=UD|mEq(N$2^e;pkrQ2wed_y|P9<7_wKB}!~k{(Wn!_Cs86Jh?A^j|u%)gpaH
z!R6c1PwzmaRXUrt0d3OB{$Spb*4n{~cIlK2ARW@yCop(d+PxnlozmH~0PK=}X9moB
z(x*-sV5n@p(G)Uavdhz;5iK*k0%(lPrx!!pFWXIf^jMiuioQ5m>?}ye%hsKPGYK-4
zGf1NBLkILF$<7Y}=pk88D45Bz5B>s5itO7F7<Q`c6@5!RO}6Y8U>=pdqDr)MSq0S(
zWynrFrh@_}Wg%3fTPVBnEu1Qr{Yu&P64`w>fS#9Kr8?Rg*<e~p)yhshgZ^b%ei>%(
zicCEWeRZ<f8PK~b%PIlbHJLUW<Gn6>dI2K!veC(~+aQ}u<(6%-^Az{KBO6IS`*vCG
z4-|jykX0FB@UCnny?#4o{uJNrl11Hu-}hvPl7am|R`v&&4`t0Pupi0(`W%+JWz1e+
zKb8f(26-Ygr2}$LWgUN@@0n~joil$fn|Bz@7qb31K=;TvdZoXTtsMoF*D`;Uz8EEM
zWEy(vy_LOn1x&9j?KezKpKJ_;OWw)mgrn6jb9O`Py)1GIuw5*)3b^KK@zJLsZWive
z?Qpl)`zKl+7Mm<E7Eg;=S1?ar7B^`D=WVgH1m62uoTBUMZ_!74%>awlw5~A*SqN@u
z23t(Eg>NAiBQn7awRmz8mclINKL>WW#ls)aim(_)9>!W|DeQ2-!i_?{aTXofAn_K-
z^t4T|5cQ&!XfcGYeUil_I$P3ev5mq)uPpwcdQun5j-MduYUvgSdu~R{`lIB&CEpJj
z4@=8dc<O1nbsZFaEjQ3^%+Ioa6Fl^{OxOg_0L%4Tp%7%5Nuk$Z%ReYZ8)~`U63j5m
z2k{Vzv>ZTZy!KiOYta{F`Ftn5-)DJ*o?0=MtEmolzoqpSv|=rd$rQyqVEOY3XvABZ
zpMu6g%N#0sO|Z<E2GB%Hktr-4vTRrf=3&b<v5-u*9Iy=jrdST11CnKFnS{P<%kXNL
z&#_FT0DrD!487a(EWezAzI@A{sN|=>@)lKHp0s?g0khC@nsG9`DY3lu4HQpVCTPJu
zZ8`jR*u897O;z4kEFH(fV4dY=Iwg43vgICH*DNyvfOg$-!g?_4EnVobbK5eH7U8Xy
zB_=S@X4y#}<+)>dLIso#%T<44ocAo(c7fctd`<hw2bSy3(VhR$(lQY;k1Z!r#O#Ts
zn5s6PTG|c8b$Vv$PU+B>mff2{URhqHK*MXxvd;kX#<Kn*9DQpUbOn}rEkEYqMW1Di
z6z1PqeoMcYK&!($K!U9P!roO9Y~|Gl5@MzN5zJ64c|X1X!mJeMp%`w()6OfxDg!?Y
z$sVgz1+XKnrck-pUaQ7aP>iz5dWY6Ns}r<^iMG0z0}^9Zv;dO(trC6U+5s#7E=a~%
z{l|dBTb0y<9JDH?Enb4vlyi_wv|9TJ15C22##i-G|6uh^Cnh1;%7%U<DOOQIfJwEw
zFcQooRxuke(4$tPXhC$$DmM(~)2*^sgJf7Gc>(RX)jp~M&a|314ui<DO8FLg*;Xul
zDksOPoQ^f+S$&=l;$xkD8N}CGv=)+n*2lhqPsT9o&<NO#wq7)m24me%g=zb(4S~Rp
zwGNsCjX3K;N8oV0^-Ri&9<&~C7bX&{_fpOx(RzI$%qLklP_gJS>%=xVnrl7S6C}^t
zH316w)^+r}D6sx+9#AT+FHn@T%6jK_K&dubThQY2nspt$9Isn%y$-+YtqZ8^qruvP
zmR^n4@xvi<!&;!yotxG@C&6s87Ci@OvvnQqUT;~?Z^N}~v5s60FK%0J@P}lp^}Y4*
zzRh~}HjsAfp%j|yu$KP~k-OFw%|Pk2Hu_K)yvurVE;OE5e?vj|=hkQ6q4R|`7Ya{%
ztOJ$kductE-s!KbZ+rmq+Pa*6hHtE=IY8vCwL>BFdaeIh24<i2YzjHNvtCNUrGD$W
zUbI}~bB96CRc`GI5jVL5y;I%gIYz2}^pKyY7q+K-;}Tf%l24}Xg17u~FhqUiQEKS>
z%C|j*hM#=53z+`$ZEG;W0rIaaVLnhk<0(cMB+sQpNU(f8l_ZDA8Hyo>$~#Rl>@c}`
zBADTFJ`=OHM?U3$>mvD3Un6Ap%KNG6D@wkUg8%#E=P1t>E&rOfH!<>JB@FJDYc((!
zE02)C!~uEI2KW>&|LH0E4$61wp^zXS>4Whm%FE87FG)UnEBX$}WfZtNEbngtNtQ1w
zfQ3|f$@dsbn!NgRI)8FRK5hvn;i$ZUk|oFFTap2jF8@IXW`;b0HWtU_zr_PIQ!Xul
zNS1sQ?QpZ@`$mD8Bj0roW6F~+GzVzD+(_pl3gidMz&s%zTMC7f^7b!azED2M3#}q~
z96fA{<$LO={{6gM*8{W*@((w_V7a{d5+<rbURezNEAk!t;c%V2?*&G9RX%VFnAhZ$
z<v_bG-*gglQ7?C)GS3G2HVcR}%7>Ig;f8!5MdxnH_fo}Cll%znFq`Gcv`x4rFTW1S
z7WoZtfEjPgH`3&{%D-F#nLF}k1Gw$-YyV+r9r7=1fPGg!@E|lg<^G>Qq)YzmHIRGq
z&!QlCU;Y&Zp&rPu(p~aU{^ufqJ(Ame31+u^9UUfnEawhG;fXw<1<pK|$Ik`W3whN=
z^z|6!Bd<W?r97?)<duAi4`g1;|Dq-18~M%%4D_vh*(qqa+GyRtbhDXs3_iKr{FsXA
z_OKcA560wWb2b8K-ZqN+X!+O-q=l5P4MVF2KbskpX!f^hrEdfT*mzC@Gtee#H(Eh9
z#$q}h5^Pf%081e@M{__zZK{^RQi|=6aTrCKZLb`lM{U!nz9ro@_;WaO+}0`vCbDcl
zFok4}Z3^x9@@&J#!O}_FUdr2Ex6SB;dYkQ}x#+uNySompcH5<!(dw}MgRaP3+fR(2
z!C<HD7nH4dYP*Q`Q_pOjmO=ETZTlA>uWhX<QvSyF6AO^Hwk0eksMq#vFTCipZJ|KK
zJ6n@1F#Bz*sl@5M?VsrYb5ZP|+u2pY(R#{F@u>iHcg45gLm@!%qzKS~3XkRV`-@RX
zXal!j5x5_NIiPq;kMKB!ivHF`yy7A40S+pDngz*3#r7pM2@3yKC}b!cQ(*Um;%qj^
zNd*$#xXBe0=R)M1;vPK_&np&3(9NxAXV6!!h&u!e6$+=hP`{{fPN(|6N=0WqI;#|)
z1%g|xSP=-{E-9QTHC3Z{&tOVw6%T2_ds&f15#5`LuTZ%zX;RowY^GVU=U-U5rKn4V
zLW|-leRuM<VnH{&XjMc|2~3;9LIrY1QPKy!c7+3rR)=ED6WagXRfy?5)~U#!0{t$<
zQZvZhQ`EnMrTYrabBI1rlz)rXLxt69h&)m>&Bp|FE52F@*B&cIj0N+FA~6PfPZf(O
zFZfKMeGk{3E7aX+y->XR6(~K526~ykR9x4?!&i!g9*7uUE4EU3+Z)B!n-G1g=%4^(
zuVU2|nCMfCp&Z;hMT8ONUD(e8aSdEqD;Z$i*nKjHxU(&k8S`L&y8@9t>}!hRM6v^Z
z2X++eHXmU7*vnK_v!5L?2=g1u4x|_60oLqC_#0<rzo(^JJbR6r2idG{%tZpbxQwng
zJAjAzB-S(stwXGAHu?^;%cep<nGK|Zm=yNMhhV0%=V&>Z#ty!P))BVb3YLzt!-m3{
zV{AJGbJE$|P*})dKf4Oa<7~GC(3z}JApj<ey-%kOve`GDXyvf)TmX~Hwk^Xz^H{zQ
zgUM&}X&qU>X5~Qg1RMS}m?znUOtcDFhEmc+?6*`JRm@&p01r#p6$hbE%KrWwn5Wn?
z8_{=~{e$v1Wo#S;($BENjHjS~mObzUmd>$zDg1MueX;?f7udJoLBE_8XbDxp_TEO{
zMRp~9>Z6i<kcd_ln@p>$YW7My6fUu=DCb|pE~P|qE!#uE_RH)>2S{FF_m@Djj{Tl~
zsaM%?uVMZgTlIwYf7jWWblSb1oo)e`1~%Up`i*SLe;_y5%~_a>n`~VkM%cveq{whH
zdxm~Tx7bN1Kw8*GH!;H7Y(8yhTG_OZfZ4{rp^swSVV~e8m$b7#&w^_m>=+81+-2`A
zfxS+)bsW_{bg_9Y(74Cmd<ld1*^F$+JYZufiu913a|WJ1VkJw!>}F>?z?dGh*sbA~
zXV*~7;3->6*WelJO}V@0>_#P8FW5(P7N>`;pjG=z_G`MXuUHE*^qM_Dr%~Rp(;_MV
z`j%adIE<v1ZT5v|AM3ml`tR85mmu2DUO9sCzGqW%q3^<_e*@ym^|ZsT8}|p5iMez8
zXxZ$+jiMdBCpW1b{(5n}2hsB8wv2~QKHPRXapKGUcLP58aRIb3@aODmK#T!g_ybr9
z<dUfZAc(7_YWQHzHVK^}+&|Y~K9tk^Z#T$&vKJnPb1UWWH-f971A%+E)$|>YNNy3;
zdF|y)=~6^-!xKREad!>@Gny-lfrS{3r|i;xZqOg_FqW&$gx&!oH!%w`aa{XKSc>O{
zQ-#Mtu4*Mn0yohe&Lnc?^lnY!-o-%V5cgp=U=DNh{)S#M_lSz*Qn)SgKuhIZDesrY
zEvK#85zfB><S6%%AILH8ix1&NI+rsEm>HZ_404<^{;UNzlbh#=!DMl*^jy#87Jh{h
z=5X=<`x$bk6b8-X(kB5XpWB%Rg#zy22#^!pr{OSvk~7i-6>>jP1x^v??Sob^x9Vpo
zlyL3zg@aPgMGta{JL3$I)123@7*ZJ*Z2TGypW!MtU}$H#7h(+i9Cv~0Mb2|4DQ|dz
zyO02la_)x-AQjxsAdrjPddksNa-W{STvl<P&>4biZZwsgU*cx_1Eq#b$-y9MIsZJg
zE^`w4-CyBW(vrN6`(hDXyUO)iQ~l93ZVLx5u5&NELF&1p3qWh&GF(9#xiu}Ybc6Gq
zg}$5I0Xjv~#4V!TLNlk%g~40g_z*B#xN>?o-sZvvqpy`~TnJ_xSGx)*cet%bpx(}n
zro2T5mqCmEyIjRw%Kvq8pX`TkUEK2ubl&5ZPk`cmPJ`^6<N>$&Ezllv8)y&yh#PJK
z#codj667)W@pSY(;cE8c)_cm?ZpP4_adRks`J7us3xpTk&|^U9;g;M1dC3i-MA$2C
z<aj8&=B%-uLi~lhK=;*KE}tF>y_{wSMEkh3&0xOcn#REIes1#tkoVl*SE1;_kF*Ai
zE5A#CK{r132AJ;rh;q2?!Ph7u>B);jA>zd!DnXw&e~A{+KK!}|fcE9L(OvDwKVzY8
z^yix_Fzf(cO96#Iejn9T1@VWdrX!gDm}(?Kcn?bGhw>}s01e}##zG;SpGpO=5&RTN
zSnS~^P=RwKzn&sBdwDe-V~*n64#UzuepMs%qWQ>Mz>MMR-$7wNua8DwtdalH85+m<
zY&v_C&X=u)Vg_Hh3^K?0pD9qB$$vyaoh<$pC2zBN(}l2`!^hJaF_*tjZ^JykWhWfX
z=Rc`}YX$t}-4Hp!_a?#aNxq3{Pzw2<+JRZbU#C=TG5`7%6iRsG=M-Hm<=+p3rBnQ;
zUeGwrU;PB2W&DT&$eiKR)6qK1=hvfkj(<;o%j7&?b_o7n;Fr_(rkt;)hkXT~F(0jq
zeB3CQsO0C+#;=M$unc<D{9rv$F7c1o!B7o<ihd)t{52!J&Mxz-|AlW?czr6kbv#3*
zoLBkeaQJ<VA5F2D>-_W!kgVtRw2f@w8)*aA$oJAx^9KJ5olv{UuQ`ihH}Sh!NH+81
zroz%K{$~eBw(ycQAh-D~RBO}9`%>hvjo(sY#3=6YTj*#_J3p67zdQIROCfWY-~1C=
zo&3M;7+M!U?q{Ig<C9N-+~++gWbuHnr}GUD`2~Yv@DYF49DUvVtP=D+=0B+cdBQUz
zF{Gz_2vy2I<J0IA_H%yDF_?Y9YtrcZJ3ahRT7SOerR(ATE54}*Xs`L=PhtKIFCGfe
zw|uNQCZU%f`!$$-{Ft#2dB=ZS1=7!}D0uvy52r)=E`n$ShUO})szb|7@TEniyD;Aq
zc0GhnS`~T<)#+$?34y4rGD^G!miGQW!tO^f;VUo{;q?>d2+;Qzeys#{fbbFB!GS{U
zdWZxGKhjGkSV*GWV2IF=3$#$7!x9Q%f`txX;etCYJ|cu<8!-0>+DP~mDNLmu%wFL`
zJG7#N9e+Z^xK9Y3iBUugq4P2N7-7g@xVT@ipeIbM5LyU>2ZW8z5Q!7`<q(M%0w_9h
zP}unhBtcl04}TMd?}Ok)lCYEZVTXk8sEY8gAW)1mS!i%UUy88mSE#27^CrP=n$VF1
za>OV|3L$z_h^ODmF(JADXz4<nfL4Z(&<_*Gh5M9C%@o3B!I><<umB3#Lg_$=<OtRD
zbI28}s5mxH_>=Crd||*7pcDu;H=uVy(9wyylfr0<+!qR8Q|(ESP;v|Aiv?pl&3cL8
z+zgFUA(!^Mr-USmgPayT>E0<5hSN{xj9{IJ)>%P65t8SGOeL7-g{g}HdO;9EFtl<Z
zl&~v=_>(}nDD+c?q*7?Ti@qwMUV~P(klPP?mxMa1%&8Gh81F!|R`~M`Ixh=rtble!
z@LB}(b;1XmL9Pm31~9J)yJkS~y0D7ERrSI|+LJa2%P*qUC{!n6o^A*Zv?I7F)P4@h
zCSfflSeu1uG_kh?!!%fE5njrmcUveN4xd_u_7}ANY!kc&fZP$%sSvzfF!TVXL)c8a
zoV&u+gXrrNHlKxwE@3J?rSA#e2SDx%_o>$If$+~Wh&&X6X(#bWSX~42-9jNP2_6f3
zU!(Ozm_;a0h0*kQeJ1RnHOO<}=~(*y&I`eZj?MK5wnrfIQg~R2VZRdUy3l$p{Cxne
zH^NMFxc^r8g3eg>3Y%%q(<j7DgUCDK;{_1u7mAN#pzno_4G?ir>ecYjRcS|y7B}VA
zv1qv~kH1Bqhf+QlK1C?M(o_BI9;GFne2i4u%tGg0WhCW7qm+)D;L|?kLaIK9QKs#K
z#(rf-E<|FLn<;X6K)GuS%*QEP9>aXRay-?l9#k%#289HrFaXR%Wz;UXouu4In1_^`
zMndnfQce-pWM$A45MzpRAqAgPl?QIXM4IvvtxS$6*W2Mb9aRpcc=0ji6Iv3aD>-*C
zk1OkcgF>cq;=dqSN-q;AWGhF|?Ukd9p;be!@>`16<|${qg-`j)ts^mA1<KUPFn>b%
zE5%<<D)-QL!U~PbKH9q!DYbI}Q>=VRmCYr})w9uAszlfpKL_P(+T5L1-l6KcG9?1(
z_&F#&4#31&W#2%UIHx>I=lIVng9pO=1!WEG*vggTf`L+@JnI3;i^{lejHOcf#WavA
zWpX4itChxw-@^PQ<#3A4)+iHbZ(6H-aunpUGOz;7D@sSIV69UsZ$t8`a(F7pHDwW<
zWxcNKcnK5r$^le5+MqPA18G#6(Z>9S@(GRprZU71B2CK4Kf<SGWsD!@@Rrgl0hldH
zk?~{tJt!;k0NSdQE`(EU%D}ZCca)n~1Fc;-d>@?YQ1;Rq^R9C6Lnw4Azo-JUOZl%3
zBKMRLWk9>HTs0V$9w<ExU_Mmd*$nbXIr<gAx|OB$Kz^)@Q$qcTvepsgsj@Vfet*xD
z-_YjnxpMqc%-##-7k-$b9_3d>KzpgQS`5)wN((x!@LK6L1a{vjgQ(EptumWd-@VE$
z!ywY9j2aKHcgn(lA=$4~(fi=NawXlJE~>rh@X%G2G8-*7)mB=Rx~ra!r2K=2>eo;x
zda6!S1j0-8gw9-es~!Y{>7)AdJ)H4Xc?JU1PgQCGP=8f1rNshNnmb?ysv;=u8KfFV
zYrSCA&xLS1L}gP0kx*4=DO?Lv#Zv}3T=ioI`XW^C@&LU@Rr#L2zZ0qQA{Y0ne0o5l
zR5z&FdY{U60`#L*KDRN6F{;K9fZ4B#9uE?$`sg#D9Z-F)g26bIDV?j2S1q^+XAY`{
zd<2vPl~o7y5><U|XeFt}(22T3s+EB-e^_<!D?lf!Ui|{5F-4^x4{oaJCl`RGsdm!&
zh$AYiJFs+A^&xF$kEwLDMod@zYzd7Fm1-%lkE=9)LnKqhI$~zCR5L_yCR;V#9ep{f
zIrP-aRf*}yN1p1n5+eDk$5iZ8pz@^*)(I6$5yz88RSxPnC55V@UMLo+Hr<0W#i}Fj
zFj%50rYuOQ>hU=+PpR}YZKqYI3gAVVDm4vg=Tt?tXq{JmHyUW=D!(sbutN2eLdh3Z
zWp&W2RCPCDWK}BNC+MqI&HN39E~&;!pirYSj<5r_R`o?BEL~Q;jDqMDRS#wJ>r^4p
zAXil@PeJ6GYTz<xTvu(T7)ibA$NvD+pgJx=t5Nm30b{zMS`d!0+*DOB1hZL{L*FU7
zrIJuEs6}OI2A^)L{#pUjs+v*@=r&b_F&!{>R3p1EigwjhstfN>9iI%1yDBRRg>|aN
zQYliG%9{QL^gUH1C6?~1j?aYt1J$Qmv>vK*vOpfG)^CMmw<?d8)Q?r`>G<^%RT*vi
zpQ%2f^AyijuW14JLiL8~*LzgIPNBfsOV#gmN4!!UdIpDItK6xW;Eies2aUHXMHpJW
zs<JXT+NT;o8{~JYfECc|SIwm~;(OIs^sOitwZ%I4>#F{ZmalH=Trt4h)yZ1)d8lK%
z(ehNEJ%fwpr7l_lNpJPMCi?yPsI6%+?yK&Y4TFB_Lr0+RuU>c`J_V?U#6u%cJ!vR3
zg4Dl1MPIPGry27cqJCBmy-;<j6|lq9!L-f@S09=N4<povX%)LiZAE|SJ5s%P2t@X(
z=PZYXDD}^G(b}h;hLa{nNwnHP<zzAHuBXu7uikJT4#%o5&W4Et>U4^3#HpkDK;qS|
zR7!DBT{IW11a<5Tm`_xHF(0iY^$e;nJfs$e0sFApm8yo5)utwxrxZ1J40co1U6asC
zQ{SU1fFtVB))<oNsCxKb&|~T&^r@?KwTl@#Gt@)(o~jpVjH5OHEl2Gz5oo#U+hZ{L
zJhdaG3i8!?xgZ7ViBgz9q5hQ4o1Rp2hcK2xwND;Uiqxa&m_xDp*i@jDsQuKK%2IV>
z2$-kT>uI@uT7A46&}HhcF5vQ>QJ+bG<XN>fMUT#@9gTVDJg;`sfm~3xG(o0Zy(9ty
ztx$iQ2D=y4#}2@YN_E%`n6FaLT#Ht<y4MRLm(&k0z*3DmxE6Y~>Pkl_TvnUL!nG^v
zOsbr$Q?JZ`zgN`@Xx6T&!zmbZUA>&n_0_9quc9)I2K5dqkZ#1xpmjsNxEV4x)ib_<
zi6(W+B8WDtQz`X)OKr3Uvqi1^1d_MaVRQ*w)syJs({1X|cVOO8kC_KY+tq&$f%y*g
z+3A>sr|RmH@adU)4~6retKa_sXI`l9_)&JOM?IaMlP}dj(z&Kr>M&YdzE(dx1N}GZ
zS~|@AR((_gjb61)7A*Ct>)J5hcj_N$1J<t|eja_t>?AgjOt;%ex9oAd&~KogWtTJ@
zec5(fGvGyzoqrWZmTT9S4rZR+No?_qk^;MBdGPzBUGy2C723U}7iO_t1EqpW>=ye#
zwA4;xPgm4#1l8o9wv%}Qt;|kBWh`gxM5jT{+FhYL_nci5<&!ViExbrq(r$VYoT;$;
z{R4<p+715>dR2C_u0XQdZq-yUjhF0heg%yhyGLtau+}baI%epyT~|Fiuh`wDplY36
z*N-rN)h?NGi`VQF&1hY>yZs^DuD3H%YNWw#934+;v`eR5^9?&qCG>9E@iehbb~i%c
zcC+0fEhKN*eNAE47P|#Iz`Sj=Gy51$b=Xazq(+zB$rpgRXE%(6=zY7=dw_XhmqgM1
zhjtFNxQ37H&d?jH+b$s*3Xkm;tbycHyXmul_RKCj7V6LK)Qdn~*iChSdXJrF9z<T+
zRnoDjS9YI$2+7xWF>Z8u?Tl~w!F_A@t^!{4+D-ce+&;Sn6)^G6ZUVj4`t5j%T)em2
zI}<Q2nu6ybuA1sm=yTJQ?T00I%`%FZcxaZ<3)53`_$5TVG@p0_(_3?77W#ZN(UhF?
z)hrr|vG{3**1>|mrpK59Zh(fPL|UL`D6Ol4G!J8-AFSEh0L2i^`P~2w(_~ORWVj}2
z6BHseQz@yiM{{l`Ohjr5x^V6GYAysqBuZ0GFOYqj$<JXaT2tW#%ovRyB|7$N20KA7
zR`Ux5`3`6r#!~`4PGdg>qVbwKdVL?%i0E!f&>VOH>?DnF0rPc8Gx8UV_pl~RfI_ln
z)<#T8ie^AQTualqK7-y-O$<Ffj%hOGu#}-0_%q0H&B$F4$<z$E1iM+9o%B=5)|Aqw
zJ4ZA05mjg9X?9SgC|{H9h0X%a7d$#oXyzS;7bi7pikTN`e8VuNB8|@+z!Ymv(iJJu
zOr8M`OEu9C!91n;%^o7BHEk4#DAQE`0kAWgibIe*t0_JN<~hy85g5dI%};b+T+ocd
zqQfXD*VIyov_i9!Vl0&!b2&7sG<)|!qgr#&1g>4uWK&eLMw6_9iCRq>)reizG|>v`
zt){vHmb~qs-2sZPeE~%?{p>pe(6`rqB~@ue+n=TYe5}2e!qoBh*&jeX(SGx4NE%b@
z)iiCX_CK{lG|hf8?PQMFi_Br^sQq1f<{z^!od++{?U&LkHpBk>2AWy>1*ZU$Y5ys$
zTeIv}(E0Ri`!<^H9D55YD$BK3%m8M-eIgxUFR+))0kh109&K{Y*n6?it1;RqQ^{AY
z{j*09y=*_1KGSl={uM2u>g-qO;mlS0KYqc`uG!C|nC^A^Kza?<+y9dV{RaC5e?hO&
z{!$s7xnX~pP;T0f-3H7i`x&#K&}^Uc4k)+ms}6zLVjuny^lsZrHp8b@d*gsAbhg>c
zUc&u$`@wW}sl&du2x#sOkIW$B;jon6_nr=)?|`D0gFYCb`yIxthhD6Mj*>SA9QM$v
zJ<j1uDon&X{Q52W4mvpeFQMzOp0>nE4s#cy@36z=N}yyoETp3##~s!hpJTk44iZ~*
zW;qND#C6JcxJxgY90!wnv~nHHXpxua@Jk9zlsXKjy!|N$CIWq@9oBygQt9w5ef6)(
z;rt4aY6m^-b1ylJri^*5!|ZyRQHL$Gi>z}nr-$Y(hssoV*y7;QK)2p)hhHdH(CXm$
zzgVHeM?V0j-2nl3Jj5IlP6F+v!)H`k`^q8iHRkEHLqZs?&l`uM^my)d81g4P>~nZW
zfrNJsT_2;>@9@)qP<L@Gqxhw(<DgfNbaOnt8eX_NuJ=WshvWE76rJ~U9N&)7dpRzl
zJi3qLrPb*4bu_sF;^)}l4)gwwne+vk0LKwB+&h7eUv7n^Ajjs701b9r9S@OE$EGBx
zhdI8whQ4setyFgw;W)7adV3s^ox*d<@$z^`?sZ%~2tGwQo^|@)>deu342BltIFdfw
z5bL-#0i6dN_fUNLuw#@z`jQ==(po&#@d(`zX^xZVadp(uZxUMRj;^!`&Tw?Q3z6fF
z!)Wo4>3H&27|e3qJ_wlEj{Wo$$Z>pl9v<d8ZlI#SJjdpfAjW*h$X!4yaNPX|CgFtR
zT^n!<9n-GC?penjv<5lnxP>ay&pU<=gZmd8yRN{)a>uX+Fe@BobYEO_97e0UD#st!
z0;SrK%Rt{H$CWqHcinL<730)9enAn|7RR5cbmO+;UMi|?H9CgTCc4eB?J*|mj^nKF
z;7q&Yzt5rH;dqp4hVMGY`a-|cv6U)|x*SJ;2K{@EnoVHdcbq~gnFo%V2atT|=&=i4
zgbW<g!(bHnZ$!Eutb8b<yy?ilqu`sn=m+|Bc!++Wb5EW|(ex&|_@de6(DWAl=7N@w
z==Xh4_7zpqJI7B{Ll?nc6pK0u(-_fJTEypyR+PfiJW)7p_wz-Dh48IF)YAyP6QUIQ
z8th5Y6spoH6bU{MDH7eJBJ^TWm_77LM9+SO!=)nQX&(&#lqjGa8mC1oCqSl56c~=y
z8PSn?^qm#WrG#3gsQZ@z157(bj<k#QU<N&fz9(Zn3<kZJR2ztRGtv|&_%Iu5A>zyI
zIZfU(1L^hP&y<9N8NeK!357uB%Uh5PV!kqNhhi`@$Pr@-VHOC`2xXQe!;3H`644~n
zIA#zs9;R2BukT0)n0krN(0u!d3qKYOFbx&Qeh=(OasNp88zbKGDXz?M@g~HZ{x|zy
zoU6n?rUX%G)3lw3AUZvPo=`Inm%+e_*kyD&W=*9zT-p4XG7H-)=w5VQJOM&JqQV9Y
z(O=}S6sY+kUs^GgiNc5d|4YlAr!{cDc-$wj{aze07=F2!Y)q$tn2a3{%uo||Ixc<C
zY+o8w6U;VKf+Epu1Qop{nc2~5_qI_!q8&1w@-#X-(k;J7F{B>3@;*BI<h$3Q<!-Z*
zLP&l#i>Uf6)Mh%Jaf`B<u>-9*8^HyVhi%qeg)_-E-IL)(ip?g<RHxdEq~vg#jVc4J
zBQ~G@hEW~0DQpDTF`M;t$S~c;c*`F&!zMf#vy)>Z^@M1l&BhdvG8^3npjFuDDGXR^
zGie3%8*M(-pznsw4<`U~(`NW+m}s)e9E(9T+r<A4(rxpa;^&WThSHIUCpHTxrufuG
zK`H8IHv7_H@43x;3VFS-S!1Mpdyh^0P-wig$v6t^S2hQ?L*|W5PYz_>+AMQ{NUu#o
z514&6krc9iXEUFc$^AADEif1FZAN_xY!}=1N)T7u9aQh^X4@ZymbdMoML_YfmHMOQ
zYpeMN>VCFL0fzi-Z5Sh9LT$HF5lxuwooyIsxNY}kT&@V)>N42fW4rD)(2{IFy8xIJ
zTPeNf(`;v5gF>e5bvlKaV>@aGMp$SY{s@vywl5~4ui5q#VYb+I#)I6pE#3rj$9BX%
zD74#7`51=Y*beET>IfG_J`aNdioLYT4^({j6l9+wW)dvLE3)Rp?_|X?6`1LY7&-==
ztFV3vm?FiLE%51#VlSoiE-HekBJQ$6@)aZ-6n=SVwJ35Z!gyEFNs;SEiu=FA?hD10
zAUM;jn36OA_rDwaLj#(=Y{?K<@?$+HUgFP=i~&plYrt<w63Bi|b-+Pv71<4D*SKQ#
zLfEJDC#6E!KaN8rjQyAjhr?ObVz?c_KDI>P9@h0E=tZ)-)&OiT8~X%$QS6jUU?#CO
z4zOoD#NKO##$on9s(wjkL+D6F3foCZqEvRV0x)Up@GWrv2pc&Ll1JI!&Vd|b4YYzu
zXE_Q@X0Wp<{CJ%8It9s0)`xcBS*(bTVq~+k-@{-oJ3S7PdF=iH7(_n%0nK)Sk)1yS
zohR5e{vapWYxGyi3fXnEXD?z4XrRUHPd{L2CF}v(S(dVk^ssb_UAho3r&;TxfGJ~l
zHiLPFo%#{<&a&1qn37sH?>L53&pOggc8lGV289mx!4P=(kX=aiQ_orBB2RF8*&W{j
zyN~_z21MVn7p6eJpB0%x|2=!a527wyM<K8SxIbkO3FL-RY$AxW_z~*CoHKphJ%o#<
zL&>4sNA$o8=fnp16v2H@$LIENQ)fdxk}LQgdV9G)%+QMB8jNkA2e~M!3rgVL#iNzT
z%^v`mBrcV{40(tvy$6`X+{{z(BAHuCCG#oV01*tPabF)t>j+m!H2_Ds0rVC9V_X82
zcBOOD?U<PiZqWl^9_LQbcbzl2@Jqlv$=&5K+(OQRq4ie@mpcR4rQ9+i7rB*N!K~yK
zHbJzSbDRRjOWcdk(5mOcEdkoV{a6ag8{D@?VfQBY5$)XDxq&0$Ob2J3hSpuKk8(_%
z+`(rM>EZ(S!ryz`MT&de=lU*!Jm9`hrRu<koCm$UA93&9q0!BySi#a`Zt-$>@q{Zr
ziq=!k^(Ch58TZ5$FweQcFW^%TH}ZEVyySW&;u^f-G*s^Wn){9t<!`u=pJ0S<IX9Lr
zFPFU*7W%kqH;{MSsOtdh=gybWUnhFc)qIKha^YWZfubv4m<bs-o}~(UcfO2nT@QY4
z1Ns8_V_$(8#1FEALNG6;<ZuWd;RduY-s@kw=zL-~NCf{G-DP|Dp+<O-z+a2RSQ7bK
z5=r6@wxD&0Z=*sy<6%C(6rjoc)ahuZ@Xsh*l**6qfMOcI?h@wt2tOzkeMfm&D#$T@
z`U5zV&R5-oYZ?3m+5#WvzrcGDg$&=&9hA-ASP9G=-mwd<T;60kT6z5WIJENljV_qc
z0zQT^@+XY^5PCVD<Z(0@cLaaB9-T$}FO+&M<_+|*q7wczW$jD(uPGCAiXXKC9-ijo
z$AVeL8|WNN4IfMeF17r`MNqiHzoC6`9iQ?cnAdr4dx+HY!v=sn;<sgCy1IFO5=bv^
zH28tr$B(6wjd#2o9jEE%e_Rdbdp^zs`YuBCD0u2B)YG=WO?Y<~cHM=&+u*N<u#wKl
zcnaT9z|c!rz6yQbLi$$#^ASA80>xLbI0$t=L6(eGfN+T>FHrb$5ST$imyt?pf(6YI
zV223DW}q`vc+v&zFyX&@=nEINXuymRDm^f!J;EcJnMh$=JX(8&^Zo#h68@##-#+0g
z9T$uiuG1Nc7-2G1K%@xuhrvu0{MUk+CQRLg))8U)AzYE8LbD6)5{?N`W1ycQti1)h
z$AtiT>|_edX=9ote0dA4Y{7g#EaeEzjUe$KAO9O8%=&oQZa9<u@zgs&@%f~68%#8e
z`I3c+)-m2!Ff;EyThk0n{ht+PgBdpAB5iS^CQPTt)xHTo4Kc;<FJ{8yi$Ken;6Z2d
z&Q3Tt1TyC)EL#GZstL#Fm)<#nUjnq0&;J`hr;za9);}m8{`*Y&R`(xIDP8jC3I}-c
z7drq>Z11PV+K%^eaDC^NHmJIY7EA-ItLV`~wA@6pcnJ83h8hO}#$U9bstyB1f77aT
zk7y|s6Ge)K(q}mih#t{iB2Kha1pRoCD^(w*h#sh*kSf~U3z8;s--xL?A~L1ubGB%8
zG7U#mPq#*q=npzCSuFaKe&i*hXgcFiDq2o86cwTglPLarQMBp_Kr2P+P8h5b-Jp7~
z>!NiHaHd|=N)gNk(I|R9HHw0RV4_vDk8(L}qHsz|-VymWLA_nHYcf3S5M7M`=3UXi
z&){~aD7z1RU83dW?>$lU3G_V`eZ~UwnaEg5+41M1E{d1E5dBS=v>wq+D#m*!nnoFf
zev!vKxc^>ssR|k{%xQWpyE3wCV7f8aXr<!Ly!{=L9*m5lNS=%h?YX>|SlXg`Gc$7_
z;=}Cx3DCZbB^BuUF+1s*>d$<!o}Pc$5>Re3ka^V$hl7~5=^(+3TM|eJ^Mamuq0A^^
zhA}C$WC&-zasXNcGkOBB_b{tRLL`!Dq~PjaCWA_!qZrjXnApcO&VZxQOaRrn$1sO8
z;M0C)*&@tgER#-ADB}U<{5McM%=|z}=Va!28=T2tmd9c+$C+VtXJ#@ptwFLFb2{mG
zlKIyhB87|%#WjkU(5-+eX4W~uZVBT-brR>9@BT*L1tvZXdgY8Kg}o}6|8_wABGb15
zu2nL%^zqIrBQumDpEsF{ROrye%*_C4W`5rR#aqnaRZwhYis?HP?aY(8(CA>sML_>9
zGviZ?qLbP1D_vja!58rU9<!8QF!z}x8}vP3hEb}|MeOVf1#j^cI_?!D?*1J1_K4ri
z19QLF7(WCC6UFVnz{C-8^f+*jidUzD91|DKgcs>zi$!Q<h#3z|{&De%=TImTZ@vu^
z#bRp<FiXS@qu^SpxamGxr^MwN^qm$z8v^rZ#9!09;H=n>f)(e)v2?Z0i+4rBnG51w
zMm@00#iP2Qe^p#u2QO}lmmG&ooA_}Q`tFI%w}bgayrTjduf%I9FxM~M@iP=qn2?F-
z_BP3;)rgNtHC0sjntb;L>V78sX}j)k5;F#a2r#*|7_BIiCNp@r&%~9U8__1I{q%l}
zG3omiWWUK=N+QLY%=!V7c)%pW8SclMETt#JK@(>heS%33l|?6-{MHAOWMZT$yhA42
zhtnNoGK{JavP|kJmUY79@4rD#naIC{$OV%zMeyR1Ngmy@*G!}{0M=yk*oM9ie#d0J
z0{Rb3?1w|<p@}D*!G2`&xeTP+<oR;IJT|#%zzCn1ETQ6>rzYm!fO%%3Uk`)*CZ&sD
z;=M^qKO|iwTN2=!t0a;tRox_Q0f2Uwj4OtMhs4Gm7Ca>hb(kP;$!(lmz}NXDuALC|
zmF%V?8h(=IF(CdDe<~CTkVMmhCs5)~v6>)BQ3G0gC3C_d5+zxF5v_faWhWsSE$NoR
z-xx{cUYbft3`K!sCBtbk6Nf`xkc`J)rvu7C$#bfFPLP<Lf-}ZMNoEYZNs^2k2AD$<
zcS^#hOXj|WOopV70&K@6l`GMgiPC(aWl8)gEs!m_Lx(bQB#~4RoGWR|#R&5yF`r`+
z3M96)tvn$?@B=?s$?I0wEtJfqTcAktLju5xCAmL=Sz?r!Is@i{<d1={R4y4ndEN@i
zA3cz{C>az7QYrb%8Kg?`wF~T4OFq2;kxLR!I&)Vek<NhnWl35$T2~}}R2Nw%nM~DT
zS0#@0=)WdW(82lZl7SUaua~(041XIWsoOEYM*MXicVOR@<c$XDl$d-0v@S_&FGTN2
zR7DufeaS}JD?gA-vIX`d$%T#3@0N&SA^BJmaReeyBqs{Nd@8BG56Neei}YED_YxV!
zBVA0Z!r+>#>EJ4;yP5L)0qt(OHVl0pre4O$(DyX`^8{S<HXStvqCTdh-vQg#)P4zC
zex{AI4)-_xXB<ESOxc}i1)8b{Lm}GqtHFSYF}+1c4fmU_$U$GM>9k+bI$-*qax!tI
zsT81&H`P<#^PuVML+~)sbYC@~lT4?nX#Ic4bW0S_4x29d5q6VJBPOFW#Z>kH^PFmG
zk_E*y(`l57Dl^@)0T=d+sT*bBs!Z3Nf%msepHa<ni>U>zM&6k=(#t8uY*z-r&YE%7
z06S-PE(pvfv$<5S*J8HoFcj{awU4CV-&3;%`A~dqc7=*z-<V}m^vTy;Qwt40^PQCX
zjxg`O0rPR@jkJ}^G(Sj{21Vv8sruop`3*IgP3AUq+UBYGs3RD!x3rxSJrUAdv_MFZ
za%y;STpIK}Fmt62A3&r+`tozC&b%o7XE_x8Wgpvv8zk$AL@QV}gzohaSwcS)!(`)T
z!{Kn*H&h6{M>fO>%t+beS8zL8_K-gI5F?XJfXIH?YAZN;K=w6NbH~Xf_Ar<z^Q0$f
zlI#S1_w|r$6D^BUWS1?WZagA$`wN}vvb|5BpD8O#g~Qph3#-wYBfIx6`toFa3efUp
z8MZKAAUjL<)d|_Z^b@a?nGXl4mf2s&B-F~f=owZgD?1Al*JK~iqO)F>M_H~$S<(`K
zHOW4F0A{P~zX6yaH={)`oeK1@XljIpmxYod@jezz1V#~LaV!v`Ar_0%U?RezaU%31
zEk2ZixzECrUdH<^vPJaX#((^Uo%sKXIg~zHsi7*qRr9+5wz_gA{{8(X3P1gjFF<$A
zMSA@HXiKGb#<eTX0(D(>Hagbt_JG+9g&*MmKZQ_6bK|h-`2WwFroz`>#+Sg2O{)d`
zfAf6G6dFF*gVAnJrPJIy8jb*A=M8#)J0F-2%zsbQV(Y)eN%;3}@1ejkZldXQ6{Xps
z;U=1cs(K>=!U^M{87L}3kX{lbx<rrvV9^_@r3n$;i3ZsxdNU6q(W0HsK#virH({h1
zqIp5^Dqr*q1?5Xc=jt%13!<I03a$~AU=#d*)AIcY{3DL}rv;|tnbOn1JIK7CV0{8p
zdBO<YL?)mUo~AI{eg`*|Ic^DNI<xB;Y-TWnZeonbnYyv)%VnlIqLs%?r{HBib3PHI
zfN4_UnO)4-rb3~F`IpYDmNGS7xISl@q`zSP9MeWsR_B?7n=n+#ygUR8Rm`R#lz+U;
zXz2d9!t82<>vha*S~Oi{=8uC+BU3?@ayOVcIcVKvQmGL0HuLi!v|5>8Xw}iibWzad
z4m0zAt6*kQ1?=8qHco*v_n8JNt9;BXKMUpy=C=b-=wYgAp#G9^#tmbX^fJkx!>)_?
z7kaWim!|H=Jod=kk(m151on$2(lhqGXd%sx3p0N?TySNyp%{r9<24Do?#$pCSo2^u
zoCfh^tTgEJVwy(7nm4my2j;_vnSKiDzD!mY`uvz9wDIz1;*D>B7Qoa{*-Ri4NH54B
z<_*#ZSOR}RCnNST%hgbfW-jKSFNT>{ioRsV#sqq)%==fe|MQZ!q<!$p!krk|suv;9
zSk1nI`u8?Au=hh3?UvTqq=NtB<xU{1eX78}*R>k|f{*K~>f!f>?ocTF<oGp^H)d1z
z>gRw4fc`RbFaE#jb9%7+nnpp<%}JjDVvEy$X#F)|HioC`-v<7UTU128)A%J#hRBnS
zFL;VpQ@ysAXwG*uCeg-kVJ}3~d>7)O|F5^}j*IH(+IQyOy$ix_mb`X}U1LLvikcWB
zf+bNzED2TwM8(h)G)7T0qM#DRf>(+niWL;B3yO+j7etM{Au1ZBC}OYQbM~&u`}_WV
zzwaf6*_m^mbI#1popR>Pg-z>7S1^~cf-XQLv0D`JoXmcE4wF~2MTcQR3cEiGh3nW8
zSBTlbUfLkp%)VF+KsswkYwzvMnPMx8SQ-tv=h#<=QGxU9`7LO=z>I0g{mHabk-N&`
zdjNimZLI}k?y{aa6o2xVJ+ub#1sie|tZ&))Tj2S?>|G%36PxV@*>m{rmO!NNqV*`;
z%QH4v!8ZJ>rBFOs4*RPkF#A~Ebl8eDhZQQ2%ZloPc7PRiL~@YTtA)ZttZ*F!<*~7}
z$3DeAM$%!@X%>0{_%m!3b&dj-L@^45tTPp!Wnm9sT@mYKYpR_eIR);q_T-(q&!&z-
zu9O80fY3_ztUqjh!Zg&zuh~Qz?ccCO@@)LhE3#q5Tt0}_@=<)wGywkKcOz&%Tg+3&
zL+=v)=ss9ialwcrf#3H><0kUX^va9%eC`aWPvfq%71_XZDUxd=-$Tz~CU>LZF^lI>
zSXvGrPT|7)c+Vryw4cjQkjv$LX!(4MXOyDwIFH{2zzM!+3eCSKc^y)Co(~uY*%$cb
zzCirRlYT@EFY<%5vAM-};)V0r5Urq>6c+Q-)Kl;9f{&n;@cJFlPLKJsUqLJ5`If+y
z^J;PrRdAc1kW_Nd!KmO9{@0ISdCFZbp@FLS3Is^uuQPH_IxVZ_*U88BoDZeIpBKC{
zxkO&_eF{u_#rM4g{xwhk1ND8wvnc}fEgwn2eD8SIC&<0$Gsgh%fv=~4uvpQv8h}JG
zgO*vTqIC>x+AOvwV|IwEC^+YsIA;b5Bd>{1$R|=Ex=#afj%2qCLRU)-+`yA5J?H^r
z@}wSrL1>Yb6pF&zlD`kxE2S<5{+%@8vUvzNr*UeCM!v3zXisdKbreK%2Y+1#Eq71z
z^Ll_DXj(*r1xw01&{?V3Jdf62&oqPRF4Zf|=pY#VRx`L2a-TFOX;%{^Co*$iuNg;S
z7hY~pA#ZqLIpmDAsR=QozovEdm>EV;1NtvSg(u1#@H@O}8N^M=e1*?b&)0^`Up?uN
zb2gh^i0aH??ih|DampD%XI=~0!zB=~jJ=~MrR6Mn48Tcj;{)W9S)<XQr7^p@0B&Fx
zXbRrO&Xb>bJ7fI-&t%r*Lou?86bGEm8q!Re!+u0>#&h}j6X5&V3LBV`%epLq6$jXv
zqmUALkmb(+&mop)fovYrpGRd5GY47~9AWL#0nBHA!d;Go&}Jhb`xu);0hh;F-*O};
z*tN;vJjtw9LFg%V&IQS7_AR|d_zcUO519qbi#kyui%5X5v#bR<@`~7FT92QLWbJOC
z^gMe(Q8yP@Uy8fD&fL;a`y1>Ih56iMKemOYTkLCECEsR~Hv&-1Y_q}gkmYuR?7!He
z>0o)pD&qlv%$yFRNy^y%Kya3`{8o@s!Qj@WL1HDH6ld|WXb9WOBQMc)i){YOYlzv$
zy~(|v%WsmuHxCXAh{@-VC?@4N&$&Z2<Th}@VeT#^hiegkOS8hCJjM@z>wIW5SnhGh
zl`w6#7(U+;rTABCJ=Hatr_DmLnm0KJ=o()23DC$CUWXioYx&y2uriewCc=<){Mmfq
z*7NjISeM2>v;^x0UX0leqfS*{XxYR&P6KW;fAb80Ej+0{09$$D4REGo4Fb*#US15&
zZT!$7aBk<Bv>eRj%bP$^7Vl3HO*<m_xcMON<XM*ZR*ZZ?0CIVJz$u71%!iT7_Y@yS
zF&L-0e>IFb!^hLfcLDb#Z_Fj0un6ie^NAfnyTZ2>A$OJM9s}+UKk15!mhc|5-M-7G
zku&EWFN;BPpJ$RwzLZD)P8Vq(@aeGtKIEecVANkcl-@%1h`ZDG_n03gUvU}VV-0EL
zynZP-E4YEiw@Uu{0%%WoP#%(3d<HFVUvqofhrQvasS~~BBAv~?<7+>l@I5ao0m}zI
z#tX?u-Xd~6i1S6Q3)(AM9Oww4OT@F!0E`n~jYSPtiFMk5B|&t5f?TS&g?u~f#1#}P
zwpARs7B;1eG96;=600eyX1DmT8l1V})fGq%h=t@_JSHx?in<&Z2X%+&6XKjqaGn!m
z>}VNuUUVf7)dg`~IgI*KY(yjJMR8{kXqUu-o}gV8r^Q3>74dWejJYZvqVMOLm=X_`
z>*BzPFy@Bn@&#ny6!$bh2fZbF?gYziv6|voipBjm0ly;-r|9SsaUnhH_r-|abpBH+
z{zjY12V%opQ2$Vz;sF(pMH@P~DH8)IP`zBtI*(dZh!-+}uM~C9kyME(-bkK_iVtL0
zi~3!_eGpH?LH2AZUIt)}l=cp^-=(&`Najj=$lVkr4e9{Sd6MgPntx)XAM9cN0;$&s
zm>(;Ja9Ht&WJ?zw7fZ9K2QHE9C^9fkid_I>wn&xan%yPYtb~eOX~tr}k4l#*9;`r0
z&4-jSsc<=1K58P%!4e~f_JXijc^<`OES3X{z_L;vPz=$LiSowN5Sk?4n2T((97Ar&
z)$%4f-d`gZR6*!kxuOLOUMDB`K~tK1K@XuDWxHBrj68G;3b)FJMi81V-`EIRhHNYY
zZks%XUX+t5-=s}Pmb~*ek{z<kZ1c*xX1E`<zt>jUq7Qp#1C7J)+T!zw*l-v+vL0Pj
z8a1;IB#sX2hu`C-J%fbt+2os@uwybl2kfI@y2;}_z#q1m0y4tmXr(aaVIqD{{rUmw
z^y@;Z*$jIDB~k1g_2zl(G%W%CV8<iFP>IFN$_c8LusCY;IM$&8)-PpazCz6s*aMnJ
z6ImQR;YrM$Mx<ochx+(x=JE)lvzWav07e#)1Yrl*_q2k}XBmr;oMOvp|5e0}xI@?_
z))Foz4D1#Z9eJ09yo!W1Wvtz6l)hxWs0n8CbXw0W<(a=gS}N}v`#Iob&Ta^dW5yID
zOWBa`08L=SDgjMoztW}VBo;si$H{DZXXs30JqLnw11qCowQcN145V*o1NH-u$*gES
zn8hM{M}jAt{m~cM92QG)Ui;V|6m6Z)!YHEPDAUmqY5^;t8KaQRZV$6Avl--QyTX?B
zgS28cKNGn-%x)nXr-Y?sp#pbVyI&wWogbnYoebWs8m4XIA>^ao&VPCU&P-kySr<aH
zc;z6J?%*kHknH3)DGcxo&)fq<F~9K*@F^nRtB9^B`b+^WRlGtG{_Diu8t7dwKBcgw
zG;zN>XdA>w?Sb1Uj-i{ho5Zc*VA(9*r6$=T>f>PVRxy@NW0pvb+R*wpPO_yv<5Eda
z^XxLoel=`bE)|m}bA@#O5^Rc>4o!gUl~UhhC{(0j6vVtrihP2?1Zg;h&nHSr!=X1x
z%Ar-pJb76F)n4vB33|87_c|fBOSYxScdz`m6EtMYP9GThf36(A6FdjyDo<FECqG;c
z)+6#Ax=Zj<{_ZeXW3`n=Xv)ymY=puS+Ht3mJFVT72rDjWPkEbHfRFh1U!u+xy!l~R
zS;f!NZ2p2LWT36z@SfymiWa{pp>+WM)r|Rp-j3*+n~Nstmt7ai`|qM4cK6P$P%_}%
zZ&2d#p3c?>PFf0^JT2-&`XDa~RT$BF0)&qAHQ@KC&UD5%`aPYzd0#$=-(&iCfXC+t
zy8k=TqccALQtNwY58E~d_J>#Q2Tw#*G0G!nb{_x*^H^I1dtsaCMblF>i=f3^40EUL
z)&jPg4s$Zt#?t`oX7g`=WgmM<M__rZCAnITvsHUgSiowvKyrb7p!T`SR@0vGHghB2
zY$<zeiCj4=>w${CV5vpGq5VA?gE*Iua0PGyA3M{$WT_cIx9NIyZHAWUJ%{#}Q*h}U
zb1aLQ2`gT+=4~P79a}?p4RM9?B;cRe%OkL9HXqUtg>(7SufQ3_3m!sJG`|}QMKL^_
zUQxW9XXioi3howZ55zX!D-78K{K|bn{cei5*Cv!)<zWesag84?fyC?lZDX{@4c>7!
zKsR|IIg20g(F4HwkVkby?lI3xg<WObI|`hYyfuw4Px#SBXxumaR6j_6%b%se*oC4)
zZP*pLSge~3*~`Q!(^1J4qF*wA@nY@n=0UpFHCk;|GdTv5p0hTz=zYPaFNV&StTYQE
zUa?^E(Y$77*P5z5G{{u#%}LN1%fIgqv48MS*P%L|AG-|rN<N)-P73$FPVuiPybB$e
zuH{id;7R41sG-*JS>)8+%J+7K&~)DECm=HTxV<Rc&7WF>We<NY0C#}9(5c`--j74?
zaem?zq@3VQQqV?4Je&c3j(<gand|&H#fjbE{&c<kCja<5oqycoFI-{bZ9Xdp#A1GH
z27q_?huLVy5^haSxx3u09+G>!6}?pT89zv;d)53BEnJ`T#w)2wc>UwRz2ucGQTUpB
z(BZ^e{_RRw_>Lz%LvF6<N1-fHVk1YetQ8;9QE+6sxYP>3L!uM839g76=+08H_?%{h
z3UL_i@m`32o}hgYy`I4Cc~V{qj8UX({UJ16TGb!9gVHZ|!C54|E`hLn(y0^Rd?meV
z0n-*~#?qh_uNnObxg<@k?XYQ`<~4;PZ;sTIEJA6r98IS&Yvk|9?VKVflJ9=4>@5Mf
zMP5z^V(D@!#n)uW7r%z=?Xve#;C9Hz-y*kH9y1bF80FkRG-Zx#Ll+_T%Qad9kSj~Q
zVA?^s=^H4_lXw1v!ozYr-DJ&|BYSlP{-}JcE`Z16ZFHJ>O1^#-h(fu12-KgIgGa!a
zBDv`j;Qy4{=9@>mJ_0QQ`&QD{{D<}}f&bB_9^n0|d{EN=1KHs2Ll5wPt?7Vze9%Jb
zz?&a{^8D^2synD!9|`hcxgKm7vVhDSI<XCu{q!ImB|lr!rpjw+45~J)>^?*c7tR4T
zB4;8*kMw*9&e4-?VWW4O+K@BmMHxzbq9lCwO-ul%pIa*AjO|JxBmTIAgC$HGS_h2p
zor=#BE)SsbKj52IV4djL8BD)8W`i8Kkor>4xSc2up1&U@A?G}yCbVHCYB|aMDNLDM
zi;f_}?l__R*E3%DJmagrD4)Yt&?UhbcFh|y@)&|2pbGyQ-Rq8mrmycnXp87V2yMTp
zDfwTVZe&4*^DJ6!xK5#ot@rXLRPl{30UMc5F56Kh2l3f|Z&QdKcZoJBp;KtvJZaV>
ze4bXg1QLGh)C#|6Ma+Q}^VmgNo-AR*y8s=>YIQ{}ffYGJ`g(@YCG;n@&`AF8UF_-x
z7`Bi7+!U7WXW!FcpUdjeJNOPT4+m&D!OCgje3mWp1LtMt9}L<RmQI)K@3TXnKwHbR
zU0}&({uf8Go44!?y?gjK^wxvDJUSHsBX6_<mB{0T^v5u6^HFb5naE<E(hT?nG1UvQ
z6U6}9$0vzi{xBv@d{Gy<4Wbn->^6!Yau9-?F81n-xa2Hx1RWNf72D;5rATaU2f#V8
z-aO<kiifLF(M#f9nmjLymV3ZiE;c2P<T7b6U9QNGY@4GnGg6XDf!HNoq=25?((36b
z-78ftFwaAcO71~!v-@++PM8alW&vt_O*&1B!4m0FEEH8r6(3QTC(?ixsO}ui!u609
zqjCO96!;=dP(ZN2V>LlO)1X~*oIL;Wn)YS*LRM*hjih_lNt)mZC|#pDOXsDhG*z^F
zKBqbU8e*<$+LGh>mZlZWSS1>VGH{k^p2i}1r1^$o*()^buyT=~Y78+jZJ9iewoGf}
z+q76ule-;9Zj(H8Dw1uo7yv_e$#3X6%9V>gMS|yuT-hEfj>)?l!Kjn+sjd)nN3KUM
z=m)Yk4~6BjGtFyH<ndaFc_)wm9qK>I7IfDkN~_SQ5vNV3Q;e0`{&W{JK^sUx#K~H(
z15mg@`vpaaZ`NKdhLm*ecRJ8^Xy=;lU+mV_r&;BcHl8NS0<GgT*i@u7(kA$-wuJni
zH?%t1|KTnCjlfx=T}4N^_q7`<py{DDgiZviwfoD!@>08bC;;!ZbKfKPyG3Pd7&^~l
z(RtuvEFvj(Vv$9oGXN~MNaoc4S6D2hRYQ)&iup*6S(G+}rB^H>Jb}1wVW0!_dln_M
zI(lSrY7&G#u`tkyz%z?V)AG*3?>8uXZIMG;(~lNw9s@AP@*OQ7qAc_22qD^1pq<fj
z%PP37HCrr2(>QK9p91$H_gfx12;gDM)zx4<Y8g+lRE3te=#cxIrF&Q8{<LgKfn_%>
zuh21IspUNCb7hwE8h}=1nQ;iX=awz#yy}%@bsU7fwVXpI5Fada8iF>v#v}*ScW#Y@
zR4ANZW9AN2;-*!hH(L8{q}65Gua#OYjtB8Cs|nA5D6`tV51J~iX01c6%BsaMsGn<n
z?mWJ=h1M_nAW^Ji$<Lc){eb4J6zi)Lbhh6501Xfs*1g7omStT+_pWwZk0sAiw)K;K
zDBN$o=vM%aShuA+kteMqN8bSOob{$%$X>G^NgLf_>n3y!;I6elxzS3kdv}F}e_0p5
zMlMD-<V(<Eb=@Ao!Z=-(4UAc#`?v|UU!@yCi<M-Z-*;fyp=&{7<8EE%I^>MHe0rlu
zzD~>r?vc)I8FDXln@sl~-syrHqjaAB+cwY?qu)Spd|Iksi*9Key8S)$`0z{bp5`@~
z)wugWH@Bqs6#5QIfms11QBV?kn9j_m9i*tsS<MjAW<ty9G{x3&{e-GDT(%RRTf~h+
zGua(AkpH#g2D-xa?Xgmbbo=%NK6?jW1=IN3_wo6+uY1aZP>JV76mV!KaQ05G6BvFl
zt>AxVKQzpLa+tlJ&*Z?6FnhNUzbQff!Qo-{gMJ>;*FG%N$Ist8+}|h2-qmG*ovY8}
zvEJ?>W2XfAdk+p77yhfyWah6FHQ@D?s+zoA7kih`(7*scpYVW?;4u5aL)<$!xlZx*
z|G}+Sd!Nuyd)JWQaFgs_et`j@VgB}^fm6l@fK$0$pZ97U<l`3-=G@WSu|56g<lxl7
zp{rvDM`tHz`|yyEz%V7RHm}nIToVF<{e}O3T@C&V^{K7ws>28U7ZlY|Zr9~j|1Cu|
zCfNH-4zddl3HG=1_wfy|51%k4$k%>qXMek(w&OzWC!izQ`v!!E3IAdDQ+uC>{aF90
z0e=2r_F>^c9i0Aegeqb6dAI-X23u2?H&n(o;2nDWrww7mV>nx~ZKAPv)C8~5Xog{O
zVoc&13`}r9;rahgnb??*VK<dCjd@pgU(qz-N$i7?+JrY{^Od8NEKwdd;oq?orA1TT
z$G`JuWCmjzT|W%~vMRIFXG$h0hJG50zbSuXcA6<oKV!Oo#u!0qHcX=%Mgk?{`KH(%
zD^oqino3lzuB9<k5*v8ixcUSS^bZ~z5Ila+wB7;ZLc)wM{lvInWBvs(ps{i**s7H>
zr&_FIoLw!h>!uh6iyC7`2kFgW<+Pt@XS91J74}ye#&Js}p;XgWDXy^A7@K^r3E8L&
z-y*lM>^<1s)w}1AL5_-kp{Aj+tW*<{A04$tR-(3OXDT5sHCh_kR_)to(Yn<ZM%`*l
z-!!HE&oyj~2`)9})iOH&T*KQ_aZ0qRYmDDqqqw%ROcK8`#vH0~&P59M4+~d9npxL2
z1~IE{Un(}MbhVVE3u0?y#lNhc4mWB-tnAt<pSo+B8h=c*;thKLr{BB1o4@ar@rwHp
z48jqgEZQ35_E?3zZ_syeFYljR`VZ~ZxQm17XQ(j9)z#bG)x${{<7ibUy6H}9W7D0w
z0X39MM>KVn_06@l6^DTqR?^_1g9j>}XSl5~FIV?0%C@VclbxfpgG1}aj*jg+w0CTb
zk=e<iv!fIGlyb&Jf9XraCI~Kii)g->x#+vN=(ID9JA3MDFvY@6KTvUS)3;J`UG>e4
zUT*pr#-fZRz4Y~%jR!XW|Ni5ll=aqo7>D=KPp`q^luMraqCU03@TD+7sEPTLCM-4Y
z0d4=DA1H*H^9@b>o&x>?z~4Uxm{~SRpVipW&)3J<XRNc2gG1*oj!r%f9i2LN@pJO)
z<mc$?<m}wpxPP#|wNB~eqhFxh9i#VD4*KYa+u#UCsBuLQqLAY3Oo&lh`{HjpmMT+y
z^^Ncpt@PD@ZBrr$?TC)cI1ZHFGoJO;@3V9~j}uq!EC`P%Z6ye=&3Ro-<XZ}YEv2A4
zQrcV)dPL_0>hb><#+*RIiEkqjG$U|q{!UVg#l%BOv6H|JD1l>6$2wBrUkC!c-vWnh
ztf~c$M!H8Sq8IQwN`d2GEr(KslHH^fjr57q#)3fWXx>y17E=oSn<<4|M<{KDCBsdf
zg1ey)TH9g>;r@cqm{Ksfne%-qMa2Tm`B0<HRzpKkxv<U9Qi<DUn4vt{YG|yyAEU3W
zIBqx8Hrj4Cbg^U+%21=hgGDJDC`ndcP?Dzf$~JiL3?F4>wqX#ufTPjyFXer<!N7O>
zDEb^jOZ>?=L0F-jr}F+eD8K2WjHYsU#sxREJekVNeU$A~j+>{#S+%^J%HR7aAE`VM
zZQ4aG@3zliV3Oj#&+s+kKmRU{rDAJkH5J#u3TmLreUpl7Diu^r0q0(d%YH*08|s_L
znSO9RMW}7!t_9bosoQ=go&1M1>wl4M|3fnVFVb_68kz*Q*aZ?jH9b^Sf~~I}PFq39
z$Nz9K38=1Mp;YZR{7X|4-p-C{6WZp&=;n%DE{yK`PjMg>M<_E<jAR26e$iJsn~V0T
z-$)SlDu+*?ovjam>zwk{0g%gsl->snEm^1%ge*Yulsr%lP$DU%lnhdI2Mu5A+$QOT
zf#{iJ*%+njfT01qpo}8QirIPrJ;p@wRVmMvZA8fh1y{UHl(CBE5reJNNf6pAJ_ilW
zbVujvg)U~;I1@~B091RG`u^Xj6I5zBsJ1G#W0YQKY{pJhYz`Z2nX@wbprNI12q>S8
z2~=@y@H{S7aS@=dHRFO+YBs2zD%EzLUKnGhhMK6%Qn{6fibQ~d<6TolCaXAW*gjFk
zWz5$LF=kx2a`+gk31YEQl80(`jD|sYn5f;Rs?ed|{9Tce3;wCdG!vCi`bMou1W2E2
zGF=5O2k@GzGYwP=vqcdmDhpH&9D%JF3-!V@+$<o4vs7F{KS5}un$vu>UI;bgW~;bt
zWmG<WjcfEmTpTmuephkdq%$E%)z{qKAWSpYF-pa4Qa%ta8I;-GRekeST#LI*n4#*k
z4K@f_W_>X#b?rSSj8vr-gcyWSv($yE)b~ooQAq6;Y7lV0(PT}miW^_SgpW$qQ8eoN
z>A+z~q&hBEss4z)t)=P=oNo}k%sS&#>h#x4=&n+aMjM0)X6iDPn*D|e8&r$hEiee#
zW{Xy+)KPDl5UyhHgPLc?u2iY#ah@El?4TZ<w#XpdF@M#oRI1lUCU~ooqZUK2S#qLE
zHG=A_V#`5|Gh>rYR92xJIDwXkSZWa9iZa!8jf#6OaiN`Rk?qQVYO_|Qw!%SoLse>&
z0;*Z+I+fbnf`5Jj%M%Qy*^OE;O{Io|THh==@t;=Qs8SbOa&#%v(;J=yd(E}ktWvFU
z4|ah{m68p@Dl>JfQbi9wi1DgX$sj&88<n9#+vvDpr>c!jF$nPQnyR~9rT&cL?VT#M
zW-4ZXGd4@5S{k@uP}SC4ZxBE?VRxFSte#?b294MplnLfW+^yp173XGL?52NkdsS*}
zP|X8XGN^c-O;WQ}svD@iO*;9-O-k<qLrZxfik|6|$pwa{tep~HfT1}8mw)#thYJkN
tn4?mP5;jfI6=K-ky;*TC#IP$VqmX4?lzEhFR<<G09Nl6NN=!rb{{Tg(8%zKI

delta 135235
zcmZU*2S5~8*FHY8yR%cb?}}Iu6npQzM2%fzjT$xf7HgtWlW5kC2v}G}#0G+h1+gH_
z3Zf_q7OIL^uplbf5JkoRb2j<j_xt`olbt)~+;g6D?wvcgoO_4B9X(#|=&{M2{c_A>
zv|3%IZxzQfbzN6ee@nN78U8bp-kDUE9-k*_YIU4+YDU$+PMt_pzg5*ax$-CzwPZs3
z3F?{+JeJJ(R#x$iIk#kn(DqEP<!6>huX5(<9XGW$Rz+96P^)q;1-ausYW|wv+u^~F
zaWvx%j-|ZLuC1+RJXUD5%%~eIqcH#XpUi5R;WEQkY-1R8eU}EvWjC!+GwOzw`{G_^
zg)wbKhP|;tWYlddk0q9h`_8Ur*uSoW)!ucUlf_R?6BzdRES^yhth|y~8t#5&C{`S>
zgZG2$Rws}5Y^`G0j=ecXJ-u=Su>@}aEog@MfHl+gl#|7~mhcSw@Un(cudVL%=vftH
zuX7`h*pFAVj5^qjTw&ioh1Yv)kPmE~U67A)BjfC>42e<4)gYs6o!>X981-d0GRH<n
z3XD3n2H9bs^#N$MtCMf(=7<!k+qsuAqb{s6nxz8pO=`fi?XsHDSk29y8r@_@Q`yoP
z_u_2Guv^-5jK<wEm@?aRkr<7qbu!)mGJ<6^jVz1k{%JApn_0baUnhi=*1uyIO*_j@
z%G^>2#7@>Ix(}Oc2hqb?lZ5mR2=%cwp?jZSwTxz<wFBM1Z7eXFp|*i^Z}HPIoUL*a
zDOVaVGh8Ltbh`J40j{d+9lGD$7c$kVpq>~uX(ad_u5amn-Ux}|YF4SB`{C1AhO6r;
zu~R^J8B`2cuSz8{5c38ZE!}$2eLy9i;ab(8s$mD5!F}f%PJVBL!f;*Oo&1HJA>aES
z{-t!0;rjf;&;CQra6@W1Yue#xB)Qo)Kh!X&SVlX%?@&g2+Y|{{Ml~#xW3+dighu7F
z2gF?`A*g1p0+Ht=6o%c}oM*K6)Tt_lu^P3Ho9*VAQ3N)Wz@GdIHsoiP(LVhbtW#qU
z&;A7)X3>Ev{2#Ohj%=xgdD;|_(Y{kp0ZwCgwYHr7(@{lksy~#eX0#P<<e#GY(J@kP
zR)6(anbE3Qw`2{&xGTyi4WnT*alf2ZCI_SP*vBA_vdRX>QMumOKuC)$J$ON-+`J|+
z68jIBvKKkBGsmb>x)kw@;>@wCl*7o;Iddwjl=U?@M(@n2rcz>%V_*|daCen*$<ay~
zXTNt=Vzee!y$zl_-w^&>peM_8<`_n|56zv?U5H>A{C7yLFnp5Q0~xZQaev7&&0SmZ
z|L6#HHT4B%8R>j9z<u43wRi<}&pcI(O1H%q{Q<*vbw?Q*sYgJlg~n+~Y#Q*<&NAmn
zP5Xk!_3bw_58dJ_TBvO(#7n4a?u&-3i)xP6z_7P}P%&a#HC}e64ry7diJccE3e0RR
zo_^>%mJz!sR8@>>=}HjaISGww@D30?orIuD8Ne}OA19%xZVa%4>hGkCsuL)tILJap
zx2on;7Z`Dfld!2)7vU)kcM_FU36jEyBb|hcs)bs^h(9@r%BopLkrBr^30H>Qw;I$0
z^$minCr(TFRc3e;QkA$8rI_xt$*AmCzK7H-C#6x%UxKW8PC`(98w{fhorI!N%?9y@
zlQ61=orP~porG1@@+mx6=_D$vA_qcjjgzRR>V|eIu5%LZs=o7(<KrYe88*K^D1Y@5
zts9)HECycgB{Or$xexoHv)w7isN5bq4(VI8_GTnTjBpmq%CK$A;o}jt1=6Vh=<Urp
z=FxvNPyScaY-nMB%A%^0ojj|m!7@N!b`q5tw##^w`>Og+s8*ht%Q5xD8^&g6ZYtA0
zxOU5(?ip3TCTd2^tU(W0qbi7iN_LH_s8Dy+vlNKs)}WWcli{u4v1!eaU#u<$B)<fF
z-f_W@!WKAujMZ6-<AAZQ;n%5nO_b)!IuY2q7moYJI&5=?)>O+LdsD+y)_E$$$kEQ5
z^b4b_Q?()P8P&7-ETgOIBm`B`6`s-6t4jJtRroWB(bca?UAdJJ4}({^??4q})K^ie
zNPw9+h0#~D4s)VRbrl(Xbt}oDO5Ty|Sr0W+Szk+;09i+bN!QRRQ^)3%QH6}uGWxnU
zYR*Pg$EGZ!ujkCMGOg?WsdYRs)nJqT%{6=fhBo!y#4s^HNyJZ61VUYc3uB01u4N4M
z&7ViBnNMKcM)qS8Va)##NlfDyLj&^<j+y4FH3o=~Z{$`7Ljpn8kQt^neojcnFu)ON
zu4y@&C^8<FXJ8u&Z{pI_<(wneT#YStl$vYvKX(<Fw&ryX4@;%NM<=q3p;M)QUdV<=
zM8?qBSptn}Co0>}#Yy1xn**0>JPOh>E(Q*c)%flYiLn`|7R0wO(-y^L486qO4lheh
zp<O!982VK9avZa?wmU5hF#lsgyeBb+fhN+!3qh6I{-&#jX{R#Qm**H5W(Iy8=!Rik
zDZ{-T&$z-~Eao&x_-Tkx*TRKy=HL6GapvbB@6mtq>ruY@(pCb~XpH@!ilKI<cUQM#
znZ`aVHBM6H-gbzFX>z*?<0J(GSyM?|V4mm%tgAy0h~Ga38xx>M#yW{HbxL5Fp2+C;
zKbefjb@a-vey><&EO?Xt%h&!WGHz98O^}&|VE*}^4C%*tXtJJCsN<Wpk-C%A(9y)!
zsPUC7o>7g_znQLLsIF8-l{X6X1zIZozkV>LacDiN$x^bz%T`b5G*OLCR9fSRwYh1h
z*+oXR#&Or?Zf}N%rP?6XUyN)cPbk}gu;)K0(#ZkHIqXuiyOyCxpfajS=qv=1|0~3Y
zvWzN5cW*ShZl^y22^B!#ISGA7RU+-V4)p|GXjA@QA<<j0V+g?$)Z_QBR7wuUinF?L
z%>PJ91l1S<E&n6b@kAYXy<74*u3~zFJCJhdX)~&)+hoQ#r8+$XjY?CQXN*&;_XmOg
zm2f)scq?LfuIg++r%f2fT;m*HD%IeK-`?TwQkCuD=;ZPb?e3W1Qps{`HqZP?*sSwe
zu=OfsIlNt(u!kLSE{z0w5^Vb_`y4M_stZ(CY?oR$9j40F*>R4hm76;2ogGqXr(;@W
zH-YM%9a-su!?&_qeX4nOOr^=qF{B!KYR7%>iVnh0GltAbRH^I~*IykOl|9))$H&Um
z1*#l&E?CuFJ*=m1@Qi6NKWwtZbnAl#YU<0+a}0Go)IGM5$jk!-j{-71RVX$;L}2!S
zlZao<t_ReN0XMb2wh-_hdQuCj<yjpQiC(Sg=`ocm99^r_V0$~pSLw;lbA(lC-FEYG
zj1fOskf)4LGkaAQni?zxt#&r|N|`ZeiT`l@|I5AYFjjT7SEZ+$3@-hvgde-}CMbdY
z=mkGin-?-wsht%5ADPnsM}``lVs*m&i{lFF|KRAU<u?0Q216liwIA?5LT*lD^NoXa
zDkicrwPy9^g<7U6HLS`1>Wp&g>~g9&9#*a766}1zHZQCOV5S*<MwLdz>~-j?)oMZ|
z_y=@$H5%Qz;MZU#v*~}UH2NPEf5-T0wQBq?70;PdmN08tIbWE~vz)MAj*w~||BuYl
zmj7GkZ^y%G9v%PxIFsA_E8{{#%jAKboMoNjveZpsCjUf(g=+IJP8(AlovVAWT^-}A
z*RuZ?Ww;9sex3fcG|c6@9URlCcUvdQ0GH)GWTw;TUNo9-?qeLL6PO;=opXfEV;Mbl
zRuk#D;-4>m?9Omd&d2gk<qUVCd3I{yL>ufx^Bn%2z*Gj@04H3%>dwi^<_X4qn?<Ib
z!_|#k?C4gD9CfSJ=D&_EWWG1Rpt}n!wZX;NoXJkD95-}|Qa5LV>}5vQV@I4@I|Hds
zKt9uF5_knCzPaf**4Lr)?8>@1270<U#(D~l*`6)I3-)Yb0SNwKar57+<B4b8CN(rH
zqqbN%mzWGJ6WwfFrE?Q-Q~e)FwL|5?Sqpx_QnaeTRch(zP`irfei2LEnyyYLwa9VO
z2}}^wikj29)x=s^sKQk;IF{6I@qOA%tSQx9t2-q%|H$uU-MA{p5+K*C#y|XjGa?M`
z|IpkTW9AvG5Y_ux53a^uM@j9uDvwyl_&ROa5srX5&3e_FjFslUx*D!>kvG6<u$=Zm
zElk7>I^49vji7K^mnC=?1c`GSV}yrw<bPa9)imd7Ty!XPJ>=IipwuP<r`_*pSGR^e
z%7|qo^V>QNuH#DRzI74SdQ8?e;tU^$We+pn4NFj_-d8L#nducI<D=tno&Sige+Fa0
z$<)C6$1%Ik3%JG=lf2-(?%PcFEg}hR=n}dfu7Y(X6OKha$1Jn|L<$`rVHwGoa!EAe
zFu{clAY&P3GH|&E<&J1aoULlQ|C&f{iPK5`IaV1QQ-B#1$27p0!7(m)I2<!gM+=i{
z^XY!qWs<qooe(a&lJ1>#Bsq46oxFHZNWO0r=sNd3iT=$}9SlR?h_VKgsDC%&%qt+!
z0lowg_<<y+-Xoc=U5ImQ2;F;UlgSASNPhVz!Vhdrxg8JFy|q1E@692ZnjtDX5|&o-
zOzb3r>+_L(EZKr(IJ0&aU5}R#N7_be9lMfRLL70*kC0p9@1(ozBHeHQi=3<BETxwZ
z>GpJ1`z$LVTc(jr`(Fql$)B!$pGyoDSrZ?Sr|vnV@JAjAb*o9nY_I7$%t*PKPh@fq
zru-bUGMwNR?546Nx)Z-qCDLm7hDtfO6FG6H1LdZ^AkNl}BoiA<_`hEy%%`=8-)A#$
z>`X3Z+%Wl=vSSm;Kv`enJeBFnOs4CXKzh2ibELfg4V75;2bpZRoN~jvkV9=6(zQ_%
zNj}OW^DZL^t>breZyiR(sQQZJ9fyct|0TI)pZ$>(^4CyCBgB)?o>M4ecL@nG{m4u@
z)`w`%?}@WwE8RD<5L{V0$@gqX4z2!5X4X-dfC>9XGVOMgj4+wp8sV(=3x33Tw1SGd
zcN3v)w?84#0r3RUb1pftJBSo=XOLTe>gcL>zBWIfqTKE+2x648G>r}u1b2!IA8A4N
zlRFcR(UTBDLy14nm+tHSO4pHU%3Vj*&dhf@`fC*|@;T;ob23wes0+u$zoGk%&&bEq
z&T>rqN;2My$-Lf$%=o4gbnO!)nS7LTGv5*D@<6J&`ZwwN>>3&KbM_713ZdQfAj#Rq
z#1G#>GP5FhYX4oWWOx-Oxp?ETqTra5{RnP0R&=QF1bXTtejt-)Uz7P*=kq&Omt<ND
zAt3fJ-EaAet~KhB%-dkP_RJu(t#(2lxt|cWIp2umSp1^5n5(At-?tKpmi<Pe2}ekD
z<2(`_=0%+B4g|W-ojATtDfjtWa_GxkdT{sf!^>HX;51lAVjOu#Xb*dmRu^>7cq5#z
zXhc5oZ`w$*PgT15l3hFFFc47Ae!3PE6I_QrRPNe!h~q$%3a`yWs=ECc$x*T02s(qO
z+z}W*(asyty~&U6Ti+w6JFAJ~d6Vk3rj73Z6bYgBGUA-vPxv?P(Y-y@*;#hEPRic#
z<nOC7be~m9+4p0~q^ce9t2sNI@IQ!ur45;>Z6W@R;lw#>qwC+($lXCcbhTheLsw=d
z{_Qhl{+#nsHt9#^b0w;+y7pa^>}^D>It!^}UhBzx=cB|?5KZBj&%4NpVUNjV1%@@q
zW2wn8@7*c4_7yUaJCv>uu`=hF4^AiI63OJ<3X++-pRTrtgq%>FWNh(d7t1Ch8nq@*
z8$2dfoJh|m|1c@Pl<1lzkxXVjIWg}5N&0W1atD2)`!Fn+F~AHVN$W4<7Qdb33%ikw
z$tg42mt?j{lsm2u6=3#e%KhV_MD1UAO5VMdNT~KJ5_<5S?kC?OlT%s~oX1~OzC*W(
zKMoTvj_GY8lLHTu6E$0q4AY9PL&j2WbT2Avol&Iay@>d!tw~owxD}(oIO24htEKio
z=^X)S4-)IxucU@e3tSsrBIOU`$kUPE=)PzS8EdqbO7MCg$xr-~>TEz;GC5`o-K$p-
zns=o0A@(AiTTaeJ=lk;RD&>BRCEYC>p=D>Ry$Lk@C>hw=o~~L03B@Da#WA%8(DnHh
zGH|gQ!Obcp^HW?%Qk+CUjqu}`onDlC(m6|*F_}0GD#(fCg;b+0Kay6svww6Hk?zb`
z!n7BjCy2_4q~LLv%4$1D**WoKm<c0(mJ=xB9T{j_g-ZE&Ac6XNlf3&Pl3$9TG-gN6
z8Nl{qWH@sR>9(k#>#&+6d11EGi5$X-9!pwL_K}n^;V**wr8+?`8b``g*AU0Nhm^--
z8wXubUuS8s!ND<08WO*%bAY+zLvR<z63&N*bS>CIW~N>uei{~ec<No~nzx*E$F3*7
z+pmOBW22p*o4OOR0I_FmM|2|2gtl~l2GJ2MGj+XyYY?8CmKmE!Ze0mN=$t9Ih43`f
z))NtXrvGp%{qM)9O242p)-qjt66Un$RJ%u=t)cNN75MYYsgMpt(t+~|?O)5B6G`pu
zS`uBaru%a>$;?7G63uZT=$O$6%`@wNqjDtGBgqL0T?akWg8%3f$^TeH_v!)U&{u@}
zwM^z<a(dnXa`eUk%8iJn8Vdc4R>t^YHih@!5<#M&lj(V!NG1alopagau2fyK(3feM
z6ogVaX7MOeZr*{e<z-YuwaUneNVIJ&vkJ3eEmQjkGPyFGv}`xY<oCC!+`gTu#3jyI
zLZ4++uqNYCFgvr<+4AL6RPDwbMAgvhIB`)d9MPxJ%+PR}hik@y0+i9*w>x6^B;o3{
z5+HScBC>%~uE(xFa6kNb9OOo*Y;f|&&D(K5(r^OUqehPe%IFoH!2gM(CObKJr-1i=
zx`9Tc`385CaIr-Lv-Z&LP*}xo{T>ebvTO>H09O3~%x&z9uP8?#`}G~D?d-IjNP^g6
zJX&rC+ixLU+QnvQ@eFsf8Q;VCJ?skvKe%9a`cxPWVVB&6<X-lt32-%(9e;${Ul_Yd
z26rFpIT74&cC{Z&>}Qi`e2ievPDB|Fu$>11`ygBX3lt8qI~*`^n2j$4b|h=3?)?b+
z_B7O^*q|gR9A!^d2X&0?fM>uRXY-ds?*v<_Kp~oK76|B*?2tm5f5)(gXf_wiCQ?@(
z$F@2Mw0QRC7*Gjp=3StjV#NzEf0_-71@jD>LjCYr*7X8F&#_Hdpq*#8QHPbt*0~JH
zBsOjr%wJ#^9YJ!Foq>2icZ(g`4U!pbrP-+KO!iVFkNVGIv+hA7n_Y4pp5De*6R_{F
z4=zISE<2d|zdZI+V<ZpR1J&`U3fPl03wy%0+yRAW?CqKGu#h#@0`n!iFBE#O*aH?6
zqJ*th4zSnkuu8D-hPD0;$+v79GxFZCCKaBD{XM%Z8)PY4J_?y1*e*Xqqm2E)gZYuY
z-UgnQvu>Y({h3{Z{RQp|+dc!5-`I`xd{?Lz(|l{CYEu9_^ifT&^=}KV(}wz)Ru}p~
zWo{kno9A`D4$S%Qr@@zBzj)#PH+@%x4V}%o=DL;;X<AGRxMtguacv&e23aj8wS=*j
z52^76v)3q2j@GZ$oC$|HZr>NYVA{8*aL*q%{gcOO^1esGw9$P5!dG;FHQ`J;IHFlV
zOpM+gkJEGDdcDE@7`*?h*p{@WT+L=+pwO;k*COoBd9xib@6)blD`<x0!>(?LcY8P6
zXbI5vutBdOQpOe!fXiRmRy4_6qY4-g$@QwF2`JcBRe3t7?W+Bo;rAZZe1CWtrE0$j
zdgoN)X6Rj21?v%o!T5_eTt>oG$-s67=h18m;F_Af!0+5nf#k58*jnf2#Grr1+t|zl
zE`+nEXF&EedwVYmna;*OLI?Do)t&yg3Z%xr0MK|0gNU|a%M4Ulqlp+?w2dkHr)^Rv
zKwwl&XU<*7Xzk6a^+(Z~uf~?1w#AqRsHc{@%Ta_@0Vh!Lt$!E}KiX`+4nNvfI*EE}
zckl|X?Z43UrbFX$nD6moBXaxAjDcfA-z<mxIDI3?%sBHiaDMe~j@%`MCh%9V?z>UA
zb?jg3fbC!}RFm=kZDR|~5ZTLa!u}-Q=J|~P8pBqMgxhhf)BAYV>3#z1^#2s=EWl~j
zS%Nbxd96)iodvnTQc0XoSt_Lw!dCnYRpFXif@{^}RCw(Xmkm#A_gaDatZT33j*4uY
zKML38tNfwa(z>4tcxVqeok!AR?3zX~jGoVD1Fr9OT4)VYBTC2(^IL~K0D6EfLJ1(N
zM>WKKt*tbq*T1|I*VevWV79B<W$^ocIg8>AQ_~x{oE=T`@fB>T9s9W4O7{H(kb&%L
z?2n*Vz2Xhmg4q2uE7;3+#-=Lz%5oM-7^`5ALtke)0=+2qJ{mpxI!krr#j)Fp;afZ#
z7zdODwmk&`lG*m_p>UBsmH`hhu}iX0luR~@-tsI~%%t^SHhaA@^q;an(h}ks>x-Q>
zbSTwYLi7V$lnwndc3o!}{K$4c4CY$Z{Hl=jQl)ADvrg5#J(vNil5R-0sjBS*SfDD%
z8zSMV+_M1Nuc{k>ya?4FBfyMNg|CB1tZMQK4W56TYDF4MTvBPU?Zc(0cI!Z0S8b-i
zRF0}@TQKjbeCe6xtM-uoBUO49iv3ho6Js#<LRD-;b$w99{f@FMS4%XdU!!hZ4+_5O
zjfWuVr~WM$B7y3LFJX7P`fu!_b7ATOs2MxAPwhJf8pqVX+=r#(>Txpwny8MP0sSO(
zyoCKtdc^KAy`fa=)GOS3?rx2Wu3g9b-@NVtm=JM2ZbidZ&v_Sd-#hFjuG6=x|Lt+A
z6fHyf>#MMBz%_bXhHKL->@IUH?9)8}*!na@MA}WotbyxTG83FGEmX+<u4oJ#?%BZy
z_XDIFxDJ1`1J7aXd|Kd5>B7VD*{;JNGcUgk2*251qYS6CFKJ$UT08F;q|RuE4nkJ4
zwhI+3Ra;?0-YxBFKiImhwXbLdr?2tWwGe&BU+4&#72-k`8k@xdLm?WiUvLJ@Q~Fdh
z>~A(M9SUlT@#(pL+x`)Dv>p(**}9QP?y*^IAePTQ!{CMyYf&38AF($h&`=84?I)0I
zQ5nl%Y^!SAC7OS1Q~iSNI5e0a<B<fZI2-}tcBpb|!i8O`wh9WjTa}N^Q7%~3eKeRM
zs%A6^4pn9Th`caWyFKvoq-sYJk{H!3TBF}obw3U-ZmCWcptdqq!#_YTOC{t$FGp2M
z!M9vhrLJJw@2Hwaz~Eig-_%0ysiKbKG3TqeT!=nUg)9K|P_>3)a0RNqUI2ZpszG7W
zr>Y4&%s*3&9S7!f)em!lR-`&<!3h0Qb+tJZUa9^%1?c7KO*mG-tx#`!h-8&|CXQWk
ztJObFhx%H(`j1cW#!EepCi4;M8P&i&pe~#a{afnBS3qT`BdP%=OYQp#wU@2_?Hri7
z>IJk2y{$GZfHQa1nzl&t)D>9LartVOX;8nf-kOHwk$Tw@R6>EeUj(Qp>d%9q_f(yD
z1z?40yUz!Z&(&3@!>JeQWEzNGs(ETE#p+J`L6xW<i%8z6e{KSpx9U0lAo*UsiI$V4
z>UB||%G7H<qi7%12WV6%SF0(E@mZ~T1m;(DunQzB)T4hz0as|wTtIPGY8L$g<{HgT
zJ9ewMwVK2GU~rvgJq`$P-kP$dD20zEAQ=XIHH+|?aT_!TR8ZWgF&08`v!=~)Ncw96
zx54}t&Gveb+^VV32YK5xVkablnr9T3*r7Rl10p*$-6*!VTQlJ{yx60uPh|<w1bw9!
za<690d0_9;Y}y1b!ZjbL)+01Mx1%rzG|B6saY%DzBs30d0<fLT9nq9{04++>mLe&~
zG%q?s@3>}McQB(hojEjtlbS0fP(V*S7tX|Mei#a{Q<}?>P(Q8d+y|vTtEpUHK>v46
zGdB?>Ow@G2(t%6T6ywMdm#j&y3@<KfTDL`#qN(`+%*&dTEJ&tmB3r`ktD3g8kfdp<
z4}wU#rd}Eh-p~l$fpSwbHxSNbXxdYBHB)mb4+YHDsCxn>M-$-*h1;4`bkuh4jwYD`
z(|MXmiuc~rm_h(^Uo)c;k_Vb*dmvh%DSrW&$C~QFNS<o!eUSG|6L23Uo@;V?fLWyZ
z_7TY|P4||tRIFJ!4^{G7!_q?Tjb^zwpx<eB7(l((Jk3Ym2Td4`WpMT~jolAupEN!r
zky);Zx&_cLns{H-*H=x@Imj&MTF|0n1-I)t6jyQYW}*^Sa|T+It>ruxqb|L;TGe6K
zoBJF4$=rHQqX5O1J5&Xdeq7Y=u&|Mv{}vWDadl=u&!5{l1x$yXyKogU0o>!EFtLrR
zrH1}??k|dH2XQTCBH78U?F7+XT#duf-^1yXQNh97h~CiK%eADPlThx@d(?usL<(hw
zbLyi&IlzUCf~A9;xjrNhbB^PXjN}^98a;};7KySP<?NpHcAVg98-X3o`O;_^!=1u`
zE-sey_yoK0981yR1nwRMeNS^ku)ocn;kqt@{yFYqDAdn$gJ|-V!;RhxDwhjP0(F-w
z{Q-J;+^`C`md_>rh`jrpbRNuy+|_WXKjLETv@7tK+n|QuPq^Wwka@;MwShB*-0K(c
zbh-9?0g@Hk!$ZJar5&>xKCRZ~(1L%hc4!YMcxfln=;5s$m;p=cwXFsM+fVzAqGubl
zYbk!US-X!$HGl1b3NW{7e`*Yc0PTof^!^2ECqG9;ZP!k|0GS=yY9_$!)XsVUyEn9^
z??K(v8Wuq^Q~Tf*s4T61G4gV>bvr;IS3Bt-s5{!vG;_bJoiPBC_p}Q;fy&o*907kH
zXnky;9%@}FFjS!3;t8J~YagDc`14b((ifo5w1GJB#68!JJ%PF?(vI_n;!ExI=@5OT
zZFd!xUTZ^W41S}na{(~#wd=E>SE^O6LGq(^?s|CfNqh7g^1f)FY(fdYYExYCB)@5!
zQ?O|{A0{JN$sesi-YUMek;cCxybp1s_-Y?u;ut@4JWL$teG`Bd&HE*xf=}{SXg?*E
zZ}bFI9ADD_y9s>1U4S{o$J7J!3}2%d)LH)9PslsZr%<#Yk^f9H*9*LT0z{JemK0FG
z#E%o;Qwrae;+^&@{I?L;P366)N4>^B83v6szOV-jUgt|G_J4zaydNUB_$UepWbj6M
z_E~&jTO`@MKh6Gg`2{aQ-R1{#sJy$pSOq9~d~=%E<@3Hc2+ZB*7fgn05Bb#-VfPWg
zhy(M9oo}=c<Wt@^9x%`O-Z@nH`~=!}e8vAU0?cB5P6LR(;a$$di?=*WV{0j|`V74f
ze83M7`NX?;L7|-QLXq6B{4<ItRPc4DpbnP{zl{fTg-}ZKlT|{87jSg7u;c`sSu5Dp
zDM-D9UG<^iE!=(%OX~#{mC0AwyaS4U!s!wu8-;NWNNy6|{tbP9p%^DtIEPS?jAW}Y
zXBB)35C-JJrzF9XUc3uJ^C3ts2`u)(xfJ0!g?v+mKPVh|RnXsup)_Hh{VPDzg>(}P
z-Vl`e;NBF{z6V-{koh;BL8kC@9FiO%mp0IHh1IkSxFc-&71(!$yAGJo7b;Fe@4is0
z38+WHo_)Y95WETciBOrP`V|`PgnFUy8YdgL=fZKCe7q3kXEgtRDYQv}OtDZp92zCU
zXdI5<-Uw}eK=KyA@cX^c-iS&l725Ry^P?cp?(HWbg(f|pg<=Xdei0%X0_>YGke0E_
z#g9WExl*ig1=K2W$rwPd5hvCG%35)K8kp<EQOC7-|GY)ZN_gWVKBZ3AS6uKFo^B8?
zZHE3v@hwHkHj5Y5g7O!8g#l)(c%d0Y0>p${up1~YJq(fUqK;M}JH_Z!fb9|&1c4bW
zj(-M`5OG>2s8CVdjdF&GlkULnaFIceX6N>c_bGI7K+O39(1W5&UzGQ-*o|gsk>bbN
zNTS3L3D`%)p7b7^5C`{w7tvymslbjA=YK>JD>hw%Cz360I}eoG;!)bSxg(Bv2=zR%
z=2ay3#Nj`}?tO9a2!K5hdtyb-*$c$)x<T==c=j^<ek%UG0*cSXMF{M1&qXthhDGAV
zUSPfwM|Xorv3M>X)Elt_;<DUZvEFT{zZVbD)<>yWx)XV2V&V%p`cb^!7bW{Frl!Ku
z7qQh+l&nG=bPAZ?M3+>kudqv30-&){`gR}KtEF5MGS^6nw3Xl`9lHaWb&`Jy6xT}=
zo<Pz^D*Ff#KgqrcA{(S{v`@N8noO;1vovBg@*L7Rn$vEP=Klq~0BJ{MP}`(6N1$+A
zDqjHR38@2hS0^R=#|Nmd7^#?|Cvnn<zu-l@l)edQr=-~(pmAFIcnf)Fr3qUBb58o6
z=C6rTP!KF7NrgV3lBGYJK;feFM>j~ONa<&hcUdyLM(I<fixhRaDus*$l`d7}!`^i%
zX%ZA}Nk{B|A~Qp3MP6h{8);7^TWZ@DmU5+O9(V?~rLlj*#9b-d9g=yH#}kO$mqMF>
zdLT&@YkVYy(aN<z%A)PbCsGp4WS&Zr3YAwV&8My3=aMD@C@-WhX~=si^`wAlv2<%3
zEmlh;|A|0*BN@&i^R0A?2J`olFFr5eN~ObyVRIiPjUSRv(g(!BxzAG22Y`N&exV6M
zh2*su)Hf-;3X&D_3ySBhlwVYX_d#-JTAu8XJN1M5E_u*Gi0qaVU&5JSxl3o&T)Z7}
z0PTK+%2R2M87BMDZdJJaoes%<IpGXEJs=Nl1nQtXl$HsH<<_)xij)%yVJS-POpCLl
za%Y+V9+w+Xi1mbQrbXdNdEsz~#K;#Lz;2xE?O4&*YEOtlq0h;G^+ncsc`U8llH_3&
z)4U)jgoC;yPq>VlNRj&-1$9LpN=+tJ?m(wOuE|f<fJ&1SBSBr4uhS&uhU`nD$Sqk-
zhXyj_Y<kvNa+46KXUq3Kftf2m_Xl-bu4Zox#k+Dt8ldy!O|;LMFIT1T@_pHU0*Vji
z!l!WNk({y|*pKA}L1<M^<YYQL@JwDq&8bix)Dh}MGD{uW3wiWiBwyvQLjYT&{EpL{
zoWIgy80yTS<nBW`w<tCH!u(dH;2k~k0A)E2q;uPp0~BlyR6^6Bv0X{TF&=J*vW~Xx
zb}GAE;l(b6#~FEUxAFrmdiN+N$(dkf?f~e8C`q26_9}%}VQHUYQ6mXg>ehyb2NWG0
zg*d2qQm1}RIimtIO$iv!qRUNJCR2mIuKZ2i>J8;x3nVv{>0glCQbzoVBtuzBikZp<
zHzZk#5$k;}TltKmO<ayrI2na_px9_P_M!5Z3nmngl^8m|Q>eV5*w}MrdL=N6l<T2X
zK?>UnuDw(|ay963UnwrDwXlKz-A_~SwdS-h(5ZF&1M0+cQX)!U+wUR#t@C0k%3jyA
z8~F9i{UB4{KN@%q8c?Xe;h#4l(<qu2Q;m&ue4xpQ_wcLfPuK$DniW=teDgAV%fhwz
zJ`b2Jw^NL{mA%VgsI@jthC-XvRG4pjPQrb=gC}uq-^Lek9kd0wc9czk>okLQQ99S7
zsA$($v{&2hAhpErX5WHL_ZM^~r^mdGknH(t8{F#OZYubrW?#eo^eW%M<dU?fD8Nc~
z9fiLA?Cg_PNQ2nF+d^&+JA4)(!`PcR)P;SHaupPgu(hA^P{;r4`A4x3^Wl9L!aHAn
z0PREj@x5vOuz}w}gWX2{6RkHk@!=F6+01{Yn5{owiKZV8K05?}TlfzYSlG(%^ray;
zfIsXC(QUlrEs{W93Pl-q@U3YXy_5g3C765obegpV^Ys-ZA^ZWVguQ$et=sqU+TWoN
z&bx=hwf+3D3&@M$*N#Ho0p8LD$wB_>1bA_XU$PK(5A)t`z>MU(<HRLRd8_E~RHFD&
z+Cn(W_xT-}$M_5bsN;MR#aU1A&n1|M=Ife~oa7TCP&+Yv;ymcZ@~+>&jN=#3fE3T$
zX-$y83)|t$DSq-%_<Nc!-wU74@Xu*_cb5Oi!l!e5;dL<WNqkkRs0;j?s^BK`F4>T|
z$j9~o^Ag{s2TY{!Zx6xm%lt_LYW52MR}2)d@-N20#5H~eZOEqahj7l4OXvS=1@-Iv
z`Mc1&!C$1WtZwp)CPL&EU+@MZS$rkJ%;qOQ17?n$j}%eDT)v!o(cAo7Pb7Ev*F7P6
zm(QjMP98s92he+b9+}VQ>k-U-e)UpR=>xu6Z#eUizt#e1kN73WkXOL>ehQSwe5?a`
zPxvJhQL?9eYAx7(#xJH-Pa*G0=SQCNc3TeWvWTyQPuaK^{1K}BmwZKUWWM50Q~_1Y
zw|N2cC47@TNM7@;Zv*rVzlNgrZ~5n);Ke(>EA7I*=id`(DL>@~41VBy(&@l5{sjd!
z%X$CDNIvsNt|702pOX&gZ+s6sZN)Da*5eRAX65U@!I?F}w_IR*366tE)(IsBfUXy0
zniBa4P3aVruTT+>JU?MV9Fh&fAgYp$LeC;ln}qy%z}zf!3kKycMAPW#5Of7FzeTu5
z%gL?6%sHU833-Q|OHN@N`L<ms!5L64L|C){$zEaJ9{3b0@HE{D6Q({!1?>}-QFj<F
z*qh;r?ia>$kc<!>HK4aus6?UBgF+t)h8+@G--J(xg#wz|L<*a#K>diI{S6{ff@fVY
zj|$~kwB>P3ke0y2aUnbfiYJ5~RHf0v=yd=+DJZl6jS>16qb_5GaTL*r6Wl2V7%wo<
zFrOeaH-mXfm_;*<(}I6%sGkv{a-ncm=ywq)=Y&uSD4rLNUIUdV{8j<UBw-Ft<RRoC
z*u0UMEGR#~sY}8Z+N)0y<_?F<Wnm9B<SRm*J1~(djG(ahRiWt{yj9l(Hwylx3Cr%n
zV7gG3JiIRSp>u~fgg-<iH-*Q8QKVbKi{pUK5Gtrc&J;QiK#{Tpui8lL*}|ofkjW8B
zXc>?ztfDhIw}s{#klYb!)2YY1!m@cl%M<37p`Pvum1%9AFErl>NAC-RY%u>oco_lg
zhk`eq)OaMcrXWp$kV5f|$3p&UNIns^D3E+A)S(H^Goj@XNEX_Kn3fQIE>uo|H$_6q
zEm(RXG^vfumqJroDZCOSI<8eLETEb#5!&EeTJE*rMbnWtLX~tVycL?x0_Z!T$5XiW
zUWl0l$x<PbdWe-`V>*<vP29a5l0o7)9JA(jh)+KuZ>MPQZ^g*COZ-ax+-~ts6X@>|
z|JnilV6o*4$b^UoS3qO0xZ41jP%)22#4xcZE${Y;mFc8HxEMMM$$l|(71SfdV|4*`
zKwRgG<e-=y1lJCU<1Zrbh?qp9LzLKY37k19esA9o@|alk8)S})LM_-mA*LJ#6)pDL
z34<ray*~pcMhv1oqge3}z1wkOONu?li&LqiNDxD{$U7z0YYFw!Vh5VsoDnC?flp^e
zmX0)>6a7jda$bBq6iK4kiN=E@vFmA?|6CA_BakGEdH3PWMezoW)tAI9>KIeR8{a|n
zve+RDidV#84N)bjVp1yF#Z@tsdfRK_FEo0miQf)GGF?Q33Jp;_MUm4RqQ_ZycvF1X
z5l`}#$o>ZC3~_uQz%s=dX*B+2iMg8~nk~+YgTWl}C)&@+6*tj2rrToXGFZAJ>X!iK
zu6TeBaOQ~(x1vn<#N0km$QQ$C=5b$)xd+JyVjtS2c_?n#2cI5`gD3*?M65^M##51h
z2a#vuxZ%(%6l=!O`}bUQ9RZmlQBCdgh1iH<A1}qlZ$P~gFVN0MvFPXu#S(E89fW%=
zj^-fpMr?5&WqK=yUxVa3@fMvbdM}=#U9D0vizeP5#J9hKStib^3x$v3pwXZ{i5aw)
zS1z8Z1262K#qTL7{YBh25_R%b%(?^p3Q>!bJXjZcje+^)l0U5gS4hKm0(7NxD-z6A
z(lJ`0ua@>5f#e#gCrwP&N*m?^#Y@_-7n19w6DLq?Zz=dP?5>vr%3#PxilzqPD^**L
zs`Rr<J9fd~25J2%Xl#^PQDkqEw3zlBHcPFtq3AC?o(55ebcyEU0n)_vu(VBT7KFS&
z={Jh_ZkLWeL=q(J{0YwNkWvYAr!=<;4DON!1R>ciy`X__kMx{sJ6M`L80sOCz40QD
zd!_pcFcB(gI|C+6Iz;P;ebSVHD0aBiq$}+1mm=uscZ9TT0H_1f0y?yMQ0hn1`a_bV
zH{3ofF<n7LO69bCIU;Re3}%#M9|OIk(nx$r&mEKAw}swuDLw^`o{+xUX_^x)eV~SM
zQmTQkZn6G7L?Osn=^F*C<D{On*o&81(-HOrN%tq1r=-gZ0eV{MdJb-%k;a_`^Q^Sy
zG$hYS6X*=jd1(qQd=sTvbAg#8J?RAMf>eAGD9KVeg`Y1<ld$E4S54B>o0B3L%aL4`
zK2s~ZBJDW<DpmTu1x#F(nyi6|bg4GwU6(Q`_<lpGyAt(uQ(BP;&|A`!A&|_F23Cfp
zOlceKgJemObf!658W;$JInr)A5Rxl3sRq5<QcPdk^1UO)7a;Sl)V>j5@+66tg7>6R
z6f4S?9_2v)zBE(=^ADs)D<JYv`g0@l9!bsUsBM81Mum7Rxhw+ni8SOaJbWt6RUr9H
zx;YE#g;M7;5WxxeW~hrIX>$Uo7t(l~P{Q8=kgjcj#w+Oz?Hm_N%NBzwkrYZ^OM`KW
z0*moErvUR-%9r8AJBe!w$@kLV^d6N;6?I|hgEX)W%$G?v+9>)cbtUgVNh7HXE|-@5
z4293qBzS;@`l`iXewE%=gBSJ+sU^kYze(9+Q8mluE($VN$RX=Nt(3RahKW^jYwC1Y
z%WHC=zeavdL)BWj4h8nT<Nykiu9N*PLcv=eMH~FSa-;cB@RQGu2em=|g@R$5<<T^|
z@|VA(rJO@%Y3m`tE)V$wGTY?#bZ9kD?n_T}hg?`0qC4gBbTD?8EC(P7mZwjIi4fU?
zK6uzGXDvkq?UU!-02MCxvBJcDSzQ@+56aKyAUP!KG68m2F8c}#k#Z{vv>lO;FaV2^
zx6vVsqq6-+I^};%=ID_em+!9z%n3Ot45HEUnqz=DDW}nap%^)oqC2tj-Tu&zlgA!~
zLcBbV_HPp8(jw%YlC!n&>9qW_ncfO{z$Mr{D`z}|+vnsE1<>c^qMxCVC|_>~$t1a<
zJrtQ2<V6%mN|rTr%I~7=xd{4~<l@8dB1N9i5}sa`uZ2V7ikwK_Af(Dxiql<{Ur~>G
zO|DI^Z<_q*39!@UA=$8WU5@?)up9EjrEoMu-a%p9OgXJ5k}UbeuYk^$cZS(vDMwcQ
z2$)=X9S{B6vV8;e@5payL339=-y9-&^0Zzscu!tK$A$9cuhk)PU$%aP-3Rhd)E*zo
z5$~b!NN(T*e+%Sz3U)r0-FraqiJbH^6rRd`F=<5D;s$Mi6v~zdH2-`qhwOqzkz6wd
zUc8X=T#@-wej5zXS8`S!n8osp6HqLX<DY=}TJ{YD=o@()Ed}1nn`ktBCwFp#!T0hv
zYTc#sA{xy;$nWPuy-fbyA9)|;w5IUzle}gl6v|~DKH0g?a(~(({v!9@h0L$=R|)}D
z$VK!hzR8Pjf?BSurD)U&r4{W*tW?s!Aa9KlCPQznQepzrOX*IJX`Qn8FDQ5`9uMH?
zdZk8pi1;Ywv~}mJ1kiCTKcyxu$u}s80z~W^m6{aX-K1n}gZa%$o!^1&uY9AhltU?_
z`N9@uD4jytss!U?6{0l}pWw_kWkV>EKxJVI*xjyN+X0jyMf?HG9ZJ4C6m}{#zJj?+
z=|!{e-HL;n)gC3y0Sm#(ULDMb*cDx0RN`Kx-*m`?DigPW8>UR8<2w74ne+`sxH5Gy
zO0i$5_7Zs!%GBjhIH0r{14{>$gP!o|kP=Lj@WaY9+7FCWn$eNYBTCvyh(syhPX+U+
z@}W9Vjwy*0<v*@)H0?d1*fTYFK+%fg0?=5+gHFiBDPFW=6R#+x08LOvo<nj<@p*?b
zomPsy0CPrZLc5Y@l|E5GJEvq*JmkExhmPbXD$x{dN>cjKHp~U(<^kj-D;~XI;i6J^
z9~3SrYg-{nQM%jPK;yD9<0dk%D48_9N>y&rDY2`H53TC1DG`L7ruh8~$#f-vcEYbK
zRcI6VhB7(^j^0$pdBC+>${0G^o}pBx3eHsSpMrXplBR<~wo>N?@^X}58vk;Y-GgB7
zwz6>>eGPI)8A6kuyUN+oNb(i!e)xS~SwYL~2TJr(XcQ=g^I`t6(xeXZo+zEEXDd|h
zodol_a)>^RC{kY0;Py(1q|eBTmA`L8uS9VSLqXpvy(h!qJ7te^uTZg5XHcr_DWW6)
zACv`VkY&ojQ*g0d`JHwEKP!eAfcc_~Y6DAOl@1~-RVZ#W5&NdJ;o-${-ByYQuh3;A
zfm*3E(!0G%x9~FTuGX!r5A`*=%*{|(s|%yagO_gJPXJq|`%a5z=dC+{wYQyHuRCK!
zrjPD#I%wvr%Xk79KizT)SZ~m+Zvy>|x`=T=+oXF)z2#=z;W8-r>w+oD;Luh34kBB0
z_2`?Kt-4%Vu?6TB`ape~Zf+ygOrY)~wejt`-zq=_>00iG`VL*Yix9Ez)Gen~(k@*n
z9je`}+tD8`?$N!VktbO9f!>@DT_`Q}_Uex80y9*1cOs}Tod<0~?b8Kz2X?qF&jTLr
z*Xby>6QTP_L~=lvLkA-d>ZWEu@{lg0H<*WYCVCW+I(uv69kJ_vpMW$<=l=qr$8}Gs
zM?IliL!EB4E{!7GvAQ2=lOs+SL_Wpq66x%7g6<lvCQs>HGa-3e7oP#_Gde>r<ek;6
zY>TILPItowz4N-Me!xuB&1YaJNw=^H3V1;mMM1A*ojslmUex_H9Qv1Zvtpo_qI=jG
z$z@%6G?FX2pVQ%5s;;6GXjgS1-=KI+XQ1<SX}Ubx{z=#2TnOF@UE5gzyP^B_229-4
z{n`|mw{!>ELN7x%t{aj}oe2l^xh&n@07z!*uGk%TYB@S<6ku|73#l&e>SAc4I8RsQ
z0yOUFf@nuAUsqZW%=@}!Qy}?3H!}@Mfvz!i29I?tBDvfv-Nzh&73)GAsHYNLOb(c@
zb!TW8d!zfF0ts(*T`vOjo$l>-px*0hvUJ3#R5x4=jSsr}6u>Uig?hn@kGcg_q4-HR
zn!+&Uy6^u6^;!3GD^&LvoyS^;eAUGcL{gzU_6&L7bcys$&2s%H>h)IW2d;somHHjy
z0li8uP+WDjek4t1*XS9Ft*q65n=Rt~^V0u)5=C35-)@8Z-ufTtM9O;opdc`P^%H9W
z#!p|RGe9@!b3dW>HtM<Q5ZR>1-$cUepl1dk&tE_3H<Zbt?}`t}xGnl&Q{l{3{TPZs
z1n7G-0@yZv$q%p_s1K*v#&-Q(2aSJ0`akF+mL2->wE?qJ|CVZYmwqEn{&(x+M1bzm
z52aIE!TQJa6-kJGSyfPb^`BCJ7OLlKLLp55JI(I)>6Z+GLb!g;2^c(}UqeSb59$x?
zMIjF9Z+(DIhxO;(AQGwngg?W=*^lV|rv5cbzcCi%QT;BO<{Z--X@lXoepz#PaYBE*
zAE;>kED!j7Qt$g2Uc~5U(@Zs1f4&#g<MeTDz>L>>{{m+c^!q7-a7zD+7IshT?;V8t
z8U1}4Q_t#SDHL{2Kj9F-&fE266thUwtLafD>3=Ii<^_F0HmGF%^YifOqCQ{)^e^d`
z(=swe-$6m|by+{W8uG5_L!wc_RDJjFp>S0{kJ|Ay{Yx4f)Aa4>5NEnRHxQWD^^Y3C
z(Hr{i5`4O;Pl$!&Exo;L9X!p@|Moq&nfhM-;AZKMtwrr+>pxwCVvfFT7SM9_ujv@V
z9evL|@ZzpMhz?lg=|4||7x(mw>6mc7ehD49xv!tw2h0ch8aRB+J=Bk<6Qz&zow~u9
z0{uL)_gEjJhx!wJft?n^&-Cfe-4cB!efsuX-)$H)iu6@0LH~umof|Y>>Qg8>@k&30
zLg2;v4P>xH|D_SsU+cGh56L%rJJrlv{dYA$mFlZ5fXD~^P#UAk^f@x}KI(h#hTTv4
zA#}E&TpzK?j+*_fA3g~hU-Y9#!0)g6I69|Zp}#%}rT?Z+jX<*8a6<%hmBB!to2@o<
zq6y?0!@Cmbtu+jAN8)8@K=0o=!%^C?^fp}U50UkT_yu747&bPBh_4~;4N&|H_pd-?
zgJIr#HQv9?hILVp@i*K|M(sHa6XwIGErxp~(BEpXG(xch40CAPcblQ>Lx=<#uFQcK
z+YJNHBMCBeqmFfl;S)tgb{bYukYbmi`Cb^@ZK(Ge2KN}|Z$w_OL2rlM5W`<o7kdr&
zF;lg3p$1<ZedEFmZ|UvWXXs^wVz?oD0Ghyl!-qpqj4-@E0OkS1@_~>%Xz&k5a>($E
zD(J9b=Rj0&q(M9fkt2qmsCh*hI#dRA)G#6#-XAlFw46F_=t6rbCk%$|C`+{A1$BD%
zlZMwc5sWcZJqj|`u$J0KoMGP?n2$HO{0W!@L-x;b?bJU$oi&`G&g7gyO9$xA8)RAt
zB^p-H(a$79F--?A7@BqgO0pqqJ)kcd+Kfg$T{4Vq0SlK6{eOqv6~o7R@FLZ2m`R=I
zRl~qnAg>wborYqXp)>wW8h71rh?b@|43h(p+%$A+55-%Ce0QK_80v+<Ql?=By#P6e
z;9NMGYgpMGUfebW_5|~eVQ>p5+%=T^3CTRek3CUc_Y76LKt12!OB;Ci4R)TUxDO2e
z6X5AX!x`F3dt_)|1dRfN$48(&Hk{IddSW=(8<I~AS{e_Y8J_P0cA+7Rb`+l*IO?;D
z41YaGSzZ{rP{{wK;V1eQ`<0;!9qBDLTwMjK#L%7o;J|CcX$rExF&ORd;M500)hh6&
z%rKsUXCDo7UV-_^aE5BA+z?a;XrB#_Hz4neq0L?t?W-Y`!ao&;2-<!5X84g5mKz-h
z;MxkKz9#Zk8n4_z-YVk{)Q(phr#=DG%eaQtvg?c;&O*W4`1?$njITH5(5%$Qcu@xp
zUt@2YQurBPi>T5K#%M$-xQ)gEG#L9E{f5FBhtcOxFt->FYEYQ1#yPY*7GSJahGd(u
zY9n9<8n4kl>2~AzZ7>*Q6lVi-htYHnc{`0!bnI!Dk$*v-JOvx=v~L|^jH5GpdyTqS
zXoMQ~KL-_NOgV{UpRsy#I1_HXwH_YsH<nR6Bf{9`APgQbM$)migT{(4U>-6K5g~HK
zm{5Ww%2-l>T0d%x#9uYzjv0TZVB2wH0QFiYjOj)?avE){orxMcX*@9t4#ybZq(C&*
zc()B?;*1^B;di_-HW+yc#%*)}=aezJ9N4FgpMQZ*=ZqeEVB);-<#|+aqA`$0=p<v<
zY)}`BQ(TajY>fE>b}t&gp9JVj#;Qk=mtt&3b3}Wpu@9|_t{Sb8z`kbunO?OtV|*!?
z>Bb_OOkX!%O@_t|V<~Nt-843y4->bH-DyRhVNA$}WTtUqWngC+)2}1RH7=)M&TZr7
zClI+~JVyJSca2k;LOstI?gI<=j1C8qe7kXReQ4Y_=G8($9~irQh2lfwW!h1CWUQkB
zRbX^q37DtG3-s6Zo*BQ;M`(q{j(JdcZj@RgugEyzD6n4`2g@kvOXD#*5A(`+le&gt
z<D-TsXo+zgotb`ZyfF@#Z;Vgef%4X9pTNNUJ7d8rV81thpcr<U@icw+`O!F!)^VSV
zAEv@mxiRn*^gkPSd4l=HxF#LcS7QYY<`qV-{xI>)`1?UnD@}g1AX#NfS_zTWCJUKg
zV_HEY^jgzmI+NsOx{VW8+&WVW`v+utn?l+nS#K(!@6UZqCl({q*JREI)6aCt4b&!6
zd}n}eHZ_le`~Ied^q3u{xke~#F~$A>yIV~*I@uUtYS#_SZKe+NT}Ys5aX!?yo4lyy
z2ALMqOlXIReE^Z&CVeFu5cZfDEuLYpDVpLhA*SuL-?`WH<UOcR)5z1P;4o7p)$=~n
zV0uTwP5yK^VZW)lD{3afv<iQXhdW^U{t65pHf_BLW~9kO59SdQOJhZpY20qOcGT4C
zHAIe?>d+SZansldbpGOm>Fr856>YjlXD?$-2WSowXIe`^op@8=5<H3olf4-Fr%Wra
zgL&GN^a#`$(@X|Foi)v-8Rt3EE;`3^-ZXVBl0;KCJw%dBU#ZqFn$FJ#$|cjTawI9H
z2wK!#HU%_h@cvyfWiEr=R8xQYK;){aup1PwnRN6A8q!Qh2Ebst=|dZo>ALA$doXX9
zI#Yj<Ve+Pr>N8FAlVKvu6eYlJwrO)~P&uZAKA>_<?J1sq+jN?O)^|*48vu6KG@4F5
z=9!+(L>=1inW8rVCf}4nr|=(|HXGo~BU73;^b1S_XdU+0R4o9CPfV^ENS>OE7AQP3
zO{K2C&~%c9*ykoI9Zr2|N*jmjer2ln2_}k7i)fNoVj9)~BCky?>1&xcrt$O@;#*UM
z6}9%xZpz;cjrXRfXP{AP`lTu|KbS%v!nZP0HkGj4)Sn{hpH1&6sQSeu`9blk>Eu%6
zRhVLb0`@o4YuW)@ZjR3f$_n!yig>Oxr_*y?Wi|~%kye}6yCH9lxi8IKyv>HOP+xDh
z529$BkJ&~GbYJseYFB<{?Q-aEFvpuAv)Md}A_4y9_Y~c5n7``<kuBy3I#svT>_t6W
zfO+U8Ft?d!_X1d;+2eOeZa1%N0`(ws@7b`s!`yQYM0T2o(~GmqT=Xlv*liwX{~5mR
zG27@^Qn2}9Dr7>;HHO0Pz2<P5xQ3eR(84dw{M#c?`^=YVJP9{fqp9M4b6Osf2y<^b
zqjbRB`WBoyXr4vi$sIBm(Kf_k^KKU~Bh80sqvVKrXaW?X%-88nJ!&2^+7922na5GE
z{kVAwjhH9QQ|b6$wAnyY#*^m3Ht5HgBl<xj);zobWr{QB^+R5~d1(~fPB4FUpxCF(
zo&G{{+FXy8OlQn#wAMOnzFr?-=gc?ggOl^-8MMQZXdXHjhLX&!#?t!lg86YAu#?RL
zLQ#r~=IiyKc*(qMCa_b?d+03KW%IP<z`kM*uL1p3bM8tgTr~$hLEbfU@_l%iW<HpT
zdP+AR9tf1{=H1(1;)ZzwZKB*XH*yB3%w1`blwqDY19_QdF9RL<&N91~!cw+*_--iX
znBUb$X0G}8ZYbV1=cj|ZV@{(^=&reFB<$vy`xZg+o;jLc!+i5#oE+!wo82#hdSISI
z)5wSBKl(!Ck@?yy=oOf~#{lKAdF&ftJ~20=;rFR|V=BPx&&)s4$&(_p51nm)Vb;*M
zDKE{IZvcH|_Fjdg*xZpij1sfv2PCh}t8!rCjoFWaP;bo-XsY?nJhctXzc>G~2PR6*
zgEC?8gE^k6yUaX)A1dghIe9;*Pv-B&L$BPtY%jn*+s$D#ihnUrp}$}A)tt8#*cIkn
z7ufw~_9};q%PnCBJiHZ_EDG|kw3r4%ah0Wm1$nD2YH#SRvDj$Yy4K=rL7tZ--x&+G
zB$WZh+cKScruCNc3M4+3p*`S*uVqquNcvgqvj>CRV3|b6SvFd>(ou>{mNKgK&6YFm
z;i<o+(_cs&mIgh+++uk^)0C~2owuMLV96!WZI%$~-UBW3=n%qo%W7KG1z9}lsQC^{
zTjv)HmSpN+c3B?!KxDV&U00y&v3S{Ooe*r<Lmf?sC4$Zp?X{fU3M$mHmdYDuSxU34
zeU{^Yqn^Vp+5@2WTdLF7BoUSc6t6vC$sUR1pyf;{)DKx)=}kRsdG{Dpq@_a_xOT)c
zC>&r>mfiONeblm_>i3u>??*d4J#INjo3AG<?H8afqAgx(=%2LgYzY%FmXJK?$6CDN
zU?R?P)e}^_Wl0S56D*hBLH(3v?PFk{wrtb`<&34b2lUQb>gs`V&eEkEdgm>r_n>gW
zlJFb~$(C`^aP6X{avuio-zAGr9u!k7>xMw%vSl0%=2tAUE<!QY@}L2*uUcBJh23kG
ztrS~Lv#j!kiF8Y|b^yI@(Pe?UVM#24`b~?2K4`dQ>Dw69onZ;4Q#hHH?$o-nEaNGh
zpKZBDU#aI<dQ77u-?^4$!y$9q^2Qq)cPy7Z;M-kG27McrXX!8p)IEzE?Q-Q?DwUvu
z?pqfA0P2CI)mj*QXgN>4<s-{&T0#_9R<#4zV~dqyBu^~eCd1NGiyw8t&n#E!0<+Mf
z%tOhZTRLO_%wA+En+U}h7B@QU_tG++jzYY$+z5eUvE>FWMoTP5@4<`LmJ5SHy|I+i
zw)R^~^Ug5w&f-QNqrA5)9*?|I%Un90{lPLk8q6}w6FQ3Y(GpDObw62(XenN9nb{j6
zpDpK_A^Bpr+&&2Rzgo&@<D$Z{hnm+nOKl38FSmAngk*(vfjb;tY5kNBjaAkk=^WT<
z>vK9ezQ%fgDMZ#<8y$p*m-WkYIJ(X{muA@B*07GiTyMS88zMf|7q4L6*E;71p!iuY
zWgyvLwMSB?yU{wiKax$>Wi$`mY+aBAG=D2Yn@0|-%Tl0iv3`{Rv(-9(Aw&YK3Vj*B
z&D!-U3<g>Y{2;mA+Gj7Sa;LTNU3j?5+P??#c3XdHh`c@4R&k($t*t%r3_`5sSHawC
zeQAFO>`?1NA7F=BGnT@Oeb&>}fE{jqH3MGkx4xleWQ6r1Cga=z>&QST9<;uBfV@N2
zMzk|?*m}GHL?W&Hc3>Z|rlf<4vhGns@~G97N`K5cf{K0I+I2Q8oUlITpdM}gburC9
zPg<*AfJTh<3{_jKbv$h@#92q-JOLMPeccL$NwBt}J%Ur#y%e24ZM|Is$r)>kCz7*P
zh5EU3*73B-ecoC?5n6nE#vw_vmeZpDg7qf7{>j$5CQuixqo{+rWZl^ve{zINv0inD
z=w)j;9j3ctJ;R`&sn)_Mh+eh&>_C~WS-W?D`84Zl+O18u9-u$2b=^9ZzWBId&7o6e
zH?1iYW4UErK^tKi)|`8g%(TX}K*_SKKb4{Kv#rU6$jh<*O5eriS{1Br?A&eZbXu<8
zvHH$IMcuW|r|-D)to3NIbI&^DG)&}M!=mBZee3vckbGd>RUhUbT06W%-Xm-D6(j}L
z?es?=9$TkSEb58%4(%2_wLYo^y=T@(X>hI3dj2&qpIZeVSSYgIp!tdYg;l74=u2xQ
z8J@nfdVU9uVr!@jm=fz*U-<pnTCEt^Z>)1%0Q1)Bx(tqfuttxDLYehuZ>WE?exwru
zpR5Pyd_=jmBW)3WwoW?)>WlS3M;QESHFpM8VYRzL;hQy@2HNFzTg4j`W`%A2MvyCQ
z?T-RxmF?#fpjO+WY2mlVCQxi<t*tGcV)e2Or5(z3wqFLL*xt5xE=bnfqMo8?J~sCh
zIO=Qj?hEsNw#7r>=muNGOHdna@2FefWZOVtn9a8Sv}@yUvrA_I>aeLOl(xlY3j+35
zTh0fV53u#WhGd&9mA175ZT)|OrR}!g=0Y;a#`%NVVOvEr&YiYJ6s6l`^QV}@Zd=@S
zi0rX_DnLPlZHH(=6Jj&pLCN;ome4yAYMVwO_b^+cJq0lPY{%)0Ot>xTK4A9Sww?lL
zgl!PbsSnsDRfotyn<^Hdhis#1lkBkV^=QCE+KjaBJYuU<iX_U`k)GsH+o{$_j@dlI
zpnlwT`VI0<*!qtGGupOO{{J|->bNYgFYcynbD?vSx4S!7I2Y>5l`|I3Ie*h_=E_+M
z=k|ht5+WfeB@)u1pmd9pqLegBDM$!NBk}v5{dGR)-gCa^+{^ns_ug~PeE^qi{S}31
zQmpr{qx!Q{>(;A4OSAspYmiB|j{FFU8P<7r@F~;UNDFqB^|IyA$hKbmJM?p`StOEc
z{d*x4@~oeD2d?E?i~mL66>IxkC=^(``+>V^UGh3mu31~t@>ytoi)xLFto?UGq}clN
zSX%!|tefa&c&YW8bMT_fnr8#W>(-Yup;2zVhQjMNtgq3r>ZbL%ZJ3z~YbI?qE3Jha
z(O6|&S`CqEYgf9mRAc>59z<?gFJgeJw|?<FEHzliP$;_5`jZ#oZ<F<&LG(3S4>;5F
z*J3@g1Fg5Mhu??6JJz=JyK1!#q9a?I^<^q!Yqvh*0G~RnnG~Jxw4S#Ib8*-DrT1a!
zp7rP7K(EXCe}(Alwl)m``@VJ2$LQ;^PGSMN*V-)#B7N3-Q=r#xz5jcFJ+NL&hf&Lb
z^;P=A4qBhdfX0yZ@09U-X#FCctcR^VmjZ3X`umN58MQt@H34JRL;27jx1LFYhZENJ
zln0o!PCNp%DQk~taF49-=fLf0>!&HxKVz+@U-hiD6%As}dbS-FY#BKcaCR2PnRhYX
zqYSr`Flf(MtAarX#wv;gI5JX8VD}hflnqPA8FCth6GQV1K%E(m&jQAU@zM?`xH9&}
zL*WGD4xPH)7(x$7o@Bh;0=w=Eiw{IR80kx3!IQCpKB3{oSWN54DTYP&CuF=CW7g2{
zVGO3D^)zFs4cKQG0asz(mtlwm=f}{~dDowzUH}rnsHIDHfs9u^h2B}lN_x!(F`UoA
z(mBTQr$B-kyK<o(!Z<_4#-WVt6exr-mMw)B=NYr~P=zyMEmNQojGs&}5y@aI#wel~
z`IP33W-#fM6vMFMK_r$@wG&(%<ANC?@r-GzuTNm4650jE2-Uk@WXyAiWFq6wn-EE2
zyh9Z}ml%-=XuQnOz6_s|887)lA%*dDC`3{jzaOIWUj~CqJCjUC5|xf*G3<NLna%ix
zUP(EOaXCmXqm}+@c?=6}(DNB}bUwerc#V>v1&puvfm~%cGvUQGhL{SN3mIGr6csVt
zYN1!m=%g5O3F8L|xKf6XD`uvQ@qvu4++SzZZv|V<*iAKcHyH2Z1NBxn8S*&HR|Vsm
zJzT3~Jcr6Pt15=*F?d+bNP8LPYZxE6q3;%>>uZo&hU*CQ>KJbf0IZ%NrK`pb3{@<g
zX=L1`b668&uQ&Rd8PnNtt%dPZ2;G0V&EUTa#XAgj8(>-)x4*-DwK2>Gq1es{KMuPc
zjM#<H=wv*M0=dgLZ3~fm3>!N1cQHPq(_}Xz;wLEFXXuWC>tVb}hsj>XVXB<$V@!!b
z`WY*4Lg4|!hN8v;j34*I8OtCeZax%;81DVhc*uCf#S9HI8m_|b2&23ceWQ$Z^!gZM
zR4l_N#u-;>A(>!IyaZ<^8KdO(6yuM_fc=Q!MFl9+j1Q@{ZH955VqmijUOYtR7#B*=
zXUly1AN1KV8|egd)WYnT#XQ?Hd*xsqn4t`GIx@>?gK>=c=YD7$XV&Gyk`q(j4ZF@v
z|83x0n5R<UuPgJ49OMMEXeadCm<#^^ImsNL^N>69yL(XZVA}Nq+LNiK{E!zjigs?N
znCt0G>dmz5rj^=<8S@xMc$)bJuGv_fVV=>#gfG+QQ|S9K{j*^rkhvoTqd3c)pj-Vx
z%#)u0<{UHpDUe`h2|cMH%&*b`7Rs#q8em~e7TqH_&vd2iXE?J}0}{b}n%?!1%s=sO
zORS=p7K;O>JDQnGWwSBNTq>W7Wv*_4i8$tSdi)LInP*RfBrp$BdiVnKas^;6GM6X;
zlgO0P{j(%yF}-FlF>S)(?`5XK4<woCTn2>{=H@5yH%Mh_o`Rt?W(=KK(wU!9)GC9y
zX)B%oGMURMiIc?)^@dC~^EFD_<S_3PfXii;&j)rMvw$|P`OIIx26u(ICmvoDFkkY6
z-c{z)^h&$N^!g3ME@ZmB54%N7_X_kCGvld<yo6bQ0AQue>^$g|F&9(4&2{G68B~8=
z&fHv#5#C^4Jqhfa%+(Ybt6-j^ds~&v4_*UT#mqR1`Ko44zYP;L%oa)*-eN9jfI=<v
zO?r9NF)I@wQqRnzuto#Zmu@UJGI!Gfs);$~01M5`-PKTNVfIk*?QNzeh4O!Qn2%@~
zZDn429HVGs>iU4z&h(@Y4s<a0QC(sua~{36?lP4((07mdDqTeDV#;gK*Uj9x8w0)1
zylsYw9_A}Ag7h+3*MQl_JVM9bex`aApdT<lEd}NPbJz1wA7sv_jF4rB>C_I<hs?Qm
z;P5c>5$)_pm<1H9A7yr0Vb;f(?sPkNoSFAIrfq`xU>o`-nT~6qFvXOufx;u^56=K}
zmdQK}ZjSlupD<|4I>d(wI~KbN>PK1SR0U_x+RTKA11o(#`W!8+NA$xu##-_$K##M2
z{}ruHtZkHLa%MGAC87)Kn=**FvILLA{0SD9ZgIG=ctVJrWCc@X%AM6s@jwq&AQgUk
zvbOyQ6JD&pzr}b@v2M_g#GCbUHaH*F+jPJ^&0537sL!x0T*{RAvI=PT;Ky1|n_+*}
zA^M_90L!0Vvw^Jj)&M=rdXx+j#M(|df^)3TCLtNja{3T@A*`QDffC9ZrBinp%Z4hy
z&a>=1LBd(~YKTOzZeN0WB+LIbkSNxlRB0B?+F+4EBZl>W0<N*FMfBQ=V@U<*jAy+>
zXRQR*GTNwLV0}Yr+Ka4v&X7!G{bmonB-T$<sCtRj5Q}-b%&IWKi)5DE2Yo55pXnu(
z%DQ_H15IPS;03UBR^JkE8LXx);4)cDFH`+z7V8!I{75#-nQHNJSd1*7<+9FE%rK8t
zMQNsdme&PXy25%l3|s+gl#U=*S@ZPZuCX?|V}ymQ9}{7|h*cto-C|by2B4I%9-};5
zDQgTXh*cRYcN&JSvtq*mR?hmJH{XN@kEOc=n47G!TF6weHiUqyWWBKnb5X@wNfkQP
ztTAu&)vyfFr*1f?EdCJ?X=07v2X-?{p8&}gR@PrI*vk5#5GLAKb0|r&YG<W6qOXJX
z3>zcsWDP%r-d)zKbKvf=-lI2D7i&M&2X?a(Xo<Yf+JRG{RS#=)2wX2~dIucsV`T?|
z^s@@QFu(__tN(o`b$}Jv1MERoE!|NVVj1be=0g^jZU+prCZ2`)5mpT4J4ab}=yx&3
zvgCk_vp&{iEE6nTp2K6r(o-^ViuH{MeUDf#zl6SNmLL&ihBbTw24`6U`WnU@tBe+5
zTlT^Ol(e;DpQkA7QT8y+lRf(z+UGm4jeL0F$d03O^<(UByD+rl?4C3<I<dzb0qV@2
zrhKIf`&%lIb!Gd~{_g}klMXU&Y~K~Ibdt@WVkdWY)goB%VCVh?;>oU{XWEPXM;R6E
zo?`D61I?TLNieW|*x&sQ?lhZ2QT8+J(QbhHvNxK5=EoKUz%_q%4Sj_yfX$@pxj=Tx
zVThb%-=gzS5c`K~z&^*$qzr#Bd-Zc5A?$~T(HF}8_#n)Ou`3>jq4Vsg5EHdng|kyB
zO&h@uv&URSvdhYW7R7$&CSao3O-G;@!#+vnda>*PA4tZr2dG{=o?X5fB!PWA50V$y
zk$(d8B0DJ_CKB1N?n7e|J9P?}m)JhPz~9U4jggqcWOhV9FjLrHbwb^e%ARONXBzv<
zF0kqB(E)U3u;*8UWU@V;ghm#-&=+>I*|B8+&0&Wv2A9jePL&B)*gsOuQ~~?h>u~!j
zdxmZ}U1PgHfHQ^c7&_S&vCn-AQp|RxXS#%~co&$Z?AuL{EVHnKsmA&``>!#~WjXt$
z_26!>@ij0!M(jZoL@U_c6lkhs&uHLN6<gZ}yVdL(1xOA1EqZ)!vA4&=r&{*2J`ky6
zXIBHeo;~p?^cvXNeX!fe-ZBq9HL(}?z~5%JH@yp5*cNZvt=wiGp##_*_H!8!ZDmXE
z0IiMv)m}_VJA3FeG<L8>&w%S>f42(?ciH>sICYPGfpYp?Z1v|L-E0Y^2=B8u(I={U
z*zdQ%nO^qB5s*H1kPxJw?b-m52kiGK95KKSw%h^QAUm)PWQe`$Ygl^7E_w=`!|Z#s
zM2@hZq$<Zz_Peiu8)L8g2#$`kx88=x1lx(!C)pk}rBmz~dcizmFVJFy(`>KLFo+rU
zHY$LeWeX_MImd3L{k<(mN+)VN&f)LrJF!POS9W2#?KvChNbSJcOPf+hPUIIrJH~OQ
zZ=)XP{9}Z9Cyw_#SaRmnoP(YVCzMJ7T{+3!;7)J^e`08EoW58XJjscz1(-X>Osj$i
z$Lkw7>dE<N3+#GvYIj5A6z7;51<kxU;eo*R;rvWFy3?HHw5318S^6f3FK4?OH2gT9
z(K_PK@p~7F0h}5~aDkl29Ux~ppU|N@h*S6)+&;$%i~twR`GwYj5Kd<Zd^*qhh4L)n
zoKI;FAHg}23oepVnnOi{QJiT?!$)%pweU2CvxqhUv7F<*7*ibQng0s>I9f`yBybjZ
z!NUuj#M2PD$houwt|fBj--N*=P6Ro6iL;OLESEXUDaDY?`G_v-r*M8gfW}mg14XUU
zI6k8w>72Q65K9K<_Cug$a?*YTOcp0@99%ZX`8Al&;Vk|YB$t!48Xo3xiW@K``JB!4
zYPiA~qe(2_#6Az0tDHcp1ir>u91qDt&TfhT6md3gM_)0gkfQn}oV3e;F6B%w0awNe
zqPNy{3r9mwWjW_*N{8Rze3lE1o19N5Qd+^WqmN-#a@@z!SH&5nC9;}xWEo7<aF$Rk
z_!cLe9>ZD=rx$v4oJd*}>p5>w>Z*aWkHWo;oaa9VY2t|Kn9$6TQYfp1(@T5O+Z@Z<
zP;}nmxKd$ZD~CmCh&Ikix`frvshot}4o(GCx^;4dDX?^x(?}n!xW~zS3NzEisfdQ9
zZcgzIG~VYtwGl(>;iMTc-MyTXi7?T}d0`vW`!OVN4>%cA0X)F@jjD|XIXVmFM20x8
z(c1cu^UxNe!<;p2I5WcG(ocSr!&k%Z80R65m{#MQG)nqTa2me`H^~u)0cMKBiGbUW
zIG<8jVVZM`E`rW*%v&&sS<V?dcsR$2vj?%|meTy%aZ8I~?<m(cnbtph?*1R))G=-`
zg({D8&n^JA6L+l#G@QA~&*3NJ!eu%E&6T^CVk;-O+EvhV<MvUa@+9}0$DrWOb*6dt
z;6^LquP66Q`ZuFqTqin1pW^PN=iZw;avqXC+>`VTuhU$+BXnu(4EJ^V&H8e`^@YA4
zms5vH@aHP2vNnL*xeEpZxvL!^a+aGyzmgzsbskKd<K8HMLNNExDl~?0O9U_x%B?#9
zg)naJ)8Ni?$Ej8%oclh#!y>o`>Fp88T}?$TQCtr8*%qs4?%p(b6T{s>xtv(;?+zew
z-1>d+JDwX(v!1}cLlr(3xU1<zeUUrZ59~zl6J7vK;#PHmT;lFN31=>IedrXJ%(bV8
zWePWhqLHawyMKU^#`XUIBI#Ur`jKXE!)JhL$>e5Js56VZYcVvkx$~`nox^>Z-s`zs
zA4;j@aj!iBm(N}IJNmA0&(iCzfE!6!xvSh%I#FNaZg>%Bh1?*@_7rg!Qq4s%S4(@Q
z67G_>AX3T=Hp6Zi*PEX3>)d&?rj}c{kyMLtgF8bxk(=C6HyEto2Ga?(lDn8{y{fn#
zlo+b!b~OR5hWqjoDBR+1JP4Rt?pFFzaUHkqE%eoM^^^{1;C{FUV`=2>p%Y9KxASdq
z&D`5h!owD>oehS2o0~<KV()M*@pKeu<z}{mZR4IM>~`)7dPq9B!k>WM$<12?{kz;h
zDxlcST}08r`&{>EkRERB6dHTEZ_}=!k6ZEqyy)kCK^I9Ma6c7bECXE0a}XKiX6}Lc
zA?~T4!9C=z%Z9=*_eV<uWJb7g`(R>}yPt|Z#<)RrId7c%bunZnxUPv9#UwYKa@AAZ
z!xW-<#I^keBGcTS*PuSb{fw?u&2m#HYBk4g2?3Zb@8u^UV#kxz!Kb6V+jNq!=ka&L
zH3!~1F96z+cWoX$f5&(R4O)-$?(Bh#6K_cah%@iIuVB!HH$w}FD^Erz>Jz-K_o3j%
zbHM+MvpUHup-;8B^IDfd#Dn(*B~d(i>*oW^i?^!=ji-404uE;{E-iykKD+?hzMkg&
zMy0=JcqjYm(C*8t_!2UHJa@|Y`Sa?7;adQ&=r{%w$ouSnuzQwQLocx)o~aC@KgWxu
zThGC~&9sXS;eEXTBB8uKieHBDG}l1R^Vmi-hV%OAp^D%I|M!sv-eZ?xK8hEy6?)OU
zOU+a?5yR8aC#qt3p0td{@kHLhj_29aAvl32>jZa!w~bEJ7kRF2KuhF(P4AQ>o{3J>
zmv~ENK`!&!Dgc_y+nt9&r0|MtU@4WixfYUXJmXK$OXuCV1C$J2KkZvHc^*m-OBN3`
zV|eg*-jtEe;f2w7b9t|RiOxJ;!Af|M&$~s1D_3~SR$<x-c<*dQ<5gY_)ev3d322ch
z<nig@D&oCKhn-ShP&*pSc%n1Fyv}=!PI~3MOKK?G;B9h*`b}Pc1GowcZ^7RfeI;*#
zHYioRX<sN-^F&q9sNr={$p02^6+OSTypTAUsN?OSg423l=Pbt5z}ru|%0}MVI`lR1
zyi?(JGtZq4u`Rq8=&88PGj4~4JG?CvI&bBDVg_mBB}p-)cAn+=S)g_BKK&CKojm$?
z)K+(SL2J-?kJn2{!7d(?hTYApqUwSBytoo5^zi;{f~8*GPm7??$J<U>(|+C_3avii
zo!WrD0bU3l+6Q@+*MKs_J2W5UA@5QGP=<M78dw<NSy`3>ZIt)XahMq6CF-Fu&U@<z
z$V~9KMxagd9#Ngp6z>z-VL#%ne+-J#ynm>cXNH%)0d{A3ckhAB@lLEqqb+}vGZgIj
zg%waZ%Kz~ZJhbQE&xHjC{@fX;JMv>FyLF7;n?y<5<NST&aM+1|j{;oI{88E@y71qk
zq6=64mmFZ9;Cn@abK?tWX+O!YIR)a*KVOMH5B`11CV27}9fMsj{trh%PVtxh0K4A&
z0jd-7;hWN7{xrYqI`q!)A5oc*FF$;cist?J&2&M_pU<XUO8|dY0wy7lzhM^KS^oA-
z&<Ns3)dS`nKmB`<V15DB35D>NEr6v^{)u9k594Pw!^89Zwa;Ll!}))Np)Z1e=@9xN
z`OG&#qWDu37mMaE7NReXKOY-qi&Z>-Ed|XI_;wVVxxmkx0J+FtzYr6Z$p4e>O(gM;
zu7%<ye#IQjU*>=QI9yBS*U;u8h0mISGpYPF|AR;x-);<CI{yXwcRLyUzQYj7<fp%f
zA!YHKD5RUsPf-9Rhd)BQ6-zGP<{%XF_}|kWCZF%#2J9>RNqS-n_>0`ZUFE+qg1&3~
zC;tbokRMF>_agpB3^-cM_v;2|34h095Gmz1&x2kW|9uCTxX$;y1ch>bp9zvT_;L5q
zcawkNKDY}05ekM@TKHQxV7{vO!<}fY=08vM0yX^SWgxfsUk$;<TK*rjtkm(9Zm?U=
z|AP*24g4K*7+NF$dkP&i@$=S$Yvx~n1AQ%g#*dJ^&9^)Y^*j76zk_S#uU3O=;}=pI
zyq$04!@~}~rP>x6o&4|i!r)#0jZfk5J$}p;45o{(mP4_dpG|v^`+VnO==bm&%VDXP
ze}T&6`}l|H<CXn<(HuN{z~B5TxB-4UCGH0KNw0$&;(t$-fDid|A3<T5Z}k9%M)-F7
zATr9|V4-)?82?%lERFM@uY}A5|6RKAH_5lAn`l$~h7%Bd#OG3sbDFQ90@)e9?^TRq
zmVc-S>T~?(DScrpFpPuP30|QM>rug3y2NiUh@-o;4uVM+aE^jIdJOxRU<tkQj|&d}
zk4}tEf^X<`=`6^h(4UK7Z2|OM1+%B%=}Ez8KStp$aGXS+hoGF|W1fQGH=ySwI7wTl
zQ-TJHk9iB;J_7|GLDmGwX~9lApqvrBN=GhV!PTP}pr7E%n;46~AU_9v0fPH`sAxA(
z5ZMP8&kFQ>zyt}_QsDEP;IC--6fF3Vf|?<M2s(;~3L4gd3lqGV1~1MFI_M}KE^wm2
zbcDd2_8F0a=6mRi5<FcDg=j&`Mu5c#I_M}KEBKgV{BeSQH=x7|mOe=zEl3aqDB$n~
z0sAI2E((h1dQ75VbO%V1;L%e6y(G|Hg8pT}x>LYT7E~p{{S?8zy|9}q*#0&^(*!X+
z5J?xzd<?fU1h3I^kSX|t8nXl|qF^Cg@N6tFa|BDb!BDOsfG%BH@&td<Z!TY;UIN7{
zg08zD1%fX>MB`O~FKykf33gDuT%q7Z7c`0lIaIb&ESN_x<PyQxC*WbJpn<+PS0>m=
zSLCk?Zd0JPTyWVMjW+}?lvTSa80dyxg+NNnZ>8Xwe5hAh1W`fw162#QP^hLx;JFks
zw*>Y<kg3I=8RqK*-BhPgFW5o>t_A^r0^@BIh~Ecxli&l2&NmB!s0g7&@K`)VZVQ4a
z-+xEov<bs*73_KeC~bm2%y6w;V5T#4hd|#7^-h5$?SJUJE6^0f#63aHd%*4zR7GQE
zy9HTf@V<Z{gGi4c;Vp>t3L<u*u}^T7_WAvSKU?AUpx_W?i-rW%|E+O?ziDQN1y;|&
z{D|Opioc8se#(OSm>>t0YF6WdFJ6O%3Bk)2ikMCczNJ0plt4y%+ed-}RNp%-SoH*C
zW(2i|U}9Flrp0(p@Ng$YY=u8i=+92Le<?<BR9Hym=JrCHexNuA6Dy(aC~RB+g=4}Z
zs@FL#oO6X;Ct)PzS)7G(`YXE#*S<#2pR2Hqf+Qz|hbfoiCj4arohOAqUWVW9!mBi2
z9>RNcT<{cLqK&7QaJ><hP6<`3f#xmzgNmblgn!eE=Cp8UKP;UQuAywLudvCCK0o0&
zWeog<na@EaK<G=4cA#+l7rL}^R(M<pnIK{A9>|;%W^&OPER3247b0YQh`vzaei~Dl
zu!Hs)=Y=V>p$ZqiN(+62Fo1S`k-~SLfrn8--D?;`wD1)wNr(|H*bWb4g)8aI6DL$J
z1WLScf<m(iLL2-bELInU8I(u3D13`n_(Y-cbJ$H1Mo`_%CE>x}p?_KU+4JxsSr|jh
zLW(f-67*AriP^A}ChVk;VY+a;0bXPX6_j_#6n^0jgIU7GR78+13=lyiN7zo$qg>&Z
z-RR2`K1sV#OTN%#2TNCk{}e*MK=_s|T)Zk=kO1s!Li-5F6beo6qOV9;wh^RQxQL1_
zN`xC82PqZWehlm~;f+T0T^Fv11y?Q<yTHT^;Y%xla#Of{3rLkv;|{m0g=!`2)d*#t
z7}70^@N_s7YlQ`LrmYjMcR^>p@OKI~HwYUIAdSMW>8#cyY^MsUX5sECjG{%je-RpQ
z3zt*e^^S14Ex1<UjxF%MP3UX@cDpcVCDc2F37?>^Q&>i?hP%St!w|VA3`~Vym(aqc
zJbJg#Kr#3G!iQ<_yGNKAjd|`Bu5W@&pRka2y8XgX+N3=Y&Yc7HfG|BA3WLI&ofz+s
zu<#B<9tw-Mpl?{{O_yp%gv)3(8x`uv`!S*078n{Ao;d*M31J5nM@|ZxECCqrlu)<@
z*pGy@0hrQh;gRLgm=W&SfWBE_G{qI>gf_nb%~s@0K`cAb+A@%%q61WEZ7<qf20aH+
ztUWkK(X#FE;+QD)c_<tgeL^)rPNHpI@X%RQaRZnxqISAv<|;Z|LPfAAM8nx&-9*u1
zXq*&1Pf0d+k&#MiJw$tG;q(-JN%xe!MB8sc;gqO7ADp-7uRyrwBigqP&YTuqp8z={
zIzZ31ujt}7^!bSnxk24u)J~hF0MQd)qAySsyBXYBQNk&Te+G$cZ6SJ2q^I+8u;|qn
z@Q8<q9;Xq8isn-&I!v_E1_sZIcDF$!TvR|;j3PuGv@?$sefwWHMf4{<RnejiOpqAS
zTnYveE4uXnmf}R0DOMjZilqlOL8PLi^aatzqjYKPqNs<8o)Se1tsr_?^jRhJlSS`j
zK|e)wuoom%)G392ny7>#yy>DDdg3xf?@$OXQ}p5m^ks?u{sJUh<h>9RoFghYfWBN&
zZXPi6L`Uf6PQK^_1$eKBS`smq0#OqW#Bx>SL?M7{qIan{rBGx`C(R<!i}dR*7TF8H
zm53J7_k&AC8I)Qn6IIYD=ep=K%5s&9Yz{&1hUkftaP6k(<JZAei0od17nP#n89-Nw
zexnkkYSEWeg<T^$PH~%CqQGS^UuzMC(aE4rbl@<4koBTB2GQ9dYNk_cqew|rG)<y?
z^f)z(^p`+dM9<J>`nE{84dcBd%BP{VicU}fqfL}W=aP2Oa0oCvL>IL1sS}NWzAJi~
zVwCqpJLufmCE7q~(r%F@pVBAyMUsWk=n>tzjDhxw3aLt}PZUTY@P5(EH|TpHk}+Un
zKomhw<DiH~Px_E(h5<((iV`VOGc3AFG3XJ|Qo3z9DypSIs4>xN4d@#eeUt=46QZPI
zKu?NB{{op3)mh>}ABi5Ldb?@S@N$@+5rt9kY*zHgn;7q$D7g#fZN&$C0BR?$m;>5T
zv6(jE_TnTy^c=+7D2nPRPOb+zCiakE*vG||+aOM2TRQVNi+dU9a}gJKV7gqz^4Fnv
zLLBg<1qR*3;cJ0*QtVA95qEJa<vl#ad!r!ZDYmAgsh2ph59E~CXAgWjEv^d$cSh_-
z?_OVVP!JmZ#P1HlZGZ9CivboO{viYEf#Qv{H$5wU^<CHv5)Vo-h;w2MZ2*JC?sF7>
z2@&U0av@awSP#&`#P8A@=Dc`09mT`NFH-s>LL5qay-4xdGeC<H*SP>YTI@#$#u#zN
zG~A9AAKL>GCw`K0De>apsq7{}{54%wxFEhl+p3FV$K60l6!*}(GfA9KM$g|R@!Q`(
z@v@k$f&0ngU<ZJvh;z0>BUM~XA0|i>uUG;uT|7jeOvw;`&V_!a_`nOm&Jyz|Y?Lj2
zi-Mau;`gXASG@8B^zy_F{Q%1szda6eMI8Mh`U=DiRP%dP{NW>v%yLb9e+<}#V#RK-
zMdHg;^i(W<>@qBsh$A}yS}HEG!0$5gR?4?r7bj7nYPtCFU6`&L;!TO@yD1+23nnVW
zn`w7eDVDB>WR=*NN>!@GUR&W|jo5<%__xG5Df()~uhWL8&LVD&Kxe%;;Rl#+5YJ18
z-A3_%5GI<$A5h6;v-t4SXlxN*p_kunaVP~R?}$YdL2MOwIKpn5`16Ax?c!CGTImq0
zKY(7R_#28$-4!o;4+igvy{FLEC4MxB#%}R@M?mh2EicjmtVbN>58ryl_Pc=HCr<nc
z&h(2rD$(~q9P}OZ2gK17Dj5{tE`i99c>ggpJ`|511I(~^1O1PQ5%G{4#xg3N(}SB3
zPf_T6QXDl1G9_LlK;t9vGgK`<ExtpuHY0vu@q<&dVjqg+&5338Ahwd5ZZK~rIgts)
zqY`gtfZ9to(c9KRQl9~Xj*?A@aP62Rc?5r-<C3N)z&S~L|9jLV*J<DCB3VdLMOTU6
z8$dZBIkF9nZj$pCpm0+1^WPY*yX0aG#a}!mVN~zxDM?R<2`|Yms)jiw>HQpi-ja2+
zn)*m=UjcVo@<AFrJR`}f1*orNunc{Ek~G>G_)A0-9uJTx_d_I5@-|gjoRye=0SS`4
zMFl?RBtN$TC0O#y*KjRF5^<0IPe`c5bt%{|$#3+dIWM^r2rgXGSr4=bNk<<@q~tX!
zmWq-j%)<R>$u#{0VkFir;9@0P={*%EDX&ChyyQh%;S(f_sSNCb#Ftjli;@<4g(gZI
z*%(=p<j-1QUXuK1prWPAlHWSuaI&O*0<9^MV;&exs${bX`e_mteV8X*((op*GbGC#
z(U&Q4`VMxpB)g{3mo0hq6_6as&ZV%ME4i-4uOv_Mbp;IOOL{&5^cBhYDEbN{byO32
zRdVoijOCid_$-K}P*Oz&+eMP|6#y-ktfn(liDWyadrBqsD3q`&ldL%bzpqOq6nQL{
zgk%BqhNO+^d~Qm<r1*4&L|y>2O35=+omC}SPoLqhmW*tJYc-Ocv=O@{Y43zctwi$&
z`syT-v+$|WBAH15+ay{17et#SUpIkkk+d%Y%x#Hx6vlf;BAo}WRl;5am^O(G-TY~n
zJV~#+4#}1%c+n~8F#_$bq+};h?n&OK2d_&an}lAsB>E{x-j}fG)!id`^DGp4C6A5(
ztWRQTP@%J5Qv3ycdm!0Q7w!ind;f*qLCFhrH)%++!T_HhN^aBnVp#G5y+cPNKIhRl
zDhU*U8<Xf};nTR}9KF{kB&A<sx+W!0z6;DL$@+hQ`AD*Xb`8^#*nHTVkpz4MXJ#c;
z7FrJHB%>KHVJm%SK49#m)pQ;2sI)HuX!cSa9i$wjJ7pk_(rdJg9+Qqtf*h9?Q}D}4
zdXu6t&eDMk5OI+jDA438U1NZ2C#0+QgL9J}q@V0bX(k^c?$YG~*z=H9Oj%&UQ~CvM
zbG)SMuEG2%>FrlRyrnNt9j1@;;xY7{mYy*~<BW90+n5<&seL!l{G^BIFX}J-i7poe
zNZaT(QJ}O|27_m%7cyWeNSaDjUFW2-0f+=k!|AmVB7MyoBB9a+V^lOBCLKrw=y~bN
zeAo?_F8=_7iI5Ic5m2Ob?oUiml(gknU`I>Wn9vs^eM<$HSm|oYSH?;6=w%%*WzcRk
zL29)Y+y&`e2ShGP%g)16qSVP2<4lrr<=`$!Kfi^sT$c7@@wZqdOK*LE))Z;$ckm)r
z+MWt8(xkqx!&18R1uCV;l74s`ma?T*48Y__?YF_FTxnYy^zx*}Td<oiy;KQuMfxVC
z+6$y-o#F3QX$&o&*Q8tj0a&5bvly-wNxNwuSS<ac1R|CaX$#GIsWe&+{W9sYX@Fjr
zmfJwFT<Su>ksH!aC^~pk`qMDHsF2D}!$hUj;R^h%lE(6&S1m<~0FRoKO?$3eQf?;<
z)=Jaqy;>(V(80Q18tVbQ2I&N4HXEfY4g$K#BJGVpXS4J&)v32gYcHYmwscAa{X5c^
zV<FQjy+}L9HtFC0ebGaDpWZ$l(#t=iuTz@!EXZAHFr6>%NriNX?UHiZq0lYeNE@m9
z(s2iP(IeG-ijnn7w^AWupLBT^Ec8n)pW0zE9!TGfhur~b!~?iLC}sT!#Ubh50a$t{
z&7o7-ur$aXiX+mAP;jHt_<P{Sqy=+;8J8yh05TzE@z6IZ-5CIGN;;ec%tzAj6f{mt
z|6%}aM*7M;^vz12r$FtTRBBlYgSIl$$MD-ucBmWNQQ5Ebtp<D9`5oXKWGWs!bd(9x
zL5|6O`)_k8dqD3ZCz<^`fI7<*v{1XqMxVhzU1gh&Lhpp^6$(AL$sQX8IVn3&tCG8H
z=w%QO+1K<A^pvUpvY^vTCK~~JN){vnjJK?jwxK>U#{{6AmhEN2?ipDY#hHC&YoCRr
zpRBS7jsCJzuHXV>NpwvmNG7brte=w!(xDeDOL!f9A+namFc>O3!ozfh$?oc)cV5Q)
zALch)#?VpyS%l2{3}hl@b2%^(C41{jbVkeC&)^RmBimC9E>^aW2}k2(Hc!FBc-atb
z>k?!WCEzZ|0_fjFT$Hub`7crC@;*?KWQ!^Oa!Iz10uh&GS(JTAmTjd7V2bP_oz_!j
z&s5X%mnM_ngWu^g`3h)c$eQRrPo`}BI1FaV?C3y~Et?sH-#N0U>7qui>>moY=gAxn
z0VZF@rBnA6ncNw63uFuDpng@>UJUhXvaP8QDU`MC0aqk*r`x~9vX$QhvqZ-H9(tBi
z+4~;=yG*8ugZb++&kksm%QljWH)LN>Dbr2ah8loY$d*!BSEcM9%JWpoW*gC0EmH@;
znHt&Q9E|XmESoYywX%Iy=&O_QM?mUjp&K#423ZfibQ@*cDgV$U^XUiIY>^%2!>Jb8
z2eb{nEeoZ}=R2~3+u&MdU(lM|CTk&w+hvc@sk=jVkYZ7tvZsE6-Mg}zRMT@$_9wly
zx?~qa;aay$N~iAoGAZRrdt?D?q0lQ^9ShPYd&LIO{j$h<h&+&4>Nj9$1G2<AOv0ed
z?J!!0WNAl19?G7W542%fRukMGk-hODOpMB&UkNfMt1m_0xU6XbJe-hSrytv->^&;D
zo{}l)j_f1ZGjuqcmOV>v;u+bxR5aSk?@-9XPA=L2*N)0dEmUM;FaL<5R}S*gdGNwf
zzJLy+$K?4`dw*OmS%ROJll&;1OPu9@I6=`xzF`U?uJVC4D4dY5qcg3W{JTsjoRrU}
z+=jdSF(X{_kWW)ho2PtB93;Ku>u3jcN}fv*M{oI$cj#c@BX^((#A*4)4S+c#x2M3T
zul$|@eSUJ@aSY90-taaw0^~nZs3cH6uMjY2<+;)53z7#@Qt+Jo%M}=XuzWY2x<lj(
zsR$ud?nTc?n7o#z`@DSDC-5m;zTiDbM#%p-L-Ef@dGu<qQSxo&Fc>W_%*6;}<XMjJ
zDOO&PiM}{_)eJ1f%WEj5lOT7dq~ZnnHM+)dQQm(LdWrID^o5!v`G-HC?~?prILKu=
z`%QR}EFYv(ev15wB1opn2Wb^elP7&f&tJMc%@Z&gazP9<GUY9l1<8^#?O;Azu33e~
z9Qm_9ViI%Z?_~lePyR#+`ts#j^h>%TPniN}ft*_d?yCHB3&5_)51fNuq5REUSSpf-
z(W$#we*7j-O5}@@!IjGEJ_VSiOuqVMpk0?|EyoDU<wd*DdPDwr0Tge_OX&7Sg?!~T
zn5dLLHwKX^`Ku;~RLdEZ*{PA|DuH%Oev0;Swen^31Fn;oJ%BUy^5qgJG{~!)pwKA4
zR}8QwdDOdTY?iNj8G0=i`L-tkb6b8X9i4aN|LX=!yZi|{({{+mAHZ&>TsRH=yK*z7
zP4CJ5JR#X7XHv$zTfWi(j^3A#ehtzi&!eK!UimkbQ0S9a(6+f>-rk752lAa1sTq)e
z^gcue<#u#aXh?2Z_9a9g%C}5n+J@zx8aOi||93UWsQfXyEjA_}r<m@z{9q9Lo{$ex
zWNT7>mrj#Y@_dStKawwqfXK95x&$U><Xc{chqH41RzT0mpQVJMtwKZ}La<XT3<mU3
z#RIBJu~+P{YzFI~sO3V#Q4vD7CXXrfZvgbT!hy>3ofPZoc;c*BLa!|sMFJD<yDAzk
zLga+vGY<OP6g{+xo>c5>gNVB#ekF*9Vv5d`o{E1d3*x1CiN5=CO3_JWEZ&N-Yal*~
z!>j20cUqx30hu$3=jk=;tH`G<l%L`pEu;R5)s#*MP;fIa>_COf6hzJ{7WKgGAcbZd
zK+h?HPN6Yap;`@}LKK4i&<j<VXfF_^=%tB0ulSmx-QkL-=n0Qd@Dedkk&4Vb`e;a$
zB884l(F)&Tn21pfP$5>VqI>~nC{E#91ro2wq|Y2AD1;}We?igsBe;tS^BuUIsJKg^
zza&NGHyG0;#RncxxU68D1ZJ}0dD`EnD2^1u-&DnUItrvIzWWC#>58vrDF2Y5h@JzR
zsc3xzE@ml82f<}4TvLITqc}(5@m$5zDKMC)_>&2ke8n@X0CQCl>W5)pQ!KKBi9$tm
z4M>p!|E&R!nqt@h$r8n;N??{M+CKqGnWBXf;MWy*-hyl8iVJ=)WVxZprt*QCijQA~
zeuX0P0j8!>p=^PPD#ds7yQ)@vMYp9<@T>*sEyZE_1YWJ8-veBo!g>=#>J@jMhF*i>
z*SqLzRE*34tVxk}03J3ggbGYhi=yi-^xanMqle>;;te`_v|1FB8F<sCkkYs7+7)Xb
z!^^%y@uMvoI~B8Eq4BQ5Lj(PLidStxx)i_DuCiM(Lfh{9it<K~9>sZjclIjUXnWMB
zI6}92`W2;n;o$?t$v5HsfTHy|kU_;Z+NlmHmeE`5p~B+a1JGdw{|B^=D9SHGe^l}N
zAUeksmJ*C&T(O@vL=y^mJIJKsCwf~>DUQ*;_mSdeI25K8x{tukD2{vxe`lcpZcgDu
zHJ-N0jAekfQ$9Ze?x=DDJ%9Gf&yU~_>Y%(}q4mU3nNPJ|$CO*8Ajg#vhw)c)QvUrc
z6rGj5>tNSKY21kkc2yoI1b0HYlJe1R%93w^c2fB-ZH?WPTj@mMp{$w)=c(LJ5d<&g
z7%g$9l&<%I>8<pjN*N#Jd$by!Rvx%x0X?Ji_lG54rLY-)5<jJPJwW}HyXZ1TfU=e%
zM1jf`^C5XwiEIxZJmp>&kaNmgbnPQpsi13KA<7yG0fZ{UDP<O>bV!015lZu)K#5fD
z)4@WN@_H$tqm^sA02ZU%X{Pu~tg^!qGI7e4w3Ufh+EIQgLD>-rjSI@v&d|81ETUIo
zqH<z4B$JdM-p0@_DX;W_TviU#7B^Y>AuV+&$|b=-NmYJU1cfwZ3WWvJmDkS$Geh};
z6Z$fh>*(c|r5r_O(_)pa+(s)wjxvJwdb!FM@hLm2Jmq)vYsps@{RwhK`NA{sqCi>Y
z545YwZ6)yHn)2Rjn9D-t7+sbrQtoL$U$OE?BrKIEe^3LgR5?ZWh0Bz;=nr~bInxM*
za%E>ZxEso4RO4m2sVohGMul<#ee9%C89;yZD&-XI*{YShDW6@V{3{cpx0KJ%!nIoE
zAM~~JI^|>vMp3U6C1Da8lxJnI)TmS*KwpzG`djohD;LqD(xN;<7Z+|TYv>?zM>+T;
z6k3(HtuUlEi*k7#XuC24uWPFgWk4uoI+b2WVeqbUK2>YnQ^vdn{VwH(SKw&3^43-i
z^uF@vQ0Vn2!)eRctGq3M`95VeopSn>8))@^pnUihoEcEws7K$Ra^P!N7*bwy1bL|3
zwi0AmY3Y0%`XkD;E|5`W^K&3$N?&?p#+6yL#7-!ae*@a2^1A`ROew=7;o2i*RUP!F
zl{S<|pHb!~!qTi#*$wqMWjAGCY*oYS(P*by_5u`+s$!{f#9p<J1>&H3;Y|=n)qYDh
zI-OK;^tn}M)dc0iT~y7qb97a`N0qTBRCfdzsGI7>DsU%NeVrJgyDE!*-5#na6-;=l
zR{aLoyi}#<!JSfV??Iop%1#b1d{h^FfO%RaI0=8xsODMF=d1dOu8{euM%U2#=dU`D
z1JD4K?QbA~s`V2X{aICV6wrcHk1fS7>744(Fw6(5Jn2LcqUw4YT&ODjTPTF7K6wWw
z&f_210W4hQ!-w4n)kp7xi&VKxf<&oasRd@V>SwA_j8W~PLsG1&(1k8d$EjB5z^QoE
zBD(*VpmOg3cR@8lJE4oJh+v>4s+LZ{ZjvhAAJcY8<wg|(msO8l#;}uB7bw=4qWX#I
zI#N{|Z$Ujx)k@jCbXDeZa2cu)0n{^9^;ZFwrTWz!T()W$ryGk^j%o?5in*!`TIlms
zm)X$BS8d{;@rr6&Be(+9j#O}0Rc#{Jy{4L@>f}Pz-*m(*QWa5%wOA#Z2U4O63<7qk
zs%{=c%2W}XG0^L(-!}oeT(x;M6mF=tTtVMW)ev3pv{a~CDV9~K8qLQ<RjH1xfQf3=
z3JSK@sE&+4|CZ_pS`=$l3)aF!o$7EeMp3W2PiOE3)!;%HY*e|tipC~Y9OZ7CRbSE)
z+oIaN72Ivrrc97KD(TN4t*X`)Fw~}cn-Zk$7S*MnFwY&Twbf|tRPEUZ?yjmT1m^Fl
zY-mf+rIOJ}q({~JFGPA(9&r%qQwgJCw_mk$3fu$L+F6JUsM0&3H>g_nJ{%oVP0-fs
zp=ur-Er(S_flwb&75PGMRCQznxG|MwjP4VRt3DNDh9*=Qi!n8mD(B@G_LPcijlM@J
z|0*<2s~(;K_KeE!O*GD`dOhL(oT`j!j&0TJDK22AZV^H6sCpYczV_->RBzy*4xpE{
zqdLF^3dhv%)4u4q`a@b(oYV^~^zjd8^_LW6bWt-`q0?18;S2XqsAW`n>89Q=4Uv=T
zG5Xr8ySm8?6CUcb(LnQ5yHL4;mwM+GcyUU-<Of*tR_`)F&qrO93UXTAxd`fK)X%&Q
z;;W7qVJ`gCta8}%SFaDVz>NU)2lVl)K=m`Ur#`EmX$BXh_V@zaId#VKfC*L)H~>3D
z?VSbvP&MyaG=`}+W&-BCx{A)E;p!PV6e84@|Jz)u&2*zON}Wd0g=qCZA>d-v-t=(9
zsz0MAHBNn%OV3}tI)&ms3F=@E*u9``q>D=z)p18L35n{%bTcwZJ@6z3dPyDS4suz&
zhbk|V)qzx}kfQ#U7R6Nc)7ycaruL%$=8&$wBZ7$xbp|CPGu7L4P{>k$F@VX-R;wrm
zoul4>L!regS3N*?k@M6a(w-|{9k~dKSJYu%@Tov8c^TMO)tl#|@0$AY)0o6Ub!Rs$
z6{+vVz{6to!4asJs6RLj?z;M=esJaLe0nNwsDtSO&`tG=R6kas4vz&&rTQ}?M5@%A
zPC~&_t^UXlpf&2VbcVR4ez6mzRvm)kL#sOVD@E|MUj4;8Fxa5JwHO+W>gh{pY*K$n
zm2S;y8y5On)N$)EwA*SG-EF_4KD`*ERb4cTzBcvpZ5T_t`aMTrcBpfMV4+jJp1!ep
z*P{NL4!ZZ$$y5Q-rG9lYu)Ed2ABW<7HJ3KEJ?c$U(C<~he*j#cdUFhh*00v<VDN$Z
zF<id38c@&u0QEt24=n^k>TwDdJX9|g0%cfTOmD3bwL>tVN7Z@s>l#y+eFiVa)t323
z;KqddRVr$mR9Db*Fr_|BGLO^`;~+Dw{<sn_GwRkifIX|eK~Kz_dhvds*=nK?L$k8e
zs8~=xs_CZfy1i!ke)!~|iL1oO95s{2p?6Fpt^_%*iJ`oQlO~}G(9W7(3)PdjXqYB=
z;i~!47TgI<j05!DG+J7dPiiu(K-@K*?a=qojQhiqr)K{k%zJ4(UkBPL&3FH$>NFqH
zTgyjN6bh8nnmvs$e@62+?IwLSpZo>lr+GFDeg2vv+Fb=`-mIfTK%nM2#gflzLMS&G
zq}fZwo#!+qR1FiXIW!6`L?h+F;ZRLE9i+lEvtn2}uUUQwBwVxIAFf4c`e-qZ)OgSi
zJ4*8oJsi=R<SKA6nr|*aJyye_5}8Yyu+N}yS<~S`_1DRoh&EVC*EmpCB13b4e(RZ<
zXnV-yYCfePN1o;*D$>f=tn>g(ndZAN*e%z@{0@;DnvW@~a8px5zwQc+KmC0wHDm3V
z!z#_x_wcD&V?#&j8ja#Nn7^e7rhr<V=IO6!|5>m3B?5EVpm~v2#YW8`DlKTz9A@D$
zZq}rYK=iieUJNYV(F7J^+FCWAC17Z6nuBy7r(L6@tU{+oMz5B;nt$Jc!aYrc7r?qS
zrD`a2Yd$;!_4}GdMS$+nJoJJ>pJpq)mo5Do5e3g4XquDIIiRt;jMhQTyVv3Okj5_q
zeGfGO*U>nvsi0rdh{jBD;!#Z-1@y)=`)DB;*F5zF>`rKel%<-~Jfw~Cl&0)`aMPOm
z6f&IAyt^J`R^zr1j?QUbcnB0*i}o<xi?h?dPJsw}?PoXOw}bX;I@3C8{g1)!F>N^Q
zosMg*dI0LIeSH`7U9<tT-*(k5JPq!IcI_yLo3@P(U?;UBR5<3YZBGaB)V?_njb7TH
zZo$wgZRpQ{_SSw%$$THJWk(n2Y3(4TNc^<()Uf2QeTEJl0orFN>l&zKI-u{Yc3TC|
zg0%6pB?!^FW@Bif+D}(NBuuNO%Df2e^ICWjsa^02`l7VMRIMAUT~rT)aoX38z<j*+
zwGv2P)b6A@%0%ri7CKfXX*W=<O0u?{0^2EC%_L+}wXe|EwlcJ#x8Q!JR(}{iWoch_
z2U@On4Q)R1v_E|a@AI{<J_YWI_RDY>EYQmCgS)EL(l4P%dp8D+#adl8xDxF@m(f?M
z{UjaGW!k-mEYQEM{ap{gZ)zv$(oBVRoYHxf+9?VtS83m+n;O;HttT)uHQK)^Zd<3#
zro(K#cKbqzG-w0pB+{%c<pQilYv{*s=C<}{s^DnTauhJwuFaxgL5H@3%1=ABS<SF;
zSG)at%KzQd?x#idf!4nStpnQfYG4m)TWK&uTKuO+`~tORJ^F^VofKyt(M~r&VN^Su
z2yRUK&6k+2ac$5Qh)ifNz5~0H+MQb<GNpB)UD6}%HUYq<wJXa&X0#&=SeVu7Q3q|Y
zn$wOtpw(6v|1W0NPUrX-JUyyY(I@5Xbr*jHnuBi09wLsq_)ZMwm@Z*88jtIuOCaf_
zlW<_kSy#UseJ(m?GDh#JW77fqgzleSn0M2CL*EHFsk0&r?z+i;(debyO6g9^DP8nF
zu--af%6$9iK8*l5t#ceg=Na9Hl*01WU0elFKi#_L;gi3v=yjMstNWOaRY5x6bs*<-
zw=>{ju&$17yM*ZK^*{;Ly;A@$!gTg|06VX1qVl(J-H#suGeY;e1dWjv-3}^9j?&f9
zWt(W-pY&A5=(-{R6RZ1;R?~Q07Z(}{y6fjbF6c5Tka$s7-3shP-IJ*hNz$>N0$Q?e
zqc2cWbSF#@N!2k4B~8~w-@r-N&Fh9jhR%x;C7HStU%|sHoyCeap4qym3-QOx(S^_t
zBUksqGQi~NJn8;!zV5_Z(7&SN(^0%YHxUhTO}F9!u#0s`bXqUbrP1P6stdXZ&@!DM
z5(?LKU)6#u*X5)^;fC(1en8*UMQ%i2g>KJ#AeFi;7V@o1S9%xv)w%<8h_2D)t^&EG
zQ=9{-)gAdB)7GFnbQR7t>UPrBxJftfAV8aSwa);wMR%1xj?}9A<SB4%y6y_-wd*Ed
zg!v9#QZUpzbpuorepff2>J;wj>ZlH-ODD0hU^2RO@6ti)zRr#!wLLnkG0bzX&hRu$
z^y!`%hDg6oLGRZGy5JRP9Mb8`aArg|_TOG!_Z0;o$8?&T=o{B<?S#UFZr#6dbW%6{
z4J=LRDt|%WBi*`H=$qE9$VB6euH<`K|7LaKduW~0+0ef1sGf5W#9n{t0t`CnyQreV
zQEy%Yjbr*)O5PsVzeQ(5C;cM2nBuITPlrMmJ$D1VaMc@a;Qa}G#s9#$>79z8?x8<Q
z3!kUHI1zeYdO4MDoYMDM==|rccgh2(kN!#v4EpL1YeD?<pVOM`uV3~HU;^~(mO?*J
zFLy@cS^W{png;8ODD)7b&!O7EP<<+egv0d1*I@9xzOe&bxIRA=mLl}|YH*SIBd<as
zN`HSX6r%NeLIGxp(MN<}ys`RsmO$~6{_y9JxvYPQ!p+J03mPb<=<DcmLaJWn1++B%
zD;b!Jbp5Vs=w;|P+=fV|e)ZdMJ4^rFZy?$Ff?q*$^ncPOAXi_R04`7OG7ozBdf5^{
zU(vg{0j$8H|M(5GUez~Jfcl#L9bdE->b>dJU!)gof_|~yeiJN}==0OzTB&}Lo})7T
z&YuB#T`xWi$#VS>ssX&A_eJX3>Zab;378dnhgkGg>P7TIt<tY}7Z$4ZWAk9XM&EoE
zqrauMY<>-Ft-g|~7wYt@%)qYKzwt4~)S#D9l)h1afFAfJeIlKCn)L%Bh_vY6J_fzp
z`dm7d-O*PrhDfV^3k90m^iQ9FrFOk)2qGQ&l^eiy>X*`K@UEUoDWrRPZz@&k(r>g-
zu&-O+FbZ$(>szm*wMV~`uAKMk-BY38r|&!jjeh-_kKoe-y+RLeK!3Ikl7srdOo$BW
z%QnOAL%sD~kYWAO6&U@9zGXQSM)eo1;P058Lvf68{p=wqOy~{GAd~u=0~CLm(jO>=
z;*7q0Aw*~O+awt1oPLr{sz(h^Zi0xtq2~#34u<>Bf;bx98H30%!)NsJJ8szR1vDo^
z0wqzL4MS`U)WzVq8+xvWK{iBA7&PBP!Oie^Bl=Dn&gFq~Hy9+e{&^T)p!B1sVfrs<
zco{-^;KeD!$Mi1pHa!0$#(T!Ffzt54hUHN(?`QZ~2L*q_mRv{%7<N)(H_#AA*DuZ*
z!e2yVkm29~h@3P0MMsEWLq7$-LJa@B1F%p-jRX3^3|a5e^LO6xBV{wf4ToPsXN19>
zHoTFBCM`f?48Kt^YOLWmdN0QrY;MA*c!OXKrYpgqcm$CPhP|(1*cS~Si6NP2=%UiP
zBttCybCgSlH|Rid+3+I8(~}LMyTGLwD(E6js^Oa#F$tD5!`4aomTuszgkpx_N1EA8
zLmoxxvkV)kATir;SOuSQ48PN*z+A&YT21o|pU_4u-|$f>$Q46eJX|X<i0Yts)evw1
z2Co@jW1_Lpu!5rGMTVs-&{%9R{0o#4!@NLvUurS@xe5AZhWCPD{<=Yz1MG6cFG=8T
z7*;KW#!bU}v?Z@FyiH}vm4<3ktTJTLCGl#*!x0#)G0X{|aLdr$0FhdQfi@U*hJLzX
zTyIcPXsE&P1r^gY8rl!RUX$T_x^LKQu!LIyt;O&oWlC-vv=o}UW3U|nTC2hLDUddU
zl%fpnh8ZVJLWf}&MJ_uHf9*%#U4tE6SMD~{)8l{NureDadJJc5!Sxz=DsX*<z<<E?
z8+Nop{ej_C+R6_Y9#X~gpy4x%4bX-R?X;nKX!tb{4i6h1GXQ(U@E*OPMh)xc!TgxP
z+ZP^=8~&#2UK55KO7%?|{OFi4W%%H4=shy*rDDZtgV7pxXAJl5KxEdi^m{<h83O6@
zh^;Zt8<=*+Dp#02YHTW@aHzd;bOQ`J7$;-FIU0MZ=IWSHSOn1H#^ry(u9NX6syTKx
zE~0RVi*X_X*sjLXZ$M5M)vGZkH>2Gf06l4RT?2J@<2gEcc^KDFJ+Y^8!+WsnWi&jG
zKgB8I1-hK)ZLB>)`9B}yTFU>OHhS`)c*gh{l}Gv-=SpDE&sg;koWF6+R}cv>-Yi06
zps_d^*k_HZK$s6Qns0!dGj87w^TEc)ufX3BW6!T3p~f$ELp{vcNAZXVqZ4iUB8{i%
zsfaS}&!_!ow9)k|urbD`C6I|V-lhOZoN;;+MB|OE+rcFm{oVx31><LNki2O8w+nrV
z#=Z1HPcq7C(0IvMJq(e{#(CG^MY3_}N0`wRW8rt`OEt#pG5R#4&mQ!p8y|lPdKtzS
zX<{vz#v?CbGO~<c763Hcm|qXY9OIZT?B*I>X-&>ER<8xgH!h`e%qzxWN~aeXpGXJx
zRiktX`mPxri_lnTG*E=8$e0=flw#x7FJQ35Xp2CTRjIN0FHByU@yQhsxo-T0{&_~Z
z#rQM5&~F$QDxq=Hc#}dG6~+d-Zc=IVsRCDJJo+u{RvT|oVz$QEqeSB^W9kx+T4N9e
zDe8<*&`sZZV;9|HZ7}jF4BBXXj>;*UjD_^mX*MbXVWGw7w+3@@+j#B<$Q`4li|Qm=
zjXnXGlQ!eZy)e;fJWCs~yT*4;!^Ayf|14m-jGa_X(``KR8YJ%<JCgz0WAxt#$zJ32
z2OxdM)M-pfzw!HTVE%#ebvhXj7{8-pjX~qLIBi%B8Jp;A_t3bRa`VH+jTU;2MvOb?
z=rd~UrE0}7V-dX~#*N?GflL^6lnR<O2K^6Y${71OU>+GOXo;ORc2K4FjB)c)pv)RW
zC~i7ud?E=$vo+1AV8YI{dmQGEngjxj%-$5d8F~(;GjD=8n(B^W3ubl9B%Xua<0i+A
zfN?Sf<iZ(e)BFqQb1{8?0gA4sOezdKVd9W^H&aOy^iP`9d!gWN`kQ`p9wvWEYIvHK
zT!v3xro|W0c*?YqGEv^95gx#NOstJCblS9lsyWY?Ox*vzKVjNNF9ko-qxYcbZ<?dO
zQ-CRV2hajd;aebj*7OGzw*;B?F@bi@G)Mo7Ce*aA1ASqpswj~2rWN!<j5JAUXC7tR
za~6`(rW>!q-#AnAI`qYx3YE}HFkNwlLaK@9ME4)kOk=-7Cfzh@2ZI@=CMxRAG^GnM
z>@3qMIwfVBYAExaV|t5L%3PC)lGJ&oSN1|O-{iUwmadr6z6VNy>25nLT{V40IlgPA
zGTOiunv&@tRAfpx0@sR7!&IkNV#-(u5lg9Q*(-o4GlhvDbKSIw3eC$+Za>1{4b$H?
zkhy6}nGeMZQ>O}wm8Nt`ELEAVPhy^`O}`AlryA2*DzUj`Vmt$sT2nP$O{_C5-VRc4
zN-u&!gK5v(7*eCD$`+VSrZlP(YCg5GhGCig05)4qnO|cBZ6+H!SGJq{k3+1(#0Z5_
zr|F%O;O?4^hr!o-CRr17yG-p=YtU_)rj7J{Qw7DZdQ4(k5PMDU(;ubJBv_8g={NmM
z>9Pl=1LvVWVA^H{ZqQ_G1~+6Hwk!qv(DeH*hz^?`RKfg+$&?Q4QPURsqmG%@JqNUL
zlQbTdCQQ5d;3iFfP;uXs>2Y^B^T_n<A0V@)5ehrZnO^V&wyk*$?Ii8Y$44-mN6k;B
z0?giALM8nUW+P=D9nJ3VQ4Hjm`Rm^RdfdE+-n&lbPm*BC*&IS^pNskZT%fs{(-uJg
zggJw*F1neoQikiK`3*YuxSL~WtKeZy`~&Kq=41*!dYSK1EyyXe-v^NNHotQkl0Ifn
zI!&K8KcJ=WjG1psckukpD`=qzFdv--cAz=vS-_k%XI}(NkU8QCJUnM!U<Z+4^S^S4
zgqUk50UBzKCYUg@nc~mq%||c8(QxxOT_6!=6BQFin%~?85@qg8fI_r6xgB6J=GfhU
zjy1o({^@xetm4cc{Q#JFb1YQ@CYXzJ(0RdJMZvs_<|8a<B%0eP2bW|%>ICkR*`@@}
zTsFHZ@i#~|Th)O}F}Km*Ak}>ARC+Df!d?rPvdnAgsG4m)&BgrWnEB7cmt6Dz8qk<$
zE~b-mzIne9AXm&~lmaU-4^u_(Rdd=_xO>g4y9$pA&D|?tpvdeYft$tVn`FGiy!}4<
zO3gKt6D>2ZrQq3h^N|!7DmQ;+p(W&o+2uX3H_fRbP^>V|7-7EBJo^%cQe_TZ3NNb7
zU;G078nfnA7`$cXt;6_g%}dQdt20M^fyR1sHT@wP%&X}A+-QDtGy0m$9}hvV*?gQ<
zk{0v94j8&^elZCOZRT)q$}F{;H(i0j4)dX546V~_NrV1f^S9M-?VfoHUD4_?Us?s2
zZnODA=-)T%HUX{2{PA~C?==^cLZQ#>N#&&d<~aJZJTTW#0)N2#F%{emnqPhfeM9Ce
zh3I=|o_rR4!{&XXw6hs8v(te#YTh>w2FJ`1UxAF9^XO$bWzJa-{YU0ED915vZljIW
zjCsuoh|HRcY2}<V_fqV_*2d#Lh@H)<ct{?#si8cRz0FqIk~r9`o{#BrwAoHsqhmJj
zyI}OkZIbXiuvj_SG*Y6;*~XfxG+k`YQ4qk@X3Ou8IboBYg%P^hc>E2tlQzH5xy;?B
zhVF-Z*su=))YIn51RA|;LcfE*r))&DDfYHGDh20blbwye(>6!@fO*DdC%v<LZC<a3
zqkc9Q-$SFt-{$ygumLs~KLs0T^KKZ1cGhMYZD50JhKQWAS>lJjV4GFPz=ha6L2u?z
z8_s<+hS|jY1cmc9w|;`%a2powE+cI6DEAy`(;N?xD4Q@Usfe~=-hufT8*VE|tj!c1
zD&s6RGxQCic$;JnuoG-9Q2EdW8|gZ57j0ULAd_gbHXZs&Hd+7Y=(^*wuDZCITF%Nc
zXU?YCdiLIXo0gS1+L;Y2t+et%P_`36KsK^eL_}mLQ}&c02*^-|3MfMnWWL|?{&ha*
z-t#@@-242-z2}_!d!B`40%P(RbYEg@UJ5S~8P}=k@iJo`<v)@b-;DsC%=r2<*iB(1
zQ~o2Bk@X4Y_X^{s7vShs#!UJoPa0#nH~P{U_CJoGHH)F5{dzXz#m~T9W4!qq@Hvci
zRA-UPSV_eJd5i)&@te=sO}qXA#`PvBEo2xexLU;Eg@Y6`UcCuY!f^f-CQ2E1XlGEy
za5aM~XPjOF3)dNSw63dQtg&Gbm5kTzl*6iGl+t^+n(-{n#SKOWJyvTNkJ>?M8A2mQ
zc$0C9LML^MS|Nb-jPH2>G%#jRzUUSsl^*Vmj7>S{YhwJsf!$`tURr*)Fy5v}(QSrp
zDgbvFWq09WD`SX)!EKBg*>)h>8ByLK9gL7J0PiwBqD}EVMs72%o%@V$D}nE1Ji7*n
zF2+tO-tT5G-p23qfT6z!@{m#N0YDEUl)fU@%lIk;q>u5l2#x)W^q-;S5##VSkjISK
zD`04V@qRXNPZ$ofDY7=maEV6e5W}<th^LG%=`}LUSVvdO2xA#Vb4MAs|A7}{49`hu
z9A`|SCD;Vx&4mCsF#GBE-Oprw0M3!Qz8%V(m;-cm9$>oCoqCY@j~fiSGS_L*=*E2h
zcZj$%oogrI{_|jN4#u2#GV{Bk^bpf|Ke)rpIomL$N0>({06fb4i%QOpF%Jo$?Kty2
zJ{rB4JSuQH!OWw;o;P#ZM<71T=hmX}B=fUg5MSoA6o2(&enk%oe`X`?TTe0P(E}!c
z`O0Z<_CTf=)rtl&JL%v@Ff&vPH6cv5ofv2+a}AaDg)wJ#!l!U%A8lMuGf%jHi(twQ
z0~g8MK}Eb#%r__i8qNHZ5|1&=2I@P*Tzn6GXPFu;l$~QnIm4$|Cht0?@;vkSQHaFZ
znIoeBUSO)<g3@^Ay8-CD$ZW3%m%#kyMf6=_dcOyU6Pdy;^j&5yptyb#GyE1DO=dp$
z28}7qgeD9omHF-j`mQj~snB<o`9V3nPh-vwL0>wvaRgpuFym=wkjeZ=5A#_}yNm~!
zZ039Ofw;zeopuO0%%C@c$YrWFU@&>iw+4X7XKta->=iI`G65)Ls_Bv~VwzrrnquZ;
zs%$D@?vsEkXX^f656zsB4v`AxcG^o+GJkprB2~;+DalvOwA0sQZZLWFub{1l`R;cZ
zMJ==c4GjAx)0x%)b<96Vw4V9(LvRhu_9;NzVm_G%u95j|Dzr5*EtC&$X3pIKEiKH+
z*U@*IxjY85c857icU&topb=afvuFgW+nN8o2SXjqpF9A+%N*ZC>ymrS6M4{mpJ|{-
zWGC}`A2{5_jQ0kjoB2*UxChMrlnZ{yyz>F3q=&grgvMUxSL*@qV^&i*r=Pi0085XU
zTj){vnCVJk*a7CZ@o?=4^DaFK2brl9*&br1B>?x7IsXf)tQcmdjKb0ga|2bUjWVO>
z12M+@l~xAh%pc}~n_wQGhmZqnxDRUfvu3!0b7XbX<>AEo_YrUhShag#@F1&@9u&?j
z+b8hCg=M3cqAP0;9V&KXby3}bJL^glI1g6TC-h}IPnPEvAP%v@XxV$1rT2!xBdmhm
zP<oVQJ_d4(6|)cqkF%Kc`*^Wlm<*9qtZa%z1hCo-uoTGB_rOvR%X<KG5zO-3i^dSv
zLkUDeS-+mbc*9tCD4QA1+7pPr)2w#-4vam5b)SOR(X66pfsbL;@F8=CRUHPqXIWGG
zA$pFre;-IJ%Xd4-dDh_{;b<IdcLzi+u<~cZnRwP_+8tbE#jb<W1l9|*+_=Q@rIkS<
zYZk3#FSDZQ;!a{6JO>NOEFJ}JQtT|XJJ?j#OnUfTVSQ2z(W|WglEG!LGN)j?nJlvm
zB#RYk0Lf<UJ_~Y<)tL&(9M+jh@F|xy{|#u#W7SdyAfGjbaxw+12NbL?WLef?@`_lj
zSs=x%VA|1?u+DyozEYNbS_2SetWYXQDQCr|f?Q`QDSB4HS|x)_CCl_TexEAVAq7Yc
zYkDghYgyYiL*ypwkPd)4RvLvq>RCxt{m{TVOQES-tW8#sMpngA%x@Emc?6`Hl_<vK
zwXlAb0e72~X72#K!>aiX+FDsbpF>R>OXv$V?JS)Fq=RL>kAdE0IS0Y+J=QKN3cAl)
zO-a~JmWIkpx>$*n7wcxt-2#yZtf2P+c*rWHO<oUcgEuVnvTQFxSsyEy9u)m7F4b;4
zV%h$no&950-5@+2U|pk4?Gx7eSK!PbtMLt7NyDtSY4ttAx)uX6%6f|m!NypVGr^6s
zc$8?JVCB+Dp8f1&jo=*F2}GROA!D$6fNiB8{UE!#4R)Q`4OH&r!k((bT)46~)y~BI
z=f+-7Wg_nEgS21wU@xBuXFS<$w242&cK#lo9%gT+<na;qb2niADEl=k`aj0@rBKmv
z_Ay#0d$AYNV)z8xpI#Z>Y+XJYec10z0e6y};0X)9>>ud_o*#QNMG*bj|DsmYKJ65H
z%3UZ8V1Ks&B#<503`;@mk<|bOvpw^{g|H9MMm>}rMGLVob|hWT;p`Q5aHrW`w4I4y
z`%wv3Bs+8=EJd-iLNJJEb_A^<&a$7OJNz6wrWEF5*~T$AdY-+Cs`c%0>^v_3FR*tl
zg{63Q7j1+tvJDiKO<>QV3+fWvNE^09wi7+eF0(!E!I>oX50th|W^?J9Nnw}Lk)<s5
z)rC-+&3<Mc;Mdscv;xavXD){MT=wb^^yRVt^as3v-SI8vu+Yv<sE14u`#aiE6tfS<
zL#Bj1?_0=}vHzn)L^=D8JNmA(XXc@?g8eHG+A7(x)v#O5en6?H8|>xu?5ts*i2zs2
zzE1bpP4*jfJ=U>HsLrCEU0n>326mhqL~gMwyI{VNZQrJbXcPN)BkVS_yU$~UE$lMd
z1KegGqi;>zVLwZ6+E%unB9LwDl{cZZo&8`p=CXtBPT9S?Y%f~t-D5kg2f5GwSPY$=
zZ0lr@F81&e;JVo%^b~l&-dPLt57{}CG3;S0?3cmzvZI~@+s78%fzp2V^bIioh|L&*
zPmkF><o5u3fYu97*zN0JaFG3t5v~oh=WmD75%#~d869PRPu25dY!j_p$JsS6Kyre;
z<6mgm&)K#VjgFj+w0Cgglum#g;4Bx?`|luU2_@oPI74f|xpH`Hn0Mny>6DN=Ctw1c
z2j>OK+Z^JAQ<CB^XHhe>9pUVyINec>bQ=1OadPN;g2y=t1HgH4=Fkf41n2WtK)gA>
zP%znt6Uu^xlN_g9i1>28QqleA$N7lP5&Co5Xc2yjvywut0h}E}7<M3Mh7Kf%6F38n
z!JO~tMG(R{>Hsd3lQ$0r!#J<d8$O&fi*jG5Id^GQ7{T#73xkoI>;{l1&P$si63yu~
zK_rG#TMX~daF)8$`tvMj$$YTqIM1BHZy(FKYysjt=i^`CVjSmJT5eq6yk><L37qO6
zNM7PRmjZtiInPnZ^D-xJ4ct!RJX#BQGG{XdWm7pdKZ3i$`GW&;l~Xncl4+b*sNy@F
z(@9~vOip4GaP};YcPNx*b7FR(^BTvy5F^atxRpaDj}vtsGn>yDzY1pxIJ1sHq>z(F
z#o<MquX`a`%$ZKnn-Y$<6D*Z-LUSNe#;K(|VmZfiDnzbxUfB){6&$z!?|C?PqtRH!
zNqr5ftL>avdjH+v<Wgy04ab~;q1AFKmH}~-GZG4!I?i$m>eh4S%*N0fI3E4zyT!?%
z<#QwFyXgQlacYL(MKfnDU4bo}Rg|i@&B@yZ?hdCS2Hv-F-YUV6+BkEY;b=SOB^M~`
z;MlEkuzQzNXn@Q;PMiYdJ||s?#%|6Ys$ze@>A4Es4>_t=fbZe_JOfI5If+b&^l?6?
z4b3Bt-<!Za<}|X<IKcUDCAcS?AvU}p<g}#2(o@cY<>(vcoLc}g!dWpBT1Gi`I~DGX
zan8~0G{JGDotpz!;|RO^xn6v5j$Fr7;GMW{{{b%!a8J;}<RI5S3dEV4@hY^raDS%q
zAy;lp4~Ff=T{sCickcc{a30(QZ%mLU_ba*{4{?Jiz<ro&p(Mc(E@wII|BiC4w3ax=
z^?n~Fj&l!Ej?#<!GnJ5>;C549z?-|0YE*r=S?8hqB=^n5(Cy0|`33+#?g|<F_2<Ss
zgT7PTcm7|W&kdzQltAtQ+6@MALzvJK%w4bxc0;({YakiQ{bz*MpJCiQiV8+>AL69f
zv`B6=?UJInRTQ?4=K8CFkKvZmM~lvIFHv0JEO-4jsEOseeg(<%+{MXgjN?wZ1}`pf
zBkAQ9&t32y8ZUBFC|sJroyY)5<l1EbT;@JcJIo~RuCyt*|B|_z9^<!2;npD0G%c0;
z5>-83;o5Iu60UMvoH4U$+}&rurE{(Kz-4d)s2nDXTYMirWpmetfV;*`{t6_AyDA@c
zbGaAj1W_LMb-FzAxlS`-zL1-shw38ki&P<0%uQ7SZZF}Et%TB2ZvO?CDC4G$09ejV
zqYP^W_cQvrD!Dr(P*cU-)&@j1cLg1CxWU~sh`t(bRRM6d+(H+SI&M}dNIkcgHrNf^
z3ab6T#T{&e-A1l&2^w3t&T`nh&D|OSWq0h{O)p~FTDkvvL9~tgsTW4k&i$A+vmM;;
zX;*fSTN)3<eQq)BJ3F}#Y3tL)o%1!cb#uS$gfkDg`IHQO$bIc^kY4WASJ2qU&FF#K
z{oJpY0q}?$K{Z>CxxW8_8{mF+7^<Ie?Yoad%^>&r0+=7-#(e|sDYwfDJ`HofIt0Wh
zcM=0?#<&T|aCn^C_5>rG;GX&$CLDOPm!ok%?;BeCIP%_AL-GL6btjY^<X!m_aA#fw
zMJHT%Uvz@F^49(c)o#4<0^r<vq4xg(^yJN>vz&)`m#CEgFmHGQjYoL(S>TTH{-OQu
zG2VOs0eGBui>~z(JkuWZdGmH2g9#sA0_~Mf^4@q8#Fv-G!XQrZf}5ZvfVZ+3l7YPZ
zLU2L6kZ0jqFweaT-iPouFQz3_D9?d*&*8jjZjd?6OWg-V1h1N6q>;SMZ=x}Z*F;hI
zXx^8!QjOtdN@4dbuh$16=XlI|G{*8?plI27UM21C<9IXLVCe$yt5o#G^Ac${c#+rj
z2S@_XVG%?w@d7r`$?8Pja=I;&c)w4E`^mf(%Cw~L<j-LgsXPzbZCv5))Z^#6%IgjS
zFpc+g7$O<G+DQ<}<ekugWbxP(eahz9=^b^ASNtBh9NsM_OkOVU1<HWu^Mb0-Sil>l
zuu&l|1bZF(v?AUg|Dv;)S4azm65etpWJ-B|9|bArRrsOrI`2bT1y}H1plD1bFOn8w
zRXou?%uEeWya^+$<uOEX?IzEA0wQ(1f9V`<Jx?Eo#s=O?uR`P&ZzKq$iTB%ekY--~
zT8zxz!dpWpcW?99yI}qfZvnkCT6xuUCAIPDsCuG<S3<Y{UEUq~ZpS^|opHJycyY@C
z=;VFb0fSw<um1q)=9N=$@&WI?S20}=c^+lpdUz2Odg$eiQ$nYo$E1hIBVGYLk{;W6
znf`ENfTvjx-A{OTDTg)4drGyjLp+xc;r=i$e>Da=!ke`OlB2w)pCCEL>(~a#ao*-W
z^iA;Ai13Rz@Tb#C)sZh4g1=7uA1P#bfWLtjTL<|I=;h+fUr9?K7yk3pA>zunCm2E9
z`8z51?ZMy2g$Ymoi!P8k#MdT3_hJ4JZMTo{XMKuM9Op|Y<>$q>{sX`X{-(L;^X8wL
z1%G|`f6!63lYI3Jc<9G(O9$uAkKYQwDgLBd3_F0oW-b~7`EOCCB8Z=7r&U@o|L_AC
z4CP0zLTea*JH0x>`L`(wdz#<w052l=5mf3O$zOB{gNfpM(IPFHzbywOhQErQT4(qN
ze*pX}|F;hy63h3e$HsYnI(--+jvqy5BrfoWe*}r=>vp2=B7fOKsw_<4^J`!tk^kv!
zkjwmr8*n&@A3)ifWd4@#;CBjNO~-k!@>jnKU>g7aKQNfiABzJZgTLznNG9Kdw!~Td
zU&zC3{%n6V=I~imr<BXrd4tR2|8@=L^ZA$4VYYyOYBN<f74oBLnN!4{Iuo5G{EhTh
zE9EbJ290I>*AIXz=YOk&?(6){RnT3*Pol+tC4U4juxVBNBFf5F^Vt;NzQOO}16RZM
zo(z$j{B~Li)$yegn6KyaKEaS0_<!z#vRnK&4$(jBH1el}!<#0)>{oQQ@Mk4L^fo`^
zSv20^8)*gC%AfNpbhq(eErZBiem^Bl@9|Ak9Cx38ycv?6e8w#p?BX9@46d7Rp<=uT
zd@IGpd-xVAm+0jea6$U`-c%Od&#(Ry%IuH$)&)@Wn6IH6(g43E3EUvxk6t-L{I)h|
zd&=LD1a6rBH>K=H_%0N^8s%@R#jwZt`zhox&Yw={y9s{ceMmY8j?!hhU$AToM(-qW
zr=pJo0_8Ix2L&yZ#B&y`bOpf0E|^6dI9I`|m(l4asB{6sL-2GXWIP3$OVD;mFhmQn
z!-9RZQ#>Mg-xDIo1urIp^Ac372X{gc{Q`)$z->N!@)0y{##l}Y4$Q$=d<DNu$0Ya*
z{(B3<J|z$j0T&>+KsEG%0=tkB@j-&&YWyU@f@QSW3K2|D1Tjp|=?X-+fJy7#(}I3_
z(?$r6Q&1;T@PP>UC_!mH;L!plt;J&m9du0ljKJp%B+m-IUx>bQf;%5U=Xt@23IO5+
zJC}jGAW&|FWW3;e`*O%!6vR*&d4gboV*Qr{mpq~EvfzuKFeOQXH!0_pEExU`h!nxf
z6Oc?5{6bIZG{Ia7j-(6n=((IBsCyaX%@lO?0iGo|Md|Nsfz}N=uL<5zU`ROvXWI7W
z3c`xem@gQePw&41!S?NNs!*_!^5#W?F)d_@1v8A$T`Krd3SgNa`U~`x3p^44tPnh2
z22v>~p~Fp8f;ALAtro1HqZT&=FHzdEM)1WjRM!g9&cn4j!Ifhm^#WTjR5u7bX8~|a
z@ZUJ?{~87JX!Fn{7}|o)W`P3RvT3&kOP_`AI|BV_SZWpUW#HNbxfE`07tEwgd57R_
zDGc5hETF%a?G$|Z9R|@QXr%a9x8OJrk`Dw5x^W%~#=nJRkKkh}YV8&LLQBOy!Bad?
z?b99!nh^(`_E^9xg^L4%Hi~6E5qzgY<DlSRIn+EA9H3)g!-BO`?J**#8bjllU;`!b
z#|1ugf^S0b!fy0A2pRw3huJS&S^_POLhA@PC*dASSR54cYar<?ETjmli*W980PL<p
z8&$Qr3D*`wo4ZgQ4ND%vbMy#5Bs^e(=wacbGw3@ajHI{!QK2_IvyTa_v(a~47)IYv
z@D>KRfb$VL{(*s>6t3P2&R2MWqU(Obw<xCSFJz>EJ0*Obf)oKlRuP;Dv<tta9AU8V
z`#5+JBK&{@E>yU817yO4GwHb;F8s6_KV^h)S~FaW6n^9cFQSA7%9_Rq9hYK+XM~aO
z1AbP>I1IPX347%rvBFpbB+m<rG=Rqm7twLEcp=*hS}qEIqWdR7XlK(I)JwwQ*+3);
zKcHj8mxY4|(3m9rC;`_+ityisz^4jJlYze?{O>;OUKJ+MYd=jGCq!eqFo@ECS;8ME
zET1iG?+5&va2=I=<_LeLyD3+Aq7)=gxNjEx%@+<)9=t&Ksy!Mqg+fmq@I^xL0gz(h
z?{hJj5@AaxNU1P%Dn!eK#mSh9a-oG%gx7@$luoD+9=`)GDuwCmK&pi7zX7NgzHuGo
zhVYpV;BE>lv8<a`Cw#jI=Ie#;Qkigr@HZ;0y(OG`nogEA3O}Gqh$i8tN#L4=OXywI
zB3wp=y0?Wv6z;ks{D9JztwIwWNN5voz6jmz!j~!E(jmM_g~4})msqfLPnfwAQ*vK8
zm;qd;(3wt6cL^761-x76MYltba4i#F^a>Y+(EG1Xm_^C;exb1kb{`2nDCGZGn5l<}
z0io<YD19QV-2<hA!hTwD4hj1x5&cwH=!=VGSXgx(UW^ELQl-hLFytD@m~f#DfN^1;
zBe)6SWSRsAkzNa(`$ciP;f15ffHENaG$+y7Z_(*2+Doe)7ttRYIP5Bt($NPu(SHHZ
z?Ji2Qf_R9IE{3C?qMyj%A<>E!ki()g@4&<n(K5O^kBWBBftKT<?x|?>60N2z@d;7F
zWDsvr&zCUdBdVe^7AHjx=RxegqMP5qlAmbC>llo`=zEHNpAub5MQ4EMJVk7RL=rzZ
z94z{j_Q@fl4YYy_6}@}~xG>TCROk{enmmTa)1qC`n3)LCjool2Qna86I-^7mGx30m
z7DXI@$Qh9*)ta3Z$!I-w&MpdT#+YJ7KmP*V=S3bXLE=O@iuqj-y+o`2c+szvYr81&
z8b@P-sCF3|FNuoVA(<pvOpD88QQK<}NfEh!17}i2yjhUEBC^m0aaDvJEp8Rjdya4>
zU9^V^&ND;@-hnfjB6~5tNU}tCCm?!F^gEp#%n@Cs576X_ZVmyMC+a+kf#!>{>0kN^
zM0;fb7K-%$V4y{!dJO=@A`R8>l!y}Q(N`)m9s|5w^!s$o`gPILV`!`pEu>>Il_J{>
z;HpGP64<L2)!6@li5nu93?OPmk4|AQwIUlO{BMf>`WiBIqFJ<|X%IPAfZP%Zdm-5<
z%BL%^N%U1ExMtCa3rLG7U>$I`Memy+c}Jw89d)bd>5I_WCK{txWV`4o9hSQ%T3LW0
z-533~#12HK=r*Odx<tX0c<&Y+UJLR-baes_KNN-k1z?Xz7YjtM=pF^A`b2?R=<XLC
zr4-g<k(SO)4v1#Z>4Ybu9Tu1v6n#<#)kC5bPdM{bl&1k17OnPzqa&g<3!rRN6jV(0
zFJq#$AL8d47ya`kWE{lH9H4u@_^sa{>L^ZI0i{mjT&kQpApWNb+(B{NDG+DzH!ZN_
zA|9p_2(Dr^&6AthlL_7K;!~F(;wjFMq4AKo@eZ6hEbgGQ8ArrXH2@qHzk}=1KJA!z
z3O%Neiz_KA<0TIN|HeYRfnLVm;@fV}<|9s93pIXX<w<b<VwV>%-c#cLC_Nk?UVZ{3
zQ2a4vqJqSn#c(@Ve4Sq6A>!9>!cwUCF#~`w@oGv)g^NR;g`o)X2yLb9k>Wo$Kr~AH
z&rJZM#c33?j}h;n#KjqLIR($oif_z?hv&o&3*b|%SW4Av=f$7C0$iMUf?izl;`nNC
z7sYI<K}rxmM=!TaV$V=;iQ?T<M{-#_PG8na60dt1jwXxGY=zDgySOG7N>jymKZnc}
zu`6vx)5M{l0-rAK&4;B7v33k3Q@p+%BujkeBuKV+$1nIru8H@wz(kJt)Jc$Bap`}+
z<%u2XVURCQSP#`jVg{|gi^ZQ015hGvdKQwU;$gb|%f$9;^pYwUe{=-iTo)gw2t<YW
z02M@4iqomQxk@}_1fp7eor;!g#D!GxSSy}mL*GsDTba;ZC*Do3m3nc2AM7@W-wuG}
zE%8yRJ8u-X(sry#{5mOX7KhREyhYrW2$4JD0(%o^tJse|k<%uAj!w3;i{Ga6v>oD2
zv~0L5mh__Wo>&_LOZUYs`(dI}Y<2<HC4OTHM7qV(93b*gype9M9&xe-mU_j!C=8-c
zTv`Ly`o){vK^}?gw*v53{6hnL8W7h_wu3$qzqSqdL9vTB5JTbyG0cyMm(t#4RQwDD
zfycz_Dat-BUQe;N330|b5C=)eP8i%T`I|g+l)M%V;v~_z0e(PIK&R{uO1|BW8Fi7g
zQU1VH@|0GpZj#q&pX)9e^Q3=v^pNN@@WNB_JMH)mN%ro6(!&z}&oR&=l1Vw}J1Uu9
z4&BEj5%fUzlI*8LRVO5Se*(Z;@_ZR|`$%roq4A_-3H=3vuVgMAaPgC5kU@XR{Byva
zlDzmbra3?|m%d>TC=rLz`ZHKEB@PaUNRrf;no!AA9k?*bT*@egOS-8f@3iE1D$t9N
zJf+4+$!>ZEMoE}AFtljN6N<;jNH)+L>zrgd3wC2ATWOnrUUGr50&$Wq+VfnHoTrs$
zyksqH+Am7{>w&W;NJJDvyCjJ@12$3ed>^>Wl7E_kNS65Q06s-BzX~K(a-E(DS0p1F
zfxjwAp|@$8<oj;eO_%)lIr=grV-#e}l*r$QYgv*DDma=gd7Jh;Ig)u1;BqCsXW(I;
z#NjoNe7j_na*G9$CVK4`O5VE#e39fM+SnIM%Kri>kwoo=XsLv?1Y;_bw70<gb;(OJ
z;BSRwy%Bwt64eA6t0epBluoteY&LY>kZf27QX^Tj1zKt)P9aczQ?mXdxH`$TPB>F9
zvA?bZqERAR4D(HrUuZSjESW+zb$28`?nYm$<fnHq`ZmdWn#*p9ZwL%NkbFbCtA~<K
zI=J5>d3^+=S2AfkNS|aOt&934X-P2gNb-;>^BzmMKf%I)<acKb;)&#&KyZVS+jfd)
z3`rUmqxGpo|1Cs^CGKv(k4O&Edv{dQN{_TL$sEd1j!Rq|K_(=7UqhpV^yhy7*e^Z#
zJ0u;YzcgZKPSRiSj}_AnNHgEVcn?ZlDJ$nJmCG;|7b$-q?72!EsnFC-TKzfY|J<dA
zD9Pp_{dqNp?I~@g{QDuPA{1&4OPi_c;fT~u54fY!z+eE5NgcD$cwG8U8aOX$Ds8Jy
zNK0teyrn)2^!Z5rzQ*LAlqOt-7GLQ&WqbXk+vpALFHLR$IVFvFj_S_>q_Zgh7buOR
zhggtw>>frREPb0^?IF^sw6PDBI?#_ECQYS<a=0{r4W*~079ju;(w}nxkCa}ccX^a_
z{8@}8TKaS;rX)ssjmp8!NL@d|kj_e%QmpTsbTk?wvC?T{Gjac&ms%a*cbs&HUYr-C
z(R2yKOW%;g;6-Vf38D$oZ|SLbN&0sbd`grq>x9T<X;usRlB63l(U>f~LuCgk(%)#E
zpDI1$0l*dMB6l>VOTUuB(G2OCaNshf`)I9|C6!SPgFRb1vlKGdq*33YGe<g;DnN3j
zpVy)@Pdb|_>+_|r)5@<v`sFw*6-v*eZf;tUR6`{R#nQcWv6V=-2mmjYUZYP$l}Y!}
zXCca^p|qI2F3qN$VukcKy8kMr-ZnH=Ni8u@U2T{8P=@A)G+__CsF9YfhTpYPZ6_LU
zO7#V3tdqul0z|#E{4UfqNJ}W$d`l{O0ey|qLtCM=NxCQ*fM)408{tKZR8Ie^cUvmB
z3ln#wS587_t5i+_xi;yFECAZ2S#)`HNbSFVkIuW&iUhFtq<Pz+=Dt)YL1U+sOE2s$
z>0v6U>Xt5{jr{|u@261nQ2GMhjXl!ODLvIIol*jkK4~c}wELyora{>w=_<-jKbC%c
z3nBwjNeApckw*K#!$GOI9e^Qe_5V+nJ(X6{2#2L#(3*NgdT|AYHY#n-g3Oq7A_iWJ
zOQUJ8H6dNG5K0|nmnhb;Uv@bdB91caa)>y|9$f%;K-Rw+gE%O=M4<y`+4p<V=pyro
z#E@KN%T|JOlYLhW&RyoWmEtcRvZbGac*>ZI(0WKV><dqi%A%ga#4*{<m1sOJd;1c`
z>m~b}YE4ea-d_%Yx2)j@^!dpA<KXs5S(ON!uT1m*A`{tO`cj*}jC%`!Q?e%7%>~F#
z3*cIyY{n)?2FZN0>HZ6r{Tzfbg~)1XJr^pw!o%ppWMf@07%uasu>5J6cLGErWWVqr
z5-D5o3rLh~`wCoo(X#Yqa5P4ij&SC*GqOgCdYzRW{ThAeWWOxLB*e-dP(jpr*?0-K
zIN6We0KXu6cRJNy$IJM$q5Gn21}zH{WVa~+a7orq@qt8HCT)E#%cL#Pog{mu8$Kn=
z{3wc>BI`+lNUE%GE&8s=zNCtZtFlmv)u+jJeg=_rSrA3pGh|=VQ!iU)Ob6hatny_5
za%5lYF*EjDnVudId9q2rL3h6FLwaZz$evQ=N}(*G8rq6vYw4|4EGy0hutc^p7;{-F
zI}#1aGTE$pOli5y@+%sz%jV94vI^O?*8s1UP5lVuhU@~RkZNQfZ3etnc7%e!H)T6A
zAX&Fe_JJO{>t)~5rlmnPhiW`;$?j9mt5G)f<crTve%a3d3yrsBubzU)9hviUAg!{^
z0;p+|CG5fo+hu#{vhI*&%!i4)GB#D~-jii~0Q2`{zEnWjDbrHIze_e{2&7wP{uuBF
zvWA!8+C$l@&oGD{nU<1Gy|P^TGGw2ur2u{XvMqMH5+2DMDSY%;wkQWO12R=1bU%@G
zTm~7G-DSh4Az7#q+*8@&Pa!faOBuw^JR+070x~KKiG<QI*`^$fY+SbXH;7EgR-S@u
z4sx{vRPUEZK7pj8+);`_ILVJw@!bLW;^}sD9+Z2~b>S@koQ+Nw`Crcf=qlI!4ufv;
zU`n*O%cuMWFFfS^^ziePpT7-*hvacS7}{ZZKP`xk$bX^|sH5^bAA=l|`=+DsxO^l9
zl3wzHkD=^@{PwG`>n)eRi#{KD)+svubyB{WPI&psy-AIqeE23T`OE+Cfaodtg*Rb7
zKyG&i36vjs43QwYVgO2m<q=fH79!tR0}?7vpv6O&d=^#Kh08zs5AaC2obLW8`3Lk7
z)@b<vUGXvU@90d$8F{#xYQ)aUIb-nVocvZbOvK8^slNBT+?7g?<K*MbXuKfz`3qdU
zJVgkl7v-^^LQR6)iMAk@<X;3qccQ$v6WnF__w=w$lJBC8Te4hx5{)TxA?>(Q<s0^a
zT#+B#2M@2xIaJSYPm`~t9b>wD+bfua40+I(;4<ZY-r%z2ODL<CE$@v3xhCIw5V~{Z
zAJfs-T=_1FSmw#y_hCx%<)PoBuRtC#3AjS}#+@)xBtIp9vSPXG18^mB;aza0^7&68
zQYPotVVcYB^4Sz+zb<c}Rd9v;VGv|0<uS?dyGrhT2rgF3H_Bk?hP;DT&o||p>0h|(
z<l`4W>gB7#fNPLHp&j)t`9dmxYm|SO1817#zZOBHS#F{?Y>T`_1IgR+4PCHsNB-Is
zSZI~o`@RLRP5voeSM72s9h2*jU*(|juKXn}$UXV5voM$U<)Pc4v{Rlt8(f#%Py=n<
z@-HX^{y_ffc{Dzh@1fU8kK9T}LVD%*XwB3ouj9k}e)+Uwh&+<7qou@S`2mWN49Iub
zDQo*gerPGo56VNSFlk8M--0Q9Dld!zVpz`PqHje0_fN1iDtDs9(3t!neKKiWUPi@=
z6Y@8xa>PLqEkxgbMfxQG92I@E=WtRux53f@#YiH^K}F9h0Gt*3C^PAzkguc|rK=)J
z1-zT0-5mzq6~1p^hCCE*^jh&$aD>oyNYPB?3WpVrUjcYT@!9|yk1Dz!z>8yw-#>%o
zam5TeqVJ`+N*BZl#jexn^H%6T0`XB~(_!S3iZLqL@>NWAf)+o;^f~m7@>l#rkGoTf
zktOggK+*abY62BaRDBnu=$QsCSP{Amzz~H!1s;YfE<FJkrg$$HYQhzq5OAjz0s8=m
zP;B@b<|7pcY26y7=tu!MqbR1>*;z$CEs4)5CezzDR<XQt60H#xQX9<2DYD)JxuE!J
zC6vZ1o~2~fMa70KAPI_=3IH!D!YIv~sJQYH$Yn)S0Q^l-I8k&VSyA@~yhu^(qoRjY
zMXMLITu~hV1>~w?aRlILibDmkkgixpal{OTKLu*-nF`)ybY>~c6t&J)tl0?sHO0Sg
z!$gi^*)LF<t1#1)<S9~eU@2cQpPpU?iq~`yDO6~S04P$d+YV=n6_04OQli)_!6cL_
z_SL~enPOxrB+C`ur{T<X#X>cdRVbS2+<v89(N6b$mE!D0SgKa&3=qAcD06~LjiQZS
zzqN|76;OIp@ku`<>lB&v+P|gvONYir#XFu*+N9V|l`hSS59#x7EsD{1(Rf?IFoC<H
z2pfSjt%|{W@UTtsu_Ls!E54wpZ->IZiX6VH5G;o1J;k<D_<ipywop}Or{X{Q$V-=^
z@*zmKVvwp?9w?GKpzWcey9g$F6c6abqrD34I{4eCNTG8}{ffRX;PxX$ycjd{Sn=Z?
za03d780McSA}AI+s5pBWW``8b_5`#(Rm`DUykUjs?`R!SEPEb^QN^dtn36GtYXuPF
ziiM-FJE8a|3<e#PTSh?kD|xg4bX3;Rg4Ibm@+RCqpj=I%#)HZg6pe9KI?+zTMaljT
zI$f3dLr~_X+(cEr?#jJ?(aBE_<-hdH99BxGp7MxtCWX+CDpePNKc;M_h4yjfv-9AL
zmvV%H4JVX+qnHwJ<vpt8^-*%EWb34IdLVTBDwlH6=coLl2`2oNhiIUulvVVi4Nx}I
z<~dNQ+Ydm9a_4!9k%TJUSTGT$T*QZHxN_ApjOn!UEJY_Gl-1c#8mYV*1NWnpNr@oQ
z%CvLP7Nd-%-Rl|U>ih8NtnwSm-JVk}A`+{d9E`s6%Bn>eeVj6pk}nsO{wAo7S7tAV
z7Z;TgDCEGuzbWhHLgte4AYF5b$~PV1%w^?@Objhad2t0Ala&!=(3YZ<Jqz=xN=_>b
zUQy1Yqi<K0TPV1Zru5qY6Y0u~Cjew9!!LnkDl`6tNS0DZmsPfMaTsvdlw*7-%TY?_
zpwXVI%zX)#@|0qVMdd5Ip95E*99jTUsH`~wrA5jSB@o5R0op*7D0}9?-%{lZ{pc%G
zmeHo6T>0|z7*mDvk0O|;RQ5~*sZtJW(O0buqk^Uz%5`tRV2v_w6C`Vu*C`cq)2<B3
zfTcR+qh4sMR~l%78<bI$B)g^jmO`D4N+toDl&{W(7tP8dx)NHHPqqNxs+=SPyiIu`
z4U+B3x8Fr$hw|Gf!0#$2E<xu#<zMvBy{}wC50Oq~5j{P+l+J!|ty^jLW?|S5lmS#y
z^iX+70<K5NKL(jzWdQ@)`jo3C0obqHMWx}7l!<SFd#wEU6X+gLzV-odPn07Ro*Puo
zp%}-IQaA_BJXP*spl?{&LE(%M<>l|8Y*gtJ3NogwFN2|RWwAXT?oTLpMnb8BYW)g~
ze!uE_+VeQ7nrUI;q^f!aA_r6}sXYInYIG%(I;(zeMW2gmfWkMfs$n|*<fht4c~W=P
z$5KdosQf>H2~X8yN<be{y-9U?hgFx;06(IdJr0qhs__+cTO3ner;yfhRaP8E=%p%(
z0y&}byawW}>Z$|YM|H6d<2|Xmnv4<ps>c0c-cL0`myo~eGVNzhsb)~VBtW&V5`BTH
z3_92qr0PY6W?HaHSPjV#RW1d~Lscs%kQb(EoHiTxU%1Lfwa%wie?Nl32-T+3Kt!t2
zDNG%u@}}<?Myvd8!iyNyQF^JKQMG*mz*$ugZPU-GG~rMht6DM_^K@P{lnyRV_03t3
z3o7Swh{UT_P`dM?YH>2)391crH(pZZBKwGcpHj6g1$$YgpbFI_)kj$%$*Sv}u$!XV
zNM(kps^^|U_Z5|Z(jQk<#k*iWO%=EalIg1R^a#yRJ)$D3Ox1$`NM@=2b%poYs%W}a
zb5+j1a3)VRYa<%-RqH8IQ=kg70AMdvtqwtFk;=UloyDp{!RRbeO>abJscJA1ePyZ!
zIw?`Eia3s+>AK39Hf|NF-$G!iQdLW}hgGVn<VCgW)e(>zs+rdSs8Owa2L9HnHq(El
z+*DP+gh{AVxzqR8>Q(R0KwpDhRjvpAmTH6!H#DkFeu2&=)ka!AH>=jv1K6UPq=hrL
zRiC~DrFT^S(0-~_)z5)sn<{A-9=5A~D+Ihlb(4yA@2cKV!;5>W*QTQHzUs9=kWN(;
zg(bRFz7#a;R-OC*eW$Yj;R!VlRnw;f(WBbj0%v+vw;0gYr|PCFsbAHy2Z%?i2UO+w
zShaj6v<;{t{|5I&l}ZIogDMkk&W2PSbaw2i>gXhRF|3+IC$UFVeH0}hRr#I)H>TQ2
zPl0h2_buq0Q03Uo06M5|JrAY()t}NX)KPuDA3iy$eXgSMfZFpQxP$88KLK=Be@L5P
z7j@acFyX3xkzV_5>KaN2yQ@1XN#>#MT?^u=HZB7EkUE}r8;8}C+97g8y=EI4kE(C(
zhS_84MUHm3e_Va%br3K0%=sAo33cXLbo!_VrXk32QoU^r{PtBR)6M0lj^{$Rzxwku
zkW=a^1sVg?9|k~opt^!i>ISKE=|vx`uA!q%A?l~Jr43d4Q{`5ex}1WG;c90p=Q^#<
z{Dl5}Dnc!%)pw-YqZ}iQQuopNHCp{}E1Zc@hkt{{GwKEJ!>6-q741vTsY7xh606Q^
z1$SQk<pTUnaq6$%hL#KJ=L6tcyxNhTJ{Q%MQ_+{8?xzIWCAAYpSQFJxc7eOBPR8EO
zJ}pVzMBD9TwZI#lDe4(&%tfj?b{EuKQO}|;rCwF<Aroop8rp}YtJ5f!o1yNeWpk$b
zDh)JCy+Qyj*=j~7$ThWwj(g;&f1u@luKG8M@Z_mmDIA}#Uh)P21?s6`5V04jt&`AN
ztX|}S))Mt%%3YPJ)eS(Dscp39DOdk`1qQFHf9r#56>4z?xJvc@x4>1YU#5zpYITPI
zqrahUDaCZvsF%>CSF3ja804lp=|%L_sYhvlUay}2CP;(&wZmw<Wmn$`f~7{a<4*uK
zsrRhHu$$FM6hmuKf4v=}zpZYh^LuyHGw%Y}s@^phq)ok(4&t<{FVdc+LoFNw;I4Yt
z6b#~?`sgr}-B)X<f~r&PPZdyI>XTt`rdz$T2jqb|#{lwBZ7+EbBkWPfnqZ<=eTh!2
z_o+{Fpr&7aiLUiW>Tde-*<*FYA3zMKo67)rqV7tB-9feeIXE+<{#J#)r|J^Q_YbSX
zY4JXye%%|5qw3l};l-GG3B78@)uR;<nNSZ?G}A#-XP3a!{hGL=AO|$8{})$ln*3nU
zS>w4A#6@GIyp*eE%iADsnqrDUyK8a^;jf1#wFJadlT0-Xhcs)y0C!m9Kw+{Yn%*H8
zJgP~jJ-{)|2fh$Fu4(!k{(5QVU4y+78r4!eJoVOaPGN?8H03^!IjNCRrJAqCCl!r;
znjN<x;;*^66y{H9)|Y?;XkH437lE4jzo9Qk6GKa&U`<y)`a(3@DV-LoSr7{nrYZA-
zvT%))5_54{V^|3ip_wxUBvO;wOlK6LG`a5rAFZ)d;b@Ge!3c6j^F5V*oYl+;f~E5s
zwi0UMG`~qO!V4N51C8+-8!5f0F+PH$37Sp{re4z6egR3;ta1YUvgW<3AW53}!LX35
zc`qD3rD!JT;g_nZ|C?&0uV~iNcO<TAKB1XS)A*ObQo1H#I)E9PPfucmnVJwG8nZNO
z={C&P_)~fCHO=Qqz~yMV=+l3>8der&Jx}AY3?}k5%P2cmps70uu23_1AK*nAc{2dT
znp!H<DbYB51`&IyMoU*qnWp|z$dqetorId}nqmiZR%kf%;;Yn@N5cIo&A~)8R%_<*
z(0D^L^bXY2Xj0!tU#(_d5a2g8Tj}Lgr{Q&AX6iMYC@t2YnM^^xTbk#df%lD?bCjEC
z()=9&WzC;xF4Kq5S~M%H5WTJWx)EybXfi)WW2<H#?f=>|?-^mDU9+6BkoPoGsD$^v
z=INK1u1?Jvn&2*t9|ilmHMjPFJkUIQvU17fRrU{V0QX3vc^Bp%YYrEnZ$RTS6+ht<
z%>YGj2Q^Mqp*Exm@PW>!nyrf<GOX#E02$E?(0Sic%?l@>WlXb%evom^=?Ive(AcSf
z(Lw8YA0qp;h9#InM=gh@*-5+Xc}&a!ZHYY^z=PU*v=MUF=2A(ki?-tq)VON<T!3)X
zo>~UHyY}*OG<s+qsM5t#JFpF-KBQ&zfIF<!(?a=(_A$kdeYI7wu<NJwSped%y-npW
zr?h6;F9v8E|AcFS+Azw<1ZjWL+JO(&Ceni~MEm}JaG~1&>L41XZ4HI_aP0!h8=lsx
z9sm)c719DOQoCyx`l7T8<1vb8Z86mv$7tu%9_fts&Mi1|R-1bO<ec_-I+q!%oz8*e
zdF@+EAQ`9K_zlPfZP78hx8k+t-C!?jCA8g6(9WR6!zJx+RLYR3{g-OmE^9@!_D|9#
zP;Nb0%S?qxiq=z#!K7+ygJ9x{cI#r0tJ+y~!=-7*>3nm#){Vk)8QPa=VUelj(TVXa
z?F6m0a<pU8skpatwFL=i&C?dq>N#IKXCIUnXhoFLEYz0!psz^#^>(N!)*kr{eI?py
zyTO%d#R7<wYd1~@cU|jC2W~609~FaCYQHRji7M^s0Q6OB-KZYwh87<u!rh=fPqCF+
z?G!mU`%SIaYe3X#-y4T$y|(x)uIdKuDms>SOFK;4>}Kr(di1tvO*=sDXc;BIw`%qD
zhHlfk4??6}+e}&b4s8krbM9*SSE1#e_HPPL-`6hOi#hDnemsP}F70PIaHd=P0}b$j
zT|1rPau2nsRNK;{J=_hYz1mOcdC{j0?SV|c)}PWQkF-s%f_to0(ovlO?NWN8J<+yO
z?sQPAp8|tJTIaQJ?Wy)L1(=4l?{on$qJ4A&I!CoV6zUk$e$R&LaqWwgub<G`l@G!0
z*E!L`(NTBgB1D~Z^%U!K)+JJ5f{V_h2t#w#wNoU`P1iLW#9i0036?x`D|jG>b=F1z
zj_4l0iN2${)ICt<rCUb@0w;8%R6O9Vn^1%E(OsdR@T6`_FC=|+8|@#W)lWD022A+t
zn&|R6rBiH!-vPR3D1Q*B8+sA=Al(r};-&@b{-aD?h)&}LE>w4e?wBy$p66gbT(^k{
z_-P$y03<@^@Bkx>)D2SDHA;7#UeM9HNF$WR=srDyzB9USvM6VKRyY0sd12ivbW$l+
z_cfKzoY#5M!J#<amgR8ff^HIB>+!n9Kcn%YjzgK)1l_0`xJ$a0U%@5n77al6Wt}b?
zI+Jv3+Tm!j?&DF2r0Di-frqI&Pm04|(Jj0UomX}33+by`8M?bx05f%8(84iG*S8er
zvvps63UW<1B7p83-MbgT<?2>dLTR3EXBr&M*L_4~&;>e&a)=b_m}Rh3q?6M!qgXfp
zN01U-$0$gtE?WS2nQk>5SSZ)IQRw=*ZX7`%`?Lz(!p||ZN?qi?&|Rf_|0a}H>xBPd
zzHaEQhXGil`z9D%oo+kTI@ar+SRm4%`}#6)w{*c&4AZFFPLI1LorS*j*Q|@V4HGT8
zZ|O9`ZC&^jaBaG4RNUCEGaSPtbm-plN29$*x9D}~?$voxIHXU9eGo2koszPx1G>rd
zuz#XE$3fqqZbcU?4e9(Tl>Ai3SPgDe7f6-#W4dQ(K{Kvf#sy%%{?sW9+fhIECbT%|
zxfFUkp#ORT<e>iP4^ZZ;Uq%o4qjtTF2{p&`iXPlY$MrYq2$`3Da|Qf9p)bA-OWykZ
zC(-Al=Te;Mq&}Xa3%>gAXlDKNs@0J6*Xt8u{*;~*2rfWBn}RBVdf5;fgY-LTDns;V
zvd|c+zfywVAWZK-@r!W1eKD<TPV4v1goz0K!ard?TK~*B0AuuPve9=&e|0lN&+40o
z;OIGh70pwuK5s27o!6TxF{U_u!$XK%&`+bIf${nklp?>Vk3ECF1pU3&!Clf{G(#j&
zKlB$wF6+H(VJ}Jlp?xx1llAFL*uA1Z{4qq+^>0#vL54ni6G*1Mg{md8^i%!@m#sh6
z2c_5a@6)C%N576v1?1{qrW9YEe*5$ADPMn{((eU&FK;+ns1MJCWRbpgA8^I`QCdZo
z=p8o0i&FjUlayO1({H4WP`Q5fudsAoZ&(MeLf=;de5L;CpTOVHKOYa$sGqzGlh~wx
zX$34b>r1J4phaIp3EA6vf2xPNqhIwL8r$@ryMeUpUws0}4!!(C7`&^09pQ{=_w-NJ
zfZW$_+(hrcPCbj38(sRdu|Pb~U!pv~Lw&Uu9PZJ-N2~o_{bCB0^y%0A|2zMB10}Z~
z=`U75>0^DH2V5J_KRyobiQYoX?Lqx^2Ta0K{bsu3hV=tapk+j#N#C9v)kjf9-kAQP
zkYbzT`q@;=I-&pcAc%t@lp?hI4RP5Ry`$mYI^dlQn~ni^z|ii9#)F30Ga%w@Xy}Gg
z7sGZB4BOS<NmrShVMZb(-3^OZfgCo>Rltj*hBs(|aLlmuJq+-;A%c#odKvc8X3l=X
zaGb);-iAq3RPAecnbI|WhAUC%^f!EHf$md=b8Pel7^c+%7-%^5IY^M<7FCJ`8?2r9
z?L!Pk9khfQ#1xqgHz;PH@3cW117#70b=v`tG{jH^Q<TAX0&YheBCxWa7GpPLU4!Tu
zLkblXo;3`-4a7M^#8jw>HK;d$#2M`Lq_|+%O%oh%$oL0pE*esOp)|qpF>Qwu4e7U`
z^s-?AMRt=6_e!8F+2CFbkrcxu3fZL^b`62MVt7LK(hO%Qk(6$*mo{PAG7M*^v@O#x
zn*lXhhUcX4E!z-z5PjDSDc{0Gfk7(5Tof7_4xq2dP)T=su_2bC8YPDCSI}2xsG`??
zxuJO!eb)_@ROV1+c>E3E)rKWauyDgrNkN<%!!xu9t~FHIn*gjcoGXXjdV@QiL2fWi
z=0i=BVG0X<&4$jepr*y}=}aJQ8y-@y?v5ej8UU?^S!@8>4E>&v>@fUy29kFTX)GAL
zXZWrUefJF;D5%nDNFk9f!|fJKP`ANh5|lkKB>iEBrH6)WFNpRT94Xz}Z&1(<^^u{T
zHc5{STYds?z%cDD`kokW&?aZdFizR6r-ni*Qy4ZJ;6Y@>aBe*sM-7{IV1gzLoO_UT
zFm926>^DB7K#!ww?q+!JWPF*P*$0fiev@(kIUAp{Amd_Oln&x*tbPhnH{(MJS-2ZN
z%z)@2<CKSR^sw>ce3&?5T(JQj9yM0vLFAZm>K2gWM)Pd=>t#%%l-UX6;=2$zX}n7D
z8eikg-GKWUf2A#tzmZvr##6?PFVp=OX#B(<h#+HLF-WlS0YyqfjXNm(6K4GQA!a7r
zxacJ2>$LIRpJ6`2*zg2uB8}k!^hF!b^3WJ#y!kQ=o-w{k@5Zyn9q|x3XWWY=?zC8A
zBR$>YjQRAYyI{=nL1VmeJuNEj7mceMF~S66|6Q<`jq{E|G|BkzC#Xp_7QBTCPBG3T
zkyN9Uf@W8YJ!JQ)F(CvVrWvy?gQOd$QGHN`@pJkVN2bwvCVa{=&Z0<kw((h7bzC!=
zlA$`s7+(WJxyET~^yS%&(HmhR-xyAHLWRZy?Z6iq+vyiAHY#}Vw8Z!v?UPH5iFACa
z%=kqr`pS*71AxD7T(A+^DvXtrVZPFsTmaXqjAjbLRvSP34mxibchHi&#(05}RJF#^
zJ>YH{eRjZ^I-@<BHe&Tgy$Na>jPo|Z{4HZPRfjYh+h0Neq#0pL47<gs%LTb@{DO_X
zJI2o_iPCD^{t_&;89!-+`F5jtH~Kn^TPbvK*SLwQobDN8mV(?jMpLa+r?HIAPIei0
z#sJW5JY*lj&>k3ln$Y^t_`xcW9^)?*I_Ne2^*aXBZ}g;d508uw=q2;mXx)OoLE|>s
zYYiDa>o6rxjUm6mnPH<ly<|p=rO!cf)L6F#BO5cm{wGAnjd>K1p1_pA3kTE6uh6&O
zG-)fnMjcI)GvKh3sh_+!V4C3v(SxS%Uq_>}>1V2la4~sZhf-J5>2UP9ndW~0*W682
zgRtviy7??jc$%U<0e8sM(*WFIlZo=*M@%Z(IUO|>Y5_QATJZ@i95+4s7m{8k?N+L7
zIbm8#XB)gt3x}b`#}s}KGAB)=w36~QRnsvBKhqZp;QUP=JP&fpbgdMC08`&bn8ZMn
zei3vBndZ{sJ=k=3HVlTCetQWd+_a9~(5FpK6nKm<CA<aiBTYj)!9|%~UqkiJ(I$Qq
zL}N^&Mvyb6z(p{B*7TGD5wWI9dZe8<O{0K#oaqnRSR|OTC|G{U^uu;cVxnm;?cFb%
zlAed7Nu~!T;F3*UrRYmB1=6NJ)sz<s)mKabbYkbKsb?}I(@b~i-DXcW?WfNaWSBDl
zMrWpJ#bpd8%d{~cO0!KW`Znh^Q>-gQb4-I&wv%gmH~<rQru_uSH#IB<yukFN5grzr
z76*b9na)pxmSU5LuD}vgei^t@)9xw&%1qV^aIM_LrnljByXmV<n6?VjzIl+TG-Z4T
zuF6zRvsZ1JJ_vHdw2hXkH73hpkXq9-6bZO#8f}B6I@5bxXsb6Zj|JCY`q>@M+%hG7
ziD5UIcF^VAWI8knBF(1Ji?GmQx~M_lZBsNKTJD(aA(W15HTjKWplv3XX)w`lTCor^
z9j3Qu0(jTtuoa^BOz)(EyKl;(<zT1j`42FdF4HXrB)d)et<dto)RK-dJv2=f!R;Q?
ziyRp2HC>&D#y(T&U2y%TtxhoX$n+MyzaE=5+v#xKfawdWReoZMpsz9yns(Esa@e$l
z>Rv`n3|HtLHKo#ye9V-d32o!1$9&)>OpiZ=QU`NdJR0|#vs<Cm(LDAJJajVerVR1{
zb09sg4w~mp0q1OP_yKOam}fac($!ozn_`=8<|4W<+|5@gC+T56(+z~DS-Kgz51AwB
zYB_8^{R0q3%yX%j`>1(SJv=;Swo`cgxY>ms-CpL~^tp@^<~gS^LT~dK%Axw07tqV)
zr1^P@#`v07&cTrU%oX$+^EWS9O7Fiw^Cl{o2{Fg&(Hd$FS`IGE+}!}(;pWw});n#U
zM#WMQ=FL<`8EF>L!!OFbh01QC%~6kFBE~#87w|J?&OVT{<|ZZlJ!gJIw{NVuBOPv^
zHxIoIWpU=8z5=;m9vr6gKk??#QHWkN|Eq;ef;o?Nlb6h~l;uq{2XG;J+1&Fo8k5Wk
z^vq8-zifok6tkcWc2mta_rl*R=2^7GylUq6!>2TJa~M2KH{Yf>eui1tipEUyq%~;F
zGH<0LquJ(dX&9jWnz_6gojK+yI<)4R)pbysXD*|se7<=v)u9xaKbJzJ(9C)V_#*R`
zQFu{ouAnVqiMgNZrc2G269FhQ2d7}3%gv1nkn85u9dNC}+`kvDRhsuW0Z?WBlhQ-g
z=H|Dd<%ZpiMKo?M^M@y3x7O?>1MsF<N2fRH%-SU2>&+WKho=qZf4@Ori`ip24Bj!X
zDuGX}X6JM0YcqG!ZPacartMgV`KxDO;;y-bR)zP>$ySW)zS%Stq|@AJgJiFHs0jY{
zo9(OU%70`&LUHlO=9kidA2f^3!NibRvkb01H80@9?_u*2GCyK|>;{oh^M{YYjhUMx
z(Kl|s_yfp<xssmQ4i@$IfbX|Btpn$1@uXOVlV!u(035J{jblg$Elqjw!r3y}-U{ks
zvC*Q|)lyG;csI*CwA*mEZ2SmA^RV0vhi*^HIjZG3WclzIbRV|3P^HTeOZ<z_ebjP?
z76HdBe@_D7xMe?G5MGv1`ku%Mi+~Q}dRs2jo#tb?yb8lTX^Bw*?rXWVk&3PSEYs)X
z73*&)qM@C#%>5BQ1z4t^hrvKg;;X<1Sz_8?DcJJ$697Xj4!@%@)Z*$35@tE}GaAD!
zf&brhSiUrYi?FoEU`8V?4)<X&%91|~jnS6xtWX_exv9c9&sbLN{{KIFTT-YL>6|5l
zj$OoB#B>tnyyY?7+i?~LF?_mUS?3FUyrubLG+wm)KnuVGOL!~HU$O||(U)ksVME_#
z%b^?SOR_i&1D9+`Tn{f&EbDW@rCRv(;=5v5Pf@FM%fZj+`<oe-=l(-yrsXR!)MQzz
zXlk-8Z@6Ie*DSpe5Y4eP(k43B^4$*f<ym%8!Y|))=`2JFEWa*7W1*!5)zs69EQ=lC
zMX}}muQ0+A%V8?SFSWds4GU$KY99P8x2V=a^15XXJwojj7Sn9FSZT?j4QrL<s6V)B
z%f{6}+_2dDL24|Ybwg>bWh!M`Z(1H&VX)2;a14F*mY1$VO@n2m0v_J7yg*B~M$3ww
z=xegr=zvtSCAbYDEtdNA5V>t}X+_^1%X-RwwAw9el3=jS5=5_#yOvs7mEN;(UxUnj
zOT>%l>$EJOuyL1VFB>A=mN?2#KCtYklDLPK6B{7XV>y|Fx#+d{l!5EBys!&gzvats
zAo<ARO{Fo9Eg{hW3|N{ej`75@dIA$PXt7Tzgl|KZ4;Dc5sU?j(9kwj0hu<TXIErPB
zT7u6*>6m4R&iIU5zMx&sgyly^xbI+nOoc)Ft(h0l=xA+ZfOE2bPW!h5*5<WPcF?-z
zA+$JKhYrCD7wenhXmqunt^#qhy4d%@lDqZA^YF&Q`VEC|J*^4;P;<ySM2VflRy$Si
z9I@67!{AY?)f<+MSrrr|IBrd%Y8Ef+3M$?^VSRQ8Ka96EQ3jlk_11IH>1%y~vL}Al
z?*uUKZ_WDu$HuKsXula?os&ZGmq4qPUeQ6;-?jo6Y<)f(h!CrQlD47N!csJbS)*uc
z8g5-zh{n@ae~OkxSUoA{6lr~i3L>Jc{}#cgXsam<A~DuCk^wkp4N}5xtabfK7&>q5
zISqf~tfOloa=|(@i{hX0)~Hgrf6*H92S%7+O%H<1CF@ao_9j{P90M@fdOjY5NwH2e
zLGr5g2yH6UtlKl-TDtYsSJ9VYy-wf2$+R~811`(Dh~_Zcn)xeqUbFs^ioP6c$SUA+
zt)H7Al4q6tP5*3@Z++(y22)_opyzs_)onFIi>%&M=1^=6?E)#W?zs!QrPdf);Fnny
zx!}sJ7pNHKx^-+da23{Cdbd_uOKbpCS@S7uTW#If2kwUTD&3Sd*0O30yVm;3=a9T<
z_4pOa>~+=<7qIo#<|4>6SiLPEx2&y>aIw+aoD0%qt)*Q`vvqhr`dX~>sgUuuwQw8A
z9qaF*P}*w!lM<9|)|GUMq1}3QF901@;a`B?wf0e3?4GsGgrDNRHIT;HY2CI4l3jM|
zyhmWWt<0anKCr$-51NP8$Qd9#)<QETvDfPKDM+7n?z6!6Ti<12*pI9(E8zZP>k|s*
z4p`mj1@gq&M2V$AtBt-wF=V~=9dJ*r-&2rq*g9!HydSat`z`uLt$I1Mj9Km9Q>Jm;
zx`Lvx6V`9Ofin)axGrdOvMp}_@PI8L5#*rlpI?D@w*9pUk}fvW1T4AQew=^_H(Ly4
zZQN~~Buux5Z4EuyJZ&G-!Ky<x^M{Z;Z2R{`G#;_NMa8Q}ZK31Pa?BQNr=qgswii}H
z)XVl~K1`gj-FgLTylu0mL)6FiEiL&@+Is0(<ZEM77Shi)a2TAwjYr|1Q?_}2Xbi9g
zP6aN|wuZLbLAE_~ZwA|1ln@EA)l!-@)TW^`-eI=*=b$s(_M3+t=1<!W(Onf``}7`^
zM%s>0N+-(pA1!5~ZEubM5o1H77PpgaP67b2w$MEo_IcagOCWK!A1MKM!4~WVk$7A8
zYM8%hTNw!x3AR70!CkVwx)76a*|yCcjY+mVdgCP93U&1UOR;5AEo`c7v>y1Yw)z*K
zEzMSb4TyBxj$D|}u%&H8U#9IorL(hakraf=vAKQ?kz89?K9uI!M(M0~zHN&?xB}Z{
zD*P(6om&M`WE&I1?PA;JkKk{KjYH+vr8bXH%Kw$wMyYP5+*ZK{@VaeMG1OGpsuuxK
zX&a-;^eWq@l|WS6wl)KQ!?ye+xEkB!`Eae)R$&4BrtOE{!PVJHo`FyGw$mag`yWTw
z8CKQNgzc#&8dFSSx<-vrqlubmzGyUw(G<D8_uj9GrkHZYh6pG~l_DJ!EGU9VZ-NM@
zfS>{@U8)o*O8wr+uX%QN-kI6G=WLmoJ-5cmvI%XqPL2xLd)KLQE3Cig^vg8Jyzlhq
z7^FDroMs$=rh2DOIpAq@dUrC!G&!mM26^E0`B~swo&G8VqRlDlD)8-2a-3VIcQ~bz
zSF+PdM#0D~r)3|Y^w24Qa?-k;Y9<5F;}lG%*IuUy`g~cRlfDbW2AmeAfMw9h{|1B&
zIh^Y0#eMAbHl;T`aT=gO7<RH8z;7_(l(7?IG3qqsBLK&o+Li-2?iAz>LnoXzk)vrh
z;{j#e?O|A7fWp0uXZiuy$7p*6HtlEJvH);^@xC)OxG>TJpuv+dycNWY@#P4l9A!8T
zn8D-C$jF64A4UybK=5VkUksrEjCP9C9%JM_1U`__;|JM6jBPIf7|aM3gENG&crHrE
z8P_SoAIj+c5>|vUI@&Qn;S4eD1tJ(_Z74-D43wT5#W2vtgJ?!WCn{qY363D(6Bt(}
zLE1US>UW?bk+G-_VlFTi{{o>&jJb4{PG&@q%i|*BySG467$sZ4d5JOS6$njbtZzdn
z(in-gke$x3905xPV`n*JW-`Xfmz%}d2WQ{(Y{u%@;LKr6x(D^SjQhO~H0Ckp(V-)s
zv4-wlTxQ5<D^kE{ItVd^jLA<hmRA^eX%AAwc$?xTR~gUIXAz1Sz4>S>VJz~2-crVo
zFG2P-#%7B4UT55y4Zsb?-AQ06V|-4AmNS~h!BWBaj^^B(48I2Y{zD~W2Kfc67)A=M
z++w6IN8@eAi*(qz!-%Aem1@Sa7g1Tm2&7~4Jw_Dm?(Q>=Q9f`TBh49Y^^D#~3|9l=
z#9^4$$XGfHq=`{ffXZfufx_r53>BrVJz%`=g^_7x+$*Q|uZ>Yh6HPl~(w86|j4ORW
zbTa;+9Lp}o4Ek=xL&lm+DC}nVQUYWT<5vo8_A**NN2!nT@IySEj~Ih~sO)EKZUuaR
z;SvknAS06k7DEg-7qmTQnAX6GCyZrp0Wi$SzlH8PMi@i0fEZ=`c?jyq7=yFXIL<gu
zXNU>LF$I9TnQyFy!OqOrC@**qlY0OxdzqKXceamNP2rFI%(ux)et>yNfw6F5UO$D(
zL(Eq@(Fr#uy8%|XGh>awc`%(%19zDDMl3jwIGEDI;PGUZUxGp}=HhiAN14e}fbeGi
zX$HcF`SZ7^^kqIwgu#Bye@MMQ)AT%41TdE>VfHa*l@M)#%v}X&3u4Y+1`^DiM!~fZ
zW+v^xjx)ECFE^BVB?tP#m_0`^K;cY>DiAyo%%0Vd7Rj8I31AeniX52HOgHjj$1u|~
zVQ?(-D~fxZV9ulM?@8vAmw}68Dt-Y=JafZ3RGwl!G{TD0%)aa3Jj0y-I#irxKJx&T
z2~5uds6WSiheB89nc4o(m&got&<^1OGnWptNz5X0i6t`?OCj_kGwBnM6sGGFR9<3w
z(y1Ypx%g?Amd4yoIR)v=MYLthVD6-7d?vG;ZdqqBt>o&=W?mIQZw|Ac6y`F$=-xse
zQ$*X}eC8@z8!t0od(Htd1<Wl9h$&>MmO%Cu=2t?LikM%~t%9q}v2;i)W(vNC>=Ndr
z4s@-Qd7L)WH<+;lC{-{M=)8K9+3^CbsASHfh)@+%^*I#YVh(3O=56NJ6Hs`Exk3ji
z)yxljP^w|>I85Ikt7U%lITYSyZW_ZN-eYd>2G4zF2u&t+%)^v~P|sXKm*g6lgWlk5
zWZsa1vx(XB655)XyEKs2!n{LXoCnOgZ@`LH=7Mu5wK3~-0JJktB!YA>L!JWZWEQ8v
z!Y-yHnd0vcnXY%x(Qf7(dVzYFhndjS%N$<;o<8Q`d1!mY+)UF>KQp}sng*CpdQci<
z=8+G3h<U98LLW0fC6DwI=Hzu~8)lxRG}#emY9UxgnQ2QPWsK=eE~RnilokLcm{K~S
zI(D=EcnYk}tWZkk-ouKQpilc*jc=fb2UwSufVi-VG(a3=4cDQ~mF038<Pa-z6DmDe
z(UYL}Fsq6@k4ISAF|-|Jr7wX@Z`P4_Q1W3dmtsVHS*tEVm>(<V6>$2qrsbk7(7{?p
z+utCTbQT(eS-zCN8Nzy5i^k)u<&>Ea$`Y*rB8;_)&KKdVDYTu8V7*NfdL-*vdN-q3
zt9a;IG;667SYlW$w8@KQZD~O11Zx|){7<qBa&X46F8_>f$Fl?!y*$NooTA$hr&+sR
z$69rU^#;9TXIZZKke$Gq`ywjOu^JXY+IiM#N>@*0)fWJGfpwQoM@g)R_wbY@v&8fh
zUS!>%RWyZll^j%;Se;g|q_Q-$b4z0_z6Q>8)=b*2XRuVXU}mzIjyb5!Vl5c}BAYdL
z7$k?45DSvadVvX&$EsKgz4@##n$j+_zK%j=0n7U_3@v0`n2bJMVVx#VYY{800kW^M
z%rcN-)+AaaN>~fYvsB6&Z3f^PtB78Q>nzO(N;g>JvmEGQ8LN_lzU8b(6o#l^J^33d
zZnBDQ09eU-{WiK*#oBcWmA6=*QEcNjYu`bTJFNe$#aLFe*3%PM!<yF$g|(~@dhhSD
z&K!o>bu1rBW~*nlz77i;SfW*s*~oGu$8;0x=cDxfv1ZnZ`@pxbx}U~aJYcP)pQ4rZ
z7Rhd772b!KcGj(Mi0NRtTk()~vRpoev@X^c6n1&YioXD9-K?|Z-|k@rQi@wIYn}+k
z^s#1CfIMPVz75g+tlh;Z4X|AP1<N37<|}mne2Dd!mZit6LfV8sVcm%X8D@1`pm2os
z2Hm$9Wp#E!#Te@#J*(raxo6Qf!OEh&&u(_oblBv~E_ea<?qOF_bZswt+bNi~kFBO<
zVLv->5;PoOZxTV63wxj&!Va?kECk%)%6@7y5Qo?+lF{hK_FsZVclLASHS=Ke_|SBi
zy(1DTj<EMm1B)m7-A+jJV#kN0bd-IaZpC@CUm(wg5Bn?fi21T3M^Wj=7S)2&pY2KM
zxdH4K3^3*xdn=t50@)0jA%Yz2@DHFOnEe#3Y9Z_cn^8K>W)Gkg%3i(&#)Pp8not?e
z{xB1W2(~Z+Vj|hE+yYAsdpCJEV%gt456%<pdGu??vqdRrJH=j3QR36=0-6I8*l)dr
z(m6Jpd<N&)X$w)A$ac8VN%I2Rg{HJ5_MA?bpTg!p2XcvBxE&;wec&Z1Ok<Ch0hrG2
zT8pk_u$yQDn8{v5@xLr~!+$Bb>_nPhbJ$D{jLBvHErz{$?2y;Mna>WP7|><5na;Td
z>`2PRD`Zb|klXhPd-HKL7O}TJ1#*===Nj<E?2iAk4cXPMP*}=7M3L`n?D45+yUzZJ
z2fa7g${zH-jD3ZiljZDJUPlir*a2o3dXxQ0CE6<4-v<I-#U7xf&|7Tf4z%57pQZ~(
zci7&W$SYdSUfY4j8unAPy{ct@k`3Tpw%mfYd+cj}gWP9Nxdrug?3vMMYh<(2VSW?)
z2Ca?FY^V7U+QPp36UYPhypyo7m3`)AaJI3t1gLCh&mb3R2m5ad3U;#PG;4LSTU_Y-
z(+}BG--PUL_NE_z=wWX!hHbrU=V<8dV}G$1njWzw-vZIkZY0<20Q*&H8)PTaq&viR
zafZ;x?C&Yw`Gg&F44lL4wUuZaVZXc&5BVtjubCiY>>Uh<9%om-53`*)fd~jYrtjgr
zdKZYjoZPP<`v9kN27oS{Xu9HXkn>#_5U!loPayjcM@Z3pH_j^ZY`Jq5rGR*Fgp|*9
znDfeuAV)aco`t=h95V&}yf_gbqI8tQ{}aEmH>aPjR`_tXtb!t6&WrT1R)-(w?Ksr>
zbBuu?0UQoZ;m0_4j39v==`*Md;W+;c^~X712195lXZj&%3gb+tGg>&umt36@oT`QB
zVI(J(PJ>aLI3ZY~IkUe6OAN=b03D3w*eO}~1ZR-4QciMOm!UGw!O<)SKAuw?404LI
zBo#cTIge;RcZRd47(&l-DyKqy0_Plgq|b3)`U@j-o>TB9+7dahQ_9x`&SGb<BynC#
z1umI$j~o#fIa}!%n8JDQJSs17+$a$_mGeLP3DY>s48Wyx@XZ3~&EVXP1y3etMlTG`
z;(Sp771^8=ayRF2evd|FF6UL6H}W`>-61BQbBugZmpOmaUAY2|UI}9gIp3F{bcHji
z8p4V=FSkPURZgKEZKa%Y@+jZnSn0-G8Rs4)VwH3J9kdOu;GDMtc$4$K04gdu1$I<c
zac1^lEN*c+KSJegPQw$}eTU=u4cclsx@G|Gava~Ihxa&JD6)E=Gj%>H>o{ML1EZdE
zKLMN#oYNMtG;%sAx2%a%@dQ6iGv^9jrfuc;t)jKLjWg2+z;@1qpMdD%yh6!v4>@-O
zVQ@ERM*uq0$B7~D{3Fh1Z-Ml4a@K=oh=V_^!jsQAF$+?jaGsukg`*sG5!%K$eb0b%
zob&O1XmaL0&_c={?q_i@W-qt72b>4ErR{XL$c0-If)P5%jXIAZb>rS9&z3uP<#d!h
zxQAv!j3+mRwv%4m<@6<yqujDL(B{is`aU@QxZ3%U?azIUX4^n+k2_QZagFn^iUxC6
zP)=JYcc2!PVcgC1=!A2x3cwk~eIJo$$Mk4!JVmf$xLe47dXnqgk5U|W?q4AB+~+AD
z@(lN#sThm1+(!C*MFO|R12!dcn>}FD1@1bU$&<J(8vsb*o_rQ<m$)x{3X;k_`~<iR
z?(+YR;@laOGnK_1%!V<!+~6dLcI0u_Qp7%=dxIiqh1`$Hy?%vzGZ@AcaX+RASP9o<
zDa2HA>u7PS;;Lzuzr~#$fU&sEHG2YghwB;&mRjyA4)osTx{$l;9@lXifcxA)3Y64w
z1GhkZJ-6u*NCWq`c#uX1x07zrG;x>Z0N>1=;|BFD+%6B49&oqufp6n}h8J*pJNJ)Y
zz}dm=U_fstciOKI+Qm(eMYp@T(<tYvhZ`(~-d^tF8p!VB-mC}U5%-PXQQ6OpUjf_@
zH}f};$K3o8$b7<e^dAR)l)L)^SjV^$@&}G{*T0Wm?B;diJ)Z8&vyww$4=>pU#9rPr
z^dRozouDw{0p2ybTjau<K@0ssUMKa?mG^oQgdO57A;*{-?<qRVy7Q6)V6O)+^FzQ7
z^KvLV@(8c+zyEsm<emKqR(SEgT?L+_JlRHQ^5(^f0rcVh@*FCCc|B8r@Z<H;$F}@=
zzILb&;2A0Ud5qVy3T6lL_U;E~2yX{HGsk)T%}^i83!oiT1aB(2Un6-TZvz*_oA*B$
z8p~7vNd6aOAYDS^N#0BJ#m-Yam*-*3Y2I}5+n(X={03sq@kX~m%z2)e_OFS&lN4l2
z=5>w%cae8}3#6p*UZvS5jW<C#n(4fSQ2=D{E_Z_^oA&|v<#Kpp6$U?-w~E{nmw9ey
zDgUK__cKlJg}haiM0<tDoq!cZyyO>9d6nl!?{6_LU^}Fh@cyJ%yp;EC95h|y{j&rt
z*Lg+XK-vvnsTfw2^Ujmks)84D8dluoy_E%FmAt5>AXPjeADp*%79DW6dFwps{j26Z
zID;P6@Sc7e_*&jhx<h%Fr=;-7J>FJw=-ub79!6UoZ!Lu{>v@YPy4}Dt+<=Nk-fo&G
zns|kgsBGrtdV;j_!YFIKjdw!^W7>J8bg#OLC$d8CL*5AG$9MC#&x8g?4=+s**}c3&
z%Ru^gV>@BYBc5t0c=~zXbD&~?_a_gPgS>!6^aS(1*g{V*?;Q`2C%nQP=+iLoc?U`(
zyjN#H?<jBmGzc5xT`Y%b<Gg<(K_+-cO7PjuA2Op8&issrAbT8qFPfqD@`X#$xR3uj
z9VPbjF$Q?L`P(RA)rEh4HiRDJpQLryl^^#HI1llgw}8`)zvfqz-1&Pc!Ow$#Z38$D
z^Via%c7#6^3KgDwbpuTE;{W{~$Wgx23z!(a`9aNK@!>o2a)9vV|3&F6e*B%W5aZ9E
zwF-Iz_)ZizImX|$3<DL&&o70hAikBHeZl<iDf=gczdIfybDXcC_<JZ{NAGPIf7&JJ
z4d?%}6`hFS-~SylBl)`?Kv)#tjgGz1d`B`$G5ik44ww<kpY$bEoZx>=)7D9Ts}7?c
z$KUY>6vp#;bf7uKpFfPs)BN1^z@On~WJ2~?{?d<tOW-@xLVu1g`W~h8d=FYc68V48
zk?R8g^LVsf<TDb{r4;@^Fvul-4h}8TQ~66Z4$w6I&(~mnI)C~furz}oGy}3T`D<vG
zmc>t_7cZOt%uR6S@HbM3K9|3e&bxX1o#Y+N=d+&z%VqxMbjU8?+xt*i$e(c?>aXxS
z$tP6AFPjZvSNY?V8C1+S&_YncU&5mEUnzfGA`sX3N9dOJb^d$X!Fq$=N<qake%NzR
zSkAAZpR$7gBNtt}$(PbOtdhTtQlP5%t#sbK#gBdlrQ3WfJr{TQ12j(6{8e=2w1)39
z24S`QK#B|B<<F+zO&!1MUpoKQ^PRp2PXoV}&NYpE&oS^c@f8_R(aayrM`a6t7sYEH
z@U?5e*~*VYV$}3D{sPKIYv(_k2-3lS^G8&6^4B?ID7*L>Q((nI{w;D>b@QK4yrqYK
zY$dGd<*zsi&OZJ^at}Bj@y}Cew4YyBjNT9MKc&xA4f2!Sff(W&`k?nQpV^Pn6TXUK
zsl)uwe}ak;{+oY+jPl#<z>V=2iXn8I|HTH73I2Oo;M^_viGDk0!6gKyrtcAm=ttix
zSg8kKpP+%Z3;P{{I7)ChAV{LmBe)2jdkCWr3TkO@>ndobN$il|yajkS!HPS;y9?NP
z0C)(pE<)2`!7}=5h$DjEH>1*15WF4z^%5K(2H>b*+bop41tlBNB_BaS3RrvvUvGs>
zKf!GY;Qj(f6P<Sh1izkxrN;zeUtlZ(1v$UL#2`U*I(UKwmjhvGh+s7ZQI88k$+r_K
zc#d*<!UO`!?G6{bLNSpD!ATZMk%C1uT}27Ld<7(0;1diDF@m4w03Iut{0T^$U^Y4H
z;ss?6E>xTnJobfcX9aF=qT30AN1wppbAo4vK~e<j0<feBekZ4By5MUHv}6cOIUt#W
zOLUaT5-eB-k}ddZBZTG%=8z9LSMUwpL(LNuv_R%%!B$FtD-Z~-!@@#A3tfD@BAD}<
z1GPnhUmjt+t_r$jU@Z|Oy@bw`3f%s?8zHzvADg@`7#>2~4Z&qPR+R~!90n;De6Rs#
zR|tH4(9xTM-N#T_DY(2DDyjtIfdJeRj2(l9+k#CCq418tZzY6P3pyx^v__z1()(8{
z_~$mvzbiP=f+4*p&{C${eSvudq)sq&148QsQJJu?LGbPfNTXl_g&LX!FQ12|X2DoC
ztY{JZ;eyfw!OwJKs8!%i8PjcoS=&(R6y!~Zur9&k1aLkSup2<S1uj{X|I#D)s1(-p
z3I<+BxBCRQC_MH^V4yfazhEN+l>>sbGE@!<7FyAnA;Itx*z{O1XERDq1V7(L*M<e+
z4FHS?oEM>TRB)~fm1BZ0{h?`G;N}T3A$V*-+iu|mxrX)%w^F>ru}}EkUZ~hF{DoHW
z148jTXmk;V(w~hV6f%EBFI<HkG{GGbe)v7c$xXOx4K%q6|Dl+QhcKH0Qip~6e+2G`
z&`xi<r%*lwfS2&!cL6^t40r|rZ{fEM;Per`O)0Uy!s1`S;^z=X(%a!LJZT0nK!|S!
z;yn<qrejK=aL0eQiiDak&=xG*7YTfbFo|6DVM322m>n+sVJF%mgwrUV7A>6d7f6io
zW4dw>EBw0xzjmB(`FXI!3*XxT+$rJ99T0t1xS$S|2|~yF^p%8j!p~2^#0$dDXv3T&
zTyzS<oh(e44HYTE;SWGA3IBQ*_*7vg11i#ld2~!j7naf!m?`xC6m40;4=6mGEgaRN
z6S=}p^0DLzowh(`zVKK2c`plNC`G0~=uf}a72y>}7m7tf1sy7{3cHR&Z;9|V2TG;F
zuPOQOny`R2p4Wx1@gekvaCaT-Ef-b~g0n)HMls2o!jCDkS}9ykDHK)0{%yeB628ww
zWwr2S82~jxce;O6D|DZX-}SEWsfSQ|PnhgM@85l)H=Ri8gq>IM`_>D0yoMe&2+z}Y
zrCqp|wr(B5!6A@NVH(8|x`d~uqB9SLxOjkhT{v$xOzRZ}(8awzVObg4`h`=I03Q-=
zq{~5%g{8DKKM^)A#W)QMJ8IB2BJ|6lZ!3)okI<=oOz8On)Q<}lOJVSYuz|8ccZ<%^
z!{#h{maa(b5iM7tbU<{5)+iSdPln2aqQmr*xQdoc1N@LkKpDtxq7NyE=`Q-{Ss3FX
zY7hZ;Sj49YmbYkR0f>*N`Azb__=?`01ciPgUkcayiw=%LXn<%gU6nW{`jbvFfubwd
zp(03R5<*Ov$V7XXa8cOTAQ7SkSJA^r(M*afM~Q~$tQ0LOqg`-}Xk7z_GFJ4N4&;O=
zq7jNti`pr&az^wFMUot6Maw8nDnXPZgTd!SQ*7wkc~R(D@Fa?E6a#ocbfFVMlSCV5
zL1Buhnv&2jiGHD+fK*Xh2HMg@3>KuMi=3SxB}4QR1C^Pg3NLVGiQb_U;B1i_-Gs>z
zef}k+<cjnkqAkxM;*Fs8is)(DFc*oo{t5h5(ewG}cCqMZ%7ZQu4Ok(qR1`=v(>2kB
z*P-dU=*$}sdPB7DE~Hh8#_4`^m1u7pDsPFdlYi~D$UGhWy(4-|4()2u+{qAKBjQs`
zvR3q4Jv7`EIhIkdtU;utvs$BQGu@?Z5^eH>v}VzPTOchW6A$EpD3S8!T1B&UAZ?<V
zT~N_3@^}@-bc?i9*(3UjVwt_7K8l?6iM+`@_egZ;G0g54buR~CK(vwt&OuQHWtt6%
zZaV0zSHq&A7f~D$JzD^yMn&&z24YMk`x(;4MPZ+TWkU4l0Ho~}|4bPb&SLvcu<Q{}
zr-<ENu|x{l`^0k`Ap6BDDPQN1I4%|?H!-Ud*1L;2bi(uy-yqN7VR6h5^c@k;-$?!!
zPjN&74E7S=?#Eah6+ih73jM|HsQ?Cu|Df6HnE1nZNDCBy5(GeyxP#nX!Qw-1uqi}b
zPbY%oVh<x!go-C|(TOPWKlJEDi`n$(#fWq1(Tf$oM_DN+#0we#KPi5!ru8pQ{0Dvg
zK3@DOO*^N=Urz%$C;sMlSaDwb8ac)i#o;fY@`5;=Zrmn`v*$u#vbg65R9+Oz#E_OE
z{=fsWFNqV$kDo4{k_mW*_=jGUGR1r843H&`q^l&^;$Ko>XpXo(jMl$g@q!|#$P@4W
z1SDTPr3n4KEdGabr3=IdiXppDe8d2SC1Ml#DoVwQ84z<#yyQ(7b6vdE3Qae}H)&^4
zCibGBZ@D<~52&aR@4X6{x5c@%{@oF~Q;5A<+)93o8nG|kL2=ZI_gc}5yW%QJ9=s>6
z+5+HxaTdiyn#9LWKz6e@lX9h7#M{o&gD8Hm5~Nl9dm4nciLb5)X%{;c0^T8h_9u`Y
z@$N$WlD*=kT@cnMo;C;8KN7E^*h0T}3lDk+#Nq?6V$dOeL_5DB@u@0^85Y;kq&*^D
z^gobM@$(cM7!yCB+?sK*4?Ud|;*Tvb#zpdKFjO3rbe#s=RWg?%28Sexbg$b@;?oYe
zyX5VEz~Uh>`$O+x$xn6QJR<o%9*R6A@wF&<NgSKUA?>JS%PGkAmNd{w#780}*RZc-
zh!#bENy-HX4Uja1K+G}8QWtOrO2)PWA0%PYBOf9udIl`VC4(E#r%;K@N8k*X#L}l_
zA|%hNATv@TRiZLV;zdWFXvv0mK~6~Cc6<upNl7~;K*vdvXxWdKd|`#qQxf-RAWlmb
z(AMpYWHD{f&q~4%0GJ>tr0?^bm)xcuW1{3m%7M5bDOw0zl4P7b0m+iDmx5fB>>o!b
zE=lA&!ICQZb06Sok~?7#oi0f*(EFDmx%M*#AybmH8RMKKIZYp7%$8)`LR*exJ#FN2
zCI1}50Ov`P$5G0c2#SHfEE%Qexj>RlvsR(x2rU^`B$ec8Et2dx5BOEdMsm^@OH#YQ
zQX-i}iDRXbTlDRmYm#FdX#Kk`X(ccF4axKLJ5@-gHo)MUk}8V&R7yT2*HV>ayBA8g
zBo+N=yDbrXfL>HfW>=%FMzXO39j%ot9tXKA`SW8ayeHZ51;~8~;|OHdOTy?l)gZAi
z21}!4MH@=Z5|2=dzqd##={w;MB;UlNYps%XqmbPu*_jSa?UMPFQ`aG>`V1^xl2i1?
zJ(PUWg3feH8qY#~kAzLrMz191Z?HU)*s~y|U-H#kAOn(0+5`+r^shtVkmMo#_Kzj0
zOECx|k|*ndbBs#n?*ed4B7PRdamiA;@;V_|e+2m5(sx#%<Sfndg)w`iT*_eHD~<1g
z`h8Lxt$6#ThfbpHfYh%KZ7$NWxd0rLX42rhO1u9B%OR<jJgsihnk6W?OMlyjk@1km
zJO=KtLn^O_v?J0#DcI~OeH;e8Uee#!fgF{VY9Pj2dc+e3`$*%S!>{ctjou0se$t>Y
z2=$jLzk=QXX}keFJSN>Z13e6s_Lf0KkaRC4-3Lo0<RJ=?Iw(2pxHR1jxKQbIB;QUC
zlRB3E07SU-jgwFjAytV{ij@9Ft5THo3wl_irF%KBG)CGt1u9~tJz{XiNt5RTA1_tX
ziS3m1b4pJ<E!}{tPSejwedwTjR{8>kWD=ymI-xJ;q#pi|a$Z_Vo4Z8m&y<~YLE7Ws
zfi+1QN{5|fsi_5>xhVA_zj}&vC&kz=Nh1$o*ixk*Pe59lbk<fVOqb@iLQIDAmtWDA
zDfK)G&MYa1T&&sBJ9JMgN2>k~DsrXQ=Yb_py7?Wj<V)9)>*2DLc^aGr(r?r0*(sE|
z)9vFc(nX74MUixjc6V2$OK2)BmUhiWsYLq0Ca{!BV^=}_4QcfTkTU7Tb+Eo%`s8V_
zR7e-j1i2|at^jAHbV?0Km9#$^Qf^6^^uGYNr3n<_xFeNLMrF11!`JBBx;4^g&%=sZ
zsq+dT?n+Z>&c7$!HU_)zOAk?AVx3e<>u$Yta2@asQj0GDjnaII4K_*3Pr&SEsVE4Q
zEz;Qk?!HLfZlJAQx-1#E4(Tvu&2~zkr=V?@G=CptK9s)cM*Ghm>2Kcx-z)uQDr)<r
z*XUsXNIGp6@cq)yhtM`4Em#dPL(+S1p%;&(J``+zA}t=rAPh^_41;Av%KHPAqtYM0
zhKg}%2*s=>q?)r3wp*4(QQkeW)8zTsD_i_6O8aDg(+1nIUnV#S)&sKN!+}32lU@gL
zmCd76?L)GgA`F6?>~qTLahHv(2Jw(NCjoy%_9BIzJ!O}Ef<iCZ{W+*SDtnH02HvuF
z=<)KAtsx(lpDdExM*gx$`i5eFEL(!U1j|m+VKT%aJI+V#aoOt`K!nPkrgK7=?6*z`
zjgUpsu{TmCrt1h%vS(>C94(vw1AsBI%G*#FD|^`kZ6{=jv^d4d#Iz>I%N~|N$|>2+
zA;3?|s$NIi8CgOo;0dz#=3to5$yU7vL(j_`!;~7EDEn9k#0A+eR*XrKES%2p$+AE>
zcrMB2(;+%lc7cMoX|kbq;L~MZ>w(LVExwOZmQ3^`Y|55ZeF%~x`;~s*T-o;@Kw+M2
z<r@&4FUv1MTY>CddQ%H!S@afPk-hJrxJQvJoZ`DzWofISuvk{O9r#k&0`lu!lRcpn
z{_C>2UMQ8xt}?+=F3W!oLs}u*H46{KP1zbI;FYp%^jEXDWZ%`Jzqe(Ur$Fw=#)(wR
zexdVUjch3meyxm4Sx)z4{xuHBzAsz(D;n!$-n7Kl%NEnYqCqye8LW-6_sDbEENiB~
zMT@L`Bh){T`I29*L$-PoaGkP?Posxjvg;aH@laO%D#ox|mfC{KUfKLC2<wx%Q9{%s
zS-TCSU&afDlmVIlA^QHrplrhp@C?aJ<ehvX``~}*=&)?zXE1F<*0l&^RMtoNXJfMD
z9N;HpKhpiB-Eu}XEOeG<Q3mlI`D<^Yv{#;Z5&hjK9}&aC{qoH@fFG34h=2xHx!4~p
zhvcu)Hp5N++)BFt?k-<51;gec=l6l<usmQR$Pu|=9(v&^FTV+CUh=c$Fzu*ZP7|ZI
ze6lx)kNkxqaQe!BKMYNNa#!+h_{%3x2MLg$Z--6C<O)hm3Y1T!4@w5f$L2wAu$<q4
zQiy!=A#}-cTrT?(DnjL(C=MPbp9n)^xLo9m#t3;bt-FzOF6B-|$-kkz(`dOX#Q|dE
z_v!Xkto-0os5l|7{u6+c@~97BXq?=69juR+e|Q<3r{pg5`k$5`c1P)qoIzWOvvO7i
zI+5Uz^QJ@0Ir%XsAkNDR15iqo|GE~e7vvYodv#Ghn_}}Ra;_FCF3Cga-A<QZq$o;;
zy!8-DneqTitjLkytHfC3%3q`;tvvb9PhfU|Ttdrdq5L;Gf?SbHDT}69ZlYTwC2~jS
zTBs<MKTR9n8}i_lD3!_Y*?=#Xzj_xVQz_4lgP1D$YFcD&$-@P}SIdtd1xt-w@Bv7z
z+<g^T?#mBS$h%Jdken;^^4BS@+aUL(uLd;AW$!>?liWgkyk>bDoorj=`yGqXwFmMA
zWOu7v<_Xp|`ObF$?2wnyhq^oE-K&A<k~7Ko_E4Tg-uZ6%-E%OeSN_~@!1c*rc?*C?
z^7ZuO_sh4^iC{qfb{C8pl)peXoQC8BKS0=HIrCdoK9M^ogJoD=?&W|{Bl6#yAaqpz
z>0)Ralb1w5=(xP-I#?&<MrV4~6?}K7cUJJWLE0Y0zinXIuQ(L}g$ERS$@%4?2)zjv
z2NnGkD|1yS6sSC;DE<eWZi*lB!RfAe#}&d3D;Cfu?TBL6F3NxLRMZKe$xHF|Tr?h4
zMAK{RttfmGJU)uS+aSJ*OZ37AC_+@Q_n2Y{?PvlO(;os5qNsZgZO0Y&DD^m0kyr#0
zrnni8ws1uWJtdKf(=$<uQViV(E?SXKpGSyM_-&;4U#!CMBP>0kxPJnyClxDxKo8>-
ze~@Q6Uhx_o-cKo(i~^CQc#UT1WJRe5+Ab=pt*A^<bW(8OlEUdbNJ&*lC}lZKv1>Lo
zr7KD-sLW7w%s?qqv5gKgSqk1xkZeUy45T=66hDz0Cs*+c<$>iX!f3Y5SLD77p_die
zu25f~aMOdOP%(2EfL9cwl%80m7@mMJR~2Ddz!fVRC~LMvaqSTRr3#;4P<c)9P6jNz
zu9%Y!&Krt=QB;;G#FSiFuK4MFNU3xv8sbr`QdH9nbxSdAGR&`5bdh(YM)52?Wwna$
z%fNb9@eRfC?kN(A0l2T&Ko>O{6naY8YE%do0N11tkAgHS2BXl{q6o?Z{DDG9W6`R}
zqjjiF@kt#>yF$GN9qdpzo)@CnshCGuOI?a44x~L)T%hn}w_^Gr6!s`$m?-rsHqZ&R
zPw|+9K2rSUjj`xgyjcX60mbf{P&laYsz%$8f=%Ja#|jtP=RZ+=NfGE_g=IF{MilKT
zC>m85%b|8mp>{ltu8k{#)__bXIw%chxAI>T@XpE?%VGB(Wi-8GdzE&YU-v01d!TT?
z@-2GR4k(jKq1QzjEkWf$<vDt}T$Qs~(0fRk&<IU#%0CXH(p~AGy8<4{CA7UctmJNh
zF<#0qBFX=GRGCd*Qt(#RuSKnoGUyDf@KwG=I|D!E{=XpGUpX-WV1ROiH^?z%m;)pb
zpD2TcLCT;g*c+_mQld_X(wibe$CY`s@eEb|OKBZp%CqNSZ@BWHJ6Ix=Eh$hGscdMZ
z`wvmdgjgtyR@Q%l##rU&aEnYop=8oY<fL+52ds!wme75ic%{Dw#`3f>|0yUuqnvaG
z>dz`u=<I%8S$GVkL?wf!vJ1-E0H{w=7VJYQS?S>cg%_1|zF<jF`q3J7N$IMcg!eC1
z$)U8_G-a9`h;-#jXRu}{SChLeQ~Ar=uqjJ9MqebzRz9KiAV>M=0xENr8z=)SPx&k*
zZ09T6<Iuy)%7~ZHR-nudf{H@rue9u6QM%GOtVn66bfK$C{w{D9D=kql#!;fQUIS05
z^4xW(xTfszh2HDRy>!UBp{$|fLYXqR7l?9Y811(!lr8tcc~g1+Z5Udqv{RbWZDlxl
zT<$2#8Q`o|PAFh#jWV$cm9<L86_C5i0&=?DQwnH4zprehS+>rhJe~<n^-6cTX4as*
zS`MBj<yTzvsaeURDY!-H8w2uC`9}^&x3Z}OfF9+$yMXUiZpwm%eaZs5boNO3b}U%>
zm5<3=HlXw<2g{(+HURZQ%2b*rpD4@R=ygzT<Uz`a(y_k)){H7Q??COCayxmE#+BRN
z0%Ah>1!aRes|Gg0m^~`|Jqq3f)$F%Wc|hgS3QaDmj|V^ws=OH(8CTVYd0;uD@=}7h
zseZc))7({x0vO|=s=fo6hgGv_#W|uHr;iVKsa|!^2Jon=sT$^ctF||S_^6!ep0lsY
zatpHkRFhI5#$WZpVw8@l`Yr<>s9JXk_#oBzLud+CJut%T5S5r_=}^`Cr!j_Ms^94V
z7NI&o8?i{0PY5cbRQx(<h*jN}1AapF_d;?Xom7R8v*NtU764-sRnM&h@Pevn0s54r
zx<X53vg+}5=)I`Y(!`poigST6X{stED$`Yg^vGwZ>b?VKrs^LGEM=+6$Ss(y`ic#O
zIjY}nXv<Yi>w|_o)tj`H&sVK~MECzLt7g0eM4_txbs(;&a%O?GNcE%^rK>7g3N#g~
znv-GSHPv|vCtO#}qt)<+>We~HSf={<e~?zL`kgYGDpcQ*Z}q0C>IaxssVZdxSEZ^a
zzuYa=WV-!vTeYYboOe`H%jx?Q)v79rTh^%RXe&~ynn~x2yQ-i%0Pm?XzXrLlI!$iw
zI@Q~8XscJvrn5(bYVQeXYE&JftzwgE1;q%ORb>=2Zc$C66Yc}mnbi>8s=7hB7i}sB
zwY94%>02iqDh*8=j!xC0Tj)%eDu^;U9;#BtP}{AFz6#Q#y2^#nUe%Fyi0M;(N&(?V
zsxoq*^sD}kg0uluz*KM!s&?n0ZAj&<g|Nq}yv1O7qWbk^;D%MQonRSJX?H@ysOp;+
zVfL6RFa#{)4%MUwXq-?L(}$OKt9M>P;~w>AufzQP>Ltg4KcIG{pV>wI{!y?TRG%lG
zpR3wH2hKz4iFeWFrhZfffV=w5Td4F<m)63V!|Jza@;jn-Pl5(dbt5Igda09}AmymK
zjMf-$wZrl$ib3j?SD`mpy^Ru)L(~U<K;v=so^z-SRmW3`X_$JA3C4u0i|D6}P}kCZ
zjY#ziLnuY5)t>_wt^SAhH!<p5di`V7{R;s<q3)veij(RlIRJ6$Iph$JS4+s9cuHOF
zC_v+B^$!6s@r=5j5{%BOUoQn~f_f2MqCBT|qmA5ob<bv0CaOO_1K<U<eLpNrQX6Q}
zOjf@)16EvAANB!BQAciouuJOK$nlw~4kXSr^}c-&ovt3C-DHM(VG>BDI_SUezhtQk
ze*<f_`V%MA=BRrqODk8cr0_|e`T(5|^3}hZz;am~;fp>Ms26Mk=M{DIvl!qa^)Dx&
z_o{mDdgv`yFJ2BniFzN|TdMwX0|3|5vuJ6(uKwaLRNhekd=DDR)UqGx`!D6{R*Lae
zs5jBNdsF@B8yI{`-AHcV+v+*wmbjxnNv_>$bvPwQ*Qj&Cz*4KuegZ4*s;8|2?w&f1
z93c1AU!H>%b?UzLfY+<<KMm0h>Y!&~Q=|GLKj50wd2gfCtls*c|D{D8LuZ}`>RJzo
zX;pjE*9hCxvtNSU?dtkSNb68v`3h~F>bZre>{1^gpX@`mU^Q&&Rv)FPYmeGNPU~Lv
zFO*o=r!FNQ<s<b0dSm+4Z3eUrsPi{toCej;(c&_sHk-lec&wiCAxwOt-bnt8Vf6_%
z$cWl1g~Czw=k%?>F?D?##Eh%YQeN<cy1O22yEW+_z_h)ZZIo8BPvf5mDf=}kl(=$G
zBd2^HSIw?8XgZ|9QjWJmQ_luDtcj%<_YuwJ@4@2f(7?@w*FsZE37khY&kRAfw`Pw8
zB_9pn3&dCR1-&bNnnqg3{58i`pcJ6l{tY;fX+(5$HBe){04YJ51vJ?QYgW-46QVg!
zJNo0AMsodyYThH4VVI`*LzKcbyD6X>p>epAA0|?Bf)>6g&77$q(VB@D0gTaXuRxz-
zH7}Jy=n2gP-Oz~FXn%ker!>3Bv3**zn`XTPO$0r2=QJg+faSc#gZxE_8c7*S7c|c^
zATvpGdoe1LHT`p7=ta#`#D1rzXf`;`qV|%e`v9b+YNmV(*=d@z3J6WtBz%QZhUR@O
zNTw!{&a_z?7dnS!YhG^xOO9qC-2=+i%x{B~Jk7o~$j;Yzor3k3HL3?_E6{M0QCX<D
z`zDOJqG@{<zhsfdp8^h7HA^Pb`d6&^Y(HvCG;h#YlxjXa4*WGuN+$G{Y5t;fSh?nF
zEfiL0mQjw_P0hTQfUnd%co%I|nrRlOxTD#YjZRc+n&_LcHJY7t;i*mIdI~bzHKSsv
z@6ag8wc4qPr`4<rkIsMhA2e;H5ZbM=(B`y9bCXWpy_!AuQR>qyCO^m{O;Za>{hAE&
z<PB*44T6e64UckThBTTgSpQh_NjKV_X!_`^G_1*>?2-}9?{_gWqnbIi5R7SZE&#V%
z`+^TRowZE}GUNV(b~PoQ?bUvH8nyehDWM?ywd3=EIG~-g2d24b3n;Papmqnj*<7{S
zB`6)z7T<wsZrZ8jwQ|=EOoAp4Z8HUi4r{Au);pq|`5IU}wR<T{>!n@&5QZMrenSt7
zw>C%yDGnd)Cv?2=)qX@Ph@bWjy*d8cWV#X(p#6#B7ss>}w5bi$dXx7mNPATVF~QpT
zCr}E}N^?;<u5CX8T&UKSrpYkvW;tYrYsa~$jL`bi^AxEa`~jsXZRH>6S+ur=-k+H7
zwOlvgW3?9gnCS`aMmouy)XsViJaO89X=sbrzWfaEr?kJ*KK-=z7I|vUXgz8AIIF$T
z0g|9K`|th}|CBjVhtdV@3O-Cr(moXlg~?jaEr4ItuA{h8iq@SRh?lhc>L4st8*>pP
zO}m}$_@rxhEP@dk+TVD9XKG`Q1CXViOFO=7?b5TT%+bzX1DUznvwwl)X}@m*$=Alv
zS@yDau7mQT3beiRA+%5{p=|jpS^=f^7HN&OkbPC_IS+_pt=|<?mT0%r_?Bwh$-R9;
z8=Q<%nfARzl*+aLqfJYN);JA-o7!^}#i-P_uR>p{w2GCeyrr$UfbQPbz7!AK9qm*H
zWsFs8ohZg$qb(~#ZLPM5c4v3B)p`u<J#8loZS~rVZvfb!wLS-yM(s0mAgxJTKnrHG
z*6<$8Zqd&B4y88ju9fIZyOzfQyhHm3U6gpJ{frKi-P+CM+Ue1{Q+Dwq?U^CE&CsuX
za|wzA+Gl989@G|h!{8yUnE{25wU^&S>4{e33E9Ki@OGFsqFqr6F{9c=l!Q8_{dxs#
z8rSw$05GBTeh0#K>(>7Oz0NvUa((a7Z6FWAUR@L2q1>m-m*IzT(MjQPbWA^}JJ$%H
ztInCGV0T?XAFS}u4TYidux^+S{1M%=X#jfa-XlN0mrgbrZAW$ex1h;ex0#L?KDsFj
zVT`YCkqB@<T|H&;`s*6#(FxGyuRz-|ou0m}6sWt?jZ%<q-eTC~2-Z1Ifr=2_dn<ql
z)8$E^B3ze7lV*f&*cly-)<w~y9;0)b4ic+NeGhFXbT7LAcT#738>Kj%sR^Zc-L&@s
zIHfE29TuL}O+A1vozV?HM%!6k9L-M&x@{(~oYQ?yn}+iaorsPuiMj<e`&`f+eHki}
zbY*SmZ?f)}6EN|Tu7;ecsk$v9;L~)0bYjcZ-J}n%<moPKfTnz%DhpOz)_wOODhqUf
zQ#`9s$Gi>P72N^{6c*{8UJl$<T?D1s7VFlIqg0}E{4f)UQk^OaJlAv~e}i1to$-aH
z8@fAm_p?lQzXY<&b*s`qDs)>Y*Re{sm?oH8x?T4m=C*Er7259TGHE%e)}?eqZ;eh%
znOn8Gmp($}U0oLWV(;lZL!rK2_hTbSgYHX5I7XpSXN^TKnshSSGd1hv^i#IzdMWSb
zfvzzWm94se@=<EjjV}aer*0-~jk|Q)CFtlw9iL(n-MW?JwC>R@eh+|N-2=)T>C@?U
z!?Z`bSMEV!zwT!`2@L5TM4<Aq?&?<ZraaO8N|V>H&V}-kM|AD<rjP1or2;>uOHKzF
z*L@fPmI+<=FHo^ZKS+z(Uj6@QlHaGF+<`%G(VJY+c2FO`2%N6^B08kF>o-h>g&z7f
z6q!7%=cr+}mwx$4l#c2T&7j-t-g-khjPldBJ&#6z{hRd3l>q%(a`px3S5T61us-n(
zhzZfZeh3Pq^ecV^AX=Z^12HjrpAwW}^=*5>azgKs0DDjBD+eJgPQS+;HpT1fDJAZd
zKDq#vr}e+n$@YwX5xh>0>1Xw4zXDH!evJ@3=k#+<qxa|a%SNC+QGekc)L+nFqg?VN
zeacq=ChJG{qI6MT@i`Qx=#>>ve@Xvb5ZY4p%-;Y=(_h{Pnd$m{t5C|&`z!|_Q$Oeq
z>$CK4dw^u?N0tNN$kAUt4ukXbf1N@xU!Ob+Kl5e%ak`jUpwIpUHWlh?;vnscK9vH(
zMf#8ZAoQw!H3bfe^>Lv9l<0Spldn{NCKPSg^w;jfrtA9C-=Xq`zTpr=m+8M#0$#3H
z8~~s~FHeRQHy!$Qd!hc8eo-H4Z|hZ2V7;Tyqwj6h>MzjMwY&Q7$S-$K{~B@D>wl%a
zbb~&U@);ZTGwBLSlYZ`JC^hT<cM4Kk^lR5(WZLu(*MYR_7gEAmhkoW-*z{2U9r^gX
z^<Vq}T#w$dcqbZr^&>H`txw;u8jX+i1E)|qsLx6OVo3kga*)UR<K(y;(GO9=%c$N&
zF{d$o7hUt(ZCF5kayDFKp>2<0O#uwuZ}5K?l?M#3`~cA|hG`Qh9W-p9Nz>J^BN{A+
z3{DR6uX!0dUxGD94I9bR<8AP(2ak{8*J-fA*APsPwV$DP3I@U7@L(MVIKZH#eAQ!y
zjnAMIXqZKSAj6WmFeca_NJA;a@H}~<j~kv_3tXtd^8>Vn88)b4Ot|5}F^~vDb{+Y4
zA`QjyXpAzj$^8>;SVB2dF@{xAsECDZw4E@lBX{CSL)?6{#TnMdKySR^ULQ1_GW_&B
z#`(12sb`?+j3J;5m1hn2S3-1x;Q@K&&l$2`0PehDlLKvuhQ;J~ykN*%MbW$@!@xVR
zCfV>E-Cn$CNG_(w+Hl1O(k>bN;PRNBYB;(9R-_re%s^$jA>%sm8HVa>kez7|e+rf?
zL&A$FWgE7UBRt1&@;6lG8m7@xoo6@}h*G{``wo;Y8=`2oEHH!~q4lrO5FG)9R}3u_
z87(r@m4N4}p>i84iwzD5ezg+A#W>hqYRIH$`Za@%T;JCXW0ZMy!!Y58QiUOy0xUNT
zCUS#R8eXM0{kFmXI4bWLzTkmW8}2m0?7N1)eugpk49_|P=eTd+Qp!k!fkoeVX*AsX
z4SJgluQWp81H&ph_O=?Hr}#sgq4`?~Z8ww#gQdgZpn18|@C&`$T?XH^V0ma*Pkyy-
z!=Ds>?=h^Va9Xe7(i;2}eTJiyVbgE$dJ~-(F#JvP#h}B`FM-}6!zUu(9~;DUhJIq`
z`xb~{!z>C8j2KpbhPF||r&d&s8MKr^JZ@M?zt4nW#wPT4xAEsHv^g6~`cb*Z_z5iw
zdyQ*LLG~FV9-uG#jc*-A+X3U{A0f=em`LZKgGNUh<+QpQ-_*dGL&hV2L$;f-q838k
zjUO7J-ov=(Wst+hmlQDVh%qh)Ku_aaJHY8>j0{KRQDYbvC2ynsGjRGC+uuT^ukjpR
z2=g;$lNZ$ASWl6!0Ha$Lj5%g}_gSz68fzRM!Nefr4Z6!1Y`jWgmk=Yf5|$n}vgg3G
zP@^}!&0)r?6vqxXZaRpz2&0<5vk_^Gp)|iJ<H{DujyBp@kR4-WUk8abc93Z&j0T#g
zP8y?np(xIHjgC|C#$7aDoHELG)7Id$k<$*@XN(S-Db5<do(|RoW7ib4oipkw8ScC>
zbQ`248iOf?;(~D*x$~2Z(m)uKY`i!dEEkPEPveJ8F}`&J@Jq&%zoRYHxUB?I(u`LU
zQJHQ$xC!HwVSJZDshP&AjsN|dim{D+9ofdUuc7xj#*JP8<{FpMHa5@rLpXr>MltzY
zFB@~7MXA8}s~zeKjp{GZ`zuC7tMTF(H-8PlRpS~Ls3<mS$hlu)TtjnFsqr^j&8`{e
zQ;6ZZv1$brl^dN;(ruy&<D_p;ylIT+22Z6?LAk$GMh9im-!g7n4u!XkW%OZzJI22#
zgSgsQECHa#xQt@2wZ@V#^!~1~m5b6nqy7~D?i;_&giUouZwsW<8~xTnZ-Y_s7Nj&9
zr|kf|$+$HEZH{K+^Xt+37URef03R5icSfnzxbq(%+Kl#hps?NOvKcBmjQ5TL*lBz<
z5}LY<FKz<ML!*@gmTu!ZigWfDTcW|)Yn-h?WuLKlCi?QoxQ-Uweq$&t#skK`--Dt-
z<B#EB8FCn(egTb-jmzmo@x=H^J@CWEo+Dr#F}`pcJflWQEEJ9z_tU2j#*MQmCuhRA
zie&FLHS196Y-;78Yx_(w6hzr?a<!oHfGKDY#KqM8B`Ob^rbR%QtEu*1{62?F0YAZB
zH<Lq44iI;fCKt6HCKkQThfR;^o1#ZdbuUAOr>UV0ZC<ALKSJeE(*`9h^fuLyPsqo#
z;%|(zugR|peeyFoDE{qln#l)CfJw0kT{>oJr(;o|$$2t3gG?V^L}jpP`AGmmOs_cD
zpvO&e8xWzUjufZ}Gi_2pVYn%XQnn&Y)5t9tX`22MOp7vYY(pv9bd;_I#Fzxn!-`l_
zE!}NDVUkj&*-6t_CphCwAAAjC;!XFQ(RRwzhKFtXY182y_|eapdg;h>*5tF9yeSE$
z2N~c=G<DNP?t&?lyv|9c8$&21o07@yi>8<M!on2OCutCK$u#d}08&juZ=jTB5`;op
zy2*zNK!)kpcTvhTMblX+$MnV~u;iNFoer6KCe9@2D=>XQNtuPFr_(8$?22jb8yM$e
zQ_735yTtVI_b{>4)J$1$H%tTMwJI|`LsNLUY5!V~YE!)%Dr-y|(xI@{^ieLP-8BvO
z19#7~gj^l>P0^d7zRnawneg?decz$fVET-9g^i{pI)gWv+%VfYrZ<}|Qg(8SNliIK
z4@}ATz|(3<ryPhjQ#Sb#+f7@qp{>J|u?u=TO=We!cbR^+p=%FKZ@q-dZqth|0@q_2
z3`8e-O}|hwTA#_I6*fIG{rMiG^qb!A0?U9YcoN8<=^Z_!IEGC7Xp1{y8lzc$)HJIR
zjbo-`S{OWT3Z^843DcS~h}muK^g@4~&8x4XZI8Jj6gC|&|3J%;i+Ol6a0kuZVPJ7J
zZ)pWNWOnQUaWik43ia-08J+k%%%?@rcf{OI&y%Oayy*#Qz090k{Juxcx2{5rw>jDf
zppQ8{7j3@gnrLY9GoL8{i@$kjCE5baYuO-y<|YYb2boV4z`|g&l}-yGW?3I>I&R)d
zDZF9kkI20iZtkPNb%gnOI$=hcHJ8w{XtU$}KF}ER%J)G|m?zOO@TB>Ft{9p)a|`9D
z#G7vf0CCFv>_e2!ntc|alwjtO+x47zh_>tJ&CLkRPERx&wP3kmuJ{pFB$@eiWiHv=
z@Cck2%?El>N;Q8y38tl)M_Ry{ZccG50&9jjlM9k*R-Zv_miY{wy0gtWOt9vdIdpE#
zHLsk3Ql2?niMD+6r~T;6W%K*wt|~CUK<j;>d5aU;u9&l$0Vpz8v(cri=DDlEQf$7%
z2K<^ig(6AU%~L6b;fC4sOUmXfGe_<KzTAA|AK)v@{iiUpH_ekSqq5T6Wdgp+>_fSs
zx6E#|N4#x5paSO|^UQR#)tEy!;YX`Ae|jI}uDQ|=<es^89;Dnie~<u{I`h8ADAk(>
zY1iLiZf=M5jpk|}y3O8XcBR`_&E_RzsBJNa(M{b4=3^%TY&BOe0BJMF`=hem+#Zex
zqQm?GZE8Es)!}ICGXFzSK>YnkJZ$PVUrq(-Gaq>b^2ls60MKu?$3p#(`FT3DKQ`Z_
zyHroi=f0r#Z`i!P48;+%mY%CobLTDqC(Pge3)#CZE!)uMZ24p=hIFqb?t4`3vph#T
zi~W|T$qRbG^5Zj5?_&8^h|)nz7UkEvT6RwXIb>ndCcw>djMfTwi=8%y9u~j1Ak)(_
zgS?RrFH8J0_zjL)CTu`>Tc*rJt&hcnTzI~g8E!Df&yw&Z6#82((=!)f>A}8v`Z0@^
zCX+ymkY?#1iwilVgDo{JFeb!OLwBc-TgJ8n9%^~v8L)&|W-kUH-0~{9T_Y^7a?qtn
zhvnQV&{)f7CBUDs3{gVjNy{FJn#Nhyk@GCxGI$eD(kV+d`7BObW|X1wjO8#zm(N<>
zqr1QfmQORla?X-p4eQTa{%L@)M9a%`Y`tLFHVl$vx&AzCO15+tfaRh^gCU)sVxiBW
zU_!T~QyebUvVii0(kzc=pfTMtS_>;OECsZ)$h5qh0AQ9Sdm%`+<>x#o%(2X*jG|o2
znGe93XA!=O%6to(f;X2fuBDJtVEN4odkZZmXxDJX^2So=E3zzG0%NXP6pm>$^;@<m
zz*=I_b%C|i5>*Km*DP*<kapd&s|4hRMMq0}nWbVWI#X_OqaaF!C5z_eo0b(c-&9(r
zQ!uc~vga3&TbAjSAh#`n<c_~%v2Q`C+Omrbt+C9ZSEbfca*)=)yA~hv&)u_pN*9mr
zTN*tfyUwy{3WU~Mawtuy!NPk6ERB{D`gB5zrG#=W9#~#}6>Y5+4&`yRS&kZkYqxy(
zF4{UQ-_eiOY1uR%{q3@hQ264Z<>PzkXSe0fRw(MRgde2yU$5nTTK)Sh{gm?c$Rb~h
zj`mw7Q$Tpga{FztKDL-BtNDrL=PsB(Y;h;`BbLAEtTbwgpe&0qi<2LW8MmyZ(BOn6
z^JCbw+uBP%v$Hi{0JHa47oG*nUTe*1l=fK#sgv;jxmbHXLhV88Guc46TD_>hhpcYi
zP~m1hMmLq*tuh%jd05ZVX6dl?_ID^9v8q-=jHk8dH`wH5EiFgeQR`NEa=op~CV|Dr
z8u(vcgmnjP^Zl#=3!uT@s@)Eo0<884z#Ye|voH-z545(t1D+u3KKh78u+@h)i6Pb$
z+H)PZZg>ecg<G3Wqb<T}-~bqD{eh%KS(jIXCE7YT2~uLLXTxDdtn~xheV?$d{sl5m
zS_c+_CC)0k1(tYgK3#M=WmV85a@t{CLGgz(RxY^-60C1$W7N-C*U{PXyw#s}cZt?7
z|3T#i>l>5{n`GU)4{gcTzB?cnt@+zwQ;OB=MM$}1b!~=Csn$huD9o^y(qSdj+TMf8
zEbFIdV0NyxbT3Gr^-pqT<y#$5c69Wz_2w8@3#<=lyI*M4r=#(TH9Hif$T~_ct*h2{
z3Z)iXw^Hb;#409VN2%5OD@eO$y-5%Gb!$7FNpDyyvjHfxHc<9zxpgvq6RpDf`4))2
zX+1$XB9&Gp9TBUnZ#W_#?Uq$Zw~20BHJ_mIj<t=_Nvf?$A45fr)t7<J)LLU-gY3K3
zrb!_8tZ97Md*Awj3-s1mpN&Cfz14$4nhn;Iw0mx}2GGjhWEFUWG+PfGg!%{85Cd?n
z))h2`wpo=Q()-tLeT7!j4(m?30@`UkL;?RU>o+y1d}s~(3+8uQcl?RU9_v>W4(PS!
z{}0{nvyPRb@{zTXQYiYZQ*|H%);H<<#Dmt?ZRpF8wU|8jkFCs?(WNKW^>pqWwn``;
zYQ!2gNYT7eYw<qRj#;-{gr;%pgK@~7u=bi^>26!tIaE5^I>_<4$2K_(z`eFgT7~!7
z(rMSf-?rxw#`1t|`BHS$#a6-t%R$@na>#VGU5G*HknQ(5U~#iqX*cO^TSS{u4_oeK
z^1mFm9nS;L5nB>HP@c9=DNy5O`;NBsM{Q@w-|KC=#{i3uZD}5a`r1~KSH;gZgCchR
zwo8cs1lXJ_A^VtZ$OpX-v<b*-9AxV#KwpAwpVMj>Vw*+TWXEkEP;@KQ7QY{yjxd{s
z=Bseqw?|=qgsqCQ2O@1VW#Eajx%>kXZCggE8!@)$+rSxXyGYlbPS{@2z?hS^35wdp
z*~%XQ7jLU0H|8nZvd3UKZ5#LzxHGoEzd_F0x+Wkj!Pe`AwsSVWM2z8ihpk48#zfn%
zbQkM_EtPgz7j4UFF;B6z4ny`O+vG&ZPPGjc0g+~V=LrDmw)r2SGa0sTXz(*_gOsV3
zWwSN`o^2~6zd(-ds~{MYYg_&~N_jSMFL3#`0NTu6ww)>iXMxSJA{h8Wn|LE+U$Nai
zh*FX5Q!Rj3ZO)YYRBXHJgwZRpoxcQ9YWs&AnAdEn<jlQp+dd6?Z`i(Fhqf}?R{FKd
zZU4Ihg%!4}Q&4f!=0od9rR@zHDywY2Q99Qx+nFZlyKS3rTm#~cZ8J^i)wb5N=xB{C
z=1m}KZ8?!B-L>5$&&fU8wN{Y(Hh(oNth1>poKSDGSYc>`ZFMwkYP78~KxmV#*#o6!
zTRt7tT5Q2|FnC}K2}fJ2?S=oAD%+VPu(aDob15sc!}bGxjlR?NbRkMzw&@g2e`tGu
z3kJX2)_WHQ_t^5LqocjHG|HInvkkn0(j%Lkwz2)Tp{bBPVB1p<vj=UL2O(w1HbsOk
zJ+`f%3zjFgg_N^2Z2RqLu#DKc#-V=Hwxgc1$;ND#zl4f$+jN?*CT!`wFlM*?<~dm5
zY)_R!+8%qwzi8WQUqD-eefBwjqE9aNiX5;UwD0}|#MNG|hrNgFsb`_W&HlLv7P{LH
zyn@Oj_Hu8)J?&H1qs`0y$&YCBvA?RO{im<}(iafwXaA-Kwf=VhUqJ%wp+%@XW)I|m
z1ls4mfzAZkSFVFG!S<>1K|<`S$G~~q9_9v?Q2UO*(WeOeQxxHkv|D_^5@qkYjc!NV
zS@ZzM*!wB5A=W-ZuDdw<l1~9}#M^Jtr^-&*FRVf1S^GB=s7<hc+=9|M`vLkk%msVi
zFz`wCl&>Hy**+@=EEnyLIE+(@{Y~=sUb25P1)Qn&1rz{Cv!A3qtaN)Qc{MWZ^G~8J
z)7~t`AY|F4KLC(xAG1Mip2NQWCPpvc9{D~Hh4vR2AXn@Ow?T^R?~!M?*#6T1gqGM3
z1VV4Ay=xfwYj)OcNV{&&p=00;`%=nsDzi`VMycGshE9qV_HH{y?WR4-j><}V{=cx|
zmc3Vx-|n`3=f_~VV|V=dJET?Hmw$(1jXjwBMz!`{^4s3E7u|%3_w4Hlao--Y0fSIy
zf1P|_jduIDP~T+#i892S?H99PVT)Z(Pv8T48>J$&+Rv%L(r#x^7^1^IKNs*$`%|=c
z>9Sv%34IUks~mr#w%gto2HSe<laE4SuYKWk0Q>Cg=(&1ipHu^5`tA0!C=J-B{RNgm
zyOkV8Lw4!gC_T0(BthD+eGi?QN9?cAz06U2RV#2~_K#ywId0Ebg~|#0K@I@Bw+DR%
zo1C}19jEi(p6%QI0)FrI>okb_w!cWpd;7QVoDZG@+haU|ciH|e9UcyDSD%DwZrh)w
z>BD`y_%qn#v0d|@pX&cCeF<2U)%U;i4g<_EFfi{s@60ejWtM5FS(%xdX_{G?rKVZA
zq^4!-Y$#<8n}Q%H3Ml)&Dyx79vWS2nhzJTOBFOG8DvAQ~`<(Cp|2#b%&%Nh-&bfEq
z<=%77ebN3*DenMneFW?t)aqzQen|T#mDU7mb0~Wmq!s)F?ugccaw#F&e~fgRHdMQU
zLKk7$7sK!^T)XfXIwQ0fr(<R!wSW6SBT9SgFW8ONW|zZmjP?^M-iy^v?tosLw*PyO
zc&+|5j3q%Ub%S1_HqjbjNm{!i^d)Nxs?e9B{g6&k9MgV4neR018SGh1qIB(S4@`cB
z*0cklnOYfz9J92w0$9q?{_Bn@$<_Ya379<X)?{Fx)SBouSfI5s11Z!N@bLGPmVE=D
zMcVC~VWL<&>px(YXkVxAt(9swnSgm(`^hzUQKsdS(RW7cPzcUcuDwE$#|rI#9?-AU
zzDLjevs!^QI;*scC&P<sttbQf=d_iZFs2&q_ja&btNn5ru+M83ZwFePcH&=9xS;K!
z4065p?mb9e)E3Zws6m_60j^Q|fMTjm+E7}HH)~%W!&q8O+7b%PUC{=FqxGtG!Xb#Z
zYClVZiECQzyU=LUhIW8l*Ct-ZB(!VK(R6ocJ?IG74ee%knCR5L+zGud?Ju|BQ@8ew
zY=HG>chR$?SIc|^$v$oVEpYwXIkaZFsr}+6Ms`bU5(a?Y)?OdRu<vN`NW$HrokpRh
zd)n-Lh~C%Q(4UojpnXUW#)sOgw&;7LJx|3ckG1E2g8HEL09B+v(XO}*XP#>N$AJuK
zC(VVzGi~b*3~*SRLD$8I_A;#lN3~lWpzuO_&-6NGeN6kl7?xah<}1+ZrVDxliXOV&
zgK*eWx9>FicI$S22*o|RsT9ui($!1@nvd>67F_eyE!hjneY#n+<nz-t#RJn{H|CB>
z*srS+LGpmEOa#dQUFH|)JE)7HDET3s{t)Hg19d72as=s8N+24nOACPLVI6Z6qd20A
zr*k49x-E28E>w4>5yKACeMOO}aGmTj9F5TJ{|>)Mq^{>GNR)2hai~Y@%8$UO7~QHr
zfElZ6e+}w!I`bfa#p{+*JUu~|K0@^`i8@mWV3KqmMIgz#akfxQ(M3&#iB#S3OYksF
z_X8zw({&!<z|PRkQh>|UojVCGOXoHXBH6kpVHi`cZWomu<msmWFY2Z1yMVrY-A-pT
zp42U(y1)Y6TXdkhQ1=S9E+)|_-QlHZEz&j8Q@&U?M2n^p-O9hwSgPC9j7cohSy9>0
z8Qp0XCdzezrEs)DH;#%XDs{OBA$e98o(EE;<CkF)s&%y!Kx%Z`O5kX%Zbd&N&+C>^
zoT^UON1q<KpmU-Xqp4o^oP*3oooy9b8+5|?kZII)Q^e+yZn_cNW!<V&jG{@`bsM8-
z)^$-Hp+&cwLdsWkRTLAtsxwi=SF7$1s<OJK`<sq2wCQwo8(r7^PE~B}y8R;<c8Biy
zY3SY1&8Et@PLu9sfB4p=3#OvbUfnKwlK1Hv=*t}ay0W){c1t()eQ>vRxZ!Y*=n_3)
z{;tk)H?Z&NB$Q~muWQ-}gAa7?({X?S-TbS-e5m{Qdx$*JO`xNJk9Dh8LVZvtcLjN(
zdx_prLpqbW1r(p@`Wi8_&vnJEP#o56rS;8-&TcjIU+9iD19VJhO+S;X-i=nlZhGw+
zxaO`eqvxxqe()aDckAEHhR7cMM0(?S>CY=*$y@&$?RWR;=g=2ZeDr^Zg7eiYsa$BE
z{#6rQtbY1*njwGv8hR$}*H8Hr<bXboQlbI+Ji22K>IXi8$RYi5ieU%p3n}gsq<>B?
zw_yE=4)_$RFQadrgz4KTuokXAQGl^T=s%5sNThyb3Dl$XKi+_PwElAnfW+t*rPG5s
zR-dYa!8rZbl^9ckel1-XiF%h%h$iVj?0^@^`i|9*Owk{wopGwZpay+M^`Uhb;W2&r
zTR=<G&$NVkx<0E2<}>x@sMIV=uPFk_)-QYub9h`ommVTHdd*UR<?1J%qSHiq`b^3(
zoX{VrgJ{0~x7~m_sh>0%*adnos<JB5|M5BWi}lVeASL=)RH$02KSd{CPV0ZpfnJ&Z
z71}<Y(Jyv}dbxfQJ<lujqE%3+)F-cj-Lv`!dQ3u<e#OV&s`cA&Ov@xXr~fw(GBx^9
zDvGPso6*|oynfwdaCQ2uQJ`JWze@{*di{FZQeV`E(=Mk$AK3xd8uikDA$dvv+E>87
ztbf@Pq)9)C3b>l}4pivfqIafc*%kd=%1&R^2Yv}hTlFtZ1*Ykmewzd^ZF&h^x*hsG
zbkO*Q-pw5_o%#c>L!(PS;Vx#qTVJV!-5&k-T8y_>9}tXr?$d8v0Lgy+lTxVP)Z0&h
z<So647U8$`TDm;$=)0%@`L5oELOb{Ljcp+J^_&F^JuvC3sM2&mA3-1cdZ^D^0B0WQ
zAJRJivA!i6ii7$meE@x;Uo{>EpXxuO!3^nhXv6qSU$YM8pX+y1%zaq@egwulqUWze
zWK>_Z0evs@FQub#OrLH8Xjj8UdZoJ=-c~}v-C*jS0vHcN>u+fFG#sP(+HLToILaQw
z)p~Gy4GSop=VN%E-b%iPRh!Vb&oD~$O@4+ebjkV~#$5*4ZwTTrrUQn)3V0u2u%~K^
zg9Zm$TOKlOQec3AhF|EsMUbJ2GH1aC&SVQ04;xl3#(W(y6n=-+5W}*)AfbktZ^BZT
zLGKRGaKm?gAQ6U{U!pP6(A*C$$`E@1deMdk+P%gY7VF?>tf7|TTycgL3LeKBUTwu(
zBp7O?;1Uhf$crRHFqL&A8&2iX{x8K~iU3TSLGv%Tbc5wCz+@QWXkU_P7&;HpEW^V0
zFv4s@P(A!TZjii!G36M3Fo&gF!$2Rn6Nac=Fp+O?>V@7(!`f}oD==K1g~md|2ec_X
zWk{ilz9NI_bJ#03RQ&V5{JUXkDmqII`4pTvZTNl>^vewE6CrcP;7I}Xa>KZv(0A5Q
zFp9=1!;U-PstrS{VYk*Wk8YLoh5%Zr))`9a>b_{WKt;w4hM8YOq0zulNVmywnhGkK
z4c=tF#qd!)ou<8F7;A^(RYO7}M%Zew9)(Q1!9XVuIt)YGfp)|2X$wfFq3eD0bs6kD
zz;zqmqQ!rY!Rrm^^%_h)FxY1h(uShnu>58Cbkp!&F`#c5Zcc{CZ9{A!Ciaejy$i{^
zhU*tVO!o|mL$Gw;AX@{_2ZmSZ<HZAp!&Kk&(BMN0sz-)?`qJ)W!=EdFHfYfKLh*@V
z+Yr#68uF<2X~@v_638>dYdn6D=Z2vIkYR(Isuo5JA5p>Ss3E@%jV}zdD2+a5c=RJU
zSCcWEk_2u>G0n5P@%>3?^)N1?;w4Yx&<W^!881=b)7vQh5$5+AXRe1`ALH}`@X6Ph
zP3PwK8IM_k_!%eDT=*NCDMYj1=xBqH9WXjm)H%Rt{sr_78vp(WeTR(8>7^KGG`({W
zpg~48Eo_2~Tfc+;VdLC082u4r7Onb2jNcE#r%>Z@icg0b>vRwaH%2XkzY)e)=~Qf_
z@#!j%DC1iJz>YT7bV4M?=rRD5SmR$+un=c#UI`L!6j%c#!T1HGvlES4Qwv6sWL!ai
z9wgP+p@$bojkoFQK4yF_hDMsv%LiP#QDXs-4C8#t%4Hdo>5zD~ai0@ljvH5=$6#`d
zktZ=-xyCD$jmS4zPXak<{AMwnDKI|04TVCZr5(6a#^+mrS!CSOMfYE^QKJA`Vmu)L
zS89CA2c+EiQ6el=82`KiuF^Pl5NKzOS12}9Wt854LbWk`FVM~z_fy$GjnPsAXKIZr
zYA}fNMo+49xM2M450HAJf%GmKGuOb;2IC1@)ioNM-lO=-Wn(?%hntM8bd;;vc*`AV
zEyh)JC0sF14F-4BxLF2`R-+&N<%BlldD`q;HzwL(F58X&eh99^_ygTlH;jwt!cwO(
zCk|e886RGRPd&y<ahT>_<JVNS(`S6tfyREL9WEXGH8G>V0PHQ}ITjkXjkUB!eP#@x
z*&8+16=I-c#(FJ?yYoM<0(-af+Yg}N?Hr?nhrZ5#(xcnoIfyFzqMZ+4$CMm(o_G&n
zna(B(P~|xHUV%uy^JnzoltSlETrkdJ=Z~(zd(&y>-6cS)a31f2)*9z#TA{Z(|FRRE
zH=V~f!I?+Sc2m(e?Cka!K6z{}r9G+FcC#Y%?cZ*F4hBQEud4!y+5U?h>M7fw#e>V*
zZe<Shh1<KRLcDyt&or2?+Wymgh}3Vddl%eg)Aq&NAhUnRIr=(L*pBuH%uw8pT}yzS
zwZq#Djd?p>_W)Y)j!*vqOx2DFbj-4ThZ*ghuI>oi50UO2qg0pQzoU!ZY6Cl3|AmR6
z9dA(m=g5wgQmDJT3{wcs$K?{;aDFZmDaw7&#dPEm6oXuDv1H!mf+zIjUDBuoIN9Yq
z4@<{fI3?EN87`lA!?kRevS3K&x)jj!CeJ0O4+<w-A}Gb5@1m@LUXjaHdg>Lsydwg1
zsSCFQ=1;q<k3?UY%b8~&XIx(X9bn}y@g{e4R=DtvAeAnss4}9;MfxR%R_(H!{vbh(
zi-6V{wJsY!MdNvw)pW<yxlE=F+y$3ibi-eC`Gn%c4K7LVps&$|3kG+|Wz+x<n_Q;S
zA>wA26$mznT3psxf?RRYQ%ttg<w?B>pgk_dN#;<&e`f?<w8(E13?#w7%Yt}XJvIxP
zXa#;nuq+UWt%A2HU)Cnr-~f?!K{W^Nh9K%yi1Y}&9MO1B@DEk_JQbAEJHeIdcmT4O
zVGm#+2boQ2l+4C|{40y-{r75QCYTAI_`%d`!=)J4>q}{wIq|6*{y%FSZPq^gY6*I0
zr_2WW9A1b2&vo@j??-i%)|}T#i?)v|mSd#zB~)gypovOqJ~7>f?!uW3kXaPF5y+p0
z*+X|RPcQ7xrr_&bCee~2y8S-?<POxn@c$bB{?d>QxTPnC(ehPXFaEvk5iOX%_8X5;
zeY2j<2`*oB5&vKDVGU$fE~enpw~OBe=&IxYVP;oPazgKST6#XLSv?*t-z%wZ;)hpq
zAphe^I*Gk@?i*+~t$T@L_3PWc(6nL7@0g*D=jiFb>2@*xz1jR#DEw^hkKQfgsjz74
zBYNciQbe)hodw76|J{P`s4R7lpk@pjUII_LB)tXURL;6rFt-_YeFX0L7=W*!?=yI`
zPcXm$)lcyF679bO1h&~w>=5)*HN|}atB08ff>?TfJ{N4nr6C#?G|I>lBm4)7dzhGa
zVZw{?tHxw{GrPQDVlUH9SEdgm8U~6l<4N(leM}jBT+xqFwqf$anI+%BiwGux0=P-c
z69l|WqGZNlIV`0xWmEu^$~gTBw4=-*9eOy%G}CpS#>^-Hb~^JO1qw2lwJ8wEWIQ{8
zoyC~Z5+|G4NQvg-OqCE^4)Y0}OUh&3*ac@!FsDP&n9oe4q-w4(hH6~%gvEE!XF4JL
z;vazK3+G$G;7Q>UIy+GyJVV9&g~B<MxIHDzrmRkp@OnF7iiNitF|-ol@$G;q6_))4
z*G>!5gwQJ!j=hDUoe{qAI~2-=y|e+Y5T?Zex>C69Er^^I_T>P&O4zOkS8Wmoegm{~
z!Vft(TqAt20Hju!{02bJ3mvJVvrc%6wip+L6UyOey|9{=As2;Fn_#Iycry%rjY60E
zXuKqRi;_y0h2PQX!Y1ME<uK7K{Chn}i?He?Kwl9~rxfi~;l@Q!Xcd~CL_zeLFvcFO
zZNiAJVdA>*O}hWug^MO)ydA>HF|c$)xRNfyPGJQd{p%90dkLgl_**YvdW4Sm;YF|T
z?*xeS3Ab9oV88G+IzV+(_y*myw}hMaq3^cv7`@5v2w!zZ-(BGW(_$#z6ZTWe^S<zP
zDpz?R?4#Y@fY5FxCgGv*i<xlkk&yorjgN%`N$_`2SVq-MPlO#5QF$tSHyd6I3D+G1
z_A}uQ%CkKe&aFY?u(0kmptzb%+>NognfcSAGt=y*J-95hMgyJy$~OD395Bbt66Zi8
z$ISIHU~<h)Q%Et-O!xwgC(N9xVK?9GP6#}_U^b;3`t@chPoa0w>}owE8_Y^58g|WW
z0##wOnK@sCWRKa63jpgiGy4DvH_bZecfDm+zYuy}qMSz*fA$tFiG@>pMRM8`?L*WD
zGwUbvrRr9Hk$5-s_lvgE9T$Z!PQsa!q6pdq6^MSn4N@ptO1JMR(K0&lQY1>CRbR1a
zh$2TNA~$n*Q7U>&C3B}muaUoJL@VdO!*bCS9Lq3?Dnut!VX0Cyc`fwMifkUBvr6>J
zIFM@52Kvy?IngH+ufJ}dOv7$Bzd{EIJIq5XKyH}dc@yfL=8x#*(`CMprn}obcMJ+W
z<|~@v;h?z%RjEBOzhjHOG4r7Rfaz*+y$9+hH;arm_~vf0k+!_P7Tq+aeHLwW?%K~H
zWH!9;x3K&kCJtC!`d@0;V!;@=gBI&6Ftk96i}WW4gDk9R!x3!JAOv^VVz>}on1#Xv
zB;3M{{(wb<1)B_maTYC97n5Ug<0?q5$wE%Y-198<%F&7CemTsav>42V`9h0tR-o^c
zh2vtlR%9{mWB6Tcv48@MB^Emzz@4?Qq_tR;#caAAsx2OcLE)T*?n5-zSezOF%6W_Z
z^b^)ubg#nbn=M{b!0i@`2wK)&u`s1SgWanZZ@1!?xn`00E%e(gLaEZ}y2blz0n=^~
za1_`#ERIo#y3^uF1{%99HqEBX%i=gaVfri<6+@xlBI`0lZdr_{75^QJvy{NRYcWU<
z#(Ng8PlOllmhl_m{SnKLSlA1(>@?9rI@I#|aj;>QJ8A(MZuurXE+Z^gCIcqYayO++
zqb%*Hm^j+<n|~k@XL+R=pz)R$l^9`y<=_Q0CRz?sgdy4Tx+_SErQMf6Nws|Z6x>nE
zS~@d(%+hxaP;xDAy$3JyEPMZ;^C$V1q4bhEX}PNupaqucA&@Dw)Kk*1$nqS$fQv2P
zNJU?X<(IVKFSVRTkJ;0f+g#9i#xjdiapjh3S|L?f{^Jj@O3SC8p|8sFH+qIuTYjei
zIcHh)E&6ILo2jhyyk*ByT7T48R_ejtv^;tQ`nN34{;zP!GKaPwcP*9mnEZQ|-}Hjq
zw^Y%qZoqPsZncM&BdySTZ22-h!v-yzJHfrMOs0V7n5Fk6sJn{eI7qsQeTw0XyLbl0
zE<ME4Cj-S(yegW$=CND6g&w+l#FJ!b^%7tC4vOAlvv)AU1L9>~@H;^K;~20HiQPva
z5-9GWvYueEr5E%Li`T6MXolE@c1@Y$T1v8Hi@RuVeq20{>XvfEQ~ki@ii0RJktZIV
z3V%<CZRr;=<%^#UV}ehLV=q9oKrEveS)uqndi$Rer`!Q45+~A`&|+~t?QlxOS${*n
zRIHQ2;A!#TR5(*6{-%h23h{K>NS2FjsQjryJarYIE5&a`pzo|Wl47-0;)fIqtQP0}
z1IcqH@sD&t)`(5ZKx)NvsY;+ue6b5M7sMtTOhUbQaRxlSDArI}c!Rjp0Le!2W`8tZ
z5?^}>l9$CDbO|(xXLf_Mh*$j!$t&VA+9O{Tf9wFRRcvMfa!q_X9sah7ZD+##b+PGR
zI<nO+UP!^^4)OFZ$lMSwq-{W_c#AI@yTmpcc+o9(*#OcbewWG-dd2s`A<`%Qn-+lm
z;$RDa-V{rz{vkl(We$;p5*d9BAXH*_3d}G`KCO$wC8y{hZ-k^sjJ_yIg=qmqqa`u4
zafp@dbODKzY;i<qyhK8^dI^&G2ho@$ner!Kk|n=P#IRE&3d&xmN-{SC^q6Gq9rUG3
z26O<+ki4L9M}g!N6%`dq20w>SMUr^Bo{A-3dH}Ohq8b3^1<9NgTHn-5@@dC@QSz`1
zv)3T`c>+2cCHZtN;*#V+G0-kcbjLB?Cdpe>5NVd|O@iGPiSJcNc1k3JAYGE3v;gdu
zsHwiXM<Q{B!Cpx+y$|{%7bv{hFDbnaw{J?)k^p^MGW8FNKi`qGvB17737rW`_ay5N
z1N*+DcnIWy#EcHe4M^<hM8iW#=W1X-k}OU{<73I>XkZUYmeD)?sbuY&KpB$s(|Y=u
zL_<%#=aSX5zZ#Y_{DPSok?5$>c2p8_2;2)vn>*D%j7iFV1-7eItQ@|%SuK7C#NEn+
zwjCZ;xqpE3w2HIBV0K&0Z@@h5v6_+#eJ`uui!ml2s|WvE@LElv#lt?UU?U{`tv+%G
zx8Ld|JGgeh>gOyp23Sp{&HO>DsgD4C$V&ACI8&gN8=V7-uqvmpL!?zHg?yu|Ud;iC
zwlbrqZLHP2VQ_I)AJcCiZ{@rh+zqQ73JX28`ke|&U8M^)Lefp@8U=&y(&l62y>!hB
zh<HjT-hiXKrOE4{w^y1;yD=Z>>s#QVuSr_^GeGxA*KdP{zqE})uluD2%FzZ$*GtiO
zP%5UX=U}NNo$)#>by|zQBhr^#;C_hoz74R$q``jxJ6!q?E#4!fjh~<|Qo8F~C`3yw
zN}&)VJw+w2vC@pWz>JfwFo&T8si|WfS`($4A|RS1-Mj)0CrfuP2FaFM#iQ@IwD3I4
z=SX8Hz@IC<dlr7@NtaM5%L!@4FObZaj<<r{0;vVv>4nmNDOp%79r+Y`rP5R#8c$1K
z{|$C8N}r9uZi95z+pyOt{mVqh1TRVZZi2lm9o`4DCh6SuXl#~7(qpGXnoEoD8&ZZ6
zsGZXLA&~5nTB!lkBlY+T1HCB?>j$|deM+BuzAX)}fcZPp52$?UzSM_S6c40U-vV<$
zy8TuBOb?}7C>{DldS@%`zn@B9S3-11dhb2JJd-w`gQw4>!40r9EM3dNixFwN80JT%
zd9<<cv$mw1mcMlh_O7D+)=eWI2dq7QL}P&U<QE_Ztv{@U-XZI)*I+)-S{eqsLDnhs
zjhbNVsQDP@VQcO*eNE?x^^;MsA=Y9u$b?#dnhO$Ued<eyhFf3ohHH`5t^F_&Wxas`
ziMF<(r)`XN3+?e@t!Gz2GS2$PyBJ}-buE2rKhfHg4*exrze)E<vURyXP*SW#^r3^J
z)@L_hoX4#H!-B{pO0yOmg86i7<r<I->-arD%d{Sy1un~aC4D+3+q(C2C?2=o^c;3`
ztj(W7KhN5D0>s<q&P9;DHZQG(q>oM2r|{{Z&9Ok(4YfH+hY!MR)Os|A+Zg=-9br>I
z%eg3<myW_;Q?$*ilopM#`G~$(5^Ix7S^hYi*g}|(x0&!dNSe)sPPm_Iqu&jZXX6$N
zg%dVH7Lxfk-!B17jm-oKbJp7AEeFbZn<cckylkVSh*y(MK@;3=wh5!Mj~1IKT6$fv
zx&Astu9|G7mq4b~X0!mU*K8&|0%)5}BW+)=+eCEY$7{EFz7k$^*pyK*{tX)i&0eR?
z-+zO2+x#>IFg-SUO8xiRux&u;v#C^o>$lmK3x$U^M~Z;*$fkA_eUELl0dREC=AsgP
zPi#yd&^!I9P3LPMLpJqv8$PoMrEt`9o4*R7IBes!0*xa!3n=6;YV!?knO<Plz`4r4
zo&Y^J*`&P?ahJKh54#>RbE<yyl-1Gudbg~OPKE4|&7$3cm+Z=ZNP5fuRYQHREXPDI
zA|F|ZD_VVJWj|no_sL>wVBSym-vCDFFUz4s$bQ+WNHiXheM(arAbX9{#s_6T$D#3%
z?A<KPT97R1f9oRI?!6E>ESp1BUq@v7>1`My6TgMVP?^Vl=!MBzl&}{rE7#B~D?%17
zf{933>;^a$E&Fu<oiVb012ke~lf5zCIN4|g`r>7ax1ldV_Txh6CCVmufF#KR@?j!H
zHvW5zB~{i>`_-eeHD6;Aj>#TT_9{*GYZ6e>W$t=3X2?2dUy&)>5>5ACmdq|6GTE{>
zX@`4Uwv+Z#IkNbh7*n3i*Ak#7WV`5GM80g#9_XKxeNY000@?c?!hE4@_8xGjWCirJ
zEs`}h!kJ3hszHFAm3_Sd3RSYnv_P+x-7ErTgDf{3B8@WTAbo$}l5Fm;XuT|ZS_QNw
z+2#VwMYF8987{WSa_GT&MYf>|8dqgniq5sl9#h59HCZKXG23L%Xq#|d*3|^bcG(au
zN;_oHRAY2Q_Tvu_>5>f_(bz3({0}4Rk!_~}k6zh_F;Fn|$r7hRreF5wWssY)<wqcT
zOZEi?p>E4g&}DK*7V;I)?#fj2(RfcbpH7qAmpLRt;eo879nL(Gb<?T2$1;l=^bN{>
zX@J5LS=%*`r?Mm75E+u~qZQ*bS$rVI`CRsADHPmHwg=qN>Tc_t2B$o1qf#*4p0=y0
zPHc~DSs>87Y&YKm=WY8Tt)%waZo#ra<YPOR63xE0FVU-gpY6@LX!Nsf+6B(vcK8hJ
z?zg?Y50(ztwouS7!1mS(7)rLAJRO5bwR@Gyh>qEr?oxeAx?ST;c#~<T2!n}iyKl`Q
znq&8zc6@nu#_6zBV7K^9NH*D}_d&nYZo_Bj>$3Z=5nQ*O%T{nbc3$+0^xC<;2ZMcf
zGbvdyV7HI9QxEN2RzUKJ-JMw=Lv}V4D1T-*74>(R3_A^n85*{0ABGnrcGD>kF>3cy
zHX2{pP2UK+V|Kr#1I<-_kgjJp`5anMxy#?-q3$6MUjv1G^82TN?I(Y*5-4Hv>9l_f
zmmdwsSR&;gP!2pwuB5+z5iRGwhkA@WVF9f_<K$Prrb&>WxB-m}`M=4qds6;N4oHDq
zZh*l;dFW>lsgTd6jX|Y+Ss-2A@-YT|Rq~<)n5dSY`3&mk<V|#ltww&o8GW_#4Sr}m
zFJJ2i*XrbM7_aDp{7oUIq+UMp4BdYh<v|qDZI%B-mFw5!Z&GlkO<wdbEM1p3q(Gxx
z{z(Y94!IAV+`1tjq7s-+`4SaKm%MibdfoCLSa3b^)epe+%7yeA>ywwvhI+r;%>s=#
z<r81P&@K7;N07WNul$_8CVoe*_zp66<@R4<hVIG#qKb+8@@a3Q@qzqw7!(KOM=3A(
zQ2x&tTze#6LMH(q%YWDkm_fPOPf&Owe_?=!PvxnD5E+su-$dUtd1xynpUdBf2RAGa
zYJi0i`951Tj>-?x+Qa0^22<eOjh!U{j62&bfs6<1I0M9!&8H9Q2C<*F06Un~{08hJ
zZ0{F93t``NfnGT4@-ikkg55|j%t-dNAK`Bl`yH*^qS;5p#jrv5Fc-1xwley$*|ih^
ziDzHQ0heH6B@5A+$ey4>%1LZZI_xI1^X{NAg`G}0^i=kh>)?*EA5(bY82ja`a3+oI
zqG(P!+ZX^78SJu4kj!L1qHtFh`!x@gZ1y~zIylbG+ygF$9d!jtE^D(A<IH0nM=+KX
ztf_?7k@@W19EhG|(-)z&fNjeHSI9b2UE3-47b=Y^Vn3h*qs8pX7$}smDUSeJ%HG(B
zzSC?qeWR+3?aYG68Fqas)XUjx4`8W+y-eYsO4f#sc%5Y#x(%z?EzJ<AW@r5`{&J2@
zrcZs;u#@5;TFd&-D(gJ^yc-&I>?+FnUtr_t*g!qInqF=fS${`JHn7dbkZff0=uW-F
z8i!#1GAp6?W)pkR5tz;FpH@I=VZ~G(aD}b^59BJlH5+r$%C_d2Fv4r>4hjvou{Y>G
zy3VdT3DVBKc?~1%U<YYKbAxS~1kg@)CY@jDVpSB`>Slji0M~lhDHJ&AWoOetnLc)m
zmTdj(<8~<AWT()X!CUOD;}E&cwhp544(oFUj^1U3U(@|}kNy5O#&n;xehz0Iu+9`T
z7+|fkq4AJyrsUltc99a?V|E^;cm~;vv}%9CdhCWXPuV48X^4G5r%|4<`-4HAv(6NT
z8D@L-LUM%Nz6$E2EJwlE7i_~(40nv}&87T<D|hEpz_@Xv-LUJ<8K_RogS$=ZW>4-@
zEx6sBb2l8`!wF--d2y9gmg>z_(utG3T*_7W<iiEh#=w^we*t74ckwnX`Ej?cF*1K{
zgsS29bLx2X9pL`C4D$ipngWQJ4s!1whKq-|Ju)~P$kow-z#uM{jt~ZOtEkTFFt@N3
z9v<N~(+U0%?nMGXL%DJE77ybbDZLcVc~a^qf}28DLL~Q1HbkPh?p3f9&F!E9j~MRp
zDv(&t+XK$Tako|QKHkKQhCwEQn|K^BiCpeqP)y=1sR%NetBeL(3RgmTzf|r=+NvGp
zd|E(`anpT3(zu`BfEVeU`7D5DaOFafOm4ppjal4hP8drzXHBc;<J@nbV1PMX^#5){
zZWFz6@;Fl-1;$Tsd8yFI=gw1*@+7yEN<s>_BATH>ZaY=roZ>3H!4+}qH$kD8v;7lX
z33to@Qp&yd4@6FLo?9@cGVc5$_<M${-hh#na}H)0b_JJ8<sy~b5Ty;za-FeIsNy0`
zGeE1ks}wUl$JJ1kO$}!}iMg!hrqUsT^W0=AIj`e_eF1ZUtIWYD>bbT&a2L6abl*2{
z?&|^C$jzq@yIkUC$)J9jOXA=~6ZeicNHcfpEWld03^$M~oO3%2UFFU$p!&a7{OAC^
z#vP<kS{t`A7Y46$-yA?=JNMQ%K<nU|UP0dt?&(rAc5?Nr0n^1LABB21w~|5+J=|Sd
z_4jhs6!`4pe8b^dKey-{`fhT%8PL1MeeoQPw>kIc0K3Cwn^XMrF1OhXiubtuCm{DZ
zEyemDaLtEt=?!pmw_<1yxy2N~e8l}q3xvm<YZ_n%IoB?bC)~@F2z$ycdKU^q+`up-
zpK)jDvU<*m>6tLh?U)D25iWHr8b>+%x8e2+E+LZczcFt6B`CTotZe|}rby;t&|Q&m
z6^$N>WmFaGsjyZ-W4A&O0Fgb4v|{vmDWogW=&kU-4eY&&GP<mN6iyt}eHCU@?zK<R
zMDYYa#R)2@@>dK{NymQ0S}Kt^popb>z9~R4O9s$`iqf~CaY!+T3Sa{jCJM#|Db~^n
zj9`WD_W(VtSZxV|M-(<muoR+5x&pmW#ii>24O2WEg+jO@Iuv~oia#hglBTGmvq$NQ
zaTIvTP)wwCQKlk>;>1~strXMAHYuJ^^7gpGd@1baD2i#3n5+1TmXmpkIWF+@gu=BJ
zuH`E(?t;ik#j|+WEl_k*4N9S6XE#7kDPB-2wn*^?1<i^TMv5+$DBgSxmP!?G?}5T;
z#mm!xS*GyJhsYVlKsvZ`g{iL@Y=z<l{Y8^X#kmAHd{&W2+nXwd6+P^$6#}XhKBp*p
z6DDdDhlhbys~BDZz4MCQ2Ef!QG;{-8P{{Ye(R#&15fm;e3jT#_4T{PXG&U;U8HK_n
zMaChxeOd82#b%lm+e~!is#&p<wvjE0MO1%uMe&T5npYK@=!jaY;)ik!`<kMjg=Cvz
zEuEFRu1Io(WV=H914xI$lZtI_D0(S!*s0Lc<<X@$PbX`-6`xY+caP%7<q+vr{QMKR
zKE=syjI3X=c9RKcHx)f6L2fC^C}we6p^-!Mjw13E7`&^Hi_v#a;aZHo`-<N$fILu4
zo{TXKC>~O!{6obEox*;kSe6F6j}?EUf*Vx4N$bxi3h{b)|5Rc51Ykpo=yzcLnPM6h
zOFUPcx1{fX3@fHCLhFda?QO`6Dx7OUUMN=0g{3h?QxZnu%CFmip}Fy)jo{q*09sXg
z@cP}b<jLQsRpD;_B|4z9hd)WBRbKp5+WUL+iFYy2dwBr`czyWYJk)*p_!>a(<6Uq8
zn?!#6z4egs=R@fwv!Cyz<lq5*GCkk|_*dz300;T)^urwDdno-8$oJTyF^Inq44;B|
z6YXFQ^SkZA9pStFfJg}6^)Ut!$_IRb(TDMKUxA0={4#pLMDQ7fuoubaxIn}d#Vb}q
zCYleV@I(yndKV;?UwZ-$$MHw~;YB>}O#83|K7+~#6L~HQToONyPC_K}tG7Tsh4=da
zc2oIr^lm)LZ!Co5F+P%Rl{7viA7JUcI}a{{PkjLknY?@*)U!-{<^p(=%{P1rjpKam
zOOVOoYw32#<+o9BY#tv%*W3wy>^@-f`Hfehc#_xBk-7r@FN)k3@`q_*a*Drl9p;O8
zDII?)=6AF~p@e@#``uFB_8at_=F{lXDdU%~1Lhgtv>^^`IluFLh*t1zO0-t;(aQjO
zmgf&(XjOa{VOR6l3jlMD|A8_jHGFw5`fB<2=mm71Z+iiQb$lLG=3L;P(#ON<`3O2i
zc99REpRj>{_!Z1I@&Q{xF7daFXuQman&v^Vi4UT9RWrX%24`CMgXh3q;V;KwqOS5k
z(2k&$zc&+-*Z3bP!P>^prkTCYH_U~JcHYSfdL4Y>>+tCYKb{tOoqYB<kS;zg93$)I
zj}HQ+hfknwU@tF^MPDEPS2?Xe`}t^kOyA_sQHj(o{vp-c-RASD*!vFePg{w*yz2#+
zzsEnLCBc2ZWC+{?-Zci?0KaW5Kp*neA7Gvy@y}@I^q7yMQ*(p-GCIZbgtw^0u%GgF
zH^B|@K9S&_@dqsF{PT0(m(ExY^9k<(W`wVq3z<<q<V(oB;D<6X&@q1IPY`icW~<?$
zn{qrYTHKX+Z-ettUVDx{Pvw-);8UP-9qm_xl*{PkW3Y1L0`whLMp7>Hh;r7?=nGMP
zOVtNq%Bm2`zlSUB@*oqTbf?H=q%wIL%ttAo--r2VrIrp2#wb_Mg+{FM`*CQDQx5LL
ztj8<25om(abu#o4m9r_tnxyQYBbv!d7YaV7C@ZhRr&MJVEliFoz3lNb9aHKlbeE>I
zc^`eIbmbfmv}P(N{R)jNr8m_;XDj{9pmAL3sez>&WeqJGa+Tqf!Om0u_Z&W*P$o~t
zbmc3{KZN;{%2bNK6et_1;<ivZp$FKfl>dANlp^JKUg#@U1}{Wki4sv;+z!f2N)?<o
zDLbjUu1twQI_?K$W+Y6ME8ln-CMuK`r!k3@$~!N?{8?o)ZP}`ne^JF>wUVb`>^bHA
zdl*cO(qS%0t+Ff_py!p6FJQh-Ih8`Q7nD7;HLX{^n+9@Gxvv_H4a&d&gL<RVG_M1q
zmy`=rKrSnv`@(LM^3|s>(X6zj+R+xJMI*=+<-4>ozp9)%4AQEsvxmqv<+ne=r#9tX
zAI#x(<*ZnMwks!1q1!>(mj}!nO5;-a)Tw+%CFfnrzrF)lw^A1ZXL^*wCR$_mD)o1u
z(Wl%=MNj=o4?SdVDoe|Nc1s!b3M}1L`Wex9M|pcI$X(^)r$D=>e1&#{_myXrP=BBt
zasnApj_!wt50zi#!L>)q1K(is9xG@1V1fpfZl?hDL^)#_B%dlLy=sDsL&}Enu=`AT
zkqQl-E9+?WJ**6v0GSbGIhD1IDzE$t$rs91QizNxwRCm5s?MatLpRl(h2Y#(+h|eh
zp_=g~I8Rl40Q7dN1}FltM`g7X&UmRNQTEeYRWt@?_NwCi=>6xT8nptbuPU1IV*6B|
zbitCJsv`i6{;FB@GT*O?DTLn#RJIo&5}@iTfolg<X8%IukSeqXeSxaklnw||^^U=O
zuquW;JgkaCj8k+(RYcX+Au78WP!Cmkbzly|RDw6C{ykh(_AbyORDSOPEmE~y1%pwl
zRS%&NtunO2nHbfUNq~t}Nqe9er&4x-i&yC>Bb1;D^n>|CRm>;APEu|98I8%R?03<a
zqN<>e-=?aPFJTgns@7BR>X^!k_OfZJC|V<$(p5=PXk@5f{s!2Ys!#rcOqS|rC(LZN
z>U#m4Ij;KD1ARHFzv!u#s}ih(exB-c6+}*`tX<KVuL__H)=AYo3ON?2>?q<{s45(W
z-YHewO*m7ey6FLf#i}C8f|RJHRHCueq{_}i>uFVMKD;PXolON=g{rw8T%{`hEudAY
zyywGUwMzXHTsx;4cL|C$s_AVQTCHl;RP>!!efA41)v4TR<#$0Pu}5RQY8DluUQ{ih
zYrR4Bt_*sOs=82+OR9iUh+I~gv@4*|q)MP5NwaG6e}HLGT@!)3q8fJvW4fwJIfTKq
zs-7)HW1H&2Uue9pT5S!zcGY_p@To%;{4K~0l}kOaJ5^QbK<QE~>c=3uRdY1(qDRHh
zgRxijHPzzvsobd)sb6JnqHNVoRWBu$ZmI5l4E@`xw{_s|sP0n);;t%d8$|D^9@Coo
zzA8cu@<4TuHvJD(-_wDLN2<>+!2Dy?7YrH)RZC_=?}_R+x*(pa(jLO!Ayo#|5<F9V
zMcb3-s*etW8&;hzqj=<q>MaU<j;egVh2jg<VoD>9sod;f$yNQ=Iymg6zC^1BcXhoG
zXddbw9r`@g3HQM5R^K^;A8n8N<yDaMQg6NnNpJNA+OO_a+bx1YA9d+bH2SLFz6GE5
zsXvZ}f}h&+Rr>ypzk1IAI`^wz``^Auy|5aJ0qU#Pz&@zf(K_Rh`srMF7^rR-1PM}0
z>Cb-$tGA7Z$YHg9B}^Pq|JDmGME&c2h=i)o(%*FmQ`ZbYJzO107h8mS;v)Q#k!q`L
zAW`b75eD~PwAzhIDPq*>C1{ORSImR?ICbzB;NsN*z2Fkm(<cBsQSC-$!%6C!RIi_`
zUY-WKDe9UJz@@4u)Po#VZ?nN998>EKgQTf%I)bFDH(8)BL;Vw7ftl*I5TInK-=|_l
zQ?@#kjyD}wf4TuCa@3CRgUeM<cpFoar~Z)=2q)B!b3yXed+3zzN%c}Xt5Kl-H~}Lp
zRG-NM_9^u?I{Q$hu9^dsVs(KU6I`NJ(g*8G)v>gOKdsKJ0(6;r!CCy~XVf(mODZ?1
z`54d&wNoBCE7k6LkhALR*C11+jt#`<tJOZKuzOB@I}%>hsMD^(e69NTwcyUHmwG{@
zPCdB_mM*CM>!DY#euG|^7u9AFaIHa|^)E0R)$SSa_mX-mP32{E3595y)TS&t?boah
zUX9KcwKJ7XUr{$$fV-;pYlBRydh4e!aZNpE86?}(S12ESU7ciu#&-3uQz6-*zP}KC
zH`E(GKx3!6XcUcIYW)&8+O7U;Jk0l~-<XF<7*Jal!l#GohZN&~q_#Ivg6OgOg%8M}
zI(0KNo~WxffIL-a(u#8kS2y&ZsfTWWd#*k!g5<DzBUOBks2e&l-cfZZ?aE%Lr&gjb
z&3=Y0B-8D4svweSAMh#Ev+YY>N8fS#v<!HWV_!|*)XKFt%b@jVp8XJQ{POKhv=A$>
zZ#e_5(EbBg$Q0Q>q5M#>{Wfn%me{XxKwqi-0xHx$ZNF*{(8}zWP;tu{dxz5?<@OD9
zIak<Qeg^fk_FtZ(U()`-DL7MYpYa+*YV3WML$B6;LBlxQf9LJP=Aab|3Of39!QP63
z=Joa?A7O?r+6!CI*I?gIk=920*J-7D$-ajYj+gDfZUfh3|IQ@1-E4pDI22m!|3VR?
z=!(5P?bxo`+t)y^)!vOJ_L_a?0l3{}&*&j}-QEN1bd#vve(QF$cG$0&0;hWH{f@xX
ze*2-vfVpY!#zOR#eeq4e+_pETkpCTfF)fYn+9%R`?4JGOP$=BDPx%3o1NLhc0PLat
zKm^nu*{}Wz<gxuiN2m|lcjiIliTzVLEA`ZV*&C2F4cUje)9-6Pa}2G|?LVgPClA}t
zor=a0d#`Gk7`6AJ`iK|y^Cv)L%>MDmfN|CIKLT;nyhQIPcg;95=%HCbVH8izzw{Q}
zt!a7!kv*D!ynyMYIl2IS-kO$7Nbc1fq&wWlq|rCRgs<k^6twQsu#{c%)4WNGEq~1t
zilOb-Y-@qy0nNQ#06nOYo=4*$P3O;02-N&TsfHlUBo~+n)^zmaw>zwv;17`_8Wn{~
zLNwn#f~8Q+#XZ0b)AUjLBV4my3%v-9DUd>ck(!owVIoSiVKzjgH3PIPi_t8it0h*`
z`54&o8mF_EuLRA`%@}W@<{%G+B+Z{2F(t{G<tN};swU+j^p0sl>FJTCv7tOqhGyp`
zkW9_;oe;^=d{hU!*&0{6RgP=gOtcrz(fo85Ch{~%Pa%3jQ@015`I=u9=sT&|oCq%p
zG_O!3y-?$I5Mw%}say=0B26#-BE_0Wy0=R-EqBmZs`<hJBBwPH%2k(X`hN%58I46E
zB+E6jL^M`tyeDE1m6~52>HT+B^J@hZt2FP?YN=Xtjsh<=n)hVTsMXx0%-ea*02Qay
zX<8}Nc|qet!RvZWDvL?DsF~W0#^;*L)v)B{@HWNj_c}CEjMK+qCjE`3!w$)`TL^U+
zqp*C0!#@<ej&?Zy8r^?!4vpVIG}%E#)0X1k*A3BBhaI%NIqJ|&ua095f(VGDIXHX{
zFVY>>(0ez-;nkmLW*xpPg%?>4U;AOYvK>yZg5+@r2_;%`9M)2)S+2w8dB8m3Q0zhz
z>o8?88p|9$!_LPfI^&Q>g(Mdo%&1hY-ofb}L@zpgN*`}&a2TU?Rincp1Dv_!P`?>N
zyX>%w0=-QR?euPJb~us^^%jT7KcRQUp{@+hTy<!;3$E3{?{8pUbBJ32g*JzWqd>Xt
zFewp@?G9O!pl9lEczG+Fy5aCqEjl|LUV8%fyB(I$fu<gZ`cpvjaJ009h^J#5Edq8s
ze!CrtdmKym12o+6kM+=taLl8WPNZWaE#;#er_mcL+A;of^u;*-v;dfKj=r={j(1F;
z_ei4Svl^gem>id?VItEp?GeVC<+#xfo!O3S{qQ>-ceIhgiyX%V&ERq!$J5F$&oPOP
z*Oxdhq-=hv<Hv#MJMHK@1*FFDbNUoutz+f4Am<&!Y4=;_xQo*0^^SqfG^36|FF~@=
z@q4PozwT%fr^3Z{$1}8D?{M5m34|Mtv*@+Z<v8hkz;rtzDvyVlV`%}<o;V(%bE8ik
z3x+VJA;;8%_<f!^=FsDL*m3S3&>L}7MWJuhQAmXiFC2gR59+Q?r4-b3b9#xYLEWA1
zeg`i+oYtH6qSMpq-Jd~rJ8kO5==V77pyax@Qync#_Bxqe1@Uou;sNu%PQrKK_dciB
zC3sQ$Ii*p8)ZeLRBS7~%IY&bzz-cOd;p?E2ya|1WoRTTU5a_hA2YNwHNLk@I<#hjD
zNFH{Y`LYR49dY7y=nQqLpa^l8(=YTbhX|)%V$m1rB%r8uqEojo`jVWU(E>fisnP;N
zOLf{wkE>%&2_Jw<cPgQ{K!%fBFGMn(HqzoD%c)=s3}!p!P<j4wr#bW#$Z`7UEIiD0
z+Ax>yzdWb50?3?j8rli8e5cmmF$pJ~dTr5I=ydlo?3O!4(Hf+}DT&I}E1fbX!2PpM
zAJC(_%Bh}Ct5iEJrR(CHlLg(dwN5A30_D8Z@(lFVIfb;MugU538jxnEUoD~D?z9v2
z941kR)8*;#?S@k*?W{YUY#v}Px}4G}Ufk_;@)7iVoL*2Raj(<Oz0mJ-8l!Tfey7Fn
zVc0jFOh2RXmQxhfFx+-pd>fK?oZNT9ivuq$A7n5J{5SEA4~)DqkCLgAYmdM;55W=K
z9VU^d;0PUu+Aa9=8vXbJ6IIxH2`XH{c?*7{wd!8M8}!cc5oq?ohOeLk71ZWof^oF8
z&lUV#0#EY<g%krgAvi<{qI|*N73iH5R8r+;fnXMuZWRiC@rKAL!4x_rP$Xz_fS##X
zuy89pE)i6FWB8?loGNIX7VMe<nKHrAL*UK`Qk&6NE=Z-<e~sYY=5gc9`vmUvwDx4a
z9Dw?6#%2Nx?qTlQLd1))OooCtlTZ(lz05=Uf{hQemR=9Oj3f|^`<P=NL&49)e0&|E
z{!E556!$Y<I$=x)m=vlo3SeTB;Ke~E3n3=+C`N}gi1{UE19so$dxR4yFXk<boFW)!
z9w2O81MFa-1LY{fgr4u<m&p|RA%XtC*`HNWgMZ9Uc?=tK^AaHX(O3#Bd^}_-gN1Js
zR=|fJ8ZGhvt@kP2;QZ!)5Op~=147<{z7`D8SMULy)H)%!LRVdx;K79d|I>1+Y3P0-
zTs9T9$As5jfnTm>(djf0vk%?{W`NmgIzt^}aX1yKu@;S#wTQErhEh0_DBfZZEq6O)
zKX*f>Pv%DlO76+b*237J?44Wa8<B;q1LtA8ivmkNwqH?6T7d1R%Yc2vcHVYyQMNl=
zA(?3FbqUTS*)E?AFOqFtDSe${yC?yDskSd?fIDit{}+tvn5{L%u}x{V>%E|#ZhPGq
zB*XS%5@sjIcEWCm7TRu01}U>`-T<^}+e(TJ*4qYs3;ip$OEu`bYJ2P?U|Mary#*83
zY}?+(Alhtee*?K^`|VOl-nadU&PhD5HBg{&!1n7fa1U)m(qZqB$@Ys-U_Z7Ep(OmE
z?I_j9KCwM<4A@U?W1J!L%=Uv^h&;Cqpo;Qg+ueg`9I<77fx%JRWLhS_uzhTWxfruu
z{SL5Q?Z(sc-py`1RYAMk%?SbLW#{=7P`vFHQ;2V`-TF_V?qg?qhleF!yA2Fr0_;Mm
zvgV-O3@rwF$nK*C{9J){R<s`ovRl^yw0OJiX91IJXQbDBs-5mK6te8D)6vWvyA|6p
z!a_UeyO6wQ_svZ7wb?x&%yzqlF(4gw_FF)@?52f4q1(>SGzFHP*?m5UYsXa{s(`_L
z^2<NMpr8D}07!_u{R3EvmS6t@ekaKTC=;4452drgxpM0#fH@_P`V~H%kq1$t@0>iC
z%H%G}KlucbE%Lp2;M(P<DDK!RA5WDncja?_huO#SY5Ps^W>`Kuo+gU*X#uyFy)_<|
zd{_^PqWH4EgaKwB8-aUC<i`e5QI<bjLw5JG&Tg2z1MCC(LsJ2)PbNeTvf5ENbBOg^
z2Dby*ds6fTvDYU-FPJU(0bqyOga^<&!XBxk_<KA%><EJitXU^C64}BI8YtWO0CSnl
zG8AJ-VZV|CCY7D=E8IWIUY!ofW2{F7NE&;97BK1T9Ew+FuzyobGLt=B3dt<C@&F8G
zvy13_#&Om#1}}2i15uF7W8=rs`I{5$CYtViHhCU8PqO*GAO-9t`dej%>^j=BpJE$n
zphav2Rd^P&4`^pu!bTflsgzx_6mxN!{qh)4%GmfeG@fDSOoCoH`&JmHq@I18i6J$!
z|I%z<XE&!pp@*#-4-ZXu*k7os>JhtYH(H0;sO7*OVI!_Wbd>Fx4gDAF6m#g0u_tMl
z?8@~N0(&1<B!P$@w~=BK{v7)w{UY4<G=Lu9o{mRf0Jo4Hc!#)ejqoXu+fHZdg19*g
zp&rb2uYulS6Zg9X*dttFCrAueWd)g7ZZsNP92YhYF!9`3`d(xLcl#z_61mSx;YAYn
z9~IIkb6w+LFqPA0f;-Bo(xGsS+q@L>l*ScN!B;xBn9h1;aMN!CGm|?>AA8Q?3hRJb
zz?p1#jJJ?m!qCie_49yT!u?6)99OUnjVQ;s2GR4J(`+c#adN6;Xyz_T0ouZCE`j7#
zF6kKTwsKqPPVMHjli^Gc_a!audbtmufb?+}A3~&`^F0iIZ*mj&fV;)5F;S`UZ7z@A
z26wnjdU@aF=F*YCdt8e(EZyghuY?y5xYlFf2Dp+Zn6`)9JvYES;>;eyr$O$Q-=Oe>
z8+{+Y!BcJx)qoFi2Yvy0#x0+U0Y2w^So(Q65v7_&xR<C{VU+u|iSo}cI591r$2gYO
z$*zj`w?WZO(U%1ocZHnF>OB+>>C*L7>}f%tpCb1YH2Nzx+e2Z$Vp=UE4=5Vk0d`Q)
z|1bUMisE}9feIyEWkHHBOz<LB@d|~-;uP=DN-JK`-cIqq1Vsha=OrrgN&uRqnDY_1
zWQ7y`qA7~qJy1+lY^lRMA62{@fWBi2NeW1sV&`o*ldc%K3D+_dAv=JbsR+h<5#<e^
z(iL=E(YXqkISN5PxLj0hfXh=<Mu9_FgDd5~@)cv0s6VNAnO=?s3NtfUDpcHT#&n-j
zET(*Hk>YF`yeL+bP%ghj;X%J>sp7wH;o)h8$J=NuQyikhF&7kfXv<!&Soaka8WdmT
zgET5c^z>;`Bsf5%8Tn?AyNdK|Oqc1NV*Ur9!-_*V4T~iF7o(V(QAH`8v3a5R=Q}ix
zDMmb@@5-y+f}?JHGi?jp`K5iZ>%nLL4Szj(e>ym`n?FDS!#(`+)#&r$AASNbZ$9>I
zpzP(pih;Th|3(tHeY})bLw+XS?`5?5^V}~`+|O&i2KE8|_B?b3@I(E;KFAkR*76Xa
zq(NgK|Hu<#3gYW&W`cQ-XmE%5ZeM^N;s2%GUkE?)9U4RV@rM8%#vi7#h-7{eEv8cV
z`)kpd%5VM|+)>^%HvvD%F<#>a>@@z!H0WpWKVOI4Og^6;J6U`d9Z<^VP1nI4=U)$p
zr5qkd$njR1;_x>{m_6m2U2x|3lz+N_;yrbd7A9Jz{mR0`jcLalFf*g?ecuK{FW$4x
zLF2(04{3{YWX2p5J+DG$_|YpTY=)!;XgM?XnM1UE#@+FdshIK2*AS_lkxO@a-wgUA
zkfP+7JIB${B>cDScS@4~Hjh5w{rfY@q5N^k5nlZH%{VyW{M98WZ=V|t_#Hu=P<0g;
z<^tADpr#$NyGdXf4GAB?t1kn_S8#$#5&Z;z(xNm-u%GJmg9Y>HV;zx#H|Z%JC2$cy
zKUz?tL|?LC8pZxn1R=v9se%qVg>_VLb0#p43-n1e9D$HdW}Xr(qeGNMf~@&yEEZfJ
zfO{nZQz^yiss&z@yFMofdH~QG!TdfLtQ8DWl~|KtZ3~=f7K~5?vqj)d@24vQKYy6G
zAvi)Ao=!m+Wh%P_XRkrMTM+*tJjACrsOqp+@Wp#@yH7AMg1&yi5fw0R3Mx;cZ$PjN
z^|yGO33kz~|45*s_|Id(X-cmR3L>aPZ&VQTEj)c8@LU4-#{^BaP;h0gy#nIKNG_w%
zonapW+k;v6J0v}s4+&*Avx4?qdl>O=FzChX%7KVC6HPg!z072)+Vx?Ak5Qn@mx)*p
z(S1w~Wi0)e86$AmpRt(-vY#o92RXou&=W6!S^W{XgUlsbF&tuka|Bu-vuy^jgP0AI
zArj2YrDB4^Of%I(A7S2K2MZz0m3eS9lnJEj_b}#k27C%<zWIvkPa~K-3QtBdlNUoV
zk@=o7(Mim3C!EP(vLY~;OlICWXk;;-HXzx|&vg8;fC;9sNFg(a;u@!zkZnLIV)kfZ
zx0u;S#S@iG{9ouh%M_+UuZn4=uvay6bvxA0G4`wI`B%dXQ6Wn$v!xp5TbTx`ez?Xg
z&H!m+&Tog}bw*F&`5VmL`%vs=R7;@H!z>HL(0ZBi@8C-4V<NZE@5|ht1@CV%aqdvK
z#dz7G?>4iM5`eD4!){RU5;o8wFn{6l4`9y}BvgKm)^K6+co>Wm&i@%EjtcXsi1(P#
zIUOWTIF7E_bm640z-0(O_Qd383iBU9;gs-12TT+RKeR$4YHr_xYb8Sa+u%xtM>Xg>
zEqwb`m_H+2O7DVl;Xw*kR0tF3*QzuLcLu|ov%*jVu&ads^+W%X@NOf#XcaEYgiNQ<
z8if-0ki^f<XnY{tUJZq(!jCP1{Q{rCfWjU#HVf13Wfm+zqqkW<)miK{`{o(ceas4I
zyY6e&J`ID|XEw47+z~TNOL!P!W^$zmN2uBG3&4b#P1p(&ZnlRqOA%&)-(wOZ%^F<b
zeze&)^n{2pJ3*t5HDeP26K8f{1SH<fM5TENW@U6-EYZx_6METZ@5$lsNwZoi*eNxW
z&4<WYv(Hb#i#oH%bje;en_;4h{F>Q(J7{#7MaZFl+ib(@khx>#H;hr-HCrwLxo7q@
z?Yi!pH5f6%2WC4YaCE@zQ!l_gG^<<>^%rI(U%|wfS<4GZx{ADF;hLK$kjhuxMN|C%
z?IHTB2nwDeod+!J7R5AD{MAdea5p-=MHlIfwpWx&2RD2~)7}R06;)fKZ=dK0EqL%%
z3JTTui=<Thcvz%A1d$`6{pY}ih=L0s87dN!zhR>O!!(tmGgPA%AzDt0nJCd8RBIWH
zKUoKq7}0P%{r%Ng(fCq$6DP_HgER4>|0Vz?LF7)E*>us@Pk@#oGNao+Q#5Tg`m#h4
z4rtk^y8t;ZvZBa#jwp-DgmXnN=V62=L_;$%3HhRBw5>cT`k1m#1)|m)uv;kFLYKfP
zQA8}A|1A>b{)E<I(Nq_}oD~^ff~6|aY)bxCi!ujc@SJE<6i5v|u>?{pI_wI&=SA*U
zAyS90l;bD7Aev5j%ZsA^d*B*G_HV&NqiEIxfL#&^=+S>!WJjmzn?zq!L%msae-r#Q
zwTQ}{F~TdNyB@&q6){sl`b2Nd0$RVwniknNMaEMY%q>wmCDLz;ez61gUD3Owe^0a`
z0+RPd14kk9Ky;}PjRPXZZAd;8ouh9>jEP>Oawk`F$sxGrX1=5r>h9+A!vXDKGT(6!
zou1}hA3}e(`R^y;qL=yVX%O``-!%&Cz2={N4bI10Kp*PxHUDQiK=+wX-vQ3g{FPUr
z5Nhs4<;h{@y=@pvxVb(DeG%s0Z2=c)K1Mm2DDz<oP)D2Zq`YU0xmN-_j59Yip9gll
z`M)Z#3Fg`(Kua{=@gwXenU{WuzGU<7Z)2WQ%%#~-Of{cFsi-pZ#tryk&zRRy2Cmk;
z@C>}aZvM6iT)VlLRwJY4SLo%GY*Cj1uyTu!Z2(qbQQ?oqYZjpt{Ajl*F(pFdmc{#T
z!nXknuM<!lvY2)fXwNK!$uxRPO+7SxEDupWJkav)RhW;meBTu!S(eon5IJQT*a&CJ
zEoV{*<TXnb9l;r}TzwRnUgGhTst?3h7BE4v;*ZtvB2(<Y2AH|xzh0yBht=Zov;;jT
z4q6FCUx~>9jsB9+U~u~-1{T}_NyiI_9FzntgujO*Ur}{*kmM^Z8iOVChTwLnMCA*~
zFv+hoAQCRwU=2qjC5P#pb(BQp0E2OoxFh&s;w3%wHP{46TonENt7J)z6#7Rc(SM>d
zU6P#vE=$su0*8-FD!v1kBeB?tzC6kNWT2gpoU?=Zd`UZ9S0^QLbc@$W-hLhAyyVL!
zOhUcnt%>Msl#Hu@rOT4NwCHS><eA{b6-n9G0J|pHf{WB7x*;hXhZ%CWN~Kh=r<MIx
zXza04P$b^lN)m`s_**@rr`G|i7%Hs|w0cUFYr$4qBxnq=>ZF%(xK+D=-rM+3adrp(
z|E-?VN2~sz{nqL*I=%dz<9z&kO&o=vz8|DY*dLzEqy5*9b92$L_P=tVu6uGE9qada
z!t91Kui^hc9i@!s#(5v%|C{3Gz}3yWi{Zx4uC#OAx`Hx=#*c$ATIVb}<Go#T3<x`}
z(EHov)EB_~_bx5A{yY5v{=F;qRp6LB{>8uD1QqrsaPER-RBP`cxc4qJ{RGk`c<V1{
zqR0P!!8IzdIUu+Z3KAk%`#D5H1+FeY4-=><ZIB`G@`qO^1SSf~mk5NHFs8GDJX!@`
z5R70G{Qst9%|!eoiivH9>1gKpY2d{$rbiU5k7XK9LN|`d?}Mkw%#PpCn8MUZ(U{JZ
zK7`E-W_Byan8~zKd1Wr+>I5#2Nu}833Fbx|NIui5!ZW*wS(yTbVrCs3WG!Ld^1|;^
z&cy!-^A*eus=caY>RMr_hIwI1fQecriwe*#G8(!*8kmABaJ`XPPm88Y%$Dg8xx&m?
z2kt7fEC*aGqoAU?4rbTO;BGMc-o#JQ$@EjurHk41zf~|3R1Lc~nM#U;-eR868sa{a
zRgT8TOhF_R2ANA2X#SrtE_B5VGd(k5*H!3FPqs(mzHrRrprjFrssByj3&A0J#*PWT
zrP*<1PEcaRjfo7vNZgt751{M8Y`y?%o=hASF79U5YtXlcF{7}p7qf0V=EIwrTMG5P
z%=K*a`IwlSl%Mfs3ZDUOA2Up~G=7X9y&(OWNtD0d&upItkr3ubH55acb2;b>V-icy
zm&B|zgI)?_@qf*IcT`l#w)d$zr%!haw2cwNj9`u+s3^`jBchID8pY9TKoJmyQG$Ys
zI@)GX5in6A7!c!Nz!7ahRLlt#bySRiiU~0X%-?TAd%rh#y|?aK_pjTl>D{$!r>d?~
zr)uwAhtdk=R#t6F```hWBhavae2fFfz`m5tILOxseS;s+ZfQux&A@xH2b6y^^j#$s
zhUr6Kqj$wT*gd@YVleplc7bHyofN(DOV5MQ5yJ#N{ePs1W#ofHpc%!;K^~Z%1g_v#
zozc9o?<uZ5(UESA5qI3FGgwMLu+3ouD2aP6Tjxn_V)MI0UmP>lqST8;Y<g=5UCdg#
zfg_RW?a&KJZ2c>kypk<A2oqMbx^%6sWhEXEvz}eG1=z$qSArpxHKeuoHufuJT%KdM
z$%b6kj`A_iv#z(G=>og34yB9CX#z@lETSXWZ!)ck0u8rWcN+eWSVbFDzGfkLAbrow
zH$n4>1-V1o7q+T1WY6HXjli&)+pGg}H&5MY1>5khDk#e=gPm>-o=o<6GHl(;Jgv}x
zEOyQgb^F-4)&Tq2=&C>-U`<mXDBHy1Xp?=C)o23?PO;SE;6Kfd(BQ~n`IMt@hK(cS
zS$34-z2{h1?XuP-lT+XhTTI@myKL=Hl#1A?-VpkP87T<#l(nEfE@kmF+rMMG$g?q%
zm+XNRvv?@2<!5u#tq5=|<UdXYh~dvE78J{sB9JcUwafqs{INeecLjH)=U}ApgHxb>
z9S@_e$a=n-^1C+hT)Gao^O-a~rt#(!JImm{ltY}!haZBby<GDYr7S*&md{7|Uz8wx
zj9)bE1jliHb3F8(;4Y-_JWnMb`2~Kf8#pfVFEr)-#rM<3<|e<5r_f_VwB#?;<#Qd4
z)B?W!GwKTYC)x=;;_oM-u9!2rJv`=@$vsrUD-Hm7!c+P|(Nq4cJ4l}KC6~x8_M9)J
z45=49gra3HxgAYEuXq?G{=DXG$tCiJUlK6wEx%WGj)Nati1xnYA1N*LJs&|SejoU+
zPf_~Frw#|hCtjEVDbe!Omr%GuK2EEwWO-l|Y}zC@Cu4TV;xs*f@u*xh1=y={^*|U?
zBKL?u<qW0GVhCNS)awjOw=0S}jLBA}J%G@2N=hh@x0G2vWUo>Z1NIL}=w-_kkgFL+
zQM7BC*^We}xk*Vh1)4Tv(Q|h+<5R$NPvaK}l1Ca-dI6L^(Y&G^zza<uI$-q{|4$J{
zzt^}nM(K;DN+Z<GR@XAiSg#UCX%_>-pF!SWs}jiZa;pL<!@AJAdiWGGY6G{;M}vRs
z-U^@L-_SN;{HeG2J|VptWKN8xAm?<p=L}7LGgwcWkLEE!$<*`N{a6TC%mz}H(h~M$
zIG7XJ<$EY4u{y(0w~mdbD9C#Do^HWgS)0)?a2u=L1MJ&bck-c_Sv%^~J**+!DKpqc
z3b|&oGhe{Im*v^Qlq}{NOZ)$Q?3<$yv!B`j4w?h(fexi?=6W8DImiams^AcFOa<d%
zW=oH`Il>}`K=x5~fR=X0*j)1D9cORHf${{?FGtf(va{|0r`WfYs(6~QNXX1#VKj)&
zu-_9P>@4dAN1h26bfq(3%w^551ACq|sD{!77I72CTw|f@(E97l+7G>agGDuirkl)(
zR>`;6xD8;)XWjOI1Ut75ko|z2oD7nOtVcZ9AF=ia(Iv%f?-)=%W=|VKN(qBon<j~L
znj}nV{ADDh?dEPYk?i4fDX$@uuO#<+7QaFM-fX^{GQ<w^`;?P%jOz=jh1>`i9B$p6
z$U$<Ba|5JY<WYWLxW@ZMg5(Y#8V}Q^%a`ZsfyKM(Y1(@v@k7%9R`O~4DgLvHKl=jS
z)!c&|g==_DKUkT}AFO~OYx#@0;7j2Ti(uV4u4x3y_5A)@*t3B@?FKCy`P>NbZQ@lZ
z&1y4GtO<rcc*1p1rt<h^pxna0F979MUVH$Q+xQn+4sPcM94P-Sjdx#+;tsxNE-L@z
zd3yX*W}X>{Qa0~(5@HVWLFDp1$tO|{#wot}C5$=Emplha4xiKw443$a1yFyPpKXo0
zEBwScl=67iQScS;2A$DIh5W~h5O$lNB4^GWUY$I~rn~$@JUEK@d^%lwkKc#}<9)t7
z2R1$6NrC8#hrAd4evi13Ld(TmV*_cAc^jIfOZZDCP(I<`T}0heo|X;pmS@oNwv_jx
zeb_txh6d4l?$i>(KJXKtfc(g9ZiD2Li60pV_?i2qpmMHU*B$*8DYtTl&{+BX3oypX
zb;wt|T=r-Rk_376Q<ReBX!7l>mA6x_*dOxNHLxjFHc$|2r|e9Tmvq_f6)3ahrpo~K
z$)9L3b5vfOhqfG(*Zly|$7R!j?I6vSkI`dn&dWaJp}HU!Jcdmd<vKKz{v|)7i|!Jh
zf{MD!@`Pp3dqvi*fH8UUe)@f`$~TvR<eEJCHyCqWUQ!XVZ^-GjFhFn0ef|W=E!mrv
zYx%Mj-P8-@nUpeJDF11qi~X*AmBN}uvY9rO_hg@&P=8-e{sk%?$u%f)Q!H;Zpzg6;
za2}K;^0V#We<HVe1@K(n=MC^eUgiVYFXf&)!S_k7K?nAyD@7_8W+<;dpl+tp#1~+e
za+B^mvz2MBXiYOm@z{ojMkynlVE#Ns41xL4%2o=AEmUgJDaaUQ8jZkMr3X1o<CIhL
zV9aL4a{x$oD#3KIXDRV9U_YX~qI|F%<;-D7DOPGM1<7a4_QxQJQX{%RShRYA@-kx7
z<>%=9Z@k(&AF@}dcTYiRqI!K6N=a%Oc_mk>?<l;#N`3VlLf5D@8p7VSYPugZty7&U
zLg)r{bX77&9l9CFKUCj3(3`5Zqg~k+HNO~qTh%mrdd_yW`XPWcmFENOP=B0`^M_^g
zLY4EBqd4#~ZP5qSs|1aM4dme+@+=&NdO7rl)kClS1e#&FJ@7g5#0y9mRdp4<2W%gQ
z?|~U~jA-1cUqB!B-Vr8*XVXeyeCI@bPN;AXZJIcrS~kTb0W+I@q|rRb#A;uLx`j-k
z47(Us*#)X%SuAyW92-&s>ld*p-=Jj)%z@loE7&W#!V}p7nvs%N!b|EVR{tSHr?FnX
zU@)_-6f@t)X3+}zFf+sgoMek>|8<Vt>;++$m?u4L=Q=ahqx8tzZ0lQCQ_KdI0{eyq
z*+S@a9@7d67x5B`E++H%=&uPUN$C(6$1YHs8J5l+z?#73JOS$pwv3KCC$dNi94E2K
zZJ~1=+tvq^>)A_6R@=&2%!Bl8Z1P?(n6@)3S`enOO(xLnVGFyVl);u#o>wN@MA_Dd
z*%ZnsIKnzm2sMZOMK_EyY`-JSy3F#((RPL1?Ez`|?9O(S3fQFi=$t}!Ee#F0&6ZOL
zAeDa_1cohq#7mgAmCq+1?KTr%dJm-A`6W9DP2+lc*3=H3*%aVUUNZ(wJI&AR0!Kct
z@g4YA%RhMntdSRvM_sa9DHkf%$_ia&DYBg_nzl~9-wSo?WvvtVHps*1c<n}6J02vP
z<lEFGo8|U#u=fwyluNGdSmpPosEku4(VlUU(v$A9ixtO}uxW|nOc~KjmB*K0(=w%)
z0(J4q3R*J=CA=|^%awgkflN>aQTqG}C1Wu3CMut3l`%*C97wHKyN-q4ZE7P|ly<7^
z>E^pz<t7Rl?@?!df{9t`GI}h>eziAkk+N036r_h#V@;60QNKS3%4lu#J<zm8>rw~E
z<JxtnP&%dEy8>2R(%$v9tN<VKx|JZXgikmKE1z>~8?@&&zd@dfcYG+hnIh%3g;)o`
z|0HRu6#Wc^9uKn6B|WOv!1tazDT%$;JW7)6?M9oKU)mpmj6N3^!KS{&^jId(>6EH4
zWMKe=daW_ybEqrD_=dG-`0icf06vF@`~n)EU34h;w~1}>eRRtop*`&MaM&O2oMi&h
z?;f-Uo%(xkD44^#(s{zUEWQvmkt~xIb5U$T3cx(Jmx4K4Sm`Oyr?ZpSL6XT{QwS`Z
zbtYHKF?M|ykU7k!0l)?J-D#Mf#}aAJc#F*>-)s>(qetm6>*kJznqIS$=fL=hO|eJi
zEPlWPjPv-hsg@;6mD6<Qxyyoj=!veYX@5B$C&6)#Woc7kMJb!n3}Qa8866<>Bl9=`
z_Al)9A=osXd-ecw7PtErl(YH$`;ZjL?H58(6c3~47B4aJyV;Pul=pN3$5t-FP};{c
z?@G{t_c=a$BQSaVXaZzh<+isW@fvSOX9BPD@27+527gV?;(I);Hz@D(Ev->{#J^b!
zyNdbBvRno}if%Mdd43&q?mK?62SmT;ZPru#f4&@E4Ti<Y{q{iiVtL7AG;*n&oCFoi
z<acOS`P%IYt+rmW&QXx`iUrW3_chxP1D$V}v;z{}vTH*DN?FdDvSv>WDr<IHB6LRc
zp+7+ELjL6%#4Y3U6|l$inI_sg3GPkU)x6(E@UP*sgHTH5MbXf-mS-vGQY`4)AT*Wt
z832YYeDiJ~(|K(hknG~^82I+_Ai8Jl$LR*>J;wid3n|CB{c7~lIsOj@_FNv=5Pa9T
zeJfC2=Ru#y|8s-;lJET{uS{F~TRbZRmHE7A3K$FcV2XYha<5C^zs(!b$iKt;jDw07
z+!%`1zvS#9z$-p1p1OqBI0n8qyd%Z>O8G>3jMRHRARZQe;3Y3mnkD;DD$8tntTWwz
z*T~Jt!Iml~Sb_0?>_TpWEAkyW$doVJzk`?(c|Gm%Udw)cQTIt6{uE}<QTDHfF+yRz
zAT(8p?}^fWWizeo&M9vTA?%KF{x~S#Ds39Vv;~^oG-)l<Bz-|CQPXl8J^yX3raol?
zZPL_<1~y4uOTm~`YHVfbU9GMl-~AdjQUT*;wTJ>@sp?D0ui2tLZ3Nld)Ri<b>`>3X
zM`^b@%nMeS)oT<o&rpLGqVx8uUQNJ|r3Q3?Y5UdT@1QSRRcIM(I;dWxv3yt^?gsuN
z>T5eN9#xAent4+F<|;VOs8#wy{aH152#h(W4vz)@MYYvo%WU`4mlJ4fx0-Ju@8_Nk
z!QcIt8es3?;R{U9!7;F**G{^Cdp}48>o4EwAhpl+PvA239rzjT_3T1R#(oYpV8gE^
zWM=>0nnKxtC#k^vqdRS?2F6CAX@i;+LB!x%x!@X7Z8SuCwZ0F^VJm9GM(^LNLC)~J
zVqknOEBNlaD*=>#J(D44#Jqcu;EzK%Si*Fnb-*Z7*JKm|{_2g2z-f&^`dbxB9vJPm
z2i0Td(O3$a@h9-XF?)dtDeVh2p<SP#m17q?gDK-WPzW+iM~7G^J{*YeQ-1CS{0vq~
zCkLZgp*Lh?GbBGi6W(=-e*mIx<w6K;V2V8hsg5`6!c><QJ0Qa~i<TQ6adczrdj2Uj
zeBK+dc|9eU?a;#g`0mf^LG(!D8CV*6VG257?C)doJ)%w=BupCG7@yNJXTXX%OrnT=
zEZaf}4sp!g4W$J3$Q9C4*nz6FoK0nm%_#0<SJuO@OqN&|mhELjX|m5^|JVu>_OUH3
zq2)NMG99ANvL$|?yv$O9QFn!%q?7k|nJt=!*<&~Dyf^XF93Y)Xv;}e(|Bar7u$v!E
z27{T`S&Bwv^Bki!uD@G6`5ju5&yUxG>;!r9K*(MpkD`5iqI|?3#;lX`>`+=S|4a+J
z4YFM(Qjk;S;cbzZoF@BGu;8pb>M%&o$pJ0EkSkY5%dvMk`4TO=B)_7>w9B$?7bqXg
z;WwdZvC<ERD@>X#O8xr4ZdZOS0>@6JVKOSymGzT>+^zJ18>ReL`*;U(>ph-jRbIZJ
z)SHJ^UsZ}|F<7W5<dJ%!IDbJ?o+_yg(A*iC8!3<#rTO(6S>g*cL4m;%kJbeFL_oXd
zC^`O@nea~p@QW<h41Ni@iJA!kz^>BhvtY|fjdgPf&DGewgP1%`GjcrN)cl%_9xc>3
z6@#)!QyLBMP!rJ|4J^@o!C`atnZ_{+rY%+v)0SzK>Ie@yb_<h_p|nw5G67(#I*L+O
zcdDi;=V5-9T89?phtwyIP;pc(r~{i$sQ29<ra-MhF6et|muw&(t4k=4_NlsF3o#$m
zkeN{bS*>>oQf6x}(X0`ty+Topc<m@Ui<zJuLrKI*+QfZOxL(_$DP(Ta>IxtwRolU2
zgUTJ+S^fa&+M#q;IjOx!H_IHYQv~cjr@cd);5==e-y!?Dwgc_|ZfR%M0cD}~2!(R*
zYPXd@(|zrA+G4)c78ir$jrLxDFnrYR{D{&_-J2#bbdK)qdGJN)rcv(10$uylwCIk}
znK}5E>gLg^Aw!om7vQK)rX}7LT><5}U(<cR1DfvWKGN#wp|0UL2*u;*DI)Mf*Su_b
zr%Rp$g{8VHv^D*#JM{<*GxUupVmDjQTB0se?@2qOCHiM@TWdD!`!}Wg&ldfo2&mYr
zzqucb2ldxqg7k=fCFN3`(YLscPRP~wcSGr-zBeV7-O$UMA*M*bCK|>R>lfBS-E;k;
z1K@k5*HOIct=@JKguU0#qX@(&{o8L*H@(6x@@LPga3dM|=2p12gW?Z2tloK}yKh^m
z)U!oa*OsC3fz^f=;3&2#$b_aRR$27qv*%X520{HS>)iABwdPyD{s}->pVEUN(VCIB
zf3>wlp2!sIqclNmvEDoqb!pZgC&AEk>p1c(?Xm9H6Ue>RB@@A5I%M674n>}@PP-1q
zT<h&SQMzg!)c~aV*0U&4^0svlxzUQOQ`}(T1MB;UwP>PjmRCYuv`qm0<G47R=e96r
zsm;fYX#H}VA84_XWV4ZcayxA5(cGABb80P0W*bJSABSz6$Zhw~WHXao*spCWlQkb~
zvh9JLV^~hxktl<{11w!+xPxI?HVOFuV!)TtojY09WLE3$g1LU@bjbG|yc%W&ddz{G
z&>Ivpi%6!d%V|F#rLBxxJw~_K>NCEeY2U7(XnKR?rjh8U7CA<IwtjFJ+P;(TL1bss
zYkc>fkO!hswP~k2sb43=SGz+$<`T?7oP99ZNDMFBR`AC>+B@|R^B))H<mWSP%tWWo
z{$ZoTLqeUxLt2Cf__qiO2?=(Z7&2~jSg4PmKWKtmg!_kuhlzPLc&+%VyqS|nd#`@K
z;@zv2i^q6h|DQW|@pg7}Zt3X!H=I}KnDL_mgTuVU^qRa&?}>rItz3xCv8AI+OP5wH
z+qkrHZqw4$D?B7*OqiE%V6c;;qtlo`U#C%ieoj8)f?5QJ1pBw}_wfyMa&~rX<>*ZH
zU*E#rj#n4?Rk`lJ#+p`PlftC`lCHr+j;eFd|CX+)`yUx%`ZpuyZ$rc@FxYR*_!0hI
ze$ASBl@AxMzY~N9j1Thln$Q*lyxGW5uK=HMBQWT~=_mW&uZC~`{pHZa_5Wi2_q^YT
ziZ!|0f7CM#{!P!6UrVB>Chz+n8fczSi%(Z-X`Je5f>&uYgK*PhOyTs%5O}sQv3xHo
z+4JG-x(Ku9ZtRZOYR?n-M@a-Za0fO=jB(&~S&WEv;2qd1amIoF6!61W)>OtcO$TX=
z!!#NPZ2!vSw*6YU3zfzmRHK&HxPGn4_}7|tUu*XLtwz{7E0xW$b$M!`80n*_DDwAL
zFzCI#ySexD_Vn-&&rhqB&2ftSWtfO~uCy>G`^mAvVu!G)DjHX|YGQW2AP3lg|DXM?
zm`Z)ek1}V!kTbux4)qTn5g0tGYv9O`F!LlQ<;y|y`sd1-o?`WUy+#BlSk+}N;^1IS
zW%Gd_G($FsaX)BUi(wDBjya1pm$kLcfkm3JhsFD~)&|kINK-rV+9p+8+oYXpp1N84
z{)MfFPjH`d6`m1gN+KsD>C6+7^nUAvSOX^i&00J2^NtnfRaLsS^>h(4-e{_rCl9FL
z-PinlV}<-`mAm!p;yu8<Xa6qtE^S(tz51IU@2_y)T{PTR!MN*!m3t*2Vz^P*XW6te
z_o;04e6UD(AvZR=2V1phR;i7ri+9&fF73SggoN2Qc4^nYiFtm4m9Ca}S<EYokgy8Y
z!njq_K&+0{=*$gvS&jY}nX<#$oU+3vsDijVRjnd=D{@287XJ&v9Fk@8cy^68&TcK7
z-C8?0u`j=b?Qx@UY1!7<MND)zT&fg}k>_sEMe-QtZfNIjqn%<N*2z$Ti2@HpeG%tj
z=tCck%}QrO6l2rP3%eL<FmbG_p`)#*ggfj1czK%Nb~Vhaz@o*BzJ_x@eT%9}Qg5jm
zZkk_TMtpHaneLj^@K;IdBl-WW+*exsx3Z@Yo`y7gx7KcLTwD6La&>cV?Kje=UAuPv
z&TU(@bawU~F`{j2e^>LUeugGCVz;-UhKL!Vt15o>F*u0Zef71)r!B@xB5Sx|sQAst
zFxWN#YAalkr0IYhtCrc~l8>RM!)*x(^T7NiQEI)!5vCzyIiiwP2o{P?zJ^A&cO<Df
z72%+2NwCN~+1HS%cfN+0FmEhL4+*+T(r1DVCCLWNRIW>~z9czY${iy8#~AQe(d<9Q
zc>Ft)Ev+fAJ#9b`h9K-+w$2zz5R3E)1S?8XEJ4Udg1*GjgFnJpZYN2T2-cLOs-Wda
zc56ovzrYZJ_L7u9u&yLMA_zOQ=w!0bfnZ}SYQ8gwZJUhun%H43;@A$<CJ2I#mNG(k
zWevpP$+G$}=6#!u-^yaqAIAD(;Rszd(P^u(k$CdN${;FkH3pf@Ta7>KS*~Da<1Z{v
z^d<02BoinV&jGmPD?05ldSbjR+heT9b-p5VkFg<$3ilWr@s_@#LI#Sng>wdq9eu@M
zDxMHCsMyC>{6WQdaUMlBP`o2>Rybq=3>QBWP{mjR0V09G0C6zWSlt%h<g(F+)m+(Y
zoAB9dtnP-WbJ=L_XhDbi8p_7QVU&C0Pr)CJkG}uHo+E6*Zaep1(6`Ic8UKPVEl1-q
z6=gP{E6ZL+v12bRj1X4|bQUZNAXhXY5Fz>k@Wy^(au(WKO(YXGN1P;V$6)b-uwz7x
zePt}}1a6B!0t3Y&0=-2Bf#sqQKt1b%u_%fC`;2wj1L3?MsAoVW@-mc-aR!<V>kh-N
z5n|;&V=Z+-8%c63=diJxZIIfbimFGJS7)Hw$x_|te^dvQS3f{?ZHvArG4=rTDRenl
zP@BX-LNx>`#)8Tfw%I_X1J&1p3Kc$t(jaspvvS*W#STL0V9jskR5ntiL5i{%7hbM?
z9IEpz98se0L2&eK|Njk26Ul@M0_v+lx#BsYVu8A9(OxRt4*?Ybr)3Lcc{fQ53{pg;
z@_v{mrk*s`*7T61Iu=b4q7V$)^q!J5a~Kl`_8A?huMb0rYbuk1EOH~n3__&<HO;lW
zRnNqELOH<8J;fp{R5%;~D(McByetj14>d}mmWIwRZ)hp1N9)Ul#EFB%;a9?>&*dna
zK2yMf8H0Yem~sxEw@j*P(UC2Dj)G%CDZEwXC>y&dqZEKynm87hbELmx(t3;S(*-*Q
zjzRC46mH>YH{U2_TR7s&InE&H8(BWGaLp$Z$FHB6<ZTg>C!P~(Cs3}I@z*idD8=Ej
zAhk*5LLN$7s;GSZ)fXKHN2$W4=Kt)ULPFI?0PI_fsyyL*0;o<p{?CEiafPvLz9zZr
z%H@Wly5>KHoF|U?dM-_~7<WQAoCHdTQ>ODQsDWZEp%wwP%%bX<I7q05NJ(g6kyRjU
zPXX1>z@<Mer~u(ZD2<Who>JbD0I`EmRe>sz%TW=6od$~I*wI(20@0UHm4LEbf;5E^
zsv}Tc%VqJ#o5YLL#)j%#;CdUxw>h}BrwjKSV<XL9I0&0Af^v-YSd>@<3}%iD0Iu6C
kZs%a;7%22-fQ=T;1U`yE0CskN7^Om*@hmU8Thr_R0i%1ivH$=8

diff --git a/Debug/Libs/sta-core/src/devices/stm32/can.su b/Debug/Libs/sta-core/src/devices/stm32/can.su
index efcce93..05517e6 100644
--- a/Debug/Libs/sta-core/src/devices/stm32/can.su
+++ b/Debug/Libs/sta-core/src/devices/stm32/can.su
@@ -1,17 +1,17 @@
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/bus/can/controller.hpp:27:11:constexpr sta::CanController::CanController()	16	static
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/bus/can/controller.hpp:27:11:constexpr sta::CanController::CanController()	16	static
 ../Libs/sta-core/src/devices/stm32/can.cpp:10:5:sta::STM32CanController::STM32CanController(CAN_HandleTypeDef*)	16	static
 ../Libs/sta-core/src/devices/stm32/can.cpp:17:10:void sta::STM32CanController::enableRxInterrupts()	16	static
 ../Libs/sta-core/src/devices/stm32/can.cpp:25:10:void sta::STM32CanController::start()	16	static
 ../Libs/sta-core/src/devices/stm32/can.cpp:30:10:void sta::STM32CanController::stop()	16	static
 ../Libs/sta-core/src/devices/stm32/can.cpp:36:10:virtual bool sta::STM32CanController::sendFrame(const sta::CanTxHeader&, const uint8_t*)	56	static
-../Libs/sta-core/src/devices/stm32/can.cpp:60:10:virtual bool sta::STM32CanController::receiveFrame(uint8_t, sta::CanRxHeader*, uint8_t*)	56	static
-../Libs/sta-core/src/devices/stm32/can.cpp:91:14:virtual uint32_t sta::STM32CanController::getRxFifoFlags()	24	static
-../Libs/sta-core/src/devices/stm32/can.cpp:99:10:virtual void sta::STM32CanController::configureFilter(uint8_t, const sta::CanFilter&, bool)	32	static
-../Libs/sta-core/src/devices/stm32/can.cpp:124:10:virtual void sta::STM32CanController::enableFilter(uint8_t)	24	static
-../Libs/sta-core/src/devices/stm32/can.cpp:133:10:virtual void sta::STM32CanController::disableFilter(uint8_t)	24	static
-../Libs/sta-core/src/devices/stm32/can.cpp:142:10:virtual void sta::STM32CanController::clearFilters()	24	static
-../Libs/sta-core/src/devices/stm32/can.cpp:158:10:void sta::STM32CanController::initFilters()	24	static
-../Libs/sta-core/src/devices/stm32/can.cpp:172:23:virtual sta::CanPendingRxFifos sta::STM32CanController::getPendingRxFifos()	16	static
-../Libs/sta-core/src/devices/stm32/can.cpp:182:13:virtual uint8_t sta::STM32CanController::maxFilterCount() const	16	static
-../Libs/sta-core/src/devices/stm32/can.cpp:186:13:virtual uint8_t sta::STM32CanController::maxFifoCount() const	16	static
-../Libs/sta-core/src/devices/stm32/can.cpp:190:13:virtual uint8_t sta::STM32CanController::maxPayloadSize() const	16	static
+../Libs/sta-core/src/devices/stm32/can.cpp:61:10:virtual bool sta::STM32CanController::receiveFrame(uint8_t, sta::CanRxHeader*, uint8_t*)	56	static
+../Libs/sta-core/src/devices/stm32/can.cpp:92:14:virtual uint32_t sta::STM32CanController::getRxFifoFlags()	24	static
+../Libs/sta-core/src/devices/stm32/can.cpp:100:10:virtual void sta::STM32CanController::configureFilter(uint8_t, const sta::CanFilter&, bool)	32	static
+../Libs/sta-core/src/devices/stm32/can.cpp:125:10:virtual void sta::STM32CanController::enableFilter(uint8_t)	24	static
+../Libs/sta-core/src/devices/stm32/can.cpp:134:10:virtual void sta::STM32CanController::disableFilter(uint8_t)	24	static
+../Libs/sta-core/src/devices/stm32/can.cpp:143:10:virtual void sta::STM32CanController::clearFilters()	24	static
+../Libs/sta-core/src/devices/stm32/can.cpp:159:10:void sta::STM32CanController::initFilters()	24	static
+../Libs/sta-core/src/devices/stm32/can.cpp:173:13:virtual uint8_t sta::STM32CanController::maxFilterCount() const	16	static
+../Libs/sta-core/src/devices/stm32/can.cpp:176:13:virtual uint8_t sta::STM32CanController::maxFifoCount() const	16	static
+../Libs/sta-core/src/devices/stm32/can.cpp:179:13:virtual uint8_t sta::STM32CanController::maxPayloadSize() const	16	static
+../Libs/sta-core/src/devices/stm32/can.cpp:184:23:virtual sta::CanPendingRxFifos sta::STM32CanController::getPendingRxFifos()	16	static
diff --git a/Debug/Libs/sta-core/src/devices/stm32/delay.d b/Debug/Libs/sta-core/src/devices/stm32/delay.d
index e97d7fd..192bd70 100644
--- a/Debug/Libs/sta-core/src/devices/stm32/delay.d
+++ b/Debug/Libs/sta-core/src/devices/stm32/delay.d
@@ -1,8 +1,8 @@
 Libs/sta-core/src/devices/stm32/delay.o: \
  ../Libs/sta-core/src/devices/stm32/delay.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/delay.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/delay.hpp \
  ../Core/Inc/sta/config.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
  ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
  ../Core/Inc/stm32f4xx_hal_conf.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
@@ -30,12 +30,12 @@ Libs/sta-core/src/devices/stm32/delay.o: \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/clocks.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/lang.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/delay.hpp:
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/clocks.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/lang.hpp
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/delay.hpp:
 ../Core/Inc/sta/config.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
 ../Core/Inc/main.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
 ../Core/Inc/stm32f4xx_hal_conf.h:
@@ -64,6 +64,6 @@ C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/clocks.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/lang.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/clocks.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/lang.hpp:
diff --git a/Debug/Libs/sta-core/src/devices/stm32/delay.o b/Debug/Libs/sta-core/src/devices/stm32/delay.o
index 48be05709e3445a1bcb77c69c1027f71cfae0b70..42c9c51e494777a7c353cb655fe72a9ef365807b 100644
GIT binary patch
delta 129474
zcmXV22UrzH*Jf|qdV9eVdrj;uc4Ie2V=u8AV@-^`L`}SiD4<{gMNkB!W1)yNK~z)}
zEFdV-q(~8Lh!s)ve-GdPJUlx)XU_YcGqbx>&dlZd#}VZpMjUD_d+~cz+XXTytgYOp
z&5aW(o6h@q_x-Zg)>XfVHjLXYxs9w#lkqk-HgbmB(1W*Ortal!Wc{1WCy`8P+99`L
zPTYiOVAHjYB6iCS&W4Fv#@fh!ZDLO%h4LpofRp_pn%wkgqlgXfE3;vSj8xjlRx}AE
z5vRPE4q)<Lh*mXCv^L6EucxdHGv<cEMz*)bj}S3kEhu+tNggq6Zm4Wzel5urX4+F5
z8<~GA@`2gn1^w8TWSogf7i?tlt;i~~^N`F&cB>_sW2%EV8(Dg*M7pmU1<stNjq=t*
zfGuj)XrJlS8l;s?$1*lHDur^@noTy$h9c2MR@H0{L~;eo*uv%2yxc}^GW<YP+Ww-A
zyoqrr-S6qEw2`+qPNDmu{RA6%d($6uKVv3iBkyY5Lig)l;l8KIneMaRf^&e;o9=tL
zcUH8sp8H#6BmdPj2*#Lx9XK2LH1n@?|ItZhqcAr~A<e&MiZ%*M(|dHE4+cf^rulR~
zeGGKIYgS43)>)9ZY5IolohAx4inh(Z(tXV`#zxVpsX&}Yt;|NzxtWFThu1>hr{yH7
zI8&@+Z4`Z5QH`0p7~BtS)hKtdk!%#hS~tp%4FzD_|KxX4c^k#g|C68JEVofiZPnPa
zKe;ziUhC=eoU!4ib!Tn(3^$n#SFLi8!#8h`+Xx#s{cgiH5d$C*cO1tnqY>Uji>j_n
zhhEMK8@Y~Wp=G0xo0ZCzN^dlJM^&Rlo~{s-troh^XWJNiw1QlcDOEAec)V0<rR5*@
zLu~Is2bRGTg+i{>DOLX}(C9|J($?!9o={6pX-S-in-+%uvAN5PN|SO0n!dS7X?gAb
zg>BZflY+I8|J3Av4*XBepJ}RWHq5;T*GlSi9?w7?!hEM}<={S-Tf=m4PviPCweAex
zley;Jo9}K-7F9M%n~4qzT-!gR``Bs*S1yetn-<7$?Q9ltoz-B2>&Q=})0|i0`tdPc
zR~!>?HLW9gSUiX8pQWU~xrDB^j&%JujM(~aqN|T6;rapJg3_jqbs7QUisZPSx=pJ0
z1Bg!S&Eh&nLk46cskFxcGM~fHy()#=vROd-#*4(z>^`9qTu7p^BUi2|d0bsrlYZnC
z(s@3D7&4j?HgG3tdLFZq7r|u&cqFIm!xyA_iJ>+a{|}k(>Ord4hLdDg0g?XfLKNR#
zk!D0L>7)%M3HK}A`(=^IHycR**Z0IftQ(c?38ni_ed+46ige!j$*f3XN0Z@sbBS(C
z9r;+{O0{3<LDxR7Nix=*V5^1_%qN~C%>&7;uZ_*VK7sBpY$WFfG}e;eL)Zh2&Ave*
zW???*)Z=wi+AKUs*F`0QjTJR3ZuB&R03jKq<kpgm&3HlAP#u-_{zN97yAo`%57C|S
zqPixxCi!n_LUpL2T8`^WPI&jD(%Nd0j5tI(+q{TB?J9AeY)A6V&fu}y9C}WG3x!nd
zbcqZM8bK0`qOmsf==%5|Jzf7q0<U>Nt#y74ne6uul`4NEhyH0x*ZO$U?ArKHl4cNF
z$06j3&2*~9x^mKg9YS))7vz@pLJa}J{-c6l&<`tZ_NP*T>IEr{9!_R9tf1@R*Ce^K
zkM0AFM3;Au^wT<$Lv?jzX09Je*3^<t8z0g++xS>5%L(i0N|Kg4sH($UN#btJCDkbx
zh+^h)a$=(!)gxgsx%IP>uCF&zy`M)@X_r1kQJYLII)@U)!wY0Mz9-%997sIucf>H8
zn%5?MH(lqir0b>O#1qpfAKB<=v*uQ!6TT-ib?M|gQ%&~~#pL7O#(I=~A)UarWd5{?
z%uGrnlOs=)=AB3?9o+cUxOkCUw=?NldXrq)-q<(vV2LfcEoly^Ciygsd*}oFSbG0&
z8_Dq0#wYh^3l+B=N&bdiC72LLUhn^fOm=)p=1q<D7F&@{>SQAN8bJ3M8|WI;fpj{Z
zr0e{9#1_7V9R1Co7)l$zh=1Qwt3Ss_i1)w3NUAT^kZM^FsV4nNs{MD9WMXe3t!Pe?
z{Ek#=Z%+;dEhUQ4U+DgeL_OM4OeT~zE;Yo~cL<>#HY5Ep>xrj4pXAq6q&cWjzcaO^
z)utm$M7oo7o&Ai=d>cviPW+A}eKQGmrG%R9p$C-?8bH(wzY+CyHPt?>HECXQrTbpF
zWGu9vO4~H{r*;yR*6_q|_g`x1;eN#5x{&UzgD@^BZC+xSMrRpGu(-K&pYWE7W24CA
z-LZ5X8bCyowvoKLH<`ICkbdb5lKf((>&zv@w$PET%cDqthk@h{m&p9jjgRu}XfnTC
zPOa6+dX$nOok(Q=7uD>`J~DqelqBt9N%DPTSJSkZOnPXD+Aoz#Z#JRQK52~(O{43B
z>7*0a=)~}=WOCL=(wXQ>*Plv>d396L@sA?AH=A22liY<o)fbYe&u6-SewM($i*z-q
zNM~L?wZS1DDm~#y_5R~I-Iv{^H^6x+X&RT3TYHX>eocSU$$v&V%biHaR!ODD#!>|~
zJ5lMlB!S-l-;2mQZ?^HZsvxDh*L2_EE}0zHi|Ep}Q~fMCB#&%-0}}OQa*Zz;P<AJs
zvL1AOKb_d7j-k5t|BX<-8%Q3}tC4djaa!h(WXYc@djE6Y5K(y$iRN!0*p3CH+Ao#B
z+L`3((FVHTGL4M&wx=50J4O2cZlE?x=}so6xzPPpdt!4uM?6bL63?OCjgB^cFD|#~
z{>yp7S{#A0+O!->q&p+YK&ydtou?(GgCTV7Hn9<Kl?-HI3XGSroXo$rkmj2OL=^hD
z(cRs2J=i!)*szdl`5Wevn4YYm7EO9bsH=_r<Hah%21F32Rh2{(RTmopSyb25WGXIB
zAj2PhNG|_IM9*u;fU|*WdGKc<U1~@AM>hY@71BRBk@WwIBK^{XbRYbQuFsm1ro&2d
zVw#3D6Xp}@mUR*pEZ;<Q;bx*<i)90b*PSF8ew@I!u;M|V_%q3!urR=r?nrV);{fC5
zNNyEPC!ROCjSd|qGYKgqzdW7piw4uxe-~kY+)MHatBE1q!AjI?8+*5XGOQ+Smi8ve
zp#F6K&aA-o$}SGqK6r8}oBRZFYtS({?z>?Hqq50t$>Q2?2GuDljGFXQAn6bPi41ft
zr`8Q`d>dvwmqFh24OQ}S2{{qLaaM?e8G_~5lj{1<WZ<_JbWO65>ar$8y{ajhnXrcH
zF|j>q`m%KG`$Pr#(^}I1u7d89#**fP#pL3ZDde<rG&y?wXDU4#PAz2n5d*wUB4$(g
z{yPVf>X|?2d2GKz24*!*sv4S7bL~K1hSIK7n?sWc+_o28J7c1T7OEvDX5rmd*$72M
zs-H|IulqN)&>b=v_K523HIQojN8{TtJBXMA7ouWTn;DI7{$CN)?B3}jmDnixRnc%n
z<FXSiqutHIHQj8QAsJ>3Q~Xb(l?@i3%C_~nXrm5~uEVA7*-5zXJ#{o_f2?T-{HSlO
zARjxm3dr9SWze5L@DVDqpn|&iWuKaH`2LrN-2q_T_8l;?{)hFr|7TP(uG{{j=HI#H
zcgXiJwF7}W$gJyw<Pg(>=GI=!%Wj|#V7}QRIm38R(?&D86R62Wrgw9wBr+owfGUXz
z4T1}om}xyhc9W^w0axxZ4$Eb*pTjIziNZ(BI_kE|8CUw6{bV8Z;)cpP%YnZj^Lzrf
z7+K3-Q5GvpI|e|U?Di4V;)+a?VN5NO^?if3DweJL9bS0J4U^%;aruL<@b`pVITFG^
zd2df}2FYLBz>8pc(0SfQWj!PRqdQ)YNco3tK-`npq`+W?{O@3JXUc0Fkb5B4KL`Gy
zyiXGB=E&ECLGy*YI1kRaDW)Dm?yO>KbErfp4weHDtvGfPWfv4a)J?=HP8tNT;jdL0
ztsmN1VX85orRXw*hUz>;Jl4|6QpJkxD0rnfOQTkeVtFNmyOiDhK<1=e>HgZ%+}dA`
z+IlMIK7_^zWv(-de3VQQ6w{RZ+JP%m`MMA4m#frX0M}z>d+ORsl`ZB&r9v5C4{xiL
zL&w0emr4$!rs}n_FV?zBH`R^35c;Tgn1BmZU7d|wh-#-1fOD$a#jqExDzc74VUp_j
zH?XCsqPrt^L*>>SU%@Sv@)zVvRKs6GwNhoE)yoT&H4^4)R2^i<eOAf-0ozwq>$_+M
z2R3akyg$VHY=w#k8$siZ7kg$aSiITuF<=Q|+jXYbfE6CV-Whhycq?e4*td>Qy}-tX
zLnn=Wv;*evu=lq@Cxe~+3T(OT51XM`z*c2KvxuFEc!;u;&ANuNayGOp+UY49ZwvEp
zS;I4^d|)G{0PuyqUyqzU=R|X=J)BE3<ea#M3gq^4!-8xuULW9g4Tk$ixR5UJG=UrY
zFA8sPJHLackGQ&@VJV+`N>8MWdr5soHFtbHXll4|JCS?C<<X-0J=bz04Ayad&jR<A
z>r@HXcJU`{kaOVI{D3k?{xZT8N_T!~7%CXXU+IAHN_m#=unr~?`S6P<yvi$HK=nGW
z`War_<wu``Y9>EH4PiE)JsmYH<ojHN!3zH0-7x>0Ut)k}Ew7u7<Q@O1I~@JUpQGhS
zJ%3^is2liA6#&=?S)EbO-NHpL2=@x-qad^vibqSJ`b1p2hDb&B01B(bgG-_MTzuIZ
zwRj~ii$GE<X3c>4-BRvYSlTD88;j;TCPh(ie?mHt0D!MFTnCi^>1!Uy&Po%%K{Hb7
zI06<fNOLEnF7eWpQ2-=L+&TbKtkMvgeBF|o=K`21X%InD=1B|N0$(hd{Gjth8ca)x
z3aJ~-CaR<!uaR?7mk20xQQz$V(nIPTcU1d``p=C>Jk@S3VbEK>_bAGu)EWwdTu|pC
z(xZ%1YkQz6uc=k%QKf3N^`HI7zE`)W<<MvKqPuW-k7iXHxag!wOMp*@HM8wha0<hN
z!aW%DO1qC322{6?K!=^k|9@AY=rR;;sp@_L0juu=Hcpue34e9x|Io@dMXTUP=erp9
zRlAu@6!>sptXnXhQ8_VhZo(aBCbAdC+I`I58W`Nqtn7{v$cGt6E#=E-UO?p|bNFXC
z)xb=orO+PP!G+M=CtLm-oH;5BqiMgFEG`l`U)d%%cpD*Gz8<*CvgWS9-IlqixW>vT
zwaj+Nt<Bb~gI1fSi$T{T-4SI&pK#EeKCd5I`|lq%;_AZOYzh~Gnb|9$o5b|?L?!Pr
z6%R2?zGL*!|K9|{++|?Yy~I>U)uk{C)$AICDUhn$Ks$6x-KXQtlJ%hArmANPtUy$~
zR+cfCFZ51tgLdlE>n)t_+xaXWM?cea`0?YN+wh}5ABBb*(BuZL1LXstIp_mT)JHXS
zLFq4<;c#qP9L<ClD1Ly>%HL;!XZ`7JDE()!0rFi;h!-m7#5C*zw>xu`dcb4MbS*Ue
zt&B`UdXAB`gEW>&#QUd;XBxdvU>e=O$Ta$&$TU_UiD|6CC5F6Kr7(>(xyGO>Foi#%
zF9&1hxn*dIro*1&+T1n;Ubl(42Twb^LQ^O^-D!<>>~`@t2H$_L9`1nknT2Sia^MkP
z6bx0-WBlnSinNUu>7^MTK;eK%rAAb3dJ;u4$&~GaN>H|NrEaTTI88ji4|B)0-+wf?
z|J36q<l~(w$TB^X;#PLdJz6#HVtNIG$DZ+AO!hsQZ4DsD=<f{Ijx!lFclBpx?*&Hy
z^Lqn;flL<7`@)%D2^hg_!%MG>WPWP`m3ZdcGr$v=HZjn=$V?jntJj$qdjPn>gx`jT
zsf;2GRe8WHqVeG&b1oZR<S<tT0B)^hWCwtF%9K_>wTcP<9;zQ0Sr+ggnWueWu#WlT
z6oh+aF3q9oC|l2f#z~gi140j(Eh6E{V=|*3*gR#M%HVylY*`%0LS(V~Q5Gs2HUqd=
zS?F%4#L3$K2Y9?}$1PY$waWga$mC7gV|r{EGCvBRK9a5K1>s|vGd;5+*;2wkk+r#t
zYFEmpd_?ZKY`YH4^+7gwGb&>z*U*@?M}ECE050-)e`vbO4`ZgN^prb2g<UWCUmc(s
zD0kfp%^>-z*+`<~)@P4k>Ac)|1xT;TQx*fCBCk{af1lCx@OB6~Vku;!{GoC7IBFkF
zDP}B;0&J$Y1Us`F-Ecp9a|r7C+n=*xa*k6U$medOh0Grv_Tqj8Lm`TFlWAeFb%qQN
z%zAqO^mkhs*D-L*h1rve#DnRTO|8l3KcS608HY;bycpIE$#KT~0(>W!d8^^lN#^2L
zSoL9?MxY+POhEwPeoW5=Fm{S5r0(CJnZ5|F1~7IMXb5D!7a<H{CTn3mnDL~UP6%UN
zNKune=IcDLg)wPkz<rvzycmcx%&q-+`e&Kyr{F%vETBbyII}Vdq!CO}B7~95{T9eY
zG1D+JSDt6qZvifvnW9G71?I{TP{%O;RKjj7GspyC9P`~hdiu;@e~=|Giw2xW_9CNs
z0P~4VKqAa1F)`5)USfLF>O7fg9S73O%<6BTxx)NS%h;>T8TZK6CTkHH%3|z>!B93c
zY6V*N0b?5su7^z0LvZCVhtlC$9^<kQT=~qG>u|S#8A7YzLgpEb)uqe{4W3OIGt~^1
z3g)5*08g3RKfqGOM7M_U1rr(w+)E}>gx57pHGR#mnP{s9CTf`}TcP@f87iRgEmQXi
z!gtJ}d&s?Ku1!bT2j<osAU-mWzadx0ME8QD^-Rb|aDQfI)}dlwn9a9Q_Kg`$&vTco
zfue5qvV$J*aKG$L)Bm5~cGS^ov+t%~09kX{N|Cd*Q*Of2I(`w%uAgni{f4Sx*gl~i
zs_oxBpwVNqD_XFpPdu)@oPUJ8_la&W*5?hqtbU9fvHnK&*5Tt|u3ght$hHsd0}ndn
zIsE^ZFp|Y0RXHl>3|_F&KVHTCILTU#WW@(8DH`F;{@Vx(-+$TyPr7>7;M!yTP+WVD
zX#<6R8!1XXAOtHp<zSmtkPM5ghqohI&qiyEPPB*S#8bAo&WLk|e0~AV<d^Q1p*>bl
zo&=q>h3~<zp@f!SiK>SSRhT>`sU8Nw=p|LRNhrIn`jfunbk$HjP+6+0&M=mz`bP8k
zJ8bd}Xuf4n4u;AuUdsS*n72%V<^|2*OAsb%3?l3w){U5o+!0+|;{W&b;Y=qLDDs#o
zfk+-RFS<jmh_Mc!SFMyeP3yKNOrIb$b{P{Nf#irRuL{<V${dqXmt(S+W?=M`HA_Hp
zT(+SLa3^F3X_j?TW=m6KA6Z!eSo~zu=OA}V_U<Ay17yN9R6I}?dK_NH$Pz9giIuhP
z1kL-hDC=psktH(~!o&mFZyu=ZL)rBl03XR>X-6bi<~Iy%`Lc@?qAZZ9X+P(&EbcrW
zbCK-BBWRY$`p}%MRHmYRkusUd3eIv_4TY5}WjAFo|5P?*CWO_p?7u<wOjfSI_wqs(
z)C+sJ%9pZE7r<>NZ(@(aUGn?INOsHZu!XF2kdIpe{9d{21DtV`kEH-hsQjEQgkf?M
zJ*q7EU|K_D%d0G4c__bKjmFE7k4%6tSN<=}P4nc6wQ#0D-o6i#LV4@IkQB*BEu+Ol
zv3&Gh&^(dHuSFx2$rob_QduECJQl!8d52W6RmrnoB3CW%NuS7bc`D7jUda29`B(Cx
z6vnQRPf#MMm7l`qtMZLJl6Fkq$v0Do@4ftE2y!3gGe4nbb@E6GMApl<R@36)vwT<y
zqz&>CBUHc2Sz7P!QaD^jeeD&$ZH91<Vwnl8zE_bS1cOcr0XyAFXT|4#P>cPFD@icu
zqWGSM>jR2sv|2f+m|PCrVa2V}&~#J$aS-N@DBe<h{-{D6jk05k*Zq-LJr#8nEIy$q
zx&<9?MUN~Xd=#H^;f1eaHC5)6V)T2I`7636fjdYs<S@JlRw%BczM+Z^hftX?Ma(_`
z&L~PJ0dQ8aX&`dpiYskE9id3^1!t7v2DZAD=M}1v5MEFeeL$6BtctZ&K*THTR>7MD
z#nL&@NmM*M2YixZ+%V`QD;Bnf%4LNM#Rab_en2=!nW7kfAAsu$-UKghD4NnL=cdB7
z5W-uE;!J3!D=O#0(rv{(ihJBuOdk)Gdy2s~K$fX!GZHNK6;`b$bg~t-&!F=_A<IJz
za}+w-mU*NIZUsc1;;J8#e1#?q!a~Ih+Jk$nsPP0%v0|+TNr_@1MFq<gUS(h@S4{Lo
zQmM%L31v?e)sJDJT5+6KsLvE(uaUe|OzZ_iuN3dCIEA2mt+4+NEmW(Ry9eBF6?y@=
zcM4rG%04K{0)hCb$aetSC&i3uD63Zt&I0Kd#Zg*6HYhs9L&Z*6PzU%f<>zYPb}I{)
zp%EOEJjKcODpOaZDIJyfo58NLQq>Z;eae%f6*Ml&1s15fD#gEH;-K>WGnhD}wEY7>
zH|6m85V|X0q(a3*Id>9F98=cT!=RUP2#t)#l^+*^+gn-J2bw39>jDAyReD@Q1N$k3
zQBd($-l0%%fHIcaH%R%b31)+p_OWt&e__f;(_!hf(wl;aXO-u}p?Xf)i2|n)%5(};
zMk<%m#}TdE_X*q=luc=F7^|HB9(LoDJ8EG!L8+u2yNk-3(_uGB$<qV9q})lNi_1z2
z#cQr8W5OYPq)higE?3zbQw6KCKzVrrfQ8D!diYkPoH`AK#mZrc5SA)SgMojd45yvi
za^-wE{H{>0u7%1|WkXLmQ>E-$21o5wH}a9}Qf;0H;ck`34*2Atx=KOVy{bh&0pO?-
zDJ<cvdUOwl_Ni`70JYUswTZSg4yabqrov%W>`F-8RIeH!JgRy@OBxT=%%kwzQ<YJU
zcJfkLahOASLUn=mUA$E*9>H#=YQiYw?yFj_f#w6%&orTbsIp&!vPUXr5CFNV{il%2
zS6#XVmIBqgQP6yBRW0j}Y>{gEL^xccYS1B9s%l5k`ZCp^*6^uZwTME@m8$OJK>AeW
zLqU>iRl8`k#WPjB9dIvH@qa+`rD}XSEWK6@Xaeq9RfkJpd8e9uAGr6bR@b3fr}||V
zy!fQ*_8DbgRMxF~QNspRf`9?xo9Zvx0kC8D%aPc#+h3z>H`|6oE}Y#!!U%Th2bhRr
z|CkLE=h;J1V7tHuC!>L5*o(Bs9mj4dMJ}GbE5YtX_Bl;`6WM$1A-u%iFF`JuUH2Qx
zuCRlx6vDmA{!I(DYwWjq(7Dd8qg~EaHun>RH`$J~36;j017J6uZF&Y}ci2g^0dSYC
z9tMLM>^gc{nQVOsRI=C*nvQ3)_4Fb>WcLg}lEYrv59(aD_BnEStgRA_SHKqODA-@f
zcA<q#5$lUnP0C{SmqqZclueogyHD5!4KP^2zVJq_k~PPIrkY)zLygbcQP}Dw%TI;y
z6&p+;k6QNdWq9$1P3?)~J$sgd`ybe$6QJ^mZBJ3UdNz^Xzy{V%q{9whS@nE0q8*op
z<3Y+@Tua(;-Oa^6gQpJM!w9JE<vdc5IC68p2i}>R`~;TvaXqO{E?n=!z`1g3o*+5M
zeWHU5hq#!XfV*)q=K*l%*c(WWa#J1PlLt3G6F#MIuYRG;u4~-qiKu-lx84cTo7@}P
zhfC+aqdlVA+=@rAbeF691k!ulKn)CLawAqic%O?L4Yq79eH)&^18&?LB#*e`UclvY
z&uJGppNqw*C}jcn*d6AJI5Pz>i@7v9`|*TR(loMP8E2sHzJhcAgu+U$$x+~|xOB{a
z5hV<u$;WeUEJb}^aEX`U;VZ7qbobJ(M(e#V$i3t4&}Q*_E_y5gb=+@W)Xv-lio|{9
zMqWei3%9!~;NQ5awMguEmnqP+=i_f7x0~NipWz;U7Pa<XzTI6UPP{vX44wI||H1lx
zK8Mb7xbXkHhi3=)4Q_xR<X2i3LG>`d!x33Geup0_ag^^#vqBHvoB_L@yz^P8c=7(U
z%J$|{XuLkj_dE`vAMZnZ52yH7?@$)N5Ac8&fqZH%+z#f`CV(Y`FQS!07+?4fxzoJg
za6Ff@{A`+)o#PL-q)A=`zfuN#BtMtl{Ahk(W0a7;wiw*8{Ni^=;`lL}P?;RwOr1y`
zzngZ?^Z6lpfEV&1*N{Bsm(7CRVm@I4$Vzx8GlXUQ&qIJK=kKJz?Mi;?f51KEd&~l7
zHGk<oy}8f$Z=)f7$&Vfkomc#>802dCqr31V-|*%Kz`x^tXao8^kKJyJqI@elVp7Lf
zk4M!$^OMQ^7v6p&s`i!dmk2Mu@js*hzDwBd4l;XTZvm(sgr$0v?GXZdg3M8PpGDg=
zPQt-t0QU)xN};-6c>Do6uEHNK&^aKipwlXcgh@1=J1h)wK$*MnGtFX;2+13O^AP%5
zkUJ)Pq*(HKVf0@RMhh>fgNhMW=b^b`g{Kr8j2Hgc0xuGTVf2Y43V;0wfHg@tg8-c}
zS<t(I=CV*Q2KcMO;N!5AB3!pe?z(WdBM>))>BFIUQ?SxL>Mg;m20o<=Zz!sGTi8Dv
zxqHHLieh94^>YEp5|TEfEL#Z8h47&uH$Wvv7|{=ga)tO7cm{b^;q+#hz>4ELs1^$I
zX`7{3IQcztC4$pM0G|j?dm||mhSDLC3SmFZT`Gmn^+>9OUUUGbTIl8r7HsCELij@X
z3p<j^S3)rDhSvz*^FdZC1jeE4jW93*uDug1I0vbGFIYXXlc=l{@?4O75~fZ;vwarY
zy#?tPp@F6ZUxmIOf%qo;*#yE};#XQv+lxb+!u{i7FIteC5Xb%k_(@T_4k|uk1C8Z=
z;;kX@;*@wa5#|HLOqx^%ijH(-AXqHrk%Wk+te2n@CjQwO+0)_*S{R%aFVkA-oXC{I
zQiM2?mSd6P(;AeW7xzf86fKs}0iqbuWdc-U#YEani5EjsP~QY`_hUS!L@_TLNs`$0
z41|}(d&8l5Mchscw-m94f-ToXPk%Zlkt)VtLDSq6FOq7S==~?S)5WuD_<cwG`Y&>K
z#qFWUWr%m4AeSjlJPBvA#KUqV+2R#?_7BC|-hk(bj<pcxil+}CmnU}X3|xVjvj+`Z
zC~kU-niYv56x}Hn9itKURhEj2%HYitv1BW_%SFEv@Vi26N@2jK;(2<#s>JYKz&{g@
z(b<{jV$3}x4dTCNz_v$PvI2>l^oS;v?o#YYRP>1SXf(_pm5#ka;vwDQKz2-uq+pMy
z6m=H>FG-8tA}e+*yy!56w=~ceUYwM!Q_toj8EHS>S9(Iu_(=t{RdGu4Ymc12)ch7K
z1xeoD00@>kw1$UaQUUEvoR+3cgYb^j{wq}ON)mOi_oPSk0c1!&QZJh+-R+I!zI5~p
z5^I(;atG3EDU^T@q+zt%^iV3LJ)j)P6$e0-kEHvHP>T}jiW<UF>2D6RoN}q@9W+9f
zlwpEv)zTam!e>%vFKQsElEN)7B$o$BUP=a3yD>1*x`8$u+J1TmNV`8@p-rsqjaO0o
z4kkMB*>UeOxZA0rKMFcqM?mTOx=`@_@QNCv%aA+J=~_ptscx_0P}}YuYv5N8<2X3k
zvqlH~UNvLE(EDgUIQ#4*C;D!h093y&bD{s^fK-_8?<&Lnfbg@p4(wmL3v`3}=HNQG
znFP8a3*A6BG?8|Fe;Qki>+tXBwCISs8_*fqltOHy_PMv{YisQ^6bAm;Tm*ORnNidk
zyE0$8B6plIc89VrQ?vy5KxXeQ2*a4&^uWRyuOjw;&9RSNdKPN?*&OOLU09Di*l}h3
zXtr>G4Wp6nAZrOl*&#NLq9KRbE3_fu#+J}z!|KkCqcy-0b}$9NkFs`7kb1DuO`&>>
z-SZlWC;O8xjGkZ*(yG~;mGyzpmo23^njhOqf#ekHOEvaq57R0=h`mXjNH9Bxw%bEk
ziMFOgS&??!!r0b>kep^eP(1aFl?_@8yJy*%EkSyY<rPT6+07J-j9^bw{4SDB+5}+~
zYY>q;&z7%563r%YFmZuRqzG&b8$g?DvFv=BSj4gZpCOEApV4TPz&@qO+C}!@0XUP$
z`i8>aBzDgU_;iW2{(TLF$?UGLNG`LFZ$g^FcBO{8#*S(NPp`9uG;6=XE*=G8Dm!o#
zOx$Fz1jFrH>|_=#o5rdmfV<6(oB<Pe*k}Kn5@#2o>>lgT8}JNvQ~_|A>{Of>SKen&
z&xU3e+r>&J8XvNHBF$kdpMdlcJBiNH<+2VxK{b!<&>l%X`_m9;7O-`HqV|Po3y?l$
zw~+ZFc3l;cVs_boXwnk4bOf9!Wh1+R<q3O~o_!g+s~jxl>^T>dRj_sQQL{=muDum@
zpR&7XkyFKXB)iqDAp>oRl`l@*E1$D%De(S+{WcP1FWIxrkbA}YJcaohw)Y7nuh}K{
zL0ZeQ_DJ5a*M`80w`^KFIQouldknbu?6EsA_<?Qp3Br$T8pSZ{*}QU!I(=qKsW1A<
zPQC~3Z|og94Q0p8Zd}51Q)uAY!*wMSj$Ao@4uLK2-$jt_<2o$^&3>*yff~ASr_ZCz
zm6K>Q;Q;4BO>&Ss{{*>1obO-YJj}^xO6<lBrJ>QCn^9(izVisTo?fA&oX2Xg9pjn@
z!JsD>SdN?*mvs-8PH_Qikoa?#Pr%UtZUoJ>0y)1jG*A%tC-r^7oW2vi>s%^2DP<_P
ztsPjxxFU-0pXRzz?CT6S<raK8%N?Z?=;yeB%>lQDb5R?h6Tw|>0cj++mv)z;xXO(%
zah|KEX>&B!f|~RK*WM1KF<dsSBx1Sd6jhAlDq4Uvo?A>IzXWb*ILu$<Zque#BG-2s
zgh|}$et=)%yt4sF=F%>K<ud0&@xv=t?)7zKuX0;IKsALsLZ_myam}4kc%9RZfitPx
zQ93Sllj}bjDz~_{^dhHm3lQkW>f~37a^L1Ws_|9b;eMxB-(4=G00!@IAFE(6gZqPy
zerIy549R_N%|uiwi<?S2JlUKzgSy`b+^Y$&`;eR00Z9%wi;f07;+$v=kjs7j0PZ}_
zWe<{kZVDY3EZ`2T09zsVksjq^uHs(^i@0I?;Ak-yWQO??E<F&!QtmJvmV3gTp_oh=
zS3%K?a;}*jG%L8~Ry9;BxeheHdCCnBhiVnqy$e*UIqoK$dB$B&ho$En-w|amxNO?*
zd&!N>huv4)uhg<NT=W;fUvr;m?orFNP6gl%H-9;VZ@Hfzqn+My#lJ)IJ*S`^!k%a8
zT--5!)nQsY9Ou_6VekYWL3_d8{B|XV!IONeRbcbsJ9h-$mv{39-jDx*0!*j)ihls`
z=XJE*8^F8L@E6EGqt#px-<l4K1@oQ$LK4C!Z3jG*A533k7{8i&_tSjAQMh)7@78$4
zGn_9DfldTJi?-$?`87VsMe(-u%Ae;e+rn-%Zx@2x1%A0F494(V=7J`cKSmp(aeNki
z+wuGa3N<G1%c-Nd$oKjN4-<J=AHb9N8k)&m;>%aVr(`}a0?B25%u9+oUEzIy0nJsu
z9}Ng8{HQpnUgPtpAi2&fDW-FSe?$XwD&GTJiOQRN^>Aq3;``G<oix6p4VomKFHgbS
zd7D2+z3m-7n8xb6e8X92-sAtI9iI%|LV?muzBUdX-sgJ^!IQLR@jtEtcQ*gSA+SB*
zm)wGhhx{`asOIn+qmg^WFYN=;Twc`!nt8m1wy5&?!5cwS!2dcA!a}~=QPk-%?@ARd
z;+NAjqnPiU1I-eC=Pcw(`2cVDRL)<X4YCT}Ox;GMmGAi+I#2mdRNpGTbv$UQ`2o|R
z^Ni1?<5AD~m>4+of`3kDCSLN}X`|y6-)RtVHT>C7B#5NSpi;|Uyo@@%;oqb}^DV!s
z84SMTn^htAp6^Lx>Ic3p&51tpA?*OD<E<;EK<5*`><2VrJwL83y!g!Dpb+#I-fJ?N
zq=9dh1N>Lsw<Ron<6Y*#yq&O_)_=Q%q23_17fzppaJMkyHB=k~+Ylssgw!+O+$;Ff
zF9#fjt^Uw-5{^Zq+Rnm-%P_l72)Dk4rTv0SB=9c6?5*(4RY>!M!2`k;+7&%0jG;i@
zAt7J|fQJP~+P8KS)+~gkyKpZWDjq@?J6Jj<=ntdJQ?UITIWM8;0g~gwn3-_qgiuGE
z-a>{2_D%{;9!PwI_Y19%`U(Zq+<wBRaloGvUad#YU-)nyCIW=zeLxc^gwmoRNa#Ku
z)eaUG{RF!q!g%`iO{lPHB648@{a#LaTBxBp{23u<7~DQ9s0Sl=PVk`p&~V|xS_mVA
z{Hef23R`dT82_S#d;I}CFX(9n6D<s(Y0d?q6&;<55oS(-hq1z4ia5pzQ52qz7n-`l
zV1nSL1lvWS-4+NFh1Gb=l}W;cIJkXD_&ou_WZ^$L>UCL|Mmy$L1T(FAuL_>4z?mYf
z#o7*0Ct)VVg0BlrX{+squ+kouQib;P<=hm8)g!qjxQ4-*G$AGoxpX1^dziQ_7<R$L
zJz*QYff+*YXDG`QhHpbV-4}M=0cV!*@6XW87V>Oi_kpmUwmlvSA-QlgM{qs@d)7xn
z2MN+#A<YP2p0H>Pr1?Vc5+nseW_!>S3JYlA_gJW<Kv9vf;WqHaLcurGqC|MH4JxI=
zl7lFFBD7VbqGiI?9jHXPkU-}dDuk-5(5w_Z6wrJsc>E4{m7qz0O0`v}{{e;1gz2%!
zJ{Q)}d4Lx}iX-auQW#IiB3=pndgN*Z&vi&%3p1kOXsvLU4#mC^TF^<~x5An3(0nK8
z=rejR9Ho;JAA~{uVg94=fqo!VC*+d%pM=5G1=kC93jz2nSpO+O;TOScBcu(2e=~UT
zRk%iB%x^-*JhY6R_#c_rC0h0)XD|Lh%g5c~O6qhS#N2y;?-9S!P_<XQauIeN#Tbf-
zI*DP|0dN*YI-}ttX8#3%tLQclxdY-eii8~&<yM+rxru+%!p&W5px)L)T(KEC$HWd(
z;jpK;gr4XL@n`x4iMRNIew%PoEOSNTCmvc16Q{%$^qVt(v4oB_28mNMkqZ`sMVJT?
z2bo~^w7818lr!S&+aNnDX4S#MIngthc3r~7?<wLKA>N@iM5Ng15}b(=Z&D2FytrXI
zXrjfwfzZ4l2A%^=jJSL^l33A7p`AE!;wU&1FDB4o#RPE@?bcir-;|;(QQW|QGf7-V
z=Ls%}e_n;%WU*Hj+`cTXREYTgu87QBAg+q5Izlx?>>h~1YobKEp4Y|6bkO>SXh$1D
zsbcC`cyUu4-xn=&OPo!+d1>OOc`%<YHm4}vZBaE9xI5w`>elayTT4NGPkc<Xx(xBj
zCy-@|7yf~x+2YR8H2-`cMvj8?p*Wq+VdjY2y<zE**!)+}<cc*i;Pb>E9DvUkS3Lo+
zK$O$>S12|g34@QtW3Fh6A~Dqjm141>26hoR>jAP-u~#hsPsHZ?;cuB(R|d^;@$oR=
z5S*YOx3yAS90j(g;z&I#Rf!|$%uKbo?<5e<#E$3S#dEQZ8D%fT>wX}8DM}9@d?f~+
z0j@@TTL$54(VkA;)r$LQp8iIhM}z5G@jx>ed?%VI?)hHaOp~k+;?K(g|0p^hKv|tt
zeAEpteiBuVK-7y1X@2xsyo?QD<ri^$K2#gT=E=Z+75mY)|2Of#9pvn!T8c&Ol1`2X
zz+U?D1!a4rE-Y|+rC)gn9i=Yxn4F{?TLEyE<`u!weUdN~D*L6&i=g5nSqIT!LszNk
zJY)|@P8@U&N&|bqnM2Yabmr!;bbm9r-K6z2yK|SO{|Uem=`e@fQRyCz4I(zP`8}LD
zCKdZ4@st+yfn6`@jyqV6OOd}octSe#9RS`^+B*nON<C=y?IYD#>AmumwjF^9KdHMK
z=1)mkqtJ-{QpIxU1i%Xj1EuXFpb{k2e}gbsa@&Afgh-?4cyOq6Y8wDyQVoTKPfNp_
z!>2P+I!(gQN-b&o@0^rP%eZjqUKCU!r04|@MoNR5()br8InXljyfpj=I1?@TQ#k*E
zG*b`KIH_-M<l?3IdXOeaGv0&rqI4}8Nuu-<MW&LZ*Y;q!Bn1uyOS0q|f#kBZ>Mh8w
zNQ>!L5mzPq1U$(UX|^N0xF$uMLfLhxayb3O?uKL=1VpN|wjYw4(!{<%+>-3mU_MRy
zho)EQQd~FqeOt<=RoxwFFmd0NT;@UZo>X9j`3&hAEf_PUg41yHzNBpd*RrJbv|7lP
zuDiqE2U6L2z#mErcmQ&wVYg}5<&l(k4mHe`MvaHTJZaql=;TW$9zv%;dN%_}k>nQ)
zzl){Gb<ix4Vm2WulfqWRe7W?T)+`lLJoRi<Qf3r{)slS_aL=SoG`78z4)1_#ucRIK
zfvb`JqwTOalH&r{v%Zyl8utdJCFl*5?<H^QwmwKt49I<y!eilny)>UT{60$u{{YPw
z$)y`q8l>-7So$h4G!gqIHK^c)oq89Af_JG4Q;@S)ccM>wxBAl+*mY1J?*RB7b-XJ8
zd)15zLPx9GiTW!ib<#&Po3pz2dywu^w@{;SzuKQpQM#zR(r>_A)hj4keL!9PJ@5zB
zz3CLzA$2+RmWS0#YXERl=TnryUEOXdRF0@ytU+>AebECr4|Rq;SdOV1Vv+MyU!ot{
zd8w_HpU_ap)o*=(KcQZ72|C{D99n>#R1Zyp&_~^C6g>1*|AU`IDE-vM^yQpVN77Qy
zUmZ^S!2#+D3Xcb>FVGHDkh<$oa0jcqw}giwY7aUQ8md;PkPB09SPA%Pb!{p%&!{h3
zM?rd4J(ZrtIrYjPQ5dd%z6eQ#x~3AO=he??QX8$l)fqlrP(PvYcAR<!?Qq1aJCRQb
z>Kf`aFRG{0Vlq+P^$s+X)TT^OUsCrNg0f__OFwvVSv}tj+!eLQUT|JjU$vnRFGc+u
z{^<dZad*%lcU_%K25+dl(yA;~z3@DMH`URDk=#<hj6{;AZk+}|y7~!)qHn9eqdwt|
zy2p>ObXV;|<K{i}Vmh;yq5g3h$THO~H$iq^?c4=EWvTo02QFLv^e5UodZ3<{hQfzx
z&x26SQSUp5r}jv_{tRex)f}~Dfx5FJxC_<ot^xR19YWh_MQX=Z5EiRvEQV%@`q3>U
zW$IPb8I-G6H->H16?F9VmD+PZ+Nnm}hJ>%xeQ6l0Ro}{|BfD?ZKhu`zTeV2%P~NGX
zzd+}`I_onU@q_wOd(`5i`k@`Xs8eg30{BTCMq!wGb(8JLeO3>rMb;Pf0xOaR^%DA3
z%U89r9A)3sBb3P5Y35L`w@cG^4-DCB&d!E2yESeUSG785j?-wmM{}E&;(Il^Wk?(~
z<zc9rlO|dR_nkG{ir~dQP0>LJT{KPFfyPzC3<T)`O`BRY-a$>T<xn}K@t_a>uqJFA
z%G@;XXv@o8WAi7RIilIP2+kbUY@-N-hvs2hkR7vXc8r5TPt6dTZg^=rIzxI~Q$X&Y
z&}?i28gI?wG~`ZdM$qKnN7GFJsjtSB&S?2*YUzi3r!@17$oXq_(w82f+1d(#Kus%}
z+y!ZtP68lUlT8tqFpZYZEuYqm@kb@jXsn-K!Kt&FRjr_NPBZ3vAi_0z>R%%?A0m*8
z)O4n4PL$>W9ilt0S=<d?L~DACNA7|~M!y}5(b#;17qOZ%G*gY!7>5BKukr2$VS?rt
z+TFUSSxgaxL`^U1r;;>pPXm5QGu29iYO-cA#lkLYoc+OeMWfq+<f<l#V)7}Px78@S
zrqN{}cU`k30Y2T(j64W@s^$nSBX4T_8&I`dnqU*k(lq{&sA0N>9S*>4%^iA=?`VQ%
zLwHwniuU&IX^wh=Gegs%y%nBjY6^HbbzgHX8md_uy#qYW)-)dj;RDT+0}wvc%%c-4
zIU2V+06x;VQ6wQ(^OjB><ZF6)z>5OSIXX{OsOdxdhL1G~bOydiQ%%wJVolUf5SD1h
z6+^RBGlb4dKhb0kqVcaxvwk-WmTUa+YX)V7CXv>{Pc^+7w?;H;I>F&;jW8LAXPOu_
z@Xs~>H3i^><~BtqUTP{Re)&rCJ^h}bM&sWV@YkA33K!REo>I%a(G*&cd#@>^!T5t_
z42@AAH9w)us;tv=@POS<n!R+Epk6bB&a{2jw4MULzi7Tqgx?LC$ipE0s`+yXYX41>
z8H&VCdyHCbw|2<@;2gB!bY5nUcJNbJ+N*tPi^NfTS^@8!w6^pjIcu*{<Zz#M{@)Pp
z*Qz@}#p<FxP5+v~Rl76=ItR3Mui@KaZ9Rn$+_W98!V7n8_B!}<L_3v!fpApo*$LJ5
z(6-Kk@R;`WW2ks)zb=IrUfMbFNRDd{*uc^Wtsg~2ytS(-NO4lz(hCNCw9Q_@p0Czt
zKg#^9TIE*QJ*6%Cf`;<fzNd9qfOfYZECp&4=xqtomaqT@Yb!=VB}6+s6u?kz3pzs-
zrj7j>ny0mMP9Zs?wWkI;t1X^@N}SU&u}}%uzNL1G&_2*27pZ-70v4jQt8_4XUTb~U
z8->x@=EqT)3))p*;C_tuUz!KTYWIagCr;}`uSdMLE(+!ow9D3m=Azaz2d*Xl&!=SV
z7&;wwS^F;!;T7#lS_oa$ZdnUUDOv}b4qnr?9tf7}+E4f;t@4I;(i9j<)gH0_028;g
zujq_Pnl`61yhzu6q`l1B+A}YayQBRn7QnmO&GVs|p&d+z!ZNkKZb<HHclQA<OB>Y$
zY}wj03Wq$<`q6QnN7}a;a5PuDl~x;h+TlYW%-1@11)xCt?>cA}YP<erg^9=7?frl+
z(te`QRI&D>Cxj*1{}#j3Qf&_n%s<iQ6arDEee(uv<=RO~<SMk|=%`7hb{35XPqmwT
zz+I(n@I+a)wg>gu&$KeywtTL=`36;bp)KwR_)Be?AB3;8udQ_IxklTU{^`qWtp`Qf
zYqiJeC+8ouZ4Gedqc-U&%-3n3zku+Q_5?Lhy|#6Guzl9nI-~51cG+=MtwFnm!arZN
ze~$$BH|+xg*y$bz!L?nw7qsDFuajq^Y`5+j{U-$n-PsBoe1DF*mb934(pBJKhSFK5
zTZLqwZWsk+_Uoo{K)C4U(v-qgm&~9^59n@Ckm8_jCJn}Jx`Zik#$6Y@0m37?2_I1V
zqq@noJLaJadW+<k?n75_dg_7(K*dXU!X5UG>ktgb_jf|)m5f4fT{k+9byC;88l--@
zX0#h|O4m(<&|lX%8i)X0XX=Rqbr~^8f^>g%hBLvs84mC;L|0Goj8L6>Fbsz2eCZI|
zY2A09Av~kIFNaFFZcr7H2wh?ko<XE;#4=cjvg%rG0OGuE2z6W0y5SO<=7NsPKoX<7
z^#>e|)m==4YMgG_k5Gx%O-hB|3A##8lwH(yZ;2#Pm+%JMNxIY}@aeKH^(Jyxbjz=x
z)vxMaP_R8kcmFTsuIT~{Fn?X=wi#w`=&aj*19z(KTLcPk>YgZ}nyz!Dz0ljb>9iGe
zN9Xe!*zW4O)k1hrxArQ88M>#}0Lau8(<a${-L4g|o2C0m`<2<c5&6)3pqr`%^+Vm<
zYe;f++bEcmr<+{@m3-ZQEm4;O-Cx$8z!&N|?}3TOI%nFQE7I|;fhg8xH%CQFbgLTx
zEY&Td9i=C_$qMAkbcUUvsnmU@@%pLmNBYG_mCpJAfNI^#?kIbvTNw%J=el-0D*8e<
zjSj=S)OA0H+$&vuC)Be>*CxY?>}y@xe2~`amNy5@8(q#vROYSj$qsP8(=DXw)kocT
z6b7x+4W)J5C*AP{uvD*G6$kido%%Znzv$l5G^IfoLSy+?T~C?<ebenYjhwySgBB#a
z^+$I?#X;YN%<s{UZCwBD)t{lCK0E5YXbs?`|K$w|o%MVBA=#&&PE(ov`g?0p=A!>E
zA3|6C0$bz`=|>F(>0x~jdUkI5B>E|(yI!RM;D|n8GVC7JADst)hkiNjxF6HU+<}Ux
zeqj#aUV0vHu2p$lucxWd3H{JQ==kW@Xi(^@U%}uR`stg?k(|;qRVee<&v}hpfPNlr
zQ3UD_^*|D&zd`e{VEr$zfD6$N(4%ES_4~E>0K)WhuE5|~eRdjz=k&|Jp$)_JMKriX
z=+7O8Yt~5p0U9x*^z(dS;=DeK)*jLNJbU<bLI2htRg2S)p_7F1`mPkzNze~n1DcEa
z<Y&Mq>X&9fn4}+EjNB!C<!5jw>$}m6^RhmV4)I*k@B9zRRegy7l@xsn&5Lg6*DV1{
zs#U-I1=5>(_6JnvmVRD07);Y2--#q$9~FeM+xquI0KB8GZv)rv>K9Ff!F&4E-BG6u
zeFyq&c&0x4J7{L>_4I#D9_S-z!~dcFKO5N1(HHkX?vb7!j$E$Zi(aHW{S^vY=j*M{
z4}h&e|ApoRh5FCGqY)qL;}3zRNN?!~6Q%lcEu49x53&QkOn;EpVdeUk9>7)T57FuG
zO1*;-fT#Lo>iVnn)94USwf^822w&*C&q0&C)OV|eg;#oKnxxg}r~L?(*Lu$Cj%=--
zqu&6%(a$xY+1~0UI>Y`>??x-t_xeAYqwIrzADz?ts9#7mtk-{`Gf$uOM^>X{zUap}
z1J|IR{V&SC>W|C<_c#4c+5xjOw4ph~F2i<;c-k9Q&~x2w$f4iFI2gWbN{f~~hMhEd
zaW>e`1Ad>uoeuKvH*BEjzKemQ_sZ2E&<^JTLpQ4EVZ#%O1h^Rlnyt7S9@7tlju?8;
zk-DRXKd5K(Fg!|z@R;H65g_w4Sk^<+%doKr;KvQ-<uH4~FmoC0KX@Cw>B~83XtfGn
z_!wp_fN#Erw-kr;Gc3Obnp1|y6(IFD?52rpfZ=LOv~!?g&12+(3<?V52OCmosu*Gz
zvK_fl!*6sTDa;UX7r4`gX7nS_GloLihB#{&WQOpZVG8;(t1{eBOpE9U!{qq@MjG1B
zfNxQTY6`ZWH~3^Bi8d@;2>b<uYkN2vV~`nvk2Opk3qYK~_X+A0Z<sX_WeJA(5V(EO
zAkeZX(eTR_BuR#oJX9_j=Fn0r*>LWAkX<$`p~ac?iot`nIIbF`m9Ugz=sW{D*9?Et
zmfLkhC3Ouq49nX<m}+2u2lq`wm$As*GOXMI?leP8E5OqY_B#Q%ZCLUcWp@lV)R){f
z%u7Z)-7`4;3YHARkwdVMY1l%WDEAFT6c5a@8rsn+Dci7k2?`$=HnK4B(BSwINsdA7
z1K=aWruHbyHQe?EFwam(=L7Q%_o)*qFl?U=yM=~z^lxJx8z$4RU1S)-0bXqQJ^{HB
zLm^EgOAT$uL*<FVy9&56L+@E&DK}Uj*MhXdkkbW)m4>=_Af6gZh9URNu!)YcKR3)B
zkCuI5IPejqFAdkXBY9;wPEnv5!#$i_R=zgaWxzzOVFnA_8^e8?YQ8npcLmuy!)`xV
zcyHKu2L?YFo>FUnG~}E@1JxPwt#n-WlVS8C0P79Se8BeEu$D&gFNUk3&}lGSpsj|l
zhGH%3elyJYfcn}QKWXvsb{VrMT4rx7m;l^v<902|9E`p90Jq2JN7KQ*#$XM~9E~>{
zW5LGnUxUTj*pGUqea3YktVs78{~8G|T#Uc>gQ~01W-@XIjOFwT>x0G~^naud8Q)W@
zA2yB~2uIzF<=c_C8*7F^c*OXgrYT2_7w!V?VVv{<fMdp5>fSw#ztSNDFXMb#)EzhO
zpqTp!V+M^;-o|yYwEjD3yx|BPALE_=pz$@f(E;yg>_i>SDWiS@5dOw<n_wxxxSQ%5
zXw0KoR**4t8`?S8I4KCZ5aV?E?MSF`Z*Q=K8Pg{tIc*$GKb$*bG}D)Q*7))fa_5ZW
z2Eny(<JOaOb}+(tf_`KZX$+?ZjxxTS1y9c#JrZF)+E~63ZE?Y<qrJ8mqg{6-u|_Em
z_&DRMNSKH>7Pm$&!FWF$@QcRNwSXrY_tSyTBx5;6v@RLf)4|we<8mHeTsBtK0(ZqY
zDF*=SHDl>hAg&v)(J8$fMt7Rhry5m-0NylC`xS^=#_=?mrx^$KL`Bn$liPy(w(;>U
z*u7)iMzPhq#*>aPanBe`Tl5*m0h!2U8XYSDzi-skgF4GtMoZ~z<1;#i^T6m!Z`VVs
z@d)*LIYw(oWFHxSTMV6CqsIj3<QX^aMlRnty9w|G#x;5HqR?1I1LtF-4efFj8IRS#
z-(us>laVViHnE4nQsez;$UQN}(GsG}xTy!o%8gDR;8TUsb`cC!8s||L{M2X-><rQ>
zV+%UYQf(}wHSIIwi8%m1H-^xmv=_$jr-JmQQR#!+E90LW*lLVLnegJZan8@k)f#8f
ze+zkIY&!rZ-Wq$*Z%^JC56wc^d*fepH2Z^bzy%0D8q<40v(6Y#hjl+0U9B|k)*Iu8
zLFcnkO;h?W#zUv!euHt>1n7J<excXvn=yt1x1H%a9kSeI5}LwadsEvS0Ct<^(m5~(
zQzji7-(z~X6)Jm8l0Q@&O<uHcb23efgn4Jve)_51K2rf564`J1tCGe)7n6J(Xk1M?
z3ZWk`jSB$HL6eD&1RXLhp?Tn8)4IE0b2H6Y1{HTx-M?TvVp^&K%~4akbx`pzy{8kV
z$4s}W)AcmvIY86P)bTi)(%ZD^5j;F;+BgtpKBlKHq3LUiJxlw4ex|k^@C;6we!T{S
zzp3v#a0i$^?*(_DX~)0tBFMC+2@t_18O={ZOj{@d5o*e73%g;a0kpq++LW7%vNNVR
zv@>(o)Sp(G=S<fr&=hXEnuc72>F>`_i8M8%+DDn5BjjgQo;O{ilRD9+9z)>b1(OTS
zbYo0|lYxjeouX!oGv!mu#G7^nAW1OQ_lD+0QvmG|B$_@yMh%lpXKj&OG9`b9B-ymF
z2FYbpPuk?ZV!F5($yHNpIg%7p?=G-#%~X%iUunH=TFWDQ!_<>{s8rKQ+8(=U8ru@8
zw@krNcs^;Su@pj2H_fJj<hE(k3DoJ1>AOKNf7djVc5CmM$~VAZhN=2*uw<HSZ$R_D
z={?0*vP=_cBP`owq%%_wOebi0^3c?-8jm8!YFb@_!bc`Q`W<Yp2@e||p6N9$*YiyY
zE8$Fm$>$@4g{Dok*m-OkkOUJ&rXSD2wPKSi&Fo7|W%R?yQq%9WANItQl7^(rv^E%y
zmYWvb1g^rAN4rIprX6&Q<*CV>4%ezoR&x~!t4;sW=K3>J3QbU+n-14Q^@VAs3ZA|+
z#SaGJm1(^k?Nwu1We>k!n}T10yVi8h2%0x0?LTnzgDGSt03S`_SitK{zePgxld1d$
z%IZzrduV<(#RY)ui|OKE*lRG&wDw2#tEoAi+x}*{OCznFdD$~mW|!H0FLL(gxiksi
zZQgMjIR|qdE&TSFms4zJuQ~rX;Ev`7+M#qZZ=8Z^JDaU^+G3x1b`ff}-yE0<M_tUl
z>0E`Y`P@V}bHF^b8o7h!f4|ZG-yyT-Xy_a^Por%cH*+k_d)>_%3Z)$}8%}`xsJYcE
znD;RI&^L0-yok27J<apy!jhLcWEnJ%n;R%dc*5*JGfr>wXZl7?n*XAhgOB<4O{n;q
zH<zHEe&*jjP<G1v;1d0dL4R{UFPIN7-=Ua$pgDuiG6b22O+zl&d?p{NA?9T<APqGa
zeg#dKxqAz!oHh@MK<<orK`d0xnq%jH<(xTzW`*JA?zKoF%-88jMw)N*K@w%|;SFcb
zo4FRKM6~(!O!^m_7tCWhsK%K4(Mh*h^AMU##F<xK2V1;(#g70cn4b*?@S=J8R``@?
zHqv;VWY!M^;F39IJ>bdad8BgL%%=cw#XM&qT)S${*@m(dv*Seou9<HiMee$Jd@r!v
zF#k)#r#01FNr#PZns+aS&Mot*GayYfJ6^yuNH_QMg%`KYOm_h9m`7Xy;;z|uD7f#L
zjXj}~VLmYrEt6^PO!2k*=Bg<WW|<$~hDx^i&^zQFn17{XWDm`=b;#wKANs;jp7{!e
zqVuihVjUbVFsD;+rqH}}AIv{C-~JuKBJ)97SQML`>Afm3`)>iT)O?MOu{|-5u!B!!
zW>1O<m7BY+1g^r|cQ`Cnn#WBC?y0%-2Fj|;hpRzdZN4=IWzWo$=%+r<&0GAS^1}S*
z^jH92n%^t{+bgpzEk<k1U+KZVHoIH^qSm~KcKqI$o6*Ypt+`YKws+<kGeGm+oJ_|v
zKA44Mz(1M?gu}x+^F!JP_+%co0c7>&b*GT~Y%X;l{)fpLLH|?vn|VB~8SE^&R><wL
z3?GI1*;}giz`$<H)3z|+U<r}I_#R7#8?dw2($)-SM@!aC2%RjoGB7(^N+huCvrMOb
zo&A>1p(t~)SVeHUTKpVg^?>EC$MEl<W%B{39I`}Md6+nCS#=+5ZkE@y)$DGWwGBE)
zEVC%^aMbcH5<(BlkWz3Tvn;s+^PUz3{i6;q%U)XF9=9C%43!g>jx@vcwp<+z+(}DY
z>Q;R$6Fgzb*TPcB&CfC*5%5!%-n3rxx8$Cu+6P#MN$?`jl1^VykYz_5l3>e*UN8}2
zaS~9AP|J1N)(x|$sS7%7`ASRRGnVLu$ep#gcZJG1iwo_Bg<Fz|EW*-a2>_9nmIt93
zWf_zXmGhRazkxH_VhxAzf@NuUn(oF}#vB47*0P_0!*Q0TYvJidOY&+YiI!WmqD``t
zQ~-a;vW>c+WXr1-NG@Bt&_laoX-X6FtCnP1kEd9EqfO6imY2(sT(>;1g%>w0ZGQqh
z)zXv#LpLq84}rU7*@~F4Rhed)(hk{lOOPX)=C)-RjhA;UmGhCiYmw*--95_&I^mLG
zSxb@rObhcLT)S@xcSl*4<s_Z;&9-E8h4}}TfA*s6q2&-QT5~Mf&w+bn33v{&T+85z
zpw6>=2m&DA5<}~*ZUvUshf!E)xqb=0J+>5{goz@{)Ik6iTTaqX-AXK#zoWfMEeqYh
zENgBZW`|6rC61Q!Pc1*wGO@~%y&Rm?mX$k@duDlm5-QIvE$K|;3(MW6NM2gT(5Uyy
zlKmcD*I2sH&d+O$@f*z5T4J9A@WvAO9a`e8rGyrJ?<`A7!1>;?mHLGbme+mY?nle7
zR+{<OS+e@T-A|TP`7l^-DWdaQpDn-8(ULEg540=WVCjy3ZLj=l`8x<I-z<G;JIBt}
zv<+puY;|;u!rpdKJ<RX69oz;v2isvLl<l$QHiB%gt@ED%INJ8P3`0(~Vj0Xk+qy5J
z4T62PzOit4zpa&yTDaIcEdkKgHk~5J2W-n|rE}1>Qz;OKY>TSEeb_dWfh9NFgES{|
zw~eLM<`LU|Gz1^DJ^Tqm58JrU$Q`rY+yxdqZ5NFP+{<<s#dW-GKZc_cCv6=}v_bA;
z`)wo;zP5cBB!0Gs=$kxcTM`4jzwPTOXs-a<F?3uy(DoGVYX;dS|9~XeHZ~eGA+{6D
zs9~t>PzN-3m~AGVhdpikfzHL9vGpi`!Lzo$w1IQZwyO)0a9gJ~D2uS2m1%=FHq!QV
z8_-1APFW8V=WUl#2O4dwI|YX?*ajX!5@VZm6Np&bhjstQ(RIgVS$%Oett?9`?cICt
znQ2xw)Uv7BPR%s)XWFpLvh}hR5JV7>jUXT*vSjZiQ>F-l13^HRvIGQy-}m&_`P_TX
z`JQtx?{lAf&pG!2`e}^N$6+a*;Yp{F42JqskW9u`bjHqN?E3=dvl)@cA(F$`NBNjs
z#;zi?@)%Fg19U#)t-X*eU_3{K%C<trt~d;)h%rMoUBwJBtz9LIE{b?xWF)-~yQPfy
zGVsb6(^MW_&e%`)p(+?J=0mTN@dZ`VR58}3K<^Smk_}!pW3D@}YZw_6@v3Ef{uaEb
zW5`ybRnIu-i|J}$7+1o=WgEkE2FykVrx6-g7;n-t)x>y;!aU845&9;{RmKX6Y_>4w
z(b1@t;Yt;Q*BHaqP`J)`BOmHF7&{YT{wAY%BU){YH|W!ww-{$B=h4papt8pfh9wmW
zw;9jU^3=)5zXV<v!&dh#XgA|x4VZTrd$wVqJ&d1~Fwx8Kc><)5@mUT)`x%XmP#j<w
zUxuZ-jIaWL-eY{{h1MYB9priz3^5+k^E1p?v>N`7Fsf<GKFXLs7tr?^u?sNkV~hs6
z^E=KM`v4wJFnVoUz<j_^z735@#xc6XH^peCw9E|SqkU-2GMuQq&W?GE2NU+p=PRJ^
z!1Sj2Hb>?+iy`8~tbGJLXXeio2XkR&Q%c|v^MxPLd6;>G@<*;r7b-DyV~$op#GUCp
z4SPqJHFxQ9r3cfG3mH%5X^J@=WqQ636JAU%m2@6s_EJ>Ln|YkR#q7fjp}od&=86kw
z`7)oRqw5Lgk!2XRAM;77a6HL;i*}^`%(Ncp1u)mqmr(+liL{;uF}<DvW-#+%B1j0c
zjZdG&2xWE-K{SkM_cjzyG5;=y-{H*NRC5r)TuwDzr<rbtK_Z!3)ewndPRBz(nrX9w
zoMCdQhAf8py8sGjnY@4CQ!Mi=ty<@pWAtpsF^|w8>O9kfHsJBh?nUq^f$8r|1!9TJ
zbN@myiHT1K;lX20hGC*EFnx{iB86%80xy-hjTWIa=3&aCrZZQ&0WE{MeGyujOxwq3
zWidCL1IcDyC1-M&pFM;^F7p7L5%QQDdGINpd59`H3z*->!%!h}l78{FB4!^QE{d7X
zN-#^9Zyd!4FET$!g!xkDHa=j=nBunqQ_i&ShQSKv3#ZXp$$aTPELAbrMgr{;Q_2Qf
zHFFnjk!qM_)exy=-la%+9kc66@amblkHJs_v-${lmziZ}px5Z*wpVKVBOGF_%suUZ
zzs7Vs3+e03Z+?Q!Hs-!uSh>Z_r_au`GlP>sI+&gm!@AAPq;qyB^BhIQx|n&iICV2O
zQ1Ra#=D+kl>|rimh(A#;GrJ$HK4#-i*z9K>2m%>k{zO%KcbV7!`wsOz=6t$zHpp!K
z3d|v<h3;MsGdpbn9bq1(=)@?~oQKJ|&)h^mjWOnj=^*3GCK<*v!8}Nr;0H`IWeO*m
zfgJFrn0x6g{E+Dp12WAF^?<<{X2MyB%rZZE0xdgM;4e0S+OsMt#OlBbSp+W}S*=Fc
zbz)U4g%{2!f`R)kthAdL+9B56cyu0S75oEGSJqxi_`9*TWWk_2%a=BLM_AudcFcp-
zx&oFwSv~ZYJj&YoG%R?rb{zyc#_FQS+MD%A9tA0USdX%ScAT}s57@q}Uw%aE1j~!=
z8u+m`^#JrFt4Iwre^#CsTnk{m+yl@+mWWE@f>;rMK_r-Eqq9y3%RV32p{yB7--og4
z9|JkXx_kh<a8~ZGFdxARnS_PYEbkR`Ng$HtMmg9h);Erri)hxLmw<MLwS-os7?#%`
zAZJ;gRErnO>T-kRIo2c<gU7KB(DjS+tVk+)if3_thW809w>X$cWPSbvI+IxDNnj?k
zKHUv}FR-kkn8OrSC!J7JS(Wrv5?dN;|8+3aS>-p;%wSpj!OUcBtpUkm{XUD%Y}Wg9
zzcYt*`657bS<9&uFpssLjzxv6r-V>1V(}{Bb}_4tt}m6anmXakMOL^soGE36Zv`o1
zZJ@`xoOSRecu~Q+cLkD_Hr8+MaIuOtKq=r$ECCf+R<l;OL!*Xep@dW|tB8U~b*yES
z+N@_)bii%{YmWfrGRs0wa3jk(96nuPy?qQKO{~UhU^laFzYo2uEDjy$TUg==D73Ot
z{@Wz7*3)`$on`xrb}Tno|Iq2`CaW$3qHU~=^+3DDdS*99-_A;<j8X?Hj0)avv)=d`
zL+fM}&{?UAl|~8sZq_oYJH5l|UX9Kk)=W3t?qwxVEVqyK;~+>sYmfsnz)G)!$X(WQ
ziZ$G0mD?!FH^@3k-ys@eO@9VU!>q;g!5m@PssTF6a(f26`z$RLP>!)StbwEBtgo&@
zWP+7Q>JL~QG^LZQ*+0RXVofUX7kS8<qJ?XkWv1%J8J6vNn4e`i?Lwy=`)gmc?AdjW
z6r^xq$M3>)JF>UaaoLGIL2qzp_Vo`zT-blnR|gNVohX}rnC(9S_g&e)`2xm`t=$2;
z?(C0R(K^CDyAM1M_Iir`da^4T0d|!A8NC_2*s*xx7aU`^y@i%H+wWV5_^^Er({;S#
zY|kKI`?A}7680^%{oxAN{MoYS0Uf|@cpZ{~Y|B4r1+m}V0usy?(-As^-DSlbgtBjh
zqZP(}W;1xF*oP==bDI5q4gRc=>>*N!VlPZbE1JzqhM#BHdnu<L!!{}4%USkc^xltU
zk6s7w9Q%Te4`1TgdfL&QXFvYmr*YXuo{&jkTfTv7iR^t9Fqp*7BuA6kuTs|J0^2|d
zgB12Ex@Vut7W{<HG<GS4pwij710We}H_Do1ve)(jEQ@{cJD_B<pQEfv4x4X)`CNAT
z4q9{b*mEgpoX^g<ir+&4`<Ds~w2+-fvsT0wJqeg%wtFbXRKi|y8j=^;Tj)Gr%096b
zyfXF>#puh~qx4#=VE;&8YN%wp(=t`XzGncr#O|-g0IS*EX;7$Pe?no;T6X^LbZfYd
z?QtK>diKYZh-zTl^e}OmZAZC*M)u3}++AS@bU?9*y^zXIo7o?S0rV<+j3Tow?3T44
zt?WZ|G`PkNy$N!ieVR6+H`sl_;N4`uO~KnXwx<Ce-eP;xjjDEbz&I_49qht;Fn^ov
zavqjC+0s3*+r?ft2Q$;n?xGam9d^tXboQ`c-H4&}vTHT)qK_@4mrFmpi*{rKY$rWh
zciDeaJ?}mC3vZw`$PN@iZ;1VpJ$xEw2iU>T2)mR8XGYnJ=qGNw&%Qt@$uag0DlZ&o
z&!r;N3HH~Yp!I-#j_$TkvL}M!_Y^ydf(8%SGa(R}W<UKoMlr+Q;sEor?9^Oz+Ht;4
zhk`xlgJKwT;2fsq!jTiY6F#|cswnPwh_i+cREIf}UeI&3ad=e9;KrG91e!aif+8nJ
zIGbOCq6a6B(vF^-+Y~fD%GtCIB3_)=gz)zm%G~hN^X3fF3E7A92tDY>IR(DZ^Tp@m
zVeka!yJyhy<2*(`*^`_n=zQbPS$PGM5WvY<3ugj3wjaNS!642c#h`*YCu_hA;cUx*
ziBL{IMb5)Gv#Zg0isQWuCc-(EJy3|?xKQBcH0L1IEJbq4Xwiz|9HiwUn)6{H6wYvt
z(%w3Tvn~nFoaG##yi6=dM!S@A9RDBSb{yw<8_oK8PU8_M#&hm*ppn4Yf?GEW5;==q
z0h+{_yaAHTdCv{bT;Ob?qhAUq-UVKya#R#sOyex4;9xrE!#5$4!4cDLEt7NhJ}|R5
z>!x5Sn^XK4%;#`^d<d{y&dc<N$>SIzZ16On^V$@e1)PyRuv^G^iPpCwP8a3aiaF2G
zF}j44`xMYFa`bfJp_FsW2ADEVG8KH4bNZ;<t%B1*udhnZ)IE?Y&LR4`=_O9iFF>j0
zJR^aJHJl+2*sJASpi^lbC;eO6kkoVZkD%GWX}<}y%bYjqyBCd|B%0?doHjqeG;yAN
z6})E7W{T}!<y?LfgK6QMrc+BRCub#E*En0}!NcnucS`Nu;1~zs=uOUf+Wxn3-nfR=
zElvVKw{zyuGt$Aiy^X>+w>dnTnodq<B^2*)0{6jS4<{i6q?hycI6C_{c71^9=M>Nt
z^#RU<z2M#Du=p6vJ<g>kATr3w+yV1LoR9y9)-dN<1{6j()lCo?<>c&!h5MZMsd8hC
zGgOVq8|TCoL&P@0DUHD>9&jAr19Osdkis%koXg)r<{@W4_Dl<=Ii9f)nc>W3VxDI?
zi>OM_jyrD_#GdPN1wJ`&`{?xG$X&V>t~qhzo(8rvcm7=PT)6o{bROc4ehZPq+^;T!
zxN<d{V9(9QJw-1PckVZC@cRh&=2~cYaMz4N!;_o30<ELmPifim;{HV`kz?GfNx0_C
z{j&<4KHQ2MKs(N@Fu)mKZYb?nPjHJ?fak~EN*nW&+(&8E^5<$PeHXx0Qk*J~yZtc6
z62!IHe+j$6+`MhT4&i=Ogwcm`f7<}XFmCEX$eiK^P%I&w`^Q?Ch~UQLfSl&OK$pED
zxij=sMRCmvU`KOtSr!i-H<W5TVz}c}#CDdO*aGvh-2c&A^c?ph-ARb!PSCS?p4)4?
zfo44ShgacL0{54zKuhEn(3+CO9iI=MlDUS5AQ!lf2%#)U;W}S{rBv=RH7uoZ_tir(
zox6t8_8Huj*MO4AJwY4QEUronlFc1{26{PMHKkW`x%D*MJnrm=;N^2iSJQ!@fV+>%
zPzt$jFT&v>Zu(Yq7IXJgMNkQMKHd@wE^@cg!&S<CgibdV+~ziPR&wW3*td!s5`xZ4
z+)BEYQ_VFxL%oLk`4zNkxzAGFN*(u^O^~eT2A_mp19!zGC|u^2gi+OMBbWUOT)e^!
zISms{+@<tTH*-D5Fs7^A6|{|P;U?68*UFVA!0&6^gfL9Pb?!!bDsFIBehm{hxvrGn
zY2z+2f!yMLBEpc`x$e^d>);O4Me5t!GTQ8Sa`WE-uZw#c7s+f3y1C!eu<vkRq5WeI
zcWpT|dbvqd;M&K{eHt45+#VSm9^gK4958peo8JTP9``IA)CajOB^c8X_svH@hPl&c
zfilANr%mA~_xMtP-RGYE7Z%322C5Su=jLpM$OJb|1~A(L?mGJT#w2$yZK<cYp0j{?
z$X!U4In!Ln_hEO28%q(vS?*hJqtlMJ)fEc%ypM{Z;J`aM1rHs0_tRj)iFcGP`Z@C)
zS3uH*_hl@|A>LDzfI7@u?hm`JJlp3WZoC(%g2LU#bD(^{5ng2wnjXC6^lJCy-KJCg
zQC@Zxh!<~wQf0?@OI={sn<sYw@!@TwF!^y_g9(%G%X=#k=1=h0<xuzIZNH1wN#0Wf
zaK@ikG>Pd7;F)RD63Fw41XvKyHiK3$&(=d#KOwx~2Ec^!inf4+@iM6D=M=A$*4}X5
zGX)q$1h2OSt<${jCon;gyj>CSB8pf119;KAr>!7oc)!zDI);}n0Ph@cTQtna@fZ{+
zJI^bicuYJmVH6~RXQnG>iM(fQRS-?$y+_4A$-MWcpnrk){XF=V!uvW1im5ywdYz^5
z>gh2|=iQ;9W$-+x5F?W}{3}GVc#pq~F=g}8eg$X_?@=*Oa(VCjLnM!<_!-doyw^gY
zSHR1-1?WQF)8E41B3|ZE3JMqV!u!E2;mx7q)r-94R6|h8bA1+`mhq-;1GJp?{R3F4
z;C)8%>PntH9VDuFza>NA5^p|TDXivwd<&p8yt|!f)$(%YLa&bZzm0Iap7+WvbT;q`
z8F1z@FI522$Xj@u-hWqkKhbNYiPz=`yUjeMHx#e(z8{Cd7M?4`3R-!t^!dPRy!@5m
zUFY5U29h^;>*iyGH+i)`pw-4}7NB*D7e`6$cHVv_JnY~_{SAfNJjXpS*vZ@e9{la%
zUCzWHx_SOM7}yrv;pu4)(!=|R;;Fs78zr#R$Gdt1qW!$*y`Vq93!H(6cX{8^h01%p
zH+vy6$ctKm))23o;`772zu$(!2(OXW{865C4@B<scGHqH#%qs(hvU2?T0$pyA#{E3
z0q<41R%V;zJwb_&Dc*L9Yd+*LsoZs%cd8hpnBkQdL4TI#ODPLGe%D<PdwvydSRMGQ
z55Ol!{&XlrocO(NXgTu-l^C`Q|0J#Xhxo0ZgB<4j(rW3-uc2t48~+YIQM<sMf0|wd
zo;LoLUX0=>KluTeUi=h_i5=q~TMk8UK7;m7KKwW6XnCAJ;0+C5zQ+j23I5Lq0prJS
zp(EEx{`G?xp+A2Coqz)PAEbd7$amTeupoZd9e5bbAA1fcA^ht9p%u!1E(Sh@@olev
z1-qyC+vw~a&i~;9v?BOx(xG^oUrcB3NWPeY(NX-DD6|&MXLNyghQFPH(J}lV=n}<Q
z{s%1}vHain!R>Q=e@~#q@x!TX^gLfChQINAMky2$_<vGeP$Hk#01uP+_*N}IllkvZ
zl=A|AlMk>{_^;ElmC7&q4tCS{AHEFGbbe14L^Am2-+|wm{NxE>XYt*rGn>z)(zG1D
zm@>|}{Exqcr98g=af~;gzleTw1^kpH&@1GN=vrqHzm{sViuwCi+F+@Kucko4MZT&9
z8m0VwRD@H;7tw-T&fk3)9#-&=(bwWC`77zddlf%}g0q+SPd<;%YW^n5nbq+1|2=s8
zDr(j7l_^lK=ey9Aqz3-S6q>oruUi7>M!x=C=w0FaS*U8YiO>5EGR^!)DWY|ie{2Nf
zZQ;*f1DRI73q|Cw@#oWB;OqQ%V<2*aZ=&q|P5xgWW7uu{_$M%kTYP&1Tx;jQKxgO<
z{%37azs)~KUqtNWzmg9NUHrz?fbQl`g<)dv@V|pS+kzf`92YXZ{HI=kOdnsq9VYtu
z4z$l7;3wUH--G-a$`B3lPyP3f<3CL^JHlV{ILwdoJt^RFpYL!1>SO!{DmxqJucb<{
z3I4MbA$`CPpe^PkKasY!Q+%hLu=kMv^bCk?n*R=7!wY8k!BlTE%kS9?89Tub6zj7W
zlrP0790b?GK^z6moq%x?oG*u>v)~kMk6Z*^RDE+uU{CiB4hwQA((Eeux&u5n!Lt^i
zxC?GlP~?c9n9?^Mf<0s4c?w(;;Pz3Qpp53rOYj55+>Qx;rH!Yzz=!I!eFWRr0PVP7
z)*c$Zf;mO7dqU9F2}^#0ghuF{6dW>v=P#I|EJ1*PNmr2r1z*s!9VGaRh7>ILTmTXx
z*hX9GP{9wh1cwQRM$kGXu;sl4CjN0bjVVI#KRVH$7W_el4UvME=|vwUc!id&Xu-lq
z;My5Md<D$M2xj`wIxA?U8oXFR6rFj_3DV{QB~EZ;B}C2(UZx*JydacP2MK}$^ny<m
zy!{UBCJF8ifFuiEuu<mmg5bttc#$I5K;MQ=6<E(fKTTkthWSbt)KZKvL!i>bi%h}y
zKfy$nV9h%K%@)K{x++JoMg);u0rw4n<q5jzNSiPCr4_sa!TLX7sZiiw0`(%nTYo^k
zSdc>%1|@>ja7yD}6s&&(%u<2ZCm>}4&n@UI7qn2#V1>Z#9bi`q@>;;F60C_u>yqGa
zdzh#e@LvK<jUeDNka~geFx+ksH1T2ZvOq^QJdJ|lNa$S=80kpcB+%M}*DUCu@bXo`
zeifzhTLhQrb40BI4+qFx6I`J}@9Tp7y|8pc@D2r9ZwglZ1(7zv7azm@TLOa~*zJOk
zUII*qAbuTqw*?`zG;|7D==M^Vz%C7X-GVB5f87zBrx<&WU?J_2dIkQGnC3pgRwt_3
z=@<M=JKX_+`#qrD6{Lp(`<`Gp02+gWFTR5pLxQ*_hztuZZ3b^d@C#j$9ThC9gNgfs
zF!Fv((E0@|jSG(a1nddHYf)%D5M+B}ypw`5Dv_QNtf8>!L&0lSC`=2c=tN+f5&S}N
zg;~MZdx2&rETJHlz3`hN5C`FAs+)EcdQeW*NmxrMG-u)JZ{dZD@CiCt91<F-qUW%1
zi5on06*4aZ)J?dTYRcS&H%h=eA`GGXU>?Flbal*A*p>nFM}^+4==8D)zn~ZAF`@l;
zV0sJl>Y(8x)D@t0T*&r@YrevQb#Uf{P)@lsKVcj_+b4y$KLyWU_>KqE1B7C#UJDd5
zJ^?RC`0b}?1q-u0VJSrT+yO|23Lj9BNSJUB{b#>Z!eunTaG}javF8XO%M633h2b|L
z6DcgD3qw&tJ?+e+g}eR>rwFqs!x1A4cn0LGa54edvBITv1UV<%Ou_j$VIn=S=Y_*m
zcoi@F=^uzB2&XGyDN&d}VW$hiz2#6(5k8v=UaGLp)&-g-{EL?0bm1qzfSDoep(id=
zcxe`MnI&|H1}|H<{5_By;r6-c%oXn14Y%`zz1aZG7Y>F)p+Go?u2d8X3lcGwBH=g}
zq*&NbA%GI$OFVdSQRqPj%~D|mg;C0cjcj`U%7t6J!K@HAQ!b@axQ|XbRYEcCq%H|P
z_kvd~d`P>b8ezT(ty*CX9Y5=Y&(NN@Uf4thMh(K1R8xH!-;9G^qwv6sFn>juNk91}
zq5J@TkIlk)ec)XcKA=Nvi}00S>HOC!WYFVuO*onaa$Wf4Dq!Cb8b8N)Zwd=f0klmR
zOc9J*!g*fsw_RB056}+bdO3W$Ez~rFbP5|bL$6C%+X#_v;U{#<<c{!LA?)@D7tV!3
zukiW>Oi-V2WGQ(4!UG5!*%k~4Pi+G8uF&aen7Ak0Ku_bKa0xx>L&AZl;OVgN0DWm`
zL>NrPOQXVJ1%`HCxSSNmgn?DyjSHjB!_tJXwg}h{gilh1*`)CA7?3GpD#gbh3csKm
zM$^J$LC~8K&V3ofwap42-h_EOk>CVC?L`4YKywhaQ`*E)G@lJcCsB<ELvt2AUJK$P
zQt>d}L!$00AcsZM)0iMvk@M5wxru7s(Q+3(u^f6wL_?3kpoi$rdjRtkxzb7GsAvP_
zIlM%5ry+98CfZMDQ*Y5{^ltSLeY_h^oe-rQN6SwXL2K_x(Pts(^cSU3foXtf{!>5;
z6!oV<KS-4K7W@qsy@=iPf)G))1cL|_U7_q_nCSaS7(699PPv6}kwXu_B1AS?U`~tf
z&`~^6Wb1qhXi=gu+UrG&v=p>EBT94uc8n+~3^Hd$zT<$275%gm<eX^qJ2(?3N~9{?
z^CEmH6_1)|9v$uyMBi-#N}@;-2$UqzWC?sq7V$rW-UU&D7~ZFdK6eIYs_4~iP)HNK
zZ_7t-x+vx;G&4l!<-pDqDW8RYmZ*o4-r1rI3P<LMhAD%UE6SwKJW;+Q^zub7-UV8L
z=%;azLeY<Jf>$IGh~QeWsE$H+C8D__fW9c|-ho!BXprih%0y+!FjOvzxIrswg{bWS
z{H_!|LVNitQS$5X`;sV_mi}tdZ)d=(5w-mZ6Sbn2Z-7=O`t>bH){8j5LZm^|^9ek>
zEE=Z(expc2mo2Y|vMDm$Bx2EPzggr=`-H2anRM7~5g90D+$#Dsh^khviJqe)^>xuh
zTKsN^zNP5oP0=CxeYA-JU10Z?Xl6f1yJ$D1Ryss~yb7Ogiw@G`-zjoi1%q88e@aJp
ziw5qZ^Ny(hFOVLQh7Mr8qF=q?TAyhDc0l)we%S?Q21Kt`)Bf|W=#4L+e^0bx83r>b
z>Mw%Kkf`n-bPkK=9|FvX$e;c}#Hc995rereD%PPjA#$R9#skqZs=k;Msrl%f5^XJn
zYY#;aY1XDiliu)YMudYVUU8yj%^-H-MHFhZ7e^#R&*mWBN;x1$aR;roPU5^w7<3l@
z9tXc&#4h*n_c<hXrU3C_@iGc8xQYX4<LV|}y#XzE@nQ>Lj);9fgSv<K`B*4;iVyt?
zk)z_cDiAO687f{qCSG+OhP=fC7covBan!ru9k+=;qqnKA*iVP%39%*}F8YaUssVaZ
zJW~mtzxWjG3<AW(6dn&0*Z%^MATf(dD}u!-RN)jNzClGjq2f)=KnW8^P?6dxF`IJC
z;o|AVXhn$g={Iv){M1RbBE@gfsud-+ZMX><Ex!IK^v{T0>8rLe;#~R(oE1OQj8?3;
zXBAAG6CbTYXPo$}5)AabSV*;B@#0u|jV6fgX$egfXD`D%C5h)(05e%!PWh}0;<OI<
zn<9?wMQ5t`Z&&z~CjMOs^>pz^Had@Gh$|>zk}3Z6Uof-8uWf;1wpcz1UXD253X&_H
zvj}$c#L;vCJYT%G3<e9t``-a}p?EdzW{bq@>0`RZ;;@YvONqFJYJ)C{w^Hz{RGeK2
z%rfyxIx>}u-*y725U(kw^IxTS-C_7$CB8)aluKepHbASzJL&IKBYr?tF16zRT%gs7
zLk<G1UVQjV=rxFMZi8!=#j9u|)+qks7DTRySJ4i+Nxb+td}<NzrMGvhIPDKeUK4Mj
zWAAnGZ;t}yhFEZl_MbP!{&Y>bO&mdkxh3AU8wT6OgH%P`A>L14sJJa&p@2xIIF%N^
zF7Xa}@VdnVG^KaMLythRN8I#3boPp6!BFTEGYT;m{o)-`@CL-AAHlV|;`epn-4n<D
zj%gkgYY)-?su~g>lf$WDaU`8DM#Lj@=pPjy35EWBv4x4&m^gY2K8=gtrGx#1_{)u$
zt_R}RUkB)<__==oIwc;aqSA-r@@yEK7Oz<kXJ*8M^fsIoJ0!z`okTSSyY`ZR$G~%t
z^qvQp%~8@yxjHAwCaOAcmWboga*_Nq269NE?gTk3X)cC_t7JSLB5sm=3N*P(0w|h#
zMAA!{HxJ2j`pJ4qzU4#YsATNF5=zO;BupHWMA2K+TXHZ5gYc1jtOq$R>G=lGzBb8v
z2QW`aI#h7cPg1`ME}oR!>j0X+q`wU^0g_ybe+EiA1JMeS?B&2<uq2<ZYlKMRsgf&H
zvbPH&VUl86Hcm-SEP_b5<ULxoA|&>dCp|5BHv@JfCGG1lmMF<M75zj@Y|DPb44sjL
zd=Io3$*=*;vyy}Ke{EtVJ1Aj!PBMp9>p00bR5W~EvT8kA@seoTm?TK<QIIiF@_{`p
zB}o#=wPeW#x?yxdl0d=z6v@q3(3vU`ZiW|W5^e&#NSBCTf}spax{YclvL)O9g{2(H
zW{PLzN>*)#PkEBXjZn;&Bwq$hf#k(HkV475AK_Y&B+eQB7E28D`Ye$=_7Bi5N<!&3
zS1PHZePEen<u@SZlE-pkp+e#$hkB)C?p<J3NfuDC(k03NPT0V#mi({>25ThAz3`$|
z^38u=<dDqEg2VNak9kmRkRU~XM@@3@DJV8dKB0n@E0SDVSeqn^zkyz}B<BcRyDG`}
z0j{-30w{miDp?u=-ZjZ=8&IxGED7M<kW>nxep9k4;&D8GZIWY@-M%Fmpu~N<q@Grv
z4oS}r=--xP(nsMtC2bUp?UJmbQ*5{7`KwU4Be{18pgj@`ty;a3m2YBbeUc}r`mkRj
z%!Y{p$#;JP^R6T;26pdBraIyMpd^{%azm2ky;PJpESdBJ_K3tpOUtNaH^me0OO9Vf
zYfLhC1~B82j2$2olJA+|J&-&Wh}NW}I31u<lKdoeK9r<C1GlFo3A4bSk<6z+?W|<a
zA{exj#!+n4Udn4j%Rvfrc;QK(-HMjYN%{i=E;>ucC{64l9pYjzholY^p*k#`^AMe`
z()TaHgq!rYN5ONKZvPXCN2H6k!Gwp@Z3x6u`XODfJSwfUf_O;-S@7_fbir@nc}uVL
zLBU5l$OX!AX$@^deWl}306SrmUU(KJ{G=TeXFe%CKwmcXm(~`bGeEkOc3FYaF1mCQ
zB7Lb0vmPp~NQ7dTw194ho{}1uz+kv^BLz1jq+?WMa$357GbSNYdPa=SD5(>Dg(X^=
zkP8cEq>4|#i;<2V#ozU;)HbgS%~<JE%i!rb>9zTAF;4m+ZR^fUH(x|6UWzZV<580y
zpr}fs)Up;ZNz!JDza&e~QXt}jw2ZPZDbkSJP)L>f(P=$RdbA$U=~DG|xSb(&wn8CO
znjr>smh|cf>}5+!ZAYPzBi%=5_+05ux`vS_T}Q$8e5o(xHVUM#(H^l-s&a+hBI%2>
z&@Yzyq(QGldNCd%7p37lfmSMgk@j3=(!BrTC(=1vp;sYY_XeOVrSG1C`6}rjtx&im
zeT6)%mcFC1L9s?U*#OX5sg~-v>ZFb?@S<M&QWJO$(ie`ynafg_RE)4u+DI9pE7GHM
z|E@_IH3-ry&3YdryehS40JKFKL1EBVY42^cu1VL?sr$Orj<)1Cq&K2~a#K1~hgO?(
zZzY}oZb`RLLabf-B%QiDq;n`zdt3V0PT1{~K1-+WE@@Ic6uYJVbkMyc-QEj@9;rL!
zNqeO~eE@|%X*NxFzqC{d>;dVsbPT*J-MaxJyC+>t>7_yGPY2LBB;Ecm$gp(BBlOj_
z5$Q-h+#i*Cu7-*G(w~-tj7j%Z0Bu~lat_8jA-zdIwg=L}K6Fk>?~`j&(k(2&Jd`@$
z1euoJibtoN%#K19_Ocxx!ZiokfnzZ5D0_*5S5C6c4<YF+>ze}$F0vLXx3?XVZJ&pq
z*J0U9bTDz1MIk7(z)g007&7j%1J~jA5m_b;#zVF<2^yZVsPAFvsBD`Wu6fDMeGa{2
zvSrbb^p?5PTI3`15@1S>%Y3L_%~$3}5r`AAq4$8|CsVJ6-bvYU3X}QUWZnN_XaTYv
zuR|kHHvJpi50b6U1x&Ck^b~j@vUExchRR%C#puIi^XSxlN_KuPB*SH66yk}Hy-psU
zmYLoHcBE|fO-M$`n0~;FmYrIM)*0EEVi=5(`DI~%XJs7P-^a>q@mXM=ll^@kmf~b(
zl+rmb`+<^*@v_foN)u!+?uBBa%)JfRNwSZ&f|o4Y69#fYcF+tjQe-|t=%vaY$%SN^
z?1T|^(`6wa0Xjo=-VG?3vi{Rh$dW}Zg+jLMqd#CiN4Cti3ca~9-fm1{o@`kfVDe?G
z0x%0?AE+Q&D4V5<q#{{#DO$y{$LZ8vB0CiTy^FE|T2o4833Tc%lP#|SO1W%#JX#ep
zHl4aFWw{!FRmo~h7~mz@VLAp@%bqNPUX9EWO8d`R*;CmtQ70=IK&xK%njSI@vP?P+
zUY0GE0IgBRqmA4Z8H;|wO|pM(!I@@REgK3~Ws94k&>|Zzh51(5!V~DcCX*VVcU|@t
zm6YC){Z5sZH)U=^u-h(+pd)REY;_lX+~~IK%mnm1Wi38-{!49gCx{^5O&212Wpz|G
z+9xZof<(Wpg7(P+vUOL%yDNK>LNoVdGp|8pP?ka$e}-hAZi3{n?3*E&9g$VgQFv5V
z_X@~;SyL4LAY-!m=Rn3~5#;BD>^McT9>{wCD`u8GVH*X^lx#E-G7n|Gi(q0}w)`b{
zKO@u9)uve)dmeapa_L2wu$OoH0oy_D-h@s^`NEITa*_{opx`WzT@D2oIo}M-L-IKS
zv<}Pt=se;o-$2Whn>;fT3hwf;Xowt<2eT<5>mh%Kwi%xCYu6!jRGzsC#7k~Zr^sXS
z97=n5%U?KwN$`=2+yQ!A?pgriE8j$U_Y?9(hauu8&!A=Xq<lYBC;H1{=(QOjzewqW
zK>1&E7z~o9(+)LQ?$i!1LgdS~(Jh@&`8&ta8z%q#6*zTDZlL=_;c^Fh`A5hHX=YE$
zw^MjKQtnO9bd>x|EaoX%{x;Q(osn;#qf(4Ko=P6i%HMk&ow4$l7GQ$T$+@&j#>qu7
zFn?bDz8loz<)PcqN|5VX{<|e0Z#@JPN%DmhQBIbB=>?4o@<q-7O_A$qN1rN>qFr5@
zd>8Hg)8)@od@DoV_5cc*av5Dm%94Li$Hr{=!U42$<o_mvmn+{uajiW0&y>!}m)jNt
zr9l4jYd|TMhX!EOwi5X(|G>mWc|i?GsoXmS?w84zQ%0s-{zx4_E9CR3f}>LId<(oP
zd6yNgU6S|t!cw*TjRJJm$iFv3y;jblFO=2E!|5vw_3{_#7uX>8qiFGE`R86hX_U9n
z2kfrMe>w~cO*Z)~{r{|H`MO7;cvZffK7-OCuc1&@t9%EAL9WTug_xl0^86RTyCJ_x
z564aUTs!dE<a_7`d`q6#fzEb0a|8qJkURd4&fD^cPte&ZSIeN@CI96hNVj}3#pCYC
z|Db$QkKFdZ7SLXKKdqL1@>dtYM8BM|6P*L{+3(=uUHNY-;Ql?i9VK4|<zcin9g^G8
zGBqq8ZwKgzJeXdoqjF&!)bGo4yTKcipDD&5#^sx72Q(r7`4-3n`8TvYPRgBVpF1T#
zY72(OL%HoWG^gdM>)`N=-0eNIX65g{0Z}_es0G;eik1CnIVcP#!E;o!QEtyk@dm}(
zofQ|TxXVScKmc+`@xh<?qa9W_{R^I}qKQ6%;ih;a11)#OcnMlZ6c6Z|H6Dr|KBWVJ
zr{Wpf3m;V!(b3RL5k!ZEV~V2`Gw@a{rn&S{By|JyxZ+bf>G>+Aqwv={p_rt+yPx99
z33zx?vHlwVBL0f#T3`k!_I?G0K*d4Y><1|#XCM-+sG0+j5XEgbkWj^j2mgIWLE--u
zoI0fl%!B!G#dnk=i%|4N!HXzG#P5KKR=6sme@1b$5ZEz_ns(Sdt4Psc6tRj5XNa6r
zI8ZV^PGJzh;CaRKr=bw9IAsTg1Vsu(k`onabY@Rd7_MMs$qELxOt{9aSVw!>6vY{O
zx1}l?P68%PkyQ+tbVbCU;AJRU0|A<;SVLcS$x<X!4PLh5fj3BwVhyeQxr!ha+|E-t
zQ&1#dF_(TU1&WycAccwt^Wa61VwOs#iWNVW!;2Edqc318Z5I`RbRDKt@g-G5mnkCY
z09CGdUIDZU#h@n)Rx19Xzi5@Bw-Fkb6vLO$s#bhRRb4fTG+!vxDr^scQm62}4NLWk
zYTBbUD3U0DeOd8ODkK{fP7mPP6~(KMgV&^(n+ETjZHl93G0>}u<pNl0Q3U=1W~)N5
z70hdjXgYCSR~(lE=7xerH6}L||IUFzo1$bI3bz#R)xco8;@e?#b|?~pA#z(0`Y#N2
zDwa}pMwcROCDgkWE?PKxM^R1HdOeDF=<^!A3Y(-KCi)b=vw+sG_?M0~0}30x?(Zrd
z`5eyNQ%u!@H>l{?2opmJFS;BvtXTOX$cW-~Y$_LwD(-ZF+*e3XVb;bJ|IiaNuK4Ch
zOv!|zeGkAMC~kEFWm4f70oSG!H8oIwsF2twaXzi^PlTlz#b@1snN=*;pwmwIa05E+
zl^dUehJ(_FN<|!%vrG^t<+hhWoRtUC!8@#6Is;3t$}viOyD51Zbh;~7QYq{aWfFzs
zJ(P_vqvffzbYg%<mEve9cqw-(Z7^|6dAI^H-pX%JqvfNVOU3%fl|u-lF7Q=mQ>Et#
zWvDY8_EY-o2k)fvB;6D9SK6;ZXMl25E<gj7BR_)#DPN<Kt6=4aX8;zW^nC_X5~_^9
z3-e)0Hk}?%Ddmr%6|PL$LIv>=%1pZVcv^XQF3=*C#$~V@r5vIhTeQ+j-`qK)^r{DF
zj540e63;4q=~NV}6gi-EPU)Wn^*H6TX#hR1%(;SAyfU`~tpufyAHWio!4zLgQhpzR
zSxZ*BQ%S%Dr4RDnwgoB5LJBUXDwk3nWty_R4EpKHL-SxTL%E7FxtU5XT_em=Mr8pl
zTNz86fE?wMbU4aYCjSl4JmpJWP|sJoE`dUUaxMp*h05$pXcZ}cpx=72GD!%#CCcZ-
zfWD|)(+{4lRM|o?)iR}Q0{Z33umE6JD7R4!dZqGG1b9`-)tkV(r2O+`XjChI%Y}Z8
z^1~<5s#U&s8-JfV<<U&cQ@wJ@t1!`^yhMeFmzBk%n5RZ%Qx8P0DEF-eSd;Sib_}9f
z=@<Zot2SjlmBzIwmv};>Rrz-&M6W3~(<}D6()J}<H<U{HhQ&?ghFu_S%8cbuyrs;g
zEkV1oaTg|`L-}qcI&Ul8e?Y5KnRN<aUCL~VI&~}0@c`DVY(D^zKIM;RAkweg6$!Hg
zO56VXXx>#8--paS<!A>K2bFFw1A9pMBBd6Gl`H8mIif5*4*gN(XTDIpuY7SmT4T!9
z^coyjR&y{x6H4tO%*+Gjj+Gepq%wu}MN`WA$U7`}sBG{9^t3X}g3cM`#1V{TRyl0z
zg^PBoNeTqmt6GFmbWp9O=hsoSoC*w_R1UOSJF8Nhq2Z!hMf;*ds#ht~a9Gv(IY3=i
z&Y2)?D*lV$xvQQy2JerkHZFtr9;&J-@H|y_=u@pnRVgM|@KWue)5$T_clI`Dc&qko
zh8I4n^<Tl#ag{0&OkY)H67)}~RxXCVpK2c^6HlskGB6kZs&}dIGC<WD2rmLvD`}e_
zq*_9I>R{FTt!Ra)zW5NWP*wSpKnYW2{tf6;s?h|fhpWDN44o0G*|hn1{!XjrQgkm;
zb%M4zQ7ZL0n2%OP-a_k)Dudz)F{;&c@#m~cSPuPIRU0kA=Tza(VW4rU$9Zt(yeh^E
zcH>nK8bK0N-3P%-RJC^jI!Tp7#pB7UL>CPAf@+l9PEmQFFu}GURmG#XVw!61m%vU}
zDei-0s1C58k*V5A*~cu^BppJtRgLt`svOli3OeVi3TT6$r;>dL5A#*u&_1C+HJ_^M
z3spUy@To{uZ2@$#N;!qj64l%jn8S-IdpZu4ss_U0p{-1H=N|OSRbP0bS*7y2gVrTg
z1U(his!~d^*QlCbh51@lbvR7asoqmVq+XTm421^Oqy7-Ntm>rDTcc`{0xnln&piW?
zCe@}wINGfGdj$+$RTVr2g%;I|@#t(-4N=JanoT8M4CZy!Yae20H&o~7lS((y3DTxI
zHVED=RmN8sOuNd?4xk;XyC-1cw(3X+oat1h(#f_<wdgZ=*sXf*Q()gw3IBm!kIG>I
z6na&%F{t;ce)$otepMQkiVUcRHL!PAW&5HYX!lgBw?cnV<w3EAAypVf2ZmMGmjPx(
z<xk7js7e$B?E9)E^z#~1xx53tan;6O;l+gNEETamQ0=DR`lPC&1tL=_QzS$ls;*Gs
z^0Z2_9MChW<6mI9W>xcl1el%rJzE2s_Ua#=gT8}0m-g$9>PZUeI;nfhF*IkjhBiGe
z>Qz)paY*g{5Bxr?j;#Q;t9l*17TnZ3DP7{OUimj#N7U!+pzfjmUkB7Z)k_`)=27+M
ztx)$;&p!b}$J8tPVBTB3=OsG-`KY=7CFj&8TDE-ED<~v;LLFBReLuA)Z6{BvU491f
zSEr<d7ogrn+p9qJ#1*IqspozRUa)$Ua*-kGZB)z|s*a}emoRnDAX=x?zb%Eo;p#S8
zG$Yh~Vi-EDZrxA+f;UqAvk!cWQpYGUZPDr<X@`AA{V0{~#Hh>Y)qGZ65exlT^)G{H
zC9C(o4}}YAn+FD(qOQFKOBw2R%0gtSU#H)Cmb&wAh~%knQg|$1y`8GE3e@WzV4+gI
zF#_f<sh9su@4sqw8wWBq>S_9Q*Q&SCAE-|K%S~X{tLIT9x<P%OkJe@NSG!=oQQbrl
zv?lfFr;uz`zZ;IZysF+nFU1!1J5);0s@}U0%iT5goPJ2&P`?-fXKtzo3o&bL>L+6`
zvRmqLI{Dbz)h`sHd0U-8@7+#y5`8?OOa0qXpmnR;DW7~t{i+xAd(@&lVE3wLJ)qF9
zUPtTlfZF}P$e)@S3*J5T2`xGY)f=ne_K;dkVbfuCEA6F6)br?vG^%c=FJ;_U|4MfY
z#`dWHr8mL2TJ$dLPN)~j;M4=PAP7@BsV-WJ)<gBnbYoyz?L!&W8TGokaCBBZe-JQs
znq;~MXRo=j5j;mtemUHB(j2BEt+Qq)#oAmnau<+8njJpZ&vF(vc0=1k^T=C1b7P;g
z{YmkDZ%y<ifcR*N{|B|>nnRSB_thNf1UaF}qHKr1#!m#00L^!Fo(R-T({C(DWBd!e
zV9mT*cpIX*PjCBEn(uPpbhzf#l@N*0-2E7xQJQcO%tmVlUI6cmX3Pg9Rx@R*hrx52
zH-CfqIL-Pph$d*{qYzEhT&5FKk|u)!U@4kdiczO(KBuzfG)=VxtxV0XI*c|;^S^!Y
zDO<yI2UwowU5e%BYnHwZ?+Y}+kDyhkSsMw1MH(;Ks}yU#roVBirtd6etjaV8D$p#~
z+@r&5g=U=M{gs*y`q#Ntn#ZMZrbhD?6(H4WR?{iDPGe1g!FtU~x^&T?X``&cWlb)H
zV4E~ubWCm5ygL^nS2Yo-uy9RN!~xiK%?~{o(hZH}0$R5;--{OD>1)@#N`Zh5&2GxN
z-`0#Yz(l9U;~NaLOH)tp%e$I^e01K^EUbdapr)1vGo+bEOVF?;UJBlbW}HICqnd6y
znBLcHr$fz{Mo5!CuGyObkqONgZ@}&Y&G1LSoYZt<17uq;rCCU~7anSwDF8jKdF2_H
zn9=+|HO;e{WU9)w(<c6jnYGtOJV2*|mQ9~}bJSXY1e%jJ-Vq|s+Be!@*G2moWg8D^
zvnir^SUXO8QCDsG4)ENx%tVadU7J8f>PNJl-Iy+$hqf{R*q+*jWa6l{>QD4~Yxhv@
z(ntF}t;5H)L6pVz)jkyhazfir^%s6x7G<MOYI9x&sK563T=*2A-AEh0VD0a8U<%Q`
z_zp;@HkCF<VcG=`F&C$_8p=M0YhTZS7ZEn?(R84l)_zFu*+}h?w*VTYeTt3FXzia=
zTYN^lTaHo0XuqfD?W}e>3NW$SQF>3tX&qTmIIo>c=dO5d289R{v|nBWcA|Dc8bp$`
zvlJ0c(O#!gqg3q!HCk!fwS<zcwWWw*DMP!L^1qqd5K4MvY3)9Qi`iNi+EeCen<-eE
zt8J#=MV|JW4lw!J=M|W)0`2p!z(k>T_E$_ok@k%!kP>YWWs}OZQi^4kYwPK?RiS+<
z2AGxF^e8A)X+N$;>yq{@TM9I)wQFtzyGEP-DVVj|XV-w#Y0uGnwqE<{4d^#$7t!(f
zvUbxdkVfqtKaeY0#&*owRjp4RoN3X%M!VitZ8C))uW3&|0?g}J4e^I*)3WBEbxS*s
zoN3p-PJ5LOZD1HZf48*`k7G=o+KqC^bZK*`rlecDQ-!&>qiw_)X+e+HxdfzF>p6^h
z?$b6u3KRX>U-}?2pj}NX=Ur{wOXwWZF4n=BQLW2=yL9dQ6j~h9Zm9%sT$_Fk3KQC8
z^wNEx9o$6a@RQn&yTP2&hSMVZP+Lj01Jl~Dt*|ts{qqJoXSG_|aXIMT`U%8QcP$DA
zophI}IKo+%^ClErbe~cl_K;3O$G*clTQD$Pb@{Y6bJN|X#mil{fTFxdbW1)*%R_gf
zl&*t$>C)((c1-tZ92C8EPgB*Ik8bcUkmI_@3jp=ieLzw1le!5p?E35eq1SDIZs<F}
z1nNFr1oa?YzAHL|bszo(x5IR6DX4Ht7yc)_2-m4-BNCx|NEgRW>nt=0k-DvPiOv?K
zdyGQn(YoC)LgS3i>m6vs==Mec?X0dQ2;+^_RWE^JvhLeW5V@f9p-6Iy?hfgt>aNm7
zgEZYDPoSmi3X?Fx4Bb1`(96`Fy#kRe-JdJqcD62M7f6nd@f}F6ZuABm&9mtyBhk#)
zEqDOY0$m#Y5(;(uT!B`k+hPG)v96v%&n3FMKIput)6plLOLavQ+APy$Y=Wh7U3msv
ztI+MF<-JmOVh1p*bie%y$xFJ=sGP4_$NU~6tI_SS17@wRkv0T%I@{(-(0W}rt&9!2
zy%SKpth*nA(KqVu>EX;3-6vFt(4>1w3+!gynb+ayRb5{`%(v+F(F5PA8>HjRH64o!
zk?Xp?zo2(Rmq-V$o4U82fJmEeKZTHP=^i}-L+!ej4v2K<-nMN-^S15@I_P!k?xX^=
zOLvvZPP%pTDUNqXC!(T`9^JtzboT11DbUiVd*&QSzb<kg6b5vm6g<7F<7&{lr@PYz
z$wA%2c!&(?oIZu!VcpksA8SN6KoR6o-6j(h?&}zHZE$!@_ZY<}#&zLT?=_*@O!wX%
z=%n2cozyj5gyOW$N;~-(-J^UAbXIqd&Y%wZDO#r-_31MpPWrU@=ycXUHv|zE{RUe6
z4(VGC0qn58g7PD-dec&j(@h_+4GQl1aTaACj_7B;fQE<O{}Wj9)aTImPLApqQQq21
zFRO&7$MlR}py92b>4X<P`VKx|j_d0v3+<=xEyZ|G>bHl&yuUtP0)+s*mWsXu^{>Xl
ziy*zJ2<pLl#$t4a=xe`+NT@#jG(|td^m8cRa7v%?8qmV^i~j~QLcfoamZ$XwN>oJZ
zolM|G=|z;Fi`Ls~0D4w`jtWa-_0hC0pVJ%Zx>20Il)g@LUOzSgk$C<3<rqYQp38z{
zqMr8&%qQvBI6@>@FQBu6?SlR*ij}A6#XHbU)f?ziOq%|;r(r%_-!cK$GV}{xf?}qA
z70qmxe$I1{%+|j_#f3TgMO2)Wt9Rdl5$5S{)5|np??W500{xeC0jy9z9SPTp^nW!#
zuUOytJ?xd}?dd&#(WY<z1O`j>oEOkrrk7EOq+EY05bjs#U-%6AmHHn7VZKUlq^~$!
z(s$75yjuVCTqxA&S+v`()qfZSy*mAoAn4WW7uSH-pnqZr1~2Q^u%XbX@2rE!75(o^
zV7E!{LYIY`^|r5c5WTAZio#4SdXEDz*s4F*2E}Xoy$gVLUB7HUI&bLLP|)e7ew6Yn
zZTeZ-*4@%q(f+z!UrLew4t)y6Bya1ZegLmipFmfS@92~1@$b=pngR>G`oO=@>eC+(
zpw+JrvmHcpK=0E4{k!^b+NR&rzwka32lcBgKpWDpr3l)v{wrTNJfeSA1?*A1k`}1@
z`sRm_9MgyS!^3gCJKfxx(7$*CK0VM!(+OZw|NegHP3dE9qxDd~{3+O-)^EH9ks1Bl
zpHnI5to|*!2x4c5qQV+`L$o{WIv7sppwrQyc^?Ly3~VZ=a5fyf1AQ06OL+i2WLQqI
z`NM|So(0d<aDXBmZU#*RP}~iUpMe}Pl)Qo=c^KMO0n^hk@g~%d8ltzu885@(zo;DW
znBh@MsCpa99>br)$M9GIu#X#>_CwLvaOX*Mo-q8h6pDU^e>cL!NkbXA=5P4w9$Ep0
zogY9X&=8)5&LG3(6krD%)|`a-5W}|>AfblY9WWnec)tMto-)Mz2oi2s_ATu{BMg5~
zs3FRbL|eXS!=Ln6oG}b$z>63IXA@dy4Xq-G#2QMj!KZVEr5hj_XZT<XTIUTORL~u7
z2s#7F1Vb<7P7)2wH=&SZu+^e7*|3?)MlKjar07gBEL(#aO*O2esuf$B;RCwhmu@gp
zjZ}uAoN5I#4NGWdvkWOZc#&<eWx-&M;mONT%rz9y*ZlGf>6bC=e8cW_AO(idFh~{}
z43rr!G90CCRk0!GaqvnE3yaWs(GX9uqf&!&Bv8r>>pzCQa+^US1hc|mPdSiE!!5d*
zUS$ZU^ZX^lc3RM@4PS_%QDg9;4^h?{lIiA1o#7GsMqj<5koFP{1~cVcFB^WAp|jEO
zA-(vn7^*2J&}8UMf<m)l{#iJ4)v%muF<T6ylOU}ITOj>*t{Fb|gNf^g9dF~8aKqqV
z4sz45gYHMP8J5#xaLce^7fjqXoT80br(wh!mbwi88;7IahWGl>x?^~B1tfb6?@+R}
z*YL_7NcI`tqqIZ6!D#|hGGG|}5<cBEyhUf;dxo`YD!dppgwSbY$gpq{o(>z9B*M~&
zp@5R%qlSZY^to?X>~kt(sqHaJ>pU>zZULDz?Ee62Q-&&fr#>{Cp(^cZL%<TK%@~rs
z;MuHUfC8I##soPWv^QQGhB*i0_UB>1(U|xpcuq#q%OK9iEC&qQ#n?v?uS3RV9|7gC
z@es~P3tWxAodwU$SZAZ+T6ZHe0li0z9TWudFtRAv<Y|nd{l!t^EPbKG%UDYJiDSn5
z$?(bB$Vfn^k8zC3+KwBem_YM2+P?=&CyXV#0p@3He;%DDjgNYP_#1D$3B3TLj%ud^
zjXS6^BgpvMC0Z_mjjvE)N{Dfm0nkw6*H(0f8wV&{5@BSM!>5hS^vjDjUZJh{8RJL6
zkc=^MP4M@e@t3#2i!*-1hu(Q({UIo%8TpQ|lx|F*v}lIWcn}6NjZIXKon_p>#Hh24
z-?6EBF~`WDH*BtP9=#g#jFZD4`Nq%oK(xR(=LuLUG)_?MXOZz1l`R$<cT&2p#Q5{4
zuyoN_NhhCD<BmVzTAA^ca)^{0?H59%!pJrOrP3HCgh-WfniMV>8QWp6+NdzkoAddC
z8snBZP^>j>5<;=g_&SC5>y5A7hx-jiK|7qeZ2XGKV;YUYPXgwOF(M7ECL`->kY?k@
z3!#41_{K_%sm1uG9qhIm3w;)5b8IWt!Csqj-EKhMGJZ{G$aZ7&AxLx>*HW_LwsD&$
zTAjxAq42ZI_~R8ob{l_61@De=miEj&#;1+|rPsJ}5O(^E9;eajH{M){c^NR)Q%d))
zabp<N?-?r}!qA}cwI;NNj2mqfJ{vaT|0m(sZ&cI9bkvwb&%%A<82vrRjFV3QZQLk|
zgQW@M3R<Zj7;jKb-lTD{8=RRkuKWdL#+XGRhFRm-5n$VyF3_&g-gLJgGwEP@@;tyC
zP0Meh)5&y%s#}~*E7njZ&c(#u3loP-_8&s@u*pDchpS0V$sjk=`b?m?n_M2k;1N?u
z8h9S2J(Q>NG|hhx&Kx!ULE8c^Q~!@pKW2)e5TduKhjv&#Cg(RHdEB((C?tJNIyyO@
zFxgW9n4d}T7sWyXOtVz46lhAA0d|lnh>8S)P3x)JB*YY72oFO|O@Biq%(PhskyECK
z`v46$y-Y9>rhQw0ecF^m5$;IS>+K*>roB`I7;S3%4CIVS9}9&T)4eu;oiznfXd>3s
zif3Zuf^#O1F8~u~T1{1a=S?Tm!HhS>QAjSq^f(h5iKgB(w319NhtWzlouG<=3nsA;
zQ<7rhHlUSidiq!BrI{*y_T_SHo+H4@Hks&Hnqx9Ohxy4hEqoll<eA>NjLv*hdl|eg
zFqJ3(QfMlpOjeO;(LVqwHm#u0dx`1oBA{F}U3(b@N=*V5+$=M_Qi4{wsjvsU3e%P$
zv?@&uI%`&$?BZbPlF4MF*G0AIDqV7`F?~*7xTrO~rhxf6Q@0gEsW)XWh8GQ{Wwa1o
zHZ3;8V54b}R@y5jdkxT<Oe;2^v)S}D{UNTJzV!!6i>dQt@LEkt1JJu>vZt5Eb<;um
z$Ky9l=JQavWeW7LL8jg0Kwn_!FzNa*wA-e+anSEHJx1k9T_!)eS=DX2NA>M@Om?fG
z-(wQcy@_6v+gDKUGwsiXLcb~g5r_<!{-!_6UDI~T0o^lQp*p!i(_;(48!{E-gEwsY
zl*(8}OsWAo;g6bl7l3x(v~La!j+u6R3Nmi`l-9vXQ^7juPnp8$fb-C_o}yCIrimjE
znK8vr!ThZ0av0{x&io8rD6=;|pvp%Fb0uYq9L<|(`{86>`Us}W*<A1_?7El*E*SkG
z^G!U9wgrdH6O=A;H3v~x$jyA2&in4>#lJx2h<RrUOn8`iRL<gQeuj=<N6jXJ@iKc*
z2=bWOovvMYo3lQLzdq*Uv;jVDW^vH+H7`j5?}S-Nx9R-MKD1_?G-sZNh`;#}N@Cgq
z%(iv#JJ8Id>}!yD9etlX*!&i4Rzu8sSCCM%gffO<=5-EeoidB4@HyQ4%`J3Bn6tiz
z!fEq7O1?&#f2W;fl=-p<-bb66^k|(i-=UK37_+Sj=FggsHiN{P=l_90oU@rPZa_26
zypaj)^X5sa0*W_(M|<o9^Ui$8B${Q(&`&bIJP(q|=Cia_xL}^3M<vA^LgBAevkRp$
z(#*Fep`LDDPSNfRb0noPGR^KEVScmB-%%M$ws}nhP;$&-U+{9xHh~v<3(QV*siDwZ
zO-Gs{GoK6nVsq(JkSQ@&4#JCz=4raATWW5n6MmVw>MB6X&6yN8t1zz%1gSK$YeA~a
zukD73OXiDo3aB<)-bSm&-19sv)S8oDg@rovg?BNCdh>5K+8s2QQ|T3a*<4FG(MEFx
zEvr||8@oW7%yn;Igw5t96qLSd&V3PzE#|fK#%MLK`5De!Gndlhe%-u3AG{mp!)DmM
zX?~ry+HK~O6cxH<&Y2H|cJqOo@UX+2LxJDhW^pcExa~A|90Tbxo4cUcZ9Y#2;5+7#
zdi-{J%<=RJ?lpI+pwVX@TmTRI&7HJi8ZgJ+2DxjNJ3`@}SwdI*2F+4`kRfw$H^7F?
zyLJF&#9T<%qesnKxiEC!JSP`=V`j}0kNk*7&3p#0;sq0CHKl7Gn0L}^WYT<mKFE}L
z2Ssilnhn3gi)r(UDRj=5z3Il!tXaPV3U-!k`uo~jey3H-!Sa4Hz#J`m+R<{dSUupj
zv&G#R1`k_K`wSK>wH@)p92~JcO3`)?ix+*k#M82i68uLk(^Nd?W#Lh!*fGnlRnYdf
ztauTfK9+S<mvr3X7=W4dwLC%PyeBN@>9p@>dG{{JNy|=(t@>Nm)4~v78KX04prwhv
zBM@ZS6^2%@1^<~0*ddkyx}Onhsec79VHPbVHcwe<=$|iyTau`dFv9XU#d}X%zNV_&
zNQ=}BdQlc0)!If|JSez%#^UIUzkG}(k9cP-X)WNzTArlBxN{ay7x)xs*;I;=owppI
zcYVC&z<nxdOR!v{S5l(oX&*3?EbWwKO~yZ12JeF9OFbM;v8-qZFV&L27BFcRK9ww{
zTL#Gc3=6*%gUPh)nFcS*lDY=GY)eQ5yw9<04gxRN(mnz&@+_-p*Pm~BY%TN(EblC*
z4^J0ba+X1($P(EFnPN+e1R5olKPgjw(Xwa+8l{%uZ!wrMi*GhS%Pscw6Rog(wFoek
zma7R6sj@h~gjS73PPyV*%ZW^g)LHx}2UKsFcorfJmgl@+;j(3+7?O>aUl6vnEx2NN
zdMk$3WN{T>*v*#OvrxQh*-fG?mhfJ*S}oh@cI7q8Jt;j}miID&cEd9MDMW5sYQBR{
zZ5C@4ByU-!!!T>@mfZ_5qz=pdMzn5Q_KyI%(^4*jp)QM;JJh=^ZXaPtwmX)j0(jG7
z38W}vujM&EINWD(^?*jdWh4i!0gLDfVBfV|)4=>a%jYknbI?+`9{NL;)tA8=ws=#R
zZp2bgOW&wvFNIj|TMFag+L+}sEq&vbr&d5@!Xh~Xy$6;Ix)wQUv+Nj!r724n6XqXU
zzI+ZE)0XwL6PU3)T#VMNh5aV{wzE170mj}cp)wE$tBN9Vj@HON=s8&jenZRI8m)$&
zi`8W#yf|d7y90&8);7BP>uN2dbibQ5oHC*A*1Y#&{)pA)yagH_Ry*3}dRixs!QfHr
zo}U2fWqs2P<d{`RSIfPv6?`cASU;G>>;+oGD9R9I?OF><!PbVmuoPmAqbO3SHQ+aN
zhFRZV4v|yVCC4z{a4VNKaS_&NIwqaAx_5yWX<cul$mbcW@NwwJShuZ&%vtN#fv_8E
z{bK;4=d8aU1c|f8eG78ln(!SQjkoqtrX#@`@HqTUwEC?DNwSu_4bWt32X$Vs+S5)T
z#TrfTvQ(>*j<#vmE$3h%-MWc_G8xw0ZnTlkwBC6Zidoj;ixADW3g<vE&-&^VI`ge^
zD%&ow_Ph>KXuS{tQe@4d=x?!A{t)9WvDV9ga?yH&qWh&*#<Q5NGV8%-&{=M+lAu*#
zoktm#N^1;VP^hvde*@kn>-q*drBz#Z#N%&JV-3FmX07!YMaJr^=T<|e-n#r1bT(L{
zUWdpP>ua~r*<{Vx43TE5=bPYNwQi!YMvGO`iZQiXH&WQ?{~TR+T-H?=x1rfI)2uAb
zUTv9KD$m|~Pb|x{)NGh7+rxTfBPt?8_8!WRsSK5k>>(&3AVY?tAc8DqzTXr7oX@@I
ze9t-eKEHAAIp_YkW|yc0X|s!_vrp}I?UeB7u)D~?<aOF@rGpLE?ZjQQ<ms~8_a(G-
z+htjxrpIo>F{tUayT%8(VVBm6f!?$eg~4v0-NRILcgt?y+mO6%_vAYG)NkjMi`IbM
z;!h!R$L{3201Vn~ehR$1c00XbX~?ehNhlk(`#lXJ_v|<aATna7_yNw?M(w<uAv$K4
zPaD{AyRKz$X2Ncm%HAgJR?=#F%5G^C$h6&$L$EYsXUj%w)=o!B)HypFrB)mmL5*lR
zGTdoP@5ES2)uYagI(nkHFrMj#T~~&w3oSRsGeXRTJ0rOk$`0BX%c;7<gVDPQy@wbJ
z9>%mCX8c5jlSddT+TnOI_EBQ^D8s252rtHZs?|Tn5Kt7zo57`pu@B>;PoUeEA)-u&
zALHXvbRK8ynTM7?!=Ebt0~p6Bq7caVHv+gIh7%v1!3^7D?NA!Rn70Tdlrh&1OJR(#
z*8mJ>yiU>b2!=Q9$s-y6(!wi>A*H=oG-KIcXvHuJXbTz32%^HPI7aOfC_TXl|F0;7
zaf#LpiHzxOa3+aytpesxG0bCdG@0Q}ai0{%C7UOJsf-mXU@47JOB<hbMhrz<GZ+pn
z5IxOsr48B{MkhVXG8ySN;7k_dD@w^`Gt6|&<S-tmokJlbX%UnbF`jq=@M1<3t++}U
zPf|MJ0;9wayi&#sL4cPtHhzjZtYAbm+8|TO_?UJORg6*kA7Ist3R)!9GO`+=w2o2g
z3f@J=l2QQc85%aUH89?ypW-rOuP=Cwj5K<7USYULqSeG`p?mBq<88Vgn;GM+0JJd1
ziy_j=*yRF|Ym9x}FyF@5DW;8VJHtl;yB!QoB1YKBc;suif1UBxYRGgkzG=nGbTb?&
zy4b@IH$iDHBVr%s@&;oeW$tb=w$j?JkKt<%a*Ls4!~AVVCOsPZ8Qf*S4KP+x-v186
zy#eM28UKET&by3%(&$LV5aZ29&>UuDP%Qc$W2Fw}M;KEB@M)B>xCFd0Ml-D!#u@b%
z7@S}<O5xfhV|)jcPBHxU!{9W-lWN{)7(P_9JImO#7?N|0`?OVYVD5hfosP_(Xs_VJ
zludv*Gi@8dv$-%&z7B0}Ob;shaAzj3gZYEZb(F>QV7_o4twT(|B8VJesy;-^lPT+f
zwxi5LTVc?PnLC5dW6Yzwpwye`JOrE%bM6j!zRVlXgZMG6`!TZP%uVmWf<H5|03rd*
zG}`3`+L#CG(Hq39p+$Ev^FxZJhA@|&2O^YNOKYbvrt?GS3}<em7eNHG>UXpvnLC~U
zK8ktBnQjMW^9($UVUE$NFqYYU0`NHIyH`O@FtauTaFXdN2Oyr=R|)SEn8&E9KauJ4
zL+xX>9dXccin(12@nq)j-@v~VX3H~Zr80{(a3O<vCmiCZnI5zoKEv!bz)U9dk9Xj6
z7W39xz_Xb<DcX9L=}*g%bIgC}bA;!aTc3txE^{}Pq~tN*rEpvU^98!g3z>;g&{@PB
zvF!!3m>FG+;gv8$${<t9Tt?x`GUmhCaHgEO)Ey!fOx;TWRx+FVAz8(Ii9$8i%&%>*
zRKxt?97JlFC6phmV~)(h`-@EJ*Dz7fTtX*-8kn`wz+GZmRzUS-X1xboYh-dpDY1Bk
z8IggZH8DF^0&$hO_P>H(rig;KEzBbeFtk=?|2^=oF`tcuwl?PQ3@o)XEtL1_VA|8=
z*U3CjIf&~_F71Z9m?^RFzMIJ_!H{~G+EzH)%TyeIvK!1+D(t$+^ik3|&pu|15Tdu3
z`9ky#FbjHM=??Spk3j~Rx@UmD%e14w;}A1&Jw%3?Nw2_*5$5XEz>P8s-$UmZ^Su>l
zjWZXm#|S5wzh=SG1LihLYE3eSp97g<=8%?Y=6)*3nPIMwQDSk9d2%Cw2Ut%z!Jq@n
zn}L=iYkdarPONi3VT8^s7OhHLSg%v|z?JprOVH-V%6$#Qoi%&|!#>FJn?lQjRWXRx
zA=a!1X7n&Ci7v(?EC!u`^<*VJ26B|;{xUkfSc_>LVLQeOc^@XcSszjI(T9~43#Kot
z@Hyc9SUaiO@;GY~#kKue35%gSfOUK~0D-JY5&R8eZJdMMU{=_VXoawx=p08VOG#V5
zFxJMk&=Ssi>s#23U@d<GS|VA`jKWY9%a<a6u{PH4lW-%BRY+T;6D(6FS|?ebiGh!2
zoh^l>1l9xv0TNleKZ2T5tc9OKGMV-CX>_KrRu;i-Dyxj%Y-y~g*P%0=wV7h087#Ma
zkTa~qd;l_8OK3Zp#rh-{zd<%jbPptlW!rofmd>)SQCRXEtN1c}JI{K>5o5|_?T<n$
zk9Dpat$fx1)wvY1$~)nA5vw;GtzuRIrN~NHXNq9=0_!(A^i#_Eoi2|u)_n?cSFrw&
zLv<xf83B<h*5mZ(sb;;o0y=A0>uvEcQOgP#2e6J+m;+MJiln?l1M3eeRJp|Zq7{hC
ztip$2sgbqeE_hd1Hwu7jVy&S)Tr(>?5Tu2bMZ4)%RuDbDud(*F!EPICK{+}*S^M}f
zc%Aiq2$XfPk{4svx>;Le=>F|tZS{ffUY3M*vNu@cv?c3f$tZz)i*=kfowr$ywD0L>
z^<dvLe}MI7FC4wYDx@suAj?8=%pq3TVss9(X8YmxJ=S|G0T^L@LB&|3Eb%{Rjj<$D
zyg$xbOhuCutgGkfSkrx$>kc#@u>5`D)Fi9h8Hj0C@4HYl!^%p5!?P^iU5s#!mG%ov
z9AKYVhE4}|3@v;d*;WZ8o!PH^iDA32tG@@_l|7F_5pL`T+Wot;1$&_SAiFysI1hIB
zZ@?X9KZ4_zjQK~{#;4Ki$)1})?@{*2Y_z=CYm{*K7<-hec)i(~Vh~^UnIFOPW54XP
z>he-s*+zIB%zli5St0CSiognGzf^=)82g<$w8Gg@wQx6r9rZlsCz9RY0zaeKZjKO%
zVSl_0@L2W;1wiB2<FBFf1iOnu?kCyhG}?G}ARXOFWUupqND}*ZD)T+X_RB|SGW(8=
zcJnFhRrCf;W&fEDW*Yk{C2P{zowU5oU_V0l>uL6>%^1oV_By%^ve<Z_;QD75Qwk-A
z{n-L|ah6?4TZ?n-zcl!H&a<2SfXih+Mi*s1`+3@Q6|ifSkSt^yDYR6?4hXkFO)<NB
zEt)0lVkgL4V6UWHb{YFY9XiX|pVIohg8fVxNG1E_{oqxxKl}+ER<qZMAX3BjI1Ez9
z{wWZ=i|l*5AX(4;mqITM?DB8HyTtzEcg)Nc_H`=;*u-AF39embubignK{NXt9hPlj
zGXv4v${wbD;Wc*iagcVlb2&%{doxW?CwpHv{JqX@-UIVp>_b1pU^n{#T{%7M*T%rR
z!M;Sd`%U)j1+@CuA5PNc&;Du|0Jqs!yWmqld(96Z1MEK@&=;cau$yS<I>^qegqpkT
z4NIVOh<%XWP50R0^wbz(o9P)e%0A=`FUHtUTA_QK?Mb<*3HA*pc=y?jZvimL-a*wW
zQ|#?aAUVx`@>@vGu)o{}$ys*ZE%4^p3O0U`1DqUMN!lDazC&=>i4(>K-kDQ54&uU@
zq#xFmlR=MOH_kX6K6B@+l0njgGxipEhd6%k!Ng(Cx&071!f8%~h$n|R4?{b~dF3Mv
z!kg1bZww!f{qF$yauz%Vo*(Dgr{M2#j`J3X_}e%SHNwR}j$a;{L7bv3Km>C>ZNRWY
zIGMEe2<1%j01V?~Q&23NGew!CNRDO|I-@u`dR0Vou2P6KhV$BA@FJGuPvzKgoE3=}
z%Lz_7t;kMtJkEo}bJoyPDuJWi4R|8Qmj5PXPH}AOp(dF#OJ6HU;an(!!>OECz5+?(
z+}#UaI;Vs-{281tYhmIHr@9#=lXJBO{$_D9C>4{<G3|ugIh<HJa(kZhD}6yBmviiI
z7|i2XP6Ck6DJN3E>7)H`A?GI>xmd(`(FeUHoC{QObb%xEM5~l@G!N#>I7Jk;E9dyq
zCa8kb6bRjwoTWyPYEBcC71VHoXro`tsiW{~9cPCOx-W7ZmP2(t=Nnq-H*hBP@Zu6@
zFQwNnbKEI--N>2UK#%1soRzb1|0>5uCy1Ikj%=83;jE?LVJqjwU!d(8r=F@t+Bls-
zu++|ZXfJr3oX}H{yv~W61L@+V(~7N|^Y#kp?%^D&fXGeGG$lg&IA2ha+bvFi6X3Tw
zp|q^+=Y0DdMGpoz&i0VG!`V(z@4K9&OK1&o4sHY)=Hv}P_dSjuRa%U2{CyxY%IP-&
zKgKyrIl&3eB6`K#=Lp)M`vFHv$B8C68C2jn#kq3=ZclS;S1{}ujyuISW;qFzo15b(
zG26EJ2e>@CE*-e64={Qs?h-2BaOOHc1mePNq7<DgcR#%$-MCp)6zI-<HXXc!+<|`q
zIK<s$gvep86Qx0pa3^Tt<;mUK2y&GBq!UEExzA^y<-@(LMa!2fT?pdGeV(=!w&UEd
zKE`1Dxg$?wFag}@Sy&3<E?bRZ2Xmhp0WgHCqObdfatA5F9>)FmGJcV8?#N=;jo`LL
z0uaUhmfi=^+zeXh#&EOg%^J&HNfDel?wfXipWwb$0{BU87OlPGxtqHonPB7o5(m*l
zZrD;Vlejtx2_|!oRREE~<<N<kRIby<5KZIe(26ge8%Xuw8C+2%Msb>3>jrI^+!bGA
zO0u{|Z-8WTL-zuZ!(HPG$+O(Q=_#GdeS{(*d0e|1h~#tMe;&gv;MzW;5LqF&my+8>
z+*c1kX)*Ut4#rf%eVsPB7r0}E=q%%YPlt@kx$8fJPZiueDk!bwibW8q;ua~OyM~)f
z@w!^B%SYhVaZe@ySI<34ulWY<KU8^hiL0hq>1A$u3IL7VX&aSYUEyA&jD8b$IqjdD
zxm!FzTDY+{p}Un^wE&1~+!2cCw{c@80BGk9d<b3#H;eXQ*SXybpu3CvQ7}Zhxy2Os
z>fv@!Y`K@akJ8{bxVan{yv5BPgZH<&A8iBa=f2QogXjP^-43F6xS!IUGss=C1EP1i
zeN>$~#QlxdhQr(^J_Z@#PEgQulp9COu`zBs1+K=qIXrYua6>Dh<pH;v%AF^<7q_8v
ziko~Noip5*DMLTY4N6CAj{EJm;2q%I{DTg}Iq-fch8jm6{v`))0G<=2CtP@zdWgF6
z{-V+wH{SJSK)CZVs^QZ?9=8hGJb3FPVCfL=YkGno;l<Hc3p{xV3E&;&`Ow?ni|0nq
z>|?x1%9nccdS8bYKVFm*TE}^>e@6#${CQV?MKgfsMvKBgUOEN%gLtE~Fc0Q2?a>P1
zZNC6#LV2IY0w2zEkAW8vytsGKisT)lg-H~TMbG7Eo>Luu$ynY1#fam0d;fwLCwN~|
zN;IB#`9%ycfybr_`$S&5C)~Cr@gAqZ<SE{pQivw=swBXt@S?>~n#Nmq2x`)KpVJML
z!Q<00(bGH!x>L{aN*2SzOy0Bm(V4~Dnt|&ghgY}+@Uy(CY{1X)WIeEZp0~amlDRw%
z51o0ur|GanAx}y%_#zwc-P^zy^WLH2%@Up)-A)&H^U6U=d2cO*!)3e~%5s<UHl2h>
z1+R`S`AQytKS&jC{sIi9n)g#1NDc1?Dwe3_{ho%osN=mrxzLNe?UXyH=RNb^5hvbl
z6P&rkYxxd<%RF0pF=!)iVH-?b<?W`8Vl$6b0`o1r!5<;o$~#Imve$TvV`09Hw~Wdh
z+IgSML#u<gm|j(#JT8UEuJit&*j5+sSISLx^TbrJ+r#@S9;$nJFH>^m2Jgu-4Cy8>
zlmSD1yiK+rF(<cp_W1zb<~66onSS1TTY(?orO@qgm&e=yFNSy<Bheb>y+t3cxW}ua
zVE72nf#Un4JdFe<#&{dvgVJ%H?N8{O;Jr^P&ilLx$}&ITwNi!FB(J{;UQF>`pfZwa
zUQRx}F=u$MnISsM3;q|aIiAlxs5!t75JIT~e=AjqI`V&e8m>9<m0y78%72Q^3Apin
z=!CL6zmMww4)PxjfNl@In-1g<zmb;fhxyKA@Cg5vRuE5q(VMVvls~@-Gvmd7Xd#tE
zdh>lALaz`1RmuVT^535U(2wu26PAwiU+#q${``0<To2%P?uMm6{=5|!Ob~xN1-gUz
zWoh7r@Tb>;gz>dO@Hd?Q25pQZ_%~<)7s;QZeODC!X{ut0=2s1(GlqXYhO$?&{2SlF
zn>hZDSD^F+e`*TMlYI7HAPM}3>B|I({Ef7rO5(rW3fE5Y3%`KwWd8qN0!iV2LxIUu
z{*$!oPva+2VlAB?Fpka){()D~d76Lm8YHv$UbME%=HFihksN;e=Wxb$mY+>I;B$Ny
zT@mN`sJF+x!rwzRVR`(!?}Oy?m;DdU6!5Roi=>dhYYvjd{6;spUBb5*(0PHsfYNlO
z{1Gn<w2Xh6{&QYAKZprj1^<=baS2rNR|o;9;yY3mK{bC-EqFCH{`Mol*YVFjgvr0i
z_jE;XJwKF!3=RC}>jAvP?-Rn{WxfNI1~>AjsVe3Q|FSm*)5M>oZ2ndLb5wKM%wI!6
zwpRWp^&r>ye+@u&8^4CGz;=FaEm|FXUnh`G{uVmWeVuR1(L%I~@9z$~-F%<Np|pp;
zm)?=R{M#%{cOU<~a*XK~znGTvxB0uDg-Abtin8hh{CbMV-QoLB!rwu@?PuWb@>iV#
zV2J+*y?}=KCj?M^kI$s#>nOi?B}B&fM=rwOaekyt0}~VcZKcqCpZ^7=w;%97SAb0N
z_Z)?%Q~b<j&^FC~g36U=_}@`9dX^uv1LS}pjS8V01XHxhauj^|8k9N-=2N)GS<u#o
zmWv=D7{pc3PnV9HV1E(-?t)Kgo(>Awo9O-LA&5Q=nZtrWF?x>(N?KsaQ!q%UERG5`
zRRZB9$omuInBWlI>E40`^hoj%ocM2JAyCuH*iSH@!hy#Hj+E316!aWND@gF_GZ=5M
zAcJzjA%b;BK|%!|%0R*d{>$k77cNj70wO|irV1t^1+(u15heJU(ofNXzK3BcR`3CB
zlHvqBdq|!T+_;SKo)i>NfIeOjNLh*m!SX{OiGt__@Gwcxxd=X;61YdgQnDar8E`3r
zRg@k`6KuVVR=U6*1xB{{8G;S;ayu<3429h@f_|zJ$rLQ2(}`Jv;zht`3yMF4(j37j
zc~E**@F$hEo)gs3W;9peOR0xE!6OvQ$rlujffNXmXfa$UIDZtRNbvgC_(h5ZXRg6Q
ziQpYykPCwPKY_EA3iNm3RGHv=9duU;ylC}ZCHRaE*H;Us=R>qcFhI9|tss=%QFVe(
zT;a?`!BQuP)C=5CLrsI=pcmkm1j}g=a9Lm(g5(v!6)I<J5|pdJyDGS!1J%s}=01qD
z2>Px=q;;i09140(prH!#Ho*qk#kLEEjsnpk@bP)Scd2dZ131_th^)e>dj;v45WFGi
zrDeiRLHS*D_6eSkf$Cd=pXon`+!mZ~g35luD8;%41m!k}3<}hAGu;))mC!sSSVrF^
z85Z<3z?XZ1y{;f5g0{~97!`!mdEYTX!2?K+3xaH)0Y4$wbPS05f<F4X%9LO&?Nz1)
zT8i?{2-Z^=eOB<;AVlT_p(jBO2$y^dgAT%nhrn|b@=t;|3IFE;xU-N&bv`b_-JfF$
z-Go(?9dH-EK)cR^LcdqxjE8W7zD9OP=r5pT`C;J@ZSjr>fBgkYJ%wXt4D_h5_AGc_
z!sJ@$J|;||C$NujcP&JGg+sKI_7ncE6u9HUR~ymkFI0UAe*=UEo<S>6*hXvNAmRU#
zfD0Ci>HnvO2;cl2xKLqJB<3Pqs86I@Btp1@sx~5pU&!H9l(3OjlhMK$DzJ+YhETa(
ztZ;rNI^%?=>7jQ*_(Khbc2f8u)g#6WKcZJulJGVKzE27JX<MHxbfU0fits$`aZ-hg
zYcQlV;fJ(KPZu6)0WL#$)BV411_|>M&^#mD-3No2!rxnf$QEw-3iuqM6V;}l6_(IL
z;GA#?m6DzpZl<?qt}wbAcJqY$tl;Gfb18~gAZ&dbt`!O!#c;GpcyB4}mIxJ;61X7D
zi-m`!Lg#-$%7m;`7_yZM`{+GiA>4Qw_)1~P3E-=QpX>vv7GC}lqBX*IU&fefg~Dc-
zzbO3Sarj#=+^htzL6|>*&P&2+$}?ORR^&oyqj04G<cjc{kD#SVm>vMtSB1R^Xf+ET
zz6obqge%klwAqA<X{XmN{FRoU9l|BwKzEn$sb9hD7Vdf*qwf*EL324EEDVOhJHlkz
zO$`cXDq;7oFna`KNa(QxWLUVC7DD%g%F{40B7B+Z>_&w*cf!J$@MBjDVq7@i2dxR=
zrsWX1FSK1=j@}1C`yCLS6!snfeoE*`FWPD0LyyAljBq{WA7_Qj{{Wd2uJ|814~YK$
z4FCtxlRrVyQPkOpp*e}%{z0d+Xvv!xuZzf@a&E4opTro8n`rP)7<3n{rn1q4qW3Hy
z9wMtv2H+u)ZZ(E|ShSDo(2t1rhCq#{h)a3IqoPIhMDr2}DMNcqwCF54y+!|~q2(hQ
z`4~K3Q5(&gpQv^%c*jMKpJDR-MNXN}5+Krkiq1gM%k)YP5}m&U5-f6~m}ZEGQ~zHX
zyy!=IYK4j9*D?BVku$x^BSc}3!Tm^4^Hp?4i6Ura94$KVK9t6Yq#OWZMZaXji#Sou
z?@)R|^zXwM%Sq9NS1={<qCM+C5=6gHz&ufO^B6>uMDCFgIVCcVLUpp}c?bGtP>LvK
z6GT%*DRc>>iT<QIoOF?!3ZfaJ`@g}&X;ES{d^#g~`8q^0MGT5hWr=L((U~o(pxS~Q
zk&V{%XGO2wLFYM9mIFHTL|y_onlJJX0<J*xU>434it?yJp-7~?K=)s<$o*3=OGI-S
zz+Vu#)qz<m%H9B<%0z2vsaGy~ViHO#MBmV}w^C%Jf`cm2VY=9=MWzja*NEPs!th$r
zS^8E(oyeb7uNOt%JpuFeq8PgW8bqJ!(0NJJcM_^Ei#AXO#?~mR-3L#vh_){WzDZP0
zm9bYvwN%a7Ec(L&M2l!c57e}ZdMTBBO%zHeRN6#OQ#o_H=(TJBIz(<pc+n|3KM5_@
zMU6+%*(K5*L91J2pa5KtNS6yhuPA{oj~k*dw}W@nCVGnM2l_-i_W*HA6ii1TZj03P
zJ<5L3!^1E*Ao_sHTJDH;+C$BtsQX_yb64~#<)4N`#!`q3ix|_u-4o@_gR&9PCdxgJ
zipnlSWK8r=7wnFU(vHBx2~h)`Zoe<erP#y+ku8`;I4Rmmi|8ql<|PbmTGW0HGBcv*
z>A^TFN}<iwoG9r9C_NxnrUKv~?g)a2qxjQTA>t&qQ8l%*xMK~Jx`?YOR^TfB^;dMd
ziA#dvn!8y23R(xn_o&9%L!3&xutQ?2Z8PX$@j^OXe?-jmgQs5Nq+ysiCZ2l%o!;Uf
zQZZg1@oQ8`;w%1TIRJj*h)=;gE-sFP+y3HBRGkta{;me_K=By8(u2f1uK^G&{)!fL
zA>v1<*f&(Xo9_EC@t!>B3>Uu<MoYv9@l$3fjTFZ&r&~?@MIV^aV$L@ZjS+9lfJm%(
z<0gp2iRF7hPKfz0Lh_{8{1P0E7w>U`WP*6<^Dv(%w)+IUBysQ(Ou{K~N&rNX#rMn5
zN)dng3E-(>--kfb#0^i<snK+?g_eOC;tzg-rPJbT6c0Efo~FG{rue%{(48gzmwd_=
zXHnEPNBm(bM9zvoSq<Jf@yk>%abC=&;C!z5^A8}BCw7@dD_^|qFK8(eU(E!dSp5D|
z0F;RLPs02K@m-XI+UA#v3%`Z#GO<1bqUGW?s!OR5U#|wfQalg}V3oLY2$NVXe&#qx
zjd+;8$5$(kYsQq;iKD(m=SA^}C*Xa(c+V=pFN<sG1=J|k{0~~Lh;!^=w@K_kLEo$5
zSMnj*EdE&x)wUM#uok~ltN4j7sJSNgrleMz*qbVh+QoZmQP?4#hrjuq;#1#4<huAh
zDmU*EBW;G8OKf37X^(gjMV)%ZPIQsq5U-#O^-ZzUPiXatqt?NhTjHkMz}*(NzXH4c
z;-tGE12*xu_Q2l}U!>}bL9yprsJSb4rDW5PxJ{4NusE5Ho8A+bQbGNQSbhd%RQxJs
z&&R~y(T5?&#kbQyCd7pd_;g>qSB2IC@iS&<nH0Y}g6W<TyHbd8TKsPqbk2x(mtdT;
zVw+$OWah-%{bAyO<i-8a?I2lx52B8eC<c6Tk~~YRGiM2#-i9ucxt{@amE0wN-6Sh1
zP2(;Rd=G;MC6_48;vtdz0WS_o*8c+!4@(|v0sM$0`8a0OQ}XXKfFG5FQ@N9u<R_a2
z^qAxhO}@9}IZDy_NW3l3<|}!98C>&|Y+MiEaf#X=o&J(UdgBF1UL!Sul72e58zdQZ
zgk-SfASKR1Bmw_GS*YY^N?(Ub;_pCbxFm-v)*>Y74Iq({YqXSzl7#cAGAdf4`4#v$
z$?x<qI3Y0>!_rB~25*SQOJ2x>(gevz5_Bd?(x%}|l4J`NIGvI#RG^hC;a-PGisa2E
zbf!vp-=UQzN!<jU>5`3`p(R5iqz%YvNp~Q$oRO@ceP*U4Dw&EavLp_)am$w2(*`$3
zvWIqDXC*g(2014wq}<+lNg5UF=SoghpfgW0y#$i^l7=m46-cxc#VnLO@WVihB<oIs
z6iZ|duv8*(kAnFNlARQ=ER}5h7gJIu@%S9Pa!L0r-G3F5$vrSpDS3GVv{gwKQc+&D
z<avq+*GR&~pu1M`Rx=!~lk6ylwu_Sa=U}2<a?}@q1__hSRb7&Na|9k<mVC+ru2FK7
z*3wrcRaJmDOFp6Ev=+%c%CEFaD!v2nnq&o)y4l(!rhItQE@`^}nGT7CUbvl-O+tuX
zmlRUuuS=4a0TbPleLDf{k@(UpwpX&U9<z2s61fqbHzjjYkUq&3ilE(+e7p@hZ%aN{
zh*rO3do7d=NOBTj;g00WNpucMj>cn1cWsif9x#U_4`>NBEUA1S?%$K}E<k2PvXxdA
zqmnZeA{mpEQqFc<QnL)^CnUvGhjd@Et^-s0KvEe6z@)@s19(#s&eyOsEeWB#(2QiL
z5x7~&)xV%@PSQZ@>;qCq9(WE?o0+mqj?y67f;dSFyJ5*$`UovBT%@iqL)2B;FNKG0
z(pO&t!d<#e47&%Vb1pFGA>FhB6Ld)W9KB=?OaEj**%9gY%K-P3zOfa!qf)~ibb3kO
zp{LI==^-;Dy`|zyAU@LFHo78wr57T=^pmz5K#oft=v1-4^lM6F1xQ7IK~11Ejg~S&
z(jVw?7c4a_g=-<wcLty)RJx5S?ZTwFROJ;e9igRlg!DsNPen?r@1YeXeaatNqNT1O
zXvIiB`xk&%>9)`5{TC;F@o|jegft);G6~XGcf)+5bSs5llB5ghWqeB7KvAb;siP6*
zQ>1O{KvJcQmjFnUuA*F3y7apbKr*D?UI6a2w1`TE&PW@d0m+oM`@*#>>GKp^$d(?a
zTvLv;;5Q0Uo|Qg(7;4T*%f0|PFSQQ>K3BT91SayNn_@unr7;wzEs!SPhlxVzDoUCb
zNk?eyQY>BYI!u&E!}g%_g4C}cBBfFZRl1f*+usE#mp02FQXvg20-#d*<xV(LC4G3+
zJlucP(whQILXFg~5hiM-AJY=5PFfiPXD&*=;zL`#^qEh<YmhoD1-T@xq=Jac(&v<r
zY?R*o3nEvfztPLMNjeFo^RG%f1|iujy+ezDYtnm4bhb%douIQ_dYLL)I;5|~!8Kc_
zR781;>r%^nkS^&@58zC<G`tfo_DJ8NwO+6E4T}2SkZz#G)=g>masd0Jp2zX~-jX&`
z1?Fw3tQ#Wz(x_V?15zKVUb!Q^M@RJsrE^74eOEdt0ANVkriQ=6(#=aj?%AXt(Ytv>
zI?BS-j7k?#+3uK>!GQU3=>v+zPDqbt!tQ;kF$tXyr206JNh#}RbWTarC`B+WEpEk>
z%t)il0hpEc(IDoeUZF5}K-Mr0;viGfa?nv0Pn$_6*_F58wzJG;qfn!ZY%xXGU1bwj
z;f0&5oL(gEvPHD&I4GN-5_J#Rir=C1kZddcFrKnXN^l;Po%t1Bc**psfFF}RbpxH=
zvY(!TGd{9~r_kvutDeA=_{pTJfIBWzQ-zklY{Unu17v*LCNKkK0WB~QB-=*=4VJ~x
zmuEs`Gqjfum09V~O@!=h0+dF|me|2Wlx&2O5z(@*sLU-!_Bq8WVr5Y|P#Py|3xoG3
zWGfOtPRf?YLs`763h}u439^_z_>?FUQ|dNJHs(n2ms7I&!C)rKme4mvQe>me0H(?^
zRM4F!`{iYLkuEc?1TaHpdK@CBWnpy9osrc!z?n?hx@-(BOQv}do!PP_l~9%=tC~gY
ztjwVcxO1{Cbgb>X>=#<m=gKzg;cuSou|fJLX8E!cR3}g%JM%ka3T401byXyLBnrS{
z*)S#SN@R8PB)=f5eiD{SWzH0tDwAEBhgP|4ZV^a@Ecq~$R>~Ms0IFnJw4JJ!ZBc_)
zBXhn5Uaf5Fi}1HjX8#0+R4;o9pXsvAZ;&Y#z|tjIv<l42vM2Y!nMPUUYcP047QF?c
zO|nu-#axvoWkFlBOihuR7FlXMOti`h{s!Qh%##A0Z89gqwadz%gclt$#v=S^oigUf
zfOpI6S%CM*0<t05D=U5zowge?&oJO`%Gjr%v`^O61jH@;qUgLWJ4b7ue%YIWaBV>L
zgB^x_M|OHGL<VJF(doFmGQly349OmP7utqpeG|}fPZmrU;)ra`Drgy%X{erJOvYaa
z+_>zacmO73FHpqezD@SmLU{8)W?m2Gr0gI?H>PA~c0${<?4ux%8QH;FSelhRmH_wX
zWPzbjdO-dp?T#GeUbF*pl<%cLwv)VtN<p3FA+$VlksDV+r>i{p3V3evehTKe%jZU*
z^PqgY6Ivc}+cqXd56M6K045I0f1oJR5qa=6$au<SXMsN|cci6=m;6r(?jMs2)`I6P
z52XL0<|E&I0>oGDR}A7OccmS{ad}ET#_KQlNyi8S<l$a0A1FWcI9fsSQ?$DYmd6S}
zLgY`_O2G`3JJTtyFnJY~bA`)S)<HBvUPrO=Ncp4hp%o?nXabVa^4pZeh>?FY41=-q
zF{+%3lc!OX`h>hF7+OxsSAPLOy!<-7QxoJf_5dWxZ_uVaN&a^@be@twwgB^#EU!5G
zUzAW@cmlnt^0+d{q{(xy!BV<Bnu1sva(haJo|cEx4Sz=d*7Im($~9Dwnk8>30LhlG
z?*}hOew?Zb&&qcVL-#rPkCgm4FMs}9n9r3z`w1lT<SXbAnlI0$8mj_%moJs56v}rv
z!~G)p61rF~$d~!SnNoS96`f`Bl~k2gE@v8msE~gY0$!!uwH>@F`FVfvs^#yufmb8v
zM1xl=|AkIP)X9Sn;b*!iFQRQ+z1$Q4pBm(vZjejzpA&(*EHAr9@s~!qcM%X*<nFUD
z-y{#o1LCTD<CB<#W_j?3nCBMx@kcS3Rykh+{55$$9b{;ehtLNp+U2`x_1q!fP3I9h
z<)M_`xh}uC1UkFql8-^U<@=eC?2(Hn;9;+vn+y02`Oj3NYr840<-?mk`4<m^c}xCL
zAjoYw|2mZR%fF@=+JM~kzZ*~f!(pfyl>1T@%UyZqRgfY1_isbnu>23YknYJ_DTF;D
z7txD;RQ}LHC>xV+{0XgbIhU$(C*;d$b9P^zM~~hIHu?2=aAQ*b)}!!ZN<KtE^J)1X
zQE1J`v*{@?D|cHBrE_vm4S)v}Zcjt0gW`t}4AfB(F$ABS6klbd(^>Je3tBFUCA3j>
zRaDZJ*iG@{epql<?55ZLK}83pgFO`A*Q4{0!j?k|l*5Xf%YZ+kxI?=QPX(7w<Q!G7
zx1-ZbQL_(rk12-!f&1Qy@z+3n6pNq6=zSFmDwjL1_>pc7f5pWA;C6swif*nzMHm~Z
zgA|NhkYGg;7o8!B2CC5tRkYJ7+%QF$jb8NO3L%x&L@55qMJrNqY6D1=B7<U$(TZj&
z=ZaChZGeebg#)d=;}l$1*gc^Lq~+^Lh4&UX6R$Y94Z}`Q{I(XnL`5P6DUuZN7a(#<
zaiSHiWQFA!Xh~5_uZEUX#r<GPpQI^N^z=zr2&RG0P>fIl?X+SI1zgW4R#ON(Q*r$Y
zcv*_a=qaDAaPa^yN3mXlxj3sZQ5D%a#fwKEd0w%HOynw_qkUMOBA6n(`HD_jHWw(?
z&^QYfuQH*fNO8Z1_J75StE+%0QOqreix(7Z3iy;NR#JGrOp&)5h;l`&KSU}O)l)E0
zrFh#7oz;q`D05Y#h;Ig<R<V%wJavjq=V0)n;y8st>lN{NXf-GT*PwMtv4xVvmlbc*
zHlb1R)`cf<|6NhY=+bLayl()xs(AM)Fq;+cRRYnXczZQSt75quI<F~$!(gdRk^VX6
zqFwRjY7DzWfp;BlJjEZo;o5b@IXal!rO<Q(*R5FkBuI~9Cmp)!RaDcS1xFGoCwEhE
zW*!D%>r*rjL)$F{k1D8cD?XzNsD4Fk5S$rM{B{H6j^b4*$e`jK`eE-XmdjycNU_5U
zLmO5k+d<7eh2crKHllDThfkx5%)J1NDVi$)7*{-<3cC}Ex97u|`-;bwf;>>zx1w{>
zrg)cD?^B8yT0KlFKK~J3%qRx`g3?(<UNvOq6uT(6c|h68fTIq|Y&Q^RW%(EAbWsKe
z!l0}2%^yMBlv=te-IbiRXdP5GQ$*TB*;ELB4=HQtn8jh`87g5oqP$4wOFfmgmndp>
zRQV_Ev%Qp!v<En*TonizZ)L$R@YF}yNy|E4<@gJ5)KA$&ue0OIzv&>XztW=uya45R
zGCBj5UtNPpkkWx_ZiAHrlv4~*z7+;9LY1uVzzb6{XbBXq{PiAq5z2>cb)b>THMCTX
zQl@x8TeNZ;4|5TtyiUQ`SmmKfcp9f%LXW!>%DwLbe^OcTEVRWdomKEKL20APk3=Oe
z5SEgad$`b&qP)leAXT~UU38`?-zJ^u%Dwi$WhnoA5&oW5KKPvS4`-CsRGX5iY{~}7
zQr6N{maSYF4WDw9@2>&=tTOW#%*;9EDlW)*<!+kUT;)D`B;_f$KLV1keAEZJ3zWxD
zvp&C2`3l{JMatz=9bBw5WB^y9jG<5XT~MayVA4yKcCXSmo6D5%h|ycF>~Mj>3Z>~+
z;478?v;tA39HBa$YUTV7AX1~OUjq}h$`KPp>XZ$12>PNjWj}cJ%6wXHHz@bS!TU=}
z*EDoqRu0iKuu+*yr>?IkchLWcY*Nno0)AEbI$ln;`OV6C?U<Str3YonT9tb!%6Coq
z^CV>2lxxY;cBO9sv~?&C9fGz_WfG-%uPePSL!?WY@BuozmCw@tuSeOTg^6C}>NN2B
zlylXPyrq0(JErTl(mn@T`jw3o>l;w!{R(2cqm0@G{Gf93C|ta&-1i;Gkn(m95W~u|
zRBmujX}S!hBTD`|aBWoi_+#*CO!?0=$hh(v1$rlx2dH}OzVa7O7<`~SPNC>Y<yTW6
zQ_80`;7u!^^M#ffW&OkGoK*%#z`~qO$yNe?Ky{yTPY$Z-Wtd<`l{5VYPO5#2VBT5v
zB_&K;RBPxLaaHwPLCa0`SqId(s~VjEIH>xbO87if3tvI!A=UXfv<|D@-hwGPqPlt$
zEl<_$0N{?Q{-I@6fND(~%m%7#9g9JORQ7HV4OVs1ZZbsm#82=oRAr!$N0=&~Vo~9$
zUV7?9sJ{6Ftw>cT6$?hG4urydw5p6!j4`UDTL8qW-lWxCoNCXH;GIxSr(zH%RhwtQ
zi&sT1guMjS##T6!s7kUqgC?nT|DyMls*}RE$*O}dz{M0*(`O*5s)>WpmZqAw53O|7
zLfVRFsQMp+w$rL#sm$Sw>b37-K2x=sHU?R$Bb0{ER*jv3NRH}vF2-_J73L2M=Tzae
z#XGO+p_g&4YQZjwzvQXBC}@|j8jVD6fod6@5hzqGr$g8!sweo+c0u)M5;{v&Wwf*|
zQ$6x0l$NVf_W@p^y6y>HrAodNTB=m%sWhNkWuk>=t*VRzkvi4uv%p<c#nZ{#de!HZ
zAPp*~5{kcEQn}D(__FG8D(`JnwY&<yuc*c;@Y1AOB!Ky=s(ovKXjaA0R-i>ypNLDg
zRrNY;RIjOGe*>>WwThn0ovIh;XX;W#lmXtY`t1ie)1%6sfJm=OL<##FszD0$+*EBi
zPxoJ+>N^Tv-%{mL=;5|1g^FSNRRQPW%z)||jqr{tF&-j=s^!mO6n9nqH=%S$)lAQX
zVO9AZh}=_E&;>lAN?3u`sOqWnP&THj?FAWEEvAs}gevY~xP4!>e=S^lpnB(TD6>tf
ztha!eQduaRIj!2rhTR#JegkyRs^(K}e@^9i8!ZQQK_PgK>iMT2>7+hNfk0RFTq1aG
z>W~Ty&0SqgVYY+nTaSWxsNbew`62aMCWxn6cNKu6Y9k#V_ENKchB6<UdTa-r@>Pe{
zLB>x#K@sia>OT4n{nb@{5Dieze-Bd{sBU}%CW6%2ba@4<-`xSXL)5=hsvuN-coE=X
zYH0&R!qrL&j76yL`Jff4ewNDJqSS?tz<jh?{2t&jYU40StlHMtgAvB5Q{$oLgnAFX
zzE7&lHP9BXZgvGPK|P!UlBljf29l)S=Ll`5)PGTBO|rV92(G25*`shKRsBjEMAFpS
z-RMkLcRYZJ4E1HI6*;YTqnO<pb<{9aXR5o-LNZGoW}_2e+3K(n$mFQ4TjAna^^zcv
zb80JvcF(KVE`@9P>a`SkEKnEIs<Kf1G`$vz)UR#<DOPtep}R!AI32AEYJMejma5&(
zz|k^w&HzZcI-?3A73#mS=9*urew6kcRqD07=!inK+G`Y~MjgThzE=H2F6`E+zo)?V
zMfFNMI8(1SegH2T)M>v$_a(LTB9vZM&(g}iQGF>IxGQQyI9knW71cqusFg~Hw5mU+
zwa+!RBh}5csnh9c*REdjE<`%i|7)lEmrk|sqX1r4ubaaNd(>O0^08OF{s`>eQ13nt
zFYc;GUx&z$x@$hju=?~Pz>li6l$ae;v*}?!t`1~@H=+LL1}xoIXHcB^fqK(Qw5HW<
z6abk~hpYgZRX?%`00+&NKD7UH)VQsN8Yj&Yv=?^P3`~KzXnenhHdl>*J4C%SYpAy7
zm}Zm`E#8{UH(}mK6I_82`fAFq!jhlnS;}=E*EGC<mcQnamB0mPo~4Nm)bL)0WRRwn
zV(r12cPLR3qWPQl!nRP&+e7FL(`@<&1|u{^x-cR&6?9B1N)u1fjc82))iT6rBoD(x
ztY-EjNS@SejsY%Svxz>XmY`|e49P@|brg;!Y2K!g(kad3YhWo^bCxO|Q#7k@KqOW3
z2$id*X>M5oPq%5FI00sc#$gqjr!{H?WX@>5p;%+4M&k@#mgdC=@F`mpunEIHr`ckL
zWS*w`3R?M^!&^ZLG&`O~XQ4*&Ct5|C2X}xg)-3rOlTe~r{}JZ*g646mXeiZu@ECk5
z(>(PMI?FY-<9_h8LQ{JlqLrFVTK86ILXTmf)tZRyK-6eD4??6?^9pT}>NIUsZg)}B
zZbGYG^T8GH8Z_Vh1bCz7<5M7Qn&-ZSzwMeEFThfVri2O&IyJ?VyS=WtQUiFG<`kX&
z>(Q*S(E_kn<2(q_8=9N%!{ANL91FVpG?&+c+|o?Zv9{Zqmub1tuc?j#;ErY?<p>5f
zE?)5WuBL_7E<>8%X)1>`MmjruPcumAj}guGdgvV0<hjAMG0nI)TH~6Xv=*Pxe7B!I
zaPUAQr#o&^vzp!#Q<^&-U`}hs=<w8xCXnj;W;M?_Lie0zs{_aZttYME9JDNoTsUfn
zEr2^|-RVW`tc`X=r;D~_9z<NVoIB9zrtNoz_wHH~U1SHfyG}vULwn~XiobYj?S$~c
zOPewS-N&@aYcN7@?L0b_<D>O(L#MB{<u0`OX<wv*>j14ieU2$mdyyh8LE0;7=nmE%
z-2h&Q_Qg8jLbVK<wJ@!j0-xd96%pV?XoE!15~b~>ux+&V;zM-*#b}SkLR+ks`vqj;
zw3QN=KcOw1gWo5$4z%o!*M4#yY7(^P=+JMX_G$V6carwoN1^7F_QTB}DcW=Nph(qz
zM-!Z;)$fCrbS>K#Iy1DlXs>ie`>QW}%G7>#2VP`p?aH9cmaWYwg-nk2YBGRlwTcn6
z&S|~KV6Jv%2}qvyy>?7nzBY`i;0m-iHo&z)Et5)ninK|zYA@ENegYHaT1O`4qC(qt
z0K7_VD&6T-+Dr<0RBH#G1+P|Hh1dT4I_=gm@Gjc4tZQIi()Mo!{<8MrD=^Wh-7yE|
z6>TqVz?!tYCIFkY#yZ$-(U#K2zE#`&Cfsk=^45dbp&g|acBl5?#{jsleWn~*y0ooy
z@VZ;;unvG8?P^y@-q7k|A$e14qWpQE)>d;1%v)Mdin!d?-lZjdzqXAs$phNQ>4LbU
z)%*;H2eo$(L2_98Go@nhX)9WwW<={mAATCuuKN<Y$F!f{1aDkhN;{zY+7}mLDj#Tn
zqKbw|ZP`YMOlf~Jp>tZh@++vG(|&5}fan3;7Yq;woyQC4b<{ol0o-@eZKj8|v+jfc
zcDTCr>mcH$TX6=&UAKK4k_UAkQar;$SDFRMBf7(P;HanWXDanPs{7Cc5507|iy(4L
zx9JlQZ{5;I;jfRbjM8boy3j8AxPia!okhS0=#nUo5~$0d-#$q9cL^*7>uxMXXQ;01
zI1phvyE2e)-Txv$B6WEb8j8|Q-N4L5>pq}Ez%e@09+;2S`3yo!obIKK;GNV}(OWcL
zr+pUo5_BF4bSCOr;^~`)Njf(kfTwgZ^mtFvMZE!osk#|&bf)RH(W)|C=hp}iGjz*o
zx-xaSE|AR9t=<ha**cfEFu^&x{UmZ$x10iM=X76?-SfI?I@pn`i>1U)o=!)lMESa_
z^i7Te-G%w|fssO8R~nou(s@#CK(VftipWcJkJiG{1>FKMc%`}=I!{`rtD%yj3Z0&o
zIhDG%Ho;((?oB&5TCGc`J#>w(rXE^qbqh1VtJ87)0l%nwpNhlkb<fU&`37B80nA_0
z$tXg*__A*M7f{-$+fQrqE4n8C{fi%Z+14QgqE)xR9+s}@E>V$4n{Fu;(RS!I&%+2i
zb=8#NysrECUGTbe_bSlp)?K0ZP>;^L8J2o=Mml_PL)S(Tgqylds(tFy9e)AjmhL;M
zpt`NQN=GRBbv3a74CwwD#USqJR@mt39@K4J0diMor4Yi9?#dphxreP1ycp57(EDUm
z_vOdnP3Q(_TXkRe=VgrkfiCkb$fS-*Z@ej8Fg=N<bq(7wz!}~0pTL{dJxuSRIo(^^
z;Kc#Gb|-iadXKFz@2L08qGg$r{!jA4SwD9SqAvQ`73g%;KhXk&n?AV=O5OGEg@AWZ
z{}Fvp&qMzOou50TUqvh3!}?<%qIE<+atSz3{cg&GAJxB3n<Ov&D<S}n=|8l<g16p}
z)^R@imp=i{S3jCWWm$guTcc<m*Ds>2xWE27Et&%KEv3*FsQ)_!tss4M1X{uR`Wg&0
zM8Cp<NetDS7ejZLzRwvV;reZl!eE5{$tOXg^=f(<$LJj?02!;-Qy4T(znnrtC-hx!
zL(571u0{$A#_PT55=hW@(egJ@zk3R;Q~C&cdL`={&w!-phbXX}p}#;e^V9l2>1!ru
z^qDPaW$Kqw!XryRErr2seNYW}IeHVtu+Hi;0-)@i-sv0+p4Wdzmq)JNRRd*tdhhRn
zv*qi*{sYVc{h!HT7V6i&idK=Huf#+Z>)&&PXo>!i0OW%H*FKmi)jvvrGX1;s$|%>1
zo8e)FUQORKtJM3=K(b2jPgh_y<`6n-^aBk5)ap0U{=82AA-(r5>R;Z1S*y3{U7mnU
zgI=@?%}e_4Y4$Gbje{VK`es^`UeWLO0BO?irA_};{jpA1YSu5LwM&cs>It-3^@9#@
z=9)fYJBHn+_oK_XU4LXAL^|~BL|Ew5e<cO)x;~xqoL%|^%F1=?ZA)h{&>sDIik0;0
z4ND+%L!bHtfH(D?+aTJfzng>BExn#fYH#b$P-v-NpT8cG1Nt3Xq2`W$QwGK~s2`*E
z!Ck!@9Vr~rFMk4^!}_J2Xx-DVaDt%`y_{ZEqxyHI;qRC}#r6j1xIUM@ygZ?|(f)B#
z|63heQ+him=$_Uq6F_G4t*4=FR^R(ROw8$7Z$s$;!|FJ6Iv5_OG_9k-{|$KPWO$Pj
z$<781J(*k#M`r+cH3WSPx7`f&j*xUWETmlIK||U(3QKqxCaHPIu(lV7!-nq7(0#=4
zG+iy8hKpYTan!*35^B5*{#W4PF~ht7*!4CXZih2IhFvZggs)+S;)s5R;Qz|V4DR$E
z@i&Y+!9swc@No<&&~TUDSV4x8S0EW`nERNPWf6v53iL)A_R%sn%CNi+x}y!l^e~Ar
z<WtR5tl?Fvu8cD@(!=kBA(G<iCk^ip!9=`)Nm=Fu1NSeGL_?tz{w5h7(CvH5keLm)
zlMM$}Kv|06CojNL4Fv<RkY-prGY|J)y5S!wWHJm7XybU=;6~ZrGluZ>Kx7);Ta3;u
z!*zPRXB%!(2}O<}trK?78kYP7f6p0uIRKnD1l@*DxrXv6n8-7%pgcgnA%(t0S72zR
zFm<6JjZTgh88XtKrPv^&5(ry~VNizN3x;hJkuEj#(o??7P(kG=<%U5HWGW1c)&XB>
zXqbQ(Rfemy8>}{5`V=BHh84*G)EYu_Fwb=cS1HIvgZy*2R&TiUH(YBlgwf*rlHqd-
zkzO`vUx$`P!vNhJS8RqZTG=-lR)_(-YB)=0I+_g*DZsZF(&>OmtHF6Uc%6nfXvf!O
zke9%xZo`R4@OliRbRYE^zNX_7Hw^iYz{E|%^R)ZzGvw1}Qg0bXsC4nRVTm4+Lxz8f
z;qN`euXN#$7;G<5e0<c<Lus`M!xzyoao@0OC475eV9_b~NyBO~KV^8-6(ZAy=c(Fo
z#*iBY-mD>bH^`hJi=NpBjBk7fxP$T6Z{eDwkuix*C*xvz+BzFoOkhYZ#<l`@;c857
z2XQl6Z3m##-MIQWIDF8^rHzG$u|N&{A!B?vbRRapse&^{j9ho<_B1Ldq3x*g6{<Y(
zGEUL^{+Mxa0>s;RejngI#w5xM`x+f@q0`TJ_HSr8ZZy1%@%kIBa=-(O3L`888t>1y
zVTOW?EiUjP*vR_=PK6jBO@_fxqxpH@!;B-HuoQ0GNr9ILW6K_NMjH1V1&J~~{~bD`
zjqf}R-7&`J^k~Hz`{OaAamKf<qw|E(b3Qsx8bh>D9d8U3VVnuZ3*Unz8mHIL{g-51
z?f{2R8MpJ{RI<@P_jZcW%7ag-#(Vz2ry13Hbfz0u(ONIVc(MiNPaB_01MiG+Ck16P
zjUF}NWf>o*+;6rq+#X)!7?&5Kb=LUFx0r-;Mo$Xq<{3Y-faDun|Dcm=1;znB)D#-`
z)6^6h+ubnwVq<M6WJ-(+sg(YL@%A_1l^Xw{#9x`QG7%!>#!p{DXN6JqFgh!Zr+$Zr
zRmLB-VQAIH$LaiOjj<;e=4*`?D6Up#Orf2`MdK{B>WwGp3nI1#<2CvW>LsHg2+hmJ
z$yGo!8W-LLxneABhngm1>^R6(<Ae#4%|^B-crC^kGN7i__+c$Pyk-<VieIwLczrK;
z?Zz*5V=g+3F|82kG}=rMxo&)f9vfZ89h3y=Hg3#<y&ju!I32og8n24sTc5GzHOSmD
zzVsZJw~b?z<LfsrS_hE<<83-XaK|`7rE!DCe>X$qt}&w+b1`Imj}C7Q8_&_<(tAej
z4oHp|d#OZb)L0k__?Yn;g)GL6Z%tr=CXCAppyj^N_QP`!ePApiPbZDb8sPVo@t1cY
zI&JJphSC}1p;34-YkY$?G;>A?Eq@P~rl>&3!L<GkbUT_>twqbpG;<QVolV=<K$(l_
z{2;Wrn&uyb7jCAdLFjZh4blf64x0Y`4Td~SyKHel95QXCNbO;hyEoJvF&(4I22WE1
z3$3H3xN#WtGEI5G{4vve6cF$><x*9Pk12i*x_wRa$MM7XnQn-IJ8s(c2y_ORo~A@e
zplJ&OB0;7cTF?ZW0%&U)Vye#u2{oO1oT4IOrkkIF8E)d71tP-q4<&CSO}lE)8D;9G
zU1+rFN+CL9O!_VWVoh&Q?kUc+kP0JCnCc4Q(@B#*Rh-3}cBBH3WC|C;?kSTj0G5(X
zA4J066w^T}V@WmH9s@7U6j@Gb>2#C*4;W#FsVE3Cr%jdg?9DR0?hRnJNt}Se<d~+K
zG5YhS<FtLuH4W#%wLH`I7r@ImDd<8jFx~nEtwPf~G>1i|ul7P`u}OXwyb=>@IdB(D
zODKR*YO34^Qf4}K@=4r(<)*FlT(2<wwg#e=rX<R&R+;9g)TP?=Sr_cqm_DEdeywRo
z0a|sYEGmk*Xo`LrxO&rP^loi1?Vvc-B~vmz3@)4IhS6#?nf}0ZT`^TvW7tim_biaS
zYMT8X%9>4Q|3%BzV)CN8?^aWQ9ORnm)&20T&9st=Q`${sv`y(S?V>`EPE#TkG+sA#
zZ2{>rMFv7?x9J;7RQ8y<=xjr;DeN}@ZkWn`1pKBcnDUi<rbTK@_bn5f#(CTH;aiaG
zH*KXaCJfk2qf|nC$25}wrv^>t1wh<2F=^jAWC}Kc44ZzXC(J$5GCEs6V)|$mBu7mx
z6t*2R9ikV=xard!z)hG&zJ=ZUCc~$|Jut~B9yn?8p_5fpremLhH*NY$0xdJ9-fXmH
zO}0lV;5uj0Qbol9^9y~@=45{A3V_b$L8?q}F)yN^j;s09hmdqLm(yF#-P}vBvxDXo
zO3-+imuF$R51C)4#o=MIAI@9NKVtskT}XPGmr)_rQS&`oWO<pNpM;iU=5nen^ERKb
zQR>;ptT_i0zUECYK#iaI8wyz-H+$2P&)>Y8o<#xXr#&GVXm0aFE66ONNKdf2%?q6&
zX8gZ3+)m~++E|B~ZFFyjn-9t$5@B9IKU1XnhaC`!GQapJbVi#EjxZl%ey)i2f3arw
zn@}2O&aH<RC(M7-Qs$)jgDD{5&7=Q<mt<a>0K_TtwI4C;WV4v!dMRdme@tSkIobyz
zX=d+NVLshF8vzp;X3sjbPMbF`#Ux~!|8hZRmO1cGxR!19lmVAxe$$@5`F7Uq-va!3
zv-wH%=9>HRfygtvmB4(y`NS6R3e49itzBp?rNXfi^Fm4(UNA=%LTRb_vue0qX5Q<E
zR=N3YDgdi62d)OGG(So=Y?b*}4g9S(3qQxmYRuE2fY+J@?@(Bx&Rk>%;6-y9-3RsN
zEsKF@FtdArzhr)dwoaGL*-gMVnhTDjb;bPA^Kh-n9IV9%ubP)oeQvY)XIf>onEhB#
z)@oi)2aK<o_gBH+HuHoU-nW}ODE-i3_Md{5PV=k(z>w{_xmgdHZu6>#pr*$x{|Drz
zIUxbM`^<9}fw*OUt`zv&<`ruJ>^F}ehwcG$Jmnqlm>2UQGH5Pp1MaSwO_{eL^Eb46
z9X2nZI`eyGb{~}CurWP!$IbJrp=`pOLHF%_n|ULZIXy7nph=iC$J05HDf7;~n2Txi
z;nxA2F(<zV;H>!-XE-`%PNjSEfaR}yAdZ&eXJF9D;&lT6XNwbkKF`H+{5t?#En{@Z
z#?3O}3kzPBXeG!o%MBF6&G)us?1hMr#rEPk81%KgSqk%hmMW?p4zSFpjBKD~Z9niq
z7TaOy4z?sM05HVTumzH#mV=a`472<}nf`D~EgkoYuslZ@#z@N{S_?#3?$f70qb*Gp
z&=O;rN`lT<%j5m%jI;dh19+;X+qMY?(=36W7-)vYqXUCEZJGWKO3zs4C=j1%>7|fI
zmSxTJAla5@#c(Faa^X2BJ!=WQg;AWdyiO6Z^On1=5XrT$YT!(sWt|Wr`IaTmLuY~I
zAQhz*TI?wZTV(l~s@97wn;J=`#3F8lHy14Fv=k||hz>wanME^%xh%Jwqa<~OC4uTr
zD=mu-0$*jxKL=j5Wu^c7YaUu^t9u+G7cC|Cp{3q(n_O$KJV$ZuOBPRh%wD$q(*j<j
z<vL}zu2>o<ZPH{}NP+*WmfP>3v)QuoMObLDOfNuZt0j~6$?cXNTF!M?25$o1X}SCd
zc-Jk`2+U8HrPLF?bX#(4i$HrUD~i$EYx$dU<Tor&Qo-6y%X^107kw5E?Wk{A+Ud!1
z+v33k>9-6FqI1A<f{H8eSZ>K-aM04734?bnE{ovIkmV+2Er%_CzlYX6%OC&4uQXyA
zIEv0ui)#<yW0uepHUP&h`zaeSVaYuJ=6%cc_3+|>rSnA~CM~U(Fy1N4uBU;RwuE}X
z{EX$<r@@=GG}ESG&eBZZk33+VeINchSepaUa<p<CA>w3>r}UDub(;%1U94|W1l-ly
z@Db+1&AKX<Qu`j(GxU|KL)P%?@Zzww;!6OJSgYaz^t8&T@cF2<gSP2j)>~;Xc+48U
z5yacNgm!E`*5I!J@U=$r(dlQseh0YY)}3VD-`c+bb_1-8U2r?ls`?0H39<$hf){Lc
zdYhhMA=ZBS?L)1TwB`!4K1PAsaO*Bg@kLle{>x5V<;UPflvTI^+M=yXbAXSrZl)t|
zvDRn0F{U`H<{a#vuvYzu={{-QLhIdlYY2se60DxzK_t=o2@9P`){+jiPFepghNLao
z`ol~34N|Q4QlUH58dwVRY1ZPc(4B70^g?Hb^&MLDoVNDR?)8jycriwiY5nOfsL8UX
z&_6WDwt5bOmt(bWg2A)ata<SMoHg+xc;~IH-@~<B>ubI+lxNMeV%GAl2~>1jV6*<P
z1=<R&0iVENk#)r~m@l@fX~A1!<<Z;lg7x18P*ZBH*akIa*2&e-U2ZL;!iEa#Q&e|W
zX^lSvZB<r_8oH~k-fb9KjWy97xQo{H6neX4ZKDn9Wvg%zylAw>(8Az~)pmykgH2Yq
zOeno-t)#qev$gt5sA;i!4xrU){l*0*u2~n^!C;$p<$X+IyLD<1A|2L6^z`VoK1`<<
zuUj9Xk7jgPH+n&`+ZwYKl0DX46c*^UT6RL&4eLKNu{W)sFNYU>)}8--H};lw$LB!Y
zww9%U^jlSrf(%&SNrj7dtO03IGiWWi2ruqhAEz5=$g0u8(y-O*Er{H+zP%K@5$h#-
z&Wu{`H^I`FHL)A5aqFr$v?i=i_d(}<Yd(dbA6R#80B_Qo`84J4rmVtZ$V^)~tD$Db
z+ExqZtX1Cy#GLi!ICux_Kbr&4!G7j8{C2c|iUQg$_I^|d<!Uc{6U5D4vl9S!dxvY_
z9kdsp1o5y>6`}Kpy=4j_p7vWD;r3Dcmiyp&+egLH9@@vgZaJF1_Tk$xrGECD(-1vw
zzu*~&`rAKp9=srXM>>caZ2#Sp;Dy*<?uOD(`;|Mv3$y=%st*3o(RIgVS$%P}$dT=`
zWm#FKm1Sv;wyCL=4d1=@-tTK!X}u^ertG2Yt)L=XrhqJwDF_M<z=<L<1Qd|p_x%1k
zpL_2)-*fKsKF=NJoO|CWM$#g%L^Jl$h9ZV>na)JSGLBGSCXOMZZ!?||`Tz7>M%j9>
zBr?)|pzkk<vF<#I$qXJj`42Ik;)3-sW5y<QJB3k8rzlbxKP*J=k1&k0FgYD%B+)l^
zjPV@B7Sb3Z`p4_z4CC8Sn9lH{H1!OIx)^eqjJLi8$znL(#!HsX2%w)Zhw&jzo4Jf{
z=pi^yFecRC$zv>}EZ=;_lXYM%V0=X@ze2`rnj(uBm!3yuF(c|8Bu+BC?t_#tj>m$O
zGS+SaDPw$w!Nlbhqdy+l<&2e4sH|WJdthiKqv-)Es~GcXT&-rr(sXi~@h=CY#>x2Z
z|C@fs@qVbUWem4LqK?6)&!L_XG#$To1LGUIle3ZWA|?1VF<f)ec9zk%6)Kt;n`o8O
z!Z6mOYv&kC$)nuLm`47`HpUxmXgkmNl+ubXF#fv%@pgvq6&TaO_?|xdiwvi~2kgGW
z7@>7wC!_B<nApWwyBvbuj4X0RUu8U`-P|?C3muTZ&d8pDXK{n^F8vfY8P5^+Ek@Y|
zp!6{Qq6FmIjGxR9xWkyFjdd^Mh819U8E20ItdDW~Fe>jc?ojqxKcn2qf;9t-?`uE?
z88L4Hdx#NRhSGh8;UDk}Gn^ET8)29~f#4|P=Th|k0pmn0$U{b`0t&|%v-=@8&e(Vp
zoD+;#+MGRNtcpk5BxBxl;B;leXNK>GX`2mucQO~&fyIp}Or;-v7qf*P#%^ZSDD>`O
zZV&)%FH=XiMDAlgqBqH%$^Hfs9?Y+^(T4l>$Q$FuWRRQ8n|YEvVm{2R@ldg!`QzhY
z@nu$Ag}r`ERSZi0%)efTq5$R#<f;f{&LbCC5cAD(N-Yg$Mm2*qgy}_zxuMK@C5#DU
zE~Wj!0VbDH=npcN&`G6m=ItF|iD3GEjZ!4@y?ZD{F_)}`G11JEt*DHFg%F5k?vDgY
z9CL9KSQ43+$eoeIJV$%?WTumT>=dRXgTB91=0-aGc!c=_je%**6*RRUXWmVK-RaDc
z`KZibeokA<Oy(*Y(z2MpcEkK!=7PsSPB335w_YCewP&F)pPAGMxdP_TU!uQ-%!Rb#
zD`Eywz^|C;^Z(pirig~u66U_&V2rbr`4+kC%b4CzgY^{CgQ7m=%*8sORWK(g&#sc0
zMSk8Y=CUBPRWo0i#4mE1*-{1h8s;lBx1M48Qpl{9xs9S2bxhSHRMa!)Q2I;*v-=);
z-^hHv6O~QO?_Wd*&obv4VQ90Hd8ZkTEld}3p`By?Kt7#T<~cgQ-o{)wipulM4c|iI
z0yD20ZSBkvGPHwvxEOL5nL8<ve2Llg7szEMi{7g%Oj!cjx|xPdSbvqdo#saTdEdLh
zyw1$s1agDf69=<zGMz58AG*bC;GwpM=|M)_W(HCi@DB4+8n$|w849r6W!|Liav!r}
zBTDy}vuaT4XG&tAcYwL&A7~n6KCuo0L(FGs^Lw8;MEM-U%(?V-jxaY+8uTc0H3c{y
zFxQ8H^C7dsS%t<i<_p{LNXMCNE+7+3>F>aP#B@+1)(%$5HL&hvsoO!^SQ)E;y@$2+
z5jwh;b$T^G_pv^ShJZWk$P!?CuwpCF=E=&M25~P|9<6J<S@-E86CalT8Ib*~<<nrV
zFYC>h$-D2z3VRbpf7Y@;@G}Rng6K>|AZzgwXbNJvbwNIu^=%X?Ls$>@gM_lq(rxo$
ztTrXc0oKb?Q5nH{X%o~(vdTh$8O6Hq4o%Ul)wC&#VX?`@63a5Zg$~BCUN^zQc-B|^
zscWaWB(Rv250c3G`aSe8i8Y7v8IxJ_=rW8$ET4~2d6;Ec4EYq+WGF}~>-%)D9AQ1Z
z5-dkqcSEd8u#*@f_f0zMl^3BRgY_~caAmUkcEF}A*6Uf|%x2;9!vw^-IveV9S;8Zz
zJi(gS1MBlxdUBxWvwA7kRlw5DfTBWHejHeeSejcfu$UD{JAsp|uMA)*VNHufWhrYk
z7^IAq>f8aCQ>>BMAmyx?d0?$zMe|`yC2Lz1N>!|03Vc_y{=5q8)2t3D+G<&Ukk__>
zwY3bOjjUWcLDs}tL(AT?tk3k2Yi8YMKt&5{l?|2WSn>NH(8}8L9xB^dY?=(uvm9$^
zC(*$=PT$x?RvqOKU1FUi55Q&C%Wt9b3M+FKBsy7T6iV%4O;v%Vo0Uj0va76L9^luy
z#!94fvo~2zntyJwHqtt-hqdiz2=uc0J_EVS`XvPF`&e%UqAvriC0|3sAZyAS6b&C@
z9sCwNBdk4ivTBs&@*H3uu%>^Hj*hebp!?(|Sc&8(dc@Lfho&9u2037MvPCg4#*NLp
zLoYX5Ld(~^?DinY?PJfP3zR+C%rO|_#g3rkKi=#)PeHFQd*~2Q{Mc1*(><>K?8N85
z8pL)|USTkM_FKRXVSh@)>jCx|HwYeN3!lQg8P48J8ER4Nk0_NVn!RW%1Y+2QbSp|c
zyPb_v0(;_ls83`UJ&8^nVsE;G(qZ;e2S^ILhq7#svZYh;ERL~fhr?`V8oSjSMrE+S
z+YO^K*;{Go&SDp@ghVd;`&no^!Or^(B#-?vEh-Dy{bwLp#2yQTKry>H2ga1LU9*5)
z#@<LV`BUr*6eFu-5B~zws@R3$Fs7Qlfnr=|*#A<he+#>WX0vln_R}=3x3Z`E(Tl<U
z+Y^H4+1>}i)4~3M1-%#9MdZ=C#7>Tf#AS9G#X_#Id%uJFPBzjr@LsV0CBI8IJB?Ni
zSJ{&V5WmJAp_5$K*&leIbc3z^72>zp4;oPFVb8LI^ETU=`7`w1VIL!xQZG9t3f=Bw
z2Y-NG++#1`LvKIZbQahH?0K}&9AsD7Q8~oE`XS^-*gulnb(Fnn6rc~-^J!x}&fb>^
z&I$IPe?s9S_OtJx6RsRiJLGn7UZ7RzPR>?}nz(TSoD>P##kuqoy1j?<7ab$o%lVOJ
z_I(`QY7lqM+gU*K;N0Jc&UkW^<Zklfl!n1xZ_c&_5clDDl2d;_XX6nNU(T27V1*xN
z-sfQP=N$YFngTe@%h49d!Tmva*EoWQFfEufoacnz5KgH9B$VSx0nRYayNl6yfb-=Z
zutsn;zYh}0$-4seQJk+1p}(=5h#6ps<8-|Wxp>aDWiT{}v*$->O6EL~hPFc-)joiw
za*ojnup^u|$TNGC^TBsOInGJg2(!~Ux3VZnDua_qakOks(-M#zPXBtq<Z?FB=#$SG
zr;N)2PDvaj3OP^R0QO1FCUU)%aKc3}rj#?f1COMfGeHi#3QiY&_m!M~uYt3Q^Hx8s
zsOHS1?c-@qBYnO#oRv0!o#70_G3<1y<?K&{raF$`L-5pd&aMSo17{&0Ry1*T(<b;V
z=UM`+Xy#Zc>7j+Q{9TZ9oVAp!+sX-3L#~ap$qSqpI6ShVowMKxh<9*q(UftK6HWn=
zOPoe>*<I!o(`R&rW2FG4vy;=f8rF1i+$piIn{%5+imMzM_4gX5#uwx!$3`hCw>ZBE
zprVI!hE7oTa$ckL@?FjgH0$?q++3jI9%nl(1N%9NAAt;T2IzR@AZObmunck9pM-|{
zoHYzo4s$-850nun2Zyim26KMf1M+~Q+k!ql<ZSp0r7_M$7w8@5xYGI63C@}dnE!~=
z8VWMWnX(3kx^myuq8B^3pZ0+4<fhXA<;HEJaM&&`m-Y_3xf7IIvWMGAPi-&vo9BSJ
zk2{5aA9t>EbPK2l*JmAAJ-JIG0OQ4d?+;kv&E<XvRv+$Mn$`Am-=d3ke7S8GV45Fy
z;&l*zZqOt^1Gvw3fhCZ;r33;&+_#s21ap5%0!j!smeL_Zxg(VC62>ij56|fUcXm0{
z9^@*W-hc_`=222~1XrAdM-$2Yg+lC6+?Dj<MswTgtal9e;Rf^~mb+ssK;yV4x`7tY
z^`L!j0@pPir9^J36;>p1|0EA*GWRbUwGMG7BzWqFxi>9Pn8F>QH!zi3*N@60+#_Gm
z_ji=Ln~qW*;~FTxFOB;;xpa?nk5V32I(H_`AQ{}9w8zTi%3{%$!_A@DC6^oQ4|0Or
zeGDjh+!ZwF=5sex!}<bl5*b>^J@o{ji@3RS(a&P8l0LkX+&gvPEa7h6P5<Lj%GJ>h
zw~YJzI<TJNzCIm1<=i!pbgAGr44|@-`)VcBS8?0O3slWrKO1PLxh~5fSHoRTsjz3b
z_kIUwEq7i9NFCQ*4%6znr}W@#;Lf0Q??&#FgAi!qK2E>nS#HPg^gkZW+`nk&)xy1c
z8MWuQ4`_$m%AM_kQXBVWdN0m%uY7^h1@2$VfY#1UCwG1acikV*bdh`A8#Z0xcK;2Q
zPVP(eI(KoOi^5OQ%`KV$%T=x_6B@2@3s0i*I=AyNaNgi%l3UJsll$u1XuQQ;x(lp5
z-0&3C-sT>sxBCuP|1TawFZTyJzHpbjmSW?5+%ptXxyM~clVU%Y9}Ug{?n?3p402;B
z_&LNKEW;zY&;2YIrVVokY3(z@z1R!Aqulm;C_UgRDO&o_$(=^y`WScKR*-S-JS_w#
zxZlyq{zu&JR)9=$`zfWzl{dTr3U}~k9>62n$@`anbT?js1OmHw<Fs7Z&D%~X410Ka
zgXqLwp7a`Q+Q)mE9JKDdcN0<a;C-fpxF>I0GsL}k&ew|};ms>M3Qaz|8TSFRpLcv6
zDt&oNH0ZA%&oB%Le_q#glmd8_-=j}~yc0O6;S$8#wHlzoynZIcLwLW^1~-)V({UIY
z#`}lTgbwiDFvG%wyhD^c5YAg03=I*yYRX-R<msI7=D0-hM*jh8H1E@65RBmky8$$o
zmj{o8OB`=tGg#tz>}Np|c%>mwk;qG#1^FaizygrNyeuA6r0{w+K}9O>5M5ezj92p#
zx}C;*_$ll?&f7&x#a!NJg<#3&?OO<x0$%Xbw39F74W0xk;ziKjp_sRP5y(lN-ztEX
z@Z8C3T*{049Hfl*#btn&^WrX}RKfeQ9u`*e29H3ziuc+xsI2CB^x<)x<}K!f^9*ld
z7Wz`l``r~Ctm9>OLVZ22yAN#*yx*%S8rR5+--TW@@qVY!#97{#6!vfCO{YCe3(rhf
zhn(Zh3WP)}?-_rnXyd)P5DL%pt}X)F1>T?GXlv(vNZ(%vuktLczsP&y21=KB-INP=
zna88$!WEv|DPVT;KFx=PUA$iWu1=S3UN*(Zuk!BDuXc@BM{B3+yxn_Iy21OM&i~xx
z)l>fSEnYnBmG1D~o(c<ld3#d9d6(C438aq~kOR~1@jfmGSU+z)Ekg%*`4j*f<h{NC
zEJM7B4XC`&^KC@sFi)t0fOCZB^$v_0<*Df?<O5#XC3Ni}Pw^F0jPcs%p>mw}WiKix
zc)bCDdBl6)8)TBVnB-mg$!sWe<2O@;V;8@kRvo+f+i4Qt!@u|{+V=9B=`X|g@m(zF
zggZZ-#y1cC`)lxIJe~XlOQFe&zn_9A-uwWHIr;FvSr5Ve{5ABY`|`#2A>qewm<xG-
z{@uqR5WtVT0M0=EOCl%?;(tq9|6qP3eH<Zty%utz{LZf+5XL`F{(uAgCyoO1Am6eA
zZQ*?RL5N52ovX=7AI+~gf=3g>pKU{9EdRqEpe68+{sWT8pHJrplK2&rM{=0&brdWq
z{8J{#rSkoIfPIWF>p*21f1&`T<NP_vurQM^qV;kX|C>}i?ri?(OlZjE`^^P8!5@DO
z;(7c^=kHLF&)-J-gaZD|Zvj)pZ&-}RV*VV80H5S<r##hC{tx{yxQu`PJAj_zmy>_2
zoPTQ(Dl7Pr^lMe|&6F%(&7Zv!_MYZH5e>a(_=mTkRLl3J^u9WNstzpm{BQ;^8~EB8
z^!+vQXN-XLEdNIeJ2vyjZvd@@f29zmb9@hS`?m7$Y(nJ)z6a&4wDTqZz_boNdk`!a
z`A10aCH`}}K`!%cv>~~|f2SP3Zzq4s%jjSie*=x@J^VBCA#j^td<*0bf9?PO$EuhA
z!8io(^5I9o8_eHJF{^%l=3JBp_;uCj=n#K;D&$A_bLpthDE}?mdpzL(OaA4D{CCcx
zZH#}661T?r0kmnK;7^+c^^f?QKZd=N{8UOsa1}JtyS78X{SX2>1+PfRleS0DL6g*8
zft8KgeS){>HE|dClP}6cus4+6Qo-L8r}Pr!PJ=Ptf@1QL`v|g*;UNSFBIkny3NF2l
zjs^+LQ=l+daEb!5A%ez1V1^2=P*#7KppZ5)2L$yLG(9NTzy^vlTA-&jOpL(uE09=$
zJ2D$w;sn_=@5T!X8iAc4xWxrY6#Q`oDv|_mYe13(y<O0BL?CQ|y+;Kh6gxU5NSzOb
zX@XbSu=lv2gqEo3g6ERKk|DTM1G!AWTuN%r5@bFJeYsA-&$FTFgkZ)TkUW9c2{h&l
z^gjZoK(Olvz!VC6e??`H;F>pBiUl?4KszZY?*>|lU=c<CO9k8CL0g&N{RgP55;T)X
zxLVL>hWKg0@&fd?MzHM#^!JP)TMw{W!GAO|)d`#{DEXjXaF-4*Hwfz5fYu_I^C8gA
z2}U|m*(!)8hgzGUlnyAK7xa(|`+~rSa?;ubBNT+}5Y(TCii-k0MaQ}XAN>eT-GUEj
zm339%^at2A!L73(*9BvnL2d{>xdJP03Ywg9&|89K6eI5uy#F*n`vmVRP<c;Kyc^j4
zf|C?08xV|B6l744I|{pp1VNub;J!diY5Bu~YDy*>5lo}G@u490DU`+p%ZgyrxS)Vm
zbrXWyv?+Wf*!2lmCIwS&0?bwT<hSHW+aY|NjydlXhEt5rO(+!udzUbu;>o*(CQ8Zi
z5Ux!^$y4Z00VywG=UQ-j3y+c?(MR~n5ESkgeocd)udp}?_WB8@_TpLi3m>kA!VsY&
z2Xdjp78<<5gclD3?0~TM0C}<x3XfBYcDRs9zNiS{Cx1XbQWz_TiYVbLo6w7RVGg}|
z3BuL%>Lm)F>V~EyVFn*0S!nEn_#xrXN|3|C!BL>32rFpVNfoA!0qnTYMyKx6h4*7&
zZ-#K$6KKm6&gh+i?=MTZ=2`G$3ny2jHb=-6047&B>ILi*!ea8=7YLhjAYUl_x(}ry
z;d`{SE*1vSX_1q{$#fW6A}kJtp{2r?=)hf>P(k;yo)W50p}*xq?uQVl5Qfk>m`dRk
zJvh$@pCDg_vsTzK0=;#@nJ=KWUbs~UO%1|qT3Iv-J1ENABrLK*#aUr$IY8TlVw(TX
z3)3j5enI#TIWpRXMRd%hL->&rU>Ai2!)UuCe3e#bmxZ5G5ag=Rm7K@dgvZ@cd0iNm
zLNB6Ic;;i!o5Bq_0KFv~rIT+xLUASJZwvD&zxJN6jgmw9g*&f8a6lM23y*71_$@^f
zhJ-WeCBH9}?|~J=!Wvpbj0nq`fbvjynA|^O!ZoWv#)aAB+?WuK%>#KPH1UBlDRlB^
z|F~E5SP)d~6O|u<yu0Z7G&FjMmhFW?PZ9qb<h?}FKf&TH8ly?VN3{16IQNSZlAy^~
zG<E?cKT-YzfccAlh(~_|L>06X2^5_nS8$N1g(k%i(UUaMhKk$*fD$GOb9%t;10tIZ
z@&`o^>6MQVacG#06unP*Yf++C-v(=pD7*?Vv7*oA0F4v*b5R*Dve4EiLG;2aAju;3
zhmboY>UaY0#bMDBT5+a`3QfRF6_p==z!A|DTDct+eM}4VW1=blIU$%P+Vn1ZkuG|L
zmW&x9zg-}iqCM|JFiR9lo`7u8jgLTbMA8T7#R<`47O>=rGPglIU-VBfunR;#>404*
zdYt?UMWUEBc+SNl))m-vQZ&C6Z6%^@w2mtkiGA^W%S6s~l#O{xbdB<`%0+kSeXbD2
z(JxvlT5$=2RigdmX{{D{q(lC+sF~dIHKLDif#r;74&{c`iaM9U`Z`e}t#;}~F;fB7
zAUa4t(^=6ZMW>oY`e(t?BGS@9zjLCeD4n=f6yHblUz_N+*U^g$q798`Y!~S$qo_l)
zejMbY=momT?vf~HDad8fI4zVrMHgv5)g@ZI2rS*AfNLmS6HOd|rt2b?eK75Y$R`QL
z+!WOf0s5Bc?;N!Ch!#@T+-;F`8RU9J9`wOE?~2+wA<-wAO~ckb(G40m`bEEN2hX5r
zf>z2yBHvd*?u*XTB4Akb_{&f@B059A{ix`v1$YQ!qF2ekHZD5zH{>QnZ;%W7k?0#b
zzd9*0c|zP(TuyF@9b$tYjM*vP8UX<}r+6NDk9Udp(TulStW7}U9`S~2XxuAyryF(l
zi7V*gyNhR#KhZ<{BY9dq#XOp6y~Hp5h$rJM-Z}_5AMuS2fbAC_qv*1)cmrkK`H96V
zK>Wp86;J}i1N2b^il3i=h9I%iK>?{?ab^rih`4kaYD2|F6?zyZUPSk=91uTw8swn(
zM{)**izn&GXoR?ylHel6pL#(qO6>RlRjl{`T_+nOei#iEvEu1Wl;Xtkbm?NecniI&
z3F1w^!_Y+WQu0A3iLW}DU_C7Ubskith+}EXmMVUS1MDN>JKn%PD$b^j?lEz~JaDFo
zCw@X_j*C|X047~5qt#u8c<oGJXNngvz?mifXBchS;>~o0M~=9g-0HdFZz!mKLhRgu
zr<Nx^Hw>_Ram!kY^Aw10T?b5|xImA_BJniZLlleG(Vpp~csl)fCE}c~p`ui*e-SKY
z;>nl5a!S0wh_-U^Z%4pcAx@yok4mvC8`xFibh>(=TKwT7w4D}r&`4S%UP<Hm8S(fR
zV5t?~|AaD`8pP%=VMU`jc{$8)661s{z8vw<r$Cy;=XhXk5l=ROoD=&b0H#%(M?YSh
zcrCd)&x?Dm!ln!2(iiba+r`#Iv~`GUDX-$9IEKdjOXAQWuv`{Lz72b?h}R#)^X(Kj
zd^rW*Uza%70}|chNs0zu6{p3+?rY+4UsPTfKTZjhH^h-uXzLL#&qnFCxQP;D?}&f<
z7A(DDvnxRFiof-QY4^k*u7-HO_%?Y=2E?Tlk{J}=ql*EC#4`ubc3+&a0+l1;hNm&y
zI7h|r&VY#z#0|rE2oJ^U$OADZ-sM2$xOmG7sCXn^NI|PfaVt5PT_sjOke!khQh>Ti
z6l+l0CHa(A*t;dyV!*ja5*-fleUi6MgSbmxrDSXmN$+Mn1W$<@CGmJkT9$)&J0)9=
zLw>(x`%@6~l@zRjLO+S)IaK;f5}tuXfaE25y#gg)3DLt~Nk93GLL~PoViziTgVJBZ
zC5LG@86oli4V96SC0P)Nk_f&9iI#Me+bCA@7j1jvB(B|nj+eYbi{S)`^SvJ+m?*i^
zjM^kg5G8yjOPDk}9hNMnIXOi#`!rxuCDUl-cSMr%EZUArbWxB`lgOUI!#^&mr-fs>
zWQ3AmGbGuRjGZY7)Z>w4N#bb>pDoGYfaQdwh4#>Sl4uIn=1Z14$wgZr(XW7Dp(L;!
zrDDmJ^|0xrWWhTiC6YJj_bru7k~g$Wvg&zYpOQRViM9&KEc#L_B^mS;S4lpgxJR`_
zO#$80k|GKt)JP7PAYLnZmE3xDl4t`;^^&rEC^bsDH#))7Bw0)Oc4sBuP<mstWc)YC
zw@CI={z|K4OEdc0CK;vB@p*~+B*+EHI@<rWOFV>7*dg)a!k9~vX>_UdWyzo!ZC50r
zG{tsGnj3-HCAqsEoZXTTN_f5|`G8WFu1nthf-Z@@A(?p>#oH3=Y6#wuL{32udnHp<
zu;Q-dRXQ!wCwYM!KK+uGBA^XOuD^rQpk$r~WJt0y05;v14A7aPVaYoUU>T9jA?M@+
z$!njZqYovsm%y|!iOYK+<B~#3IGd1MIYH~sNy&5H!YEhio%1kphcs^otk@|%NvR)h
z($7=T`(4scsfW9zi^9;hPkJ&2D%_=l5U_Yi{m8xGDINL@#7jCtTVikNkN3dhBVGMH
z$bRYTl$7Z!6<49nPbzPMY5vl58W^1c()Ig61Eq7T!5SppMQ2xnrCsFR2$9|#hiReG
z*KR;>n6z~<Di271x{dxGlqS9bh2c_G7fKP*s2%82q_p@msECqoqQG~w^iBxcVx&vG
z(H1NHj^^Ds=}O9#ikIe6qG^It`Zuk>5~Wu!fHg^4^Da~*OYhqtaY(vzJ}f;f4POEC
zQ>2F}b1PN4l0N?<QUxv0k4k%KF?>vVv>u&ElfE|rx#LpB&k#tLCR2zpL)!EOI5VX`
z{Q|HY={gF==SpM6;5;F92GF-%Ag!l6g9@c<=mwx7X&S{;N~AOC-lS6L6O@)!CjD^)
zc2`JG()?K|Eur0Sl~hl8Gd0p_uS3%rX~h>%Q7fHK3*H9lpA>p-ls-wpwI=D>20WP-
z>EE>VIVVlti&Cp}i}QELUy!DFgQs1}e-orbI_GonT$UOs<b6eYpPVb5QUiI^x}@zc
z5a^aZoCAedr94{XU6anC<do~umG7f#H>AHc0Oh9irD;%cOFH`%$laDECBoi2(&o<~
z&@0_bzO%bhu7T#iKIs~oGy0|Zba-+=%6kbCgVO(=1L%<SFWM2@mu~Mx+pyH-Pqd9l
zCw~IksPuEnAbud-k`9)K(snv8I3~T_0nBmfPxP)&NINN_^GIr_2j`?T@gKCg$}-%b
zeuu342a5mgls$6|JiBEZBcX7Q>@YdM_R8irL&ZMXzazkQm;Ee5rH8EKFK~Lwbj9HG
zlEv%<nvX1<7HRus?~u35SLVxwCO_E@I^XCoYo$$Lfb3N|hZ-o8wSWZ47Ss10Dm!zH
z=D#pmEv;w{$aY_cM1)L(bPJbA*$5>YN6DTj0g0BqM+tf{va9r##K~68Kq+3vy9~Jm
zS)M0KiL$tF(3T`yLKA(mY;^)khh(voL~vLpB*$`!Y#oi@sj?+Q5Xh3n&?xQ9mR+C~
zYmO{Xi`rb-AN}a>3E6{nfXS0NDM>kBc9&8T3S__0R-#b0dOAu)vZ7RA7t6FJkdw0h
z7@(BMR+1N|R5q0ozsh9mX|z2h+d}#2<+9H`puR%3T>+L#nUvP8RZiIiB_vkM{uqTd
zr)7f~5Ui0I`=H{CY|aoQYGo_6sH~IKWWmCE*$0{6Y>>(CqOwtTwG5n1vaOW#*CPA&
zQwW@sZHa}Ut+E~CsJtNifyR<{nKc0d9kN-JJ#bN$djVjVWX_E>kiRVZZYl)3WXmZ@
zt6MfnIS^N6D@H)B$?_h9{B>Du4&-mh>gZYAl*Q0IbW7&m2GS!le~upBmZj0xbVpW5
z*YWkrCVs|mcURU#(aS#B$9JLdo~-FNl=@|27eEilCY=O2D6@M)?~sgJ0-pP_MU>n%
zEbFaB+lXvAg&#*{uh0VFfovDuwDeFmWhUCjWCIFl8kcoZ_;5m2^BB7JNGALYWKw3J
zG#FR;w;G7=kOwrv?49x^8`|9D)$~Yq$(P@v?{BwUNT1psxv~~|_sXwvP`OVYNFSHG
z{0!v`d&qk_p~6%C?tWBy$(wJW(p%nJ4KyG5pS1VzlfO(ZWq)}i-IWj^A0fw9p#0il
zSP>+DjaCN1a?dS*4v}vkgIuV5laC9&zc6|1KPVoMzeb5O2jvaXFgRS^`Yu=_<a)Y6
zBvLM-g=ds}AB7mB<-Mt}H%4AV6LqXyOKAsj^6GY|h?jTA0VP5H3*|>7$>)$)Bv~FC
zj><#w{4TH@mLK^Saw&4}U34475qXyj6dsj7bretNm^_O%@9FYgVJKzDx6@dbDgT##
z(Jc8iSCq2lE8U<lM}9d7EV=T3C!pzsJd5V*Jo#6YCz~%%ltQ3DUj8RI3*{Y@j#VUo
zoWcRc^64v}@1)$D<^yMmeD@L5mdgF<a)&ZGF0;ZXBd<zC56k6C8evR@JSYI9QeH>X
zewDnH98}fvQc4#(Ef@X?&KkKW9>$!J@2CJvt$bb$RMg3PgP^xw{?U&h4e~M{ur$iu
z??9kQ-cHNyvr73p<hpN`C)19iMczqw2(-x`6a)LbJpBJoZ}~#<?X=6U)S<FN-g*+`
zqWo8Kx?PfgLj(F{`6vyuSLDCa`lM5yM+eEe<SXmIa#g+}B%F<VR|d|Y?VkMOKfu{9
zub~5#19Ia$7&9nemIQ$zxhFZs?#q9z1<SBJlstGN^3^mTK9C>TNiV*f!2!yc{Cp|Y
zj?4WFsGN{H$zAkFzMoEKPRjr2M&%Ag9c^-UDlXE9<fce<(#~m*;`U8w+N;=dA7q~*
zWdk09yJGjt;PFr#6oGgu`a58nmtt8SjPX`XZvv=~;se_J?pORyj&MK4LrU`XS2VW3
z`T&KA?hFr9j1QwNNU^9D(7}osxj+d~OkIRhnBrsstuzlP3h7-vsIXJILb$@9huskh
z84bu$3g;m_u4u)!v#>i>QNRI9oFbH#T=5EKJ5(eoUf@7HS+R;-Glvvc$SaYqNC|{7
z8HzWTLM~Hr@(pw;OOa1=Vz%OiN~q0I%+mh<+?~QsF@k)>JsxTc6bGMziG_;SDB4=2
z=(hv3Sn-G)fF~6*euKgi#Y)N(Dpf3`gF9u4>9lG;rO@7n-g1Tia}cOhta=FoRSMqI
z;H*}xX+!C>Voff(U8C4~44id}?;fM;xat+Y6oGC~{9FtZ8x^*%f!3s$Lb*$472f1U
zZB`g5P|~6Z-UPvO3OOxyS`~N0P}!zXwt@4!Vt+Xv!Uctz0+j8FbF}E_Q2cxy7G6|5
za~^V+6q~;SxvW@E+mb5^EhX4EI~6_4f!3u6ONORyg`8G}R~2D5A%9KLLgC@-ir^{e
z(+$O%#lXI)c!mxf-BP$wTaV(mN3i#{LQVt39mSp|^rctvH>GUcRV*DwWuGFq6y%;_
zc|F?t6>nbz%7Ef1IpPML3M;uvh7_KZgm7Qs97AbXF@xr>5ydV#lrXATOM~76MI+r1
z|4@-{1lpKFV1tTrMF`~(O(?cg=Hw#<k2VC8iU5kNxGGnjK-*5`{8wT9Zsi%;zU@)Q
z(XYH$*+l-<eM;v54}$K>337#bD1%=?qo?xubCB>-en!Woyp<d1&G%9AC@W;Y^4bxo
z@Kyfx3FQ2g5gmZ>SNhX*5}-^VSK~qDnri3`SJqRGafI^lMzlpL)yGj8rSzv<(rD$l
z6vo6Te{|AM8LPZaXEEZG6?CmZyfW!C2qq{mQ_wY0$)e9cN!dghU&+dJ%A`1?3>QM+
zu+oKG-zmy($a9#g?4`rXN0cI8Sa?+V&wP}QDPO1pXPQzo6=27e(~<V$lCDfxgUSr0
zEP=kiOr@Q6H(AQo(;(T(V~-%8qf~prm|W#Boqj)|9H65*dCG9&%vYZL7uW^L727}x
zl_zMdE>d2Y4who&MLWnz<pcU%OO&;gj#a9x*@RA%DVekrIHe5IfTdjdOECQ%WQFp?
z*I=zu&ZeVD)k*>RsZJ};Er;G3<<<qT@QiX58C<Je@EsmPoziy+(CU?6Z$)K;GVLN%
zG%A1k8Kg-$V;L&XD!pljZB{NOKSZmth#b6a%CE=)abBsWf#QPlBWzxsF73+UaPV{}
z%ll!)MddBp6kbxclB?sg@~=a%;)-%URzfbF%J(VA+@;i!BfMML?hm=EN--_^uPM#s
zX}PZ4OS_vJ%2^&jxv31>36@*Rwa>%s9%V5t1#T-_zCha@Wy#MV&R%61xnJ)pyJ>sT
zr(8o`-+Ri(%qaCMzoHbv0p)7)Mh+^cK7<uR%48kd?klH%i{~_~?A!!0qMR!S=cv-_
zZCLm~$s@<bLuK=3kTK;b51Pi6>Pc8Jp_JbO$|L1FHk2lvO6?^yx~ekB-Rq|MJ`)nV
zR82<#vs=|e3!#0g|0uJ^T{S%unmklLOoO1eDv<%=qiUdV_I}m9^<eQ;!4r(HLS?4p
zE`QbAgMbcDeW*YwP<46_NRaBG8XAICvuWWMqH@N4f?}xZzwf{rrfMAnIiT8{37CT_
z0S)%ys@L8FiBP>ri}y&?!8w45Qf(mTV6@8h4U}S3brideRV^UTP@F28Ccb!8=QNN6
zm7YSGi7NLxbSX(CCKpMvs(U9&DXMwSA7DnR>b>27Iik8rqh6Zo9=&tNRZr6TFJ0w9
zPQDD)A7@a?RK4^&K(kbqcTkzFQoIO5b5!H6p)yx>ED4n-RAJizmZz%x7SQ=BVLdPl
zRD&x~DpakIf)uF^)8@5U)#c{IQ$ML%Le8KP)oS`0OI2sC0H#dUbqkfJRPD(yzg(rg
zgtiLR7j&;&rE34nFs4f7|2BTgYE|t<pq*9~(kNY{n!Ov9XH=Oq%Gav?q`ag$)utTi
zZB*61j8c>86^d`3RmFGFnXzV-&r^_ZQLTCdjptOK8lmF6%9x2>Tu`l}2ynZ~LT8z7
zsnX*B+M_zph5FknUkZ`mQGHF*S+8nSF4W&ujhCZKeX2e>BzjLZjgHdys~*s~<N;MX
znLViDUPjxHYCeWJr^|g+UI<hStGdg;I-;s>f%&7Vv>V`gpz5Y=(L>dGO2{2kxwhcR
zjH_%k5lpB`(;(-ne%u?JJJe4XLhnwsfzHafsl5|Wxl8>|D9CPg!wV4DqyFV@u<TXS
znJSlkYVY-ccDk!)e~6-oI+qgaJ=HVFLFJ{kJ^-t?+CU*7A9V+fdi&Kslh?^t{o1>*
z!cTpY(qH`5{`9g0s3Rpn2~-PdBNL?F*n(29dW1fl5cTgbfF)G@I|VAj)ZeZE$^mti
z8X68d)!#_~6Rw^XjbeoQdI?IA>KVQej8do2I2o;Gi2xd-eufr#vFerdLdB_*enKf;
z{SQUc6Vy-A;f+M~Z#1hVscY`whe=k4(U#?qx|LiGht)0=DNj)kQx0sZT1+eQBWh<1
zIc1KjzoX&fnEGvUil(V=(H8Nz`VI1Vr>o0mgJh@|lglqty^-#s$Wq79W-?oyz8+{f
z>J=A(lB-VGh#sC$8`^-Kr+z98BwxLi4sR5wH!lQAq1xvch!?3prnpeC`noe85+~KV
zB-ECu4=x92shYD5q)ffD3*?l#fi|(_YWFDgutL2LM!8g~_fWE8mAd8-V5-%DbWP%E
zwM!F>sZnQ^q4JFS4|?3S>Q?e=H>jhJpwy^dlz~!{dV4p(&Z<9sobDZKR)0xDaf^Cr
zDdf+opQ04PR`sew=x>|)%UB4WS69=ShzshEV}RYRe!Uu%9qNa)R=cP^FUNDfq|T;`
zX*$(jba0?c{ncY&=~f3l53sB17>W>HQwPk2+1J&Lt5Le8PXB;BEj{YDDBJzEI+J#K
zch&B+i|kW>Lq45*YEK#32Gv_BH)cqkMF%zRtG8QW%&>at9oRdfZds4EQMK$<lpd%z
zdI9^P`W;F^8dKZKfikXshq6y6)cY60rblYmN(fA<UqrT%)5TSD^9ShNq46M}_fAa}
zExp_{-gH`WmqyFM53^TOaUIzEG?&jo&|RaYHH?>L!62;g)`SM5(nqs|3Gw}!j2y`M
zYF<1J0Y6O(<zx73-fn=|0h%t_Yy@h&-hnYengJffoxz$`TC;^{#^~J%)g&!OW0<D<
zAwUmkqI*y}s2N!Vo5D3WCx9KHxxNH~(V79u1&`6p*#+@f&Ex-|qY0X6<Pb~LAnO$0
zfyVn)v?XhP+X>SSX}+F=(qYY%D=4LC4!#C~RHw#Zf~F&yp55rvQH^;BjmI=={z55D
zqf~(BxW@iHG^K0iMx!!AbL>lyOwBDC`m;38(h56U<B<#tPiP9si<+kyV4=VHnl#$K
zm1^?nPL(pvH}rO%(pV@XuUu321}ZBw&cn1&sMOe6Ay}oEyA=wnHMJi@@U+I8@@s1}
zS_)R3!9Tx2qE=%I2TPqMatlbkCf)~{8Z=MRZm>}^a0=K>nx8X3&T9N9$?=>fiqe8x
zHSw2#(xzEahqm(?F3pq|G;5sn?zC%`kbk;Ev*T^lUeq*`7xt3o!~uYIY98RYrAwE_
z76J3SHA&&%ysDW?OQ>s_9{MS-Ykr^{gd3W0ihkVGj2EDEOB41cIPYj~ZGl{`W{it|
z-qlDc7}2Nshn&^-G!NgR@2_9O7oc`P6T20*4QeFkp>RmkyAgJeXvz<ua#XY8dyog3
zFCGKvL(N^fzGX}^gR-H=HLv7Bd_r@y0OXNojT)7cnvE1T+^OBM8XDZRztEV!ODnmJ
zhp<<>#uaV*v|rDo{hzz`eM-*s(pFEvQg7`Pib?utKa!&4r~NGwC4VjV5&9IMb)%qb
zur_cO+CsETH^Qb+?aSokJE&bt*~Q`77io%((0=U!h4I>EBLot(=5C-QYO_zFl%x%C
zf+blSltzC?a7Zg21lnP(*bPRdXdUl@HC4N^6qQG`+i0VERNGDNreoUd&%u(W_5Tel
z$F=>GJCUx99ftZ0?NhB#pQ(L7o2)Et>Q|7<)~=*IOO7^o85HJfBWs}kgm!xf+VZqV
zO%QPAYcFjBXo2=2U0PhI_4xo2McM%`m|v`YjZPt*)Vh2Oi4tu_Bpz^?wk;W@Q`$!}
zU{krahP>Pr+Rg97rb_MOG+I_^)f5P>)=n9P_-XBn6fmgKo)3Y*8SP$j?$v6&LZGkC
zsr_|6Y^&GS(xq<=+JQa5Zq$AvhJ2IuqyHdrR%^@#OtbdEPN;9yhTlSEn>I8WoaeO-
zUa+@A8?pu}E^1xLA9qRHLY$pi%l9y*OWQb%wr(wp&Nf`t4lG6Kns$3UP_Ap8^Oi#W
zEp5vRkRGj#_UX5^zb(Uqx~mN(=YF5|hy{Z8v}`Nd`nBg{VcLN9!N+JD)E-Sj<*@bv
z?NCRwF^fP(we94v9MiT_rpvfiPQj)L?Z?w#udD9fzbNg{ZQqQxow|HyIV|0+`<Sjj
z+M~NndDnY&M~6|`r!&<9#$BgO0E>r?L4Gwq-5$#G@z=e%6C^-4i~O~Lx(k$+7^K@m
zuXV7lnAW`^I?+-*;82~2j|Us3TQn7=1G-)02{@>$d<n*c>s&Hvfghnua)&jMx}a4M
zjM6QA8;#MrMN$|Oqf-Te#OexKfgPt?NWXo&uAa8U3AzdkNTSY*2^C2?uZw6)*3Bh9
z;vwDc_t17&_ev!6rs$@Vb0k$aG6RMl(bdtp^P{@-YKpWU(=Gl0*lD^N^2Z<7y+p@K
z({)Zd?2@6o9*R<?ZWRT&vUEvwrD(P;gN}9P=x$X4EmwCs5NIcK?^M8wJl*LCsL$8U
zFGOX5j$IG&LR~nyWQ%ln7lEZ%_YNgFp426ur$}FkZj%wUr8*gPtxUJb7o}6W&#Wkw
z>vCwgtk89MqExAyLu-&K-2#e%R_lJLLgi_lgmNEhbPg7Nv@^OHaWK19mquaqI^DBj
zu%cd9Nhwziy69k(&gvFZV5M32A9+QbExJP`fN9f}hoSbo&axTgg6_quu=}F!zqK&t
zk}lm9f|qsuN>p~~TwVoQx6aEBy;pVa?NE3_7ebrho4PkB?r=*tZ!Iu;bZ>-#<+g4m
zjmvj*M*6gSb;+NB<*x1#?IQb}x>FQ*zo+Y<U#(wP@G*Xh0o_$ftr^m}%|<Wo>w0Ox
z7}izspm#*~E(7wTx)rpgexO_ZH3S~&Zc}#0m~PWYXdBn<RiSc1ci$7%KhiCu-)B<C
z`vU!S)yLGLZHGQ>0F^uS&ODkI-1MeukX`yYSJ0W=`j`CCxJUo{TA=OKN7A-vpMK+1
zl-%_LG%kDS=h}hoseiczpkDfCXw3K4hd%@2qtBMYwEg<Oav|rdFVTV1Pwy3jN`L)K
zazq5^8B4$!s1I<yiP|826&(c&)~AqHG(`U&g}g%bZ{@<6Fn!Q0upH12E`Wsx^)ZD|
zAFl7Da7%>V)(k@<_2Ey#v?%?{72u54KUxL7G5YoU&=#vdzyfBRzV%&@c>O3H*h|o_
z`~}d7`puQ}{Uzy}$+l$uaT=%&>8pF8>9BsBc2_C-bu<R1>UDpC9MNy?1olz=#`S<X
zroTBAoN0Q)7>qft_oF1ZbiL=V0L#$Nd>YW1`k%>-pQWFq7cpBuiyRR-dIPPla`nHR
zp}zw;q5q7s0P^&2P<C>@{>CwY7U+{#fu~TP^BNQu>07^s`NjI2X(*l4uck8<CHkNI
z09vY7eE{(?eF5b)ozh2<`?Xwen2u6~ei@zBuGBB2TeYh6B_fzst$%A31WxNau}^lo
z)acicSO1K@I|G8X`W~9j>h$Fyz^>Q7x(J$@^uNZV@~ocmB}&cuIk!=2(K9IL_nf|R
zCeT{-nh&9{P5;P<w)6V@7XfxbZ(%{8UBB8FdOP%cYhe9FeG?m{OZsHGQrCG|KPL|+
zUeU*^0Mn^|i&l4C`ovcN)2){pAb(YVA{lMh^e-%j{B`{zF9_byzxNkPH}!A)3xQku
zeu`rB=->ST5BRqJNxHiKj{b=_XzJDHeh-$r`W3%{rBBbI9Lsz97ZbtR@6>-PLG6Hk
zDIJ*`)UTikcS!#d4R`nTb+jWN)<1m!EF=2Br_eU4&!-*513kYJ@(=a)z2F?ve@QFs
zas5&{TsNV2r@LMs=?_TIHmQ$z1ZY=7odT6R3~$m6<hu;pD0s5l;7rk>c8|f>53<)F
zTZY<wh9pwxZm?{Dpoih(buie|;QB0BybL?DQR!_+q_5e>@ZdY3?Kd>hMe)7{X9wE+
z4Bq6h@i*uwKoVehJOSc?hR6THV-7O(H=#?x1{MXrLky>#Z198{-du=2g&Cs0hl&G+
z;z^Va8a~JY2{){y;9P_u?^g&$8qQiE5M?M$M`g5OD|!B744+V{R;=L!iN_i2YhhZv
zVa8RI5)2<LL|dZa{l{TNl3_s?P?8Pv*P-%|A?_OaUk)3Xt6@!w;oQGyOf}@t%XY*N
zWyFtu)G)6VDvlYxCI?rVVM`uZG7Qg^Lq5|GNIvK+!-+nWvJFFIc8;OV4Ho7arep!-
zghBW$1o8}D%|R*O@GuZy1qRXY5GXW!_%f|OiwvQ(St>ESPG`?b4gXC6Xqlm55;j#B
zdheoCX*iz)mMX)nC-IzX4Dpn?b;e*J4`8jqm9|w4hG_C(H5z8q2;OA)^HY!u2Cp5c
zY&YD=gu)KPhC+Z{G^F2w+$BTf2h;HVT{c{%NXHe!at18zG!)U)(Ph{~tHN$WAML@f
z8e(a<yJiTdtmNy46_h-5!*IC;EH@3i7sJq7hSlU&>@oa%8f~`?KU$&pj^WA65brf?
z)1zm14clg-vd?hw3CP_u)X=FZXTL!_19ZUfIeEPX4eECQGh`4`_S}7g+bAlB4VN^4
z88KWu2hK6W%k(0S8)j2(%7j5Y1)z@%d6axGX;@Yb0as&}2l~6i7+;RQ>@<Exan3!)
z3p5?=HE#SCa{G+O!@%P1G#1j7<6+DvSGK1y`Z1{YGKSHP&)fJr0}A&WIqN`tjc4wo
z($8os!SCyD{Gb#t0mgVG<N}SQwD}G)J{=29!N$|&U<olUS&X(&<72;q95BvAVy(+T
z<Kkji7;fA_yM+j&^SNs<D$<yA6Hh4GD5HN?iZSwNdlPH?Z#RsIH|jDWm|(m`5z0iP
zo+h_s<I}VaJY<x)<H;O0TFH5wV(g&g$W-H}cThTJw7-W^n$bdD*yF};X_!nmK1b)G
zGmLB0V97Lo=cI2X%cwd6&}`$wKCtE(pY2B}&zLiU9_AZAzXsL<<MVHUv(R{M6G)Nq
ztD~qaHs<~f(38dwHlh<H#@9XpcB!$DVhm-*^L(_OGA8w*FXhIiYzR~sLutCNG(Nro
zZB@oMu9H`#+89q^wbRB}>P3z5`=5YTXIx5wrF!Gc6p#kvJxXC}G_tLbZ!+%r1M+8$
z>&VO3Y-E<8vc+gKK>VEX2IYjd8b@i3*k&vefb+a@C?9R@#>6QA>o5w>!NQBiu9@Wj
zykuNR5z@=Xv18!5VsyWUQm0XG1y7gp`|B{j+qlOU7G5>Zlta@sW7H@ruNzw%z;eU5
z^bq838bjU#xn=b7L1m9|9{C|}8wWlC=N)5U4BC2)r7xm%*LX7)HuV`dXHfiaz_|W4
zii5@_Do6|&$D*Kq#JH1o?W4wjZlD(rjPHL6^3eGC0X&2;W7J1z8#hjOKyK35OB0Z*
zY597v>@dL}hxL?+L8nr8nTDd#-`%FK$(TK+40^5hn))~>?K91!D6!Msq<IJ!57YfW
zA>nD7O7oDH=@W{<dYg1F0o2!YH44Pfq@*Nre-lFk!2r_~%6SSj2?|gOGVR?7lwi}N
zub?o*bdlb<P}5>BXbLkqX)HNly88vpK4_BATODo^cfptlr)hOEKqF00>meUy@_7tA
z(I(foAQ5Boqx6?pQ#*wk;!K{OgCv=1DK{nAbleWkL#AgDM0GiA+Dg8&6w}iU_?c2o
zdoKg~h-q;xDvz3siy(K*^js)NnrTHYSdN=!oCS2c$ywD2v<%bNF;JLk3hf8UGJW|b
zNVaKOF?e!J7TW#hn(FDm{0Y;WlwXu*`i$~}@=edt@~Xh(LXPP|QyQ%-icG>}$Q7Gj
zn+I~zWGsTh5>urH_LiE~%>`$fY4%)Ho-)1Qq*ZviX@s^C6{cZ21zc$grDa2v>GDTV
zSZzA_HXhJv)3jlb8q-QKIM0|8Z-KMclv4{8b*5RtK&v;!Rf05_zM`qU(e#LhlqS>k
zad4hB4bZsUZ0f!WlonIuJ22*)={+N@KU+<!YeCvfKT|^DdDG`>QMzDyjx23AeMR3&
zhpB;9vlmTU$vt<;WTyj1mreIPq2h|^!~?K&nttko*<Ge16eR05acC5{ZmJ7{+znIQ
z9JJjunYpOEWhz!duE#Vok8XOoZ4%c*;*RO<chTQo)2Bb8@vcdG0Uhl#?Ih>qJ<~W%
z)cvMTI=VJsa-~$SLDM<<Duzr4D9|}#`rvhNj+(w20N4Xl9J!<(ntVw8m}wbpO~*~W
zCm}vz`ZXBFJTmc@(n*I&(^v1pC|C0s{meVe^T@ff(`-Bj9yjxNEK0k~Z{$I6ues(!
zRPHn1$cBKs`E}~AhuJ#-Dm=~pbVA9?e3=g`yv=uMj`A^|`W~hI=KBkQ;%lC2flYqq
zYqe<eH@8hg$r)hI8He6L^GhS(2{Qjj9>8GpTjU-LF~4s@Td4U9x-TQlyk`med%*lJ
z<qjS+w>}Mp;pXeKMvO4eUx23;Y0i8eHpQ5`j-V~p+(aX3oH>6kz~aq+w}2(VJT{8Q
zm1zDs0#+nB%~NUhoorrD-`^qgy7}NaY&O?JQ;PXAop4Gu|47@DBW4CgBaWJ{ke49M
z98SBV<L04Al+w+5THR%s|D)4DndVn12R6&B--WhpGrJ8W$852~rd)HwETEh)`*gsj
zJhSs%iVPK+&Cg(AQ)K?^CTfe#%sALxYL@;DQf4-hFYA<ftq~n9H=n-`6&2=5TJBex
zSLLFu%6y7$rl~e_%`p44d8`7OYRp?Hkafm9O1_R-^WZXo)tUFuJ6><TLwnK&bEh*G
z5{>2@N?UC*v$Rlu*4()k*v;lB${A@fKS^7}bLOcIRJNL#bd0FYocuo8&YQ1LcF6^E
z3Z3+8H`n}(zI2$Ez6|V(=0B%^Tr%%sz~0N|>2A<_#T-u=Tb*Vb1vtCRhrc8LT(?=$
zi^i+w*Y<;4GfQ_t(+zXD0)jWqW^z5;GS6E8!5*_a&8D}_8|VU*JLc^a{_i#WoI~YZ
z^Ibcv?=#Q+8<qFW7hZu}zxiG2_JFyZGPVZI&6H3vWF8`N-@L&<@%Lf#FBFOzF>lEQ
z=&1R?Z1m}Yc^2(EADYA30W)Tf90KULIe0rNC(N6ULenGj@q56YG^eOxsH>$g8I?OM
z&rlqEr)B;kaJpIMQ##5n%gbj0z1uQ8fJeE<lDQE5+-tG1=zkaXSw1=qR(H#AEHrso
zo_G;Fo|e9wAYPW-%@FjqREL82SX6W^!hXxE^g{VsE`JK*XYuVso4;iS`FjH_vnT);
zXsOHxW{^cnPL*KG42s`{SX?t85NdIu2xFKfE(pJY^MK`davLAC6y?FvaLYWJ4I?aa
zN+XN3tfTN&ltr-ztkIU`Z$UoBvd9PK$66*SnIO(GTL_kT3;%DB1WP`hut>Bly#dZ7
z%T$WpCR^M@z&vEJQ^ftS<p=r+Q!Jr9s7!TQ-W&qY5lis~fF89({snT(@+XZ6X_m))
z(01I?l!D(U-IB{iTZYAt&R}I))=}zxjwPBV^IXdu$}Kx#*?I)nd6rq^TFSTFqvJ;f
zmIQK67Fu%Y;TKt)l%ZB^(bBf&q{XQ{0JIXz%m7$ZYB{k2r83KWT56uM)Wkr2xn(6~
z7FAeY3x|BA<=84<S6RCEp;T>giXnH}l0cbIH5SJP*mTB{od!~CIZXb`I!he+a_cQ4
zbAi%eSx%SwHCp0zAWfE^oK;YG)^a5Vjm?%>4^i7<@uuX5a~3;gcePrkUxdOo%lZnm
zowsbH0sVqy%VBi1-Lma@$aPq9BT>3&870TbCCgLSKrUN8BX8Li%TbCZbXxwSn?SlO
zB@wWx+fpnA=2c7k9-9BISpsRVcHMIO8>qNp*%pSzo0j+gKUZ14I|`N_%UA(eZd>N~
z0p^ZndI?Is78V89?^+_(<Kg#NdfQ;{Jxk|fc)<OZZz)rHz~c7;N`n?Ptzw5Pm&O2g
z-;&l0vxhCK1}M{W#4=rgK8;#xUjfepi|b{me`uLX`<gM!03E;?x7;MZ?S$pZN~m~b
zx!?)TNz0O3Fvit7cm!7Lur~5w(@tyfe`s^F#*^E2mvt|#V)t6_6oO@+HS{A8ck3e!
z?Dep=$CLlX(|U*t6TPe#UqbDEt2hEYzSjAlL%pAMGac>;wB`w5Q;;?HbASe0U0YEZ
zV&z&uLakL4gbA}Me+M~Wokyt<2d(p$!<caEqIn<@*5U`?jI{3B3zjIW^AGeT)*3+Z
zerKHZA7AjqTc=P`XM$Bsk?%xn8|679S)=seIc!zZMk>Wx`ypUbtv)NzcFekQ1eIx4
zkLxHMw`Tnd>`dzl@*ZVbU#8@tY^%=+u;f@JwBF9OZh^no<%G3l0xWq}B?SQTKeBpL
zURHrMk=z=E)@gLougLnn5D&4~T0=pnQfm>V`;}P_ggontj7|SYJfIq@OE2WlSp5T_
zqSop<2+lfdYb)gHtsb=FYp|ZD5vI{P>WNa5l|h@rvsSqk9c;F)*Q2t<TJ;a~wOX5`
z_?g<QU(ky0yfu@iu?yC76n<~F9+!Z#!<sh&xr<hR=Qk)`vc5$Um#zE0L}#v8dF1Zu
zwrbZw{Z;GBlmvdwx;7UUUbp(t%XY)Mi;@s-T7Oo6rN?@c))2R?^XaX=WBrJhDZSQ(
zw4%6cU9tt0ebznUFzuc-!Uvu2w_YKi=zx{+5yh?st;+MTX2_bCg3^6!&Y$2Jww91j
zXvBK{b(BV}fmuL%Xx%{@<S}a<?H$Ig6O^_yVa=hVV~?zxKSJfC^$j{4;A-1KiHJLF
z9|fXvr)|l0RJz%=1%vFeEu^fy-L~0pP{e$XE!-XQdu^GtP1tACA3~ozZHf-4_p+^C
z0-L;Tf&X_&*`8jHlAp~z0($*zBSlaVV9TX(IncJW5Tzhn_a7*Q+G3}ICCs+ihSCAs
z+tUGk(6)CJeF?YCO+{OTE$bt?n=I1y;~wxt*>>Y2b&0lh&`kz0wmp=!7i*hJvv-_r
zDjjQ!x6PzcFTpnDFys?$zds4IB-=}wXiK)a6`<{qt&$E(q}pEi0ANRKmAQD%M{QEN
z0^peKN!sM3*?h^lc-+?W0K}PTTTLFOESu^)V6tt$#Np>UVSBXzoyoJgkHeUJ+YfV~
zu)ubgob-jZ5eZZj*}nc8pvAVw=}NVewkQg)l-O+bu%gs96o<Al+xBB9owBK3fOxs>
zOE-vD*tj&hSK6{3M_ZNC=K3~NRNJ;DLH@KYLV`Zk*kZ}OaK?6J6R>M-A_vgwYz<0C
z)Z1bySlnP^-3Di)%}86HCR=X@N@s1Mw0k{gdyH1yt+t4V=u4Z;n>=vmZJ+t0@`CN;
zesH$i_9j3>ht2uMQb=61HD3a`WGmbbw9B^c-|;N2*i;Ru?6lebLuHpO{1ODaZ52JR
z>8i~q5op(JZZvFMw|RXH&KtG`-6-9({aB0AEt`KQde&nrcoyBhZA%$Jx9`}5(;?n#
za~?$Lt}V@(3)Vhc0_CCHvt`g2IAB}%6dDI@Bb0|SWV7)AbKe$6S?9wx1MNviY^rhe
zY1B6M1q2@0X3#e_W~<r`GHyFY@63d4-HQ--WUGE3>L+azGoZ-T{^pOU++p9a0CH~j
z4o{k~cG<r!LE~<F3T1`uvFqs)slE1c3h;Q?zd4MOr@dw;IKAv<THJZtD<~7*$L{|Z
z9>RY6CsV=cYyXZiJ^k!?KcUUv-boJe0DCm~t^@6N=!)AQ``;(P8EiMY12e>aC6Ugi
zhuS};G{Z3aGjkz$z-~N?ZXdL_ErUe3y}1FFM%a^og=vxYxlJHZ_OTSmN89uKU{j3U
zO$*Rid)@+w$Jx`#w-RsfSqGE^`(HG8CE9<>2TGEic>*Na{^u;n9kQ?cc-oZTT@KqT
z&cMVY_DBlT9<{p#0{fVK=QAj!**WPb9k-ua0G4$7^R#fxvIo<vn{D6tfB%;KVI|sf
z?Qi}G^(X9pA^p2?<!kK**i>luq+z|tK1%DMV*3sQDo@(`PD8xZZX;JknSCm`bWhn;
z1u(7LzA7A*74}kZa8}ww(m<;0sXw6C)%LGw<5gpy%z<TR?DsB!v)1nR1uE<8$qI<q
z+x_X(Q-ghtldNyF2bQ6>$v$f(c+T3d(AuThzRieIi(M28v(MROw_$dxokt;pHhVXD
zi_hC_<nOs)mraLwyZxnYD0SE)>VSFCew;p>OZH*PSG#O49LHn6Vt<8P!JT#{CBb#s
zYuqT&wA=1Z>7Uo_avHjC*ps{=anr6{0<<3c>y$`!+m4kjz6yKiHmL8lpQR1KU3)wI
zOnvq_A}G9P|LhX5`|T06z#OnI+YFXLy9b^38?w(OU(S7dn=8n$J@0w+Y}6h*l>)&J
z?B6%w$v(6Px`1`e-au=Yal6Z}kbh+V?mo~a?Q7^~a&-ijK>ZHKP999#>8PLqb(dq=
zZHVu797+Yt9!C*PaeE!_&Vi<Vjy<%Mb$9USJ^>HMm;NYuI-aBV!OP)~m(%Iu?N~|w
zL*U~$M}yFQ$H%Kdd>tVSu=+WC=@a#Lyz?zs0vtZ%o(^>UL8rrl9J`}Hf*sG&`r?3N
zQ7_0rM?NL=g*#rR0X4$0kn+<b9Z&oS@hAtk4dT&`!F9llaReu#%^B-xH9=vVgI9q*
zB{&-C#YlAU{lJ>!c)JZ&Bs&gm2J0cmF52}Tc05&vwiL(4I`lBr(XkL{M;wo)L;R?t
ziVi!cIZ7yt?6@O23nbl9{XTw}497dm!I|l3UJtM=M<%89W;-1MiXY@Sf-6wWb!?`5
zs1uIq9{@Yg;Z7M;g^m?JK)%SKI15tj_=X0bla3zRdXzYtQz2LCc#pP*WsaUdAb!em
z+7FoJj(S=fRyY>Z-%M0G{OM$0l|%X!O4W`K3h$hDI2Ue)M2%yd^4-oj-lD})tz+*U
zl<FMyV`!^)yhuxe2FC*0EjK!XX$RBfc&`KUXC2RP0cW%0xnF?Y;<!W;*Exrlb^@)A
zsh@(hIgDOlIqzs30N4e`2Ww$yyW{F&V0Jhfoi2d6=y-x&-75}F02(_T-%=h)mtzy{
zy}KP=bVbrtNA}aud(C0cp}*H1aXxs?Hyonx!TCRyz5^_(>v`LImj!ky3%mE;ZGiqX
z#+bxtVl>gjSYp(~mSQxCEp}sK8oMabxHRcS6h#CC1Qisi(xfV&ASk`4APCY#RBV8V
ze(&V_KTjSfbI!~=bI#s!&di)kw>_5w^&b0Ns-U=MABhFFxYzzAEq3nPhf%3<pZ&l8
zEwb!Knql{$ecLObJhET^h5@wS{vmz9>#=<XWm})vJ5pHhsr`<#P<&?p!(D(rx1Xqi
z!2$cvXfT8Jk7+YFWIuNu%)hX2?*Qnqy*s7-U)t}hhscQiXFsFwmHjVg(D>SZj1<sL
zI_X%TIO{y<1IjKs-$@jRbJcCxgjP3QAkEi)T>!;M+;t2^QN47pDO2aI%NY+Ze025e
z(CDjkr_v=qT`66%{<_h%AOX6`=9s(#I`Kt#AE>)UZ^(l>-%xOebcGfeV35vGgT});
z3(ATe(fxw=tw9{D`*{}T>!_~(JG6%AesKdirdvJ%mO^#DjsOkQS-XLR>so15cU;%k
z0xm-LAyt+~>c-RZGfMZE;!G!WEfm6v)^UN5jM1&F!Caiw{U!l-N*6$0oYr|$$wsU$
zgPz%jINcaJAaYJO(E)6N?)pB!B<ezF&yl2iMRk<Px_~r{Fh!@X#FVD$a%d%UUN`R*
zu+wx6ZQwF=uK&P9rtWYX^s;n+Z-m|j-Gymr%+|&C13E`{a5~g;b!+CpUY@Q-kH&n1
zPJ0rxK<7$vmy5a}I=FC2cQh0-g*p=omKW(hrq51X(YZZDV~OtEayV0}>-`RP%XQo7
zR=KA8m6oR0bt~!WuF|c#1WVPrnG2v$qmxm%wqDo16$%ZyI5OX;3y6fm4V_^}6X;Ey
zO$|VA>AD9X)1u4x3<g_uzflF$9bE`Q;Nmu&Xe#>Jb#MOz?yl}Mt@b-~^WTDAr|tsP
zt#s+i_kwimYBcbvM|Y8uruTFK$Ty06bz8GBvG;X>_aV}!+f@PbKxc07fu)DKx4s7G
zBVGM$nCRE}{{$Bw>rT)L>WR*Xj;}w}DJT*AOt+Bsz|VC@>GbY^?(LhfG^krg28VR-
zTH?2Vp_8S84C}t1ipG~ZW;`s6=&UJ;_)0g6Qsl37!7IQy>5HSN#>83gk_Fa9zn5}d
zuKGh0(def4PJ+IN{vPcXJoUw^VBSkVWgYB#>wl*VhmZam)pYyndyPT-^j);x_1DKf
z1s9<I#~6AC^x28<H&7q(CG-yJb#y-QkbdC<s0Zoi`%@vtVZEAGGDq~ge}I0letrf<
ze^h^tmiZz2KH6a((+6gN3)Rp28zN!)I*OHt>*vz9D30r8%RnOZR(`;a)QhPWE=vE-
zU7(!M-zkFI(fVy)gT&}7jDT`dZ|w$WPU$^sDG+yBU-mZi&*=Mqg%@Y_;kJN@*T)z`
z<DC9icW?=M_BG}rQGb{+Zpr%NyJ0>>A8H4fRDEALMtENTRSHDX^gfi>%+yDW2FcRD
zSO8}(=vQ<>AzL401ujS5z7d$YdIe=`40-x#6f@7)+l>IbK)+x=T8s35QAV{`pIHm;
zvOcW~Xjk+TX)Ru&H*JDKslI@6pjY)<sU)CG|ArRMl<V^gF^Fq=r49-edTtX)rM`&b
zHC1|tAK_@Veqk9JYxHy8#cxn&&`&Z#YrTH;UAW(%7wrRDqdttTgd6%#0>RzX4;Vw^
zmj12nkZjg(*aGghUPtNd7X9!PaIN~ibXVQcub2T#ZTd^0@S<IRvI;(R=p~V`)T#fS
zaz<TxTPon_)?3k~)1x=w7%FZOy_}-2y?Xx=7#z}%8w0cveRVoyUh5MIV9CWHVKlJ!
zJ0w4Xf~UicN)R81!Hsa#-(epW?L|7=Yr>SAb=cbhuq225XX%G=c)J=RnGT=Q*HE$@
zewYfdJO_OZ$VG>b478~$c8GDs=*t{j0|9f(A>AIGJq}J)aOR1_S*oNMb}*&iz;%~9
zZ9+YE)uy8_V3+nP42JCbjly|RyId@w9=GdI47lW78;oH-d)Gc5U`4x{C%}BkuI;lR
zQn{<+9dLEK+I}%WCSdob(J&FZyFCOm6usLpAK1yei~d1l`fdwXpyllj`U@~6yMJ#$
zU*+x=+Ctpi9q0*>ySvM%=DvIPdn&lrzq@4@ObqUpQEBJP-F;?IcX6E8ig9{7Y68&c
z=h#nA(u0nz_vn)&haG29%~YtP$A0L?I2KcRZ>*zS4omTl#-<4TCpxB4NH)bWGXRol
zj-Sx;Cf!j^$7eGfYkBl#I?kn&D7lW?XkVY_IBEnVEO2z+1@jjjXB|P`CC8PIK?)u3
zY{NK<9N%@JLX2X^HXF!Xc8ngR8FCcpJX@*beEK5;WsdLBI-}h2rv+%d=J?}3@aeka
z4%)F*IBujHzRK~h7x1Fm(Pt9+Y8(qFa8m0S`8zzUcRXy2#s<e#6kTX^j1qy|aO@ev
zbhSDDLvJ%fhhrE*0HehCuaH4f2N;ZT4E(EO-cN@^4NPG*X)#~Wd7E2|**nl`W-K)j
zX<>fg!QElLpo7aD3`_5X2h8pajAwuurgwr9yW<gv7kk(P13AbR;8^c}#)Pp{LNw0c
zk_7&ZA~%>C|0abi-<(Oy%n3ad*qc$~gWj2ebI|)q_za+b+CZtXS)0Al``IDNSk7Ly
z4L|0b;iZ6^`<Dp+&MTpEna`W4=zIP*RJ#4eSX#F%_=s{N3!CmhchTXO(E8HaV2kdr
zBI)_Gc<gd0ED4Om>@0m}04>X6oALk4ZKx9d>#ymXD&HKSjlj31G<DzoS&a4-L$td6
z{_V*CUAe#>psT7WbM(V(dOrNvsY1(7%c&+}^|}PeuSubcX6>X8Aiu64#DJ+<|Bok{
zeoiidD;ulm>Az_p9kaFB#10BuQvA`o^`?OKZR}|L|Mr8Fw%U6o9{=uVzM_&-cV+?Q
z%srU4E(mxsP4uVFy_lI5u<OmdmkeYd=Fd6s$d~!y6&&_soJs%~C}EbIfnqCD5&S3!
z+u=DB4;p6PvLbBu-6<gM?4GFr^<amKFnylvmrelnV(-wk=*`v*Vgx?y6AH=svKCZT
z>c_g=fQc|xPC2k}cH9M!)2s^xwPM-*i(og7ZIZ#z8FuOhfSqMc>GW7Ut2D@=c#eJh
zJg^g3F$Dt>*;!GLNn*>|fSt^m(4r=VokLmURCekx?4D=;N2iR^*-DBkWw4?7u$0L<
z+5#+1w3mWm>7tHa>Jz=v12a?f7JbGdOY~<S8ZU@;Qgkz0G<6p($8$tGC`XekGOvN9
zJkf_#KA121eivX0L=ShswTq%XA}C%Gg-n2@LeZ?vP$&}Jq%Ci;$R`xomqk|ZLgb35
zI|<k&qVMd%m5Sb`<1SZ4fpm(bOeC2HQZ5>#?CUkr(IKh}yDsXWO+|&Mm$F`!qVK45
zrb^U8d+cgaHGM6tMwCfg-dfRi$`I9wM%{tkdeKYTN;Qb=*Ml^Q8t78FA(~DJ*P9}b
zxlp(z8h;d$O`=a||J^KVT?PxcMJl@CT12flQ)v*litdNN(jC#L0O+@g8tIp57rn0p
zxhp!;2AB@fY1%P&ie5H@>k^HkM{Kv~4LT0hBeJ2}^qxrO2lZaj^_{@JFS`5(`uaqk
z^x>xmqMMYzd?+fV(vwG`658JNi=MrYNiaMXEu%uVC!)HYXniVbjex_?L`$eN>A7g~
zC+HgxeVYKggQ8FAAjFV}p`_Uh(Vth)I4mk30~jZxs(<j?IU7x&WoD959-YlfHrl5L
zW{Qz%Hc(QH{62=ld82P00wv98Rtr$l4My=pXw5K+z6iUSMt&i1vBK!XOz2k{^*?}O
zmC>Sdh*lf9Re>}a<x)*Wv(f*mAlYFwbQNfwMj`J(p~on8Eky1ajs6sR9^!HeJ9vse
zI02u$#H)BX>MNeI0~6~f4mf~Dd;z4-3HkxzZ|IJT5HI=>8d>5wi$E@j&vt=ii@oTE
z%@LoghJLPi6|M8~#J}x?iG1-QV|Y;@-gp^yFN$}PzlGx9>F}^fJd4g)6pQoEz|v*$
z&p$x@irBv!eI??TFJQJ*ywN}*`Kw|Z3d!F#PNZSC7-yFNrq$R#3)~&!EAK+T&A5SH
zH|@srXu9tj?-_tXhw&ft=+`pdOh-hX8?Q4*-)rO5w4-t|X>5eLvq|p_c;RAlhw@ZD
zCgZv>BwrK%Lum9fX_{t$H~uEqX`yz&#OVVJCeS4J6}W>Y+l#>knF#b`J8a@lZ{Q;)
z_7oioHaSgoj-e*s>;(xkxlFZ8;U*u3gG8H%DH?X(L`yrtG?Qijf~1>tQAuKkiMoL1
z*QA>YF|$oH%P1U`V^U4^q`4+HXT$G2liHtPKHntB2HX`BFIs(-m{`*7P-@Z|1hlIr
zOJ<_6%;XJP)n7BQcZT|P6V106eS=9d2e%tdx@aML!(>-4?A|olM$yqGlRv03xY=YO
zErf5IOkOhz_g{;NDhx1pOdKf;-Da{k5!iQ4`ep*A!{jtQVY*ECOlWkQm{U>hJrf67
z<KH)#zX+0jCN=b6d|;9^7GAiR&fW;`kD4~p@sSYI+q7~%X4-ZJT&SsgIWWUavjb?l
zOw(h4VmNMkobsO$rfrWP8fiL2RRz(ehv_pOF{V3txOURCp#qJkOt(=?A=b2Y4@jKp
zn0bIXW4iqbxU;5%l#h=$-S<6E(oAcn!Haa$nRGrN(=?dgN?E3Z`M|tj`Yv4w*``Y<
ze4J}At)N$Kp6O?2(3x*KK*6a3)6zFFQ5Q|!G~fzNmox&c$kdwFM8&4V`+;`Z^lwVW
zmY5pT>9bPPbaRlarkj?cuiW$*6^ULm73jS5b<^xW!1b7JrxPakOj|0z-8b!`{YIau
z;q4Oqun$bn+y;4Q+Wud7#&k6u6nkuH(E!n>rYd@fJu|Io2KUO;k;=$lo3>L3(@DZx
zLDE_BZ62I)ku0KUrK_Z5EWB`&3>=0}`z3Mo&~=x%o1oD{vTg<RJSDT<#Q+aTh75Zl
z6DawJZpTBCcb`HgNb-CK$PtO9D-?qz?DqgolpLacQj$bRZ@d)AIvez*O6Jm*=)B}t
zFK}rR^LCJQ$%D!8H$(C%{UVu?c~3CES(3Uk*u5Zm(hr4f$rW0+<Vb`T3J2#(jGw^$
zJV`(8Y4RmY{)B#kgf)f1i;_jOj=v;P=R%}V@*8a(izLDH2riZ^Tng;Vk}r;<?~3FE
zMQ2MSyJ&q>D(U|Vl2;`I8vs@&`E@x+xg?1){?{d6wL+vqVkY_T3!IXevp}noEMEol
z)e<)yL~A5b-e|0qyk`T^I>{co1nMP!w}UiF+W&;)4ap$wif>AI1-M(104kJdl1w=b
zf14%l@4@_S$((QDT8rc#iYB*8*4IPwj^rh6hub7h?v&+gmn`G)Tilgo{RGk>`GJZH
zIwdAFrY^}TTJm*E-WUbY9?4d!W(brfQ7z&@>9-$4;h1z*4?shuo<kT~m^6}(<%UaV
z8KEyiTKyToBBf=tQ#c{b_!A^rI!I-xG14e4Pz)!fzk8$gw6vbKuCdYwZ(!JQ()t}B
zXQY{%0U9q2oQS>zY0U3HOOzJVVc84PDUaY<w$z6XzvW7s>4M6WF5Uys%ThxRFe{`s
zw2-Ql?w~DtmGqzgf<)3aHt4I7=F=gET7&dy7SQUXD^oGvdTH?$OmKsA+-cZtlvdDA
zvQ7FIMY`Li`)C1pSDO1RxDM$8M;Ppso}%|bm-K&fSn8I(q+-4vY5j3v_ey7PLF0Yt
z5?cH8NiR@12`{K%KtGgTD92bHNew1++^t_am5wJomcF3K#uMplI#~Bq`duinpGmu~
zLu5eu38ga!rCwCXG9(=u2kwQmkb;)O(r-6|yp$%DLVZNqLYux<Qq@1;UQ5qz0ko6Z
zbSt>#Z1&9*5ErvS+Gn_$IT(Hc>t;627zX#7T`R^!xtqP041Eu?A=(akn-$Ox>tkj{
zs|R1R8MLtRH{<t#3otum4c88s4aA`_(Ch=+z8^F@MR(I7vu7*81({8BhI+VJ^S>C&
zakFnJ#v5Ul77r3>7Vk*gffHu)pMZ@vyG*}*j9L0RaCgiWK85=OX75wr+R6N@jgWLU
z|0MzjUCis^$$j(M=MZr-x4Z#I_nUYB06j1BnU5giZGLJ4JoGUS-T+Kr^FM!qg1`9y
z#aaW*o0nspf##j&R2O#8{IhV#95G)_C$@sk_kV}Zqvq4}a6iO+2|cz#&A+Cq)-dyc
z4dBAfJt=H=+&p**6e7)QDA5&VzHBV?PMCYmf~9El3zT_0Y5vjoXgp>9br3{OoA3P!
z{>GX&eg=|a9*>8$L7Zwnu@vUdoBL5nKh1nDz1-5xf0+iw4D;nbLp0O8g-ZM`m^V=w
zP_}s<<pcA~r+)#x0`q0t(Rk7Pqa6^bGT%uh+tubC6JW5$TtP?vYR&Jqf~zxMNk_=*
z&4b9N2J>Nh>KIzhr@R1r$J}WIoo(io2O!#R{xt`f4)c@0VxT?d8`?qcnXey#WUu+H
zT$sOazLbiQ9-2qflH!rMj!H25&EFe`pXssrTnbk_H}}{EGGP8IMHU9ltEK>D$h^B0
zj=nH&Erp?BgSku&H(r|WWHGZN=2vKA;b$?9vRM8WW|Ybcu=wUB$N`I8E6^BdQTq(!
zpvAR|&^u&N-3aqR7U$@$IBcO(0Q-o=<Bu_xV2iK<=pD8Ai>{Ioi%QzT9J8>X&~~WB
z*NY(;W?|@Yg>T0#%(@{OVUf#%L|UAs@|Gxzg>+2(gvF{Nh(=qKwqS%Y77GVKPFW1L
zU=mJSWYRqnYf<F|lsJos@n}42VOWEK##^L*gT`|f?@^vP!D8~)Ac+=hJOGwtVNWH!
z$rkGjlQD`Ei-<3vm}+sGz7=)eqM;x9=@yPDAfA>+*Fd~1m;D4uZ%gH8@adqXn=kAh
zvz#`a24iVYHGyH4|D%m_xaA+8Lm|R)P9z+SwEX5J8lx;zZo|R}O9#qQL|bN2#5l%M
zYe(hA=PdWqhCj_R(Fr8o(k&Vq8J5BHz{s>bJ{vG)me(k-S#D`q3Ycq_uGJuQmOJR(
zSZ`@p54RgE9jLOS(Q<|voVj7S>wgfrX_=P+kz1Bb3L2X%Qyv1d*)o}SueU9Q777Qq
zSjv~ci&o3eT_JkM^4e;+-)4F6H;}uQ!?fY-u#Bbbey8P}TEKK!Ub6t#Z5e$I3Xd(v
zQ`r59<-%v^dusU)9oBnh`MwqUo?9+i25!J|w+#j{Xqij5;gIE4TQt6~RAtg%AR4xe
z{0glvEtM2x7_n43!M9hI$A`f=$vSBT<}72JAmSn$pj@=8OxcM>HyQf_$bOj@o$+v&
z{p|zJL)PXFNl)2xHPpRi+Ivv&mZj`MqmOKGCFa*xmQ)7wezN&gd}#2O^-=00K&Gbx
z;{&n~n$keoMFzt@D0_VZjfZ3h&SBaP%QF947s*=bGXTLd4V7>mm93<=VTdg94d@+{
ziD-KhD*IaogJCj>5(dL%6R1S}xJ>mk^de=+-Qc2RL%%`cgh5tJv6yI?b1^z&Wb%#Z
zJSkf{8;Yl7$+tjG%MPc)M4asMHyF$rSugEZ&&t{tW7gwk=9C>dCo`M|N`h?KA81UJ
z#VvyuNwVdUz)Y6$i4aMV-J=a|s%#Z)r_RgFJ29kmnc?qI0L_r)(NW_}nO`1Svt(1K
z@ce>o!ZeuAmaX^~T#l@Up0>HNUi!Y#W!dp(K)WKVTn&RIGILs>m&z_=LA_e`=~0N(
z$SUq*gtf9)o6%S&!@dyLs;nphv)v%;t$>G(vL*v9Wp2p!6++{tEG!3Tw`5LKRMaG!
zNn6Zj*=qV8(`{Mnbx5|zUeThoRkkk%3U_4sZz0ky%lQk9cV$QZ#n3ureN@EJDf=Y^
z3SF|N;~~;5>nR86k+lUu@}BG=J+pgdA805Xd|$TdE1>ns=6r<K2eS9ZqVb{Zop5M8
zl8vYOpC_^j6cT(Yi@b`yXEG;xCOntjpauGXEX)%kgR)XuF%HR+12E7Rvf)f9I9qMn
zhej8xD|CX$)#~3U%(k1=3<nI!-Ksc<{sM}JRdgp<PpiVYFz96!<w)18)i9-&eXNq{
z)$VJxXc`**tmITn<!_~?{Y8M)bc(MXuo{&JgMn58eS|C4I)^@xaK_r-9GLOeqpm?O
z!TR20IFn@koRa)0*7in_Ja2sk8$N?L-Fh8;JNkmP7o}?Jtry>few+1@`Ot5-mRtdM
z*Lr9pxDM;8-=N=Vy?HVWc3D@`+oj)HO8cqD)@^h)>$&xBl%5#0-a-lAA?q|VkQdgc
zsmyEG+Up6tcxmlGfrt_787XKqyt1yNDyG-gNeMu6lAopgtFt_36AZe@y{M?dRbIUU
z8ou&*$-wrLA6WvJQ2FU|Xbh9L9K~Rc%lqjG9wC>|U$KakS9}F7O1^I<B%|eTFQQ41
zf7T3zL^&S|yIJz?RFDe>`5HQ&lr8U@4Vhy3`4-r{EFTV{t6P4JinL4Q(`eyYDlhsR
z<f=R&0g7evd6c9qm+$mM<2AXdD_pxS=ky>I^4M2stdu9xg11V3nL@a?<i_8_(I)vn
z6jExIN9=;3+j7Gb`tC=I+;A9dt9(iqytpHux)-EP{<RfIyZnzKDBhKCGy~Tm&%Y0@
zQ=Uzw;$8C5A3(iZ9zm&|9{Gt8Sh^>_+zZKGc_kHr+?VfL29Z8_4V48vkk9xQzt%(f
z#W&ITNFHQxMr*%3hcbbW<&U1jw<q#H?}K|P?^p+zXYw3+n?9E({|OHV<d5$|WKeF`
zhQ1+rsR4Fh$c@9m4a=)2^!-w<qO9A9{Cm2$oD@phE;}oB(<gUb6syD#aaFuC8N^NT
zX*J0lR;1Me`-q~G9)3p^-+d0W5XCb33V4_zON+S-S2)re^SHwPM;MGy><xkYk&0jI
z!9^(w4?*vQ!iZ||qZK_A0Etl?hzEC4(MJ)_Q;LZnLjAO2)@j&{RfOM1W1M2aMym2W
zqgZ?!>{&&n1eW3zPL%dKr!b-)CPDFsKTISlmXrf6Ng<|iSF$3+3NR^(HFSg^Rbfv-
zr1OeGXP~4h8kb|B>58qi?affMOan@$;@NpfW+_G}E_XrEkqj<dF?~6G7cfV$nu?)v
z6({M4WS-*L5oqKqs_8=(1&T~MhILVKm@+n(6n1AIQmE+4hklVFx)+v;6<HMixvY?q
z<Q2uQbQ_i^uF{gAR56X>FIN?^Q5ad7qBjCuxuS~}S=SVQA>=AHTvv>t+*E}k%@4z_
zRE%}TK&upU=-Us~iuHLAtx^0-w`#4T;t|Z(DXPeBy`n({&<4d^31Au(?fapAL$Tix
z<fdYA3g+ULqU9XM+obTI$Z)e_938y4tx%<bv?#)BF~C-X;wWus?kIj9570KnbUKXE
zu5jvu%w5HykKtN}!jd8<or=Gfz+jg`LOZB##iN^0=uvz@Cjjp$9@F=>dKK{$M7pmy
zpAAR*6c1_B|3ER+h9Nyvtn7y~j}!q*LHZSn6!bk-82&WJ(4Hu2lwhAK^pw<jrr1Kh
zJy+!K0~t_!L6!y;i|K61kfQ7$$P2|n3d0O55-EW3Qn6tr)JGJS6pVeP=st__zE<o`
zfVvZxJQu{7V<|4~!Ua-cm@BuE5*BXUF~fGS`?-oHIPA_nIttE%`+F*U^5njv^CMo|
zlREh1&FN`l;KS{>4C2de>VzdfZV~1D{W%GxjRUy1LeY1Cn_dU=f!x|Oh#cgKec|CD
z?tKgR8^rzb9Nb|}N5=t=aB-KY93hz7N3qJIoJlB12$vTQ&|{oOF!V#Ycoj6lxGXB!
z3FnXq!EMMDQ0Zp`7xz6ZMRM)8FqkOL?OTu&T+u!_6U}X<6<7?%g+t^d=XV+?r?|`8
zpm&<9p|ZGG?r0>H1I2M^l<7OerLKU?S+1`PB%T|lnLWon90xBFxT{kEn#jHL8YYrB
zx8Kp2%*~|3Tq#@-J=asYlXEe`^W4_|ZbR-Ny>imI#gl=O!3CXyLMFG0z_PgcR0DE>
zyNC%gh_g8hN^#_Hac=0$<)VLtMjrRU4siKg)Sn;)+?>CmagiIn6_S^@gLB|-A$Ms#
zhE~KCj)G6cTq6~TT;`g*p>TzJbPNh5T-qd%Qf{?7$W=~6S-CRKHyKk|&dKROz`SeR
z6sjt}&i&~Dm<lc{38Sdw22;RQajWURujW?LlDvkSKOe5ua^p>)U&jqt!i#!tbFfts
z@@Q)tfPIr&JqwMuxce+nnz)WP(b&wbNrQ#kTp!htv~XdSAg$a^4f^hIGnasC<NT=V
zs+}8(hWcIZ6N)u-a8GHO-^tCVNM{!}KMcNfb8(l^*Te0d3cY)rma=iZ+`ERyK)cVW
zS^N}z+~SvjdBBZ+2>plLR}|cT#AW*9TI=WD+=Q__=42GHe8MScN$`~W;T&L|aTlnR
z<T-cA0sanfhu((5AUB#eP($49FpwAAY<dU`bL?zLzU1n+qH%=tc$*%<uejfWL0)r@
zDS_t1Z?puAGv8$mgD!ki6&hXnnnL*P#xIpaaz8H)gorzzoQ6IRzK)j7o_tylu)X+K
zbRB#1AIqTb!zY+x*uMM&iXiy${htHHpWh~j`2aqtiLT=Ve3cto19^WLKo9bbbO`1U
zKPC+_L3|U%F%I*uDj;%%-%hcaV7`Hc!K1wF1T2N{^KL-z7(a<VuocRO(Kb7bKX({?
z;k>IJ3g>uR`ldhvKZhbMiG15)h$Qjh2n-v<$^35=#Yy42DL<RaAEOQSdH&uvFqp=l
zqxWAre|I;Amcgf%z_m<1*Z`3%zK2S-FYvpm%p{xN)CABR{<mW2<??Snhe96zOa$nB
zzG@7-DB!2NL*XL7iAtX@@h+JVF%<HXPJ=DtjT^ug^LbB!cA38s28XZkr)fV^!b|Dt
zUdn5z82BomIuRzycscF#%6an@(7VRp`4uSF`G-HjQU!1B2}dh=e|mpa@pblat(vzw
zg~l5GYbw^P<zINhP@REyn-8>l{ueqi)xgWOXl>+IQi;(G{<B1wxXC{(LgOudS0RSo
z#LtsKvYFpaN1bl-y*wma_$}XowDJe3p5_kkL9xO%UQd@tJ8$|2T)WG6>jBomE5CwB
zCoiG+au;uy)Qq8Z^9$Akt%vWSPbu8vr_(nddihOKh~DQ*Y+$gD|B22mKj4Gtl-@&r
z#}$Y?;^)1IG4=CrhobQ@KbeB%Px#$2u=|wHpz%KA_gx3~oM+cTWPsn>53oVrYbwkS
z@pT3}fWF`pjWG$s{Ks@Y=Ow@A9mtIEmo9_6;zK@yrPuuV2#mr>`0{5A%~?2C2F^w3
ze;+gBD%d*1lAExFKFF|N_~k4(ci{w8Pk9L2XtVDrSl)vLFCmq(fZl?yCDeU{%Y}6R
z`3f9e!G6NaHIVTaYU!;KAdDxw2ZVR%i54jQk52O+6g=sNIV2=eYClN0Ws1hb!k<Ur
z(-GkyRow>*`!xVNDm<kiZisOG6Aa>*p#2J?4;5-v@GwkBe*npF!6}3OlKF8VQ3sg_
z;U>l0BZcOtkckp<?t+{UTF%1ZXyFEZ1~Eo(3<CB^;d`nSJSB`A2X|VyyBB@2g6kHj
z#|bf0VE2qr5C(Eq_%a)k@q$0yD(3|4Ie;Yy*0g9y6vklHY!D|2VU#>g7Vgi%=u-sO
zCD2F}7LS3<dBK-%hcv-z5*pKm^K{K+2+3_|%oMKGLoZ9vAA;lsA%tS}*}^qiiR1_c
z^)R0+=xEmSgj1DJ$QOPw!;BUPWfb_hC=}DBW4I)|Nw-X)kQ@QFNU)v+(PBZWK;vcM
z(E@;85iT9T&`JdLGGLbq-l>4ODqN?WNSQFU3w`CnBzogq6SfY+;B_I8if<}}Uz;FV
zDQq1;UzKo{e!^;D-vXGg5l*cKsWk`-cA~XTD47MtdZB^>R1HF<8JuYpUeOP8L%4Jd
zKgCVq7Ud>x34_xh*(8{HLcdvfhi3M+u!fGyv<M|8&}$V!-h@wggeMO%h&Ev|oos0r
zmeFaQyFybRP&$Nlw5{nB42j{8=@Mp9s=Zstq{noR5KC21_k{f>(C8HmeGs`Xq|n}>
zPk3+@<{t<nv`Ts?EP4j+kzh+G{lYzpsXi9`XwmUR@Sz>`Q^D<LKtB^EorcJB!M+G?
z4+stI;0A>(!x6AU!YWg^|3WxHM<j=Z+wZ}*mqO<Z$czZ%=R@R`Fp3ucuZ6j5AmXIV
zvWADw$_z^1yC{byfOA!T{TzL6%54kaQ;;&2HmHY{8!ORwM7fDdwu6=DDEWC*$*x6T
zi1KY~S}cVsKc@>aOgWVbjl-2yv(R~5+4DBcM<|zf!F;3=Wumw%lo?Z@a6(x}MLf~U
z@V#(5M(IePCzTH=?0QPMh+?Xzl~vP0VwL{KLE@Aw9mzbSyg@6Gv&wGzXmh;s!7#-!
z&M8$NqBB9+Nx6w6rDiiUl9fjsKvI-L!vIZH{;P$h^U6?KHl!)5DMFjB^mzuKGL-Yi
zW4bbxY41ZaOW8LY{$5ZD6l>2`hSFvwN168-?B*)RQJOSQxq3GG@|CS9Co_l(l*N=B
zxTvh90=i2|#Gr6HC~t?rM3M5Q7AA_73aY!ktjrw^^H-E(=m}Ax+(JctrOIz9`g&FA
z_yBWQrkp(sq+EH-ADGva?|upM*Oh-$EVe@VlJ=sN$|)y7s+8a7qR~*T+`1e3HOf6r
z5Uo{4odl^<-ln6d^-AqSm}pQYZ-i*0^3Y|F8_E$nt#DKM>2r`<N=wQDHYtDq4n8$2
zuef6lZ!4FD1G7arcOtk}<;@ge-cd4Nz^684A61pND;sHhf7hUN3xqcv$`)Exb}Cc4
zq0yxbC_-bma>6f==~3qA0PUVquz{ss<@>*)@xHQcEl8j8^#h<iP~N8p@<V0A_webF
z@+&P+`jvNlz&%!eOS`!z%8+j`c~6xSyfHz~l#|i`_FQRb`U;{0%JMOAaZp)GhX;m~
z94#4ND2r*mJ*+%A1|lz&rzZn#L>a#elCP92j3D`1dASoJPO80e@X%Qm^eH$O)dX6U
zx~j^@fpb%N`ay5MYVJ*7x~rn7@Z3XXLFrCU)yIa{@WxBk>IG15)i4!X`KY=n5$3DP
zr%D??m4!DN{Z+H*WgehfdLDisQ03E^mO#~V3OpWE&HfuAhg6mns}EAmruhG1RXmlN
z98o<d4}(>!`#_GWY(9a#5LNGoP(P+htNHK#Q_Xq<Fk!0GlR?5&BKp$lan*f_1xKh_
z`=Jr3N}?MmN;UF7z?@JSH)8UmRj+P>i&6Dc3h1Qj_!@AhRBjZxIIXH$3ocgGI|)9;
zsYdOF$Qjk$(*QfGYNTjYyedTb-~FdbqeWtZ%8hQ4M3vV<kR(;%4#*^{&Zsf7DXO_c
zKucBK*p0sPs==plCQbF%TA-z?0u&I*P_^zsW2Wl(9dKEyA3Z=WsCWu-W~=u1K`%$8
zY=bkos)<xPl&AUyX%B-qU-eraS_@R^$!NW(+MWzcmsD?@23oOdpak4y)jFz5FHvR9
zg~3u)$QrnIRrP5(^vYD;br@Q?YT;z`T~p0o2TRvgJ+$(xP^HpZpi<RAwWd|76?Car
ztKuZkt5MxN1Y)RFsS6-er#ek9w|bQqMMWA^1AhaiQ8kkRcSH42C4P#Vs<VeMm|LpC
zFVWbn8n+FNw^dzKZqTB-ErL(2syDv@xug1>N+jD<J<&jESM{}E5O-BSP~~@r>Ip^1
zJ5}#d@m-fe_0$Y(x5{$>qCKh&FW}5Ql?#0^u2*&GFL3u&0~B-UQ{CPI$p<POy#^nu
zniU|AR3F!)@v&;}R`~Qp^)D>|pQ=(uK%S{$>0*1XnnwZJ0oAh}_&ca7MfHGqNVT1|
zCofcn#eQIiRVC>#|5BCO1a3s7`yPs~REbo2`dT$W%LXU4VkKal)d62(FfQuj!yv9|
z&)?AJrta$i_I`D0K7KTJ^~Xyg>7m|U3lUHCOxmD&sV~ogL2vczXf*n${qJEeeARkG
z7&QFUd$iE-SHI{+XMlQl6XyAVI<^>!f$CT>un(#$JE3t%-Tg5<3{o$kW$a<K#~?gB
zqGmJ@30BYg8YYga|7->qqIU3x$T9T@{gH-H^^(U>4^wB+wHB_foDU1f)mML^Ja&Y-
z^94wx`Y6R5qSTibfjgnD{siWu)e9Gci&0lnLE%Yt7>((a`V5sJpH?q0!aT*Qr^LZ-
zoH}j>xHIb93XrqvmBtuSyxJ`Q<eWN(2T4$8nV>IG-9T4hlKSScQNjE38M$HoDtLTe
zJunTZY3iLnf=gHbKuLlO^<=s&GSy2Za3f2-Gzj)Ds6UFtpt99v>43{o3n_rhRaZ=f
zUY>fT5>uM5w(v${f!c|d?HAP-uK@azn$O036{<5sAX%gqQP`+h%^K3td09P42XaMi
zPK(77_3Z-~aH)DOoeaOK{`(lbC{v%QhWT>!oFBnmQ+K*R<ht6W0G2A$8rmgQs-N0H
zp-SBs2G^?92loQAMs0}+6W6L6v@lqwK2Kqodi7B{!q=cK|JH!cM)h_ohQ6VmAp&<(
z?bQgGTWa5VFwvy8S`N`>wGZW-Z>ty5>aaz<X(A+B)ko>Kyrcf&Lo~Lj-ycF_yE>iH
zE_c;S$HIJv+G9E<p<lh5QU#CIz7)uRqMk}Qpr`7a&Qx3fOs%5l<#Y8YI>I!dzCer2
zLA5Du`G(ZG+u&ZP4^yf9u-cibI$x?sQBlr_`Y3J0Ua4Q^0PUQnmBM8S8Wml-Nt*Y*
zfO?8%rycrIH9fS^J+CRef{~?ZCY?fKy5=`*^$g-n&A4;uyr8L}FkQCh)4h<%)s#{a
zC{N=?(YAa|h(N!n#+1tMFKW{Mg~BCG9G%E3)Wl_h6lr?t3NF^<eh&33nh{!IlxSvT
z!I@Ic0y~J5X-?3ofpX0=I`VN%bMQkn8m?<{W<#Sw^CN}HD>d$)VTP(Sqbku^t+AQ`
zm>SK$t6;uX(?dzcI?bgzaP^u^Z(zC`G|`k4Y1A-u66uEK9onSb)O>guCT?jS(rc+n
z)9ZmjG;19GhU9I{3JSQkXm0(E##V#o$Qy8~LsJ?APrEh$qa}Ke#)3j|_cW`UV7^!L
zKML#L*Ywlf)u;JT1@b^MB^U}1H3_RB*{|`N0kp@O8am7RMDubH$Wx642lZ!~)^vzG
z*GxBo-2qMBXh;rfHn_sWA&o))0<AAJ-(7+i!y5KIw7%4gDTRp<O*s`oywY@yhRAEp
zzBzz#(w0*>nzPn>0{UFEeTQMmRog|86F2QJy*T%4Yo9{IU0b&gm>$}qx#;uM?x3uk
zmp1V&jKy24tbqj|ZN4E2t-jjw8}QUmTS4Cx@z>r9g?@l`bt4oHXshYe-a)N~z5{Sb
zJFp%KLE1t}Cmhyp{u3sSXy<j{w+q&e@rTG!?IC)RglH{#Vd<E5&t71LYVCRSg=yJe
zp%<=Ap<v%}ZOT*%=R|1F$3i1gTSTw%C~cE16i;Zs>;ra;R-1?UI;nMEkMW+;_6Sfo
ztzESaQxdDiXZ!Hj(|$lD0`c0C3RpU)Jtl*tM6KH<kR<JgyCIUS{q!>Irf8St0xVUV
zkO77BT9Z!t$YHwn<THq7XuJMJXQo!GKxdZrjpOj*g0^=bK(n<z2jO9k)@L4Ia<#q`
zRLax#)4iRq{h<Sm1=^={;{T%dJOv~!X;qs6R;cZWf@G0)-U&1oYa7R65SO(d&~<S|
z8;hbCgSbTd$1cE>LLZ%FT6-xp%C+N<K;xP=(+I9z*IuINW`$No0qRPvnySO9w7Xl;
z_(J>EMOgB%@uGOVm(9Nv)%3Pm?1jEyo4d3@IA#+_q4#i``A)DKX%jde>d`h=zJ{bB
z)@A`sTb#|<R*0Ulk<*Umtj$bQSc<n{4nyXgP4SoTBEcq#UbTrfmK$hhZ7$~nCfUZ1
z)~_ixY0Ds)YLidXecmRT%E{7fmd^xchRuY(Xku;DpQG^-pz*LRwE4;!dKCtncq;a)
zv^m%V(JGre8)3KFrihkOH8#_KhcmS{x-}SDoy~p=ka`=tcEB{)JWGInqfOZ_(7R!C
z?;@PJX|sS(ZrP0b6PQgl&u2iP*=FDwP;T24()Yz$Y)(&rUaJkW9zNZ%G5lPF&NiE7
zS|i`JaiU{N9X1PcfaYpj{~C>Mwn6mX-*5Xrdnmfw&hr3hnC-bAp%-r3N@<(pwpFxx
zkFXU{#xT-$?HA~avYj~->e05ZpFusw){)*Lr);-f0ZO9nQTn^;Nw%{MPcYtO+Xs|?
zOtGEo1^rap1bWGwxBaOaT$-)JR(P6jyFU^p@@<_dV_#s~8GycvwpJ5C%4`o80Il5C
zX9dVL+eS(;UbkIL#nF|vgOpaQwp~cO$r{@;<KWC~+n-Lr!xr26N-E}QwH?_4nLD=M
zI>1u9?F}k$ziaC)0eNcMPYLwrwx7~z&;i@ck1(b|TN{dC4%s$+3^HsRNZ0yH+l9gC
z8?pU{suy0_PS^)^Cp$64F`ezYyCLaf*SZ2;xZ1t&LZ6$R$7U*~+iw?6U($8A8>9rf
zr=8C#bb8r6y8+^DH%RGPAG@x1;kU0{)G%QD>@IDDC4ak#KY|OeJ4*|>K)Vf5P(NrV
zqoRvLc6X`lAjocjuIj^f_Zfg4u^W0HlEHSZW8l+KyU%x0G3zlqQwm{(+QqJ+U)1iK
z6X-l{m$Mi!r|f3CqVKewFBSjB*#*%BamLPmDoDKDk;xcng55O=1ti*Sr$=a#-8x!4
zB-?dTL@vc{niiO;cA67tJa2cf5FV!4&7^X_bh{|}aH1i@Zb%2TOuO~JVG^?JW>}*&
z+iui#*e$ZVM^EcwyJ*UZUbg#oEZo0h*HjG;OYCxM&{%5s4qX>l?bg!ruH0^-0}NiX
zD>{R|>vqjG=&QF2`Ua%It}YnREp~sbMPI9(B~`!PG1vvtX1dMJr56*`Zubj?i0|6%
zd;pmayAKzmvD0q8GxWRc*3cc-ZFl$`47<l}+*&l=vwOG@q}MK{6O#As-k`(H2S!hS
z!on2(oAA3Eti07m_wn01k79(bj2DIL+!%pQJnc6ydH-#W8C3~1J(!(N==5Z^AA_<N
zGo9W!-i!nN2tLeLsFF4gWzuLhpT>+(l~_76tiYURF!hV!TPD*<7flv3Ox2ke7)vV8
z%4X)dK_rLqtOChpQmB$SkD0a+4(BrldwRYXFdr8|<07-^eaKv579Ids$jqd)UJ+AF
zum3V;-sVxGjJudzdRn`&1^1!9pS?d0XzuJZ2}C^DiQ!Q2WHYHi-ir;S5<73U`7Q?P
z!+zw8Mqk!_4ix;@->V?$&lVVdhhhNxigMQn*lAQn6v);^!;6FL2}G5QBiNJ3d>GfV
z3vWqA8M}*iQDKOuDBwM2lyRWQZ3VE8h~$)(2o+UNgux_{5du&D&Hjw~tN5Q!Hc(O1
zthvV_`dLUEEX=Xahk@@czoNrTt9?hom2GBJvFPxw9-@xZr~UUMykCnU`Y_k&%XJyd
zzqDew#1y^pe?KiJe;eJeM8CcZ+pk55YWU@3B&Q4SfYDW|z78}x=?*T+B>W6iPncYx
zL`Ag8$L_$3F<C*ewpN4eofgP+$t?R}|AEYQ1v;O}Zr*|DOIgbI;9RYaP%O#Ys)x$X
z0<FIM0@z2b_U#52Vdb(LlBcXvDu8y{s^kNB5o=XTDe5>YaX9+USba&$-LqE9wqsQB
zR=X*5ea=crU<p>i|CZweD{CS#H|MQp?S){r)u9NGOICY+09L70Ed>KBtxkOp?Hg9z
za`fG_nwAcbTUNey=xeenco#!xwtBD)<bl<crI37R^>;nEM^<(QNcLMb90B*(DmVdF
zpIAMj^LbCL)=`@Mnbmm%Rlq*CYK;c=fK}@*$P8Hp(yIK0)itUaAGW&o42>_Xls{uc
zBUT^KBKeh7wg@n<t!BOlY$xl*w77S+)>ECci}i&da30qEUjW6^`W+8&Ue;&bq33N~
zZUI9+*6*?40<ACJr=93Q>y5u*Fo&!!RpG}9vfi2vyN9hkTY(m1?VV5aYW)kn<j+_K
z)<PlKdNaLA&s$Hk#|X2nYx^MCWPNKo`kJkkeIPB?LKH}=^^+|i?bhl3@b|9u@wZ@T
z$hxK<>Q3^B0!4y+<?qrO-%sA(0}>*COsR}WdF(>?eOg{csm}ztFP-;Ilk<PTQjUD$
z2KZDc52eiBRe2s2!d1x|D4E<SH>1=^i+ucYkWTsA6u<71|FR8spURg8z?otBp0A<q
zqWHON6m9}9#R1Ajc`ITlY~rK%J_s<r3XVd!eyDbVhQA_+-eCcXfZdqA1B#?4-~tt0
z@enzvxc>}jhZI%|;dYQ><ty|ZR)kK3-Vw#7l>iG?^mRe+sN$dNXpB*uqdWejqW1<A
z45t(sw`ib>@2I9YRuQ6xXq>`Tgz=tH<ZnmgS%v&<h{h{S^FYoi{-X6ug5qlmP$nuS
z#$jkliZ2TwnXJh1g25C;&1?9Ssz@1u!8Ao{C?wMrnnCDgC{Foe4l@-WP)<6_py(L`
z{R@ia^m@%!{6RbR9L0SaXs+THI=qmlSV8;Be8sgtAX%W;{y8KsD#Bx6>5}3>BN_`8
znu*XWQiKO%N-7l}#A8Seig9#x-B#?6fI^2NdmKExuPAhY<P*iHJ!l+OtmT&h`=x@p
z0nrh~jTz8?rSNS<=WE4bXL#Yn#braoms=@?h#wc81Z;mU;#-IWaBlR8_5)nPSo8&Q
zFKOR#h;#W9J_T`a9SZ)blF=C0cIZcO_7Y&9;1nmoMRSuzK_iBf(#zu{x3>ctr?@xi
zGZLq{emdP8%Z+7#eTEyMD8gCp(K#r@b5&ILbdFn<4ND2!Jt_xE<N|tunZ&*OCrC0k
zk#aQ`xMgyTESoDe&~rDBYnTq~d`?f~DmQ;4V9L1UMu=YH2I+*{b<T#W6dJf)CID^Z
z)}%x7CTEC;`YrAf-IRB^rtxs5gA1ocTqn2b0Z12D_y{81oOdw%?cprxPQS-(qq^Z<
z?&~=E5$<yqT~O@f9RG#J1J2b9mL76ti{Zs1?&COc{oH|m%<N+>*%>fTxFt{F(=%?{
z7AQRD4pM?{fE&9M+#naQ5oCzl@is>Ig6o#jPszQe-Oo$zV=6=#;hd`g_KKUDP5Z3Z
z-2EAtFDHK5W+*!IYvUo~!W&wk=*mxd1rOc$)JpXE@pZKC_vh2)Pzd1nP&W7gKd=vI
z2YC^#mk#j?3T_ASMsz_P<|prg-4py&3VB8IOGzY#|F{v{Nq)h@QKQC)Pw|rT06onM
zpJ7a~{2BU1<M@g@P&~sY1RtnINy^K1m`~uxb;FrNzLv7*N&Hg0@=&X=J_>rN{NklR
zInS@}2A9U`@eW0iLQ5pL4F0>ln8QqdCh2AIZ_;b;0$)wx%4~jAE&6i!N2Af0%Uhp;
z**ty&m5t={@$?fG@TrEc;nPLl`+c-t;??7!QNf?2j6@}GxfgxaeC>HC*6^3!LSsGu
zodzNe{6U($KECH1Cg=gb;X{yNKAO(5zT}@hh4~S_bsbE+;zzGU<7>X%4GK=ensIQ{
zS%~@(-n$6@c2a4ht6)rTPd6c!4!-Ocd?^;_E_}KQeI7#ECqVNQ;@<;|m+)=~^u2{0
z(cpXqUs~w+2|ugQ=r4>=(M*7lxD40_1j9`91qzmQs^p;Hd>4I(gf1S9K|;6_hICkP
z978XHBSK9W*kIwQ2SASs!L+dp5u8_`@tCmO2iT#)$5iAHE3Bb)Qk-z;do-RA?*0t!
ztl)4Azev2W>K|aA6V^_KdZOT82fInaC>C~;g&%3lnIi1D0WMYeiK=nW3mWX24C2U1
zleS}oDU-N;7;oyN2e$y@`QAU<VWM$zoD3%JOx9n+%#3{KNzuwzAHGY6*AGtndo#$<
zX<yQ_C}i4HdYyz$3n&EG`Dw~mFkdun_GpL{Pn-2MM9QZfqFcLbS~#t-V?SE(*o<C8
z@OFnP5dZ%AK7CF5w~dQnW9N7ky!d_PApUiDOzW^+=R$$Md){s6Ix)^Ofa}aSbc1tY
z`XeCV&3rHhC_c=}c6i{&gwcBQF!RGQKpbJ%?HKZLCj2ZwA{h1+xJbrSPDcx4nE(pw
z#W9~h0Xf5TZ^T@kW$Hf$XezTYg2uzx?uVruX6-I;xr{g6)_Keq_b^BKOch1oN}0u!
zh`!1^r^5whOhr3Plrv2Y=&NVMSiIt+8D}Uq*~rBEz`_ki?@wR4y2EUwd`%lOe-lVM
zGlOD%cNw4Q7-0uvaR8v5%zIPdcNg>gDf+sZK`VgvFxjc->t}kT0Da6<r9%A)BT!`L
zDKm+3WzU$29JmoCi_VU`Vwgpkpx2CD5fq$QdwS&>oY~8@Xmw$A_kiun9@+#^H}+$K
z+0O>kcFLW#+XRCitkpS)c(P;G0^5td?1vG0vrl3{eAv0GAnD6yQu@)4wHkoG{w)6q
zNC1006664DGZP*Lvg>AoJIK1za^R4G%~b;}h|Q#8<HPLZF_1aJeov(V!K^oxGaqHQ
ztcHmYHgz@}J;riWydKI<iG@#L?5t&&*>KiC0jA^ZzjSEq6zfW9<<soI4LFm??g+<N
zlGvh4P)KI)7=xs+uTP=z0&Cbj3NqPj5``>s*mXYxCYSwjC+z02j#LV9nXTG^zAJ3#
z2`HAZ6DXcg$}ZUj{j03`3b<Cr>i43roOQei^S9V7RLaoAZjS+JX1o7D-)%OIPJZ8E
zTWFbhm%TV27CP{ymq6%uvSw2;iY_+wXZn5F;u&ziht2sH8u!?{R_N<x>+hh?Nwni%
zD0qnGDj?!7Dwzy}heb0Mp)pMKks1c0MH*Uro)ul1jK+9T%^8q$q8lH>iv-bcR7sd9
za&W@rCy8cvQc5&O#J0jjuE^0Ct$8BVTktJk)Y<{AK(yk&AfKqz7Ul~@=}VwcB&z=b
zq*(M3{WXfqqPJ+9eMPkTPhgjba_&OCR<yYWUfdGJz5|ptQTSo>^@vOz(D+E?SptOt
zQJN_||6YkkuZM=a(Ue$Bw}(+3tv@`CO4ow(GSc+Igtw8BcH%xpA5e6_*J$=Ka7T^4
z76CiN=x=&%95dSW0w|$IF&ja`jK<G^zu`t#zsDRNH!2aJ7iqMNo)A$+89m@m7=4dY
zXM;G}NKK{tF-BidWcH*{mK|L}Mk$mhNiiz0hQnD#v;P1oFuL&*e7a)Pa31>Cjpj{(
zi8`ZC=^}43N;QW<yHSi3>b*t-6#u_(RR0(XeMVzgkOxK^Xh-$XNJq74kBr7r`HZ38
zXtxt!9ve0P1pQY=-z|j~uZ;v+!a9j_j>9!)@iD4CbrE~H0ozrqO^1S;_^&-Mv0pst
z3MR-yY}kuFPchR4NiT8NIe>YKC%yyXgEA2)_=;E43dc{poT4!P;?s0kI@lm~@`ub(
z@mp8HhKSFl0OlATRd6^|{05~6!o)jii4!g^ISa`M@g*4~Bk>0i0TU&bQtjXgaUvb0
zi57no2xnr%Ivb#z6pv7vH9>r|4<d=;cWH%_Bwn}-eaYgzRM?jyHjJfwcB;6KPFkE7
zXA}b_O`MVdhcm=3A7K(Q#T;!Kv&8Ra!|ny~*f!YB7RN2c%;bpo90OXe`1a3e%oAJb
zfpSIst^i9V;?F6QTPjvk{n=IV++dJ0vBh5?<>HV%FndjGYq$xS>-g(I_zf$>pHUXF
zN}SmPu3BvMHcZrrd#M1dR_sDK%{uYE+u-WOKNdp2K|F!dEsf%jDYJ4z{MH^|cZ$ED
z{7RSDdK$pG#m=;<?h&ua!C3Bz3n(kzD;^~Sbf5Uw)duK45J!hV^r5))EMy*uH_+wP
zFZOPS=woq0BJ92vub|o`C*v}IxaMq}K`~Vq<3ECd?P~l70+(Vp<DE01zTf!4Ie6${
ze3UARJdGy|0ou!0z66}N@vIxr^D$oWJ}`ZaEp$|p=VzRxgvK#rJ1RB~HI~uJA<X#6
z1IUCM&sYcUxbdMS;3ACQqDNt*@h>50j56L54iBS^t4e?!W9(uD?xgXcAHYr-vp>M@
zY2*Cq=!-ROyoYIyGoBa+y)(u)Zb9Udv0^o40}72NQP!s1xTp~B-!@i`;MZ<3E~jH+
zBgTj8U^mu86%Vu`6N3b3#U_6Rps~qB+<?XwlknqEzh@HlCS2<`3CMunpvj~xfDM^U
zkD<|<=2k$#+jIjZw}VW-ybkjbrnhN_U`RH#H-b!#X=NGg7MXsgL2Hxg&vb&O-*o&b
zfO<%ZDTfmziKYd@3CT_lUL;9;DP*1|*-0D8Qpr48f?ky*EQX$sv`C3Yf9Y*MZ~@Xz
zOK=CI*+URHDDD0P{vML<r&8y`2I-$W(RxH$H2}YlNk4FhXsEP>s#3zFPmJK{ap@~M
zCLJODpA8H~OQ+JKG)B6E{%*!ese+b8u~L}@)Xz#c>_A_FbRM1TPnPCJ!QWJA)DP%8
zFTJ@7ed*G-q5+m6-7JCmOsT<=LfBc-rF4szN#~CRxhDO!4wFzREgX%$8mV0YOw>sy
z(W0|Ky4ML_+>nZw1FcDVi!RbT(rv>KaWN~TEU%lHNgX(Mvm}bKdzyXkg+ch6t=JFA
z17^KcCmUqOP|Ej+*-`_G))2G3^eKTbvo#~M9K?Tokt6>7K7}$vE8VD2Z&evR*?utn
z6#xI@+reo6>7^xfSC7!+cTHgtVAsws0P4CA;?cfd{SVCk{G$#2-Ow@ver;SZ4gYTH
zoQ~gevpgH}TMFb9tJ*d|NkF~I52JO^&<k#tDh3d{U(gHO@%EPh-P1;kt$)j=<Nx=~
zpv<~qCC#TZv!3E(F3c1voOflmz5_)+=0F{s^=C%Y`Jw>k+GKDCnB&JlLYS*_A##iv
z{|CTB4a`miS&=gM*8^^4FiR=kp3i72FsLicB3cDkFiTPJ|Np1uqY3z*2=?|Zn2uy!
zE&?!$ji)&L3AP~##-iCz+Tmy{J8J_P<Jb@*G$ybUdSNq>om~U;Bz7m&N~W<&B^|9#
zXWM>2YX<u;6eN?qCc)b@m;E3L8hPvtI*6Lj&hWtRQ^aoi9p;N!SuON0v#JJIDq}6e
zVWOOMqiV7$_71&8tJ$t9cwWQKrZrP7d;Tqm++ZiJ1b37D?ku=lY!sDR8d_Oi1@;ab
zGXXzE8+(}|D(&o}TIk<pqf248hy8Rau<x<kj$qgi*$YKze9B5Gyz`8GNJ;$XtOH#z
z!|dV@pywo7r-S4Z$?vEy#J3@~Am#Mm{Jmm+rAO>*MnkjX#Qwd6p1;oQSznCAg*BN9
zWmk6B6<Bj)uTdG|el|uxpF3+q5n0T_F3g7~`x9-fz1S81y=K|*6tVPSxAX(dmo28k
z7(ezny&wHq3(8Cfu-0!wB!qq63VO%bg!AYNWmo0Xk%ZH1^-EZaW0yaa{(m?5q&MLH
z%CG*!$W}Si-TT9rRGau?tr>jzDTsDUtEU_X)S9<C0l#(?g(B8@Q7(M_*h+x?Jk|&D
z8>F+~(MCtgOKmEn-S}pCFxt1ArcLSA&k<WOh`0HC2#8+}20`uj_vXWxeaj9A?JA`@
z@!iuYqv*y|d;{(M%#T!(?ariqOM_yjE`Y%UOh6070~z@{aN;0yY6=uWndwy19LA_0
z!Q*hIz5p&nFmLWb;|ZqwbD*4Lmda`W6U$h#&_B!cu7`dCvykd1E13QC$gO0Gsnnv1
zNxlh7)r<|*HrFt1e}QXc;^qLRnK{Ixv5i?qm;XH`QG&i_%x{&@d%>uiAu_@+p91VP
z(>M>%&g}I!p%B3y4MU?LoxK}|edvD=om8qB%VN$?gVF_t-34c}nJi<BAcxVY(U;4_
zeF&1rG+UuDpD8*4qynaq3fD@RW$(g+tIYf>P%mR<(zQ{}tfjl-8e>L{*O@vukP0SM
z_-}CA?$QVJ+nF;IkGjh^{0Nv1=J+yzK48A15Zyzj{tJv}kkQi9eu!EB48w9^r)~nM
zE1OD-c{kRb&Wrf5U3)?N*)~e^1hBnLkUYw|B!Yyn?W-}j$Jpc{kZAT-DuIY$k6|lf
z5T9hn(8}f%yN&L{M7Efok4bD7Ri0(B*Qg@+0{ea*EM>D9cc7ocX4CGWm|fh4#>?y$
z`b^0cR{9t0marjYu!@~?1<q8nV`oF5hW%|G23X4;rF~5^TU3d@+wABP^ch;%S5!OI
z$~M13=N-0_c0%{qh@I%{WxE+D-e;RBJk-YyQKj4i_68LXK4h)uLgW$qfRbGO*nvU)
zF&jg9uqW&n^!RzoE})X0XY9-O(D$5;41j9`>`#xOKFH>{VPr!F_Rv_gzF^~fzz(x<
z6k~hII;@Ar2<u0+UcRFK2hcbs%A;jglqi)l$gv_}C7ekXjmw7@#iB9xXuKf`-VA5@
zM1Ay>a5nnP3z*?XpVPiK(P++WI8$KsxD}WcMjvfO<833ueorVqF<RsfGHg_M?f)JD
zm0~LmCi$jV7*BFy2da;06~|JVzg>JL0#Kdeh1lm}O*xuAxc5N(9n~m37Ox0|<bb$&
zJA8g2ww?&?H6nwMbTd{B{U1E{n)Z)BY<)m$pr6va(7VRb3NY(DX<hyE`V4gcGT8+K
z-r@2N{?)xr+XVfKBK+$ROTp`1<0*gX#N-rXJkHEcdK`H%NmLo_%^adL3<sHVsy{l!
z1h=3ul(E8o7mozhTJ*&*XDP#R(!k85bmloGpCZEvObUIdD3Q5$30`C{_EhSd$&~#L
z>?~#xWm7LO!>^&A&5V)4tsKTK0AA!We_aGh9#gUhBKgcgF}MOIrW`02nbEW=xWvpq
z3%x?7Y%A;*G4Ff_=wimOk!mV0GsYbtSD4J-AzH%R3kGN@(=`|5DzirfQpOx}0cbh%
z8C^x!7)Q$2US|eq0a1a^W<sx$`SKPTtC)*aPgBj5+=4SVnQal6vs=tFD&T2i#=Z$d
z%}hG2l5aC#8D7AR7G`t`WV)Dv4}smyRM<nNhgo_A`u7-BCZ?p9>HZbi_Zi1G0Mp0d
z1wjvq0eVOzvEly$EuH;_o+Fv;6slObz<y5g^c>dnAS4S|^FM%6$hvI8ST3_GT4{jn
z&3@Ydm$SnZaIIhui^0{f$s3_@ll{>HGVSb+K)B{4irObZEB@nW&{)IR!~cMUvy=0n
zdYrw`57h`3TPj+Z99a%0quA7gaO4Dg#sg~6?7Z9XE{2V?h2%+gGG2Cg=oq>d!OCei
z)gFqmZ23KC#Ic<kXq;i6(L((!%Z-C*JbSzalIPg$EJ!A>lPPbM$o^#uOG)f9DppEn
zpE{#2g>^B;kCMSwP`<T*6>@=ck!_%hyp;Wlsw=LtR`=md8EazbgG@Qgd<Bg<cCRbU
z*R%6!_1(aBUjf(1Hd3CrmA(Es26~4rqhkSW?5OXc*Ur9A5#zh81qI<d*gGrG*U7GR
zgI*W=emQ*VX7_J_-5&NI`uXm$?G!5RWsjQ!>^}Q#1I3^F*cVek9<a;G(D{(f$pjf-
z3ut*e$R47zrbBEWT}3b0KPj9t%zpC%jW5})Hz6{@HZ2Ev#g30apSx(~$Cxe;(aaBk
z86f(do?Qn-5fmyuDylz)Ya&E+yBA!PXqpYhUrvZhs0{3k$Pfvq&WfUF;hZXRp<K&(
z(KnAEnj_j82$CxrrqxWb$d&5kE{hJ&0QMD8DZS|`ML)j<g(}g96ridWxp%;)8j*?~
zq_v_m+t61h%A`P1y~yz}Tx$@GPo`{qqsW7Ppc|t9*V}b4M0IRoX71f9g5X-=VI)Lj
zK>`a%0H0zBMTlZSFcuJ&qJY4zEC}k;Rgs`iq(vFThP`8rtB8sv8Y|IgA}ZEs6vbY!
zki730-!FK1io55YGpEhj<=&Y&XNI5iz;j9Rr1J$XODY=bT#?o^!)UZt+O-BOS0y_-
zRN|WS?G?yhmx2z!(hVt`e%XJM%67uF+tRC1&~itrxB&CNOXCM1By~~-jgRh2-J7EA
zfi(9lIP0Zg%3~TIO8XxJK9Np_13Z;_XrcR=lv57DM#+ix+fSD_DUg^U>u3|?O!)}0
zWXT690W(Y1YQUK-_bW%&X3N_<!}~e%>EZA`SDya{2It9ZkHCDM+-oFQ@@0Ff`74kI
zW}$7pQBDkor#oclA0bgG=Vn9xh&*%)cuvWu_JMd`4#=g?SM^IByqK+&^n|ut<ua9A
z<SC<0fTdW;yawH+igFlA7b#V<fGt+mO@)U`l$n&eU#d)f2%Tlh%Fp2M3Z-;346Ra(
zd##~#jk2>jd82$=2I>Z7tsRtZRL;>F=_aNBT?lSgJm~P7Ey^;QbZk{(uL5jS`1B7$
z>((_?eK?{G&DcifS;OL}DqCES9+(6_!$0?f(-B$y!82yY0KAV4c?t#NjAv+ZHojjf
zkc5p?CzonR^)-g)j&K2o{i8Mgb}8N`##2ptMhbOpN((bkX0aKaDfTSm9L&vQYm?E3
zJhr+kOy#q7KL8Z4!}s8PA#2+P9b3pM=rLN#66qIw5&Nx{vUH2twnr2vHuD}-Z)GbF
zLbr*PQbK$mbD|;iVV3_bz;ULh`BybF_(R(T7Ig?dUS`8+G<K6sdkSanvs2GNe910a
zLFaUy;Q@n%d@rRFm-C|B|CW+0bOND(F=Gkz7P3V>AiI#greeNQR!tk17qKan6<*9j
zy<l?{O9%w#YW68Tem1iv*-&53zWyEpTi7FdTyJIDDLb*7nfC{_hjpO}t_n7>5yZo6
zB~=R?VH(Pro?_GJfpMCRaHK7vzp!XpX#15l20+_2ws#A#>+Jjt1nCC5xfMOQ$u?68
zU?X1>3V}_${t<m8_%K?dE$8)gXUE8~Ih1bY9q6Q}ZQQW~z;^xz75JUxRoftNjfZ~;
z@nw>l@~LIg%n3C9T`p~`hKUu@Nfqp_lp3ibX_d4s2!gAnj?NHVBekTj@>*$18d%mz
zl@yZoQvbQ|cZ0N^vN8E`585YMAm`AOu~5F#2_}l<YTAeRot#Vyne*j77+$Fs$me6B
zx>$aQF$4b6h<xi)P)p=lb@Um?1E?~-RPHtcb{EP1G|I?UT18Xul_wKmw_NG%0&Ise
zl^(vk6!8U2>{c4zp%azLr0rnYuSC)esY-c07o3NbO*Y_ssf@%)J2=<Ym5RDIHQD?L
zh{j`0PX7S(M3cpZ@Zv&~#^E1^X!m$=OK7a;`TOAe6TY1u=P!5-txUY;6KS0(N7_;Q
zq4247UJwlW?%sun3|MZ9>wzVAVLP~{BPfG>Cc?(xNtIABq-YN4L&w@dc}T8t4cr}V
zLkH-E=bGa^B9?M|WBR-XYh))AC{b+(zya-1+TxoS-W}KDy(pV+I2M5pqy_E-&%esA
zfIjuJAV_61FO+d%miVX!Ejg^+JrHNJwlv+E!zw73vxzw!1OHBDWjqg_3U;6#MyuFZ
zT537UJjy{l#YVITILBg-!uN};m?n)^SqQDo-ezA}0DHjB^+iu#Ft3x4Yh=!!pe>8H
zqy@G)d><;i-j7&X7t?+@e;cd<r~-;;dYO*33Or(2+$0*lHLxyDQ1h0(n~1h|Y<Lyq
z|77oIm(Fw^J^*4_JkbuEvv~eBsLJ6oeXCLSW`^&|cYJ3BVmzN;rJ?#}ek27L&d9rM
z_Luo;p1lH;i<}ihMGX(X0fm?No_2`GWh1Yq(}=F{OSD>ihu;YT>+ihK6<8hDpMzib
zdCmLk1wNi;&yV<I8$|atANDoWzu~QD4ffyCd29HUCym|>-9=IWb!5Jjw*V#<NZopW
zxJS3Croq-T)^!#XJ!f~3y*46xJLbUVOQu^76|dNtFn|X3ecAhNH^#s3c3}~0=JKJv
zpm!dBd<mu(aMx<6FXks`<|OzKA}-^tmO;FXZ%YEUoFAVJODp)wci`N>|D-)T8+k%7
z1U7NL1)dvs^3mqt`JV514Rjy>l+uFx`8&$c9_1HbLCrCKa6V#G&5If2f8tU0;Jm~o
zdhlN6yJ&yt6~1ILh_yVJrubKR)lRfs<EaxMcb#*}e&68N&qMqsUqL11w|K`C^z5mT
z`;15LpYg*qa(&K2^Wo_W{$LLTU-E(uAU5!kl$?0OUGmViw|v)Ukk68Qdcw6?C<X*e
znN&on;Ehrg)u$bhn$ar3uTnMbO1dV^e-4&<$&99WFQiw4(bg!fy92kgW#d}PT?=_t
zAWUqOXAT6mU*?y=S}k|F0ByJA+q56xm3+nluFX|h90KP8)$&)s7O9r4fln(`Heu-R
zI@R)Q5Em;NS~OXzFiNp3Q(S22zD#jpkXx^`qmju*WlU#)P0AP}-TTUwD|Bbrrr1!r
zYL{|$G`uh=i{cT>Jxby{L~pM$?{i30Dtmjuwf&0Qa~P~r{z*yAgG%Tp5I?L8b%pp5
zrLZmJeo*QtnR#5%o`t|^Wz`UvKcje$f-}{M-&~0Qtgs5>hr3<>A1l$<z&x6p2UW}P
z|Lc6(b2lJ30+fN7w9g{AhKdgd9bF6A!5z$?cF5{SkQ&Ngf<MG$f!1NG)bJs+uMb+o
z0=vQ3a2qNz{3esK+#?puM$bk*q5{lOJ%5Chadc@SREHP+j^;5BY~f_&!4^;y<@o><
ztq<-Xs_5y3V2$Zf0!6V$ZbL;JGA0<qT=oNHTsW0h#aB@xI-w118BJu~xE}Ab1+7Wp
z6>u^6@dnUSinfEIn->f#`tmwNX@Wz@efW}kv;l~r-USUAdBbr%<qu!bXRyVh@ddLn
z4yQt(ZnI}YN%tYNaM5$_Ot|eELTA|y=&};@p{Z{``6e$H(h*hk1c<%3LxyMgZ)sbL
zSbjcmC)|qeUkv#K>#2~@cXPyb=ATsAGp+XKhx?^sqR-JLoc8J1o7Usnt5beBdf^;t
zj(3lil`z^f<0@48-KocQ<nd}SjZ3e^^`yYwNWNnw%uF(CE>65;Uf!C1dVNwtj5aMn
zmtxQi3k~k>?wcMR7v$&fqSfm)zPgmOxRf-5#y=)0L2roD=#$dNC4f`3Xkh*h$=Vp5
z!P6ts&4qs4UERC8_HgU&=IQRKNz>_)3}VJ>*0!GpZ1D*xab_REn2*LV$?y>j*?f%1
z3H=+^>|+_SjMr#Wlbus^DRItm+UNvLT6}tPv}U4LoO80%SiL4*n;NT$PDn#^!whk$
z22G4MHA!dC_~~NOliz<wLcR$N)EM;In7GKaIBl}Vx8ERVUr0p;>tfTB;v$FX#-?Rx
zQ{%+Ew=ClS-7U8_%w8;i$FlqW9qzXGi%uW+w{+ajbh?qH-xeKAytU~5Pr02aaBOBN
zN~^6b#N4$?OW}IoyqSoK=C-C~w|IWN_}S00t9Y_YwlU2-D~%6oi>O8hd>P^%8Ss_6
zcjOSA!J(_WcUaDSJ6YVfQ?(G+8k(Amy#W?Y#nA(*jwbtdDzQpT$x^zR?j2AS9nM*u
zrQp>BFLS(_npS67e9=<iw1?(m>vMCt>0cV%!yHY&EwI=YD*k9=-d6aAT6Hm9th0DK
zQoJ}W*^1oarfp4*{+7p_#Hl4#=Avmkm7U3af~Bwv_+P`V@ry&O#f{^LPt93XGf~io
zTZo@}%J!x^b1ijmTLupEj~w1_V3@yyx9j_VVW!ZWW;LfwiJ?}ldWqs(m0IL>vosf*
z>nxm1rUI+!)Bn-K&E46})790{!OhL3yNjCx?p5xtUT*HDkQUa5nmM?|L~A{@v7TC2
zS1)fjcde_3yO(#2d(4+HZqe?Zo?bZ~_SSecH+k5rTl+G5Q;=3|*_1_zutfD>7B5yO
zsxw%LXg?nNbJukdDdW|H_|`6BKfx+TVV$HN#MB}p3C!MN^IxEmK%fXthRoJJVrepX
zf9fM15^U%rdZ$39M9fP;b3<QomC&xjSx4MoiD^1;UGx)Y2wv|m?Dc5270G(&93u7+
z&<m>x03{*<fR_b{@(J&G8i_hv1g8SniX{XJL_Gnu@G*e3%0=WE!0IY$34Po{xTFD%
z5>wNF?hX)V2z3zc(}7+L6e;OIOT<2)EK^ub1oe8b7&8%6z1R#CiW>=Jir@@t93hrw
zpiwRAfg*Z7nV>d|5_y@R7KmD)Y`Sos1Yj<v5*Q&)6DSbvC##*{SkPp3M}9X-q)b+K
zRz1UlL#0?qq%CT(A0+-<E$$F}93`x$fTe2-YcmgVu!VIiF>s1n&B8^*6m=K&g~$d_
MnQ7H#b?;mM10l6YlK=n!

delta 129406
zcmXV22UrzH*S>q(*4qpA-Zl2#yD^$rqp_Prqef#*EHTMNEGQNf6hTBff`uYQk)k4k
z0wPirP*FfBDk6$v0sY^@_dgHM%+8tfzUR#B?(EE&xjcP8Cb@3R;WqNAzeKcKB$u|d
zQ^?w;da7l)cNo|G@;0^}--$A2=?;ZV-o43WnM|f&xDCB{8MAf|FOv^yvXDe_RmtB9
z8M7f3q9IM!HHz4EH#iv+xtx{Bzi;9|BBg4i0l*o45KU`(tWm@s>MxfuBgd*_@)b>j
zNyMol(*V4>2clI?<7|yG*0Y?IF_Ug6W%4~O2SUX3w4#1*EAohGe?u*k`?Mlgm;vQ7
zncS~6`M_-TfPPFXGR|yG6J+vBt;s60_^@0izuAh+F(rYVOrF*{j;^1N1LwV_jq(q}
zfGuj)XrJla2Bc+8Co(dbTB%yK_D>nJsz{W{E1J!NNTFmEc5rzruaGIs#%@HFJy4V>
znwUn=wPSykOwq<Povuv-1ev0P`B%Cg^dlov^e}Cv>y@u?-P^p6uA|?AbFk?oU3YQq
zqHJ#q`$H{Ld~Y5KW6YqAoJ=v(@;zOD+^d!;ElrY0^N$}znbO)cldcoMplsf>kgk86
z0G$@i%IMlQ2lBQ}-_Z5qse(+|uGts5&R)*Ql%1Oj#3}0JGG&)$R=OTs19`tzKTyM&
zVm&KU_HRusW<EvZdPM6+`A(T6Q;uxYDF1r|0F(YF_e<er%5VQCxBp8aQ_g7J*t26?
zo2ah$c6-6dxY<2f86V~%mvNQqT?+Vi667*r)1N=f*e0SsB;t${cx1FfZKSB~!F24m
zPbpLAc@|nSrNW|8waW2Cr*~2}N)%~ILDhPU>q54zsi76*l3b;ZYR2QC(x|M%To1E-
zhb~+WPn1f9O0QBcQKHjL29=#>ChkxxPGwD4fQy#K|FOBsO)4|H0$tzStg_~~*0ar;
zc2%-6#i%C#bKrk!eoRwUGqY<iuC>(a0`7t0G}A)WdYS8dZY|T<^%ggXdF#sXy_q1_
zzI;#HRZ%Td$$r?SMB3>&U58dONQGM@nY~Dk^o3bOI;25{bo@usY00aQetbk}x8nj*
z>w1#=UE+}bTul0Fo=|G%Na=qe#3ubo=`m44`T_5PO4i;slK{>|3Z(Aoq<Yk!=rny<
zq?5E{AZrZO_8Ls)V;H(FyGCxw7LmSmnHU~r5i0foN%Z#QN|K64x?m0Ihg>C{7h{Ma
ztSMmw{v*v3$8F?Aa47)_6qM$^Bvl`V`e4ddGT+{fRD(v7q{jmy?Q(!9zPuvMh<wrs
z89@@^d%E75O(yd;lK!-J#NX;0s&x#e>%09aU9*aGa((1BWS7R1;YIU_Zr%s-vHT#l
z{&zP@t*=S)tt-I>jUd>mOC&J{kXy11gk2d+*LOFObAuaODeflh;l^(NQzB+zA?e)2
z<A!E9Q`+u{AhW4tagQ54y+eRgcSz~?R%C3>OG@|asn+t5OwR2=uz9D5&fkODn%IWq
z%{7ElRZ}Y`_9rJ!4WQb)l_VK+m~^&#5P$kL;{3Ng$+zqSk4^U53j)MEr0O{dWMIe`
zl4z8aE?GdSk2BrffH(rLe@QLAu$D~D+)B0VKyv8sc9bSuBF&zSH^pf-v2__vu9VKC
zW=woa`iZAW{`*UE%eJMO04e`cMK_GYXmJWv6ulrNb~KsUxPsDEuSt^OMAwccqKnNW
z{q#=c(5DY%W~dKIme-Ju@)YTWHs02!jorTeAW7P6r>05=iOtEDPpUJch~l5$$cevP
zs2$Er$*oo@N^fqWc3+F6T5Ug~s7WLj=LQqS{U|cLr#D^O4<R1D1u@K{?v-Wiq;&C0
zN{@{uo{Nq0c8!iUG_w)ilP+W?KaG4(uAu9P$K>O`jqNC?C!K5S$h?!8%uK&UCRJxh
zGc25Hhc>=72Rz8F^ejqCQ^}PPjblR}me_pTk><!slF!6<4`YB2OV9sx6B#x)-noL!
zRNY}L`Fr+SV@F*iuMd7lCcnHS^CgY<Pt%%oQl=46oj+aQ-AL)Cj->PMB&CZpiEY<r
za&*2QF_bpG5u4spugBsg#Pff{M5?dWl4?*OsV4qTszY{?<cGdQTHc%_;hm^<mjgKz
zxQr+!*3<P{iAJ<vF_}=wmQ@qmz~O{C+l=%lHNK+pg(SbMCe1#L`W*G8O;)KUBG!x2
zdC$oVGmhH*Ukj2*Sp>WEgu3p&8`TaUOw?_^5_PhMTEC_ZX(k+`>wfv<^y*Jk+oW+k
z9Vbz3Hct%a|Dm29>qGpqhjeY@T9bh)e5P?<!wGhAK3#jfrRqx&Wb)2LO8fg0QO|88
zf6<rB91}?Y+U!PB3#ILUA+{cllrD-O{Y^%auSg*C-!<OKcjL+Yas~BPgY76~BRi95
z*J^56y%U*t4JJv87?N~v9BP_BCX<`BMD3SCwYQp3t?3pSxHXf~d$UMqccT;SuaU_g
z>quvUH>IPBiFs{P(%Bk8c5gMeQDH}S^0d5hZ147&t~1XOc)UodRZTjJ3aJkqPf_h+
zM{4){7j*sXHa!7rW{{?38M)<nl=N>5BAvU>NoVC=(rK!q+T|0e0fYBatq?EJ^FP0c
zy!(?SrPI$y>C<bv?tGg}PVPf=A%9c*n%pD#g~lh~lz~hx_a*~uPttkTi_*GT#5Q9B
zwbkw?LiuhaxnrM3&i{zB$vl!Q`&~`Xf94w^Dhnjh!i@x*wTM(LDFl8tn>_uifv$(l
zBx5oMYC)DS>3eLXZcOe;Cc7M<>i`F0b39KxL&p-&rkx~N+xWh$OQ-8E7YN(L5h$Ci
zcsP+R4krU&2U9vyM@kz{Q>vdz>AP!W;LLEM3w%oEE3BkhyNHO+d?xvzos>E^&JzAy
zOsyP-xg>_|wbY|WYYBC|aeO>cLD-XF#A)N=iQ@TX0yNL2wgx3qby6%D{&<SyWsO8t
z)ns6=ky?4=TOu85Px^oUMf!P*NZ)%Z>Hix+hD)94I`|`{SDTXN%$4NC04-^HEF{z^
z+YeN+@=u~WZz1Y+ST^AE`X5Qgo*?jkta$LX{+8r>u`s|*=|u8!FCy}DB)6hw5l?hJ
zrN0~@GjT~IKRAo7&kdv0ZwFxq?;-j3YltCjmyM`5G>&dga;zp~o%@nx=peezuqcrx
z?ck7Fap%;shq2@qcU*z%*S7?u*{xWlO=goTXF{k;-vp5U*imGl=Tqw4(8i~s{|h<f
z)iu<}$4|(K2#&Ks6wDAT-+@#&eI^6*TT&WlCDm`65cTS&WTxp_YR3;9NYj_4bYO`Z
z^2!?0Z}p6>6DN|U-%@hXe>yq+U>rGm@>{B17fL<Uv`&TVeV9$*{eO>ny;`>aSGpfF
zuabeE8t1YNO{u#kV=Pn4&iA0!{5FliA9_<NVxk6Y4LLCf&$e176%lFe4`kBCk5Iib
z$mG8J)b0&KsKv`0pN6@C#O$~j4YSGmH$M5lgi*J<rioM|Q}Kf$;fVIof9M(Ab{4Mb
z=g|zw*mI=ve;TdjSbVD5W#yxfI-W>|OFcv4aoxB7c+d_^Xb=3jyw;FUoK*qjPwG<W
zFC2Cs4O#SzhWO>5n{jyme>;!?!20>yVPu151FpArN<_NtAL{=9=KKu#ZszR};GCI_
z{g55TdID7*%=K?T@6Y7fAv?>=qppo)SWmR%GSjCyRN|Np^jgF-X9D3u0@JrQ$WocC
z?QkWNS@xS8_U|!ER-*DgGm?hwr;Ibb%|7zK=)nz^iwfYQ<ZDa77A=226?HN4^y2_r
zl&2p>E3V2Fa(q*Z<o({DuO7=M{tPcX6nQ_uixY}_U*NB&;=vdQ0~9iMa0V(WWbh(L
zvHb!sQ`^oehV;ba5w3W@4Twxdb`lKUQT!1E?kq+2E|hW=xzB;mQw)fQ-Fu4VA<%rO
zC@z3AF3N8YqjXOBeRHUUDIK2z5UKR=LS2;7hlYt5<tC#5HvF}YrEg4o8%#Bpvz6Vy
zegv*S>4~+ps#v+=Z&bWeo~5r=wQ_M8ggaEdd_cBWwZ!$cwYjaQ0<Cpd&B}v@r>bxt
zs!pk%#zFCxYH53LWvR0Ip?&!(T@<(;sXEcnR*az?D$i8@4)C^8HEIGJt5Q|Wz@zzE
zCC6G<<)TjA1K}z4b~A7R>g#h+I;|dK0^q#*?NZo_R2SJMp)y|W@)c}J>d2lb-B2HG
zj<?{ZTJ;@DPt>DcL$yq8rq#<!^^S0uuU2=Kqx4xV-wL)b>h~GwhFz@he0YDD_1OXy
zH`bZHHy-TSEnqpxo{a`eAY0R!9s^dM3wvkT^^<L&iC}Xap&G@8g+k{RTd*DGGuWst
z(7D6Tdj+<9w#Q%4e8Aq!f@Tpr7x55PF`IiGbx+y<dZ3@m*~4})|CW72tCaU_#B>1a
z*@#alIdD^GPPLm`(+s7(T<tTI_H!cxW%ynn;_QdP{iEFJ?(j60oA?hZZ*Wsvz|;HO
zr*C1YkV}h)Go{@1KCo2D{k;J+)m+Q}P<q3~(xUnu*Jcw8e&FQifcwIAErV-2`0X;3
zcJb@Gq0W&%h%kl9mH#aS4GiIvI^uh!I>&cj4-;|xKbKK?jaR>fYBGOo61=$0PdpFR
zEdF~9ggN}#S!m%y-gFrTpYbzy!u$)qqY;`lynYt4TK-{AI9kVVr{%~e-fJzW8~EAJ
z0I(PCc0oIL3XvWV?h#xfAhbOc|9Aq`5^>sEA{F^VsH_lUmO=G}Slt(`cqOg~Lslc6
znGN$hCC`bl<Rq=1i0(QrMbc>RDJ_cyz*}mfhl;;cQ~<Jb(zvhC43}z0!$Op_a2ncj
zNlF?AK%CTZJpf5I>FXY};-=IxAHXb0iwKgcKpNQ&_{Y+7Z|IarUoJxBnWPy4VTJUD
zR(N|gj|J2n(A?<=(!-iqS2X*m=KD>^+%-!PoKc<B>^+9M2#ub?AW@o7M0!*gHHKd3
z%Ig~L0-98*vHiUt#dn%1v>f`ZnR6Qs@7Atv3m5ll(_`V&5$!yCHJrldLAf~y^eTrs
zd<N9XN1?;E<NtpsP%<OnmO5?}2v~hTuyHqUK*C@D?|*1j+b65wN0;09?yGk)vnlYg
zi?MCRbVj|GsZE7D`<M%T@U3-X{?NkUe&+X{_yV0`mQhc6Gy0cMsbf}s3#S^GA80AG
zTkgCVnojbSKf#$}@(`N#d&tAXQSz40b%D2G@|7EayCQFS5V&;tAvM?77?n=(H{`Zv
zGuA_^ZS$p|>y_q+x)GN-XwDio0KNT(unFk_CZ#D{2x5k=gl;_3)g6t@WFF?>Gg-^z
zUikkm5Ed>6qrMtb9d-AI*=S~u08D|@-!!$yu+;NMJX!Ky6x>wzZjBX)y3f*52J?l!
zK5fxY{d&KJ)BU@h!|fPgo&`S!W~RfBLHEPaQG;J6BOOvelklNcG*KVd`~Ygd3kro}
zGcVFiXi;`o=&by84tO>=e1qDp!;FycU_w05xV_BR9pH9lexecZIMZDR4L=)GC?Y@4
z+-L`B3=@avPko7L^gfnpbpJBb=zkp3*noJZu>}bXd96-j8e4LmK~rD~f5Jcx#w-g<
z(G^Wczd+i&@EW{syFU}2cFaUqs5*zWK|g-u^%H~lzfUh$!1{H-tVK0si#IApsOdJ2
z8by(|@fvz)CU2l{zz?M+G;Nj>M)yWjcKymg+43L_TkUtz#Ix%fSEK`M^l=~6D;4s|
z`zgpWE1Tk0_Dlq=8h0?=g23azY+p+D-I*B;AopNy?}KY6n7cH0^<(Dk0f#^HYXg7*
zOfJp)LYavK3}dF@p;v`7^P52B5_A7K;IT~mXlPz$W{!c?Waiaw0B$h5(&1qW^Z6#4
zlFJOD??WCFm;*2FF-d~~x0NySLqL=>7oS13g4xg&s_z+PHt=;!Wq%m_z|8lBaF6^z
zb7(rsCo`bgE8o`(LN|FKBH^mza*Gex+~u1~;eC*N*hP??mdETzU9f!QY~W(#XLds6
zqP+eez%R-Fy$K5`Hu)NgOs2{o(`~yW_oMLXefjD>5I&MGp?g*&Uq<*6`O^$EyG-7%
z4y70Jje2y~d-;gJ&=`A#p1xVT71!GUa6qx$51I!R8!%H;xhtH?Vb??PLq})^D4h2|
zGf=U5F0u%P?d5$~x}ey%0;Jazl}mw7QhZYV|CrG<^lu0{VJRe2b!(hGj&q_Z#q6aK
zfc>~pf}J`0TyQ;i&1tmtr|;&%<h;fGAfG>v7BatXp>b-(2MW@zpFs<QE&b)VVYWkq
zp}*6{te*h44lpZIkhw8ka;P^M(?|4?JF~qEB@gDy5o9NrcbM?2JQ;^IaLJ2_{{pM0
z7^g94hc}bx54aDbUIfFwOgs($e$1>TaMhpLLV<<=rmYBJAk#|+>p{#3n(3ToY$GXZ
z63oaJf-Qu3JptTjm@7+xILoB%hwJB<;&O1GXXenNKa^P+57IE^8cmVHnY%4fieP4A
zX0E!xY}gE3B-2lWx+vz*QBX%SKb6654AasK;YFrZCf$9ezaPkAnV$z=K=Cr8&xQFo
zW?LN0$1@irAxvQU)9O5tvAYP;E6midpt;ISr)BIlW`}Ed8?)^i8OmmU7zsl;%!C!_
z-CU+=5V-OfmppLYV_eeUSpl<bF}Mnu`eeBKfN4#u;D^j@`c@Y+E?V51Ql^guEYFyD
zHvr0+!e7Bs!R%-Q;Y%hs0JtjVf(WmxnHTgnzh*Ajv@lV_%-jOiH_Rvjm2a8Mj}X=}
z`!Z2_$K05Oy7!FFJRs_r$6rzUz(n_fqn{XC9k@R;13sW(^~{!Z)O}?p(*4{aPp7Dx
zgM6bKJlrpjZu<Wd+)hSXZT6r29UyD3*(h?hZgMItt?#`AW;e{U;d*1mNNk_bVAyU#
zFKG1o>mYit_pwVz`|KMCd0($@V60y@J*+-V3S#|@>TQlpg1PqfRVa4Y+z%dfe6Z{P
z--NMwZYYoQIEx2ty!INdCq1=QAX`y@B}F5=*}t1$p{sQZJn6Bq8fmZfBarr;&=v{<
zW>J)S@LyQTsfNi`K{7Jz6TBVMZZ3Lbe7*xTr~23-ogM26`NC5abX&Gpj{aCP;|J)h
zi+=}(jU}}Fic{ZTtj6RqUY!vLqX}xw52#C4|4#35ntGH0sBE?KJ{T)d=g~YqgH7BH
z&9|)AFsSU{Sq6Y3e3Kub8KoVT0AZZgAj19;{g@dj9o6rS`~Q(Xlxd*IaRFlrK=z1v
z(GzM#jBO}AYQ>B_t=meN0fFf3Qs#0PvZL~>3RpWPw@*Y{j?1H)fze&wEEd@b`Jdf^
z^OUcnS(cZ)?jy2O@}LJ`@sanNhmx<n_A)g6<<d+vJV1Wt1iXxv$0Z<(k-w+7>0P;_
z?F`(=mTMluM6SFO-Jm>q@;w0W%XiU^NWR>DB-je&@f4zbAlJ}-&LjDW3%Jci^7r?l
z`9yA|Ia{&3vKpmQc^?}%pUP`0VW~`hOAhnp@-06?SSgSE17y$T50rRcUdjXeVDDB{
zCGQ#qZhOUt9jM%)h<J=_r^1FUWYsRk<X?c_qbPg_XB-t>DS{uY2(yDQL}8{|m8}>-
zYls}hb1PW#6t^qUdG{3KV<F5}jH19G_L0`XnFoqa{g6FWv|Ej=NHK0XEgl{##@_}_
ziQ@7)bV8|ODYhV0&lD>r0$8T#oC3BAg<BO$m5RCaio8(Vq<Pm%ML#nCN->JU*wu>f
zRmf@-{@8p~y-|eGj!CWJdkXQrQ`|m{Qk`M|-KGzUJv0aUq}WzTi-*sOR!<;pP+T%W
z^^4*;P3Cqe7hXYo9hANQf^fI83vKu9Q5FWm;9jMKoo>}WWy4mqV!tvr9tIC6yVK|T
zkTOjMoU?MqQ{av$)6PKCMLEP7=8r1hQGEWGvUD8kjw^2tLS}PU=2NiPQyFy=IwzHV
zvVl0Ie47t1yp?OIF}})X?@;Hb{Dg;D6{sA31YQIw)yZgYu(E<Sf<lz;P5_)$mi_?1
zIpy3TD1|D0+JZVvnd}YD2;~iIb*nBY%f>($rObPeCPmwnD=UDwr2J_WyopsVn+KgZ
z<)!n$$18=A&`DG-Z3C4n%0m<vyr$GlLtT<`%3T1Gm7*D5+)y^BRZgnX`5}ZimBm@m
zOjD-JhoyAoZHjx`R{l5{Dw)duH$ax9RE`D9U8Sx1ICOH9sn4O4t1Qe%3-2i_MuFzO
zGPpGm1<LC_$O@JE5C|VCU(p`iBV~m<XdWv!XpucpE~Thosd8N@Se`1|xg#r6=8i&L
zx$@Q{Sg2Hb&<gdr()Jozm9kkM7<#3AXTvE3)obOh7U-cG<-*<IeycPIDAg+Uk5Ttt
z85;mZo$}!>uzgg{nTfhj%I4W1tyiw5^<#swf#yo~sz)CH-=Qk11a7CQXgNAzmrA5K
z*&bEO8g!+j%DWlt?o&N%37nJam}mpd0o4*KR1c~&f53#ZD(5*&99A{`6+jo&*o6?f
zs$Qi)#ZA@s2begnO8o?b9;%V_Wjvv(TMX`#s!#o(>808j0Jyhm+jVrXk4hQ`6+cxb
zg@XN6hYIKkQcW<!Y>;Yti~{dph^k-~ES*uEq9EcqRa7Wc&#Ru_hl^pVGzwIPtA^9d
z5ve-x5!_L#>KK@hQO$Y>yBAe|*T8P9ilrU9%c?W8U^ia%xDqM}s{bf-aYfaH;x$)Q
z`$HkTugW-uQof4ARKcctpt?2%z=x`+Pw=fs)paH+AFD>kL0GIR4g$VJ6-qm`PgS!O
z@cWr+Z4Fe)RbP9<nF>{P2^_Uo?=3{OL%n4xgge#l+u_qLbpQon_oxTa^W>-&DJ-#1
z9hM10PU@ReKy5pyo=aOAht#WSQ{jj@W+kL9>aqq1kEz4j1L3CbehhxQtM5KVKY6Ha
zILx8)R3D{%my_yl)K6LJrsGh$tDdwLnz`yWG@;K^|Fjl$_tnf$0P@v8_@Y#(zH$>R
z57f=aL-UbMy<!lGMd}}?!r>?CuX>b<)g38XU#cG720lGi|4bp~GIc%ela#A{C`eMN
zRz#vNo~tk01NTyW`B!LGsVAqw(rfjgCg847cTNCHt-AAF;NGd5Bt!Fqy3G!F@loCD
zGwSNqwk><m!UlD?fDgh~^)lK4uxAe{kU6j$UZZX&+nz%yl>L*0VeF*$FcHBz&4q~z
z?5qf|MX|w&=-_BJp7yvevRjK$y2PHBVD~ax;sTa9HmC!H3GB@$C?&EZe?r|=c7%;W
zxYyV}XrXqUy}tlD$?Qhj<xFAke1tHSt$zSZw^)lm?545J&!R4aHP8mYZT7`T7`(%-
zq`Q^HemV`6Y}SdU<2mdjdJyy2m4lJpW0UrSI-jk4fl>jhQ=#)7u)cZ<_CI95p@mEl
z>yA@Rs>f`TCGf47Eu9CuCG3(07<|SiokXdOwTl5wB|GsRbw0b4!d6vm@pK4ZvB4Db
zs9}#>ffsMsl-|hRu?}y5d(T>?K;<K=q$u4d)|H;X26n4RhaJAKr3=uB_S`KT4^r*m
zifMwflM8<iPj_+tVNl(}txZDa$PMiZ{66m65?FHL`cj(?a9wF_agbYHg3OsqrGpHI
zIrskncj1m*0Kk<iPeyi(o3RT%xpA$t;8PO!`a9a}y3RFBMe9?zLwg}j<)UdHE{$tN
zdqnBn()+M<o6GtL(oD{vg~2Rt+zJTqa^d5_mcwOi!#&95CeK55pF8ORTs~JtyTFCq
zC7g;<J>U{tVZMmdQULQY7eZ%0O1K<fa1JQto)h;o&gCO2%eZF8fUn@vF#koAFpwr6
zFSwBu^?k`5xdIPgan&<ji+h-C0re==a?UK8{f>*A2*3w!z6bR)*PSA9pSkhZQL5*D
z>jC&zE`1#`d;Y+5XgctoH&NQj`;G(4ZvF@A?LEBuHnP3^F$x*(<9q%K>-%{RI?Hi@
z|N9+0JH&5v0o<9NVp{^$Bm8zp6kYhqK4`=-zAw!R-FUk@u<OpRIR_OFemSkOPx8t1
zz4qcwCm{6UeM+I?%Rj3{oj<R2gBJmOP(Iua;?t*q<uredRt_P2Q7uYm_|2nnU(WG!
zXjXQfKh%mQd0~8aIq>29e0uUD`JcwXizwc6DY#?!UuuzE<R|@!#@yrWXb>sj7tro`
zA#W@I{2~AEb!3nD33FigG5^mLkUilYEfALS-wg-uDW91Hx6Am}{{mOevva^%$$Q<U
zC-*sjdpx97{KR3<dBsnQMyZBBz5{pi4R4nVd@b)o8_@6g1X^L#@p3w1@`2BojHZ3&
zJCgZ&{-;f7+85pu2QR+z?UMlCA$;o!G6!Mr15oc078+2uTL|h6GDqQ6Hf_`F6=o&^
z=p=*{Lv_E9@E$q`h2;mJb4VCP2O|y(eQ5jUh|ppe>Rg33?;$)Y9Nh?<n_y=}>A3Kb
zV#ybTW~(8L6iR7;iWb%upu1v(ataP!5|(d<7qP+udPU-dKL!F|ix<u!K&MI+9@FOH
z6(M2*@YjUqCtxW_IN^X&vXIdUh#SJJ(a=m4me4-xP2os2d`c5)DXN$*teuNerm&Kt
z7<YuW3joL#68}P7j&LR)!aSjjHn#5xx&bhhFC1=(dr)8#?Eiv^2ZFo>R38enX`AJ-
z;N2CaCxX*u084~Qip-P>mMQ?B2?uHJQYLi!gsejNN(XQ%h1aLR@<NcOK=@LaLIH|b
zLNM)yR|}^Wf~-aex`?_rf-VfM)e72IF!WBaZO2Zc>Vpt}0NF>uJRRNkS@`@0r1e5Q
zO$ojTLLCrah3}d`xI?U?^|XU%X$tpGh(FPS#8d409pGN#qjgX@C0;FsGd^PQaCqS>
z9*={0e=(aTl>y>DIx-L>#`4Hci#u!y&<PR8c0uusc!(AT=R|K>E1efVJ%Ob#5uJmV
zLrkbf-34)_1WS=(3@rnr#Y0n|5+m;G0=t*QkR-G>R^0grw<%66$Uzn__B;#W6)|fx
zG_Q*P(84WAyhFj3>*5JNIwp}KUcQR1NfqNs^_IBtcW|ePp&Iy|A?E&r(rxjdV3h8N
z&NNNQ65DyfnQZZ}0$GmePxn4gynPbzd*UM62+kMJ9YU!<?9~Oh2jacm=-7wi?6+uH
zk(f!*oyX$ukqG;$ip4>t@TNqJ*#hpTqK_y1ekNAak*;zviXN{DaYG;ApNsQbAbTO6
z%S6^7E<6ji-O|_<$Xui_npC<<VP0tHQK?`&%pa3HULkXnQaO+vmqIAm<1QV!4S<LA
ztUDc(^OUyHVTzMdQ#*L!C7q^`?UZDq{djMwgq-n_9?@2XujJDKB|oX<O;`$){`?9+
zkkq*iJPeUe(J`kpQmdH|W=NgBK;^bnO<Td4QUSdHccg(d%4SKo`y#t5ZLLRU%a+D&
zN1h{XCSa~4(QZ?o6h?bM_atW=09D<Wa+aVKPb41=gvHV_4zrx6l0E~SP$Atl!?j9j
zIt$@*skH}nkd#Q_mY33@Tx3;}h-NniM%p}Lz|ihPEg<bjze1nbI=sD#)_1hhiO)`}
zmc!l7^@C8+WycsOb*&BtU$<A(8Qn)_K&M9>t){+-xQN#F>{1QCdRZpH$=)@3==aH<
z2!_6Y6@s(h9CD)n<|#l8VCF-ApgslW2mLC?_23QXkPaDCyaRMYyWc}Ptc3)+;Y(dW
zH{vqw`i>g)80qL%bXs&w^$qBZEyv!zYTN<Wmi_H)Ux&lM)+t4B*MaFogYiM;a}ShG
zF!#QJvN!YO7vKXJ{~Zv9Fbn90g)*K+?EkvMiCu6GYWvx9G-w`R-3wsnAnQT1g+uIF
z`qDYG1*cJWm_1I>kR$9>+K_NzOK7rTb7d#f8sI29f&$>jSckoky0NZJp?aKM{u-G(
ztMP_WPxc6{noqJNeIfK_3u%t#!**37^JRUh#eVE6TBQfF$JPT7#7?K}_S3AEwx)yG
zQrhqfVLuE(c7}aV@zk?6_VhZ~J;x4c1=8~@qeK?U{zS3JF!mh9@50%We?l0+nnjc@
zuw^TeMY1P3n22IMDFPeKZu3F!#IU1iVsVlE`!j@>*d+QI#j;l_kzHn;55bu@);$>h
z#<Px|@F{_{O}LKAM0Va6WLMb7sgNeI5_Qydws{kHn#@Mgto;T%dK`o)Y>RO)k;*0o
z!R?!DM;1MMi`9hzm(Grz4HFsc`TtFc-HK3`$<FKx_#JlG1K_gQ$v82ty33xK3(aiy
zm5oj`=CQT32EWHvlz{X;JDtwb<+IC1LA8KYbwF0gT82aO0sHB9wEiLcMgZv}b}E@K
zV*3%xV|Mw!=+Y-_=@>Xu%wG5gEG6tu!Kf=`e|`#<r)<~()IDRf7NTWk?1>I^#Il^-
zNsF8cwhP&<WGgb!m(ST!TCu%g<rH{-$ui?mSH&J^hSDo`b2-dcvocR)ui0gHL0ZG|
z4#?iH*N4N4w`_WQI9khgI1b!9)*}N3-?ME$LRiP%q8R2UHvTC^oj$XrG!}hfd(ny2
zuWSIFhO+18H7?<~PW0j0&GjS`j$9dj4uLK2Uqz5Qah;cgW<QssL<<ja=Psb`Ag86x
zghSjs>Jn!zssyFO+#jpKd4yBal-Px{yhX{C8&oR8*m;zjL66We&TS3Yj&n5>WN_yk
zpQ7Z!<z~W?FBiBLnICt}6OQ_GI+|+*aPFn(pg`_-8vBB{+)nhYb2l+ase-w!?ZFbl
z6;XWu45y;l*ICYV6F!~e4$uko^IVJOfZIa3h>g$*;~ZK-8qWQD3t0pgwFxFJaP>58
zj^tWWmqu}8>_HmMMbb(lhHFVt#fw}V1u!mgzfj08mKzlc^Orea+SH2U2F`>qo?9~j
z@C5Eu4giUqcLG?haO)_3c-6+GB%^qZ+x8x+N!*`w-rzd-WiKj|x$N<9CWSjr$E8xa
zA=998lWRr~@-42-U6@GYdQ+4;ojX>Ew<?2MO0mA%-024}n8|&tfWbSQJsthd;?#0v
zce#mlOeUNAmUeh@INMzsesj6ZDX^Qz4eN;P9@mpbiu>GZS_9;B4e!BSz#ZC+tdN^Y
z2L>N-(JR3Akh?>-@)1}54}?YBXeT)Om<zPP{1YxC0K#JKPdY4D!kwp>Oet4R(Tt~D
z3wvlj<C@zvP%Yy+)BL8KYaa^L3a)o|s8(_nbmrqZcOngzUT`mI$Ll4RPWydTT&qIZ
zeZ_rGJzLF1*8~2V`%H6>8t(lK0N!wme}nKXCq6<y)pC!2hUPm?Nh5><&(pcM<NT;2
zw01bbZ&1OYCm%$6!6#9|XV8mpOPi&q_%9uS_vT$r0`J3jqX3gHU%nLpKfZ#td;R%8
zuEEg&K8;p$fxPTjWI;T;8rf;y<!``)`4RLshVW}?bU(vCItJIy@~`9Qh-WD8N1ul<
zeiLoYhx2`C8XCbjrAPh(U)BzGBYB6@C`Iur-C;1A-#Q;OG5jC2A$pO|rFZ)h|2>5o
zWBHY1p?R6_{S_X@@$!Cv$MZEblS$x{*TAPlJ~j;56~1{DMV+qlDc^zS8b5$O2ub{e
zi%`AJKb(#%nZJ1t&fMS&=);`C_rX@8DwVGs4b7Xp<~DG*_~5qak~F?72~TG_znw<g
z4E`VbR^R3u&OtMi|DASx?(j`0P@2WRy$BEQ^2Xt~leTPr@G5ZU@Up{T%jK8dgo!-<
z<pHSP<Nu08=|11LA4v0gt`{^5_$IVPRmhLn1eyo@v;`18<Tc08rboOpHMEFdNz;tS
ze7Aehe8St$L8+Mk?Ie79${(ByvS+-7hK({C-}eP{%K5I;-U?oJ2{e_wdKPq^^LcbU
z>IHu>8qU1rtLV%`6+fRgI$rTzhXPm4hXx~i&F9lLat-fw1#No6*QP-8EkCLm4A$~3
zDo}dIo9LVRp6@_&qB`Ez9)J(LZNzlweB`@yLnnUXC%1zapLs6|LD%zFr=d$4__p_e
z|HAvWf~BwgnguX#FKnUp-wvV8Nsu}SPUj)qDa?5dm0d#9)5vxU31`8%M@XSx4mb+)
z{h+y5I39^+?-RCMfmtUZ-1Zih_6uvmfj=P3+XCMX3hC}Jcu1H>yQ0p*8Vckc7W`KL
zctrT_Hh?a|`o++66(S;`;wE&rho$2}?qSrq3wD2?<RRqcB0C{W`Vr1}3ZIDcq;T2_
zdtQQ*8?sYE-C`T0-a-g<w~ugV67ar4{05Z#gz5`0;V*RU2but3H7yzfh2E3V>>y$6
zDA+wMjCMm^urPHhN+AOMUJk!INToUaSs`yE+&(8f8;a6-VKeQAh6;DrK^P`@%>XW3
z_&$}#`xhZ(4g&CkV4@XFBqIGV5hb*xqf^ns-0AQzM(~^j{6!&>!qb<8dRpnl3P)66
zyDW6v3}KwG22Z&vUKoE7ZYK!8#zL4VETyAfSA@xQsQ;?)j#g^dgcGa4nIufZ+73}C
zp?fH3l7;59)pkP|=m1M8LI-+tQiZmkklhrVL*UFUAvy%5G~serm`E4QJ76MH*iKL2
z9l`P(by<RS8~W+4Fq;n1Wefk&fwLUpt{v>=3L9wKBTqP$4@d6_`;Wq&?Y_`af;3<7
zHUU^544MFGq0s*cvIoMQ4xo7`ETM(pBO#XpMMc7@bl@KgkG`T6PXwM06%-2-oKaUI
zG}WM?rNV^mXv9<DB%Nn?COp3e%`)Mb5}M_L+s}Yk2oEnorP3zUcSGfKp=}I`FNEWC
z9^j>r?1(m131jG3#4ADEfKs(^Vm-3gf?XsWtr3#xQ0yC_HJ$W*E9~zH%~~Oc4t%^5
zj<x~Id!gkZn6DFJX<z7r5J%pB6h_bx{7G247=X`$Z5V#%gk`$tCP*8E^|UGRMev+~
z)_)c5EI`lLi#9T`L$vNk$w91Y4ih`Y-)Yd@C3<E8zFRCx1=}9c?K12-ipMA>x>pQI
z24J74p)(o>#IvgbI4B-nfYKrHJVnBehy}LyK)8s*XyN86UZn`So4D#P=o}Zh8F1KL
z987oAQ=CM<AUP=}(QgyH#Mpz#e8j^`VZv8z*bjq#VhJ5<3>5ohp%f&p5@F)BXf(s_
z8F35^DQCrI=^#5N=6-;M^WxTg+I0yPyHLb2Ow6P;M7a1a9?nFF$0&w%LEQK^Xd*>(
z05qe-p!1-K7FX^>79;*hp`DB3lyPw8lITc>6=TKev|Dpoj4no9ocJdL&UkSJohL{T
z*Ia|$MA2LUx37rZl_K81tD<5)5ZA=jouHZ|_6$Jfb+LqkNXg<fI%s`Ebf68P6fx)=
zyhs&$^heL!6z6#Za7%2n5a!dwmK3E+7a!7qnjuc7Vg0ta4ToD*nPM)@>h6d)K7uSu
zbl3_<bHx9~)BH163?Bz+p4gAhVcrurorI<PV$D?0<cl?O;0wfVyMQkg$CLp0KvdED
z_fTv(76u=Q9tY7EMdCg)R33|8F)LR+5uecWSS<220F;PdXiKtG{6vw?r{d$0z&#V2
zQjptLCeDihTe&#i0816(U^+8XDgNOF#B;Hd7Pv3O_7>E=6a#!fS|#4ef$){+br!g4
zF{c#5*Wz;8tgR6b&^-N(*oQu*Z^hr5!C<XuM{&=0;ue}@y%$^k26&yg?-1%f*u=nZ
z;NnNIy(18x#Kkl}`Yc|<hOnw$lnSBRAht{d{);$(w*9|~hci&Jm)=q=YKOFRG5`+J
z<9gKXmcC(u+au|D2puIY-KM?Lzgqy<Ck-otqfU}E0xJ8ZD@&kqK(Y;|!-fZ?rVCI!
zB-wM&ah3-6f-{GuK6K{hh;;WaaJxvGXm;l+{rEcoM<rJdrDM_!92-PzX3IM`b6hI+
zM&>S!?gzUblAkMBPDp#dgV0lQX#v1V$-5RpFUd%=?^9BZjh-uSY1>hl@R2%cVBS~C
zrQcZjNjHCkj=wbSD1-sh-(#Q>D82a#VUTomBU*7<YX2N{!IJ+r079fx3JIT)6f{Dd
zmC|Sueom^T?Z5L<BrW4YrK||3gh_>qAPkpAG^OufgtUT|ffuB)-QY|lf;y;-lI9vf
zdQs}v7o|&5YXeAQr9tmNdRe-jh%8PTLy@U?>5T(e5+uhFU`dqLhatNnt$Yizt5Q$;
zRm3%ELM-lNk~D~RU9L;PzNkx<Dn`>!>~2V(0)R-7W)47>DmCj5#7$|}EttP0{Y}%W
zG|BlJ_?<4f(W)*(8cN)^rTGh>nJGOo!TcTR1}zw~r0g?r^sZ!R3D>fvO|)9bk&<2E
zZ>|)C)13%RE#U#UCyh?0U6=b(*m<-tUz#u(1`DKqhoDm^dF4Upf%JYhvLeYo2!217
zI(~rW6Dj*oWTn!UH8B5FN~bl;Gif`GY!%X}2nZ{sT@k=Nm;R)0Ta~nGJ6wAu&A1C(
zwX~GB!`?{y7QvqFt>n|VHz@sr(LnW1T0+Ctd#S{TQk@hY1NT2ki)q8}v$Wz@(9}!6
z&<U9asa_3BUnB)h#J)=J)bPSyvy4K)J2df0C^=}_(5t;ubLT4T?$T`R2>5Qz<%0n1
z(a6*gI@&agXMk<5CbACQwofCx1F4gyg$9-TH4b!&@_?pe5oiu-R#CM2kmf~K;GH!B
zox(b-c}k<@5zSDF?7C<!Q<T9~({Th;j%r%3MRrUR?*^Qk=B@)+j%&WgpyaN(LO-<g
z(AX+IqN7e|Zk+<&Q?noeIwv*xv;gzcnBpNkrD4axLvPIw_(_DyN0UTvj<4ndE%p2~
zyJ$byUsF!u@c_*h+JOqx^c(^1AdR{eJUp#gOD95uH4jxNg=l_U3HTXJMG7>}YL45+
zL3&Ozi|)mF&6I(t4Ao>VK^CT|DFf*RO%+XQBQ<GV;8T=_UkZa4HT`La<C3O<zJ{@y
zG8!~5Yi7}6GEUPm1Df#~YZj;zG;fBXE>Sa|b_}j)W?O)}s&U@~&TE<g8NGN(n)&#r
z2Xu^Ei&C=YDjB??sSZN3Q#3s;0GO)TF$~#FO<Xv#Tbg#a07%m$Q7AfHW2P}7L-S?;
zEZx?uq3>p<W+|OnyQ3Mr9AsIVX{jK)tNFP*e9G3C1_76&NgYLdN4c6-w@{g<IpGY|
zdzu5zxNG+{qt1dRUn5XoKG1ZbZQ+L+#dQE5X`If%V3Fp#)(}3{v|9?zCz`OE$VxS<
zX)t)IS=$)4)s)lG*H@ag`_WI;n)W1ot&!+6R-?IENJn<xXu8}0>08aKF(9qg?5~H;
zJI&qC=*0J$gbrv$o#wthy!fE0rtOQ5nzIy!`J^e^hSF!vSXyM&YnIrMHE5R6uUfun
zUQjsxt7e=EC421x8ufN)&AVa9L7PJx<~y}VDXwbUr9DYs)7{z%T8i({4qA@PQTreS
zP1~!D*2DdM+HFPf!bzLw4B-Lo2U>s~)D{c|=^^dY*XTTFZJ*zua#-s|FZ>bhj!CF<
z(cY&mFIR0Q9UnWY{c8!FIi}rC5ePS}JDt%!Zqxcrf<bq!kq%jTXglqL^n^C@DG;98
zDQ!V>Qakt-N?zJ=H2FWJ)e9i?);iM}Eg$V$`XQgMc997sKkaOK)BUv*S_2TEeMghK
zK<%U-00`2iQN$%gTTbuo8Er>DG~%q**6<2WozqTj4W0Aa@m+xk)#_<{4bx_Xp%kv|
zM$?=KZ7v<6yP*B$8+Z|^?KK&tC~bZdxE-yP*TIVz?RlE1UesDf0)9z*st<&*+9toj
znakQ=D1s2D?MmZRy!P!Gz!S8yZ1ho0)Q+QA*cI(mKd@cZmQl>&nl_PQ@=4kkm8iR}
zHQqrfSvxfrKHbocbp}2~JC~M`salT)H0`D~(2TlU+JJDhFip#k1|VH~f}Z0H?Z0y&
zysh=8y}eBBR(EjT(RS`&gQr>A93D>H)ozc3YPQz23!dg^KaYnnR~vo^!aVH)I<az3
z`&R~l_q9hUl8~>>p;HHi+S+6A;(<1Z&Qm?q&Yur29%&u@fh*F!py>KzZTKh%pJ;{0
z&@9%Dr1R1x+U%k9{VUaO+6jYCwE_4wgX)>qlh(rJ+AfV-Bii+y;c%r^ng+yk?S2jL
zFSNF%0KC-RrszbK_6Ef-UunM%LS41ip$Fivweb`#uF)1z&%DuIu%h%%dxk#7@3kiS
zM%8HtqRyuJpl#&_yC1cC=`6t~?QA;J_F4O38vL%;cKRNEH)szZ0qGa*_rIX^U$v3J
z$n15_)N4C+%LW6tOBYV(Wp?Ynl)=&-U4k7lN8LFkyx*&<q7~*oT`WZoopg);fN;OA
zv;$OZ2Xs#KuNe;Nh9*JhkS^;rd^@76rx1dRuJbi`;i}7751)?eX3;MYj_FQxMzh^?
zZD`N;xbEB|sJQE7%i)EGZssLqCv+QRu;i)RDo5Q(-82ePc<GAWVepjhQx)ua>wNa3
z&c~)}w*_{6b%pilC_h~tt;76vyM16OKo>_(OQ0@>qU=Gs;IU9Sts5H*V6g6q4}>AQ
zOW#8CjBbH1va`D7)IsNT=ck|%=XJ@^Pzlw&pneL|ozbBbuB-Kgg$UhBJ<MLv+0tk;
zB~sV?1R4{iTUihHqji7MJTOMLG#EM;bx!nnT+&rXz<jK3*apyC)-{<2*W&)?Q=*Qe
z(@|G+|M3uB)eWSD&^6uGb+DAAn?%#W>$-MBz>=&hz%OZ4H+0jd!%&LO)z%FrZt7ms
z8IxPOdtKl~n(ht_p6R+nRVZcX#>4=4TX&LHId^m>Iuw?r^L0UXSGT(#aM`-ZCSc3a
zU8QhHt}d01>)hAH+<~L{x^1-DDA0`>4q>5ge-8j2=>Ay`&4;=kt8FmxNcYbG;EQyh
zDKzz1SLY7l6WyYv@U&RhM+@^My4w$dDAm=z0ozlZL50#Y-6T3{Ql|Tfz6a&H&8NU!
zp{u1I^i=A4(U|>Qr=)Gm7dr1ZXwpkvaVNm5bm=}2zS6z1(W&QZU3dCD!E2oxMcHd~
zF7%W0_qq;7I8&!fEQk3Iy3&^re$;tV2Yu4LY7e&0y0`mKSFam(0!?esZKm+g7u~wC
z;Qp%1Ab`F8aUfjVp?^sm9u9h(g~A)7zwsQnU3%wdGQ59|`Zlzf-K)QegBhxQ`nNPe
zanhUVmD#VK#Q||ZKZ~Xm2lYo8bm<}eOA1mr>j%)s*hTL+9nQGwuWy9#sD3ORCOxL_
zMZ05e`hVXdJFYM20Zw;)z+k9&=)GKF?}YwK2{>(@`hOBpc~akz&SQD$wUr?C(LbV1
zYG1vcPUQLNyF~)wuWv&mae)3pG_pYbm@aT8NIz#6JUp#0q<BWK{^uYV4AHyMA+|I6
z`cDv^)#oUn5~?3wfh<g)P=tFBt{<};79wo=DvGvU(6^vrD^fpJLf1s;g*(Wi_0_+^
z;TU~H98@prCk%wjCH<rn_#LZ{r=z8p_20BY7N?JU1MYbJ$zR~p75&Xrl&<Q3yNX`F
zrhi4j_9Xq?)hJ!p2O42MS-<ozn7yI5ZTkt_Df+Krs7%#grb%L&-kJ77)Ad~uOjl*-
zeSQMlZGEpA2s8B)u0eQ5Uw$2cEPc|C=!?7hxhr5dTmO;vD|7VY3Za>+H|s#1r=M{h
zS-yT71#=4Y^PWJZP``+_J0IwOu=NK1p}yO0n0Tb$PrGwP`i#bTl|HXI8u~;(tpUJd
z{bJftD$!$D#(SVQ{|A~f{U`cfm+J@9FFq>tTXO-Z)K~XJ-E;kva8SR{D|j^YrM@p6
zhN;rm)6norpWPYltk!?bw4wM~e`_H~YxFCdgXWFiqYjOEtN*$k+_n0pG`*_RKkkcG
ze9+5i9rsaxauF<j(hs@__-B17{k*tdpH9=12E7w~%fIM3ngV^*FFu2kgJCl*NOl^2
z{SPX;3<@&8+wg7U`frb6n>(bAhIO<C*lU>j29^5^iw7WcGPI?s%zncQ3Y;D=*a{&$
zXjo{6(qTjU5g<Kc=tcL=#bBd}n5&_T4j3FY?3o6;#|(cg0Km=ApMKPG+^{tRD(;5<
z_W<`Wh<I{ssuPA9U(k3OEDxb`%J7F4mEML`4DO+ip``+uuc3hUJN*m`UZdo1SVUVC
z0S1>|$N~+)G#?8xw0Q;GX~R$hdM4Q5pu-CgVrX#{2G1EXZb5k7u;?rLFx2pbJ}zN~
zuoH027H*hP4xI=?S8tfOV2Gx*N2DRv0X{_;-uj_w7Y!z7)Lk-2y&#M=j93er%Z97Z
zfsZqczXM^sVZ>vU5)2ie!JTOMOf$|ahLd!N=c-}$zsRl`E(uUcG9=Ty=!RkaFJMWr
z85X@no@(H`p)ofN3%-HDTZR+=Axkp^2cj<BaC<m_8HPt~;o5D(sHrfRX;|A6ZMtLN
z=(pin1~(cnatyUsQOY$$(1w4WVU`Sb?-`1Fp>*Hycoa(chJ_SQFEAug(7MoIOFsm*
z2Zk>+CwORR_X|4lk-_sYXo?I?I>AJ-;i(SJlo+<#17B)5LhG=nhA*_=^31S48(EoQ
zg$aOiLo^Nj6^7Y#h^NxvSP$V#L+^R$k}5;58d!K`aG*(AwPE%^sJu1^HdhpD3>A|>
z^TsgLh;Dmp(9#+9TEkIVslGFeYmU12hNW~)ug)-r{&UMG!$XRse>SXHgPy53SoQ(e
zU>N!j>b@A<=79UF;a}PTvp2S<Im8a*KNRtFFixWTy3=@%eiO6H*s3WlT6P=lmqB%(
zarpw^os7rmApd^j28!+<FcwuIJ7|<>hx3q8PYpd{yiAb*7o$Y86<6a!`eD#fBTq-_
zjv4#V$mV7|p9tY`<GL{*b2m2G08J0$oL+#RFxveFv!2F(mec;jN#hcFbG(dgSHX)@
z#yN}No44^L#UXu+!>@zJ*BJc_q<+TTG;#Ge?rMd84lu5Ngc8P63gibFE2l#9w9))G
zO2Nj#bRa3jxcxS8XN=A0N1$hoIkXLN&e+TX;dx^hjAb@es4<!r_F=}(3jqu_cA5>}
zB8)F6*nYw2lZ`CWxOg$}QN~|s${1}dq1zN=>^c#Ei^k(6XwxNQkFltWHAb9<+n0?J
zEsNreQ#T`vH`?=1Nif>eQY+DTzAMPC7$?x;%y!kdjkY+h8MP~6Dakl(Hgv8V*U^?+
zvN45LNjHqk+d`OP<bMWts&VE-lx`Y--wy6u#^~07ry1w}2SB=U@FUb^81o;%!`sH0
ziRh<H<BIRWa>wX)7#6aOn`sl}uJH-Q1G8<$j<ib3G5+!kDszp0u`rQm+*5_@p0Uac
z!28C{9Z;8VO!o$`z*t1*0}G8gGzdK~&ZMpKhsNpjZ(|-AjdX~h$T*S%{IRi3EJ{y|
z7ibz;Y?RY8USd2|0bHrE{~WM9HQKJ$fb^L$raLOjjMbNbC^udmiPCf9W;)9L!q|H<
zdiJI9U>!)Sj46L3du2RHQJ`vL7EUg!UK{7!fr%R9R2H~5#vGbzzBMNF09mbZrw=T=
zGakr*!S}{A>g_sXfG;}egR#&?$7MenJ1hb4ld;7quzfa8ps#qn(K#484MwMf;QnGP
z*1_&q<DB<suf6G^4mWRy=@>=J988a<0JqaLQ-``;CfRP_cANZYI=IIatVNxp=}coR
z*wp1USoWDj8kw9-{odP<?>DU;3oj0sejNbSgC^NDln$B7=oi+`CKdf3sl%o^>h&Y0
z&O_j+iz)eUWUi)~kq{m=wO9rZkC|d_1MX%rya(X8=`9WK?xtyU2*JZNoECK_Oxr2u
z?r93s!o!oMjWM+T^D?D6Lg$nzeGq88O?9+R@G%KA(D<5izXQV06!s@9`I{zEdjm|T
zX_ggeI<pP^9As({h|+1(kM!G-VAF1j*M^vCrXf3H8b&{yJ8QC|H}#z9>3x*Wn_3Tr
zYoVs0UUYUa%;ZHsvI#eZQwK+wZqI?I7fjpYU_R3HbQAg_%4DRywrG<>Ph>GBZ2|BX
zP08UfamjSC4N9@5v{1k=o1AI@k2C#12R`FXsT9#lFm0lPv5BUYJiNGKN~{6ys%g?a
z0BqMy*UEuNHeIGudN)k2G^I~5eW9gds%iH3K-@I-ppW@26WbdNO*3_D2kvxJ^bXj~
zFwLOY>TQ#^BTQtPf@zEXj%jEXN?E3T&j7z`!oC7tHPbU%O6Qo)(<z)>(;xJ7<=ISb
zH0s?mecuVi`=<Fzp_6Y~GX**YroVQgRA_3}1o#K0-wNQxLsKbzI3Jmw(08}U^mjG<
zeQfG74W%chW)3h|Y>JqPQi&;+mJp?;?|OmksmbX*e0pYjwit%WOp9m;E;rd6yMVO9
zG@g#LRGLa@P5a#BH4nfSCL0|}dui%E1Ef`^950k!nMQM9t2X6j!Hd_XUf-frW9mu&
zE#!@<!(f<rYwAV6J*hSQHV1X@Og$5ky*CYxg0Rly*9V#(OozK5`)G2u(RcTg>Ci~%
zd^VMKMpkcHe+KS1nC4A^&KFY}Jzif;7ddd-n^WkJ<qk976#hDxpXC9t)7-@qD!a_#
zbZmUL`TiED>@k=4LdDU1m=<n(%`?McexLbQ`l+3h`4Jrw*>C=%jJ|&d%mozuI%v*G
zLw3mA*&j5{=34q)?qTy#ng<>+PrMB_7jw7eP;oVX_y=r9&A+KZbIkmC9aP-Rb#%h?
zxH*XiU3YWXE@*m~Tc1Ezo-~iS4-dV}1BamQl)17Bn%?H~=V<@W$E>2GJ-%lBbs+rA
zcD3O4H#h77cYt}pKky>ZyuJw#LFTSM!;91AtrUR>Hb=CB-4OF<+A%m|4$Vj1S@Qzg
znK@@3LMzSl=F=2t3N>H9g;JP#+-InSn_E!pBh1&(YMbhU*`H48M4B5Y!W(4{p_y*9
zc|;-*F=k)twu@#j+FZC~9`BDV)_k)sG%uU|X^$YzT>A(uj5mkcAxkh{ZGkM&ys;YD
z74sL`<i2X&yA;_qvrK_3$=s(qEL=Ay;PqG8lFe&*6mOXIG(x4Ay=i+a)ogAB)tlzv
z2;84r=2jF!Pcwf*ACh$QTu-zq!`xyh%-=S*Pe5I!xojg0-Z9_$11wqQDmqkl*IY+2
zmTYr7+6c=rzo4JI<(j={d6H*tR*742&t@L`1eN#A$LV*l`DWZ~ym;oDv|KMV$E}1j
z56nC0pA<YaZ=%J{BXg5@m?$z2J`dL(n-|c`{)zcn8<;OPkD>jr60_eeWTobrL2&e`
zxnC-9&&;P6K(oyJFCAkkH`}GbwF<NCML8-f&HvKo`g3zEO;BE#SJ4mPUYh5s;c1om
z@-QG?nI|dGU)APS4)FW6`BW9SYs|Y%pm}39Y=xum%^^PmP-iZf0Qd*<v~XyCG?(2#
z-6yl~4w|3MvHl>d2Pf<`nCIFCq4>r8nSTH9)$C7ST6@c~=V;6h%bYzZIap@UBz&i3
z<QbH9Ssu{BZ?|PK#b)+c9-aW)(b7OWlzT0+rlZ;WEL-Tbg_Gr*BD8G3#W4kr9<T@#
zVE&*bY$}{NWEoY7lC$N%ueASn*s^^*bdFeN)3%L^<r2+%T`eqy(vDh;p5Q)aDXD^a
zH_OlTjvTlAOxxP-mf`bZ$-@#tv9}YJM-(LVwCtf7=SfQgy(3<h-znyB%95N46>rP;
zPtZ;u%dc*z^R*mLpz~*bmL?uB?{B$IG4}vV7@cJZv@kPK3bLFpgz9O_ifE7qTOND?
zO^8L?5-Mjb1Hw=`YgrNlm2(!4d0;tjIYP6-P)qL`WMP(*bSJ|tuKkcjSa7%w-!@B8
z3p66qlK3P2i_IuYD-NpBmH~9qEygmE<`NezQ<A}U$ueLdfU%a!(Ewhy%-RB<;w%>W
zUdLMuLjXvyoY(+(qGdj*T(J~i1K_G<!4SB1%@Vo|bxD?emjSqLxqS?!WQ)`XEH^AO
z>GNqzv82#p<5bJ;Wze~4S#=hqw=Daja1YWfO}ybnx}|`2KQk<LQ9#_b_>KT~rp3}5
zDt9bi3(zxJmd+GkyK8wq9l~tOy>zJLSX^pR%C$_RV`O=jd3u!cE%&`)sKBz5LeYgb
z%N0EweqhO<;LJnIGAEdSWbybJ!XnEdT39@`tfJ@Yi6vk&fW?+Qbd0UU($pS4m0Au{
zOz5el$4cOySq6@Vr83LfS-_QBl5e1{!s1#9>Pk!61k^pZ^rT1qg=MM_R9;$spA`dO
zl_hNv*j`z*v>2_n)X|N7Z8;PLM2%%E?fAX1w4jysTT7`HY_*nlvqAIDl1Rrh-dm(Z
z!0RkSL*d~EOD^pLe6)<*2(nL>iS!-%Yzc53{j1sLXoKQc%NSZS*jp=Thj53r%{a8r
z!TNkR4D7U4wu6CP)(|<2@3uB1!_FRS2Md@Tt+}ZX?zKkA!Mx9UT>^`f^+(#**>CL@
zjJgBXxgt0ZS`!>$^^kS-BlzcR-Es&jhpiDd9wv@hSKkGji#3uy9In<m+n{sQ`XdD%
zj#)2;L+EDhUkvW!)}dEn-rZVGBbkTwUs~Uuu+IGq6;Epynqi)_R*VPE%i4j4)l=5*
z-C@bw%2UYA$EuD4+}HY!mIZ#+!VA=Tf9q%oUIbXr&|4H}UGM=}koCttFmc-IB%l?+
z)@0h&4Y8K)hNUysB3c5UweDMt(mCs~9#A=N-ATJ)q1LNJ7G`bv3jpEPFSMMGuntdy
z$_1<LCvZkumxMwXW&N!uO?RWMlMVwBV?D^g;fvPh>)`2S>(w>L;;d=3qK&tfJOe(#
zx{-#UMC<F8$gWu1(@nc-t>)pyHS1AYk0)814}=%jtyRAvOSb0P!HXN#4x<21u{Nc^
zP^z^u54fAwp@<pVRJW}C+M}3e-Q<X_Nw<!s?`4KHY9UIutrDG~%d`&2g^4@X4HW6m
zvMT<CYj>@IuBgklded3o9BXC|n9sHTy$5x9Ru@{d-m|*B0PenZ`wNieTSrU<b%FIm
zAOMBdi?r_g=7IIqVN^b}CMUqRN7f=Qm?*M#9tz-Nt2h1B?TIzzXY^OGb*XFp^5(Wy
z_9&ED57KhJ-1;3Y6DzEFzk##T`uld2o?G*1nfSumW-;u&wBBiotjgM)zIv~$Y46~5
zwe{m4u=?6+`3iG2@DqSHR>v0TiMQ7KwCJm~E_(vbch;daF1)wC=?8b~tkY~X^Z#JY
z?gw{2T2~js;3w-NI<NKF+J^pBK)p4&DYzS~9r3U2RbQ;@0-^HND$sV0y<G_%b=qNP
zq+=8gc0YfD`JHwn+M=|}u9X>eyX}NcAlqXX{yPAUcKxov&|W)DDa`M)b6r9k1WtCg
z7&yG&ZV4T=IAAyD7XT01xo<>v$WE9JptD`qVjvFNJ*fcq5xZapmR#(X)11uJZWpaK
zkJ=5QPw+9j6(1pVvy1(V(s8@Ly2FCI-OrN&_ptjp0Txc$eGEk-yzKrl(+2q|yDwvb
z@V4vAAoH<XN$;euT}d?Xes(F-(O>>{ljyi~fSoVxYX;gSc0(3qcPSDyr|rJCpoPJ9
zZFZr%L+tA4JnR{}Oga~L)^76y7(8e93vJ+>x9f2LS*YF8wx|oUo0BEO6B}-Kt}SRH
z>}GC&i3@h)X#kD1Gy1~eD7&De|HsjF$7NZ4aWzdV8~(C*_uhMHnwF-y%Ce=EO|!Dp
zOv@~-d<8@h0U3fa1Oyp^AbW!>6=Vsh2qMbf8)T{czNf#==iD>z<$dmR&$tf&$u>FH
zAdzBIIu7|%8@qY1lxE{j(MY<DW(z=u%`%FyGi}a%4)a+yPN%?<ZSy<TV{&ZXp-&WC
zw&|M*)wwqE-Qdi#Y1{(Lns2is29qhUx#<qULK_L~T~}<fDC2$A#`!JSy=LQ31X_{J
zG_{8p+w8Z67uRiG%Y|Ht%@@>3Q);s=8FFPdtSr#VZ7Q6hyTT@bGF~@qwyuL0l{WL1
z0;{s|@Wygg+dRD#7H(Q?%#k48vKhV!iQ6_Z+NNr3o~AU<9h*`5CP}T$OO)BHv$-=D
z5_fHmQ^#Pv&Gm8!+_QN*7vc>zJK|yfzRlGSfjzK!n?AkSXcIy;k0zTBY9QBaGcyGO
zEj9~jdup`_rOO9xHrAx?0o!c?D?se9@%$DO?X)o~V4}-r%d-I8HlJrhX^&0$EeQ77
zn3ls*pUw6>DDAiT$sO2$jTW_@IfFJ&==mA4X?YX=4%^(IBm0O=%M7R<wF#YrRexwx
zMR$J3Y{uV*hvPPB)~`UEu$i$Q5|cJwbcb)sCX>oCPi#Kf2W;Br7`4|OVR&$1!j{of
z40$_-C-t}4Gq%47mZOXtPl4vZ_?Yrw#~1-r5^!WJ+JiwS#?}vj9cLV)7DH!7&2_Mx
zU^qU8Jr_o0pB1`Y89&gCJ~u`<<(y73lBp={&KUU#JRXc5%8Ge1c5cRey%@oC);PtO
zq9$2y#`6@q`Y_yH!L&~^y7yv+XBa9vk@_-HIw9xBkO?v9&xoV_G=TBb0_Z%;coGi~
z$cW|9XEA~pErVbUW^7*%!E=m%is5$%V;A)tgfb@Ry9ehP?>Pa4G2T*vC7dyR3Gxw)
zPb~nE3?B86U0@vKLm-O5{}(<*Gn{GHy2u!(XETQ3KtWV2V>=zdFEQ@Vhfi?~e+Oz1
zi)X|hhF}7tmEzJw#$YfODv9B3fEUROi#up33`a`0q%xeTj+(}J%Ng3z8Q;$bmcg+7
z1Xw0x!$p8B#$9qIo1uLKfgHv!6eC<_e9VPUxs2n~(V541=MoI%GpcUELu&z}mx7Bz
zhNA++D-7vL%<wAX{dkza#`uN@HARfpbx>2xuy2RK>x}2lW3Ys=bQG3K8PYIlD`O1N
ze9IX>(-EnH5m*kE8;k+UlvgsYJ_lMABX=$gRWr`JfOeA+840;tUe3EE)<Yp+yUX~c
z3F_+^pGATD9%I|Du=#+oGY3{08Ts_tnI=Y1B0w|a`<JkeEsQLRvs)RzQbw$ekwTkO
zJ7WVi|8+2q(EG5H(N2f&E=Eodux>{353t$8*b)HH%lMVL_WBr!|9ywLpHbfiy912O
zFF+h*JdB3YAx5heN{1QFl${u1ymA?fGs@UZKaGcs57Pj~7`LUE&p6|6ssv9kEL16+
zWSnJ#HpSRQvG60t_6q=y89}Zv_=J%_-wK*$eDo}^Bh16US)tUH8BHlxJLci}@WP%M
zXn@_L%;1Ia!htz|2HZc!jJuDiIWprfVbF=$@Gq1eXYQebzccfjOc*@D^rpj}3v)SD
z$6T5BmcWu5GxZ>Jo@8!$0T$eu>ka~VFgxh6_GC`xP?Ew6|275MPBEu^pxc}2y9byL
z^C!A%aGJTe6H3o8uc)BSmzm-Y*Zi0ZJE7E{DW=xA0A}dlU^&bDl$JY?X`c(-LChHz
z2m~{4&ILHfym$b#5N6=-Fdxd?KM4!xnZGTeO9Ej`TdKi^GvBtyT0}4pl|fr1vx8=F
zf%(&408z~EsTVJr+2#z+i_AyV3?9S$i>_b9G9#$z=@N7BS9l-C+!+HC@yxBiU@(EH
znuN|ori5x%Nla}J)-ajbP7!Jfvy8q<Vohakya!?$v*bR|bmrn75HpzHRsdu&4^Cq+
zi}@bi@62Z2z6zx|%!#LgU1t7HVNpKwE>#f=nA{S$UC6Aa>q}RdeywokD$~vr&Rk>K
zQ31P%`2juF#mv87hZonGgSWw1Vr71I0xp&^`>6z6#+*e>mgP)-6C^5_i>M%VgBeaq
zq)KM53_evcgPUQunz@q?aFe-+p5R-|e?s8XZRR^3V5wo&ltcF&=C$`ASId0T1G{z1
z@i7S8W!ihd-+Jb|v>)7KT0f){O9RtN(bausWja_NFxOW>TO;%3pE3I;W(rl5nwcTg
z@Ycd)e1oaAG7BhHYGe9Q!M>e2{t-Y2vvUOoJDFqcaJ!3{K)Kv*=H3B-9%d06pqH6Z
z36?(Q63R97GhM8=p>2Tq1%1GMkooviSQ=t3m<{4E^Sg2=9btaE0JKr&i_}2*konQu
zaCD6MRV`S?nfpn6g4s$-I?0?#Ws@mpkpeS(#LQWbN#JAVl>2(Z{Pb0rpJpE2fx#oJ
zZ4@rsva0PVNnyu2xdY2>&ss&{@=?|#y}=z=_cs9?WBo>79du;vplZ4k%YPj1A7}0M
zh8ky<ZaeIrU~RYy%!PGvA84*D8_NE=v7&B4*-6&t^k#5p+2V<x<H2fL2h5Z8!}nnE
zVtG5!b-Yuoebhwc%_{JU+qckq=r~;SWyxQKYCqPwx4`MoTJ$fl0M>h70i0zGe2c+A
zR)+;^5X8C|0xX#I@|U2UV;!fo&3V>Js+xqchDjitbw3qY1Z!a;{ETF+q8!BqmRSy8
zqFDdZdq0}heGjyYtkYH=e2HPbKqtCbR<{SROROty;E7{Bw+*hvvo>6Z!30(oIhx2?
zNmY|1mXQhu$t)Ayvrl1-?ZIFwtC&(yX{_8{fOM7%RZTKjZ+AmkCTrb~(2~XaA5~4V
zS&cfF&tau)r#<&FtL6>3n9EA9#qS}Hwf{OMn$L2eRV!eLpM#o0*0vzb=?ZI#@|IUw
z-%vb%jdkX0(27{Yl%p?Z_0ntcI%_X|siA~*g0`trR=*ygj8$5W36`@uQz1~n5>wjq
z1}pbZx;0$M`ehWvD%KV%L{+mk>tNz0YYWu|Zn2ipb9b8+&<w#E)^pT$dWZE%FqGD^
z#wjyf$EsfgaF?~2LW6qNpZ5XovBK#f+Q8~P3)+2_nv%B<Snhgw*vL9XH>#RghsJ0_
zY-WY@!+Z<t%UD=yWlhreCfcw?V`bV|ZB*jxU|GMyU?*$khnQLyD^d+Fx>+K6x%9B`
zF2j??I;I2G$2v^?y#1`#RskDe?Gr+7kTuU1J`J%B9f6@?RumJ?j9_H|tfQ<%A?!Y6
z{SXMHW2{1|;EuCi+YD@i6-#&9Cs~7M;rA5lEF}#dvGV9z=VR7OpJ5hHSYO$}{50zz
z)dr5Rx1~YAmMx=PhaGztZ5Q_Jb3eeRW9*ZZcXVWPD4=p;Pr5_yxRt$-S{a<#kL{uD
z1iO?nCob$2D<SC0PNA}+8#{}V#wXdE*Mh~Jy+QzgJ=h);Bzm%oC_?sPKSdAvDfW49
z$a%AEUxPs(_J#$(PP3n(pX?d-e2Q;;+05Hm1V6SHUCQxiTlangg8}R!%0ZoF|3#&k
zK=$Hvm<VF`QRY0DeSZZ8&#^bZ0uv$ZMY|vn%HBYUoAd0ysb?vS9Y~v2IQwtfE+W|a
zd<aCcf1|VY1@`&`I1|M_y8}9-*^lY9d6B(?qUabl!%C|j%dT;O;3aky8xnEsPv~<s
z@$4!(h$gVJ8vqj7?>obpB=%wo{gT=7$KXW@dp_kBQ`s+2axjhk;cBp?vxRh8%V1v|
zh0aViZwi*O*adT8KAUZP1Z6pFKK)@XvtJCg!qZ&#k}05h?BQLoo6k1V{#L;5pc-2t
z`(+BFuds8UhqkM116_Ey#!j_DO%dCN8or9z-PG=Oo!v^WuM+lTKR_wlk-lzP#=iU;
zw3M?uslZXeu5^XH8*CSfN-NoE-_wDliv9FcK&#nx_o3}3dkuZ};ubrJ*7-KO<}}pQ
zut(`e$Q|~_l-sXmPp!se>e%5FwcKTAEd^H3{&p5TyvP3BfcZACO}%jRK0A(%{}0%2
z*8^*0Cy?qU_AGivn%OPiQW~d)&7q}fWoMT_u!HTt4+cBg5rF_*?AOLH*v+=<hMFGs
zdAg$B%bwT`S|59YvR?h{82W(106S|t%n!0fKLHzJH>5*gm>pXKmJxQ#&#*Ac-b9@n
z57|lOSiCXzr9!Y+$Jx0TFpCMc!$uG%*?&`7W{Ms4J$N3mKf#%4&SSP?G+3UnXELzP
z)9fZ+Xgk8W^8~<_bNDuVvg7np^kC0f_%&QR%5iuBx*a&}GeA4Wu@_*_k@N6-usCtP
zx(RTcqx~56oUNQtdXb#q=qZeL;pDG@gezy+2qfG%zDt0e<a|ckmOJMQDv5Y-4o|{0
zPtNb981&+lHbC1cPO%=&cyqp^^QsT$$`a5{bH1g6`5DeU+O>Q+Vk+PHaa5G2^5=Z#
zgt-K8tedvN?paRIx6mEP`J@1|590j!0R)3NDbIlC9Ouw1u!L}e*1$w4$C?drp7WFz
zgJB%$Pr$-CqyK#}fm1{~Oe80WdOR+02B?WGijzn^bkUr}+aPd}Q$%+XVmNo{*^K4%
zSQ~&|;;f-CI*zlx7TV%DzO<(#aQbJ%r$o++j{uT5_DG@3N#^{Mgju9;x|Oh$%Gpo_
z&NR-h?T}07EUSl>49*!ksAh81B7iK;&;rP1b7oL^HHQ;S)4j}@Ny+tGPR$Am2=X`|
zzKqd)j>~IsxPasTH3kbg8>u7c3a8~E%wOevM-SIE4n7NrM~##A0D~o*LRTm)<pc*}
zu#6Kbg+MvyWe12?aJJqCc7wB!`c^7A?Q|fi;{1CCa@CyI%OG%*b1j&<R&Q}wZ@|Ud
zoYUuFqJ}d@-J^Fn-&4zfE$4-CfI7~F3efIy6mjsoo)Zy_MYzZLn4XFT&a!V{;y&j%
zm3JO+UNQnSa>PPRsflC%7|NPCLv)e4g;PX_{Z@|KJD|03j{ZUKzjn@Unsx_g1)U!|
zIf`OPba9fX!L^%{^8zG#INee>+{>AH3TpZ|UvC7hpYsdtj{}^HE11(DXW3H#L!9X-
zXc^}0phMvZ=g);uHp&S<3=0oAbEFU$<9L4!mT}HrDU?|!IB(L&HzqmT=}0}r*)t6_
zk2nVE%z4alcn@};aAGJUIL+C!9)m}?Zykq#Eq6m91njtfPr*ZbZeJ=)9OZs>3U(d1
zc2ui6#x+C(IC5`%2u>&N5?|Oo&i(W=0B5d_Iw($9xksrU;KI!h0P4zpfnM!y+%}5h
zPjYig0o=K9R4Vh}j?o|1llzPvfEV{$N|T@B-ZEnGy}2vnVcv(!DTerI?zTQ)XSl6B
zaK@K=WfIHf$2HNR#h?3e7?cHYzk34gEZ3SxT|a@`k!q+3;$Ha*Aefs;T|eizIkfkN
zaNBb+i%@Q31+eqn`_E#5!np5*!i#Wj_b;GDaG$pTL~;+(QThVcpAXtat}X)RW4KI8
zl*Mv=DIar*n=k?phyV2nT0D2eS_0Mt?)%jIlgQmP1^FcI&ROs+nY%3jf+<{2dYz?m
z6X-Ea<F?b((z!>e5hH^;@;g{Exed!Or!20+?@*e}ohO2p9PZn`V7bgy?uF`H?$SWW
z<#E#+p*o+ti27^_xEUuYDO|`s*8}1e?hI;Py~>@x4%)79xBU;E7ICXvptP8~djgiO
zbGJ~wx`g{*AW_QwBM|~++<FZ-%eksXD6QZQv;w=qJv$R}mE83o!tE;Vibf1pa|><Y
z%uQ|@AK(^uMhm_FZgW4P*GdgH#U6I=a34~{R?FQz27`6npD9;xmwSRfA6U<ITMF7e
zZt6C0HgKPrjTzqOhW`TW0ahJYBiEIR+D+U83@k!3cmF>SXyH2Sg27hqcN^hv8@DV2
zlW6Duion1+r-N&tGe{?Q1Lae@xDT$tQa87@0jxdT7U~!6<$67Vhkaa=1z10KO&3@O
zxcip?8{}qFetwAi&w2<9b8BeNAK}V&fn}8Y7HvrnxnURJ;TSi8w$O2IFkRo9;J!)M
z%B+*z`BeCr;;x~*<|FQl)b9G2Yg>p}JmHoUKz^FLi%J$pcv*b_w!9KLu-frN2jG)E
zZ#oDpM|ow=z#Mo(3QYSL&yV(eN8Y{90GxP#&~AC0S3%i6XI@Sw#82?T=|$jX<t^&M
zEKc%#CO~xOouQnV2hVFU1U-5ERP*)X&7sip6tCYC65hO%!vH=!*Mm@VnpaOD*BM?S
zU2XT}&7}y)k0+r3%%8X8XDAEcb#%bPv%GZlip>e+h5rOBh&N0*v0$F{tuJ8r9Pc}d
zy+e4vybmmtCr^Xmd7dA|-eJ6PN=AqCSd?0e;Jw%eS|sm#N=9Gct)WX4QM?c80HS#Z
z_rdLpJYP3xiQ%22w$WIgTm*kF@tD^j5XU=2eL?ZO;VO8Tz{|Ei4W)^^jg;j~;w|=q
z?qr?~ZCfck{~uvDmG|LtC{5#aw}B;{=k^Z#&fq1CLw6?6g$A>DJZeqL=834{oWt9)
z6_zgZ2IpeFxxD%Go6F<Hyac&?-b}jIS-`tNy;+64y-TgIbcLs(M8Z{`pbiq(cpLUY
zX%UY>8*(x4H79s@o##Pci!0&Hr7BP<FMyJ>WxVHJ#b7yaGu6y0c!vKTJYG3rl{|hj
z#H)B#x{_4Qvrua0Chx*aP<@N1dlz!Ic|K<9TCL&ne+17RUc+1vYk6M7m~S0#_S@jO
z%X6ZPd_8Z9ItuRb-n#&n2A+|s_xE}Keu8N~;Ke?RNi^~{>ET)vk3s)lrkVHY1Bkcq
zs_Bb}t-Qs#u+YY<Spn7UyqsVxYzOa6gaXz%oxF=2@O1HBTm+tO-V=(tdw4(4Ilq_Z
z*#N%>cr#KkILPz;?;Xdhq?H}!t(^z+BRqFXxQz1tPJ;MD-Ysf78{@I5Q*4~~9A!u+
zcwThGoaDvR(RPX#{R8Yh;<Y>mus-Ig@EV@;g!eD?+f4I1zXZ<_{;!nlv*i~r#4POi
z^&tTE{K{6SIm$mubpZ#yFCCAL@g1rA#*uGN_YR!+K9p%b&R@|Cnlpc)8Cp*88!0K`
z!oN!88(03jbf9tLpNNCoC$0QwS}%A0FO+lh;P0e^rzhW=`nA3IhPR>Z6#u?0B)s{z
zX`}JsceKLNX@2A_$erQuFoNdG&q>03{rEO?71^Kv1wGpV{4Z!qXZcI`0D=6)bfgaA
z|4LhMFh6M+*g3v6XdQ?l{53SEQ2tJe=+E;HQDZ|GpHDCPaQ+*#ZAI`)DdLOd$6tr}
z3;fY;U{U-F-@wCYei+3(7x^hv){Ei0Ed@&~|5^G$T;l&prGq&BFZ6<s=kwly-2{F-
zHNhnEpR!WrF^PZsMR<|S|A@W~ox)#y5%Q^g`&6t~8b6V8gz0>x4qjyNLn!&4$>+QS
zrCEGODpzIm<<w7~!|!?vw9EVs3Tbos`|pC5$LIeAOZj}?D-bW>fBzReEaYFN4udQF
zv=A!eU*&ID1>!Zn`(}V5{*Tl_QOr-Ep26$<U*3W468_~n&`SC8Xkcah!?rL{&KJB6
zH5L4TPXVg<A}6?A&5z;1;7$JX)WdU&Ul<0t+k82Nv^D%$wxHeNw^Dk!mVZD=W&ApR
z1$~a_F5lG-JoWroYV^Lx-`xdE4g7Z~(R!c%2Icx5@Q+YWbtC^p9dtMGKY1N$n)&f-
zL2KdfrmdlsKSsBg+W1FOA=l3LqZ)Y!e;?)8JNdKdl+?xd55qEd^EF4QYo~|5mQK38
zeAj+x>*JpZg6@8PrynE+_{)EU7lVBJ8n6uUW4;7!n7^N{$d2&mSHi?7KZLx0$iMJ8
zERFHqeueIF{tMy2CiqrQ%y*K1om!-)_;R|g|A@cJ0)fZ;N{R@qPxy-{uQ1L3W;e7Q
z5#&%3%T}<p0KiW0HT6x~3r<o^_NbtWN@xxO{`c_WnBZ9oEF1;%bf7s2w9fGGxZv&;
zD0LQmPd#NP1P`u&<|44A6TPdzk*<!p37XPj{-nV9E(YDLg5~t$^bpwo2%@JTuM!eo
z0&O0!Q-TGaaLrp#uolkv2&7ayJ1uafXZwtxWeaG&0<9~={RESASn?N)eF9p5VEGnc
zX9d}AuoNhG`2aYB1ho_{2MfNV|Lk{8@B&RRL||1=?m1MzG{N9`f!%%ZgbD7`g`seP
zj85hef_49;Qv}&m;kY0OSO5?ucoYZS(Slbg1i2{qf|Bzwf>ZRs#tKHL@#>Ob-@jmq
z6Fe+|rFenUOmHR%_7p=rS+Fn#v=l+LwGA*;aEP|xG{L98ftW5Rr6(>!;69DD%oKbU
z0a}*etBnBJf+aICm?PNnGu*x`=*fc8TtRgR1o8yU{{zSu<i%qy1%fdSK%t<NQUF&3
z%enC4s^A9-G_MK5D2-Aih+)z5S1kC(6U6I+I;y3V2!5g{r&J)JlT?|&eK%<3f+uuJ
zsu1KGf!z><so+JWU~me$s|2;wU{ozwMm^Ox1x1v%xg|L88qD7oB+^g5MlkXRevfwq
zv%5j76%0@iTPIlYJH>x@1!G#MsTbT#0JtYG&|$hk@abom?|nhxIVgP~D5MNVqhPi>
z{B06k_l44C!Mif})FRN{0caIm_!4q$f~s3!X%~D-w@f+&CIRer3Z9z@fi6LA5*Dai
zFuD-59>D>mjjVHe1)(2<*e9@m0VetdGI|;Z1h3JPJ}8KL9-a;f4$zmDh6P6=AU`4)
zl4EM4f<+|oP~ce#+L&N}EG&%+stTZcLhw9wm`w@}UjUdAxKV!WkzhI9FnTQ55dgU-
zg2rW-u60^4dLQPG2>CuxYAf^@gf=^2938^#h4oAb9u<ZOF*OHaNd>?$p_+^NItn{)
z12_q%A7g=z3%_^)G-qMe31BCLO^YDsBD^^l23>_I8==fic!DC4lR`7qIoyTS=fUD(
z6&|42)KmBYy<5G6mY?C2k1+NWu+ze0wD+D7z7~i<U!iLU{Pq*JP}$I5*hfc#0HNJF
z_<L5k6sPGqfx>bzCJ`jOP1VO>;qFNoJSX&_+Cqr%P$!gy3jd-F=De_jLh&%6HSu+5
z3m2BsSuaAUp`=};F!304Ul1k)gC|OOdJJl!h5LR0xG22&Bb<p5CQ_GftZ*)McwQ3L
z(YY#4xcpmai5If`p(R21=n8yF6be3tT$1pT2;L_PKXZW26ydAiLLgNrwo+`FCbWGX
zXu8l%2HhFL?gfy~6n0b5J4+Zx>Bwy12vx9hgjqCrS$NMLa=AiQAGGBOKN<tb7w%mR
zT7gg~glmPu3zWLMB7ABXs;>%@w*$K-9HKs_B4K1A3>6E*8fZtoE=)N9ze|L3=qz6<
zOnwV~mkE#1)?Y4M5(!#`@WCONxFJlS(^;kPk9FXz5<dA2EY-r!&G7K1u#6J;w}eu<
zY<XLlLz&?k;Y;+|za#vZ&Iz@`hBVl%6B^mDa979-psv+=;d2yH-xJo;=GP$nk+PHb
zg~#dl@j&Q*40aoZPxb>e33pLxrCIp?oA9Yc_&J5dtwNV&FxV#ar*d?=u&fV*9m3MT
z0Xl_GQ2^E@+~5h<x`hY6gX$jP${lc~SGcmA&Yyk4w?Bt`zmWY3CNm)HD*(@+u=-yN
z4hdV1LCvu6ANmIoBf<cCOlDMAs0B7IJVxh?3E>OWeK9Fi@h~_g6z0RVN5adrYLA7F
zJmJ$5Ap%Xj;)Ji<0XQP6qdRW4qJTumS?xq$Qw_*o6i&PCQBhC^3_6Go#=!4mBBy@*
zeH=w!QG(b>WJBqN<D$Kk_;eP%^#QOGq6KECaS`qM6ymNTMl=N6MCX48%Sn-aDS*2u
zY6M<*h)l6C<SDvw74!5GmAwnvDXZu;dYgKSe6&D)MCvrScv@6c4y9*A4JDxYibCmR
z;3q1i^tivM>Nl_ih$dn|J1g?04yQm-N(JT=BvRgimS9mBHL0Bwaj3=|BAR{?Sg0tU
zelzDqFP;GwCVG>0t#FZb-F?6aQ8aZ(MT$<)S8Xqda_J`!C3^V|uxL>+ZB!RU9;FzJ
z5%K5^A1hi%y<e9^=jk;XC$gt4G+uP-6|7T&XsQ@G6GbId&q@;cHN)RzQAigCQ$&Z4
z!>3fy0R_a<L?$c6W9gz&Dwt%5{x}R`rfAhy5X=%iJqcR2DA)p!Bf9+@>|Pc*(*^Kc
z(GNv1m?zr*4s_>>X3=T3K=dwsOt(<9=R?fpiYSA6gRY8%AHnW5QBDbT7KxTo$W$zP
z=P1B+5v!2mzY@`UC-_||ilcK%naCy!O3Ov->F-n_nxZb38=}G-XsZ+j9)z|k(WR}B
zs}^1U7OveCEu(|jEs?PiEVo79(Y1#fQI!{bsuQiExA$Gq>A%2PFEUpHyC+&gCH)4G
z@En~#?~A^qYswEqp){FB(a%4_V3TNwx~Q8)pGLxq7SRiGu(XPNX!C0mt)>UBUDQHL
z+94W#3Y?vy)SoceC7O2@0^K5JKGvc~^n(PnUQzx>aIH^d(1O-4iun`EJRs6J(*LR&
z6uHab)DQ{>&^9b8rl5aB<Q4?^QPDH>Rg{OK@Q3heO!O`V_TwVchghx&(TjB4pA<c$
zyP{K~PHHNBBr3^*!N(#AUD10Y8lt!1wCJ-$SU4h9Pr<IO*mEvucH*vBD6`s&6RB2r
zRJ@qF4jjY-^cp=T-uw{2Q9P>^z)74|2#Mq3x=Ubj7TZ&z>4bPMWm8?mT|0oeikHw&
z)=j*Q2bPoK@&8&V#f@}D&qI8e1%Exozhz?*Ug9k}fK%esZBXrP6~Ai-qK~*q2^UX`
zZ!Uw2XT*ce(B>;Hd;lIlu`T64{l$s?zyid2HVmE>yU}%xK(Qxvas`R?ZD0u&U!`s1
zocQzkU<ncHY1axB+ebm?dGXunup1`MUyHefi!<nZbP-~!%^z5yNb&BS&~`ywr3W!e
z{2~2cn`p6&$_W?6vuL-D5r0li!?EHwHUPUM-bn|OIB^>#8RNz8+rm<Uct5$8D3;L;
zqa?8xCHIrXA#Y$XMJ)OfUZjd&iGvqu;#sf5P`WtYO1%?V;w6V+DO>y{<uh``Z+r=#
zE{mVO1;Jc#^i8PA6YDDh^2OJv)LtO|+X4O-it)``JZj?hf1vHE_#FM_u8GU(99Se?
zwhf?IJR=7du8VibAYLLK?}g4%@oZ{VDid$>v4U7G{&g1&R)`OD!HXN>?Vd1EDW07P
zhpWV|aUobOMu`BAn)t8hA$Uu?h#FRIi*spXtr54<YyXb;vJ2#D#g0_ktP=-N{qC-~
zhVBN{i^m>7%RTYTIM5oz(E^Cy7h6K-;rV+Y-a*yvMsYtC?wiCnY4>RscW;M$i#Uru
z3g0SDqxhmtyo{pQc5yBBk93Hu%AmAUyoh$KF7cyPm|C~^S?WIQ5zokiiC*zf|3GJ-
zc+Umc?H5<J!utWS59Q?s#Y?)VDQ`&p=rnW>i;c9kjEHwpK5<lhq88XgapPmC858?%
z2N)NxVt_UwZubK=DfUc*(kXF%0tO$6GZw(@$KuFo=zb!uqTJ}Tc;|c=JR*sq+^DT&
z_&zW@3C!VzCt3P6FzZptuQqVeK{8Hd;$xCw4kqI$v7-!?lVsK-3?7$kDuW4U$)8Vy
zb^=Xw5Ok5$(UHPc^4%bSn`9GRuRJL!u>iPBJZKN}kW}vn%~O)l4a`eY#DSJml1e&;
zdP^q4q0GlBN%<d4oR$<&p81UAkJ(`Ll~m<n&`)BdQ<lG^gD#x}N*-Usss~9*;~^L<
z$)($&=Ol)gU@%0okdm9Bl5uJ>IWPJ2ODsZ|WS0no;gX~D6_yBzdk!o_N}k;e+6BqO
zllZ$vNvy5cfJRGt7sAtvlBC&iF-BsdV_mG|>#M*nNsiKgc!-nyMOl@2$;)e?CP7j`
z`Ikh=MM^{@N%E-rk}L^sfk2An7mC(XC5}~4ohIq6hui6r^%e+ZNYX`6ohgZ@&zWRN
zimfLhkuCY1V)z`%db);jS+bsz?YWXHs%_*+R?!(TU-Hax*e#H-rXgP_@lJ)@6-mG)
zuw0ew{Q=spNo?rMRU|q6U;acg>ubnem#kj})g_Wu=U~26^8Q^2lu2GD56dMCr4@n|
zlF4c)y&=(2A6KR1$7ArKO7cItXjm<I?G&83DY2$thPNa&R1vx@`IYY9)kqEx0Njyy
zyoVXqN{-k-X`LjD(x7)Gxh=rzB{GV-?@9ioBYA_QCLCJsOFAlnJ&^1vq4=*+vWN;|
zO%eq~-OZA5%0;zEp7{ZGTO|uA>TZ)nUxHw}<R1!jJ0#zCL7-Ezo$91rl1=YJpj(ne
z%iSY!riSKT$wCSP`y{(Rz|8t33#hy_AX#?+gM*US4+9KI);>jFZ5x)PRKfibiTete
z7?tc>4De9$$#rNOlPsHo`Ho8(=*Ko8$>_%5q-2a-o02S|;Ovpa@jk#~N%JKP9+Cb@
zDGOVvaT8p#lOFJZd3)*Wl)O4B{rV9&9i+W8VBwfFj@s?5j?&L(;pgQfeVqc6<I?>|
z3e9nrHV=X4g!Hd_@Y_Y2MU!!rDiR>!CXL()ODCn@so<Ks^x|ib^N`v^fYVdzN_&x)
zbT6eGPf52>znZtyoiY$U(&CNKa$2fc0l72Mos=f?wMu8x5y(%v`YlNKOCSFM_XDJF
z<v`6@=^y7n3zWK3Q7}mQ^P8A`uyi&>-RGpSyTKVE9j6pesB|@XcwTB=2i;-Prq$pK
zmyY{DXN2_VT40gVU4<}sLHYw-<cX4U>3kn8wR&cPcv1S%C@jTDeQ4W?mHtXa#Y@u9
zX-VUx&+mp{ywvppbSFqZ`5LrD=`X<mNz&yec#$mKCV*Uu^lCOZQ>6zCu$v~e{Rpbl
zrE$*Ck|FIo4}nbS&kG@tCH>?tn9r8lSeIcmN6P&fi+EYuOnvjY(*Nawm?vGJ1Z%!D
ze-KIwq=DCf6-u9_sQZdE)DLo3rDe3IT$3hH)LkT9Tmdb`(j}LGU6*#e3uPtJTs4%H
zO3RIyV3~9ag@NVLZb~UtNS_I!#lIoFkqHx(QvY6HRnix9;Hj2oQ8ai{x<CwVx1@YJ
z$laC>{(*I_k?wDVGk2sFXw#ZgD{ZGIwN5&A4d(Ak?^E+?y;P=$+&$?AYAJ1y{z;vd
z_oX`rVYf-@M<H#qbXFUE+^9u*WE}FX(rm9Iz6-5S9|cRNw2hh*yQJ0BHrg#cR|<|E
zX(^qPd!@2k(E6lnC^geBo$(e}2BatG;?JN|@-aAvq}vB!c34_Uq40>b`VD|lX+}8y
zAP=SOl*1j99`u2q<I+=<$(oS%{MXDZEwfTyd`emq2A)UK)AM2Cv2^k4@cxN(@(bvm
zmOh>d+7X%TDoohQ9-M}5JDGhA2JL0feFW^NY={j32id{J5I80qF+!)KtegkTNp^_h
zk>j$DXq$4DC5A!Zge*M*EH1LMEGo#l$~Mq3!%fz34?HJjp34B-WwsPWddMzQ*~3%z
z3jMgfWc|)idP=q}55QaY5!Ky&WG^^@<+LoFw$(GTjlV+NS9X<Nn|`t)Dj)dEexqP8
zK;};;)U&dG=?hkYve9qomQIlDol_VMmc91|oH{4lLidS6WLxRwA1WK7l|3(8Md|G@
z*-m<<!(~y?Sf>aXFCCnbGTD5{U6B1tEss&McjsX+TE?A&1-d9(NV{Z=jBx?xV`ZD1
zA$~~~^ewPBnZEA7TLQ9sjxdoRtN9G_iLy7`A(13&Itr!9G6S9HQ)EGOs!Nr<^Dk&=
zvOa2?PM4)kKp;aVr|U?WvUezK%#uCV3oKi<F%h&J8IST>mt{MmU@%u^`y#aD$@nXw
zrBD{+hgn;%$X5Id6IW#g6#&;{KPAKcBH0qE$P~+(Z$RmFS=9!pDUp5A2wJHu%L3QR
zWWC<7R4!xWVX#8B+XV3&GA@0gtWxGz4--`~7X1RNWxvv0=bJJaCFgI+YF~oDZP`92
zSg5hen&|&$-I1+-8iKX5`S(DqlT}hG>#l4&r9tXt83HWOJ=x_&pf$)+>EXC9n|TDZ
z2Qu9VoN1IDZ^mGg?8RYBv|0A~pBQYB?c0pOR+&Z$@iy81g8=QaAv#5N$o5h_sZ(bC
zwhpjMc8PY&ZrK}iV4_DhNmqAzWixlc#Xi}4OW=OL>@zC949NbXqv@b*HEmNvvWX@r
z9hUt;uhbFQ!;26fmD#p~_D~j8h)ImeR?rD(T=o;)%bbvHr|of4c8t!sQ?ehdXCd)O
zX1fyTW7*NQaQKPLWh1a@*``%sJtF_p4BfW!Wj(;`<cc$(*~=eLZSSaj73JC;<SEqL
zbxb~&58x=*9l{^YNq+P&XvgIln_$;jzBC=!33=TWU@r10`eu!*{MRiM5V*+~&{_DT
z+@C^2cez&|Fb}yK<qSOKt&}YDl6$s8=_&bV6zO@(r^E5r@{vEHy8CJQ9UpjjM!umQ
ze-U4K@D1qnlW+V20{-$%bl4A&M?3+`S$XLUums9moB@L5>n8sDjDq~1FW}TU`R|uu
zK16Pz8d<2kF&tim%kBS!nh5ze1>_^;ck-e8g1oW`cBAB}YRn>99_0X*i}IsXjE|Ae
z;lp68oI&}tOY+bo5QvkXp-ghT{4~Yv33B{@4m@e{-e&qYB1!VKbf!&~@1l2Giu~3Y
zs7aN36oMyB9(oA0ba|jZlxE1+(wAK_<<ZoGmnE<F1jv@JrJX-VzEcUeFUuV%DUvI%
zeFo<9<hJ_(^5s*r;6;Ianp&m`<?qu+2Cm5GEy7Y-ugd-DI?OfsR_cZ>lK&J4OU3dQ
z8MIxO54pi$iTo@2i<ZiJZb70<UR4IHT>c?-bydg@(KkeI$PY|FOQqbc1(vGhv2;eO
zmM2mD`lj5P0?u3VV-s-gwtVqC&}!r@De(S|RsKU1CR!_B!iS|g`QN{Rcvn8_YY^+@
z&h)I@lkb*6O@o|GJtp_%|IUEG1NpVb5NMRIser*I`RhX%Y?ddS1xt(k++i4OmA^{e
z8Ex{DOCjDa|55`-JLKhGW1gMz)%1CdF1eN60~6iygG^}aksqe8rdMuDulqiE^QUm8
zU;g+8Xan+RKZ1!tdCb26L-HlB0SwC}I8@FVkw0hy7?lqNW7QtYH`5a{Cf~LPOENBR
z*#%`2^5%AEnUp((!nG-RSOvr%$tSGT{ry;eFdmkk$Tzh^&9r>J8iPj^^&eo+R`K!k
zkg!u6pjHukMH2(ysABbU00+fiX`neNo_hjI#}(sL_;yzC)fhaXSVpa|E{Y^d$Ga+O
zmIHHByxNKho>VX+AmFZ8qp-q+hr;$ccsvzvp9kip7_SHMl;RrFsB^p(In?RtqsVfA
z!>1Kq`$0RS@S}TTzKY1VG3cjQmII~!is8Kg0g6@Ba&=arkA$*7#UBf>BteS!K9~<y
z3{eDePN8@jScoFwD{6=jRb<e;$MXuuna~!dc={FC4Oa|MjV(g)EPZn)QsG$zr56<O
z)Rq{f_=}>VXoc7g*hPhV0>on!3sa#qR*`fY*d;}7Gq5<tmeWuculR%VO9_hi{IF_?
zie1zakfiWN-P<}RS&>P}#T3P>)JK`Bs4aqgn&O*TFqp1*q6e0t=wd@YQ}Ht$+_Dr0
zPXNnSJWs(<j>3l$VwV-m+aR8+*!U6z@)RvB4CX5m%YYRqK1c;tsPGiP?iEG15UQ^#
zmi2&Uy{4$9oNAFmJ`VX}#U4NCzOGn8J?JHhtD&HkD&G1Sv@*pT%OO#&_%jFc6^j2o
z2keI8{TBRvDiuFuV4bQI18=}YwIYrh5pOCYMzBt|6t$gTxvltp4V2X=UT?xA?kGO@
zgFvlSkwC3+b&6qENZeH%&H!t@!bGpwdkWjFz#0@P`i8}Q#YZ~;9w^clL$FbiN=Jew
zMa>Q@LbF0xg25Jr>o34s6@llVtW6Q{I-F@&*m0q(OEG-_EZvH|kznajEDD3!UWN6*
zD9}EI<0yFg6+O)m98kC{hweeeQYtMDDGU@$4lB-{g8Ya=>J7nB#n&5vJygu1*Wj4q
z1{(`Bu9!U^D>I?kz7*4*RGgr5(Uf8gb%!~R6e*{n`my4G8G}z0lP;Lcw4%z|1s9Jf
zt0)m*tE>}1&`!yv=ht4jgc=NvDnFy$+CiD>0EuJD1rCsRRIa2-gOjr8GblZ-{3!##
zSvj&8v=hqt9`N2p`SC08-c?yh&F*f>`}C>SlgeZxEVwIwq3Fazx!l$Y2~Xv_U&0G7
z<=!t~>6B6(52ClSECKR9O3sUrKdt=ab$~NUg$>riSNR?_UivBT`NIo;C6kW%0m}c;
znfk0!dly)s@{3Ktf|MoCK})c*<{zj&r|gb{c!=_=xfl#p&P<z)=kL6-f`ZU6<rzBW
zgex@{VLn0`(FiP3nMwJC3(B|X;!l*)hEn~}%KNkhUsRrd8550BKA=QTtn#=!>|RpV
z(#@neW#>WA;*}X~P@SOknub84a{n<*H%a-B+)h@WL}P+=PKxp|-H%FD&fE&!X-eKG
zK)Uh|CL}VHYo3RErt%R5p;^i_`es$Oay=!TbCf6fpj}qVH^IYP<!f~2%2Pf?-Szp(
zZa4T;po}#`b)oXfBnGc2TfDJ`SCxNJICM?f76K2gMar&z$QLWWa06PZ^y~murnIN0
zqFfn8UoEUq*1ZYyH<TVBFj1*|Uj>#bWwHYVs+FB*z;aXBLaDb~${Un$xvhL<0a$93
zoAcr59p#E8Fj%WBm<xeA<<d(SysNCFlzF{X+4=&A_mnF)VQLLZ7y6{qeI<*MA`g^K
z1E4i3J-)zXnv`}&ptM<8=mQfi%1zC1rd63nk!_pug-_vOyYiJS(A}XF{0q5G<<U71
z=u*lbLcCkKe-E%8r9(Jo)~g&+!(N}#s;`2!e&t(VLw-Pcl5!1$$|IB=7*Ynm0yV?R
zgS2gpD8&KLJ*ph21NKlE^A6<3l=9!<#kle!HL*=7cTsYEQW-@oQ_8tvV0ol0qsHaO
zO6g*#exm%7K6W#$e0mR*9Z|h)tp;kV`t@bV+o{gcdEH)BL@C{)s^(%$%|WH5L(ehQ
z8`MeRs5<d4{B}~=UWe}Es`d0*a8@m&a>)tRf`5Rys16;0xT|VgGsN9g!xRXeRBgQr
zad*|zJ}~5=TGkEoo~m81Q~c+pTK!*fPPLG>EpOH9l#=yPg;zoTw91i=lV?;;djWh^
zscE43saDWg++Q_*8{z?~r@ja6tSXgik%6l3sF^cJ6+!JU!K&^7VCPi(7sB5VRV{6r
zp{jBb44qfy?5BUh8>afr3%-S`jw`Ti5vm<@!j4qUqqdz3syuo%N2!9NAs?;UHvlYA
zwdXwuB&ptW#YB@;HyU9nT@^-Ehzym@6gV?g?f-z~vMPkqW4Wp&)RmQ|Qrf{niOLcR
z^JS_fd+GgGt_o#?r$UuWzwR5V)$|9dRK0T_x~o)8-$9~U^$*3;H&tIzKypjvM;Wvl
zRm~P~-ch|5g0-ww@#v*kr`kxZ1b0>2pTTxluPUJLiZrN}hQgWqs-b+W+5^?|7cjF%
zRev4Ctxc-esEp8}ilFyytICN!p3tUReG=N*RT)%I?oh3ChkU1sbs4(5R5RTm(4*qe
zzTB&FrBqa(YC$w;{VHz_1_xBeQn)>+l2F=oNEJ_K>0#Au`XP;|^0Pr3RsBJC3m)!L
z9icbDm}-m~<;GS05;!%X;s;<!CspBVfIU*ZNjC-_tGw3%JW)L}6OK-+TKb{ph&q|>
z!P%-Gd<dGo`b;t0KB{)6kk&zMcNlh$saGEZa8$4Lx);TMrnDW>uIkFQUNfU#wr+g_
zC7$XFWl-X!zWNiyPN{cLVcuK4yA{Ak?XeAx`Ko<{P~xZliQ)-=^)&s)0@P3c4cb}t
ztQ+t)P<@Bq_UF_asH_>HUbz%3q3XU*Fc_}>K?t)E>Kltdi&WQA<88G1v9$^YFRIu4
z0rN5H4Mkv$Q*%ea8n3=h5mSOXlM-Ob>KMvVr>K`v+j6S<h8S3edPOB>o2lNp4?bn7
zStp?Evid#B<>#tLsL?S`9rP5ie6=DB1`E`lbXF-;FQUKkHFbFuRji8CORobhR$qz1
z46myvDBoYAF4zzGQgsP^UZg_JRe|M(dKN{=m1=Dq3|6V<(xr=P^<%0U+*G?z3bsbw
zL1F40^?NhHQmZ~jK}NkglnrI~)W3FON)76llYlj<cMIp>>1$H2q(nfodKXpQThuAl
zFwv@Z-G+&_sf+1-*{6=n#bCesxl*tUs1s>2gX%lf!#SjOkbpL<en=_f5p^d8rlaa5
z6x2La3uy7j)cSO=jH{Qfg53#q@<-4)sZPcL$U0|A-9shJN9s&UKtEQmSO61G)W1?s
z^R(KBx^j<b5)WZzZ8c#N7_`$YpijNoYZmT-wxb$Pd$2fY-hKeP$26}|wb4<NOc_ll
zO$MDsk84V{gXXMZ(cQEYngnW6chO|GW4WxZnleA=cGEmZCQfSn4q?<&^F7rry);W`
zA3mk|jjGt*nr2EB_-ML2K|8H!PX+Ca#(O!G`f5(hgin4NBOUn8Y7SDs6sTGH4nUB`
zmkvk4nvN-~#W{_Ns?Q;s)!FbO)T(hxgSPV;6TN4{G+Wm}X}IP^76v0U|4?snq((!R
ztuAQZ8G!C6&Es&WiPqet_hgJ_JGH0AYAS*OE@?6;MHr{~vL3qQHLWRNNkIPqlqGBK
zQL9mkW=aK?RLvUFlBThyia<=)?4kN^hUPRCJu)>Bo8V%W#);09*&6>W{PA)${`9-J
ztO?RWO|FI^$8zOq9xjK8d`->oScC%2+u;CLG*+r66=`IY%PiL1q}SGUO>-o4mT1m|
zL!eZnDhF1k*<ekEM7d^e3v^d#&TIkkhGu9rK&8foj&W6*l?{-u*1SOB@lDO<WdOG{
zU8ezVYbLj0)oL}~m*GsEW+k0^?`lp^`mtVf=qc#Dr<p<5Rv&2k>HO8GnN7|#X;#u%
zrCD=0n4Z5D&6;_bQ>#WUgG8I=6!ny}Yj!BH79E-z#7J{GHI7#Rx->ryVV%1*aZkfU
zk7i#tSb8<DybHNLjl=609Mmk(!kH1xC;y$&HJd24_)zmr320-Q_<9J8YhIz3?u5qX
z6KaQ_)F^)jaY}QZHrYp-bJRQVShMGASbC!Qy#a&M8XcXu?6ezx1+do!g~Q-cZ4xy{
zIA~i|L*STp3)NvAwNeWEoV2!d>+iTW)E5(U*0#~+bwWFvvb-+Z|9u9`ReRtXT?cd5
zrqeskLpv`9f}Yx!sO!v2JM=feDQ!R!lzMAFpse^AZMg_`eYOA6>();@{3F!(Yd@P0
z@c?b^aSWc-a{q?g!P++{sc=qv=n%XJ(TeCG5~{7Ii(}`t8d`)f?YDG^&Kj<LhEnDc
z+KsP4B2xR)JCL}b-5m;TQQFD?%r{zl^(6=<YS(=XmL#n+Ws;M%T_l&HO{a?nsoEFZ
zpe;>%CIK@{*KRC_T!uFEHdr#XA1r~}S=tjj0J62cKLF%tOB>+mWvezj3}~))_5@h-
zw1?=IkgxsyIJ6aLzcfQzp*De1&sVeqUKqTp)zc@PuW3CfwOORi{1}#swHMRj+I8&?
z+TKgFySGDUsrFC0ELEocoZ9)ywFC55uFxJi0-ZOsHFO}T)LOqT0j$zqqn)u@s~?Bp
zP3>qPW`9eYpo25FweL|QLXCF02D<NPquzp}wc3JQn6K0RP7nND?GS}C^;$LuEcdkC
ze?zW88%Y7zeeH&4!SX=6ky1#F+O`ug)TFI!21~P6Vf_$ji*`N*dac?NDhIV`v#9N)
zU0X*5vkvWSYU=3Jep!maF6|Xcv~+9dT?FXS{=N?az1nk>JnhqVsetusA3Ol(fOhy2
zSO&FUZh_q)?Y2gMVQmj(kVmwejSv{sGG|)h@I&o&A6OdGhETuPxb|bZ_co!OYy<10
zw)QFnA8QxWN&bm;9uE_p)?T3))J`X&?}ypz+^9e8sLpjZ1|4*-41(pD&X9_kIqK>h
zq0C8lo$4dUb>@Ybr?W2aTL_%c)iA00;G&zc6%wwxeVbv)O?R2TcXCoUpX%1`Iv$l0
zJ#?1eAmOQ-(FQNPbgew7Ii(AtD)ebx8CBHJ=%hg~@2iU!L%>g`qo!|v9WNSQ1nA}#
zK>VzZ`631bbyYjT5~OoGPub64T{Gpi&gmRiLR*M#!9O5|>VBu9<$0Z+3Ke0xkBp#&
z>ssh68=>2#hSDfq7&Vqg>vqz<d{Jkj>qarUAo{LLtnT(WST5-{EXE|_bUY?F<8}Pa
zFrT1XYY&!0-Pqp%)+8N|a^=ao$?t%s=!|qJCRO+63oxIis~U%E>AJbELoh@42CZzS
z?hfVOvvjNOKzFvTf(M^+bP3xr!^^rhdYR_x4$wg?Pq&pWfaU9^!{Azh?%!(273wl~
z!rm2~J-z3zT6Ha(Vep!6kn$}>x>b}SDc0Hg!~N^JMV~^xME9#d%$Mp+^c9CPT`NWB
z<+_#`5U9|x>9l=AC#4qSO5N@N$W`g8=)!lkZvG$)-qfvSLEx4yvl1+~bq8O9-5Q;f
z2;h#+YSe<YR`&^|nd)?|2Vn57F7^Qg>viAHfwp_PSN3DDLAREYPWN>WslM_+H*+>X
zqpqCJ*G;->l<9BQouQm$i!SmP&{}nex8jf1p-ZO6zf-p<85X*9Xa51#t^11)tVb7O
zJqWZ{=Uff>KHXn*Oz+n{^&SKVbUZV(4eFLt25m_9l{Xw7)-6;*_lQnK8`P*S?h!a2
z>VkdY;h64oy16y3TiO7hCUlMz0Zi&P?T6fy?l|=wKGH3D9(Et=KCTDL6W#jHs1<Zt
zw~j7?9MMN6VANLcd;)gu^#0ixwAX9jgTbTv1=LRApm*+o{4xFV%TVg5Urf1qC;e0Z
z1MRr}eadt=>$RcKazg*brvNVc!Z$D_SAD@U=ycOhu7>zYy(7g`?t16HsU6TmKW`-_
z<Eamvi$8^z{+T@JKBXVo4?%Bz4s}8L==Uvz;A#EF4`Jer{xZ4dt2g%p^V2VTA1wZQ
z-%Jb!=#!G6`>cNL8JG{$|9BlBNZ+&_=7aU`<-y-``U`siLiEijO<U)L>i1HrAzU9#
zN4^OCM-)Ow>W9+d#RdKFN5G==nL@Bc>;3ED(?$KOAAmDP|HoIrV)b88L-!?pU?e!>
z^l4N(iPw+Qex9JWy@A0*y@is#N&3SQ3?}Ps-o}ci=y}w&VolZS=z?FG{$=WsO4sMj
z1(u<IiB>jKpQ?oyS^B>+VK7_&{7nev=ugwv{4VSNzKLn)>Q}4<$kU$-24}v0?j2Yv
z(0kCas!;DW540=##(WH3)q7Iz=$hU!3|flxnonS_*s33-9MW~YE!99u^o?{gy;Ogm
z;`uVYK@D2D{tFQ#D)e9P0d_;5NH<3+^>@pFRp|@qEK#jDQqA?I{!J+cZ|Ogz7vF9D
zRjLWp=(`dia7TZQ?xfc0mryTeo&Mn@z+JudYx?cf>$jYSiF^7V*5jAZp!Y8ZxUXML
z_ah$YU!~2UQUB)-m}t?5(m||MpXUinZTcN!aI{@7=>gWEZ+i`#o%*+^*xIFEu?w8t
z`uC~q(4#*#jwR{U*KCDPefkX)^Y-i4si^T{Kp#xe#-P53g1aGoTO2G6>kFtDKB8Yv
zq0gxPX|HqX3$5+%!NP<-@GF2x{ekx(Hl@Gl0_>4KlDf1X>wlxx{3rTkcX&3fFQdff
z5yN4sCfOPqhG5Rlu<cbCus3*Y1?{L|CY_-j4B2*=^f5ydWxN~>z0`8*WY|ne;^T%t
zqd;>uL|Cc0_JpDB5=LDNt&{|DHB3-<f}6p1CnQc9nhG&NcSAANCp-+JiSWtOFiCH8
zFT*&swVg6VGN8@d@b*Sn@-cY*3}vScEw5tmjA5QTfUlupHRSvZdg`6_H~c`I83Bgf
zWwc$KHLRe<lt4q14U`5ML>3H&7_LydB-GGx9^kwomVS8=hFCg^M;aDUi|z#j&j^1n
z8rH7^Eyf_B7e}li*bxG$27x^+r5O^aEShdG9fZLQLoM}VXBsv!FzYPCPb}(Q%r-FT
z4Vz<_MX$!ohQT3#T*K$Pz?x@heg>BE4U^RSSztI{3rmHDHB_#<Vt8{4EL}B}P~>yX
zu<S3mR%Dn_43=WU!Dqm7-M}$IONk*^0G3ii2?>-LnBT!(xnZtp){M{QR2UY`fZz>-
zQUJk9gAJwjs|>3~;eNH@)h0M|)9}>^V7ClspM#p)hOks%H3s%K0Cx<UXCPi{cxx%<
zRA<<F1a|Kl3ca4mVq2eH3wsX?oS&hx(XfqT$R>lMBRHB3Y${f?7*@IgYc;$Z1V7sh
zdv8N!yJ1ZVXdQ-WIx}|~?ot}6%dl(!cDfB;(BGrSkiQh`(rYNDl5U^j<6wyQ8{8hj
z(12l84X{DOLMx@uh72P=f_2!Sp@Zp&!7CoRM-8R)_k3umdluTp48j;#8aKR7JN1Mi
ziF)!T4GWy%%#>l-ZvamW{*+>vHjKMK_Yq?>of>V8y**e-J7akal-V1#)QNx8`0Fg#
zb1*XArb^r~W5+I-a5UO)0;`izPkYC4<18u$IUC>2fVLCHFCW36i!m@2G*{zls#Ccc
zpWX;(P8#2z3El3-zC954Fh)`e(bHH;9UWfAuU3Qel=1bG;Pf^=Pm!~a(Uuy(P8)@P
zQ!d2MSVsLy{zk7S&>dh5q$Yv0#&@HkCeU~?A07r7!{~~Cu<=VNSk4*4MxivsxSZ64
z8h`%^y3ZRgQ-(XtxVi}--1q}E0Y(^`J_U$08loX^!C3JC%A$;cl$wY(#^agzaLz@e
z>*r7tV_ZR9e6dEqG!QQt-KB6p&NzbsiFjjKDzF6Ok50f6jeDqLAjv2cU`djVBUQjs
zj4%BTxm07B*S;LKb>A>_Wf{#BmS!90zKr$BF+MjBzFanLyoteFV@nad&NCLup(NiJ
zNR_Mt;|u>nNulv2O1)n(t}lR=tH!A1FmTP-#DJSc##gQYD>jC8f_B}wXb@P5kx8*;
zsc|*^k;{xmE4?ntjhB`ItuSt)FI?O(u9CxirSZB2Q>ilMya+F<jm<wn{-&|r2!pqb
zH>iMq+i0(bwi@G0A7Jo~aU1<1YK>p`LQ9>o{S(mc8l8I~S8ueZm&QHg@;Vr5Fj`_E
z&}cmCY6VY|@o)M9L$mRzZcMGkI8M<^t8p&1E43MY>1I{CG5bxZ=`e0t0r^g&knT-%
z8C|}Bc(-v^4g`9PC!YdKukkSbS^A9Is0P$;ETcZT0b~0-&<2eKxu6XhH&YwSuyMMF
zBK#2}KMC4Kjr(T6;6vl~EdXOi4ef)I#-nQ?KV>{m0nQ_%kg`&bjpHt0d18#8g86A<
zYB1L6i0K)+P-bhIqRvM<Qwddz>`g*CejGK;e+tXxV9I?Oc8{5a$1r<GQzM>5>l`Q3
zB$bPfn*u2<<ZQZ4@%{-@`#$ivn06$?gsX{5?JRDl1r&mvG#N;ZyXhB7L3)_%=-P#+
z$>THl>t*tx1Mn$RKMR<*X>I~&J|-dEraNu&rakM7DJvE%zNR@;#I*XEzFP~w{Y`wT
zz6O}q()Y>FnqHy9YM|*6fgqFA1GHe%LOWpROfA=-JH)iL5rd(o%$*Q8Z<<ZT*D%vo
zI!T6`E>a0O!nA-Mtw>WBwRB%F+19{(l*!``K(tBt7bbDhYAX5wXpG6ofbLk+5Oo1v
zGFj-19cNmW3!ZqBJQ4B<rZ;DSGtqRBjtWVpa(YyfP1`8_m11(DGDfPYb`s)grX?T3
zZo0{d$`~0Y*N?EinWi6Kf}>fcwbjs)ZJI;1wj7g{?~c(t(=oc#kZ&rdkfy*S;6T36
z6!koKu9(gZz>BM<5xS{+&D25>evzrX7D|gv?iWD2ZsPa@l$ZvnYogS&>SvfJGZj%3
zP;OeZ9$1B``&C%DVM=@x7Aj3H?_v^Frp;C=MOB-8=@op_R7Ew>Tc+!@t==|S+5l=y
z5vwr6JEk^Dlhm4gUV~trNkMOnyQZ~!;Y_`$m^Sx&rUSX4HJF@DuzTMmq@(r&(;mtS
zHJXBFL!imD@jg6kHf2-dx5XsMp$oUIrdAJtHW-9pyD5$W;0{w)6@ELNrr+ol++}K2
zLZaI=GzT8`m=fv0)N8VD0q8R+>><!^lF}8w0h7!ZV9*rQ4rN289owO0*pyG#qeo1O
zIWRP8D$j=8L(_B5KD7srnkfjc;yL3c4V7yrOgrc`GHLRe4KQWeN}1b7ra8aEi^rzd
zr!e@$w3Cis(<Z}95IADap}()K`5^6DcILP5K$*Sy`zByV%@$X<?O^`g0S2AS;a&p;
z3$5Rs#u~Vo=XFAft2u@~T;gU{QGx%Y`4%<LxtsaaDdu6`u?*6l=BHo7pqE)jeMzUx
zKl))Mz0JKJ0{EESDB3@5R`&s%F|ViGs;~K7+8F%I;}nznn``Jh0s-cqgMpnj-?aV@
zx&zH|tKnymIr$B!2{!9?LgJkH>?g1kVs@fN!cg-}%J-f(|3h85VP=^#<igDhsn<5b
z>_W-SNV9`C{_+>hc|?mc$JT)sZGN5_<1U)_9D`3W=2z))jWz#8@A^yTKSrsgEzW$G
zUP<xhO1hDsU{0edYohtfXFy9bZ`Hx!Wb;%bXes94HBggkewA7l)6D(keY#n27n8{_
zzxx=pOtbIXpk<j4T!;7B=C1=l%Q3eM!;8yi_7bq<nx9z%xjZvtF@1PC-yHl3Bnr$C
zZQv<1Cx{_&#rzLd%CDMxh9GgxJoG&#Q)J$r1*OGid-{o9H-9xBYD&!MabPJmJH8IA
z!Yrd&@eT8t46sz14^fy<Wghq+SgOshxWmFt^K&9_-ZHO5+SWSfwz-A6?rO|Vd`$a}
zxhe{RwdP&KT4z4r1?;Z*d%9g&ZyuD;qh;1)KwE=(VhdRAo6r6TpB|VOmx8m={4f}+
z)@0r|2UBV`_uT^4Vt!{Bs$0!LQW$D8@1?w6yZOD3FePh;IVlg`behjnma)tH@@Y8S
zZT`j;5<TYOY+$|S2|9@OnH$tF-*5g5cf;olnB6u&e$f2ZP0)tSrzlM~Y`#fb--vk+
zrC3MJ?lExfp*fYdzA^KQOTaR2W<^47!kkIhA}6ipr6aI3W$s|W{3G-0FGJ$7c>|pU
zo|x-j1U79RpiSq9<)1;Qv9(OleJneR`g54Dw?uS9?x>~z4`2?K2o>axS)4wE7mk+V
z4hT3|Qt0mQam#fo_d8quqDtrqOWu1h?_#k!d<6+tiya+v-7G~OFnH4P%db%CZdv0D
z;9+T|tL2`SVjcv&EV^l|p1&o8vJ3&1jy14!)>6_3OM#Y4gIJ3oOTZr(47O}q43=}2
zxgMBrh~*I#Dnl(7C`>wUIobwVm}RAvGM|x_r{+Qaf@S4W@I+a*`NM9s<q&-)@uKD6
zL4X*`rSAb^EeSuu(My(Ys&vFz4$(;>-txm5fCS66^-!8<DWJh5%lC8=NVYiAyDY_`
zqR=+g^2SA2NV9CFq)fVHgEJkZGb~;IgJ7m5;3`<N@Es`#Ubeh3g~42ll-joQEFEtF
z<XfCW0SYX~Df?S!Q9QzYuUHbK&~nxCfU^77EWHb`Tt$|B3oux02@wOkZn-lHpu`eQ
z7Zge@UfVz`v#hG7D6QPG{Sy8L6_)c!Al|U-r_5NT#bpI}sw_+1z+kl{{4KEDwg?(A
zSYrwP5-k7c=(^*wuD-vP+Au3Ct<2I&v;0|U^6b6$q%3WkW<xElv^49HEx1_9R<<C@
z5KvH%y#-__0y2~#$WXR2fA90<pYyu+ocB5B-sdy!J?GpHx9mJ+;MLoGKw*sryAK;N
zrbat0g`IBOomYZ1*=?h<PtA7Cl<;V=tL9+xTJ64~gAI4=q$o_a&An^)DeYp~?2cNX
zrrmD67u0mvHS<9_?c6&s(0g{v=#+n#-E1nl>$X#U0LlAy^N}!`+heE9M61_sfcE))
zc6&brpx^G(=fHblw}t8fAKDeqhq3{?&yyfBX!q1Xhz!}OeuFc%VLMM}h>qCh&<1wY
zu3#~o8M7;S2Qxcvx13hn6LyQkK_>0i)AwJe>>Se2nzqwY5_QJTfl@0Dj9oX-a%60$
zExi+CF;$N`Gpgu`=ECT|3%jli%U!hG7*zty#UaLS3VgcT7)z<T!-EmC9=(SdPd|Za
zJHq&k3MY>;7SRsp7~@k)3?FAGuL0r7(CvpMFNT1kK;8^4EsT8_o4$l@U&aE;bev#p
zEJWu?hGrI8evAOB`1fb{P(&esu_qL`K!yt+ok0v+X%mzNGj2W)62cg3hNV-C9d848
zn(;J6%R?Ez)1EwxagY{X;f!}^FBZXgZ9iI(j9l76Mlph^@G6>d{beXU!|?xKQ3#`y
z)(mls$*<tdIYx5{%%5jiN8o5Y!$xtR1jY>;l}98pX1xhZNsQ~X@wvc=rig1Y!>IwH
zDU3t3K}%)C)3fX%!@CpCTw?r8DcLl}dvwjDGv?FIA&2qX3s9QNc<x!i^B9q|;>u^t
zr*uLA<H`x}3K?SofEP11euFtIVT9kXL8g@PCG8-}7(Mhqz^*Y)(;}&YkzNg@m5gFn
z@UAn4C?QtG(6FJcn$c4Rky^%1U+``)lIhubli?ADRvqIu-D9^H&wK+wJ!7;HfCk2+
zJcu+hwz@#%Hbd10^G%E`V%o?yGd4(Iw}tU)97fp6nEMmlzr$GdE@bX9zHh|Lv@x71
zy4cQGUI(QejK6ndE;|{sD06p@!KJlb7voQRkZy*W4fFRIY4m95Vel6N*UK2Dr$8UW
zqZ;P>83%tv=L3c<iH=k}WS|TUcLyVtV$p+)<vN%jVhr}er(wp+`QVK(8fm>S%1EJQ
z&KRRs3fION*S>?&35MSR7@TDMdJpEO7<;K^cbc(yAtYxQk7%pnz&x-NosLXKF#t}?
zd1D~XOzArCY%a_*E1}JeX`rHyL(IfAFz?R%h_aX-%*Bt;I?UXj3z4Ht%?7lNF=Z{#
zcAUALLUNwWj45<_F@N|TO1+t`4}tSxw)BDL%WPf*a)P<~07iC_Il3Aa{Fo8h5b<Za
z(JnW@#{8=ay@AX`T6707zo2MpFmrJR5FyO#w01hhbe)aP)68$^MG(p?{|l`!Ci7X~
z!<ieM>2_cyOu@rQ<_%gEMln0i03OZ!_!h_+X8NZ9#4x{-0}#vXDuwrFnO;=YAIJ3h
zt>P)$N72x6p2^TcJf6Al7x<UJyzo3)iOd2GTu5g2orZV{)8RavO=ad$X!9cT%m0JV
zmzb9*mzT!eLebXC%pYhua)qhGYh-Q))4BkXnM^K~q+DfwOyRg}<_mO}=P={Kp);3R
zV%rX89y2Nr!^>x$D1uBOvo{(8Dq_w_gEPg<IyZ=vFh6=7z*1&?4<yT&lavg*#$?)H
zshs%<l^a(u-Kd7Sk~uO1@2@kZKfy#5v*&*s9Om^1;A)uWH=(+gndAZ2ZZLVnlvupU
z^h?Ij>X@x>0db2t>wg8m%w_aYZ(tsuhoLnxD+a;4&3q{gx|^6OQ?S&`)KK25g}I(C
zzgDI<<sj}bm(XtbE;A_#-nTLB@-d`#<~xmWw1cTS2xXnjCMxW@$2_5=bDmwyXdy(q
znK?rA_A(>dVX2S#%tnxYrr~+uA28QY;PD|d=p%>>FrAmeiy`L9cYzyb=6#IL5$3u#
z(Hdnw{}Dzw#{BCNEInp^LrJZ1=Fm$Z6U-#iGRd@3P2d!Bsf-efGt9G}0C<q~oD&Q>
zuzVS4IkMI!1MkE-^*cuB%;M0h#D%qrvInlLd9Op88!PK=kVCALP7K?f<u`$r2kS^b
zT8CNF9+=T1ta!Q@kFxCO1ne=^St>a_&id{Rbb7K{QZXeqFP3dBOn9?4QS#A;l^zAA
zFU$EQ;7_o&P_^Yr7K7s2eyoGEy6|W1+X_GcYg`0>16g)6up7iWwF|9a)|YgSBZQ@<
zt=}ou$Oq7Jnq}GnyP>S5??Fo#Yr!xKg|mL42w;?rWg3SY(X2e$BAsEaYDFuCwOI^&
zEGwiCmd>&YC<qY8I{XFHoM*LCLMEQoNC&qPSa0RRZX)X{z1fmjjg$$wz+(LfTr%sI
zERa;zRz3h1S&L{pd5Oi##BY$sT1I<|be3(yWmvk*YNoK{6;?(qe9K_H<%lt5vi5|d
zb(NLbhE^8q8r8YvunxDv?_5^FX|(cKp_C%aXC0-~O#$m~I`mV>GSTHx#A<vN=1W-n
z<xpM9dL<MhWvmuDj(Cmr!JE)o&RS)Qg^3DQ;3$BVth{uPDpn}v9jaMoDpaXqz268#
zEh~LCEZtx|^#Ht^td?xx>R9j59<H9{9{|$8I(`)<8d+ZS_`c2B*#x^ytmYzgwzB@<
z!{8m(x?m`~%Zgu!S!-jxA4&IbJB#ZB-5snIRyf?rs;4bk7fV42+-_DfZ94C>Qfc4Q
z!@7Wd)7)Ox2OV&<kCjJR&VH6X#W5eULKmWQfHkWZZV$3vcng3b7Vi|`!>r~1qBX)=
zaSW<QSuMw)WsFsMg^o2nVtx7@nvYq2zHn-sHH!{#OtLaRgqkVV{scHY&C))=2xnNy
zf5OB;_P>kK>A;Srg^we9wFHvR?4{c<Y!~*>uYkL<pP*2L8@r5l|A*LupP|~F9i0W7
z2fJf0a7Wnn>z<v(n0u7HVgY)Ov1dO*?{W6_G_*X~bCht{i#<$Lyx#1KVh~^U;a%XJ
zV6%Oe*S=yq@d>;RVn0K{tY9`P7pxHW8@XtmV)sv@b($Sn0e3^$k&7@tVeGyJ_!+@=
zcZ5hJd(~HfN3lmJ02<AH^fo%ru%qIEi(wbhXk*#_baW?<{gDqu&arn<neTb__AGS9
zvlDH!n@?abqc><G`}YfACb5GkS#yDXmzKB5?D`iWlEOavDTb2Do<q06B{m)?xc=D%
zltM{oi{`<L%j{6vT3lg&t-;Te!45tFTqgS&x+t^QBUJjC%??&VGKX!Z&{8hj|FjKi
z^4M2aqnXc+aDq$$d%6syh&@q>&SEx`*6$_k&O(q<_QXHnm9aPc4iB%f=ZGLu&OUMk
zq>^o=mDzQ6_V<viVsD_(OEo)m2Y5B?{gjBj$!@b^fOYK0pTM<S?9mB|9@Mil>9A}A
z`>{WI8`(p&FTBmJJ_*vy{<j#Ug>6q0)XM&}4gTI?*Z&OjciG$jfWbC)6<s;)>^URg
zb+WI~?S79vU4T{>`-^e9{MoA)18|?6co#nPum>r(+RNVmn7$Cz$G%KU*M4?(Dbze*
zfABJtK4k0Z-89G!qo>9Ydp$jahS{6F;l&7hz7@Jh+1n^LHO4Msg7=6W_dWpQ?C+^s
zWrF?H%aEL8&))&bDYoz{NKUh}yTO}btJwHO4sx#0O48=Y@p%Y`oj89|K+u_UbQHve
zGf6+JD`zh)c-%OT=<wMg&O0(ldT_?x2k$V)_hXni!ntw)B1bumaS%DiSv(6v^Wsd>
zQ8I5%Exj>(IG_CmfG?+WK6ocML-XP9NzPUh@w0Je-++q&oIO|34CHiw4nz>=yJ`$O
zm=jNHj}T5V55Q9#e+r77<_uCMDU9>#a&(4s-lbPX1gC*QtdX2|_rr@Q&M_*-j^?zU
z#aPa8N@+zF!*R+0iRH|pr_@=_D_a4N<JeBDg3Ni&=N~~$JZFTyR*=9c%7w#;oVR`i
zN#Yc32k!zWlQ#UxoS!OSB9&874|0(cUk-mSaSqo&TN=l*8E&U@B40#j2FE~OP{`!$
zrc3rJ$36ytEKVtrY)%>Ne{(ntTO7>ia+dg@H=k3~0ek^ROvexlIbK&`zKC;$!gj?R
zU)ltfaLxxncPWQw1i8jZpto2#CxABk6`V5^ey!xlWYB$`^Et)rt2k0x=~r_a^zfpF
zqoeeCE$0vguWxXs*3o16CTEl~Znrp}(Fvk@jx!tP8#s^b(b>qE_ygK*bE>Fnq={2c
z=LnlQmA`=3$~k==l6N>UGaz?4DYRm1<9zTYbhmT1P;K}<&NL-LyEs2kky|&Xy$<mE
zoYS<d?cx0T5=9SsIj;7Q>Eo=YsP_X-d<|L;Ifp+18Q^61LiZqN3sqVSad!GZWSEm@
z0)B*ZnR0?-oQ3p?dBkBhLHA>hJPECFPAU~RPH@`K!0k!Sw>L5DDUJulH>Nq~C^t95
zQDe4ka}RRgcn-Q9xC=hR=$*JdRA=JM-8vh@g<D4{I#=$0^oDffrc+ViA#QULc<$U>
z3S%ASt~5gA2-k(uAV;~6Y2kH@yYmLfaqb;Qh<I~fO-9Ryo2^C5m-`x}S5I&k(AL6s
zk}KMX!T5297GN;`+=*#e3go`_E`}Y%eQ^lDV6KwB?ia!>qy+mZ?%rDbBB!|*7s75R
z_huLX;oM*8eGtJ-rFCv3_cFa%qqvJHf)mYs&kpc2+;{T<kKv}%+B=rJp$(E}ZQQ-l
z5RK#ReFe;O+~+AI7|;EYioFxKldqta$aUEW(Il=Ht@ti*4^TaLGWUs6j3R}5-3{6<
za(jNnlw9Ke*a?!xJ-r=(bna8Wki5*br>Ar#cP>Rju5zC%he#H8?IH{}n`_%lA+j9q
zJxXrpa!2TZSRVHu4#t$vowy4x3b<)G=q%#yS_qM1?nmFkrxI>96_l28MIwllaq|_>
zUCzy-cwGh8?F;ZKx!dXXuj2kdulZ{3*Hn2^!_`u(w3eHa0Kg4yi;c>zZgQ(BqhH7E
zIt$<GxhrX5(ZK!Z9&|V2zc~PLn|qNW`c2&6F#wvmFVl0Xg?owiV0XBU^Pu}K_l+Qk
zv~eRS?$yq{L$T!!?k-A$cXG2hFxbsa7=icqxnFz*(!(9QL(#ilZi*d5`?%lGozu@<
z^c_SWaO0>t^&xiytqljb_rCxc;y$LJ=P>ubVt6>h-9v$^QSKEUI>)%DOQGd4w~Wf2
z$GO#Cp>u+p_z0a-+=*nsr@6rw(3;`?x&yp}ysW?JK%4{blRT(#<h?b9-^qz*q4b0c
z&%O$xt~@oB-njAF76WmJclH{5a_23fH?#+DPADuL=KVxZ@T0sxwU9i<^EeCMaoz@c
z`+M?!q-VAlui+W+ym|LlLdyx>E+@23@>cDn137-Y$USKK^FE_RVF1sY0{nrz+!VBe
zc#G}P3g&%V0B1sYpGN_InrDlI7oohE577$aZKs7vIFCcm<p`cjC4R{$UM|Imqj{43
z@Zt>b7fOl7^3J`60iNYe(7&dL<24_H+qQGOXDBdvo;M|dXgsf60(=6`Nerb)yeAGr
z%>~}~bOR;xUZS$a6rKa!sj0lkh4Anquk#;tUg8Ooab2YI@?Hk~GA}L-@GCq;JM3og
z=CwgGllM9gomY8nl;g|cNht=OYvVoa20oAXe^k7g&vU2Sset!HF-ReA*3)pfh?m^}
zkz(HZ7>JbcD(I3g<!w9wQpPLBe@mWwjrVgCNI6eI#S#^~eMy*$O5W>~3%$-;Pq~9C
zUS~7BsOF`aKx%jmI{~QW*<$lRZ}7@)!^AC~iZ+V%JWf8$H}EocL9~(QMK!Xwc?+Xp
zzKQo5l{qx?zMO?t3-4umRkiZC6e7FB`<r50cX@wNZnBN{qX~A~d4gD|?%=&i$(2st
z0{YnUJ>EeE40Z8dw(Y{4bo1=90KCt;egV$(@YZbtzL%Fkx5ES8oOSTxA@7qgv<7&q
z=YcoKE2m)i5YLI?`@_6t^xKW_UilbGM|t1wgU&JDi!&gPcm<SYe#~p43axQoUm3iZ
z;60cPFD7|cvgnOD#hY!0=rr$-|InJ@?cEJE2l>AWq11uDiK;{$`J4rC&58fP58%1-
zpQm#IZu|{&LirHCn2s>G^XK_Pw+G){2XdHSN6Ymid{;7fl>b&E$T5E4Dp)wqZ=|c!
zlmFz?R1)dU-%j56@ZY8!urL3UDF9FKchYHxll*2nEaAuBL51u7{Oql;6u^JtO$;WG
z|1AZ&gZLgv;05!mSA(45Yw0^9r}>k!&<f?p(gH4w-$?teaQ*_SVu|4A_M<bB?-5Da
zt0?{g+UrE~f4&K&XZV8?V8-y-bV&UyzvF9o5y$_47F6f>|JMlD&h!0#fbMwyqt`$Z
z_&X>tnaJ;_PX#9N&r@RU0zYsRoyq(y%g~v^_o1un65pQImTCO!%OR4^Z{7lDY?t|$
zDF=Lozl5%c3_j}Zaj)>VQ%%@a{=iz0EPg#j_Okhj^diaOZ<>K*9)HjcZs+qqFrc%5
z-~9-<LVk@W23o|AqyL;&%>SARTnYdFUR(mD{G~zw%J~0K6~Q(BybAEjZTxSK0$<6`
zn2pK5&Ohdg-YWiS3Nlpl`>q36!!HxUU@hN)N`r6kOQ|a6Cf|=zopt={l+C}zANd|4
z_52kSWNYMqSp{;Ne}ML|P5dCb0-O0+6==2aPdb6L^8eEScZY9F*Fy9z-|rCYw();{
z21?ucGI~dL@OxR9?k@fd#TZjJKbMyD_xW7fj`i@TD68Jfuc3HcA3tCm{`T_?e*pJ@
zKkGaI5BdA)1vJ3_g|Y>M{Eun*I?VTa3nC+Ym+SC%lpkT!z{D8;lS1fz#Q%ZP+mHEM
z6d>dL?Z@Hi1V4T;v`z9`^B^+C-$~KvX@2B)AO{6WR0!oDsG&`kqd@aElsXBXqHvG1
z;6@W#E`oo8KwJfVbm_PW{-9!<LxOK;p4<hmt*7^&hrl%jGDidfV)Pyr1UA6ZF+mlb
zvN$eST?&M!;OagQFTrNI)4c^x(<8}85c|K4h2Xah0GtqXxI@`Vfg>e#0tERd(FzpI
zEWmh!1gVq@4i<cL93({Wg$(4B;J3x}{yQyD90np(aIOp{!UWgW0ue6QL+Pgo!Tl#-
zDN67uZIYq|JbOr<5p>mJyfK1M3ed+2JSj_YR<PtSNSt8bJa~9c(DDL&Ixp}DgQa*u
z!eZbO1g}zhAW5*P7Oe|{^(Zj1%}o}pr<Yrb;CKk^rV1*kO5~#81v;I0Nl@?t@M(g8
z4N#gcSa%glFAKh+veqkt3$z){6r7~g!&Sj#7Cg)n<cxr13!-Q-oFlk;93)q;>L>gn
zd4i+2VIg1e*axIQP_qv>TcJSq08SMNPUxV!RNzgk?=rz=I$VEEaC<I9%LQ$8`&S4;
z=p9ulc*_;eTo){Mf=HFXBL!-z1>brCUL)wz08lHidkD#!f{RqnSSNU(0`Hb!JRPd*
z1#@;oq(SiRahPp<OCSz`=xxE<R6*V(c#3wh&4R+?K(q+<`mF7E#Ww#jB-;hfWf*mb
zAmt(iI|T)_Ot>e=et^y{!K;x_-7WZo{&UEEK}H=^_TW?!M0y2rHi+~Kv~)8)5NuaM
z^FzUF^j(qxK?ar34GK7}AVY%8Zvhw<d{5_nM+7GyLvmE`ukBml#{>*7ARY;_>FX*J
zf?2dznG}3TQQj%RLJFf#3!dqR$c*5049G#@q8%{kARH$T9fiwcK%9gtTmW|#E}%7l
zi*VZ(Ore{woU#Llgs;=C(_OfQYP3CskLhb<hlM)@v?M+vd_Y^gqr$)bgwkWeG&2Tz
zT<CQfJWrt)ee>K)=uL4KAK|tNi1-Q%4}y0>_(macCxvg{K&PKjwGICI3mu<FD?r#n
zYvDlQ+;hMM30d_2Q-g(5dw~lPUJAopoE946=oSeTim7TNOem1Usc>Ox3R)4u{ZwEV
zDLg^tc2U9(N+LxIFVaKrjBs~3h882_P(5O-@C|xJofGy_;QPF=jkfjiLJNfr6NFc3
zkCP~Tnod3>2~D(1zaTu^09>+gj{E<<86?a)i)N~j+XaIch5H(SNE5E4Jx99m%L<Uo
z!XA1EToEp!Qql||i{74@!fkD^dsXOf1uskJLs7(RVbce2Ek}4>3`cW?skFz*7plV0
zDiCHz!NWqK>wh3cLQWzK*@}g6^qwyfK3xlZsj%=2@MXfUcY|CL-rNPza^ZqEFs2G2
zs~+aB3x9hC{#FS$D8Z{1UL8Ycjc}Oq47I|tOenn}Ty6llDctb|wA2X?`9t+B;k~nH
z)eGm`gEI}nS@cS6vI%SHU~98bN6XI^;mf~3_g&$GKf!DhuKfU`Zx;^#2huCd3xdHu
zVIu9O`h}yVu=_xGX$a(@@W^){1Hv`55E>M!Q($69_$Jla4GZsWhJ_I!he~`#g_GWB
zjS1&3fyg7FEoBLM9}7SG4x;12dk2A^5dKOp+DYLZJj3Qr2?xYLObeI%4KgF_q2%vD
z(Z72Ea1izEhNPqD?hOphN#y=7I-Nx?t-^R+L?2Mj%~kZ77-Ml074Cz<L!u>AHtH@K
zq-)$m^r=k-;9-&OT@3q(=+jprdQ`MC7;27*IFv^`E^4ADnx}|C8Cow<M>;yaMSGIa
z@)6~11kYF0M6-56RK6O#lOpGDG5LNXmy6KiFWUVLIs-&fdL;*nylX&$L_f|0E?Bg-
z>VIYMA|XAsPKg9}F#6LXS9+I+ivD~G?uUu0Z=o|>6izGS2$ADjD2)`o$N?Zqv^@=8
zM2qhK1*K<12cN)LVnk6(F(t7g%^HxiqR%N{9w*B5g2*|MM;JuTixv(;b-ZYi1AQ|n
zLFBw1qKP6Gx&)F$|4<#y1(CZ7qRFC1dto9)bUp$;rHYy<vv5(wqWIJ$kwXSL(?qAK
zwjf>PK<oO;qIdhyc|}y~fX=I;Zv=2OOSCBvxNOnDG@Qv1Wv2n2D_UMa_g|jqn{U9(
z7tN;njslT;C76XG|8?-GNVJBQdc~sW#-X%C^b0+EOGWFb;Gj%&j4rloqLqk|&n*|d
zLxtfLq73?0L!~HyR<GAZhG${EN)%1^U$y8v9Xe}7#W7G_D|&@8Ft!`Ggy88-(efq0
z*NL*JGWM1zlBzlDMf)v4G>D#|+QCNAJxV3t76sD@l_pWgCMazd%}E2GMf9~1UbKpm
z$D!qpD2;NDcSYKxXtjw<6o6|N88QLr5S^pTqf@l)Yw+&bM9)+GK$l4VGZ5XPZ|Dfb
zeUX~JN7*BqGXR6VA_kSU^oh3ELruRZiSEV+qPHpk^iX6jgvfws%_MMxqU>2vHY9p^
z69B`al3Iw2h-`OZcU1J}QFu5es-@HIk3^vqn|Lg;h0qAcMJs3#Jt0!Rj-gG8TCYH6
zO0<X`jMJhd+FZ?uB435lgJN|e01o0ife>*Nf3plCPGSeDrgj$Ru7FY(aRtQ+T*ZIw
zL8qJeN)TK-B-SoP%U#?}HO?O53$zP6EdJE?Dd-V#8I?vH6|+ykQ%`aH08Ds^b6-WL
zw^)#f@%o70rb-fD@!ll>oDhe81KvroYc$;U6Qev6x0?93a=-(`z4S^C6mPx_K#*8K
zi@IQOCl{`Th*w#_J0)gah0fFBd8cTJ7%G0=45eY>GjvuyTrB7UGeXSy1)`B+J_R?T
z#CGc;5-nE#401*+d<~K@V(aU0G*<kx6C}@ydnw8lCuV*L-Z^o|%b0}o;v|2F#EZv^
z&`J>h^d;bl;*+yMlEkI+>D1^2u{|vVlf?|m3a5x0DISn2o~FIdMe$ZT&v!|@fqY66
zr&H86UA!g{BA3N)y$jwI@tagHks;<&a6VJ~!)Fk=Dt4PjD@)u@PrY1m{6zrr#6$A|
z$QS=N4)X=#N|b}z<`#;N?||+iu`wB<#o`vKODPezT?4*UoErjQnK<GhCh?lMisCNi
z;-N@LR)|m4V@fN<e{VzQb@AzE;eC~O`*Of*#n<TtbVICr2U>25)9qomPHg%VhHi-`
zDH>ld{#^{!wg&Nl7Qa)Yxcm;(+!p^%Nv$UF9;z^E7H_9TVT*Vc{^qudoqmPL9r07Y
z!~9(_(q_21#LL)F+Ady5QKt^Ek}mR2aqDw1cu&0XceJ|1k!#>gx48a3aQDScOJTQ1
z?Dznr*CystB)U)R^M63}i#=CE%>(gQlx%t^ZqcJPAWo#?ri0>BR8T)8eu<LO!{WCo
zdp;umjXn%HD(+1J858F);L{`VP8C{@#SAmFjEg@W!gNoF4^fD5QvBB`=$sPE^D)k8
zv2E+mkeLyG>jx7DC7pEU-9fT+5TcHf9~kh-N%8`%&YUH$%>mCv(((s@u96GnubX6a
z2Azi_qF-UqT@p)a77vN!Z+LN7vi4tictkR*0q~;|ualV3W0Jkk1Abf*M&(YP60OYw
z>Lp3M3!t}TKBee<B)%4C^OdYv4A)Lb7JUTZNr~1Eoqm#i^v3g-yiRHYBt5raDNwS|
z36en)_ut`Du;kZ&p)5pVPwDGZl9)c|JT38}inUNlN;OEBq?wiy;gT>uRYpZfw(S8v
zTC$HG24^JZJXng6toMd!tmJt*FmYD0NrKKeN$ez?IVV{{wPxofJ#w_-CF|}$Btdfj
zCOQ)(JPJM~NfOpW=LN~LpF&Hr<OkY-q)0jfpe0rEChapXN+RQ_xZ;w;i8gL&lDBDt
zn=bi|c3hVw_x=F6BFUrNUWO!=iuE%kktOK7D!KhKB(o&dpQDv6d5xl&Ig-H>7-+6!
zWeiB3MBxBS`4W$Cm@km5pc|)9^3s2pk|N2GE#MVP@}}wjE0Ii634W=hc`dY+NuH&m
zylawM^olN*>>Yvb3d#HRaJW+PeIB%3mrT=|xJu&c3qZBxIXYKWBQelN=V~Q(EZ}ZP
zex$YZElETf;PsLZ&Vw{a9#am!Q4+QjyxWpxRO)7Hl323fO|vAm05UBSdwSuvN*F?j
z-jSqH<nOM;Eg2@-B$~|two6XZE4D+jyb80{DcSc4I`2v9q##|ATNFX-mVEgYbl#VI
z{xn)Wk_{D5)+=$N0C=C|Rt!4(CC6hiqz5)he><2DC68$dH6RIH3-<>lf&$14N!HTJ
zVp!r&A(9bEG39JWC6$X|eoRt8bx4mS&$VDmA4{%<128UeS_j^Q<f)%vX;KnQd7&xE
z;0@rWB_mXrI3tOnb@oB2BM&?Wsm)4RCP(Rh+JZPq)7xOlS=yNj;v#i<1EQ|dJ}EqO
zlP-H3h(pqE#IWlwo$U&P9@5dJn4rVbE-~CbBK?N}Wk;o!#eg4^zP|~$<5E)}Iz6Qy
z($mLFy4eg#Z|RdYAU;yLjjjk^X;CPcC!`k*ASa~`bgI}-`U@qp{H2opP!k~aqNPlr
zR6virAgTTpxE3t!?}3^S>8Dg_cS`C*RbHp1Wwf*om41;755uGtgJ^|I=lVfQg!E7_
zT9H!ee*i>D`CI7y7cFh1Y`__*R|I6vN|$Yg`8eq&3cs9_K20y<^U`XHI>k%PMwm~K
z#;pNKl(Jq2AW1q(H~a;u>@$#L>6QZEQl$A*GL$N<dmiMXG{qOLU6MZ92)k+0t(0p@
zm*(!J5ang*OGlvQinQbhkPN9d5co`KcOFb!mCi;Sac-9McZ$<yOLsqli5%&pUx3e*
zj?mgAPx|yqn8=sz{TZDF(l2OA3Z*Nk(zQsM^C3vFv{43;5@}E_0HxBSo8e5E^oixO
zaQ|JC76~v3<<gxuV4_0$B`u*UrFp?{=DJkChqfx|?M>iSOE<p)QX{=a1rfE<SCo*v
zA<f(mk(*Kuy^QOm<4`*Hmh@6TB<rOQXc2H*I;ccvlk|`ibT&(Csj{U-Iwu;g*;=I%
z%3Iu#+Rp{KE44m`Gi}m6t#Gj&GYd5x()TIq+bLZ~i>-Uo!X*H9Nj*>E_wANeQ3d9G
zsiF-cJ<`Z-kY4HL<G}SvtJ|ThU-~E)svk%n3IKR0O;*F-0qN>jKn88nFX-JoBpqd8
zYKEmR{D#(u)Q$o3qtZ%>#g0jjUxeL9(iP{>`B?f6mEMg@S%08&Li*=C04AjcbjD&z
zx~&+1X=yPHVn*s60)q!-wWA;oGBqs+9c6#f#@tDk{yyAxmf0LA)aW7`rk9MX?C~vl
z;U+7l7s(-6^#f>gm(@{;x`%9PFO(jZ+0zemOqNRt&f~JwJ@CR)_HiQMUb5Z}bb8CQ
z&%+rXSr3ICd}S45n35AR`EuY+%6_8?EkD^sAE@@132p1a43O<=fQdlaZW?Hi>`!_N
z2g_z?FC8NLZ66S!vW&A(8YUZ}y;8Vrh>{TzvY)BUEmFpzSVffV2l_Tuw5;|Nygws*
z<t#{ytSbh}Vr6l(mpv;B?t)Kovc*o2JSQu2r1;BuSxq3A@v=qqO_2myPd$K%vQ!mx
zC&~7{0WU7d*1ZK_vdr=fL{emb(lwVVOK^ZQ7iBBcFtkguWfU?`ll4$;JY9Bd8m-H+
zeRqMoBHKvE+A?H+(uzJ)_KzO^UX_*h(LXWElKnz;0@<=le?cZk_BUNuxw6hM0P|#7
zl(5T}Rne2YKvppymI`G*Qe>(~c4HP=#j@Eif|SUdk3eau>`5sAWwQOWow_F5s0OcG
zwy7Ju3Yqma_*;qR1cp>4dr(6EM50>u{ybQ!kvXZrtd-r_1!r!^BHo6<o3g0SAzCLZ
zrc}%=S=1$HtCzh+k(vhCnOK-;l%1p;*=?C81v;B#E`)2A#ZWm&i)_IQ_|aNr?2Ul8
z$v$HN-YyGFgJg%SU==!ToifWQ;P1(vr%$GJ$=d6H=$5@lPm%kwQ*>GO$eyC&pI+H-
zb{KY_?8s_}^viyv({T@E%e^4-Q1;}9&^92uItDF+vVS@O7?O=IgO*|0E~=*(k-f48
zxKUX<1?$FSuT#Y1kxh2sX?XKk_Wnm;j>|rO2Yye;E^UUkN!g}AkSUpa1uRX=W}Sum
zGqSHjp!A@;f~tNT<o2`!a+H5hfov!FZ7KzImVZmjBNzF5Z$YQ4-1{bYZt`>r<{XmG
z9)?bL`Tseg<sr9y!i4By`M00J#1Z+A6h%5J54jDQV{*l1;E&4{BM|YFtKI^_OD<Xs
zp0|8o0!HW~m!ARgmG8*|IU)a#b_6HoE>#$>pZvrHjL=_x(i7$b<VT-DD^Pxpb~i!t
zNC8N&e73C+%n-RVo#HwrFQ;;@)AHq&5Dk@wP^>&mKJR0+!sVthNJhxBDTxs&*ABp7
zlzf;fr=sP_6s0~R&kcf>82QQ{0Em^h(L435yv81YIC%$c+Rw=~r=jz_{F!-}r+B&F
z<^M$q<;TyUH&K3|2r^0Xl-sa$K^{dxtYrBvN`<D#Pty&bDqpn-t&8$CRFHZ}o|z4j
zCSTYCUb@`B2Y}1+%>&SVMgBV_KQiP!+hIOaK15OVtMZ{Zz_a9ORAZGbZ}g=Sl^pr^
z&Tv0h-b0VA0(rYHoGFyoS<zV}AEv-fv7BiDqD1~)FnFc%L(Slo$-Vu+yCz@T1YWuP
zsR-~Y<e$^2h)Q|LVf;+j<@vOYtCFkz;ZwC-+6Gc1*N_*r@{mD_zub`T$pzx3++!N%
z>*S}d0&z<|@+>ByUjEMp%yWa>e+~xIC>KhAzb%ia-FlP!0DX|6S-y={&n@z8bRMBq
z9zyAzJMz+(q4TbM1-<Xv<X<r%*)D%=3?6pK*JT3UDc?Xfy0&}raz4E2k}IA7vs?aN
z0LXp0@D7yr$bX?2TCd#oe>a}oL|@0~m-|o^%L94BEs%%ubss?6fc!VQkOt*V6v7^o
zOXx*EEWh&<l#R&ken)Fm{?a!X;F$b1+MGR-`_iNLu}z*o3vP_dSIvPJ6Y@a{nor7&
z;b=|C|DmVAwA}q&D4mgeY5+W__>q!64vOD`F;GXv!H4k4Nx?`%r?bM|1uYjv_fFtk
z6}hw}c2n3NfQ3Vft@PS=S7cE-*h8_c3Y~`)wqRPI98nZ42L7nx0qr)9DVDTB=D1?s
z*XZ<ARPKgdFGcacaNk=|@ivH$;^hSxy{|$=<#Hz#Khn+Nrx<+)Zu=|7>E;ShIIy8Q
zQ1MzONRT3qi_T!h1**{sQMA%2+*67W8@=dHD;85}O{l_{iB_26+&YkOMJmM_BNX*i
z&K0TX)x$)T!iiSj(F(pR?4D8VqvdOi!uNAH6RY_4D-8Rr;_ubq#VH&pNO4Z#UI3Bv
zihmo?idVeyJhUVzrr(8@L`7o|rB9L+Dth`{P|TVHK3OqB3A7Z&8x(L&Rjk~F)<s1m
zZSF29o}s6Fn!?2cymZAp3FhLm;uDHiUr{VM3dsz`8Zwcom{0q#tBN3s>}DzAY1y2u
zn525o9L3vAXvtNKx6}SFPZ6{nh<wHL61Z5Pc#Q%+g^J}Ao-a}yc^8OcMX(=4N);6o
zFj1x$qm<4y#gmk|Dp$DI15lxOmi9cAiuG4u@VdgE!k|@(*sEw&D|W9yt46VblEk%&
z|D$cf4Mk7>v$+3mDx`Gj)hRwVfZS4i{2Z9|igl$xG$>}j3(}}q>W0qSihoYQQj_A)
z7R*JnLh~+$-J;+Y!?jk${;hEBjv|u|Cf`-)+JI|Q^gavHuGm6{ZaNedE+CzXNy^aQ
zQ=FKELD;$!!2{6Ntq@QJ)qTacQ~}ka_$Ls~^eXh7AbpCrC=%YU_>g|s2a2U~n0To8
z&J#l$P#my>nn8tPK3p48{8S8|h80cQ0T@v<mH;rScp(vX#}u>Y!kI^kmX|>uD?V#P
z=eSMrF|FPw6g9MZm{k0*3tmhqGWJ91v?BW&WM&i_DY$u1d65A}9hCpjVGn0z@ek;9
zQT`VIgRaVFcY(MmwRBS+QZ8MMmb<c%BGMkp>pAfEu(FVjSsYQOQVGLRWi_2IJ*Kq1
zK~b~gN(=3?J(cHa58$O-9sn6{rT?Gs)JGXX%Q|1>qgUbR31tPn&Q2=-p@Xn~N<#^F
z{>r|1bOtDYz73H;<yNY>4N_K8PBB=y`V_nfQF3;IcS`voErCuecMgIVs_d{;fQBib
zIu8=A{M{4UB9ve9Fc*=^Rtm;ODLuyFX|(b=dfc5+>OKTMMp^bEw8bjFQo+Ns%Fn6t
zBTgv@fTeh)hzl(V%4!AxiOP>YL}!xnebRYBxzirFWF?=zx{;!MyoK@)sme&IO}VJ7
zPXoE6jHjzCO*uOPKBX%^SpocIrSqSdnJdbEN<3sJx6#aIDmC;-x~gP636iCp=L6l@
z${(rzIY-$-H7&Wy!7stfQ@)W5T)y%EeZsFmnUao4FI2v|jK0}iq<m70-eP603k;Sh
zSMCA6RQVYlhbdDIQJu~;WfO&Q%9S-MV4^}<VuDDevepx7t}ERRfLEowNbButr6wBQ
z*C-Dqp|e(5L(jk)%1k<SeN!p^7`!@Vt}o!XluzU3WSd*ByxD}QX;6MgS+Yi@gra=6
zmCSL-G%44Rr_IWf{?OK<{Pi%jwJK{U&3i{_Ukj1D%A=p5vrSp^4$QYJv#1iVL)n=K
zUYGL5HAr?V=YEapy082!9a?&nbrkFCRi4}fV(U}7P<2PYa{M@4e4yOD6Xc<?w;hN9
z<z*^27*u{-3#CKKXX)t3uyX!W@M%P8n*<qEHdCN?Ou3J$*B&Xg$6)ZW^4CSsJ+AzD
z0%St@f(E=v<)9C=OetfZK<BhFBor2AY)Y;Y_=Bne$~`%#rWa#^9aWp?H*iwzegWp4
zRZ2>jxTq#+ljN$(zloNcYI6(J98%Re0pPCMMJ0S5s#dDvJgiEMM(c>`1B#CwRaM<X
z>zJz4AGqTx8!fB+RqsW^Y=FvkXCY{y%H9p4L8=JaO$Mu;`yIZ8s6M2S$0=0~#iCBD
zuFz92RJG%8w8B(%R4f>-atwj_2vrfK7$a5A-2g<XKA_cIv}*e<@Xn|v6ETPw)tYJW
zVpS1O!`@ldOO0?QPIbiQ40=vw_z%73Rjm}hjaO}c6)q;I621jVR6TZwwj|Z9U1(iU
zJxg2hWK|ihEK*c|QJF)k>g``){-SCPZ454{j#C;wO_i4lk#yBQF2-_M73v2IS5#rN
z#mi8&(aShf)w!ACFIQFDC}@|ZDh)$#w(2!HBaow7N{6uXRd;#NR-l@SLua8XgqGGt
zs=521v{>ay+0PPH+cEG;RZBKQOPT5_l?Gf>t=xfDh3X6kB9*F%Dd4WFV(H{<m1;{V
zNVUo(pW-hyDm86}YgO~9y!VDGW*PjxsmiCoOP%T-ALehVcCP@UUiBkw1sYT-akyj~
zRZD53dRrB>7rYi#8&z(!s`@DFdRO&#5#VjAzkh=>?W&+Lh;*plp@e;>>LCSs?x|kM
zp!=^&^&17RyH%MKdbqEOr(&2MRbU33=~ZRW2>Vp$V<FP7di_O=;(@B~9+W;*C4C0h
z22?S95E)eE(gi%E@^}-iVbzlvP&T3}=l~g2Jxw9qF_rrhaQl%;yBe-NR;mAiGTXT7
zlWrg;RQ43koK)GdVRuTkVjXl(tJY9%e@5keA1w!UZVq^k>Zi^_(n;+_fk0RF>~r9`
zse?-}v_t9)3bVPZd**<6sK>s5rNin+43J}L!z}=gtIc$L*i+5<1Im1C>RaEzDPQ%T
zO30j0<BgBEi~2tOhJNb&E{OW88$ZI72B>em2NQwn%XE1KsTX_)w}aLDC{+-m-thw9
zr_|DFh@4idDKHkQ9`r#gO#Kp-yM?Rso`m@b^=lsk9;r4DfJCWnaqSpkwE99U)SOZ4
z>Gd6>KB<AWSoNqYcxTl`l=6;KpP`+|IrSfo&~{$EpDJtO)#15tEkXU-Fq}zL58j4I
zl6v`8bY4*3c?=WD>a$cUlA`{W4mzZ&_YXkzMRnR`NM2Hh+UNvWntJmPWYX22Zi0)K
z)r$f_uBbnu&~Ao$%`0#%OZ~_IV75AdR+TyG1@v0TRWJJ-Bu{;r3ElbXg%{8&Pzy_;
zvrv676^<6E(|SRQ)v09=DNzdxV5n66B<(rM)Ryn*h{84XwqcNRbubtB3ibUA*sWA6
zDX@KAz1$AYRH@CM!Ha5j@*e1}QS+`tX|4JWt?X~8Ya)QVsa|^;t$MYJ>L44`Y9&M(
z)j!bM=eF9J>SmhMDfF~!R=@lqL|W7<nyLP!RsGi-0Pm>h%wUA=>b0-K#SZn_qp;hl
z-gXjRJW$uIgvdj6!Ca65b;^^#53BW*m>p5SNDuo_^#K-mV`^I`EIm@YQ=Iv+n(-D|
zlj;@<fJ~`Ry$Ld{ZlsYpX!t&~|8vy1zY8@^np^+Dyt5{M0>nl0*H6&qstIU@sHf&V
zs;%+T^iZP3TXS(0%=>73OE5xTjmIrmI-z-ya@{92F|VTKr)hi>IDbv&5GFQ2BX|Rn
zftn_YwFhZdP@*JQV>t(&EkyHw57B!{v-n>a4Arcl3nNSudkw!qxMl}MHzG8lRLc;l
znezlpL}~7P0m&H6hDhLIH81CacUBYkDJ0`GpAN&(bDHNUq;y_0e+4YXYrM-bqy$Z8
z2SgGzZRr3cX?m=HU$ALzMT42FaaxXMismf^WKuQSzaVo_^Qtp=mo)v4;8U8$e?5kM
zMYGWi$*Y>Sn`mWej%)(S)_lJJojDrGKD2T*ReiwaX?pf!67n@`zrg$!Xu8)zXQAfv
zr{GhO=K0y^EY{feoq(q$n(G-5E!8;Fy0=W@>xF?{(;WO7h;mJyJ47lpOKFo-scE5d
zyX%@}6IxXo!%gt2HPYV!zoGf^JV=v<vjhG%Yr0;Ar4~&-6&kc^Tu)+TcQm)k0l%x+
zHG@{WW`&IwfE^mAeu#Ezipa%#ni&>!cWG)@gLG@A=vdo*&6~8`=+Web1JI{=nsNmF
z8hcOp`#{q`YnO)_#Tm2)G%M)r@Sx@)r9Xx=f-2}7)?~ZEwGqutZ?r}=n`kXQruppv
zec<4+W<@4?$2IflEis{a-~r~Ori>0xO=+^JzHeI7>Hys{n)itu)LLi-=b&9ekqbv{
zl?8Aotp~lRowcrx=ycI0&Vq=mc4;4Ux@r5I;r$`)Cv=gyYri}XNe}IV*D3yTOv@C)
z3s0@v6m)xOcdx(*y|qu!sT?2e7jEeE)rL?g`h<1~6<qskKkLR|0<@<n;u5I6rH1Yx
zt=Bs6g0%}PfeX>HXx2_?-=o0iY3;I5@Itk_M9>nhEugS%gtl@v-G7l<pD1XH((-?R
zOtki>1m@3ZV`t!ZjMhZU?pW=*45&G)&7?!WaoUcR0G!iqodY%JwaiaJ61180ph(mj
zXo8cp`rXiSLCf`p&SY&j?UhosU3Z}KqV}CWcyUR~EP^synl`l%GU?j1cmOYJRYPc9
z(QYGyncB&hL9S|7HDlVcv;|ZJm#ytw2Q@j`IaJz{t36Ju_B?IkmoQPRb!K8NO0;nY
z!7J6q(w$zWJxL*tYuf%7!K={5<F!AxQoC^kyz4gYtGB_d(e`WtzE*pSGJZF--_C$}
zQ=3T}usW@v4#0Y?u@ZJ0v{|&VZ`3xfg8R){!AIb=Xh&&<-KuS%uj${>wo@SQuC|d5
zUbktT)&S71UFizRPOX88@a}0}qWpQ6)^@EM%x>+k6mhw)y+BL)9&KnHNU!$JBu3Gv
zUGoPV?$-_+hU9?u4@$)jYRej+W=QKqAATCvezXm`N3_a&;Eig7X$SO3yW|B-<zuat
zDjLSMC7(cKLi@J~os-($ZBRX<ecRRo(Stf31H?i1%d6;h)P3+7+;`G#pog}zj{UzK
zu5Qj6h`8xmQ$P;s7^9GM*L_5B8xLLaB}g9CIrqWQW4b+5>UmuEg$W*d>iD@3@zTxy
z62x0q_ayxF(Vd`lny>EkUHZ6zpYFpKfcMuOr#MQ0&YgbyK%EfbiMc_#l2_0fqC0UC
zh*P@fXjyk!_mIM<VY;gn8Vc79cVcEDbf5cR@*{PYpJ6^q_j5nAMC;!81iTnsIlV<=
zb@~@!@2u{K0-bTX#8~>K;W^#6w8TBH`;i{+2|AbeU@%cP<BiTF-7?zkU(os8fQQMt
zre?G*>M~s*c}cf&E7YXves~`foUZ$iL@w*5)&PD*_aoWO&|Ra09htf)O6*+Ky-uY>
zS-Lv<CP%ieXfAzVBuCet1gCO!o>Uu<rz@Z$@_b!UIV=_Eo)&{ws0*O;q(!=NDk&<_
zy+a$uQr+tHFj%IWSr13A={#r;U9PLFf|d&1v&rC9>iB+uU)Rl};;<^+!x?C)*5zlz
ze2q>)5!!{dy03qL(i^%1v?jl)yX1FZ;p{hTsWKoMbsyTp(rw*16^S(I=2H=Ei;gu5
zBW%?rP=@o4?)MMDyQ{l_WXjw&-7R_#wd;PV$3Q!Ddv=1?sk==PgnPPuRQuGW+xRL-
zw{9m@P~F!x&=JZWT~HJNy*k@42GOTmW}~aSU-#9UAP;n(QV8Lp?$*yxGpO4`#~+4t
zA@n{O*8Q{*yfIxrZL1#X{;9?2AM4UCgN*AIufupJbi3(EJgKYx8UvitE&Uz5Y26%p
z56$S_{|a6l)N40`=b-<dO6nZ-TQAYF%t`+bdEu;|?F~^E{nVT2bk)yp0K!eby9i1T
z>DL8==dRyG-_!HZe@*A-4(s2cmF^M!pBvCRsxPSl?wEetAaozsPkaZQr~WMw0ABhp
zEU@6M|C`ovKKeJm1kP7qdydMoPUw4v(LAYNNLz6~eLDTj{`$m1XbaH)n}AlJK0Fky
zAbnCf1{$pIF=G-#^wx#YeM*1d86v0kpUi>5Q2m`}K_c{OdKpLRohbkrr8iO-G+Muu
zLPKZtxgS7FjDF<}3Jb>Sf1*p^tiGL=zj69i6KI{+httz5USF3AlAs@?z;?3UhhpX_
z`h7oP5>xfZXq$df|1u>!F6pzRFqozfEC(-LZ=o30W&K`%D7&KHas>u6^gHPC$kZRw
zK-pD&Ivv=tW$D#_gPE=WJs!*){j<x^%GEDZVxsc&>l`7PuRkgPDbVlef{8+XJFS_D
z^lRvqQLLBN!^0B2)*qx)?>7a>GW{mH0<Y<73Zb)Hf2|sT3jKQ8pI7Q%r}y4<{SZZn
zs%(0<XCYIqfAxDbYxMH@aJW{#upi`xzL6HCH}(H{fYj+_wCTU4_i2Ttdi~S1c4^Qz
zoI$HmKi?6~+}4MGjbS(G{pfOT)*qb(krw?r+EKUaf0lxGM}Ls=oOku-C@a^dw>>wF
zfwt@CQLLmxZ+aOroqEJ{a3ATv`U;|5`UmM~b?c2`7}|aP2?{Os=yN`TWG^mcsOi(M
zPR5w}^=0%vc%XNuBZUw3P0yfnK);|BtwH@PCm0&i%js1$te-sze@FE3w)a3s^;z`g
z<uSd134`PMzbnz2&@-K&ds44H3o@mzPJy;*{gt&aF{9^v0Hp^FOQO-~VCZdwQb$9;
zd+^Z7@Bt-~oeesAGPxMMrT}*}?EeXFyBVq+A$iE~Eaf8I4PI9$Ea738q~>A6nhqe2
z7&<<M?xTk1=xRA;xc(y$#|?sQP~&O%?It|*GK^7_+}mKHr?ij3=7K@^8d@oic*5}C
z|H{Y=8|XdaXSnGE3;u?HXE3Ay!vMXp0u5)DLNdfKdlN0oLJeCL=nXUcLCe^1!@^4F
zjxZF_!z9v>Lp4)ThPSD@GTM+v55F^p2#Tx67@mFz6R`$1Wtq<!`1?WP3^`Kxd(Kcv
zx9@pFS{mGrH*9zl$`TBpc><njxYP>^NrnYevvB`iFxaG!Nj6N-#xcd<M%ms}!yej-
zUo<?m5S^C{ZS;6gGu)#Rigbf}E9_o2EczY(UNLlV0LU-|--l0`hPZH;xM~=oaDJ8{
ziM~abZMaHd>KubRogB?IoK1q3JcEKtAZ+=DLK%7s40aTeE;O{$Q@+S>n#xg%4G%ex
zDKQMv$&gY*?HIf$Gc?d{@R}j^8;Fz}hRy>}VfdFeJC%lQQjqHg<rcVBWvKZFu2maC
zY4KfSP*RAr)}UVrEjJ9kbaULa84_t_UuT#S0eH)hL1#MZ4f_*-Z!qkk;`v6y)~(>R
z8YUOR;9Y|<A3n7iPKANjZWyKesKX$p;}e~R@F!v7p5ay6{dO5H(q~e;4P~=1!25<p
zdPqJr*wYEHLBpSP;SU*X3n@N6Y`8#awK2o{5is${@cmox?XiJFr{Kp8Pm=iwL$wP;
zCJiG4XiXWi!oiz1glq+wF&w97_Cez$O^JhX&knfeXk?9})5$nMs|IJ|(lHFl#n_S!
zFI<g@%^+^Z<+g)RddRr)B{=ME<kQB&!|0?2{;)CbG;|*^u2R97qsA#(pByv3Hx6yb
zjl&C|+tXM@?|Uy}(in)h@#=2CeT;FG7xpzOy3u*UnDGy^oHXj+z<B+PpU46CH$H8I
zg#hD&xi-vDpfQGq7GxCs0H=bDbK+qz#Q5GK;7=JxT4Cw5Q9^;2P-EiH=nONiISvwT
z9NB@+2;=G}pgYnys6#8tSP_dEjW$kGVbK|*>s)lk7*A=TI@WkvgmIoV7X1nmXPjO^
z_uo0=QU^GE-ng6(r{axre~<*@avpq2G*<fopJbe`N9P6OXdjd&8@D&We2Q@}5xi6*
zhk`N}jo+1ncgc8X6u2~_qdmMxHx6c_b=mm!4ot!oqbG%QuNpU5K(dUnf78jeY~wXP
z)Z`eyqN&L>HoIZ;dB&m;$mAQJrBeC=W9cv86&h`n_$xA&#zCamxZ!nlmKZfpptIC?
z{x5h~X59T1hIY+3i_V{x8!u$Se1$RSWB6NXOro8{bz?2Hs*E1b!9!cMG2<}Q)EL(W
zqFHM!UJk?!V=I+)-85!4LrtAAcogK8vCag^dgHuf;58T<E<jDA@rw$0c-zRFgI}`A
zn6MqZX5*2qn2Q$UkBty%HGXb_$Q@&23wU>pY)XQ(85doGy>^?i>jHG&Gd76fTbD70
z4!v|6Cl`Ww-#A7&z8+&WZDD$iy>x(}&v=<i<NA%8KZVExV{#tm;-T>+N-qr<uh8Mr
zL8JaVNDdkAQHjj3F)ak}5#wzNS&SN2k70twjP+U2^2li0{SrhU8(qlLabqt<ohOWc
zQrK$JSQHPXQ$~+rcrk5!pEfiz#@A{2d(bpR1wsy{m3`3dXnJQgT27{!80dC3tzQ9U
zE~eA{(Bf)(${k*~nd$=2dB~JRAAE2(1?`0)57Sm#G!TbP?^C4qh{?knYL1%zq{@b4
zrdk$S$4xP#Fz9KT@`QOW(;$Vgy-kOys>R0?Hv`?irj8N(FegkUV&G1izIhTl{Y~>I
zQ4(O<$bd+oDVP>CK_-9NS_Ye{(m+B?yPlz_$SG6lH(;JNeR3IyP}2cQ-iDbJ<>(AI
z-KJe=gy~!kIwMW8y8uL)=27k`+SK(W$QhG&4t$C+U8Rb%SkuNt0M41hgs^+wB=d)*
zc+<OK@HfG9h{{+JO%6|imt=}4rnK}0)BpX35hj~F10j=Q%A;rRCDTf80Mks;vlvXe
zX{sKh&oJ$v?PI2?_9|SvYWnt7@Ul$r(}kRE>iH9`9Mgw1hq)#ZMPc(yt1g3=Z(6Vf
zxB}B63SbnPuI&aXG98MUkNdCKw3Z@yC8mulAX;iVN14?!(_Jccxn|mY7k0}{3|in<
zn7+?OtI`xmMKRY+``!Sq%EX{|YqjY+ic{5?T<Kv@Yq~pt)(w-1j&j{Jg;92_&NSBo
z$y=u8U!knt<oO?3wg!_M)qOXbzLbO9HobiSzBQSaQ*lbOsf4yEEvC&>2-0eDpn}Fb
zrnJvN?wbAzfYLS-n~Pa%Hzm^9h7Qx-y#REYN_GK$&-4f7E4xe!)tK&X)AKaW`=%A|
zL$b&8=6$q!ZKhl*A?`CZorP2VruQkX@W8~Ted|M02pt0)F#SbOm_gHHI}Cfs#9j``
zVbg62+m4tv(hFqN#QYApG1JHn*nMO&eFNNMlak_r<0hZI7}<o$=Ueb5O<zl(Wy*9f
z4XtUDZ5{<&XH3hfqT-<W!98emGCzM4Kxgwqs!VV(zd%79S98J!NV=Iz>8*Ci+)l4E
zce6JoXgthIE@8S4n+NF0cEr3L=dI=*H48q3<S}#a)95^I9;QW>r}@=!Xz?;1rrI)Z
zbF__8&pu}H6`1ffuYVP4PMCL4$nvDwmzI2fX4OkD;csp`3dsO-_A#^q&2LkrC&--a
ziOyg%{@)sICv!4wtWTK@bZ?$E|15(@sQET!Tf@x1eFu?n^O8Bx8DW0c5#}S!T{*P>
zi!vX)2c^;Glqz^}#{4BMWn#?i2_Rz4b^n2P&fFIZ#Cdb`E(|-~%%Qkmg84H)Ok$$h
z)dwO;X5VEnf5AK}3?`Dzo|R~&nAg05Nw{b};DXLe<{$ULwKTJ*47hajDtr3o+hz0d
z2H-Qy*7@koG~dqx;;Pv#ALg^n9-o7kZ9YqB?HqG3#hdcYt=~YTz#NeSrG@4V*Wh-M
zdFKhVip|e`2|$VYz`G!&<_0^sU1t7E1AniX-`awam7AwS0Ix8M{*S^EmF9dq0I!>4
z=su`2f4C5cYV+E5;A_lnRY265lj?xKVGccs)=l#li{M(FIYf&Q-ZH;T^||$C9j&q&
z%zi8=Yc$W}pmp19ErY*J<^namZ#L&r`k}@A*95e*nnw=6knN6nmH{$t=H;`Yrrj+6
z7v!G#+*#=EGLKycqT77G0QmdnDcZO8m>->l?q0Kv@{WDxVID;K&ACm$JutsPnYV}L
z9khELFwca;?LjlQ3(7{!^XZ{GYHlinvN5v*-M5cy=4YwQ>9M(sCSlwhN9RN)%$v7k
zE+);#RsuL>j{g|IX*0(ej?S1b(7k!kvTqQ?(GvYU3_4ldIstIDY+L}JTr4Md0^n-N
zI{*`ImdC!Z;A#0s3F2kRKr!50Z%guai1=7+ORm76ujPY6m_K1Dr`lnE%Ttt*4X`}X
z1AL&xb_BYEEOGMy47SvM4#^P9A<9smvh1f!|7pv0I_?!}8SKIYg;^YFEf8+GMV|tV
zuq2c~OQdD$9CSumy6>Yi+G6nmJkio&TMvUtmY`!8XtKqz1%pYk)b51RRLgAIOJB6y
zqmaiX%X^DJ(kwM1IFoLPdI?G|TMl+(6jv;(C?b|&8E}P2riD`uXRcbtDQuf%8KtmZ
zw#A)_(sC^8DF~Zu5!3P}&ocjp5H#Pin1ZndmRMSf6j~$)p{B_4+(XP|u_cp|)FqZM
zsyi*UJU9e=nZ@x6c-Jh;{noCS{fe#X8HilB1XA{-%2G<MRa-`;VX($xp~q~k#l8W&
z8<u>^Zr!w;rL;+%rTIPZZduA{cT;Z}p>S1$rFtGZ8!Z=UpWJNeq~%<TCI24at(LQY
zgLlUw55@f4wL~9-FKw12+Y6xWmSuV9?XdhyIr2_R&%fxrXIXaybJ1nt(T=*?a+RJe
z_btEhKzc0w{pjqq{7c1^eU@%H4E9?(F2djgi<&AQA6mMb&>FA^KSpcNvi}|YN<)_Z
z<LDf=9BK!A#1eAG2H>dWTgpa^S+Wj-`N-1t5xjV8x%(Or<Cf$ajCaDqrA@=6<zEk&
zpR&BP0K92SBW)UHERFR2$b;5d>)@}0wJ`uKM=ReEB2HF^e}Hqge&d2p7wc+@fV)~_
zzQA0#S>K7G)V_!Ha2rN(*y?u&UL3KOZ3FPAwLBKUW7c`6AbQ+7N!xT!>)j+6^s<J1
z0^)5Qr5o1A8uAkWzSamnI!{>J`hYuW-9qO5tbOxf*WbG6d$=87T|}wwKx<$QctKW|
z59k>dY|WwHKEygiYpzq)d#fON+RCOBU#K<sf7xm4Q(o{Q+$vrNZ4uVR>A*)??dix{
zl=a0nj49fxy8^pstYy0}-7(gUwBC)i{!SsGvsTZY5Q(#X%|honYhepo=dFA4AZd%Y
z{`NY4g9PhvB6KHO_Z7l?lC@wHbYHNhd7?Af`XMcPQmmb{drh@gEyO4;TK{|>YA#um
z=pP!SSv?29OSdkrgTc$zi?iVU73=xy;AL2oe}!wA*0+6O=&Ci04qIng&r#8Bw#_Q|
z9NKcMfpj1=*Scsi%;#C>2SQE0^%;5_7FZ9?gPKBX*jG?fWPSWDbQfC#sIZ~LTA2pP
zQfpi)w3S)y)X;s+>fVH*m0Qmr0`9tXC57H<tSz)bt+fhYfEPEck+d+lX|<KJV6e{m
zHJ$yuWeumiZoM^O8`LydxAmgcXcfD_#BJ+6+9x+zmp{TJHd}}KA<|-9NKcPe>l`}0
zc*j~#g++I*cAk)Ivqo=%WV>}Mg#|jS%Qiz<r`1Lid(XOM3B2gCZu;MMW4o>FEkNA2
zmL!1mSeMNK>9xL-2p9XTfk{x)Z*{s3FCJLu(+%{{x=Ra716KR@Au?#4c^SMRYbiZv
zhOO7@U}?k}-iFqwwV#64W7ZeCp!1P6heFVgtt-}nH*QT^K>51~>*74fOj=)f7iy-g
zwH07aTa9;tn6YNjp7fyo<{1DT>|5`{Z%6y*DWL6Q??;7DuJ+<pAa3?=ZwBCyz0+;*
z-0h_?ARhLI=!-!|?d>NZa?Jiu3N;?Lzx@b2Z~LGq+C%%;S1m!)*WU4KOz8=GUJ67{
z+RuF+qJH*sGr$Y9|AG#p2HF2MAG~1uoBz+zb;o5{eQ~WQ(=5v}D=jNaO-m~qwzSM#
zEqnLgd%v#@ZM*^wrc6OuvWEhqOqntSL6N1h9VjXyA_4*e`um>WU*~i0J?DGQz3=nf
zan8BVdljIOj0G~ZMKLs#b#Rc8xCAWGjLmeQh+$lzI}x!Af11JL7!rCn;~BD_(6a=_
zf%RZXWE{iQB&SOfV_GYU$qWHG`BNCralv|sap6aF`!FMpZc(H%HY`T((-?~BSe()s
zN%W2#VGNZ6JA=Wbf4n}*Fuw_f#~4ABrk=_8sswUbj5k(;WHT6V;vvgnu<0kvWxP+z
zW*%b=4TAGHW1$8-`PfbYt$@)>Uh+c53$#HmVmwPrWHIBy3#cq%#N36%3C7-GkWxlw
zEJzvSho3;o87ncFxKuC(Dc*mQ@x?(@Rx%j3U}zQN+!!iPG2WqhwVLr4EhjaMcn-*E
zC*!;SANm<715jVf=xc$*S;jJY9qJhSp2DwP&-jGC$=Se|LkT{O40aycnivCrLd7}8
zI@;x&XDqKn*Df$VA&+u1qva7;S{N_2pskhhh`h#aj2-kzjdn)hWf;@Jm_@IBC&L-+
z1-maZ?$AE)3S;1TnApWw^eF_dGIGfkeU0&ePIKLimpUMSosm8bV{wD=8vPVE8J7sV
zhjFqED7P3Ea;^3<Hk%=En=y4M!1@?9R)F1MoKFW>KjRwR54p>zpzO5)MwOEVYwj_=
zKMgX-aD5%vLyY)xl!h5=DKp_d!<E8uBMj?u2#zw|Dnr-C7=E!J4;cFuP&m%GeHU^Q
zjLkQ}Im!5o4rdP;E9e_}j~K5%56&G-_{{MBFt<Ddd)=756gYEdu1=*NeJ3-H24feq
zW)ymNGZ)jzcn{M+Uy1Z!o}(wplez30NO&>l=b+7-`2=}me3)~{P3FsVCy&@(=AZFU
z;m7>$39$GxORmA*0Oq<FlmeN8*Ptkfd4Zfy!OX6`Ap4keCMdNugt`A5SVNh6DKU3H
zGg1j-4lqBV^FbJsPbu`_%)wWnB7)iH3YJJF<7<?nn2YYBbddSc_b?`!ncIxY80M!r
z5Qt@pqJR>|T;2$lL}n?uGm@Asbaqc>{y{(XVWupT-oI4lX1e{D#(bUTzzpUpTH22?
z&nCd`W6Zj@QJKk{Nk_{p<_en9vY9Vjh532RiN`>WGY7OF`OF8D+*QEbL!16W=5pFu
z7cqNj$5+e@rGQ@v)Bpdux6DsydM#yo{R(58Wz4t8Wna$x^;xi1Fn`()w3EznI@wk-
zC+?!His?>%-c!sGN~ox2-g$^$q=wmi3i79!uhQCjhN-5!!dm7Qiej8)Y92vF9dqt)
z&|A-}yo=s9Fkifa%0}k*FQS7@%n1VwJ?CWJK8MEh%$pRzzQEi-KAmP}4&7gGVJ;X&
zWh-;jYDly(3$LQBotaODb}$c>K(3RylLE;Xndkljxx}1%7V0lEWeI4z%2Z~-`fJSp
zXl?9f-gq0B*O~i&0=dDw9S5^-GMz4T9_nFc@KAe;sVApsFEfO~fVY{?)3nvc%v6Bo
z4)Zh}m;0F=8&SH;?5ja(fGLZC-h0eHwnNh(^E$a9hnO$W;dhvMpYl2GGcVDkJHlK*
zY0#t0Zz;ez#$0p&oDY~q&QoX{XRi1MLps51b^)1WuH6Fchs@vS!){krOgC8FSU<Fb
zxU;fX0ed&=i-+jw9#-tP0QF$K5DfuOR@w?+d$ClNX!B;}J_d0gRw3<cd|55@A(OqV
zpPmEpV}1S@?Dc0Yc$vKW0j%)XQ4C}~_B(#&AeIl^sR(8*Uja?~Si8C)AHw?dASy#y
z1AZX;S?B3%^9NXMN{}#C+Z0qrvR?WL>Z4dELxFja)#3?F(X6#}D2rh&Bo|98%eVj?
zjAISZ@h_hB27l`JQ(O{QY{~~oWX*pEJxpRfNBNA&tT*Xn7%43C2dF&6`ucsyA7<6=
z2T5gpc?>LRtXZFfC7o3fYF&Yo#2Iqm9Amvqm!30OBeY%5V)eVirfk;yY;fkV@cLl^
zV&y*r^?59D8Y+*oCU?X7e3p?M=mo4=E#wMW8>T@~5vwQ;EX6Ec4-70}h0sah1Zy5W
zxuvWpqEK1JdJqCq&PsK<0;U4kASYQf^1)iks^Y_#D%QWJP&&oxr@(hL>*s60u3<e+
z7mRCJYsqU{&*GE=w1JgJH^>@UYiZlt#G0;$+&NYs11iq5R@qQ_fo1oAKr_qZ9aOfk
zxU?9yvK(vaB+<djq<5^76;C-t7g^C1JiWx~e*=}5Svk`oafMY*q0}x`Gv!}iWhGOL
z>>BHbG5lKHtb=rK_9jbC>rW4BGwtJUvHt!M0)4Fhk3jCQ=7mCiKkKbv^yMCF*4NN5
z$htg_qTxfV@YUcMVR_Kas!`U>S%4X1J^39vI>Gv#z9%=yN+dtgLzeCzXmVvY$^qlX
zUJwIg+}VQL^l-D;w0+&fKDrNb9_*>~0cCGCdmP62u%&eU$Cv%=Oz8Dz_oV<OfL-$@
zeaAJBt$QA<``Db<!5YGTb^)+M*&oyN8pe)whhR9HF%#=%1bZW8s2ybYH=#0`J@ror
z#IQ@~t0?j8Og2gh?1>kkK9L<W1D!}=zkM5}L+oE2AcxtvD9bjTy=E%L;t2cM2$=26
zVCVY6s7&^EyI@on`xlzJv)RR;Ln4p;#dNeCXNP?RlF#lRhF}qU@C*ct*+an)C}D@@
z!k9Alj%;9;v!9`ud<DCMVq{h9(Vt=3DRy)OjHzaCpcvN~_U5HPInUnd2e}JQ_Vvf1
zu$ldI06iG&zr7*Y$`*u!r-S`23wk@*A>`4z$Tq}7;u1T9Vj-8={cE893VRdfz;?0!
zhy%IG4x(MdHFj+w#JkyJbd&2kd(;!98|-g>fp`zQp&q4M>^>Vfd)dyMAEEa)`v|#|
z`q-`q(d~XV?>+S5F8d)5dI#9*CSc!Vzf1?sL3Xqql|$_7OCdMH{*m0SqwIG^0XoJW
z3xW6q+mHp$N%oI_K;c97U7C+~aCq&IbLGsYU8oyp9YsytISwa9f_8E)Z$`IwbAELJ
z&mPWNTG>4~f^R`QIZx0R8@xCp8_^kW&U!k%`f$n)z+PXD;9ZFC<#>}*-;c8<4aA=#
zUk57!IB$FcmOzef4KxLDLO(@YFbCfc!n4MC{Q*o1;f&@xp*NIMVF20Baiaj|0nUSE
zXbj_gxf`sJoZl9KL~#l)L;XR{H!0|EEXP3});P|!S0ES9`FAA@P2w;&K~plP`Uu)m
zI4Tc-rE=2g23Q(rm@WvXbC#_E%2Cd)jWGKdrzD$_q%t}GP#i6X)35?0ms7GHFnOHK
zH2V~A8Y$zlkP{OJi6Tz@bzq<1{6wy|Qcjcz#*}f|T`?plIgiMJSIOz3_r8j=hB9JL
zab6yP71f-l>G)W~X`<KnG-s|2U}rd^a11+LYB>Rk&~%m~SPGsxPR{p0tLNP3!HPzX
zhz`L`oPq>cagL**q=)mIvA01ka28RrZZqeA8geb1UwpvX#u1Pe?VKl{gm?$1!~`ok
zIr}I;a*=b2Ty~c@p>#I8%&}8|(s_k*^jlcd#gUwXimRM-nklYvzNP+la}N81+~jPb
z6qO#%VgXd#;+&PC+kKo@X}^4j^AfH4{hVDcP;r;DiMD|QoUO}1?s10bdgUO8u>>qb
zoVFRzFw9xUK;?bT$8Q5=#L1cRJ?JRsx7{FPoFBKMPY*bo{z7S-bDlz}6C5esU!CN9
zQ3>-Oa?Vn;^bzO6cQAAZ_gyV|;mZB^7Kj@+g(fI>ZaRg-c5?Z2cG$(8q}-C-+;~bp
z-NXI#d0={Q%ddgOlj}UY71WEXUI$ih?kACe@!?MU9ai{qKVJjZz1)eXpx%%B7JXR9
zpWD_3(*n4UUIPi_`aA+?5ck#<ump3Nr4ZQ1ow@=fg!@4fP(ryXiY4yn)=|F80dC1V
z7^g69T?N#JbJb2?z(jDvD8VO^D^0@CL~(zm5c@&y+_z8}&F!SS-Z9(<8_<hbuJTWS
z#&HX-0xh2FL+9KCuG=w`61m&0up){37kN07xxdn^mBL*p#i$?R7F(e3Fn5fez*KJh
z04meCN4}u<FP*!q7}!U+KhuTT4DJ9e^hdcFl*e_9JA+n`OzuuPV`Xs{#-c5kn@+1s
z9@jSz<T$tc2vG95t7y_K;BKmh^@Ut7GPH<W@g$&&x%u<Z&l2wU^x~c1-Z=}-QtpCX
z^gkYD++}paE$6<l4y+a2*-wGzBzGMoT`IYm_fT2IeW42KPjL&#3slYB_zci$xa}W9
z?lgA|rNW-!-rWMuTJ9T}AZNLra+p@ft<;0Fo_kXW%m!{bIfxp$Ptq^h#Le15|Ko9v
z`!k)q&U3F{LhS|a0xpK8nft5@N-f;}@6r2KZr2wmwQ;wv1X?>cklgtl+;zW0Qzy6D
z7dBnyc5egA74FLv=;-2JqJzv;Zp<WDu5lMrW@$Hf-w9M+=U#mroHw{R<d$>Z<n}K>
zV-NS^onXDijXI3lUhbZ?sJzWJ{)<8A<GxPU7w&Msq}X^rH;h6mce(G-qBy{v9}UiX
zT!|WH4{~EE_&LPAU5+6c=DrjH)9!OiY40<_z0?Q2quk89D2;K|6fJ$=<UT?3`Z)K^
zKS3tAZ)zbp$(_Rh=tJ(D&p;k=2Pvgz2k*iLD0Jn`2*Z%L@tpLdyYq@A5ZK9kNZW;7
zyiJtCu$xynh)(R`ecBD1Jb1InLF>tTKy#QEZ@LcR-n@U$LEMMu94v-}FK>4`H0|Y0
z9|nvc&$$kj{=5|$^f!QKx(|s!Ucyr-1@R7jhdu@K_TZw1%RZj_w*U>{RWTtR%G*K*
z-2J?zM`7pz-gZh83gf+DhK1ogV<uQ4ct3<dLnN=7au=d_1}D5ZE(dv|+rb*md;SOn
zV|bbL&8=8o7z3p^-q3GgiRW==fh6!MLZKp&XPyrEBp&-+kVCv&9#kCWo%jhVQh9&U
zN2`wTYF|RPGkBdJ!rr62e`u?i#~UsLO99VoF;EJ5+n%M9d=c-$36NsmK{`8>@IGGx
za)KAM3ZSJtZ}J+K@e)1(Dd&B437{u=5tmS^<h@o03#)h+(jb0{H}5%AR`Y!NF<dpg
z<$Q3S;Z00OUut<<cA$f2dE2f)eI2j6A8qx#4b>ElYv9H2L@ye7Z%}BWiT5>y{m=29
zqBF~R-p}iy;sWoPU`RCco)3hI7T(mwP}s`LUjno?-d_=DYv(Pc_pgIj-3049c|F%r
zy2$IMT)0a-9&Hyc^R`z2^9t|d0$A9^>&Nfvbh*mQqZs)$-WmGUx_J?_ce>6~?Lp}V
zZ%Z5mZ}J*~Ako8%r?b*+-rG}QVIPl~3eG#c<clEvJfB>cc9*x}B)|rEKhQSx9<P7`
zV1vA#cfc~lTeuOG!#w{6RNm)_RS<BF@P2s<Mvd~cbQN+8Xz1Dlp6V;880U4qfyxQq
z$9<@r<P`(~<{@v`2jmfNImz$fA7VqHJ3ose96R}SwCmW#m(U`<n}6vQwC&-aroRmL
z;CIqm?#Vwy^P3lc$y$tzx04_7F*Nz`11N~%%il*ar@j0&>mlgJf1ciSfBrX=Y!Sdu
zo(K6r{@o`a5X28{17|S*B@q<v<G(>i{}8?_y&R$Z&&dz5pMU%-2pr(2kUt=dKP?@Y
z;ry@3_Z7hxghM=%?_5hx`e=Sc8ipo@-$pA)EPn=t%o6x}w}T||-=_NmNqkSrBRRz9
zr-S7%ztRM`RKC|OU?1VH>Of@%|1#Y_ILe=!3=6aP3uwQb&HpA9!=1w)c^Vq>`2O=i
zj`JVB3h{h?l5-1G6!5puIiZl>Oiy4jzwv!Emhi6~L+J#cNqMSe{B;8`xSW4v4L~dS
z733c~$?si)%1VAT{aUB^8cLS0=0D>Gdu#YlMnmrz{-LcX)$-L}LGCO+T?dvr{#FJs
z>-n3f(filP@4XM!CjKT0JD%e|yaBZH{N^H*F7Tz~_HE|h`3aS6d=urZwDaHJ4%0gL
zKMjJVlb=X>FY;&a0=dLrNe7b4{Dmj+`(ELXQfQ)!|2oa*xA=avbL-{j^nl#v&zqq2
zuaCcE0)lt=@FU;}=1VAMHNelBhtfTMd^I{c#IHFF`4Rr>bk%2+{}!D+#`sS1FF)XS
zH==Evf0PopCiwg4&_2n3Vmj16<bU!3?0v*fr&NR;f+l*_Tm>I2g@BvjRS9|0b_+^q
zk=i5pfsI-Z!CUm0cnX5a7v&}J+)q!bz)EpSA3^S8FveF<N?!840{0^rgdl<OZIEC=
z@oVVlKEakLP#7X8pnz<sAb1d%`vp0a)qg;cLkF2KK?4O%!v&kzKygM3jI@V|5%_)u
z5-adVW`j$dU@z^*;swDCz)le4QUokfz`6_-NrI^wkYqu37c`{_#OGmex*&vNM@Iy1
zZ$n{*U@jZ>9u<_*7WJ55b~0Ep1;wW!mn9gw39xKI&J5_wa|#wd15L*Tm+7WozJPxm
zjRk@=n*dWNSpNfHiUi_cP+2Uv;R}`$LG3Z1oe(5k1zM?KDMkOw1kAV4RxWsI43(z@
zS>zF}7WA7TUL#mui2j}y{5u={JtNqu2UxA(Kbo1&3Y;@3`Jhg4mo6{Y3+h{dc3yDj
zJ)m6>j9o!xvtS1u;93L;bV0FIaD`mhZGtVMkZTvzQV_C3aH<t5It50Gj&%t>*aS^i
z1<Pocbxq(J2(WHJZxhIMLDO#_Hv~^zh7~sj(M~yNkKn~#sJJDVq+ou(V3;cJ3OaTH
zdqCh$-)OieC?SX3pdfq{b`J@DUk-s`!Llvjye|l)WU>*#6SOuy5V*}mX<YDrF>IO;
z6w<D4Qt-kL0DCCdy&No$1S2;9wnI2`HF?rpg|E>yXE$Lu#pv9HYsA3bDGdJ)WS7uF
zDLG!kg-IxR3xg>j<s+Q74xGNi4DuuH6+Sftg?_>XH2L`p-I8E$fbj7?j76Yu;#(*T
z75<(Jx&6X8n!FAOiw*%SOjsXAp6qbpQA*K{5HiUZ6)AN29r97aYB^LK6u$ZsdJ!)S
zrAIG8_$EDii9(mF(3B($p)U_53xDZ?c#7~xCCDM+tx=#H7FN=<lPa`~1MH~KLAUOY
z2}fdKZ>Dg>1#MZvr~0Ph{mT}<G7CI8!m@8sn=9lB0Fx(d_W|~C;X(4;7YfhiLcT~i
zzaOPy;WXM>mk536w#W(L`C~A&RG7CPhL#CmrVDrFLKS_NwL<t!1^RnZ_$9^rD}|wS
z52i}^m>!&Gggq8iI%|bZBhY(RIAb<y>xA2M&{QuBp`As8u!Ew!jly;-R5S_GPXe?>
zxXc%ztwMhas<#P6cEGd?i|Lw4hj5t^V4cE<`)Io;oJ+g2OTy162y#v6M$Y4I;aN{q
zUKfTRrU%g}jQ;@irf^O!KzoFhltOV!_)Qh$dxhaYg4`9hQF6$DkW2Te?+Ld~$8Ze_
zAERi(kZ=Y)<io;syJ5wB;bGcCj0nRUf$~6@O75R=;ks2I6T-dZ+?W(Lkz4Pfa4jDw
zkAzMEogepzT=qeQhbSQp@}8nXiV=8;w(NmIZ;`MY@;)N@A7Jqnjng8rSERWJPCt<&
z37Y&x?QJLph>FGl7ARUBkNyUUD(NH=EILcB;C-TIS`<S?S5kqwU$i|4C<jFUIK5zZ
zm}rX)^5LR3dgLQTY?@}HMAIp6?VzZGKA{sMiaG_DSkWhPfX0aexu}d6Y3b;bAbM#o
zNV15v6mlt|rYG@S91<<29p_<DqzRa*qQWo;q=~LBLS?#W1#Qreh#vd@|D$DyUR#J>
z9231tTgFUL&`yvnk$MpXvqgWACm=^uMfZerMe;H9;<(7g0+xJH&fm~mAhLx3yHNCj
z4%kJaC&{l+EZVjf<6I(IdKosI5WUunwo=i*w2vzjz3GqfEf=}2qioCyQ3vH=ofLJ`
z^IR!PpkK5~H1i?^Pl*D^(^@Su9fN$0=mNRrPm5OcfaQ$nb|qM9MMqY``m>_{Xtz@*
zQceX}y(pZ1rY6zUPS|@+v}qPt&WpYw&(Z}^J3YY7qQrh$|5`-9y@p=2iDopQv0b#W
z2OaGYEt&x76um@Wvb!ic{xQfU(FARjuZRxQd8$h^lajNpiVWQ-b&DQ_LDO~7Qywtw
zhR8n&#@rOu4gtDH^mi`WZi!}4)?BY>%}U7iiG1jVbKViPU4cZus4fxe?}~2FyfGm9
z;2-b|iXPEUc}S#v1!PzhkqVakqHA-Ya71*He*00;Gw)&$#zh^UKyE^mx(#xZqR9r3
zhoaZ%{^}!<#T()~#0lh<a21;ZV2qpC90>t;r}$0s9`6*3X~o+m)+eBGw|I3o8uy4@
z>5DoZ;uIQuPw_>X7`?=s$kXaAUQR2mkND+H7#Uyjwn514758)i%ujrjqRal`O_X&P
zApZ0-kU;Tf6;Oi2&w0S!VDZzF(6CSJbWlJlM4S}^5-Q%c61DrqU#QT-1LCFh{gp8B
z%o>nz@pt45iV$}>023+B_zEOS{Gkuz4vK^Rzl#+|e1{>45!XjUMXdN~CQ5PQMEdAr
zy!a1#Ruja(Y=NPP;@RYbP7=>>(tXfF;w^7L#bI$g9obUFE*xN|iEsM?J6)Vd2i+s$
z_&30rAwItuojEH0G6*oo#JrbbQ>OTbr-7X%Ud#Yzw)mg>Xv-0Aq)&L{iVMiCo+ti<
zg6hY`ELV(LzBu(hzzW38-&35YP+WZ-Fh$}(JsOL}kI@;TM7)m9Oee%o(~nmwKK?aS
zl!@282$phj*-K!l5I;1a?WFkEG;mgmBPjEuN}R+7_9<}|eR`l;{46Df)rbpeCOs|w
zoaXa0;_)xQQY#)=PMJ*gV(XW%qCtG<Q<&c<#)#m}5vR`tIVYavf%Uxjd?UyOu{i-S
z&Eli<<F$ytCs${yIE`FsZQ|G$F{JHcO(NPl#AlX3pi>-2bN)rKU<fRi#DBaAdoPRM
z3&;3g5!Zh?1@B*%IL`|bSH)B52f8Lc77x3-#e@E+ye_`+|LZN{&{Jr;C4MCbg1zEo
zN|?DVo=sueKJgDb0D4FKhBr*RD}Mi5h!2R%$zyU)oIoL&LGeBMFu;&_#yzwRi$gv`
z<%qcISxh(1QSrOeVB(m#@jeFOfp|T6AjZYJ9jKfTfA$$vJQTl2L90jN1adI%kbDyW
z;wD)o1*p5^!?h^wlzdD(>|K%@bY*R~BsK!#9+J0eKs+V=loRSDDgO<F;4N{dBpx5h
z`A<Q7os#d4Lf%jE-%JSlOPp(=FhIh19+iQTzn_CdkmO~0yn-e3$cYsq86>|^sAPyD
zcKan$DE%cul1it^NXhYEQ5hv!k_~}_5)pauq9twQHj0(}MaSMa3EWS39VDYQ085ZK
z7ySUiL`lUt)Fw%eQNm}kWHYT!ha}@Us5~rjsR2x?q<aMNX%h1+w53Zn9)x^`WYu#R
z{G*bDXJP0uNiB6WQ<6u?*jbVgJ%%J(5>H3?9Em3fEXO5rbcW8CxKpsUK=QehT(pG}
z-DeOil7zIQR3iCfJ#0E5S^O4AsbtuR$}-6%@`jd6zI*}L6_OXK&{iqwV*{p2(#C}N
zDalNVdsIu*6ws}a1iuf3rzLh1#A_vMC~@Vi<S%+->LizG5^9hf-{=HSqvQw5w`-ET
zPU(&3Bon_v{=8&2<*zhL4Cm0_7D)kxj$0)^J_2cz%%<~SyTl}f!Vbw^E{wS-d4fJF
zeMwSkM%!gc7%j0^Bv~{QcS#!7gY&B703|$kOO{dU(sjwuD*8z54atl<DE3Oe`4)n=
zCDBvR!#>GW6|A@;d5vz1^h=&0htGf{yBKKqBsbqeX;AW}24qMw9tfL;B|~(l=)UB!
zda#U0=8$u8O!CSn=;#B<wdF8vT++D^WI_@||I#!mX+2K+&qtEkt6|g*>9tmv=qmMa
zg%xhnI7<C+mo7_1?{`W+rXKE+j!+=kLmC|e6`s;>Lc!uC^(6O#x3u{q5FhCsIuiRz
z-@6Nzz0x=7a-5%ZJ|$)POIZ}Q50J_mVOpTnizY^AkaVLTXs~qR6j=93chlXK5NSJk
zH$tViCSclr={>rOe?Z#$J}Sec&-S9f;Zo1}P#7Vd+l5l3w9plOijum01QiFRuTkJT
zT6!cDZ86fPDUm)_x`5W*IO*K8Ao0?CN;FMyN`<roOOz&2j!TlXb|F+GOJA@<B1P)<
zHY`0Pjrt7cAC~%7fHPJ4B)$G=(jRDpo-Qq*y~Gh|MjbklAswenrbnf!A0co|YVZSQ
zrZoEtaArw2{|vBP>1-OqJZZHUoX4fkee`Y@N*m~#K}FJaZYUK?k5NpeR62vcn^Y#9
zMrm2)()UJSccrwGHl<b4<8=BxB~?(~%xP)MtI%{tTKNT3)Jor>4R5{l4+=duNM}-T
ztx@`AJx1odlt)LO3)190C^bv}aBhKon>5WAJnd59>mVJ{`!rCOq(%yPUzU!LbLEOu
zPad@{X{QSWu1f3aX5uyJhqTG-md>T*l<U$b7olr6q`%bz<)*ZSHex-}8FL}mEA>i*
zy|<;QA3>l`>Pfz{J5s)Z*1vw~7qn&!NDKak!h2HgOOP0p?sy)cL((7UL@+Fs^r7v(
z^sPV8HX`lX475?{CzL@vCjE{aMGvG=9<XU#+SdWh3F+JKK+~l3Dn)c2N)2`3d?ZcY
zj<y}LY<H-4l}%qy@jo}&^WEUtCEFYYg}Y^5x6u1Nve(W*g@=qa0&Gv&G8rnpWaWQ>
z(_3aJ0jG~F&JAdLWm&XI^OHSB-ZFogKNp$;WbSmoF;Lb_hr%G)z{_9>mMPAI?2|30
z_kF+YNH?v22V@zvqY0Dkxekd)nGWd|E>W^tN;W<yt3Ck|En7qhdNH!=^pwQOzMO_q
zyll%Q$R)@My-`Y({rwHvl4P@Jp-+~rO+YC{7DGt{hh$=MEFYFFrn7sh?4uzFWXs}c
zmUiaII%vn5D+|%0Hc$4`0Q!4e*18Tb`7&2ZQZA4+JP%EUvK4fcD3UFF3Z-IMFr8#d
zWPT=)6SBb=pp?qKATLgttb!81%4KiRY+E5?z5vXVvQNCAzEbv|0xVTB3GG`?Ic1M1
zA+cJvbrjar$Zlmq@U%?X4;5!*V}p>Wm3^*7<yl#6HY}`@y`2TldKvEyDjQ@~lup?w
z+eS%$=Vhxugun$EGZuz6%iJeW*(O^}b4j~QlK_DZ*)x<q&?(Dr1K35GbJ=OgUy`kv
z3c)VfGn9gORW|iabo-iY)d)zptnhKjUzZ)oh5QZKQ5uVzvN&3YdSq@bAh%>+eS#kL
z%8t?7bXyilpX2M3HT{U+?vCsjMKAkhEABwyU0L+6C=JM@E`Yu#yYD2>LD>dx=pB;r
zOTjZNTSCcQ_hr{=(KaHRGYt}>vR7$?FeY115$Ff9@@Z%rmo+M&X+l;;;loK;?c?a$
zLz(y^kVmq$lm@dyK2rm6SGjis%yyHXv!TshUPeQ*Q~r4my??vpVtUnf%aygzyGMS5
zgGvv1Fuh!!@<GZO_LA3JfeLT=LO)dc$Pdx&0AG23HPH6TS5a&~Kt3xRpn>uR`c^`a
zyp|kW!SWl2V8uT9T?(Uz$bGj0I#mAOIOO)rf7$DT_wRr_emja`@_Cdv6E2U6hQSf?
z)`eh=lpBwtElU11Z9EUky(q*OE$>f-y)p9Bv{1*&C6sm$CqLK@74h=!IG`lRf2I70
zB>8jX6-k!IN1!rA9?%7rL-MqLA$M4=*hyc5NRyYjKw-N4E=5s}$kXZYeoU@8fKsOX
zKbp(3<Rbb-v*l0hKq*K5xjPi*%FF2cQh9RcBs3kDXVZF}FMomZWDDfGr4T5TpZo)y
zMe;&Q$10XTN#TGJ`T0+w?}Xf!)&pm$d`}u`%j5y{affpG?TsK6@|r~S@T7c61B|JZ
zhX#RE$?Iv^KP6A2b6B;!g3^U*<l;ZTd0M_E9>$!JZ?6PPt$d^gD$dGl_d#!+{FzN4
z_3}izNY)_tz72s!dFOU;HYw!~+QE8GZlDvzdHInLlv?EDCBSZ#NB!UFEniH&opyQG
zSyXn&TTg&=$`_H-?V@}RP3V{84``abEMHFhlPmJbaR_wDXPpJhHTlfY2sXaE(s%}K
zcjYU72j_r1oi0?~lbhdwF@y4zNe~#4|NJD37?y9T1<QST7<uqU<ZEd{9Fx1d(StAl
zm;;n?d3zbuPRKO|R8Gnz<Su$B51`wbkK~_UMWw5vmJT^?ic2&jxhve9baL9QIC~SC
z_9!^RARdae4HyJZ#h#bJ<E4lcfp{x=I$)ZQVrf2%@l`zC2++NXDU?j(r`SM_@Bl?4
zCHV#_n$E-eAccj#86K<{ypOhhiY3i}4pH>x0wq*2bqPub6z+wz(+pE&(X$$^*h=XN
z5sJ-v*d3`*(1d(Y@ly(hD_XIo33kUSiaB73Q>YK1GG4)Mhl(V{Y!1Ye6|azMCPmRj
zUWsFhG`ek-shIyU<gyfH^U<Yjg(t0vIf@IE)tIZ8uKoYLJH=Lt5fmsYd8jQ^{5KOO
z7AbCi57uHugB_qHiYa>NJ)xNXD-@P0o}@gXGR1p$AXl!q^(zD_6#8E1J*n_|9s*U0
zFJFSdDaER1!C9?XM;`1N#aeQ2pH^%;0?xCF)sNHXxat&v6oIZ+tSf<u4GQMhKx<UA
z&<fk6u#y+`oZ>qQl$=-W{|SN@6i(XgG%JqMP39KGS1sUdRqQ^AL1<HmC_ve+h^I|Q
zhvMh!u&`6{d@JNGDwtn^TvE)ZW65QOo)T=FR}?*;0<BANAQ_sjDn6%O;WdSg!U5fi
z{S+R)uGl*TeY&A|@_k_6R6KtTf<1~KsO^?w!$a8Hs}Rrxaa-Zhh`#hG{-%_TJBp9)
zqq1Ldv<&2~;`2JR4JhVz0_C0}ksNV@PKBLZB}0mz!+|!ea2-eKzM{7bjU$TPbSYs}
z@dHhIV~XGz5PYC0G6HQ}A+kZmgd&u3h$a>PQRd`B#cy;Vc%;x#WMzkP)p4}BDPMa9
z*6&i5)A4P$avS~1dzAg;Z}m_*hj<Y5RCbap%u8vUi$-tdz4MUpQBJ4pQohPH^yKeV
z3MebYPkAv7D*Tn(mqRW<>F5AVpi)Z9Nsuz0T#ez%wbjrYp=_WW<4EOS8_^b}R3Am<
zL8Uz((9y~XDU69xYX1LI#wz>hE=HU(;tu5Fl_?)VFhSW&LDxj(TzdVJl#P_}m8{I7
zOo|j`ln?@kl-+lLc33%;Jcp^ue!8rjrj+=@!gS?7luC3&`O+zHW+*pJ1=vw#4J9%i
zQzorNWu|gr0=<7($~APl$yOer`7uYC{t)uH%CCH2OrCO-ZoeN_4$)Pee5IZ^3zTL5
z0=rPT>Ti%DWdY6A#mbJSz*3^TWCuB+9H-y4RGC5PSY^t+KcN%l%J(LLS)mNofaRp}
z=Mefk$Vz3w*I+%Re3q^zRVzOvKUIyg<x}WAt^Da-Sa?SHB^g|+e0L27;jEIe0%&#0
z)qkS0UYXnp6%EP{egtV$PG5=2CZ!*(u;-NH-@)EyWekPpTa@3B1EN*=15Ffd%6_Ck
zIbGV76%pX+P*x4VicV$e3J6|QwvwyklG2s}D=sUa#7@ZNigF1BnY)y$$q{~4nGy)O
zYs!_h>F-wlOrDnO%1v~-xuJZ<3n(|08aJ@?D8GLJX5Uig(N>^Wnf3+RZYvM`2;%Hh
z9w7JY9cB3^kndN1L0;dx%B!@g98i8mDTMcwYsniqs2rnLW=QFwL))<O$<-LA`^srQ
zgN!KWQD)Dmaxd-C#*`nD<Klrb_BW7mWj$p~PAE4%f)$fWeh*L{D&Ml9^vJ2yUqs^$
zRrYJJ&0RGs3lck3=h6YQOLdzzLLMqHW%hWgIy0fkOZCHJ5cE|gGC=mKf+(Err>b8M
z7Jn5y!FVfFA5wBxpz7^GKnJOoDo_em)$9h@r#eL+q6<+yOB=sXmD9Ey#r-Pw8n7Nv
zwT^>?sea1>Ot?x!lYNA0-a8<XsyVcIk5Y-}0Op`-F*ygLRcq&?6r+l#*lnz8f@Zcj
zRR}G7@v7FxKoV5nQ7AJ}<$V@iN>WM5MUt%QrYnVqRc|_ffElT(cXk0LO?851y$n?)
zJ#$A@Gim>KOeG~JU#9BMGbm-LhJOWUw#xh#Dsxnd7h!0ws^e8u=Baiiq4K!uz&`-X
zS5>bDbb)GR9WV=3!=Iy6q*^5fDORP@;k86{&E1JnKcQMd&Y)7&%k(yusbVh!rd)Nh
z2bC47&SaQ>QnmCV+A39F(0ApkQ~@u;m{Y3X-^5Q@t*YAyv>H`5&C;h;{X0>4M&(6g
zQLFlk@{-P~e#wR222}!`xEfX0Ww5D971>31#?GnyXF~qG>iPL-yrBBf2o<d=MHYI|
zrkXzomF+4u-DT=g{T>I<TdH<0)c2|!6e7Q^T20GYpX&WQsK28cK8Y^%s|M(j=v~zq
zov#N}<8&|io~o0~9#ru!p>0U@4yHM$%do026e{kk+RDK?qAEQP^G8+3Zh&V@)lJ8u
z2dYJ10ef7<K97-^P_3keU{Y0)0l6LOCw;-`s(z{ndfn8kqR=&WwO;}%cdGx{53)-g
zG#diD)xT~7%N}(uWiWZD{ni88>8ZZ`9*SP-d`hVIR!=7fm5<so23BA7DhdJZRUe{R
z&rkg`d7b>#uPlTW0qQ(Te+g7;>0t>{|0e-Tu=+hZ$m~-up#>yF-Ape|sCv<Cu<TdA
zNP&t2>Tf>-N|?Gv4GrN=_1hA_M5xCPq8O>JE=4IyebWzu2i0jbPe!ZX76CLy-Oom4
zta=tbP;u%#n^B5aZ>MN_g8C}GKZ$A+t!hc?^xODhlGWjKWJytnJqDIT>YGmh`mp)}
z<-n$@SJI9=P3?>$r%bwf4NV_M)N{!xnxXEcBjQmtzJG@oKwbU}NTzxrx%{%!o9SB=
z*=kohOy;O}tOr`IdKCqf^3;ECL=TUvzik0_zWVABkODQIE^id7e_ITcBDMd|5HD7*
zptw+pI>kvBxKF6%NvJJV|NSXI%haF!4N|U_cY#!>8|e^xQtf>ZJ*-skfl)41Y7a_Q
zJf*Hp0Zg?zm_CzOqwZ{gF{jlz<)}QP{+x!pR-I3N?RvE$4W$P4Gnptgs{gwRuqO4A
zC!A1mPCc8Z;`8dVk0F0S-S;6Xo7F2)(BBsIL%L4Ts;;Ix5pC)fF~DwDUp$4%4s|E(
z)jHMfa*Xpubsl|~=8F0kx;W6Ke&KPjTvhwN0I+N7IEoN<tM|==+1J%g-=fr`KKdSc
zT5hS|qHOnGbq<~M?x-bnitJYl$ft8x?JGmupxR8iF+=KHx~MU%{>KVq?yG0qhP@-|
z{p-;-s{ZyBl*ZJXeSrNy{VJs(jjPw61j>YZA!VOVs#S|&(?j*2RS<Zjo`Y;7r^^n_
zi65ZXRpUcGZ#T_haviv9{OGpiPK};}A7+mxid>BznhO^o=&9L2dl(<h)8vQn)%b;=
za<AqiCdB<T*}0JO*K}n-AV9O9@-YH6Z`Z@@AWa?}Hi9*K--0pwH1~KAcZO){Y0nm_
zX`p9kzb55<G#=2jJpgE!CiWIe;hMH3uqi@wYZBOzn(Hed7_B+Mhl&`@+?^1Q)x5bK
z9Zk@5)03a5LDnhW1C8G+XiL`o<_6PJG^^*JbV&2qWt0wU!d`_ys#9YyK~tKhW*7RD
zuCWfG@rdT_zfj81cq_njRI`RQ5yvzW<lN8H_<aeIrRkxmKU?zx?XYt+res)nToXxN
z)O^hl3;iw7WYGDoOye&^&&oA(8i7)w(Nad<NliR`t)^1rOr?!Nm1avb1W##J{RxHD
zn%WN_SflZy{Myr+%@nLUqv?MF61AH35nws1DcA~9r%BukP4$|YbQ)~X^i}}7QL`=+
zq)FpXNsbpZF_aeEtckw}lorj3vuJD8d_XajHqDbxdUo11i^xCSq2auV+D^?ld0{VV
z3c>(-MKg};mM&eI)sZm&swOG|oYyoHbj6`tbDMt3>za9#gK$Ih4-L>wO=BTSJsRQb
z;JmHL-3qxrO%oUWyrWr5!H9m%*W|3et7%(6@85vtYXNHSY2yEcZG#$FD-;fC`ZvPv
z5lwLzDn~V|z5^N4OwwHTKy#Nq-!iV5UIFzJn(^ZhpVR~tf;`l$Q={^c<_!uPx@l$K
zLW8^Z1Df-9YQO8nAneh;vIA`%+9_|)`Oj0kgpxCTv@w&g)K@z~ui9Si0|`n2+VxQ=
z1!_Ndh&}~rcTvzaM7wo5+CsITY=lkwwXcwqFI@XIWfw<iZ_|Pqsh#fyh4I=8MhGNm
zRab$MsLiWDDM@Rf*iEwbuMGM-f)wqigFri^UFi;^4r@PM2-Z~XtTI%lX*beAH(fh@
zGt?i^`p{>WGPJB;!E#hPNVyZowDI?$K2!T-Gt_5k$LWxjt=;|=<Z`tC&t%Wl`mcn-
zJZ<!8s6VdV6pFTdZH5T~&H`=L-vBMtPS8h-i?sglLB3eq=mYahv=4}!&^A%vpi~<Y
zg#j+tCMKg)p`Dxtn@(zL$;(}-eQ6PFs?t``Y<Wtnr9g1C_VNhCYqT#?z~Hp@NGJr(
zX#XSUUafXlDD<6mY8Sl?+v>Fb^wGC^?TOvMZqR-xhJ2%T<A0E7(*BqOm~+|=H>hvc
z+IvvhqE$zOvlWKI-VSZ(TBzvMO35F0QJY7cSG4QCgE3v&EXrfNs+~)BPp)b2eT-7K
z_P2PTT-Q2B$Wzm!P5TVwmexV%^j__6D=|=aw4vnO@7KCpAb3~HwW4i6+a3$k?rBFq
zK--`;BMFuFwc~U`9nr=u0U6bHlEZRb+nxzc6IvMsn<ll-J_dVt=w?!vTy_8ahBh}{
zl=CDk-KBe<K7X`ZcZKq<_vm)sN6ABHsRN9sZhZn+ymX(EUoAi<q&%NM-H<CtknS1s
z*9Pl49>My3x=r+0hv;%?-y5ove2f9!uM<(8>H*!-sVIf%c9SO{T$l6`jET@al|>u;
zNL`XAtclY7z6yc|byMF&W3+Cm6vo8pH2Xkeb<SpB$La1Tp)FolMMvTUT?!>jCF*>b
zP?4llcA_m=H;?>?DLU;tXgj2PJ_>pd>z*d(NUE-G8VpU-RZfGVbX`_8McR+(9)Azm
z8M<2X#~;;=(wB6O>0IfuOQx=RKT27;FDb~CtxKU#istB2Z=#f|>#YJ>p6*aE(2na~
zse~2zx|&F+FVH<sUwALnt*V1~kuHi{vc<ZiOTbd1TS!TcCv-8b6zMC~{bWRKnQl2f
z*5$ed{wP)GrdUxrsmq}0vQl@*8>K4UT-t-2(#@wBXtnO$Q>d)beYP2ur*&a0{Ag!%
z)8k-vtuBee=x23z$wOMFtEQBzdfko?l$vzQDX?-*_a}Kpoac3}rGRPCRUJTWtIqZt
zNSp4NYp}ah_wDyE=Atfe2Lvza&M8sZrF-fXpk37|?a+Ho=iLs4H*|h<2)?QNp5hKY
zx;_fO-_pHt04%*Q8{)ThW_q>zbV(n9<&N$mog(|4x(W)s-_>={uQs3y`~W}2JzXKC
z)(q*kKZ9Nj>k4SXxUZ|>LGOreGXwIYx>xB)J*Ip4YY05h^-*@mxbDYgXq(W9RH&TP
z4SU1-hq@Q(_j#lfe1ZP%&?{@v=BoF<he|iSGmzE=cfF+=WT$@aWprkjemDS)yY+v4
z541h{t#mB%&~KQElBfQJ6vlYz=h=bnt)F!spg#KNY0mf6M?D9!SAReX)BN;b=0VP1
zU#bIVfZh^=%0T^@A5jX@vsQpJSpSFfb=2<Dm(o?R5PceXMML#FDCD(Y|5hH1IiUY*
zI#|N=r{9Hz;d)CE)JN#sDBKdM-*OIyM(M+6z_f$<2lO&W>(8x%-WdHN546SVBUr$U
z)3+`JiPt}%3wsIrFMbAeqMlhr?_ZKWmuySc2h&8AqCedSO^5WC=yY{hFQ*A3RloZ$
zkTm^ESAd<a-@G0$NAxGAf-^&}ABQnV^#O7S9MhYB0a&Jf#<PIV(k~-7ezyM70T`2`
zpH7a5T)mujS9$v1&d}e19M|(G3m{+rB4sBR=zER;v`}wY1)d_kFU3%c^{rpS{1Uw{
zc|K0)*V3JeQvFi;nacFa_aI)bFQ&Yv3VjT@Ur*}SK7~@H{xKueSLxrQuWFsr$BSTE
zwf>D&5U9~#!8zIKa$3KRy!vPK-I)-q)!(M&?5sW^6xen8*Oow2qkc;~Dx37IFHt(D
zpWBPldHp8J`Msd8d>UxY`qfLJuth(`gtk_F(Tf0U)7w}OXxA_Fhu#kTrqi&#Q=d)g
z5f}A4=##q6OZsb++<aMoS_POZ`YE)#>(VFB1<X~w+yMD&dcS0}b?bX*`Ms`R>I1<W
z`td(ex~ZR}oU|VOAVo25=@<Th0q)h$^oHDReNQYj_38J22bMefRlkCzU%!-cEbr=H
zOa$kEQ~$99wfFSz(UrMD{mZ^!9n!x{)7`K>kxu0I^|QjjGNSjHiMCOFCY>n8^!zK3
zf1uyG2b|;juW5%pp`SyS>n8Qy^sU#2`UnZy9_fQ00(ys`UV%zi!-6g7*-pd16g=5w
zaHi={yW3zM0NG<utVFGcA%zrr8Z28O=w*0f9Srt1xXl8Kk6~L5Dt!&f^fvD`jIRNj
zpP`yQ6z^~NqXTUL20wDx1R8V{APF*5k%uVQ(D)~Yd7ojh5nT!~d`^MyP(zKA4W9jm
zhvbnvV2Jq+D#8p0AE6X(n4Sv~VfccAbCHI?UmzG|XtF@yprPUzDx(d5lIK6h@FAsY
z#Tp7oJkGH7dzcn)n0^hV1j7f5(UxeKq~lnUVR08wk`3>yLuHB~qMQ6LhYX*63u_J=
z(*H$cs^K_2Y-xr{BYyOB!<=TQIAWMj4z3KtANgR(G|WB;`7A?-4Jxt?1^p=H7|xN|
zxrP>ZSeR#cEE_1t4J&6sAm8xK9Fz(S1Hk|*G)T5UpvZ7%4(&gS4eFy9no`4jx_ee;
z*f9m5<%Uy_U{j@`{|-u3hNN7uoH9(EfpI=<NTkfIGX^tx0Ba3wI#$&iqREHVVCbR*
zpGL!vAA+<Qd|Xl4Zn%>Lg&l@XMF8tGc-)5EMZ-}zKAbL>3~B4=1u#6zfTdRqJ{0%p
zGQ3T@!mEZlI)h&`gwu4_ZP-d#$=40fQS#6YL+p95+%#z4hoL=&RpeH@WpLJ@t=F*0
z3ca@ty_65!XZV+*CwC0rJdMhJL*|o^yKAVWTT{*fgLE3`J;Mz0dJP&jz6F>e!<*N@
zGi>0EqVm3>SOb_5!-Wgr95=i|58{NOt`#hkhBxVh5f2T8lzi~WFufWAJB-)7&|g>M
zKPS-_H{(i*bM7{_(Q>rM_{M6;c^ESffW^~kETJXG%UDFNY;U9c<52Ho)X<5~*T`T%
zp`Ver4#eLWKa9!%qpcLbZ=kWS6fi-?L?z^cje=sd?K94bg{BZ=%}KC?8b5j;ZTpQb
zzkq}pXCSfGCEWOU2`r2-Zl}{iq|rI88%9MLQ*L5}qK&KQzD0~tK*yU{qih$9i8mUu
zAedn6r3huB@h4i`l8x8G0h40<))OOh$oMNcj}IF=C^<6K`21~@ju`Flpp;>>kr(!;
z@f(^Zj~Sm=qcYR@wi+y1#_yc;u4EfGP?R^vIMEN*T;sF>l=6++N6^Cp<4fIOEi}Hk
z0Gvg}mY+b1jq}n`Sz<iD4WK8CeH+k;Qsb-3fn8?Y0l&ISxp9gBZ576pe)Q#}aW*-x
zDvefJ?yHPTH=ym5amsb_s#F^jDXdmwbfaFJHo9yE+F9dL3M|zbZyy4wH)c`_Q-kpX
zE94uEalb>p$+(`peCLepQdFKdZZSaog0Y8kLYs{Pv`1_)c9RvY#&ZQ|Yd3mM0a%Ce
zjSH}_(|GM^@_$}5zDE(#OUCvi;JIw{zKhZo;~Fb?x{Tjnhxu2H9{#ZKn(>MZn!1fK
zqo}-Y466sr4dd(-$lWyl`3^{r@t3`*yk+d8<8rTYXgN4<8@I-wt<PBTB1(6R#j&ud
z-?$k5bf?Qb<NRI}2aOMvkQg#f9)$W4<4!uYj~X2}(2FtSk`F;17?*`%5XOx$%g{Dq
zT<Cz@BV#RnVQ`1(^YvhHHNhW;{gmnB4XE5{YK}&KcbR68Q*^f}n;xq@rXmhX9;Qol
zKz4eXzJ350FVp!yAmMEqrNzR>^c=-teNBd!0P1h*B<Ey+X%Xcv1)7#<AQ)tNjB=iW
zO|R44&3&eLH=u-=u6zZBp{7gp%<VUg)3*75iA8fsnCb2pFgx7z9X-_%CTSOpiFBGi
zPX=g|=@UKV51RZR2T!z#y#Nw1CVxtQi8ZxTs3Fee{Rv2tDT8uTl1-U*aHg1^LlD*F
zkZBwF&JLSq)#GPMHF?sd<uudsT2!W+j7uPQ#Ps}rkPOqRJg^)!O>F}7F_ZJe6`*CB
zrqH=H%On^8$u>RzI!KObycj&WrmsIhFY-)vbYcFuX%6KV<(pPgeo%pF;0d%9n%d97
ziXu}G?JSB-tYpZQnC86!a>8UThQd-)wFdT<nZBO~&T`YU^H5n~8gyzg&L>TEbd;zx
zouymARi?k=0CUQ8X&Dq&o7~^T0M(erhCxo7o)m-gj48PXoVBKmTBtZ{dL{&Db*6+W
zkb2WMw6r&vru4wVM$^+1;A}Dt(Y$=l)OHOh=S|UX!I%rCMMm0xHk;Pgg0z@^ri8>+
z(`VnK)MlDRmbRN7(JbF#%AnnBr)e9x=PsJI(uJc-rhDE{aoP0G7+9{D)>3*>m+1%v
z$*!7SrCH#*DSaR0ZkTq@LEBB!_mscYV=7fa?v|<f4f@hcuSr@5iQA?(7oxv?rjIwF
z@s4Rt8#>x=;*)douIV8y)B~m~bam~X$&FII22CyWRt%XUD9|}#dh9iDj+(x?2e2{I
zHgZWlFqujHxak=>nogMdPC$Ip^ic?md1w-TOg9}KnO;~3qjs39>1TE|cm0A9ax?#O
z1U&BM!B~`bn&;<3aF02CDJnh8hjJj`X`W5}^)j1+pu*c6NH>&x%(;A6;cLE2Yt&wI
z#CIt9ne!F{#oxTx0-FNNH)_!qXl{NCC1;S?ZvuLQ&CiU0XP-HoJb)qQ`}3e8)I3bv
z=l$jn>3bOm%pNPy-!St(lsg!1ZhjUDBh1CLM~pPT^Dag$${hLvY>F{=QSN)Jc^}QB
zapnL5i#Pv$9xMsw$x#efqWR}YSdrv3KTf;vWV4yxzZCQOx50DBtf_;h!{!OP;go8A
zpN=PKW)?*w(#<ExOORoXqSMh)^SLOLj+sCI3x;NzchGI1Eb{~naJG5VPPFBiKWzcY
zHCybkDbL(E9Vo}mTRLD<zS;RMMTUyZs^_q=DK-z^Ky8V6a~$k0GfTIDl$*aKUsi>A
zo)H~AX>K2eib``cZTIp20eNUUWe%h-(^Q-JW|&=L9<PL^)8;>oAZN@i<m;$4=d1+S
zS+fT{<8|gUbSAAgw>k45(O?dvwADuQQZ3XsnUB-w4bGWkC}-rn`ObW_T`;%Oal6^P
znXVDFm=7&NTdVof#~7eC^S1Y(qTO8kBl^-|UivbyJI&@PAQ#QM8L;<~`Du6Py=>k|
z8CzG(HVSZdnN!zLPQg{PtPhRX%=7#}y3O*P&~(EbrGVf~^H(&7_Lv{h>T=8MO{;0I
zc>!ITzHJuL&9^?Y{{>XuF<01OeZP5veAjo)`EwyRV7~D&x_!@FMHyRz<_nZiF=W0^
zWZ1mHK=Jqc=3glkHDdlF51^yw1J9sOW9CJ4?tEajQ6kj1`M)86PM9<QLFJ@*Rys62
zG$-E$_9Jte8iww$>_|qXtEHbDpKg}7mVndU@?{U8cUoR)0`xA+oqHI{-Ikoi=;t2G
zY8L(Pf`{d?8nAj=Dq^9@%hEF&Jl>WYH$i+X{=Y%c*K&G4$X?6WC1CNhj5R}rzomrY
zGy#^tD`*R}T+~5*kfnugr3PCf3xK)LA}6Oxh~>f#REAolnGo1-nWP-n1D3db_zj$4
zmX+i-4!30Iqcahf;V}qCT9lMV7G;@D;jM!f#cr@hTjnf)e2iu3UYH+inM%oBah5g#
zSmG^<w}B*Bg6M`tqGk3Ca3)zEr`T<><&X%NDHc0L+z(kc&`)^SV!nmSRHtRZ5O~ro
zr5ga6Zi)U2<cQ^GniDcCE_=~-)N=YT2Jx6BpNqCki){kfS(a&(dY@}C(_)@y8G8Wi
z<Cbk{z|OZkPOhZ_%RRb&RA@;e=VXy3g9g9Y!l4Yc5{rb6H76|24PihlwOk5>HD#6q
zpP^K4d55-|6_(l<s6T00eiE#emPxvwQe`>13fQMCl^!TnTN1^PtFa_eCe&%m#tpFP
zjAdH}NUbH6{Fi4f3FOPIv*gbMO1<TokI>d&*-pP!qh+b{6cjdDnq$y-&QePY$$5*(
zjLHj^t(4u>Y?;ytg)Nrpm1t|VETIX#&GN?~bhO>_%?pt0u;fRf)M<G@j+2X)=ej{I
zSzaP<*=0)xMH8-A64WrX%TgW*o32_)rNF#q>D*20U$-TM&T7{!rQbls4a?R8XuN5e
z<e=1J`7RwSw=9!|VCl8o_6N*u%hRPO^;tL+T)$(9T#v!;xAeEb-n*94$1%VIme1%Z
zyJxY@MrqKp@i0n5mdoP+8@42!gW2~jU*4lk&k@TFKKe9j$(ReCG0V0~Q2)SE@d)b2
zEkkqxXToxe{I-*puFs+3p{2+hoR2I|_Q04O*5Nc*;c9K-!6rBBw*S!PZcQY&?M|zR
zcCmY`cZ$H`VYMy;@w7hFz+NwFV?6m^ysdw7VWN+<^Ci^!S*4NS@wZ;5=`z5&U=!Mc
zt%U;Ew9lIV2|z=v+-6jUTHm#R?6=lX5axhYy#*x9`iPRP!maOo3S%OyOWy#Aw1$p>
zGs?Pq4_FRbU4KVkVy#{j?{~&o|M3S;ymhP|DiW;U_(ML?+Cq5_N!EjU@Eo$L=^%C3
z8om@Tsn)%pq3wuu^9U+4tfuQI9ku5E3+ycGD)Js>TVJ8%p&YCKaj@iCKcW40p49|@
zugh_3`6O8KtzS?8pkSHRm-4a-t&!x`D6&35H~osO?+7u7CDvLBI+a;{4A5I{jR>8!
z0~wpaQ5c}p)^<8XpRoo9K}D_AIS9_P*1BfM)meS$#8+=^r5UEd`oJ5dMk|93g-zD)
ztmxo5>qb2)&s%G@LtnEsS&E;j#rg&9_*$(ww2ZY`FHrcs-I^%@XNNUx1ah6$VCOd|
zUbNnqK;n|s>q~UzvQ<FtuB+C~>!ALc^;t>+@3y|02Me!TchSRk!^)>5gqzmo3b5R=
z-k?21uk{^zs&8ALplwQ@busNI?pQzCipqYgM+8i}Yc=de=Lf7^<P*JTUAl~7SA*8?
zTVc(RweT=X!`5AYfakuooP0tf)}+@^8np&z1MPv;oes$3)&M#?OjtW9ZD-PYoUV>N
zw7#?qm5;3R>2kmhn}ZS&U2Sg%qteZ`;vZDH+x`v#*=c)78^>L?8S^P(zS|b%3Hd!X
zFFGc8*nUbupS*3t4ygCBy|Mx}`P#hy?~<}zr~PAqO&1BhfwtOWs0gy<)4UvPd%6gv
zeYS$%QQB_{n+lc#HWwR8VYU%+QiR(iqv%V7ZQ?N6B5k?L=-XsbwjXzc=b%k%f!=7_
zdHRw;jLn0x_F`?1)9M{(Yu*C+c-xuR(3u3=WjZ1z+CH2Cv?N;#WlkpBwilu;#a2xh
zB~oqoDaM^<tIoqXr`zQ834kNEnRLj>umzHH@u=<g7>F~=_APmsvTcjW0g_|;H4Z=5
zaa%vFc=<Mu2^dpg`(_Rl7TOxfNnd2ElR!nWZS^*Qme`)4PpX};#ZZ8y)TXV26=k;j
zacC>IIgX%IVH3@U_(|LA?hvoE@o9Fivi<c0+D<ubZf`<GwQXAx<ZEmOij$tU#gKd9
zjP3GIz^=7P96&p3t5-sz&gMqmy?WdGz2I!Hnd#`$Xgk?~Qj_g3I=x=7Rno4z*>>;&
z`qE<aBM)4wZAl<1+iZLNz}apSB|t-m%{loIBsy(b<XXCDEBOa#mu$yrxG&q*)uZx?
z&G8>9yKGx8Lh!0B<rZwZX4{nrv~Jrjnl`T6j9-KEhHddxly2JIt3|2D=6wY{yJb5#
z3*GLurH!E5x9N|Z@N(E(!%@0p^LOTfwci#`c_?>nt~3YUv(2B0#zET%<)IAO96Z1b
z+af6I{JzaZXVMXyW&(X0wN-xsfic^3ddJ3XHUEH2*pAXOGih7@A_N}VQt3AOBirya
zDB59PunCo}_BroD&fR{|n^vry_W7k~++{aYR@iR)nnW10$6iGN9xwZghfwmi*Sdkz
z$8M#~ov%G59-w>efq!8T{Oli21*gA#HD!7R*dsTiEzo|P9O6OtSn^#5+s`b7hJE(G
zkApMB?&%54P<vM*-A&(bUqNYx2kiIgI$W6D*o1C}+w)dJBEp_p4@)EM|NR2fqU@I%
zKn~g)4nscLUKjwIV(h!L0FAXrz6<d<dlvat;_bKA0VTn1p~)-J{(1pWlI(Ahb3WPr
z*L29G*x&i!u_;?z4%ti2z{E6rG=*u??Yv-MAF=Oz4y6qH`^Qi^YOj13EXV9G(#A2{
z&Z9>+$G-Xh{w@1p725LbQ~!Ya<MyD?fnE6IYuyIeRAiU+LA=<0HVCA|?oPMFPS~&4
zK)lSZC09kcz4bX@R@gr-glQ-3D<V)?X|M1FXO;ax2FNM9+Yjh<wfzM;c%8OSrK8dr
z`;9hm*4lYrpz^H!4+X^Q?7?*FsouWMN!B;mjpe9qv|s)VJWcj4+Pj>yZ!w~D-p-DN
z*%$1*UYOl%7f^_x#okTc;#T{X4H)}2`?pU)yxl&$9i<NY!Lz{ZwC|x8=c4@%<*Qw?
zM^9jwFWX-wSMU`(o08zV?5Eu+(e$dFL+PK_?Q)vBZ`i$jA#u~bVFl1`*&lw2Qm-95
zTf7zatA9g%pZzW!2=3TZ=x6G;&lN%8UHi(5z#gy%*8=mNUGN)N2JI%g?>A(hN4}h4
zd&>@x`*!~q(6do{{8S1AkJ-Pk$H+dg|LFqOaeE@|T_)_yeu4Z$`)B0;cw}EkKhq9}
zZz<HfI^;Z<=H~Fs0_RT0r@av0<v5%QmfembTH^LN7S4et4@VpwWj!79=rbr@j^}B+
z>+P6L&x4Oci-*(c;_FyJ|3k3X(L$4upJT<hApVYG23P|ef%J+7I$TzRCCIUb+|$91
zKk0VZKF6MeAR&&YX@3#sSlkB^?#PM;iEuni6KbU6J<3mya`bG3_(8{OEf9}(oL&da
z7{~rZv^irPtrWV7bF8XFpAsBR^k5`9<_CZ^$uZIlE0P_De*<fZ<2O3>9&*%|q3y6^
z<5~1D)seLrXlai7PeDB0QA(GcGaMHwi|nZ5zig0Wj?;_q!(=)hd;-oa$A$F(%XWBW
zp)JSh5K#Oe*I}$gG0*YQF2EdjJoO&1^BvxlK~>~f^#kOK9jYdf630}Ud`>uO=~_#v
z<4`K(${aT-&#v52^E<>V9HjxkJn3kly<w%pg$2D;j^F8K-zmrE^ks@_2Uc7xBM#@Z
z-ym_?@sRS}&Nvp(W~tWUc^jp(jw9n}t8=_aTY`EFFwhztzI1|VbS&zCe3RqFt>8T8
z82Sm==N+ZAa9wcd=_JtXXr&!Ni^J>#mR85ndjM;5O!*#$wmYu956linlhXw-osMbr
z=w5cb7lg(uj<+a}<bN!E2Ut|s^S1Xc3+%G6uzT;_2E-T>V~c6VmZ&kBXriVWqsA7a
zCTfg@T@~AcARR<R5m7+_1(aR|1q)440qI!iz1T&-^1bu>{?C)g$(%Fu&YZKioHH}$
z(&#Xjik+GqR(D|5n;jgjV7J8~U>(NW>JaINd2Vx<J_C~N4#GvKcQ|-c1x2Sr5Ej_t
zE{8X?*y(mSNu|a;4txH$$Z~jnA9f!)WV`{&BZuX~ji8Smdg%jRPaG~#w)LsQE(+^C
zbNKfh6rVeM+zikc4x_a&*yk{v2J_P44s8be9fmK5`2mOg7Jv>qcu?B^m4j0yL|!|*
zyApkG95%$D@vXx!DWIM7vSC1R*1OXOl=tcX9ZP{Y7yaLVq19Et?h}aa*KeX2iJM+T
zQB+U;TgudV>Al{E7vB1~<!JQLFQ?KaUwt%PvVQuvWgrLiVi_jSUvG8=-XGLQ(;G5C
z?-v5@kp8MA1{kRSy$p?q^>WIJ9nsIl`_?E9(!ci==If~b>91%F)^BhHIi?>m0+vGb
zs~iD(T;E1TQYZ8o-=XoOKA{d=sQz=REDzI<pylT&{S%5aoz_=V2rFDK9E4<qenlDP
zB2qt70`837kGwdmPo$EKDE$R`W*ejRDmow%s~^1$Y@Gh~Uckib|E4`hg1(&UC=>OY
zQZd3Ly-f+GG+CcbE14Ai%s0SJ)z>tFOV|Ig6DBhB8ylf_K_9#ddYSqFy5q9+agPCg
zQE#9p=_UO;(_t@LUtvIFj!|zH33^!{Msb%b`c+iHaaDgH1Txq35(<{*>Q^jAUx9wt
zLo^oZeSd^A*Y!QW!tPD|db(9^={M5S^tOHsUEQVn$yZ_Nj{fy5D3s}KC|p~qZ&?e4
zD*eA?zFL1U3<@=R<G=SnYxS@00Q9cDvkx+L`n0JqSg)T!6;KWOr3itG8};JP(AT6N
zvJ+gh-axDU7X9!Kq1UQUqPmqfef(~ac725wK6U7?QPQ+izX|z9ahHB=7ACe^@7WEJ
z9{rMHkY0VG(F>Ly>fg|+;gP<28caOa`z?WsPxKMAf_kdIGX|EP>AU6w?YVvw?SWtD
zchTwHKK+<lSbC{nNe27%A6enIAJCg8gAD3_{|t?<^h4f<h1Ys1B@y4~r%{Uhtv+}G
zI46V0DI@GU8+Kg)yU(zfa$PQlbtBQ}YVb*bzPsTv?G`)?Cw_-{Ps7K{Vb{y>r4M}a
zHWX7$w~wL66vWq1K<iyUL(DU92Mms;(DOH(q=524L+Bjn1sJx``NTtpcY2{7X!zET
z3Na2F9@47gh+)wp=m#05q+|3)4V!71A8hER9p*8^f^={phGAPFa@<fwvGNm!$@DFX
zlLnjlAfX0@FR;T5E%gvNWf;~Bl+%W$T(})>nD!G$gdx%dD3JymS2%OVu(F&2ac2#;
zMnONup#B$LoHK;l0p`46w<$DY4IACS#TiWAVlLthL6mVzG=%Md`6NS#Jz$azB{wm`
z6vNykh@=|!wZLwMVbwbz7Yw!E!kJ9N!Zs*m8GNk4T{N_;0_G(HPuUt{wqXLr%ySGw
zUjzHHVfKEs<{BI*qnc;PEC-iwINt`e0>fxpix(QC_n>gy5JoxB8-{<VB%sJJTnA@v
z8V+B>AZ{5{dMFedxW7P34EYqVDK#u!3`g%6rWT>G%wR>ARfW-DZGzTH!?I?$Uu6*Q
z1zNS?BwYzLhOZ8St2JbrLgTK%;vY!fH~hH<+yle+v{S4zWPc2<-Y|{sss_WDNwCyt
zI2r;knhcSp@TtX66$(qOhWTQUHiI1%aI_l~bm?>$j5vmho5Wy4(bq16e<2L^8(L}h
zUK`5OAoJF+<uWYo+vfHTu=j5Zd;|rLZ8aqz-rELN!BM|$PE@oPw(Z6}Ov$-zzq9}>
zVcS3F=!e<%-W`Z!Z2OD8hLW}Iqt5`Ay=`I{$dzrAjI^oC+jhnUqc7UF{~%!QZu4<K
zXUDdErEuoywpgm97~J-@6+XFaccV?H`}WE-^c~nfcpV0Vx6h?;-l^@bmQau0?hpYk
zar;bDn9th2fCpIa_Io2>zHs~cuOL#gy?HdaitTypjF367W6e7-5wasO7&8>U!+9pK
z6L;kAL}S{Ho_#>e-m!iQU<!9^u0mhQj;pkVsNHeM10u~kPEnCZ`;L#)aP9GqhV3x%
za!1=2n66hlS}dTx&v8mU#_8o~djO5Tj_vd$4R8$aq)(0<cKniRra~Ou_d`Fzv4F~Z
zqZ~N}ES-0JP2b^)cTA^{Y?5Q<0Z67genrolG{@&{P)K(?&!aEHaWb7mx#YNx_VwA0
zm9H?u%Z_We!~7M;FOHz^s^f1@K(0B)|BZ3xI?6CIqd3p;sx4&l9UWiN3_14GuI#$w
z6#63rMUEfSI^(9}SKp%Xmg65g;nQu$8MI?7c3e$2e5vCCiUHqo^c{=7GRMmlI4O5L
z{U1E6bPO^@W0m7#iY`<;hKoRI9M4m@wb5}az0Hg*jwcZU7$U}h*BB&qfWef9!@ml~
zEDa7-F?n}Li}{Yu+uUV(M?vd8b58@2I%WzFu7UZE4lcJaC0aE0GK<nNo<8O&y%U_+
zRgXYC*&ufeB!Kn9vEKg~6NXa>(R;>y3E+n}xWd%?A5ysTgD+{BIiiaKdy~q%(L33H
zI(nyUm<04MBRAsTuhx2@cj{rvSWcV&H-60Nujc{oYX=ejosmQ3GT&ULqVJi%Qt9@r
zfn`AcRz<my?;bQjcec+fXw6X??a=-GX?i~WFziPt%v}(T*_k)C4=wXI+{gd_Xit^!
zKW(IMs{HIg8-ZW0(A539H4p6zN@;cb+n8|xUHGj7Kz~oA;=)BdJs%cFtI@J#+Y;#h
zu`&+wOAphT>t*9Uh5YicU@C-PvC{)hE0YW1%Bn(o`v3JP4YRdcVh@EiNq*>EdqP0_
z-|Rd1|9=dWw%Q$Y9{=uVzNV5>H)a;)%-xwhx+FcAGWyf!o{V)d?0PXDCj!}<`F1)y
z@?n;|fy2Jc_Cf$2lrXbmpjgku2R#bJc6bKGg9aH3Yr<ybAA`8DyFLS`J6o2E>GNRM
zIsw#^ZK7+@i%orr5qPuLDJ18^T2fW1FY8(Z6USMOa$qOe_cKAxvaS@=iehKahTUlP
zfgFZn*d>1g>>SI`>9O<dLnB?;vFw->V8^j#nJ^g7Do;TsfsJbfb|QO&7Bxxibjlhh
zvo8i<H-&wdP8p@K2^3XIXHVq7QU?389l%mWD<~M2Cd%ugKG97BFf&A>=ra}<L_hVQ
zF;g^)qMKQwpSII-{Gw<&<!CO6L}jp)E$X`g6FH)Z+W~V~^msj7yCQNBLGh|6WCSc-
z6Rlnig<KIsd&WGGYY4FOMUO^9q(Ib}0PI51XAa=5i-ybr*bUJ^Iz>_>lFR_PDH@>c
z>n+iNeyR(*Eh?l<MX~4_WxYy7qp5VJRMbFw>^q`V%Epw5GHJ_OF8Y%)L=~b+s-dbB
z-TMV5szkr80I3#L(WO!&>c0zvwW1YYL*cGykZSSoiEL>9eP0we9~K^nv~<JOiNbNF
z(kQMM^#;RIgJ{SB=r@W=>6d8|eWn6w7M*VdOp7R#cFe7!H}}D{iC#)!uwC@QD(H2H
zIwu0OQzZ9=dY7nVBe1(gg`3dVBicY8e(DuvQvULxD4I%79*GKRd-qt>_X#G!_(U|E
zN|B$6DmJ3^nJ6t34nG&oq|&4pBJmXT^@$e5!R|}ZR5}RJFRB@Y!2!`$stO+z-5v@U
zCzH~h`0bocq_oUTFma}{S&1fl4Zut?Dar&&vdNl>P)ITP^&wDFP53&Xq!~@(`q7$h
z;&=siGfXxH!^L8g(HYP$F-hr#VyVf{n-INYvXqXU-80D<hN0azVM-y{VlsFGXssqo
zKY~Js$+l$>=`?vxZo7+bQ`o^n%%6r&p5nzk9Q6@@x*ikjE8gmlMtlL}p%e5Eh<~O#
zE>t{pF*GiS)w4k|#j$N5S>k<k!(J4}-+}%m@qAk6Ws7HQgozySbW?b7Sv)x(cCUy(
zCV#JqgTH`>xnc`CW05C5O@&qY;#G^FULf{wM_-}%%>c|^7q2o>NdAUcM<MwKre|o_
zb*6g@0aI_f{{pxM)0i>PZ#1o;*G-e@Oq%Xy)1UjG&|>=E4EnW9|Dq!zFHBd;(D&B#
z586>VnH5(<-P!C~4ZPTA)<k(KZ?pH?F(e<erH9byYxZEg5#IQjCDKC8-)!Zl7|cPl
zR4NDyFq@qRF3`-9o@|HB{OJvR#B4o9hl0$asm?LP?AP5O$IUKLP3;M@(I-H{&CDno
zmSSc{JHb@5pZ0*HnZ-~^V!D~`GR?198Wmz@nc2>#aMVS!a;hi2WL7&3erKDd(|2ui
z%mQt}6`1`?tFJ;cYq}k-n>7Xk?S|Rh$!IJxd({J&TV@7lsNXiT{RN}1GK=QmcC}dt
zEo5uV{_BF>TC-7iFr)X(woqm8eX}{V5Po1bZs`!*e|2W9A%JNx+eKmMMzh`Vz-~6X
zH5o81X16J*)@G*4fJVES6&2NXn(d%9ez)1o*^ulpE29TvuUXPCc(KoX*eZB`)I5%k
zj|7|7)5`gnd1MT@5c9S44U*&LNe5`U%rhc@VmxWCr<6;mdGjNPhMCtmLMGh&Fnz`&
z!h9apR79Gm7o+iv`8tXzM43140*N+n`Wi4X=Ift=J7=Cx2V&2gJN*WfRP(g)@FLCJ
zn$8Dgm~W)F(gpLEIl#;`|A?-HEc4+MKE7l$51?0Ww)xZ;bmo}%?FZ;(^P&$hQCG~r
z(}KHZKC>EVx#rI(>y>A&b^}_z`PT2CP-uRg4u)Shca(wLF!!2=zMJNKR3v)KTutYt
zZ<}A*1g^vU2RdQWY2Hu_uG_qW_8UFs#`g;G!}gkoKLB}XK7?L%kIk3SL9r+1@+ycv
zGasb2*mLuW`{3S~e@E}Ax8^M+(07uktRd+v`6V09?2~*=(MlId!7!k>N_r2&r~Q)c
z^w4#a>^DQByX1=n(DRT?8-oG*OZttwA#+eNiEhV3680Hn0ws1EK#oZ6?So>F#Dr?w
z<0Xe_pOhe3KySPx$rxMoB}?9=Em4YOk|(%SNi)SF(j=wh;BUG_O20^kMEn%<dqGlF
z1iP7%vd2)!k`&Oo<)Xy0j>5s0BppxSezqiq_B1(?ahsukSz=-igI6Tq(K`OBL~{uu
z*ChYZ)-hMIiRu>eBzE(FoiCYn5`6`dH58pKl>A8RqwA8VTOfHuQu`;siX`)Y1i2~k
zr;Pt?$=rH~6iX~6bpMq|ww?o8spQAsVg8QfZ#_iIB%8d@SS~TOg=mGufi8hc$@(Uc
zYDp7S9oI+(Xjfb-sixw9yOLk1P~x7%^ep_nFY)*Y<{wC={{q+QB)ch^TrXKz3CRY@
zE7}e>O7^)?maj?j6OZ4bS(3E`q(!oXiVIpLW;CWYNfa&l+9mG|0ceNhOR8o#D2=CD
z!~p4niBLEu{k#L9A<}>PF|^~-({wENgmjt-`a-2KQvntx&83~fY3YT{AmP#hDnpHs
zhUtJ}jFfKnLhD&+C2d`!q!)){*wNC6^&m0QqpJaWUb<i;`r@R!{{vdQw4f6vGNqqB
zf@@jQKWD(FOVT>Jpt7a^>;h=MbT5_T6ic6kfh&>zNn7+%>9YR?iKNSI(N`ut`~~#N
zjnWqvfL0-0n2hmON}~!e!BtYxS=g<X7Sc|#QM#ET-Az&_S^zdnbAAEWBAx9BgRRmi
zdLOh&hbmyHU0PlXw>zZ4CxP81UAqR2-O{<V_UVycq;OKNwEhU7A4)IY#8@6ljh%ro
z_*gogjwd{kzM{y+Qz>&5*w3WD(c$ms(xTfC>61>ObmmLxIx1x8m-fF0Za|txLCZnu
zsMR2^q|w)*{#x2Vo4z+v?M`rSrLk)O?PMWX!!>7%cRmK$XYrEu87>wxjqAX=TD)%x
zgZnLV^Dt3v79S@<-`%2^wnJVPVf4d#TQt$hK_81Lw6O8B=-C7AfW<cY9GbsHe>55o
zT6|91_W%per@%gB(YFv>poPR4>L)Df_Fyb0Ef!FWH`F5iJV=;@k0WgdPFsBY6l}Of
zApQ0c78%RIHCTN64DR<?d_sY1C)ub~kaU*K4TZsdvWoNMzO3v8L|kRf)o^sbtaB0c
zJY}Cgf{2%F@1O9{Tejv;VEV{5uY-c0te;}72V`MCVw?wMtum?$3y{gEhWUuh{uX|<
zAld$3(Roxh!2tJzWk1kkD@67SRka?MrP1pBgv^V=b|+;U=RzS&7EOt+Q!<-j&^s;j
z{0f%BWfv*)7%7|Z8ye5Zlz|XAE8F`${Ed>;P6bJlmEmD+6er6Vtdhkkvd#11cdG0g
zdby>^#*Bwzy6oqb5Y3R)QHfusER^o_EZJqs2WHDmW<l?=Z2muJyds;h9wMc(O;oad
zN49JP43^21bmXsGcD5c|g=~>4z$#^d<WrUGIz4ra^|BEIU>jt{*XV4N9rA~0lk67`
zFfFpP8!*rg*<Vc{ow9|mA=xFne+lNhWj|6e(nDD!Eh!$!Cj5ZD$1<z;@H0J;4X1F$
z3)%X=LHcAHDYEcVR`xMa`ep6c;pl)Y{5lK`8f6b{;KnQ2zbt0<wXBym7QU9#DU0Q2
zDWX)~0n0hBK>RIFE<oc!%b4dN0hW<;obZrkc{R)jTKdvmaoAF=1ojcjXA?1&AWP$A
z=pD7(Ojk*;Wg+cgj#>7kfP`57^aCW1TN=Au;M++{Q9DFKEyGxlFw1Z%Z#iXY_byyK
zZTWjHM8hpF*I|SamQ!DXoUt6J!z7%w^rL$u%CgK8DAAUu=(7dqES;BPpyw@9e@0`h
z<;Rp~j<fvaCy;o{rS1SruryFfZ=&TG<2Z~W$?_DP(@D0hqz~VuSk^p-ewyX3BoGfP
z(_0{(R<=tZ>1EaP6?_V?TH*t{$E^4-XfRfDsKoua)w{HDK4G=x8z_WYO$dXdVOF2N
zLgOi`ln1bI+G-|cDZ;IiC}JF8WoJ+2#<5m=X~UmtmFNVLX5|_VjdZK+^uWll`g0m!
zimYNOuzAzUc^+VHS?#|AQem}@-i?)3LM7a;vRX`$l4>it1)Qm|a(ovewN`=Y5V>oW
zn~27HR$dQ*dEY9LcCQbt)O8dNuCwCi!i##Vl`ar%uqyro?l)Qm{tMD<^_n)EEmkp<
z-EXxLl>?^Ds@M`-yOm=s6rNa(ps@Q>E9rCeJ+oRuhxMLYeQb@s7gl5DgX^=JVv9k%
zv~r@`u;1!iJ2VbhX*1|A5Di*w`yQ>YtOh91{@P0A1mE6R9T^1YB#)*Qn6tc!!sh$r
z{gjJ#ky}w@&{fVZ0@*K5pfetB@~z(B+~tvOko1t(XrS&X*LFg|OYX59jo$Ksg_vI-
zxqlJN`^vwi;zOgKyqQuT2jss|fw8~*C{5`>`85W^4v^QKM&lv*@>opUVR_wp^c|63
z%LI0i+?GnXj>;F&+b~!jIvjn+<X9x*f{@Ra!{Bkbg$f2w$U9$wJ1HMr0lhG}z8%~t
z`Ou9}IBk^YQ7k50zB&(`5%Tsw(HSXUF%61m<jHqI&dP(5VIo>y_%j9*BfmoX)pPQ!
zA293Z<&BiDij^DB0wqpvxe1N&@^kayMS}d(FkmLitK%S&B=4jRZnAtbZKqP?%`F&G
zn%t-#0?>4MDjhY>kiWYR`WNI+Q=yS5A2}Z8v*e@pfV(J<rl;*Cc@KTxC|~aU9B2jd
zs6U`kDDS?FdAct5xB$>Q@~KB5QYMe=#t6&hH&>&vLT+{qV3qQ$ILvmHyr&o*R?F`i
zX(>}9ce)0RTKUO~K)Wm7K}ALP<kqysyf0ry-(z|pPrD7tI{8f(pw-KrBB0P9|KS&i
zG|9cTps`u*xCcXPkw2s&j#l}!U?{Z7Z@dqYcKP|6ARY3AKuC7VAJQ|sOU`R49NaBm
z^F7dd<e~{^?UmaML*qkv?{R26l8dSS=c)XI=|FoXce#PS=kk5@On4!`OAGWq`EC!0
zyp#vgim_jwd;kL-ke6ma!P)wgy=dHLeVtAaxma&Ih1qtsw%LXuxmiaA(qBMvw~lND
z>tP-IH4J)Mhda_WYyE&y%ih+>^lJC9{(d|feXY42;QXw0w7)oDEu;9Fzcm{Vg9ojf
ze}<(f8{-HJBF1K|44CI_`l*5?&Zc7=oJp{`KuP{2n_o>JnPPJt8$P2r&E{+Rc66qV
zH>GMTZD!O$ztLv+Oz1b+3@HHDY*V@lT#L=wf1%%MvvwQ|w%Mf8+vTy1jP_GcY$E4C
z@`cSfN>9ABSwjimew$PakO7-eD)Sn&S@9HJyt3Irfr!^Onj|zD-`G@971LXrLvcWJ
zQaID~?5qg<3kLToJgKO{MNz&08a|3iiNN+%T$&4*5Jhw>8jmYtk76(<6;J629;z5Z
z(ep4x>G$AHDfUc;WVm9?Y?=hc^!reVS3IY+<po7yGDxOT@#zK_%u+m@2AMoXS{>}>
zD+UAU>Q;o)k)=Y#1X_4rSLA;Kazo)42gM=<mbZ8yD>iwc@s`5e1+Lvza0ZZKMa&yC
zmM8*f!CR_`rV#F33<8ecQ~X4+nfr?E+hOQ|!q|Bd8g&Zi!(i(bBirCbgJS${kVeHX
z)*wxa@A{$GtXORUu0;{l4X#y@MWy0xipEc%-mWlGs;5J7>@_TPD)PD@*`-MS9$dHL
z>-iArQB+V_K(AuTFZi_{DqKH6<0Hipqcd6`D~?kp@QEV%1$=v|_=(Q-JyWzT2h4Lt
zHoZ+>C_FdA!#+i7H$+}4RE_BCR|FYhcR=x$0+54>G75daQdm>g?X_Ye-CIt|&-Y^v
zos~Q3le_zri^ULeQH~u4;;Q`o4#^x=rk4Zzi1OkpU>{Zf_6^X2l^eD|@whTehq*kV
z+)8iElgh6b!(gb=AsFt5DZi-%cS`AY2zsZLwVCv5D;p>P5}{ms9$cidha#S5l%qd~
z`dQ_)v#=Ybbm~T9v~uGrs`89c{_p_oIprM*ES*;_qO@16a*(1qamuf#EHz#^>?Y6>
zl&{6WPE>|i113p1jf3~eN&^LvQk2)6fs(4M{SgCAQ;wu<Z@Tg{Eh96O)hUp?pe*|m
zjhV{AL~vP38FJ7@@kQlGDu%kGJWEF;vz6UPppm02rw>_NR=UwKtSd?bWo)i0RWT5`
zro52@{aj^a7cAu|vnc$NudJrfUxD%?x(y4JS7}LbT{(f`FE^AnLol);Wlt!$o5~xs
z$hxJRgOID(cw4EW+*GkL-50|yQBHHlKueV~=-Ur>lryp+TBck^w`#fa_9K|DP?nM1
zN@a~2pjFCuC4i|`w(N&`jdGbINUidRB+SKK<>^?A_ny+7BE$EUk557JfwGl`Tc->y
z#{lb%%44*lX;7|uAE1rOiF6pHNx6t3Tg}Ra6X9Bm@^KKnXjMAUv6nVw6)oA?l}~D+
z(4qW}P5^c)E9iS$UCKBLB6TZcv*2it@(ykKdzHnF7}7(f<}sXkq+CNWgU8Aj^cy@;
z8vl`DXit@CDzML#+bOB@T=_To_Ck4OFG!#AJF@grIgiek^eb-#fD9;k3d0O4<0*jg
zN;z{O)L$#DDH!`k*?tb=eXHCV2X!Yd`D+koF7Gbv?&B6vVVDcIh!PgA+-BoHVE1!{
z_u#M_mwXhQJNL_H@X3RlL0_oz<epc+CogUyZ4A7*vH2iA+?rNc^5wpxoWCDuaS$R0
zxUOU9^XI;(fcb;mid2XMaCtuP@DOKX34a5*wJ*RO<`%4jg(KX*S7}`p#5qx{@+c<>
z0SV>;PXP27=NSb35N?wi8ppXTD%m-~wIo9EBzJ^LKSR0b-(V?>Yq^WToZ^<!8Jg2v
z{$4l}&ds3}SOmwNfJh|gdKM^WxSqeEcb1E$vbZR2M;Mg@MRVzt>5Ji#7eMA5*IWd0
zo*Sf@jpZJ{2QT8do1XzRo*VlXCK5Qe|InDoeL{!1lDH%ETu<g4zQzbsxV8Vg4Y@XY
z<)m>|<A9RR9XSJq3~n)jUEs9dFrUd?!vq<{S=^&z@bn^g&J~@PxbVf$$mTv@4=#rb
z-wbk@TecM%S2%VpB(HLT)8X$m?&=B*Etd-!0-y4@EGiJm=N@=Lp@7Rj28BW{Wh}^b
zZU==7Z*ZfQfE0226ET%HIRzaEm~o3!QdRkFZmT<BiaGZLjG}}aNCH>NO`-e#4!4Mw
z<Yk=MOt@CgjWC0L1=nu{FDkjULDmV#qkTq&d$ruMuh4jxyU7CO9@qQ<8t-${Qeoi%
zmqj%sb)3Egq@Md%i@pZVd@i^~&X=mLnz+Gms5f&;%2c#)FKC(H%FU!mXB#*CIDBd6
z&gG-8gZut7=yh^~bXuT`V~tOM*3Icy{1iRhyjOtf<?IpA6hGwVP;mbdx62RL+GFm+
zzc7|3oSY(-Pq_}#d&W(S1<Z5qSOdrlE^-_E?c>&sg2GFVr43X+_ux3l0QWUL1O~ar
zsgQidRjx(jYtC~NJ%ZnG{{?}(<x=VU8&3QzE5JDO9X2qyj}I+HqYHnI3SV9M9~F??
z&$m++#EsX}de@z=qGhuOf4BqKo;<D%+;{wBIn=#*H**Zzhkry71YbUfs;2z-zZEcl
zfcL*g*Rekz>WbEb{1!Pt1Na0w1apWVnhKdf{w~Ea4)c}85IMrHr`SvoU&F%SQQqb>
zECutEYoK?G|DXycLinw;%|6b@A4cB^e!l?<vHa7ia5RpeL6MetUP23@1U?jjVWT*a
z|Bs?LNqimUXOsD3w82i{GiX(q%E#0DFOARLfuW`IsfBPYgAX!7<N|+_O13lk9cyrP
zW$}~l0rVn2GY@)~c+(e9$maV*fX?B|hQf=>yv7X*SNJtl`h1mNl>rgsHU5LMU~~D_
zO0ao+>NB9_^T%lsUBE}vex{I@(bN4pZ%f6%H+bifFj2%yX{UFS@BS5fxA>+FK)KC7
zUII(Syp;zWE#dv?{Z-08ae!-gc*Pksmhm4`v1U0x-~mGwM*f$XK&#|8T!Cm6UqSoE
zYJLwzvTOKv<6)wfZ_P#HU4HvD4Er8GQx3`d{7yRR^nmZ=Az8=!P)4<$|A*>n8u-71
zV4{(qNS8+wFWm&!n)xCFz*_jJ-$SI8?_LS6jW>?FkD;~mvsVDEgYTkGDRlA^>6;H-
z{3<C#yZIZoFxbN{rE|-@d?20Dd&vJ=0Fg($_5+ORF+VB<jZgSbC|LfKpArGP&-e>8
z-sk++x52&O+2s)F<M%!W*h~K3&tSfvuQJ*Lbbvo#ib)vcb(E=i#qSvnnb&-7KFAwB
zWCAR`<zquJ3MXOYN({|eI8y{}pO8Y!NEhL`6D+w3ANIl0eqqBoaBe~bRZqDKU(sgY
zLul=Q1y3P{vVdNKpB2=-g~Dre|M>_qx`KU$8%rVMCsfi~<$y4P?D`91>4|nwc#lr=
z2MF=>!yFQBQNANkxNnZe!@^HT;L{PooAxY0!arJo9TjwIArdT<Ou-<I3A*nw`Vb*T
z4G)hCslAXqA<R#wzvOySNYq0nRH&txdzcXR3^Jz#V>8HUq4FFY4j1myXAmQVr4;pz
z6vk7f;2EL*B)GG}#og$O5?t0mJz5C=7<OZXBga9`2_xyd4(Ej}bgRS)idcZf3C{#@
z@j?><A4YM4pr_<%qL4WqqfZk4nhT9&;iI9DNfBJ=c1RT-jX`6YkVe;Bx)9Zf#tfmj
z5_%VeMTa1nDFjfgK1(R3mB>ZmNF~f)66SUSGg~-O0)-r5g9T>vvhaigA6JAEbm<tc
z3Lnxfb4^GN1)D3B(~+k<L8e4wzVPH*fEEZ>{V}vcK{p@R*9D(sz}yhxC?`@Rh}+P2
zQ?R5r&Mjdo<+yJP`qA*ISlD<Ek|n~o^sp}#V(BNmBSd}+^JT)V6(HqCVfIF}RtQJF
zf?}mmN&%`WA<6>IR0~54Fjyn(r}as#aG!D$cZK}%kh~|n?*aY$f)&l|1K~?LE>kCj
znL)2!2>t**H3-iiVi1kOCv>u<Nti{ab()0-JwRy@R?@bnRWK%=fJ~b(Bnu|mg-m)(
zcL=Ab3aV3>Z3c}l!MO(_-9j|&9eRZP8!+E1yrosrLt*H1aF2v{2<5TRO)=Fc!U0-z
zJQe2Cj{2FfWF?@V3**j0<b^ON7jE|nHBI1N3I~iw!1fD2n#278A%c!b4hr=j!M9gJ
z`y|M`7Us@`$Qz+40Rw$2e6tiHPO2;$c<8L!N$LB2s=*Q9TvWfjK%c8>{I~EaP_>sf
zsE1X5l%Vg3Y7Lca2dOsCfWlE#^-}Z&t9q<yu@s{EfL5``RpY79_=M^#g(^>~x<<i#
zsOtSTm=9BJ-wE!NYUgKAIISwDBA#&7p51UeLiHtqMym2C?0QD^J;hYds>;3qiBkDf
zv^iQ;OFOO@)p1&hoKsz<Z&03BwGL7oBUaT)Yl1jc_Fl9msBBk5BT;p98%UDs;vhhi
zRm*g+l%m>2MLemha*EKVseGTqr*zfK_c2`=D(_Dqc|p}Z4gO}T)D&yaQaR9O<)X@Y
zD(qfTO{cP%Y}K-9=*v;nqnykrzO3q|<iHhGkvZOfS5=5X;dW5f2g5|J>YffJ@>DXa
zyUkafcn9VSR86!;D^&eWMSa&*3n=<}L$#$Bb6BJr_7%uY)n-3n-ck+BhWXp7@f3?K
zRz0V^Xo+fMBuJ@h?j<xD@2LLS0sS)7ulFEYuG$m{QlYA+qo|cCyN57QrAk}{(Q1`f
zK1hw~EuB`VRZV>Xa#v+dS-^X$nZLrP`>N}1n8OFEpH2X?PNf+Mu3i<D1k482hqK^Q
zql#My(xeKZ?R~RR<#rI>w5aN6RoSXaX@^Fe$|Dzz?Wz&$Ak(3`auH~qDzz;vb*Vnt
zfW~fB<1&yQRYfn*dQ}qI{ykLH{05&MsfOu*@>td64ep7Gr`_CBmE+Htyk{z@7bfVr
zYFsM7UZ{*I-$S%db!;eHe5op;!vp=QXCV+BP=(NXdr-A!C`4YVqQ?R4wQA>fNWM`m
zG=bz>)$vw{IH~tW!$W8Fp)bMhQ;(oUsf)VkJ#emSFJI{GSHD{eOgHs*Dm-^r%PHOI
zq5jzT7T$QO<2(WCrG8DtR^I9&N`(2SgQ(KRS1tEKqn~;Rz041&e@ubj{^}e$({fP#
zGX)+4)L(Cf$RV{g#p(mqUsL@5uzDYrnjBHzBoBkspY(tnRll7Kd%^0i&!K)yeZK5}
z_n(>{4w&O=<2aBLYVjDLom5|?Sa7JinktII)E;!E`IP$AyMQ^ZeqDvh4_BAhf{Rc;
zq7+c1I&UesGiq0gT%1+ETm~*m-7^+GMXT8z5Q$M2oCVl9buC4!&Z~E;{&)YW(`k_y
zr~Zy^l6dvp??4jNA?qQNs6Ma3%qFQ-^x1)Ab<Ga+rKn4u!I@O`f@MHUQy)}9BwZc1
z3ym4-um*4!)PJ~xWU8OLW7f0OyL+H_QLSl&Gndq(sdgw^y$)#)qc}(XUp87Vt1}YO
zdPO}o5tgp1pPT_&p88fHxP0|;s!A_ZAE)o2T~}{e3fFF^r{08Kk=msKL%XRSH4c5Z
z)YF#3(rtAYt^A7BM`$fjqHdvD(^B<9y43He&q<(HroMLw#8|F=MNyFobu_))D%IW;
z6{%A9Z3RrV`b!2}je3A$cC~8nLm13mb>18_-dFdpMdJf?2bCMtsnbO8sb2l&Cy)m9
zW-5_vRM&?CrAd9Q4ufb`FQUrt7WMP-P-s<;px9TNQT@UKY`fan2hk4o;sH3*sdl9g
z#&xM9w}9(b*Cv7VsO#52vRA#0UV{(SbxM#&>dBR8e4^gF7Ct>y8)*UfOr7!?<hj~=
z3iMv6XHtN+Po2>Le_yJLP(2{-SFfk-$$;88&ll{VIwuY0U#U~?fqSj~{WmDSQJ<mG
z)3@q=S~fUo_=SLR)}+nBVD@SBgCH&%uYb|!s!3=8_I{0b4t_K@&E$EIbk|HRhlq#f
zOWL4%Y6_>rpqHj19F5+ZEuEMPAI&$$<IwQc?9oBPPgBy4&I6i7_b|`?nwUH&9@Oj=
z13N&I+zO3Dn$C&vFi<m_ma&I5dtbuCBbq7=M1nNaeu9akn$M^*Cs?z?3nIrfZ|RRT
zglNV+f%<Vx7F}y6Gzl|d;iM*J9p$k@HTeS|VVa{9b2z0rJsaF<P0SRS57&(N0bGRU
z4iyweYPQmt&S+w&4EZb`ub8JO&8N|@8?Et~1TIDsRt$1Zv&a-fI<Ij%01~Uo=0V~#
z$IZ|euc@IcFhNs$Y)H`l97bUr|2sTR(e#Z6YO3a&#o*F3ODIW@uK9#+iww;y3Ea4#
zc`p$5Gc}XKFsLj|TpHjmYSc-9yQGQy40_p`FI1S)9F5!yjh8i!v~0hkxl#b=s~TAr
z=IfefS1=@VHTgjxc^cN3hR%G=SUpIAMnsFnLQTCt27F!fZVc?+(CClBiz1EF9hkqV
znXwq$EloRReQs-9FT+x?#)fuDC7N=3D3oeSj>EM(nt<KFEYnzH!o=m8SRD*jXwoPQ
zQ>ocONBF8Vw|}7xbG2p#6+_o(rij4RYP_o<b62x^229-3Jfd{qea!|1hW0@74y_LB
zG;2mevR<=;e#-`p9eqQ(QS(_p8k;n!ly+&>%o_&tEgH`+FbR(}e^9F6iRRxZC_L3j
zC<pXRli*CX_0Kia=y~}<GlGsV^=Uk4k@-?%PFucy&0IRDJ)qg}8hwKr7pm%frRl4{
zcwcLd(MIfzCg&p1VzrkkTo$L*(xscA{b&}{leFL1qc2(8NE_W0ZC(LJma2UeiN-YT
zf7t37#Ti=LSafD;k5HH{OFMNpWG-ogC<&CUT|&{e9Bqg|zo_;By;rVi)AvB(sy2#F
z<XzJmFM#A~yXXqe)8>2w^#biPT45Awr(A$D*R`|kAyTA`pi=`kwa@9u$1Ux_&(UbS
zt<9bWjbiNx3X_*;*HV<ER9i{)Z+En169H4EHU19s<=QSvDpqK7E5KE1*9^yWS7}|6
zp-`<A(MhBl?Ju-RtJQv<4-<E_0!{2aZJav>abLS|D<mIi7gE5rPMi228taYPqr>4;
zi?%2bp0;b>qa}KWR!pI|PVF!EV7^N`mBRYnTE}lddbBF~7D=!6(;z53)cXAa$;aBi
zCIRh<wt~*GKGnXN4f0G|qJ;W$?d3FxywFZGgWW!D;5(3fsr}Oh9`<XE+yGh!v~#b*
zi$N{>5n5kqMb}~Cwe~g@LA=p+yaSQ9+U3&$<D@%J<!H`2pAqQWr+au9mRxjg6ghF#
zmC=iHzb@q&MBH>$dx7b$%l#UC9=d-iE9a?;`w)Zh(#gwU!CQC5cnYmPx@$G?)K^zb
z-xTrF-Jmtl0o@<fQ1sWu(5bxu-M~#W9@6!%fI^@ykJ1T;b!#`n#1Wmg1;1U8ZipX5
zj_SPWMG~xQ>V&0Zx?Q`08KT?3qwl!RWCQe0=mIF%cT$)18HIB~bwN?k2-5}7Yy6b%
zt{oIl>t^==J3{y166PyX=dl9gJ)`Ropm0{VcsZsdO1CK)uEpr2R3dO*ms1Q&vAO^`
zEXC_q(_cDF(8+c{BvCgtA9j;;HUyTe+no-D6y1<k`p99LZvS(Lrt2>4L1%_;knZ#g
zx`7k$B2(A37ob_X{{rCQMV;>qz+BS#QBWyc_muAK9Nm%@G+x$K*+S%s&c_)Buj+dL
z0@yWO+bKxq>SmrsW1g;d7zUBAdrsFyfi4C`F-CErZp(JST-Uv@MQ4%DAce+F-H0R5
zxTQ-lfor#Q$0)j4tQ(|DuSBPz>abGX&U!Qs=(;Y$lDq9bipP7}{z}nFFWY&Z=nJxK
zr47O{+d~w3KVdu533kJ5555oeaNFLWAZd)U{fee7+IDz7L}P3@+R>b|wKIpM^R`v=
z%#XE=oC7c7Y**8(Hr}>(CAb9J{2ag}+WtZ7*Cg9}^C6jR8${EcVjD^2WU014PX=bX
z?Q1%%o?-i#9;jDsKcUUeHQP}(&?`3D`cSb~iEUs9L`!XRSHbQb+gw^omDx`G56+a^
zZd;0>RoJ>)f>hcLZ30Y{?X@`QSKHoN2fZ5G&MR=H)^;|b+_kOW1k8K3FDF6azHR?=
zpggb*k3?ggtziW8>TRo*!>0yY<EmVAHrgiB8oAka5gk)%vHkWU&|K`!zeS^~-4S~4
z@3(un6^d?lGu;7t+%A4G^iJ5-P}=6CT^X(3L+!+rF$}X?F$;aC>?Tcydbk}!TjL13
z#XrLQ8M|o(K#8|IN`F^9!ES=_DaM;<*Gl=vB)e}sp`UE$MlYEZyQO!)rP|G<#a^1-
z-Y}TRvHOuS_LuG251{Xgonj<Nk=^0TK)Y$@y#VBvT>@=*Z`;j7u3TJV_o$L))NT&#
zCd=&3zXxX?*eyK`59{oTOQ@Kq-mZQPWE$)~+y+Zcb~RMs-fZV30eNOuKne60c2nsz
zXrJBWM;OyfJ6noi_S=Qh<9X2T@6`}_WoH+JzSnjm-Us)_Zp2=wJK49>i_h7<t{sy5
z>>C%r3m5wVPxQIkyRW8Vy8ZTh8Zmk|`w~i^d)Rybj!sYe=QSW+_W6{q^|tRA1HXOj
zj}8LH*S=#FEcw}wq`b!gdq-Nx9kl=J6x0LkTW+E6kbNta9R%9<(^Y-gzMBEq5&MEq
zAQ@zTZ76&?YCmfu6|)|*mr@8L#6D&z{i61tpGN0N`=%cNbH@H_7xbOA_i=!wX#4ea
zLB!Z^{S4&1{lDWd&^Y^I3I)X5ub@Y0g8fQbJS5t;QbaDveu55|$@aFV(U@W%cnuz=
z+E1o(zcl+(nIOh=d%*y-4Et&SViGRcPqIO4mVN&%*v+-?pr>`7eI(^X^X-QYgZl;c
z<#*s=p?yvn8n4?Ar|aT|{d8L1-LxOQ4F+%7=f|M$wtZz8`YP>@{0vfMUl9c8I{Pil
z&{uD7P1UarM*D-bnQpXq?ZQMg+51z7xY>SFFJxNmzxV--t@htKL%+>_6y0&{_8UfH
z*d6xoFGFLe{p0UIy6n%iLbBW5Y&X2{e@A%A!W8}+vDp<?K5VA@c+|Y37@-TZj>2`W
zjG9h7?Kd(f|F=121`D9+&dhT{rw8-TF(`X70)2bNi`hXxf;Te^Rnn#*OggRRQ<<`K
zc$&tPDKV$%OvDfHErV&Li{=7zovJf4na5O~mBq|-g~&z5s}$rClSGxw+02Aha5#rC
zI?(g|GGm<!jVsKQPat!Z;r+o~V?Lp@UM|x}um2)u#_AzMOxu_odRn`(SG%FVpY47R
zXm0H1^obvLcIXKxc(937An(ckO(k|-Y+W-3>dj8_L8A}rHXRDS?3z+Y`mt@s|Dbq)
z9iqjU{MoSr#(R*h3WpZ~><&bgOhehT$b6WVvvzkSLrmR7j#L=pA=>&8GX#HE+-(7{
zkBI6&gufx8sF5(3Ai7sCf(`sPsqzN?oid>tHop4iBt)k=M#I8%WeyDdR*Jm4QT)e`
zL*UBa7F4mgZ4O<Fj>7o={Rp4Yc?@qRg1%gr&KPLLaFvM|{(nC$$Bjbw8_}dOu>Dq)
zsDWQjCLCRO{wBU7fqBs6tQ)vfW==6sJ#E%YiHdNu!TrFCFk48mwtAy{Y#n6U<d5ml
zNU!`U#gd-O6B;1;O78I+I2Y^xD3;`9-9cq%2d!nZfPK_@?+$RG)}cEfdB!@W7-(m$
zZ+r?bqO4;mMICK@mjdB2*0M9;&RKu-4@Py~dS@lTVy#sK7H1u_=O#X|vOElPlVYvh
z4Z$qyg`pr<t@kVf)^+Pj3I>)~yZr|38tZI26;^9KAq^mRt^MrLchCCj7!2XQ^`pN*
zdabSJLGq!sz7pIc>lYMRd~98F1l$wrpg354YMuNohVaaKC8gP)TL&7c0``S<csQ{8
ztn0T!rr+8t7Ul=6i>YRO&^qBc8edsYU5OFBwpP$0`Hl5n5n$e0fB6xxoowdO;@;WD
zKy}XhY%T_ZbGLaq3n(5oW8J}d+IYJ`&&%etB@B7ne87S`XmhHYcA^0`tN+Dd4%uXu
z;>QZK`6ml@58HUu11-YFC5PtK#-CpDF*aMup^#|vDZNQkY%Cox!YrHg9!TD^$@&6)
z_ig&RLF#N?gn`uCl&t}2vPtuUzs)vbAHq<-&AG==cT&g%iUj#6KB6_gui|M3NU-8D
zr82@4G2g-Ovx+iGea0zV=)7;Lg5Ly77Zs!bgiqHLdnvPbL*Yz?aHWbGN+wq;SW2DL
zDcUK}*s8Fk!igTmhQDF=nPMz%H&p)Y`3dU#lq-vd;3n`?22eK2OBq686L013fq?N*
zcH>SG`zohU{jZ<Wo8Dmulxuci_WYG+pMpE6Og#^g0A<&6pdC_9_zrFdD(AgH-(lsh
zk<dG$T(b~hLCS<S=p9uqxsApMWjs}@L@KY;K*4xMdEqV%RQUtd6h|pHQBWaTxl@Gk
z#wbt!gT`}8n^6!wuY7O`Bv$#|3W&rhKcoO<ymE9jhL)fla~YC}%4|;<Oj6!?3!jpe
z0k2^&RoNH<$u#ACN|dE5&-h>tGn9&H=(}K4b`6Dort({Qy=Eyl(T@G1@+uAVl5ztb
zUdUE1q<v+MvUn3DFDplX1Ia7O&<I$%s(e(9#%oILNa*D%Hw0lyN|c|U$B?R&BD%UB
zD0hcKp+$M}J$TryytWOJPnAP<p>a^TtY;puUnv`^A^KW*b`td8C|&B&`Bu5X8D2PX
z(e!ByA8tOKqx9uM6M*f<t@;Hb2e`ju0qW2B4MX2S?oJmb=n&_+89oJaF9L#=lrUOj
zOC$78alcA{eVS9A1{cn~KLi>PT=n;8jO6yVK;sP8kp_cjxu<lxIf@fAz>eYGQWW7F
zS3*hu^IRF#J;ickvtTKX>!xy`cy4PKFcY{jn?VvehH^ET+y@GbEQ^aa(sMVPi~R!F
zIouCKZgAhO0!$I-Sq;%!+)Fwkcbn_{6kHYOXa>+~?j3TbmRoTi>UX(Zx+$Bv2k*m~
z7A}+)ajo2%UXV5}{1HUjxs6nK)WP*qfTNT9j_QWHxR0ahN9g9{ZBXptcI|;iFFyPL
zOAonQKfsGeoM|+;$6UZ;%<K~`&>1jKxpB|n({pa!8YsNrejAJF?&F5f1NV|UxC*47
zn=uL_9N^AL>8IqXX!rAqn@j~YuQ``efW6_yWYIqBE!Q;(^X0@(SPeyIe#Lpn?Blo9
zLD7Y`egh9(`P35h`SM36q0x^|RY2hYzlXBH{(S#lpat+l_4NDl9rOW*K)!7l96ijN
z?SkFY{CEm^h4br4B!d5>8eAkl^5KvnL&azKAt?Yo%L`L6rYQbA{i4x)X#*5v_$@*H
zcTke@rU~Zbcu_l?iRUXRd!E3L#VZfB3M)=QFPXQR2b2_kMmxAve&YAw()hYCaOwQJ
zyD^6u{FkJ6ftS#0FO!d=aAg)>P2cso$d|o?#!I|124=JQnN&8C!^hE2c$rT%{sf<{
z@Ebot>s7vOI5dj+{l{Uxgty*}zB_zn3KYxu(;uR-l7CkVkt%*GO<oV*6^jY#<^TE|
zWRTxNXIWqIMbBXVHQ%@#Cf@KpzoGFhf6WyNPQvo{;Ha~3YB9XuCm33du<Ih+`y1Ds
zs}Ms6U-k=r6bp0{-uWGU?n25Gpm_*8KLU)W@P07#y@ZMMEd(FIj}|(<!YVZy{e-tv
zG;=_RpAT$*!Fe+J4hp4pfDRB`n$dSi=-|;9C>WeDq{G6}q4Xj+B2*j)8zfwH2k22D
zh&Fb?!r}#JJSP0?4eSs>O+^k-!g5+CMGJ?2Lt~6^aV5BO!p39xMa~P0cLF<BST+vo
z@xsp)u$v&TEbJx<lW5DCB<!gHmn?ip)wn6blM4FMOW4>2|6qhkWBaHuJ9+G*yMXcd
zX!k!bQ9aIC4igRIw%@|cy#Cxs(aJZUf0Tg6fbrk2201!@3_Xj2$B(DiNyzv$*8r9>
zzV<cD=Z;ss1ChM(Lw|zE&G8HA)@~agN^9(>312<2pcfImU9Ucfe>Z$cU(^2g{n@aw
zafBLP{I}>O{@vC|>#*(dA;8};^8s|7n8lNT>&)zE2e*$Y4~2ji^XX8acr#;~;DIl5
zh}N5jnI-c9afB)P8$&+Hgq{OPC{z0yTo@x&(9yyu#*e~!(TwIPNDNcB3UhUixiAr+
z$;`x18V~c%eptH5?A#9S65~m?bv84z6LXZqyrc-+b!HwVqHi!S>2N_2bG8X4ZZb(#
z=&NMf#{#U1aiZ8{HRIzA3pLClKl;*D1GAX&HI2;7zd)LpDHQ8#X8!sDBWz*h{s3)d
zKK>Yfw=plDp|73kvj%7fb14~pkC_}PK%X#$$xwgFyr4+fGiDs+%APata^PMwS##m&
z8-|&U33|&kT!VrWJBMDmMrSs^9IgA<ZJoe&VGsWWQCC(?0iyk^KW(Sn*jazUpgXIG
zg@_0Hk}^V`Y@jbj=*3=%0`X?Q`5lrz>@G?_`m%~X`0K~2rhpt^!@@xP**bc}9b{Kd
z1{c73&~o6Akv*&dS|FP_4%mm;)S-|$!v0RB0YU64DrY{*e)b1U1hdK0;OH^7imC-e
zSkox@betVJA2WM`ox!2;Bx|HYV`o?wN-LjbGi%^XJp26#j3t3Rb`=VVY`rN+5?gl$
zjhU=*@({>mu}RPA_hpx_1k5G&lZ~*O&3;Lx5czD`dh`{rTTVl<kR3_!gzM~>?a;r$
z*8U3Dir9eN=)1{oy#n)h*$=6d;U2pp0^~j`-i*En>^VC5-N5GbK(Cn%o(T&r>}@0M
zyIR>^s_t)NQ&-aO%jQjj`yFid9%yv31=i^6Vyhd_=OmiA2MX?@uayw-6WtgGgNH?C
zl=(g`8c@SvxM*NCOq>(>Qwi>Q(Ww}aSW)#vco8R>OqGQ3q8(0{`~=Y#t&|eIC>p4P
ziA$ngrfAI;JsJVuazu?S;4X_M{4dBSDzbz5Ya++FP{<WkE&|CD4bZQZFZz(S*#)AJ
zn}J;@%5H{wxoBn?ytpfh84Z+1(T2n5>kzdY(D+E?Q3!=T(NS}H{=E_PEr*7i$y2Jj
zbvMbN^@oQ^=rVAgCN^C#;bqbi3w>{sPbfOzV`4cU+)<NXM8FO<Sx3)}V<wIRKnXF~
zy$a;G$%skt_k_vK-!O+KO$r3)g_+E!C&Vce-wtr6P2M|A&%bb!$1i~vVKR#%vymoQ
z_H+rEq)?tD$t1%D4qq^Nhr(-@P2!iprvj7M6zJbJnfWnHRG3Vqi~OERstgKECTFBj
z?=pEo@&9g<;3rV%F?qp&^qPE4JF15!zf*16Ba;DBIBI-sveOALPfY5TK>v-&uk+x=
zTay>BAnGLcItkaD#e1mwbf4JU71%CfyEG`civ4!M#D4Mc0!)y**qKfvc!>L3A?YdZ
zhy|FJc=TuxZxn_=!ACrmRye-mA1MmsCk~~<(m_V?K0nAD6<gc@8!SGP1ejyuSaLW-
z`~js1j*Dl}66b{Y#yLoa;@}e`!|(?X0dq=xD+H3K#rx?XO}KdWK{yj3-ewDwNbxgD
zv&M=4=z&PQ_#uVP62x=p^lqYfFBSGBiH*Z4pPekuqmvdXV&6Q#q>5AG;BdNl)dWmJ
zhFG9Y;{~xi3wATbVp`T_iMP+g%v==fj{)tH_`ymvX5%AsKq)}M9xN4#KcGzRb+JJ8
zXE(%?gFuSJ@+}}Y#UZ<3_Li78)<Whs{$3D%!(y>OS;$gxW(T-C;s+yPqD<UK1z_dk
zHI&n=5E~wVs}%on4f<8$`BVi^Ew-Y}N{x8bE?~EczoYz0o4Dh1fVGQVXjR=I{_-Nm
z(kZ@5S@ABM;{$Y$IN%Q>^n1mT!4Q2Yjy?yON8$-|c|8`pG(q%<I4&M`--<_3?UIw}
zEkC&CY<i#o`uj|`1OeN{bQS`aVpr37lcB!fv?UfEx|<%OiXsowk^O-7H09=k^D^aY
zpyzG6;1gi_nBH}ul008i2Ng7qnc7jYafs<1IzD*Zw6Yg6CrsrOH9l#2XfC)=(^2#&
z3^N@QjK))@%TK_=aMQ9vU`Lp`T7!!;ed!CZGp4n_!|qwrD_@{5%Cw{t(;RKu9R<A@
z(~`RoxoXP)LD_(7rsF7UbJH~98r*+is(FoHyUsM8RwJ)X4_Cl$l$rKC&~nY3B|ytF
z+j0Pn_sq<y&{$`7<RsKP&B8x`Ymd#grbF+gndJq5^_xwMpwXLODu#lW`2;b{2bxd6
z4fCPq*|bA2CYt|X0-1~EcZy&)*W6x<)_dmf(FvNz<|EDk)Ll|QIh;U=BP|e4OEz)v
zB0=IqA@fwpCfZ0|m&~Lk=naYM576_L=Bv=?Cq3m0?trx23Y@?6Qa?ljq@7dX?;+`I
zDs?_=ly2RK)+5sEeefIK32=jGh_r#KQjSa0OyKEB=@2T|4wb%Z3xnZOh90F6(tqji
zW<*MPS{6k~pU9woPC9Nq`r@Qzv`b8s9y$eolclbU(3c{O+K#?7>8NmkrAsGEU_L`?
zY^Lk#g7kg5#fzl2!$59Hf2hDDlt{0>gT6B9(91AUAst7H&MN6{CwNgKEu%;9J!v^z
zqz%$_gAmzg5lmTLR|`o6I5&$!6l3?W_{|f}_*pF64@rNEo-?ozXi@w*)Q?#FXk^hE
zY_XJ%dmXn}{+gD9_>a$Z#J|6#P-bYM8x`vPeyt5?i=<!T{}+#;Qx8ktSV8xXxAgd3
znwJaMWww`rx_tC`w6D<YgxQt0bf)#s)JgDbmF;-^`&auH_$^m+S&(0IRAB`9yN{B9
zhF%|xcH8|Q@c-LwA^@@DF}=VY&(8tqu4Y<n?Fs$@|G!sGnRVlEnonnDJjKWMF;D5I
zc47V*4MktZqXN$QF^%;2KfokVwTwUGd<-O*x%o9jjxq0V0(gj#*@z&kIG!=O!>x4Y
zJ&L#IFm}ZlQ~~ont%8f0A5rlC|EFcb2>eedn|2qb!`L-f0C<WGr#Sp+_E-Xpg|lBZ
z!O<x8t3S~g&2BP5V;uWI7i`9}d>POa*pI1JGL;onbhJK=l`KYUI-3^)lELOm@HV}~
zjy?sAY}S?zqUNv~sw~Q7|N0N+^H|ez=;yQADp)FFOQ?GMChJDkWTk8ay+!Y^9i{NR
zjOA&~RL**R2$350Cn|=kWrcI#?y`kcYH6%zyHsEs*xj`1Xk_y#qSC}ZDTjVD>vA1-
zJJ_k80lSkOe+0vR$R5i@<1<!9;hpDf5+(6pu-oW@8D!^u3Oy&$7(FDPN;adu5Z{Ja
zhLqF)=I;&j13hBjGFqA)CpLI4J%63qSRagJA1nC`$}a5Y0$6ip^QjDRKYK<%pBww^
zLs)ZXn`ry$!TwAeYfpCJ|6a4~2#Q#Gvr`@e%!e(Y!WdunB)uQ~*d8PXumo0)f=Dp?
zOb)$cY+MTZLf8p8bR^*{Tlxx?qFKd5>Hl|=-%I=8g+nQc`1@+Qdl&scwTX)>E#S+N
zK-w++G2$ekmYTN$ewmg+5zGIiT=)tdm7uO1?hW}rC11g#RgRRG`YXH~n5(%Uw69rT
z59GD85L+>d|K9L9Al7*YLhV1BnK0(iupUC&uTY)%j){~}bY)Kb4DJ2QmsFDN#vJ~I
z2E|x>3xod5!8(W^WGY6%i2x?*V<?0$6RD>8IHP+6k54d_m*GMv^WiQuo@R=^0ZJtE
zv4ZwLQH(VU{c}v$3h2i%d=e}bGw$@rEnz|~U<9R1axE;~VP3s}-7+R~3pi|}rUT|a
z<ISV7k+Gr6zmsvNkNQ4mW|Tm0fU&s`k=KmqOMty)&ddO`GaL5-6hhf!$I)m^WA7fv
zKJ<SNon)#RyTAmEhf*eEvK`K5F<GV<!9_-^LEj}N`g4$Mrp_9TIZVW9AYEo^sc`K&
zGkgp@xWSB|yiO7GC0!dgnV~1pc#G-HN8@cK!xf~MNfrJ#xOL6+0sSWCJjJ7$nH`G(
z)57ef@|#}fUCQq~Wa4IFJTDnLdfN9h<LSH!E>udjyRgo*n0IB@?tp?XTd*6%k8P$j
z&jI$zJxCs97sZ1FvrT_sZjZ51{UG7&Mk;}bV0U6GViZTRB3jv;VZWks{dl&3o{tHv
z6{W>4u>MpLoXNhu1WQ?LTm$qkvX^N0kjK8)h{k;OZ~9D00V~@AyM^o~GFZwEEr2t3
z*p{hKC}aPdfdQ7YM`>SkpN%L%-vd@CM4z#a9YU9CJ$v~LIvd#QpJ9eN+0c#X>|#3^
zD0Z`#DLmA}-lIynUiK~(4?bker$gis`-qZUk68oNK0RT#QXcFn`yD-gp0OO2^gL%@
zeS|(dA`ZZ{K6dF7sJ~<bTrskKBO5Rbtpn^PD%cxjjZ{GTiruyX8n4*{RO{s<dfE$(
zW1>J>W}OnHQU*Cn)KAVNinKZKB2P5T0gW}HO{?KdkEmoj`kYM|Phg%fF`W#NcoVB>
zaOSefvwC0_n@m`X#s?-wcMm8&HTm8RWYEOz*8e>MO2i6EkkyK7hLfClG1bS^<FEE$
z>YBtmLIKq(o`ZcZ)|Btk2lsl#zfq0S6Y+$Dkn9uJ{R5u|#Lqqi_ZFc*NV=NdeffXz
z+*{f|F8a2Y)<8=#+R(f7XKTPLUr6ifl`GQGy>9M440yfsX#A@mL)!$yt6coM&1pU)
zx0@FN+KI`|!+4yT)$};>WZWp5<;5JLGYkRDd8$7;#4Mp0SP1i|8QgJ3y$pR3Oe|$M
zB8`lK(wVW$6^abUF&^}xqIl-&Rd|669F_WJFh&0X`vUVJWm7Ym2XCRD#k?bhTNfGT
z0KB-wI9vfrHWRfAB00=@F}Taj?wdfl!t_z0<W*+oIp|$uZmosgTxRUAfX-u#tEr|k
zpD}L%DPY|GgJ>ahD+r+1nHyh&++dcAK#G{-`v7{A;pi&5#W+&F_BK;Y3y5N7Q6cn7
zm^pXRSjwDIg1f^+-Gwu?%(_s_*<GfO3V7}@!#{wb`%D_Gk{>X0j013^j(Il;GHuL@
z&w<^}lsZ7BgBg1S`kl<(bWBMX)4l=N-OR4xfaziIf}n>)9z7%y*b{qzmd5@{&yft)
z^bt@p*;y1%zsPz7K=Lx%NL!R^?3%wYmV9<@Jq?g8eN6lRn|K7mQZc(o46ck#Tm_9<
z_DgrjG_n64glkTs?7b4S;y>Po#(JFnYbVGFR-O&jlWgK+sD`p;6ekR0kNyZJPqCf>
zaO5-_;|{fOcFF^I7s38z2gykGNiY04!y0eQhLy8yssj|G*wdZRh-O>0(1>BXX`z0O
z?HmTt^Xw4{QpB>CE<iGl9nlUho^`N;r3Chq0C0)y3up8tu}f%Yoz9k0zV$L|c?l?2
z*c!UXud`~ZuDHR<yWva`D>3#!<|bP+2O1S@unWvrvft9`yNb;&09VacQ=Yh<jr#@z
zZD6m`v4BRF{S|sm>}M1)Zf4~agl}OR7ND<{-RTOwHkP{ypW0dXHL%;k?xdfulWn0;
zaTj|;2C#1S`zne*_ptXr2I*zLD?;Z(HZ=pJkG)FE+n4O032?ZdeMnc)0K1jKDTD0D
z0W`j1SJXn}HT&R4kT>jzQ1rQp#!SR?xr^*5q;x>EnVwz#qU{taJ}Rm{gKHvKRNn>e
zlt^t$@t4!0lT-#4BU%v#r_PB^(ZV@d<Vv}gl>gV;bw)*%EMdC)&IL)1$}_OWXO<-i
zn6t8qin59c1{HJ^1O_Cim<9zDS42>;S25>+7*I!DP*+7=6XuLLqL?uu>-&oJ&;Ho6
z@9dA|%uL;`uKKFF@65g3UDX%S{}n`YMQ}Pup147)i}@mf^5l*R*&5i##7Vl-ofSb%
zpm0ubTA(^Fj1S?{1yP+Yq!&fjXw+R2duXBPve0F~wJW0Lc8bPd6;tU1T@#m5A#+_=
z)AI#x2y+_h+!RZ#F&ZrtTh>A3mgr1-DQ}CZH=%z=)T7_^UExkY_6H(<CtQ0dKKTLV
zk;u6O^N&S%FLX(fXhY+pXTqZb>Yj_xbC4_+-%%XX_(Cjv1^QYn(t*4YH3NbDR?NzV
zVwrHH{r2(78WkGTl+m;aa=NmfL=u!m6o5%oMmR$<N$H%8rX?%Mjo|$(rC=buPf-?r
zhQT??vLi5`s<aydk-5rq`r)K0eG*W&(Wr!Z!_yqa`8YIkl^{wLIHJ_q3Yk;NnLIF`
zDLqo?{AzX=!HZ<ozb(*G)QgmIk*exWKxCmh;Wn@rs}_d=nyDU4L}`f{PtPA)swPtC
zewjMp1u$2rYwN+^RcfR^46RX(Iko^@r|zyu-l$$Hz}=*7v<K*BbqB4HW~p_aKyiy&
zjUIlpRh>?gj%}*$7RYw>A-=%nmj%1Mlzlk38qL^-jIxDAzeCk=?B6F0e(D}m^fX{Z
zcgPG4?1j%!J>LLev@x3&XM-C=p%Ai)^5mjwQhrVJ`=)RqW;zWOV)GZ{b6hXVNgr>Z
zreWm^oJ5w;i29zzork$OY-2dukjjFaz|>q;IUgjAWj=-T>Fl{38n%cnrQ7IY7Dhkt
zOjcM(QMx58=Oy(M(?13DHkR-!uuW_U1;q1MGa5o4W?3^peq)g||0-Z!o<O_Af)2sQ
z8>}gf#_qBBH*n?|JM$LI_iURDFypzOI}E1tJPIeS<WVUc`gqx8I)IVJt{5e7)7jG2
z&|SnzDVc9ETS^<3Gnp4fg_khjmQYy3(t1F0Eh|X{*}^I$0Y01c-UWrN>?Pf<x3L0>
zPV8Y8-BH@h8dC<>KGwSo%)@LHWeXf(6)9$VicO^(#%bo)l(vLkW?g8Z?F#$)1JG`>
z%&jQhVV9?&lkT#7+6s4%U8E4eX1>7}3Ryg#@=v$$rnE+z%^%T~eJf9<$;~$Y(F@G&
z{3~rx+riC#Ld#C_)a_8X&4+qGeYvPi@zfO}aV(90SBg|h;$I~WYhZV^xI`IAYebG0
z6xWK^-$QYoD4GoBdf^`fkqsi3x@4p9nhk$9i47EunXA;GeWGc~XqqynD^D82#60Eb
zJoq$UiJ*nd1q#RTN|T{n9tr4$$}5Z+@SjGMy>-C-S(#Bp=RoN~nemI2kAq-0Q|U&d
zj3l*95Vc-?Jr;Je)%H#(<*2>r=DS<<qfMN9)RHe~M6MdQ10ws?jx<9$s20qI<RLYs
z8YJJVKD!{9V&0sRy0gqD)dbUc%)B5U#S`Yk(&5D=^9uvN4bh(RxXM5*=IMFx{Waf7
zxAPKyo>nG4@!qt~G*iqj{FeA+XYhi-uKRYQM|v%)j^o~jC$Q~(gTfVkI*x;lzLRnR
z;j?uX_&<8t1H4~~aUI<CuR#yc)1_MAGr*r>d_y~bg6Oc?CUAzo=m`e`i}g?&<L-vz
zP#cQoM`r|}0WqC-LT2)|o8V8W?**+SW<#3;XRs&NP&1R&dJ1MTt4`CcSuB}iIa$o{
z802>{)p!vy``GSc7(K|`X{qHXbIb<w6!WVEa-NMk3g54?IGQxxV!pIC`;axXMCm!(
z(FrXrVHHn8uZ%g@L|p>6qXo8E{5mqb{`j%w&<1ADidY5E{4kuRm$6u@z%7=wkE7w+
zM`rE-m{N9P9O}NXz6YWImA$21I`O<CJ$XNYcd>_LBG=yr)J(3<f~91>)ePU2`F!_2
z^zj0|vLO_<@S_Hl^7w-XW`CG3;4@c&bCrvQfVjqe?*i~T|K&UM#|<Mdh=tZozQY5R
zkN6WWh(6{aE+`dopY!nR8NX4Uy}-k1_WY9j(0a)y-oGc{KXYqZgZ)Wdu!Uc#qQf3w
z&l7gkkOd+w112(rO^0vS=>P1X!PZ;WED=EOSP`PvM)cmUS+Mz@d2R&62Uaow<Rkle
zMR~I?1(!G5cOGn}@H*{)JBPoz4$~RDc>&-T@;NkflH7-w%lXq~P+!5fhoQ8RpG=0O
zRebFiNN(cyXwS}O-q9NhS-h0avT-L5uz<`izT*>$dAuHl1^4rdzr)f|{>ulz9OHWy
zppOc89E1K@9#k8W*SUsnyf=8<JD}a<%O`?a$iJg0{w;oJC+cqVsIkzy!|%nT8}IU~
z7omQSC)EJC&r2!B_r}OOhNAUvc|MI?-|>NS;b{rKzZZ({F*gMBBX_0X#AmM1rMHwX
zst5f9(Y`HQOBCVXLu7?Wr%>=_QC~psfUu@jf-B-2?Mk{W7QTZ>vEVetD-j?1qOMGY
zK7!jxit(rAK$FVk9x$<4(f3Aazfwx$x&o!<C7|6`HtdJ!2jy&CxQ2gZc?gmjn$;gr
z%GAWJgHNk8H3p!)8#Jqvz+9r@NxpQ$7ZhSyt~$}u{R&lO(A%iiqLImFb$BC?EY;me
z*S>7^7F`*(tJhznv|HWj4=+q=NHF?xuiA4CdhZu?ZUboKs(J0;+J4pT9Sj~++fh*S
zS9M@bs2^4vyFmSjI<_kG^3~@Q%=}IDI|qf+>SQ07KclwtgEIx{53`|uK|Qk9`0Z-f
z{Xj0-+9QqT=3ZwM_}?>~_T2UA8vsu4!L-l9`vxT+_Bp;Dx_uj%0oG^9OKAOgl~zUi
z?X^U0|A|`o;M=7=Y6tXa24e%SuL5V#1d4JGo{)@|4S7uon0}RxL(AwtaSWh!v5!$b
z^hk9$IqYyH01dD49Gt+8xPoYc2Bt%F#1{#mk+}~6p-037W0>u<zjd^ZQmcYjQy@CT
zj<$@BdC(Hap=MiA8`ggxTns<D34FtV9pFUhy<sJCMiF{xY+c`H@Fi*)g&?Ezolr4e
zHxS2@%({U;jV+U9C9IlpFeL&tTbm3Jw??#Z(Kd8C-0s?oo@LvsY!&!F_WKOZAYBTy
z1NP7zVC3~21)kw$WnYNCY~Z{TZUtE`gno#_6zD{nHO29Sdz9HTHRs;9>!mt}&SSNq
zpJB81#Em#^*>J87t#JIW1wP%aa$&S>+$}(MdsvL)VJWm_bF`rl$8kM7AoxBXr&XAZ
zlPBJ@md;(<==%HO<?YtIYiy9-tDEOAS0`5&C)Ypmbdh1PqeBeQIvMzhc{Us$VsL9t
za!xKz&0U(ixp*{pbM<g(p^J%#2#eMQg&3TjoTSAUR@=(S35S2Y<gyQ}&cAK2np<>S
zwAsJh%Bn8^w#90)@DsE8N1bc@o3j}h74B$=Fz6lifk7d<5W|SD*pYhO2nPq9tE-b6
zz9@edhzX7j57Lcmsdo%_7!|1t4vZR!FGLKT1LpzJ`lx8<5rI)*<DI+dqeEjNBAsJu
zM>xg=LpmbD;5<GeDl|GWaD*O02FDnEbWF6gEoA}!sA2#A*K~D@zjE&HeXG?bD0cK;
zHtz5B?M<V~SnNaD?}c?0IVr=^QdVED)|4H;Dh;H;+S=TtyU&x0+x;^K(aZ2oPTQ?i
zH`PBULcM0LvsdIgdrd_d5NXxe^uk^<Z;c#zh-+oOy{3U_(*e!A!?M1~+D<Mwps6~u
zU4n|YIo=j{S1`3pu>8Jql^*>)hYjr9dw^%%<{mEPe*;X38J639<@%-;Rb<~Z8;x{I
zvvDv*6<L-Jk&SDJ%JThLQPmXQ&8oyf&bL>pn2eEDOYEiX0c%TB*leq;Qj^0>>#L`v
zN0DWFlkl~v(oW8B5q9$BJ>EzTx~8dWib%5=6K~<++S<{zwY#gltF^6SdZV>HWL>wl
zduxvtE_$~XtzF$mj0$Yks+HcgrJIYZYtYD%E#37kW?rmii+4rS#addst}My)bhy^4
z0y`*6LbQF^ap^fmJDz=%d1JJFxkVFc8>;QYwN2zuqIH|eY)}>{%R(Xiv-A!tCrgQJ
zki{Te+evl^hpbB{nM!nUCwU7Lkd6ja5AH0d8c<A@r>UszDr-kTs+FfS5be}M?gwQP
zq)j9+x8cNqoRwRMe3WG%+^nbUGqzl2=~!@|$YLTBWcw(PS8@)KNLdKN>pDxPXo#lC
zDbXnUw2^11cu>}gL9u#wX^25FUglA;m6x=QMe(Byhy}z|xdnuG>LY(A?pf(Qt{iwN
zk*l&8gm)SuJB&wVq?|Jz+~cwkgb((YP7}a=C8taP_l`VGBv{sp1KA_PiM*0|aaso^
z<<mHAecmHb+D_Cq()clMmLpqF1k0w9910fqtt4j<^$C>OB$8ao*34Z7R<f-kpHI|k
aS*|RbsBO$rWW!0?#+u=QTC<|^+W!I9z#GE=

diff --git a/Debug/Libs/sta-core/src/devices/stm32/gpio_pin.cyclo b/Debug/Libs/sta-core/src/devices/stm32/gpio_pin.cyclo
index cabaa3f..ba482ea 100644
--- a/Debug/Libs/sta-core/src/devices/stm32/gpio_pin.cyclo
+++ b/Debug/Libs/sta-core/src/devices/stm32/gpio_pin.cyclo
@@ -1,4 +1,4 @@
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/gpio_pin.hpp:31:11:constexpr sta::GpioPin::GpioPin()	1
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/gpio_pin.hpp:31:11:constexpr sta::GpioPin::GpioPin()	1
 ../Libs/sta-core/src/devices/stm32/gpio_pin.cpp:10:5:sta::STM32GpioPin::STM32GpioPin(GPIO_TypeDef*, uint16_t)	2
 ../Libs/sta-core/src/devices/stm32/gpio_pin.cpp:16:10:virtual void sta::STM32GpioPin::setState(sta::GpioPinState)	1
 ../Libs/sta-core/src/devices/stm32/gpio_pin.cpp:21:18:virtual sta::GpioPinState sta::STM32GpioPin::getState()	1
diff --git a/Debug/Libs/sta-core/src/devices/stm32/gpio_pin.d b/Debug/Libs/sta-core/src/devices/stm32/gpio_pin.d
index 6a5592f..2a86635 100644
--- a/Debug/Libs/sta-core/src/devices/stm32/gpio_pin.d
+++ b/Debug/Libs/sta-core/src/devices/stm32/gpio_pin.d
@@ -1,8 +1,8 @@
 Libs/sta-core/src/devices/stm32/gpio_pin.o: \
  ../Libs/sta-core/src/devices/stm32/gpio_pin.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/gpio_pin.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/gpio_pin.hpp \
  ../Core/Inc/sta/config.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/hal.hpp \
  ../Core/Inc/main.h ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \
  ../Core/Inc/stm32f4xx_hal_conf.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \
@@ -30,12 +30,12 @@ Libs/sta-core/src/devices/stm32/gpio_pin.o: \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \
  ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/gpio_pin.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/lang.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/gpio_pin.hpp:
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/gpio_pin.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/lang.hpp
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/gpio_pin.hpp:
 ../Core/Inc/sta/config.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/hal.hpp:
 ../Core/Inc/main.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h:
 ../Core/Inc/stm32f4xx_hal_conf.h:
@@ -64,6 +64,6 @@ C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h:
 ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/gpio_pin.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/lang.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/gpio_pin.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/lang.hpp:
diff --git a/Debug/Libs/sta-core/src/devices/stm32/gpio_pin.o b/Debug/Libs/sta-core/src/devices/stm32/gpio_pin.o
index 956721b781858e9138be22429a7bc458752c9256..9841557f788a4f22481e76d7eaa260aef89a8293 100644
GIT binary patch
delta 130417
zcmY&=2UrzH7xvwI@7`^<S9|Xz*4TTmi8WDUtcfMj*kVgeE~tnFP(;KoA|QyO0t!+D
z1rbG%jua6^6ci9tY*_yHknjJW=g$*&cFvslJ!j_bPB}Bnlh6^{Lr3gu!3?_8axQBh
z*+C&|`Ro-ZbKfV()UyBoKbBD?e=o_HyN6^lMMqmFlrkH4DrAbz4aVc1W%yUU1&CY(
znWArlxg?Ua%B>0+vpfZ&{tZ{vi@5&Dyo_=Bos%ghH`q!dCHve8;HUsQWZyURte0^f
z{pB)dz&KW>SlS?fL_FI&4aiZh5G`*QRWIVMS8_6D(jBEtv7>3dM^Y0M?`%dMG0T!w
zGKF_Da)lXG2CsdZlMl>|6VSiXjEplQ(nXmfqB$95+D`M7%M?k?$Q-jfh?gnuG$%XE
z)A1n9X;?4+?BT6yW*<{5$rNRcW;5hJCpCj(x3vnH(roNOfR%$JnX-XtFx|TjU}ee{
zrYUqkVxTBfwlOcJ`yYQ`WXdk44Ro)0gZu90UAQ+L11D4QMkZ7CGaaMC;zE!OGGCzk
zsO7jHY4#Y*8SI7YR5Imc^8nH}b>U^oX_m=!f7?wZV=WDCkp8$il8m)BOr`rb;A9&&
z%%^+XB<M70^px)R&4RpT!&h{FZ<;7$TQ&MZ_d}O5GPZp~kvP|y<ubNIBP-oMcnf*2
zW<QUiOamJyV|zEJhG4Eo;eK%Qdii&9wTvCoqF#P-2moXMlZV|EWbC;A<U6(~WbD-D
z_07sh0z0h*HMhAz6qDxBiEm-A3RlRkF#+J_RVTVLve^22wd&bdnJljUUe8aNCc9pL
zYnEBo>{ZBaFqh@v=%ACYGbv@R3YkoGCXJKn<wPS>d5jlihWdM@YV-zCW~{&GRej#7
zWTyIiH9vmTG?^Lq9=CbD=BIeM%vxX2KsDOqDc{xp_c=+{P;Le@%PXZCM%H>pZ%)>R
zW9XsdMls7AB-wqGat2p;!aeDN2N{i%Cds(5@~bFlt8BOK&xJBZkdCWlGHb9aC#!EW
zt5ym9UcKQccl@dfDC^MC%K9>XdUq--AFGmeka0<4@xE|c{N{3*jqw*{YQEEIRwnx$
z|Ju_HxEX(sNTHdEN-d{7iiAcS-HL1{kFP>|x%@ki4q{V&K#WQzw-{YKCX3D6zH*ey
z8kv6@qL3}+WHKXY8sMLD1u`;CS-K!=uB~q7;VxS2eIj{T8_luVGT93FItg0S{-0*U
zv@xt~VgsU3HsqQLvPs76^aIL7s)22KI38N2IXO86l@}VEgyKy`_5|(X386O;Z6Gi;
ziA*4U=lLobi7ulo4*%xVD<~Ww`cEP4Po`cW8->OHmq6k4|H=<v_>Z6#Wp)3zT-I?e
zFUUMeiD_WihiiN5a1T4)Woi}Xn`Z4j{G^s$Q&TyaFojE5Aj-P9PFKo=@!Y-rg3J-l
zD+&Pq??NxFtZQlLYpEgAc1R~dwi`t~drabG+;bg046&q2jiR8|ko7v|(L>XUS>iE6
z)0!#w*rXZD?DUA!bk)uKO(h%Lr~-;|_occRk58J8%zBS@+Sa&EsK5SEf8Aeyy`t?P
zt`AbkW<kGCm`9nm2{Y7#)eX~;@NWoZ1L6f(3!S0+SvhQaU-ZMGn#3}tLakv{E-WKc
zn6#{|2bxaNOvhS#Ey7JxeZ7vtLvCQry;q_aZER$%eLQMRjoSPzqL*%E`A<P$Suv#z
z#sIZ~RpmAZJ#S^L`5xWOJsXc(f&Nf2wBdi|{?qqi8nKN!UiH{wZl?Ykj;>5`hH1(+
zf8^nB{)5@?VX^dOMte-QbRT8<1s&plNTrh18m@xc!mz6FZ_t^tf2;{1Zl&-aYiEgV
zw%7zO+QB#cr?{i+$~Hgmaoy6{{>*@mPL{SyiK}Nd-M4;;-bkiPCCThX=+<Ow8ljVv
zEkLKo$_{=dosU`;SMCX2lTV;al&#)C@)g&3T!)m9{`kjqz2QRFfM8;4^A}wQYtZw_
zMx3PkruJC`Xo#nqm90!6)kkNEE~PKJJ6Rhu8E7?@N?rPq`Cc5|rzetI4Hl7pPAoBO
z$R*T@{Uqsu24`hEBy^;*vFqr5T_WkU9Z3wcnh|!?cG7%u%uZg2&&l_0B3-w=BGnW*
zwL$5>WZwNKsm2T^Nry*7+R>dT&c7kePer7YJAx#i@s^|Bc${GduN*5Y{z&|VJ*f23
zdAh$pkgl^<lg>3ixgE)06Up$R1w`lYfqdNQLAC$(7+sszkmTYaf_aW0Sj(#<DGnsJ
z=4>SF{8+l5x0#$<JAz6*@P4tf$ogiNn~1s9LedGtL&wUzJ?T2*sVK9vvcOXEv|}~_
z=BATUc^fjep{Cwn1C<W?NTe@%5X|mNbiKW)u6#?9|6?Rn@*ApULVt3?cOaE=FG(^8
zT?dSzAA{40#5ukL$<OQsk6pH>h5#XtsrY(48K@gW5|v2T<qPN<dXRoy$2bB%d_^^G
z{wJCI@K1f|AaZDGN4l<wBhAhAKgz5*#MXNRxuTds)!6-<^lzUh`I<^{%N|`zfMeUJ
zK*02dmEF8W1+g`xbYL`@DPBR>;crP|-$(a%%|y38lk{u5kVBikl9@JsB<cT}be5hb
zozVK9HLbqcFT0Usq$5?;!GqY|+w({@B9bUdekUicXOU#`QgW+_MAzcYRPP+T;;fA6
zO%y}o$i+p$L=hN8hCh5;e?OFXid#`j?4stC?b}V)Z&uNDB1@&u>gDQsM;kV=6J6;y
zWai2}@?CgI_tB-~<J9_ktdNuZyY*z=+K9|>X=HN8CDJUtObq2UWZ<{M<W^KVT|1<b
zv7-9E;b#r8ZEj7P2VatWGUk(bp8Pp_{yQ}!14*$&*YO`Jemsuo5^oVKC5meAFojG$
zd`0Ff>wmu|ZAs_MR3b_Zr27k-={mPF>1;kt*K=9KcJ?1)b_^f}%>`l`TT5;1hnEn~
z|I~)0I&M9wemF;}{nwD{-@8as(vL_JT9V{)7b-RHBns1SL}8Yb{HT_CG@XrFs7)=g
zRgWN4XbaLmRsV|aC?>flPnvo4J>UVdYnM$_6H$y${k59t){dikSG6RGK8Ij2PpRpa
z9jDT=Aw)ebgPaT0Q0+_GlI8_hx<6b*@^@d!aOGW+`x)r^0JBtd+nB-NIq<LNFQ$9@
z{rb*QlSbg@;RKtE^#Hn*4^%uMf=u4P42G4->pPrv|B_tSpUimZNk4lwNt_zd^}{l9
zx3e2vhhY3-W%)Le|9gYXOVQMFOD2%{_n2FN*?yFgxm`)LZ7tQTYB!lb6ikw*Q6z~z
zN#>82l1UY&m1vK<RGQG7N^4Tcz=I#@x@r#TtXWPvD-+4&cb`e;cR#u+9uxD%=A^Se
zoa|<_v{U9|ck;BPzHiU?ME5;I2>iX8t}E1}^LsHlG1Hey$GcIzyH(Qt^9-t!%QVt_
zww&AwKSKJ#5Yq9lsMm2No!=!YJvxz`YrU6Buf>b>{3n)>cc(R^^zsEM4SP%XMVVys
zY+s_QvQz!?^GQB$DCw6N$z(4-GO(;S>5S<^*P7W>dVUPmwe!#Qs7)ky>qpr5?Zo-#
ze3H1YR?+jn>pc-23nEd-T7pF`CRHZ6zDa)~Piy7m_39tVm}wW?A38(&?KV*}F8-EG
zMq$>+%50dvv9i&@#M5a!@jR`U6k=h<$_mn`bUEhkcy3&QvdaQSP{B|vN?2LfA#~lN
zCne)~y7tA24W03=dIKYgZu)aF|E4i%ZvBOb7Bf_*TlKGHMg1({`7b0{gjEoJzCWo&
zyL}{7MScGmR!P{tmx<Fp`36x$UnfA=eX6TF7Bp!5Yh-wiAIVKvX`rcV$$akyR7?4H
zMB3e%^l$w|`XlC(&i?utz`zhP{O3W!wv!QmQghNAvWlF@zE3<?7ZR$2eI^w|{zY_4
z8xwWT&jkK^J4rIViK5dKYN0@^p74uC({*JRl251~VA|9_Ttns%&)*N}n&U-g(r%HN
zpJvm2_;zw4)RC}}dq|$NmKb*JwiESt^}X9}EXGu_kiI1G>Pz>HnkaESxs%6rD}FhZ
z%m>qSJj2HoxQ|Q|ajkB{;o5H|)qdm!YSP<hNx$D{GO(|HX0@XJY4}(zhrHE$s$^Oz
zIWa}Y+aVgu6Rc5vcWac>{ifDrW=#`Pb!$k}Ynqc8c0JW*T_>u|I}KeAm8l?K{hst4
zUeJBFNu;@HDY+Owm7Kmmo*bR`J(UVqsD->fqbHF)!)yxg|M;_{>bH!3kI+Oi5K=#v
zeb<nhYaIGAmCXAul2_ONSby{-ik_ILVI}gOoJhd4jn=|!SS4#bg-n(P5b7Uv(kj{F
zLaO(MVN~Oi`dI?wPt0%ViLuKp^-uoD%hc@4&|@Q!vBIBN2eaDWozNP(`)atRpGh+$
zqrNkKCDLd((*dp1ZX4E&Y^Qp?kthDb{fzeE(3`p12q%B&bO`r9c0Ld8S@Y(CWp;dj
z$mg7+M|N?h3(fzQdedmM`Wt!%HeRCXwSDFg0Jbr1SYfg*Oja_IgG>(1OT3u7Ur>)j
z%#<?Z4l^sfkQ`y6YQT4tDPIGZjx#^8@cIPPdmP&4Br`7%aBn7IF$|w#4i-Vvhk3dH
zuAXK_2h#KB%iIeF!jGA20k=OR-;3l7bBD&q0491N>JZ2nCxZJdBP;<Ri23Laz&R$a
z65QvRE!4dSGqYnrdVx`12jC);+!VP>j1LWzAxyt5z=bkHv;c%L@}r=>%&dJu^Y1In
zA`7J9OzTY8jbM5NfbA-CHXOM~W>h}dqL_`>VLqC98UbMp^OpMIYm7Dqq_NChCD`Ja
z>T_VZ&KyXD<_#wP1kA@XJrR{+)0w+uH-kAh5}KJz+)A`{7Nb7Lq5ZQNw*nw?nA|jY
zn#Uyn0`7dKb0UBR%oytb3Yn;GNFFf*^!TYtm>8Ocl`<8_0C>inqfw`f=`jNhT)|xQ
z1+J1AW<(`kGF$3ER?W;a!$J+S{vT+*Vp8-dd(DJ?h0y+n5wno3WhTr<;aleOd?4O2
z|EeH-&v^8OryrSBpJA|$F@M32_lcRB4$ZGjHDWESqdbh}TU+Jpyx`#;`K;#udxF~?
zpnj(JvhM-;V=DE{t4t~2T<!4-%&zIP1NUnm4YgxAN{@4^NqwNwt%C<zw7bhSTzfq2
z19{Kmy<n`@Q+jy4nfX}dk-AE0rN(BnKH~*b-HO9K*FyJS8LJ#U5-p(`M^kq$q#vyD
z<#!<w)(eO%kg=8;jC^c|853l9|F<#eD%4;*^EU<x)lMcT6;<BFjK#c9wVRoyh5jC9
zTyMPFCzu+V1fOKwUP0v@Gy8kE{FymMlT0W1+xgJkEnhhg74wwezK7gl`NS*8os>`a
zfQJ|4B^!Z@l{@bTE?M4H!^1xLqdV?^f=1WYK&xfo63}&vc7}X#IRakn^kD-~`ISF!
z!qtT-Zw43qnKR3w8_hgCj!LF7)?9QzZ<s$K|JMX!E+Sp5{uTxiRp*D9Xs|BxFu16?
zE^$I%^o`R21jf28|Km@Y%HF*(CU>eHzm}uh>KWD^?bNH{J)G{{Ed&k!ZS4&B(I+zv
ze)QEL+Q{}>kc?~prZl}7aD%2mBbU3Qbi(N{I5sVb#+aX%bc4>aL36>gW>;^NZfa+Q
z+>yyUiOTI{oSnh#!4x%+@cwx*-_d*T!<dXn&ND+gfb<G;7g1ML1XJ(*Ri@tkNT%NZ
zD5kyw(M){}Vi@vTb%Uv|NIXL|ssEM5pS3V%*;|gLXs9D!8rLSl>y~@6;Az{&JJ6o(
z?a3|CkX>UChh=+o@&K~e#z3mz@l9}Ma69@Lhdy_KN23O;0^Rs0w9xwQMI+En-?|5Z
zEBXO#8!JHBRP2KL)>;}RI%<yM`mNJY7$3Sk3G(sFX!$yQF};xvOf=2M9hnR}qUh{a
zrfeayhnVFG6dq>$-Qe00hCzS|&GNtn9H*Hc3M9Tv9}IHn>#7KMftiel9(`TkW+;nb
zBC6rrRp!Z6utYL06bMLQuI&NfCUX+;Nj8y5yMwA^F$WevC7UU{PwT%NCTR%pPnkEg
zgm}i(y?|;N^ZXmAzGbG}2mT%7IS>ZlGab%AxI@09F*Kd!3pvp2lz;6F;X(O&1oc@j
z`38TG9g<%whxh*SDKQ{BBVX>0vH*GSAAq|eAF~@O;qub0O8ov2@*A{POq6%&2gEJ8
zN{8G%`E3eJ<;pu#An1X7KK*7z@;QWmEdM7H)qX0U^B%bu@;nQg>#h9a2Gqqtu>g@r
z)=BZWEdVZxq(Er8DkfqKW)CT<Dq;7qqFp;^`YPtT(EQg=aqDLwE-A_$z*309v>c?@
z6_b_#e?u_^lmGgkxW%1u0JT=UM7B+NKQwgPpxyr~8?g)%B6ei2P}mx^>K5+D-mJoP
zsS4r4dUT^vn^FIcF<U^|#jh6EZaqih+S9(bB{aTmP7#rQNtiXT19$%h30C+h9zOYJ
zI6UgnPTWuWOt0dM%ER~_=5CgO?w2ASj;|Os13Igg)q!Dc`<JLgl<L=CQ4p;<5(KRn
zRm<rpN>II72K*gW9~;UtREze(R-Ve9-w{sV<^FYq>T7P(Am}&>UMe8mg@-es8m8@X
z4Z<jGwjN%%>sw7n?ts4f`v0E&V5W|u6nV^oAS4f%6}_QW#B{~rh7oILF9;tq^UvZz
zDPa_sksOfwJ%=$*`Gf>s<}tF9!Tx6t=pL01Y!9o)<vCxGoRIf^45YVw>^$U7$-S`g
z!Jd}C`4M&XmFIiIG0dA1kX(`1(Xu>U?r{-@Gvu2ep@FjGMYMj+mfy++E?2&q;%)ck
z!6PBem*1oXaDhCIp2-LDG<!IH*&=!IeW(`84^!aok-WMZxe__&1kxw+@e~<-D)-`H
z{+Zly4us|MvbA7)F2AC}pj;vUgpDn>QeJ%(+zyJ-&M0$KL_9&VO(FXhfbELdWq|Kc
ztgnMJ&I%Wrz6U5=n$pV`s5n7CPliHw2f0jzt|@4;6_r(JupEUo4#NA2PPFdKQ!JoR
zMS)@ht-%Ww-+S!qY_?z9fLfO*ngxQSRPoCsC_YtmNd~%1QSchMaz!K!ye|}s9Kltg
zh#_-TiX{{kd8wEnA*oT=v17u%Qmn!D3HwGdgI0{SisbXiy;GR!XL+x<GZ<ta6%Sql
zP^V~H3gKtPXM01aeo?Gkiz+!PV{W2?Tb1MfhR{hF+z`#YL%E$My*rgXu_4LsQclLi
zo86<_b^``oly!KMSU2TZ8i@BQN0bBSuDo{<n){V6JYoKT@@_k5dMYy~pv+5|G6cyX
zWd(&Ejw;Wk+M#ny+0+x+6H3n_cyUrWfhu!KIk^sHKFVKjfZI>m*BxH?E7@eYAE2zG
zxMH9(WDfvA%0n{&IH&B44MR3qIjtSYE+|v{;Ke27wIRTTDCJ`z3{#$Xk1AbO`c?uE
zp^RNc-Pl#-h3~-@rEC%ke6%usBy_GR`?iNptTL09nb(!MrSRg0a!L-|Pf(UMgcmoJ
zA83+wOF8usgh|S7xzN0$9MuDECo3yjAW2b<`yMK($}e|7mZt1A5*E^xdB@;Prm~`1
zKsT19^eqB+j<R|TXmXV&+X9iNY;y)lzH$Hsf(w<}S4bWxwI@OIQ2Eu2q*z(w4V4mQ
zXgMrBQAV6V@>F?l49cD<!ym&$xpLTW2%jrM-Xf_~y7qygD&^_bXp(BBPb)N#y+&EI
z8{DsztFSe~zEQq>h{CtZ@UuX?Q+n?K+XrRAk0|@7tjz)GC*{w((OjRE#%oY<U=Px|
z!jUa~4%{|&)Cx4hb~d61T-(9+T8pN1W(T)`-CgXH*1+v%Kk32Z!Y*q9O;<as{u3tl
zvJGlrVjsJAIe`1wv5O$|V0)!N=O8Q2gb6S9rVRMQ>^7QiA7O|80`6n1#{g&^XMa5l
z_(?WC2@UMcrjCb-4?B-GM^3Y|9>TmIyR#we`m<5d$OW>>IWTmVwa3$%^c?#+6sqUh
zi$ySTf!#^#-ixdwy&R!zXYBE@VXTq{#4Bu*cd#4I_IU^4Rdyu>fFs#E6s3-4mH0*3
z7<T4Hz+>6zet^fZJ86EE%W}TR-Dg#_9w}gVP6Mux^|i|&En=f*A$iEIx(?|h_T(Ah
zAG3)R_<zD);^B8G8%Cj}XKZXARJ4rkRt`rURMtmG995sDLby$}cq@F`u1cUa{SMVo
zdY+tB$uvOhQr*cywRfxLO$N2AY7qs<+*Eh_(%bB=8b%}6e$~Odu;i)g&=H7(s_LWg
z^pHyV0u6Oo6&w$hqpCI(#yh5}egL~^s^7;Um#(_A4w_jihGsF@s;KoS%T*N)0N}pr
zXaI8gstxzRQlMIdO=|XmYUN<$id5osgb~<cRiPExN2;R~{3%h5ZU>*9sM=G+;;CxF
zB#=H+z1oaixylv+51*^NoKevV)wtiFS*co{3`^CjIoOhAYg8ZN!SY7cITyHE)#KaH
ze6KR@gcl!Fz6=1LRIO-Q_*s>Rz=ECqs`?rR9S5$9h-51_`V|VdaW}Nc1#>16Uf^cD
zgNaMrfw?dd!c|6qEsT2>j|RTX-JmU#aBlfi<RZ9EM%azyrW^uG6zAL-!WhnvcGRwM
z>Uk)O<N8xT;5yg96+(MFH)IiX5;#{1nkRA_>ma?wy{DMwZB9H5yLY%2mr!<>yNFXN
zYzp^i6b#<u>L|RQ#zh1`C4&o~HGd}enI6P!Zcu+DIh>v*`1iSa*ve<~xD_G*1zZ~|
zSPHqdG<Peqa}9C!gnh_W{R-b6ah3C6_c8ZH0bwaO|1@$>x%-izDd$=gP~&sIE<#et
z?fwzMD$d>knl)Tp9K3kN&84xlmb*-`qPJYdRH%I5p6mhOBd6{GyPvs-^!k6{wl6{(
zI`DR1I>+J2_dbX0Hok2&Jl)P0T!u3{_<Ko6ocX6+f!M`|J%gp)yu&__y6{;Cfpg_Y
zJVCOTA9xU&`*_I#@cn#XH~=1e=4~XN{HX2l=^)=c2R_~4!>6L!@qEH`B#FGmz8BJ4
zyf=k)@9-@t<e1FgErg{MKJF_>Q~BOz7);}ztb{O~*Np*NCcnf1zd;snI}4gzem(7x
z-RGldQz4%(#qkxkfIo8x=8O0%I8wkq<d^nD?lIqvW{M?zK2ewQr@z`!_>|8-0(==C
zKNQ^Md}HbZU+^O<P?-we_a;27;`hx0;w2x}9V#{azVDH|;(g?B`wd^CMkCbngT_Jl
zp7+HeAoc^lU>ywB@w1bV`^3-a3bL<!KU%3e2rH*SbF09mGI;;C2~PA}ItlT#f4oCj
zn}KAfP#20?>=Kf;!I?b*V}c16p|B2)x(O@y1HV^@SO86TVI?hj_X{chVDS_Jogh3Y
zG|7V9Lqggm<PHl3w9q&v#M9_~T-b0DLT|ynOo{jJl+Zs9+0%mWF;vu7aCiW}{e>yi
zrJWIOP;??t7)Ex_3JzmX-*ZAP%~a0|=UXGWAh>eiz9`UHDmGL&I|g2a3G$^de?>_9
zfFxXS_zQK(5guFvOP(;Fwr27L?L)xrg~GnuNFNBZe}dhILgT4mD;9=h)y<X&&LaSP
zB6#11-%o|%+W~wg{4y7$<-$f94WA3mCqP&!OdAfBDj_loxf<b5gkITK!is#r-w6HZ
zAgL8%Xif1>5Gs+p7hX?5&FbtzKQjMG`1dbV?Tb(s3(~JbCB@Ah#puIe+bSM>1n%u(
zycK0mB1iiQ&f=>3P}wQQ-vn;AIQSVf_lV0sLB&<vv>z&NVhh@J+b4$6<j!6Ev=e0>
z;<UxU9S|co19wogpKc5tFR{Z#AVS1{)<PO8#!-KDS^VuG+Utt=-2ylqAwJszFRqG@
z-QaJO7%~WeXwd;N3ig^f{Sa7U#o&p6Ul$QL!K)^^>_RR<WV!%wQ=Bv$nzzK!6r@iQ
z`_#gxJK`$)CXgnJZnKb06@Q_X+&!@~?Hy-`!^mK!=wAe3w%FMOl^k*F09d*&>S(7s
zPxRjc69r-|#Xt+i+0UW!P@L2axnglj9B_}tKw6xZh;OMaN=4%=<erMRX-F><U#zf0
zS}qR80V4K=*z_(6D?|eYMXN;R0@U!OXkHAq8gXL`%3g`;%W&<D82TEPYQ>{dk-Qh*
zx+3`?PMnEWs}nQdgY%OZK@)^8;>%9}d=+z=Lg*-M%7SpKw6;0CKO!xfBjEizDovRP
z{Bh~_2I!oSWY6J@x0Ev+UYwGa-+=kk(gB)d`bv@;5`XEH4#^p5=?$m^O0BygcUG#Q
zWx_crg_cU^r6o^c>4M}z6NHOWHLYAjq;(n?3YEfW-FI0UIgQ8rcSVwa1G^DYRTAoZ
zRa#Vp-ziEe%t8_^{d@_+SSesE*y5z?@yOkfexfjDytF6)xkM>45iN5|dO@1ErR+7}
zz9a21!R@<J@;2mBB<ls_?n&3nkV}(dX;jIOS_??*nNmFc_SsUJ5AZqCzITw`mmVKL
zE>8;X3Sfb>Y!6ztP-;X=!y>7A0#qJK-Vwk(l5Up4na9%kf5H7k`u8Z@E|q#wB;=XY
zjh?PD=~ExTpG$XWWA=sQi1TXfXKC<7kU81a8&@FRubxG7Ob>PTX;k!p`shTM_f$8o
zMRHKRM+-JDwLis|52?py0B~6Syax;(RlCwo-7&Ra6L@i4EqcSJ6Y49p=sl^9BWJwT
zM<)PxO8vYIaz5%-DKO-xc43kDtL@F&!NoxJG&=rpRvr5zXzr@tC?HHx&!zq~Rh>;Q
zz&&*b>Soi_ZF(U|SD*ZhBt!kf-$*jmHX0qW)DK!B$yPVQ5}(acUv)x~t6oTP$zpX=
zoFif%sfUVK^gdCSrl1kZ)Oq&C@U2|kS%CDpIvY<P`$Bz_Lb?^|DS1dL)yH=HFIv)K
z4s9~D3i}91>tElXP1+RQMD5$QDS^A~a+bi`_J0kAyu;9O(CHW)47yJ4wDZ-uHUm0c
z#*Koc>#wn>>^H8|xb|*4CZTrS(`*3rs2&T7o{JxXwAat%MDOKO0sD5(0s#6r+=cnR
z3whl4lfrQA@9hk_0ly-M$_^Z91l=I!5ZDH9pg`!*peMKvtD`4zc)~5{j2KN}{E?Rj
zLvvKrA-FZsK6U{LW(`b1W~qJ@Om5oo1U1;ow5Qj}mD$o0$q{B!FQ}bl%*#RP%j|WA
zFpybCzhN-r^@IZ&|L^7+g+Of&r&|Z_T)2{lFzw2*4*+uG&eGtwm+Nu?W&5}w3XiyR
z_A4_1+|LEle8hv>ej1DixJDEf^yH?wL3ofG)C{U#T<5n)4sq^&sKZfi87-@iao&9)
zJjwk;lQ?fKiDs*(xDnI{KAa;h<NY|tjR5#_s#9?74A=Mu$^y6zb5It@eYOundY0R@
z5MBgvtv0~!Ij*7=NY8Wg1SG-SV%h?^!2LkGLKnH0n<2c!4WuAn2xp?uYADxG3lm{n
zHw%)>T!ued=L&ajHE`kFZwxF%a8qc2y2^RKL=wr3H~?p&xM9IG|B2@Ioq|&_+~wOS
zyvD6j0ujr7Oo8wQ*Mb@<p4-$6!UQgYru8?ux#J*A<R*@SiCf&*^Kd(fYpp@c-sa!|
zh7@l4Y?!#qO`<*66fWrr%2K(TeF4A636FqF<1U(M8!4T0nhTu_uGdTGWOJ>FG>21C
z_&Jw*bPUOTZvQA4%;VB2+?UVI9s$h)uKgO+zK~m`2k8TD0+}!3HdP^c$SwQ_En3XY
z7z<|}ar=6K<uR8>zkLa}tQ;&)xOw|&8>y7*yBJk_%B^h+yU(}}v<fQYu9Dqyt}F{}
z`J7YWNHzO{n@QV$72M}>D68Z~Hb<_CYf}mH2p{?&speMX!e9;OPJ#MYT=Zag@tUjd
z2uI&=m+2fzEq5Xv_TF;qzCvh!$C+9|=OcHe6iFRdM%~jFZp~S!e&vRK1gQgWtY72v
z(q}m1#P=Z+&U{_~lAZi812lK@mzDs&hffz#Ll=Hs1j=0b>?=sz_!HD5d->Qh<o5Bi
z*MifX&pLtJemh@D!=(q`;|cHw_)=P5dh$6dk@MnTQWWA4??|p4=6}OcPWBYvVm%Tc
z{;fA0J<Ts14}dR!9GeHMAOA0PhyMKJF8D#u@CQ}U4B)*wfF+Q>7lX31yqbbzLA?4N
zd^*S5m(!8Q^L)Q1zz6f(I_O;BU$uhpB0nt|$tC{d6bM6j!)*XVc`G$(7;oDF(#!lU
zT54S3*S|zthV$_h;fUa!o1kh}`AcCiAIYE8K^VnHQ4A%Tzx^%XG5qU10Iu;7_IS|5
z@);CTjN@P3LGC(#WF#!z;LlcpJDzW_8)XUn{0VR-k$0u-`CI(88DLA|TW*2MZT>19
zqP)W|r$~1)uY8G@>Mq}kf`KV~28|b~{8aMr9<QOJhG~2dha{aJFrAK3X7C(sG-vX~
zG-Jx*A5Q^kHqUiJlEYu04V7FzmsSP$`M00IoySjeL6XmB9R;9(Z?Y0>h5VTh_$eOn
z(R8??h)>@KM<4P@7ML&Qx6(rC5x<WPXFTRdP|&7??{Y(h_wNZGu>-25d>KB>z+&jb
zb>yD$TPPY=#^37!)pEX)&a^z|FQ>uM3qFDN0V;SoEgUNOGK%k1@n@-JU-F$4uvE==
z3PDoC^K>fz6`!{PoUi#`OW@iYe(hpt*76qg5Oyqs_PC&iUP6r*RF4RHH4GjV{-zzW
zW5Og31LJYwJL>072nq^VpA>c+1KwL0u^1|+gqzfd`3Nm(6YR7wD-n+R3Oi}J=O;8;
zhQwbOv>M47VV5J|0m34B8v}(Q)Vtfy3V+a>9whk2qcB*g4MuW7kZpi77lp%q$XyZ+
z{0Ws1p?hoC4HcRMBNrxw9EZWnLKaO^uLwJ7n<!k!qjx((IGO|DRpA%vC?W-cMOl<E
zo1TPdA(ZAeF~Wy6@adXeI1+|5Rv7jgI&nhO_eib_NeiHQL-;cWs`0|<ACV*o3n}Px
zQ;49UI#F<zAiO2Crp>A(L6ZsGZJ}j*G|3%-xsB%{S*W7k_O8%$A#f=|)Ol#83Vmsx
z`JT`;2acu*_M6w>V!F_GFn-Dmq0?$`X9^()!ImWiQivj3_<^=vbA$pqe3UEr^#kdB
z;S3#J$`cy@155cr#AdJ*2s0K!SSY+Zj4C}4rcy<VgywV_>!HxD5Sqn8&|Ksm31z3@
z(-Yw*`_Eu26*^MC@l?1#LC9x9^$!4+3HPEwQ!bpLxz%&w3_X@FgiRC+sStjDja;SB
zj&?q(gd;<Ndnts{*|%z;nl{&Jgv<m~>6MV20?pULSUOVpMsTP?u2yJ9W9nPMX|)~F
zcfz1fK)e@j{eavD;Z!#?;z!|+4)CH*P_9PVC*jTvG|6XSMIrECgjgKj!7|Zh0n9sy
z_v!qYqqyx9NVkf=hd{VZyh~?$w~H@mJI6`fatXN|V%HU5aTb%#Ky#-!Gfal}Z<m;!
z2)nz*x9?$Tk2smmwYZ3V|3zE6igQoGpqn^94v4+tON#XE6T8w@o4Z(&3EY0s_ZMh-
zh|g#~eo#zyf+a6;{UMYc61P(X_^`Mw2gwn!Vh)@+D()f9V`42%DcRZMV%AaEJt40A
z71ER9#@T3YZ!vu`@TbIpP00C(yCY!Yv>4V8G``|-T1WVa@4iR1{l(eCVE2p|OsBmA
z#C3G;B2aAP2@lVTt7%prBzld4+vmjR!;w2L%4x|PEY4dGq5XoG^#gzx#nJedi@hXv
z?gwCqXre_;sQ4>QbHc<E_;L*E;n_dH!z*Grg(SnpXbNCQh<)5(@Txdd0z6Wjw*|r|
zF@F^}qeX2D+>R0V$3l2boO2zTv0@D!+ldnkXz_O4E?QQD^oIBkE%)NZ4q>245Pu1S
zr#Hp%bYd@2e0&Z*-4e&uAxRPsT!1sT#dT+qyCWX#4im}ZLT8vr6&>gayeBq!fwDAF
z<A8Qb7iVOEGeeyGJv1}L2TfooOZ<)YMY2V^Iv<|qh_4UBV6KSRCtfabQ$qmr#P*XQ
z%opE2K~f-Abp%bJ*q4@q55!@qs7#SKgw_!c#W5<FFBUJ-cFrSl#Xgih7O&Ik+7fZ;
zR#f7NsM`o(sTiGv>OK|SL})$}i|uqQs7xFi3!QQ?usaH$i!KzRe<6OMQ%M!#5?9oz
zQVgKY;wrK2M&w?KVfbu@trjog-~<-uesl=ymAIZxmc16o_k!jdgaII|6+>x1`K?&f
z7v|rIcWLA3z1W_-{~&7IDE|FX+`1TuI&me=)nnzJwHd<CqP7LR_#%#?(EL}i&(CNX
z2PvCOI7<8;<hDvb(~5GNw2C_2?NaY-z@4OMilXn34#dH(v$TqWraPtkHv!lsJ=g=d
zi}Yd*0IpK?LK^?vq<-Im#$CEbp@RKV;g7KEA?={8h=Y>P-#~at9j3wILsB>TMUP6a
zt<XFs#nM^W<I?X3ka$b27s13S>B~MC^pT8P&_I4tWfpS&QnDTv&PWRy!R}cpU=@-e
z=?T6Nv?F5BjwXWVrD+s+3zk}b#qWDTT19J!i_(I4ID@`}evuHVKRy6M{J<Ir%`mAh
z1T>eW_jE?+iZqs@J>k;lad0L=iVXqas<b2$Nu>1b8OoxhL=K$MQmq~qVx&vAVAg(3
zYFrM#V<lGs+;P&p1$YFmOS`&2^@h}k4n@UF4=JvcAdRPkeK#dX+A&I$oG-zPThb>w
zSf3;<qV2xhQm2J5e@B`_al2$`$&bL@l~Sl%Pmwl119hqtNVB?oQU!e(k!F|NDFl=$
zJs6E_mZYO3TiUS!+&R)=A6Uwj7EK4ueJPd)K2Iv&1$@4Aj}|lq(xYxrDU@!}>ga)_
z@IYG>Njm!O=Aq>C7IurJ6ZAYjk{-PU;IY)e1^$*uFA)4hyuv<XG=Qa2Cklf<mEO>?
zqi0e}8!VMcPwC`dIU*xKJeRi7lJ|uqYmBlA$;}U>mC~|&2&<$%mw<aI<(ENNEoD%Y
zw?;ZZ^Ym9z2@R&NrP3BK_(qySq0m}sJcX6sO3wC`z`v7Tli%;9{=MMh2dRrI5Fe#g
zw1TRW+S1wfPf|l~lzo;K(boMJsaqqo(^sh|133rvWr|KYs=s~*z*e>D3(B0-q6WAf
z>a|)3oz+G3GwoET`~$!)^@tKUx?9~~q#ZhY)WWaOaZy|72$rk52QA6n)DJY!*{i<V
z8_w)g`yGLKcXfMwRf=eh4+Wb%)HBuqa6lcYMb1<Gl?IuEYQ7H6c&VGv?%N@Clfe)k
zRxdpQmLux<Qz1O6KH3U^W9p2L6n{IeUQe^{6Y6Suu1>1|JOC5kYF8u7pHhz=k4E%S
zf4dASr`26)X5p(2qe+jSI*X1Y_^Wj^`8cC4r;la=)QNTo1J!MQhNZLWbuC~%NbOh%
zz&Uk8+8;cx&ZT8su(}}*D%#l#>L-gJy{K-~95k2I`3|rYqHad>-ca=hitvZ2-E1HY
zS7-NyW`x?u3ev0UKi+~gQmv0e5~YrRgE~d4-FAT`Mt$`yRIaK0!$20RZu0?Taq32N
z3irDDLmW77sBJFr!XB?qJ%hpo_3SY)aZ`QdED(w6R(+7%QoHsCB1!$%J(S&6+i7}r
zM}3eEh9#>DXjOMt{gz@aDeAu$LNiqzNju~B)c?|gF-`4$5niOL8?}aO8R~O%oIO(=
z>j8hW)WfLj&bF%u>43;lJEfyASDhb<8s1kY&@t^i^%zg+<g3dHpi-c2`4f^N_0}Nx
z{ZK7_fo8FK^Iu3x)QjnJu_x+aTC<d@%^ARzsdK_1ELU6UTZrfC;k3M{R8Mn+YgOv0
zxxl?t+Z|}b?3H@-Vi<g_UYh{bH|p!u3)HIJsoQ$1uB0Py@6=YB41ZLA7Es?hb?S1^
zd{Y0`3o4)0o7J%NMg0p+#J;Mhso{l#W;;cP9W?>BklU(>qE~yH<}sZz-L9G51#l-#
ziroW<9hwB1JveL1sK45&S^NRbwoBtji|^f<BqPf9XnvxzWiA?b`sTn@!!t<SGy}T>
zzE`u9&VKIGR8Vi}u9;84-u;^E6lL(xEE)-w1Def$BJtEX)2C?%HNm?8_tGRr)5Cg5
z)1AKTIILNM<Ie06%@RN0k80Y+L+6-gV^1W<HHI4yp3o@A!^4xBi4n+oYufsvhNm<m
z-O*}3n(?%Ob6WE=1<ZXld9*3zr#U$S)czVLir1gf>`)*H&`4?|ftnl3Y5(c0CMF50
zK^kW|B63cnqo3lurZElJ!J2_|!0v*kS0zY8G=IKBS*XUJI^8hMieF(cTvJRZs3J5U
zX*9g5IgkyqNKFe3+9FEhpAOAvP2+4($7rq&N7*$^$^bNMtj4R69PeM8riBYguWQm7
zSh}HEfUnxwcuj8|atWHTWbmeD1g**vHOnIayrubeIFcmI>nliZYw~Do`;KPk2Y8XJ
zIj2N&SK~PlmQpmiv>lYH!I*}(LL=gD1F&hDaj76n*DUJ^pX?c$27`de)W}C8$<mZj
zTq0XD5TEa|Ihq@u_(gIx9WR0AzUFUg%K}ZN3%Cn4FX_2@psAuAwjxb@8wek2-Y<b>
zv8MSwBqbV-I)f*g?)8CO%^-?7RB0Ic+~cLD^ghg2+cigM9IMg%RScR}8uJ~HzScCQ
zgDP({vuQ)KR)f>qcn>sOTh!v6=E4qm@m}+HGvGdGiYW~9QB&)HT%BeJEwVmo`Z^)`
ztjV5?<csETIm*6jJn1tU2d(cF035Y%cEQkAt^L7VaBtHlEyM4$UAu{9vrgJ;P7v<U
zp7;%kv-ZdZRBfj=-3s@2X=l*^mEBr*PY7MK3A6xn)fNo}shhUrJ2c*2ZPZez?9(o$
z7v5dF<~x+_*UnjoDtTxl=|I^5ZI55!jHfovPA4u7Y7KOB)k|A82?h^ob#w~rur|*P
z!Xw&+^xeu)E#Cn&$FwJ@Wshqo(d7Sxwy^}#lUfft#O1BsP9Kh((*D{AIUns(decv9
zEo}kt)#lUW&QJTt_W<~7cTvD4P&;Y?#b3^9+n+%#g0$YXaO#|PSqtc#*RJ^nh+yqq
z>R&HtZ_~!pMQyM8Q%%~9QK(voHoh0U2-RMhfLxfixEb8OtaZRQ66_VNf=0Y>?Y&We
zM`*XuQKhR|<w`gcsr_^wxhU-piQ=Ep+Dk#e$7r|Gpn6R^pF&}=+QWfhi_<=!n8kH%
zH~J}WXcy2HalE!73%LaC!dRHNsqMWN@I>t;T1DQ{4*!a(C26NNLfLI?<z-axj`pw7
z03>U-({p@Rn@?k7iuNRS`|ND0HtH})?`gkuf~RTPc{;R3x;Ek}R5P?*bl@~oYnuRJ
zmbQ&2gxT80TVWzc`zRf_T<u|sB;425(y@emt><xgQJ`I&46;J)FZ1EW18sgFa7Eg7
zzR-NAT{{}WV(p+(XxblXkNk{kKh};M1{X`TIx_e~I}&HS*;4HmS_?nZex_AUnbxf<
zRLZrPGXZ$6-DLv)g?26t+ZEbgkq}mDXHy8gN;`50%3f-R^#HtDD;tSijdlmM%q#7l
zCdk!l57J=#)~=mMgVZ~1(H9iH*N!>{yC1Z({y_3k`#l|ctJ9wP0e*kdcAo~nKjSF_
z=@)I}V$}Ytc5yHg2VI30!fiVJP~f)fT<JiKlWt@sEbY);Z;HfO_eF&FJ9W=#g}F<2
z<`Hnab@qkpAl;)Y>jWJa-IQ9;xauY+LB~xOKr>c%UCDW<?AHyVPk=pij%(o40bP0x
zOnB-Nx}w?#b+s7~dg=an43$H=UBAPN!@4HdkQ~vSpnmnJZXb`bW4e%2$Q{>h^@hC@
zx;Xo57(A(~qC*|ty4zb|_mplcwS|waJ55zj>z?|<lCLhD_J;j*VH9Qe*L^z<Dra;n
z&I1>q>ly%Ipf2b;Xr9$Y)6uygT?RGKIbGcpRN}mDUJO)%bsOmEx}XcNAa_ys?i8*6
zF6qp)o(j?Jq|KC2-G{@dOqg!C9Ky@G0-6V2(aj4+E?n1+9*+oJS~$#K)h*lvnn+#N
zJh&G1pHJ6xj?|aL>hg6E#_3wnLg>0KV?7Mr(1p`<FkaVTC|DA7A$#flyQyP;L_;O&
zUU!3uB;9K|gmPOqy(7H1qx*+C&t#ov6>@iVrWgQIbpEu;xu=^$hicPw!XY$5x^8rT
z;4*Z<%|Vu_`{o!dW$DuCJWsCf`y4oWUw35`yvWlrBOuJz?deJHUxAL<0M$a>;?ZcY
z2f7Y}fG^Trr5(J7x@_7dE7l$O6^-ynr!~XiW1UkG042JCAHenmdtJzt>Q0Y^=2M+3
zjR((kc3(JCraMa;isd>j_1VvLGTO*|q1*T#RjSZQ^yt_tb<608Zk28Twi(%%x=b~K
z2GzQ~6lJf`^?eVY-s%($;mkW-D+->y*Ufqb;Rju52dI41<#q&Hoo+jYn?LE&y-~H#
zx-}I3`JyYP-IuSr;RJBd3qf$rQQwF5JGSaO=AmqxUEh%&<n8){Pa$>IU!=wCPW?mr
z>~)uZ!EZ=*>kahE?9m_A0^y?1qA7)|em{pMb<<B@i?Y4?mPu%!{rZ}jaK=MFWfO!4
z^b(ym_0*r!KzL9;lfvU(`df4o=aAku1S*I1c9sG!NA$O8WAUi|N<0dW>5tGcsN?!k
zv;p9)pG><Er}T~K%$|>ab_4*Y_1kEU=&LV_gwRhv<{LQUuP@pK56|d7Q8*(&zv3JW
z2I{9#i=NeQks%kPZ%e&Euzpb$k_-BwcKSH?qW;2fV7sKxqi9=*KEFHgq59@Vv`m=Z
zo3>pp>!&S;!&meU*P$7%pD++A5qiU2xP4VW?Ig+~^^@p8PLzJc2XII0e_IZpV)Z2{
z$i?YBucLjh>sQl9k2mxN+TV%SA8SByqXd07k14av_Hqejcl0Z0^D|lBJ_uxY^>gXn
zO3|Nx2Vtsy)-4F{>8&>bPt!l9U9oh1+#fKMp+8Ma@J#*GVrXXRx0vB)w!Ym>B=_~j
za{<WH7d(YZzTVs#&KKy1_W-<5AF>-39_R<yu^q=2=|{H(;-UUrE7Yu5zk$}WkM#f0
z7Sdxqz8k`WulLvvny32q^u9jRub>aj%Jd)d04Uc_`4(l*^^TXp{X*|R8>1EaCUhXC
zQr|lixhj3=H>l@JeI1KjwZ8j2aMtK|w4|x{D}B^wROYq*k|Vg^=;zXW>Ye^KihI7-
zhtb0AgZ>Jg;Q6Tci2=S&|Dq*?pY%P`ko&Cnr@{M+{{3W__^L0ufZSHYBAO{~GdR(C
zfbE7ST~X#_xJpCv4#W795IP&wezX+cY1sb`g}V&D4nnfqP($CC?=ftmNU4iq_(KR?
z4e?Eo+h>?M0;KMS$_sFRzail*yznq=phE@+4E|GK*VB--5P*Y*{j}@uWiU{*_>iG{
zA>fA%9`vXlF}(H%%TdF_NAyMi2}46O3QrpPa`+9s4KFC*a?0RL8=O9dytl}mHn`9-
z%-8Um+S$(#N)s@D!{|4_oiQ|QfR+g`bTZ(H4>WAJ1%u}dlkY)z-q3-8FxW7h28RoV
zCnw?BMZ-ZFAuk!u)1JCL#L#LX*g_4ro#9lNq09$W3pY5^q$9#`hoU%F4QJQkr-(EZ
zzXU$YAfxbFwBc(BaxsRV<?!j6;TcUaV-1Dn;Epp)+>YeBp+*mt8-{P|SJ{ThrC>=k
z^sGX1%P^Z(aY=SVO;;GaZ3y}o$sNOnAQUDWifA+NuHkYkxRzp=J{1O24I0}0xM#2o
zgfPvZq7EX{FeDMVEW<V0;m<ZqRl#nK;ncUt<r-R#LGHfc89hjO1|vmb@(pJ_KvrO2
zXuv5n*qxT55g!=5+(A=hctfY~9~o}z;LKyg8fV~33@d5j^~6wi1i(_mgj^&~4d=`N
zJTv@GeSMkXM;~yP8yd+`R$=HqAI)89xI)XQD#Ik2mAy0^rn6(!h9UGtOpQTFUmCtL
zT(sNJY_AO`y@7aR_$eBQTEj=$<9=(H`w*_ZGwh)nel*;m(0QF9bS+xulc8)caGwq5
z|3TRo!>hUA{%ZJv1;D}BoF)y9#?&tmZZ-PR@4C$xJ{?usZfw&WWllzcCM&y)_vX?U
zRlALA8^Qb@<F~XRcQGpHxpFnm-3q*$aVAyN-PrOs*xhd&O<`gW<B5?_IbigygBPAg
z*%l-Rjd2MOdKrHo3$jDTwHu*%*f^>?;75#&R>1C2V+k#8jv0OF#W`-QSw%;oPZ(pU
zH#liD(lI1&<M(tn@RV`!3y}I4AJIhhwDC=Aw6m`<rvy1a;~zAB_#0nOh2|M!Kt7TH
z<0Lwi6li>$3EWxZfP3H!GX72B_;W`8Mi8Dirqj+yurY)d@)wM5ID>3wFB*ep!?#OD
zb|aDyW5RtTp~jo@fe$k-qbcHL<E#e2UokeM9wyv)tPFLEFpeIFva80~=izpw@wg|d
z9c4`2f+X6wM}$g@F_G3**NmMyfh^XTv=+iRqc?47TsIp2fFb)0<Lueci8pqqJ+=g6
z60M4E8n?HDFwr=8DY$PL|D1?il2N%8+_#Mvngf5w*mXMq$;Rm=D7$O)L1)6I82cxn
zol=c|PXo(6W8Z@?k!I{oyC&(zatZ)u7!|ZC$~5*~hO#WX(M)H)vyI=rMv`O9^#L%~
zc%Tys?;B%I0+?s~a2L6Jqx>511;*0Zuv=*Sjs7md1LIbD4U3Eqh~=Tt7K>c5F{lvE
zJTf->4l0k0Z>xYSG3NaQmM6wrufSPqTtvg|Q=|RqH6WfDt41RG+^D3(?JtbKe2<o`
zFz)ya(n_PdBa$j(MK_eaG<r=%Qf>Sp8`Z8c22#}Nl`)UzmamPydV=hYalJQ8)Ebv$
zz~EbB4K?>W<GVBP>Amp~otXV#9P<lsAC1lJzF?~}nrPVmWIPfKozKQW2f+QsxXKE<
zUyaWwwCZ5$Xuyx>Xu3t=v8^WGX~1nWd09}l-Si%xR<cf}Ae#T}FeR8#=4|@wTL5;N
za%;h|%Op_GwA(cE6Ouh9zmf35#S}1*rsA%q`*hgC&GZMIU)gI?&>t$<XEM?p!re4;
z2t3_y5*(0tm==wK@PNrq^Ab;!G7Ip7rd~wqW$Hk)&_kw|KFA$5HKkSD5z`M8V?Syd
zTK@@ysXuiv$4y?Yz@0FSA57!lNmDH?47^P<sG~V$T1SV6d`zbfB6r%fiR$ZX3ZZG0
zpJ|i>+S%VUC<wVTropq33oy0s2WJ9Jbu*BhHR+!N9%TB5-qdrZX?e(<H?^Tn$Y7I?
zFUT&KKG0V;7fnOZzIOJK=@A`54l&u|U@+7);7_zgnCWj8_{*jRy<y^tDeVF9;il_X
zU?RfwXM5zXn#Ry443VZO?*NZ76+QxYw8^XoON?nrE8wn~_UgbAYpQt%T%0Mi0DyQ?
zK?MK_rp>`{&3@C=gieqrnkr~*c+1py1`tW6Ni>+>Hs#Stl{=>X9l)Jz+UX3tcTEE*
zn3`g0?FJL6rm=lMde0P*gIt>F#S6gGP3P%@h76P98&ovYw2{JFS*A_&bY+`%t_C2-
zBy>S8*KV>dfzEx?gQ?KTGkxBPT)ru$Dewg*{vo_5H1%GF+ym1w8h49Kj@9t@p=r<z
z<cdv8cf#N!)6E}|du+N+Ylae2+_xZmV&W+%Qfi9&6_%cw7El-b%(T8EILk~yv?*S0
zvOmoP+jEo8d;njVyp*U~h3OTYeW*13=nG(#X^0kVFHIg9@S@tZ_&elkOk0{l^OdR7
z5SVyvlC~pxW2&BuvRczgI-dR3^fnCC?@WRHp!wdkh7Rn0Fzu(M_eWF4D5%t#%IsZ{
zelo4S0QWzeCQpOT7gIJpUSCZIv><gbXVF1RM{}2EaCocv-$DSknLE(IukGf8alkp5
z*Zd2W9p)hcP;oYoqm|lDv;Gpy?=mkN0?ys$JUSJ!$Lvu7^DgEb3U;}gkEhd71UGZX
z0MP6;^HY%QGY_YEpu2eto$lCg_E-TG5A)1R$Q>{*R)faV+-(C?4w{{opq;$TsnqEn
zGCS{q=3(<_Z#3mGv-AKS9yfm;g0d6lP<nz+npcD%=WTvKr`}GPJKv$dsN-Y)t`?r2
zHaoh4+t=*v2rvB1o11~#-|VskcF&l7Xx$iK{-Y!82AZ|Bp?lVRwg_cG<{Uckd(OPL
z3slaVpHpBd*vzLPcfmZIf#yYX1FHQc^EIk=i243%SO_(HBBE<&!_0kXrhD1El{UGq
znCDZog`4}(ZbF3F{VbBJ=7IfCnMiXmZ3;x07f?7p+I*!Mk{GjBYb4jqEvcW2H7}=4
z?KtzirAV%u|KX9`FuQk$g?MvYI@pt7?x{oWrnx2zUf2`Oo+IJgEpusWs3w_Lh2sah
zZSF%c^E>9w6o5!JM|z`9cg^qU>#7v98*R^~niDp|;63w~wV+8eue*XI-8|YIxD0dF
zVc;^&mmfki%lxG`YL;z&Nj+1J`JbmK%Qdg14`J`y&EL}UCeQ3m>+^hbpH*<Cz#Q-%
z!a}n*MI#@WztB@wWd0@;u01qgrI~%PIl4W}KQeRGD0^&nNJUa&eiZ~qpP2I~_*806
zS_sXj=A(3O<(aw3J-Ak8?p6iPa`P(MOn+{+FQf^|3-fFl3M<U#@c}nmY3@86h${1F
z0W>eo9d^R+YO{%s-`AM$G=%0Wa}Yi9Z_UGL=J(F5n+Qwq&E2m+^Mg6&F3LWdkA8$^
zo%viK$Ud1p2f^THbHl;NeK9*X0pP3IY@Y%X4wlT9sEng!xGQp7EzM~XzRePQ3Ayc-
z)=n_tWSK(2m>rfBZ{VFR(`id`r)B9(RC||Y8y&CMZCOT#i1%1tC&N(}%g2c@?`rXx
z24~zX^Q(~CYk5Z9`aVk#Ipc0|A4%iiev6%kB@atFog6t}sXl^2PfPnZFn`dp<qi@r
z%fe@%Ib@kKAC?YVdai)x5lcEn1&>;`(v0(%rTsS`J8mhX!`LS*ZYfYXY5AE#N!}KZ
zV<<ai;i+fxvHWxd9-g*ry+D7_!Phc@`ffi<zaLR;e~al6RL@xYM?)B32~&bC&~mdS
zES<Ha(U22lxfu<WbC!E^Ky%*WNVCFV%Z9f|E?8XXm%M0E(I(<0i-!;3A(p4DU^mp_
z@)Lw%mdRSET(;N|lfkD57MA7`;TF%^V2iK>41~^AOVAhqBQ1^oflpDEQWvO1TmI;e
zmWi>XZUp|Cr3tCTT1L<ZV{sO47+kw<Nu=QV4NF8E0Pz+Zoia+Wc=Z9xP0RN*d?s4*
z>2UEa%L|%o*^?~o>7dPR%alm`26rrf)9zNXrI@xm?^?P<0+C|*iQ?(0mTX#9-Lse$
zp=Hu6{_!A9x2*aB!VJrg6d=m9G};4UmZc?~8_Txrv!d+2<+&d$<ykIM>^a{u-3osT
zEC!t3Wee?=A9ln11IwyqkQP~{(8A)O<sW*kiY;%p0Qktl)3o8SrNRk5m00kHV(^Yx
zuF!F;QcIUHu=LcjX%=wLEZynRE3@1u?s7}wM3g<ZL^cNX3yYsWR4OcnaNsH}J$?aM
zmBn5{M;>2V_Fsnk)s}%#K-5_LPJ`x^rH&5$y|$PvV0&Y!o(-B>O9Y+Acx#y$5Bxie
zcNjc;Z*ic&{|5`Z31lBFK4*}tvkal=>nBS?+S&hX>30;kFP1q}iLaJ1w1jZ5F15Es
z*3mj>9O}E(8tejt+pJti7~F2%NRa?1>&j%<-C^z87?zx^v#1t3tyUhSyR517ZOd+}
zfi`ybSQCN)aIx+)fYa65&JCJw)>cKZyVu&_095u_r_eDJck9($knOi7deZpkVePsZ
zItQ$b83<47RQl5Mptb)qaC=#gCc^w7tMfVJ4qJQCdiRL6Cxhgubu9%Hj#<SCz#X?b
zQ8#<S+LX>XpS1oYAn~@YxeoX#>#wwa^RWu`aXf1({k<Pw>%vwP3ih)O_=4K|TgUZ;
zi8I!vdekDodYATf1FcamaOSMlvjtRwtYd#g?woZ*PpF)?4yEm|VC#4E7eg;tFVX?m
zi`ECUzQ1IBod%T<Yq#0p47Cmmg)q#zq&IxJY~6SefGgG#P9+=3hFhDhhcwa}zZOZ9
zRY3vxXlt7a;A5<VD4c)IdaDhRSZfFR)#9v`bh!Dtbsw$IZ&<JGUtzX4q7%xA)?5k<
z-LlRpfL@aI7zK%MTctM0-LbB9LrWxEZ8TiowPr6uF2(v6otaCurqYR)d)A}p(Vl5m
z|2rT{x0(*4EW>J6z@bd*_dQ`P%PMz)m)X|7bf_@LT2KRAu66F18nE5BzQV^%Y@YR>
zbHL|YbuR%durBgKS)ujvHMsV`TI~Z9Mb_Vk0r=2*^dV@9t;I{wJddme9(gMo+kbaL
z=Bd@2R`buSO=y`|W}UJUl;u`eN93McV`-K6!aCp=n5(efX@R8D+Lg`{R#`pX!RwdS
z(m!Ff+FGInuEsjI27p)A(@oJ5udS)H=6hrP<tfT)tt+Tocx$x|fVc0g5q26O-dnr%
zhPxlEON(LfqqU08XVqCp(@~O7)<w<1{n=Vg!L2XWML|&cYHdo}Hx9NMJIWkwgXv56
zt+qxoB-?C{+acL*JKGRtPPQ_dIP9?5Rs-N{bBKeXowilwFuTjvZlN97-L~(d;P4*X
z2s&EfVjHm>Kv&!L%}CsA=9vKQwFNx`VxMi)OK`i};^_SAe%nHtl6ly2X|Z|0mP8}4
zr)|<#2oKuUGSKw0z3L1Lhio0D0Djmumcly6Y%jx5iQ~4|hV(|9uw5Jn#7SGO3W>Mv
zHobzUY^Nzg;A5LY=Os?tZqV^)U)y}z#`LodBvOBy{VHhA*k(3C4FhZ*^i^u0Z5~ba
z&)S+a20Y02OEC<dvlY;W&3W5HcO=2KrnJv{!8RtHMx=|jJMBSp$(FJaCPHj!)PIKB
z^8Mj(m@VfBlFPREyFgsA{rM62aGR?DOA)pVT8vz^?W9Rbq-`y&v7>B0^I$&O=Hv;L
z7~4ARzp&SA2a=GBwf)Y4I?gtC4K%OYF3d&Fe#6$5{t`jFZHE_t3AVM=SKYL=U4?2V
z+Wr~`ySHrrq@pazHvR;1w{3Ye9k^p#LgDsgn?IeLxobNg1zd`)oMQK>HXnCz-?OQH
zhTSw<@+5eXZY%7MT!t<DDBzj42}5Ba%WmrzjKXYNLOu{VwuaOz<=TSJLFc~hV=@fp
z*~U{~GvAg&`*H=gDGo4EXe-SE;DK#aBH%@~jBuELXq)&Wa>cf*O5`5dY&9TzY_rla
z#}eC$XaJtrMp1WEYSU$+?5WM(atYFBHlJ)1mf33QxJS9|TvwQQZi~<%d0|@;57G+T
z09wyh+E$GKca`nmB#^$eRZyIw+SZ%4c4}-N>HT?Ss~8P`U)%1}jQx#mp$gQsHkpK0
ze`|B0uYTXzQfHvm-rMr*i&6N&R!s*8KH8?zXMA<GMB0Y=VjH*#xv#cZ>LMK)>}d)U
zjt#gp;I}p?`~|LUYfxi>%Jv2b%;QySFpt7uI~p|9fz!D`$sZ8zY>+_vMY|e|-VMO+
z2LFen>yFE^`r?|SG%ZcDckjIyEmvt-mS$;bsbyx{mZ`t8vX?Cg$doO6iQ)hOSpo`(
zpbSMsHpmcUZw2)CJ^gh)_nvdU=iJNt+~?kN&V5*00TDOGC$nJQov~%~zlaFqWf5eK
zF>X`b+mn$?NnkI=j$h%EH$y;W6F!U)`qrl}<9FI>_%V)Wp>>>5MJHE(MhY9l4q*IE
z8IVARKkW*F7*g8g1~Y1;7<LH5Nb6}RBk3hzo?yI#va~s2jDIDw@ce}{BE}&a!3bRs
z#Yje431FfaU38p|X82~nQVio&PmoxKUJa2r#=DgAk7s<b93+7urkb&njNj<1CW(yQ
z4)Ey|V;QYlrx`Q2;3Y8zTS3k+0yY8VEMpzzThB4}qEZ$S5ypE?P)ufY(y=s!ksF7J
zy1-By;YBK=&>y@shBrl9(it8U#=gkd=LNJ3M&1i(WitNWj#d_<^*l&6qnVt^VW_F7
z?h@kzIwIsUc8cLs9^?J>Ao&b69mOs)qU+$H^$O#N6($N8=V?D($k^b85f(8PB*Xkw
z#=m0NEoL}w1k5$Y$zB*NVa!WJXDMUhBrIKL$P<BfgW*NvEn}3^4yl|GRt1p?#xMoS
zD;aASgLjj0Vj&FOVr=yVuZoeF1ijn7-|d%J*Car!j`1g5o~mc8IS1(mM%e+_Y-U&r
zV5Nm|<yGjmGQwTJyT|xy8AjK}P>(>bo#9OZu@1%;v^aG#ex+K!`-~b2Lv}HiJ&!+8
zH$yv&)&s`lA7QhH@kS&_FXKn5((7Za{O>!b{fwhMz#d@KeF^3u!z%@#LkuS>^&e(@
zN5P2^#wNP&Fv_?^KaDYlI2UA`QK`asCK!KE=Jz2ZYXamE<1Zn2lZ;Y23QsY9Jqt3;
z@b-Yg$BcCPc+e9De?D5a%$Wx$DsRUuqzJ1$bCTxDfvKcDyd(1v3tl)e4^j@%naOF#
z(2g+QPe-Q<^MV6FU72B#;2mWeFT<c4Gl=$f?o16m&mPS1Rj_o7S!4@LPiD>%Sny)H
z{|n;H6jIf-4|8rIor-*!3O>;Mn4w|7KF;JEK+B)`21U>Vm@B&h8pyn709p`pw?AA9
zW{&m&G=v#M$AeI2`ri;a!E~mxP8hSe2-xAwyw{)*!DKxL63Hz12fQfeAbl$^n)&+-
z7>Z#=tfT_9SmuYcZpSgx9WfX2%-}MhB`|Af6epRs|AHhkm7(zI6f?*RlBb!Pe*l`q
z<WiXV46}!7oX#?*{s+)=%=eRF;ym-nesm@?bDjV*g}I1QRu`CC=zE;0%%}T-nZ~@<
z3UzBbv$_?`i_GeFG&7i62f@r_ena1P$YL_)LL-|w!w+_InCu$>y~Nx>rGL3h8!9un
z%seH9`W5EN>u|e(soxEeLT1wgI8(&@UjUrB%8a3ebuqKU0Fi6VeySuWVQy=HWT}<u
z;|>?EGk>1IT;5=cK0>REDeHtrIdd`PqbivH%FtQKEThckO=epc?A~I!N<gZZ<rE#b
z&3rEbK2<Z5{ULIPDZLHs8fM=I(7Vf=L+ANgW&>SstYeP<w@G9!r1hYIX?>Y?ERD>A
zbhv6_9>|1fGjnbg&{~+we#MluG6N`~bdNbg1#WH3YTB5$Gl!R=)xoTw1bruyL1m`*
zncFGp+Ql^Y!tHM6fkrs<fSEQ5(!+d51k%gAd<P<Z%oIPg`k7K|1JDMT!X}VG=Fn%b
zG{pRFK71QymeFf+g!#ow;EghysAPAH`N4Z|bewsm2_h5Bg{1zF8U7{=K4OO0fj7x~
zQ-{CE6!Y^BFo<d9g*VW8%#6itoH<XJLqDO@mUSu^EjyO$=T<cBSp`2~x*b?s>A393
z+C%$NCsxZRKyzlX=-Z}8Slf*-@4|Zh3EX#O)doZFDC;XKYj9)DY(UGMRYYke50;36
zzsFdPwE**EeMoNxFV?f4!BKD4?Tu*pus+%g5nq<f6W`gL<HxF^qM_rgXDI*X&l<|X
zBm}TJDR2_VYCQ%|gIIccmjtth*FiCaHR6C)DC@gDASYNw6oCt4Em#h>!&y%f(28I&
zz5*|j^%n(kVpwn7#$P#>wUD;)ajcOXwBlK#7wLjv0_!~rS)62LY2aHTYdP%$PO*xc
zFs9S26h3@PVi{<IcZSvJgVtHrs2@bmv3~y!uAOI{!wz6hGE3r#Rtl?<awr#ArSxJ+
zWi6zO_h~HkL3F0G+$bV-k+o+8B!hLFawyhJR>}a-vRG!S-OFa>Q*bedwao(amss<D
z0Lf*sDTbWKimt_!<g+p;;CY#~k0$X7%eoja1+4N|jH!_I?kPwXu@=zj{wnL^ufZ#3
z?Yo24HI{QSpi5XA>Bf91E1XuX>sFQ%J(V|DF1IkkGFD~|G|E~2uK>G(6+mCQs$?;#
z0{12>j?z-MSjQ|dQN{X^;=H$6+vzc^X0>%e?+$B}J|0lRS{DJmyDSlfa%)*(8$jw<
z33O7ZXU%K}X<)sy5ekhg>p(P^O{`ximfOtIQ;MO5btM;_t*p<cVfP;Ed#YM%V|{i3
zmfBgL(>F{ySV40zGo7rML|D4dTKP3PyI5<sVQAf~vs8NffF-AQO%JPsHfX&pXA4?=
zEE_s4_p=hHbZCI(WR*j4kj1BW>k#WI9SDb6v)FKEgw<*Q8D-s+!R{C<A{wCMta(&}
zI>9R0f!0G-I^Ar4#Cj<PZcnndP{?44^;{f8rddCIfk8ZG{bCREPgo9)AhvANB`Daj
z{Yzlao*kJ<?>`4N=O;Mj%vL5t@d(>O2P_x%s24O`+1dDqW^<0RZ@2=@jqOEo6L<F3
zH=*ajPNF2_F?JP&kUiNiZG?yy`wJ=j^=9v+e`MvuK1t_gU-mwF?)}*IagaRDKC%+_
z{MpA|paSgxb};>B1KBI+yc5J8rUy5e?e#vK31P>41B0RL5NC*-U|T3L6UKf&7be2l
z=0Ye$uvu@TGm>4$f{7@$<##AVvrj#ZRt$R<Ro}$2Lun0*W3y=Wh-b5|LLq^D7+Y=Y
zoRjQYD&S9K&;A*pr`T`VgPdk>p;L7ddkf9_8Md<z6wk8zsQl#|+t>>1^XwejmnO6O
z+dxv-JTEwNft@uC$yD|zMI+PLTPf0*&X!TA@FIK3dl1QBH_(qXll|NjB&}KO=VpSL
z%|5aa8aeC*PXYT9`x9E%bJ>e&Uz*1*odJ^1-n|dJ%j~XtkSpxx7Xht+{be5hOoi-$
zB|s};FQn@ZSJ_F<@Tr(xLG@nO*lkqpR>IDww^=FsBt7BR*{}No<%X3#LDweA*m0Ea
zC}-dFfu#!edOD?6vSmL)<|bQ2@3>oR1Lf_i*gw4hh1={Dn&)cvHzy!+hrM7mcr|Pt
zh5GNZ*R01_YS|uih^b@iSEE(WPJRX+Hn6YTU}78D=jeuO6WjVQ4VIeOn_JOrVV4nh
zD?5W~-tVz>bbGIj-Mj$$?QF?SDBfoa{y=9J`(O-6H(Nf9&IjzM0ig7-8{UN%z3gv)
z2d|HPPK2@avsH^AGQd9e1I!PypZgW9A$Ha!C=9b*to4u?VZZ+?OpLN4sgPrgz410?
zZ=79l4Kfq#&(2~L57`^GfcJ>Kk)kw{>?M?|nqu2y3pHn&Euj7XWA@}rnCB<#KdDI2
zmQy_&B6gg9icr~e{tdv895@=f)a}SgSPEz-4n7b8rZZ=Xio%X?_U(m?3n!r##FbO@
z84MofB+!e*jq?<ps@*xw>!9Gld43EE$2dRJsoIk>ZUYf7j*t>0-kkX}!1LjZP?*@4
zbD<4jew_Dg;L~x=R2qEp=j@|8-T=<UKDr<n$eB;eRuHF-UZcUB&na#d!ui+*g9+ul
z@g?k@;8cGD>@d!+*D(5U&MG?lMR2eQ#)HQhr_e$aC!b=I(VW05ATgW(6FOr#?(|T_
zaemPNI-c_tEieh3xnDx>BxheOWu+52`BYMOinD;?(x*9(j{`f2(?RFpGn`-A(K^f7
zNT=#^oVS{QcAoPWttrWz4fEks3deIMS{FF`5mA|w%K1DKmeM!_dRR*5uxh}&$SM0C
zdKsMQW}swpR?@yTi?dz<V$J3>EQVqZ$3ofGOB`<+Z!X9A6EO2QeQ&^vd`<%cotHVU
zuEMlk;XLytItw_yR3B8x@tT4cMVwXia9!mb7=phgoZNPFmU8a+0rNU1no1vTa2)AU
zP8ny1Gt|pDoI12BtQ>zTW2xlqqYcVU&UYuEc#Gq53mR3NI$9!bbC#@vht-^45@F&F
z=Q(<)YdGttFs8elVcJ#Ja#Xj$tK;;iLZO~>kj}9Uoc;7vG;+>=0}D-@?<g$Z%=w27
zw=JB08HUu#nYqmOH@l_Q`b}tca2)r;dMAfL<GjzAN&CkxjvrlS?dIIS3+M-&=;xr`
z!+DWXpuL=5DRA1yxkq19>*st*3*rDLt^_E9oWN&5hB(S|KpEyVYhhu8ll>yVMmY{n
zurS7%uZF@nXUa+`f(cHS3TO{GYr7!xh-0KJ^(3c{zM?<H*-V8w)0_<-!|r2_{yxYP
zj?+eT+H!Xsg@PTIR|ExnZqyV!bl_g36qh5nG8pPk+}$M*apta|-0~6b)0BU5;o676
ztSk4z7qmPd<%ZUv*Ny8z;eU7TpHXOea9^Z%`7v%ko#H*Y3+V6S#hs+ofH!yX5rFz|
z|8W5E<qlI++>e{`3TFE_w=NCl{kg(2s0VNtji43CEgFI|LENurq7}@QL_i^g8+V#=
z)1h3~CupAFe!LwTVcgZU2!wN&e+?4B-Tpi@BDpbhU@40Gs0ikxx#5-YFoyf%BFu9v
zw>ts6IPPY;LLbj{dkrLk+eg8$liYLxc&E9qCBb|WH;nQ~XSj_Nk2%W~AaaUGB-e8R
znCH1)RzftH`y$o;q;Lynf?VL@=#FQL`(qRo)41PK@FAURdI|~`x&Ab?46bGh&SY}e
z{RNRMu4oPZu-V*we?cUNn<vL0E^!~x_9U0<@IPSYad*+4C7*k^70}kp+(4?cxxzi|
ziDm)!!yzyWx!-+`RuOmJMxb5g#xdY<G1rbR%v|F>OW#;4;clXMbt#wc3=`M6W-5fZ
z!M$gOWEuCHPGFXETe{Jz;Ie3$s^sq6is`z^HPH7oZ*gyM;Y^j4n=b{u&24Chi`85=
zdXL=UmL7%O8t#vQP`t~1_A!Q5%XOewK^=Dy{p9Ppg4N(PaGkz~WFvPkT{3Rs&O3-!
zGj}Pi>Mh*;`A}%(ZsEbhdt849D70~t_rYE}cVZ*_?ciDi@-T`{?jLj#xX;~7n~p9n
z<1+NSxs#=^^niP@38FpRPyM0a%T?1ous&`q<v#nlM+YD>z@1)+)*!cn;`2k?S?@t%
zn5(DU#0Xcp4<e&n5v@UETp1;t$GK6oW=?PqTj{>uL;Bz}9z3p}8$>6$8z`<h#Z9O4
z*EIL%YcTkj+guF&C)|H2Wns%}83D25b<+;jo_CzC;5+bMkA;XMuhR`JC*D3ChV9Ht
zpf&youi*<27v4X#Ji7AcmBPYNUUt3}`fj{>TKSLhmJMJOp1hn#V0!U#DJJI43t9n1
zA6^rse0_N_6ch8~@q?gnoL5a31^jsyLJ8oF(V;AmmuQO-2Jx<~z*vHLuhEGsgje+=
zz(RS?^a14rZ#5GrVZ4R^eWp2_H%dXV2wnn3G9!84(AhhRXZ{eaXx`c!D8}$U{T86H
zyfF$!$MFJaV-e3=+5=t!?`sN1pXAki3hYGQ3r!%Wcq4zn?bAHBV?asb{Y6!yXLuVF
z@b@gwLRDwyc$-ibgh(WBxCYE*-s|)jrtpqmfc^!Z$q(46JTWa>X}sA~iJs2;d<{S^
z^6DQzB!d@4^{tt_Q;#w1EZ$-2%;t5RgozwpGo>sp@m}~6mU4Mp7Gk`4yeRt3<@1&<
zgWhG{Gjxs9dWH8H)n*m&?yZ8QLf#1~ek<bD)IsAa?=aQi6!SXb(YnTanF?Y{cn(LP
zP|90IS)l8@qZFLI!P6~6XBn@S>O9MN!v7vT-hRrURq|$JLH#B#maZV(;wdOJQ^o6B
z2I$*XUcm+^R`Zt9vUP`-Kv{+w-ood=yvtks2;;5g?Rgs_b-ZtVfmYAUq+5Fpyg$xB
zq>(rA4_ZyUWjiqJX5R0MfYQRdY=LX7yrsTy?H-Ta0`)dt!*=l6c{7S&p@VnhZ9sSO
ztj{K3X7BTUCWBqPQXyozd0ERL^MLow_vq~5U8NLHFE8jG{2t)tQ-)}eH}>B<j%TKs
z9fms0kMOD~;4;cvmI?JSo;OvUjq|*zP;7!{qzLIlo`&|6k9aTBUUriAf^{zpPVri2
zL1vnF_%E1v%uA+nn<u=PUqQx}-%hbUJAThnjKZE@83p3NU-$qpj{NX)s5|k;=0U-k
zzw-eUj_{wQr`U!69Yva5`Rne3ca;CaYd~@1*HBQzoxivq#DhORX$A8bzbX}ed-CIH
zzP$JXin)37SJ6(>hrdq?OTK*j^+5CEYpBxsIKPV)8h?JyB!(TpXVOMDkS~21ydeIk
z*%(VOzm5u>L-^kGXovE>Xh<jc-E=`Bj32%iBH{c$xwH$7;Lm!5W+Xpr1DH|#FKJBC
zd_US}#PB_0L1Ou@(ThHgucc)xp0A_Kd;))f!qX@DCB0}R@~z*(!&Cf^>5y}pzvF43
zB=Mh6EcOilF#RCT^8a0qah~Ig=>>nD?}@q`>zri%*f7ke@caLS%mx0+7vV)Je}@cq
z)A-Aip`XtG<Pt1h<lmwgVFo`}2QM=DOAo?C7XP3J3}*B5C|#AqUrXimm-s8*0az}d
z^DTIJ{FiC_na^KFl>nFd#YIrR!hiN(s9Ov8pPdDEA%AfKWQzC>Yr(wAcisk4%)hY*
zo!9s!R5Dn?_j@1MrTmk1;9cj(pF`^ge}@Z9l<_rh0HvIN^>dJ${7MhFeT$zefx#;N
zOe*2I&Hp71de!{dtr-0s{s<M`*I4<pj1axc_tS&a@;B1qtd76I1v2&g7yrw)@mr`G
zq>=w41zMZ<cPQ4^%s)yc)h+xRCSbSn3s*z^9zSLScy0W@X=!NZJN^lg4*sf((Cg$s
zN8!)={3-e-Nf-YF?UK6r){jnMo*(d6yMfumSJT$Emv0yYS|8s&2H5@l@CaxO@K1gR
zF9!M628aytZ|nwdnEww8FeChH^t%}43&{I1e()}Ujq~px1oQ--c^a*Ud_geA`-uPR
zPC!rc-=VPS6#rf8>(H3y&!H62V}2F|5}xqGe+HVZU>ilP>;#f)AohZuAAsf{@S~ip
zqk!d%mXqMMAK-<vU~~}_jtHK&0nbHn$O|623Z||D^QhqN5G=U~+DpK57X;G%FAqVb
z5DLcx7xE}r=PCG;&evXot@Psb7Ciesm_CA{YH0Whc3wuyPhbszYsUpX8{v$<pk)js
zK;TEucAy}42Y5k(?~Xw|Sg@Lk*Fpr(ZU-+^5VRAm6M_$@az0E@`!^)R1zvPMju5Pz
zvjERuq@bo4Xi<WWTVO^Delx*fjKH-GGO+@0x-S$bP}9ylUhppM=Mn@~da6zeZoLGO
zC^(jm&QpSy>CACjz@^}PlHd$IuxA8WRCje&F#0aYIl&)vGCePdpfJ+~!Pn(<O)yo^
zkq!Mc!Hc~h>4G3yf-eg8{R!+0K@UA~nF7HaxRxc@ngm|9U^CrG$Pv8!G$#0x;Px-z
z<qFi70h%Y+Pn+R<fr28smjzZzs9g~ZazF|MadhM_6fBXziz30#bh5Nw71&eYq*$O4
zqIpf=83<;HfKT6$DHT-HDd)Q2A4+T85P0qfuS^g@<ss#QZLgwLAxJd9i%P*hI*Z;E
z#8W-dEdi5Cs;dP3R2qF-aO)MAuNHie4uv}c@nJ~T2=)(xch@SYq+@HX;Lk&7)(KMS
zajF;GPX}ob9C#Dhje^~uW4uj*2k`)H7N{v=(IWWiIQ(rD41@#pp5O-!d}<RY8$sFy
z-|c~3hrq8EBAtSGdqCe8JVoceE<xhcQ0NwnWnh9H2&|7;VD<=pr9e@y;KXNO_6hV$
zVWMB~EIo|_f;Z_&9~3Z_z|kQ=9))Ix1#2kiJR(@3fZnK}WeG&a1mBf`H!e7R0hT5N
zFO>lLp<o>qm^~6CoduZ`#L<asO0a%8%ufsMS|ibXEWn*uJa~fLlxnjTvit#RC;Vm@
zX!b%0ZNeRdI|Pt)6lPG^)JgbtHHfoty%^&?B5bb*aS<M%GmoqAv!&o274GrDbh!z;
zsM6S7`1lzZ^bpS846tLub~=f83d3(v6vj(9eG)R>!Yy<*^%1&vgZK)6_ys=s3m*id
z6(CHawKq^Gj7DdWFqsNWgN3_a09uIfY!=i*g+kh!o)GHag55A7LxMqs3yUfH7$Lkg
z10F^S!zh^$CG775ShR3)GTqII5k5orXkvxmy#cg1p$+Zz;)P8<KuZwXxC8s7FeU;b
ziNdaF_<c%vXD`TU;XF#7BniE#*5-_`EDI*i3i))nJ12ZZ8`kr}3R*jpg}1K5rxf8o
zpF{70uuKl`Q-$w2&A{`QCOrHtG}47H)7kQ(FlGr_8N%&qU}p+{c?tSi!gnafm@WLC
z;zT*ZG|FII5;CYWSJ>eSy*#0?A0Fll4^dU`Wns&^;9U_;Pyug&Fo<Gxg~Ig{fG!e7
z{)pC9VKdb^S&N0)^sg7L3FQ>;DG}BmhTo;a`Lvh6E<8_Fr#FPXwDgw=-OhqnE*$v_
zCMtwX+MQJj-}(TOH-&ZwAaYAsupJ&&2}>wqe_J>u1g~1SjzYnAghi3y)d-cePq-^g
z%7NKhtMEA?Ow<WOqJdp6^rvgw4Z?f0_%#Z-6tZs;x>LxoS?J*myDh?x4}!D`Cx-!g
zPw4X&^xA}X>G5wDu3H0x9YWDV@H&OQBS5(?Tx<u@C2UgzrCT@|2-hA6d%g#BkI<_5
z1&Y1Gw{L;jCtSY^`u)N$mtimi!d|LT8x;CDqH{=C;0Bmsq3bxzj|g|r$D&4s+i5E@
zA<U#$`9q;YAIKx2gon;a;fiZ;ZA$pYIgn}Li9q=DScnuRo;2Z;8W3AilGO|5?L@C+
zK+#_G*b$%(qL*p4brd<}!l09=EE%pji+V@#_c<c^00n(>Ttx2wJ!+y~DAIXUw00{T
zbrZ$C1{8PE=;!G45WRCAlE*~GLm028$l)f4muSHxyzmwcroe)aXvKAU{(ME3KLpcH
z^bx&HkBeS1qvbE^qHRNfXnhqx14Y>t;01}+(as=PWTJR@h)A&?BB7#MsysX)DxnIe
zFi|EI^@NM0R3#Q6s@M+KB1H_!F-M8&UqmZf<W0Ys7*RwRWdUPFOK91O6G>V?;zft3
zLMlPj@C5Fk6#YRzfke@vMzl_e#@~R6)1r58p)*Oen%?kdL}zFZe^&Gh?Gw(44$~5P
zUewCQtR;&oN`aXoVjG}-LFCs4e^W(&^q@0Mr1hltU%Kd&7Wx-OuhDrdLv)ieB$=X(
zj&L|jH1lgHW{cXNfR`hReGTN2sA@6n=8FEL3*UJneHjeqi{{fg>ayq^+RR=NDd^+5
z1)}G-VJwBBSEx3qNc1TMzpjdA-2`T_sA@Zi^_qxv6tqONt^{6`ib_1-_jS=#+NazQ
zJwqAMGSP)nw8}*@C?H)Sk`@B3QuGaFaBqq-c0uo!XpF+dRiX*nh}{<Dc0i<B)P4ZG
zJEHycpYLi#Z_wMjPE>ywlJz3<U9=jkqTpu%(<oXRkMTB%{+)(sv*<M%Op9p8Z!p*@
z`jnQtd!nb$z>7A~5-mj9MWuTI(;>P-4_>DzgQoPpXg%exyF@)dgV!zE8wG_2q6fv8
ziyqNY6?na(J)c6MPsG!K*DtbG9ERNiQL+bQ21SKxI5i|Hq4UMC=m@Q$BclFT@J2<8
z=_@E>qQ9o#)3|6Q9qcDWb=xpq4@JAz0rZjRhkpS&DcVN6hAGjaD=;`MdgB8)^H}r>
zy$zp;e$IdeTX6{m0`0{8)&*eNixa4()j=$#GGs^bb5wQUBvz!N<t&~*1#(1uj)Gq<
z;+Shta1}42Yv4!4QxaHm6Cb2#s=N5ppV9IV_frn#n0OB#BA()xIWXuYeuiSB-r{L`
zi~5LHT!DFC@u<ZL>L>P~0Q_-r-4QVT#n0=Z5g>m1P0UQ7Skeu&An|7Uiw28B>83!4
zI3)_LP;s~b22Y3`b73h=TuPN(;o<{55Qz|5p8{B<IBPLPqQom`)ruCoP+~Mj{9G=~
z#)=!?r%KE?@y8dS5ikDmZ_H4F_|tvBJ}LIHV4#WO=V;YDC61@C)oF2)0L~<dzqk)e
zXT*k0Xq^?WXotu-acDR!ofq%2gQa9~8@ZMumfgZwE{NyaK_ONA!&-Evi5qvri*)h1
zRLVkJ6dP8<Qiiy<2To;+bxyF9BeqgJ<B~Y_EBKTvzEBOtJn`eZfXNp-SA$#@Pac5X
zD`Fpa_*)=m(Cf2MY_SJek$6A-V~?xi)3gsP7N7qP<eIpIX1zqbS`PJ6@%4USTCa=0
zrfQ`d;v*CtDHDfMc(7cYH2^Ov#H9f+Q7JCTgTpt)TX;~sCB{|_kD6FQd#>B!6;!ZN
zEf&$jdPf}n9rS9%N+0Om74JU)*J{Nfl(4H4uZ{(;UOd$Slm_u@^pUAXtN3#%^qa)S
zlaOf^OTUIpi}?ByINU1!idLU{;sZZ|*CyWaEJ(X}nu4(%;veZ0+bNExmFd2C6;+IM
zi5JqU)h%{?7ejj>zDDn;9&tw=M0&+fIRLXy{OMWP?H9k;1MdgK)>(U@I4F)EfTbbv
zx)Z=27Ek;O#Sw8_3|gb&hqY*piFeO};<z~Fd!S8-!+GF66jz3$^+-H@3A{=1U^+Ud
z#OGfE*tGc5Ip94O|2YCjpNMrYz@V+fLa|XhiLL`Jdr1Ixqj>NnYxkh(DA~Y;i%ya&
z86eJ*#s6(CB@Bw1xk&za3ZSl%k8i@nQOUIh7^s^>W(z%c$vN6mct~C!2RSB*rMHr&
zL}3HsB`I*gta(eK{szxSa%T_<zLIyuK=G5P|Da0D<C4<TK=YUQGGI4A(m-+MK*=xj
zAsQr!q17u`@;dFZLL@Iy$yJzStPFpqaEWg^^dcl*y$W8WgiWW=C`kYV(-kfGLkqna
z$sH=jjg_>~_mkr!Uj;%WUh?-9SV)klwo(@Uq(tTq7ZW8P-GJyR$sxMOeOhvFK3q(a
zyhhu)Gm<@}Xq}bpqJQ#mPSQo^zw;9Pdw@xn#8CVtMdC_<hzk-o%D$vZyt|-~Ci#I*
z>*<olJAl3@dFLM7&XC-C4GNi(S>hRZ{<0*l4`DD{Vx$92j%08MeqWMop<5TZk{chw
zQl3P-A29inqfQw8Wyw>=VE2mTof!}*kZjF{UZEr?6(U8Foj(EWs${1vM2aPk|BIhU
zyy$maB6;gwK$l7uQ8e?q<h>RsSZ_$4Cl|{k-c-9(E}5>vcq=6TR6(OsVoQ0Ro09r^
z@NP+Jg5XS*WPLV9cv~W+j8L_t=Na(sNVd`^jcO!MeT)&_m2}dgTPyLWFle1*_5-x)
zB@IIO)F9E)HndS<rDEqMt0az2-OZAeN}#n!LMb2CDk-Pm)ji2Bibb_a>VAaXc1blA
z@pMSmVcD9~Dd~=fYxgCNR8rR^d5aRG-I6_9pzuJ_L{~j~B(rpY?v+&Eg-D-d<7SMk
zU$XNqCSgFb>mPIuN~{YVL5C#!X9I0mvgt0|ACY{&4kkt=+?60>lDu;8#w9Ux;o*eD
zmVRsxCHg^hK9W4z3!f$>K761|N!GW4OiL0e7ilYPr;vr6G~{ErW-s064f76C2?ehl
zrJASUg_G3XN~ck0>Fe8I_lQ(E8$T}>sRjp=Ij+*5C?<4N8a@FLH>vYIXt+!Nr8BLE
z^fDC)ACsQ?4VFBm$+W%llJ49NJ#XpxBuM&5zoE6rS1OWVF8rkZbf@*WbTLIB{G}mV
zfD#~$e4C!XK<V!kCkv9+I$~(S(tp=MBScz2v64{f_5#41kXF)tqcCXzB?ZH!wyQDv
z2&srp-H}o@RUJf0rzyk}EyX`q#DgatrJ9&n>EgE`87FNG0cN~3>K(Kar0%7#cT!rB
zPnFP#(t27VPDumvz&tH=qJK}BB;~Kd=+8(uQd04(bQ4YKIq7fvp?F^UJY9=OmX=V8
zFhyDx2XaAr^%Z!LDmBWWmnMCs5R&Oqiw*2vltyj=bcS@77f>>#`%gh3OWKbth;>f3
z)I^(r9I5zC^j?z2|A<M<m41)|m^^7cMa%Q0N9mVzS-N-vpjV{(uc1{SolB?gLa8MZ
zdPUNUw5D8@uBB6Vu~b$8lxx!5RJ2N@FMkBEQt2)ez^+Swdj$i$AzeeqKx>)w4%Ot8
zOC=g;R7f4Kz(l1qZx}K+rBP<c+>%!Bfnt^PngVFIrEk$ju39>ee!+L7AKim9HPRtI
z6z)pTH$b6QYP<%pI_cs!(OEB@Z3Ddq>HRrCX_T@u!E2Hl#$mSAD&0(H+I!M>XxGvv
z{p~UI+og8}n6D1$8$J;2lq&Z_<i51S1sYw_M^vlWEq#ruNFPX_p-*A-NIy6RXL_YG
z8o}$6#!;lEUut~^A_LNLx(75UEu@X-khFUovo<V^R=}ANsnz2x&{663(=a$Deg8bj
zxb*oG@Owh~)UUAnP`aN^laHhvijq%C|2PGaDd~Y1U}9RjcsV?LEM<QM>?cyyEbwe)
zZ(fIjoosFxpzUQ@_2_hv&G{59M_CUW3Qn?~<xp^z{c3#`phsk3^gSLI*#SDAxXRYj
zvUOC}!GQa2vITVNc9#XP!1Iue(rfgXETR=6p0a>7AYL*QP~gFnbx;<>NA@Hbli(}6
z><vsm+2yMs$7K~Oq317a^ngf!ESpx@K$-19iUtMAex~IvShlDKeuv1mT)?nHWtS%*
zb3)eD3BSW+8aiKu%ii`wXN1gqEqscU<xnUrN|sK0foRzwDguv@y-d;WSlJi!h{wq+
z$(W~jnK>7d2{OqG&^sx6&<P8Pvge<pZ!?^dy)zdxbXvBTUQ$W2J7>T=BRfF>uCubP
zZ_qj?JKhYx&&#Y7S5KA|e}OTj$X@e?!Ub8T8$eTK2d_aSP4+_p{7skT&{5!`Y%UEj
zLzeIa3YoIz8E_^`_U9Y$Fk7Y`qWpV~%ryhdOEMpdkLSu{^l95X+4IW)lP`PuO~4e$
z4hLh{g)%z_m?)Aht_Ha(JDi0v70Z@Vg65hm=Qcn~WP(jVDV6zC0{pt{!Rv7ChU}FP
zcu^)(UqxrR%<EOCSIF!J;Ec6W=F$oiH)WahySgR2K+)qWSuiD=Z_AwM`*qbaohMA(
zkv;VpL~3MjFM#4*nfxAjwKDNcOi7(A;{ZIYm(|G7YLKm54ql^-M-NAn>;+r!nq`OS
z2iziiiEazG%I=L|ocFA<tVuN6WUF_8w9DR8L%%~7U<K)veL=g*`?B9@+ubF5su`qP
zRzZvB1KCW<FZIa2`xc$OvZ$ZoVV`XCYIxr-^QK(PfGmf0s)MrPQ9uvL-lRg&VOc%B
zVMk<7r$BvFW-aOk+L)}LPG{q?U0Z=RA^W)#<e}^ZS}q^Sq_ppylsy##jVak@@1Qj;
z%X}Z8k7aLeLF<VukBT~N<^R48Y&-eIA++q}AJFsXAphnM4AfCRj}nzm@=bK=c9t)q
zs)Hl){Z=dfYA$lk^H6k^*M11QN96`8u5^>Hqf@uL{4ssQ#zX$@PM{r=*U;A3Q~oTS
z6uso%4WQ*Mzd{iNANjNYVl2M$(>=iSlh@Kq;<!AB-iH42`7Iy;a#1J@1<GeM;4cy+
z7gjF?Xt4aJFQE}4Ur3w(Q29aM4`Y{F`yT;1Lf)|xPDIM9=*%A_7trmzXnDkG@Z#jf
z|3EEXzD5ts1bGx?5l+f`@54}{Je|@?r{qVELgci39c^8b<V-0HoRRONaO+vQ?GY%P
zlM9ky;k^7ho!OJ+GwU&w6uHsb4SGRtq&;n_e2m_0Y4X@Gz@*D_C{%G#p8gkj8FB$d
z?lR@PBj9DpIkehk%WEi=nIo6b%701znD%zL@~<f<k|%$GejWMppua#a%Y)~^i!1Vm
z5P%iPHD&OkP_9|-`&HZ$YXzN{uE`@bP%n}D`oTh}Jc|Bg*X5h*F}*kBE;rFClZVr0
zuw2eQ0fh=VZxZfS$~Vwo^``tXZOU%R8!2I3C2!A$<ZbzE`Xq9-+;<^(cjPm&;ckt5
z-#HBIu6(N$hHB+y)<3|klmEI4%zF9QO^^opM!Jj8D4(FCN|RhP7aGm-Z)al=E%G9Y
zm9@%$o<Qe4`PvwWw8>}Erny~yoX!Isa=$mA-YMT>f}{84HeX`YUGg6ypw}(;qCMRM
zxs?y|J@TskbWO8Y{sO(<`{d(0;Y`2$PBoYV@}=8gVo>hj05T*`TLCgG|A;n`Bk}<%
zix`#feja2@zLTDbad{cNLnq|Beh1h?`Mf@$Jd$rb3D+j&u~Z{JCI6KY<<s)*X)yFy
zUilUU2cF0m8_{d482ALec8Xt@K*L^ff@(t?6bcrIqvHFOAWn+-OW?UEQl7w)tD>JW
z-A5I_8qw*dI8L>$?uu-Rzk4W_u0`vZV$dF5cq(e>*X*Sj)WCwb;;9OV_$bz$q$@JM
zigS%%`YFn(KIgb%Qvg8y6@_kaI6$%eFYp2tC0@`7Qk1MmXRtz(i&+a%MD7C#Rh)Z>
z(VtKllYkwjnD-KXNZ|@Ig;FCFC3IwnRQ$UDttbU^7ZjouZ>@!e7=`9(fLUV|O)S`r
zQzTPTEncy593(*za0j3#6&_T0n5c-Ifzh8*%y32Pv|=Bw7R*Uftjz)F8Aab6w9YC-
z-DsUtjMFuv^9mIOl#&(a!l9R<c!{bQFDTq7(VePrqF`d0B8v()(yfX!CD6a9_~RKE
z%uu*e>NZo6C4_#Kf=fHKY{dp2v~m=e!y$4>F^^t*xr(poO`fMHe-R4#iWwYqURJo2
zqjg2`6aCf;6mL=7p-_>afL@VeQ6G3$6(=Z$TC6B~4E1XY>o1YOE>V0q3o@mOxjQgJ
z*A+#df_XzRdkr+o6lqt$D_0y?gjR*Zj)GN{iamLlr<)4iT9~+{7^TX?Dn%oG0p_-1
zCB62l6>B!Y(jCQ5_c4eXMP~#Q?ke;PVXsyZYDQ<B;zMgbMC%p1=_T5rsQ(hJM#U6e
zaA;E8_!*>G@iP7LTNHNm(r;DF{sr@VPqCsBoo$ND{b;o-7SKVhLs7CC&U7k{iUHQG
zi2Da34-~R95b05Tatd~P6$j`K)2BE&36XxqV3!q&1B!KPfjy}Bl5&YdiVjNX3@g40
zf&PdhC<Gd#ii01ZHKurnZU~Gk`h=LE3B}46Ff$Jot6s;jA1PdE=QF98x`oau#qB^q
zPb=zPL+4|Kn=i)lL=i|;#J0+r&qBmbDG}2D@Ud4)==pU}cGAwrQTZ_~&rZta?$B^n
zcG1q~h_WRBJQwAC+8($n6Df*#RQc*k@Z6Lu0^q&7awnBmdMLNego$IyBlMqYJe3P5
z)9j@jN(7j<Qs)8%ALZWN5b;(1^(Fledp~6kC6|vYU(JBNzw(DgFcF~KP1(ahWfTW<
z5v1H)27|%Mj!1YBqHG$2eyB2tHiIXW>}IsWl+7Qb6|Njw43r3El060ysl1*B^(bY^
zLUcweFH;yHMtPMEow3R^+Q(Sql-K{;J}Q$t(M(XLQvl(la!CYQiOL>&I8G@YX$d~9
zJWZ7dNy=Rm**T*;d>nSqDpP7f&M6)4LgBpf`yOB?E4}Anpef2-9v~N#Psr_5<#8%R
zNK=~VEtsxk?gI2htFn`7a59vEJebH-UZ!+omXf7~Mz%6{0JE2)^tcT7FDZA?Ww>1B
zG~F=HQ+`f6fqdmvs-M5C{DiK2T~Yq@DzFQbQ*;NgP}%N}IV@5d==gJ0c`pIp7c0LX
zgZee4n;%-&mDaI7G;b(p&|^`i?5CW1x$^zDV7@}xcoHy`%1J#$ZYmGCL*tfG6AY0m
zWda=%ZY!@-gr!<Jv<xD5l)=Stv_?616%5{0e)Sv_YL%g>=&V!rQjEM_xp66Y4NBoh
z7+Iq--})PRo0N7-L7J62hrn!6PVB~DT9v#b0KKQ&PA8={rDqqMX;=EwNw!0oLNy+p
z%6)W2{=Tx=9(r9$yJw-$t-Lr1^#{uS18DUqy-s6fy-F84d-f^yH2~{ZPVa&GfYRqT
z+Jp`&Ln$0Eq@2eF%&<~T%hrfe76t54Wn&XsW6G#aP#jlo{0m-8C{<Lo_E0%V&%q;Q
zAc;&W@sHT>;3=c1Qh8e0z8uhxl}Xz%T~Cx>9sroF>hBt~>{J_=P`6jTd76TA4yp?j
z!*x`BU5=qSspilw$5~}Y>BO8Psw0Qtw~H#Y0@$vqjr3YLs(OR+BW|ikc4)b)ypKTL
zL$!zA$;VXOr$IbbTU(&+r3wgzC2v*YAk6!y)-4B^uj<wRa&apAIJzQpTy-!8F#ale
z4a^6qo~Z^2RJs2F5~TVw2fSd_pR}I}QBB@~eyGZwg2g9PH!1lTruv?$H^WtfRPPd@
z`e7WcNR@!T<PxQdrbRPa6(@#IF)HK#Kw?!(D8?42ve9DJtnn%j+CwL(n3T3Ssaiwt
z=0w$bDvCU%(ozvjifVW>G%l#}eKF8fl^<0VXQ-Zj0rQ-xdT}Pa$Wq;=7k#dZO;L<I
zm7dD5@>T2T+byN4Dk>Pcq1yaEh?J?82q99gT1cPds<5gK(I2Q%Rn-RUo2ser;M6VE
z20AQPsUFjj<F?97A+tNG@okW-QN5UexxA|yq_c0W%9d&e>Qt+q#d24#dS(ccjVjGa
zSZY!|U5p_$tK!dMN?KGWo1xySnn!7aHq}40vb3wL*H=TMLzR9UXq~DMs^Gn^YB>)5
zE>#=NUbo7}4;nox2Cd7zs!g>J=~E@11Fv7T%!JMX)$^5bdr;L*RSH9@2HHFitLmMB
zGNMYj4Bn_}MH*UTs>Spo7*~D&5zJ1guI`Y+sfVg*+8RGn6|6&RO4Ut4!D-dkltO*1
z+B+AXK2ar(0>)OIN;lo?)V15db5K7ihue<o>vU*!Qh!RpHD~n(caS6MjlP-Z+1AJ|
zXnUyn8z6X0eY+lZJk{$nLA=$q6z=y?JKO@KuX>o?tbXcWC@+6p?c5FGuiizq*Fox3
z86bnzZ_{xiL_LS{r=jX;JMd1ZhbRserha}5BvSn)Wi_MJ>sCV~THR*dirzSNqYPfe
zt0P_pGeKSL2Xaci`7R8eRv-Ku=9AP86i+&*9vp?_d3DTe=qIbwDgKqJHc>rzn)<6p
z5J^|}DbdPQue}5Bv(z8`37@jn-Ch98Rr8CXm#1E|5#Hykf1XFhUzgRzi7<FYT}WG(
z0`(#KlV4STa1Nct>RFX&T~q7+3!|y?DBNGFUiKICudClu!kKcli0Y3j)M7dnSE`FC
zIDAuWOLs1AsplTW%v7nzC<1#&eVi&5YScYXL*%YHDvQ>adi8bz&>Ga9efV`Ws^uAI
zwWt@%;Y_P~`WQs-sh=BzVw-wXEljkl1$5h?L!C%(&pvhORdn{N+bbb5px#13ghBOi
zIqVLpkE*~MRtHkVctowH?cb>SEjr_jsh45yt#iiJ_wpb!q5k9@*nOz(*#?<M>O9&H
zO{$*}0BuSwuK<}=|L-N3c&t``3GzfeK}ET?npt+3Sv$>JGvKJbCWH1B4x07*0p_Tg
zLn2O^w>mHuXU&%P(RoB;y$VSe&B|pkWOdc7`w`5enmu$E%}w(Qot51+dwXHtLo*!#
z>|>f8wjiFGGZr}NqtQ|7(pMv)RoPGTJ0-D?Yiubr;IG-<4_<&~GbN(}HJ^VCgF%|D
zv*1&(W*2S$PH48!@hMDmX%k4eRg;nn7b7&!Ph(0WHM`V+iPF4S0575e1GE^;AN1CZ
z)g;g}5~rC@6)o|aSHFdRf+kjtQJmB)qAgFNCMzB&r!@1Z3?fO>&x67l&6aqOvzlrO
z37*sZ*b3<LnhW&hon(zQVlL29HD11eNz*Xt$eyn0r!vutnqx}vGBlB0(8$#6rkqEX
z=KRO-Fk2HxJIox-f&xs*C5?rC7rB}j%|OZ1tkGh+@->n*FmYMae+UzMMf1xkkV1_!
zC6kIZvnY0XO;ci}w^)g${|rD&HNmH#ab2UTLhFWRekL@^H1Bi+yIga62Y3~l=hlN%
zYW|{4-A&DkHmKjyXy~+Dr73y?<hCaB1W2{!yFHk-yPDcUI8&=(rvR)@lY0=PUi0TX
zU^Zw<XIk->Y1Z`8cC1D7s0@m&n%T5<xu@xgg?^hRej&!xuF+^9(xLI9l9Eo%NjpsG
zea#IzF?DI8N<q3ct0vI-K-07UCVDi@1DLK}jWaEzeVU_hqH|F5yBW@mXo~;avug(3
zpT_eyrun)8%yA936&e#78J)QwYJ{J`(j$%6ui#B;K3oOflqQWz2c|V|eFIC6HBI->
z`9xDk`!9QK!9frQ?NAa7I%>P9Ho{4(rW2{N_Qj(Z#1ZY0E|_=G`bGiMRXZ1_KkJ;M
z+P$=TxoQ8h0jRsS>~pj{w4YyxzL(bZ7ntzY?oENBkM@65h2g7RV-Mn|J)8;9<JvTe
zf&^-BDPT89`zF17gSBHn0VPD+@dDICwaKpNJfU4}4+|06WQs9FYWLW}3u~0t=RRbj
zwZ$bc7^4krK`U0fCkCK#+GaUg@mj&F&`8j(rvI>ZQhOj8Xo=ddqA}i6TJ19ErD(tV
z7$O(6dns_7s?Dd+dYU#m0K9aq&<|i2wZ|`FE;6*ORnW`SK3@-!EUVUU75vWDj!?;6
zj&|$MAeXdT>205@T|{%4r=5Nb(R^(^{Sq!~*Lni&inf-Pv;u9MKTH&A1;OYn(r%;=
zI$zc9qDW@3w&OEcx~46@1lLNm!L+)UYH$At%<I}~hah=FYduBfd}Z2gzhP+Q+O5t2
zt<aXx{-9F(Dy^tDwfAUYyruo<F%+w`onaXLZLPurXR5U^)xf@^?J@$pM*ID{aP+QL
zLh<%m?J;`b>$FS?$=7S26G5awd&&-ajoJ@snQYR=S{Fg4S*xXpQj50J3zk~7XWAii
zPrG6(T5Z}aI`*||g_I5I&<<UI!A|X=S>WB*E~c7}E^TooI=i($({1qw+N<ZG-lN_1
zClq?Mhu(otecFEwX!UE`J0LlrtxAQ+pf+PC#m0xUo9RB*u=Ym^8INd3UV+A_wsS5V
z9@Fj(!?4G-i>TadLc6#U<e_#|FC-sn8!06{tu@oW{;_tk1Ot7dJ>d=od!6PJh&brn
zXQSn)bDIz1q}w?T5og^KTKtaaoIL0gEH1hNHb&v9`;>)&9@R;{g`%6zmIoPk-Oewe
z;h~$o6PAwYX46T_Q@2$F1utDV?M1zH`F}vcN4KU2Uij)}(OTrEbNdP74bZ(t3H3nT
z?{P36q;pY0Ay_vf50W9eCrHs+=Y;B5*PwqwH?|bLVY<qFkO|khC!#Y#*W?BLNZp;c
zffl8!w+Am;_pt!H7~LVtOT_95Uj{Eu_c`rs<8=!Sa63`AiVD|H>1NTod|J2h27F4=
zd47OFoYAE|hR9i6+{+k*^_-3=farPMdplr0Sy$}>nG{_!9UU&{_VhwORk!;Gw9<49
zbSEZV=erb>a8dWoW4M-~Tk;0<GIfqLvspSW<qooSn!CWx(Y;HxNtbjl{s4b-b;}|l
zlBY|eAWXi_uLR_>RX21BzFpDT*FdpA$NL=y3w4?FqA$`l?tsCoI>B;u7VEnH2Fx|x
z-Uzr~qFYCwD=F2@h=Td+y502Ah8sGk6tv28t#hGJuG>U=?+RT?6!a=}TO*-&Q@5Ay
zci+-&9)rCqomDJ=#%*2J9mrJc&Mkx8JGwZ!9bBV(je<aTbswDsOs#I>e=u053#U?}
zdR_i}pf%|BQqH4M=R_f>Cf#=We=p6t@_8UFI!_8GwCcX2ipqPs9Ewo3>BMyEY}ftz
zCH`plbx&LA(s`F|JQF6mb-lE(KG1EFq1B@sqRe!!?$z7S@6*N5roCVHGgU7S=oVXm
zHmF-n8>%54Hw69;>wM|D-H7hdG3brz&QSH$nC{;ocsQ>6)DwCWx=BjfJ=A?e=YdDM
z$iL`(JE`-cy2B}55q;rtTK8fLWFG6pp9A}eZZ6#evDJt91Jq7m;10X?`X8^L(?KuT
z0)vkFrZ}{m^hLc;ch(;&1m+R_>lB)I(L28co~wT90n8uOJ0}3zO@Hxo5O=-vT1vio
z=<lom=rR4p_n_~okEA1(mp;i3Fy8tj>tNSMAG#2K3Sa%atLXI8hx~=PIIhoLj81?3
zAvW{^^u1eQB2a&fTno|<kDwK-FQj6O5dHW0=nU06WCHqx-iu0%!t{H~XU~{DCtSbD
z_l-+St>u)9j@I9yNJE_dAnozu^~>!cnV`Rz3$rKn&Yz)`sQ+08kyHABRyc85U%C~N
zNqXy7Xr0mbt_I3keQ^>b&*@_*S8`sz^j#<<>z!|-Gey6EV!jvj?<vuls$cRRrZ7$K
zWZeU1y8a72hI>(OOLrAB^t^?T$<!~Usm#)+o8d*aeoa0M=IB4Ih2kas`T*F?)i15X
zIP>%?Hh|>o6XPIxSzk$+@GJVww2vy#dp`$Wq5h+5=q%C)QRwKZe!*#=6zey9LV?C>
z`g{r@mFW8pV7f~6wRH9Tx?Z~%25;yKXaz6RFQE*4x&FO_XjSOvn;}xEUsHwFO}*_G
zuzO2Cx)459>E&v4-qz<X1*z6oQ~2SIJ|P7PHTrkY!<oDK9fzS%t3N)Is^IJNE%all
z*LR+Pi3YuV6Xv2(-&_vTq~Df~xoFnUpr^k@-}n<uwCOL=&Z}K-69f|-`Y)&9Xs3S8
z5L);34^}|3OFx5>sonZD`yly1f1nqnN5A?prleQ@=1%z3r?2&ygN3+XFQr0@0sT%o
zUJUA&Ov2M4{XP1c@37v99-I-qKb>_(_1RQtIHqr)C1G6unmx#besVJmKGa8l1@cHg
zxdkYb`Xq0(ru3_*NPAkJPB$JO>)ZX|=o9@(+Ev*aUe~~1tDRxzLzuTWusJa3V2IrX
zMMs1FO%Nx;6Bmd&8`3BMcEsTSDPUX-137TU)ev_MyrYI#s;zZ1@X~<hZupVRdl)*Y
z8sV7XK5Z{N4Vn^+*URwG3+BBIDHq_AkHJ87q`p?eG?lga8P4;7cHEHq5iI!|tiJ&*
zz|hM<XP{vfEdoJ?m2??1*pL?ne?tsbs>}#Ayh%&Z2}6DdM8XUTCP2dtNmS+)W!TgX
zlxV{<bf$|joTeXQyrGr0;t7U8s?a@Yur|I7hff>c+X!Zo!A}guGluYE&`39AyTZ~%
zLn@^~GYpGtVKCFMx(SxD48L<R>}<mxIu+#@2I$Cg$*_T5jk$)x5s*BC^FB!C8~WzM
z(q%*1S3tR9Sl$dn1%^pl2@4GitUF<;$lyu`sH=u8|H8LoLrFPgt{JMIgG`Cx@GF2R
zHFOIga@`O_3O5WJzlXsxL*dI1DK~7K3%v@%N*VMj4SWjp-!$Y+!uwl>VX9K8GW2<)
zb=&acvp}gf{6V)0?-;zlp+G>5p}P<ocMTU-VNA7#cqf3?8D9Seyn4eSdej;Wg>>Df
z(GU^<(qvfiKD=l)JWI)%7Q=EnTDBTSOmOs`;XGwD+6;VOptKvlh(%|IA&ahkb{e*4
zgLmKXbPQ0s3}<|(3aQ&*HwyP382(NKXpbS~b<9_<!G&^TeTMhqpx<x!;VHBR3<*^F
zGHCeUVzh<~yT6CzuwgFkS4Rw9>A)T}l+d4f%&=_{z{U+tNw73wuoIy5&~TnA^&T0b
zyx`2FA?;6k{vI37Qsm)@;aOi`+ZwmfZqm*eI)n+fH-4WAGza7S78rCihEkP_lhHzl
zL1$yt?*Khwe3e#W7h^A7_;NMQn1!(%HU5<cFgN4&r=ad`+({P-Jd8V@0q>a6jSfDZ
z#tlz{XZ13MybVxq;~5IW`xuL<vcuQ7@jZz88S5zVd)ydACu)D=yHpnzV9c_EWUw)V
z-W(yu%qPGOHLj#mffL5|^WcRU|Go+j!;M!RAQEAWlR_lY_%a2cql~i%CEBQ`SaXck
zC`yB;vBuc@AaTZpR2vv?%=#Q8!MOb#G)@|;+kuv7WKzW9lre=KmD9#gzW_{<Q9!kQ
zXN*7Pf_K*Vy$s%;GcMpl;k>bn@@>h+T^?wq7#mCA%mw2c^r@y)V_^+iX~t*V4nZ;9
znCSaKA=}!20ZwEa{ph%wV{B%?&?RFc#p`p8k+tZ|GuF~!Ip6qD1C-0g49a(1F(y!f
zZ-McT-Eg<i_(uU;Dl)EF0}EG;PCWQoY;-C`>zeU&H+Ut+g;XzFY7F}jVAqWeR0V#+
z=whX;P?>R<?!J{9b3&n5VdUvxzS0<MgR$H+*1iZYZW+seg?^Q>?^PJQZET}7d$rNQ
z2(&xKjIHRbF;3E7;;wNqE!nk3cY0FljC+TnS8pt)cT0n@gw}#a<6(*sv=}$|(ypl0
z_;wx)-ZLtwUboGdo(%nV<NPYP)?xgEE?jjQ7rq6U`^Mn6q2Fc9q{5DF<GZ_|{=m4o
z017?E1@j=%Yy6P@E`7$ilqu>rMp60Pfbr|+z#B9kzY5-vk@+lm!$!$4?TSW>PMJU(
zH6n?O$H;hq%3sHgO8T2WGA`Z#{Yhga9ek#Y<voCzHg>y1^0D#5r{LNXqZHBmIku(%
zx@Tr*I(`O{_NIH3RB|w-&@RQ%^usflE+>=Y0zf;PqTMk1Bc`4B9a!hMm{wnbc~{eE
z3KtzU#Zer<&BXo_GVUf_7Dnh{iuxbWj+v~#fq0rm$bBzU-XVZ`o3{0!)5pZ#1%G`_
zk0|5nXBrovb=-769Xx;2=iR^zF#Sr4R-ozW1~?jI%3Xs_Yp}_d$|OTf4ez5FYWjfI
zsS~E9w22Kfl@kd!eL{J~2$S3utw>Wt8L*>FMIGpjHof!{6k<$PO3}ueexVI!oaqMz
zypK0!oPtP#=_-{^oHQM7fcZp|M<d87Q}JO8;<VMYaVwfhrW`J?&zQ!k80f4ijP~B=
zOdk|M=DcYr1NzA(uV)~cV)}-56c<eKOn8xMx=D%gG}By4cBGqrnt>^~XfjbuJj3)Q
zB|9=rvd=KTS*DMux+UB6Bc%s(Oixip?vlyM@<MOEX^#;4mrYmbsB^_ME`ol6DfKzX
z6q>5W;6;(Cd=6I0tEMPA`4^ik%>cb-3Ox&6i77D>q|`J(wH4P*Z~qDtH%x(^5Ggao
zZA7cwRLp^e3e)M;uuy5T-HbupG_AE#!s?c3ieAlCrfr`<^tQ=`c5c<C<((jROfm0b
zgf%7=#j5X`LRLYs)-?4R6zWXx{Q+m{P21^B*I+6t1h3I_hDy$wOg6LyZ#LOew5Y|D
zGY1N-rX%g}@SZ6J0pU4qraf0ED$s7)NH-rkOeH-~>@=OFbMbvsLKS{HU8WTk(C;>V
zrGmx-(_0JRVUOuo+DP@9jNKr8CQcTx`%Ou%;0>6@!axR1f4vTrA=Ab0fii45u>)kp
zlq!OuQPXP$&>J(kJWnsfansMyU{07UENDD5`O|ykk*Q}s$fQY15#1@1nzDV<Cij`Z
zer#GoyRs*y=U;+?t$7>$eeKMj(5hu`PQD8;2XjRyT8?HJ-3WCu|K<*ZF6J-aMyIP;
z_%lR~nl-qVXPx6_o}jd*yIDa&c@Oi)^nH_KX1m>(Qcv>=Dys7`E2x6Z+q`B4(0t5?
zR-n_@Je$gw{LI%7+?#XUypXDX{mrjaR3N}SI1CbK-b69jAanOj*bO%Cq@^sxd}A9r
zL(MU<uxCACE@c2a%)D|voC-HzUj>*5v+*|!G}63xJ1j++uTX(uw7E13`Z4CsPH4rN
z$LQx3XC7>YUc7nvAb1JpWt3$+Y4)ZZNTT`Mdhkw}|9uBwr_CR@!KWni^Yr+hF}wLd
z<gC@aeiDl3%#Y|Db>94YFqp~ai<F#AF;6}Z-UagjZK+eu+WX+8nX}&mOuBhCRWe>Q
zzqbdS8Rpg|3?|cD`V{=lGN;q~J=@$+fmV*$Hxj%{=Dm;LMXq`MN~q_VOW%k2e6!VU
zIb<%I+m}J(iupzlWD3l`s-RJ5-uwv$Q)Et_fW}qxm)OY7DK?i~hQc-T1AmB=m>pjL
zOsP3I6(ZNo1#h5LZjM&N-wN}=T!>VfBPmyO)4YuVkz3|8O6XOY4GKu!HZQYMe7D*h
zMa6h`%<&QoyT&|q7K(Sx3;ZEkYcA+VtIm9PHZ<zZCsp*QnP12STBA9PlHW~c*PnsX
zY+hao$rdvw9<$bJ{@+{->7IFe9a?SX!w&)7ZjMpIP=|Rvh5tIuj@zsl(|z;9tHACu
zdr>g5+x#4DI3Ji7`$40}+;$1AUbATtu=~tzMwst6e}rpEa|X=XO;8^+&$<iVka-O)
zlf&lCv=ok*?I;vGYA#NJYhz|lS_;R_Srpu!FyBpr-a~WhXLJ~RWd7+9EKQpGcrZU@
zKF5H@v^j!y29M3Zy@=Kmb1yAIwie+yVC*dYPH5R%92No1!6KmwOh=329~gA9NNDn%
zEx&Dp7e_4H=%wglNx1+Et`^zn5IJf&K>1TQ%l|&6D`D=Io-d%`VL3$G-eZ;(fiUQ4
z`RyP;y(}Z1Al{aL=mxrv<-Qn-zLqnyArfLqq-aE_rR{xKI$`;31eU@qqZDllxA6W!
zXM|;P1w<k($^IB`lw}re>Y^>Lhl3Ym$$J2vHP#}e2x)>vI}iFNEx)XSOrqt-NZ37P
znHYxXY0DB@kR*$0FUT27(@${ptfiAOBIhjQRIhQ~67n8MvgMym08O#HLEDWBmYbB=
zNVP1Xy=<E0Lpl+sTX^ST;iAQdf;Smfi^vnrOv?}xidmKgHz1mAG0cQwuH}Q77;l~>
zdL>A{CGj1Q%NCcDAXh9S*^n%-w9JH0g_h$gpcGktp}5jji$CRMiY+x1u)k)BS7P!?
zEY;6|lv;#z#<^}u`WCz!7VZ_QH7K(P&*5)SZuyAnttu=*6hW)BWcm)4FSW`$AbH0k
z_yT=37Weg#xNDJ7_@maMY=NOVi!;Te>Mj3l1ZlAJ(4DA8%L&SaG+8EBW44+t-@ggH
z7Rwh@u-a<L{|;dHEH8Zulr~EhJ!tKgO>00pEU!Gkz&b7SqG9&FCC*CwxGu{EJw&@L
zkyJeLz>-eMupY~jJ&@_O%r`@$&mvp^UcY68z9&Cmk-Px3LCdRY5E-)Ys4`>N5_u5L
zj9B{Uvo)g@Ih||AEb|#~X58Ye#4qQOWjXD(CoS_5K&C8zj#*)8+VaCCG#^`fUV$@D
zERH{+WoPqK9a{D_sn?+IVB_}$b{%cTX$f<(8SR8!XPce((K=!ixE6EaVl$s2qOLY>
zR0DF<#!N?cH=Fop;EcOX2%Y0SY-Z9C=a|iJ^h))#X}U=tt@E-OqL-4lO(I2$d~8<I
z&e+#x8SQ@kZ0hJ8aoooDDmwjbuFXL!z~%>vOa|HnQlufsW-WycgKaLaL1&1Kqzzt#
z+EgtCIbqY@21{W!ugd?=(RIgVU3GD-$Sh6MEGsS3%28ID&)$3Q%F4{L)Yr6aX_-C<
zA_6K3GGxdQ87dnERHkeZknLb2TR~76BD~)d|D4ac_nhxJ_ddUI?>XoGfL;h=M=7{a
z#xg3j4P)po(h4=45l0vBDMk|A1`!Ma?O#qa{HZ=Gl5yiTfJQMgPhu3&jDxgjILr8+
zZs~K3wlbKHWu!cYqj3x&#fRb<n|+{{z*z7mEG05lt$}(HV-E#llNt7ANTx7)sZi-W
zql2DZ_6v-2z3?WL!J|}d8Y6*@FQqfu_Cqv>QTH-Ha~T2jD7wPfLGQ#oh6AM;@)^qm
z(O1A|ISKV5h6^1#EM^Sff=CJD0qr2JGSbgNq?GaUj}R$iG}HsLoZ){6eHDzR5;R`7
zGa}hQt7Po2gxzXJZ~!`M80qw|tYuiEz|}FVbW_zc-lyyF1|ybgD{eC8mO$hdV~qzy
zZZkZ(VZMR!r4o{jj5a0gHZi6qVua0%8d~$WFqF$6(#kN?2Wr|F`zZ+7&ajW&0_Yva
zxt*BH4#uC9((7axX>r%ZIQRufH^V3dXb<DSQy{&J?-oF@k1<NO{ar?VJ<Q)@IRAvk
zenw9!xB<rQ>EP}&cD4a?kWpiS`5{Ijm4!ZFd`NCTWZa|m!6Qbs-3o)lj00-;HpXz@
z0?@~dRkZsYXB?#B_a}@!9T@KfW8EA`PBOA~0%jlcuLWpyVtz=09cSh;I%>Y3d5wua
z7iRbhfVnaYs21cP)AR|<yD^VbcGI0Xi&B6d%)Ru{tHaF2UsILY5oSp(L_L{y3e_ED
z`aF%!W6V#s0@RCn?GY5cnWt&Vb)4DrI*1Q*F2$35nZJAtJwIkw0Yv<nS81Djg2|{t
zV*qpRDfk=6Z21uuf|#R^FzjHaL=AG1`7Yg*A<PjweY7Byd3G<@Fy@-s&<|%;-voDx
z8T&N22xc-Z15Yz&Q6M^!dH*&@6f^lNh(t5L)IubN`CKXH;tbQ-9po(2XCBBoCg&V}
z`&i}-O0~u@BY%a5@yr_fVr>FbOC<}*%%%`pp{6j!$#D2QvyQ@^7nqt4;CCuhM^WN5
z=3WZSUSwKm337><$pN{{OrHbE45o<6RWg~+QZg)?`J@ecIn2;-n9pT?K&RWTFn5;V
zm&{{sxCW5|X3sfHY$5X#D()^~<{p8Fy_mV<btslF*A7DTDszMqWu?r255UqjW=Ae$
z%9zVSK+2g{93WD`EZqtd*O^WKZE~0|ok3$2^OwcIu4cN^`>uwWPIY^=%w6diSsnA{
zn^34{`u<lL%zTI9x;L3EwAZ+0XVwg%^ET5EiK%H|{_-?58kx7Bz>6lPfv&)2=26N|
zv@n079dRpj%UQVJ#+;z~=5}UZGaS9ce2Z$ZI+!~XV7HUGmJSSdG27%I-ON-u8vB^R
zcVOr)GcO0w_n5a{hI&8K?nW`m0p{OpAakGj^b&Y6#MCZ_;sa(F1C0-v+$G>1F+D%Q
z2#1;K3|Jav@+jXm#;l-o#*dl&SwI<Q{zTP-PnczNH%&6jXs71LTIdYB`&c)4;G9^)
zX;61&y}bio>}Rd8(@MmJ^)V$H4zSwZ1ez;rCzT8xWR3P=*lw&DPeIY0b^QT24_4w)
zOwb`#{W&;#m=#Dd?jx+9DN*3bYI+-uM_F20I~-&Ez6vJ1Sf5c^(wo(G27Sj_)9CH(
z!+Prn*z;xmkU*(1Kh|FQvbR60V-qw^u!h8NIDi%GfWAPM{=e#b)*t^sKbZA)2oz7U
ze*OqBA*>6(!EPu^`2i%uSjD5T6wdk|g#k~qL{p#;$$BaeB#M<tk?Uwyr2^_Ptm*U~
zI>Y+NMmxl_ET8p&iDjwiI8hvH{zZt!vkX_@MFQ&(z1$L6zpO%I5-WlNq{*zu6uUjo
z+A4#>1(uw)l&P$@ss1jFb!QkPowXnvmM*fsr;5f)ECJoqmsuANVq!B`zej`1WDTGm
z$L^5Dy4Vbj99BjL{LW>?M}WJ+x=7ixJl4G;*v)5+(E*?WRvB$@3t1g6z>8v5uLjs9
zEdNM|TxBhxr%x$s!4jCb#>)N(Ln>qSjYF@THJAl*o%K2WT9vHNBtWTRU1))Vy_)sK
z19aA~K6r@ET2@Q}e5+$UeE{SJD>DS-CToCp)VElh=@EXLwY3d)8(79NG&ZyBQW$Ju
zC7%LXE9=Bdn3*=#KSv<h&U(imgSf+z)8@5<_2#P}U93A)huzI`qkU$NofSxXonF>K
z+A8(2JbK~GUDmHu3UiNDMr(lqmfx#ryw6&6AAS$A3Km0Qh*eL8S`S!1Ie~k~(s=^=
z5z9v9mBXx)lqMWut=Ix?l;w3CK8>-adq82FmA3{cPgpOf!ruv&ee?lFILYe!2PPcZ
zpX0;Z4*S>}Y3<|0eq9aG{cQJbKyzXLwFCMG*iCLwaAmW)Kn}9K-5}z|o>B-sced9(
z7(B%OlulwEW-p!#a)cc^0WeSYTT~r)l)Xp?e~+;p_QEGGcD#50&1dbtJJIFC-tP$m
zzU+3|8u_t}OF{hE&#?g+$abLURuJ1-49Q?Nvk2TtcFZ$yEQCE+4c|lA``*B0g|Xvl
zuY8LA(m{wsu+<x(ewr;zL1QHQm1Ss*VvFbl;?eBCXq_6ve#K53fU|60f5@C;->*Y!
zEPHQ08spe8w4IM<|F0gF64*1-(3i-Lqs?CuoBtO`GP~{-h@`N?zQn-Jv!~NNk;?vk
zD!fl)zekUtboS*J;KfDuN!nXnV(-`Dx4O(0&;hFq_PTL;24u1Sq-|F=yHW>|!w#ij
zQ!d*buPBEr?4VWP^4Q6AYB!&Ky8@(;J%!S+MeKHp5*4#Qr>#v1Tf7f_SJ?}9!QWE$
z3?)Rau^$}+DQEL(rB=Z{w-u7t*%_4}mF(SD>1<LJJ9rPKrk36C1x8rM-a)4+>e(Gr
zp?HHG*8_5s9T1AfTkOZQF}%$l2?A+ktI9x{*hX4&G_#F#>b8Zg`UU1&*_pdwu#KHV
zmr*;L_XvF*>|(n4JJ~B~LEXi!okIV@s+%401~huu!Y(+~%WkBkY#;lRNhscB*V0<{
z9y=dtZijyMQHnGSu&2?BYLH!xXNbcP`=>mJJYdf~0WTi1`)t5|#NJCutYNkf3w<N(
zgb(5U7~An3jPo)3xz`{$&er_|N&6G_>5UMbU^@(;bCUh55Wk2c$AgxZP8<`}W;=7z
zsJ?1HCw?5ng|nW1*aMt?dJemC{GNfxK~A#<#GUi@N9gn5%wxdBA<k~9*+0x_P6YH3
zjxTK>j&WwM#~{2oGZsR`+s-+?2O7sY-@k-TAI`)KIPA;WMW@vKIM39=#S@%wuYe2S
z41EoaK+f5E3_FN3Z!Q{xIp0d4carlBeWNRcQ%<R+Fiz*YXbk7@=)G}@leh$~MR1gk
z@ZvOQD^+nva{fueSfV&~+ctDYa}2p4F`Ro;Y<7k-WgGO*aspODCYJLJ12A!%eEO<E
zJZA=-4^H6degaA4O#2;uNt{vI@h5Yn)i80MQ_=)-ffH8+e^WVM-vC$|r*I40PUo2E
zDDGv>nYW;q!MR{}guzVC7je+Y;*=A~=ICfcoWm(67jrq6{Lz@lsp*A&KBvVSTmh#x
z59SLwE>zE1#Cg0P^Hj`{(ITgWqp*RLa$ccV+BHta8laSM{&4|U&iP#q=nBpT3gTbq
z{I%1L)=JJj3%sb}FhW79Ie$<%yM_}&JJMRti_bu$o@1K>jT;=L5aw@k3ckdcZgGD8
z6KJ<NN2$D|fioEjXBs(|enVd~$0r$*EgaReXl&&;(eka0vt%Kl+c_oW5b5OX*i38S
zF3#GMXzk{h8z9=l`K|#5dpUnm*rJb<_$3tYa&jmP-p?7m0d9bEhz)X|^V1Ma4023=
z18s=2IshUMINK>>^pLZQvV_B&M0(+jaKc*wHp;0@1vkcdBL$Q9m~#rTD!aotheO+-
zC!F~d;h5mKP_}N8^EpkoBiElU%Y9tGbr`)f_v}M(`?)R8g1B(|DQS0ryN+I$uH5bu
z06oZkBMp6S+%$?~d2oGg5IMvhP660qu8<FrBivltCwg+L+#q82;yR^+_2#akBGcpC
zS6&41;hJf$;mZx$fWi22>t|vx{@m(kFv0*Xb2)|`$Xz=My&&$UrDzQ1j!`E5B)9km
zevuF^hl(&lx#JWs4Cg+g(<Z05(`JH1a2HT4{xo+Fg>WM6+z1Zzqqyv1=tpx|v=Wcu
zp6rI`8SV$?AbOUY_d5E{abt}DjpI6%Lm{5)^g6f%u4Drw6S=c#b&|wgK!xMU+)|3{
zr*J<#0<a6*x}Py6soZ&#;Y#C%{|1G0?lV4+yvVh$qsMdxcM-)#GP!?HP&|ukqkT*^
zw~1n8Io#C^Ai3P$0|33kT`I<y^0*?}^yYJ`iqKfdHM|OuBJQpq;8QX8N(9_4;Z9XR
z<SLh;1N1fSHUad?xNYB{ubkUQwJX=TLOZ?mE4ja!Fd0=`Pl}dSb0g@9TEmT}`m9>6
zc^uev+{y&Fc7uE3ILJ+I78Nhv;x3^>XSccabkwhb`w{IN8o3MUIn~6Cp*>j(mpuc}
zt=!Au5NYFv>(STFeL}(IJKVPhX%E`L{a6GSySclD;eHSI*Y7}jxf2u}>*LmQA$phl
z1>HIKxYsv9vY$KiMTiV=f2D=ueeMK3QHQv3h<Z9a;NGLP*+Xsz1+pG-|D;^pFt@z|
zD5G3YDvKWD)@?-NWA0Ov^x@_w+*y>fpWsfT3vrVB(;w(`<keC6#6F&(1Tap#x^ZyM
zygbTJxbVX2AbEgynF6Y=yxxUSILNb?!6!G~NIAgVdAlNE$%D6zp5TXhxh6;+;T?)c
zpC@lP2$)BCEAh;>I~?P!orO*>-jxpk<HK`y2j|OM@dpO#$E*4moIme<S|Og`WmAMd
zfVc7zxIo?t3Q+{{BCf)jVBUw65e(rO&cKUMo@x!aFrJ+jCgHrf^jtp0d!rV=<Y`{!
zZMYW6WAB3(_9$LF)q}?HrqdJo3~vY3;-BSJ(0Ad^@nlkvSl%lXqmJVhtDqmx%Txd~
zk>_&^FiE^-x_^>+5-vnict*NY&-2)HLihr&!3mA2yg$-#U8M6uUxWHZ-ai>ozr>58
z!@QU6yyNuR&)})VXwBsH#{(^g$D=5GE{`z){VTkKOmKO;nRGkl^U}*e3V0vA2!9KC
zMq0@i@$N@Mq?mV<F8LDP3r-+cc`IJPSW0<sH-TK^$*6pyj3=hkC*{18ln|`o**A|u
z^g8d?c6d?ATl^VF6;JgCG^%-f^FeBO@3uj)o>%e*Msb73z6$d<dC@x|d5c#|AF{g5
zd+jvLH}L+Ux`#&Ix+&nAcq#O%YUZt>kXZ|_hGJc<yiXTEy^Z(Vr!d>j%d{r|`ws6b
zO0RVA=9FSgojfxg;pyUi`6s5Nn-`i5#U5T_8l36n9r_mfeY_aD9r}4Yscv?F_f8nN
z`@E$y&^O2%qG<RKZ}m}-2fXDfSa`^L>SJI&;zjHQ<}mLlEjUMb^=@|1QQk~HTrFd~
z)s^t#F>e}GmW=aWpk?S2-n`GCF~L*r2RF$Z#p2e%k)I?7=sy1cCZXrV52RCS&V1j^
z=sUolO9u*E`3t3JJjidSx<NNS^CY0%`DQDK2S0_D>xcMPuhac^n7_XTtw;E~KZFTS
zejQz&NBNo;0prDYo`yzmzAFWkkMpCR2JzwF+z3m){3X5c!jGSI4#b~-b1N*J;NPIt
zP5^(3AJhZ+@1&zIh+jwHnv?ux0hp%{{uq_khVmC9f@OCI<LA&WES$fV3R_O`eFxxo
z1pmw#%*<*2Q7T!8<kwKDDT*KP1bxx`Ny;sq;afMri?jS^XhC(3&uPJ!V);{k0(KmK
z%3C1ueAi-lk-%R{tNuj(JW2*9@t=Q!#$>*I5gP3&{JX6XP38Ydi_0|rVSG}-A)T+>
z1ZOVtXHcN#62FJ)MK1HPe8sK8*EqtNO#V?8NEY8ppG3>%r_p;Phd=lX#&U)KHysMh
z<4^q*jrsi9l&34;7y6*Dkbi*wrCt$#3LkpKcK+xd477ybD1*jT{t_zLDdpcPN9Q$u
zu^05q`E#DbtXJ?khtPPPUrZ5)O8)&?=vDDsMR2W}U$+A$YWPFhP^jgzDc4!Ye|i|0
z_56)LK;#Dh7240-;?J)Hxy=uv4Q&J89!HfAjr=@1(A~s;kG7P}d>=Xp-oiKOA==89
z(uTT?zhxFc+xchc6?un0Nay3a_;=}uM>qdxTGIFM*|Z(&<&RUEy^nu}f^&EIy;CrU
z_xPNDpx4iDp&Zcwe}MvnxX)juqV&Nae;ch|AMn3>2Qm-&w`<_=BfhT*CWiU)Qecnp
z*HXTFl%J&p8RJ(Shog`A7vBKdIDbZocS!f^_D)(1I|()|hPt!h3e`mI7hIv(po^d}
z6y$*5F<m9Dg4I-rb5LNWDRC3jvVh_)xSS4=Ljo@e8V?J6n_>2d;BF=wJq43jp>R~-
zLRa1~!8W?5y#y?J_;?FO|Jy+b{<g1!hL0fg2+({5^H&1qgdi>uT!6rHE=Cq8@SwbJ
zkRXc^1;K((DdTifkg))6hX`06PzV+5y9N_s0uen~!Ub|lJe?AVr^C`|!ED+NMG97Z
z2FWPF8A^^u3vwwmA0seU|94jiu2GQetYGI1xOh(BF%Le)3WENGVw|Az6)46F?$A3b
zQLw%ST#_JxzC4#K*hR0g6v5mGaOVX#s6ga`Ktl%>Qw8Dk;Aom)$$DU>3*>pgyeRNm
z2a!vHbF}Tu5PY<bo+X)rf_zxY68Jm@$rijsr;Bm~_k2Kd1uK5WFLFh&wiPDw1V06U
z<O`NK!ft`!)%)<NP~c9-hD!tuw9dXN=%Um2rGhVM3x7=zLN|JuV2s{I<$~#l;Y@|#
zB*hx83kELIUba&3k{|S|1WbD0R||OeAzCZ&JA@gk6Fh4`U%j9-8`w7l1M~v9DLB^(
zkz0Z_!63H<d#R|rK`?{%tBrzPzEEfq{6LTHX2F3A5NQ=$Zvtr(B-3|o+64m@=({8M
zlMcn&I|M_tK<E@~dWhC8K@f$9y9L}m5bY5}qA0_mSD={&kv_qj`yg^pV5ZxsUvO9l
zO9O)DXw1cZ!QpziHYhM31{o4OpaXyp1dr?C(?h}TNk~2t^n45TVZkOpD2xd5#W4Ta
zE;vHFlySjQiuOJcOui4934sU2*d_&^#ep~qkNysW`-CCnp_8zjKAPh!jC6<oe&K8M
z@^=xkw_-|Nh1)4na8US75%k=IpU{@pUAX%QBt3+QGB|TcSVURe!@|LTfO$k{@Ba(~
z^%N>{(Roz(qzc%_gz5C`^%jm-L*}^fwI8A3BfN7J*uKK;x6tS(yuJng`U^L_4DN*R
z9Wodo+?oizK;fKe_|b!eOZEaYSePD(xd;*NqEg0C;n!5J5hh%z0~anVw$n25lrV&9
z?IMI5vSH%1Fon`dk-}Pf+(ij>RTx^dQ2YP}V}$3^0D4YXLh<idp_VrEaY8?e{>KX)
z#^6PQuz?npiNe=td!8ix^A_}yg=SA!ND=Ni3+}vd?>%rAgiXy9OG*>IM7xc2p%+!N
zUlcy1XTl|6$!E~NER3M{W`;1b8+J2=;cL;CCH(j_NVf3tM{q4i7_5S$xk4W8Zt{eo
zk>K)$3aYR#5H5BBDHH}#k!O+ccY47W3!l3Q^%7xhES&?qD%`mfFr`AvPKaI;=Dme6
zl?hKZ!hD60KOGKV7i#qAs}!a_L1UHBbpk$B3un`YzDC$-1F01*`vxd=!Z$;JT`%lQ
z0Cz+9uouqU6msbMybZ#&ufTkx@E=-tHVJ>(HU;-zt8n9A=xh_le2CGv3%N9xeZo)a
ze9c|q<J%zjggfcPQ@`*JikJ@wvp0j>7k*9E?1RGT=`b-Q^rw=$2f|fbVB(?hHLC7;
zB>d4I+_2Dn5ky9W+h}B?!mFDhIVQ|=g}VK*a3j59$A#Zez2p<&UP?ty2wUj>n-r!}
z9@tSd`7bo~iG({L=_G2rg`qi%-rbMJ{UX%|7_W<H_<tDF0nv5|#^Ne!q!`6P(Lt&p
zbrUWB9K>CeuZEt7$Y%*=^pGfk^6ZE0q6r%45m7IdGkA(D^ng1mIu!toW1_JvG<u0X
zr@BRNQPKwV9T#!7L*GZV@?-S*iso#_<ok)%W&p)s6iiv&6QVEaT^u0tx&aa>YNtnG
zkmz0|P=ZA(c7Z!7is``ULqv8DdWnaMexC{V!$d;*(Zfa0(0R>MqHmc1jSz(kp>bNY
zF%$ZcqGNji8YQZH4ugpnef>73Bt|rC704OUP70i#75(B5k#nLwQ4on0eLDu|IMI9i
z;C8%7%7$cuD1|P8MA1^a2nLfxV|s`ti?aTOi4@VZG4ScUXm%%LE{Hy%$W*E*I|q$v
zqCl!LNEbQMivFVLWmhO%5@oxhF;jF|3P-a<kHessEpnq}RgUODCe(99tFJ=jifF+m
z^yP`-kji(+7kyu2M`wZPbE={*6df4{S0u`xgr#E9r}XSC5gDlV;HoH-F1AupAPf4}
zL?x53TP8X~A9pAhacSLJAu6Fg;dRj@-G7y$J7zRiiArJtT`k&2iI^JEuAT6rR)qh+
zgIh(!=%;h=^`cZN?7ShGq}tD$qSS7{+!F1hr1EXiw=bfvL8Si<ppBwM8GvaLb$$vj
znnmlz0n;K{*8>x+q9<P9+C&2sdTSRQ%7wxm5tlBH4$<C?=<5{yMwJ9zqQoD8(k<#n
z#f9CWN90t5f%b}=hGDQz#HTI%T~XH;fVn3cc7ZefA}`8A4TzRrgUEeRH7%(JMa!oF
zZAi3q0~8*J@^3=qq3G96*nK40a2y^Ei>m1W{D|mRib{-%7O#cKm}oC8o*#?0(U)cH
z<D#To$UG5Moq-n<qI<NfniM500H~vQ)&*$n6aO9t5hw8%Z$ZRayog?y`^5q80@Ou3
z_c{~~h(~ur#8v!T7+gCj7AywmCeEaCXLs?;@4$J8?O%Z$5*z2C@vzt_0FEBDiy5?D
zI40h-5UpO~Kj{>UxA+~ZDLF2-QPR>!-19y9e8o3n;kTc79~+#%ct<7lPl%5{1{WZn
z-vEU`v5FRXLE<qUTniR|L-+kjad;juL&O8&a642y`*UE1iLFeGK3r_?y^GFM;wXy1
zM~Ka7kU1@0&4Em$IOi9TC^6?PTzb(MJsgb@FLQ(B88P<_m_IA#eTTkt;>g!939;gR
zCm|9i7L|dE7dO(d6U0AE14$IGdI``;;uzW&B#RIJ4K79erJV~m&WktGF6V-H4juVR
z6+d$iKBb8#=<%K|UVZ^07sY<d(056^h$<&8i@&0<e1`bRI*4S7-=oi)W{ID51WK;>
z%4H~A5r0N!H1fn-G?<xu@ouUFEfDYi1JH%yJ!z0E632Ve`>$A>Q3<pX@diqfT@`md
z!X%c8f2VxQHSt19#FmN0O_<VhaSLtLD#R;h1MRwa$9qt(7W;h)QX}3<*`iu;$rrF&
zCtmm!EY*uUDGq-_yhaJ=n_^emo!k;n(v#)3_{e`Bfo~9BqGF>)aS<&No5WM_=g=(f
z_!BZM;$=bLTE+3tfwYOE1psXq&!%wG9q}r<$UDSR+Ddnd?SF&o64z5zZMS%o>Lh!_
z<8Q-mulPJAEBnN^zJU5&@%nji6#wNFUwFasFY$AAU<bs<ZBV=~=F(BaL9w2$iy`qI
z3L8BTyXHdwp*W=k1AQc3n+7s0ev|wi5r1R^H!2o=29Ysw>?nTi$Kp*CTpSk%M*#DQ
z_~T+s!i4zh&k&gu#{|JON6B+^HpIS95-<W$C&_a>jKW#6h?ZyjB|h{vbdjv4%jAG$
z*(&t8N?v>xiU%bpcEF&U<Sr#x+$HmO!3z(d!R<qm?M*OvSmNb}89gFtpyiRLB$5iB
zj!K5sf*g|wuAt9L5}67~Z@XmW7eG5MX?z2AeI!qRgic?{Kf!49ll(|;Jb#HJ!JLrP
z(Ba+y$?I;A43wC6!KWa}rv30DSn}EkL{3W94goYoVq6YOp_24EkTA(F^o9+W%%Ot1
zQ<9mxp&luTpoc+}#O_0>k!VRE-2gF?hgSf4M)Hgrjb|nNrvQ3Rl1!yev6AUZxE3dQ
zu?-^e66XdqCP<=x2bU;WNddJaN$^)dNtS#?8<G^syilN=m&9~|yC9iH&)!tY%f7Ii
zCYeb)+jPmBcB&A&D2e+U<dUR=l6sdV{3)=TA^Ds3kC~GHy#~=NN$l6)vL%Noewibg
zPuaX&$+cLJD-thPVCPBNqF_E>l24(^0?7tvpcG18{}Fvf5*bC0iY1f3z(R>+D-&Q>
zB_H?E`>#~udJF6|$xDwRQzn^n6Z2dy*;xd%3P};IiLXl@oPbEBWO^zFQzdadg1M-c
z>=M9Ijbtq?rt2loQ-<<}<hx{$o07Lep?6Di{txusmh7XVw+4xCKAdTkyju#9Cdv76
zT7Nc6`sEO9k@z&hM5`ny9VXf&30t7pF4<47*gKL}qu^7A#F2x>PD!B#q)Spmv9oST
z)kc8!NY=avu2)i51+YHJZxs5zEBQShjrSx5db#vVR?x|h0m)~yg1Rqx1@CgZ!=U8l
zQpgNRKA@Gw14%puM;=P9Rl~$1$pfk$8<q@GJ<^C|Zab!QR5BC|g)xbYg}%p<AzHkT
zOO8-N=!qodCiEsGL5={Mlr%X2%u%|YD&_Y{)yYtBlKRpX#95lzjXwK+X~9;Yxkw`x
zLF0h*EafC!rCZ;I#zAR=5_a9BE{7oEF5SEs6XYQsRASZ-NqIb=9hUl1mBJC}%5S0P
zDQy};<58)Bo<7H<y`MwUOB!?o#9MldE{NmOr)YiRBRxWKCSSYsqhDajPx=96u>7Sn
z_5tRE^u^g2Q-HL99(RG#5sK6VNk16`Ot7?=YVJ--k39`8M5=uodZE%Kw4e%;zB~dh
zT>5@6P)<oR!oWpH&)cDJTKf6_U_MeRpfo^~^vx8IGg9wY9=~Y!9EQ`e(kO~D#Yr#P
zU^HGTS`CsQUA+iUiPF1tn<q)HQBEsa$}WU*inNQ8y62@sFN0i={v8M}Q>7nLh#^ht
zPr0RZ>7{=GeNig)0?H++bvwvq=@j~qVTSa}5?IKTerl(%VV3j`MNhJ&-V-p9BR$m&
zk}Lg(mMmAKE8mBSJZZx(0L_;M-$!48^k=GcEtJN82vQ^s)<UFMdZ7pkCDMV-aOSFX
zoK`HQ(uYzE{hCyG3l_?xdCx+!T-qHDXDX!oq*POTU3%?XbXH35(%oJqotFYj)zVr$
zL~Eoe6!x!`CebUnPAaEsqh7l60VHqW$AQRg>25U|8>D)7fHq3AsH~+)8bPV8X6Zu8
zQnW}1UjS*9u9}21ZPJ7ec-StT??N?2cclFmz;sC8Cx<(wt#3fFOZs*&e${SiRtvZu
zX%y`WdZpw2AbrvrDqXoNz0nP{d(zw@VE0QqWKbB8b{gUDed*J$gA7Wy(hGS=nkK-^
zJdpmo1KdMt5-mI)N!fUx<6BHpLn`c!NEu0J9hEMk!n-l);Xly$SXxUdfpMv8Gp6K;
zbOV)8PDuZ9h22T%k_Z@dlv$sE?30zyBG5^eL0d>?S=4g4y<g@?kwq6-E4^6`$R0Mr
z3s;#Zy*&=fUZtgm-A(pAmGrvHr2hicL-sfQGDl=(l+W~(z3>;jI4aw89{R^*&r<cR
zm+YsP;f%M;l!V6PvPBb^5+B(cOQGj0`<u$M{A6nbf$cBb$U)x;8Mhf00%RZ2I0I$A
zPT+!Ma#~>p+hwm%L360ABOah(vJu)Mh0Dwwh@O%u-@=$8WZzJP;<W6w9Dqj3!Xw~*
zl&mTqBw98U2ecU3GJ0p9k*%OZ24`i@xkK`tEQ2z(v9c=qoN1hl`#MG+FZ+XXEeWz{
z1E3RScKh3KBS~g>3yR6I*jbQCk!_=E?!0XL0GzoX>(9W@Qe{iuL}QxFS^>0lnTG0l
zF3R?HLGO}`xe#cVWveN|ks<rl0u!0CSr4F)C3_|rBwJ?L3y~bzbh@l^WuHbt?}|)q
zr>9JwERLSv`LeI+(>(>U?<gKsDBCd&T#?N46_8>X(;J{Avd>gdxGL+RT~w)T867gX
zCbRdWuT1vMLik%Q`*${mbX~Tt940Dd)@dMBvJgG`s%3ptzEmUgaDzy#Z0a|(2Cb9r
zq|{5j>=zp74cSHt(A<=5rU||!JM09F+p-!8cQ(jYEQO<uvUe%X-X!~Y9)7fD*#nAx
zw8^Flq24Yl&V=M0S=&l9cF59CL%mbRNd{(@ERt$syJg$xA<`o|^bzd=du8{7;ai`q
zbPa}mSN0PX5Z#k~D+1RqTi^xv2V_rw0<`<GQ%?XhDD$BUaY**!dw_W$`-kc$9?IVM
z1bUBT$K#+dEc2v5$B69Ii*ROC_7RnYjLDWPgWHc~Zd(90F8d&q{t?&{Sxh-BO~_7Q
zo$D|u%ZmW0qg=fJqu(cwq<xQ*oK*_WS^ncZi0qe-(4xpie)=7N9*~#Tq0d!r_z2hs
z<p=3(lbc*fSy6ZScYH{C$UmcVUWepkly5#PKhX-2Bl5*rP`7)^w@@<rsC+)f@{h^a
ze~eBq`By0zp|@Ol4&=D}yCM)D`6Ai}_{v@CFkV0Tx9J$6zg*%A^C#p#&H@)8UqO$S
zK>23Mjs(eT>0J>lfBhqvKPi9f3Fab1exU}Eq4L@E$Pcs2+bNnCE}tBM=qY(7B`qT4
zv#Buhw0w0WG$Q3+QY~1NJTwq6(elu3P>7MgNw3l~^7UUq;jBD{w(95P*G>a8RvtYA
z^Asn4DhFJ=JRlY%LB8V}L=xrO8(}C(zL_Fd$#VN*x*b#G<CJYYFK>Ar+y(htRF0Y|
zpH={pCZFGjzI1uo05mSj7Y+mal6(^-J1)zORJ)uZUr!&E$do@rkI*dniBF-BEuR_)
z$sGA=cMKv|{vutg`SLFU;Y@-2*DujnD37#LxTZ)xZiGg${9!mcOXSbrLFZNZvXkg5
zm3Pwi_L}^w81$9NuTVK^xm<q?KU0PLByHZV%YQxzOO^5@sxz#T*HIk0T3#^%^%{9r
zArxxmUpxbU>*T3<P^g!$osCJjA@^Ko$2{MZ`#g`%Tk>%g^l!^wp-p;&Jm@?0HOhx6
z_t7NZUJu1)`6#7xTI93l0kl>A6@4eOP5vDZlI`;LaoD{hpF->S4*8W$=<AewO5sJ9
zJa-!Uy5)~TKziiDPGI)R`59Et(<g8H@5Ymxj{)YMd^=UG^vmC%aM*zS%!fd`FP9gA
z49dTtm&}m-YkJW?kbg51Xb<JaUEm(c|EBt-Vfjs}ryh~JQ}xHF{QgvUF(zO1JTM>2
z^C(h2E<Y0u?uk4bPXT;_KrUGh&`J4PGZY;a?Q;OSPw_qNJ)IQFNASs65t@m{{fbZA
z!MP~(v^_nbFwjQWRZ*}9CJri0^xAh*R8jiZU6E0XMh}HMtxpaqYzv@%STScW%pXy_
z-31X(#nSK5Xg{i0z6*AbDFU70zL&yd8Hl$cY%WHBT=Cn7=<`*)I*QTzDdsJM-~Nir
zbaS0he8vHGfa0TEkU+(oVl)ORf<l2EtoV(N;ht2y!9!z+BCi*gLKR!CfD2QsVu6G!
zyeYtV%C5+x>a7UHdMiwvRz%a9J5n*@5bQ=N3TV|Dt@vp@oQY9P`5wbQqbT|qeP<PW
zDKv3T@n;D{VikY4fQwW7I~OSNiUssZv;>7P46Y?A1oZStQrwz~zGTIHN}{DG+$hR=
zUSSXY3+x4jfVOn03L`z`(-dsViKQzZsW2B86{r6M%q7KHZ%AHN948YQie%b-Wh(Aa
zKsQUlqA+Q;;tUNmN3ogerg9Zu_kvteyi8|1@)U2=8b4q00Y!NV6wVZrFI0SCUk;5T
z#q+_CDN)F%eEq885#2zgibndcSJxEZH$tOK;Y2%~az*VW7_3lK4#KtTibq-CDizlE
z!Br{d%VDBg(aXi?YZNm|F{D}rk1oAB#dlVadWFXv^xaS}%b{>nk-3~=)wdLxhtPUk
zvFQ{nH7M@?2*pOl+wWl5O^R71aIIPK@JEckMUnqHhTW>*cR{aB@$O3??TW2*=;n^X
zN;{PfMFl0~I~8-N=&Vc8I}EUH#TQgB)uV`^f~Q`^^e{Nnr#RY2UmdussG#`wJ;fgS
zVfz&~wJ<TDSVzav?<@K_fEiSrqicOgQB9vVd!Ug228D-;MHNtZqzJkIyTgi)Uw|_s
ziZTiMMit+;pm9v`DJ|X~D_m&tFs`uw1uvc`8utNnLb0=oYT73iQzzh*qw)?9p6*j_
zJ_52|$=rrU7iG&y7(Afd`5TC<as%b24l19gM46lNCdHxMl>vqD*F$-<1muv?n@ScA
zD@(rwcSOmdP?@K)Zwv;HD)-VJ;Fxm4A0l4Lgn!_#-CMbqmUYLKQ{RNAKFYu8b>^%5
z%MUVs%2%l{&0kqY8>SP=@>YlhC>`H~`9LM_I!KVxgI2-8%FTbE@1&ALOP~<toDuYe
zDlOF@Vajc^QVmzm^#|A~Wgp$C5z43E0y%A022KHuRPJhk!%@oVtDzsQ6jEk9MyWS~
zoKdo=(BrJKj82QjDV@cDiC6BW1EmSd8K0mrQJGGlNy=xxf)~lkCJLygD7S0{Ij`JF
zr6?Da0U02vN`Jb@(v)G*@F`ts@1cj^MWt;wrsk5;Q3P^Xxrt^rLwS{IxiXd7=}^p4
zGEV?ITiHql>p4ml-G;f!FR2*#it>we=;bMId<`yN`A-&Ry+HZNBA6&tzCd?zk@EHd
zaK%d9zfdnxzSRPStIE6fg_!43<*(}?b4@w20w&6oHrhIuEC2KbOoj4SC-hxc{+R%S
zl}g=NxL>8begTcu$|!mU)+lWs0Hszr@d^6sl;2Yfrd}zem(va9{Wi?ZP30qcnch<N
zQ&Hh<W$q+I8kB>XRJ`A)Yz_umlQQ}cG@6wUDY@IC?7In>R%PtxXlzsJY5&)*tfIod
zJ4#2&M0P1_Dk0ge-2FYKt4H}tCQy2nZxdLbGHy4>UFD$PmglD~woktSy&>hvk753S
za<mwI50!5|ji2z5at}pthm~e3NE=a((_!mT<z<R7k0}>V1@vQO9<8&-mACzY@<f?K
z1xFLgiAeNKD$i2AqN8ekCq(wCrY*!2I;k9Knw?dj&%(s)SE=ok32{*sG{gJ>)k!K~
zbyY2C2h2fL6s^VGRJ#^J-(9s~F&aHo>#45gkm?x<d>vNJybJD#Duvd`o+>ddo%~g=
zorB#Is`>Ll0#p-J>=LMQm;n-`a@_^jf>mcID|1q{TVaQOi0Ykfa4J-#B`!>Lj#9PZ
zDwk6*e@gWd<qjiMoBE+~T2({~xJXq#of?QzT};F%qE+%|U^hn9O@&TpR8yMa%vsfT
zH;{9xclV<)RwbaYY@8~7Atd8fuWSZMP%S@7hszUHGj@VaQeCIrcCt!Mi-#0dA?-lU
ztB(8u^A}VzY3-k?ddUMMP4(erh@`7r#2Cy))wW=mxTGqeZQNzm8Z$174Am5>sLWKI
zp<rB=>OERmWUCfY)qjraOFCDbr|Oi_|9i?;`6i;ZKov}@=R#G89iT<3w!ffXteQ&&
z7bU9tEr7YI;{1WWQq@6PTb8M6gb*oLjZ(~~Le)lR0j{f@uYy#nLg|ELm8v@cebuV<
zRQ*(=+C{1VT2(uRR_atEbjZS9ue$UOG;XNeXtjS+wI&hn-%`2X#ISFxX75B_ld9}6
z`kGajwt}>(x~@ULO*Ql<oM~6(jzHv&YWV|@4%Oe=;cutv#T=k?sfsBm-K|>jC%}4C
zKT^?4uPQ1R&h)8fQQr2hU3EJiGWS&ZRNvCCvfKmcfJ#o!i~FjdhafYk`jD>RA(dn?
zxCg4r9H2c^g?EBHQWaEz4680Y4TB@9M%wF)s(2K#9aH`99uyv{PSyc)T=j@T9Zyv6
zvjIJ!Vy=a~NtHc<f^z%R4HV#aQb#32)LA`S1)mP6-%muJtGc!XLp!K$4TcwPYIh3Q
zxU0Lqfh7<1HXg_kb#fyVJk?9zL*G&LM*5tqw_33gJ{?#8T>}vx^$10(ebt-jC-hTu
z?m^ODZLu>jr6<&HErp2yHJ>i8K(%}m{0>qNQw|_lJ!KyBPpV(7f=Gz^8s#HH)pxzY
zg{cSVjtN)4_B_m=QoqH7dW71SzAtcE-QR-|MymC6nlMV8Mla}Sb-NK@G3v=f=sTmn
zokcN@v+6JZ%MGi|bSf!U{c|v|<J1|&a4lY)vjom0s7FPBNmRShotmT$plociI@A?h
ziaO*saOc%l`h3#`^@VI;rmBP5;AomUVH6_i>V$9M;YGEAqVJc~917W9R!@JOmibxg
zjTBtWR{PSzF-JX(p8UD$kN^A5jXFyJ>^yaO5*qW>YbpR*pk8(fjuxu7(AU6<)E6rt
zQmo!U%c>If8CqssRi|tLDOH~s1G%Q&$%A^Cx*`X5%hd)7SXZd!D2TQ@TvzX2hoM!f
z+jaxHN`1Kopw;S6_hP<k)VEGSu~zLJ0q%zS7*#gjRKH5KT({JNw7j{kex0_h4eH)k
zq28#Dp=z-vbw?{qG^-7C_Mk<*zyVylnoYHgchoZaq*;eLArOuBes%nNz#dTdKMQhS
zo$@sFAE@2Lka?*7h935h)MhsNhSfQJur#8cyB08`YRfy|#?^rvVE2jo@)D2<bt?^R
zpXS~P4BJT)w;U+Wnl~x*wqKJn6@4z6_N@Rrpjp=j?x<b!3~jTIX^JR=;-#6g4CcKx
z^UC4(agDhNmV7i<D2eT>@sEWGKh0O~K+#|G8qMqp&C81+8K9}6D0-kqOFP>j%|_bp
z25ZV5q4A`~jixeGvzV@nFpcYV{08BgEQ(*8(%8SDB83Re=4mi-TJs@2Z=yAtGf<4t
zOcbE+jE1oeqGvUgV{r7GhDl+gSWW8+Sc=n(R$*xIn)mx4lAuY-ghHa`*Ds)+q-mqm
z%gLIs_rRrS-q1nhyvCEFi5E00JkXb_sj^SNsWi>QPhj_wrjcryGc_G`;IcG}zXr+H
zc+Ev)j%NPf;BqxdLr}b;siv%Ip61XunBaU(6a%0InnyF?Q=#SuO2HRt{_=&R#hO{U
zkSx)7)6({;M&yTamTFu!LgAXG!JR4)$~1G<0=rz(N@aBwnk);r>zd44=&RK1-Ua;{
zjY|?pgC>*~*o~Sz3g0woZc_z8vu5c@a4njoDyX+=rZ}LnU6Z#T<c?-F9Zl@excIfq
znfkJQm`<kkXf8hm(yKWZ4UxN=U#Ud)o~F<j9`<WWJ;4oV%(39^YeW^WH>i0?iHsr5
ztF>_Zfkt{5zC6@q`+<9;d56~5!<sB7jCxe_d@dTtG%M+?@L2QKG4zdVDptb5Cz|K%
z0t{(FGjtHxlNu2bN9|xBI`?URpm2nf_Ri<fch+9?gyMefs52T}v~g5td_cS89zb2S
zf4XCw2eqf^vU1bbB|*|%+e0adBicXY@ZzX8<Y{<#Oxv>@1N721xuDNmyY`4329Il7
z9|FxsyMbyH{I!4HgXjtEeTt$4XxAEn9jF~-p)W}5RSm^p?JAnJlUf}GGefiky|@lT
zwJ8dqglp$e$orIb$29asXfr4;ep(y84eF8F*HthdrLCO;N29fG?xvuAjP|2kh@R1Y
z=?0jy+5-9~9_O?<(*YB!)qV*QuboE8-~_FNCOA=h{V%{IX@3j=XtH)K?SIZ|&j!G!
z3)(G1@FG<^lS=v1v}2_ZN!Ol8hTcW(kx_7$v_Fu&3~e;>MRtcw?Ywq)lcg<Rht_PZ
zfX<2LXg5-kPOdhFmf}~mMc=|ikygpaToh|_UC~#fEvH-is`d<pF-o=X($lU?8%^)|
za_!2;=&R5=w4kp_`!uOnYpW@BSEFS+fYfSh{@Ya5X*ms0yrC6V!0t`$mN+Qh()w}%
z)2J2DzYA&7ZvO#;Y1U4kiAiYD-lphWtM>UkD70x8e*%SeZL9|*JG7N&A=#<*_!tJe
zw7h=wb!-2mC`yl3cMCJqtKHlP(x+{D3Sf8b+ITv$eoy;0rJn9<*Hcn;P<x{pFhkn=
zv@3d`U9}z954DCa^gYtP%7OlfmN^e|Ija3x2kbGe8yg~zwW80_IIgY#2@^D_wcUZF
zqwYr@$Ufa8itIS)KKTmXJL~4qLwdi?zB>Ts59p?^hK#H3pUWTzbv=(E>ZZF*F$#Cx
zi42Gy){PEA@`&yt)lhosKKu+G9@PaGLFAZj@LLcs9cMcH_0~Pd0(V?@i9TE7r>nXK
zOn==|RK9mYx2zrJ19Tg%qA^hSqWu-L2J4muL*u0GUs}h7=ypVcgy~`^+!L<*xDPXP
zN|)u2`HIl({RQSv>yA7COr$P>jlO8zeY`gvVsy)2fx$Dnb$T?O)m^5N({s8Xu%>m0
z)fLm@JYKhcDeNWawh&mN?)f8>R7=u%Q>k9EZWhhg1)a$QqN%#L9|4o5dub&mI9>M-
ziCon6u7v(2-8k93tji38hZ(x>Q$aFy7AgwL(j`0%yV<&hGvHH>?yofXl&i}Q0e3~W
zKMBxzx^JstC|@_Bpw&i!E|!jj7V7p>^t4zfpj}{zu7`e6eDI40PfK;{X=8j%x3C^C
zWxDHW=quM<qXbEX?&zmLyRQ4y0p=@pM+)FtmF@xMDXMjyn}J!Q3!*i6t?oLNfYs^B
z{sC97JH7dZDSkiBpZdH#NdtsiI@TAkd|UV3FCY!Nj%N{5YSR5M6(erejZzk~MK`n>
zeXTkPB~03M&%F#I?YcEhuzW{%`*-wp=<ZGd>C`2Bj-htx^5%nd>r%f5>Cu@f)zGVp
zJPU<B-Q7_P>aK33ov!wKI@1!6e%<O%Kn8T7zhWGNIx`(<7}5#ph4MgmWdr(#b!#a1
zG@`4xiP;#{b!LN%>8k0K_gMD}J(<UKoDCS`6Ww1Fv7FE~Qt)|FC;kpzIO-cVqHmu*
z>sy$2(*K=7OHOCK8+ox`AMOWH7yW`IXgr`#r;-O({f}h;J*ek~qt8vx{1C3W>j%a$
z2_E`g(_!L}{`gvOhxNrbpm#)nZW!2}`gGbQ9o0XgVxMFBvlKe_()Usn)?5GgchEbo
zKc7e^wSDxfAA|MP%X{F3pFW!leSdu}9Z)!-FQ7DUfIg8H+=2Qn^qrv~{b!$J5`*=t
z<^%hremm7!hv+|k9tK18O|wBx>A$77afH5@f{ds2+n2-pNWF%_KT-OhKLkp&J`)cm
zyF-kA6I}vl^f|A?{8{}|6abCYFFgk?P9Jj_BwqgpZ6cEO-l4FYqJR2FICEbAMKiby
z`ns8LG*z!xLoZE#u?&6b`mbn%e^LKxD4;LtHQ6wDS-*!aj|}}x6TmX{eERx;JxhOh
z4?45;_mVM~9Q~4FfadB2DooTBeYz_|^Yjx^kbJ$Q2PO*i%SoY7Uq2uEMf$@{@UU2a
z>m*2to=NAnuj-G{6<DedE(Lc@A6W;5GX4DoxK^%@r25?oy?H%m?Ydn*?<L4o>i7N+
zY?WU65*)79e@;os8htP=OKbI|o*;GlcWBpNulMeNr5pN9ETG-g?}!6;OaJmgICES7
z@edewgWjDk=SDrwmf$whmn6VKv;KVz`daiue4w=I7jJ<`o8BJrG<<8<ze&N8JNhqP
zgG`5h&+}01)bH5{(JsB$MR47ENfaibM{ipLg<kz)1|<9R8Q%ituKtB|jOm_UN$-b#
z{W3ZxIG`8JLgRh?-*><b>i^h}86DF9aRp!x^pjH|`B2|xe;<B7(mT*DZCIa88^|&J
zo@#K9^_8?J7}vMbp6!V~`6AFJ^s7)3<1ne8_c1^n4P9r^xX;i*r!|}msUN^YXTxer
z7VkIANeAbG?@og|V2J+-Zo3*<ogjJ8u!<6nZib!Nl-Y4NESUw?!?2?l8ix!`Ujh5D
zVIf^DM+{%lw{biTY1`q&QG@t4JUnJ_p-8xwA*LP9cpDCSK=Qc3F$N>_F>L>@K+Mn`
z1W7-`>OxrXH&o8TkWLtw#V{0LxUvwE!G>qQrI1Ug;XSIM2s7+{6L!N5<rTm_Wyq(8
zNrWMf%Armh?gxWJ8s4FYUzFi{Dy)e%G(Uui7{i9yP(Nch<Op)sut*Mn&ly_i_Kh{T
zXTj|_!#7I+7H_Z|gL;DD&^=g4G_0AJg8MJYu$w*%mTZ`E9WJIA94VuF-msM3{}&AU
zSJ9Yi*g;o!nqh?MB+?D9cEIjM!}u=vd&!W^g~DY+%K&`JFuX<)(@aCs3g~4SVq4Id
zZ8%4v=o~}Gn`q26cu=wU6@!H89PD|93tF`18ys!{w7{_G6Zl<dXp_R>BExqg$P^oz
zKY)IT!8!pit{PsIV4$UjEt?>6%`iYY>oS9$c01(;ClyGA;h(K=?Yd!TH(aYUbh$vG
z%J4dcL8}ebD}YjCK)Mq5mfi4<AMDl{*mV4~-f)6WYuqr*I}iPvhI606(_4nUThZ5S
zs96Amt%mO?n$%|49)-Sk!*;rl?ihB`!H5n+`7<!lX)w})u*>kG6(j35v{6xFkKs8h
zBnJ$ei{bB}A%-seA%p$GFf<+*7G^<z*zo5Wm>4m9{U&@HHLT~s?=izdGXL1neF!4s
zhD*cXo)}!C(KlgunikiS248w+I~p(2l<YGW*}yp&2PiJ#Yz(GV#D3$vCm528F|iO{
z95DK~gSZ-5c3RIKG=4oF4!aq*(?-MHxY&rHc^ETK1N)FMf$DY+8@njuaKz{^1qz<V
zSE;(>sBztAXgp@DdII8QJWUsbw{Z*Qevcd7`_brQoIzV5U*on#7_XnvsDU&7#=mW_
zaKczJjsDA2fH8}P7HCY{2B(6Ixp6QUY@DRpoRh|mJFpaDygLfTP~+U+&=_VE`GSNS
zSNx8~Q^xZD_8Z1$E#OWYjq#Y#NF%2c2BVB^&!aKgc+3pw7~^cJ5<g=s*#UCaSo1#J
zf9H&&u5dWk*eQWiamF#ax8se~V)&F`yc`7mMB~2}G$t9}ptWDJag<80QjAsS(Rbds
zOpm?`#&4_8muie1hhCa7{8M<5ZnPDGyJ&R(9g}d$_%lVQGL4_E1<5j|VFzY+$Tp5i
z0Fz_fMN^Y&tZ>EXuNd#1f=r%KLmTFN<K!>sD=^MJj!_gE51xZak#Ul;D8<HCpF?Ab
zamOBban-nTBZgLLjHbf-YsQ6C*j;9Pi3xwpjhvN`tT1YcyKeNE2@ma+MwT;tt1^0r
zfUPzje-9cp#!xEVsx<~Q1E$WniOLS@jlG}3;0@zH$I*AwxZ@&VZW-6p@r>KXmuSh>
zU<~{neT~Nct(c1@<HHt+G#jUU4v`k)raS0sHHs<I(PmtA8TQ)k#^N+!cN%Mz@U6?Z
zV<}|1jgq<O?7<~~N$54Iskpb#XrgT7UE}QufZj9i`wSxe##Y)24H);*v8?;Xm;MAd
zXuP=@l0(LjrNDe(Ja7u?4~@+fvv_0-c!CKUHhxkFlo6x-fAb+aYMe_I|6|5J3OheG
zKK~&^$BkXd0DWRqj=_rwWB+H6oHX`1!+l4S#~d{7Gku?gMkmt*y^fqs&%^_Jzlps9
zU@oS}exMvM`Fp|(SJSRAG#)hVz7FDMlKu-r?xwYNN)LFLE>o!XkSWt2Fo#XeRK0M-
z<Vck|o+i#X3?4PDq(gDXOx_eA@G_mG$`x<Z%T%a$+;r?Qei$E9vjlp+riAIh^fxt}
zf%*y41|G}@m@d+SCeU<{wwghv9qAy!rpg!Xn3|I&*0<;kF^y+IBh)0M1Z|ipu@a5p
zrv0=lJ!Q%&L}P?$Q9Be)o1UZmQl#lQDt?GE#nR^@qD@6qRTg7<K+n!|CO<js#+u%y
zG-90TuPFE%Z*pD%kp$B>Gtrl5>MEntl}V-zR0)}EIvNI<6w^1PpK4m<1;sRzDglE@
zH+|oXfnGKR(ta|-^kN=d%QWp@h`ub-Cv+iao8F+1WsYe*&0(&|PGQ(9CRrBx@=Ws<
zK`-BQzyOf~Q^!t_LX#?vPL~v!rY}Tiv1!%25G^r<Qc1&AQ#X~fl$x$|!R|HF5H0Y_
zOi=~k%1wt?L9)WM?``N^Hwoz7T4|C{psLE`K_S{|Q}-aa8q+I#F<rH$Fv@_{nLH_0
zS#Nr02f%Ka4!D4`-!%Q42bo)@E)B?S(<~?W)?ngL1xlldH3qaM6PJoTnoZ}aXtBj4
z{RX7fG&2;9ZKe_tX06>6^asct(~*Cn&|zw$6mq92oN|&~rf2ZfcIY;B()+8&6uc6W
zy{3%=;QH*QxL?5DHQ93@de5|W21vi@kq(nMV6uJ=a^Iw&C(NL!n1NvrnR?!V`wvY0
z6u5n8`juWFk4(XoL>e}Y{0_S#Cg&fZH);x}fZ&+vtA8=F$0pMz^o^T#NP+Ui6q^Zd
z!eno!E!U(eXCu6EGzZ@WnzMPwZ7A+HuS*4SG4J^i`UlK6zlNl%*?9`cL30DW&fLs%
zC`03JuBUCVhj|M<*$$caT*b^BHp|z*rz7T`7t!cxzCeqtqh_BeAjix@R6pirF1FJV
zA8+$4N~0V%fBq_9e9XBNv-CC3`U#f&%!lY%<Zt$&jN=J&rzf}oGlL>Of#ywqXbdtJ
zJOjO8a~tinPny4_do#rBqJ~JQ`S%crgqfeBjbFIAYdSDbndiB|e1!RNA?^Q8n>XAA
zXr%dfO5a48SI|->+Pq;L8Zl<ABl^yne@=u(tT}%th8<@<PjS9@^CDUmCYYU$LnP50
z{4UHVnZJvIiDYwQ4Y(BZKd)mFE|{lK)kCWJFGskRW}d2nUb>n61^t(|i{@3$(7$Ys
zdkL)>W-fi9A=7*zALg^nXTCsRwz-p1*E#0n6o1Myt2RL--~4A0Knu+8Q;M?CJP`=4
z$ov--c@>*KeFvn(Je_XXtL6{P@VC^={vSqm%{==Q)XU7Ct0?7AZZ6?MvBK<0_rZ1Z
z`>#Ty(#+_Aew8_cf~?i%g$>ZJF}u^T^IG$6`jAbX`3Fi-)|<Ef0q%zRds=1PGzSX+
zcFX*N7~F01PuJmZgLy6`dK%6BtI*hF9-acO+1%$0L-rQ)^H#{TnHNn3OuJdU2c*+{
zD*@PDW@9b9=r(^<3XL9f4DDNc%~A?T_L*BL@p#u<_b#}5=CDTS^_$g{dK)m`r&!#5
z^EiE(Y|!j=4`2_?#c2?EWR}w*gkdv73^HOj7cPbVsQDgE!kF3F1;4>#bNR2Bi*a)@
z)rCAU%Rh$VgjwniM<>nuD8}SyVT^z{S%zl8ptI%cE-37`tep#=TrBdRp>V)*htAKq
zT4VvRaMZHR0CLRIPX%vYmZ9ws@wV8P=D^@_%am&{?_-Hr3Q&KGJRglGENuhO53sDJ
zj7Om5ml;qDvP`arWUyt;E8tFAc$Cc#u_!m9G1Rh*a*Sb?^|TfUw+!}yJ7sx=N^v7B
zLrK6qZHXU1W29v{1^p5%lXlA7CtBWr116F!zuv)MQY>9`BICRzloJ0JELSMxk!tyH
z0Z5wVTLmQ3EpN;R=tYZb4@PmxvV<aJmo0IJA(CMkr~+oD<qH`^vMf9b^JQChP~lmQ
z<!y?}=31uE^5%-=_Dw9o9P%u4C_0;Oai^t7f#pqF4i;K0kKkgFCI1a@#g@NH(N|*W
zIt=}*7UmW7m0HTZVE3A(U=Fa$EMHP)x7_mUY$#M%{!6A@w}{EnO3UIY@S@7%OAp;@
zi>Vp*YAiwTQDtqd#e>o)b(Xdd&{=P}M4O!(7JsTvxoN4GfyP^wJG5<Xw1m^@uF3Ko
z)&4eH!YG8;VzHmbbhTPsyy04#W&S*ncFUR~G~Thq9)~j>7Pd1QJ1x0hn3*n%nD*D*
zmcw|?;B=+MUyROP%d!V(?X%3K5|FzVHI*>lvz)sOgZ-9-m*LES<qoAW?^{yVfE%=g
zEW_0~WbyPt;{(gz-B5pMSr-kxN0v&;RSaAF=p(Kp7AFS07`60L@z9uM{|yZHu_aRm
zN&C3vb5EFmV)<|`Iwvf-w1=3q_)*D;qqUI<hxb`yL%=y%-3~&;+4|!?SlVyxpv;Gh
zHI&Lq4p>)jz+AXm=bc5PyS2O<gYd8hb;657){*VdJ8T_}gWeJA&!-{jX?38i?@_yT
zPbv%^vobj#Ue+bFf%CSO{0xob*7Y(p`dAkZLDAQmKxOuRR?$qD@V9<MH4P`MZR;_Z
z0Bchr6auX^AAtl}BPo#<Yz?GZm6O&3A3!q1%FIS%sMYVkWVJP#%ACTj_9-l&ow6#j
zpcrBOVJc)!TR-T=m?EvqvSByMYNnJ&wDt0Nh{RZbr3ld(>kB&|a@Kl4fW~vytrT^S
zwQA|pLUGouuffrH>!k~TPOxse3iFB963SX7S-<o}W3p96OQ00%RQpxX^VWXK^jxqG
z(FP&a`VIZlf;8)^BWO&weou`Tt?QnJYnQC=Q~khYYv&HQmSJ6R9F{VzIX28%mh}LI
zI<u`W(3Ip@L+IdVuJ!FVVE&5r94&wItPAMfm~Y)P11JU7=f0=PzC!E#<-jhoe(*K8
zVykmDL`$r{Ujo`y>rWbBms%xs^y->bNQ>zT>sU9qD(kGHFi~w?LiIZ});W|6s<l?~
zVX)5nJDu^Yw|Y^Y_l9)=<rZ&RRf8~p%R2uMEZnx<<35A?ufh8J1SYZ3>i+;TP1c$8
zFln|r(J{pqtA`I@TCG7ofN8TnMS;_HtAwHicdQS$0IkEipJukxy8d-|(PbT?^>Vj0
zWGfVUtaHwT^jeM2gY;RSz5oyJS{>4Wa?iS;j^dyF)^o>UaKO6B1WWg=r7IybXsv$@
zE)H2k=&|#_8qfes53Tk);2v2=DTY04opKkTBi3mYksh_iGtoC@RlW@KkF5tNj5%(7
zc{xy?SYs%pG+`BWLSfSCK|54O+mvS^Y2Rn-?1kS>wihYB?P3dE0N)PSeq0ISYCE_E
z8V7C1TG8ibyG^l1ciT}V8V}n}PleqhwmlSi^t637i9Rpe?{vv~+u|01J8tX$1~cko
z3%dv~Ut8i_Nc!38a?uxHdzqHMfp(kkOXv);6?OqM*yc;&l#@0uszL~{RecDJP}^qO
zUxe8Nw44mL)lgOSDcfswZ${WE|EtKg1sWg{Y1=_%%~7@xO4Uc(u5SWLjIC=uB+uBy
zRt)>Bt%#nT=WLrlg!i#F`&%>cu8OmLK=)X@O-QMR1lwCrp)t|sy%cCkw(qGlJ=tc;
zhhmDYg?2~hZ4U3@D!X9ouZ5*l8<*aqX|_xXP^H^EwnOBiZLcH1F4@8;W`5ZgP3yo6
zTX_b?nQ0TuM`M=lE&DJuvTZZQL2_(2qd{_Q92>|L+kSeO<k>nX|DSIQJdMTz+p<15
zT4?)Y3dU4q%cDqZv26#vPfBcYUxQq=P0+Km)Mli}(ly&UDqbqHN$7Scw~bNgufpa)
zU){WJWA@YiS83apiOwpU$6lDIwguHdvBp+ZgQ3;h%45-3XRCDpS8v<gfW8~Hg96Ou
zP1|pMP`_mh?tsDDw#Ki~*kJqNDBNzgU7=NBi>+clJZ!ZMGojb^e~zv@F3akRmuA|q
z%*x8PWtN$hW<$+P(}tFn@7{awmv;6dDzcOzOE!YY5<!Ln0t&K3WC;SIAfPM-St7E2
z-}C$HeD1mDd(OGf`#kr#_ndQ|cV{96raO0z(%$ao&MR&7{N395#8bE!T|2MPmvFjw
zYDjm_&i8LXP4CWYVNlbzbDUN*w|7Q;3~hII{%C`?{+)tMXdBqMD;3PUJKv<};^0mL
zAI=Qze60p#c<1L-urso=pd78yohztN;oeRWCF{m^KK&{EpUM55YsxVC@tu8CmiAz0
zj|K)OcAmTk;N;E|{ScknX`-8TdgpWk`et@sptX-P<N6%<w3~5>PT9CH_EKVP4<m*)
zBzqZFngjPSv@@{l%J@zKW&0UDgHYzi=%O3RoniR~0EY+THhs&*li{@jon8z+Ma>Q{
zMkqjbkl~1h32#Q^V-WFSO!Q!&zKn0<(DGya@d_**Vkjua;?Ecj0103uJdD0T#!JnR
z3}TE>DQ+;sT@Pn)+=6xsA&hP+nh#|J(%Gai2V*V0RKppIH=`NBFx^8dlCkm!I1|NK
z+5~1a<01MU>Ji3`Sg46%?4m?q9HWe)8^;)#^C20}*has05~DO5eaQ?pop(IW*hh0<
zDuYRH_B2LyB3wJk@S@0YI%7R;G&2~E`81_vGJfrW`==QX=7D50covWx#z89f%4JAt
z4{(ODc|FFP$M};LfccD4Dnuz@oc({fEki-`>p6xO3(gcWUZDVf5##i;kUY=mkA$*f
zMi=dKOBkoA?yi(EM)e(Kj9^C?I?EZi9|5_*I9LUI1tY)?a*^?g2FyyvMJnaJ#8@*2
z%qm7W8+NN1m4g_44P(wN*sW#!xELd>V|;9dqn8;2^aZMV#x@G5H89pugy#z5vA@vQ
z$Vi_8vx!l#1%PJ8BfSoEUS%wy<y8x#=`4WP7-^JezRq}?YA#zDX>?z;F`kG+Uk76*
z8}4^9w$QurCL{e_D80o<{uQK)u{9AMb~E0k-BAzYya>!*MkM*v$7rFX;B7|HQnc<c
zGQ2?g89%;A|5h@<kZ%LxE`v*7eHvuEcMNui7+=#l+hNA6A0RryI6&!-QAR!;HM+<6
zneNUp#$yx;yU&Oh0Y1)nCIXTV7=BcVKf!3<jhlRu5&8tk6hr<iR8KPwQC-$<W-jG|
zU6`M=(fV@_Gxsa#c4dyv25>*q?>i`UV>%xN!kxMKW9ar^x>6$Flld4$w!D~oXkl}J
zxkU?+gUpZxAl}R?^kF9-=6jU*^JUtWqUFb|`3FDqA?AY+sP<>hr`2Qt)2AEoK;|Py
z!E^*Mj|YGTGeggUdzhK50|{ZSe-zAc=GC8IK7u(K4yBRIArDxJV!lj!v}oo6inttM
zdM?EXW0(vlco@rM(%Igl%zz?@#4&r`!$6NQw^3nmJX2K(EeXsORDYewtXTzkl7kr@
z37X7opk?TB<`)|vlft}9NrDs1X{vuqWuBslbQ-ghVml|9MW|hwlg=!mC_x7EAxdav
zGWX;Hm&Ke*Q_?Bs>4k9SH1m8qnAyyDFTit{T@+o<WzI4IcZOL!A7=BIj(rJ`$!Dev
zz~KUBDD4c+GJml^<{Wc=ESQDN;xLdRrhY%voM*nW5TuydO&h-wW{numlrmi^(JEtp
za}~<UnUg)xeSxW>6ULRyrzxac&D>lDoi)tozkr9e%nh^(u47sq7630ZZCseBXLeb^
zZD4lO^}520dmqe3X2S&hZerF_UaN%}OHbT2X7?71@H+Ev%B;3BlivZejk%Bl7&n-^
z(;(T-+-QJE2Q!HhXr0WaY5XuZnZ<N)wwt-?Gqie`=>hcq>t#MeKl2^t*3}^W%oE{o
zc!2q92nI96+(0LzhnYcdf{ZZzH$r5L8AC^_?lV7F2sPu(Ns1{=GEdNF<))ZVJq^ie
z<|lh#X*WxvMV|}H7!POmu$t&Yz^<&PXfeB=^?MkdEOBF<O-9p`^)&5;y;$pJp>=@u
z+d`=EVY!}w8edlTG8pt@-Cl&g09FH49R{*qcn7+JScn4SmSy>Sz(go(;wijE!&om+
zIa?&ljmq<*STF4YAezM%Kr)uKfKty#S@B3<JLbf(lApvV5?J32;pa+ZUHcOxiS-E;
z;ij<i9>ujd!HPTr*HT%h{oqqN>rpTGl)-wEX7Wtd#~T1R%_^p0XR|n;f#k3}sEj9%
zmH7XyIBPMLOBJxT6~LK7)`l#oE@B;~f-uK<)~~eWD`gc>c)g4@`v{yVXKkVk*hN+=
zodl?71qA}wz<Qo$`75kM+QKxlo}|re6N^u$0b5vWd9Ztp)k)#5>#Y1F09silN|dy*
zO238q8?5m`kam_m0i=WV5Un9P9jwobfWOHq_k#IbtO_5rx>#kD*Xm)_H=xzave+To
z$6EI*?A~V0ae~r2tbwB#_5iE)LyY1si%$g|gRHJb=pJIdLi^5P)@`a*9AVx17`QQ(
z>UWU)tmpAi&lzWVhXX#zaztlCbc$s|%6-l>>j<qXo!Kw90l1s(OaTQK_Qy6L_OPSB
zM&Dj`-7grnEB=TMBKz6rn_$q5{nB?J?(DTWQ0BqT{~2TPWIItT%8MO!82%n$FMA*G
zgY5VBL8mu+hN^*l*n1s6zztvaziS}l$IjjYONZDxA%Onuk|)3nU?<MNwLtcTbFdr4
z{>lat%>J3OpNHAAR--S3{edea!`WeU&qS~{bisTidov|Nj<Bs1evM(DdmXq~_IvB#
z=rQ(@9WWHnmY;H<Gl9L}Ahad3k39}&j<Y9MV`wStq^(es#*Y38exGDt&P883`(H}3
zWwF1V0PYlf{*O>|n*B4)KDq2WRGxW;9TN{g9{c$_5IM_!gyM4N*gQF$DP;ddVToe)
z$~34hVgLElLwNp5+57q+TE^}hf*0lN{-=Prz>c8jw}P$z9ojCkjSmA+$<9rJrAzF_
z_aRcnzPtt6s@Yv)cu~u?(w4Z6ot*?PF0;R*iimo)?LCkN_P1O}USYqb0j`mq?F-3f
zwg+O2jyYG^d!7Kkg}vlAcyW#WQ5Ni8XNOZjua&)>_G)cxC8aNKuq(I1nRYh&5=?Zk
z-D#reWN)VN-egAxfONBGQ*^$E?Jb3gUUrlk!@k2Vqt$ain@@{?0ruNZ!opqlr?e_`
z46^6Zi)e`b6O}6svp@L=G9&DWXJBHKeVq&DJ@zl}LCqN3N@3&s>}F4padyFP7}Eo`
zk&bIluva|+yOZo|bD?aC{d5^zn`ZBg0GVOeeTR`bbD~Wc#BNT|T@V+}A2dPjad6Tp
zS+<w6jkXf|I2Wk$#Fg{va&+$JgfD_pH_klzecU-C|A2UKSlc1#$tj6}8ZXX2zr%|I
z96P1&4|4vZx0*L6JsN#JoQ5{I=F53?35Xwu{V*oRL!3XmAmY#Yssw-lj-!CeSpqqi
zlA$JubDfGOgE?JP4Re?ix&jv}gmbq7c0)POAA*`NPAk<+hjSJk$CZiTWa&U6ITz@;
zjpD@9Vee?p?jJCSBb+OLLT3yonRd3Z98nSaj&dqap%uqb(RVtJappVL!bChLf~Ktm
z&VD7XdLpO%cNk3KTz?hJWX_c_FpqO`Hv*r+`JK*Ep5UyfBeSWT0eaD=aon~-%Sq08
zN{ys*<h13=;8+vTcZy@g_xR_W=1fqnbvDPA1(6)i2`Yxm<#<=o8uJWiiagEZoPQL$
z^Er)ly$U!IdhpJ2_EJUvInHO4qA%nW(|)&z^EU0J&vPtKLZq1EaRFLNI61?BmvUMz
z!h9L$D#e7#IY$>l*#*wyYk{lasOUv-kyEo1l9ilm>Gb?v;^^o^b`_`G0?}&D9VwL7
za1=*?sO1FFPg%zia&Rp!bH1T{SUu;~O)wic%PHY_h4aJ{Xf<+Lw?U+d(@)o_nX{IT
zmtN&8d>D?la6*5B!E2n^l)P!<IGiDJgX8uceOaKLBR>k64o=xLWI8#8xiE2)bFT!<
zTbwk?*K~1yrzl-FXZAAm^>8ZxM5~t*lLpeq+50`1w>c@4M!&=PbPl}e=e$UX^8rqR
zGql|0bbN{-4RUnHAUVV-(ZlUwjx%LO9V48qa*TeIvnU9@-Q)Os12M)Cj==7Hj^{nJ
z#yJAYr9R+fQsL_a$GQuaCOLy9;HEfHTqvF9@V*3@;S?7@#F;zvBMk25G9%%P3-?L-
z(f4qNlmP7IE`A>Hecb7dQ0?mAZl+Hm?C1X72dCV)-L$rK=iaAD%!6w+1MkT#YX;tn
z%P0oo0QZe7SUSl4g^C8fxtTwJ>BEgMV7$KE=?MV*xO3;Db%@)v8AI~t4&^{3fV<^e
z=nUlk!UsHv+eF*lV6NlIEO>gD%cLTr5bkTg!NpMSqx2huaeohkiEyqDRW?L$KcLu7
zB=<?G>51YFQCW91_l!G~9^s~N(2C(6py?`>>$C{uD3=)l6LH*XDnmQQt$H6Mk$XlA
z3rXA`7_gAc?Q_t_s!ni+UdFIfxz(%Sa2ogN8IaRl)p^L|avxg>HD|ablxWH0zEJ{_
z&)r2^i308=>O0H*Y9o}M<Gw*L<U;N*bmp{(Tj~r_%$-N&ZzbF-b?~s1yEYy0GH&AY
zV3u=hM`-<df!imB`HS4M3ow{UuFM%Dyu?lFg83@0+dcGEb6>51`!!s-2S_b<7v(nU
zxb{E{^fEWcAIy5LZaYjgaE~7b;0pKaV3=s+4!jG4P27SHp{$v^`w053a-XE<uZ8<u
zGZg_}<KFE;^E#JDm2$1z&uG2S#@&I}|C}4#1r&pB=f+QhbZ|eTIB_SpjefM7+_|)L
zy2af>yU8vtHwL(F?iYt4*~8WCK<hU5ues29hr8h<B>TCmIza}wtUS1Om%9zIXUCjD
z?$8Su_7HbNHW0(y=!HOxaM%3=<|y~aS}^Z%yYxVeam$v$r~BL`ThJQk26kd-54cA*
z0WiVMcn8c$Zu}6KQ``?jU}>7GJp?ktJxy?D-VOo0-@|L)2!HqT2ApBRv5)7Vx40{B
z>UDJP=f%;#hP&~ep^^l5-rV^R_24c29zU}u@9Y<_<i$HjIh6yva7suW<fUx~&YSlJ
zJ?TEY-Uk5q@|L{?xF2up6963I&2EFFKkox7i4EY{{)9*%FO?pSAP4Vlic19ZE^G$k
zFmF9=Q$l#t=};QVOI?q?Fy8KH;KO-BirGi;N~z#2npZ+^kR!aB0cbnQtD{23INmxj
zOdR9wq#~0<o?iw;l6d8I;F5VW15kZ}H@h9oRNfdJR!HMHF421|gJ+}#b0%++7R*_^
z+^1pUH1EWlAlbZE-UL2}m&<~QT;A`rO*q3__6^kJ^J-V4uYmU^rH9Y*ay1x4A@AWa
z_*=xw-U^-Pc^3M4i+QCVfmy=4M!!}WFQyNza$ZHyi(7FLCy}cCF7cdcrCG(B%Y&9`
zUKu3=Yk3Rl@Jt<V$`>QM%wth1wVsz>gjNGjMp54@yi5j|&AetY09SeI>2OgC@6Az&
zT;sKqq3gUWo*=Ef?tB2+coP-)J#X+Hc?BbC=e_Kp8N8P_kJf5^JkLIm+q@_Le@KEi
zYZkok=lw=I@w+^iXW`l)FXa`qhIj>4=o{fF(g7diMR}p`KJNj&i^qB46kmS8`>zRo
z6TG`r#x=>Cpk4YD@5a+GKh1mVL-;$xvuvlAurq&*?ylYZ)gJ@l!jD&?<;uTBFQxtb
zY5|yT{1-Ez)SWM*P?QIMaU|W9{9h<*>BT>m4Zs2Zs}v+Z$j{BhML5L&{5=qV{%>z!
zpaJ~<sGdHMA4uuhAb!U<bO!TlIv!Kw&f|YZJBbkfLCT?q^5bZy7{%W}i<W5q;Y}b%
z_&yaFMGXHxT7bp!gRemMQN9l?d*k?mn=o;V|EU2ap5NOIOUL;<N~NUm*HP-|1b=_f
zg75HSKcJIy>HM&2NM`Ws`=KS1f9M%lIL#L>gtBb@%2z;g_{9b2%jKv23`fuKFK@#*
z^Y~>9F!TAp9D+yz-=B^noaHBXL)kh0$CUgp<UjKs`igMvz%1kIDFj^37dQcafj{mz
zhXGdbU0=cgFY+z)w@Q`#hiUG)#D9Wn532aj)7zk$|8gs|)$^;UYM_Dt2t|#q@K@1F
zuaRFx2Naw5?vy=f=G&<x?JED7UW~Ja|4Az>T;p%0Y*;&gls01>{KCsn*2(V)q8a}t
zKeG|!7GK2$>EioRWn4GkOAFG&Z>AJ^FMon^`2+kL#JtPD=?UF~{LjvTImG{n0&v6p
z!g07g!e32m*in8URpsB~zfXJSF@6A@(0IU~S%}sIf2;^TP4Zv-mR4L-{7<$)+caOX
z1~N1Ji<C`s7PwGQa<{-rX-*eG&btuVBaq3Vd#|9I63F`mwN!%VA$TVlEl<HdN<euD
zmeU^cfZ$Jx8y*z2j>Dk0U<XZaK7#rb`0Fc39mcir6WsrnzGV?4`1A~b!GfzaKOGhn
zoPf3v!Rja=LIs5s&<YcbxWcD!!TbLLA0b$wfr&^#)lQ5eRuDn=+ED?E?zK3<<2}F~
z6I`UoTfE?-4!{!x8FY*<QQ-FgT9O0@{su`F{6I$w9BG1nI(L6kP!JD?(*@ioz|9b3
z4MBIN;Dtpnm?hXj!HH9X0y_10TJZcq=*||Ha$)d{ATA&9JVD0@TKR&1Xzg4eP}5<N
zvx3^waP*wudIXde3K-wOLXjYI707u($^{I!*dch268t5CQx(u%DtLsV%ohbLE0~pn
zXK9sjN$~7q;Hv~9W>~5g{CXLdY6J~00Z=Q@{0<X!g5e4%Z4^Y&8?H&9^@d2Zpp7CG
zR|UVwA=x4b(P9wS1m8`f@4BFQD{!p>M*}6}I|W4v(0x;|*azHOg5p%V5d}$WK)MCH
z^Psdx@HVY7dId`_0^cV%LFKh~1<h0&GAIb6dwob?TLABe1?8JyX+-b{2X;pV;{EXA
zo}hqM31b37BeXma*eSj<Auu_<0-Y4(QT$>`;6stSX+ft1YGwotv_sr4EDnJQH=*lE
z;N68e^U&uZ%sBvqp2GY-z`cb0e<5-}nBoV!2Zg2%NO}wZI}S@e!tz$Me1+>MD(5F$
zL}ieNgnKjKn!j*S&lUg!gxM+R3=$5VgwkMPcQDi(76y94?+{_^@4$x&m+b`!7fw)d
zafI+qDqD*bGT(t@v@koUZ9As2gS4GFDqQe7NW3ufBS<C)Q|94LNEGJMn><NaYlD_#
zp)Cry<H8zRjim@rjl+o(!q0DlqzWHd4!2JV8)y-jE_|8F8Zv})RsfeN{F^rSS;BoE
zgPam(%)skx;k@4<k|W&haDm-iVQVOKpAm-YpgT`Ez5~}VU#R^77q&pCx&@!k3cXs;
zcTRYd&Yl$t3xjY)i-eo0BJRAfo9eELg=gsoE)lMy?Ov(yJ31>@CiJJ^X}K`w6yO(x
z;S_hT5c&^5<f3r;A{DPy3YV;f`<H}!XaQ3tEO`{#s)aw%4^t;pcfiDD;dM&n)C;#z
z(NBYLhd)|ZgilbasZsbIotbVH#v&O$=c>@rkAb!bkI}a6nsD_8FnC?~*B2nI!dzPW
z-VpvrJEV4D_6Kx$sYCcuADTCXA4WslEn%}5_%2~iGMwoax<7#K9${i0`g(<PsZ6d<
zxaA9o+!6ZIBi1i$?!sUOgiC0ix+_efiDFP_-wlyrVGFH&M})<%gNzD4&49=~q2(3W
z8x!{7r$_Qo`1Sj^2oplbIshkygZ}|ICA`uAGA&$12Uur>c|O29i{w;8x?2=Zb-XU3
z^;DF+M-)i`;k}|Ndd2M%y^(}ISJ5k7=-V$kK=s{jqE@>2?xII1Lg*oyN5NB1(I@Yr
z<?s@P?ZBluAUZn^;6c$C<>|dev6Mgd5$!qxyS}1z8$kR-r&UmMNECPw{`!m3=xag&
zq91m^M4%{+4ig567OVv`SoDqoBRnj+Ku4KEM6;`5AygDeb@X8(CIx-MMfG2TL^wom
zc>x$HI{yEasfhPI5YeI)$6(@!Xf_Y67!m$;7<0DhYr0pDiWYI;Xq?E0!pg@)&(nd>
zM3H$ZOeBfQ>9w0IT1pj%$3@rapK($|TWIfkLR9oNBvVD@bfO|nq(2NTCq)h=E#T5c
zH=l;?4ABBEL^DN~CefKCI@OH9oD!|2^1Rcc$0==|E&A3Cmn}!+I|*&MqVIly!84+c
zK4{4kjat!{FFJkzk_Do-4#WIe5u1Lyb0Rx^|F=-|5*<k>60N6dwezA69NzG>SoBm1
zL`y`wvcN4BrO{d9GEvie@S<F_W(Iv1MAbBRR)|*741Q7MwGkqfqEl;NzFKr+BS?)X
zbv?YV6)mBEv#1mOGaux#XfCB!>P7X9APpi5Wl*n(xHB-+C~E%E0huPz?nl9G7Oh;2
zOL|qbhH?olqVbhLToZNDB!69$_yB&lidMgi!L*4E(2MqlsC+%(?IOJo03D)>l<w;k
zX%gY~O;JQ3n72gF&4FZ>NO}o<y`nX_X!VJBR1tGq6!i@ikKPfz<O-$zqWkm$x+}77
zh0;OMRf>WPiK=L?J}mNm3iuJxulJ#QRHXYHYQ{w71(<K{i)KFs564BDrf?A+hz?Rv
zVM6rq-(XIPYS+VyY0+v*L(PbWDQ4^}J{bh!A~ve%`P(Dj^BtOd#iQE*+$V0PGit8l
z)f5|a6E{_ZxQhp<2-HLTBLzx4#k;6X$4k75j?Wzs|9uK@Z*j`A!1;)u{2m5<#a)ZQ
z^b`N}JOGEpS#)>#i`P?FDo~tGk)R-P)MDs#1dE-i!X-=`PaDK=aS?stJVIQP14N{F
z4ebP?#HT0}bVR&{cCs<zTiwtdD{iQQwxi-ET0zB$1De4+CeHN$JYJklZ=*!9ieAD=
zV%I8YNftjzOTFXb!ROJJB3>N}c&bDE-}AtyiDRCFrzgd(bc!cke4DDTGsHy}T#`(2
zGHuJV#LrUEc((Wj+85`DV}6C(x#IV31Aa!_wH|i!#2m^x6o|DyVk~FHZOcH;iOcqZ
zStw3g27^W7#V<kid2vrA`bxx(`ShrkiaWW$mx(u1Dx+LHN!6+s#Fdm9s1Uo_fv*(*
zK&2^{#HXn$ze>Eq8?74ga+>vO#lcU)?K<)9*|;Gti?96(c)gfK6)IQ6FEwDijpE-Q
z0cjGq5NQ@Kp&i~;@f`={DO$wYB6xFMT+#yFt>WX@s?BK=ze!=O8{&gB6Ss>Wry{Zr
z@hBw-Z;Bs#1AtrN&o{z+m)M;`ZGB>&t-#$De>E2)yd(Bh!Ha(J!WVH32gHANf;lLT
zDuS{halw0N4T}qn4$u*CSP0aNifi1^x+l)3wc422Kmo^banM=}^ntjKzC|-3&VL_d
zQoJP)%qek90RS`Nz2CqmXNhYoJlrjLb|buSkrYsE#~w*v8pgX<BBBBAlax}X*iCXI
z4i?-cUj<X~sE6bgT4#7lF02Oek`&Ue_kiT?C}a*wzNFJ|-ja7-!zg?t%PBMOEBUMr
zuK7tGqlxj5<l-IZ_LnqQLNY+|f)84Ol5Z(s5hQV+4H7Jgx(&OBC4W+_QHW&cAch+%
zIr<v?H9(l;hi){(CGq<)rU=RW&tW1`a$*$_QIek{(HAYrJ%qj^lBM+Cjgefc1&Nhp
zQ7P$B$?vq}ij%CNB9>#4*!N)~UK05S011+dZ^6+-N$HpHK1p(gO0$wBf79cCT;hBH
zEk}yvLt0CmkYrNcI#n`03u@9ND|P~LQu1FQTIrJVbr8*vJo7WOosx7!0B~9|Du;<|
z$tP5+dq(mCB}VcjOWe`Qm)xh;If*+}Iu=T_RCiS*X`n@Pi9|uK&r(S~?QhE*k`Jgd
zrb5#81}t5aMAL_LDkVSB3b$HPxeBcsiJKMpTFH0~u1vjze*$V6Bs=LPb46ld1Kupz
z;17|jl0V-DX^~9Ob!wF?r!01x<de-%c0;lVx!O7Hl7A_6(;-QqlN_BA$D6dsyD52-
z%1>@d3RhrgU6SessOgrhoeL8^lF!aVq))P(@*B4$>GVaMJCcP4sOgsot@sTFB=hK%
zF(}FW1Gpi{!k1xbSn|gU&^aQB-2|PZ5>-E(xhE<A2Yq9b$9{ye`x1Z07I4QUj?<8N
zAaVDGQxlS&b|{^cJhB3orX)_WP&zH))3Ku&Nrf}r>(akGV1BoB#dc_Ok-pvsk$uvi
zVqwr#`ZH~Q_e-Cob)cJc%M?_*OXVuGJfuPgBt506#gO!pzVAlGGY6%<v`X`qeoGNB
zAL&LOEcr^~X)5%SO6f5^B>jm>!~CU7n?VAk$LWC&mS){T-(l%nw4w=-9={DhxO6L(
zGet<*VvHqH+DV7RqNIxx(HAXULH9+BboWze#Y(@rNzdO=soodOIO(1(=sYHUn_l$s
zQez@o3DTY4VT6g&^%N{llJ1}>JXxAeGgGGY3eD14QlmHePDu}&z&tHoI)?FPOGl~b
zCP$h=Rmi#0MbE;+Gg2k(B=V#`%|k0+dK5bs$D9J`JsV7%l`f{r!E@5B6sRebs;RcC
zNGhh;_Pq4M3s71tUFHGvCDL&%L`tRpv~DevzC#Oya;b3|&RmdIP|~tO`q(H;T$Fw^
z3P7ba&Islusedj!tdizuL$X@>!Cf#NHPUD3sjQV6-h!HX=`ZiVQiGIr44z(*-k$~c
zo25yuKwOosNdlrpT2u?kYtk%A&0UuUQ^`@QbR(U;XqP@tHHID1$Cm-uDfOHJxhds8
z4)`spPafc1(t8U5=$0nYd#J}D?Wc1gz0wo31?iI})8lkox<4G|??}Jd32pt-59gt8
zKw38fgLkEmQ;cL#n)L*94@vKk(qZXUUtEh3>2IYF8I`W6hcox2*;VKplOCds;(h5;
zbh*Z*Ubmt1fpqCp=$nu_Zfjs^QaYDD2rwlLeGEgJmWn?InUN-1aPggG<3`|j%i8H6
ziHmFpMIQFZR?_^sSGH>a2KULB^r*SY_FjVB{jwM#m~OIRdbZqU-Bc9pA*;Cs3!bt?
z-e7vk`tN{wKo;kq_02(93++98WuH=%*iXjSLFSOGf<jsTvS(;tA0T^zmOz2B*1w@U
zNH$E#>|j|NO*@BW8+L<)$o2+6GE}zY82k;BjV*^{xNQ0q`XXds(ZVxQ_7GKSM9F@o
zvZ82NGK$wRughLbhxr&;=na^Nm2F6XnxnFxKL-AoYz@Uh;$=5!&QFllcS9smmOw{r
zl4R>V;o))FSCsuuk$uq!zzNwt+O40IJw!Dn>9R?h$}(i%(hr&`i*iLPOE%^Pd#7YY
zf%N>Hmc8}}5ZSV?)KHoudx|Pyb7gr-AkN6V=;T?R>~E^L%9lM!5&i<%cNA1VD{~uz
z`E#;e>0lPhzNDh6B3Umzo9AWD$rxd=EU^KqOJo&?K}u!E=(S%atD}fixvUixK#n;V
zWI_Kzv_jUFfZz9`>>J8`R?0**FmXwCDg<_`Wbe`@t6Ek`yM-FrgCPKFW%0D$u9Ka=
z0m;j<%WdeZmu;fTqej^Tg;<(o%KwM8Ww|np?5ga{WiVT0O(h`LWHS_H`{26lRhrOS
zWsBB>+a`OS7AQAl=jr5FyX<>0u2-jQ^Q#!zO_?poS%{DYgA!18WwUnyFevLTLTgC&
z$5Qw-EE_ro+=wid0%D`Gd6xmdCwpr<$e8R6ni$7rzqw=d4`km8U}!>iw-nYVWfyE<
zPRX`XoM>8>^(s`)$o}jBbGLjW?R8w_eKaxck@Fq2gL0ME_rTJA`J;5`$xXhb4J~)M
z;#IUf<j*QVJmpu~;hLA6w+gKT@@MGwI4FOIHo@NV_bBA;E6;U?c|ZBfCn0i3KG=yt
z_{)z{-YY=<QU&Y=%ID@mOOX7(_h8|$e58o#O+w^$x@AM<jZ}#cCU-W&?{K-4f>)99
zZi<3N$$x1A{)oIs2$2}MDhii7R(|FN`i{x_`GCjEV+YZfAU{IUiIei?SXfGzr=|dx
zAwT>!yvUT7(5o>^zWY^}JthCs`2X{E@^s1u<jQ}hpw}6>`%?hs$(1cIpD%x#vO@*(
ze=N{_R$jw`!E^E<ic%NK6~n+4$sec1`+0fSAnX>)2NwZQDu3~10LtX$&qA_X?sFZj
z3-V=O!;1>JITMnX<hAqYl~E;MK<~e5`P0Sdtdak<0orQiW%Q=4lj}O*#bx<dlo6?y
zzq%8^26;Dy-mb`hjRvz({^)f`Hp%&=xCqVimjXbp%3u8e%oh1qeem#_e10o%*X6}u
zgS5(Drrk-K+&>9@jvI0{?Kaxw>;zcqkoVH!uv7jzr2%frS5e~kmV6m)X}jeAu7d7v
z`K%rQd*p37=<AiY%|>6Jd=*U;x8-$>7|R{`$CSnDmp?iQ=79X4GLXCSOBBi)lviJe
zmLd5Ul++z|$j2yRG9q8`2F#Dj-<So_d-649=p2(z(gb&3uAs?pTz+o>fDhzn>=2od
zpZWtPCguOqS(7RG_hAs3mgm#PU`D=|zMJH%Xvs#Oi{d=RZT2ZXJ`A|4VmAHC`xWab
z&g!Ocq>2G_S6FF_>7j6X4V|8fi_JiIDXvna^nhX|-T4O<WBcHYw}O`r6F!PV|Dw-V
zVQz;SKgD(vT89*me2iA8V%G)O4O6_-3)SI@5<2V{p?Lcwn2`!j0aQmRwyNMvw4&NU
zKjjg{bChI_QJkaC8N@2Ip96SQQB3*NIK|)e_#ace@-Fc4iltQZlb~262Ov?AL^1Cq
z#d8!uOjfL*dFr^rI}jeGC_<=6=!AlI36iObKW0H$n&JSh+)gUAKY*F8_#>H~zYGQ2
z4K8LX7SS}BrPxoWn@=hF{XkADVmClrwqh%VI&&1eNitUvvIn})C<MDf@)T(_XXh(s
zKLwEj#fyJ|oK-mg4CXmSHC0*_DrSDgAc_?4&W647it|Q@6f3?Dr0hqDV#Q{NmMNZi
z5*N5!QSdqJUQq1)5_T&Tzpen{qGIZMASxBFe~pW9NpXD*v{fm*sqms&5!e9}H3}xJ
zf@>8k*MeE6$UcFa^s?f|@8Ithh4*{tYgAMnfrTc;O)9->RwSap8TDR@?_wa+qWI}P
zytt+)`wYPA3I>HdS{08|xo4Z=RXWLkL*aNFy4w|BQUtt1@#<mVIu-M2@qbgX%m+$u
zDTK7i=~D3M6G7dIzuh6yqu8+!Zucs#(~6)^aq?^Q-B!p;!F1eFL{k*DUs1Le_yNV6
z6#c!cc+rm5prU0jT0@F+6qOuSc+n#>qR2C$Z&Xo62Vd?f7VZQYQ>fICyst>7wc5C1
z76mXKC^mCICKMk?U~p3L`$K?FDXRKGrWMsx+dJb>tmr_ev(k&gzI&8E<^Zu*`5B#U
z+owFg50}JEdHo?U-IYVxu;iiKIt#!9$}lF#LFFw<RC_CLZ--Al%3r8N(N~#BWm|qq
z?R}^|r2JQdmcQ~hFOUFb1}(q>m1(s83sO2dKS48CDf$+ohn0R0W1u0*1({G2s&u2t
zK1|t8mDS<OjkJc3P&QJqFH*UQf`n1Z^d)FTD-$S5dqnwwX0{mRE_(6BDnFeEa#Z;b
z<uK!vO_wpGW6IAiL1(;jnLAoZN<YUoxRI>vq)_&8rHN*}RAmL-b7{&)XdQS`DWPCr
zy0W+ytqkR3EGW%X9#{rumeTYb96hBx^g5WQm3xkZnXTlyKv|A*?G~ucReoL%ooAG%
zHlUTK994qkE9b|-ivnf52Zb!oD(_Lg@tktLE9@33uThSmNO`dry3Z@;(kaPe<-Shz
zl_>91xVcmr@+zDuQ~EB!Pg$-kq!hyi<xezAS13QD?<8JSy3w_$RPLa8>XPz}JlL&K
z&Z3Q1t@4Zp%sS;`-SoYc%Sz+3z}G8%-a==C(rSc>CgnFd7)7&EPpRLl%F9h?^(YGy
zp|n@|nHc8#lp&N1zpY$Dud_SK$ultDuPms*kOq{0QBmSu<*8cW29;JBEDR}ck=w&c
z<xTXBC~qQk=a@69d^8*;?kP_cLv&2J>MGp7uWY;nnQ^5=2jBxG^K0myQ2u%qS7uTf
zNH2mZ<@_w*oK=~Akld}RDTG}YRURFR*`snv0&}lwdj!Zn)k`k{;Hp~b43Yh+3Mx)=
zQ@Q*I)ed)6@P}x6sGg=;c~6xurGmUv&NC1_pjtwypo6MBn)SR@TPXVEqxzgqNBXKh
z7>1*MDkI%2hg6vgXz^G1Ga(tEnoTc|Koy(PCPAu)UV=!lDuwD24y%5r*k*`IZ-j+V
zhss9+HDRhZ<IoIOJzI)agsRjZ_()YV&6828Z{$!Dt(r}Xyd$dT=!S|>h5n3Itg6e7
zp&eD#(eo3h%BDcxF;(Ur{4nvVjkI-1P)$<gAyKuEQshaholgRuton!+=EqeI9mQr+
zR30>aoKTHYA$+PzG8@b^Rqs5gIjQn_5+q$!TaUgB)k7>enyK1Dd&(@;rR~smN)<_Y
zrPHe0J21j*)tA?yJ4e-)36iUFqEi}YRAKb~%2RD&0-mpuL;+Bs5<2MM_F2{A$H6_P
za$X0eg{ps@L5ft`E|Bx8V%p0Vt4d-q!V*;+0`hZ8RWH#@UZ$En0X5~SZS=Xs3#uDe
z;7o;Tq8!YNs#?0-m8ydj-mX?nWuR4~+H@MNT9uh<K<iYlk5Q1~vTE*5H0xDsz5u>K
zmGmi?S5yNj7;mF$TLOShs%F|;HLLE^ft#zU_$n}4R3o%jyQVs>!F9f_a?s-NhN_m%
z1hlIbJO+^t)yNA_)~On$*XK=@+Y-2aOSS7ew0cy}d_?CBdR51M0lrW5S|GgWSH;k7
zazHifUy!>hF;xr?t2XyR>4>WSeY8eZ%W3Yur@B1|f5%jx{fNH%s>;{U8dr(@p!<Q!
zdjPIYsJOK3o>Xb8z?@R)R>G%g)%J1#W>lZNLC>GFI`v1`-K}=e#==ECN=vUj>Yww$
z+^gO!#1FGyy`4giZt4Y%0J^JJ(i+A~y<h}h98gb%f_YFa<N@xj{+&t*eAJ6i0pP37
zp+XEl^;A9FKBV@g&4#}^{arW{pmyT}?g&(`r-Hm7^(G2F2df|d1f7S~E|X9iqJCx&
ztx$E@a`+UcK0O;I!qxA#fElGulfXo@y2S(VBkD3rejZidraM1Q{ns3jV``5#&=;@n
zcLOd#{q3u0C8}rLLMus~_c{Q{4t1jqmX50vJus#eb^il&o=|Hjf{?22r!t2$wcod}
zbW(kbg8b>~yp13k>L;IviA?ouT486YUrm9B*=jCT73Qc9^D*9BwJ9DVh3b#x7+H~e
zEoD#6t5@a0i(+;1TVR%`9S>-sP^x~v1;8?O8~y0zYWar%UQmZp>1>7CMmejC>N}4E
zQK_y!0+CB<+20^l>TmsFsapLTou8>uXI_BrT6NoLkUBMk$`>2dQ&jPLMZKpLS{l`9
zb?9qSub^B?v-+rGJDj?zo)`gXQR|n1drd7;0C-)!ol1Rgs5?4A+SNt0O6pKEjzF?g
zT}Df&o9bsMt9DB*q2hxswTdoKx4N$otseEow;*|2?Mg?!?x;T!W1Ri!zbGd$pmw34
z^<A~sQhNRd)yD+j4yj%KgKxv?WUBKSQ9IGbU`*W^1?GMA7@epXSBvLC=>uE~h)k$=
zP@(gr`h^0(r_`QQLN~2m5e|_VwF{*WT{JaR%e+UkiRS#hn(uGpBJ9^Zy&rvUn!nzr
z{hzzWsR`P=G}*J^;sMP?dejbTs#WmYSMz)<T7H@pbRhAN<{wJF25JVMMqiMocL#I_
zYyLh4c&KJ>Ia*<wwNxb@uDN#*24gi%HUN%lHr<4lI8EIJw2o;uP!1<vlafgx`vlEX
z6gx=NyyF2ANtzSyK{Q!oEd%qo=KCm+6wM5Uola<S*Fhvz<HdwXnx>v=CQfRWOu>A*
z#?}J!8JfQ+M3bpmNO9sUO#|&&PHBSZ%dw|5f7if#w&of|HF7j3oB(j-YLZ-_^o%BS
zHJW*vFFyhzUsLA`_X{)=M9yl|tARMD8IQpQF4Cl>pmknz?kV_GtZATNcZufU3iwp2
zd5&hwGEFcggv&JrQ-EL4h$wMTq1h4vz(vh(6y&SaB!$D?C5NVyio>cj>`mZSYqBUF
zSfeRW0AH(leJ>DonwP20=dxzUUYNh42^s*iQPUd-$tI2b5d3Y?+@sTI*EH%|ki4#W
zpCoT+_R-3^U2}B|eH|KMA6lK79iO0eQ}c5owA|7-rYT_4qd7@Q`Cd&v?bG`-3)kX8
z^=md$kbgjP@OJ?3YU+MR-=HRjs+5K_e|>_!Va*RIVBXWbMDy~P=G=!M_ciw^a5<ql
zOeHRpnpVm=O=&#oB!;uLV-H%pwL%8^T(plnD&Xlp?a!})>#B|U5xVzlwUcPMX}_mg
z(_Pz@2oVqM>Oc@*EsqL({Is_yaehcUkHWV8+Qd2VB0#&5ZtFnpbF}Ua(vEzA3mmNd
zjY?1tYcEh9Ekx@=k$_O`>X+e6nD$b(1I=*lVRv{Fp^e!9V5GK^qQ+6$Y!#e|)&_-w
z9MR%`rLgMIK1{!TtTvOj#7DJ@s7NYK8_tD^W7>YIWR2IpNa4f;?Z$V|m#F<L7Iu@g
zt`r<e)=oc#%Y0n>)>AN)qD`!#fAc+|o%a!Rr)rZZET5*`Lgz<MYGdgfOS<++`Y3gV
zwwdnEOzp`x;Y^nH&3?2_Y42Wyw$obw!_bzk?WX`pj`lVcN#$yL&VhMGd-O8kd0Hk#
zX7jbn>2O$q_F*b+Jgc3LK)7ShIc=^L+(PYI8d{OIg#sw&wYPsqt62N-WmqcF?(##c
zRJ)VbAZ6M+lo>7823`X5g7$r?fvC{N^6;Zw)K102?Mm$q%BEk^HdCauO6x<lR@GWv
zC|Y&eFDb!tS^G6bMI80o_EM;6)N-Q0ZPIc%AkErmdg1pq?IlWpU)Q$o1F%*5HI<CC
zYZtr@Z5`UwKVi31yZ;6Zc4>FfCb(OhMCpef?N{GJXRlTp0g*oKESi^ZYhR{E`;PW|
z+F$o;pQR|<fJ2*4`S-ipM*7tTwe!~Crx?<%djr4`?Gie>II8`La&-5!??_;GOv~f|
ze_uO~w$$TV{$>CkXuqQ5z=XDv0w9yx5(Ai1+IU}hKdqe(hNT(pTnc_U>!#|^w_C@$
z52lOGF(87aJvygLAbWLh(U%MM>3Rau>8cC)9@_TnbhIsU)7_z}Rd-#W8qRp=I{tue
zPn~ZwlzQp@`2QDWbUAdC;-KzP8C>($4HN+9qx;YdNnhQyI57QmUs53AkS^;}Nc!vi
z9It~LpcBv`uRvY)CS0K)-5yGP1?z@s&vaO~=Lv{}=#oExhoQRWBA5@;xll<#xbFQX
zI2xf7KLghybt-z8qjWEBgxzS}8}w<SBf3&PbjIj>mxILW{_TS5qq+hL<i+XCmGt}_
z(=9y)V7xAxCaMJ8911HY>K>)nev<BUngf${AN&V$T=#7kbf@U%{{%HBbd7T%nX3Ee
zVf3Zx-c|r`Qg`rYC`;F^dk(5IbP12c-%MS31f0pzjXndBQ@Y1#b#+?DuA%QeWb5Pt
z;B#~XRBE5ATa^i=XLPH+f=r$+fKsXXx~k1^zd+|nk&m;w8agg<PWL+fOock%4*@UI
zRa1G>d7YHPuf;mse6&h*{Wh2{)qO;P<uctfVz^eW^V<Nx1zj}u$&NV{x(TYXx~NOe
z2C!16qu1Fbop%^?SLwz+gr!<t10AKW(>=Wjt;@Q9DbQQ5dz6ZO8+0B|L)#VI)>Sar
zsQbr`z9wD!Vkm3Y>G=R$)xF^hyDhpaR91COSI<W4x~}*I035Bl9cSTUn{JgJYHsLO
z((0~Vx9>Hm>Cj1Sz<25nP!Rd1?#1;O{Vm;JbX>4YH}oG`-MSxK0O-*@gT?fmUY+x|
zFwv*`lKxuaw$42smhR{>DDB^`%V$DlK$l4Y$h*4yI7kjUbOQ=-hjg_MVKBqG7yTeQ
zqRXP`ZdA9F&K2L&wMRl^OgFp`efM>XUj!M~z19x=1Kr05AvvLYp#dV3x-3d7PwB4i
z#uc5`RV&dqqgzj^o%Qe0nrXLw2^(auK8=zn`}B@x`nZ9sK64CYzkYHpxNiE8C}?xn
ze@fMN9{Pv3!C_B*#3G1z>3L_sJfN4+(|k}rwiVjE^|5nd!biW7Lc6~D7v2ZcPd`bC
zl0*8%$$<OoZ~TYL9H75{1w#tdHzvW+ApKPb1^I*Z;Z$9DSTCn2Ux@zoIS>uiH_>Z9
zOh337O2hT*=%b|(`rQ@)BK6*MvM);is{nn``Xd|R?-Bhjg2(7rZG&sEdP6T-NA=sO
z@IOvJLEEuo`j@((C0-x+1DFZ=#$JlQB<g?K1aFe`l0E25)^A9H?&JCoXev$7|4e(H
z6Z$VGz?G`sSpboA{mKg9GxT>U2A!!F(UG7mJ%ijnrSI7T4^Qha=R!-i{;x#<<mg|1
z1+84YI0VYh=sQ^e<mol9(E2l9A3>X?bNXk$flQ&k=TRsv(*HRJ221qTQM5|+3-cjT
zrca<-zCyo+3b-!nKiUEhEA=1JwyIjc$`iV4^e=ycR;|A9GmvKew*6pU)o13wV2j?n
z2+FSMj}HNNT`xr7!!f5--|+)<x9Ov)_Wg$bI=wpD^^0j$*r9KrJ$R>nGfj6l_5V;g
z@-6*aR72FIU)KVWZar%yE?$p5g~E!x`n^@?>(f{L2D`WQLmhzM(ch=+Nxwdd(zFBm
zv?qbPtACj8K*ykdh6XdF-%3%hVf~wLLCuI>+6$Rc{f22U@9BpPP&20AL`&QW{TjLv
zC-tf}h)n69)570r{lg_-&ghp`0pM&n<b(0<Hr%d2pNl~o4WC>M2k3RQ-yo+?6}TDJ
z(m`Z*hv5Rfay$&1={St1A@vcM_cCPDj_-isM=qG&h8MPj_!z#TGxWZOs6qh!4D-sN
z=8)k}9pL_km9L{Oz@R+_OM!;*5{LvDR;@-~u)%`?5@LuIL3OBMQ87FWGkin4g>Zx8
z<}ElCVVF-fyitbzF9RQK;LxLb#NhfI)WjNUaxk=`2Hr48oFPXFHSq=;Z37bwi)ovY
zXkb$CILVN67=UEMl|i&l7|tw3E7fp{qOfU(Su{<aG=x%KHr-&*LnOoSkb|C;OhfWX
zD9ti#8inX7!|{7)<ru=IFv48JE4>gsW9WMal6i&$43K=o)JZT44FA%u`>et1Ck*18
zA(ghRg@$#AtIsJiJT5`sdBd`M7)!BX86SWWLnXcLOAVWTL|>U<ZWl#W$_+*~hIYZQ
zpGHw(i2WJ(ONJs!EL9l{sc@#+u;FtsYYejAfv+|EK!q=LhP4#syKK;xfLU*FwE)my
zi1`K{UNNX>jo4@yATOE>IcL##)sXctl(iU6)17<G;N?%>Te)u7K^f9k!<h`ov>6tT
zp>@Ns?GMPb8(eS0{SL$FKzP_`_>K-#-88&D1LiHm>MIcGGCZFGT(^O@9Hhq}3jnj%
zV5K-@pP`mcblf)l9*4d=hUmp;^&1u^z^4Jjmx!l3<_sA&4Wc=0=%w@DBZf!gV1CTd
zM!WX=h7-3jig82PXCMy@?UA?$6Nczj=$ka8{R!NRVeua5b~eua2_n0VxN)(bGVY)Q
zr+bZCXwkFJ=uOVJ8c)(~wcqF|M9a;%iL%5FcjJ<WKs}7({{Z1>jG~u?m+>1~9Ud^+
zUx88|<7^5}`WoG-mfX+iX9D1mG5QHG{f#E7@(nN^cY`y5#z!e47GzvHj_VX`yhO|9
z!^Z72mxLIlG)spXJzOCYX8gAsxNwJY>^PK07{koKM;hB7gG`iB_YM%zMt3TMIby7#
zR6~rhdkx4j<1015#~Y`qAThys1WD96iN+gLEs<mtHQ;ATHd=2&_i^JVwP2<gdnnm_
z!Z;8Fl4{iCLnO`U(g@WjjgI0jXiGQ#7!QLP#>6p@Oyf&$gJc<t&qL;vv4(cPr;TBc
z1D|btgpR@G7>f_WM6S_9%d0cSE6wmC&zMdti+tl0MKcSG!%IQV8q?3i;5p+(BSuze
zl+zi$BI657z&vk!*I~kSE;fEm3xyKn8mdt#HNH&63uVUNK7he;<K#QIKo^XKV;~jA
zWeOO)Xe{f8WTo+AisoE0t`CE@Dr0XYNVU;M6Kjo8K~qYtv5-<Kb;fa;moFPn(R5R9
z%zqcoG#HoLX#IJ`_-Y+UqmfN@iA~0MN-;JYKO|4D8iVOsX)z|yYWAA3c{N0?8<lsU
zt<|{454zioQxxU9VeF>w^|c%4P%Te~v3?dT-7*G;0M})#cmaLg#!Dhd_88Y2fa^87
zzfDI5`iv>{K-@O!-^O_F7~lCBo&Cng+c3}p;|~;^ylcGbiZKluz0D9AGL})v*Rav}
zIhZ5H97=SK8F#-4$@|8ARMk9g%%hOh10#pbPZ-zHUTM<!3QgTp#??V^X4>fd1%2;f
z#`wZ=IOS|wPnoFQrk5zV;$qsD0hv9fbM#e&y{5A{0PZ)1(McgUlPDhmchhMauZM|E
z+Z#{QI2}#$GQCD0dN^R}qIc9mlh^lXd7D072`xURBq#XfYg$8@C_j^q?p((q)47+S
z#@}@2K4bz+n|6U4XqsLE6G5gMcK8%*nlp^P!=`043xt>=semNZbml1-3^RR6Ys7HV
zaawalm|CbdE!q^7g1#fBPmqtB6Jt6|%3@6=S0QrL6gGp)6=(V-23{O<n6hd09dD|q
z=P$uD^Dbl(P2IHZO)|OD(WYcmD9s|rO)iv;NHO(OlpxiV>V{UDDL)3SlcsMSa5UZY
z7aar2Fip_~&NMA|M_-m{!8MRmreYg>I&B(X09>{ysU1G$m>gkJ7|b)xe+Ex;zG-bg
zxCN${65w~CX_*70$W-?=be}iLZ5U{=>B~u&C^229<$kHj_WyN}$?ph6%1zwg;PwU6
znlf0bFrA`A)<u(oVjY#Huh&A^C6h1R<5i|CiWyX!VjcNF)R-<)`D(4n-wgA0ri5+K
zecANq+vuw|Jx*K12Gi0QXuD#1hfWhUnp{_+ugN6*0vD*+G@p+6T{WHk6=P{JefA1;
zUo*|6bli2*6I}S)YTD)wyKN>{s@%F^`j8Tw?WQAJse-b@R86n;PSdXeAU92&?l9kF
zvS<P9Ha$&qXpgC#-Y&hS$LMX^XZnN=dEPcHp|avTrmHPr_M3YDg7*Waum1z{t_lCs
zizmip`vSurGHs#a*<sUm4akVeKxEY9hW9^~SEfNKKOHlDmItNxO~Qp3)3|Ah0#y%8
z>!=`V!nFJWlunx5UBH|&C1%3XwCUd==$<j98sMn2`QcPBcbm(+A?aeSqhDl?xq*(t
z?=`>H2-W+{3HNa+UCnJPG0y$w`F#4n1vm4n)llkgejxz}5A(|BA>(QOjh2&M=C^23
zdcgcV1u_nrBZ?v7ZLXtWxsQ1l<!OA)dv2l6&-^vTdk>j6Q3B529C{8q1I)vb7-*pR
z&VDe1%uc5P2sZ!R4AqCt5druO93keF6gCbu?>!4o!_3Vy0EU|#C?}f}VU|*QE7Ht#
zg=mzy>}}wq%^UpT{t>fZ40OksC!`RGHGk#|a@3qO2hPNqKe!FaW9AQzqZMz?kU?jH
z`3-si63r!}z$KXv-32q*VLnK&%H!reJD@bheD^<)6Xp%Gz)Urp4}qka6>0c=PMQ}{
z)-~NcNJ+&Ea}lkwPMO!!%lx$Y4Jt9qHmkj0H^*FA3P7&;iw6LlF&8h#Sn|wzy7>9#
z<Zr<&FjvyH=B(MVDiVluX5Yi`rqCR*9<3s?Kh?yYH@`!x*<$k}6j&=UOQL}<H48UF
zcbU1(9j$V6tsJ-u<{K2Us4(yP3BSQb^Rx6n)0JjdieFwbuU0}?m3jFRXsI^ur?2<b
zn6FttYR!*1sLs94eDoMPFPndw0k__qPQ?!m=4Ptyx?(o8!(gNNefs2FllfVi(3{N*
z(r^*4n$NueT#NbTqi9_-e?nedH$T)1(rR{5!oxQ61Z5L$n4hF?fVP`2#=xfz^Qa0s
zJIxL+djH)tYtBICmU#~C47$uAk?8C;@Bjb1%KUi-M0(9tMG)yTM+8C5ZS&PqwC<Rr
zBVnoE{Lc5d_ycBUEBw7{-tZWHkwLRZ6U+~pr(Q&B*j!Gl*b%d17F3U#nRJTco;mwI
zeeYq+JXeA--8bKR2{Pm6o1Kt(U}nsL%!FAn1@n{UTdg2d<|n>_iD~ng7bIuQ?+?Hk
zXUm3kc(L2EQUae`EVmu#+hb{<u<c%phE}orEguv?#Le=@Y7lpen->0hSfUas{^Dub
zB7%!vmWLLB>ut&O2j0ixPSd5Y#YBgE{4M9C@F~DDvkpoFElaL}8Dv>VA<|&W(-mMI
zwruBvgjnKV!&pKs@6+k2Fw2sqAmNt%Gmwn1uns^Z(vtQM#&X0WrhLC6#xg$$GO?Dw
zskrl~WnBhZahAYSaORk0z6COg78Pxzk}My73^mD?zR%Ei!qQ7uCe`B9g;ttnd=GSI
zSWZm>o@psw4`o>vRslp#S$yMholaYtu7jCv`TP+`=2$+b1VHWz%QmXZI%DytutuIG
zClQ_bmZNl%rNH9(JrISKKPiY+WQh*C<NEN+j;a`3#0twp!@ys(tT_x5m6mnmki2Ah
z;~H>PmS-r^Q*F6SGfa&o!56JsiwkWE>nv`+;R0Q@Y`1_}Z&^%{nkyES8b4E`rFsQK
znk)_U8f&)1Jcia)i<wGBS}cE2F6EkKj)TspT(@MXfM~S@evR?AS)3`{)nU<Yh51fP
z`vAsr)AC_HJiKLDO*dPYWi=HcbX&p{5b3o%{u=uFEMtX$-?of=haugu%%>GazvcMf
zU=CP3kHEFNmR35^F=!d3nCOsY)oKSshb^yNhc_dZTU5?GYRT9InR}L96cZY={P`wY
z_btCtsmcQjlQzf`mSNgEOj^dMY-h?+NJq$~EuJ5PIb&JG1;E)lxDGz;w)!3h)5ZGp
zzku(t{vHUj*XkyQ_xr5Nmr%ys)%v41@cXS1v`uicPEqpJ(^_@|=Dn<MPyyEgtLpzD
zDQg3*AAPMmkHD^<we37i9I|%OyzFmXQiN83weBCZg00KvLgcXZi$Bl`v5r!ZBGkHL
z8m@&|uce|d+#0Zo&dWzwFL^>H(pqnU-6(4$Rh~p!zoV+XBi0kw0F1FpIUupt^>1P@
zN3HF&MU1niEP%FSRvT4S##_HHL|=k6j?POYTRSPoecXDVwkIjp#C;$qtjqp{&Qxpa
z>mX@X&xc^hkzxInB21aqf>x->vij1Ifo$s?dgJ9-rL#bCtv|dBgJ-M-6r|6yeyW0r
ze5<zuN(-#J>1%0ct>-Dha?bir4ZJ9{<|m-9$jZn>>%8?m#TbjNzLZBRvHH`zT54^6
z41Hw|EB9TvQEuHv-;KCn{hIQm6;>sM7cN@kc0hNfHJEAuFIhL}fT*&*xdPg%txr+8
zLXGtg+WOR5y(wE%XDz1iX@hl&0m&=Y=N?91qxCt8z%^Ne=o?wh)>(m&ylUkq!9t7G
zkxO4Ryk^a%(9(75)AZc8S~t_>ZnHjI59SSP-Ci);t<xO<c34yU;8Uk{CmpM~X?=Sd
zZr`$oY=UH$)zX7jx3#SXtsd*xEsU(!`i(b8pH(%5Vc)h2<^q1lniYjszg6tWgXn;@
zXbHTzYc<jwIAmo#i_T$d3e};ESpO6QKWbG`@%cS#F6~LjtSxl<;=Xm)MgYdG`{)^)
zuqyU|Oj=ia06t~i@iG9@){u8`)n}}~J_SS0w)&sJ+-<9UAGkfX1HSae+H0Fvg3f)m
zjb8%jYTJ+uXZG8iD8b`ldm|MsPaD$>l3uoFsLtqs?R&~19<*`)!$t76%{&T8AKQzM
zK+@NCemna7Y||7FKV++=*tNecn7)-7VEgebBm-^r-jEEk1t-%#1O?leRAzYC_SCBY
zhS<!PG3-!V-WNcG*-{(eX}E133%^K&?axM#NLzav@KH8l5PXWZJ!FQ`Bevg`0Ul%P
zq}WQVZ7YS&kJ>ihg@<uA_jAy4%yysvB;Iy;0dNVnj#U(~OtfvRg^R~+I8%jZ#r9e#
zbf2*0K95$aZTV@m(riaQfXGRkC>&$TwB^#Rn`QGILF<$)uM&NyZBBo{e6~$T6@fXn
zL!L07Yr9T6m@~G*pTNwsxzZ$`Z#xtMQed05g6TMG%e@F~g|=l>AXH>~jUv3~Z4rg=
zwAgkl8q5+Klg@IK+TN%08f7-ec3gyV+hW>>RoH4NuXNEC*#gN*TlhvWFWF=|z^iNv
zX>nL>`<KR2V{0h~v)1<Z28h(z`Y1GW*<s7Dqgij;8IMsk*e>10D6ZHZP{yFq_G}Zb
zWs}WF;h$z(KGk|%wXJnVtHt)$WhlL7+egpQb=x5-Uu(6MPGQ(>HZetpZ`i)4nz(kG
zhdW&BuoY4<=q=kDG?91N&L0Gz+va$54Yc*zE_{Y&pAGS0JS4Uh7nr|eE1~^CzwNoR
z01ntL%V6-XEvpl{2W?t9z%yi1vLP~T`<qSyj@S$*Au?*~afX(AHtmZT*?rr+xnPdl
zzOToHePD}z6p|CRG+N0_+CFtKfS<NKGzM)mw$JHza<;Q+!Mof3y9lni*xxz>(Y<!o
zUEufGx1~eG)!s(C=Kc0>X_ez<|A=<B?sjtuBt7g!!DxBfQz&fYW&exr)dTi=x<Ci*
zKhl)sZC~*%`h4tV9Ey1Q+MlB**3bURM#vnp`%<*p-~Klp8Vj)d90duq|3=G=5c?JS
zj!CG!nL=n`_JItz9c~{Dg-C>b!8X7n?KiFi9%awn4xQ0<&t&u+u``@tFvh;L0z*1#
z|Ap?0ID39DMJ$imhp)klc>6~jh$h(cXcL@h@1uxxl3iPc5hmLMK7_X8_MP*APqBOE
z!hEWIAJrG7*$?G{oV1UAfT5+^AErqp!~X4$P?l+r%t2q4{REw(Ic5LvB3h^I3q7DE
z+rD@CLwNpj?91HYO`d&%K3I`&&!Ky+z|N-%)wA{y+KHUA=bi+x(C$Jz#UgwE-@u=@
zH+92Av0cXjpu`@`huu<pw-YWxnf=SnXqDTaqZ3&d?60r^sIXU4_1i`J4q7@@+CLpe
z%W=v6A?<*w?4QsIq1qlqo97z)1Z`+)?Q7bBud}QEhUjJc%R8XE-u}rxkOn)SHU?Mh
zZL~mWw7=>HktX{e_hG5oKJ`5uy=wn^C3LpftDk_DYjzL1bKC3{A?Ukd57+}O?GF1>
z6e#MjZy5mTwBL9Zc5m9pO&ISjd%ZudbC=z`8KT{Gej)HZcJ?wz_S%(LZ_nwo&!yYr
zw*BetAb0Gt|F601EtHKIuxC-3(Ovs4sxTe2htQY0hU_OO_d0A(q9EUh-C<1waMXUi
z2TJeR-+2=T$Ls^N#=LL;brzW8c3;Y~KCoBbg3<|lEp47B?f<qwWXgV!@(0uQfD>TO
z*k_)GZfB<sdZq7nN_+tT7pLWzX6Nj23e|$S*9i+|JVs7jikP@M&2vyt)!k_U7or|c
zc6u#&Iz6uh)63~os$@FgltTCHL8qoh5O1g13o#}ir|qS1-`6RCUYLGP`O#<{axy)O
z5&Ap5+XQBS(``C46X<mK8F(1v)Vm3nE7<8Z9+-!n20TDQoaU{h^=GIP*BMH~oF=Je
zD%>glCom(N+Hay2>C{SzuqdZG+Nef5eP@TGN1V9zXvH}F7YNB%rw>lR#8IbRPoov*
zw3fU$=9Ehn9Pv)uXwFV>+7}Eh$DNM<i&lzL>wo`a={vxpx}LXl@9qM-EG+CTyUPN`
zl9;B6QPVWGs7Xv>FHvKOiLoU{6IR8<EKTVMD4+s@6s0K$ND(O(Iw**ufJhS*6;u>O
z5d7Zx{lDk&ah!8z-kEdumUCw2T!E78Fz}HC_g{)bM>#}KJNSKu5vDq9ybiQ9hhkdT
zq&u`pVd;#+q)u>|4l|u#BFkamE=HK`@M;6}&N>{PjK&;?5Bh+8&S4fkNpl^NX2D>d
z!!k0M?+`^xpaO>-l>I;NkWR-KE;!7>%f%?W=<pWB&M!G^T8++Phj~w+SmJPOF`OxN
z*tY_9D;zX*uT(lbqLu1phj-^-W~v?BsJi&7gV%RZsBwr207|Wcn!<WF9A1+7n+_GR
zP^fbl+X7PWP<sQI4GxosAkyTpYbNX&n;m|jf~XdU-s>Q(4(}q2Dr<9iLBGfyhuO6F
zZ+EyzOTG?=Oe$l!>oDR!kb4eKDM#Mv5J@@I`wn`fA7u|5<mWK64;_Y{K%~o|=o(13
zgCPKx9yxf>8sf3Tve~fk#NjwqGW8f8dT2rQ)Zw>}Vd<H}!6iWJb@-LG#Lpd~=uGbm
zhj*Ikc5wKQ48C+Y$Kx02cZjC4$N>ip6)3!N81^1a3_9#+K;w|Ze%gn<b~vyCoRi@?
zWdocIv+}{Y7?z9%aW!oH5RGmI<Dv}cyBjhO!Jvnse-+Go8ba2<u9rb|06uve`o093
zkKro|5MRS@G#7q`Clrm@Z}?IPyZ(l2=}-?ay!{>Y0uAp`viE=?j$Vof4JikJ8DvPO
zRY$Pl_f_Z%F?>vAbB7G3#%8#2*bqk>&Lajhs&NT57<NJ?%uq(5^Ke7X74#i76j7=!
z!tmAs*o`ziY=_7(!|QgyL>cN!VItaaZz)KOAzA^HSi=Z6ICI=Ejt-BUF#J9a>Inwp
zc6gC!h#Lu%BtxQ-?!S|UFMYtCGDOQDlWa($1l(!E7ZlA*H3ZoMCe1MUDh88o;Ic4X
zXAEoZ!fuwKVH8NV;rVxP=B(jR7Zh>~PX%!241aF|X0Bn7>P_<uiztGgZ|G*h6&NbK
zK`t38PEf^4p+QEW>>`76C(w!wYiVg-V%XLSjZ%Z7AJEDS{aFwxH`wdpOoicmDMnFg
zxa|mqD~9!SBBjbO5COev!~PX;^s0fYL}QI1ih>N+4PVlyR%#8g_u>5w!!b92-82|*
zB^YIOhRYPPs5jUuq0wO2wF#n)hAXt$xo!A{HjYh(Z$AOoY^b2Ss>LvF8Z5OM-j0G7
zZHC=f;ZwU|B~>tX7|JPybl1?*g2sD>WpwFu8nD*FJz}_S4TT4Wudl$~OT(JC0A?IC
z3_QlHzcvhafT+ukk#7Tg?~c$X(D2w%whevWJI2zp+i!>E28cxN$ZElqB<=`)0JM}H
z_b3*Xz9Z%aM6!1LLElKp+3|pOnt3~_>)`$Q9ai){DBLmD6OH9N&V&G^VMpq2^mQ6{
zRNjC$Pj{44Va33XYxm%k>&_6`le+JW%SGS*opqOC@bJ#}D7trSXCw#x_??D$aHn@}
zHHG<{on!PsyR_4K49u78Jn<Dos&=j)2k!dLkGDW%|1Q_JU?FtZ=}1ga^sYT~0DXFw
zvC|2y8M_AEftI(+e-~g%cI7mpvualg?I`MZ&G3WBom~-B^Koz2J6gE*WY;(ft@iDD
zNUNP!yS}%Ex{Kq9b_~?Zao<5S`Z}JYCuyMLy~ofCa{Qets6rhb_d-3!@n719#W_AP
zYG5hJ@g{wqE7@^4DW*EE41(wx$CdQF$#8si4;q<{{glkla+K1i{&F2>7l6xiyv72%
z!0~q~<T&s6QyBU#I9m6CTyzZGih*8oTuvh^baWgJQslUrN+3!c-=x!RrH*Zu^glG0
zJFca5Mup?buhClR*y{wJE<3u@2JVXEPP*Z%9se1C7grs(j7MLMV-Cept~tg!z{6U{
zgLKsHhNA}s8*Vzjl!Mecj-lvlt79p>&DtG*i#LG={#;~^(i*>p8Jz(4t{WNKbMWW}
zV@6k69rK))Q4P$k_o3Cu?4~-1CdNqw*TT%FbIk3`u{Y7!&5S;W0li@Q=$+uino^O0
zC%f1WD1q#*WXfCPk7z>`MI)!3#=l41_kyLjHqi0hw*zREIeN1j#V|fEq|MqF3umKy
z(%=-JPY!Uv-(P;>kKQRJbKug{bHC%qoc4GT;HFQfPXWx>V1c>&s+elPXMRhS+_QfE
z70|Pz?V$Vh+I!IbW&(YP>)UZ7(L2Ya8(QCa-^9PazfReW9})*CVmr664a_|2x#*bx
z_-%}8ffsEA7HVtp_o8nrptktT1vt0FcOpQSTF_%>Sv4h+e&p!+u>5;_w5)Ji1DTaq
zDdhQ6SSQ?CWlqn>)n1r!*_z)y(6Y9R?&Nj(^z{Gb>^XY={QA}?D6Eh1L-%hQTXbxA
zMUUK#$&|(V*OF>E_A;F+40azgg;MD5Oa)z%9!xY<u6i<7*J0O-c|mV7Z)W~%c;v&p
zBL%82^L-fr1DM;%&}(LbsEqaz^VU{0K4xBF97b6`qrkNx8(@B<h1y=09S5?HO_TxD
zo&AbxZamn@`@ng!dz=C4#U302j5pgz@j4&YluAy0+1a--`C;r~+Qfvj4=7f9f;~#l
zp*Z#~ooR_@`vn+EU~_*1SRz|a#~X}E>;x?oPqKAqfqjadLXm=G_D}lCSqdB12JF-9
zGFsxKvR;%@PGhUz0GG~gc?VnuJ4hj?Oja6<#w@mKB*4x{exOKMhQymnXEG%NbZRb3
zQYweRY>D_3jb|lVD%;QbRq}#1QRgJ<DS?wK*|QTcd6M(h7+St0aTj0;B)?On;Jl=Y
zDzPs}vd3Ud7bV4;pm0fIPW7{el7wTxE|Q%32qMLj@fpA_k?h+Au2eE1WLh}B4UqaS
zP%0&#4#2`?$qU+3T#<|_f@@V04=SXomW2NT=&KSf<z{Lm^|a%?Ch1QB^mU2#T^OpB
zJf^MG4T;yUAU7q|!!QSRl0}q$t(VNBz;A;j;3y<-Ngim>*eKC1hK1XbKaF(9HAy%+
z$I&b)h=8RQNe^9ht&-4km}rwsvIn^%38$*McFD|V@S;Of&<gIZ#MKH0?@9V-3)d<6
zm+sR062=$m4<v(s1Nxz)+<?9=Nz6CU>y|k6LgA65k_u5COYZ$kwLwoL*FVK1^hj1w
zS=&>I>sB;AlZ-kJhkGTR^bC0}`F1+`UP!{zV7E{5>?E*XN=g}U{gRzjBR(K0d>bfE
z(f}un#aX(8R+%YMsRrC>=`{l|Q>DfWKuMEso(hF@X;v>qy3R-=?!fO1>4w*6&6N5S
z!)}&z8Qq^(q$Bd6UnPC{42soK_p6Y+DqTy5&~8Z^sluXB+CTxxcImWg_|zf2Ivxt0
z(vV+hE~KB&fS$XIr=lwlnd=Go<SF}v_CP)ek<*>-E87}?RzKNfcj)hz#f^uj5wbmN
zpph*zn+I}McJv`gj!aKK`Z-zuP3Y&!-lsZ`JZy1bB3~A64lfF12^Fw=US=SFFUnR<
zhKHAABYe?VC>ueGf+Bpn5bDLUjBfN9OJwsI&{CP2KH^g*J4^xk+a}>O>?V_%4Is@X
z|K@|Vm>e1d{Z^AqdfT*_Orq(&WAe!$6xvPR{DyullhJfw<hjY0YV^G}`JHxDPNrYh
zL*3cbw+UXjm~yno^)?l|FeK#Wst%*o*YxNlc;RPym)2?iruLs=Faf4NNI?QkCzOF4
zG`&gxLtv2UDS811n~ta8P>AU^s(K7Ho$dk>X6ixz-$c0S%P90ko3_-TG2L`}9mpBe
zcU(a-OqDA1Wtwg&r1>>9KBc<M9MfZq(0R@@_*?jvYg#i6e&?AErz1=Grhc~IicSBf
z#aD@`mTreq)2Jg*C^H>B3615ZjZcA6X?lTv!po-8A2IqHrVn*+`=;pxTF2Ize$@rL
z^`;joR(i|y`4Xr%nvOG4IO?`(@G8JGnfk>8yTx?EAbe{z{UQa8cT5MS0;b*cCdJh5
zns(+v;hrgX10wfLeQAmR(6pSAlU=5ER1DZ{dV|j1xtQ($1>PSrOR|E&!)CMF(0Igb
zYAU!;vzZhN4>Q{uMAaAJX07pnIchdU+0Y2H_o+@e(#)RDZAF_IZvr&Ntj-1_j5YiF
z8XAwA&9;IUac2LzfW(_^`x+<-X7^r#OEmjvDI}B3v_ApmjM=_V;6;X+<L`jZGW&yG
zO4(+k&ja(U+3HZb|8mUUp=ffh*+Y8c=9#@pKxe+0C++YH%sM~7M4dO=vKx&T&4MWR
zcF9alOQJ%v;XXhsG8^~?eI;g}(=)8ptic+j%<SMo^i`NmrjpT0GxK?H?XsC>2e?i%
zzr#?!Z}uVfm`2${vl($1eV17mMU1=6RFs;1WLCQu`cKT_=-60~nV}Ji&&+i65bHHt
zMj@jiv(y5({o3q4g)p7u&jd(1%fHHpGcIy-3Rb$xJ4OS=P5u)dpWG{NSp<cB@^3BB
z=q@j%Pp%t1<WoP!2>s>RE|3Y3d%pqhfP7*<WDd&Rwt)o8A9+GCL_S12*JQcQ2bNOg
z$LJN8Dj%fHc$$1@Ezr{CO8UQ)&dC3|2a+Mb^b!2clsizpM3#K<OU!S!{8kkt&&m(K
zfO?Km?nmpEbMpJmAi46#PvL%^eEMu~`SP&s&@Yg;(06Fg%m4iV&Rmcy^600K&!Mg3
zCHWevVkngREdq9t{L`c8E0({e<X4Hjm4bhz^7>tnER%mt*JHVS>wJ(3c`fDtFUyUV
z?U1=5U!=mYtK>hOhNso?_o(Fis=VF+(Hi-T05o2c?;Qcj>vG{X8f)c$c7oiLZ`=XN
zI(ZjuitFVowcr}$7E+K~a_LF<+bADB5$12phtp}SCi$NfOm3F@-+)MqyxU0I;a0hc
zFIwB=20gsEBj33eq+Ncn2L?OjFT){nS8k*g-#vK=t$;e^5meg{fD9`{0u|yEC>&A9
z9{@B|@%3vAElhES4(Wy~0u<<rP^8X+WTe86HVRRS6R$v`6~pW)(-Wh}e-ogwib#L7
zo>0u(1eiEQ?0Xn?yuyDwNP;4D6F`#`l~iSRN|8dfLCK0w=;-WOMG6%R<tSEv1D|pg
zO>{lwDQuj9S)}Nq64@(?xwLYsQcR&8dbQ$2F(&V-V&X{pHb9M{`%@@hQ@m9GwCf5!
z9pkN4@Rg9cp^zoP?oGwFHv!YC81@vT4cIVvN0I#_xOT-B8bpU8g5C#r6%`cFyr($Y
z47WQKPOsqT14ZR#G(J=;;{n~JXr^dVx1ubRGChwJ=c^&}SaCN92A?R_(P4!i#pxx$
zeyXsg8l7i~j$^>?ReVbC^cRY(_W{$VSVUzlFBM<W`mbM6Mls6)MZji|SBm#2JTj>G
zHVE91qTLDHYXwIqh@8w51i0pG9yk%i=wg1K_8G3`A8iBcX1-GigL};n7h|IKnLE;w
z&E5PC?S{O}jr7BMo8Oy)Mj!Jjw6O6rFK`97-#kYR*Zj?glF=Aoe&if11)BRm1M~s&
zMXSIaG+(+8>fz@9P@LhY`Em;JMi|Xcrh-PASO163DD%pf;G)g<&~G1O?m*{8TFlvg
zxc|bum}*6xlruL#(pi}t1A{Kg11HIQWd&VOZp!A{aCEQo_-g2RDsS{c#7o(}0UmlQ
zCv60#kFsJj6#SHXDA=-JX}m#6*#Ko4o&OJ1`bR@1SeZ%Zw?dS`KcerDa@#*}|FBX;
zkF8MU5~^_xQ|dN=3s=f1Y<E<7dm$7em0gtQI;Qj*4ZSF(%M@TnE4@r%DOS038WfHz
z(?cP0LOFf`{EbuMbB3U)%0_xxrztmHf%$Z02u1YID1W4vTZZxqRjFhu_fk1emU4z1
zl4q48=uXd3I#G5oPx-|h=oKi>{ei~w$^%<qw_4dX1iM$2>&C!fjna8L`mQPKI>235
z+Ij=5R{7@&djH)}rqN@kS$TyP;VsG^B{0#doNx%DZORXA0Mo9#wjBfQR2FuE+*c0K
z4)THW`9+w2s7#50$RlMhEh!!=Yv-fyiL!n)ex@GftG6+h=gJ!!L0%~5Xd&6BobV}7
zUMfeFQ*B<q@{cN58c?p+z>8N(YpNL?R4$=g#@C|K0ODt{s|Wh~Ep9OY^|y#yj>Z6s
z#sQE(3llm<e83{O5#|qC?4-LQ$YLaiNeH%xoQi>lSd<n*{gA~>x=IdPyd{Uo5ew!l
z-G8AL9p6JV%;Haqz8|${?Sg28MWqBJ(xQPrVt&kG+-P_hWwEailF=67Ef`^pMaN5!
z;}$YHTyer8n(mP}i(mbL5^s@Dhh-BjUarGHlPtoQq4A`}TFN?~vgn|%OC(#&bqAO+
z#e)9~>}iV#%DALjsK0|^n#HEqu$yl2CKdW-Saf88cvvp30r9l7SPMxn%W*T|Q=p~t
z0PG&Iw3&o4g<2+2g<zN^M?08s%kgud5Me1h4o4#`S5g}Em}SZxSctOxh>{f1M#~?v
zVLrz485M$_wEXQ3JUwIigF8rurB5_8GA+$Th-O)K&jd`lWhuoqD=bZD#aL+>PmzP`
zmPhH`SZnD{A2zvR`85SfZdzJc!<jnEkkJsSw~Wt)NQ33-Y&71ooYM=;MoZ(^cVXhT
zWqlidye7-ih47-;a+4=STP(k(*=w~t{};#|OZ`~Dv|D~hx&98zuzJAUwOmDE?|YUp
zX;A2~l;#8FspaSa^gXkjOGo#5EpG|vdu};x5x5tYiNi67KFi^#beFxf95hk@s^7AK
zzUVMud3QcqUs+D@h5Lh+?>ND=A<K8^nsZX=-h`sFs&XGhTvUf9z^<$6H!5s&Q#I22
zdatVZ2UyytdMf~&yUO1ek{+s$sr1=X<@pE-UMk~%X!KUSwF>j=quN?!1h%j04Amm~
zsg5A^A=|H-O6A7>s!E#D0F_{dVF#*OPN4CCDmV?(7NnZ}zjcx7D|d*5sIF2$*CAE$
zW01qDym!%fMD;#xZ$eeG1sDud-Lr+ka8)b|3rAHODL)pe%I>C2>oJx4U(kqBWl}6A
zT2)ns&KOn3MkvOrmdt|Uan<=2kQ1uGY?z2wU7(L%Ca6B02$4ip@<L2PlB$l9BPUf~
z#sTG&YPtc9$*PYQ!;2JEWGpaGtNzM>NUG`(ZE(|6?~I{u1Ei}0A7D%wD$W$3nX0{X
z<{?W}bP0{wD&JgaoK<}|3FdQD!`;B0Q`yjBD_1p%O6rSLe$RnctWvFm!4g$m4d$s-
z^^|HVuBx^kg-DI6tOo<Urpnra#_OuOQh?Q}!YEB`yrC+-4i|5#uF-?FPE}Y6je1q%
zd7w3@+^EFpmg;ZXVm7MW6VP~Dm2nM{O{yj@pf#&Lp~-JiUH=gxZK@r+(0E7nkdi^|
zs_(1;-J!Z30foD&EAK<(o@y4oTsl>wLLqtIs9Hr~rw6L7beTL<eXsy%U8<v#(b%o(
zq;DTRQf-TY#$(mfRygxib#E5Xo~a&PL0_+`ik=D2Rnu>Syigf@A=0PXOe@Bhs+qwU
zXuql>4+_p!i}s??#p)cLCvvq4JAv7DvogN>FUGXbDwY->?pDDMz<F3je+`44R?f6+
z@UmJ!nPqRQEPA#3SUsPFMqjH>sj|w?YHcCx?zi&xgC&0}&odwaR(qGhQk-?)2N*<x
zb%Yw2N!Gimp5>JF=8147#d^hISV*<5GRh&EZtX%lz6|RL<6-Hn^}2T<T5H|k0R2{L
z{yX%wSzj*!cgOm(P2k$C74(aASkIgYgLkb*P<G;p^<=6C?XjLY50cNV&rSsCv-Y5T
z?@Md!E-)9?CbTCVunv3)FJ4(M(Ni{O(0WWJT8FG}QBBip>-03BIjMKi_3W%3AcHRI
zB&w-!RllZ8t&iF!6WG4$;st;SRqH6Y8K&M7fw3G_|4L8r2z3J$(MPJ6&Ifl){dg)Q
zqtyd+fa#QaZW|Pm)i09hY)H2HRu;^kRR_^wr5ttfY{(R<cin;ABK7lwbaktby@9?G
zb+r=|OVt;?1u0YinFhUb^-;=ER;b_DkH$)Mu?JkctZvv1az#B%hAF91-=YO?wYp#$
zNP{|R1suJlK8TQ#QP!y5zXz6XtFvOD(WEXv0<KxTo(^TTsNZk}X;qKYfV8PUeGSDs
z>K<!w?dn}U;5yVN_rb%v>OVe(`aSh41sXfmV<d3xzS`jlBp;~jsRrbsI&~35y416&
zDxh0^jVdIJkJN+jqxG@+z)>hZQKwKQut$CU6~^>bE%tzWrq-_qOs{&+FVJ|d&fNhI
zU#R<gAkwFHy^Fq=>a5$4>{q`P1#Uonk|N)))H^BZHmFW?q92s|(i^{lGgn1tcU-tc
zbBMSaxiJ$#-8k<XkO|@(>wq21d2IsrA&#2^w8LB<71D%phlXQ<!#N9jVIJi^UITw4
zxOXGqeI&=<0(XoXO{=>o?q&h~+T17`n2+Ihrh<#*zMqMCI?i4C0_rC?YpN`a<BaZI
zXpQHpXgQg{z1IXTkxQnEg(R-`EjV+MD~*PUQ{3r;Fp<oSxC+S>ZUu$APIFg9z@&0+
z0=!S-e%K2xoxA1?lr!A1r5I=iw~MyDncS>NK*{1P&q6Yr)6gdk&T>P>46r#|@Di}+
zxPw#-mCLRF4ld?#E5e|W&n@TyXaV=rdi0&=KA;!o1ulg`=NCDi)>W4{p59-DoEaUL
zDdJvI=&zWooD205Zal4^O1W@KT$XW7GK{R8d*e8`3hsr33b`w}8y(QN%srs8xGUUn
zN)1<W0=?X-x$lNS^eXr7MM&0g+v!fd#(6!5`Rm*avRlh#&_VVa+)+!Q+~hV;IY1p}
zFoM)`@-)mv12_2$26&5erpRz3H!}{Bx48v5RO!&fh1O$)&0IKbXj(Y;_W|0<Dd=cQ
z8}~Uyw(f9tQ{Y-VXGM{d4(>NP1ap_0Lp!K@+>b3#=;VC+VDLU?o(+))T<>!<KIC?u
zhofCw4{iFpIj$2!dc>`M0cRd_wRnx;|03i*$V6ukcZITbPq|lGaL>5Sl+)?u+GyGS
zoIC6WXI^k8n*rL#Eu@nsFS&__K>9hS0(ddN&D#sfSKP15pgzbgse<GXcRUH>ea&r4
zhq@C#>T3{Zei40@-i1Fwbzw$V-iA^XZhRe`3);(1XobW3_{EXn+<7Z1{_x;~=roBZ
zKkXKL^5W}4(C5w1rNat7{J=w4^5xBy7@8j+76Os|yiXMR{Q1voVJUzw%z;QCzbg<P
z9^n1d@b@79VIR04Bk#EtCW3i)D(nj3(<xSYi0_XCIn0lX0q7AvI~@9<yxJZbVf@U^
z@GzWznE}0{d=wReM(`2KU@4M6(TuSi;~)J962-6E3umJFC>wYm!<$hYBbNW_Bv6j?
zi~oS$3EsGp4u!<=>tcZx&;LU8a0&dS<&a6_vnxT8_)wbJlf3vIyg0>|eGbrMet<Gb
zDSR{Kr%&^B^eL27K8Bv_X?)>qj4++w`M=wcpG&Wt4Bl-5P%`=Nlc12r|MxCPHh<C>
z0P|=0cWJ+z!!L@2`E&d~Uf^>1t*fDt$N#(yTs}WYvAY8P{!S>I=l|RQ$qT$}Hs<Lf
zzvO2O?Gm46f?*f(tyCXU#Gj%(VKKk>7!*qQiQ_>^d1oJxGJXOj<;wXtGmV(b3ciXm
zk(K;KsxiOJKl1_16+S-$qp0HF%>q}=_q>TwT;<b$251d`@LRZcjW4o*`gQ(Y0bbPd
zQ`|vr@TMgIyUFi!0jc9Zq$<98{_+g;HSph>0rM8Gqor*lZ#YYz)4t7rcmS<U{4NTE
zHuL+3p|gcwx&T}&f0RC+(8hPiL;nu1oeF2#c{f`1ckq=I_`J(o9)oN5_>^+=b@I8N
zLGM0aPe%zJ@Duw0_K@$SJ$M)YkcD11U-=B=5nqf@zfty>_Y1<M_k_>bgrW8DZ%_d9
zDQ`<FglD{t&Vcvw$2vfs^IFP$z2LWg1cg5SUD{8*<gbQ-^z#$wnJ~ax&4lDDe(gpy
z4)P~Hg4;v<=iwl)`MFo2=OhHGfZ{APYhcglB78;>aaTcK2EW~eH@CyLy}}*JiR=?B
zY5D6e{6wp0523sp*q%ZdUDjU0Qpy{83ui1bY#$+Z0rY$Y>u-VLC;X*``TfFwEl}_m
zLcGx!AmmvAGf>DJ4}}B5Z91NJ&?rPuSR+WNzYdvTp@^c^A;SA|7(66=76(g*g<BMI
zJR$_%f{9QemUi7?!n82-g$sEU962d`O2>*$2}7%(mn;m;he(Qm><DfSp_gJhse(J*
zBWc1%KfrFfu$<P2X9VL)T25vNati-s3TG?fTb2-KgiN;ZJJoZa6*{QsBuALo3ea;x
zdN~wxh13Bk<O$zWbTMDJ^)@UO2;<$Ma9)@`2ACIwaa6^AQMjB0?vhZ@0IpE*d=9W8
z!Jd}X#X^LUwl^ih?Tvsb6;xCjTqXz~!bG_c{suHEgg2IhR0^$s0p_ys1Kj{u1b<&R
zS|zMDfkL%lbcAbHg~^F%tPxV)fciDzq#rC@7h>oasTIB~f#eNg7VRQ$3U_G#Rwpb=
zr}tmIkW+-#2I2T64EvTaoFeIsLi7|^x-G=$A=)GaQ%1E}cuse7i?ARJKD7#0sR+1D
zu-pOH?g&$M0<2vaKMx`u!gBgR&|TsEHjM0^P`e&rox%co65kiTqL9S{;cY8AY4T9W
z9RY(~LaG9t-NL<d=zJu&SAski20p-;o(N{4aIHu9gktAU1;0eteI~TgczcEVYv7&>
zo7O<&h4AVH!1{#A6JY+O&^!v5{eqH;v<HOG>Fmxc;k|JX85BY*>7>b!u<A=#dM(t%
zViZo|+VvQkvpBjMoQpV>R+X+|$v#+e6X(#^8up4oDd6^rAJYx%E^ef~zlT`-2qrv5
zcS;I+iM9gNy~VatK>LWN=mPc?AFP9jpQxbM{eH2Na)U;HaYrW50>lgE&<GU8?La#q
zMpJ74p!lx}jX~lUq3|hKRMHkEL==XBJ0!YnfyiO;)^rT!h<N%tj6PIMwTFjc;;;0C
z2^X_-VeqK<!9Ng*5OWqoBvO3T50PVHKGjo48O5N}a5!3g*B@TQh|6go7Av-lg^A<h
zR}|wsA;!9(FHW@B0R4Dz)F-f;Adbh;DOsYZDu85?Xic}uNwGQ=V5h{-X$_GqA`Xn(
zP^_j@>S<9yZ>3am=K?6CiF1ZSBwaKvqx<2EcxoJ4GsGsk<}$^-chHz61~fo1TU>k)
zqG!dQD0H7AUZ91^IWh1S%;$<@9s@K_TzM4=`C>8ccMC-MT=bn6{~H7K3!)o+QtP7F
z9Ru!?IOk(X7K(xnjYZ;l;|~BW7IXbEv=Y&BF|bR;McIHU6Q5Cvq+C?qLtlk>=}mBz
z;#f*~Ul!NVDfKJjrdCK+iEq)vzFPcV39zeT@pmv^BYw0V<eK=k0~)W3&t|~UTCtbH
zRX4;IYoOc||M`dZe|6&9v|OndKcp=|gZTL*h~5&D{Gi_`o{ER1+v4UKFwrDlv4CQ;
z*!DJjY7r;XBCl0E&VsawX(1Te9ntw2P};?6+6H!r>Cx!BE2dN8{hs(IJ*7Lv;xLf=
zVuF&sjq^Z!{1h?|#Wl2*=n}_N!+f{6o|XiU#GHO`kHrxL^F-W8&(|K&m)0Op#bVlE
zKNGcdu&!5Zr<KKX(NG4rUx<_LgX<ID3J3R6Ori?;e)07h=naU?6M*tcw4O%!zd_NL
zzOgtY>S!zQTFhPt87IvVEnIZgJf>{Ei{=I$1$Wg{y+WUxX3KZ*>7b^C_NzgfTi4MS
ztXWAF+##Al%7q@%1pk7*!<ua(xKPcJFerp+E@VI?T=RhT9!E8k#=)#HLbIt0E=FpK
zoxmQ`$UcWgl%|qOdZINKoZ)wjrj$TqHFXq)J+5h>jqV9e-DHqB%@Ybf$7>elKp{c%
z?i@%aYAo&WGbL#p8K|GsEdLzlPiX?&(3qkL*$jo#8k;>JsYXo*1C2BdPnTD^X2lT5
z8O=Eg*k)*&2H;bsX5IUkuPlwpXE2|wIYsf8vznWqqcKOrP|@=_jU~lKb2Z{#^yO(T
z&qQCo2CH@44w`wiw>z&nuE6{6g60r4Ues)lgoR5QWBYKJDAd&E!Tlo5JUV?{tofK8
z5hWVY4=|;g$NL~!rV*dv_bJzWJq4sfGa?9}m6~tn!u(~;1u}m{<4;@DD$N^-Ak`ZE
zMKoU3uyl>rXzW@cc}=rB5#+ii#TRC4H3i0An7E-~saW);W(~zy>NJOFXI`)Ie+AN@
znMg^&Tbj$u;ZvjLJ6asx*0e+ev`N!X2QZp7?O6bA(af0xpISBcD?!>c<91*ycQhFx
zaHd@oPDfBXG_hS!xT{%6RZjObL0c*R(5X3a5oq@{pNxQ|2bzd&Xnd&YUkB2q>3;^a
zZcP(CkRNGA*+BoX=GbtMCz`YXc-W&!PKRqxHNHz>@R??mHzuf8^ZYEpo@=}pK=Os=
zx3}S8pC*b<61>#hj)Y{tW^5q6{{}Q)jE2lBjp7ra4Qf39gXoZ^R{_!2n&yYF>!j7D
zz(Z&4k{RG!v~SU()Kz=`9dK^i@B`4>t5r1tbf4CN%Fx}lBLdOrp)H{b4o|H!rKP>J
zVT9?eWqYCSqaEH(-v;p2PNlS`pY{m7%=c?W^4nkAL?>JVwDTwq8K`~75h4e)N($W{
z)Fx3nAV|A`Do=v7R&@V_XqP?(Ii%$#WAul$-%N!15$%fWn8Q%*)%SoBrrq}mNVqoU
zV}Kpi76`CsjL`0R0gXuQLOSq#OsgLam?-U*Iw(eKtD3>ZXiF(06sx`RGstmm+gHFo
zp=Eyo7pLtS51-<-&Hn*3K|Ajxz!J4#6ue5(UZD5TN$q1=Bc9S0E1;09eegY?Q?%@M
zh@3WRJ%?dtQ?;+C1T;+>`5!vdwOi<^cSd`DHS{yITXhi0)K<BmF-seH7hJZsiBi^Q
zwM{;l;2iCIIu3kJJL(>s$<=P%2ZMRqm6Qd^*ScRqV}W)g&DweGq)ZsPpdCyCSfSQf
zco}SwwtWsnOSEb9k+f3nO^PL#X|-3OSgw6kkD*m)wI89cQoHOISh}purj_3n?K~fd
zRB4;3^0ZpJkFNErT2m`D)@b(}2Dzr4O)-+|+Aw;z)oO22iOdac-Y%fr)CL+&!PaRH
z)Z(|O*BTCCFb!It`Dkp^uG@;n+u9;aC^l)^Db?PrJ+Ta=MeBVT*sa=A@qlU54z*(t
zceD%j@S<HiK*913?GIFZcUN0u4ep-yLrPY4Y9CTw>Atpi8q^<X-}#%?pAWTGSs-27
zmA^x@TU$bF>PK3s4aj5dUfT5cXcH-S{8Z~k3&3Yu7YQ1BwGni&J=f|fUi(5j_z3>?
zY3I=o^HRHywkQ4C+Xui6Xfw{i{44FnR&aybolBuNq@6oN@4wgDC2Cl5(sivwtFx|>
zRu3+^zZjso>U{q~pPR0iK5V;J_mDo0u}}AC5e&NPrqn~yLzhR7Bv0MfU&El6t|lIh
z-nv~6Fc&^LH6?U?b&E$p!B5xQjlTW5+5g)X>5|K&xc>rl|C$3kP<Qq&G!Ez<Pl1aE
zbw#v{4br{c55I$TO~W7(qBB_r6NhxZRH$=UC#SO|M|AJ41_{-DLX{(7x<0zt!gUqj
z;+H(CYog#rgl;zN2qJYp6oELV%liS1QM%+AaC=#_Zqj_PF}jOXUl^<Vi^g<Zmq2yG
zCv;0?n36ahpA5V4y0u?`OVBB=gCy!+&}t`1mk|VVQdeXPa!OZZhQ4Io#E|7hIL4p9
z3XZ1h7JmY;GrGz(;4*XtRLhg83(Ew_(nVRqdbaK!ox?b*J8~Rj$<dYN0Og#nDHCJK
z)m^0MPoD0AEe4UV%cEoI1-b}Yt)JHo&}RRFuAu<abWvwZ|69)`-G&H|LS2C|1D!=W
zR|k+{-T7+Bl<2+*#yCrLBa>mbOcxUgFUoaJH(|a)cXSQ7O5H9Gh+NjW6~WRKT}L7G
zs&w8Xp-`<G9|dQw>Qd=kT#YV)9?REsXNJSzb)A&~>b1Hb=^)<?UB-{};=8FcrHbe}
zot(;}>vc~kQPQAW{4Gq}(n;w&QKPPfGS9blKhmnONvHl0lFhn<^b@w|MomIvtM2q`
zG`8t>&W59RbRi>PzFjx*OH9HOU1L6c>d|dI35BP+1C$ARri=2R<XW%p+jY=*t{b-+
z<b`hF3s~yYeM&pMm%7?EaQ(VX5@-zQDyX*em2TV(jCW9XhW1}Wx{ofQ@1)I_93)TK
z48tWWOR@2q4fRx;??$07&Bp5_yhyiET*k=G*nD*ojTttM*y0&wSvHoL@cXPyCI#zq
zZ2VjxlWWsRsh~WY`IO7dw<)ltU)1Izy-v>C>~I6x1)IfG#&Xf-U_Qttn?|~F3vHa|
zK)u+effg1eHm`EwOsUPUBOy|5vwS}EDs0N=+()I2>I*a)FWY=c^$}NWv=l6_vN`w_
zW~kbx_BuMR+8m*nYK_e(TGL*$SwLR^ylzv_0It@??mf7D!zP3>BR6fz&Y-c*CYyH6
z^)~UBpx0pYCQa-uo5Ow>M59goPDtLi38xi#lMTNEjm<`zKi`K_?KT4CH164it%Yx$
zHot2jdf!HI8!!)S$|<=2&}JIlR9!Z!==&tyHvfh};gQX$wUB&bb7CscdTb)Y;Kfs$
zJ##^x*(}vTz1L=c4n&^Y_|Y+_7dCNkL9);0FIO0PX=D72irM;Y#1eQhU~_0JT3^}x
zc^M`KZ4#*zV#ucFEhxUWIXnw6PWr#7D9u^Vk3pY{J~<TXuKGO`F>%v>K`+d``nCNK
z*{4t63ru(Y&<yl>=(kgD&Qsqu24nHk&%Ox@-uiUo3AFm?*H9kKSN|m~tNirok<j0-
zpH&A%fBgX`fClPQs2=iw{>*wP9Mr#}q(YE>^G=uu)|cGJZx^Cx4nX9P-u?}c!+NtP
zuyjN}iHi0@^`|J&5vDiY4!v-_ih_Jc^{NRJ#fi{=O;N>2eLB6pkLmkIKru@Hq6gS9
z`gw(zuUP%idW`qDUP-CC6Z*TqVoKulM=9`_pf7s{y(Ik}dU~AHzvN*lS^ppXCx|Kf
zQU5{Yw0?O7?565n=vGP7-=$4=x_<HlD(=eAkE1|Qras*bomu+r^r@O`eFz1X&+5J1
z0GgxUd;lJv(+^R2JXaq=v7|hG1l`;D`lttJEYLrtuK=9auW^UL3;JbS0CrKId;*e}
z^x-GaSf~$t2ZJcm|3lYBvHl`TV~nyA{XAM1mFhbw#8R#gvw}v2etRf1D)kl$xOQ0|
zK|#$c`soy=uF{X<F$vZBEmRlSuQw@yC3oBI7NB_A?xSd?m+cup^o7{EP?5$F+jqNw
z8E$)rqSTSL4O9agZQHj5lEygOfhx4d+m7mhXoBs>w2?`){aOx7Nw#63kU434elEN?
zWgAa#*ks$cexsSS?JWSzY1^^1ZcVlASOm#5+hm&VbXyB5Dm!DlY8o&zZOwMk#M-vd
z1NDNfk~TRPZS$yN<ciU@j!M3&Z2KNTwAyyuudsX7*78^QRAW2I0nS{r{bwD9cHLH>
zkZ!H5^*zAcupLN;{!QC&wn4AXR(BE3)Y~QzN`vj&24LQ@jiIBjjkYUa0p+%BYyuja
zY`Z^zUbAh`did00Yur<Y&Q{x-v^2hBdt49fcH2*Lf#zzLAcKsXT^POY_u4f$LUErR
zLnn2@?6$0dUbtQKd2mPV{-RZTgxyNY8%Eky%|YKWyQKdmbnT3^BaX5AgWe;@?UE~j
zl57{KgM}2kGGiacd)n>?5uK@a+<xe%+2zwqCfzRKCb%<pXa0Z}8Fn#raz5W~1m*1u
z?CgWlciwLDhaly4m#A2{!p?aqNTr=KB^oc=nNY&K%I;@Mu3fcTNSnwSyI<)n#cjKJ
zaqzIoZhkFA=bP<*pj1JN-Q1AvmvP?WJxZKExBHArX<yj=@f<VLXIJctU*x6TZ}dPO
zu&bi0`;}c9g$@SoK6oG8klknhD`mHTkAfS{_UZQ_>0-ZoCG5J|KlFraZuXDXgY30;
zyNluOv;TB6JoK<{qAi-IeN#R9yzCo|`{2H}eK9^VBlEGJHV7DB`|mfxlAryvRp9p9
zpQjg4fc?4S&=0h4uR-4ddpXru9<+Z+*Kv^jLk4KU_FsGoun_wu3S}L#FZdgMN9;Q&
z_#0~f+d3$O+ee*1-%<OU6p%h{FZ<vBMRme{ks~a{+i#>xAi@6eXXs3_Z=DG4l>Knp
z^(Na_Qq6vfeGx4ePTOyz&|9kglHmYNv%f?4eY$;o2|PSwKc33`GVEvOfMnX|?gm(v
zy~B1)Lbm-VYc%HA@2-JQm+bAw(tfkh-kfUDi|ilLk@;eKb9!2r*z@&hEVZ9QS3;Tn
zW?IKp*ypVSOr?Eq3i>YFFRMdet-b#;kQ?@CA;503Z>L&~W_zoT;aZD*JZ+j=?b#m8
zMVtLz3I*S>fAS3K?e_03pm=MC{YVe!-?d*y_t-uAZR4QdY5(3YXuNM<Km`g9?C(8<
z{zLoSd*Frtuv>j}I1YbC_j$s~J9p{Meect7_~y#IIUK}|xt));y^PQQHo?q>N+`NB
zNA{x6gPDB<x}Ho0UNS};$(rm18{W*BmC`p%LYYr!*?xw(mkU=j7%lDZGnt<G@GXm}
zqN^sG`GG#|dX{;g%Cd5pB2S2%WA@jA<T5oj(92^^ZiK`6%y@dB7cfqgOF7TX_zWT!
z7|&pE7a0@E<{2+Be^LgmoJqjdYI2ter{}X9JMAg-_p+aig28=kpCv@x+3qN4c(DIm
zhKMIyMx}LL>}Yx+c(a=V(dfe(r$fP)9a#fOKXx;H{Bl1le-lIUXFu0t^a1Qg@$e#$
zb-^WX5@BSMDlzP9tgc1=hRHt3H}e4FAzAw&^M*-)<oy-E4wft*3x`7`C+RSDiez(#
z1UB&J^XKLGd(ux-%=G2=F%X^d&ncLg_RA$$Sh9`EURIu#;qMJ!6hd;xW4aa{^<Vt&
zNBFNEBlI>hH|GL1lS!hh?gF#z-T(j7^5<#QJ0z(b2ivbDNpHe0C+Syo;rUBVJ_Klh
zbf*uvW2SGUKsCy=k1`U`rX4=Oi!rUHs9Lisxg8>RRef|;q+7LT1^Rkb5AH(pl}h~+
z<-1+2=6wWry{sBMAQND9m?CzEtd{Ho7hyH~KZqW;`h+SyPFSt^9A3m(aoYeBZ?%ge
z-U(J~Xn~t(^~)a^R+81^27sNkk`ve|t64rE$yOVVV{+216t0lWv5Gzpa>2@FHNcFe
zRzFhUugdDk3h38ag=o=PZ`F4eFb!6%_rTq<8aW>38?EfNf^=JrS_sKUR`s{QJ+>;P
zDB=?<Ipw5#td=Ch;8UxG6w`QSRXrPad#%>K1BK^Sj}rj)!YXqoMDRt>G??!<TJ_MA
zY``k_Ia*&?9it%ipw%>57!O%Bn*rvvRrmy8J6Q)-f;d}`rwV5m>xW0cxm#cO9xxu(
zgY;8)T5s`&o|knb2TR`8uBPAutT#~6OrUksUl`{BYwH{MwGLVv&ckewwekBFpv74K
zP)IXteS}`@3D)1$LF2S_jV;WlTfgOq5$0Iubwl!&b-^U`HCpEqXp?m_<;k0^ZMT55
zS#LTBg*(>6#=_D|Yu6XJbez-+G%)C+uK5WDebt{m205(WK}m~9_3y^H@cV?iPm9)5
z>i6mV<{9<HKVj*ddd&v-bWweXl6Yn6Z@vU}wR+B1ki4lrp8~E)J&dZgJJerMsJctt
z@dxZaQ!5X`nF00eSehr!sRG243#G)97q^K5B;K6n2vB^u-5o}_=*!K^hK3)vmfm9f
zxu1-fJ%8?>UT^_iS1LpTx%>e*bAVg^J^Vh%^}a@55I1@(^ny7B4K0N0?SkGRPNa&%
z7%q$IRARZ@CMX=|hEci83GOR8LJ`O990tjFZi!5Z=YImH+6?y-xhWq)G>Ln15#%H%
z`wcRuxOO_}p3D^{V`wSd4vHO}=Ki2PcPf`B!lyJ&ErEw;IL$FgW^k`5Czi<_qANd(
zn?~v9Y%a(j<Sf_y3U23c@w7=l$7N%jMk?>2V+(oQO4>{2b8~jUQURCs4Mfj#feEm5
zft%EX#*17C73W^!hQeX6iVI1_m~L?M-GF_Yn-dF#c5cTgc=(XJK?PG!xdJCN4seBw
z0sV^0X@uk;_xV()4{>W-(Pw<kt@41V6aPJZ6T^qEQ$fa;XDJ%t#~)q>nf-h@9q;w$
zS5OIg0RMva8VC5-<mf?uGo6<U;{Tfo^<X~bXOIv+$Q0xd-_!<jjIW|XpeWuf3S2aw
zCj&|h|2Dl+VvW4d1Hc^T!}H+934Z$!xH$e}76ude!>7R|@~0{3pTq}zhj}{5zkeR)
zPw|fon3-hW@gYD{_<H&;8cy>Ys{neI-=f8MbNEDh8t3s(CIdR3-%X^9-@Oqi<@}=C
zkgVj5HFRL^GQWzd6mIab7684;XH%NLo}YFa`VD+F-Kux^-`<Ba?R+4u<~n#Y3e?}_
zH$8{QJ$~yU_}j@}rbx$q{;evI2mHrm{vp4h3wmArB3CGM^UYQ;^oVy^2rnM<*2ZM8
zPx!hQnC>3l)D<vK`QIoW-OEqf0*&W<Ic4Zx@bL@5_3^(@X8a{TavVn3&s$j0@5?)`
zfr(dqtsBT7Uws2$L;Ujsn0U>vriHPSAm0o<XW?}!L|lYLR59-=_)F;ia})O0qSIGc
zGZn3V!p~Z0>=zbSLeyWFz87eL!bwW09}vb+`2C=eKN5}x36E*F8YQf!kXN+uf<$73
z@J4X4!bguWh~q*_HZV^Js;S`OgxU0i#tRoZpqC&7R!~SLQ78^TXOeI`9^|Aj`#zjG
zCD?Ug_L7Bq%B80WFX<6}T3B!lB58tgAwbiGZ#%)A5pK|nHbbb61eYm%<%%I?3DZa~
zTkuSVqi2QV6uit4;_J|NPI&Yt8gqp&@i`(RY8EmnPoFO=pkK5=$Xp5+&kJimM&kvc
z>OE*&5&k>|^HoBE3;M1KA=z-hMwmMWjkQAlFo@g`dgv+8B`iqCbae~vUw{k<9(2(4
zl`zzgnHdz0{t632LJqz`jQo1EC)ABj;>7phsk8X$O1SSL?!{Uf3HDi3{pBW(rBg9`
z#b*>E+$T=`5q<9B%IQG!5Z`+P!}b)vi-5Y9=p7GGAF-Au&sSVE42^!``pwYWFS=8K
znZMXG6@3Asqyx}_Vml=y4;V#DTeKb&zoCqNkhqK1?!ls26u1!aydOXhiA5Kne^`9D
z0*yyR=Kx@biY%2p#EF@7STSDQzY>iJ;>Zo)62*~`a4kvv*9p)k#it)aJz2cp0J|yT
zk7lrYTHHrF(Nxjc)&w?9?4xSabn#*XNaUEDKQO}7F`FqGo;K!T3t&9Pe*Y&--2AXe
zfQgn5$6mwC3{Lox65T@+cAi0F;Kb9k$2m07pB`6-Cr+VPPUys4r2tEx7$kw@rHR2*
z!&x|S+5(7FOjH=@v2%A~AeQ2?xKFL0QB^YjZ06{a+#;cx;omR)0L?$Xw}%&7Uku^z
z9mDIOy|d{U@OOPcCp4Ux)zg6M%-re*=fcd0g@70H@0&pJX0}n8p)a$57NtQ<6CKnD
zX3lNJP>&j!%cp@7!SqO=AIVIo7jYc(1x5SfneVCSDS>I-fVoO!d_M<h8go3B#=}I@
zrE!iKz6V?`^J)r69+UP6bCl1lp`wXW<~vGDmoZ;H0%kcgu@eR>m{X1Dt7U4(0_+B3
z^q`pKO=dm4pz0XoezdkQV<>ym$^=msvW@waLV$OejbFmUb|x|ypdCyACFkxkD+bVa
zkBJrm+R1D_i@qmJt`#tQn0UJNpE6MtAbZA)q0Ct?W7UBv8DzFm#$br?Fn$a6HN%!e
z!--u$?`3DU^g0?{*c@7_xU$%L(T?B}!R%$NY0tHfjiW89J8PB(5f66FFTnO>&8Q;R
zi>){X;?3Hwf}{^CP^GCa`|BY5^<x)L2iebt90&1dk58q1X8;>M4QwDAKud-LY|k*D
z9b|V;1a=TR_HBp+vr4KI2w{V%*7*=S>SvfZ%qC5Pqes|vRM{TNN>9P3F!t+tn8R?k
zgyK#|+0SP|?>Os9S>_Y$f@V0A%ua~HSW?)NCA9xM&BiF9n98;!qV+8MnF(Za*pDcZ
zagL2!513qb*59z3$2L+xzlfc?9eu@YWgPTM*cJ+Om9pFag?bqqw;ZmOv%BdSU<Et5
z80H&TFC|cJv11ZI8reVt^lq~Ua4g&?Yhm|3h2kC7^E+s?vok`V-@&$w$0+Wy_@pg<
zUpDd!xZlaHpcl-2R;fnc1Geoh`kW*y+@Rnt`JN7V`AIf?0)s)4B|o4sOcHJngVB<&
zHp4=qL_+nsNfPfAkdu<{=#n*_l6Witn=C1$9AS#Y{2nyUNnW?ZM6RS-iN-uh^;o!;
zFPZreT!CcK|6+fV&XF*GQF4C)6fQ}QQLv&=@;CijMUs)U7cZ6wI{{rHN$!ODHHrOA
zc+nu~r#gpLNfVv-=rl@{|Dg4;<U%PlUPz)T6gMPUy&f9-q_dMT-R{zMT8(%}SN#gk
zQ`+$mCcLC}v|aa>{zf5QAL-6T;0{US<iI{Gok`D)BhruYERlsu+cp9$O!^Hajl!ib
zR-*B!bhjhCkCYk@(IeuRH1!c+qNF>h5IS1gG6WJMT}lDlSZUx}bO}l4?}K8hbeIPI
zW=q#QfD}mQ{|ujsr5DaZ{jya02|%w)|DlWgmNZZeg*NE~Yp6ev3Zo$MP<pQq3SH7?
zrXbzYB}UqHJ(8B~zz82p-=%7rC(?!c0MjG=;%Dd&Np<t!#cSyf7Ct%2EMq~OWtSSE
z;3Avn4QyB0og65*$)-8O#9rCU5=@Z0?0Y(@;31QDLDEyUlFnp!$!>lG;*Gc&6ntc-
zUFZq#E9*H66MnMkR2CK@<ANY_NVf9|xWlsPS%5hrOC*OwWqyZgE@fJZ`-aOl(`qIH
z+dfD}%0_Mh$}!ozXh=rMj^x3aXxY<XI1?lLVI)vuWnnMDosva9g-Eh2V+!RvQ)EMn
z(Ro_7lIr|YWejDv(`1c%U?N=>Q4W|hvV?RvoGIHd8Pk;|bEkb}woE91-LtZeR@lvv
zwJgNUoRb}i1X!+Y`#Ln{$=>(}D8;f(de|+I{gerXQd!|sh?L3JhST>p%4N?fu3sUW
zNQ;X~S!NStF3Z@z@f%)|=_x5$EmJ=RcUATm6++g?^6vocn(TMVa9)=!Yz9{=8&d}L
z8?qmNhQBvu+YK0Dovhax&>b>+O1s>ZJ)Q)xdoqUB*qyQw=P?%JeOV7B$sfqJ@xbnq
zg{_5tx9rhTh(3~er9kGf?0dSrp2!~GgJh5F_Y~NDEh`8^qmzjw2(CGsyrxjAiwS!a
z*sdlw{n6)U^3PPL?=^`@gNN=W_dkN9he_)Ypgm0*7J~CKnl#Zu+}k8^96)_c5_W_0
zH4*Kgal~ZWFu;VGY@wAym`UR!h=iL|(rtLu<lVX8B1~c_Bpqo|N%ir^Ox&X3VYG?%
z3b12Le$jx7HAy@Gu;V75u7=$cCMI8^FV1AvV@z|riSdsVC?=SAG(zTrN%dO%uoq2~
zl+39x@h^e<w@tDn;F?TE(6u^fa;O$|<4k9s2HGXlI2F(eO@G;s##^SP6#Qs1Jr@Io
z`=;-I0N0+F`kjMbpXn{Cetl^gK+z{pvy)X&@G_fdG>7?vW&))JBFxMwK6lz|w*oTf
z%#y0%%q6p8do<oM+epW2o|q*i0n}YyMyZ{H@+4XyM9FvAz>5_59*U%&k^lBKL`vlw
zX$e{;?_B^rZ$-2n8vPXM2f^)E6!PHw6{<HV_z|dxnE{6nC|YiyGe{9ZmtL^qr$P9A
zM3LnK(NKlcc!-24v<f(SRB@T=w<8pK`VvXB!a$GG7)9_{=*22#(XuE`F=zqxM1_7k
z`tX5(Zm6GDJURh?(-bkw(U-2s{EyCiWGJ@811(eWnF{8!6uZMAldb5Z1!=jW?j4Xy
z#as25gepY~J;Z7h>x*FGy5e10bly<-I>C!N#g~g=>6T)8CmLH6ISfYTVm^|pq}<F`
zH$Y*Z`5P2^_b@lxk3smE+xXD^=Wnh_f{BCXGbj}tY~F1K{ln&~={o~q<~0&}apR9r
z;)uVOG*|&>X$$SQmPOH%?MHD2{=NJs3O}vzp(@vvlV{-HKXso$`>H)f09}3QG}_lR
z(_&+-4;^^@`Q=pjweGt~2m#1`Ntg^@e|?e<H`X`O)^)@BZ4fd<9>8dKDCpGt&U^GJ
zmR<Su0(b163($W8XtA|NIT`={PeTcJ<M{vZZ)ZkDAv71pBnZTnF{SDvU*;th4frwR
z=<v~gCYowz{FyrubWI;-yuN|V5hl<9=%LK@^%!X~Gu#(mWirDlD4)-4xsE{<Gk?-5
z_zE)v<^TUTEzYCyj|kSO1*Rj}<Rai5W2aJvGm4#%1=VPFc_$o=W8Hs4V?6r@efRMc
z8}t|^lUbushcTwG@gJb`47<k`Tn5Xn2FYX>MS*0oiBzte%Pyc3l6kCR3{2#+FDcS?
ziM9R{<_p<$s;equ*Ed44oLv|L6BVrUa41x>J@gj6%09UP&uiH2v}U@-?jH-0I(CJT
zYUAqJlvJ<{?EP=SHM39cz_qZeXw}imeuWPZ%i7rPdg$L_f4&U6ooo$7LhrLBR7m-V
z-B*gnXYBMyDD<)qD7XKd-AxzF0Bi9X^qeFE^k91`k35QL>{UGOW6+5|#v$eddd9wH
zex>PgV*M7t1!r~&mFc*!rKIf2eo+Z)ZmfSk$X?df7Jd8J>s0IK&Mw`B`S4&rJ_~hE
z_IVomyx2K(UwgA#UjWR9^;-s`zHI;hzO=xmy@b8}>^M3KaoEW26rgy7{rwEQ31vrI
zLgxuKfrVl`yR297e{KpJXdk@v{hb)uGB>(=f9$61^71rm*jurmc1tUJqk;6(hzCGe
z^{)#5UR|;cF0Kiqg4DG&{*eE<d<KBmc~SD}7l(SPxBImz3?1vkXjl5%LJGBP*!DRf
zHkBNK+SX~aVC?TZ+t9xA7kV}Bx-*p~gPF1n9_?j5rvmMLO#Ct$6f^KW4Ei%+?GO)O
z=6(bx0-3Krg+eGZol2a;n8VNEaX2HRJ#7SI+~thcD5ifVU}6~q2NK7uGlPC2Gm+Nb
zr<jFQO?id!qDO8Olah}SR5OMqSh~u@y@K5urh6y2n@sd{s5dgLw5Mui5;H;WGX*O2
z^)fSRq1Vs6ZiUDo<1igyubI9HUjy5j-TgjbBG~9Cv}UjY$aDPP-F1>G$g-IYpFrs>
zvv?1D&0(@aobMxZcuvGX@|oi&pjyCuMBD08#+J5`Wz2yJD3mj|=xV57mW_q!N@fK$
zUS?k0g~%1Ap7#A!OgV)C+L)gy9(9Mgwgy}~6SxSN-OQg9qI<*~rAh5$zNW|fOJ?H$
zz+BkH#%#Fe%3h(>yBnLh2O7RC?*ih-uGj>-``O%9h#q2>oB=t^4y?s&9%1JXfJC!v
zsTLvzc^)XlvI<(t9A{@ywSF?|NzcO+RzlgbY<3G31fOL$(*g7x*1HYdIac9rgg1rk
zX)5<EViRehUd+1hgxwNc%TTOlPi_JBRrar$(5PWQ_!c9)#{Nw^nMQUkeIxBQ`=Atk
zO>8n<o6T(3YxK3Shv}#Ub~%5e?*Z#c?}LYI8pVUU*jH33*UcvWODBaNu|Lm-%wx8f
za$ir_AS#0DVV_6Cr>E>Zdf+@`KcU*5UN-PU^gU<a35IJg*!n&=+Q)A8hTAXM(^TWx
z&!#^DH^5$`5ZfzOPLb3>c4-z+d?ed@p>RYpIskpgB!T<r%@rrnErU0wB?(7BP>Hu2
zp4LffDG1Uf`N|QE&eDhb0U9o?q|jcnboER)Qy_ia0njVb*ez(hE&cgd@>go<3-tl%
zFq|Iw-^EuY(^KB8UbgT(5|b5DolLXrGNt?5WUt22MxaABAq4pMWo<1m+AZTLSKK2T
z9|+MGvK4>A>3&)3yWn2Sl0&9<F``lV4Eif3b_4pSU=doY3uxiI)-DTXH!bnN05`XM
zgufkf4?^9rrx*X;u|*4voeq`w+li?whx^XV$1(5=AC{z~mKWpa5B)&qHPsy*V0_xq
z7|Oip1Q*5_SEDb6K_w`rEtXlPgV~cz??yO#irM=OM3b4GZh&Sol0i6=#e7Du!fZxO
zIn}d_IRm>nOq&X>oMYbc2baru6agiV>2iWdK6BU{TmjQ|73$}iAL+G!fnk$i_aamE
zJD@KyqnE>;v5?t7C6q<Xd`esvGk+N%TEaX$1kh6E<qVKA##;(f&V1kj&<ds~2zD!(
zWk-N^nTgtq#w$$8W$0Bgrnk^o&5Y53yUGMN!<l-fEEY4@!0e?%Mz@$5AHYx}vx%0$
zw~fq-H-Of}q-8<oF5~b8xO>dV-H_>IG@;PH&+N~~lssVG`2*MwnaKA5)5VOUv}ZTN
z(G8!%u5txh25UyojV$)_=Ri5jZm011Io350k_GGvUo>81uTqss5xby+2FMy?pF**M
zEu@I*74|HxCu`W5ze1y)UFrduHg+%st~p5#y2;UsKY}xjHH`hs86=$Ty#Upt2wOlk
zg3YUea3s5CDV#jUPC5*mQEZqy)S}rFZSXFJtr-EySoTxA&1A;otYi+XoM1oN4aGRN
z_%Sr%*=8GPB(OD~0Xva>^bSOmST~A7oMiVGK=Kr8(hV+|{dXiRrLbeDNa-{i=z+de
z)>DZeC6oPr3%COI)&&?m&t|UxW+}UxYAnjwyeDv`+{n5=g-iuoIv*O>*(gt#uVve5
zm3D*8s04SDH7$Z-Gh6lzoM~Z0Xg}S`-bc6wlauKMa)+HtG52=1XF2*hSXVFT-DRDs
z;nO{~YYRN=WY7K%l>2Nm#eyHOgVq3h$Qrxpq1?q*je}@6TT+G2N9_OpOTriId|JQu
zv4=C@@Jn|7aaihSFHpQ>fYrSLe_yfXO%NGm4=e>4V!wz*-#*E<DVQ#Ii510+_Di~-
zLC;@u`!^^Yl02j1+sF|;0e4I?!AQZIC`phTG!i7=Qu;DcvdamhNR#ZO)JnSKa4$s9
zNveWDawYB*_bZhAQHQ}4Ny4WByI5j#3X)Y4r?DW_l2LB(_o^i4K76W?7}rAbnk4xT
z^j(+CoQ=L($?{;By&)OQpf&hS$qyGn>Lfc3LZ)6)zY)$fNbXnx`<7&uC4x7Nl1X>q
z_if21v>t1c{7$d!W{C@)viKnBFLbltksPG7WxM1IZ5lfy!x~`zu4Dr3Ywt_KXaV#<
z@{bCA4<)l|A=xF7rP79{Te9^zV4g_Mt^?_jc&-EXQ_0+KKn5itfxvc>GD>JTOZ(pd
zagp-BpwCt6;*35w>7|J<u~+)~6b9-c_5A?edrJF%g7-esi445(mHu4>^M2CXbOr90
zT2if_zqHnao`3Pu;S}#klXhH&#yRO1R4{N!y6g;ODx{H@(D*>QD-a?>vVR}Lyobq%
z=|J-_IZA~WekNQsM1oBwHv{{K$w)fV7iyB~1}@CxV+uQlo6O1qIcg$217@U2*=YD1
zWn#S!hKw;LHatL&n{)|Kj5i5Bfz||*eQyFZ(Ih?b|Mhkq4pALje`oIQ-CcGUHxZ4|
zr(zd<uz(1PXf&cx1Utqk7C=;#7K+%{0s@K%iVlbcv7w-%B5Q+S!)UO?-Ydq2Vuy$(
z?|1n855AWN?4EnhoH~1V%9)u9%JStiFCe%>UU(W|?~==DR#6~(RRHXkN6!B;cDA`V
z8O$Sl(3I?_BpX;9^;<JskM@azpMKGFCVGt78$4rU2IGBVRW&`}W>N-aUng&kg0|o}
zv_CHLxeo-QHqwrZ=pHmOh}pFs@6(1pMo_W-6xysDTDFX1JN`{|&*ol*xuq;W3NfUx
z`}Q!kj6J4GPi3>|<YO8;(HMbcGA*UCRx=&VpR-thGc`$T*q`sHo><5;s4ie(WzcP5
zezYoH%qnS&e2nc&1~|nI(gf=q>pKA2E;E-?@bM;FJ_XnVcCrS}JZIh?LHxij)`!k{
zyhCRgOyi}rdboi{rE$pP&nC+Wgj6#NT?f5stn53;X0mawAiJ7X^@Gn@>}C&uHEg#V
z1U9j)KH%KUwo>=AgDqJM^*dR!!w}fTc2IX+z^2ji!+w_557+_rl1@<^WL~s?`WR!h
zW8gTu{2sxTvmVr8oWX$G1UIg*A1IS{mA&zXw!3V0A+URFZz3w^KC9h_2p%xEVCc@{
zKBFLz&*R_IEx{iLLibKSv;v&F_$wPIE#Sd}LEO#jQ>(p)pI?T^e&b~p2;Ak(x<P!s
zBxw0GTe@S8Md1eN<0Y8Lk!*FayHUDD8<RFkGY6w=vlQ<P!7b9o1t4yfcFq6`hFV<^
z;Wp_;8vNZZHK9e-Wy%w@{~%S_hvtN7N}2lE<w}<f__RWKl`@s-$}D=i&`PBTHOZ@#
zs*`3=h4M@rP&1V8UxAvbd`1suU#%<~1G`yDjS;%z<+YP2dijS)*xf0YbON?l&ZH4}
zk$m0>CicsT9Ci=OZhOH}A`hb}P^lcS9GpkxMoq!_L3TO>&SbS+7^*8@?cI{vpOb2v
za@aksR%F79%jz*Wl~8w!Jmn=c|3T+)6kfjO_ozF6&$n%d@SnVx5=jYCgNI+XKiMoE
z2!p+oi%}y3HaEq!cL{Av_gP^F%E0NfVPjC@QK%SPy9_=J$)QIonTL991=DDsiBRfi
zUk~qNzNJOHvG@K4>$oR}K^cEy2psSqPA7V&baTh`R1aFck17g8RMEE%fM<3j4LRrJ
z(C+Vew$Kg5i`a1Lof238t#~D}7BrnoV%uo3CZ9Q%gC7UH6KDnLAX`jpT%~LQ<x<Mn
zw!I*hGpE)77g!$E&o!1ylfpYJzY5qR=BNW!$zJq9r0?0Z-y!#zb!myRh5T$U$R+Xl
zv%ZX2Y?A1BT%YZ&Q4@XF()=+7izOHnGqW$<0X1wd{U?%ImQSY#KQWvWq3Pf=I+Zhz
zPxJ<HAwOaZ&N!Y;hlvvSl@wS?<TL4^!z*~=5ok{5jp<oEJ9w`cV8#5-BgOxHkmvZ$
zTu`oYpDd`j&VPCgg*W*17S#UV<f~>u>J~rXfx<ud%|T#&%p=@@J>wm&!msCiZ{2PM
zUQDy&DsD#!kw5v<0Z{*uJ5!Q%v1GP^Un$b4V(4Bj^`3(u)1|>#sPdIk>+im_(G8yW
zNAX+sF$s#^G3V!$n0U|nro!e2He?r6RI|TF0n{*gOI_F=;dNoZr<*gGTY5q7Qhwtm
zOt0kn%Mf41FVIX$aCaiE=Zk1TG@HMs(dq`CMfH@!Jt=9somaU-XC5!Wqg~L3#1_&X
z^g<qI4W51c*x%qO<{g>?E8&$&*e&A^YM|yMZ@U_GbdGP~kU!76(h|%KK9M@!oBUTg
z4tk4Eq2&5)9!gXAJG}iNl-=dk(;#<`n`n9aKJQ3bw+H-AV}OUe9-fkF#su-;&xrml
zpM4479j~TA$a{X{7YKgfUbL83!~4_f!$)3}j?ikk5A_xcrA8ibElz6e43=z3K^e3>
zDP9A)U!-6clwFk~3?SZ>Y-+*sLMlUs6OSyvHUwp#rGiShZH`ygY=SpJ88Qe;^OVUx
zz)F;p?t%53vV9f&eyHSSV69fZYzx<xs9Kx^=StQ0wDz5)ipqyiIjY^X*Em<zaS4cP
z<i?a0StsA4yz+YaIGvElmYb;|w@vOxBa=M&3GJWBH_QE~?b|6or<P&2Y)9)+MRKz-
z@WLYdhNCVI$OD$ci$n4c9UyU7j_nQCO5~XzVX#zgO~c?La&$|GACuR*Lj1V=xe4S>
z$R!g&JSE?}0)aDfn;&8RtbBGfoH-{qq>axPW%KkSUs}5#QfQRk&-zd3>z`x?1zttp
zLVm!BKv2BhR=@|J3-k>hIClqR2OX24c5uXNNDa{z!r!5*Xv8>ddPDdy{1bWUd!hr3
zjc7+Z4S$?P%h)5ACxP>)s6U`#lok&dM%%Y59IE|hKSA->7R}-0xa@DBXuRzUQ2Y%t
zt^+g~sL;T*>!E1Ek>^kmR6%}E-020%q#-%Do_v~Cnu9yF1?QCgU2r{hbrDKKT9(4a
z&<h2ihgBT_CA|A^Sc#bQiV|)=AA1d7B2#FMF{->X3Sv9>;d<6lFVN?+SU&`k$m)-V
zl2V3E_ArG%UBic{oYp}HzI?Nr|LhKimgRR~rOlz=V8!86D|qg_aSv3wE~DW`@2B)x
z_nkpg>ybyQp~cU<h;p=JR{sJd=mKSEC)UucC1U+NRLak(k+`0|HVrCfICRAOT>Ch9
z70>$i1X#u*XiGyXOXvnHlYQz0^&8pAMsPomz1;_FFDuT5UkBMk2M`aj0o3>(W^41{
zLNR;gVuqEI>;Mg<F_j(*)+;O^424&j+8eADtRI7kY<{0+;<>zw5}=TKbOCW6e?#fM
zB0f4B0v2ADjvz|;MfwL9cX(Abg1O5h+Cp`vq#q8|t0k{Yh-XQGbT)UBw5%~bU}v*b
zLnl$UNYnRY&vBj<>0+gj3#4M2nw*vX^(!RKNmU&nab9Y?2-qd*+t&!~vh+QDXRb)C
zcY(7~+IR<+mMae)h8OutUs?j#rA&SXfxXH++Q3t&w8Vh3NLiimrC(~k&wL+xTlIyl
zx=;0jvQaXkzOHP(7xeqe+{MuHQn~3fVyRMg?0|6RtEOy*vP4ywt)$>fRH4CP3ZASA
z^`8#ws;_Rs!b;UDTAI&L9exM3S*rLz5Z9^hl){%&svtY)Jg=Jm5n8U9Rc8vpb6ZtY
ziW<GIint5bN2-8CfTyYgF9i5P^=SlG$gfll=s7vdWkGYOb+T^_v~7|v9S62m?luiz
zhun_#sP2{dIe33qUfm8XN9F#MYdayYZ2_Ntm7Tjo%RTwk91#DI2W~$CYNc%2g3zku
z8I<X*l~2uq`M=~3^eneHbuKj{sp{!Z;o&OvwytnLQ@wz;4X;s;q-_eD)l=-DG*@kx
z&TY&c3*o~lwH=-1D_6IpyxTeTRhk4}Q~S+=s+;PZx^$y@Tr+UqS6`&1+6wiHXHfiD
zy@zI)Z`DI+ujB`{>j(&ZQadT2e}U$B8~7Ek@l1x!M9uGyfi2PGo`OJ%<|ldtVY+6n
znFb99H1Yy~6Pl(iA$V1@YY;5m&<v*q@`supUBLQOb7mUFtm#A<|2G<iH7vc?^rwvo
zHJZxZko!wBwGsmJwL`W6#A#C;QI?>srTxS!v{!N<w@vF+*N$sD#=^oO?c-9~LU=^G
z@C{gxYbVoQsWaMudvN%?wpC|f7qvZT<Jc{&{dTB%r1hj*?724g8<f4)4lRM)JMC!`
z1gf=F^yI0J+Oj1m`>f4qj<R`HGNrE<T3ufcgNv-T6d{OPx{d*;?FYKJ%an+Hr0bfF
z!Y8_cuOabV7k3DjUh0N!0QOqfeKgE3)CbT>$i@2d9{_}YD5Z6?^fRd6TCX2NiO7xm
zOVl3Z>w_nttU%v)Ivg$3x1!9_e*HWz5D)41#6aMv{@GHL{i?rvi+c3)dLykLUDtP|
ziSAu}znS29px;ATv`6}GJ>c*Yz1s(1iH40dx=%J}pTNUZgXwEHlWy3$1JP#~F4ACS
zjbVQlwCpyxQBzoG@YnzWi{Y!zh~=1JHD&Fd8tl@5y*Het^9|-&!`&93##?{i9xf(Y
zH|z$GX1yD?W!-l?Aa5;92eXA>j!>C!J^krZ6wR%E@}*gjB^o||Q=ov>X0@~;-e#*m
zs=_|bfOnV6N1(7<Oa)3k)8FEHT$?N4nRMd;u4jx-@I)VhAv|u`Z_r0^R%>lgF#MqB
zz>ArDqk<x%Oo9H9A>mOb&+x#Q(4esBDAUj%hxao@Mfe8>jf)QQ4>k4fHPF7df8>O5
zKH(E$LW0H(3!fMr>mL~;N@d<y%$0cSE~Z`)5h1~W{?WnVVNs@G!+knA_l^k&>hIad
z!9OCx)H^&Zx=wYUz>wgGs322BNX(>QaEjk0-p4l7KQKJX)n%NM1N}NXI(KsH>eR`}
z)!Ee)9UdMMC2ni@H$A~MIXEmx@jtNT5j7*~pSIId=97E=H$DQp|B9BT9sx0v{^^+U
zIkp&Y@{bI)4+{?qvJdhP2sTAejtLDgO>+yf5A8TH!ZaB-nkgVS`X8@<`10dFeBWBm
zXu0W$XuHYaF8uBqti*|f^4G%LQ*JF@#>#5T_&2=%8!>aFu6;s5g=8tHP?q%<DF!Qz
zxLG7?h2fH_l^AqQuVT)^>6N;^Ww!$+^dh@lZzD`XZfJ45q<Vf-<jywe6NU&GFEw5o
z%MhV`P%Bd7bd4;XR#=^GD5~4*>WNoJl}b_X4Y#s<wcYB;FtOfjXdoueQ?-(ueeEpn
ze_8b$Wyu+-d)ZOUa!|Fj<i_bnH0k^Qy+2K!LAb5NSJ%0Xu<pfWF=nfkQPj)VH4%rK
z$Qp}Rwr*GL*Zqd|88@Prw{IWYE{=6SzLuISeVgAbqb3>3Jw#Eg+9(Ph%R1qDR$pI4
zY*1+k)rg$^yovbbqbyryZ!!#?{cTq#XL~1CM@KtbCntwa4o<dcN}L_toSZF>ZLJqr
z+d2gX_`CW~aP@a|bnD{e?C<E}?A9gFIk0n}Q-HIpt6M^n$r`VEmL!w$kXP5X)M#Re
z?M@IcWVjUEpinFzSWlr?NAN3!!a@+cEYA~cpiq2gnKRQEtK<3Z;zPV~8ZUGgVT+6d
zd4;<uAz0}ytP_l7{GGeFl3*OjT8lP`#zD+Q#1QZlClZaZ%ujSrG7jRKdWw`JlI<z(
z05ZL>UkoNcF^52$I71*=G+hGT<Gvzn33xyGiV{HfFJVZoQ#b~ISBwxllR@<qpNSeR
ze3pXxX{1=Uw9bbYKvCE|1t3H$B@iuc1Mtc);jj!mFuIITg*Z#-1kp5=^nNG8Qh}z6
zVxUYZ3~8Vq_ZDN*Ky?v2fWpJiM140(3|tNm^GAzyfUxsoIZC}n_Z28D94}H<fa)o3
z6IwAzIHUvh7IV_6bgDQDlvhj@%~pc!AwpMzTplV)2%R7dtDtJQ7z4m>MT(uPz+4$A
z{;Gq~VxXX^i5BYs!Tmzixz#<x*pXk+i76Szmb_wyNXam^RXw%liqYaghOrg-l3{Ge
w5``)gptZ0EQ2pA%THzx6TUyr_A(=)a|I|Xv%`~<}IGa(-H_a4hGmQ=Z1NM9z`2YX_

delta 130383
zcmY(r2Ur!y7dC$P-n)0}?akhM@4dIEiHW_%8jUTcsIkPDT(DCuh+P2{QIw*9pj1V%
zpfmwN5wHQGfTCcR|9i;q`+v`uC+_T=Iq!SU%-x-GW|qxi!=8o>+u4LUe6Hy%*3q_&
zO3{>g!zr3)F$!7n|Nh4^8qXgj1#^49LZNDFZ--K5_I8y*)xORc+_Mb-x`&`(_P7fQ
zRqr~pNTg&-omC2E@EwTy*8RO!#C1#N6^zd>oI*9O&PEcc+2=L@=bUmt_CsCoS{dio
zSE*nok7gCB#dS`Rh-W*d0XfG5qNR1CYen3HGETuPx}{dAwl=KwsAU5bZ*N2%F&mRL
z3YBjoa)oJJ0<VuXCLfr*qtL(5h>SCAx~Nb^H727>%dy@{h3ZBlGRJH>!z)y`8j~GH
zF&3oRb!+8iUcQ<}j)8@eLRC_421EXHEgQkH%Q}@pZ83EvK$iiMLS4r^knRKeu?lq)
z^LV<i(_d7mTUZv*eZQ%ULfyf<hVI$7xbI?d!M*t~IGNP93Wd6l`7jmU%LCZ}O9<UZ
zFU9?Ei`PKT=%`+$QK-jR`jLLe4!lA=(K?RqpLl8%thLS+(jPrjQn0qVDYZP{Wb4<x
zPxoEFgHD5bMRdP&I^<33R?@xyL{Y&utM`@en=NJ(Z0ouraW1nc6>OV&HoDKMhP->D
z*`p}a&CV&<9*wCXm<Q3gAK187K2j+w*g;Kd<r@b9@Xdd6*V}@E9sQqt`39AOozS?p
zS({w~c48B1ZcCkLrqrt)-^7s_sZzu-r@+l?oVzfJ_}Y6}bE`(7NT|Ix@Z%>cF4x{#
z6xL}wREjH1gc2NW^vVThwZcQCP-rfvaSDTyXcU@DV+4h<_Fk>2zeZG;YVUc?_-c*9
zTzfC`V@6C=Sa9!klQ(E5B`OuR+JZWo`d&qRN5{&ulA^BC0%n$1t6npT=D+pe6fHQ0
z9y)FWv&2bK<e-!jJm3kJ*8vZ*f{99#6x=t;izsNRZnf&q`3gpmj%XAL+YJv+QQKxV
zof`VK9&nV4yr==n)_J75wv3<Dh00W;HHtP0?)o=)U${2-&6NuKRew<-^X>j%6^dW*
zuQlC(`>Ma!C83dqN?#oF$`|T!bSttWylRBj%A9dtZN!HB<XDYDX*Hen8YebxS?a7*
z)Uym7q*5&A6bch)>foPxIWh`uT)LoWtP>l1?Gmky&X;&a3+>?<3dM5x`W>_;{{NbF
zOGmMaZ|e|+x~`_7p!m+TnSMZpNHwtk8i|LNX-rOzN9BcXKAhsoRYvg??cxogFA=RF
zFg1xnAbr2N8U=|WP?msyGiw!8PUKjvLfD^7twI(G3;z#+YRmsE5BZOv3T2=EPr0J)
zkG!DpCMBkhaVM^=Z9jTBq(-%^!gOjh)XQIL+OZ^sQwZa^<MTvChkqui6~Y+Kf487;
zhV!Zi0RMNPmsZiSChUz=muWe$ouF_<QMYfu;}u+~o*ssHQl&;wQEMo=@A2xYZN|*;
znyhWk-1b_h{f7D0D?!^)ziydEF|giCC@Oa?*5C8`tZmEu=+#Qs9M`e6*WYTdyKAo(
zbZx{R&!`mBq2DXTt3=m;>FmYohv-T8H-w6QiGo5gE^M-XwtC3K-sp!#nZydUO4hQP
z-&sbXGV56Tw`e+5BRy*y_Y-a!8ftY^UP>ct`Tke*qV-MaMZ8{{>$UI}(Mvb8{-+?Y
ztQgh;V}Pt;HQ9|p&)Znr5wFgcZuL7YM}MdqT=ze7|LGrN>aq1|qP#X(8p+j>=*m<9
zOhdMDuGdM+Z_HUQtF<>X*K3@$%ZTa)=n(%ys@1HnI11EOhSj8ZLTAeUHtjrdtA+nq
z+e>VtAI<Qh6@0^gs$1%gY~!6?m#ys`j0qi`qSQr=Ysf3QuU~=QNYOThBolr@x2EV(
z51pi9I66I65n4k!7Cnn=)2DRxJc=$+;kt(8KgaR7_IyJ6Lmt!hihJ!fnAj}q>Doh!
zo=-8$hwghjrV~KG)6FUt-XYZ!fkao_8{M5^kcABJ-%zQ0A2Q#bqx+jl<W`-ZNIx~6
z82a8L)biaVv7^CR#TE%2siNa5x?i3|IxUA2!}vyo9kH1-zaDmw7cEN3_c0<}H&&8r
zsFK>C=3g?u{Sc}84kgLgLLzOtizv>%B~4oa>7))LiG32?_r>GPD*EG<V-+7i5`Sh_
zDoqZe`y2h~I_MA5x!|vKAldUR8Qw6D=oWk+ACGxa?SD8-SH)|R+}cmDzlRa5=|z&<
zJ56r=xt6d~<LUnIzsR|j!>BX}?-vZ$HhTjzF*ln}ItTI4v5KwUbhQ_W3J0t3dq$oP
z&mzF2bW+M~LB@8zrfam3N*jM9()6wbTX%x!zW1&DX_}IJh>1{%Z>g4veaVTq{#061
zPLcuWI#|VT=*Q3=NyIs{4araM0FOg4|1|+_Kc?b<L^AMk6iHZ-t~=+^b<JM-bq^&F
z_(LVtxbdH4()KTv-Wfm+{nD1MJrYRME1%2{nn`Tm52O2{NmPw_rKBGcMDodH<d(xx
zMSzQ&sDQ!rhE-g<P6Z*aNom?hGE=ymu3f81;@C;|Ar_+h^)Bh_JCZ}YYsgFkf0A^0
zLpo!Rlg^#mpY=j*v+wsL$!uq;>LM><t8nC!YQ`m^5SNn^QJExZzL?yq6zQ7w7uEah
zMJj#TohSw+kc*>(i6SwY3>WmQy&p_GADdB2xKZ;ecDvGb^zU^2nWfU_wQ_Z>qo3<L
zh%UMlnF&rM-*1=GefBf*add4x7Ai^p%W5*Ot4C&<rjf}p=ScHL1TmDnCIib3kXzB|
zbRCvL#{6pghP7H^o7J2&Ln}x=4)aNH1aS2HH>*nq+~SFD_&-$qc{I@#UME;_G}Zp#
zcruw<N#^g?{(fIul1{(`BD#K>?r;7@*J15RXYO&jCS?+v(?7&~=oB%u4k5NdRn*3A
zcnR_RkEu(lKdmO!n6sohX$7fzyO88dA0o|fN)opYRN84fQJ9wzMJFZ6ck8G})7hzo
zELFrN4kwgL6Vi{aeMQ$4lH8pq&9vGc(4Fi$6gruR!jIAQ-YcSWA5HZ>*OVlRY=T7;
zQPXWaLZ!;VM7=zNoI9<h+MjAknjs!^AC^z@OEqNp>1~oPG14^wvs64!n8DyVI7$3P
zg>>(TtL-ecX#@_6B-l8t2k_*7pyGv5WHJvk7`%9=i0GGpN#3?EnOSNe{W~*A@=raw
z7Azrmjh=MviSY}Mww>hjuaNncG1PKSW6AtG%q>{Oe#aq7)^sG%k(E@la#u2cKA0p0
z(Im<CA@h;X$mCZHV`!(_RGQzIN}t~$16kAP>N1mbrY$9%@kwNI+!xYW=ucPGV`ARb
zm~_64B)c!0Iw%v{g*?6Zh(tF()4laPfxF3c-71sLmO^skyAxC@ds4kymC?QWF4gJx
ziKNLaBe&8Il77KJ(mC?7R>zZcwn$X!{4F_GRLkI;DAMyE|Af5r(vp&ZnGLI$Sxxuv
z?~=)@y@{^KLG^okpXBRmpMWG2nQZ4z1~&E}oq4_JD$OLepixxU=Cf;2>q!1@AHqJ|
zOq`x`Npj{74L$$P?}_Nb84{geNwB~Lr263&fk*yG^(a%4*WIU)u@6|&LNkE$hp(eH
z`==+F+=W>mI-gC%HZqua>Wv|uo0!ny8N$L0<3bwUZ^GOiKcWXv4#h9SsGv6%C3rvv
z(e*b2DOH`NYdx&k&?jCe180U4-SAQ}|FS-59$rX9|1eaiN42lz%i39j`e%}i#3~3s
z-=EZ?jXx4fGlcZdmJzl~1aUeRUm;QUWdf|tp}M+YLBlF8$C2Sb{YhS3OEj*E%y+Lt
zwQTS`k!rS)e*AjUZ#kFr&tjgBvHv_7_S{SNLlne+v@vP6_??`n$RVC{^9l9UF_{W7
z*Av~M`b3>Qo50?iNmAxZ6lI7i;9bY+3G<&Ax^C-0@{Y9w%peb<v&<x(K?QV;*+*td
zuakV}47yL>OiqM36E@S0<d0VpgNv(!sF&3CZmvo!{}iixlVo3Sx)&R$arN8I<N7mx
zIgKI)({wyBM^w1~Cr!jvY{}tTe+t!pKnOMIl|a&;IFbwm*3PV!*FFuEuauC#e@B%p
zeMU|!)AJ69=JN#WQQO^iP}2SG=49rN2Bf;8E>XKRCNnSoq}q72quLmCbUk09f!y^y
z=^uPS_hY^z%{hz7#gh}r>EJQs=(-=M^mYWb(77-8@f3G3o5K6wIgnJ3ETP}ycoG@7
zT|1Y3SC^Wr6Z$fZV(WU6Cru&nh~9LyVxp!|OnXmGT*b4kQS`uUSflv*1DQ-dMW}t~
zq&12k^Qhj7hER>a)Xox^lf-<Fo*0KhTl?hqi=bwoiyj+^f)!?B9n9)}-GbK8r^#^5
z@H@?rOniI%N~BSDr4w4G)h4VN*><&h!;h}V{p6vM(3>*K1ShAC*pK^Z&4R!^ed;W*
z%s9{&@|h>-kzEjUkjMMKcpr^Me~hMQVC`v|UOVax0$>xf0xL|`orz3FvX{9-^OAi`
z(O1-CKl4oqatD|N`;Z)D!d`>#5Mx*gmyR&2S$KVv`5tR=)`uB-8gO6c-~t%-V?6Vr
zd5kHV2Um|X15VTPcY?VQ41_=PofX_CnFc$M1Ta@<d_2Wu&qp0jGkw1WcOWAy0^khu
zc^3d@nW!>w2QjOudk<!2#DX-0X>=KYP$sz{a_5*B8Ys^*eKr6W#x&Id5YChw1a$<n
z>;=ugFEAsmkVY~CsVk3S+MNR1MdoTGa+jDn_rVs;jJpi;F^u9Ogt3g_0g^a|jRk2u
zb5#wt1m-SvSeKb)NzlB)Bp!wNM5Y^}QfxXCLUuEl-NT`Im%0Bd+B%bIb(TZ>XE6&O
z0FlkSPJ^epO!Pu<-)Gt<0r-GvOZ{ISbF?#(M@&}(eyS%-1kJ*pF&aci*kUGWDLgD;
zIO<7WGNC7cD`RGwP>Bj=?<bJGVrE-l;We}4A81xG#RinUVO(k;bi8F$naEZ#3umCP
znkkzL#5-oc2EzADP;Yqpk(v7i20t<KSNwRNnP1YOS;L6*`#LKR(tK;9a_T;K=%%dS
z_<v7ut6=J9dd&L)kl%ixzWI0g4mkg~v=C-j^x2C0m5&BHupFhwx!HhTQ0d&p3oY7Z
zQyi{ci+VxcEwVd|b<d}V*OzIARUWBp)E~~k99#YcFPJ7U0ry<B?!PitU4J-QLL<@C
zojcbD*7&oxArYnvh%At?rmZpZv27-gRp9;K#N5=N2Adgg3>2E}%(WC$*@c;pd7s9W
znW%%l8}m~SyxT_^-5Rj@FsCY^@{Sqv16=;XT%bwj7G?EZXu2x5%|XSyl{Zt7JD?nK
z0XZLKFE4l)qWrQJxOk=CZs3xY-)MQ*Cx7&jPAI77w*p#C6BmK5bIdl#2j=RaIjK)S
zRQ}f~>u_~vN*ck1lZ@+9=*BSFM^MQWMtct(&|9YKrT;a7_!^Ne*6;{}h^BqPT{KvS
z*%(|j9p`L8U({*a9t6fZFa7OLg~rjPCnk5AuCt$`+v?`p8tv5m#d|p2W6XIpe9x-M
z@S|5*8vN*8bph?vXM8fQec#aZrr$-H0uA4^3#DWK3WsA8Z_pSs`@7E2Su%ANcvk$?
z1EuR)nILy&-uR$$+Zn%Y;Pztt>PUG1_A!I#y+6jNOh|$lrVU6hFt-tP)kHD1-d|*D
z-N)NV{zo&l6^LPKYY@wj*P1I#ZAB6ps!8pyEUu*y!g~5Snxbx7@}+*%4S3yjekMF^
zY2J$VZ0!hciiYgyi#ROXwVfA`-DjVs3VN)AGXq=E&p5c$9UhIC{5$Bz+@gin_iTO8
zO<LlHz!m*~_Hi#k*--3&`{qySMQodP5Z9hQgJFE|(i@PE*+|RRN&nCr>BRWZeB7By
zb|8w*Ze)_@BfFoOp+eyS=BOuJJIK^WfC|m>&K(@bnQv7{PB7y!$f2(*CR_;9Tn{Uu
z%!EcLi(*c_f^Qd@uhdChV%&$p>QyGk4S;LRYQ!hmB<A`pR3($yJP#^aOlA(P|FW6K
zgMcq$-qI4Hm`Q&D)e<JC6I832<vGB=V?z4F;CrTV0EAnWTkAt}n{omNn(fLfJs{kx
z?1P{_yHC0EB*^wFbDqQdlgd`HAPZ0~-G#DK${tgJyP%xs3YAD@)<!jc|0rc1tre4$
zqxt}GUD-sBT&nVk5y?H}ND2f!RQ9CbEMGa3@Q;;4?xNa7%7O2Zd!bCXqPeP-UTaVn
zC)IjH9@#CbM=b$xSGk>rriW@c#$a~8iZ6%V11g~vG*77ha;N#Pzv|I!AkL|j`LJ|e
zWnK!>%c@n2fWM+zhRJ{JPuwJEG(gRZ%8_l6+6N8Y@|x@a%7%T92@yNI`aEonn0p=f
z-$az-y7;;Jf6rpQ5r3inZSQXYX@|e7aP8c6IIi6sJDP&9r=21qeS$G-VEel+gJe*=
z0>wiY&xXSzzHZ0;cVFmLoLq4Lzr(Bn3eYWl&%^QMb0$OQ_j#YduySYx>JY7Q{EUJa
z&8{=hiq+JegrcjOw@ZM(r5SHWS%zlxPT0!TI6~XP>D%1D&QN{Bts4LxXJLm1h+V>m
z$xsc~b%=v7T9;{n7rPA2CLy=SkbU`o&wenIE`cJKX?_ODL*|zrP|Ih&!Qh4wYfg6v
zA2WXi;z4=BG>ky9M|rpu#=Moouks47;q8nL&#urtr0m`rR*xuCYLFaNzIz0uuX6Al
z<ouNTu<^kjSL&vtt|ydlec@PyvffoB7nJF=EKgT14Ta$h<;q8BpiE^ptzWa0*Y5#$
zPdSz1Z8^%5!y&w{ET9GO17!j|lMj_)j!68n`O3l^s1_<WP~h&7^6o3-o+w*v0qIla
z0*Z_lDbMjRU#vVe6T;`p!j)hvRR(D=D8E#G#>N&~rW9$P#z{4B8_Jwjp-+))Qq@qK
zY*yti0eq|K=TC5Eo9cI(zMoQ^Y)CKPY1L8sc`{UOZy|SA)wUsMvQ%6J8Z2AYB>}=5
zRhb7WnyXq*p^68pg|r6GQ!Vw{+1}#FS%X?XQ8hXZl4q)Z-$AiRH7XhC64lW+$URp*
zqJj5?YJ)SlUaDfrT)E1Lq9PTlg%Xn2ssq?DVJlUCVEcr9s~SNo#wwLx5OVKSGW{&?
zRld~me^kAz0N|6V;WG%osLC95q54%dekH2ptPZ+{3T{;Q`5VG5>J@d-%v;r)Y0|r0
z{T((WSr_$UT6nvuH(Y^1ceR!JC{OiZ8i;qOXFUgQm-=}qG<T~nd&B%5bx|v5daD!1
zqHLc!b`X;N>ZcTXIHcZ~;(*R!wUy#`N7Wwr@WMyEkSgP+ZvF{n$JF0m0k^-p_bzyG
zQr$Qi?w?Y}QC#t~+S?6)GwSnG0644GVZ)FOR*!83vJiE#KfE}njvEBrdG*Ip5QeM0
z-=j(q>LX<UM5#l5r*7<`ddm-Bi&ocA>>x(HXE=1?)Dv1mCth7f%goE_>(AiD74@=g
zxPMixtOqZysm*<mTvz|{2*MlcG54T(OFg_R+)h@%XoBR9`llbDlA?Zh3uI|(+i+M&
zSEnC_Gk4WjUJ2;NGSz$X!JVxx90i(t>WeLb$W;#tKyqI_nF7Ii>Nb@~9;!JX&=jca
zT9Fj0B|oS<QM){crKf7oqezO>Nuy9!tPXh$6VKIyheBAY-d>HQOuecX43(>o|A8iX
zrH*Na26DVszjp=q8?_6zM%cINiUJf?t33jNc&9$*2DT6Cs%a?us4mL}>1TC!S2Wib
zbqNg+PHZTxE1cOIrNC`s=PXAfY-TgM!nLhz_mybMZEW)<u<OEJY7U$$`_=#!cXnd~
zXnHu<R)5084z}BCnApjlUJBrDcK%Ngda>i~KxZ%eaWYKoV-G2SKfoTL>GnZ(=t6KG
zW`p`c^9bt*1l)%`c>@jX%a)9R$}x5wZH^pgM;E}nKkHN%c2BZ?G02@}8_k5FK-Te)
z)}&`ydpJ~s*j4#35yEb#b#ExUf?kd=b|m)r*l_lK4C;G<HNS)1NVexY2rshRC;)tk
z4Vp}k4tu`>DzWU8wSdR7zxo57z|IMW@E+Ur1adiSUIKCt*kcoc%VYOA6p-e#XQv}6
zU|lXl`iS)j0RAzXM1lXO>}ei;KVwrUv{cOI_CiHV*vb+(>ZHjnMB=QmO@wfh=AVu5
zX|pDP*7RF7o#}bnrb(s&!bNi_6V-Or%ozu256wslka=o~dehsyOEZK<uH72X+py%V
zc|r5Iy_%#$@N~bX(F-)x0ZnisR1RqxV0V~3tO<JvyJ?yUqmfJ3yj}&(OwH>G<gzro
zR-^2mCa)g=Ihr}Akh`zhnF^K%8W(I*vkx`f1|pZQX)y_51h!C9ZA12vCSoCyCz`pf
z;L}shP>NU-X}Wv|(qfHFftKeQeH1(_)g0J{ioVqRv<#YMnx)CG^hz@WTe9qHjrl5A
z-fHUK1FlN*;3hQRYf32K^Fb5G0PtDUjHZQOG=&H(IM^D^`*7$uaic^e8@U0MDBQ&5
z>5vQNI+8Gi>-`QU&T-MRVB$O%8U?m+4(msBCR`qEnM87%ija%qnwent68Fu1utalf
z+d~-39e#{l99KCTWeMCQ3J6^0>UcotNaQ;G1f8o~00qsHxZgfOdYwz5nC4ARJPy0J
zxPIqQcAHy8@uWN4rx7ri%DtiRei|2b3Mv_#8?E{8a)tCDW^s-CBFX03(F8w-n~JS`
zHkVr{0`Pz<wt^*(bEmmmzJoL2><L@IW&RA`9&whru=|*+qlWMq*Yh}XMO@`2&^+hr
zJfOzsX8(kwj9Whq!gB6F8)&}f5)$A=B{z%4(kjmFJ#f`r-UO(8;PTu6_{gPFu=Wdg
zk6!<;+{~ZQhEBZW1fAn>=HJmAWE0=;6+GR{Uygt?Tlx4KNVf6$9f5G+gNk9vl|Q%>
zr0#t3Uf?|VzE6?t;G6D+=1#txX2rXCzeoVQ_~e^Ny!jEE;nQBeDhobc;nOFe+KGJr
zBqT{Zrg4y7=NIgN`CEK{3OOe8*YaTL4j)<r(iFah1qRdjufIZ=&g(~k?Jn=+gx?^O
z?-~f2d;AXCBg^5lXj9=nUxVW->;v9sKg{RzAvjXN7VvYsA@`V<X{PvuzeUu~_+vE=
z6c+Js4+3ApCk_VpbG|3_fiL*}FHxD7{Q7I~u$*5r9f%4(ybDxb^E-b)QpvAV!tJ+w
zxQs@q;s=a|@I4=gLqO~Ye)=jH{KT)if!t@lcSn%b@bzh>>LmO+5t<u?(mM>^zfHm~
zbHKeth^GDHt-_QHB-;gRIBMY{Jl+In+=Q#NQ|K;Ke}bc)!mqo5-ys~D2hCl=ue9Xd
zErgu}i?`su1;V{TuT0q8FNB>#?tpNV78-|zhctR05oY*6=qsElQRDsd6T0Ridt6w5
z7!^Gsta}K*PYTN>z*2zVPtl3f!c4LoC`=uN`kocCX;u~_oNbOI1V<Ra9V*aSDmF~m
zISO8c3zdst{(?~Y0ZF8Aa6RghExd~ZORn%kHdO8lPxAqH<Oz#zB7G=K_z`vsg#7Vf
zD-?!c)y+N;{DuMeRJe2#eisR?Hv?EKOr8bO=fdwa8kP#|SP096<wK!TF8D?x_gYwk
z&?{RhY`qWoTVc{nBvnEztts9KFJB^gFJzBJ%|1B<9hv_uOkR(weHGrsgS18{x(>Xv
zc<cb!Hj1H-z`a?FwxMi`*p&7awuwt}pt4=udJQ;Nv12hb-NgByq2eL#-VGH`(LlRy
zJH>r8x!Wba-HtLZarpw^_J}+G0&cJ9I8+}x`@~_PK%5sRt%Nj8jHLc5Lfl+{_PQW`
zKMxK^iOfIn;-XmN34f!-+XDcI5uFgDVB^HT`@s?~ZvGbV%i@=#uyjTI$pyKqI9&q3
zHSxQl(7Y}Vq#*qbu~QX%x+S_e)`2uxTrnNl6!G7OFqkS%oCidPICBHa?urStyvq`G
zW~gL~OZvf5j#$$izd^3JVFOG&5cSQVnI}#tg-U_As55ef;<5zb9*c>zIDH}(QCmC{
zJ4{EeNPI#=dWo36+yUuxQE?J9FT~!rQTS36C@5MkHkyYTR*0PzfbF%oD;8yy;$s@j
z-->76z*3d??*t_8#as_0A4J_0wAv>z@jW;{i;*-z_$pre3_y*T(hx#tX$6JsHcCG=
zhW7_0mze_Ize7^@Z-GA|g{*<jQ7IAru)b2tP<Y`dZMp*U$E9GJW1f&&(uUMY>9HP3
zfHe0CR8C9g&d3Eyb$*7Wv(hzMDg{Y%i(n~4no5hYP$`L4uIHtxS{MqGTxs1GA<dph
zVdM)^Nk`a?lK7jb??vgSeEd$)QeGyK7-{V}2;-$I-+(PadXR|R6=@QMF%zW?r;tmM
zGLz6U*CqBmayO+jE5LnA@;Afn+mhcV<nBmaLXb<9Hq)dfP4cEuB|~Z^AaUH4PSS6m
zC6yinK3iHu+YC9<=RL^fN;f(J_&{3XhL+8fOtdu2m+TZ#E|4}w0ryCXD1kGNrA_~W
z`>FKrA-Mfa5-1W<ERCV3t3-<L1$e3CK^wC#q;+XXzDPYoLAJ#q|GpgQZh7<+G@_TB
zavT-iBS(A-^WJjLDkOVlR~^{)$vzZc-Y*Z%0N{X}&=m#`$y;cr?y!8M0lYXOmr>7l
zRK7rqULQGuobi<-#scRjm$pFem^|PP4Ef6&SR^N9N1s-3@w9BE;}3zd|1{9tmUU_f
z@5qCxe@&4q=mkiX+fX-~Cb#I0BwgP41xbcH^=~A1<u8QGloOjG$&wXV;<MSZ&lV*2
z<i9B{Stwg+1NM>JOT?o0shoEQjZh-LaZo($x!g>Ev{b%*lv+rRppfoMd08%!GWo*R
z|3yohOr%YQW?>%zY2N=W+N4GHHPpW4peJy*)x|~dw)I~FA#XEdG<4ef2ZOHNF53BO
zuctlH4$=rnI<|>NWjh5><2pL~euvt1DYXO8_3k&I==Ng)NV|_CCwgp}09eoY^8o1e
z$8DJJ-J8dKpOi3M`}%GJUB6ifqO$#Gn?N_9{(i6xTup({!6%;LI>bsxk%mTJht9C}
z6viK(IuM#8qW8nCZyn#vL&5a^caT}E7y*;(W<5m>HZtGSs@sG4yBm^&jJ`Y6e3(v4
zL3x5XyA8tA%mVrigPC(rIiT^sD`z|pH8<`Vb))Xwmjamf;J(sy!jrp7gWnFWA{b>m
zx#JWb*~K|7OaX8=mq_ywFYf4ZFz(@cP*~8LTkZ+rUgV&<k856yWIwmoA9XmyZKP%O
zVQznK2z|K8G>P-&9@A{qkDEn}aEx0)%Xoio@mc^*a$kJmS^(Gc3d&A#i)NziG*{*r
zf;5nGnGY|{a0AxB?pf|>Gmr*xQw1c!+$h=t3E}>rU4u}r_%8_0aZ@PBcb@A=q17<X
zsDp`cuC*0O1b6BrTIT|{;}75>xtR<sL~%oCfV#--q&31NZrC0;6V3Gvruk0{7w8A4
zVmbetD2(IgtAU8;EI6OYUg7FcLnU%c8bNrKJ4Ms_Yux0~5GHY*M!>{%ZhjElzQKKv
z(XuzW#u30JbCYJk#BEMb<M|!V?J3GqxHG*0Pvw|Lz@>4gEVPZ3&TW|moeZwJ96DK?
zhDfuyM$bWdkNb2ONe<^a0tR!rn-uQ5&vhOK%?I4j6{vk4x7YyEhg=gag!x>5VkzL}
z|AQ7S<bL}G&OG7*yMyI1cQ^!PPq=x{!Sa+_x0|++o^h=gplU_jl$Nkt%$aEmyo9?;
zcAs-`nP|&Wu85X&FSv2E{r8fyk3m@(*S|4x<(#Dq<}0`&KP0cXt@mK?HFt&r^_5)A
zKzQ+n6KRqAmP<VXToo6U4tv#{M-7CIcbvHybUtzio+0_fDN|7Rm2(S(Y7N)<BS@Y2
z4z+81{t=C3Tln#0VjKVF6q4=yOd~X1`E!c^cjE)-;FCM=5rr}jzTyHBPkuf%$qqiZ
z1i793;FaLq#g`vNZnuMfNW-NUZ+Qy*9{wS%FTMHfUy<9#U!y3*etsdjc7WfEqnxZC
z-)}XNW4yr+jvnW~83Vux-W!_-tUv!Rb%!T;LkIkz0eq+iny2`^ZNPGxPmM)cApf~H
zaA)|`6!>(Ocg&+Bk3oF>2EYgN+$!jV@Da@*4CTipBRR)^91r1nzWq%A!+0AtX*l0w
zD@Y^wcv@;);CED@EhG5@6yb>C{TiTZ7y0CHn7_oY)<YQ0XHg6#hQHYp@K|0;Gs8IE
z(~$_8cs_zciV6IUTgYAJU5CTc75*5V!b{{oxuEPS-)t<LN#X-&d;U6~GZ}0*__`aQ
za+BXchbV9H-%+GHnO9ZdrMk^GrC{J4K7+=K6#f_TFqLmdM-9{XKn_Vd-)<5eqs-vH
zo(1<^{v*wpGWq-CL7K(av_+E5pPK=dd;BF@73A<$pTV8WPj*LgpD#ZIzyp5xuVBmL
z_kF-m@sQt5Ywdjg#ZEX{z~8XKd?A0B7D|u!RdhJxF+YofHc$9bS2TG4p7I%6q56z3
z!G{@G44G-hQ_Rl|gK7!?yem|n^UspuOeyb{21_sa0NMw5$$!j2QpV>{e5afbq?WDV
zN2p-w6+eQeBd_`VWB@ApH_O5KhHvu(uD#_~E`VkgZ$%H`z%t0+9W~r1T;B)PgF-tQ
z1`i1<X@~5vFr34{ctlu2{oGL@w>|Ja!q&sU`wGJrK*diepg!!FV5Cj3<HGnPIC?^G
zqUD~yU|NFYq|oCJBmu%)XTVPh8`^^Gv@o4|cSoSGo!;~_!s0{}1`AQaNJ4~$v|$-4
z%)-fb_M8y>CsfW0U7Evgn9wU2xp3k35g3dR%4wQ<L6}3^M3KT9dbgv5h-?Ti3jdCV
z<|Tn=Q5G%CpeG?lxI=TBSmE^w_!Q?5c84R47i@2!lOR0)0m)_I#yqHA5j<m|nkd9h
zLvmGUK|!BuLIw@hNrImQ;dP-oZC2e7o@4-bQ+V16O>#@9e-qC|vXDu=?QP)=jox>J
z=pbmO2)${aIaTOQk<>K7Q4j|g(}j8i@l$39BmMyQU19rPuw@E~6r#uy{-ABwY@vz{
zAKeq&`hYY?xJ*Zva)q9>Gk#yl_zNr#gx}^vm?u;mK$RW}zfeW<g}yZNC=iC^L9<Y}
zHVe5&!kOdn>8UW(K_QuELR;!LiiDdKge(?Bs&9#KJq9$-1&`@aDHSeX2JnTjn_?j^
zg)MK8D-#;g&PTZrJ{Y(P;SQaBdnFXo=GtrF!c|nMQh0U;ns0=LO<?e?aF8~#ssx6{
z)N0|!KOB(06FRg5;=OQWDsmr$g`LreABF90;Ke85?e8f2EWDnKCix<4%>(|cklO;5
zYJ|=6VBSfrr1N9W;vzqgZWI@shj5d)gI4UDMU3OLXk2v;xvk=4I;px%JQD!T?c$Vh
z1>QdwaZeKLx{3x`EW3##>0FDuIN@KkrH8o22L?UGVF^I&5N&?~zf<f;TW!0<leC++
zTZ~%>O)v2l&BynO$y;D)pV((V%Jz$!S0Z;nT%V2Pps4u~&Kwf`iSw}d45ySF>=Cj2
z5bPcmx6#1oBhH?I=Jpi>#sTjqdagt6n7AnlCXS11`+(+zIFHs5{-SX_s(n%%Fa&l3
zM1MN%eM+24=Ppi*^}OL>pg50a^=HJrBjEN~@%~Wcg2a!sd<ho+UJaomMBFzOz)-P1
zzU5-iiS7FUcwX#Ci<&UeLDQUYF{%=|2yxX^cz8ifrI2K#m`wrfD6y_53|<r`OMqVz
z*KL3>TD<=|IAcUE7H-FiXX7D^69-;~X1rKJ$959LyR>+_><~Nu0n#htYFh3kieJM(
zb5;D8!qL~n&MvT&BtAY1pRSATKOwmx28Y0zo8qcK<Zg+fU0@<v{CgWrq=*OU2}~7h
zC>Wn6KB1>8U2I41W`?-<2WZ|Evl_rqrnrpuMY2SP>OMTp7PSXq@Sa#nFK3SUeO&-^
zMf-OU-WLsY=Ieo2))q8aWYbdcq1ZeHmB|--(mJ9*oTq{LLh%l5=R6XB*om^oVicXO
zeIkzAh)O&aD`}VanV5Y8)h!Y|L}(U^g$_CvR3dhaht6{`u?q@I#g!DIe<8M{Q%NsH
zClA!AO!TGA;&O5DTI4Fk6nr+rz7qe$!3iwR57Qy6N^yr4Uc3>9c8BI$QBSW?m3Y1-
zSgOU$-Z1}8+(8>h??sWk{~)&Zr1<woas2`yK8am$t{yA*^1mSbBED@5FTRRBC^TOq
z_L_~Bagr*?gtNrEA-7R#LMzHmk_&aZo27S|fNzn)DT=;TT1J8XZPH>2nr@eJt^wd8
zy>kQHU3#zr01rw0iN-%q=@UiAc1e3^dbL}+G7WaUq%pJ=u~&-u8;E_9G!YK(m+-RV
z1(GUl&^#=8(^=Rf($GCfe5K|;!Gxbwy%PqHNgXzzf&8UsnaG`#JPoiAAdRmFyMfYv
z>Qc@~0r*1Dfr!Bnng|9-V=3?!EH$aY?;9ey&>A9C8bt^D&q+lT);cfsbplP8q&p4G
zaLF15nh426yDS%^h7|3Ils=D!Gf|TNc>pd--(5m-NeV1RS+rEhfip(Z8(|?<O1=)W
zjyUOS3H*+i#tYz1kk-w^BXC(d-T|stq+WC=Dp87{xYAW=3?1ydCLN+3qa?|34qjZB
z3VNVrZb%zwyYHqnVLr^?lK!N)U9vP_8gRFzV(QlKNM6ODPLX_RR+lQJ(w7lw4rwig
zfbL2UM<Sak=_$#Q{#^s^Y-#r~Sh^?mnFN{~DVGO6S9<OO{Cz2&7Bml}Po1HXCq1Io
z(L<@B7uq6U%AlRo0x6~%b_=Dw^gKS2(yIY@EPbLq%O?^x=kQiYj^9QC_)Ka?VelfU
zjE)@@Oa1MzR3bghgz&i(b_|G8X;e78cp=rRkFuB2R)3I|N$u}LST1!w2V8}eQ3ByB
zDT1QBuccs`r&mfBX)t{wWi^4px6(2Sg;q%mXp&Ve&360>{5wgz2ZisY#@*rK2WgB4
z5Fe%AX$AF38cb)~KT9<}DElI9pso9_Qs;VTryA*f269evDn+N9<tyI<uu*>g1!Y_0
z7Fyu8$~|=uZj&$5&$L}G{s#aTx!)5w>MC~|?tqS)Ec^@|ceyhi!Say1(vsX$&eB3>
zhaA-d&g_)k4#NB{xi!8jMYJY{!ct!HZz}-UBWLQ6^Omb=kl8CY`vhn9$-QXzZNFSV
zXIl=)0}q1bp!~xG2oK2-%>XzopZZAgw<Gd&ntdOY#noW*k^kHS6Tb2m6U_U`bH|_&
zkI8kGK;^jHl4ces<Zznw_{-&V9O0zgmL?wo@}mlrostV35T2GTvtcPv?$re5&&bYs
z0GyR8Xn!zBPNijBu-qL76&-AdEG>XERPNCjH0R`4Cs;Z!_n~=jnEV|@_`~H>c92HO
znZ2PICI4&#=|y=$HApYXh6E(h^24{NQ;dAd1uU_0Xf;&gWS4M|#mmh<fGj~)tVSDN
zmSYmYc}3Q{!wW~Ed_4e#SLIcsVB(tmPaqIUGTRHub$L}^Aa2NeQc-qOK0wo}Tk_T(
zs9LgolvZ`O<tmD`+>z(chh~bLSr_J0<^8l^Op~{V!i#jdM{~HAAt%vs_PcVt7yQkX
zRn&E7IpnE&AP}rdN8vp=l*YdtIsbbY%#{Ui=-ii;H0gOD_x}+|zP$bn{4S6Szd*B4
z-n$;j6M4)kn13ptY=^RE@;&ryh;GG1Lik+n5(QkTJd~CfW%4j*xK=K=z6V@|>{vh>
zW|i{X1u*zVcCXz$lrK{+P$f^MZmU`@qa$$d<SsNB{wUii#_~yyTMC-b@{sOO`6927
zVd<;<FHOX1<gqfmaMCWO=&-Za_d0SLwc+$?Z_-B5Dbvl`;T-_qqAhlK0kKt^NVA7+
z+BoX3wrgj8K(o1My=n37s=aPPnVWVJoh@_My3#iX9{9o%iKli-7r=LDr_tHZo!Xbw
zTkg{Kq+suE?L~?*cxg8bhsqwU*PlqdwSM$z+Fos_3*h^-g)#K7?$?f`FFOusop9Wl
zJ*XYv5Bwo*qeSQ&*6!+t<cPMI&e0y#-X9GQeY8!Zkn`2@Cs0E_?d)A>;A7gxw1IP6
zyOsjxC$xuYQ_5d^aTusiYFD>_hXL9(DkP`0pClxwwf;+K|0z%#egmp!v}@^z$XRV$
z`YD36U+D=9);6L8b|KnvWgtDT^?Zl2Fl_>Ly5U+cig-tAbLa$Bls1h<!;4zCERbE&
zHqoLjqP0Hh(2UXc%mQ_+cEeDV#c9L(p<&~-JL)O%{v~Mpxr6kwHk^T_E86w=s+~>L
z+V#j?)y^k_*R+@};;qpB5C!0MZT+E0ZfJ8aAi1f1LtERov`!S9PS&1KBe|`e-XE6k
zXk%&IOwnRY!&{+kfxivFrfH=Vkfm#<cY{xk46R`R5O=j7DZ-SgJ(G&UEbSD0zRPB7
z^Stqk+|%mMfhI@mO>Ox=d)FP@dD>!nt{!UBX@@OeyR`*`1={>Y&@9yIQ;|H;Hl@zs
zsdj8_AXhsz7i8tyd%Mt17228{n1AKay3#oITD!6kG?iMJz8!g^RnS3|x7t-o;H$K!
z86c{)TuapAo%ZHdc=2Alsu6G>v>$yz^HKZ23As<&>9olDtevn0$ro+KI3!=SF3(X`
zqYa_YXq<F$7XWb9y>x-0jXH;VHn=zG9xuV~v{|>CX0uy#54J$KRd;O}l5M(OA*kAR
z-3uGschOC!11he%?cNZ&>tbjD=Ala&3{p?s%W5><4qfzOsO;1&pcj6ZZvOWu+pQb8
z3RUvb`O<;1J-TmyhBMx}`wlvBu~(Pb8f^P?`f)J0U-yir8wYf`o)8|?O`z{q4(Z;v
z2F+pJ4r<vWx<xekKdSpGg49PBM2EP1bw}yL5kH-y9&*QY1L;jauKPsaX`Rr8(&Wxx
zHvwN6uqSm+L7+aZ>oJewFM+zo0jR|p-K8oxbyoLn6X*o#{^$fmur8VU*ASgg1ahIe
zakZzKbZetgwez}%-Qh);?!s8)!gUuK!R-j$!7uRQf-d&}0Fk=qBLI)m?WObJ7j>n}
z;mjqSjUouqx_>2#f5zy}odG^pcbEp%INdM`g~jV;od#QiE{tLpmvv+4r@W$@PFuu@
zIt_hudR5mu9wx5odh7r^N%tqMBCqTE)SzlNbmQxx?52*RU;CDB&qx50b<5~EzOB1O
zW8)p&MeO!D*c9E-10YS+)oBk;({xkyXp3~+(Th;c(4C_Lr+0Pwu@GkJL~jVQboDpF
zM7Hi~I&k-NVH8Qo(UsA$g!{VbN8rT+-O^-`<>}n$IKx9-!fD|0bwf@-vp~0EB!q>!
z8VU(J9_hkoquP&kvxmUNC%U#|@TqP#&UmxWbbr!XxLEhLcDF=#sv}gM>&m78P^z12
z2L6R^4Gr5bb>l8USf-mmA@Fit-9ad;(DmsG_$ysDg^OS7{-Kts)Xi^zT$OGE4aU_D
zT~`{U-s!TwqVT<L;9=PPpj-JHl8?F{=+N6I-L9$d`?GG^MELzhw_z_xzv_-GK<#UE
zqk@q*>7VK#+@x<e7`V;)06I{!MXxD?rLFpX4Uufq*P-`syFMWtEG~MVN5Hx29e=Na
z)J-4P4m$4o(N&=F&^NyU9Z&s!nz8QEe+h!hZvE6Gc;TgYUICx>=wG~s32%LVM^t;S
zzA6L4efsT>p|W3p{1<p}KyQsha!~I~{pumT6OXdPdT&4Ej_61F!roDRl;aHy`sn#x
zDD>4AZGc@r{a@4;$Mj=qs(M_npp$SX^y#!W?5}sFDEmqM`){BUpx+t<+$sI500>X(
zuYC{AKz%j=&gdhkfzIk5jYlPd^i5--60HA?o~{u6zgFZz^~Phg{yV2P(|YQ>-ibC-
z!t@{LYuIr85G8~W`nxm_yrAz9j9jFC2t6KA`s<M}e^K9i9cV7;%jdwg=>L3*(~qFz
zQ}Oz@dI%Hr8d?Zl*1ud0Ls#_cX*!swA2t{)SM`BA=>5B<Z#)eRm87ri3==o>+SLHw
z)K6*)FK+37rOq>1zmASC-`01G1@Mmk4y|%h^?y!7E=}KjKN=xjKesP%8TuQIL3UT)
z@-QrA>fg_S<~_YB8;<7a(?-CHT)ko#g!lFS-RS*$pl8-VHBUckB--nte%Juu^YwRW
z2d_Y%MZ08$diS5v2#@q_XfN%tenUP0PxMnhfbFTimx$am{qb+0S)>o3@t|0L-~^m0
z(fiSc;&Z)@`s`ADJ=(~8p<nzSReGs!Nso@BOuz9J(sKP|Y%{VI`dc!B2CwuxD9Zj?
z-}ya!s@6BG3uoTx2T<_ry?%Tpgdg<J+Cb%_KDI5`KIxBAxcM{8qiSFDD=7T)RsWH8
zUuyJy3E*UCeg>{N8+y@x$40~OT$F8c7>3h>yxH(q5v1D;x3)uPyWt9b_Ud97z6^=0
zp_nG6ZiX-&5blOMG^Ow`EaA|ko`&@lq}XAodjk!$+i-6RobfXJx(>oU1|^*~^){T)
zLb%s3lEUNr41shKXTQNV2r35*j>ZRI@Sx!dZ7d!#97sgrVZ&}Z26e<RfHnYp4F=kc
z@H2dsAUtMR6$QX?!+M${o-ia|g3#a4pc9-qX?X7f4+9KuDV%Z2F!3x5o;Hl377aA~
zsX*?GVXz35V8e!TBq4?w4*EDZ)DW@^Z08K|6m2_i$mjxmn4zx;Efa3IMB6SAhQF4=
z;R}Yfm!TPH7}g&uQ3mlg+`edN<AbtGhHvRWPPAdx2XMz2hAf3o@rEyVkV`OlUq<_0
zHn`G9k5>#v+TTeuT&P2FqpJq1*ZAocd{K|GTZXN)`I&6^5(u)}hBfqV-7#E$2Vsh#
z({%__4Yq55rx~tIMdi~Cdw+wW3_~m}!S5P=DTHRGVXy^$W*Hh@Ly}`CoCQFxp{fWf
z_YHD$IRC)VqATEehTE>N@X#>Xf$cap-@vy7qQH>U3^gk>%=il6Bf|#TLV9fYL5<uK
zL(pc>6d794`&w++dLOtFLuD=i&kf6ZqO8=gFaq2!4C`oP^rgY#1A}FTdSS?w8;*BE
zJu3`vSma(Ay37IRYlCl7nu=E%{{4c=yfLIWgZr&v4b7+C89Gwj^Sxm$E!;jB(&z-w
zN5l45;6E8IH-+%Cp;;PoUkolZcz-pNjDv|9!{rd<HX3KrOmUO(7dj8H*_hc8Wm}AQ
zX-M8`>`cr0ZN|qZXeqqic=jC%U5rx(AaOO`qq&Ql(VHTr?#3SrAoMU^X@J~L<CtL}
z-DNBbf&06S+i2$HW&Di}8SF8-jE7xs<JI{9>@}{VUH5&)%nYdPH)`?#KVS@^NA;lb
z#YwOnGNwMFFZz!f>sV0eW1PU@H}o~K0un#tTH4?|W_(kP+;QVcT85o4YH6wEZ`?~S
z#YtoRx4;D$yVpU>oH8~w;)y?P?0X#s&l*RiLKtLh%s?1y{E-HS5aU-LxE5-hK_lcj
zqZjR|JI))~`Ctn(Ufu?$!i^=zP_;<ouQch1GG3u5&P8M3D*P0ej2|n2k2b!)3t^10
z?o;Gqjcb+gDb9F@rkL?YA3DdAU~IY>$z|gs15~aUf2dt$8!s&eOOml|Ig;zfRkVt`
z;V{1L2!l6`XZ}TU%lIpO1d?n_q0PYC#{JFU+8yJ!6JRjK*qU}fQjPEF#Cw|YCWRsI
z8k;5|mubwQ9sVq1YYpsX8>4$7chC4?Byu^%KzfjJjU6ZobKiK(3uF(B_36}Op3!l3
zF&goqas4jP<QsJzVd9bTrXJ2bHh!}W_$S6~wD5XrEIbI{Gvly(NQ#U*EC3W6f1<v=
z#JGaa@jN%0lqh>?96J}yU1m(9WmLIwB+beyjA3+k?3HoI0pwmAKYtI+O5-Vq9nJQ}
zc+nS#x5m{mKvWqkX^*?w*sTDry)*tsHT-D2M4|If#^Wo|GM|kpJAnIQ-1!g6z8Ynk
z&D9vEumCuj`qHGq*;Mis!i}aQ^t)~{MNUGMHk$@DM%flqbDFHUn9k3lv!kvicRJed
zX6iu;a(7cM?TUGr)@%gc)6|D5y31r-2D`gWb16*hWjZn(Dtk<OKEVrbQ_<f@_L}xy
zg>au~%Qqm~Z*pG?%>$;^T>w95>aiSl51GVYpmNx>m|mPCCg~443VqZROTB@QNupy&
zzNVIRHqg&B=><rSnLbg~j+-Kzqn%HfUOhq1-?W{^kCUc)G&c+|{d*tDDbol#lyusZ
zaTmBiQ@>Pjo-wVYaQs=*(RvUDnJ&}LNU&);E#yN?|Kbd?gAFxZqi;#inHsM}a^94m
zgCxv!Z7%TPra?4Cj4+L_1N;S(Ks`*PX-^626lJPUVS$ULi9vAtk}1*~)s8lmY(NrY
z`i<5|v8J-`U@6Yjt{uqYO=ng@m|)sOTN;;5?SF$I#}$*)4Co}9#?l_!RZ{}3imsV9
zwSq9oG;J}subU2ii`)%UqmAIcX$ol!{4G<%%>X2u+CD+qZPRXaChQ$km#b)}6w|7S
zU`aJi*b5VBrXI9wl5SGfMx;y)X;pOB^!*Z)Wjaiq=*)MPsmB{6*{0NE0NyhNw?ko$
zDb@$TT$7nbv-_q7acKMprmPvTn`ioo{w~2o(?}Yp^G)xFrNE?%N3PIxC=bp&GTG=M
ze{3?)F8mYI8`=kZY6`3b=QGnx8g7eBj)!qT6q|~MBU@@}M2Fj7nEL&ImVIg3@&%-2
zrZdh+%1s*TFe*&vCLnob>X3zMzc%?%)Tz?+hUS)UOx0aM_SUr87bdDqP8l#*ZOWwP
zerI|Z0H5BQ_S1>k52is2f%|Cc>o@_nPp0QfVDPiaDHu9mOr|~H{%Ufu!ETL-`HcEH
znPnq>JZH0OF*G-t<0b;P$-K>qvd!jvd|JtFF<+zk-&S+J1!ddJvwH%t-JD$o78i2?
z3!JOD&SxZUX8+;v!rgqOKTX9w%sF(}!qdE+&adn+=hE4Uo#qbI>buP22Eo(aX2uDL
zmwCeo2=|yz(!9jm+$a<9z2@pq0PHglqgm*F^Z8@Q9WYyI6?f1)m169N%)M(rVK7gk
z4(5pYoCk16&7%j>_~&CzriFp8xi@t*e&$|uc<7jU^IqhRoBLCJPnh@9w94N+#|iCx
z(%kF}aslRPGmtxFZq*0QoHjR`f+Wz)(dTk!%=_p~J!>A5i(HV|LYt7m=ATc1EW~U!
z!i!MzbhNL7J!j6PL&)dNKPA9mn7QAdXp3;OHw%1(d3_I<xL_`Q2z;b@-vyY6GB2d4
z#6|O9`h?+<dGtHLqs=~a=rhLrjzU<mW~XMr#hFj*!4hx2{tmbV^VtUgB%1HO1mLRq
zk6^gwxMprJ8U~ZhPibv<-Q06B5I4-7X)wQO4oL*?mRa8h+{xy3+hF&$xg7;l@0bUA
z!bFOBelL)wnlrMIOEcpG4ZLdR6ZAnthPh!URP?U7ABDFv&2#AK$}%6L?fz_YMSJA#
zIm}%aK_|x?HUT=hW;@Lg?wg$&0{_6QD1aAv<{nFsduZN6+gkbNg|Famfw{+I<O<Es
z+hOpLId&RykIfHg&G5v$w<pM+nwwEj<eAy;XILsSuct1!*gU;0I7`eKv?>1F>?pbm
zwo-G<TmWB~x2aLJmu7i7NXyIvPXJhMw&=iCVRp@c7q85Hzen!1d3i%<R+>i)f{8cg
zmYb2hH7CtNS(W)GI-Xr^t_}zFJM)1)(0p&6-x<jV^I2MYe>9&O0hLeYI7dgMpUulc
z;Qkl$z=_cLYL2GItHvCx1F4gxoDNz#TiQ2*!y7F_^8nan(H(=zW{YP6a9b>H|3YP}
z#c~QN+bn}=rMBH-I0y4Cmg$4Q>1ugHr$XE;K`&w6-Ex*bIrOm1OQ+3ZPfOENpxI$j
zj7PH5(v{|cyDSavf^D~D>2j!eS=ygNZja?388qIO#%rLm*W$AX?X=HwjXK@^mf3F5
zJYX5*i>5qm`9yu-5lg}#lpVFW&=cfiS#TaXUrPd=dh@fC-=x2&bIj7U3Z5Rf9P$A7
z3Cn(Gc;RpHY6R|+mas*z8(@i{b>k_^oVKug+LBIN1c4SOI?R8@@`?`pp0)hb0V+Y3
zI}}(7wlqsaF2rJIpc!iEMzud@*+bPnZ%O+D7Q!rlBckhI!!46&rW;{7Oq*O6EOV*Z
zA}t?iHzCS0IS|Q3OVd86%q2@OZ3;wNW>7dj#*)?uNv!2ub0l$=Ce+WxTYiX#W`bqJ
zVkDO>t9c|>EIYfvLZYRFUjM6>u6pFIS)S7w97mERWH@}gZb@zq)f*O<Nc=!IEv+bK
ze#^p803z9P#20nCZFxsuSKYDvN!zn2mi)h9Fx67M5;SR+UoId?x6GxON`@tn;(&K8
z{sqv?wA7*HNtUIEdZuj4q#~5vvn-_#VRIaop0vElwd|zz`F+dy-{H&yi`#n$^DI6T
zjeKaSrl&05GCB;d6<B;|W?yK@ZVmH~EH$(N_Smv61<4aj))_eZ)Dl9$r)QSn`Oqw~
zM9{gFVoR@7xK?7p$r-$OmfvYJz0~5EP7{<DmN5zxzO-D&2i$C#W#mvG$}RN;&{SC3
zY=_^kED{~Re{H!`7n+rpYxKxhTYj7cz&lG7eUI_p()t24KUnVFM%hP8#7Ag;vLu}b
z*=LLQ02usY={^v-uNDU#-LA2eI%uSIvSw7EGR{`D2XY&&HkyQQvTi(w+-B>*Eikdg
z+MR+iTdl>uz;CloqAkho*11zqZ5Qj`biBgVI_N2?=4Q=KhNJG*(r;nj!x}?>WXRL{
zS2=P!tPHJvcUsSoGrO#3hST`B+j@Y8B`@nOIyth(`syGGy{)BhV1BQ4@GT_!tbZ4S
zX1{gxTv$3_{cbrl4_a?hRPd1XFwHm*TZeW6*%50o9mYOt-F62mKGty*O7gV^9Y&d-
zHTf#Yj#&pCgonqie}&LrbU0yMNPV}z_0v>T`=qtwBd7*gC&fT`3fui)J8g|^3QK|3
zn>6H{u@=NY<*fDmOwa^bSJ135*t)YCNr-g={gR>9m-NP*vo1Xb_<3tgGuREYuKW?g
zaO*%FR3fYn#ANU(g0(TtB_gfsZh|e!>e(MU7p;M#0K8<a_YZuEw$`{qCC2(&U$jiD
zHEu2Nan|~z5^wEBAB-hfn+}0%m#r5lxPHZ&kpMuVwJV)6x@w)-3oO^HEot~nvS!fX
z;_FuS7pORHSX<LUo14~Um+%|hvd*F1tz>H&ZFk<bDlY+X$GV#0=_%F<T2`f6JN|^0
zNwXeF1Zld}Wh#Uj*6|b|x@)cH24SYPKb;%PvIg2vmSa_)gr!{Tx@TyF`_^x5@b`hW
zJ$?M2=dez7h53ipDN7*DxBfs2ivsIvdaeqsI$E+lvL@5Hwa3=HE%51y^-DQCd}_Tw
z$FZJSM~#A|BCF4I;EJtgdh|-HmBjtrTKFx>O0DPXgZhQ_?~_n@X*EUyS7vRx5M<?6
z$9+2TSYdUGfcvkkQ|QkVzP4^Z4w_1<l~&eotR1ajduz?6Gg?*FC_0Z(ZT&eB_;=Pz
z;qdUi)j@&(4_0;^$Ua)v1t9my%24$6v$Zbm?0>QLIRxBS>sYEpjdc($A)IW}94(P`
zw)Gf|`fjv^(h1W|wx(@iaI<X}9lh9Mo1F~1TW#Oehox<{PE?ESwp<RRF1B;@ZHud|
zJ#Fl`+46${aJM-b!RcWe?g>p#TeE!F-C^st2P!*l%M7rv%Xar3$adRYylMRNvUU6m
zI(uvi3PgC@EcB)4UR&2<aPPCZCBgiD+cNrlK?iK@XuW&TR;564$mUJ~g~PV4V}Uzj
z^XUQ7qqg33#@WZVT0r7!n|2v+KU*7Gza6tRuZ`o`O6c$XoUqMkMxkJTTeq*M{YhK<
zZZHvGb2gwBr);-rU-z_amphyZw0Sgv${Ab3pOHIjo7D{}LAGAB9Tsd`LVqzd#1={i
zTtjVHw7x%Q)22h^yv;NNoME;;VGxGfoO-~g2-{zK0k~lM!f6!4*+^R-ialSlJzR+-
z+SZT)@G-VQFM*G>^`vlqob6EyB=NQ;^s6P<5@~{d*|vz*=T~gbyO&!WJ?MmTlI<P^
zhOXNtK7ig0+gu6~-?WuCNA8wwx+hv9+18bY%iFf-pOCv_TTf@^Qf#~EL`$kIA_(o7
zW=psQvUHnx0A(4rPAWKb*Y<rkSj)6Epncmc+k}}&vTa9S19#8%-Kf`K%dyFmz@2N`
zcNX~jwzjnHdSDy94`q3_h&Z_R&?X*-iG178ApjQGA__oLXv<lI=6PhR^2%La-?3l|
zGDWsEw3;ur^`d2BiEY`hpnPr%a7M1w7D=nb7q-a@VeX~vX%i%6HWi&EEVsGRr{Wd1
z<Ue8cmF)|C)brXl`85EQwyh1(5^rqRXwCQ5_HPl&s%)L9Td1~m=?8D$*)kk7@qcgY
z+ym}@usIjP;73~-ozMDYtB*e(z<#!kZVc`(wqgoyeYI^k1C<)v8;X)T+3z_}=4_uv
zU%GF!_fR0&WdGa>$!7bpx+vRXSFQ)yR{Nko0N7@CN`Rs5c9-Wc>tb&;-+`>FeN;3Y
zcC+_uhs539W+{Lk_GNz|@wE4+h0YH9wPGN4+UHb&dzU?w&cE)q_ogYCmpzsin|th!
zX$1DRH>-hguic%2=01C6dsx_SA2uHF1NOlb);Vk!B2bAV_Q<;QMjW+=j0VETo~=RR
zYrjaZpr1XKA_T|mt?0bOaeE#ek3M0aOWT<K_WneA(th9~XaelNH$V+f+1Jolsi*B*
zXsRD*m+J$5#y+bM2G81$(uPfty@39zNU&Yo24x}kQRy@yh1#FC2F*Ep@miQTZ@)qP
zXPEsh_2S|7R|k<q*dN{o;)4B`kHAOT{}5m)%KnlTBNy$*Xi{>?zKqt`(e|5jU_Qpa
z#2YHHb`R{ouyOXaH;{|BFW^9(V4u7KnwRa~vygLKvA3kZM388owGY6nc6aKluGv3P
zz&pvlY&7g%w@*qz*$w-GqsZN~zoF^CE&C!0w<p^Z9>DF}_UqBW-LV%^>^{Z5eHXY>
z?aybyZkqksckm+J9^V(a414Gy!0+0d42FeFhkar&3bX9t_kqZ^f2M%>J$t}e=;YWf
zRP9`QUkYsAx1Xhbxd-;~PB4*Y&&mYgp?yvg;Q98KkuYCi|9Kj6h4#B@<R01euR-?M
zp8F8EC-#Xk06eviqVDLKy)px3MRtdJ5z=D&?kp6R*c&WDMW5S$?+6p6_P_N=Uf7)y
zLHg3(oz}Buc9&t`F1HW80n!S4D#a;Y+3mEo^V)8C1kFl&-bncS#$HJ?_P6#K8c<i+
z--~GVYP%bK_503VG8wJ*-X8B*fWi;<LOMY3(f$j4#`np7n*MacSNoK8$ko_$sf%=~
z<JJ%+oa;PH1%6|lyoGRWQymG5dUkUi1m^Lo)fq}*u&s5BdT?&5^W--Ox7P`z{UVn-
zBV7S-t<x$EDsFXt|Nl6;?zk+gFRm%B%*@o@z4u;}W?E)tX=zK%)HJm$e_EMkQ(t5V
zh-_r43}wg=1rfo)bg+luV9VZ11O%1e_w?8KoO|ZIyw82kJ?GqqDKLMGvG?(R84(6Y
z1Rf7Y-!)kBWVBME&x^78XZYmJc$3;Dd>HxktxsRZF$y*O7++lhcAU|>0RsMvA~vQS
z!1#wMAc2g(C@KhINGQk+W|T@X?GT26_R|xLldnPNNyfKmOS3t}*eRKU=P#5IO7~d9
z7}k#<7|ytq4>b{tDbHc)G-G`lES+JDdjLc-=BdFF#n_$#`Dn(PB>*vurPMQamT^=H
zfmp^r4)7_CF^6`ocm|6LS^}f95#StSFU8-9jAc}BJ<o7Lrz|oejGaypOk&j2u{4=+
zDGCd9k)bxiixft^KWLX2m%oJjsf=h!V_#<M_ky-GM%6rE>5SuF1G~bgz5sBQF-Fc@
zV@#%|y6cSh>4=cQI6%3;OvZQg&5$gHn2uuE4Bu*aXw6}STVW!XQ9$wZ4TjzeGrY-|
zodol@7zf3$dz-QH6R62!<n+K`KBN9D1`8Oo$6=|E!H<QuBE|ulZ!x2TBBT<=ZxvuE
zWxRA6SQ%r<E1;D#QmI?=4nyM$S_LB_0dkeTyY@@0n`6LM&G4biQ#B05d2rV<ihqO6
z28K2lRvt2H7eTg>;p75Z6Jyar%&wX7{t)C^7++GBt(CEkHm5em57g_|&KT?kt%EV`
zW&DXc87m(F>tYP=hRtrqqHus7#%}7;>t(!ZT?hF-#^2r0-OsqQ4a5P)7s(hLWH?c)
z|0Bj>N=^(hOmyGjF{6hvEyIkZ82}@UQWfSi%J8Pj?-NGlD8LxQPYBvLBcG1KPZ{qg
z0z6}QyTjmfMj3rPXoA6?1<a1wyq~i2hnd$X!)nibL~G^1?6!qnN9I}<yl`TA(mCn~
zb3qHH=FFUvia{4<nFEx%GB1aNc9gj~8wTB&K@{5^V{+(uc4ww7gC!4Uyd89UGE-iK
z1uv%KApmdY66(74VLr>HQ;{!I&WAQX=GIfteVn=CH(>ru17*+yn1W6y4P-tuKwA*=
zD}T5a%xvj}(hz1c9S=@0Q~v?WN#+4M>zraX-h}Q@X4PT{gfT610K%CU{{=0A*+Jh5
zJk9)Y5)7ST1}>!rwMgbl+P9;a!H!sqXl8IRw8b!Q(=5(1e>nsY%bcK(wZt)lyucaH
z{NP_GO<=x3Y36gxY1uHC$SgkqrRSL|l3?NjGkiY=lb9(J(3#8}{u%yWWPVKF<4j=+
z`=Ij@v#Al{)>P)rMi4JE`&)pfF@G5VF`a3x0Jy?5O@qW$<|IGZy~eaHg3{|u9<}~u
zFfG((kj?a#LOh4Lv=DCRGC%qjEH{`DU2x_m^QQnfbBlR`3f8xotp>2<G5e^KAfLIf
z7MulE=I_VgVj<Ic6l+<;wD}BJF_YH@i4vxo>QSZ4Z)F%PV_v7qW;rvx19tB)T_gY%
z%nr&9R5F*xz^A*+LVvK_W4>Jp-S?SgYasW4+1>+#Rm^1SD6MAJ{ud-N<+LBvGOe>I
zVyR<#(&4I}`CB?z8<@}TK-)v6;b$yKBQt;sN=?i;vw<};<0&w2VZKC1rB-G#73kZT
z<6i)@Gk>F^YX?))1GhVw9(8c0i&^>@pqu%I2%v{qa}O-N%p&T@?qjxFDaqH*Y^K`)
z1I)pVur$a#JPW=(VqUldr9({1YoI-5W>drDF!P61aCC%OTMw2|W+{n3VWusI!7*ma
zVbI2zavlC6Pnm)>n8Y(?@H@bsGmmp%aDq9w2ZMI38^OR1vs|}Wf!edK?!j_9u-4FV
z*^zaS;!-Ep_&R7i!g__iZR*TgO2L5(>&pqa@5(9*hTKusztq;?#u}{wc8t|PWhHmk
z3`+ibu>P%rGEdfSdNX*j9)1N!y;*&q0P|tJ@jtNmvflB;cXn<3SgF)Bbez@oDu6$0
z@ER5&fYnBclR(x}4|p2H`iR~o!K?=#Krn<g>;UWp>+lYMldO2kz@1{rmcZ>$R!a=9
zFqUaMXyGhBO5&VhEv&>}Ig%x(Fg}Wve+^hPtNSut5R737C}nY$RjGk*v8;6z2gI>5
z>M^HymOmdpC9o6};GJXT`v6O1jrf7(JZt+dxORaRMy2^A)-q3E$*eAFPrt}&p%+UE
zYbss5zr<qyj=@w`BxR&7vkndcq_GmIhGI=;CG|tw6&7<Z)Ldm{QgZPci)DfN>#Ujd
zb?yw-zzTSn$vRzyCCOslp@e5PYXdD}4l9UC47sexNX+R5>%};5-ek$>bbpKW(@xNC
zv)t|h%VSxSpgNzm>s4R{tWesu3au<BdMb-pc6TttVphd9NR+VteFM5nSpoE=t1{Lr
z)PY;h%GAT|9o9|@OjNMmp*(LTYa=~|cUjLnAa{>7GzJs*Ss#Q!?g8s9O669uE`JPA
z&GMj=LJe!68K9PB`~(7ZEbA;POVzVJqg-wS>mw>LJY>~oV6c((*)!N}Vr`?YwPu$7
zA}qDA%yjv_m9^OhE7Qh06AMf2tXFqpu!FUE1E$u=3Z>TDF4l5-*L1U5DM0ICh0%$)
zm$kMOEPbqOY8~olZL-QCIKZ-@ck3W4gARm`SgkBLGsL<<1>MK2G8ya+v(o7}Il?NW
zg6=3QeG{-Jtg>*Z8Dq^o1GmRnt0-mglvNf9mS?OZ-(V8YSwGps`~=Iv5x|c9@pT9s
zW*^CiJ$treI=%lK*st$_Q%Bg{l!kO>OXz^*!hY-p30HP9{-K%8QFfavw7Ic;C~tC%
zy?8m~+}UTS2<gGjr4+I!+xQ7syx3c$@YkFD1^pu{A9fI(mwnm$=(+b}pNInIad!Ap
z*z;%an@0`W0ql$Pn+;^Ir}It_yNe#&VD|T`;Y<ko`gbsRg6(z$EGO9-D$JZ>3o~FM
zl>NyK2!yfcy^q0g_9+%jM6lQV3W3w?pD1l}hRvn!n@IMrw1-8pEwp<?v*+D{Kn!~u
zLT#(fS@sY$@W-;%d!aOr{jEJfJbN*nsuS3IY1PlM!+ao^$S$Mym-B2zBXnP2+j&B1
z5<96GAep_$3(j0*S3U!03cG-^k(bzuDbtwBUP!6J%WUl`u%xkT=tr8)Ry+l#^$Pnr
zr7^FvkGuqlYwVKA(0!e~i1zgi_DqUPGub(l0J7NM?gK5G-9X!24qG`F+H%?3GVy1+
z!JaiA+HSJtblu?=+u;a&y3J0eey==sGj+S=v#aTCR=|#-C%lmTrZ2P<S=sZb&!Cv?
zPxX!xcD@fRm9iJpDYc9(+YO#__FMFhyTevc-L8UtWF7=6*+sO@ciEfiOT+iree|!&
z?z5$o>VLrg@gvNoiXBadm}<7}ZD2L*!Wr<emYrmag{@=f(+$^pw)Isy4m7a$Gy;9d
zZYSN1>^s!+-o)0??Y(Ap{cOm$u;-UUu$?XV1A`sxJ!b$q*{?mrU>EypKeTkSGe3kE
zJ?!s)1+AAIBf?zz*rK^$>1W6M2=fE%p`U;avMaAc;1S!-S_7UT_OCy~#AEgqYUCJZ
z&#lDjjj-$Tz%$DJJQ1^a!v6jX(8k!iC`&WW?)V>Ap0fW&2xaq(&7}DMIeYvytn&nW
z4K)ecapI?f<uIp>GF0}QzyM6ifuo^I-Hx2V`B3e|8JSGa-w{p*HHA5I-2Mk17fyB+
zfGekABMctpWYdepjnnQ0zmIWpK7fEbXWB3XJUE}ysoInC3hi269A-b9@#Yjwz^)Ic
zhtkBpoZ@CE^W%JE3!jd2GA@DU&vBzZ-T+Q{FI^A}<Va}S3gVR4LTNDPj|lh{!uiq#
zlR3eWZG+vDoZ|1G`xM7D53>*Dd_`x!Fb;xXJb0WwN-aci+9@}An)6c*z!}a#69ywW
z$@EY~af}+Mj^;>{U_OR3Z5!mya&}iyRXUbaO)YhCoI!ex#&a0{(4D}^qjT^%j!O%$
zM9xw=RiEdu>Y?odXE*IBNu2lSRGrLmo($|FXFoD3HYuDh(_!fn=cXQ(QaQ8kgLawo
z_y@?Pab9}}E$N&M6t`aC>`(w$uX1W%f#5aHEULC%=lntQ&ESNs12L0R_71$r;#4v)
zn9cco8I~=F)3p_Yxf}=T54yo|c?vIXa=xO6>lVjj5dP+KQd=-szzOz)&O**LddC!T
zexpk{#hhhFAYQ_Gy&71lm2;ljSjspnH-fdCv-Knd?{FgSK%#>4n6`*Y&a2Dd;a$$I
zSeUrS8KCCT`y4)X{6FC2QB+yQ5m$m%&6#-#0yUgHbdIg%xYJWn$0_&@7V0^>C@tQ=
z`Iip24>^@GOsSDGd5-Tdhv!?f*8*$h{JS64+c+kgXFG>Y@nZ+)54z0S$$5eL5W6_1
z=Rmxhqo)#R59fPIoc3~_eFj<|hfNz|Kj&0Fv<z^(W&jLwR-A{HN1U5lSQz4jE`YMf
z949AO80Iuk&(8>_+e#&ZQBJ%H+MaNhbbx1!qo9y_oYOiLf=@YrQDe?C&i7x!?sLvZ
z?En*;_)jos$6a<50*AQ^ZbHDG>+}>JI&d#giOZ3j8VqqK?tA%QIl`SswPj~+{(5k_
za8I0qSy%3vZ)kfy%JsdEQ8#WhrT>p{e~tj=&b6U;xd(Tq1cRPj8U0<nxMfrt@a7KD
zU($!W)d9el`-rmQe%zuru-eDD6_;S%pSz?O;sM;3hkylgFAc((Anu{bz=FAwFbITj
ze~hQv^a<{s37{vr?|lu4Q{0WT350Uj?F0zp{`N8?!nw{iuoS^9y$SQDx&CGF@C<kR
zT&!~>w<rd*DDGeTL5t=dT?`Pzok5}WS#GcZw0JH*0p=69m#L0)j$2Imm_+WI$ebb*
z$#tF$;sx%CGO#9b_0;>5%&nUYaFL6nJDx4BV*~^*alfPFLn>GG0t7B|kJHrBxZ<a9
zCY`(OZ?Ih9jxNU^_9}P7-(b1Mt&(FB*SP}}o@8)O9)QkF?pGAEWN{BRLbWxUn?Zdx
zIox<ppt;<&gCO4E?%D$ECbyo7>9@H43^;t7yN@o+<Z-3+jkSF48p>A}a2Fqei9)WK
z8X=0fcg)}{<}PW2&Jyl;C$LiPJldwpxL>Zva+PyewPNrNw~Y&DDy-aUDPSeHq6IGA
z<^DwPk$c?mqp*9Q`)MEqA8@75F|{i0Ka?w|=Bnr?U&EdDHfXinO+SFMj;o_f#`WC#
z-+(o6?@53?<o+)U0*&0gJb2i|{nr5k&D_F$u-C#J{RIBDa;;vOm_-}+6FLdBbDb#Y
z=-|Gb4f#&)f<jp8;$E%?Yd3e9KjeG3;;B&D%XM1}tdD!9A1wXcrlr6JxKXz;?LqF8
zRS<Z@{fKH4L);bn!19<okM^KpZpV2T8sSFJo;k|3TIs&t6Z+sZ9z5<jH?WR#^_16q
z$~{NtuV>uv@?h{eckDLgC%9iy$-<78Is|Z-*Fh1gJ@3yyuxbvxFC)R?$jf&F=EQT;
zVcJJ{*|f(y^G3b_aN+$%+oLOQW&tc5<@sb;A@9Z;J`PVkc+>hZ3r}9y7>HiH2+E0h
z^OE0!pbxKvVkKYRF3O4d@fHU`;5e`U34lNEGtv^kn@eY`K%Si)W*Ee4dJA(2=DkcO
zt`J`8ZYVp!6ZJyNN!|-gXgS4u_7i=kIh5B!NwF|q3}rIIc~&}mNAS#_0z1u<;p2)n
zXL!2rp)`_LNXh6Zo+kws(Y)E+pvCYGQ8M~0@Ag;F9m~_y1H|#>{0X<?d2SxilEC|m
zx<=3OzE{BCMBW<eIy=u>i?$$SB6)fDK}_PA=rK&@C0>O5Mcx8G=uY81IS<+;Ue#XM
zP38UZE|gy84R?VhjTgKYZm08NpJUorcmXtcl{bmLhjWeBKqZUoJk2&(%HS=03G>b5
zMbK|9i#K~A<g$5_=o+UrhqsY>vvPTj%V6mSFO{0#Zt_a1A#sbhmwIq+^J=4k<?%Sw
z5S!0)aE3qu@9806g}l9#oGs$%7GkiNH$;7&CA=m7J$O8Ks-TteM(E94&O1d{knZpV
zl$xpF)h&eTN-Hn-V+h{my-M5GJzh3d8Se9*y#(R|o_Y-Pt>W!?A1u{8J6~w4;a#9x
zd$m08b6~0Cjs6R)o@dyEX*clp&4reSyci2yYvhg4p}C32ehBeq-qcN?weX(YfQ43G
z+xt-6#<LbjV`bZUTjoGp2QOa;o=#rn67Y2K*8PCNZeA>vczSr=P4K&)SDlW*0bcKa
z?>OEtWuzYQoav(Y5U-ySE{}OHr$c<07e`%ZBfMSIC^pJdQHJyhPf9W681Hq8Wyg7o
zt<<dhly`Xwc%Jco{~IQr^J0GmnBYy`4jw!H1m*e;^SkF`7WVwI2mlBEv@WP|<o`}}
z0VjU%Ob8s|f6)a2XTFr4Vi*1f$~3$3m$id-l&@I~EpGflN{Srgt7`z<`F-P75Iy+4
zDe&8qf7BNf_2LUC=jP3~rAX6<??&y~zWg6Pf;K<CggTv%^D}6p@#o(g$Fu|ZuTY>H
z$mhNeS`eRo6>|yZSG@?95Plpz+9&ufG^LaLM!FzzivK&s(4l-EE=8eX{F_gJhVzp@
z1~G#FI?d@c{~W~`XZX>P0FitSz38L(TH3av`2%#si{a0rIi2Na^#F_IfA>8+jN^Yn
zhn#r+*VCaTfzNy!YjKXhgMJW+{GXO!p6B^2dcj}dfA=YUrXq=-Molou{K`MUbCGYm
z0A8f<f0x1TCH}f3$fxpuz79*5`Ijh1n8wf0!HaahjFRtH_<y*=;8p&4Dpy_O%c!0H
zI$yLBv<&|1--DLP|Fi+LEPnSP7|Q0~z6tRhzTyx(wC3{nCqnlPzB&dxH~9`LK)l62
zvH{>W|Jn`==JC_1WiX%r$7<*<;GeAqt&o58Jg_4E78jT(=6~=Gw3P54ZUHFgce%su
zJA5|@3|8=;9LJO@`9DQL?k<1)A!dJ%pYIIXeJh`91nUF-IXyrXe-|Cjs`(#NJ5&wd
z=D%ti{{dajtmE&dL~A{NfO35e{0r1l{g8jd1l^7NdRpfu{`HSRYvzAz#q3-7;eUdq
zmA~vV<l6W{^!{q+XHbs4gYQpKQYYW~zc{RO7k;xKcJn7wXxqbIH4JUN{J+mYcOTzB
z3=;kPW4qwR0DoOASO)nwz6I?O-=76FL;O7YT|DN$N!}0h?Y2VM2>%5NH%9praloGN
zn}RUkF}~|&s2=C5=yv{7{&wq|ka)(grX#>}{vk>vOz=bZLYtl7Q_5N$7I5<b>;==P
zZQ4O_j*63x0?QF#P6FeP@ZyNz@mvTv3nna}xd{Bd;GwG^qYyfe3d#my$xSek585%o
zKNP~d3(ABL@DLPdQnJod@C%)<y#$Nt#px}0@dprn1Pyl~;Vamj4a`q)AONl%7sP)8
zXZ!^X!vFz-WAtnX3Nki<79?2Z0r6mgo|@M}1XI2S?S#N}Gq96_AE<Nwl%VP#aE1z8
z=zJU|u-MGT^A|2CyA5p-f?CQwpBDULg26L_!_DA{6r7{`LQw)SMds0h?G(?&2!g1>
zaaPdt8bGWdCKZEmf=}tp5ij6Say~)eO%LojLFMOIr$oWal=D6>_=QfU7X)6EX1XXi
zR6^GTQv{Q)LH?3J-vf{;2&66evcT<6=uQ)q&=Z#~XqpPwt_U;<pj{RG^%=l5!R+Z+
z;Om0QpFqnHyq^uFnS%8c3}*>mq#G640xK2Nas&e$fLy^TI`ZETXeIFCreF)5EUmW$
zCn#}pTfh+l%@cSBf|xH@Oy7_x5ERiVr%>QeWvwE?+5Mmu3(~1Qq(rc95wKE$odI5y
z34WxrXt^MZ`ibrc%+yj{A(%;tno7Z)H(>s*U}Y)<?g?fd1m}H$`v7PUtb*J0a;y^g
z`~|dHkU)=9ji4bFpjNPog6TSe%NESHUSJagr4545DP!?aaO61rZ4`8bLTQu0K?9$f
z1uN<RS_DgXK(1AAt_mz|f-JgZ(k^JHa!H3EcRB<*1rO4&KwSbWgU&qNf}bf-)FVjU
z2x6~5Hy<YY1P{jn`UOAGlRhA*o(D$<1(}qZc_i3ON#`NKTMEcM7BsvHmSMp+#h{G{
zd@jP$sKA&H)lUT5{skBl+)4x(7x>eO>#0Dq1m>R!9$CYIJ{L@1j`>aqzHWheJ0Z&-
zN)HP+KY})U;VcTm9fYd|;B*vvQrgr>D8CDEM7TqY`8o?HY5-h>9@GHfD%8&h?Wpje
z50=YK_<%Z%j|m^nfI)X*=VwsnA)KJC!Bc2|hq5qU!q;NK<1JiAXHy@cQzwA0@Y|o@
zlfSSz7+8SNi}v0?A@ei_gM=>BU>YpkI1k!Fgn3sWenQy%G5kF#{OCQ{JtbsFFo{s%
zZFhh$;r&VQFkE<<iU|?IHfpasEu57^cXQ4NXV5*GNZ}{%KwFgXMQXx`7S{VfTa0k+
zG3Y)kJQD_%Sm6{(Q^g4fsI4$wIGKtk3BovP(mf|^zXB79!k6iAcV1XZ0qX_fE!sPi
zggu4uDOu>h1#%aKMRItbB3$J(3D4gp;ok2dkt&=`XUoe%zgK~!2|vfb6|_kg8efC_
z72&t9LibhSR>~7y6PD7`d|haw!3^P)qmauKPVIw-S;EcK)tfCG{}8ks;XDOg%N4p(
zuI`3#$0$_a6guw)c1t)$eNNWf!i)5;7xIM5Dc_SXOgad^3xpCXuoMalsOz*ySV~)e
zv2aZyXeGj-zhR<OIFq8YGT}FCz*#Qb`5Rd72y?%NhZVvw%Gg&57m7f;E8Iq@;CsSr
z;h^0YzD#k#17YMfn60u36+)P(7JhRYx@&|Ubd9@KSWTN>o$w7x+1CrBC}r3nbUy;S
z4~1X;4$vrEK(&-6;ScXYu31<{kAI7B+q*E>Dtzk+Xl+8bA!unA&O8jzA*@hCOQ*0b
z5UzCzr~L@k_;0iGC@a|`+<FJZUg3_dkna<&Scu8=3#ZeEeFuboju;#iUZwwb@JP64
z1m=f?o9JUvkA+`TC^9On_zo;jg#Y#ej0q(?42}yYs9EKya0;FHo(WR};nQ;=N|<=k
zgcJ7x>_om+N-iE28PXtVFM93>r4FJewA(t04raihlc+rjt{o9gAI9IuS@Z)M`fOZ8
zQU5(^qW37%c~rDzJsfotWiE!6W1@mB7<3nXdjXstqBVbEzMi6u<p5qH**LuL7PTkC
zf{%z_NY9_IsN+)*{X`$p+w{0-p&6LJsDr|W0MWY@P#P$@SPEK@Xd6Wa!6Fmo!$U-h
z{a`sEDyPoFlcH?ua5^Q5rKX-x(Ky8kVWQ5j;aa%JL^b9J(eMIbr$uq}n>iy&KSfo*
zNYO0XwxUFA3XGyfTd6}TMl>=3_s@#F=_e2?@~s0FC+d3#CgMfg?_e-N^a8!%&xtB2
zhEEjjqB!BaD1f%m3!-v1RxL?%s{lHaMYaZrUlje(41ZHZKXqg9l4zwTz5h~0v0BJq
z78&V0mL}?^3Q4+Xmm?g$B4Y1^;8juW1ZdYpCl>=;7sb8;yBVTQbm2Qwq$q~LEYU1F
zM`ep<Q81e$diND*$rU|bkGb3s>8Us9rii@(c5jKe<<NOs)cZAnHBV$Y3YahA<im>s
zQL{VzE)>O5oKhs3K^4(rQ9uE(5)q3M(xsvWH=wOd^c_`j%S8=aA$LdAOKIW?(I^FC
zm7+wHzHIJ_X8#V_J<;nS@Tp3)klx<aqKbpytP#z80Ib$3+VUdQ)QNP_m~Xvk`7^LK
zh!)di9*Tbd1qK^MztVQsB<f6n7tNv$4Om)4Isb#2R?!uD@Y+P@X-V5fJ7$5iL)5$%
zv`*2Q2nckEZ1S)c-J&xp(0W84eFcGD(PSNHeIje;LD=mV6}p3GK$NS7Q-dP+8PN7f
zw1xK2A<@hz&>oB0xWI-*e?5gyBci2rupbo_Y`}6o5v}|HO2<SWAA-_x(He>xo{CgC
zF!)Tgh;HaT7kx%=!wJ!fG+3|`H&Y_;u(-`S8$^3?4E3}+h+i#$8b|Q}U0rb!&q)Dx
zL_9VQ;4BWK<d=*1L>>fO#g8t6<)}D=5>0O6)oQqQO#IbeVD93X^po`vf4~Qer`Yzt
zTh-#Oaaiyc_t0C^M{Jt|^S<JjZLNTQ;{DVZeq8+68AN~a96ekN5N}<Ml?fCt>x8x-
z@w@aF4Hj>un*t%?pa@_m#M=chcv8G81C~yS&rv5=sQ8U;u!M<!egVqD#fM%2ON5wD
zyVhxO1QkZlh^J@3Y^3<^YU;#{62Ep464Bz_|6qk;#LM<U_gS%v1rv=GKUYCboOm}C
zDC5OX1aKxnyuKZl&WTs81(qmY-vXBNV&70$x**<q7?zU6(d1gP_$h5W7sVZR5J(Yg
zR$%awc=TI%kt#l$LRE;%V#V9AlqPQNhErF?Q=MSxn%GMDjO*f(?eHl>9CsIjnd0FG
zP?IG-bQd67-1Qsm=7|4127hzKy*FU#hFD_{WjDp{^qadSzDaT5ZE?XafIM*yt$My#
zB!_r`IHwOft%c$p1_&03?I=4^EWSkP!4mPIet1zTZV7;iGI4Vz94;5X&V%3`F+w#w
zYGN_PT$N%AHLTnfzeOACJ@H?=Aa`H9!Uu8>#2bHuYgOVDD%e$vU!dx6jd-XPT584o
zOQ6+R#p|SyuNSM%f~P?|PLbn7aqFvaxKaEs?LJLnkKLd(i+_I+phet6$=Fu$ZaT%b
zi9=~;Y8MNsW28eYr(LU4{PBmFT9-JF-cjA+x=gV2h&c|>*(+X_2)ljat}b}rFSfQ)
zVs1d3)elR9;%z6P`;mC`5Cn(BnP-4K7WY>H8y0Vz0>Ke++z-$;D)!`o_C%Z)3T#Z=
zbRD#D@r#!+_*7i*8k9W~e`*8TbMdAjI65KL&VxZaiG^~bhb2>6f!Rv}5RKx&lkDCB
z)KT(17cM$UYSRFYNYwuYml6hL&0HkjFF>iQ<fn3&I4WtHjfuKRR@g!An8cq#3U`TW
z1i(WQNpB@jiNY4ZOR|LaKyQi5KcM+Y5(a?zO5PAdi=X8EKd2M)xTGZ>+WaL64A>2j
zR8pQfP_lOxSc4?jZ(}f6vcVNth{Tu$fm4#SV*HsxB?+mJ3zK}i2()ksn@*t-lCK$9
zuG124E#%Hf(zjrJBPG#t3`R+|2ZAM9vOfnFVk9rErz-qeiNYU$*jS0B2&{3EeRPjI
zUUFv^TuhK~D6BgtIamNJQL>)?$-{Zc6gur+kjPg-O_C&p@-N8}H%dfYlsHoLB}Ed~
z0f9@Bx9KgMD!F?PsxM1sHNovPiT`2<q)VoVDgL}7`RfS`UX`q-1I;zbi*$y+E_t19
zU1UhwK82-B$ttRCWJ%6AVfNXQF?ZO_k*FqtC0FvxRmk0t{G0-oo050;K-n$Hmv&&e
zE$RI)e<F#c-*LX=n-8J7Kr)@OnS~O;LkL)lBrWvah+@ef)Vow7c~*h>mP-69AW<gS
z;S3YylENC$?nnlM;7o<&-K&^krQ~g@2;G%5&j9V7<bz>=`;z-#V1^GQt+eS@NzQk|
zwQ5OKC$Jhxr4T;VN+cA9)=B=PX6JgV<RqQC8ze<#(DqPrjOt;Hl5YB4HAyy5E~;7b
zcsJ~}Ncxuov`XH_wq?^MDT;<`?UGZ}Qr97|P+_!Fvgr#5bV=^fRnKn8O)XUSNctau
zrC0LF=a^Za<iG<gLce6~zZe{lSf4on4ocQfg|<hMc@N<Jki`B2n0PFCV=2I}<a7yW
zBa-XW;NhsmN<X$I68QiI$0YOjz^8GEJs(=0N_I2@Jd@;7qrIK9hEf)XrH8+SYxdH8
z-Z1YVl~D4^QTo9P@WM$NWu?>T5$Rm&w|ABbrsC)2BGuqvV&f|PoN_`(rKd*0;wBAi
zg2XXtAf0L5rA}!O@Q~j41(rOeg%n<SNjHBDId5q}0yur7R@#evr7Q{7!cUq+{c6Xh
zvnT`MFLnC@S^}h3-lyj;Q2HU|$%3RKj+k1o^Z@-!#}H{Q<w{OSf6IlMlhWvD&`wF6
zsVEpK-SIYNA0~ZE16sJ0O<e~O(%0x2IW6Urhi9ZOuYu}F>Ck)NjFMJ`KxeenX(g~2
z>DmI=J1f1EMV-*G(mDq?6({{C6U2DwCOUN|NNtv3_UEL#sHm7I{gIaRy!3<p5WFB&
z(zS>rX)~1wlcntxpInq4eFI*kNMDmd?vivY7o4e5jV<h6mO6d`)oIedyr3mr>K+Gy
zE7BxXL98}cr5{rea80^&IYzHbqjzHwGo+SlP?IUGya`&C^b;L)XG<$apfpFiI}cc{
zR6wWh8`3r5kh>{8PkYKO=@vS5-<HZsp(RiHAO%>yltZWP0_k5SC@Yly{01giBvsHc
z&{`}lp`M%)sYC;bQt8SZm?)F_KLSs=)Wr;*JJS9g5Uh|kDWI)V`V9qgccoAM!8+fQ
ze%J(O?n?*w5O^RBuZ2LB)R+fl)zZ1kF<2wz*+Q;X`oc75sgttOL93T4MqswlD*cGg
zv`x}k6ty%<w>^h^i}b1h>(wfK#|Nx!QssWIv`gz;AkiTmq+Z2N=@-;R+9e&O-jr_X
z4<2x)M><*yTCX%S8V38MK`X)1FO8&oKm*b^3Oom;Q>j(?k@Om!jEAJw==T60OP9vO
z;ILG80boShasqyjN?-UHcArSy=`=Yet*0#cxb*8dusoG|%!7$%(pQ$i!{^e;+o5|x
z`qC88>|~n?A#hkWaT2QSWyv)dbdd4C0_G^|W<$V9R=xxRM`Z6?7eT4B%#psw<09KY
z=Mz`i7TUIs$|f=4zMHJ%99WLY0$8BA%ZBJR>LE*S1dFH4`CR}n8M3E%@MM!-hJcT3
zBp8d}D~s`lPCr@FEr8>)lBJOImyNoEB|vtScG*DLFTYbZC`fjcw!2`NsvCZX$W~p%
zv`@$)DPlb-Yixtxr(_a3Uxdou_rqYAY}X3-6fSF~R9J*8nqq;|GGAKRGcp}rSdEme
zp+`JQwk8Sd6fK*X0nQlN7@eHXLMJT5%I3_WZ!^TnRMW6R@v<HCl1h*jp9ArnER_;m
ziL#FGfSs2mHo)%-vLMQ<C&|uzgE=M3INlJrDD!fI(iE9z9#}5Pw&%j%R9P4u1un~m
z4?#<sEN}t>>9Vm&aOR5amv`XdRoVN4RDZuF`#BB7>#{$oJvc+grBB;t%9IPCCQHVo
zcDr2J!C*}LhAf0`Ioy<~?*iPCeQ^bIx-HXDfhJFuQVFH`vT19fr9ifa3gCsZtT*9W
zk?gY&cu_2yd<%mmve-osFO`M#!x?Lt%&rk8%4H|%cXda0hO);MGCO~$sgya=_v`M;
z44yD?PuB7kSnkWV&W7Lv*|SE_s$@$iV@axIX}`h48rh%>Sgq`>C7{*G=FoRy>Sgon
zKx>e_GX`fK%BIt8;YL~25a!urmBrEVrdcN41kfVesfK*3?1B}bO}3n(%68dq3cEXG
zWAy-?GGE#}yJVB7zSJ#S^*siAWLNjX!(Q3DZ^QdO*<q^1^ve<`QXP<8ehk%vvQ5+|
z`bbttZ`dJOZ4$&E%dD<F&^9caS%5Vek-fVf+D2vHwE;YlX=u9~lf6xG@3`##X-GVk
z?OzG(nJjEIls=bjqT7HIvMOrow3GkzCUhT`mk$E7m#;hpnuGkiKQK{8`AjNQI>~>e
zQ}+?MN($gC|DV;0znY7j^D+co<<~xi-J^0jHCMXHm2~PpCTCDR+FibVGqicg?^9^(
zDId>=c`x}l{lL8C*_1)>kw2u|nXmjzH+1^Rhv+47T%JsCLw~vCAwYoqtrIX5D4$e|
zzetdrb$33L2FrJDgG7kDiGu$Va!=n+Bj;ON$Dle)p0^oJgv)d3%pW12Mz`}$%LC#;
zi;`#l3$bXqNe`Vd@(`*boRv@SfT37<8I_gd<n~9w5-;CIp-Y0ikKVKA<ZfpnkSMoz
zhQN9G6gt*lkmu5wJxPAA8dFJ@Pq$LcbWv`km^MY8M(?&u@{ChZlPdS6RK;a^>ffNH
z$(tgeG+n;P8MG_%`Lx?zm0zJ!<~8{;+WD``n<=)-kRPI?NT&P+`gLT<UH=BimS3C+
zFLLCyAyAepm(Vu`Zpc4a;=4WSRjV(ZnDXRDG!W01C-}iafjpT0WQFoQHCWyvxm`K1
zVtE<`gC+916A&nsFBpfrW%9S^uUalor=aYPe3S~-74iwX*Ip^-(I=7b%H3W9?Vh~p
z3f#RfUwIxAdm#Ts3PV-$o7O)-td@Vi6~r3(1G>9bD_=@?5$fdgsHvo0E}RC52D#l-
zOyZ$DgK}k!@)e^PY?5y|1D0kvn}X&Rc_N($TIG)KK)g-9*aS!0<+j@}>kj$$FvxYv
zT_~pOk_Yi&zFS_gpRQ^4$TjqS@0Is$hBJNgfx95~%a?3`i2-?-1Hhm><t>0matj5K
zL-KZNi+C)5kG>K!EdQ9Ei4l1*y+cRkfBgz&PvqiWXc?35It$mv<^NPd{HgqXDwIEy
ze|`yup3C#zqvXJZyp8HBc8d0O7(J|TeH9Y+3OnizaZtQS?b42l)k^`K6j|3nb5X=j
zz>=$CrVN&jDqM{ibW<eKC&G^@?o$5UU7=e6%tP^_1HAB5l+dr)OVOc$1#iW830Qm-
z%g)jj8DB+o9f*DkBnj~_DSixqQh!CG8ypT$eEm0Qfr>)97#5@$pw`!5g(d^57NQ8>
z2XI1>{{*u?sZb_B_bJ8X*YHCMRebUo=ED@}bYuuu1kMH)p<r%>z-h%dD`4S_LOmVI
ztdWWox{4H~xIjg<XvM1|05OUS_n`EwB3ci-u?m+-n0=h$1y^A4iXU*bz$QVl<r<Wp
zQ?%RzmZ*5E6WDo0I$blmpkO_P-6Vx?DCCkAFH;xeMMWePx>FQ~D4BRkQAv#(sa8c~
zKIAVecFlmnG{whMx=mMv3n70+(U1*oR~057VAm8ip<ubL=spOg8H#`DO`fUnSpb17
zMH3r?*$Qh3upGtOtH5#<Z&BXih9Xb_xtogVy`bGv_)`w`wxWR=uJRPtFT<fbU-8Zq
z@DwPfZNdr_DjL25u}E=iIV6e|r8%ILDBhS0tW*&~$*MBN;!Lblxnki8n7E_3Po0Mq
ziY)p9Or>H2z4q=ZHh&CD_Z0eeOya)cS{MW#DC94}UX|ikGX|>_yRBJZtx>!|FVR}X
z@HSv|iiKAJ>J@E!0U8vx^vi#!_?uq(jSAjRSm!3iyfO?nD=PK_Yf<z?!F;PC`)xSW
zrr0KivQ9<LzhLQ7ymJmL-HIhtqV7@bq(4lrVh??4s!!3;VTEA7V%rMn9#H&E!PTIm
zmI^wL6pKP2KcujRK;p6D#2R43idht%k0@q{ut1{<?L4f^6UDMOG3_zM)_I_fD;8E@
z@TuZ*AXGn7Tv&|3=ZZ*Q%w<C1)ejHtlmm3|Kdh7p>3{gxE9cYm>!6(M0i}*gRShgT
zDc2o?#1Ul%MLy2T@c__Vlm#21)KwWwS;V8tIZHuvQ!WdD_s5h6sLbfDTss*iJd}s%
zKh=0DXH%uwOF5g4Bi_oXE)eih?)VlgzRK`z^grzVl=rB(d|df?8sz<zAJ2t}0OfmB
zJq%QS$H7_zDfbk^V6bu$^(clY?+ru#gff|e!IR2Y8-Sfsj(rI%R5_cP%)^xV_LxMt
zGUpP+Ba}riVequFhSCUUlnHd`j8v9V9Ak}Aw*D7BDhu0y#wg1ufpAu-4FeXdY@&xF
zPU%2faJ=#+bs{7v*NUO$obvbMu$!ois{%N$Jox|u7nEOhLwAyLmklPGtQ5HeTvRg2
z?G$AqH6mP6s^~44s$_13>dRJT9rfU(DFb*gk*-Xqa^n@HMGJ|m%7}if-Zf=(Hr&6i
ze4nbj8OqnzK~1L8Or0iK%A3?bpRN4a4?g86cP@hNTxB`k0lcBS?T<CQsg%?4=a#Z2
z2HxLR+7ClKPwDOltWas4+Xu8rIXWA<i<RY6Q!i0|_a4lbD#PhB-et-K2C$SX|2YPU
zJIa@X!BU}&rb9xdGJ-NJca^hW1Is<-#oKW7zA|qq3_ei)I|l+)%1bF2tX8&Aj=V-W
zcRpyfO5taiS)DS?`U^(um4D3#Xi$DJ2;xI!`?r`(qjHfmlr||1Ct;#l`8j<OvqgEH
zPO`1aBI@yIQ@YU=`F3T4J>)u+AumFpQ&~O^@h;`e-+^^255!|;JxUikd-f{v-@owS
zDPP+O@qT6eFBF6hDE%lMFsLkKLCqtjn6|AU<vS73{aAUo9@wxlZ!H8zl;XeP#i;T<
z>RNlET;KvrV@fY#8CO=vg5{|)h&q*@DJPad^>d}y*I2Fz<=?+SnVo9?ePD-G-!ma@
zuad-5a?U{&OgUUf)fRd!IjQ&*<s4Ccg4PKeXO;6o`0b+lwG_HtRlDf5a8$KW3oqPM
zori%PQ~lu#ad*`wdMA6RCQS$MRQ>W0;$Er?Ct%52l{*0QKB^CvK$)*<>wmR4)pyvn
ztTxA0o|J?2R|)RJe1K~5U4TGU)E@vrDxYhh1*?9bcq&9Seh=~|R8f>HKB+pM2QN;k
z?5TS*R5d{TE@3K%5n$meK7Gk0LUn>R&C@DZF?>3sntuQwQl+IFTa-$x#j07ORYxd>
zj#15|vc*}|l2Tx?Drf5Dj#Fu<2_{+f(if1psEYQ*L{n6L)K#3O%BQkJx~hwQ>sM5L
z_F&0S)lohyQ)NRRWXV$Ppl`Pns8Xq6q)4^r09cAucd2YpqAH~ycd1pinf^d!s$9A`
zR<0V_1*h()OmtYTP%(aj`AXIBeX!nBRc!$0eU&~2YxzKRkIueTDtqc3s8-p&i0!UM
zRWJa~I@JefVX0mvyp1U}sIsX0>!B*V0pg7+F_jIPRr_gYX;E1t=xYhBs*}f|txe@d
z9lY(T@#B#1P}S1vb*ke1AknSrrLeh2^<x!SdR3>-gVv{7V8UR(YI+&m9#BnO0c}u~
zOu_Rb)$kE$8B&F1gZ5ap{t~cZm6~1zBdTSe!R)9ib`#a1o~WKtXgsEh{s7oh)l|A7
z@Jw}R4Zw4iZW=tDP(?h38as7~1!@kfhc<xbpzbSy+m7m1I<z{ef2ZWy5%rJ90G!nZ
z-}DP?YhVYY-PJZ9gV94>Spz$s>W|U^yw&BD?)OojyaScK>X&|o5<m6#RF^-lKGX@|
zuePP$>mc<-8B_+VSJH7JM9ruA=?V3n!=Rm14^kfLlzNcf{o(2rRMm`7Z+jaor`65Y
z^%#v(hs)qawA$fy5M$J7egJXmJr7_oUhVl0%qOTFD4%p*-ToMy7u46MLOw}dM)|K4
z^~cl?eo6iQ7+6x(Gw7?H>1y*mcz;FxzdzyARrOSFD9cbUz74rd^^8y8eU{pJCN+O$
ztK(u}Fh^Zap-ZlME&a)Fsg36`cw2q56j+}6!xYf+)m4=4FHq0<8}fzf=}I_Lq8_FD
zE~V;LD$JFsvnV-SuKu3xT-;HMk78vi)HRfWy{Arm1o8XoX*0m`K<#ve_Lmy<=K^S}
zRiEv}ucJ=QPXqQ)t(L=Jqk6&vtW9bK72TWF^QvH?MJ=G)4z22NdVBV&J#JyJPd!lv
zmVWi?ltdU%=as<jpn97Mv`6Xy$`}u+MHK!$R<r1gGpt^SwYS=gsG~B$Gphb%CG0*?
zCvE`Gm^zB$p>cH=AKIR(XO#jxQ+rXj*>m;#+W;oi)zp-0r{NyP${yByLstUqHRma=
zaL_E@4`q&;c1N%{X})R2T#jf~ug0LW=FeN;#D2dJhODldZM#7{syTQGvv<?D&{_GI
zW>XK$yK7zxhi(te?{)y58b=Ep_0h<wbm^;^MZ2<}=0hrCAJ?ou1K_XO*aupGW)T&m
z0yXP)!eEf*lPT~iShIn`zmuB1bbLCcxxW@5)T;5%fQw<8LAtmSuK9+l&k-7ZF1$Fc
zS$!Sa&S<`-w{E1ygPxHnjYNpSXwB!}Lq10HgBr6qtC>L|PpsxjG_=HNCQ}<kf~JiJ
zfpeP0(Ey2>eo6_R*Elvp^#x5leR(HIV@;=wXo|+m7iunP%yeW=)$~!D=w(fe60|hU
z6*|tRYrdwM#}&=}FX7=;O{Nf>*EA)RtG%unp`t;C=DrD9GBum&>TQ;W^DazeYwG{P
z!scjP;s9=Fexzd3Z4H-lmwB3IE4{_?H8;*dX@SNk4ibf$Nfp3~G?H{k6l-R6LU)Pg
z%qGxEHPb!<DAW8(L0!3KeKW-GXg;9Ra)qYh9e_$r#Yup>npHcnY7aC+H{eW_#x@zs
zsx^tf1Jr2N%!JNbP4;9f{xS`k916!CYUYzOjhZPGx-@A@A|c<b+5Hmc)S`KTS`Jz@
z-`9cGrtv(CC2iNV(TS-;bF~1VQ==QjV3($3HcWJD>ie-=J(|t5k@jl-UXH;5%`r2a
z8Pc5lFJ{-g=sq3K->~LTDTpJQg^iFH)yU|~{Y3NOMpzot*!>LJxMnwPxlc96sCD3(
zM)e&mJ=ffC!r+AFu^ww_udSna#zC8s0E3R&htwP4r2U*uq(`(1j$#td+VBpTchM$9
zK&Pv=;}pH$k7}K0_j1#2vxU-Q+V(BL+_mcpA@8L<O>a1Fty3}teY9TGh2g8+Y!Be4
z{Vg3zk84XQ3lgY3tAO1g?Q(kg25aZ;g_aQQq*oz+LYw4@!IN64JuHN2V=2cFuKmIe
zURWcvZtdVXt<B7b!82O#hrlAW2hTuhly*!GELuBd5hP-?`p+P7R{Ps&Xp7bUdm8hN
z(@GaYE?K+kOR!wjZl}a?indw-xl7uR0MJskOZ=ehvi5(Mu@-6CrxlP(*UqQ`%N473
z_cHi>Rhv&Och|I<y#Uv>AJE%ALwhG4Sf=*rbFgM<L+O{0t=-}YZ8_Qpw58>0Px-^d
z4egtBefg$#7j6BwwC__U^R{*pH6G<@<F3QCeC<Wr-3zpFyP>mC+w>PWi?r4o&mdT=
zUHJ>9R-)a11WHS_%@iM$X+NhOwOm_G8{-}A{O1s?(6*hz>?^fhW;k<Kd*Uv1-_uSp
zLHB*F{fBV$fp$LS+pDxO^uSkZ&2wO(Myn8krB)kv7;<&mm9$OPYcs5K!PB7SQby^a
zw%!Yt8nuyh5voaRSr4pPTS*D;7VUJZ2DNG{FT!A(cHb1x+O<Q&aHc~WSBAk(?M}Ka
z-le^M0pi`-_y2@IkJfi3eCpNiGyv<<*0zGPUt5p@mI3YA&6NBf)b64CSdX+nF2U@F
zv~w0g;<0w}bT~Y$)ltS`L_2pMBu2F}$^f2d=l6hfOgl>DwrAQ;D6W65RZB3@3GM!4
z5U|&Mu?{Q_y6sbeIqJTh1>mGRFank%x)Iv^oOMp_^a&OhT`n85aMk_F!bFeiR(}sc
zH{G8+@Ep?}*aiuA-Owgj^3d_<q~)nwFM@!VE|6kTZ(ZFV5b)7$?uHk>Ixg)+e!6{o
zFy8<jhYIR}I@>6i57I@bAP}r$Wr8zAH-Zwa)#ik*pKel|)XiOh(Nnsvec%bzZKuOR
zm@eB3^5ME`??YRJZrC2Q)4DGNpq<hEMRkctUEJ%SMd<`opNrPn7~poS?hR^OkJH_x
zeK}sYs|Y?N=&WlniF3My=U_?HMZJzmSkLRs0<d1t?WF&Jm!#{bBTKTbl#UJ;b+R7F
zr|3TW5!fZ&2;GTE)g{cwB3#yOc@EdoblP_ym##ZSD|<!v64ef_>NF3a`<m`W>P@<?
zd+SH|o1rt%%QRExMS)nB&MzMz+p3!#58rZhC+<TqS2wf|25;yp=tX~1H@XQ1Z|R09
z`*K@1jS?n#x*cI~KVSC&eXgWH$BKaYLft>~(S{;jXfm*3-Q{TzDA9dJv3IG?H3D*F
zx;5dDE7$4he)k>So?+Ol&{>xXAW^CFz6YMWy8MN(dry~1w}bENUZy0_1Kp~#P*bHF
zJphB%x-@Dvs?nv*g0@=S|ET6srwgSNRK4!E0Vr$Gb<6~Ks5?vPght&i>Zokeg;9pG
zS-12z&{}lsw&9P~t`l0Ro3}&PpAHk9y6F@rcj<nV0qfSyrl_Mwr>}&3ukLRO+WT~0
zd=9~W-H;jD26Qthpc>S@5dwc7=@RI=-H>iRZBUPOr>OgCSa&E09**dic|vYfx1b4w
zPjp-8JTRua@;9At$8|2$clcD-K)dxbo&F(sp6kS0pnF0$jqZWi=`Z_3>0y2JG1#@&
zf186r2mPC0z@Vf4ZWJ&leMS$&kLZ1GK&P|*O-jwX=s$W5G*^9h7t9~khs8j(n?7a>
zz%jkk3M#(2>(k$YQV)IkD#&~4gXoCmrN4C;YP|K~AHc4U{@0iAr|{K_Z(-0+fBA2$
z#c{pQD;V_G`?4Vypue*oCIa<N<XVuvX$V-bKIBWVgy^?sVeo|hpLD1`sgI==qf>gP
zlBtuX+Jx#&zVBS0Z%v_E^l5zwWg4RNKT(VqtykNFGe%#Y0kdcI2Q~tW)qf`gOPqc$
z6~E&3E$hLVppV)P?4172+t8AzZ%hE^dHqqUm0Zxz{tyC5`mjn2ChMP4E$X8FT_pxn
z^x9Qe!b|$!tvf(W)&Hr-bT8|7P)k&re&I{tN!QP(rM#jqGsBCk`XyN~cuoIn6$G#A
z`2nz-p}$9gd8U5e#{gOS+$eBn>$9j5o}=GGaa68;*BsDp=$GeV@TUG>N*&$O%i^Ks
zwqC!E5{-HKXi6dF>wAC0auw*S=<0c)ekJ`Eiz0n2?cl|FEmh!4^oHMomFj1i!BVC-
zRRAm32Y&;*cl1Lq!KVuSOKJ>O>Qm<f+|?IT`r)2FCK&?v^)Ft4GY|B?AA~@aK5;U2
z!B^|g(2u1?Klv0))asY7#ah(q$4UU|^=nhH77hB*P=JSeo4qj6tiMl@SBst<1QV_L
zt<T_SoBr_tuy%dZTj1=_k0e58r+)K3aCYfEdH}lh8=qrIdh`;iZ1w7gd~C20_vzn$
z19toM2k3Y)pdY5w+@L;<zUKQ#AKD0sA^k==>pa#cQ={RqzLvIx5&dF&fKmOU&tdS1
zK4d$<n0^7}8^`sL-oT#fmr;}UGkrAOczmvJ^M|7o`W%X?><j`8{Iwo79C!lr_68OQ
z1|1A1w?fd-AYTsPWMI02^@t&X5@61TBVR#{iy`?MoN+Z|o(Juy;hzM^xf!Njg0^D@
zM@osf8|v#I?qRr3;f1H+<$TQ7%P{T*^WKK!i}1<E@M;PMeXRz3JQ2^9p@0W%#|?je
z221{i?|y-{0K;@H1_KRW(IyaNSW1^MgAG;mX9_U{?SQruhDEd$oitRpg5{LqMJAMn
z8h)WRuL#52Ezok>&>IVI#$ZoB#Arh~h2k-Wf2c$Etid|^IvkES2tENZ!LUIL!E**D
z4@jgM?z+O#WkbnNU`aEm>|ik6u(2MNt{C=lG3~2{gLEpoW|&29*z1Om>D8EFxJm`)
zOhec{aAq0GX2DXnp>#X6<QSgU!%(i_5$%LG41-n**=`zK=>T=hu!3s#w+-$k;K?%-
z&jC-qA>a+DDKK;jz*1<iZiYaSVb>2ZSZuiVI#@~!OQ%7u)bOeda%G0cR52<yRE@*?
zJBCi`QmHV^z>m$Q(y;qQXt`_frdx&g3~}F4BH+Fu;RYlg7?SBCZj~X_2}-LCU(zQW
zY7BqTqgHFULDy~S3?Tsk^#;*uc+p^xQnBWtVI3VU8x3>ll+k2xriw<h;Wb}qX)*j6
ziNRJwC0+Y$GZ?Od)^3=723k4{em>NN)M*HL4EMVX-_qZy+u;8u)~m;0rP^4pVP_QN
z`wW^Ffb|=)sr6;Ru=o{VgNFBh0Ouovfa295!}qDs{n!vjf97Gs+PP3RVyI7mrBTB!
z0k9_qXX?}&GhFq8GvkI*T$HxjJU2vB=3&Ah^@VOb<0^_K4;w=UvB365bqcgO7$-l3
zK}VyNx?G%$8afOfF{b|trOw9BX(x6u_RxhdS7SfD{*D^`GNH`PXm|nQ$BdilLV>$+
z^$gHFjFEKk@idC2gJ$(I9(o^2y^Xgi4ew)&qs|Ur<I+`N^)o)E!tZgTH=U^cjUQ59
zSb(weFgSyaq4eemF`k@&?i0oh)GBb&IB@~AQ^x(b;9;mS!2v8`#waOR!i}F&0y@Gt
zg|wVDezXIs&sdFbU4o~P#*B7=DC0Eh4U9HcZUKlf{&pS`XN|=z&=zYnQ^q3B=t_@D
zyz#4VpeDg6px(Z7#v>V^B^p=D;Qe{yR4xQA7z?T1mSo)E4lLPNoDXL%8sDZ*HKiC+
z?gP7IoDumK1XGQ<zH4r<turYnf7N)7en{7hml!Z~-IzNEzGN7$RADgFI8+R`vy7t}
zXvsEuQoSq3m`x47xyD`J!rdFjKXT#HO{3ynSh!{UkOx0+8-FhVmS^<r1TEkAj0&Iy
z#><~VS)nnEy1<K!E>@}v6&v&D?pulR;t2?r8W-tczRY;g7IP^#4lRHecZ?}NL%zaT
zw+IF+jWtweziT{cgtmLev+FT<-?$(NK0Pqbpe?(~7)4J?wQ<uU$kiAd>D^LmbZ>y6
zI%5Fk2p$^0_ob+)(YP!V2Ahn}`!Tg<<GCcrw-{$tz_nJRH(j`DGd@}YHSNY<-iLgL
zv4R>qI*r@Eg?N|oqg)7d8>h|$OOJ6k{at#EHdHC<GX_!nT)%Pi9MA@giMK!-G%~22
z<&kl0kfNd?V`w_GJvO3<jK|0rLhY|3#tC}Cj~OdgLw?+Ng$_PXjTzlg^UT<J44lu6
zyI+876UG_H-rLxjJn5d<VN>EcaN3)isHo&%3Zf{*(e&*MESHnXfl5S2OxN5nduP)D
z{0^)(E~bq+Fz;%*N$H}arcBBMxS3x36FkREA6~%>-Axe(pv}W%{RP0&^oZQ|GF|=)
zO1({M=r)FrY2X|9>uZ`%fw7;dNC51(sXi4nf7AL-=nOEq(xw$?ny7)JL8b@qV$d3F
z+CgoSA*PYlKu?&~&^~q2G)Aw3Q>GM(WkXFHsIC}hddU@7xGAg{x+6>(tr$FQdTkE`
z&X|IzL>p=Pi~`Ik(?$ink2WR6fhETDkUG83ngVKJKGqan2M}j!IfzNbTTQ#x15Gfc
zaH0F0sgIh05>1X2d!IK+Zi456X?8l~lT5KQz?p2aQbcjlbdU)zQcTAwEq2Kypkha=
zY3C#?$z{{WloL-gt)OB@y6K&bSl=tA&#1fQs>zYcgV#(g$3eSpva-A|nq@jDgnYIs
zhmJZqrdPy}&ou?k0nZIn>@d8zX}W2HUGkRcDxLgqo7OZyX`boVM9}h0cHsa8rkm7T
zQE1xwGfWhjl03muY|8uuSc$2T0}G|5__tx9%=F9Wm_)g0iIoagcTDy4YOXNtqt78#
znp`MyyKCaL0o*hF{UK&}-!zGG)elT=%OF@~s$UF&YST`t4b_-_^M>wPQ^O6=>P)w(
z<*eSMr4YQq^c7``9-6{zAkb*q(gF{gOv&q^y4iFvhq3}Krd@RNq1Dvf4Z${39-WKZ
zO`#R|?R1zX=*`?|+OC2`m+70?@UYvojsmG3lduz@*EEq1-F>E8uAuds=7s_cnEc*^
zmO<0yAE4!t>EtGWAycFXh8~;vxsV$+*}Y6J!x7WY(;$wT*03P)#B`qCBV(p%F9M94
zIF!+SYMM;dzGtSW$<Y1WG=-wF36t_Q2-unT(cky5`Dfa-?9FE%K$(L%uML=^Sw=TP
zoy_Zx!Jv!z@Aon2Y8LJV%Tcoi*Yd13ZsuYtYaTPdOG$Zm^FI2%iHAAlTP&%kSwl^A
zUgmeHgUs9f?px62W8V4}27S#>i?G0c=J-&|{<yjSa{zy{iLwF#=8i`Ifo2osV1vw4
zX`=`>AE2!)#9XuigD1?_BVo^a(%iy;?o;MTAHk_mbK)|n2{W($1rrT7fA%#jMVN!A
z!SJ*>_X_0Cn16Nx7HOXA1-U45dn4qc&2J8X7GpM0mGP`Oj%cywEj6IUnFCisS-klJ
zH~5rbE-%7To-;@KfF;pt{%{<E=gm*(9d*HM8w_HS*@KF+$>s%fLAz+~r;s|u+}{S;
zCG*8qP?KtYO4sNwn*}>Cm}Y)jkIAH)b6$YISIoime!priDg}1UoDdG$b+gkLyvQ&w
zUkdR|bIWR&&oW#0Edfuq`SwCc<e1yK!INv=s)ED~^PY8>%uRFbC?sx~w;_<Txoy6f
z4S_tf4gF;E&8Mizpup^t0+vE^-8;Za%%|1xx76&J0hTheBb_eF&1)H8xnnM+f?kDr
z6@470()`rA6WZ>Y|J;dL+%rc>Fzx&1g%krkFw6YGT4k>516FN*G!+sx<{TA0YUWuP
z&{k)@OvUed^Ur&srNO+e44e<m3!<@VjpmKhFr_B*7uCR;&0jo$>K60gY8YxYFQ@ch
zn|b91E9TU0ewC{A9p+d{Ms}L#P{7$`Zu5mix4HQ`upYB$E_C;rBaJZMXZ{S=l5G0T
z{c9jTVCFsmZP2_q4YWt*J+u`LnL{WQ``COg8LkbRf2FN(#9T?q?NM`S0_2{UOE%JB
zaLoMf7%YvOXYgVEsX2xLiD%|8iVU8ce^>x)!kj~!ke!7&0yT#%H=KakTTar?!@;tQ
zIxrnA@BRyeP8JC*{t?U34e-L*vX)+oE*4k1BJ65;XA4-4T2@hCi<`ykOS%$v%+mc0
zB-|~&6!v;pM1e5qX*v2klzLg_P*<q8<!!ow?qg{aL(ta}H5Du&mR!n4oUlA!4NE62
zKMcXrDa*?vSc_20qJJ?MW?8TlEa8^3{+MrsWt<9{r!8NGf_BD|)&-h1(!!t&X^ds=
zOvs<Le7_7lu@=X0*p0Ky8v<**MQaC;V0rI<0Ou@E_Q26Z%j6cYoVWB*8`A~L;Z*=h
z7XP(SnrvA_;l@Qv3Kcd|EH6?ld&#n!PQ<B}g%@DqvL&99H)&Q2%M)n2Wj1YoS1eBp
z!Ftv5>SPFJSU#DI`DR)omI7p1&aMQ=wtRCIAjeX56`Z-2@yYP%hQ(b4EjKMLlvlcC
zIZt(&+m=#F*ymXeDzSL^miQR}1(qdr#woN!eh*rag?p8H4T>$o^Y|N-SpG*Jlr6RV
zOBu8>OOo$E$$Trn6`c1hQ@+92eM{6w;CNtpx*E!=EGr(uP_@NM`KTI;|0e*omPEP}
zRcAR#m5_SN0(vGJEcVMG_t5fZJ3yo5%q}Qvvh>hRlx9mWJ!mbKAKwLNwa6)f)n=J|
z8fM!qkyeW1IxHfpymnf`sd=Q!@^>z<Zp({1z|&*tH$kG;BAg9cpJh$}O!Qlp&4ac9
zi{TPj1}#&mGvkrv%I|Py$kIcft$A!&PUqTTOV4X?X2fzpiC@l`WgSJ^;}&rYz*EbT
zVJj>>vp8G_`rOj>2Ar9&oZ18Iu<g6l2Vid-m<M?W+jA4J>uCE5{gs_;d)i?4i0y%P
zV9vIiR$wh$Y>O(O%+)rMdO(ia4llx>n{Cz%ICISQ5S`=QZQFi?qaL<jP>-soZA3YJ
zw9d=+Wjk2%wvDB1k&o?Cii~}24HW(Q*=Er@;<&BvEe!hGX4wD>uyyc&i9p+=a?B~n
z_DxC~2HV!W`+ttEJ1*<$`>UmunPzFJX^w_jX8O%%@4dI9GRv|w%ciCED|-+T5ET?b
zWG`9DMp-ILkd4R`5J5#{$xvj-`n^y5b6)4(bKd9N`+UZ|=bZZijsA=Wci}|<<Lo?;
zKt^*LECn&%TnW8k#^y3`A&g~IXdBA-77H)?^e{#wUBKatGP(`UFgDZvC4!Mm^;waO
z#|r@(#YhXnD54p5S~Q$vY^Pf~mN8xd^Kp!dQ8*gUU{JAr0>i-@dWnq5C9ssl(5;7h
zGQ)=gu_+ASR!E*_Os5Un1x6V?yX>iqGhOf|jj@qZwdo9Jx@a;O<4zFGW%$hlXddG{
zJ&LX{+-b>`&zMeWh62VifAn2tGz3Ath!IQ24vQIcDT!9Xn7sw0l#zH2B4vzO-$SH=
zF?0i%*BHr1(O1c+FG1sVJ0p?}v?_+G3U+H4X_SAeWmLZj(K^QNC~)<R-E>pkV7x`w
zV*?|OYAYHUAC^F*iD5hfk(-RKI$*w;u}2BXTZ~90?6xo-Bw~cEj9yyv-)1P@gUB6*
zn%=B;89@|;Y-89TH39S<BVZrq@;>87O6fgdC~0xm&T#kyq=WID5TKomkZB-YjK3E{
zv72#?Zu^IfM>k-;hY|QA8haVfri1Hac)tLypK*d>)Q=dw7MOp`$fB~)0fw5~e!_U3
zVgrMWG&`+ph8Ty`@a-vM+fIOvGIX^29Ah|8@%uPq+kK38f+2hbl9P<=eSkT@+`AZ!
zj?8}AEF5HZje$5Zk2BGCh#C4mz+9MzsTRbQx$9$?Kg^7$AI6P2n^J&Bm>VcnbBxLV
zoT|*+nYnck^<eI!P~CB+*E8rm!F*vCKs}ic2BCP88AwYmFXo*^Al}Sp95J+0%>S*0
zo)2?cAw*6yLus4q%UoTJMnC2tExP@gqu;|q0Q1!$3_FmyMGX?f6wyr?%zVXxK3WjM
zEch2}D0Ak^&<|slH-Zai9()Ge8Rj{vVvk_1qCj*c^TlS6C}#O*5Q%1fq=iTf^Z7E&
z#aZS-H;{8o@A)9H%%!pT?c<nZW+=onbAEw`3Cx0d;1ZeNP{~3Hvn7~TsOOoi6gYf=
zd5yxJsm#@@;ddHy-CF3UGfz`sHj~MsCCEkQ84k!LX3{H=yv&?W<=k1!WfZE*VLrJF
zy<BEU7|iD}r|m)C73PT&{F3?1Ps$;3m6;QZi7jLrsJOd`dB`0i_G0GdMNlkZ{`v@_
zrOYNul$9~Rc7~;LW(*Z3S1`LMcX*B2JRKsH%(7iDaUK3*FjdSC&Z4oJ`O^wu*DxLF
zeOJq@eu~CA=Fb@zSv|AyO(@)8?xr|e19LIObsL$ZwAW~|Gt(cV^Coj=B+#0f|9b`+
zx0p5K@S=sOpewMIxr6c(x0&D4j`$Aqz&W^ompMfB&27w^t#I@nlS4IF_n9XWVfO*^
zR|7=and5Sh4(4?^8oQYe_h9HDGb$I*J<KO`T%(t1KR_|bKIX~wkm+YWrX9><<~OUL
zIKaHfK;skUhPS{CGTlFh`$NpHFT>IZb0g)uo-#Y>obf1g{T!f-F=dqy8E2N$-89K;
zr=6MuYso>_J-~X*1Lw$^n*sHMtY?3R7fvj>omL`;SXxRnIJ3sz1ey!$#7YoX)}?L?
z`!MU>X;5@yc@2O&!b&=h2|CJp6bna>vHU2;?aum<5(OTtYs=AioVAwL4kuU}*TIA*
z>t{+!o@9-mMV}X|gfau(EDqIWo?`u*NQX9kSQ}mk_Gwn}x6trqJr=`ZKUUgw^!c;&
z|5e|!w*MdW16e%U{spnteFT_bR`aj08^YSQ8j_)`q7hgMV+kn?7{U5z3KSw)i}OLE
zSfLcTj%IZ$pdQ2OrsFtgS@UhQLp;a2v=uOMEEXLnif2t^Ks146xB@Q{SqJImmW08e
zF`4B;0n!xKD8+6sus)SRA(iz7Z7I`O3#tAtoz*-9lEGr;z)~h_zZK*ni%IwNC030q
zCiXJxhiGtFteKtk{>x@1w?ZSA<!~Q<=dq&BfV;v<rtDch>sAr$7O>_~F!3rYi!P5s
zR`HAQqL?*Z3+xiszmX6rWsQiTUdCd+1rz10?2j;{3f2s&O1Q?FMIK&fZKPkTilvYM
zrJD8EZ7A4lSicRRvz9gO2|DXoVOQZ>J!`r%NCPV^7^IQaN;~Q%)>e9i-((%U3%kuM
zVFemnS-w&jyv^Dh4zxQg-?^BXyR83nhh!UT@o5a=9&05XS-sDiN-Lpu)+EL8I#`jk
z&+N3bPSRedi}lmDK<j2jbitX2EH^5J>0!0gTA+`WL>~d@XL0-C_ajUK6dtqUsZeWx
z^{pegC#*Fdz#e3Ayn!;r@}@N5Fze-=;6_-UUhwHD>s>nOF~&N-9w_6idisd=1j{}=
zfDulzX3z&K9N4QDqxAs$A6ol3vS+Fx>cn>Y0ceNVfxkoFnSJ{(6kOPA+d*8}afcyt
zn0@6c^xW8vJurBb{XU(<JjNcTI(>I`<^;ez*mttQ9cM4l!QT_?>HoqfPj<q|-o_dB
z-TTnx%?|Z|fm7@@+8X(=jVnP;vwK*8^k*-n=vDxGela8i+2$f}LG0bn!m(iXtXlXU
z!uEdylNHJ?roD1F`vX^qoMEr|8tM`3PtKz;lD+mlG)A$f(b%Kef6zKLhCSa-8-R1{
z#M6+8Wp~!2HIBWZ0FCkN-SmP@V1Ic7mJ-=B($Sa1E~3p}GJDfrkQ8>@YY;il_WcwC
zyTBfi0ws<8+f;a;&KA=nD1&|eMR<|P{+;#~7uh?t_^mFnrvyUpGW(A)dIn^(f23_!
z4m({3lFQDdU{fC34X>!_SJ+3_fy-x~qf@&D?3zlDLiQp`!xph?C`we!R+fX5u-OOD
zSIS=UC;TmAk0~Hh&VJbw<QjWDt<);np0ozO&W@`BsbcRbrL#%Z?6m!unmYE-Cm3Np
zTT7=YZm{d7La~8e)Ctna-Wr0&CieWr5V^_j4*<Ev7FU3@unn~4Xl1XXQ@6L-s-I#0
z4m<Tv7`)3)qRXg_{pKM0?z8jg=6}HckQUVK?7k`VFRVJ)JKumtCwomhoa$odQ&P5@
zZJ31OLw3fSn6Dmo3)0-vd)clOY3O5@Q2yo-yN7D}9<$B)5E)>1oQ4-q*xfc@53+xv
zB-Rl7PZs)y+0JX={ZqEz+Zg94`?-aX9AoQ#grt3(?fo@GC)i8-&^gI=6XF+f;6%{U
z(vf2vgu@3p?n3B0aekwv)*;S5`eB_p$@Cm{;Uql^5m(Mr4Tu|u_YwMzaON>!;wa~D
zM~EEbJWT?$JI9?i5GOd#Z^a-yIWI1O$VodVdp|V1I9ukT)0=a9792js`GroY`EZ`C
zgNweLPp*LT<1C^_wLhoe28JELdFfR&26B`V=ml{$4S);gT&2`fD5v}#G=_0Lp!Y^N
zr<7u@XE@s&;6(&y8&z>fas<g3OBBcc;}7VJ<|y+(VmSAy*z7Fl{`b&7$NA+$$i#7s
z48X*5F40#F5;*S`!{0>Cw?Bd;afW_HUoz(r?f6qTpVz>|1x{NFNGivv8vdqn^bG(@
z=iJ^2w=*~<I*NOV<F^!gmpSov2N=xa{1y+5Y)%J}9L^fr5a)6{$;CWQ?P)aTb9%d=
zU%(kX3GOPVFCXR$IsZ~UXAx&~E9R+~vyc`!C7j(hkTT8;dZm?fBG&_@g7f_$aMw5+
z<$$i_Fer$BowH+~9j#TI`xban&G|3{q=vJH!r8T)Ali}EaVDOD$PLaadZ0CMwh3Xr
zkrVqV#?-{I`~kF^oa0np(##nSfit%_p}(T9m6MPH$=jT-W}xv7CxDi3cR6n@0dyND
zlS;}TaNKv$8n~UaIS8#C98EJsJ2`*TI=72+d?C1QPU)vme8};kFnBNL)kbiAoJclE
zKgZ=UOg!Q+{sP)#&hvf{8Q^?Q8KWnhKPgK%#3`j0&M?RS4!}k@eQDsHav0|^d7~UZ
z#H#Gm$2jX~8#K=OA4NDOIKh;yo8<gL)9t`LPM75Y?vL~j^bT_UpMZ1XHp~Dy#O<Y|
zoileUy)Iq2&(QA8l{+;ZeTTX36vsNk{nQ4LqujX{0CtS~2_GWv+?!1x9^9D25V3o5
z12Vv#<UVHs>&5MU3B;SLroF}~?$IwX7$5G9moS*q-0EjBLO-r~6^8B4{dEL-0o-p^
zqA`%$NtyT{Zf*m9kznrFYp@%_eM0fVFz(CrJ_zS7e+lFamr1es2<{&g!iltV!#U88
z;#!NLAI-JUN<4;}-T~3GTxBdo&vDN$LSHQR7m5kSb3eHTg#@mG4$>rYw|oi7B<>Vi
zog{N7&%%5P*MsWa&vSor2Usfi@=utOH170nkaX^)U!jn}ec%PjOs-w0gyLl`mtrGX
z-0c(;&*s`_ACto!c?|truD%&0kDKcZ&?{Vt7-P!k&ZkXp0ryl98Vk8QUx!E$_s?(O
zQ!%&s4BRf^PEkOllxxxfx}1B60(KSL@h{MKjhjHVE7!UB=iZ=I++8M2Mm0BvHgh#x
z7kZ-Bay{3B)N#Kb19m+(oi@}BT)P)YBiH*Ou$#Dom!NQy>rY4hnz<`!=WvTF{~UcS
z+!)%E-R7>H1?W3mdl*FSa*OroYvaEDD)jDg-+V-S(ED7i2rhPTe;$JSo!no(0_oxo
zQgp1F`-ltChulx-&gtQHeGAE6ZY7nm_Hn<Xg<?N<ke;ZIxkZS2P9NajqP5u*ZVUyo
z2Du)TiyPujR03s$>rQ3SPr3bHqj8kGc#=NcJkEWNa`qG4<#ZuVa$WYI(}7n=<r4>Z
zFP8wuk=H*4?jY|h<tGmDF4jZRnHNR@RTtj$H=*Fl+gkyj4)gl10nCkOjD)2lydUTZ
zevB7wf}}goDFJ;RyvzV#9_PJ-XSRL%37%;VIz4&Ks{!N9+vNuC6i>bf1NGr$`~&VZ
zZ!WD6eR=5=;rHXcdJ&vIZv}-Y0(e=aa3+wqk}`t9Jo#C85yJawJ-ATbK3bTB@jj&I
zayXCi-#;(sc~Ou!k~f=<me`|s#Z(U(!y9=MBRtDvQ7!&CUL}1OE|w>gg2eH<RS=Em
z-BsaANZ_R^0Gh=6;RIlkc`bDRr0`y+`o{A-Bi*SNcx&l|a4Ijw5shiQP3gEUGI*H_
zp`OY6?K0Fa@^a}g?<G6WiC+7cc_J}dvv>swK+EOvC<>p)8}5bv6`m^-Tt06l-A)C(
z>I#snyrr|@Zy|3kt>lY%{m~F9=6TR1U&4FO5u}v&a3;o5##_(=QqEgQ<r5XW&*=2Y
zHC{R;1S@%VK4lNC^R~6Yiz?pp8$qghsy)!C;r&qnQp;<<1H~J>xIGv}1J7Ct^Nl?B
zeUNP8_0fl{Zt@mJz<e{$i?%Aacw44`YvEPUtE!c^o<e4~d9@Vly2JZvG1Tw!PSXj5
zHr@eyBCzlAey33GectLajOhXIV>-gq&a?c1De2&a<Up~L7o84gx_FV>px@1lq1&OC
zx0UK<`*?4Mg6ro==!+JQcrW$9?qi;w0{jEKNhK^i;obWPn1j54e}Or~bEO66FfZ${
z9dv{@#|Kx-Q=Xo_s5r_SqVF1y@!p|j=s54CjnJ6jF`d9o@@`^rJKcfrDhKER{?1A0
zIr6`F1+E?B|Fr{s&ioJQK!FRtRf0xW{!OYIJj^!-0oslKy%ppLzk-(QNBQ@z)BSgh
zA9Ne7?))Ftz=Q`sjxNvR{Oz*=<H_Gc&Ya|jQb5^@pZg4mH~;e2uyl%lzY|{g@Ev18
zPV=jF!ICfkF|Bs|_=|j??$3Xaj=lhX9EEFw`0x2)o`U(6Gr)!L?_mLFpB~E3pj}uP
ze=`-fg!7N}!S6Ht<7Y855&X10a3+#pL8+!F{)ut)Me`>qw{(`z_!3^6<B!tE#A5lj
z+Za<Eziv0M<N0-Of+X-mi{V8ge<rQ^llUJ|W-Xcj_Ba|-_+KwWqy0QTkuI+^KARSo
z>HPgGA(O#ZehX(Z`R`Jo<|4nG>P0T`v3$j?!r$%yXR`QbSs>Z``SeM&9DX#tM{@a{
z&tfcB_^0SlU_QT}J|0uRe>?)ctNd(l^cC{=)4$X!;$PuGuh`CS*^hyi@SA1ODCIAv
zlASVs)irdM^Y8w*dEl>p9<yG_=Nv`jb^cw7I8^a(*FmqEUm${OHT?SDVWO7*QZ5YE
z@kf0zmU?~zrT1^}72iOlf&UuqXPWp6sz7e?Q)xrn%(r_{<-;xhEh^k=;frZY*~-5}
z2f=UiO?rsl;Y(>leU~qo1JE|UAH5>)@n=zBww-^Ej(BwNf21XSCx13=$GZ5h(T4)N
z`S}!_d&r+Y6?53bUrPVVrI+78Iify3Q-MMB^9NK?U_au2L+jT8zUpnrJmJ^W!r?)F
zq6sF3_>0PbJ<Q)s`R);Zwi4ti{~?`49_1&$0kkpxo#K<h9gFPszoF4lpk4v>gMwzN
ziE<KLq}bpgL2d|$vtT}zqPPfFQ6Y}2z)VweSWv+Nikl!f10qKSo)R=36YOq<S$9EY
z78*SSgQZY7E;vM2-U)$(p2wa73q5>J3SRve#7huj-vSM9L8?2@P6-x#2pC^Mq(3-6
zfy=8HnZF={^1cCr21*nJ3Vx!DQ;;BTG29Lou#P|>MDS-hOoR&Fp(jh2;0sDTg$q7=
z0VW~@b7(shDOk4=l2L+uN{&VgGAT44BT&@*cUK6?DM)rsV3-9LV+C&W;ZvL-^$#e<
z3#wj&VuIi%y`z!@TWi533!>@Eb14E(dX1eIjD&-`Ah<*YBB=rm9au~gT$&F@(*+}+
z12aRgC?A-af<LxE<f6cXww;#+nl1D!$r5B2z*4rri*oNdf|++gas_?fAbA4$PxwWy
z2vm1qB41$h11S&)9ANjVV0J%zDikD{fn6dPYJkB~!L$)5lnE@fg)bMJqMcKP;3>V0
zt_jMH!kJ1zI;}0Q3ua!Vy=;}>!71oh3l`J+zDDq7KSb*U9!D`l^@0x#=({1fp9Aa$
zK^?t78U=M;u-hb99|*~tf}g0UyjgIEHeR;`MgnUQsMcbjtpev%h};oeZvnY0IQtZO
zZG!4b^xYG9(4koSeL)v35FQA&K0#}{AeF+y9Rluth;|AhQIs*gOCWg;BHe<i2O!cT
z_@0iL_6pAHV5v{=G#Yc!FW7$ru00YkkAXZEbkhOA0YMfW5Pl-COhR%{P`(Z7Ljt=G
z6ov&C=xZ#acELBaOBoZ)q-gKB;LZn-nGi%!jBQfzGkqh%L3s8z7(5{KArBpe$@I~j
zgTfp)=sO8}=>**&p>-Fg)J5n_i2_&QpGD9+EL=!iS~sD$J0y<?U1V_PsIZW-xW|OE
z{syMI(4M>z1N9I-pNG!l!q#eFpAZJnv-hO%wOYt{3B}(-!&`W(6xgSP&P{0a5nkU3
ze@_elng`BTC?tb^LVXhS{Dm((haWvaII<s@fx@In%tf%!lgb!Egd3<{BUHFV2QEyQ
zYo}#oxbTmDm^dT+BnKuUgt3%PiWK(I<1R}0Z8e4#EqrSL24jSO(#t7U*hca1IH8m_
z^zp*|6#Y*SE`16w5`{Iis7w;RLfi9X;U7)VOA-D^!Lswh{pY}45N_xJmns}-rC3tB
zaEQ_s8A3;@X3rEZrnUG*VcSONUlO{|d-JkzR|o8735z$QFIzYx0whN`e=S_g6&_Q;
z(LCV<KB_l8Uzkamfdb)|RAGNr$Ug*9C`_dsVv&$RkIrJ@tp=!<2n*xr9AK&N#6G~3
z34hoJ(Q@IXr5IC%FyI!<R|@$rz~Sq{?RxZ82~)?>SS_?qz^5AF`?R626;9m%QYVyt
z0hD^-KoGER2xn0Iq(L~R8_qNe7t{B7n}v&Li+4+CrgdkF@aG?<;QqTKRP06PU7^Ps
zjJ{2{jOMai_){1RJ`~QUeN>O|mrB^}75+vM^FCqY4v>D~7gWvuNcdI;Ogt7QQ_0<c
zaNSOrcp{uj)jfm4uTFy-68;~Z;U5-mr;&{a@9lu(Q{hz?sM|+{pV2FJOt|R<*c}&2
zC>1#&yiNDtq%e^3zz(8?`=N0_#M}o-N6~N-hIUXSazdk%NVyv0JtQjs4r6i_nIssC
zi>QKP6s{sWRgfMQb<;KOCTdYb?}*6zEzIaq(f$RHJZ2XypyPz@qE0Gj@DQ=+0e4*F
z=Ld}wqDuO7oTtb@b&DrOr@us>mx!|)`re||YteT~w0Z|7-$(T8WuTlE<x^JISL8tN
zVn5M$^fUX5ZqlPLKy<GPD1oAv{{$B#3cHWd2aD_x^b!vdsc8!zDq_)(9wvIT1EAre
z|6>C5jL208jR?`FS<sIZ#qS4bl&Jf83?^E%VL7HGMl|`~=`Yb|6gWR8QczegR^$@}
zkvP#?PXQe-diMa_P7ra~P)HQH(It>1lGsHsm@JxSfM|*+`yZG%FIpA@pDu{1??Wb4
zWT41Yny8VMDe0nLsmdTj<VP#|Owl|SC|ndZyPz>k6efkE*`lma=;eqG(6TC56p{t?
zJkj%|5V<0HM5Rsnq9UrHED-IlwWIT@$VgT6g`(&&a7Ch)NmwctZJ=jwiD)g=9+Zl5
z=wd4q{mO!VxhQuMb}K~r^l^u4q7AfetrX?ap76S8VHDJ>M3ZJTR*UlD09_;ch7vKg
zBJX|hqE6(z6zcV&4}0kx{0-4DD(q|!E!+%^Mp0A;V46h!lvKVc`f@h<nnnDt0D4RG
z%w@o|h%Rq{7p)@e7+`LTY@IN1M>OsU?yhL2FHqV<k$F(KC)z-l$9>ViU!(7V=m?cp
zw~M^K2TF%17KbG4(>q0uMHpz8C}0Q%yG8413;$3w?Nh+?h?)<<nO;#W<)QjSl5&Xj
zi%Mxp{YWHx4rq@>OTUD|fT*PrB2Pqa4`6ptw89G>4vBi`0Q|7XMp20o5uXP5R3xFr
z^Qh>1`m&6DOjMQ!nQ>9|S$HuadR_w1Nm2A-fI5g*r9$I?_-H6Z9L1k3g~&ni0(xOO
ziTA$)&_m)6uS3CE{3?|=xro0Dg=?<j%`3ni7GI!pXE*W6ufQD<`+f#;R6KV+8jpzs
z{NU(uyVyiu>p3BQZwXpG#amJ_-jm|DsiwqB{39hTy~Ul|(RWH55C^|~#Bw&c(_;53
z==+L~jDqtMFKC8>zjz5P@&d%o^pT)I@$yaR3lh8L12b6M9tO8V#P4qcW~kW0#OTAs
z_NIsE3>QaH1pbUzoer4@v7Q5&NO9B8AW>r5Qe1k`;@_6S(HQZ2haq`Z{Qes-e@?vd
zEA+*RbExbjPV659k$CZ^72p!Y!!+zf@xRZ3B#Bqe1$46b3hfJ0#14OfJ1_pk&V?Hn
z#16E}Nfp0P3+y!U0Qr<IUQhth4DsXzh-8XCdk=jV#aybKxFr6a!t$5JuYV4aEU|bx
zyvP<0(o-)_?0X3cSHuhGj7GkArv@`qAl^eyh^ykS_5iw2?2``3B5|<?z5j~E^;JMC
z5i=-7Rw_O>h)FCHGbrCuE@n|8wnEHq!IWMTr~Qb=O7V)9fp%T&{w~yO#7Xo5sudr6
z4=8owl22f_Ui=Id0^Ja|P#nHN{IL?yjbaztoivH_9suR0*!jPYz&DG7sMzS1xQG^s
zE#fKoo8BtE^ao^ai{A?XcSoG?Jjh+Ky8xhV;`b@sbWc2R5+e7-(`hUHK)mrUaP8tp
zR8`v{ezgy7cZx@s!)}-O2qi1K#krqA{h@f@d^p-8Zu^wZ!S{++)PwC4$J?OTFWx{$
z4Ihd5^cy@DZ>O-)fOu;j^q+_;N-)qt@vl_2G9-SJ{2dl+jNnGZJ2pb(skm?izxJru
zPQk@7@u@Sw92dV=j7gXfKl%wGlj17@aLqx|;|OT`0m=Dch&oD2xfsPk$x>RLIZ2Mu
z+whR&eY#AXC0$fE;v$)t4n<c<%I`3ESaO9DEN+qof5M9+k`)Kx_EE{VEiiaY@`n#*
z)Ll|b%Oej-4i!Efm)zY9aze7~3i>=H!D)~@X_u%z0h*Vj`3>0hmfT;1&QlVvKs5SD
z%=E@PE%}pRd?mFFu;eFU9fqX8#QZ0G3Xt%e;6<Qh?l44xB%2-sG*}{B1xq24>Uxk+
z$zfVbgh^IYL0!1y{lB3eDaoRTL6pRvK&g>v$pyLrVkF&H0D4yPrW%dsB<rUEG*+^=
z3MS$t-BiXKFPVN9A_)>@Ga3^m(Z7L9lC0(cG+A=&GoYkM4$y|=yyT-0pj?pH+rgzu
zmeaF0O|s?`?50Z|Q~W<eGXK8{u}n$)Ux2wNnes1Oyd+sa1$Hk>exdzimSo#Ph-ORT
zJ_na0`HkY2xsth*&C8QqjRUzNiFE;XzGR%<JOvV03RPZ}Y(5B-Ldp8?(N`qlQS_)-
zvhWvJD3PpY0<2V`?WXr%ndILlu;r4eqmZePywZqyz9u<Q1hh&?F0F~LOS*g^QYC3g
z#bBx>-@9WjY9vMhEY(U>w3xmjd3qh{4H8ufNTXyy2=tmH5qr>gQ{qoWZ_ScKdZgTv
z%%{4}7Rj|ST7R}mUZ7j%w&Z9FOx%(DmH`uYB_TVZ*d__0SL{8>>rwFOzT_7U8Xri~
zG$8GgUW%P{NFII-&`ybQHn=WHWi`OMC7UVq{ZMi=0gXKp1HD{&C2!Hmk3PvpT0!+o
zx|#G(_#R2tltJdPWE!n31|*&o9C;#nPy-W#lG#gOen>KlPVx;)UTnjZj!0gLfx=VC
zRu=k3B@L7+7?ZeDLTFr4(FnZ>NrnT!CM9{(0p=jxN|o{lq+h2%!BOf?Tabg&)DHC7
zousY1fObe4z6=`9(gMm!x=42|hlZ<kNC~@#rNKub;wD|S0uyvZT13&oqtcB$pdFL`
zMO6y!Qq?x-c}Pbdqw%<OCsk>mkmhcJq^I=D29T4|!*oG-Nf*=pz+3w729Q&B=|?}q
zl8;nL8LZRNcMkx@S32WmjLA<LOOHE$>Ci&B79bt$2TY(emul{Uq&unJD_F{14!sbm
zfEHAt(lx{2!lZ8p0wr8p9}4b_^t2rc5mMuKFdr$MG8==4lFmO5a#niswb9x3m?1bF
zCyk;gQ@k|92BQhmcc_dtQL0}Cs3hqXy3LcN;gr)#k$zMN<@3^M9L&xI=}YrLQl%z;
zc$p@hOCg4IsVn7{GNiTt06J4D_XNsC>F(Vim!w0%P`@nIl)yrklxwH3VYalCq9-}h
zO%pJYE8Wowk|*_|CCe45>I0a_mzMtw&;sc;nux1X3st%nN<Hb3RU}Q*LZnz)Sp<a=
z>FYb;OsRB?RxD-Ghf)l^T)L(S7AmB-W<c_q^iCL@sg!P(Qcdl3Y05TqR!Q&C-CiyI
zhzcNTq<wmb)=J$d>|ZDSgI>Y)QaN24H>5iUAlV>&Wf4SfO8-`)u~}+#1L!SjHkGxs
zNL}cgNUc&9Whrh;XUzh+BV9EKXYNX!@5943>4X#26y1})KvCZN(htbt2hxH!px7?u
z1>#rjkfz-R*D1}VT|t-hwLXw;=|w7Cc__W!0kj_J#Ufz$N~ciiSfBK=5&rf|8y12*
zlJ24x@?&Y005dZn{pWXZPozn-@EDZN#`_%KVv-utV0T#hVlrAsq=V-`o=T7HLF1^@
z_eE%oNkdyPCF9Z+bOL8W`jZRnPD%x5V9-IfdmQ9|tc`*Sj<RstLLQX4t%BQ5GCw-N
zb4XS|!E|TY9NJB|$UNxn;VNr<0x<hw*%m74b(3-b0q7CgZ}iK!%dS#B(?j;+UU+d_
zroI6E6S4_fY<tSK&Vw^2W&cY?qnC_3fhqBpF;+tFlq`gD{ywrr{=hyh`-d)4U)lSu
zu;3^Ah{owJ`-k4W0kSV>1086WeN3lpLS$1YL=h_Mqb*XH%*=skxNO@}jOmPQJw+%Y
zWH)mF8Y%NV1NWn3B?%zWvW9q|#mJV?JNv9`MGt&BC%Z+d+F031B5|?|`kZOJY{Mdq
zK0$VzaxICnJOiMUWOm=>a3fi^b}1B7WQB7eb6zH)Ywm(<z!}b@%GxhuXlb(XC1^~S
zNh^VtA)7_@Jejh+?a;d@GcN(!CE5Qd!f{#VV}Xe*S=D1GWXlSvEFeer!@m&8mAyrm
zRi2C$1-&aWd<z3;`LZH<eiz90z5+{EWpau~70TS716L%Ac@3mkHtQrnOJqD16iQ`r
zw2LZ}N$HS5xol%E`YL3bmcZX@vQsZ(NY`b;YcNqIV>|~^E%VW%uSS+f<x91)h{F)6
zlfCf;twHN$Cn)uDL-rjFv_ZzE08OK8D@|~dY`Y^gZpwNo+}SLXQ@P<S*%C^#x5$>w
z$B))3oBbu!@5<f~LcL9PHw%*YWaA&A@xJVz2&g}h%}D`fyDaA>6gp&U=poW6`}rf<
z19r(e0^wV?tZY4o{ZO`b9b|fB+eF}cWs@i1exGc~$3W|s{WT7lN3vs72L4#q_6}eM
zWT8|)@kI9G$Iu&;?Td%PkSvA*9mBHAv*FB$Y$=t5Je9rh9^4+4h3^E|m`oW${|Ibc
z7IO`jCS;yi=T4uLxtsy0gZ#zC82thHF534v%GZ>EJ1BRW4-qH%MOqXcl6$`mP-pp-
zdi1%-KmG{VuJSNC+jLm|Hf2TK<SafUkH|ODIj^JgN0e_qCQrEo5qCL18|ros`TLZN
zJ}#el3mPZn`zWmCDYu@-2v5p|u^?XZPm4gj<qK#Za7w<V9^>_q|6c}1cv{Xr1@pdg
zr#ayK<g4h>;xGS}vLgZVa(Y(;$`^eE^FeYB6&MD~D=D%VA|GVHUZ`C@LD9T0`QR`_
z!{uI-v^XPwo(dx)<oZZxM9M#+TCga2h(BPW<(WS~Ax6%oSLs>#$DcvroIIMg>ap^a
z2!O`P^XO?CFK^EQmmqhD14)!?%OR2^-+l{*lI0E*xk{1SMRYr!myc1l@q)Z{5x7+O
zG%80;lXn(?q{~OU(3c^vqFqI%eDM&lFUswd?6@R<n`)OY%f<9ji7a_z64bNhz8j#B
zBY)}#$y~YK4TH#&Pta4VKrZx$GgswqpQ5o){*Rr)HAV6<BQ%QTO=0LPk-vQpou%@L
zK=hT#AJF!;TrQ45Uxhr9jzwIP?>K><sZyR!o44!ook6fvB|k@XhSl=R#~@iFj~s@2
ztvsv{3U%_|o`t{l^6U9fxFKKkGA5xx?y|*>d2W;^%tU9C{53W7Z^|3!AVag<>nrr#
zlFy|@bBo-W4kWb7M<|_hTmEPsK<~%}^qtJR@=tk?Y?IfF!R|fzP#)Cp%Ok%<-vhb3
z6kfE;GoM3Whx}$RNT>Xh2f*x-Z@NtNJl*oU|J`_U^$EcA$bX=!m0tNg3WxQ{e_R8!
zemSoQ<dOV0ddWPN@1+<0fPB+SKzkzp?oV)o@?BKFG$bFOdg@{MHfQ`WBl4Q5@Zza_
z=}cgb%5PDmd`#{T4Q^b15KjSof<V4y6+kEDznY=wpt$)8Ko2Ok)85ljAsmEH2Nlj)
zXmnD1;0ErHVg+qaofQh&2)ig^_QQm$!bGqA!-`T$|GFtI&^Nk{D1M~%$x(%FG1QMK
zR?`;4U9qqoA|8sDwxiL0Tp{}tc26jd9EAIxiof3jIjOk#Dn{?6II;$PrxdeCFnS-w
zy!YVuX~jjlxqKCD4zT?cujGOFE0&1S7@+V90d}C`2pz)>QY_-3F<5cF3zk9@f-B%c
z6>F(ZD@+kb0mg8<BA=?a&M1~yVIo42M<+HS74IH}-6%yCty-fME?ePDjH2#q4EwC&
z&RX=HQ*5B!NUY+=5{SepOt-<sD@3mXB|*WYPogC%mWRT%B!z&UKFNxpspv~lyr_lU
z^9l!wvR+WwGxvf`RZO8RU7F%MddjCO*pw5?P~2BxE;1Fae*os9qJX|qdP%XFOk7sP
z((WruagPGJ*@`6;Ce2a!(Li$*4pcXlr`X#Caz#=94ixeg%V>>Xpm>|2JXaNg6q7Gh
z2<@w&QKXm}2$>SaRw`dFRotW-s7z5yiRyC2mRr!MPz2CU=bEDKA`Dh4x*x%{>x#i_
za8(NF2jHp|ughVgMlqc>2epc8r5IA3f=icPy~5QBazhdE3i=upW~$F@RK%~Ms7;gN
z#!<B1RBR20rDjFp_fWj0c=l}!yG1dh1g^Cz=Fn5`wxVSbhJ8n|sU3QE74zqUv?&f!
zZug#IH|<pJD+>Fd@IWz>iq6^<@k0RXQ2a*qQk{wzDtPKrw1mK!ZpDsn`s%<##Wjk5
z_b7bmhwW7iXknsHvE?|1)~~4L0Opb63|;Gw6>0QovjN2qze3@Of?ElNK}BjR><%fG
zy$EN973C82jVSitM&nb(PqcU+RcxWf!<fQ%FT5C6<R1X$gyKXs)wEA4hAE`!puEU~
zrw5d)=%|O2lKBG~4=MA5V9;6l*{>ijN-5>0T$K;s2RW=9pg6Rf@?;_WJ)%5Z0&-M&
zl1dhiDer#@&RuDvP??AF=2I9vuKbDi04J0ary=604EaC!Yd@)6lnaAi$~WGGr{2n6
z=yi5Vxz`6WKFUT~@Sau{(1yuZ*>MLVe#-4{!o0uo&Fdfm$_QEo2Pz%*pf5<dj+Q{d
z%9+FH3sJ7G0SQ$aX{8#btn&d_xU!4x)HBLyOF<&+O1~+fk;-42;V{0n`#<PME7wqF
zJVwbkf}B;pM};2el<jm{G+z0s7%&OS(|jl-D&PGWjY-OM0!>yf`wU*BD8neAdS1D6
z7sv(WPAWx7Ri3{LlBPUP7g@T}DH=XyDDBU_5B*Ff=Wk5SMdc0=$R(wnX7;kuooczV
zl-w7fn5{JX0y{^UP6g|^%9(T<<|#E)417f?%z$3LviNgw1xl}M%=%U3Ys+AwP&ukZ
zW05l38C<b)`9DxEQO>yyg;M21`x4A^nR43}$doHzp{u1rxr(;V*OVS~7_(Bj%@KXq
zmAeyRuu3UA2luO$U8!iSQM%DHuvTeX4U{_N;K%5zSH4Rzm>bIF^m1xY7T(3oG%Cv|
zHP)nTp`yZ@%0rV7X;#k4rsDlu%BO)qYf&CK3XN9fVyd~jtxRZy%pK+NO=!HUoJ0G+
zHf1Rl{@qi`C==PPJXZzD4yE^YOjoCJZ5B|vlsp3KRtEhI@=#gpvvcOu751qO(0i<O
zS_|_7%2!L!_e9Bl20!7T(uX3rLrM)5qzx;pyns2PjHMX!Qzd^YphuOrXq`Q#tT_#o
zab?o;=$lY3h(h0_vViIp9aNhhK;(dG`4UW_qiPdP^Fh_7IhYtHmDo<1kVC4}R+x8I
zouUF(7nPt5Fs`axT8kf6c`kvzo658TjYm|QV!<6%JxhVFW2zYs!MUqqX`Sq$`iz!N
zr&S-v!mh9Ce+xkTR1;L};;$;A{bGPB^iQ}Js0yR3OpwZ3VTXRO>M1?gLR8-n7pe-U
zRBf0lI2`7~RdXqKct*9c7a9?&JG6j{RJG8lfhbjG5=IfNTK_EU#;Bg5J<?g#a0{F{
zr~2kFNUTcagvL0PfWorzs^BG%Oi<0(0g|Zt;5Z#FPg0HT1)HquvH&ziC8ov0dDU&&
zfm~3z?}7PL)%aS7q^UkQ0+OzpcL^dHs$ek&lc_os2oo1ot+b81q<Y<q%i^+Xcn8d9
zsT?R6m#rF$!f%(O;?i;OT-6>rSDmk_m(u@xDo}YOq4lb253QaHRT*}G7O9%{Lcdrw
zp9(HYRPj3jQ>wD<L0_5b3tC%NsLF*9xu&{CF`r7+T{;VJU3IV&q)L@ZCnT#?v3}^Q
zQSGDZr&`q)l=`nzl~8D<Ue!(qkL)*87vF|PgGx`U{YKU6NpQbOb)XT$zNvb7ANpEU
zCyt@7Rdr$)$Q{*<a_HYxy+kkQHdVwhMDD3(4S?KNo!kw7AE^3sfYPqIOF`)l)%$+{
ztW&j%ie9=@xp{D=TlE~}Z6DfIg9(u7QRP#8ORwsO9)R|#*3<K%U$x^gWFDzj(iQwz
z#aRJvKvkRzv?nUx2Oxv0%he!5D&J>da9EX3dz}&0#{DqyRJE-K3Zts@dSH&JUKXNp
zT=fPU&=abyn_+KKWzV9Z+yV6v1^6A+xhW7msD57spPbc-B=otc>q;;*S9Mb$yf~~r
z^CF0wy5b91I-<7lK-|^kx1ivmmb{C;<LZC@0@z9QdsHOgrQTHw5pQ*q65J`Zoqj?e
z_5XSxd0M^F&cKxVs+X>W2|x8Fy1e|={BPlRfO;-v4Fc7}^PnH3e!UtZ!RiN_fE}WK
zcoJNwdZq(l!qgwng!ypw946Gys1pZ4BGd()7-6J(2c0I2Qv1^jI$B*~1XzrE@iFwB
zRVQatjN_d8qyKWlYAc;eic|j-2<&*ZLor-SP-naaXA;$~(zTwX{_+PjCacd=Ha11Q
z*9F{pwa2gEE~uqLz)n>k%>ibbI+YH1rK|UhKqNz5vJD<)s=uV@`$hFS3fW##zqN>#
z`PphU1s8MFyJ_K=tA382{CVoNpMqRbCkTL@ufCQHu0U<91n5=u@{4e^P`!h`23Dl5
zsf0+edPNy5m8fHAnNg~4qF7&<`sb%0<?4Mrs8^_qa$)zHT0jBoO7#~gh_+9^uJ+!7
zp;f8J{|0uo`a&&0Yt*cNF<-Unrf?|MsrQ}%*PuQ@m5q(+byUmMq@I-qy_@Rwv~6ux
zPp8M-Ep-f4i?yhy+=Yo&^-el_a9cf#ax`t~*-PQ!J@r;PwtQb*;*UmquiEonVE3u3
zW`Ojo&p!kG0d=?-GEdY-de{%DKc-I}52>5FVQE<1L2tnk^$%}@8&hAP7{|D}?k$iB
zbrlWmfF|D;!*<jZtpdtH&9fAGbJCodioQdd!d(D!*8D*p9=B`Wq;2*IO*UmvJT+6^
zgZY!1+1KE=m*&+LSn}3fp(OSxO>!Je_-M3mL-DkxcLXMUHEUKt(oge{qUin_nLoGy
z4Vxl{ftvO~GzMvQ(^Q6NhN*5MRAax6-ylrmNb!qsjeXNPuxB)@o`Z=9%^G^%L~FL6
zg<_0m@GAPwYF^v|(Q}&ar*Je@vyj3@ahkFBVJTkIQH`M`XnMLJlBhYG1%)Jy+b2*@
z))dp}<rK}ucfp<4^lKq<LE}Qv#8l18N6?q1iLp<>sdUYgk74(sW|(T3vo!bX!DVY!
zd=8SMiG3A~xtaxkfy>i`J%-{HO}+yrAzu^u1tz#a6U+eURn5z@;ZvdJUrNCjX+Av#
zM~gM9@*r8F`HPmer5dIW##yG>|1}iKH92lnfl#4&Wizm^X~w9mu2Pe20e4-K+JwF;
z%@2P<zg82R4AQJAqy_dZjUR<?S~NGQf}mB?83^vSrmPz3cQjWh0NAF<cLKSmSw}|`
z?`!t^+<s;1Jo{W){dQ{Vrh#;6T%#fKQ1c6w$o6RBPQk-oO_>L{J`FPtT)$?1CG0)Y
z%%P0-W6hj8xILix{1|+BqDl7wH>g=c>+2y+gCj;gqM4S5#;2N>>8&uTS$+b2W17eh
z;o!KY%TAx(n$R@30((;P4iN|K1%GrN(5fgL;izri1pR~BOCC^k(%w9X#zR^ssxx-h
z&gcQCi`K&p<8;-!(q(m6TbT?=H|?{_LEN>+<nZFS*5es?ctRVu3Ip`i-adrBlUjkh
z9R|I$5foqc*8W8`3a7OmJrMQP)>9P4Py4G8*#6pCbTTbKd!z=6fm$7%=L^y<r(kBV
zb|&40AzC*DP{On`DdZil-SZs!&S>i?FCL-2^aIo*warwv6s66W0!O2@&;Ct8{TS_Z
zN*kZm?l}yYbK2C^(1_J$ya1Rut@Kln1nqK41}ADcG{H&Q>w5u{tab7OXo_|-?SC$4
zWA9)tQnl|>C^t>JvI1b~+Ii&=$<UrifnKIIdIa1>Etl+F)<z*;WS^d;eW?xJWNQbv
zpfyJ;pmU<RTD26T&(j{IrT7(X(KeVU(r)8pE{e6$F6b-K7SXL;stuzsMwwRhI{GTK
zM{=QXO}ly&eU;krR`gYCpCR=c?O96Q)oNMOLF%*x|81)3wYFv`HfV*Fu-mBJ77xWH
z?O$BL+|q7dkG>YI^EVhwt9E1-CgHX=nWA%dv@`Rea97L!7z%CL!XuEpukAhu$p>2F
zS{Q8Ca(mI&q5YAfD4p8bO_-T3?W$WK-P&u@0QS(X_52-{dbDp*>ZxD5m6EEDw2xZ>
z^H|$YyP^TDZa1)>XxFx*Z&3S?b~VFVGo`aev^#XbeyR;;Lu6F@=_WLeX|sOB1WjsR
zy9Y@JotOu5K-WW&9Y@_~pTYZsy4CcMcGB6u@Pm10UCTPixab6zKwNc=qYyo;E29{N
zn=a)tM33qEA3@SxS3@<F9y;|#cz9fQtOz0}bT_tvc<RQUhrcIvJ(MEz($&&uYkYL4
z%7J-WcaK6NzPbt8<M`=TP{hGs*KePX)<E6tKxhQ%cGEg8Soc{ZNT@D`!aZTSRo$4G
za9zV`%-0#+>7QXfLif!8U?O!TZ1hFzUgV)MMkjj>2G8pL(4+C3&NBfbvAPXd(@u}m
z9i_*4f=;{=_7Zgm2rNlgevFc8$-1~Ej4(x4)dntAXF3AWG+oj6fJxWA@F6BRL+3>z
znYxM(p?^{L8V7xsbXlSB@Um`u8c3FoMMXi`x`bz7H%G^s1)p+t$J60co~|(%+!fv5
z$$-w+y;TE41-b=FT5Vj_MSKnug*qpSo)+s~r5P&GJ<EZ?Qr#dIo|fqhv@tH%v2FmS
zLf4g!zH7P%lpv|p?VvKR>$>lz!+e#_<tkjO*3G7<YmM%~4q(>m0%#3hrz@tcRK2d^
z|G?eQMeKNSiqH28rp~mxYJkwB`{EN=zNvHl8Kha)JOeSM7M+U1lC8R%l*PQQd-Ol_
z-O;^G36s0J74u-EP4{*SEZ@^Tvj=_mb=?#tc%a*}2}5nyxhw$b(4}n$>C}BssfI4y
z(Q{Df);;$WgL<e_+39NU(d~K*q*tf^7^F{^`3uJJNT;GB4UctGgW%zSuK7#!4e5-u
zuNu~MHexnLbW^ET{;95vUU{QB1wEO^beu0S#&O+oidatQhAH?wsS|$%FC6sEU!(7U
zK4BZoJL*lBX~}s|A5LC4=`Z;}^pO6Ix6tUUPo$Cu7yXBHUffl`Aq;(o_2xBj%}w7v
zhDkW0_j~~+j_UVq26s#!+yFgy{na60d+0rAmvmhJvJwg>^yesa?y0Y!DC|l7$*-X2
zrH@OZliJ>T{V3Q|`Y$@+g^xawe)iM)({w<=SKmr$UO#;jEx7&lU($Dm0`$C1n8ZN6
zZUL}^^v+ag9ju=*69z-{7hVPl*Keb@@frPH3Nl9Momav8Nd0yS|3v9`tN}{2{s10I
z_USQt9$f-w^-YUl{+zyG3KZk?l2~x@`YV?}67&q(M5O5d3W448`e(j}GZ*ygR&c5M
zx|iT+ntqNNdg=Pi3iM^@f2R$8roJ&4&=>WR92mT$|A#J*%lefjfMw~o)7J;=+4@8K
z(V3%vkb=SF>R&AeXr6wV3KMljU+n_XeEk9$NP(W+2@_ZK%SoY7U%vqQMf#`~cv!4|
z5(HABH`BT8QvC+H0?YKL%D|QDgX*DBq3=(GYuEI<=tWqm7jMO^UAOB$nhTjK{ZHS4
zt=2D?3x{j;3kN`I^=Y&$t<&H40IAo{qh0?EecXLmYS4en0$QWqJsw<>ew{0vxvAHF
zgJC!8&(P(3OOLZ9xQ+Bz5@DfLuh5|Hw!VQ6lskI<PKeyq+XJ3~Z*BV76fC)?|7{^;
z?(6r@gyIAJ_OBt@uJ_CY*P-7Mg-Pht>()b|OV4LOvRhxj4KNS&(=sro9{pkt-0sy&
z>6l=je%c%~_UnJU2kw!6lM`n2v3}1LfDPztr$X|H{*L_v_&um!O1rcneI#ulpXz;T
zz>Vs=X;CnyAEQ0nxc+P=&?fZHQF-g6{-d=3buhG?L*oHMF`d?MG+bW|4-Xpjlq_~K
ztj+*;$gu2LaL$IPAK|u(;f^CDT@5-)I370qoI{x%H-lgf*dqq_E@&JzjC=;{V}`|a
zwYVETqi^GQ7^-%|i{pm1H{sz4!#@-W_cZLLr}jxh#1Tk(8Men@gx&@drSVT0t_48S
z$MAk3ESxsv&B2g-4d!AP@-sv(fk>cX*)|Hfgc!tBLlJ85eiL@X3|A|G9d7Wahshbk
zt)JmjgyF>?kVwOG^ze%^?5Egyw4w3|OvD)edKv0x4UrBY=M2l_@Hf_wMz?RA;Y>E%
zjyJ4-3t$O`^(Ua7XgJsd3rU98C#K;3OE!4Zhrv<|i>|}P^9BdX=w2|ar1yWSf&V%h
z(+uu(b*CGKsZJup@Z5da%{09B7yP|w$l*fal3}zDK3z79MZrXtA?$tVWg7}_qcO+e
zL1#8{4Rv%FG|%8j#o|{CTW+Dxo^OcMqP4*Aq!FN34c~kWzY7f+QaD^>_*(>-V#5{s
zf>McL_XNBsHLR0hpk)TZw-6~eTup&Og+Wfcooj~wQ-M?(ymrC0>xRdF!?h~IG-oJO
z8^&qlSYzm+SZ=MMn{JLeyJ4me?A9CB((%(9hLm~eY%t8e0R2Y8&r}xQWZ1h4eXWLb
zi(&AN;ctp2-8F2FLSLJ~neL-|hMhG)xo=2*7A77TzM}<UyJ5nDk#!iVXMl7XR#+j~
zXW$pZ-$#aMy6_(x?D0d;7%)7O4gDbl`z%Zh8$N#%zKt06(c0pvVLq83HC#IikugKc
z5V&zeXf*mJ3`=NnJ!x>JXSRd!I8Dg`W4aBTBUQNIb})L=D#FP)ZyZB9WGpR2qq8x&
z4aCK`#7^s3SL0sVuOBx4L>mn^<2?h0cEori0@z25iBz|9%y^D64(`VBNuYTcpQAkO
zapSs;Xgpy&H4frw%>EPVCyhHO_v>Xe^rF$*_%3aQP8q*nhVl9sl^Up@Hu7z-;A_l%
zj{eJ(pD}`l=5MT`>`j0%FCGR1jkSxQA7q?zAC`iR_eP)?V(j<@jiJVAr$EAtD}F;`
zxUu5D{f2SE3@*aBE&($dX`J%_2BVBkGtn4rJZA=UjPZS{5<hEf`yJ$*vG)VI|6+}!
zE^s)`cvb?Z;*I@uZzmWt#qcT7cs>C7Nk$QU^gr3y{}`Yt#!FOsb>3Kd0eu&YT{`ro
z8kyDTOEU(JK`-5SXal^+Fv<$SWg5@?hDo?+bfuVXmhq>}Alb$s?7-~PbBvE9fXOxf
zLQ|7xtaQQXuNd!#Lnhz2oi@w`#-X3lch&g57e-NNbd7~bk#UH!D8<Hg&!e%#`1^i%
zQEF6ujiHqpgU7&?8=s-V?h4}r3ani-+CGG2rEwV(+;!uhFTq25mC<q#zEvCd27|3J
z{@=UMs5Ks^(ycn<iB`bW8$YMAgB!-X8(^@(xXlZFjYd``V495k=y=9W<MXs+Yc?ME
z4SlzauYHfXXfdYWhDfWiZzDu*8#mrV-yP#x%2(bs&btJAZFXZ$I<OxY`;_pl-T2u`
z$aEOreifaa#)WTS61t2pu7gOoaTjGH9~y(H{H@3M%|?jy8t>3nsL%Kn9n0!B&iw=2
zBjdmhNIo`ZtOVwOaep|}pBP&yW-(|yKaL3+G7eq^%COPyxB#Lf#yax!sWFej&ZEYe
zYalviEKLFExKZ&GUQ8HYpbgHX@#aCe?_i2}1&s$x`;*b=Xj-ri+(FZu3BYzT&3+$X
zhfIfif#PgR_J9{ICSE8ST}{I4Acsv~{sTj9reE!p9ynqOqfqTpQ_g9?95Y>^>IHX`
zA64pjm~3M(c-*9-Lvbfen<zlwX>y{<m6N75RH)}=Iy{OW#@lp70=-kFk{5t^+EjNI
z>b|DGcrfp03Zw;%zsZ%hngOQYGe81O-m~qPnjq7nZRiX(J;{bfh)F;R+E9~M6&k}#
z`)OAiZt^Zf;~CTIZBU3XO`-f!q-hEjKSY^+q0dD`n|i6LEXMSZo}IC#BsuKHnU+%;
zG2Zlf6#PvvIld2(MAM%yp)bia?HZk~Og5SRzz9=JdqW{}-n5zY(@e`ep_p#^DiMRp
zFzs)}KrfkorTye(Q$H1GXPJVQpfB6>8ePaaCI*Epb4_2;9OjvRrZDUk)4SQ|%QtmV
zu(7}tVt~k1)096!3QfXzI$cs^YN6+Pv1#5r5G^r<P)S3nsSNLj>1C$ocGxX9b<qO9
z!jyXz+%?lL>mXTa+PoZk*G;d|yS2(Bp+Hr&>2C_r)|kp3fvYvW_AjQZ&a{s*VD+YN
zH$(D<Y4Ps>YcPF&2%Npq^ld(5noQ?3AU92`9N}BD$wn0@w@en=rnHziRP51eIzo^1
z+olCyfZQ?N4MyW#Q=$m7)@E|t19H#w?>|tuZyKi*@&l76<s{opZyGV(9j41P&Q8<8
z4<XrQdZ!Oux83CRGuVeF-&~0Hm{b&J=rz4e``A9y?oA;5rZ4FU^T-s-z_1^i?z|26
z2TU(`VJ@DSHqi@Y&~%KFNJFMq_Q3A2DexQUjhHS`K=7&QvwtwMQPZw((Klw=ECtHA
zsW1!NgvmZZTdqly4^>S#n2$XK+Cj7XO(;5<|40KlWZwTh^qtKEpF`5c97u09SMyDJ
zogFqmNd%gk`37x+kC+AYWIJlMm11U&nb)s}PwwWN*=Y1ISJEQuxH(}8$O&^Q)sK0a
zi|lm7=cIWCrBS@hn_dTuxA`W;EKiwN{Rm4w=AY?VblUs_WgLCYB_81X%pX$Z$KTBJ
zL1TdV>a)-bG>_9xJIJi0do$R)Uk#BEvzmUUQ1dj}_=TCL%>-t+xyu#i&zP?l(*7^P
zy!jzOBh9-geG_F~K}(rvvvdp^G3E~)&=+f7mjsPCbIU#qJKh{malQmIHxQGUX#Um<
zB1z`7cVIr*{C5;gq?m_m!JRjMzX+3%YF=~{jcMl39pGBJ`3(*9GR*8x=)b&Wnpd?#
z|B|_AE?O^}H_#UvvdpOkFrRHc_6hoO%;l82&NY8e@uz$<>syEvm_3RBdeyvwQj~?}
z1p(lS%%4(`SFxG(Hb{xNg$uV!%}O);Ei<qE4kIf!zaI|u3UkalN;zCJw{f9ZX?CXj
z;JSJ0>(Hn&f7l8AYV!pOveuYiYleQU*^!Q&*O~vO582e4|D_b=4fC!&;2O*}T4gnw
z(*yu(GLMSD-89Rt!{27}hymW;GPkTlV~e?W3b<Bt-a#0$-!`waLgub{*;K%^nZ^4-
z9^kqHcDq?g1xg)eZ5cE=&7rh!?J|E(0m*K2Iwc+-nhW0n*JBR71-)ML2b6m2Grvf?
z*M9SpXt@2z9NPo1C+6aGhzy$7(`V9#%x{Q6hVACGmCzqCKTnV8r{=&z_zgzQ*M7lV
zjG4<R(?4#OuZ7}-`AauAI%)Q&d(*+Pei+2jQa1+%4_a*PP;jz*_$qulWRd>_1!qg?
zL6~r{Z1sbM<CZN3kQ0`IVW4<g9`A<8NsC>Q3xi&kMddK>ZOK{*(9@PL3ef0lsqTZm
zpXGm)@$k3&Gz*FWmW5wHGSKqzYv6(`8!4L~Y}xiT8bd70D90FT*+6T7FiU4QxNyr1
zD#blxd5MxD5tgVvG)7t`Dd?AIS!kaI#UxA5BA7_Ae0L9nId8c^Co(QrGAZ$&YH6mB
zN18>w7$n{DmI9I)mRA=5G}H2ZCq{A6BA^J_B}?Klh+MYJtN~`0MJR(vw&l&&fSF_Y
zoeIx#EemhMe4eH6zr=;5tPxAF>G_uSMhvFFa)6d1S1rqEIap|!HwYJtEG@JKDYpDb
zwWTGN)??5wwT$GUugucn3A^Q%tFHjN!tyC)cCT67UWP)YWg{h1u3OmTXq9F96nIf>
z`IH{IHI{c;(N}A+ze|<1b(X)$n|e#eYINSP1kq-v!Lo&_QyMLiv(VUNxkuaPTb4_-
zx@)oAdI<ei%RUMr-nRHgV7l&D_Me1ncP%f^2Whhyi_mz_lHdhr?pxL#MB@X?O;5~B
zyX7<5Uw2pz;W>lTm6qdTbaq*!18D8GbWlCzLyMY97<(*NFTr51We*iQ_E{z=joEM6
zw;tRhOU8S+Iv-nNywNydIoSdACzdVI&>OT|pj^d}C5b-bI&2AGz>5*f^rcXEYWckZ
z!yUC`$slPTvlu;Ke%zv_k2g(NZqgoN(vn0aCl1zOCLBIsEer<dXbpFT$U*C82Vlv`
zI)%dChpd@YR^n`Z{!7e-i}j;(Xmqni(08nkSiK&=i=)<8=&N$ataB5f=WbmW0Z9+*
zilY!YZny4DgTWJ4Glf+>tutr?chcJS6EwW6`($YJwz3{W@su@@%ItltpS}bWr>!e@
z!fjt`@m37R&pJ{F1%GSrM<4;#f9SUlw0cpkN|5#6)sPIf&dNb!h}Gx6WVQ8&)9@n9
zYG1?xTDbMgY$%?wZl4O72&=LKV~Vs&b6_{hYNnJ&w6*R6L}IK;iV&T(zVkao&RIhQ
zXpFU*euNisRtbGtDBikjAskJx)}{hF(Ym!1=98>#bo?gSy5|%cQ><U@137Pf!(Iw{
z!TJJ)#8Ry<tpRA7^-ubz1?kpx!)VN~?x$TtruDNKaP6X1LG=Tdto6UcwaeDUUa*v9
zJ!8YHWm`ii)R|-L{~XTbS~Dn3mS<h~2Fzcv{!Gi?eCsrNHx^iZW&!1@b@*$l>?^ds
zz6#hy*2SNLE4C`>1VM@Q=tZEFTFn|@ms#0#^s3zY2`#28t^FO~s;zU6!$ghsEvnzC
zwZ1~hpgL;_9|r5KYC7Y2!|F(R-UjRBPM|beS&v}8$=Y)S7H(Q^ai7Kg*K9pHfl0h&
zJw5=L7VAoSn6z30sNmqX^($|{+_9#51Lm%EF$GTBtXn8baL?Mb6KMCXK{T@utXmhs
zi*{=_t(QBj9=o8>X<dB*q{}Lt3DRwSdI26jv@T5tN{_Xrj^dxa)~jAH*k?Uzf~9_|
z$A^%4WR0hjDUYqE=&>_kb!&#DC)U09zztekD26>`UGxy3!`9_<pgv;#jfuXe)@}1(
ze$={`!kA;$&i8;aZVjQ3(uDQX2T+)_{!Ken2iu|<khCALl~CcfqwPJ4Zy&N{E{1Q;
zHm46kTx@^tgodl_+#U2CwhdCO(aq+dMB_1A_Egw)xA{@z(ZlxpB>FsUKhPzA(pIz#
zoR_WY3(Tmu?P4atPT3M)g`|(IKM#F=woWIw=5Mzp&P8W{?RGmr18s>EP6@KbQWZk5
zt!fQ4LTsyOe-UciOv}kITRP=!!fhYZy?Msw{a;0{?N<XtB5m$e)*NN~x&>Uct?OH$
z#Mq{N0m-wrcdZ!qIa^Q<Fk@{FYv6sH&HmafysP4EtLYv~uq~%lL!#}qX=qHc#jONd
zvTZ+=rl;86DS+a6TPy93F4)H3!Bv)OOU7?FJ<Ya(-lFNY8x)|*uqE$?NT%&82Y_9)
z`BKdMlI>qw2VS;yT*f%FY>WkH%(ijtL(s^vy*mbyYa56L$+OvPAXjWb^f1Y{O`%6x
zf$c&B8n4=xcEiy^+p#GaQ<3c!MOuq(T6&+9*lIrqDYY&5F9cvyQe>&zW~Jh#3ft>+
zJ6yB%Q|PbKHb(!Y=eo_@OZQ)uO_GJqYFos=Fi~Uks)b^$?MN+#R%h#oLu0)yb~?Bl
zwlDslqw9{#vijm$S+>lPX2XV+rZz3J%*vKoIV#@0_uem-zlJX^w#pC?1VKQCAPzue
zihxX&r3lDU5Cz#ohK%3$^w;^^bI<pjbD#Hl?sM-s=RR*E`s$oabReeQ$*T+Sn@(x%
z@UX$DfS&tCr=31<yTvJkR)x2mIv2yk+fMbL0@vzPK!NEtr(xRL-Erz~q35sN>Crj3
z7<Zkn(wA`VIc+7~9Zo;of|^dJYoSnc-)W3iG+j;^w9oE#`p^b#Jx+h5LR+uXAE&|W
zbDBrd#eOGOKAahF`m7RU(CI@e*co!FD?w}6=@lwec;K{yl650aD?X+FGZ}Syx)`G$
zbGjG@GVau&fx(APCmsMe;Z)KC(MhN8X|FcrG#rn<X{Qoe`?xTgX2GXjj6ynPvzzfF
zCD!&ZT&ZMiFN005g?)@Y)3EEx*dT#2H^!p_Q0C6arW?tFvGIEV9G;9e`j(3qBj#On
zdNW?7sM&r-8U@G>FdWe^agY)8Bt(1|Lme2XFXQVNwEP&nS76DXv790ohZyGrKmr)Y
zW}+{UF~1&?L5w-AxQ2%rW<8t<X1qkZg%HLgG(#L=aOrGPsDr_vmueWJ@mn;HGTa}a
z70%f7Gn|QFyiy0|F~(RX5Rr_cXsC%|1W_U|hLJ$gjaWwcvyhBqd`rJ}0^?RX`Vtwt
zo(DO}*iLicX@;5J>}MFoC*ayy#y=DpPG-DI8_g7k<1w1jQW*<7;Qo0=#cYst#)lN;
z%V4-JguzS(m-YZzjAiRF-fYGfv;fRu+@eC13yk{z%5518nqMz6Vpwn{kMSu5@beje
zFMwnL<4ib|U1D6JeQqHmjq2`-7>$8w6*KsbP;{0s@*V>zWyF;OU&c6P2f566N(1H<
zMkFP@uQImH0<)Zv#)jPr#_4{HzLN1;JM305)GuL#)r=KZIC_oIOJAV6&Ul{!YBdZd
zMR;y7X3{zJT1LVon01W09{{LlyxQqN=S{{P^0a|bmkVGcqm1&*O^mM`Ak7SCy02Oo
zPsgCIl`)zQ_uCj^dN<x-B)kKq?TqN(LGCgnC*a{d#yhk->R@Dv!0coMkx%y-4=5?v
z#mJ;ttDBMN4bsDSb20r}NiReG3lM#b_4L)Je#UpPusguu?}DX4#yCYKhZwO2=pJU&
z#-Q&3V*%ZrBaE@#P&&$p69GQPc=9MD#~B_}iT{u>y$d(_1S8~WkV(eI-=TVnagyq?
zb}^GF7rdMKZVRnH_b{)24c)HH^N#}P#@xLLO5K_A<3M;YzxxQfJ()jIBHxSoCPlWq
znPIfB+0T4O3y}lNf9HZ6WcJU7zdp?GDDmgZ^nM#HKV}*gZ2L3&L!kN)b2+Uh1DGf7
z0UpSF7!9T)h#4IKdYG9?pO+727V1DknA5Ys3}fEh3iC&q&mD!*aOQPSSc+h-p*`9$
z<^u|KMlwC$#t5UBE1ltCH1jh$+k2dODjy;-%v&ok&{*d8R2Uq`bfJQjc;;JFe|>_P
zwi@sR2Xjw2Xd<(mmZ2w^PG3PLiCIWVf>X>Xs((ApOrnVN8Rj*L?VM%ip>}0fGBbyw
z1S!lJl+a3LhGhbGj`;*lNomXj^Wn^SW>Yel>C8B9z%!UL=_kx&j#DBmi<$i_%w{tk
z;qj2kVHWqo;S0=E+8N|Bf3iU4B6E2(n0d_RP>_74-VJIBn9cOjj7!W%E<m!7IVy%T
zMa<AEXcaR>H=(SA+0_BvrOf>*^j%>NQ$)Ff`9(2wRx%fU4iBrCU(qVKnkjWy0KCTZ
z=EB5v=3OheHOyOdy>2jbSAki}?0X2m>zGxP*J@zq&=c3l%=rN$Y+~9dv)arIT?S?g
z^IZyH++yxJ1IgRWMFxnpGB26IY-3hV;fJ}y%%Ov`_m~UUqSe8?5<u_2PUbxNnY)=A
zKL+Vx286-kUZ#Ocj0TvW(#hyS=D{~WhM0#oKxBlOO-HLnnRDku%@}jhOh`^JPtj-P
zCYg^v2gxbs);+Mai}jZleY;s7#=)6AtU-DMxUy!^V%CkdIh0P8xU<p{(ez@ipelB6
z*3?Y2_Op!hp~i>hI0ZGntViB~K|j{1Md%A)6;jn<AnT)L&>h6m(rg>T(s{zf5!S#Q
zyhTG<bK)Qw&ibVu%m~(#{{nD~Wfed&nl*z`&&OG@NMJi=#jp-OgHgn@ULC;Cb%Hg%
z10;d<2^HZcu~Hw$wK&B}kA!QdS*QKrQ!;C|H+)KAO{{>LRMv-I0dSs`O~X!S{kj$;
zgY_4c@no|Ks)5U4EjR+e1=gGka3+uS)j6onX9<3UhmHc4ftGwltU4xqD`vIRX{Zv`
zx0C_9%(_G;0j{%nfdJO9X3;EvgH=FVm|E5{+RWCmzM<2A4Xo8X*llE8qi|OfYgYmQ
z%`6ioN?KUAeuVj3tkHgu+blyoNGq$=3PWuU)~orz-(j`VS*~{086ULnvW`+-tAll^
z2CYt(lO3Y>S<K&Iw~IB)8A`iZmyToDy{v!_Fp56bFI3Rc&uXcK?g7^GwC@~bHBhzU
z5NpP2;6_+3e}Ig#X5pcpHO5lXHhY5Q*qaW~N!BK$+-FU(LY83^F6=ce0PbSDP(Wcf
z`vsb4_OOG$LEm0>H)091T-jziN94xNu7g2$_Q!N4(SyAt1Ij$vwZCF4UTikSqP*D=
z!SHuK`?XboA7HQA2b~Am52zZ*hn?W~8E*Kp|5*bWKX&*Ju;kC)A_VXdyYOi+1K7rC
zxE9E6y9m2MY_1LDF#AW!eg?B^SEDb4{hli%!`Pv8&m3iQ?!tUHTX+iNjb#5w;nyhk
z&DVg7W`Fku9F1kWZ-b#Y_OdhwI^)@M4?tTYJLV}kbCTWlF@~1JzO)f)&ai{G!tb-}
z6Pf5sX8%q}wsY*K9s-xf9^4Ey=h-@%eKOhkRGyi|J`x8&HoLY9BDw6xC@y!A?JS2g
zdF+oUEOCjw=?qjCvUhBqf#<J?y@?8Di`lma;6(|$XATgh?DO>ema*l3K-*=u8$IGz
z*w+(a=_<Q+6-3I}X+J<)1^bE^UR1HAv?Z=)A54H3*VtcEMZ|UXniU{5?3G+d-eA9}
z0j`!^?F-3zb~Iv)j#)R^e?JX;1ACO-AdT!5=U}&qeTV{j&FuBGS8HKAD1CVgmjuq-
zX1{k8CR*8>AAv|4`wJTH9d=Lv$UXK$TJUzT9a5O+WM|MB>TY&1t)6?>+i4Nd%l_&a
zSm<NFLaRbYKfC86&;hoF%9RG$Z+!@vA$Hh2m>6b{a>0DS)~|q?5w;hFjYru-ULa%a
z$n6-@INNO}S`XPPpN8ED_Vp*AY?A$WF<hHs|9uo>njOChBXi+onlOl6oHKnOyE!JB
zp!PU89+WKG%Tdx+VjriJDo<QFEp*x3I01{G)SXk-2@wxY>E9rpoQ<0y>BVV@f*Nm*
z=nr_YpQESr{Q-`Z-f9OqSB|02htt;r*L*o^mxB0lw$8-F=+DvIg~%b!+Cl&VIF2+b
zX9?t-Nrajp&M_*UJj}U4)iA-F)OT^ALO99)6%2Ad@Q0dE&JC)W4&!`y5?AIZr$Pr3
z&dH<aHiDB!hrN$+cKwV&L~=5AKxY)Ekao7woE`b-JI=Y2hE@z`GkvEsmb2Wk4kqF_
z2WZ-g=Oig{)lYE3|G+>KI9Hc|naDXg0_I81^$ox$asHsQl&3ha(UIBHoJ;hgKf{Tn
zBCoTYCQ6MYbN;0*R|@Boc=V-l6elsH^PB;ywNB@FpMyvSr-X{(GCA?(w8qThw2-IS
zoPx)pJBKqs*Xsg@Ll0gq=O|V5U*s&I6n!4Yo%Xx=oTq3nUBJ;i1CdLd=u&7Y<b(|Z
zUc|Y68Rm;QITRBr;ar#xWu=@JsthXQi0MUenN#Tm$t#@3WP1Lta^&~GE$6gaAX>q>
zBZbmR&hkhgsyJupr>y2|;ow?a<Ge)su<M)|R037Q`Hd2eH#l!UjaDtE{1=GSab|ym
zRy~KY4$5wFo|*|q8#qU{!(bz){Q!Jw;RL%t<Q6A#6Mb3WHs`0~kZI*4OhKlNvo8}S
z?r_=*!EEQ0Jqgjf93P6(-Q(0PLth8yF69q9IoW4G?sIrlzShMlrZjptXW1-x(ZhL;
z66d{~gD%k0$GQ0_hSbk_FBXymoNhhb9^|-CX4EmnIaPwu4|B!>;oAewUk8C0;ruxS
zyQ7@HAD}hH`Gaz)<D7CTe0|9A`WKcaI8U2_o8<h#h0-a`hhKtBbDA$e#D&|r1qOF<
z&EarnH+LER=zF-&r~uf@{bV8F`?zfzpxV{J71E~=+_=Bqhg0s{M<`(H!M#e8m?u|i
z2HuN%yB>IN?)R5~*w1ZEg{1>rJrxZe<R1AMOdsx11IFviT|5DRAGh=wwEVeQ-(g6H
zxV0G&3E+PJBXkCGm-7J+;ttYw_b}J-*g1F_%w<v$Q3&_5?Qro3w}eUyLb*PnFcHS}
zp~{A%+#e~n6V82xYI-8LomAF+j9cdcrIFki4q8#%SemY)xd#@39Os&k!bA+$pUTi;
zxqhoaPH=0)u#mugodFAp+)4+1tm+i^89LB?nwz{D4xiyZF%5E_yP^OxncO!iD4NBM
zr$kFO_t8R-9BvS8B`$F9QC}{Xy8%isa@SD|IghKSGpG67TP`4%xHGBzt&m$@4G)XB
zOOgRE<`ygjvxM6<MC;E|?kow+U*=wzi@{vs%3LtQt6bAvm@nr>K0sdu_xUooU&)nw
zf>d$kl-sE0?hnL3uW>UDfq9)P+YA#m+@fFrZg9Ul3=_57s&`<pjvMd+l+|;OM56B|
z_ZfQr8o2M*QxR|@xB4!cO<ZTHlxya$rS(D!cOzc^vu<%$QVjYwH;;bUR_<?fBA|_1
zOF!BjZg(EMXy<-OyUDv;ZWM6$xK6>4?BMFQq1DCpe*!wYxo@3?WDj>~8%QsATQ*$l
z<0=t*cFgMM_P>B(4{*Oq2V#($IUk52u52rq!`v-ZU_Ri^GypNe^;!;}M!D;MKx>S9
zpbbMC=VpBiz(elUWnfNlBL={n<Sq<>r77+<e~@Wzl^%UAJgorU@8Q*NfWLcr&(IFl
zv5zOCx40|sh1b#P#tWl=4R`0wq>=;=-ZV{cp1iMr!q4o*tN$F9ym|SDplv@djS^A^
zcx9V`JIH&So^&7H?QsBnc`v*PxF1jQGywj*iDpP1;=M;Du>m~Y4u}Nu{OREca`2v_
zxWr*z#&<vj^FE<%N(gUp3X~q<1+GV5DDSUhz=!evq?mmKFDw~;ALAv`8zhof(hF_J
zd1X|{7{mKQ3=^@uMO0*Rg0}<br)DMaS}7@?$Q$W}>QlTyI#Ya_S5Jo(&hQ-f=slLg
z`;ZpQsk{kVFrVXPJO>l!c}Z`8r1L&~1NaPHG7Ba$d7EjQki~oUd#K6bb$yJ!3%n;N
zJ)Fx+&|naGycr|#H=lQKBXkz<%=GhK;@$cX%tGD>{aVGm(EDhW@XCS~Z^TI)7pnHV
z%KMI1n&rF^F0@qeaw!>D#Ty=hOVzwdUySS;&qArx>%7!_v}$;tQPlSaubcs9Juh1f
zz)jv#I$YGiTRaSrM&3;_)Woav0%_(Y<N(mZTX-42=Plj@r6z9k`W>`B>ExBY1H^sa
z?)xBJya`Gibn|9D0`Gfx+i54>$FnT}v!9pr3R(lafO7N=@s=k8KEliJM&Bs!dD?7@
z@zN;1JkI;34t)=KPvxU;g10aWj!yC(J_qwtyvIL)ztcR=&GZs>;m=zKvWx#DWkz@N
z^OR`0@=NHY<i?K?fa%U(O}B*y{~roPdGbFAr@NBBiL#d7{EO)T?B}ngAo&6Qu~b|H
zfBvg0Ko0SZuVbJAd@0q_2lDq*dNzn3GX|Z9`LV4}s&VJ>Kct;R2;YZts7Ls@v{Q`W
zb7;|WjGz21NF@J68AcJsH_-wtn(uxCx{vc+XxSUXXWW5_SpNG4kU0Kr`ry(@zB8p#
zlKAT=b##g^44S(MKlbxUU?%eqRX{R@f2jvrQu!z6!NPg|mibVY&VTh4kPLpp1@vX|
z-F}6mS^S`1FwSg#5(CT}zTO`q7x+o%p)8jleGkem@_(V^e;$7(ZA|m|O;cbN^X0T6
zF5wHD0WakbI4)v<W&DU2F~G}wmKEBr@MqH8bCrK<5iFJSKX@5REBI@gq3t^V0#yyv
z@L#2<(GC7eTItpD&(Z<KI=%~K59;}!Qc2oP{@o6Yvw{B}J?@Qs31!1>^Pi(Cg;st8
zC8gW=j~=EO{|>*r7NnieqFenge-~B8-Q(M|ARYWFN|AT+D=C-X%P%5kAO8_bSN8MA
zDK|F2AEd0uApiIn+#ceuqBZO={~s14AMoeVo_U0SicV;Z^GD{R^^o6}51%IZi+`jQ
z*Ce0+3$#t~cdmiVG(VrRX)c0L3QF!0SSii9Taf+^MD_@Ha_HVGXxRg@PtbJ^BA$X*
z6VdV#gi`{_Tksq0A@>XXC~kN_P(B8O2L-EXdh-z+PJ+L_g3>`;3qQg9P4q2`Ai=L$
z03H@xr1>dWkah~%LIjH<fH)$^qkvYZV8|6dg$ZW<1N>2elLjWj1szTpMYJH0?zQ8B
zt#q%&2p;JGE>>`gB5!em1+9R`3sUG9-wA=oIJ6`P_WuQvD0r44D~>aQ+5f|^&kE||
z;Bd0wm8Zc?5u^@4cdDR!Aq<`q%%|W)n&1MRdOR-}-4EUA0#zmqW(jh00M8cO96~Ec
zAfmPN1%ZeTi{uL8&co4*f*VJnEKgwi9v1Qi<*Pvo1V>9T+)EC@GnC*j6r`0wcafl;
z&S_j0d`{trD}o1eK&}ejdkOe*!5j-LRS15*21}KKnim16672f}CaML`UWU?Ifh)b?
z>IBk*5UCgBQ>5ai;5RuW8w4R*45Cr6VFG<kg1U{sH47Yll#Fi^G{!^s9l=^3aN7mV
zr|Cu%99aW$PoU0*(hk8>w94odEV&H)eL?JRAbo-%stxHE*gAn55Nw(Y?*|3mlsy;{
zJjQ|DVZpa<@Zy0WjaCUG0zoabj0^TteCMIS-SIW(gy1B_FD3;p6uFxcWJsW9TF^&3
zL^ok`2u!#Ocb)~_L+CRbeV)P_`(e;aSbHCEZ{hZTAhKVW<OjP4gsN6Z9uz80!jg~h
zB7O6~SIDGFFF)aPR0ioU+?xW|4hcW(_yNEGVRaHZgM`Irq4cn@`7qQ33;*W@ze9wf
ze*k|(_}X5OFf5NDa#Z*jm92#f7cYb4F=2I3%VtbvZnT{_E?oH<NSrX`LrBI8kI%-P
za6*_&Z}J3TsSR2Zh1v+<P6|_KHI^i-9D@_5gumYbIW6p@N&2j?PmETwa19;kOc72}
zxF%I-qs{#};lFe+I8AtU8eXRhmu`nhhVY1EH|%B#YmPv7mT;#Iy0e7~C{&Om<o=8c
zdqKFq9X{m>_coyKqHvndp5+Pm(I-~&g+i)`D-bqQ-PI*w8r{H!LMCnZiiEGW0aq+c
zqTp$X&@~P4Qehg!-OGeYy%4!9ympz2*RBX>uY>zng?3uNlnXr`hqemgR{CM8g}W#L
zbxl}9iJa@gmnm9QBV2O`tsBC(Db-Xf{Ep5{*9+A*(05b#CshzN2*YXH)+pRUU#Dvl
z`hO16EX<^}?=7K%c1X8{XWpa3ORd5u@1uD~_|q|HYZq3Dfxj!fmI!C=3Ejt`yF*xz
zjlND{r$0t<U-;$c5a|{s(IeI)9J-6a^a}5sg!w*U5=|8SLj5j?3<@96+IL8p`Wncv
zaExB_4}_XmU~fd&hMykEL*a&1xCjr0-+lq$gs@{LfRn=V8jvaBN;<$gExh3ayo-oW
zHKe;lX;jC%Tl6s%CGQcXQ$TpH=s3ON_KDUdpwCsb;4b>yMEj_|+g+4L7vDovPcxyX
zXf_2;y+lu~K+EARI=2m%X1}O@48Q}Td9BcPP?SUYV;@maB<%W%R(%EHCpw~n8h=sp
z0r-1J6gLGE0itiW!9<`ah7J=3iK;&b^RVa{14bAuYNMk}A)+Ppm4PFoAgZGe6@5lQ
zpD@w+FF}qvL~nWn7%nRMZ)GZS{t1X<qDNw3B2u)3hgOv6H+m06i}-Y}9v6Mcfuk`Z
zcM2=Viq_MC&=Vq$w_zed)Jm`2MA2-jI6Nt8!s(@1Ng^@rT~CSf-h$+5QTp!~%NfzW
zU}!ljatL36Q^}&~=b$@9w2}+aRMEW&be<C>)nhPeqLoyhcV0BJ3$1j~5_ep-43T;Q
z+A>A5pJ6adbn`y6WQ)qI=*tnE+z-hMqBnzKK38O=-|nJl|M#$vC+d9>BKe}}mmpFg
zn(H_SPcMn)Btf)L<a`d?B2g`!B`y{Xu7DRMqQ%qbD-{*f+*u}CO*8mqk=F)@ToF~S
zf%yv2!wn#nqSE#7zDl%|{>`FV^!KwM*F^7AdgZz(p%$b@q@fJz4biXDFjOn5-{OEw
zo#=m$gIh0J_7X1XP0_oQOK1>{z7IsBXo@EJCXsO*em9HWd<TPR5n1R(drMTZ9`M^D
zy$=AbqIOF6wTX70fZKOO0fAt)i$?xC&LZMnMPH|AaVBv0MITZ{OqWRhJr$33i=K3a
z(jHMCy@2{e){RiwFDj!b$bhJv_UeP8ggL+ui43FAJuKSt8Ptr3RC6)kjEa`bfrn!v
z!6YuixG0W-3J*mu{{`lRC}2Ijm=bNFG}N@Hj$+0x;=^=aXSdi5!3-o1#oA41?iD{r
zbJ;%e5S>wT6>p)~pu2dm0>ndniHbly#cxue#7q1ymFakkSJUyi{bETP;0MLU3xM+x
zmv4eWUvcvyF#W{aXer<?uAsZ?koXe{O9hIrP$Vcw9R3n?Iu48FRN)dT&Z7-tn7ES(
z?on}R1`y%mZ4{M@5GPS6C{nzJcCu08ntRY4ExuX~ZO6rfw1SEe@2dwhR$S`|c%1k&
zy^T(YH`7ZvLF_1pmPB#yDBvf>DGSk;BwiH__-TjOv=I0+;{QDlPtS@Y7Q?q>@#9J$
zQpAlGT#{6AB5ljhi93W4Nf%EBLurQCmGZHf;_tcu&l0z<huv(kjj|3G#Cx`2EV<(G
z<scWu=l6k`CyrVUgZbi5UWDob@uOGKS15M$v7x3&{4_nr#o}d@$|w;}P_=5QIO<~<
zEEE4>2mXrKN~I}R#c@=XUoQUXAX=5;88quviO)U*x2wfFs3zr_xbb(uuZy?P|H9r7
z&#l3DYsH^G22v*uCsHq-O*_1s;tB`lDH_DpB6!mzZfSt-X0boEYO`9zUr<=<me`eM
z;@jfxO^|FAKS#mHJK{H~I;mYeX9LXN6-QC1?Y{Vrjlgw@xldq(-C{2lyyy|XyBOE7
zS8QzqvtN8TAIb*Abt}*s6gL<hphIGD2-FOVtKHFhAU;QHwGpv_0*+(iz;zhtxcDZ0
zi{_y?X%)zX_~k$_C&i%`0GJjZ{T@EKNOm^E!(EcGui?dRNhH;F?2+6)gYoW_?4SYe
zlbobXvAZNB1{ORdOAk}=sHfz4T4#7kPJRsHElH<c?|#X>VaObitfA9z2PGR`#VC9v
zZ%}65SF*MmuK7vED2M1TY43*aLz1d1kPMJ~<bzhAWJ3#F3z9@V3UXND(*?W15<jXn
z3Xv@8$8e8G++U@?1_+frdk@Vp$t5?8>8PY)Elh+<0#*YNAz2WPzGD(!fAmF4me6}Q
zN>W$_5-q8qQqtoRE-krYB%>{mjFsf9f{8du)}H{xOD?|&M^8v@QHf)MB!fz`5+xFP
z{7*{cv?6yTNfy#t;*_ME^46y%<&Qwk8OcT`AkIp@p{!xDB=HM~rby=f3T<hUlA{2e
zm%O5YiFC<Us@2Vsd_;+nY{^?5Xyr)ekD_%^5=E7cd6GR;ca<->N{i@1$u4?*7D>+0
z{<hd5S(XJvndIE-uyk2+j6SS$MWUe<ZiVE^YP2dPkyhZVBz={*GS?+er=X@r;zTc*
z8xl`8;Pn#DA&A_R_`L<vAQ`0V)GS#^S?m_c*6*O~mSiDvwX<$Z0x5OVD*5mKRof(v
zd9=v8Bl&{LPueAM?_y|oC7m@;b5Al!3$YH#Zv_y!FL{>o8(oqp`XWxZ<XsA<^+^7-
z;y37(Oea9HUsC=ja08NgFT>KH#P<d09Fll`3!TG~pL*cT14;Ye=o^uAZHBT@$sxxN
z;EqX@=OHsL*?bTe;i2SF`e7#|Lv*iCN)ALr>6C<D0m*5}9T&RSrGI<E{4S}}W@y_j
z{ro;e_DMC-Fz71XM4MkX>0`7GbeFD~glZ2dUxk*Z^iKyQy`-g=An7gr!JUd{4oDMd
zm3C12HATRDq#Jm!<SWgisnAa<rN`J``W2Oi9g==s4-z0Pq6hx4G`Jmo!P3WRMH3<|
z>H;84Dxq?wqtf@p7)!V`wg@Cb`pF6O9g}XPyCh0_WDZ)<(zSQ!`8zJ%=Zj{H)cylH
zW2LXqi#|^3b^@(<>F=8`!V^*!1&b4;t7*5MD6OWMDOK7}XJpPv-Kd~7O`2>1^SpH7
z2*#T(?fw~BGNi>+g`6oJqbh?esgQOO+0u_@qm?858#@=rtP9d5c9_VOenORl7o`#k
z)Z|H5Qf*hhbQ{gK1=741p!AY-xhKpQN*CxLQY7`Kb!)M711%6rq=qRtQ!34)q-B|O
z<}gfLmM$0u;EFWH2<BC35|td4OViRJSs{I^4@^g;bf_4jRZ`bCq2{`D?J`)Zk#3EJ
zr#GbYABFq%(r5~Y+?2jccUgn9u?mun(ux*nYm)v=B}dKD4RrS6wzP$+uv(>WEeEbm
zdVCV(j&%D|fVWHCvH`y<t)pvkPkM>oLmdw3T{;)iDGi`4$bD%cJx*OxM;Od^OJ8z=
zwjSy7+34$)b`QZ|pR|vOR=>1@0<#0sHc~n$J>!dOF(f@$1d(CsyVv2&1L^5<^o>Zp
zD5E$keU>iQm~<N@mB*#`o<-k7siRE;OB2#*N(oL%Q=i1prlkL)ztNtShFEa%U1ZHh
z;CIRDYvA{8nU=ozw@0>|=GVQlpk5f<Co|Kd<|^BJ6?WZZ*+MYgWrOr=dB~po6?Q#k
zCGD`_C0le5OmA5MmH+RT<vM76b3hhOdk<gP2NWgtlks(s@s}N=V>E|kt7u;zAiGro
zM4)W!FX#@EJ^Kg@9+r*Mv=c1j>;egq9Swlw5!vim_!}ylN3}O$vc>cXk)yJ;wD1g<
zy+oB75i$dn6&;f${!Z)9NZG<<n2(ZKZ^1;gj1vzv$7Q;YfRB~EPjQeqStHH)@v?+_
z5IG@>rz18AvUy(c@T6=lWxtbTPPG7>lI^73`dQiZmyk@BEutwnMfNrQpsBJ9SG3N_
zM%-a9O%@YK&)<33XS7X8mwl~<(hON!Gk}@0R3#8uGH*J0mMybU#Z``M*=sOyLH0fc
z)pKRPjKKUwSx_>Vd9w9XRFyA#>>*kOvXDfK@RBU52C55XSAs!`WEbhRUo4BKeOQTX
z3>83*S*5Zw|3I`%mLHGb_p<Cu%6(puZLNfftFlueuv;#Boi<q&veUF%sFXcF2tbuA
zkJj7OvXonpye7Ncg1+mrcc}8HR<^JZUew7P|An<>nRIgOrmW@~m<_T)>T8tsQk3nz
zCfTzzp*PDuTn}!G>{(i%+>*u8$+6oqxfs{0P4?{)4DF6g7UUvC$YL!ep!#G>{so|4
zR+f*}fXw%8_%tXRhy`v)W~YGIux#lyz#quI+zc`zTSpV)nCur1jDB49wE%`5%AP8Q
z^$A&o4a`Z|R}?3jl2t5$>S@^*9boQ~e@%Ox-SS!A0lr86k>e$BUFGLHV98DXI-UG-
zmoIHW%R|0%30j`=_Y@#r^77ko&0Frg8m;~ERdjnCkWbLXKPZ2lLf*de1Q(e1ldm}o
z5r6s9cQA-U@>t4y1;~3#VK-3TnFTFD@|`PSAy}T4PxU4tavj~WN8|&20EWtUnBjMr
zTuQ;KaQP!tb`l|9P9IZ=ls`&KuPFKE2wd)HdCe{K#mam5fXB&m`q39J&!XtWS$TFe
zEG5fblYmQ+C%*+RQss&CYCI=rFM-)K`3~cM=k4TI=umg2e3=B?EV+R~e%W$m1I*{h
zU!m;K1$lr4x^w0CSul7}UQ1ExJo(N+;PU0&zX4DnpE&@#m*gFb04S2Lei?vb`Naj0
zERmmRLaS8%%{TC(Ozx2i$*c0p+4RaNm#?JvUxj@3C3IHG1z$m1mHa%tX{+U1TH(bt
z`9jKRUze|S0<cCtixxdM<O}HtN3HxpBP8qOzZc;m)XV1vfZUWn`W~1Ka_)V2*eGA#
z3|y1E`5TaCc|QfRTjWUz=yTkXt7x}zTh5M$rB-<^Ee_k{&rurSj(nIBzwPqZXiIxn
z{`G3;z9)aB1HcY>6!mq=Yad15efcVyD7xg`wHQmc{1?h%^~h&UfY~c|E(Yn7-=k1g
zzr2V(Wj`SQh?2U44*9%a;na})-Pd7$SibHNh(3@nrq|ere31r-QTfi55E+xF&joN?
zUSo&ILwV(&Ffk$jht8Tz%H^RDnUbf`#$Z~`qwglUC>qkyw_A}#ahrXLcY*<TRn*Z^
z!cD=UIIFwDQ7Q(|L!qTDrl;cPSJCOED5wX*TTw=l(*25Mbmt#X%%kb<pu&m1OXH*X
z-#_T{Rs3)pYWx(dO=$Tm9{mWdBZ_}ZVK-FqaVJ!VDH7?cmPZwDodq*o@#_Vsj!<k=
z!I@)<ZU;qCBNgvck~K;ZM4z&XR_yr<z~hQ+%BRLCzNE)LR`JR^z{e@RrkbC4#fNeL
zPAH-%=AEFpK`ZM-#YPGRpH%n;!ows*3Ka>RQaE3Q<Y@)(5hy#O*hee3vx+@GgPE*Y
zmq^cFisDOmxR|PVoTkZh3fITrMVg|(59GWe=PPJSS4b$-nW0dVWTqlz4|HcK{@4YQ
zttg{8J4dl(4n!^}R{swqR}n(L>qSK}Ra)gK@+d))ub83@L4l&l2$4&Qp8_fSQK;DX
z9Yl*2Z$E<zT%ySN40cNuN56#KGQ~UZ0&!XK0y%s|@!B`I2v-%y)<9diBAyB_DijA=
zVWLv;*%pv0#U@JIRV%9LaM?A*$D82q4TWt5`f3#&k+4vwXrx$fy~2nBXViNs-j9Mz
zgF-V3FB%o+*8<q2Fj2^(S@Gy8c+sMm@eS~|6v0nH_ie=jih#E&9;Ll|o1*n)wC*Tg
z^MTTK#q0D_+*LRqgqC{>i3dbF6x-&*?M}rFS`pk=M1F(5E`_`ZOh>okPm03!D00^U
z->X<m(ceDBTsvC*iiW*t4Jd9>RB}+UmmZlRMXCvX!-}Hsah)D0K6e5cQK;0A993MQ
zwc40spbmD&6)QL(4;4!!FgT&$&H#K;QPcx6rKq6V-f4$oV=Fpclra?c-J|?C1BkuK
z-{@@HK4sHBToQL>%?vO-l*Q?=<f+{F2!Q*Qp-hki%6LjtA5^w&hEG1q->5{<S81fO
zEkETR+PL{E|IwgzNV(k`BtRKL3$Q?C8Lj_<l#bF*&^)Z%N*|#JRwmBGKtq&sQ=#UF
zGE#_EsIoo>y2F$_TEibz9(fsR!j<bNNEo5~V<}q4lnzSLMk*^P?h>WkPA|S_<@>Wi
zjw|()!;Dc5Uc-=LmA_G_Bu@E_2U-crM8_|1BT?B#q3n}N5zTt1mB;9wJEMG+)`4f0
zpHi?dS=n5LR*G^a3rbU!-pj!}r!+keN7IyEuYq}9$vp{Xx{|va$}*IUAD}u@`ObCd
z%u-f<g;uumITc8ba(N8AxS%}YNg<0|Wjo~?FDhH9nkrA3OgVyl<*82SE>OOa1otl~
zH?^U!P&rEB<|1Xv5;#+=bY6;|vP9Xi4cbbT8)=p<Q@%vsNxZBS(Y3guTtoBJRpq*D
z*sW9!PzhU=GExI(wepdB^u3j9O1A~TUst-kiOw3O)d&-H$}ci7ih3oVQolEqWp!wE
zDEFO!(oW@XVwk_L{Fjp9UCM3rI_p*rWx;%p@_ZSF)T{LO0<%w<R0UkW(n|&l1Iif`
z_!v|=?x1f-IgQYrW7e?p^)Q%tpp3Z$(Glg!n{a<rInWK6G38&hI~rGR`3AZlD&M(@
zD>I?w(u-hHx%?b(E~;`rNbXXV=E3f6RTLeH*`o?g0CTTObrfWus$nqzuBuH`0pzC2
zr{W}cRVc;P93Cp4576{ft)N<YFI57ig1l9ZX^8Gu&0Yy@2UJls>m5{yDf;B2TDt;X
z_^RF>grk0{@91XnSDjQq%OTZYw4Vu3J*-13P_>QHCPAv2#Sl5HvQok#Smi^p%@EZ-
zBP<+osO%D`301umgJziO0hKcyRb4m)e7I_e=E(@vN;%XVQ$6H^8L4`VZm1}g|F398
ztM1w{wBxFLdVXS5H5AB;RUPie4-=>2(bgqib>Rt!oKOwVg6ag-FV6s;sCt}^sGU?f
z_EKynN##k?$0=186~doZ{Y5*)Gpf$nP;*x0^9)F`s^mKQQdBRo;ApDqZ`xCyQ{m%p
zcmP!CtpJ=?<!!?V(^U(apgTi#E)^tG#immlS*lQae`Tx0Ou%zge?<UrLG`*LABbGl
zqbI?=sM_%bl;)|NT|n|x(z_r9s%F~DUQ)G0V}ymO;|R#lDpGw+GkLLU5lVJvm8gE9
z&n1?sDsRA<GS$LTFfXeD=yG3CSt-0-p~_7`t5Ws$d9<oj9#jKbt=jn{1u3qnMktMO
zUG?(kz}KjvJ_YlJsyzwgtyRs52e3|6Pn)ZH)qF~--&E<#!E8|7ptV|~sz`(D+@uPo
z#o;Yg0G$cAt!n@8C86qi0m|A`&&`0y9aZE~xZSP_+62iC)!Yy1yg{ex;&14@ulg(y
zUi7H`N4v>h)ocHN^r`+w6~lw7b@!okNY%Rvtzp$ln!6vU8v5byh-!Q@`bJfkUPWt6
zwZjj($5n1rUGz}(K^e46sP>eDIjP$4KHQ#CeOCg&v})_?^!&M~BeuZqE_E<%EOx7F
zY3a2`t;+#(uUaU?596j@-v!<7>L+Re^iVIOHH^1<a1dVXR}UQl^MLwK9^ePnK2%EJ
zqn?olfUo*rD#Y+pzfc3W{ncvPY#dTwc?Zq}sNMO1I|9{fs30#$y_kZ}ht+R=g3e&|
z|0bX`M7^pXtt0A$mGCK4UG*qTgsH!605d`zB!P)z>LyRXBh_~t80c|zIo<g&Y7`XU
zIZ#Kxj=nhcY!Be#)zT$solw6*#i|MFtk(cYbf{}>uyj%#>4`BVsb|ySmQ!lUzi6FS
zFVsTjjC#k9uyj`4L_z*!b?OF?6!kL;VIoz%gjU$+)H9OcVY>P^sw&J-C-X7hOtmQv
zB6;d3<QQ4LdXmBd1?pAV@Zyqs_nTlAsvXZ$LaRvqW&?o5>Ph<1OVsiY04#+iI8&x(
zQqJnKI{zskuBa0tA#zpi_zR?5Ej<KF6>1KhpQ%(Ql|pxwy6!wkwc2SeL~7J8(0p@4
zy{8#kYSkyI(O0K_gmNkMYK?>Lotx@`A&>_3H_O3oRPUo;Y?E3=rM|b+lWick)$z1S
zYE}Od3CT8fE-j(%s8>-|tzG>o6(8JHi|7K~Q(w$Ot3!S8O-OdB4RqwITm8Bi<Lprj
zC@0aY{(*wled@h$)AQG__7s3Spbp&$-v-r%ROd6KK0v9|5p`n(n4{`>l*=4bFP#mg
z<LW1<#Q33FOHcZQdOQd4NwtYe=%&<f(&?;eHHXrNyEUa$%e+Ukj^_Nmns>W!5!^I)
zT+!#QS^pO8|2#AY>Y&YA6aOe&+^@-}N9};-oC<#XYMzNk%TMzNg~I$b0hD|V)O0+D
zz97wGze4w6&7oMpk7#C;pcSfFNw3&2P0s-sjMfa=064Ds{0_9lXu3<$iq*VNIh;6+
zZz_fC<26&G&~`#IL0kC*jg3m}6E)IeFi&behyY2_ETgc~DUI(J5IL>c#)QZjO>YuL
ze^#@866TXN`UaR!(fCueIaM?I4RGf)ef!W#)3|*BgXcAeDq%idlTT5N3{8nM0FF$}
zuH8_YrAhr5&1?<(Lm+ZAWxjC#f@Y9Nu4c=}KwQ)`MBxJGYl4!{D$wN4flrq-eH832
z)cp1?d@9o1h=a0X%~?tamuS)^0WZ~vC~;7xdHE;+mo)|o@?FtHhr!-ehvpg;hm~ty
z`WD;@O(@k&Rch)Kz*lM3?**b-vw-S+u4z{9h4~vAV=tJsnu-`m)@lCrhrbP)2Xq>(
zQ6p}LWRqqNN#4@%X=Qy|lS37Yt(w>Gqt&L__6b^dG|NsvOS{I=Ljju(O(Z4dJ2kbm
zPrt8ucO5QNkLFtn^7m>Ke*oC0>HY(K{hDm5QX0_g_ym1}8buPA4>TXsygZ`0`2onN
zW<Fw3vmR=Ksl;VM(?mI^NzEQQiQ%H1K||W56*ADbTifj@g{S+p+g=6NRhzv9y4|#2
zPoU+lm0yP%4{hlQh<IujQ9Zh^_CqT0@zZ9xgZOKgQrPy8wtxx{1GJ0WzzozrL+jok
z?VNSEz=yTlsRT7x+eUe`5N#+$0*+``y$okUwfE8;XohKnJ>bnz?UAnl4A&-8)Hp(0
zt%5Vhv}cZhL~3U@L3fn)?n(4TYfsXa__%h=0urMQ<HAI&w&^zd;<Sq?oEWcta~b+h
zXg`dG-2`n!KMW;md*<LWpVYoQ2ZoZg1?BW_zNfTJR1AGudx^sGXSDCo`O&l596HC6
ztnCd(D@8j*cW0{h@*8mGoc5(2w9>Rs(K(~@TJK<JOV{3^07!<mii)H%wYM&UnWc5V
z26(pCOp)0fZTI^SxuAV{9$LBD#}Np3%(|$}w1S(beVuOWd~G!aPztnFf1q_qyYd<=
z6>8;vXccLVv<4~GwozuZMC*DL%u?;kw0J1fmQm96vi5~|xP3*tk+SJmwN(@;E!Uo)
zTB{1J><C)bS~ewEu4&g%RK#&zTU7)#wOU&QxOG}P2c%y6WGDP?)cXDeXPUG(_5s+e
zeM<%AZSBg}psiIKu>*G7w8w72;9c!@+63RzR@vZ1hxYBCptDoE=O{$(YsaGi@6xWJ
zN4s0QiT2k$+NUYX*6YybQ2xD7TT8!MzqaWU{1gM)Rj&g$q<xXjE)Huyp&Z=<?FI?#
zj%fek06(g|{|*d}X+Qc7fN?FCk^>L5mni@;p$#>FIjN2Fh4)k12Zv#4TKfhCzg%>=
z)#%%$+d2y7Zk?l91WS8#2d;wb)qUBH!R*uB3Ph)??&43-=BC^5-)ybxqN-I7-9KtL
z<Ed-?6S}>0p7l`bt@Aa&{C?dvI!bXs*CB;#2X$vJz><&d12ZIjb-6KM`srp+Ai`f)
z@hKz^>9#vw12;g&q(feTy6SIng@SZpl=?cXdo~Bo1nX2!LnK5O`W`$yqRY*P`B2^8
zR8kP8dz04rM|Glka4lT-QyC;9bUk0g?lIls{pgF--J(xtMClS%f<)^A??Ux)U7ZtD
z$LKt+(DN6on;i>aoNg~oRPnmkD6Duw*Fn3h1Rawmj6~hfJ3&tBp1KR&NxJ1*q2`pX
z_z6g!*8MdTeP?uUDF8UDv;GQY$vWoqP@SSX_7wb0)m=OaXU^${=RqV*H<MOZ=XKUf
z`rbpj&Qkz<hOV7T?K5?oQ=v3VH~bZ3vUPe&rRL~5C|-O)C#6MguI@e^m$;~Vfqteu
zozDk==j%GDys1F<H-%p>>15BMRj9jWgZU!e&lFfL)(wf^T8Ym0D*#G$$FNU!%qr6@
zr0D)-U12(aS9E*nb#_(f77E?vx_MNkUZv}!qx99f72l$DO&3Uk-s`$a`aVUC&f_^~
zyP^AZH4N730_^Ck(@netW%as!d;o6h9`%LY2Hg!Rt7_Dprz(jiUFr(}IGS~9a^Yf&
zj;n{7Te@Ymy1T6le-&z4b${D{Z_~*sh<r!aL$BX<oj)BHysInTiPk;cx4Qx8(5=E^
zdRC{-<wuyfulw2;xGtR`4wkxgiIn#5(bX~`(yQ~LFms<SCkB%J4&9SVa0hfHGccGz
z-CRG24(Tdrx*OIlq?&*Sx`}XzjOgyqN8hM!{$h|Z-K)2OAJ=_+0Fn=NAJGbXLKjSF
z<w@P}E?m(mT_+WuOzS=-)h_z)p2CoJ>DRMC_Ue-<iLy`c7^06Gxa!MCK-~0;z5v%<
zpArFW9{NwI`p#2-<7YVRr9Zz2BHsGnvcTN0|A(ID1NwPCLfb+8ktblnNB=g3c7639
ztpd|eKS7BSe|;lGhz{wCcH%Mz=;zmBNP+sy1UMR`zv-YL|6zT=yBJfj{@<TqB1Hef
zEQlV_SJG=gRG&iCU19oFEC7${cUb@k*T<*BM1=l#0s4;Vvo^rrNPQ5&qx749fosuv
z*G{yK>s3_vAEU2)5?;jWKfVhsar)CggBh={?4<b13H?Xk!kYyBuY1s$sOKa=_enj2
zrqU$+kF@7GrT>TmT&MNM3lK@xZz=;mMgP<em`K&{pd&%&^qa};G=0Y&cz9mllL;;9
zdhH?rGW2U+K`T?w3W2gL{S*s;Z2hWNX#JU^-%FdNi~9GzhfJRS(I=oZUvHTOgN1sp
zVYG_$quCHC)<;l%dzoHL1zeZ)AN&9hujpsdwyHwE+6%fX_5B~CRi!_?7NlPPiyN3X
z_2n5b*r1Qkhq6Zfo&n&R^h^Xk9J8ABB|k%Vi{6)N-*4#)=+$vs-?t0+R{d4lgSY9|
z({y)7ucvb4cKrgXA-b!dx(Shc`p@6T#p}?=P*|~3f3zHZ_x0u5VYf@)*$Q~Ke!dkW
z>(R^SfZ3~edj_~Z{iAdTI{Ni5Qa#sz{uPRP4eB3z6KaO^Z_yFcVg2({U_Q{_H$csZ
z{tH^-KGbic8*xIvq6H$8`f-Y7P3d1Q1an&d@G1Z<hLb)R?=C|_8Txh`_8fyxu7>^e
zI&w37PM<1pH>_*I&*b4Sw9zZa(;%dY#>?RU7|eSc!fD61-=OA#dC>6DW)L642Xuzs
z*AS5hpr4_v7;5|temcMp84?T77hu>E3rm59u|kLh88&~6zQcxS21tm(jV8Y%hOPp5
z7;5;Eb_-z!M?*WDI%-%>HM|jqKj|-(ju~w9s74xGDY_VKxSxTc9XB{rqB6!1MlZKG
z!zS7W#vA6-Hsge03k8o83>j1;nP@2QN9&X!>ut178!9OZd&V%6rpdF0Bb1j-HYoHE
zNin?Spl2o3aPTaYo-+uBA)015{s65EgLo1n%rrdT3DGRWtmTl*HpDVOaty;~!MtDy
zrd@ZgVcS*=;-cX+ZCmpUQ;(pPZ}>=pz5>HH4=|QXhS&H26dJPWbzfxAZb4tMp|hQ$
zDkTOtHilMeaL_2q4C-HjziP;&#8SCo+i5scVVL<Dn3aa#{{X(qpr*o?Y6F9!eAf*7
z3c<W?*l7Wv#*qCzJiK8L(;BhXut*BYI>Xsq^xZTB&xEoD!`}@US)*awA^P4*lR--v
z(q=<S3S?Rg?~b5#%kajZkhyJ$=z{yLhN?h#*k<^Q4piMSd_E0kyWv3%MD7}%O#<$o
z;rEpw9fr39!0a@zDGqtx&_yRYx(ucm^mQ9DUqY+L&=&`vdJPK@Pj}23Ff8szbI?$s
z2V%(ZdJN2u7{;kIZqyLhg;9(dZm$IyH`ImWB0Mx?u14R4;pz_HrVaD=K(~wWjja&b
zWyFn(^_1~PI&iwz_zo?4_8GU6Gp@$VbX&O@twOZijf*Ku?C>y-PD72SvHx!%yo^Eg
zvhX&pr`6$p<NjBm)W<k+9K_eSnM#=aj2aVw{>IFw!8~Mirz+n7W2rl|1R6W25IM;B
z^%$<xVPgs{n}dx@X@?nN{F`R!BSxbuL_&>$_kas?7<*1a=}}|88TfGH#FLPTFm9lO
zy~m91R0b1itfW*!l=0pgkXYk%1@LjkVJb+BHy%S0b=C>vL#mcYFz%?q&y;BNx&z%O
zja#e0Ofq&*viX#;Hwfgkad!?x&KUo$h3d0LNA_K4OE%7pgTWM|k%|yfjlC3{IcLl%
zfJ~Y(jds81jiFBgpKhF>tXzh%`2b908dbEs$}*m;hZot#Kw4Sk7#~nH^MdhNIsut$
zyix#z7me*kj4aP6djpdB#*dbQSzvtKVZwF3WPFPj3WdhEsYa#9I7O{u<M#Jpu*7&_
z87@$%F?|H2%=oMV1}__L_dxQBaV14_t{PdP&{l4I>?%lw(U~UJO5;wNQmTv%lv1fS
zE~o(DnlXu{o9o8fci>Eo@p~JsKW`Y<R)f?UtrVWGGv-l>vEKMTd3w{xr)Q<Xc#KxF
zjmDvmA<|@YbVFOSG0YFTTa39B<-28Uq3`wGHoiu+JgvsVGz+vFeL{e{YfO3pefNyf
zB1m=^Sq9)bjl15WBLnx1#n*x8GV0&Lc)N`oenn@Gal9D=?KQ630!w|yMpulf-+0gr
zkpbgvD)|~Tx_t)bkntKNI!BDwHy}A`45zB*F{3|)q{fZElKF?mRkT-{Fup=l_oQ)A
z5S*DZhI~%ndzdzMuYgl7rlpjL+GT2B!0+8AO$uc8n9j$cwbzuJ0ic`7K_`XWO>g7?
z;9)vV<MlLcqwS5CX^f60d7I`)VQIf<CgqL}nEv?*t%Iha_n^hcR7L-A;%nMQnJ7P#
zmhN1KzbX1<s5xXx9)(PRN&GLkfu?IqVIs&>WQR|OO%ns?3pRa2vp|UHC>4+#F=fqx
z!BEqCv_=dw715gOsOiE2C_83~pc42<(+JI^Q6@7fi#D~~gvfEzxoKRk7?VB<Uc@>~
z)pW)o&NM;KU%ctX6_7b$x<%XG1XBzhZAvulq*>&oDU`AiNv3v+5}Y=bx}$Z*bdL6x
zXHD-p;ApbR{~zd1F}2VIPBks{K;Jpj>_(6@(<K{xI&WG)-xo|bnQp_U43p!W6b7?R
zkIlo=oMW2o2KRz#Zan<XGc9+3<eSndmQ`SKvSFZ?Oza7mC^TKA<$jTglY_ou(~d}x
z5|e#9+%7e(DTbvoQyL|*E}H}t>$qZiY#o$cH6_qJUT#XFm_dap%#i~`r74ZdSF21q
zGt5_;f`5VTYbL+9(0AR`{VMuuOm9a)+YQqaI!#n-ig+J=btb{*xIp!$!4F{Krm6mS
zjHSW!!7I?+Xqu)4T$AZ-F8pmaDJkLDV%kZSTenOfP=fQe3IACPM60QjUhQorLjcGf
z)079y-!*w^0la4#_J!^aQ$4+1I!$lV+w{KaEjr}cWqOIqin~q24Pf?|a{mYKdrhD3
z1hdcd6{Q3EO=~{Kum?<Hs@xhhsi>f0$mB|7*yL`Y{QCpb)0B!DG5wYerK2Xne2i(#
z^b+km$4#rKAnKuM={S^5m|}K=IcYMc!qSw<PPgT>snh^RUCafiz}#idJqXF&=5+c+
z_L$@8ExgzK8Lj&FnU9U)Qo5SQ-^V!J%!54ozXf;mU^$d}m?z_a@HEd`2pKQ4k(QI*
z<^{AU-EaPY0vQL)2QES6pt+2K<v!-^l&A4Ehqa^6&-?<#d;QJtPy+6d*?JK=1I*7-
zP$ke@?FMF$*>E0!!{$x(P#tVO8i3!x5n`T4VdEp_zjHB|Q1fYe8-|&KDTH^_{3E5e
z!p%%qh(?%m-va)anR5v4N179(pgYQZOA3)_^AZ=3<K`oD&?3hCb{8aL%|D(*E6#jV
z2A%Qd*XaQ`VQv`)F2Str12fTKj-yxQNpsjXC`~dy<p4Qle*Y0LPn$jbLC%<kXK)eE
znm?qhYqGgxCM>0xT~WO-E6u!=Ugqb`k5Y+Qx>@WEyBX%fA^<YYPU8S%nVVN)EZJr`
zUHlw#;g4WmFc;9aCfDp(84konvpN{w<e3B4qm^$?8h}iJc>}FxFPR?}LbTBQ-7(;c
z%ztix?qYMk2U;cOF*$Ih=7$urC^I{4#cy!gT$2WJ#T-HL%d6%sN+>HgcfSEG6=orQ
zy|2=oYyqh<&vaaY!D@48EIO~5=S_oq-JC$h4>jf?s_wdBR^EoeT6523^wpW4rU|{?
zyz&e#;!X437l3OpuQ`rZqj@WN(PVz96QtR!RKmj+^THPN-7<en-vGUBZjXXbt>)*{
z(Aj1V_NMpW9rNxi$h4bpeh(9O&Hmx&yk{2v_pUPko&u3hb4NZz?wg&1pr*?_T!dD)
zIWruVdd$my!o}}3o15WppZU`#@r(4Ech|xEfO&W^T7%|9TEz~TgCBwFVe@7>Me)E~
zJxbqu7%@+aF{V*--HVVJGdHzCX59P&eev$0dFLd|Pnc)4fJ~a-{u(Bx%=O-ooHozw
zg)=S|PBOgMW!WTwPrEJU4)pD@^ikM$ujMOR#kyI3%!i1(Mg1{|hs9kBe?2WhCn)~n
zWmzSHi{6$Qi@-f-IeZ9sAIoN%E`2QwI^=W6a#ISQ0xU1ChtfdH{6;W?ETh{&4qH}~
zff;O3@j*f?5wBt_M=U?k>8Vi5`nN&CEPqZz@~FkKA0pwFvcEBwNDGVd{f;Qh@*v1W
zTkKTadECNGK`X`*m<DHJEzepYbHd_68>s}#!jGUP(Q<z+`c7FMn*#H+g?$&TGnNH=
zp*zJ=IRSX8rFlJ+owHajKqSqgj>C02Z>eemGu`t0W01_S%%KE8=DU_(s4gqZ;zePN
zY|FJ1=*+RW(@B;KmgAIk%Cm?lh?Q^24C;2B`Ld%U3Ky}=QbU{Q%a(1yFmc7QZVZxF
zEsGn0E4QqoNKb|38qF}3mV95dsw}%{Q&??r*^Ucz&7!h^dEN2}MQUzX)~oR|)mkdv
zg-D&Hk6vT-mZ&Gux@qyC08xX*O1YFq%WDogpVDOUQ~}X!IsFaB+hPf!a968k^G29&
zv()usEO#uka^PXRWhLEgcP&rSS-E=_hXNv<mM33D-+jwGx~sb^ZJRKpZp*W@qUf;{
zQR!2!<#;4q>$6;<6CM4Q=Z>Q_U|IUH1EPbLMNRN#$TH&$TEmu*e<Ab05=1ef5sT;z
zv_>tzQ>n_h#Y`LIhn91+cbKsBQrXU=rGbu+O<A^n1m?75g36R!tbJd=r(ITes?*zT
z{q-Nf_gMc31lem9iQ)Y|>x!k6F?Y494+8IIb*62CyS0UquU^)Rw_x7eI+qH#_FIMj
zg`}*7w0`up{t^khe%5oe`S!O?(Y$=fI+}-8fHnVbv<_RBJ^_(n>xw_o3bB?^km88-
z>nXSvYQ26MePPy9tLeP_QR_V~$b?(ZTVOZBdYCFtj#*_?wHIl%H3ArAUCRN9wobo}
z!5p{N(-twt8Z#H#Vy$a3(HCdkkcYl_Yc8FaNVFDFj{Br_{smm;Bx}JwkW<!gc0lK8
zYw2qsXROC(z>p)w`a4CKQmwn2q2`=5fsPEMTl49SmtmDW0+MO{_GK8%vPM$fTefwX
z3MO)_@eU}xVBJMuOUt!3QG(^7bx9?>$g|eQqc7k3ODb9g)+~xKUa~q<9<9)tMDuEq
zHS9_B6+5i<ci={eRe2KlQtNWcla^T(&%y3xEB=E9kAw9r)c{_#ex(DV-1_3X&{koc
z>VssZ)t9zDRaOUOi>j^J6h5u7=F+PBhV}iK=&QB9PZ78}>wzFJ>#g?!AbHdJQ35P9
zSRKjqMZ-pGGKH3!tSj~a(QJK@E_aJ{j81#qvUbyCaNF9`3Sg_%|2}+bv;Le2ZFj6+
z(X`QS_4^i*cdecsXx+2cR-)Bm?Q6%#I;|TIg50;dOk&twR>2d1cUvnW(CV?W9oZ1=
zwdO5_H+@zoN)ruOH!eWupf!o=P=>62V&I3ZVk$m=V7*Rz(h=(eD)Jw-$~OQoW(}uj
z?4fn%9*_y^7Eiz@t=g9Xn6my$nU!hl&vRhN#nwwn=3Tb)tAN{Mi}j^9)?V9;LUiu4
zefTASuD0hB;f$N@03~=lZ4XYN<z+LwL(<!}iWYbKZSPVR@qmrH6Bps2?Zqb`>0^80
zF-ZE_V(I*lpRI=i;{LX46uUlT^Pz902H4cOkPNg99E4<$?QA0bL(pNHc{v6XZ0o0E
zaUnMIH4OWRE%kFCLTwQ>@HEWU#KbRh)b>R!NVx6%8Q>#qe+I#)W44#fP#S6DEC)Qw
zHbt?OXxl~#ogcTY>w||eHuFVjiM81;fW+B)<^mUQySbVomM3hVSHZ=Tw!bJ%n`9db
zf$meb>kH93ZJTi(tuwZ)_aJiCwj&H<O115zTlbtTVF;}>+qo;~J8xtE3G?Z;y;KpH
zVe|Kb`Apj=?O?KO4O_v?wh0EIEXSrL3m0sQZD2ZbZD%h-Tb}JzDiF%I&7lZyfo*Rd
zJiTOVJO*Z=&3p)=MYbQ(K#Fb5&A139w!Sw&%4}U!i+9-;*Z|2ZHv0xJui7^0057+_
zON+w_TOf_4(ssE7%qrXXmk_D8-KNmYHHXd9j^=gS<~WR^##Y#eQQWXS{|Q>Pw)g6A
zE$eJb3jfsG&QYz`P1|Z0v>I&w*Pyh~#;50~$>v4nYt6P3lNff3?SB**zGahBP26pp
zrw3eXwZ%~}XuIuon#k|kVh;dt&*qr=1ll@nC)c8R--h@w9uiyeZkX@3weE)Q9@{wm
zYQ44|84UK>D%zmC-zK30JOegwHbe$(LOKOFWOF?Wkzreh3$#42eZ3eX8@0`y4d$3l
zejOKf+_v{|NItZ=(Mo2*CUh`>pR$cSfVOGd@ANyl*ng!3?=HJZ1lM-k+i8B?Yq#_P
zzt65rhKQ@ZnRd-?_8)1L<8I$VJ6jL?>Lf^d+Jg_H<z+9Xu#vZY8{Mn>?N{gm9k8ou
zN;+uYNQn*~doPC~p1$_?>528TPk#*=e>;Ps)rahd=+Ibz{lsyQK)Z>S8zJ@@`i{vF
zdo|Vfh1%Ow;C7h(xlo84wGaLbc(^^f3GfJe0)5BlnEiMn`XcQnXBdpKFDb*2j@$Kg
zU&PpV9j1t7ti7ZWUc}jd=0G&w9z~nr6ZWJMs7bJE%Q3=4`@RpL?WFyeXMs<$@6Cky
z)AmTJFFIq_W`dlxKS%qpWPAU5NT%4OTc9k}zC8nd=j<hPjwa2{xQrJ5S;rGv((QX!
z&cO4RVgH5-s<Q11sazq)evR(A3-(v3LN(WZgLWbp?Y?IL%(MSMJH>o^`(MBp*az>y
z#3lP)4giIAcRuVE*~^@95sK~aeTP<w{e3!-Rce2p4M3T_ld9h?+qcou>5Bc=L9`rK
z?aOHgRBr!-RtOdLGqicGv=7jRrpmtUHt^MUm%ku-%|5jiy06<`*auQ$-%cBY8}<rX
zAk^B|`az`5ZXSiDdVBRxaP+4AulJ#|!QS~av^3hI>CSDj9|%F;E&Gl=&~n>hAEJ0*
zt9?x`NSi%+0qowfzi!5O+wC_F;X2>7|Nb3B@7cHK0pDT&aycYB?E<W~XWh5ILAOVj
zeZ^*wZoBNiHJ81CvJt&@Zz?nDv;RXCrv3Kd7eEH=CEvlBLHi{N@(tM?US|LtwqNal
z(g*epZ@}P){Ye_ksQu?hz#OwXi(!7;e!3k>AKJTU^E_b>Y=Fq5-Aeg`Df=m^kDs=`
zI2XEIoG0m(zRUT<3jpkPUW#dU)*k0nEtq?qC7(fZpYv}NF>!TX>Y$*ihx1%6L_M9k
z^jh+Ao}~oS+j$wCg4*vKL-*_f=gL};gU)sHFeV>oRT13xb^e=Pn10T+$I$Y3HZH&j
z4>>QUa`gb`$6tXnfzJQTgNH%RC%?tzI_&%z56ocaC%r&IoJZfI_2&`i4_yAw(szJG
zbv<wA-n$Fzvaqmw@7-ORv80*ApNX1gqKPfWB(}s7jmB7`Mib+%N@84k2L(k@KtYNk
zAXPxRN>!027DVZaAgB}(v3&33|2>b7<D4_|&YZKioHH}$3eYfpjSon;K4dN$kLqLE
z!5z~#QX(uu-%T6UNd4^XaP+u-VI8<AeaJybM(eGTU?N7pMF}oe|0#KKLf^6s<fMKb
zJ+tHVyF-AIs4v|O?zFyf4^Wcy&Eq-Tf64mXOAt-bdwhZsrs`MK0WD46ObeTI{R;^!
zozXA44=z(b(FrE9^j-Hb!n69(zd<is?@f1Hj(*ltVCU-JrYC8h{*Re3n6KYP1`G7L
zv;->D@24otIsK8@P(QE#94{B6^n!jW#m<ZL`&Oc}R6px66wCC7e}psT`iNz)ds+Vh
z-76J(nI9}&(Z8aryIQ}Y6qaiA-+v2*T77OHP_F6Uqp;p}eJ+{5p}!jgg`4`>%^>yq
zE7yT}OTYLfL>l!wXTYAZNk5tjqMG$tbs#PJ=?J4rTlE$6i?r$Aqs4!_K8KckclAkB
z#&S<D-2>90w-^bZ?(4HDhuW!EBmF4t(#vu&vk&x79z&#CA9od`NB?agEIrh(Tnx-d
z`fYRs?6E$UDw%qXdc}3HefsY{gr$DH+ajP1=)a~d@e{o}o#`FaPowSfQ+>$mAVd0V
zJbsa9`Y<Ys9M*q81q#pg4r5{Bh5nCQXnd)UqkY&bed023PKFT51~?n06o7Lv{P7lu
zt6>IJDY+SpTQZ>UX*d!BgI<Qt6)^8@IP?qb`WOZ%;o)mgO#zypVTA>VzhNcKMS#J4
z7~EdN=L*=}XUI&4dZ6LWZ=n}t7)7zd{RUrpDIPFf+z-rPgAc7b4jR_3K;I$5J5)9o
zVz_9eRsUhb3EFTTF<hchbf{s=PRN8A+9-4$Zb+|0-%&%;k08ekQ}@GegrTh+B9VqC
z?SMIM=r4zfD8r4#AkhX#IZ$E@quk(3tYKt5264jR@d4CN8Dh7=i+IEN(LhNsgevI%
zOEfI;1AE$#CxuLsp@b4}DTW^@nwe?{b^uJ8VMGlElWurF3)6MRu=pPAW*Lr-0Xb{v
z`4-M(8&bQWkYnf)z~vhJHv%)yprN;LzF~_9uE1c%fh#oJrQ5&AaQ6gNtP~qYP$;{^
zu<Jh1N)3P0(!9*z(*lih!?pmRT{Q4iA#lmyU<+q18xECY6cvU$j!>vHtfLbtRR)3d
zsttcFgQGPDc?BA44PF#vs587y)$-R21)cEzx*^96U^fhVaU~d~Hw_&WvZyySnnUB3
zVfjXg-ZoUyX6KH<fi{kf2E|9<nhbmCu4*=n{1TR049_FsMXTZO8u-+1_=+kR?;0*p
z3hADqxfzWehHYP95cdsOYvCR-T(yQmm*Lk+*c&p8dIMm_7lvn#Fzc@jll2gF*`a<D
z*zP;_JcfqXj<!G1=euJzJ-Y*TyuAS;5j&EbF(vUke(wTW@{UUsi%Q=SejOrNI}Xq{
zQgU`k9Wl`S9S3g0`*S<S()*xz$82vjUfNN42q?F9c>RsO`^FvjuEU$Y9qm+DF}&ka
z2b^-<d5HF;o;%Oyp>OZb>MJmKc;_gJ?nUm*Rzp8-=ax8dDLWUK!hFt7&K77zJFVV_
z`LdnorbDD^=h_dz)$J5ELuBu+@Hb!~bl0H>Oi<LWLvsL~vdhTPp|gx#1D-(3-?e@h
zV9IvY-9~5CuKl#5sNeN-07Tk$8D!||*!8v+u07uM?H-tTx~qY<OwV`Cu!g#eV+0kS
z`#44%K%>878a+va9OEBBFWAw8DyTvo9o?ZG?Rb#(VJ98UjapbraIB=yb0s-WCdE`o
zLoh_oI2!1Ali}Fd0gX(@PD<uyIliFqK%V2OLU8$xr&wSYI<BEYj&qKS!q9i#(dsG4
z1xM$t7-*5>0vcJd<F=6?C5{uR1ftB5qtk8Wj`f!GKQv!*TutkY%Z^jNMr(zm(iuKo
zaokB8xJt)By5XxGR}RCA8b|jD=&N<ip*YG_#{xY(yykeCj@n&!Jf0898;)u@$W6yb
zFX38?<2ibpwL3Z?An+QM(O+PW(i*>(u{Z_y>WoY;tsbv4qv%Sz$yn_N;w`4&U1;5A
zR*is6BeO;X*UW5s1HkQ!=j&+fVMgR)K!eO9dM7xsuLeN8*~I}s31U|!QQjJV#EG-u
z+UPG+@b59EzOeL$Gab);GoDtNZ@IZq4CB*c+N^!HU>3S3w@v~2=R5WI`-}Pe&^zVz
zIdExe?(g_9zm)$7xUZJW@b|Qp7MQ!~r>F*e#+oX~%v`V*(6d7Aq5JjU9nhWq?n`KW
z^X+K#&Uw8DTHnUpz`wr>Nyg-SU;Kh1wsXB&!OVMiE;{CSyopgQ*zzStv(V}q{{CUj
zWvKn=OTnc@Cnf=Ou?0PLmZVdy;nMr&(EUm2fR<$^eu2#L2kDUi*?1prt++x(^DA92
z<I-P#_d?4m(@mJ5)fx2kUz3(g&!4qZ$3S6SbO5^7*VA#h4bSP3`&$rYv35UB!Qbvo
zlM;jVV7{Ofx+jxFm!ubSgeq6PnY&kE*N3sr!~lGmH)p{kKW3T)sQ%3KivSE{t|vjS
ziSeg0+K0>=ThaK4d5&=yrO%i#xHhE2%w$@qxwGx#K|I(~Qh<806R76Ki~Y$1oHu)j
zu1p`+?<HV-*))pR`LU){a_Y~nx`W9NW7B986V6HtK~At)yFgB|r@n{5IF_fEz$vzE
zJ;37GB0An+Okl@op_s__Wdr*(JBA_!N$gDe%2_h&+Y0Oy)`pfisjLsBl+)M)uYpTv
zH@^)ogB_rdQzkncjK(asa5TWqaN{XbmchAF=}acqOsD3uxK<eqp5-k2(1`#2lFIgT
z)^a?hXmh#Al)%a3{@n?fe9o;JLo46{b^)f4^PqyKb6go!VxQ+~-^Z9Pa6NRIq=@@)
zDM&FF6$$JTE_OUbO1bYdfL+Gz*#)kglOOsr9Nz}GOv%^^Zrm^|T;b|zPf^M7C2*~Z
z+eL*m)m-KpK-X}?5$LPs`f0~|mFr6ebRBn(Dypt=9ki9Y&biP5wHsXZ2+YAvPNei}
zJvWsCzqhyzM<Ln3oztN4Huv%eSh&M^8|jW~<gSf^`6jOZ7%Vk&y>!*Ja0f2IL@T$*
z0i=z~q^i1h?(=?lahI!a0e6r4#|j2JIMr{^yU(qryR?&I{Gr~(Y3SAUfNM9PubcCn
z4ZR+27iBXaa>Z1L@`&r$O|?OfxrZNP5_-7_RG8eyxo$;cKlhCOvyTC;nF^Jja3j7#
z-yoNn2D?u=%hSLf;?6SQo^gSfL58`;H-X|L33S3(oFzZeDl=J9DuPRqTr~hQRWj{7
zP|_sJra~cIQZqo2t}~LoZSXro;`|D&nUd9|u$v{BNB3u?M3)c!DoJiX6ssjWYam%8
znNNq%8YF{nV`#S}wRMnemn^G>Pj@B36QFQk^6wg&3yE?X^gN~GsOZW|y8Z-w@|MoG
zg`<8_%{IEz{iO>6(HbCK><Rt7(vuV5=`rb+U!ZXo|64jpwlwPjNRE`JA3ayf(^-~0
z=_so6$d~@3hlv7dusOUalpeVZyXT~zkiQqChR@+)k<`o|jm1(aEecBT4M3=uN~?O%
zXDpL$VnEBKD*A}eMQI2H=<k>upkX(f)NTN2GTB}L(roh2`_OMOsiwD0tH~mo?lu#}
z3n;XkjF?TomdTrRVC0F(5*7Mhnfy*WDksy4^-y;<{kIWbxR}0Adt6`B@!c2_a&sAn
z(duuSH5pz6m|moH+CEe9V+<zHbfyF($n?F7AO}n<>3;|eHZ7wU@IlkDg8)5b>O)nJ
zp{C1SK*CIo^#4tSn?5>@z9`e-S~RAcF24zK#&nu1NQP-86)0w!x);;@ni_9XU1pAH
z&JXC!HBJ5ozU7(LehI(xO(k?>slYVA4qU0}Vp@EanSMyOL%C`05hz?VeTzOnb;-1%
z4=5F;4fGRUF?FE&{_Cb~I=FqqbS|x9Z<>DA4ZHQG9uzBWFtwuU(A%cp8fhVX$MoO|
zz%-hA#sRz8bnXlI)?)fuG8)@V`=$b>-Sid3)b5#b1yJZPeg8T{I!#Z|690keB}z_q
zo7z(`V2|lzI(z40_SYJCA7bW0he-~bt!hQ%5i>RwT&UUS6blbCTNg~#7vW~l;{bEi
z>?&nLkD1LJglL4BXoO6Znehfdqs^*qFv1wK%@ll(HCsg?g_C9nT|nZ@CVUN)Q)cWl
zaPem1Vn`;KefTp_&X{fd2wr5E&HEkDS!UDgFo?5eZ=C~Xw%M*wy8m*_v=mLwGfSd3
zZob*`Q|K%(^QIksp&3Wd)pKT>|3>2lGk?mx6`2iC4y@R0iXYHQ%!X&9ugvT@J;Tb)
zj#`6UG|O3tzRPBdsbsXm?2UPF?TXn4JHXvH+eYV2I?cYhMzui?%zi$J(RZ8OrHFBl
znHi;KADZ>KL;tbadAikl&Gz1gV!zpQT8a&rZKIIUOS6zdxc$mZat-QEGD{JX&a&wR
zaK=R@p<tz}teuXKyUBhCg-`CXQhMlm$Yxuh(NlJI8T5=^vY)8ZZ=dX}3uFRiF|UE!
zFEf7znFF%;KS2)4>b#+NNTyv5&?MOeKUhkZ9i~@Ys;reZ<7u*<RX|IZ_3j0CMz*>G
zBtv$B-rAY6WmGSbCDROHe$UFDP?cD=EN~F&IYwCkty^+s%}pSAvRXRtnJ<&f0#_h2
zZi9ZIY?!`7b58cpdvNBwOrB3ag={Tt9gAf1sEVOjw)O{Lm&iUoioR0Wc?!;!$!aM0
zS1#+{1<8xDv2;CNk}a4Ia#?nT^8Z(4#<$xcQz_e`#IUPm(^BARwQMYveAmeG3=plA
zy-n3IS7nA#kgStg+(F|t*@pWdH)Ox<faFb?=>m9IFLTg>yCtilvWW&+eFFTwE&FN`
z%-@lXq|;c9GH(hdH_1G&L!?>OW2EhHi|loOw6@Cj+QN%AS>P&=cG>A(7`!VR3Wvx&
z*<o7ob;wF-1$19#pxTB&xupyuLGtlapnw2k7eGVhQ(s|dVe(2kq#G`em!t2P{P;{r
zM#w$so8ZUgvCl!G<exfFrYBmS|2jZp<j41+^@M!JM!=ku`;Nu1<K#QGft-?`+6d4D
z`Mz=JJ1vi(+Mp!)d^$RtEx$+wLpkz^v*A;oe2A{6eEG-Dz$}qJpyHfL`50O`RmmsO
z4!v6LQ;Nx}k<S}V-v+3a7kv!HtMaLZK&zAU=@{=d`QT;9T$jIyhus_UX*U4VB6sKm
zX_Zf;6<?dYb}6`axjPNwuKX;$5AMk?Q9!dp9?%50@5_%ohofEc{!M6nAYVeo&fW57
z6iw=ppAV%>&qMjGYREj2Ukrx9$MW5DSfN*bX%Vpd<R6s*8}G8?z#fp>&^vulp7kzZ
zp31*H2G@q<(`o(pOx{K@%VD|mCXnay(G(teAzwo!qc7#JoWQ-3zfUKKoXn34aLw6#
z*CY_5i+LyQGhEHZKf$`02P$CD-F#muCd$KnKP}lj&9igizK{7%`eA*|Z%jd>pZQW+
z*aVm-yMo(mepCh5_L*yw(HLl+o(oGs=G*%Lz2AJx3UCL^=XyXr+&q}#3`fnkQ;7GN
z(Y!PjG{U@m4?2&V-x~rKWxj@f`)Kokwcwh~nP+f+(7cptMV%C%Z-At;A}AULT@?Eh
z$$P~mx}e+?8F%2QyP|L<^t=_7wEgl?)NO!=zKW4lMDM4#ya@^cibE7^*{d)fp`>h}
zB8|@f2Pt+$LFS<1Z#utqNO5o}`a%>w|G@pj3QKxyg)08o0_-rwmm9!^D@Ie;?x-St
zArvAM7bwpasrdda=p9$MOaW$;BAW7$F^WZBLLpYMGZZ2x6yGm^zb6%^jWa=06%zWu
zNt$A5CCsNQ{+<WF&nW()ms^G+h^kaF701>?GE4E543gQ3b`2VH6h|mKn6G$!4)h8Y
zxm(b9PO*P8>{csGserpi@yYuzSgUZ}hQ6zcu)E;u6b`-syQcVK8NL6mD-P3Rr%6#l
zi|}T}5)LL>6oZE#+N$`*1~Bc4o^2TDeMRGakWR$_?I61pRz)!XKyfh|A`cZxijX~0
z9HxTI$BLS_@H6!)8sEfNo+z?^0~u7TrNF{d#oUj9GNc%FiE8tnDaKd9(y(HM23|Z@
zSW(UB3&n1_W&ABV4Ilv)fA&Iuuf<gcp!+N;e?nuRMcOb(kj0Zy=<T;iz76vSEdHRo
zBG_WI8k2C)B6}(ZddMQ780sMw)9ETXY+)~h$PtU7vvmK3THO5(qG1-^KJe|RMSV9!
zk69#hAQ2X|4Iq&grgUihxP?bCB%>@2G-HI(7Pp5$Vl76{;ffO$j&zTlwAix`C~+1y
z>9B0Pg?bGJnqZN+1dWLns{>*Fw8d-m$-pFwxt;(sCR>dA1Z;|hJC)|9TD<oy6w@qz
zeFeMe7N1d}Z-&KdXF<Fyx7LDqTlW0|Ngqp7s^ki?YzczhBbKVk7*nXF3sne)S*mFV
z6K?ta94H*Kd>#WwBP^#-8Z^@KVjC<Rw-hN!5oNTTbr$BMEiK;wNwjoogQsUKH+X_%
zSo%dlBh!)-A(~~GG6OJ|EYDF~^RngZv|_BVyg-qII?Hf+H(s+e(uYm1TaKkb$qma^
zT6*2IOnD0;2<qfP<d)^gvuJFv{A>W2w=Iq1-hqibmi?{x@fs~#7s87sOAl{|He3F>
z8t%7P-uerq&2kdO;@U0OQLg{4<uCPsxo5eP!rmR0f2TpA*V3T?D1DZl&(POzIg5_&
z4Ore1(D%ghlOMnhT5cVQK|Hl=quX%Ea==IdsArY~^hJkZ%e?t$eQv3t7{d$8x1HeH
zOUsdT%{eI>MnKV78RY>H7iH>1*mYGpQDLK-@;1G%-IYCb;=@DvMj$v(<q!Ul^im2`
z`s}UrdI$v{<)S@k^i@t>f%)}QuCFoz+h18pwTJ=AK%_pTdzBwkx$!>bWt!4J<^Rku
z>>%aM6KLG8+?|GL3s!FVZ(XEZ<q45P$_G@?6{2i@1aerJ_YNA5C}-04CRAxBz+jk?
zwTHoQ<!>x3994cx`LPJ)?jFjtMk-JL1&!m%Op3)sDbp^ZGg|5Q8x&)df6RnptnyYf
z$O)x}j_JfH8|Vr?rL>p?k$B~?g_wi{WfCPv5|v+^1j=dU2L?1IDd+qMFOrq6F~Cew
zPRf8tsxpK&xM@mrY^RLUbfrrd#+0Fa-xQ#k%H4G4AxnA56Z&VB^YfsQt^8&(%;zWv
zUBTrlAJNk`Pq~On>PwW{o&c>>`HG6t%ajqdn5S~(P0G&KD7}tCq*fWxiveC$9^H(_
zI%Quuz^*CxQ<~a%UD;d*7jGzQ>A`wa*;o#Zdgb6bpxsjLrV^tD<u|m&yseBpg~mHd
zKZ-0hDvN!9)})+Ili#e2UkZ^{<<Gm&*ru$cWKg?uoi(8ED&vnq;hr+)U5Ioj&FJNF
zUnviTWT#QNg2GN+$^~?pJW$SB0JLu9ub-o_M|qjPee_T{AsQNwlwB=wrcZfqCeZqo
zHI?WaP<GNY;fZqj9gsog7JrC5RnDgs<B)RYK@9YnGB+Oz&Q_ngqtV6c8l5L{wF*9g
z*><xs>ULvH9#&qo`0%t!?gHm!<@hxWdRv9kvcbn{B4w6+t!k2>=x1g1IU4<~7EonX
zfYsl{u)EhPCIFW9Sw)=z3AEb01eQ)(=g{X8PFe3&0W-mRJJqwCw%#}i&LmsgABKfg
z>oTJZqUqLQwByUL)=Yq<Z0p_cK=hjR<6F>gv6fJ!daL#2GH`9yZ*K(GZr!vU`gg5Y
zPJ+RE)>6t&Jhom;^`O1hrt={A#QNV!AWyBmDBn9|jok(2!uq8a6Etl7+Yr2XZvBTX
zWpiFwzmbX7m)1|Hrs<XSp){a5spiu4?5ye{gD$EBs;O{Q>6SymPi376Y=2eH0>Ff-
zCQxuQOtt11#&T4(ho0caR5esYAEEklKDbEL!>N#rQVH{D5>&snLLo`@FoDj7oK;=T
zg86LKW;(2tqiUW7nPOE?8|;>-o*ba7Teb5w^p&Z)oS;~)YWN1^qH04L^e(A>r5xpD
zmCar>R;Wt7;Mx_{t-nDkRi8>RB~_{dTJTn@qP_&VrSd{iy0k&H2_Yq;^tQ_QFD%_r
zB}GG{QPq9~T$5@g9m;A}*|>tVsJ_*Jw5r~E1;sX%LIti}^;<8vyQ)MFcz91W{$r?j
zsQTq-ysvtLgKM3t?T;bZrONvjb|0t=KR~2gwTh|&dQ?4BAz^%|Dts5Mk5rCFq4-#J
zk}`q4s*vXxQ=iJR7hJz;(mKEls1DKF^oc5Q2Rs~9<@G}3scQE<^bM(!??CdI%HcS;
zVO1$bzMrf9prqRiRe%%ypz385X?Iq4(%Bssb+I`_T#f3lCxN=DU9UqXSiS!yun($N
zZ3K3R`u#aTJFFIVLNQF8Iua8ct~Q|;=25kl-onS!uOEZ=5o$>TxJY#;HbK(k>eGev
zYpd;SU_M&?eJZ#Z^>;HcPqFGdpF#bE`rSmBJ*hTs>PBmvdXScrr_^H`!Nse~m9Uhc
zZhr&LB&rLeVB)m;5EZE=sh?IuGFiQl!d)rq2O?ln)f)tOpQhg64lZ4N)fp&f)H#bW
z&<yot+V*Cu%_ajSOa1sPB+sh5DK3|-ZZ>9s%~Aip2yCwUZz_h$Q~!5hGGDzQ3>pRM
z&Ak9ER8L!nzH{m^^uj!^j-$}|1@&MN)Qi;P=>1i!9!1AxO4N-M`YToMn+x?a^}Do!
zDpzMx;_{+;NQ#kNQrpCWyR5F~jOeUTm)?cO6?F@h#Z{^&Q);+M{UN>Fs@3a8K(t2v
z%LPc*syEV|dR6WH1m^41Ka<^S>MA<OeqDXg5-2y+&Q!R1Q@zdzQm>Y!VJ>c|U!`M!
z4QgkK4Bu9drDGU()F0<ir9-3oOg%=}q|T%bO|v@kU4XWz$I#J~R`oj+*=kcaeF4|n
z)qRu@zpHklLooN$<7o%gq5i8G3is6~p2A?Kx+e=FU1}u-kshf3JO@X+)pfM#?@{0H
zz>prQM-IZ7N9u$h=>B`GR%W8JS6xckx;}NI7F@sD?FX0`P`A>u{fRow4bBXzOPc`t
zRQ>x6SQ=8#3jukiUS9|=hSl@jA^BYW^%AJRQ2$W{$(QQb1dR8U+9w_APW+UwL7e#?
z=A+St-$Zp`Mpu3!r6}C^Bsv%5&cELRhdp>r1UOILjEX<Jcz-%g;>|B>fKNVr7;OxE
zdFu)gKVImDC4XM7z|aEt49Xhs<>wto-#-4+Yp@i^H|9Vjh~E_i5BKvPD)@VVfAcB0
zU?cCm6($bybIPG{h`&Oy$`GE91Ubx`Mg#N+UmFhnP`=I{8e#lON*0Clk29cml;4#M
zkz@R^C9o91pKHQcBKgLpAjkRL?r<iGcejD}(YzVOF=F`75`hxS|FZ>pCwSurbSUH`
zzbpo5ar|<shdad={REkKKDh!Ufe)pbP2|Uqg%_v!wod_?#0zvGC-cuJ$e+Sj(Wg*S
z`Fwh=r}6Q#Fv4_x=YO{$Ka0Yk8T{81fs)Curw>77@geVkoaJ4OfiR!VPpAEI4*yXE
z%;)mKKH&2Btt+9C&;Ro$xB_0Y6Qqzg-35hn{K5^8JkO7qg?YNbFZvZjE8?R}FzjN!
znCe4H_%g~9mhxjMA792#oB&eJAN2#d$S<d)+$CO@X~bM!=Bp?ZS;5CrjrkSc(jPFD
zd`t#LQN>Ts0$0s<zK&7U@K=5XXf40w8@P6rZ?b@T9Y0-w7uWcuo*>tG(=veF;5}SG
zZt@5~;Wp$urlIc^|CJdq8+a`(ZEy2Sv*~l%cX(kxS{wP_C=A-f2aG^xGynMla4q~%
z`glSsZ*~g$ZM@l3IMdD_rB(l3zJdau_jr>?xYog6yoA2{eAFk<>*Q-*ps|ZLe+sY%
zJZFX<rkgjR|6HPnzuXV<kS{@~-za^=F9^n^_n5ERh@tiJuTcQAkMAYLe%_kSfDiD8
z?}9wxhj(Iv2KgD|q41Pf(0*!&uL%Qr#?Pf^!Z2?(1Cr1ARllL}1%GZl+<wXb5DxN+
zx2}PnlVDH+#aVc!fjy&(Fnk@Yu7deR`0XZqwhg|y3#F73@erzW(dQ}bpjEV&aG?j-
z-a-al);_|Y0`z@_7)uP>Pbi>(g1<008z=$7Un-d2E9_{7!am_&Uo-{^kygMA5>8Bj
z!hYe-8HgM(3P&ld5iDG+gUmspiK5nrgqboJ3=tNdgr&p6RSG#C5quk9B2@T?cHLpZ
zvM}_83pXe@k|<cv2M10IS_-@*32)H4C|MXmapDv~`3#Mz!XCOu(uDEf!*04TmDY%7
z1fyXxKr;k}!ate9)e88QC7d)u=BzO96zpaTcd6(kM=);zXs!@Vxz{}5)G!qCg*6mi
zED)Z&2}^~7=m~{$!t(cld0u!Y4<Z+Y(gbitLe?#C#ex&n)RqX%QSi4^IBT4VQIrW!
zDS=lmyhEkI7lq+*FmXu;ehnIzg{MnFDum~M0p^OZfo_0G;S}8?Rl+V4C{zn!j&Q9;
zSR9YWTH)ktP`@f92EbCC;PVZ*Yr>K;NM0ArUPt2%!F(GOZVI2J)BCSpNG(C@Eg`lD
z!)_2J3lP06<V}I4J3^E#L>q-X%BVI8m+5Y97QP9CPc1?)T^_B%+dJS|n=q2D&URth
zJc!&CK3@&)o-nf&BkK?ztpnJ7VKY66JB1Y#vgi`tu%eSD4}|NZV6a=bEJtULz*6b<
zLm{#P<dM+z9>(-oFbjoiy~2Eoo%aa~=yNCi!V4PjfDnEa+!JBrFAy0NL@M}uDvX#2
z^FzY3F~EE#NT^7ASg@nK#dBfC2M~E7oT;FbCNG7ZU%=8U;c^T{;Uq3yhoL!(uUCU}
z5m{PQx{6sIu;eCM(AOH=#iV3#9^!X&!+MHSXz%YOW>TrDx44Irf<EF$0@QuQ7v+HV
z6JzND_7|&HLnJ^PL$CY2B1dM8`^0^jKnoNb=%{~?_yzqk`^7>^?H>>iD$y7$ei#a$
z4vJFR!W<GUMt}<u<2FO&u=wOF4CaWK@-0RmDtbA<!!U6TJz>JdV|g%mRGjq>M2?9$
zKSCrzOr_{Vr07ER)W?mYUkV(K5~uHj7t!M9v=56BZ;peBSn*AYah?!^UC?(@wAcXs
zIC1nxuzO0B;pmh!UNkL)WP;cq2gyXSEEQm<MLSwUB#C9iFp(^tqf}~&_-H1aNfrNC
z0EIO1{gDt!7mai2emEn>et^~tafq(DOmTM`8neXsTTnbJetZC;+2SG!-RFo6v@ppP
ze`|pGJkg%cyX1=tYoJgdHq(B$P#ixOedolj??e5(c$7Y=bwM<X0aqkid<e;6@qaor
zmWa2E-vhK%%-e^dm5FatAxpWq<t$(>iVrA7a!Gu64}F)#+}FWXhz^wUz9P<i4?b0j
zt}T$P67A_>UoEaz0IWvr`4;AD#U<-Nu8P0v(O4(ePlKb^L?x{+u8Y;yK)E3X|3mw~
zo8tXQOjN!24Q&Z-i6bUMv_UKnfc|YUkY@IdxOy5)G>QclP;3%g--J)i;^HS5MT=O-
zg0zaK4q<3*VrV~5+Qlx~2Hq8~M4|7VxRVm^9ilfqrSFS{VIZC276pA9r%ROgL*{|F
zn6?t#qJ1^Y_lQPX5<C>+pMiTMeoiotMVA!-?G;bZ8l+G3p$&Gw*s~tk1L7-MSv(QH
zy$H7l#YLUqo{Ga^;D*F#s*rys>Q+H-SbR1SD9^=rzoh)%3-JUM6TB3kpTR(1iM6XC
z<D^N~!bN9I8fEicG>_>hxT~h~Ir`i*3%-R<2Q-<qUk%pOQPuH5je#n-4`~W17aF4Z
zeGU2!YbH?jL8!(l3<_bIh75>=YtBta-%-t?4`9}KOf$6`E=FjYoxnzF%07X{am{5a
z>50;0JHzj2jUR!=Xp$%j8><<hjqV9e-{&AFHRdrOahmU_`2UpV0WD18H81V(GbL!Y
zF;Gv`Or>w$p4K?Kp)pyLvIz<)nu-5{q#8BL7-*zv6m)r|YZkr)IitBo0ox4C&@g<;
z)a-s2^OdD(_!#ETY7!~_lCA0e6pcBW$Fz0H)l^RhN}gtdJNoi99W&5ZpuuV#w}WN}
z?d{HK!sU4Xo!5j=;{}ax1S}M3jITz*M6sqaAMTfEzNXXHrJ4cSvXyDZ2LPsABd1{O
zMU7=YexFO4u~R@UYn~neXoY6nT$sP2ai`F1rN*1Krd67uQy|qE)de)xXzb`3uhm$z
zK=P_)RXj+Y=Au8$UenYY2Vmm5hNWWB8=A!wW4WnGrJZ@b=G1eLTbg;46l~B${{)|I
zYt~V*^&QP{6hIp_opb=BNpmR+pv{_XbKp~pX6AB`R?Ry*FqSq=)*(34t_i0jsCP95
z-B7rv`Sv0jJ2b&tDgSU^lXwAWotpWhV5v)U>`yd4&^%iW(ygiL2U?HjIX#dcYIqyy
zKhgw_1bM8f2!w~dn!jjs*Qaq`41@g|Q(sKbfW|5ZU{5svEP&*o=DRoH;Zsd6og^62
zT#JC@GmRvO-hacIv2Q`<xn|5qKzpJ2V-G}MYLxUoc%{jB0J~1w50l}cv-Zbn;9RtC
z(4y2;d;e{4ZrV($MReDiHUiW`J7*4@@zj1EghnrIAysgAYd7ozrjIs54oqKdJEg_^
zwAStPZ2*7mSCsY)(5|4D`Cje#Z1}xT+ejx|0<{|{4jH7K<_MAf+BYe5e?VK31?*t$
z7gTw2P<xj=JfwZE4<tnUgvzTAYiCb_`VsAdI?Q3H_WW3&glTtt1QM>z{}5nDwFd>*
zGal0#2B8t5okj<qBegbf0p_@N^-U;7X=9tfMQh6_BNU^3@+(NJwsktNPiWs+1MZ~O
zlpZE=+Gl$JdP@6YBEaIc85F!q(8kbvC{Zil4S!E-OXN^U(w_bf(8=1~KOvH0)JBcK
z%%*B<s01`k8?gtS>DuM=)H|b%UJ3mSt(OiWnc55&G-heD?}0n39io(Vw)Q%G4IoGR
zH5~`e)lTVvGkIDs4;akXE~hL=fi|)TjfL7TXx7eYtutZhytXv~V8vQv=oPRf+V(jR
zEz=&PkEE4r%T~j;i`oxspm<5!QIDZr)(-y<eHGdzYhdY$ww6|YmD-Jd5UJ8OQRQj1
z){Cz78tq6cG}dYl9R|6oeTQ;Sb=nMiw_VfrQi;rUZT>Ex+|VW%O~KyOF207}qF##+
z%HWRE#?D9MZS5yp(RfGOWC_JaZ5^fBo3w|PfHZ4kt^m758xseZR_)bx45CfDkm|tO
zwE{gD?`mgJ@!dUbw>7v9?VFUWy02}cyi%uD`4!Z=wC3As{rN!KmkH9XHT(|I9&HP)
zsUK<`Y(O4qk2RpNS6fWE<38<CS^)NI!#Fe!Xk9*s-V^O4iq{Tm3m?MYr`nD5!whL7
zXnXQZ`*c6JVQpeA%s<!OZUOf~yKFJ^UTSB)r1#$|?H?*wa?({TN2{~0pH>epy4eiS
zTy-b@LZ6#1s|%dFuAvyenukvIBMf@#_<Bfs>2A;?$y@j9*D&a#i;F{}uWor4=E6_+
z^f(m!bz4V4AwYMj2Yq{WQ~ui)>B=ukaQ_AB7E-lpkS?6o8T)nesc`Xtu4xb?SZDtX
zejn7G83B<)y4RP$M2K#FE4ahD(SZ;-qMJeGWT848RgQ$|RK@T&TvzlBe#xV{>lEBL
zrkg@Lf(V@-MIa(|8Q-JvxbE0AxV<DwH(@^5Xx(k9FO1R6rZL6pPEnok3EihsOvy>z
zxFpz((@p;j+$r5dssf1DS<~h_L6;Q_lBjF4139gWGecjJZr-7vN^p!ncm*6y*Zuer
zz|QER=zMvGuAXXnGIbf5AX&O2mau+Smrv&~vUTaP7)y>WF$XBQx*@8a&C}&j^e11J
zZHGY==x)%l^g>+-t=7-!hH0~ZURP6yX}X|mq^MDmZtO9TVqKvz1Dz#0S3O9nE~^?c
zWxCY|G0t+GZ4&HW)a6IOi%Yu2H(>s<F6$R?6}liVh+NSfErF#<-R)xNRq0$uL!nwH
z9)~kEx>PzBSF0<c$MRL3??@P|(~UJi{hDq*9pt;Nt6EAgz8kuiREB<2H=4?$>viUh
zkh!Is@eNEg=$=zj@V4$IWuEWoX49&$QTN{eAlanzqo1%@$4^FMi|*1ZG`8w?%z~qB
zx<jL2zFjx(3rxaeU10%y>ea1JghHQgBV~g6b-TPMxi+Btb2T)c=$5Vo8Pqj@21`$M
zAJa~6NLNCKx1Z^za?lvo-KE;j=eoDAW4tePm9+nQsq4FdzC@czYDk{8`4pF|G}*>y
z7SvO1Mvg&WnvH8Byhyhha|I(iV`Gwt#tfVN*y0(bSvGHH!tZRGzbROkV{_64GI=%^
z+<}&F^Csmo3vBA`=ohs)Os|u3HoM$_cHZU(Dr31|v#9{2$mTX(xy3f2bD&;oQ$q`j
zG8-`;&Xn7%84Zz3HrwYz@3PHBI`>gwWBC~xjaO`zP<=$D&C8WASY_ik9WzvIlTe4w
z8k-eU08?u-h1RrJZ8lSCvCgLc7PxCRACHCG*KPJvX5@xV+Zi<8v}vNOXT42C5%g}^
zd`%PEVDobT265XaawjD3*ksa*ywRr9fW{`HjrY57s@>*)l+)<230no<?%S-@LbTI{
zxdWIkn+`f9`@m-GHz3_MU()wUdTb7cLE)iI>?%k;w)uA|(0XmM=|F3r&7rv<{Wdxs
z)CX)lb0G4><|G}18noH-1|*-_{N)NmLpDYyDrS3Tqb!3L!!{w~(E8kF;T4#8VN*<{
z5HD>M6uEe16F3tvPPUt<D9zb+-23Qru`LgUx~uKK6ftqL9lH%ax!W$KuM~OMX1D{>
z)Ar>w^m*C(Qf|)Mw&i^c!pC;X4OsBCy<$9pRzKUtlt=To{eqTN0k#Pd(BEr2^ClGc
z*}6IbG|2WO)kE&Lty~9%1Gb_DB-qw%Crli)&FaK&cgS`q2qGc2;%gv>ZSOpSr6abJ
zsc0|MHkJ|{VYVZ;K`-3al!AOmZIu%#igV0%EJYO~Y>&{}JJNP&6cmr!KIsK^w5_Tb
z^A%&OU61j`+A1hjcfyvTSj9=(EDAiHvd!*?UV^Qjo*s#|k9k;1vfV-d31YG>zXu{I
zw%aemZmR9fB7mjYR?wz9-F8wJ6?bLWzC(ecOj{o}bY|IZ)S~mO?G_3wXWRO^0W`<<
z`~C1R*H$|lFnP8q^o!)%o~3)cz&5uFjfJ+?>>+Z_b{=J=&)dGg8DJM|%TGYE$Tsr?
z8jEcc-o_wGY^Tt5QEGep0^NUQwi{_(RBp?SM&~8l3@d0{w)G8#Mun|Z4%e>O?xmn+
zrR^9BQ&-uJ;V}u-w(e9H_{_Gv6qY>g?ll9&+wNxyO8VGU2B7bdT^Q{Pj@V770DQPz
z8%3!j>~2vFY?R%I#gH_fwCk-xYn<JbyAVBP_Z@9y;_b%DU@5`wuTaP&+MS&XFHYP2
zPH)&GJNxxCvvvc8fJw3AY2BJ?XYnH>)9jAXbf??BMMY(2>~?+$%uKsGJ85F=s_B7x
z-j1V9&IP*+su-y>+Er7@SCyUW5k#x)__eTGV`sS*KGoVS(!-gncEPJLv^u;0@gUdi
z-t7R)b-U(t=-;qg{U`Kp+UYL9nR>gDhv076IT(Q1V3$uvUvJwPo&)8MUHB<9Hric%
z4|+{@o7cgoW;^4di|A~zJ55XDHoJqiz;3tuI1gy9_D)jBxY=h+0jRtEIY%gZ*mHDJ
zC(Pdc7wCoChn)j=)ZUL)?Z@m5lsAm9@0^3aNc;Hz61w(>X-6DwzmCqO#@ZjN07{a5
zkPa4-?av#ZV!SE#GevZ!+P}XS`f2t_^pZ)pFS-HljJ@v`c#&ZrPABIJ?9C`|Uugfy
zLG+!oU;ICiOZG)nEPUDCc`-<Z{WeN8Ua^0j66RI*KT&e6#{PHOMAq8xp|ccs>^Gi-
zhmH2%T%!d-ll^!~6*SwAIkfEx&Re`jr3_E(7t$fnLHp@XFf&i>Oa1YS4B5X!59DF{
zSh~8O+k1zj?}a`4F1VNWpZr(K?l6Ob8_o{#ose{KIItXcT^$~H!!<XDhwDJx9d_Tt
za6KH}+5`{19ENC%=Izi}k3JuV3q}vP@9WU~Aw2bS`1l22{2jLc21@}B{VTxjb+|w;
zpg@OfvCt24$f-r&euvRiV|l<qO>6&PhX)MM4m!O4F~ANvoTpG$h(rB$^c`_{jY1Wn
z4o<6~5bof90)0mvUd;zetb^%){}<H>haVhaDb8UET>_^Z9)5z(1c$6i;7&VCrd@B6
zLlM>NCp$DzT}6t+pA>pab@*c>K+_yv(tV%qaG?wyo^hB!WquhBGjc#O9qRuESeC=@
z+b{`d9mZIrF~?y$eZsQH!G0X=H;WzKXoY@>Lk%67FLmJPX<g<pt{#o$4%6vMxajab
zt>Z2`WUK~Eg@ZB$eODaj-$dUvhf_;Ht~;b10(PTA4%KQjIgI@ft~EQv(Wbe@!LAo`
z(dv*uq2M+L^8u*0J4{EBuu*!~;SDe7-*cEv_gII+tPh}n-(kiYG<G`F&jsmnV7sCJ
zz+uI|@M7PHt54~09R9qe@`07N8A_Cn{a-kIb7iz6LEM<91!!|;-2U4HGjl4S=*a}R
zqtA<(bp*QJOc7o(MjXkS;sYDLOw4l0YbK%0d|I}jVe<3fY6fFQ`}<7h#(eme#Z=K%
zbC#JvpLWe=EU7FjhiUSLNG=n14J41Lv4LJbQ~DbmE?_3m1HF*>lX5BNm=8aJ$a&_E
zgWxVOFD|3cSj6~IHvbZH3RkPiJtmW$&u;9pKIpr%A5kr>2Rmp95l^=LI5fOi{S}CK
zvk_EU=fi$QF9ct9a}XN+SmRev@MmpmAsN61>Y=xn9sN3nw2%G37NZYj=fuH_AT|t_
zyvZ>mTT+2xUu7R+XKmuat)_wyFK#;amL`GR%w@nn$W5jELn!A;hq05nWr#5SH~XJH
zxrBdA{*a29zE~d((J9+c!^D^W7Qw=z2~_s7Trb7n8$K(B<PM8}AnB<7?7tr&q#h&m
zH8Q8?0yUF~rmOBe^V>WB|EJ||(W>_)m-Yc{zv4<>hhI*T70EObN%=T{21)|`z(tz2
zCPDSM=?E&qj53Y$175Ug7e&>Yl;!OZxu?8EXGMCHKP*Gvfb!fuNIq9~ET??8tJT!;
zaM#D`mKS6Kt$v;Z>=3I(yTBc@TC)eDu~ze`(&L1c<EQZAq}6>&O~+ZyrHJ<_t5LMT
zjkj991;a|PT6_y&iB>WKJ8d=74<yOTITn+XZq?)h$sDWou^{KI!d3#zSZ?(f1^%k6
zf|f!5rqvcLI_s@eIe@uk71IH(!Rm_%Fn`<X<E<b)R(1;^`OvDr0o)_2vlK;qY&Dv4
z(!ExTl3=jUN}!lVzg5>P*d4H1`Zg4vSf!l;*q~MBPKXRyy-J1oXGSZ96J&<1BA%f2
zxm6hjsb5%qLJQ-UR#9evd1aM35!g=F2^ApD))T10*~Qu<6r87Z!*_u3ver=i&f9v8
zFZ6t@cc@{>*ZLn*aDmppP|-|~_0V4!=YDJ1b^KZftoNRS*<fqqcg;YHww_f?Gi!bB
z2bxmr={KQ~VtvpK=F_bOM~pDXI<g0n4c1wc(RbVW41qRU-=I8slQq8?q}6)k0VuRt
ze>x79hOD;_;?i+aP1L}kpQ`(381z>yd<1e>WuT-*gv!G>7k-~msdQ*Ptr|t=H_xap
z`~ge3D#s1*>4NGXO5$BqnN!6@wQB8jNZwFoC4*~Jwfq2bSM?@Ut#qqi+X}n=D#-yj
zGpw2wL-V9|x(wp2K0}EoAN48<koc-UI06(u^`^T<xahC`8kN7&0QC}ji|ti^XvFO8
zQ~xypE>K;Y3Xvdn{xF=`uXg$lejiXjc!j=T^@wrMJE$H*Lp!9->V{s3+L9^`qt!K3
zrxK&y-w1_R^`}(sazed=j!>Lbe?J0}aq91+3OxT$se7qhEnfY_{~(&6F1-MfsJ=yO
zmecCGH=&WFZcM_^lGQ&^>?lR;Nqg>8^$ig|rK#l{JUpZRAQF-p>hqKn%T$NZm7k^l
zgwoGv)&BcHveoU+;dYKXjyCDJ>b)4Jk;;4M*h0SAKzqpo_1Yb<RH*)EHbl><6HdX>
zdG(@3G+t02qT<{lbz3+LR;g1`F{bP4*>1qTqy8!e3hnBj#=ye|>O?A->Qfie*~4M=
znI8fDT%C3sk}uRFrb7LtdPxiVjIY!ayddhte@EZM@Z+nMkn!j3C>jyK|GWe;d->C;
z0Nuwgq!RK#zTz<^Xg{yp37-z|^Xa@?Fu#YYsSfhVzk(d%gH1s~`17qGk$f2y0v+eg
zj)RNhGo(O?<`wixi81oAU4V(@SLMTt6TI(Ba3^_zg~3yNS_-&$J}wm+34Hvwn5RUZ
zIS2EndD#xkOcMX|1Ar#;^?!n-@Jp)zn$0iQV!Szg6g`de`O?n;UBJ&La*;pq8&EFs
z)9*mCf;ZMqhT;`|I#nrL=L;+VdV}9hRj&2?Cn?as#dp!I+QvJ*3uoH-1X|7A<wsGV
z{vQA96Nq&13qs)UeZGVu9i6;=6-XC9mdrokH`BYjo8Lmm{d)KtRxtFC4_gQ?9`S?5
z(_kO-eS?_pUcS=>Fn#<t1Mq2pU$hw-Pxt`J&<*kz7J_@q|N9%r5U>6KBYehJDe3p+
z_x}PD&-q7mlH&#6bsb<Y`G<ut@rqwT3u7l?^d{&z3%WFjxCnEoV%}Bo;^_W!6XLF+
z(_a`h6|DinDlIhj3R^26x=&c{4zwWQBBj*#3mgTv4+zIc!_i=&iFT{Ug$)$)iV}EQ
zYDEhNZ-a{w)Q>QTSmDN5V4e_^Q^B1SR?!a{Cp6rJ-YH?xWeUl}qqqW{3BsK?kVIis
zC!9Gg2;G>yB%z;j>B+)ldW5G43nC$sCQMrh&~)Lw`{2$9N9aYHAyh|z%M{*m#gMXu
zWu$jj_?_O3*}`rLUgijgZ=x?(sCgZYdBPHWj>w3bg(Ew`76_Z^7cCU37sJJK!t@W(
zcwWdD3yn%)LnO>s2}LgGs}WMp!u?ud*86C@Cd7<@$aSHUo&w#%=5$O~j}ZA8$gr@L
z4!S-Uu0F%eyb!Y1!oo`-ayc4b38CIlH#&*)#==u)@#E!i-$ncvYiT6dZRr*3CeEf)
zG47%zt$IDgQA^S1DK7g8XkKFXD~NcDGmb&sN8A<%P(SezO`gBFa|9X#MB^st?G-(#
zz-*tW_!51AVo5vng2Y#pklb$+-?l^R0r3;c=m(3-Y3+Vc9CaMrA@M{2Ktsfm^Uyym
zHY`Kq5z#de*rDRHP`H0mtfs??abg@D1w19HH-L*5Z6ffCB!~y;)tV^w{SWF%V&W~>
zO&0$$gWVKy5A8%#MdJ&K|D}m{sM<7LOuGdV@qP;xgQdRzJw?OQ-Z!D7ve&rvf560z
z|78d;(fq&JS1~g$CQhV8_sfZaXV4flDU$X$A(OV#<LdCFrS!@Poiw)`VCj>Va*!;V
z<Uuu@#gj%afXL-Z6-K(#?@da;Qe1lSW3zs$O2(f}YPuvhKcnw?{_gobG`FmGfEQb>
zU*Yc^x|`76ITQ)}U9;$fh7&XQOW-;)PkO+)FmJ>_z=zrWI#7I>S@+?AKQo&arNPV)
z9n?6;9N&te9yKx@w3j%>v~bXmV3upqd6M~*qJ449s3DM3O#KGTRXp?OrvOc3cE`|o
zm^`{Pa+xXrg3Duur-0-$sShzn1&jw3O_Ve1C@p=FS@IB=mzX#1!{BAc?Kb+ZF=xjC
z>^fsyNioYC%nEuz-DFnpMQbxNhO##;OfY33TbTtE0&HWJegO~LnQSUzzstl^a_%0Z
zA4XpXb6f=Iea0;teUF*_bk3xgiJ)7*k2yjCvVP`k%A5@_eeIZ%7mUvjaP%ePW&8&0
zE2j7&G@RJC=)LUBme--tg{`BdiYxocCWyMRxdh|R%4yH#!B)~1)sr2S1`#iI-Wp(g
zvprO|=EJ7aGu4;<Xayww*c+6L^k?_HfWHCk)~`VJvMI43``C?BDc>2$W_}4ah>fQu
z!+y491ket!2POeKn0@>PL=LiVQl-El)`M!DLs<E*Fmaeo_!5pDVc($2_E5Gy5k7^n
zW9MNG!&zU7I~`?zm<hdD)|Il%Cs@7-&Lpw#9miObS=Tb!f2Oce3Mi(sH{;Qo&03m3
zCWoCvk&ImS<T}9Qv6HsLZay19g%Ks}Z`;sU%0``pUKu+~fv$3P<8G*5WCMPJYnRwf
zbPVt^JE;`rZ?WGifYQK@IR$c?O)^054x5N$;YMjQ`)?l<+gQhMq0!F1eF*w@*`f&;
z#XZ({J^j9H#Ak5-KC7n}Oeg!$8hu^ti+kvE;=Xi)f+zPK9q<a^Tt9-rU~cmFXbj_4
zIly2PH+d5*#B=v2qA`KnmJE`}&7n&c@4u~7SeV2$dSLRCIkp2Dx!hnoOyqH03N+?(
z=f=Uc0&e94aE07Q|Hb||ZVb#{;1U-=p@@s5U_~+a(VHM8+-Ta1mvX~90A0qF--r5D
zPP_pxZgKpFKxyHM>Ac5%BPaO>t&h0#<<J=9JSY_RlAF5@8u&lylQ7+$k}_J2cu6L#
z1?Mff{QxF>BphwmeI@HC#Oo(n@dLOJ$$1&D4@)M~S%V{z@9-><hDvIG16Y`3H6@M0
zCDuQq@u=j0BfO807(?h05h?L{2$<uNpQ#W!N>cq2BwDhV0=6-dgg59Cl5FyTVyZ-=
zfxl-ZEA$|Rk~e>aPo<KOY^Yz6ID7=qI!Q2H<PDMp6%<+}bFHD?CE>?F<bfpqDHOUT
z7fnHWB;Olp*Y!}6xC0}6B+*ed&11>$9)RhU{P-*MUrKcI;KeJ+Ru(=vN&9K<?<~!|
z4FwnJ0$*UeN?+zc!A-it87ADNkIFDXp3?QM=<|{?-H`N_8qxvgBkdgz;w!yp4+THz
z0T+70`%8PXVIn~KDV2pClD;1dnGor+N^pmzpJf5&2tL;UheM?&57S&q%_#00E_F+V
z<S}U-6;eh>M{fp7q*N6J$>Y*L^WjXCwDTaGiI#2{4U`z^{vmLurEB^ik|cGULix^Q
zsdf=MQ=|r}^GlW5Qg%B{T0y5U(xrw=fH@;AN{7Rl(qBHubY)2+X<vztVNjkaTUy=%
zyE)R*g_xOK>HY|S<w>`#Mq|G8(ceHRmA+>SyJga;l-Dhn7SXBYi_)LM>3bWOq*lAY
zUY5?I#YKfQsSz?)q;}i!8&*oqDJfYkeeV&t8tKyi!9=YzqYY?RrSmAmSttFb3EVa5
z*B7CFU23G7fE&`UDdBQcs&oPLUFj#3cDW~QnhdZGsV%Ls?@MjYVJyZ@X+I^&yQIJI
z!0wh_SOxtasq7d;A4*-4A@fK&iY~9m()%5d?3MnW47;zS2dR|F$;3Vwt~r}Lq)@Ai
ziQQ3PyPBNdhdwux?Ng!dZW5XX4?RsJA3)N}<oQcLdz%a_1m|NksicLtuSxs|0QEE3
z_cu6ylbf{jJz_F-1Ykl<#?i_l%%t!kM8Zv?=r%lR^3Ggv$4m++BpqS0k20N+CjUmk
z!zhyvD}fzt@~;M5j7j`{fW?};wGwtun7sZ4`c9gB@d(o#XJQ<m48>C>#@moNZ_>32
zKkNk)OLr(<Ht{Nh`*%!gIB<<7Qo2@On1oz|-IJy(Q-D@vdR_^%V$(Hy(b!<xO2Lmt
z(=*Xf=ro=A9$b5Dx-A!aPff2<_3MynJVl?p%@V7i;A3WPG>7>EW(rCR95dr6K9^#)
zNe-D@vyy5!Q)E`)fW`*1cj<V|W3!S3fO^W>D7AAy=0XdE<FX(dc#$momm=wBWKM5F
zq+I4gOVEq5OADaqE6<|?hXL}P2f*!>H}c^2$=`X6!ni^5{AqA_zdV{MpM&LR>C!tW
z|M3O<J|eI2gJ`Jy$OMRl$#2Qv=uvrxDH@N-ZS7z%O1_*PrP1=_anOsA|3b^6lkz4D
zsK?8hZRk5Kub_=&ioEy){7sX4{)E1CdH5bW?~x&Qj{{n!+)@eiS@QYekU1;wpatnA
zdHLHQ6>|G}OhT2si5_CLa$^Zh)XAsQqVu}k-w9sal#l)qmKx-r-A7}yypF-hT+D|k
z`RiuB>lPF|%v;yPu9vylUN{qAZs$k$-#+sX5@6zh`P-BVK4@+xgZ^Rj#R)JNX5P)w
ziyME0GDrNqXn+z%i-&2ywd4pr*_Mu<hJXLGgThbCVg=|fUpx)}{@IL*>sD+j0qDxS
z6tw@+M2n48^XS0qua#5b*Xogz5dx5|Df%3~t~D=&8|x})>$+jxpAa(a*pJcfkkhI6
zoy~E8*p)#qaL1;(0R1PP7F+-JPR76YbiWQ9qizrW?aZ`mz_>8w^i#VsBR_<qKl7N1
z1_GFVdi?KYJjR3D$CMtUYx*z~JsUDdm>@mSLz%jD7-<qS*&kkIGJ_Im6fo{}7*r|a
zO{?Ha=I1!t;M24?zlFb#v41whbOakz0=!7}Bg$|dX9qK(8pUqE4@Xb3p6k&V$4-}{
z@icqj5lkkr#xANfNM?V351nV&-FDzI*w0piWU}uZ2gzcKsa!XYokJ%i^Vx2yG%a8s
zQ>3kkwf+O<i`jUpt14lQw;_3n6{2C{G8;M)3e{{cy+vzSb2=DZ%YIF3rmO6_aS*x5
zIvc4ruAbeV3icLjO$BpJY`HzSX7+npb+oY4@d09KD{J=ODwzH03hdrzyD1Xd$)2V{
z%7^Tpay0g{%OjvLz@Dbu{uB0Zx?qOcw?2VgC$5<uY<;rqqnO44dB;-*o%myX$&8_A
z>?>w1O^*|MW&vDqW|vZ#jtkpL%C78$3RrVvy$e9x*>F4bd9cM)>*vXSx(oB+#lDjb
zb#K<{zt=3gmhNj`cE%vU{MeIAVAP*|_TQHl*!UsX+sl4SM<EUy+0O(h9$|l{;|HOv
zO%XazuyHID<5-&k`Tw~od{6t}#SG;Zmu#TBcd6ME=>Jq<4PTb+rQOo<2T?%!*`^B!
zE2dIlVr3T9l>HK12e(&s?}PlW7pDPuwGSn))~v0kdb_nlVdz-*%UwXP|D8fD8-Du~
z5F5`Of!fy5GhuA|%RkY+b2+^lcfFiSlfjHx0*~AoJ1WrjU?P{$pqQ@jU~nIk(GKxI
z#(F%Q2x5Ny7z&}xaw>5SW73|$<8Vewd)i}+F~}LM$C=wR029M3RfC*lcAG&zo|!~z
z@6*gDR83jQMAIX;it#AG2&$RAjj&Y1L_CMxTISA9a5or_ub_UL$r^*Pv@l!g^6zAl
z>4U!mjP@Gzo-u<h5P87_d<C#q%$<o}1KXMX>s`PcWAl!qHG}m+p5y=Su0&h><191h
zBPeAvTmOZxIZVwV=T2k}uZb8)0dw>OR129ow5={@6ts=J$n3Zbg-gs6iuPP)7LSAJ
z3g!!Hyuw&_K%|oCr+t4F(@tT4R^}gyN3}6MzkqAU?hKec%pwZWJ!ArCQlB!v(&K%I
znKBG87xqWvS-9qk>lHF?Y}CKd@Mje+AOWm?Bkb;F_qRYagnjo6$YFMP6=w4Y`}HtL
z6#F;TLPWEl(B314?d}CwENe^E`blgQJr9$yk%Hb?b{rK1XS4H*U?_)mX$6<dj`1|Y
zn_@PSzHwZ_Zl#5KDH};4$uf2t8LVbwHUqncoiqa)wd|~KFv6?scG}6@W|z`8((bS=
z<>+f<%jw!|Vyj-EubJIF5%bi^Dz>Aqi;Xga-UId^#e=%pMyizSVWW1_N#Td=m|2i{
z#44|2h90xQyP@C9HblXvK6c}EfcCR?RNFJa2K^6xPuQ2iaBYz7|L;%+`=u}39%7TJ
z#`77w^C7rl_ArImp0hHFq`qMP%mRuZ=R1Ir9pPTkx+;=8;6ZP$liYLiCWZ4q0#eM`
z{0&cUawQZ5>E_;aM5D7LX)i#-CHp9}mn4}n1I`pmbhLA;l*DXC;~mM@Ysp`Ul|R&n
zB`vl8|DLasPNKY7y;K-WV$zdTC)0#4;9}-lr7a)CK<ln_@F4Izr7xOcv_~pZuDDk!
z20?UCs{aE{Ka&=}1MZcy{Lok3jA)efLx0)49zg%>Awp|qEG?W@*=J$A8~^gc05>&_
z$KU$v2cT~FVF3T$F;@$Wol7e4w-eKM3GO>H??l5dd{~kSp?#Queb5hL2C437KQoVl
zT%pXv`{2S5<v?FF^FT{AATi9>I+#sllpEpfX=eFsh$b-#ijrh9eb3=c7V`<c3ePff
z%Bf~EJ+HxT4%4E9E4hsMK5%)=@e-iqGwn_gDPX+K!4)#KHBdjt%%<1=d4^4Z-3v_T
z?|?31zWNFFjKz#Il~9&2n<#Nv$}BZNw2Y|?0cbhXFb(7)vsD6eiJ9dE(9291T{IQU
zk|RL7f+Q{)E19e-(5qrh8_-zIyrBbE!vr+JnR=#;YVdC{$Ea|pf%*A87`n}Dq-F3O
zBlFX1Kx<?wvLJJh+5Q>04(5x$A#<NmQc$mxSy+H6>0;jA0_+D&_E^AlGh-<2*~1Lc
zLm`=6;R>`2b`(7~vRLI4pk%YY6h6;oU4tN5$nNw<;|2B%Rhg8q-`u4Evc|AJC|+js
zD56@){woJp%g$H}je7P|FUYjAnh?0=#HF~&(2768HX3UfyVMyZob5gj)uZfg0y@Ut
zsD*F@>$n(BMzYq2Ve>c}<_WbZHlh{YMY9J-K{AGY){jvcW7)gkz{&}B&ficx$%a3I
zMjYE@1C3McrB8qz&lbN8(FArkMIjQ|xI##tW?#~JFNr-k8kUk-D=Jb-VH3R2m&!US
z@S|k1>o<cdWNXjE;5qi}GGLaoGpNSmBAfRZ&RjCGk$sT4%$}VOjXJi#8|JUEuV|Ha
zo%O2#cY`%8fnpPTem0zGW&>zH-NH(Kf?g|I?E})renm0&cDDB?^xb76e4uxaT~iI8
zI#^Sx4ZhE2{|=N+_8G;3yVwD1fIVQ1Mf6baX45`^Xb*d?3Y`zxUHKq`>?T^jK4py=
zaCnH_6bnnw*aq6R4P!w7f1k5OjSzXkCN2hf$^ICFJ`Zlz6ik;V*GJFDy_^|6tM+kM
z)<YqLvwROChdG<a;37GVk%BkJxy^3SIK_QM>C1R-mlH;j#syMpC7nwffM_n)NrkC-
zoRQ*w#oU&g7)%M5IThHY+{Dw6tm2N01F7cZZt%B;OYekFwVZJkB(HMiThLd>jh%(Q
zYux7tVfH%LpFwNz8{CWwAUC;v2Ov|=CI1FzZgDTIfZf1-Zi(Q{ZEg`Amb}BQp!HZI
zx0YVpP269_Kx^iHpqsso^P{w7J6B1Y#=D&M7R=w{=F+~lllz4hKwVt05`7Q2FRnqd
zo9jxU4NniZ@(Exba}ldSdb!_M1G|s=U^d7LE+q)qPLd&WXgEuHUjuQG43dbe<S%FR
zxk>I!f(duYtJ4^$mt@U*@ZMX(uYmV{l6efg@Rw{Vf%yQ*9l8SdO8V)>*(Z7AMbE!D
z$z&?mMsaH;G;$?YR4`EV|9ZRbuqcmizccUdySuPUHcCvQQ4tFoK01nuniwR;0%9!D
zxE4TKL@+F1jAbn#2v{gOAXdZ<5f$C2U_`-^P>dy-*bPQeM2VtCKlJ_%@&1uN?sM<s
z^L&?Qch5U#PMdkl%$#%PMcIEJXeyNl%YnS7{5At5FIBM*p*~r@^)aNS$$}CumdQ>(
zgJhN5?>c0!miyC|zFc`v0!nLSdvZIjl_yj9ew~cBrsCd|YaL*3o_w2pRpxxTl`VvB
zk=1R$xLqE<71$l}20IAdDHrTSU4dMBAB=@^D82e-m%NKs6-DwVwE(+i?**^t&bB{=
zgLvFHT9S>QWebg8-s*tk31KGKY4jQbqbJTB4w^~R1MnMq`zgKPCTs<HU&B*OkQNb3
z`EfBS%Ca$)QpQDWFPa&|ZC#Jw_@1}XsF{J(wArgEY?;7L(B+)SvT4L$%8r}RhGi_@
z396Q}tJLW$SS0OyOlP@m(Xbp=Ps8SF)|J-Jx$F}&J(AY2)^v@pWh3rFbP)?Z4%rqK
zPf_twc8})B$Jm)PfK%)sEwF0X2g4xkJo7&V8!xf&uTZ+lZajlA_gLt2AfK>fts!$h
z*Y||Nbp9Jf4>$5@=^Xs{*zR)!VuhLctb^QicKsvp=CD~0!MmEBr+vz~tZV?l8n)XD
z4Ee0u50snPTpE4~+2$08$85L+47*q%4cA31lfn<*v-HnUI=~ue7sWwlNBPsoSb0B`
z%2`zt8du2%(11~e3AYQ(_=SB$p0o>0=Lc!mSZpy$*V(>gbj}TSm3F?}WRoHwdnXU0
zB%A^s*F={DFAaw5@A$A<Q10S;Z6UOXe-r@ZZeHgAu!rAWj+Xtz3oKx`#(R5%eZ91s
z!lxUgXXcrx+$de4oc%oMJ-W*_NtKkClrLokpl-7?%^i$eq+<(#+$wFE1(I#j`@PY^
z?b73P*t<h&OF`A;%2H?4tx)!-HDS8aj>g#xrDHa1%2YOzr!q@93DYUnO6AyT5WPy-
z@q`&zq1@CJ*lgunjlkw8Z%{`3YGuJh=*?BC4UnBEmxod7<-sw~`<-0sfzn>tOoQ)!
zInxa)zL)27=q-`G_JZWFJdBn=N95iapgbxY+Jo|m-2D(J)6_mu=&k~_yFERBPN<zL
zq4!7iv20jzUhOgQ^^C8MZ>06leSY^StZd}ZX*h4<c{{-T7tbU|Qj&x>Fhd<awhR5C
z&}U02dSuwz_BbAXn9|by3VQ(KpFx|9M&uoZh=BKK+B!0kUa4gMeCSpXO$ZBxP~+gY
z@H^2!LA*)NDYQ2EMhP%e_Kk!AfwQN9?JLK=IG)yuqW7jX!Dv<N`2(PtlSWg{xh0hS
zoyf*}p?Wd%qtPje&7rwmGV`Y8)DpIwf;9zfcqQnu!FxVMkPfm16yrL=!pWC%oaOBW
zvXTw!0&s>^Q2$(HskA7(%8oxk=@x5kjZ!_k<%^a!vCyBv*UUb*N8KWRXCU~N@O4P=
z`nzwo(Dpdr@-FC!PZ!bpF%DC146)4YOIN@%wv+x7$qTleb`SoWwK@*|SL{X!Y?{x9
z3<q)%-)#rV1RhVDiIVukWzdw&zowTCXY#x<NY3I{Xlh=_C&Zyt%FAvk{#IYZPi_O|
zA`i=jh+p~0+YtC0f7FSd|Cjix+2Fd&xA#NkAG~P<NN@8gUMSt=_7`B+Jzmw4t-vqP
z>i7YF^#OYKFJ3nc;-7Oza<ZmK^K4<)GO2$lWM@b{=Aw~V(pS0Y@|BYMqu0;qcdBW!
z^@!P~K+t10{2n<bn%I;T(D{Tp?1G4=tQ$FDp0PR#nl9r1if(E4_c_p+#@7yn+@<`t
zOHjR%cRLUEReU9_lmzcf$o1Sv0nrV-k!GtK`9A8WJU)q>wmbNlzL2?-FCGPk0zRXd
za?p$UIvddJ<40eCrj!q&u-{>RSqZ(zdBrn`Il<enMjzGiB^>;x`6vp({Kn_gz<Y_O
z(vI=VJYfNlSNJGe!e8Z|975eS{xlwZ*SQ0Qw{P&y<aN8r%i03`&R-#jXT}2Y+}CLR
zBfjb!z+?XQO6n5+^ABKr!lzO&?-}ny(TC?eEelP1!NVS-v`BidA52S-JdwGGN7*Zi
z_3o5D(}3>>DZ&$V7o-%*F}{Y^w}a%qbP^s;yt4e_NYph;rh1rdPE=mXhc!ZJ908#_
zmC=4E9ac`c4$>N>-2>SDyRxDJq)(L^2bh+s@;(8|l`7*)lyX%=3Sd*7>Zb{4?>3ch
zDv)dBhZJpDCqE~@@_M<Pc1UcHZPeh~E(cM>Yp2Y~9bRCTJJ7T5J6UxMjJxIfrzq{0
z*+f`jk-ekQmj`5@3|MhU4x~*dC33nCOgk)RJ%_?0@&H6FRb}!rd$1pqO})TgE;qFU
zUxj>;qLruQbH9M0N`B`HsIQi*C%~8**)<*PXJxZ@+3Tm>;6$3Gf7bmk$Qu&f0|JJg
zrZl)=*Mfl=?ve=`{Oair_RlT^?}#fh#0G>lf@@^`UfBD25zQD!`L}@$quUHZ?U;%W
zp=|8k?ZA97o5I-R;+BAN{L()l;md1P6!4v}H5#IglkcE<(%T(j<m7|zLeLcHJ}`j}
zGLD0;3Up}jl=Toa^}s!d2&pBzLlcGq6E-pr$Kiz(X^wF32FkB;d*gW8#Qms^eE$ec
zoW89H_^3SxfQfdZ1h5%jJS2zP*H>uNiJ3<+MpH>oRLnFOaXkC-P~aD^bR!y)%vw)?
zkRuF9_E3e7wd?QboGzaocztJg^y~`)`@E~r(skZX(Bj;NI?KIu4@CCbPSX#cALv|v
zn%RKkarsXn#c19@KH7<^e?TFmo;<XnmuS^8L(E5~d~J%s@i&%qh?v#E5x?^WC%~#i
zHsxc0<t&9#8dk84-YDg;GaeAXiTyyENOrRQ`%v1;iZ{TngY1+ukcXHXJ^V|UWhYE1
zWp_Ny&~k!pr-^hm%bNt!U)Y=|R9;~BX&Zel3t~{QftP;*OSbWLN`PWMwl|Rb_+4`M
z?dNeDz+mCWv(Shm{73o+7gu@1Q#9rppVAGYbEKM45WQM*$^m<>ltO!R^QD-!^n#tu
zQY)J1ZIS%HN6s<sU{5QBTqKp!(xh5?bpjkUQp1PfI4w0NqI6EW{18n$FBxex{Y7fG
z3zYRz=~ZaTP#!FS6$MJiP9WK(Ot=e%y~+wo;3-yG;y}4yX$!AP%Sr5*YQ6!voj--H
z7Q`9l%T%=bS7j5u6zzs`UJ9f%C^t2uEf18PKSXmEs1i0qSh8xgouuHYs_79?3ZAB#
z9{3Hkt2CFOVWq059w#JQwf-^0=Bg5dfn295I|5rysl0nY=4n;Nb4a;pR#g>)=8CEn
zjbJxaVb?%<OBIw1P^bEFC>nTQ^>{2-$PZO7Qeaw!yqnfg>tw%Ykd`ku(C*=_@|bvl
zLU|zNsP2_7R>S%dd9DLUj><#G*H$50I>Dxs@_YRu<+}WEE|7o7{^e!B*2@lC(6k3~
zCV6^a$fxE){Y$y>48$a;kJ4jgg*u}S7Oqm8`@sAh^+HM;UZakoG=<IT04E6DrtXx*
zZOvVZVZ$l45AEfvR9lhXtw!DW7|a*d@v|Z7l6o~QDz2($bpYiJ^?eG})~bu{Lhx<%
zue8E^r1qp-$tUW7v0(VOx`zVt7iy9y`6N-}kOrB_nv=ItO4ZDxgr;R07X{d}G;wB{
zG#t>#3jr!Ll06tNXiklQrr$JC6d?ayW7`{~b()HJYP04EO`8AIw6%ezCQUFUB0STa
z*$uvzn#6iAEYMEd4v?VTMlpgU?K`wE%G6fnfp5EZD&;{IXnkiw!y#?e5lSH})2{s!
zq~%&i%9X0pet8`RpVt22iPBlEGbN5))(+kQ##`F9bcx;5PJ0)1joQe=;CrksbOFOt
z?Rm=Jd9FR4in?a)o{p%SZ>1vl^&+b?>!EP5)w=y?#AR#WAoTW4>pADi5qrzpI}4R}
ztiv0@anE|)A!ur_j@*b+qqWlns9&TDqMeW_y2`--LKjJH-CW%W^5(DC`H>@XlkOZn
z4+?aPrlPJ$_rW(Xv{=`lJWJo}Ru2X8kgg^U3`cc^OHp@H_t#|_(NF8n?nd!f-6&e<
zUekqq3!0m{IP#+1(s>Mk!FP1e5lc}e>+@)KpQi782Ntf-yR?EaS^AVhv_4zEpC&77
z^k;G*Ww*X9JqnBUtu}(eqIaZhq+|MG^4ituebP~C(l^om2J;L3U!8zWv@v#viODvu
z-T>(~J8)UH+~Yw}YoR)#!y*vRxI}@kZz}6hHLvQ<>&JrpD-EOX{-}V|4u>fs-gRpr
zy25F&9>1Q|Wf17SycV^CG9Tf1@}2Xb2|Ife$Fs(69E35Vk4}M0b{@tk&R*E)6%2nE
zIq+pZeO<<wLSjrV!GST6GhGISn5M->&v1#2c8U!Tahe_-9py4JI%b+_MqqFVXri2A
zLrk$I5hd{fE<SyYqekQ7=i%-X7ZfsNkndzSXE#@8w}0S_Ga}={BBD%2!L;1B>&%EK
z4|k$-c6D}lb@y=X>F(jy)3ui|Haa@eWDJUka&dMRp<3R-+SwV0e}BXfCGYs3RygLr
zwUN%inCVVY(NQ5zA%Q^=E)h||k#SQ)Tuie}ivQ1Mm#TPpuQxnL)iQ7YNqj_bh{?qi
zJKe(_hQHCdhMZ1s)b-~7<y`-xi;b_l*cj~SXmoRP_P}NIPlDL+xamR0crRR*j-fM*
z;ejzzak<3)&nM*F|HOrurskbQriS-=qb~WsUH%qa{w{aKlgsK>+Q|XYCcEzL?qe)f
zjokQWzc)LHxUqxc!jb~;ubBdBl_!RX=0(;HmH=nf<jvw;XO*Xz(yX_&+&`<ja8$%s
z>TJcav#K^p<*Q_T)%a>G<*T#}FPN7wyyWj&YBQ{g+O+;`l<(xR1BZ|CwR7+3+VVHX
zQncNwZj?yM=LS);N$+9#rP*r0m*UgzQY+zIE48uMj<arX6niqP-m`Q`upZmaQnudu
z#S2SKuCB{ZBB$A^zvWS=zOtWK*~t5fij%yxco?JBS~}$G1Lm~r>DI@|t&gW$54*oF
z5Ia0T++Drg+!YE-lAX;$8@oQ9eR}qC4e{vJ$IUZ1G_ZH?-XU&Y9<FX~K~txCd4}{#
z>fvI8?^~80E`~!x`(U6@a7>^#62$jMf_jCbj^JB(3}Yt7-&QD)DXHMdq4Xm7jzY1;
z(*9e+Olz+57ON5s@!Zy1*eo{q^FiKX62al#;=9F$<9xKYh)**3vjkC*WEjD+#5>6V
z`649QFq4&tD=2a0K;gWEcn6AkfGko}Edf!9XrBU5E2a~u7o`Ba%UEHP3R>e>F$s{(
z5rwHO0-FK&pf7}f8nF3dZ5puW#C-s694`heZLwkL(iYk)1S*BovKE@T0DO3~s9pvd
zC|yoPCZd+3ST0JbIOt<xvjWA(V&V$$OcjLyyo;ZBN!Tpmmkw;bSPQ^MPY@01uux|d
z12RxsDVAoSwm@6~;I@InITP4?F*lP0hl^?|7Krv)R2wOxvZyB_#bH3UM(9@p{jVr7
zX(fu~q7X$^ESd@1&m{a;fq1w{tZRXBqJf|>P7Dw&)JsK+SyzO?k@wdLt89ZkAM~wo
z&Ng&Y1z;!5=VE-ep)<=9bF&Q&?2gz>AVE|CsJh$RC_DwTw`nbOIR*na+KUc3hHhw%
QZ;ru%D`$(S97CJ`0!}~MeE<Le

diff --git a/Debug/Libs/sta-core/src/devices/stm32/gpio_pin.su b/Debug/Libs/sta-core/src/devices/stm32/gpio_pin.su
index de04263..f8c9569 100644
--- a/Debug/Libs/sta-core/src/devices/stm32/gpio_pin.su
+++ b/Debug/Libs/sta-core/src/devices/stm32/gpio_pin.su
@@ -1,4 +1,4 @@
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/gpio_pin.hpp:31:11:constexpr sta::GpioPin::GpioPin()	16	static
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/gpio_pin.hpp:31:11:constexpr sta::GpioPin::GpioPin()	16	static
 ../Libs/sta-core/src/devices/stm32/gpio_pin.cpp:10:5:sta::STM32GpioPin::STM32GpioPin(GPIO_TypeDef*, uint16_t)	24	static
 ../Libs/sta-core/src/devices/stm32/gpio_pin.cpp:16:10:virtual void sta::STM32GpioPin::setState(sta::GpioPinState)	16	static
 ../Libs/sta-core/src/devices/stm32/gpio_pin.cpp:21:18:virtual sta::GpioPinState sta::STM32GpioPin::getState()	16	static
diff --git a/Debug/Libs/sta-core/src/devices/stm32/init.d b/Debug/Libs/sta-core/src/devices/stm32/init.d
index c8d3750..60dc648 100644
--- a/Debug/Libs/sta-core/src/devices/stm32/init.d
+++ b/Debug/Libs/sta-core/src/devices/stm32/init.d
@@ -1,8 +1,8 @@
 Libs/sta-core/src/devices/stm32/init.o: \
  ../Libs/sta-core/src/devices/stm32/init.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/init.hpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/init.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/stm32/init.hpp:
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/debug/assert.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/stm32/init.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/debug/assert.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/devices/stm32/init.o b/Debug/Libs/sta-core/src/devices/stm32/init.o
index 53fd2b4f7c34eccfefcf555800bf5eb6490fe54a..2e4925e9861e48bc0d5e80aaa6c9720e57f4ec50 100644
GIT binary patch
delta 7497
zcmcgwd3;T0x8CpG=iO(>2_Yc^nFJA$oSY;QL4;<gAPIudQWApn%T!6w+v={O5!8nr
zil)_~#1{lXP5qQo+7eooPUxVNDs5G%YTUb?)%(x=``+I6_gic2wcov_=UMN;CzsV9
zzg3roh}z|$9~iIpSCr7l(-fs&oT50D|M{Ot8Kfv`gl_`5HK9-QRumEFL9R%@Om^A+
z>_D#LR&pi!jfYE>k=f+(>_o04|1x%23mzla!^g>$<@W+y7WsS<xjv3E$d}{4l6}^+
z?&LE@k!zY?JzO?f8%?f%cOzGk|3P+HTd5|o)|Xr_2BI(_HL@25p(3%GI#FK_LMg(a
z+SK*Is6nhBNA}(zBp2ty$=(-?q(Y20e-L3t<Op(I3P1*Nq8Hg${WFB3NQ*2gtyILi
z!Q{FYFpgZB#acvJ#bi3F`LyqeFDhs*nxA(v><t#OL%fH>wxp8X)dxpKt4ek+@0qas
z<&hoZQv>^J5}MJ+yABVHG&-%nPb2Kp6i!R^=|VZhXgAq|J4D0Y(wpoopT4k@DZMtb
zLl*3r1f->d-%)%U1iPbuGwj$5vOD>I0sEd#cISYruw@L{q5ijFn;x1ob7~KAg!?-X
zY=3*QdjxcZ-Jj64#06m<!tYVC<AX5>F})Aj$-(RoA4~Rt5cVH6CuzQ--khy{ZX4f~
z4z_nJHpf}6B$VXRA&o%wScQK4?G%_ivTNP|dW@7ZsEE>P-F5bBA6OhRSbyBClp&53
z0#tLVQomuoCi@xBWzlz*zdpApl7Lb^OoTiT$&vt)ilZZ>AGIu%NfX#lFiItsu#w6Y
zAIOv($f$V8aH>@*Ptr)GQq1QI2s5dy=9q7ff&IM~q|t#GCza0WEIG}ZcCZ`$AkPeg
zJWcbJicUyKrFsx#p&c@V2qKk7V<CfRgi_ht2J#Ub<PP=}@VArrq!9@J9~?P?n+!9E
z>QecUh#-~jX^>W~D}{UA-xr=?Je3Dr;>#RvD2G1Y9d8>50I6K&LO<m6skEX}X&DIl
z%M*|<@%gR9VVW*a?sx?3S#4-(rP7aI+@M=SDvLPrpW(23kA?h#c26qn{UN(?nk1GP
zBjIszSr560)wDbW2XR9xJ}HoQ=xU(icxKOrz`mCZIf&byJ6JL3VNGYaR@1^rrJf<E
z$$;I!Bf9(u?DjmgZ$`r|V*HvJ*WY~M3Cx4s&<pYik9sPxOe$qjkf-SaBbd09ehgwN
zv*A2tF{EN6rb;E6i<p@JyNFYM!J`|<rA(wdhh`8BnZrT7dC0riKZ$loDmU4)jVE`B
z2R?$qy3S=;TsZS3m$iWXF=)V0vN*&+4zZl2WeASG##sI*({mql`)w!un|bW-cY{4?
z1mrN<cB!=GG<~_(N}ftg82l|=AnVxv2W_WRdU2uY+^}(rD|$8*FHSRxBbeLU+QIWK
zhwjV^wv<ygF^b6&Z{KJCLIy63-=5~6K7;UfJ5%hvQLs1gT=y`+!|7LtU}B)-3`X>j
zCtP!RZI(LtV?Oi|)8vsLcxu^G&tsfP_k~nOF+b*ahrNWmbnx)Ea5Li=tT*@$xWxNa
z%46@(;GXlsSF<}Z|L-#c9`FDUaP7VUc-=V=auWBnlxek@yR2a<{mzr<&80UnS89jh
z{Hr|VmzbW9a{68jV#9E}&F2UP&p5?{`TrD$*u-mA$N0U$crRuiEZ|Ce@W2C@E4SJr
zP@gQw0zQ9|SC`r&Pa)6aVifG^evq09d7I&A<{Pk?mvdP#^Zy19Y7UR3h!5T54p#7x
zf9i{mr*O)y?772}DCS<1xbJKVB$d)wNP{C>X4Gq#XfyfkWd3$0&$WW*aU0DTN)qGU
z%CB!Rx>I=)YnTm%-1iW!+M61b%BRf#C%M-XjO#VFug2r;IEL>SlRA^>R>)vI#^7G)
ziZge)pznC<M!}<S8Qf(NPr|<qJTB&E4deHN6P}0sK>?HNCU>y#arnFQz#BMaAmf_D
zWc-7B^<#hrb9;X5ck|W^=0a->4z!e$xp~=MU@YAX!E>B=BClmEBYJ>m@HD^8VSYTz
z<UPz?UgtC?7?ju3QQV?b$PElu6~l3B3_Otx(7>Sv9#VM*J$2X*c+_+F&}K&c7~kiX
zfq45L?3vC%9UOEmU%med!rNgC$3^DHS#GR^OB}|NdnXHLayiZ!F6Ha7%>Q8S><K<}
znU}4Z)4$8>H-Oo2)q#)KbJY(yeX4-RcLd~UChtLxGl2Vkz&~9jgYh<y=PLMo0Yi|=
z5Twv=3f=z&jJGx#M>lfSD>>X~CR#d&IKcH9ywf`w<38NwF+O?buTk@*`xU1N;Hzm8
z7bLiJPcC{sv!sDzu1KbghVpJtB(7$zc4Hv=F>z+`F2u8E3{xzaXA{arG&6^L^~bjq
zndGfd$YAC{Cx6&Wxv_oOu(vQvCNPwF4BTO!gmJ?guixRGPH~_agWx&Mi<icMIx=Q0
zIq<*nR{}124v(>czba-1%*n)=SGn&)+`vut?+%0iyA;T~-5@XV5Bddz`P|BN)$-8X
zJe>3VL2NHY(Ul{dz8zt&E9+@!y3(HJp(|EmiLUhJolYG9yN>;bqG9VCErJLB14Sbb
z7k7Xe)1fblINp``uPZ<EuXO_>+DI>SC5ty(qd@d$I>vZ!9_;nZgIKQJiwf11+CV-7
zES2s2w%7yyQtsY47WQ^7tB5XRT}h*|bfxDI$Otduzpfl+<n|H}x{}lu(nXhsuB?eg
zP}2$d3)h~&dvSs|p(_Oe@Tc?S?A*XcqOh)vWSF+<u(xMH`b>oUnhMnwZ)#FkY!Q$b
ziMGW5${q-m#)KL?9Cm;w<ZQmV_7Kwaph){JY<HU^JIS`=F%7S-6kfK^qf~q%crn2x
zyUc>@mWVM&e}p1qFSa9@a1s<utpx`%jChh`lOwSI;~#*D6L#517On%OrcTD{m2Xo?
zKJ^kdV0I}bkx&1Q4S4Q47`;HO#Mu5R*5m7C;sfw_jmY*QwLvVyrO_Zx0;ncY2?8Au
z`|$3dI698hA+Z(^zio)a;iON9fvBrlOhl6{q94BaRNQDo>O1iz82h@q9PjGY77%N<
zx&Q$0QHK#N<z6)vG<Zu*)kwXg)+CU+q<#nWmFiEJ$~D@T_+YKp3P!%7O#@6DHKPU1
zys1sWh&E|DHLf>kbyTUoLz|jG&StI3LF$aQ7@KrfD?p}Cv}#m%UTcfCTeQ9*q<+-q
z4<)t2;_gdot7R!5XtX%`k!rGhgs0t>7EEogr8lJoXod`KrPYyP-js_`{MfP-bN}4Z
zg28`d>4|aOvOI(B_{pLG(7Cc3@-39V#L!=+7t4~OQbk=NOY&z^cDWLKS}B8kNv)P|
zqv}^=vp=cV<i}vl`|>UtJ1eJj1^%B&uV{L_C?8_yzme-e=_|6jE2-=9XH;=h9vMv&
z`B^>*Kv(D~Zc?x5cW`8*z6%X**3W=b+w^&uWRu<l>X4ob2#)G2<47IX>&K8fso$p!
zm0#;4h$M!*s{7)@AN6>^`;-12K762mLmMg|>iHc>&9`>KjFwqXq3u=H9E4e8y^N<i
zs|DNgrgbd%RByeAJ!-JJl1S~ehM@c1)*gb?`_?}vkUC`*Se`T1kFh7lXVy%N^h@g-
z2y@Bm#IAi~{R(-%v$g`Q@2%%kN&RY##1QXVLn2B2Y4t+-7i>20X@SiHJX&aLu##GA
zs{({eZQVh#TH7d0ZNDvo`jy9RTL8?bw$ISg7lv))Akvp@J2B_$wwtK*C)-}sblWzs
zKdIkr30Se;Z53llJ+#dsDCAuGN(7y6k4M|p_Fus~)7}|RTkPkUfcEdx=;@$+3HX1+
z-Y0?7F?%Ph!D;(iTxe(QMhn0@XV-A%g1u@4sVnx;ICI1PBAD=ty%rtbv8Q2d_v}M~
z&mZ=B%&FD>3Wo5!V>7PGd5+(3<VA<08>tH(J3Ep3*5gS`=8DJs;iRs4Oiw3u!{a{Y
zd&?uhfcF=Vc0g^O^Dyq6Mb0p&mz@D1#4FAMTuJMkFJcciIMadQR_BxGcZc%=uBF}1
z6`=J#XIos=2c758%Tec@fuv44M`J_JIs?a$`rP>=mg6huQDE?`^BG}~zT%XfNnLY}
z$G8`IPQrkfc)t7usb!u?SdLoH;zUxbJ%?Zxb)JbB&`wVs&FuE9$szTY=TY?Xu4fHy
zr0br0fbVaf^DvSJo(9lb&?W|RTG%FNFsbEjI;Yb9Vd-^CKJFMflrrmjXXLl;p_=$Y
zuvABpL5;#&*Pf*95H`ksiU8#kp*_)f4?luSpC^uid-Fveeq$DjYu)LoM)(qU^hKf?
zJuMa`Ui9>um=cElUng$5$$L+9!3MMn3!WCJ=N=)oNbL=NtW<N6ca1tPh15EAI`TKF
z1d}2Ut9L<~57pVU7F<r-PUte=9M~6n2}5z+r-U*&3xvq+A49TaKO!v=#!r~*Ch=$+
zQip^m$ki;Kp%U~v;{C_|JEEfkQ}oJ16OnVMBfXbOtkR=8(njjhyD6gT!apzSF?Wa`
zy88;vK##qhOkc$nW0&IR(C?`1Jq6hkGQfqzMy#>XXIuuUq>u5s@7>2qrtZPDHbkT3
za^w+0M@|?H&-B&6<*8~9lC%E+$a6&$#<EZ>MJQ8@N067rVz6nwI0@cw6Hnv(Ug4&G
z^?ibi-!HiO1EQlp;jbSQ+`u8h9lR}2wtiG_C+`Zh!eezr5u&ogDirUZh>V?TFwoE(
zTvFX`;tvMl8MxG<eg(hWn{k)K-30-Xj-tzC4Y;KY172xA;7-dla-p)ffIzt#5r|Xy
zUc?{*w*-<5b6~k5>JgxKRUeWmjd3J1r`t&8UhpOPyqF4N%@rE1-4{d#HgL5#i;~ue
zV>+p|q7*ULi(4SX25}#R-zWm_V0X5QA^k`-iZi%AcZe1Mw@>((Spi*)Gg!b+L@vrW
zFaAJHEn*-#xhi&LlKNgmfb!QwBG9-inlbTvLhC^4ci{sbzo>4WK&o0DiE<aJ`%%j(
zwF19*FRMPZNOHA$a0sbQ>OG*iS?z$1>eW2{7s9=&Ke~NO{Rl+dr`89PdQZLHiPQ=8
z8C)@E)X(wZr|Mg{6fUZEpmIt5C)oF`ihqceSJip=1-YTBKBVrdr!a%(wF?;90*!76
z+6e7xIH{MkVvK3EHZmJ^uhDuV+D2^yN_<mOdXw6z4MX|6v|ONlL@Pq<quMkg8iQDH
z7;9J*iFoDr@!{+xv_SH?^lo%w8G)iHv&|1WCH8R*DlacCnw(!*R90Hy${m#z7n@pD
zP?(vP9-Uua?n*5ytt>39tZ=1IE-ossD0Gz<S4}ITlV-cX^pKML$z>G@@e|$A_&+u#
zHZCT~9p_GnO>k9~l@(W*bAvh#a?z>jMWuzx-<~SjRq=Gi-=4<z@1L1j9_;*o$>K5H
zl|Q2-s<f=MFsd-WpvYA@y{e?ZH8Zg=sw8r1xodj<j47^yqDq?T=!(J_6|TwoGm6V9
zTxn&Kt4f#`BlAWLc2$(;PcEETS(snqN*$CPl}cYt%qp8wRa`hRw`^+Vto#{;=1U<F
z1OE?#1e*3xpTBuF?%<%NPeSK79hupq65>O;6c=}CDvREzHx2JSpriT2%!sB{Ltk}d
z{BOH)r4<%bO*1pcTr=ax_%^xoPIx!Te_Zu2M?{C1gW~;~!e-re_$RqzqudEGF%cnd
zcXV8|JA~FOHYU*>+vIxTbXQT`)Vj%P5yhr#m?h?$a~g6)t$Dg3N3C0A25rq2qs)@6
zIqJr>=D)XQtEbkQZMKoBGoK)Jq0ZdCEnB3St=n?M6f<jkj#y&8O0t)ElkMcj9QDu!
zb7><EU2M#uEKxfm)mq(rY)2PLGiOJ*%<G~kQRbE%VU+yzj&SwlT=VXZ?rPm8GiYab
k`TJZ&i8q)3%iA2k(~IJk><m{AEihNntF4<9<tkqN7beGG%>V!Z

delta 7614
zcmd5=d018D_TJy#=iBETI3NkgB%=rta+pyRN1TuVhcr!0g-E$EB{*c|5zE<3-IAh-
z=6pi~!+{*~>eaBW8r>|lQqvSCyp~!HIo$Owf4@Ka<32r4f92z|*4k@--}=^i*So&0
zr}?~k{6}?Rka(~t_;bh16h#T{)k{&*TPli8`TZZ!u7{$i5nf5;)`VW~t|-FanOu?H
zY3#COv?A9bGr2l=XTzn+;7oG8;76`xpJH~IhdocO+at)8;XNHLlgv*hmuh#AFUzNb
zeddZV@=bV_Tw}dA!DW#L?c{1fel_1`H@nPDl#{sTMXs6tNK8nL?AZaxNR(40>goWb
zA{sr(UK5BM#IoUJ?+C!*BCH+R^?^84h(X3x(Z&%xkX&bcae}zhp6n){K0;9><ylmw
zh>CvXy6iigT$;%|h)xx`v{dtG`80MMBwRFa_b#y4n#c}v9{~G$PqITjuv9!$$!_mH
z5q9izWXE{Sf&Bvs&C${QJv^)@=(H4%8rVB1oR;blLT8E@v1Ir2w8LJUNOp!tC)kB_
zyf(-)1NJCtq{-9!0QQ<;xAHj#+piDVem>vAzN3@f+P4XIVhq{AJ~v?-&YCT4C&6M0
z_i;inC#uNQ&bJlp6zZ-iJ^*+K(U<ImKmZ{Ib|kw?Ap8A?k=-?j{q@FZ%}XpYCTpiG
zTS94JOQ$kpxane2?qFJ^QB$2iMLj-N3QQgu+Py11MoJm5i#Vu->Fn1&H#y0`2hSU2
zGRP^B8mie;sUJ70WM@ZN2JJIF*=|xKHA>mm0rF}j<XUQwR7SLd^rn)fGIS(lEwxc9
z?Wi|WNg{GcB{2&!Dgkmb<tmls1gTVVczq7_Oe%*tX5CQOzqvs=Jc)5qk-Z@c`Is$F
z!B%`A4?P3<knoktjn0rIJs|U}kbQ_CQkfJ7X(kAz^0_NyPYYxvdlvKF(Y&(JAO3WX
z+>(p*aS+v|@--1bDlK|J`f*;}xYjkD;CY5oxxgtlaJU2x-6|Y!zoQ07<rF7+mXA-S
z5tYim?vR&WfSkzdD^g+aXXJi~fIZKZhE^(}{Nh?X?74h!1`$Xqk;7OrDz`XmKRza!
zWy&DD_2#tfjKLM68YM*BAk2seQaPOrd4w@L8U*`?E|49#>`DC;2R&SE4c7u17^&Rj
z!^Zc4y@Vk;LX#(zTyMw|Lm)?S{|<6r`>@}grcf$hwTIl#P-hd%q_QdsGJxa9a4MlG
z@T4*uKA}?_QfW<0B_i;mQAw}|@sW)TT?D5xWH|i)w)093YGsf&v41qpkW_wT&m(S1
z0|Q>p&GO;(3DH>dC8xEW{b4A;p`>z%-5g>O%liz@N8HQDOwSLQ+h5ucVkN`w8wPvm
zK=yF6x^eaM{NOp{1zFw(GMwdgmd|oiLO9WPxnRcy&gf_`mOf-E4Yb1E&r@)VLl=6$
zbG9v{iC1=EO8WBPP36Xw@!J4@j>FVD!xY;?-vFu1XI!h8;NkSukxENWF~Y$eZFGUF
z+yc443Gx6hYG5Rc0C+aB=On{8k?sqrbYXsc%}AUMfoBARf1gvF!_E4V?|=rLuPTPU
zEjRa)8`gi;iuvE4c^k=nTH6CJ#`!`Pay45Ss0B=`yIkdXrcxRolg6q4ow+ji8SI+L
zAiv4<oW#es=O(^C0B=9y2oA=$n=|u&28X!AU|#3`E#-cf_s51x&a@o^?#5hE*<;VZ
z+d5u<m`68;u3)L`U_4y7`VzjfG-i7Ur}Btzz@6Q&@?0SE-;W`EiD9Yao_)g=EM|~T
zcEZxhEg(bLbDNRK;aa1)?o|{>Dph<3)Nq7T+;s;Nt%2X>^4<o<wUqI=jA9&0vJ*Bx
z<ktaIf>d@g5|zw`Jg$2RXPwG#k23%N#<kXRUoW%$1>gKVxqZ8s)NxF=Om5a(o{lI6
zzi$vuxyz_K();3J99LP%phdaDGmS5zkDq{MgQq3?>$vOJxq_)9;Ge{Rzt2bdb6;08
z8PmBn`7HZ!dHL+0&eIgjiOz9wptF3~bRM?p+)LjlE#QOS;jzq#!eLh#gB*U_yFWZf
z`TE+#RbJs^_Ht9^^v2uLRLDwh*2~<E3q#?V#nY6O?!ZHP#^7lkb|eE;%8Pb$*LU%K
ze!UysE@00<4ytg_g?#n?7J#>j+>X=Ck47#mms1?gQ14*ErgX>3L!8Pt!<heBT-kVD
zl)xi*kdOD^pzkmnnw+q08Pn<#AD=4Vap4=VE0gyc#|h`Uf96kDZa=IkVq68Uuj3Xh
z;T9~UZwKA~6S=SVIP^NsdMbxYXQFlH5Vf4|1fJ=w+~ba1<rZF9&qsd8H`-Y~M&qk#
zAtxj_^<R1A6lTf$9P_m<l$=Ak^)zxUVXnGzBj)?UvysQrpFJCyVkLYLd2tef%wf+I
ztRy%{cH_z{%!2|Sc-C-XA7;Y7&ny|tt<2!YxwV1ck-|{?gKIj%fkrShk4n6*;6RVL
z_eZkenac;HbJE9nZ#D1Q%griH!<wU9cQY5zm8V~ZvY+Gh<zk{avdzKVzQuXH!Jzpv
zIAOdYhsdZaA9TlNGc`z8<`HPRl1m|U<>3(a@XGdGVP9u|vmN%0B<u=gz&q0#U3u`N
zmCTq&Tt=(54!k(UU+ZcUHZ1D|PbyD#JO!eEL~!ReGtZYX58fo=&_7kEHM(-qpVy$5
z$~t~qK%=EARb0JFG}M*HoYtVuu%oC*T?y(B*~N|cuPbicIWvK&D;X^yr_rUME1$(7
z=tdjlB?h)V&qXaCT*oZw%*fqj<d!oY{kTn=bwpT~0qHafGL{;oEACXJu5^rm{FG=*
z{0}Bzsngu2t^;7(T_8W>o9iNVnjREsU4iL#O$Jk13<4T%z7$@ze2$Ld6@j~{T{2`N
zWZNjfY!5+<xSyXQndIY6GW88`pwGAjlEVrkF#p-lfQchNvXIRCiBOO)4aew}Y*9(R
zG7%Fnxrh#tuciU)sb|6H8KNne)H~u9&|4_{u(49)xRF{b&f(Ii7Cs<ZofruM?Gi`u
zZnvl(PHK->ID*t(hj430x<N!BuVbPgiu^`|V#f*b*p<`;(LRjSYIO?UZBq9E>}~3H
zG<dt(6X@+wmmss9YAWuJf2iZZy))`jsIzJm^;A}B&bYdlYq!A271~I&X`SXcf@0Qd
zlL65N?E#^tS8KJDsa~sP^&#gmZGsc2FSPG5VU1cHPCBlYAj7Y<(E#-uZC((mW^GD3
zsl_H=;;`IodJ8S6G2Oybov8s&+f3nrYlkV4jz!ZPGO&q8N49xDWZ*9T+q3|<pEB(O
z@aIfHfa^b|*DxJ7OasBXayb#_&6dHj^q=W@vM|3$QRmCTF_Y<Zc?f`3$YL*2%cLuK
zwL%7BUzI!z#(XBvqOeA}Jrw;vDZAV0@wCjMDV67B1t@({p2X7?c?wxvmpg|LB0tI9
zn7qY$F`X-`^xkbrt<zU@Cbdzo2dB2^OP?ZDr>8*e(NoZZ1A0X~sY7}d=I5~Pf|2?`
zU*n1Tn{+R1Y}WnJ-W&S2*!Y`%f+kcx(m!fN>MgSg7%epWgL3bhdm~JxIRQ`anY}SB
z>&=<q(<ZYW$W)uXaldRezk;4^Gq)3@J~Q7ON$QCC4z_<`R-;HcPMVhkn(xfp5$259
zhFLpjjsbcX%$excCG#hA#migf*FooB%>yDyJur{KNz*NlaPAC?0FP!{s?DV4Stg)`
z3oNZcvL%-FK<#786slJqvfM}L6PEob>05{8?H;6mv@8eCS1i|&=?#n7kJL>|0lqK4
zSY{!MyOw;q%;Y0WDYZhDTbmH{E$h=bewOtLm}gj9;_2_!J)qoXYhy1`yRECi|NYkB
zBvJ>h>CvQ)S{LF%YqUD{bte6l)eCFBx4t}()J5wIthr`=9ZdMyIu{dj+uG?lQg^JQ
z(4YI(O~C1)wHY8xb2@>m@=d2}STfUT1bFeiv)Y=}dFRnU=A!eI0i-TF5A03qnsa}E
z@E>P42fRN!=YXYe+P34~nQQZbT58ikh!wUv+$^hXuVW6@+B&0$n{A^}Z>{Znozynl
z><m)%wl?6^Zrdf)a=>=FJE_CA4VchIn>(6*%GR20UU}B$4)D&~UK0+|7i~k4>1A7Q
zz&+b#C;*=C^7ad)7P{nPIF`5!=|F0kOLt)Lp37JOwAJMX0N&=}$Rf4Vr5?5X)5U=s
z>55Ag`umH^tAOM;mqr{o!*w)pn(b=FmvE7*Or`n5(Cel#xMO4wI$76S;(W7C_Y7YM
zrkx-v6$<b5mLx6fF)`Nd)KFd#+!cklbES6aZ;FH9-dkc8zA>{!ayUKB5iZ0XeXe)|
zHO&*{xZkS8_BNRRRl*-x-4RKcfQKR>medS&Pft>F)d29LLS2V*E7gK-q*kdfW1MT$
zK{$V(+6>bCOWj0c!RfR}M?Bv>04Ml3K#6t%X}VPTksMqQL$YuUBFz_$lfZR@7~x84
zj|j%PW1^Z;&~J-<&;MUUr+lF3mVqK7kA;zJf0tUWM~$V4)a@52q8g2#7xkE{#1B38
zB4MD%eb<F{#qY&@Cv16|WMT$ROG*J3I-JEAJ398nU6`!mp;I%)CshZ1``-iK2JNTr
z$dT`dk{q`HeR;)>-c9}qO)eKb0LyIg33eM|KF(Mwz6YDuh)=-#E#g&YQagk%)vMPF
zPX1%T+3yl#eW?HXZoviY5nRDufwc7lf-Cu_Kq(BX(@1dFb3T&y8H*GBz6GGct8ovu
zy>2BLJ`o@Ps4K`Zb|dbR_`V=Oay6>#qJcNvdZJ&wzQUcB=176c+zSE?zQ+wE%j+uu
z;eVefDBCC)u82hlkoZDJlHF?1{<Luxl7pi_>}et!#3~ofct2e{j|p5R8j(_^IH;3a
zE?z{;HR1vYu~ysz;nxZOtC*b+MSN#cHR20gpS5Bi8dooR85zDIj>j0l<01`dd@a%g
zNPQ!^qmm}EDUH-65dq3y7PHZfU&VPKen&j(N$Re6i2HS>x^g6`S?XFZQnS?><npe1
zunnoD>cd1*%hav?No`QW0qsWB85M0(Gx!(69jXti-KjQ!i1q5dKvJKoozUq9^$4z*
zFH|cwo={ighC8i3kFK0ie*pW=tN0;SHmS$)1-YgU_8|4EdIT6u(+(w*nxPSpG!a^d
zcBJ0casbmZtzRbcuGD5C+B&TgDX!P9p!%)aN~HghmWFQc*LETH0c`*gjro#u17n!~
zI{II70~;q#A4YQOyTot$VViyiR<0PI`*ny;?UX(ES^Aq1AD22ICoip6?@_V#*cf~4
z?|j)M1rx^R7nNokV*+|-PRcKekHa#1j6E(UE<PqPE<QFfCMmnDxVWG+J14&=+HQ|7
z$j^x$o0}UwW_)2(QE^dTRNk1J{OH(Nd%Qgs@Bja=QPn!|uaSmVeCeyD%3lJJRxy8#
zJiLt40nUG>JB~jf$?sT^onMq&FyY0#?A*x6>?aJ#{{4coaT5x2vL|-Piz<wKsU&;c
znDH+X&&trP=pm(f<4dD+$BZwS6x}PY^yRYRlIXI4;;6E5w7R&sD0))y_?Jsd#^mPF
zqN1p>ywb8#!!;-(>3{A0!>#_tk|2*igG$>!K;_Bk)b$QtVKd&E7*y9BwMI|*b7>M3
zITOa#y`9jll@XL^F+P}Ts}t#qoQ!=#y^U{&G}WCL+TiY#micT_LQqISK}g+-zg=-Q
zj`nY7T<h*uw`bx_C*Q=_<fz!>gxH9nCp`(GVULUH5F4k|HIyF>6?f|@HkeJ~xUuqs
zNut^Ctj-b-jJ)bB)ilr8QJpFF7;<x#YFl9p-JGc=tS~k}tu%fm)oZ2EXG^BoY*cK?
z5=V@SBySsuA7+Uq#tf3Tjjun<QbX4nVKrDZp(cw?IaCv=O0#jZCWMahtPPikLlmWr
z(WADFxMt+lhO05tjRmz~s%fLKgVgBh#+lkM3MjXRtD!Ru`_?e&u~AW)jM(Y!{{==N
Bd&&R+

diff --git a/Debug/Libs/sta-core/src/devices/stm32/subdir.mk b/Debug/Libs/sta-core/src/devices/stm32/subdir.mk
index d19ca1a..e9c1525 100644
--- a/Debug/Libs/sta-core/src/devices/stm32/subdir.mk
+++ b/Debug/Libs/sta-core/src/devices/stm32/subdir.mk
@@ -28,7 +28,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Libs/sta-core/src/devices/stm32/%.o Libs/sta-core/src/devices/stm32/%.su Libs/sta-core/src/devices/stm32/%.cyclo: ../Libs/sta-core/src/devices/stm32/%.cpp Libs/sta-core/src/devices/stm32/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Libs-2f-sta-2d-core-2f-src-2f-devices-2f-stm32
 
diff --git a/Debug/Libs/sta-core/src/devices/template/custom_printable.d b/Debug/Libs/sta-core/src/devices/template/custom_printable.d
index 25c78e3..01c6421 100644
--- a/Debug/Libs/sta-core/src/devices/template/custom_printable.d
+++ b/Debug/Libs/sta-core/src/devices/template/custom_printable.d
@@ -1,6 +1,6 @@
 Libs/sta-core/src/devices/template/custom_printable.o: \
  ../Libs/sta-core/src/devices/template/custom_printable.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/template/custom_printable.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/template/custom_printable.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/template/custom_printable.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/template/custom_printable.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/devices/template/custom_printable.o b/Debug/Libs/sta-core/src/devices/template/custom_printable.o
index 1489f9213b51aa99e0041e67fe3efdb674177304..80d538effe64ce840aae80b013bb98763b6a03fb 100644
GIT binary patch
delta 3087
zcmbu9iE~YN6vuz>z1%C|WsyWQ5=65|5KqDwAw`?S1VPBsL3s^%4T6xRm{GT?TFa>A
z)}YN;Vyjv*`b>=K5IPJU#?olDg3+o`OPN85PTKy?r+-4<Bxip2{LcBFbH3+$@0op$
z=6#MeagN%x-3GKf8Ld>euN+F9O<r4?YxV1@lq<m1M(JNbK!7ro{yP*S_Mr|kR74j%
zrr68)pS6>-%Oy6sv)C?p=4%i`eFnmEBEJa`&!ZHvEqF3?bwf=~6`Q9cEkmtLl!yJK
zMTW^a640F#n2p`?iuliQo7P^=*YIEJCg=R_VwdYl47Dmr?B5=-xjn^x8ZY)D=Q}ji
zD?~io)3mkJDtZ|R&<B7{i<9eOxmKkKVnb=p1yBvm)zNfpxZLJb($!neSBXsMDCbRX
zu~FPUW`NVgyQnpuR_qj~+v-gVy8<PAncjn;G9txJqM);foOfbp1<83UJd^-An0Agb
zQ5x;90sic(5}D9P?D|l#H>q+T9(se8M}wU#fYPuL9VB#Wtk~N?2Se^&k`EB`C&?p-
z9NtzUm!OXEQF5L`%nDTVBRCc0HZ#&kOg$TJd!UQWk(Q)A17bhD?<8mm$y=aoE_DA2
zAB$MY6Q^V?LU?ru?-cRJiJV8%*(|azkwd_#fR#bqHldfFLX@R}s*(k+4}FEuN)yv)
zH0^&u=zN-+25GevD*`SBPdM>4*vm|>P<*2y2xnOCeK`9W{41Tr-$pM~zXM?uo{nlg
zY^dzNP^P&@nJ~)u9Fo>V{ABjs89uVn#0_HhFyAq51He4Mnto%LQM8rH0A=F0)cffI
z8s1)PG<#|R^a3`FJvFn}^T6dp``1j_O8l)}l6w|q1O>}^MTFR`6pkUwBIX)sk61?%
zgIOOk@h;@HmsjTzbDv;;<usQAfy0o}YCtapNP!&ec(P)g;+aT8x0%wQ%tjDwR@1;6
z@dvFZv4}*Ai{I(dNr7}G2nMu<FIFa7j6nyLNlb<qKPRggy8*T$h=0t2N-47tR(gd>
z)-n8b_(u|dw2hr=##&hv8%KB7p?5MRTM*qBFjNi)nM|`o3&&6uY;+UxKX5w`=ojRc
z@m?fA`wo`7hxklrKhA=lGDe`A(8+v8%IzjI-WtKaAJW!FAYuqT4}_nI9S|OvEUn}*
zWf@;VKk?tfVmd;;hrb8*B*?`qcLnwk+|*J1I^vDCP(UnmH&f<03NL4`gDFtJtRIs$
z5%nCPmHBLa5{+KKf0C8$WA2x%doH^_#Yl@_-AlU%c`pvTp|lE$?yn2%7~#g>73C$;
zwAbztm}2EHQa($+1jpkUrUn(>gp}@d{x*<npraEpPrz(IRR2Kqai%lL9YH^Jbl%F0
z%Za%S+V?Ch(M>`loUOBO1P-zsP?HEXafswOp)ts&nReIn5y^z&T83$Wi2I1GC-z;a
zuScUR7;iE3wNUFg{^=0i7t)Kt?9~O(?L2(KqHF0om9#9oAt*lLJWXr_bR_Xk`$16W
z;0jv53h7_kQEgMK20j+&V7;EK5olp7CF|fapR9G<UZB<nvRc{yGU|?IGq?HVj^VZ%
z))&*~BDT>jKx7=9Dt3legsFyyyX4`ezBW~|A$G8Rv291|j!rh!1kJ9g8j;f!I9sXt
zFjar}p1@#h;B2XG+Ej-rpBo~W<$8EieTQc^QoKar-H<W_b{iR>Ua#9!)eM$_7^Yb~
z+|UoEx<r|QfpV^;%zGX=pU@4N>Y3J%M%O=6t)#8h`U9ll^xUQz!vF?SS%&8B>bVVd
z1l2m+64R=Y4fP8QS%@UkWy!^8)>NzYXR5oJ15?eUd^+U^=ulHF*K0CW4l<vCZ1eQ3
zp)z?DR>E8(tBKM})ECMK`b$~}*(^46pS%KLr-h&J2XQ*0MgO~$<B9Ea4;<<#s`6D<
zd8U?B&a9~NWLHeBndO^ZUF8|~W?`<UYEH>ipSRjqGRu?o`smcGlFCx=sEX2>nLckp
z#XHsWN-BN+EAFx=|AP2jr(K^B>u*Y2>Iy9=%+B)WjwvY2$@Y5V()`6KBZGpAvd4Od
zy)nE{d;0gY{ps86ZRs8Sg?+C&hyC9kJlVb}HD&(S`d7MK!}1F40})aFTNy*lz>Ku?
z)U^J6`uLNFE{kv^*ar*dISTER!ZD7w>;>8`w9jgL&W<kX>1efcisFrlnyh+zR#CjO
h?NEDNQIcb{eWa+n<3szFwukJX;_i;8c3N@Ae*qMwqx=8>

delta 3084
zcmbW1`BPP87{}ks<sP_lWp@Kq4B3<`fk=Tkm_h=f<iNGT)GHuiDq<|@FL}bmNGH=y
zQd*NMHcnU*FlM8fqh-`!t`#OOX{n7l=HNa<)BAk>gc$wKx$pZd-|zQ%&gpHlb+y?x
zMBAD-j(R%a{xGFRwcC`sIcVd8Jag7arR=_TKc)YCeSMWf>3=sO1#jsfhng@#u+tDc
zpCEWIK+tX%EEq00f|C`xh(m3m!q-$d=qo4PiGq<)g4MdaLzTD%3w5OFQ0=kuV=rmp
z!Sb9=(N-EP1<wqX^KNcaLge{8=Y6B(xjbI*Q?10Iw#EtGO%{wDE4VL4a4*l-Ae0m+
zC!13=n(7U>%%RXKimr{8>q5C!YeowOK`xd;??dhfNJoXrZ8<F;QKyH<vLSN5*(I33
z?Pzo#BR-a1rBJaFeO%^fQg{1Hc(a~^LuG^unl!wGeXGXENwrgO8$N8plljm&fT9%W
zw^RP+6A~Hmq~N9?!Jp~Ug%1H#D}>++CWYoCNl@4z!6s&9F!_;~yPf1KM4lnJfXMs-
z68{F<(K1+`cM;P@?j!0{lG}@<HK<;Iw|)rwINX%9dz3f<_f~>hN#2TOA7HnGVQd5Y
zd?agSfZz@m?>h0<h<ppuFEPmRL}pWGBd$#6_CEV^E>M}eL=&4G2d_Y=gfK&0P2WaP
zXba>PV%i~^EvH-}Cq<}l2k)Xjjd$QM8_~sZ6S)12`c7{B^g#7HV9?mh*1DKb752_R
zjf*`9rcI?y2>nR>Jm#H^A35yAMPd%1?+~|-$4UHWjOkCrG}5>T0abEts#jAbC^STH
z7;}oG@f}Lv!kb_=_$U;g$M#-S_7neWlH~4YGn@nEd2N{BHX4VJ)j-UCrhc1o<l&!L
zhT<+Z`3APz;w1ShwwFOJ7X!0crFSTL!dGH)!4|S2edOdt2pQ;e&}KaqPGWu=Z$vP&
zk7E$!CKs3B_z;e%C@7%l9&~3h#Yv>ChTIW`vXQJp@GIP!M*KAfv<8PtaV058$aQl5
zE$7w5AMmr>MwIzF&GKM(0ek1sG7^iLaA+|eq@rdQUxFGYx|#T2xSd1khvZiINlP1&
zb}`&N#LuJVHw<VnB>Y{3&f_zZXPq@-%$2;yW5D&4n1tfvl-Pq}8-_=)ABm`(%ew6$
z{wOY{vdEV?j|T5ka|Od~13U3%2i<S8yc10p@DW9OY4d;$-^%tz(x3sYZ<6*J+jAHy
zE13FRh~DA+EF=2~-B024E6n~nlIn5Y3*9s9&6h4Lt;3@Jcm0QijpKYIn>P*8jn)|d
zL~|mNRx|WdcwCB@2Db1Z{NrIhpOPD}BZ8PgaO+{IvM{9&bq2Ww@acqkKN^q0{12*~
zVPK^$5>De;r*+YPqIr>3nT9pdEXe~xLs*;B(A~sGqymc%A*Kf-24c{3zH`OYImLP$
zLf%ep1F-ma&R@ppTux?DbLj|l?BvH0p3lKL8;TxlpED-xC?vWmS__G6>u=}qfrU)9
z2h+Q)!2=Rai;qP&uD6m^z%EqKatB_z$!g}-MaO!w`kDV0`p#f7Loq9f+ZJ4Jgy%}8
zG0IoomLRv_e7zBd$`7^6kH`AjPzm~#GE|y%a=;MNUwdY#*-pWJz8<UbY@PPQQ0e&H
zh_H4%Ytp0*bu&V$<pm0E)#45HFDIX{ir>@tJf@W4?qLLcuE%YtFEH^rmZ8<;$3Oaq
zp&rsE(_fxHqD@`0JYUs>40TWMkgl%(47CngP5J|5sCup2P(=ucXH}Znxr<u2L$$EA
zHkZWo>&gyw1&6k?B;j^bE@m*MliE^4#cD!^T0;8-+RxUZhWb#C$xv0iI*VA_Df-r-
zvUnA`aPBap>C@Y$FO<W1M<@ioCm7TwuR!oI@h3D;3sSfBf4j2%WmUQ|)2C)8d+I7{
z>yj(VYL_fe&Z(?hTwk*+xxU6-zp&C>T~o6(d3jCk;<{yJ6_q+>sk^?iuD-70lB;TP
z*8j`ZJ<1!ZI&x$3eFl1RW_q8Ul3(KWMyIEB?227y?|3FL&l#FOqa;1eJ2jyqF}fl;
zCMLSD&}vED-cdNd$0x+=EiTEK>dh-EF3HW&i76e6(rfM3`q-$BOBo)+e?m%zJ0&A6
zr6X%{bC@mI`mT7nZL&3~q{x<My{&PfbwT5P%k3F!>$7GShgnNJ!H${QrB<ua6XSC~
f+uH4kvt?SxJ@K|>);*2etl_ib9hYZHh)(zqZ04gS

diff --git a/Debug/Libs/sta-core/src/devices/template/delay.d b/Debug/Libs/sta-core/src/devices/template/delay.d
index b6e7b3f..20c7137 100644
--- a/Debug/Libs/sta-core/src/devices/template/delay.d
+++ b/Debug/Libs/sta-core/src/devices/template/delay.d
@@ -1,6 +1,6 @@
 Libs/sta-core/src/devices/template/delay.o: \
  ../Libs/sta-core/src/devices/template/delay.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/template/delay.hpp \
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/template/delay.hpp \
  ../Core/Inc/sta/config.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/devices/template/delay.hpp:
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/devices/template/delay.hpp:
 ../Core/Inc/sta/config.hpp:
diff --git a/Debug/Libs/sta-core/src/devices/template/delay.o b/Debug/Libs/sta-core/src/devices/template/delay.o
index e99f32d2a40d67e0bbad0eb69eef3dfac26b8c49..d8fc9b3c315a1e10e52584fcb09ec37563911f04 100644
GIT binary patch
delta 3113
zcmbuBi&K<U7{<@C>?h#5$W2iZfmH;R7EmeFMi4Z-fD%jUG|sv%>jf_ui=htF7aC=G
z#m~EunmUH*WUZ5qVmVz*Gc{31vystJvbbbgS(B2T^K1GG+JTqDd*0jgywCT+x&x*?
z2TbeYOeMAP&vf3_Lx}jO&O)qAsx8UWOA>`JhnYJG`3VdR6c!=BR`pW$Ba^bNy_H>}
zDZ3wki%hnN(*eo~Zf}RE^Ru#uMYyQoCbBwEc|J^5_9C7z+1(=YQj`sok-9~s^i#i-
zlNQ`no!erREj24U7+V>w&U?5G4pZly_<ix}9Nu5qj6TXbBp!?S(V=YmK>T)Pk8ysV
zf#Pk-vpP*$T~sp5FU<HHMWf=>b(XpoT3=-^leRZOo%2DQ%h10u$^*{r)Tsl;<8CT)
zjaAvB+@1!&JK@T6i2AYAG?D|XdNiqXgVf~;xd%y2q_R(F_ywb_9iTkv!OAX%hfGR#
zW1K@EddN!B;bbnkwp11WR;aRP=yC-fqN$e6fDiQU>N=Qmtu!9a0vafN0YW#D{5ml=
zNlu7TSvEGGhdR<gokz@!SatgWb*7Sgn9AcpJq2#tl2pvgk-GYEj1m)>y_BFANv?#l
z2uQ49lW~1j{86y_km4+aS4X^?$V?P*A4U9$jJs1O3|2aTRL$*qo6u#sq0G{gxh}E8
z1E7)B<n3NUdotWKNUNaPA9!N%w7^F`S^GhMt*6SZq1tMe`#CW?fO?SIZ=_#71Anon
zB2?Rh4UHtU3N)*j+Cm#IXg*<3J97OLR$|b^C1U1+emS>4Kc$B7v8HCg^y5La0AP^v
z>!LJW1+`G(euO%2hvb*Ajc{|Ay&hr2(a^pglvmj6*+DAHk23ydh#A!J(%3@Q9AfH_
z^H;3nH2mocK>P}FTaFlO!M%V7rI_JDATSjvIVrjUm4sl^$hrwPgBhp+lsCfESj(s|
zm(}cq=~Il}%4#}vsJ_IEZOquei%M%IA)hyviO^q3i$p%7puL8yENmuhwZhYN7BqtR
znXnQcs%pN6e<}WUD!kgsNYP^SULY93bdAt!r{#7iS`S01aF7U^IlKwV*ytMKw{sg#
z=@aA*;<>N^sR}0QiEpCjW)`%GA<kLRWD&2C6yvgH*Au|;C1Wk4#0g}0juLesJ_X@l
zBex7t79zJg;*Y{&2<%?QABo*YWi!it8e0!Ho9VuTYR7fR)WE$fKv8!AdFHU!BpM6^
zYZYmOQO`o8Itg)2W6*v0Ut?tj0BB^b833LI`q{AVWZXA-E)H0sbUYLtTp!du;tqZ9
zz<MLE1FJD0C|P#^DG8C(!*Ky%@=@U#NVyBhVoJ`2j!<IG(#u1&s}Q}JE={x@$vnAC
z{s4?_VjAFK3%l*G@)lVJXQf6{&~UvK$~u7Ej3gQewIG{QjJuJ&H9_%MhMNKrs}aUE
zJkzODNX!i2*`e<^z1;Y-A^LYbFHrM*EEl`^WhRTRVCs9|uoxc)+ar%K#6pU;6MsF*
zXb+C*GL^L+0{&#9TS&6Ln72hO5ByfrLJ>m*i(U$u!^o=Qb|1~AlGT9##xY$Yt7(9(
zFmB_ay_!LNtm6l>l9@S0S*MhQCT!uj?#XLSv<E7iWPBUaT{mR1Ci+M<XkrU`3WPe3
zBt#RB(AHy+r9;{{IkYC$(*9YSYLFw*YvNrz^N2rAV;xp*v5u1fcth@66B7XTeLt0(
z_3vNoosv>b_;5XuJJy7oHnSY+?2!X$qD6{GR+k@5Op-D3KRNjZ(nN*Ct%*ng+(0YS
z5o{xm!fs^yPzqKPpP`|vFci;N-v#LEB9S#!NX2U6q~t&oX|#`_{dI|36XWHYG|?NK
zk3zQ@^420uJPRI}+rnyuT%x=Xmf&VJf^CJep}W*G&~>HaCwyz1jJPeo&BAoU@LGpu
zIf{MWa-YNFE}vKCbL5tJ7R~oAsPH+SpX|(Y_!hc7URQ<JJ>QX&U67LFE-!KAmz6A<
z=XDj8&8(<&mwWwJtjXQ{!|izi#`4S<|E7L5=FlQ%ZjLK&Vv%!nuFDmd=8sN}3hq*z
zTj&}yYOGUwGKLr<(|3iBEpTQGapfd=lH)vac6;1}3H}@Dj{?U0-;o@--WiK#`F|R^
z&Fp_WbBY#}nU<cCmXVt3e>}1(!qjFgDXKKZ825`Nn)({q&WWa6qgL7t#x3VS(_N!W
wvE4FSa<<hNT5LBp8B>e<n-Yv_X{Q+V(ylNr7Wa>CC=_C^B=WzH)B>M>02f1`HUIzs

delta 3102
zcmbW3i*t-;6vp4pW<SY_-Q0twAz4X;L?kqIsS>#mDWcgmOvSpTR1nRkf<`~8rY?2s
z=Qdi(pk+{()s9ga)J$E9s!LnbCaUNtqtzDE7S;Fs{0H6HoO$=W=klEAJl{9jyu-Fk
zf7{y1mM3>>ex{XD$#Kn<IvTfpTz_*~no{;Cdo!g!p`oG5q4f9gQ)2hp#I{HhJHrsW
zuD#fsI@zI)hloviTI^M)*j~DbL;0z&k_vM|#j_+s?4Njwba#h(K1*zrjx-(0n<_tQ
zNDGgYvx}k=?Q-sd-QH5po4E~-lJf@qE0g8iE?w-fHe&PjJPy^AE!N!;zent9&f5W$
z>=Mu19BoZC87!y4*pH&mww3EVxmNAliM>GDu@pI11Fj0tcYzX0%d6B`#~9rcByvfF
z*poy)WPtV2;yFkCBx+h2ArYpF)T%JKoUiwwsfiVv4DyXYo76!(x#41`!^31sb_33C
zCc4i`yl}D@u%VqLexY0JA-e2^hkMk_2Vk~Iq2f#lx<%uPL^(H6`U=x6BKZK34M0hW
zlNcA9?~gjB#EYk%n72^P*VGwI?mjA)GW8(1J%O60#hQ|KfD*5QeIh}#NUnpj9+3DE
zeDrN6@%x!IfE33gyhFs#C$bbp#6a|4$T)#IU0}t{?I!ec#-&VMt{+$;!F8S;{=zi6
zn!Y_o=yQOpfV5RKYel&vJn6(Q#GYdM2oyh$YKvK};`ReZz0z7LpVEH)4BTN)C8+j3
z^!A3{JIwkqZ5*_zWSV^d^&r<Pu#$)-&J#0>`Q~zat&_9~u%_z_GaOjy43H^)Q;o`%
zpqrHVJx0zAG`6t2;N}K<-3i1ZXy3<_7uoBPOvzdX^nU>{hB}oregFtRF*A|gG1hSt
zM$J+*xdFKy=F!=tdDrFGUn$_65SWIPycAs#Dlty%6taGVn=SxqV#>xSiJ4A?t&qP8
zrf&fK7OUxDa&dymegb293rS0%=p5cyHbUdjK^jlQIB0*JtUT;Xu+@h6vn*&NZ3<u|
z*)28K<9{E&oA}wytSlqZ97eNT(4B)`4=o#@s2YYk!$Bg`yuzEHnvE_Y{ylEHQo4cM
zOrDEd<krK)HsTd}TFrv?Gsfu%G+EAT#A#hHJmygL9fF+>E0;+-O$m#Mzku)`o;++!
z*^f<I#P5eiCqh1n--$g#%~X~<9J>u}R?~eC)f!F6xk}NEAwu0($g_^UI%qJES?fvj
zp`JI9Y8m3H0O$$)t614o25`f49s@66`jN2i1@3m9iyaYAS_(yn-VIBLG4Nl5^}EQR
zlhq+C!%StQ5iETh91micfvE69@Q1TQA0;P1hntw&)SO4PSV;Mj>6&QU8$3fn{s%Lz
z2l+vGSi^2}p1fmLz}Y)iQ&>;)IO}c$HP?~EK|&v(yo119$=)2PLTeQpm<bWP0QwJ}
zUepP&hE<GL^ko0^nu|XlqMJebP-+$@F~=r;tmV81)Hc!*tWU!|u{!~=nWC|PNQk#?
zhbOkkW39Uxe})zB%rJetEtWe4=~B|%h#{4pGa)m9tQu~wJy|YUj}X8J8mF<EJG^s$
zCAR?D=KwUoI)1iGm%phtKuf|<u4r7p>1#vX4i%eZopmOdpXg*mwb5!Y)J0w&X;3#-
z6Jn?bXv@Q7UPv3DK^y8Q?R&YTO`V?JP~YI0MEssC@dshW4!wsN;BCEcLoHyi+ti$8
z@?)=-hN0HtdaQSBsL`~k$d>aw4aiV8wTN_e{V`OTj?w?WXdM`;R?lsySO$2^BQgrX
z9_LY*jco60!5ZpwH1sVD6`+z!A*NiUv8JtBv4(o2IWSZX?W1Y`P|t0s3Qe`4dZY8c
z=r&W|I+TrPVFS#qVKt3fZu&ww!oL>?t~bQGH_9^*xk&hl{;aKzxTOE=%68tWjOdY9
z&?DOysH_QOj~!hzsV=*)GEh}pJvF<wI;(a<W!B{C>M7ZE)iqUtsiVhM>X<26wUvR|
zK=5)zM*MUCFIV>%^V;}eGfzoK3t!<7e{tUuuixJ`uWRt-)J687JtI2YI+`12rRJ`;
z7r)@O>f@4w4|6YswD$YUy@dt-{)5ZCMTI&eNBR9FgS=(l7p)^LV}o7tX4$Q>)Wl%0
zyUz%FCZ~H=PWP@k!N@-KF}Cll#pQLjFw5Z`Y>Tvf+IF_KXgk}w=j~`~w32-uM^DYu
wQme%0v7NLg`_dh*K1y}9^2=ka9ll6gq1B*$wfRbo!}rh^>DW3%sV(yBKg|-H%>V!Z

diff --git a/Debug/Libs/sta-core/src/devices/template/subdir.mk b/Debug/Libs/sta-core/src/devices/template/subdir.mk
index 8ae2306..d4687d2 100644
--- a/Debug/Libs/sta-core/src/devices/template/subdir.mk
+++ b/Debug/Libs/sta-core/src/devices/template/subdir.mk
@@ -19,7 +19,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Libs/sta-core/src/devices/template/%.o Libs/sta-core/src/devices/template/%.su Libs/sta-core/src/devices/template/%.cyclo: ../Libs/sta-core/src/devices/template/%.cpp Libs/sta-core/src/devices/template/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Libs-2f-sta-2d-core-2f-src-2f-devices-2f-template
 
diff --git a/Debug/Libs/sta-core/src/mutex.d b/Debug/Libs/sta-core/src/mutex.d
index 7ba9d63..29ae8d2 100644
--- a/Debug/Libs/sta-core/src/mutex.d
+++ b/Debug/Libs/sta-core/src/mutex.d
@@ -1,3 +1,3 @@
 Libs/sta-core/src/mutex.o: ../Libs/sta-core/src/mutex.cpp \
- C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp
-C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include/sta/mutex.hpp:
+ /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp
+/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include/sta/mutex.hpp:
diff --git a/Debug/Libs/sta-core/src/mutex.o b/Debug/Libs/sta-core/src/mutex.o
index 59a7679af43d88af35ca721ab261cdd7acea1b51..faa65045fcc2835d65f915976289a3eab103e2f8 100644
GIT binary patch
delta 3204
zcmbuBi&K<U7{<@p_4~NEF5q$z(_q~cQDMQnMrOuZS||pTiOI6zmNwWHD^^y1M(UV3
zr5(ze#>vUTFtW?0*=;PQvDB0rr|jyKrkO?MBx4$5o%3tzABdTKIeX4~-uHQ)_c;vT
zcFNP8a$UacSnprmci2E7{7dqLXfIs<+8jAodF5oeT+Ni($!e4k(&KGcjWSp6Q>)}f
zu3dSmLk^a;YOl<bL3L6_LMF?VojrT7{*^9rr4W1cr%QjN&n1NDvoEMm24*iBY7%rM
zAx`SgZ~rCqKa#5+aXly<mFv!vPGX|_3pw)K1wvS2oGxIAmJ3ZhW1Bc&kco3WCSK|`
z@mV#=%5l2L@9AT9z8_)YWHQ@w&3Zwxi7PD=>xP+loV6%1>vbBsB@R<<3(?|MYKGa5
z5i_aW?Ke9W!%e)KoaO?v9^;gnUr{ZECH4hO>|vcpn^j)3(>B_~4L}KuH0!r$wl3eS
z=Wu%9BD0>xtxKqr>N7iQ0A1VPtS8ViPpfK)3`Dsz2L|U+<vgj^gDz=^NgAPIc8)WF
z#xlk1tk!d}L{p}Tt+Y9VW}U!lC+BdwIsIUOiEmOrE6uEL1#|~W2=3NG{wSw^(j~pf
zWL`tHS3tGgq0k26%~_OYK-CPl2Tt3$oC$Ov`fVihrBsu@8?GJMX8jp;&T_X5aCdVz
zNd7K{bq9*3LhM+kW3G)!GI0;s50mr*AihD^5X#Ml#|Z{;iqhZrHMhRwZXr8c$c*EI
zM#gt9PQ8yhZKxjL^n`v{mbf@gIQmz0Az#2X6*dJqW@jkl@KUH1aQhKW&}=Q`9%d&B
z`wxjzC_M+`pT#i&26q{!xxg*vbf(^SEa9W^(|EoDdEZ2?PT2UFWixHoO9Sf%@;5N=
zI`nA46XW}t)92uKhSMTyW};IDciU(jN8SBqe2!RsvAH&j=TwFDUed(%vn2k8Hdiov
zH-_3lxk6aZ0_acJ>NvK#2@n$iVUrmG#2RuwX6gmJoq6czw8J<H%Vc1mL-76!+2erQ
zlng|y)Pw1g5q23~*~PHtGwD_cjDTM`Q{O~|<A{F%0!JXWkU`(&aFEA=hXxP9pq`@5
zKxwAgJQ&yVA`UT>Phhr|C@Gptbkp)6l%7PDrI`0U2A4sd?F{Z*l3JEJ$a$P*s{v8Y
zq&LvA1c~;e&~7vcQTkg96~mr?A#y1@?X)Z=rwyZRM)o5aM!$CQ<JA1aXLiN{;wlfR
zJH2MBUJdOVa9(B*)x?1$Rl)cyC4PkQ)d=26p@pz~AZRMQLraTlEAfYq{3|&fj+2%#
z+*gSaURE#pU*MZA2N@^AdnisG3xi7br_-PluHSL(5D)TUth$4#&jaXX<ZNYRN8vpK
zrC($Ay-?bQ>N^>F7Iivukn{zZ9aPtPa(q=7Y9-by1NCF-9#5eY`G+x_(rCOT&1kR<
z8}_0~G~Mj%rsh%fSU^sUW_xi%6s0Y?Oy=%p0IdP~6HMS&pbtTaV$872!)tyU(WDCY
zD@z)NHm&N8emTx2nB9V((lGLuK<|e4d$g%S{HIWQGV1;UnVqQBL**6ZY=K@MG;ZN<
z$sz1~iuGv-xQJQY%2Y|-fbSFn^-}XfFkGi5c?Wx!f-?gQC-T(-?{Mb@{x*z8r-NKm
zIINVGJt#MqYuh*-OS84yDg?v|8m~p6Nk|jobSoOaNX|!SU)#sbBv5SPIelu2mj3u`
zgdUbHBKq~&VzKh4<v3sIBwIY5Vxo@`ypM`|v>vu-=IIo{>;p7Aph4T>0@^==J3rU#
zZPAULPU5_78u!)z;#pz|kK<?j+D-Q_>EdVf2OPfa)?aM#25lZoHtS=wN$AVA_{MMI
zc->4_*FUz{3#>==fNZfz^R~tN8jz;MgXltb!T3JIqeHaDwg_pGmguiRSYihznc=Q8
z2dlt-gc4;MkS(^;eh@LHQ*E)35)WbF=PA*m!CB%N26~u3v*#I2nI59pr$277QMINQ
zULL$I9&L&T8zN1Ov3M{PYiM2+y=`$kST(z5S}=Zlq#+t!9E~grmQR^kR32%XAD$7L
z-`p4tSI2H%d}pL7n)p3^V|HSH!Piz=bxo)|Jgu_2W@;!L&M!^06^(NzQc73a>g$ps
zwRwDE!1S3l<Hm%`hc^`FH{=Hb`4tr+9KN!mM&%9kCzej=a8>?aIKfc#rsi98Ro!Y<
zO_iEbl$oe0`!pqaV(I9j(s3mviPEXBXQp&$1zg%_?<P*oiMi#^Dl)H9o>s5u*sEk+
zrOPv2Rn;w#jcQL_rCgzM!<DjCE!43?y%8QMyVS98K&PhE7g#rHVP98c>jN&|R8?C)
rOx~dGuP<<UYSmW#WvBY2zCbrPtK%r;j}#0TRjdE=(7yQh=ilYuA`Z~Z

delta 3169
zcmbW3i&NB96vyvxm){RTSQZvoQ4A0j5plyuC|Zz0QK^7pK1voMeCryI>?Oa335On5
zbWO9#N907la%u%N#~Lkdw9K09Ibj;UlNoigq%rE=Pc!`iIkSh$x!-fn_k7Q}xW64V
zP8~E}PBva^PHF00*;j~^FOr0~BffdpETcraj9lY;ImL+Y_3SVqj0o2Wx!6cB4#<_p
zK!-P3Za4ZH@5`e`k}*hLGAi;l$`K#m&|m#<iv&Z6BkFTpeGHF72oZ9?r*8Vj9~z_q
zDw7bG)aS~7fS9Dd@+HT!#&<HonPhwy9P9kS$jD9<!W6fu1g6+=i?)AQ+MY<)_JIg(
z$2+w>E^jxzb_DqAA=>lfP;D3D=}ge)vf<h`n%Zs{tnE3@zbk5{*r%wQ;w0Hxu@i_2
zkJkPGHkQl<1GH!P5N+GRY)aGTp>~%3@qm)T6sZHX{grbPWmdYh=Zz8Cu7XNJhCc73
z*o9<$F5-5u63G;WM7@%#&*2_zk3xEOj6PRVG7jp|h_cH|2R*2g&b5S{AHEGTV0rD~
z6gI+iiY7G|Q&h)ldzms_XtoDhTfm%j>)R0WoF#u;l=duybO@Pe5?f63o!nlfij}F6
zcarTrSnap_Xx9ns+&F!{#(?S>ZZeW?Be;Z;Vd%FW<j!!7KTNL|<Mr7CW}sSIQ_O{2
zfLI^+j~LcG6csdfHrCeAQK8zV!2Kkk7=k+x_8CN;K_7VxA`x<Ddh4ju#Fm0T4{`&f
zKVf`NIW%Skd3wk{h1)!CM@9)-UDva`>F_F`n}@wROx03$F3`&<`g{!0GAMS2bT8s*
zp?j04#dN=>pT>8yF{uphNiYe}UBvAa<+n`{M&Va))d3Tb_XFh0p_|8<WgTUj)#Efp
z2l%zjyPc(OU?;L8_3fAR_XoGB<cvk9Xkt4lynzuP)8n&6{YV{F%yXK`>V;Cc1F6rU
zjm=!UN!L!gQo1aL=xNsKC)VmANK`_?0+~b9(_juW^)%j28~WKB={S#xPGJolX`0Xs
z1YZETO}(_|E>`I}OV<lw>)Dl?$o?>sUQGkj>2D%aUqgmeFrV-unxMXbLATjVC5{UR
z1)isa^#rt`L><N22y29#57|GZvj*%e)OrNl&47An=_OQog5}+fe>{02LH-#k>%$Z6
zuPIg!iHS^lEhU?f=wlQ*j0QP$bBcuuu%3S-au%KwlpF}=Z5C}Evj4(xw}AhQoHsmL
z(N(l@cLdNqF73Ks4(gq1cQJ^UvDJXKvWDHH_?eFHMeu_p^3&zxKAj;*Nt0}i>_-^*
z@!VFiN#F9O!Wr>i>`m|?Y+IU*>^}M)#3qlXgH}Y#r9c<Go+iw}c`w23OnnYS7vTSf
zk&UB)=TLeVvoEEw&8WVIq37|iFM5%58=dvYk_fM71q;>4>PfhF$tNSy?HTm+Cp|?`
zxHU>^@Gfh34OOb#+H;tko#-(i%<B{zK(-c?o<NmcV&8&L8`Q5rbQqWc2r-;x*cZWT
zKF?ztCVi3PLKD&EBl$?A*Iq+s^Vp{%6di%o1*AJbnXP!5QF<-vW~eV7rf{QHGK&5L
zrj_=5cp40iIW|JutDLitAQy^x@X3{-u2j!?1R6`uGB~^<Z+G=~ErVw?9P(1+eAf{B
zP5w5FK&K;wNjB_3N?u2~62dlfTTQVBqS7I;lfo~c&=W|L!>t32cYygE?PrH*>IuWO
zovLmv(GcU*zYJBwvP6Y?eU?}#Q=+`~R|;f_HDTHovptC^8hJ$NVTn4P&JsFHLbERv
zX-mwcd<)wdr@FU97wdG1&FiFaA*w9qaa<NUXBXAIG&YIR_x|_)=d0=$OLSA_RW*A{
zoTbbb6>N#o1GLRn#Z-3n&k{$W)uaYwiA}0+OBiamEU}RXaU9uyXFWb=M<*+dEs?L9
zG)0UeVG0*ZGTB+CFIK`mi4>114J^?{`9$oes&7lICPh0d{0=D|Q{+t1!a)0>To0qk
zQbQC6)W<2LT<uQ3ZDNjZdQDYzjjytzdhv2!epSt)+Q2ejZ6LFDepTj@KwznFd7yex
z&9aKhDur2^SzA?8TNC`ty*_^Y|BF>M9;%xcT$k2i2AeWRI%QsVW^muFjh0Lv6DOBs
z2c36KDwXMdQ-ZU`Y<EQa{nJYGC;AJErj-`t`~AsT!TZKt3+pvHYiwrL*il)*f`Z+#
zVJ)g7hgzKWpgB9>RNvL><`fyH<RN7*$hfj1$BjZcx9m}4rtByyGM33qf06ODT%qi1
z@|ZuvI3%wYcw|JmTfzI6r<qfgSUcoB<*AOp^X1a=!DfDe5aqIDjz?}UcROy(k{>GP
kX5}13<V_X%y^O3#Gy4<@u^->03b)y3w)&PKo69`^05Dj{L;wH)

diff --git a/Debug/Libs/sta-core/src/subdir.mk b/Debug/Libs/sta-core/src/subdir.mk
index 35ccd6f..6ec0f6d 100644
--- a/Debug/Libs/sta-core/src/subdir.mk
+++ b/Debug/Libs/sta-core/src/subdir.mk
@@ -16,7 +16,7 @@ CPP_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Libs/sta-core/src/%.o Libs/sta-core/src/%.su Libs/sta-core/src/%.cyclo: ../Libs/sta-core/src/%.cpp Libs/sta-core/src/subdir.mk
-	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/Libs/sta-core/include" -I"C:/Users/carlw/Desktop/to-the-moon/workspace/can-tests/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
+	arm-none-eabi-g++ "$<" -mcpu=cortex-m4 -std=gnu++14 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32F407xx -c -I../Core/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc -I../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32F4xx/Include -I../Drivers/CMSIS/Include -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/Libs/sta-core/include" -I"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/App/Inc" -O0 -ffunction-sections -fdata-sections -fno-exceptions -fno-rtti -fno-use-cxa-atexit -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -o "$@"
 
 clean: clean-Libs-2f-sta-2d-core-2f-src
 
diff --git a/Debug/can-tests.elf b/Debug/can-tests.elf
deleted file mode 100644
index 9ec10584ce5f7c0d98c0e52d2cacf28ece01ae4b..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 1218972
zcmeFa3v^UPwl`i?=kz(JA4xh%hjbp0PQue5hJXSFH6)>VgqMKI0BQ$<bdVXNpd!&R
zIy&NO6yE|WI*wOobX3$C5fMim-#S5^VFVqcqoU}HK~Ms%<ooTabCO2A-@WUu_5Igf
z>t9*)>DpDhcJ2CAo!Ygls*8)qPl<ERnfE8yU`EuVe&&qCchk)|jG4?glEs*Tv?5k0
z)0uiYU~wKC${2lYDTKS}f~Xkcoe%=_u_y+qB;SpT;X6jL*C5eLCtCk$1T+E~0gZr0
zKqH_L&<JP*Gy)m{jetf#BcKt`2xtT}0vZ90fJQ(gpb^jrXaqC@8Uc-fMnEH=5zq)|
z1T+E~0gZr0KqH_L&<JP*Gy)m{jetf#BcKt`2xtT}0vZ90fJQ(gpb^jrXaqC@8Uc-f
zMnEH=5zq)|1T+E~0gZr0KqH_L&<JP*Gy)m{jetf#BcKt`2xtT}0vZ90fJQ(gpb^jr
zXaqC@8Uc-fMnEH=5zq)|1T+E~0gZr0KqH_L&<JP*Gy)m{jetf#BcKt`2xtT}0vZ90
zfJQ(gpb^jrXaqC@8Uc-fMnEH=5zq)|1T+E~0gZr0KqH_L&<JP*Gy)m{jetf#BcKt`
z2xtT}0vZ90fJQ(gpb^jrXaqC@8Uc-fMnEH=5zq)|1T+E~0gZr0KqH_L&<JP*Gy)m{
zjetf#BcKt`2xtT}0vZ90fJQ(gpb^jrXaqC@8Uc-fMnEH=5zq)|1T+E~0gZr0KqH_L
z&<JP*Gy)m{jetf#BcKt`2xtT}0vZ90fJQ(gpb^jrXaqC@8Uc-fMnEH=5zq)|1T+E~
z0gZr0KqH_L&<JP*Gy)m{jetf#BcKt`2xtT}0vZ90fJQ(gpb^jrXaqC@8Uc;K|JMkJ
z*rR^tjKSvwe8%I`fX|8ed|#7O5Vy#UUxx2X@Zkad`JZAy_<DK6Pxz*kuNbk>Y{-4o
zocQow*2c@rTf&<|jKzrWkqYKGPZ$kFj~bH<neJ?+_%PBbZPv!g8`%(N3maU#WqN1#
zaC|CRXUoQi_Bf%RerCSGI<2nvy3CIEJ`?5UBP|n-{H$|=b7w}}jAzAJ#pG>Q)!r0e
z^v;HZm+q~5R2($E-MS|x?y89$6kp}nt*e>7yLej3!E3($W9rbJvQTC!`~2G7b}di&
zI<Kz{yi@$S5PVPfsJ71HORlf2`KsU&F=j!1PT{>9Hlz-9W~Rbr^}9tqOZmS3jpQ~>
zwx_$Qt<%2bH{doeX{r~aYj*RRrXp6_@6mT_SosT|vAWHlc3yFHt@92W#ybDi#!3<A
zbK(^H*uh`yVM8Wu`(3Sg>(W~GRae_(g^NBn1drv%*{~1W!8zgmU1DSRKd3&eqNelu
zwyO$JhY6^|Azr#6wf}27l@}`u)$V4snX(p+tc7n+_h|9v^^o~$+xWPu!TwI$twCmr
z9lCEkajF`KH}4zIzS`6lj^F!vrdhMwS98~{KkbRxSJ#vsw7;FQ+X(p%@_n&`_TKLZ
z!Aa$HPoxfXkq-V;^rYfY{cc~qlgb1t;voNu9ps%sDcjl8eQaCjsy0IB^0xc;2&bvO
zspyUkkEago^`~;{$L}`ljZ|ijF2<hjqnARLCGUvpruw?wPTj9l;%3t6!P=MNzmK2%
z)~xoEAARI=M>HYMJZSHKrRKGo{5s&YJQ`=EgelsaQ@h8Y$$*1=&mA>K)Om<Knvxjg
zWrxP?_KjoE_}W_Yps|mT;2do^`lvUrtv&J`F}ksSQqc_?z)$#Q*Y4)EzEtL()o4ZP
zBZO|BH&@q2-Vw(wsGnIlem5I8de`uHW!%{{CjQAM;dttkiQ^x5bK~d2S@d}*lUM(G
z*ZBDET@~@0cGbkU?P`y=?xLJkyPSAn7xkLjT`d#XmbNDz`nu0W>|y)sKFfanb>6aQ
z!VB5x#RbW5Ty%~(fUproXxaglnzM|T6}EWcDc>9_TjS=-S>}`#E>kIyW%lG7J~h}c
z@Uize!rl|+o}^I+zTWi`-o3Ub*u$)I{z29m>0+I4;PW$l)_0i`yZ1lZJ$+x>iN-|U
zdEJ3SyV#b&^gf%SrtOKF9)ZTtsj`ffl3pJlwD*JzR#uppn^=?Bktl3r<(m>^4Mj^!
zC)ahh&B|>mLD)cOQ({w+mA58}8;X)elk4`i)#WA%5H=8MO|&LOdG!Kbo>~wtuU-fl
z3zfdSv-yC5cb&Jh&JVk?%2NqeUX3zZsT_P#jk0{`!aH9}d7Q6zu`M%3ZH~8XW?R^3
zQNvmobY~CuX~>^kn8<4gm(5M&HZWk9gXfM!7|+7SEIj8nW>EON5QWbR;JM~JKb||z
zvnl?3i{j5WC$i4r2ffm6L1}H9B}PrEoa}}iloM{4zVCyoxrt1Yk|2pY5<!yE=x+$2
zB!}V~N#c%1AF!VCohR|9QX=X=xKAOOt0e9}M0!X=(V2sRG&gb=4n){M$U_>fa3-~a
zKpI*BX~H0+fncHtbRp7Aq(x<#X;dewldOzdJ_2nn=t5{#D#2a64d6{!7sNAA`!^0v
z-`9auw3=)UO10e9D2V&OvH1|&5=(Cb^dIJ+4?WHvKIac?3;Gpnd;Axu7xjv8!@Q+g
zvRBM%%0Srb6{M>lJ;-r;ljZg%sq2;y<e%DQw$l4V?cDanRgkwLVeg3?)+bw&MahE6
zH`Wf_M!g61U78PhY*}too|MOyRX0{Qqc<h8fkhZ;glDG2g&V0vDmi`Mv$I+oh1=&0
z^i_X(>jElA)i#dW4py~AACP^H{nz?br0cVfmAm>N^k3;?;0;LE#yL!z?(cfE*+TuN
zM;~B+Xcx7>fA(ZsJVc4>Kc(c@alP!N#Ah|U)wQb9hxThRo<pcNAKK+#tmFNzk?k21
zGbd$EX62&e?K#iSFh@Key{7iSTfxb}DXg4#<R;9jdumf}b?@KaEjqV$b?<-pJG3ej
zF@|@5<`WMNWe$DchL7w!&;c!!%s{DVNxWG_$pH1Bg}Dg_VVlB;H)5=_?z=2J9Y}rQ
z5G#+WabYaA&!w`z<TMl}a~g_P6vU_RTe<A9)SkT?QhWEp%5+Y3-$`Dc+0mNJstEj@
zm0gfj^OW-MtjVp(T#QJpgF~vL+8_F15*jn{QP>o%D2$`uCUfh}$>8omm~A1xn_NE3
zl9JK5hd$dP<Da-p>W6o>f^XyH|AG!TcEu`pZeSH++lplO{$C!VzFnB4XKg1Jg^BL{
zfA8)}<aBiJf4f`6Q^~gq0~Nt{T9fmZ0H><f<lF_VNnhD7x?(Y2{%6Q5O3q8tsKF{e
zZts;<)+wZ{4X&);|Ch4v>X9W#);7rcIj?Z&yGOq^$h0M&(zvXXVxZd(IBR~uNinU-
zwLjpD{eY8VT9Z4!$63}H{vKzojDda^e_v1Mdz@vR6azhfz-j(~lVVzvYtSM)lZADV
z-b~MV&9%D?j_>5$euPM%Zbu_pwTxPW%hsTN8FqV6+v8Wrb{_*tMafohQmdzyr!M3b
zMtkZ)f!X0RZHpR^()?BztHO9CTAR0au`)%M@4Ikj8eLY6)-Mv!L-K%XHabfTUWU2T
z-c*9}6qluvJL?K-h@%+%JDXWW`8G-krKN-@C0SrXLUQefW0NzR3m|i1Rb5wAxH`F3
zrW7UDY@iYXbr&>G9I=xH>*vC*>}=*0Wj*qgCL|5x^8Z!Z&L5Sw7TWoxG&4;*vkZL;
z8dIDq!K4y;cq3`N5to<Z6mNuhm+%T($|XEhe6fdV55}zA>S&ekQ(GCmPxS5=_gW%3
z2k_oo^|tbgVR#ROY-egwulK9>l^s&=>$l(iSMO^M$}Q@BUm=rvP_I5{e^(#XliD7?
z68)$vu`#hSQ4K35d(rtR$XJ`))R;nVMsK>9def6_o6slP7P5-KHVQF>d@|HFi&bD=
zi1eaNqth^`&xs2Aos=3;L`s%;X9ovPYig>Kg^5j&&MGptZ9+M7eVfo@4kY~&&FF|C
z9;`1+WOZypEp{;CEUf!6j#RQBxhYxL+}f=2m?KDT(M7x>ds~X|lkpf)M-(LwCbN?m
z>(5E&ZB5!EFz#BdNekaaCfYLTqman0TbVSga#n=nGT&~7H;1$`zJ6gDy}5>)PxR#D
zJ^6kt*Yn7gu92&c>@8k>8LWqkSB}EVa_P1*MMvZPdwP(1`@h#}=cZ71wAMw`T6^0z
z0pUy_Q3Q0URaiwIP;!iSOW1`HiqQL2s{OsxzazB}2p6G6a_fsA!xR{`P=9K>ki@t*
zbza8Sy#b^bCW7C~x6>)_Ow_g}=O(@{Pk?{NVX@R!MrRhuX-wy)_@cm$4JiMI@u4+{
zpX<d#SL5q<mlY*<Y^Y8awzyJyVhaP+Nj~Du4L_0+s!oa@PsyxCn}0vgKb93HtCQxB
z#1|#06yJ}hpcL!JQ&5U6Q>f(}*>XFQDYQ^+XH4vXRitoXvll~t)DQbe?<mvu_~ovJ
zpjoSHAI?dw<Q1YlwNg}MZL3B(mbAV*We-Uud~)<qJ%Z-6(Rie%&oRu!mBdzX+nDo)
z8g?c(C7w!7|EAl>t=U8^DK;f@>*_kUEW}J=#HNHfc~kN&%xBW1V6I1V9us+s0wgDG
zMkCW`zHh|GBvNPJdcdy4XtT2#Z5f(GR1SZ0L$LlAU93FNL9x!H)CK4-hFPsr3eRKd
zGyV@)2hA<h$GDWzy)o6ib&qYB6@#~!n6amt%@J0Gcqi3tR3i^&&X~VdZE7a#w*#XO
zS-mwiwEooE%n|nv#)@D~Ze99234GkSBJ6ebV|&^z=5O)xtd0O?fV_HEBCC|<gx&jp
z)$Jp%E@3v<Wrdg-_RI>mggc<CD}!ck6S^_~llH#tiC;=oXp~MZBmKJf&+lH*xH7ph
zxuTh5iukPuvMRIV(Rla%Q;{#~=2Np*lJ-cqfmCk>sxVoR7y}K+QzjoxdCO;hz{^sy
z=B<s@=y5BXb8D&_kHt8<rnaVY?j_aIx)=tp@U?qkQBjG0BrQhsJZ8vQ!_K;=kaH7c
zpcf;SutZGVCd^fyYNl~y9xRMkRxkIwWRV}UO`&w?%|Ua7d9t4x75VM07}coVepuR?
zA1Q4|PhNpJOR9N?)0%XuW_6WSk__sFYgyL!w8op}ru1s=<=og@*Hsp71v)>jgVYl>
z_<pSml^*+QMv%pPyp7(>1bo@k$rGuY)pV-s*V4N;Z*r=6ts_Rv>?(J)G=89EYjP%h
z)(W6;BEARUdj`Hs@I4*h1^AwZ?_7LO#dik2r{LShcLTopHXByQDGzm6c%OXbPKSvR
z#V9vB1bi?KpM{klY!;n{xPjeRqgvwVNlL4yn#XmO$Eq9F0)gu0^wu->wdFF{p{JUw
zWouVW-qd_!qLRjnA8@k6I0u3At;E2Fc|XPp#Cm1+1?MbUq4*Kbw!=7cz?qv!HS-ZE
zv~*U*#ot{2dw85%dTpt@{xh1_z?ZC{H7r_#U?F_M_(brD;!}*zSYD&nBUU7W@z%E7
zcxy}R3es!kDzZ#QN9(FWlS1jEkT+^l4)povRAS|-R5G`w&`c#Uj;spS6k;@?JZYmO
z#u9qtSKuvCe%;~^skbRF?A-QMz}@H!Vf+fUU+#vTikxki0z2SuJoa^4R&d+TfscW4
zm{rU}i_e3kQ{W-iLejh>I8Ly(od=F{sqc-*P4w+h@#~KYZEHdNSrlKMoA@chOI@B|
zM>DA8<Z_wg41^a^7+gwzZhQCs-*$~|bl_Xw*CpcB&2JSpRq%I=a{I%1;8xmnwnvbD
zi_3SzVSIZ(II)*+8+zatRd4bb7q(A!>&hyE?Gt+HUA(Q{tvAha#!-H(V_|lRTJKD9
ztPJw<7eA;*e0gV=fV}3NY}BOOx?tj1)OjaxiM5Yx;24d&_cyp&O>ngmQv3TqsOXW}
z**^F%Ndu&$ypH~~ZU+fRxDo~)CgF+?sJAM;I;G7uIvwbE47CjWk3Q{rt_A@&zjavt
z#UBJ4=AGr{Z!hYg701HFq5XTiM>l469NPaSEC8WR^KPSj#s_LWXF_dT=7ic+Jvn!~
zC7URjb>2$j&$*Yl>tzfx0@#4WMW8R7Tqjp%SGsAmUWk>~bI+$bV9kV8M7J$Rcp3Ez
zte_m)|1k7$pvUie^q^J`eXyh_M<;5!7Oi1zYicMuYavR&3fkggw7}Y=5A(^>5qlb9
zvEI0NKEm@{j$p?eP^U~Tm;5IoJR4!+QZv!K_CxzyP<jBRFLg^F_tmN@jBn83)s9KX
zp>X>*`rV=Zb6wt(f57`h$ML<q+h{iJ+cpLWj7E91PL1-=Qmpgtwvj!3Z$8xu-p;sf
z!`&7+!bM`>VMtujF-W#Q19sH@JDSlCm(ZI(Z^>Ft-)oo5b9lA#Lv}7HvWn2J8ZgFD
zzdW?R`;fvnb;xUHs@?n!tVSjctW!d2`|J+6N)7H$UG9$#;~w8ZYfLWpw&MtS_}n(e
zgwY+czhDhK!6wue;ccQBBc%>*Pf?5Gt=S3tUy50&(Rl*BLrd1w7H&J3obb)F%W`X0
zCTA|Wf!|n5o|mz&rmD9#Yih}_FgjZnKmuyDrk37DvMkZKnxm-kx6NJ0qV)_l;=R_9
zl-k<HvB@>Hp?4NF9Gj#$_`<YUlJz9&QG^ocjgO%<C`|p^*Zvc<(j4^Aj#)QCD#g<q
z=WCyZ_?d`L)ZLhvfpB?eCu+1dITeUs?Q+s;S3SL(=&|;;2~?&WNeh71#VB!JQefPt
zZv*Kk^x*18`dJ+`)+mi=O>S|=C|QbuQsyN`%2E#P?*pHn`fLu`h}PhG`|R|N3h-lm
zm;7tln%d8|4M?kX=*==0i&$DLVNvB`LG^dq3#in69W!Z+>yuVDLc!mjBU8yUqwz3P
zrnAmcj5<N2&>Sqw2uyl)ei`O%eymDjjUE2Lq5bE5m$nYIg<*}9`c5&{UYWb5dE{r0
zOuru13o}dX)1>gJmisl-9%Qwgii~!rf_-&&8`db>P2jk;V^+hah3a`*$8;LaJ5MlL
z7f$UN*9T+lpO;+gXJyq3RxYSsvUM+tE1l3_q_D$S&QiwS-1@r7>r*1<;DSK>sRaj@
z<kqJaw4TYzHZ>k>-2RzWzWuWRKeT^4)i0hKPc59)akM9~aV2IZkQkWW$$~TE^Wyks
z`0$_bal7AaoWUv2hR*}e!q0<##0z|k>ASDYt=oOu!s)wL<!t!eF&BRB_jzfbv%1~0
zmwm`0@xJlM=K<`SjQ>1{ofR*A`)6$YkoeW2G+wuR^{mqPRU#ZOh)Zn~2NT<|mwjme
zr9GNr<WClb$V=xV=CSI92hXfNlUAQMEfgI-;KsIWIx`xt!Hj?Nr;l9c&S(1XV>K%-
z;^b?6f8ChciT1j>_jh89@}X7MN>9viTU)MvqfLjRO%>m}F5kQ$&6R(gPk9>N+j|0f
z;*DL$$#rP*F&S32#>Q485AFYDsx{dk)NwI-CwC<2S+<YO+>uz3WSv90h{mdpjJ>|L
z5Z*#ja;~B~j}UVut#Z}MTqL^?V{^=vN#DoE()=n${qb4!#}~WyvF%;^DvQwL%lFmH
zpzu3MdKM<JPjBQlQh1Gwp*2~e=DFWHn{(@4?CPqdxFWny<@@@KEA0$%m3uo<f^}~t
zRO&pE-a_Hqn^ihVpCzRiCa-H)Q|oJ2@z)}3ZtLDZrTfLMZ<&Ev(Fhr$)Sb<bea)uV
zbcQb3-t}!ID|@l))5;gSzKCuA?AY;T@rwBB=*C6!#-$c*|Ey1WX*}n1?hJ|7ea_SR
z=gUUj?m5e*?|w;KAHO|b9*=%*7%z5pR93_%$<Rl#HuHeri(P+*>~|sin4DmIXS8}z
zZoC#et&kqUn=_h!xBpo5fndC`0ekS}^ZdoAxzef~Ip0RkkyqBn8%V1rXw|g+vz+pA
zq*Y)NX%+N({`B3iLaVvZ>J@QAd~LigUMO{Wsj?y7AVaUEY4t2*KM&cJN~<PUD@YGR
zt14*qB}UI+JUd<uy*Tu0DiatBUM<|oj6GH27*|_(iTk>i71w(@KMA={L+&t7=Y`OD
z;r7omq4SB+F$*Wf8^*OR^mN|-S?G5^iNDHD#M^q}vJ>O4FnU{!cx`-b^u?}6pm{)|
z^<vlKX}aH!G9E-3M@Zc_El|3r7GNBL?n9ybYN>k$>6i=6OF1-u3z}Dra3<fAGEf`5
zZG!p&-jMn=3F`yA+hO=A5nfYr`R6BkwONmn?nOz1-P(*<FmGHd%5hMe*-?rAkB&@r
z@qa@9+o1n=iTt`W?XQQ-n_|5P^r!KP$?<9##w)h{vw^5VrK~~X2Yq4{a$f_D$~=4<
zfv+5eCBBUkU#zjHk#zfK=KlrXwlsV%>(Ox2;)9EO^Y^=Q60{pfqv^77Qo9(m`v9xu
z)Hg<duWuCbsu3f45biX*eo?)6<>Kw16?-}-pmT!8VySaN>YP4;|ED@{I>YM`sWYhc
z=nbnrW91pW`bK}CZz1%(QtJEt{y^IH_J^#r{=l}_U$>pFMt$lJ%G0D(Vc55`Q^}{W
z8k<TUyr2-_^p(6`zLkfq&5^BO&(OXvt--Cp>Rl@&v?6csE_#c!32LmTxf-oE?drB&
z&SSC4OQZO82Pnl|YuYk4Ef39rXclpC%3Ir_b+c<wo?6Y`lq_m>Dy(+~mK9Da#5t1(
zy1Vy3){R*B**5kI<|VPtY|u(o^@30b(QC}?hTNK`k~buu+nbHG`&6TeG?KGvK`J>X
zNjvcNo+w`l+p|iZ{|Ift477abhG@J}u9CImtjo9fF!pVUrwi?d1mmf5QYhizN?KPt
zwEtwe)9dAyCr-+Tc2F4yR-zP9jS{N9O{v`^vPvy0n`zyfEYupTi??DQudroP^O_LF
zZo-Ts8#6qtge{?!?ZRbGEy1%frKodh&q(Qa{S&G^2s=7cb7+6I)Fk58qc~0}T&9@r
zZnThd>~gG7Qrlg>S*<5@Vg0ZW??mdH-1w$*4zA3NuVuOQJDD@$AoiYV7qJL){v7OY
zk#`A-(8lfu>VOz%idnLX*^wB4`V=MCuyNmft2}^YPKefu;L9{q-g(%UlR1&6m+Q?m
zE|RxXa_vB<=%T_nayD*SNyzdt_z2i9DnuL3OJ2}SwZ8m7@4BYiJwr`e4zB2}#Y)tI
z*3N+Q0@C1s>}$=)=k9j7UdDfx54BFqH}wbkXuU4l0jzp(qY}wGrhP#N{nL}MQI<UP
z0CX8a8f8@c^Bs)do*wQ>I>{^iQF#Zkqe0Tv;K_0NM@in4%*1Y9ugnjm%-(e)Z}oUg
z!YDhUlvaJe#yO7_Np}_5eXldovwGiX?`;=98tWVuE9#B-jkRoB%LJo~7aiEeSj!U`
zQ!}PC72O+V1MjQ#ZwpQhO<|qUE-%Knt!48`U1s%d6ZkRz-sOe9+I26+1n+Y{!d*|W
zEnQDLPv04DnUEgl!Z3Z7?F<`s)Rg80%Z^&Myz$6|XPvX?sAcCYJgRBYdCdzKQRGiY
zR2{Xj@n^#pwzM!-H*Q+2YFK4$tfldSrDruZ#g;X%TohZhV&S4iO^cc^`*r_FHbnc0
zq_7wN&>)-}9?YEA@!5X_bFzmp=Y4$g5uT1u9>$6ae8$N!!^`#G|DONX?u$9tAL7ip
z5}*HmPR*$i&<JP*Gy)m{jetf#BcKt`2xtT}0vZ90fJQ(gpb^jrXaqC@8Uc-fMnEH=
z5zq)|1T+E~0gZr0KqH_L&<JP*Gy)m{jetf#BcKt`2xtT}0vZ90fJQ(gpb^jrXaqC@
z8Uc-fMnEH=5zq)|1T+E~0gZr0KqH_L&<JP*Gy)m{jetf#BcKt`2xtT}0vZ90fJQ(g
zpb^jrXaqC@8Uc-fMnEH=5zq)|1T+E~0gZr0KqH_L&<JP*Gy)m{jetf#BcKt`2xtT}
z0vZ90fJQ(gpb^jrXaqC@8Uc-fMnEH=5zq)|1T+E~0gZr0KqH_L&<JP*Gy)m{jetf#
zBcKt`2xtT}0vZ90fJQ(gpb^jrXaqC@8Uc-fMnEH=5zq)|1T+E~0gZr0KqH_L&<JP*
zGy)m{jetf#BcKt`2xtT}0vZ90fJQ(gpb^jrXaqC@8Uc-fMnEH=5zq)|1T+E~0gZr0
zKqH_L&<JP*Gy)m{jetf#BcKt`2xtT}0vZ90fJQ(g@V^Fu{`*)M%5Z$f9fe2ZqQ(Wy
zj1NH2H){NmQ<;@vPxXs{m19PD9?v(TypR|1VqV54)YTmu8$4m!NwL{yowamX?2NO{
ziOrflbwpKc`0!yPhMlu$>F{Ayl~p4uj~+he$l+r~4j-ZthQ|<FRXJ*S73*|R4C5wB
zV|mXEFj(o<KUi$@o1BFxD(%n5trp8-e9~=<i6Qw%Ac?QN++d<2ItgJPcdBj-GG1`G
zpNUb?`4lC5)n7P_H~$$?V+ziaQT7Y1;JS6O&BWB`r4(iQPDkzekb4m|z2IgUWxu?}
zWIS)YkBP<6`zgxtrB*`Gl~*FFxnPrwvY)zEFy8v2$;2=FN`*d%B6(FmQi!*_U@@`2
zA8Epm`vgkgQ$i~6h3mlohkjHxf9Ayi6Hk^<p?qgD#KcSes5JiGZyY9GDWPKcpW=}D
zw*nbIzXo~#Q7Ge&i$Ufm1#z@oAJf<Tv*nDxxjo3lr-eU3l+Uz>?nmwhz-2^ohLfZ_
z0GAQXJr3c}Qt<F1fMvvTXHepqK*{JISxDjA0go{>_dE($02iY&awWn!cT=W(pkj>9
zT}O!*0uEzr<Y5YLg`P%Tq>Ok@gPz93ykQhRAqEYmMvkTM+fdM$nKzZf7XddjFZvwi
z{U>lU`xLxE;d6kSSyZrt!Y2SXv$zmX#uouMv$WtV3O@_n%(B8m6n+o5nS%-fB=ddX
zW)3dwL*dhMY-Wz=NBHnlDLk@-fZ@*^3^Mb$5*fdl!pFyC{1eannK?nlKThF^D*n?a
zkoUwAiT^GN&x{fNegfka!I(q2Z59ao{{G?nCJP#jS+gh2WWIN@A3_Q<2EXZJz8#V<
zjZ5zUu~QO`G2{{u?@A)X_(#a?d(R-55cbjQx7lnC37bj6K6ZuOKc6$-C$6w1LqY6v
zg-y)?@u?^5FUalt%*cm;faB}j{3>Htld$;A;mo&32?J5Zd|xSHjBf#tZ?Dk=w)~jk
zJIIfmWV7e-YFbn4ph2pitd2Ex7Km>pVOq0^_)ZdzVZCiI-yunajJw|f(JhH^#-#Bx
zfjs4pWQ<1^F2m7`+SxOikm2I!>ghq|Gk8BLF=l>t3R;`Ljc^+`=iDvuf`0_!5pJ#p
zpT+lqXy*m-sVLv(vKS`J<F}(dq&!oYzX7A4Q!_cjZ2D7x1!PJ{m=7Z*C{x11JnJKy
zg=9)Zm>ZFjAycBlY(Yw<(oUFLk&?xqLgU1QnG!Y&bJNFIjZi&-G?hK!6y~QcK*~xQ
z>C}p(ucW!+r@WGej?^#_k1k?`M*(+VHaBiXd@hY8)|ThWIXez4_S28h^W~pmBxL+~
z#9Gf8rHJx5=J_XvSkWU#*(#5H)SnJ=hWC@%qdvCr{1e_5ZXX%NsAT{0-2gM}UtWW^
z%T5mV(-6EB-1aErBxJ~;T!CWyxXl|Kc8rBC{KnTvJU&ENGUJySA!d)0glT+y2U6-K
z;TX3~_Az^+B+vnfXpltMxV#%0Ov|MzM2tT94zo{`M4oZt--67ZEr~ux<u@Qskpz0K
zVKRHJB%;PWwx8LjN}>Q=6^hvjV-3V*zW<=f2HWl7%Sh2Fw?e?1F$y!|byD>05~_h|
z+?NI7ZzVS)OU%gG2)4hMP>1Z#f`mQ)0AlQa8?|5#u0VY8vgJ+8--ich06cM20#Ty!
zB6<$LnVwY}=s9vOI)pg-9C{ve6+K7YL(efllZj(<C|rF6J;&D4^Y~XN{)7+dIgZ9)
zQF|pl>j+v={|r6jXAtLvpVM>VE%co9dwMol^qkU<o>PyZ=d@|`obflxb>hGAWPO({
zZ)AaBaE8NJznKSs5~orE1>sgyBQk4tJ)Yy|%tr6YJh>4aKQKJ>2vUq8|Kcn#B5yvz
z%v#pm!~!GpNGH=;M8wgOa9C!`biu;G!q9dwT1W{NM@TX=t_=HGuy2G)3o$9P<gx;j
z#omL_3r)<-MJy@BMVP&d3|xT7!6)k!Ji?9ixS3k5wB<<TKR)x0FVVpVA^J#<iItJS
z&`AHaZ~7VK;&phq0v1ycuK^by=c5Iwh!F9Vo1|&*N{H@HlAb{`Uxe=)@fi?%z+m$c
z7`UqtP>igULI#~MKEQZp4#pv;4I=rvU0@kZEIe}<u^6lGZOzWSHNe6}RF1Lw+1Bju
z-ZEHTL_)dxk=E=9#{^kXkTM#p?{8&82p0Lega3{!=!rQ`5{*}w$_}x<8}OhxPYlJ;
z-@E`?5B2w}Igd&69HSyihTE^^Ies;_F==jNj43#UQiPn__|<&Ir1^|7z2Iz0G39*5
zujVj*N6uS{)SLlnG*2*TZeT`pX`WDg6CNhb2h9GF286SILlHC)Fe@XADB=%zgy@0s
zmStRv2PSMp@A7DA5V!Y7wS%rPd=5#ByT*_Rle@-{2#34IkO&xb*BFvK7{h=5lmxkk
zPziDkp%Ua8LM6yGgsvdh5LQ9}4B?mSNRVp;r63ShWCW!kX1Yf30<iUk5j^03OCW=5
z096Lp0LlzO*8mdXaMu755#p`^BqHon2CyFy5udVvl8E}036w;!AR7o1NM*(xWdi?+
za2t1&3ET_f5$-4xXuv$Q^M0NQB-u<j$^;T&3P+hhY8Xd2$^=qMNI1#_Qc74j$^=qM
zL^#R>Qc6@f$^=qMv2c_Lq$ZCEN14D}=l~Na+nzL)ec==qqJ}4BC5?1yKhih7uTWk|
z2U&=krQD;7ST>o!Y<@ptbD}@tmm$T6ImkRNn~8}mjO_CjVfto_o5@a9gd=`}l+zRu
z5>IA^*y)N0`{EFgP(*}f{|&EPBOeCAIfFAr2CTEV3Kk+P+!B5l4zX-SnBqz>=P1Gv
ze}>RpMTC5l>SqEonJ4U<4kAwx5phc}#QG>ADq0{QUlGN=aq*deHoGs%jIj`5OF<Wz
zEK()=tDF!k5Z94*&SWtiQB?gYN&>=|LQPeK$+GjI>NIgAm~vLl7N5eH5%b9|v*1WR
z#bp*Ih&hUIe07*u{zMTW@d;AqDk3bt3xwD_MMT6eLjYS5QQ1RJ71`81ip4&#ou*P^
z;%Xp&x+3}u>Y)jd{UX=~i|t@*R4J8WA8=Wqh>>D5@+?%uXhEH|Nr@gSHUs5FDy2q*
zk>?CW)C=mli<Rh!;t;e>s+1Yx9I!PjVz#&)t+_-Ia|HG2GnMH1q6&?%RHY=uCgl04
zBANts@SiEsNfAZLSt_MPBHp5i<)R-%pRL$dh;yOnIVz=1TnDI@DdIAg{W)s4T+F40
zDgIiV1QX;#!|hk;%!l66rNXAKcIHfWKoMvc%+U`jA_Ss}r4$hcF@k-oh=_=xu<sNR
zW!XpMhS(vo7p)&AJ7H~Ef$|JFT{P5m(R8Pa2_*Q{bWyU}gB~W<H4w*)1*jW0jzQgp
zaSUQ$6=t?#<}}o}8cd46>Mi1*3Fw(I3B__|W+Iz?w6O^Zfv9ujF)(xddc-+L$)N$x
z4G~q6FnJ%efOE7Y99~4kXi0>4jEJ$42=fsa!UUfni3l^tk%UR&eJY~TKm0x_;!Eh@
zA0asy|1}u=$4J8DONkgG35VZ<hVUz?A$~53@GGfd{t&9@uT@0^XH1#G{NwwO@=<2C
zqGA1UQ41;%@i%-+<(*0FQ{D1LQV}!U@*I*n%PsFbba?;Ck_hp4sqmjjBFxNxQ>OW1
zgOnN=HWM?1;Ed*<p-Pg2ahhERRFzEL0v!UXN)GQJLRBfm-y}8{C}#c@I0TLt4y4H@
z3e=xRQ;!qTjLi5wo@gQqEfts`PD4VVGFUmtkNTXBd_mPJjPFI|f~r+a{yM4<^zb_h
z5`rFnCqj*&hu@!3?VyXFR6RIe)+5R<9)y(1k|^evLffFiEygdSLTAd9{(LbJCrM&3
zzne6eCyAlV{FX{hh)can1s5-b&c;S)#*7eHxv>ps3L}D=8Ab~vnMNT>!dk-3q~y=U
z2xQ2jTzM0rXd-ykD9o%lISIjQN+`@YISIjE^&>b;e#7Ms3tr!k`u9jq9z*bkerF-&
zX#NpK<ls#uW07YxAB_Tox0Fr;F_v$j8r&v{8lIwZ*GQtC3nJD@Vj}NLwYgIgQ~1jy
zZM`IBaB@b1_sAK*Z2mh^=iYuazRuxe3Elf7F`rpv1xw7>B$R5?gIUX=nsq#a=49f$
zUr>bX0HLF<L$o11KSO$chV=Xl>G>Jb^D~s^XOia^8fBc03|W*bP#hXNItXaU>kAz(
zn?v=>&^Sq$oV>nJy(An?USDXUBrxkCqCpa2PF`PVS}u)55l&uT=tN26aq{{?vnA1o
zlh+qIMH2a(yuQ#}Nkln$eW6n&QGmG_yuMJvSPvcZq}LZ}znt`>_6)rlqp)hv(Ay<c
z0aG?%=x-%!ks~H?4*k7^3~qmB(QLycr!VwxqaMtG;*4Qf4PyK=K$+paji;eGGQ2V6
zD@yU+i9etNW_a%ey|fv1Zmlh}bVghf5k7$OOp*k~lmV2f!MFwG$Y#nox0X8dC+H|x
zN5eB_+=&eRjREN7rA8*6WyXb&S8fbI>U!f`^vMopo<wr4Ff3%tA_-<KDR6xbb(^eN
zh{$^t?DZKpkIZoK$+)$Q!U~^^+e@jcCf`rl)|QPyN{lxXaYrdl_WSb!<j=UP^idE4
z`7`LQ8F!Z*54OR45vBZEvJK^fp-;wdB-=3lBHo0I|0p>f<yZ1<%JV>39rBFipA+#r
zNsN{+S;j-9^pcI`!>G`QOQ#{var|efZ^mPiI9@ha#ve+lxoVh2*3(*#utna9H480j
zzD}CFWHcdfegtwVa<4+Ie8ynZCjVDRJTfv7#rq5_aK>_HL)AcseJx_t;|7G7RR;5H
z(J-8Q0&os|Zavn+KuFj$kg|xMs`f`ghVo@frw6l0dSo>kEYv2GKB6RgFpD&a%tw;{
zeUoyTnMjfkY9nTmIf*<7mHhvZ=_Qm-4`z{N%dJHV2fnbXDO##b%0Nf*O$#!nQnW0n
zbSI$A+?h*dl-&dncm}tgwwVKf;JRK4#`0U?a6XGD)Rb|oE3y7Z6XQo2ofdOmlYINZ
zm-#;6|0F_Kh}BJfEaWIg;&YT_Bk6O4+Cr>Ous&sO+CRLsFWj{GEPA|~CiDEuji19<
z!EzM3bsdVFEsHGpGw3@<f=)_$z%xLDFSl0snDexZxdeJ=CeSM9^&w2e>WP`(0haUo
z5O~Jw$1m=)4!oq}V&WtnTV;91>PIeS(I?$RnQ)<-@ZiPh&|iX+kN5o&IqShRQkFL8
zx9BnAnj(XZMGKOH{s90hkPiBT81TtKp9N0(yFUjuAw!VMN1GDTLB~b}O}rfCpgU;}
zIyN83L3fmc?xZ>B*l-{R-BAv@qa1WcIp~GTK}TATgO0^}a?p!<9CR$$Hy|Q|I)`-7
zu~NT?BB+!3=|SFF;95Menn3g}kH*qw*z9%C&3BaJBOP>eha{APZtj$Xa?s6pCE+^g
z=6eRogP>jq-Tc@UL=L+7i7SX4baR(0h#YkDQ%?{%=;mhzIp~>=+3TR2dz2vQpqqy|
z=;mI79Q5LtVWv6gW=h&nOf)ddHoujGDIIk4J4q-9-8>`-<)EA0lK3Av=vKOeZlycu
zR=R`UmmG8xYt;1iFkz)T=vKOeZlycuR=R_3r90?Wx`S?|JLp!rgKiz>pv$%=2VM3B
ztWkRox}>p2?K$Y_eT5u!Nn?%LbI>JS#IpWhJLp;eTO4#hH5)nTE;1S9pl78y=<vBW
z`7mH;pZkA-&z+@wZn+o&pL;N@;{Q9JJ4^Z8FQE11Y|gi(0p<PB=k`5kj6i~u=5t$B
z=Mn1<d}!-v<1{2>M(km);aj?fwl^7-8!zdup`Gp;+Uc&LeVA)#A1^K?sg+LUMKGPx
z?Q@-R<@UMGxN`d(Z;DH9pX-c=IJteUGalyT_BrWppOfzPIq7bnlkWC8>29Bs?)Eu{
zxqVJT{2dBQRGq~e$=v_9-9G1M;!0%5pj^uBbFR7;a~kO;IM<X=SWSbSU-ct6l-uWA
z-;bI^xqZ$J{r-#;<@Px@mE3?l%I$M*DZLkja{HXyB%$0sXN@G3+vlv4gmU|wJ0+pq
zK4-lol-uW|yM0c&+vj+0pG|IGKeOa6l$uQsX1@Z}?3)mjZl80%pa_YT|EP}<{oi-{
z{G*H~kRgL|WfuF#{tEu1bo>12Zl6Eh?enL*eg1T}&!6u0`KRU5%b?so|A~@NZl8a)
zB$V6dKSdJC?eou-gmU}*r%J+g`}_&x8|bLqK7ad8(v#di|C=!itM>H2T|yO5ZlC{e
zC3}!VxqW`m?X!E_KL5XsHDJyx4h)-txw3TodKO{G?Q_>%Oipf}yYAv}a{JtMmylYk
zNq74K>26=(Ft;zzV0?k{WHSZMy$wbF&)mMi6~=sI&L9cW?F%TkFXI73D7P<gGkG5p
zpTMnU6jt~IZZD;(Dz`7Nw(L5jD7P<=?)C-J-M+xxWjBFMxqX3jw=a<H_67c<<OzsY
zZeQSmvfGhIxqX4(NkX}Ofrm=zB~xx+;NjAHkw>|GfyX4F+`fS4_SrOm+v};*)123S
z04*xrzQ9YyQ^*^A4HNSZwxF<V`H;SqO)g!O+`W!>dQvFFY#LK@7a<Rw;9z6%;p;fu
z$H;vYcO(VH>gCM76WqD85qInT4s))Td}n%mw^k^=*&%Y6ZjX>qa+qELD>)-G!5AWE
zWWA5(4&*T9f8wUe_<P*=`6y%s3Rwv*SD9Z?A@5RL1qG!t9q2Z>w;=B1Xpb^o9^c7B
z6rWONPLDFjx&^-PDRX+SGAE}i)7Yy_>?#z(Ypj>x!O1g0>-xOmI&%Zz5=q_Tu0yw+
z<?nXWWc&m-z6Dju#N3?xr)L0+A^oSm5#>L%QBCo8Rv}WdaCpi+)a4%Dat~}NKMBVx
z<iRZE8*%plmhz2E_rQ~T$VnMiA44hPQ_EU~Z~jNC&CeXv9!)GRK+JE?0S$kZ=n&{T
zntJKcpszo<m;M)kxMT)s)PVR;M*2CEd+FOiFRbsS>p{;xzL)+0`Nxm$p;;zP5P`^W
z4AhwtksZiE9_3aPK!2x|F}5=-a2iH>l#Y9}jXX-B&=Cq9q0kWu9mhSkMoynlNC}0M
zP)KDdq>x5lq~jg|BQMfkg@;8C$35fq6N<f)Vt<QA=o<4${t=pzAA+vtQ#|Kk#4>(>
zs7*YFcuf9VqMlZi!~aawW<`aJS(p-=&nPNv)Dg8sQ4wR-#2L(dmgnq40a0F_hkSoh
zY5n<MNy>AI8q9}K+Ezsk<%@}WUQv~NB~gD?)JR@H)C-Cl&D)52QBh-!8Q63)U*b8L
z0?SE8Jy9>K8cj6DVJF6XMNw0DCgppT=L`nt4Bn5Z*LV({-birTpEY0SITJuF=ed;j
zhALqdGiijP>i8}}0Ov~xJCiW;gIh-8w9WxU+7uyE%DohWS-A+?6d_ZN^HNM^9Z4w^
zVN&Cq(wmY|M;iQvKaOabw#-YzVU8(C8<R~r%-iw!m6w#oEIL{eSc>%Oe2SLozxUE@
zX5C5Y!;n5UpQ1yntl8pB45|j2(89(dH9g*4tch9JSyUZ?b`~vcEfVDzw6$nqZ;_}F
zr@ciBn~Ow+Ic+Xl*j*$l!fAKW!uBFjQ3<ex{Y6r{nA85Eg$+hZi}9;rlr8Kq64jqe
z7aLoQ3!&g(PFsu?_82LxlG7feg-u4HMsnI@w6M!a)M!o~w}ov+Dq$?AZAJ_GjFeWx
zX`j);Mk7)6oIG#~JB?JrL{2-67PcBGZ3d^UMhkn5M9t>3*Jxq0k*GPG{BsMtja0&X
zPP>g3wi_ue!D+kE!hR!BO`QC73mcA9LXy*lqlFzuN^3D_kJrMMBT>saZ8=)lb0p3c
zoc0_oY&ud}8>dZ23%ia)UB)uV1G1KjXTT}cz!;=%ab>`Vi6n~!Zv=5wmd_|2%ADY1
zAg%^66h!!8ym$Ov8uHM(__wYbZJxdSr!9>CBSf_kt6ThI(Jk^6vE1K|9Hoj_>Nk;6
zp@^jaRiqrNh$faZA4&W_tZOhL_9x-%SP8ypL~MXX=b<AQdk+zpgN+8ohlsrm<Evyj
z6)X`sXs+#}(!T*O{rwX8?!p<XfNv_*ww9jOsC<mo*4jesy;}G83$b%8-WN-V)>a5@
zwH`(Mh1U3@5c|26RT5$s^HY$@_%P(+ybCdc|GXIcNjxKpcZ=Tz2|m6Rxh(!Kq}u$$
z0{A|>7-2tW$Q9rpK&>D@DTZ}m9tCFxzX++BJPrw2ydDz5{7rCX^EZ&1!|z6FF8>HI
z5nh7Q^LRF%efTJF=JNxPALVC4hXOtl{Dpi9o<)2$N-5??BEBzw2$K8pZFrXO2M`nE
zE0J2tUqIe6eg(qiyd3fU`5z#203QI(fqW@S8N|n;^uc^4o<sPz(BTN40#5~Bfz+Y=
z1U!%ACnIJUzXlSH;!SUHyiyL1UJd6*K$9xI7&RTi8^Jk}k4ITY^ZO8U4F3qJqxg}C
zAI<-Q_%VDSa6XndqO58@2Re-97vgywp9npV=i9-50w0Z-8vYW>8pq!UXDuIva2@{x
zp7neQQpfX^&?nCSg<KQ(b>NxE=RxyH{EtYT%x^^L4Lk?@Q+Nn6r}9_8GmY<jJ%CsB
zX7HSdmQ;3i8B)ZZ209L+<dJdHU8z-e6*CK(bx6C4<5R29qfBL2O=VY2Wmof*T}7I-
ztM1{b3&Gy!cX;Ig5szTlw_nhy7f}N=d<R4h#WFGN*B0{~RFr9-JZ=gO*DA^puR>ej
zw<70haH2m&iTq9&e*zgL!7+#{xEBG=GH8VNkIAO!U|1Z>e@aC)PzA^GY+00z0b3lW
z2vaNrisE=hIbt_*ixU)ulI}!FqK1p15E3jFFY%8Mu*Z>rS6pdgIe-?gdg9I|>NQuK
zjp0hX?n;xzzM+V)xQ2@Ti=rap0?O5{s3;5VMXQNz+*nD)t`f7wotP@g{ID|$F0wNM
zc7`Y%>m>?yhA77-J0oCch*D=*1ndk^>JW>7ogqq{ViB-2M5$ve0(OS5Q|DL&><p!;
zgDe7ehA4HCMZnI4p`bd-B4B4IO`T;Curoxd!z==JhA4HKMZnHb3F<hDfSsW<b)H4Q
z&Jd*zv<TQ4DnXrS5wJ6qrjE1-*cqbKnHB*%LzFtyB4B5z1a+!Kz|K&bI@Tg!XNXeg
zS_JG2m7or`2-q1)Yq81B2-q2-)X^3JJ42l6Y>R-Mp)_^4MZnGwbr}nhoe|50u?MUH
zJAp`R%kyYFF3+5B_sog1Kq}oH)Jf^`pb3`;O}IR0!qq_&$31BBDwtFTr>Ydzi2ob!
zbQ8Y?Z-0RQ1YyokMi?*YbLd&lDC1jX$QX|P>%7*7l*{-OoyvJ#0+aDJ-UsK6ViJ^f
zBp#>1+F_;^%NhgXbQne0xLDSB5Q#jW0aFtT4?-3nzY$UX*%0R^faQY~wxRb1{5(KW
zza<6=uy7x|-zKNiFDk+}0ufb0vLPMENl=Y-zA)4t@`G3dv9a&R8o!4U`2rHX+{TgM
z3mq2o5RT1q6%&&s7{jZAtc%NBZp@u8nC#2LV#ZJ9?32S{PI}#7?;RF%#}q$%J3YoX
z8bkT3s^Tb$k)w+my@x^Mx!zc}o__=W8+&6TlGk_(`ajHRca+6cOkc#@l^#>{6^3<w
zxr&-7nMR{YvcEy}<vd1Ui`7drH=@)lcu0{gnd<=6Dvw;we3zpuoXhh{B@7;X#S76{
z_(?pM`XK!&5BF9Qf7cNqb`l>&8N}+dGUpG$i8-D}jAHfqnKvNg9G<UI&ttv@C^MzE
zc5a;?N6)C^vd^^#n4@A1a!E(?jQbHY7-jNxeg8}~{H~CMPeg1&#&$!CetXep_;;16
zR?At=Ur@_Wkj#|RnnT|C&R#nAPN4jZSDQIfPA=^R-$8LEWY^0$){Xo$)oKY~9YM~c
zMh;N(sNZ0gM}KQZGPX5>d6Y7ezO?hk0c9iu%18#3kqjs!>2uE*FM^1GGLkrAOTUu}
zC?gqBMiOacBz<XTjD4=bB$qP>uOrK##}oKuUV?{BwsZSe6mm}wuSb{(_w+Ckrf^RW
z6X6K=^e_>4dEL{)BoBiAS&e$y?&)FTV8T5;OoS=i)5AnK!aY4q1O&OKhYx`Y;`Hzm
z66Bs9CJrLx>0u)9>zysHqMCb+31G{Ur-$!CkG0*?!^8su<1KzZLxgF&r-zAfgnN3J
zh>&nk4-*j%tJA|2j)c|WVG2jX>g+Iui~D##pP>@Hv%?P~+~%Df-U6cM?C@VewDWxL
z>@bOdx1hEriRd{yOwH1Bc9>Fn&JI&b&)H#0={Y-0DLrS0DW&J^@NYoGytBjaLx&on
zTAnnOEq@Bjpk^m!C5?1yJ<?awnD&r($}4I7TxSW=zx3!L7WIBUa~|Te)mg|0Y?NQx
zCBL#uKKCr-x5yVzHcGPEgBplcnkc_CQGRKnaITQfLi$`2H3&?S-#O|E;+N;F{PLWY
zU!Jq_%X3zKdCtnO&RO~BoE5CqDaepRxq`*c*h*L*LFcTT<3m(0{E`r6)fp!VQ+$kb
zR!+Sn96{%-oQaY^{~)445@A8-tek1NRLh8<b5_oYlE@Qu&dQlBi9UkPSvjXjB45xs
zD`&1GqJqv@Ij2gZ0KFLJtek{#8|gUMS%lx|F_BjWwHC|rnE0?ih%+UD2^poFB?(7d
zi;=}yE{Tx1gNO?x5f)DqaiJt4qMPzuDv7ALgi<b-M6u{o3SyNcVqycOTrG+I%y+^?
zpl&e6LY-jLx%CK)a^hxUzg==LvA!I{I!T!Jr26s9xl0m`Jrln(bMBEu$gZDK$DH3t
zA}pd*#Qn175$3a~h~FD;Q4z(?WAytXRm2mL-7VrtNw`I9l7w5tGm>zN_>&~ULXeKn
zOClngiFip8QRaL10#L6S$Do`7d7{l}57Pl|L3<m{n=uMwT1{Qz?GoxMrl3=a&fiLI
zMB~H+9UXN3Ua}rs{aJ`!0v{b|bN+4Ihn%5Rh%Y3=<lh~j-em@W(7FCx>f`hm$A_<*
z3A4v(&G}sa7z)F}8e{^`_vaBKOrUY?sUfz)AEjO^R-ea0|AKV$3G{+yzZ6Wul*PNm
z6V~h>ri3lWFD%jAaep7mPJhbsKIL)7{l|L6QaKa7a?WSg3(&U|%K+%t`0#af_*bf0
z>OaPlZZ(1lKR)VVGO@@inZo{>9;Ss*fu%7G@tAOAxQA&BBz*}}>=if7WBSq=+ru;g
zE%=W#rez+}Kb+bgrnO*tJ&g%xT$E0)r%8Gj#XX(IwAo{NI!)3JNcvqG(}y0@@0{M+
z4Fc1eG$tEi3Bj5)rWeuGuS{ba>M>oJ#&iL2T9L+dqQ|ttsq3lTA5k3r5X!@e&dAB)
z7N;>i3rW~%=wVvxF`eAYRP-10A<Uc6tc?8(-Gi^IKqE<6o2;R#z}dzMaBa5aOM@K|
z<3UJ%#v@yd7m&KeBbOR~MC!91nKVvE>YqHa$@nMUhUYvoVN?K<tsXfa$Fsq`&gywV
zra>*fZkeajI%~XAX(>MmZMV*vO>dQ0os=)gotFE8oX^ZlA*Z!h&J-zUlP9Oua<N>>
zkC2Qr)8$;0Cg&xn8@J>;CUU)9nH)^yBt&s*w5LzW)qXHe@Z=ms3r+OuwOpz<$rHPb
znO8&mFMP6^{|IAE4g&{Yx55+qg|9kY>=(Ytu2}vrsPlzyF>zwYi}#gcRve%aYjr}F
z@^4=c2q79i&99N=6<^ONfjuu2<-`7(tidb3k*cWqJQGdvimy%;HOIIFvS0J{wD~%;
z>gyi4R2KDySJblNcW8=?Kj_8yc3*zqU5G%t^xG%Do1n)^AoAN@Jth+8y7`_SzxDMX
zxfdn<*4Kk1jf4++1uG;U>M59+_d(5zd&Mr1V(<0DUhF&0MbZeN{7Vj(b7`8KLy$8~
zwFpG8tE8MSJUP>P<Zx1Nns18N&@^Js@Z_N5Ed`1nnzCgFXEEmwm;>>3XVVHNjqo3u
zZp${wru@)6nUc_UvME0_7ptb6&oiW$mFLOSIR>Hsk?A&uLjPmaYv_{Y%g$l^6EC@i
zg~&8ZW^)p{_g1r~^=o9cwtDJpHAi^x5X^t}L@1bF@Jc|3y$f<~P}PD6EI&}S3gJu2
zYTaNSt>iQr{PYmJ$;@642C`$%qW9f=xY%3L#Eyj6WxZl2OR=*&vCBNPRE^K|GM>+}
zrUQ_%re{ZQkom6m@{R4S7I~`2_mt1F%8<{I`POG*o+I;Z_3}BU`!XywC|{sApP2_m
z<A!Y34oG-bHtP^{ZZ!@VJ<VE)0^-JON}^ZtpCBh1Jq`DJh?!)lDFy~o>O7MTw;h+U
z5Y6-~+K~=mK=20lSzajtQKe8`&MexFrk^-_Oe;L5gS^sX%4$YwuW}EhIGFjmyFJEN
zx!Y#TSr#3k&XJ6t!fpLVR*qh2S-BkE(@6-G2zP6<oW<s&cH*x_3B3$P>8vr5I*O>W
zyV0@5c2#r6Y5_61zz?A36-yU*7dkj?HPCJd{S`vJ>-q>*Ah!}sxs~9^tprDIB{*^`
z!I4`Dj@(Lc<W_<sw-Ow^mGJ+ctpxWb8b56%m})D*Pb((Ais(|BfvXi0_x2f|S~2m{
zjWfQf(QAo8t)BR4^~5*5V7-izztDDXnenOBlfG*8#J$PIPpc<ZG?x}y16%R%(=9F5
z(A-NXOv@=&W#lGG?7$=Y3q1Onnfw;+zn^C9XXEEsxA7-w1}=ZYc{|^Xa7>&v7&Av1
z-zL5R&srJ3K6oC&>l8l^(w^xZDgzJh8Hi*1DhChJ9_d{w3lEkdWxZQQkaj`u=2%!n
zAtjS$Fn$lu`4<&$1h*pT*ZeCGoknm03c8n*x>)D3=$n+ZY5xPiAt&7}st^g1k@<>#
z&!a~%ixvk+v`qh!1t?8sl54vp=@)|KEJi`U;pR6W`&{!Rr%N9MooslD??Dt3bgp5O
zRKyf?s^MuF#_xR*-YmnR5S?gvMux*7I?u30h9e<5&G0Pm50OzpXBqw^<NFIb$?%*E
z4;FNeVXF)e6?BT>c^R%0bcW&2GCWcgApC+1j}~-(;YAr98=}(-FY)6cza~Uy7haY+
zPYlt?g;!*FilB1~uktzInIY)Z!fX5-gcGv0U+3o|yj;+Ug*T+kRSGszS;7{?j~o%U
z2#YaZBxl(}5Drj;Oqu1S7%aPvQYb>E{M1Xq50X!%6pE0Ia7AxQ4xLx{3pcW0XZnQq
zi`S4O_r?wg*#YFv*g+XKL$oiJl3}$g_N^e@U?^x$3|nG1B6FXiFPe+sJcv9r?#rfX
zNZM?B#Uz1dXy&w;>{S`YPs7pGUz6dGcn|!q%Wzl>NBkQy91%Z97ygS3N5vS#x65#`
z_$A`E$#6`JL;RaE++X|(@o&lSV3xB5Lf<xxzeBMCdnwAdH(mwh_|5lVURpY9Jl(qC
z-qTVRc82*QaOKRSAfb}pXJ$4bSVci@J_?tAB=vjKyk#YJSSi*qj{(Cd3i{1eC~FJ_
z1Ln8Tr<#I6^J6d^N5PQkL+l9@%rKuva2y3Q&2nU`qhJ>Ew<FpaFIGdv@|O^Aysy^X
zVR&Jv`#%O*#@{$n33ZCf9fm^%&r7R6T1G5I1&mQxkT9O-6{IblS1WuFvL53^(qBJ(
z__|w&^8zeb8;|ipw5fts1(ts+G`L5~Q`-sn-IB|74<F)j6;?vt4d0XZNe|}@yu#zm
zzZsluY4SpFIaR4`X{AmD*V&S5sMKvi57*gzfGf-RhH8H{mu-M!55{Rw74%eMrio=M
zgn({VbdnWOeY1%ga0_KUnagpQ5KwsLwj=roS?nrVES+UECJ^rtd;}2$UJ><)+(C%N
zky!lINLD)fY78I^@_9cO=gd)<)6gF^kP+iXCjC5*{$xZce&&@s30ctR@K=csHXq=C
zW>%)N8DJYon_9*{rM_04w{;N*Z`M-~@Xvv6iEPj=QsHm1M?fP8jAUTi{xTJy8nBfz
zQ8T~X-)oe}nW)UhUY0vOmW|~-EVSYF>o+3!8Mu^6=VYanU%Sn5R@Uh#`PXh^B(p9A
z_`jZ})M^_1AvMKsLY|fp+KjvQNl5D>rDfse%cADIcBscPWI4p~PwYa9SPss5$yp6f
z;}vissmkL$BDw%~E!}9BQ595&ITw6~!Ow5Djl(0>*ai##0;McKdtzw=AHMEul25;j
z<_m1ME={tdfu5ksOURA}`V3lM5v%9Rjs|*_qUU6o$lqkU+GS*;h(#{dl2MA*IK!ou
zvb-6n$^=P<P{%W*4$W{WRhbj)(Mn2_LFn=c_6$!4!WZ-sMbDRIPCBg2$%mEM&|79P
zuE`lDNvgM6>BGHz>NVuU>``8$hkx;m!J_t)Sk;&<HG8>-D{7DMUc*AtBx=_xO<Gvq
z-6gp4uSdRWx4k_%g?)67{Q8p&wnz5Wu~I(v8eJ{+SiM?&iNm)arg5Fn!}X!nBP(xG
z3R@7;no+G(sm(o{f3e2&lzPkv#-5h)CdyJD?csXbs&csw?<#+?e22Zd{5i|V!aH`@
z?6x$$w)e=n%^L2NR?%@PXZ#vV_TzOxQoV)YeQ<Uzux2AdDM7EiYV-@NV-=K3Gaf;s
zx5_$Ue3MOlp-U}i(N5sL!iaX`>!(I^0=^a)SY%UPR6BlcnJ2xdd(h#?i)zG-i~io5
z$=IwY_7>7M65ZcL8fsc>sEtIQdnqIRF49m_WFu`;(fwVdp*9r_wW(;RX|a3RA<}v_
z72V%O`rJDV8z59}FnYg+d=L?t^mrYgtZVVWwo3FV-WOw|ISD_{dzwFqNM?>lc(V+f
z{Cw2y85wr?Y=pPSaEOmW_*oean=@u&sz+HP%)bQj&v7cj!HqK5xM5t~C?iF4b)gJ}
zO|I^fp)iij;w)dTpm4}kx5-dAY^uv-C>-JHE*T0(xw=Y*!o{Y#N#-FG6=RtcMM1ZI
z8Ki+<{Z4H#f=>SuAu!zWh0wE97RbyQQ|nln44b?Po8aYwZY*>7@5kFX`m$LTI2`-~
zB#&DNvB*LUmO&EzJHatfY^Fl+W4Ig87fj5JPgZ5fW1^?HWvJ_CNK?mDx6e>m9T1%>
zdDQXHc`~dHht8K_bu{!;L9M6`hMp$l)v?giWmp{wO-Q}fk<dmNuMUJRkYRNkbfFBZ
z!=O!4raB6`NXDy!pl8UiItIE}%2bCylQLc%0d1CHbpUjU46EaxXG)ps@aIw)ua18H
zREE{T&!0(|>e%O5GQP#6!#FK6td4x1EqT;|&vRtFI_|klhA(4&^>eo}w1WBt+Quiy
z_mLCMd^O=T)b6HCwgz=jvfSOY<nE>=cQ>uH-A!w#@idsC_ywB(D3h@Qx}5|+K_lQ<
zfOaQGP|ys}-6Y3Q&<W7ZBx5KT3edeIV<{MBKDw0zKRx>b;$-o5{VWKy<gFx@x|PI7
zx02WsL^TqE$Dtpk)Ercq?#mG?g6Nkie&l+{q`jxY0?_;mH7`}u8tix}wlDZ#k1gjy
z2z!O+QibVHSt7cHQH+6rS9p~SuU;zUzrt(RgGsDjB9FV`P#g72nvmsgK)1#XCn5GI
zx2}pZ_s8ONk)agyC?AwA=utk(6LeP7IhY1Z+(=N6t`}IttvQfU1>t-hF8@?A*6@K!
z#&W658h(tDagGQAoi%(K!6sIp&2kQ+Qs?t5qUldn|7B0k`FvQqF6Z;(*MkX_3jGB6
zF5uZp&iO1zKbsk-AnZc@__|{;w9EPo<O7t9CaKFnel#^EmJ&nPLB`;o`h>0pIm9Dd
zLbriD!XuYT6!9||l^3&P`ZW%}*NS0!IT|g(*KJ0D5o(Eh%T;;vBXhuW?^sF@tLNBM
z+<mTq<u;Y}A1<}jro!%bsiYl&lm}d@rTD%+$_(1{3!FWE)s9V=R8wbW4`EhC3xW4$
z<7f2Jgq2k&6Sm&%D2q<R&wUH&zEOE#)JXdw#^EbFMw$t8S9#o(9mD-m2K}@jt2cC)
zu)DHjxc3KNO)1Kp6(6?BW2F5+BfK75Mw(4C+}~*|LVO+#&W3ycF77m70gBj-PmoUg
z<9Zf49cqrrrsx2*gGC*g(y~~X4p4{a2LNVuKE+FhK^_C{HYM*PM85zq$L3RfM)6Dh
zMtqxeAoLafGV<fD2KWuH%CO1lFz9PC?3ftDUYEfT*?~7?FwE%~=wD<w!s!rby9`HJ
zCLICY#z#{rFr2v<%Ur{$N>PTB!k*!zuxB_a>={l9dxn$3p5dghXE-VB8P0MP6=MO4
zqM!?09%+!N4CkGs6mDRfg(#}a6hX`gqKZ>x*kqaN{<RTc$$<HL1N}&uKgsHvKMI>%
znLi49=8wXj`J=FB{wVC3KMH&1k6P0+e-!VTKMH&1ZwJDj`J;Hx{8895e-!r2AIbF0
zAH{p-kHVh$BblE0qj=B!QP?wo6!y#?$@I)0#e3$D!k+mfnV$Khc+dP%*fW2`<C#B-
z_sk!KFJqa?{GA5q)j^+)bQsl<=C7}7{_^pDTTdIfjo3R3l!t-9k%xgC_b||52Y_lQ
zS(->knn*{QNJp7S!#x0045lnxban^6g}UgBs?3DC=ZwOpP}iJM*bzn8;&4V&I3(01
zXA}+#b;lWnBg}BGIGaMkamATU1G~E7j2M_uH=I$}6zYOA3OhpGZ${yeP}iGLI4sod
zW)zO}aW6L`g`>=HFE@LDO2Xx4v}!2S<z~dqgu2^|!Z-;A)%~+5><D$U8HGbaU2I0-
zFf-hH&2k|qD-sy?TYUF%?=>S1b*?Eeg2JXy*P2n-5j1xQjG=Hys7uW#42kZYW=)V3
zq659b*X3B&&%MXz9mMCz$3GBae)_qVpNcJ^6PCgEbEzE<5EIE`F**hl+$~4R-1Emf
ztijBnc(piFdID?+Kh}ip!MlSGUzh(1I!;W*G|8CLk!sTgG%>S^!m#T02a;)elO$Vk
z)iVn8Q-S#_A#s}_%b@8uUw0j4r`v3{8KWpnlL9|Aar6LKpEoGi#8U5^X!JTnJ}Dz(
zJ&|RzhC<DU3|R{Y(NU>b!OP%1*O2gBSi+oZWO+le@?g==aLzYEBwMVWZPAZ+&NuQE
zIp3n6@0@S+SL6)q1BhASG0$PS_kx~jKvn88RE69>B4$#0O!+bZz-<-PE}7uCGCLE|
zwo&SqYcG=INVg#S-w<OPQxrMHqMy<FjR-X!P8Ia0^2m{WmMTD2JlF8i`;JM7JO(5a
zWkQ9QFdy?&x@>8>kj?%`UmOLOAe6!0%Ql-X#;P`3YJUi2ri(eM^rS_biYE#eqUCG=
zUCP9F7E<?l7IU>ueDig5xMm<V9^W}mHC|I8Wqi-g*HSnaQr~ltT^bo!#2mW)-s(p5
z6}%6POIY%Z9D{hOn^gaLZmW7F5i{syfWlvr<$_fIDZ@JU_)%)YGB*MvB_}MMN2&=+
ze<((Ooo9lh7#kdF!jh48csED++&RkU&Pcl~I7j*1Im+kGa1Zj*ge6B!SaOulok0^8
zqq%@4EIDez(qBzjz(@XfM%tm?g7x6aNV_;V?@>e)&?Cb=@4E=$yca2!9vL)$F~>$|
z{!)y4UdI5jT$tH;{4K<=e09w$h0R=b%PWPQe09kyg+ux3j#mnYbJZ2E6ppaI>H?Y1
zKosL9kh@4UtoD9E$t)KeCtWgV=Bm3lDcV8dboC~MLkQE&n-mTsOc!rbIFhgK-K21o
z^;K7Z)I)lo;}BzQd=9~&v_J!t1<G(O&~K5Dqb!YNwFl8}L4(rL1f``3N=p+|mL|is
zG=KF(+f{ur#0BM*AwhNRW`=w1rVk1IaJk1D__pazM_lef_%fUBbj0NzM3^?+>4?ic
zh;VH8at|UxwtKk;5n<cC+=GaSEsvv)mwBQ#tzF`B4@xPv=}t#n?m<M%zKjZ;DT)3z
z-RX$SJt$?cO?Nutat|VgvJAS@5tn-mfua%wXK?^;Mo?bv5tMg22IZZOL3yWRP~Pbn
zRChXN(4CIB++zpw=25N^d8eau)jtrn<$=j-N+`^1d0_Ha{Rj@zraK*Rxd(wa(w3(u
zZ|K(tY)9L4rz0-+_$P?bHr?rn%RRmZG1jI#9dWq_5j8g5>4?ich^V*ePDfnsLBvFx
z?sUZE9z;yB=}t#n?m@&1TOQ23ryq5a+4k=UseAho1aoY<(-D_@5HX)+QjZ^K4(ddv
z2t8OP?jK{BALEfhcRJ#74~pnl>>suS@4HQx6Z$J9n#`tKDsV8FM42|-Qh^IkiE!*c
z0CZe<N<>IDp}$TNVVf=|^v5L;vFUO`|0GF78IJsbYA`I6BiqJ*?gj*d@^ZqUyqqv7
zFDDGj%L#+>a>AgzoG>UaCk(2~2{Y(&LjM)UdB~hc5;Ev=LjUzSq)pydM3l(O3H>+U
ziveFYod4D`3af_m-(E^pHEp__(7(3q0i?uix}4B|hrDR8zfG4D`tOp~WuQ%$6Z-Ei
z`#sqH4{cupZ&MZhf97+~z4y(}^Bx}Wndf<mXO<yDDvFe$&?E`Xl7vu%ka<o>sSHUd
z5|TnPCLuGSQHJvWe)m4--gBR)-|zqVfBx^o*=Mi4_F8MNz4qQ~?|tsxrEMNg=*$yn
z<!v5L=)5h^D%w1p(0QlGc95=Y^Ke3EQPE|{Q{Cp_gwDGnQd?My^IkTsCCBFBgwE3J
zb;wiC=HZ0SG7+gS>epGB&H8Pq#ItjW=Nv13HXm15dpw-b*`j}syjdK}e=%78EROZ(
z#cTTIia0$&OJOg-Uu>jO8YO*xWz1%^G$Qk}NEh0r0=DlZZlNgj{z^EZLP8sP&{XD(
zK9tg~<3n)5PGsmDA1<l{PC+hp`dH-BdG<x;_{w~Tj}YL9dw;wz3e3X;v#R2ZXD<qi
zT?Hu%tOuRTag>~Y{Lo&V-pzJtU5=|SX|)cVM-i{a#j$SS?gR#a*0s1eV)CcN%v&A*
zn;~vI-MzO`G2Wq=*k3cpV%*~&woC{v1Qc~9VAvAT7K^YWu32%B!V*dCClY$7y+ru1
zHb{isBo&2gN}_bt<3p@C6c&}m(W$^-2zEG99=WVC1}uec4#zc?<r$!q$zKJ7^s2Z5
zUeRYGw>ljMW=PakaSbGDZ-YOZULBXhBzk)B8-STm0eof(pHT8p;a2GRQR6e?a#;N+
zd4Sb1J1)P+GGR;kurfsCDJz)O@bV0a%`?=OX9Y;M7kRpgJdb#J+Q-%Q^SRrXrx{F)
z$9!P2Ci2Yi@|29tQ`(njCh9j{<S8xk?DX=)$JOxjNsQ*nz74kX7i&z}B=Xco6$?H8
z6|T-g>*JQZ6fuqNcoU{^IjnC6I#d~B8UWV<%72>%kZx`o5mwtgR#!Y$ePdVwJU7a!
zg=>XPW33QKE~|E~6}ES+u(fN2G<Z>>>tR!tDAw2k4nZTLL_FhC@DT@E#+W<M1S5Ui
znwMNo4FxBC+$y?L*@a*Nr-Yi@2{mu@)O<>+84U>#*#Lz+XT4&_Y8c=to;>i*-C}o(
zEjEzcV)u51>FXBzVXz1<M5|dA_S#I2=q_G_Y@*tig++IPOEq57x5EaPh1;^f(8tYw
zN$0l@%femQM)h$sUlNUKML3RmVF{w@*sAM<+?M@qSZB+|of|L7kNv6bw~;DJxX06Y
zY{deMJHb2~>gblReQXJV<d(3TTf!c02{HGG*ia$_6RZw+%8adCfKNnOHFa4vjAaER
zmsM+*RXdkei`+JJ$Yb+xjHv>AJ0x*!=mXD&aQ1184FS!yp;gj`XiTmVEvFI1(?An<
zqf$nP#W;niG7$gO>07<(8y&9ac2%PGMu*$T-oCG>ywTzNS$W#HK1zWr=*W6Stl*#^
zqhtOpte{u;Hc6(b-Ul5-ukgLHaWvEmmSglW`qlcl&tB4dL!5`g4VX+@*W*R}E{Ptk
zifQPUL{;<)yMs!sT?70iP~4uQn_Cq)X4^lg0LiV2hux~^?N&vP+*Q%vV-ss!0Pl;k
zY3;IU5z7WhE}Ql)n~p9Uw%vqPC}9rtttb=lU!C5JO5>=J6Rzm>vi+g7`eAp}9v}vh
z24Qy)>8m76K{7YM6{V&i@w`VOBV5fR!GWismj_?vHU)>nuvU1eqQyRt=(0T=s?I$6
zxYu72jE;u9(JImqG7?<vpANabT&!9Ez5o$i?YDQ;(k@mlKyuY`pR1N`u39?!+T1XY
z)ftafY?}kPGf-Ss4FxM2dMqzsxx8Aqyjr`wn)-PC>G3-6@rrGD0B`YlaU64*p*M;#
zE1(Hx?B4}98nR#~I(p&s2+v3u@LwTY8h4MFMh<Xw)QH>2Cwsgm<l+T1m)C5M*L;uH
zbT;yYAZ+6sQO|{hZA|j&`I}ITZETNJvy#vWJ^EsiXR63EBgwUm#UU~9Q^CSEmP9f|
zY@-HnMZuPPN{qD)fI~oWE9@rj9+2Gnx|zEd8E8ND*u>fe!2P0ZZZe(&$z_wrc&;Qq
z0DtbqP>|KbKe<Y_nYv(OdNJfW)dQ5oSE1xSq5PZ=@h=De)#(YzE@q#Q+llrLJdMWQ
zHxy~e14Xo;G=RQJ;x}lNHA0cjn8T|&y@f}oM(9@Ai}n_dZmkF%CGjjWCg;xhvX?PA
z)WV-J)t7MyB)AleaC}y9OipnnzZ7gPGv@Lpv{0V@8o(#P)2-W^coRT!m7bS3k=PSX
z=fT_p&GQ607<5aLOQ4g%JOu*yS!Dfhfq?X10yTm_>vIcKJ=N9F`rs{jYG_;D0s-tG
z>wgObr2h~oX(Z~JPMc?u4|}pq3Fb&y28hvlO0e~ZK+?wbQ<4^7bRHq{02wwl+RHN{
z*u>4FB=teFf6j;Wk%#nLuxSM8Cm=oQL)z;hJsRPzB&~+dWDQAn*F2>Ag0&-*GSO(-
z_$X!Pb9LG#=s6uqQbpJ&@4&#UR|wwBL#pp7et?oR3Z<*$Lwd|Zs^p_I95QA3kj8pQ
zSy4)5GtlJK+72cvm^We+#OyD_m8!N=k)rG4CJYK}f>d>!NHbmr(sjLP-#{2D%JHJT
z1M@+%o)>*MAjWbp+C%i4t--AyTwT#`zT|{tf6y&5AfU@u0KOF{!g6jh_)tSY6Si}+
z!AJ0;S3MRF(T%KiOzBlm9;B4x@=z~ybb(4RvQ18+G@!N-Dbw@2QttGmY!M?Rz-OaU
z<~eLpN}#z?<~?i)e(Xg@c>KQe_%)62V_gE=87Qt+hI+%~VBataM}%lDzt_ECa;!H@
zj=(S}_|*pD-yXj`9>0b$`~dzs%J1SJ*9AB?DAol4n#=F+L9PpMZIJ5%{4vONF3C^S
z_(92wqiPH@z-yx}+`=97nC;8O3}`O1V;-|p9<#$>rj!?Zq7z_-7rh$o5-IT+a1c`b
z>A0SB#~2|1UK<r+izmd!TtWcN6=H`c#P^;M+aN@Q-@Ry0g5TdBzxFZw0ImQOx6sQy
zejnuG2Q-)88js)S9=}yLX!u``SGyQq08feXn(gtLo{JaITwV)3UQ0Y)^QmAZ{1AGe
zGXZZ7+(UTO^9#B?$C*Gwx95m1ecV^TRl_fVJV!2os{%!+0Sk4m3!Q7)3M3&I_Rd_l
zHm_;xW{=f*k5#Nk2Jnn1tD8()f#kBvW7;Yzw>tDt3q=-{`+FeI<qv>^KyfSgrc+m-
zxeCvF>MDA1@)Nu+d%R-3b%39a@|x~-4U>Ic1E)+tb9v48x`u^b*D#wNboemFsTq;F
zJq3_DeHNT);RVhJG?D`v&oh+kEwzv)1e@*YJ9cgga2!zFs=dkF6iBYV|HrxM+g|x&
zs}<k@Q8qW3n*zyYlh@od{0v5cv`Epp39nASR@g0iT0poy`nW#^1qQ?Z(*xds7-{T{
zGhI~_^i&ZmBf#lEaaGaIwer@nohgu989TaGexEyeYww%9E%jIx@>s=A2ml`Du@WmG
zTxS-`X)%*Gpt;PNy3AU*%o_Tb6@d;!6=!?8kF`C3e~U7MJxONsbJ-ry1T)SH-C+Vt
zf?U_;2=C+fhR3hD$1ira2=D_yaog1dkKfo_{D9{2o9^+O?eRmq$Tc(V;_-?)B5Zg7
ze;egB*yD9ASEmUym)8i7*Xtgyp`u+KgU#%>y*^Xi*gkz<mTO%5ZQ%pL+luy?V~e<2
zKWOLKX9C;{D6Tc#q|XGBTfzU;XI}MK{phiZHC%vqMp@mY&jgao>c9HT$53QpOGoWI
z`%HlA1I4Y|oA#MNbM^hd=`&AxykhMZ;Kfm1H|;Zl=JL8(pE(XL@PbI)?oc5A^j+C*
z-7c`*Eu?6l`54lK5*B&-j_or6ZUhv!YH!kK0?F0)|JY}~@0CBcS^-`dWpk506G$$b
zJp0U!=rh|yioQo>(X)!XMQ>x*l&-+FL6Py|p`vct+vQz$fa?LpE&EMY(}3g(^<S%L
zyF6BRc&uW}5AdQWtDCK+0n6p}U#n?Nin+zQ+tYPyhYWBUP+Ysd>1rC#1hfB~(9joH
z=JC7F;}>h&01uDy%X4Z%e*kDMzr3d=vA)Ms9<SK`7~tQcyz-oukQdNgUU^STl<-c>
zEK?)Kv{kgDE1of>+U~Txy;z)2wcE?Z`F3LZpKAATXKw)>zmaC=V^@pMl!W1N3OF8w
z#1yc+?QjYRKT{3?H4zc5v4ZW+31ZCz;O)r!->nfyu9f7`8kKN8^bmW+f$3nT$dY|u
z!fhsdEq7HymTa$em%n6ttq1)j+i%@avfdyhN_N4zNy#o+d6o>|MacW#B?Hobm8>Nu
zS{)-LTP-?(mrA-N>u8C&0QTBMoprR@$&z&wb=J}9CQH^uFN2!zX!Vu5=^e#BNGGd?
zTp7R-U`Xw3#caLbXL(!i0e-u7zvX&ky@kcHzJ*3!^E86R#qcd~ZL=ey{tFy+`lwQ_
zsM(fSs}YO6T(l_WQIuPAY;#3{D-5NgmFGqPz<;CUt~zhB*b5|Ao&V!vZ;r<%wkrX+
zD<pB*v~b<XT${H*a@pj$*!vmm@roH)2(2TkZCDvs7gx+Wvfq9^>W&mC?G|41q>3H0
z0RA&7)lJ+HAh}ZA%pGCP)dMS0djZQ`tieV=WB^&{2@+?ydkL}472rWYan*AZX9Y;E
zAphm8q(dR1!V|nQ$JPYEXFXQ*YF)=S_ueGX1T*^IuHzfCHyPW>CVRYMJ9L2WfjFXA
z`na1qD?oF3-Nac*tc1q2J6iP}Mb-B!=T`l0)1BsEKa9;_uNgDVVKXRG*44^kGtXuK
z@O4j8e3#<dXRiG)Ah{LrUnBTLkJU+!Rcr+S{1{N&y1v;64lI|~e~sWKR3Iw*l*cQ!
z0s!9U@w&;9Bu6=*xfSrg*$+GG@roT$0d5L$+{(V`=nXWNSKgzy5-yE){;}!JI=VqV
zb^0e>U4LvwR?zve!pCN7|91Ds=6$kv?xTd~BDsHr%r!yg>GH10^f%oFY&m@OH}B$S
zZrV6GF!wjT;Y)n+@RXUtjQHXq2rAKy!8x8HVjDBSt$^-U@J&2nAi4FM*Vr4s4}8LF
zVax3zCFll_I(>szf_7$IxvVij3{&mQR(?gaGdp{VNKAn~i$xpHC_yJ!!PP{uScMid
z@06O5-wzZsAMogemq45?hF35A<QBUW9+@qMyKNvx%`HX?|ERge=;)1_{9Is*@z7>S
z!Oz<`Ol~z|hRLsum|=38;SG~Y_%2}gjfhZOh>%#(ElFR)-RO}b^fhjmC6NPnU!$vE
zguX@}zX<(|6p1W9lEax~^24#dVx%4r6(NbYSMAmyy}R8}!(+c&6Q57<W3wb)UA4)F
zbgzfBNvrDC8dfB^OQd=F>>{e=6%TQWRx5&-29>prARZQoTRp_qn)}Jy0DVOq@!HM?
zf;O(d{vGPQwbo4*v$qls!|S=Kdi=HtG8$JhxL0~r^`zIYAm3HBsmzDd<gTFJKZ@jA
zEb^7}@_nRwW~hXDNpnwu*cZQzm?{wYHHTo(Q?20@s6sqSu5~qvkcIvlFbeYQu&zcG
z0t%i*al0C=2p7kQbvNP&SK{dbR~!UswDN9Vfm`0F8^Nt;h;L>TWpzM)xBoEq0@Bu%
z(3R|*n)18-wP@)4TQCVuExt2VTTX_)%H*d@?f&Rcb$@i&Qh>xQ6>7#XN6~7f-$#)A
zo?mr;fcS&}*_-eYlgeYJv^MEO2$J9StL~2xCkl}GF`}C9R#VX)N?%Bj{LWu>f0+2G
z0NJZ?PL=usj)T*NXHqWpNIG(iC`^IWzMCvXn_ZZasP#@j_PIqUg8JZe;IAx9-s-x|
zK}B0tgiO^R9)`xY6ec(I$F~EDwzUY^sOy`7=AH}zzYjmR&<+(4@OoLGc_M?$J^AHt
z4b<=Uh7|2ofldIq$6=|hpfx=;8KaA$x<8t%$M=HJlb)5*j_>YoCm-ZHPs`HFr##Jf
z_ji;d`JNxT&}*km=ezrJ%B6h&0@CSCQj4;UcY$<zi+ub+huR<ueA}c7@9%qvrQewk
z=jkizi_n&lFMR{^{tRsyX&K-0y&tq?6wEll_Xg0GQK$f(irN#}GO{y%<NN2(mQl2T
z@UDM^wv194LDKvQ+A>NPNE0$7<C^4Zg~cM+{d})pgz8Y&;U;&ZUJ(Ib%lG<O0={CS
zqZrL4d^z7+NcgE0$a_Z-q4kq|zcY(kPwzjVhhn9vp<X()U#S~NYn7knv&vXLt1jfT
zdOLI~T8)SKtT~v^T9f&_<swt-1o&Pzi_e_eeAfS*@CN(%Y}A|2#zXmR!s~>!rpx(k
zb{{dD58$)K>wLE4{U%zgYfNpO%J(+q`E1*i&vyJ}k9Nl~Je7?81G+1AD6|}Hs=$<5
z_+H*l4h=`7V0jVAOi<4l_>h{h5^)FcB<6e+aVh>AjOgp|P^{EyxErVNnCdvA3-L`z
z-I)ucdu{ySIk_D0wgBT4Qhz7L_9%_@$Xzyhj*AflV{WVYG3r8s@`c~UlU&LpwJI?v
zhhj0YLZNLS@)8KQL_&KnQD^nyns<=SPPqW66~t?${5{a85Q*Q~4<s_BQBqmls&RdR
zLdtI<VIdPmajAKoRUsZqYHt*)R`OMFWwAa3-j@+Vp&!s?=cF-<5-JID_3|;N5$cNf
z`r_SG97-F%8<6}7{5@X$E1;Dxfr!o(kg`}W&79}(<S+HI@xKcG8;s}?X>iXM%F-ge
zW(`^V7D#PNv{QH}g?jesq1Y|cKY=`Cr#=KIPZ*QQLeAF7QqHBoX_F-6RGfZ5&O8g6
zfp+#ZFeuy#Vgy>+$AF~&1_JUSaw=hxcBrKUT1^6@rm7uB7ak_Sp>`8YJi?^wumoXR
zn?oVP|Kfq4h(CkR_MJ<34^sZlrTD!*|BB<kI=u{HcGe<Y`2~si2wn+N8F!az>|zxa
zShwfKN(=()&ies=5&x4&;AcSM3PbI8R-^cF5An4r%dO;N{!S<<PmuYer1zV`4-pHH
z27H7-FA??)JSoB_lw_JntKe2d`3E--((Xk}Nc+8zc7PJ>3aqA8FS=N@1=c?|V9~0p
zmrAoq31*D{IAQ=XLF*Gi>tWF~VU;6Ghu~^WQDZz6EXYPvvdmp><{XikiyXep5QL2{
zEBKs?CDk^;!*az<X$Bo+-M&sR?5iZRNf!*h=jLfBDAUjK7g6LX7|p|uBB{&~H&11e
z=bD#C7G;3Qlk~X9Cvi0Lgo6S6(gpuTWf3us(uCU*OUXwPmtl}~fWbdWn75$?n2|M<
zB0_xg#g-lDgcyFw<Rizr4>V-mXFt;8Sw#)p!OD-D0IGp5!VZd(9)3@zOh?E+F_upk
zw8%joUe-78IFfPkN#HpV_EGTr1DG<7NtlYg@BG4hQSOr7OR`(@kIYh(mkZ;*N}u-<
zkiS6GeBMhy{sK|+c`pI!y=Xq~B_Mx|sQJ8?fb?E8pZ5}wzf9D8-b+AwFPhJL3CLe5
zYCi8p^La0t&wJ5)-izk*UNoQgqWQcR&F8&nKJP{Ic`usJdr6nxi{|rQPzL^LQuBE)
zn$LUDeBO)Z^IkNc_oDf{7tQCrXg=>n^La0t&wJ5)-izk*UNoQgqWQcR&F8&nKJP{I
zc`usJd(nK}i{|rQv@TKaMe}(tn$LUDeBO)Z^IkNc_oDf{7tQCrzz^u5gyFq3KvU68
z;lAjm@LzOOI54^?JQ&>+E{tvpA4WHY6Qi5Li_uNt#^|Q-V{}tEGP)@|8Qm1FjBW~F
zMmL2sqnpB;(M{pb=%(;zbW=Dqx+y#w-4rg3ZVI19H-%H9o5HKnP2tw)rtoWYQ#dxd
zDLfn9df*dG_I2yQFGbLEj|h656Tw4jh-nX}iQtiPB6zf+2p;Pog5Co}@VGd8&3f`Z
z5$m^81OqOLfIrs*m8UVMMeuAB5j@vX1cM$F!7BqqFm$8{hRqYftII_&Li_~4dhNW3
zjlL{`H^i@jwDeB+f%ne*bVS`-?+biT$yN#)h3fT3N*7fmX+J-SuBu}E5cEvim<RAa
zK)h!L0`t^CjWLBqZ5B2H3-ovKlJsxGFwTJK#Me44aR5vTlNIxN7i64o3lGV>1M|4R
zBJ(w*7)p@Sl|6V3Q4pLPHyAVni}gVOX*IyxNz332MO)VyXAl(45Z(&!yi6W(2c|67
z9|A_Pg69DU*SQB@FI4Y^uG_qfL$jTlDSTI)u8%3T1Z%^*y$|5ELX;z5b_GSJRw^T5
z^A%8YY87N8(dqiEQakh*GN&q5B7)#i(0>6hLP(&G!KePkb9kqjIUlc1eMc7U5bDBd
zAR>lYwI3o4MI>N8Mu{4UNZ7pA43Wknl4u^KOie^2)jWfv(VeCul5WoEhRCfVQpgOE
zbTbjjQo`G*!~R9l(VKQJBn(L6yJEJehsaYFrNO1N)NQz9hp_VSn;e{-u6>mW$pX>o
z+E1A%mEv@LMwujD1Lk!~`Id7Z^O<{a&Ym+_MB<&U5A;%|B(cPa<~%BHs>qUVPJx%^
z%t-EuVX2TAM=j0?-UD@InR_6kGcR)rQi_|!>mc%W=6Xa*n`K}}&ce83h?F;9Whoaq
z{~%J?>H5?I$`Zk*I^O##?+I~p@ZL{(UvO+_K1CrvOwt^9Ic5PEobypqG9t~LuDu^n
zR*2j!%rAN(VU@_z&K!FuBA*0%L9X`ZNDBEmPG7}Oea-hsY(qRP@IJE}RONgjbld~3
zKy$2(JfyN@M&rA~%44darWnQBV1-EyRRmANn9_ogR7L`Zj!NpQ7G@-DG-`!QPSt=g
zDPs}Z>;Tmn0b;2}g(q=&xSI9?I*RlnUGXDCXP}xq7_maeZ7||NYH%zfS;o8f@~l+B
zwYV_=8hk}YN*j})!J(2|c_ZtQurgdtnTR}<jlF0;ud0bt5vguGgghf8T5V%8%Ke%e
zUW}9+V;L&vO<9J9MgruSpypqWl%~c76m_D^gP*|AZsJ)4N-lJvvUXJw6-IB3Mhbig
z`qU|Ww;shq<l)6BzC0o-^GqP#OyczeH5!5sk04dzZ6XR^X&zA&#X60+=sQ^RqFLf<
zw3e{jqFx+*#$?RXoqr0HLesDaj~megT|~CZtuLcmcizLAEVjXn7wTjEQ${SK0vc{{
zHJJ-0VdD=NNGY{A=iiA+kg%a12i$uVfaVfgsb7-dY`nKsWv62_Lp9tkYs)Z3w8tW?
zObHl`(0cArQ<(*)-mr^`YXnPc*Fo(C{TpM^oI6VO<4Wzv!b&GqSf^nOgCzILNZ6PO
z1L!Oxsm2xbLHDTv<}YOQK~e7ajAmvd{4!Xgl{Q{QXW3OoDjQAF$#;{H+C~YG?k*z@
zjW<E<0U2qb1X-g`gRs!Ctt2;t;aCJ%)I%x_Rn&`O4I{7`fEK&TRN9$ai%Xd@i;t~H
z)&^a4a9mp=Yeahk<p{M*VwI<G7)>|}@&C3?GBY1ItpQJaHwKfhOd0}*RheQxkIwS4
z0CJFZfvGUxD+0(N*9ERYyWA>(9DrTmaLlR?2_T1K7q|iJ&kNua9#G|*Vo^G~Axi&~
zXvG|~qpiTry#+1tp8)0NV6F;-=R>hC!KO|J==yMcmu-kKRXjvV?G)7Z*CICu|7dQP
zcz#sUMIjoU0s&MxEK4QZjnQ-bA(G2PlKG}sJ1Kdww)jb}MSMCDF3DG+f}<i2T?z@z
zcc}{w6qbDE+=pde2g;MuC}}z9?IgpIQQ!^;rV1(Od_?6|5*~aMze}-}6Do?B@EIE5
zHj7?~l%L&*VrPQDH-aM_m1v5fDKw<yyZ;Fsz$27nH>!uz*aOT;PexRNV*i2kQ-Vfm
z0)?pvo>^RfimMU2AK+{*GpK1nE;AJ6GJ_fpa+x72vnrPvid6@8^-}PRsNm_v8zNc=
z(R2|_yoPCA305p-Xo-6<PS%!@zKQ?-;wa5Y13weTrHxpY5O-P>RFraJj&|ueIY%q!
z&e2Z3qbS$2HQY@tj<ORA&3c*qWyyzgG`(DUOT35V98Ih+>vDxT<Xd6ZZ^>ZK6q0i^
zvBIp&73Pp{g&B7x)0GOzIht5u*5wK_?oH&CkYa^de<XvQT}aN+#0s-MJW~k7IhyWU
zVb*;s%(`!dS@*3l>%J9c-M7N5`&O8B-wLztTVdAa3Uhhi3bQU(m{A7K(ZmX~k(yiu
z0*e)9BRz#H%nqm4Vwu_SEi)U%Qy(NECu)Xonc1kEIuh`bbC`*<HN&^ojH7QNYt4pl
zt=aIcH5<OQX2ZAEZ2H!kP2XCx>04_yeQV98Z>`z%tu>pzwPw?|)@=ILnoZwYv*}xF
z#%G6-wPw?|)@=ILnoZwYvnkh_lc|iY8hT~swsEPYweRRph7!WEiN*Uqt^G+n$yVO?
zX&n#|dEck?gNVrcKCOcyf+oiMKCK^h(gd+%-{88njwHrAKds{~G2Z!Uop6cq&QI&4
zON@7ZTBkf>yz|pKt>*`U)PQwy?bnL(8j11VPwQ7n43Vme^_wK7sJ!>n`d#k<v<g|e
zbw#bv(pEO23$}Ror**ZkD2~OuKdoybVpzQU)A~n50^;sZ>t7L(cYj*fMI<p(-u=n^
zshRTbPrj#T%DX@LUZ^7P{<L(pFga$0Ps52aR31DsSPgfa!=o&ZA@YG5o<=<N4@7pT
zm3a3jzUUBa6fG?8{v<s^3-iJcM`bkyv~Z90K_#d%C9H*c;YUcMBx>O&j@e3Bq@-$L
zUic9wQqr|>U!=r~ltNmV_kAR&t5G>wTKKAl<0Vx($PIC36<JVHVF~x(2a3=jg%xq6
zvlc0@h^rExc||;=B(q{ty?8;TGVlJhl2rXIz{PHr{n>_Ms>0)1<HV7Faq`GNmG^(z
z8+5KlhvcD5RX9Txc><-{y?|eDGLJZ&DNdZu6emt+ij$`^sXU!2P+so<q^gF<<y2aa
z8<9R^E^!@boVX4&PFx2XC$0mH8~!@98z-*=Re2q#Q%iph8A>u&Y9XiITHL(Z8@;!<
z64a?5rh2dkhkaG2k%-7EL7k=|BCiB>T8N0e64YrWBJxU5r)>%gF0TZ2?hp}qC8*P0
zMC6sA&OIU`uLO1O6%lzQsB^!FWWc~7nA1()L2{*?UiDtYEFRvwxE9oTNbr=`f;x|h
zh`bimc|t_wwV)X4SsZySsPmkN$ZJ8Jfg&QW1$Bmqh`bim873m~T2N<%h{$U}o!3O9
zIGh~F;*8gyh1ycnoyi8GeJC2Q26d(gEJa)m>P#0A!{XJT&MXlLSiBn4nJXe;i&uj>
zZ;Ob$8q`@RG?1#Oyc*PbUrzyP)YS3=7;BG4*sKs)TsEsj#AWlTh`4OliHOT)y@<%`
zL7j~vBCiK^wuneNuD=2k=WG3W@JScfgE~7BE7LRJX;;p7S$vn*gF4?Aq20*qL7hEC
zc!#>Y9@N=agiW`&VzZs7ydKm!ub&4=o7;OfN3&{NJ_}*_OoiJlSI^AKFCxLLGLg@!
zJOtUSelJ?ES)(7HHAnGTYc8L+z>pQQ4vz&l>z3s+r!k-Pw-VmqD4$}z%xpZ8?@ee1
zX47?iHtR*q=7acbF^SKX@AKKp;<Ggtm~m@TO+MSU<+B~XmNxG=kEc?d&Q~}TI+KLc
z^X|MHP;8Zj31{#M$pUw^Z;I!w9eL?W`uc%rt>F^kyO3h_e*|lVrSgfkW%XpFw1^l=
z`rX~pq2b4wBY>xs`30xwR?8QMcQ;dYi6=AF5RrgV>iDy`DB7S?7*}8kSvP9i$rV5q
z0%%J564YdRT=DRE3h=}Ok1BB`3sOu)oA-2Bi7O={0c~V;L`oMV`$TOogpMmykY&R0
z@}!*J_jXN5j4u!_0I%DE<ne`4StLapi3?EUGgC$R73X*2?uS_E@x{X3Jlqobe7GgW
z?p;{pHH-058Hw6x$P!;#q@*e}xNjFoNDd8!-&|AdrzT)O^(dwf35+Gk4OMFYO|Y1W
z{{|!a1w3#FDBRctxug0A04tG<aU=$XJE{qCOZ75P_9OWiQ560vT~gteYJ%KTCCW7<
z+YrEy!fn$8xv5G<MUY&AD3nD>5UFxk^>Jjbhm;mxs@zpAB6n3!0-C^G)dab%O0385
z|4Cv~BBgY6Ta~m&AYld*MWJa;zHQag(QQ@Ay&QO}BZM?=t0v^62@BM?ubSX)tZLj?
zO^EEQQsN?VXVruRMSMG}zkymU)=+}nS`8vyErgm<@S7Q&&Q29ZWKt5ixtbt%S4p%f
zaBd@BDhpPdyQ>Luca^E?gGj<`(@mD*wiaWxqH%jQA+o<p<GN*NhN0Bf63c`hPr!-3
z_+N)FikiU$1p{RUxO@zH8%UE8y%_n5^p$8C1nouI(MWn}rf2m)-tu)}$Ly)%vnIei
zE4&1J@m)ezAG}pu`;?3Z639#onxnsS1iez2RaM1*$*%(GWxtOWm2?PHnj+ygFHy<v
zi!XjMW?WE}`v7|&3jZGb3l~7gKLD`jBk<slPoT*a52j#|g|(|CDx9%S0m32=Nv{fy
zdLwqw!E=yN%L#S@A&IUMeG5>3jG(jS>b01snaEQMthLVZ3!Vw%7B#ZanCBYswRpEs
zO44SOM|&{Xok5~OgiIt>^$?^z=8!1)DoGf16>VU!F@r>t_-%mOF$P~r+E3QQg6Ytc
zmS_>HKQIR6!kR;-V}fadmQAcFz?kJ>DZxvqH*HD&hR<Uy2v(vc>O@)xgpE<8g=Dfa
zZX#Gx16pE$NIwJNG?5yy+Jd(dX?5H#P?AUvkpi%>c>H&fUPr37E^b-`DM+LWK&Tc$
zs@s7=&kQ~a(V7F=hAA{YMY{u)lh`AZc4BB-K_szfW-CPC_K;3a8AxcT1%-*Pfig3;
zg2r4_>`08NZ-UND((26Y90`;RW+)0e1T90_Ixk)C35ZO;jQmXBg|tJF^hYD<bs#R&
ze@EJ7FI}lu45XhYk}51wEuEGKGjT1EO|MuYN{#<Qp4^tGR!#dpg02$%PM|&%LC?z)
z)msXj1XI@%nP)igU-$CJ%2w+aOMp_`$|lmgK=?3%B+ON9m3F5vEQ1K!ka)yH$kSZa
zJJLQD_$KkM0oR81Wx*(^G*|VWw1c7%Si~v{j0(B1Xs&AKv<@h_mS_{J1u)urSh#5r
zT+|*JiNJF$kw}jNp+AvEQs2T7)kiX>z*t;MB+_^wOpYMcrzNU=G6sSbkyI@)NGx?l
z1VwQOXut)dB>7!RLoOI4x!<L9z=0&Xc!&`~vDqo-<G`DbZz1_fiY);D0BTd^4!eAt
zW3_0E4$Zm@O*bEVWSgf3=A+wS7a=kFAvO~nHnC*-@-#Ftt%?IfrVvnuZ~18OjcC@i
zy2gtA5`reiMp(oXc(a+@R0FH00GS2Idi*cSZ&Y}|O)-9_kkG6+%TkOVsU$S3A!;s-
zm)cI$QaI5%2t=KYPv;xv77!?nw^Y9?(=Dn*q?3#;qN1a;>4c~8n(QT7kZC1jFqJf3
zh`c}&X%$HlZ_KZ^15B|wVX&Fo?v6MX#KcED_u@T`H~r3)`3HLWl{DVtJ4ZstN1?p+
z`(p`x&x49lSSiS!Y9n9`%PH=?WIGWHP)W^DVyyKk1=;1D0<>%d=g%8(*mvSKFC{gC
zlYv+aop^S_l>z;$tP&`U;;GYHdpLy!ufB;bV4Uxz({A)}11zOrHHh~hkY*xFN0DVl
zY?j`I79goHlFB}!%%-X!a-k)FRR%1v3l3?Uo6Wl8H%;i6Ib19UiMGIKCkUR;P4I3c
z)t3avdIawSth`5Xyq_RPDKj4`1Q_zOql$=$g3ChnF3zuDhE*30bKGM>q*pVgNH~9!
zqvEZ|aj1-!zfWHI2Uhdv9~8~cVRsmEBqIN}qCi{o%Ku<ZH-COQ(+{@E5i04Ce?7X4
z2k#Yq^teZbY(1m2=>{ADwQZ%ntLV<>qOHW!voO=(tN~|&;C~xpzVf%v&j~}0EB{^j
zFJffQX-=0y8`nC2^O_+grxQ(H8`mPS85(MnOfi2QhcjL2+H?oCC0K=iUC_oYDzUUl
zt#}Td8vIB>P%GY^-VJCAYNa#9q<dVq#QA6%wS}{YBPNx2x>IXGjej^p0>-#CmNx2!
zuGkSk$AZ7aIe!BVeK`|L-ux?s|LXK)#C+u+pxl}OoGjwh#6xsIG>u{>3*e*ZU_;>p
zHe;@d7^dz(cpvyx7qlKgtOT>ds!Nm+VPB;=$7GE8{TY7|4?(gUNGdIu;YoD#6A<Qr
zOqL*1LZG58V<SM(<LiX#hHk-G-N+tL>SPBH%MPU@ihBW~skJ#V5P)p6u6av#;g%`2
z(IuM2l~AaDh$kdkNDX+zh;Elg{z7=cB>*i`D&fUZ)s`tLNC#8YP)Oirt9{}L2_-0@
zY=csSO9C6yR6#Dv4B6vTaDk+oFT_j<CQz&6^Dlg(z&uISDRH(c3#4JMBDsc0NHNs<
z*>)%!>|?m5Lc{<?%$KB=h)+Q|3dVQHpQI+{e-0{3a|;Ix$`64}SvV<gx~m+Ms$*$0
z+~P|BR8zoJt^nYZzPgYNR&k3ev;-(ikm*KI1B@0nP{PME>W4z0D%lZSL<2Yn<;<$6
zHpuWQrB8gzl-8j(>6s~2Lpd2egkrN}5uyo2V-s4sd9olm95J%P@=HavN=l!2NvQ;O
zI>3P1Ey-6Y4be*ZNhPVtR>Smx85Fa$ACKBE!}_MpxyllDMrCONAS%~YpY9op5o?pC
zP^%x)idYKnr6Bo0l$d9hPSh-Yrshz{kRa&VJY@-cMj7XsY5WallpxJ0@dh&@#UvrI
zv{an}B@6480KqfGudz}YIYL{h5g?jVN~w&NDH5K~XXV+6WRMn8sb;?Bj}fgw2DO|n
zlVO4tBj%qSS1QA+8kk~U)?F}a-GyY6%ZwU1c@=gw6|v|d&^#2Dl}{}tN|0SqiCUv9
z0J<Mvu|l2@&kOuwnM#!uO4Tvc$-D=YU~rycd6?3YN<@gjWMY#_=4Ki#W+_pAQMIKq
zXxTS4JOf?W|IYAynC#%tyAa~pnH{mkK-A)*y_{!IH`-iGHL?=pq=li2^EyUhISJCX
z1W#dGH!(rk5?sR**fEADy2NZNR+Ct2WqEwP<$s%=XJ+Yc<z(9&Ds0c5VQ)8fp#`Ew
zR!|yQp;#l!%xz?arI8i!j4Y<h^9t}hdL>1Ts$6r8B3C(yrspM=5f#gfwI}wnRxBuL
zU=e$YSdSK!fx{)ozet+lbu6Z52bNTUE$bRCwrBn9H5|_-vJa^=PFh7!!b~}!H9*gS
z4y?M;JjJax;)Gq3fmMn+k8{Z)E-WTKF9jq-6_A)$Tayiz<7s3_C$HqZG$Sh`3HPye
z$j<>3R)FD8QN12rcJ@BS=+WAOvix=G)e8nnuU=540;#3wIU1&un<YrYkFs;?Jhx6|
zy9lD+4*5rac5k6vdJ9MNCI-Vep?Y_mkeZK-3!;jtkAz%x;ps9v$W8+7O?K%?UQ3H)
z^b{!#Hqu$Ma4Avkpm~XbA!>oCc~xe<Xl15J)5<RmE#0%g49@}!L@L`=suZwbEZE~m
zH5H0Y@~T1h)0vS((ND)F7S8PsDC!M*@N6UE8R%Xsh^WeNdE96S6c4ive<QN|$k9Pi
znzLsu5oURL4xZHpqb=LB6jX<3Vc|%xALl7J-cxWwi~upUM{yH{!AjSFE;I(Iq&%Gp
z&vDJGzEh+1jUL<cOG!Qr<mssi<&k*)m<EDonI3E989rx2c%TJhTR5E(_^y#^7FH8u
z9+~hN3Gl}BOcR4V+eYE)?n@E37m3s;x^z!UdJP<@vBm9y*cTRc8=uH>V_zanAv;;>
zPxogfV|SV&CNc#ij(?isRhjKoS-|T}oLE~5%C^M8TMUzE(PRlFhGi|XXY!<w-Gvk^
zEIaS`-0lvhE2N}HrzhwyBDB+@9U-eSNjBkRA(OOyYQ}RVK}Gg3vNEKBdoHD5k$bqu
zFGC}|3Q+I<oN1ynl;R5;&+plBEFanI)1{-SQG|kUwX*RcLq=YGtk>O0X@gO&l1{-$
zLn@S)oo7bvys&HMFbFEANN%&v5|xRn$wp<08C_Agdq-nuj$#qJ_L(rd+v0g83`9bS
z*aS~sOez^^4|#NZ@Iw7wvDa8IJ@StzG}JP&?ZCsNxMlrGud1#uFKfA+>*k7rcw)&x
zSemNv|B|HTYd3VcdbDF>O9{9ht&5+#KlQpp+v}G_=Sk@U(qy8}rffdaKNg-xP>Lhm
zM6?O^M<LIw+)>?cgJF+_X!T^_ImKR+P4JrRO}t<bKyd_V*#whwv5RVpN=}KGUmmV-
zUIyu35b*3QJ=V^=Wq`;S<23=%DSJ)aHUC&M^6R3I=WM$!ryMc7Iu&}QYm)7%Rgdkt
z+<FxYHD0|&Yu&m*&zMMiU4!d*%03Yl=0tQ9^lBmG)q<?B7#Ar{8in92`jL3qe+hsv
ziiC*1<Y1a8`?;Hpg3^EUxkR~IZ>p!Ke6q9V02uLD#Q>Pg0{luwHzr!D?Dk@MCr+m2
zQj0XF+&xzTPlu7_P%tlpDHQF&GChMS99!!-VrpC@7U-=7WX1L+ax{)kyM4-Fw^THO
zeM8q!EJ8mf4_iTTsY1Tyns$4wMOtgjDiB*|u8z*bmOYW@1!$fZActvx<1}t)u4crU
z$X2;RK$)yuFzNJ1mZMn5SRTz~zBo#n70vuX&q6|8R~GiyY^;OL4Bq@n)U4RObr&Y#
z+IeiEo~6`H#P7dhvO<bUF${gqJ`<Cp4Kqb{$NpxEj)|kbXWe<aiuCc|R`|0;rsx5>
zf;3)fW*M@vp-+mG#ODggvJ{k^0S9+65#oeB<dPRnIx}~Z=HTqE<_d%&KBrQyV0m^d
z=S8BW(XYg6Wkil#YLOmbc0`I|c{Q)%(dJdcYhESMVZkO!dFuzIBaH$TDm8JFkynnc
z7<t{{`-YZME~IwI&pIp57e%SyAEfEWGOc26Al=v4?pds}b58HBv&%Zh7o&2y)$go&
zmcubL#0B4~*{ZkJD|&5a5u>r!;2c@S!HQ~Rm7s^~>dE?b{aHa#4$8jyj5iQ?#xJYd
z#RYFnd9hk77wTd39*b<VM+#gpVeBL!3xd(tLkM{?NF`%|KvulqL-`}FYow%JG2yq$
zRcU|MotBq5<d2#|dh9ZLM(i?s0j{U}Hxdf^0aZmk%6YFlmI%#97TGiXCe=qQ%*S-<
z5>$ls$)aV6?#Ue{3E*TWGDwLP)7S#iVx&!Iv4*2#gGLPdVt>Y+=Qy&VvLobTc}&mf
zTPyc0$(2L)2mVz{+4(qfazbi(4ES!t&L&oNfYprwU#JowOa=rfKA*eG6PXJOo{}SW
zYGlo4hrLCvB-wv)z9u>xT-zddJ5r=6r{+`1DW9wL>_`bP-;I_E+)b~W!w$}kOOfeO
z>+sA0Eu54K$gLU9Mo{cRuFl==kBj26b3^+hcH#UH0Hd)}5#-N`wYBJIEm|<Uz338o
z1cd2H^T>ouER6f3H*_Gm>luS9hlywx!kxSzD@j<&jazdOuP)#<R~lxt?}*M|#4b~|
zDz=%TeNQMlYH>1*;m2bAySsvM-cTFQ9>8n*vitFjLeyfe9xYK0<eIbuO5_clE_Ul1
z1WES1(iG1tO^sBTx3`!t(q%>L#cedwCi6?1^s$9gAKO8=-XP_zp5g0*3wXm0mPn!{
zm7QF~hnH*IQ4PUJu+f+2hGY@h;U-88hz?hFAK8hl&7u^bffS%nsJ9$Kr4LK#vx9x&
zeZm#>>K4;qQAD@pz`hX0OvzVbZ1>4!o08IzE_K6Bq#Vghdo50gNO8P=x=dqlU??jc
zJ0Vei*$0-(t3{TNw#W*ow3z+Ximr)^R><C{5&-NpB>*%1%CYUVifqJHWh1T@+y7UO
zZId<p-8~y|O+P^P|FztLM(tGe|8kJ8EfVt_9BvV$+_Iqa0QEYB&^l{}s-hHiW2t(&
z%klG<nd(si%m#Zy#`>`tV|RY>nbwU%Qp4CB?06b^J#%9;Eu{%nMIQJt${S-T?yb_4
zWl5WPDRT6cZMeA@*o9^=?u$OOMJ%3}1c*-{@IgHO@QE${HX2G`uy~UXeEhCx${*NY
zm+4JS`KiOR2-hI3x}^jjMmQZ|dxSXAC$J6S8XE`DAoTun@S-UbQ7B0V$K{CcdD3~Q
zwu?lZg}LHh{`*A!-6g#IwH+nEpC{IL!=`R{n;W)s!@Ch;t3v7FhW*@dFv74$9AR<%
z*OZebJ^HUBoiOnSpUV4_c$dq0cpm_d-z6zQ{KUyaLU<1UHKkB_56?h)Q#ZY%8&WR*
zF>HbKZU`45ERApnLRtX-yioA*#aoC}3}?B*R5$MBE0ileH~!7yUjF|nB>C$6l1u4P
z!z=G8$p4qCw`N4ZpC=c?!}v|W=SZI&uLMSjRDA#FhPS!lP&aIduyleFSn1Lm<-#9z
zLr)L1kwb~7H&ld{;?@gbtzEpfZrBHFq5Sj9^ZzrRyWTu~2%bW355Y7HMwRxEo8_5~
z(5tr`kpdfWL(h&pxEB(>3i;Z*c;p*SRRX=-cpo=}Q7Quf7x)PIRn@l$YrE+lUoQ**
zZsm*GV`Uewp&O2HL(iT`pMPF{emls&+;NXzSSE{h;J%8pzBJ{%J3PH)fq!kc-u`y&
zfO2$9R{~WLjzU=7&FtyhlauB1{)Xa3Q~GxF=n|fY|DPlOMFYQX%tZg?(%->E{Q2#F
zU=e)UhID)|CE6#ZRHD7Ma6{skcJudO1b?Mv5L3Quz|oZK?w%apNuxwv?BZ{8!^3Xa
z#SL@YEzghTUsE^q+DA75#n;Ym=*2s_cszTOfB(urS?$KRx^XY$Z>9L>=|g;&j(BOe
z!#gEX(Z{-Yyv~k)x#j%7jeB~3R+3Y4hY!1OFU)b{UOt}O%0JKUO1kpZlwffSE?*D2
z@quob<Kne*<D1;jtH*9`+zZRP@yc#EJ6HT^&<ht;0;gbK-roScXv+SvUi}m9$>q`U
z!iG%5Ur`x|OF#MA-i_CGL$*8bls<wy{Nipp1HNm@TT?u~-hlz$IRYN)bb(j*9S_g@
zHqrakk$BXr_o*f0{N&R6^wayi)cX|G``p$0Y}Why*88s4`(W7n*4X<l+53js``(#+
z_?L+P_z}E#w}sQ9DwX^&;i%ZcO;K&(rP#tpv4w}C+R{NO<If^|5?gpADn8`K2bs2T
zN8E_gz>h2(5L>t(ws1ad;d<D@@vw#4VGF0j7A}V^9S(Ly5wV4jAs7wT6nv-~O%Yy&
zEq#i2{RzU25Lr5kXT19q?t?9y2V1xf0-i3O?R@Vo#Cw+Snd(a|<b(ThZhV)N^LQ#}
z{Nf5PKo?Y-iKpb2YK!4tx5el$)jM7Ww+XbNGSbi%!@eXiO2Qr$2(lda*&OcY8@3qj
zMM7)wY%8AUEfIJ;AsB8r`G0--wb@MECK9PnF?QQx<Q8ml#8Zme)CZC9rnVTX1-zXt
z#%b}+@1L=LX^RosUd8d*7NfI(%PNx3fGtL40k15c4aIYW)ReT1^1f_^Z+NdQAYt*0
zSL%Xsq%<6HS4j>2Eo-2%Ek;{gjI|<*REFf8raa)!&O#*GVpw%-F{(-;JEU-)>4@=E
zx5aR3i^0?uL#ZIY5Wn%qUk~vtEuQhpGW4dNkYb=QlvA29$((8ej6Xv;qZ%J+%QeLo
zgR11WSO(i<a99Ri1WCV5%$FQD%D^?bZUXI^%p)WFB*JPL{40}I%MxytF*n!~Q|wJL
z!$L!lJS8!YN#NAr4dVDkyV<+c<g+5L|M{?h$fvY8i8)m=l_s=6vaTs`C&-k8G8iae
zYb1iK=uI+3)`V1qe3lis(hg=zBpLZjv&G2gDDdPW)h4hdPl+a<4F$ZYcuI-ei}%{%
zS>6_7n-8aWY^N!PGFuL0{rud-*ky~6OXMzOi&0Cw7qG>MrP^Y^Qf)C_*<!R(Z82Ec
zVyLpkKxK<z$`*r^Eruvt3{bWlo^TF1Ezsr<+;v6Oov`UFS%UY}IQsy;g){WDc+>h-
zQx!cW!OZ{KPOR}1PBhb6cfm_$lFgrG>ThbvCVs$gDSE*aGi?jb>CrPS`z;K3`cT!h
zzvRmTHPy`e+{8)bMf2Hz5aJkS@Z=*nizlp^R)q|lT^>j?(=Ii^!QzGT+llyPm0?#E
z&(HbP<I?RU`~bnw<8?a~D+-1^h)*-_5QrFhgADtAj7Wz49G?1IwSZaR0tO|$azT3<
z;f6f`Lz%uXp^!bNB=ZeR?7I|)hU@RBnP!pEIDW&hKQBcBjfbNEv+%Q0LoZy|UW%BZ
z7b#*_Sc?~XA%47%XqIh!#^@7U7=262wjcivxpu2X?IF9E@cH*ln5Gr8d+z4jEUmb`
zA8x6B-6&z^du<txMz_1|XUaUSr2UzAdsnmVKYt)>yH?6J4g>ogt+ZYF2tf<AGG^*1
zG)=>9`!fO8wX*g=yy;`La`vQS0NJU>nJ`T+Z_nVHc}gGDo$#us@H7lFy&A@Jy+{Sq
z8kZ4N^n{A0)wL{M0zuQ7313ymsj`IwNvM;Oj@|V%Xm2$tnMKOtI0Hlf#;9y3oh7+!
zJ`Fn_KO2UQ5<{l73Wv5EdQuhBy7x{f5`XO3Or>YMh3A*AGWz9NzCU(O#k2m`ggn$0
zC$uPIl0tZ1x=Q^0SBUdbh#h0bVLpf9{5?~t(U0(Bs{(j#JwW{3`}wRsl+Q9a*#W0<
zKg;K76Gsv#KjVmbQ@Q6Z;=go6$Mf(;Vs4y6YVE7pcwWJ-fvG&$l&K@&kebRogYN^s
zpj4YW5x+7nGXURjm}~1uLQdebBvYATIC%cpm+y-{C(bKPNa0*T=3R;V2u$UZsg$A2
zaZ3IGPVqC9^5=-zPN4?Q;b16JDTedT0BJx-<Nc($821mDN{REtjQ@c+of;A{?{>cL
z*-efso+SPsmq>qNC8k!zF`=eX>lQxGKTe$dIG_UBXhyz$JCj=eOO){GH(2&!llk0w
zo{(XanCpiI%=PIiLTb#RR7LtT?~avxe+(WW-WxOZ@!`x{SLi%7o|G?iB+hM*lEUxf
z`E2wfHMS22V3<m!oy0Hj6>;(vC9hF9SkzQ%CNOoEkg9Ga=K2^%7n;hW(^=Bu+2l3V
zVXij6u`GM5QifspRL)dJo+ISU8^ozPjr0@XQJYGzB;h+plFt6q#9w%bsTu1@|LKN=
zWa@nW*ojYl4CVZ3E%PRvXL&b1MvfLPf`jC>NoRF&KEJ~;4yN+j0dik^52@vA!1uX#
zuoT}NCH{bS2`_w>QhkW?YE7loK*C3jqg2{v!mSI$`7noEhV|gHFV6FZJg@S-ERJI`
zm8>1aKVO>i48BS(FY+uS<(0F<`DQk8){8prC3IdJ(|c1%evu{JHI~$d;5a<k;R;f)
zdQyg$wh{757fRJg=kv>FSnBB?GIe+rQW*XjC5&4_3YAxp@1xcDKCUk5EXkxE?w&*V
zzM*_y@(7=URHi14;(Jda=j$1yHl!4}bl*nF|2@w4-bX0mG*OCi*NM})54rz{1E+{d
z%0bKsAT3-bQyG7jG*3>ZRQK-Sv+`HuHCglta|5JyHH(-l&Jh0V1mf(NOZe0@@+~83
z?L1D%ft@rZwKu+CYPnBX_L6PLvE)T^pDgOGO*V1nW8^oLTjuk<>Ht3XmL^W^Iefmm
zoz&u<qMQfjlfoF$7RLQT4cEm|ovEaY62;+!d9>Mi#B7K&`%R_QFhaUkC(Wt&l-X47
zEWy;A;gn}pcT%|eFW;Nn?8izcQa_LVMw(sfGuMT5;`b75^W2YwH&Tf?%;K}N;9FcL
zo#d%}etC{uE;nJRYh@5}d>3<_!^mMOGp8`M2aaMlm1nM!GJg<hDit${*=sc4m+z;{
zNB&}JoA0RAu>qzw4v@n8IKT$=B6R-xA-)eOO8QH_W!^sTGuOoX_<rFprUqA#<L4C!
zzh^e-RC<B%OPKIN0|CN+zMGJYbUxp}tsKx2PP;OdrSB8}wtR#){+!$&5%u`Xtt?%F
zMqN#Klh3Je_|Q^%vs?#9k^75_3F)$ukl&_JhUtgN@m-8|sPQdK9b15@({YxXshn-k
z=jsl`u^%E%=0<Yt@)vRD&EoUc!=&7|AaU+mO1@ub^1VrE%K4Az&ny1P_cxX@?{bIF
z)z}4qJO?Sm;%Q8sGK{5u?l|8wcChx#wIk-`o|MX(MEp@TiF5H7aX!N#&!+MLW;&+w
zcMHnae>hW%tmgCRkCg2|kT|VQ5~uy|e6Niotk9;ak=o*cEZz0JgdY&K-zbqBM@%RE
zc9n@!u_~YCI*{6FEC8cLz)LihS@_kosr*uddAANG&7{tRbj2}DrZW0Z(mAkz@3rC6
z0>3*kmuzO<m+qp3J>hDi#@mutt>Jv%Gne?)o}><U<7_8Wd1n;g2fR#bd)_0R@y$r5
z$q+(b7A>XYw|swKIrC=X;7VBgEu{I$hvc=iE}y64h|_E_pWAQa^Uw9fEYOJ5rk*7C
z5gEiR-Hmi^6Rq!pXpg6aSD<%i882U>41@YopVKZe*Y~1Vyz?ycPFYHt-PV#q6I^p(
zDn+-mq&c56wZ|IrT_$?Y`Tvkk^WVt5a}vw=77lJRl{W_w|CMKm|K5GXuPsLWsUH%5
z@p#g#h=Zarj}$$?_q{2@mEEMXxeIgEZbJ(1KTT?5Qc1ZmmR}*&U_zW3%v-lP^|Pua
z;a}oBN{laM2>(EgDH+19+TKYzr+4#NW+J&<7h`MxyZJtFFw1!V%gnoUB)M<zLkd@4
zCgtLyPwS7#gr!`qNXVPD_}(`IrxYqDhXnAv{tb>CR3?2&sS>8?c(1uRh-dRG9AKyH
zy_02sdlB_n9hU%EN=9SSUn=~le}p9rJg))X_ae)942OurQ#wit58_i6cm+c#Va0z)
ze>>I>(6{F!=FT)y9^V=V0V>mQiwVY~lEl0<$md%>TYzu;o%pj(@O@=-$`jv{5<YM{
zW$x6NTo&EN)X__*pIMjDK9vd$iSx%he16@Nb&+o)=|3a9))Xu<n#vRC!BEm?30K-O
z@4-rZe)Sji^V;u};SpH1rIbHRn#<ad<NO88HSim9R1dJ!yX&#MXN6bL?rl=;dOyqc
zhOqf}mQd$EeGy`UVmjMaf?xc+=AfSNj|0gPThSj%p4k}dki^J%;5q1~WP3)-3cM!8
zpT~Q9YZ>r5ObkNCyVED&{hl}GgLcQ>oj|2i`Ko~5`!KEb!QD7@+I*-r$Dh6i>;IW-
z6I@?<v<C2BQ5!Xdc(1ENzd|rcoj^C_Ep_-+lwz`a@F&EksQ->ZFjcL00pzBs;m07+
z4D}ftKx58S=QV-sv()hmkbSm#<zDceqgFo%%(<%89g@ydr*asXukMTk@NIP)feX~V
zuY<!o>NpOF3)Ok|qXdi8PqFN2E>=Ij9~s_Ni@y#IOVkTzK>9s(IlJ`t)!)}3`%?9G
zO!LeS)RVZV-uzIVg9<P|Qdjp!zGdp#5Ym>bPfrHv6>8#XuwALXP0#IP^-gx*tJFv4
zg4ic&U<G2U)jE5?{ZqBxC*ZzDZMqV`wQ9kA2-c}D;eagjGc`v8vCq}w?5EbN_pSrx
z1~qvmxPPI3@jil`YO65PzEgjKv6;Kn&5uCS->bjA1Jb+Ig}abpkNVTskaNHK!2=+D
zK<)n}^8KJ5Vy|~lEmZ-*5%mQ2kj<afq3NJ<T&*)18BVI}IMAF@w-f{LoO*p8^8KRT
z8HX}lP{;laVi(oHI1JAGRc(rEXUyN!pF&9cT~+@E@DH`#w}}0z{)Dv;^Dp)2{m5`h
zovH%(w>q#o<h-J8yaLi!)%jPUtZV8$-vINv+Ld+tvR0`K(uQaz4%{<e)1Km~(=^SJ
zBiX%FKhqjn`aH)D`H7mFL9_45`@!|eL4)z$?=!i=t(ZmMtp<!r!$(1#mH%0RXO*Ma
zoiM9jt_WV${-D{;R=>eaj>IkFwngA(=D&=VWfh$WQueL3Of!v5bzx;zPx|QgqAFk(
zX!ivm&H+o6qGkW^7$h(K;BBA;3+J?Ps5%;BgEc}maR8w?QvISD`mRxGG3+p!uc=jV
z)sZz*{g>|UEOpX(pj=X~w1&k0sMF|A4%6y)1Li30g-(!VqV_P|rzzT><01Ae?f6&-
zyHq>VANfAh?i-7IUu!LSiZT_IFn=K61qwa^r0m-t0JTa(Uj@8gRv3tPZKwqrk7qoE
z=j&>NbV#s3H68-)8nxv_6!Ba2`)|?j{GtB#fvbSvAzU(LCN9CiVU^3*4JVVAABF+N
zs=%{htcpv=;3m6DkMtR!Se5^3fr3?;Z~~oG)pu~nw^>bnANsC-{XINu{D%D=v!?bf
z#HiJKIkZ%}{8xD1GLz0so$v{8Z&Lpaq~7*24*4_h?8jl{{v+jq^YGL6KoL)_sDjjI
z<FM{yzO0s-hO&)Nd%ptOZ>m=lko_%nS~4)^s<$N|cu##5hv1<#F6fAwS)~fuKT(D7
zt5qTWr>YQtjVk0{t5RrdgDT4Lh01~mod)0KsF3fi<4{CKONvr(7<HPxU>gK2v33Zw
zSt^_Qt<e4+=(5Vb@kp)q1$BMPkf#B!_vJT$G$=s5Hx1BUT6W-Us_l||pmx`|5!f1L
z?d5OCD#<iiBgJlGg_PNi`Y>zs$^q{N3pi_RxrsB>yPjcF9IWDlNNS_R0?-+v-qjVc
z$?7_+BBLuU^%~esRsW<HFjq~%5nbpY)4>QGWCsju=;0bM-%_<7%pE;kTtTF*Qm_94
z(LPZde+(+C)ia#vZ&b&;iVR<>v%Z3Wo7CnTAl3Kkb6tS4TOEV7Ec7^w>LU9I^<B;s
zPO43g0rQkvtt2r2Qt#M>?3dJ}THyD$`r=Fghih{S0`paEGFOO3Xf4VEI7wSs4Z&O5
z_PHQ7S-UV2C=0Z-6(IJGwi%}lnhUi;cLTUm>oFWCA8T6&Bl{|CE2o2-v}Ih+*{rn>
zA+}v>&NZjK+DBCZ{84+J^>s*V%<M<C%U_|;C$wMxMC`1Vk^*J@rNs?EQ3mTJUPQiO
zdhH^}@Vfr)Y+#PoEA9u%Wc{zxU^_)$h@*4O`TD=q%iDU7P6$5K5A6q|kM!%<(>2%Y
zPjp504f;%e>ci^IdY~Ed6#L*D-izN`6Iw3u!f-dO@xiHxH~DxGST)^Am!Wz19G(w7
zhV@pFyTGQtD1Di&Pl0Ip-*E`KS?RqTJgdH&4TKtpOF+8Xufj<%>puM`Aob^5hO!%d
z&<Wx;edT3fwyv0lXZ!pdr0+|;1WrAYOvv5)OgrE_@%P`L&~MBc6yZ}V)Ex<HtP69&
zbFK9pZag$MT8CM#t=94sq<v?tzy)9Ce(RZ{AhgZC_$)Agw+G|^<z;7$jtt|Rvh9Gm
zJbu7h06&et<beIS#3FYgHX*UaXRg)1uV!Im5Mx!7xd?t#$5a5?AvJj+1UaH!DhJ?E
z_3%5W<)78=A0e2aUBIbd=otsELrLD!zNS|-S-a;G1XHyg*fTPxY1i-_jX6W>^$&uX
z+RlBTGF$7=8L>H96}r3gw5jb;?D<-0?5vtAw3N>ftkfoR624P=dLe}PPFwN=IDD`5
zxrBVXwXS=RZ?9%?UcXPP+z7w}+G5Ukf6xkZN$^MQ(G{rTLt2x)z&xz|#nrhZ+Klsv
z{j80D5j2l!oqt3bPH2Nna6hU2iQ`Dk(^`CA5IdulxDG1kw12B0!!O!)+)N2;JoyUJ
zUe@nEir^KU7onI#^-VpHeYk$)Z^-hh{u`b4h57^dc)?txk77N2r%&31*e<;nc23OQ
zx_S<5_vka$0Ju+op7YH8dI>H|{GeB@f#9H?`8a|@`X{}R{U=>#r*%{>{v=fJv;NjX
z#E$F7n<C!{z4I0jJEiY9gV<^PM~=d0^+#}qnR!lMMDFMH&$u3PLD%pBu=%V0Ybj9q
zO+UwFw?Fh{oH72XzyCI3m-PA9P_V!CRvZbg=*Q0@!&UtYmi8b0uKd9KSKrD3?Pa6L
z7bxuzqr!6l4l}+^gtCSkm){1z5yl6nP|T4=@(U=#YsM$IF2H=<_!{lY9AkW}Bi|dw
z-6xQ5oH1(&FvlA|j0X1!MvbDtoM;SafwZ@b@;L}58&|mOFwI!92`JNznOwA+X&l6Q
zygAEQ!=lVFru~kzxyD+UvH7-fd@O`mV07IK;TIaMxR$ucs4)^5-Zj2!hYU-MuWKRp
zzL7%1TxxtY2SR*kOs|i89~nb&si(Qz*oJE<%oWDxCy`;5G5>MM@`<6g0I^Sv=RQF8
zHOBcmKv`$ZrqrJqCpgVqZ*0R1!Q5cHv<n$F8tc*^#FxfVx?7u#{)YhEVpRMNm|Klr
zWg+#~M&kkqzA?_X0?M~W^)Eqehq0+4sO&Uem;zaL8Fjd3`n?f6i1O_*IyMEBy~YfD
z@@wulUYv*Efbl7pnhzR9aTllgqtR>%sQhFkB_cR%l;R}wXXC>opmNL@H3`89<60x6
zoisWe28Ywer*!~4V<;C8{9^pe5%Ij?^o2q$8cCe3{c7wQ0n)!4%R`9$VN^MUw7-n0
zbCKbaacUTdT{imOg|sWizFnYs&G`IfDC-|%9|w%VW;@O;UN*;{LcUkb<cFbxq2}_6
zkZicQ?-3~SRr9w@upMbOFNA!f%v<9@<#n@rIxt6@clQB@H_VsLfx}pHQcvU?Z+5sJ
zz&FjhTYxgjJa;EJyoGzc!EcKB8lCQ`=7r86J>5*G3CtPhZ3~cnmf3$3v^(3ZcPmil
zn!~vdGS6H`?Y?am$`7^+%#_uLEixav8;lm4Yf1uh39b+a=6hygPQsU(8SkSgADDa7
z09<A^zY5aJ&8^G9eWiKZ1+e|teE%ZYequhx72nn7Bb-F9G4DJDl(pujr;+_L^ZU8T
z{<+zUp4MJ-#2m!-ncG$&_Jg^r4e}i{FaHBs4w*CWM%qv2kTn1vG1K2c_M_$iZipN+
z_n46SxVeQ(N+-=`9Ar;nAcCBOtz~-=yljnY1K=yx<$(}ssP*7okY%{_P7`E!)vEU#
zsEo8`eFsLPtjF7c^k{1{*Tu$I%egc)&MMD=Y`oRzD=?a9J&7Oko0F^!T-KXxg-=3D
zQ>?!>0A-r>71!>jTV1{f+a1=DTM^r7{n8tl-&-x{(CoH0^+wuWYhN8?*k=uzh1daW
z2VL|ZtP_oa`J>gg4q}I_rfnhaVe2FOipV@-E$@clXRCfuh;+;<$i<2i);ldh^Q3j+
zDa1}&<FH?Ep0R#<8Trmx=X(P47i+;*FuG`cz(My{Yw+iw@`tted*u7mO5X^~zpbZU
zf)JOjCI2Apnl<4Sl<yxasTHzcx4Ls3X|UbGL@>mD;|$VXu@5<jy>C|{aH)Ov4{-R<
z4&Zwo^CSDor69K4PFoM{uCV8EbL3<D#h(#dWp7Ua+tv2bH$df6ds%4!*V<LMd$!Jg
zvNO^?w<~cqV7>kHPyoNMi**CaM*D6qk#Dkh{SM$}JNW<@ePwr=3$|PBi|j_X+21rn
z+Bf!wM&P&I&QhR>9d;Ft7T?*OIpN=BPp1v;whz`su*W_=2Bi1dui*G{bH6>#Mus2k
zMsc8W(0-m?+#&nkttj75_Rt3**%7;YN3cC=7q||7$L+?`5IbSlTm>qpZG9g#Z};c+
z;V*XY4gj9FPZdM<U+uu>5aKtx3kTCbZT(l|`^z4EJ5Vm$PmMr^D|QDi&;DbVX0!j-
zUfl^A931F=Cx9;plDJs^O5pBaAm`9P?PZW<c%bJd1g{1@EQbsu13Qj@(WpQNmgx0B
z8LnN74t)Cqf;R$V-UQ~@z{5B}-W(q&Mhkf}FbMb2n-c@!p%7_Opw71tX+uC`i~Ayw
zfct9AO@Uip1#olVBA0Qu2C8wD@$10#Jz(@rARim$w}F?Fz;8!j+`|Cw476wlV!Hy5
zbLRJbpu^jsvNv!Scf$4s=3WQpfxzM?0Q@0PW+J#B3RGNyd_M)UDkF9@aQto1{5epG
zq>l%t{f)E}fi07e{ZwEMrqt%?KvDL5X9N9CqbTPBkFJG)=K~8nAj5^g%F00bH8AUT
z1iu9?UP0O)fvwzi_%qO|1%Q7CZsiW_<-l;dI9CHBzC`R=;8a-<yB?U>2f<+H(K~@T
z#2NZEVy`%7XpzI55H&yCxv(9<2<P(qD8oo+`%94JHK%Y89A0-SUxJ)toPwNjz2Ow=
z0?ctv4bINSJFm|Nm5I(6`h%04Ry)CVvQuFxP^LJ=IoX)*WNrbm8BSmZfU}*qj{{|n
zbC%PYdCt=lP?Y&j;U6IN0_S*ZP<h8`&xMIa&V;`ZTkNO}P)AFg%XC=ZbM#CEOPyQ)
z1@HrB9J|V8&e<jqV!3m&2S~4Uj{Sw;W9QbVQItK-&efo@-wClxIN+4ti|hxTyVoQ5
z(RrvN*#6{{Zvi<EI}dXW_h;vc`p9?8DMi2TgfsGG<U8ryaW80|cItBcJL7a~4&X0N
zwfaCg?<9YM*ssnSEVi1zIj`<U_CK7V9T5EK)SZE}OU}wOkn?ZnwH7GYRp;N&!RVTE
z<Vlp_U+1Ycpn2UXwgK5+4ko;X3`2qoe+22F!GAbm8Wz03oq<<_bH4-1h+yqC$TuoD
z{}?b|3tqkql+nS>qk%Fe_z-tH#|D%7g3-9(=wV2EGuW*Q@=XY4lHa7@qZvSXD_HVf
zWcVmJ;t>Fs1zWS1S`qB_1C+HgIH?=NT@^f!Pb1Awf)?A#r@^VUkzq}+$ahFv7hJ%F
z>d%6e=&7y`zB3JsHUuvWMr>p7g%Zf{Ww2}`U~Ufn`5Dr-1e^T^k+ue(9srtO2TR<I
z*tfxZIhETUoYe^#z6&-dzg@xU2LRk19LWumJ;C2=fziHT-E36A{-84e9DWFX&1KJn
z!4W5c@>8%ydBhF}o325=qruA65&Rsi$6dzb!FTAmoCqH07=9}FGPiF}2eW2?%Gsd7
zO{jChH?g{Ho)0eOrpkq2g{~m>Yp~@fNc$~#hJ*JX!EG18=+9uC+Y$U7eC{;_mxJH6
zhR&`AwZA~~TJRDbf`5bc{zQiB!5IYsd^z+k7wU$DW)_0*Q$u?=3z-%=MJt#Q>N)@@
zGeg!9$TB<Bu>pjb6S}w#+~<W>(w&?iI?Vln1)(x=2;K=DSqGFwq1($Nwm6j91;mzw
zZs+{yz0i=uV6-$;nKQ5tLiNuh?W53dK`>et+RxqR6`>c~0A*$9#d2V~Dx_{iX+H_g
zKZrW|G&Eorf;FMeO91>V^mk)mejfUM9by|oMY(eMMQHXs#5RRq*#Nz44xJ|ESE0iX
zgY?!=cYfKiEmRRVL7Lx$o_H6r?V-&-A+{qlmm|q{p*q|w+!eZ)^}ah)cqX#%2_2$S
zx-V2^EMogZ>&qhF51|7?pw@$-#oWC-6q>>n<ex%yRwCb#Q27&(<!C7JX^=h^`g$s)
zJ|24EXP}%6)ud&e3f)=}+0TShxb=EARC)`7e?lKG0kL7>8IK?sAFgv3H27vXj$c1a
z2nV@XKQY`2AN`t>!XMip_Ez}NT%=77|Mo31ObIu{H#_FE@HB46O%L}j03l|Cr?Wqs
z8E(gE?yPX!Gz7E5XKzKmIbo{=VspcHYz3pY!$&j(3&Mr)^F4D>c-cx2TO8io9#po4
zf55VX`Av8;_Y}Sje@)Zh9=<pn*>{9XRzt8eT=Ob|@4^SUO|UCmi6g@I;qgTf><;%^
zhhR@QgkxvTy<wYck%z+@5&=9CKC5AQ@K|`*mr%i}@YFO&b~?P5o7ZQ;4JJ`N;o{XH
z*}3pjdl38*?mol<3;fI4$`#h4r+-J5V$04!BgIE<K-o*w{0Y*QY}5n7mP)Awc<DEq
z0H;jy0+1_Pj!XIFZr=`^@;&PUQsMLpl(phos<u*G3&>b`Tr%*h%)1p7s;WPNX0<h3
zN3NcL8|=**LplP#X6vosUTe65_u6kP#`Bismq4vfvF&))UC-sFoC|M)TD=v&f?9*k
zhwyB;lSbI6?q|Shys;M`O=jEz%%-*ZIYX;delpYXz}I+x=m~B`K0Es$<R7Bm#%c9v
zbtbMz!8+c=vOt@q7VUxj^VI_QdJDT4TUdYZt9Ku^ksJR;*@G4V?KQi=qY&<Od_o4!
zqwU&zk!g%=aJYNJb`~IQto;cWL&n)NJ0Rb9`;WGe=uO+?TwsEIkqZeE?O#U%ILY2o
z5SVY-@BNNovfXYTbTG}{nGKrL?M^iSoMn%p$2QwOM#prHU75Q?bM0Q7r@w9gACj&+
zuFLBCSEir6_ntY@_RgGT)5_MjrDkbn!z|6zGGoY4M5cns5?O-CRF*6SWbeH}WN$%4
z1%B_-@2~SZ_n!AT=UzU~eeONy+y}*e0Kyqx`@*vbMnMMpA{pDiK;H$%=G7okjIeLv
zL^NaBUYNbeh%rKE48tD({sx=fF3PdQGV&-x5XXrA6OHkVV?1yPjLx4x5*c|MSV&^j
zh(RthE(c<6t}s}%wMb@U&7m=ckxcKTR7Nia)zTQjF7PFt;e`tMg;yE-1K?5y<GmZ`
z%Vgv~441MPorP$;#(0uu={h4+gT`FOj#`N1G1@kuF`w~Z9W2~n1YdyH1=y)$S_>K7
zaljQb`ZmEr31bUoSxXsbn$cIrc<}|m%Nd*6fU95(h@hpCvHnwtR56zJK%|yYLptji
zT#7c=GZa*m(ZG<dhh!telS-PJ7)`H2vY9bON%j_oln<S)j6Gz%jj{U{NIQe`59YIj
z(YzkMbTSS-4J};^XZpL}WGw21mTtzzljys}(0+@7^)M#QFx$%zQ-ZsXG3pC~&2=dz
za)1#+$F@O+=m2m-jD`*98)npN!HqC}9)R^x#vef-V~oAk&^gZdlcMqy48K)y;x?oI
zG59&j7^I<0F-j=|aEEb)s{5uHPnjWdkI{S+<UT`DjJ`QWQ8*;$8PSwlw_%pxA5vpC
z{w2M=9GI_>1t(@^D2Ou?1*x?E4%i8}3-it+7~cuz$4TgOWhNznoMd{@gt#&HcY||h
zj_!d@4`#X_I8UaQ-j80)|8)WG%{)%Oo>R=R-QawfRTO0KWrmYyXPCJtc3pUmx#V|{
z5az`|xOAQw@+JVG%n~FD7KSk&{Tq_u%+nV9H6xh+EP!MrbJzqe7nlkPfJQNYrm$Bu
zcEE7yB6Es1HZja-s*t+GblnS)SmsJK8snIS6kv~MPH#eE0&{IXaEZ)GimfIwLykb_
zW#&3MQCwkq4`3pbnTsiYk-}_KU|^}t-{WCDjhRbv{dDFg+Gt#5=Dh%T29r;_z)a?m
zbZE(9zI+bWvzaN^z~wM!*22&=<_apQyUuiULSHWP@H+UC&-|5g?>CsAY=W`^X6r$S
z6f&2T!9o#}{uwAvDZ_nuoJyDh6yz&q7Bs<L8S^)Cu$-x;vcU>w+(RIh%;rrnRK@(6
z^2pW9o#POxVea?<I%}B)OF-(F=Rb!?J@eBFsBT~`qFS3qrk^876Z4u6oM>jQ*$HJW
z%sTorwlWQLm~LY-T;XRsGgb!c9n5Sx4s|l+RCdwD%zOdxo6I#7HS1>j+d=XcGnEU;
z9;OZLZ+e-Haggj|u6qKK{Y>8i_%gt}TmVCZ%rC6y8)7EW0b!W=K`YFTFvDqDN14yg
z13t!F8UxkiOlB?s6U>fXXuQpQu?e0{GPiDr<P<ZCRt7tk&2fy+ht=r@Nk7&K2JD?>
z<x$~}KP#QWzyU1n&rlY~3bq0s#H#-9J<b~Y3Vr8TZ~p~A2<r>Vb)9D|phDG9);c=U
zg|XIt4-(G$ZZ}8-Yv>^0k*u%jF}%QPr6oOz6-rNdG;1N130-1Ug@MGfczfVW9P3+u
zaPh3Ozd<B{wb25v6IuJCz$LMq&cfbh)?b^U<qFH0(m}~AW;q&DSbmjgOl7U11tN{r
zgnuZ#FrD=^?G&!E%(RusU>WwnrA(GI9wdu(auD!r){b{Ta#-E8wZF!4N`d5c*2u>o
zxvcVP_>#vuMDON&RvH71H(0joAz8p$S`1tv>nA-Xq=;3Ni{C^s>l<2POIWk?x-MmH
zjDchsi%EIpa@IzQk5;fYro+KXRy}SIF05ij{sh(4tdNsXR>O*?07NZoIptOBSdCOq
zRL_!AuBL&ddIpk>tbv0t)Wpi#4=v5C?>3{cg>~pOM%2p6eiMK;)*;$xw6nAgknCXb
zDFxHXit~d@-K^}dpzIbamiA0NEcq}*dRZ%Jw0*31QlX`vmGv1!23SwhFLIDoM~S#0
z*1l12!>nEkACIt1D}ftj`BEv{7;DKwh>Wv*u3<zItjCHVd7EXgguO|Y^8mOhRsg+4
z@37o|K;txP*Af8kvg)b&WQH|BNxFNiAFOcVKC7R?&JS3tKfr{{vW_$WKF5+9VQ8M^
zw*}U1*x7XIvt{=OLZ==3)+IFBv-?@la+F;`c^e0IM<h5$_9m)0bz(mm21#djQX&R@
zjQwT?%pPa6=``%ZzCk~R6YR8um`GQ)=ULc0$?nYnz>O{54Y)g7^&@Z|>~D&I^JFJ{
z14%EoEp5C{vse8CLq6<0H}v_km;D6p40|1=P5s!m|AQ}Q**T=spKVgZUI6>T8IVA>
zBfaW^*lz#BTnDp1dlT?;?A3pQ3t<ZqVc|S`_9<uyWuK?xLKu5J#pS};L#tpmg1wf?
zwIkV__rP6XXHvOo6#HY^zDKjgtKs!U_B;5`(+gwRg>*`}#QynLG{&;O{s6c*_J%xg
z@$4m3R+hkS$$_7V>_pnsB(d>Y#WTj9{}>KlVZZq<;K}UE6p~J1r_up0mHo@3fTyu7
z2ho_${`UvyyvlY=hSwSFurxGgvPUu@nZ*vEVw`NY3mtWH*xFy9^BQ}8HMr~SMRbJB
zWnZHRa~^xQBMjxUzs8jhoQ>P>f)ucKM8lUt_Rs}zMQr8@SSV&Mwugl>_V@JTD`yu{
zbiIQ8+X2i{C3{a1bXKvQ-i2f}`*$@A)v({DEJrQ-G?gOPu?u`)ub%y1Wl{q>Nd#OY
zyWkx(HnG`VAkFMIEYQ-zcB126D?6hYLuq5j=K|i&KJ*Bzcd#=KLZp*D>WaQD_HL??
zy~&RK7h~vV|3YcpTkO~KFxnn=7*%=qvQKUWypJ7p6(arYuqV(r!0x69$spVGGem~i
z-yXw=hS^<Wcs;^?X&<;zcK%+FG4>1b@N=Ba!v7t|>H9hhPTXcc@(d&=*{A3Mnqspk
zUwnt{@dB(*v$d22y2}nF=V#a#Y2CfYcHaiTefC#W6#syIW<MHd+1GV&VvfC-V(s(n
zBU><8HXI8ZeYTuC$HCcg!j-UK&k3a6(@{=bG2jlIA1E&F$oYx__fDLTDHQ6=G3Ehq
zj1xnN=@XoaJpj0JPHzEsl4DC@FAolv_EMglNjm3waV9Bdewy>c0f_i;Zcre>m*Yu)
z&9fXX6&?F?0%Ab|IA5Ot3FZjCgN1XPf9ZNc2xk#3hhZGwN^s$vD-2kO;9Q}!T@=Ta
zmXc`BwgM=-$oY}>d@-Cc6t6A3#Ce7yjj^09bX17rq-4XFc+MB}=SbkBAApub&Ymzx
zCUL%ugO<x2Bc)8PaH1%Zlg#;zBK9d9Z5#lpoXlj9G|q4v`qJ^y5$L?iVQ^s~gOhs=
zW-~e3UU;3w+3*llXLAm0#-Bfjb7Ki4uW=mCqwhLr8-<K=Ip5<;CJXa8#gzTY=R8cS
z+YL_WvzV6x&RdkWE93-z1?xqe^%RgR=KT2~a3!4QX)Q11xZH&5GL8|yZ^Rnx={c(4
z+&l~it2uIt)z)y{-T+d|S-%ge>o}GEFjUV8dk<O~IN=KcZ{&PUMU+jP7jFUA%=u(F
zL|Qm6z5#o!oCbP3wQ*L^ZJBn?opG4$;CxO$#ZHcJ5`ZqwSxP<L<jhk@vzs%r7PwoS
ztd9Wb;T(#GvR=+Kr8oLGp(SYS=e!sUzyOC44JQUUb@*h_!XZvC)$k8<>ToG{;Rwe!
z8n{u;!5%b@ah}=(z&OW`HslkWYI=R%=7{vLH_4GvfOCpdK`*d79M2tqPjd=9(07+}
z>}fbS!zptB;2!5ua_K(j2`Wv0z;UIR<Sb`DrQ+u}@2N3M^PJXFa5mg}3Ow0zwUlnK
z;|5UV!GU{?1)L*y%R)3daUJPz<jnOv1i&$FM+f{o&Yf8U5f^UqW{8~Nen>S{uG~5N
zcZh{2xsPxl;>K;J0IoY%<qPW`+?f4P?a2+MIFc7P@Mi$Lxl9hYQ``)Cubk#;srtr;
z8$f9^Uv3KBm^j0I#S>cmxDQc+;Vjo%4}d?{NLk_lZZpkpAotZhP!_~h(%T}KTPJ|^
zbKH_QFoPjn&+j2}o*PRs`cSU;b%=y<Q>nNhoGYijMg;fgVf00EPyLO?3*06O{6=xF
zD&SHycaV157r8%Bo-c;$MQ623+yhAviRCgjqcM&<rh%4t?n_5tD1qxvYk49!mm>B_
z+-fm&CUZ-k2A9IkqHIhmcOm7M(zsvHU66F{?NN;AD)*uTv}AA>P_i+TyC4C|vbbMP
zKv_07j%sOhxL+mX4}OgsNjaA5+(i_y%H?*fgM~b9Sp)$2+@j||ZgA&lXH~#;EJj};
z*Om5CMck=p;B_&#f=+HF+~uUYlsmr_l4V?X%59f(U#7%v1$Qa}PE>Lw26$G*{rwM+
zYVLL~xLd=`MF|_iP?H=0>bR~Y=&R?ZL}Ppn+%MmSy+-co6A)?Q-m8a5GxzA{AZ^^{
z2zcGj{o)QJJGhSfKyGqpeuMRH?w+OSyTx^<^{kKk++{TObL*0T8{mrR7%|L!>0fv@
z!u_QjxKXa*V+?bGyW$(zyUm^XF9*oIM^FD0*M}CXJKP#ExM}W0G90|eRZ#%tJ~#0P
zXnDYGq~e!Z?qh5in&WPyUDrJK01Hmo@GP`Y+wwli1!u=wOV6}DFESHmkMjOq2Dk%H
z>jr=$ubDOrPQ1IcN;&hA$1!Kecp@qsInEp4pwETZg8yW^@B}Z0?hCl`tPkMsN#64-
z0C(eUq#{mt-pWw;>A{N`2Edc|4FwUrc<-)(h&ONbZy=|5`+b2s&AVd{Ej~Qo6mY)0
zWV(@YhWG0O%#t7PodCek^1jZ1h(E8NPFVrGda8yE<T<Q^gF(Dyao~b^E_5<I$2&yF
zxe%U)vN7j*e^LlMl$SvHr7+&&)lePIi#Nf+2ww9;Ad$TFERYL40~OIl@t)6yWHfIn
zRd-zE-PsC24DUL=_p|U4FMKOVEN>+hbS3Z#CeWA2Q_@PC#B<vUd&#`tD20*2YoPaE
zD(~Y`C`;pw(_cEB*H{e6tGsuspgMzB_cHo2d8=Q>v}W;^D}l@A-E)G@9NzkQ0Iu=g
zc?pKD^E|0|H<x#o?B($cbo9#S<<M{G1}|VWNC9tC5=bHMxe@@1cuJ~1D&|!_3{t{t
z!`HeNmhzsWH)R<Q#iV#1c-kMJtb&)D3uTo&@2B8W70>S#0IGRMDR@-F+mVmHTHZ1b
zNY?R09{7vZ^J*?ZO9Sr_n#g9}2Fm@m@cif})yjJ>7JjzzxLP!}^G@!7WCw4s1mq@f
z@F+a%=6&{Gbe8vd4U~=WhL2&EMtN*%9OFGqZ?17(PAjxb@UkfJd7Brv7ThFnEu|%=
zcrN!agLinA$1sLzp0^#GxXW9w1#X6Snqn;XcyAp6cc1q>ounS{w6-9#yr1Zr#2l}K
zLhkdtCc6A$!+(U<I$OSjBMjN`KcbwtJ-=={EF9$z&>z)-{|-e?9QirhL7ez=6d88r
ze@NAA$M}A&aN;<>=L8y0@Esn57FYhNRnU2ouN%SCx$z@@fQUOE|BM+A0$;oleV+W}
z-!LLC{wAsk^X9+&Eqpn}ucmT|)BLXtQ0Bw;coX(~`R=s4IKzL*5siNQNV;xvmjC=?
z(BjYkqZC{Ke*<mu1Nk;o)fvQ}`3+tN^V8_U$2tCDsud04KS59Ud43k%tP15XrJY<D
ze-YLHg!6|foN|G`Y%6p|@ommy4AK0_F}QS*->id33_oEB0GIe2T2y2C5i#K6_)6N;
z#Pdbz7+3;7`YAY($j^HhToPZafY+D#&NFc03jekT0LlDSYXMK;e@_)gseHem;7c0+
zGl~$T^P`zCdzJrqG~gM08+wao@~bGwmBl|C3}xB;wTD1*_*W?GevKbV*MP6{Cn~_@
z@|PsTLLPtcB;fh{#dK1<!H=89zzX;WCFm>Uzn6&d74aXY7fLbzsaRMq;k$p0#!~(%
zO52t3-}iyea{j-I;b#Tko(q>M`9j(xR`E+6;b%4f%v)%z;UDlsV=dp6ic#wLTg!o~
z=Vwx&pn<<&8$_D;#olnDneUYcWi9*$szzw#JK&1P!Zv;c#mn3I!>iHQ!RNI=vXlQ3
zRfBf%i|CAglm7(S>*jxh8tsL*_;={E+shC5FZIDMSqhPUzWyTs2KbjafDiJY)dDcY
zf95h8hxv09mK@>dQgz%Yf96TR$N08XmOjp(qIsF%-;jcv;;+~T$vgZ=T0Ext?^EAh
z{^8RwJHxM|T7i4~St?Vz&$q`VkA)BTjqkzhS^gp~=$zv}_ASOf&;L6b#6}>ZIkOj>
zpc`RF1>0$_=pcBx8-^SOvoa7T!Rz$kISUHt6nRV#@D4<d3-;|nql>`70+ADfD!Q)g
zDv(fG`J|x!HaznX6kLFar{L%7aKcN_O9fxvg2rLMPYE)XVbG@q-j!(d5xBQQ#8<GB
zawca4-YFn{0s*b2X9YJX=HV|;2Ep9`!Mi@N7bsXi4tqg@>r{{tEU4QLv*!fkcQ6wn
zf+;#|ofoX3+O<$Y4E<2T1dR)U3m1I61|kuH;V9rD1;QXSUJ!gl)p1b*85J@{3s%we
zToiox0mcv`=t_jhCBa#mrC32J4_usJLjWwq3tkk!Y=U4NWkwPOf8uLJ3zG!q`*8lU
zz$!%J6~Vf2h$IW%pr1yHU|lS%rwVfSKuek+{VRBu{{Jpz3W{hA$r2c-0xnxnOh5J<
zfzR(SbWMQ&%!VgNz<Lc@as|(wfa*NKnvY>9Um#ls3k8COzXMk&*s}~y6bW)^#Vi)A
z9|Bh*@Jj`*RG|JElI4PjJ_T1HXgh@|s1%e?s=7+>mm12d1=$qrs1a<SpMJgITnYSa
z5Nx7DMWf*GN;EbJdY=HGSrEP(k}U%1>zJ%oK`7OGw+UEu-L_ruF{QgY1Zm&F&rU%%
zCB?b~i|PQlDL6I>W!-{}4}-fUXnzZmJ%ZQi9ndS-5e(IR0x2a1`vse5p&k(2p}*gt
zAbbiV8WKE8Kbv8J?;yyCVBQvFRPZm|{~r_VUIoCoVC58Cx+BPyz?W&k;}jLUEBI#=
zjWdFWX?pGnK3)Q4_XTMu(Dy)a-WLO#706DZZ%**T>##R3*hv5z;qgd#W-I)d(ie8Z
zr)tq>FMNi6!bgRdy3yz)Y@ll@&cgHA02~u$(01gwaFq6+F2Xhz04Icu68PdOOrA&M
zN#UPAgSZJx=<Vw%T>A-p@e*$N9gW_?SEw-bl<*76bDb6*y#wMS{CYWb`U>MH+j&OV
zbQ<>jg!PmkJS+Sw2Yvp+Vk)5t5a!d(#9-lR$~>PF+E9&Mh%osw0Oy6RgWy7izovkM
z32!dO-!@!$-2o0p2-)8P7b#Rk!QKVo+@qM!C?R(ajnTrN7DD8bu&^H_R=BzYQywS$
z^gCFH7w(}jT7uAv7OO<z6lH0Wg!d?ia#^_lJGgsAs7-}rvasZ3h@=Rg&xhBkLaPt@
z(u5&ekaXecNvOUm4BrNqvV=v2;If6S*_hoNVe2p&uL+k^vgW!_Era!3VcsE_%@c|~
zgX(;tHV%C^ghtvA775qW;ip*0J`dF;!q@2;D-~Y8jm9#eJ`0WI!mYUgR0t1!ikYYs
z7Jm;5RYEZxxvPcSTOe5@Ji~$NT4BIdkOtvWiqtd;n>r!VB&;=JD9ysiCjoB}o^XVP
zR^d|0vb70M{<nz|9@Jr&9YWp%;5voXlpN|38XpCBQ}~4qwDbrMFGXXo@Vh$T`h+WL
z0O%LK{0#aAgc`aEKPX(m#W072nN-;_EcBoV$cV6gIfgkZ{Fy49$AkyBLg%<}N((I$
z!mvpU<+d>MFQ}dreoT9*X<;G-H}48%bXJ=Y=29WfJ>fm7K)o;gK#j%+LPi<5S)ob|
zvva~T@4>>naB&PcI}wk5ruL#zJBS<=3CX&HXf3^x9Yq=bXmk>d`oo^HD0~uq$3(fW
zfE*W{rHzY=$bq7vCqz42(C8`}kb!d-Ra2#jhv-Nwoc9!^(x2E%q@l`AZ_$PiVD^+K
z^&0?Ai}Kc@(MRM;cQ|}S@74f*Ms$#Vw0@$EwC_19+RzS>K+#Gb`hpObz~3)eR7Js+
zbE2{V^o58zC%~N-1yRN!RMbq9941oI(-AK6qS}H8QIi<+5-F-<;irE=G)UW#i=vZ-
zXp9m0%wPsDiTvn=5-aixfM;<c7kWj;i+-Ubd4kB5ju?reua3f{B+*MD7+A8XiMAXm
zB6|whq>4WL8CudrlT@CcE{d)|<5iKQ6I_Pq`#Gr26#YY+%Pdh>2UKT^E>SH@j%X<#
zBG*J$Y0C3NyS{;ze9_?^kQ<_p>Eu=*y8Q&~6^cGP0#YO@4nbeBXw^F4N<>m4JS!E|
zegJ!AqJN*ph{{EmUq)kv=tEj3szoE$!PSVIGGU=s^yeHVq)xQ-8F2NY(A99FLG<*~
zkZcsyQyjWUwA>xannjY|Akrd=+y+3aXqg+dw25{ug@sPh6#;zd64e|5{HCb=aWr;|
z%oI7fC3>O;@E#Fc3_!1_mhM0GiNffe+Amr|--s9zd3}uu85Xf`!@`JY5ADcCMYb<P
zWK6Wn3*5NKaU--$hz`gwXSYSQ{s2sho}jbnl<1@meRo8E*2CVkXk{*R-V^Pm(D;3k
z?{Aow2cng9t7TTi{u_OBBDXJ~dS0|-4ytX$GJ5COibWL1v=hHbe^h&M(kB?vQL!J@
zxj2Y>zK7&7@y@RRKQ4Zo!e}lyDZt(d@kjKNauu770De-OD1wNGc+oDH^%S#dbK)gd
zt%8WRSU3YGPKi&`dUjgucomI4;y2%bGGFma`yhEn9QOp^e&Q9oVD_wd(GH0Ci_g#_
z6CmD0DXl>9!f)VNkoesIaKU036&9WoNA*Exi1-L?QO}E4X)wv5;_)_cVdB>*Fdr`V
zr)^<`_*xZ6r1&c;ExI61t^_Vh+*k^o(c&c(ZoeqrO{t9-aU!KXE{Wag;2ta9w+&pJ
zc<pEKEMBajAbNths0Jia%-aTdl6WEQ4lj!ha=@>M)7}LjSzLSzBT5nHuSH*~_+kXS
zP7_yqV9@E}+Jhih#bXSJWQh0Bfhtq{=HpP7C4P)fVA<lAX29i$EkD7~HF4?35V<Zs
zNx8FJu_+W|$P+hFd_G_N-gi)aL#*2Xu0YH=0@a1$VguksVzC_n#p2z~=qnL3X$>hA
z*QR5Z%EZ+lLQA>$F;7^i5XVqTq*B~PalR_?&~wmIEq-$c`f9{aQ<-+HxNQiePW(;~
zaP{KB$I#ax<^}=RDDEf#*Cdvu0^TgX@j1-4h?(@BZWR~P^VcSxAua7<=PTek#G)qn
z(kTvp4<cP+8D-UPihunaTDrx5j6vru@e}mE?Gb-YfL`%$RDU-hj`|*wgW@Z1VOod8
zrzwv<EM7td`6J?6%h5L~?%D`4CjPw?gB}-`QG97aoJPCK+v3B^plni{OI}Zje<_2#
zJ7Q;=>uK>7DjmKn7E!VHjQCU9EZh_C4uZ1#;t%Pq{Xo3oB1C4zD=2d?C$<&A?7a9s
zg->lHPJH~~Y$c^_khGJGz7L$eWSH)79+fbT0p}obr>&o(WW5M|P7*T(4V@()jzY^Z
z$&<7o9ha=R4Y-SB!5eVmgv9+NNV-aDH-S4T`Gg8l+$2kx5OJ5x(3E>f>Q}-~Pf6Zk
z5HCsp8Z>%KLTFcVO0u9F@Y50<>GYAb(UR^fNj?MajKqgdZhjI8RfnIIbpLnZK*FJg
zB|!2bWp@H4T`xjQkVMS~AXxG!tuN;!N2vrTMDm<Bxbu=DG}=(f7TQvUN!~k*Ne-9v
zMuLlw-24n&q(o2mj4w#`d;k(9@$UpYTH;HO=tW6O1-KZA{c3o2N%GTKD2tV>=E8|M
z$tIfJc**D&@H0Wep!{E=BzqrbB1v+IzRYu3@($uf3$I9~ngCCh1YLrK6iKiZT&g7U
z65wf)j!D4NC5IZI`l@6v4_Y!LuNi>Ll(bS5JWH}>47hAbPb~n~C5Hw8$d$B)!LvNc
za;o{xmuT97yCK>6ApixE!S}%xN`k27q)1X{gz93+ZU>kxkr*goS}OVSI4qP&QlEj&
za!FAYxC#lo7w}36YZ9ufB<q%8nAMWod4ShQEcDB&l`Nw8e4XSdT^z5MEd3554U(tc
zg-D~M>nOM;Ns|=tX32*waH2)hMQ_Sh$y=51x=r%r2;6O#cz*=0L$cy1>~%`2KLyt%
zv6DjeP06|^p{!dXqzK3@$w%8^s7JDw*4<tSYYBArNy;e8-7h&p1;_)ExUYa4lngzL
zfelGkeFB}s5_t%4Ba-clplnp~Q4yRNlU$~(^SC6E64MhB{O<ugaT2i&$fV?<&(Jp|
zky1(Z9m!`&P(3YSz6i;?k^m~SosopnS^J*klT{G8FL9u)`vXaFG@PH6j8Gb4PGWNb
zX6Ny5+@aG(+S3kVE45R=T|4Pe6#({9f2!R&Divk`=O8`!7epMTreKITNegS?r?Yeq
zZKaP%Z>)sQ<I<!J5OI-;`e6Np^qURP;wn{9O#GzOj#gSX>GAhL+@-;^=kt($TMT8M
z(!lKy@sb7}hB9xdhEg}Dq|!eia$35a>O*~`8)#$gD;=<d<QeHdewavq>F>1i1xUp&
zqAyUo$%MWjX$93e21~!8Yq;m6uGwe|k=~ks>hsd%V^AF`-FyU2gh}_Rp*ma|`wg6k
zke;QJVx-h>G0a|&ZgmANN}5}TzG!JH)#+Z8Ze9wJ80le(AzhLRi^0W8-ROo_ob)!m
zgyW@e(V!Egb5voIDAmlu&m`&Vw5Po+Jw@58E7DAwvt(%k%}a{(k8>cY(u*%(C~4AD
z6!TA)9&QEhs&u~!BtyDg50WW8GXjz&&7m}Pwsexht~t`-g&^0YiFByHE*+-FK3DoF
z6I`D3XIhu?rGKu4XE&sNCP)@YKS;zMr%>ubG4UcPpTZ5rQez-SR3g3oDy)}Ed$J)}
zCVlG<*ejP>e}k3^>2Lx_rBv+(T$MDJ!hO|J4OKeTNPC{fz-pzh+{Db+NqySTS1;|H
z1J@v3M2DD0X*nIoo209LhA++1HFwb1BJHG@W2^Ka{lMC!yjXbFE*)A6$qwmb7Fh3;
z9;3`wmvnhC$W7_u3-GgBDwAWFx1<}tfn<+#!T?;a^t}>z)+gQC1D*ZSEiSMyfDcq+
zJ2EJ}Gz-Zg>3v+dUN|gGz*jgIj!1uc7+OZ9e*ePHG3kmis2-OZDL*|SO`sq99qEbB
z0hpHlLf=oiEA^%f|BO^oh`xK$*l9@KmwJRj*#oHumEg@vgI@+WC;dPTz`S(l+pu6G
zyV{ST*vdSPg0qwTLAz~x+3S(uj>`JzaOWVK9R%D_mf#P#ldO>vjn1<DA7jwRWC|*k
zI4-km!N6Q(=L_NI3EA0qVBJ;r_J{E0q-@_HI5(M^3LxBN8!5)(Av;7V7*E+p^dj<-
zy+biFZ`p1?s6Hjr4#N6rSsOhaKC*q3nD&)z-3&u#WYZK>^OJo-!N0SzE%dwgml+?2
zvH+Pag%kp1@i!n6BwKY8!wi;n`k?QetTP`23y}@e({WzbLqYUV*=Aa=!(>@h+!8K(
zvIUY6vg{NzM#>!M>9`<sG{8`l>{+_j7A-qR>8^{io%ovj!WfyEj+U2X$8Uqg$~x)K
z7$-YGxxskZ_kQptLH3RYV@Q;Ze}Tp%*-;K8FU!tS{N;*l6Kx%mWgBilS&B^c3Pe(6
zi`N2|CiDLTE~U$kIz!~D?59@%$dD!O2Ru{evj!qrvW7eWvSs!w;aQF>`XBUNlNF}}
za9uX!3ocjI@dUKw$)2DWX1=VCYJzXbQg=e6Ko(4q?n2p9SMUcYl66wrs#vz>S>Q@!
z6Y&6)$_m#&b(w54ot?^ME4E@@DrD<vS6L~0^kXzu$&OPtsakfz4vjUk$P9?o%4$XE
zYmhBH2Sbgr5Q;80$?i(vZnNy*0Qy>FZ%}<mt8C#;G`7i#UxU4NnG5}-I%KJIEbEk2
zP~lmZtkNDX-ITpg;r4D>$dAC?lJQ=Lp&r@LN5J*UIttL&CtEWJ)%~(_Z=-KOW~+kg
zL78(PM22L)T>)-bCjSn~Mr2RWd2>`YNq^Ka*|lT<#$_Cuf(hAGIy&E$eIbOhNg4BV
zXql4Lr~tns`zsspX<1+_9K0)wpt$~w%ykcx-IF;4fx9oeMiJHrvYyY;I4g6YAM~7T
z4UJ)5wx5m)HgYdBI9qupRb$)9?>NGqy?m<`_KwQ8(n;Sz{z@UtI?AIJFytg(Nn>!9
zm(4--G5Px(XgMxdehYw$To(<%3Hc2=R=dh~IYRQJ{6q`Py2%&0L&RPF9S0UX<SA89
z<|&ucyTePKcn~7qatp;7PRVO8q4BhQS2tAq$Y-y^y01K)*0VG606Nk7$xEjpa#k*(
z&85FQ@pa$=<hyBY4U|7hg~>tk;737%<%OAmpOasrn&1%m5C6sM<Q?=ao=~~jh(U+R
zi|&Jj%VVE{g$Vg79>x$U*M!2Q3vxZJL{ai(dWb~J|Je-gqI~sJ5Q&j{Q=aRRd>bFi
zV&(o+nHneGO6T`@`TM01Ns#B$g_uNnS}Yoq<ky~pOPA&6+yS^Emp=-3ljToSbU964
z`zuJgynxQISLG}E0MC#o(Mpsl_cDNF$v>yRShifugcCXPC^~>&lQZaBAJ^p%?EuM@
z4=CV7p8P&tB+Zxaq9D)>`9uS71@iqA7cP{$n!pvw&)@@E3ybA9bx>U*|8g6+Qn`VO
z;L7B$Rl-8KTpNwqt&nFQfoGNSFn9D-$+h!PT`m88Ijq;nTPQhOD=(pQYMs2I54d{y
z`4K2<kgxavsvG5XkpMKwpQOW9v;49*`dZ|(8St!C?iUOTZStX)foqq0G($^=e9;a}
zR;Rq{ci_6@wtvCwO?d?ifNuF3IxyantL-4tBi~7f`d;~ybYSe0fBqu?{qoKKfE$oM
zLkGq|`P)?II3z!<0U4G*K^21|@|;oV9F_k~l@??2qKAPSm$!`oFd>&~Fg>^BYv}wp
zDgUzzeN*yPv})Xu&%J;#Ov?x99B@~@{CW5?Bj3^jd-vo$REl+9?nSjD59A6RRL{!4
zxd$zC^0y)&GB3ZGg+3d_>;It7RuN1$)a?`x&teMf6&)6EM-{&-(C47|nf4QoidTOG
zz)4Y%1w+n?U%O%Um|{I$^Ej?3NQS#EiUm|naYE5ROP8xceE{U7!kJDzZi=Wb0NfQD
z2cg<SF-@O{@l^ax+cYo5X*za#D_ZEyd`jUrjmFc8FXzDdDEKR2!B?^GJ;2W>ax!7T
zUr`o^F$5?+QGg3nSg3L=NYOG6KZ6y^bD`{<;^7p)LloPnM&i7pkV>CJ6%A2P7N+=o
zIY_u->t$$(P?!|JMJmSV<AWCzwzTt)QtVX%9<6w!4HhmctaMR5MzQJ`$R)))l;Vw5
z+$x8bIEBdqE%Az)eXx+A@S(LeQK1ZhyGe@2=<|-36%&O3Tv1d^0G_OvSOh~UiV!-Q
zq$(bxfK-~ohR)jQ3OOZYt|}B>5Xn%KQwk<i@kTzlEJgF9P@S!?`xTNo3h7tit|_ii
zJ@j?OpKieADt@PhEKl+DP7FF<(X|0)Zz%rBM_++rfC{|}6;JGivLeN$Y~YF&DfRHW
zL=k-jxKf2fDjY0ROr3=4azy}zyebqQzYQlU6^H3#7gdVUQ<$u3Me$3pP@~XM!Dy}G
zqXq!#6gISG)hiyRKu?2W84bEoVM7-Rn-upK0?@3eIsgkTinJ;KS{1x&fVU}%6JWhv
z(LwLc4#m(z;5rqrjX+tK;waTJ-c;nK0?@7al@_a8iW3#+>rtH84$`YQP>sGmg_4c~
z{fa3oEDR{lF9I1<Je38VLyFyWupL%>z8b1W6t^>>b5!xJ0Pr!z#%|2SxMGZ+oC(FJ
zufyHj_%i}9si<54)l-VcC<A^+kw}+zrxkyEggLvb*z+y=W)vP&HE>UHZUX@K70c-w
z<eVaNFSvQdQL37=QAX%s!B)vA0NhS_d^0?=S1zEl{ZS>xg=b88o#J4QN|ayW8B@;w
zibiLpgfd3Ql*v>$cwCuX3K19OYq%D+@PyKy?zy=t2MrK8sq9Mu=ce4X5f<E)YpF=n
zL-{0?N_Z+C{S>41QqIr@#9OIK0C!4hpfl`gC7W)S_$aS$hCN^9o3uqeqvX@J*H3xI
zf<d2EenM-jzjA>LIs=qpNg#pB=P2eMq--C9WU%u2w}3mRyj=(_A<A(&R-acYs9Gyj
z>Ffv+ro6rsBH_yL1i&Md883rGDxab1unWpJ%>YCx7yk>FqLr;wEpky=LJwt(l1B%s
zOUizVb;T;(sJ<>vxsobj<CRa^0+*m%OEsm5N-2GUDoObSeH-Ai@;;SVTv0BhwI^8_
zMDgns<=Nv<ma1IH2bZS2{291(<r^14t|~{!mki}0DxS+!CeVo?OZk}rhO(7uZ-C?|
z!{T7*n)2yJICx!o@^4tkRYuYNI!{^dit*(ue~yRs8_F6jv=k`My#XzS$|aOgD^d=f
zLu0XW{Ui*PC~d-_tW>#ymgX{LDQ%m|m8m5VsZg#91Xro-<D;)i`57CAs+DiLpsz-`
zAPTrz<rWVZs#E6B<;{8}K0A&lPFYU-)<&g}UQ10%8@fc>tX$d+>n+OR7$|F1?)wEU
zbtr$zgcF_0i!VTRm-4y;`fe%%Dah5W{CX6)TgtyFV%DQfqcy8n8F3DPKIL>j`udgc
zbMf~ZP;MCkH>kAkf=ffngaD9XrIL#EMwIWr5BR9EvLC9)l>J-KH?EXMp>aYveHc1#
zD-9IFm{dyWj>D9)nSM5Rlu_v*)5`a(80}r<?j|@tqZCly@Sbv$9)0(f!*phTp!_%j
zWLEjME9}iFo#@*Y^Gd|A@WiRM(r21%Rof~0YNrYozzKWRUfS{>Rb3Xt2?tdqow*!U
zFSlc0PO9=4G&-x+9EQ$gsv&>$9ap7f!k&xDa0oh2s7mQb<EmQxDh!=eDXEOfO|?h_
z3+}47{|50;_0aR~srrXv9$u;=N+|PI{qGc1pHi*a4eqqcOp$dT)d1Bl`>IUzDT6br
zE3N?esa_j`&a<inI!*YiR{af;096JZi~?27IZz#>dg}!Mf>qzJK+dTy{Dr;{Rm^@^
zKd;KZ3k#ttGetwgR9z|18LpDjTP;HM3Pt%NRflM?x}f_0Fi4c@z83(|s%a-kUQ`(m
zLT8LBfo@n_Qq5DrQ>^NnU*UY5D(@0>#;ZQtgT@3^*8}KGRE6(`yGbgSAk5%pm1YP!
zuc)%x08duE)`7khm18HkRMk%-=u1<1(-#}kRnI>Rz*W^&y0Mv|ve0LDGF8u00brIY
zj%p9CsmvC@udDtlhS#~O+RYHjQ`L0AmweS-I^W(<C2RvJQ1v|xkwVq^*PydVwYLG1
z#VXlxI9Q_EKZ%JfRpn5ku}qcQ4M4fdo-$MwDly&ss#M*394=L<x;kODTGdV;e5g^?
zQ4pb46%+)Q>QqkN5UE#LE1<eT<+u^JMpeQf%r>c(-vOXm_3kOS+oC#5>qM*SDD7X`
zRR5!cSi6d!2FVUpZZVW~s+RtY3F%UKQ;O-P>J<jKZWVV626jvJGM%e>RR5#AeXlC{
zBal8-=UO!Ot3K?7*8{3E&G2PVRWt!Iq}pcy8CDfg!S;yC*%RET%Bvd6##C;#AmggO
zFJWjx<+li)-B!I<37wNFKLPrtR8CYhc}KPEE%-UDYHNbXUDe+NpHcBv!QMSp$Uo@2
zuewV2_#deL+JG_4s<f-Y&8aF?us5&rp}oG1+J=tRwrW?Zf3Z^!(B*e~^$t2#A61{G
zEvkds>0|Ucs`Ke1rB3RcCt=-L{l9x~{+Rj~PiQ%={*7uKT-0_o;7+I;DAVMsE{%r0
zlj<Mpq0CLanBErdYRyOR(?dN>MPi=n-dzy!Qg3!apSSu|svtV0-bwkm)9P1gckiRl
zqd<?ZI{5?uXVmxU_2Q>~{te*Hs`nlN=da$s6(m5t`Fk`5swZEB*FoycaB#uu#aqyK
zPW=r9dP3D-Q(`4dt)cyVxH|1JxCr&mICveYj-gch1$Egn_!6adp?yKL`qO&!T~sgr
zuVzoZnl^iv)Q8;RV658U29Y@R=ikG#c(p?r>?NpY$j?Oet-Bye>MDBKTvn&jh59RM
z;XX7btHrOtmlSpKC`hXMFG{SWsr?6_EL~kl6?|9KuTWwoLmj*v)-%<~+d#6^{;$Eo
zZ1ti>Oh}G8hoYg^)QleixUSBn#6zw+fr@(b)XVAneferHiUQnFuiS>d0=0cLxI%Rw
zy*G>07ApEFRzF6IRf*b(p2kx3a}^k0nfgR30Oe{1g-9#Z%me7FRA0D@zAAOla+s}F
z&#r)l8a0DLz_sc)dj9Iv@7)5fUi~<|DI3(M{!6c^H5BG;Qun_F(yac0P7E#TAG$zV
z)q%7{ZBwrfLSMW3Aqr%5sLxU2p;KL#hQ=;+|2>$!sUDaB=~lmV5r%H5chLt)deq-M
z0O?ih=y1@d-uE@Qes$j`7}$WinJRAw)zi_iFr<E!DxHSaU37FFQM*w!@2L7IDkK_H
zFQFvJxcYT^nNFyGq(k9t^_xogGO2!te(Y1~rAC;&qc)v`&S~}RFaUSe$zOt-QTx-C
z^?T|M1L5_3bp}Ni9;nCtAu_9GeT6a1sg-tca9;i1Q4kx=qiF!xYE~4$o}Fe1ts3?k
z3*Aq3)WlGb(n<3(owA%Y=iLD~rdd7%oyRo+4p8QzX`tZB2~GcM;9NCplF@fkvy3tv
zZkq4jhKRc+Ne_2DG{tmo^wf;eLE1|rr{~>Uvmg|br!>1>g}u|7A=*m&XfDyO)mP(k
z3h*<UI(lIJG@>`)%UMmrHrVsm*c^pOfTo>(A%PlEGAsmX-pmFdSmVDQjpsCX=@v|g
z=EyGqoY!op&`zkPl}bUvG!3+Lg==1<RU<-^cO8I8O&1H+FKGNO!<Q({lAX{Qt@-G0
zkc*oB-{EzPriRY;mo$G+@lLGfTdIGF(_}QlP`rlc1f2<*>}HTeO`HpSNz&lczj)#_
zHz-zlMYD(kk;xhkMG{jqb{im)su9!gGfnf|G<2rJPZ+wY30wp~h9=@Jlx1p~lYz_9
z{6smFY|Yp#xE#%*A7S>I<|kU@u4}e%p)6MuNyq9u%?ko3%h%-5*64;tcm!GsG~PMD
z6>6@nf=H3(IVycF)|lwgF46cNhn7-J2Hlh>(^OFsq+Iif8|+nR_R~4FQd9gbM5;8)
z=&e?*InV}WHJSnXvPG?CmL|DQGwltLdQH%4=xfjfPzIn;lTXL$CXH|(M4B}PFN15*
zOfP_gt(sNOVYF?U6uQFNuKAo!1s$3lZQwdJ8wF6^rIFCnaZ}Sm-{bDqOfLldmS(0L
zxIRtZuW0Po6rBYb&>X&p#zD=MVQ3lB?5C^e!x|3V`yA2yZp2VVHRU{rjA??uhxKty
z=r7<VG^(or+}12^g2<%i*IlqMrRko5^*frvVocq%=5{_r?rPF6U<@-FANnN5J<T^1
zqPefpQ}*hC=26-&&1&qTAu^{?C^5<Nns<Gn%tmXS1+mpSHNqu3ZITy8WUp=d3Z5O+
zPKlt}LF+RQfTMN;{ZkDm?ZF=);;c=p139J@eFl5SwO8of;iCPFj@2i$UT;8|tM<zg
z08VOobgXvM{z!|JyY@U~O+2)dci@?)c1Z~uy|noqQ0A@O`XqcgrM01*>S^sTmGSy$
z>uE#otBs?@>Wp?XCHMTa4EnL3)oPvLnZGu73(N*+AJEbjsC_vPV-M0E`xv-j?WeR|
zKBxU*Aw)v7KfM79=e1iYsT->8eF}|X+E{v=!nMg3sE*L~(83a_{a_n#7qp=@a3V@u
zO{H|v+7NngUevzt0o5_u_vj>iNxQoPT&(u;dbkv)-AZA?cx?_XB?;Q!8E`34YnTT~
z(uymf^Rl)q9)_-H-&_hq$=ZloNTz7VzXdK;YiNU(G;I}aQPZ`-6nMF+%@qNcp>?Fp
zYo=DV6@V<Q<|FiFYi((D%h85XS;{qS(kpQHx^~|dH0Ej#Qh89G)<`dgd~F<U3vXyc
zhv9CKcFRpP7HgN#b)pjOIK5X&wQ<V;DAN|w%22Ld*8r|U8$fj|m0DZcj#Oz`e!x|0
zoyq{H(LQw-PSk40>A9`bHip7Ny|yYF@CL2VBu3PzT}K<pCheAT^fhDb0JLa}0x$)w
zS|@rQ+O$P<t+`#BMDg+t?GZZPc4~jJVnkiql@Gz*P3@ypan`MMqD}rS?JMu2uSXm8
z8~S>+-Zbbw?PA(F_G?8Yus)z|tA(LKtverpAuWF?+#S|F>;Ww!+Jo<-Z&Vve2lp}U
zM>n8lT$`~FWJ2o{11-0;U(<eYQaev|T~pfLe_`Q{HiAlkrnQ}vN4Tqf)(mAc+Pysx
zxu<oct@M5E)<=MQpuJDOvstarhcG**eex#Ay!Oer&}gG8bOOLucPaw_JKZby;Gn(k
zX^K1_)ot(v+(9RzoQ9*$Z~*`(-AT$&IqNL`FndgQW;4if-Qo%~y68Acs6L@9Jp;~F
zw~k)rCv|;vsCUzG=x^k%Yoi2$hwk5_(CMjbv;pzbwNv!mTjx)=Ax`PG#l!k(-KJu|
zeRR&l;CywwG5B&uXY&A)<)_<6dz7;}`}3Frf1Pm_T!3!f7XSq6KBBcCNcZVBkYL>}
zY{1XySPNh%M3<cj>*sY_3gKX=&W(pj4%6ww(HE}U{|ovebb-%;MCwemhrXbDT#vqs
zx^5~qiP1er5wlCW=P5Q5t9zcpr*XQKZ1lzJTFW4rpxZ{3K#97NSy)ffeewuAyR7>#
z5V$M4v-AQ>)>-LeWGOm6rKwYO&Xe#ZP50`b5J}gae-$ITs$(34&J10q6<RWNJ5EC+
zOZWC(;Ief-v}4K9WpzOHHC;ND-CWmgcLSHJn;Ar3o-TF^xO|-_<=AiN9+0~Qx&pc{
zQ>a^VABKu_-%!N5Shv6q7D{xUi2#)91axn(O!sd)be8L;dcjrbj#C)4Quh<avam|`
z#!WO<>+)6brAC)#0;$#g*a`>hbQXG()a#z4+JgpN1|8BGbx+U0UX#v5p@C*y*hX+I
zI_KBW*Q(3;29j+$3*9Jg*GYc?*P+{@1=pz?ret@QZkYxS-qf|(0MM<o*$sQQbc_$+
zZjWv}4P)rlHPHc}Pd7xXaKA2zVyXkWt{X5ksJqt+$st{|7vRIXO%Froh)(_zxKZ6W
zCF#a=zpex~t~;HLK~Lz!?*edJ_W>m=CUq-!Lu5+#0j)%LbWss7G_6}l3+G*39$nI#
z(Fy4O*gf5^lnc49+d;w22fFQ4?K-Pd(w(h2oq%47^SU=EVPT_xY8b>;zn1o<cKV4w
zFlYAq^bm*~)&F!1oP+-8atzv0pGNDvlYZ^jAkKO<t&zv{Zx+GAalIYg_;b-Or^WxI
ze#<b%;HLldF8bW{>rX<9hyJfufb-NpPa7pKeGUc3y!F3&18_=jodP+nUw05%eDsgf
zxyo11JBaa}(Ql&Myq|tP34Lev&+LLSf4z1P4hHBq3!x=YKk*B=ApHjv91GTuQ8@FQ
z{s5h|L-gx6fjh4+Oam@df0EAHVS3FXkZ}ELeE1Tff4v`lk@_bn9DPBb_CF|#(!bOK
z60N_#4_;ry7@#Fa|K1!tyQJS>g}bqO4OOtm=|?Kj7q916!odW64+}aI^|#{zPtxal
zK=oz)B3i7j=mp=yY_fj!8t6>XkM%($Rd0PCUZ?5Pr=dDs??H`M_0}+0$k2aDA-zof
z%-1lKrC;$VMw_jVe;<uG`VS<)UDJp6fLzz_qB5;q{bAas<>{>yHpth1R}H`o{da#r
zXMuhtt-^)+Ehpe$k^Vg=0E+dy4udPv>zBdLQoT%$#xngLN}-kOU-<8d(=+LPTdDs&
z0q`n)E8Rb;)<;norbhpU6sl|W)f<7U(=VaLs$ReQ2Z%K2-=NS{qh56fqixdr(<Rwv
z{ikkF)}q(bMc-Ea-Drrk>HqozT)Y0;|6$M_dT$oAbn2gb7M^wK!|9ZKQ@^Dh@NWG_
z*s?6VrGGIS7JBrT)<bo#ek2gn+NTdCd;NNo1|kFcmtKO%p#I&RXdKeNKyU3~{Y#zj
zdQ5LfLE|`n1>h$1T$<L~`gAs|PwEFKxH6?bn*{hB{duZCo7Rh|WbCf~M+$?^=ugsi
z@}9n#cCq*MFHouO1O3wvKxXx?9DvR_eZwA*d424c5V0}LQAp3$P%Xt6><mV#8n-tr
zy9F&r4M8`6b1-OVGvsIpr&=5*!!5dO;B1(r#L6*4_bv1tH{7Rit&5?KA|NLWmIe@4
zgA-k7J!yD05nj6)UZJ0xyWt4M);tW(w8!)`+@wlvFT?dWq0HM*W)HwALoBT?rwu21
zVaUf2Pgz-CL)&xcJ7Z{}B!Qn{;!%j4HFUURUi=MLXhZ>qXcI`F;U`)ugABjZx*Kd5
z9s_sIu<Bj(g&4Nch|U{aX<HF$C=Lb*GeppfJ={=2NwWw;51r~F4UIIS3kE3_9Yh&q
zJK$inp@d#U7Y*AUf|eMABgI=U8AhH#U#y|^WehXUaFE{U@rKT~p(VjEH~^ApaG*OX
zNrnSrIC0tVsTpRk7&w;zPd2oq!BC1}?}u<A)sXWfoJccFX#q$#WH`azRl_t7sxu5B
z28d)D{-MZFmf`Vl(U)!5E(MokIP@nBT{8&t0l#ig9)N?nhJ<LS&NFz10iJK@q-*{+
z48ML3Qea5<7LA1l!y_O?h86EXb+LilguW8PXbiYg!+AScC^PU@K})&e@vlIt3|YtE
zb+tjMgS{HVUQdju)^IZnxH^M-BgS5D`21h=H5k@W1i8^r^*BhA;WIjqH5)RiG^)ig
zKo#DthBI6=wizNQnA&b=qmW*QVUEhFI}MIcLv@#7<9`<$4gbD_zHUP)EeW>_9=}7R
z#}JSVT(99<%9ZySHc$|~-(aRa(SX4%9Fsg~_`n%`Lxw}NryVvN9fvO?hRI;49yLt*
z05E1)L?1&KH=L=3$b_MJEBbC5R>`1c(y)tOU{i*r<oq4O{AMVdHpKi6)prfK7r@OJ
ze)GU+?-?Hb0;=yDdOm`(2Zm=}0$|qgIVFeY3=I@Em^Y;EhB6ytDut(PjbB{{u`_yp
z4`ueo>y(l_YHYU!=V1J1C!BCJwg>@mGXDB3`kajyo#Egy<M!*&dE7WL3PUbNX#x69
z7&m8wb2Sc|061w}nE~r=#w<EdyBnLFK|GApbfehQI9LsUmoYR4oVQWr2G33zE8m7M
zr;T4y(#*&BEG^r<#>1bW?~HN41#my(DLHUwjjGSl=WleR??D6@k5a{apmFm)NCp`{
zGNLcocySioIU}FO7h(*h=<<2v-e+Mi)VQPzB4NhBzc7?=<5#o=k1)PTd$&mAB6^%I
z7?l!`DB}l7XpA<#ODBzsM&FeH#2B?SluO1%bXblx?x3J{oH42xhT@I&6j4et{#Fe5
zW#jHtz^@o}{UFK4Q8nNxM*Ba|muhsOM=j0Ra~~6#ZhR#SeOHb5-v!AqemxJ8Y5Z#^
zyv{PdoduoQ#)vQga*U1?wY_F+i^ou|8+kgAT;m&b#LqLf>)}Mcv6c>#H;k{+@4CSF
zg&tg?G1U`&MaE~Z!QEoxE;`GU7|+u2xYXFV8+~QQv(E6W+*th_xC-M#%ivk1@nJfB
zRvAxHby2nP5h|yyF|MMZOs%o}C0MUBR@0BY-njoS{1h9E=ZDbOXk1Tk!zSaZ{otC7
zztVHmV*HLi;n!-MdIhT6jJ5y6Fx!o9ghFSB@dJuabQ;%r!QC$7QmTZ#X^dC`m%5FH
zCXidkfUkh-F{ai-q}TY%5vcAn9->@GzcK$200xYQDWWuJJWS<JL&o=4!NFl;{io;~
zF@8i9OQXgw=`kELUZy8}-1q_;eoh#FrEewOHY!}9deZpCQsAbH3kYz>$jC?Ew2_qn
zLwAjj=Rx(1k#i8_o-sNK<i62`B3}=T{V&7%tg+V*xH+T8YK(T?_)j~m+n6%xTBWTi
zb`Z+!Ob2MUZEteY0e95&KZ=byn6A)0Q%6&<9;0<KH8+4bn<5^9g=3~8T=X3`ojHlg
zaxuOADsU%E+ZVx}tLcjmq3on7iVhrZCT%4e-AzX#AmU+4q|>LTDY6^H%jEVmTsm#y
zQk8;_X#*{|z9uiKzByxhs25)QnHCA5?5v5G3b?;%HElx!Ou}_A8)$moiZKM4{&fWj
zHr>7td*@6)DWNRH^b(cXoj2{Hg(cJ!L1*nSQ~4?=3pcH$eO-iU6$RrWO^?%u056zs
z)1ffRw1NUs(WbB;KrWh|qRdE)N%{x0TrveGV+vwT`)LyuXL@=ow8Wbp^M#fK(-Vbo
zDbb|*61XIj)dc4+o5T*#dBybI4giu(4>Hi0Vj35MOEo>a464&iE_}e#O(!VJebv-Y
zQN|3@V-&K?G;N{AER(YxaM`9Zx;30*5>ip`HPfy)(0ASRtp%RtnnoxlmuK2C1=abc
zmngq-!xT%^Oa-PFFT+rwX)%R%icD+v!|P&`aw~8prV~_lT55Wimisc(u5k2~oBsL>
z7Aj10l;Nl}*}ntHDpT9<5UDoVehdd|Opz3kuQe5D(N||O()Op`q@mY*gDGn}tT&pL
zq`_>HsappN&8F>sP~Bomr~BHiCR<wa+Dr#1=Gbl;NQa>g(`S?&?=&_20n%mqa1=Uk
znk1`$>o)yJkNquE66LviOn*{>xz{A4>_DHX^dFFZlaNkX1ExWDcs6Ldy#uO;OxJ#f
zFT<ukD$qA#`ur=vM@{D?7|NLGts4*-Hwoz%Ibr(D8Cq_ej8m{aX)3kBP^L_qY3Fg*
zR6xP-8Pm=_kb9=JdNkfQ1!lps2c}V)vssgiH(Z)CrBQ@#-t=8Ph>iIn3L)B>uO<R#
zXa4OlblRIA&=PypJf9AG4(1hc@XXPy8^<5V$!xm-#Mzwn-!o>uN?X+9=6*`VxtPr_
zK+6g9!v6v8YTj@Wk|)ip_d>+Y97rF1b2o3h11CJppGCuvr#ZC{!}K!$OpCa;`2f8>
zPnlm?0q(T<?G!lZV?JC4oxbKDO3`=5>_<BRKXd&qz|Wd5?S+WH`O`S`1(?UEj49CU
zM#Vcp<~39Z7Hod*b9i>nT;Bm)h&e$F?!38zelMZsIzMn>=0y6=Lby4u0VKlQ_9ftv
zW+OeR7tEFP=Z`XbH-d{cAEM>yqB*1-jWOo%YZ&Gwb0uxoW6h!T-i$LR)4~~Vewk94
z3Ff!1LuaB{x&rVdb7~jdy=>0uM&lK;#sw}Vn;%;Oc#656Uf!wZ#8;s@&HStl`qIr2
z-vD>jynhyb8RjJ~fn=IzSTLJq=F-jXZ1cwju$N<2(P`<L`8C?NUN_HCjc2ZT$)^}f
zp1Flefbz}l6xO<7=9EHbf!RO@qeAn514xk>AIZWKXAW|K*Cl3`Y^W|Zhg^luGV>1l
z8<m^+6mqUGJ6(gaN^|d@P*!Drf<Ap;ZPspwXEkOY+I7{M7k5LX&ir6E`s&RWJmFH4
z*+Q@DX0z{KkZdu3KnL4a^S(!*rOiAOg3-2{chME(4)fbIlumQwPq5czUQCPJP4miV
zIMHp6dkiAC%;Qua(qsOFp15A~f?LqiXFg0B>3*}A*6RUtC1q>}&3p4O6GLYE#poM0
z|NR*}8!;!))Qy^h4#Di0x$hW6#?5OUgG&=;yLni+ZO))W{iONr5cEx%-=|v!cg(R<
zaB12+No)CCbH-<wtQm92>(F`6oKKfQ@0<Iniu8fmk_mgW=4<c4mpSvh^!}SSKNk-R
zHkKX=@Y!0VZ1mY#UZEORd&?;0+>Tn@Ezsg%aiI66qvg*T5GTttg|(b5ALava%o3FV
zk>i#P6hm^ch^_GKgk^RII9JO%^lLq7snbHl&9X%Xd+wH?8CdYJETc`0r)6&j#^7c7
z;b{<Wi-qbcPgxc?qVKe2(^3F@EG4hOL0`*?9w<9wNxcaXKg(P;44t(s2?pnH=~KX7
zfW@#5T%ct;Rci%Ve!K~hU`x$B8qZn6@j=yvA(rY%SU+$1;v#g0S{zehHq5f^9SkMh
z(m=&K5f<42Oi!d`<X7M>Sl)RSeNmQIm%^oJ%W}#NT(n%K6*|V^N)^JFEOqaJi?wX(
zf=HZY5giBOEi79YO0YaZ-@8b(tfT8hNtW$L0Jv;%d=-sXEO}etM6yL32PaZ239rFW
zs)a>$5LYc8hhZqgvXi0}nU=4&!lf+B-ZJ2_ElKszl4DWUfLyb5?1kCumUGA8Zmy+`
zUYL27z9UeUZ@EW5w;PsIwC5|Z6m177v^<mv3q_V{st+l)$ortP#NtRLN2Qi53VoDW
zexj&fxh1X_PE=TePr*W^CG#rWt+M1(#cs6)`!YOZmN&V;)moaU^rX)6C#|OSmPUHb
zH(2J}fNQj{_QJC!%PmU8HCq^z@NKay?}nCE%jrb)wORBQz}qdqoQFt<<!j1McUnUJ
z``U(uxedPDw0uOjl)Ehl7J=Ndd_u>F9!o+VoanXi>Hz4oq*Kvkzh&ZII5A)eUxR@S
zT2@kR;gDq;1viH+tbZ{DBbEg*Fgt45(hcXwEZZpHHg2gOgrNzG<}6g-w){ma%A{pU
z2)HSWeHFMnmdb~Ko3=E54`p{P#TxX@SoZmYyJz|AD*EnQKD>;^2bQO#P&RA%=MnVH
zSxPA4Id9p-fjt}R>lE>{wZ7d3&d$2)QE>LwotwcOwVKs%(82od6%a?O&42qy>yq~&
z;%xnQ4vojG_T{i}+{$NSm@d}m4gq(<`X)sdT&+J&f}FH2-v@x3)%pU6yLI`m5b?0S
zd<cD>*2f0Gd0F=vp~c%eMmx?^*0@M0J8k_@1`9sczbSO=Yjs!v$urjF^ds`Kw%CF@
zYki!`rUI>d^DyN>*1dFRE7<zwGw3^KeS{90A=V@TChNTQ_~XEZT7Uf-vm0i8!hptb
zYr79bBCLzEVIk65_zC(hSU0)jj~ZnyD*_j7U8{tj7p-b09E`E{&=&5J)sqgWu~yCk
zgn8qvztI^l-WpHeLrSoY(1M$2t)w_Zl63*4QZ8G=dH}d$wWs5Fvh}xGs7|peo8Wb-
zRr?G8X;y;;s?)70cVO?TbrBs~GORNr@H*34MajJ^>vt4A&$hlvnTj0ihjgsIX0<;K
zv)8Q+vw-JXlW3crXFU)Dk$mgKk5G2Qs-z88f%WEp(Gly5^b;<!8a6<6vGseZ<1Df6
zXau0tx{MqwvvOAeS8hF34V@L%zsmurw2n~Drpmg$34PVp{8R9y#+q{l<Eyn=DZ5i=
z-Mk2W^;U=5APv?H8!^5{D_;(sP1Yz1ZZ=yt-UQcT4K%=|R;wNDz1yr+;n31<-9g9d
z4r_V|lyzEdzXPDl+Co36o7OWFX6m*M?}XV~)-6<v(_@W{1+Le+iH@>;R$nTK>$kd4
zwsXLmz6pRqYXHslkago@P(A#A99?%@m(};z%B<A<+Oo28e)isbqLyaEtQ>6{mSt&<
zGPPK;1Q8HKhR7bGh{#5n%9JTnL8gi_WGegjK0p3BuXFEtpL6d0JmcPT&V5)lQ3sK}
zRqH>&!1`DHUW+Msv}!e#^$n~Vv;!Gj)i4`?p;cEZ;Qa8aGz%<@tU9d*8C_+dn&8K)
z@E<I3$F2H{uCuXKpZ1|~eAWD);nKvat8YQe<f^aQK&Do?Qijo%@fSrT>=-p0;h8;S
zsTZs}Fr29%$dU2#3?z>-VrakV#8^-D^Ue(aNdR0J!;TPfWgMb-j~k<903yd2{&WV_
zoe@sERu9Hns{1|8xbhnec{0w?TIvKNVjFN?j2Ge{>CISA>m?sX2SpN3GQOgUGhfDP
z3NZLFzTOBerx-d5aQ=+ix6pT*@#7H;EPyd<H2{H(wG;>mVyw)8mSD!^5cHj4<Wq7l
zgz>TgV?WFImbTTQj2x=82xIW+?g(da$-xMQc^y<oGV-jDjAA(YLuWMOvo+vi7(=<R
z7t3I0V|;OpZU4fhbBtwI(HGCC8G@nnj1%;*y1-CUZZLr%r1`waIJ6VEM8=ElP<@Hf
zL8-nZ1}hxoGUI<DIFZbVp>2E$BR&(7sf=EFZ>BNK8=*R#@qs(EWH8F20mx*`r$AN~
zBl#e#Utv6BMB`P4&rZx>HX|wnT5=dK<)SZ_Q9~C|9%G^pI`bJ1a=;ZZChMW>8e?ZL
zaMu~%)1#!2agesvMT~3Z&{E9!?-IBYhTDfwR?4WNZ#I@Oc8D>)8;ph>Xe?*g7XVkm
zVDbT|WOSv&LKWl19*9&k2E`DmVRX`t?<S*=0cEue11;L>7<~sZ$@PrpCiv38c<&7W
z8X1dk0no(wy$H%~G2FFiyv^vP*KRZ8nc2|N!nmA{zB`PlPH1Uo)X=WAgQ2H2N+;vm
z1mIna4V3%5%jl!4^&X>~>O<}`{yGXjyBW`Y3G#sPDb;^IWHeU-(8E|sHFUj<Gq=#!
z$C#m?qo47H4MZL>KBf@O0Hc}Kn1c-C5aw)%F@F_&8D>nFKt>qHV_|QU5px0LF{AAy
zyne!nrkK?jqmVX?<BVqqpk;z_E(Ri#jP=O9&6#2>(80lJM#wi%J;QjV5R$e`b`gjj
z)94S?_RLL905~vBo4`3TpL+{{qs*@~05~xl#L(%?+_VCm3-dJXLR^`f>0#x@{NYtN
ze~j532@!W@(wpe>U@oRb#&Kre9f)``M@=9nm`h(kpBGa;4*+jw=qXHr5A#(|=sd~X
zat*|n`HKoTKjslvh@4`6O3zk*=8t;;Kh6Ay9&!Q9-zYl}$V{dEUl4OEtxbcO__qtV
z<Cvdpht3dYw+|Z6GGEferBG%o1-ZhQ9rW%GXWpP`jbKK5Lo$*%^D!Eum>w4}OVP}+
z6iCJ}*S!E-Ec35Bun@;&&PC%nW;|ub<C#;mggejFMWOEk^G^z0B`{BY1@0pA;w^Zc
z$oz)_<(HTOiWw&{vnbJcnfbN@bS5)h3Luig450;GD)Y_5=u2ZhJPa-A%&AELGMI&Q
z-YJtgZh(VXOjAF&E6lbO^j&3kQNTN!=|+jF9Om*x(2~n6HbP4QbNn<0eT}*HKUlcV
z{9hGFA=4%a&KEJA*pMt{+Eqhm3G>JXXeni0q!e};(@h4?ZZPMchM{ui0A>Fxn19Ow
zuVlLRU|y=2sq~$NYGxl@QZ>vM7DMtTvzPM4wajSx4qYAdfGaH2Gf&fTz6R#hbHFt+
zEw|9u#N09oWw)3nih0~-idJBHnwjBp^tCXD=(f1S%=!;~t;`*C?Y1%hy^F?nrl1$Y
z>|nBJ6Vu6z*aFhUbYTL1m-*8nkbBHqw1B+NJV>dcZsxjXkOxc^ZL1$LU#C=253~Av
zH1;w-`WX)PF%$K0zMok{iIqppmuXQtz&uP3t3hT49ZMKu=F&TLnAsHv_y{wz6Mdu1
z$Fu``%p9fV&l6@4t%b*!v*;N)&a}`9cY@g!2*4yW)(UQlxp*Dion{`QGk!D7cc~uJ
zmes6+YCG1_K5+IdC%W+*STFp6VLGyo(JSOAD}d^=oLJ8<2XSVJ4&xVdVSPUzI9Jxe
z4`J4g6`BIcW3164aPF-CQA*i^WxpB9j<dGWBG{8vPrJbrtVG%>c(Du=A@FAXPEj!*
z*7^s~d6LygF9u)MU@U$rKh|5#Ag5T5=_>GN?YxDb<238jO6Uw={qq$7fh-$Z<Oi|7
zoDIofRvGOk&aevHKtfpW55dq`){$*+DU_wmhxIU43MIe7S<ghEFN)=O5L%*Hzw==s
zhSiV<)v>IRPAH3Gy-bJ7&asv_LnNMcgOcm#S%)dpbb&P(1waC;$PR#utWV=$A(1t>
z6Oxx$OKxIdNvwnIAeULM(_%K6Wuli`3d=nJT2fgK6qrb387SPB&bm)uS;=5M?SQ^a
z)@7=p%VO>H0=dFkAcZeiSqEudm(9|?2rh@UjxLm3*1vy)<grqoffM;GZXlEuu<A?T
z#5L9{Doo^c)_FR{Qpk#KKwlBdpEga!tR-A1D`DBu(cV(l*Ys<av3Au1aDyeQ09VdB
zL(9Sn*2a?nRI>h|iL7Ed&<|eCdXv5wQp5Tt9^6e<ZYm^eS@S31Ssg3w1@zUkoYLWZ
z1MAZm46~7Sei;lkvE25d?-r}+OZ44l?WLQfnRSrP6|}I*X}@xZ#hSrTT3Plp0JO2j
zC`Q)K%EVcfIUTHj&qAb=b=?;Bx>zx^E4a%VG5~&$Rn3K;_gP22#W1^Bp_DRsz)Gg&
z-9uL2n^4xn+D3bsUe<f`w(n!j*#=+wS<Thxd&F}27#0RtFCGRNWPPLr8Dgc-a&nlp
z^a02SD|<f3C@YihmB*~TzhXk3uzva-%Enl`yP;*Abu0p&O|Wuq06xijB!Ej(tecl$
zXqvUj3NpjmL8%m5_Vg#<?AX0j|7p)&Mh{~L_OFXU9NEw5K#sCA($VL_UhxEmT-m*p
z$#!G^EI{Ki_BN_vb!WT0j$wMRCyn5avlX2fpC?;S*Yyc@78e%0*fu2)@n(lag7aZZ
z>d<$REnNa9eA!2-NYjtK!x8SDV&C3_K7aPG8vv)-du`Adz}|NiIs@5r_kaYk3q~>a
zV76N<l$~K$zJiM=g#A4ouRF^gqm4r-yX-k|VeId|0U(^sFvCIwTSEEiNcNJKVK#~_
z(1VL+AL|E+VQ1Zh&RF&g7iQzw%4y)vvEOq57td}_fJ^7upQl0R1$KM|xCFMP3*1F^
zBApdVWc$%m_!8S1j5$kUM^lFXGJ7XwvXj{{6hcg4e@rzQscc3b;A!j&b6_u>UCjrV
z!QM@W0yEkF(xNSk9YQbtE9`9)NxaJbi6URw>{fcQ=dgR`1CYz!OCR&iV~YyG<+BIr
zDlcHqp{T<(_Dw1xzRuou7k!278j711u^&<qRWZB$3{;n}BWFRRl>Ols7-kv!i%-#a
zgS}h>KsmcB2YnUnZ{~ulWV=$7s*24?!z@*^&zfPOhOMUP`AzozA;4?dYv?st$F_SH
zhU(dW-oY3e*y&V`+sM8}rEN{@d3-e9V%J}R<ZbpWdZ#wCN4^Bt!giofRNP_T`~{?y
z9i#xRjh#wMfOdBEFPMT3w!RpRootssz;&_zjDYpK><zR8xX13Li|7G6X+K0BvVVw$
zNDq5fEX?+@=RF43$MzY7NI!eoJ>VX(FB_qHfPI11S%YjHZ6Al&aynQw%wBLBxDoa{
z?|~a->*&SznEln;n4Tx>eG4%!V{EM!gC1vJpjFTWn^%R#N%jsusGef4mZEW*o$HCA
z%&_026XCWTHSPQDIA+R0+jAV~zIEW#(kjT2^E*AEk8<|70N}*gK&v2UPK6KpTsZ%2
zhE7+`3s*qgIOz)X9pn7u1?Sy4O^e~Y2j}oK`i^sC^#5f%IWJN!`2^>E+LL&3y#52g
zn{)7MIN`(T+X_P`IY%ga?8}i{2HcNRxB&1|oY@)>e@^zxn2FOIyHYq9z$vA}4S}5R
z=u1>VoL*WM26NJz!JXmk{}@~dXZMTHa+Z^E2&zLl;tPO>ab{CVPB>>-2DC(Q>S)^;
z$yq>)nkWt<0oJ2A+dII;aJ(sc5X*TI2riEEJ>3@PIIi^Ejpyv5GK2G+V-(Z5!0GdX
z*#wSXJ;+7Q`a|eT<Ro-M^(9UU)q5v#66iY%mpPr}bu#Awl^LXPw$N)Zm2>xVs7~WZ
z`a#k;eTxCe;OwBBVkTz`8-Og%Z+)1$E1a|RPsy%wo~MmpHYa=|wB&GdXkC!YX`yoX
zJPy|zF6DC=N~kX2tRF+;HO^lrF@x7RiL?hQ<h(;szaq}=LBNYS$;ZK!ai$-DyTOU4
z`=Ok3^jny%;8dGHDml4lVWEoim=BR^PA(nusNq~a1)VoJB@|+-<=kxqspAyA43T=y
z`F!}<z*(Yzy++Qz&jZlJ3BHKNTbw`W+l#mHKbX+h%z0-c2G+v4w+oGTIGJ?zv6U0`
z0DWzo=5H{RcFt1{(AmM^`@%ve$F~)}baCGJ2RiR^0;qc99_Pg^P<@~C$v?n#b2PMk
zeZVPu0{BDDD4o;q;ppNpuwITE?LPZB>nowGpVRpb;Ey;F6j>PHyhFi&K@RgJXc^-4
ztN=I6*+<`&9N`?MD{GYV{yN|ub1v?I6Hho&DnlFNtfc7qI7dk$6P){D5Siq>aTQvo
zIKQc&dYZF(3npuZ!`KaFwp>9SI6Ll&*8sQY?x#(m19v?|Z5_Fh#TeL8?gM+^oVX^c
zig4yij=*adZcq_ayK?`eSAiS1nQ|e=xOe^o=gv)b1l)t`-3?{Ox%SV1cyc#11Ac;g
z!ykscxJ^B<?#;E*X3~e-MngHty&n!qU+!oqwD@tiRm1uzu8vlY{@lSmAg8%?bgu+(
z6KE|J$n~iMJc#=Xg@=Q=a!L!F;jW`X%n<H^73e$5-7^F(l>6?>un@*=q(@~qm%SW@
zBDlx*f<$s>Q*14YJBx=oi{@UVrF0B;4W;&Dx%=r|9LM#H1^gU0l1`;0aa}$H;4=3W
zFAOu8Th|Ih>D)oeF=TMRr>i`Z8}TnhvbjG{2qTB<O_f!-+}9mpp_Ka^RY2e1{_rP6
z%DG=slAwb7h_35O?*Hh=sp4wep}Ly8f?~}z+}X5QzR5jD`;J;}D22-ExyL_)WCM3o
zI3}`@yP95uP29MX5V^&DK#|hh+^PGJY~e17grPfJ<u#0`l{+gQ6Vk?gL>ruT?g@(T
zc5;Vu;Y1hr1Nu0~UG59CAG^mbqzv(WZiN@%-P|{`q51*0=mY>gTq!+_d%64SA=1a4
zPp3=zxoRF7A8|7%JvzX(q1fmkH=I_@L)=`th=#dave7rfU2+NBDED1@_&?@mtb^Gn
z+;x<28sn~~CGj}-uhrltxj#{X{}eZzvZT{o$rL1Kxcnh#vE?liLyH~n6^b)B@NV9K
z*N!|d+O;0#b<ncViPuL9C1>9Fedu)MJ>H68y73xmVSSAEqYF59o}dlHgLjyAS;u*%
zTj=xTbx^>@i?@C@8ohb06)@z(%iRgpCwcSRVcnOv>OP1cFYp_<becDB84LyRJZNtb
z$h%9|U=Z)ygXjz9c~Mp18D11E0YZ7h*%(+DkEMr5IIrw;G)D1Q@4$&@-g|QN#qfUi
z206#ubrbgDdB6Mx>*skn6koc?)Ad0zk#~&tPM3J+smdgoSGWNrg*WyXBB{JJ3~(8|
z{+n<<lXsK8){w<J><(qwyr=@;a(LeB;e0Od(`Uiu@g}2TFQ0dV)-MITar*j2A<vI0
z_=<S{6@n|~^(CUOgcp(o)up^@`meTSJdb7YrGoc2oo1=zxlwqripQmtRyA*e_A52K
z7<<giO`h-*aP_=0+O9V6o_iW1jXX9j#cuQZ-iESfUid>?FD<-KD!*vsEnEeA?YuP<
z4Cvr(r&N0<?@A>sbn)iX0fxIg{Qm)5d_412H1_iz-hjv>o-;)j26#h-FgwU&twi4t
z&yzyO!@N?e1RCM7XoEA#oBj-19`jby2c@6z>gj<y#@qW5M8<i)(wb<3cj#>>o8(1M
z9D0hE`4TKl^IrNAWQO;X0~&4lMTar1cKmNA&}h&9kyaND{6BU>nInHYolZZ>|GXVT
zapKp$hel_9G6gqX_}do1kSqU#pU~&V&rQPEkMRp>2kp+k^Z?d9`0ocn^>O|(vf#;o
zo3<w2{3yy=`tURMK;$IfqY6Xu<$oUp;>Wk?M&BuZTqgSb`M-V#d#Cx=CSWLl-=+r_
z%->3Tr!)Lb?}LQ!b+leO%a0nzOoZ|qS3ye{KPU%Ig!4<%pe%x4y9gqY{5k8PGm2kF
z-}Z^-uip-M48Ly$RLAnY>28eU%cG&?9A8A059j$QZvk+D|57AK0{;rd2QTsuw?K6w
zUzi4wOZ+T~jVAN^sH`Z3znKq_RQ?Z9(2~Y~OtH#zery*28T>{{dt~w%^u3EL{;Rac
zyu!bjfeE?F52I@$oBuTzT5|Y04kjy?A7z4tJpRqUFs=Fg{uq#Jd|5A47x5cuJ6_DM
zqt{spzd8y!OZh|50F?39l!3d!|2Y+aa{dQxP+h^#pbwN*@=vS<sp7xh0#eO?yA|*n
zz60%&Z}LB&G<7XM^fX8vzxrFuStGwU2fj4%4^qj>Eq(-r9&hu5XG3Q*Upo$WTlp_d
z!(JQzS@NZw&!qKB2mcd#4R-RsdIln0{9?+g-{r?q3CTVF#J`x&`}}y?Ep_u<Df;?=
zziR}I5BaaX01G|*;s=<lUVZ~TRQvedMl=raw~64(Fkk=wYj%E*3vi=+pBw0V%>Vc{
z08jXp|6+Q^_`XzFH_qR`3w;y(GJ5<@@((AXaf;ux9fqd)6U}Ix;n&j|%wABs2gE^8
z5dnLSf`wE8c2uy#79vgpXG*|23!EtK?IJLog-%z2e-Os!CYVJhv5pBIN}<zTkh~R~
zhv2zlz)uL~{sOp{;Fk-)c?(uk-Gz@}E>#Sk6!axRr>~%jLLdHu-OFM2w7`L0!U2Nk
zeu0)i!IK4m2MPXhMPsnQ`9D}VE2yW)La5-qf8j)!-~xqt!v%W_VJ|{ZdJ9~nATb0w
zqXg?#f{Pa9C;*5Nw0;OctRO!O%HjmUAsFpB!H$=KOA<W$2}CXnDky@SEa1{bn<8MG
zL|>|4w<naP3HDyZ)TImbRlsEktaT8{6ue50*et=!k04hB-~9k`Rgl#NKeGkB;ox!v
z3!XqSSKv)oL7t%24a)KbRrDY$5U_n<;hNwNUo>79M9|~DP*6Zo%_70N&ta%o@L?7_
zD-ndzBfV6xXghS439jsi<PAaJ6X41P`rk3I3PIby&{-)+pjASZz(|kLYQc|dV4+5!
z8v*X7KzRmZuNCa!!IwILk^<NDf-WIcHwe;f;Af-2sQ}iS1pDbmza`i~JDb~r&UYZv
zEO`4Ma4mvK`u`Sp1o)?Yxby{EDTdT0_}K%7+67uV)6^kYzX@EYAeMG~U4ny@4!SG&
zh^kEP3C_$y-+e(06>)S6)>NSJf#5cUS{@2`u^>Hyk^KPl3W_Oi+9wzjfa@2$LJ`(S
z0`+-_3<#pO!R(;mCpuU)B&ej&@vz`0s+k=Tls^r3M+FQDQ#=+V{|vwrK}8YBm|#~I
zB*z5{sK$Cq@Nh09rv)!8!!TzAvuHzQFFZ?+CkJ8EB#5K%;!|imDvTS1h?DRjJ@TA|
z9ga}uB5YlPF}Mm7Ud1rogztU>z%k(~Z$ZRe_|%sGcnAl!!q9QyV%lYS3jd_V><M8t
ztwz0s<+}m!7OuY!Cwzq4=n-^MxO^u@drFu>d31l_XTh+3TKGH@fB>O$79<0O2jgKO
zNZ6VKc(AZ+5gN}3mr!X&i0}{EDx4K=r?6J2@O2v~3lsi%1byMcxHr%jA!Jc*B2uW7
zqc2JrMN8XgVS@lV<Ai6aZuFdR4?T?Ih4Ny!bY3XlfH7PUu9<{Lf-p>pF<caOy$Q)g
z;d!csyCj^Z{YsMX8f_dd3%7Ivo-ACu16+!5D;;r36)swYDM%B#O~A8s;V><mGKAGM
zt(n5T6m`!MdQ$!16`|J>xO7#h-VS%Og+I{iGe@|ZR$aNms$!5lVSO|_%NIu10#_j9
z`~rK|gfsMFzb<^8;@*YAY>K!P2}k!qOR;c4Fq|(DF53!tsZe(Y*2{$Z=&K7ige|m3
zFBi_GdhZJ1L0WrP3Xf9taFwu#aMi+lbWpoS_|p*V-4u?!1wgH^t^y);!jVNVTQ8hi
z3DO{p;X$%d=uR8rCgCp!VDFYNiOPy@3-8W_vS#4`MMGPJmnrCUN4UKg%36gfw1jID
z_R?y*UD$XCQ_vy&isF%-LN4t$yM#k@M*6;RJ(cQq3;#%lg$Ke*^fY}aOj{1FN0@pD
zT(5An4DdeTPFl0~3nM=Q?vc<>0%ZfjL|Q!!3g?}IyF<b#Iy5&dbf@Rii16uIus$lB
z@P~tsh5xw&_e8j`6^&!U|CPh}aiQ-4;3kB^d*CL84KKp%lu*?Ik!fM;r%*j3{F@GT
z*ou0+pwmwDt{cqSi=NFyql4)BN3iE8l2iS}QBgY;N;!$FxzOn>$~g$LE~4-k(dR0%
zp<subXf6f&kBNT&0>oW3+kg>yi2l+-=W)?<YXSEZ75)HUPKXX4ffg^(ax2Vwi*o1S
zckmHa=b`bWC}uBkzM{70(dZ}Az6RVW(VS0V!C%BB&rXZ9gWv*0{ZxJtC>l>gV~}Vn
z1*(HZKT<u>8BstPNQfw7JFK4-70|hfP|==0K*B^n{tS4yXwgdmM2RYBc^55OW(z=!
zC_WQT#EO323@%P2Tm_MHqQoY+6fc_d2_(;p!oC1^LG&3_YA1-+orB~>k(Rzqm?-k2
zhxjE?ay1&0L^_K0UKY(`p)pz1w-)o6BHBqsDygE)Jd8a})Vu=@ri*MSACMsmplQt%
zy)1$gS)!m!*t;UySqI!zk;W5dvqkn*7<7*4%4(2Yk!Khr^F%7jhv$nf(juxrltO0_
zuZiwmN8@$TS_&Q&ihhiNmLkzZdVLm))D%N15&2Nsqg0e;gh-j_g`Z&WhRB3#Yfian
z5vAcPM6DE<s1(hYL8MBwxEfrwXva2~tr5+q?CMQX7#oeXq90xYsT0kiL_oc0ZV~_u
zqOxfC(kS8{1fWTjI0<q~G)<SyZPD9QfZHtkb3JCFMRdOe<c_E+2{X|u3JU^h6V0ZN
z1$2rcY1P#wa`A(OyQ1Br@bjK%LqE9tqFq`@c8h+XwCV%Vr@J8eP&9ZSq(?M1jtS`%
zHEe}TeWL%--nU=$B2`*E64}tEVn7u41bz;RaxcKpkSO{N0K=krw80q>F{!q2RP-S|
z86Jx|sKoGzXcLv)jENGz0T~ya_y}4iM8f0XCPikd#-0)_pz`}^(L#!b&WNIENo6Ze
z=D=M$@ed=gZZEdJ3VROXq%VPU6ek)%j*2TBA?YNZ^$=#A#eaVeEiU4Hm*I=6IN}`o
z+{7+aNPA3tC<)5k#WNHZ@em)q4ft{K4O(4zif<QUv?s(XkHNZ^_@&Em$y;1PZ*(6q
zzY-!R#c^*!nXh>GJs9#6zxq3rof6-D9gY5C4|*1y79UsxT!46#expFK$JbC6Bwqag
zpMDVMv_a&I_}AB<GekTphL$jKG6hh=#Yr(B5#lPk2BXD=v;>b4Pg6N=toTPM+>IBP
zuR-5=ar2wNT@YVC20*H~=_m}Pi3{nUbEJ!XD8QE?-qr*|nc^ZUu*wpPsFweVcn<^Q
zs(AcMz_Y~*DbJiE{*+26bH$sUgP}Ze@Ym3iFK(bh#R72@Jr1vl_iTls>*A+q(^M!{
zQ{KKvy!JXoip3N2AW|a!Q3frg;%6xsUM8L<zzy*i-@{(H_+L3hD#VUY16L`&^A2!T
zVtWejSBr}t!}%KVf4AVvP4TMZ;A+LXdC*cPp3VSQFOK^Tq(S^m766Un59m~FlX#sy
zblwtgqQ2YWLv)Wdi`(cdO^et>rF(b8r{9AUt>UwvVMJ|W3vDLb#ZO#->kvCo7Nb*q
zmcGu?B@Q|Z=kJPd&@s+?;$@f7cVGN@IJ9(&XP<zU2V&nrIR8-0q~EAVyh)A8>J|5d
z!|Oh=ODN#|;%CO-;3IK<1GoY4ch8}3P<)k6Ukr)o(@J$%{CfgakBIx}Cmt0~E`YMf
z;@#(A=!sbQ4!AL~Cza=oiyPeG%Y^vKK9FfKhn~<g;%&#F+E$WB>qtAvnjXxqy`<+H
zlsQQJ8qnw{nN2yxqmmTb|2au^?uJfh$)6h`=_1*135HxHpV9lzP2!OWWyd5j<FMy0
z$xKC`hs2w*SH~sGXuIPn*+Ywk6Ot{v0r!%4Qt;hdvdt3~d?bDELh_`fm{PpHl5c4T
z?I$Vu6Hc6x<Q;)zfaIf}(HJP%Nacq?lC94|OR&Uv0expA%mO$VB3Wn$k+YIK21G(7
z>nZXaCOJx4!X>X!kU2uKG7)}8N+LQyq9or&K})n`WD7`)B<(x^v66iqP!=ayM)8Sr
z64hEvNW6qW*@5$tx2c}*f@CNYeF>6D3fo<joP863M9Ci+;4Vp8UBM+u;)>wQWr^QA
z7<97alR9uI67T)MrAlny07;YJosWA=@)<>AG9;s4fMiM-gCJRw!?bI?B6({OtY4K}
ze;y8IOR{Rwm?ODcf}!L}_A;S5Pm*2?k}pZ165j&JmlUnPCdtl+mg^E16U-J$!d`{*
zMUsuh;EE+%DI!=R(GP<wmB=W5Rwnt5e)k&^H%bnbOZI8ORY*QM30$S*1P9iuBvu*5
zS1sA{5}c@!{J0D7o01QduvaV5Q;xk(a)%-r^^(9((bypQlzyB>$ss>zX_73b#O5u@
zrANTsmQ>PPrdhJ19)?;Zw<u81CeeCAq+Jq{0ec;i1Kk){r({VS;9ZiiYIt^6GQJmm
z_aq-u$@_iD5+mT<k~wsW;(<i;72ppgeY7~~ksPKH(OyYC{ZxIDd6Y5gm%KsI-ba%E
z%}3vW<SmK_4obvS<1!@q^C8Hv#332VMkL4~<F1mNq7vB0l1ucc9G3`f0H2U-rPRix
z<TVObO-VxCAvrDiZ3@<BB*!R(VJp4<5X4T}M}?90(u<pcbC52frHZ5U_#8~uQE4Eh
zikzhWt{A(s^n1EAT%?~|g>_fyRSFlmNmo%Y;FxsQ0f@Lu7o@_1hxFawq3pPH6>ZWy
zrSnM33F%=9OL|E|JJIMZ<!y$$KGLUXoqSR%djp)WbSvej{iFvwq4Sh<KRv<xr6Eo5
z^R!ez+0Fo|jH)FAr2@*)21$eInH4P6(VF&*bcF{<i1a^tnVyxt?*uMXy7d}Vhe_L8
z(HJh3{02aT)QNJmk<u4w#Tg~_r95-AbUxi`G16cvoQRd~ZG`nWsY4UUIce<yj3Hjy
zz7gDcspAr;z940G0iGbOqm}qY=_^+uk|;fx0{A6q?bDD<k}jQq>dVp&x=E6y2Pi6*
zB7Kq49;s5VDZtaDztLJTUE013T!wVdr<mPLshVnBvZT9fq2-G7q!0S8N{c+vm@C!L
z#ywA(PP?9bY5v=Q7f9t)O>s@Sq90CNml~%rk%iJh+Wr?wKca%QV(EX;=qr&PJ`GYT
zomUQ0Cf)oiEZmTCk3pnds#^!HLVAYo{z|Ev2^OlP%c*#-TG~cShZ^bjvoLg1+C!<+
zTIsz@5UG>uyFlut3=78BAU#I`lt$^e4!9<1kP3iX(u<TMx-C870oBdYkv#OZNd4q6
zdq<i;kNZ~XQVJKfNmo1#K)W=w84h+x11SdIDfP|)pi8=fPCVR|cHaZ;o^<S2=)5oe
zi8e;v(lmNOKal>*1>m97buJw2kv^ccRIl`JIvUd_4NHUSeyR6S^gWU`Q|Zuvbd(OG
z4N8Cd7Fvd++ctp=OWT&h(1_G47r0TW;Q!xT(!2olJ&}&Q0>GFwmR>01(xr1jCZs1P
z&^IYPP8q)`Y3?K%r==sGLCcJ^auEQwvM~B>?PP`Yu(Frws{nA2^|XO=lr_^WdQ|qG
zE9|+*%FSqWm0kY<B5tyRI`kcrl~7{SU8bi{yoc<&zrh`s1$>41^pq{4^Y$lX%c-2q
zOJ>vq;4OQgL8Ff>p#-ygQuakK#_lVN{}{wiHb;oYQ?k7SApWw+9so|uo}~vwfb0%E
z!2)H;o6#5~V}!$Aux#C{P<=+W%?y`9WZ&qa<*dx+HvmFqm78HGOxAn{E``f%C?Fgm
zYd!)lQszQeR+Q{W6L8V8PKtlV$Tm=-F;=#c(jIZLM>Xg>C!1pfW%05*&T#3x>{tON
z@`9|%10o5se}{p)DEoLRbSBF3ywG<^Rzu0zB-w&_=({W%q!o3tOh#oJDKaAk^i#pX
z&or6sHZ-Qo<~Cy}88Y20xSJ{4X@kBj*`;!DS7hr#(05gqJpw1PWu>%L$dPH^h4oz7
zq#7c5GWII~<jdZt9YcXEkOjas*^`YJ%5|A_6o5k6ob4D&k&KxGK(Q?6Bt%MNPc4L&
zQrRn1xKt*K*MqB&W%J-}rK~0kB2_Xq?JcThg|9-SMi$`(3pZt)RgkQe#ZzFnPS!wm
zdG)fXw=w7j**01UG|I+FvPss^1MZe={%inl%VJ*w*DQ0VQ<*I?8Ku7O$d=OS(N@{c
za`d&yJ`Kg3waaeNt=1v)s0G(4D;<F9E}3N&4BeHLxC4GqHjk1n_hs`bQ{OGyPl3n>
zvP*t&_n~aII{-a0{#9_jvR@WJb)U?cLXZ725zZmac_drE7VrTXyAFMWvPg>M4av6A
z18`VYNkP~V86y#%jmj2L-uJOgrG>~7nIRImF<Jko;KpScgD^B9`+*A2CS`xU2Eddo
zj8+2EvR7XQHzWI<o;|j5#xS(l$v-&)&R*_ImxhD<STAsn^4`B-@2K2NGw&pS?Nd16
zEO(;Upo`oq9u{2X`BWg_CO=LY)MN6C9|7(zms9bThdh;*y~pLAzOd&hx8DPuC*<wN
zK)mGo7h%s^ZloW_NB+)J5DAq3N)d@5dG>oS6fCzLfT1(;=Z7&9A#%pwXgn+bOAV1w
z`P}0eZJ0cil9%D~-GS(fkl&_{v_#5}#-lGr?oH>>W95(NlYw#akAh+LoP5?JNXE<G
zJPdMPF4+NcL4N*c_?aM&q9n*gdH6i|k|=-jF32T$%6jNblJ`*KWx1MG0?G0wdYz@n
z%jvpKmHVHEg*5pW6uwE9haUr%Ay1-5UZ%XE1d>_u^OQx*mW#$ga^!j{=FXKfEFgLE
zUqeCi<r^qGTp%x+#%Qm}KW9VBb-67CmI~!ZC=*j8fA1AE7Ry(!z|@t<CuV_^%C)q?
zDU;XGLD3uXQ7SVimtUf@j}`KURP<HKH55OqlIyJysg~FLjlLSW(FUYWevMYf_43p&
zAkrY;L2;Buc{D{pn&eBHVfL0hjKWj5<(cn+G|Qi-uQ;{H7uti|k$31Yb*=JsM&R1y
zKT*|cyZjy6(samKA45y0JkJ|iy5w~Rkh}7K?_-$v<cC6F_P+caE#bQ5VJt{Kkcac(
z(nI+dnc#Zl%fE$4uY8*rfIj&kEv)<HTpw6?B>!arlnux)(F0;oZlwy1A^A^x;LEW5
zCn{?gky~khJ1YO+RrvB)eu;@`9ha}5W%h);FC1i2zN;68rsTQ|aMSV*F@A>`x!=#=
z>=aHl;OrGY(uUtb5i|j_j*9*CgCAA+biu5XVm_5cJ1dg4m<bn!6U9bd6`52D;-)xE
z8~0<1{HNiIyP}15^B#&*bX?=OVwB#go{BGu0XU(Uq1Td^;v)(dc`IsZN$jJTq5#TC
zg_)8dzKTlvhK-*>^E9|qisvXu>8~iPz=%#O{DXlDP{dIMW}srE2|9xmWAuH7V8tu#
zFmy(dv<kQo#Q>c)KC7sq9eb#vnpRz5iv6@L3s<Dm{Scv8O$*jY#ojd_QHss4L1(mL
z)E{GrQLLpk!#Tydui;C);w6d!o>x5g7=B(*gi(MfK@sEy+(m`w5*SKUydehslHx9f
zWRn#8Z$t93qK8VAk`*@e1WQq@?}jg_iag5ErYUmh_)@x}$QF{his5<CnWu=S2U5P`
zS$ZiJD3(*I;hG}T8-3Rm4uOCdDPq3F3>GV1q7+(*!bBT~QpJn3^Da|pcR-|E(Qy+x
zD-<dh^i?X{3ei}l2vb8@wPF_i4mTA&lzysJi0Fw~r#KM?u3qu$|3?-S8oCr46^p5w
zqDgW48bod>o^giAZG~$atT!vPHW)*TVwMqR?<nFgV0^8LO|;f;Qv@xCNW0=x3+AOm
z(JBPIQ_<W2om~pA{g}wRiU3OI-BT3Ny6(Qh?=z5Yg-8dT4-~s*Ao5U=wivh`g&*Dh
zy^8u8SnpH#Qi`x&(QygfBSp?L;06@OC{#VDSoi^~4=EPigG<AT$K>^h!axy%QN><b
z)I3&<(IaSFk@GclPAJs0-<(u1AHe#Q!k4Ofrxoc7AvvRX_YY{XQ+m_!7kgzK?GYT5
zFVVSjN9Aim^c_{cMHzQz<-&KsxhQjmu<oi%pkKvJx%4r(W6IT(tnpBO`TsTfN|$m-
zdMZ6AP<KLkU=ku;%0Iq^PH*KBN{RR=S+v|bsr>hK5MSk!|1dB=Wf}{(Q_6{4i1;fv
z(8l((a;OB20m_54+747+r6Q^z<p+Zpbg;6B7D{K77P=cllrx7g%(F`2L2#kUt<M1-
zrkqP}^l;_G1RRV|eq9QCk;)TsuotC#tqCMr+4~tpVw6o*0AiJEN--00$~{!)e@=P$
zRgidPXDojA^UCud0&qdO?>9J@pj<(#i;K!T>)}L_QWyfs%gPAa0w*g)6!A<^Hgn*0
zs`9!3@HFL*6q3zQ-lH5?rcy*-9L!Qa^*=~nQTkGK%2lN^1?qB?{5IfnmHna6nWt3I
z$+mpu^mUA{KxtnHk?YDE5g1XSaxE2e7b#zIf=ID4l?uH}l;8A0vQ&A9(qv`IvkowH
zL-{V1B9|-MDQ{SzjC%?qmCCeVV4+HB`~N!|<<2NH)+nznf$E#ed9?1SRpySOu};~2
z5d*7Nj=lpxgYstzqctj}6wz%`GM~f1ZYk{t(05x|PV3}m<qP95)S{d{0VnP#AJQYC
zRhdjFiZ&&Ow!rPmNcwbDhf-dE5p^m*X@Q?z%4ets>#nkrD!}e3!`_3)edQ4|NVn48
zg2o<YUIz^IDz{LLQlGMSA>jSW3lxuhq}(on$beF`3{DIwZ5Y4}E8Xa*!-!J06x^sX
zkq_q|E8k3qp)uv6x6wDQjCvJhLiyc%Xqi;*qQb!`rNs&|qfDXQnXRhO9%k)Sxhin>
zs=CX7JE;EM11B6+3uzs4RP`z)7o1e-OQ6hIwV%p^TvUA>7__VEm1%Hps_PHI9aAlI
z!F;-_w$i2Op~|D!_HotGXF)tw^Jvd?LKT*d3Gq@j3Sq%pwVbM2d{jSBnaD}is)d02
zs-FE8_WV@aDbjsPm9Y@2{Z$*k2jH}-$_#e{RF$+A4pd#*4K7Hvg${NEt7d4&cSe=U
zgq9Fh<4%}8t1_`68LFBdgrP8%2gLv*RVSz5M3hRB3tY5naR;~<)m97Ov8wVi*o#x`
z_!y1nRL^e);Jk`Y$B8becBi5-LFJnVvlmru^g2saJ)k_vCDrVo;9!z!F$aCgsv<K0
zDXPu1i%eAoUd0cPrrJLOlCJt+77S&mo={jaQ?>ghJj+s@al}MkQN@LUyQ+FZ)i>Fy
zEmZN6tIBVNOL?m0q2TgWt&}?}P&ras=bCDaP5@n3;S*-Kb5!p?4=0LMf3AV*64mAi
zh?J@#G=P_>2A4wT4b_TRSSVMCs1l(<HHRFmQXQe6s#<lKN>*xAn;HPPsdDK@U#;q&
zUi8(e?&JVhuX;-fu2D658eEg=lRQ|srMh?*GjUtB{tnDGtKKX_W2@?06YRCA4h2A2
zyUKPE=A}c`a1@fAswgVd=u&mill`vhJKB2PR~ad(+pT(qsv;h!Ud@8YL)AOqLs^e1
z?k;@kRsBYVFMX<7diOt4z4{6o2UPMtcs;0cUIxIBDw8U*hE>b|12>{7cZcdxRg^ch
zJXUGbVf~3J=Lc|OD&<MIG_E@50KlYbr4(AGRQ~7T?zC!8AI3MMN<07ywrcNJ&}gS#
z_Z7xxueM(UNk_Hldnh}q_SglulbYoSfU|lN6}PyklXgP2t9t(x;M~-W4`I(;eMJn;
zL;dbNkmKrWV^HR)woL(dLLEjsS}%11mH2wAJuDz6)nmV-&sQDe3=4khyR;)ZrQXQ`
z@mC*IKxd$Of~pXM)R(g%8LXbk2X{ujdIDUCdY}T%pH**u9g`KRzIhv7hpR^&AQGW2
zqeG;T>LB`<Xq0-_N;F2R^W%YwQTNf<W7P@tOP^E!>Iac{^(tDdpI5KGg2oGK2E9`g
z)F)ShyQucQguX=e6z%vfsb~KQlB9l_?%T`igwHXsWcAN<KcuSvoDJvG)GyMrCtb~d
z9!_Ma?PybxsebD{{8U-$y>y1^iu%lBh-9m~W<w-LEm{YXtFEBHQl7f;47B8{i-h0`
z)T@ue!Zo!s)xH+0Mb&65QuAo(UaVeG3R0q;Jc7PbbtJ6|%GCR8AaX-p>IqVzZV5nN
zrP@mC-72+rB}lcJS%k(K^=}6;FLmn0v`?*9H%s7IgIYHOkw$eMot$k_Z$E{`Tk0&@
z4c=CZPl2?kchXs!JL)2uo>ukVcDUQ7?)eGU+tvT<hw2VBXD#5J>gpl%-BrIe4nz0U
z`)TofU)?fEH-b9%B>*0%BfDVlp?cq5kREj}#T<Lp>)yg-^{IzxY1^-!^%`_OQioB_
zW>9^b9v(w#NghOo)lYlDi4k@8Ca4}&CsW$$vD!cdR!`I)&|YR-UB498C)A>sAUUc2
zaTg?~)NbEGa$5b{L-ft4w`lQm*lNC@b)>zfkhU!j8V!X49W|$iK#pqG(2we*QPYCQ
zS(7vaoQp=h29j=?H+kqgrr`)-!Cli!RY@M2i{~M7T=Oh#6}&X>Y{MA5HQQf<h>vFH
zK>+ZH@rCH~)qMW~-1XBqZH34wP0&p^cv>?r2V8(=$L9b9YOdVGpo27D)5;@QQ)C40
zjHZ=VWFeX_8euO~^YuzJhG~}3+ag?Z<Q;exp?UQ%oQTxC`V1<hqBPSn7)rE8Od0SP
zjYAeltY$Yotl~6&lmI%XQ86KMUUP*W7Z)`0DX31+EG>Y$7d3CtL7+rU&mZW!q<Qr&
z;7OYIDq$g6lXD9sMN?b~cT+Xpl#of&w0;k-(=~rCL}Qkw?k(W1X#S+D^{U1Y2SB#w
zGLaljJ8gP%HJf5#Jx>#R5{(6#=6ir&(^OF2;<~0g8`cXoQxu^q(%8`Er&#kUEow?M
z-4w?x(@ap&!3~XxDq71m-#CD)(5$pVb)_cobu?CKzMw^ZwPr;&oT$;%2Z7wwY@>*E
zt;UbGopqY;XG5ex^EVwXYSi4&z<QIW<#UYamZlW9_?+9Cr))7V%^Fo8d}+~a`~!Wh
zntch7Yy%vP?V4X`wbr3Ay$#i!nvfe1xu@~ij>h|%s9-d9YaHq!`9R}DYubkz6@@8!
zG_QOPkzS1tMY{Vn^XkAo((G4&3}_;#%6U-JbpXnSG#3{`%dqA{N(YT->M1GsSn~qC
zWu9nisq}J8<98X{xaN%nOwWX7F2$uLHE+>&XG+7RfX1{Yo3e8=ny+cDZM6ovBJH%%
zn=p0<?cg9dNA1REK#pp&C`sp}4YvirS*xZ^nu~UCGWuM#ODJY_Ok2AiBJSGML@4vn
zGSv_{u5GRZ@zg5qAmXh(bQzqF)?ppElUm)gAimnp#c;__Yxfm~a!MP!07LQDMoz&{
zfYxIb1|6u490o2(n@Q#H!P+~NaX+K|uO2@~i1zarVfL(6POFPB?Jar-gljj@3O7Ql
zy9ZpPHuYs#h|;D?0gu-1xDI%X)<lc$Snc92NXBV*Mnm$P_RZJP7q2Z@1DzMN_Ehhk
zpbepqOI*~lzkp<-R!_^3OWKdABs@v`9u=}**1EYtS&DYoZ<vr&?U&skY1+%X07%#R
zc|$Ton@^ACE84jf`nalnkK*3hS}pBYa<upQ0ngR0ZUo8Ge)unR=4-=s7*T=NKpWd@
z+V|)+Sg2k33Pg&uOsWhh)-Ixac!~C~5hA79thG>mLwk=xbLCpwZRo4e?xx$mO8XDJ
z=Bu?s8!!_!+ORzI-PHa}kI`D~W+_OWcFPl}uGb!+J#(YB#|xxM+ea0Ox3qhn2jI3g
zkIwNmYYpQ7v}nCPL*E_kDcX9qX}@|Ns@t`Wry<gzeSa<bI<<!u0@tN2dI*>9YE!jv
zuv;6|59c3f4O>ATYJ)m~>(S;YA=#_lN4HF$w&OcU_G|O0PW6%2kCuf4+WB9A3~BFE
zaC2CjK})d_ts6zDMztLVG(Oh$ltRmxHj!$c$F*Hwp>aaHW*m)ETGwR2r?s=_8l2Il
z?n0lfE{kd;>~slq%Ew-pKL*Z0r_e(6QQg^UNIK~j`hj!SrM?b;i*D(4xa6t}FM~2S
z-4|zI=$P*5T6pcDTlxVckL$Y5q0dt%ptt=AT>?F*y>yfF(dVsGu%X3Q7wrtrPpAI_
z!#t&9`~%KkmrL>T(>g0fN&|F9)4&Dl)D(jV(#2ngFTuLgk${Kj!b0K1SzWpaT&T{2
z)*)fKH|Sv;t`k(_XN=S}P$W1?7f9cOkJjZ;#b>NeK~Ld0-4!aaKc{m(4zJ^Np;nOd
zx>IIIUeHCX20TG$wt>z>ot-PRT+$8Eos*<%rPGy{bxY|MP1eo40tZuc=6}$bs#}nP
zYa(5D;5EQAbi?U@XX>ug5#21^1ij|3=!y+!ysE3FbY8CR4Fj~~>A3d*&(}FB!4>Fi
z=svopd$|<ky6&fWaJNwRupS~sx}7l)Db~$10bZhe{SZj0?&+s6lrr7<I*=PWFRGC!
z*Da;<Bo#W@MvzL~Wy%gz>FV0xM73_uCm=Pto}B>P)Qx0;)aphXVWC0CqP=0G&btuS
zn{>wgki4bq&cYaO>wb=a^=92cs%~h}p`ZYlzAlX3POZ9+DIC_OtD-<wyN*jq$PQiC
z2Qb^I+Z7GfT{<fzPwwh0ROx$9_k{BO_jMori3#b}-OmQ@fo=uu*dOX5zXZHTca3g@
ze%*Z;oOq<$dluY)?ha+g2X))JVRlHj%pGJ{7iWTn5#8?s=p5C3dk8uo<DZ-W_e3{I
zx#TgOiZaXNIxU@Np3oVoc4Shgr4{FtZsjKcOzU{|;AV86?}ipzz03fec6#Ljn6=lZ
zJrB<u^s|3JpOe0W);7+1tp<%Q`k$zP#Z~Wk8mis&fggYz)4S2S++AN&2F^ntavS8h
zKAHy$p85g0Fi+@@KMyV5`V9IwvX4HDqQocl2{XX?>eqY=Lw@?#+u_71eGrwd`|D>>
z2=TN&lGZi>`aX(g2kK)I&=;f^a6r!JBTvKK5dBix37^&fN~^U{y^c0pVfwvPxe~5#
zy^qES{bw<lmq>jQl^{gvpR0q;X#MC2`eO8Ue}Tm5uY3t7&gn1GskeCj`_1s|ynfyf
zFmyq$Uks9<|CnNV7xmfiLNZbRfRbjH^j|+gW0HQ5PWfEcU!^N6RsRjGBh&Qht00oD
zm;MM}GV~iM)0?UHri&p<Kk_UZujtFDEbOZODM~nH>jNo>m!n^{8n|5j;-@f_e0{JJ
zye`le&}W~n>7yS5cU`acMqi;``V`zP(yx;NSFC^k5QbTz-)aD$RDXc#1j_XGh3LDX
zKXU@`3jLaAF!PoAa}H>%(&te~p;{k&6Sx}vegizassCypEY#{ZUIm~|??O4udi_R9
z*f;2Jd<T(6{g1S5xus971i7uhNW0c%eKlQtE&8EKaCh_{I)k+8jdZfRP5<=<NVe<G
z(w@0P?>-kgJN5t3OR-B|qs3g`*ZUV^MBRE{TDm{b@1sQ3L;YGREbr0tm>|9SWs`8X
zPhUZmsr~vdE&%XIpF**x0sV)R4;a)tcR_Mk|Jn+OjOc%_fxDx6{RUWgtY2LK)lc*<
zdcc=4{lr?3aea(8{G8B#_y&|s>Z@}hGNnJ>guZG0%IzSwhH<KUvNM$JhNQirU@3Gu
z7~;OcujyzQYz24Ju=)&$lVJfBn>ZW%=p=!QA%teh)!?asYBz&56(a72-LxV0FkEba
zq2q?Vbi%^Za3CLm6Nb5TDS8=t=nnTbtfwcDkKyY7?;i}kp90`(Fj1b%&+w)IT2322
z_6HYWkT1e$0}YZ-U_Hn%LivDTgNTw!XAIqM!0QkL;}`&E4Z{Vn5NfzckC`xo1Lc;&
z4SVOnP^7_ywn9;cH>ijz+E786&=^DIx3Cavm``blI0KKOV&@D&&%nWW!}%BC(s{$(
zKY+VnNPi8u1cNpVB8i5P8gQ2k%btayB!exz&Mq6OL%}5*wona7iouD_BBmPtehGf2
z8DyV9XS(5qEa=QIaHzgD(@;hG%`1j~D7kReFiEFJvkfJ~AUOs>Gf1xC^%Ed@2K`R_
z9QlSTcVMBw&~^&sn&JK-;I13K>xN5(1{r;nx5Ut23wxyo{V)J!hT`WSdBgBNZJNpr
zqx4#;Fl=>%FO>!dM~GAz`jVlg+A!M_@EU{91^{jv?o$nNoq^?w>8Up)(DJ9ju;~g^
zHyWJiP10nLyTj})gIy3LZyV%aU_P4-v9#xEG5mZSfIEgtdWg3gx{@K%Zg{x`q{Faq
z2)Iteu5$Es8EVpiyKC4_tAu-o{ex({Zy2FSaJM0AA0!_b=24;PL&NXSK%~cT=wFER
z86<R9^&6CHVCa$Iod}F!!0;yR)dmgUxPc5Ap4tw;u;G^qxHMuYehkS`!)IRu{@8HY
z8-OQ<RTM^>Fnmiplu5$|3hYi9d?;)_ZOH70$c(`!7R1(g>UY?)GbWIO_Qt2_^R^Dg
zKo`IrjgwJ;A2qK35%cM6bfJ8Ji*XNS>RpY^bf>x*KX!-YF{6~ek>zfTrHrkIaqIwe
z9ycEN0K@b&Mx~+egz=v$sP-~$q!^2j@$)K(oHXjchXr5bbJv0MGyYqT##6>CJK(Or
zQLzZzX`_nl1sJbi04~sIHv^qPMyLJI8Ekwh95WGOtfOLuv&NQp!G#*j-vbwBv`GOM
zZtSHRx(H)>1}sDxg{f$aGCrUuU$k*!1qK#l?4<yEtWiTRsd!_O1ZK}0eP|nh!I<fQ
zVI~+i;jusGqVWi=Die(#(XRZGv7r&TB;!5`j$Jm6#(_&Vp1%t&#W;QofHY(DuYji;
zcT|I97=NLac&720jeutv7t-tViZQ+wX0IAw+lanw<IBMyIYtc+p5+?nP@FH%xP^8$
z1;*tO;I0|ZQ2qRM<Ng&Og~nhi=PWXM(rdohxUw4X5~Fu4;H5^_y&z@AEqft(!?@*b
zjHujL*8uC4#s$yA-74d%b?B=$7LKB^#u!gog`38ew2iMdN<RXrGcMc)E%nAneo)<D
z%!&usXnejKzBC!D)&kIM+_wPMTa0hWFqAt+*I%K!-I%=>eI3SCe2l%*_%%&rkJ0lC
z?DZNK&=#uC7)NKC`i(IZ8h>Og{|;op=tNJ3LF0}TSQs*fP$}K8@y^$<Fk*~z#u!G8
zlb+xn8&l|<{uATOTWB0JcGAXu+&JGJ@Cjp$7aAvx<@6w%G6os|m^OaDA7sWTWuVd4
z^z1<Z>`dc(A!%>AS&xA^nE1A6bTs8MFxsOg8Ku{pOfyCd#o3g91om7^Z&FdHtLY+L
z-fpH1tARUaN?eISyPKLRf$m|_gh0!2)7O+R^fX<g$Jz;#g7UClrkqqXdYcL_fb%i2
z=YX6vZTbyxU(-h%^!b_6zQfF)GPR^bi@zy{GPb8pPthwmz;wO}B+zt%B9}p?_!7W_
zO*!=FI%B%lim`{7GU!!))^utPoDVhap&vZV^mHe5hMU&Opfkesf*ycKQ%y49QKmBo
zpflREm=dBfrni@3LSjuhRKgW!dTk>{bk6k635dj-wueLHylMRaR9`Sv+QRDu(*(UK
zFPb*d&!1=t*TUW<lihoeOfp&MS$EmwOeb=ZO|P{;B*ny`NK~q+nU*SPrerD}NH;an
zdOpMC^e+IJrtP+9ylQ&N3_r6?`ToG=m@dqQp<L5H8Gz@Rp3q69eA6diqOZWDpz4il
zreCVicips54#`4OJ7wI9O#e;7P_e0}4(^tiYN(>1)O4S&voh236cfK;(ohk2x#=K%
zyP?9w_5rCh{XunkRVG`y@v2S#Y(Qg;X=NN#-!!#Q*+#AD=x#VsXKH;7@Osmc9yB(X
zj$B1!qv_-)05qAV??THhlgoc_@V4o%x#(*)Nxp&37E=_JOy4mr`T$O}no@_MrOh;U
z4;I=@U$}wmFtt#mt<w~n4M3Nvl`f6DCjK_`-82131p@a?Fa8WI-6p97jSo!Og&5{T
zlN(h*^_ZGEpsd$)<Wp$rGcBRpu;26sWttwD?1~{WV6qtnZqW4Q(@-{KQhW)(uqm?+
zA|ocpPM94vB^-l;k4<;m0eE71ok9^~rc@f=xalKWJWrT%7h_<PCQUX(rc4{?aX4+N
z(?jQsX*Csy+nW0l0kAWl4~B@ndEZiqIGDqz7S7T9)=KC+YF<K{5hwF3s$X(8U-yS+
zF6Nh)f^#)1a>2QonO}iBW^Sh_oV)qg`DpYoZ}x|uC(N!xu;693e+7-+=ISJj*2kPh
zWg;idoVNk+HT!>oK0k9x1iU_FE)jwAH;4a!eTexHy~6{{_EfqMXfC1!U646|zWWnw
z?xOqsjCnj4Iz!CcL*VsUa|*59Ld`#kF!nIBl+rBW<_$X_8DTED43S9l5+y{U%tgO~
zM4RWliK{NgT>d8fj5P;PkTTAEg5p`{%<H~HU%YwMYnX!b=AQ!~a>4v=F}MWtV;b~D
z^ZU<$B%1$u5vnhlZ_}<I$-MdixXb3>WN;$ctfLy%6muml{Zh^ElS^slMLCd6H_yEQ
zkqmR|QuJk-rBn`)Wlp5v`xWzhn;~-5Y@G!svds_aS(j&ay$nFU+58*;1?B_mFfZ54
zYw5{w-MnZIR2Q0WB}1~vY@wQyVsm~ul$DsRlmja@zmp1FnK_1HEH}(&q9IvscD{}I
ztT6Y`Cau!^(E=!|GVfXe_)T*=y>n{KIg}2nGk^0j;Pqz3W*BNPd*?v1(VRe$g(kBf
zZB1^O=iGso+vfkRLtnFbno5US%muU_yknk)zd5buf!`p~X5JqNuH9_=97u=x4IOlL
znzvDWsmp9fm-k(>fOgRL%<a3u-8c6N;Y+u9K`*?1VE%;C_Ycia_kr}7hdu+m*Btgg
z_}ORn-wd<;<`-+gJu;Vn2%Q7wr}M!LntiB7e#l%)aiU@K2N{5mn6s`y^{DydB#_7E
zH_6>6=6}|K8#5<;2$6Af@(6zE3A2tOiIe8qGtfC@zI6@5oHqCEfXIyb-vD@KYx&p~
zs_iUc!;rMMY?NXQ4wl)p6mzu9nTx)omcISKIa&6w(dTSgLn#;+%h&W3AXm%pltXc|
zxc&tvj#+x?0qAZCX$0KEvdR|&J8oev0^HM5TMFC>OYLVMUY6Op=<~MlDD~!J`Fj(T
zowUrMG_J4Z4?g<*EJglkJY}i)5>EJAifKu8+M;fNp#V#k9V7!S=iY|(AWP99kYG#f
z2t>|UX7xg6h~*zDLpy6}xd{?#iKC@MnB_E8#)Vtn+y{7+W$tD)Mq6SEU?|42n=buW
zix-`Lh_mdqLE|~gcQf!M-Xbc7h4Ypy8*mpa0aP!XU>T@E<3-B{6lO}am??gC$>O#J
zT9PbJ)4t=f<@-QrNw(y-f=jVHM-SXo%X)8^O|yj4jyBzLyA<#Yi+B%6rX`tDc3GD1
zsQmtl<xw6QuUbTlA(?I2`6;*@%N<{Ext5RpFw8v5vKWwj%Vr0tF0lL%3G3G^6F%_l
zy5(hCOh}<6=STDvS(0W0S8Q2CWzi*;O9Ch>wOqIduFSHCs+@0Fjy!=#xn)01a)l-8
z8kAL9R?zv)DvOgBM5-<K=pj&Jd4UqsH!Wid7^<~Ap;dE(<xU0Qjh3qyL7FU^1Ax0_
z3D|?a+m_l<7;3h}(xarsGEfYWJC^4uj?!xR$_&Xi%kp|yXt!)ngoO@^?~lNBS~k%o
z)n##yf=hQTca&(nXZiVEkoy*o=P{ApmV;kI=L1X63*a7FUMPpM9?M%4;_kJSo<n1w
z<$5gO{g$<Kc;k`f4_Yq`SR6%ge$euJ5k!V8YiS`dY_U>2WW+K_pPU=Dy#G3^Kepsh
zb<q<`VjJdj%(5X8fN@KS6nzsG*WX}h($X9Zol};^df=ulu?L}S#<KcpD6_S0rIL3$
zD~s|+_SV-aSMFf#y^B6a>y00w?5K784FH_16RY8%v-Rk509>qpSz*@In&|=&H*3Nh
zn4V+Sz4Tsjx8^CK%){D9wFk$ox-Wq9w95L?c*6P}Ra|>nCq9IvxAlce5FhIrx)@Gc
z9m3J)Yu)$>h@W*G9VI?x-AEZKe{0wwXgO_7qJ>L<RYecEK<m<%;aQNC-3=|l*1kU2
zJ7c{wfyNN)fp>sAYmG~RgP~UT2)Hoo_mo5qx9$xA7h!$r2mq1R!#~1$ly!)L{n1wY
zb0Bfny%ZxmXAP%NOT4vX5YC^suB}4j1?wOcuq0SLMIaZg)AZs?w0?XTPF%7!ZvsiO
zCR_#XvbB;Dx5?H$i$GGW@B6^BRO_`ZFq>vQLTRLQYr@}9onigW9a=K2i+6xzSwA}k
z_!Vn^AuL?A&P0P`TR)eB<XDf4z(TIoOi}4P>%vWd=UbU9SSYaO?Sjs0R`2`hyKa4l
zs#XiFHuTIYvd&)%kz(tA1pt&-U;Y-plv-b3h7pxn|1x6=ZdgkjV4>Xl_$f$MSeFOG
zmrCnXIw-5MZu}a3)z-^&zt>pzQgy>k>vAf$s<kdY2$4GL1igLht>4lW(qO$h0Lez{
z0eb1*wz|EC#%AkDs^w_0Mp4Pi9cu$6v0AO3EHt)RUz`ilZq1#9FCEsB7C6{x{nj2@
zx~y6X?B2D$ODn5;*3aGm?!I;NY5ca`*1i^S53JW|AMnt+<RM6pmF)vuuk|llarRlC
z<Uw`6wa^T}Bdg|JxI17qy#z97o&E@34_Qr=YaO;O{|(%Tb)1$QqgESwl|Qz|r@-tJ
z>&x`X<1y>gR7y8)eR(e$C#(sS0hqMLHe*7jthcCoW7?{kg4r4C*JokR)@Iunh@DN<
zUm*52ZM0H#u+g#LwWCeRukh@s&4(0tak6>X1Sgzr7VU;k7n}K1nCxo9rQ%#So9Vxy
z^O#Ly5CF$*wo@sjr;XQsIB~*e<`UpuHWByH=xvj+2)_8(#3!Kfq|NtZm=IqZ#}&Z&
z+4NFQ|CEh~H&pxEtXH7#w9VOOSO~B=PQwheY55Oakj-Y=EC<`Hq{8I0|HsjF$7Nl8
zf19S2mJPG~R%SMBTA7xkp1t?p52dB0l{PdhK!$*T2*@6?1ymGNmTVA_DN_MKWQm9%
zAP5M*_xb&GUiY4J-sjx=e8#=!ocnngObSIDWgPqh7GfB}b&!l@EMJZh#W7MT6cNwZ
zdk&ZhjEOKfpU7C72$IBzOa<66MlfwxlNmZXG?2pBPU+ZG#_L3mGdNM;onZLAfU%!s
zI8tIIjj^2%=u?cp{s$*cGYXbNFP(9BAw)75)s$2^!-(7uU(PbNW@2FH7!EI@Gn4Ul
zHNdhM-BeAO%{Wdc&2kt|(b2SAMhY$6&oh<@U?Gq3C>7S_GY%XBDPU;#LZpzfi7u%k
zMs^(ZiWymyh$~@ic@mwaj2%zIP#MFGf=(A0haN_&oN<(nC|zW{<ps<N#t|kIE-~gW
z#n>wuTj|h16{D&TylTc>+A7pADxSiK>KHARuyC1i?op6>#tJ@o4GhUn_|nKQxI(0f
z5vc=dW_(X+mKH|eIe=YZ_)!?<Dx)F+7Frp@bmO%#+9{mb&Uoid_<4;{u?S9dF#cJB
zU#yeSs)zaw#y{(z-py#sf@BY4#k=V2WjKXHy^pap1(^MeOIM(9lVPQY#{grJo*K6p
z{-N+}kWu~_27Q|mLUlnyjE$Sny2Cg@Cwzw)7OG?(VT_Ce<t}5*O(={q(q0A17-L9?
z&T$6kW9Z#uq*4@af{{c4jY-DHLilo@;X~yfQ;bN8T}(5=8~`@Mcs3m50fSo&L$i!&
zDy*Ah91H`dBlG*`Fm@;Ae%j|aGfz;cdOvgDGZ1lM?xw|%E3<9|Fx{A*HQ>23%PCTG
zfZ0YzlsuSr%6)n=Cq9Fu7juIK77j9BqX3aN)At%ge3*{8Q1@lZDBXOBS+xQRe#|fm
zT^(jNq+xvi%%~)g0OnJ)ZVhB^rIr5?W^@fk8^r88gYgA3k9fm+2=k4n&<bU4peITg
z^ZM5y;Y?9JcoEFyAHjMg(@qtGQOsv9Lo%A_M8WW*%qoi4#V{2kkc?&CpcF+M^Y9q#
z#WR073WWsb*GB=C$h;j2lq6>2Rwx`}M$ua|nfbFE3MtG++Lfm=55@xXIJ1Nvu_u`N
zJhV<SSt%fC%-y9BImNu)2t%itB@~`YXMRMtVFq)Oa*Ah|Pdty-S*9D6mY!ptD+bAA
zmfi#}i&;tAh-_xyFragoPf}_lm#L!~<nzoi3Y+IKyN*FUpLs+Hg#zZfKu8ucA9lkS
zikJqvOiP)S!SJPwnWIGK1?CY7%9JyoltAGk^T%lLDwqp8!Mntq3Iwl`DQg3-in)y5
zjn&M}6);r8T<?wFsFoQ=d$l@dLNE+nW>$BB)HA;%CmNWqQaZMgxw8}sP0URX!QE!2
zV*wOenBUIF6kK6OXferGnWFjNwK9basJAiK(006?nQR8{8uJ5MCwDM^Yk*!S^K%Y-
zxz3a?0cIC-gf>k#m^Z$JWH)o&6ddefhG#>)m-(Rsczw);bQSb7KYa|mo6KzyAOlS4
z4Pf447E^F+klFG7cO0|M8z@7}4G-YN9j2H<Uc=1MRR9}d=FmlSmuaE*$|!Rcz1YW?
z3!enoIMcctt$R$f9kV;ZTtz#uN#<>;l)2Be&%xa(=GsT##5A*sqTn-3?`X6hFwfB4
zKg-<o7BJ_SF#_m0vOJyvrV}fTHk!_?@=>_7pEa3-P8U{*8(OX`4edqUSijMx*PXTU
zZw&JQ>kE3#d$6ukir14RX+WnJ>s5NN9Av%xGSt0U*J)GX!^-c0h%YO}iq1o<p<OWR
z$8vOn^M_gIR)P4l(y3-BfVJ&C@Q$#y(`^yN+P(r_2eZ~vhB1US{so{zS;bW79mYDh
z4xQnwjS+y3U?tK4+DMkuXXuP#JxL`p(X0=0&^pRuQSns_YafLWV_7Lwkrl@Z=fOfe
zYi=nVOkllQg7GD?_BsMAiIu2@FUMG4=+T+XDqIbhQdmaXex$NqzW|ZrEdMKLonVD5
z1j<R)u2n!uW5q?nvs0{9^w2rY`ePF6>8wghjAgK1p(yGZR^o4Hon@ua2JRe7O;7er
z))9B`vRGyoW+I#QFa@A<Sl8)eE4i#wWZ^vPaoTL<u^xI8(D|$+S|As&MyOV^kR_&K
zs3O+iy&%Ob)Bm7Q!upez^`)!?3g(otTqxXrfmQz&6v|oQ0T8KR38)1966=3n=&WRU
zQYyNN^-voWs#)*Q&ZdU-OAhSSvU=~pvpUwse6%jJ{(T3ndX_)^Dh;gPXgkoz+Es)R
zHL>J$)itvg(u<*mRr@q}S6JUuvE^0P0PTxgSy>0r*~V(7NK`xP13UDtv0_(X&>bu{
z3YB%TX12hy>nyhyFz7Cpv<G@OSjI&l-7G$xm+4_0psh(S>t#x|^|72E!5I2kjY9yt
z$=XC!Py;Ltl`-97wNfG9AS=Hc<Ti`(4agAd5BgE>u-;?C!Z2&WAq;GUWnBxDyR31#
z%12qUOK@q7wUx@@$64=C?aw`yF&$<nSX-ZfFOw|ZSK!@e{oanwDVB&<>C>#=X|XWF
z^7{==JYaoH%dJ^fT@6I$Siexn(vkf)y`7xcXI(*D*sXSSy0UkL!=4+vVF!pidxFyb
z2iTGCfOxP!qn)BByS5PSda=t&Kn}8>p%;TU`*Aw4;=?{f;V@semNwFd*iT*o@nioT
z43Wd^z`x+GKRc6_Z~^S8W$-hQT}>~rBkY%hAQHs(F9R=_{b?#XL)ZiD5D8_Ez5?rE
z?96JAaCRB3cO%%J?F289T}2C?DE5ov;6<~mDNS~iT~3SA7`B5iz+%~3*JCE)*t(ZM
z;@SJ|!_NeE3Y8`%vWq@~dJ=mjWx0>BZwo+@+22tSM+*DVa2PtlesmpBPO_)gLLrSk
z{t-G)u|Ffs(`=avPNcJEC}5hwe!&KEhHa!Ole6r}Y>;#8h0(B($!?5?OIhssZ$mws
zee*BOOAfoA@(8)?e2U$lXMa!#LwRhc$Dx<cb`1b@0b4*t%Z2Rk=>98WZ=|B$Vs_eD
z=#{Xy(ZBbUvUkw8uFBX6|AU1K>|InwQO@SOpmmXbVi(ja*sgSp<q~_rtC-|Uwn+z(
zD)z`*uu#o*pj~ne+u<-!YS}7B@aouCXkmSs9hV3T_3V!_(AmJ|tOaHxTeTV}P3&`@
zfY;0pp-@W;yOG{USJ+RsVP3AX%PHN}%Kn0)cWvy{dk|@7_h!SwHTIb>fOW9n_k=<x
zJCahh*V+0yh;*@;N_5^}2htv|o2?STLJ#{<N-g%Yhbtg?lO15eWDT%)=K$pv`yK`H
z2HF05KyI^5HmDD=V}0S^9rn5%Aj9l10mukjPQ?Rv*@KP19Az*25T1>(-?;$2arXLI
zcy^B+G7mrT1UrZ7&nDS}2Vw6%dkK{iOtBZtf=sh#X|+AWHU|Rb0ekW>bk4Fhv2baQ
z{V4}1j+{N$A>zcDN0+xV=LY=%`#Frou<pV+dJKB5oYnMmxN)3X&~oRjy$+NEoIhzn
z?!jTc1a(i27gb<-anh)q<shd}feG>EyxWJC4@XVQWnWGtEuw-svxzVp!ZAGu63Q{U
zKr)PTjW&$o9G~6rEP^AUfJP+eCWV=zI97VrMRTh5pmmfZq^xWVr#=$aV>$VhDU9Q!
z4niTG(@iV61db=22uS2CJB2YMaY7z~*<+j!X`7VHiEM{2DVztcAgP>%be{4!XB~xP
zPjFgahU7`kv;#;QN8t&uQ=F0AXr1OPr@eMMXKW!1WpEBs&B7VZn(eTDma~pF0OvT5
z)0a&$Ic{{~D2uaY1BQ~#k%z!S4(ER_g5+}U(A)Ps=Pjz8%;UWO1qPPSSwM@70?u`M
zY!`CgD1>AQhrJnKrJTtWbe3^4X$^gWlR&5Q$~jS#!@S7Z;0s;_XORUcmpGeuf>+7$
zr!{6ZNAopAYB-!3=+$ywryNlor=SAlGUvxKSg7Z$qup);Cx!~18aYLuz+Mx_muj$@
zIht?KYT-1~d-Dos7cKd(a`v6T)!NE={xSyL#&P-sybjK*^f2z^Oi=2yi<5B)>Nhx3
zzrvSpj_w{rdN@rZAibQ8Tj6dWCngUl{Tv?(N8jYsP-J0%(?wM+w>ZD#!IweKB^uvt
z&eddy3~~AvVGMUTx&dGgb3W0-vk}hlFhuTh_;l@#avpvitufAyEP#!3KI{Ow$8n)J
z?F8qQhhT4#qx%4!-RCT%mDLny;1(37IcfF4oZ<XKQH}>3&(8rp%So2P-W(^BVscL0
z1d8iBbLXW&az8hj0(@><j}zdzbDyL6JivXKR@5HcgvUWVxgrXGdvV*o1o7ckUx9)z
z_s|OP4sq4L1I(YBW`RoqTyZ@_0=X$nw2p9pqTerwySyKg!Q8Nq(HX-1>TOsE<$gj}
zRv331m4bwG=P2|a!Hr)6^+@j7I*3GZ?Q%dzbN&3$I?CO(7br1Y;p4C#%l&r^)Z@6x
zqag9zwKp)n1a5pPP!hSH)9X5k`;8D_$GAsb!As`GP|`Yu%cBiPDmQpPz>afss6^%j
z_q782(kHpjE8t5S_v+U`ImIodTl6$nNtxGl?j!%9mBDqPV+m)tPW0iWv)p}|06WM1
zrvrXwazlq9lEqaU;b1n`pQ7$L+-3^b=5jk;1ZF-rlmdzc+}*T*Eaa}F(#s<5LLEpk
z_tmceUBdnFG+L$H&6U6`<3^u>pBK2#(3ic+xi_mIa*<m`3#<z6Dq3<};x<!&uaet$
z7o>{2>no^NbNO^yu7;aRq3T-hYN~mz<6fgw!)0#spMb9C-l+j*1NRiI;2XK`#X_%%
zd;cg}SGdQii18{{&4oxS_cX0^+PJ&xK-#$<(?jkWH-(<%9o(r7Sm@*~qH_h;xxYS)
zRyTL|QaISdJxphhd%3P5=)A*ayb0)Gu95;FBV6o+aCviorR?fBH-plL_qfBKgEzsw
z*bhUK+?5ib+~>Z%0<9UYGgZYu;66udn_2ERYoXx8yXJ>MJM$7(0cAh$TMD?j@D|L0
zxbnW)3NSa`&Q3@k;@$ojD1JO;D{i2}yyfq}x<5~S5nc!I@)}_%khj7Uyd%7SsPrU=
z=e7cR!Mv?Bts%V5<&X^Jou=q{7|%Hnt#ICE3KK@~-k_LqB(IkyGMd*<*V$3tr`7lY
zVtC;cyNKm2r6o=r@6}nf;(1Z@m`UP&m;k+Fyko`SCG%Jc@KShJ@4?ShUKq{Nah}6l
zFm!@fP4$W=d9TxX(KO!b94MUPJx2NP(>$MK@X~pcE6~c|g)<;>h9}qqk+Zz-sOat-
zZ^Z;$%H)l#f!Q41E~-|}<Ne!&Rz7c=5u||Eya=6zJdeN7D&pNA24*oY>t9Sk3GZDh
z@Gs?A*8sDOw`2iay1)yfRC_t^i2(R{k++&s`xU&Nf1!7Y7vKZ4l{|k76smX{T2)r_
zrqm!cyfG@5tL5d&(5mC9uR#4W&-w?{8+kWQg0%CBX_<YEcXAmFb?`i?PN0)_of5Fu
zd6`u3)Ws{CMys3m#Xj(Qc*&G(>*Z}E2m5$hie&WjetsY1ChrqEcQ(Llc>ujzyxu4%
z+~yf6=0C)HIRNh7;q9lT$}n%5CUS(giB9<5<vl`~>``9pWnhl+)_TFSao)E9Xx-!K
zY0*8wbNLrjaG&Qwx7rl1WE?2dJf0VLGrXUv+U@}_iN2pT%UkLO=sBK)D~Kci9a^n9
z@t>!_gfo9s0rma-ZV%|W@YPP}bmiC2!U;Ei?JZ!s^CfO@{s8~sec*ZU*BytXC;#j#
zAU^!BH^YfT{IPj((2u`n1;%%n&u|3KpZ_my=K}c6gRmFK-&zUDV7|vKNQUskDV!3@
zALIc#jDK|vc;Wm~N?S$nw<|y*`5_d}jN(uB;fjprf4&hYG5idQ#m4gY%mXiuzcC45
z@%&%5LOp@Mb|b7O^0&^y>m+^#t*?*q$Fm@r%>R>01ylHU--SXdzxQ#V9OrA*ASd~4
z^ngg?7yF}iivPzBpq%Ds1p+gjKSMjBGyI`WV4me02jIjx{?-bBW%3^`he#IxISSNe
z^V`PI%Hh99`RVignk684eCBn`Sw5dZb!!FuO?3RTke{>(o)z(zx`0>A57fd!IlpQx
zX5u2h*9E)^{(MSoUgBp`K%<hsZ3%eQ{I4n8P{X%V8E7p(mJSxz^J_IwZ{QEr!$Ko}
z!7O-9{A}7~HS<5Z0=+Bzb_#A@<!95zy_NsPmq5A35BUhZ4!)}uL+Rvirmx>$=eJRW
zu8S`(hQbYgz=u%i=DWK?vX}pU5+wWh4R6C<KmW~};N9du*9#{G_*t}czr}B802$<e
zMi;|v{!_of&=6lh38xW$K?^YN@^7^PWt4w}wn<}r#t(oV=Zky6yT^B=ea<95gOXVH
z`NNbVoZ>(88APV}o-%aK@ONy-^vv<!Y=fkuVBY_4UIphV!s9GRRKWTDg8LMQb`d-s
z4C`)!zutqSyI}S-$N_=+J|sN^D=8@BDcGI`NpHcDVMzK2s)}L3SI{7XgNFob${^w=
z_`?ixSTHgNb$`JgN{j^vin}2aB#=;~CRkvhAW4YeTiW%63d(2$7bcKBht3E=cqkMi
z1zcLfMG4l#fgBYaqOeblK-i0Ui4_DK!DPh=gxg^~UeGoOlmx-*&%jF(T%q^oF~Qst
z*h?0Ka?qI~h)RS=s-Soi^o|Rh=#hR>FhVc4G{M&dc1ob91>|XgM>EEkF6eAU>#U&A
z8B=~v;PpLFG6ik#VRo|wzmQ0_;J^2wo+J2+%;pN7J_-lV3yRKy<Oxos!|Qy3-wb#K
zg6&Vhr9#0M6nQQZETTn5v7rALpi2a86);pP==c`AGC__G7A^>eT7hy=plOBI6@p*s
z*SsY7{!92-DfpIl$yI{o^+2f>q-B6tBX}ef>a~JwA;9Vcoe#tMWkE>+tk(;=C`HjA
zsNVw2M!^+YD>eysQZlMppxldAi$FoUmn(uQ+H74Ftoarwt%4L8thWhVegJ6~sOBKj
zA!wxMM5o{wB`>cFURVuYmmrVQB{u}3#W2(@2yKJ)9>Lsp@OlN+6gKD+tQAAOUvPaf
z$W6ibR17sB_>oc#w*<0dP#6?EG=YKL7Hp!6eMqqCb&xxPS7-?^EO?a?ad!nX4<X1k
zDww4A%9x<d0N#XP4{fL>1-BY8A@>DSIUrL4Z+fpx3j*kwJR@+j!0QKsuXcksE9j;G
z^qk;n9h`6!UZk>pCt;i!)}4i$&Ol+mFpQjV5gzh~q^t0^<>+)1GN{(UUD!*P@B!g#
zk>Gg<lir1Ap2FGtm;x_h%44u_Q24$IEpK6W9rS#J1!I8r72YvJ?~suF4HW!@*<zSI
zEacJx#9#QD33>s-k50hrK%wJ3w2lacy>KE(_!|B0!NMXsj}Rh!^E6taLMauOg$b9?
z-*AQt;}n>|2;to&fQ}T}4nQPIsCpRoqJ@tx0ErbYqE~X9@Dv3b<Aud<!ubT@Qi=s7
z3fHX$N|JE(Wk?<q_I?ABEDTx->nXyB3ABz29qB=KLijO-zfTGm)BYh{I6o3*GlX}3
zgfC}=d6cI-D;#<pex4KlxC!<$g}N&6vV;oS)MpFpjsPr2Sey%cxk58t8s~*Ee1PQ%
zE%ZHsd?9Zycm+b~3GfPqS@c9H5)LylOU1&-{g5mXx^4t16;@q`g)(6eEt@U~=bnXn
zxiG2~4qg;K8wOG#l+Qu(lJF(E_$q}3Wx%WwdNe?xS}09}XEnlNs?n_#K28Pqb;7rw
zg2-i|!xpsag<EOr8iWGMMK%gg(W10Tc+?xDS-72c`YpovE*QEZw5<i$Rbf>!TCKvf
zj_{>T*kr+=+l5xTlCKH9=Ru@HxSBT7ox)Hic-MvBtp`e%@GCkFeM5M09z5$7swg_r
zBW!vBBE3RHnQ#LMAF@KSU${COt((HPVll7*;ZvVN;g)dWCy*QzHW`6(Tey#oiVX=*
z(u?7aF!UqX8y3FzI66m!fgNbw71q*<WmK3`1h6roXbSF*3r(v)?g^LC?rcK%$vW7Z
z5~fl)%d~KqRsu7^ua1K}z%>Z4Sz**iurMcde;=5Rq7AX=bP_#D30P;*_}g%Bzvz9+
z5W9#*=qcqYS~L$WH&Np@c<nAa=nTmNqW>t-=ph=RYr<3X>yv1CiE4YHa8R^N4QOxC
z3v{9Qh}d+U`HJ#?fD?yA3I87=6)g>f*~6l}^t|>Lz2|~41c)*cFup)h3nep-h)ncC
z2@<u_nmt&w;AxB~M8u=otx(Yy6e5ifJx^sY(IPhvI**Fh(<(Mb<XsNvSkVAIL*hhD
z+u>5Ys3im>L3ETJd5NL{ik>Hl7LUThG12j-pq?y}?E^^>>6magRdk*1+vB2VbK&&~
zQQ<4_^Q5R<1Cl0c>V<_<qD#||JS|eQAd)Wns2UDth|HA6JtJzgLgcI{=6Q6U6D8Ag
zK2zjP6^dD+e{aBSw&*|lvSp4acRdtxMchHSbYAoy#ZB`>*WQL+z9_aGodu%JbQYsf
zw1iH27Kvs~0Hs*8_9}QKA`KUvrJ}<vz$_EF)06#z=)14rXSt|<Jwz^wcE1Pp3Xy&a
zPFxbr(KfJB6hVd1RibK2Q&)@1vN6duqDNUEwW0&x!LvHip1<MQWzlgbDAbFxDG$^j
z>Z6EmqiB$Bizd;Zw5)FyWq%937SYaU!Mh^*^CZ--iq=pGY^x}43wWKPXJ3H5F421w
zJh~w&j0CS+<VrVCk4Q)-9(qNeJq!zdB7a%|_KQwRFtD4VmmdWg5S<W1a#*yw5boX;
zt)y#yRFpjig)!0Zxlo@FX^+Cfr06dS`ra3@=nFwpA_iHX7EO9UWJV;Qiopk>(pd0j
zMRi+1=0xMPzjYK3(}XyQy<})Pi<2o7v0wbd`%rKZuc8wVuHr9C;Dnnvxf8@)Y@p@q
z0r64VqkD)mXj9=S-bAO&y~H!ofIcYBrve>s@t1CZ_7MkC0gJErJE|l(B;HO{+<xNo
zV<3mc@6g5IFK*ch^#JjIz32=S*Zl*OBjQ3zDg}va*-#G_XYwHuf{**-of;~xrh$ct
z^S8pKaIxY9>_v#bdJgK5;;AkeiW2`b0ljGPt3ROgsMyyVBt|UViOyJY!~gFs#0SJ^
z#fy)mVm=eZiVoOI6hH9<I+Mg}MSwmg4%&=iCX3sC0Z9?7--f%X;%}Tm@I|h5aOs5j
zJG!S&iof0nm(s-M5U8IL=Wx+^TKpp|_R_^inqfUdEIJL|88M3i-dXYAm%uwGes~Ic
znc{Eca3V{5rUb2Qv33WhAV)m12Zr**K5~$J@xp(=D-iG71e8MY6wOPKIM^LyFBY$&
z+Sd~C7TP73idX#%UYVGE2xGV)ekc_p<zoL=(0Nfj`zSgq#P@c?iA&<=%@|mv_|b8+
zs>Huj-FCJ3@P}}>Ml5^}lC|PX)T$Fd|0Eo|ES{k)X}x$=1X>N^#cx8PQQSxMSxw@%
z=zH+ZV*g=~7V&)<>|GI8`GI#;JedZRR`EePcF`twoP|ic_>*72yCz=ZfSKqJA8vt2
zr?^W2k?Z11UEp<zlPJ+~Lwqg^_PWLE>21*`KE;4%{o*@h{iZnT8Sn<g1r!OsCHABG
z-9fRGl90E>WmMrdBz|21kvrn|N-z_{;^|tnM#Mq8(Yh;kv_o=K96=Q?W8&6OsE>=c
z>;dndc!(-DC&WqTfifxXeIAnc#cAZ{lz4tEyq*?6^&uo@#H>@md?5aN6i&>F*VA5R
zPF&{%=N%;xRPEy=u^mUJv*ef6XziEWOa`=zr11@axk?nbf#N2q_JR}clFh;BJRq64
z0OBE${0>8&lCP7X;3Zj0A=!hH{=-1=mYAqm!ACN)4lQ4a=sxTnlI)`cZhn%B6skTf
zDWW13e+h>w@d6|(?&DVpl<e9By(5xwI?WO+;ZiOnM6&rySPzx_%mOb=@^%ee3YRR(
z0*R2Er!zQ_k{A<sQ4)1F6rv?rl$AXy`H<!_M$$~X&sd3TK04zhsT2o`m)Iz`lpuML
zY8?_KZ{)+JB+1trh#Zrs)1Z(l`HMcSc3cukQJfQ!&*S0lNy&qi5J{7~xDdQklHrSR
z{<MU-3*$?dJW5qw8Il5e;GUCI`#~>LvNRP#$&&or3dvl_C$w)oFS%R@&+;U#RNtB}
z30{a+fn+g7CkrL+G=oKw?<n3{EV-BqUWr8Z67)(XPgBsMOftC(<bot69z!XYu;^KS
zQIh@!Br7Dh!(jH3<j4R>rKIQv%vMQKX(3-N$u2~zMlwb<F13;q%b-^$iKdt7Wywa0
zOVvvT*28Rr<j62ujgsKsVWCNqOUbWhNfd=8TO=?43a~4ZoBPnZDp^S9`&%WCeFM@a
zx%Lk{YnMDs#U|Gz0@{ppNPeKw{7%Vy4iv6S<Z6&ENk<ScZ%97ffH~`yeEKU$k7U<g
zDD+Cke}j6T<O<~?`z6VI%=JylN*d;X<fZo^c}t?{Lu*jN{28s=k}p%?(vZYw0Tk{?
z*tA_8mK>zBdLxq6k3s#e<kvMA^r$4|4M>hjHu_>F#w7vt(zqva{tkK*l7%~Ac2eSJ
zf!=+|CJO#dN!oV7`DuyG2HuQh{$`*&kQ~iMYgST4`>Hv~gbuzqO1mlFxL@kq3_TaA
z@-&F6^bLyQxJftYAn7jM_5g+sNN>{%%tNZD6pW{I?K#Y~m$aXrX9uN>V$6%T^cTwD
z_(&JeN2jm!Au2*WB#oE>ik~zm44sFiuTe_bUwSkX76POjmI5VEI!@8aBhnY?=v|O>
zfF41?QrCl!43Td0Mk`dxpwLd3R7Hnt!=*uwLN7x43GJsNr7m<+MoH(>Lp)l_q~GYM
zbjSvg7-`Mpz>Jmt<p}F>(n7kO;-x+Vz)X;SOzD|KX&fzFlBD<UL*bY-k&2H~rFRpd
za9qm$4TC-*T}nZ`lhXOL0!))We;6XCq(@f3`e|u4r83i{?X_rSNNbm33eHNuIDpP`
z(sFvsWJ(V(p_e7CqKejR>0j+o&y|ioh0gQRAB&)nC!M9IX}<IuHFyQmP3NFjC=H<a
zQi*gmWdlp4GqiLllU^zX$_43X!Dy9BpVmX+qO@rRNQE?M4ZOZ2-6DXyl~VKf7+94w
zI~wZM(gPpB!5V4GTIkhE-={mEPP%n56fR4@>w|i|)Ttf{4N@s3`WvOIgVAb|+FyWY
z&C-)XsJBS({D#&QY3L)syej>7J-}L}+cu!pCjI#$+-;ZsB7pPPq_2F0&JL;jEKoY7
zlD}c-x-?w?ksH$29|B6ZbYLGypY%!!p!=nr^>E^*^sNf04@h^@&h(aaX(&(zrMD@k
zcw73&O0<TgH>k$!j`a9EC=5&av_Tz_u8oD)ccrIp0&HCRP9{X|Nte|EY(g4AH|(Tz
z^i8PWm*N|MxJjfxIN=AFmhS!mGchAgr5cb2QufEto0WDu!_PTs0o|02vfU#f&NA84
zu(w~<Psu$O*}f;?lB>+T0}5`k51e4ZUG`EiEF6+OMO6`gvJE3ZIV^knXNdUA8t5a4
z0Wv+EfeVy9y%LzgvZpE68X|jd2<oA-Lmq$*les+xy>OXb56K9bdNEp&vJgt&N69Q^
zbVkdPDSdcUR!Q&v7}=o#v|?qqs(=zFyL<we@v={b(3v0$rjTBmte3L!r)1nEP)L_W
zbzvwOvZ`Ovc}A8y3x%_?&)<Vf=VW(Y1j&^B^ED*1WL+-+Gh6mqKgN(FTSft}T-iN$
zh@6-4YvD_t%xg15@@4;05U)UHcovd{vV4lS7RflYnkkn3NPCMC*=h>Amdd720=i7L
z#R(`EWNa#@E|<BH*^9E<R5w~7`_U8Xmt;X%;8n`b`@n3K?D!HuSIcH8V_PG0ei90`
zvZ{N)tdq@u5f(1X(jP#iUgkwl+6I^fuTl0fh5MRhmnl!uEOT51UW-gZTbe7fGgOFj
zRW|-8I$LEQP$>7B%!5{P9kR7l)Y~b0^iS}v%jU&mvbtoCAA)B$Wb!2--7<$#boR)a
zec(&4Z16vH_Q@uFFfaYGops>dl+C9E(17gajUcyVUyq=3P}UO&=-V<U`nbf9?B7h-
zyCbW5621(}$|ylOB75*YT6bl^Z{ornmHp#~&M}#HFVx3n4T;dZC;NzY^Aoat^sUuN
z+1ST$;=Zi=WhhL^o^8fxr)9~{Kw(DKOy7feAWK~g-mHv8TZK8<zb5E8%JG?hEUDy&
z!_ab;i(MeHUoQC%dM@$;N@lpqv#5l`P5v!yUftzW3F!2cS6#;#yyTa<;lx3C*$>e3
zmj9IsJs<fO;gIx|C(^F`ko@7(u;(W~O##!x@&gY+!CxM{4GIDBOB>M{DF0*_dPn5H
zll36E%M-8=ELTyLLWrDez)(WvcZ<LalUKhF5-uO3-#tP;M9Zy6x%oXvM#*Q+p)*>}
z`u`lXe9{+A#K_%01z4<Hn+?4<Ico|E@$%1lFroyx+j*Exl#l<6xlWRwr_)x)<bf3Z
zNtQ491tKZ(9qZ7UDxcd1CyvVt>A`tI?z#*=z)5-NX+WpRpDBm+Q}PyyC7hOX4x=+&
zuA>D{hP;Bdt7qgc6ze)GfBb!5o|Ef81j&?dA4O-D{14h3WXrAex%C|R1}X{2l~?`-
z&(6yWXefDdE1inYmmj16W`X<{J$xyYAE&HWk^Ia{uwE?RO$*%;`DS_>mdZb;gHC1g
z+g6}lkneZ{^HMHfMx_fE<=tl?Ss|C51K1_`V^pwKDX;qfZzaih)2g{v?nWWDdigr4
zKxvRaL*d~@`8iq_G|83gVXs;KWd<-?<bAWScSXMEd!SsE``kgRRsQ#WSZI@rD1g~6
zKXV^5cuk%(0+9~+BlHaElzY;7!|U?Dy@Apt|J5IoH{?l_jqjE(r6@p;-0ORQ^~w*^
zwD!sOybLG$<*H+7-ITj*g~EXR7Yd5rlDp0a8I*554hL_`XK5KTB=@X>6L;jHhhT45
zzK91yBk~tkLFBId`6b|u%3q|E>zI6AD-4axpKM3#o;;4C(i8IM2Y@*#7gCV<zI^fn
z@TTP2#jrjtUw#21GxAd_fbu{trEt-#T+t1MIe8~#O&k@=AA+QlB7mx~ofW@Q#M)I6
z@)A6AQ#iZ};;#7ldng=G#9jl>L-BbEh^JzbflhD5)ftHRC|+}d*S-q-G<b&<x>dmR
zSGdr@;sAx45%U?Sh&ltwBZ~T`AQ_}E=Ytoj_>&g8VT$J$ffuf5?Ez+l;v~gNA{FCQ
zSP-Rn{v9YpD_Zj)c~o&#2gw-4OY{(rRk+hl8K-!b0tNAk*VqtAP~_8sE>ZDy6Iw}%
z0UJ<`Dc;aQGFkDL1cOddyhusNR7D(}V>qt3L|;oep{S#q>!f0+4A5x`pDDCXDGsg#
z*lEQYH;{D23+JJip)hU)Iio0Bi3{wk!bHE{IYl46H!~Gw6nn~2ocJCh*@{+LrsXJv
z6a~*!?4>o|dBq3xip*0Se*vBOinm9hP@s5z5~NVECLW|n(IEjTR{TTHkP^iudXSYW
z#*U)1Oz~ScJiDOqoknN5;tP73UR3zdE2Kj4h8pCOqKBTCl?pjUjj9wqbx^2Q%%>Zn
zM#1but5&gl2Bc2Gr{bN<icijhSFbp{7Zw^6AJP)1QNgUlz?u~AB%`xgG5r7{EsEKz
z;9XJNr?~J{h3ieIw<<(ku-B$w(EZ-7xaS40I~5L8e|BBr_Z%GTQbc_Qy&DQgiZypD
zVh`hT>rvcqhkCE#<0ml_eTx0`JM=5A5cEw2yA3D<ik(zTd`t1%PACj2mV5xP+lu6!
z02@*)KMk-uijHJ-4l6{j0Bl6@kOscoRlHdRGOD=$I-tiC2TIWzS3FC#2lo`8JqNuB
zh0`a{n^a8GYWu#TIvQk35k%q4X~k!BQesANZUB-G6m@i&&MFi~!JAVI(n`lsdGay1
z<fPoS816bN=Usxxe&swWP<2r@(M-51U8i8yO{q2k%w0Kh8(;^N$LS*SP>y^J1yAJ`
z`t*vIGU{FM4l1P-4)a#75x|g-vN{$Pe3d1SL*$ThX*b;UQ%1+2byzvD42Jxb4^dzu
zK*^$5SD><b7M(|w!UjkNDHmVE3<fJ-`w_l`DEorpOQ>>c5qM$BbowwuxN>ekL?V=H
z*P|7w%pE~1O1XdoU!s*KYteaB`PW$}#K0_2VwL+StCyhsonjY>%AXfPGD&%h*7_;R
z(hTrYl|9dZ99M3mCtsSfo?hjrl<!hZ;IuN6qP^+LU9_3ZP=>TY?~GF03FkAFuRR2k
zrTl&?NVam#bFi1ATt#dBT;+{*7}$AbAT9RtluuC}FJHNslKBP7FnXvKDnC`gmm;NF
z1$T>;jZ{`!qD-QEPO0)A+RBzGKc+(_7nFPo<(4a}sbb=yay?zw70UigP`{)Mr{c0o
zrQiVURVhEG6h*ai`NQa}fd!bYRqnlmvDYb=-GJH4%1d-Wv0ka!0Y4j*?hW8ID%+{l
zx=Hyug>RabrN4vMqHLK$=M|;y8z@{=ZtnrFRk?}QQf<l=1<-3({<j^xYs#B@K{}Kl
z&?VKW)W?H&L+O$M=ew0}(%Y~{x%(|(_9`Ehg7hh)65wFJaxv|JZYnPu&^e$iC6{g~
zhbg%?sC1!+)omq{zVI}p^mqo)ca*<T1?{l1sS2KrD7VJI>|JH^-!L?)bm2g9Oc_AQ
zjB(}6QSk05ed$R%p&W7q=A?4i4E6iU^iW7nDHjxhH?6$07xOuzJpCxh1Lea~K+h@%
zUWM0ADjg+tomH2qv~<5J{A)nFsSeR$J9pI-3z!E~y)jVmP_aG%w5RHJF?e1oF~zJ7
zs_e9k@m9rbfryW4lJ+^is?kT_?jhA1l)&>-ZG0WA!>X-&@Duy14$`5B0M)%uVJJ|w
zxf|+7RJw3<2B{wQ1_@UA(qlVBmA3^XRQ2!!*o#mNQ0_BQ#Rvgrl<E(<7@}44Xd`x1
zl|TW^7}fPxF}_%pWjhq&RD*OVH(q7Vhe(1d`E86ZQMI)Xz9gx3lmq3Ms^?>LCaYF_
z4D}S%vk@SvDg&)JkE>R!hsX)lS&I3eRMk8J>uD;s3J#u9U8K0pY1IIgo}{Zb(<(hf
zmFxtOGb*RE&^xPYp*X`iRr^BtlBp^>fzB+|%TzC%ts0_ud5-Fx?a<3r{rV)#o>vve
zK_pN00)0X{UsXXHfCAN@6hSUj-Hk$Lkt&@Y7saafe}Ph>nonV-QWcv{ww0+^I{0!y
zb*ciba+ReCU>8-4K0sHfJS^Z<sXQr8TdNu>0cM@**>!O6vTBf?`t>UH4(K(g=Br?#
zQ6>5nolUCXgHUKzb-#tq7S**0czs3nBn!MYRVLkP?W!L)Vtm(BCQ6TXs9IK{vs0y^
z_{4QpCnZa}R00Qx+)$mTR9Lrab{fA*kLp1<Cb?gAmEJ%%RR?GZH=uf*e&X9IE|sqh
zsaA%;`W@9#dZOG_6;QZ+RHc0lWK8wjW{6CvekuXxq{?eCQ0}W9eE<h%RD<Q<Jy5NA
z3X-#`ihp3pN&WcuKyg+}qu|Sa_4Of0x~W5H-RiF924H#)sNal3%S(NaVpa#$O_PxH
zR_84S${}?>tsMQ-n^wZ!VfBJVkPK8m{01bCsGoTQ&_U`ddc=mRC!C-crcRuX_hz{I
zCn`gWQs1jZXS8~jE}Nt382WlioVtuw)bZ*X%0VZnpQWJaG4+uFw35{Wzk;NwrBp$C
zLjA#`n2D3>tMpZgH1#@PxRkCIyTPRl^_TSYKBKN!3x!Pe01Y}z{p{x;+3I_f&^xbw
z^#AwTYB|+1=BsPYz?UL*#2G*rtIuwPgC*+iw7k2ZUP$rsa`lf<@a3Y~Ou4K|wVtZ?
z8`XXEI%`r3>B-)#4yKJti~3vIu3k~sP$alb&DFqcyL$ag5V@ufi-AIix-SJNo$93w
zSii20xdqatK0y(e8)_4+8M@Vn3ZUMj{^0<u_o`p@L90*QB7*u&wNnFH1L~?@AbCq&
zD}vcUwbw3S-d10Zz@YD_U!g*&VfAJz#u!n*To35GY5{F6N7Z#ya5$#^_5<imsQ>y6
zWKz9t8kqOhHrhzfsNX&Z$p`Aj-LN;Sc6bwGaMWz3RgjZr6|Fy=H5Yb5VZUZ2U4t%~
zJz~0gG-v5Nkh^Ar>>bejNaOR+6cCuFW&wq~yfjzlp><I6zYw_Vt(kiV>OPu?eZch9
zI3$A{(tN;#6MmY%K8MI*&D6Ir<ga<i0KEVWJ{f@POcQVqo*mK1@?bVd!`=ZBtcj0=
zdWh!N_rVL*jJrZILX%0?OQdE)7pzBVPSbiRMswtGh{S4wmP0R26aNMLOw`O#$#jyY
z?>KnJG&@`Yma55n1il>Cyz>bLc0$AY7AU7QD}_KgtqDyBFI^Kv*|M{mPwqnRoMsyz
zD4Cl7=%JINxlIL?xtf_cD4f?U?1o5zW(Nh_3N_zYF!M#46h{oKRI@r2&}ABTy5BEo
z_I5$CT=V%YIB`+ax(J;Wn$P})pO-Xm?*dq*=6AZat2AF9gQ058*!vKv(YVw1QED}t
zOmO0|MopXEdQEsNoM_NwQHH8flk+-Alja)5Mw>N@e}G<##>W?uS2YJx;6$rtls?bc
zrupC}IMJ>-Ou3M2ns+;)*P+Rz{aB~wNlHRq*GQP~rAwnJgM}NKH}6BCTN6&B?a@4Q
z7^GiQLWSiwHM=daFrYc@fI;8ZbnSrIA<a&D>EF?8o(~Jdn#vylJ)+Tm1aepN92FUj
zYOEhXWK2`A5EjNY@2b#wPm}Z}UAvk|CSALl45|^luUWneBbw5Dy%()%jfRq?Ga3;c
zK7F8Z%ZKx`nxR0DIgRog`01!k+J-SWX`==~oVAtoT-vXdt_06TYoQ&3s}^B)T-Vwy
zE5LKtHa`c<1KO88V8}zO*#${Y?F0{!UfPGEfpSpWLQZ&V$0`5rqg_SsF<<Ra1bBzE
zm2L3MPkZoxAcwVO_kroJ?dXO`fOen=3W3_cJ_R|VeK;8?LE5(|VHm7^m69MK+Na;a
zEQM+{MKBwteZ&_i;o2~&+KJFAlQ1ulS{F*7M`^w2hK<&K^#5N4(H`Ps3^Cfz{s3mI
zwtzOTaoQf**v4z$J%d()c4jx6NYr|K4hu=zF^ak$(<YlS<;mLBJ76zGyO6dmsoGV;
z=sd0s-vIR!+PpkKpVZb;1z(!>`6nTHO4~w(S*Nur^wLPzzDfJ446QO6ymQ(*dZA=$
zy?sHlw4bH}C0kog<!d?Gpb9vjtJRaA=e2mn;oYz0(26Wy+a<t=3bfbiAX%toQ;xkz
zyQT`5#oA<w`juz{7eJ&`YolU}GVRt8bY9TTQK?e7b}z+yE@}tp9A<^~*r(9Dq>ZG9
zf2Fos0m&-u*XbbDS~ogIU88ON36iziY03@OX;+6p;j;EJ{fzb6O==9RL7PaMtw!zS
zb#yjqBWXw5tSz38R*Tk=u8Aw!8k(i6+QQEP)~b!6*nOLJ#qTiGu5~*ImpZj>`yg^%
zyO^%zF6|q1fc=KnG6RurE&DVq^k}su=<L-7Q|_ft``}YZ_G{x`1MjAGXg?$ew7ZU@
z^Op9pZ_zoZ-Sr<P^0wCNVK_0Qjcdk)+|f=`@?=;W{u!JY(TXA=c~^V$J9s^+eL(rm
zG3{V6#y+l13V>(#w0*SFnb3Ye46~EkY^uz;uiZci(J8G#4l=F%Vh;?>Xm|byy$9Mf
z88BzHt)GL;X@$8Ean$XmAI?d4FC4x&>ndp{yk9rZ1_c*g@Uu{N)or2j1UFsKIL6?v
zE4l%f4(O_A73-mErAL>iPW>~~y>wTbpngzywg?K|y0}yr^3g?6k)N+_2^XD*bd2vX
zT0h+qN;e<Ybv}ZYzs~a;j3_|I&xA;zu3$4TkLYX)s0Zl=X-6BZb2|+`Lv%8#{R!3m
zuoDi3={!$CBwSY#1Pc+mCBFkKQuh}Zttj2$y^xI7{Y3TGM|Eb(aKz|xRcOWPT9gop
z)7@PH60h?Lg@puN4pojN>Rwt2lB}!H!$OK~w-6RmbsOpH_a}9{r5JRYZtcf#_mu9l
z8IVlf!W@X?=$2EcGgtQ}?IzCaYU$$ydAcoY(3!8RAYOqk=PO_q>cS~5T%@a_^P<JN
ziB4da>fWS+wKAP^EgZa{3rd4}xi0q^bY9f;QV_jDcbN{ERO-4GU?^3(ryMc9YTc=8
zuwJ8U8v(CY7eITbI$fg^$YovHW_Vq%EAqoI8+0!nL}#OJkOvD*y0AbfH0!ogCc8zq
z|1H?NqI=;TfL+yXi3G1zw}5WEHr-qFqqgftdeFM2^QO|a4qZktTAjMG^T52W+i@Na
zcIg7>N4=q|qzrhsPM;1#JvvJPoaogx9YCv3mlOlNe%&IZG#|UE+ap11P?t&x(c8M4
zCm}hc3%(9=M^}9go(=0hy#TNg-7;En-qp2Go@-S18U+K!bln_uj_U?%(Roj2C(kBy
z&%OqiCUu84L;b$4^g0GMrSsef-n8z2Z=iEVS9k}V4|L8!Ff^;nJp?kR3)}*pqrRKM
zKKu3GQToC~KeGoGT=gH*TiZ?l(<|V)>tCQO)B*iHdU<>3S1*L5r+ywAv*e{u`W%K1
z>Tgkk#9RO4QV<{gmt5%i>VKm<{E&X{BozGgir1ljSifgJ6#VsHT!mzSzLiRK1N9%$
zPXCDBMz=+fKKm!=1?%6XBZ47%8*N5H_3bBt8Kz%BL9TFpRv6SH^gAgAAFYq461Agx
zBYm|rMz6RHuz0=iK9B_c6LcaVQD1WbzjU(x&MAnb=vyhPo~r-&HlR=Hf9ybKn%;{J
z6r9pObqo$>=%utWKBNDg3WCn++n<1iO#Nf8fMn^tmP0*Te^CJoIr<XX4&>^8_y#C>
z`VT(>FJHfh4kQ=oqp9AsNWX^yD8>5qn}AuO4|)a)rTTSL+)}15rJt%?pWlPlMg4~V
z;BJMU69u!C`q5v}s?xvz74)k0+h~nhqaV`%vsOPrIljyKW8;vl*BdCc*r5NN(xZ)f
zeGXbp`d$_kn)UOf=)9_DQ9Vkl-sfL<)~4Tn8zSxcSu%S~{~B#nI`lu$zN1sGD#veo
zT_3y*<LlCg)8b@6FQaAJEq&t+kU_m|4k)+vHz?aOq&L&fdstsX$*2*1#d5Un>hmvP
zm}C0>V^E*a2YP}xspo$Sh5PzeiXczv2W!Ba*1uK&-i*GPcI6NB=bnP~S-mgSc+Tl_
zsB+WM&_UOklfmO%C^#F$HniLf|Ilm6-O#B-=K;e6T_GL@9tE8|4N@u;_A(SvF7lwk
z_7HsWHe^#2+{f@zI-K`6q|;Xy0t^dY#V`X6cV+>0#PHZ06oL#@!@vwS+@eDL5W_aw
zKZF{ZC@&gjU}%97Z78J`%TdGLO&~Fb{Bn#T*6<o1B+kHW1a!RNce-T~3{zdOkZ3Ue
z2$E!2){B81H%Ob|?g_(Y$_kw{y!i&~r5V!Xuzt$mK~dY&hK^$pNjGq+pqF7-J_yV+
zh94KfUZx>nF`%;yVfEl;8~%45yd1+LJfP$nM!p5gdBZ&V(~CUATYiwtH|(NP-2wx@
z7Yc=jCF_AwWZ3W)c*TZ4X3$w~SWPSAi-w0N0b61CC>NexGCcYsMq6okoVHh0hA?^{
zRU0@|SWsj5i4Gmt8a`+RSfgQ@PANATGH#%=*)U3hvlhc=k7Be}44*%Sz4lduX&id3
zhQ(c&);7b|E3nXR5K`8w%dnaDV>b-TX-U;>$fIvB_86`<g7g}=bj|k}CaBP@-|)s(
zkedc0WxxjvuRjIMJBB~0bJ*ZcDajE-@HuqeHSDCg+o(Y|0k6jlgLFWD+|Z+d<UK<I
zRfkO&F44EArVMe<pfzpyAP+9h7?d0+JTSD=#&6ajqBz)`K}$(9N8@q|L^>HKXxZd!
ze1=kQ`;EU?0qtT8cLZ@Y)}Mlir}4iew7iTV191MJv7P}*Z{t~t7Wx<$O~9V7v1>D?
z=aBJqJlyp&_6=bs4jb#4uoq+u$bw$5@ypYY3^Bfx3b0UPX#^C)j6YG0b+~a0g_$CZ
zKD6?WG)io+5M^8-!5HF<U*CX2ym230bqU6Gbk!vq9dsZ`M%8twA2UXO50Y#gx(k#P
z<Ko{yQjI+m06S$Ir<3xhjSphsZo2W)hr!D*S_T1q#;8~Xk+a61C@^u(INt=6Ok=PY
zptFqq6qwI7evkw8^TzM*qLpWC`5nA`<8$;s6$Qq$H27I)d@%%IMaGCySSU80_z<MT
zxVIdmEj6B}g61;gSOuUj7}r~1uhN*l1D#dIX8H(CwXxxOsMi>$x5H4a@c}I)>Wp_O
zaeLYL`%YM>H%^xUv&A?{Z@eqU0WXMLHE#G7D6Pf~4v=g!a%})>H?~l%-!-F(mSP=7
zE@e2njms%K++!?z8>H8`lFnrJ85gbr={H`<2IfuUw#^^|#@ceI-!gt80U0*NQq{+Z
zv74^)yT+g=;QXkumr7vAjDs4O9XD3Fz=?atb+l%fFy5!f#gs9R9@NuD^;aM>#xaUr
zJTT@`yl&Q5q6NyFv7NSv?xyr3uyDXM?<CYcOda#U^EA!4!k(9@y%*{SO_IML;%$1$
z6J~u(PtnO|U(>rOFm%YYl>*6rCdLfF4x60fFj{}p4cc%7n0&jT7ihXfufZTwZ89)}
zO?wXkCB$^;KS+j}th=BdW@@F2J;F4Po~@Cl3@Ve1GDXs7ZjPFwD}WMX%AiS(HN8h6
z**H@fZE)gEZOcHCOwI2?@0dwXM}Lw{o%EVdF-`6SW~%7|!YYp)H+@gbv=gQ$X(fKr
zw27>znf`klV>oR(PpiXp)3_^0hN=Bs=$$du(@y`aY2!yA=S&k*7(<rn<zFF^ZCXlE
z#vIeH{(#OkP11qn^QI^vrXbI>kZR=fO^(;#Qi17B%GDK`vg!O-k!cB)85ElusNTE8
zWXXkksp%)WlFLki^su^MveR+5a#I3@PcND_oPm0UX&*)1FPXw`L8Q_&TLO_PlmA*c
zUv28z46qv0K?<AKno{ZIU2k%xyi<c|KV@(lO&L_!(`1UFn&4*BS0muHn8uf53|CD{
zs=;eDJv4}6wwcz>fwY@`eFyfgndZ^vuEX?!Gcd24>S)u{Wpa5RA~#IdezbZ_|AYgq
z*VJ!BXP@b-Wcbo=${PjrP1E^I@CHmFei*|o(-r#g;BAxY1@MMUT{ke4JEplfSRXch
zOpl8Z(?|b8WYn}i4=7`%k>w!crtD;h+%v6x8TKYjD~~{Z(v<TireNAs{wefkOvnF*
z-UHLTSxC;BHq+tLIn!Yus5_dMuR+VnJV?d4&SpQVGv04b9D;Qh^9p*$xth%h;JKNT
zu7T%nUhxVP4w(1Q%zK!(Qkc-wy!8w&J}-0K3bYQIKM`PFyv>Woq32^>&;c-CGhYgF
z$ozIR%=(!_zXCaIUilqR{LR^Ja5upG`UETlnky;9cEmg$4a^|3?h|wdn{)p^MQHAw
z19Yf)aV1EYxnw>h!_BAZz-NT{_pd-A&Cec$UX(fi{}-(0WF{u$sCjV|EX0^MsL+Zv
z|4c8UICJwpwBpS+1^i4f&!ez%qS=E^b0(Y1UWbJg^Xs%NOEu@xVYK7sKpa4N?1cF-
zid~#EFQfcQnt7WPLpf#64gkt&^L<*$rJE-f0y@KdRt3p3=4U6tJ8S;tGKO-_yoCbg
znPz1-T3P1g|1f9S=8iFd<(O+&u$OCgx(Sr?=6OGYmuG&G;*t60XxbPRm{-#eS7^Sz
z2^NaXswEI9HtUu^q{N&?k%dxo)Nx3bnXey5=LPdB6`;$_m+4~x7tNKllB+Pw>G^rd
zET)HerFlMmQmD$j@e^3DHUIE6NS)bl9h|>x#>I+T#w>gqq`~~R7LtwTVJb6kGG9yp
zO0&6~ez+F%O%X({m=hjB=T-CgQp{(o*)tZrHuHL_k!Uw>py&KGbHE6^?l4<cVJMyE
zQF_r{Hz$4#^)B;8cPQL2+v&&YHYdcx>mKtcrNVm6dme^lpV_4xya97gCR(@5d@6hy
zG@t(pBDc-6`++%R-g6L644c^usE?SJJc7=<W)&Tx88shY0QE6*^eA}a=7nDXWy1W*
z0z76W%{i1WzHdG<i7A*ew^4v$+Wf>H=$tV>_ZckAnqP_rZ_X?gVSJ93#{xl|Eq_y7
zW51<@g_euuJ6cM+TJq_LnVV%t6x0t`)>MIbSQb{mT~CXNLMC385URyFX!&q0h_|IV
z1M0q((M8ZZWO;Wp?D<(vJde)9mdK}};BP6XD=WalH)DK9EbG@mGRSh_Iba4`mQo!{
zxMe?W7$YoeCFqQ_@XkOX%Hm3)xo8W6PD8|48far1YZ3JVI?m!$39xv}ZCX7gSl*x#
z!$gZ|Kh%>f0(u`MTk_~7oMO3f5h$sa*n3bvZdvp+cqc6J(NIsbG%SJoDN8vm5>H$D
zsfIP(GG&26hQ;qEOvo9_H0{yPT2`tdl4aQz1k7y9x0Ha*v238QYp%ud3+SD<?4^uD
zzGXEZLn*Laqhk<-mgDr>7Fm8;1$)JoRthhcSQr)Hm09BG7QJB6((PMrX+MkBMa%5R
zuvcOEdNu4_vTXkq>Q$CJx*w`75j)YUu}Iy~s<Z6lLgccgeLm*1-ZDImfi+mJ%Aww9
zDV;&9+0tAE(qegb8j@EmF+{FfcGDiO)#5@aiZ;t~1AMt=xpf859Tvte@H#EO(>wLL
zMNa#NE=vp>k~b{tDIVEl>7X=3uO;hCfc07YDByO>QpbSapvCYo#&_HDCmlK-vK)FI
zGkC`ma1EU!7C`~P?pofVGNw_>&L2R=EQ5YP8MiFkkJdfQk9824u-v8dB=;>HYcR|y
z3;#2CHf<Sr2V}<bxeq!YSRQ0SVb1d8X1L^Nt!jgVPS(FSzzJvTr!S+m-zqtVvAb9c
z^>EPDT1y9d4p^tD&cnl67YGqg>o>Hl@Ului0Xb-WY6uG6*55`U;$zLHT!F9kwU;r5
zL)N2(;Q3jb>fqU7>*w@1^tU$L1ayGawE~iXR?$JUj#&3n>>|h-KMT)-t$jD)Qiyfn
zBXovZx&0VznDwRQuorHXcAynu<vU_TkyiCbun=XPqjW;Fbs?2l9JQu+ffr-Vq8Dwf
zbx#dQoHeKe(DBwON}wlLFE>Ln(YoqwSV*#_{sM(#*8Y|7Gue7_9h^_Gy3?`kRBKfL
zppRQ0p_TXvt1~SfPFlO`FqAYaXBv8^tbdB3aN1h!4a{`wk5nI$VSQZ+uya;TI21Ci
zFPR{jWo1(VZm#uxN{O7eZlm8X&-&CjT7}lIddx(TwTLRKimh9w;B}ex0KG6TSa0_L
zv)md_^)HvK%a_4Wr8VL!Sg5joK}*|OYt5%<)meRihWcgexr>;WMr%e2P@1f#T+nK^
zCd;9I)w=r-L|U!l6(DWaf7U{z!|IU+^-k;ZO#r)Y-9VwTE^9F5Y;IV4o`=0|YY_*2
z_E@86^V)0O@E!)%XYINSlzwZ24;;K{-BJjVTUPTiv<9t9)}nRW+DuWgA?wbc@dMnk
zn&>q#V$IzJy}Q<R&%@BDb^JMCj#&pb0dw5?9L_mDcF)?h8@vhYQ9i&XtyPqNzi(|m
z1Cc4~6*ssvZSA-Q%o*#)@50an>q$z_%vz_aAvtFa-3Okdt<VM5ootOPfH~XV?t_S{
zEj$YL+-#RAtmSTdvl$i+*g~fO?P2q9K&PkeyT2jnWh*X#<U!jrE&%hf-Ju|*uk8_v
zgB`LR(8G|QZSFbn4%<X@`}*7VQVu1+#%~4*w4I?FJ=pfK4(^879BKU$YJ0yQ3K6#1
z1>i;6wo-*~luefh5^bA{2k)qDGhHFEwz36i#o2aHTq@qC^F}MdcI#X45^V`$IFV!<
zN<{0Jt?V0&FWI(=g2gGeUV3b&+Md1#g)_DudNiN4#d?8v&X%$botZY}7)G0A`;!Zl
zY}-DnEY7j*eg=keZC<ovIB!dT46Qude%i0(+m`(VQefK^2b4nF+Z3WHvbj+0R<Vsq
zkJu8M-wVJjwY}g8>t(iiTOe}5wrCaf%5DEqHQ`0uKNIk!!uItk=v}fcy9*1IwhMQm
zP-PQ*kIrh_u5)m(#>Su`qgvaa{phT-6_!Ervh7={*=w}<(~+7c+sRn?*=(CPht8|E
zYZUruwRy%sq0RQc8g#bXQYjyI&Gtey6gq61=@dnmO-prFH*Alr#Gt!v)wF2qvHkfN
z)O&3Yoq>9vO-VD+Z~KWh#5Zj#=xenDw%5PJ_-@&H={_2?y-T%5w{7kM{BT3IC`v-!
zvAsPEd&4#z#Y0AH-n0q5Ycmt(sO^FW%#PVM7DHs*R#FdN?%Avtz?-mbqAcR1?EtOk
z@7tVi0CURL`Y3qQwk2C&XvS7dX}||I=f^RySsV9rkU5+04$Qox-FG|Go$R|C;I*?|
zO>u_(b{joZUF_Whu;*&8r+duJzOo8t-R+(_bRMv;ro5Vm-H!*ep7x#Hu;68{@<Hc8
z`~Rqx-`hTqRx>{KRcqjjpM3{Ki4WU3+aTg^pHH=00rs88;Y6VQNm>aUvDg0r=pg&_
z1Ly_YU-SbBv9taG3AO8};w8*}Jr3@M+r?C26JgKG058%WOl!<2`!cG@h_*{lz}=(v
zWAtW@u{%@MK&<`D6<CO~=O+Lq-k!P|>WTKB=~He=_CxfXKW4wv36W&G;veXx*dv|c
z;BouOCt&Y{eNzJzPTGfQbAH+$LbW65_C@sE&9L7Lf%+M{i!)kh?LRug-Z{I9(qx(T
z^|TquvcJC-nA!GssJ=DFe!~uhT>BzA$$H+thT>p(cITHNnQzZp2YUr}JG}!6?M8~C
z7TLd}vZ-SGM!G3W?0Jb8U#Y#l7QU3($NfPr*q@=-e7XG#+H764CzU|5!fyNvl9%ky
zC&HIX`&P<!R@v9oz(TcsT@cLH*pq1|Rcn`eL!{3B-VhWn+c(m}y59aCh2k6Ruh4%B
zG}_OGqSazAp>WC-dzu82SM7;*_}OYNszqm;J*Ehx-TvVOB(K@`eSx{|ut%&#XQ#b1
zABL{m4O39)vZvB2sM{X$A_mrDKSn9+UVB#pctiH}g&=qArzi_GY`;vAlM#DrAzF9s
zzpQ}SQTz5ph>Y1iC=NDmx7Pyfo_&@JGGT9_hvR*FizD3#c9jlhr|qwm!orNbk#<WD
z>?0H)nzcW@4A67-e>>6X<Zxvjd~tTDq{q{KhalQCxj8iT!H~PdoiEUNz~Q@VXn8oS
ze;F-Lht*aPFNeoF;n_h4^+#xVJ1nIO#mB*eeg|KNPzreaIYd*%?qP@BCm`bQFx-JL
z1US@C@+;7xqX=e?ICy6RCCDN4U04Wl2+oFjs6#VdyI~HURDuxhknj_{j&R^<Arj@_
zOo7j6ho9=89^)XSRadOT)d<XdoI^8J9Va@ZD4?F?ka`=uV-D|9DB`rk<`@`CckoYu
zUWUW>ufd5k4zE&z<gCN_7hv|B!~f`Mn(gpV?Ei6e9bj2k-#>XphQJHF11&2{%choP
zKP^)mrZ&{ltW3@1-FvE(DNEVNa3Mp6$Pkq+8)eB5lp#ZwY!KP9QU9Owf1aL>=iGBX
z=iK{#$GzvC`vq;8wp%FIm1S#e2D@zAf44w0$M%s9vE<r1$^d=KcF8aBciYyLveJ3B
zN9lA)zHQ777!=rUAAs9J+rQZ`xMMqL1A}5)g%vbQY{MUdE44jHY3wrF?FrDVu<fG^
z);-%r^!~eVyEzv@RN5|H53nlRSE&xE+V(UhOlxd!(O$>{+r;g#tF?WPCOmbvFJFML
z-d0AZ3>s{!a?q8BwhG#PY_z>VGmj?QUA+jf*_P1=yB6CYzXWNu-9&4WN4A_8w6)om
zuK`%Q?fqyt>acxC)51<$K|jp9Y*Q1U*=_qHtzmm?3*QBFuPwJ5c73)yYI|&JI1g?8
zw!!qccw*aCgRTtNDya%%(DsXQ2#0JF@<4`dRlfmq#C9JQ){WX8m_s+mY&|JE^3-<g
zQg|P?UH=T+gl$(L+9qu|Jb+EvX1)dCv~8Oa>}G5iC;&EVdrS)tbGBk8?4H^F?*dew
z+dib_zzf?D+B~u69ZpA^Bky-g(VXPv)5`4>Z-yokE<A-RR9t!IDVOKQ<I<YaofpqV
zn+NYk9Sl5qqFM;Oc>7xsi#M;)0kNFsWzmUEA6^%gtNQZX9s<RW*G}&hf8N{gfeYki
zl)!Be&%O)L!MtTZqAi5ylmOu+UKLe?hVq{7M=W7HYx)_(d43k?N(7HN0PZqxnAWh7
zyr;CEdWE-(Zu=<S+IL_c&5NVrh!|eh0T{&cKBN@)RUXe9QOEJdZ=vlPFWm<LUgwQ0
z2X}*as05nvyqOm;Pv9ldq%DzGzZt?L-tGw4CG-A0i2zf0{S_doyx*U}{3fr(9kHbG
zmVOQ{o##gB%nV*6X=d_HoB(td@BRNkvUxuA*v{eoOy69|<u&U-Zt*xjLU@}e{0)7`
z<87e5kbK@@S_c&H{KQZx<PDrfNJYG)4bUv+<r`ykOL(atL#34W(mJ>;;|(oGfOmN^
z3b&m1Y!eJBcq={x*gf8ED!91ME2IZfC2xRczg0Z$XAoBNZ0JQ>!}F%(Lmh9~3bfVp
zOeyQoz{{p|?L*#XDq(Kq8HGWmi5EVGAewnA*1)cX_a~({T6r?6>U_kD-vIMAUg82k
zxAP8B!n=c~qAG<>-Zq-@ck!Yrxzf$MMk|{h-YPGk^zuSZL8XuPnKhz*%;N?Dte<DK
z5p7R+D}M$V;8{|6-XQP$wJ;yzWz*K_FmHnj+z4+w)d7z3N+|U>#!H}k<teX2inejy
zHybcY6THkHK_+?Zzo0qAi=%1UH1BjB+|Ka+{1s%DXH8X)b37y3VSL83c><K@yw9k9
z_XTg$BedD`e}5H`Iq@TJ!oZooHXbM^`7u;;;>uS%hd(!dS^^xo^H&+b&WrE-D~LBg
zpSGz_^A+Di#fSeU6(joc$EeuSkN+R7)%^MI9RzoV-{S;wmj6B7B<J{sH1#{r|8+IE
z3;ZJbazp^%?m5UszA_mof&6|tA0EWtNB2rF|29qCL-^yA(!0ce)C*xKe{M0jF#d~o
z5kxrub;<=r@ZTvx+hzWrh9HsrMB1mk!mq!F9!2qeDJ>GspQK}eSNV&#Ac#2r9!H>D
z<EPNGE}k!<^P35LN16d9^8cljUJ}2c99%NrW*0D1_#I0jOy&Q|Mw~bKD_(^#jW39V
zFr8m!2e1tOZAu$t^3AJ(nZ@7mIk;@T(IJo=z91Yy<no7Uv2}~TzXK|_`6~J&4SD=Y
z+5yPt+w}svfbV)0!58xPG@`AD{~LV*?hfC7F=8p^55JC|v4k(84TMs@mLAPz{75GV
z@A9wFlf9g88w~Rb{%9K9R`OTUVylY(iva$r`ERwudky~^OPD|4XDvlrE#E^94-Nbj
zT5vq%pI;1NBmY1pxITVl7%(66Yxcr>KmTJ&m_FgN=>;~xKb#KlgZ%bFU=HzjQTgF8
zUtbEl5xzT}C?4gvQq*I7P8-^u@@4dN8|OD(gog?K+f>yu$uF%(@KgMaeQ2BJ3u#3(
z!>`)_=vlt38sjp@cc6#=GrlwlcJ_h@Z)iFQjI!a@QE)6A9di;0qabt^d~y-wq~J44
z7@QI$`~wviK?9W|xe7K@{>)8a`yn`Y!F#oc%tO%i6b7Dxqf^lI5(LvGkGG(Wo^_`M
z`IKhz5qQ&HtFPd@VZ`YtFr^E{Uy%PdP|gTCXtVpQpt}~_IYAHIGUo;Bt)Oy2u$p!w
z0tA_qz`Q6}M0u$|!7P<S1PT5K1s5#HF8~)J*y;<rOM+;6IED&}4+1kxU_}$Ua6w-c
zxCp_kw3NLp@RXusk%BMi^u-lHGv(`|1c&<Zt3(S{(0V0CkW5<}v4SHEKwlNSFoAiT
z;Cq^oUlXKkhllHewe-}uA#kVzi5G}yZI~d)q}+C*;BPaKB!Lel_>u*m)0ZPs1WmMx
zOclIOMZGr#8MI@RCfGn}!gRrJwSdkL<Xi*E6tug*ZI&R7URl|K6FXs^Be+hVRLB+N
zq{HBrV1E>Zw*?04fSD&)`yWWYz^DtPKoCfa*FwRTaP+T8F!u^D?+A8Nb$hX3CKf0q
zf|N!;mkN?!gF%_Vq7cHnf;}|W<${%zzrHVUxC*XP&_w$(RRSj}^{f_LT>yg`K{Rbq
zJP=&@3|*-e@Td;3PO$3=dRs48849}wf%6G?cqsUcw#*v^%Zngv61dRBtXYuD!yvZ^
zN`FRMn_!5NzU_iF^Ptip;Bf%fDOfv;wl2Ye*AaEM;0a~j`vjl7i>^Ettp5q-{em%C
z;|&U`x*!}9F!dnA0yWhHj|sdwfcaFwS^;ic;G;q;6M|2M5bmU4_qS-95}a8AZd!27
z3(zxyI(o9t3SQ3#%A7z=<)hC8Mk^4~b3y(s7`zZfP)U`&@MrphfP--FHbmwqjHG;l
zlkj>bgwDeMe#fukBJ`)cqN}jt9_-wN(exDd6lPNush99H?O}QgZ|#BkX<-f33HS()
zB*Va0c$rEp{Dh1uIPw>k)1u;xFm5?wIV-&XC(O?Ye{Y3{^TIQ9*<28gu0mUYu;nQ*
zFABeU0xnRv?;V5`B)s$zJOm5Bq3?%;3fG{{$1qH|{3Oi7g%6IRn~}l*y5_G4aZBS4
z5bk*eZPCIiXV}FES&P8M3fb-8t_oR;VGt+$PXb5RgkQLzN7scD6KK03T>cNZc%juH
zs3ZuhzlEbj;p1UwCJ8svBPdxoMvwaxp$$!?Q-wcYMS$tT`LykyAzb+zdYdWip+#Dr
zP)L6uCST}8S%3mzEEU!j3YkkFEE3+MdBGi_MFZ@Lg#+}1mk9Z*U{@+UM&+?(LKFJP
zz+Is=0|w>7sEbgk5Gu7G_k?TcwDEo6t83uBQrKSr=qe#U38Y$h*aRxILi|NNT*<=1
zW}wsyJIm45ApDu$jSq!+-yoz$;pPF5CZYLK2%Citly7Yjx&*^}n{fOQNW0LH=0qLB
zm;h*Y3PWkW)Fm{13%^6RFq#SrdW7|%5cUcaGQjl-Ij=zTiEs%`i3fz7{pjYP@CEHS
z3<-}=R(e?Y(=r&02siA7a8zh$hsef+IgRl5RA@pAfJxyJN|{Uvw|omSEwp(7yBT35
z6%o%0578YyCk)Pl`7`0`R4(^im_z4GUkJTK&~y|H&|A$(w3D9m&Z3Dv41tSCa~y51
zqC5)FO?2u3z&u43^AMnyh)es8-XZ}HQTvJ{f#Cc^|IDFB{vsFJPdz6(XO6b>qUH3}
zlMABi2$%<ozRU*~Boe#~lwi>js_eKd>Q}%ZQdH3dlq;g3B5+ZnWwbpLE!vudaAQPY
zP5>-c<mP~ou8O9XLNiWeR0QEQQ8q1QuZyB7zjQ<N^QTaW7qNbVN`k0|${`X(?@hyd
zk|?qk-jhWhluu3({Z5(SR8a;kO>T-N*1}(!$i5uj(?vhi0jUhpG_960MHc@6GfQMn
zdj;8|bsxeYN3`1;!RLyO5xFJ0N$1>di~b5jxcQ=eao`F>14am`P_)|yK@^GVmLa4&
zqRC4DD;D*ffv`lhV;1J6qJL;xpiE?Q4hDBc-O11_7j>M6zY3A%3Pg5Kq@zNV`=V}l
zKv#<R2Vq_%iaiE{YSCFL-l-AAIlz0JsH+FUdQl7|z#2pWrx9+GXcgtQn?;6{erplA
zl4hIeDHSWUi!|eC>k$3Y4z5%5!>8c7M4yBMrCYS066}2<tMwp{MfYhP-Y*KE48fpC
zVg;2U(TE&&!=i^8w2g?`A`scADDXqHjfo;+A)FAsa}@@Yq8IOhOo?t&c5+rUMU^Xa
zq7|P)^O<ONKEkyZE2u{f;=Q}k<|xi6Mw}<bS8O0WB_5=bX&3QL+TL~*@2CWdoA{Mz
zsJM#@{Xu-iCyWt`pLm-+h`;zbE!@wDeGL%AS#bni(C5VKXoh=UtXhN7y&(SjHw<fl
zxZ42SMe$KG2o%pOLM%bzYboG@#ecgYmJsn<>tT0EymdL+LdAa_LM&n8?sFjF;-nft
zM~LIDqV2M{lNP;^VlCA@T@kPT86Kj<yC0z~TAX(bU@_vFWoU~PD?{M+s(9cD9L0&(
zm|>8wiMK9<qwC_-G6-*o54;2Dc<~v^x+jPusBSw^tfj*#N#c<6;F85Z(uJ8KzDghW
zOcl@X1$R^YdMUut#N2ZLOBeHV5k!V~VKBUBifwZs%o4v@1@mn2jk|!(5o_OuO0Kxh
z9NaDOrUszg79SKtm?!R{j^&F#_5xQRcGQ6@6!R*eQY5~A8r&UmO&I(Yi}%s~W{LRF
zT?k9XcXvQoCSJ4~zt~-I`(;F3E}k{U?s$dx80EI_i5sbU>b}^FzH3x1-b|Y(HR2<b
z^LQXWS_qVSv3C%J4dNHOK^}@X^&skIasMVbY7sj)!md>uXA5Dw*yI&}b%@W>(X>wS
zf6egMBaVB7wq9|C6hZWf?Y{%&W3efnB<L6G=wbXsY(w|-fOr$Fpa;e4D1SC2en{Kt
z!(vBD^Nxs*e2Cv+R4jZIc2C6>3($vgaUMM<Cd8<-#N{n6`5ER@;vg!2nie-v`R|O_
zky8J&;vq_J%!w;)A$%rY;D+Fzi|x<C(F?KDdi2&_Vpobb2TAuhgpQJ$eQ@L?i6{ec
zmQ>RM;G{(AkG4~iZ>T2GMN&?SA6Lof3z)k}KHwu3cZpO9Xb(w24TPSO%_4aBlB}g8
z1l|($Ux@6qWM?Yud?YmjX!=UNxeTG7<k&WF{*sW@&^#kCd=<j8lD2rDoReInROfj~
zC2eV4kQAmPmH<hwF;p%}>fb|vfs)m?;XOz)Lpv(L5(}Eohe#Yu5$7cdw*;D@k^tJ6
z4wHnrp)FkU-tWMSkX&B@a#`|kJD?*ayLSNkieyg-NR-5bB8!%+rN>i@WHDt6V<o|~
zgt{upr{_eR<ntpS*Cao+0Q$P*_iaGAAz>OqGhVW92C*baEO{_Ulzg}yU`Y~tCZLlg
ziz!>5B9R6nmQ+cT6;y6Y1T>dQlbou6dAg*Iw)Qh52cAQiDe*~!FiW!IGjQ3G%0=*(
zBZ=RH;BzJMl-IZ=>9B;q+Y%o?VCG4>sYoSX@(<N06-atNh1)_&j48MxiL(mc??@K^
z59Y;^SN;Z9B6)u;3`!-ef8e1^vW{~1cO@S52r8Fo=ml0G`8WX3_ax%?;iyWoDhk4C
z$$wvhtC2VlfO{ZGq_0ZUO5&*Uy-uQ81%LGtM<v=CB<r{Udnk$A1A|6Mgf|AHN%D3W
z`ra&&QOQG#<P{DKS|w3bnEXicD-S4blK3y-wq5e)D?sUxT$RDRQ=+20aF^sdy>GiE
z+fT!;NAl}oaJ`b}$6?SXv8P${V@cK)c<7f1Jz)1lk{t<01Cq}+LuF91>u0D8N#ZDV
zJS_Qy^7<o^iGvW1O1_%LNQ_AW=neZ+@(w-Z#w9<$0Y?*(JAqJ{l&rTz+myte77o*r
zgO6Z7Be8RZ=B(sZno7?}9@9qgGf60Ya`m~S<sjN#NUlx++Fm+e0HK4lco#b6EN!F>
zl9SSC`YORGDPs)8MSAoz2wkNof&k_wO;f|pUF!G^!u60Yp=5`rv@8iiFX?@{i@l{)
z-vI2ibSHhr)kk{c0or_}@4W+|pR|`YLHwnYl>Ip){p1)1`K<KS2k6l`sTsw2UYbHl
z`wLP%eK{#WTJ<eFT$G+RfM%d{R~m#tQVUAv1WRAt4Z9F&4;7tXl5$hwAymrTjkYl9
zyHs@*E`37g5mLwR5ZPs^M;EwAsr$QVyCPj`fFPozAJXS>qNT5X2Vso#X(u#erEMD#
z%T?)S2eidW&(n2wO}dkwpVy@p_u=7&G;<qbiI*m1K_y8#Nt3o@X$qy4Q>2L_;8LXp
z6!lH1zY_vXlm3|olyvDm77Q|^Ba6UgN=JMFmL;|O1qRvDlPqvK(pg#&-IhM3n=4Pc
zgaOQaX|MtO6-mQ}!QGKcGNDo|{guko%cOr(4c1-hRm$v@OQp1Sx-Y#<>8VPoJC*BH
zNk94s<e@bCIE0PTGpX>`Bn{62ShIBYG3;8T?@(T&Rk~>_pdU${sC2ze`a11mv`hc9
zgL#KkM~m!EX(m17x}*<RL#114OqD=A(wHi!^hzJo8OA>8L_f%5Y0_P^^-FbfxP2n^
zp=#a%=?mHm8I*b$LO3L?oe#TV>HBo?jYwaiimXxTLCR;1Nh6j5<*8KI29<HC=LCck
z(!~;>OiJ}MnVpp;(UW~n%AjJCXVO^8QazWlZ$tP(`qmv7*vlL|(OU;uS_#@5Wv^dC
zNT+1|uJG<6>--XSt}+STPHwV)+Cki9DfE2tka4I$&Qmt?E$qBxF1sN-Efa15@sVAf
zg3wpiOFM9WGD$8_{AKO}n4giomWQ^pvd5R<=$!1UBB-2~d9Os<1=;I6K`zR^*azr9
zSyL7Q43hmrtAb#ex&<MH$T(Da8!Bt2qwZlcOCxaMGC8dxFU#(wpkt9TciMftB72Ko
zXVJ26X{i?@3v|c0#LDWZ*yO70e{?WBPWHzTxEr$ix4^~A$|$v(AX`ok$3&Tn5W*yx
zp9m_+vYm93q{vKYGci@RXB3(@W!YokGGwQoqJNpPj2>ua$#%a9&1~779UwWfBR3$-
zmATQf`j#waGx~5_mPjkpJX!5D?DA#D|3F)TY}F{bQYc&VI}D0siS&NIBkTVTZN)O<
zE*O-^(rACIRAxd+?J`-)7JyaAdS3!}PnLWQvD}xrP&rbiY>N)&RkGixfTddYI%V%_
zWEb-xd?1UH!=P4XMQ6+EWZP&ySTD2P3(W@Er`c$0l&zpWjV9UK)d;Xz*5m=wBD=B(
zD6O*35}@)(CKv_RCc94OcH3p%y$HTTX5@zeJ7pgV;HXQsViv+~Sy(w#dSr@N*!9X@
zc?YCVmgouLW7$WPUhJ1;u7>6l*}ZVI4aknr=H8&}Stvppk}(oMMrA&IAY(FnF$|u{
z`orLTQuY?D%BN&y-RQ%#?DJ1RW@KxraBx=k>_fE8$#T@Ndm*bh0cd;qciYhBAjfhH
zvnP4w_YgYEuSQ_#PRh4aET`lWx};p>!+XKG%73DrUN^aF3MlUKl%p{4kTdDk<0+TW
zM9@pVk<Q2Y$iJYRqpy4iRe$@*gZUu-^6Ui=o{@h-`><!_I~;&=PJV@|htJE`O<<HR
z$lsuI3<2^R^bENu@BIQ%2g;|Mpb{i^?nErX@;@WtFGQXzg83!+3PY%b%FSMfL6|&%
z%2~qY>9lhYA@5uR5+x6)fO)iB{tR|8@^sn>jg_ZTR_v;Le<gmSIJr|Bps&eo??HH7
zZulPTZpdYHL^odkZ#q;G<SA8vPLx0G1Xz;%BU+gz%g+pgq{xp^;w4o+n*)`b@;5$4
zAJXJl>ER(R|AdN#GUT)F@Q^8QF+y9Ge549NWXr#&iA0WkXEf|`<@??Mxg{^kg}>YK
z7BM=OCr^JFn)!0e*B~sAZ>N2kLixgSpcKhprec#j@*P)zQY=66A^erdH@}8%mdb~R
zK+5FVG+(+aZ|a9;xtvFtnhLo)9j?76A1wyCFAt)pX{B67kCG~R3~i89%ik#nsgZv}
zkC_K@4(;*P%GXo!p-#T+9!R}>ClwVo$X9I!_fUS4;%t;Jpqr#g{vJJFn&o+vcWaT`
zQGIKxJlz`}9?5$sd)FqP8bQ?U^0h`#>5!}F?(derO!X5zatjXHdgU#9AncQWBZA#y
z`S)+4tzUlaJ`A47U6!M_1M<7HH!&zzHKUtD^8WAPXjs0?0X-U#$I#n;RBmpH0LSEg
zbU!?mThSKpr2N`z(43N2)5K+3ZrFj~XXFoQ{WmLLN-Lr{Igg&#&*X(vbMjm+qSJXV
z<jHR$Bzwg*`iUJBp+91H92M;eP;pXlL%}&K_GZA&Me)&l5V|VblVRYdD5l=JD;mzg
zgNNd){ZR2#FzEXXUJ5=<jl2~fQa#^k#XoNW#Yd4RM@YVkPia%hPvJlpt-oSEec9`b
z!g2&EXB9gRLwHW{_bc#lUU5W?kS-{8(B~@x6alNz+lz{EE>r>)G4wHuAcdIbgTabh
zG{Fi{d~OA>FvZ8$(H5@QycKp4in*5oc3Dwh2bD-g+6)HkisDiTf{0Q~(s_hv#T4Cm
zF^XqzK_yo4$~`!`syIidk>V8dXcclzv6D6zt}9fO1&CMto&l5u#Ydsw5)}b7lS@*_
zsRAWgar!I_QWTjd(Uz*X{t)D*;s*^vN>gkx2THo)SOY@JP^9dKzidT1m5b*nR&_y`
zt5DF8=P6<igXAj~Q<kbgu~mg`7Akxv;h{)j`VqK0iqij|1t}JULZw6zp+wZB3e6oj
zDpOR_p445%`-{<5u5kYtU=<2?y1efx*3va`U$G<|29=86sO+>#aY+F0)r#-80lG%<
zEtPvbQ2e(9ZM6zrIKb)@RWzrqS4_Q&wg!c2HHPP*!j;bBH7W!<(3K`d*<wI9D?Xro
zwH8I_ZiL&ac;zJAK2o$&@l~6`I~ic@3MZN;cPL&OLR+UI%m<`P(cl8_JqkxY?0OZ4
zD6`O~h@cnBV}%vHKKm7mHBfn?xJ=vk1B!uq2nQ8EsS*5;;u)o*hZW|O-XBq9euPes
zDt@Elt1$(i$|0UAP7)bcgv$`bgd#+Uu1qS<W&m?aabh8QG_7!@rR9twtOY2uii}BM
z&MD6Q3*j@x$~ZWBt|)p8=ogAS5#qF0#$SQZLAi}~vK^IM=;v@!`qOLIS@{jk?oTSO
zjbk8BDI4BHH(ivP-=X5Fe6<*uZpzv#;M|pJYp8fAFVoD?Q)x)^PcP+i%7Az)U&;qL
ztyI&s<fHtIHeGy`=R2U{r~Hv}xc*9C+DSX3{5u_(XO-_#%H*8ViZ<fTD+iNda6!3%
zb_xTOU!O(aFDmos53U9(x%AQRAmuys{tH%aEkKV#lsVgAcS-r`DQJc&-RLP5rt~_E
z;KP;WR0|NHJn<J)E-T&s1Bq02(sg}BS=I;5DCPB7L>8^A`xBTk%2Tvu9;>Vvf!$SQ
zTQ7uh%5Zu&UQ<?l54-Eilz%{ODE(gmEMEDoFWM56MOQI`iOM9}I!#hK&~d3`<$)RW
z_NFq7UfyZSo6~?!S8Cz`ouOn<)+kfyLT81tluO=5SF)8#8u=XMfk_zTDu1KZ%PnOM
zt^02)9efc>o^t8u;PRCP1F$PlM$x>rQ2B2TG>eo)AuzwAZ1@7u#meopJ6EC{-v_%=
z<v3*|%9QuMLr8a(=dXj5D?KSKS)pv81noVgb}>-yD~D<MQK{^ukNs6ClS|;QS~(Mf
zwi@Ny2?!r38>n=lRyj@;S#`=wP4HK*^vg$EgYqohun(2uYv^X9vW32p)uhygfooQ7
zr65|A>>iL-<-j2X_(*Bqgtj*2Dn8<DS0-FSNF7SXAz*eY|8WJ^r5vL5Shw;NEdY9y
zRRL)0Ri6L<x0BK)9x9KOdu~CcU+H}sC{L7!3cw90zoy;sLFJll82KTk>LJ1%R$gC#
z(H&84qAKT6WdRr5n9}MxxTnfMs!AGHvMLbug!1-NpiC+``_ZE*<vJUvOe^Qn&en|b
z<vGMMt4y1M!JM+G5#*V2>~nZ{uKdRxnlF@gl-ssf1;rx>2i2B+0CQAr`wwkSs^v5V
za8{Mkgw;j0?-o>CRT1>4bW`cX2-jUT9)=)1RIz^|Ku=W<2g1{;Eq*ZfQB~11(pObR
zB}Zpe_x2&Av#Or|0rQ;7^&y1kRnc?^<ATbj2*Lo>`8^;PRqL0aD}gGrb%-TMHT4Ea
zu&QYenjxxjSEyW4MIJ#{!d10d@DQQ;#vdw|RoCvrL!_#JuH7rDajH^?QY8wZ606Fi
z)zVc}EPWp=4nd&phKe~2VZ2IDON9hg&Iv##t8%Aco}&6{Ex=M$-)BPQrb<T>>ok=a
z<#5wgn_hxuhUyhc=x3^86JVaDGNe6*Y}HgG+HzFu>Bvd0s*(1O@>CX-p2}C<ufot3
zsCwRn!5x*u&mhIB!8(u<)lSOxmZ`S)1M{wG*;%+PSE)u}UZF~(bC~y3S7@nsUv-q8
zHkGRLUf`-!rG?<CRmU|Lvl`U_8H5j1t;Y~Vohs-6ez<y7)dx^%P%Tvf?4b(l8(i}$
zhrglOq%xuHl4h0XMsO{v$NOQ>syea(L-0sd$APdzwd7lP?^Jz2HQimR@e~Butr{r@
z*P~KWVL`9Th;EX{s)Mwv(62h43-c$cecz!+1F9Bt_#0FuQyJ5csv#JW4XalBVL(Py
zpM-)NRUM#9YD|^Yh*+MgzP%1^T(#g|s7$E(DG4;G`tWsdQ>ug%fX%3cv@V`irPIP;
zPIZ=^k<V07p%6Y-)x3kqUZ_^?fq}jHw>1dKLA{L9B97`>I%4Lee)$}Tv-$$n-knt2
z)1Lk*^%ov6cTsPmHG->}6NesosAn7D-BW$yQ-tKDen8(u@KGP3O>19uVF=v%sjtwI
z+h5JU3gH=bZw9!t>NGoW7t}lELnT1{njYLm^~;8U4pd*BMPxzh->#u8SbcmI#wA3Z
z?*^4i>eULk4OKtLg4;0lJ*rL#SHJrIdm(D|PMBX-pIn3>BGq49h4~frE(?G~sVAuT
zF<RY~j<y)}{2YMAsgKg$^)>av3=HyhwbB9PhI*Y2nDOe@Uja!_N6msHtLGdsASvp7
zwLnQ#Kc=exbafKF_%hUA&mxvgb;~07%Tn*6^0jRBD?E6}QSbg2n7Qg;`o`HUwLk5l
z+*WrMBZxfp+-0=otJC7Z6{tVu!n{yDNZVvZ>S%hz-ckF#gtlUJ-ZFS7QGXNz^HO!4
zEqYX@b}@$cyXur3fG$_>*8{9V-9d-c@2RKX1=xM{uY=I6RI6y!Q>7kn1y`-Mqg89I
z`Y=tp>(oo0p)2)jIVId0)bE~#@S*xwe`q$UH$=cglUlb12F>a}D3#Qrt~m~{R`o6#
z>qqLiN(kH37wjQySM%Cn*P-6uhmbne(GdXaQg5SYNVj^)CTRAk`#Qn(sy!;e^{H8H
z=-6YmryEGWdg%;0{X~s5Hf{^GECk%3x*;8!L+Zs#5X-QdLHj_XYA;K)jj0zkLG!8l
z)Lxj6tKEt~Ce#_U7M)agK1YwH)Lmb~U|Q`-H`lCMdIDrl{f;ZlpQ$amFnF$BNt-7x
z)JJF!%wEI%5kd#ePw&FcN%Jo~L!329d1yPSx%4^gPHEn_j96SWD%!zu*D#{Nd1yX&
zhNh<`ho*O4n*XAJ>8)whV+c-bx*5>)(M->w%~!LJiXZ(nyEy>!*UV9l`i$m}74UFY
zQ<DYFbDC)vV4m01QbzuQW;>M%2521UEZaqm5uLCI)NG`rQ;=p~4dM*eEZUBrBSh0(
z0dh%mD+cDFnjicTQkcd_3e0eg$y+dw(0oGal*<~&EkKFXc+oTKil!|GC{dcOERbl;
zVl&vqXo5b1hggmFE&{x!=~)Beb<MCJpl@hivH};cF{bY`Bxu+)Jx|np5{Mq9XtZ?E
zrfMQbz}?h5x`VbfO{EUr(=`R9h$Tbg-~sQMnrND)Wobk|K$xwmp(lHehEE=HHHHcZ
zZ)sK+04z`ALD`CYjgC^e1)7Om#965MA^^f7jfW33?`ZmyK#DalZN?CkX#S%WSefQB
zZ5-Xzyjug!a?NY&Ags_#31NOu^D@m2?`v*bLZwopxdUO9Ch{|=RBQH9Hl{|CD*^XF
z;}MQN)M{P~pbvE#8Ep&HYgX1^AR9D8l<#?{k(k1~Q8RH2T$AR+ePA|gM05kSXyT|0
ztyObi7QKC>(d59cO=E^S7{hkWoIM<MXkJc(dAH^SJ-vH0TRdUVtI1sru*VwB8gTs@
z)UV*~(0uzJyboxqX>l;9k<qTnkS6m0{0(bTsCs`yV|fRdqnd`DP#M#_OegoAYG!DA
zdtBph4>F;Nv_!|IG+!`aH?28JuiY8Vg89&#)v%Rlo72Sp1oP(_YwG3;O$&u<ul2eO
z?+#k$KM|RuHYyRC&RWR;%ui}B-+;;~?Pv6kbJ4Ek!jY@?OIp#oX@87_rn@%D2b_oY
z7UhXNwZGA2>ZKi|;qlh~N>8HGTBC14e6;I-L7T7Egzi*7?Ts&?;;%hVS?M!cPde*$
zR;#Cc-8pS^Jwm#uwWkk`1Zu6rK!UWp=%E^{?KlsW5N-5Um|xQFcmVTI?LJCxglSdL
zXbac=se-=<?fpCGQKa?{x+bn@EqtIEr8Tcb5YgJgUC@lta_H`e)&6t~ZCAC%bRI8G
zd;0@`UDF;lh52<YBNg7`wSH7Al%V}12_#WF_%22;NqdkU9?9B@tpH2W@)OaPs@2gc
zn48+;1>n-O5vPEXt_`KcS%!A=NyL(^{f<fya<mWVcgWR#KozF9v>tR+<+e5;7It~s
z1++xW*Tx=!d4cw}H~L<vP1yy5BJIgP;P#Govj#&@tPR=(u0;Ea4$!6A_jbdeOxsRX
zY<IQiX`)oFl@Efe(B?iz+dXXtO$hF5?@;=?QhSotGF93wEikXv?xiD9HQJ;f0sTPh
z>j+Y-Rnn@UPP=gpNWFHUH&hz5MiT&gs6GBQ;%w9&TM5i2t*bFmnze3p(LU0?;)k|2
z?WjFa+O?Im0PoOxKEaT8YM-0JZI^b52)*srzMxNt^=OxV1<hWqA{*v?+A6A%c&yE!
z*>=D73C(n#XwPi{8PI-0d7DA)YgA`7q@7R4<c77?Z-R_yZ(D+lYJF(uXG}Xy^ZBRR
zudcyvT>DlJFekL5ufX4=wwYc9Q`$UQ6i#dBXggs>ThR&3S*@0~_UE*kdZ;|pP9H$q
zbM06hgfFxY%m8h#`*Ar?9CW@mFmTj$pg7ymNf*O|&{=nn2J57*@hpU=bpNCDshjRG
zZOggq2H!yt9=e%B5PItPRF&kV`=c0|-ny&@Ag6Wjm}2OBbbsX`cwgQ7^osP;nbADb
zU*|)A4dRS0r53`ox;)wgJExnpK!E3UM)Xno3p$5A5C-Vpasj!h`}BP{3e;sC0cMcy
zFGrAI-L@Yg4AI?d0(VLGvlHw>bvtO{8K$eCG*h_FlQLKlx?N|Wd0FT703#8pOEv>{
zMYoTFh|;a1nv7`O!els#(b@O_<(e+}D7fo7x8p#$p*u{=k9b{oJ~R__TRubo5_L0F
zG?JvdMbnsM-3vOlmZJN-6WmSRyT{=nO?RjZcImp;|At+LZfYHbnYvGD;g_Ww_!Q>Z
zx{~$qm!msC{&ID*G~v0WoA)0KZtKQ3!#q!S@d8xxbsu)3tw7iO8`|#Z0{S2<)~%va
zx)NRGuW)-;x1Da1a$P4)N-K1+bX`~KKBZGIRl2CJVNk8B_X0|-?h%zk)akfiLRhc+
zDFOx!x}7Z`4|VA^=wGAm#57b|bz@(`!y{ch)i$;1)OSJJbyk!x?a=K#3a(Q(`x@fx
z(gnT;yKY@Km8JCPPW%hft2?v=A@%8=)As0NUH1o2>DNVMVpyN(meF_p26W%hKo08u
zc7vlK-36L64C_Ydu-1r9OI1mux)GW^jp<TX!O>IQ;avb5*Y&u;ZbG+i5@3_M*XZ!+
zlx~0~$kVzCCVuxB-8)Gjv$_x}I+)Yxm%+m`UCaXrpX+whM)(U|`LE#Y^=XvzchDzx
zV0aw$IkdCoq%WY_S7-g|M3}qix1EDOSAG1S@b0E>{R?j0^@nIr!$bdQ9l$*Gz9t}E
z`VBM^-ujIb;7;pz8^W!R{^LZL`|8*H06RbZ4g;w8>$lQt@QnT>C3?>4Pthdfoc^D^
zXgjZupq1$b{bicn2k4t=O?gr8nF20Q|FI4#L3-6s2sc<iSAw<>{YyJRF6njNa2u+3
z?|@2}-lG{P;d+xh@DQOdrM>dY`eFm1MC$L-j`S6M4xRRh(zkp7^H_bj1VLQYhrJGz
zIDNYb46f;$T)<t|=e`7$8~R4tUQ5t_^)I|9>JwfAN|HYP9=ejOA5FqwrRe)<b0JN?
zd<jUp{^&NulA#Z!&k<zmKV*T+(l6!%Gh5H3*KUr!lJ;+N^$%VE`j+0n6~Y4jPm$mX
z^){5TF4CK~0ql;ROH=S-bPNV1`WbhCmFhE6pi-v){1wD<SMPEgeJIx-RKwt&o^=r9
zzCM8xHkJCf>6`sk`cpK8tJcduLbwm~;RX=a>dm^r)#;<{0amYXp{t-lKmQE4hx%~?
z7&Pi12%y=l*Bt`aqL<UAb*tX*LvWAueRMOo>3zP0qjvpN0D|byFRnyLUHX?VW01S`
zUr@bGkAB%B2z&J#>9Xn5d(Q*+SU*WsLjC%%GWeU;N7K+f({t0H@<QLO1aUmPV;P`N
z9^N_x1J}b_r3ldD@OpY)dmm1wO1#j+ds;CdR}Z&z04)CSN0fU?K3rD`m9)cc+ab(6
z+)9hdoWmRMBlz2g?PwiWc$jq(!m`8j{ejYWn4>{k-{IE(&lw*!p?byH!v`NBB&Q=^
z(PiUuWK{;@JblEu4E_R+JfK`&*pb&PVIFg&A`)D}k!qT|WgZc;09J6s<862^K5}{^
zRPG;fc@Nx!Bd0}BIeqluQg{eF`c?>rC*tVuTL7JKH0>CKsYkt?0hV)gjAnqvN6Q<~
zcK_(Nv~YNM^donubRI33hqm6M-!4LABS$Cf;9=_M4_{!g=8m4VfVrbxKIPWj?f&$G
z(93QCC9eJKntNb()-HjHp#tr`Itla3cBwx=GurMB8;;`aoas|pH|!?p7EQF<<_paf
zyHa}0q}n~}hQUp{or}?yX7@QAB+0hBoDD9=?#)^B@0Q&nD$TfUcjg@0^6YkwfaKeK
zEJHU7>}H)1S)twMuY(lX#Zg&9v0WN1#7gW=)7SmW?A&Quao5gbGlb=KbH@-;g<Ufn
z9`4x{(T!edXHB`^D!bhup{?5PFG`Zs*xghiz*@T>>1c1AU0^yi>+L?E<7W+aHWTP{
zyWOAF!0fWSj0OKohWIako(oOptLIfkA-V_i+G(O#H}8}L5j4!}q&ZXLJk`4}YM!_1
zRj9Pi%V&XWo44%^;C9X1L+^pXd0}bj&g8rmy=b#Hu%XHUH-jLmMe;LPc8&I<@gH~g
zYecr}5`79|xu+96z2%&XUcDVhGs+dKXz9K#i56s^mv2Pt7yR`AU%x_w|9@HRfz}OP
zv^lx)ZytWgP3Lw3?W=d_xc=8HDoOlC_ZYU{{(2WWo4=!J%6F1iV7uk74%lvun1I!`
zY`X8hw|ESzAAD<|`J;0bhUTXvsxsSt?jioY<H|P3cP1=HpMHLoPVxN`OXIdHq8K{6
z|E0XqulkRHx#zSBn7@5X1%tn@rRTyQVh$vGpZ*S=Km8J*zc0849{2C2Qt|^IQ11P&
zPhBB7m{JNahd!cj7uc?*f`8uZQt0#l^hT@TQ>q6NE_xmR7OkdTs$<d{`2WdyXQ_hp
z)V%GqGww34oUTUKdDe5#cANKpIo!I>tEHEh$Gpl72*`6Da~@E==H=gpitoHlv9NnI
zk4aUqL-R`c5Dw2fP7lqQd0QzDG&?VqCS@lL#4ABg8Pt3N4=x5ws-ST-xN{sH+zg!m
z1E#yd@;RV*7@VL)oTtGusu}e%kTzoEgA7*gMi9XUt(hQE2J!Uxi8h$O8IEEMj?#la
z*5DES0g<Z)^XLp%oPj%~A+8x5yb0**2InXdaKqpi`rcT)L3taX6AW}Tp-D8jLVLwY
z2C_-GO*U|$<3gzh36xE`Y4C>^RMHIQ=yX~Nqm42usSI<fgt^K1=^tRGF}mi%UpnK$
zFoYS5XO7U!WXz|{*DOX7?a*X1-lRg(9LAT$@Q}+eJ`9vw46PiI-DZp%!Y+?7`3`!N
z&v<+Y1_g{0RQ_7XXb%K*5kt5VDt8#ZNq{b9e60sp!Z@`BV5N*es^%$Ugna{Yml6Lq
zFv}VKWAInOh^CdqJ;o{8@w(5DQ<Y35!}%{bs$v|c&6sM&AT4og82e~{=mF#XR=BNY
zJg4PT9peI>E30P=&_&b0SWf$_4;eS<xK|^?_8c^u7%OPG-OSkeGd#2~-08+^W$b$y
z-XAd{1L3HR5kuEsJ0pjFl@7)XormdUBv7eb7h^YVdv`OkBcam6h&G46UWO?Tc72S_
zFM#=&k>-iEenuX>yq++c)o2@Ftp5&ngA4=uiqR0mjS5YM844-~A7SKtiXj+f-2DKN
zjWL215I$uXg&^E<#sED@CK#oZE}3M^#v_O+#_AYAPcvSl4YL`>l@bVN8TreAVn3g8
z6kTzcKUN95`1x<pZc)Pgy?S6K&VQ5!l%)A3>tT>Qzn7}%Qs$$lxI*T?F$dwz`M>1C
zZQA_liwN-Ee1Ez(@6R9Xhh63TefObRHQ$WBInp%$)8*(`^ZZLy(CnJO^)A4==fCnk
z4EpBx(vSLhe#Ympb1{5p6wt1QeYBPCW@ttWA5X)7={1gd`DqBf4d*$*{Ip>#-D;N%
z5ABCRx?v10butVS`#>@c|D*dh%g~IDqGTK1q#0fgY7pTe*D%i*LEJJtT#CqU8%ikL
ze8cwtA;1E|kLk=rp`nBdsEY8xW0>DDeDyKfiVaWB!EK45@m{zsHGJ_Y`rfj@A{EfB
z3moW}-=hTs#I-H>;C-04F9@agO~-<DG}fI9oX26%wZQ)?`l%LdFanuaz+$59#R4v^
zqU??CRKncBXsiiAI2!#;i&_t(_o#ft(`eaw2)&HnqBy;cj?)y)$Efa8bj8<5GY`bi
zsI>^>jM0`^pqw>&mDUyKjQ*xdnDa(EsE#qv$nrQykkKTi$%2ix({~pmjC!b|CD~{T
zt^HDr%uj%%8ciCa?WWPiJQ`i2A5!2w)9AAuXv;D(+>FSwjS@B?>KvoAKM+f<QS1_M
zcZ`<O#H-k-j&6h!BcF3HC^cI41%zcr%SV7xZsbD0UxiWZZuGs*$leA~*BgCDGuQ?r
zuP(TKX!P+t{3=aG9zVmp+2|XZ0Jj+7)0Y@)qml?fw;3J(|59V4pXgE2Y4jg)T}D3=
z*JGs0gh8*-+8PA^*eI(A<cZNk+J_u4TK5*npwa#12*S~L<{*N<U|dOuK?02bZh`Qk
zaeg$oK;xluU<MiId(vPT+eQH;#MpxNRxTOajY2cj_~E}$i7>XIt**<)p>!A|()cw>
zu3s@;VvZo9jh&8z#29;R07|U!@Hn`u#wX~DJaNXhzX2u1cqOfLQ;nUe;y=yUm0nBf
z#>!j3%rL%2$3`-ZJL6%OZJbSS+#F+lEZTC7XB~lg%XkGnTW=eW*g=?Y{9z-&3XBVB
zbF0ue-x**<#-`NwVq-^obd?wv8H1D>e@O@1?;7u*63}wv1j^=C7&ocG^%*av^CFLp
zSJJZbiE%!yG6sw-i!t(p#_zX)3>p7TFSiln47$fgjeY8&`PBF>O~b~G_fT@^xv?p|
zmR=Yyu7<h2NvSn79ZWoO5R0S9SCo=;GFkryP@GK${SeYglg0F;J!Num0fa6lslUU{
z)g%x*3x+->@Baf8Uy}+t^XYHmGzyh7CQ)LLb0#bo*qt|7y9byzOm@)PDBk2(ddDT2
zB+?FBl1aw_fF+y!<pnOqq=6C-sV48!Tl=O-K2=1dnQR!w=%$-2q^kZ5lXu5qo@ru9
zZ~H8h!}TE9Ccz^JKF8z$r3G?LrWG*1WfEWtf45C0-a;&SCck9U?_iQei^T$yWP0uv
znpFM(=pvI-!Dzc<;zSA9Vv~E6<0~=QuZ3o*Ng`c}WhUm^LGGH&(I$U|$(!v^xo2|0
z6hm;|#OMaVDouKJ!F!d-|FqDoHaY7JVU0<`>(G2)vX6fLT9c4&ka`ny1vDE>{Am^Z
z(Bvo+T%$?!47@j)^w4%lvq`{5@ZMtb8s(W=O*nKFJTlpS51MTzsm>6#o2++(u*2jo
z7eREI9M}iaWfDCEf88cqsYg8~4K&&7H7S1%us)MmAw2k+{<;7vex||eU~tiNR|hZy
zP3veD6l6M|rslz>wT5WBWcu<q&<r&#p!Gqx=`sySgz4eMXuE96q1w7g(^7W`qfAF>
zsTys%l+tT4rf(}jVomD>z>G8H(z&GTre`$(yJ0GzgRU8-X;ci9Y1+C8A!VC>u@aa$
zrYrsdW|3(vRo>h){g|dr_f1P_MP6z8+yAG7Oy|9ZwrbP8YhYJnx;7JF4@|X5=xwd3
zZz)E%&h$Vu+}4{OtAb{`X)$H8J51l8$zG@F*e-Bgrl0={f8D0R^bY7T9iyyeuj%|2
zMBQgv5(Mae(_vc(pO|i-na+S|F(r-$O=TAVJ!Cpem*TLgoj?4In0`d(4Mt7-DT^^?
z+C^vMo|?W90_btmWO|2Bn%2;c<&^0-&77xA|DvhijOjFGCTC3#i$LZ~rIZVKX8M{x
zxaX$-{tNDfX`2wx_6v8g5Shb5#wQ?-3+rih;k2+w4$gUDmJ$4&Txdz>!%i)%quH9v
z!q{X4@4k@v4E{V8ZlTG7=fa&djqzR>NrwVXFI;Si$b1%7(7`_6g@<p#k>A2EM*;1>
zaQJs{XBJL5!aR7PBV`pr7QRbq+)E2RuY-gx^rA;>_`)~F!9^^bT7g(DFZ}Z$xVDA=
z8$<Au3rnc>)80(NgQkNSCmjA9&6Z!I;LV!o(>Ts%Gqfde(#&fw?A*+HMxo+vR?0_!
z9%hw%V0xN$OJLw_mPGl~(`GwqpVimQna=3@ne7OJ$~m)7=-kzLv-fwR?Sk2wBM3gg
z>}`5j1)2$|Vl~KY{XuZSW)YN~3o(0xZu?L(1<lC9%&K35UAWo74Zw^rQ_qK^NVDdj
zA-rPtnDXdRX7V2qZnT-fS0IUIr|1ctWcFn_yeFHj`Uz2|n7PpFEY)n$YS`U0^Zy%~
zX=Z;IKr_Q^Bi-SdW=5YOmK?M5TVQv~>~C7O+%~%=h1*KA@fo<SGJEkB{8gL1O{ey1
z%vzhlJuu_Z!S7nL4}O8L&g=j^Z62Au{}f!C**e+<Z8vkKk7ak58QK7)%Pd@uZuXgV
zQd0M^nS2tO{bsqj@czWCKNKoMX3HrRHf+{I73w2qfp6hA8a4A-j;>6YeM+gKNwcLK
zXik|e`2;A_W`C6;&Ka}5A~>2g`+$QW=FGVB(7$J9N9kViGJmK5@iw=<1@qJ9^Im}X
zm@nA{p|AP-PeJ_5g9>5iZ=U%O-p`mX4uadW=B6w_pEF<b1-f$H+%6w>7tHPG3JEa(
zegRZ2n*W;$5@<gDBQ%4|BTpf+5OXW4w7X=!dLBrqxt6L{!py5_9T#q1Q2@;d^LHE2
zzsu%dkAhq=PoYD2QRZU0JEF}mdIBZJ{27&*T{XXS0Nso;|AwYN*Ua5L;QhM!(qBMs
zm~&kK7H@v)6L1OUmaEZ+MDu{}V3%a>JqNeR=87?xr<%7Wfw)@issM4b@ZAqhcZ<aJ
z2+7Z4&K+(qS_G}7u2|fps=pwMQZGOUTZGfx?UKdbV8j_}F-rSUVHV0q@DOfMqy<WZ
zMO6~KU$(eKg`L+djy^)1DHb0)fuveAhQr{dMLazx(kvEII<L&)2TESvwFuk}lyZw3
zlqYy#v50b6wHB{8AnH1cMk?8;w^(h0SQ;z_--OCT3ni7@G+MOZfUwEJcNCb-7T>=M
z4=omhkMP5_S}?XFh({I+9iiD~F|Z%Ow_BW6fOJ~?@h(uhET(AdzT3jI5-2?uO3G{Z
zS~y;X!KlTdETD{8SdF6XsYR|I;vBblZh^K5iwir!O<FvqvXd!`-~6F6ZIMHnrWuQM
z8L*qRSho$rIg6X_2>zKx)d@uQ++zE4aQ4hYHn4MGendxw9hs)|7Ik9&L$!*|%!|9x
zc9N;u0!OEqPOjiwn2(&H>B`hEg1H-0(+2~0X1g9j52ouM7+p{1Vw!P!F}tX|(3?3#
z+Zv~t36~)BVQ!)E^kwd)tzSRp=a(V$XO6{V%+4~!|33?2R-Ay!d8Q>*Dqmnu_Jag4
z*~=ij$n@)jT_96x4u3(+oW<}L%-l2$E`(W48(*Q!>s{c&n6XkAgfmZ2+9iT%UyQcP
z%+bHl7RmgKa#B~A)y*JL%-Ljkh+)prwHwR4@*z~NGI#F85X3Rp)6T~=W@;2rt~1}(
zLU@B&Nb84q<^nook-(gw?axGJBCTPQm|5>Zn9OYGMUPUMs|<j7llhb~HEGO-lQ2(b
zT2VE52Gepayk|0<{{@%D+)t0#Z06@w7+=JE>nXtQFrQLwc`<VrHs1|Pm_N{NdlfS)
z04mkYMg8bs4Rbr49(lk#SOl<I=1a8kT*oZ0M1b|oetMcVFzX9o@Q^u^1F%NsA}UyJ
zVjh>mUo+D<8p0N4<y~mDG8wJ_d&JaHja(bEYbR7Xm}Z9|>||~`hK_YHeW*I4n;CT;
z20cvKa;Wq&Z<m1dF)v(z=3}M-9kcCcCeRh~gn8sgfDJHPKY?(NxpgUoL(H{-Fc@a~
zK0+*GOxukBd&-oRqivjdkDdh+%zX_YlgtS>s7x`lX?8fx{KpU7oMFbL!oa~Y&=EpM
z%P=|%<YZYxd+*Mc7XP3}r!4<Ra}5{E*j{k1mdk0{<YqaaW(n?=*J-cV!_t*r<(`(B
z|3T<wxqzypye+l2;P$lTZFe~GvD}sj;%gba8;+u_zFLkx#9Gxdff;9Y?Jn%DTOD7C
zSmLc>ec&O{YLgK(ldaazKqb{G{UbQauqs;)%~~txYM8fMrEEo8ht-d_z;#-^Dg@VM
z#i5_0+v>yB@YiE?f?g;iRvxry8nycSJ7`W=F=+2$%1TLFxYJgcJ7XlQ4pZIMtkt6t
z1TkmzKIIvnSw$s5_}uC-6(+r~vPuA$y>%mPsXACcB7ct7{!|~~WPRv27<gKHTnDt5
zwdx0;1X_pFA}z>zBnVvzvF@kG_9bf<`tui|*8M+#3$u1x2h9lU&%dW3us+xdgB#X6
zW8gO3dQS>ShIJ?%Gs?8K`5G#P)}C!}TV#Fl3|-gOLsWZRY+X-T?h@<Z??6he`{-O*
znf1%G^LW?#GY<&Mt=HKjvI^_{8jyR|zs$pc+_(0mscoh8F3Qq2S{qSqd6PAV5--ix
zx_{xQ#o9aw2Cdei7r;HTcA(Q#ZPw?gc%|KX)C#1-+H($eo!0Zs!F5^Z4uR{o)>8p^
zk9F!wnD<)CXcMQ;`j?jw*<<Th`=Qxyt=R^*Ppn72hsuC;Ic@R}TED&<kqudYw+zBz
zYa<%E5$hb<-y5~g9YbVe))y!r`PBMdI*>bVz3eX-Ojw8O5a6WsP#;vLtS_~pZQ6QI
z6EtV6_XmNSwN9ec_MCNsHH6QsjgQl>$!eucx&!MqW1u*)h8IA^iIq%yT+XalA3)_S
zE2I|C=U7Dt0eyjGyBS~sEJGFSf>?^zFuK7kKYB%mu+Hy8xR+S|=Ma1-i%&1%FxGyW
z$%V5*(&(3FrBQn0GV9k^aFMK&-(r-mur_@L^C;E?m9j*$KJAAvhBZbr$5@uE8QfKt
zkjf9@SZ~mF)-~2^^xc%}toeTMaD(+_DKz6*Cn%AXz_PIhN+RoyHG)rKt#$yH%sTD>
zloZyJpV7@!)*)Kh-eh^xlrfEU<|Z`LSr@*5FoSg=8C)jo%1_|3SWj-kLpCerI|P`+
zdg2d*TvpluFmJI&525WgYv47w&0|?piY=d2kO%Vu*0=P^DrA*YYNv>Wk5c1mWj&_+
zbup`qrT`_ZG}?|VWfjpUHp*BV!ob~S?V~AGIcq~F3@TV_XwUv0Yr+SezRwD!*I6a&
z+gG4j#oBZmn$@g+x<zYP2E*|FfTba~wJc9MZ(hgx-V7-9tbMe*-@w}YAIL+NC=nyk
z$hvhE{cB<cQ?|F6#h`-}Evy(S-)d#~)}nupST|_d(#Eo10nB#R5;|GZ!LlEQN+)ae
z8bsE`3a1_JZk8DxVd-II()_HKrKLjrK33Q`{5@tx(ieI9S>I5C=n1Pb6LAi(d}&cX
z$g*lfkA_&k3?i0c*5V&QMp#Ak1B|j3G10Lx)<!P4rz}g_t{G>!()4_Sb=)4YOtOj_
zfjPxG@&JyeS*GVeW?1#~a+_t{J_gM>*6ePWKV$7LgXVMA>v8Dq3)YT!nA@|jehuQl
z9<GO5N47JSb~&*((*A=pyHfz}BwN^oa8I$9oCoK^E?I++T-iU=1JjNDOFcqzXTM7e
z01tKwoj34gzuXH)UhFq%2j81rMfK{Z*}DVK=EJV6fp=fFH5({?>{>Sj=+FMd65*a<
z?;i$tmVJXx^qph(<-*`RJC-t#7uc;qAOUQ45HK&Yjp(f%$X>;PK@j^5J^~D8Yw0Qo
zVV|TL&P!~U-{2^eUDAxMgt064fP}NZb3iN+>@GStaGCvU5L6=BQI~;og?&T-yD0V#
zz97-;%rJn(u#ZtaTP*tzT8~|2|4|4M$2R{D<Qkj#HiEd$PWlX(H`wj8M-<PFR6&@)
zK1pY?64|NrEKg!Dpfk|P>^J`Z{$uCRTPBrVPMPkTZ1*S_q_K~@1(MDVaD(>@wjnKu
zGuixna9QjhPJzp2f3XJ!IqX$3aJlR}4ahC_Bt3#|v+wc{XCB-0D~wV;Tm3gWR=|GD
zK&K1Yc2w$7#NOlygFEcEX@9+#{o4m1CG2G<K}y-twAoh1j!eKn-es>!fI&IC@hUJY
z*nRFmxyN3Tj6U3FyQF}tWS^q@y^6h;=HAupgiVO7hTU!q^9O8&C4#7BFLMH^V}E-G
zVD;>esOY+Zz3l-UJ!Jn%Umk5_ryByZiS180vS#)yJ%U=;jy@2!vX@ga>?3y9BDA%!
zW4D8AXCI|Hst$H_B+NV6M<}z<#Xd)~`)+pAR<!l7?Sm0nFT1rEZGG&OpTX`iTQUn_
zKig>-U{BchX^}m^HhvD2LH6cBm=Cc(T!Xe@c8e#jx)Jt1J~}qa-b!i7F}8#z1W(!i
z*MTz5-q;B;!Pe^$?j*b59T-fpZ_%P@n*BOmQZwv_+u>oB?e`Tl=h#1rAbiH|dLRCt
zvzG>dykM6W!_J;FYz7nu&H*<3IdZO0&94(D;SQp9=9ICZd6ILOb~sLP{F2b-!Wp6I
zvMcAOCxCY2*wY2=&Z)72xd-RTLUh`b(@OaQFU~LD0mYm1hc&#P<}7K2fe+^jO-g+^
zODurt$LaV82L7BcsZ{k0CzX;GXE`^jp>mF6OKF(%9MydIyTI|i3`YT+WlgZV$SJIa
zhd|EQ7z~0qhcBQlnBzpLk87MXIudl9)Aa}JZg8T$he|wWDdm0>INK;;lgRmm?v5nR
z#-HFenWLupU<#*>-hZi_!haCwO-^4aB1_}^Ld&akPAHXNXK*~Id?b^z;~_A!IQF!k
zn$7uo8U{HWZ%P{Gavr=1N4Gd(&M>&mNqPsEd7P_Mcb?CABMMvrC!!u)A*Xr}U`3qn
ziwO4)$DS53#hhW<h%4b#(I@&!IX)l2Lm4OU8NlvxEcU>zob!PkC>5NseQ<P-!}ma(
z_c@yxFsS5sY7ki!C!5v*)tpVwVNk<acnXdlaJuN{sO1zCK(mhHO)JHEj*$cg4V+|}
zRX*gb&VjIzGnkJ~H*qGdpxMmvpc70joH8~vTREn`fIQ+9(_P%g8KaC~J7*7F8XX*+
z3Xyek0(AiE;xuiAN;ju~zH-pRF>6J~dO64b23Q|wM=Ho;&KPAR`Z-%op!tO3|2q5)
zaJs16VUUxNhPEM&q6B1^v*JDUXoR!D6`G?QJ{^S~<4D8d_9=%K18$tNrwrT#C*dyy
zKgpT@6kt=F&X3`Jn$xfpm@}L-6AZyD=gBt^&T-ye36*D@@e+{doX)jy^n$aHPRZMI
zPaQ(X9JqVSz&UbVX#(lQz2*!@&fHJwa|$Q9W7oi);@0y3?ZW+z*7mMkivf6W<FY7g
z>&{(i33Cr_Tp^%6x#N@t_u?uKLdBc=620F~b5-Qlhg*{jFkf!V0vPyl*U_)y&s|A#
zjWb+tQwYy;o6aMobKH%zP&v<ySpx0?H<AaH0B-gM^x-1+)(_}=Aa{_90E4(q1JDfS
zT4lmt2=|jCP`SiS+YOaaZo>#v!nlQ01Rc(ujz+i<+~-~h;xf124{=6v<EZNI3O6PU
zTol*c9&ORwX#vb*xNBFzZ7i1?2y&I{mIci??q<44u5s7I0_-~X7zf-9?hs`;;<>4`
zA)3Jb;Tyz~$erE}gCuVDYfwq%hS80X!WFK9FqM0UF1MRpt0oB3xT*E9OXqg`LNkNw
zN2&Nsu88I#S=_i9c+ckQXvlN8i%VgU%QZ8{c;4bBQkLU3H<m7&JnnmRujF%;;ou6m
z{_jGwkn7KZu!#H8HelZ2N`26=Vs0`)mvC370Hu^GqHIMO*PJRe?s9*pcTPFi={fvW
za3`pw<{tO27HHn*rp%zNk}EO-SQS^b8Q!b8yAFWVaD5dJKHz@733j#IS;|D!aTn3D
zv!3fnze)pl@B&8ZAy-E;|3+@?T4*+L@1KHsGq?Q;9JO$tY=nna?gDzmKH|Q38zHrE
z-A52$JNNo?pmcCIpGL<zxetbb(#8Fq)-v5(gG*59;d0X9p_dy&kLEt^i*q24xlRli
z^mCUELFEazgjNg#T!VY?KFIxwrT|0S6;t4bxvCIwBitSIP#xtSrYXl5*OFGyPr2La
z;M+KNSu|88xL@QU>Phb2E^t%a$ur=lxs_DXKEqu^2Oej+>uF^($DRHHD$lq!-$3O#
zHz^6-e8H_c02O<iKUoOS!Db!JQ5<cyy$8<8rhW=-&Njtc5z-l(C$uCzYs0*cwsSV?
zH=*sk&C45MaKYy8UbF?+c$tF>w6VAdgCHA6I@A$tBcps|h|Q-T!uutg3tjLYYU6nf
zT$s)Fk6;jP(@d2)5jMw<BkIdG-5Vf`v^l&Kc2{hyC~q2Nld%pY+UA2WkQke?6d1(X
zeD@VJuiAY6GJc~tn~>+|(KVY=ngU$6IZQ<=@irj>7$n%dVF!|Evw8}cNjA~1!cnr#
zW11zT*c_rHY^u$hlL+aiP3YSgtTY?tN6<{Sd6$wa88&~dfiTlXL@SgmoA<wf+iaUK
zsz1)L`E?W8a%~b8;0n2AqoD=dZJS>hc;n^S;3ELI5p1G@;Gw{#<yCknwAoGv>5FVE
z--P!&HcRNqP;4{*|JZvEsH(27U-ay?%W0sL1DpaUMx#b!jWtFSqtO_R(U{mvEK#Ge
zq!^8f1t|g+><v)t6#)fN0TnAMDu^O>1w{q1_x^rA61@L^;`hDpj(6|(?i=Gd9DD6G
z*Q{&pz4lsj&UIjh-T|NE0l+-yQ|S&&$?&=QA&Nsj9#g^du+NG%kbcDH0;OmAc=1<-
zvV4A6f#Rso=41e~eT>XCJ?0a50hq^qDy~71<I^q-Vo&&3?m$AWPdu{}PWqf+1m~2`
zrLWO;+UFQ;KjSln!M(FS=f8qV=X{!SA$Z=$moEGZK9#ETMeu2o1fF?5_xKRy`^@|X
z#U-CMZNTiZ&&3(grNHMomy=g~wibcls!!-10I&HpqFbxb$DRgeMLsM1An3Z!r{4ou
z?6bNXiW@$yZh+ZMpTV4kZ~6T01M=HGhn*<y__UY`1@HRQ;Rf!WPvqC=y8Aw>L(x4C
zd~%Y&?4eJ!cEEh(lUD%>KK2>r3$agpjLT6x^|4O^&u2aZ-T}&UpS!ie?1j&nKY;nt
z$DQARS3YI=VES8sih+U?tXUtT7GQPd`ZLhlv^;7-)?$V$gRSf7V3=rqz{K$o>rd1y
z)Ov&I7h%@pQ^9kRb&Cp~ldTIF;F@9$VZzK*>!3*hhFhKdcu%uF;FLGrI_?NiW?0wL
zy*Sf~qbc|hS#R*;J=?m1?)^E|O-ve@YyFrC&a*D3=W@O^fho}ote@5cd4$z^7(Ezi
zeOVb?qO1jVP%N~1*8sCc)&hEaqpcI}gJ7|B3y&r*vHnyJT$WlNWPxs(wdf>j%dKk}
z-C1F+5(?=nt-f?qtg=?*;q}$l&uap>#@cT*P}W)l*MiwPYdrl@F;<n^)%Dg*To1-t
z&&wc)vl>1H>v-!`{y@tH>$kq>){WNIkI<H2Ek6=%iPqdl&}Eag3y)(YSwHm#%4Vz8
zAHXfvFb1QxTD|B=OtucEA2Y=oaTRo_*5j9;%QkDB0La^J^<eVV4r}`~0Mo3#?6aL#
zTO0)KvaVhWW_zuB_o24WdcQR=_gh;wg}ejSZM~t{L96o!=rXM3b70sZYfyEx9k#07
zA?S#8F;{t+)`~U&v#deP89i!^=Tn|-{lW~oW7Z$$pg3-QNDoMkwb@r7IAL8#4@j=H
z>5t%Y(z;hh?UYqI42w=%AI*j-XRNtx06b?M+8@C4)^TRgU9kG<q0&WbSVt6j)}NW}
zm~WMNEasBcdLA}hwhm+Jc7gS5Ll9iC21i1dtJXDTP`hRgyaUWat2>vkMb<HmL4MsD
z{3B|`*0q~Z+_3ij9+)?+uKe)bvUc}EaoakNoBF%f(LC*N&ziu+-hJyJ9e@w4A2$Ns
zLu(M7u#c>FuRz_$)?nrWJh3XwNqlOxOh@gRwK5a&pIdXzqxQmDhCYaw)@=^~d}WQ`
zD#70t)D^%9wvk+^2H4V`pa`@@4?|m!ttcO?gKb|jk#C}{N;}94v31P`N~kS?Gf|i=
zuNmY`vL!76aI&ppA$nqpZQ^1OOtqEs13|d0`Bk({vt2%qPM&T%pANbiwk0xH&$Oi!
zfMAyG=!Z~nw(ZD06mx6=jMdGxIjlgLXZxxHB+R$<I*r-_+sDW@QzL9snE@7QyL21m
zQMR3Y&KBCf{0tHn+0-E@qHQM_`d(~1#ogc%ThlhEEwz<t3hB#i+uEYG+?LC9z!kQ9
z8(6QjVV=gzWlIt0kkz(IYaw=xP1g{$wYIQq6zgoB++D}mE>1(S-Zs+*MXc>T4Q+9@
z-}&&x+v-Jt%LZE@a|<`xnsr5yV9V?X35mA$^-<eo`*c6LC&_k(nK_$nb2g&bVoT?7
z*{!zZndq!!+r6c*FU8h=D_E!6w)14dHrp@ngUfbXm>uLhY%!AoOta-iLy4WXhWo*K
zmu=`4blq;-W%`Ns*xsItVz2G3B(&|b8AqT<w~apll>Iip*|7b9ZOl4|J!rcd2_-UY
zky(&_$o6S>)DGJgPXx*lTiaa_lxgd^4Rl$yFWv^hQQLxOXqIhjI0ihA+2r+5_qfe!
zhrAqH4*f4DY=u01muu_M5p5@J3Ct!xWxK7ScG~808YpLMsVyPltgXjaz&vML&5-hW
z+q5zOUa*y^2F!~#Zw_jnEwCYg`L?ak0K8<o%O${NTS9qAFR*RkFDKlw^+!^)de@dt
zr~N(KGRAuD+f;uP4{SragW#cU1&<&-vJK(l^093^_jpfijd{xYscrK!v^}#`-2g$)
zZMTlV+84GcZoOXGjwgf5dV4;7WU=-y`3T3`_q7E1MtiI;+7j&NxUo&NdmMmao9yM5
z1DIs5k`MAN_9I+%CEIUpLoLPr^*EqxvrB<sw%wjE7MMHiK324)+1(#PiJkWQ<G^f}
zeW)91yY1aJqu67w#*Ci5_S-E$o^BtN!eO*`OMxy2?8!XNonfEV26Tt)gLrV`u)Ta8
z0FT&nnevcnA4{Kjmff5FkfZiHOlHfr$I*Ry%x>nI_PD*>CSc~+lX6izVQ*9!TIbr`
z8T~kEU$X(gQ}(lrXr8vO+Xo3}?9JJ&XYGZ-u;HA&{|I27w_oRi{DS?hp#WaA->w9e
z3hYJmpyxHap6l{L`&lnw7TG7~K>Bt2NuFsfwl8Xi;)Z=Ozg#!%Uqyi6mOZs6Fz?vk
zZ3t#}?cwu5e$VdF8pVD4FK!@zU^i|7%0v5EBg8(kw{`;avE4Ti3O=!~c?RH9`xm>Q
z#4~$D4FI3pi!&hMg?$3E8(!M4zYUaEc1Lq?@pp&^C?+^6S4CTZV<FGG20EtDNfP9E
zYdBO2cHDjhl!*?jKX`^XdN2bz)bYtWV1_w*R)!6e9FG~WnCw`v48SRl!ffa{)sfF1
z1_^g`qH}DTV>MF~r#pTd2c9z>-H!k`%aPs(1hXBVFmf=*k@XWK%ypE#hJl;s2$%+x
z`HtrNk}Pm^Dukd2$NJIW8R=+dMO&1^HWYLV9pmZJTjVg;g@kCw)!M*Z?07yNz$K3M
zd{CA;78ir{a>t$&bk+)oPhVKO(s7R=v{jC&z0o179na}yT<dUW^gqV&A!m*CjyjCl
z#5tDtM-lHZjseOBN7MZfyU|gJ%n}?QbFZD~=u!X)NsgV5fw|e?GX`y291XqEw$<@F
zJ;=$97k_|fisSioSd{7rZVoQn9MkDM+U{_C0P-D<msbExa}00*WvAm)hMRXeX7vTL
z-Hsbefw{-wWDewB$MlM@VV`3@pNVwG6sEfDcVzztE(aVt=vB#Z6uE%lkfY@S5FB>A
zuZLzw953m>%yb0N9i8PcThIkZ9pjnZ_tf#nb_fdbeVfkrFyG_!Tu$<xGzD$*d<QV^
zBEq*7{p<^UJJB7z*!K~0SeN+@X$Q>JzFYSLxW>1BJ}}q%{>V+tI^P(6En<9!%>v4L
z-{xOHiCEu7{Lsevw&}-i^=*;{E*pF&aNWAmw_96aCiu=~UnlzJ^AOM`-;bJr=Vsp@
zhO=9J13m+Am+uyy_u1_mYyn-S?;kv(ljW-`2If)Us6G&z?VHL))G^<-KSGz|zF|FK
zSdMRHI&V+-RxALQT;DDmL4MM=-4M{7^6j$=x}5e+ypGx#U*Dg>^Q>>V#vnN78}|rY
z&ilSx3E&0aK~+I_(Kn+9RLb*hxesmmzLkoh{AJ(gR<JJcJ(>z;fqt1hF&yMKmLL6K
zzn?~dZld4kq2L+i*P%P;7W%zlcxI7bIM?jae&Kp_@?yWvEz!2buSH3y)-QxR;pKjN
z`R!Qg_eTb}#QDYAAR*rG<O5i{!7s!UZ5#boOagg=-$Q;^68+X3Lv52^+IP@1$?q(E
zT|4}KWi&p`Z|DrP?ewen9*PV<mz`jC$Zt?56o>t;o&w4dzq?PsCCl&0DfXvd8*U$u
z`Sq;?UC#T}T@D2=_yux1e$j6&;{kbo8%99TCBLIgPrvN<t`Wt3zj}<0KlJ;#BQPKN
zrQAe^Joc*?jKO*0_Xp?XXMSh+lt1?io`bd*eg`U`_R=qZEXe(x<2a2@aK6k3W`J{V
zCnyo<ObkO?kn>D`6v58&1+aah)AxI*8|oa%bx4@A*(ns0oKg@>ne2?`FTqT4Mm+$R
zsm|ejASm3qvm<KLoT-a}GQ-(qIml-^b<C!i<vhuZg4s^<CD6@rVvfV~<Xl%5nDd+;
zy#;IMJJW}wEyCHQ3Ji;Mw(SLig-*i?v@LQ@pdWgrvuzOCRylLH5?|vSR0D>sb;|Ff
zEymf8wOHqO-228kJ9FZUcjhs1VuQ2CK*-zZ+{66&1ZVkW046$5?uCMzobF8BOLCr1
zMzPs>@E0)K;*1!EF4*ccy91cwTz?p1_c-r!$+6d2={(5yIR{pR^6AcPoUivgYvurW
zz!|`2;-E8A1@Msb(6``n*m-Xq+KxCU9Yfm*=Ru~{<T}5hGxdUV0FyB;I)_w;W_ixe
z+&bqwO*hdKmz*^|hc1_$Z}Xf+fisf{zgL_;1c3aibH@gdUvuuO0`fv<!(IRuIbYEk
zcinmW8Ze8UxxYh+>2D2rC}0HsS3bW0>b(1eFL2dUybqK@*`YyFHqR&pOI6PSI8nNM
z5QHI8`T`JzO1oKvNu&6gnIr{~V6wCnY0g@tl*J|dCMk9k6it$bagV=Q8oLKZY?12l
zf!Qj#EQO-UQtTw~Op#JTfRZY`^aQ~+=_!ltlAVj%9nuQU>1mQTYdfVS^?<ocIy(!s
z-O_0C+#`+o5d<01Ts)`RRjC|zuR)^KEtnfDIxsPIqS&+&bRnX71PDUKqWwS#6FJP6
zn<VB<q4HuDiz%Y#Cm@(A^62>t7uoy{P7}fx7EKq2S(_m?kl9Sp1KuMoTAVouqmPR^
zr;IvnqMY6leHMySJCaVDA*Zo6S3dq8)Qyy7MwQ~_qnBie!2b{GWZ?SY+9Igmr1oN<
zesp{-Bs87569PI;Wl~G`QO`j%Fo3y-BVX__9KEmsa6+Z&Ct%=YsVa|8ZI*hSKu_+H
zYFGYiSS{PQ+I=be)r9C*@^20p=dXOiXKuREt`a!UP`pD?TcU5pGcZf_Ll}furmxTB
zwdMMgbg5k|8+#EbSIe&8S&y4#r*=TwgR)2)$3#-L{5Plty8S_)(ImHJ%p#lNmPBve
ze7Ak0P>Xi^dK55Mx}EI>F00(m)P)kO-JHxBU*pz25^ZbU8gpU0&Mj;(jEZsVL)Y|r
zx1%8-k9DiVGgEPHUo1t}B)Sd#9hfO@6BnY`<u<)5m>qEYmOj5Mx7D3Ne#-5b8`@60
zb=m?hXWXt`K<%uXxhABabGr^doqE%4OgmuSa(j@A+HK@H0rQSq=lQ7Jb-NM^dH39g
zH-`=P-MTb`*avQJR|3I9w_{7d?2+5MH0+7n_v<13soPE_eLr*i=01SW-S*Hm{laZm
zQxLp#oBs*~uiS!bfwjMT#C{YL-1jg}AK?BW)0RTqrB>h)>K?^$2y=fP0=h}=d(EJm
z?7mt-ZH9Z{Efh1|uMC5kv)q>*$5737FVA)V9QW`GV7A;na0k29y$nC=Yu#&{0Ko?L
z+n%r?(cLr(_NBQ0Pz=no?#(_x+d21-dBX34`v*%=Ty$^tJ&H^2>61Zl+5P?ZAn1wv
z#`}0|{5@t{Aa9CCau>*(>Jfb%#R88>j8iQ3*!(%PUggow0${91F3;$0@+i&&msF3T
zeWB8B4=otv2R(Y$1@NfHQO1W)dQ@aw<bub1x)ZN>oTG>OhR2OT5PRQa>U8Mx%wx`S
z_L67IQ>cY`&SsoxlIQltAeiillTJ{{GY>D3I@R+4_Y&crYx&)p=DA}ex^BAX-W#aR
z@N69ql$oCQ??abao}wkRp6&VFW3<ijy!#&L=6XhV2D5pdMVCQ0-*aasfXh8MI3RC@
zXKpSCR(dvKGRrE@&bQE!t34BZfVswV&kJxt2G2k!zs_?OzQM@g*_?u6z2}ELffDQK
zPB&znr!xkI#d}s_2J!~a?%ZN;^c?dNDkXRZ=%C;x&%=v=ndDi>2-s%NR_yC7p1ZiK
z+Un^&6-BaVYkpBvJg+e9p6cn#Jhg3}(O-khcF#%NJnr!P>SqW_^UR^Iey8WCmEf|=
zv+WrGcY7u<({_*N&ykRq<vC|PEXws%CV=&M&uFHB6?i^=8wwVCdiDY9d!FzA2H-Q#
zRUN?kxo6iiz<lAkq%p`}dKNSP`ITqdcwqWluB3qV6w6B&piH&MbUlPy%C!T^G|Rj3
z;5psmU?%tsOAAhOvn<*#P-(Vh+gvc4W7$mq<6KK>XVA^F4A7%C-=gHBSYr8=Nj^(0
zotL1t%yLP9%W_L#TL4#BW?u!Dm6o^p6A-H`qnYWx+Op{tFxOh{(s!`V@?IPWVk~(~
za9VG<!z8U(i}W-4CC*Z*2$=Dfru;*28!SzZfM>F0rx&bEu_$z4Y`6T(;~+aMZY&O3
zLi>SBhGpv+U>>$)@|4>V%aMAh<ywji;Ca&0BoUaWEy?Rae#SD6ujpmV=y#z@fn^le
zaaSxoZlkzrxqc5Q*DSiZ=$=B$w|wo3ELn$8T(?Z-2cX!}wGebSEDgtl;HD+G3<TY>
zq_%|;w=JnLsNJztzK1@$Yx&L}T<%$3&<p**(sm#S9$G9_F#wM&A2Cn+vE^6Bzn@sz
z)qs6ZEsr&htz{awKF=-Z{2}OtB`X`uURv67mHf)`s3AJb-^+pVKpI1rIG_Z0T{sE4
zKrfvH=|Ns|ve7oxYfOCr!@WY?K`_lLmQmm7UfKjOo9UJOGY8!3*UKnodws$OY>rnB
zx2H?JrqSWG%uC@1ZMj!gE@~^h&fS0wE4?~w0MAukH@E^@?G??@T;p}(66n@?J=uj$
zUg!1e479~~bzXyFz1R8z=o0IdQiQIH^J>aXZoF4Ar|k`1ix&eW!E5{H;F;*v`YLLh
zysq)fn&efEZJWI&`@^CwUMm@B-|BTV26`rY-KXC&#jAcU+ETsxGN`)EE2Iv9+r2Em
zqPD|p1xGW@tLN8HaHm&#O#pX!wRsl=nO=F^lV^Et7>BlOuLns`{+O4Ilg<gR5q?0)
z_3F!xyy4X@4xM$=Yj}MW&%EaGSn6}HFYZCm3$GQuA>pN0xvl`d@~TVsm%n#XMd&%f
zdwh2&AK;x>2(f|Q?U~gT<oz9wv;=#X<@$D__lb^Z3-LbD2+Tsgd({S)Fz>(xAfM!2
ze-&y|yqjF%FnU+90~qdIX8`D?c?Y!z>*?O3KSbLM@7rg=dZxE>1#Ppu`}+Vm+q-%Y
zESlqeo&7S`dt)?e^SrN32G9B4Ww^sz;C-qKfDzv7c<dq4d-;4QzuLPYmriTE4|D=>
zt+$~+YU{jzn}^|u@oqB)tk-)#s0s2o?=IO88}B_?f!Gb+?{e?C(fcL6d<ot|m^_;3
z-JTn$#nsObfPEXQr!)IHp?dx~a0#t(a1bP%tm*3s33)X`v(PUu>OP~-;bq;NjR4N9
zH<vq^`Sot__X8HxYrwBeWWA4ef>~m{T2CQ;PrY5`fwH&Wg_4tc^}_jvU#-{hOE6pA
zpnEa%i}8Q(PKLREh~qC|56NRhWau&*lo;k;4xC3G<H~GQ^@U*n+ea5c>Mw0;0=5&R
z%SEUKNUN6uVUjez9JoxDhB0$+s#G=ueC9|a+JVtrslyOhx=1<{118bZXA;O4OB0z%
zv|9R_KD{+k1k;(;N(MSo)=AYHfM<dfwvg6Hr}$W;N;O8JwoRJDw|l!3RfrziAq5OZ
z?SNF5(dUEG@*?oekfN?Y-XUp!4%$vg)tDidD_!@6`6s0-Qy}4#B&I?_o-~TlntZ8w
zZxolL>bW4lETuPsf(6nErlMbwM!yfOuS&5G(RNMRTNXSEr8`MzyCdZr!1JzT=PQ3t
zdY`_X`_km?Ab%h|W=h=)X)O<iyp-mBj_!FS4cZ9;e=(Kc;R&M8aR38E`C_mR6wkf`
zW{~)XT!O`?+*nN%8Qg`2h^w(c2^F9A0qZc)eFp5CBt~&2oh&+a0p=93fN{sEV%1})
z8!j3*K`~9_EI~0{?B+Z-Lj*TQZKjyS6~Zjx^aHcmLaGhcbHpe=pv)C5nG7&b{K2f{
z`C@f1NLU~yHHDrLVqG<$M2f2`pi-2$z@KGXC<^FcS|nCA1>H)4Bxy{3;^qnH5+_zJ
zf+_LhmoyM;5Gg8(jiM0`BPNTUFHuVo4e7N=6`gv5%QjK<Cy3oHRxtHppXfLgZRsL@
zF);Uw3v_555Y<P6{Gdqd1kEzUw-Z2cNc_AL($9!~%w0Gu0vL@tC!%@y>b&@X{`Nef
zzXQ6<qUz@$C=hdIgZzpZz*L~CBCs#VRzx*|@`a)gzbQpxa9Oln7qb}1^Ou)S06~ac
zhX=F5<ukP*Z;rgNHGolavKQnnlLrligmv-=Cfmly^<z=2moGPf60!2xFHwt=Ck3GA
z<K=l5K#(fexC9B?<hSUk-7df252Njn`&~sXP2Oim+fKRZTadn6uEP0$k35XNh`n+u
zhiadkJ{P*A%j-sf^?rHx6_6j7r5q@6M!r`aT=M0w7oe?B-aiV!+wv>ML>|coJy^e#
zoA(33M5V$?^mT~xy$--oWmb38!jxJCkT6O4o%`|0%Ed~sVTuyh9<}+(85OJ-D7QIZ
zL@2fw;1a3qAAllC>Bb<@LZw?5^xz_8*soB2v69G{VTq!<1};mLddz5Erqq9q0?riX
z(ydT>mE+T+)MaMDMr9fkaknbne?pO_q;W@^u7qv``4MF@pVl0uA0O|t%J*eKa7k(D
z0`lw14}L%?R<duwh8v1ahvKHvk6Wu-O63u-@3zw01U>I44FbUBuJUzHkiS&kZ3hXj
zlq;`*>8~E<-hP7Gf*;ZVbzU%72dYV%K@g<2<#F6#^~W@HPl%e&(*~hx!y;gYsSf@u
z%p~=Abrh4;cQ}PkQOo$FZK^tjewc7Il-XYM)X!%CWxjg<5NZq5eH+0gLd|*w){$yI
z#s#9(7yLjiRCmV$Gg@uW%*e%RlOMokiRu#p!<MSOc|>NJ+A18nELUw#a9N=~W_UGL
zol^vqI5ndlYVm5r_GsIn*7g9ijreq<NKkk27)7EQ&2-*PYFIqf-K-XJhqXm5!>!|1
zbs+;t$*MUIVpCKbhd))#jsUZ5YR|p^ZdVI_1DAAlq6Y-+S05&V;DFkMNoEJt`SVa@
zsH1;IaY${<wZvidC6hIe;7>JR{4&+wKL+_xwf1$?veg^aAmNzWhG|~MRofj%$WhPd
zqIN<}+z0Yp^-wpcdr}=U1ooX$CyxQ^D{3@DDp%EZAAs34)yUO!p&GRfrWC2ZGtqWk
z_3{Ag8>$=0Z>rOyfO$(*xYoU`dhp4*qq<xI=3O--4q{)aGnu61uXUIX%_e9W^ri-A
z4I{uhP}>uVwjk|AV~_`HhILRdM7vZCn4wzKGq4WRDt(FCB(23+&`s9X*9OliTGQW9
zo2u2ZfFMGfYXz4`?G%p#Mro6{cwDH-^cFAD8h(jdv=&33^I~ldqnAsx)P+!RnO5!~
zSTEP!@jz{bX5_wirRLiMVpnN58=`HsHu45Kd5z|~3Uq5VV-8SuX<K?=P<LxX#)IyV
z_TgSAe_lJzeB%q+crHF(Xti=6cC~(KEST-lKQx2cUcG%9fM@kL>DsuUzrP6NMf#7b
zK(jk~OETyl>pLZb*%Q6TD%x)NA`=9Y4BZ&fo^41?hxBN}4sO>r7&hpEl4{s^7-IJr
zx-((%tf42*#@sQeYrr$ac$Pt%*~X__5G*x5^oA1g#`^RYZ!&&Y0VoHI?YY`KX#A`-
z=q8&++W`zWDa?|dW{Px2ZMvxg16?ys9v?y7S*CW(VV+|eIvl{crom64b%g0=C@>>U
zcbS3`WxAt-o{LQQ=@_VMYTyfb%S?syF=ES2)2f1Qg=tn4iq)nuW{|HlZ5W2OSkusr
zsBJK1M?>8N(}$f=OEekBpe@O?X9bvTHucm)`WDj{^jvQ>o#U&WVNxrhIBYWHq6@N2
z4V-8@X8LU>B;=U-aebL<YTyqgPMLoF3e3)$dh+?qGu?g;lmK%b=063QN1s4#qWK59
z)<ew$Cc=hrbKi-;oNk`a9N5|Bga#m=Yc?qWE--KA*Eh<1<`tKI`0w@QXk0s1aRr}F
zPrF0k&PO?)b$Rp=?z^s~XQ|sFH_&!}=Of(rh}{Ty&kIa}=v65O@NfH$g4EtQR$Tl1
z&bVaXygIn{tKAR-`CYqh(4v1GZ(IkOm`nBR^vSSw<kVKUANBQeaQMx#6!)V$e*vC<
zST}?J*s&kre%#kgL>M2;9H<FW8#>1Vq)r^>KxuS!5Kfh5@W@BF<hTvsG|5y0wdvBx
zg(wzCr<(&MLTWGs%p;|p{b6UE<QoR1HcP`9a@ipb&Votl(mqbsnNnq>@c-E<3oGL$
zT3q4pA1oH%?g76g;sCwxOU0I0$XX`)6hP0_qFyfm*NB+{z*sS^2qNP|t)t)`FYfZJ
z*e0>u3$-K>(iz2OQ85C=7O{~@p4&tik2G!<i>gAx4lyYdgR@7xHyqOUil3P<wNH#X
z1<VX#kA#FnqOC6oj*2LLH?zf~V^I8<_=YQ_<Dyz+pqvs%nDBO5)Lnzx88M4la2G{Q
zZ`ATc7#A7&;@heqza%c70QqI%k^!-WqFp_(E)tEI8F@?8-Ur})@n|6k9*BW^Kn|Zf
zAC_lgb{)|9%QHBi-80_g!IuZ7mk%T~;{Qu&WejLvNgnJQf6;)44kw5a(_lw{XkQn!
zfud(RgawJBttf&;R~y<U3W>hh5Rt$QYN%MoRdtwX7mv0{!bV@^WRZFc%%+G_9Uyb6
zu<(l*E}B1rylG<idq7zrX1jncLS!VOEm9m#L)$7b`56SQ5nmLW{#4Q{zcQ5X6g~`g
zb$0Nr?b3|Nhh4+UKwP&b+@W`G9SKf7(yoC+&w=zi^jbd*8h)FZ31+=_P62+OmW`oM
z-@4;~-%mOTp5HB>him^V&L;z2r2=Q5(f}L=70w3Lush8l>z9W^03WrMAH&~ze+YPx
z)ae_L1xp#sw4Nw!{)Q$=QLQ0wy7UE;;%7+nDud@tY3utSh?I6PSvg8tau*6Ol-llu
z2GLTJu>dZW)=|m|>6jae)zT^%<m;qMJwP5St>tedWlB+;XS1Y{o1y<vDdH>yWlIg2
zvwTcC_A6>9rTQO({G8On51o`R)#QU;Bt7D9?mm!u9s%7`sm4X1ypWzX2D4Yv2Q9#Q
zg6L2MT%twjA^?-bl?8w8G`$WupyO7lY+cYKOSaKaHAVW-2>nx~S~j$8lLV6mw@WiU
z0o)<IS_VdGQa|pZ4@f`hAo-x=b`azlQawHwhot$;FgPsb9sux&WM<4ZQ>tw(v8{*+
z$Cso?I-V{|zjsHiKq}&K`kT@rdg5+LAG3oWOHDb$KarB?xCjt8w?K(NQK21Bg2X_c
z{+KHEGxIlG^yv?=(?srRV9pnH)}vS;_IE+gMu?buD3*y9%OHKZ*hN3}3bC0vSu4c^
zzJPJUjgw-$h-n47twMVYV6xb?6M|BN&l!-XicD@2_6lnOfcr#a?)=h4IQ@?MMQh4C
zDvo^**4bj(hafm6#(WC<j*H>kzMK>0Y_y#heRrbmf>_9h^r9H|0&RKXllRd}MPkEX
zv|Se~WY850do2KOh*{sDxG4s5e|1ZYYXX$p!hRgxb4NIs)^t~FS^|~siH@9g?u&5&
zs67y~YohI;u!cjkM<T!EjD<KH0K=XL{o4RO6>FH1_e|WSEA6?c*arkJM7>0CnIezA
z1H&R@&oHztkx%<WrPXpgb=e>{o{wU$95@2NQ*sI&9yjF0BLSSCG!6mJg-Q{3wsA`I
zC(tELiOUDiOr>={0M9Fr`cPe^QwYePDUtY1l#=-=OSLc_c3O>mn`mk?uEQ_lXa8aN
zB{gLkh_0wX;b32+suv*hraE&RSlm_j^3>BKwa*Vw`KdaxGHS2Xc<x<-v;`mN{$y{t
z!#!e`aPBv|eNzZYJ&NhZ>Ghb8Q|~dG(K_gnKg=C0SH*S2z3E{0YsL-SkBs#K&rx^y
zg!@Zr>9A&k6vA03Oe)9d)g-Agy)`qX6y_Gql6um+6)DZRidvME-V1HZr7DbRtdQ38
zo4a0;=~jr9v`>H;Cv~NVWV6)eDRkK)o%;c-w@Qf%K%Oi`y##rRq#B_~s<e(Cl5NuF
z-QcoaS~C_XJESZFYH8AzERgS%lDP`lCH=7ubi1Ye@4<SH)aM(>+bfM`%H%#Nh90_f
z$-rOi*e{Kv&-j2er74Po(rpPvhV;!u@H`|XO@-LQ((wggc0>vZ1Ta&YeF$_}(%{no
z9+mDhT_#(q%go8sQiY}Hw=>dvebB{cCI8A0bWTd2#4(k2tOUUY>6cAFxhkbh0_$s%
z&q$yYN?YfFyhxfxuitg4*-&5>OA9K2%MHnuvCW&(KyKILMdt5dmL!^S{@5Zyn3a$$
zlISl_6}4vqGflK-R@ZLPq%Ta_C;YjiKOk;h2i+mjfbNe>F-t=2n5gv~2u_PV3@Tj`
zb!I~|fBCJkMnLi3t1T^!5_`s>SSVKP0O=x;Nk-AaO8?(tvGyzIxJ0}+19~hK--Uo|
znb>^}$}JbZc3`d$)$o18WE1%rgsc(`MuKj&@M3P%8u8o?g0<p%X5p+8Q{Dz<j7Z1_
z=6d114VbZ_-gVUC#IJ8bP`uc|M5GO3WDwdmiZmnoYqR)zAZlsiw`6eHDI~ga4~T$3
zXnjx&<oWpwF^#e7Lt^lkAjlD)20;1=(V5HaT#>XFwUeUVUeH|>U$lgod7=#W)A?dL
zJvEoajfp5Oi$V0U7l@Fr&~`;s3<TX(@!|+nx+YQvLcv0Dd<eJ{i5R+nuZxyt!K_#q
z&H(d<Xh4VdP4Vm?+HQ$QTTna_eYuc*EFLC6-6vuVAE2iqg}#z!V%Q4+pNp5Lfbv2d
z{tCrQ@!MjwO_cA{M`wk|qc~GelONs&-E?{Pcd&21e4{c@7RZ*Hs4bCK(QmU<e*6ar
z*2+tlK&5qZ5m(3wau0@466N)Gftf0=V8ZD(*@y1Fy>eDAOxY)oYYf)u@~bt#%#ycP
zL2*<bG69-p%ej}K(lI%`H!zROI|rdHM-Fa|wiEJo{uoBCte*#6PRfNGoKy05(}8kY
z_U;W`&dABGV0~7;!{5|BCuc1K%6a)hYjoBHIr0L?FUps9fmxm$!I%89TqX&c706NC
zH(rrDF!}tdJiaX?6v-i64PBShOlT{XjmLm_LynIF`AvD@JrsB3k9woHE8qVXtnbM;
z7$<lk58;V<f2EQU1QV3Ecp4@^8Q&X4pfYeg+JclAo_q*arZbows#L8A<-?SoU7`FG
z<*VnAH&rRx2I=8SB|d!9lupd#o35k;p>2)Qy&d#SP?~0dAXQly2=YBjB6GM7DV28u
zcwJe_REd}B%NtN4RQtFgm`%}kGN~e58+sThbG32j!8$@K-UFVI+V4TAMQJ{CHZIhb
zF+9IW>v0D>7i+sKK;5O<XI&v^xz^7eJXdP(yHgi!^dbP)YCZhGbDieOtyhd@xemJZ
zS{?pgO`JA{dy9B&bRLQg+NN=Tt)VSX=m_sJg&BHXPq;&1w>@^;cb_*DYWA4X6gu~m
zS_7xoqqevXxOX262AZOA|Gn}P?gv%j@t&WnGJEEiXl7H4C_IYRU%!gNb>!CtFlkg3
z8umvzW0OJB%6HlE(lUPXr%Kz0!-R0DYDGwzCiU8mV!E`u7`o4pBv072K$^%8XM{AC
zZ+4{ApA%7(<jSXep=7%T&he6MH&}0$S~KdsO&Z9x@@}bfFp2}x32w47rS#@tmLsL?
zg^FjSBYjZIm%Q#nm+R6u4*`5Am176^i)^l5W{7MC373fbQ%iG29#sQiy7ci}u$>{r
zehAV9(!gSnMo6`I!ZlKA-WWxcw7vmEE|=Q#B;X2Z9=|y2CI3)xkCj$z0YRMP!nI$#
z6v$x17HM%S)V4}LGB+z(n*R*I-BL3q1niMIGY)!4iswh-u#{94N}P}m(1VsMZTcL{
zE=UjKQM)KTV|r7bG>6Fo`BJyO;IdBSGr1;49J<TLLHN<}8Y_mK2WFgb<rXGhq_hHX
zgNQGOVx#Cg8HQzu3S7Ql5G(3~JX)^C80lhp*)M2YB9F?3gr#x|1H>+qKdcYKmdktF
zplyYm!&I7;@)jQ2TqO@436#~cS3}shMs^E_x@+Y`hE}F2)2pFvx^nv<iW$nM{IJec
z_VFO$EG35i$=Qkze_(EoV&XhJSE;)Pz<J7WrW(&zDi#B{K$*(~_Xy>^?hqTPROO-~
zSWD|o+qJ_#L2Rsckq7=0w1-@ZCuz1Skg!Et{|YvwYI8RNWxLjg`=B)KOMbz3X&0F4
z|4>`H5tvi-a}yybMlY2EFkSDPj@m(e`{__3M?VxN3`#z%g~Hbz3~z{6JD}tpQPBu<
z9tg_{bo3KZmM)|a`Hzc#<uqAbzJR>up2_HsHXk@}|3%&vh;BQB8I4~y`3*AKeYG7d
z+P_6F;8z7!Fz*oB0ld3+?*pDaJ~!doGncWtUeBKb^V{B=0qH$}XTSQ4;^ExE5e;zv
zLv~#V|K$s=Qb+Vj1kRY*=K&wvpf#w1r8_mzJW&ea2Ps54z=d0=q;XFbCRP6yL@`pI
z1Hey|k{K&XmX0%+l_p(igSLH=ITpY}(hDbwY$<`gb5iQcec^d2qX@ME{OCAp#nSNR
zu=9b`CKGfoq}ooj1tNe1x-bzw;;#jY#lkahE&Sg`KeT+nXYki8dUWw4snJ*{@mLyH
z9bBGCA2$Zi=Tf^gkiU|;^T3V2c*$SX2^2T{fEgr`&w*2j_<j-ug^I$bK$#`VZU^Jp
zqF;H`){9m@p|(xPmvw)RVy4j3mv&N=XR`7s5qcR6Pm5N5=#4YN`U{B83M=DwSHy%b
zfO%D9)<vyIxE_aE*TwvjR0I*g?eQ(q-wR#)L_BT-?oY*FI#wsiOI)E=xO|a5&6)C?
z-(lix`J;J|Fh|}DtNvW41#)S1PdXS3M)##~E^i-5W2QjlL#gg6aCjvBLI=!aX~?n?
zqu(A{Vswic5IIG>_y}yLiY8pp&Ji9*K|WWcbAL2XEIb8Zv>3Dy<co!Q7-~yIBlgl#
z(VLFiwPG5N->eh&+JGQNoZ=8Cifj{5Hi?wSsBIG!7~R`0J`oVRPmF#DF6m;+4D?W@
zsG<XTmQcB6IW4~Am-dX<cn8dIUXaf8b0U_%3vymmN<!NO5j6~S7sb&4bYh;!%LRG9
zc$?4sC2^m@y1QcMP}qJ?oZuSuz9`_D<AE5m8FUXttBL?V7Bv`acq&#-fnm=?pF5}p
z%9h5^EJ*gQ36#ZhA;Y=r<R;8I+adR_i?&>OiUGh2vhO3H+>py~ANN4c`3h|><Q12I
z8LaeL3SH(Yu5H0{o$^i_)V3=Tr-7NNtSyGtmy}Vdz<i{%C=bmhtL-^g%~1zFK`m14
zv>YleRiAf)wX0P%1i&cmA|oq{v?O|xqqSo^?66qtsDN&bwvM5#b=or~#>8kv^o+!6
ziJTBNXr2r_C25<wL5a=U^&#lUt=ge*D3PLlR~ZDUTER!qY`eDq0pz7=2fqPur*?@?
z@ovq@_kEAH#|FB+T2@~G4`^kMg5a>G?+EEfH18hJB~x2H1?0!HQ=9*q<36j(1z#)g
z2VnQPLdRBXS1*vaIsYvnUu>BM722-moBL(zYLK?OAc1T9<U&w=HDCkO?J$I^!><#|
zK!tAxe~i|Sc~v2+lW7Scojn<-?xG6;X4jwdz@eLQANr_!&Jb|!G4={td$sk2ir<d3
zfKTtkMS%3VFL2-Y@ibue>pT~HzPo)59Qtpf+5>9xyFYO865M~^w=Lj<!rlVr;4bxX
z|ATWqT8AX^F&esQHQ>X3i3eo3jx+6#u{U7jPxttt`T5c_-2d`k9l%FT>x%n7YPSS@
zg0!JC%m|gTI)F!-bQZg;k~jFR<k|p~zj6XhE0$+MPL1qxQ1pE%9xUoF;p(FKWPZw8
zUM$3Ymo5)L*keB3us!p)<G%kQI$;O=nh8aJ?9PqxPdA3+{<oi}fy3x-@8UY{?szB>
zEY)DheVWvj`3cjd;SEq*ApKAc+?Pq=+|I6(M#Z3(AbHG(TFFwcY5=B4nT))rN&%~&
z!8U2l`w)^YE#eCKh%~$tFi%J$2BR%k`tEaJUY2UUMB8F9qA3(vEf#WXohT~SgV;?X
zfL^^M(KHGKo5kSSupvz}dk!w=MU6YK1uuF9kS~yf+W;6LpXEM1Ql8iYeY9N8_Calh
zd}R*ESIV8@ktw`R&VvnFy!<h@Hb>+`dx4TE4|)d#S#oF~YRBa=*I-zVZ06f>LJnOC
z%wl=}83>xGe3J?#VwCzm0LCdPS3!`VbX<(KM5V`20F#sj@R9sEVwp%zRx9iu`IjFt
zTd5odn@=e()&icVnCWb~sU$vxCAXB~$}o0<dVMK)g{l>tvQA7^hYlL16I0ZoeSU**
zHIknEIqIgX7>)VrAm*M$s&%>pxJdnZJ5)KKit^x@rA~PSE+^G$^d+BD$8(pQr#?Rc
z%mVfJcoc<dgO)JwhHAn>MZ2wj5DLv^YG+LVF4DTfCyrgg!Zg%YX>FOkw_dBq?9v2H
zq(k{stwu$l?9$rMi?&yr>j#zgYs(se%SA1MryH(l+fo56)<T)^dQ00*XYMnt&99LD
zQghD$mmqyIXN&22{{kpDSMR}tkqh+qMuI#_??->)3Vi|3qpa4aUj&zR`o6Ac+n|4M
z0E$HYRDMVf=x_4tct{^a4_l`G0=Ky*_3cN2^%?zu61Sq>X#-}SzIr;^F6-~*LC{rw
zcY65m=||>)*+YHCS0H$<-}wT90t~K9RtPqvhk<9Pp(isRCL4w^O)1>4>M@GhhFb{$
zZZ-VIvs-%&*>6G5Tti`N2s&+8&j|P>!>U>kRA>nMg<W81&*kx5LyMB7oS_NR3?3Wi
zargPs@C(lgOfatHav{igh#`Rx<0Ga8&oaIj0lGEDo+XpFamG)OkYfCJJLq;Ai*5jO
zk1?1DP=}3c&OzNQ<B)2o9W%by1y8|Q<HVKVQea#)0lHi_?k$71JH~gCL3iI+zd8sW
z8JjUP=c%z_AlhCS^$xW8oBZjb4m7zlaz4>iE&(>2H6QJXzRow-WVaTW`-P+Jnt4+(
z2(FvW+=|>ZH&}?;9dlJ2OTZ6AOGnYWlUxkkk<4=$M&E6u%g6NIN4q4@!MMz22`7da
zmr>uME#76#aOj!nGK^lMEiPFt08DY&!K9d7E{%9Xaleal8gyAMvsa^b%H@4-WiPmN
zWL9Ioi)Rvm1uok@go4*xs@*^>)O9bH@l#ygFGIoUuHGKdWwz^?wXl7@>n~iJM7j2>
z3zQA6vpFLsx|Ugh+Gf}JwP4C_*KYL36}tLNMeTuW!BDh4bKT?wFu2UR3Q#b#%*^^I
zW|Z-aGk`b#_a9LP*B`_uB?~ZtZIVu3d|T4VI!U&aRedHORduqnjOzVGFWmUK>7V1t
zmS+j0Y7t18mmPZ5dw&%0{WSeNH#7xFs(vqTR!Z(_xitJllU&|IHhQY2tAk{n>>{gL
zb(>Kq8!W2#qvmFv?CYg>bJyt<{re@?G+t#_Z@oLLSL8B^-U5fOq94br>Uthb6!~Kx
zeNQh!N8>6lm8`1$7UoU4me5BMuIOh!gHEf<+Vo2*kuKQn$2c<xS4npDt*K`4(5GR4
ztmvCf1YWc#qbRb|p^rmNk>B#w?=%ZEuEu1AszI;pz>R)5d<u#@Pnh&Wu@RJWBtLz?
zF*c+fXG5fL>ig&LE?SuNr%nLnmGYMAH90{8PH&vxQsiZ#oPI~i-8$i-=g$)<a;A7&
zuUrK7Dp6iv3!Vx^UM(u9mPwe26#bX*c`EWN@s55B?&RsBqJAz`=jfIKHbly<`h~p1
zpOhKbhw%5Y2vE41;sEzAgJ(`R(+zt?-Cm}F=zb{1gQNQ>g9rn8)<_rbj>lT}=o#@(
zJtfXYGaeb8?IN$ibMR#9>itakWxDxv2Tv0}hl$?0x<R~Fi6J-RZ@d<AU#h#r6cAl!
z=Ai4w=i#N*UED*=JzVeTzF~k<_tcI2`*A_63*|;xw@l&v7&<j{`??apRx&wUK1`}B
zZ?kowf~Q({?nmCQ;VwuQ*qpS*+)e6|{vg#>9_H0mVR%Z{SL3x>F)`b7eXcA1opLM8
zB4+!K32DX;pl&TZ9;&Y5O=6Z|YP_y%Q$m)t<Nb*oO58->kM2G{Te>+l+4}xE-Zx-!
zjPB-8;`s1GqATPoN%v!Sa`Sma4M$F+)fMLRdhjM8rb@&-8b+K`^djq4pJ%IWC;5zQ
zN{F9aVsBSoWkyYO7Z~!_mAy&+dl+HRX`|R$vmyB;zr$-bXBXY%)6{%hXL9rUnD<M+
zqW;<W#2>MaaOZVuvVo3mUF9)^PntokL^|QxE#howOew+N@%kg(kGgXqyszp(ZsoFw
zf0OPlo&PgR8B4#cE|A`J-QmT=*;&#L0|t|};S@qV#?sPb(+LSUO3Wl42iIx+sl)g~
zgar1YR-eec?j1#|qc*U0Vr_DmxPuzH#*jlTPU*VAb$CC69x7doAN!%x62eag@jhk{
zuj3@Px=-SL{}Mf?*vKt_(S2Q?L)83b0q=(}Dy)kvv0?_jCc5sN-F4@DD5cLKayD^l
z*Nvy=NjH=3dEM3d)T&z+ueA<P*8Gw;Xer|wx@YBxxrzP(-5o9zby-UZk6<>du1d+M
z-J};p_x`8kHf=Xs-`h&tE48J>O1CL}e#zLieVaJTzapOxmh=97#`1KzOf%OtT*B*K
zGvCKx6R#CY=7Gi~_uE_u`H)#QI%|nVu0K)kiDk5?DR-T^Hr$2lzO7515&VqkI?!LN
zYs`?6Zc87I(K9ZLb)WHokM3P28|!|c%T3pdTQS`&EAa==eWoiuNBAfF9b{cF-Q>FN
zC34@9$;X3>2i;z}6?IRV)9MB`LJE$Nsu**hs#~;xt=}~w=TXnd`FF0fbTzmL(hZo(
z`$T59>+&A5wJpE?y6FbCHls5}7t1KKu2xB(Php%(7f_!3V~&t^7(?*7Iot*6ZXq25
z<I69qF0DG@ofnf&%|8f#RF_h=7zn@Ai4dEW*J%UDt;1wq<6?>5n!i1uYnDdogG$En
zMhjY3R<N&T&*C-WT|y2Ip<QPuQTo`mg!D=x<ZdK&h`LCL>)gqC`F^%ex3e{hZbaR6
z`tfwh9f_kKNF2XCl-P@lcHOdQURzuw=O5|6(0v_8xfxsz>zcnyJztc}fi)iRep(!9
z6OFtk8;CO&`#a2#43+8@aB-s>%^X&pEsLZ7UVCCb=})b+xx}ATpE$QK6KBU{;>2rg
zecXz={W6iQZ}C?ybouma>rOLqRM+MzalX07`-XIQ=w{X-x3yzv-K$)}PnV4TCvKD&
z8b$u?d4^6`gL&k-_jtk?b1yCZpc|>8M-YCa9%&Eylc#%kLcSfs>s0O_bf;JHzTwZL
zie?VDE+(C{<G-ec{jnIrh<{004JPvb#8Tqd`H6j)Q;QN;(SfQPF@fAptS6tDEy<^O
z03j1f-jps3uIc*HtE%%0CDq;!$aCuk%8KJcP*><moR(bi=`vgM`d}w9?Vpfa#8pZU
zwGs2(-sID|<n6mv@;+WG`G(4UXycRT)M4C@?9a$Yq&i+QD|Wa}+67qssk+|V$e}qM
zgSzsWw6t*=Tfa-C+=P;ub2$?mbe}QkpzH2V8|Qsap0magKX4TB*Y_ZP!;-IL#0KK8
zWoo~!#&cekk{RGQy*0Y0IpmYxi&U|U7VE+-<mqH!UDw;65aU8pefSxBX3OV<?@i&=
zzY5{;C0`R;$rJS@Blfz&9A2x;A^%r&KIwj8?z(P_KdtLIfwXa9gl7&Thi4PW`JIy4
z4BH)@rh8U{kXeXbXu2P5IIgR^ihzQqdvzG6baiu6s8!iW8Ta+mu_@PmR!)y=ZU<Vu
zVhww;F1+2E&en|l<4RT?FG`+)F*mVk)%|#zHeSxB4rTJmp&xe_x}qRzSmOoxXF7SE
z&r~+uQEzgd`Gpynkw4RxA(e>Pf__Ndyh|G3d+rfG`U>xpKBGQm`cuQc?Wl9tW|Xp~
zHCw0B{h^C~f;UrFy(w|-ui`a>5ip(C9`YYmvbytR09!X4a~CXS?wL;aC27ynai%)}
zPp77ve2+Q|!t<=@s$C?{1o)OT-EyRzYq~LqDN#C2t8<#r-s>gnf%YrN`P-hfYg)<E
zzAA=&eqr}tE{9mDoB|<dq)2|P&Pn0b(Glk*kJYd;PkQto+VZ7~%zwQk_1TDGwz$PZ
zopXf$c68-DkwM+(i_Tk7M2IX#tRltpcVOZ|F@QVeMdIj5a9J!mc1LZAsLh9JnTVi^
zaJhIl3TAB*o;y$^iTV7<9Tg+#7t0ngXCUFY7{(;H9P#Z5(B%q^-_4Vv)+Yd-7Hj!E
zIU}55Q0bf)ya{%m7tI-Rz9=4Y#h51+a=~{=%tS&0g74kW!G<ehoC@hz#e=T_EEHva
z1hXPh@fElfi<h-Qa6@En0&9QyY9QJs$er?0z_(ii1VQq???66L&U*}9Lgc%AHCD@g
znXbD=p7cG)v*o$W>pmtAV8T|8EEPlS33*{EfG6eOIgg)`EAq2{Mt;8@inFrcP!#9o
zt#n*mkmbWD^5u89mA@p<Ta8+QT<|IAuE^c@gV{AXs|dA1`CLz^bX^`a7OacqHI#l+
z-mx6DTe2{qxFg@G3@&%&VlHd%%L$y3AIPyQP<tdVe-6VQ%We4Ccq$iM2Lb*%C9QoS
zf9(Uzm-0dGcoEcQQcQqSeKdf<N(PU|OjMrm0Si^)uffbP#p4gyFj?7}3VBnMjESg)
zE1PA|A)0*!bTgFb7+}s+&M-tdTd7wbm~)g7t<W}4sn!_9eB~)W>yb(fJ+V>BA})#-
zDQ9`aAX-VKDNB?{=CdtTw(S7x6-oh9hgK@z(s#33X~VVp8l@f`GwYOWo)L&qG8&*3
zt9bIkj8ir)ff5^(sE<ImQ3?7Kz(nQHZCJEPNxKSyEy{96H?}HLD=<q@M#qCZRk_&+
zDBG3A)Ov?<h12*><q+OOb(b>!7zp+#+r6R0UM0USige`{#=Z6{HL`(uP#I7aT4yND
z>?jT^H`@T^h*Ebim}M#Znu5zw<qu{o9a9={PjXx_G0pyj(&bZd$yFAX2f-<2>@pOm
zl@xA&&MM`30Q#KLasjwpP~4dZa#5+wsr-_%foIk(E0Y*MzM?$;1Z`K9ju#=JP)TV7
zV3DF@+UX7DCD-pa72}WSklTto=fpe8F~*PYDT!v(?klyKIq*=4SPFti%C%rHd!qdK
zHQJskCy#;Wb0v)qq!-G`O+fKi+w;W01a;;$&;_a<-=hnH)WjOlY@&K{5IQnMy~`t)
zVd`f*!8S>4Q3hP5sC}%!oT_#j1_{&D@$?)`SLgNz-AuJ(PXK4BAMOXrT(y`!^LeW0
z6UbYjPR;-@LcK+IXOvo&?v{mW>y;pnR)5)t-o-(a7C>35P7DFvGIcw9cZKTf1F<Vr
z&t%lrr~^Ae&{{Q>6Mu}_eFHGpt4@CE;#6BKOo_)2+5(uMe)bHk6V-!>ke;Nrz6G(H
z)!5q*yH)*xJE~-L5I<F^YKLn;*{1HJ+j56`oDSSHbwCV&xoRj55Wx|9XbWm*)MLy-
zIjcTl%FcOpQ75!rPy^^D%~P$bK%TFT;P(77PL4q90(C!^Y**Em??absYQ2ll(_c%-
zMKM8}(H6i!?Fr*wL0Z4Bq02;VRdW!8XiY|gOPCg&4MCH%p>4r>s+P`mXSkNgrQZy#
z+F$@@YM&f{pgG!4<v=i3+r?$`e9h%5dTD|7a2HS_wF6umM`^u|Lu{57(*m`l+KnN=
zJg&83L?cJrHw10D+Q~*BIH`?`M(wngl>shiv@6Ykc~1MX5o+hPPrrn^7qyK{l+Du;
zd!x9deN-MQUDh025?s+%F*0yfyF&kHp*ABC3KnS>CV;M3yV)O@H?)-pA?UUi?+w;>
zH2*Ykxv%9O2i*hBx(Aq#wO@Hs{)raz0&UN=*(IJ$&7C;~ue3f~r}^t!sVD;U(~4kw
zp#HoOwOD;k0^{`8??b`{y`d8%Y}Ef02WE+S@15w~P5NaG!E>{I>?PE;=rhYgY_dL|
zi3Tb91V&M|>1)%Mvt9oavk21kHR*lWsUJzF&Tf5$-ay%-@5C+WKK(H!-=^z5n3#J&
z-*qX(9@O9FG<ryXxFy;S>vw$ud71ihI`l-AzBa!W+4}CEVl<EGqxcNw=+D+iaYA1Z
z4%R32fj3b*rJtb(!5RH0uHbT3|2sF$=k?tV!oCaopnlLSPv55t#OCYmuOP2L-;6&F
zaz$UCnL>qn`6PQ@{|lX2H}pdo%Dbt*MtA2Oy&(-s+|~Eu$Mk_-z5}|4`l(D6c%uI`
z6a-K89l8B^p?{aJ{Y!l^6OH^0eHhi6U~uPVIMC4P2J{RvG)#al6Ak_Mp$IW-;CbyZ
zLslLHO)_+(MN<q_!a+CHaO4b%X@>Awz?^RQek{mm8Y=J!nPnKq%zykna^?ojH8eT`
zmGGyC`Nr)wlx>G%pW%ZL0MiY(xlKA~sKZr!hT+u-2s&)=;!AnNFu@)2vJ5l62k@w&
z6*oM`3`56Y0FE0vt^k)@!`G3ZJ84+@3Ye!2Yk4^5jG@XLNI!3=u?ch+4CQK}mTxFn
z0iKr(HOacb5XnII6~lfe6<sqd`53GV4dprWT{rw(2vdp;gSSD!n}*dLL2%2ER0}9~
z4AJdS+%?>OinjZPgWT0WFtlj};A2Az`U9UBCUS}M%n-U4wdaOwRl)3)Va_lV{>H%_
zfEi#6%0Mm9Si~nX*l1?YPc+`jL=kFy5(^u`jG5!1%VeX|1PN1&wH`swaHC@;$fp@A
z^aAD#W4#d6W*Vm~2bVd<aIOdE8rvL&*!jll+}$oPzQf={l+kZLm@PCKc&KHuaYX@8
zmKd+Yd8;lnj+_lsmK&XCp!G^)!584N%J|J3w5>7Deu&yyqx3PxD8~4N3)b~U*$+jW
zvBgUO<Bc;oRVEm(H-{35#;f0fb&~P&Llm2hEk?qW6UL(qZ=5okIVGGnzMBj3v&K#g
z-<&fJ>;kbDjMZ8}&x^+Ixl_7i9L`fhmyMOVuDfCkn*h42#;>}8XQA;!e*cP$y*~r+
zhOy2^K)Gr3*oxX6V=A^Z>Rn?<4#@8tgF2#kVEk|)+8!B`ilFCX<K$K_?3wXp8U#Hz
z=KTa4UK)Q*1<zN;3cEl)!Blo02m(y2&w+K2>4hiSf=#!$^A0gB%?3)SsUgz=CYhFB
z2IgeblP5r#YD%99lyK8PdK0Ic+<%0i8K$YhXq#o~-3xTHO@5Sz!($B3&ofn82ZD{J
zQ2yX}g6Rv+QkzV@&!DrCOmllf-7Th@zd?zuCXMe(iYcNY2vSXNWutAoX(hLVJ4`jX
zQr&4<6$wGROt<_|+hh8pA_(@Hs(u2@bkhT70`E7qybF~MnnsQQ&kR$=PN*F*bvp%l
znWkv^Ub9V~QQk3A)M)^7Oks3DoG{&M06`~BAHIzNIAt=9fP^!q3~nyZnnD?My<lop
z4YiA=Pg6mcZ>q)fIhRaL=*25At>VJvim8C#@N1?CbdMIA%JC<RuA3A(d5TT5u!qDS
zf?Z3e#Vu2HW*poxeZCcKcTGk7c;7c2x(z`OOpUPj!{2-zJsHIlQ#SUG_+zi)A$UGF
zJ>r7krK!mS5WF%ibO1QPyzU5q0p>-_EQm0l;4UQ6e2q`RLi4vg_PoffF#@^R+~s2^
zvBZ3vzJg`uBrYeHn=f(~zS3O96~!uZ-gcm@F}JIR+FG-PKXw#jZpZ!6dUL=<2#Pb;
z;tnj{{LxLcZ8YCCK~RGE6urBf%ww4Zo@5^T9>i`jOM77LR`c?+7^4*Ph+`;H&D~=F
z++lv)447%=<J(c&WiD?8!EW<n{yf`0bKoxYOS-v`m<P-kzX$7s=01!w95UBn&hTOL
z@O7wVn$s_!mStYbFG;q!5uI_z%-uNdIcDb~ke@K0=c4qaxi-(Jo-*&`PjsF!pAJB`
zo;9zfcksM<!KXmEU~ZHIx;%5WE6^q1>^2gtFPk$Wpml-yk4r$gYOc>G>zcU*eGNrs
zPr5d*o8R4!;)Qv0444JGEF6Slrc0x*(Sx&GTo=L2*)FEfAbpNYo7*Vnx@^{i**ur?
zOVKvp<?ay>EO2RB74jloBI)jmav8!LzJ)GPoX-}ywC6TA+Ql^z#bTH1EkL)#MXQL~
zQkSm|LeL7AJb_}Ri!aZ9u5n370<*O)xjZd($mI++>FQyZbne`bxMc9r&vdyx5#(7e
zmFl24>Qet1ifos&zoR(jQj=eV<1RB9WX^H<nX%s!E@nIEa$WR&VZ%k2U2Xv8xm@S3
zM_zUb=C4OwbBXYVW`!=fbPgA}d_0%k<MIwu%!*xpJ%QqeOP>G@BJltJ|4q98^}k6s
zS^gFAfH(do9r|3X_V|~uu(!E1EbLMm7IrNS3zsPk3u~oeVYM_Ytdxd@%a(?P-DIPC
zX;@g4hJ`&!!@{0#3JY6G!@}|#!@^$w9v1d44Ga7HEi7#PM_AbQ#;~vp!@~B`u(0Fb
z!@~Hf_J0ct>;Lb=!iN7sSlIZ#CM<0F55vM@IGkm#gZy4{>1c}5(Ns!DQ~k$i>Ptt{
zP&%5%($O@@Msw+Cx|EKlYw2i~dDCc?Egem_H;$(JzmKLz>1cZXZ8R<a7)`G?j;7#f
zdY6u-&%ckR^>3qTD;-Vy--7&(*Fk>Y($Vz$dywDxI>`Ul>(MNy|0~G<_Uj;j`M(GG
zE0hNL-}zgRzv3H5Q}(W;dJnX?Al}cnv{(6m8P{5`he|6QDy4L&46@N!I#jP;JX7gV
zncp;2E~P{D<`>WP--oJ9=}?vZ+fcdvW2n?O4wZZ9v*=O!EP9qci^v=KGvP#!(ex@E
zP49mnO`pGwrnPi5ZGRh0`|Htkl#ZtF-$&E$^=LX@kLFvYqgn3tXukdT(JWs&nic*w
zn(w@EG)u;CV%2{c!*>j&-C!>52A9%q_-EdYC>>|DbevsfW0}%%ew}wywsf4`-Zakc
zrQ`hOyc>^yA7{_fakl(zoW1@r&c-*6v*Ew(l{Edg45HfLju)0N4J8MzADp-1+Q{sK
z>xYy5aBbS49InlW*l=yRme<b=gtYpK_+OlG;@Y;oH?CiPPpS^heR2JIh#l8&)&r;H
z8HuR-FV9GhWGsD1Or;Nr`9FS0UMFX{{P#a3e^1W(ug=@X|F(zZf6Uv4|BY`t4#HNb
z@Yh({;ko(iTP(|8{U<|-wbozLUg;<J^@2)z(@?6VpWy%E`>wt56Z{{&@BilyrQyHj
zeJ^<*&%tx`dObDd^_*=ieH~4uuj7BRC^nalp^I#EEuFJpf18ni`Dd<V**DGEZl!bf
zo4?KftCvy#Q*-v~Me+Z+A6|8QQI)^m#{Nh|cs-KM&7~8oOX*1dSF&DROGmPdY%Kea
zk#s8^N%uF6q{n|glAizm^|h3KeZBtn_4WS8*H?Mt*VoL6)u(g`W&QUh)PI=u`hW09
zc3$uvzLZ@)s)lRV>%8yo%KIMutK!--7?6@T_Vy3|GR^_wp9B5+mHp>3>-87(jRXC9
zne|^B=r=F3{-c5Z`?UMdWtR8<{6O3OwpO;6u9Y2sTPyp%UMs)e$Nul%`5520R_1nR
z<y;IRoL)NSs!MuR>(&7Y<_1-D8W0JTD{1;~5v`C9Dp-0}J;-F~!-`4oj^AKV^l$Sj
zS264FyMf-Q{Np{v=l0JT*Y!>BX_^1*J;h4}EzI5Ox#(nDS^a5O9R%v|@6TP@py+>9
z+qD$2%%6zrJC8{B-fJsdO06jSKdiun|F2fK|A$umKX9ff`fBBn11~FH`Y%gvRPR5H
zkoB5e)vP)~TSHGjAJs6YJ8n$KFrkUE*`|u$y8)uW>qp2xu5ty3`d*LEfl^bi|Bk%>
zB7H}%f5xg>x#kyWeb@I-xLR}YU{o6$RdZnv+_?JSSO7MEWep|mvQ_^Vy~9t{?th6_
z{LlKIt>tl4=(QShvW%pH*VR7}<*xV@(7(Y-h6<<ahGQ_)K~h~@f81Cf*WX+l;ySLN
zj?16UNYVB))GIuOV(L2+e*Fvj|LUK&c;nxh_}}R{{r}LP)eu)#y?*<IEV-%1m>5g|
z7LPyQKH1w-)$Rz)8lIL?x0qMyD!{vR72s34p2Je_Z)@_`z7}igD!}&F%c+)5F|WT6
z_R=ZF@un%pw{(hm^B2PJ-<JZ;(xt##rAvVk-mq(R*>e9_3cUTsFN7DD0_97W0u}Vt
zw{e>M>j2C<{}+320vK0zmWfKPKDNBuZTFh)blJT`?rxW=N|KjEUP`q{C6}b?s*;zE
zNj=$?Z6&hgvE*(y1O~d(30oi}0fyx@0Uo@80GTiY2_az#0TQ+WCL}-@_F*7w86ZqH
z9`F19|D1czy|+qsXL+x?>5fyn_x$Icd)9yd{~Mza_d5#lK#W4XET9nmPMfkPu1$F`
zV9Y~J=R;1L@^GL{*&ElUWSll-Af`>pcBBwDncD{u;h4Io*R1^(BsxrO-E7vjVJb=W
zK|A@(HOx-m21hD3IwYG5k!;>avNx^U^7ojKn^N1hn6>YQ<?5!?_N_{B5NngVY5Tg@
zz^Ch`ltE+*Q3<(>9!2en(XWF_PHaGbdhlVMo;AIn-Lko-7yqFh{J%Go87N%7JkY#y
zwx{^=)6EwCO%CRZSI^8<OXYShlgnmuk+Rd57p`8IUtB(YcIi@Pc?JJ24d&0HerEpM
zT;|f*tC_iLD|1&CXBSqMmKK&X7Z$JXm8-qym#*xU+L>G~GnlzDw~)&`KEF7a=W8<A
zOg@_*%ns)VbHmwvr{$5;XXY0N(8GoKGXodSo*kIIa%u14(&F6Sx!E)G1JX*4@Zevx
z!u;adg{$Z01}@E>y*R%(_re|E@)OH1*unK+aZ6X`ADg?fJW!l$R+|H*xyR<u&J8qM
z_=mk(8M=0DpsGvlR}O&f@j|VwO|aezcBTf-KJ<`16wk#mM$YDGdp1v_&!_bupN>{o
zxp?)`nbVK$pWA!sq4SqdU!1*i4(MQo8+~AAnY-ca?3IPbu^X0Ov$Aw~U}b6V%0*OO
zT3Q@<eCf(-mM_m@lboGh+`BTjys|t{n?JKWu)H$6_w3S@xdDe7P%v=jD%)E8;x~Lw
zHY(o=6v?ew<g2j-*$@BT-?qBPQHiMQxwwuuf|Kp^`s3<$90zK17iP~s(bL0a%ACD?
znPjPbZtnc-)rFPz$`hC8mNOT7AcwV=SI*5ZuHXjgeuC?pc#Y{jKa|~n?HYifjJ6<g
z+rBuv(8fxm7L5I8wT&K-RBXbtON-~{F96cl(=&fAa}oVO0)vZlv*)nY+^swd2neaG
zk2^#epkb*4z@^!Fz5uLx&<(y<-x(=tvyBc_+gHw>?Nl9eqQ%_7?X#DLa0lrxn2Ieu
zJ?H0USFT=>8N(#C7v~-a>1-2s&M&c7n5{PEaQW(G+@QwUOUv`i9vsbS5s3Tc`GvVF
z`U))r1=ib3m#?;QSRdQ3x1c^NbC<9@vJ8<~ml<D>1xDSi(pen_IvYG7wJ_-R92XEv
z6NOy3JipYfyvrkCLFPL>a_-V>m*OrBVX9X;_v-w@?DEA<jR~Mja|*jMd+Geu#g1!y
z`EgEpVhT{)rNyhWS9m12pO+R_t}HFcqUr8EKfeG@%x&JKWu7YVK|D{`<!7;qk%D=z
za*rAAF>5|>Q%_%NbFUeAv$^$cr_GKF=FY2T<GguE&zhTh-wGF--rg!&O7;8;-rtF}
z6og0KGC{<j=Ljy~IB^l7TLESHH^Fo!mh}te&CsADlFxVA_d*q?{Ih&rqAt|%EJ?ag
zLrBemdLk5_^eP}_&zh<$QAyy<?nI>vjqOHjx)6?lnTS%X5GhB>6;E3R0c=ME=(qv0
zBO!gqOa+qyOdDK-H}Pma$$Em;qe@8YQ6o<4(R6~=qs%AneEW?Ocd$O_ovwrQ)N%tt
z+&QgX2-qs5y2}&KL7LoS;KI75WI!%|v8UIh_6-jY3}g?P^(2&EwgyqFy;1{C-hHWm
zLXBGwT{WrKf7IOfG4s*^vuD8U9xw>HS$p1?thr~<?9Q5d2h4o~D9xI+D=h8J!j0Ir
zgZuz}sb_G5+&39>`ysRAkh$xSx$V#)lRjkbz@J@mb?+gw?vPnKA<qwm{Xjr!U+Nd|
z{0{s4oyXY9t%uA`KF+rM=hnIR!cVv__2+mF)lzTx=tqCg+%}H~2h1G<CN<#Q+%5OL
zuU@m!Jqic)zSJAn^xm|_q*7n~?=z-%*G<S)&Iw9A)tiP^w6_<rKwu`QQeTysc%fp}
ze;bObFDcKEX#9E3XF5Upg}UXR6*Cc~mzS0=XN0pzuo56!Au9pC!aipe1R-xBqN;x@
zv`R^suSN(+7zlWxTseb8v2q59V#^tz+_C|2mZj4xtezlV)#?e*md7v%TVeGi-5CZl
zTdOk+s1auv$eD<~z*7zcWvU#&t<OKOGfDoz&A3c!pd470e+c-v#Ds>NMFM0wi$pnA
zOgW1LB;YI(5GU<-26SmIF6}2CR%yReanPc276{hrOZ^-<i^4}u?|%;&f!q54_y_<y
zkC_cm8Iu|PU316B%$*>~FBvfR3>Y(DdM~Zn;HWUoN2$-C{)S_$ykL6UA@D!4v2Q1J
zKV~+1je!gC8w*IfH1^Y|ztJ`Jh|v4L#=56^Zo}`YWZc8m-Q)<OhoV)Q`l#Yr83JBV
z8r2spA$Xw<?B5(y*X=9^ivEy{&qLu)-9T8PnsSPvszwi~_qA(6FDxxgl&d^Xfz_#@
zJ!0+`gTOih6xa+<;E_<l$CiW&&9&FSX9-pVB-WF|DRL*sDjy4U?yTVp@o^f9cPD6U
zP^L5%w?2(!Z$BRz+liY{s^ia=&-!#M@A8PHy@^MZTk2HYrJ;Z%C!SFbD^ctyb!R}A
zx5O!R;$fxKor=4(Xc@i86WH!zby1p*&vmG_KxE)S5r9QWaF~D(gGLJ=9|8~#+?V>Z
z4uA;){-Fb)PQcfILdTmzLXW=Gn|gbPk>wp=YA?>Q2&u=tqAM)=;YbmjUiwn+!Xv4?
z>CLZMgQt;95aj+}v7uHa_b(!N@u_(p`p*ErB$+QKSbJRD^|`X==^l7d3WwWF7gqfG
z<UUTFZcJ$R2r}t)yb)g#U&Zp@nT&fRyQ3r=A=w=yVe$)cNjNA|Dvev8N^=N4V*)~u
zP?B5L1}s9PsulAS)uXER?!t6;LZ4{TT0c6LE1gS#ETK=7E1~aH+@+y_&?lZzLZ2vh
zguXMN%Uj}vKJl;;`cB1NTC{{7PbgW(XL9<G2)@^B%bDKP#wXYGIRY!<@*e=Q>5#c4
zV|HcCLmBh(jM<bk>oO*F*xdH3)VklcTYeuf`!i-cwE3GdX2W4~_Yw2(gqg^gZ6oIH
z>F|2z5tGlD10!Zrn&SR#6Eq`e6L;NbhBD^X5w^Z#x9PpQW*fSK{A^HS-PDu8-!;8)
zchKJ6d%&{v^c)iCJ!`hELDsaMUikr!fGqfZsgd5?F8p_|`-dz1FPj}mol55h22xuy
z1Hu=eK0IamQlIGQ6&_|AR6MC3eBKoAO?sg^AHR<Hq@xSLYPRO*DWL(54gS68RuH;;
zc3?I-?i19D(5dI?Hh7WWfRCi}3ycuMh`zwmeITraTu!nc$k`;#p-G(rvm?bI!x0IM
z4uYLs2~d-SG|7e}o(~9Fg78`b4+I!=K*+Y|i*Q}dJ;st$F<j5oA7~If&3#bTRja^B
z>dsaqNMxX+PmH^pQ$?t|Pdu`USAbm!w}jHeK&78(sEdb&V;&Oql|fj=<*)sv@!nJB
z0com51~;kPt6%-<BS*{zFcG^#8J(m#^)r;dv&RnG|G7#xMfi-5^+GxiWP5q;FCs<A
z`P-NJ7c{l5W(G56-3px#Ho@5-Z_Ht{?Sk1*GMgSWz4v?e0Y38XH838)sPI%+{+lfS
z1zSE4V|ae8OZo4h{FYPZ=0USIV{SfTwjD8Bj+nm3c)j5$M;&FHKG~(6r&GP=_G9F!
z*5=ISn%OX7`p^RX3ex6w{uwd%^A9`@j>Ovh9z44po)s5j<?lfG%^k{r3gsO8t~G&2
zgv{*w*$#{(bZUr!el-NeXXe8I!D%A#_W$0c{4ctc|9zM8PjxB(8u(pwdha)C`Tc3r
zI}jViw|57<4WNw}MSOHW)TR8#BjvB%PM(m_onIWD&@l?nQ^FrGf4F#&{|ouQ)mVK@
z)vB_?i#*};B1+HKFm~hZJM)AR(jiJERmvzsb0b`#Wy4m{ANfv<of*S0pd`Z7b>dR4
z%l~;?s<4$`8g39xC$v{6^VL;+dy>_4ob&UaDSZA!btqr>m*lYC3=U}Rl-YFHY)tLV
zh*xJ04k2di(`G$5p55klus#`cTh8p5H(P3EYwEF#xg%rlNt*%am!Oxq!K&L?6<nFg
zzSV4h{j<GFz25BT8#Y_frAhKbQNEP?(ApXYv3?kR+B|a9?0C9c<<F#g9|@gSh1L4{
zoBX0b-h_GirL|DDJxc#oH2i>ae4A4D!s#`&Ig{G_<Wpwo`%EE2otv37x4wmwv@U0|
z-)f2(GqB6tnlTT*)EpZyhwm}jM@-2ptV!XmU*;Zpy*cVZ$MunVr$=6;k9@zm_4To<
ztiiV-Ha%@_88n+Nn%><Z@A<YZ7|qxAfuEY>>Tb`mzuTWS8;_Vx_nJFL%m%Dy&fGF@
zw$;q`)YS|*&RuDf!`M>Wph!FtHX5Dv_Xdrc+zqy9*dkuOX|h|R|A<Dxd54p3j=FKp
zb6kPfvn<@3*Mmm}pFUu2ho5t>P<-ZV&30^-w7COPz(o!_7#38c!88TV&(hp4pt((O
zTK3!8a@5?OF)vMX!nb72hCyz>pcnmHF}r_?$8Lv=fsSB{bBK1sY@ITFBW5di&w!S_
z!fef&2VP+^N6l?e!5*>Q+m$yvM$FAQE=DP9Y8g}9Wj60MXENqs+LT^nOU~>y#ocD}
z!=^f54&GxnzRHY3O$$k9o)50inst5m^}Vz22h5gFn%f4=mW$?=A-f-f9?L*~V*`48
z%B-DsJ-ziPdx{OrofW;<^!jkRqOJTZT3Kznwq=b!d&%1kg~((|*M4{-8a*Xz5cE!4
z*_$>m&6sAFm5_&j#Xby)(>)B=@S9R!_u7+YLu&H`#Dv>Yf0s&|TSm;S_nJc)GjrZ-
zO`8p{JA148hug5Ke}lGeze?n2SF>-5^5mUzI`q(NyEqiPH!mABW2kY`+zhQcK6sHa
zd$VQ|-9AaB`H`choiTHA-Jdn%8M9kz!dJhVG4=C&YTtl4o-to`-rSQh*#T3}m=ou@
z1#>y`2--Yvw%~9M@cQI=Zg6Zjmh8IGk`3pd^&|d^`tCLBj(n@>xGUD|Am-eZTtEoV
zw;iT&Vtd-$Hf1k5t^Q~6aAaeK$6wG|bOU}j!Uz+!-_mWn{xoW1yCSLp$MiPu7v~)%
z`m5zTa%Sy_!LOc$TSNn}exJE*+H4vzx8%%SkDBdru`#vbq}fq)6(6Ol;EPeQ#18Dt
zvR&Y=b(3btbXc-3*DyOqdA}vctpQ?8^0Uttex8r*khg_xcfP+JND7BXaoT?Vd4<`L
zH@DZXU!3h+`=A!znKSE0%;wZfFyz}(^J%mBn7QrVRepDy_4gTk3kfF_Uy3!0RK-Lo
z)JL}UHbPu27~+2>i$0Ys`nv6j2fs5}^!8-Ydy_@Ko-F#qWYOOzi@y41pDU5xzv<>g
zzrHtF>z8iEvG8fAkA*jblRIMW&X{{K!x=0lgLQo5ColRdGy!f83Yh4L`y|S5iBZT~
zj^b2Y^l<3UB2GQk^OEc6U!oqg*Auv3G}c-B&5N#|$UGn^SFmM@&W-zds+xPzCg<7Y
zJViw;v^Va}i?CM7pm5eRv{`)%ZFJD7M52Ic-U{q?PTz1I8GfKoLH&q|#WkJGm+*Nh
zU!rY$%AV_LVbIU(*yI9ZTbPO?m^aTRhcaIa!?{dqVcax4|FtkK6H9dFpQEO^78&MG
zlVPrzoi+0Dn+MFjuQZ4Enk{?H+E=o~H-daO>whEo*gFTzMv(18F_X%F0BG$g^GJ=X
z)XizL8{$XWJTwxC^A!UB-YzvIlJ*@>;0XlVrdIfR#M1uJ+H|N<kmvuaK7Ti4?zGt_
z+{7zK%mug%Wz5E-l+>f5^`CZmpXoguYx#fOaLp&T$Y^h*5AWv0{Rh^+V6vDUXsyyF
zn=u(o;;6~Kl>Bo#ZTd${HZ6tO&=M)*{V_iKsCh|^x)DfbM<>jkM@>F$UOqzh`>0HD
z5X7`;Ctml<cx2NBbI+8yZNxl$%v{Ql(Ot{mHDGb^=ccs~Y5DhF)8L;c^=`nN=iS%9
zgPO1y3-+gM_UiST-Ni?DBjF1EKv3bI6}=nKyC=2vID_|=tr|@IvBxnpSbCFA{l`8`
z3=|uCDZOpY$PW44$8~4mYrq&&>c{%hVJ}xW_`lc+1`<3d6iA0@aNe1wY@6C;Ho!a!
zfqOuH#Sl%iC(;noUHsjA^o=w{PjhpVo41hPAmsZ2!O(XM(Xp-fr+v6A(ogZpFEhQT
z5|9sdg?xmNtoWAMSFODTulh3-BLc1WSfZ(~w&CWVzDZ^%WwxZg;VaT+?Y!A6hm~P*
zwk7G*w^PGfGcUo}hP-yKOy6(cblyK;snq+vA}vvF{)0b^2XC#*6hg}1&5OPij@KPr
z1#{mnbJ+d1?lJf6=I!Tq(U-cGHm#RIxBCP}kiyC6yPM~uZ-Bo@5kRB4-?NXPXB%M3
zKIBiE3>Jw<k%GYVeou1RXgKb;Hg5)G10WX?&wO9kXZ~~7XFdSPT8PWoAPZ*4OHJ>^
zWcS&uSeF@T;1BGNQr5u%pA!XZaL08-n2si;7qealsXkvQVF_PMOR*>DMkU}EMVRMg
zqSr6Lge)#<Hx`&+xm7E~Kwt^jSBM?{t$L<O(mr33kz(r-7cWN(@gkQODB-E5UW1e@
zLf=MlExfM0LcuE$rWo-dL=80&hw=)VPFRhDGBvs5))!ycnWXsQX6W+~UlMZ@dJrZ+
zt3>~In&rTQFwu||U^}gh2r!8UoB-1qpkV}EV4-heqQVX23J5l$%x#!zqDL6EG<l`}
z3%t^%M-kA!ZJ$ZOL~*aV|536i>kgY+PMf=6nSw2meByw)i+^C$;vdL3LuUUW^B~Lu
z;EdAdC5On8-wS(&q#uIk-hGG6_6dUSK16@QF;oNRjD$i*XwE~kXd!>d-0xaIiXqr7
z?~@jocj&0Cb{~vk8FSYub8y7mp0=-h;E*{6mTANcrU}I>@ZhG?1}T=%hpiI*a3_);
zWy~u?Pyp+-^N?-vh`IH5O}{(`&OSXtrc4KM^C5FLM>m0=)LQ-;{;cEAdj4$W&u0E?
z<<B<C16%mBi9Z|o)5jkX6u@KNjO#Vv{l@SYBFZcHXT%KY-4^{r6C<KJ$n;Z+;U9FC
ze<qEsvYmGWdWQfG-f2%!bE7^0108%Fccx*s!)Q<!^-u?JEb4V(JJM!nuIrP4?!#Nw
zq`m`Ln(o0BJSclpf88^&=B41lWG@K=`Ga5}buWR*m%X(0QF@c^c%^|4Av)53%-jWm
z2G@{q|395;hPz^Rp*@Fje@6zHt@wv~5vJUoxR*bs{|Gw>SpYqK=sYE-olnq6`w)yy
zFzG-jKVq`y%_L;Pw7Gx8?8dx39;t9E!g9doPncWNN6e87V{z_)$;Hj!2}qo70w11O
zb5~^k{x|1ufwGpt9?l*WKHW2Ip1d6g_B+7<!*H@4Jn|@cWQgz(?ZD^<%KooswRfW0
zx=ZG^Bj(-_vkzM@!$U}sATBlj3Tke@VAhSAt+m64&6dLq588MyyMZ0NDGT#z+;smp
zcmx8qnZR-Dt%YxvUGUjd@2jNf4M-mQ1-NoPPkAcvh{3-XJvP5I9-A-n;m@xRE_?xe
zIGNfTWW&3&mVRE3fG2tu%y|&Wl3>CDo;zsv^XKND%WV6z4E=eL4F`ALg|Uyb;X*V&
z2tG;!NsMC&evV`uQ9H&=Q4f2^5V;UA2I~jSx(UtSF<?f>OjJ#2z)WS#2<SH4C@0Jm
zOD(4^?B6=FoV{yL;&;soep0-;>4WC3weJ%KAH3fYvvs$*8_W-Qo~+sWpc$Ni6CoJ2
zj*#`KS@6xN2VtPlP7SZtDR_r;=+ye5)U{{KT`4fE>*34*Kaei3TAz7mSLhun@Riz!
zJBPrzh=&CH9yjkcFBu`viLjl`51Jgppg9;YfN|hg5qL)mUSZnIt%nV~Ro6{q%`G1_
zeemCz5dT>$L99)a+CW`@uLue{trQ9{t#__{uf$mAqA#o2p6p;xBHeJ1b?C-n^U?*;
z7a!r2?#g0v*tylFr?0*W81L%#?5-3%q9BPuK)B-#WN+{1n;<Ju?tsKs=bsUClz$-c
zWzF#sb6PH@C+O(5bPo$388Ig^=2dAkm$oI-BW5OJzUm%xbKW{#2H{cv>2B=m{|eiL
zIn7<Yol0>tfjF-zjuy=49fRfp*-|gblmA|q$(onUyDRf*bH`gP92LQ+!aRY!g#p}?
zXUB!P9xyfSF<b)`xMA2{n7rBk7M_w#yRH8$JZBNrb_Dw~W3ZjKa|SwgC>OjMd-eNF
zX~euTV~&i_l^T*n3f?%6(idl|JHK+S-vC!+vrsU1{2o&9F=-x*f0Bd`4za29Gw?{h
z1UJ_X!2c2^%9VybgodE^2Dc9eKA24b{dPytYwy8Ce-a?L%|W=Kcnql!T}NMW#J`Ug
zf}Qs<Il%S@ICC42oOr^F=gfJyrKZjBig{h{KbR+bF}Y8g@q#OU62)r{-K>D~=9VnQ
zikisVKpX2$*)})a%emn907N|O+l9{j=sLx5USL?7<?lxM#;n;l!X?O!P-ypslyTPi
zfYuovp+9DJ#6a-%>&QI(7V6v&Z$Dr%*+9Dv8_1tKF*G=J9zM+=LJP=FnOBIM_8?rS
z;s31Ff%R&X3t1gCP#x}>K)CispS}O^lo>kAEr=O~+60|dUr%0)m^@H2oIx|3E*cwQ
zsMI<%%EpYPZ-cvZ`cX4@ggOvtErxQo+2NddS%!uC^a8`piQlITIxtkqpx=W=*205)
z0xqU7$3}O?ul8A!$d5nx1(`%%X#92{pyA?08SP6WqdiZ>_ZPjoJg=^(P$P`%|9@e1
znm{OF^|0)8qFg1jcrk>&c#*TG&~_0TPF@VROHR}(IT%#d=`gk3zLxY{OT(Zhk;~*Y
z{s+{saQfJEI0e4WhFzt$ApGj6NliXoc<O1h^J%mF5Mzcmz|A@y(Dvh0j`Hz+9Us2V
z)6kw$wThQRcIou;r?2<^UjuW!_A#~quC7xHPhGc(?=W@<W;-<blSo=cO}P#k&gm%x
zXLT6(FPYwYOc(q+$)ZnyVcGOFVl*a9AH)uoFt#2xCeKS1QPsw=2D7*Wg==6);-5+J
zyIONtk~pA{W~nuh9Qa2~ERa<W;0~hij_klu<hstAjkVoo!<#4|!0F||!(`SVZ{ioG
zk)6BDo+&XO;elP4F{<jfr!G&BlUvW#?|Tyk9E3=0s)-sr8lvz)hMd`<;90&I5o6tk
zLX!@9eJB4M(-Fb?z`JKTqDgN={fB8`fLZL;39}Pl-GHh9?6~$sbOR8>_zK8s`UjCq
zG)W+o2SyG!!Rhq`CM+2Lyo`Tm3Rb#~!~TATjy)D#KnQNp1(boUWlu0>X5GLa8m=%{
zyQcI$LozY`m`(iix(=3x-@K7`$&|uxXtTDD@FrL+qD%FUZ08#LjGX|VI9V)gg=gRG
z4cg=T`3JHB|K!Y`$Q@(OLYTdy1qwA~)Q60WdqV7js40bMR*>>n;;MIw!Ed}see+jN
zX!??46q}{!6Km1|`2An`CIz1g!0%g=c7~g1qW5<(#_oDccLUS;J8TDtAjjUgGrJ8p
zJhN0Dta(OPW0zUWy9pyTb)>yVg1-OeYZF6zM=BiJQ^}!y4nspCy)9@TZBOW?OSJo;
zWV=7<wfni(CZ_DE6z3malWx{Om~7%*UK5{9Ht{-bA{R9Ai^(S5<2CWAWD{>dcq8)Y
zDs~MFdLrn322-ArlkMhP4h`np&amu^@Z~?2eEDyAFaML|%b&r^5nqc*MNII{cSu+o
z=Oh~p===RP*AbTb1Fy}G_-!iqhtQ^UENtX^{YG><|Do5&hy6wr{Py_7K9g+XPrN36
zE7`=4b)VSpr3?2l`acAl%HOPqgV8^keCxk>Z~cknTYm*_g~|o~$@plKdDLt>8ooow
zo!z+MJO1e_5(nZNZVC^?|DAlt@5bH%^+$pw`8^KtYXxIR=v3tR3U<bJ>PV*qgCFKm
zz9G5`#pfiV)bBM2uw0KUO#g{w>CUXVxn?#FvJiQtK#Y-%@=oMrg0URAl7teA=6b~N
zO`zgmO($yL$A71P9?bFyIOBqRJ$TezLro3s2$aVcsPWw}MJ*2W*mxlws6mnMJk0lQ
zPeF48y1pZIFhlhU{4h`jI;)N}?xS#IS9%dLDI^w=8FPq|9vq-+!ic<uq4>}st(Snw
z9}PCo&waVKu%rdOsh>6B!v5ozdl*T<-)Mm8kaFwjQIjBNZ>1l(kh3pR_nu02?{i-F
zelpp;53SO@Uq|;+9AhmQ{~tf$jbC7??^zp;|1JIt6#O?PhLQg$*~HttCf=NE;&0JM
zVl;cqLLBt_ep8BMe!y$$jeb)K{s%O*E^pSJjH9y;C!2b^*VG%5O??VYDOT7dDsJdL
z5!byLJMp}^D`#$o1IBQN7yWedMIZ29^mk8qJ4pNdEeKIq{YAG9i$4}JtRWKvID6!k
zO(2gSL^MEbG2h^KMOW)nURU1ZcSXU!h^`<*L2~+@^qbOd|BKhuPxwtK_*ZUVRFXfU
zgNX8b$+3L+T4H0qeO<UQ-{5y37%KO6$SVA|WD`H)HSzjn6Q9NyI&RG0@SD={zSC>!
zYy74Z{Qq!fJ8jGlCYySf*VJdPCHBkf)?I(UFdJW&jq+{VgpkT4g)H8;`rXh8{J7VR
z4_^C`kb6}ydKsPHw<eqTYp;o4_D7;kyc;9wIKSWQH>DH!39qU5`%NkMeQauoIAnd^
z^a<sHS!&Z!nxt@kJC?6Q4nvD5LWb<G9``nyw*75=;YR!J<g5QISdWcEL=g~0AB3cO
zl)hT7{Sc@9cC!5+_1b?r+5Trbw?8mt){dInCn2yMf!u%0;9HQUM0*HuLo^5D|G7PZ
z8{Xu1Ls#SPy>9%%<KDJY@OvSTb;J$d;5Vf+_D^0@KjSy0;GaiR5sU|`9OezFQDCg0
znc3VqN^9u4hPnL_8iP&4jw@<7`FL_%zwns1e7583!{z(u#}ecEy7jSr{QhJU@AI1Y
zWU`5`U*BaPzt3+<$Nqk=sZaP#DfpYwR7X7Vu4Gdm^qTs3vZ-%HQ`enk?47%gnRO*j
zG?YjF9*WNOyOEaQ4oSa*?~H;alV5zW6wUw$_}e*Y`X<D27X07<@d7OQa64Rkzj=^%
zC#}b>*$X=xbRf_NO{j}9!Y8%*?OC())z7||&boMKMjJUiVDb|NO>IF_&`&`HHen8F
z6=4eDl7aUW%+1dXFx3rMK+D9gpEjG}b#PKVbv<F~omY|9h7DYR+)gjv-qdewV1%AZ
z{eOP-g9?5s0Dl)6rJF9C8uAQugqtr?%Af>p+QSl9wkfroK^hL|gEplu!u=t2AFobR
zo0UtOJF(x<lT;NlS!zFG+U_U%x&@zhh5ko=k?3_j1izCeKWesNzYmy)PSJ_tu2-6y
zCuwv=QhDj>WYEt)T1gD!Z5zX3yg50HzZE}ekAD8)ig&bhCcbxLc(lId>U-i7^>-WO
zXyt=m{C={DAMl!Z<5iE!=o|h4>35K}B#kfIaqdGA?8C{X-tIN^hGbKpLQ_cel53kX
zs01=F&70kiFt8S>`JpsL%9V}w%fGJ-I{efATa@AdfcKWaTk$%q;BVO|V-5+*yOT})
zve(34C!2WdMo3#Z^U`DLJ`|4m$CFL{y4TeINH+DI8`E&NnKw6M4^23&>%*K$ep?vI
z@%vaVIcDHk6O^Z(`S(CWso_itXQVf^J-sI7d;~<x@wS}_9r8PpML&})`t@YdA0&%D
zzB7@Q<<rTcue~Kv>pO1gU5x3rfBqKGzG;rkDP*?eh6*sD4&e#;^DEx=R?6{Ro5St>
z?aK+u@s~JeNJE^O?5GL)gByMEhmtS;N$<s<yOMbEQ*eFn{^I|Aqc8rk<cojHd-0zn
zU;NCfFMji_%2`IFZ#&zZbIcR}5LK^X9Tae$@kc7@inv-L7DRPxKk+4Q|L?SYDAczN
zh$GT2{vtsm;%1{g`4`mOiqPe_ll~9ihU{k`l84F3Km!824O%3W{b+zwJ_pN%P?S(n
z{M6QPqrKzbdF!oA!EbJf;gnA&n|Qs~#E&GK_-`<$^rk?Q%-zW(PQR|*P8I2!64l86
zarY60!ox2oyYp_ZJD<6n7}3*PV@%gCC7bvuuZd45o4|mvd3r<Q^8REK@AI1YWU`5`
zN1z2MHJBIZ{@7Z`r@zN<O|_)I=(YB@erpPTGg?y-#0+z;@lE&+bNwB+>lQi6&GGOs
zJ(s%HeJ|?LFANL>6lYGCF2@TS3wo|YophB70E?AcNUrDqM3d`ZXOLnJ+H0A>5#^mm
z%u6@{pp5(zuI<k(dAn6f+|O?dckBOJ^43<t-?S~Zw(m<e@qVv~Pb8c8=53&WS<t^p
z>ghJ7mJp$H(!62?skD$*FroW+;~hwubrpgT)FjX%;v4sq)Fonqp(0Pc{%Nz}b$lp#
zhW|4kdfYwHH%Z?v_>n^Ah+lY(=`SRnlmy1@g+pF?{vEDePEttYe}B=NBt5e~usxil
zH~J$~@IPRLLS(}I`w_npB|tyqHS%?SBMSa!o$0WN-%d91qh1qFC!6>T`mq6d26n}g
zar`A_M_v-@27fWx_<Ov@Keg!X1nu7&5b^|$3mG1wQ~%G&#^04}{DWTOA5S*^t=nVU
z>?e~=e8_9!uaZrC8~WE#|L{(~DP6GN@S6H_zbOTO7n%aQ51k8AHbh7JO?S$PzZJq#
zCk*?83hp~B&Yz+Ng$4oi14443_!G5Xssx_w)f2!Mx5pW>4}UQldGaONQTY1;c{Gy9
z<C&m>s+Z8A1i^SW>TH5)0{VWKaN`F5jakz#@s41fVA=<%y<?Zz`)WgFzj&vT_})wI
zoEZ6)NMqZ{-2BIQM+&xrr%mb+I+7+3!l&5@WOGC(pzx1(0$v9Ok*NrTMZn)qc$Fhl
z%BvB0YHrI?Ae`XY9x*Rhbog5Qfo<cG{&^tF$6%C4bmRj^-8GuXnr*KPyZyAe^=Y#W
z&Z$Ui3(se^6k^mT7d&L4DDz)-gvjD27QAz$;9o&#Cz1+MI7Ms!CAD#dSzm3;UqG)n
z?S@y($L_+^q&A;7yHe}_oSAd>j+p7R867caaL`A9%s!4JBmf}=q{z(nD;o$PfVVYV
zyHk*oAVebZ<z29ltohg8n;B~f`%mu!=B}?s$!Eh7&4K*0_@qp#=l9@M)ahFgwfQs4
z1IsJ3d+D_`uzcn00DOvio~LeyFM6a7AT_`XcJ*Gc0~<K|&_e^cTxKwndoGSK;@o}O
z`u3hipHFL_Pe&`PT)cYe%<0GW&+WbR(D}=!FV0>$clyly3isu}%rgC?&(2<1czmEV
zxBQxwrON{=OM6!?qVm$x;=toeS6;JxdG_oa(a_$Nx#gARfhdY{NkD<K2F_e%TSQl1
z<c819ow<79xwsT(<`)?ly)b`f0LejOZuhzx1J3yx^@>F5Rrn%fwt9NzSLUu{&R)LE
zZ^I{2M8Z`!Oc5!`5N*N}WEMHAxg(iG1*^{QZOmU#A7E+nBASHX@9Z)b7vJK>9Z1g7
zGG8&jIJc}d&tAS7EeP^aB1Ovez8s4_gdcln78TnCyb52x?12c6k7DA#JIux(H7^}8
zdq&J!n;Fo7Qt<q_L)5U)`9gjeg|-)-oi+?8s0EV+l4Kyf=PqQ4bH7mL7%QIy6~V%6
zKV^0!Pd!3ulozpzY|-B-Q-c_x6M*4QQU2fuVh?^P``}OC+IX{R$>)6!>|UDuEf`wr
z0Z4|&7+#3jLf8a0!wK&p#w4Ma+Y3koZ9Qm%4h~5|g7paB>HLT}fQOz^eM0ci2l%z~
zW9V5gK3ld84zOlG(-;Odeib!#9HZ|i^yT+!<l-r1safZr9srl~Td1?~Di<QL3LgRJ
zo>R>3fY~>iTP_^q#}v8;VLTb;rni&u<-)>L@q1$|%=7yAzR1M9$i$S&&%?xV&uu2=
z*-*~sp!gGIv7SRbnBv+vukpp^$ezQzSY%}!^EIG};Px)gE-nR}(HF{kkz-oYOm^pj
zMB43@CoT(*1-9tQ+}t7<FsAfgSUUR}y^^PJNj}bF-VzL($5VkLi?DAD>WZ*$C<xd$
zC>EYA`zCwFF^UVbi(n>|lWWf|F3)RUbpmmXJfyB`9N7Ha+}!!gC<nuL7PCP162<7w
z>=nzD22+A6jw#g?f|x(8t}NqSF9Wl(sdph{Uxru$>(P2~lGr65SfAKJ1qvd`libG_
zdz%Lm4bD?k?4f4n+}vaHXXmJ{!T0l?!zW@@>EuQB=7r7PV13<pLp8hW7n(ZuIY^9e
zgqOJfK7VfWOA)g6TvGbPvEY|P^@G)m=uW(QKMmIlDu1zeayzE=rXHy_cVYJI6JK<N
zn~?aGD@zLt&`^;VfQE{(&E%M<m;#-Te9r^~KU7wMu?d)wFtwOXB<u%MgY^5il4DHy
zDB)-PkJ9qx7pc^8sxRmseC`Px()>Bs)ARES)U4TlU!0pg2PLPw4K!qSNS4!ad<h2V
zF*vxxm!mGuF38hRZC#q3XGf3&GLl6=`xYs30r>H%Z4Ke)P{O!;a5TY`ZH@46)U+j%
z7-LpL^&9!fOUv`i?J$WknoA@x4$3r%F>d`N#_T{c)0|tKXcFUX(pg<7bT&HbAgNqp
z32iRuj^!F?p8(m={6x7XP3TnIr6El9${atglX%8uG42fL(wsch4zn019@Z?zor=4(
zX!AYbi3p>QZ5?IwQ4sLw_@;ah+&s;i5i-el_D)D<BKS>F?{}JIh~%b<b%kyoP~FK#
z6BJD4Yzn&7`{4vXuU|P(z?=9S{0(jez<#vCd*Y??t+goNNBG2jV9_s#nsUP2w)Pr*
z()VNyoIvi*>@p7(m`oPwl#oH_2#V6XnED5*(t&%;;xl}Ye4#?$bD$s1jr5wAz0T}^
z(yTwp0Pwr>=C;=v_-7+;*j^+RPQ#f$gFrhJr0F6(hzocJ!S6L~9zG<$1N_~FVY5@J
zinTNIYkUC}n-A4Yam8dVm>QGE+0URrd5ar<28B=F6nS#n9z6MHcryDv7=+o0F3B+W
z9WpP+MP`7xqhG-*bKoewW*?m}ufoSQ)6D9;2gz~=q+Z$_959uPIXz+ikBqsH=BHEv
z-9I4DrcEA^*GK^^63<$OyThKo$99T|oNrPWxtr|QDRkQYkbV0c`*wkS+x<FoHwGW6
za_fVr@-%W+b+0nTD&K@E@XEv3cI`HIyoLJh2eamWb@pA8x^~`(C&>uhtv8OWG4OP?
zGy4pmekObxeNF8ahxXK)c};!1|09<ERO%WsK>-3E0_2_>kz`M3@Gv&<KeNHNqrnGH
znQgCfDs=$&1Gw`c0Dl6&ZP==+wg+S%AP*A4FRw%(2LL%r$onFYv3hm7J>9IA%cX|>
zn{Q7pzb4(Ey*4;gOOK4CJ65SLE$`_m7N**j;YPk)8Qq`uZ`eXlr8!w_HyeZPYNgpm
z{d9kRW=~J~WUJaPPd4!Xd^R22O*Zn`o<_0QF4RYJjb^LSo+&h1L%4Fi$!Tvo*9p6G
zP`Z;psQqzw(jj?td^A^{!rNQplZ9fvRWDDayOamd6q}89y--45DpFVOt5dx1nQ5Y%
z?a@Y~U8){$PtGo`%r7s`raKph(=yt^yo}B?TQiL*otxY~OwLSmv_0J#YgZbRQ!|t8
z99JQ)<Box3z|+SukmKd4R=Q9swu8H#c6+=~Yx9ZmW?QDXS#Gr()n;{StX&=}mD{aG
zb!@EMNQX7~TGT#KI98si>qF(K!f34=JXabk_h8!En78p(t<lC$I(9Dul#P(fHFDS%
zd0hr~C-8Q=(3osj$^{I*+-??H>0D2>*{;k?6<gKmDfGPADzwV|^1CP9-|wyt9ZHv~
zP4;O|`n9hGz}7&yc6CoUgX6{GcmcCh=RDf|T#3$Pq>9YvWPPUHD375NZ9FzwZtTNL
zuFfy69B8lX$zIFu3)?R>Tg`TJrdh{dthO$jUnoOuo@y2=W9>=o_sKf{v?r%A`~JFi
zsUrQUo+ypAk2TuI%BRxabvVmII?3VbYP5>&R-saC;CHfKsRgIUp5-JwJUNA2qg^Q!
zTe*XFM;^qE<YKl;;{cTkt-}6bD(zgx!O|KxAI3R@y`$?=N=rKyRpbX<EA~ixm;*3r
z!k+Sc4d=7bZq}<gUd5j4Qb`+#PDG>pNIT2Z<giE*98QGWt;5mHJ1q0glUBt1;%^<>
z7f+@8<?Py{P#7EsupH}Z3@Gnvb6oj0wtlg8ESM=hksMkFXb;z~P-{$%;`q%ZMifHi
z1!%cdEgq|2@csOev!oX|GF&Bsfow22x$O9(_EdGPas4XC(8wM^<CDedTpCBl{x>5y
zsX6Wq)#4tGbi5FO^fXH#N>xlU5W-}6dIp1*c_#g6hp1Z`Yu3u;I*_m61+PuaxFYyu
zEu~C#97pWL@+5HMU^~yvksVSDA(Sf$mkD*}e7p{vU+3wMEpvwocBwhrvR_NZV99N#
zOZ{9J0QVjS@ylbwryof3p0tp++-vx|XHOc-)+nRDoCda7KhbC(pRTnEW94SCP$POT
zPES>;WBqL+vYA?;HQi{p_oUA)rN07`Q=Lu|oek#OE9sR>m#@rSNFS0_nt4SUC$?HS
z#mD;5?B2u0#=~j0k7YPM-F!G5YjV#k!WJ6kLa9AkZFPDO^=77Kn&nczz7Y3cnST7@
z{K8y+7R%X@x$yC0#|kp3_Dq#V#~STMrBZ7bMyHRLE5(+hN=b;EVC*RnK`<C&>F`n@
zy6)BKAxzYG_0b`_>xN|8DM=qIw~Dpt;<4uROruz~bUs?BxbC2!=G+0rA?{9I<95l|
zRK0bQbcBB&X-(JlKxZwE>RwHTFIaO>xt;KMNNHZ*J*e+?ck*tFYe}1PS(bQ6F$xP`
zazI{^6Z{vi9>Ao!-L%TURrAF>`8Pno`tj@rBf<sgVyjVV1;lgAE0nGZ766GC%2S>y
zX+sBOF}V4$ypzS5_RJIzR{2rzG}X!6AkUHl<TT|fkES0ul>RDPCfsGa@+hCx`rtLD
z>%dup)-i23lSQ%&(&^kFUS_x1WVH%@0(`4L$gBxtRYl2U15>FFa7*ja#OQ&+!B&%-
znJN_;rF60=<c4Ey$k>aMC6ERD7N;lcwRDFvnJ0F=Ia$Xd;Wrl{3NaA+xTmL56Ko5r
z+G@1Yk-MO|i4xe;2~vFFEW=x=!F@6bp14^n9AiOjPXr)&UE-9EmTS`|a7x4F6!cGQ
zeQfTD7R-n3=0zwha040z!axXFpw_86*v0YbMhiDRrO5&YymDo3_7c!VKW^<^n@yDF
z&Zi&TllCjMM+?oeU1;F6$(b4i5#b5kfs;KDfON7b!_<q7A@Ea;$kZyXa1g2Nut~9)
z8?*a?+hMF$9W9<b350#T+^$Zw_MtJbyzMsFGhpIUd1@N`@MLwW-A?B+L)l#Z;DMoi
zLxcID1G)XVxxGWf71-D0eWNE@=t`kfB0n!A%cocosPxDkxKeApQEY+UpTtECjFgVs
z4ZLeLX{24BZdOmWvB?DI1*f=FE!Q!ecD2<yS&1_|L6gx+(jfOwvs!{6aWXxF7BC4#
zP~ZKPiWMnySw&zuJBv9?qu=0U^B9IwnQ2T0*n^!3i)EY2c_|fJ4WNovsfs0!Y}Eu<
z`bGw;ioM+^gPztav1j5?c|<5wq0$&{^Jf^`y<gHS*K&jHT#v<86mJ~@!aU>z|HR(1
zYSmx{fjh~S*DP;D%tQ2B#6at{TBCHT8efwHIB2V~Pf>ihYlRkI9VpumSw7g_$>a+1
zYqT&^twuhla(r+rHG&O`Ee=EiLNH83k<WTO7I$m_*7@fUDxl6}AOi+FPZBJ%S}Q^x
z!p~4_&SJoDWZLOmAi4N5M*x%Rinn=)$L3awOP4OsUYP^Wq<k_8apZ`I3yrdNg+l*m
zBbSq&$oof|UXk$X&|`p4_fM)wU{WeC)mh>!=&4S}3uG>(^(r(p)lyb>m%S0Ftd(*Y
z`2)Iyd6G$@USL4(=6bUko3I$r&Oin0bRZq#EHG~E;=zMNTSUJQC>lB7E{oJF73{TQ
zrCnLN@;Kb83kwVS_WgKyn~Dr5ekj{?<I%g+PzK70qgEQFFly%xx{*#(%3>J?@i^uR
zfAZXUZr~OCr+Y76L7sB_bp3d#Huu=vLQ$N0MNASlSZ)Ed^qq%^%QEVTG+;h%fYB!I
zCbNtdz@w->>fwkIO4<d(--*S(k*8K;xFL16CI|DCp=;M<YZpOJ%OFl^!5*bbvox8<
znklXq2}HUU2h>p~ulr!K*r+y~te1lf6>JaC(mGTSnBH_hPjG<4$^4xx9&eOtr$P+w
z70R~ehO0NG#~Ou6Sw`;7(NnFm<ypFcb@${3g@iZ}-rh;OcJqp$4%PyHwTFU1sTXKs
z^PDJk*kcYL`$Y~aSc5#IutK#3Jz}CnUME<W+)|}QjiJ6v&Zi!Awot4$tKeXL4MhSd
zFU4^N$q=q*Xf>`UsARdGVCD;?*waF|!<qLArOS%^Rc^>zBAoY$uvMLvAofK#DEAr<
zF5Q*}RZ-kU=pdaDCfetpsW1atY}cBj!aRHTR)#OMTELvG7FQtOhPp0$ZOA7u^=Jj@
zjG}Z|mIl<Ls^l!pw5BHu(1)}sM~_;(?<&Qh_8~bjl+jg7MSR06J<5q<nb}Y_fHqb{
zma>d2xC_sSWt^ae#3>Rj6GbT979g90oSE@jDWXhFLS@8fmX;RuSm>H|RKPh<xL`_B
zI#NytlFFiIf=oSCgmM!!YN}OkK#@phm$FZ>-0v<#0~Ovtok5|^>Yd`{`7Y&yUCM{L
zln-|)KhUN8V3+b-9&(}xo{%-LD$uNyCd&@-Wr_I6Jm9Doi$l})py#+~q&Lk+fRLJx
z<o1a~72GL`0M-GnY+*-4c~lZS3y_)C?bDou<p3Ni2}u$3ICgIlpx{4i22o}FL3x=~
zIFo^+^uoV6;IN7gWSE*d>gVglX8U-h4q{(|_;muZ%UF4;+`ti`c6=JUH|+p=>qZHw
z>=85=!3%Z*EJ%jpSZU}iM`2d6Y`5G=H#wEXBE;hMbTJRX4-Y}nN+cx6#OfWaiY7<u
zQmA9<AC-!OStUZs{Y*|4o9U3>;jO%aYstoREn6qs*tZQU8D+CMs4jy8hiQhycoLG6
z_5%Qi>qd*fs8Y&K$O*JYFC_@h0)~~v)N;Qcz}nTykVbV4JzUcP+CzjbY#BwwbpKvx
z@xqeANeGR5(>Y?zC|$?UN!0nLd2OoHY7Y`QVoV2=2MPhQ9R8##M~m7%uWTn=sDVlv
zqa|$3QJTftqoe8mdbv@pkK<BEPWmBLVM?XxN(Fm0{a|_!ry+#Mlhu~BwE&C>bQq3Q
zaS|k6XO@Qu+p+}0JhXDLT|8B+m2r-E3m#W)d+ffhLtuxlrrqEVgs<3%>Q*b9gdE;n
z86DOa597t6wqbXgHC5s0wQQjP;erZbw@zDnXeTZSmDflyI0x7|Mvo<|8gXdYGqv_)
z)3R3fChP_GS*1K#hfc>CUgcJ5kdNnf$KJ=L8>=?4)k*1UqtLoE(>N|7Vpu7bGAqWb
z;<DwLlkl)(s)e*2vp4cu9_!I#_1wXRoN&EVh^n{67K>dE^|pJToja0V3d_`g+Y0hR
zckD`FVp`yuu<d8+Jc72n*3i|pTDStET!9k}$G8Qz(mzg?U@e*=X{kLWl0dXbNgXVf
zI(sUU#fhs-oCC?*rG$n+NV)ihdcX>GVOfKP*z#Cv?8a%RniIGp4pO{0nQLJ8PUfsV
zKDd=ZooG;cE#QDo9m@gBmkXn52rwOrbwKr*I*yq9=B!pDEXq-Z1!KbHl`HL)PU;Pu
z8&Eu<Raiipanc<$8_8PIRWAQ{v)Tsgh}vMYjzMG%v^(q!XdSI7+&-Q)#qFlym^H;y
z<?d5mhU#_qNnhG+IR0U%^DFJMvzJ${UYT1?=d-!N>`=|p+PvTlJLfrjC(p`Shm+RG
z4XgYf7UhQHlYKB=MF}@Cyl|+pAF5L@_mtD^_Uy{amH9JQSLWL7{{Gp8$7i2dMqd{Y
z>I#Dq0&Q33&!+WWJ8P95mNRg7(pf<)kerAB^KLZmR%%!(swlpnchsr^rGr?IUe>I|
zxSECS{baQyxT@vuq=}I5<doJ9@i{u0gpd%ms3tJ)3nA_H3EIWG+D$t^17ck|j-y<k
zsR148Whey2A>oXua!eK>rs}qOGf`25HiW{7QgK}Q@~rjVAl@Jkp&%I^ClCH7t)?(|
zz+!x%*M1V-33)VRi}EqwTgO8r`$)+42xnR>66qHQrz}+!Zb~+&)2adML^~0Oh6|&c
z-1>Le8<{dJkGNj6z?nEr0JXK%$}}(y1Z7alR`s|t&RBbHn_zv$z!OkW4G)IEas(1g
zY}_bM7V6w0IP|d7;G#IbPxg#JBE>?p$wHu7g0hgFhcKO;dKFlvRj-QifR+PZ%huKn
z4IKw;j5TW)qFHFV4hM^NeXIb3>r@%$jN_BpbWlh$tdv%#j+YxP7-p+e^%>~Or?bi;
z(z*;1Tb>-Bu9fo9&7vGYw1RX~dXApZ{{RJ8b#z2<7agkLLKSjLj{en)W2oG0)v2%v
zAF?tq$g@07-6kwSG#kr3Q47t+@V$wZ&;sqAl3Iltr3LXq+LJy4d?agyDi%O@ub}xo
z>6hO~o9cu_qGA1;qAf?jiT1-D&;<r9upMAdtX6cad%$eA;UxtJuDqwFRE2;W2#8FV
z8kR52wMPS`4pzf)JcA*}Gl->e?r`w?T7^^efU@3ko?cF)D(l300THlHBcb~n><OI%
zwe3-?Zp?^l71)X5xO2*(rBrG_30Z8UUwg>v)o=sf3lPX2YyGd)OHJnqz-t)|u@jVM
ztP5S<{`~0tiVBeX^gt^qQA*NLo=`Sh5qt804|YD_L9s(DU?_Mn8<6No9A}zzMW7pm
zOhw#EoA+tEa=1bhg+Mi+tCy!JW6BZ4VgX~TmPMo|D>@~BcCongD`2q6UfKO)#SK>~
zZ!1Ggt(76AD7xRT#E%o^Akv<Yu_83=C-$Yo>-IkESvg|ZnZg2EI(WnE4<CxLKMq+q
z6MTLAR8n&4Qc3zMtL=DAUnZ9wTc{iq><lxA?@f2m;;xEXk#d8&I>D{%Gxyf<Vw0+5
z{7}{E=FZ9rT`GCYVi`~CDF8e=C};sZX$OY^9EDE)0`gRZp9KODlv2meX+W&U3!$T+
z=|v_)mCoYPmhLCbP<0~tTKHdD_fE$l#9-2QH!d1C%Q(6)aOT?3Q|gPvIf3X;UN6d1
zOA+*JI-&~!uEw*O7g`Hq>svmBK1#pYoOIhN0xiom7^qzK>uC-c4qrPEz@*=H)x{!e
z?VsdOEH9LV%0u#Q%Y4G9CVdhPC2&#bpd@#`3<{EV+@vMFYutge5^eX2(oR5yVQK`K
zraRDnj^aQ>zYI_am*@Q9HO6z$yZ9xTj)U#Nkl#TkX!n?@)vLv3XwG&g(U!|maMZsv
z(}FuFnHXSS-UyU9f$kFJYwc>|k@4BZa|m7%nN^%9!ZKOpMrj-zI?XCp(ZNm2El7Km
zs<YYau~46#ESJ}k4;!!2;j{>4Xtg5jrhf>OH5|;P?cSnnF(?!vn1t~nHCiQV-|VuJ
zuc_vn%?6O^{K^y(IAJX8o+}KrM!IFKwI?693cEceuE>Iy?1^ojsDd+)-`tSmok)?4
zP1eoYbUQM}0ZbM?>gXXpJ3_0ixpb1tH3@5Jl*1N68o;C>&MCPus+X%3nl(gmC%m%9
zD#Lopc^jW<HjCqMGLA?O!RC(D(w+tsguHY%!Tb;>Vz$*EQFa5_gTN(G_lG>nOJG4R
z4V(_JI%2!m%PBSZ1Met>>rzR2Bn!14<Q8se@u`l&q&m5C3KUs5gOZK5nksv+W6<yg
z`{V^4my9upk~t40^WbE}{uTp;ji}-+g6+xlL79d#P^g`7WPsY>(ur2P)|{bw%Kq`Y
zYVoc0cIjwm31IU6kn-dB=e%XJ#NS^xJ;mz$#+j!sO&5;O+I71|l{wvA&^(oZdS3L%
zh8jR0(OcyPfYKworf$_^PS(0BLSQ(Fs&>fl*YlpI!+=mym1E$o!4CE3f^wy>aSud~
z_zD_xVlD_34x3%)P>CP1*Qz4*nQ^R(=*nw~%PKf{mIjfDoH`D}U}=7N_RPW@Fe#Y3
zSV_S5>r{$h=E?k3YO5)AiUvR(b9BJge=yj?cCKY)0Zisiu#tKcj#tOVm8$5ycyL3`
zJOxxdHco>LHph4Y5@-#M5;W5UcaEutORwYUamf?Z6V>N)Wg{iJIjm9G>U!OsJRc}5
za1h|tYGZyl{km@%&=ZP+ESoAJM4<gJJ>h`uoV@AE_v}4fU4#N_@$B5*!%b1+1vSML
z8nUT<&^iYxK5lv(m!fdcl~KDLe4H*DBxcdWu@_CHU|cXvKwdg<wO%`|n7fmKLx{xC
zx?6QRK$Qoh>_%pcp5$<F4Lv-)LU}`DY7D$HetqXg-l|U{Rv2Kev+w(eTLlNS0K}cl
z2E2_c<=XLDp!*t&0py)BQ_;vUcPxq8gaN^RhS)`Ccpg`E%_UvvuAJ)tRbi`%1*$fh
zdNS>e^n=u}MjSQXs#XR?;S=6=>#05a?5I7f^#)=J;C9o5l}X=7-vC(ATQIxgulSrh
zW?Xr{2wcvfBMQzaX|cIIv~j3B;&3nYS#UWQWdkmSnITG!7Rzv=@li7{FI2~-$|YE0
zl@qoO|LsO$YOLHIQs#iX{h&kOm`c!5pN9^%K;vYEMicxgh0E_1N)PlsO=z`X<35-^
zIHR^*_!v{6U(XFiD5cm$JXkPn@H<Y_iCBX<B_2%b!(FUFgGjvuHO*A13Te2V9vsR!
z$5%1Ho`BP+v}7k-1@QnR4M~~UTw&SKeM!j%XLS4#%nBGsc-ih#m3!!~hezR~PI5z9
z&N!L^xKC&}n#V%VIm=#jsv)n|69bFMwDZ!N)*G2rp{-V(-I2u!VA2@GdhUF+s>1GG
zgAodwrC)wUGiR@$k&}vY3%}Z_u^>LKV~y%m(RoUAgFDZNZt&bb@O(b6;8{yWxa7QX
zkAX!igWAdL=IFua^%VVpGlXgc1`&|5hp^@~Y>c|TSGY<+@aj4h(H`tChVlwcghiOh
zoN=Dk;%aNM-9lTfE6CnDdUY8)hrK|gmUi5E7b2=bdq+#J3`q^$p4TDVv(-gFq$%F1
zs!0p&JXkA9$Axtk6`@O^JsGNmQn^xqAG%0$#Cc(nY#Bu;ICS7<0wr4L#ux?5t_e9r
zQU}j)7_x@rqm0TBg`aZtwxEqC0Km#ploVnOCukU1>F|LOYYYPfU{xbPYoC;*;*>YE
zayhP;+!V~3wMWx|DyZE)a}_Bo<`>&%7rtDl(;fv~8ZIY?%9tHURbkW)Z^ENxnfn7Q
zp`7k>tpQ9XiDRSpoM2<0WD39%O^Zi_C}}@}0V^|VgO}}1*bh}~y1*ZI7r?=E;*i3U
zknCmvl3wCCU_*$j-+t*6lu|4T3~t#`=p%zoD<W>3jkFuu!lYR}wmQK!K*$OivUe@7
z#`&ffH1oEV<{z71o?lu_>*f*=J&za$g`j6d6;DqE1cG}QK`3~Ys=Pe4M0325hlE}@
zd-m$3s|&L*SXNtsf&yxb5PoT41+boG5ze(Z!*E_`fJQ@^Z-anxGd{205?(zzox~-U
zl~=HgJv<#vIF&+32z--O>F*yBD?bHtZ=nB>N3Hziag$A}=LvXFbVx9m_3#yEVYpB!
z<yWs?S0<Z7SbnSg^zdm!m<6|T9PEJNvOI8^Zy}KEKW&HsTo7#Ut}u`_coM<jnkOMx
zrCxJpG{<_t_t&eJXT1aI)$28i)D?ih!Vx4N7)bJ<vv#fk3w@8rX{4<l&#U?)SI7?1
zQfS?P@{8wuH=sOrhPnYco&X!Id1|Ui$51Qn(c3L3(<u*(7!b~)8z{7I03@5Ig5dB<
zo%<0nGz@r@2OK972kL%vmQdh%Sky`|h)VZp{EKJ}!F!NZ)xJ|qg=P-1o9eR_vpNL8
z*p?P-womqSu$!N?H#)plK~1eUy51<$x(|Au?(XQ<d2BU*bSD>2(8o5AlI2d;NGD9<
ztcnmU6YQS`XAxxQgT5M9W*<jFrYrM{7wD;x-Ji?WdKhU0y9=Dib5LO;^avY2UIrOd
zG1((<4Qf6z1n!!Y#450a(RC2r6QX|xqc{rxAj>t&jdUHDk`XLX4W=s$HJIYihYq#r
z(GKo(VQKM#{=mDYr<0pIkZR=w_~lhR;a!!0JrNpUqfwo@RA{BvXy)KI)GT%gWF)r^
zB_eV|c<h9w1%x@#B3dDV`Vi)pKz%5aiQ<`t%A%WBWD*E0K*GY;V?NR8)r?@=(Vh<w
zZ}q8|6)eKnH=F6$z4SEDaUjT_k-OLh*daK&c5i_EJrXMNtiTX~$-W_ZvRZSJry=3s
z{Q`NJ<FIAv;<~RGP?{xa9xZ{vfLkG3@YtXTNGh{e5Km|WkYi`B<<0RP>ll?^5>^zl
zBgKBXmM4TvRd5n2D@}Yw;qu(Mcn7GmjaHCuaF+3E##`7PTZ5<vkcuK$FeyOm<jfRA
zMc4*Vu7M?pcE?tL+8GuD*=6)Nz%4S`6m8TZ_E@oqz}{*g0!C3W3B{0x6~U8R{E<3U
zkgj-SztMJ{ae*-DJW)x|>0-#g2htI@Yg;HY=gtou8UrIAz5YXMP!c3hax-ElO~d!2
zg;~rGjXr@-RH!~6cK~d<$~t5#TTSa@Vr_8TJ+54a6c{fMseA&VsB{=bpeiS;It3?1
zXdh(9RYY*A6w;A9=}v@G3Bo)i<|>pHxtE=DB6P`mE04>hy0A7`S)MDnCpMrGsKLRc
zM&utz4cTjjf)xQnFVWnf69P2^4N5AgLOQxn#zDfD;FPGV2m)K-0iP2b5G|Z;<^#hO
z?Jo>Etx$m%=jh$K#wvvyXqu=U$^u66s_MWM<OO@;0EEmCJl33|2aa}RgT}Dqk=|jF
zAuC9A0}&eJ4J<kHd6d)nq=VAb^!5Fdrlu{yu<3g`%d-Jc1|vJcDnzY6n7fmOMOUY0
za5@`hCK_q?Uz&aR()=D!5U-epX_Ts76w;>E9>lF>f&_eU&;xNIp#MJK=^;M$E`&+-
zka%bSVmG?uRuEB)kt)IZ^IVdvpbK*BweHzS6?r@HnuM55CKI^0a;YeLB8V%_xm^<a
zXdi6nu@A64ladT(*CUWgcu)BRy3Et9iH_730Q4>8c)e}|tJUaeRt;d%S=j_bqIk5r
zSBmWc2E{%S8~UIPL-2XpAkhkJ>{dmh$3cu6E-P7}|M2}Bqv~l9JEN#3??hZ{sZbf0
zQv>HF$eiUxnsk~7WGfaHXBU<(h(MZv>1^0tZH2QuHAaxJ3RShlSsR=;^Knp5^NHow
z{Mpwatqo$*ZQxlTMeOOp8HcJR$}ZZnV4>{sw3u^WTISs$Qgv4r)eX&GaP$ZAE|pKF
z^BS5Y8kAz*)1cr+&Zst{=Q@)AiMtijS~if@vMQ~G`-{n$R*|G38i?7kg9X{8b%IbR
z=i0^UD_7{9;W$*!5%C}7Xwjf^!@zoA_3H6b8KRs!NsT3*iE#Z9ej9CBcLmvWR(y9}
z8%~<XLVM>aZr`BZAT*eFVK;@_+!ZA7!Qh2`8m*S9bk|MC3#8K#nyPA*1EC8*)GtU9
zB6LGT5f37*>7QF+F|A9u8o2Z7bWXm}`V9|F)fukm-FjO`H)M1_+U;mL#liLzVod_Z
zQE#P%aBeXNgWg_xR%UHJYt=Hcn*)hP&q#19uN3x`{%Fd_dS)|)SS6qy3&nI{C^4-o
z!j7wu6ByPpIXUS<Y!S$thUWLMmMnlH6cKl&O0#f0lr7pwSA)<Uuq5S^bqI+4dvn=5
zLcYX56F3_NT%>!@`VtAJ6RLOs5^tkDRi+*t0&iejwP?z#Q%}_KP4aQCFVR-1wcdJ|
z%Ur3eJXAK3JDGB~m2r5Wn|F#VOROzY?_9^ulL{Q5W%cQJRF{)REKnZMtxBh8gkv@%
zih~$Ps=MP?s<_BaI=;2r^<(3st^Pt|EcY;e^87&nYCpD)XSxtL!Y%ed&Qt}tYU!a4
zOIAb}DV1e>W)PQrg0-nuhdwuL37D#^5h7t{QaEK{ZhBY(2QEnL6yBT<1r<nvj0DSa
z6L}%6h(u;sNHJJ`@botAWI~k^fd+F331jr?mF1P%+~Nhq-tBK)!B;WPBc-$;143z+
zLQ<JAh$H)3uu3*7&_RlaF5?@RDiSu<V97XE{--jQ6R3k)@?H-WH{hQYy|p+4i`W5I
zc;vTpg`Ttc0$}=~Y{10XSoK=7RJLbM+)k8riH48c&FcEzsfu*pI~>qWMETJuOslIJ
zQZr1|Ve=D`#O+62GaSrqNF_Wdoew9}SvKcnC)>S8I=fbrH<yZ&q(b;NT~GTrGRLAF
zW9TVl3twRt7Exc;td2Q3#8zq|+YY#5AS(oZxA-V1yoZy-I!OPx8OAd~S1nj5UaHu~
zc>@RRpH;ZZG=@MO4Llx7;|<}4;0#gB;YPe);)OCghdoE3qKht(50Qpt|G5|$&ob!k
z%VxrDEe4c^<SaYwn{6mhyC^+bs)!??MIsS^5C`eZc>anVk#httZ;z-TY~(kXSqhf)
zEfk>=eAGme0(+;5!|G6@Cv;ISjkQMAox&;`Vj$@Yl%AB$Io>4W90y@~L~*-sD7|}O
zVYi?bARfAKBC|~*&ym%OgkX82I|<@#N~!%M!Un7>H8l-*DPs3wUqh^?J%T93Yt;Ls
zRfI>F=;_4!L~dmtK?J}lbs9)ryplIz9iSKwxk>g2vZZ1KO+x`=MF@j*N_dBqyfBXW
z2cRR4v4=za!lN|Bax#{}C?}(D9Y?4VG8n|uAK7B0KD7Cdv^Mz~D%z0CMs(PazGv$2
zuL!td<f5YDH41dDTR;uL18U%9JUKWWr7L<ZGc2b@J<L05K^@3$ES*|%3+UVpC2Oos
z!7oU{N08DN+%A;Ap`F|Lze5DW)(GQKffQHvuxs3BqtlftlFRA&wxKN@jj_1^==GKp
zNgO!joxH$?69^V@i)6re%A=O`<=$sfn>-ZMlcR{Cg*dqkCx-(#<d%5gpht*MI&vp7
zE(jU6x5)yv8wj0ZYS9DzP>JEZJ`Cn~ro>ft)x0XU&K~9q)oObNsIUsT)e|#urH;e5
zgxFa@YCLEkH8Gy#ILKx8AKbt1;9zcW=)k`GU~YK-+(U!e1C@P4I_WC3bTs}ukTk6;
zWTh27=5$Gjphnfs(tm0Uv&MiXRiuV_kZp(yhvm?UOF&mfjAD$QbgUx15k0$0-57M<
zD!^kvulp*e2lahV2kb9$isEkJf)wG%g{hp1g(4oW=dC`lGrT%Y?Gm+&lDLq@RG0s(
z4QCKI&ll>jkHIUA=>{~D+iEFk5cj5`RKY-6RhWJmCG6&FFysrlP9a<#QTy6-9d13j
z_9BATEtcl`F>^O4K29!13cCd3+?XgF+_#s%8?obo_6_z1w2E_%r)5*v@THC#&j2PJ
zk@HfA!4Wy@UDtiK#DRi=R_v*F<~PLwYJC&o&{tTDc2r}qRF0;m5K)awf>QwY#<mTa
zh;VmWO(khwI@ph1p|tJKLxORQ0cCKa!)?<AgmazMiL{yM;vAbiAHcl1$%5!2-rT7T
zMQ<3G(`)pM)k#j6+7%YIL?_}%3YY9Kd?LfRY@|q@3M|aLkwLrE7{dN`&W%APKpfG;
z1r=dHknuEf*<yx@RWHUFF&T3Jb5jNmiZPp=Q^1hFib3i9<XnKLM{t=|g2;RHg`Pmc
zNRT(7^FXX7!X~Ujvj<5wymLgHGY)&vxOM5}=}<Apxh$xiY?VkTtzgIMlxD)wMTQ*u
z+F(T3+~5?Lr`PsSwR(ICAV?1?;E%O<w3^((Lf-AIEMwvvNn#pwL;a9Ep0M14JAUk5
znxF$U)G1i)nG*J7R49l6Wqc8;VHs*@uuI$@@Ky;GbrmoaP&MgS0>&1W&de@ER8ID*
z53ncOBs!9+R(6lIwfMpUc{JicxL>(WI{k?UksfLj)}5}S8s9p9!7)o7u=7Go09>Ub
zcQQvXw0mDkKzAprP5K)_1Vl{Z=nTHwK(#7aKzjlIRPTwYX^W?!8li4PD@W_VRr`3m
zapL+l+B1#mRcb-SfFv$L6;`RGZ(FS$TSMOF9S5;#(04o?oRFYM=89VqY%F}B5f`L~
zj4tvb7>1sa$T$@%Vd9tN`7fVClJ<^_30Qi`)-_DV#6DZAm8MTj$;P8136AWZkRb#M
zJ@r53(cu#y9Rv;c%@BV3BQO#BiHu=#grg~czzJ|;S|&c~PwxX{o5>bNb}zVB76*Bv
z;{`H-!HKC&k75SJ^HJ1mGc|P%tj~aXXq43lQDzu3BGZm6xR`gzf-4RIOpEIZq-~+2
zLtW7@`V#|M97KzLwNb0Hk%*o})sq$|gH$PrBa?)(R~PYFHY?sqA)P3vXD9}tZAAf^
zu3-#0hsH_8(F}|emP7ILYHMkrfP!ONtHn$bL(zHfR6)8Xc)=20>#ZpX9(_y8sN}h4
zUP?cIZRZ+xyft_WN34-a*}hv9jj?LBuuhN+L!K~a9SG<QiV#`ge|Uky^#+qCD`2^T
z4q)4-sp&ds4ctEvUi;V*{7&)dfpq`w#ih%;L09lD2pYxyYpmkki9-*KXgE8dkp345
zNFzgtyv0&2ajfQdJ4n7{+ksq13M1RPBzZSA&m%~h{f3NJD78H*V8xEmRZufn73we`
z#rC7DyiIAPaKEEUUb$A5t@L)X9ZR%|JnYPua6xSsXBvpFP%c3Too;_&@?BS~iZ@iw
zLjX`JgB&sC0&^rpk{3NbH~SjUdKs_{D7WfwcPA5~L!*}@jtIZH<S$MFC_R@D=)%H<
zrRLni+}Ra4Gq)#8!?5)ty?miIHjSuk1iO%op}5C>97&RMabm1I<`=tRIR1uM7(NR=
zPZu&cmb>>D9G~AWD2F2*FH6`We)CFG!h0Dx-^SgiR_oEL=b?sg&Mhu4U1=9Do$Eh)
z>73AA{7vsUbV#KGrcSZX1@`Xa4f><DT632!>*MI_%e`7Q(y>D|>+)|ieY=zm!L9UC
zD3X_f$anpZQ96sR{KNnuVYD2HI~eq%q01e@N+Pjqkz(lpH_&J^hi}@n9<c(TC~Nu!
zAl^_6%YSX!zt3XlF=he;8-M7m=-mX(wj}9#YfLx3M7;UTjeInUp#`4MIpo`3bjRxA
zin+yZVW2Y6YC?5$yauHUjC%Z26%H(381$y17(5cg;--s^C)9G%H^oaB;lPrPiAjgS
zGHB+m9?|BEpFrlKRs$9`EUG_w?i3Fa09BW)r01QI$a;UUofA@=hzpN8@e<v1s3OOf
zx#^JUYy1SW)X4|1#!vJpRSl5vbTK&7R<;Aq_6kFfBAl&arBJn;SRnVSdPp2kY?cm~
z%@_fOZ!9?_L70EOP#G2kA6?_&1Xq`{K3(B<M#wZ*nX=?K!x<T3Y!N#95|Jfxq7+7-
zLfyPuIF}&{$DmScjt6ujRxa;ao?ARu!FM|6WN+ckq7sivKMfm=EWsA^&zzhrG&IN{
zPG5^ruq;ui33eTXAMmrrgY+*}G)Req`pcYrMayk}dn<!-lnqo{vwlc711y~YOE-Da
zIrtVbDwO5i2Y2CVvRaysLVN&|=4>w||Gj5IpmHf5JLvOHo#4`*n>&Z&iq%q+IUN8*
zXaI!<SA%LsCP;&)5S&>{bsGz!pCE&9rb;qORfrjEmiw`iGb)YQD~MXLI>?gBK+mR?
zk-FD|g$|K86isQcs;NJ%4XGT=1zjAsUo~<cHH!GqyK%%T$uxj-qE7}*@t%0hQr{m#
z-7(;H%SElYJ6Xn{b!HSH_8S#PTAfFi;)G13O~$UGL3l5X2xe19R4Bn@2@nBb`4T_y
z+hdxfD*;RfBSny|MY+{cs~7@x^!(}>=m97Y0$pKii1;iB-yMO5Z)xU$PMXDh$G3z)
zd4TvwEm*)mc6b^f3w97jOzTOXv}1JwE3c*>*|hm0?M--8L-#(&C#!yFjRK6|Ve8im
zE=gR+BuuI#nkswNEz>WoYKL0k%;a_YeV09q10Eq(^sJ~qqIE}%fx=ahZ_(j{l}IKC
z_AA<n(B~qkAP<u1vPhi<b23Er8Wxpy#(Dvc9lVG@SgLeYcOQJqRW)EYqsSyp4M2&d
z3?w-WAmQ*;@nh|M_C{7FLT#+QBhY1AzP)oDX<U$O6TT#xVHjoUeyZV>xJfo3s!DA#
zAmmW+45<XzeMdotvp{JIku(|y>u#i<Vj6<XS8GOuP_J0}L*j)mR50)X2FN(w3L#QC
zs>gthu<4xJZ33Dh#VqblI?|EOF*{T2z>w>=7CUTA-xW}AHI#-A#{2;V>%{z7vk}pz
za}6C*;GGy?K>w?f=+v{01k>(Dze^%vK&u9Vt^U+%abV5}*c^5KSJ)i%^u`BD@C_Q$
z?^1ibUbmkTb*`$qRPIieO352H0}T1mvl;=(%vm-T%o)#dl&eFCxy9?^eAQ8XI;<fK
zR#x#tE_wc?b^B=*`l^QLtjtSQ5hTlH7>cNavxGb@g1N(jpq8+cbV!I>$Mra3CKM<G
zRySBC#)L<C8~EOt;cdJVJ`$#BGXp>mM<T)ja9HxAu9k|~vra5Pw5<BJa$EtY1=4ew
zTE)*1k7L27Hi1B?aJ=U72Z(;kvHgV-W%Y;#E&`IFN{${lGt|KbBNWg}+!HCJ+LDO~
zi2XgbgQY&(5oD)A+fcs+>GE_3z!E6sg6kX|VVaO!r5q?X?Y#`&(Jn@#ft>`;+u-K~
zqGRe(Nk$i(bjhAJbqWeG=>b>3!Q6M>8t%Jq@(HdWBUjgI@&fK292nZvm<(yyDVO0!
zK;<$9iFI3*U5JBi0u#7>Ac?{>wxGIyaewK_j6wAHxsap0rDNf}Or*6@j3Nq(kwQb)
z>Ts6L?Hiq&m5ijhEF+<uS{P>m5+y{9@Jrs5D_J1hR#eRWJgS~0M$%gkqM0Dv-ez>j
zxzB4@CRAOfoumwu5`5FsGAuEWOtbAjdR88V0Z2H0VaOui4TLjYC9t)75yHNBp`wom
zl=ivEkjcabAQ^jA%^wJkfcc7lR_W1iPE(GXF5tVB6vFY%MSHK_BhnP4+<s}8hz<%B
zDCdh;6>It#2JNPHev>@;J~-$m9iAxQNM3)Ks+p<AK8ue7y2pcE8>=bJh!qzf!$peK
zX27YrC!;{AAJTO&B7tAORa-~D%p0NRFk15D@}XE5sSOE<$iUEaa+C8oOHfDz=oCNL
z0rF`Q^h=`}Ep6Jb5!ldj`f8>9mN+TD?KvgttB4JGHm8|?S`2hB(M-dON0cNTAw874
zXjg>E-A%jGu6q!fHZ;J&KylNL|BKd9{zAI6<@7j_@3i-84G#hzDl2QopP6PdLASmU
z$J{7h>{vxQCUfQ~A49iHKW->mK^_!xWCNIdV=G)7u($OqZ{5CQ*QExKBsFaK6p+gU
z&`uAb5R~;mdiTYPyK!B>H}yIPD8?Y_xe|Wbow0Q8Y}ovY&^~zIerE+4nQ{RE-w;=C
zB*5WxD9IaiQX<)Soeuqu_iEG8p+;22r9ua0nkp`QJjr6{z+i$646N*i=nH(#q+)AG
zcSEfYK0L)tK+*k@0Lw#e7eU(sUmox_$l~twDI6<yXCfZUmWA<HI0+>8h0<|;>8gaq
z1=IR@fAi`9_P-?vla<kFps~qH@Bu^Mz|d(P%jVUHj3<matRHJNPAW~wF<dR=txD)L
z6WuxPiWG<0Dl0QnY6uA~&@@v+DuEV$pgsmQP{XQ`fVK2qiFL4Lq6;9WD}YIFiG!%X
zsn%cs73SV%HRuPbl=KEfE8+DBzf>+%z<P^D;}W3kUo9{J;2<)=c19F4DnD5J5_gRb
z!}6tpNNo3?JQ={;Fkogb+{n5M_3!w#Gl6vc-kCr;e({VPxl82bHl6s^643FRXVMl^
zcgZ$j^1&ii7Pv?!N@ObB0dZ<chMP#NbHF?#An_^8TVdKNVnl`l5+OCLA4g6n=C4*K
z17}`~IJHqKT(zDqmmjhg*UAMjSuT+YV2)Q4nkN$YWjz(9xeo&|^)@{7kuW92jyNH*
zIcz9qL>%B?2~_TuL2!Y0v4{(8`Hs$k_DcKQ+<APr<s2A2;runN3h~Q<1WM~rK?WFd
z8qkG^?>Ur)&c{AtlN9Ad;B%#tI~6E=h&+uBNImu<8Cl6&&@A3SYC^7ByA1abyNVTj
zQ_67}ejQ;%64mTZV1pA-U$q;@+7mV5P{LbVhvOxk^<yNySb7a<_gU*T!lzc#YsAD8
ztPzAq24rct%?WY{F!u3-8y02K3s&)bvWmCFJe+cT@GUfi_z^Rwb@2)DS^BVoCc&Z7
zF_r@-EMiEHAPTy|HBN@ziij`{CjHTkuZj>i2p?fu?Tm6GjugXsFXkI-3#HaCwCD6l
zEu{8AQUi=_kOw9bGVUPZ`;`xl@hb9#b$)prYS$^4ysJo-j`WYJNDck2{YW_OMWisp
zoAGPisI@mP77VT@P@Kpaj`S%44?E^E4LVF1-bZk(GwfjT3gvo$V57zI1bc`teoWUu
zy{D&g`7?50!jg6_Kk8%(czGcnZxW$JJk-{-TcaV&Qo{xhtN2ve4|kB6!Al#^kq;s&
zIeIJa4>1hX=p+e(FU0FO5wNRRCF=P=xygSLn8sm924R%#=c4s1K`LxI2LsE>;Pm+V
z0vsW6UWk>I^;sJSlNa-=M;zqrgg{v^UFfK*t9X}06T?O;giEceAgdIxH+IToCnh(d
z$540{Xihp#7$VrJo-!0-16-B7k3jM+`~W29P*w}7B>hTR@$$loE?}g{kxcSGLCCk<
z*uH|b%!4-w$%e%%M8OGIgzQD^W$cigCRtS2<Z%WkoR<l7BV1~f&{`jy_aUe%YhW!I
zQV?eLB3tG!F5)uSc%%p)ine%*BJ4~VCrDkAcq0SjTr(3$VYKl`C+GAKCMz0lbE-_e
zo&6vKnx@lq@t|7?zZS)rk!0DZ3QCR7VInDOwaEwsOGa~w1l>o~?49(B4};NHH&JOS
zxDz<(OxyFcu>PWc9*}J0nB?tuZtSVioewg~%xLH4FW@tF%X61!ugtD2A&6H#WOvYh
z!4Pd?&G50#+Hl19=(-R9Wrpba;(uMp24L8MN7WVbg;IR$Otw`w!LcJ;H`oCoFV-E*
z-UPFUEKk)M^5x-E=1ieR&4c1JYW~2PiEjfYwb?o*$&>|+AgeKVL<3GVka}u0Z9BXT
z_Dn^kgNQ4d2nL=a3^s1TC!8qNgAHA^EAR84Fy?EtC$}%x9ozxVCc>n>c~J&9!m5eg
zAk3f<SPX*4Spj&IO+tAoNeD11oFW1gYX&B4`z2S7&qIfTi5y6lH^SuxxhEjD!7zx-
zR>!o<(=*7t+pkHsL=WUHq44o4+V9EJtJUg$u3Hah?l|RP=QRO;oD+y@4+6=ZP9SvG
zQLvs~`f}oU;=3Z{B0f=u{MkW6UTSA+^hl(8)=j4<Tx6E`OgWIej6KBmf_r0bTv~KD
zvWEih7CddtKQ{`JwrCG+QV9p$aXe5i3iDrGnQX<@)Aoq~spze5B5ElLlj?%FZLUM%
zFRXQ0CPUFR{MYi5fdFcn<d@fdsI(ZEU2W21;9<CVkZE;_Zd=eUo;)cZ7uB!niMz%i
z*8QXnR|^XQK2Fn;2ksBC06GWNZh&lHu7qw5W`?r)1Np(BeftIv4CfCV*oUCP0~J|(
z`6gJk6maDpLmPmk!MKoItv08tP+kWtoRg6qKsH72)Rgs>!QV$tGVO<G^j!+N?$zYo
zvT!z{G;aKh!lXK75uh9FPUaKQ<8RfX5m01Y2^*5EH5GP}B+vCQQB4|A5{+1^TA3z(
zxKbBS;WNe1O{NbDa`tUW<TxVIKhYUj8km_vkRshW)B=r!(wp^(fybR$%90{qkMB5A
zjWn`SuRIjf<NGwPQKRFEUxNLJBJGU*PKRaS#4_lt*-S2giAeVo?YpURA9vEvtcCjo
zaQQq#@bxu^&uzRG#X-U6QOs?Te!P;*zia}VlqK!o$R-Tcfnem}&JDibZ40~IJJpbe
z`O!zxf5d<`rqhy%82k`)7;<=U_`zy1Wf=rFn@y2#cjeNAKb?(QJ~_cCqHUI}@Tg;i
zDLFek1^hXuKy~9?wzdifm3J|}0#7|W)=N-Ww2}Ha>WR5u%<F+;rsVMS^knrWR3f^P
z;tS@MvLp)z3rlgldR!6|28qYJR0)=aG8QyKi7Dqig)pfeh$WC=+!sRufFgm$Uidjc
zf8A=7sz_baLXKh2BU!Wyx%`1ie4yR49_5faQFen$%~rur4k5ZIe$qM1`=JP|q-0E6
z#aXN)TwkefND)avx?;5iaWO3l3udok<JN5U8*Yo@(v`W=+?lHvK=S#$*5izNF2arr
zT!G0Nwy{z+Pv<^8&hAdm0}>Nqn&i^~Ph6fOW6x``2|G4k{rQ~T*WSs)3=qUyf#Tvr
z@F6k)ndGRiPd>?S$18-7j$%lo7X3+Eb`*jTl_+9wO&67L%cXQtFh!6y07q*d(TRv0
zk^EFrEKk7AlOa9bbMtlrV}J02mz@R37{p3`(4EMqSQtFo(MK>^L8iiSLxo0d+I~TS
zA2qK{+ny5#)5s7|6+bIS66owMbR?h)LEd=~kWPuu1E&x6pUIh8doVAvhPyUy2Nh32
zHuf_m<%V0US|o;@4yGwsj!(}n&*3{LIVZGp=keb1TPIqGJp+>&#6H0uqC{8_1Viux
zc(_?Y5A+~0v2P0X!SaxcB3Ajia~v`Hs-NnZ6a?ez&tf2HGQeLFAE|Dhog;|73ehLQ
zcPi!^(yz)vao!<EuZF;dPlDbIasx0*$nT`imj{$b1l8D3f5_0$TiI0l9HXu#kz&~s
ztVoiAuiqgNKawR#Lcds<G@=;I#^kz;dG0o>Vf~GQMe`U?NTlMCCdkiXCg<kM2I9g>
z01Jny_L#UWSi0swQaRLu5YZq!2B#?^zITvQ!$9spP?d+RkSdc%=TRhVjP*7GioM@A
zXJ`+eg`jL7wml$IVRf82aQJwUGH5*DVW6m0y)hpFxnpc>$+X;zOJy-&tlJ!U**Eb=
zCJZL-$d_0&>Q0^k2*R(<zx{me%#{6rErdHZqs8)>#$4r5)w0^E#OLkGqsXT-hJYQ2
zln^J;oVS7bF{P*s5Ch6UbhGN0Y&{o07B@;Qs7^4K8c-45${waMS@WEpES8UhDr#Oc
zd>uF7gI$QyXnvGYN&zDrE0^XR&*#!*T3(DsZLyLdh4|>HR@w6460buYORYs^`P{<n
z(m7EXy8ETsbAoi~2oA5GV!jgLRk=Ytkj#XVn>-vA5`INKNa~6%$chE=GZuwObt`N`
zPJIM+85DuD<H)3{(|yNPmNB3-#Fe(8OOsPGZh0+{hympRh#+l5iCX3mFJIXs#(+Rs
zq+FRx=;-cbN!V-3;$Sr598Ux!FR~{aEF)aGqbMo@lFA{{!Lkbiw{jsi{j+vtR!^<q
zlNRE(#b#Hv_pSQSYUaLnyIiY?jfvBZfJJB>XVh9`jYWRB9c`3bc0y~~n+7H*4%ls1
zA*vIH0=%<UT#m4Esy5VHQVYUmzEEwDPe%9;z5DE{gpPJpn?|che?5FxDX)SI36uxq
zfKsFpBNT)iO*QD3$c7@?Ylr+u2bS0eO4FXGW3x0w<ecoVGiFNakg*nU46Oq8PTuOB
zM;j(0o-)Nn89rjI5C&LnRuG#aCliSkWIS+MKpYLsqr8Z2=p<bFs%h|mF%{J~6;D_!
zwWxJPCQ2aZsVm?g&(2jBFJD~=-oUf$sDecsd6><eijLQ!=L9}PesQ#@pJlY_ox&hS
z0}T-Vrjtc79kN?2!(fwVyE}pVc)i7st_AK%mO<%IK?Y`zdA?mmPP^!YML<%Sb1%{U
zQ<GJQC?U)1^b#H5@?Zz@NBKp4anq|p!{OVI(2m|e0Zd*ev!w}sayFRL%fL&1!l?n^
zW*hQO&w_K2m<!9d$lDx)>N}jrPL9o(8lDz#&oH6Met~IQ^`QqM9B~{Lj!t>ag!xqZ
z62PRo^dfYv#H3qORal1Pob9Y^P<r@lqycn<a3PWWhb7UTYq5j?craB>=ob~m(c0s3
z<;@Nhc3s&P%gNgtnF-l&z&7AP5&Mt4d*T-#l_@-E(4u@u;N<kNI4$O6gs`A`#U*C9
zp6kJ_bi%`3B1P>RIu_N^WGj}px57b3Q6PYYZ}qn*LYhg-)xS$(3$Y8G<l-VC>2yh}
zydXz>=}GYh(I8S!SDHv@7j9ikd_3aRrAA`Ap@a52SH84V97pP4&WE?0Nw^Fyhz3G5
z9ZWl%bO{Iw>7?&g;ADSCEy*yi8kyxkjJ(WrST198sCNR*bW9G>uFNmaFJBZ&E9oP`
zG8r(9&l7kh5ToE^?_L(&qc-{YE{eir$Yeyt6Ce-ACz-%76je7gT=3;6x;uFb)HXIe
zms!J^F+6)RS0BvPYRAGWt}fNM+<a&qHLH_gnac<)hKmd_@c94B+?#f{ab4-c`YBkx
zt9|Lj?j}G|L+5sSffz_w009BuAb-JPWZKq>EV)H0QEm^v{e7Ni?|p`<g6t%|?@CrI
zqRu{5b?OXz9vD(b_FxNr2;YvvdkLTAC|_nPFQV#0%anE$_EuwoJG<zE`7Lm?gV!oE
z6d+&*?(6GIma_|cd&;>vU0%&5uq%hcLWHziUy*kRF$LTXDz(th?hM@|^FYquuSqw5
z@$6$>%IFD}zH4fP!s!HqANdeul^lS@fFF&pG><{}e>K5+lABbZq>>x1?F#BY^G8Bd
z#qs#tBz4|fkQ+~U0U<AzF!P5tylvlvKn}z$(BPga*zUL@bm9gC5>4bWnx+6A2vfod
zQQ=dytHuZdQ8V$DoZv|xSR8oW8?9fi<mqPDrce%tD)+5OmpTba=qbwimR5-_xITn3
z9S<+^nnUZyVM^Ct_#jqlkOCiax0sh=)x!qs-T=M_B&Rwf22T8IV=)f~oDifVLiD4D
z*CWko9K7w#Ar4%7H5zbzgf^+!2i*_XFEls1@b=VRF$!FKN2zczV3i};Rjva|m`wg6
z;V&>;ULDnCU}iMKSZq_aDM%Ca2<J00ewdrU9tVTeDU!t%P6YuwzlPpJLvv@Z$Gz%G
zQ-NI{^+GK^xh6<0ux3|8RiWXLZNI*&4Y%9o!{<_)!2Mphn<^Ci-YN5fZ4-AFiuC{K
zQiCP0Mh8fI2Hhb_#byJf_eq(7ojgWrEi_nc5jUN(^CQm&vh(AD5FR;xYm}lxOsVfw
zF#}<!r$6QCB^>u>7YC<Iob|))eH8IUgMC7r@}$w=`SHDOsqV4kQCl|Pj6jGz92%gD
z;q$%8bUnX~y68KxX~YMjB+~)@lQT*|Hq`XFS$*&uV$kL}3N`?vQ{!=oLJUY%T^4ol
z8~!IAsyoCN*bO|QvhyYbLveU&fGPMX@FIhDgj{e+<AXicX+f9Ryc9%EIEDSEzHnTg
zxTCVSgW1^At_@@CZf!#8(7)FmG^ZBk37O3ZX7EzQhnjTNfX6yB=x9A1xr&uo%`p<y
z*P;5x*2IMds;N%N58UGJ*$)OL0N7Pw`fn<2>oeGd>Z{URG1nT?gm5o$07iU+{C0QK
z6P$r@o4fdC1$W0ooDtaDO%G8l0@N1EHT;s#)=O06I?jG;M;=jNnj4=iztCir==Ruf
znxos}hQa6@x{D)zTj{Ty%teH1JV>n!hhnNxAqh;@c__!0R1wy$WY5q~7ZiA~wXPlp
z>yoKBRhPK24`A)WMxZEIVXV#$8cvmeLfCEwWTecOhljA{A{6cB21t;Ry0Fe~!Mnn9
z=<r6`H;NF%k(&+JJv<JQ2S!QUwj!%#Zh-vM{FM=bmW&oaR^a-#H)Myp7Ph;i#y&(8
z#m<9QeJ^;Ez#V!B(LieHyOb0OsD;;Dn^WRZQ--Kv_A)a}BVKIfe(Sys+%9bZb=BQg
z7r;&2exdjJZZ_Ty{1KA}CgZUfK5ta-I6aY=3Vw;R@jT(Fx><K*1{O#q#f}HgDY$eK
zS37FDK5O{!*b_+r5%E78t=`|=zq)->W#ObT6%dGebW&PtBg+$bzS)|~XS&iLwTv(L
z6D+OSAiYU5$TJNxqNB}Z0(2tKg?kYQ!(}(y!^-T?0_u@5ktB*t{j^z*$5Y5{049IZ
zq8MbvnwGU7^UQ)lFon8LD`yq!DjO1Y0EMf*D+PE5r}a^|{7}R~T%>dsPn#->5l-1|
z_x+pKe|Yur<L>tU{_g$5!K-&~k(tmn_W?uW{lneIpWau!e%Jf&-k*O^iq7wD-`w9-
zm}StJ^4_oxV45vxD;5moUcWfMefurf+Sssk4GKC@{Fz)A5J_=1+b{wV%RfIwaMp&=
zj-+bv>Fvk~0W}|&(#K`T!`_X>phAVa4R}Vje7M>j_o9Kud^TWyHk%<LaB@{CEW&^G
z!k-+)Y$uy9L1I~S3XbGfT<UjhKnl}?&+hMUANr4b|8)3e@1OekZ}1tCH-7eS?>}Ru
z4cy9Hj-SnN#d=jJ#PFFx_%u|P;&adm^X#AC+RIKvl3<!z5ghZpGjiizcsL9Aruk@G
znmO^BaB^-yoCh#Tq_8P&7R-5t)QiXqG3RO|rQkk@skNvUTHi2Lh%I%#Hmnj{EAlU`
zCnNYEqISXM*%=DG9w2^=>}!#Q6l=ai7~W6s?_S+LpolSaC!c+|zw7<)&wA+G`|N*X
znXqkdzy0hB9Erw(b@K`(dotpRVZ%RtBY1~_E-H{_wyZ=B&6atm9)A4J|A%zP!p!FP
zK5$R;xYAb&Zp#&UGU7^bSFyu}GzGI*T?tOD{T#(l;2`IJh+aq%vl+{jvu@JjqJ!)6
zWHBo^(1U$ZP)85Vy36v&lpuSW+LcI-=MA?7iZ8UkaE;@6sXGLhA?Jrqe^=Ln$&h3F
z+Y}h%c{bV_(&mI^n6CnNtTNp+E62!aR8^Dlf=4vxaHb?W>40!gj51d-_>frkAbH!H
zDU<hgJNkl-63KfXjZ155oZrB+-o=%zog_9e9AjiROvS|0wfZC?LWf0I6B8Yl2O}EP
zE1y{f5r0aD1RW3gqMBfMf+OARN+f$EJQRhPi5X+L9YY8N!(WCt_qv5(U?oFrzrvX(
z8Z_979f7<>O_THRHT!K0i}%osMkZrmnc3-X^L%n`clv!DVBMx&-EGiSt97Ci$@B~X
zJwP{A0xu3YL)1A>c+joAf|il78f<zEE5iuFRDZp8V}kkX7~ETyYxSd7VCy|S!WX&7
zVWr>_V*nE?tlb|BvoTZSIW&Z1x^3@n^R<@Irr`2|{0eYyu2A{yyZ<CbOATNBe*W&&
zA3+dxO4WZd1|4&Dfx<DRZb=v@7Y<Bjf#s@gyt={;r|eNe^i4T#OP`W2H9F$)6b_1%
zwv?hgU2y}X3FcAVe0{w;t}_p_nZC~enGR%o0|m-dJd_(^k){F25X>m~s)RCBtPC{_
zJQX}u2EqoGYO*pp#tAPAiCRPf7#Sw{HN3aKTl#=$RH*ATIAx%2i036d()qRo)jc9V
zn2+NKAMuSFf_Dq9yLfySqh&-AZDv|8wDfb6yF{o+5Ol;V6MGLs?nRQpb0nTZ1t9_T
zSSD#HD;R?0BblsI-jtqj1{M(>@=|(IuJmi)!QAzh@ua0iZGzI$hK>tz5gxtB2-y`|
z-tKPzbGZBN_8yF1l_r2s*S@xW{}dav(X>X}ql{+2j6P{<b1KQIE6WjYYDrdIPb$zz
z7ufc$ORlaZka<!IzJmS<`QxpS0mA{XYr{#RtAkdLGAznFk{80ys^nwYrdf1#+Hs*x
z%M%09wXB?kIr&vQjrdqh-S2u2KZ2+H9@uL=0kK8p^(1z2#%uSabknCijk4L`I?M)2
z;sOGj^1DXTK=1-g;s(wVT$>Px*&!l{Zd?hDx9^ri>~Z*AT!JC0sY(;7RnQ|{Nez_*
z+F*C4y@#lJx<CS7V9__Xf4bXk?*8M$-P?!Pw{PH<_v-F7no#qwt6KqoB$s>~TKvTU
zvk{S2=k%dCk90D$S2Nf~#8yQ=Jm;VWB_mX&SW0y;0|yzJ?CztF^+maX(DtWyufP4`
z#`zVZg`C2GyVv8;44oC=JZC09b~>5_D0eod&lU0%G6s(|@vq;Yu*mxE`_~Xm-bV_<
zB(8f@?g6zClaCM6*LQEe{c?7{K^fe;+dsUy!|&1Us~_UGRTUt>6zJt`P?w`{vHTW>
z+EU6b#1h6;8)gzQo>Zn6uW8(?On23tatccKr6D!$lP#{gPmF!KFAu+Q<EhjG<xo$#
zk08X+(mkpx$rO8m8uth!cb!W=DY7jJbl`qcaivpKai>6rM=fQUH>$TCAoJyjDsg_5
z;pUj_hCIIzGzyoL!LE9u`wDf^@dUF??d3<#N1GKQrOq!;!Fqe<jUb;v>KlD@zo?Fd
zp=_QS4T>upBBKA+XDB-{N4AqxFAj1q=JrXq{jmuG6+;jgk{%$USDp$M$<=>Sk`=3C
z<$flK;oe+t7+;^IGE?y&W*<!15E^1%aOeNAG8v@L(`qIrw^9rPj@OxSn0Sm`85d%l
z0BP%<gaN>3=*J9WOc!9?p`r#s+aQu-1_{Fc3TumnGt|`8LxZ$U<RY-tVNg+0B_)8h
zH@%T7P=1Qn>FboS6D)Uk)ITWmY+J~kt<hr}f*~+eD6FSjV@R<4R8#C7xw<2+w4IC}
zKuE}u;zDNMl#btAzVP1eyW0%WW!MC!>!LA5AERnDYTto4BbpEXFR|GtE6VCeoPXyc
zYlw!c-Jjj<5W&-EDOoUZtjx<eokhML?ijMM-m1Bhb1Vqw#J)aX>hncUO&az@;+wb<
z+-87E%~Ahi<@7i<LU^HdE<*<D!=|Ya<LMN+d~M<Ulr&+wAr6Yn0TAi4jR2>oY}7cl
z^2t!_x{Z9TK1qz7EZoXvGVQTx-<C}IfNZkc!nfI6WHO&G3wfyDnm`RZ)|5>7WH>s9
zQ4l)h3oQO583z5cKiO3e(^q*a1$Rn`EBopks0dVwMFK`Uy@cXZ3kB4q2UyfD`2CK<
zl3+ggAW+Ej+{9&>dI_i-_Hfg{78#AXiOK^`FroobnYE^flmCKt`ct+nP*-jUFy8P+
zN>bVc8lbCzA>#q+Bvx8RSEup38s7w5D76m_HRUmEL-lQNz?a!>k1o0mwAUcn%+cOl
zQwH(J2aZ3dI$y^aN(w1HS@~K*!|U&)Mox{M`;>Pe!)fn7d;FFp0*svd2R%R!bf697
z4z`cpC!TZqa)mS&Kl3bf!oz;y%l@-xdBQ$5u21%`xBYh*aHJ9a*tUaulV($15;y@~
z`58zyAt|@&bZ&o7zdVrfz@2-Fa`*0gRJQ2cH6&xBtBpqR@HlUeMpGC`Ag5VrlpRwf
zLV?w6do%?T^++F7TLisH->AdvU(<D#1EkJWf=YU$7t+8Gw{irIPgmhHWPU<YezaPJ
zI-p!ash|1j^2QLKC0d|37Pza_5#7*zGX|EO`}TL$Ks9Z3gfiS9OZ8ZHkLJxp-N-jQ
z8Lx4>yNkCTduSNZGtGm4z*F3zkmyA^)fKd@0pKnomxL2##%)KT9tc%|G$5^!IkPui
z%PWvNGyjcQKfx#WT(`pMLR^E0mFrX~*qVMJ<`NysynMNzeV-{t;v=|R#Otde-9vUT
z`U0sWCs<UI4Wz#sO(1O**BhW+L-B<VyHICv@-1kd1y}DOkzNPg$w1wp@zG}iI70<G
z^7vvn14SP0;HKMjckiFo-tPTzjJi&*)=n+MiZW1kPZmX~VQ@T9W^@{C`);t6zSdIO
zoYZ>33ZgGF;zIw=(@StIVKPIgTxt=XsJ2q+S6Tt`>{`Bs%3f^eB)Ayxvz04+6RJnK
z>Iak;8+<ceUynA`(d&ZiMx7SA0m^*`44tRJubT8>v1MVzz!rorM2gw*;PH+QdW8n;
zq8}<{mzPh>UOT44KkWhddqy|JFrVqDc^ZgHd};AZpuukIai*-u{opK>x}=ZZY(|u)
zfFp)oDWrfznmu%Dd?d3l!c`0>8g@CRmh)PjRkP-e-{6}5Uh!Kn81TmkmE4o=y8#kP
zU>b`t3Zm3|g3k?zhN<;N3zl(xcG(KAYJqi=&9+B$I?_>%4MPs$448^CId>>+i3-6X
zn;I0?Ha1^|7Eo`p2)8N7d@ujhjL>b66Sf%~;6Evx^cM`1x9|Gf7oISz2^s8#9PNd`
zF0<!pCwn1}_d=fRg**ks<!+a#aOT^qIL$!KR8~iG%^FUX<iD#93`uGCfg5YH7Z`$H
z)DKY?t$vwlfX@*_Lt^vWrIrz*KAih-A|u%3pHJ3b9pWD|c7ds3<UG~yM}yP9Jlw&t
z04}%sAHu;EE;+J9xTE2UE(ktT-I;K`PiqsGsbJQSsc>`{G2p*6P~tz}K4Tc>^9_J_
z4AeK~a38Ea6a@qDddRB_jvdZ2lP%{SH=E!?F}CuPGQpO20Yr`B%MD&3W`JS^nF8j!
zk+0#gGG2vGib`q2@(ElBUZVe~Lzn_(I}#D?atusBeV)cYSqxWXBSnD+GOLfyA6tH-
zHGxftb1<A6;HOrUF+V+hySa#IE|B`kqQ-br!#WgugypR1%^>Hu!;ceu``pDkTK^i>
z{b<m)2tB#j>>*BZmEq1iyD3SGa>8DPDXH7nx#*z1qzS+`NlT&G<GS)?h4O7rCp{p&
zTIIO0YmVdQ%CJd0SMH%Zjml%kF2{)Hs;>00(pkvi&Sw%;v8PXl*tRj9@GEQPB+<E2
ze-^YEGz;3GdOVi{CKTx6VK;Zq6m%}U=j8woR9r*B$_42FEjtY%B?LE9Ggcf<bf?=6
zWVU)j8^An~;I$x&U9u<=8bN*h4a&ZU1e9Zuh;*fSihURK8q^w5WS8T0;UDibJA<k_
z&k%1*N<SQLm#Dy*uwA2F_lVi|pppXln1TuaB97^d>8E<u0y)>NAEjYl!Q%~5z)pYD
zR%;7k<3>l#l9l3^2Ff-Ca+%|Z`=|*{$<xNusWQ}%qs4E1kg4NQSQQZsZO0ID`xOj`
zgYwAk&7B*j&FDto7n8<HagYb67StkQ&2gS<n#9OAR80dUH>p)k*m;)QMBRlRNpF{n
zm5E@A%;zNnxabPf>jI^9AjgD+kf2^Ld9F|;2PFaF^X_7S(sG;_gB^LGYmhHTkPpr~
zbVGkz{GD!g-zmNYo2-#&U+Ha|pp;*qQ1?wE$JOAj%|zAj<V6z9&S3aTu<{d?b;qNV
z@#D#psk;P1S+%W%4tI`1tM1p~aPOlNa~F*(J3L@;z`!s<<Z?B23pNediHAI$ezFj8
z2J3xVk;vPggx5wUP)MVTm8eBh5L^$hkeagGsV=%1z?YV*f{X;U_f^4Xb;8sBG9e07
zo?l)NlfVNRuGeuUSs@ykT!z<8=Dz{d4SYM8XfWfa46v_X(g5lPmk73Js2Ym}u)pSr
zv>4T`ju>KZ<4&@jdzd5F@fXZdX#MRzV~>#Z8!^Rj!&S_S!ldga;gKpM-4nT#VeGvF
z`ansSaEi(R?u$+Uw8+NyIzCCsl7J$P8wll7*^<~j5Q=Iw5jBhsUVYJf)%#!nt2dwH
zHP~#h^><>)CMZIoOjuuRC(TWuwHS^HcwQoA>QEtUJH~RU5WzI(05>l9g;q*vRsw#j
zKw<^bJM<_sGZ(2(Fac)$Tq<U^+Oah(J!FF2I!9ilG8B;yk9Kv;Qi*Z=dHOPU4L+sz
zDYb?j?@$l|;z(iKL)tkIO)qQ)T_@thk>Al76SIt0zHvTh<X4Ih6^bgf#7%2w8?Nur
z=xLB!UV*w6$!wNa@KBl9=1sQZ=^Vuu^6ph$C!XPJIL|Zd4jyT0?>s%?Js%eYB%6}4
zh8C*9Cl;B*z_zNzQ#kN9=wW^&kwBTet@*?lZby!B-Rck2JcfPFRWvj(o7!3>##m~!
zuVkw8S#HqY)ZLJH#Wr^OBxImwT59y!2&wguGsn=HYoBU}Z!f0&Mjq6ilECkJAKu=-
z{+`uzz@xZ6G?W_P&5xj*qD|M`A`|bfG?aqtsTZhJxp}yK_;6207}V#HuTtGQzWa_$
zG(}BDEkrS<gZM!KD*vW#V~x_XqL*~0XQr<5;8Xzrv_QXQjtXs%w2*(bw;Gl_JD%AE
zt>#qBSplH^K5M_=)=zn^X&*!y8xL$umkEni_`iS59cYIoHe5tbB3k+Eywr_zH*P+H
zuB}iAl&1jZ@>XfbUOpUM;NtA~aoj`lTwp9nUL`_4c8vgQyE9aLeWQ#Pu6H2L($0gh
zBRv6Jl<gyxMTpoIAEQvBA>@d-rdk5mL0X1`CXJwf09^QFH!bW5X_HI*JfD4Y+>y9F
ziKl{V|CPL4JdWa+lP)k--1ii<cGoagU~s4*cU6Q|f|*W!77V`{J$nWc%Yw_%45Lm3
z!2CC<M6qH`5I8MbLqLVLH&OY+E;8bYyb$pL7=N_|kd}Ojd{+DPJ(NF4LAfoZA;28d
zrweG-upi$SK9&WK*8plh4H14aZ+imj2C}3Lr=VU(n?Ba|Q&z8Z7|jcy9#7sm1uKak
zOILcN%@f>grLI)$?1T}w8bj60)?!*oJCX$I5@lC1cAr|uLb|J=QA%f;Sqv&}Jr294
zH*hAvD|sH<X;Pkzl$Z=!Oo@ZeCx=xK5l~848Q{EBMzSi$R&ITa35!0QZNxdJE1R;=
z@Nrk?$TO(;cqcP2Y><j=vt3;z!;0(B+i(qp&Px$}jlUk$tQc!&?BqPamlwOQ0_i!C
zDBS7@rK{mh@2g&@b`l3wKTO*;!SeLP$*PLpl_=;?Zu5bVB%GOT6Jk0t<PV>ZCtFAa
zZV&1oo@V{9JL-iy*I>072@RGFzDF6KiU>)VXAuj2v%9>QO=l1?SnrF76NG$5SCTb!
z1SPp`!t`ApkjJuUh{x+<C_;8iQMs^Zc@iX9Q7Rp<MXy6gM4Si>uw)f(b5j!-5ijst
z6Xfhm_`4}fcF(YR)#fw7LO-wH{&4sH^#kgj?-XhK{==)N_jA(k&t)Ii(M9Hcppwx5
z7qNMufXc3htxlRCkp#tmy0?Y>)&PRfqrNXm;$f(RR1j7V7sMsGzre~M=Qg*l*9$0`
z^+sX<&r31|o^A4vEwFCVLyDAlzM&gxfk=p_TU=R3m3%5$fiGdn3b-oif9|2>JPQJa
zOO6JD2i{^jQrB2_`V=IX-l`{T`fE55Kn0H`IM9Paso670l_t^HebiMlfyH7m!_Kdd
zYj+>L%?X*y3^)PU5#+Dx2kh&W2kc4s`?brmsh6B4E7c}WZOv&Iy-qMaF~(~#Pos0U
z43p6iy=S6Lidg)s2_hsVs4s|jagaPceF0QR0?)kS5k~Lce)szO&0pTW`r-Y%x3B;2
z?ZfMLZ|S%}hP%5LppO*MkBXtIySLxsgw<t4b7N8fQ6Eh^$Ye!rZ#~QL*>xYyh#vuH
ztzJN_Qw3JlAobRA)g)9-LQwvb)3?l3w#b;avx`eGp~Efn?_D8_5YZ%e8`6<s7g7o^
z&b+wRzIL8(wb;^i@p?L4uhyb}PzzO!>aCzfWpYG0=g|~iNs;}Ai&x=DXlh|615Ow^
z_P-RVG_nd&zcFo@028JO(0bA5^@!>0Dmqw!)EO9l^8yG8qUElK1pfN21+`&oPzrQ`
zRWJ^qZ}UMD=je21pq^Xs%1zu?fz+8u3j;vhZm0ahcwS^0KoXvu2<*rNNAeC88I#ng
zRy|omb2rhZMzDt2s9hTimGODX8(lCY)YKX*KfP}}YPUOg2I>ax&BE|{;n7_Y-qix@
zrl!Zx;N)@bGIaQ)Svr#b9WTuc0X}iQL22ffE^EoRwPVLY9<Xq2m=ARV<ZI2`f^Jr<
z5>qKQoBv>hmPv~zk=tfGnGauzc}`b40;J{8%ThOMwl8ZiZLL}!ZD0R*w|)Qm`|t1G
z-+jAy_wAkGeRH(;L@a)xM`pQ&I)?(em5MY;DV07)Vhiptsl^X6Mm|Li`ue!kFfE3B
zz05|q02p#AvbjuXXQ`MqX-qTA^yb~$@1=jqLpB$XF6Eyk-L52QAuiq_eHOP#!%s&T
zuF<AB66S$A19r{X7PPIXaUCt{r$foSNvMWWCQ*8<(9hsm3-exzF=m=dM6#fMDw|S(
zacai7Me?paYT^b&hZ;+<S_ThEAI1=lO*CdzG!{*BM9m5~(xgRl*|^ka6=%G%#Wv4W
z|8cW45YAL0N%Ug4_-4LYo`c8GjweoZLPJgMZhb+&^?LWT;o3p)5<xTp<e@S1h!P`D
zU@1g>g8J?PU>nb!tx(IJUT7MH3Mj+tntmG8yye|g+CRI%kC+`~v_xdSC6OhaR}$F@
zmwS3K6>HQ6aVu}6HB6V9YaQqu{qdxdPg_8JlpioD{nyiJ3bL%Lv1PDs(h!YpM3_@O
zYc<T?!P@F#%bPZLeUd}eH5S~{&`nm5czRup`rZnOnrH*9`dD}X;k=J#IIp|srr!2Z
zW|MXa%wH8A-2>lc+-5vgJQ64v02U=@MuW=MLqFs&L3My8+44X4m6ZgW3tR`&`h?=O
z(7-Y<@dEqcVl+`YKkPVU#`!NsEH>NWlh)aOw5R=ePy5N9_Q!kLpX_O8J<O!*0_rV(
zYiSJ4a(8Ksp~v2NMRr3~$ig;5>YKH*$n02pB%2`GeGAZ;>J+3CXPv79$1(*?xY07#
zXLU+K38wvE^4E|nzn-R$UMhWY(mmabC5K@?haMWm`dG4=48U+NCf7{wQ8BshN^V{%
zMHazKpP;xf+uq-<S~o)0is=Tz{Obe3?WUhqr&|PfC#M&neA+^AJ?cUt8K@iFref+M
zQFoeHEJKkrMky*&b@loumXpLX5jJ0ti0uOE?lhhS1c~*H2iNBMxItBQlPeEnYwjjs
z3Bc{-fE4!n>i0y<Uy2^<F1dk#GABPozG($7{99>8B)6D=QMBqH5udJShijapqE1dm
zV>R41E{j$xNe#SuwwLRRPR%R*#|@gkA0ifBM3F0D^-#d@H6>X0K;|`n%aC4>t@|(c
z+t;uDxSKB#v;s>7|DZ38;!YW;jOk|8EsqpndN>agbB+$yz5Fvx$<z+ck%#KVRfc<T
zs8$ye6nSS;NS9$;rT(@JwPCobooWdv)@KXVG&brW(J{z4KhL8!3qtOakB5%Nl?}7y
zO-}g~+uV2yq}>$%0xJ&R41@;fM&8)as@C3*c{5MlfxSs{wG0WCz7c4SSt#L)h;Zx4
zW@Gxn!O>HA8p#2PUU1U5n`jYN`V{Jx$-t~eqv4wC-j&Kus|bq`^1%TwHN5}_Pt6Gs
ztj1z=NqUQ4R^coBP0KdDR!1vXpu8mX3*lEB_Aqo)PQu=b(MLuPEqi!Sb#>6JRPt2C
zO4Sf`wpn$~w|mMHP&ZItL{Y|aeYBn2I-tpAZnQdYI&V-bPY*hQ(xO^;MR*xQTMt?$
zg+dC(-ay9!O<%V+WCrSqB+@`qtV_7wy0WFXwoQ#wK(#6bg3w2%OZ5POOX?0FY3>TB
zIKg2J=hw(4*tqsv;0y`hxXSYBoCD8D2NYB{Ox097)wi~#)5yJSNXoyva~Ts%Q$n#9
z8M9ZHTVhS{c;O2YJju^=ND_{8jZ~n1BGYu;NAKV5sA7M6|Lu>jdngV0^zfNy=yUH^
zcg%?^%_e6|PN5WMA%eTc2PJb+a_b4yJdSRUN;NzQj_cwxSVJ(pnSEqy4Aq3%tZ|bV
zwr{$+6huM}GTFAfmJ4mST^H6TEI4@3(Fif}Gt;F#bq1BkVtsw-EUI5=CQ7Ci12aXN
zMU#&=#5QK=A0WrCi;_jsu^}mfq<(HNBM)T%)vm`2J+aAC1yf~z@*!b$yM=f?KPkD-
zM6(`59+b%Wu!)>UG~k4IM7=F{(CIA4Migy&lBU<(v<8*amZ=m=7CEs1mBB;@TgFVc
z2>==3p@Yq7PtQ)5dR<bN!}(b1@_KW$z-f1&h942rVy362D?L=aAF^*ma>_`N6-g@L
z7`KM4$V4-DM%;xrdvZ=p(-u|HS#D%3NycKT8tr;@&^ag@_7FL^<Uxtma=9&#RVUmh
z-dx}+k1?J$R?>ry;dm?Tn6C1Qx{|X>d%+zm%&&|NC8twEH0OK^xM`?dtB$EPEzHzV
z`@offaiyU^44O?}a$*kf-<M*E$<llY>5qTE=$TUnJFo{*!a@R8c(dPwYB$Jz|33%m
zR^&Ei0-tyQgial*!dDJ8+3QW!(Ltj(Oti%Y25&%l^oWd9BxG}zIRSM`rXjky(C(BJ
z1Z-Iug>!z&1`yQ+O7CF64ZREEZ%U(Y8>%<QnT|}IFmbdZK)U<bx5{T4SVOs&>-jOU
zHemjp;A>B68d>bvHc)=AtaFDfI%hC#k0;aNC9={|sVCP3!q5mRsGXs&q?8Pj!hgNy
zb=jhRknG{|byS=mqoc)Ox;p^-!**QeO)G9`K;$M<7;u}2j<%2rtU2PL!Hm;(ASK^b
zAGNx?5iOom0$}Ep01P8~_~FBke;CN1Ws`1+K;CjG;dFHBK9?++qX}w+n^#A%vqQaA
z+yaYoNYhEC0AZN5X3eq?wJU8aUlM+fifHxo7g4;>cQyel^clEJMW->3Pc{aV{AE%a
z<6C#b-u=V3m=k%S7VFz)eE0M)KMnCM2z)I9&=V1#MlNhG2G_~HC75q~GKpg687zXq
zAbbJEL@t*|0L>V~{UCe`?=6BwjwrD}cJZC(f=t;#nnY*;%+UE*>H!=?S1dkGBq^x2
z^1duwA3+yAtAg>g)HD0rxO7w>RxsOER;c2rr!C|c#XfN3nX91sruLu*D^whtEdn&)
z!op0HL0+L&9c%`7A0My?lsf2+3dd6wsW(88mpoF|hp!ur2|>|LfeherTDn>^Kw2a2
zR^&$>NcawKBc_MJ=h9CU2z@p>o>o}30ZPwtrnB#P(p=#n<xrmduFN}lg4JEp*+Ib>
zU^2QH3YD8L23RpJP)HrXBFWX$g#i)`4`4J)c<*!b<a4_?Z;`iIqqvtRKX>1TxY81G
z*?B^NQZzqc1ac{ax>fzh-$7Iuy+Qig&E1>3S9CJysjXi(mg!6TySLZtRl`tPAT)>P
zNw%D@oi^$Ksk1hummpZrk3)T)ixQy8R~gd{&ma^zt!bI9a{}tALFZFW*UDX?1=T%4
zN+T7j7lLlQZC|haF{b%1Qpsz(xZ6zUgd~_A;u5wi2d8%ruYRE46krHDB%RRn9ETah
z?H5{IVk@veDNG9vWBC92Y$-feLKvkLK#zNdhH=w0znXiiLGo8(fzEfsDM~&;SJz@@
zDyVMK3C1^VQLxfY+0>kADVRcI;HlFFwQEiXJUxy!M=BCS|CcT`51J)+YszY&d^R!7
zbQ0N`O|&YGRx)-b)D>pnB<H0EP;vv0C%pW)G=SG=xdIhPf*9K(8TSkViZY3b#UP?d
z=w9CF8UXPQHz>-x8VCF{7MIw}=-**@aU+eJY^3CN5ye#rVe5@c&3jrguvC);6E+<8
zI@;8iTb<4vpnojP6rMYAoz@Yeoa>|$Jr6|$m$?LMci1YIF;|%3F2Y=QkyO6ijAp1;
zxm~X1XbG>4>{3vai)RQfJuilvD^x71F;Yxx-A5zSvUm~offGb|Xv%OQIt$?dWrXMl
z^wb0$*+!9&2oC@TNRD`6r7X?Ed3$qL9oF1@-qubmstuJ1#UaQCwv!H!5t<@Qsl?Yf
z{B;eV7Es?z`b76EbAS;anJ=}*dD!MC0p{AsC5HT0hmzpqAbTZymlWrG?9bS{K5^5h
z>|IWLUH5}of6TMm*bsX<X?DaTY#xyQ_D3t`f+Tii8x$-5TkgFl3XIp>W?{+o1C7?T
zHAlWF7%T_AZIZG#{G*%xU|Q}B)Y#PK)XAOK6$(Pm5V-(H2On9mq_}$2Kbd}bE0*H+
z4I`EA!fj3pW28Vo{<uQ<R%G6|yM5rt_51F`s*_<sxrKj=Mqs)scWm_w?Hkuvpr*af
z2AQvhMIYil8Zn`8ThtsQ&WiKvS0&?Gc5?2O_>`{Wd$UF39yw=Lol>r7K<yM6$KxO1
z7xn=>8k9PqpYfGa3i7}pRR&09X7}Y(ijeT?SKf}%WHz6|8;5pjGR2hoT_D}g7*1|J
z28C0>Kal6a(>)#r&-S$U2S89UNfxlILM0_5(gD_{*6cuFfSP#ID=)MnVM9S^)WzI|
zbHz1ewrp|=D+G$}Y~SC$z5lLp)c1C?cOyOMYP~#zf<ww&PsTt>Q#RYKiO@zfh644I
zVG5E7|Hn1T$B`r`5Lbx61iOk<#4J#pOu0ni`5W1zd1N-U=vc(m_8fLU677TZivmk|
zg^<B^_g()54Ox>l>;uSzZhk7oBf4+G`63;k|I+?P{*ujKbCdd}iBotQcn<u{NFz-W
zXUJ73n6Ey6`hmkdmDFuLKZNeEYymMuldYUNIaKT5B#tR>z!ojnFPXS+J6TAEaz@cz
znUoi&-N_yeI~sZ3D7%y{6FLb8YnaWcCM(Pn)JUdQ_0OtU>S|H(Rl+HhvMlt)%V5yU
zBr(p-l}&bX$~;3Uk-c`Pa+He+RA^x%j|wOVwob_cw-kQe9TElzUCGUKjeu;uGL#Gu
zi9sGpyigI1<Uc6iPV8&20pd_%8m&nm=&OB9k^qH;(hHiw?C?0Ge(8#UTyPt_`5)GI
z|B)=^x#`iC;Zxh;_7r+jnxy3@TxCFZ_RCWWxvC<rG#ZkeuJUBv?b<vjcH?Zcc}x`7
zdZZXNc`CC?LDOr!2^B&sI0TQKHFiOKdaj5@{tK?CS{bFciW3(s^7-ccf~K@R?Royq
zcNqZ)WVy8>$(oZpW%tK5tK_I#ZbK7{LvuF{H59JlD?;T`<yvSF0rp<l41iTwexS39
zX6Ay3aJPH=;msS#6_tjDEVd(-r1`b)*rYeO$*uTC!1QR+fb9)R_FSAYGfdL4iVwI1
zNwf4_x-&?EO+s90s&pVXNYylhS>2WfA1x(1sAJ;69XWCNp+qkshLOTWtEasXSNRPL
z;Z+>F0>!$-`?`ZZQDavsRs}m*RCUVJ2A2*JZk#AZBX8<p<c-zMoQ9g$1{PNum{|i*
z%;^HbCP)wfXOU4{Jt}5=jWnM1rEce!=1>%ujuMCMrq$R<+3SdDu{a5k4>aA9<yx{q
zUx843Pus~Siy7Walf~hjZu+}^qtMfV08|PBcmx|-c|B-cABM<h(tOLL#(Ul23b6EE
z_b{^T$1tAfoZbAeJ>|QyBpTY3LKKZAyV;d1SZecEU{v#AS(z9zxr9aqeDfbUVfgIH
zV<9;$bo9&LA$>08D~1xF2q!1smAd4+#NmVV(x*rPq#M7`hA`@$(>j?aAPp5rk|=ux
zvT=ir$`?$$(2*eOi{8Kcc@vcX7~;W!oWT66N3y17@kVws$LFe3D95E4?XP^x;ZwLU
z8WU2gQBzz}vL{1gfF#i|&y1VOsJmmNqnN*QW(3luKA%)?W65lpH<>f%*sFqQvdw(a
zaK<Tc3=TFJ-pb3zPGlkbQsby&ncHwucZV7(=nRZQv3T^)HuV#|Q??^G8I{)U21p|;
z#@rY6_D>Ume&kT);d<-}@n(=HBIG<9xGfWA8>PO&YZTR%<h}rZh|3iMzOXaY;j7<|
z+=iSJE7u*JD{%KCw*|zNR-%xiTY0r=m_D^eKG@@hV`FxgB*zN-$YcSFxu?~x9p@@|
zn!^a&?+6ymAoX@iWc5I8qtenv@tX%96NM-^Wg3fRrOyjOjTS?ut_Q~kCxv`jgcIjN
zT!By%HXzcsaN?qqh9gvGSiJAL2r1r6%hcxiadO0<5ewJpC{VkF*w7#VL?65ryf@e{
zyup+b!Rnlkwn(P9LqrLZjV1=DYPF@MvQ#mFc)qDh<4SN%qUzX%Pj6{eYeV&^c@Us~
z(DAFjh=wR>Q=2{Vm_4peP6MQ;$y9(i2y-G$IM~Ctku`~VPz|X5Qr4_6CqStT)6h?S
zjO23I_4>Qz2yUV#r|0WDAt_hY8scpzkfG|uk}TMyo^}e|7@Ksy*zSGmN+xjLBSkWJ
zDkt&zzxDp7tDb~zvm(HLGbpDHlAG|ro|$DK=)5X1r-Tp42r$|r@hNASK5If`^ASQ+
z@K4xCv1POi&4U?^OVyP=im!yL0Sne%Jx%xyN!9I%g$c%Sa>-CuP_0Et-z$$n909DP
zsiNJ_wwbX{m?gpVI3>=5ULS+o9m4*!;zO7>)7WNKxvHSLNkLStoUa9OfOe(@*4#^p
z#==UNk!mh9H1q%OKj~FhwlzYDMz=0zf&oeaca5SssJa8O)arDuZ=6aV4d5YZ-Uf0a
zba#Vnfk+0vZUcqTiLb3knz&+BSwXZ2;VSEVrIK{D&M6X%6u80<FSCwtt)e&8hcx0Z
zw-)QoEqB0TCU(5U862Y|kDpXuoCZ)UqfMHs+xU?ABop4B?lF6D1}m5lAwuVru+d-Z
zVP=xc9in$?vD{Vyy>>mw2GF+;kP<{gD6}ZPIK3@nf;!<fgVS_IB>_t8j+VquJ9aN}
zoTM^DsA+0jo5wQ4G%lh_?iRY1z@enlMl@l%!M4F67#3PL8(-c4>IP#lKz3GV7*mzw
zmDk!7{18?1V8RMF!BR`Y<%R-<#`Pm`zx6aXfO=W%t~2OJaPD^JryFKVamLSPVP79T
zK*xN)s~HY?1Ng~I)S0mb^A14>{2wM6%JOinQ8QlLavOAfP&g7gsxz}Br*jcOp2_TH
z{vvRd#S<a#P<+RJV|Wm2Prz=qUB5igzvB4)7ufyiq88*Tn7P(-e~(FsWL}G-(`1ui
znp&OHtm-(a_F4<5TZ{z`7S1y4cLYb&9du_bvIlC8&auH8`=_&uZsx{kEn`b}QYSra
z!qN@0YM^eyh6z!yJa)`czDdVOj*cX+836pWTp=27x17RPVGG2L-Hso<&eoFV4w^ot
zI(HsX<N|P^jNc4rUdJuz0nGUzyc6O|XHn1co#Yz{`$+3kh%^ZmIfiV*H8Dbk!1Ewo
zo9Bu6^`{?*oXt|_IfL$hc=!IHPDL1ui#!a-ZSU1SB)L3w(%VHXC<}wzYAk*QvZ3N+
z;dWx1?dc`bRdNQ)2F;Gflw2HeZhqFJ8h!K<WkdxT=u}~0qg0@*JtG6460;W7-i%Fu
z+6+y9Y-F6ZFW_zI@-^*pWPLU&`~i*Tcyq;K1Q?i@y-Htb$@q~;$72H!V!(|tVT>PA
zU~%ohZ;T*Lv-ZF=TfC_6CS3;tcI;lLisHyMI%#TX-7?{%u~Y@XIx<Bd_Y-0vsZ>Go
zD#x=#c%{9H4uWLq_nES|X@_RbX6E-+%olYmO#IG;iEc3Aw?f0bo5?YV--C`F(KeBH
zB=ik!ux|;<lElEwjGzM((ztuM><Qr{`_Uc3$#`~tTUIq39)B<d;wX90m}4FK1k<=Q
z62*n~pY;xOWmVjuoC8O3^uhKRYq&s%Cn3Op>!A3mt#1&rQ2Z85Z!-reR}}b#pn6q7
z_$oP9da|*6xN$Z?Q)`}}1=gnsIhisYr`xsagHY7eT6Q!8Hvv81C>9ArdM2mw__tu0
zr-fCKjyF&T%r;A!7+sr6US^In3_JIFdzlK9^;lW}bv+`X-fFY~JpjLA)>D|KN^c2M
z1!K19If2hEDFOzIFNF-lLmv7-#JuF6x<h;{q)Loqu_9Vt4G*O%z&90*%MGj$_)^9}
zLJNmiqON%|3n&+-v_>LzNJlorkVY>tU(EgWn5PE+Lsla0!(fs<`&qioU*Ox$RT5e8
zoRGQ+twglFnj~a^p2oa(P1M+LqDC@HNW+PlU?eC$V@s|q@#A|z`Wi@D`l!OESl4uj
z3CYPrS6vQ~Pl~a?rYa&%l3zx%5xcHV*Nl>BIw&q@^AihHT7k67u}I*P>2JIo9WN?{
zNCTwq##>q8Gi5OCNb_4jbr1IsXv*~^{5N2oXqqkykh*J(ZgB1t6%wrMPRU~6S_QM%
z4Q#)IH{ULf2Giq@ALYg@85pxf{K;3@1g~#!Zm&$!%YBHjLo9jXB=IP?{>{E|@36Yi
z8$cPZF$r}*BLQzZ{BsDUYS|*gdITA46=Yx`>n%MlP$NSSihy<-QJAV}dpX{dX<12V
zt%Js-JzgYr_l-fbU#7!edm2^AXcn;D5Sq~-!;L<+2#u(3Xr7pTJKm90l+8k7-Y+j?
zRRRy5AY27)2#d+;6c_@erx?bq2%{MqCTEZZJwHeG!uw@Z^miRk4RTw0lOCwJ=%0Uh
z{pRlA5CaF<7;mmA!y&U))`15ra2h^w2OKYZ8&8kkzd_Qp%P)Gr?H$AuvK06m*hnEr
z#d=gORomshJcX@pnl7GkmFYfx9{doA0Wl^NPau>)_wbvzoPg>u8nsC3X1P|^*=*~=
z1HJ>yQ+Z){wi1sVZ|8IrI+ih~GAO`&iI|ez?#tR_K&w;J-0=I~_o$NWK`7O8Op|p6
zAF=V|=8J#FEnGl*+!tT{e)jhM;r8vTJK87uW~ggE@pF3+CS5UpU;Hay+ZagutpkP$
z{*t#2e)(JXj{Hc^(6@ng1{!nQOLORcfK2_Lw0W-F(b)=+c0_C|%M*!&&(OYfv}sMb
zO@Q4Ymo%ymKa<qfA6xlhzQnSS1V$*{?f|`;r*ZQ3_789FfEYFp?|x#oHqkv(Ww(LY
zlDx^mNfXW>@V`O>uB2(ycHme+*aAl|oeYs<1PW9jjnNXWY@<R7+FU_eCucE6lpqG)
zgGSS^RCu^~W{h;H+2UCP`zZ_ma(yHd0I!*E9M_L{WN-~}W_=x68Xgc%AB^(@=$;`U
zBpJHY$ChBtq}J8TVftB<`3vj<g8M6DWY4CMYuSR?SK0n>pB=x@7ePDXm;%vLjwtA6
zb&1SR2M53yz5io=S7<;GETUioiuPk-IEhJerv7>Y!-(;t#6S#KUtCSshz>_JSR|Tz
zfA{_C`-i*t_pyhJa`|$tV4obW&o(w-ry@w>#nm||G||#PdU_R)5!09W1|sf4tv#5`
z;azPvlX0ao=IiAY#2Eil?E>SW@l}bkb#&1}h<V<CmX6y&VOwukN2oSD?~K*?JN#!z
zk!x3MlRtwtGby87f08*g0reac7>NN#3SL}a$5{Q)b#%~;O$n+~L0w2#nq23Rz^J4k
z<1Qmz0_sg-h6=S%gt1pmS{7|%XZ2m^iz~sMwVW<2h#bp@pMprHD@y|OS}p3gL$>fW
zBD|-&>)99wP}xfLTHEN5kvdrD1k?AZyD7IL2rsVm4jgK$m@tBZJu(oceKm#?&DT8H
z()oRzE_Ex97X>Q1I)X_EVWw<RKdNXD%ZhDwy~Pf08>cFuM%^Vq)}PwdL$}sAa*otG
zH?lc+O%hhuZgTFNg9@w%>GP7v#(go`ryA?%rAI_=CQ0|166s5P$M5N4vp`RJg(h?=
za~`vxB$PS6BPeC0vtJOgspUWtruEK-d@D7ChjZ_@=E#ey0d5&TJ5=C>@zV`D951{f
z`$jWD&ZjRE7XnfwtQ=US((%aBjfk3}i?d=S<0MvN4;v+3B<*uVrhtwrwz@Q26_ln0
zGt~hWS*io>g!803poT73kTd+Cjb?TJat_Uh;b>VDoqVzu>UJ{?MXX=iIiyz{p@{Lb
z8!6XkB)S|OxwCDU6mg&~XH!vX`>E$-f{A-gEo+f(DaOYGVngMd^Tb9Al_OG2g92J^
z7Fv(zo0ST^hGE$l@lzys29utqL#cKPNoqok?E(d<La`MaGYe&97j1j(XWODF0xfRC
z)|mz<cQy?L3YVkF1+!9bcB=4<**B9)h0xtY4;8sFO`$6ax#&_89`--jmyb`A*2|?3
zD7V00t7-u9GmPfLHS(Q`bApEgrU3<ReNS-H=qtne>?2p~gD6m~!b^NrX`5(v(a3dk
zapX!aL$H*d#U1Lyq4y{hbEn`U3de}p+v63=Zk89?ZT1o7DveZ9^=0m1%24=7X?^-M
z+9*9c4j=<(q$0$oo9v!~K3t%}*LJqN*z`WxM_mj7WfL68l{>5DHZ++be8^Bo>Io5Q
zKw4K56fr~1E}GM%*P!<}@*mH~opG~(6&-YEhXDd{f|f586$L1?0xvbA)=N~>hT<OS
zKaSpiyBocP{s5#IEZh-vf4X!7y9#hIi#W<9Xx7DOmRrDs+Dwlj4jX91!UmgDL-soZ
z^=Xo!S$G^MZ9N?#|3#}MuRr=sXBQAyHIk$^v4ec%0!duu+uS*}^a=w3k`zsL?12Bs
z?(4rkcY7QdUm#CP-1K0>FLC$Q8<GCj2&E~_F3b}RUGHK{$Ij-S=<1=bkAtwiIYa?V
z-$;0^JF3@U-Jzpll-MaAC5aNhA9tJdLjMV<9%Ncp?BrE5eR2u0uFA0^^9}Y0EwXJb
zUJ2DrF(f*J4G<>WxYp{#_l-sErn4(&9OcFaw_Coq+tknm>10A;ox!bdJlaTgpD*<?
z<f2+*(_fBLCVb@Vw=>z)ZdT%yv$^hGg?M!`NbX;iKEQ2zbxGhtDgB9#nk^cFAYa0l
z4*$~q3a#dGh!Jm)n2Ot;dtXUuv<Xc64PsT}pBkoz*BmI$7wE|PMog$)BY%igkmCL8
zcc}XEm$UcpKKz6n2EZcwKtYorSb{ijr<ivg-f-_@i>98TGc-s7Lv0s{YmQysfNIDI
zS1JerTInMs?SV}d8TRFi)&bXj{CX_(ArLg_fId&W1ZCIc;#tpF1=3TD`C<D4$&p}v
zoukC7M3>?^v1?(oJ-rxa%H|saZS9>7b<+^T%bmIXz0rDu{Ckev9=KE5lvB!F3yK4}
z2O`}f5iQbx+%wgLf0Ngx;X1VY=;I2@m!^kk6iQDE1nV@vw_wI}kinj;uDC2TCqNID
zlS7z&#8mSgekmnbgR0LV@1qs6@Ja9LpgXzZpa?W>Fs%!Gc&R2tInS(&Ru|YeVf{c!
z26vuHN~(cS6DG@*R0B(^fpRzy=9sty)w$#&TefJKa8zlyycpA9wmL@!g4t>V%VMJy
zjhe9a6x(t=T`rtUqjVfY!#u*VqPo&6N<M6T?r|-dFMIar_Wu6v{lo63+xNFW9^8HW
z={*VApWeOx_6x4-W{iy6@IT&7FX6umW(cW)kok+13;+PxYP4s32no;<K^%1j{{U8W
z&^jax=ceAU^X6UN0N4})K|l+}K<D+PjSxI8@|hf9Vz)+>{TIk^cUMn4;GS7O+uNl+
z2qjo^^AZ$))6@kuq19JLaxNrp{Q0s;-boKI&S?!{2WmgGnAOa=XSLWGAm$R*E&4_A
zFvRJ0@kNKB(L+z?2J(2Hfk&=;o)3MU5H`LGfpqX2->m1t*JXniMNcs{3gNIdvaDfx
zsYb()G-NMZZF}{l9!T0RZ^ct=^72B^F6;D3f6yq@LS`RFlC%s~n-?Z4g{t)cm3BU*
zho$f=w^tQ;tRhv-FW8!Z2f04rfZ>T+in}0!R2uN*-5m@gI&a|TTT)nJrZyL+4U874
z{s_sdXO_NJ9Ej#U!PK3ShC+HEiVWP3O;&XhE)Rb>?hJN00@ziX5>egN`dQ^_Emt}d
zjIz@5*!F8~SRea-h4(cDigP4Z>C%oSpoY%LoGws%0~Gd_8t>ia?ms@<y?uCn`(~#Q
z{U2XH0Ii!pK(k}ngL?vX)ftFj_L-hFC^W%Zf;WWuQJIPxJ6ihHoX6OfBCwg43^^hx
z@{E%WkiKWPL$$nz-J3gn47BtQJCyl-&BDQb>D9@2d<_h@JrWa<FSY+|s2~kjFb7nw
z3?;<h6Wb7{=t=lY+vY8+Vw&!hDLKXaxhj?SbfhUmjy4dc@q8ruldd#2BEdqX86pR1
z3(qmbvz9XiDq?iK10GS~x4b=`w)V?YJ1QOn-$c6F<_V^6R+Hu5Fs_?xQR;CLOx>~k
z8ri5Lea4p_FKWVGWY;Jvcu2rINWDOE^sI<7brQ1=9;H6^!K38IKKQYcrm~1gk?_OD
zfJgtsjt!sn4?8wgQ~8G-+sQxh*pS=hA9mi5U*_)}8<P`vp0obp&p&+s&8PwNb0gb-
z^RIBk_dom>oYDO^|AIpV%msNE&V%sf+FL2&*egW@1w9*4@V$cb7j9`ftnTR~9PiR?
zq^HV>sSa5gmkQBJrvP;;4EAu)CY3@(t~y7AXFUOF%Vi@)#pu`O&TU!nVvC&HEWst{
zqkJ8pm+x0{Bpbj^{&4%JyB$l|@xRB%&JTb&8-N9a4p*$wVI7L>AbqK64(HFQr@LNn
zhF1*^p$*q<DZ2#y<ENu@5M;cXoDOr4Q%82$tFA=sX<(g^Ik`e9Wh=m*UMFP@SZI&D
z10~KSsgbM&6`?lUgW-JpMNcWF*HlkzC>CSN5#1;v9%&{ziGBv^3z8HuLoVtxibDBg
zIWWwFK?)33jzX55T!Fn{+EsR{0%}C`%Yn84HO|PsP?1{9Cv4@|nel43n6%+GTJiFw
zhyC?(ZRO0gAz{+-4?-m5+O0Pd&^z+)z`|OWlboJ_w}#Hq72I*9HPd4y3Pu{|nuTn`
zHDFUJp(+}jZo#nb4>c*|j)BWH(7}E2=pzypVY4tL&d#{PD7JtzjVL?B`#|KoLcvW}
zrXL<oa4z*Y*T;8<N<!B~r3%t<*B=u2z<jo>hdzZI8bw(Ca~d~g9eNGUcjVwXw0WK`
zn=Gla!y~oy<m~|KdBPSc7}$AaIh<>|V5|r>xr8Sb#D2XjOs|taLFC!I`|$qN9b8|I
zg+NeB7lnkDmuq<FpiMSoO{uB@_?-A|By*o(8jB`4XPK<$umRK!`lt!e6#`q}VPgX{
z-4XOd9Q*im^c;R*F}2Qmr%wy8o^}o17P?>r!a#4CE|4w(xG+Q)=(?-gIXSV2Wq~xm
zK^I(@;gMAum0wxH6ywi;A{Q&qYA`UQAfY#dG#aQiuc4r6WTq(bLI)Uh%<4!`ugjnX
zTn{HJn;2Q)Z5qv3JaCtteq8EQ=8uhsAzSO^9BS~aSqSd~2qXAbM6ieVNAdm9#6mge
z8$N(qd#N(KE_Lg9#n<iY^2iF`z;U+_rMyj;K$BM)9fL^Lxs#$*-z=Hl@E}z0c$}NF
zO#^~snA;4^a&LK{67-S2*}OqdR3rVHqVn^|`c+Lf-w_b5Y)W%z6`(>Kf+m6L*;-JL
zJ!58F&_gP&<u=>!{Ky*PJ<ha}6br>N9*RiF2c`i<CZ2!q@g;h?Me80T<xA1~mp>HS
z``3SHj1*GluRqdX^`SA+eru#G-SBtL>96|G80pFXi;@1S4~>x`2WMmT>4fli&grlE
z&=~3C{}&_O_t5I(9_>)U7_q@HilM;k%@)YQZ4AA#6(~*~LCAG;F+815#M~gML>~xC
zPRu}~g;LCu;F+#WEJOIrsHt`igO_slg(71bG)Kng(g7w23}YV@VmEw_BFEY4QZ)-%
zngI}O$^@$P7^0qUK}Er5#+7dJ=nX_-P9j8~zXcN;0@h|eXJ!RG63n2F*{cmVvybR~
z2_}MLh&uVVgJL}U+5F$n3cdn9C&{G`MD;ho?r^q>kQA1=&_Kbrq9;sY2th$s)Y*n>
zSMn$L4%+Z+QOTU_dy+mGUE^7HhwDJI<50iT?W%(7`(q`;wsd_7&Q`OjWU=&AP3Ahd
z=pg6G2+4&ig>iQuJw5m-G7z$k_m!7UbHX%-jdojD7Z}0Pp}<th3WxA$kYf3`Pp-ye
zev3_qRQPo3{pgVmSKodMsIhXEe#~<eMG#hDzVL)x#pbM>^TfNRRE3rWp(9u?QWaVU
z4HjBrJ`_PXGl;Cvx8h&=@mnL<b?~sW`RVdzN1N75PrFyznHL*4Xo4+f^>$0rS3=>y
zGw)~)<8<=|_(Xi-aS;Bx9tY1Fw{@q-SwVpOVzXflN6&K;gb?KAx*o1Cs*zjsYPi|V
z;OdYb2r&qLeEFJTp&m{+g4a|A=zcM#iOo0BmNQ-Cb>VqRo}*;$3nPW``npYK3aGx3
zHDa<Y4<|%{qf*E(g$Mc7R(_~*wB;@Mfx(HPM8MUB5H$XtZO@IRY&2^3Yu9;wib3fB
z83#2SKbXO`aS%JZ*g3?Rf}h<Y*?Qd9izmw3({TmoJK6xd7~b*=4GlF&=T*r>xH3^G
zhRPV*%{c@nP=Lm@?n`ZWG+cypAG=l`M-=9yjDwr#kTPPGAC^*6x5^!9>P$~D=(Hdw
zn4^yPoXKi4n**P+Zc%^r)lq*wf1b*mTy0j%rdl8hofu3{iy@k(;8fWb05DQ)M8<17
zff63cQHautg~zz~<gqdx{Yn*vZwiX@`eH9jl<<9NrAjc3(e{?5h2E1aC;@dteCKNP
z9Ft%UDOfbSv^^0r5M}iXB$1}0^<+06pU#u_usl~AMLXc7Wn{eE@5xE4`~*J>Vpj@p
zb<ZdS7Rt17y#o?|ZX-}qsV8KxFRj8YpuRD*uDM1{c~2W!%%ph+4?KP=4z0ExI0T)0
zVj(9<Sv+q*IyJ-4Q!&?vr6kZKc{S+Lp)@~|ex;TdJ8=+yLpcma!=!Q;3XRcoffs+*
zd-(AuM2dlVQ3Xas=_iExsk=T^5CceBvC}C3jKgP{m=5d@@pby?J~)T~&HZ38ku4><
zclCi`<Y)VY_4HHE2@C3{`oLQ8v+siG?PvQu{sn!WB#Kuf4DhafQYLFvcEZ8*8<8gO
zNS13i{f1bF7zjd-g=Plw3MLSLhtDU|Y4#RuL3H}TG#z23$U7A|7}zR<Ob8I+3f;5A
z9+!GVb^c2cgH!`9qZlgv*Vb_AoX#&d$hm(e0@4l2k2J5CZb#Jw(^)1BRGzs7l)&ZL
zuK>BL-0X+&Wm*7%Q*$Mw#<taL_>pSF<GpdAZJ^<F8)2mGk1IV9>jo7q91Ed0U74pq
zTnR4ZLM@k4X(a70<6R@u;_38!da;<DxrrlmtDb2wLkm>ripI`NSD}UUR9DVPL!I>E
zDbg>~Z^Hd&D~KK*mK~^RuRsq}QvnXNLsq>whZ-$5X2_YFi&fr}Wn*6W2&2XG5lw@y
zZlZ9v09dNc${DX2utWJ=3H{`%=VCz&DNY1rxe?3<N%n2D+b)200TDbsmm4_`<WNyn
zZL*eBxV$)9VrN6<{~A^>xJv$fmq*1$I2J7}^r|&XQ%w$83qTjg-SB!W8L4Wi=bOc$
znGO>E;Vu!9!bbQo#DmrDyAStw-*VX`F=9q*Qf67JSd`=(r0j`oq<UdW=5|s!^*3R8
z|M>}UN*h<2TP?4J6Xk3|{S$Kms>6)>Cs+Wi6>LwV10}4E#q_*%3owG;@Tr{2C*dmI
z*-2y5S)*cjgs65fBI80=oSHOBE(ml0qfsB_y~_(h&Bnt}U(ZxkS!i2Oy_?(&wdE;A
z0M7gtrb8-3&<L~~N{BDyk0qXnc~1`^Kk??&0OceO8W;$8Rvn=r?<QsNqD6*Xv#8E5
zmJffe0@%|@11)Gg55cbgyy0Z|%;|)sp9yv<t~5chGu#9dE41GT6J&*&tBBF@C<>zq
zhG*UB%Wa%-rC0LsZ$6TD9WQXkUBko^pum)(hOIfDs$NN94wYzxheVtt<^tAUI;(4J
zu7!&DCgn=Q9#P7W@%F6tf98fs5KXFfy;VI}OvW?Ro-JCK_zA`cHtS{U8MK24OH0<Y
zw6!^u4Aqm9Zzkd>Jxi2%Y7Ur*YrY~!xZk$b2{#mMipNbMzF<~4%c%amT+g;I58{Wo
zzkC7SuIz>?)z?usXn!aBeCMY2cRQb*o&RhnVCk2tD}jTe#j^?#oib*CG?%suy$+8v
zH=;X4#sr!I<YI|Xg2{0Fl4u855*{mz{K9mvmK#*$x|(ffP#5-)JL&0RseH6x-+f6Z
z1Z^ypZ+mCKI>UH8#{*;i-rWZaXDGKb$%!8;?PPP%!~ube!**J6Q$l(HD4uMy6M3us
z2wHLgOaShBQfgj$S>$PggsBwLi`;JA*>+2)hLBME5M+S_?_59ZuyYBzQok$nTPq(t
zaFU}2nDXI8kKAAI=`PimhB!*7#-Ia7=T(v>YzSnVN!|;G{SP(?rEFKvK?$+djm7P0
z`^A-zT2m2`vYP*lA|mw@RzqyZ_H4R=`922PKOWTy<^}`4ui!}Zm7Z=6K>PAg9)U7$
zp>xWbA#c!_^%b<94(D(i@gs70cyc(z`p80n-n4VnFDxN>yKR68F>)mM)??G9-js>p
zj0qv?%RCnBQ6npjH|mKQsF#XEP<Bj2X~N%Z8??0wy@$4oRulyCLB>S=6{3NL<M&zJ
zM-NA+K76W>q3{OSoy6aXKApjVstV2s8L&hwqDW1HFOuR#?rY=86<yX))ZCoc>N%x@
zTeF8olFkw8#zPH=2i&}1j^io{YhNclf#|`-n*JxaS-{l2LIVf}E<CV)fpQiv>mQqT
zHU>pu0_SfhwJKhLH3(AeODg`~%6d0hn&W0#!xJKJtILvtI^5_}oZjvZ$=z*t3XKO8
zBT1{qYV*KP$X9I#-DnN+fokW)l{RWloOl66ysMxPft6A%7R`EClwNP1TRu9&H1~R2
z)c^E=pLD6WQ+5Z*maF6z;ib&kZ1H+@m2`)!@E7VlMHZFsctS7qFnoVsT<LX*n_a;H
zY*1012B_FOWGU#I0qOt$2j7hC$Z~@Goi^{<;p6XoXxO}KH;TXWq2SQvMe?gYG)7vx
zQE;Tcx^Kqc`Op|??MCr;J~Za^SAA%Vw05K5NPl(TjKA}tG1A(N;_rND%;~;|5<Lhn
z@ICU)5IHT}vprXbx5zykWu;iUX0o}2xqp(4ZEkI=fsTvnB&y@dv?rHoX(VCxbOP)V
z)=4D^i0&svo`HFQ(>PQ5MR&StX3<^Vj1b(zQld-;LaI>Rk(G&T8VckSr`AkIX2n37
zGG-Etf)7MIHgrILx!=Bi1?KM{@<UNMOjn4wmbX6ik)<E9DT|;(G!JGZD8+-`zWVyZ
zk3U_%{`TPq>ANOS27_uglShzwNT4>2>NkiKJ{Qw!+&U{(;nM5R*RJtm*c%=6^sD83
z3r9cH)xE&K15aq)Xf^&TJaj!KEnR8^!F+_y5PwbYZUP9iN>TH{fVZ!)ELguX2Sx*w
zzMD?Q7IiMhAYba8T6a^DqBKR#-_<ZZkUI|LsQS+me@!oE{?C*z1zi0tS@+Y35_G1g
ztgJ%js|7cP#+-jTEtvt*OL#ap9~X!8`aM*x1G3CEtQc6MkM5Hi$-*F>)ogYJQC}Sc
zuT)g9exdyts6HcfXpJds!+ly1cY=_R<zfciFZfJVprEC<Hvp@MmZzbU^r571S-6SI
zuL;cG8kXp{P-b{Q1{L=qpvzgm)8ENd_tHMNo)4Soz=WH^YNH0rt8dvJWY&iu56Nt}
zMxDIcjITCrC~ZTCU{ERNNK;-2s{LRx>YmtU?1who_JbQ(OU+5)N9O6&!6d?`j0c)p
zm2=e3Tm5i*e;1z?jk~fn%EZi&IR}C_WE#|Rv_of#7v7~@J(lAbg&rrQ29@uw$sk3q
zRjZG55==FJ`jTEQEv0NIBmj1;Y_u%taLvPo@L}M*;d~`CQ@ZlW<v6tfSbtg~ut{bY
zmrIC(ovn}X5vVVSOe}P7HX`C_>P4KW%SJsqoL=|RqrNiDg=wpBuoAjwYP(Xh?^`f;
zq?Oko1Idjk7)~JIZdOSV=^+K3U36}YO1U)9<qmURNSusRsuH%ubDN#)fSZtlox4Ux
zlbX)D0OPP?Bt|dcJb^ZtmpDDS?~oSlTI-SCL71LnQaPM%mSb2(>h3ixcOQb!m0!JS
zdDCTIYqJ_5ug2ZO_T%*R^qs6aXo2TjYD+`}O9ei~w}uLVdMYtHZl2+(Gg2zSG%D%)
z5hp;-0$!t$J+o}l+S~Gp$0+o^K4a93r!ClFse4vw&w~AOKMglF7WH_+(Os@q%k|c!
zWB14CHUVd#z9%+HBtc}*!)UWF<9D-{KLWLssn!KDqN@T*w(H!^Pa%MBdN?RyB*D3p
zFXS`)=yf$}>X?EFs`f$Y$X4hM+Q7nwgY(zap%}iW)j~iGS-AP6hz@CassJ~);dqh9
zsz7Iw+_6wM&dr286mWkT&i0MH3DW+|g+7l;{TI<#25HzyCyPiw{2mRUi?#Epq)UlT
z;q+3g*f?V?u%21yW+MozWVJfLHWae^z?q}ridn6bhm>FEGhpVPPWl`mJy5&cYj68E
zVK#M)EH{d?vVNf#_;Dhi2TT?UM&?D(eW99(A`bc5_t|EPIiAlJ%=iMzu-u5%mc2<_
z3I=9wY$Y-V3#WGFLlnTiqiI90K>9>`iujd569LvRbuW;`a^nd{QqZJD^B`)pjOFo6
zpV+2$A}JkopGZ*f7rPlNj==TLW-E+@ja_2{Gb_lEA@Zz(OmR}d^_HAY$@<2@iMTA#
z1UiUS-Lv|S<7b^oFo$$A*?4FhOOvtYr1m8JkX4WZ9;?T-w?zj$&%d$L`V#Y!;51|P
zhetR|_E!vF-IVrokyWauV4SA{s26HayY;WRJ!+V`TRNO+Yi0`M$Gh4cGG6kePb@S>
zHNIo3vemaf5w<Weqj-Ha3<=hWO}c!Bftf)65WtSCjP5b)$UJ$@oj_u%=clWOe|3xn
zD}h-rKHp`itk;eJy{?!&yW0cyxEe^UG7!13Okep@Q^4^c#uMQLiv2W)g2diYS8Ln+
ze9cn?j$(C(RDIw2T6pVZ%fcJWabYbp%-m0ynck{tA!zGZUtex!P2s7lN8Yn;m`vt;
zvuwFJKW+_C8h*G=juaJwwY5ULjPZ>eEX>+Nd7^AfRN6ulOe&Jc0|sJR5Z*$OTyE)V
zRoJajSTJ_@zgm+4!7*b`NTfiMjU&uRflr=c>!1mtWZ+Tt2$B%Rbc0b1QD;*U4Y#Mz
z6Cv&YR<>qiVX?px6gX_SuviuIQCt<LglrAf<w%cYJ0cn=7GaZIPLbXpUi!5wH3;(B
z^dLsl*5J<z5_e*-q*Ob>mk6AdYG~4uAmU{MhxejpC;ZBuT&7L68l8a-!y>l1+<4e5
z_gqHO*uP2Z@Jo+4?`a(IT(S>*!gPpCjd+;Wo1=k0AGQXh=(Vb>*-y=)Dq&!Rpt0dz
zWD1lF&{{#d3e_Z5^*~w-Db!03%d(SuTH1$lYxWO0N$2n<07GyM$BKyr<#w}e^*|=d
zF?ODJIt`TeP<I}6xAZ*~K>iDHEZNHx-eKltS{DG>(65gauWbu!g3`i<;S&zukizX`
zN$x5+!+uTrYLMnN@I%=7Q2NQY2_+9r^G7TXizSyA2}zDnFxl#nGh;CVecQ4;Q;__Y
zxN~%Af5E0W4`$>RUTH!BaixdzZRa!k8I7oFZVF#5u)d}^L$I!uM`|E8W;+AUUqj5O
zsgLMEfb<}e{jBIgS^2obCG$31w;}a2@WBK&VyI4$ReB5tYVZgt(M}QOGe<UoIdx2Q
zKzj;PG_Bd(Ok4x5eoM@#0rjCZA;N9}3H(*O+HtNy(f>-P_H@&yeA-zC=H;q1NB1%c
zYJ%{glx6n%?=)fc#NdqOv?G~0fQvT;%rYWL4RZJf1X~hcA_9gaYE2)e3Z$i0&W#s3
zcSzZ*dzDoYX(AwM)ccEf7eL=C%7X$kLmq80CvBh<D&T-5zCmSFzk(aG0O}RS=`wdE
z3OZKAu!g8}Gr#{8+$iZ18xAB9d(z19Uv$%BL^Z(#z@w5?B$H0XuQ_Tg7wi6H4!@1{
zI^niHo;v$z(bJlwOFdb$5DCoBF5#%(YEeJApD;@}{!{XS%$eBK)YgxVFvhxr%^<kS
zsT+<;DbV+R=Ly%=&kzfW<G`3`lo5?Ku&By3^}r?1a}ifQtDth0%cF%z8W0od+$FD5
z)=aScWn~E(*Nqw<ea?i1im~=B8K#CNSkEf$2MESRn=A5TIq?ajzLbLIYa*PUlNdTy
z&kbuN4wv?Jx!QtSyv13@&K;k=bn{cQS(7DQ$&$)pC`$U{C8!&)3jXF6pHvL%I7A@d
zsHN!I1-9vRi5X5u^+^?}%Ro(vi$99F#1s3Flp1$+^~h@z_DXkoNtgZ&AwrQ+B_E8c
zK=3a08sI{a;EKpYTI>=%pe@`<zR<V>o#72CrJNM;Xo7|mI$qXJoj_l?SbHgWztD?~
zg`0xgI_c%#JLhim3O+VMog3DVeG1J9(w%|Hc|kIv0~>1)vwN-<z$;}0DZ$K#WYvkk
zP=wLmPF_>dJzn>A^Ge6Rq_;8$#mg<esr#|k@vnU(Qb!{&{^IPDBfeO!7sELS8<?f!
zEbuAjIdyX8IdOa_qF@J=rdLvD7{{d@ItqPD!iTeOj(ZIpiYDy`$Hmy-;P=m_i_IwE
z=dw+GLm^<|CQq4I@cJn2=~SExb4i5HZhfPj!35L|GW1}DQ6CtdWn4N_TUJdPTjpGp
z&%0tcDiY3|-kG{%;^H9cG*tXe$*5T9^ymN9`yWLpupAdzmmTjiP9>-;&L1>6)s;r5
z?{g<k#QbXQRE|#ouV~g}scV?#BvgfSszUeZ3M0}r)N)ER)r$xw*m5esBZ^|nA@D5Z
zg}x-Pbfuw(KthFuTqfap2+ah20+Gd>vBCB=)TZ;pnSl!X76o8Db3r2oRlxK;jU9*$
z==+*7F?W*(e*i<yDs7K;v@*LbP`I>-oSRU+i!$%_hPgxRPi(>LBhc!h`$X@;AEHT|
z8$jJ4%5}b$i@1@q(EC%<!YxOfIDUQ4I+v$^y!>g6cvWwPIjja?lTPO-cXUHZW(M>D
z#`TPKE}j@lHdSxGGvF=3G%Rf=w@{XrYPMH-jpd_YLVpd*k8!h9=Z;OVJbMi{-a$;g
z3vZglRv+CCUTt_`Oq6M#J9yL14w@YlKyzLw&RioJeK7FdOHI9zM5;cj;tIK0BWmF|
zB?pNwa;|(&r#yic;_t<r{6fdgwk|#M!@d(toUKS3u7|35MQz`91Ur1ooj-%rJz=P&
z6(Ql0`_L<pI-?d6lrMY5zc!GFm3r7c%x?=;AYytcoCJGkY;&#Qrp~&^iczYtD;0Mf
zGbB`b{cf;$_xAO}yZ58pH*fxM3zx5a+B)H;?u!gWu}5gB3dPxIbv{h0GhS%%cw7{w
zM3n~S4xBXZVe8b9f1?~ARC8VG$fuX*Yu$!g1bt)XEu^rx)(drVhN$8P-FU6YKqU{5
zP7P?gKEQYstfaq)Q}T9+3C^-KLF>r^QI%j;grlpfHL4#rg(S*QP~V<~9tL8sqM=pv
zhUHW*Hqlx8Nq8Meb2byYlT=swsGvAw#2Jv{FoDK)N~Z};X{f8oOTHMbEG7;Y+r^|>
zHyi>@k1r#m!j>yk1BfEqC<Tsawb>SVGd44p|LA=hoDE*t)7|n%bm$X7RUvaPaE4O~
zjhf^6W%p>lw0}H2rb&Nln7S)^nw3Bi8?kctnACQ;Ig>INU{2<5dqjM`!o$AX)cVl1
zar1Jf&02u&h_{Tjc1%%$^y<**L%XpGs|H`7QMz#KK58<7YkhLAr!_q(8f|E@+ug^?
zOZUc=HcTmQx?(Rm@-s}$v_TP!eo;rGU##>DZA0iztu|XTV@(sPuPs!bOljD32W)|L
zlcvH+WJE-yOO3>jEsD{?n0jD;ba>;ZpI<nFL9F)E+lGM^#o;v;*Km5n^NN`)oK@|B
zXj4$*x&=AeZZ}p9rEJh(?Q_8JO;25SkaC-u=|93`<4SjN!(n=`tLW0?MVh1<YPIIK
zSfH(ITKpnIgRv26LzNf03lHSSK%scDz5wT>LWrJtvp*O-W&ENCdDwm`1Y18?e2l-+
zo@tNd+Ipb^X!NN!#-sGKaxcEUUaz3_Rz!(%Z(mA*A2%x21hJBKV=(B5fC8(BYG%sM
zSzxfu?pcY@HqRP%5n3k1iwLEXDx0j9+S6n)_DM0=Uhk;Vfb-Dv^DL$q8`}$oQQFs}
zn1@y2CY38F!=;HKN6Om3a9QNQoAwUaB+qZPgQ#;L&|ai=@97W_E{G%>>?zcqmq6mb
zHGWM<Wp*R);x@$=P)Dv#cm9XJJlwr{_W=b-0PIm!98wDr_9_CMOL0a3FS%84NtARP
zr1t>(K@vHA{c!Q&$3NV?*D`n;$dhGdu_=rL-z^5)UW~X_paU+)>E#qeROuNG7@jVS
zU_XAZYKs`K<=3~y|ATGU*UkbKSdUk`=M#kO%G9B-J8sJ1iTmDTuh2t|)5lNX#3<o+
zMtclY4OdI<1kLmk_E-MrNZT$+XUSgiUiN}&B8%Kvs>UlRLud8BH`qNURTtZB&?(@!
zv!DCe*?Y?riO^>no$VRSiEiD+Vj&<E(pV;?gZ)m&WopQ#*zu%us@;x6Wu^O7*{&^7
z*U26)5o8AU10$Ra1!XbA#VsoP+~42oRG53XvHE+u`Gb-4u9@V_gn%lcpR0bVHhowy
zS>YqNUBYEIll}4}t>-M1RJK6Zh$i35=C|#18JbSg0<kHApQ8TF)9nl2dPf78*_1~R
z1>-S=eLUFG>BV)wag9haM@Lwd)l_&y`!nbagZ|_kZM#;+^vJ^xx;BBTbOf^rh-I0F
zKVjQF9g<m>c35PZ_y)B0as|6%FD9-D(5z-uGubXuWrdnW?(U;i<(bKd8&ndkG)QhX
zb}J|!Dhx~~O)}v-j*t~zGF-)xG%yTFSKIr|_(){ztJzT}cU(KbG#E8``5^b^iz|Jr
z;6~OFu3KFRUVjX?&p3YwjoG@z9hJK=p}ql*GkH92^yt*#Cz!gY!yvaaE4KKUwBoo~
zC9~+DJH-yeXa##!5jj3OzBH^?c!9J|#R*P@tjoxhfFNq5V-WHiGem21-V2c26-~Mo
zp9KWZ7}VA2eE0P9?)D*6UEnIR=Lk0(J(4!d@p!uKNH1jVntS6yHptNfJNE!gK9Dj*
z*JL<x$=cB(SE>X0X!NiDa)|<p_y6+h_Wheb|I7I9{*Mpue)^Y(cV9jHaQD@Z@7}%r
zmp{LI|Hu2EZeQJ@&)csa?(QG%(eDo*zRw2;iQ;vDP%W%FKXtop8TS@~`~ag-sl*^=
zr5}+&Y=Kd^akhT()=(UOxt~&~zHQBYpN9?1wng1Vj}wo~g-M1O<PVe!$knm2$yzmL
zJ<b5JV4KZ|C0>_fc$e`rxXJoC@Q9OJ_R!nP!)0g3&z9!F_%9+n5_7}K3WgIB_FTyW
zwOh*uwB!^TM>aWmp-<1sk{4<~B~1yKhLXv(A)Ga8gPFf)nAb?PJ&T@k3P}Ouj6>Wg
zA0&t;?q;ZuG(WN^xENRZOnWnJN3vU;O%O89q)!Oy+a6Fys%F(0MW-)(w}wHf<DQB`
z?Q~)`jzQ|rs`J2IUYw(lEQd2gMuzA>@3IgZ9IZ1S2_cqLw%I}Zg4#Ift^3EOX{h+Z
zqP@u*nw-&H&CO%cO^Zb7j*d#qdyEm?K0LgC{f7?^ce~xe!TsH<hu81k9(?xC>)Riv
zAKt$Dj75l`!ndj>pu=8<qS3@+6!<KxH$SeRFT6DRLTo{UB~#x@v~dB3bj^}3T&%zO
zbXJDcK^qX7LPq(3RU68Oz<+Ct1hox!$(8&&<B-LkHpkhzj~=blerl;qto&lhuC<}M
zsXUwMJlm@(kUA@@ihE*rF)5jxq#U^bNiM%a8ZB5(X0)U1|B$Mi-lQ`2=4I4Yf&*hz
zAS13$oefhQ$oo_H!V)qm{SuQDm8+;PjMO@=HSd#Ja|4haS-{i`)0YR@RV`XEJ;3b5
zolHi6{F@{yOcq0iuP#Y1MJVm$dE6~Dku^AFQ@L8Aiqgx*ED}GcPLl!il3GphPP7o9
z+}RnZLL&fP9)`bCnsGEBMyCOy@>N^I@Pj#@L7MGoH8&dI3f78jTC#XHh(`>Thi7;+
zlF`SN7J%PR(>9ImZk1M2`moU#?R89?_$;WbP3`Ar>cZpJ@b|?Hb+DCfByH?gHx0F<
z+BwSHj#3Rv-SNRFmIXB}vYdc^^^YuTW!Va)0{vMvZ)K67Q<NI{qcBKWCg>Di#Ls~#
zLnftNBKgpFP&oLd)h3402?QpFOy1;T3%n)6)Og}maKvlzB}m@a<wMv6VQ4R8Rp{#6
zfY_;?Dl%p|EcRx}1vJ#&+7p5=sZfN(zTF{<Ro&7@hHScyh}I5(BaPrKFQzjla0fqg
z^1=P_<lr?M9Z%!fd4M&(3ywky>{S7^pn2B)D0iv?_Id)^O@%HX;j<cV3gsl2Z6y$?
z!ZW6p(i<=vYM9NH;S)xO4b1C^Ug5Ku4a}^M?e}Jw9z)wNdS4?=Xuo1$D}cHhg<z!H
z@?t{ojr!p&ux`@2q#}X?#xtypFw2$qXatD?en6TLQ@96b6Ia>~M)}AFl1YY<-I!<?
z)KiQ4={Y7!qQF@_z#68}X;Ya8eG~UrAa&OLv6mh95cTL2i@Xl-Ms7E0blHXiSvO@1
zeg@fLx$1oin7@sL8zj(>8X1|B{y0Qa+fmIA(Xaz#YXZvX5*!t6{l`g!Gv)53TbAi~
z1z`-*LDV!f)3Vz2B#;MvD$zGWxb<5{awm0Pv*~l27$JM+?ox;kiTQ^pwb^*a=e_?)
z&j&H*9YAMxhf#QZ2dKL_dPoaMPe&*H*w<jr>rGIB^bNIuWuYKqx}t(bSBHG3(o-%_
zUeKhT@B^umrTY*fvjdKE1&*oYN<o;J&Zf%){-ZgxA8tZ%Xe8<Gf-&i+8GR9l42x%T
z0&19Eo#$kRv<pw4LL+P}mbL?m9hTmaG!Yyc*wnR|Sp;##$%FxQT+70V=$0MyX5wH7
z{99&nhN08v$xX8jpl*=D5@Kd)tRtc1)L9fgihVGjoo!p34;nhKC3d@4KmD|O|EJqG
zAMSSV@4mZxfA{v)9Wy^Z?jO!IV~B*2_m2IoFfb>r0oHIby&$?6h8*hJiViW<{IOgL
z)jf?c7@R1Y8K5bJc6YZy{k;h*+8oH0+H~l2s@6H^>geV*?~ZL#bYeQp^h9hE_tc?e
z1qYp@e?C4OJRKYzKYo1l^aRGH$9KOydOAfdiX`2ir!0F(9p+kqRLoLJJYimUMOL-b
z^Xn<18eCDYWH`b~p8Ptp#7YxuXxlhu(Ecgvvs&6lH+(tS?98x|U}>)a1&o%>Bfw4M
z0CjBc&&_&;IOAS-vrw^+QY2$&4y6IqEA+XZk+WA`WX$f0=u(7HM+<5hcw)u4(tV;)
zX2tL{IDV0z8iiP0;h8SggC~scWoxj4fujoUC_wrGXNdT5B)a?yF-=Zx()v|!Pf!ga
zsoJMFWyx&G4FWqSo(Yppilq(%lWR57rG~lNA>IZ1V%N<<54u_C0ed5B#R0#vPz<ou
zH3OQzY|ejLF+eR~UPw<|7$yXF1JziGOL1P-E0~$^Pp@&UK9s*G@Ihh#uQ-+6t+-Yn
zrURd@#v86qPC(_Du?5u7l8JySzw`C-V)o6DZX%E*R)_@Hpw=<$$_GOf^^L6^Dq3Vm
zqWoTy$~~R*E>E}vN<N#uq+{m+{`*o2CuDp55@*(^wW5k5Uv>}J_jeX(gkPw50sdf)
zn6H~_7E`RNdwtFaLV5uQa1f8hCCYrqvwzq7@7|w(c>U%MOAKW(f-mtLJon3e&oXY~
z646P1;{kk*41;&s*#<=422ja|K1x2wr8YBa5Uvv!2VJHYeK6E!hrLsHm!l=j^gIL*
zQb1cs$Pb~oTkIOvUg+@caqb`xTP`lOS27hcZ#0T=W$1f0VnXPbjXhg2qea6134w0E
znp@}`P(Hl1Fi;E8wZS-p?Vd3M^XU$GRdT>zFR<Ee4TY?0DvEMuhce038+BhVO|Kne
z$mZY(YHRZ0F%?~w$^gWDk9%^`PM9-%t(mYkxyW*6oCC4qsN$Os4~>Va4A4i7gI1t%
zVSg7XR=^PJ{!`<b{X**<2QxgJ>DD|3Tc%aYspgzM0ZWH@oMYUMbGVHF#KGx_$hbh0
z&G`HRJHa1F&jM!=r(pfhFNM^gNV6*qN&CX^U}1K)-6FDX?tqAHqQy=VfTO1b8JEas
z4fQTOgw0$<>A)01=Afh5$&G8Z>QvB@%J{M_AF~Y8F7WZ2$JlA|mO653*97aHIG7-I
zg>95`h8_RtyLaz@ynPVkxHczk{ppcaEE_aERV6=$I$bf?)y@^PoQ{RKkDZL>BkUTV
z@(kN?D3TOFA)#aKcl#-})y@vZ4GP}`>ziXEM787%C_`hnc6QOtT5h-3hW~P66wOf4
zoir%H^cYT-%;qSIxE<QIe&!|Dlfa*LXL^AvKqDJVy0isgJ{gc?MjAUhqg2qK@%_38
zbsJjGQElJcH%*ORX{NTbLmG@iaE$Lz^Y&)_LTqBX(pT)hxj4Fixa~hxZp+c_+tItX
z5AWZ-d2{#v1nuu1CVxt@-}>f)u240m4B^j#X)M#Qz8h~ES9+<q6;^=<+YD2qBL(7o
zt#`_L6OKsqw(;`>N{JIXT_eK^v^LEOLnXjIZ#RXBw2Er!W!lz)C9D;j6`7JCKH;N~
zd4;PRB~_4`0e(n`iA0^P*Y^)F5UW#Rs`fG^V+65PCimFu1zd9`<MhcM)jB4*0=fKb
z!~wyCSC^Z$9J)=euG+mX^T^F1=3R^;2(f6fRe=lxl^--8%PVk@<(1$ua?TC&?=$^&
zVS+DPtN!6$Guqz3{_T@V3SjCzzVW8Ht16J@#~4)Pv1ja#TaDZitpT#`to+fa{8{Op
zOa)Ur1=V-vTs=o3yzXF^Zp?7q$83hX;hXQ@ZSLNf<&lzcAIrk_`PmX4LvThQ_ssT3
z&hLWvgz}PMj^K9j*Td$?;L=I0#o#)BdtUIj>i3&3g1-er%jYDXG&8g34Q95!v6GpN
zMXz#p^g3I$=y2~)m^gS>RC$FF=3++w3t7YI`vD+Q;I%-e@idO4>DVISH$a+d?oIcE
zSX^A1KJmC^QXxp);q<;eLmsDnXdu3(*+mv?_#z$AF_6m+3Q;3Jv59pD+e1=s(bfQG
zw=){3NhM6hMGY(PgeXDbN7FZRMCsOPns<7Iq2}d6cr-3F*GW2)zJ9owT}+EQTww}E
zeO6a(ksctkgSpI^hUV}lGO@0{f;;;2gaCsP#N0rjv_mW7>FWL6{i|D$2j?)%!C&i3
zD;?6-)8Ri|(+KFFdN7<y+r&T6B6;hfqJK{g&;PIMnQHJe<wA&(eKia^p%FBi3Zrd8
zXg-@D;G+|`x&C?&1d$peh85!sX}EcuDytD?3hTEC6x9i9(162_qJ$lw?hn&lQG&3(
zOXWzPc8(C9O$fH%59%JF?&==l2|c2^A1F}w18v2+pZJ(h>;~Cw-H&`?`4zi|;=oVd
z+5O6=l2E&sz+l~L02tFfM*YWnfu1Q^uX7ay>K-RNoq?l(WIAtj==mNfrHS+I8(}ra
zV}aQAJsBznWE=0k`3Np4i&-}eIyWH1ZrBO3&A{^yaj_8m9YtESFwZ>0g}c#cqmN-y
z(QyU!!SAi*xnePWjJ2WOLwqHE&siZD)!PrkHi%?5mhnf*a_|tY1pZC$2(dXZ8>-#!
zOU_8W-}GR6`Qp*wFzf-Fhueq9R;-M_k@~$H7^zdV=WmcvXGlF78COTBbl?>p^ptxr
z_1Ble^VBw`dMnaQrYph8f`f}X-89`m3V;Set^1rT9%FTmdiA9qWz5ZN39PU@XN-L1
z>d=DfsTv+^-lGvzv*m@J7_|BnIl<rr$To6QC~FqBD<|gBLC;h&6soYK$D(*^StF|^
zJ-<VBMl{$6Ji|l1qT75mzZ!3f5QS(+%O0WzbrA@bixE4s>2gQ_HCjn6Ua`8Vy02mC
z4gthMLkm}cLMmwkA5oQy)YP`CwabeJ+d&pPOy351Hm#pv>9m*Xpkg!|uNA5s8CJL=
z@qP4x$Uq-33Bi8Zqym`?=aFumAqxqXCJ%ETc1SB_Z+bQ8a2~$k1S&87bT&!aRr6Gx
z;NVNvQK|WkHXBRm)<e_j%5`(lXC|EetYHhLQ}5aQAOtn_L}|A}LLpRNNbEtKpGUP%
z-`w8+uzL6ByZ7UFe|}rU;da9H2{3>5Atpf!C@wHx>If9eoY%h(WLW@WU!a*hAY2|-
z;47U8{P>;!?~?2qxOCd^l^X0o|B7w%U*L$!4!bZM?*RwR-UCKOlSfH8Gr56|228f+
z=z~T~hsP~9Zs4JA(Ij|I=?WnrJ7k9&FRw3PmZPr@0!lWtZ?-3P_2JE%%b)l!CmxE9
z?_PhOEs;nkR~c)PiIM=VqevOF+aO?wECrHDoUv*}h8Qs}a%SQ_oGlEw15I(SP`}?m
zFrVs~4$RbpOyH+vbL4hU+tbQFZlQjt1wUlL#&Cn1jL#;$PrwbCWZkGEk=(F8RInHY
zam<i;h1+lKMR;34p6&GdssY(i9je>O0%9;Kw-66Ktzr`Z%5Z&tnr3Lh=()?Flq8VS
z`V@^CkE36i2z{>1zC5t0;-K&yqw_6PdH4rL+IEwkWU3YXdqzs@iJX9jap4=1`-4Yr
zT4KtqW%cN;Y$)*ty9av-XQBK!>R3*J-Xb3eqlh~;2e1N)q-Y~)xAB1R6R1tc!fdB4
z2lysb(@Mgvx-6rkGviK7Ttr2Q?ZI$;*8dX!fO*~R?mj-;y}gHLH5BXz|Jj40f_NGL
z2z_7T4?EKm$G^}*pkcG<9ejrHu7}<~9e&ySr#}80eAfHd-e>>z{xe$aaN`%eoZ(7u
z`Lg$!LG+BCo`OzLY2+zFkq&r<011q7^!4S6r#2p?*6UOXxULSGfvgwg1OXA|U99{I
z6&$nM?(+HP_}Va9;UVY*-;vgnI=bb6gXHL8tBAeHu$bZSH1?%mYESw~E@m@O!o@Y)
zN>XmSAVKw&r7MAqCglwU?RT?LiGiWZwt42x*o@xN`4eA=;Ao&+c%)t<KvO;XmxusD
zrNh(Za%)H#c?GEXq86lRb^LDn{U#$~Zw{Eo?u3*HV(xC?-2W$V<I6vRj=q2Wr@J=3
zPavA@aYmBQU_a!7NCQfX8hr+RK5?p9H`5ir)JvCi{o+!}(O?3gWx}*e_9$GiE)1E$
zSIG5JwTG5=tgE}-)4XtHB_dHp*un4;(i!%l=X{1ukq+3sPjxV@(bU|zBjzNoG}J_J
z-5OHwnkG~;Pwe2?A_wD%xcq!+4-MHu=G`n?n6)=%h@+=Ajnp&jExFLL8+trrTwLk#
zhJ8Jn>!`=lRhSu|y&<&6mlv?_A&qadMRx-KARjx=axez@j5Z+Jk23S!ERA{V9nkqt
z968yq@nk-HIT=H#w{=ynw?Nh%Ao62!_2gME^#(JBpyeIb^5<{Ut4lU`u>o>JvPGIW
zy0~Gao+3MJ*o^Y=1oD^fSfn@hYE;<CljX=$Mf-(jMRUaxGBJC}fa!8TM+fZ$9m@^4
zQI=-qqYC^{!_=J%v>07N>_irY2^_Y@v*CqT{qWqn6;?4(c7)g<c<<v07KBY+tneNf
zG~U|+>(xO^&qtfp99fnxPiZ0DQ+1~9lfTq$e$bR_Fd{L`jtl({sz7yaDtb&*FpI8#
z0Wasxi#&7}e-(KjFuk|HHSl`WYvt8M<mBXFdfJ$Q8m7mj&qurv@&=PBEwvOKVBMw-
z1!V<%elKt0h|*f43M5AjYF5xY9FHc{Buy(x?h_bBzFc@f3~avC?&K7plG!ovux+r=
zQfDQ<fty2y(`<6%#uw0smZ*mtGtBn`U&+W{O4;&s3E@%$NmuE<sfmk7S=X`I6HEi~
zVfP<PV8Fr9v;{+8C#uC(cvN9`%mwdhxO19Nm*W_YUCfJ?{;~1!9wO;dU?g&K>fkb!
z#TAEbQ$`EP)5sDea$1`c8JP$o4kpz+T(B7jV=!-B1#~pZ(wHIRn;U6bK+PTr599b`
zB3lf%qjN;81JWD7WhrOxx!7!<W01BQfvmuZjF|7|GN5{5Jyi&K;nNNjMGB_OY>ZK0
z;2?fT*v%J^chxZj*)}9Jx@}0Po!bzUvc!RcEzI(RwJB2*q%F)u0{y`!G6@_tG6!^J
z5)hKMbPm939eX;#G>5*YpRC37;M6_Q)R#D|p(QLZ+A(L`iIjP@W0$4_iW7y)bkKP8
zuAg5<vK66P$7?J<g@FVM?3cRJ@D;)vmA&zNzNe0Rg6081Qlpv^l4pu<2%V%+)dH@&
zY&)5HEsAs>RXT(29=ci6ZaTuqEgx6<j;>ql@R{x&dN@T4pt$J_B@RHD_j~&nJwkEA
z-ZIEFo<OgEHF>~o=Uz!L4Fe?LS?01^kvS?T4KADH`aIOo$6^)pr6z;?Emd!f8eU$B
z-OZO%apR!mFSjkzueIh0ciuXA@HkH?Dr{fp(az3<C?Towhg2`YPE9%)$Fq<>EOR9?
z=K*eKAu{2l99UilR>vU&H8$lV-7RJplz!6%1CN6&)80;!eFm2evKhFo$fW1)o>eA2
zrES6YQ^taBzwk~H<pR3l@Xb7%!_1Wsy{pkUON$$({$0rkJW3W(8U_DNDEPX}etUyf
zlCc77#nV6@<VW=3cO@keCFp$?c^vx|*!@_5<X2}y5&%sJEhw%OAu~(!EzUF&&~`Oy
zM49`?b}iF0LR0fMR4ia<q$Q??Y?I<7L9>6?d-(AuxCcQM!Xhp?m9_WVbJM3Q7I+?1
z>TO{ZoZPG!WpVg41XpD--r&20DKUkqL7!e@)7|6aQzU}AuiO%d?!&cW^E`MZ&T`>~
zk#{2xDz>b4=zOk&YL_msLL&B!#B`p%kJ{=OxHTlG4oDmW`WmIObr2zLrcf0=2SxTe
zQJvsonIUJw<U9c*F~ttHOj_v@`w;WVV@Oxgf9^jyIevD0baMD~fW&A|PVT-!tP1)N
z?^-d8(gV7e_fdBTX#~zqM7ZidHY7%;H&(u9wmCGGY>g70QM0Ulo%x++wn8$M!por=
z=^)_&(p*|f#|wDkT%ZUvedcBtE95M`Lf*)Iu-TG1tbn@815$i)15zRj2w5Ph6<JI)
z8ZJ`?)xdIEUrXnEB19_9G6iOv2*q>Y&|_m#-43g+h(p<8{BBe&a*efJ9{R{AAk*#&
zbvSoNA+v_Oli?a0&jAq1dNLh7huKYQqP$8-DY;G6-Oh`+hjJ^nUE|Uw7O2>vWg@Ph
zPt|o|-;)Ym^P4*BP<3Q?fdKacp3+b<V7CvRM1UGRs}}girUxEv$51yVsAeUdJE+;E
zo?ZggbT#S&frn_9M%BmJR4Svm5LA2E^1OAj76H<W#rtF<gli%jt!rzp$?;*uBUHp#
zUb~LiiW&jM<`B*cP##F(w&lC6lynYlKU&-r(y!I~O=C_lJ(Kg~+BDW_L7PQJ$iQ`l
za>l69gY(2oY{}JpL)#qc*PotIvqF_x1dYtD$CESJ0)qZEpav9b3UXz>EZwecPSH{q
z4cCN1<Z&}r&l3GSVZ_!PID@7|k|&Cz*l2Iwz5U+)`2d^2_iyjMrNO|hZWqvRh!`9m
zMn)>~hMSKB=v}e5&eq7+h+<*mRX8`R&~|}?fpS1>z?P4U^w932;0zg&O~`irEFyr2
zLkevz%9TkV!%D!9p;N2V1o0E#JoA8r3qKB==~a_^nlQpyI_2gj?I;$a^FZPZicOmh
z)m6T0>YTy>v~`ecjQeV+9$lNTx{Om)qvNqFQz&b<LBf`6pp(_9DJhKH1@oKdIu@m?
zo7ELu0^LG_MY&h_e(DXRT2(xs#rr`dKNbJM>eMD}D4e6a+`St)r772Vp=q;v<YqM~
z2o#lYB?vo{3vpH$b&B3iQ1DYYV!)0_P<@RY;bkr^U#tqQMFG(~hy5I`zOXIeFGykW
zo)*kdMMi9%zY1E<BI^5Uv;@^5$;QFz4HP4d=^}}OJU);-PNdbTBm-CjE6{BvHmKc&
zAdi}jD{V_#cH&J4neZjuUL$^(dUt3QXBS^X4L%w7J`Gkf)2OI$A|@<d=^f?5H}Pc+
zD?ddxU61bc@G;$N`^YUGw)<#0HA27D&ZIcgYc^;oIOd=t`z=NNky(m3EW|zif6TpW
zb6ZJrEvlb_YezUJ&uA_IQjb2zGbcbiNVEt70zgtdUl1ILno(FSwe=Xw$Bz5k?^-J}
z>$Nx7_8fmW9nm6oW$nFdS7l}8JD~?BQ+qmSuJx?orO${%FI)X#3)QDpTLe0N804Ts
zi6ZWloH)R?IAVceePGT1mI{)Tu*CIdVvh}wXVzurst}TNm($7W8q5zr*nZ(2Q*vsN
ztb|AJSsoz0gct>vc#_#e6sEsJ5{{$J;Ki0KVST;^ajN_1#R-HXim|B|%%p`6(r2U%
z#}m^+pD;TohhqcVPI`r5tEVq34I2iqOpk~=wpS)r-b3Dd?I{VS7l`mgHL>}4*6W^D
z!F3yvEwZ)h-D0b$GBRynub)<c(i2=Tyr{YRKxCMp0a523G)9b_0=E&p=-ONybk|5p
zy*S5C@=!yV^~eAerk-}!binpLTK>w~X{L-QTeKsE#%435+H0P57LY92pkAbA%9Gtq
zgXosDZW=_ybMP)w7kC$HifLdNugUWoiu#`OCXG9vskj?igZ^vA0p8OX2eAD;1JP=7
z0tQS2i8!z&#<F1aomz=})Ch?Ne7O7T{eFA@FW>Hwi1+Tpe)swA<CmY`f0d6<r&k3A
zO}bj)q(f2lD-fb81>b)E5w-cge)|kx5iwZjuaQgRY_W$Rx`ioWFg%73oM*w#;e*p)
zNiN#Vi@K?qhlKC9Q?u3!`Ej8I<{j`up!NTVxn^5;0G_aP2gn0s0&x?COC3Pv+asD$
zIrkV9(XIT62`I3)bipNCH&KIz#|d3rG3iY`pM#^p(Z^5kKYn=s@&553>k8@gl;q2#
zBr&8*ew{)54s;eeYSzZ`8e;Y__#QYai`nL^F)Jefme~)~uGz$lMGC3iYlJzC=d=Cv
zr!e<g_&PW{p&zo27hgbC=k|Q{Kxk;uLt}M^0GJF=IXtw1WSY1Sf1F|?{>XzWW`Vqs
z84nw{9u|`mQ7;p4WJ#_q8?`>so60Gk9~9|R@3K+7MRP=n*4t%A%xa+;jt-0PQWa}4
zk1IVA%Oc6t9Uh4(&?Bp<NR`yIc%~$~r%01zye`~b;O1x*(8@&*sRX{zn{j9r>HNIW
z)Y7v?RByT5O2j7x#P7~LCHy?Y4gDu}rR!t2YH7l=5BoJOH`zMkEVd8yN>Q?-G#t^U
zg!&3F?(##h{Zd0cLhK+Sm?y2ki=k{Mf>y`2t;Em|aXmn~s8lk;^KRs8^(lFR%HW#G
z%LYYcI{Z*cT{`jE7ZIP0Tb;OYEM#8jUxQ_N7RGyS3N91GMKYr8^j9EFd1Z*@Cc04y
z-dZ9(&`A%-AC|L6xEPr~%0^m+oNMU1MbuIsgbxLihgG~f95_<-&<J>|WgJGCw(ZXI
z5*{gwCzQF&IOV=Xo_LBud2m}3e{FK(A>I`8)zcyIro>axs_8Lx72Da(Rd1&13S1%M
zxo1q+ZeFpyP)7yfDSPO1OL0^&&}fAWDgF}nKqP%pI80<sdE65i<Ju()jA8E_8)NsU
z_=pIL;bG<#GO)Kw-;x?)Bcy9#k<spSAaYf<<jvwKg{q@Mr%q1a=z%h+;p7n&PVi9J
z&P4WaR~vYOq%h1Hpl!WdKzL)3s(OyOTN6k_*PCk*z1|8v9dx4}1)dAZ_008{E-1Xv
zmlo>0QnOGr>ml5pK~&2*F5A^nsQX-Gq^q()?+OG&r=rd>AwNSg<_EQP`oN_0d_E|z
z5!L)WBfp=BBGL7{2JXiB7*yP{)xgkuehyk4e~Wv)q~d1(BgjB2?eQ?jq#7tqdQ?2_
z2w<irup}TyG-{<$l`PcNPt49y4B?;tDIf3Mj(TmwI&CIiKS~rwqYM*p5|I1s!}5~i
zu&7>PUd#&^Q!erL>RR}thrYsbyM6V-blj0rv4W&Yfzt2Tv=zzIHdrDeY6;dovB(Hs
zN5ZsAXhr&5crsKs^$338_n0L6DS7HpJf{$fldb?C$C#)-MR0aWUjcbldY?3lE>-D}
zO)wivxPxw9!%MkY&m;*NP&Z`e6{)UnkHAnNz%ikSCu~?UAALfHvQev|ad<J)-b_si
zrdM(oV@H7fpA5mI)R%f7rvv9U93trqVaBg?sUD&j*aS#!ylTF(0_lZ*rrH8<iHq=V
za#PMjnCL>P!C!i7){8`Q{@_p<wbHs~BLg)8;Z-K5^l@pLppZIF(;nRSYy~um?OHZ!
z6n+3=7MAeb-Z%%F%+}_D=;fgOLiY&`m{$z(XDbM$J;^PJMNJQVM_&+)6=OaaV`Jb@
z+|o_ZiA=BN*4+q=2_=r$@bGdlr~EWZmN=<RkTnU_uhQ&M#YHz_3#n2;BdI-;0nsc2
zJ%)oYAQq+rWnVvB1QVxz1MF(I{n*aSPn#Vk!5M9Lr;L)}aj71$_B=p}Vj3}pCqc{(
z^~=a-*0)3joq`An1EkK}jZrbr_GY@$hzJ)`J!8Hp@@bwTqyp$sSvDIY$f*$CEVK0R
zTe9hky7|E+Z>01+<;lZ(kXN(X_L@X22c|K?q7IG~|CodpSAy^Ns9f^Tu*!8bH`eZY
z8>UO7A#MNm{vEUrZ;Lz=Q-$F`pEJ2w-0-M!*Nm!J?+OsvS27>dv&r<TwL2f^WV7fd
zG6v>O5M}l0^S|DGe!IT=^5y>R`0d-z^Y<T+il>xPALynbQMJX@0`5-lKivHrf&;(Y
zPk#CE)ktyMni<DB%aU-%U2OM5_s9*G+f$RUy&~ua$^w)#gH%PYpf-U~2kMK&agsL2
z?7;N)fR>DINQIV6UP+j99OF<z4gQ~0oP>-5-7WB!X_!j(vH@xOAvhtu+SyOi_rZW-
z_SF}N(Ph+LsV?JLQ5(T3xsOLX+@k1BR`6iN2|5*QUe7OYknbeEwQ1Lkklj+QBIv1x
z7Ib979Yv3eoM*6&#_oXiVa@pilH^{~HJuuo4^$zuz!FoliLFqB4tj$QLNiHu!DGMB
z*9hwI<0I2D#FgMivbk^9hbny|5kf%qLc667gVXxfDX8lXx)ZthU+ov>CITm*Q0QUh
z8E-S2z1&Z(H=Y$fmGm8%QcoFTOzL8Gsr3fwLED@;9kAZ&>KO*NG5FYLwM?dmr3<L;
zpx&B-(SrH<Lf1jFM&Qkbmu<kGSFGAlMVB7xq(^H#jF~*?waFxyy35xRtj8P*+v2yD
zE~`Q?Uh^&J*C2=0DQl3Ug&KP4f09G4X`uRt=ISW`ZI;Z#t9AWahU-@Ypx>7-1)Z#S
z*k*VP_zfzNG8$T}QAsaaSe{2OcjRY!TxoK+i|Mi3P2ps%dWf@j;}cfqMV`e=<P!hF
z>;@noW(uc4$>N5Xgw6&m)d%fcsg#g?M^@^Y9ATDQ7Z^vU8dgChb`un}9kdPV<>T^V
zFvvC(=T2@>KS^T{{+N<tjnlumR-dE=rau>)2AB^$r)20tZFXT=QJpd5)?|VRW-)*g
zm&SR`0mCMopVtY1a}El&;N^=Z`)E20lgpF_xpYI~Dw&^wrZ8p})^GS0@E`->A&wB>
zp;3nDU8f9+u_dh7tK?HxlgULcr|o=M-l;_wO#l-7h6)3`NvXo1i;;+W&cwVy_=igx
zxsh$odb(CO@F6ZWH+d8Dp_nGK)47_ZEY5z|LbcG@i)a%0gqWm-^i}i&J=L1vf~7D|
zAARrI487^#vY)dA5ElWuZ~LC4LbKx}UHbP(cqvx`{9o`G9T-+MVAy9V$gAh`L#J!`
zbV3=;o0_lZJi;aVpat&O-7J!ohskY(Wzz1OT<K09y|(Mf)#-IngPplKV{tV-XhiFQ
z9%T7Qyu`6zXr4k?rbZq76DoeShgn|_ty0o2fXRJXd&gUYUT`+0asy|rRmK$_q_!xR
zn@Q_#f>`TP&}cw<vn>`S|5R1ZHsapI&&UL^r<e-1?Cqz2|J7TpD`WYI2z}4?Dog%Q
z1nMh~wrGOp*wh|A$9|zHu%&b=Jz`Tq`5IuJS>)K*fFr&IgVx-li7&x+69dG+kuY~8
zT(Ur|ulz=*GV-@>JLp!52a#_nP8X$OAi=~PKd#|&Sr1!GK!Eg+5>Ie&z|RjkFP#<}
z&0yXPZ`Qo<c)_{DQ@G>fQp5BD9#Pxxc;~XuR#OAh4en<#T^8w}WQ(>Ijl-4zrxz-z
zRvDLFa5vx3*vfDi?HJP$_CsTO97U#DGDRVOH*<Hen?}viC<=~2a2}09#bPig&{_b8
zlul%14qnuBq$YilR%b~YD$K_CYdl-gVDnFd1yx1Rftjts^+xd_GFE}K;ULw%EvOxu
z^o;lx(hs1~i{Mf%oK`cJsHyGIX+ej3;h@E0B%33sxUCN?m6Kc`BBGf594C_|iSgOy
zl{4_tIB3bu39whq8X&ERks!zsN{6bPVZIqcA=A@CcQyyKmz&6kvt+BT$kjRsc0?|z
z_d|zHw!Euipf=qg`5O>}0_UCa4oPw=Nm#=#fx0EOIJV2gcu`ppL&vSEFDcMtBvBUz
zM(M!y-E~$jvL>0|>+PVoGG77gaFYpY9V2p5KkW>2)wi2AMx|{dLdlpShDPR^Rt0<2
z_R{;D(2y-;otFB}2B;gzhqIQ)7G`ENc=`mK8Fr9k$H5^O)>oepPKl>NHO(6<_1fn{
z0$5F>zP81)^oOg4df81U92MxOB|U-XWOJ>33D;!s%<#3{OtIonz2hQ2F8PV{cG5@2
zluhYGIK$DsU3;k}%W9lsle&iBcum9HQmNU~S+Cpcz&*U-c^o&;M>++iwRZjk#)Y0X
z&4#vnFo^C?n=W$?!>}lG9an<u$xJ2zCz9n1xiBX7vZ_fvnV^4pGMb-$|DIS01kvaL
zlzUDP$GXA1j(68vSAvqb<MS+`D>;53(e)a!T#$DlnY8V;9e@;6q!yMwer5K1H+yVx
zt<hyO8<M}wpnwXi8!y#^%z*4Q*JTzIT-ZF=w+)h{45@@HTM$HZKnkYKfm&m&K}2;*
z3N7eC1Jn)LBrwT_{S8&Oc}EjqpP~6JQEtwJ-S#yF)RE6kdJTpZ2Tp$n`4*PDeg(!r
z`2*74rzfayPjjS4uBw#RJtoaJ%He)#I+!O#(^6FC;WhGgLC#1FNa<wak^oVRD_hhJ
zD|H(UC{5)i)x9vCUU4mSkVW1~V3s<cV(ReZF1(JDIF(=55Hj`!C+;~<7!C->*JN@6
z7uNDZuSF97-S><8ySFJvGx-om@Uj>AIy$>SwX7$g=oel6wnlMWl8j-m{N)4$Kuwo+
z>J~JeE|}$6R{_-3&Rg2PmsEDTn|`|1Cl(4B<`;TaYG~Bp^FIMMjQrD5oHH8Z{OI%J
zfl`Zo4s|spL-YyutGYB=;^7c2-=R53Fb$o<0=vl?zB?EV^~<&7ib6_EI#UV`UHXg+
zGog7fsTK<ks$txZ1)vRoFg7%<{1Zi_Qf-|0j4ZMD!tKLiueVBUeOU(T(?GaUf@(+V
zyg#3Ts-a4}1zI8FcRwH)Woeqg7_`bKYtm<E&9~5CFD_%n<4W*gq+ND^Cb~3BN2L;P
z)*bqWB7|^o6q#qdU<_n}9#K<rj(B0C7vkf#w>8QFouXZHBcc-(>5Y8}+fOhswy2f&
zpHno-TYr272BIEL3r+YXA#bvP$7#YQUgeL50$9RY{|6>utm+y8CjEJ6u|5?@O4cY@
zNJbe;MSibt(m=RgWCym}h@C~)f8iahg!O0FNLPW_>&vn7cNHeZiwPBbhn;~lTwj6h
zE7KHGX?pCR{ZS^D_-T1dl_rty>d3ZeS>Ai#1bSE~4M3L7I-Od_qi^;05s5QSm+H?s
zau6UiDhw!8OGXg@#-Q)V&^*8|4e>|GJFOR<m<W)5Jj9MFy7CJ(;I9jN9#tClH_)f{
zB<Sy|NeeP-#cpHQmBnyKe=^U=UnsazD$g88b$0LOx5?MK=g1Z~qg-PgEKWoch1znc
z(=PkS*gTNYCXy8~oLBo7VrHmq7{Ftz1J0jq#<G+vDqRY9ZDMvff2iBWf_0rEAPpv{
ze^g4$K)bfW*`J;$x_^w#i9{lZlau1t)`>IZ<lmK;y*yun=_OhV2yon3moKR+Ml(K{
z8!IVjaeh@Pg-W|C3326bE6U6}c)S-6;lff<w9`a7!oj~6iv&1Ctg1`s207~nM&`@%
z8Ql(>wnM6+hc5~lD|`iD7nmZHvcFmD#!Mr!0igWfIjgKVK@BxT2d+sq+P#G)2vK^q
z;r{edt0{^{I)Zn=dZJFA?GSp0?IiNfq)Uyo+&4?{yq=E*-T-h|2$8kmi7U9CVP%uC
z`-g+{b3ZJYZcwgkCEQ~!<f)4!Oy{CZNX*bs3JiwyB~;%cIu2e1+YD45Mus+ku&0A=
zL}~{t2jizu2w(umYRyV0<=tSUkh|VD2UdHj5+&$3dUE`FxE?-z8Gn5PIj8An^|;a`
z1-3-&0J1i&nb8149LW9Cl9+-;^K7P+90vdRcz_^s(`d%7s8rsjM-Nw3+a$g_s(uCu
zwL5j_iKaug1+E%z3-V)^8Z+4W;RD)KYMH1_RTSAPeF-9If>GtcA1R@q882hb#xWD&
zuSlI$RycK`T0|`kHU_OU$KS_%HU2}Ce`4B~Fxqi0W%n;wu92^XF<>KU5p9fa|K+C^
z1JJDj(z~@Uv-<^--SoH#qS2me?}0V1=dlTvzX_)tv;#n{;@FD@EkYq*$O7Cvw*%Ir
zC5SP`g6?2JeC#Z$K<XS*9?mUrQb1~(xXlU7flhh=*C0~RB2mwvxz=ZBTCIZd$W1SC
zB{+p0PQ{PVp<*iPOZDLX#wd8qDl5XxiOy9t;o4Xy5(io_Pi!g7aiv#S3XqK-PiE|$
zvGlU8WuCs<uF-HBCzB-*do>v?D+1Pl^a`Un=0s@LiWcRdaiN+BK;2Ls2Ck2GPW}as
z$H@gkT#;cA5vxcj#Ojic@_L2`&)b;|d<6y=`$R1mSqYe&4klSmaE-%gBFO^%0Xim<
z4p=uK!NJw_gu@ytr9QluCtybWPv9ei;2v8kY-kW>x5%ANnnnKsUTD-Mdc!j0nLEY7
z^XLM%3S-G+vAW(GdwivI`vvG4Ae8<h>nxb&iIxV{Y2c*Ah2Ce3FlI>({`eRW6iRFH
zouG%;;K>ipLxyW2Dj)O{Q=dfYM;h*k=5WQp%H!Yck71V@ke1cxrzr~OeqqB^-VInh
zMtl6j6&e{eMF5dFPmP<k=ZX#*nZ7(LjrcTTWN;`gINdXUE?Vvi(Fo@a=PN%=Y0(i!
zf_a7~k`d-)<8}?YN1j9L{`e8p@bp0heZNAoWBweov_nsGrKMARkusY3@cpYxt|s@<
zH>3$U;f%pX<go-1u+Rf<za832G<jYOt&blUWh^~RU(kyI9Z&(g_^nm5%n2v8Y*FyE
zARr(ERpJhzEqHxk>##Dr^Zn7Tfo4sy;x%ljX`Rf~53WBNcU)ymGhKCm9n%EUdm!n$
zz8kC+$<a9iY_DCd3ZM>VRX!u{)pRgHip1z_Y!<HY1tjsDIzaF7wM5f=wheyNu51fP
zbOoZV&lP-IV}kAH4Amp`?Ov|leH`OTkK}sMax}g~jxx3sw7Q1rar{yY2<l0j>>)k>
z=$xR`5i}soLJgc-%j!*rb0zClys!c4jYbvmRWgpdWr1&1XP^Vg5Q<SC3ck~#FXUN@
zvl2;+7B|nbIsqO#G&S*K5PUZrloz^B^vYwL%zG>Xo-j+2f=RtMOBU_KE8;@;>O{*X
zRb(FRwB)hPHjA|q)=gfXzA*VYH(jC)XW$s+D6UwDXuh`7&(l-5dtY4Xp{=pU@IpD$
z%&-Eg+$|^@d&z;e+GG~Yxrl~zcoX@mWBP?ye(HK`c@EvR?bEBF4p4r9J7S0zxxPex
z_1ZzBX!p-!s4C<}99-CQ@S8h-G3YiKek3;pJ1<U%Y{yka(eP8S4jPr=5qE_W<(4*y
z2Bhv;3jkalRnqr=J+q}vh9{}?nc-uhDma|k^1+)P%514cH2%<?O#H%UI{eQVC=EJi
z%&5xz)ZTZd;&Asfgbvg50{1lDXTeunQB$T^724NC=RhaTG-<(FObJSJA^^KC?WvD3
z1F3(EU+80WM$fj_psm|$^F4_x!JSZ&r)<5~E06|K@j8}L3)<^!DXQSk3*p36&MkN&
zAmDj^IUU`MFOS~6zyI*|w|~9+@C~^oj>^<&-u4dzbs7Bq-w!y>$Adrop=i-)G`>>q
zEJ$h%Q}>wR2xmUq-XMK*|0>jd^4pw)AN2|x8K@ib{)jiDFk*p9SyyIwT<FSt1Gp0)
zlx3u}phy;Z4hl^_KD=abloIQ>vcoYTuJRHaP81euJG>+N#%?Q-ZkN(=z}JBEK87Au
zl}V^r{G~cD4|FP~O>)nPbGM~GIcPjie|e%66r^C3dZ57{dQrS!7@|fVhb_0I2b`U7
z#J5mA6*~=w8)EwO^#wkWMJa&#wD@c}X3VdUtt{pR(P5tcqo<GVH7yz<i*BdqyR%9?
z(ty<6a0x0preK_JX0t!ecrp!-iA2`?<PSuU`5)!c?>*TP$r{xiGS6yV;1da!nd~~^
zPM}=XMT2n;A&XCx1!{B}wca}&a6N-`MuBdE9xnZ;r7CCML$_*!yWfS2jLGB{72SK?
z$udyS5q*S;%^cD3!)RpLqK%*rz$fon=UL~eAEy-{56vYYkjJF4vPC5KyS@K9`SkNI
zcc1Sa)71zi>14H}lvJs_>It#e!L)74FlR`NyBLm|+0!H?m<Gqi;}QQO3bk~6tQw$h
za6CwU45x=MrRt$ujkm&v>Iu6eFJlmOjpdXrF>KR5hi02Dd(<5a&MBmJX)=K}0ME2i
zE^=jGOkg&Io1L0d>c>EYs@RH)BBUi}^Y(OTfEu{)2i)|{mdSqgUIu;aXsLu)a0WvR
z<#I}}KUK@)D+fx=Z|>z86HIRkQW82mx`H8~G3vEZ{^J~gN}b((xrcX&d^LCpjVdnV
z5OEzC$qZFs4a&rFo1!dr(g?~E4eM7XYtB}i#cB|VKXOWP`p#be&jIZKuvAtxNb1Do
zL5v>Y`ash_lMdeY5Z`AXutlDfDQG+-Bk^=tDBp&HAnq&!jGf*>H@28}=1N>~g4K(3
z<>6rX`|360!JhIofe(^&Hfb$8-SiZYBdi<56^cmkV?x@rE9e?1W*+HZvo-TtwG`Bu
zT}%NMw&pI}KMW^;%zNgzKHW)qhBw=u5q*C}h1Dz9SNVkqq3tuQJ<=|fTK%%!uq9&o
zWPabi+CWV*RB}k^!#A^6wOYW$Zk$(y*fc;$kJOzf4W6=hhN*j_#D{-}lTOcS+lA}4
zSc@>*oQ=+Ui#&R}CV{&I5j3unMx=)1SF{XslZlGXi6IGUO~;L#m4f8sN3<EzOn|z@
zTWDKmQgoJKugCD>@uM9i2fuWlH&5>AVC%7GST(Y*lwsBMr~nyW-ME>GXK3L=Kt(Z)
zz4Io)jk^$3;G~&Q+I5yj=}M4HypP;j1Zqs01(Ur-epD(@CLOBab4w&E+w+>&-pxN$
z@71EW9dv8Rv~U7tk_}g3N)>E3aUK|n11HqBK}g_=C)nEI$@gOL0`7%HMZ<Q%YnVoW
z{MqI$h`fMMH`sPJ1K4k%u{n|X3o9P}!<aSvMw;V?{D;d<dJBjHwz4uuAG@hfO)|9c
zJ@kr(jjuXj8=R_PdMst+$!fDhp$(9a%J{3WyzogGJ~I`#6&-U{t@0Q*|C%<_T65U^
zpDGwkos&)tV^$O(_@Ij6S8jXgurc&7AM~r$?vJz0YQRbBX-{I7`FP`=<a&@=gmUy(
zq5T-UHuR0OAJdD)yiSFvR*axO7kq+g5lP3u8G(So+U~xC7GZz<!tFLt93Y`rq=Q#-
zE>JS%mc*Bw!{vA}KZY*@k9ht^H`|i9xyGC(0G&BFzZi3m^rsg^Leyx{SJpZ?Ohv1|
zORNm!VCc&s2vIU_a5gxZx{p5F8MzeXdy#{DJ;oOw(cb?o3Ei@N@O&oyvy`%;kA)h8
zC$fC!jI@OJrAgs!E)Y#ufHXkpGRIg`Y6}kd^7g_L9+5|+Fa-?)ekEk8n>E*}ih)A`
zifk|$^TidbHz#AGk>-j+cBTi;lgJ8DpJ^3H-y!Z;XtKJQFBc|T`SoVG$j(-*!&N^_
zyevaOyhIlW)SU9s653#$J3Jr<JfGUe!t#*IZ@4_Jr|Rq!v+h*S&D0ft4xcWqOM>Zx
zO3dyTx8lIpaR!{nRz=Vb+(7v6>eAy%&5dg79w#VZupb=1eh#(4`pNT)m$renL+m}2
zz3d%U25MZ1iHXRL)pUwPfF_WPqWB;Ti{P(PWL;bd5qwX8dw>p8Swj}61(CM3w0F+Y
zfti`Y%WyUU|5^I_K+v&zE54FG=XTJ-+b6*_WYuai-zgoxr!UWH3UubHV^;J29Q_HV
zN7|d*U5=4eCGXGy>J}n|XVpPH(~@JUA?mEvPjaK-N4oUwgxkQ%^!vDWU{F-Sl@HsG
zRe`L&($SOQ@rZmLD9ADs7}nXU7DHn(14v=1<tpON$fj_5T-00=X}eBr+9*5@_0eIR
zi&;ug`|t@i;$-rjf;`e!NwV}P)o4q!hrvZDIS{;Rb83|iL{kP~NBZ{Ja=gaS8EM0B
z-|#v=l+<i{y<PJ!h6G^>2MXCi%iU08TyEFs3m%XRot4ys&qVNbb&Wl=KhhnAAq#~N
zCBB*T)`jNRTuxphslnu>o4(SeKDAFjp1g>BxAgbX3y6`_-B9!@$5XbeW9FS8%l)5o
zPF;DMkNp+C>4BRb;+pc%>F9(1@yRQkOXo;AtgHRw0r<_u{3l?@c~xk|m^*Z`a7f(x
zTNb?YyAm-m6%*H^(C=zDxrJD^fA`3?C|pPYV&CIRi>X`8RRS(&n0H9e6rX$xBH9az
z@-5=V12^4S+Hk1T%NCAlGI89(s~2_naKeGS%Eo7B<^~zWbCsE-UR!MtZ{+kFlw^UK
znamb9kZ4djdNqMw3O?ev&h$gMXSM6V00Mom88WZoN`h>kfW}4Ypu$2CO?ES((kax6
z6&C43OID~%ZDU#RrCU#_EhDQ{tecx#lRg(}UM*UwOa)TxHu$pndScn;M#iz>F+~9r
zlsx=_sUXRdZe;bATQuTX^F>-r1XSU~CCN<zR&ibQ*&U1HOza9*)s~b9v6&{g78Jyc
zyK^;pjoMzA;~8)w>a#vj1C~qTTAb)DMGxA0>%XGCxB4sEPY*oj>4EkaSjad8AR3$N
zch`BBhpYqjq1p|FPo=4nbjH)90&m{D4{W+Bn4S?#Oqogv_6qa73-6snoou?H6(WVa
zT0t;C+z^6ut8E^x9T~3MGST70BYR!Lcb8ki)TcdplXR=^1kMJ1GskDErPzeH5F({d
zurlDN7cRFu3<b538Ec>e#zTBeezF#G9LHuwSFjGdt%AuoT2uU$@%&w&ah1WJ8ut=c
z8kduh5R1aF7T4;Nr%L4Kq~vs}X`<Lw&64CWy9qymW%?$n9yjvd!?Kl!S{JIN5*;pc
zqLoA;4-TIKqau9%u>p(u;RqiLK#coj!q2Jegx$t#p19{_TxnLAo?P+I`iBb%ilZ+W
z&mk$n+E}x;r(QS!T2W*Ze${yNQ2~oq2kEm-jDVEC069f)wWNx;w8e`I5^z{en$K{S
zt6+Mdwm7{8<s?Th5a%LkQ8qOjjZD{kHqS|?aV130fuu?TUwN{*Hl0+x3ykv-L;<Pt
z_piR)!(8y^c#UT%CMJRjZ2IVhLI8_ORJJ>_f!oR#mQjc(vX=T-Tq#<1NW5j(w&xc>
z#u!NJ6OBC!wqkF6G!RV%rs&E`e(0x`LfGQMRf(Rl@9P|v@kZBDALyi45;5p-1$C{L
zhVcu%Hts}LtLxfbxrXRb;4=`2i2`5Xkm5Hh0vleyI|w*5TPnduHzFzLb6xx~xFxI@
zbK#y})1^RvjDFN@8Yq|<RAgexK1wymlp1j?Z#_h<)2@4*r7shTRGhL0E(3{kg*Q9K
z!m%04H|VtJ*<7y~W|AIp&d6aC#H5AN1a33i^`N&^PXYaRcX6b6=wZ<1NiLA#F((WK
z_$<3<&|1IL1BK~~AK7?H82fG0!M*j<7NpG$4m1nV@F~}MStC4XRBbpcg4-i83aaRw
zUg^|i3eS|z(=J89L=tmGG0JEuI@D&3q=P7W0i_&jGX>=c{-^+H1}rK3e=Z%o9fl)4
zvpfsc;$LTIWjq%7Wni}0W=IT2f<5`emWe=fyGhxez;j3E^D?ws4Ym?ktMv|ffPu2R
z?G{fVfvQ^i`i(b827^yE66G|FqWS##Jo$<QiN*slr3q@Abh{V#&s@>r^mi0L%m(PL
zfZ`52efPs>VGDe?ADKSxFgUmlPd9`7Q=cVzW|_+17+rHzHB6%>g}P+DrLuf(G?<OV
z1u1t&DvE1%==5_Q+14r#mtn`l1){+pWedXwe4ZR!Tr*H7*Ks0(O71pLGVH9&p!B-_
zUG&{48TtfIw?s&Hzs+8v%E%KD<ZXw+8DD9f8ougpsQyi>MQy_1V}C^uf8eHv1aYD(
z=o6+M2b;nMQSSU|JBM+iO(Wa|3vG0;usAD1U-7X0;Mu8SRJn^#sAP53n-;BxYSLR)
z&^eVXAG#LM9lgU3&uD|mpGx4ypYXEnv}m;H;De=kwls!F>ccwD0<fY(#tF0JR#7<?
zlvA)WE6`$6gUE(8cX`Qq1X(@}V@N86D41&MKc<L<UR`bFkKNM_0>~Jd{mo*#K>VeL
z3T@^PRp;OpY*hJD-<#=oqSQ``N=W&E9T_}-+76uD?cMvY1t(Y2HIRg|Pkt;Gi_abT
znkpk$qYhA*5P4ANkUHS}v?6e(Rqg~xo%1Kc^u=n&uwIR*C!nT)&j*U42Eqj9y2@{(
z2I*18QYe;{ssoszsyn*i;;up^UWz_;PXW{|!Ff=N%EZ+(XiE*BEWz7$3al|@pP%c_
z`*P4-pj?#ZWY%UM=aWw#zY;5oNuvi-1=b*3rcolG&4ouW7m0yJ1$)m0_h)w4dcyQT
zVmd^f6Z~^(es$reUO_rD0G{=MlntDt=%HI3RhiOxeRiqi8#v&X+7D@Zk@%j|%jjK9
za6KspI;Ah6?g6Z<_No7_9!_484_|CoP=c)wJ-*Ye`uwOhiWp8Z`W2Ci0XBVl@5ebE
zZp2ikhnW?69nU{iU_%4c^GaM`$(B}=-G%Em=NM#&ieNvI^1>d3&qBc-D4nG2bc6JW
z(a|{XV0}7hU8!M#i(F>s*?iGKj<B${)A4(~+F&YjK#O0ikDUt<UI!00r`DV@oskf5
zz|Mqjb$C2+`?r@~@k1%D^vui_DEuaAn|d^_u5S8=-w*yjDlQb4V!nB})wNBK!Ee{g
z%3j<<0S<JDNg{<#`?X8FeY?gG=oO5G1aDy^NDdv$YPwZ&XrAobn^XtKAJ+#LN)$^k
zQ{Zs)qOk=&!{UScfV0wWI)x^+2<t(d0n*K71oar7r0vr2lC)jA@;w=D1<29cZu0`v
z!S&6>bEqU+>_$qom`cMpn;4>rx>{uK)^Cg}jf8BerOQ01Zb2R^jU$c*Xl)Rh40Q!s
zp=zb%MFG!6VrG7!Vr_j1kx<$vDn2`{64oGP&Ne8F%LD_;ryCi2joB!m;6rYhRv<dW
z=K^z}$#LF>Be6k}{w=SWcec6KH#1=aboV@G=aEht8N^8(c8d{|<Ot`rZ^Hu<Rde#`
zH5;r0xhZW#xJg-EU3lB<XG^3!;HGqkj%&?NBurS}Ecc7etBbpjZ$F@f2d568*>@!|
zu7QtCtdu0VJ|ELJ$681?bZwYsrdSkPu2D(UF2S^hWIj9>E~~J%cXYtT!pn&6Y{sd`
zvpba96qn%QRovR}(n<8W;PWn3)<QttAXE*brBgaa^`0?cv)0y-6m*+Gqk(Iqg9^be
zFs6??Q_3V`kZl?;bOk_~@3z8SGVu(wfFsIbjXlD$L@%>0I$G!*Gv7K5g`SvH$lWi`
zuICVR=zrPkZ`<25B<<vNTl6AE=4Vpa#^hD*qKh~{#Dd0`O=(CcBLjYB$iFpm9qeW(
z)5-V*JU36yaMofGN@1v*KFjl1?VjLd6sSO45RRl$h($<|?F%4E;ZI3=;BVlGUn$Q`
zK*|!&3c4^v5no-Q1|7M-;yRS+FsG_M+^B0S@QQ)pL^N0*XXZ_RXi2u@_e5J-qm$2c
z=mKJ@+isfaEC`_*!{I|zK-~Z~#&v~@$!HD9tz`c@!1N9%SiNp8Q^ug#OJ!(+O#<yz
zN(4v`iX$Wi5C>AZ)}ss8ZC~iJx4e7*;q23QZgL<a4-}~H3h_Rv^eFbjrRn>-=D+L9
zOQ8d6mF}jbU=q5B^knbm@XGIJ?iz@WF31fd$PJeLLe$Vd!9@oLYWUTNmAGj?`0(lD
zpY0!3aL9C}2>W!qT4gt)XG2nuHc_A1WRyzT$o+ke<QRw+hh)yfJ~F8wl&D<z2BdKZ
z-YEcTqMFs<b)x7Mo@s45Qw?$CsWbG`lhdjNrK!hqX0I-%r*(Cjz7Bdh@hTVINFL3x
zCt7g6hb+OX$+|t-bVGvq_mS0tsfpGm7eM3r#?u*0o&A`XPHHosU*=QZvB*w&9v$I#
zi*nhs#GD_$pd$c2YVLHc@@&k62y#F2^)R&>3<AhMDQeU<+Jj6jYKcd&8<VG9B($tD
zN%U%-3Ms1#*Jo>8f$FSuU3#>Y?doXvqZv3rE`h&dR;kwHe`b8|?Wt#IdQPR3=?_{+
zFm?B>h8*0l3bSLq4;`2vKlBjL7@IRBdUb-SyZcXIMJ@h0ydnPY^_?i@uW}0t0R<YG
z^+lV!umS4Rxw<nbU*Yh7-erXutwK!#9qjxhU<8=qaEfpO?slV_tWkt$3)=^bHQVd6
z?959qR6`QdqpF9-B@qx2$|i*>MwvgGwLH{Ik7#A5lepPm+=c5l;@Xc>pyrQ6Zu@Ey
zIC&Yfq5{KM_!qsg7XiU<t_Lk?Q`JG7(rTj1$Af=jO}L>p1-`h$leMNavTNG&yVq`P
zTfM9`6ntZ4l(Z0dn5oCk-MLeMXL)khc!iu`q|Or}U&j&tmw88jX>&7n5tm5hYneoQ
zK;atH0}Ah;9#A+4^?;s&Q#FiIsER8Ukh2H=D$Xho4nmAR`gSgyy~@SiTriV(+2XZ-
zi_=)KdQFzjK|ZWS$tw2)d$EzJNJJJ_L^R_iv*U@Gv^0p^XwhT-4aOaNvU=B8D+NH}
z9(6o#bvzsPDFJOVy3#WDwB&5aP+(Ebq(#q|ES|vR$_82fp5hnQfbuC2gh^hJ;Qa`W
zkH5ulVF-RdCNsio83B!v;vK#P8(A#B8LW%m+%1hbp{oPp*^yhnv$2EuK$`2alQyX7
z=iu;S0-57W<&`A=ss=8HeW(JUc~piR?p}U|NNF6TR@)HUI%yb`$<S)UIp^SNX5(l0
zD1&NjJsT57x`{R>V^%a<n0q5@5L5Ll2$P>s2Ri8m<T|$BsZcLysS(l&q|OQ3ge`de
z9$7I)$d2*rnK2NUkW*vuVOaj$fSHIr%fa$Jux1?AFa{wnd^@AbZg%;&UUp2+dOZCV
z+(@1D#U>nfojU-;qSjce1uW!%5@%VUyVxxkXKKKlLl3LXQgS5EjK2=&_8O#N`6jU~
z2e(i>L)4bZ0{JF}ZQ!ryhT&EC#y}N(inu3;FpQsL4&WZR-m%}S$eG3SbTzYGpkcnp
zMS60}xY9`YAxfpVy~SAs23oTy1EMj7cvok2N{Eju$OO@Z8SCMnidb>^$d+@inW!;D
zbEDhv3nVJxhlLzL-@e^WF4|I6hk9u^#{P-(?9WbS*~BfaIg#9oP0Ar^J$_AN-Q}RC
zO<TKgFW$oW7iPbnt=-cpkL&~-IAUj96QUfXI(y{uw|PAs-&}Trn0h+o2l|-=zP>WN
zl?-I5$#9i%B-KinLI`BiJ3|!e<?Lp5c~WyFD3xpI5=kFSnjssNazLcz(>b<dI*w8>
zjb+Qw{1qww#SI<#S_7NT&aTfRcVz@EoeuPo=~6va33kpiZa;YLLmrWJqlFgVl<Hjv
z@;fLEg;^eV%bATMF7#+Je6W!)noR#fomJ0yPX|3V=)IdeAo({p_H@vVdEreZO%p{=
zn?{$^W+*z3ZuO;l*v>F5j=7dV=buE)G~*BEJ26og+olT3znw@ILd8UNK)O2}lzZnm
zA)iSp**KlzJ3+XqeV3mVJo+m7QLt$CMHLkHh^c{D;yITbE`YdwJXIpaszrfNmAYIn
zwgUqb^I()@FI@Rb=hs)zrNKvOwnPooF_LzPhCaP!h63RJ5&o1hwruqnTU!mI21#<M
zMA(1{6&AZC)bF&eL7AkNK<TRUKlJRerSr8`U44?C^_j8B`C5HqXNHsF0+!{)Yx)#&
zb->povBv!b;fEE{MC2+!lN~tbMl<vSC$97!TP~ec?rTmBAe1bujnoI+x!Q?bn5q(K
zK*U*vv#&5k7R!!2C7qVymE2&Md$5M!Vf^gOM^kt!mex`3Ro+2=Mf)y>DbMF-C#Rxl
zbWBlMd!CMH3zR2L7t76Yt1zRFYh`4&b3Q55k`F8~+RRAP_h0V*^x<A!7vqn2A3puL
zurZZD8^v7IYGaQ5&JF1$O@V|$Rn!3s*T`sI$fN_qlF2pXPcj!;0Chvpr-;;s6GjhQ
z_f@LOI?l2IsXG;S*<G?ddRwS&(Jpi6poEdK-dcX|id=cFIarBkM|mM~g<?E(L9D8s
zrnabd8tI?B5OHt*r?7MK_}HL~h?QQ(RHp{vt1<ak@KDy#Nj%H*zWq*sK5V>0LSype
zj0M8*vN$J?z?3`(iSYiXISJwy+*ZLw!cF@1?GZh;izGY$`1l|A2uOeb03QK75V>=_
zwgJc(vtsHlJmj~B?tDCe-Ws$b-FTFk2B@nLX~hpLkS|VPfzkrQThNP9pC>!Eqn;~n
zGgvn<c7S<!xV25uUK|=ND6uFPYx29~$?*_#tu-uVP5Ot#!GP-Bj$UNxI@~}F^PvW-
zd^VoEyjH0J7(iB=35(hu{bOflMP$u9YE^g7u!Q!JMv|GE&16mR<wFxT^+6JFLo6XN
z!{lLVS;4hgh69~6VD3U_&Qa{VWaM(IIw==7RK;iOJeTZ}(*Q;?p6tSmp;)y;9BI?{
zf5mCxi(9v9ONgq<YyH$Hto=5a`InA|tXMam;BP#rXexW+eLuG08UAVm>65f}#;Tv%
zN0CD@YUv(z$UbAD8nWmrB%SGKfZ$H|A>V;LMC=0$B~4(C;aS~5Z<PZJ!&P3JKMWi)
zz~NwFpLS*M0>}G1NM2z=7|B@ZbBZ6rr?yd}b{5ofLz2f#TVqItq$VVkC?mJO=4(A7
zxCrt0P+}p-deGCRzIvV~-tCx+gB6YU<ZIoVwRYrftm;dd-y$FEp@Yb3v1pN2;=;8O
z8Vpp7JQpJ4b-FBG>4|D^X6zP|m!vl!T?i`HsqC#>sqLq4pWocW8}i-zKPy$$78tT!
zo?RfG(6Fh9@D1<5)3f`#udd)dX8B<)AaD{wCQcwA2#$2#7g#v-$oqta(U2$D4!+2k
z8CM4X^!a{z|EF(%Mp049zKDyzoXysR;XQWbOb+xBvf408Uy<&S&(baA(B#mnyU3*B
zn`T#|$Qg~FX}~#l)^{B_PaYFYeGmK3at&jWW@1F7Br)aMnU!vKi(-n&5=^++L(X@k
z7qE_39<>e3J}G$<vE;U11SUIusEW{d(y7Az+CsEWY+PnN*^Z06Mc8_>(vS9w$%#h>
zCEsmx=o|G4012kS86RII8DQ=Ke6ceKy&ZHb6r}=EFMY&+r1P~OFbgCYnDO;>)EMgl
zLy-&ke!X_%!Qn0|SV;ckKfpNjbQxm~9(V%458VwZ59}2j+7G_~UA(gUgMI8Vzut9r
z^Xso<pI?1ve$cP?9mAJy1#avSbC>H}C~}<iI5rB~&7N<Z4a@sFyVZmQX1I_;`UFd-
zL}NADu>Xn1+INw)UCr4vXtFpHF(N<8>}v88I2Zqg@V|<af!{5v6LmDUjG!WuO1IqV
zW>W;LkamUHkdSebk-d8yclHZG&M4vs0y14-=kKj52=?kFa<9&AhCx7c0x37GyX%(@
zv+AtF_C)w{J{s)=jMhY&cGFAv6Oxp<y^W+voQc=AjM)xemCB+3X`;pMg3?l7);iJE
zFm>0V<RqX>456;{X24L=W3oxU2B#<OQbqwO&GMx_Fodl!g3`c7ZC{2Trm9_uJ|tsf
z&BNC)y)GZmh<yNkzFeGHu?N^Du3_+-{)mbLSaL>2+<kcer_Xm^-+%ge!zA9q9gvJF
zFUQ1#m2?zB%d%iXj*xGNI|m-*<@EAx#BJ;-4Y|(cmx_s&IUd_CX)fo^8z7eu+Mpj{
z@(De43=kRZT6G#3h)!`9g29l<uMmT@&<UouFc7>)wNy|2flg_duw>Yot`$#LT5war
zs30n`NsVEN{Rx`i-31+Uw}U=tO)c$nL(`O8dK~vP7a5pFG{;60j};+Saj7v$hz4TQ
zKeTYvwBuK9z^VA56dFrh>PC_t<m&~UENZTu3@@$d8h>QN0(hPEC8*qH$8h1gOk(h=
zO&<-PI|TE23sa_(Nbdh&#gZR&=~vSM>OuJ>(0tMLVsdeDD1bvL4O1W84)p+7Nu^-~
zJ98v$fv!p|W7)~Ijg_9m)w1BRsFpp3UiSKt<qL;?@wBMT=hXx))&HzY{6CX$9xl@+
zwJmRbZZI|5fBUj~|K^`*klatMHyf1H<6;r-%~t{}X6Eh49<P(rp&MXH%E<URP~Wdf
zO@ZSwo}nF2#VccKBkl#)S%{&_Dfl2VW1KYV10kS{uONBH4{=5L0-O;~0p}sw_VAKu
z+rveoZ4dv5w*8?5Djclm$3iM}eWxkPqhPDsIbPU7RG21COi(Ucv{g*fF%v+gC$t($
z2&hyV(tM0U`xK<@2ZhbRRGH3g;LZ;&8YU4<%zR7T3TR$M6|}<%3VQD%3~iCtpurZ)
z6|?q#=UPR0bc`~R>^wh!JB*VyA6GDf+uaG~tZ{U;a_Lq!ZZR2J!SsBo>9MUK%{Wwm
zr6f>8G~@YDrW48O-{3?-^?}AssY_hO9ByUUOH|(>*|OOK>$ch&WTieJC}m@i@X<}8
zu2hJt{EbksNO2F>qRN7o2`pr80`;XXVPas{)6D`WNpotN0Gh$NiAf=ULNOfjnwP6v
zO9)vs$b4j4Z$vpnd_R~aMnsq<*|lI~ME#9U#tMMFOF^MUTzkF-RxrEr{+F+x-@bqM
z4mp<pg3Mj+r|TNanLDOQg^)9{v}$^>rWPO%IuFLjBT!arT9H1YU>fF9(lYhjH~_A0
zpiWjcUlbPgN}`_ESBZT?O$amyWn!YPircDai;Ke&BocRt5A7-v>BS8E1w^APXx@qI
z6KU?ru8pdO?K7Mt8#*tLdI+fJWP}$&{8!9AxItDQR|}3$T(@|lWS@4{*!ETK6ZcRz
z6`5sn8+rkixDqbgh>&#|u3u9)Z?hufl9gsTz^a+8p7ImcLU81EZaO|C1FAF>Mt_ke
z?zkfoxDp3qQVBL3L?hzH$&7i0H^0zG`<R6h^2i&$FurOIoeO<D{JfYfr`j@YW34vy
zH-*+vT%$W}EwOgej+80F3>6Yc11I4@kQx5B^RPVkZG%7>Mcw6?Gv`R_J>*^VK$B$g
z?>UPIR&iN&t*sB0!fxUxAISCB$K)ZDw*&+LY4egfd=0(+7*=4oD{N*60NoA#?(eXx
zRcV_JZHw7t|Lpkb(;t8}qkNmZ`!5$TB1^6tc!^lc8tVmb{6Z@v(su<N?Pd)3UKT=~
zqPi!I@Ca+P)3ggko#5&HyR24JV0xvr;~qD8iEc0%Q#d=Ang!2wQVWE`k)M*1pX2~(
zTF}`o#ne_PQG(ei1Oa`?tGSw-dc3i(P6N_=H53ro2%@#;Q_`xiQw+l*5x?+DM@}2K
z6_N%zPk}CaEQ3cUb37NDZgR6g>OXBRA4nIfo7Oi7Bcy+UMHELCYc->TupBA-hVa>2
zE&}ty{h4Gj1NFQhh-X>cR<aZYbmTUzwCgI879WXKvaX_TRsX<r#;(I@1YEBECS_38
z6ddfSF=qOS)iL{nttYhW|6Mspp8hR4N9?ADa*o7@RpQg2w^dW-qPu4!=sFS~hv^n*
z!(?NV51+m;MFr*wsxqQvo-79aWJBcNGFKJ~<oQ{uxS)qh*cEwFn|mIbDL>&938V6-
zon*}*S;RotAdc|ABqaTHZ*u%beBIpn+z#aG0O0JWHB?RDCdD&&@wHyPNP-C|jm0pR
z66nme0Lt}YseM%3tjOc@L*fVAbfWw1r0ex^3Xon#{YqVrnC}B6Grkk1jS~@T*mQJi
zMQX_|SdVL@*-}%`fYiN4N_X4IVTi+1AYC?Ym*%fQ#>V~*{sB~}AX>RK2ix!yP=gVk
zEE#6KoUF~j8dpYipv!o%pB#OEjF&U{tX&lQB01mu_Yx8J&^f#_%(bV^c9d><Xlq#2
z(D@Ac&^93cb2z@;m~c#O*~M~(qs7qIYU4V`=NFn4!&Y!M^Rr&uw(uoIzShbMW~YW1
zUz^-3C|G!Dsf*SpAZ=J_b+{kul(F*_ZEUYlQMmF`5_Tq#dNZrbbaq4i8#E|T@t7vA
z5c~Uj=+*)`*Ep0(D|`I0NX`mRVJp_O2j|N)RZcc6?UB#BU(`q7?qWk9)ZJ_RxCEjr
z1tDy!#u&$ZAgff}P2-IH=aIt4RmfZis9Rt(lsh8%dAQOnQ2iT@-{Z?mI(uwMIqc&p
z5Z+8-Vh8hLWyrJ3*X$!bzHZ*W1=NL3#sW;Ne(!*6rze{8ioRf9@K_G$<w4KM9;j)I
z++*yiX^Y}Ylh|i>8ZGO58s@eM-fy>IjN`!e1M(~%)^lf|ArduQz`7NZ*q{N4YjK*|
zzVW9-DayFi;IM;rTa|!!aKxjyJR-tatTWn}RdQD_Zn#91nV|}*q3J=EGP(#(PeEcg
z+n-P=D}{-1+^w1J^t_p_dDa*wTm5rx8U&PP*MC)IE^X!#ADG=AN+Qed5BB@i_;~7D
zwotoXUM9;IRd)Iu3DqJ2Ws$)wY8%>2ABeLd;&k9ZH>Er%d{P{Z^WN_7Kn1LA9VBHB
zW!VENJ@y^<>Cgx`I|P^<0)$OE-Yhj89|gWf#_A3r7@H0ttj`_5#i2(nK(>;2ftuU%
z@%1JBH4`Qp2K03iI@;V`UwQ6XVCSeeH*M9U5il3C*=)X6{J0Z!Cd~4L$>C>ML8?u9
zy-6FV6x^_V3CWwrL)*gbBwcFj2GtE=y&J<?TCssx_TacJO6pD)Drtn5I%_Aq%C#1p
zVJaFD;n?z&Tb>=N*<OM5QKaXf!J#sQCWLRzp7ZWe-&(;$KoZQRr%X3r3ZBxT7J2BM
zjs>SX(6i!7Ut)R-n$^SZetL^DCK4e)Nkddx(6t9C%y%o5Z!BNg1J)QT@j6v!&W0il
z#Vw$b#X4PTXw?(krxr%@9KC9fFymjpHNBv?vGP$^524C@OTlaO_0Xr-9AS#q9{Nme
zkr0J$DcF1X*Nje0<HnMDknNSfF)F2zCrf)ZS+HPZZaeACRjgKrIu@Z?221KqY^Bz%
zIW(UF*=He04KarhKh{hz8L5%V7OjJ(*#szQKMJ2E^Sn!DZ{N<kAwYUnDIjj<w;K<a
zHY*gl7S6p?&GZFv4;ah;#7t1<NSfe;3;k}#FK5?l>u%p&-H{aCvBxj2)|*$h*{A}x
z)inLJM=5!fOVy@N*Lr&D`xC93wRq}#H6=cSTF~C90JCB+&4n~lJa0j|W?))xUZm|d
z25+ay^X*=WrqymRb=9*$U!w-@)EAm;CL}QzaQE-3K^l^6B=hU*PqW~}*Ek`kD#l8U
zTFZzYmSB25NFHdV?8_Fmf+V_Z%0>U+qKcw_#+HKAT<qK&Qf$u#s0Z^~NSf#i<MdR)
zn_49+F6X6h{6dpM2Fp_`O_0&3zp`ae17Z;*QK+b=K+S%NQTNfv8cJX;9!=v$tqMV@
z&V~9VeaA-VOq~tI8!=J9ZQ<4e^QRJeodCcNI1kn4X9HtSF?T1%-ov0ZqtK%bO7P%6
zh_cVVrBr97xAmyk2OHTZ@LAZKCfmHC^`T$5(fd7~u%O??wjG+?>4lI3HYekGm0wC*
z*x~v(>V$zHz$c>sG<U_)hQzjU!ESH};6pc#BE)8@MctaNN;{$OfD;FKdXm%zUHW=x
zkO3I&muD}74$H2sYrS6E%FDm?DxDHck5u<Ck=UmTL7-Q}bf6$lI)<ERQ{xyAJt1@9
zs!sy}yVMT-r<|j4W9b?l>AU<CkyDtF9`~8<S8pVs59@mO3X~SJi^71T7e+9>G+^nS
zrzhJf)E~f`V0x~9KP*w(LGe4yJskJkG-je?ajia-C8GpzQ3^u%N2jTL?z{c1glGgH
zW=t|lnpTw4WUD*hq!{D07Txe|k2r37K-hZo%P;%C-hF;g#lZgS{m;LAxchqlWiUD(
zo*bWEqJz$1T0k#ugO5b+Ro5-hKW==58hrGvd;96%VW(5z5YKCd4VCaGe^`9{^7ZcH
zoBJn!0DJLU>?<>@!u*c7Lj?A;z2ATR-NnDoKYaSv$=45bvafF_0)eo5Njd1ZxKZ5^
z{n7$(-nN#z_o<u+;vy}fZ3lR#j)M25^~pCDPiUyDYT8@Fv`SnyrXQT1Ws$?pMI}gm
zbvun-^o1m~lF{o}`CSCVu}U3>oet7FB-A^!LATtxdV25SzrG-8eojlgsUDfabT!}K
zB9$GGaB%vFxh|JC^UX0bUheO|zq$Wq|Mm0TFTWJovi*A=>Y2aK*@j-uC&6s$U{~~7
z%|x~XWt<b}5vAhIwFSoNpbkA3yy+9ErhyLj)-5s<-W-Y(uexX`hV9g#!TOdtPxnq#
zUeTKIthzeaS@ibp!vhw)E}U6fZ3yY5=U74Ph}4qGxw2<!ha6W$wd8<Ckr_5tX%LF<
zMK%wtf1&Oy%Vn6!rp*Q?B}(&Pns`eqdz3rrw2LQOZxF{r-_GT1y0~8U8nD+$Tn^W`
zf(jOgH|GTh`1$^_Tif>(<t6h0$YT?(q?ujkK4EC%e2H-MK3=l`YH3Z3$l>+HFyxyO
zA9KE0L5fhab=#KD-6T_Faw)AV8e;*|%WUAV;iRCB((|AT)lJ&^E`|Hnm+!AjNgyr@
zVC?A&)B!fpV8Q`%Lz9NT`2^y6|NWQGiF8+lz@0L|O1PJ#D}+i@cIu<y1Zo9ivxGJ>
zu|j2IBBUD>oj_UE)zZ(~r$I)&0HHT4xW@Q43$2;o-qJII2Tiv*_+VyO@JKgjO`HQZ
zfQAe=LuGopxOH6gtlYpr5@C0C9IokknXfedh_OY|TX415!iH*!%QF^o2ifv!ikW9N
zuIJ-pP(zdUO%N<3eRpOzDL?Z|cqvYj-i$FGN0$T1ioiOEiE@ogW_`**mA#;bWL)xN
z1h%D~<0}JoL&08eTsHF05cg$eu|a;;aK-_LuD_NnqG?RnFy8_jP#SpTDXG$>dSJ}-
z?*fnDUJs-NxiLbYb#@}J-rbjbEtpmgBA@h4Tu;e13^^pRL~lgY5BR9MNw2hR$35xl
z@5&C<f#zwcUG;|^Xzy64iR<*x&D^*cE9DH>_2>6r-~1&R_LcP@wwM){M=4}vN2!;p
zuZKOm%@*S60Scd7OY^KSwpU1Y%h{PB#tNo2X@}`MeLd5zli1Y@epCeM&B(9bz>5#k
z+QtVOs+}Cl*Ywh0lZind^rPR6Mo*8QpS*bb0)N10p58w>Iesxm<rOk(v;$M9_la;P
zyb_{k`Z?_3T7^O&093yjNA!J-CHSK@^a<!?i5}u8fiv;8ka`LXN?r8YSdbuq_zS%g
ztW$>oLOq;sa7t*fJvRon^8`RSKqj#@-He?;3^wGTFYJ83ITeP3!vUKDWfAasabpG>
zY#{XUEE@El0OYA17Eg~)cvz54raXt3@L0o?d!dHub9E-UpP`?aMIj^(YC4A-K;e`!
z$OKOyOMT*sNbsI=Oq`l6|L*J8&+q^A?JFX4j*bwl^XHHEZvlZVLu-_xX@L$3LpPf2
zC1_Aw9!xTW+ewd*|1`h21tq*%!YZ<`r%>$G*SQ+*he36vWwRDDq+{FHTeAUby84b>
zXzS)$f~S~%8SzLFVBF(D?D$qR=V^Cizn_|_xhW=wU%Nq)dr1y2zDdm?0GMd7yx_-_
z57W-PF;*G>i*EXFeOhuUJcB9u3K=?=py}{T-A`V>MkV2ocR$~M`Q`4-J!bXI_wQ)=
zckmhJ++F3!DQ3L~YBTJ|zk6WEm4=aa%@y<}RD$#GtAq7a&pX{TT_m(QbH{dfZA)wc
zh4jZLjEP;@xWB`r^~FzQ242GR(NbwTPl4m~>to4mDa_VX5pmGPmCdts*x<FHd@K3$
za^AuNyXqjm=XQ(&$slM*{ey~0&hW4iRyDEUN{vsoXe*+Uf)>CocABpEd7rM>TxXL7
zhmI+%mBBJkcn-8H9<*V~!4R6UpNIkb)zyqzn5Y2f!r62XK)E^!$~a4=ua7Vv>|>C5
zGh$tWx9_-%>8!Q4=0YyzIh<hn-ZAOE{PqXTb)XIF8fXs@iz_Wvc`o2E9QLphY^%4A
zxz?`E=SWVassf$5g~dt>(;7KV!$SUQ*CHh|U+Lgkg7sx^&RQ=FtGoEzf?|3vcJMUE
zKbijVi>W8Sgcu8M%yprnG>Y4Wdn<H;hy=yz!zLuVBsW#;TH{;bev(eV)S_8($;HdF
zxxal*KW&6H2(MHg#xrZBjQoxK)KLroRt2_I3<{|qir;#d?y)$>)*R(BRT<_QUl7Om
z?MwQV@j(SAaiEh{AYf6%$ug)RCd6|oFac;jki<g_Lqs>MFC}#IKuQw2J0#g%647(Y
z_EwH%Zj*)=G=?9q_rS#&xW7w8gfQ3raQ%cKi^bSTRU9Y#239F0oX^HB&8Rf{ra48L
z@p>9-nBy;nJ)s{x4XP6*tB^w~s_F^>Pl1%U%cLTwi6D2(^k67j&%Go&a!#hF?zn?N
zJE9afg+o|0L8G@^xT?C~^Ff-N;Rh8uHp@sO0ifNr7e#cDjgE|mgpDmy0WIcGvC!b^
z7q)G<o@+37o6*P?*DnMOTM4<fep87iJc42Sg+C9C)s`@G4Q8-P6;<p5mt!(mYv`@Z
z`Pm9PayfV7t$9O{u)yGCdL1OA(oz=<`jQa2kn-Q^1a+d!;H;E@dTC+qf!q7KNo|^K
zJp$?uPKJv0sD7rFfFw-InX7Rm=FWAT9k8CoBXPVyu2n3}!W2b(U_M)@Ek^Fc9{e|3
zZ<O35@dD)lA%l!k_pU&CE5&=Od73GA65@>4cU+UxFvK%Bl_rTMl(s}NCQLb@{H6|i
zxZ#T1QhWm`ZRlQ+(!ZJ@AsqSe_vSe(Ug?4Mwcr}7D=m8PYH*9(?{?dZ<lztv>V<TF
zE}x#T<YA;F2Qzzys?u5=S5F`(BzzsoqCs?G4O%P?52~bmvU8*=exQ_Bm{uI-XJ^9A
zss-np874rnVcLMbR8KUw1it%l7Rer{%}B(kcK8;}PyyAdXlJk*22wxmc9!JH(IohS
zzAkx1y|DKSTY$K-1t4`{>WCRKdKr1~L=r>W6)5_L94YQ(P#*U@EEzA3@OI#@<|Jou
z$UZMXF&}H0@1TNfpjyS6ZvIf|wR$_~Ry$cItEKyUI8jF#0ho|@97>DFR3WrLl?_m$
z=iAhamk7iDU(Tlqsy5UA7mt2C_#bU2<D#*bw`64beh9C@8$``^_^-MX|EXzRdpqdE
zoT!2)+uVZ5sV}vBaWAw*EUXw<Q9sy$#az))f#p*bweXbb_YPis{CfWx=^$_K{`vm;
zm&^Ab@6&!5Njn<ZqNE#@vk-6;=56fe+3v)SGvaP)(zvxtk-H1Ukv5(Wx+Z)*9W?$p
zB@*GXHz;g3NEx2w9L?npoGSQ<)p#1|vkX~Ez+y>@1yaj+7sLAkL%j@B*`klI-0`D+
zbq6-Zumsu04;Pt|wsKiv3`!+pw9aLNUM7_nFhL1jFcs7mgwDbVb}WCW;c(VP`VgrN
zGA@!&rMLQadc0;`quC97J(r1Z?+0rbc0!n>)K@EK4h0IWm2$Pq<6~2m!h|*;I%7jz
zFxrt_a!iBXsGT!ihsrtU4$7Ig_%I|K4DuZA+1Uc`niH~vJVSHBz|n5wE_+7Pp|;u0
zAX@B}C!_i4>(@NTjMJb8<P_(GyMo1~CPs3Wg)~#!4AskGeUY7)PGFv)_fmck#3=;V
zHP?ESIC!VY?k?{%`Kho-49o^8<+&Jfp*#0VQAYOGn0F^o&RRFhw_v(SSf{1#Ec4vZ
zxsk)pmI!Z<XEl>VMtp=P2DbyoFEYNkVC|~^xDwnBF8UW*9?TBY*Ba9_Igx$#xt&<)
zQjZMOg5T}+R@s?}8@du)2T9({j6i9cFdB=)L#ofsd_2Rl>yKe7S$5r!9e!cS(Uz2t
zkG6=*t9)U>J69mlGkuPQ&W}oq7+>J%b42TJi%&zxC)<x^LN7c@;#{apUZf3PH)~e1
zcuFCv(4=N;2nh_n7qn8#szUT&e5>Jtro}i0WQlM$F}og~7zK3X@c8Vw(h!Wchn<v8
zBOTK!c~)6b2`vr;v9fN+QRGbo-lS)y_&ME03g9Kp4x|Y{D14*|&>Sb{p`H~@Fg=^G
zd^*{#R+FD5sG`;&K^Lyu^cGW2^jWay0a9nMG4ddQeV})@_dsp>-OvaByTBZgW^=sL
z^0@)i_Cy#j>p*Dpvvzdjc96|{d;j(3{>|4<pFwr%20x97GmFs{11{(i8sgkdTIdN1
z?SVb<9Q?VQn`?h^ITi2~;)#I`*_K_(IEiak4_ltI^W_9l;}AGDRB@9M#0oi!>JgrG
z7oYd-9Cu+!BmL9wo?dL89P{6the&zI_HdR)^)uYYXe`aP8$J88a%G^uDd;op9fiu;
zD0|+OVHc^0v~(CWoJpGjDvh6D*A(8xG$O}?wm~~E$Odgrc6LEWM2YLtQ;TZv!CAQ8
z1f;kOWk8xMOY}n@kL}6*_pkPlqrMXnX-9P;a%LEuf>bDB+#pJcFiO*bT=V6H2C5UB
zq-VWUH2cne3+DV3m-lLmEC*Py<*ZO7(|ZKkYcqsVp2YG{gpn?BizV}qYhCaN($a8Y
z#6ZGZ`P-YXi;wTW&Od+p`R4uG`%jjLRd!T%L4DqXoqR)L-cpfKW8^fwkNU%mUw|)J
zdFIq)s(Y}jhHRVN)ef=u<5IJR0&Fzq<Ii}#rT~qzv(vV_-fF5WI}qHdm(slEOFhb7
zX8PQu!ETsRQXRRqxcUpn{3&>{{@g+aNpnvxA7I?_4lXXA_uKn_`F8*D>-)P8`_28E
z`}cpnC*GU?NZYaOq3K7m68I(X;0TV~e19qNQ|x*T_Yb_+6bLYRQ5BFhw=U<E#iIH<
zq!79KL=zIre?y<<m&~|8{*+-Lc{-!|qi+$VmMo5JnO$qWZ9!w*^jgEK9cCYC#$2zq
z0XKeZ8nD8z*Be*lI8);~`nb{{gK|__fy{4Ix&rL4PW<AijbCJ<6ZlV}0_hmuY{-0k
zMc*=b^BV7Enu4r*ePQQStw4BzM_4u#gbuSd<~cK=oZ7}So@sPC5W2>de~dYx<JDB|
z^hMV;4B!SFptF$`S9pvOfZ0+i7A9h$D&cbW8aY=;ajaJ2Nt-~X0@?P>9u?rUfS0p#
zmY5-C#@S+8ous)ew_AYhQIrZDn+k@J_Dvbip-a3Rs|-0QBi&G$fye6SH5qu?Mj6&~
z_T&>wRp43<%C99%gCVKLW@TFH>upQb8lY|nG>cl2&|M;$w?2*f`{?#$S+_&9nn0ty
zZWbaH5MCIK?4@D>vVoCez`sI>7S_(;vm?Y#K^prl&cW*`HBhp9qF=IzqK|iaj8voE
z@A3bOQ#Ztn2ra5OGO*L>%$mU&4TFG2AgMV`qwjW2zYuCeX$>_PRo8SMN3z@je@kxV
zhQl+THTIuDCNn)y`DP^NlaZ<R!xu$783S?4T2Du+_#|bV|AH2->=0QH`=OBwu^$>4
z5j#*O4nYdY+bN<9Z<q*+_?Rz^7;e0%iThj1coF{1@T=Kh-CgZ}{`B@f5H2`Pcb2ZY
z2rII54{vZI=Y=%bLJg7J{vWnT)HJlkO?C=5YnKi<L{(ZsH}lJ-=viE7&6A87dRn5E
zy}ZcKW}ZRfhd@)Di5d?XjyMjLlwazp;Ul@(i@~Dn)gan(lkFlC^T78uXzJcJL4?z#
zUQp6yKb__5L%#r0K$Q>yGUI2XhUm3&xv1$zu8h=;MX<|WyFoBXy?yq;pl*nzTdtq?
z5<UlMk-6uT8EU(GnLMwYWVbNg0Ez18=P!SL{}%hk{u;)H=D;}QxYG1Bu@{&ntHAkx
zTCxS1*5T2S3$I`W{`QJ3C9S4H64&F|I`Iu8^SN1{mG1CN8j8#6xa=M3rO6ax4c(C|
znBln8OC-LY-+vvy`3im#6tHd(>E*d4M^u=gNQ!yQG<8rmHKFiCSo#jRJUcf`^vyt$
z4GL-7(GJ)n`y&z=KS3kQE^wo_Gy;d<K|~M1gNz=62O&KKj})_q;E`(f5IoYD9)d?Y
z(?jqVzw-S*{0e;ds}nd3qLR#U$&ytvR|QnaWjYka{%$LRhfRVg8|BRd7y9kv7dbc%
zkb*Ngwa-u*4i7=RKMAyqDN(wULaTeSQ2ikkcB<;0ba9nwr{$@E6{6;kbZ>$=c>$a3
zSwA4bTjCFR;p#m(8@=%p#dUhu5=<$%9y@&eLQwk*C~9E3-|h4n*(j9T(v#+)p>pOF
zzFPjd7F}M%@MFh?PJ>Qw!&0ZAhCBe%8|FkORvgF(f$S9rBANr1>4s&=kIF4^r8kj>
zHlBF5GVKD`XEM;1`~>;w`xNs;m=Yw83JMdZC4xAPj3LQ-?|A3B*Rq4gS1`=*h6r;Z
znQJ;nQ0lS|Hh$1Gu<jXRUVaih$J7$-u$Ty~nq8VOn%ahH>~asD#o5&<iTuLO1krE5
zLq%U9HklX=KeSe|B#f!9;s6Wg=uj_xsWw?w;X_|v+6}r;-DF2TCrJzuYs!P9o;!cb
z_ArIgCLUlDH%$+^eO~h5Tbr}<tLwq!H@_L44u-?uo&0Wyh?~*q`1x=&c=Gd`U%vhR
z&8N?Z#Ch`bDX!n)`rR*oJ$>@!mnU!GtA&;ipYFasx%<=m-~Z+A^IJ50{mZwX|AfDH
zpWpoD_jjLv{_FGmCqMt@-7kYDe?A#JSsf3aeEItJ_kaHQO|N|N?%lVKIHW#(eDVdl
zSN#1lc=GP;-PgPF`s1f3is1`5u0MbM`W`*;>)V(6CvU#rJwc%7cf=Asd55UXH~)<0
zyFcIK>dn8s`S9syludZ^<jp6<gR;}V)#_kN+yT;+vu<b!A}fEJL!$u}i{pwc&pU%t
z^^|%}Yqi4T^FK<@nKfR}p8b)@X(+m!N;&3qd$)iSC9Gr(UU3T~kY3Hho0&T&lc_lp
z#)Y<wGs1WSHpP6i)efigtD~!{j1P9xD`ZQ2cl!N1;}#A5U{vI9ai5lmYXXODsjbSk
z&!2t)`Dg{p7v?|PX-3!38pB6O30p~X4*I%T>F~<e&8vy~?e6YYP+Dn^<Kvwmb-=!)
zRNpX>RCS~TZAck2QTuapNQQ4Z>A57cDosQ!B{Y&?Kv|(fp4i#MZ8?8b7x;u^#nV!y
zx2q(dz<Q`CV}!!@hL~rdZs0e2cC<MvSGFQY2dtY!c*0uQ>S`Kb9u`P6)urJ;l`e&!
z#NM+hjd1WPuWEZ&5IxPX16tk4)yR5|i-?s_JDjJi%;RELXrRkY_Dq|s#Q-y^P|siN
zNAGIyu8R0Bpjx~EKTKOA(ow%al4|^%jPTnI3YqEM#%RV2YEGUWIw<howpTTO)UijR
z?C^yYJ6DD@sWut3RJ&g(P3B$l3yd?VoXS4Ed-vu3>!)`|43_;ZxVW>~h6yYG^zHqJ
zukSzZ13s`01Mgucw0mf|E-DvdgNfV><%tuu<Uo}dSkbAT_^TB%j3Pnr;NvGd4H7#*
z>?(AD@+W_=NHLrpy720x1lNhTLnTF47OwDDI~;d^_ZQ};4hjYQ972xoE#MCJhnD4n
zGI<NhJbe;C<ZBLr#I6VnlJ169f=IW}s_<%<W-4eyC>PIGp)g@epemZj<0bZrq(>k<
zG$v+g<^nCRyM-@Xs9s1SkrI20dreo`+d3#c59{WF@vdbHm@^R8<I=RJJdG|xXa||I
zXylTP+yV%)D}v*hycwd&9&{Lgvg}>AYd|qW=bP7a-hw|5BzvxU>4R++c4jJMb-R*n
z>i~5NSJ|8&c#^@a=$tj?91;E&?fm)v-Tq&`A!O{``}@ydz<`1MI=;*<Lr}g==HrFu
z-%e(;<SLrrdZXqzYw<By_c6_F47iE82pz@tD)LGynzNGDpADY53D}J$F2$%P>2y?H
zxvHX(M_0zS*KGNEGl9dHG0V<<^mMTKmJc-8dF&+_lL`jg1{g4Pmlo?44jUwd8rF%1
zYmj=A<tgH<#v5e1sd@Om9=cVht;tUC3af9bVd@@JUAa*DU9N-e?V_72f@4Ww`*YO9
z8Ild@(IVc`S)ueI5Fx6ju!m8Qr1^#eo$|MbrqgBjbjjyDT1~gNbVh#v^$N1U{pUe6
zq^$5xx!q_Ll3ZNsA<mGNNtd357F8rU$S~0zHHxsg+@4vv7AOfts#OlDjZ&#@Vax~i
z-vmVlDk46}6W)P6GS+r`4W%)PI$=Jb>!8=2kM^L={v59z(`pZUip5W|Y$?gE(8Y3T
zn?Jp0OH^uTGM@}_o}la)LL@O<2KGSFF*$nkc<^TM_kTaQzKp<q%h%R&WugY|1|tPb
zXl5$kld9aO2w9KkiP{y~0Wm_~PDOmu_b!1+mflz}wr|CffHzQ#cDOzMW<c*oJ3J_>
z&rt-fx)K7kWXxsPOvIk+1eNUu^n-ck#3)A{brRkZDCD)ZC3+)(Q4A{`u~II+bGXvf
zDN$l4pnEA@yZtTQh*EI2k{(^$u7VQ<v2nf%ejX>6%TenhcY<Owbh#wyq6grQz;8PF
zYj(w##EAnRqQfC438)FsKtku|4)y6$^PbV4X?m)yQSPjkzkyYO9M2v%8G94MhLI`;
zt@QIASJ<md0#jpgfHuF}o;X`jLVk;c;yB$A_O-o+0dSCfhduPCH%cYJ^yR)qq1%I3
zq<f>oOF6Fn+le)udgBF2=)kl*KW<;K_~$Ekqm(bOW*S<0uK6e^S5k~3@fjE`FxPx9
zPc=UYZAlYQBiByI(LGNquA>9gEjp8N5Uv*6lPjtBsT9zaJ`@wmFI`SnNBAG9=n-0A
zKbV)tAfbY9+ee_Av?|Wm(=B%I)HPo&OV<z$CI_HwW?;`~X(m2n!}7Ecp5Qqa&0a}>
zHAv6O*eMw>`LY<ol&&n|j_{os(Wa!I<^faqhZc+51xBtPY@+FOBxhVO<aVXe8x6^c
zcq$=EDB#xX5(7BF6g9PB%=uK4-n8ijdWLJeJpw7N1lRh@2N0*LC2Ja}k}zZz6d*<x
zLk$s9@_!5>nS^ztuEEyg1QGM_V|PsSg=~PD{q}2<9Ow6R;ku2%eb{GEiy84EYj1}P
z5q&p7ByXwXXh3>IHDwZ|F?r31`}-K$RMPuowY^}7v*ym-d!0v)E6pw0Qunf*npac0
zs^HK<Y_FwgCR|s7+w-e3)J`GjpCM>I&ftMllY%Z>pHkD6L4B#$s>wC`rO8?k45emx
zH|OhouZ6zWL`$4FY`sY8LOYQ8r!|fCNrhfJ$A>w2(-7(o`Y2=OZ&sH(7KDQ1BmO<f
zk`iL{NekfMv%0+A;TU-Fr$ODYe{tqar3aIg%7;ueD19IIGmB=is3mqXi@HV3q6VMK
ziu_O^Z3n3D(uQ!i3}5<WLP*@XcG`(lL%0b#2ks9tMB(rX{oIK-q_RQFWwMu*{W{H+
z4@XF5eX5ce;*pT?o_@=6Ytc{3D%5SxC}7^&g^f2cLQ*_30IMYzWiE1Ml4Bt~;bQ2Q
z3|Zq!FN;0Pnda%=Bs{Vv^%Om4jzNUUfRpUxeeJ@v0&#{+r`u-4CB%?0qDtin+%MjT
z|Gt;D2Mr|&rB5rI3br_zla2zseau-XWFFEK*L@6mY5{ezzIisE$t+fgt=6g;60&)u
z&8d<7xJq-4H4i*^Rq+vAhzh77Ky{C7hO-Hx%cdZhL^mmGS4_%_9za&IV$HTT?LgCr
zT#UE@M=*nIuV#$k=Xp%6Xc?|i9>*=L)?ww!yppJ%Qks$?L6Hw-=tXYTNAWmPNDabr
z^$px_MAYo5Us4YyI%EN4tgVY{!7z_{104#eUZ*W!xg0=J>s?dB)IF`@Z0X4mY!RO+
z+fnRen1WfQrPM$1vl_4-Xw;AN#5ChH8Wy=pe@h=zWG%G#(p)RN=<+xxJAFL(Ls3v1
z4~4QtIj>J1|1TxH9zFSk%nGbopPtNEQ?qiMupr=pM5>)<M?UT6`Prg?|DDf{aSsoU
z8y^W^&x;}ZGFY2#=ctmnM6wq+$NH`yqt7Ydey4;xT|#zimcE7hT49Sl(*ac(y^3AY
z-@yni*KzlH^-^d-{lf9nW9ohjG{f<C5Cs9#D9TgiWW9}KDR_{VDxy(fzy0<n`e5pV
zp^r5u0r-U-auO&(HX=I-`cn)fn9s{<!zu)4aDis>9&FbA;PhlPv<HR$$+xY-*hGGu
zopa9<)!-4q7RJ|ADvjR-S=&vLK4*Lad(QF<Wi+A8`Z9u<{uv3pR5v6yiNJ%V?yvrM
zxm{i0e5&WSzmL8OIHBDh`G}a36`MwFIp(`*fPkhBH8USNj5Ks$9i%N6dUe5ZJzDIR
z$lnLry`ir!!{0%~@g=e3FpEq^300kIYk(SieAWeIX=u`?jKlR0_q+Of=+-`FZ<G&C
zsl{_q9Fy#d4bXz5e8X<y(jn=VzBym&tMLJ>#m(<1vQD#AuEV}T9E*~j(j26XhXs0r
zzM694(9Z1dkdP#oYB*=n;C?J=I%&S>^<5ST)t!{MKw?rb7+naWqAyNm>{TjAZ#FYT
z9zfpy`R&o0pXq&hq`$xay-h0!E4zhl$O>xNJy7=ij}kb2|3&4t0tyjM>_4N36$|W?
zkFU<W7%VJ^#k!ayYf4|ERwoc8zJ0rSHRx$mUr{m>se1`ofHZO1C+1X|rK?g@O)zz*
zcHpemcok^ZfdM5hFD;s`$w~C=<nnT3l*tRx{@|0N+8kmti%dF>3E_?1f^BRez=joc
z|LS^tISALgCET4x6*oZ3G*-p{dW5z<nwYpBtFIA3uu3xxJYmi{I+@M4-EfA({q%Hc
z#+hlB{=k(lwKr(_oF2&=Wdpwn*CW%3l<as8u<-2W%QX~5Xtj_-!z)OEYiPj78&ox-
z|3uQY*2ZL^Teq*TbZI@fD9$Wk{eQV)t63GiZen3#xPa7nxZ2{wcRf^Yk*qrPmbbT4
z>RQ{<haIqgGRTwFrhR~Z^>hH5bFw7SMH+Fpv?xP}mCOK#xO8(jd*&kysmGx&%;(VU
zv^bP*b!Md4O!yeMR6&kB$q)PS94TB}t2LfOk%h#s&~2g7DYut}uuYb9taaLsZdi2<
z*DM8+UyQLEm>tG`By!ZW3#SvJ;p|LE=|*ftD##I*nl4KbfER&4M}mjByK^{&Ac4ro
z?P@Y)gm2|o*g|^{`n(jVN~Qe+*$`Z7Pp%X$kI3+D`BVz7-56F75W?m3jiTS&g0mwf
z-__ybzbqss;9;3_pXUBPejwS3GMm)d3a5tCP0pi&pAgIj$<eYbqa2_-r#vtAb4LcZ
z%bpH&R>YN-O16i_X`>+V&^9zcM}BT8qN7oY|B{`NM8HIWH7Tny#&SbhVSwK0rGAZh
z<~4rv>mOBl1&w2tu<HuP>2(#e5sFKwA^{PGaP=-0<dL9FYHijHP&a4`r-&lsIn$+P
zQ$YoFrujl=Cy^k?teERjeYR%AbX9nzdo$&@-Dd`+uy&>V3EeF8?wOI2D_}vPc!tou
zE%HQWZ6GOCui+R2f<meu4>eS{A!`D&>K12IH+XV?{K#^4jIYL*NU6EFWQkM9o$25(
z?2)p*i<dJ;Qbw1xZH&2am5n7$JF-98gz?jDIZ*3Z3yhwNh$~oKBiFE%VKB{4>M{eq
z7F(y6&9YtP;$m=*a666)@=phSjl!B9mpSEvZQbZV^&Ww`AmkKg1C9sP+o0K5uaV7$
z6qW0`m`5R@xY8?vibo8Zd2uHqUN`Fw5>;#h1;ik#RTeW|Gav@naeielTE@i0K~}fw
zd73|qXgFa*;kQzOwA0v<^Zc0dOqH%oB&Dj#GPmIi%wQ7@de?fwV~2d#%E}ISgK<aJ
zE;TUou*l?u(-=yv0|u0CCk?V^JrQQeECkQw$B;<~(leY&TW#cqmw8T3uxhY}_Iju$
zSf)QRY+WG<Zx#=azkw(tC$>58`7xFEbOUh$o+^E+oZ#r;YM|DKHclKcv}Z=BDSvyY
zDY?}jS95#~{+-wPJDid4>7ox4*_?d1zx%wt|M(U;^cRqKJVdK$4!oPsf%(h8H@nJn
zYP!YNgV*tl(=D}#DQ_r^AwXug9O-0*Z>AYw@gYnxA*+h~$8nM0U>3*18eqzm%CdD@
zi66Zk^!c$l+rnh-uXWsHmFslVLo6y?>58Yf@Z7@a=L^&%TS7@)3lb#FFt5AR*TVEL
z(oq;sK_)lTpDLaLQC9933B5lmR9UXcft^HUQ=Td_KlS<}1V}IKnV_D!*>yeur?;Rt
z%m7n5E9c{(CN>Xt^_jG)Nw*8kG?Z#5qenXVi_!~i)uS%lpCmbfG6Ex%<ER5_ACw=|
zu?ogvq>s+^zynh<Se!3`dR5?1P;y*@nso@gHRrW)Vceb8;!1FmFFCJH&styp3Z&O-
zYni6O%2E^<R>O*kA(r8ofg*w|$KT?@H<XQ#(i8)HOn2dS9>371*nB&^-prQcH5{;3
zo1ZL3lU$d<p8Nsr8^pXRBeD0lCe%Q}EFiH^umVP!k;z7%7gu^+F&K|KPoj-0(0Yv?
z38pD37}o7URu+)d8Da=(P;4&{N?l_-pHu*KLy0aF>R9~8Q+`rgMWR5OH=aVYzztYU
zw8oH-NDKEExwH%g@i<jgo<SDbu4_-=-VPcGI5`MKNLV=8!H^D3qniuq>ZLbw=r5B~
zkW;PrCIIx5lz|KRxn?)W)0FCq_zgWBs)?9Vyxk)>nSXr#6zZq)3u*XeFWpb|zv_8_
zUM}~4`nRw5Z$5qd_%$98>f!^v^avr4ohOmRE3Sl2WZ5eh8}6;=ex%kwJ&)T89!j7#
zH<rBt7tBvF!pX0NO`FYGZ>LARuNQ85hnnz)vqamf5&MqkL0d%)7)PX(Rq|^Orl@Gq
z{n8&;E>YY9hPG``FZ-H)za@T00g>j{<csZxyT9I#-@g4kx%=?pPl$^%jV?0_?#pIl
z_|3VyKa@1VH0%5}6=Y!SP$c7maH-2YEAB1seui-+xNC%v;EPJi3I67-r?asXuRIf9
zZbJGHE@0{3X*Msf|Jwo+s$eUD{AO84cw?y}hCf(QnUuyYsahBFqu>4RcaKxx32Zbs
zW7x6Jx3HRud}If}6XI+5pmJd{NQ0ovDeKeCYD;!QGAL%wE^Qr>1-VytD4=>`Y}Ysp
zt!e>4@FY$NRcw#-vLyl1!$QbLy4&fLP7XmGEG2ITtedo#!k-O$l%Ak*V~{Xzx3-IJ
z*7l*{a&~*Jxue;V)qPwFHLq~D?9p$^($@Z}kreTC`JnZ^Z+qJl(wq*2XOVgPG?;CP
zbIaWv%4xW5qktg&w&Awjd{L>&?(40OV<+qts$IC{>Z7Uw>IR~Ncmr@yII?f&i;5vV
zMjb&vg6UTpHRbIvwF<DLdlzR_X||H&HK0ccd+>u+%<D^(AiTj~QR5_1xpYAM5WI(c
z9Vr20jaei`It6TwD54720vs?9Ot04{WGmG~(}GG6d;o5q&uHW?ZZ4b-SYegrB<h>Z
zsUW|tx&cJC=MHC`WdHONJ!^}Z!EMdb#72l@!AHe}{fu6&bA$<Cf!y6+Q(ThVdWK7g
z%MTPEd`Fe?NbIKs%v&PjHTw<r1yr}B6Mwzh!oJHAQh{xLcJ}qiZ!>?dQA`RyK9--^
zlxHX*4lW3KhpXB8YF4LOZh^uMVQE-Yd+AOF=3%(!p(izoD?L#A4W8TQJU{ubiNj@!
z`sq+-#at!D3-ZN024Ze%u-=>(f%kxPb)zAWpBqX8gXYl&C5DL@jqVEt+<=4Ad=2`8
zGkH1Q!G%<r%6E$!D-PrY0af%i_jgnP=u0}Sc^b_ZqQAg%f@xUf6shEeTKLTKE+zjD
zKYn|;@dVRTls9ht;m@D8_a7`OACVm6(bH$(9*|LPe0jb?@E&+rIphmsRLOlW2e$ao
zTY)9YpJ93mcu3b|P@NM@18~}UbBVNfI2!rKON=E+zPF2R_MCaImE+V>fgC*<9*;me
z1EnuW>E_!@6n@NAK+DEF=rSmY$CICD8gzpBd#@w8D#CV9p62y@zJBuJ`eIZ2ty%0P
z4m73kg!U|AFKH6?Kn|ZFXQ%@~6Ik!-*U04@2BqZuktZ^;(w_a)O#XpRdV#*t?I$kz
z#g*nKW;4>QqiPV7_?PtUK$rY@qdV9uXu<~K`7VLdeBKIOD31v#6v<+qHeb;I^>~{!
z`D^;d?OFiav?}hoK(%ujQ)&JbnhtkMasm}s8C^X7#|N%JkV25mY>_8ttzjCs9jiHo
zM8C4KfM=|pqbAK9jy)+*v@6rW6C?WQZBl&G+BTUCr!&)gr%Qd7@;}~g#!RZptj4J<
zibr|(@~8=>mvDKu->*<N0vZJDAxOK3Y#RL2Kk4u{h<`ha|0010(sk_bzI?g={FTwL
zr;LWx;lF3JHA1nKmVp(Zp1*tduBi4seg9Wvu@y2=waF!8PQ1;l$-2*1GsE<HM|hGg
zk4d!Uv_vU}P-SQixB=iR*APb%NG@s)4XP_mpzv8NN2~QNAsT=awFr6)g>PKzaY?jE
z)iTW~4Rflb>OhAu60Bi7#&dzb*$%x}p-$7PFCCM!04}V>mEM`vh@&Ds0*<}^bTZ%Q
ztIy;oK-+o)vE42CNJl+jqGtUEO$a)$XwK@Y!~LdhU6xY9LL`rYEF?x6L<VSTY3-CN
z{P5{A3-nmsYzFzKz8DJTt7|4ofCRU=GG{#KmSJ^shi{s_W&Ada8_nRdre$y_K*QqJ
z*CiRfLxi#{5Rjpi55iVYC8i6iSj89--;_NX+1^WoXxW~T+cLe69J}L6U+lPtQxnB?
zJ@qt>BXTXKrPBJ)&yz%8j%^5EUO9s9l>|(6X^lx9{ctVkSI;lPTvnCxLk&L7ks=pC
zg5Z{LY?@0a6LLXtSg==f>?Tn9EM!4G?l62tV7TrjIN=`)dY%2WL+wfWcF(q3$25Et
z9F(~nvh@6h-#)n>=r5Foj!DL@jQrS=ziH2L40*!mPR4MkrQk01Dy2@%S#av+9+N{A
zYLd1<vPck5y3T;(tL}O4I~nu}zkuG>N4HDuL}z9a2RcrfBC2fBn#GxZ0ZC)OULpKJ
zGj;s^ltl~DX*8t}xxPlxw7vZ_WR_~xlmSWrh6Csah+OqD`)(*ZXo%Vb)O9bGFU%vs
z6yGl-yE_N{W9<WqOAT8a!t#J^l?1GPCpS_B*DLpXvyV8YS9$NG-kCx&_>mk&{ywwq
z@D9+H9kSZg4OZQl+7QqALV|7aKfTk??WU2%I*|RMR@+6h=Ccm<(j(-whn;popTOqE
z8m8_dq86);^kCJMrdTZ|w7I{EUkJ+C0$O<l*RxIp*RzP=a`QrKcGA-!G~x(48!FvP
zr6G!xcE*&O5);IV!q}J@Cs5RCzq`0zo>dCFEDaU%VW{jR4V&|hM_yTi60t2+i$1V$
zP?8JJXvti~jHoaVrQxX!crypJLK66byCoaOEcA%cot!2ERFT2I0BR|W2C$%@Gq<(T
z%za1`v_cr<HG!ii3V5@&2OxtZo{&`LU>L~wZ#4iWpML)N8#%F0A7_6>f_iC=yB!2e
zo8GckmA1IlqA3b&OnI@OssfoG9B4PJ%E`l(P5@%F)ElHe7(8^GvHO`SaE+W@r{DSS
zaP;Er{_ZOYIF2r6_T%Bj&m?&Pu}Hzg;gmz$7)d`;wV8M3;2*3|j9uv-`u_~*Si><C
z@`5=!2fyWRd?3*9AQ|-5k07g~ic03pf=auaR6SD{`gpP>RAxX)ZU<pz=`$!}L~>~)
z4QEPsDx+Ow70NUnbf>6O5tR8u*OFgBb(8V*RK-lfOV7$rae}jS@<XqyMFH=a>q{nv
zBqRF-OUq(gXtx-GtA}oY7*JFaGezhq@9NA2u(DT<#dp$SHsF&!*<hYvd3vqn<Uu_i
zgw3Qk*G(c>p(QYa8CP0ePGU(%T3M<K*JC-wtZi}k`Rx`v^xGFYsJy*@XU3ftFui|Q
z+O&8knd8PYKbI;uj%UVw&}IxNd$t6YpBncOMh(NG3Z6f9Xeyvq(lOc{Fm;ET20<ee
zMFGa9r0t-qwXYlnb!66_d5LF^VlhJK@f=R$axj35QPJV!xh3B!!X2;t6XP36Au6zj
z?9bgm1qPR&%O5I+y93lM;;NC&oP5gW{CXZ{=VT*y9cS-hmtcC7Buhw{aE7~dEemr<
zNsg{z>aHpGLJ7S-d<mAi@1{F!tKIodsG6<}Rg=?6B?2Bx1RNX?5DlvP4Qr%hCv6J9
zJ=INFTZ{UUYg%ts=SYXPzeUiOr;To#O`!9n*Pa(4uJjy8YP6*wZTR&iQi*SvX5D^C
zU@NXb%-ItagRfF6Bu^LHQj@4YJEG9fdUcCaD;~(sS+^JtOS{*|@XZ*_7m{B>;}Iua
zr<+zG?JZD(+0uykiHNx8f9&g^I};J7F~t%*L`>L!G9N^dAj0$7(ALK1{-{0KakXnf
zF190u4%i56I<I+42>^n|2Bj_n5(hRlO(+f8iRI?50qx7+grak=K-uqilYzP+=K5m2
zBgcbmU$0*wQaf`Sb-VCJ+r|=B7B)v6M6YmuTvn1;(X1CXatoY@`OHFo?dgy|&5wrm
z5GW53=`O%^nBD?u;edvjg^Ta4Ey48&`un8ON9kaYw-~xBp*i#ts#_#8Dvr?06$dYn
z49{L$uJ=Glurvp(`*20|RXu1<K?13B#V{in6^-Bn6nlobK^XL!`2;Y$n|M?hfH-#*
zT+ibP#J6BR;g}<jQ?gF}AJ}8=d<NajZh^*no3b>}KnSmA-UkVzSB5IVdRLqjmv)SJ
zVym3s$JC7+4Yo33>~=mXIJSV7lt3XZg?eBI!4k7TxgiN`lUs=%H`G{JIg7G|bCDP>
zL~bwF&LjFU68x5f@@TDQN3MzJH9Sxg5mSO<+4CqpU0j2Bh+1VUe20Sc!b@f)c$F7j
zmbCW8ad|NF_nc%)OJ0RLWnKb2ealNklZf7e(9ridTLZDPi<qfKt&gG9)R~gPvoL7(
zowJBQeJ~mLS(gnv&_%1kHJAGc!@P~XCyqV^BVZ9S3KYGVUo97O3nQW`o;ElvPK#yB
zv&F!C{I|us!FTCzh<CHQ9*TF<eld(28O!Pyno#n{nh_d?MtcQlgD>K&guLhC2IJ)(
z5=RIZUy&;WB*rPI2j{;8Yf*f`kiiP4gI_S8)rp~U7M@rUTwjx$HfZyR4^Z-(>w&rQ
z>bJg6dn6~tHRt1etv(zT9|^(*i}R%z22KF}16t?_N;pP_V!d)ts}ze0l%P$3oW4E1
zXwc(}1%TeCx)R)W9Z#0IN3=)w`9TIDY@6URi(d3{4`3ssae~NqiIYi1nJ40Te&|3g
zJESGa8aB*NsZURblWUVkz4BiMrYFkZY<tU(<{TF%V?flkJ!8$$GO-<TJZJw)<7Um+
zG)kscNvk?I&Do85x*5D){jlTt<4SwX+y)Vn)s?S|tDlOV(-cU6+on=B+57D{cJFAv
z&{O=mVDcdy6glMMg&lzI;@aU27&HCcsw*EG`0>dE7UKnS=M=8z5oI<q>X|NeR~%6m
z7TjN|C}3I)A3TF5=)`sQ;nSOc9)I`{V{hB_673j@z+%HM7JrOF@MTl(X*n^0n|R^i
zhzXv^WL#~*ahm=cy2rCiWYFnt4g(?r>nAT^@scb@$wilXi?*ECaEKk4F4e;~iq(4Z
zczzyWjw@8n*hdu-n8N_l-RblLMYY{hpLGX1X_9@LqYC?M#v(C`<?~)jo8oZTqbxJD
zMQ{Zo<Q7+kipGHVp0)wfdvzR|Q-WAyn|)<TT|+xm=T5c65rw0yQzw2{2WI2&VlMqY
zD;b!_vV{OW-%i}X7FSxL<X5`h&aS7c{mo(v#J@yY$fKLb1B-1ZuQ+w_sbwa`Yu6q0
zUhx~Alz-%VCSB^ynk82zu%Qr0Dv%!Mm?Vk{d~GvwSyPE~L3`1&d3gCKd=xwA6^1Pr
z8?^0FrD{SSa-<2anrFMo>YC1jj<-lx3*Fjo$IWQW;IaGq8eUiM;w>Bl-cve*CeFuo
zy<v#yPn`VB`9RW<oOf%E0GxUzyKs#{TQ~FenV~SnO$Y2lSJ}_ka$$l4V0bZ|93#lt
zY#Oui*+SM*eju>M8OiBSwyQ@;!DLcpulyAty_0;@_WN>(m|^_mo*8ke^|tll`)K4w
z3WnCTJ~P*8N)=lYcp!e;ZjMQ1BufzZVNLG~&oP(lhY<yB1Gio2mS*tKEbS2%S+c_<
zq>7JbvN8&(AjndtxGtp+uBjkiLMxA(B20v{nPpv=M7QwI?WisKdgy`LqVbs{r@QnW
z;r821FF-VC#<7s~;#$+r(O_{Do61pD!KrMZR|4xDK@^P2oz%d;8Zbs!R?RL9Sads|
zVZne+h?@KBrw_37e7GMR{oTL5yZ<{P8S$Ab+zp#(AVw+8F6UN3ztHeCDR>a36THh9
zYf$f-E?iS4!ekB`k&q{@3S{JgI+S<D?zK+WxKI)W*`~IizI}dk&&su$IBA64{~vAm
zP>M$7xdhXpsWUM*gt>0B?h+p@7f1I7Gy4LalOSbl{N`G3EiKVaFx!2Wu4Tuf2nvVB
zbm>A5YZ=N3nEhrNd%NVBga9kMX&d>kVP>FVt7+e8O`GM~@~$G_;u9MkXgB0|H25MV
zBmHvYbCJddvl=}wFV42gUMEwJGtr0o=mh~}l0<r+%+|olY35(xlfu*u9fIU5Ncz*?
zL5vz>zjm)@A$V}F7tUr-wJ;5PIGe%W>>Wxo{KRycN^?Snil2<YzM_B>RC8UsUAEn2
zu)Z&`28w9Cncr@)F3eENkz)(v!|ITg;j#JTj4fn^B*IHDoSG9~x)S~*g2o!~rGI7x
z&`_LKTX8mhWiJzn8N)$=JD_zV!wWJpMego?=BfoHb8$xrF7kXFR+zNxUMn-H)HPC~
zE*<#BXPZ}8qYhh>Vd`#DaN);o?<)1`y<Xngd#JG2TiuSg_isLYWf@{t>^OdYS!QEO
zyO<f6>?kV)=k_?RKpJj*yV=ht)9lah8?mQ@Zls_8{QAnAvk@Q&4|I4x0EDdjMwMKd
zbwKJhBOQQx+J3)>|HA&u`~Q8v|GNK6Dx^+g(td<!iCIk*D*pe|_NLu!WLLJJehQvH
zcu{tyn*d3PDtEaSh=GI!5)c4VQhvdbB|4LBS<2R6XFXT-Z|}YLIp<ChWTxv?<yt8s
z?zs_h;|^yYOs)VTL)r=0tYV2mmBO8tfqI*$6|=}+hG&BE-0Q){_ZK0i+No}t2m1~=
zGa@&r*&tMEp|jP7{s^Tb#?xnR{&ha0bl<Ozl5g;!)N{kx5p@$+>4?!uV+aopB<&Hc
zDX!JWqSn2z?Rury7?_igdYf|7U}Vc<PQ|^lPk=O8niWqE6KqfNpN9H-y|G1vb0oPT
zOU#Z6ObCC4K(0@N>x4bU79BMJ>r0JVd(*V7;4ob6N`-6zh;}q5ITM+^$xGU~bnlvw
zK@FzQ5dCLRDZNqjmwdnZo^_fvAd(=242I;6rwk7G;pAZ5<&dmkOX@mcy*@Lw;3c32
zvxM<I9wCt*dSEUgcFClG$Bj!!D$)*@X^ssALLMol1n3jiS}fWO+ibQU$<K1JWgNwJ
z@L(Tx5mRHHK$FQ4v<v)lYWT<ok&10zU4e{=5z3b~XC%>Ll(5JLBGFtv*!*DSn0+m>
zZDGlvN!*mqvq{22n35#0QC+F62d=r5uI2@NBDO%#l`l#KQD5757F2(axSfEy;TmQ|
zvS;gws%c{uu{(igmMqbLDoc&>7ZW}l^)hx@XE7X^!q!zQp{(`GL*Wz}I4t9bZ3O>K
z|Inw&(bzQuy_UQL(^tr7V-aSNXO#<D?MicrNK)%Rt*<xzspqG2Wh!<INc;op`Uh`%
zNL#P)Okf@|V>af33&Sc@Ae(QvY8+An142>Z>BF(Brpn@JhxZ1TS^*L+wEAd%MP!)x
z99EVscrr8sAChAUH~Ax&?`KdzLOn~vBmMiWLFa}QNFeD}B}nKgz+l8qZ4v^+3c=^_
zXhfx^JjBVzK@3A&Kjgf?hvWtEUv}Rxum(*8msJh;wcg&0!p2!|4`x$(2xn0_!$3$8
zOJ953)1WM8>an$FXUG6~`}yto?c3YWpJTK&@89jFQQMxSofJ9$ECZnVAw;IyT9T|f
zIw%|$m<ZR99cV)GQmnrmD8vrNJ@!598R;7;Um@3z@?O_K5btDzPBH|<%Cunr(#2*v
zu6K9QqSba+VlaQKcP6E7-K6a$T5$$4X@!%tIefAkkX|f`>*34V%GO|&pTxzOb@v5m
z0cxO)()tz7t=k0b*=ySw$P(JY)f1V?Vm5*1eD<>S#IHblQfx7tPspw~=sc);78i~>
z3Q8%a)H7?91rfq=nSSV#*+Kk}hfcnLgANb1JLI(OQ3<|nj|%W@dsKdJ+oR%p+kRTu
zfXVfa!rRDMFXQd?@u-1hDlTc0`7<qmpK~y!kbyhBG=IiU!P9d!ZR6W2kUE2z!4fO;
zy5%so<m*My!c%#dimXPkaKF<`0o9|$kjcY|9#pa?E4PBHTYJE|E##3XWMH1X?(dd3
zXb+t5IgBfvg?K=i$8fDQw0OF^b`-mP8(#HJoR2{=2~OD1NKaW1s1NLfmaopHOU3-d
zXX#}sEgM7Y*e{E&VPR8tuJt|H0s^QRLvaPTDWkgE0ybOd*^q;OFnkI}Y{b|yLEH1&
zf2U*Te);jk_xKI(P6zCt&t5AYVY#|G$8UQzBB2q}g2?Dr!zO;Yfa>Msh9w_arFlz%
z0edlWn|nMeU4@O|TP>#z|JHDP>R{gln#c5&E-1#{qH;vbXq4AVg&^k%oNmrnS7S><
zZeeOM*JXB{WI8PywP{=ya0}!-ta@>+J|w=>10$2qJ;{X(;)@cl65<D*1a<ZOL=|^3
z8&FA75Lf9;>@Lw)BsVC%#N{Rh`Aeldt9;nGQR4-NPi-(gAd%}Hj3u2Jj9HMlwwdk@
zVP(2pNLou*y0<tYn^uIZVftENWo`tRHJKoad0)k`^hUO+V@?g*32RGmC+3Au<a~3<
z$Y5;&38M{LHfXN(DcWOD$%vIK9k~pbcEI|eDnn5=wvhgrwH(~kc8hZYe?SBnCT`50
z>5Ny=K@SbiaD+MllcdK;dKhCH9jF_`)r0u~F28{#cd<2BEc}QD$r70q@CMQgO+>fZ
zwgotqxyKi`ODi;=U>bv(Ou-S^W8*46&JC2kf=Yr_6MG1!G(^<wj9~$2z-T`(!{aN+
zpJg@Vg6;1D9r1GADT>4?>y^9vcvzQT%1{iZZ-<S2zkl=P%cr|Pef@H~-$U#3`Su-l
zq8ZKRGb9XW-MR6O&N@)QoSFi}6f1}W;0GNXQC|{xD98~LeNC_0Y|Qud(wr3sZVNZy
z^76Ep0H~(_i%H>lXUWH6!|g6-uBTK~A}6?TWKW?*M<IE%a1ET<Lm<A;XZjob70#QT
z<HVz=3$J57S;ogixEyu6c@nCj+=iw{rCFd=&D1ar!6*z66PVc9<%KBB5p5`;9PaC&
zJ25FzhAfbBhxuWfYi)kws_jo}s<2b;G|6L0B&&MpxjImOD4?N08`zSRUBktC_nwI>
zz3j^mcdUD~WGr#7RNO#J&j1{Sg@dLpgjRCV=Hm%|oW3O-KvFp*O6&34`C4Nj4J1BV
zT%k;rq>*%$vB4q41|~5xEnr*;ZrGMerO8?ZzGMkIz%*Z|s030)YGyXF;yS<99j#!~
z&=jZ3+#_ba7wu)BUMojkyz^{rxwZ6Dj{?61t{LGmt=$?pBZ&SzJq$~@;=Hf}h;AhX
zcctR0K^mF_AkedGM0yp!HMjyfz$MV>l9QMkrbo#@MY~jMo1%S+|Di0f@t2oKp5n~q
z$&olkd?U?w%%+(l<ji3bte=*^^ICYqS9#*Oil7d$gOVdh*c~c~A+RveDvV}jiDG+d
zY)RKLr_0Vd7l~$_BJY@kX$J+3Qa}z4=)uPc#<uR-#yqRync2oPc~%F=eHZ=0_e88b
z7NoLYRn82QX)E`T5OR<3BLqbAuz>|sa~M~8jqCiOSzXLuUoa{~xK#zY5WD*g5H8t6
zcgCg99!#fS27i0={`cmei(gjtYKdU=R~Jl_1?_F>_?yRwR0M{840iPYJBY{P@;{L6
z)1UqO!G8|^{)3GCxEmkD=is^D-1n@<18}gwI_buPNJ{USt&_II_o==+!L&~``<W0N
z8`h%hVm@>1W5uDI{O74R^G>0{aeI$$A(Ne~4Ws+(h&o8)2~;&i9!?}ih0|oG#TJaX
zT6>NqbXuxU^>qnNr@Qhvn2dDFE02ST8F^@%qz8A_&=>>C8O$&}miv<kbU$NU6ytN(
zpFV#7>CImi?FSKVdx19gunqw(z3Xlmfiqn$Q1;sMD@gQv`5YOpJ<4HtNYRY%pJ8ms
z#W&YBjtfmnHZuT)bd(z{RHJuAKRhyD44XK@8l>KNPf+1wOi^b~m=?3x6Ry_OE!q>B
z#l;BJuH(K?f%ML1hbEc9{SrFhVxatj-R2dHPUjaeQO~wyQwF`Q#{S4E2l^_0$1gOq
zTE@My91r&&m?9R%Ey(LYiNicOU3f7JB0?}ZrgHzq)5SY9TgaF$yPJiQ?l0cF|MUDS
z9As0ws_c+LQYi}G2N;_+uOP>Qgz%3YX>uo=+_|g8`gV4PY4nv71*)UKL<P3$Or8zM
zSmPK1ejY0I+&Chs8P)gvd+pt(Pr^p4>8Hk(V8zT4@J}T#jLe2ru0e#U5$_U>7TFGA
zl`EY@hWb9R4hwxBxY$RPrJe`)hN(!>26PVnzFztaoWn4ADm8&qPU2U6v=gDyz%9N6
z%q5KSU@qs9IGGH^ueBYu=~t1!!ebWlwfgY+XWJ2sm@nF(Bna)mVo(_o%kx?DdnLmj
zs8ra*t|-~6!{op9R=FdL4hO$QnsPG(k4LD{hujYJk~ct27Dt?OFL-}H<~2;+#i6-H
ze}qIX&9#Q(T+!wHY=r?|dQw8HN^Vg<JHKb+tLG4o5RgM0@y97lO-<&IE97HQVqO?u
zBB;A<V?4JJEybH7%L-)Lt11?`2dqyL-r<z{CS-uf>DO|?U92H3;P<N7D{^A$<KseK
zL^eA|z((a}_$@7GMJ+#^Vt1cgpgbn9@n&`dtn6>e*<5=pIfI%Q^z;xWia@H#a|X85
zn}C?AhHDnIyK^1ql)aHkYFB}=7{VM1S(F<IRc7h!LEK#OJPDTenTR-o0{hTlhN(Lb
zqyj6?reG$UPiTO;!B&@wG0#NcU+oB^1J+G`AV{b7_$MRnnhe7^fci$GIyFd-fgWYf
zny0;vp)DxsP$EMh5{X`ovoaTnYp4QNt2UKv3m#5N-wzgmYL=80SDPMrQY@OBIb4mc
z%h!55v{Xpr+CTONVp@$l#xPabC|QHHiv}ax9qI+)fG|a7tPdB+)6EmT0e6>DG-q3=
z4()nMIsHeq$3+cNZ&Pys)33I!^3ZR6xNQk~Dzbo4VtMUSJwz=$LB^3dzj<5<t{0*j
zAB;|y>$=oO1JYo&6EO61Fp}3-Q&ymqPZvFb{M7Wpb)z9l+_+t>W8VCp3Z%}QK`Yt-
z`sI`CYg2*LSzqY+E1e!n6`j%gVlqm_Zj~{wBH+2)v~qgMPQqs*O#(PgBu%g*Wugrp
zT5+#6GOIwejEW{dKR!*etX#K&7tm0&hV(wU*uYGPf8b%1_Lixy?BF_CD*M@lF<cpw
zd&7KBrjw2<t#W8H!-fYx+alF3oNt+DijC?mJnGhH=Ml^rw;3L$qmPt5>m`y#UZ0V<
zu?-)Q8}YiPPhKvMSxF&jvcHN!lJpNnIbup+3V|1V)}0qk8fLve#ZfS)jPGR3pRr0Q
znXkVsUw5V^B|L`Zs-B+;qWh{nG!hed+*ce+JS+DCJvuz^_zcmK$iC-|{9R1z<O14D
zBx8nMrNkn6PKyqjQQs6RsD9?1qLB?yH&B11N;Caly<MOeJe#62DHoecN@vfb-dPW*
zl~Z4DWrLEWYCFu_8(iZmWt2)NZEwG<Kiz%&bob@oalG0lm{F1FiPcYt3UD6j){kG4
zi>Hch5vXprec=ADuBm|YUN!~rSaepn;00ptyZ!Q(HVlM<5(Pejq|0r%->;uv?9L8Q
zSYY@K{u%KfxG@}nzb?Z51&3;fGRNUhJoaSckV=Zmp0?u%9shum?Rt{k!QQ-!cR)x1
zrlxXDUNmrgdIhf~;gkYXw{U$;`q)IpAusgMcC_m2#CsN1h2RI~xXa(v(?KsXy}}R%
z3DEuyKOoP?1hgAem0b}h;8M5a8*?TFF2#3Ri$+uv(aN|`gYxPnq|od8TtIaTbp9~V
zcT}{?z~jKZsGx~L>Ysl^C9vCf?Sz0$!<Oyz(z8i25a2AEGe(QQMt^9K&`f#=V5gc#
z1JuKKFvxEqL7r<dlDJ>WcI;*a?dKR8q&uC@Bo}t_9BP)+K4HMb6!m(lOm!Wo##6Ac
zFox$?7bor=ux@e|Ml_<;pw}>U&%7q`R^!_*<T;zz%iO51&;wYd0@;6rZh49hPlmGs
zJtRxv3hp0x2e=*Tsd>U~Sng+cwuHB+AmNH%<`{FkBh!~JfS-Z&3r@9kWa))JqO=}~
zlbD^A`kH$ZC<Ul2sVbw+(dc=dvhWajMYPBWyI~?DB_E+``Z1JKa7#!!AH}MdY!%!<
znQYNiA{fVW1uObGC~B(N?G>n5p-9GEc}?U-t&nX_o^X9i8RgP|^l(2v3SN~%q^%f?
z*;HC|oIdgCJ*_y}a0P{aj)}{Ge*3y?ug`#HW1q(!S!`D@Lu7o}wC6o%qGcEr;!1F*
z*}FCPD*Q8OuGNQBkfQobrQPT6-+caI{qgU&pQa!G{y_?40HHqa0~<N?GH1OiwFJ|Q
z^7Ywkb&JwsGYzR})3C(w(k&MT98{~Qox@w8p59f1X_)~-;^>?~AC$oLA>{_h2qU1?
z9tdO36a0`qjF}_KMva-f$dmOkyr3mt9k9K^?XEAccQ0F?u&~J*Ox<w^9?BW{geJCS
z-c2D_d**$SFb`;o4cBzhTR@lA4B;&!<~pw0_jT#9_jiilKG`2Wf^ra=Tl#`A3Li4y
zY#OQ*b5yCkEv%@|14xe?Tnnx>tRbM)+;z0tiD49kW#eg0$s&sZinZ8#5=hi5MH3vy
zQ|1uYCOaD!SGG^abWDb(_zF3+JPa(ZfLdVNgCFLe8cd-)554g>h+-6DvBLKSk6FWf
zIiadA^<$m2?1d+slnP(8j)Sp>iVk|AQG{#a9h&yiNhtLq+2$vzVCLHGc7ihxf{s{a
z9kjARlgD(u(w>;+#Hmu7NS8vkr4PWin9i2t*Rv^T-_A>tc+1%e7-=@UdHQUSIwMA8
zyoYWATk_}b@~ku{l&eJHaD{Z4#@SYA07gd>n9T|cO}DcqEbz|}?Q}>-=o%QN3$+G)
zd%}Ajt5CDYEmRK%ld!$SNmd154_k;BaLSDpkS;wIAwGLVZ4t`sNrhPWGi04BxbE(j
z%7$4WNVz&!Msc;spUa(+;=A!0<Ks$6wFA@_ZFiSPqxtbqKglJ7C*)!f{4$*nrYPkd
z6XOa`r+Wd_W7<7*GVEkyMh$xn0ZKx6r=tF8JU3PpS_MQG1yGNrTrk15r?qBe#)-Jn
z62^%+#}D$mtfn>2>5c1V-9Z99z5D#;Pw#IbP;cMg-u`&`@!hRxvrE`LV4)5s!r#40
zE?q80amoUsG21+=TJ627P(pPRwGi0&)H#eC_fb8*fjEP=PG)dvEPm@t_~N7tlX#o1
z1UF#;)3ur^Q`+F5b_1X(v2q~HyA4)<lH<bW>n#`~>sW^eh7p!tUL`>KIw8?Q7VQ_3
z>JD}zFbX`gF*8WPiWac=oEEws;uId=6aQ@KG72pUP_H?SLKBE6e|wT~p24uC7#i20
zL}-ks=0s%vIny`1`}hw#vt;t_yT|(e9_;D8Pp=;fj}Li@D7dh}_64>O{jz-UNAA%d
zS6XqREXzxRvw-0#*IiPF4<p9ro^G1(InJOAU~mE?Yqz&L#ixS=K(%vv2$n!Q*RVoH
z!K4D;`VjyM=}14rC$01|b@|5aJGM^YC*iz7DsD-^Q(T3~-^K1}jX>@8(+SJi2$wk_
zZbAA3TV=RSk?<6z09qt?N-{rAx6)CS%!=RPU*<`Gi?C{LBuY`sEfP!Kcsf1Ex|47Y
zJA~>Kr3bmf#o)9T0;J~`3^7ylB`(47R0ph^xEJXEOtmf$OlUP|DYVZo>(}@QVjp!o
z=#krh|Gc|<`xl(F4Qx$U%*3UIjPG$fM>{@!P=e`6Bs4hvK+9laR3MV;gzAvCF^0?>
z;eA-7j(YFQyANMKk2=hzJ*e%Zmyj}VL6{MeQqOP!P{(qB9sblZu!JjTT<KIo&B!HA
zPLLgLu@4Lsr<6oZxXQCfUw*nk5xd(@k7!xfk)k33$?T1R!$>I{<8}=HL3yJWo_N$s
zr3!K98hj$3EgB+Kj;Z&69*89bQaV`M6zO!pL8mt@e%(RyOF#F;2K*vC<;K(3_C6Z4
zK^mtQ8{!1~oQ&|>-bWXhgqHBY0wqCyPmnIc8a}Bd8S@pvG0&DJ5ex{oQBD9337f_G
zBFB3%M#Mxzqbx%>=P(%DhL+?OFZ7p8nFZ4Td?qc9atVm0!JWklZk<M<pH%+j?GJB0
z)q{3H3p?=wYU!sOjvv`7HCN>$Yl~CCHT8v%<7$5rM`wqq^(?ATJ%hQRV=H{Ht6mYD
zTB<~Wz?bDRTXULrog59<YQ`BEak>KTDRH<YEEMd)=UjFxGFhtzkXdb@3}6-bk>xYl
z@!|r%WBhhbs1;4j)TH~J=?)Bpu+58>IjmvTMDT=h!BIZ+Ii1>S<P+1?_R7m;$pxT-
z(BhG4u;c>MujWd^yakZpC&PJVuYv#vt9JtFc?D*x9PK%;o*cwSSCrAqSwl?L1Qjvm
z9<mvBd=;I{lpXZuhS%A^H^lQ?6!I+ETy!_`P;j%l-?P1KmZP{i=YK<!-D_^L$k(Tj
zjVnjcWYaW6=G1v$SNu$jbHs*h;CN>SQ`{iEmRTk7vsq@nwA)E@116WK1^#lD$3oS9
z2R&`}fzDY#byDvneQyTl1^1ePZET48Cs^(t#+HnGV~<9C8yQCjy{$gaN*hBNt(fEv
zIgAHfp!Qo|R~`2pO@R>>VHxgl;EC(vO0RDipq5GOfc5Dau>n_qM*}Twm?sb8z@Dyp
zSVlqdjffq+R|M0}sYEc_OA2;2Axy?Z73sNLA<$&CLH#&eey20N9XeydHY;@x9b}l4
z4;dLolL=xG+|TVy-$s-mU?7cDPQ|sBfkTq3%Hrxq!H=B**HDf2`GzsLaFZTezGhy$
z+@P!l6&<vD+b*(`5IeOaWol~|P+MX6Xu#T_NFTZY!rgE1o5$v?LGquqzvq~A`cHw4
zgx)%quxiy83Mr)w?vBqqgS({|EA`!6)Q%FIjd~VT$5F9w0S`GW@@pA(K!C{2D)In4
z^7gq@|D9G-9=q?|=HdkT7z1T`Q5D$2kBo0n#%hl?>MHZ8mvNw`t$hr*CyD2j9MaT)
zzOfDjj4k8mGnnFP%ye(J@&$)9S?o^^FaEb%!>qPfGKD#28@gDSE;V~u>~~$AjgjGo
z+zW_~f-4bqOO`*jxYq5ogzwDrT7NR?Lp;ZNQRX=HGvgvZ&q05O%%WMS_u{*e<;bkV
z>{2K=;hK(^EZP@-kxxXYpB|$lV7aD8;o%_@HY6lqz=%^iRz<HAtu$nqIvGr;IL$4r
zuznsOH1!(AIN=K6zmPzp(@Q#C*zD*t@lZFAVwq8YL04K^e?hnD>KY=bI>R{p?yrA+
zJDe~nbt<+!*uJ~_SU06DZ0X=u6R$Q%?-Z;(tSs=cma~C99cS{i$O?s-gntybkEMmu
zwYC(gj9lo}XNXF3A2!PuMzz8gLe2s~l+8&IBb;DbNU|*M>qP4_bo{gR5|S9D*7eyl
zxg=HqG)BI>GnmC&@!J)U2FhC{Vw{a_iYt8z+?D9wR;byE-QR+gEG$KU;`vZzU@n9I
zq56Rqr^9e715Z@6*=a1@`^~cpqSKu2{U=HIQT#d#2MEG)VZr@&8Db0cV-&(OTe&qU
zt^^N`z0xO~c)m9-zlQ9*E|DPWKJdmuHPhE4&#2k1MwRXU{MD=d6=FS<LwkT777Qu2
zkTIlvG#L|Aum_;XoH5>!f^y(fD&3L4OmWtGCPotf)#1Eq0EVF@DR{Lmmb<5i>H6qO
zW8o@L)jT5SdXgpTVJlH%5hYPey8zArs2A*v`4Xkew1!L<Y?+9(nTXPPwl3{hq2lQI
z(rdvIa{+a^ixJ!qUp(z~?lp)ODv<33w8e|>_OFnGAAfw6pPDll-4Ocw=@BNo76l{C
zi>1t=jlEhIjKpLL3BUP#3r9Yf?4ki|h#H)FC<W>S)Y$C!&g+?QpJBG;axuplr|bp{
z+QsvzVgyAIUs1?|{*7+wX@K@b5KdRcI+txuHF5#c=^$E42~-&jzkDtRM@nf_b3l`h
zA!FT8OGl{1e^<*petCT<AP3G1LB)6w-9g~TzbBZ3rfGw=guqEJDP}{5<+>Sa4JFxH
z@mZz|ZN1z&V12m+?QrutwxF_fsj&eizKH4yhx$fZhPKP`bITo)uF`i#F`HfoDvy5_
zop$}PTfR%{H6{n?(%|-fc4pI@ubr{0?ViL`zP_<ZlUY>X$yEn2;$tj_b6jZDM%e+~
zUY*tFsDk9Z;w;%Q?=G;UIFSTXcf)%;sH_Mpb02>g6T6&12*5vxHbZ9^f{2W@@&WOj
zH?$WJ1)B{7-Y(D^E^baO3=C>@A_Jm|3(Anp#uJk%eIltaRZgkgxsSRuQdV${+^GiY
zIAGSs6a3A*qCV6U6pWnYq|3Y!j4AW6P=9ELk4YBcC*Mq74YMK8*TQq2AKK=OE4@Th
zRYc(&SIDCa)k85)K#NLyb>yg9P11|1M)wK)U&1l5E^O(`M0;JNQJ8F^NEW_|c|n{Y
zZx)9ZJgSwI;gfcWBxHg)p|VZeyVI(t(0dPvX}X*o;D0is`tyJP>wrd2eO>aKbYf0P
zr3O@4llmopba_zyS&IJAx7;D9_D-E-svQ&8`iMA=Ba&QZ;DL7U@TX43WC!Z8@PI=_
z@EO#HrUa?n-%YQLW05t)1^?fl_0zVYsR0vzX3klXrX-nanPh$m3K(d%%@j^{bOJr(
z>}rirAl=8kZK%RL2c3hK@1zGuAMuRJK#>&iU3P&HA=rAxrJNL8N{6q(X@Or4rp-A9
zR~FFVumd840pqoXhCG!*+H)LFs^$yRtKM>2JfoKt>gnLjobRSGsr@PK?beP0$Y6Nq
z-x)iXcV4M?Kh?&A<vm#mnC+dJF~3zHtXU4&rtIn84u)7hb03&8|8R|cONcg7xsXY|
zJX>T1eI<ATkPh$Ml!aZNEt^DV68s|H<<^g0vXEdJn)a+2x*hk27<LY0(drUKZ7~lJ
z!8j9JL=i?~o`{5>Ep}D=@QC={2!T{7Bn57lRVp93w2*~$!=STSMYBdnUV)T^6(L5g
zilYJQ2BUK88)O?3%0^k5tMi9)c0Sb6_p5t`I%d=GWk93{-vS5k$>GV#GtAIPX{k{^
z5Mj^TA3lEivj5xd+b<tKeU9xBjKTVP-`C4O0EHaZwc>J+WtJ|`4D{yghjfmGwFzPn
zX@K}Ga1?l{@d!SQ+^!ePP)dgCtexi)qOK^+M(KrRQRUjhYib)IA$xPYv`&5QbYza&
zNX}p$kjs>I!+t=yp$(}XY(ji36>zSJxWCg9DU)%0MRKxrV*||8@#kclco?DuNp%dx
zNc690()8uIuY&7~HL>=Z?P*V*9R=r!bkK-grGB*IHTvCXbaMFg==9_ie@2JH<J)hK
z4o{i*M)E3ye_)1XX1f>H<0&LjAAu7kg#gtZoDjf8Z+10#4fBl=2D<g7wwGIHW5Jby
z32}F0tTK2&((qQ?E<)2J5p%-PrkUb5x=%5EBwDA64%qiQP;Nr3u(cxHkDWU=lei)+
zC#PcIf^q$z-;zI}LBmjU3<Q;qNH!SuVlpY*RkR%8pVg(g_vA~BUi%J00cHBa2v$h8
zr?oP%g6La{vxhIrlW3Y!EPhByp(CApOkiL}N>3!}beRB2rzBZZmImlE7zz!sIHbfz
zgXK{*_y_ihXV*CzAq~%$zyA2?_Iu>t;pAQaen8!g(xXi#pp+Jb=;^hqh{OldYd?6?
zL+Q1}y0QwGVmN_M+cIH29rVpyEGA~y{_!RDHTHpv{$+dWXt|l7?&xRAlFh<JLDm)^
zdIpoSM$A0^;Yu>`eUR~s6_ktN6it04=5hpnN&Yf9LIAm*WjLr>wAa#uCfNK8L!Df}
zy3N-hra08+OR(+S$w`?Qu0i}rB*01F{GoPaoGI{&IGS+6k*I;`I^a>Xt9@yefpIxH
zNglzOD%FCP)dXk5bw8RBSy6Xuc#UB3nrNsBrcuU+GeU&ly<MS*e7(hcyXa=vY@q>|
z)A4sdcyjEB>&=J1K*az?Lf#}g0)8P8inu|HERJiB`Pq@E&|Gf^skW3S|AvQ>OGF;q
zog|I%?Xs(;j^j~um{F#}nC@h$G^QWA#3V@%1k$7N5ngGMR3!lpkJ5IW(m9vGXg-lo
zoxsOTCb(^s)zxl;>=GZ=8wf%CAczCx1(>t_2|U@;PwgC`Mb{)0EW4UbH-&Wf^$ON7
zy|k+`ICho6SSkbE;_4UAs1{dw6poxD+%#RPhp<1A@WL%_^O91e={Cz2_2cJ}qeKqf
zvzJI1Q(amQmyXFAfc5FuK)XWN;QB<Zk%x@$hbOjX5kh{_@y|rIIUGbUXvzSzV^=~M
zd+u@DexY$uErBpGn90YcT|k*+dFz(|4P|}tdOyD2!7O)<>=s}rm$O|I+Xi7$yxSoV
zmcMZ%n%4==(3&Ke9-M`zQWXCuq;~JBhiSzS%8U54DgXE;q5_!z*|)WwbZ2br^9gr8
zXyST2#WDc~{7D+Bp_`wpPo!UHB8{W!5gLbw|D4o_ozI;HzB4n4CdX4WC{F*B&rO+@
z$v736mc>WeZL}>6zyo`xWqWE8X56j$7f3VxJrlwRpAz^+(SqDNZ<PU4iHMm20|9QI
zZa?3mh!SraLBkC*90N}4OuD|5uGZ`Cqm|@BG4ImJ{dt#0?krmvpKQcw{{{i?_s%Jx
z>6P&Aqzb|mG1xOS(rzao=sf{80cu8I?bQmDUmud(J$gFiN4i=gQER_TTQR|McN4jX
zURyP;e1DRBpioEBsq_<=o*uFTMGk!`^IAL5F;ujqhk^GfSPwHAv`dX5N_TH=u6>7K
zl91YvnKt1|JzE|Q$}7lJp<#n|x3&>RgP!Xw1w@q%<Xn1|QmTtMx29Qlq~i{zf%|p4
zd4XRxDCrr50KKRrFl24nK}kuiftv<fsicN!eUhw3DW>({YJj>SQ8yU0X-m2pjzS}T
zcsK=lm0++yzz=j~E~4`aj)FspjloNLAv_5+t}To0TWRKPQ>El|7zD!ksM*E5z&$(b
zt#Fa`G!$6K$@~$~C#XNGyR`K+eh@o_G{Dwj&!hM!)ef@lpHqp$e+`z7p6y%r`|}H}
z86Sz~vAR%A=AbyUeWEBG^0(lnl^-yr2Mj9#ObZ6qBvbS;W#@S-B~&1Frpn@e?WX*B
zaR@Yxk-2p^;=o%QN&(e_ZRXvR-WhG=_$4+0#>4}30+ASfhFlFGy!5A!Q1c^*Uyn@|
z<cF}&smXhc!I^ueBmLBqvOv3g#neNa%>x;viY^*x#2!w@lZ)AUk2-o+@b3b~ri#s`
zW;;QlYI4nDl&8-OG2Fhrz5Cnk{O->mm+<4beODMUQ4Fq=J(Oq9Oq>SQ%lr7%#3eda
z=<lQ3({Z^(+JCf|W4v}Lwl5JAygNKAfnwY<<_Qf(DHL|0dW&WAo0W9BkOnxs3Kpsm
z>4)Sd*v}byyhrrVtK?ToCocpNAc??q_G%E?a62?<a!RTZAU%Q@k1i)V(Vm_$H|+O*
ztf(WxMxI?Vm_y!8HhJ2&9?{~_O>w2YCU{DzuQ}Ju5&;0^VcKVjQ{d?rE&<;-TVWHa
zyOK<4s#QUL84Ou+>i{*vvSIxYJAog~Y2)gWU{zi8<!Lw2&|vyaN1i8kf<q7}RWAG<
z82RBqbF)AW`R>UsfO?CzWAf#r{jO|bC0nF`G#!)qOIVtX=E*v;6<iNT#%K5wp&$j*
z`jI&slr3ZUTE12@u!YHhg(<N+5Pc4qxg=gAU6+4gu+244V~7cs=Y6hQ9e4W1yRVlX
zVRcdO3k;-yUBPU&>f$>-PR9Y7uDXMb)ul4JWZLdZeg)h?7r~K`L}k{SoCR1W%XWwi
z7yK4$^Ln%U#{=*hNLtNvXzV!c*rx50MSJ`58=kG6JDpmXQpH77zu*-5PBd|;<r$1<
z1WaETn`?;_gxFljF;GyR4p6t~DW0{(6fNWvPKI+#f+iAj6k=Q%!{w7k#b+BkeA<Qu
zB68SSvdJX^gdvSV;e`}eruiw`(sv>h7MfIG{@H+o%9rZVuo?ByYk+CBx2ScAl?CHC
zbbKOzs(L#TbM%<1qgijKE|h};wS-k-&B8OBS%kM6SCt)T8U0asAPs`eY})nIt{&2S
zm^->lQ3-7&@`3}7KV9ib^>&5$T8N315^;waEF~oVD-xjl9GG1~t0EV)jG1?T1Zu9Q
zxdCdLp|V;o=jO#Ortt8UN!t0}^|w!;En99vy(L?@+jV<n5MrR7F6k_YEAq4ABG5>N
z5n}=6bGh6OoM?>p3xsK=v*cDcm*3+m!~KCru9T7>pd;cAxP3?;`gV;;_Yifg)?m`^
zHMaFYaSxMTP>ZsEcl+nN54Z1-gxsf_4!-j<Cx^sM#dw_GZsKhtWX3dUBe9@9eMX-9
z(?6po<cRX?G2fMUbPDrAiJ}#APgMMD?C-Xh9w8#DsHdy50ZjEvV|QR76G6sV2bBfU
zMrX*&vZ!R|Hw8&RE?XjLyLzBQ^%d?v?!yKP1B9tJQg4g|i~iUoRyaf5yMzg*achRX
z$i}F&&<fxR%GMZH!>Z?Kd-O*61eY%-B3s&AO*=`IL4f&+60Darc>Sm{U37rD#r4cM
z8>Ub)%TAd<%QQy~+-Kjk9R1`dVE!87%`F@}5l{ew&~&jGR9Ar!s=VxjjLbBO3Wz(F
zGcc@(7X8%^zcLR|$ev&r<$Fds6u+zU%srjag{}m5TErbgmv8>n&Ie-0A>-kLTNs>u
zkVEqFrA#ixwVq%DmGNBr&T4t0`cvrVLG%gG2>_b_cl)}5hH2X6b+>x)5@j6!%_l)n
zwOJoWmyzkfGaUR&+uOb-Mp5@J4)%J3qqoe;I(|1*I2M9=L<;AgOu1DH>r=Oe;~gew
zzu`aNH|)TvbgT}8@g@imtWib{D|U)ml5I0$7BN|1IzV!-*RaiC`UL;>575Q1%2Ew=
zqq1wziCIu|+6F|t(xYpv2i4O-Bhvwj$RJPOXP3vypXp;3U$9{%Ixz%?(4yOEF<pDF
zuV{eu9up^3JxKo0o0rY3^>oMsOcsI0K%i}^Pq2zE$SxZx2(iek>5xSsb)Zgho^YVF
z6NNup^j1Rj;w+;hD{y4<qq<1zy9F;d-%fh5M1tu#`M4vgPv)~TcYW|1uC<kNp|*pu
zUWo<rL_lz))s{$i<!w$cD9fSkc{aJPT~r9_Rrj%Boue4Y<kc%|UldK-Po6P~ngv2K
zW%dmAD<rjdT0`=zG^;R!ttfz<Z&uf9STNJRKs|X=_Q`=s6$#o%^DbNi(zFJ{lSo4;
z+Gk+C!OozFBfq=s9w2oVKUl;_T->LJNDdn8p<C?;D6jo6d_W+wZDub9L*tL>8>r!1
z5N}1Aoy&=wyLckBj)`W2KOpgRel4!Ft<&0-DQDqZR<Yd4FAf0RmE2x9%c3vvq{h$5
z#nEWMAC~pDf#8&cI|Ng2lo2$Uy#|16jhrBY`;Ft^BX_qGS_U*9!AcCOt9)viQ*w+#
zBUM&OK09%Nq-SBf^imeu8`@>?U!rwoF}F|4mwJQVX*?eoXq$NIRVdtfjONt}ZXDP1
z`E0|SAhpgFnJsDBxS$2+25H5RyOWQlvw;kV9iTQ#@u7v|v|2+cJ?cdo1ym2>;}=vs
z^WCtoEKtFR-+--V;a*6phirPz>Xd<hMqmbcNwwJB9^x*RkRO*jF&FkzQ^(Vyf&>Vg
zJws04=30G{)@GyRsW3(`b1Kz1-k@HF*5$qKdg;g~!}z^xm%){n7cyO0<FmA70z@I(
zI^=mauGX0!ztCHaBrqZnRAA?I7n8TOvC=Zth!pS^A`ed`PyqC*bPyqv?q5xAz@eIR
zt~vaxG!4=kY+ih@Dd4Y4A+@<6(;BR5M7gFM0u~WfnbqQzEaVHR6E1`BPMWS);1{+7
zc#zb!EMIJ<m#-cvZQA6`hsnneUp{?&{~ifhoXOj~#1@BnF1|AzUhU(yQ=VS00q25-
zkd~G+l?8?u6so^)>gX?`Dn&Fy)NnnI8VsgfhpP-2zzF`rVT8B%1`(XA&4iUf7$cYW
zZ3D5-K@`aOHHnM<Jn%_P$NX8zI?=KKI;90vw}hDl8yoCo%~aJebx((2_i8%6S>{7w
z*L*-M%gqvX`Eb7ZrzEgsM!i_^w3|O9L-am!Ddyj>tXHB0M9<S~-sxnIQQ7A(??l#p
z$C`;;nM1&+m*Y(^y{)9TuypY3L#Y%jYq6IY9foug5NSynNjYo-^mrPK8b^a+*F7D?
zG^Iosg`Yv;oA%|q{a=w=FV>Mb#z~E-C990233nkdTDDmmBWHuNs~9Bs8^*(&E>xg2
z7g$uFFK6E_6g+o>B1Yt!hR0T>P}|R?@}uAg3^_nw6B`FK97JJuww1`1t^~IyNXr4S
zzTT@fOyd$pq8%9$ApeyjrQjaBaNTyfS>8-x1cMxi(gSA*3Y4!i9%2A=GQsr)o`|Av
ze%dqB<4#JwOk0BKRmGsarlOf|^>Kz{v)^*o`jp193a*C+a*Z?zo;nw>!GY<<I|TC{
zHC{<my^GsvxvP7;phC!TpoWun89Wf~O<XJj8sI!NhM`TP1;&KjO-W`p7f*W9E1(FU
z_HS9KaQEr%`|oc*$qAsWR_JasCO1W7p*!BnX~;&;h~^lb=s`&i<bx8>;*&W?m)Ec0
zM4qQb*V@YrRmVn0c1K9a3S3WDd9OR3a<)^pH`_AC`;XF&F69D<5#%ZX)L@+cmDsqb
z3LdJd-d?)j=~dL32(N^C%Vf^Gfh+o9zMitc0#Fy8D5qJz4);)MAUR<30kxp9cPY@(
z6_img0upihF`R(hH;2E3Xwb=`0BzEdxIg(g@Jh3*U1U=Cwxi%^fO;TD317%(j>m~3
z_xra${s_JA-Iu#J@9+Ni?Wg_wyU$<neW*Bg_+;rOav-0{WO%i1MocV<JSqXyJA_%;
za=d6iumY*GqYg?}h<fYAg$`49XbMTP;C*qmS2Bo532|_6a(F#J)Sfq>f(8ox1r+Va
zM^Flwdd6}YZ(+kgtU>6Dq+>TDU}?4}_#7;TIoSpd@sJOgJfR^1<8d{a9mEf*+46<O
zen6$BG!|_;YJcS7D&QcINb_>GU5`Pu=xc!x-9c@~Ql2~8QB*4>R%DCA$B+`_wJB|G
zeQ-@@X5w7ZtTnN}%(G8f16YAJdG>MVJ(#JfzeA<6siMM!c~WLfu%BtG#KG_Bp)d5^
z62;}r4d}{!OvB0ao=$0l7Fl`=j{}orTrW?G#N9nZ#z|;OJ<(*!=I8E1E(67t&agCE
z9&ih_SbbTXa>PrVA?C*fl%#31IfGm;T-j?>$iVUlt+tcJ5}`5(0)_l_kT1D&%PX86
ztBz5+%bRL9Nys4t_I1%qg^TJ6Z1Bki2>3Fwtsz?%<|I?<0O>AQljk1e<5!v*p^r43
zdY%da>3xO&c@pc~CM}914nGGlY<CMWYgLQh;#hNdg41O(Xf2x+aDA=NHdf@1SWF_A
zxXFaC7OGpc>}4j}Qk>)S-H41L6>z3%8*G$7jFC$ZIDT6&@-k{c2LairC(^XQargAF
zUFKef&f>+D-o1A<B@*T%oy=x7L0lG!3S6I`&$hdR@pAWgkXRmHf+U^z=4qBp>?p!4
z;oK$1_p8-<Ge^`(Os2C6UAU&x=+Y(DU@<vH^oBSlx^hK>My=iBY=%3l#+BfFir3Oy
z>j`m@@5bRGeS+qyk9H+s-WI^n@=;8m?;ny#JslYR<Bd3)dDz)=r7N+N->6->9#(kX
zQ}Gx;uXM~NGrfqW5)MO%w5`|y>n1PpQ012^_6TMLIZJ2M*Sj)6T0ToogtDB{U#6>K
zs@$;KD^P^hS3YrMO7NCv_YmS1q;qT{R$ZkDU*itYnn`2B8+{*?=_4pzAo!XrS6pl8
z!OA7e@_15|lB-(Pzud-~<x@!eWeczYn&K$n15rk#)@MFzo!z9pIib7<(X7zkgfpDr
zS~q^=&Z}ull^YitSf=$H5CcUty>4_ZNWH1w2dGnDAQasr7yeA>Cmky}w9{rrhtT1a
z$rinzFa<1)exB4ij%4z6vlvya!m1W(Ua+c<-T@8W8cMqLTFNk+O>ZL=Bti1M2ah-?
z0;;h8<_L5<n3j~PRp@~gL2ML`)~I^+jXAQZ$IQR`_)kYN(*BVm8Iv&tDWx6^Wqjza
zhhiB+gNBl&_DRavoWBWh`hONEf%^&jNA5oId#n>qg(u_@ene=q%Q1<ybHu3QlVDn*
zkY>e>QyJao5u1RzrN_(;L@;)X7=pyG*C|`QbO&5B?G+8$e<ea5^-Hbp%u`6MAs}w&
zp$n3{xRr1u6%1XZf&b}XU$X5Y2^pmC&<MOVVaK(^vaF5T8T5NZr^H(o0xGOlWvNh}
z3!nEmM|2rWT{MPrMGE#e-GJJ3v~=!X;Rju1g}fM(CG2%?H$6K+QLk$UFIS~t3jPUP
zSM!Xrm+sFw(`(6Iln##bJk%k-*=l-OpP;WKu+k1gnpxwFk2h1CXoUZ#<*s?Zd-`fH
zLZEOna<^2vls(~Z?xkX;@9pMagqe79Jowf7_rFpAHLdfD9qeJ92iY;rP~Fd6#AHbP
zr^%>ZgVZ~Y)+i~8&<rA)JidH?_Y(00)1x%KPV=3+iYpzaavLQ{qUX>{k5xogWF1x>
zT5OwhxTbUOU0kg<FOmtiYSp_dbdV}f!8H_`UgeN6+}5Mr9uA4x4Dd^`uRty1adcdr
zEx1LddvA6?1=8ffcxd%?4xh5Z&frnRJb1c(MrQAi+j2`5y^A?O3gidKSIkyVFQ^b%
z+(m`zQ44Fjgl-3ldG1!*_cN?eq?oGNY4&lIF36t(Cla@<Z;IDaD>l0nQbDn?H505Q
ze?GpXIpcl3ZG(YtJ6kh*nPN@pl=1i=g2K)s{Nup2YKYbWtHj>F8BiC5$Pg?eZqEwx
z-@s@GYUD~p8soNOcPXLbF2*mW4-cZov!_iP3=$gnI?8E95IQdzlwyG~QPrui#^*9@
zljV3bn?mgq_GQ@6fjOp(x#6})L{u6N=abkHxpJL4QwIrM)?|XzcQYhQLc&p4p@G`h
z-wscn8)sItRs}lJxh<fYYxk~zksF@J$24wAVztyPo!kR8%om@Ax$}soKjI4`b*+?7
z8K(YrBw(4iJX1=78fCUn-6DjN4GB!@j+c1$gbq-*aHC47qkbU{WwD7f%mxMSV84MC
zY_qg<()L>`&Rrwb0l;u(Gs92Wpk79EOv)_cf4E0kq7tY3T1uHcbbhot*?%=NJqja>
zp;NOV*`m6yZKXUQ7oQ!{;EyKWrf#x5>-@f$GjJ{B+pI4{g0j(iV>8RKW4pR3{jS7G
zA(i)J3x=n>&|U5baTMZ*)8dZPXQzXGpL_0jGQ7AdX4aH)FnwaZ;K4&`o)!kI6xIbx
zvYK^5z3%CxRhNsO;*sDQEjeL7fS+{3(<3=~BQRth81p9{AQxeamOc078G%4N)yW&V
zvM^4fsTkBJ%cuoYVpx-pD8c%GjHDD3fY4|vQZz$~krajmubWY%kfvP%Pu6fBr>h)G
zqfUO0L@#DxrNmJ3wD)wWhbfQHEvRwo9W7~}l7NeqLw-hWGS;n%5Y^L1&QjT|Q<pGQ
zi3QuuI1I*-rFK0wa0+Z-ZPK#}q_IMJ7Vdy1{`oJ_{_|CR+JCg4V&(ZPpmC^pJ7JI&
zNbjz<N!kL=I<-*UB82RQ!2<21U4L=Svk~=psF5Y%881+@O`c6s?Q6#{;@6y#!6tx#
zw2T{M6L?ATL|sb4UEun0PB4F^xZGvU`#Y34t+Jld3(i@%DpfVtX?^yzFNgJ0?TP6e
zen6w~HGH73eca9u;{dSXNSoun4kL|)h5)9d=YDA@W&&xxwI$iP6(^%XJ1(}j>R(jU
zs)nRT!p}=l$0cPjC!@1Da1;D<F2_4~rNCYJYD`}=n?YBu0V{ULJ<mYB#tbP{rJrsD
zGhK&JvTe6h5i{L~ZTckpt#o4Zqw0}%=XMCDay#iCPX^}k$Tp3A1=1Lw;9O$JD?@HO
zf^}00X_7ZPQZMC*rfAUu_)aFLx1P-R^N*kY{^rv=x;owq(R~!0vY%8P>(Ih9psXsv
zJV7KVJgG93@PL#|B-#iSAc}<RE+?xI6$T}b(*f$;nsRgd37d-yIuJ3;UQ=rV2YIZ$
z@FauMwbqD;nUR_A<*#pk+JAB93Qrz<PYiqk)hJ`f8*>ej8-b)fZJPdS(fNEl!3=Xm
zmXwcIi|w(s%G&~Kf_XaN(iH4CTb&<Q{^iKNbo9u*8qPeu=RxFM*-S4EO<7#V;}Yxe
zrC^!Db4vQLB(ljB=+%Lj2c7+N`}Ujh+qbu$Kd)~;{q^qi=ev&|ykY$1%cr|Pef@I#
z`J3(6KW%Qm2gq;xW((uI%*y4129N2_mr_f<GG}OHU@4n$>Op%j0SE1C>$}Hm9iQ@U
zG_`l<F+RrIVP#LRQaV{+#{bA~-}3gd!SWjvJ(MK#F}5}pr*K%mLi9Ub-QCSSXn<+2
z2HMOPvS4~H$8ebb`B|Zi;zm#=$795WtSc6z0Tt&{q3mApqjJv;fP_WmKA2U7W1Q>s
zP_VeF_G-$M-RF3dfEr9y2N7XG&net-izAxDw!Zv~tg=~!0J=~;ka8z*1&|zMN~lZC
zfLOKUvDRkx2MScm3~vJludua1xtj?NF8Dr;7e)YyT}8w<%XBqDSp~K6n#iK4P~ppT
ztmy6FsM%toz@JR-{`RD0g8KXD;hG~b-Ny*#U_|k8UlGm{th@Yy(EC78Q$@)IbR&t)
zp^vmaHByQr6-slRXBgBhtJfq5cQQ3sepoLzYbXOy4SRg`96pZtdB*fKJ<WC)Z2wgZ
z6L$bs22$C0+4}I*uslZ?rjpxSET`tP+IWj4pl%6VJ#DnV35mA=%?HAMuv@66uv{*O
zuT&%<RIK>B{`P3NTs{XA$wPSZklfe@cOi|-XG#exE4l~=W&&QK#t_0|YIvnxq5j)L
zHwv~deKPbf(L-~gmCuR@_h&GtMb5SgP?crS7h453IOV;+hvWq5B&NIbt|M`R*p_9I
zU`xysxpOVI#AvAJIGr5IvK<#%71Bu>LuiU_jR`eOFOsljRzuQ27@3UpO8Tzl2zU^C
zkc2o<7g_G>qo;#A@tw{(>3QE9DkLY0jVMm^*gO=gCVh|A!@N&`1S9p}2~bf12>^H`
ztF;A{*ZF?AT_6W`Wukq8G(TzS-8h1Z_G>tl)lom(69LdTWGi4;J%22Sl%=Fd(Q2kY
zZ*}1!c>&Uta1F?QQac70fRds#Aa&PkNnN))C_Ck+88INyV#6!lcT#E7tP{uD?xAQz
zWTx-eQVfY10U2O9T?p)O#@^IfW$)>uLF)8H`nM|(;R3gQHM|xjx_ZT!4AkS|RpC91
zV3+xF3k@A-TxnY%sbVFH(#6d(3?DFY0A_<WNq9U&cJRxy$$oiu_vJG-kTPU>&{?6U
zWf&M~Iq=0WXnK(pbq7ZTkh^3Y$hvTD0k6?cxZbU8;Ys&hRTNiw)4K~49T9S9i#y<;
zN%Km{l{tq8d}3Va5nOOZYca#QV=<)&kJ(M`4_B`d64KkM2Nh$58cS;+H!ZarxvE_H
zFE(V-@c(qS9KW7TySQ>XNPTdmK^svo=>E>20^=Q0bHkq!Nz)laHgv)u&dzu}i}f|5
z$A14!9oS3exry~1{NWFS5f~CCHPmC6_$nnqdi-y=g$SKC6vPdG`-jDc&tKkrczesx
z;h}`Q_JO~)=fEJLyx@=jg>P-f(S7OYm%eoLi(h*0xQ~9(BTPfcU<DX7U;##P;?-(>
z2G1Esq-Lt&>VwI^sewn$e`x#h61QAJ957y%bjhm+mT0a6)RB<b52SPUdN)I?A&ZQ~
zmA0Xf;|rv!q9s(1i-4#KqGv%mULz7e>vRL@72<Jk2l;oeZxF`C@0XW;<UcZ$M!W#)
z4L#T9sB%qJZ2T2bq@@kYTn{Dhrra7x93|s|^U1Uv)9q6FihP+5U1*Q{u~`AtN0(~C
zHc><k^Esj-E|DBLsEaO%zW`c60UG##qc2qP;M`-?jzH0o@qINlg01?I-lCB^vyBH_
zB0ryrkPsT2TWFyg3JLiXyGsPUknz>-LcXw#$3L|KLk+XZFy!7Sht_XCf4+S;e)sOv
z{O<i1c+2bSl6l-*GkQsQfb?+jOxY@P(y`_DbkL2O!z80ofJq!$SWf%8=w92peMaqn
z(xwegLaAXj+nLdY)0FSvdqR8MD~9$2oDgN&M1Dk>7tn$XIcR$7n3)qG&c*cn;*cv{
zS$`5Ca5l1~kf&5VSO~mlufLmZR<=^9{d#*oA73wb*kxS8-wskZw3AWSlgoEDr4z(9
zoZ<ZPf7-!g?_0p6g=mzDK}<)*E7CV%d$msHZr{>DIq7SYx@gI?FP*pPWk?cC-F??2
z$@%cUeO2|)t&UJ=gy`mCY=FAKPBT;y&;(DX{Ze8HP2aOYidvw&8<Y}3o3Udid?{}z
ze29G)#et_F<3&JpOU-|ilOq4o+*QtL>Y_1-SW6G$Su9Tvp#Ft5=^G%5>#0(tP?>2|
z3M7~pPmbwbVErCH{>=!k7XKHJ+HWeT-411zIW8+{5b=BZ!S9tt1RDnl<tmrCL8dG{
zP-B5T?#?GpX$f@(8`pZBGvHh@x+UK3pIWyI0jTMTJuT_N4}qSP#TS<&+FYeQ9rQ%<
zk;s7tc6*|-Y4Q**8-(@SB*pW!7f($Im!cF9XVGI&=gS53h4;;44>TP|rs-$W8D>MC
zZd#>C?4GulzQ^_AoLTZG{0r5iBo@||@}vjpd;2)&?2>d&+@dd{a*M0ExQC7{N;>A}
zKI+1yOHJkH-A|Wq?%tn${7I_ph<>rZl`@o??gp$+42OO&u*hhD*rtm)cxGWE7>uNh
zb)T+usW*dXf2dR^tLPDL7MnIp<dGAmss(WT$Z|EY3YhyUd-kT>Qcw(x&@wey!Y*gp
zO1j~e_@0X7yw@%9>GKhU^?ZB|2Hpc4Qb5+P{&xF`iu-TBe)tN8;8*rZg)TEYen%<+
zQOC6Z3PXo2znpeZ$Q4N(=g1l{orMpOX5D=|<2-V&P(~up$Eu%jAw7{IhYfVhXM_9Y
zUrl$+(+g=GRycDL;ECM+M1WRXDnK~DUQeE<fH)d;XxRuirDIuD)0I}6ntw%ST+FX7
z;e3oTsx*u`-tI#6GJTG_uDIYDS9++84afqx0#*MsQoj<MgJnGjNXt4l9H?-XarRW}
z@LS#Qr-InWx<iaSTHN0^IR=!CdYds*Ved44>qsvsmA1(sY8~_*jy#u&besonLnu(s
z=1h?P*u7dkw>;D7O7K8JWD7{bP)@c*xxHQTG<$A{-YD|~Q}>Ga{LB$Dht|rY+kIRy
z+i`^GC<D3u9AQZEol%)Sb0aH3Y_9Q2>AMr3M|8;<7*BVr$%RMPi8FJ~gtLgUw)5LB
zZ-2P^@I9xm(A3`3Ngqxa#EcDfqfA!O@@8GQZsWe9juf%DPHo9Q3a^dlPxkU77}S?T
z7l6!qW2p*CYe-_Kq*<r4qOS}Ny2Y?pMk(@o4dfB4W58EKNid>H#%=*u0JxJ?*?X8W
z6yw#$jVF|GQsP-O$Hv^en5>=GVDDhZaT-y6gK6KIdG6_;PvFuizZY1lB7=Kw%Zc2@
z!G^yX=WmK5*}SH|kKR<_#LcKiiJMWvz7d&?vXh0<))o0|)B)7`Dd~cwc{@f;<HoWa
z6bx)-dC`=>P39U?K+hQa72DGc9fp(pd+MvS9@7h8JU-%N&|GV*Y@2&t3J?9K+1h2k
zi;d#x$IHd})eH$fb^`{BP0MDs=6Jj1_Ih@M;%ZjEo^Cw8nKwbs4o$i1Xs`=SBcD5S
zQaHNWR;Pgpd^cI~(nqWV)RPpO4GFUl2WyVGhAAi-8x;YV-F@ox&S82yuyquODhk$`
ze*lC-5ELs|%e{x&F^W1%$TL&!JTv!k;(jj|r^Hvy2JV3U3*8pBurg3b=5)kG6~on=
zzAppwd|Q%~Y8xip0yhP0q0(o<HjZ9V?3-AGVF-74yoqY#ms3+~N#B#MY=4|>pngLg
zZEkRF36E4(i{W`2-6-h_oLkT^5=<XM?6i5s)L(Lp9@zb!t;|k=7Ziui9d9(aGo+QT
zOVE*|uqG+Z2fuFCqqxq*?=S#G)d-@%OeUqZfY4|-864(69mQqpACKa4T@ar7U<}to
z_xzFwE|CUta@1BEq2SEL1j#oaW(wG@U;%PGSWwdY`{nIt-pxbLjT2XCR_S?c{+C#C
z{UWG%htPYsQ+|OeXe!g+9;K#W%O$^O|Iy)>Ni?TGUX1927Y((6@di_@=0yY*SDaWC
z=vPV$&gwAJrw=Q0I&vw6sIQ%C{J9%9WMHCwuW-5;D{8xH(Uj<vWF1;M7X2zT@fwej
z^AonL@%!&TZg1bC4lCpkIADxN@EJD9@_YqG9^U%gyaush`fBu|k_6LCr<JBcY69*n
zq6;W`7|t+xyt3TH+KG>baH*=#{mWZ*(JM<~bn+ba1e8!F#8b6s%JTXtasW{#7Vct4
z@t-P4m7`hljDjx}qe_Ewhhuf=9;iWSGmpgB%SvX~8X*Y`lW`ynApcAduhE9sl4fRb
zSB7ayg3Sb)ZOxt)NS$q7D6}Csn0OoJyfYp4;@Z~ENphB;>|QRqI2m%EUTMqo3A=69
zX)ZhV_)U0UzjII08$2eY9F~;;dpfoRwR8!kwnUhg?%VEfu7j3*&vCN3;cR%Mn@r)n
zn{i#d+(>C<1Cv|C0+o<#f0Mzk=vGkv!^be&@g;it4keNf5$r-UT%ix-P&!7vo`*tz
zrlOSptq%<z<@kSMr2nlCjgbyJBOM|l^#5>9|63m#BR%<_80mlOLt~^!7}V_35xm&`
z59jp1^`SA+C;t;8z3-vb$vxUXt?5*2&@5?~l0v|&z!)`ZBw(~Y2lIJ)W?a2vD&1j0
zM}@1Y<Te`Y9m8GBqBygBk7b6QF>x5^vEf@q(-M6nEEf~?0-3LXzrn=-(a}C-zLa60
z3K@)r2O4GpC8XS~BQp?ak~)l<=}16Rn$ATw3YaKI5c_ldVE)wW<r-OSqiioV8=Tve
z)FY(<V8AH}9MfHne<u4>3HO(By2*#Gw*!j-v<neRks*2OLwBhQemwjHND;o;fZT?_
zT6Uh+!<_7t2qi^hbuIV3@JEQQ0Jj8w((@&fFr_w6q6kKrg9d4r|7Ue&^c^>44j1Z(
zWAeJTzO;dpI&b;ORsvh=J|uve3(HW0>~6j3Dody)kW2Z;6{|VpUq-jO>Wup+34A$R
zx>whf!Fr@NSm8C4D>Nmqp~EaJxc6HvOhv)~wQ5duZp>*rGG@kAg2T0bXzGn)wvnX|
zdp2(`!5XN(k9Kf$pIu(Sk)m^7Ul-k*c6&sNZxJsZizK5OmmU!o)J!0`NT&XYR{?Mc
zULMEqKcqWWhMj0cS<h-UFDn<l29&2gpW(wwAJQCpH`DRh!CR(dOU~`~t=z6+XJDWz
zz9jA3HNuh8gg{Y8o7m+gINzE#?d_sBxZaA@iKl0bqg8A=K&CFJjAhBIa4wAs*+0X%
za>2cXz)z<c9xa}HbB8iE(_je{>Ye$ew4|02RQt@6P399vsRHM9_X@eM)6cZ;<|eom
z_}o~{gq}CgrRNZ;-aHq#%H-=N!D0i=xA}laoXFh6ZAuq{W)-3O>Y#2kJrcRV^h2`@
zRSJHX9}^eE8ypp19<n6Jq3P#DI?|C(p4nZkTIil>uGi{m&cY9<KOJoWwJinSA0Li{
z#`I<YcD1>t=&h%D0e~u1HV+PVW=CxXiIuYZ@U%?3K-CJ<myH-*NcS<EwC!vILu8<G
z`W;bK@)NxOKfn3Y`&;XdoZ6`0ySe4RkcowCP0z7v4ZIe#1L_M;7MqE*!&P}1PoKVQ
zGj;TK(VV2YPx`gWzpM)`?&1ik_DSAQcA2-R8(cl=Ij#g3VT73lX%A3mk6efoORE$I
z?375Sy8?KsL9aF#S9)0bJc#C8TTi)L+0*XnqtD^GQD=6u+R|ydzSJ97N(G)2rFD}^
zJ}?&uTE>3f;;jk$m&)-@FTGHx2YZU<!Ivn1(eZZa>7X0!jB``!yiuq8U)STAi(bmc
zB-a`~_CZD7gEu{-$wMFnCJ|};4&FW<yfu75ryUDyY%MbSyb|o6PaM6P!!HwV(E4XT
zI4yYwR}!bSFcU@E#tOG|EpqT0OcZRcnrS0PgVx?~gPD2@Q$WpejEYRi&T*hA>j<_l
z>v-}+kO^p(miw>r3@H_R_a&vmP1yYmM*|~%!)zC*C;{#&w&k$gm2DplfYc$fkgx)6
zN=d>CS`tk0K~sD(7|N)!xu8iU=EKb_r}+9fbJK7j2j4{p^1*$8Jm2PYh?32k{kRg`
z&cO8*;y7nWCZl=^<{Ribp4L&2Jq*LUn!eY~F~Kw$T%XJii|Oc##Ls{{bgyUU6<y;>
zaPc@}I@qwN_Z;yCC8g^^Z75)v=r;g1Gi~c~F?pNA)nAMWe6g2jbS%vZAhlDvO1|C<
z!GtF`kgai51mdp64BN<Nnf|~+#QoLleZsk6Q%@&#p@lPDTE<(TU-yO)+ukm8)|S14
zx7gm+sd;{Un#nPeL%uLZcG+n+7cz?-YK3ThRDd*X+GxI7i6t*>JPD@m;2yY!KwzO@
zM2oFp*=o26H9U{33_-cx!b%yGN8!G{zWL)S?=VXoi@^Ds)zudym>$Q}-({vCkv3*V
zLNhvGm3dQzY<x{M)pSa#fX*mkpCEUr({)d%A$MMbJEeEgmM({;0LT_;IQ<A;lr8!`
zwWd-kkv6z!P%qB2SE_&<fe(StAZ5|OD;My-UVKNt6aEpLvZaWMd)6ms&5+h=pk|M0
z3n2B(SRh4NyS39gt&ix81E*a$A{`F$@BN`%>J^Z7Hcwo|_RJFK<s*StoYvD^B7Ccg
zRJwhsg#$aaQ=xTF%&t!dK38J)6x8jHq>6bOID43d>9utH`jz$;@CGcGRCq&ezlFn!
z<!&kw313IbJilBoW{4?EE@miqbg@~z9Ha(@Ltm|snG4CX#Qm4%23s{+oHTy-02q~C
zG)A_GmFS*CyGo};1E-Fsuv#a_azDKtuokzWSFpk#QFy<{Ex_$p%I|tyra>r<3s$58
zJu(~2){;*>9U!b2#7|B|;3W|_T9ypA7S;?G64`QDb`Z5NB=-m_+w}!NIGQ?{6%}QR
zH61Sx7;npfd;5z#*dxk!&WUp6;Bk~xeSq+&W8E#scpEi1LZK>6m08G#h8nG9E2FtJ
zC36YwBt>?W`SKbmps&s)E>R!(#7!qm`E0@{AGXNCXtL7<MIPuY<0@^{aL=%yHhAyx
zMr{xkJ7=0f?J?>4@QD*7ce1d^_;}vXYy)TTxGk;ZG^2m6CCA}pSf<co$$Ox<k5ZoS
zC*0n+NQp}?O?(!3$~*+@8VRsjkOC={inR1J?xBDfj?x+qov6&aqz$!c)$Hd4;5kiF
z3h?lBk>;*9k1I{49V$rJAp`m`D_Yb~`4VR5GR-oL-{|B?o5=61(ICxd@?=UHK+9hh
zRD|9k?O`=!0LhXdZF3weDH!40HyPGkbOTcNJpF(|L(SR$FF4ieW^T$blpA5~WgP?L
z@8_)*A}BUY2li+p)zeFa)nZjEVsj!hWBwlCv3po2_dClOSi%vFw`A7IxO+~Bx%qM9
zHEr%I9n{2`*mS9VkVk~^K8;g>ztH5Cl*`z;l5!b8$GdD$_9W6N>LKB>bG=(ZW|88m
zYOx*TQ3THnA;gu&RML>jg9efM(C#TrAB7WVuhvK?cyxHGGJR!E%A--cmrscTJewtQ
zSxzpuILltw0?%8(GZ88vvK^Lq{7Ia3=YY%Ha9s8dTpxw-SVWafmu_M)U!Ch0FZS+C
zb(je!?Yf28UYGj#r1OJG=Ga7vC=pSEv_W;;QzVu$Ayt}^9=PsH5lD-x8#v&=mW}4Y
zL23@W4-_c`{1$0HG=oGHJC+iB`{VnspZPy(w4f^0Xqou6P`xu8CVMwkt@_Z+-=WS8
zqcV~bPt_O_SZUX!3JQtI^Z-2_^l5>Cu`6NDM;cQ6u&-0mpVgZFD2&czNPnVatWs-}
z6~X*C0LPX#II;%!!0XApTq10M8dKU1oMA~*8bI9=nm?wds~P_ilDg7ZbA}j`Zr6aQ
zt4RPwUZ(<C;ZRiwr#cVF?J6P4HF3u_Uq(1xOY@TK4(muBr<FdJlJW+5LO{`+K#Opv
zrJ0aj!~Y7ykL5FYx5==2QFYbV2o0D&P^B3M^Mmr!;A}HBFuhsvwfFXcfeo5?`X(dW
z22u0?bqJ!c4d;N0Q2s4kjuChPu4Wu4!99G6xAlQBzidWAuik=%9T@wQcR-4d1x$XX
z6GJ{wYDNYlQ$9h%xLqK73hhBu;n+bi?j%6I5$N_*Oi<{oGrI5ZV7S>T$&Ea?Ca!d9
znJi__{2BD2#%?(H_V9Nn%jL%ZKmh0@<R?wUWS58H-cEVpO;YaVC<3I;^`WF}(O}KK
z4n9fZ?I1weih^&BHDw$2KnB>nc(j7c@^Phkp?Ji{kuxVL+9JmV6WuJyRc;w?r|s+>
zdV}&p_p8CB?^0~y^RU|^0Ql_v$G3k$ZaACGHXOOrtDR01G^$aEUh7H;_dgK+gy*C1
zCw2+b<4abi3axC^xHY~@CXc_IwC0T(=5vlSCx`1~M#)>U1<8O33Uqc~4KD)pSjDkl
zUzw}n^6EL#zjzo>nxft=x*4yvyq91}@6UW`z%-#*Xx3WhOU+8E2(x{SL0SGX9$ELN
z?10l_jXA^d8hU=+s7GW9qDQn{AUtc2tatbYtZjx1CiCB6(+;1F&i);V+nlVO8q?WV
z7v}&90o22hZ2~s5+HP73&;30#V4W;vOGuf+%KJLN{EcQE?REbQkUEQ(1UmjB91lBI
zl?JFA_WM`B?vY;OP)82J@a`2^yye;I6(V@oyU3)Y&{`e<iP4wvm~oLa@lzH^)suP>
z)_!27*<}%F<;)oz?p~aRu~rw_5PNEMYwkL54Um2ZRuiNY-ANXWa&FMq2n^kBUXVK1
zNBf>mny7$9P!}@<k^Sm_Lfb1X4(!qVMC6jJn9gD<08(!}Te|&w>(o`{=-4$>NyY$-
zdUs2dXOy51x0bE)bKzuwz@rczU1y~z2V$O2uh+}js{}K2Y$zNR&x8l#N-Jh$BYZoI
zu4sQp!tlNh@vZKaDshmbpt`4Qi?>tt+9?4KbnjkV;7}L4(6^u@fR1xPDJtQpRQpe0
znU2lEchi*r@)``JTFtuz&DeL4SA5Z(Epxt%cNtjU6dNXdvk(CXVpl4_`+MkSr(xqm
zW+)m@@ORK{(xjX4g{*j$qNO+~z}1k7YH&IZDS|?2@w4pFwChd9f;*<Q)we(@LS1#L
zZ`9Ot_T7G67D*eLb-QY+chE@QL5uH3HQ$ytP=?!dk@JWGs?t?Ln4oA%o)HoabVw9z
zpyaHNYX_{SS*yaCd7H&GABNvY9kY*S+nI)jePaAV-&8r$B)l{sy<sq)?w(<@?cipZ
z_LZ@zoYMelWXN}Vc78cQ^e&Ycb^19V#V*j8V0vjY@oYTbX{xy31k(#D5>$m7f!BWZ
zYX6dXv-b!oFYl#CmDruin+o4z?o>c{$m=@1GF4byX>Ry|@F1WD04n-4zOYHOU=5MZ
zK$JMn7SjdoC-G4sJhoun#3zNq)FY7GmEIzdGDpS5zbGY;tkStx&7^z4=RsFyiSG8U
z^foUU9t9u}86<N4H=}qt9USM2vkEkV)%7SfWmM~F<pxl1(^_ldU4dOWt?|~LE}9c<
z^K5|vW^~V{+=jxHvA>;l_voOw(kj~IB@3tp6GTq9dYAT^N<I2OQ3qP6FrXQYiL10@
zJa|m{Q52%YG3R4F^gt=_8A?C+c3{dqPrtyaklt_jb9uyjI*jC#gm0orjQ=V;qqx@K
zM8&b9a8E*lzZCfK)J}5?)gt%;#RAHw3Aiiit-UgY%aw7ZxA9i1iHqcZ5T24O!CahK
z&aJzomxB0UV;CN}u_Wqf$~zB0V3->(dRHU8(~680=rXXS9O$V1qMiy&BM~sr#`}*S
zz8`%3@cHih54Z1Bi@}N7`f^7*;Y;YpF+j^YrN??=2D(^u5;L6cJ<!syZDj`u(t5!%
zH8O(YZ&{e2Y}Ra2?V_-M>J^U%^<`RJA|9~T&{bEA4VN~9^64t_N}w({#hH8TYf>LM
z|7KyM!C}RfhTyUbrV2AA6E@~58H^&Oho8}OsaqLcw}9I643Z17(e7xcdTpc<sA-Q%
z(qH!PZ{K`Y`kcfcFs_h%@|gz|d-|5J@NkXF0vdkUE0ifCSCMo8STx(cqJ#!C&F0xO
zU#^f1o+>j*QS#59T*C1iNhO>W%MOcJ3{@JhiMmjTS$IbJz?%DKde1p(CRCPl--mQf
znNQBn)~zVqg=>-ds*N<*b0n?P)-8pN>3V@!F7t|Znj0Hap!AISc8C{mCt%d{kh0c1
zm=;oHH$k5woe?;PN&cqE1^nKt0~zlyNO}pA^zF8ziaziIqFo*1Uex4(3YgP0=r(CX
z@mAztK=~r}<f*0d6Wk{D`2iIKMLIXOIvUQD7L6$c&^JzLAcX2fslrkOCoidggrgoT
zgvj0~i%Xt}3m{QU)e^ybX~?O`jt|+yg6kYU?J%N4S-6aE%#Ph5HAu}~*a0o#fFDdh
zBVU^%BEC2w<{{NpE9N5-5wpb+i6$ge$K+P=s^)+ns*bp_6CO$#79-Ju(C#h2j@cH4
zLYA{@-(8Bfh|D-=P`!c8e8u7u`^n(;CuGO_F!<HvSA&0qt_1jIv$D!az>9X3_Q2f2
zNs&2Q2QRJ!Cy63rKU>i|FH#E9BCWpetmA}yNJ_4D_<HGNyFwYp1d#aIX0g6N`7Z4v
zaL>n)sC8*Kd8VCS3uS^;d;I(g)Pa8U{5#){Z_>W$K=d`9>1qKCN>vg)H@7@{oNH&~
zl?di?mb_~U2dV_p7#x!`59Dk*lW>Qr^~*fB;TB?U2h?C^$sn>uj7s7Ww9pnKuJl01
zVGt6qoO2{@43RRosGk?{?N`F%{5>nVV`FMPIcF$wEK?^L+G;u7xj;50+IYZ?K|Rm1
zCvs|6hPBw0tPcapcXu&3lt&2sL0)&=1+CR4v^m>PI!D{&)IbfSY*=+HB>!&5Y3*Bp
z=0wa$fe&29%tgyRUqZY4bYFsLpeAC`BMxT{tTvx7+k~xb2dtZl<KmhZJ3HDJZiTbt
z_ZCuvo1BX@RK%}F*}z&u?@EH05x{#wgBLqPhFK_J-4uOSZo<b5AH{R1Vk42&smdh+
zedpfSOP?9QDe?AnJgvE`4pjGKTr2K=?;i9`GrT8OSM$Yr8f7Amn0ufXeUNdvS>{JB
zgrYr|+o5SmQ+|)${Em^|!#UyYB@j7_lA=J|jA=qtjY4IYOp2c(J6h32PK#c#!fB%n
z;W;r?vuzT;YH6yPnZc<o3&@-CrX)f4=1bt6?grAXIXKjAlVK2=<zC804TXEwvO&7&
zD5YDdMs8@s(~B7@12;?6pL7HTeeLl;;&=Uq`IlFN@cteA=CKqMXHzgNXG%?kf|CC_
z@TmpanZxpg)wy7lJG}+dm7_4dJfh&t=yW73?>i?{O#7%Hk(EwEkx^*z%F-7I*}<2Z
zq_f|zE(d@6`2Nk8yZ5)!nZSL0u>%cc4HR{g{?U(ecz$DPkg!VnAV0~j|4F{#>=9am
zkT9)`AVoiFe(+bpGKNBs(f3%shDA_IG-zSDF0k{0X1yvnTdF}bS;}zVgfg2}ZnQpJ
z39vM}R=`eZ#Gn%lLCWIaN(<Y5{vGFmydjw7hzzpWveFhqY>QwrCee5MjaqEW>h8mO
zD8)GW>;_8Zxx{yD>jNetRh1w6LGBc1-~z3bqN9dfFL2}q=6Zq04*^df0uB*wt<41C
z0SmU9OaB%Z`skoFw#LM{{j?~<wWM(y#7G+JsOa}yO3p5@bXZzQWm_d(e;+-ZTa4DF
z*~{~eWwC~(?#_W0S&)=`U7n_=p?d&-?yf{i@aaiE@C=+m3NA6EHdw>IEL=!wSjKc-
zujeh{E<{8@H9WF8by&Fk02*hPZjbzJ9+lT0;+KKCAxY658gvXq`S!;j_sDelY5(r_
z&v#I}?BCyk!GH6fUPy<hhtHgQcJvy8jw+4Opn-2?N*YI2=F&umvRt0_-N&y8<U1Js
zZZtYPK7Mj|{A_e`cr-j3-hMlLf>4?LcUMQqpg%m7FWKbHhY7;{K7D-u{`S*kh=7=9
z=7Mwa=EJ-9w=Og0)o}d-YF{GRD|vOTnCf)-gkyvV=&d(y1=7?Q9S6U-nig&<;)m8i
zgJ59vV2U7_A|V*WzdVU7u2g|zW&OsWSd?2VFM!)UECKSdaie~b4_{sML_^SSG^@_Z
zJ$im3qY73VKXYO1Y-LE>yQ%YoJl>Ehun`P_-`h=-NJlGV5*@+GgPztlW#+OM@-CwT
zjMD-IHa9sWW>$`^yFarkLTYmq$s1Nzj|cx4Fn0}DBl-h>`v+2L3(XVFMlW>w{op?b
zx9>mS4(@-{+3PhD7W{(8p(CF6PrUOVg9&mW(zW8@A^vPHd-H$dTmJq72)@`)1*TB2
zo}G6?Fms3jW)_|$`~91!H%E6OOzPW@C{h9E`J_Q4tJEtqnrD(rjBa&SE{o$3-t0<S
zRD@SS&8!t%1vMiLI2+PI4W^%V^)?k}Y^u7Cc9aPumOp${o{^C;deAO15h)63Ef6O=
zxtPJdOKKlh(qiy%fYc~n2bDrECqockH=*Fyu@##o<uBUNtZ2atilLHrO$>#S$C$b-
z?`?3TJ7M2!bG|7jQy&;{%nh2zTJ_JOE;w{$rrTsR5D^PCi0e|4U91xR6HpULZi7zr
z@-~7nz#y3hMfG;k&E%B}4wQI5<+B=8SNa-aSJwkMK2GL}vb1v{)CxN$SQ;=;HyBVP
z3S<5bl!I?{Jij&7A4!nXWE2(P`7QZY@E@N0!%M*%Hg?sy<9o5t1W*yf45>MFuddRk
zfyBE#0;P<dlB5RpBD3!~aur%c*VrO3p#>R7i_e&VP~qd<Htmmw)m#a-#%C+0?7qNG
zrVJl$w#i0JE)IR#!^JO3AkC~uU153X#HJeYGQq~w2qX6?k1KtpV+Sg8a;Tj%`V~xX
zEtj}Y{WbUH*J@BhN+R~;L4Lb|0@s+s;C4zp+2b!L)*b}LeL<YpFB<e+8mVc<My21N
z+FkSLN|w0Nede8tNVi_wJ7>LuX?}O9@~AzrxYjd`ElI+ohXp3t@dWb}ly$OUywh^R
zLi01u+iE<usJyyQ0m=RI+!1H?&z{Co=ya0(vP@}M!8_Y+bMX`^n|1@9AQoC}t_Xu5
zRWnZwP>;<Yg<4;Q{=C&)AZptzOet<QT395^RTng2DUmUK0(0P5(ZtBJAa{EwZYFp#
zg@-rf?c>e^2+-87NtfzDU5v-$F~t!|8Z`~-#UsSnJ_76MC?WZ5IX1Hw`b8d)>zfMR
zRvwc`2Zc|c*dKq3g!R%!0Yn6x2baHMXJ_RQh)P|u#Tw|gtGg5;ME4>fBGl@l6E7q0
zV9>+#&$`igQuB*SrtIs)cSmNziolJ&4tXxj!!21H$n9vi;<zxX9LY5IFRmBhC$BIl
zx~nL26ue9>Vf#m!l%din1EHn{&7|%=8qxRh6>t09(`QegJcBHAeEMW`G(35F`&-1$
z%#TK>&rlZKlPY%s^>!3cH?N+##q13|=q#@EDo6g~5gfd>9-J!clI<0cC`qX8Nok>Z
zO5Cxp%HCpUh}((lv$~4t9eB#GsCxt+05+j9<Btf^oI&&Ti@R2gU$UXJa#+dv6`hJv
zyQjRLqcC@vQ%-|Nl0T!<pbl7%CA*@uW=f5IL?*;-?lr_Z8ymrVQAbkPfTy6o#_?6*
zec;?*CacWXM$Ckjg0qkFL3BBbl~r*;xb6+%jcywLtS9T~ljp?UH+$Ll1k2q$C0D$p
z<PiguCT5qCFAR5^NXL&cD@nJz?ho>=F<e{X?kz0THL@yjH-UN;KMy-qPQs`KQD55j
zr?p0cce}&0Nba0M>>;|;TIQldn$@?n8z@3sZs=z^Yjhehyc+hv-e$N3RiIU!zTZe7
z;tpgAMRj(KY5{H^U<~+#;*-h?eULMxQmT^mHp&bpAC+Z}<o#tX7Jq(Y9u}dFQAI-q
z3R!RnWDhV#&`$yZK+S>yH~z~CAi7#Hga{Et+0<>3MH!$`@lmGnLuNWXOP&RWT*D*V
zu&+)^$5B@<+txvI$IlF<rU_N1MurC<a?31kPO+8fKm4?$CBCD0ZwF?ZtK=#?ZGw=Y
zZAH&?f{!`r)pr;0lyU&!+9~A#L$|SMjp23Oy^&GBNGk|!veE!a1q8BZb4K;xct-zP
z$p6a8hD8`mHm}!pQ~NDXLDIC@iqAuv7T7|97n9?8<rl;SD?plagx_H|P{uf9a$v{@
z2#)y)`)YJF!E)B5$Re>4>*lDkqE^vG4^IaM0iCLF%0JpE)aw*1aqV+m`rEoUZ@AwY
zAx?zKvhmh9qXB9l_9|PDQNMOA0d+%)2w{qa9o-EzZWKCALb;OQQ^gYqxHPfSzJlo_
zSkL3sr%KFK07C^)U)z^(0C<j1f&L{j3#0nzdc7v@11mH`t~S;q<yCZ`D(oN3dypEw
z{X^#-7^Z%WF4cX%=S@}1@78ZVAzvCgmye^0EUT4t(3K7VnNedFoI=zveHKrs)NMd-
zo&F6_H&8YKi#6T9`~<D?e)}VaH2!q^2I<WE0sGTGrPVnijsVUmR3_G-<0v}ddn!?W
zA9@W-BcXco68II$?(OaW`<2P$-n`%MKE3(y`LB0hIC~mb-K~Oa!>8DmX2Q5bGfZzy
zr-y_I>aC=pCL>Vz3DLQ2KY9)oN9iauF02k9ZpzsLMK?J1L3(iAu9-2N{+Ayx&+k6J
z`Sa}_+VwAYZ{fjr_r;X@PnL}z^3%{JP|*t%&E>H$kC$KzcbgRwHbA!??t8`d)PD5{
z%dFWfcU;cU%?i0k-(c(@03ek|eC7;F*0%TEm)~9deg6LA-zQ(*o7Yq4mU0twG|-H|
z4PUaa@-K{GQZf=d^z<`u4I6p(8T{Ojg5`gSdlNd0U^0Y@kdzB#J0HZ|oJm@a(OT81
z*M-tF2%$3Ucn~DLVeLUH-Jz`mvCH=M%Y<Qy)4RXju{xPkOo4!(6cmG#f+EPPD@V$%
znrIzP0*%Ul%9V+lU3}MpO>^OwXAt+y6GAvsrb$mDH;Qee@_5`dp0*Lz*6o*%KVE)(
zcdH}i#@H_O(Q1t>Q4la7dN3?!akXYLp~cnZz#!nATj*ltAr;2HIzLdF79+Y!<s-2)
zP^ghcmjc1&ViX$N%(H`rMFDAIGgc^oF2~Fj1(SmI@D?fjV&UEACx`c9X~6ALtjgM;
zU*x?wJZ{_<O|67PZuTtWxy$4U{Hzvio4{NmDv?j?Z~5Y~19~YFB$&1|?UTqD4LvMO
zI@_B>EB%fhux`^^OrGrxj}4H$qZE}>CfRJ7g7$gj<vbh#Rcld$WW!ZLYxpRT9{O)#
zMh(kUBUTj?wq3F@PU?>KtZHrKW()MhE61qZ+qA*3N&z`Mpe!+ZDk=&9P}_FHWHqVX
zDhK3CV%*Ji4K>rvY&oQPB3)tAX=J`!S(%!hCQw>cN(_00Br6UNaj$ogeWUvpxp+n2
z!8KETxWBQpeht)?F9Obi6LMTR@d6!Xatp&KynGnA&NYIN;Uhx>-u3p_{3trjnomkc
zwWuk9scy2FKZ7#YJ%#o-Ufb~kAKe@N--0B4E70ShP2I?BjZZ-8l&X;?N2oO}RtS**
zL)MnV?A^cNI`8q_TD?%PgsQ@IP^PNzS;j#s%h`qG+cfLTg{&H);6b5o80zn#1+*kc
z5)6j>4@k-ptDZb@x;^s2jR0wL9CiPPK%OakXU#Krz<Qh*QksgStdjI^E=|F|M7`9h
zW$LcQfO|UG7eZ{MXZmr}y@IR`Y1+-yMyd*^?n%$X4?44~CzC}?j3cz(F1pza5{JU)
zhJy<%L~LJzOjWGv0Pxy3J#k#wzJ_RlM2`)9D4y5{_9XKoV4*AKLCDhQ=N~?P`ZD<K
z&~yW-cIahWDQ|)n89^hT7MBfAYi5B2tnHym$jTSbGb|NNyTv!qJ=oaj6+@k2ifThl
z4%g|}Fk1t%S1>yR*Onn#2Rt|WrBZFGbLtv2RFFr0%3wf-5kIF~BdbZrHHfduuxdL*
z3=1kDWxm?|N?08Un=)%NW9wYJPF^p`xal?{M*wl9`|YfT9mhkJk{QQr*~O6*ZFr)Y
ziXE-AW+v*BaOAnlq0K5?0A~&VkBt1aXBMflC3$%TR<MgeCiy(6!9Uk5X++fh#vq|Q
z*EW`Z+uAy=B{8i6C~9A0o|Z!UfkPDJ$##h5t?r;N*8xvS1(c-8qKf?-_rP^uiK%Nu
zZJW4c;h{~5D5wH2nWB$e|25P%*vtM#PL;Lh7g<VF_<^Dcfrw-^Vk%^ZC)%JgP+&nT
z!Z>oB9JPz+3dIj>CzHvsRv$bq+ciPi5y7kEmK34{YG{ERQ;rF}UT#G?C6IhBub0rj
zR;kWwkRBAs@?s)aUP!3Wc-8CI+eJ5%G!#ZK_phqbluoI{Twl`z$bQDd6BUcccYEp`
zR$`j2NUj%i6*irziKDs@VJqSZaGDdwZusXEA(|!B-jaOywl_q}WR<~5=+1&qHYdKS
zi*DzZq{{)yQY7<;%b^u0b#`75w&`M9B2}^WwtGQ)jtEY&_*Btf7HD$xKuqegSC52s
za|s4jf>{qRiC<xiNoUqS*3Ot4Zd^%kxD9?7$mPW`L~KqHR>j>$V4^AV3>nxCZy2G(
zl$ECEP9M#fb6!-;Y+h0|-!^a-Gk%A9lS&$FtSYvRu1Q6^?x}+9J1l{VycGZ3Okz7e
zn4#8br-j<qDn%o>)j_Qa2|&Id$X!7Mf3<>mtQ_&dxzgEVakY7&{SX%#aHifJ(XRsO
z)jID$Xd8L3Y?n7O{!P%LQ2a+oTMN>#yGBqLeNqsMak*V1bMiHDA}v|-`Ro}}p%dd#
z8SwJWUv95|lo|tF7a|Js#kQal=`aW|X^ggChN150Jv=g*tZvgMX|I_y+3x|HVEOoj
zglh*TuJkx!*)Xk0(Gv!b5}+q#gYgVW;Oc`|!`c@+7fgkOofMbsY&gF4Ef%Rk?oZ8H
zkP*7YB2p@vOn|Gh&n>9Z`rD@$&#|xFB?h@@=19Ns05K2GRUd~%)tj>36j5BrK)8qn
zVlAmsyYcfL0n8k@<!y2a5JPQtAj?16IYOB9E*yKF!Z-&*l8f`j?6bhTvkioAG@)ht
z@$09zw{Y2j{Mys_Ywf*IWP^{hXi+?|YWueV7>~uAmAB8$>6ErCb2>FU-fn_-e}k8F
zU;JxeIi3Ne8M{U_>c6zkp}miCa&B%gTQ@1kRobADE%w+`dn=JiN-Aw~ETmW?^YkFe
zUikGs?dzf4+Uz?7O_ZEY7pj}=X;2Ryh1sOMsSDLjp;wuGV6~T<ckk{#jxIk!QT_3g
z6o*i)pcqUK)XvU!2+z#z1cGY)Wja_Hn2%s=a%agrYzDX&@m~p37h+fgk<yrIVaQBK
zI;=9Ruq=(~$s(5#!k7R;EjC6^fz)fVN-&LZzyJRI-JjkfnX3GCZ-4sn)Beq8_~w5(
zK*PJoaBHT5=}%wp-ha9Ku)q6k{oWul|MqWh-hX}b<@Oy;;je!^_+Nke`0>5n^cY_g
zcYOT-o50&2IMoM%eaua?wV)Vg3Rs#y<YE~a0Z5-yh4vI+-6OKX{em+Bs(<`-$(jmI
zY`nM)(qGSa2vo6VQ?|NFPKnUm1}Ajvo*K59ik+5URz`2PiZs2q?w}jx7KkJQ3T>js
z${2FWbw91Co3Y*H?2R|+PUFfURD&%)+E#A64M^Q}auy(=i)n-o#+6PtwS^0WLH8@T
zI<QAXfS%|7B@C5IY0=6CJymOIy7H07z$oK6IgXUk!o$smtO*!MzK(Q7Knp&?qegSw
z3cLj7V~7jR^|A{D6WQ5G-BIRg^BRde7T5tr3_SAUXEoyVf*R&6GIT1dr5^Fj)8V|p
z+#(&CXC*i+6$c5VxrHi)AB5qo@Iqr+U{yPyX-#y%ejutq-PmEgT%5zP7>09?le(`9
zu+*I8BY&nFyA0gNp8Vz<HeN?GwD;M3CrLX3{8G9K%NZGYJ>p7BI2v*hcRyXexqE;1
z@ux_gV1=;2@6BD`qOhF2t`P9sGtdAvb>xT{w}c7}ow9Q^%x0S99I#-Uo9lrx(AjSd
zG)M~2DU#@a2d`)8=_oT<gL=6T+(~^|iqoLRo$Q!;z0v<r#5=Bb2Zm@B=0&+rL?Uvb
z%@MG;)+lrulMB}q(73V%#|Z`;59Kv35*4v~$V`Iy=uB|pj>fN7VAk7)f`dsMQD_3I
zOzfqRC(dLrUamQ;``5a*QAT4#Mzg=c;O(5z^^fmBECy=6!4dUPi0d_GYi4B2(ua?F
z%?k;pPv&Z}*agbakoQ_$BS$~iPFz+8z$ixeTT1%J95EcZ6(Ad+&+8b@T;t8;0&Za|
z_>s;APoGM*;4We253^N5mx=zsQp~eL{0OlP`i!gV3OQE*J>LkP8BN0>a~PM}E*zDN
zN$^;4#f(n%OW0qT?DJ|hc|D2B0x0T|&}hhx5vo=VPuRMsu&Tj(h*$8rID^^$w&ay7
zmb>HS>}ho3Zg+L&fySrEQQ?n`JiKFrolwl2hj^U5Y?EYj_6nfpPe&&!>MTj69jM&8
zv1Tv)0aXCvn4!|V5vyk^g4~E>0$01FBRA=wJQ6)n?JFpwuC5T0C}qdkl%e6&0Be%s
ze`;SwwIb@*1@%A!Zt8H)V<-O|pg!NxBsMhF1ky2J$^23?O3mVQb_37EtIc<CO~4PX
zH6j%)lTjIkpiPi=uzRZ_Wx{bH@NmlIwVq5#-P4A;CRS{%D<F70$^htN1waoTgzB**
z@#Dn?)MX9dsm&_#O}i?r2dtUk<^YFti3G>-OOMk5GhFG(%KSpmEYx9djshFHxwo{N
zhqrlE6@>RRR`bA@JbX+xF<Zk=KLjS4CG5Z(hdXjl@d%eSsaHLm47++#D%W_la$q7Z
z30s!mP!O-a9-5qD61oOxS+ktm?TSt`W|i(}Hh#xYG5)yJocf*|A9;?@qX!&~i#{4?
z|MqzD(B3g%UTdGsDq`4{IprT9$)Kl%DoEKYou2#qdwW((XD-F=;2~xM(gqwaR<H>i
zqj)-vO<_VID^f!Br8S=}l4t_9IC`vWKAsQ};8MFY%QnxeH|U$W+x?_&yOx0r(MvDj
z?1BVXi_7V3IetBxf}|n6r^HEbK}{{VLd<TSoDNcFu$1FH(y0ND{M=n4eZ<k*i?yd!
zqP1X&N)50hsH6(~Zk97#vij-<FW+s(S194ZK@5JrAG>7=hYe4I>U;`ZZ}eBjj>@gn
zf*|0N;KkR0_>{s~QJNIKyUrcRmfJ$z5ON8IaxodsE5(Gq4JJ+p<rC*yF@m=2&>QmX
z$b`*N?!xn9O+_Xz3v<FICxi$ADTnaa(G3kdR0&R3kY(^=GQzKT4OB#C>FV~-ivpEI
zmSCyRXczHxawCcl#Kn{KHAu=00%6DQp$lWU9Tl(4*UQQ!nBG=yVmC`A$EmD#%-Z8p
z{a(TIBpH@RJ>U}e+1%6765--<vwfz7ndwSL%Jl?{z7L%Ne+$N^l?**zXlo$)T$=*)
zHe!NuxNVm_VmG09$YWgTt+5(z@nQxdy;x=|!^pNNTCuB!<#(A_?oozZN)12a;M`7}
zE;WXm)pCbQSBQJQ!oNozSK74N!dtYJ>s6_MvH$p<P@!-~?vzU_Vo+>5cHnu;zGZxV
z;!0yP*VA{m?{B|{%jt*jO+oeP>s#palu!ccAC~s++IZ{qGY*3x@)Uru_)hfKM_uPc
zsOomueNk>kBtYZN>I$43sVkUfgG&c2q_r_RUzut%PXbO8-e8sg9a(Qv3cLJ~DwVl7
z!h6J%{I8UVkoXC#%GuXXpT8_`KYah?hyCz)NB84D-(q?Kd<~N@JkQR-r~^!_JfCg0
zwlg5EI#<e?vRKk4UuXjAvz^xm8NdT<r^*qM#~gg!BxmlZ^gfAaTCL|f<#*Mp)pjC{
zC*c<pH(X86UI%Acw^pZzdL@>;1z!eKjr?j?m&wrTTy`9^-mdz#=n=y@U%^*nHlN@3
zq;5Yw#+g(Y^ULYXt@bWDEW7d2)L2I&L<AkkMOu!`vvYjNboQ!SG8SY{1!H5p{33dT
zUs6B9Y2hj&Bd;C1{$3gcHk3SA&Nh`OTQsX%@*>$kpS>Q^)_RH(7UQEcPg*dBxGnM?
z+77>@<11JicNBS&OA@Uo=ad29@B(9e47gdQx{t;o<ZTsXkuwub;L(Eb-asVZKv9RN
z_>7e(OzS9yQamUIy&T~WO;*g%Xc64X`+Y1mOk=3@OdzoIweT7DoBDd_)?`$hGaK7}
z@HDF|%$7dDNrnRh&X(KO)A-zS<|S?7O5-QR+k)V2UR_y+=(rHn^G5<TE%DUFb~>BC
zJiB)3+XsAK9}U{p9^biV4EWXL_5ScBV}Ts+gC8J{S#QCm@PDoenG-g$AU1?;CKM}^
zPc$ICB}LJrM9pN5Dj?0AcHz2>>yzyVuAEXLYb`?LrXT@ieKBc|QpSpC)jaWZ?pOiT
zg-rh~Sn+{EsPVB}9nsc;P4TKmKC@kD8umPVIc-bEm0svlmgR1PLt1mKKFDCSk*Ts)
zJMg<}K;o$FKy7zxs>}F{VxtF+sQYNJGTMX7#NnfRTI*{^W1xf7J)U%qc_#mUaVE-R
zJHV&qzCL<@kx0Fj+2WA-8Zl=Z^Aso=(q|C~(~W}OHTY>;Q29RX^qTeCizGn(Mz0Vv
zg}eHM9(0J|`F}osqBpYc$F9~yqI@ZMZe+(vWfF=r&f=y4&C41JK1WYD3V{!#Or!ou
z$#t6rxTllNNF*qouCC9Pa?4-LW;0|3LLTJTPmaUA*wI4sWX(c=@;FUkX_%91PM|Ur
zfEa0B`Vy$Sawuh7)jo1!Q^E8$A#F=SHEM=df$US26Py97D9-z(2v`NJ0D4EPfZKeE
z@Y%remPo`s@ce==Oc<Uk4+kK;2y}x;N>gKbdW(n;wYs6#4JtI-2?Z%PIFieuSThVU
z&FA#>&{t`3fsAYixCF|J<^lKj(_?}xTa<8pfNPk#8{<k=VmATuFAr`5Qg;iYh0z9@
zt;q_3WbnDC+%ATsZB3^y=j^t5B{{Ye%xB2Es6W5~MrV+gb2?POewI7S?}(SkU-)mX
zxe-)t%>(HKQM`>^%%ds46Sgyb?b(|Te?h(JJu^kn3s{YQAxB_VNrr0?NpLu`B9X>Z
z(d4p0TS`0E%P>~4Fx>xtgyxk0xL1x0XcDKH^yzFq-egs6F69|Q1iD~3P|A}ti8_bR
z!2|-SZ5Au0qZ;60KEK>7R{0#*yt3J36+Yw!?YX`@-@KQ=G(m-HyZF}dQ?ltRpxQ1p
zB)Beyd6TJ-U!(3c<7$SIyF0D!YCg2gCKdS!9)>wj^mGx<tmGeQPMStwa`a8;)ibr9
zWZ&RO-i{_M8tFL66)MBDn5Y721i}KY%Jqe8Oei>VNvrIZgkK`TnN~SVaE|#cqYU+T
z%6;318Q=nK7$kMlNHcFVgV+s6QBBsth{`#Ag~_4)wYd^Zk0KWY^z_vBU`|q;ESg6^
zBU*+cz-@@Y$K)!6gTb8cJ5+EZzo=9L*DqcG^NQs?wGjpJ85FY&Qbc53@j4Xv?*8@!
zS=!8;TxPR<qBTs2D3n<Wz`(~KCWI4U>?;n{cC~i3hF$1o;`*SpoMBgNuh;9<MpbiF
zzIZyDEG`*-h#+tHK|T#?Au7@=k3Pe_{%ixYg^rS-6|I0%fi&%Q!W2sIP<n2~vAH%B
zxB;>oe8KRFPj}xhJ~Sh0p?Xj7UF7m8FaEp$R`${(5`zHEUz5~GEzD`8*|5}GNloT_
zQw7okl?DX97_}<IvAWI%f?8T|>=LE2fl&;9<NN6#XL7IanX-@Gcy)uyt%!bIf4cjK
z5b}RN|Mc<ek5DY(o%ewri2@1fC;IeckElCn?)yL{7PyWLtgnttsN8IRysS>IlT?Cf
zy#GIS@7m<Xkz|SLr@*wfW5sT1ZUI#+lHD^shG!L|LIDI&B-LMFY_X)~4j)>w*rTzT
z-QRxCIqn{>Opw|gyJK@@-9==0WM*W9hljsiTHLEG6wV`8_0sqfs<l$p+ji3JnsVE4
zRk<3A0foUK9UrdL%Q`9!yW2r_fMf!Xf!Lgz80FS+y}r`dTO=k}Fi$lHryj$7)xC!r
z8`wSQwD4oK;#71Y;&42kIEiC`Zfu@2l;In1e0w;92jl|LJmUM*g8W=<%|sx!4@uXp
z{o6lLH@En+ov7ZIO@%%5p-fshS7mL6AJ_32))~^mDLlhpps%6{b^_TKKAN2@!Fp%i
zT9B9;`592J5LsC;cR>&s+?=#$s4<x}bRCEmgE+NiPHt*l90Q6So<PC?A%BWX3MaLq
zL60OqfgD;_aLwFZjYn|59RK*^r?;Pwq5KZcny*;)x3|yRH}?(~E8v;daoTu#MksUS
z)eaux><A{bpx`NTUY3i@RaA`{x}V_A-s539rU(7aY5o>&SamB#TnR3JKxpDIe*>s9
zjAEGRS_v>NZPA_WQ8%>44fsWR&sdm2yMVwa^7)<U@<ApBz3{K*YtT|<T|;)Hrwm~?
zr~aOHGgyg6%|ytCv#YH<T=6fcTW-`GSmFR4iW}E6(~mIASd7)9kvH%;+~KnRtnicT
zFj-HIiC-m?Wu1h?X{S)9@nZT6cA_6R%pM(z3Q0tlyaVDi@O+DY`7rN6Dlz6j+TCVW
znIO}v%MN<3PB;r%JnSzQtKBrb5l9#{RVb7WP5Kly5N1;|GM6oyXi7XH4k&@`bd|y}
zC6*kfFA-AT>-)S1tTE}h@h~1Y=fsuXR!UB-lU5C@=G`14W?(K`f)mqI_Q<n?GX*l&
z^#Nq3)LH7#P?DPM&JG;E&=~a%b_l!P$S*R~DnKvBsip!|1U&u7knLDj(58|+Xd2;8
z5#h@87Y;=?lkEV`_Fs{-aUslCX)({E1yB?;D;blYbZL7m!TS6{6XUi(uBu6l7-Q|n
zkehWcwpOXVMVo1LwT;?bmz<Ph8}#?lV>PeF7{UoqPgNy3&fD|Nmez%MSTJ!VC=HE#
zz{`(!aFFf<BO?}>gQvR%1kLF%nQq+0r~&Gco#`z-Wjet8C1$4VHOmGlcMgQ9v;}rF
zLhHPq;bcc=@GYcc!4y|TDhgVRwMG95%6s<f6<Av|k6$3MqWhV8e%)R_(*)BvYu!bq
z1E@jjt+6{5i?QdjfZ$bK&03&_(FO<UA^OnfOX}}zfOZs`0sTzJn1?Q!F{g*y^s!Yn
z^1^L0W%#dAI5sTpYSO->ei}3iw=7ZV9A2hK55BV6EoDO-*EBNqN08ZJZ?q%yWzI`_
zVmUfN_i&v|INQT?n#(j?<K0tSnl;i&3%8}M=Arz|cw#sg&Ac7wzv}Pg?&UoR4k9@D
zf9E$m+R`<n@IK9yjK1Ms8;#1e(_bIDIq0@7?a=EUf_NDshi4M$Suq&qmv|;}X<#T>
z=mJ9Of{2IE4vhEglQY6_eCv;Iz;>@;IpOXCS&5;+h1`inHS$LMgvCm1t#B(YME92n
zTVyGvvQCogeFn#2h76`=ar2#D=%Jav!cd<S0Yg}PRWPV)3f;f`<-^_2$iK$J?6#>T
zK!FBYFpDPh3yKL(pyd1GAl<6K%2ZL{^EchzAlh$sV)v>RLQeFi-E7+P@NSMPeVWVP
z&#vJ-v_0q_cQBIfJ@Uc8^Nfm;74orf!9kWhMiI_Y^|4)u#aei=xslyg+iep}-RbJh
z>}cZ+m8s9dNuwx4>4|$#8EHF%TO6Wh;4%S@YzFTqYJf&(=g9?*RoVwUn`o?6$##s}
zMA7U@f(*mwHCHaSqv@d0`JpL|r5yM}-tff7-llnF-z#S25+WukhnvNn2Viqe&I52p
zF$RySBJA7pY^wko2P9T(3kzH;y}}Ec+}{Dm4_O$FO)_n<9ZAN}Zjv*su-idOn+>^{
z4Y~zCLKU5Ya+w7bN_!q5l{UKRknzE2R^`BHVfhwZcdZmB;R5Ut`#m5DfO5HG33CKw
z27Wmg!OyI~wurz7`QAf)n)r?|7*?<};4P#;20EnE*;zX7tqfE5nnT=-u}-1_q`YuP
z{c5>~_b1kP_k0biB%+2yop$8fv?RW<5Y?lgBWUjXkDge?f}oz5$@a7?84(cmHDsnj
zee>Ks&sC1qm>R2K@0IN9>Jz;k^hiS@Kj4z1E=br}&sq3)|2X*HeTN~thXw}J{c1YH
zs$9d2LT{q!{3L!Tf-7IZ3Ki%60>xbZ{okR0>4jeHfTvsyi$m#2|G2&T@$U8C?m}hJ
z>37H-Y=MkaRmNBl7nm(TrhS7G<x-pLHj?fOYE~|Rb1{xXp%`;uF~NM6#A}?xIq%hP
z*r#@r?bH&pP}H`*6rqBJkM7YGn_3W(F3<@mE5gmEi0yKYn3k}T0X;iZ4th06pV{@z
zD?<sfEyCag;=m~Hy)0IAoQVc~Kwe~MrDm^xetrM)%>se4cOMQYDD~6ppDoBlaZ2c6
zZB;*8Ug#_r%NwYqYBp0-mS7rqU?6J6K|R0TY%gbEH~@lRKo?7{92_fHX$3+9Wd0p~
zHIMD@qsMcqTq~6HNaX8$$5D3OjuB}^%bUHGVy*V;crmJdy!<kf8*)Y;(a3{<0%&5F
zu>EwK9AS$n+m2PbjL+4Wjm*Gr6NmhK1rLBGZnFnoO{Me#4A+1!pQ}gce|$JFbkxd^
zGtHuN#;e6-jcHh~7Ol%iPlr4{rS{u)4Eh>df~h++R!m1p=ZZoyDq4*Yi_<l)i6`c$
z>=!~zK|N8em-&h-!Hte`wQtrpO1z^LrHeST@bCf_eFzA0tNB77TmQABR1XHCCQjJv
z38_j0si_hW_xap-ji|0rv}+>F*0P5a4MZ$IKX8l@d%g6I;&EiH|8`J_8(!ortnVpr
zi=S$mn+(*uj5wLxF?256#SrMw$+|^YKw0bgoDv9}0=}YKOs?XQuadDVoPJ!Xp)f1H
z6TWFU-{}qQx=3=qj!0|l{5`k=rwPtkG(e5siq+9d&<$t6TZ~(CP;n$M%gF{=c59*|
zluSi83D-NEGFagq@rbc*6-0gQ{5GwH(<a9U<{Y|SKX3JVnu-AVC*iT5wT$$_O{d9l
zdSu2+c_Gv5X#3-TW{Z;kv)fni#~zT52+jc0^OUDvq%d4CSw_VbXC#7o-gMOBDOP;m
zCWG6V1Ud0>j*Kl-FQ=&!$bl4*%h`$kk`?hE|3KM}zPqkYL{uNVb7!dbP_H9}4{);q
z)Pwm{)I7qeK0#D|-M@zA?zAeRyVnbeE8hGSgbYu3TsSBXFSseNEu^J_P_=;9!7VuC
zry%|?_m`xpKzhC2v|_&h{6cS%8c4!#7sH8v1@41z%RJB01vtazFE)_PPQE=meS`sp
zqa0Jz>{pu`u*gVS0;zAYne9N<x6B?altpw!wu<3dX&?H+nP`Mt1k-eBElE1jh`$gr
z+_0P5wrn)Y=niBfS0JZLeJ^)8%+_>eMwKt%V!c)!u-<Pbzd}V&@KSh&kpWXkh>FT1
zdxWX;@M*ez4oF`60Fm2;8S2pwiJvP;(XhV&YD9dPdqE<9vD_rl4mp~virH_l>!%1_
zEiW_!Vp2l<lWB>JjP6$40MXlJDW#z>kRrf*cEGb>L0MD2fA$KvO<y3#2H1+JYwH>Q
z^63N9`xt94q6Y^!$p0{KL7En)ms=@c1M-y=Z_r%he<deVH0#|)Zot+;V-0pZ+3uZE
z)nMJh#K3q73vc1njz}EkBpO<g3AXOA8zdL1BJ&{^r5KKS1g0a(L*foBh^9RZ2J~|K
z0_G-^6+qpSBo~#9T1D+@^Q|Ab<7HfBxGDUxGioGvf+SCT@efX8Bbt)hlY#KAY|&#g
zdvB@lj@P%%aLuaT33C)*+Oje@!$}F#VNwan0n<~UMgqO2GAYs*^S2n42a+sqkoOmP
z%#c?g=?B3bx2?W*+C;4Kf%RrCZ0c@zNfu)YXsnw$VJ~f0&lbq?U)1%cXXe1SL~@T}
zW0f3wR40cX8I4NrZ9OZKVESbGpy2hOil}83p=Gpf6}$jqNFoWTTQuw~#&-2*eMm69
zC7-d*yV&|y+zN&&>P9zy^M>OP<}&BvA$BO+I-8a~QgZs05Xd$hbL_0AXPrvXE!1W}
ze1S5p<lu~ggXe+axhEa2+oX|$RHQtr#W5OjKBcM-X^dbFgKFETB~9PFO`$$ny~cbb
zvjs8^z@?38F^W?lfgr~UW(#1BX|=@-lpCYM3D456RT`c1tmeN$9c>z&@z2xU_*t#X
z3`)^<(q{`TSOaIWHJ;cScDaR>%r!aCs8ej*F?JY^1cRcz(6lT0&*mAX1F6n25Yk7S
z&YNqb_?bV0(XT0wN$*qT&M^nTW8jc&NdQ^Hb)a#M7rI`q1H8RDj2DQ0aGhA03N<@I
zilCT?4y~adx{$3<xe2q4reSJRv~-#Qd^UVy5l-h*a1uYHp~@H3P%&z(?0Znjb?$#4
zAa>{trcc{IQ81NpC6{Pcw6qL8I)+`xjE8`*Y?yVaA=SrvX{r6)O#Xq;@1!XWY0O5J
zpt>dTX;x(82Mn3&%)^!3MR}m{jo5}4|A+c1-eTIRz)qU*DEv=4OjchHjV=(7%R&?a
zf-!LN#QxEm#Lrj}cJuJc#}lv+^=>6EV@ofx&b*euc+-h9J77_B8eM^AdIDTD!=j7g
ztXOtN*z1TNAm4Uok5+IGFT<-EkUmND(2X;L^1_Z&)F?K;e~WCOi&%XkWUrgtLl3?-
zJH+ezn@?~5a`(a5%f>cg<l1agOi>OSmHLH+%9=D1jvc#t77|$m_eE7h8@q*nOVly~
z=c4?`4<@mnt?lR;2;NP0ABoewu|nlu`aB;G7}2ro!)QiMu@;*vucBzuP#~^qdIF0I
zsijUgLMvU0?S(dvuIs$1$v0A-Vo@#EH4Wy>EeS^H)^y}Vtbz_|#xB_EdW`3^s|&~<
z5^8{EXYRNA^}>9(Szsr*;U)`8Ms!mRhZ}EnknjbbWeWrC<^V_Acdr=2{T5=_N0Y-I
zhYRQ)r!jPgSEyiBveF@WB%l_?sJhJDO!>F1T)VOT5Rh;-TAU;8VJyo01;|U8Lw{c7
z&__uaauzn_ZbdR|bMGZXw@hduw^>deqr1G+6W9YZbWd?}zf%^b$~~qF*9QeP@^~7!
zfR%f?3)M}MM^MHahu3OTM;<mHb<c|hD0qvb7;1YpVQAjEuumfKD5#!TRnj?7T%481
zRQx^AaFVh;Rg;-^ySb)M@)czLy0a7w0n+zTESNIJ<{HK)a2o3G8@+|;2J&q3d{bVz
zc)puY8lY|<GU*6LaucK`rww+$Hr9>?dHqM(*U(5}M#Xj&I?%Jys9Ch@J+a<aU=e!s
z%@__RSq@V{#%Sia{lwvYu<>eYta28&$iNmp9*Pc@9=Yw;ayyTM8w&QvRHZzd8>zou
znVt^%D%-S@VPQP5Xkv(5u=)>NsRaEmrhVukT4eDHy)R;-SYm}5*;dR7awC&Nmb1J$
z4j`8oAj@QFL4l&qOkP7tWXzKs6sSxyxvztJzP^+f&5nYtuvzbxC}$j8IkJ&IK7Hcu
zFrob^_2gODS>3+quv{%v6R6j^t<Z>*UkC+si_6LoB>i3dl#=;Aw?%cwEeYj@t|ld%
zdA{_x(v$6TO;!s_pI-?MN^&znT6d@_cI4k}p;J>`Ez)xKq_~Gr)|Oexql;mUXM4m@
z!Nv1^+&NtvCxO-GkqvFC91d}p6NA_ZWe?pd0tCuL&Fad<oyZSb!_*z*jc$@l>ctS{
zuHf+ET63ehFExb0q|nc=J%C~5i{-kWeh)%6MLssX%A{I9d>8_;-GlPgQ_(`x2SFI0
zby-AfRVOX4mlGfP`lm~M1ZkniKvtYa7Ke@3(33n4s<q41u=HY@47N|F@PN>FlD}fC
z?{c?R{FsTR9_<T1hrBZ_q&boRfd!PioguU#AkF}+2IML;)2iA@YLkDn)lZ1fOSchg
zT8m?&x0A-7xFsl>VUwWcbo%1Oa0r5njLXB}AO7%F7Uf~iuE}Ht((`Q7N4jfrLVkyD
zk}f<=BRrw_{p}&CNe@u&>?*Ki3NwwEo5FOD_Xt~=bujubj85Sjo`-{+I_W+o&ZKdM
zdO@7NTxE98scy(RdV~tV0{LRI9i+_EIK?z655+oHF|B@v@fAFPdwSqzj;xGVa{6D~
zd!&cEMayXEQ~t>3ygizIn*nS0z#BtaZe`7y5k;svG1b`1v@??tqYt|Bt5rJn8d5Bd
z8(~VvOP%O67l7Szd$8w0d7^1&TFA+I3)vTLX*{3vwKg!@kgI^z2bn{`e!_qvCL~;Z
zj&#z<jD^sU@c`HeP{MP0bGyFXrOXUvqXv~#beJ@#7LJ8nBu!q?&0qTCFTWgK{`@n1
z9vKGo?&GVsuTgGvc*c}ZJ;iwI4c61aA4|UUNvT^XP^1IH9-h$G;?SzUi*u;AOR=OT
zQS=+-T)?nA+QB<|z@8%#@Q7#497}h58AQQJQ~~g>Lr$7f_AI`wfhZzp2YQ2CobVgt
zze5G&G;KnmN|$6&_K|~!_;1_?(qti3|9-FPNf-`nLEHr4n+A)*hr5qIzI<awILLn5
zHj%7BH_!+hC`>yFak}~B4mi)WPqZhmj4OSBjj&1pR+U`tf#>HY_x*EYyz+H^HuThG
zh^`X=k;|N8ixJe|Up(n}2dFnv%s~Fw>B|qVrn?!946p8f(jiv2&hCDaZ$e7h;UT$I
z8V|J5Pr;}oJl8ASD0AO(EFHKOXbx&J-#kP8aqz@(q3_PIsVHxRSR00P#bPBxd~YXx
zXs%BW7n~y72j8=Q0iD$Hda{1uR7%nnQH`9KiPoq}US4QO!YF6B9S!12aC#-t(`&p)
zPG4gon6xR19%Iq6k(2f;&e<8*pRn7HO91s<m}D2Rrt4d3oyZk)q;;!|MT&5P`T;ir
zWB7eMVxWu0p|P4S%(fF(`T}X=m@9PqVm5x(I(W2D4M>fQ{Nj%#22xYX4p=v7Cf#_@
z%UC3sy3+`@g(eGTOA5yP9>{aXit)`ill0c$XT*{@OwUMk^u|pO{P!tLlgPY`T@$q!
zk9X5kq?RbXOS+5zsAf+GlavtiL7!vQ76{H0(j52DbB2S!)e<Xo7@Uoqy~FmP62O*_
z^iDGu$!a}JC0%L_jg@nq7tMa0E+t&3=&S`y0~fQ(J~JR&u#}6t`yc<x;Pw7yy~|h_
zIAqN(TU&Vr(%kWg-#tar7*t4b38*fRU=a1S&omjiFsEXg@T$-9aQz)@-l9|}^0R4D
zsszaqlA{!VKI3%H$)Arxv34I1646(yhtbAqRUmziKVy2ehj4^H3>An~(Wg3NmeAPz
zj4F^Gr0ql-tX#hsL2z85PUkS|p<8*h(ZSP9n^X#CT?J(y!y6{`nNFD0ar->kNOO}`
zJ#jx%6i0f7)NSqB_jJ$@{Cg-)IO-ZRBKL9Z0Y*}U(+`}J5eEcvGJXL^831{7iAzKv
zFml&l&mr~T08(O6;}m-UWReL)hy_y*Aru5pf^2LqE#1xAf~x)2pXbDPAAo6^D;<_6
zG$zhScdQS&o?niqKMefw60mx`7|gURu0OBPuqPjZrq(<pk^;opxC*2(29aY3e)z8@
z6=2z@<#xm=Y~te@a~!*AiCav%CY}zs8iOaNUC(9<#?e$7?HFg>C!><95?sJf=c%V8
z8#PbUJS13titW8BgM~3{^r$(S;L1UIOhs5t#RS_lBhA2B1S=ZE$Gry9rRG@d3KNqV
zMz|fyIl{P7Pi+A*8PB=*@%q7u0)%aME6j)Vhh=gT&`wG#$Ey0uk2y5P<l(=F<Zu!c
zRSn}(FV)lqV;UZP`C5IT$$_=t9yOcZhMHAP@?KFMEVv**ze>#%j<qR7_FO_Tlp+;O
zb8AZh#vf*yJ>sA7uW@Z|D(`{YeZc{2F5QF!ZeSx3r-<W4R_>Hsk_-|;v{XrwQts{o
z2GbWsK@@91AGmkFefcXEOO!tJX-`c5nJ!~i!g-_R{m8YsBiim(+-ADUlkVw7dwnhw
zOdkwBkOG@kCWM#WQpVDVGbsX2P-QM!WpTk>$cWaBN+Bb2r2Xtj`}vXfhez5UA8CJb
zq<wh$pm&_Z;gR;yk@mAA?dLF%3)yQA9}#G)xodl=%vu_19XqqTaIKDzW^`Ia$yaP=
za7*IWLgXz<1Nb|_0ojngfa@J3v`~hOhm@2i@W!0HzW?|LnxW2SH*JzrBELvDXVGCu
znC5hqZ0CAHr{W1RB_h{p<<xV^O_PqzW16-84oUw(-ivW5$Q9!OW+!JP=R#<f0e5dI
zd?w_60Q^(siMd}qADb*Qo~8zUjkc$S7qmL#3Z&WFzkYkSyZaec$?b=i9)~BXaZFSW
zp7W>FU~n;L+x5!k$U=~kFP)nex^R0rb}p!8nQZ&<{&TsuALmrt#8-L2Y@Wr5(AGuM
z+^)e=$?GzP<U}`ylola()Yv2kE0r0=m(BRpB;(w&-nnP8JBWL%f)X$k4wXNkTEq1F
zl*%08qgn*F7g^3^ief&j2B@JJ-b2v>W@)~nD_=NrR&81dM-k;QTZG#Ok!m*C$o<R1
z-`qsUR=mSdjtIBhwJ!I<#sFzNF?CcWagOn_PS8|;AKfl)9;PB>N#8z)CC5%|FY^em
z2D+Ld77+S`p{YHAboA(eq5=Ol%P2Oj?of@9d>v&>1_XUCcNKuG3IRW?!M@RFv2T>I
zZ#PD=I3z9I-M_s5^zm?g_wnQK>8F<;5X!dr^ybYV!Qt}^`3Y?MZupdYX}*Q5e*INM
zPrGc-GHi#(t4T#<<Z(tlN76OJMR|OEJ3rB1I!=vl2Z(R*YgLsz2_V{GLjdDJXQZld
zV(AFcg=+RfYT~pjDlYcFJJ)!dFb?qptXN{we^<8X0zo;a(9aZ+l7s9?(Lm7m7Fhy3
z<2e)r1v~4OQ{!#TUKUsv-27yXHSXuGt1kLzWCj4DC|fUhQhGQ-C-LSzbOHJU_9y!X
zF_<OFF^Um&u7)+A@R0g&43@`%{xWFsOddOSdh~bDRt3?5y#$4_g~NW~tAQp<W7b`Z
z7G&9`I%%f70do(pn?mhi&ez3a^?|u!H>%o*`s!4ip3$9UJUe;$>eUB1`^h{t_;}Bf
z6N7!(XYjiREQtE?e(<;VuV3*>H$C|FPk-Zit0FtcWY{jyaK*KZz52EU(~=km<Pv~P
za|K;)fN7V={DTEXOuJ6V;#%t=LsL=D6xlOseC+9<hj%%AQ%s~#eF+74mhJFbJ2E(;
zF$p<Krrlmi(YWi8w6)=l&aFT?(9ca|Xr4v06BNmwDZjy|3d|M$qTE!yL0YKIF1D1i
zB3|7_cUN=jXlB4JAnKaQht*%DqhPhGlKX!$p%oc?letVclh+A$*ek!38{Nfv1{)%h
zpt{m}3s1~56v`Kj4xC#gj-{p_C8Yekla>v|;u-6LiD?l|co86dCA_tfD<!#x+9f=_
z?L_CkbGsVqPjUu2+qD<|)tKdTi`;muSC5>KGwAG8_IFTUCNJv=Ll@w5bP_+fx$|$F
zKf_Z?W8<7F&f4t;PsN|Kpb9Sx{@!OZbuu)-=?CfJ(rv7*d;Qsjl!1f@CuQj%I><=T
z1Jy>DfY&+OKlMWwbn5;Am(Nm|3=gP(OY%yoeR{TRZDtinBh}J}X{1*jm4UiJTYM7k
z2~=8_rmQYhH(?gd$8I)R4ay6l9~sXpy6ny7liN$EDTQp1Dw5EV!ncu~&cnB<q|@L%
zMy1kH0*gsxoUc^!*YP|A55H6oajw}hXXttPa?5u3(0E@f>qL@bNiDpnYhCThvuznA
z>9ENfZh~oIY`tlXq6eHQNUJMqMLm}|^4H1yVZv+Kp61vLS2*VN{l!VZIWK^^!E9io
z!|WDSh;4t%fg^JT7IasW{(>(^F?prto%V>QpY9M>-<l)5Rr8+l9HSV;Hn7cKx=9<8
zTsWZyQw?`%IHBeQ+So|)$^5_a)i;gGXZ-n}(4U_(PCFgM?T#wHhG}}8$?wV5Z4O?<
z28O&`&*z&1@Ved6WRP~(-y`scTtsNp>A1nrkL~RZmF1Rz#v9NN?nmE)g~2&<JKYDn
zQiVC5oc!|g$A7+i_08bro7X?TLt*#f1ALrsl@vUNjN1%$uXMcqee|(H?PUKP)R$Uu
zQ=7oKX8zn0KvDAD-l*a;7-*OXs+W}zy#kyrt2#QxbW|w_W)IXPL@6bf)AL0|sYnW~
z9-~113eK~YMZ83A=sP5be&w(5);S_$kcNL&JQ~5{NaK*7r)zz)O@ryDEVFsBB^#jO
z4ECNEz#Tu&xuxhPZN+j$@(^Y+1hK3W3Ya6=C0zokCas(r8koHbM-+`8)7@@rOrT$A
z<f4nzA%NsGCeRV_QBORQc$oXJ1SKjSm9lo*r^}pNxN6nQiPx|`g6(<=uIr3*7Kxu~
zkUm654%2HakZwLnF|L_tfa%Mr6QbdaG5Gx9OiwyghGx&~k5|k<J+E_y2$P#uoFn?S
zO!$B>sCQVL{+Ztk*L&tR3Nk{eR=0@L>oDN{0oYQBVJhPGXghB(!n~QvxIK2tAC!Fi
zI)2akvJ$MDgw7_`Mwm)m`G?ox7>L90Ee@aIBb#3kJ>5wU0xYQRf4)fNkaCOOqEVQu
zBV6RFD<1`?r(cS1AjVxdO-szb<CUJAU>YJb3|NrM?ER;|z_|%Y`hI-<@%8(Zl|LLF
zj(609MAq?@2rWM|8t)hS0?mFZ#c&FhaoGYh$m7GQoMY(Q+bvFRt$L54BGj;}DRLuh
z=X0oYfMFNJLu*ZW&JlckB*~T)=fwe%==<~9=u@=otu}Lx8m;`$0CfX5fCN-T#Uu-Q
z2vrqK-NVbwGoa~E@kMJuc{uK@>{%M(DiG%CX{d5eEil0>XAeC<0j!l9(PTM$EX$dh
z7O-xcOGTmJU1t2##&xev$*b<}V~jJ|3t9BTBuGza(Yz#v4uuj~EcK8i%4Gi7Q%e;T
zS9xE!d$fOMTnS!qbwHXjJzx#doMjqDS3=j=h=KLY#o_N%cO-{fcZhqXG38-&wVN}6
zL^_ZBT0`s=EpRqqhO`4rIla5E{Sa5WRf+|ry!OI!A<o9V1;0P4zFtqRpqc?YP?_~^
zitxWdeQ6U4%uI(2PsE2fW%OO0*0cafKQw&2mCD|J<|kG0f%cfHDLsRBNvP}+Yd$zp
zx(ug;j8&0`g2fV~DTR$%Wf!V%??UzMPB8cxQSLxIyrozK0bxG&DAxJ;UK(|rS5d-k
z`(kkoe>UwH+Ov+pYi{vKCk>ch%3H)X?lz!~d?oqsYZlb3A=VjO`Qmfxv;<RkRak*a
z9XV)_d2zhAqE0?Gw<GoU(d`t=R%GO)dnA{?P`tYFToUe+w7inO9X7la#RhsfU1G;T
zeOr7~4_NOKD(3{@k1J`i1Jo^s*Pvo5D_LD>=|s#dC0TnwRv`OUxG^!VcaEe5Dj!OZ
z1|-))c3(4w`caNTJoY`wywrv3fmwHiV7B8&I-R!b4k9<q>FJ^PaD)dNW<-bb6+uQ*
zN{?M%R6lt%VI^2Y$`<7%5;wXt0}ar;)Ra-c;AXTC6lj`JC~15x7MGKO|A6w^t**yw
zRj)NnZ`D}bHs{{hQr|i2D3Mu<2cg;al?tXZOhe`a6g^^CtTdEk8R1|sv`E%MUg?1K
zZVks&hiC3+8&~??v@t>cXm-0&u0q^uLNM&nsC9j`CPx=&qhyUvgfrFqOapX?#uluz
z7=3g6NvyuYGK|8ZCLB^pS}iyhh=Umg&em|NhA!Xz>ePzh3RPW+$C|B~qvx*}jFXll
zo${QyZ-2XQG@l8k?%GO`%g(8{hOc!m4yT?>R9XW#8b~!dqARXm5E6|0YbyRRAJ(AZ
zaKTH;Snz}Y7fGmzbtwt8P>_#>@bbAN)StQOb4jRmzS9>PCc`cKD4VtDfHke|2{v7A
zus><+`C-s)()<Mu)B2VQ<RF&>&V7@jT7d4-M2G8G2qXDgeW1)BeWy{@(rw}+pq$oU
znVtL>f~}(;*E{&8f&1PZ>18?+@a964B(b#)N-eaU9paucvEpBZco!v`YOXXr(=!;h
zP(9Ny4ABe9vZ61q)cu0M@XJp%K#`LaY=_cQ1!sXpizZEFM&DS)WKXeYRpPbwZkdAG
z)pT~Rn^R(WFL8vBc1@QvCc<&5;~V`*C;wo}Qit5<STa_Sdw8b92YNpw&1lU6r%>Ln
zC&*C%j6|V2I03?ie)0qIkEy{`PGmaCdB%B^A}p}K3?i@wAeAUy#x$c+<A|mBjcJEA
zmUJjSFnmssLG}17G@T5U!kB-9+!ki!qiLU4S~;Ug=Gt^5I4S}4K#}c~KpiHC&n8$G
z+?Rta6vA6J`|WJGSfKvNVQ>y@77t|-Y%m(2m54cM%rZnB&t7h6a*{&YF4K)tO6SZ7
z;ETcWSaf@xuDF6|aBNXT3T;?uvGb9v54Hm>cW}COExn?t?6iXht1tD77iN=ME7Zqa
zM;O_3npn1TAQp_gdslGAI-^gS8KCN_(-%9B3dwL_QnU)Utn3T)F=$zq2B^<XZ=3Em
z*BIw^FXLV1X?LWL?k9nvv<%-`WLWFuD$OAE7K)kSJZ+qi0m$$ND0hZ##{>K8?QY1L
zfVu%24>qt9?!SU_V5@TsKqtB`l?nWi<jVZvPrOy+KK%v`@s4B3|D5js#_l5=0ZK<R
z-`&FRdnW_5NzVElXE(}73u5DX%=w+o+U2ZaF#|Xq<UV{tk*`hIFeIN3hvK}|#E+hR
zW~236e(bhpo9O@xU*3LoWdYTIxv!L<<r*`x2LpU#d0d({(Wg9U(<9U-+k!TP+E$eg
zRCJI^Ti(<R*a(>WgsMP9h4)>s#>{QBl6D9_Khwu0MJGr(OdRf3;K_^$!gt8viU)w8
zB-z67y@=WdAN~yKm+6U&;^OdOGdwrUhzeeQrAf(qlm16I6SBbGlXPi?01=~VNV{%w
zBzNcriR-E>J=#*WGV%>6T*3ztoU74HWoL(XTD>i6m@RQuiNOtCWY1J$Bas06!r;f8
zt){-g*$3l%EJ6T!`pwuv1TYTqHWnO}xpx-}E0~61B4Ods|40vVS<f=%I&%+C$;t$#
zF(+95s3Hk?A)l#tfYdo?B=Ypw>geDwp{Gc+bjF83Ye|hr2dD=bXOW6&m1gJ$r0%th
zyL|!S{F&~Nd~4|&T&7>ZAh@&0%koo9ArL@4G$9<0io*uPF>&9PEs5k3(+BKwo_v3`
zCDXQlfgdpKx>h>E+>dtC%WMZChyevC_j@_7)^@1A4!ToOho$u7rz_bD%vA|-wIw#j
z1ko$FyVP7-3kat6huMiLW|<G{z(Q+*YVWizIf+16?E{$5&Z<Z_(CZr8L`5x14lsR;
znzDd7^t3U#1*wibwzKrIA3optX2F8Pi=)WBJifAUx)JJG#u8j1H}LY$huIqT#x}0K
zzmEoI6v_<=j^Bm4kesNV`(m-><2k=l7VEwUM=H;}Om`4_2Hsq^AS9@n1z)QZs^%*d
z)Uo_m@eNQyRb7hH&=^k~KL0_n+t^VTyDQ!l&;G3J{pCA9CxB~Cy^dU_iLPWNgOy+z
zuguv$Re}ZAi~4usHH<W;m?e*GP(nX)y{_V>I=#Ho?$<zqsE^#)HecsH<}z3~`$-da
z%!O8A6Bk+>^VjHXMMO<>;R(g5AP_R{_P3iU4oqRA)Gj2TNdE|7c3el=mVk`#mPfhr
z(zCPArHqObt|0jtrl9LxrvRz59R?I&NCA`Xke-3HqO+kS4KTkrT**A4OuE#vSg~>_
zn-_1E?=~Oa|Ex*Ec`L3<uA<-xrVFG42+@Q5%mEV3=H%B01ITj!?Z5qs{~r!MyyDQk
z5JAGxga2-EPZ2uyuniqkgFnJ@ZAYFm_!uxx*%Lj64`Tj#v6AB-uGiz4d6?C0zyVl)
zBnDnjK$Hf}wZ5G?`=ZP$z3MP)15!!mO?W<jHiv^Fbp1-q0c>H*@Zj!d9$e<L8drL7
zVtb&iDt-&5y<(De%Xw6wynaD7leVXnp)yc66kIc7cnke}rHG+!w$j6xvKF`C2jrH`
zlqDVztjLgsG6_Zpz&sfFr3KNYCiAFct?7L#$68kfDO|ucL7ERsv)1v7s$u%}ym3|&
z6y4=)7u-z?)h#hzV`ii(M>}}-lwUiax(~t2w1*PfjF&VHaCm0R9amcLFhn7r0E|_C
z`PciqACZgmK8DwrtJ+=~ram?(GhAA1j48-Ij}fP2X+>^_D}KjPyntF<9z4fO#jre@
zSsH#5U6sabjr1erE~}<(BC`mVfocjn%veCX)TiU1hJ_PBRSTw>MjgM40$0c@jq0<x
z#8Ej46&Mn(L%PkdbdQWDc4~Q^`$&pIhe}kyLK(ru=T49Q4w+6R4DOsePRN=LGO0<H
z1+74q6#QJzk>cEz%Ob1f_5ooX2M3rhXjl0?r_!-{KMr0C4s!vW?>nM(0~ChjEl7_1
zxFW4zzQ;X{tQ_PLx&nZFWEdDk-jT;J1JO<-0V|@p)WMXUTo<FG+%kuCV@+_1S0Mj<
zQ}^^zJ=YUyy$xNj_fSn;zkYW&|J&WW>B~27{sMnXVQmGu4^SW?co|XXoU-$TXB+%F
zkb@dgJyH-gEmSqeed;y7W{?)rqu=Zw4E|~0iy<~i06wmG!GpmcFn8^HI!`ryAn*e&
zsXfoGz&&rsqu47Fk(f4z&0@9bd@)^7Yw_`B4IkM(j!+acrX!%o!UF@0jxy~cE$Hy!
zs|vz(pu$cUJI7~;yWM%-W;sYmRt67>@~*HWt-xGH3md#J3U$tw*$PUVvpO4%-q&={
zD}x$cnWhu!PV!QTNY%|ERut`MllCNSH};~_$a~WP>opwickr6zpPrm88D#U2l_RIN
zr^rk3$)pH6gGmnXBTk3Lu32@_BS{RH$8o=!OMFBO2}L9})0O%8_qSkvsw;gg)kh4T
z1nUiM3PpS@qAi-3w`%b1017P;8;|rUMFOG=$;PjT&9jwN-_vfhHfsPx_iKDmMOmSv
zbftmt`3$Z&uY)U2)DAt`9<U+mGL+Y+K-av!_!Oq-P>e!-<oEZ{v}JmU2g9_}Q1a>^
z>R7Eju9<f_r*bvkp-jP>pWmy<5w9>AY`VT&^K^!-V|S&628Ox+1H7!{{7~TBZp-qr
z^Yn3>DY6hln}V#IyW8C+VQ<r((3ctQnd^!kH~378U7b#W2h-`V@b6%~5+E3^$|hT5
zWNE>fRF-BD_fR@plq#zZP}8c`?CsK1v!Mj)7Gl4~T~?m+-*oMJ#4SQ}RkS5s7YlTa
zri`xqIvhV`nD}tG|6H6nzz6`@Es(1eX95coD$9rkp87#*=YN^7jj^XS&}K1&-ZnCt
z=xYodRIA!YzO^hOy!Vg`kRz-FvVx(HV+Qlrf{aM-u%Js6=@2HQ+%LgKwu&f?Faz~c
zqvnV@I){HGgy^l3b2Vzq3hZMgbx1X271oR6LN2d9YP)FrB*eeO)&(I(Nz5jFZfxnQ
zgTFLOm-zMKdb27rlX#0Ql9RJ=+KKQR3V65E@40!(;3^*V1xPP5_K1$At=CiuQCCrS
z=y^m%j3?#KJ_6s<%RdchJu0bGmxnsi!>!la?xS|B1t|bbuhPO%ayCyX6j0&eum4cB
zZ6jJnUfxp!pbS=#DL}KkU!IZ%Z3jfCxDbU(k}%R$wAfd}G!$%OSRKS%g76$?HB+a=
zYI=Nc!vz=nrN4tr40Lp-3%KtZ;)cfNH9m_}Yoc{w;cCC90qTPScV{T%L0dlasO=Xh
z?vv<x2cmg1#g66pM%_KcO2T<Ba}rffTE!BY?q;)oj%CMrtn>+`SSWH)gEc^r08cFF
zfqikMfe0QU8d_gZ(ry78o!z^b0bd$Kk4cCPY<={4ZZz<MKUk_C{nBeGWK<cjn@4ux
zhCfi@VBbz~mb9xw?M?!zvk==V!4^6Lt)f8cB%RZK1Ir%RSjcxvX`UeE<(6We>^u#(
zZ@&_}LXLimK;Tu_1aKUIH>gjX0-?LW#8uK5Dxw50FYy~>HOoc~$w&d{Jd}NA6_M6H
zRx2D#fUrpQURt91dz1^Xg2aK~Sx&2)yL|c$VAGG_jH|^BTva#QC1RHsES_7?9$>r?
zR;op%&}(p@h3cu9$zv>czcLH}GSvf?{`3fA*8dc$yZ=j>4BGahRGh<uGKIN`Es||1
zsa6TsNc6Z+)p@<obg2bMf=tfhRVkHw;Cixf$-Phyo?y!_pO_7$4WUhXtU8F6sw|r@
z4@%K?>^ZYD82xV{wt2>li*wD|3IuffVkPq6zx9DU2WjL5r;XfO!wcbJjxbT1O}i^|
zdZSblOdoHnft@^u70dN3vbH9y9J_SDQdEI5TxK(p^mofEHZ)?_tEWw{+}(VKT_Nlj
z`gZ6K<l`hcqkDFDfr*s5GOcgNIY_SuVNeQKOaDrLs}ue)XGZ;icA@EUI2%pElkr%W
zi}Npb8IDkP%R+hWl|647J-qm0pNGRQ4`=xO7aueFa+mWjcX|BfF2jp2_c{9wqq+DE
z!@(SX`DK{oFL%N$f4S3e_2p^)a+mWjcR?DXFQLxx;>&%`Mqlo8@f(JNY5wwqFwI}?
zglYbAr{U!nzkc-PF6ZcCIwZ2L=HHq{KJke~P8qO|-6p3|Poak`56ObRXhG(U!<hJO
zP*vAdQ6YwL5ReI@t7{`KX1dgi3qJqCo!Qis(_)V0#m18kssaQ93{H5Sx881wYJs<#
zPDD3zyT)or=~wOMY2h3W{f@}^fV+W)WWDNS+iZaPAlem}s0gV}aH2@_aQ64-r=!QC
zv-69Kv&Rodj~`#${r>Fn0x75}ucndou8=yJ_mrMUDF(;Ciu`2`c3@=QwIcK4Xk+L;
znccG1sp}CfH7BJvp0nbHN_o)~7{5uYW%s&Xt1tqi)Ob#o?3rppwk12s>AeaT6U$Sy
zX_>_Wxd*4GZH=oygNn=dHR6ZqHKqOM?5KuR%$#g0>Z28_7QwQ5W7eFzglC*_5v425
z!_t-Jq4}PX^TgK4lDix3q_9pfy-<4~g^r$9+JqM7IJH}B>2v3HvPXuju6x^FKLYzK
z^v&8hG$ke>V)#6NUB42v>E!Qak&h2|_n$tzJKQ7u26X^lA=MV5r&Fm9A|;Tn%(Mem
z9;-rT5h~7pjZ_N~XO}Z5B!MhAF=9sv_Td$UIHy+#uq^9v(t2<8fsop8F}}Uta|ZSC
zq(#odM}10{XVYcI$t2?9osQT0+4a`q<5trxw&51(5zSK-wE<Ft9-(EShzLT+%JjZa
zxn(;%GkIJk0QOLxK(*qLu-wqvVlcHZiY9$P3c_olninn!2eKH?r`u4_44=Sh%BTbA
z@6~>}2;#@Z(k-6-a|L93o`e4#kNbM)ZOs>=oTMg-PZg*ZBO;ei+p5W;NWmD}^K@z?
zkxPD%1w4P~cuJ4NW2NRD);rRR&l<z!g_JX>!r5;++Eucx3B`246iDxo4IH`&28f&)
zwo!02d7=iYe~1{d{pe``nPhOJUDK2neKtW}83b10N$y7+k_6m4v(4g|MA6r&JO<&a
zs1<bgLyKt_osMnNI-xf}eIaK_F3;n2n7Vne>dA?Mop&i1nq+jOyVUN@%fH<nc6a~t
z)7`uK*Dv23ws$|?y+#w_BzUM*eF`9mP}J4w*yw8jdeVqM0~dWsbZ*1A@RR*lky2Wd
zAW$xn!04<^xn#MI=HLKhXvo1h_BkcvEdn<1f2YPZqL&@?0Ajv-*!4x06d-jkM7f(a
zqsWmowDRIOMZ~fe%Zvyvllp~_%=bG3PZ<ibdj0Ox$KiP^>K^N*QSb$m-RO8?G-M(-
z+fAPK0nFa*LhvlXjGQ0WZ}mX!^E_)r>G;7>k)eb8^Ag@#7^&re2!v!k@$J=lc=PbW
zDvU$dHY`fh-R>^asltbxSrjKM5>Rl@uBQXOC|zkz$*9Pd1-@-!H4$;51o;h$jpGD_
zTe`zU#jQ;b(Xu@TM^PmWh_6B|Ah3h=5nsd7(nJN#c1`sH(`;C|G+I-s^C#bq+?3^o
zMszrc|2NgmZp=`HtXgY9n!&=WZi<qQoW2qGC~T7nasj|q?||S|rfWGF{rzb4@bnS*
z=EwL4^~KKbzCAmA3_c#3>%tKODGVLK!F%67DD>Z`!ma?RdXIo!a^kh<+2+`DB9uT)
zUHW`%$$Fkkh`OdCgjP%)MZ9h<cPgb0E3W)4pi;I(yaTq#qXJ>yKxd|FNK^+Qj!=BA
zXUHCgYBpE^^Q5YqwG<UEo2$y_FbPr?)+(D$&s(qV3Z(IyeUBAQ=xR!X8&~Q?;!^!>
z`^(iBTnDSflT_^)@cq0e(M<vr&qo+HYIM4cqgVQcGPh6;!fGe|X5r~^CfAcPMxxKt
zgCq)kkAn5~)A_=WOL%bx3uwCcq3d1U(2d=W)lExa9)Q!*ku5i=r@x1!1sea(ChUMU
z1KMj&q<Zr_CYZX%%2&?$2_LFfjfn)O)}aPFDDjeDBpPFdIs6SjE+vjH<j9s+l(=;@
zp#TLciW0DtwuBhu`D~%eD5`YA857j)kY~bU-g?=J1XK4+V3-$zH4hidOPn3J0v&P}
zio-W*fbN)%THv{t3nbv5Us}{CC*~WA3ez0%LGUC=bH-~V^LT(hod-iL6|Mesgz3O3
z^udEaQui?mJp^nitsY{8vLVE1F@rc=r#XL;GZG~v&&?B&d@DtWQzN+n8isf&0>7}u
z&pZPbs5Mz9e|;{U?SxeCRYzC4(!)%QjmS<tEUNF;AU%!9E=NZX<OBE7ZAuu**hC?d
z2xtiApfmJT5+(O=D{aZb{#L`%ci>=?V`O>ilPX~`an@|-T(K0Y_9$ulyIt&w?>`{z
z#9u!Bj6|rwb%=2{Ak@eXDZKV2YoqH@r(#eZ&RQn-Z;qdI61&XR0qbdQ9+R_q?Ridu
zl{W^%%v+v`DjtuS?sxUnO>*|kSv;*i;diw!ZgIqOm<?26fjcb2{zc1;h*x)rzDEQB
z1sV~BWyRi0RP6wDi}*p52|aGY$6?lmho-1<rPGG*^RG*^pRySldK5l}-VlBxL55p^
zFgh;)P@YLXvLM!~*`NlK+edb_j}|uwxtc9Ml2bja7b0uza5J}2;S}vHQohXqgC<ye
z#vRc8IFDUsttc~H^syx4MIO1~pvWEP5vj(FhWa+HY&I^hmlIT8hB64z61(Ni6>Bl%
z55hSEPIkRTeF+3a&iCD~VU{~Ta*Rsw7W)=M4rM)dXH#H@d$oc2UieXtZ%{j2HM4&z
z?5MLD>o^NUi8K#NnZb_DvJ<OfmJ|8HhGRmp%KcD!DP+?zasiRDu`POOF7^;=+rb+u
z8YLJ}2)~`e+~M3n5d}^?Qass7Q3sqJi=o`y$a@J+I~H{lt|EL632P{O=su!n>*f~U
zSF7c&y9?CnTL4)!#wj0)O>Ehew$>~Ru+U9<3Tf4<5ECi4WQ7<(1$*hqM`rS^HkaiV
zRxTkWmW!4^ROF9d4k=|s>GW{XIJ<*M14)w0X^}~Qt*(yO2`Js;c=yAN>g8eAucz=j
z<+Tjj?ig(;x-G4nGe$n=1u}cuH(NMR5X3PIM?h6jewA?*)o&X$^PD%H>=THf{TTxd
zqDR}hxV_$sYxH^HRXs|%dXx^VI0m`vj0XWsFR?QWA{{cF);Vh*Giw^NkXRI%)SDf)
zxu=63OJN0@1oLq`ojO74tcOs)8lh^_LAOcsr_p9Dx~DBH8XUjz`cai8wm1$uFpH75
z*AKWo8AZ?kb2pQ;!C?-?+z`lHULe*rZxb)?1Of5dU3V3D85=WYVxLiad`vOb_R`!)
z0&!24UI`?@a`zCC+y+x*?J8*Tpg?G+&iq~zl4&hrl18Jx)N^wWeK!LW@SXYkTW}WD
zVkR~;a1BPbHn`)?!8crkEjtXTE;v0uzc@XA0=2=}@N9VZ?eJm&-xIO*DVe30V$avM
zu5no1LKw#bFZBoKRiRI#1JYr;KHP5Cj?f;+4K;)2(t>KCJFTwt{8+B(6)Q<ee0Axy
zhUnvjiteh@x(nAZbuZ;h`1ISvs%9p)7!3$W;fRb@o~=f?<}^YJpzGht31+Y0sSqj8
zTKAih7e@t({0Uis5|Qd<i{_>9nlh)UbBU=|U-4E;mtBKkJJ&v`<XSYEE=Pyf7|HwA
zmlXKs2m76YWZ+?k;d=*~MqXMYm{MY>tfceRc*CQZeB=f72dKArq0@LvP~9FhQBp^{
zR+?ms;AO^&5Vl-MacO{(j?Dsy+U7E+k4%=H7ODp&B@8pnk5PF8AvrhW)qL>vo7aE&
zc>n6h-~aw=9E!Q<IO927x9zI!^bc!EITEcFlQqfH!pg$o>vM~yNZ;fhP9s+yr%UyK
zi(910+Ripv>i{od-E0{G`olI8Oy3w=Bbe<kS~1D0dnY}>na5gR!Q}_P<L6dymvX77
zZSB=cn4VM&rtN=LX1Rv<f9aCNFOGIS)%Gv6{}Tkgl$*K0V#i4&jxGk;Vytg8>Ows|
z6w)=MJf74vu*eDz%NMA`5>+dU@|FLkYFUOt&L!or$;PD+OLV5pqFl^Q4bx2bDMUv`
z94QTi?gA#VDQNPbxpq`$OdR~HF@LD>0P`GBaYM!J>eNFBdVtHd$AMek^WF%K0BNL2
z=$a$$wG_cX+7fKFy(mGd1tI!KkC$+%m}e)18o#R^Ha&^|a$DkO7_i(!w~{9Aex-c~
zDKyZ6oW__?<+<J5GHcOzyJU(z-)Vk~cj0<iZ1O5+<8lvA_&K(761e-pS|w6#?K6cW
zBU>CfA=6WNbRtIQq=&n?D-<T>F_qnC#=g{TdQqael4vKl%WGf+eH{?3vV3}2PpAsn
zM6xEMWoNyILV{@uG`1k3o+Be&>doq59<Hw1q7rZd{b3PuK~g|ZFE-=3j^QI6VOk~2
zkOJ1r{c;~06J93&E4GyQ<OI_|vG5V&OR-3J@VOY@kdicfuL4kVj@)wyk;F5ff@`X-
z?6b214q=(lRbzhl2s;K-Lpbz=#vv9uxK2L}ydj?0WlamDESWE+Nc>DW2`SGZPo*o3
zCShuu$tX^gU|5fK)L1IIWKKsQOW97Nc_-I~EdZ{q74kb^Jrve%dWnDu01t2@#Z%Yp
z-QOdL8ga~SkfCRFSW@SuUw8qu&UBPx!u}<&%=2oyw82GirS=v_4jugP??AfjqCs<5
z@O$nh|AZ(vqGDY6uKK;?i5jpg9hVOR=#vp7;Sz~E@JgBopaGd(BWxRn0k(MjHUM$;
zr#}s_K?ZPA2Jie&KyT{)<1SPWT%x4l%XdHCefuZq$5AGe*vBEWTRh|MjP>X9DcZs)
zz~}v@jvn|OPs*c#vGTK{*)C51Glv6x*%yX0{LdT?(DJjxL7>5Z;#%Px{OoAJ3jTjF
z8uBxVQ2-NBaSBMSAtu+f{^SUu<&qpl>kBytYpQ765n7Or<0EiAgH{TusE{Wn^j4Yg
zQoaXEyLLQvQx~ppa6e|q`$2MzYDmH-_pQ3^q5*#7@Vv(nED|Q`rVbf+VB*YKZO$s&
zSOdzBG3OY!v-w5(QgA_*{HJ95OG6D`9x7(+Za7AYj7`VWtGR17shkuD1zzB{2fep-
zr03}jnd+T=F_}F1mc`*m&0B!<F6t~4+UFrtI0<aR{Ej|&F~}623%mgL&=crW^(Yv>
z<!W<1$N2*WOjC}Cn?f-QCvsT(=M2s6sQf+2L8V$ZTMh3jb^f##t)7F+EQO<ND-y^)
zCR94&)~=T;=-Re0M>=ypl2H{^z|h%?a)?94l<)T6Tm6TU$LIj{61|wku9m30QX^#r
zQfKiTg;$Zkn`~K!9qB84D4Z*e%BR1&E+41oSIi~^R}EIgR;~el7lgog={233uHCOM
zt2N=*#QR3O4W!QL_u;5Vy`1jM8k>}#tlvbbSU4A}r~rqxRmr-53FaR3?80O$X~(4;
zPXP0^Z-VnL_MZ*TzsSM)+Uu@5u;olK?Y7Fj+RXrIX;}ISE8mfUa(iCEtTsXd9?o)S
z@zh*n{&~NtEAT#<y1W6!QI_Y1_Ga-kirDq%#2!Um%fbOGvHgfu-r0-;(|IBEL4UG}
zXhJA+Qzj4B>O*o`=bq4UQ8%e4wMH;>T9v}pgl&Zc(Lyzai8*$~Hm=8EQcqf$Bc1es
z!)Co(zBrhphuKylpF#b4-+(FAK@ef0i!sO8F9nYW&JgBa$d0!tTNmkldKo}?`oIkY
zj9q<4&OHJK`k0>ALHd*^fOWZt<28yg5t$gnEgKkpZ0PY>(zyztM+o;#@qBh_+-F>A
zg?OmZ;6Pc8k3W&hUU%6^HY|N5q*g~tAxP9KtR4)`hnilRZ3p52&8B*a={H9nxDi(g
zJMi8KlBI9p-8a0L+`YVag&;M&t`PKKkG8s{o}OU(*svh5=I4Cd>Y-bxZV7zHEz?oT
zxJ8CZ&o_UOD3BLd8a+J>fGJ2pbAtaXU{e2rq4)N~aR1b!)LO{sC<L{FkKBVqH%A~3
zk3uevLLME3JU$9}auhN=1?b=D`P6<XvZNe?a1#3O;Ux4!I0^j_PC`F~lMtS&6R1|{
z<+J$k(xO!iE81q;8?={!SAt&{G}drYK*2o*Z{jPN?ZvG-GvJDL5sU=P++6Z`WqaO^
zj<mgszXVhF@^D6Wkw?{L?*MfRNdO}y9vO?JfSV9^LA#*qMP36EVQet|XZ{U4%eI#k
zKO!WoeQq{&RY3>!bZ-xc1a<N*bNpbl#$e`S9upL>!8|xMmXV!PCr{iH7IC41s&u*&
ztIkAPxC=>*m|rZ4V!&a@XWnjCJJXV5eL$IK^A{Aik;DofczLhmE|lbL(u7+;9pX49
zBsWrqOIh_RD50lh$A^H7QE{nrg6cjcm%dW|cR}Tk5LVmS?cOpF8wG`XAsiT3rb!fr
z=jn1cY6X)Trnw7yjlvai;K9uKXtE#!mkiT0+(s{8j|JiwNpVo|1=9w@mJJ=P!VotU
zx?WA5E_>ve_s>$&2C~Z~+S(T<kj5o)=uA{%^-2*V!PK2+dy&v^xp{U0>RKPb{eAM=
zBBzk2RN;4W!W1$xLzS>934aCAGXe*Y6TZW@)i8A@%JU#Zj{E#mbRf753bjnXvcm@I
zX;WWKliT!0exlNyoWqO24!jN<5RIinPJ3F_FpbddH3%vCFK@50u>P<rNy~*9c;e?*
z+dgE)3n3i~)vJgF{I3R`7R|6HfTD6DGGU7R?7SW>SQxVRR{t3<oz1VuKg?(FlHbp#
zG(EywQ!SG<aCAO@cJX+SIzuoWA0`JVD86`?F$fpf*)SP6lO*3;v9+t|{&KO}k+t$4
z5w_8`>!WsvliVwFE=J6~9WGL{!BJ2qO!9n(i=1y1qE?zaz#4Bh3Unl!GgQ>6H)IJB
z#tEAd(na$%QuPRNl_ikW(u0Zjs30?PZ#3F`rfSev9pG`ayd*cx3}`R!??1f$%cuK0
zFpVcCUd<eZElK0`qNt!J{%H|cHb2Q4Wm@m6?v@sLl*3TbMPCtn)toE*lN)C{gQ>e^
z149~_)~L4`x>2tSTds?glf^mFpNXaDkf+&fnTUeaT*Q^WK0ctV{*3HTPF@(UKt{t-
zMqXDuLfM{Qg)n-qXs_6tVCs&z8`^XzKX&W|4I~Mc-$B(F5d%7IpwhFVft7Lx7$JWO
zMjG^hO=0Qg+=ph`jH_x=f+{2bGw5@3_+?of(Wk!hrGBD<>x<*;1MxnV3mVnE0;*e_
z5qn6U<?Qa)`<g#|2)Qy;O|v=F9#fQz>+XjGBB)t``sMxID@d0(9Lzc|Z$Xb*nD4h7
z@PB>sPf<E~NgcpmfYKfY@U?Q{O{$2nbua|@oT5TpZqyPd2I0!8{v;I|oxk{>sdu~G
z9CwKi%Jc|t5~QDkb!YJLukSzH55R)<Wmo`@#0(4IiV+c=(GweT_*s8ZYRL<KQ7O%N
zQ{yd4-Zn)vfX-v9MSP61#Zg&;I09lh<HlQOJwI0pxIS|Slb#o}mZ3~sJ=nz{8lj4Z
z8*QI&t~G1A#e2i?4T_wqs<U6K4~Y|k+`(y5OYH}aq<yTor6RB>y_0WG|Ni0i*8X}X
zhSKRASu=gJCRG7!+9XSr&Q-+Fj)IZ%QzP<INlw^cM<pA&S2JvYnkIjcpVsxcSHslZ
z$N=&KjG*aQT`m7SGInHBHfcs0G3=tU8FYYpxP;0v3=(h`^O5+-ONhD}7D|qkVl=Bw
zk$d!VZVJ3Uh;s)RE*!h?1rl4%B=}Wvadij1GcZS9p^Vdj%nZQbBt;e_6_T2jkU7k`
zD4QnbZDrz3O;TOq8}Pu0w$US!h02`>J#!kp6d55sP5aMIp)#Rr57hL<inr@<{@8cm
ztuTN+K>A!J+HS>s=AEj^IKSN%gSqcRLHK-&tPBxGeGFjSjX6J8*%4u>fJ|*cG+;WF
z;H-_3B?eV6ds@gw2xaNP<pQct1S7Uzua-Dzp+!Wf;@~0P%I{tvIm;~^CZ@BwwiIJc
z5q~^RLE$c`gK~jp0}5b7!s&W_gQJS)xTNvtFaP=O(=U-JT><!PN3Q1@qIVVM#Ye#}
zaKVc$k0|4wuXD~&60Ikw0J{ys1=iXfjw&DMNP2vUgBO#WWVfbWi($+ky|%hc-m}C2
z_QS~p#@>l6mHRcEL@JWd-$Tn3pd#|4%8}j!*L_(tU}+y*F`)W!IyJ^q&!BEXNV?P~
zgVC@w^kkj~xT5%*TT(dUv)yKWZEhRD1zqWWt(V7O_F`j#X|UBPC^?*lyk?z`bkYMv
zQ#0chxhQhWb{KI)oUo{&nbYVGY#*oDtP5!7ey%@}Go~FedUfe}ZOH1X54R&r{3ONR
zJ;iy}<;T6bT5-CsF<<w50~1a{(5h8)P3pzCT10_u5;x=wZ4J}o6XQv@_34u**zY&b
zz<LeggqA+v%Xw`Yn`s|h4>j8}#<07YxFOmuG{U&;5`Kqp#HRevaXRepqlc%X8%T&F
zqE<7uK;0qq^Ry$e0-z#BH$Ri~i*@Y~Z0ow7=eIl$YGPA?^e(Oc7zI<ssMZGrVph_0
z%cKmG&5Mm<+Q5fChHi8Q>NCc%H?S?mLx|2$o%iY}Euc2*SoXuDOsI`!=sGC<nXpgI
z37Il%rVF0)=ixKucP40_HZ$=cu1}K~S6WByz+l+0h%~ad^Fw~N?UEl3c23-u=(L-J
z@E|LExq$`AjDe25B}C7lk3{JvGQvgNlUV=WPP%>fuOIiXfBa|j(L3zEpFbB5170O7
z5m)Q^fV)N-MO^5^NiZ>({RTc`_+y+;qf+r{t`v}k#>K%JM;0T9JXM;!-w@HLdoc5*
zeykgx$h9i0udD8^si1j@j57Q3`-LXKR^x^_)WtKx0nf21L+tZHw6!SCJy<*17`6q0
znUS#VAcmmmXuZLL4wOCgRB=-9IKcl(^JdYkZoBaknPG3HSKIZ?8Z}0tco_7wp>oJ_
zXq4KW@(tg^Lmz`O<pnr$Y{)ZXs{KOKkrxpg1u{xsRI0~%=7?Qypq0=)RN{Ms@u14G
zk0J4Py_)#xRTqXg8=-5yR1Z)W$hT9gsg^Ik`tB*pFIoK;eNl0($xw>*{fq6>W>rWF
zGR)Sa2rO+`vQkm)ESba=Z2rPaCYkPQn4WI@hC&msfN-Q;o)o!;SZClmlH?rL=A#x#
zbJjP$z-B;m*BNfxnDiM>qs?OZ43_5N6+K|RM-<VvM8vVgm1aHeON`!bw#g@V)vEql
zN6ZP#Kxa`Fi53k*tsP3H%^>`TT#>4L3xF`K<dBfF<iOW?zvcla5(TaU79xMj;`YW=
z-6+2B10ovHjAvA>!g#PEaCCb*49PmN-$A=w8<{TkDaHUqb!^F@n9^iX47<IhrEuy`
zAzy=_=Q13PQ5y=X?Fc~g20dLq1`s=_Mt}ni&QR)$zdd{Opole}UG67ExH&I%v%DN#
zhHNb=H7qT%P<^)t_v6F~c^^!#ls1B(x`EVBLDy7rpXL~BUD^oj_{d3R#B$@l+@gMF
zvj8Layc4Ecfzmk15G+>6R_(Y=BS*16=n8_q;0UN5Ar%BW4{sG1yI~Wg(OZ%wCjA&F
z+YHWwk2s4}Mbc5EyA&fq2Rl`@?yz-TxCRf|bFqYLwJ9-iFmNka=G5s3HHPZTG>PyV
zVv4@a*rUIRLHu4Aw;yf?>6iLzvzjTUzvx+lrRjuMG`W+A#*8aH?r`{*AOHID!{Hv7
zXJo}gUG3cP3v~^0h6T1`15YKA@J!*TD3!o-00oWr&Mr!#CJ4+NAuE@7O{X&Im7o$#
z!`D35N@%cGn4atvx`bD#p@UMt%12YW$1s^;(y{YtGOLf|9_w1}s<&&?%FcpayTf;3
z347W!16<nhCOd~=wYg4xtf1<3&9|^~01S~TUgH`Df3eqEe8k#7qX=1>E*kJDkfKYf
zP+)Fx2)I`nOhk0R>OBbRE_!nidoTWVbvuDk4Y(OfF(cw!ccrR`umI4y{k-rXqmvN3
zTBHGD23RKZ4iyBbK;hlG!Jd)F90m>~_1aCZ+T2_*w6<3@?f^0ogHwrOQZC(ea&>b#
zgTF?N5b61KCp}&>?;+p)flL{w8$^O7nFV1%1lA`U(NGdW|HZrriB9!2YDaBZCWdYf
z^*A|}1j;Xq{6J1LWseG~iL|f?A;U>ic_p^c{48*z8w3IsWY#9YSdPj*DnT)8B&_&L
z)3{ZuzA0<eU4pexEZzXu7C4$E`&+5`>;r?Jz`j8^alxayzJpRi2bS0)PZ5UN0IYZH
zQ*stZVPHYsD<gpwMv^|0JFoN$36MH#3hE56UKmFyo#HjbR|e~DuuowJ!L1;0lytdC
zK;<r#rgj85ms|&Z1$jP^6Wu`w#@=+#TLm8a<}@1U87nXkXB5AT+`+9L%=+Tb;@$fx
z;F*Xe#4wJ)YsxIZ16bsD*}%EeLA8Vg0msdlOP>>>S3r(UNspgbJ!f(^NX2%Mj$n<@
zQ&Ev9vkS@tfyg1ku?6-b%`2m_DoKgJ2*R%~^(8iYcCt{eg*d~&gh<Kr>iyu~1ndn>
zfaLl|QxO^X@BVS{zw;pl;!gPg`j@}HMn1<ZVk@m+E*{F0O|gsEeke+IJ%5(ilG6(;
zd#T}EO;87K^7{TGYTZ5ta!_vNe__rupE1}3@vJ!!sieoqEctKPE6epDeAEW_Z()=D
zSv6kpkU!?@^1d?mYq$Lkoo49tx$^8HlV<Gp-N92l5hggsAuV6vRh_0x$=kex&@0_#
z#7>M;B)oLuCv7}(+R-nv$e@6hAysfAHzm>Py=PL+P8KflA_D1^hBDc21x|p46}xa~
zsR4-;-EiASwNIi2@)UStOX&AAEiC9-FWk^R*+PPE<`aoCwR_t6VlGa-)2dw{y5-r9
z%LBlbMcU~`rucMjBPPikPqt6}t!6$dO)d*?j6>8X{0?48^BIyzC<T+b<ab)_Q;MkY
z!Wd_9zty>9D?ozJfx~u#^P`NWsx(i>5{>Cr&odU<K!$_io57n0e~Ij@A;hv%ECjUf
z#R*is51YOyAs+feuoqXR=qfPw>Nc?4MY0+uY%_Xt_43V6o0mV|u@L=-mv2Q21%d6U
zfh9bX+G&cj=JSdv?~!&BRK=|Kx7SvR3#XOLr$O1Z$)o{uybaSz+)tn(0~zykEg|^P
zgPxOG1F<D8kvfe|4a=Ja)B{g%p=^N%>hgwlg~KU7)Z!t=yObmUO+12*&6E*oj9nmR
z0@4ndZaRmpbJZh1xJroTLZS~z(SEycnW!3OQwQw8G3(XZ(LovRVtwOu?C)d?oiyO4
zUmcjdNtL)OT;t@0h<KJn#4`{+oX80=kwzUMNA%-#CdXgh(?PFI?NcReThC?;e+CFF
z3CXf#AD|NAs%CqMd-Zd>a6MMB(zN6NV~}=tEYC#U$?>>M=pGU6?AkHy(Fhz0g$1$D
zAkkLjOykS80s8Vj-;P;^vH9!}+B00w6T!=2U{1w?xS`+zm~hT|5JSF7!}7#Hy)MED
zrdN=vW6&d@VG;9J5%n&(Sx52(`c!E>Y!Vpjy&V+4wf-8MaX@8e9pM!73_~=tsZi44
zBAZ*$3g3CC+uY>rH4(Op1w!X02sl|p5sAeAI%fiok{&%}KTUw1oE%D+TcUL`QJaR3
z?N9P*83znm5QTF)Kha+bmj2@(SdVVVN_3*x5ih3cxB!72^f&7zf$BPdb2e$aR1fnI
zh2mt}^0g&IUl-1#s4#c~hNf61Ltm+1Dxpd3CQS9BPk{7z?<|hi^D~=Q<4C*3+y^DG
z6&gr;vzcp;2&@UHw;VtSnd60##jFI2`G<3EQy$hDK~J%jRVM%^K=`~Nr@vn6m1BLo
z$c0JmyCJlCyXnaNLeiyXJMT@;e~K}=$xk;sL!Uewos!kCJX`i@ty)yQ1EkKv5S+_m
z45*jTFGHM8vj$3Xk9cV;DgKTs2C)I<(RjX(UfPymxw|`BKN)DeaizD5R^>oci0Bq_
znVXm>$Mmw(t3Bug{$$rHc@idzVoyH}LNCb@J<4G<E!&|-4i{)TI3ahG6R$Y2qTWCD
z%k~8(IG8D8cHJGem(lIO(l)o%!gQbUmv6Tq*q&4D2+m6`v@m!#CX*^bnm4~O_wtje
zIW$#f=DS%V_y6r?vxbk)EL1uQr^y^BJ`}}469ek{oy-viOHjvl+t=`3{({`C*<O?3
z!A{&m!BL;G9k3P+M+_3a!37-*wzFpP*gARn>eYvD{`T?>2<PA4zkc<A**repe?SGJ
z!M^G__}v5b;J>`-0kn31Lp%fS!`(4k2o8d^YrlsN{)p);S*6Qt2u9;8xJDLxjLfi@
z^vgt>gCpiAu~j&p=M#JwJdH~^XvWF>Z0=^>BWKi{x;bb)7<F>13^{;FW&=gSemA(t
z%9QPk8;>aB5ic4CUj}!kef{&hyH^A1%8kmI2Z8Gm{6fR`O-pJGTP0?|$(WyzRP@6x
z(Vi(S)YlYWV;MG0q;ZTY7>E82b|iQ?X86t7D9FOaT!htbx_<#ZSc73lI%!PY%s3%H
z9z2Pn2}M~1uE*GEmobiP_jlvlJ<^_53Q1DX4AcAUU_h))@&z~((iJ$zNSXxoiR0!)
zISea~;X`7KGYOP*4wN0(<AG16*sGo!jJaT)Ik*JESGZj`Vs{DE`?&#$YHq16FM(I?
zJnRvOPD<VG*n4Cpm>w<!gOdu*-|2qj@=m^P_7JyLD^eAk2s=<7-6^{?#a`XhY$Ds;
zQjCnZCXbjdgsSC2=%6DPnFG0ZWyY#*)*aPx89RmA;OTCM&?Tt0Za%&J%iRZ^#@?2y
zs@o=Xo%=AdFOGl**mjykv--wK{a7ZebZ}b_Iffz^^a0ul-++)(kgEmrJUEd#iIxh5
zN-mMYSj}=ZtT;=2NTO)Lgj$=e1=3t0E@VIBv>-}S>*uj2g%_9fb!HWbEmYc>MfJ@e
zZ|5OcRJ3RkpTbVLdpfFZN);p{jwL3K*qgZ0KpkmejfN3AF2*kg-wsfrsQO|GdQPqj
z9e8h-{AORQUM?uXa`)g5%XqVVG*CNYjsisH-$6%N>N0=#Ku9Bx3G@VyFqz;Wvl~L-
zG+c3yAajs0i>j@V8zOr-&IHqNNo!2!5v)Q}mRl2JJI%7t2h&3CNDJ$wI6c)#TxnH!
z^K1c^iQ)Jb(+>8+Lu3$wLtVbU^jL?XJsvxf-bHol=~Jv~Q2H|5ik8yK-RoE<eLO}n
zLLgAC_0g$0dgktjLdaC{@w}IH9+InuE3_UR?+uflob(~>TH&9n)n-c0yj#Q<(%5y*
zwh}uVsJ)^<bKp=AYALnI0$|rpMILO^I(>=6gmJ02X9BW>_l>{XV;yRk-rVPkk7BpJ
zNEUEEWWc@N><H&nQuZO8Vnx;3Q7Lc*%MD7}S`RCbhElu%0V(yY)i8C>C&7FQVXbmo
zYhk*9dzG4s#Adi3WNuI0b}%o|SKxLM?(LbaKh=iqAE9giES@F@luc>EiV)oYx(Q!7
z5m4kkNs7EDcBZnuwt!H8GtQ@gY4-S~a@V1$4)RQe`wdVxXl0$q_HrEwrtTtBS<J+V
z;|Y{<8=6c-=%J}#Pb~1nJ#|RQl(5<YnP7vdU8zC?QE1Z(PS>;(1q|DB%6zmYANZMB
z8jX9PAsd5(rC0g%&HIn9-~DU{yA0;qRbCn7v4vvBm3BF4y^>#ZN~LK+Qid1uXqa9-
zl$Vs{#_qr}t)+L~Vt2iRYS!LN91pS<4wIX!A9lC9jde&aWtv%@zRTJdC7LuwQX349
zUR3jK$K|?(CS;(7b~cIB=oEosOz>dZ&_<2G8XFJKEvIR!jhJ?J#?Kn8mmChy7fT%1
zV7pK`<8SZZyu61sba3+Zzx?$2Yrf6&x<h4g9@LlmFbF&5z`Wk=mh!NXJ2S5YH(7zg
zfNRO|+M*JQ>ttJbS{ot3e5BVK@?$1@8QV~xVi#z}1SOMNBAL`~T2V!g+kAr@sF(N*
zNoBfUAZZ#^pfGMbHp=M@JBDuOrXt`LT=1uk{GN7A0zU^?FNVPI%d{?qx-7$N6wGH|
z93us9>9k)gbxTodm`~as-%a&L@UNL&Yak|{@_QoLD=pWbg2}WJH}G-b5Bu2gF!n}$
zX_Y>9B(V;hgDYpwJl|W=qqN>;#&?C5MKW@@m6_@4-Sh3{@Pw)!H?8{<Gr`-!^xmO@
zY!f=9<Q)=N5ofEkt_g>k)<g3~N{(b3Ao(}96;o6Je2PVXNJnMZSJE!9FyK2QQ&+(X
zgNcAHNApJsmDPA9Cc~j&N41VL9O>59Qas+?4v3=JN{p6-VbHQ=QLEsxgck{>L3@)F
zBE8CPv+iKtitf%@_3qV>`XoFBH*ad)(Qsg|i%Sidlg4I~u5d~sXdfF*tQE4NBJOjg
z+x)j77b<5@7XTuYBLdl%sz!hT4o;N*kPvtrtN1B?67c(hqII#FxB*QT^%=RwNKb1H
z_+dpOTA1d7hm1Si(CyaM`$=l>1d3Z6Ji=zbM*5`TnS3aqu1A)N@pX=`F4>0+)yrIb
zv&{!IWzs#TMHstHYvgM1S&mE1SV8d_)6KR5F<PizX%F@F58Z2VxNKH?nj^3RHW2EX
z;!7=y;~6HgY{9pq$;mNR0kv_U=c$Kc<TwE}k~r!@FLryqSuP_aMuvZlHK|$h#KfJ{
zaPW{s?iCcxFgVZcVhvfo%GZ#PR&GSei%=||o}xws_dodN)otaxnOik*&MRI4w>pSD
zJA|L071NH#OQFE*a66cFpzgYayJ&vC{DkmLM~=7#0$$4_-p$<qg0485Z-)=JqS+Wz
zmP;8}OWsbT^K^K2dX}A%h+~-kQE+W`wEiZoE-F<ahjiBJ9u5cOHc0Nve;qK51Si|w
zOHTY>Dva}Qq^v9Y98Nt=PwLyik?c;1){enPUx1%|0e=1k_`@&2FTMbO1iiiQYs(=k
zu8PLdyrD2{hAKC6rqCC*%o!XTt;(!#&9?hYKT#<wMA)0C!0CF&m_Wx+=04o+v6ER<
z+B92JcUQYL+*<JU(8XN<+fYj2>ZrB63rwtPxqs>T#?2sqOXEc<EpJMR4iq8Z|LvbP
z%5Blr5!bBn9BzTw>B9rOX?&v(Nwf-$+nE(MibKDGRP=_d^&aW=u*<LMjj935*+TSY
z1vYLmSy=(Xf|@o!J(4f6#5lXB=Tdj3E751;j_Dq;0@vd%C2^@9daC(Y#X%ZZg2y=;
zYAz(ay8+7zv(ukp6N4!T>!~!nq&}{uAz9Q1B7wfX(@q7_50_+*_0&gcNRaMJ<9E8$
zptzl-qDA!|HWaf|f%Lc}f?Cc!ss&FXjqt>DSidi-;jR}8*trJ38=T>2#{n-bdEA<G
z(SU=Tm#$$VaRnz#9VK3E&bQLH!#mVe?qF=Ga_1c~{+Uy=<ss_fqhSxKV0JEhS=^DM
z5BZReddP&?g3}*q`j|pi4mohDpkoC_3c33F&-lA#!a_FT+j81N1rp$R5;vQh)AUA|
z8f+zEJ&S9-&{i~^`Spr5Ks|KAqMeO7z}wOi=&Y0qB~XC)#s9Ll#K3xFWSgBm2PbG8
z8sr6gxw}?4H=?wNwWx4_^1N;tGRH)4=2FFWt-yu&Xv*4d7d%8BR0ZM`ceS8GUfxYw
z%+JCzVfyA2vAx+NQVI#tuzPp(;{b^+w_u`fFpzC-R=LC_cXA8VijpI7KU>s=t*!(Q
z)(@7?t8ga+hT`p-amBM76wm_R8euIuvHh2)m_<}o9rWVo-tk^%BVaEOSNlNDF+<w{
z_Panub1i|FgROsDst0K*ZC*_D1=g}+#9El`0O#49lFL`izkfVpRQF^msS0kTajh4b
zc58DvMiK8DxXGffQlwx*BTIX$waL@QG#q+*N(zEJe6Vs?RIsOmhFYHoPCDWkBQLq#
z>l6V4&fglQC2%<=<#Sh5u&)%xO!?@UM8|?Qmk<qyTseA9r)Q}=A5|b6{qfWW2-Z_-
z0~;6SDMgPIJBPz6LAKGoLT9h)Gr?@<D1Xd&JH5h=K{1-E+tp;?&Q50ecfCAiydu30
z!mcLsElepVMGoDE@P~nDc|`$oHlN&H&Y!uK#&tAZs0Ja5QwVsYN_y-<^G$`mf_2o?
zHMgP3n7Zr%c~Mnmj7L-6!WPh{@~oS#=`7Ya-wi|zD5COlZkqO2KX1%hiHH`b(2xvz
zI_WbCG7(3jF&kKYtbYin#wB$8Wo%m~pq`j<f2sh_?Q_HbA&tJeAtXI;OVw^_fO&jj
z(RBryYD=0`5U1394Teh<FQ8<_#d7YE29@)Xo7Jl}-*&W2u~1;)ZLM)KvhsQoY^c&x
zX@s7a)h$(VrH7@Q8<wgHF^!!T^&=s#H5on=QN6j_A<srkpZhDOOFfw*EMk1S6I=lG
z$T*)oDDed>3*cJ@{mtnWh<laN$;S{^HVNPwVdxGcvhUHe(c%6<;u;BeeFKwbPpIzW
zShXV}HI4~B<SVV@3S}7E_!4rQt8g~DSBsip)u)De6W>Vor=Fwu@TQX<V5m)3@mxU}
z{@WI2M<#^^K#Sdkzv`g6lCmO_olcicvQsu_@`@uKvDoE_&(LfPH7M+Hou6Z*>-_jY
zYz&zFhEO<4W=jd!+zi!gm`pHzxe(u65}|ykt~4ke*dV*(=d+PcHtLpmk%qjTU7dm~
z!`a&$yNYY|X=tIL14xl`nH_K*mYpa?t~d3)o_>$*JN@2EET>DoEVGn28XtDq#Y(7<
zg`n~)bfW?9b-zN17Ne%{OmR+925F$SkV8}G28ZNV8l(g&Oe5kvfTq39Q3W*3$7Ba@
zmHpFl+o`lT$=M#TAu_LV0pt3#60c0^NJkGQg0Xq{lF|pHjc0=(mou<?Lbh)tq4>pt
zkA)0YM77mv+dqHP=c3#yO9e_bL)ic)2jA0<JpFw%W5Sg>EYj78c~^5Gz$<~Tgu-6P
z;zwmhlkoLQvZuSGq}wEb+F^j*$doFm2<oSU8lVl|O^u~?t7xmB7rUKcX}uXDMk|E}
zS5RA$Xc&ITB6<a%!bH+TkF#K_FimW1!8Knq_HhK8vy_@%{Rf#FI%V_B{1U2|E?k3D
zgvNA=KzTo6Ur>15eEazJ>U-Y=rh_Qu!n{M{W8h*+%`qjbLW(Q(o3RL{OP~>t;y**e
zcD$2I0GUVhx#2{HewfEuigG0+wOn{&Cbl1zXEbG|)r8h%qk3~w?Uy5};zB#dwV>q{
zGlR-MaEUd3RcE2ekyt#mn}Q1qJV$xu>-~0liR56&HoLuCi<*`Y$SX*`W<X6JPDPl>
zS;Y}&0;(*RFX5PU;xCqS_$2XC;qCJm$W(&Wv7)NR;v=6o_Wdz$SZ<V_9^h8-AzIyB
zB^{w7zPxcRpfXU4&J{?A!s+H##VDZUzBt!Zi?6)`vt(_d^2EGt;bpM9fB(xba2_t*
z`AXpt-e6_wrv{|Arevx6`HP?%Z5~yE)LC`~q)%at_?wr1yF2Xe{^zH=clWPfzB%k!
zN$TzEd-%dy;9%3Q>|h(+f^*xFG}`9@(p#atuqg)H1T8L-;=UMe9$kGO|3dEZJZ0Bw
z6vIFy6#oet$lXRlXzJ=JhnME&)TJX%e+AXMgXdwomL0Nurs5M$Tf6Y;HbvE4kLv<M
zaZdv379uC|wbS<LaV&nJ-KAM^x9caSZip+v?U~fM!gn{tl~QaJiO*6Q+-o|L8tq!j
z7=-%ethD<S74E@nVnFm?4GKgp4YQEpn#H6rXehvGH<Q^?MTs}q?Kf+IP?b(^ws_wy
zvJe?}>+!#*>9O?A=VLvaNN=vrrjO=}>?O&^)ed<q#B8Q3n=y#@NCt(Jrm;PS%t&1w
zhE^Fi%!5>JY86sQkiOBpclb2SEcTsy^0T)#0+wvInp~|x9Gh#6gLowZNDmt)PVR)q
z0JBW#wS*lSR35SlN`WDvIA*O0PCu)u^J01o9H{YC%DryifH!d<A}5GRACaOMB(cMu
zW5Ri{xY9RhR@@WLJXs5UO9Ry6@Lj?DkogPGl1eA7M<?Z>vTLqyU_pNYW66*2Q3>|$
z*Izs)!rAfucW0p9-EM`#9^rd~hg)Fv<@N=_SU2!0XD*u{8m2ku?^C=4;Q=TO0S6rL
z7xvnsMW3fV5Zrg>%$(-5P(7OSiP%usXDBWdxl9%)qqIP73h=}W=)kpp2r|)JUro#k
zM;;3sDn6v3ZD0uME_zu;KkTQTfRK!SUkEXhPyk*!=FCg5mB&v5()(RLgOV3sW$ma<
zc5|4zhi@wa&rpj5MTARx{MpT>c>+)mYCqZI3DhHE6eMR*eRw!QbK{XtX~_FAz0>wE
ze{ZO~ljWjFx7UDmo8bqgXY6sy5&`+{+%T;J)GavpkeA-9GRGK`BRxP@@bQnt({#Md
z8c13*3jK660DnK_)c9_2B#Jp{dugaP(_mzQp2I<P#m5BMovuKckh%_QkxpoTyc6cC
zhtC4XvOpp>XjENG_2?)2&zW-iTFtl2;s+uNe;WJ>qL0ir%v*9hdm0tlPyHqg1j%=e
z3Q}wkE4Rf<j)qd>bZem5E`5W{AFvs0k(gGCsd}ZzSk_Ep4b%742{}PnomOLO08`v0
zKU^P}j|HDJGS>%j1*PF_WUN8er1=-60hz*H;9r>f+`TNfF)PzBsEK3;6W==D-~^}c
zqE8{Dci0bYITo$QMlAY&P~yh<vP}{<FT_YMz9e&h_O{PS-I`5?J|IW1RPa!s-ap{V
zoFjuV+3ej@>;-q35d)!9(k*~x;0gKfwvI675*}Y)k;9>h2+}Rn!<AQB(?Z}p$fc0?
zSu$gG4y`z?%KN%DSr1t2XGgg^*$t{Iy^;GmIUmMZ>6~x{)6+u4`3~ZbG+_nPP{Z=e
zO_f?C?18+?C!=c1{~z4#f&XS|h=^Vb%A&Gq0-sNxvXl{wGaN9@ft>?n-jem8Cc-@(
z@{J5QhVo~=f=24Rj<nHzH9V~ma1|`<)9l9TE9!V`F!ipOXOx7aw&~O;sKV<g!k9iX
znFlD(xH<vHxx7)qo|M^-$O1&W-eO8P*mR*a+fPp06s4zfZ<D9a?h5?T_{SeVz5N82
z@4FB^E7;pN6iG$b!1&64Y(P5YxthB24ZKR=#1f}nNIh!RCZHDoirL3zD|k+tXMS<5
zJ~F98)w03ijWdDnp|`t{rFiT#>kcC+w@jE#VeLsJxOae>CrTUZG3X3(wULZV{3sjr
z;KSkF9jYPya{uAg>z{r)+~b_%;}E@4Ymx?;73_tZXk=l1NyF%8w<tw`G&bV^Ru~*q
zA5jvPA`_wyz}1vwGXm9iIKz29xjJ$fa%!!fL^Jr6xtt>S+LV3=_WkP#Jaypdcxz52
zZrp{;5so<I3x1EIXf!qBu513NZGc1Qauo*j)SwyUYjScyv-uR)>Qn5MZ1?T%BV|o-
zDf1M&4zj*8_-8apYaUJV^1xHS&^vVQhCYspwTI;NG2Jl2BwMB1d`8|bhaGd|q#|rP
zfoN|a%6<HPptB(B0MLOHffUTmIsABknEn8daH!#UiPz~e#AJQ|Dr0L1a#Twm%y1{z
zV2{zj8T?&xdlpDo;`0wq3`eG(!k0TX$;5LpsID{*)Iwpgkdz8zpT2+l_7gIIzJC91
z`pX++9ykKfx4Hxmy>A{eXB9LXUUG-?$D$0lqSM^@<Bskmlo(l^f_xRWZ=5tLL<baj
zy#<>80AY5eQ`!v)*6G_np~H5yF+tvMv?da7F=((AG@VfjyT9w<G^hW2@JDeUjC2Q?
zsc48!TyNLpgWt`JH92T#dp^DUXz2)8+zUQT?jUjc>m25Am6Jxbhj<dt^*|b7Qxouk
z;OUk@^#JNj9Z-jJ=i&m11urwMy9!(6C<0rF=tKab1&H1)a@D%4?;wN>zLYb-e?fDh
zQbkx))u>kpvD{kd*^K1R>D#Q$u_cV*Dc2C=?eN?*TLn^_Cy~m^Kfy!M@jLBPi@Wr_
zL-9jLhR3(f#?P*+jKKRB)}(>=^8narbTQy*>Mm2W<Qe0HsD=p%xC0f3f%6Q9F!+?3
z-{``1o94hw*KT2StM!HLUSk3vP-xbYuM+kv-m{p@ccQfUQs1SA*3>?gclN-}-YyzZ
zKD~fkrQGXV569bo%!bFu{vX@$(oLU}CNK?A2UILYYmn~3{fnzih#SZt&*0yMw0L6_
z)Ve}#`Q<d>Vc7G(EZQ@vTlCU<=+bzNWt;r#{T+BMLl7tGElfA)EKK3pwL4J@(+%2*
zrgZI3u9INuULc>HwbroPlF3$!OZccT#p!rRJrO-1@p3TMvahri!n#1)kVwz1=sCp3
zbrcp%ykEgJx{BUd>=-<oA{s4xLCs4wPHF60!{6JRoLd(MtEJHe>XPDlPTjhT_*!}!
z>=502+)N(OJl)~oVCQRGX&>$(Ji^!uo(N|M-6ru1Oa|C0a-5{B%y}+uGcNM}HT`};
z*R;4M){R;tSPjdAqrGskMi6f}W1XwSdJ<wFO-jh27K2?}_0|KoC7He>V*=kE1T6u#
z*XxCpfrBT$9RB%jgrak3t`UzbeQPE+kfnPxbfw<Z{3QytJ$N{IRnTEZ#|-qQb|hk|
zr_=MQLdm(rMkA|Mw9ON<_=Se!j8smN2a4Yo2kP%*6C^d`#QoI4ACJ!H{|E=VuX>On
zPKdCp*|aa$=b*4C^62>&uwruL?m+W0M^@RE;0Y}<FyG+*`LIu;4F?{%4l^WQGX8_n
zu|BwP&u*Z4RL>#eLM%_`MmGW;L#mfTn}R0C0X%(wGTvSezri0w>>LhASaAm)>is(!
zD*r9#KxUrM-8bmK-VBlCzhLq#V)^9jPaj|25B~e<H-rB^#Q#TM5B@Ot`X4`hO_zDx
z_<)y7T<JC648Asqo-xo<&<R{1MsM6st3@@fA~67m3FBozF=82QnQEBkiR=Pg+lR;*
zpy>|Yg)SG@>*t~z{#)}Q#tA%|;WlUaia*6u*D=Lvw>k831Wz8ru4v`epsc!HPGETC
z^JK6}QT?X<1SbmYyiIJN1&x6CC33;qvnJhu<Hu+r+!@D_FMS2a;F6E&dpoeA@-B87
zs33|EOw10W(h<fOgBq-%ur>@8W!F@ELEfeZaCtV(${lZPGe55sxV?m<%aoz8h(ZLj
z$#fQ3$HW=Zui_E}hN=RM4nkw%<>9QhyG#_r-(ueb{el676xy36WV(*WFEpXm&P58r
z=30G7>8yCDkK<%Wsjp{Of`2USNBuoCs`z+gw}EWHi9uhZFFUXusG#{SQ#$)eOT;_U
z<0~WlRkYUvng;|y#{A-d8BZWG_w;lSj2XJ)Fo#>1`9egAh4zG$0F{CIShczJA4jSX
zO|?2TL7vGe^!t8U=Fgy{fykWJ+?EB9)FH39<C?!s)fv?vdjRTd$lT26*=f;iYgF04
z{IQ+ceq?umdZnCFCWx{_jF5Zkz@I?K<N-+@jU89MtO%P%MQj+Z<S26b_oug4+r$Dh
zAdajw{!eX2LXW0hkJ1#=*=)Y5a&<hmL6|G($dwaur8{-pO~@Bjv2b>&9{LPKnp3|q
zDop`)Qbw9XmP_`v<@N|<4tw<kF@5P1%0{0Ga*Vu3UlQ?%j+1PEKK_1w3$r(6_5eF_
z%V*1kY8*eQ(h78T#Z{TFA79I=4|dk_({GXA*LExQ3d%L<4ytk(@%jpZHXLeQa={@s
z*~U8-Cv==k!<5wqZluL$bNk{6k6VgLo-75+(e_i68<)|DH_=UQ(D=#00iT+#!YZLP
zG;2=s2j+T8haQJ8=a#d<f3b0_DmrpnVwy=mii9)1E*y9R(G<X07#~P)fb19SB0UFE
zf-`{-|K6!=to06%bp}&FT8Mm#U>WI0cR<VnGweJojHvK4&^KH51pj8gNLVdj%vG)=
zUK~~lq<2#BbcS=%%Iy_b_7aaxJs;?mai!N7RzVlZNa2W<)8)gyX$RI^nd$Kn93=|X
zNHT608KXjNqO;r8kft9R`3J|9hQgH+bMb6uE>GeCxQ6t6F(wEfAO@c|6vy|GPMRB|
z0<!zbk*mJ5h1zsBiOZgUFU=lcaBz%JC#<n2J$Q~xp+JH9!Q}rsUG#M53C;b^(@G+W
zTI+&MN0fJGwYbvMSg7emY`{>^*@@`e6Y2`*cpR({0myY!og#my>FnK50Awk`CuYbw
z0y``HVOGx;aQ&UV|MZtPcL$Ui`SG=wZ+<$Qy_~592RNTVt8w@7M<_7vK7K5;Pc=ZJ
z=OMBCm32Fng%-@DM-pX#PYejglcO#cB}9_*4)f)dO~P|=t@jq}7JN!7N4OfKw-cLb
zg+lR!j&pnoQfDog*%B)ME=gXXM@fjawJ7LO0})eBW**80p#PTnDH}`@ayLDEzPNkg
z3H${=+nyfcQ@>j;FoXEZ(CNe|nH2gD|1jVjHC^nrQSt10e^^hx1M&>M{`)tt|MKzw
z`5Ir&!{-?*H-Kel{@$8<b8)JtgPm_VwC%K)t?|${9bQgREFYAwf?sI)McT3w`K;9{
zE5rvP$fk%`)>VoNDr_9g6!`E0j_gML#**g!bGbl#8S15EU07CFnAW{eS6D;jmrU^z
z#skANe?xXR)T}zppKoEDnZJ99O}Rn1>B)mX_B4<Bn^97#ulG5c2mfo}WsZC<o%0$s
z7$|H{FxxFomW8%rRJz{msaeaRhuHdrAQM-DgT@suMZUpg5bL#$dhtX>SD0v;(;qFS
zZ9*ip_)9o(Trh03z|8~m8zV8x60P8mC&g}MuLc@-WeyUkPA{)Hv%uvb>~QO{W`Fy1
zwF8m9#QV87U~4`3@W2%lAF7Dd%@%c!w$Ghhn|~|QfL7X2cefq%HTnxff00N;mms-@
zqv>J$k+Q8xxZB6Jf65lUL)$F3J_<o8H*L}O)y*?ZFZ{~y@7`|jKHlA9lG`Rb218F3
z(m=lUPx>nz<=?!2_w(7P$yqYn9EOuSD1PL>uUufsowLxQ%#LVL)UKCcjdV7lax^M^
zl8^fhsVQ*>G`aU5?q0r)WHoV@IN$;v$!d<lBU#NccqFSi29IPl$Ka8y<`_JZ)f|IA
z@}T|}4%e2?et*D^eSg4@eSg4@eSg4@eSg4@eSg4@eSg52tjBmVi}vemDzGI8LFI8^
zAo0r3{XHyHe<6WJ9?478<>VbTA9<{oa{$*<J9Um|UHZVb%}o0arV$TvCpXbtSKV7P
zHI&-lW<{jrDX)?(D%2M3(L6-yFc`P?@IS!6_;Ni30-E!UtTqe|tNy?m=ARW*8uR#t
zIt{k3i_<m93cQy)9cz^oDF}*yK-Thi9k52B>2O0!sa6m_hPTiylJDsE=d3&EfynO8
zM1^ie%Nf4TF++Npr6_PMpI?X`DbjEHT*)1-z^_qP(bJ~B99|K3;}J`A+m-pC1J2)S
z;%8&Dne2v#Cw2TM$7<o8!^2rp3nRR2e6w3Eksx!tnp0)FU0>7IwVXkDCyGp_3E!HW
zT98;3dPPIE)Y!?@$B>vTcrY34?$gI#?%usZpw^LgO$2>z5GGa&Ma9|P19dy+SPnGd
zAz^9cAp)Rvx}GbD+J5Rau|bs|>IDKZk&I>kqOKIU+po?>i}PPm_RZN3WS2M176KfG
zDHf{K&h~({RPnwt5%_NWjIOhAe|O31SSLM!lLpZg-!O5H+L&Ur%H*}$FOZxB?!IvS
zW}?&0G?L9Gw?xRNWX>#)GsI$&iY$-v6*V*Lali5X=zy2)QFs9q&t(L1q}3zP1EGjt
z=+VLxPb(!K!zDp-P)E_UY5HyZ#8z~(Zng9j1Ti-RXu4)pY|}dt6>&y`>PioiM0eab
zj+Vb$c=<4a58dq{5`oN*k#lk&DGVcm-;ZsAq+39o)#U;iVx~FR>LGTH7}o^~cSRY@
z5@9+(jh<g)-k`UY^1p0PSb=Y(@7fJ=X!6qv4U2EI1l29@e7w2E(2+!Q{`BPS%m4As
z+t=@?6m-C005Nii!}Rx9S9OIV84d)8!JlBU;|&jTj}zWY9O{Tt1yXci=<nK;tfT(k
zw-$9i$?X>dc8?y=Y#4><9krZ}7L}OUfb@|%=du`?!YfM;ni8CDy8KKw92wkz6ry@%
zsGrYz62dzj^mu6<EvB>e3^19hNOPl;#kEPP{Dvp>GUpENNq8bGUVgk^y?=GLdGqPx
z^!>Y^UjKaJ(nACM=Et|Ml=%t&4iE!vEY5>}QkW|GCRw$7;*n=P_(O5m?Da>AxWDDL
zlq^xlFgE39Pho>=>Wsknhgq->59Nx3>p)Kr@S|}~E>kFA%ac;;oJD@GEuzxR+?G&a
zTC5mvfyfLzS964rZEsXl2?HFQq!?4zg>0{L&RAD}JT!K}3X)YO4?Y!#KZ~*?Ee6hB
z_~F?tiE0l5Eu4r0@8p^Q-U9UK-2w=3FPemCAB&4Ht1vU45?`7&rU;WxZM|CI<slbT
ziTtBc!VnMN5uAtA-?a~J7O1=t^iYsU#XLwQMHO+1fGD}s#D#ifZ0-35zj}TnJ#NCK
zJIp~kxwy?y#(TX*K3o|8kxMWybO#2igOx<CM`tel04r14_rh`C3}<dPCOB_%Ca+pT
z5I}5nqQP#PIMPXIZR^3cV{l7Dyc?iy;QG&b_H2+mLWq|frd>4X)dD4$9->18L3{Hp
zgLgJd`1|s>$t~;M(1|f4J3ZHXrHM5*r-16g;N75-fyTgn2?l2gf2ku+M7XesES$!r
zv{&@zQ!21W@BwDvHP>GDqnpiqDvfcv5^mU*=woa0u~X3r?zR>bTa){0ltVy_`PLhZ
zLIdVs`r|LZ9R7Ou>*1$2@1eRFoenQf&#vt;ZmLPT+46G}%pY?dm^GW@jI}Rz7dP5Z
z4vRn2<Bfj4=5J<;u7t^kA1;>+2iWp{+^-gsHE?RZ0E5!Y50o7=4o(NW2I)D7=v*|J
zoESNn)Re_Blw+DM#>?w$>5djHh|@^Zjq}OUj`N{14cU5mbXCS-l8l^BRUA?XKQ+iF
z&WtgUOhoBUar`o6vgZ@=k}htTi7Sne^JJ{_|I6IFHph`1S)%+Yb+u+PQc_E(Dv$(s
zMp~;UP|Yf!SPuZymohdRYH`ITdq_~zd+*Ht_Iu88_jqJxp__AU&2F1SRE9@pMn-se
z_}fv7sy#yqq*rOYzHHGMZ{mLidPIkOi+`cZg>j|#2cJ*jBV~Mqkh|YxMPvs|_i{2)
znJudAAV0VlK?9VBVpjG}|FQt3&g2#6OcbKCCSB!szrt4AzACc7`84S538?4MYi^4C
zd-SSbz4@OXKd}~WnnRnt?mlTabMvd|9D9J&IVjTL0kMpgD<XkKeuGyC?W9f#mb<%z
z@9u|jrTO6ztEj8h^y#sHEC+c!mQWi8onaVsoG~=H>=nK6j`?M^fjFmttl*v-O5x&6
z?1Y=|jhVxrTd;y(=&NkQiooLR$3$Qsr*zE8!8ue?6gABz0tLb~QhE-1G7&>GTW(pZ
zd<Ydh<vWJ=!KKIJaClp63(rEwG>6bNz+P2v(WBk+8o6JwP}u90>Rc3k-Yoh!KpVMl
z=6H>hU=vCDe>_Ei@r$$5XQ#u#=~@4I|L&X9r*pa6LEz$v4Vh?H=tw|-rIJ$g!gdE%
z&Q5jB7=scr+1dG5a~cbc0UUD3!n9hn48FfuiH<>GboljyrGjV@^n?`WC~wsE@m<4p
z9~dKWKvZ`ijos{Wi!X%yJKG>*#H^b=EO<q@i{R!?B{A8mF6A@YJC(v{?^Fh(y;BK{
z_A_wjff)@qe<%^^l4fB1BC=m9-jK9QV%n0l$;XWrF!d_F;N=WqO~`2DsF_cL?rxgh
z7)C|f>5Y{J*n()~g9B<O;4UG01u;`mm@I{m!bTiV8o&ZmDsQW*Hl1No1-BO=!v^&$
z##zNQ#EWX6ZV0Y``d4vZ-J)M@WhJ$7o&BIAEk{AvfB{`S9+|$C#YJ5+WTILu#W@R-
zGu8utUqStMU6<TF-c19$!R7!XaZCT?_<cBFqsyI)w&kor9ezpZ8Nsw$<hRdD?|FsT
zs8zqd+Lq#=6H&I}-NEWnH;*a+jrn&zFo1dfUA;}+SJIOz&@r3?E=Jeb=-Zp|a&-9;
z%y+4-zK$?URc|)72)b3AIM`mk4~7*_l%Qz@5N}aw6lolK#0R@Frr8;!(x;tWfMQ5(
z1OsoqFf~YzPuRUf9?j>fLZO|YOU-DkCK8G5;8=4xN|T>j)K91i*`KHi+Byv9?W##V
zH3`OsApWho%5d|}?Brkqqz}l4$L@B22@5VoLO^<txkRqPyukt`5zm!b6-bYYFP&b4
z-2t^b=x_FvY_w~vDFxAJynrwWnd9~r2BX8_&HeqSci(-vM<p@f`J3<F9q!-!K*#>y
zy#4v-e*ZU2Ur#4-l}v(Aat?b52H%@(UNceRY_!RZTI*eM<TKyt;@U<6-Q?&TlnmNd
zx}+es@pg9!^8^qwzARR3a&dXyT1GbJ`S*-X19vt_m$`?Ti+ln7!bd`uj`#rj0$oI*
zX!vz%BfLy{BcX;nKe*FwT<JyeSyPGwR5`;l0m4C_Khx)R0d=<!)+s0Uz7+6*w5{gy
zvnlQ(zoSN%OpDmcS|%EcnEF`YxUgxd$i>C$^%axcLrbz64a~6F61bZn&`7EYluK@R
zp*)~#<e!2w8#x<ESMwR-T1)c;o?(YTvOGl92m8pvoakT8J7h}44|D3|yS5is%V{f1
zBD-vVrXp>=yKn=l%%)1ZV*;^XLvM~#_WZ&u0f_}Zs}eehD=T2ym=d&`X4x0vd{OJZ
z(2O~y=3Ry6d+8Ti6{u&E(VFTO4E>q*>Zl~q28t`9Bj^~W-*%pg4ADmkeZt|xBlgp!
zAt>}qa8K<F#kF=lh&&hOA9ZaYH`Gjj1<G%A=i^3a4JbhB%*FLWU*wF!4co-5P&xIU
z2aCR1EZ}yJEcDK@$F)8t?NyxE+^3APC^l)?s{SZQP9@KDaZY{KQ&)b<TNlN846&@@
z&#A#YN?>#GED$5d4M089*Y2E~Mx#^76d-*%DVX`POJcdaY7|fQ$&%))G?<%C$ihiI
zF*kOmb9fD4T0M6jzQFk^IngGVy^;R!sFt>Z0b3_9^~mLl#kCe!D3^_cr`ZU`3x%|0
zszU9U|LAq}K)!1vyv!UqqE{EAOH}7GeDQDTg6o4!4x_e_l_T3G$2MHIX+oVTaM~JI
z!UwypNP#va$@B7sEubEWV*tLt5KNKwQ&k0dr6gdg9Ui0xika2=MJE+<ke*f|uu2E5
zU+z+EBn3&?``j@-U&#Ey5Wtj>3kP#%acOiw2F8QMecT{qCAdOU^)!GQi<llf58HnH
zdX2PYhB&g`Ya-p1qf|U(6~7&Jut&Q_-)P}4rvr}r6y}gip2fsOAPMG$vVnhvv$jV%
z<)wFDoXSZDG=P<^3!^yjHF%3ADE7Bb=cW*+N%6As+OD2y3nz`%IQ94RwH0oZH$ZT>
zb}tS(5|}m_JA~_bcA^s)fv?tV1v@wJ)T@QVoC_M^7i%sZgm5Z%E^geFq&wlUQaeHS
z^W@QTy}X`w2|5nIBjph<R-UDogG4c<i%lWYj_&F9u(NC}a0#7U^tu}LAeFLOt0+aK
zJhkH=Xy`C~OM$V>BI=qMQiPSVijq~5u;+1TraKqEZYO;N{=m<pZg}Q1i>$b_%gJj<
zH#XCBVo7Z`TYGwu$j-CgmMtPGjutetSfNjt&AF^xV;XR<*s~4!2)s@Pxh_CD_Hp=a
z_f?e=p1)4q0ny~>!;67HC5(2wmnJE52tX)n(nUJcR^UBnq@#yKo$1AfNDk3vGQe*+
za5UQV-NH8Hk%arwD=V!B$CtCmh@`@c{{UP5etMAA`*HLvdU>}ee}DjQJ)iWx>7|~l
z5ybl_?s$eXNDr-g|E`C0FsMz25@pa}!eavd9#49IvQ|t2ByIDAYjbHe#3$_KFHTrT
zkKkHHeJg-u%P^qSnDSa%hDS*5EsTO&cWWgjVS0f}h+niyTYbWC`avRjZgcPw9l+ug
z=y2rF%jg9GiOSw=E)iL_i=3p?gcwFqPfA@Ef=i(=wtwSnakAV5+x``SQuYSqA+)Xb
z6qPn-ufT}OuZ^B<hO0KQ-B?<|#P!RbP0zl5HgD@vSm_!B_g==(l%QBTj~o>h&AKCz
zA7pY?9V}4clyg5FIXH@WAW`_mPu@t@!TFeDz4B%?t-cnwxK9fbAe%Ow;)Qir97@XY
z--PO($;VH3)4T7!`~WpNE1h3My`#d(T0*3l$md-uFHyR`mh!ZFha#9V)$p@GGT!OV
zq4Bju7INX2uV-*#?Vgdkj|~@w^m&vNI&Iu1Vw!=vf#)cl?{-^;!MI{Zb`b0BVPH`o
zIWD!h>S3|N1GfjpmEeAk!PwJB2sJzzZk22yF8lzbXgaYn#r0<v!cD4T47L}K<4NVk
z+lvJ+A^J9Z0Ne_cc&D`Fq*-Qe@-6i0rN%P1=_^uStVptIN;qmv?*kn*oKR=jn#2E^
z4nMrG4FuV~1<?R>TCbt2MmFl*4pxt0?Oxdd*ZZK`0bPUL6K74R+?3bctRdk6Q<yqX
z@itoJ7enpP5&OpfX}d?K(>un~>Fkg8vm@htaiqO}@<bJSTi@G1(mpuSK0MNX3iY9F
zArA)k;|nBTEK?!-o>ab&ZD?9epfcC8sTb!$Cy+W*zRwXzu-HlBuUdp!$r=R7w$n;v
z5^rJ6%cT;^{>D%$J$hw`&g361;!;Fuv+LcO924ma2SJXAX-RVQ_r^vFWo6+=zOJT>
zJF5a}5;B+DteOBf&86iMXw>yUz1HQ%md*4mo;r?Z+)U`<ClZpGpR2ztn&F;C@VPyY
z=es<-K-30u14>tB!;|}xY_C!`#|wK}x^AEtCrr0WCqsT2<S-;Fvuj^Sl{Rg;T1asX
zPfy19(4b=xGj_8Fe$}M8vx_Djg{fdeJWOv!J*B?ph4g&Pq)!!ve?Wc<p2ZY?s$xTZ
z{vs)cqnJ+y2^C6%f+x<ytIIT*CR{_Oq;@4Bi4oHjNghL0N}H}}M>^@lnA#M=-yG_$
z>1;WA9r^+K%M`f5-8&8J__cDoZfXeaA_H_}gN3`!LJiVoB&61>BBPiuQt1rb>Z6Zg
zJrGvPen^Zt(!;Tmr}hYr<12&?nj=ibv>A4`I_c$hULh779GfTls_gz9a33@^3q=aG
z&J1b=+-8Xq^a6ILTRMVcb$*5^vzJP1;>atSVe5a)KBFgaAU@e6F;gdaOmP1wctY^t
zD0oWn@F;jj@aa+ToZzQN!RG`&I|{xa_&LEOX{4JIgxiC5qU3~oUdnJP;{Z%3>OzNM
zV@<$fiAf2TztODiDa38s0$9Ag0EBlewZ5c)43>v#gW2d@#VRS^)zpdt*&xd%f^C#*
znRXS(!=c7L2G?*RGOkvo^)fXllk>E(V;_ycoI&>zJ1Ts^yjAEJCV1QA1*zddw`A}>
zxz>RL=qRIennJ`3LH&3}?{QiL^!7TC$197YPiJBARsl(`E3O09J-ysrFs?K+LG6@Q
ziLwSJ7pZb>WE4$_9xP1&O|>wEHtX5drA`m>mCG43#MUPRUz%Z>DC2@GVmlKlm+l(C
zbi-!4gF6#uEWIH6qVS#qu6yERrm%!r!6E!$g$5-fN9uml)gJ9;FK!Ea7fA4pGg6ZR
z?X8`hruT-gd;8nnvCsVA$u!6-tc<=aP>;%n5|j?bMmSYE5gYAVM(!VT9UdWcpdL{T
z(>MBvELCPHsg~oSCtJIReY_{t?er#2u(XbIR~vWAq6wz%+#c|_1y#3DP1VZKE`w2N
z{CWr9&FV^DPZEI*hrPj)X*X})-M{<rgYUUi{0Qc1Y7n!fTvxi^4jTsNtfARAO(?3E
z*rj?LMH#uCr9#9<yQQgM@yfGf!HWZTuW_YON(JQGBx#orDI_aj2p7htT1~$~7LIKt
z#i^^uxreEy@leq|96^GPmu>oJyWeKbX47qoI0}v%Tw6dpfg^jcJ!qh;<#Z+TZ_O#y
zZI71U>gn&YE(h)o<%I^z4+FyiW~Nb3#iClF${bQ3CZ1$VyX?-mXZxMM*XGg_-}!~0
zehvZ2P;)F9PGV`y>pFm1?)0kFzA{^t?dsT+Q3_RjQO?RkfcW7wG4L-Y#=WqHWIy*y
zcN|Z-(Uvbozo+x<6xG9GX85G#OD($~{U!*{BA3Ozcz$<3`f?AFh){s<ojRzUCJ7{|
zfCn#1@r4Hu>)a=+ts80FgU3K=A2^8|`gSy8iqK7vu1AHs4es^W)U)%_XwGxE4z|L8
z81syWn;U+Te3yGFwf13oBl>nsBbEDOu=2`&ZVKK?)8Yi7Qod-M5COsYuJ=1xA&?N?
zOu8Z7OyMT<a1SG<;kDy(rphhPVQXA$UR}KT@csL{Pd0*lUGU!wZ5g1BCTFhL`$Do*
z!b%-9_lZK4?)k8s+|I#;yGokOpY46qTC^<W4WJ%OUw5SKfrrWa#fSB$k3W<H3c)$^
z<!8UZx1Whonjx@scTU&agZ&hKfYgIiR9Xj^>>iWVva17q@TYfw>;3KtH4Ukg!XC3s
zySqJ^M|}Xswi&il3Ce=b!|X=0g<A!4qHM30`yFldzoL)E?HadXi!<Vv6u`V4PH@`H
z$AzXLhyqUF^>*>s!~yxPYJv4A&;TO=4V4CLBQKBf6{bW9f9t@HCX=DZ=W`Y@?_DI&
z4q*XxgN+g@Ar-<zeJ|KpE$*JFP{KMfK6;o?T4+G=8MMxj1mbPRlPN+mMoxuzQqfAn
zUmeq2basu2<ZCR;eA{k9o~?rA0HVm}fX8?ei;j>dSqYe8yWAvj_js_Y4~&%A`{nJ_
zM^2^QV{88AFFfGqe^sn!#}k2r;K2EIXeX&J-`#>vVWaVnl=EeSb{ym;tb;jU4Gz~+
zct2cSE<pWz34*L2MSG$j#OhA>P^8B+SVj~QT~wam;i$l0(@0f$zbm-z<9;IF%amWm
zZw)$~0{k{u3f9-Bux-?2vb&GZH0Ea5kO}<+B(u>0bxJ}gnC@nx2d+>`PDy5~NKPr<
zi}y4XK+b}3rVyV}kG+Oz%w+W=mUJjZV!BFG0uM?c1-KYwQoWg^q{(HQ`X=+L%eHzs
z*&RE3EqNa}2PzKWHxsHbN?CS>!c|7)%8_=-&aa|DZ;%des?um1WD?=F##fj?Orq{i
zZIqy!tZ)mg&)2eSC;YgpDF&FCR;}{}@tX*axY}=-2`Wx$(~28x513_74h>~7#wpwj
z@)I@tCeOOth9r$FJR;HuntJF7$9tr$u(h-4<E_e;d3*KJY-;IB^CGvFS0HfPR|6Ma
zU2?4;>65VlaHWLno9PHWH5U|w1tTT9<&OI2Q635?&XF#9wo&glAO6wjql>HZoGqIn
zp`reg^JdAEMIyfFFma`JeRQRZIg?V-5D(kNGj)7Tbq_kY*YyHH9+>*|UwZdHB8%h?
z$j~m&T-g89rhMS0hpKzTi8R1bZ7DiH`N?aR5eA+l$0q;eXB3EYeNtB^O@D#obPfvB
zB{`OwyTdW?sx4t8=1*WfQ9PQ;sMDVO9jbl2{rJVB>fuu1+g27F4~%Z>WXB~~Pt7YQ
zTp&p(RSMboeKGd(#>w~{EoF6MCu<T~yH5^Dr0`hR+tuB5F_lN+KtYdo5YfspzRKC-
zho~n}>CZtcTuJ^E{7{FI63w!xfO=klK|J7}SW3B*rR5~0DLZM9dSFgJSJX7gjb7Kp
zKHmt7d+mD`0%=dQ^f=JquQYCPmqd#U)0<6!FCVwQm5@|c9{69FoZW`&Hi_5Fj=cgI
zs*jxtq|PL}Oc-kFVSelQ$aYt|w!3B|swRgk3{hJ+gh!~<1bo>~YyPwi)(|?Sx;hJ?
z7c-Q2S{&3k#_=jfctmEj(vD|gF~vcxz!~1tIH)xTNkvW;i&M~;x+9(R1(v@dMv^Ri
zd2`{JgC^Lp+q4t|sH-FZ6Sa*hlQVMZK_CS;5lN_+UVwp<3M4MHE)nQ(EHW2F31JWw
z)bu;Gjfvjf@ZKp?z&AViSJ#QCNb_d52jrrnC=*O}Nlpq5th<9EbalWZI$QC%>ud6>
zIPsZ<U<AKUI{B!6`fh@9F^=9&jvGLY()Oe=tS~6n`=J5!&q8sQmNEv~7+V(!L>3U6
z84BQ_ZN@Re(;o95`S#fl*rYP>&<EqrW!z#JOWg+91FreEkYn8yGGF@gQhZ=PTEr&H
zs|ofV1YFesl6c$EE-WL9f|4MnuZasilUVI_H=mtKtK@|@pPkA-9Xckc+ip;Kj5WQ1
zq62r-v+VnQcl$JI(|=(Uj#*D}7uJb5ZF)zVY!Py`rN21zv>>#H-f)oQ+Np}bZI~a-
z?H95i*@A}h2BO8VPQ2U!*BTPLxFY9pSxUSW-hBVW&U<_m0aPD2_2~`*Xan_yxqvv&
zXKlo~NpmaYa`kS>0Q~Wfe;WPt)1S7V-u~(S?(_X0k+GxJY<W)lngm9odLS@HO%e=z
zNyl|t%stYBdy~@fX-x+jJF@|e)3eG#4-;N14?VC$U+wmL*TlwEo)y=c9Z^o1J|)!T
zM0n_Y@n=BBMu=Wq>!H|x?1r+Cz#mcz7!=?c0XhlM<Z?1AyrLQ&Qn(FyaE%U>xiAWK
zTmvWs<J-7BbM2MhV_FE=ce6Obn^Ew!ywEU-+@N1(KP-uC1<(uhQe%yp@>2!Mojub>
zx2Tzcy1_^p^)OjUU3_s1teZkf6J8zL&3fWgL3Yr9UqB2)3<wn2@Y-KrVdrmQ(DpgD
zwH<~#Vq9u^#8-GllqUCB!>aKd3qLGAD2CSARS$Fa3t=ZIB_n@pTs+uh4`zr~Qjxp$
zpaImwh#ky@LYp`X|A`a#{!N%}(2{!jg65akFm<=}*^xt7zJ!x`<q_Wk>K1xP${Gu$
zw-6I3$Eq-_;j*9k*~TZj@DK-Ud9otbGQsswv6JpH?cUmM5*nC0w}&4@snK+)Y1M}r
zZ5VXoc!KF=!Ko@oIMHE*UuORT|5~-?$6I!!K)1LOT=P`tnivvgDtF=<u5oM|<?80x
z1$-dnMq|r6JLuLF%B*nq`DnbIBR-Y$u)>MNx)63`rt}+I?9c_$li+SX-U*dC0YFAl
z^MIT;vCxVlywEp5MQek}0F3~bu%}DyUhCVDfJWj!c~&T_;8=e^*kRf??sNr7ff3Z*
z&3V>cKR9supDv4emwt&AG<voU=~{gl`nHu41`bB^5y*N|_tD)$-zdDY{5M55Ae)XF
zrtU&wui<oRw#m5CSjvy3V*(OmEVk7Yq}HlGD}BimdGl%uRb4!$Zq^-z9w%&OHy@n0
zb(}iVMIW%BQws$FT(JzKO=wZ@uR|MKK=llfS1S&QLed`mY1jSJN1|DtLTR7_cpF#t
z0l;7jtVI&mPN#}df5W2&K)o(a27ZL^;C!19o!U4fW8k(244=AKh90tL(YrPBtB7Z6
zxu>+idcV-XTvwaM>k6dKCdRqGez^wW1Qi^guTU1iK(42+dYE99GkJOp66HG{_TeT`
zQJfN>H%q+)y(i|5S&$KExit?8{K!pdmtJrxIgM-BxXUvqrn~B(H}Kdi66{U-L+55A
z3m+04aQiVMBMC5aUOdMCCEe&RYcW|neVg1@y9Hs^Y|(ERH%!yOS+v?a7>DIP(abw-
zbJKEMX{8M#=-P1uX#{K@TZ==!4c8~?vBuhUqGo{9InNZ>78+HJ;x*oMtd|~P+mFMf
zgqp~kUFt)8JApfR1tzyr)72n7&p8wLRBLI#J>sXHBg(bLzBlz#F%>1G7*yC`m}lVB
zn1=eat2=bu$$;Y|M28mCzBul+F1pvI-t=Knh{&(>0YnMlEQGNg3fgA-jx!xiusyS-
zrH52(#)lN=3mTEKVA}#v^O>5`yXhAx#(~&K7J`ss8XaXDee$PSxN979aizx_-BDhK
zte<3@KmiE7C7L0YQMfOw2gB^zL1d~PA(xr`XSIRt)OZ5Q+y&l8aF3z-V4x8S?#HC7
zpHd}oc*$T&V0u&9=%xu)YSKmzO-iN7ll^D`l?y;-7wY)*nm6w3kf+<S(nMa6xYEbO
zj*JLt*58Z8L=Hwf{5w18@p^G+G#l}v@1SIVfA{9|JsA0WKU{(9IF=C0gN-!sEnc;0
zP(cYW1vsB#IDVoxfO!~}asj7sINU<my_%vJLf7nK;c^AFq=jMuMY!re_P?Um`2yLp
zLmvf$Pw%(C1w)v6{%ZgsyCHm3AvPJBZoS%}&Jh{LW4E(|9uY1Yo_kNePm!GqQIqfj
zR-H{)8lc``(B@+juW$ZB9_$ZN0g9L@{tU`MJ4cFGkuBVG=;JCZlWUp~+fEMTSysEs
ztdV7$P@lCxkOEyoYo@&c)PmUYNH2IElIuM=zm7Jow(Ve&437+JDtrqYG6a^=hHRH{
zpS06FSD80Bd%lF&z1vRVD49RkPiA5V)IpF2Y1ij4E^rOH!VH2;9XPvPGda>X{lU{P
zpCqnH_82#Oxe)~4JV){*y+;8U&;laNZ-X@US6f7RLPBt2>AR~9*A((ZD-@Y|+$w@M
zho0uyDfI=+Rn}-?$}*8)B#AMu0hz5!>qOn!SOwDbwuUTQv_j!uWao({WmV#fz_$2w
zq!{K4RPFkVW1Gc}=?KIBJi#J-`^eZS2W>OMt!&YC2ThNV+tjC^%XxN8t)S3K1wWoB
z{A#%<TJ*g__Ta8PeGKF4MbSLxHyrR%5>a2Q7FdIU0fF9znl&@v7J9)ZC>P$?Uqa)1
zemQf$thCSe+jB9GE}HyaAqyI?sXD5%jaHiz);F^I8@L*UAVVz`U3)95L{Lu$Y4rLg
zYX7ja@vkfU8?DSE47`0rRk=XsacakMiZl`0VKvP?0-+URa?1uigt(n^16P?WYmmmL
zFSqPk)l%EHRN*w0SkM8_&og$)?4<?gqIV^jy6Z7pxOFTxA$7-9#w2h-^jGPJ<Q|vm
zfpksC1U;XPludj*$AL)W101<VNZ@d>n!&pj!pKal%q6OCL&to+kRle{mSg0JgsX|A
zgT_J=mH+x`?N~#Z&$(aZ3whNa*m}d*t3oq1D1X0uhC}O#HctRsOmuf?ZclOMzR6^~
zEG@_OJ&S=Y-=VD72P6ShYI=iMwY&sL%1m0i{nb?3=*^+rZW>=3Kz&0cTascu>*V@e
zv{VOs$+i#ryoJ2Rm1!<~2I?ij_b_yhGEH_Ft?xbFFVDA6om=bU%F$!Ig(Dfxbk^5a
z-Zi9`vUEV-s|4ud{vV&ec>e6gus=LKdo~#MpFY3){qW=r+0>lOri4~nO|r2<TWB5;
zJFP6VZ8A^-%Ykxj3ilqHYT^+^4v6qTL6#MQ0jI0cIdahm5or;J9Zsptk1!66SKs_)
zEr+lgRvg_BEvO2**y2al1eL9tK`{?h4J@}aWF2ZOZ4;Wm)zdZhgkh1pkyH*<gTbyK
z0_JeZB(2FZ-QAuP35nIXVuH)kP!T9n_s~c*iI`WEpMeg&y3)tRt(GBi$$SxAPcFcE
zY}`hFPgAs!m+rc=?xCC8T0$J^Qyf%6{G_jKDjU61o?y4)b#Ar<Q+FfQJhR{v=iF1K
z4457eSFcp9j8>Uz<mN`^=^3r0UNoX)R;1yscooxm>o#DLYgiZ!h<Gv_S#1v!O4}t^
z15SonvSB%qml<n~H3QqIbYA3qBgI~K79OVM^DI2}VL9EAdCcNmE>a++Hs9s4sBK?g
zPN+j@V879Ux`#d>5aePqL97?7*?tm`cm#};PrBIY$r_x*c6NO^$5Dp+abz%tk2{Bk
zxy9w?l{NErhCe8|56vEvNguy6P|?x)0<XpmFWcO<*<Uu2k17nUnS4}@X_yM+JKQ2r
zvhnfp9YqIyI~O0)8~&7TeQYh%`A}KI+%Bp`5i5kQbC^kyvF7}Iws9_x-O9rA#sa1r
zrU<9>8!Ug%m?uA&wHT}yJFo*=E~u%8MynyXtH2;`@=aL7)ZJPCwrQt0?z;Qf+sv6u
zx)D^7gHh5BN)N8~11E#+ozjPfz}I)NlDObP6*$7R*~}ixawgf@e?ex0e%EB?+=PgX
zW)mzn%_bmWoOMuD;jlwZDQGxLEw1f=5~?BRjj<}U4E~i3U^y|P0kblVCivU)$tapQ
zTQxfq1tZL43;v8fH2*EJDQ}W^KYFL=Jh&3urJhi_P$HAF>9@T&Au~JkEtyDSR%oE4
zHXLE9$2`Bf#q083s5WwXJsq2_y|XjaFY+W<ac-XizYsK^q}X*bsM@ZXg3QI)TSLq;
z>UPrlC_u+S<Esh*tOHuij6$`NKZp&YIzJ>qmo=nZ6OS8R)U|0YHH=5t(YlMFi3uB_
zoQo@8KIkCeebX*fM4xxi5Bv|9iEWL2W`n@D9=3P)6S}w}gsNzy>(kYq8Jy6Sem>36
zZ|_XZ>;ij!J2F{vpyGR_9ufueWwGJV;2M-Sa%s%F%Q9QDzE&ttyD^Y_w&F>qtwN#|
zipZ`m+M2>dL$46Q;>u@|!U{hP6J(Co=3nQWUAf?<9H}@4*O&0#&~AWxMP6Y@=rpuB
zg)B*Of@yqCZp{@qIsQsGhM}a<tPz)ct29_c)i6SoMaAwEE7u0P=G6?BILA)w#OpSt
z1vJm6yC0P<SOq6D-Bm=khUg(k;EDs;lxtfSQ!mEZfcPL|@iELnm%~~G*E=lr*c_fg
zH;Z0*p-F5a;p}q1nqHy~RlQ(GyZL7nxbvXfY^9sb@y1QJ*?1kYn(tSg9JxXK?F?)>
zy54PIrNP=P=}IhFEbFw;^r%=aoE3PJC8aldk=P#J9Te#^q~vsRhexPQ>ZPkhW_rv~
zSvJUgD<`h)YMaTH@Z9C@$mpIfwTLCdVYx7T^*R_5gKOgSV0Yi@^pZ(1pJ(Vu3$<rU
zjn@S(<V0kZVTBmi(3huJ4M~L2SW?8-6n-H^TZO;QqR-Yum?0^mXBQ4ssygU<(q6b3
z<b82-7#MoEvlt>1g&ThP)J`P#`E?aQKavUTSY~H;3qHTzJ)Gza%X9A;@j7L{1oOE^
zSQdl<7#QR~6IMM^&9DiOjHJW)t7Bt~vGLfLmet^Rc+4-|_fUk4?HIE~7Rh_gc-B~}
zf))p@phYMWtw@~CDvw#DUfW~C7#QQ$K_2{?|5SlNTH5l=Y=ZLwJ;%w#aseIdIZrTk
zml7Ukl{L6XkRtmVyU;b`oqcpSH!y~evl10;8!xM2d2F6KuG7gR!E$%g-3(m27FXIs
z#z~h}>{18PhUSO5iu6c|2|pd(F^56a2b9M`MR00x@}-?@?vK{f>%ut=6Zq(GxSq30
z0#pTkV{lE*8=6CvU+6=`LzI3X&&i84=JQA=eU!F(*7I)=O;k=r2UxcSjiD|;*~Q^4
z%*y9S+BH@YUtgz^dy&vG+ag23a=SN?C9d*)hI`?A7*~R8jOJcd`C19<RmzK;@d`%g
zyHDVQ|Lx1&hx>PL-XC_K-hBA{<GcG%PS?FkFji!XOlMyAl7>Dk4NTca8bi(Rs_Q;A
zRPGr5{76203)m>!<fXF3eqgeo%@tIBz6au3A6lCXwu{wtH~@wix8^>7>#gAvqB`I+
zFhS6ZZY8CFM(6SpX=k4^LUk6#Hls*H5l|Kj<vz*<n~+m+!Px^zm<PFAc1J}gV51hM
z$lOFzq!ukX3HZ9@>+*Zoy;J)}=%&MetwPe+uL&p=#plRYN;@+jNBZZ?cm>LPJIYyf
zo=zF48|<CXA4EXEO*>s<qQ$=<7)5^ZMMEGZ+4rE!5VLuyATrprWmLOp1Xv}%R~m;V
zFJ7=v?|M1A?F9fX7Y&dRk#HD(NHl>aLZ4^RPe-s9$b>^87kU7;>m#A=G0oE@8GCH2
zmVTf4<J3hS2+;V`G9S08O<DAeXg=xvk6wPV11MtIk<aHpQBJyFe5i4!Sas|!(c}8j
z6}bI^JO*>_<3^bw6k-LZj7D#u|K&AG<E}T0D_HSfpKq@A)UR8r2W&aG?jvRnLGfF;
zYT++bxQzzkjfkZg42xVC#Eq@uy7{kXEGirFy~a)Ty@F+2Ww?6-_VgmZ$j}IJDCu-T
zzx(b|=xI^pWuJ&4)$)VzQ1c><+EUu|BVfEXf8jFC>yay2L51m5O=4X1U~AICS{cX5
z0wHX$!m!}V3rE2&znD3!rAHlOxF<RtV>CoNR0>CcOf2c`RtsR2x&StW4FapV?m7*2
z+f*-^yi!%dx&_lrg4n4r6W635U0j3&@~ygM)rmc_=z(n`%iv2YM$T=|=B#gAi_eve
zN>&p*EX!tSs@onx6VEE_F1Ec0T&7ce7#dC0Ii6s^@aK3A=@K8#BtrOaZyDxokHM;a
z!H6RFkb+VVweg^Ka!t8`OQ<82F{PqSaI8^Wr!sb0$%+q{ZKd%r36d`SngS0OuFToC
zg3f@Ks<#&%EckE#-230oma9&D!Gphuydhq8sUU|zw2Y27DJ4dBTyk#%?MrO?2KN(J
z+OENIg-(sN4w1shrh?8Z_QhIldWV8!!G$GRY5f|@yF<_QZZloXkx^M?XHI^8{x|y%
z0xDODmbgho@)StfgytjFJ;yqbcpe~ij<2Xf7i-M#>{8uqk}`9|H{KVw79FY^Y3!se
z-_pwi1SGS>pB~;vLGyvw+tZegAoie4l#S8&_B4>j5e$q1f>6PrQlhnh`Ib6QOy&Em
zyK1=ZBOZj8P2aev(kmo`)O$OELKArsw)b!DzkEK-e*EeFfAvzMvX35SD>!66Vnzk}
zFcK@kTUusixFXm_w1cengOUHZ!B1t%J?*KpUkJIK3!YqTpw-4d5g|vSO7|Jr#o!im
zbqNL?siFFVvzJI2n)2B)l^ME{JBjF1sAMSatd~e|!b4^~K2v@eI?p8l8f|2zdiRm}
zg+@jeGAXV~iKzl;5_yy$<3i`DH&2I}Fs&jM1s!PvD`nk2FwDj7QjzBtWO5FOM)s6|
zbon&@#=i8;fb=VnGu$*TsftcGImz7QEt-d{&pom~LaAGVr57~pq4EGO=d;Zv3U`=(
zumezpWEqy9M4B!NHWsU;x#p#1n?-%lCZpQ`>V`tjf+C`lyLj#27(6@{_q61E%QN46
z3Q|T72<2n~$Sj_kN5L3Q`8Xdhzx?<etT4KQW((Rogn@zfmhNDatM%q;BJC&)ZP*=G
zlRnF<SF8Xrt%T}(g4CVkoix(pFra=g?sNn>(o0XU^TM2(8S=Z?!+jkaY=VRz*_DFY
zHuZtNYO<jv%<f=mBY0+RcmHAy2IfK9g8%2g|NY(jJK3qY@yXTfwq_Od-<thG(gNFn
z*roUw|CTmfpFxCgdo~N(+s%3r=Tj-^cJTJVGm1bO1l@_NjaR!IX~ZpHdacpj!gSI>
zl?$luNvq*uGKh7fBT1}T!{5H{qz6F2ZE;bLjpLF@J$^#kYV|{K^>Rkh%dO}S_AU4}
zO8Q=Lo5v>y{9t%bqm#xRqOLXyb|-g?&HRAoLTL|`?0<91Q|Myea>MEDqGwmTV^y7~
z4UoFWQi^G|F>naf<5*d71Y$Guez!aC@lJRGiHG6VW@cLn!sBkgb^1;a7EpttEtay%
z^y=m^={$0giBijNXix8ks>TH5Yt@D=I1;zV`0F_5$GVs~hGjK|i+PVDf__#P+92`D
z6e+E2(w>p41=O@kjPi`P!_uyRaRa|Y?S<FO#;Aty=Kjr&TDiaNes(;dGL1vVk%kki
zk<s?lgprwLwACRgmCts}lH10yA~0-hwYKf30DW55Zg^$81`TZ=C936OMaL;nw5x5;
z*a5SGxJKD8^c{RgQHUCkfiDz|B!wKgiTZFRRzA!7hf37jIsB#c7iG6%V>JMJ6%Tht
zG48fk*Uj1|H7p~xNeohm7Hqq4K0vASCYcSA5g<(MyrBf^9;0{^4WMoeK0!%kbgeOy
z>)gHq4TUfAP_jq5N@#$I#@fJPzNULTpc6<hWDAP7IJ?O!F`mCCGCYUCsdB=Rf%ee*
zO~3!g;UD|G!O387^1MIzjUB7tY*w&2mME+(=<R7b=En6wv_=!;0!o)YCi*w5SG-H0
zKvjGNVm5JNj*n-rKa#xO?@Md}D$YR;dGZJ+7N57+8MhFpn6(89K|K-%L;2b?WH2~3
zn@Tk9RC5|qOO@>|R4Hm-egc}W$RBS@4+A_fOSLOxfpVtb3@)8fq5;w*8-ct)u`?xE
zp1l9~_8;p{cc0(BVZPrAIztdB{7h1wo=UGd@VJ`+Ieu=0n>{!R{9~)bR*=~yErIUP
ziHcPaEH9~?Y?2;06Z=8=%RLd<tB|i>>dA;Jgc?N=sbATB_;pV|{krZ?zpi@}sQQ&-
zkGfUAvU`-X`jy?I%GIyzjtVkgwNCx00`_a4|CI~d|H_r^f92BlzjAH+U%9ybuUy^!
zS1xb=E7y1MmFqkB%Jm(5<@yf3a(xG1xxNTV{3?7NeC7HMzH)sBU%9@6uUy~ZSFZ1n
zS>ry>-@S)Dcyspy1C%~JDmj$w8RQ~n4b-U>ELw81p}Vkg2y}tBV~h78=!3aBK;WTQ
zrQ*M<5&d)eKNFPUl{?>GBJi|lryLo{^H9FSko4tI*!v)0T+a|mc6p7??l9m<S0YzX
zx)ir1zRwbN49-mH7FU9cXDxjKTv1piF|5Iw5}vvET1X6|<;|JwdihchhJyJ9_U$q%
zqmW8kFk@E2f@A}YD?QI-4u&y2m>NETZJ0RHA*qJLE^L`}nb1k!Zq{pJt<M2xRuC%K
zm)D5Ks?;&Zdg-N{^4;_Txy<NsZHmz1+Ghuv)rL{2n4UHeSTjN0iNgf^*9GzzUd}d)
zNzd#pjiSB55K8>-gb@X&z|G^vi7v2~Xfy9`4%jNW;zgk!DS(;@_lzi`iEVJjr%HBf
z_rMUBUa8Ox6t^BF5t(P_>u;V7QNByVVhGA;eC6CZ`F7it%z`PyErZao+0Gvm^Rii*
zf$=_=%AT0IJA>=a#2yu|g4l^625&8fcxZ};&{lT9H7R;|*yr7iOBM)fsHucq?8bZS
zaHlZjWnBhA>P4zXObegM1I%ucW}rMoGUmzYHjvf*BOAbkqp-?Q15%~Kid{B@l@7%-
zbAj||5cXQHhWi7B%@7{j9rRXF4bY4$TBXVh-xG?shdIh3?xEl(7cV3GbOuv9+zd9a
z9^?O1bm<S$D)7e#nU9|&3v8%xv4@eUFFP+}6)pf&M9FL$2!)9@8>1>Ng=G@+3<Jkt
zI6+>`1{sFtV0?w#*QCUvvu;{%X1c3knu&xQkW9T2;B!vkS!5_ywpM^LT=#J;uc&B7
zqDlB9pe<`Ichenc&hEUaO*DEGFg+&GFHC}Kj^|5MMbz_XNHknTOycGFL?#mwUS4RW
zxO7xYY%kWwv=Rd8T@<TGY^C_)al`a;_9o&szi9SPxM^)ae);tF4hY<rHcGx5F0P@?
zCYXsyw@Z{P##G7T+{bRiUOz|T)X6PU=<;+#bgI(B>1ea0AW6I7#Hs>ml$@j)RZ}<T
z%}=U8>TGF?PrCJk_#lX<*<BTsNYpe1sJM=9>U4+m)7>E_3RrD-FQXRQ<92K&c@8e!
z@2Np>`w4Yl3-A>6!Ikx2gy~}f7pSyNB}AImQK4|SWxH)&IYWpF3T<RsUg~d=nzuBO
zb-{fOxl4=q?2}&#;65=N@Jeg)Lm?g%=MTJAWoeamz;uaYMg?OKiJqF79E)^TQiftJ
znxKNXUQJF{Z7q`Mu0Z-QW9jhL+10wG!)^e5CJ?mo5O#EdP1%@z`h88vk4jI@j2W=E
zA!7mfQoJUU2`@s048&SgGr=OXmMYr7g$o&y<{O%mbaOg|aL^(Wc5}X;yAOYI51*Sl
zsXMSf!Suy?u{VLhRjgGFQ+Gf96mhuP&5@%`W73;>YP06V&3>+&H~w2+L(&pPvw?qz
z97>3kI~wdz<hcwKEZg%yonMYbbR;<3vlbCNL%?uzlQp5~Be450)Xfbdxa*JR7ZyO>
zfTJ%*!gc23Et2!n+CwFHh_lgOUU!0o;M#_Sh}wocgYcyF2=>QNCayHef*YsqF?meq
zYl)VTMfwQ;PXgS48b;R%)7>3QhW)_J2uXHpXQ|XZ(nZr5FxGgQ!+`*5<=gEjso(2n
zeHj*jAGf;&U0W>2SGSLm%=>Z+LxEq*-qvcvQq;Gd^jt>&<*xl--*wQ7#W6?pa2Sd!
zeFDk7Oymq1KoQC6QaxacMzW%OS`~z_20Y?{Vyfw}1gPTr(HG|W`rDh&_b9_+n}hC0
z+nf3*;HL3*Es1jmsxE-&nk<;*7W<0H3br`Be)2Mv8X*~XQJp1Yp4HJ}6-4i<KHZ6>
z^!vhJ3(Xxk0uPA6;(+kd>3;W`qbQD=3S@g#tUD+~({3Mp6aeXyF^eoLTY9dXpa`aB
zBL|H=kLjqIe9e|?3U@f`GH+WfTnAK#nB~q~)?x~YWB@co`q{ud!;0mQL*}!MBKNA%
zBJsD0R~$1Q08iqKL141KIy}d|F_o@SVJJNp{?NyRa~{6yzYv=9wBZ-{a6Pf7*)7od
zw`0_<3+&_$zD`$DcZoM%RhGNL3C4=8rfRE1<iZIi$l5u50ht<ve_yf4no6ET#gpUR
z8u**J{q@Y4eLtJ7U;vxWH%;ca3Dx7OgnI*t+YoefzP&J9gR~NFN_U|Gjqzw013UT{
zGOtGCFP}c&FYiA5aQ}CBgY9HYzWel9;sd5hu1hF{e2&8vVA5`2^VUu@V|xmBYwiOa
z&ih643k!gK+;njzM>+jN6;Ec7x^{(qoiqJe0tNC?7lrgUbUcmCuO{14{0R~t61mD4
zKojS&2a?Bb>BT0J04fHq`>_t5Tn>`0?sO)JCt@xNFK50O1PLKMKp4MZIe=%vzz8Ez
zIoXLME@&I{tel}Ytfh3-RSL899;reW3{*g}0ag=m@)_EJ?oOKAz*7`RgChn1DfzQD
zR5!IIuh8<vG;>bXtm(4gNC?YMJvI_Q4^IoC24iZfWEb)p*RHCX)lnhGO4-qvXgLTG
zTd}xajo>h|MGOIb(-G(|#az2xC%_eIwV{d%sthXh2qws^=s~e6Loh9X^hgs#+Q12`
z9eqKlvMWJDQpaI<*aB+Yu0Or|_~{+IJP)R1DVhqjd$7;}jv$^DQdU7v#SjVQ)kP-k
z@<Nj?HdKDa%Bh5<vzTKdZT2)sM&!VjCRj_Z8A!>ii*5XO)sD42?)k(99;`J`uvVoi
zxV}LiwoB%cPpCx^INYvg>pp)5{<@_3U{{Tfrg+ej-L3nUQDi6x<qqP<a4<$CGNc`+
z9-~he+U#N9XMU0Ju*c|uGUz5ZTlv_##|R{_3uKf8cM3A<@m`nX4Uz@sukqYZa6(!x
z6R%52pIb|<S{fziR*o8>De}=FX||C}q@ja<!?yQO7xier^jOXyPESO|fPS)8y;BI+
zSax*Kyc+h4ARnpF45Ld~p_#a|TMVf2MTzt3O5d$;M8@4wxzZBWn^27*1WqLFriF(K
zvv+heiB{)#!7cKwbI;^2b+1e4n0;VKsBSFM0ZRTdPYVynwnx{oE>xC^w7BP9&OTeG
zsl|}zL8_V6b%ng=ze>48o;xcSh$E<j(G-3=I%wWB4X$x^AM3c%QrI+^Mmo`eQnzD%
z<pYnmg@B2ZYqUjLMJffYBK1}wF($=>v6{AXZ6OD&+BGC4o!Y>Nh1{&^h;lPv2`g}q
zM-5nuq^)sVOK~)G#`f`+MrfZXnCovg%R#TahI-uN^b?7T(gH<;rp?#`1|kAkaHbe9
zBEJ~TXk<8zAgz3@+hw4{q<;%)-P(o?pie{PyS&=Y3RV?^ghEclOt~i;ysGvSGw@$C
zRau>sKQ$G|U{V<Zneb+KW6{M<d*8S;HM*w{n<tZ7WHxHnE&78~M#<{6!UQ)#U7{?`
zk5exk-FleQ)6l0JgNIh-7<~97<${i(NhO1Kz*7Ey{@rjVqk;@3yY<x7W>IY^Xi_Kw
zokY1NP{?DxTgB;W1Xx7o;zmgzVg7)@*`3h9X<**qV~nU@2!a0(eEd;;7V2$KWhSUD
z;otma@!|9Rn-6dAzWECr3jcu9DZ-BMz!}88X76|Rf4unj`TLLmKDmESC-nM;f9d^a
zFFTprKsU1$>K)8hSDV)d)RuSI!ljc2&}g{jBy^`wzYs=}s2~-^S;5Sj-N-z)Gg!MM
zcBOJ}(v7|3Vp~An;u9{{a}S;|cTG?{5T`EfSW<!ev1v?^Qs?Ik`Fc1vVhWXT-#JqA
zU}YjJ<$5>qN;;^F>aqvw2X5h@a3DX5q8289q(&1q`~WoVd-nktuws5>Ky*KUG#fXl
z^MhyO6njK@!2}A2OIVVussM=z3`vq%nvI$;GF;|NI@wNp)s^7s+iM#b(8`>^i>M0O
z#<&R3#51oU3UCaR*l>W0URPsYvXHr&nJlze8JL!7`!khJ<4{*qq3;olO7-KJL7-QH
z+G_=Oa0)hgn#AJ@l_IKlz@aqRkqp#((<cYxtDuBD6IHWMo^93v!ayhFEXzyv0GYQC
z>K=aSNQMA};Fp51H0lM!C`#}9Huv*DFL{E}7&U6vh@|q6UMzIe#qaAY=(fgTR#%4d
zQB!m02opffQym^Vs3bFemuF4!i0Qb}d=%kph#0?y72vSnT(z`-dW<KJ_IU2N(qmk+
z=_OEFnX|*yS`vQJDcX+FBGC+Mdj>(x_>Hqvb_4v>^Ycpe58!erzHjzx+yeRs8N$~z
z11i?nm^1f==P|0NIUElq`77HstID)L9NeO6IBS(E=l-F0`o|ZiC(oWfJAHa~+8>-g
zdwP2J&2Vr!9}a%jJG~kw2TkmLZgiN_7Z5!h&goZckds|5eU4RBE9IZuYy>un=ovc}
zSDG2EOk{=-Bku$Y^#fQwh-~QfW;Tb-V}!it5rY`bm`a0$BuKGi_ic(l5`ohs1AlSK
zY+sgQt6t7WZC*{*noTKVo<bf3Pi`Zi!0l?G#Yw!sYSeddV~Slug|sHOBrYjhgHZ_{
zsM#L8PqV$#o`hG1Yh$y2xG*-`&!GLnS}9X3v9?k{v(P&QE7#ly8k7P<fP@F!&Ilyf
z0oj2dUU!ZTE9EKP?4&z&T*F+2%x_m#qUR|Q4lK5K+%{NudA?VuN0gC3ci0U95j|30
z9R-eSt;(Japl+!B9k7WRM?^0aI8Cw4mZ{^9s8x^ju<0}p7Pt~>a^ouFe=(=n<~*Bd
zn;|M&p{?UGbb{OTPz8YPH%4KM6C~Two-wlw6e0OIflvcGNaI?=8L@bqnYLlCG1Zfo
zgK!2%LQv^!DTf2)60mB^`o>5)--SU5rZI~%!GLgpT-?kNS#{ZKH)(8)nl_1a3Q}K$
zXmqw)$g<9Iqe$>@!A;=T=zzsRdy;*TD{HpZ@(kLgR~o;`A}XVm&T#3_G`l{gJ1Mn@
z|Av@do%G?Fe(CIzYoX5jqN$>uO$M+;Vb_4fyOaX}u82rPSL~@4)Q1s_nHg~54d*2g
zNCb_mCjGmC(}RnQ#870|y8H0`N2G)LU!QmH-u`3q@x$NV{lIbx#uckD$PV_=unJN@
zDm74(Y;}|dQ9*uG1R!?vVw(a5k8HR2mXfO}yGrXTvnUd{yS|XT_xE>i-`|6~e*EFf
z`}aTHe{y<fmiD1@7;%+1sMkVmE`d-z!8Dy@TY<{V5aA^w+~>CfsH^*N9`l%?JXpaJ
zzD=1lymSYO*$}{<9ST|IF@oDA$k*&@J{`RlIV1KbA5K$t^Pv5eUYx}Z#tVUq!3M4)
z3kR06r~lL<3prC8W;#S6VppbMHF#o@-b_vr-d|qinK#2bY{(t_c7pkI^0SCRKr?fF
zwT%Te(tp8pN^5yCoyv61$Nqxl^nsfmGMqL`w5}$vC**AKU9qFKKd(;6z?_VFrvHgc
zO%?e_VO{H_C?T3AWqI(dV(~kr6D!S6C4!08lt6nFZFY(-W_dP>ORd+7lsCKRW-fPf
zBZ3nuzxA=ItRJA&KpJ?k&Z^@>YZo+-XCYW1UXbocsAnAFXKvACXt1L>T&8%8)(j2`
zc41<v+xIERSDb{{NYH|U`Mic8INm0*M+%k&-UT|mc!q2QSzZD0Bl?N#tU-2=jAU``
z5w@~MpoS3K09My?oX*?7fBbZR_~+f*`;VVK>+7K$cqH~^gj^S3h3x#$*JQ3nFMzMu
zWV>yeR4b6?I6fy#6BATj#<6b%zidqVjn108*+h(r{}znj4ZI`tTSy*SERt<)TDpm&
zu|$}%T|<#=5Vs?t@Z79}evw}7>1+n2N0?kfkx&uj<(NGiZ|dlvg%W3afvku-WXTq?
zR4sb55R`6x{IS?gjQJ=U)GOw!;m@RL;4w+cvqaS8Ve;emkKg|Iy*PgU{qvuV1~FZl
zcn%jTKD_zvJxcrV7D_k3LQtvyUUr$j``po|RY|K~Nr8^~(7caeM?o}!=HA>RnYs<?
z!ro)M#3!T0pO?2b@{%<+J7$+k8e$h6jzJccRFCG#nkIMk(EH8ErNGm|5Oylxf!Yvu
zq>ov`jIm6?#P!P?K)u%(-18l6r^p^wiS-Sb`fCGaS1N2mEUoE0Ex5Lo0^XYuRqHw6
zNt+o>pbZ;p7Fi=DS%#G#_3x<FSC$>bMc>28p8EaZMl2sjB!KfPt%7ZcXGdI=xECsz
zF|>Y8HkL~>79f4U&0$Lzv3DYG6*i$^v#WeLUwmZ=vNsw})btP6^8=(e3e_x_|GD9v
zU+81i-z${)WW<%=bOVFmd!IoCmVzi<3C^@|vWd{Y4RuCP32bqG(JPx-DeSeE6me!3
z`ctOt*`lgg!f@y1jT^2y<cafnb0IIT@`t$C7tWVd6#HpHUU|*3i0?jp`HXn7?&ka?
zn*?_dDRZ?+&7JhurPPi@ZVuFdO}u7Uj3qcN-94Ky-B9jr;5hgk4u{8-zonytZVYP|
zie)wKC?U;R%<+SE2s*AZu*P+8Zi)Z~N@<%92;X$H9b!z%1%2Eli1)fj5MQCf1FKnI
z$6s7%-s1p>0Je+qRu*>A6xWg+>!XkJ161m%eVv_lhikngS@M*}lO{dfYU(har!zQz
z?$52wDHB8fkB6IyIyJzyKa;)Ek!X;x=oC1C=%r31N-%v9h9_qf*Ss|RVL;rPEx+yk
z@A3w5j?#vaK7Q#`$m8>#o2shDwhrBW?yAv=vea(RQQX=ww!4RJPABB{a@?p(Eky^}
z1whnSXpDy4mIt|48q3#OSoHzF^DT;zA+D|3I5kX<G&k>yBSfC#u3&aF!zD|KXU+rl
zdfJeUMh(WP3x+se2C317pm|?mL;Qc2qR1{JDN4KpANvbZ)B`s?Bt@nD*K*n%l2Aoy
z@#Ebz`64x*_cD|{Ak}K#LV#tJLod9OE;VzQcnLJn?@vzWwoMfmVNbMEyt@FTC&vQN
z*B@&HBO6n+WWv@udXINX7(r$YG!7G*@F6#q*w8qFZ1hx^Xz(7IP}LiPcQO!Ja8b(J
ztCykbNm+Zy1%b`Pzb_yiXv5{E4chGX=@Py~bouo8rghGa+MONlv~-uojux=kHq!^T
zO$F1tH`Ap@6dQw4T<i0=J0qjxz=D(_bxRHM5rhf?$ndld)2I$4?$p{vHTLdP{D6i&
zZ$r)+5*wA#1XDiCPq%Q4(P>vP=m>VL%1T8w-EQx8E2mq)yf6`{gmO}n^@pKxu`Y52
z4dJ`WTtTAh+Z&#3`WL0b+f4~uJe+LcjL?9Lkg&}BBEoSZuF`$G1y%~`qaHiQg`jz|
za#7$?8CbBZ>d+AvZ5Ty{NP5niL^puG)K)}_s)QU^Tc|s{@bW_%k=#X(Z0?WJ16UK}
zv0d)x6<3-9Qu_$XQy6f4tv;FXQ+M&~H0dtRD4Xodz>iZC=F7aMuz@lpr0Hvy{0ZtQ
z(?m4=4GR4Vh%hxQRP!!Sa<{%YQRqf5%~Ia`AdR(a*44F<5je}jPk3`Zn<`aAyIG$~
zB@(vbE~pl@+N9xVMn3o=dmAqt&$Q;Z2Q#Q*<&i78yM(L^s+@2z%i{UQWb*I<X5Xnz
zO@J+tw2qq`^0C#b%|U7uDNz-6PlZ@@20YZ|(Q3222FsnZWky5FjAbMiHd{=<v3k}H
za*QW&Ln+S@70M>5U+p)OS+AolL>m;)g=-)(l<L#TwF=AOp?3il#pdD^G_`D@(gJiA
z^iKl1NtU*kLz>RJ{aBZz#$!+$^{7^1I3H@BDs*ka@(SsK7qi*SiEfp#K=IP`wAXM;
z)UR%x`E&<QpEdL8(r=lT5Fpxqy6NSgLNe`iH$ioJY$ljirAahUPu#GKhp3)q0(VvA
zRTLDjryD}>I2=`Myo<?}@+jSC*Kq166?;dzXe_~Urf`d={AJ^zvasLRi`}_NM}%i=
zXc|^(m>$ksm5<`4NXD9_!vs=ipwGo9>K>hiDW5hDb0)yqEz*!$fF)WJTDm}%X@tZI
zr7NurKMz42rrt$xhghnzLA{WQj7jBEmRjEBZF%bvhiHL^Y8y^;HxL^tGd$wfGIx=@
zXx$&JgxIv3@*gfb<5}c?&_x<GeVj@LgMg;&-t3}B=aX-uxS!2Uuid2A=x|{eGXk16
z^T}*wqD9%Fex$HU5lb37lhG$%s)wXtXlvZ|&0qC!J345v9YP^_--bh1<5}bL)dZ1w
z`1(jq-*J!QR0o}Vi1tCK+LSJGD0_{Umo|0KpL#gLdoM|=<3BOrl*%j5uExf<ZQp2w
z|1ySdWT0<W%_wJ)E^W>`Jn%BPWM*=v3IP?zF@;jH{Dq?o4gy*Wt2H#MDi6(+QQJP2
zI6=*%afM#f@>v`aqZ2RudIHZv!^><vcb=u}qs0(qi%L@E3GU`-B-w`&Tv}P}aXr`t
z|07-WT=6YnEU<Ps6QKnxoe``>6PCFU$}KpV+gTmqFQ9DngzDL*Rq!ehDDV(*N2Czg
z7RWtPhIRi+dBHPdGe<am@He(<JZKqc42lC1Z&jY{cbD6vUM`2A8XG${RPL%zB5&g5
z)21sJ`<r^ZHe9#y{N0RRr(`hImGA;L;(S8>aFLO8rMc&Pp{Do&u_86ug#NsEA)ODJ
z`>O@^;gGW-T_rO_2kgb={t9c~ZUT>RwPxKK%H<U|#!)pv=|D{m8J*#y398W$1@T?N
z#G-zSt|^N-NeIXCP97lx^~gB1%W&3Lh||BW+5F?(^px^YZcc0sQ+I7qceXA=z_oR@
znCJyUl<YW(D=n{c&5VqN8mqbz++FYGd1}ci<a&xMLtGbZFR<sAAX76aM=y~Ee2x62
z*YNIp2)?*Nal~+$P`aDt)p`GfA#D1x$o}ReEM00q`cN~Z3_JCv36|%@$!}-(1XFh$
zN8l83ih*5ltrGPzJ};~J_zJXY1;;7$Hj7o`5b$D@h2rI@G2yud2TNN$!$vzg+;$*^
zPr)|myAw=<)vL2HadT$OeQr6EH?gvWtS<NBR^mc)2`?FNn~&)%Q{X-?4fPe|%J3>Q
zO|BQP>*%u|O5Q`pwlKT@+m|<=?hc<me!SPMaA!-q)Y;yP{g|;{rg4hAW3e|Hee~6i
zk<;;--%!j@0Z>Ph8Gg%ZyM~u22=ZhMjfSkg-ke+0sV#lHtKNVbcB#o~Ec6ST?7Xa-
z7wOYz>}P!z6iT2ka5c*Kw7QRd*#(I7eus2-=U2PMh;~>fxo)*&i6YFe`7yhTINd#t
z<SUX3xx@7W;gI{ycl!7wSnlrH(m`iJung1<+P%(kc=5-$(i9#JAMWnHNB-yK(k9&0
zv_;MpJGBuzJiDB{22R*Di!`LRo2@UF-8^u9M46m40QaD54!DLDA6WXP7wDwPauk3u
zLpSh<+QJuxZ0;JS`chVF!txtDrJB3K$CYM8FDYYWngd8MJuX&$j4jy?3{(y)LDV_8
zxgnwhq2C@2lWb%D!r?R7(JzlZqAZ$6P>D*GeXmrb0%~f%F8d&K;<YxGN^;&o6{^dH
z0|p*LVllbUukwtUy|+6}Q-awfq;PK6fKmaPl^Wu(T;1zqE%m(+R5V)G_u8e{N2z;r
zjJ&49?HF#8jw{Ff&{gX|_BR?!Q@#*6{mK{GrE0A=^vh&`Pz8rRPbjMCS5(jq2Rf~=
z;9w}R@T=Wyq;tJ$@j*$a^YkIJ2mK=39YE<USO%Mnk1DXXglGk_&@wkMg`ETUYM}Zb
z4pF7L#qreuSE-p-`^Dm~rw!ww(hnBUgw(s~vd=SZH!>I0;#%`UzIC~fPi>iVC^x7V
z7nF7*WDp!d?{t{I`|$4b-*voPjF5-0Y8J_o%6|D0XiaoUS9+RG7fYV9IY4YIuKQ1A
zVM>l}wWlkWz5wYXO<q!Hn!8rGBB5;3YvEdsNR8cO1aaA>8&XWq_D2WgQ6r=nONs52
zB^Ml*jjGSaF_0_3Rujk1Dh3#(2cEdz2L!G3iU@TOn$xPy{jkAVsN0qKNce-(!P6?$
zsMrANNrg<pwe`4M9UdGYz*R<;;qJkVEW<`d7OK4FSJyeXWdQqCNpDav!RMJ0=kH*&
zhxozFQ^UdGzW2K)+R6ByRFL7%JzExVRYe8C&6HI-X=Zi5#U@bSnohjg>V;_o>}Y&p
zI|m|jcD*TQKg8_})#G^hQ0lF%gSl0m=mD*rF=3JIbNc_2xG$IE(d6ZpVz@}9IX8q0
zcw7l3<BX&K?d85YVjCbE74V<MEqRFG2nN08QwoB_4bteK8#&4~MmfD3y}f_;&%4dt
zk00;vZr=Rk?#oZw#Rc%qeFYW=hN*ZhT?32^+yw>mQ}I4>K}f7&%D>IDgyp0MUs!d}
zKqVK038(qQijjmd#U7oOc?Fvh?&v+H`j>ZcwW{1c5^E9Le5rQND-_dZT!AThJ3DGL
z*H_Ek=p2Q$M#y%C)iKO#v^r@<*fMm@v(?4ba(Y^G_`<PNs>3?y`Q=Fp(`J1s1Tpkf
zz37xYs95h7I6u~v^ZwMh(nE<2q8IK7%8)w~6&M^8jh{aLWccfcdxS8Uo22B+nz?{^
zrRh^pshXs`XCU|k*^>&Pe2&=V`ci|pNdi|2t)<6(yZ%vZn})ms20<KIXh!40?tb%O
z{^`w+cZ=_J&QLpRHU$V&*`zR_i6fA-RBc$Mu8JBR?`CTOim=^U!5JN2`PvbO)p^!q
zhD{lsq-zb>8P>{+qJJvwYwvL~a7UP<v)$=ZkI+(6*=;!+9#DJd4jMbh3zUar*wqF~
z{z@hGd>q;$m(y)GDuAa_cg!I*Dq#<qC@^h^D|=NWS9%P(1clchAcgOzR_5ig@)eN3
z%Q=|f@}+)H{(v+C*7Zs6n_lYLNZHic{dYacl&IK)!aY1sk$v|mE_;8n=HMhpCoV#q
zBp;@tNfRo5#pC~qWD7<|q!|{;(J#~TP8+RyOkj>zJ}n&RQ;Yf;)d4;uk@Wg}q@CJm
zvyJMGK+gOt;z7G5<Qg}~seYRPCU7~AK}WqTEPyK+e!be5cbS`s<1IEKVknw+mIhGB
z2JWm5u5r$cNZ5d2n5?UQ#2u#z@@+QS?M@N6i0~==?a19-!8M{-9~S&$roIU<*|3~P
zU@?KNLUHj`Yqo}ZgE5ka-IYgi$ns$7vGE4JFB@aW3S6=leB8c~NIyi_H3F*lNT8or
zi96-LpxxJPwodVp)7`~}Ii@zZ_`yRHQ{XvVQWyGFF!ryL{?)2xaxYO}VrA2P61mcA
zn5J5jS$bd>XIu?acX0{e9PyVicz&oCR!mkabD(a>GX}<Y@b!4jyKKG=2WMcjRu?`S
zGrDvGVc*=}e|q=bm-{>TZ_rEi!^cl|_g_AJKm<^1F59`OUIByYL19Jt1p4MLTc`|}
zOvM4XvzUTlBW<!wD{S!C<(UxcykXRVg$$K`ZVgaggg82)ihRB<XpyDe$G>FLoGYr@
z)Hm=Z_79AC&`#o2z$@;cBE!Pb0>K`zJh@Si$!I;f-1SV>DVy{@6C;`S1ld$}a90Rs
zuLyT4(=q9z#lO1<3wQswZ@>Kb<vm#7O12f?$M^R}N>FDP4Rrr!c)6Y0b(@BxMdR8s
z1%PcCdP6;hw`jp!V3N44=&m&1E}MihO<}WJUNB#F)7p8Qn=ulgXaiC_s0$hnh8=J{
zFc~T?uV%Ls6g)hvkv$4kOFXd4`E}Hqz4RoSLv!xn*-lbF>zPVKzcmYmq|h`;R3N=y
zT5a5m`nxGPIBW4@A%osZN$u>9a^Cpf5I@*_Lk-g_^iuZ?anU8N@@riB?$iS&m>w5`
z{?%gZ@<>WpE)8Wfu?hEG8S6Ce7U7C$DE82+484^thzM?JgR*_4;gL=gi@vq+o-BBk
zSkaQXHM?D>9kJa_L(=?)NAtk9Hd#OcES-w`6#9kcSd0<_;V7`>g!kMR8nS{E1|V0u
zg4J}sIPd)j&e8tq7d)F34e1ECFiayoOrm6|$=>d^u0e?_g+hcj+)#*+jpjm*r%12D
zB8DcuxlzA{WF$frXiyr&_-tXP-t`8jUz|Kh@dP6h*aasJMT;gNA4f?KMeRr=Z_#N`
z=u42KJE=<$pjnqYp*&UJ+omo`6ID~ggaA%iB9l~`EI;iJnto>RB7)CvkybC%$v6T@
zP`M^uU|ShuQ$6Ve4+64-ik}2Z?6&Lqe1+^jm}pQl;)M2064ZcN64|uyS$>OV&2I=&
zSbHmr!`6bOXu}gaTS+81b~a5aMCk&UZkVSNvdnvDr~F!{7T2o^<pnznJ`0W&aO2^h
z7@b%|B`In3NUu|<d&-WPuJqaTra_j=&0&6j`SHW{{^L)Y#o_+ZcFN)sh(ukjz)gdq
zAm23h6^f7s0P)sEJC=99eHCtQuwWyR*k}*OJqyK$@mf1P)uOP)Vi>c1II^@ZXUH{W
zwk?!phns1yKj8UCf8bbA>ak#jX3UqKAk`#vKU2I8RkN(HFN1}bu)V7XHH<-XcZ<Gj
zR~Z(d0eOCfP^CyqFw{zhcqgvhGvO^kN6Dl!8w)dez%L^LDv^iVXb~ekH-jcJh%g06
zYvUpbW!bhnsYH?j<g;WV9ip*XA|2YW1hJJ!`GGOrK0G)oz?qg-CT~$JEmN+M^{hm4
zP~FP`WpbK^frK*{ur#~ej3UmX%{dW<e-c3FPcC4RyhA*Ku?5z&kW;4-aln6{R&=!i
zQuja%)5%Co$y%9y%7o}Vk5@#AEA4^$sq(Wa-cLqC;s?Y7IyKtYMFJ7-9B>}oeD+gM
zG-Bbl6)E?saNjmqUqU1`_ru9)B&NtQI~Mjb@Ut<l^tyTq@ECJ-tqItXPI_}t_GwpU
zWb|;UPU~fos3{DrVJq2GEwQD@ay2)A?=}PJwL(_rZ{#7%Rp8&r#Xw0Vl)JHPW$s%X
z*h*0rd88Qh$K-Qt$Il98B*UwK$wmmowj-d?s7b8x9Rvkus}e5J=Y^W$jf!OHm)(#y
z8+p*9Cd+OcDQ;<4Ecxw942W{(rPx)rYt~Sk1ZmTu?}ju%rdrGFj7Jlu8w#Px>P<tk
zP_Q?c1Qt|7sRvsdBZZD(&J0N;D!6&h3T)3<@*2GYg-j1+J@j^tU!~M9c65P5n;Qfy
zy|4V66c<g3Hv;F5?4pR=8PS5noZXZY=n1zRPwOOvQ`zeu?J*)GUL4($r%4ygpV7j2
zMb|dQeWa6yUZaH7j~{{HM~+BV4WjE$A1NZ^vB`1^I*I10iyj&ib-rOO2MD(>sVRaG
zlrkR`&3vlLl+Y<{x<~ENcuy?29I^tY7jPq8sPK_Unf=s*w92J_MZw?HFg?f)%|7A+
zaNLv^dRPpYStzLLikcK=-1Ffb>!jz4dSq{`jazkd%hN|GiGPv9pHsqblt_Jpgo66a
zbd{zo!tbAJ-=-_UiIi@_CRgu_CGA4g!r^#YPWPy7aC?CIcU3zX4WtovzI_Kpys_<-
zAx;Dy_QM3!_iBpGmgjt5icK_0EX!z~f1no7o|mdXICtQoW(POD^2VB+3D{qH-8H-w
zSSrtQXSLlPUG=atoH0_n+x;a1B@;sXO6rWS;QA)=;h4-Z9qpOgg1&pf5Rq*Q1Yqz>
zsyv5`!CZv``;K<gON^~yA7t1P9~HVV|Dw1Z;G5CQ*?wL3a@!-U5h+7}o<ip|&f=3t
z-|kmqRQx~=Tr`YcFRw=CE8o#>w9*3tJI}ZT)1$>*Sh$)qGvUQoL5dG0N#fo>Eldlv
z3{mM<MOw}pt~Z8@5GRxWceO*?;KoS6+9>gOmGY)E(y8RerZm!73svx^WW~Ttl6pu~
z9$i_OMO@f!^>me2tJNMnHT?Px7U~qoe38@}k^Iq`lUM%7e_)R`o0(fuQZ7URxV^(K
z0xt7FSA@wWcYhqCi#6PYYHV~{LjW})+Pq;c=~Y*WqUe}=!1Wv)qC?9^iXrOM8x278
zX|gmNtxqaUuBO=-nk4E*v&QsG^&Eah!G{Ko_V~C=q6d1BdT}>_YT#el-HkNmMi4_%
zZpyBfR)vuO>9@fkFVAg`lc?b2r<icjP7mFy31oz%NG2q6c}ZU42K7(w4(m5Rn1Z&^
zb~yXaDJJI^ufde(id!X~o6J<&qA5h_7L%CTXyaOIAQBSXDKoM7E;_S3c^m=EV+(5j
zeNP$h(AUaNP*L@}9;`RCIzG1hQ_L115Nn-pvl<JPHkUjrPsB?U4}qm&a-lP@YRNNh
z*7<=e<1~4iZqvV2ral#9u!Qd_i!03+51JmMB*6<or<!NasWT_G2|{mYu@SHQ_-7Vq
z?)|s__A~x}IJl@Q>p=hT;bsF?P|9$G2Af{qGzMh{Z77OqyAkc)yDg}}%>A)b`N}dZ
z&n)4&G~SUA?I@5}g2h-O)DA+2d6wztrAOUFL_WW|qmu^em~sKT8CbOo`7FRyF0QpS
zI&kTo422IuA0G(a4!9m|^qdX>UPE0o7j97W`Gegd0d-5(8h}i{kVA%_I3@bigQ)UL
zl}i!t5QXR5LpEBO8@+xd4CB0S=F8@xPb5nqjU*`-L{^I9x&Wx7@H4c??jN0Heb4C{
zt{&#`YOWrU&7{z*6j(|+c2Q1%9roM)MwvFs=v3I+aHznylu<rVRos8Nd-LNn+scpC
zq*MjJCpR=wVuGOGq8gYtCPv{D6`$GJrC3%eg+0a#&ArFebr#I#bjm^mf`rz~>i&)D
zd}BP01E9wT14Xa<#HQWOH<RX?J<u_aa}5g;SYH{=hh1K$6<qgmK`kciYUBL2sHEC)
ztbie1M6gk4Pdm@d4AgVMLE%WO^a2H=&}1giwKEeoPgO7QS#cR?NA(XO$!>Zv!0`?}
zS(pg80%9|x5PUNptpQB)fJdF!qn!5UB9>OC7M}I!?1u~2lJYVAMje|x1yl)156AgR
zrlO^u)Q(Cpbtg9R=wd}su^DlpjeR)0{pqK}mk;mWe*FIK@E&LEr#J6E_n@$S-aoPU
z1$+p04(B9&dWgq-T?w`qx(DUHQh+#RfkS`(2yA^?@4SdcT=}?o^1DCKmW3^$7sw?`
zXkt%Sb%Bz;$XjR}Aol{{oKkyI&zm`>gEOBpRJoSKT>PQfAVBj*i<7eb4!OV2?A)p$
z`kW+JMeYjd*Qr=9t7C|7%Dj;~&>N$qniD1uV|k{tB_bIe4P47ASvkS<(oFG{-#Fxq
zDz!mbyF7M1<SQ3R>aI!5qurj7Js=}g6ltysx-8TS|9`vCnu&kRdg4K~{w<(BK?eQV
z7T<*&Na>6HlWSn{$$C~LK>{6gEdwH5DtM);dUB{JVP1_ktETPql1JT{?W|6+lwdaa
z(DhAWo6}PgLfK*E8$3A;!Gg?P+bl4mO`Bl;oghjUkzj_x;&^L7s8AJ+AQ$HelNY<q
z?f>s<2J|}Ry%${+8sFC+1f%SXu6w1%l`t?cJbao)o0KeKKrKz)F_`mIHqvIe3{dIT
z_VS*Fx>tEDpT%|x3BOn@jJyS|>`Oi2CUh<^m6*Ls=-}FiR9}dAgZf&eA>tIah{IpB
zyhbXJ5J?a7@+KvRr7aYZ7|%?~v&(0R3|!DZg}y0nY@>ajDmR?)uxpy~S;spYrSygt
zj?|XXNZN_;B{EY!UnfKU$>@udR_q!0|Dz~-izgO+Ey1=W!jeVjdk~9DnBiIb7)6gz
zq<MJ>HM2g--7}%{E7fY-{)yBV@TA;96S7&Yr3=lM75;$agY0dQMM&FPqDSCX+ap3}
z!$Yay%)dfk5l^8e&6My+)X~*gk4LGy=Nr_=vJr(rtT=q7%_y$*0IUq6_{7yB&OuqX
z)Rehe)*W^U)Y%e~`?HcwD3oCO3O`R3d$pT;2(hwmNqB<*(Gk-CDVxoDfaQBf=)`0E
zUzx}F2M!J3v$4<9;fcxt$b5Uz)R(v6HY_3@qd#V=6Wdo73UXosfIILEqFRp~y+|6y
zU1e4Wi3870RYD80?E8-&ez1SOeE9tChYxq(_uvE=J8*b_=N4}+cz@r42GXF6u?No&
zmn`G#>w~=ww;3X*V5XcS3I4=8MSef6$co;NN@QM*sfOjJ(?xB^9DAB}8t9+)>D8qL
zkBS-t-vZqHT-*iJUyLYjE=di`%VCK+1_N6U3zQuU9*MIfA(@nf#Jswx-~d|SHPhK`
z?_dA52d{h(kId4c_Sp<r5-id67~TeEKEU_uN=u4^QI-c*Lkfn!5*wmXDoA#<Po&t}
zlIdJ97B}Q1PDHz@JI>@>awaIInc7##BtW$~Fx<uX3XmsEPi^kO{8SkXe2u~bur`N#
zT|h1frsHOhxhZ~YW<)4GVV0-I;=oP|f5{4}(P`7IuWlg6!S2aqD8}SgO?td3cJOj$
zG&St<M^_L%Rp`$U8OT1f6`ghlb%~L#4!Tnxku{UUwyH9nWR*ZXhNx9<+C+a#xtZPc
z9v(;Z+>^x5m!dRz3q3mf=yuyp#`*a|Ij^VS^zIB_=VRX%X58)1u=^+w@ubBk?@_qX
zxt89eW*Wt$k|ep8=Hlc;4mc$AZmqzf@Ct^eYHeyz9=mZ^?pfm(w#?E)1!ZGG%~DFL
z=^CM3tL7%Myo{UYPJf)Siz$msy*U=FeHI68brIrtM-4{o8xj+D>yf~_)i4j+#^j-z
zZH+=;%CXxFlBdpmwfoM+#g#rGS*6E_AH0N)do|mxM<`k`TAp9^3QiTHFw0GcHqYX=
z%d+%ztl}Ng<{7(ddycj?_sWt!kRb}H^eHfMT2D3zv9Z2ICIXOIc)5eYI=_Oml-!kg
zZBA3sEY6Bw@Abt&OMtI(O2g@W0)}yQ_zp$1-+uh^;XWqLo%WCQ(j*eyvpJ?|O=v=O
z3y3})IYQHmTxgG#5sgen{6a)~>J#bG7A|*q=dLb1bC4v6Azh1|`Cv$)lG>2-VTEiM
zWRmHe!SR(DN63p=%8@`z&-?*y^B1#&L?6dn@Q!ORR4P4x5L1%llc7_w_+*eCU?h^f
z^d15V9d(xCX#bXu{c+}#8Soh0>Vs2Td@#=!SJ~s3E3;A#hN6EgU-0JL`|-!0V@AYG
zcrFJz^xz5UN+TlKRr=8-@@`IFI~#%#rP68LHVUtrRsiLCLG)b1nXulrVPPReGiw_F
z69Ib#w3WUg(zQk=y#!OKr=05bL)&mYI?fSpQ63}k?-u%Wc!fI&#E_xmYw`kipae{h
zuKDrH6d2=Xw-#78>HJJ#5uWKKU+YutU8c=Q+P~76=WL?f#<Kgds@;2~WfMD2er5&4
zrOAd#m1<03y3{M}++g6Vn?6c6suoaRVoJ=<@BVM3UHSg*&HMKs-@dtj_wfVNnEm0&
zi=~kwS(HA#`(g1xxO7&yHBiu<Lfp%eShQ$JL{55)Nq8~hW_SV&0Wm~IKAz2WlXQ-t
z0L(eX`yEA`>TyL1puWQ9x>Vjm6Ui;8g-TI}HLle#n~e~Z;b32!E0fz>*x&xsP|F+-
zhkmHXl|I&o#>5RH*0-qN*M#PgTSlr*Bngl&mQ7UmncIT7VTAagbdeD)3;S1U(YVur
zic|C@W4HHUP=E6qH$(DBTW{v9(`T>94Z0hXZ^XIxn6Bkv)eRQv8A_=nIoU$02c2rX
z1j`fS++LN@p<3&3)$^r4)qr?FVWj5>iP;n(F&pWnD|U1ab~F)^#H6w{z6^q-Ns{Jm
zq{#VTST?s%o}dV-^DlO(8$sYCb_m4~2)u)mm47T`t+>EhnL3XA7|mTv==eeC<U#24
zLFnv3==?z_G!Ifmc8~euLFfWJL7e8HHh0xdy>X6o5}MS<=fLE(e4Y+04hn2ts&3Yg
z>SokxlK5b;z?86lJ2fhQz;7`;(yl-S&TC1z_De*7#V5Dl-q^vKBdQF83)eQ`svA!`
z0*OM`n&L;zF)7@m;=5bj^yLW}>aeRxrop)_Au`JXjF#J7SG-q->CvS)^Q<;s)}U%2
zRiIn<3RYcovogqm!0azoUGA`huY>LluRG*qqiUvv*KeIe-8n}EQu@Z42kAv>(#Pk6
zk0LUQ58(m5$J7I=Dl>FeD^`Fy!Jb_+2KAfa$@5C#4KJO7<Yu1$i#RKM0;~bj47hn<
zH@Vm%Pf+lNG<E#U%C6TM2~;#8TQa4)_<`ghj1=c(e)HiUPfrGCgW>73XT!6ngR`?|
zcfTK=&Fy3|&&sA&MK~BBO`W(YP-+o8uyKq&cT}bWC`XOz-B+r`w7j~h+!;mD3X!v4
zCmZSj>y=nRM)XLJhivd$5#45^$wHGArJ>27T~OQV6AGk<+G&(xXyuAi<6Tz|-Fi4g
zP9175<zj70ft=l_(W)ulVBgc4ON|eee*8~pL^{H01)+IfIsj!{@%b*j1Z@F$3l^Xt
zhA=Xghp38?u^yS2!0c{{%<uKrI)g!1RKWC|t|+@ftzGxsAo7`TtF^MzXLdQ;uuM4O
z9(h!$v0)EXNTfzz!%Kx8YGtKtYG#%d@)-}~43l4IXA;xQ<9~5Ex!U#`*XjcYMg%))
z|Fz6{4M?_9KnaRe2POB*69D`s!k+}v<d9DQ4z6JfTF#J@saVrTDYNC})ue+WF<?v(
z$EH|+>SmudZCXTvT>VO3L^+)cMH<~D^B7Ki7E9QfHkDGHvK+NDDit6NA@kX#A}P13
zQxM20lNLZHnVs%ai{@Ob<|=;A(-2pJ6VW1D+-?q;2~P*bqQ6ICC24Aki0Iyjk9R-6
zz5D6jF)uk@OUG;icF&N~rR}PR(@{*hoJWI<()EYw)hPcDnK&v-q&6Viny{Yz^CP0u
z-@U(+;H(6vE;jpbeN@Pp7Dly&Cv*`q3BulJ*F7<z4P`_X>vW`#7DN+m-irg**2R^c
zFVzC9AKz|opf*C<fM$bw!G{ldt+YiduLPe`eOPCQ#C}!I>5I$R`ZCwf_JcS+qqD0%
z#<$btW*=59ERYUgNbD>uZ%LelpJDQAgVVgIP6x7BJ9cp~w_dIjM20#E5*x7Pb8K8l
z$Up#2=k6A$xmb>`ZnJIXL`l{(+2%GAwcq1P(`bA`p_A>kTGFDV@VLTHLCnN(a0~C6
z?co&)jNs(PfZ%Pd<DD)_D7%-I&`a>SkXF35qFe1DXo6~F1;3$)zxp`n?xWkeffYOq
z>ayE<S_01S2GwvI)e@`;46<wJ!~v!hr)T;eP6yOwFw+>>x4oP;F?kFgjjT!ha3n_A
zGhC0Dfe>aWS~EdWc60^3u499>vMxS)Wy-kHiup_^`U%V;bnnNftJx{x<J@?tfn-cF
z0HrP`!E$#mFj;!4@lY8p7{Uxp7M(|kuV~c(wTPSPD64AmEvQ~Jy+LRgQ|mMH#5E-J
zCQH!K!ER*IGOX#<_1rRp==Y`~2(+;qEl8YonBJ{fb1T!9ymZ5VtL2o?*+s)J?A}2g
z;W0$zk=+93TawWWN2MPJ#NK3S{(YFOJ<nFR9xwrIO2CY)q$j~wPe8)6r+VT`9G)t}
zdS>9zLd2yeMygDyAu!2Et5#mam(yxBFrfo9Vc-}hz7Dy;P?urWz?T`7^Wk_$e8$lZ
znWV1rer7DpSuXN!&Y;*b184uTRxF1wByEgq*i37&Uqf%lPF@BtY{-yNlC6TCU$#s}
zzm&hhxdCOSFh&92#2}OK^7c!8UmP0SanmYZLbO2CvtTO5TT{8%Ps73XxqxjqvDv`Z
zinA+e85Y~C1)O_V39(xcJvVB!QTPk12>mIGgSETFne#bZCw@kuQ2!MI0q!t)pg6FK
zV}@rv6x#?EUD2E(#}uZoEJX&IE(b%?yE(Jw4xHz%hz&0olz$u0Kgu0D;!2<Iycm`X
zSxlidq1acO;jLUt-9c-mp?kWeq$%Z#Jh1?02HA-nePO1MK!}!pZZe_PtBQo<N$5jy
z)R}TO%c3yK@&Ig!plS|Zf-z!Cf`Oz0C{TlDZgR!&{=OU~w5VD&C*-IjN7qf#OHyp6
zguyeOS#5gdMZS-RZSp9<PeEb?JR6~QUc*?p3&sCfGM_RbWSNYYrxqX9>jFus6|+#8
zyR}uf7$a*vXtMG#R>SflMs3=@AFTOWqc0Y^OR+RJ91!}NKL<jB`vdssLo%HV7&a`b
zrUa=nDJSX4q`lG!7n9nAR_lkDm%qYhw`abqiiwIT=5kh@^qHjYqSNq=nGcb74RWAr
z@R6mATcIFoF3t-rPQ{ZB#FHlfSGS~hcG0W34JOcE!3-*IK2wVn4Vq)4u%*&ob5^8z
zVV*UJk<?>6qcW$15d?*3bkYbg=Wqxt2vkAa8W7u$c4&4Ur~%T0T^Ru?y<0=yQ(x+{
zyou@x<T#5SeyJW(lF@4_zDLgUIOpL>cKF+y&-YN>QKr<<nu)Yq`-?B>?qDBe6lLI!
z263hLcZLt1DWx;=7Q>po?G7OHF6xmm2qhcNC3kOLZ719GN#-{cXx8ZDON5iJ9f4YW
zUMJk_g<cz_h+!iI+ih{S-@qv66YKF36-e(ExuYi({G(?}nVLcE{ZeyeYys8?=?UU-
zNn~W|0te}Fq84VWDb(R6EpRXRP64mO)pQC_sZT5jE2&Quf@OC#+>7-pSG~vSmM%4N
z_CSHzzNz#~&rw{bK6Ar~&UzRDN|R;ts)@=|Z1Nu_!dwJQ1WcEDk!W8j!`sIfiwx@5
zhKGzq1MPe=9<Ng>|J<VIXBx7C<3n|dH$eK7qC(5N4?n!WJN)$N?(MtJFbs=cpISO1
z3;shkNl3PfYh)HS4caUT<6d00e`-{|PYqF^I%Ns&hu!TQlBFL5bd}7cVzY)D;+uE(
z7y>_nLRW1B#vGP?GLD(}7kMA!%4Rxjyh^;W7heYvy`d_mFNY7h7;`h#177HQuQ+dE
z`Xxtlg7c@*v_ab=B6-fg1x}BGsHlFcRfA>b5;>}DU>*Uhw?)*e@jZo;A**&`YL2)d
zYVMyrio__82!UEQoxV>SAkAW|5{q}wx0xgIYYk2xSd7Dq7L_eF<ESsTI?QKC7KQ94
zWLc0{qBM@^;Fb0_Qc~z7#*#leU=?<o=>ne8Jux=aXtQ9?be4<r$cMlIWxLBJMdZJn
zNK;OHIpG!12I|k(C`|O_!}mnL9}(mA*=7yJDLe=livxWL7Pj3}k1CnP)j>%DPv|sG
z$J`pG?jl*H|0`^Ws%ZfM%JpDmHF>WqfG?b%SA<;V5wREBi2zT&gzBGYh;0V#DT|sr
zxs4Evg5HLK%jvC~x6+*rm35}$A}L36Z_(aVM$$Ht5y27yS_cn>5N%p61!T|YQozrE
z;sUwCLxR8+exe~OqMJ^F%jtMYQ-C>jBz<+Wo4}7Ky&>`(<^jY~pPDlPTFhc_DvfjG
zRVf?<bh0dPu+Ux<yo)V+1=6Zx_T|xy)IW>e>&Ny-7U=j1qd?IEI<U(y*&pe_+!1bi
zKhooBI>j^#;am%nnATFQm0$^-vuVAr0CVASvr)TV=lRWgwdiL(1=Ep>+HE@keY3_R
zaDV&$%|GuB+q-}Ja`)l>-JAD^9gA%I`0k$8IhpLsP9?NKV8Iw!$|H;)(V{6(&BWZ!
z6ForsVoTUq)u}H|WC#v}3TBkqlhJ@Ei$MA%(gRcn4|K%a*DI98!_m2!nNG9+$gN#9
z15~_H7Oxr_EC4uw2{IGfmnsU=R7ca~0Z0{D*hscF*o3|6N~=a;NN%H~$!>~PWP_cL
zbp4?r_e53~7;+PO<IFz`x~M`V?XH^AN*IC|3mrZaH;kNjpu|P4@tnDI)(}nfJsf$h
zclMI#9uLrj=}jeeyAHzfxd;~Xz?KNfEJI3-C3_y^u~QyJTv=l^Cdghrz5DLV4>+M1
z+rOhPfN9uaAZvbIbsn|9+>G&B4;G_odWfaPGN8U%I9F!{d0Mf1ogH+my`Pp9Mv2(W
z6Oob<dAZ#`tYyv}^gvleWDZ#%9W5eXUdtLntP83sof10x?j-M57$zhX7S}>i_CZQc
zmNlMi9BoeeFEF{r$tvp<tShrfGo2fBzwJsWUB}QnlRB5%R4s`|rCN}wy=e2F=S<wn
z5W+)v{Bk{X4F*wE56XJg4O~i`4a|*fb1YyQ3M}ES7ZY!n8YD5AD}h59_+t`7x>OJ1
z9V8fV-%1?1d7OUP;SudmdVl$I55ADS-@=)x?DVf_KB3Xp4+2ZYZ&6WLj+9v;Dcg_b
z#Eu9Q!L{(gprAYxf}w{xB-}-r*BZZVuV<xaO+n}=?Nl&dT+T_$jVB}+$VZkvw&aIf
zKpP<$@e8X8MD0LiQ{^&R##f~BJi#bvv$9~FqQS{16lptc2%%Bdr5RbxP`xpsHi?2K
z?9KRHG-`Il9@1fp2{&sNq5`Ey1ChM?=+*qn$)-xOhzwfvwVRmzLhqqcom$J?EgsNP
z3O1p7TTCdHaerI*l=`(ED}@V<8&(|!NNnUJ{ENIwF%Ox@7C~)nk*Lw---q%vBHOh-
z&OI~{a6*Y8i>~0x<#uqm|McdkpUA~y{K%+lhT^$R1NI|ZExSH>mdVT0vw~w;F1Mq_
zT1*RCJ3ta-%!|b`@>3RzIJM;9B9NvJd4G^*Z2~3T=oaMg<o5Y|{mt_Wgg($Fhe9)E
z5yB6%2(k1GO+@%>44a3p!3Lm#4>+fqhfr_$VV5p7EjCkjzD1fS9qc?rmV9d|g~g?A
zCFY_R+Thjfvqe_QbrwgIhg4S-AoLC=8SO9ZRm)Lcwj=L@wd#X*(;byF%Yq4@kat`z
zc<!#o!q7F*I#OBN5@XB_F<(Ao0w($m@fFpl=TLWfMJi{AMchlEuO@~B!^W|kPZh{*
z1o-rq&Zv>dig`io$8tt;a~MosBg7Yhe4Xvv!&6i2S$J;WgG1x0-h7tMkDITiAZd5z
z4*D3w5sy>r<c_P1LymT4^{g#a&~&|`y6cr_y{zTV9P+C&P_K3TqULu#7D)uQ*;W1?
z294No`K#l5>JEA^<}>mM4`8~gZ)yN_0|__nBT(`B=EC~G5qQ6Zqr~F!Tkz?#>EV2H
zwO?y_x<ST~2Zw^hPheE^S&3`0Hhr9-KjqBpDe|6}1%b}Uh^IzcE%5NObBukrS)8BG
zHhw}jyBo30cTCS`h9w>}?298SOXF-VhzKcx2-zyA704o~3sZuAI~pTC3ry{f!b-F7
zFu4Cv-HBb(akj<Js~Ljy>!UB4i_a(BWt1I-1KL`z_TZY6sg!C)RCf_^W>y(ELxCwJ
zwZv;s-b8ApdU2ajt*-o}hNemP<0TUx;AI7>osDc+Ag3(EaH1+tMRMIq&MEFdU*^a3
z`1KlvK7G5BY8Kq)mTBF}>%J#qNTEcqMhTu8o|}XVO^mEL1Wxd)f!my_D$qfFGzp>D
zJI4=3>ad0Z7*Nl>TQuq;jFKW-mC8V=hH8gfN(I+jNT;zlz^K`!rb8saR3J4>-L<rl
z)S}~C@F+`oL2NazeY4GM?%sSq`S{~cC?YP!K+*c<ClnF7`~LdP`!9FKJmN%vG88#5
zE8}1s77o%2)Ha4s0|Hz2uqbXWyW?{+ShvMAhH85YH4D598Xt75mp`JCek~xNvZs`i
zu~A@p@1u(5#?Jk8r3Gv%jzV6Nir#|1KK+wZbog}lx4TbwAKu<6h1D~ruuA)uFF?8w
zqZL%*3n>fJyJ2Z=*f4Rm;}m2lW<*jYqhoUs{uka!Q(=2EIgx>0Lq2*ajW2r`?L{%`
z0W(sMgAwMK{g{cUvi{&~jKJE@X+|LNlti;KS_E(AM-X{3j1fr9=hEld?QC8~HLkP-
znZ^+Fk7z~1J^Z(2M6$LxZo=OX(mZIe+Y2oNHGxJstmci^zKOcQb)$yq-X7wvPJV_B
z=aiA}h&$x5knH1qFedINO(iUWgM(#BdFq^*n)Db&(4QgoR|=j--&f$cha?B#11dh}
z6;54&G;%Q_7Fvg8s7ZSb%O5&|Bq2c>!e5!(9ibeSL>sBgZt5(6MZ2C8ayW9W!^5rV
zA<=~9SBJ*0&YJ`A{}CM*J($xxKg)(k%&n=JolNG)1q-`eTveQYC88K<q8Pj)CBq=B
zP%^?8Kslb)_*Dqh9Z+Mk7biGTckw9shmlcNmROS4M&j7i#JsU3>JPweb1+hl#O7Br
zeC~cF;BhOTN8Ui~d86q_rru(>2;pf$ZBE=D2vcp`s##z$MZgls7@z^JH#p+3)!hNq
z%E}Vwn%3a$jua=}Ee4>6x0_cTn3-Wh4^%iocr<yM7Q;~kS`_sJO1lP?r9R0Sgwgzk
zJ{23O#Pt_u8<I4)buVlQd1OXli>RzcJanDmg7x+^^H<8+$EKPGN)FdqSF3Yd?kbEk
zj~9X_3P4^BE?sppyBeZNVw0Du2T|5IaLHPxxNJ_$=Cm~}rn3_|nD!nibE+%h2FVP!
z4ayXSa#P6)*^`ReOKczA78kmUP^~Gqh`{Me@IdtNj2(w<HTeg3_0VVYG>|tGNFRR7
z8>-jUm<EERMvy1R;j0o?f*V~ZRGr$4JfHXpo0N#M%&3{x0vvUvBd!1%EVU~0HOjyz
z#Xp}v^b^z1JNQ|Y6ajjDZc0rdl?MnubQ&S$BHQWYk9z0}L?^YWd;!!Lz(~O1XJW~c
z^Mzgz5t*d}F<%hvdH@@I4wLJiEG5n^GZqIftkm{05q_Oxpai7vnwyt*;mlG^Ksnhq
zgHtAK99`5QMGcU~dU?HojrPNv@7~`nHm^V#>jv8vmPfqiRLm!n?gWv`0wnLba#<LG
zPC`h@uGRLG7U6Lx0>=V;!V(;W6`&e|3n(P`RIW1XrCjOMlmoOH38s%O_-=OyM>CET
zs!3uW1*=HSIFP^(9iA!0C{~poVKvr*#S_A-6CpJ?o@>18?vt^{#ycpzsSA~oC+n7o
zgv3GaCLnWID_6I%6D%e~O1F9gOXug$Z}NdIuX$!cB|=VI2c54o3c67%d2x3baNUL5
zMvB!#T9C$fSD^g4uJ6IwUQd(lB-0ex!JnpoH>I*<yR%BrU<OlzhD_2DX**y(VVqTq
z)9UV{QDtV@Qj60-q7=6<dKA_FhDb1<%KyPaqXgwvQ2ft5zojs2%~7JtEn7r5FhP$v
z(`#h?fo5-ouURqCweeV}%+{&xBZpPNY>#^OiE5KtRR&i8|NQ)K_MZruQxu$onqx0k
zV_`Me$W}xG6W3Uf3gk28rdDZGma`drW^AqsHtSfIWJ*KPR&(kv32U4+38)vE@(jj9
z5A@+oK9<WD2RE4j=O&Y3*T6GO4<fVT&U0nbx1!lUkTYI|+ZJEef|<sMT0*l)JfKF*
z9rPl4FVQkFL4tbB;?4MQc{AeKM?RTf`||-hh#$Y)D|5;ONmRaj^Y$OoN0iV26lpc4
zjHIY{mTg2D&jr)~gbA*ebvNv|(w;Ii4USOy)sz>4k}T5GXSGv)L)g{pH@4w=sSYw%
zJJR^T99Ay*ot*T)U^9UFGLh1QXxynqcBEEPRq!We!3SzK%Z4E8)Ib#8fEXc;1!j1G
zImMzsD#5xygf1`>|B}d9%mg+FOQ@9%$Ol|{S#9?<dzAgJ0MTrvb0cNHDK|_Ts+)|M
zQNDHsuA;9aIrkql!_e#OQBzp8t`VAzInOQs7ibx7hSSr0_T+y+6yO6d;jM)3b!Kl5
z+%E5a();hn?|}Dc*Day(_jD@~x(dynoeBx4Z{(~3r_T>dEG-lnmB8|R-U#YUde*UU
z4JEI+z|04psaQ*r>V#L89^|Kl);P028t5s60R^N8nN*ZnI$PLW8RD^WEk&p)YM8!F
zWlR%eqRdUMK9M0RnR}Szy54i5h<LxJzxH|c%*9PN4~;g#^yWY)%eH$pnOtCZb~TCu
zB(~~Qo(xbIpZZotDKAVh=@?&vGY?4s6qsmdkvY!7nNUNBD?O9bVd2x-0j>%&QiBbA
z({u)RDq|phLq5vWz~Ksqn%=FoPL=>N4vNFhX%wOb)yvN>w!EDkpe~DtT6wvcf44$4
zfQ|8Bbq2*C3Kj#{jC_CKt!)&QwoXkv4^);2BjB|17^3+W4u>f8o$2Skv~`=^7(8n!
z%=d>TM&oT3xj{7N2I7utHfl-ogj!S@Xj<Mi{t;z7je4b2-c{)M6x$9p;LK1xgHr`6
zAkbL-bASEKGdLPAH-;c?Lw9B+t~45<j29+=nX<lAk3v5Q-oSm9`cxMbkN~jV-U)L*
zrC<v+Zc(2E)SBw8Q4yoEm~#h$c*;gGR=ifa(%^LbDd`2XV$3#uSM63!>S-sor6Cz(
zo&R6j-oCkwBS{n2M?v@(w?W<78w5a6($4H`fOsKc5d;K)r0jnXv_yLtBTG7o^muOP
z?z8`%=gG`^>2A<7vvU(;5nWl`U0s!xmG22>QMPkr?ycU{L&M7f!B?=Vy_$Z<9Vjvd
zf8L5u;KG-z0j~9O(*JO#P<8H_&a}XJR*d{1g)^FPmQpHgasuuH#$#3_Br>P#4z}8&
z9@bikxYYOzC#ic`pcL|4?q0x4qu~=7Q9A&7FdPG2&8GKJm62R1ufUI-%+KjCd&Sa8
zH~06S?|yhdnJeV)!7=y?VikV4Lrspqu;Kr^dW!96LpfV><u|wYW2CzK)9Ul>m$x_X
zZ$IN1+^!Bq!6<qLB#$a>)-9?b$`QDsU`AnYn+KgIE*TnY0#XVN3c}kC=9MoP;@f+v
z#>kVD!Mobiil)FRb+(zx?^vfMoR60&hZ!$G*GN*#59(FZsNDc+wMD6|C=|R52HW*%
z!)cdITCCzTI?o`>geHuMxL?L@<5Q%pBgR*CmI|Ook_nX1$>~#2rpoVpSf)vVgE&<)
zys6=GZX>pFK@P2vzX7z#0P)0xRI^V390^32(PwC((;~6%?XF}_jVHI^dU#421H>64
z0U%_1wD%5DJB*1c2@Y<SfPbZ5UPkK3zDJzFasJgOND(O7_RYhGhc8H<{>$xW2H^PR
zSHT(6QDQw=?T&t3!LglIt=pS>eobFFgK)f?=5qke9nALSg%+I+o7ceIbHVJVAkFw+
zq;GCYE1g|57owl^;aywpg@RC5Aa#aieg+<I9}C|G=1KGNxhmuV6}~6i$O$Q&zGdHU
zW2DSktQeG#CBZbRU=q&8B%}CGnP$0gvioH))lkTs*g%ptTu)8R7z#uwseP~2VzW>6
z@RB?tB=A0d87`3wx=6!$qz@_oLc?=rDE!=Fv+#Bv{?L5Df2}V9V@)1l?EuqJ6z-{^
z*`hm#=ET|gPJ)nNzKY^_VE5GuCz-}+E9avuPMYBM9^)=6R#PzvpxdHq2zl=^qqJag
ziY?}IobKQ^CwIRb4Qy_(!^!VvDmjO+)XG=U0vBJ$osR<q+(@AW%KT}Vaa%<abq@~h
zbPn-BEdR)ls#vf5uwZTL1arn_dde3(j*CQ_|N8ZKWk#`dB|JjT-z~OyF<f5{j-UxL
zi=I+{;gr)dk{7f3BZCL1%z%}688*Y^1P%xFrQRo`F&@CHrled0uC$0FlEjZJ2Od_q
zuJ+nZdT!`7&XFo&PWDF|kzS)t!Dv8!VRCvzcvTRsqU#q_O|m{MN{G7Jwxky!OO@N}
zRE<71wvuLT8N*om8@Hi)n&>XEQ3a~X8)``I%xQ+Ps&6D4SG;KMR|KEAoiOiVS_!!d
zIhZvG>Sgt@60Ems<&1~#-0cBUXNki!>a0g8rGYNASjNCJauLHu%1PW}MAKQ!8I18~
z$lO$4I=(7eaAj1%-Z^lW*0{=umNLZlH2QRzdxV9iUTyUbkUmJuT^H{2TVm2WdgOU?
zQt0$6uF^2X%*xE}4}Bg_<w!C#KhVC_!_xgikMlXh(F^t%xoTq)Q-gYu%O&oP#}oHe
zp(h^+wE4z;{P5%5PvbQboHyG(fBXcR%do?4n$dummIGNE2fO9?XdzJwDr3LYSfrp)
zj-aho@-&C~vc<lPo;0O^<#sih3x!glOmDJ!4WMR`Gk{YQ1-&fiU#UxO!gNE>eamnI
zb&4_Cp6~|iW+-V?tT6dGE>S2=T6<mCLO`Jb;{qHk7Iz;`9)8^XZ|w%icO<|j36KK~
z)3?NcFu^ASc(uF9wm74$4=;iGl0x7#la$Mjr4fqX6BPuY1lU65(ZKfxv_ws6&RTq(
z=E18S$*VsrVQ6xb6WD6vP9P>A5%&<Z<`EYtQw=U3%0fS(1d;A907m|@;gV%xGzGZ{
ztKFiKEfOhnvn{7Plw?Qc9H==<Fq>6n=&GV!I-DUZxbD+dR9e&JxSux&ToG_79Emd{
zY@6db?8IlM?fgUm&|Sozq!CkI{27@8Bes<1<FS(~2p$l#P~ZoD{p1YSfJks%l~0a4
zOZ{SguE}vyZ6OxbvM0-d-R1gH54~T<4AvEFQr=~F6mu;n)6;;;N?72WKi-0(Sc5)Z
z$kulkh%WB|eiwJ)K<q|-Y|?>ZZLEH5iMQ@nl*){zU2ooKP$BsyDXpvtrsd|zh?8((
z!B1&d`3+5|ZpqWVeZzP&1l_;hjFK8Dj*5NV^bGPZU~4Q(6HEeTvI(DX<A15{h21LV
zj=MOD#Fz{%bB&UpLOF;)lsB+8ATzU;9szdYR(-Z%8s&N>YFITB*wtRX%qBd(W5P<i
z5S~aGKp+rNyv-=z1=PyZ3BkhdH~;Gaj=u=f|9BsRi4fGzJ{pwREqvSPdeU5*3Z%}Q
zDa@rQaIZ(}3kv3@rKO4aso>yorq`#bI<FHAR79;O$Y$OA)vR19*l7rsk@EoRyTqqC
zvb4ZyP@au26sw-!Ss!FPd~uArS5DcYiG<X>LM9q~2y;}rC|^2`z@iJL8cFX=x@Lwd
z48UFdBpig}PvcW-m<And9wZK)fxqPptS-9QgeCfbLp2hHnX;s;{KExPf7r>Ga&n(O
zp$)Wi#WPo|&jt~^UF5Pj+<ED>vungCZP(ZU_<E#Y+>{7$km(tq)1vko<X1F6V6)>u
z*6_h96IBuhSW{OE)6VgiuM!VQ32Pga=)3qWZwH{ZSJgQ|RY2=sxH=%Z2<frVTrL@p
ziePr;$VuYMj3Y#6j7zl=e3`sK+5{pBeuD>vIII-niB@6<kn&nJwWf|G1GQ8pWl>Y;
z#Jv=aT0q^x3535LgnRhRg^rrXS>PC*@s#Has%7Q^^L^;r_<g<fY%vol+QK~8iZ5t^
zbyGNxl74i%jq1Jvy}aUDg<iuv{>W1X+f_OK<~fk^nR!1AMr6kPAdzejO}&F;+oWSC
zg|usT)l58qNkYRW{n4`$OpmuEDbqdHv)hL2Hii(X+TCP%ec>AhK6v*}p{S%IIWRPZ
zKO$cyPp@9IQ1DgwqwyV1sAlWw^m_zG0sD@qGqGl~&dt7;fv|(5sk@xvk|st}A4+$c
zePKSoK%T31Qz7Nd;lz?d>Kv(vlP2{zSYK`E0$-Np1lb9-77C~;*2pDWTd<NXwJqfG
zpIf!8imfY16d?z4QD2H?P%TsI4t<ekfkN#b#p;I6!#S_G)T41|z#V3^9-k#0EW$~-
z1I91GJ&d+g!3qf|ODk-M@!CiB^>pOpp(fjgvUwjSTQqnR#_(rvx!nh<c~pd}vsL4f
z9s)RRCVNdWu?fsBNmtG&d0=`^#m2`^W?Qd1@r3cjDf{~%!OU;=0XqF=A825q{BsQ+
zMGex-PJfvM(;88$f&#v$@SMXUUm_pr^%8ZIY>K*pQjyX72TYIC1Z}x%7?PMi7zwzP
zNs`mYaum!6b<XZ@5f1c)^9)ZelZzT4jVKNe$l2HK4PfG3_NKRUDC9cWUAOQhp7?PF
zb%Sw_T?*a?<OxmRWv<h%nvLXhl_6*+vFKZAS>4X$W8lJbdsZ;xjNR3uR6dBI@rt<S
z<Lnp0K_`<s^Ew3tOX_4Kz;du4|HXj%|AAA5;`BO&Oh+%GvlBQ`hB#;QN$T}{&&RZ2
z#?!cqut~{&p+S?z8AjL;h!9fL$j21=<r&hbo1&&{(Y+CDLgjUPS}7P>0d|Lpc%Dqa
zD@?YhFz-Ws5jAc|Hxoq2B%0|FH7{(~aiw?D&5+j5>Bat<bOzJo;6B9ci49w0fdpM(
zAmj!)#-RV&&S&45)wgHv2MVuSAmg1=)IttSAb&CWHVMgAvY9lmkc{Ep#TN7I;>p(G
zxV2e>h5Ns_$$Qd>&H34<nrp#iNan_G*^xDuLfptF&?!V`pgzjan(^881VSDEbzYI!
zqo=vYuwpU_#;JzsS#e}a53(xKn-!Z4b{6yn@u4{?NDqznNDO5w!1?!A$5@Yg)puzq
ziMNUjo0Aim<%1P08#OWA!gLm*;UH{Z<l<c94~k1YBoYW^6Hi42NrCdFEyI-(v%#qu
zEX=0i3cqsJ07^57HHLTX+!;ISdNqxO&<79X8fQB?q{or%#D6`#&VK8g?5nZ;=zwGM
zY?=el{O?jsm}eAsNv&>Jf^9WvwJ}DKJ9%;Ps%2PiLNzclk=RtT$t5!gqGHqGqGlx(
zv6u`(s7UY{At@qsG;s4uAHkVV;tTda{i__$IN<E2z~!-|o3?V`Gv9se{THYQY+_MC
zsCWM}vSa>)ok|yi%ir}Fybn!QD*3`BrC*24q>QC{E?gOYm+xIiRap#9OzdNKU0#6U
znjF}R@s$75`|}@B-$Z6<8~y5PVOChrA^_Q#`2+mG#Rrf$8J0iRQKA1Jzx6cZaOHU<
zO1(7hwn-0bm{w1-9yU#pF}dnBkaAxyJ)*$A%5lkfglqZHUCDZBcxJ_p-hTSDdw=uu
z5ASXi+WhkH`MF~s#2CaBBisk;Kh&}0N`)lFByj8f74}<2LuX#G6|Dqn<I{{o%TPU1
z6U8WyleKGLtz}a*iDgz6urr)T$8!43mxj_=>4<MBeUG^#T^(sy&SRcIC9ZW}UrWu0
zg7Fia_70#kMsAlYG-XFrL=VxC1o?7?z#1lnKe@ZVc=-7TxKZUMsLi}$h_o?-!qVL$
zgHkj#$z&qg5wA187{Q@I3MejYkO+`95|CcwTGK+$n+>Y-tXUylt~boQ!)M5|nEP;l
z$ZQ8xRR3gyqG#LJ!WS}{_+RXXuur)QW4hE}w6H5=5{K15QJWzEBUA{BqD)N4D6p=U
zuV@y&_z8?J+Fn*^wV|W~dADQ9eEVFq^otBNW1?l^ZywPJrk82IZTf4tUX2IME#3gO
zZt#@-e!EfLk}Nbi<r-!m%cH|<+#=hP4y<&k4=Sh~l3qenEB#oLz7?Q?x=U;^^1jCd
z1ENOT(bt;HDMfz35aFaSz!CH9=yL0665zXzb`Kq)RtO%nB2drzgI5h#-{fp#XK6)R
zEcAzyz3vFr4st0?9B>1H9{6d84QOrMtQpHZJ`(aGJx9|~yA9V;&<h8p7?Zb3HPIYJ
z7dXXGm@TBqfE1(&CIG1j+@FPCst9Ym8z_pI#Ab8_%M$vRrr%=|sv%2KfXl^9JEOq#
z0-%lswTDQ?<GZvKx1qYJ5PF?=O{*9V$DP7_2HLx;WSNo);Wb*Mm#Cb*JYgod;#}RN
z+!ZaS=mt=)BrYvLKsK=1Iop%ich}sOE;^iBSU$l!FaifpaCTh#-yJSM90XACzcw;d
zo1R81>pG*sb}p<vs>2TJ_!uFBIDVc4Hk*$VpL3Eenq)ab_*42)KBl><Wb>HXl*7pi
zVKZaWRVT6hxk;m;QYz&=ZQ^MIs7Kpj&NwZYD5n==ud>dGbRM`ed7(fPRKv<7W0D?N
zDkPG&|3QX{<4m=X3<tXv;f|mhgTLr(8#Cd`$lR`Oqlf#CCl6niKmKT^g9VJHKr%(a
zXc9skn$QM0yVxveX}WTgdh%2P2Ehj`UhQ&l0nob{y#wNyq6}OkP=+CNcc>1sPIn|f
z*W4Xh*yx5>_d6RzP%wz%Xo!3;sB~7N3=h)+s1XPDp1~(|eRkYo2|~Vg8=ZOi_(b}J
zrpLC1D{UL^tYLbkD9nnkoCrKOJ|?d8xC^+kY%UQci9#CW+jWgd0UY_>?3}0DDc9!I
zV<?*1lD-za|J4*`#{~n&cqBo!5j&55)|`QMF37GP8ofR!%EGugIbG)I@G#|aZTLuR
zAShjNHr6Xsf%F=Ycx-Rx&MV1t*`60LnQ&SOv^1hh#52#*y)3|^u|7&K?K<2kb_5*1
zof4WP>A4;oAv8?)$Z0#-z*$ACWG*&#AOP)Z01jb5EU)``l^KP}0K#JIRt1G`2y?S9
z(ApDF=axaiGgB$QSL!}ej#bk=rmzrgAvpV$n`WegSlE+dDd}Htni6uxk!{lh{gZ#3
zGzjM4>uU{tIFg8nbpcY?l@=@6fh;aJC10YFBay7Ac>QM9<PAEz2vc-8T8g~BF_(U!
z*E%6MhAnwBxc&9snf4cEv^ox5oQ12kwV=Gcf~EZjmBIuX{OK462MA%L1<!3Ibs6|k
ztYBC7Q5~~d8omIQJ?D&cK5rJA$`dsm+yv-@O?!x>`LJ7O)on?PIqDYti7z?5Hr?O^
zs%cl6Dx&DNNHOAjIgCwBu#bgq^D~IvFLuae1WLT?4F{&Ravs0t_+^}osUiBffMJ+r
z@&(^S-xv5ooAiT=?P6Lm{n$M)Q%vD%29uRS9V>@xGR(EVwODB0g&$$83G&vFnMq0G
zOr_uwY0;v|GHM@gV%&#=IxSUK2Td8j&hwW<Jv3MmFcErgsndaFg`$&Vr4<X~ce3@H
zKfrcj-$;B?N7I>Hu_!>=F7C2-GJqZ8(iugi1Gfw#^9geFOzGOVLuMQ|wN{M@HD<o~
z*-$WS`kVmi19`XsYZXv0|I{2-KmCO&U#x>pz;>que<GE;1sW`XxXVeTtbx_(m2YDB
zyxc#{96Wm)-xjsq%nKu36%$NqC4EI>6LETz%CBFBFTqiQ$0~1XgfHO{q~^ed<@!6M
z8U%_R=wF#B{THm1>SVPk8Hax!#>LJatX}EH$9?b@zX9(b0})`9LqO4F4iiPM|19A}
zN*sCi-8tNc5{KAm*Nl-}2aA}w#GnWnpmpc>C52WbgeI;rJ&2{1Q$c3^EKS6oa76`|
z4<T`@w2JXPrLU`AVw#k}ZvEyWRTb7dQdL$4VUFP*p=t~wu+a0zexQwj6bp)1WR~x2
z)i>+dFhkoq(s$bBb2--4>L`fO_9FNL$1_9UrCNke=PCRI+#{MxC0_%i?@fhcdg+%2
zsBIS%EIjM;wfgAD#j>&1gNt^mFymWRmd-M=3W!XhgZXq&7GyiRK>F7BL0rziX>;F>
zfn9Oz(RJV&ju+r(;5iT<LKhx-2SP6Z*}*GP<Fk4PB0(@*i(jLeBK;^&9XAP?I?IWr
zU)To%<CN=mOwSK(uzaZ=<w&^hnDq&YO~Ku3FGTl6mRTncrY9+nScpT&G+TqQ+4zp)
z95iY!t2{H~CMs<uAFC#FouNY%9c3c9nPE(Lbzz5@-t&OA7xB#U(TBH6D!l5xlMSHZ
z5*8Q4a1K4r1TKSG2tG)|@+8C7N+pPCOeoLnEjH#LJv=kxqR1sXZnKw9XpmA<$dv(B
zrY*30`P+Hq&9AC~hQ02~8<$$9bjU*3pDv*D@eEiII@AHzV4Vf?5<n>#=HUnmW$q3d
zftBe@e0#cb)ZhWf1B65ZnVlNiwEUf6Ch5p?pj-Vj`6zg9<d8n&>aGUjqO<c0x#<A;
z;>&$*2=DFsOt!^OKwEsgh32w+h&68FFd7|nV?hd=#^nm6&QjHb@z-{qFkO*G7J3CL
z@+)Y%X-@S%tP|j<rwgP?0icKEW7(Mj70ggO{A`+?8KOn2Vk=E-osLmIqGF+&Fujz^
zyk>BE$_bdR^gt0wcOq%bR0Yz*s31XJ@RA?z<qgq-8UGt;6`HfE$7i5k5Y&pb>nQEh
zxqOzCzEnWjskx`0o*`r57>v~0`@3Im*S9}^yuZD^`P1#gCvjt|0NvbIKqC+4DFe+U
z9tG7QUBHAep`IoxoPzT)ILW)HO6d8U-`D_F-xy&g%hhzBb8*#0H&@y+I5$&;XWDL@
z_*5PjqEfLmF<*5DTOZRyHPwh(odD_8jt<hmHNUflrS9t}iXi%ut}^0z*aL)2+=Kb%
zIUw@{b_wGN2Qr9r&+x*=YvB%&HZ!jDOx}u^@PUFW^~A^&fg=SE!FfpOFfMeD(*sLe
z0*dkit1F5`-!1&cUDl}HF_Dv$I;m9ew4rG#sFU7q#|zCwT;xG75PA;9^$M6*K2RT2
z!1Orsh7j`=dxgK7ZJi^$1FYKukL?8Vm|UNC9)v!5h#-4SMI!y4yh>vQ(X&W-F^eZR
zUvA|QCD#i!P*A0dROXE!nTZqKf+tzO$^1y&ZcCA^zq#D2?|9?b6sQ8227&isrSCuA
z-uw)n`T&=HwcGyX6Y5(1$fSB@CvoIOK5&Sdt<aML%ldJ#LM5HQ_OyS|3qQjt!Ly6y
z26tL;CeD+(I=?AZ7pE^!nBQ4Ql@&-IwX@tn#c|u#)&!cJ*><m#f!ZURZ?AU)8hx{-
zjyp8+i^70wVh57A^r8JadUpK$5Ovxu$}h+Cl}deLPljlyI&V(saI5Uj{$-IyhVf?^
zs2lhUtRqx)@HlaUJC$!UOUhXkW58a;9le84ienX-3Vn8YYGJs=wJ^tbwbDzl7~2rL
zhz>5O^M?NlX$73R>Kem3pHZ=BG(2<`LAxIlmtAg@gg4IFBg@a<@!e2}J5b+U@F|0p
zwu&baL`Vhh1_9@pC0t+{V*0&~&y4crYq$o?XWL|?^e`oVd1I607$(O`54mxDc0YpL
zk!csUODcduj-?_vHuuBlFZbuSAAY+3<L-FNqK3%1|0V5o%Kz~AJOw>HR+Z`5bd5@u
z$i##c5U7#c&>|1v5@u=YC}3Y!ZUfxg)~e~!M1UM(9$HG@8m8`DHb-chEyKif=X7UY
zFw9lZa%?Y1iU+c|>xl=m=uopv56HkFeAIcX_OOh4vZ!=fEGW^P{DSdINjmtuowC4t
zfSYxvEW5DhKI)Y9_+5`VWd(VmSj%WPuwa*P4bTLTAreun$zh7zvos7fFz9HsCW2`j
z2@(wiEQvM4J-WpV*NVpg&s2<gwub9Y+RR0pmO`h(uRMISY~@#iLoEn$lw5-BGEpb{
zRuB{%&#ra%3tQ*aax;J9C19Ws5N4Pq&9@qNS`3$bqZg5$oo`^wtB!(wz4XP2`ch1S
z>`?LjEud~eDh;Z{7I5L2zF9G|)HnUZLEre<an6HoHjI3&4>R=>xIFSdT6l5@+%TBC
zC6o{qmr}O-yGz*-(H2>MUx|%UJf<QN1!_+v7;8E$g1s|7F+h5!gtQSt6L^4v6ZXT;
zEg&Pa3;`QF62-rY^e#D(tR;IjrOXysufvnTu!;G2{uuL-Iyv)EN(5D2@054xVmWpN
zc51rZoYtwBXiAaprt}Ch3R7_XAeL>o>?0UGRWK-#79nY5l#`kZm0nM<%D`xSJS-2Z
zL#R~NFs##%duYOGtJ(GhEZ6h$wQc^TyTcQ*i8OUEaXRv}_TWn1XoCN_?=jQFN6mCE
zjA|iaPq^h(B#xCvo#4yY!_HZc#R77{wAE3frGV>Y<eF&SELE7q%xD)nR2!z=*cGTm
z)itg5*h?uHwx8mT$r-GhAbTU>ThhAqj}u)f%AALvMlB^r2R*0l3o^Lgv`wJLGS&=A
z3;1rQ8YHd^^kprTg<W9NuYn;NP-9_MTGNZVoel&AWGZreBCJZzjzK><l0&wYlwG+Y
zy_a$Tk=|pTLpMyCtT}d%M?c$>TM;6dDC9=4xnBvnMUjk^0J32|Vb$b)QbD7(DHAF}
z%VmT;lod5li$Ic{vmtnDaSCSkOz9o+{G>D#6puwf>=44SSREl1$dP7tz8!)=$0-2A
z$iMZUKRbGPG<<gWVlWuIc>e76o8gNY44M3{HLP{J8AMPU13yc%RA#FnU){*(QG@-h
z&~J(foRQJr^<LPnbsntKK_<cU1nF>K@4I^U?(XAY@$tjm{m0Kc)D}3q`S6Yz5WNG8
zZ~MB~L|Jwy2r`-*uj2SupnL!L!D)%D@4y2w;!4XMoIWrIv1-2Fn3venV`LWSl^41z
zo#dci<ey-Pfyr(*+o$D;DD&LUXOSP75{^)dj=kGVHxkW>8l);V+c)s0DHtObATV~0
z?HXyJ3|UpG5oi{HTDEHLr^JRra@9@<kjCo|<GC_BNk%Ji+A$+AoUh3Nt>55BLUwA=
zipRCw0&7??Hx?4$=Hnu6DcO!!3`siZG93G0DO64%k!BsEt8m+Jy;nmq=c(?L2??g|
zfj>Be_EmCokh+VJL+P@He2ghHWR3&|&B$lrb_V(kiT%q`*x=s=gTtev<HMtugJ*}s
z{;+@hP5=136ey8xr99+9K7ur9d06t{OPiXL(}FSNZg5`EQ*JP{RVHriLpY01;S+B~
z89^s0Iv&^`S&-u=jBas@?ywtN)a)OgxH<T5>)t<+ahN;Ft^R(z%PI~@mnD<QlN$85
zBC>T?m1F{s7g9LgD9=mE(NJWZ%x4ms?PuOsX5sUyE8GKVmvD=K7*yuF+?Jjod(FxE
zbxx!=;+5c{+}W9`=3ZJrVT{o+9MkJmbBIhKkrImv7Tzs4utCDmel;`=OMhlrNQHw%
z09SFS(tgg+Da;!qelr>6s+^5BXQ1LJJ2`lE%oyH>pC8^sHIH&K@8BIHLf`81^ZR>;
zx3%+1w^!4uIBliR;m1cxzHD5C-FDn(q<pynOmDNm&>g6Ga&n|C;Lh*PESdLvk{9>`
zU(mSL@+8i_kz^I&%*LczZAcRLITDwX>2|)p1i0W?r`WX0SBXS8PgyBRqKiI<8Wm<B
zg(?*Zccpd8mkHOPKj8;Q7+qWmPJUbVXjJEH3Qsl6=I`TYC})3o_zBk8H8usp4X!_!
zl*vTWnl4})cq#mgL!w^G7Ff>|MjJb~-W^wgxX1oP#1PSa35TGq2!o2eL0{1o{m_hk
zI2>U^q)$@$b~o2zv{ucX$EHSev0NebcxJ4@)@qN0smQhgsV5OCgo%>9D%<sy46WUA
z$AE~!t#(0{&fMJ=@B+b6wmoez89c~fvddsSiQlj?A02q$yeJjL`ST18jRE(8=P)^f
z7gfC=4WJ$$lx+Lva5m{xSDNbv0ZO3<t~+jl^-vwAn5UF{Wk`0Uih(PDx`hNrhw69}
z1x-Xy{Gg3Cqu{RTtJh`b{^y+ruLRS}LVAArB4wD6s|eO;a=oRF0FEHEOvo&O-zvXg
z_+;Mv5LcfGpYmm%t{kJ_buo(u^@?d;jZcA%r|{Q2!v;#TUpMQHf@51RTU)mYwU4yq
z$9QlZy(ALLw8$Cal#CEADAJ_-y^f5!4MZDfY{lY~)<V5FJT2t5mc^*5x}#a_qPQ{j
zJ|g69fwUY~FsSk%7J5WMKxo@cMOHLu_Sg%q3So(}pBM0=qU8)lm*w8Ir<2cR;3uXU
zKB^5j8*(M?qi32il$GXnsz_yb$x9E#RpcJ(K_{f0_|G?LvYP84c9=$B{3%kOAe3hd
z5gC7vIef_A=A5P^f)(8EQydWA0A?R8n75cui^&;4<ZO!z3Fe=_#d(|YrBGbe05?`q
z_}NX71JpDaI5}{UnI?vTY*5gRf9rS0#!y&DbkPum0mibUWI}bNC1&Coe5EN5{Grcn
zYAR5En5iUN(d&A2f~h+=W9Y%4`#|n~1g2gr;i0jfE)}E73O_C2G@xXv=j+L6XGsXr
zbAb?Z-V?1wmP0#?Jn-4eQO1?Nu{!^mpf}6+4UmSN)kjF@4L^u_s+&;V5`@u0Ip7mI
z14$H(XV8iwSB3~4C|jVdflq)JNQSk1Hkx7`^e5hE(MX|VA+b`$`l6#=uDwhy16lau
zR+sTAP^<|Xla~_b)EoN7{c`T*L9)+zu=XAd)SGQwYN>n+1A4Xrg-aJJX!%g+d{3t4
zA`~orUl)5mup$Bd=f<8t%4$ExX3w{v<L>HK5%6NWc7bsh^zgO6NpVXHmi+LbIyO$K
z<izdlrx4-5SS}TsbZ06C=B(DJJHtvF@q<J(|NcESKT`B%CR7pE;DNXB;=*Hl2m%p%
zG+obEXFEj5n#Xg+$z`V}us>jobB(=h-@u_nfg^jxc?11PXi-jrY1Ul$1Ua*w+wG`w
z?{k-|^cl=DvK57j;vk0O&Pa8DHE|+G&ci3>%XdW$>&7t<E3y`5VW*Y-(#cGtRCl?A
z+TLC_CklLXzM)OCnrJ-Y<=BS55ToaMJkC*I(hR-?*m(J@D7DUQAnqW(^GkFp;!62y
zC`e6<tTx0Ac1_7_HmHhs3zbpatsCqarQ)@+2FJclF4ybL2I+9^SfshMp#&m|9gzKq
z8|malI|mdIaFK!ZomjROgp2DRN3tY+``?Fqyu~>xQq0j9dJhuTH5_G4&SY*6xa~J+
zrReJ;y=@`k_ej2j1y&A`AJX;{@}xO+20cKjHpiO&F@#;4oB0wh#!CugM<#zq!lgD?
z@2LkfJKvp5&zILT<jC0z(aed7q?|Ngc!4DI27YN;gf<shA8wp-dXAa{6;(mOYPt-!
z8SI|dUN=R29Mg1`@o`AY017}#Q{+?)Yn9yAt`W$REz?t7X3I3On?Zah%USbat3Wnm
z46tzxVdN%Amzo>@xRmiFw6i3Z6!EaG@O8#N(q*Nq0wYzP;e7PnbluB8f#v4ajZ&M1
z=EpXu_zNVvF{J~3)Yh8P{b&!nWjeIVeGqmsM2SM&uyk{>KJeq{RZJEhe;2iTTMMcw
zt4KVup*j5tvsb~L10`h0cJACRl`RRCfSx|>F^XUc=KARqR-Yt_u14RTFGmwc*Q(9W
z!6LL8qXAEbW#BlmyCSiyrYBtV8ZdnU%Yc@-9H3xp=5l~=pU4nqXLs@a`DS^x$x@@F
zrfAh->wIul*41BemEj&u?AlQI8)@^I-3q=@{3exK4X%&j_Um&7k(Mpw1HlHu)LojB
z5a5%w4$DPKt4gal_0KBxcXlaVwEx!7_^IGXG?H*e@yyfH$>}uFUGynyzZ6~UAhuxc
z&QpLSo2=V(1w^sWlz}i97zkRM?=Hrqb-j)@4U=n`oKK;ZB^%*0Mlp+e+6yLKxI}VC
zm%@<^r=yk3Dj$Xvy9fA>$DREpMq2w0)FTw?>`_7(n?P&@jgp;YwyvD-Cb-sk^G?Br
zZl}&EIU>(cQUpYJf)d_IYMMwQC>zc9O*zu&Wdhnxy~OePVz-4>EOImCsht6Hf|gOX
zmrnueBY*Y&D_cxsg9e@c&k1Jl5m({d%6hsOt&B5-l7F<oSJJV|px^ufko96^fs1~J
zHIbW?jE78Ejn15v?!Gt`|LVPYKc1W(gHr@4wLGKN)8C0mbjbrqzO93I?CN?u{YQOd
z8emd^{#l%zMUz%n+wpw-3a0JxtHN4gQ(Pvcf)lQ|>#RCBDZ!dU?LBj{Z_aoHQfKaE
zy5!LSwYR8kcmw-kGGyko+KsG&_)5+<U}1Nv%m>kVaM<q`d=-!$bFzL@Fr2=;J)qCu
zoJ_6D11}y8Oy8eR?Kf|H%zIDt+0BrhynTXcDuVo*TzOvFoN|*8K@Sc;$12yMbn*;a
zVT7ChE-&#5&$oli2n4lHFyDcLL0S+Th?`!kCHOG&yC>-rooW(86E+I#R;{)W##T^Y
zbkYe0al`RSmZ)9t;lr1^pFW^q-Q5RNI|ROY)@j77H<-T)7FdMm$zv%;g}=~Ka7-ip
zSW{Kb=LbYj$fq{q)!Iyn9rgsNw-&$?iL{Q;ltaSLTspZB@hLN7vg2!9Ff1W@HXFX(
zyk7I4q4=?MrN#H5pM1B1rEa2=6{GV@^$0{dU9&303MU}kGBXYog9igzUFmkU7$Z?R
z9jV>?47!tmC78Y=8P?{otU;Et0i@Q3x$R$(S&jaGb%r_AIYw+PtVC6QIctqGLm44D
zjRNk-A{})p{F(PtjZ~tc@QqS5mz`3smUgA2XVi`>%@h@b++-A1AHM8n5AWaiQkx}O
zfzj{WYW6bfMTxvHJ1F32!}lq3MS?jnK@RcKtjcuVB+fi{Yj{G*?PNOufj%E=Rnt{o
zRS${qZ;7i65AQu&D>89fbhF1KLuRR-2v8cs%ylE3ZlVdM?xBq=%ru?|-1#n-?=XfW
z-??4Db`1=r*ASJVrK=aS3Dw(7{J|oG-8;)uW>+4}_L`glvJs2#FlQGU;x=AYL5}29
zRR9DN`sD7*%@6Nykxa9H@bq_G?Snn-!#(XtRbQm*^kuPtD~}goSZ%R$9i#Y-1>?Bf
zRD2^Y4UbtVU1hakie(tP$2?X|1(tYDp3WuqFv6%*5{^NN<)Ni?R2yPVpydLfDuc7>
zRMl|Od>Ww_!3O*A?uWlDKEAt^M#vpVIy=~rRQSSm97z?_vExME%HaV9hkM$m6Dh?7
zJ+`b_QxVt;lt5Y}1a3%~t|jn{!chP{UD|!ZA!4{IYqKuxA7O1w#!Y!*6>Vz|ew4BK
zjoW^ct+B(e69WRIc@-;Zx*b&^5Myd~n+jBHFPj=$4#<C<TD3C^2+SH?Z!k@_snxg?
zWq4ol>I$S+Q$kObnxQOJxR!gYBS<S;62{0a0Od3s!}){RKq1)4tMqTnVZg4wPu*kB
z*@pr3kRp5Td!N};BgO-6@IXh#gOGzdsdSV@W7@3S$@w9U1fZvd#}wD<!&ic%01nnZ
zMeYTBWHO2}i6c&;SPSsq+@rkTOicyM2vM269x8@(nt(#cW5;tkrOPxP3yFXQ?YkE1
zhqskbEnSu{Da%85Qi${3lBNS;R(+ceI|GYr^=T*pQK_`n3X0Eg#ZZ}`XGr8atUMq}
zu*ONGlS}4oKJ7Y7Gfds7Mxd`YoJU&@0X0nB14EHnojgYmo{FTcN|H~*rj&*0Dox1D
zyyXy5Bgz$5f;YJL^)r|x8*OM(az)f7K$O@7RU+z>m~usirD>QsqtPwvXP|Bfq$g>n
zNm)MhuEC^sHsDnFq}(5GphwRhw{4I<&_#UU?<o-Z=!HZaT|u*V^g<_RDCQU285HyW
zb<Vr<WUb-(3*DyUS^nZmuZ=Tr0B5$Lc_gM9Fm@oTgd!`c&F(k%A3uG%eJ3ISt}(Q)
zQ-n;^Q(Z#RFxFUK;X@a~6+qn}IyMGJ1%~Pj+9=A90GQ+`YVC^ZrrUT8)3ahz_T||{
zg{GdQuyP5h;w?5?2%(^1Z3IsoNzp|Qwn!A_{~AIg1ugCl+LY%%+W!j8fjNQf%+DOQ
zrEm(_p@4$@UaN)z2-r7&um&on>7`6lRO<e;_xs-qFLIv*<ba?K%Ki1oef=c?J%w6L
zJI$E_H#10Ino_w>Prt^z$mwKy`jpNlyv$N07|$_9x~7K!CCq?nvh*g4IBlx$Dp2km
zS_O}q4!2VhU7xkdcVo>*-6X{3SqMLkzwsy>jiK`vJ&~<)2g8w(7rTUa@N2e7c7{Am
zb<zMz>4MOb&rcA2gC6JQN`{RMQp40;i0f{EP|MYq`XthS&j_=r=DPyuVJ1RCDF}(p
zQ^UyWTAR=+c%FCT<vX=R0kRQiEiiHzNK=TBP$`T{jaaUU!@(OI&y{zg7TnL|(r~SI
z&)v|;&n1`!0HY2nA4nhP@=w7DG(on!wW&EROX*_R?4nnZzcAhcB!Y$PPgh~Gw3<)y
ziK5KT^jmi7ON8g8=0e|Q7LXL$RZ6b`((7EPpj~k{`<_nfbYcVAm6Z%5W8LGu^zx+Y
zn8T-cI!1sWlpvznK7`H=KFRdEw_-S!Q=k=5*xeyE3tYTkL$y}npYIk2={-Eaa;!go
ztu|MKrmk#HCq1Cpfmu)Cj?NWKy))tW_|8Y@e(s@L%R`=m7(%u%o%`Z=c;1)2^a$IZ
z;X+5waKM!MsEOR^V`m+zm!FdL2o~h^77lPRtQJHVAbMg}Zn$fwD@eO9a8hlqR||w^
z7JPHLlUl&yY@?N<wC-d@MD|jYX}nHJY1VSx>;@k052o~9ziG~739+?<M}bl%T`cCX
z4k_I^06i25EJijvpKoU(4kg-VyAy;P8(6YCMGJO1ZuN21vNhN=Do&S|>+y8QI&meP
z_IY(8?pg2SuwwkqiJewelO4e!c{JG>qZ%%y=pdxAimnv$?}JMQBzpzM)NM~F44uH0
zeg|`4XKLaCs7cK-6gNwO33<jm^-Y#^BNq<t$Z{^~x>65XXnlAPPtMjf%i||1UedhO
zh=%OwqG4$Qoa}r4C6sq_`P7Z-bYBT;p13;drI9*ff|Nb+OPfIUVNXy4XN6-4A~>^@
zpoR^aHilp_Q5X;DIjVASDjRKj8a&`Y8J`0mid3w{zUhD(x)cF1h3QO~L?hUA;pJ}4
zBKFKM#I(JY>ep&1T9QjS5h$X+e>ga@TOuPODhO#B^R>pWHdBLErDzNj$W$=W1gY62
zhRji3<xS}rMdmaL2t94MOwB)hftu{?txU&7H#{^#-w&TY{ZEOsCgh+h4C^TVyQ@3E
zP~ZO@4~>jJ|I~-ZNRR$sjP#%S&=@IvhZ=L*$FcI?oYQ~mLt~`R{$GsrpZd@k>7X@I
zy2JlB=k%ZY&=@H)-ZobMpD@yW4<&g>J9oHy9ugrU1yOO`Bi0k8R(x7NYxY+7DZ1JP
zNYP6ulua+hF?=I<ydO{k-0eQxLIv^V?tkCz?p^z(>aO6S@Y-4r5t9Evl7E=e@<|7O
z<Fn1>Ikj6Uk7Zku2*wJDwYvKnwRIDgpL@y)M3qw!<0#X1aV;vW)5Q-moQ`qclr5QB
zJDbogKp2;xL(*0Q+|;*IBpRwGMZB;>bi{I$8=ToJQ#;cb)0N&_FpHkf+?43j<5Y^N
z?d;le0Us#HCP|@?vpkbeB{O%x3s&Uvq9Z7`GdD+PPg@k|@1)>Ol3pcpC7@pGDm1vL
zjxIKf`9?JzRwG!9P1Ix3u<&Uv90}mEDbC$236kt9sGdzeWV^9+R+@t-{a&=Iqj))O
zEGS#c!!X$l(e8Si4fMw-YgKSs)=5s8s2)z=HS@EClP0gVoMeKgaCt;NoEk9-K(P$O
zPe9;JS@Ah-uJB({%AQ~gb(=AUe6|G((lgKaE-IOk9oS+ApKSi}WqbGbPgc#hpcL5n
z@V)2#(m>Dqn~q^8kj)`H`k3zLY^<cr@;ON2QQ4^ZASE-k%4C7fFP@~hRv#l7sz|6p
zTs4shBkZ(<$>Re#JdW04LiMY7R!r-o9;EcUP4QirRdS`A)P@78WZ8+zAWydNNU%`W
zqCxK!yJtiSkw};*_q9~JTYx;=DXw%MHEEb4+9{O=Q4WK=5_3n8+fv<QumV9dH%9Ka
zbr);}-|Y1{bcvh`X!KC(eh1B$Um+dbdEb+J+CJ^B?Vey-`oNR%c(M;q1Zp5SbnJx*
z{osFs&n-Q=kTH^@GS3?m<dD(cOzyrHO??Ar6iuwk)!SHLO<rt-@TC0sofpGX%3w9>
zji?pLK#dji19uL-J7p#FiSp*`1MWjL9qH2K7YseF^?uJjb4mG7i8Ff#l&YW!*e-^H
z+0n1Ra;R8(Bz+PcT#u#gq!HgvRXOp&b4CTBq}*}R+5s+RoA_c1q=qcPEtWzqLVoz>
z4+sr_d~SOb9|6oyMwZB&2KCI}kU1@SX)Geg5JF*9D2aE`tZo!sH~7#w$ff=5vUD_i
z=+;<6o<4<QJ;&Z)5^ULh+G>cNp|hm$59l~)DyV%LrB&x1aI%AD2zToy;XrZ^GMAzL
z>xY}q_qU(BT!;Fvc`i-Yav`!$E5n?T?}$l=<XX<E%5>$^MtGKdi#QL3dkB2Dp)s4G
ze%~eX)*<aI(hV(75VpWvNmt0q<VT;Iy^kW?V1eUY3E#_Q(?-j=;EVZpk8`&u_Ty5Y
z&%2o0f&cmb%c-PGpq>{@(rA4S|CB0<wE|Tyryc~Nb=}>j&&nj4-0i$G*)<xx28|oY
zurX7t1N8>mWLwMzj!LM0Oyi6=_-NoWu$`&5=C^Ea@8{!)2K#(<^ZwyhG>Mf00f0&i
z4u#Y8)#&^ZrDje^khkl}96==8o@vg_lF_u?6^0D4A+}Dk?Jky87CB{Yqpb|O;G#%?
zGhIw<zd{;=#odR8Fa4t<SrcH-Y_{vO{GQQ(s&%+250KC>)JYZq>Rui0&Rq1<<jJ82
zZU{T1XkRZ`tL6OT+ds*h2b`BOkI+lOpn~~KlCr|CkV?UMIx+G>uI;o#x_M^v9-Y}a
zB0DME7nexs@@lU>K7%!MJc(JJSID<GNg2>XhhM?eodgY>NB@~^M+J<4sOyBFC7%AS
z2f!eHK>xD$dsrNK1v?)MeFi{VAA*-B2S%%=s7$784e<L!n&&tTU1MpdVG08`J)ZAI
zztD=>o{-+K;!O;J#S?qn<CMH{b#%1)tXh41`E-f^;m34Dp010hz!2+=j~27PKn`nK
zWvTW88bd=>-j~1K_dS*XK7y25-MUXnid+Eyf>X%JX#L<hyG)2|7@XU+oXn%^iFDoE
zjH9pq-|8FY)J0NVA~~H^Z$7_M03&luyhHZuu6AU_mK=u(qWO+*eR+KHm-|~38CJez
zRLh3sGukc}bI>BFI}xD`JMaMliOf7Kufv#@-Y+-re`jUJ@e32itfTAcn=@(&ov-5b
zA?3xt@Daqf-v5<hIe8WW(a4PGE<EJxeRn?XVNZc8NjDzAMM~#3^uLP{$~$%**%_#b
z75<rHM4^#Qg1>^VK_jye5iP=AZl^e3L2Uata}Dt=v}7YGB>M-5-vzxJE2&p~I5_WS
zAYXHOSCMd90?f+Ez<mvVgkvukjc)2J%67i;;%cgR!}Cd62gvs}F1mq3Z43vnTByT9
z5j{AFHqZoW_cZUc4kuV3D}_%M25;Ib>Nc0u?Qq_AT9SWo`v<qNdmS?vD3YV_s2Hmu
zEecwYmnyTsx)78{h+{jA)%_CN`(w%ZEAmzayY1JR&(4zt^wGI%l|M>J0#j+(!_3rF
z%E%3mVo=z?x5`CmzD1^GXivOuxWx#=_C$m9Vr2$l#`7Uk9p4Xshm+Cx6;gLL)3$?2
zK-uQBpJ#1N2ArzA=y%p%py>%}JR&KQ)i>JpoR)IO<WO|%&fwlbN=c%Pj&c*n)gS)Q
zgNVUcGEl_-#QrXBdiu>DGRuz)X6Od#6bI7pMF-*$|I*V&<>TqI0|yrBVLRV}Gv~2)
z(BJ64{}L?5<1gv|6J7$&`mvY5X8L!02<5kA(OdyjMyJ!=#b`0@ef8<)?VoOby8Y$>
z9N6u<uROns_`-fv2*$w%SD4<AnlSwD^2wJ!e*Ao2soIbMPK)H4Hw(`Yb%IRroy(e{
zOXOuhuvmc?1j8yprY+zOq-I-huo33y@9u1Vp<Qj14y1zqI#ncW1xX~I#Y>;nvDqAZ
zq}>{jN(MnBr;Fn>>4{y41?OaYJdDTLIvOo9Bu>Jd+^8n(EM!4>>tezVH=%nK9s_6d
z?_C(Ii#=8F^qDiuMCTLc7n(4wl)KQE-oH)B)72V@ku&L~(snpgu5+!)nbt6ktMP_G
zke*7QJ$zEodPSfdOBGPYoXAhere}jJV2IM`v;rhpo)yQ?Do$Lw?ns*16vP@pJ!vO}
z+)E)wtrg@cN^YQn0ioD-R3K9KT^&6NWW=;Um-LU|BJXrm<o*+1uvw&ZwVRFQfaT!H
z(&*UYkX0o(X%gz@j7oNf7jnLmQH)V^^?KOLzY)Bx7o;7M96|UfDw<rR+1E=`AGCrw
zHW*z!IT=HMtnTmZk}zOBIfn+FqF&+=BXbZpMhUK8h{w{66bgMyiCc^~y|L<}+nwj2
z+WR7>ShpOXp{B?3Fw;kQso4eRe}Uq4rx(-7jsc4lqLI;NdT{gZ-RG~tAcGG5^6~B+
zY~}|CU+zCYyuI&jtDa!C)q{U|(^H(ezv$%P-H~$w^q4i7(|q_ka2qOlx&ie$WU{f_
znFgy)Bw7K~mB~S+TIeCkte+g(OiIKIf24LI=D~xDQ>Nc7Y#bB|s1aGJN+VVrLAlF~
zDJeYJV_%%2Yo*8-QwDwxWkHvgpnz+z)aHwdoy>a0Z!Lo~?GWJ@0|-Jh8JnuTY*9aK
z7;P<9`Yv^&WxHNh5MX3DMibbcaBraxFw~CPbpAU%T-B1N+f{s$uM?l2Kzf1bthqD-
z@7%ZXr8&3Oo{ledjMt9Xb|`ZfQhedDdO5uqe}_7D&=y%3ZUrz-z&tzM>BKKIa(!*M
z)O(GTbg3SmRm!Men=(=pP{CXoT_naBax+%Z4+St!NoH|Dj7w#rCai+$rpyRvcOL(p
z9#VFb*}_N%vZo^|@HG~(4c7?B!XSPD2KI}|B|_I4*Li|H{Yg_*r^!z+Ju(Ol+-H((
z*iVPN=Q;4W+_=(vG)bN)pEjHFI*c}MtM0biWS|BD1|K0ks&~8laE%l}{X<GBM?owq
z{mGH(Pll2EfRu!#mG~DaS+L2ADzy>Yi%>$F=1`Wg8l#eYl|33ujS~`<)4j)RoR691
zixz4Lbz&A$T?*$zmVr59LfolAjsl_1Mc@j;FTiJFAW$92BokF;729_`#!4|$o^2&y
z1Jdty%gh1OH#M-jCFhwfUk?qp`+@tK<?D=MFi!E!gC>V$qe{TWbOK`^u_9Yuv`Rw8
zenDC$+?6*@GixnoiKd5SbQ+)rwb`V~L_r;3jV*5gm@I74B_TQER$06Y79C_3Y+VIa
z0v4Q}ppk}WiHC79hXB2kI@jqMx>7P86fb7i%k{+bS9Sx#$wKw&$Ftq+<L5s^uQz)C
zzVR++v^)A0OTk0!YJ#X1`RdU31^PU=1VG#2`EUGFn;o4VM_H#G)8mxJ0r(jT&phZs
zXc=DMATh6>cRGO^MC0R8tZG{u%p_7lG_Hkz4NPA5lju+oZM4}AiO`mwFf*<Uk?{^o
zpLK$20G8M91STk~Oz&T<K7i`;%}|X6YOIsq|Lj4v`joIn)-6Dw2`Gg{BFJM5I?M!O
zp-al)Id62UbLg}QYCJg7rbY|lAD*0Fp=Xpoz>93-E1K*h!N<-_L>_ovrnnN^c~X_g
zo2+(6zphYr<@o62_U4`hxIb`i%{I1)eGx3_S9;EF_x97L-Oc;En=iZj+n+x%Svwpz
z4iBFn9-SMG)Z9ieJEkHHA)5=H!lZBk+PnGq@cHd6)k$6=t?GOJD%q}}25Q{#JF-sS
z{DGd%n&@^9=$&1`4J~@5L<UXKH$Rh6Vo<ssL#4$6>$^EL;MB%KZ)f^AC0gy)#YyaY
z9?l+Zp&zT>gu19WEIEw^4XR*CeRv9`3B?m0IGLt7X+S6m_+SMPMt#0D6Z>KRf%Rly
zuW>r;E*720@3q;wXaxI}X|e3n@*N-%K~?<8rn01KF)fa$3x2`O1;|yU*p^m%`YasQ
zv=Bn`F7vYU^3OfOBjm0|FOd~}2TW$Gb)nohjCS3Jkq0m(vfK!xMQ27cXcTb%K+8zu
zMz%(mxWVp)1XzIzvWo*?`u%h_hqHR87h3@r(Tr3p4Mh*F!5O6Ir_=3-miM#siG`+B
zOfb9{5>z(@($Wi{8)sum8R1R&dV_*Bh9?RD&pZncG9)8w2e3eqhA2RT>ZRf2WkhX*
zC{`!8+=VbPfwp<*6J#t#Jz3}m?!^Shmdu((wafK@A__8WQeeWrEfr7;tkL*NiHCBn
zr3a-+{+05{q~0;S)1`UJmqHTBgCJ5EEe^}g=*s4Y_Lb!d37B^q6n?r`Ud%7xM}sN@
z*petAySrKqdym2AOJ=tt1|q3T&LUgv{uT`Vqp%-}-9>G`;UOGzg~>8zFqtS`znt`}
zpsigaY%~Gf&jQP~MD<HhC5f^4t<Uwfp<*b)(nzr>Jah%41x)waezTx%S2da~!*m@3
z=oc<<j%AKa*Sgi@f|KvIQzXjsEKy8HemEG8SsbF_OmhA`_+zd(gEmZ41u6wK0e?FJ
zn=3I`vr3RFCb$W51*}TAf=TNM`w`)XPr;>z=@cW9R~s+n$*h&S8UrO2*}cEL`En0y
zp5>MT?rbhkkZO(76&HG-=vF8rU8O-=JZs{?J%cj2m&5ZboRWk=IfT+)DD9{KWnL*Z
z`I{bsT=mRIwWj^URj{vtlP<)k>4M>A!;bCD%yvZw?V<XkpSM2RqgT8ZN>i^Sq)4#5
zDUA?E_Vu{Zq(J?Xs?Aq5j?2aC?h$OX&Opm<OXBpm=C&>S=AlMLl}=G819gMDUKpDa
z1wyMv&nK=~jr4kuX>m7BXGUfV($eRI_Ppk?UV;k_B7W-n$ko|*=c}AOz@_1Ry=>Hs
zJT;2Vogb{S@yUn3K7+Y5m{M0$ZD@84&PwsIUE2{l5benN_<XFVhLg`75MD;TmD-yY
zP`7Yrc?!3YTgE9`J4-}qX*05HM07c_OCg&PEyKUUi?1d)@@?onH-6C)eRWFY0ZK!H
zR`NyRn4_h2rAm>n4KD*7+j9;yK~LaNy;9O>(0Tqo1`Qu9$Lr~gamg(x1>FRGf>M&8
z`1o%!Wy;<OyrZ^AdPcWXZ^1zUsd0LB{GyjSL$5g6A;)v{dE_qH0ll8`p5%=uIQV5H
zG&c_N0gDk*O!Qo>Y*$(xp$afkY67VS@k{Db;%U{Y{#VQME$yA~@5jGKE^;?o%VjJK
z8H$>C4Xp=)nGg5Mu>fgx(|!UqW{~b?{Tjb;xaG`FxmjbQHjiHH-~wN>fehu)dD{x6
z=L=Pkc4zm}Ia9jRJOvX4iOU5SbH+eA+Io8lqZ3RIQ<JILkGgsXNS(7K06dXz39*BE
zifMkj6;cV7UuvQ#B>0XoCYZW&sdL1t);M4Cb{+U+!_Lo<tf%on-ko83VAkhyE+-+G
zxr$>_xb$K3m2UWUX*S)4AAV+!u#OhBkG%w(kao5H#>e{>L!=UBb>-y@UAj`B0f)%b
z{F^`EIG23Ot~%dkR>4isNmP3TqdCU5=$M_fVWNwTpwc}8gQ=bZaS#3DrVoYJX58)K
znt^(jocP3rZr>ot+ws=oJcH?DI&g5K`Eos_S_LHmc}A;%(gF!I-;hL2CrTycnov&`
z)XeMUNJ*)#ugwhp2s)K>sD4mX?)J+Uova8O*EIRkrl_#s7L^MTmWl1_Ec5Hh&bc@{
zTjtGjWey%S+whPR#)4Qk+l9J%mT6O5=js<3YKc=SgFES=qN*o~s_x^rXk?>J&xp@6
zZa95lIWp&zE12#rqD$6D$W!`|nc5!qH{|>*ne#pEdK?d35D~1v8phMv?fu(7-hKFq
zphAY;(@BU_5E`E?qbwE;ot&i+_+}~O<vPtPz24^9(8av3-9@t?@Zg&`mPnRTL40SD
zXjpOq+mZ$I*#y~vQo5cOAL>hQBB-4mE(WNcdTBc>+cgRu0yW1MrkG}{KAjKPj_4-0
zg=o53kI(Eood@gy>ovhr4MUQz9BW!opP<mvagfNbo`u*PIEL-UGdk-)y+O3~1R(5v
z%{_9KAUY8>hzG_9o5|dcQu@kKIWeYkqDG=PZL2OCo*2Ic0{(d_)HhWi{}$mCtU#@$
zt^u~t=J{MOi<}A4D@4?M{P5%5Pveh2|NMZEi@T2>roY@m9P~mv?LGm9+$eFBmZ-K(
zv<U*sPmvlM?EHjf_VR_WfQN+Srs>6Y{oU?*7Ey+-+=A1SFoD5}*T#vt=wZ0(!dS1m
z(vxGp!yn`9Vzo}ZOjFPRo#C=spR_2MFl-*ae7gPc4mp@>T9DfHN+u_Zoc-|^52N=Z
zrW1KQbD2(4W)uy20NEL<s|R+bd3rQ}8YOwL4fr%DPx*jiE0+*Q9Aw2P%!loz>x5(d
zB79K_&$G)DDLkthY<v3HM1m=R-vIqg^lv3gsPgw4vO9CArj8GvJ$nfq_Ml|U5fE02
zRKx~n*)3GebVO@xo%M93Y4zWlQQ?IhjFm@&9Ev%n<rQpt(_Z6R_Zl&Qs#1C$Dl$s~
z*oNwJxxYjvSjUIfzwZ!g@~!;bb2C~5dJ^oEI1vljv`P*puF~ECc0e~KvUA*PTx+nI
zQY^-^vz71^)=5$nUaJrGrnvg;8{kr~6SP+v?Zy^k)iu|eSOGSdBW(to7+FlNvop30
zo&6~*YY1TN9@Xg=8d&lE<~u5oW|)uS%FUQ9QX4;A>0x@6=TkNc%}+EBav&OGTQJ84
zp?3i!T8ktYjbGD>+OvEm^v3KT?{&wl{iEp+4dHY(sWU6)W{r$oJ{${3ILjnJ#cACM
zH%e|i*Wk!VU0mt8`ZiG5GnVbJ52Jdz|4dVby7Y{;U{nQ3NL2D^2u!YXB}=U*pdwPx
zEXKGUF)pp#hb^EJnbV8QG1&g;_)>y8{j_PbF{j?k?d+QuUnTa|_&;DSou=OKil0*u
zv6@k=I%e8pNox9*Map!EeODpE0TpJ3?G_HIN3{p8b}t=RGdv;J43T-_(L2KmGEg@d
zekw5^sfiUA>qikoyY%M%5pXRy5zHT4eJZ1U=0#jzP$a1e4T5enW~5xqy;VpQhCnwt
zF)KuNL^qZUP=S062>Nc||F<2F*5K(ayqMg9eM1+h4lIIZ2BaU-$k>TlT}lgB(YYp8
zXiHE{aH6xxcGF$MBY|}n1KLK2_J#<0F`17pP|87Q4TW_&(GXV%yW|yUG?a(b^}9Nx
zYSso5arMe#+g2&7CR786ry)=CcDZGE1k&Lv&3&&wV8u8Raar`QaK7M{lC81b9fhpp
z%4rBtV1JgUHW155oRh%o#W?GuKOjXx&RA}vJZ6RJRK^6z=Db}aFQo=?-BIN^g^B_|
z5YG@Is%_@&!n<;`0$Fpa;5?f*>5aO{oX9GhxZ1H%DaZ``yh)duM(g2mf$oanUSN0<
zs8GfdtR(RS0jOJFClXiJ|1BW9^o_I}S&&=>&?vKVCE2O4Owir!F;pd>FL;oQ0;PC_
z82=BVK~IF__D`3KQihQWh6I1AhkjRVcVCP0QMpPFzA%wUus<T9Nih~~$sIlNvV<q4
za{&WdA+a41#iZ18MY66?;WxZp(6__c#qLjGPubb!8VaHAiYZjLAxkT=DnJ*9v?CZJ
zHX9ewXp5VL&qv#8AzQ%wZJu1G(|(j->TYfX7fZ$tZXx3O)(iiF7C>hsz78RGm6iVm
z6sfWPo-<@IP9!U}2xG(!V5&j;d1lj?jsJm{^a_|>l$({z-1E*`%y*h}zfdj3Tf<=x
zxWt*(B$9nnm^~FJZ|Z$owreU<#)nqU2!s$bl|))pnL=>9ZC7AN@ejX>TtUQ^=6LF|
zlU~xX*W}`mHAUH@)ZGT%qcpBGg*w&Eajfa2Vd@=Jaj01p5tIbeSadER&;IEpPhtJB
zX-mEX);|*B#g#@7)2`xntJ(bOJgs(aQcu0vC>cbYj!`9;Mpe<qh@>HhEX`UJwpjDn
zY!th&HocQ-%Q+b75zu-x`Ob4>l0wI(Qq~_8$?e%j$_;t~Sv$-MHYJ?5>x$krNQ2(d
zXP#jhk1@~tx|n!VV7(`6FR?yl`NEj+f4me3he;9bWf?VcTOiEP+w#}=Y#;{=RamRr
z3vXXgSoi|J+VAXJbVzHH<2(#8i|e%9h)LXS7s<8L%YAcY1ER;7;u8XorwHc9)NPxv
zI<6L5G9#y#COD49sX;GIl-}6o<@p5mswljk+wuTW5D=&PJZ;?}_pa?*4Ku+t&`_}t
zS^u-l6U9qCG`2%g@2eEXJHUFd1c)Z@%m+4wj8-4ro&qe^Z<cVG0XeO2ZNqgN2<V=?
zHFT}us}HF(l+ZsyAkFfWZDrPHf%L4rc^1f1QHfv;kh*JkyZkNZ^WsBmn7YTjg;Nzm
zc<0||LgTJhYSl7iuD`77PLDm~MtH7;$bcRtOKBa9qjbKjv{cx~)NWx`gBZI`8NyCZ
zrQKn&Ft}o2A)cU|q5^??_EhKaBHYG&Q=sy~w%B}oeSrU%Si=4y?$_IQ{q1Yd2c;eb
zWUv=9+zUAZq&TW)%tk*0m304lg_=_9Ln1RlRwyh3m=R!uOA)AQAxVK=FPK-I-c$qe
z^yY}cg&x8PeO}1<T32UYLuN>qnkY_TXdeefh8ah>7P!U@=(Ks_Q$wKI&y7uxaH!QU
zW27%lp@*JagULa{t=$T|5xr)iB;Z^?-Bo^1Wn*gkdj#VM@y%#Fw+$3t{MR{~vPDxt
z>b?0DsWWz{?7^LgJbKQ!CrBE%bU=-e+@f4EE5VlKk|_w(*DRl`&oQpBu;7=Gm$f`b
zn#Gf*jx5qsY-10dV~Hz$m%}OXV9shXRm1dkl0JchNNWc5tjz>6buh%e2Bo<`(KI05
z_H?U_ldkg1y{MdTY8B44k9<^G#erHWK@yi+r5(8VZn~{iYpI@zKpKS!x^gO!-8uY(
z!B@Jhw3Easdo(<_6|2vl(ZH=whZWteMqc)x_WskwCPCF^eeAK7dokp(e{c3SO^6So
z(L2+M@QGqp&ndMM%}A`+XdNB3O5DaL;KyFct<$rDPiAmX6XEOzCB|nB5s5tN#y9}*
zt<j*#6-S(78iv(L)B<WeaPCq-$>ef%4l8;8aN#0NxQCFar7CQ6`kzLb<VMXlI4yKw
zwDYy@<T68@s>Rien!Ee&cR!;bn&=70CN~s>4|#*(uU7|&Q1uoxVf@TRf^hsxmzt1R
zjWf@Dk3X;JayvAtVtZ*{r|KQlHFmma;e`fM_w=kWs4+FmCyyoiKWp^TBQj#cQ%4tE
zInXT7!Iuy4MsRZyBl;ru>HrQ<xbhulQPWBLP^c3ckcx^|rfpFpkKgN*R}xHP_882N
zoU;bfn8vJ_%#>r~69o39AR1+>uON+)luK|ZfD~3-VP;7Mv=w0gI$O*E)SH-%ui=q+
zIT1~fIt`A1ixJMuoN5MnLDci<*Km@x&MKe-e^<uv#9fHxc>P;<F-impQ~sg*4iQ&^
zb%wodu-RXZ=3uU9=CLK!gxP4|98$A=h=&E|mMro<k-_h`;F?QeL1^6EsF5zUJnX@u
z5=hDiHi_~m*r6)&p;AA%e)mP8-^Grh=5DiIjZyroxxTLLtvhLKCL=){LR}Sb{qC8U
zt~ENb{#bgPp%>Frm1b`@sV4~xwCLy?g&H8!06~sTGjnW(<SNZ*%E@K?-!X_7Emw@x
zMTR)kIGQgpC**B<b^B$sLy1FaPn@O#>hMiWRK`C_h66~Xvn-l%{Bu(6OBTqpBQCV*
zqSXSY72VDU;1S-eUmKGUS2hpXatrE(aP9h9eF9gKGQXmxEogf0%$SdX$4$hQp2=y$
z9;V0)7oW;vUx;1%dKp4c)IFg?B#0)a-MM!9s>6CX84oL7tssgmn2|*;!fa+-7g>80
z6U3vmCCs5=;8AUHWgkLIx&;oIvCDo77KcN4mnb@>8{?}kc?LI-*y%mzUQFpSuL~XS
zp#z>S&LIDHR*0!P=-I|^lhZu8ES&vZ@@PVJOMFXsZk%kc&gnYh8`ga_)S4E!h+v<u
zu8wD+<uwEEYgxXN*|p7YcXxPFRGYi__<;rI_`*V@?&zRTusSsIQfC#NLrda?v}n|N
zk&rCcn2gRMjs;YYGNf02TR2`oOmcl%(V|%p50;c%$KXTC7N~a7<Wzy9An+foN26P5
zt(Bl_XDB178*>vUs6hG@4T$IG3C>)!*a$sKhFV%;TzEIT@kdW6WV)t@vn#^KXW+~e
z#*~ekDorWAAJKG6;_?xE9v}+BDklM`4c6!b0aax&DYmj+s{z+NPF2X;GL+Q<T3@7i
zR&0GB$7Pq@6ah9lAtTASDEH>Xl7Ik7HYYQit%i4968=hkQmc=DQ7|+NT$p{nc}q7i
zBW|IiKG~pbL+u4oNWg=J#EVF0AO&|DMu>H4Vt5HDhQPc(4BK?NN_B|oBp}VBLXTx=
zACLV?Ygkw{8Kemr&rVkyW<~BdG@GEuv}|^P#Ba=Gz|3!Ay7+EH9KuTn6=j&)EI**i
z1BZV9&U7|~;mRNRwAX&-;BS29fVDgJz7gydlec!h^IvTE_$W(0_vF{Mt<;+|)3OS|
zo<iT)gd@SD)j(evqqkHIP8TW~hLAW&IY|GPQN)&kM|n=a7v~=uC1YfWdEp?tFB5&c
z21{8bctE!!)Z;-QSDo<0@rP|{3T@luVw#!$CLnMB6VXqP2JPfn%MO|mozE7m5GI?r
z%FnHnqE()|Mps}<%?4FH*VxTh)9;uMaXgvMUc4NgxEd^qBz3x?WT2iS#SQk|=o+Up
zS}ch=*+7om%m62AiKk>bz;%d!L4H<?AV-uQ1IYgkWbk}lEY%FId5swozGxi@)Y~h?
zFKu}t`-J4SUp4IKvFG@M9adR=hR%1>p*yu*Zz{K>;bU$|0@}>59v<`qkOC0?s_N7o
zhC<Ae8Rc#A2Bl+fAkug~*^JLlBU=iQSG)y?2ttK4>4}vyZw5F)3vuE~sKRprPEVr&
zYmc3bcW1DPeqlli<mu4bgt~X;P7EGzsr0=(zEgw*2Mt!D*VU+3K|m0l10Kv=6BANg
zA?AU`M5~cTI_g66^;Z^gZ9_WcK^^$R&U^5%qkVv9odCWc)qb9gKYoVm+7AyuA-aH^
z6ARv*rkEOM3-)%>>UT2@aI}~9iA*)jOpp%N2yLv{JCUyp)YIaaH%k;0*NuDHaNS1L
zO4NI9Dtl^J9y7SPvmO6AD!4he&`^(xug=bqJMauD!P&a(2QTl*-Itpm-rrumdxs1w
zPpEaDU0zra-TB2U#1dJFoR^mti|f?_2Tnj#I7jH~shZrGCay|kzB-4-10&%dtG@~i
zuNu|c_}MLFDM-ZRJ4!oV3#iGEyy;oZ;HibDw_5b*@)SdWJQE80fhYZ;u}djWlrzYF
z-5;6-W-(@v4E<*9ukC50l$=%Wv&LcMlb+r85IG>%#=?Iunsl%8&e)lJ8YTbG4ICH~
zV|FT)b<}QbcB9$ccTL;?cBZ2j6gb+!kM*KzlsVV`mX2%oG?#pL!d_flRx4Oa^#EmL
z&bs5H>IUu35~y3so!313YM8nUMU7N;TR##kcc&0OI^S&Vj3(862Ay!yN7Jczdve(-
z#Of@42InV2e?@(5r)x-psk@d6Igir9@5ZmZ$~sZIXg)`~sn{rf!wJs|D0fIK6<n|3
z(F8@GX}(cGCAkMvziw<tdAc57BU7_yScipLCmU{unt|#4@kHY&Y?FdL!kPD2cB>3d
z->i`=#>+k|enB_gdx29@fpwGdmnq`Voa47BfpUuFG4qRaiKK$5pBrYZyJdz-blFU@
zYZ_(~R}*}2S0{}_2xg9$ky1FWM0$k9iC#a4b);+|y?(aqn})~A8R4wager`lo2H0`
zx&%duvH1zt)k6cbRRp<05oKqX>_Wp*T?br)>!C6Nk&AG@D=NLfj}cZ+g`6-~dE~Rj
zX{bv*qanj;)Z}~2Sb!XHEU!|Zn-xgIjEO}VsPo+^lVzH|_8@UfX3crT(6c9)8Bg9^
zZuY8oVG7{8qL&8446xG8q#UrkB4fz_W=fv!Fpun{G@ZRvZ&%P6%U?vXB*X<rAjR%c
z+C(oQ+v^y@gkEX))$>%tG&VzcvGPo~Il9~~sf0DFY}sPEq$ryq<3jTFQ<4LrtlNki
z>r;V>*NRazTf7U=RKHJ40Tte+|J9IKe^NyU<VffFs7L57FlxZK-!(d~e|^07|LOht
zk9Y5H<$UE^Xh3r~6v1WEBgBR2BP=ev88lLX^nIFXvJf)sLW6F*j~ZMZCq;l#%h=e_
zp_nt#9Y{>O%hhhOyha}S<;83s4l$Y&bO9$e{Xj-+_3-}v<tP3-`S|A#7K5ixp;l{m
zzFe-DG2cIS$hx!q80G*!KY6vFz8Nu7$Qdx1zfq)=>EdOFz^MT@_GW|ju!){hV2{Vp
zf=l)6_WmYJ-=-Oa*9Ols&o-9#JQid<^3sg@t#?Fv7ln}QddkJ#LxLHbU@P`LG{v=5
zY#i2lFLMWH{_6=g5R<xRQ%*aN7Q|Sr-DLbqX9f_2o6k#Hw_2Z&4F!cgm2EpN41+u=
zN|+APrM^iR*ifEzBxr5*DDZ>iL6Q-svMcV?%M)gwZEx_KEY`!8!#4B4Q`x$8*uve7
z8pxj#r(-(V`tEZl8kM0wJj@#PRNeKW+d!KyM+$fIFcS#fgZPx~i}1kya`)2*L`%N?
z<IQKF?D^Po)rWZES|iL%1Cor1gJ3OO+f8{Pm<`ZS8%pRuT02(LRX_`r_JGj{3W&?R
zOR&|3JkuEO*G}450P{n=Ah@6CgLI@BaVoZt#^sik;si-&ICL~{x~(ts$dYP_2STCY
zG32oGGnf-Mr5ZDwX7z|c)AV!4*dhON@k-fqpgkQ@>cDq39$%rZ^IJlx2FPP|L99?a
z2oyV|J{J4J^r>ji^JWgu16Pp5m0nwNu3$ltV>=UUZA!Nq1RJIB0&+X>cfnaZ9?{ue
zhpjVEO;{d<>+swaS{2(1Uy{}CY&A>Vg>R=eT#rkoEKX1X<w7xU8&tJGws9+4*wZep
zQdC>+>Ol`h#!T;%+*K0aetwRh7dxaSmvYE#6r6o?s5j=`J82lKWhd`@i~@f3@aRN(
znNy?{Ee=o+hIE3;XUrxmrHK_znbVrk+B!>3@@DzU9MIC0R*Wo5WC9%8&N=jum>Ohb
zEP6XCGnH7diKjHOkZ;4^*KgoflZ-hnh+Zy~DC|O>6K9XrsKH6nAW8~$GB`o5-jyL5
zm47DaFss^F#>@3}W0pEP=<CP`jn_!ThUofF9$i2F^!|Q)^Zxx0C~P9GfE^Tu-`Pc|
zl2gX<1J8alLNfQ#FhIg1|N5+wxhue4oEZ*koWXKB&UmpjcV|?dPDdE>3zpjiUaiTC
z%eGh?Tydq96B)78^3ZA&X}aJD+G4y)naQZ0aVSl_T@BL*8kbWl-|b{cL{&vhc(mlh
z3DZ=2VP+K%{Kb`qr>HW_26Nn$Wwb-VEOBFB)K>y(TCxIf1f$$9$X~ns<@WRB^W87E
zEtWDt>{K+lw5c@FlmsXtDI;%@cpSEu+1-b`FMrgt6@*+g5*0x_xKf2&#7l}zIjN6-
z|8aL1ugw@Ih#fS7NL@R#)V2L*E{$5yDpMdR$inNZY$GRveWo9yJ$;y8XzCIb-XbCi
znbf8|+sI+?MJ%u{y<3189L$C17eTL{GatX;hU;}V>yFs}I4bF!-_~T3;}%HYEB8^v
zsX<H-w{KdCi8-CN+CdCyo~34*kzVPy-kb;}NCZv*q<w^4?)(ZKKcS_uJ>YTh;b0Y)
zHc?y*XnG+xBpXeI{54FAv-uS=)JoJ)Yg1h7nI!d_*AN?!n9O}d!_l$^*@S>APtn$*
z${v{K_7UtMeEn>_QF#%D8R+w*xR>h%Vrmaz*In#>KzYEoA0LpvgguY~>`5Vrx}K;o
zquO-R^m`daB5i60$ut_K1r9O6H0nSIu;x&^pqM6p@Z)tr=i`~ERCTdWzWFeJhm7ez
z-yq+nA)Mug!&*G!gY<=DA$6t|4jo?Cz+2?dF#xe**(~HM-tBJg??2!D@Nkdp)CUKj
zaLU}i`?`l5*kr^H;D~M;HAg}wqh6?(Fq#so;c5`Ic+*|3L#uC`D=>B%d6_7rk@*AG
zTq7euSokG(C%>#I4*GijT<63mnWD%J9yld4K4PU!9~buKDj10ja%XUP1pHeEeW5$v
zL3z4{>o@+$uddq5d%D<q0zaq=HrAb+E?sG0u~B74AC1rG`nE&8g>jbAYFFWoj(QPP
zf?5ov6gbeoW+p)X{)wyv8Ekp`&X)*yF|GdIK1f_Pzg+xgx3l@_*>83NmkWn)_O!S;
zh!!$H{d9MK^L}>s9@U&Z>5z^Y1Dgh9a#wUpd>2JNYzaFqO!v$!V@NuM5zw<|a<^o{
z1^=)!__vn1Zi3L}PO&U|dL~A+ib6n|ki0!bUqi-pcfE9}rPq46yOXJd!__H*eW;IW
z;(?Ps10@tgfk3fV{-U_bxKDou1mej<tP;KKj4GjeD5){&ADjhRCXO1W?wWUF(@+S3
zi{KX;0q0^pIqM@Z2^nlnKT%w#J~Iyr?-tlIP_N93g~uZYi7luvB{{KF<haU+=zIq6
zQ9{IA<QNo|=C_lF&tLA(Z$JEW|Hobb`S$b8hc7?ge*Qv5ufRmP^XUcB{1J@ooSPZM
zH)BRU*NCgJJlV+57?K<wfZ^jDW59cdS1)+j6F2ii)-%#Lfs9xazyhGj5Vm=$@laKz
zOTz*ctpVC7=r$hbPGCu;V8HxH*MAsVM;IC=iChQtgzMXzcSSxte_E!_WuN>|kM`<h
zK@+U#Zi7H_P_(&Oo+wttY~;i+VX0|#(DS(E$g67W70jyIJJ?k+2}ha76ASNcnpEP1
zcFEe);v7(>A#;vur?PUqzxm~Mx4Hda56GQ%ck_NHeERwBo~R@;*X&sJ=t2-ogSmav
z1Q&FQrvhU>QvFqMgxNo<f@t6YjaZ@W5@FWqo~l*-JERqSd+82iCU8&KWv)Vle;c5J
z+VkOyXD{$)aM(Y({bqRhVm2K7TKa8Fc~UQ+iEu*BB<Y+&ymNQ{@z1M|f4==}$H2kr
z_VeARKYso8=XW~W@VEE$KmNn^Jbd%~uEqFLH=9Pi^AU`~YV>wbi0<xjfOy#hd^>by
zC#QH5IIH481sq3?m7%qK=7+yV`D0JBV3gmpX*uP8UU79a3syQtp>1aHq>^%x+cK?0
z=wDoE?Zj9^|BcmJtXwavEC(_LzzVYhkB=li7E0mT7F$kHR`UP*a+h~^FoI`sI-!A+
zAyX2&6UpbM>vtmQiNxRtJDXp?o+W}7SJh`&a>ZxW#Kb2COq(6NFOss%k&nks4m38H
zrV$p&j)cyrkf?UutwRoE4ov*kb$>~};l_Fh|Ds5WWz?s+FHjZ7iH*Kri{1w2E$wP2
zNN`{t)7}hilr?K+))0I!((x3T(rrK>Lgje;Jo3>=8zSL?mUeUfkZvWN+iVYWbetkp
zo)!u{rsU~%r${hOCHIGv28+ovX0m<w`GFO8VDWkff~9>}f`5L0@1Q4^9%Tg|LN^UW
zVw9pOv4cmD0)rRKSv*`9<yv-?D+FS|8Q?Lr?u57Gv0;+Ocrs!s%j9W(T2X5$T=q0X
zjxwfOUr$E6Mi_khPL=2B1{#sb>P$;PBI1x6t$NIpIB#ZmKYm<&zWez3?*1<Y@s*hy
zieuJmnobZkhMFdNkP{@IHVv1@dXA$Qtr1UI3AJswRzHrK)%X;29>Ls<b4%!4wF;Xx
zTfr&Ajjeu36I#8Zl8qn;UPjqE+9sVVS%RpnH%-U$22f8eZ4BcxuzbB%iw4}(rK50p
zLoxaS1y)XgovN_1MYavpLJKDV=DomCffL0XoZB|ACMX=yFq<e9#gSVgN1mc#`f^@*
z&}sS3Kz(OYh_T4d_$4X;i(YQmePqt&CzHd0Kxwpvif_eSqHxE-XnorM8vnrG^WeXF
zEEhtPG>$}^DqrId;Vh2Mze+AOLiOH*uO7bK-1m=r|KsrM-v8+1zrj~Hj=%bk&tK6Q
z0JrjV{%VdZJ^Jh3R|e5jdU_5zAsJO#R8T+WXCA-*_@!V+pPA(BYuo5!OAKc!pd=Eu
zV3McEV9>xeosbp0!Z(yfq?=G_1`KR>kh&-50{BrQD+{~}%=wW12B|5pogLm#u61C3
zf>q<7_pw_;pyo?^t8Uf{OwG-h)+yp8yuJ*VRQt-Uf^Kk&E8Q5!A@ZR%RbUlJ<0=Rq
z&d83>aQ{#d!-|0^jG-};DN-3zx?E@9{YJY+*}4a7$B6EF2>W_z?2@cdyqJ|8vI;Eh
z<dnw}Fn_CiVS9LCTxm!)v69X!35M<K`5_P&T0%U@vV3@Nn%q#cu^x5})5{q`-|z|X
z;CY%0v8<4a<$!{e{O8CYdw!sQ#XS2jIEH!;H6TF8bV7T;{io6x?SY2h_a5-@(VN2q
ze9z6#9=-Ya@nJuQ&Z#!>n324lD>4~;k`=u+g8KnZUeGvyqQ4PsDxl%rGeKq+c(BPO
zs|%pLMlIm^bPRJomo;4pWeR?-SNs+%scTa4)t0XgRXqusan#sxcMkCjdmUtHb27$v
zTn(NbX9Z5Utf5hyvpe;kUG}(5(v=>=dH8lYgO&;ZvI?colt~ijtoL<+{p;nO`v3O)
z<@4j0!~XE-#qnU+fA;+LUm+V>2qYwXI7?wHaY!N#E*ZX&k_3r&HAeJfhLZmAlTSB)
zdH?a|ovCfYF;zM!^A4zvZg&{K?#j$I<Y(G=8NzgtX$%>P+^o-pMT`fpf~FZ+We0Gh
z(T~jmw9#M-opYeECsHf(-8gbkB?P;FvbEGjaiRC%j6EBH3@|FK_d;jBn6L9os9rXg
zs|)A#RZuSL!gON&eU3!D1)Qw=ZL|0|g0!9VFnp2!bF&2&-QmJ33JfXIgltMX)FfK<
zO@_QwM1lpRZ-2bS9^V4%C1Hyh!WRN3mfzw=i3U(N*gmhko#Q>>pCM~N)gygRp;dZq
zblECp;M21UE`99EeJ80h6)PZA&l4w|eb@UQQc$*NUW~GvhmNHeEo?;%pdQRNx>u}U
zk5^rMLWZU8h!m2B*nBh6mEKQGwER!YF_iL+Ic`Gr$lb|iVy+|GU9S=u;GtKqQ7KQ*
zeedHJ3*QvFFE_0`Hhf=(sXJM0F{PX7YP4qNbiIN|@bt;U2lFNaJx0o2NSaqu&@*JZ
zracw)(srW@4D}kpUGSqZM#nUYDE5t~qiVd7C=1HYVxgM_i@gQ*ZBWRK*1<l$wt+!x
zDbYhS(CVQtqtsX!usx1TUPfAYGs*Wo>OQWtYO!6E459Yg+U@TD`0(=&pd5W0-U!u?
zFt2bDDx7={houh-&pS{|vwb6(0mNx*(aVH!lXFl8s_=(8wYK>>^_h7xeRrUXE5Sk1
zkj-v>dND<H9FW!F;NVxWB46%5KfJx~ZM_w4)c_#6_Lmr+ooHsfh`n6Wj1sPCHM($$
z%wed<W2-FxROY3G>_6IGVIUJT*T9cd$`bQBZDMZ)@@LnYRTngCqz@i56th_x&0b6%
zcs?2B>;<_=GnSqL&wP5uZ{OetBvJb!MxzKxqUd>KBFfi#3I!mY9iSMH6N2BQYC@Qq
zl?E<uH(FV>8eeDc0*xnk+MVDu12t2AKDfsO7zF*Y!PES)+wD??Nfh+hy}SMKj&7j|
zX_5bp>dxaLUV<$$Zu?gDxXIGjDDPOHd^>Eo^wP1RRnD~v&5}IsaaeF%W-0jMP=#bm
zofbc@2{Pdvp_@Yw-NZz=D<va3&%j`y_UUvsLSi+MG#03`nf1)Toos)CX<oHHso-KW
zT(Ak%Eu=G>U+FnBBQ|hQq<V3J(>DjAK1^a<>EiV1=#Yny4>H#dx_S*qdm~Yi1*5my
zi)^Tun^VmSQ~7{EXc&IV(>Zga@Xkgj4J9^7SS^?!Z4M{#J?%o}E*NTGZ8~ovpx6My
ze^&`p@mFev=sz3VlQ3;h><S*eIBx2>Z2<GU)<;EWu>f;PiqDuheOL#5sJ%h=cGD~E
z9HCC2Aov9ewBfo<iYHHczu3&y*QNG3-sn-VEeDu3T+al0g8xF1XXbl8F*&4aGK4Kl
zFTwWe(ap`)v}9XmlSQgs_Yod&VTjjw6`9Z@y@#>{uB^Dn%zY3$l@|%7A=A%jGQGmX
zM_>N(Vf_A2^AC+>?&@JPm=g93noOKd9UNY;+6=f`L)hf76H#+jVMWiHUWeGxAo?JK
zayk^od9A|EFvJA2<)EJ5;?Z1g^b1XGF-9}x*mwoQ8)cFh_vbTN&T;gNc_ApY68w<!
z&GZ2OnKpudJxCR8%<Uc$eG_uA2XOM;YP8uvjM2c%uJpo2<`;Uo=D-aUY$!0j0%-;c
z#(sk^cT|6AwdkP~eqmh$X~4h7m3L4Bq{k{5y{aC=NJs%w22&q-8Ee$^T-B%59SZDl
zEA8b)QJtOGVeQ}ifwJ1{dkZ`EzHEx}k0}#6=1@}+1%W$JB?C1A)-~9G51Yd!&;B}z
z<S|p=9aPfjk0UX8|9Zs89>K@N7AxPtT_E=zlK6rVZ|lqxeL-knXJ5A(VZic=K{SUm
zzD0{x*2x@C&hKC2RB2qR4-Z$kP#|d+f+UB?7Q`r7bJ+Jh9mX`luSMUk;sVXo|L(bh
zG#ChEfvN<CN0kI9rHnZ9n<q(i<m)BDIa7E4I9bndts|Fen|yU*v8e7M6&XT+;NC8L
zC)Dh|6O})U2W%boI$JeyRyO{Xma-*o@uNzRG*DOu<ouqTPPGx!Rk>8aY;=-WC<GWP
z<?3Bt9$Zy7eSct1TlG^Aiank50OJk0>mh&AtwBY$m`B%wG#iaiD*BMl0grla0P7LL
zKun=Px!eHpJr!bM%C{&<G`wtEP(3nQV=u&vmHH9{J|(bj5^H!C{?JfVD*iwNDWfCs
zNf6yDc{n%<2kB`d5ys5Bu<I9wC{f$B89GC~Vh?IOx<3=ww{NB`f3+r5@6!oI&y(ra
z%ECb>qzk=ICL5LkWBoV&tx>22)+6mb6tX;gl+)m|G~_wV?+)%Tkwuf~D*<0tJG&F)
z84M1kZj|41Nmjv3j4_(6l!(IW&2r+0G$l$Tp&Fx27Mq}^{D&28=`FH!2xyu*ki3(d
zFSkVQVRDUwyT2MR2+BuHymhi%;&fvsN^5gkP=UNVaUJd&IAl>jVRUhU!?xX29`2QE
z3D$^9il7wiyUU9$^y`tArbtlJ%wvOF!e$Y@#fG5$8BW1U&NJ0d2h(N#h0Rb8%(XlW
z?eKHuo}Y<gL51<2%(ha?N60496*EIVOpNdV5tF+1rk%B+*f0!L<2P?i>1FOltar=<
z$>$Kxo;Zz;BYI5aohZsMtp--tFfFyl7{>VS^4tYfw}fQ?DRZxpkI*<KnhK&p8;onk
zRQ==ek$deY?;6_>m9dQ2#G%kdX=<seG_5J0sGX~(#|zOMuYlqLc)`8kr|WO}h3ck;
zV<-;{%qV7Uy=+o~8kXj4iq0qCVS5~PT<F97^cfveKL9<!VIhs{7%%o)N`GAD>Z{=C
zg)_4ZH+2D8zX0XVv1Z6|U#+m|Ze^LEwF0r=PRSCrGNN1rr(#31hzTb-T#4{A8*Wf2
zFteJ_9OX*ma4M)PTy;P-WsiyfsFtSWx5Ou_wi5gJAKmq4{*0#tHRv-{e_rhA$!0gX
zxxd-UJ$U<TV<$b*QH$V3z<^Yj6NL1JG9g6<n~3Q;RKL(vXthk8kdVWbBo#<+i9k;n
zr&!;PQtEhmF#oba)b%Zs4N&r`F8{OFxCct2uTgX1Yt*RaUpi(qdkh@P9zYX2@#uqp
zu7X-)5w7Aoe}~aT|4P3Q)Y!u59+ew+Nd=2DR_?i&Q~cFS86L@F*P8U?;5;DMlPT$n
z$a0Wo5X9qZd5**YQ}}tGP7n02<W>I#iPe0ky&Ezwpx-Vsqdnd$PM*hmMaHzpdmZVt
zTK0bV2-i9!$Y>c1fdJ0KJU5e`^L9kl(y(ZS5WSZ5Ybb>_uLnAZH-4dc+@sUzp?o4N
z;M?^QZ0U+8Ii`^{I|>F9h9+c4_OXQjISq2gU>aDnFN}_|5k{!uN`tV|Sy6M6i;IE|
zaZ3NQD?0dd8$}whD~hpjKm$u{+1;Id1?bf?9ZcTEAK?0(3giYR+P{!#Y5T0FV`7=E
zi@EUIkBcJ@Cmss`;`zwrpFFhgfBy9O_9wVzQBuA9T@U7ZvKm#$#MicoJYWI?MqnnK
zuhOk7?e(|bba?^ivdMwni-)w*xP)ZuCen1Nj}s!e3cT}#OEBS$AsYnwfs9pPo2zQn
zZLsbluNeXAh3dk#_j0v`bbx>94jjnqgtx0l#$OLT4bx1z)Q9DB0xo=R(9enyGoHD@
z)-UpWSVLvQlvsjsju+-&rk}cFhb;8h;1yvJJPH#9pzz6fk&bGFP39QRvCA3?Q$bI}
zUROHVxE8NKZr(g1QvFw+$I&EKEn<5H5+d9rVwkL8HR85@faG{~tXd6@=IpKk(U(CD
zOQfDnDtmfHM`NBQPlEzKWvmHoy;S}t3{b)g<R!ryJ+YbcE$?=3KYfBV>h1e`R7T$2
zJlucmA$(zYcyw;}u4o?J=Asa#oSb070q#h+Q$wEv<+3&uuBdf(8<+dpCb{2nN)wY{
zdQ!dX!P)A2<mjBmlu%3{ZjD@T<+h*o#F1^VD*>VOYi{|{BBBU=s_<;DBr~YdSOvr;
zBT|7h^f+T+rPyt^C~@u7-w&e3NtAl&-X!9LcPesyP-D84d#c_Q#KI$B(`7~ild_rv
z_45U6r{yp*A8v&#qa<?E4FX&QENIvYg4x(4=ANxNPp7x{%;o^j%1OC5Lx*Q>2q5~A
z&8DU5ssS0zn`RxT--xF#%=R6N-Ln2@aQZqAry6t`6*EvbWHvo%gz;fOG!@5eC_ohZ
zBIloyrT4yiTpanyJwb!_p|^m=kPm@xFfex#dJm$rf-#W=oCrD|4>uJ%mvL91YDg)8
zPuGwVFb^q+cBdXZ19d~N$4En)va9r8H5|fe{I+8Qaw3DF>)EY9c^K|BTbjDH$R6!E
zbc#SJB2-?`!A4MZh;Z=QfY&L#ID&*oP35j#&!A{XKed4}ap7izRx@jsDvDBDo}Bg8
zEiygjqYha!t%wwM6h5DqdXacIcfxqg3qzE=Hm#ztDW(Z7v~=<y$sMP}cW0F}3SrSF
zcRHpcJ_KO++SmbQHlc1aM1pBG@|0+vhmbsrBw2Y@TzOZJ*-+=%edcvn)lmnLSx;YI
zPH`sHoMFzNO+wV@1KOf^5jrHw?dcMV5};qNv(<=qkV!vm)1}tJG9OZdb7~2I71#)s
zmW4Z>Pr(J*j1$|q*RYb%<)CInjmi~BlP8i5uMSUC{G!^mEnsy^c!PNHz8nb$i<_;X
zF@oKe_5{;2sZ<y<85G<A<#&Le{30+xd3iDVVR4We-LBSG-Xf*{h^6)=e?Rn7l(V)0
zi8@8va(JVs#CU$K`Ht_--Yul`o`J6g)CX|uGw<KYdL`M&f9r8h7Dz`c22t&%!ih{^
zai#lA@cy>-$$q49XK^s?4u(<|(r9W$4ca*vwKx}O&heEcOdDT`7g=*rSG?Qmj-5P&
z8rC*0^7zeU7dyF}A@JH2dt4L2VdO+m%wIz+XZqUJdWIYUd<xZvbNK9B@MXO(_mGs|
zA_d`lI34-u<f!3vk?vLHS2%l-xH2HR_+_O>1ye9{=RH+2$KuS~LaNn?i@e&g;T)OM
zrF!UmWJcd1@skF;A^a4S;j8d_YjkMs6$s!t(X6AED642B)gwY*R*r%ya{Y!^CiHcJ
zG_u5Wxb?}3zjEiup(qSi7Ku5mHg^-I@$y{2%V)^BIvK$~Ku;o3DfGx^@bJK)<Vxf-
z31Ep4$7*#Z*8v~yp!6P4&hgpy1bjRHO{Z>~4Q+PR6S#Sl(`+#{nJg~yigBC6g3;6R
z`Gueo_z_vv<jIST1&Yzp!HH3hD@LMVW7Pas=i15+hRdD}a*wzb(w2)w#C0wY;;NSC
zNW`+d=pX(dwNGwAg~k&MhX~+Gbw8n)T_%+79nfkxO+m*g75$?I+INkl2uD(+(9)A@
zoq>^F!m6u(BDnf_L|6OY^K+g`eJJ?4?A3>1uV(z04$Za7>dvZ~=BZ6f$OB`}5(9G-
zj9X7p^TZVag_BwnF1#tZIoB5ADbDp7g~=zG(-5UF67eb2{d9wDoC+0GZ{ulWMWbi)
zb6UaDBJG3d_y#XDhe)+kk{ff1aorrIaaTg^o20O#!8KCf8P3CRI5%n9w7}+X?V1d~
z$h$_)#(T?GLm$iit=Eczc>1VD0-qYB-aM{=kM!sl&w7QTa@K@vH&y^>_~{&;+hOBM
zgJc3Js(((maC4i!W*Za<Mu(d)z1TL1y>v4=IS=Efzg=X&m!+^NFj>a+&D}jB7<&b`
zoLlpJy5#0o!?+S$NHdzfu>7!4e3cI02t?I-xKm98`q`<ctyyQBFc%Im*JIO<fPJ=5
z)izgD&;V|{c86RwkO3#m$qh$Oo6D3|Qqe186c#MIXi7C~*Zy`2vk7M1b6F6jm$(88
zM%&?ftpkSnzhJ8-(c-S4tcE;7;9$X@F~2hM+&8Lj*-W_IE14=?xrA^eo7O7tj+(+t
zsubGna7V5wh??6i5)0yxw=EZeHXS_zvEb-n+ToTGfr&{<P$Df+5+q5~u5fWw2~OM!
zqZhFm3z%8j+`K|F2=WnS%8&QkvO8{9jB+g=x>DK1AjyaJ$vm?WnY!{LRA;!Zh1=DP
zS`0$)RX{lMW9+d2b-jLdIoF!Rg`oAc8dvq`%v%?IXz)F(I!OJ~Xo8$6XHDOteZ34R
z$rJ|4IH5_G8lXjqo0Z!qF%*-G=fvjYY?IVkY}>`R5Mv?m!QJ7_b_cQXa;ignFVwd0
z3t)U9u-03*0ZgH6o6T~nFgmUgFErxj8C5!h+nyMpJH!y*A%0aXM=-hC2MVQ*ys)-h
z72I(S{8|4ICZr22R(*zqfIKpzG(?f|5BIo({A7Wtm$-n+E6APLO~>7lr2vX!1#<xT
zV!oY;V@+53UidYG3azIaLeH+IekshIdB`<_rtzUrXOPfnwLzgb!tKgmwE{VoViQV6
zzl>aZ<fVC><kStDDWcHpjos0qK-r;|a1d)4ml**}Q=e7%Ea4)|s8#rAcDB7twAxi&
zv4ZE3*qaOQ18#>EvWIVO@7KT1?q(mAO$05-ESK7V^bDirQdJ7^0`EKFwkGuJ+%Beu
znRKIh)*oX^4Y_S%9JlSFm=&axSxzD!qFo3o6jT*<@^fBRGVLTMtd(mI1lCvZ>jB@5
z;ML^VMBbPce%XeTt7^9a`tf5KLJq<oja=+GqQ0Sj0-jP`Ry1gY{JJ%g%E1JGwKjpC
z!l&^(4WO1M&XOc$ma5ejP`6N|L&}8}vM!kC1`=Xw*VK*6P2ax7{2-j?@e2)>NMO01
zAPjBZ-`;*&puBsT->D4^BUq9<+xwv*l~&4tjay+&8L-jG3N*`Sp@oReHYN4Q=OMf%
z>+{eW=-dqdHx^FCs%}RMT71DxK^utQpz_u-nQlS$rQU-hJ!bK@dnS{D2biHyW5Xvi
zPOhqh)=6Y|1GC(G4fQ~Em2kxaCi*XIE7<BlE6X$4(qG_9$bE%2Is{H0Cf@>$=_^p8
zjFGks%QV3C?UjF+Hlt@@jg&Q11shSnn7Fbs8Ln!w<T<z+jT*aeE}pLC27AP}2zzmG
z`|G_WE2zAP02vaJ%@#Pr#(kD3bmS`}E(^zXus+_g3(Jks%&AR;QwqG{5Dl<J+7vZP
ziDnf|8!Zg2h+EZbbWTeJazb2epZ5MUNFlm7p#2Uy|G<Cpw;s$wt(PleEmpk!_zK+p
zlKiDj#P0fZX0A12?1rNw!$ELXvLiu$1QL?XkIDs2`JsksvRk`h0*9uWM09q^8wLtY
z)(<8J$?|-p^QG;p0_(2%a)s>;8jd`v^jg>Xu)A9Hd!2y!vj2oGAV30mR=}F0%B`+n
zXal72qZbwgULYcpqsC6O#B9mMk)CZ#>$sI?oADuvfVVl8s2DSB7n)xvSFcx#`Mw-R
zZD5lkp@bL`y!0BgYOQ($&nei>2U&2(ci>F71B~fL2?d8CdJ{!t%@HE5^dSEbA%_QK
zNZq3Lkk^u|RGfK9){v6MvCgo}XT&e`8nGsbHO>_l?>-I|A3xmPfBbA*ipu_Ufu)fl
z1sLp><6%l)<1qnL$P_>!58Dv2fYSn=*5yT-I*9};D6TL?#76%vo&KCW1L<MSa+x?)
zQGHgZz}$?g8Vn~l-wrNJMysCS>I>GjMv5~uS$3PexR9XesxhHN?n!eM6k}@>l-xIR
zT&8JN?rz)(wbXK5)C73ZrJe{mDxc1npGrUBJwjfF>I6(QwCxSeNfJjuQBdTbY2p8W
z?%uV_jpWD@<WIrQoTHPJs<a8@lfCMi0|bCfQ~{YFfXrm+3l7CfNnEi=Egw?#Opkv1
z-h0i=9}$5psaySJ>PSq4n@5C)yScf&?M(W(sxCM{8J^Y#{1pmS-xjfOxJYY54VBhl
zxqK;fE*sR#-d&IsJBKSOLNaIlc&O4lrA$m!L(;$!A|dUA)`?+RS^Knc<7|O3Eufyn
zx}nVu(b_k+yG^tH&dyt=SugbVhe|=xjV4M#a{ZOKdxr$rX*?Rcr?s)lJ2mcg;Tn~+
zNldaeogfGL4W#Cpf_LG%t)LH;ASN!>TwXSCn<_570wXMNDtAX`x{{Z%;T1r=hC45t
zU{Y8cZ7{8IKGjo?a{gK=9$2D|ZhnZTe~vQ;DIPN7Z>MlGJ4m9b3opglyjypu5woAJ
zp@l6K(0%Ycfu`l{&*Yq7sXJZdH?u|?-hT`46Jj;rHx0BLUXB*35E3~HAQ-llFcnCz
zFuUfw{Jh|JunL^M3MPKStvec$|JIPmnS$AxZIH`?;f@!)g7O@;%Qgs#nfnCQL+2*J
zRz_Ll;2B^@c4xTTw7;jPgT5*jAXHM<H&+l1oZNCBdyEh^7>h8{2Rt@F<pSL8=96Xt
zC0_U2y(B!v10n%~R`Vcr^;<?Y&M9J0+9G!;0v#@btDD_=9v@j&hK#Rhxk1&nBa;g=
zR3|Ty6|FL#a;3IzNRV(`Z4=Y`R64Rea4*|XIdym;2i<2*9h@8@GID%XWVmeCEIV5h
zu@l?H(Bjd-%;emxXzbs{9VM`7&@t@>kp#3{Sj7|tr`B^v0jUDlh=pUCc?DHHB(Y|Z
zR#2^JOJFwXD}Js`5Ep`Gq!5wAKJV8(#!AC?vFc(Q$1@)~+QpT<AXFtZDBK{$qE*$R
zT67FU|Hccv$TlUne|#hyP_aQoI13xvWkuk+(9Z0Ti9xwih&=OoabS@Gfn4eTKH;^I
zx$K~ahTE9OYTTj_>jq^zTFq5B2BldZ#-QmNF!q}{qCC<Dx2@3u>s@q&Se=aKr$7A!
zSK%#WTrWVj-`+t5W1<S|uwn3|p=NvEEL{R>+dDH@Pj7RNNN@r|X#)#pI$LMFXuG=j
z;IbX#khbnX4^x$5(@mkYIuRmLvBe8BK0%Gb3~b}5gCn*-qbJw<s;yS$#&@@P^JyFW
zV!&&i-Ha~LUDVkqeF1Blx@2IdT)!V<g6W&HnnDaEvfVjLnE~oYu6g`w-!N?wJihXk
z*sPqMY-rKZWrH?~D0aktjas<U0_ug*XU$gQH3tHm1sUb9=K6HNzoxdU+HFha#4sCh
z0Pcg58`<`Z&(5W!>a@_3k1C)ig$5M_PD3*XZMIIA4gu@~i-K%=vVc^+fV*2H3$=JM
z_t-)xex&NbbPSG|F$qa+k;kb2-7QEV;);VpSr;%;iH=@3MXT1QCr}=`?rWKVE|U3&
zbP|e1DSXIkM%c>?r$5}HRr?y~!TAl6iteU&vAb;2@{I_mmwo_@22SjB6scOVB{Mj_
zI7Y=)X93LAI&!0DT<Hr$aEk0l%gNi%pWu5xQqkkfh(aauENL9M-Yw=M;ZnZTgJ21p
zP`pD3WyQ}nwz-tjWr6Rlk2B(M0tthK)!QKy+1mz8ik49t4*_5~r{_t3mgIoxIj}_D
zuFWv#D2EZM(G1IR-ik7SMIdFs#&{79RaKL|&;&9VIuKP4EAZ`dDoqv1Z^sN=bkS(I
zw(Y_ZQDI{9_~sF1;0_m<C^~3kP~HM_2u$iuW`^m#exAU?j&A7qZ<vt66(_w^CBgI%
zn|Y&v!A1I&CWbEof-q6{9QKL&QavK2t(o$uV`PjzGd=iTaBl?+P!aK1hyy#e1u<5`
zc=XDrSZtMf*RH@xBgbo%4jZJ{3f!J!4MCyz7(kClQfx<ZP~;puyC`PGU6;w0$^>o-
z@n9Y7FmD0#T-xL%?1@7bdjaAG@muD^+M_OKaHTigou*X_lXAzkU9j6wz27#n*h}U<
zIrgob8}ftArKXBo!QEiaKO-3RM>=ZpVRlvK7b!cr+ZGA~B3`f~TsYC=7VL%F>N>sZ
zGiuEfOdppy1L$LDWk=m^CMd`A(XjpS<>MO^Q~L_#1ejymf84~6b^Lg_r$!!kef^E=
zb(j(z-o4sE*g$Y}?LHPsj@W9CevaREfyX}|{N^`pEs<4B<So+B<1W1Z`QV#x6tw#_
zBX_$utw|2`9(%S1+U@pI-JoR`KU`Z$Tn*A{)S?HnM<SKk8hW;zm91{hXyX3CNyRMb
zQn+0%pD=oGMEf|GqpjGk30YqcEpQC+3VIk?`jMnD7fDR{iM(<{cuF#WEN;B^GPL;f
z5>;qTdWcjjhdSxi+D)$5?A0|VSb>V90G3-B>F^eF+D*e<Q{3(Wn7eQ^@NR1EkSLUK
zDRzjVoQCrI_kc975JH_BAZy~f_ChkXR`5i4Oe+ea*o<8u?jYBA(a%P;L56tQN7Aj?
zmY0{SpMpJDTB1lA4SjGd0)qofb_=tLJs9Z2_(sl3YBiOeO8Z(#td1&GPK$6<V)bM#
zk!&yx9E_892?9&FVks|}dn^`Jj|-5V;b)x``FQj!4!_ip_Q`I#gLNJ=l~^DOnAtvG
z!1ZLKWgL#hxLR%%|83Y*sC^~%*PF<P2A<7S0?bJl8w-;MgOaC;Pz;V7yBHG!{XEA^
zdgtd-1=85G7d%sJ@2Qhuxx4#KMZu$VsR<HmY-NT}3@u&3o-%X|IkfcPRG`HN+cm0H
zL&lfY9rRwgdMd}=;$Eyk9M4&q7T!8=VuOb8rn0mY$G7DGaxu{YFe1ZmT<JSFzh!=H
z7629HZ#SxUsF}s;FvK**XIRkz>!Z^C052kzWJe;%UjQ3{ts*cHm$U-b!52lVW~@?w
z5ugOitLAE((nPPvgiPvQk|e!Q+2ZRLP@kQhy%-#)on(OpPXAMxpE4D(2A+rmL_8#z
zSuTN~l_YWU0`CaL(HNy05g0PLgUd8*_V_w-*v@8J?XfV~d5OyP{q!05cKBGs0)KnA
zX=WNB-Jel1F^bCr>3vVy>Iblz`XcAA)a#w|qd_Vk8q(Yex{?yzKOV00-J)>q)2Y&c
z#=^HdX=p?|bjZRW85bx2?RHJora8TIADqdT-=kjQzWMQoqy9Q=@HXJ=;vI0(GS3_k
z5Zr%{&>nEc(70G}HtXRA(pDEN9!YOXKAx3$$@eTbAz1s^ZK^PlA|4dcKR{yqic4)E
z@t;4@TVyD558<X?4`b$p>608NnWdf{z-t`AO@p#AE-1VT&0zdpe|>_$ukW<Ma<FFN
zS8FOCv7DatPrJ#i(7nN`0jd#j&MG!@cqSJ1_uOWr2%aHK{eR+0Knkh$pHUauC>*Y5
z^Ya<>DxR^(7N~Y-;|mJXD}fsU5ltXHU`+m(_ix|8w`>0fDQsT9LB-fl2+W6a0)hEr
zLclHFVlSFJJID+?Sda>Y-j0KEHAnwKC;fNn`cu(_{3L!G5}+lUhw)hXX%SSF!v&*7
zO2nC4JQ7tBZvoR1a#&(pfGF_{_F7LkS~1UNR@bRM1?BmcJcu~KZ_{PMY=x;&NIR2|
zmM_)AzJi+qf$WQB{qgbBo7e9iKl&UBfZYZNcup{qvkj*3uaB?)gbr0@X}0yt3h*y4
z&4<E_T5t#t^q@_$`9Sn;tF^mu;hcR#C<k=x*IrT(!`S-uH_D)@Wngdhlv5O_y1QpZ
z0fLPPMY>9}DRmV~&bwHkjQv_4=JcYfTz}c$G&<#G>FK8r(0QM5g7pYwBa4SP19hmE
z9uZRmz4{tj_gCX)w?@)3!<8JjU~bs%{X#YvYE6{p!dia%QG|ya=N#cs{(01VX6#!v
zMVwypHA1QJD|1I`dm#z3HFh!a>Ml{ZA_=Obf>{q{MAcX_QKHN!CdJyd7|6*2&VBMd
zJmH`)480U{By_Ah$Zl4;z6b$}Ln3NZ2pzmuA{5>=_u2wF-feY4BTNY!l+{{9*+455
z))t=raj9W*GI8Eu8_y>&+t~WhRXdZDw3I~-+eA|S;ha8Zyzrbpc9C=G!hCT!vCq%n
z`Lo%5!fRsaZnJhhJoAZiS$AO5=2tdN^bjob9UC`awy0msRhYuJn=RJlD(Tu=?Yf6#
zGYMd>8fNTn?9P$z;?Z)@ZPF9Wd|<hOHq#=W)H!aIT+U!2i@wqM;5KsAu)wWktK*49
zEmW!);0Ymm^O_`>9wS`O2AGTPMks-KpeA{ZJWwpI^zqaj0DU*FP|={?BPB$SlE`<1
zxT+kCXi{L=R$x9(n-^h+b45jAhBH-qGQ(Axby(qYL2pf`aXcg6gmI-WAY2(Fl^fo_
z0ol<CDS9zNHfzruZwk~X5?fLdIcSu{V<l^C;e|z)Y1`b~+gb&WA4h0veVK;jl~tiB
zt*2F=Q)*E|Bd5p$4;&?-PMZN-1I_mnIMkbo+J=%eTj9%5X3vP5lOH&F!}4Q$J7kOr
zx7!G0HJce37&BeIc|LeE`0xLHa2J7>F7YaUt56g8ULXZEyNzv3MzQR$F_A{dlFLbn
z6JrY31pJjr-oBS%58S~y0>+j1VL>-Sj7kF9=;=x;;;9-RP*n(qDkM3FwL}+!#*5vS
zCm$)y1-uJLNyxY$O)sqKU@(;q#$64M&}1#NE*BTS8OV9di})QMBMZLKNK0PPyVC=t
zHIN&o`2ax##-74n!oilAQXc`1`e1+$^sr331*L7fP3tJE;2J^JGr;KxdDR1peOq<F
z33V!46F6I9PR@FQQn;*zwuOrnShcH&;Ho+>8=dtC9o#dy3Sf?n-V}m}`4F)FEy4t_
ztXxyLFG4a*90}~5CK6)FQ3ejW(D)YT#M)4OO6gs}DK-w1G`m!K9&&BqVwhUA>VbRp
z1?RP-QmkSh7<XYC9dh_<gV3Af<*^7A#t^xuW?SmV`gP4ucX<|$D^iHA_YW+8J7y+G
z`e4ZYL<xOE4P8p-qZ=6}21+^8VbXeph?0kM*X$%iG0Yc{8z^tjbU#Rf2Qf+vbSD!}
zYi$p7(h`Gp?a6tI!|gt2)1zUO=fcAsa<t%|cs%8REHWpko*UF8>=D<KEz8MdF2?N?
z-p)s2(bhOvSyAhT5kU};KfDK8R5ID0U%&a&;}2gAUcY<$2h>+OLN41lJ1pg%r``*9
z*AZi9oB%^?p7iVYjES+tdcn843WsrBu|o~3Txr#X>pk0VANIrDOOk&#ijg#Dqw7Xa
zJFVml^y7gUmXn~dnoJXpiE$-3H~92=bGey9jRr?-{LbrPtI^j*i$X+z`isE^?xT&L
zH<nToMIL-D`#b3Y9Nc6(++XkmMcz+PB>DM~+JPK9z(z3LmDkKR3{oIJe?<w+D=)$p
zNUs?~jF7SuVFjoc-)s=zm9I_j4G-lJW?;vZhZmgf%hGqfgzAyDbP$Rww-JOJb){yY
zToAjS{$?tG*4i8;G5i-$Wycbfa&5ayn!!1IHHeF081ySGZ>15H?tKBR(FBxSDm?8&
z(D2*HM()3LuXwizu>+L{rN10>8ySU26iKIl$r4onpE<Z-^AyMaBnhKNs?ad`Y!S73
zpty%~Y0?GsEmgjw;2^*_sDmXu`UNb?f3q8klt)&%b_+2S3FH&T`*btvDS-@wC=k8G
zEW=-RSjQ|$R!SiC77pUkcht|I#dJ|FDPfuxFsNEH`Att#Q<j^-15R-i+^z>t0kufl
z-{y}KhLX4voMYMGotv2-9V8#(G`cC021lfByaVcl4TkT`AY1*EMH-X?tEE%61r9fB
zydUL0U}xZvI2%ja+;g1<2ioLOctXexOwK&LG*LJ(G^Y{w(}a@R<AAI%r+=1(g1~9#
zw9k4~K=rzU=|aHA!Su_cJ%}U0y2+Oki-Qka?Pd|kLv}h&Dw<Viuz5l&12W}m8Lc|G
zH&?}}pfh4+c!^0`qna9;&M@2fUibo%IqhdlD_DU;AOty&d>e<lz>GsC|5dI%w%NE9
zu_H=OIq6z*R%B{um0ip{K*2+(MR$hwR(qG6A+zGnw{WdMF^eh8L=l&nF2DX}@g7OY
z-oJVL`Wtx6P@*-ClI}BeRI;k)neOctx2p-3oz-wWve8<*X^}`*Xc`Ys@D|A_L0HYm
z8bE0t$85VHO(1#n#m&ZZ;3S(a_h$kLd5r8W4sIk4uLY&J1gARWcb$CiHnk%&tx-ry
zKM~2AdfnXa>27Z+`=f8!!JP4tFv@K%UQhXC_>6*?3uRVJ0|dPcoH<U4Abj$26)GTI
zXgWxusp*)%`||0JOg`{?OFn=$*tLpQ6Z>x^rGq=+mm@6zj-#nZO^CW#$aH`9$pq8X
z>H*ms!fmGF*#r_nvFrl*XUSlnv=uf+cFYzQ-VFT-Ug6>of^Br2WL+|#Y~sDrp+hum
zedTsY%x-!;UJ^{*Wz?w3iJM`gYSKbDr|wlo$ux2+`q?9I9bz{mL-^ZP3>ZZ~5F|RT
z!0j7VCts0ZV<N$f#STD18@P?kf?vk8Gn>xlnwjllAtJvH)XSi0SbxjHV*;E}kz)7t
z!V~2O0cwUx&g=w)3#j=ai$V`t<fIb2;=eT`*dGs@+FLa-))2u8)R&3r{B%WAU5*+X
z!ZuFt|M7x{D!41Tho;n5ezNuV(BMeM#CtL=;t0I5UN86G@{n6Jr;L6tS*d&iI#ACu
zG6y$VWlXZHJUy|Ob%%sTG|J<AX{gC6{dkCCB`n<#Owe(Cww6qgOeeu(#CvfZpY+9q
zR`4`I9(OZcX^zkgo`FnA3!m2uGXhx$My+TknKhwuX^ulV+)LMRI7hwX#rF1AziM^j
z&-G5Tv108qQ4*A$U*B$a)MSwQIop=X4WidM^|aRhv*iZaUE~CtE11#oW_fEnm-@3r
z&d6CIAO<SY5?6Y_8noIyGY1yDyc{LYrSQ5qk=)rzs$IbKP))iCl~#-pIzFyeuvVw=
z9@*~hHl85^vQ%nG#|58ZVau>mXJJ>7&uyR94&A6-S`D1OCYBs23zzqBMtypzqgVd0
zaKM4?35`HR5_hWy35M<d&RWS;^BWirIi74@CZ7bS2sJD{eKXyW?5`H~6waD&B}R-f
z-9P1iPj*{D^oT%ITK~ucLA9%(v^37t0n8}$%rI-o*Az6|3w77+S`P7^NNG|fXekp}
z0y{h4G~INXnS*vRGHyGL+0Lq+cyp^?nvuC{-reeyYy;T{v+=6Gx#hIT31g`p2N=C1
zRZ9zFjo6#>B}%Km0<XATAV($)lA~XbM#rb8=f|fnMrX$-!;|6T*TeJq$>^tN+kgAC
zd;8{3%zTIH5I1nw^9;^G<a^-xGfa0sa+y4?G{GXSz>^s=7{mnmGb@lD#;<_)$a#`c
z&01b+$_%XDx%kX#eAB3syD$s;$SD&^C>F4L4rgbK;N7z`MzrWo=jOHR&6MUlgB!!e
z#EXO6Ejf!8)Tp*6_{t_>2rCwT@(ksY_~sc^XZR*$aznO7sldjF2u4yw{28>aHPb{k
z#7v46^YEXDgV?K5X2Qlg3Mj=5G5n{k%n!E)d@UCT?CQhRser;~N}`JMy}Uec8CyUV
z#XV>93tBXCQ&?mNf~}IWBl%+10y+_rOkg=~$^Cn!S_%r*D0W5ZyrV)mP|t~A-j?K8
z+MR?^8ou*(Oq%SQuWYdaGwmt(_fuqcQ38m{rOvpN0-838Vv=UB7E>wt(v_asI_?!i
zOzaCs&){nl!0y7LL_XxZimTyrWr&7g$8~v5L+Z9udT{V4A07uM;zF)iVvQz-)&b;6
zVzvgT6U+isGF^6Fme4dy9)97Q!(uV46sFx2CCU?XPr50@^{N4<gX&77(V4V3hS(a4
zp2R}AMlk}}(xvVTl<<URweNNZXww|-q%=Crp%l4=sulKzPyuEmT<37-1G}zcuImB&
zr~oi&d+;V4m+|3qWhQ_Kqh`)WnqSqiU{sgbn=<zh*Cs)2<Yo4r&ftpVJuS9lwr=y(
zL2C@6hx=qHJB1Q5XF=l_=_%rlDI+kD@NC;$FH(SR@>ufBs$MKEuC!7VHq0FhjPx)E
z6H@k&JGtnQ`OP6^j7jn<R!(IC84w90&2Cxu{Bm)X;ihm#`J$S)(g~4ZKAY+6>C9yd
z@=OUX)(ZuT+aIoEb&zrXsw|ZG5Hr`DA{Bu<_UIPnkt?FHl?aywi5akMUlDv;j>oP$
z>2vgjRzb%yx{+OrJHZWN+wv4Mr5X=MBkR4Yr#8q~{8Y;<(yF9}OUvd2Vt&8<{w5*}
zfaXTFNIR!<q&0bhkrTX=Ej01%$sQuf0$ymQwe^B@37TdidzxGA%;H+OQXT@9{OjNu
zVPHKuSR$4evvPZkT-TMJDpkex15+BXwqD0h&53}K%7b;_D=iXDuWh$kZ8r^LTnyDO
z<d}xNsHKf7y+{lOmJYiE?rhBdQ~GRnp&C8)ad1y>AfMe&fm*jnfQqdJ;v-cZ%p=n_
zzy{(<{K#W%!;*5yNgql6p-e^wNeeT#hxPhY1xTIk9Fq_7;D`nZ5S_*P+8TZZ=HnEl
z+wYbxXM1GHsLjOMzV{^iqQ8Yv0hLh7JY2fe^y;p+@8G!1RJ6VT3*~87gE`Yj#646+
zKtPbU=KB0Xgv}!EtM+Opd&6gZmc`QfSDDX<Q&Ydt0EtMGDOR5zmB*1cW^h!`QR-z8
zXC}W>m9l-HT@TX?5t0@FeQ$)6j(SH|K(#!6TwIvL0}ii3F?D>A&x;$%U@}$UU9?H)
zMk_&L?&Q|6h2?9qF+PIhh9YpeowdV3jz`Aml5?6cE}gSMLgy;D;HnJfc;w<Gh0^uy
zdUG}HxWeVbt?ZM()1ATENL!BF)6*E`BvA<cYp!I+<J`3mm4d{0ffA}W8$Xh&IM^9g
z%D#Mk8*EGIn&@8rZGu&^vwL+shlq?eXIsJ%3r<`R<CCiMP*qazrDvAbk&5T70P31p
z{ng#gcK034pBe(&w@NyK2rt$Bfrqp}ze4qNU>A~H(J2UIU<kqCVho|uD+IXg1|L@2
z`xc%6pY>oNa1=n#LGyZ2jD!TsJ4&#|7|3zGh8~(Zi+4$7k(>1N=ou=IZ7W-1t6leq
zR>OlHS=pu&dR<G`>sakBDE)nG0+|lXOJiV)TD})*(QAaN=FjVyj{Tw<xP8xdJ+1IF
zJ}X1@Y8O|iorgbG>C_d*Z}!MGwc@HYsj)IW?c!uN<xuxGBPIHs_50>n1|4J;GUm*}
z;}!%`7BFoj!;>!`KYd<4zW>ALKkm<V%8$talz`rW^ub%_3J89-L$%&5$`fs4+mJ(&
z&e(Q=VUYNy5htq6QaM9O#7uT5S_R?LZ~QAN=GdjCnfQ-@V6-$UMC1`3xk0^%`>8?+
za~QylPVaW6rw^_HkZghgf-Oi4hH`_9%-w0&6v;u7Cb5@ME}(ic=Ydvu=Id`;rD|B3
z34AM4L+l{to}W(s?einp<w9TJO6kQEWi~O$**yfmm|<*aclI&sR^3T&Q1Z|f6l-%t
zUtmOwtz{6cnlzin=vA^=x6JIig6j>`oQs`vO>p6G2!~A}hAGn87PSgw(?Rce7Xe2m
z`^J@q$aNC~$jqp4B&jxE2dGEdSJ9wsWfwZ4J93@`OgF?Ht~>!?ZixJi6jf7QTI5iP
zwQ!uPKzg7))4hm`!Wt4WbWU0VQrn&==PH2%3HJ}U5zLn@n2Qc=;{{$j{0EE|>>kDo
z8?l8gR0f&&6orBK?$4Ed!a@<+Ccj3ix0uty22okNdf>&>*}2s3v*%}6IPJxQs>Pdt
z+Tn47qhx|{E@jx>(j}V$pvF+12d%ZPK<XSGA@`x1p}emQOPI3WKt4(tB?xoHa{_!3
zBh58z9pkS0ziwy{Xs%PqSx3A0@C?^@NXp5^A}g9bEAg-{<9g}=@teuV^kFuJ0}EqU
z7s|@+oTwO2`1aN0y_hq=^j7nODV5dz-Y`8qo;64rjZ+nAmTtcM_&dbwMFZGe^J`G{
z2k39{KTQueB*o2${a2%~k`#d%NtwF{&OeA?+r5foaKv+v`0R-VuAIwH#+=of>_75X
z*0Cjg6N795rVrM>FtM{=CP*-K=eYza9$YyR$-&b#oms#YEbj?C{$8pY*ub=b@;Vqs
zB@$w>Ug*X<7rNq#PZN9t0dkM?0VVU;JzuH^-MCiwbJRlEqCV5R$35z&zj^x!&bG0>
zezZK%Q6Iyj8fKOiQjJx|7MfQRvJm*B26WGO6@1(0=e$LghpmHujweNM)t_bY=6PVc
z(9y_NdlcGE+3c3vU63KnO6lOW0mY{O=p7P^1Y3}VpC>x%n}pLzXOnzfsMyE8+?8%F
zE-<$R9xYIU<%dR9#KQPurebhS2mq<KRteD~^i+2%2_sdy)Up<g6GLN7$aYRj4eDjz
z*D6yEg4bK8ob8}tc=D)>|L$l4`#bP7+fXFQ);mZd>#v7rn^M({>Ie0=7m9DIjNqHR
z<1Rx^Gx0&919cZo9NVcNmFYjd$uYbJs(&J<g<Z6g&2<lUFro(9ij)eZrzOHlJ!Q`4
zIbL4f4st|BgA(*hNP*Zzax9_4y%yZFjd>}GxY9yaj>2GLuwM*0H7mv&_V=-YdAdwi
z^hV+b5Trpms}-vpT7V?SRjnF=hIlH@AL_Dt5o?%UDb&kGVBgg|CW|!pNSs_<=|wP7
z^6aD6@eU$Sq$Oj0#Mt@QjHJRpF$`MD_@7OL@A}k9<Ixa(qxuZTmA{qzEl(1T{JI->
zR4K1%=YrqkzYhMEQfjKnZgv}NLM{tw=HxFG+>8Oa>L+W1flcPaY5NUt`-dZCEuhdN
zWj(r(k9{&o_Q{)`ijUQVI(K0tyGk%shjBZ)xK64yF-5Gm$4<a)YYhjs@n*`*g?HPu
z^=z4Ap```r_O<l}{y={QpMN;XeTBdD#l+9&wrXt1iZk?-Bd``Gxd*y&u4J94O_ReK
z6JEDVMz?@A3^I6g)W+HEClhldE?e4Wgs46hC(v<VJi=9}XVp0$=dTi5CLRMcL8-lM
zPZW}|IFJOjQGrjOD+l>|vA>ouhudzBU5CRPxw8jHUn^H@YEpi{uLnc-^a8_$Q{VE)
zPVvi(tL@fub5T7E?bYoD)^FIO5qLUg=sq`|6ECTW+g)(9e0uvoANQZ(5n`0m*sRJ7
zpmQZ#(-+W$+{2+V&qh|jBG`Q+e;la$x3>%z%aKYwFnvL&QGqEr{=@59)G$qO-q)li
zEYw&8QB;(KQ&<y{G^q`K0ZHvy$q3H3J!t|*2SpE3VN5-kql@UHO`j)*a}I1oxkJ0z
zY=<6HO9q*(;WHJE6_hOEphL6;O~%cO7nl|3-8@DO<{KQq%$-VliYuPSqf_GpEFB@w
zt>e)b*{s9@tRZ5feheI_nIJAZ)-eFYE05=B5Zg9#tuqHZuY^>#XxTzegXg~XHV4lM
z1d9L@|FA7xRiI+0Br|Exu@}~N7bD3Pq~QD)a{bMh8dJCou4l;NlfTU_)x!lz8X~&_
zRXQjf1e||w3NY+N>|o{t+0wf0W96Y3NEFB0)qe~juM8o%<l3{`zw|-wsX-bfJ_4KF
zlTC{-Op*=ejwI-S$e(~(iFhJa#wl{6rLW=Sd*<wHj6@o3@hi_98N;%8V@|S21#4_W
z2dvk&THPEOB$$booQ78ciSAfbXNfT-kj6;0c1lPC6}na$L6`{$f=H`z0PGl8L7fc+
zB1)}6<f&0nJWmC$Cyg^k@{V;F@^5{2n%j0aJw&Wr2sG&^_7kQB)D6xWaA}8bsxzk;
z$hLSf)zX(Zjj6OK0-M=dCRhslS`Z%69pN391f9VEyBDMzf=E|$$cq>>&v*`7DRl$7
zNg2;`u7#uxh0~8^GaeoAgf2SduXGHKG!5xe->G?U^_sgH##M$ppYMlRTnXM;7N9;?
zFLUX!UJj`5l3&W4J}JK1E%wVCSJXitMCum~SP4T~W<;ESFfppTnH^}Pv%t(jyFsI&
z&!a5F(9Ep%zk}NQ&4(}VKevW-s8=;Em@rovbz6t81M|vws*-^g!7nr-Ulr+P1GmV!
z>KKajIb~)E-oSFa4B?M)JN8!~y*r4bH0AxYQClV-Rc4cHHEzs07X<BFdQ|ve({UXZ
z{$7212IeU-ZoR#OH6H;=owLy|DFTD-<_#rS_Y_PVSxA1~8cG>Pn2mIPcUnb{b0Hy6
zFiVf0eF(uznp9Q6w1}hu49hh*H})}qx*$RpUY}*#4L%SUBmCYub%Eu{AddF%50~z2
zgHpTcn~QZWfcj!XcV@jlSOVTb>dp}t8E9e37k3n94#wbU$U#ENF&n@mCv=#Re=5et
z0=y!(lCvRWOY=rE+8lPE;zE<BI2xvK0>#@HXT<twdW#dFLMqTyUr*rj9#ItF=nzWY
zb^7IVDY-ypYgt1$>#S`S{)N}fRRQ)MKHFC}U>1YGP3T7EL@MR6sem?xAW*qB1iZz4
zxsyWyrHfO(z&w;H+k+AMx`Upo&o<k`=!tZGfT?@(q2}4#QI44dbp~lAl(LTYP1gpF
zl6KzBMPZpgmU_juzQ<<IZd`RD)xC@c)UlfNpg27Z;^*hX!xWBpbC@Sj2l@B@w9PlC
z5*L{oK~e1a`j7{1$aDjfX5bo?xbE43_WHa9B_&830*(w5bs(mURIl5iIOj<|O0!9p
zop7d0cKUZ%%AFdRJjz>wQFTWb9FNMOi~?`OG@|8^xKP`}uiyV^L~qlh^0H)2s&;4<
zlzgQRp}M|!EtC`r1!jA$yQCOO=Xx8U38y>2{`apxeWq?b5l_y6bhh~6RF0Z+-?U<T
zILWi1jnu$_TtWgG?Qa*`lXlIv8kRSRGcJz73bWziluab3N!Brw3HBjaz5PDC7!3E^
zBIh0#ag`9tJh+lJAz!KocPcY(oYV;^*o?3xfm}HustWIn1D0b!d^hvpa+|8T<dd$w
zAf8#P!of!K-zwh1JM!cyBDpF3-mW347j7w=2ka>edoW)XHKfn*0te8!JJ~CVxzlpd
zU<+v6f|74%_qR84fhGPbM-s=*l~(!Xa+?e?ryR(JQYwXIvPF|Uk1)j&c!Vt%&G!X$
zz9u6%-$Hi@v7_{=j7L`;GRnl6<n>n4r6$3)6dby9v>89kJmN%>y?=eT$xyB>T0@Dn
zS|A#m|1d|!fp)zx8SJBMXYdH-{uP`cTH~`qcAY_*riYx3Pdo(X94i99RD>VdltdU9
zmm`BT8TP4kKM<o(Mgq1#)!dOmHIs;QC^Woyoe3TRI@Uk421QA#%1%zG3@d@vQ2dis
z=P&yh@;!EvkQ^*0(<CZ5I<|nt_)H~&dVoFn3l@fhw_<@tizt=zBm$L+6r5qtrQI6A
zR#BLQCkJF4>LACjSV<yXAQ6Ev>CBM6+GGQW4^|9(f@!RxX2?syR5T+iV#>myb}6*T
zJ#NvX?aI@J>Y-B49IhGwve*L3Y@M_~$CWor5K*k`YAqY5v#!RGcua|3XvA^YW!CqU
zKgCVbE4bCJdn8??81PO6_+^V6%$K*fn>k2;<PS_2bWO>zOc`UfL(LjAauGkS^g_Wy
zf=4MaOdPOS>Nji<4wC{o)N^qzDJHdFp>I^QtLNwWlE?@$lpoFz0y2}}zJw&5+~^U2
z=GrtUO`UcI6+nlw1Xb>5hAjG5LBm9cD}H#vmy6((V7+;}xB}a)tnHy=r|J}3$?Vk{
z<=J;c`{x6x*@^nFfbHO;(V*%%%IX=9?hdQLO<H6hKPVqy7ri>-0#3#h2es(Og$RX`
zctFQWCsKNoA5Rc_17w8R%3}1CX_%KMRv&%P2eJ{mf<99j;e(s73sP&s7;>&5l^}xX
zZf`Iur0~D_@cwad2nN4Lmz0cM?oU18oVA5K8x4Z=1w@9HjXMYzEH!Xx6eWct)k`Rf
zl3-dt#=Xq%ZlH-nKuY@Ix0$XLn4lXuU!Y&<w<l6*H~j)eMD<B3aB1!TePE5q?8Iv;
z(?`#XFEC*t<BIC#RL}l}-w~R0-Nxd6>ScO&PdU;ZLw5wK3#evN54_*r+WMe)X$*7l
z8+)CQ<z@n=h%^Lgy-zL6cWjbuu5H0J%c57|z2yfl(VV(-9#uf(m(nW4g@_JML<LmQ
z1EMX$w}5($NNLhC@TFH0VQMTm)Ju;DR)q&1%pvuiEue02SxR28wNEUzzBpzaI&jW*
z-KNu<(#yRU{!A-XWVHlqiT8n_3XVUD4$JR1F7!$prgQk_MHJRS`y}Jt$MX?+V}u2j
zkqwAH(EUdKU5)7%dU_T>r&qhlun<Uj4QW$^68yn6b>8L>5LbGDkfD%JlfKJ!lU;bV
zxRQ|A=b9o?y+E<FbsycXlLdDvWL8D)<WhR<RdBjs-DTMj4zC^Uo-OFJ{cmqhkWOiM
zsq~V~>-Q+!@%iJ2cgSMjoI>OKLfJ6)*RS9I@b1w?ew%Yw*7Q0hC78w)r`Z*Lke%Nl
zw?P$P+1tV9ky;lVaL_xGB-_utFxkh$b7U6{>g5Q(UhT*P!sic9#W9K9Y@s2RXPQM5
zkz5PB5ow(MgNOr-ph9_2g|R0sx@k^xtV<gaA}v2xSrXy)Asy18*DgW&T-ywGwD=a1
z*NWxP0~MLUfmWYT6mhv88Eb9A%5IvjH3PA~NF&_$#PcX9FRpFfHRfgmbBPmTUFdFk
zSzh*M#KLwgAu0Gwp3cEq(F4-Z71}Sb)u@s)+cCKfW-jtT_Q3OOxW}Grsp859r=9h4
zI-b&>#&l+e!1k<`#d&U%k5KP=vuYX>OvB^KQs_$#{!mSBaOEV5nv&<z4*Bu}z5ZRt
ze_S(PWuU%mU9RsYtUBIS#&~mHP~*uVg%~nWE_76fmH;ujwPT_>CB2{Pr4uD9rT+xe
z7m7G8AW_0r49ek=q~RQC95&qUydGtQDM-hknR<6W7!197Ew|P7dORAP?&ojczy0(_
z6}E}GwYgatm!#1}K5*rM_7w?JK+^aITw~Tkc}YUwLMm&-_Dza4N_L2NSR0(5<x|p!
z4*^o=to6Xg_>Y(ePg>T&kbm*4&2kNth|F8O6e`q9J_ipDPh3L@dQdpU#KBVrB;-~N
z+c;gg){@Fr1uk)^x1{X}9RiAfEq;r?CTzsy_4H^>i4`%=%2?+tdQ?Rac{<&o$$S6!
z_{09MtYD+`p!Cwi1`~Sh2k$<-{{xcveo~^|0aTUc2DezVLN*eHBtoKrig<^W+5I`v
zr6wU}f5g!Rag#Kf3=9n{5OQdru@;uz0yUD95w<4WrO@D;t11LARy_Un@!iJa*%@;t
zP4(;^RnSs?9N(P^d2e^|N#2eT@!FZRVs86897+ud$t<O-Q*JHeUKJO`(!(b*>Ubh9
zHE4#|3;9-dV;NZX52(goQbK~wA6p@H(3NtAnBsTXQmIxseotCCen+60np!g&x)@6K
zTn8;&6q@bUwLHlZ=j=#-AbtjFI<uA)HZ9ASiT6Q6!a1qWgeSY|VXhP8u_{dyU1#^}
zx!8=e;40b)Q;4eWO)9*s;CgK0DQMHnM+&dB6d*vMV;|j!<#vtxNE&yWK=VL#4X0n|
z?#M#EftBva3yIBsdVKR0%8fsM`m}!h_~YA8bmISt{NU`T&-1sB?|%4d@o9_Q`S|*G
z?;i2HdHv>(@!N`<39$Y0yUpVtaIZi2t1X=Co)5}bLT0VrI_SJMb!WsOf?<!UaSY0V
z;3AI%7kMbpzZ!G~Gtg*^C349dG6<#|k__#9I0;vq<^2@ZA&~oz#sxd%BhDM;w@rbe
zT+is8y)S<`Kz*|3&}|&W6H=_n;FnOS1FbEh<+9Y27ke0M3j8g#=-LMETu>TpgQZ~k
z7P=aaxA(|LZ(qS<p}>xz8?BR5RGi`cTcv;s4~3o<xeC^<Qb1K8buML3SWj1P-+%cu
zIy(>ho@COZ-4GcDU1%n*=<7ureo-T-Y}Vcny&kQgXN5|Vx;}5yGc|2)=sqAc_r(4i
zxoLl8L5XB3bscdb311pdUAAZxnOopYS<Hhmr?CF~!`|0WBj7XZIz@W!lkV3~-}RLL
zwN}?0%owa<?q@E7)qZDZg^r&jG_f(6q5|<{Z|?OtY(bKcf$7HK-$FX$LrCic6xxwi
z!d8Ny=vsAv14!Lbl6D9s>jD+OmV-`<)`}jEJsGeD^jjeNgpJ-H5s`LSc4$4vbLW#J
zCYD@wfHc7Bj6hTt&IqWituW;|&WPB~^gZMuivLqYh)=J*(hqgkn+)?qx~%tW4O4e*
z*yPr?g5RI*)vC#nS!a5b@;Vtkt3JwOM(|ZRyL=3kMi~+*q@{qR3)o>+^SW6tq55r$
zIYoG#O?5injhE|0_vn)n%x0jKv**4+SXl$|?b8{Hbhw)>Sv$<%sVf;gC|EdBl+S<$
z9T5aK%?z4#`#~SU;sV-HbRD`{G<UN0(Si0892MYx&%uQ!8<kzqMx~FoL!nAbnduGk
zpqw6Z!G&p=+Ni=O+*_ES_Y@$!TYDcoNy_ncLWadtWp#j>FQP5<EztZxH+q613iQ7=
zJqsg|dDFM$(N-LL9T@tPnwOe~qI(-87Z|af;Mr@8PYkJX^M3x0y2;Fo$K&Yi=@6oK
zS;7$CjcEZsWSYd3JU#?x?`oK)D&&kI3_G(;cmm3H1xkZ$|2>XQm%iL}IJN5mLV!4^
zA!FAc-G=HGEt)0Q-lSwwc-8In(uZ%FNN8?O`!qKNRL`U1JL*|j2K!+vgS|^eBMC;q
zTw$IHITSe)OPs19dV}H2G_;v^aF%Lneo`BpC~4$<-ELljQN{xYM<-k=9u?5xNIiqU
zD;ouhA}Ug#18vWpY5c${a<xc2k-Kq=BHs`l@W<Z6*W|4z?Q}~c`?HS3yh)k@kO`%j
zHZKiD+92QOPA@`)zl^&t;UT+ydDfef*&zA~p@nNRTn8UlM4)GsvuBV8V4@yxkq3xe
zt|?G^Ak{oG>1?x@B0pVGR}kc@XxAHPLF6bvilL0%y#fJ6*exlG=mdflF>^eKJr9j#
z%VNwY*AISv)bGNtaRR0Q%(*0_vc;HsFK=!<nOW<L<i>NX)qIok=<$uk)@a*TDv)Lo
zY0R%T*q(}2I{xW`L4&r%BcX+qCspR&9(Z06XYO5X8&{gIj6_)HC$&u@aE9%=f4rxq
zZQ?G=wTO*&aZ&g+)7f(TJ&1PVH548n#eE?2BZEujSb)<4r=ZpTaj?EB9q%rhU<ca1
zpmb%Qlwyr2@bnszs~#EInA(b1g}*P6U-;f1Oa-*m+P3yXXUN@E<1%>}pgyk)LzI!q
zL#9Vpl@1_>rBOsqq1i2?U|8915Z~MdX(6@sESZ>jdBRnJoXr*`#HPr<2;U+E^e&L8
z0|sh%BUtI>veC|bxTWAxBk)h$5GvQgO%PHMU=R_sFY2Z=hz;|7rgW?6O7J9~n<7@+
z9`eZ49CbKYh<;KRK^M5vWlNiqsr3RVoN&1iOf-t$gfwVZX>6=xL~goDBJR$x=La|k
zoun1eHY2?CfLFlTF-n$`z<3UA?ZgtO(UFRhw7^LyNA>VRW1|WhW#*^KiM793Ee32+
z`l#zUE?tiYbXwfdC=K1@ySMKjovc(*JFLKt!8iwM#HH0i11fS;!e)R)-*0cmEL*@x
zH!=oY9=6j@55l=~bHBjtD73iVEN(Z8-S<cFgPdyq{Tu9k<y$8%!<SF{>B+3g=u|qc
zR9TagI0bF8CJtW_ER8ua==q_537CIZ4bztx4aL)-)rW!__R`*h0(A$QOzionk=1YV
zad$ERb%Rlo`(1%IYNCbMdKBxUw4e|%h#`N6h!NfNB6%ZWRS|p3l5MuBM^Zv@%-bQ3
zs%_KnGoFEZ6kNto(O|r3z>#cjk??#*d>rA_$U0-=pa%I=>4h7m3GbFjic#=1WJMR-
z@dSl?k}nev7R^zHNZ~!lI?*9I{$i}j&}!ZnaQJkcf?p5Mo^6n41H=J;It+aU@-JT^
ziDni5T6|&$77XB;o;tAl7Pera*cLqNVs7HX;7D8^gmp|R{#PiXZ4xO2YX8brM87cY
zJW)vo^IVvdA<*LvtQ)Hx{gN%W18Ns9_n!y9d~VDPcoSxqgew_@e`q}^qa{~}qrbHt
z13AsZPn(Ckd9dL8ExN_?xxqNb%jOPrknTi2A{;RXVRnw{b34AnTHyd`@-+dNvF&OC
ztH>DjFj_mgr-N=R7}t}7jH?u$!8341!7h{~K$9*l2j$5(u|ISD1!0&oF_=Iv*<s-8
z^$JQ_;w9K=ii@z>q@~N~0Ub?oh$Asob*1^<?_X+K4+kUk!j;&R>o|K)?fK+ScYlWV
zT=r6WFaA`w`|dQs%KakE8P-D|H7-;Cq%0J23(yz^^~f#%hPV>kB^t;w;Lo=R-qBgD
z{PfYHepD~>T!NcnJ4rzWN^AWsa;c2=_?MXqpt>XbLYl$>G4yTo%G#uYk4!;0!uL0?
zZ}vZa_~B7tIBeJnj(`g2H{7dGO@1N2!sD^B)Dri`H{<2)l@);SV4A5mYYzZhm#T#l
z!+gUO1m!>vJMEo>d6N9N(u@&(DQ_Zd-TVV_!Kn31TT#;%w*3@*ZQQ$+#EAO_zHY;x
z@pTKh=0BLzuoX-STLFy%KD2vyFQUZ48dVmkbUHmr+8a`LhCiguU4%wjyWYcY+*fy#
zLvim0QfH@J_np$g1wb9;3_U82vF@5+QhGX+6YD9jk_p5F-+t%v1k>w{?|^Kl0!xtX
zTI8w+Zr^u}92BtBPw&>t*{l8Vc;$?=l5FDGK><$8eOenAmsyzzd?X!TS)J%EhvG)C
zK&OY$E1rXVCSctXBa(Q{F5D)!9XQ9-8P{Ri_Oc~ngA2Y@L?pp{k#5%vUL~`-Jw>F%
zt3kUVr_R8^JNf>%vkkJS7QAfY7&BOpHj-tkBy;$8O%BdBWU$0+m3neh<CLKMkWiTQ
zs_Qe*KL}?5I0181=<1$&pvB1#GO8SLU98RFW#JWC=wYKN<(TsmiyM>z9o4pUX~*9r
z<P~i~1WlLwZ@cDA9HsD7%njvue4}M#(UHzPG!Vp3Ol9I(X--Pz(s`{WD^71u!d%5y
zCoM|&j<lefVW&EwLBMx-aTf?{PzNFR49;90Cb0kFq(MP6LzjfoHB8UUV&)j3M1`Em
zOHB{5H*cnEIsz(1R_SQkG)@YY^jvH+WplH=oAuWk7q>?3vmau(!WMO}XrRL6LS|?U
zTMGe$R03<{hUFHQ<sMCR3gi*St_!5zVI+f#P%b95p?MBaa&q3x$V2l_+?G^3mK6os
zOMG9|F^|QZTHGVgFEoRuQon(BXOib)nKMYwNi+vWEs!^mHPpUvT`bQseY1IS6$hUV
z8zOr02lWfRJ*&>Q6GV~)8(~bh1ZrV)qvT99N3<Q$<q7}wH|xy+taa^b?jv%~NvPHJ
zcsZ7lrH5LkdHwMRC_3qi@WbQp#iP}&)5qVJO787l9%Aydv;4Wq(=NE65chgr_FUT2
zF=ki_^$Noah8-4lvlwF8!MSmI<3e*MG6EVSlEJx}aMRT&)!#?UNf0m!d<!dOaOO2N
zaR*KCdT5Xr%CW?VT!F;y;vsCOCWLjIEhf#ULne@^uZzZETLqf}0buq-c}7x7b3%4e
z5wZ*C85tkfD3RpmVGz48H))FaY|rDFV%RLDX_D&rjZLYJsz^HLHj5wSWLL?SIBBlC
zB296YCO-)lIcaoL{x@szdnCp<t(${ifa}*hh+SOkbNW?!otl<d5IzlyMJ69P6>6NQ
zVOj&xUT~p^*>cw-{nks(W`HNHug0KSZbL}d>XSD4+UbF^ar!556(M|p^moUBV>N>_
zI>hNc>h)AFpt>ajr=oTWVyG-CfWcH&P6fYIRSttd>Fn7~`D-EX+}(f@|2;-u48Pat
zi}p(hp+2X~@V)yMIpljj70Z#q8h30pZD4v^{>=W3F1lI7ag3-Hi~z2pNv%LuH1aus
zs>|<h`;*i6#Gf(`GHLkD_eC!LvQf*LDE<seN93oc2?=Inoa9S=aVj;`^SK$O;X)SU
z`;?>+PV8=Ofw3j)S13UhJEzd8oWLzRDOG}G!D95U1Mg3z0w)A2EaULJy=`9Xz@HVW
zKUcXj3X0sjebYhBZ0hEp*Dx(}vpU^l;{n5NrenlEi08ryrbK&GzM_;1M4QH9-%9{2
z1@{h1i)5vx;#f9TIF_U+J7ts=B8?Ib(Je;F34jP?Ei5KzFFI({@vx92rxUl$Sy{}G
z6T4;CC?)DFEF_)=HUx6B(}$cL@2Y4NMuF2r1rOp83(}0j36BjF^-;Z1qCVGh5&b}Q
zJN?K_BGyowposKArJrt-Ud)qAX*C$?<pOwQdgivA-`+1~W=74Ix>M(qadIP%R*I_(
z_uPn4?$Bh;vZR{=*P#Z4y2KBwq9s2kB49hQ${Ixh)%vCISCo%Wxi4MCOFqPoYdHb$
z8b-L`E_aJ0X#3L|?hWg)(+IoJSj2Rh;DB$gt^^n5!um-)=cgEdhZxfV=q}h=cQno1
z%C&}SiDq-V9Xz9}7pPcW5E5I^lDT?FcVu=gm<=->P=xPK+>+s%E#M|CBo83bVEDk=
zk)-gF_!w1ntcXrqq!dz_{s)Pc^fWDq8{BPPQ;dakcm0lv8K}nu<1&&z8)mTGVC!MW
z`2;8F%8iA}Q+~i@tKn9Xz@-|g@H7HhTtIL*KR!D{bl70@teGpce*oWa{gBq^+L)L7
z!asQpgCN7X?}zHa^h@P&WeeVF^u?Cmyh!1>eKLC|q4tW9jG=v{XOq36)o55~3M!-^
zo1kiotE=ov@R&-ddKf84%9y6NXj9)rAGlFmR7gUN$xFxzRWmS78OXU>#;8mUm2Mv?
zVwq;1+8b@Wgdi!OX3z5ytUwQticzY2q(_N~<pgVQf&$*bd=qL7lf+!^X``|RonU&2
z==_*uVh5!ULuD%?YY$krC36>lFn4I>Ox%VRpTn<lV{U!8*@6{d8=k3JL$d%j0Y5iF
z3;P|;KWx@w@*A0kbb0#_1}{n}nbiQh2I2!fc<>88b%i4jaJqEDuuIqE;Kr6GMzs;8
z3RpmsvY<3acBu&4ND&I4co&LL81%#>Bw+d;B<&ZXDFU#qy-P4nnDgCS(0MbNtc#*l
zcrMtFGNA<@<*sclpsm<)yuIFA$mRQo&Dz=j+@Jya8<AE82MS(0efyW;F$%R%B{6PV
z&G`;!D_|nq%*V5>?GT>GQV?50c3Egax&pDOr-F_h<D}^}0bH%buY!?(RT<^;HwmO~
zB6{$UU(Qkz5sM09UL3?S6%PA@j5EP3)g5fF1yT3NjC5(AnhcJkkrM(^f(m6$w2>LO
zKn@#a`G7Op4JjQI9r=uURZST`OoJO|d_s3eF3;ou6_X?ep0z}FgQg1h%#GE9jk*gq
zL5Px=Pu>fWCpK%ObL=^U;hB-3n)&LRZJU7Bn&0#>J+rBkplG?c0p)L-qT0~3m~%6?
zL=m01(%i%$fWoqI2-qUzvVC3x^_czJJ1fETvQSrnk)F~^2<9c}^Khk?73G@Y=C-(>
zwQ4wT?rt*Aili7jXmqwHLxBhrVe}2GH3*&(Q3n)1!(+qxL03fE4H98vALzvM-+Ft(
z(58W3!hX3$Q78=3ytBQ;jvCcFW42L4DYpyx3$qQp2r`&77Zo8i%?0t>eY1u>b}}j(
zV}MLjL}g3{xvoHR>sfXhk)S@$o`}seZ%5kg*1hp<k%T*S(?g`yMn#qpGvy#;jZ5o(
zLoJZHYtkc~XIpF60_p}X1#`P^5W7}?QwdR5@sDQQD4Y&Rn{a>A3~xR9ji(eR1l&k-
zy_;YW`R`hUwAH3Hv{VVmlr+5>d!7Wl5L8FKlLe<d3PJZNACD|sUkv`lkAXH=UqDTv
z)zz~M;nF=fQ0_UiVJA>nu>DG-a9Kh5d$ePq3QIg4wT#iI-XQ9lmL)SkhI@VCf8Tb-
zN9RL&nO<jn^groy(ntI0f%dZl?Ux7IUmR#3G7i!wmukH=cyPxXPcF~`YU1q_pwVF0
zpoj(9tX@@+-^>`62;PO-DrUxLB!#kbNh8fYCw?-8Y(L#y*>;H}WfeqE(yCrhu(u+~
zXRNc!gdmM){OKni#nHM4o_U@-&^iJfqy6|l5vQlyJ3)GWqInU#O}kQ_qkV6$G;2!c
zN&~PTu+&j&e<fvP8P2EuKAyjzdncBqRL;Hd`z+&0VaV1!=F#ub%zmM@p?ng~eS1V1
zz^uEty7os?KbDIpt)Uq4kD-nwB4RP$mu-Ht3)IUL)d*N`VKO|Y0%;nEN3>~~f+St(
zX@<ecII#Hbs79_HxTc-vFdTnyV7GtK2ommi1QH8jwXV|mitIN3Q=yA|zTrVndRteF
zzGoWaJuM!ezN_RK#}n8ZAr{XUuUKHhG>_LUNuppJxv*_;cP|{s$);vaBhM_70SndE
zWSDo2DtJpogiwWm%bwYtlweIRNeysH$5$LLx^M(oqLeBWnJnN%7b<+{>91d$9-p6`
zpPpTw4o9cwXQz)}pNvkI&VAE*z_7fuO68I14%~jaS`riCyRkj2A_A$dpAUl2p4lMp
z2kseq3sbp*q(P&^YT+tWv|bOolRK0`DxEq;qJYTO?w<^OL#KLrv5b9SEIzlx@!`eq
z1KW<7?vMj!hw^eY??9pgla<4?R*B7l;gxZBavV;KUHGUccVeSUmQgL4?n94_r_TeV
zhl_~0t9B&cPnVjRc>T3I>#Ot?{9Drq+5p`Z&jqb0OU9_#3n_(c&OIG3;nz@aBIEMR
ztw|{!z*LfsO@5)bb&i(dNj_U5(||LxW+@0J#Q9lbBXizjF>L<aiTEVaTNz7Zl_%^J
zU#W0dvo@4>^Zp4)vItjJF^c?{jxjmKbZa#$SQQdhcvo{D{mLpeM|>sbh&uM`n{@-8
zFlH<=G+DDg08A7oWQ9PcF`RA(`5H_<Q?{x(@PsQ=8tic=<+Mayfmk#mq6(QdkhCpK
zjD!Yz#4)H6i~e>I*)#KKp~3r5P|%L2@nm30>~szH4OmND@NrRy#|ivv!-{V&5u?(U
z(Zacz3lZTzl^cHcd@VD8)j`kZ^PyN!`UL8vMA4`15hI}aLxG_A0+C!*zkRTwPjpct
zjO`Zoc03TlCQuF9ltx=rvV>a;bS(%YX?BRLvf{%y*XU!Glk_M#I;=XI#pG@`+uuWy
zoGefTmZ^9}T-{-@tpTiInlr6Tv7d?=u0ZOX5D)u__=qsz*|H!9S9QBEGVTdUZM-3C
zSR+h-AH9+h<qwbu;6RQ*Hu*l^z}0sU?T83Ql1Hf=iCT!}Ff~P0%sV$~NYwnt@nh0;
zI)w;AFysMn?0(Z-A)AE}fTS%p@`@a$_2-H5C73?TXry+}DAE@Dm4;}i3k-&beUN#+
zbUQpVqdnZjXE)9Fi2t-}*jvE9c-w=Q>`q3dzVT*Y9<U!DWtlS}Nd$ki2|){(9~7+f
zK=Tk+`f{1{n+HjpAa*GUJC6#gy?F=dgM}TEQb_nA?<d`v=}9P@Kiuse=F*g;E4={o
z2CD|xIr==e&GjvyMx0UxA=fRUkU&xwvl(l)-;6ikpNz2QD&-bZ6ocA9Cdjs!mLo-L
zy4z5DDU*0ZPY0dob~X6Rhj*_(zkT;OIQnm&9{=*+LIp>zt53HT`zhk`!R}GDj|UgA
zvpf@x9fFf3e;AY0Zq=M=nIiR$n?loNv22*swy%e+rvUn}WF2T$Fp0u3px!GTux{e}
zO%6i>T|1ZaWgek>S%*`9x>OHN3N*OF$<VD$P}6NcLxgTRQ_-Ugg{sMey4uNSLL5z#
zUCm*FY3zETVlCPwBT9(6n&6UC??R1c;+!+1F58tI%(rvHh_}{Ir0Ft%9-iFRn1dKj
zYvw4!d~x2OS#m`LS|J5wpERbna1aIo?sdKar!gCQrkYe11roSTUn!q*^|;|4zPnq%
z+`8XO#Goe#5*b6jfWZJ2-^^m5#4<ZWRhhb^_N3E+DLv(WfH{A*SYwZKXU77_-K-L^
zd#!f1I1<@|!Ehs=<Ml8uH6OM)Euv%d<^B4@UmrhCKm7H*Tm}V9fgL5-b>tAf6un5<
z?1D$@C7c%qzxj=+^C_Dpu-1sY8>Sxo)n@v=PeMwZktnkJ8suvmDWyUBddR<>CeJ4w
z+^vJ&%Jo4a%417RX`Z6Rb%__LuE#aXaerbRY{nYef1Y-8jM^oz$DKU>^tsl5Tm;!F
zGx>vSPU$E@byem0C%(vmh#7^#6##E#kyri)Yl#e1m^P^?{lJS$4L;~0-JB>!(MzYD
zvaP?5ZA&<_$Z^R8a5(oUJP2#Id3AfU{GRV9_@)*xP4V3G9QyGoGrkMsH1BVABoZXi
z%EL<rXL`N4+)QCHg`yb04a$SiW~zaWWyQQYWh`n7WFN3!u5q$GnJnW#52JR4R=4<2
zoeBZci)w|AIV5%Qo@Okt^HzIj#IK5-=&XJyljBm0*n7zO%)275w~HPR$4b=}+kSri
z`OByM$;&UVKYo7v_-X#--Mc{onz(cFlI;C#L!Docr5;0OF%eF?+MVpp$bw*QPb|f!
zUkYuSf}@AJuF__BbklWcGR(XUg%hmi@WTit7q%M=W(chW_1n(i@>u-VRFR7TH2`$A
zl~-q62x`mba~nc#T&f4ZN1<X+J8yUE8|QOR=m;Ei+SS<e4<G*uU+VSiPoExt82|9Y
z$NAfLm{>lB6V$KXK6H~!7}NEDIe<$llv@1J+Fl*FZljvi9F*b4(Pl(jK;0m%8fFmn
zx`%`ELQ{aK&VucF^Wps`PgCjIf&N(D4Ad*Q4z#(CV4Xf$nRd?YP%V(U2crprRGv~e
z9XA8L`theff7Hz5Lz?T2%tQD$S=74m0PT)?0fkGHd)hu^<K#n@D&Y-&wV&SJF&>y<
zOXHnwe&_l<f*`ImOTpZkncg@Gpq*W+hmoUF2^m|~_iVR=hU$b7>oc2d0|Pu-t%lju
z$*Wr|5A1%no-CumGWDqb1wW|2N257EKXrQN+aXdg$E7~W_K$l4#?VSF8#oB1KPV_$
zoYhX*(xo0~Y#%Y=3dNtHa1b4Go-a4=P3Qg0HD2^9hcUXr-_{^{I%tww?a*@jc@wI2
z8VyV&kY!Hdfk_2D01aJ=5QZ<X;vx08!}BAnMfw$J-QAQS(z1cbP{B$BjFiT5Alb6@
zd;a{FEcWq#AD!O)vVz*}&+(t>G;)xRJ8>$<L41>3(=b<;_;Fx5sxFQ-^sAqP&fLL;
zcY*JKFh>;tSc)qMkQRvz97H5`w%(iafToP3$hIczb1R6}+I#~?*!IqSwttYhzO33I
z!5`M6C*}SwJnv%Zh7=KvZ?Vm_!@%6@3ZL!K9>QXCIUDK>2H!#Fl;DFR?GmoHcUyS(
z*HrjmH^VgfDk$_v&cc@AMAKE|M`ca9Y?<#u6Vj%0a9HO?Cb!HCCFZJ_x~B*`d?S4p
z1BK0h(Hn)nF+Xq-k%Ml0WJR0Et~yw+2r><l14}iw>;g_Jb5^vbe!`VY2fgxoB}Vtk
z^AJ4Yz|WL*=zvWJMsW^D<_2EqZFx|Vbp_YgXbRR0sX@jwlS|@CQ)JZ6xV$Q%i*B4j
z6F%DGU+{Bw;@3w}yOUno-ZpS~E;-m9ux`^xJhSJZywEsF2<SkxS>3x!g@T&W$xrX^
zk^G%g-4Bh~i3<!}2%9tl1S#Y5bMvD$({)0!^pz1eU1FefvQCk5aV3$|%)65qh`GX2
zAv}M!nu$KtP5PwR5uUs6qC)--P;=yz=9Yms*n`8-<pgzfk*Y)HQS&Y%hQdE`eft3I
z+3bobC7?}1#!Uh+sO5UPwOMgBa+SC~8&`GsSLr%(*c1E%NN%f;ShehV7eJuuTtesz
zHZPmCxg_9Xw_>^z`43}i^@hS0-F<#4>F6(PJ$~*R3(*0F$0J}Xs;`JYEVRZ5e?XdW
zXa$P{Q4`$Gnu@G(9%#_AA)wu3JfV_<IdZ4m1X9rPO6y4*(1JL65A8lgP}Fj|ifuED
zXt~}_T3hH%mX?it4kH5eCg&&5aF`B$m6M`{MX<RUdrYOIOn$rjd-RzF6DV)9#S#LL
z>BzBzXtHqwJ7tduG6Jr^Gmr$9yUfys>snu%Y3q|7zu?R)yOUmCOgd0frW`C*hdQ(-
zzqB&BF4`jp<4PkE3K(zJpD{VXG!~b@fkGyNk064}?ts5lqaKb>23mLCe!ltg<L@3n
z>df&rES8ykp7D{KH84wQA^fbVKzS~3v|tz4goz55<Sj;$x8Ckwet86E^#{ja>WoSW
z;}kJm_4(a~=B2mDhKeT$T64W0BkRY~O@>5-U;_g2T8Uxn=DY~TcX-|szpz=v3CiLU
zP^x*=3FH(1^5Yk%zaOP?>i~az_c^gSQgD!q3*3taJ)05Z$V|N+Gk4a$xt_rs%Ag#y
zGXx<3XmTOIXoc6yuoKXtbDTucP$c`M3p~!TlZ*-^@5meFS5h}0Cr`|W&3KLN<pV8R
zG*T&s-LJA&X`Enr*&upa24gf?x+7mTtfW%YIlGF$K{j~k``mRCGzPRot%f)*Qm9qt
zzJdF}`sPNqRcQvzXP;kFr~#-MGXPY#N;pV-b@wng$AgqmqS03<mb4&V&ZkNbfl5ak
zsJ_T3yX&e?zZiiQ=-K{e_OM(`=s%@>dQG)+NYvOu6f!rDuYcHmeEt5@?}K6Q0JJ(H
zBOa{b=So}&F65&k7Hs2gM<v*)F}mSX*VjSwU{*gY<3abU3T9|(0(s$1#?#YWwzuzI
z|K)M{_S5Ib_syT*eQsXAd-uE7Z~ml>WIeh-`57aWW`(Nf5xAc(^90yQI&!T*T;&Pa
zf}>>mEkp6R%J+u|jJ(G+WzzH(P|ZxxnUG2>h&5Sl>Sn!U&#Yqy(4z&(R1A#Xe!4~B
zsTyzN?b8I;pwc#-t^ByLeR&}f9T6(VH!?SE6{bcEt)O}u4IP?jrflMwi&_aj3_l|J
zdgxY8nGysn5FF8+%>=T}-71Y|hpRN6J!8rbxRWn1DR1ASBE$B7#w(l&?&+WxwRSrq
z0OLm23ifo+jUrqHZAsd^(ubph>o#pGA=+|VVBJ#FXbkNw6X1feKoKP4G}1MPX7o7)
zSt$LhYVp*S+@QEVO|^CO=E`mdr=L*-OFU)1EBig83ffXOO_9=e79<V%-TDDOREceL
z4lV_0BQFW05o%L~#n#EFi~EXXkZ(`~+erC?twVnyYqRQ3$bO`BD=oiP1f6Rql)M&+
zzN^G)m_}0?c`2$IwNJiYGL}LJLtiK**j%V*Wx4ZaM<DcHHQ(LNlnf8&N?dDAvp+0o
zr&Wjn?{g|IA3tUA0tsy)Lm(Dtz6D!rU`y``owWQ*rns45FqMBvZqzGv0wKH!dmLsw
z1}IWYEE?3y5<Q0UX}-n>BdaZnw<7uD0#RzvD>R8RDXI|Zj#sy3wJ}7>TALmiRO-4R
zJC6TDX;JnrTGd~8qWm?DIr!)KHqTag(;QYqasPBXIA`ROUgiEh?TI=<R>Z&cg&kp%
zp#-Ntl{?O3?6e>wp-+ft^ty9_bq;}*UsNDn2@%Tq7L}=x!3CQ;tIOIzpPsfGM<{C|
z!e1H*uSb6~>mvPUkO+ZU2mSabv*n&U7AYjf&NF7bo3G^`xS|bL!}6WbhG}5ZS-%AD
zwtY$KrhkP~{2HkKd_D8*ZI|QkJWV;LA{jyHsB8;~RxY`hewwZd1&9K}twpGigicDO
z+k3FUdIqu}B@7H!J~^8fvmKaM_t9{nd;s6^-exTveSB+kXKOa&wC|6zEud)zBE@hh
z=#BX;Y9#U`hLsVKh&e`SG}44@e_9Q(%kYm)6y=!KQ3TdJErl8Edpc+^aVFz|NQAG6
zm)@y(?O8bn`G%R(2F()+Q0k9R3RwPTw;%V$fhJh)9`lBsq;bit97`1()733h1+)3Q
zDCPmGLO<LD5r&9B!b83=4-|T>A&Ddi+H!FP85n7&Zw7YYTIAEYowk0V=V{%|tb*|c
z+I!MBpm<bv)Yu`+=F&oRb+>wDhVy+OL#yo&ntaqj^ryRKvUo>y$a7}-)~d6Id&AP$
z-)*ntql+`qp6UC#zlR=5eH=`7@|jVYM~N0yOF11RDt^E*%p?oxNF3ruSmrzTr=~Ej
zC7m(gpgd9<T!bC-zi^BQx4*L<SHQDy1q_o_n1kJdB_&1e-Ue+ic9ff7NO?F&Y<#E=
zo0Fi<9K2CnQZRVTG0BOGUa&IWQt@S~$Bj&{Pxdfght4ud4<9Sqa;8ae&An?>CP-BZ
z#jj~zbfFoSZjtJ6m7iu3uNn!va6QyZ&?2`l+-y9zufldmCk=K%P0tECmzA2d@d0z0
z&y0Vf)Hh6Hx#62{2C#{-AU90z|AYL)*Wchk`WG6|`g*}|Gw^Pc=~ErCF!4A9(*KJ+
zc(H+zjYS8Bcl1pvU-1j^E*dA<AN2db{uOzj@euU=7ygpbBkF-d_nFi+NO$`K^GZ`3
zt>DnuIIO@Cib|k(APdul;Y8JfV@P}|`t0bemoK!KeojKM@$#aUwJV5LQ24qUPhNj|
zB$Kp}g9LuiHA4;0WYm=MbN8w=UzV>WeiNtqMfDcMu)>R2wgXH>2@_016n{Kl%x{%(
zn}3<EDiGA@m>)}YhUoUxQ-bS6oei;}alcco4p=vlV^FpnmWn);VmDuEt|d5ec5sB^
z-}6w2=cWzXFg<46M7#qIh1paJ7k#V6rMmLZFZ5)Nh_*W#w#5M+vTRp9G;G%fRn~|>
z-g8nFRX|hzgTDm@Kot_yNf~I?%N7mF*mUJ%2jP>ESf3IHDSgUjU?Op3vf9=Bj$u<3
zFZxtZ4PG-^*hQ&dJ8Tz~^j2tIlTRBC!g#X_%H^BQ?~Q%*PVNh;9lym#L8WUBF!@@a
zu5lG|wrdc}7WGr?yM(rC;6<}usm1r&8O|wze5kc>n1Fd2t-fuCdoPoaGF21+Jv4B}
z_!34%^OrL`^j9(_L1cTlXC4b=@a61ExhYr7oae$j<Ow35z1!@PuHLtfCNII%-ChG^
z+TNg0JztQtec_%+i2BB|T(4mm!f2ao9EX6wIU55GsAbT)M_|wde$t?MUTaN>wW3+`
zpYhxjy-$g4f#jAnJ;Zx^LMg6Y_Np$b9zoT}v>;udK0xLs4?2SQyRuBMNB869-Hfgv
z{^K|Q3gZ>NH5eSF@0ia-iY-YAa(2w6%d)q)EB7c6+!sQ~lVF-$eV|13?G9!#m^dp@
zJvaK)ftLb1h7v|u*6r$(4|kGgq!cK<%Bks1{PaL&0N9ghw1HqvBDX{6K?8FhJ+7o?
zp-VRu(%NyJZOTJ|<EpjNOpMGC+j}6m{!^+@;;E2v|DVC<AOHLjsq0y?3NGH5M$gM{
zI{L4~6wqWqN*(t+Re{pQ@ilaD&>)SHBO_|c7gktMPn>nLU?Nq`7)DRbD5~>#;=orI
z;b7o@*I%Cum)~U`F{K^p`kj)6Okg2Pi^75ab!Z$78$vS^4P4~+i`Js>aqyk{r!R}1
z`wuTnzU!%_>G7F`IhCa!Aw!^&g1$Y8lD(l#1yr+|>>CJK-tAc7WmH#&=<A?6K{=`b
zxFd^$QvhE2{R@mui%%g(Omb<P9{d7~Z0bvHRjv<`h@ibeCOX>sC~#!UQJE~V4{VcQ
zaRH71ejx<NRBQpNRaL`lf%K8}ktL?mMCqDsIM_`ONymXp>kDK+Ss>;7A?73G{oJp9
z4Ah<E5a68vbAEbw*{V-P;tCH6g_n_1$mL7Z0;foCJl_jj!LWg}HBgU8nSN@VD-|c!
zs)2B#7}JG7><!Y-`&2j|(*jl_kGR6kD`bpeMs)3a<leH^#HVz+=^>h9r(@hMRk@g~
zIfl<j(i}rbd8)Q}PglLk9|i^izx?p6*SoKWZtctcJ3Mda{-p+ndI2!-^!}O8in8jy
z$D0*AyA-w430XkYFHB!$2Ya=+MAo2yfZXB6jfc!o-NLn^SjB%lVIieNZaAuS<XEy-
ziX=sI9_63f<>e*B-{KxWl|9AE;eK`^VyjOdAZXv+n4Whv-a*mZ*6Q_k(Pz}V5AvMY
z%6i56`{;He(|*}}2lYbpT~_NFPPTx$K`I@OE1zGBNiT{P6$Pm)-IS)sJrmk*sbP8v
zWHS1H_sgtp5E#*!Jh5DOx>{_(O<@(6%gMO;Zp-pd#`T7VY1E@(8ij_*9rxT$JxT>U
zy!vfvlhVk|tPKTjb=5j>p_Lt#ggiTlnHX94pSfJgJEX>!f>uIHo2e`zK5gNU28{0p
z(UdPW_vxHBJo!!YPNER-Qp=yEWlNmVYJ{ExueNi?i|Iv%S%AQATZY+^ei@HigmIEN
zi$=|xS15#cIharCbX?{o36GX%fz&R9qc(dMO|%rAW34R{)v(sQfha)B>xZsw&?%=a
zmwUqNin5obfDhFaPI0fDs<*)TigVEGIFMi(fx277U$53YK<XSv#Z^(8^3_Wc`%~FE
zS|>`kTYjavL%4CmFC2As-k*UAGa>d2f9ZmhB{=GyT2SyTH1sKfHazE}ZZ~2T4v!c^
zaX;^D<y%eQ<7kUXimbV@-B&n|1V-WHw<-X1*0h_bd1itOstq8oysRsUR1nQX#aTvG
z@j-8^=Em06eeil2P1jOe>0S_c)9K=%xr5bwmXy4yp?IuqqQb&vq}bk>fEu?gMjUQb
zNxF8#^po@%v&p0OmW6N4M}QpWnQZFqy<EmC=!I@~a1~fwX|#E{<Vo2%bGz__b>N+-
zu0Rn}z9e1gv0T>e=MR5=c>SlxyFWMYKD_x8qD&VO<iyWd)UMh50nkF<j<L_6<i6a$
z2rjynUkTI{u}c3bc?T2{d*4M$yHNS^C&is7Z+c4Fv9+~hONOL>!2UZm`!BG|d|lVe
z?Dx8sp2|pjuC_j^I9{Pe3DnBjzM-*iLQ57`OVq~jvklcPTuc;@o~|(So(F4<pIS_{
z4{N|ktGUHuGSVB5fTo|SF_MpVM7#&Q{~a;$>|*=CY>&PCM}TbHJswUc{Me}3-2>N+
zU|7Jv?I+DtLE!n)-XHR3f8vb-s)sp~4D}tI{-&=#zuw8|Z}(Hn?XLvoy_ten;T|+H
z&t!<nIjFma>y27?Gk#u{mQXWSCwwwr>Pm&$hUsynOxu?r!tfXv)+4Av>TMWr-hMPa
ztyx6~diz1Q$<R0XNHHKnLr*Qk6Ps{9WX&12z*eKC?m#R%rXMqQ1oqPO0Qq3aC*gSM
zb%5-^@&V|HXDH<k(y3T9YW+kOr%O;tZvDjeh39=6tP!<WpmarV!*qk@zz;EZ9gZsv
zA|LhW`7|?W#`cn#bn`p!bY?O>mSzZA?QeIpH5{N0sR26OeA@9T<yg8J(Ebi!O@cKh
zrl9O~R;pyS*aYl?7q2C5u*6gbAnXyusXg!#qOlUi3&VwzGrE$v<T?5B@zdw!<NH5+
z{^NdlX?q)y-pS0zfCcCYt{^J|jC@$zIV{r|m0Y2MiB;TNMyD1)t66f(;_MJqY1&bj
zH=<F!W3h;)Ebr&#v}%%npp!n{r9^xwR3&gyYgXn@uwsUzXws{=EIuK#j~_pLjL+8v
zmdzs%2W1%)RX|=LiXoE43}0B`Hqc5~1Nq!yv-9Z=(Ac;e6k1hz8lgwwXB6L-iyPur
zGka*?xX|Zb2yvwk%Fa_`goPL%3rBFrKxHoouSv4Y(EB5W*ue0!1>HT1?78p*O+WW1
zoEFN*1rqxMxXf+PGZ-pJN2pFzSbvcTW9j;6WoQ7yJ_xq$WWU0tK1ih1wfjM7)1`X&
zlz<#gDyhF>wJXo!3Zhj>GwvA#85xvNI{dX1E`-&U@VDJI2&qKnN{IVwV-U+0jSP|;
znH6N@LTWf%7(<nsw3#GE%elfc!f+^MZXLpG=cft;Ls(LnVpA*%_q45FPIz<PYnCeD
z&#pH_O#FX3TaLe<O;JR9hj1$uO|}+zZzAi;Y<7R~Vvu@6voYRJP@nzpxXlkiml`~+
zvs|ELe447F{N@2-HNwEUO~vYOV0_+KG@2c?fdCeumZ>Yg=S3|uX7UPVn9^E7U%iF1
z@B$zZ*u@TWLR0tMw)RP^0KynM@~bR*Bj*F^Mtui&1}fME8w#IyoB%hhXeZPGXjs9h
z2wcHO65c;t5;tE_10nk$a_;FDRDYdbuKDZj5z4`AK8;*2EBdx_s3cu59vQ2awuM{I
zt(U%^G}e+|+=1*N$uZJj)ReEUhi=tcV|?%fP#O68wl-9^Xpfr{M1RS%1hc`>n^Btz
zjEHs^mkaq5Y32A*e7&-T;+%;%K&pr1qr(>PaEBZheT`aKBUy|chXD>8qwPu+#*BMB
zv;1sLw}O&0>g}KpFzkZjpDB)mztknkFHidict6jIU27;3g!o{G6aoL@lG%Fq&5IWh
zhT$FqvnnT<9%|d=cQ7v2t5U->Mp8G>5DCMMytAF6A(16k6^xqM|3Qh#dp7(@C57~M
z&`fEMGL^6;h<E<L_gD>7|G<l2fZ%D5v%0k+2Ri8iLitEH_`)1()1}Z>8_IKd^?R0P
zVEqlSRc_K&r-9K(Mfwbb>z=?6XoLR`Lx|%;DeNQ3X?(8?uh=HYZ9n+;e}^i!12~jz
ze|U-mDG|eP$Y>!!7p{q~w1-wY1<Fe+Bf=bYLe;{RYFJrgyHGu}Y~Ea_2=C%CNKoLO
z{nIT@QCI^-L_+SD&woJlNU{BpQ{Zku%|%UeT0q@Eg5zGar*K%QFNN5~e<JPDLmf?4
zwChPsR!;ZGT869IZ1$O23IAW*OcB`QBaBKAn*OSTKby(HEj73bIsWkB%kSPj9u0qe
z@#5nA#mVsG^zwXkGCaF@{ME_vCGuNoJDQB&AL*B1dV#vTsi<@*(qWWhD(O;iirl7h
z<0^G8*rE!$v<~@+P*{+Q9!0o7Txw#C%aUBlWFkx{zPP!&z1y1Fw{GjmOZN~*ufK!1
zVN)26NgqC<&fM?5`~mzV6LIBU8kFmxB2B~S?7U3V(9p5LnM~6iz}$oTpwZ_sF4rI0
zaT%sjV^#&yn<^Iaq7-dP29oxcihm3P%!MpgZma(unN)E8;<Wx=FLv&nET9NM7<e4>
z{yqzjta0>ob_);Jftj12-de4XwFLQ6>%|`5-p;YN@Gs)gA;fi?)H6<!RFjQGPi-c%
za6y@Ac+89n*Kl?Mmq4E<WpC)T`kI)63!+>l58J^LuwwG{MK3Yj&3E=W_B*j-!Kq@j
z<5_Zja72nvXm!%#ZBsDN4+&WMEd@&DVo=>;N4fYd56ZAo6H?wj(@1fc!{xE{aU~=_
zD0_l#aMXHYjNHgJO&JqR&`@G>eY(;b(TKB!W7Yy&&;Eufxa3&DD3GItqa?EEWuCQa
zu9iGfQD0A_?XhFvtY-e(ee#Fdq#&#^l6`2#hR5=-$eCL3YrVZ6wG+5Rvj&tG3F2U7
z52zt}dETv{5O7P>esvk?pXB0a4}Q|RV(Pit%dfcYDf>!MR5xjps7KJIgF~M*3`~Kt
zgi9bq)3#EHw4?$T(?T4ypnzM%lAxfLc2m_NY}-ti$EM=-P#Ohf8Rl0KEb;{Rwrbt9
zoy}W?UWw+?OB)}(;zBXO;mYDt64nq^0%nR;CyK_Q<UIm9*V#8{l3s+-;0#pTes^j_
zONkFOFtgjjQIDqrt+_g|8O{>?RAZWls!1P467B*0*B-HEiFPqwdf!vA3?{=psU^jC
zn=@*gQzi5Y$f0&qaa+Rg8m!gK{uL<OR$l0#JQ{)d$^*Ov8G8Hv%O{+Vgz>z0kFZ0%
z^a8F5osaL9u-y9vs|Q+=VK8LCza4U>FyTYWnW7ZNLWha8GRA#agO!F=iyZ+L@i}rm
zWn5|enVa|)Mw+1c{@c`oAj+U|w8ooWFkj~xfJXOfzS=U7)PLl)7KaCRMoEB%=i&Cn
zB(h`pT-C=CX9}MjKur))Xfxdnu}hXI?#acS8m8_%A>DeYbJ2fmuy{0Vm!CgAzW$L}
zYH;aSWvSh=lXRud7an6CpxYb>rTs!rrB-S|zKNRLE6@9nvC!v8ot>epGE<Rf#>z6S
zyZgQ|F@GkhpdSaFg=mAW7$7#l_T7j*DIU`Cu&>!{Vw>^KP=hH8U-04ODxs3^!9}tv
zzaEheMV@U(eA^5DitX5H)}-l-ehDit?1HU~BQ;2iYGMPh>$p&Xhm=FKyPhA8UpAPY
zV-!^9qf;q`BS&c>M9G=<s0?W-C_~mQMg0yvs@4qY^N7g#=-sY1s|W?xGG8IROY`a#
z>`_Rcfbi~{28u-Jei)po3M&h|>V9$S+T|RxiF6K%>V!w3wivSW0&PeoC*Q3RTTtw~
zcn9@M4>PFNPznmv{tB<v<=&CgHN&T^RW{5`KuurpcQuPzV@H1<zuh9?z%A2Jshs4H
zG99Gu+@5s&f-V@@@E}1^ZOD4jN#ID<@?P(%0;=cfi#+*F?+po-yZhGd4TDQCb>|u|
z!#isek8&voyA)2?=H@7T8zSHk0g~5<B196~{a5mwGE<PpS!Uq#ufJI!tMBXgZyxb$
zwm}3Wvk}y{6sgYO^O*fTaG?R%lFA*elF>*9p!*)V`Va}-wR6d=sD1CbIa9uNiZR9=
z*2zX7(JG(2;CT|Qj*{D#{h}C<%eVaqn1FhmO(6+{1_!-7=d$UOg1fNFO=t+$>u|Q8
z&x&$2I9ZS+efs^)m{Bi~E?DmiEDq)<O-O5cumNo6uJ2$jWAq)A!j00jV$=gLETGAr
z4G#wI1tMt>l?Mx)!a+7k50p|TmVPE8S=kXsvb7Q1Y{`HR)aj)LRhTf;SeW+aASrQ(
zBay}l%E*Kurmri58JTUj-q!s7b`M_?Ojw=i&+`&{c)B~q##OQKh6?bYs9$Ahnt*x>
zk4x2j1er4$H&jR#(*10aP!%=|x{1Vt$andv?S*lBkt@Lp+#=DT=Lzh<Mtr1kDz>Q{
zznK^Kgw+fgejFRP*rU=n7P*8Ap5pj9;*k?+lezgAoZr8IANdbF74%Z<%s=<3!6ZTV
z`Cl;Bf9_Lbti$eDhtNI#C+GE_`_vfg*?-Ac|G7_%v7#7Q8wYq6|0n15pZnAp>-m4l
zSPwq6-o+<-)C@5Ovl85cJFFW;2GzT8t~WRJR%_I!4#o-=dw9#>pQKqzEqbU<Dwr&#
zZ5+^PJ$|c{L-MBfNK_f`DXfMv82rgR!9*F;fK&?ni5i%7E$~zXljpT$%5N=n+kb1c
z)mLqm#-;u)Yg1nwq7AG7ZD9pWZTNNd!ky0*-!tsz<N~J8Ep!fwlSkv=NV;rJO{4|t
z)u?8mJ*hY}=_`Ngu0TidRZ59bqQ>%se$L}}@9cOBA2A%!kP@5In>h9;KS*d(N@Qm6
zmIsFh$+d-BkgSxlc$AfABvys4`n*!^wLluXL=i|<llk@hX2n!Fd<B$ZuFaslizuwq
zW2AF2PHJYHIn0gR7?z+DPB*B}$|N{6x*qW#9ia9Diga~l2T#X?TqWT;p}yTNSnK)2
z?PmHj-PFZ{wjsISF1DenwOPW8O~9@M-vXEVJ5<ctX6btA%%7br#mIbx$ejjxVaM-Z
zzx(h9FEi47c>nvie^8E*)WO=yZl>5y`IgfD^aO^nR-k#v%PXat34mCT-8O|I6HQ`o
zT{qh`v{To26DEP-R^ooYa2?8lUP1z_rFl!;AgrH79=Av7m)5bkV)QD+5(cyutq7jC
zCwP&_-R*9?gh|!*EGu_dku%d9n?yu4o7_fJkO3T4*#Lydcc~XIVetJQzIKADt^MTZ
zIJJuRvX3PQa?c*V9Ya$_6{3$jUcQ)=yje)9pw+cv$o044OHEr2VI5RrwxWTrx4c!|
zK{GBDV;MnrVp_+lNz{-mG1Cu>kn8PaUU{^%KzeX2Gu`M&AP{~F#Un`@_e1#NL2$W8
z;YDfAsQB}1C%?qKL$N>|nC%qvB;Oz?L#K#czA%z(VaZXtHm>w8i5pPun?ea&QNL`w
zBdWAX@r(4z(7D#hd{QPKPtI%|Je!Y6b1GeibSkkS`~dXx6H+i?nma=pejzr*_I8du
zxhTN_-zk`$TA88xp^0jEQfjCI`((Tf)oXbW$<Y|8ZDWv;%fAGvv!=I`0iNl|3kcW(
zu^~)Tp47YWOlXi)F{yX`TI&$9m{gyUT-ueNIssk4WUhixtCxY(raUX5#bD`zi4ma^
zcnmUHV7%g+X?#PHeP4DSiD_{b)c4_8%md}k$XVIIA2epFT+RUL<venf|DD2Dk{P{w
z3#c133Fg|??-r0?>W(BlmNH}9yu4d%W`hx^9qRh1KsjdK>IfcveFA>b=C@4O-C@NN
zP!G2WrTETV&FkBxEt>>-Z_&aT2@vma;uFY_I3;a{#0@+qA7xax%qW2SI$+$z?dCDx
zWm=UB+U2bsStwzTng7-lQ{I<NML7C}6n`MG3A16;Db;{wyFOQR01u(hDDC#A_|db#
zd{5OyH@|uP9>?qFk00K>d;ExxAQ?Fjt<eT)Vd#a&gL>xW;<K)}$nI7SKd`+{?Pjyb
zFTn?NtKpQc4F@A~c_(S1PEK50#tOPBv9*L9@U#8}IWtWxX3PBAHQkBq&QYa#o)!7s
zc3~RV47>-l%Sdb6Q5)63w5HHgu@KXllvbfv8=`oeQOYb68T*qY5O6O{=A~Aws1D<&
zV?hpe$wo+WpU5Oy*dU`t-v{=iZQdT_CGEfxSp{oBvKrXxgxfd+9<2t|jED+shrqUN
z18Yc+IxGY84G_{umXo!yCBPX>-Scock*F+C#`9+U!vb>?6{aO`Q7QTfU_d{O)wQx=
zvZg97a33DHPgN&MU=55%D$9-_)DM1S)s^Pn$fKk)e-~ecv?$XR>W5aJQLIT1G!9^-
zEnY8h^h(#}nU2nb8+Ffoyma)G=RV;!4ZbR2T1}T4yKvTA<hO09vxaFZoYJ|i3{xSF
zNBaZRt<{_-CnQb~Z9E32Arq2m+B{c5k{?R+NHBY~ZPHstGdS+K<=XeQAk~7Q4q<bh
z7ED*2k9Mlb^V!zX@D*WzJqYf|44~cvdQ5+_265!r@~r7Xv9r@^5BAWT_9W}238u#~
zE(ax-KtHB$|MK>S#~6u=LLG371^fbS{3y%R&o3mPZphossDtP0`mb<}*}eJ?I>-2p
zPr1iP%b?_Bs2octmMS+{YSX%tpCH2q-^}r1Ik`phb!6Z;QpDN{26Ahp$k=Iugm_fn
zdyEi)x@FjDfdbL7%AD9nQHC`xH7q`br}*sQ3WKk%1P`I;3O{fP!DVZWGVZpMsG=eM
z!{Tt3gl5m<<@l1pTK5P~*?oNd=5g}nlf_PzvUX1o-5KKu$GO=W=XxNgZ`}Sqx}AF?
zTbm)XwQlXg({1ox0h7G~Io)iv$I1rHk<fr~A}Vo;gVKC;$`<w0is4!EoofxChS_A@
z>@N4s(NC-z4|&vn`;wX{*iR<{riXY^h1tz8a^~WvMq_)>xt>hehdm4{%X0OwM;J47
zESA+h*iiaefct`<h2cn2rUn`AP27=z<+QI?J5K!r^nWm50Rk4xoV8SE(Hv$jaoB}&
zGY|k#@HP9+Z>n<MrQ{?yzd2-h9zvW2^Vm*KV${)yuE*J9H3onAfD%S;-#u2D#+z#<
ztkO75gNBKKG}9mb+<_Up1(^e66#p{hDqK%eix!T!3LLcZ#Oqx6+P7RAoMsef19$r7
z0o4xj2Ci}@k*&L@3M^rkKlD(q^l%J_EN&;!x{t<T>P}P-{dr|&H_i_#pHZ$RZOJ%1
z$yi?pJra@&9NDqv3xva;AD^AQfcZGm!{goSRL6|8#*c2yhi85;sGfvp5S6bf`*8{U
znh6;SL?d^ykbLOUMa3clp=u717^Yh!o|LSOsV9M0M3|gbF>3cQ!y;G#<IPgszB4l9
zW0cl<wnb>$e2atI^p+9oQUmpQz&dC}F(Wg0%qc7(UFk()FacKBWTk<rA$nNaZjJWi
z6uBj<<?4aQYDIjyPhY{BVpVDn%bpk!R4lU?kz+Ux1W#-%7G7ZbI$@dls~{Y=y3&{8
z&{A$dkM%|V*pccfE{kQxY@PM5GNkExm92rK4=I-7<TW8+SS1d!QgzStnQoc(qFrjr
z6~%!P2)Kwjj1ViV^|q~#>+hqf)_2E&(8E*)$k!zZDL$hV!#hYG>~?|X(IgSx1##`y
zEi^HUL>Q?daD^ZOEyg!DGgSBC61E%tpfmR>WWqP95tmv*ZeTBm!SvS0GL@7K>c#EM
zEb4nC&W7}z5X3Z2Go-KuwLx0TDU@kQA#i?<AR{`T*Z?f0R7IvV5_7)jl|%!iIW>~y
z(rh@F$V1fJ__@1N1=`j4<_eBZioV+o{$Cq``C!P5;h2r2jWRWO8A8k3Shm=WUPHo#
z4C#b58v5`eVj83#nxbmMcES1v5v=hXftXO|B0#+q4KG8k#Y2<i+SPBC(ELpE%Lfgt
zF;nkLFm*>l@D)-Mt+t@YQF&l{2eShK-F6rNEd}BlLNE?WB%xd^B3D(}hM8R2Y?+4A
z>!10B@W)Ru@IT-Jck5sQ<GR~twLu2))+bdDu@3sK-ei!Y%XT)%F?LNR-Hip58RfQ8
zkQK7_CT4L&R`RNpkQ>f1FJIL8(6|@3mX1bw#H37!yii?ool-_Q$g+ldK|}WkkE?R3
zsJCX$49vpdNP+~mDWnCQv)RdxCoqV&ywIk{o~#Pn&&-l0Efz;d3t~fIA`NIo%|^tF
z)h1_JvpP)8^>wnSrxp#iO<5;MHedx-TI>5nN5fzDH60x@APpfDuhyFZPMWe{xoSqu
zS4(3AU94oV!u32Dwjqs{wo7R-0H=1noL2hb4$!v`DSMoh%z?%V9!Wb94Sw`FtDn@^
zFnx_k)>$a4M>;rE^+~r`S|YzW&PAh4miG<3Px(=!WF!e@rU(d}kj8`&MIR<w?8b%C
zyeQ5YA!w+}+Ke~IPlB58+sxFukZO-U&{xlwv60bCSKyqbWw9{*XtMlTkiDyp$*)6a
z43hj=w(A37mGd(79|S$-{n0Ux8m3ZMkvDW2e2k!~Z)*ySG~}8EKN{P_w1(-U{8^hY
zrkz!cUKgsHgjhLbbMf0#OU)aZd3)fxkCKD@FK%vkn`Zr8+c?pM7q6>jfu0D_x`Xa?
zad5UmN!A$(tbGsGc-1(W@MB@qf(H3y9?E`i%jBG?cW6?r_CYTT5TIf}?M;P8jQ)Ym
z#O@($b03?B(DvnNeS+5@e?5qe%!1UCQWUXCIOM=uchMtsCWK?mSw(MJAa(aoElpe0
z1IeWw9bDScwkxO{G>0be)@`E0Jx>HlfsL5Y96SlF>A0#b+}yI>0>phke#9DSNo|#T
zUEc$wFU(^HW7*81yX&Yud%Ngn9^_zMRk4Qd2`7=vNhNF4lGuJv$pJ2=w4%jnlc9RB
zJ|U87hAFzrRz_Y}wj_82&!ECzq~!gViWz_$4ZVUy9&`HXoUy%doEzJR^$N+pDK;Ot
z^FR;Wd%H$NKq+VWX60x*u#(sfJ=Vx$Fifw-S)iT+wV^tTQo}T9MlOiPoERj?yxZN<
zOl*f^)r6sjfP`Fh2mn50Bs!6i$a2+#c2iEdUQh$x>`=AO^M{h@3GD(3A+DivK!r}E
zx?h5oM=~9%tXRPby0_fs?nAkO@bJ<<h6`Sn80p5sql9iO?KEtGKy{yDJ~;K@S)tV_
z)mN34L*GcvAp5d<1RMM&GlYRRWL;?J?rx{hiI!K@uB1*E=iYuYLUixlA?dc=OQUuD
z^6+9a$UpV)KF<35^t<p>a?92ni;%=G<(JvdZs&uqhgfSmB;;U(;jf1;M#nEkmoLuF
zjxR2UqqE1aFXr;~!}^k)g(VZ2SU({IF-$RatA-W)88+W|hfLd*S5gP4Z=}sdYJnpJ
zOWQB`sm@QNA%M>(>yAVo;ggYc@<6tSJEZl_2CKp^rU2><+!nj(ZUntgZvbJ2sk_mD
z&HmdpqD#<XmhtlF8EN;#83lD-(qUQT^`I2-1g*3@F#W>84S^gDaGUW=ITHvYKsHPF
z7|u?GC+3sJSkEnp3B2B}E{||O$kA7rvb(7q<>a>pq6ay9SM>9a&%c5=X?>rwk`PoC
zgI{42#$5>Ec=<DTsg?!2NO(Im)x7;5yxaD0%}iO%@hUT1Uk9xX36#&}9P&MV0oKbq
zC`J+VxkiOk{;dFL1g^^m00A$(i8{MLmq7|A8!jSst8R)hOfKOG(OBz~mUlP`33rrf
zjhh$LV|8;^ZHS^-_m^U{>Mu%-!3+;9L8!-3n9xD!rK!BYM_dWn#I%4a-CJooY*S{^
zC6Zz$B35T%_J!kg7Ps>Y)B;M7)OIf$H}iaXDUG4$IZBs$aZdX(z1n%91$tC#ugO3M
z)CPyty7ocGvBbC>4{0?idXSGSgQ1RrLBeu@nhMM1^lrUG))-_*Ti+tdojH+xcY2wn
zaRgw4l)p4@lw}{ts|SF#Soz_SVKE2S1k#)s3KK=vDWxJ5V|J<UDwYviQ?0HS5sL4H
zNiIB7VZnNdg2EeA9Z`9`*{1k*_Um@=TMb<z7INq+pnR>dq_k0PbaXr~n)5=NmZ4=c
z;*doPt{)hTw?X7;1N}#+R=G|V<;cVk{|h=j)s!;xJ}~h>7!~VCo_q!Eg~g4Y@R>7I
zd};?>z5V>_>%Y$5efVqh`JE|kJGcDr!C(Ifi<X>Sbs%6{j3=9y#$zeV2d^|6VwbRs
zL8f`aluO+L<)xPJ4uk^ztz7GkR8X>apl%7K!rWVVT*%LgZ!gHqp<a3fKVq{u#)%L~
z)YFwdqGZbuKil>a>VWmoIQw7(PvMK2GII5~;*D7Pe5v;dX+fr#r{Le3*YDo_?)95L
zl?x@0+)eagzUtJg?Do|l!r%tTbp6AJA5TWVd;8f;@t$L1>S=M5-cQ>oB_66Lu!i-_
zybPmv%k_c_;fFo-5wUw=i-Jq)puW`S20@(CZGg5RWfY9$+8t<GvUy>XfT$Sn0{Ted
zRb)wW+hib60_#!W-{4vLfbu2>B#S<<yu6tYVeBafWS7$<d78P(5)dEJ3LmI+>IeGd
z&kfu6@j&lMmzu<w*Av7uEs?;6xIZd1Vj`FV<p+9Ps6Q{R^f<l2HNi<6R=PbUm>$<w
z1tr~*&wLlI+vafd(h-8=JD(s+)F*IB1uWg2$~{c4H<z0!u%l^)_{}l$3zGp8;zzrS
z-oSk?IhN79HOEjv@}$`L4~;<&{wJ8aBLRTt9)Jn?cr-e`7`ii?B{Ca&xNcl&VkPa<
z;bWtsch`YF<VIqaJb1Y-58eUhA^Se?LNRfr*O80cf?{5w+9WZ&{-`$8KPwJRlj}BR
ziNxf1m7OF+cyqFH$ahAH<8EF-+T8DNW)GMzx^9Es(dsTFb5FKjZ;u4iz+!_$8dFq0
zgY5^I!vV$qr@>H;$)@x_pj-g4?!rwF0!d_*qlflT$XlX4fEtTdBkDZ0%_uFPZm1Da
zBbGMFmle815KvZSm~U&XZG-4GGKFQ-isYo?bnEG$m+FWGGljoU<Cvl%T?#+qT$D)8
zvCQ$Sg(dxc^ny%L-AY)I?haJ<Xt2T4ma2H6gB3(BjF{wiF(YDocmMWhWY_!s;Fr%W
zcL{~vFmupyx?(<BM{)PvurVZ{MxZ&j@R^GD(g1>;>s8lgpnZxt*nt0m(^u{D1pyob
z$(E(n=B%_V31yze`rJ>Dvm^%YRJMlYal0rB(H6>h$DWN-3^dsrBQ<K9ifQgMP*3G<
zw-~zp>h-73k01Bj$N%sDXYEa!+e(rwQT`N6j@dJ2S1X$UscrgIje%H5l(--PP*T<x
z7*m3jw4z8gmn>yZ_x$#E&T;ox?!91E*XuM(5jQ;U5)mFAzWd|m=Hcq{dc9(aj4xLY
z)I%20c16#s3pQYBs5*T+aRCr!-GgM1>9qQ0u)d1!XrSo*0nAoysvpiqU7d9MdQH}6
zeZ9em_K{scLJTypP%-h}^OK*XW~y4WV1evL!|3=?gi9%3R)r-4*PaGq3^e0AC^t+?
z(!>Rao)xz&o3!@JAHhK&YfoM#9~c)u12rNx{do)||1-CmsZG+QK3yLcT!D*07O0{;
z_=8#vSqME{;3T-?^k?S!7DItB83*a}go(|VsqXyYF8`@CGtyDHk0`%X4{<;5*3Mjw
zkEwUU;1dHL$3I72f*l1UNu9aJBFzABW;i@L9bNd?-5ik2m+G=JUoFP7DH7BTQ3QSs
zt~FgEmCR06rW8RJp;AQ}u@p$RJ{><VV(3!*T(l!}&bB^Qb7|?~3x=7h3+y&m39@+8
z*UiWD9x_BGs#ENssO~~+$@qg_7Gh$V@8)d0T0j6G?}I=t$m)pwLWZ6C+BO1Cy__zt
z+_F3mGemPO^$WGS@GWb0RoETceNk*3!0m-ZTOeW!R-p<@G%VkF46I>~HR*e`Wy192
zh0QE&Dv)DphGcgR@(bO@S<KZdnyhXU>SJ(Q1JyzE;d}4~>*HQWo7f7@6ddnys+L<Q
z=FlK|Y_K=sxUAIl$=#r8P1_x^4hjkQ4x+Rr8enR(N&tzYSarQ98I>Q?0{SqQ5XQXj
zVTV6Q3ux{LOguQoLedAIj01|M3b`=+<N8~Qi2+0(!X~DJnw=qr$~Fq)7t?$(iNgp?
zVOiiJx9NQhZ(UPho-Ka7>BSFhq@%M7WS*ZP-_7LxWOSi&5%f{y6d`TVr1#y$YWi${
za5DKW`_+Uu3OP<wp<=_iF127$yv3LlZ801^%OzaP4q;rdpnm)eMZL@;m^{xm@lU;d
z_-#@#tXu6qWd1w5I6Z{Q>Yu1}Cc}F&r?RLtsI}K>Yo9!cu&hjmqhn=hKt1k@MXnG)
z)N8;rsj%fCtC(jae7<8F;OzWtb_T~Qq*BI`%r92!xAT499BtU_eBTuWk?#uCwLGAA
z&#Qw8J5#<a!G#v?u#OPx<gw1*X>Ux8l^itLd2Nvd)1!Q)$Q|)i<KH4qQKwSQ+=)}9
zEP2p|>X9_q0pBQdMS}DqQ+gw7I(nM%Pn3u`+A>FAGJGOL2DAyF1(q7$x67Z-utnTg
zn_*p?8|)a|g$jw`1x!1lGZr{^eng~jb(J<I)8F-RI8dr0O~Funf+~9el#|oh5&fQ<
zrUIiv7Cquxb-&O%G-F_6lUGS%V^fRz*_dSw&8372sizIsv}n69-`X)`9yx|tx;v)S
zI83J}dr7ld?wqD{8?LHZx{VgU*JWEi42DgWW8tzxhSHhZXw#^&o?WT{9)wlejBGlM
zcXj#B@?L*=(7~ffio8VVP0MFvTQ5zSwnSoKUHDRB)N~tuP(3$2hM~w%L#2EJUggc<
z8o3d%4bLw$ZAxW!5oc%U<K<>cb-wRh`QEr~TrOcks1U{@06t%9+KKAi+i?C~9$D_3
ze3{X*$-#DK97<&KNNyr@5<yarX25QYz0pY%u>9?Qb%k1-;2oe60o^)X@*_BN=5mH@
z@29ydWSbO0laXM0sB?}?`AW9>;Ba&4`DEy{0n~48jTZ-ru^a);Nn(a|2pM(?xp}r~
z(qu8E&G8f@MutEyukDg+6Q*yA$#4zme6dmjm8UeI(I;b!<3v;6(!z@zA%XbWm{<S0
zh@BurPX-gf?Q3R~)dY+h>??5hT``*|y}rGW%+w=2I~4;7rbiY`%=n^LU1|1WGDZ-r
zQ1NDbffS@U!mSRB+tRn1)bM!lB7hasNPh`$*Sn<xaQ9Z*$Yf)P8Bmc95;{Qrp0NB_
zJAZkyoSRmISnBGP_`0f#zO8XCE?$D=Y_y@t)D`CUJLptvC78`Dm&!vZu<R*%Y(S1M
zZK@R%A`**~^AtBKaU?iUWO>1PIU4Ps`C%!wy*LbNNoP~x1nMntO0t+kYx6!w-7HuN
z#ScLGvLXXIa2zjLFVBY50)PYH7d%JRbhsC;!LrMz9xffdW`h<;*bK!uBiK<Iiudkn
zcsga=GmnzeUf5a8Fm7j%D_=R&M?4_xe$Ea)2CRbZhR`utlfECSQ<j$9swC)uQq6(v
zEvTP1JbMG5e*7G|s-xL#qJ7Rq0DUJ1CWOeXQ1`GoBi?-VUcTQetH)jWbtcqnbkb;y
zX$+@Nm27>f1@vOx9q@b~QDHhco%;f%%e*|sK6<#0UkK{@1ti3lqM=HLZ7n7afD2%~
zI+PLGmOZ2s9?=TIYx*TZlMbRSMy_ZR?$SGwDRU<aL0l@ZO1joA|H%?qiQ6|=UBecg
zNp4Fzp(JI(w>oIn(o&2_ZRkgqNRYY7D?^g>p{6k<Q+F|+jw41Qt~G~&=h8`Il32>l
z&{+C6xQF#kX4<8nYRFNnNJwudIRDGrN!uvWlJ=^r^p>y;4JvUsosuMoe6bzGo<S#~
zWax8|dYYFcy21`Y{#&mzo)=ym)s<dOZvdu@T`o~n2c8&^I48rylS!@mhr>2iSiId-
zhsG#kSJR8dUSb}N$=>E0TW<_ddx_}nhp6=h%EjuNIhM?qV#;3>{+Z!;05?O7*K*TH
zJ6iFjPIq{(^QG(chp%7Pmk$qjS3f^KZ0=zr+k3V5`ov_A(A2!FgeeIm8Kf_VeU@~y
z#V8kgqwWp`y)8lkutKDUoLK4-*Av#9J4I@%iyLMQl(G(cVtI@vb}+a@n`F$&pWtBd
zd2i9P1H+%J)0-YnnjA?3s6lH1{Sc^JS~x>+jl-XTK40q>`$8NpvQoKj8@gpHEN-ac
zk8_4Qu7r=8cUMLSXPtrxj3<U-!tz}i(QY*ADPk>3J5@Z2#!X;GoW6rIi%asu7?--;
zkk*w~Nyl4ZbOLIU0$VUnq^&bvl{JI>+8){{$iy<Y+(1Hn9GnH-V;$he>gLWC)?55{
zf%6^^9(T#exg6b)`$bB5m<#cU)6q{NiDK<J5@RctaPo!b4jgcQDfX~z&}XMC{V$3v
z{V#mW@AG^*EHwOfn$6A+)-$;zH+=ou;DlqjW{MfBi|gj}iK~HDL*=K!NEoY=XSvx;
zuaYy&Db70392kHLE-Q|XkY0z&w<qItdQ`3Ypy=-&?W1GNa_U|-s<(1<ZSz(HMpmHg
z->X^zCo^Q*Sic1ife_F2`tt4zjMkC9Jva+`T>9y;SGil%9W)8t=SnRB+*qzqUR0-F
z)uNA<UcidUj+sEPajia>LOa71Yh*`14NeL}2jkiaH1u&H$|%2ONl<pG?W{-_xQIbt
zpP-~}5*#LwBejz)q`LED3Q$7Bsk@W7Ie5S`H2lu`JgVT(*tqufm5oO}ZOU(Rj@((O
zb5NQ;{G5<Woq5U4TYdbfU`efa3xorOjzi*s%|EaOq629zfBB-+jrt^xeK95b4w}@f
zt^`k-Jn6KWQhgJeW(Z|l;Gi~z#xJP}j3d(<5-|0L#e+lw^`pIi>{PRcI85F1$&Y6Z
zN++mN7u6lc&O1c;(!Ly$1w7Wj=}W^-*VW0s7zs4ZbDi-4+gQ4|9c86hl7P|AKs)HE
zA{0LzW2WF)@<fA|GpViVHqgR=C@*swJC?VF3%W3n+|UKbL4{|E%F7vmKly)fh~>Ek
zjj(@w2S0iM-3#OMD{<1psXbdo1Ed*oCRjN~co={Vw3`w_8555jj8GhFEB2}Ip~^>S
z4=HW7`Uxqg@suJre%?{@5&S4%yC0ACafX;k;wNC44zCk#dxt{O49>GPw&~;vP&F=b
zkQOJ-pJ{N7c8!qpL)&88Qe>@$LPTs+!*t?&fYcd7)WpF3KdI+QI@Ji0GIc-aP~GRF
zfkvU_e28G`6J`>D{DtB(2ro*$V7Y?;4Zg>yE*Vg<if-#RVOUxR9umwTL=DYiI-EF%
zp6<wYh=u2Y%`LC}p*Uj?7q5&@^TOh<j3%2%(wW^WK$@Sht-xouUm0{OfVyfN`5WNN
z@RW5VZ7<SoBDDPS%#;A4jjQYj$TBWypc^oPGC-4O)1SEUO$?#zhByp9Bg8nSwyLgS
z0AQ>}>%qu(P1AmQxD09hA}R;z^D&_3^#lX}PgqVCs4V31ZQcp8!Q|!=6;Q1+GGoGD
zX0hSFSGPAd*ZU&Ck&q&;459JSu)XWM@plR8SMM8+qR~N<ok_LDOy($zid0i_?lIge
zsS=?a17A9$Vv5}F@-3Z2@yH%b<o3B94mb#0qzX)HTjp1Q@RY2~rN1auE9C)`VESr~
zhTkiJ9^yNr-kklQWFSok!^V|MW-=~nfFBM|5P?1!LrQ!5@^vru#7PXT6Lf69b4&YN
z?};SAc_p9pnEIV5B+N7FeaX;4`GY8M7>|6>6L5}!baY5kx<?g2{ek%q0R|n$2tiqV
zo1C2N&T(omWY2#f3AbQp=LS$sW&0T*UR}&RNqZYKK7VHpmOQc;KyE?g-N%*o2bNw@
z8mZ7%TD=xH?{RmS^V*4VC45fA&jRC?lL_<Tj^X0zq?=inTYe!_o(d1(!dIx3pj={n
zW98@JZF(6Qp6O{H%+TSfd)UTRf@fzSbNMK)i#{tn1aWL)(h#|3R|!7#e24B<8&?T_
zioGPK1Ab6kB<R#jT1f%W+jZwum}RNQaJ<U9S!6W<Y(qK&SIW@A05x*#)wE+vr@W9k
z7|z$SXvp7h*13ut<O6asR@(0A$@x2`sbG-GuKyKkr{6$fJ5y6E3!DI=EWs1K;2-Mv
z{zNB)u>5`}Jc+R`iNq7b3&U?q&Ib$EOxUDAce_WtuJ)^xAr>oiIvLL{ASK$CXPr=;
z`rzeL=ytyc`leuR=qZ(Jo`IvI1^iXBVylG~o$wTTK;Z*UHe9lT{+drWgeHe--Mbwe
z$UX1v9fZIZ0pV_Q$j*)?t`+(QA}-Xx{BoZ^7qU3HO^}@;rIJ6SJTf)f&4%ioY)ODL
z49+3SLSp_7jx?chA+!~ui4#6K9Jl#gY*)0C&BbF7|C9{xt!eLs8++UsFC_<`0rP%h
zCK03`N|{7_`zKvmI5+yvOP3k|myVvwKpb$y)m7e?Q312D?3%{}(`=dAhYw^0;*u+?
zA?mDIF|}`dNiiW6$W|@XlkNhWF7vl~lWV}^N^tuGXh|RePflTNb)-n_h39G!aRy&6
zqkp~=R<r{O<E0fX8q~{ZEBU$kTd)uEpodA<6RrS@;PU0USsZt(zJ?RII|Q)AOTbK-
zBALKQ*rmS|Gli_vRlI+(H9DX+m8SmiBn5t<CnjPJ=MD;_%gGp{z>1lTlB>R&4JaGY
zl&of|bhr=0Osba_5*8DCcv~@3yaTPsz*b9t<SVn@UzE`U`Ew$>eNx4ulslCestSNC
zToBRgOTDwAM;645b8aen^c?iaxurQY-4ZQmC1|vvNip?M*$xMY2wD!qnB<pwktQOA
zr0@|VN|<>D(*)xO`0@303`&(0igD1YwOSBFYN-ASg2$$al;t=N_Ff~)V0s{#G1ysf
z4R$v_v1+!-uzUxS1`s-nztZ2^Pw*IOvYznzK@PL=`fL_skhw`yQ+QMzRQ9Yk)OY-J
zE(Hg;so`{g5N-~hbIEsgT<QJLikzvq5IAx&o6s&Xq<Z)A<HtLl`yXymS+jTlaQFD(
zp|>jgAZBCNpugT;edLvHLZQE3%^0IhJ46*=p-3RI{=F3L2vRj0euu*qwgx;=nl4w-
zst-5nC?ZmEG!-7ASO*>d;QpleGwN-WkwYuIItFQH^_g}5M;<h=s)8%eXFmEeIQ~#!
zJa8j;;&^$Ymmz+*E;SECEo2626*V$9b9Q<<CYZXDABTV6OYq*Mw^1nQGFZI}UlHV{
ztgbRXnx>jc(u9+yRi>=W0}{o7Xm#Pw^VKnYSGyYXzQOcxBaT+@kpn94o2prFH%ZP9
z0;VWzTlnLcAXFoYxu;=)^z`@)WloNd@@wk$;ynyF#|)4<*o$+6dO@Nhj*26L)6m7F
zH%JA(SeNX09-)3b;?j5EBk1Aq?hW@-{*0<w&*#!a6q-AH%lQrO6kqvxcmHs*x%vF?
z%lcr&sGU!nyZgj-USNNC4W<L74WCXHOT#vk@0++ITnmt<jxVwzN#~=3X)|1@3DqsJ
zLMh<3#e`si5>U4&n+hU!elMR2vX?Yosj)UbP=o@$1}NYPS=W?9aiv*x!a#L+C_aKI
zHI0pvLBG&F<=T<L!;6bJv@LZG@vQ2maq7h`Q^uRAaxuO|34ZvqjP$?y)ClW1p}iUs
z7B?F2n4pl`|LNUr9v<&*)CjZpPygEc&)(+xegjBp6?yh2ySuoVJ^xdo{SYU}L=+fz
zx_%`YgSu?yEU94{QK1?fL<(^R{ewS(f+bBF6#U%Y+I_X;(%D6i)=GoXLgl%p_gw{2
z=XlH*B%5IXi}(1!w6gKGAa+|jrgtLi5&TqOd*WN-Lc<9!LZn?TBPohzdkBv9@#HOd
zv$H#F$`6~_&DX~VaUUUd8GUvZ*)Q}8vM%BYpr#zqmAO)&G=X}Zl*hvne2=I+o_fi1
zMphLEAP#MGb~gxXH#buF8N?K2)6z7gLWzG~Y4H?!r=Xw4xqE6%SJ9wvH!OC6>;j_V
zcmc&N${0)*B@#+Cn~=PWQyL>mN#AD7a6|Sq)p4v}PU7y8%eY`#!))(Ns~hb><voi#
zwvQ~@#xrZaf!k@iqbPS;3<qkuZSu^`rtfYQ@SK;ZA{&Icx+K4f%Gs5N;4*>qyciIZ
zZ4q-70c49+o*4wEc#PTEWPWy91Z#8vwIn*dRpbweODs1fX*@LHPy$RJZTw1qj3HvT
zY>!b<r_Lx9zq1vk!ifT<M<UljC5M*nc}C3=;jvnNp&>vtq2m;CqSE9%IoV~6Gx44F
z18Z5qQA1JM)NUy196kYMQ4AelOVAzUhsfl^_C^iU$9FN4@D|IdseF6lJYu=eSGn9L
z^N9yN2<Z=x#2&@gO|Bs3f*N5lxmhpQdF@Ksrp>*Esk<o`=qQ6T!s!9t6&MK4i(E-b
zaT*{!B@XNH><GRQ?w(?@`hGK%PMamcbUQbd^fi7wm-(UxeHmeyt_J#)q#7-RX;POG
zq|HVH$Db$XBiAM<3(yKgm^?hn#jQ>)xB-(btG+xS5$*&iasZl9zit!a*+w@i>De-z
zENZHqx*Do>Til_Uak8M1TXH4_dm)|FtW{{Q1-6?)to9-WB{P*|Y=`Lv;izRw!WOVq
zu01Q}tipr7z1<XkTbS~mSDRH>R6+F;H5b}F`gz0p;m$B^sBUuNhqRnOW<055pADwo
zfqLN$M22gXy?*LuEm$q~W8XnbuzH^j%}FCrf^;W&DH(#8d}qD<dU>}Q-fb?$CUvy0
zU;UhvEnu;snuJ3He(+g^QdZv+7O?1|v1PIh=|vZuGNZ~bL6wDi@MtkpLv2<P%tJs*
zNAZl>QD>%=-?FodKFE%4elX5>%J=ZAfy!EkWZTH7l+M-Yco!xB<Wp<!_UFh|;FtTp
zW!#_7nQYJZ<}vh6ExoqO++$3VrK$x^h;@QxV2Q{i;2Omy&N)b3-9y_9sefT)I0M;$
zb|Q%wMu&3!@4H8j*XUCv4s43L!6P3$16Whi7a}B>uM5&l$`=J<s}bDiK8<!{L@I)~
zvW);99yS8TVVW8RNO&Oby>2~U_IHpB0Z}NRN7TBJCWH{M8qz<TE@hyRIOFj%H|RAs
zHkm}iPqf1ip!OLRiO#A@bNrxnIB!#YY~8GvnPc(i&CTZS>cjf_^2^U3FX>&}-`_hp
zi9`FqJop0(+&Jy0b^tZ8(njEr|8s=m*ITy*)=hDyz=3}Sbrq)z_7cZxJPhJw^Ay%@
zb%fU`<U6F$+wD~+t|qmD>eXrvEl|N2SMBhIZCodGP&_`0g_g&M7M0`+?RrU&T=JTb
zUm=czw{C91EuHj$^u(gtOcouhoB%d4CSiAmcHyk$jLH&f6mc~^>6<fNa-a*Tj!!GW
z>1%-1@5b$6d$YO;JuI=s;hWHAaTl0<8pZ~sQThpG5bPSx!t2!b&ebVF@Lt*i_~py&
zK_ur=7|N|m`!Uq6TB&@5BHg`fyK~!ujoFU?Zc8}Oko$Mn{)h>VpJ0RaL@b<<ZD(}5
z;4r*^Qrij`ZblKBNWLkdFzH%=@1wyS3`>bUpp|CQ44@`6<!hgx!#aW3eeDv2K}BY~
z38IbmLW2qx*aM_c?gYz?e_buY`CqTa?pB9U!3ws4mAhXjixCcgisx{-b~ut)i_dkp
ztD<n-tCTqSm6WGD<P@Ccui~P~TF-~CI})f4U%L%S*>JojL&;+s{*_S8q?Tu(JzxP+
z5Dcg*BGY%w%m@q$e=c2lzBE!98Onro7iW;b$H-ODPmF#jrzYp~X(ZC3PYxgL1#*~)
zx~iC?20cFZ%Ykb~?buKzF3!$dIOCFdoIgH5>#^KiZ(tQDrmYJuOvBp`3w`GPllsj4
ztk2X$SvXc+^Fo&qAfpLXp&$tg6aml;V$CFQam69l$nUfF-Szc%zW1@!>Hk}w4MqkW
zq=!0JA`Q%Hia3X6gXYcln~4PO-yugR)g3}Y1<&z7z6xK*gb_)k7PqNbygsBNuYkhz
z#Zqo|0S0pY8qOB@&bP=I{$^s;zIk5p4WQKdNq8NYi?{o>FZ&a#rK0aOhmZ(oiYtxB
z+4%w3`Bz36B70*6(F_S^z~bgug|^zh0_!f%)DgMkJZl6C6y>~8!SEFVdfh=!(pdIv
zGr5i-uJYQ19u9X{(HSlyu#);f)b2D~N$v}NK1II2bgAd@ARJCHHIXux#07g6i44z?
zWT+AoDv*zx`^6b-9D>~re@Z;ibojH)S(ryevSVRdP`%Ev)hY%8Ur^c=A*lY59`f7W
zN4N7^wc?ihiaB<*-y3a^WuORzCDBekJ0h3v&Kg&mJfHT{>EStd*);h{(y`Ijx!pyd
z5?hRn1J2HRo*Tf%Ofzo>H4d&#%t8+gj<su$H8A6Y{DQLRBt39)Fljv~_}U_xD4OVk
zN}f05rzAl%*-0Jo1yq9&*9BX6M=5x<=BbHn53aUMmzs7xJ9D0|o?=T~FHBWX_ylc9
zz1ZDBCpF|9Ap|`#4%Vx|0KOSV=RM+034$-!+XO8`$EylKc^R-{Exm`ib6_Pu-og%o
zx}4`ZHSWWguXmfz+CAVw{<X)*f96rfrbDo!DUAPF)YUIY2;i5G<jLt)TEYL`o1Ur@
zd;#*y@&^#bdf<oTb4Fq@8>8A=jl(r8t-dGbf(D{g!-xnW5!E5Ez%8K-rjsrMjV6#*
z=S|%OxM_Pa6a)i(K8Dka?V?~fn3Cprfn-2`LA(r3u;bwzSdFR#6VR~9?(lmSwF-K{
zG-gmRoS!HGla{@1LSIUTCH=!H25D@9gi_G0Q-$>0a5wb$ejXVl?*^BdOG6xK!~|16
znZIq4=?c_(NK=*<vGEspp)@y@dA6cLPgDT(+>o#=g~;-J3aLHh66I&ncp_l-Rkh{~
zke;U%qg;T91=F@dUHR}mECBF!AmhWEpk}xIGS*6@%bg;{!Gxtj-_o|fm`F9GBM~SY
zDq;E{!<7ORg`gSUxA23-_!u!v452cg+TvPdCymxErnqJi%iv3?4CiFRnb#j9q%%E*
zjqD;khUmq?vs;s-6$l^UCK5M*nx>8;uD|EVK~G*H9`7@MZ#o->?<a~}!POq9is|J>
zF4KV#fi3#qD52d=e^?!o%|_W@Yc0(PHSV~Tt5!ZB6c5xf4?0I^W+}ilKu|DvXr1=q
z7l?m?vZQDMnRpw0^2E^C2blv-H<9zSY|%=VlUgvi#IBN_uP5-U14Fe$ID03tFW@ec
zU`Miq=ODh>6+8S`CC@To^|7#0E?IM!=1TmCJL}PE$uW**XFZAEJp!F0>N*<8J2nt@
zKEeit!Hz|y$T{F9!%EGA?fnk3tD6ctt4M_%QME4;-uLYrN((NwCqHj%qOl_D7!(8O
z8g{RUZIb66+6S&CXtwWz6-f^Mk|Uu^KZf0rF8(v@0?L!I?cw|jgEta9pDI{Z<98P_
z-;oL+(QXYLR&{u9lSl@Znx_B4Boe6{U{V>Pgr+%u_=V6f9}RqwC|beLb(x11M-=C~
zZff{6hNug~V>(o=Fi8O^w&kg1Ru|7so}hss;YY~)_!Fj!3TI7{3t<;NA8aBGuk|tC
z016#VgsOaJJ8HgEaNS3;Mel4xFCpW^0K{PU;ltyXM^q@^AfD-?$WW^TvXv4@swVH`
z>0;{n1;AS`bT%6KG3mOwGlc>H(r2)R@e=fTYK*o5sWTEB!v3&=d*XMH#f3MSF$Lz7
zTuvLB-lvoN-I2Rsan{v2@z2J;K(E3z6)0P}nB<|AyNGQzY%{=giWmXXXSl8i%d$Wb
zGyGXoy_ac4%3h?DVAw(v`&v}8FR;wAArF9Z^06sXB(qWIFXN5}kRQ@9NOgisja_#S
zeI^N^V$w-5mrHzXlk@EAp<B6kahJswf#<6+xe2vNp+_r{n~1bBEkk{ezOw}DCXhVR
z`!US&rUXsDqz5goK=Ihq1BzGYoOTp?>^Z4x_cS<Md;OljqoduDw5T5X)`<`O1k^Za
ztUiQe4_z&yQpfili9sbzqObW}uzOAps{506DAIx&g<z1IN<R3cy2RW7>QkhX#X;=3
zB=O4%2vtoPxnv{H#>K*Lo*UKMC@}|+-0<B6KMJE((HB+6E+2f*eW;6eN&XAgimlFC
z6(`QXP4#yEm_0@=;~BkYNYRb)TYQ$256GUV&F<{6SAQFjH<rZpe2WZ1Z-fel8^k7_
zW3$VgXKW7aMb2Hr5sK|{$x+d<Mgwpcp0j?ldhrsc_y6t{k5-$#z~{@~L)Hlb@BeCc
zHg9|X2IsxRhwTOmyG7Z{8^x8DlguX-&Woi}QmQSDakW}b81i)e?tC#0y*>jVtK*?G
zRMX-Jf{_IXnH=NLr0q$Wiq32ICU4UR8IwwD<P>zPBylyw_8Sf!MD<Z6H1Jr9xYEOf
z0IUpm2+@&y#u}En1&hjXWXq>(k!|^Uhc3L9Er70;`HFeNN&V=_pLMp1z>H~<{|^Z(
zKAZU)=ZG!eALIm%dsf_z+yFD&K%ICxe<7ARUuq1&r@%9&qq>$7(2*=SP}5>81`MD;
zM;2)+XR!&>4Wh~z31<ClawHyIn@F(;_5nFOr#hiqKt0b066h#+hsi0O><8v!&APm~
zP2<y63fkeMBv0bt(Jd@AA+<Ak=m;uP!{&U45Zpu?z}uSk6N?aMQK4xp!FeutLYWuQ
zvC|W;Msk5tfXwY^Ns{+=XcH6dw0~Ur%jX9}QrXZeDV85k4%IB;M9o9~OkZj0&~3f+
zv1w;DU1P;X?L|I}t=;qx91;k}g-+-2r`2RvuI@T^{TIuSW;hmM{vX99@{*R9(047$
z>%;TK_d$j{T+HPy^Nj{&ehqR_xTH9F<FMPnoeqBu^aAgu62q~+Hgiw+)zGtCfv0RO
z>k3saU4d%luAGB-m-)t+hZn2~DR*<@W4dxXLsWoVRppLDZuyg4*w;39qp$xwyMapt
z|K2Zuf!`AI6MWxm+_H;MWM)6`d%j10grYl>CHPZNKo$`UN}o`)KnDX%g}P3padtMI
zyf-SzHeG^55`QRfRe6nzh3bS$zRyu(71=Oa4sxS_GM?COvo;6%PQT><`NC<xY&pAI
zFsWYLF`%^1^7t$L1?UAbgRSEbb<6jVLY8XapDN2ETq<b+r9BZ}X%!{v79I|@c)c2)
zO(9Z~^fDQ5Ka%nGMepk-(L^FYJ}sXuZp9l|R;K=8VZ{rxezNM6X&W-IKzG`+RT6PA
zgq_38+AN`{%b=N98>FF>5(PpqFZ5;N#>~9dspSYzUQv(q^y4|M^spdHaCk<vb#*1U
zP||#iu(90PC>&vG-=iqhW&C)ZWz|`nB?5M&Y$LzJ3%w(bSDZ?8sVtAm2FQk#^P+{u
z^b}@fKU!kyw{`MGFp9+uRq@JB@<7Zo2%C>gC)wz*vAr9<nV?j%+n^-k1I*-xSNEh4
zGvqG0ySco6clp=N#n+Ron++aP7V%*a`s&<xIJf$Cu4RJd#e}>=W~<NuVl1$HVtL@+
zaRw>4W&SLHdQL2}5{xh2T`ZAuzN1ZxLu{)m5ErW9B<W-2s+Stp&_x_Lv(jnfY4Yn#
zg4FSPQuE-#BF|tN@M6}dt!C2Wm&AoWP2tspL9tW?J;bC`Am^xYY+@(f;K1lQu8iw$
z_NnHK&K-2)hTWhs=$OH>hi)aM^$O%u_<bBmd@dW(M0<G!ue3t93C(17S)wOEqiKOQ
zbMT-coyxMNZh`m#zCVD~aG2$qygy5S=lx%`+FXYX3JI8)odQ(~DxVi6C*y<cM@&sN
zDaY(IJL+q=zby9;7>4Bo>T3S{+v)Acjdqsv5M6Mao|+6LQ<0n23kntl%q>Q(ToJLK
zGfUD)7U3Q8bR&)_E1SgElTKs3OCnabYq+A|=BeVzR{TO!ZAM5Y(mzMdk5|~45Q8Do
z`L+5a?p~4pOrNt~+vK`B=-oO_PI;W1j;6;=YSD!1mN;zbg+D{GvuCjN`uWQy7^T*|
zXFbIha3PD@P{<z8Q5&l4ps8elAx1aqpH@b3qiYGIZ$YW3nb$0;A{%6A<J(EWO>dAX
z_&;K!2Ez%z1h-M!g+2F4BlXjFJ!Pd9PPmtgo8T<Jjr0{9%N7rSPWa9VjNTS8yFYmO
z;uX!_hsgPBN)0JK><mkEA22`FBn`5Q<ZA@VQ9MT|7H8J8d-YkhJZ2lqR4Hk)Z$~ig
z{{iuZcc*++yv2BS4Lj<ql~g17qSQTv1Ya+IyS}~rC_V|BO}dk~*Ux_!`wgU<st<lu
za;@bDo7YeA!B&3+AN<NbnB(Z;3;WI&_Kh#Jw~-Q%iO0E8rq4tUHnuPW8&XzfEoB+T
zmjm~{@BOJzW#W-gR6IZu`Lh50|L*Pb`q`i8q6pan5AX+5N%apr8mF%w{W3qA7Qp|`
zN5@z9w|zB61X%mEO8G@>;BmOie>8pegNi)|A^SHaIM*__!6)bE^TXlj&G(8_Yr~f_
z1h%fW-fm#T2K!Uo)<lAOae|tnuu{|XZ}M-Degg>)V<UjNC^jOw9;6)SE-@fv12@3j
zPC%mPV6~LmC9z!Lv(?c<@8eF$%Gv4Y!k$XQzujVPgVYewB*TxdlJ1sZ-$+Q(0D<HJ
zd4r%1JAqMR4Q)|>j*?!0yor4Jq$5;|@h{DhR9`BQyl4@kMc2w>Po@E7#xnC!wd%B^
zh!{RN{`s^vr4hq8uQ@qbSH%oE;2MA^iW!jin;u{_Ox;VSFxST8L^-YL=%5>!9dN1C
z%`i?*hrkZV8b+u5&h8#Q%b+<(g8BsI@9vQF84M1_+Q?3|KX?Osh)9iV-zS(rk|&RC
zo1KjgN`gU<6bBI(7s<wX9D~VRnt@mcH!rnLawxK-MlGodmd+Bg!_(trMb)bko6K&m
z9;SD<Uxptqzdmd}j&8qv0T(#Bz4>(YSzI9d(#HC`y?3G}GMJ|&CZPA-!4HEU_P&$;
zfzcQ!BL#fYuY_F|zu^$YY(S@o2z!hOjIP(QfsGn_37$8D0)tnW-}U$${y#^yv0z%v
zF`p8vD`qhGV1sC>qlvnCXgtAO@h|GYxlq++qFX)n9N>dg-Iw<put5v05Z00IF}&7t
z>v*6P(l6?4GFw?ws_-IBB#)qM{8#FG@dW7{XN&+vsapCA3I_-b(%wa1s2!<TkkBL7
zcedfWjSnm`cf!+3WGd)X3#^;AL=H0_(sNk`ka!X)#o*Venh_?%dlS@8h~RaI5Qp{K
zEJlH^uH9USP7c?bLoR(nrwY-uf&$SLZ}G%#?}ST(K+$gU?kGeNMx9nm0K8Ck(0Z;r
zyXgBx1HJfCr^z+Je7M00TJ$h<*&K$;N~L3namQpP;^jO9byvePgs2=+!5}38aaBPB
zsE-iST9ip>YE#;9-Nr9B@@<Y|^P^!le1L0)i#%)s=DNIv|L*P(yeV@3!yjyk+DUjH
zP^Va%6oog~W^%xMH9Gl(kB}7l2~_C<Q}x*gO962KiGx7u#hQT3-rkf}->R3Je>3Nt
z$7=Nb9}%p&oPYJ)Ck3mg?|MqG5^_#XhjSij(7VDX2tSYq>xJ|%7QtDyC+a>1HKwjd
z1bMm~z70axL6KWswNw=mGAnV~QEmb2?4p~6vtHEQ9lc8Y;oiYkh5Nijvq(*6O@4aC
z&g29`t!`LjYgcYeo87cA?NX?ZoM=cx_dilX4_6Q@;H=0@+B)|OR;UFwgvA&m|L+oN
zBWx=<<!%>hyTGO`9V}#OcGei%Nv}k{y1w$&#R?T-Ak2#aw66(OmIV#s)2OKAce(S?
z0azTmd`hA~6@}~oYM&5!2MiupnsL&#^W|s;26=V9;B%QKDU%eWud47-x*Zl{aHKTd
zpy6Z-mZ&;c9z?K@rEiS4q^r?GgBDHqDiujX=95&z)IC^|MoKT6b?PPUq*ka99XP=Q
znEcCfMD$L8y8HOBVa@AhLed7xGz0%~2)92XAg?7wWsp8ldt(lp{sKHQTHs|yzRTV~
z>k6VrCJR=JhaGvbl7*#i^1kLL;rVjV7v@(!ByvPGvO_^P`LJPF1KyQlF-P=26mQQD
zsq5cx<4p@%?WbZ^Ibg4e#ut{&Xwn9p5(@iZRZ)@El%aZCDMOVMZb%C)4}$GA69yx!
z3u-24wcQTfZyu8kU?(n&4@YCTS2t0_nzajv;#`B%%X`>C*2~SmJu->=<@I{8`LMbA
zbwg|y!&Ubx!8^)2!ws~Ypwt3alCulciWeW}8g-=2NbO@bh&FL<_0+hyH0CbouHW-{
zPih5s1&2j90WwGBR2Ry@c%Sd0a_eCl*+H-2Y2(U%`cXqxtxP2?ux`pbg<pwtYb#F`
zq`T#8i*&bD0#VXQyo?&LxmC$YS6VbpN4O7rD&2Ic9`#3!|Nmh1*s(e!d+<o(Rb`&8
zA(|AY^w6{ni=vq|r4OKP=r~&8`knO<k^`6YL0?reTG_4#m21mDgwWY2SzscCNV*4}
zHOkx!$cNjM)gE{#7{X)|OVy_9=-?n#7FkL7aNUQO#k9OK5;ELQxrH<30bqvAvO_kE
zGj4g*yMOo?q!5Q!9K8QHf7hh~$5Wr=?w-2mY2FTL(1zEaZ)q%AGa(JA3Y$)j&MC91
zsUR4zqX2Wj(P34M8OJmpv-taoT<e3hP^e|>0d@$i@|o0C&Ds-F<jy*MONRm^e*N@#
zzxfD*NDhZEE#Q_;38}MsZaJI3WgbX<pIpC$dd`q3!<yXPJBd$6FTFwt%3|;EO<%2O
zEIL5C1?sOn@nBa6-I++Fs{lG&!wUt0Ow!?V6~^Btz0)I;;n+iGVt+|vAhg9Vn}m>N
zEvlRuCr4s;i)$?e#hF~EF1@wWy6kV&Vdw6{TQZBdFN3ER(GB5lY}{X5=^F&Myc(7J
z1H5-!VLCOZHE57B15>0M$rP58uoq;%&9Fy8{Uk{<h*mt|UV~we#1Ma;Pmav}7$lMx
z`eJfFsKhef+lgQO^b3V19J-%=9i(5+#f?U8yQYgH7qo<BY_eoHO};}|5g>IY523w$
zI)1(_q+;!`h^8>ys=WQ&Twa@qrSvs!+V>3aOzEGAazP1>mk^cX;^_MJ=gaHDM>+t=
zmRQu+GK+vXv9>r}@wxqa9}0(^1ujx(fC{DZ<KO7Snu?GkfDYWY*lq3MLhsVcxYPuR
z1w35#*DqE-mO9^E;;*F?WPzgp5QfL~9(d5=`(F3T3*l0%m`B1qe^D%(n7twj#(-G2
znjIAd0V}V>4L|^j7P*+{<n9tFSNR&LZ0K$SxYrUDP(1nc;!F_?g1%)%bdwNLE+H2o
zJ5~P)CM2vFh`uZtFv?^G!sgg}Nos>30<jRPuIkDWgFgEcAc#>hHs9~CCK@lqha&j7
z(V2G0?!N0jdRt=I-M#Ps)yT<I<#Zt#SX$|HnTeD64nYl6Goen{Bw5Sq<QWpdEKc6d
zngKo@E3`OH8RV<zA@fF={0f$TdHZ<xVFOLxzLe3dmA3Nq8fXh08TFSddQ#LM<qT_r
zYDJ7LZkKWnnDYiwPC*Lrbl?8Td!{A_bfB@7Bu*<`>Fn&!2!mM<FA%iC0C_hh{0>|i
zcFPt64SUlY5Zl-@%Lu69aN?~>4h9y-K67B;QZ65(H)FH30EzKiD=GFgWeY<FGc#zE
zE$Wvk0A~Y^6aRG~;;<n^*ds~y!k2)N{q8dEK@xQZh#-*-{{lPGB2*$(kYGs&os3qY
z-s2iLA*P9i?R|@*GKbiJW=<Eb*(j>Ry54YxUhQHdk6=4quYZ2Lx_-F2SzrEqd-uRt
zjc^);Qh{j$Mz3G5-%;3xYDiR+xla&qd;xc<#aXZ2q<PnFf?7!1$s<0}rFvM{A2Q-%
zjYsqIlb_g1jx5Wr?JhzX-xNF#rU>Hh+%W;v4Ke?8=^{%D(^A97vb%@94W`?*Yaj<k
zRN_kG;4!cLf;4Z&uF<93#xJ!QG&y*Xr&jV4gLwkHnRGsUsTYUC#qMJB8MWU2nI(RP
zsDH4zzn6`_y8eHZke1yMqzmB<a{yyK4l=u$KGxJ7sDs-;qf2UsYYYNT*=&-1VO{#s
zbWd);=LjpH=7n1s4Cn}K-J(1}*)FRofy7x>>qg%A&ztqn7}Ce}r`tQ0?0&uX@+9#e
zVtR$X_$A(!5eZeRCR^BMnMcXPw-gX<xW2VnK6%P|3&I<hoI5+{R$Is-;Ig;N6{At~
zFB7P>=I3&Vh3IskNLCyd5C<%h)qm^DB~${2WQV@+1Nt_J>qoj54V8Q<ei*t?y(S8t
zr3>Sd8;$UN#E0%IhlqKF4iY)1X2=UpbJ!WB>v3-zMDGS84CO40Awpxn&<A^5T2-H?
zm&vI#vlY;A-h$!^?@eL6CC|;<L(1<#X(KBhjj5_Yi6SL>1gZUGcG&BnR0gr36*;)H
z*2!5xV=bUsXiaMp%35hPH75wKUXD>k6Xi<YoS{12I`}LEDgpvsS`(lgStFDYDJq=Q
zh=-7d8mzAgL<X)fEZo1}-8mb;{Q2NPkSJ*iNyOb)%51qMP`3!RO|@Ue79b6O1ybjN
zaP>Pi(<EuZu#;qRK9953|K+0{YL<L-5F-lB74Ha;-e+Va0`Thb*D!VGlDcEweo2kA
z)Qrpmu+Qx4dmxjoMucH%#8!}O;OA9bY3X?sitR?SQmAz!>pV+moY0eMNwus$gvJu&
zsm6!(cI66@wRV3V_sR=BI&Em4ex=8*)HfQQx(wm4K;F;C=T0o}ISqUUk%n#{Y~V`e
zr!R`+pth`WrFUytBk*sV#sKz+)43}QIC%Qug1Ri`UQ5ic>cNN(PSCS-15QItPz}$g
zgyl@e!`U>ZD6aKj?*nIAn%z)?0Jg)E=vlX_KS!Pu!RYHv-Ng}%FHis!2j^s&bJBFT
zgVM`IXB*Ge1{xMb;;W{VuLa3K4L@-o^T+@p>CZ=;lBNlt$Xsx}DH6%U;O!ve^D!|T
z^xsu0mGC2Fm+9ifU1p%ZA#}~i<mBE#u5mqHrRns_m9GqsA`l9DQ(wdrn;IBx{Ll`+
z)LF?`)+J6pc+?)jnVY`cRg)cbS%P|1@gI)-3+OaS+B`9s%Y+<D^00&4mTM0-qD{_G
z{&m#rKgWV5-@UAgN+e;9DeUJN)uko?N7e*sJSmYYD}DcEx!ngYwhzc0r1gX|Q!1!%
z2x&$uNYkNKpm5a~IJFqifX8ovC0i~LrqH6LK;P7EPKyHvLv((>_))8qt^|({N)A`H
z6Trj_XLi&Yvrrtu4TyB`iqM{b;uR50NR_~Ay(SilXVBur)lT`?fr72(B<HoYqX`sV
z>a2qTMxRNfv0Xs!$e0lx24OBhb~QGd;SwIkV$Bv8^Od_9H(FrQ=iP{$pHArPTilHL
zVKbB*yS(|ZdG;sxktrW}eY?3A=l4~&;Na@K#}68db&#3?M+C-FoE(V?``K85G$-OT
z6zOZh!6-3c)1u@-s8Rst^y~<k-6*z8N!4h>)M08AI4Hl>m!Iqd%sAey2Tm}3LKA_T
ziljDNw`nYqw@8Qz-vY{r459!X@i>>+80EQ{8~!b#o_bx4j@G0k;H^-9(<XpwOP<m^
z)+|`&@bME0R;@>0KJI?_@==l$|NilhhVjgL;5R^*X193ySm>_)R{`^|wgmKST?>TY
ztM<<L^5GK3+h0)~%M^4FYw^f7(DC--tcU>_bOwpkU2q>f>{uAQZFTHr#(ZlZTVgx?
zJC$Dn$}43YQ0EaAAj5{zuIi{r${(8-MwjvU7&2GM3$%dwy|z7?$|E69fYez8C-Lmf
z{!OTE35LgF?9wfrHWH~`3UWTgrlG4g<HeFe3=B(d6<X3P!x;8~WOJ|>cAPX@?a*V=
zJZ@#@l%@Qz<H5BIuE>lly`hrLTBN%W%?uWFH!44ZPsGnNXXC?9--&axlV;60ZU~Fx
zQ&jd4)s&2{OB*!Ut*P04pg3}Vy`*3XmY3N}2v#+!`tr>2NJZasi^rS!?cX+c<J-Sk
z{jsF`woua&9tzb+c5xtULH|Xhyg=R%R3?_W0CMJ&zU7^8+eIFe>Zi8cZs^A@Np6Wu
z$cV(nFrm1P#_)azu_E9PJqrIqXwPD1#LzD^qcx`PnXw_oj+*_(P+ZoYtm0*bgaQz%
zUo>lS=nJ;bj82EiM!R2UqDbJh_Q_>>57wH<NyvKCemIGQ+YpQ}2nB5aFG=7hr#OT)
zB{{pX*$q2`?A;>itX{|*5VMlRf!_)5;9%;B8!a<Wah>{1J!W{I#CM1&A$=-kiqq9}
z#Q3ina>^f7azzEv15Nvbeao=Fy>FlVzY96+lraY{4jLf`&ymFuoIA=i8RKgHkdRIe
zZCWv<S~{}>n!=~7p>uL_F|QWDJa;Wz7fCRBjq5yq6ZH2}EnpW?b?Sl%Dw480R+CTF
z^7_p6J?&At)U&xZ=kUZLtsAhVkTYtSkV$%b;NICq#o`yu>Smc>P>`1E0V!=BPj>OR
z4cBd<5Q227+RVuP3-6BqObmHc^cf$Yk)sZ_xNc5U7G^&ml<yHvNkGz&C@V4N<?@Xs
z(k!m^IF65QIVX$5#H*3*qlp8wwM<IiUwM&D**pj=YHao+Cw+ZH#O##XlyqR&M>d#i
z9Z7{!R};J=$xM5liGfQ!iq4eC7+g`V!YkLX#dM|J97e$OP3mrS*em%5sa@oR7;JqH
zcAI9Kvlgn7eeoV^Y1~A*)~s`TV*){QS963iJl=oZ+<b%v8gB;ypr~bE4D1C5S`zc%
zP4;O(g&%7rsI-7-hQt4uaSAQnw2O6;k-dX%EcQEGmFgW-!_*zLXN;p^o7mQb?O^gi
z7p$-yhfxGTJqI-sr(9&ohKdP`fh-CpHxv+0k}V*3(GhZ{EZ4|SYR=4LqKVCm&Hd(K
zHk!k3@!|4%bNBZ0`f(#vrY8k*xv&P}5;7xvE?CVrZ2{N@)+3avjV-~59b6kZG-G8x
z;$C1R9Y-9R(_TO1!(xZ?LMXw{WOgts9kJfRw0A&*ub?S*I9pl)1|U~l>*<D0#z(tC
zfcgO1v4X9#zlMU8R;trLm4H<#TAI_B<Wo2wNUsHbK9RU&plgUD$N3z3mNhc~4$p?~
zpe}jeYd0D7F#Dq0wERND(99NjD))k+$Zcq{hfryYFLbnhN&YpMiO}f+tdG;aVd^bl
zxuxTBt(?SGItXHvITztBTf7|PA9@woH?DDEg{?vJ@Amx^V^A`o38oLK2~fTBYM8o*
z3K+4qTlBxN#pTVcz=TqB<AE%Aa*B2Vwo-&;$>-xS9f<0WXhQWFTAgeZVir-qtEoH2
zfyAISbjZVXSN%bh74@tOCVu<;ksKl~ZgnNZuoZ*@9o#%uD~8MN*WNo_9rSLW8M$bI
z<hW<Bxp9{2j4_;;TV4<y9rVz2+$)M<dU6gz-BI@llUr_^=KQ&{N4<8~Tm1trUd*jy
z(Y9Xto}f0gGbg<tDqN-Q;Sbr~&xS?y1)`L;hlX^*?J)E6)B`u-N~@>!^tiQ7t~<e6
zqoLIMe!3XB3e&W2pRcce{_ySF`U;tTKHtH!{o(HN>wWLjC8|Q($G9J$3wUu=pi&|R
zv%ho(URUsX%@K2bgrL(4*f_ygt@?vkjO&7nr=1u|MvrCJaR=>^lF>u(D?+Bhu6kC$
zjtcLM6oGm-&&s8j)^*ZF@~(OHbe5$am+esKgV85XOeZz`N4XD2^5OY8^L4K1C&k(;
zDCEq1?EztO-C%!QUqs9!R_+NgOtAk)V$aNNG9~q>oF=zdo_PAMr~H$pwOZ}|N<QFw
z=&6Rw)84PQNDX~;z3J_K_w!%BKJ>o(p9YrmkmYJaFm_fmAmxf=)t!{fcm+cz6#s9a
zd$AqrTdT7}jW{9}^YeGig~lbK!`Sd}@uLyEbY)uxF!1gm14xd`72v@d4Iw_#NI7R=
z$g7*j`$9a%;T^0Z6ku|TcQ%z-EZt8Yq&rv(JQ_#5JCTq(CEtK0rz+Gn+_2`i+6@0Z
zZAxccQ-WzCgsw*R`<+~Rf~h-DQb`TZ&XJuJm|XCW2iQ&E0ngsf;2^S?oiApqpVmi<
z^Nabe{*|`Xe<3+V)lbdqsHFU4r${XSWT(h7|753q&uH;vrvv&xDPsVvR4g<G9}4oj
z9&f~OoOSR17kEqc9&hfiKHqFU_CNxKyDAkxrC6$LhDEh&;Zs)As-jkzfdyNG%qfw~
zs%@1(Y4Ct%@YR58nNwj3kgma?rSx!`Y|DOWD4Z2@ovUqB*$=@aS0j(>DWs~#wU5CS
z^4m<JU0_2}OS{+dXoDkB4wf$FfhTnZleCgO+zZjuCl6w_EDx1ING;0uQ>H_P#sj4W
z&;rb)c%FN~G>mkZa@5R8k=exo<ZFu;m>meVqx^)fr&?wqY-hUW&<V7Db_MQuLmnXO
zrQ#WU62#<4<XnCb5V%9E0H4gj|GmBEAWTgr2+2vF;*qSBLRN)`#$>tp5yd)8njurb
zS!xz>Efhj6upO(Oe6&=Y4W7R^tyO3JL#K!#NzEaFq8JcyvUo))Yef&e1+rS<daARf
zc2hMJjXX@jAm{76n@oz(mNDyH&4?ae%#Z{JXFq&R&(E+%IHM*Mb`iigF1;uR;YHb@
zUVxKj25SIoq{mIN-3f|<yqm2?$CG6#-xbY;Xwgw-K1&t?>IK4yWKC&uh)t+&@w0^L
z-|oWf<^gKXFd2QAyTcqY!N)WfFfqqfpZvB+ywKCT<4TL;{29Y%Uv~N^8AQ)gOvq$;
z0pnp&N!CTz8kpbhI#heLU+B%mI(o&NEDxu2;nOi)HmFzakuYA)i40cV45Hd(;mTXk
zc`pf>g@43rl?h|9`AsQcaa`#ffUgL>L6gH+A&o;92F-u!kOyUI_?EvC_6rJa(ZiJg
z&Wk-xHVDS7lO-dO3di`4GEOjige?S_By9VWdLb-%IicGWGKd;0I~Eak+9ohEFBI_X
z1StOPExc`k0Oa8UVN%Yd)qA{io6ObhrFlTDWef*L=x+}jlrGU&5vHCL7C1OfQb;Fg
zC^@>i=#fq59j8)mXKX@sOHCakLeD&C+}o7wE<H_&=}|byMGlhRFqFUxCjS)br9f@E
zzIvo~O*p%H=(C7x$dw3zl>him8L?`x?jWgMemg@%sc=?OPf_}bfb?WCz3})FLhGkK
zmuni{^^uhQ@Ej=2r0_|r*YKxz-}}muUJMKk2vA!h(+%~?7t6l!HLYg7y0N0OzjUfN
zfDeWggljOt>JMlMp{BDuPg_9U0#z<+caizAO;GSY4TugW7PncR4Bu?4ZeuV#8fOnV
z$zwcwm;Z<rw;$wp03wHA4rIY!Zvh8qy#;*WJoOgvtEa*J7f-`q{LbSc_CNgqFcMF9
zc-|j?U()Foq24V6b`zSgcLHZbByq!aZ`UF;utWEuSa8eWOScT37;|C#Z{;gym_ZLV
zn!0Eh)Wc*_HdKVB4LD^%s{`Lr2Od<*x(keIEjsAiN^f)3^Wm8S<^f-(j9%{YQU&^e
zgB*ch0q1gYezBDLzl;N_!8@cx%sy^|Wgto2!t~=ona3O!jyreKA*HHKGa9l=>V1QQ
z%lfTR85iljN#oL)@6Pyk3j2k|Rq}q|5}UzPEwCQRs;qeD7-w0p_^k(uwt){jpDhnW
zqG(^@g-_$r*#$CK_WG<-h7sY!Tp%-Wr!3P2*6~g*0Tw=6c6xWZrh5)55?XKm)+-Bs
z%bk>s!IHAO$<&+Qj&Qe77poQDJ32j}gH<v+>(S<sF-T<Im!O7e+7w1&+4aCQ!Q;v@
zh?VMry?rDIiFyMlSb^ZKFn*c>G2~q_qZUhGQTi^-<P0I<4OwIei6$$b^Mbls>|=eY
zZ8OxGuCDR~LLVZFUl_FGQax~Rg7F4>(%YpuuZU@d*9P*YA-4;I>k4UILj<p%$atMr
zh#Iyct&kLMoR&tAGO?4mutct$;<vsj5d!JmNhtPBWQg={T^+PcE{k&{>nW1-9Uf6|
zd|@gb^sov=nkTR1*yQ_bm>xPpHkY3uJ~PVXcy@H$V~A?iqIICrYJ51=D)?`WhI|eT
zfH3zAPfn47kIGSOesKsjOmA~iQ9Ja&v0`)iK;(r(4}E%=Zb$eOX|ABJIXi<zr8-&3
znOJ6_8f;s~N<=T*v=~<zZ@g-N8=U$nH@UmGE>5^A+HcwE6;0aaJSi~wnsT|uiSGx&
zSi`(LIUD`7-hYP}f>0Chqc$6Ax<q`5#qpjFA@J!DO3N18hi^Q_u!`y>dFOZ-Rk3l(
zz^Y@&D%dq5IUs_Qci_iswy*+eJ%Xx>lV*w|a`^R4on3S@jK9+fN8!s7E<|paL%54<
z^Q436A#+&B=A$uKDgiCWk!XhTPEIX)c}uo|Mi|UsSg4J}9>RZ|yzOW@oSn4P2@L9~
zJ7^rxiozuUd3i?2aRpg3EgV)Ranfh-IiJ$<%<o3HSCc^FFwux;6G)>S;T)y8WsFd+
zMRqexa*MSKDUJ1JHqzOsKdl^U8X$eMon~N!Pj#4Z-?_!Ggs7`Fz3G9ir0&!&^xjNV
zAowSu0@8&tr8XkccRj<sdrRL6BPgCU!rhVF-^&=UG#5xUx}ch1@g6^rkl1XE*zQIv
zV#-?G@(|1v??dnl4MDrK=~VzjX{YBL+s!uyL=T1WhHrq3Sb2QX5oD5nKQvWfh915T
z)yjZw$v7#TetE6=a}=BJwVU!sB_`C-G}kq49^%CUwh#F{2kyANFFK6s3bO9%gqJ{`
zDRCpCXho&<xZqXc+((}qesiIDYeIF)@)Rlnx+0vMA5Ebaqw+K261Ras$yv(gm2%R7
zy-Hg452!xWPystb?EJ74K*>c?yDP%T2RQd4V=wj{FEr;|3VK8i;1M}&a*PdNnp0N&
zMBqbAKqv!<*#S~tD14@%AF}Y_21tbkk!pfk)ZuBBtY?~$(%GChkbb?o()f6w(i;tN
zJzKI%8ARVJGztWKV@FxK%+tlP%y9cqrRJudMN?LHNYgfT_R@V1;>x}gA}OO=a3Dd*
zm5U_xXp~gj&AMZ~rsa8ky}7)9;Ko~j+<ZcnnU7Ej`CW3g0zb!GRW+`5bjV-nj8Kp!
z+c4(PD%xd%PXlKI2H_{U7_a)6lsboj4j5=1K*LzcVquzxqCrF9W9d`4{PVl`P^Zi#
zL|=%oeP9wp?~%2Mb)nXC=n+B6sgc2d<CNd7Z{sMeEd_QAN<%f!l=>v_uVs>~5>-3E
z+@*A0DYI*JoW$Kd%EMvc@nm*Xz>JTjk}=IQ#;r!kBjNgbnp#I{P_GElv8|K6lNK)w
zcXLZwtig<0jnQU~DFlmNSpmU3dU&S`8g^t3z&L=u)yP$WGFlmn<Gv7np;3hO0GSA9
zXS7Q7Y<f(zYq~c@76l{cais_0#a0QvTXd1%I}Rivu~$wm(IC##<B=uwMl@otqfM`B
z960&pEDk9ho5qw8zy1u@iKqoB?LyfAPHI(-I_hZJ8~|I16!9_He6Tf-Loyz)M_vP$
z{Oozf*`+DTK-+0N8FB@B9oogUzR2z~US?1-uh73~w`rc>ivs-!JyK+VOh5nMo;=^8
z#yPwkaMK(o-tM#h;5lT>MwZr7Ajcb!Hzd7OMvirF=L8iKQL=V1J5qe*1Xq*wD|rdS
zksWdUzt>?Y=>#)M9(d4lz2eggppzgNKqGwAUDW%Lql{6Ywplpz34d~?in$i;?dYXv
zixh29i2{jAi1{CKzfguuvyJ#}Fyqf3-6jITb2^%UZ0JwsP7D1-P_0ULp<+5GR%X++
zdGF1;aXLknhyKaJ(A6R~6pc}gQFsv`4NQn|4&%%@+~m;$2W0TbwmbfNN*LFo^8vpm
zvC1{fXBy;N6)cE%2xItR@8bB4f05Rxp6>rHUn8y}R3HB}SEF>(Q=UeYhl#Jt>&ss^
zRyJYz+s%hx?rv|c{vG~Cw-!9q-Ng-YDUhP!5+-Rq12u!?<}XfJ<AYaV8=eSyOThdj
zvnPUy({tlWWG30JS+yX=thsWo0n86H5^tt^Pbj7mkt%#&*As?&ICQzzM$N4qk+37G
z?Dhyh@K`*9lB)0DLXXwG!OIT%s36}g4o3+W*I@A)H*e{bN97Kz7AMx+av7)_i1w^X
zu(yzP(SB-1%e8}dpp7ntCYg}boM_z>AU!{EcbK6iTsrJIRPS(-Ky<=iN4qiP)&@*Z
zO2fvCP~-&}MF_^Wxv4wp0XjsmfJiV0uO*iMp<+56nJPI4Af`T_>AbQw%}Mw-n`=^c
zhKsCY!8WSYFC_y-#=FosS!z@6P40YBJ*9Z5G*-R*<Tem@FpJR7S2ve;zpbyYkWm><
zrpO}H-`_hx7NIQT93vH}oi=XDuVI=h&cA|OP|lQE|B~+SBb|meFp>-%Snd_vV_MQ!
zBeEZyxfKGf>!Yo!N42~P7G?Y>@7IIH0VHk;^5QzBU>;6!mKEuj?YnAg4~o|BeM60D
zDNnmP==H)}<5DoFJRbU<vo1N~>Zf;?A4nr(NIrk2&1iK>kIgAI%pg%*3#rOLk;OZR
zE=Rj}-}k=z!`*j1{BQ?J>b<wtJ#~=YDB2TJqCSmDqVkYP+YiT(q~t&=g@&iVsUdn8
zo2ZsW8onc0cj7`H9&3r58hF9^Xqfj+w5XrvmX*v_r$`*ZLzn+Om%Eaf5=(2-FBv7>
zW4_rDkQY~arqit#iEO=)hSfL@$aVC$ktwf5{{p4~iUR|B3%!bzooe^O7NJB2-+lp4
z>QK&L$4y~d%r=c;f7SpyD_Sa2d>P0f2TH5;;=N8a`>7$?DXCO)o;=?sudKUendTg<
z5oto_3#Po^H)V%kR7-XQ>M4`sDH4FEWvg1N{<S=T7vZE!{49u<@v}ge=lm5qiAJ-Y
zsD+K}E^OffnPBewsqUdcrR;A-v8sb+ttxuI>E4u;NZ+Y^Bd(^xJfA{9fi1D7N-eP7
znuH6+N}j<ux11wG_4;It<f>3<qsD2!pE7I#FUn2=n$T@5?PC4fByPKWZJ+8o-ZG=9
z5Q5yelws9Xo<KjvtNg*j;ozU^@l_y=%~&ES3z%>IWvM+-Lw=V{XXX7=gwXcaH&pY>
zl>>GrC$pIubhuus&w$~_)6~GX+E$4BAj`kYA7wn&#&wjafwnki%OVqjXrW>o{$pG?
z&*S9rFRd6K`#W6t6E{7@g>y7ClVhtgpvmTde510pZ!d>|?bQHE31kJ>rYMAdqE#%e
zwTL9*tdcZ<4dh^2IZ`%2npj&~nRh{{Vaw%z7bn@(3#${cX%*9EXDeVu2R)HEY&(89
zS{0@xad~i)v!q<jLdi|29wq8VT`ru9N>%Q@&0SStw4lc%Or?%FbMNF&mlsG6fZeNw
zkXwlz>0Be`-2{EK5H!2gq#ALSyVv2HmH^*`>f5a}7u?Vh`no#gQ;6cO#cTj|L+1Bn
zVthg!XN0y?$2sZ6jU>on_BT)VPWyF$^k!|;tQv%XR5A)}sBY3Sdv1f$08CONoE(9h
zObolb`89yWxO46ogcv_rA9&yBY_c(XS&D37KG;dD%4o?r6tE|dJQwNUL;1y`*%r8E
zeSTS5pI@@Vh~>K*FJ{nN7m@@I%M{!;TOk7x>P{*bgJ@dAG}ql(6G1{jUw$~{p3a|F
z?yU`wx~I7W0dLxAYM8o{g<`&{*%{J1)#pV8QfDo$omTD>;uo4MK}{a-Rvadn9!9c*
z7ekxYDvw@)Y*Z+efX*1e#dtB0t5&|uZ+A5>n8<o4`m_wxBPEoQA6vb@po_+0WJZUo
zNsoq-5^hqMBKoM0;4^C1$Y_|_KzWc{d4KR;E^Vfr?C%W@3@Hm`FY{ny!}}4bO;kbk
zX=2}@`eT|n5N&dHbPL+1A#8QiLpWxtE0-s4!kq~9hM?|a)P!d}D3s>(?OnV-yqHdD
zdqf%%3Vbje$yN)0p5gF0|HlI|m8xr~7VS2{WdaY&hz`1Mu@!sIJtvBD>3vuBDH$UX
z53<QAWWRE<ie^1u^mPee+eX%u5Pmo<z@$E=F?dnwTD&b|jTx%K_Kp$y6D+YV=25~^
zjZvLlY}j;#81o<o#iD#gpJYR=W~)9S9~18uttD;%^#Z<{UZfO9i=>8@f{$$=N<6Bt
zLEz$T2by_DhY&-wgBR7-vm~_6`7DVREA-~4i7<)St9L*`mkpoZeeZxq*sb>N5OAiZ
z=#8|YaivL+|J&#tjGC+U+d|m|nZPJzvqPGRWc9?dvhKDY;8;c5^q`waTG1^9222kN
z8evi0{HkK3Hh{VTWWd-Y_e|RLzw#kYzu`t)^-8gP+k1qg@%A3!YrMTjgz#<e5gx<a
zdpviK;O#xaXLx&$m*6@mSb=hr7)=&Pi`BRm0wgg@VGBU2X&JMydcTLdUFoE@OS=zD
zG*2*Lvs);}1=H67-8mmG-(jb*zRDR3`YghK)B#xCbgr9YMz@kL_zA|bQ&DxkLXm3-
z+BNEI>m?lGR1_tBK$+2OHjm&p`)h2c)-#P4HJF~ny)Ax#b?F!|^%Ipyk(iIA?a+)C
zft*56pR{;?hE!$SpKoBjf(nf@WQ~*yb`)uh5Wil6qF8QckJecT!MS+=x@XgRO}i5_
zpg>#PgYz51G|FVOX{EOSZ1a1BZpnvgBcJvcAPT3*aaAu>1E@h)Z7!lqn;?KE4v?Er
zlUyX2p5qDLA5q-y%VvFfcX#<43IM)-^|C)W(eSL~;0gSUm^xJ@zs3qr=>XVNrWmxO
zRftMTu2^u-k*-k&NZ+P>M%WF+1y}Rx*xwaESOUbMBkTJfvR<QH88og1ehNpVuqGC|
z+gr-YNY4`adq77^?YF_7{fW-D)4!PhJG;sy|6AQ=+Yh9Df}8P%*i5vIs5lq0E#SkL
z(O|YbN1w)6f4{#k4o{CDBca^OqE`nrm;_Hhi>;Tkl@y2&yojmBQm2er9_kQE5XLH#
zOHUz}2SyMS!+dvldpAP$G9kAz*CK&^k9Zgt9KGv`85ij)!M1>|M6sp9klQHIlNB~P
z;kdhfcba(;ERP5rosQ5>TW<y$;vs$smCBeN384>X=Wju`u;rVYxwMMSZoYU0)@6Zl
z(1B}oRp~%AEH9)hcxAeXOks!w6D})sc11L5=&Pv(@hBMT`VSZG2<cAHEDi&w^cNts
zg_m)09JPT)si+uV{5YCNAQ&~{d{e>&1;>Ybk3^p^appc&GZJ%Bc&nR$w(km;eLj<3
z^AQ}3zc_21XQIb25f-W#S~`rk#Dy45CpnEAik<1D`oRZAe7!y?r2uj23(KV1<sV+C
zbdWzUUBPG9vLTaJ*dD^y+eWjS!_vxx6F7vy0D7e5AXzCx&s?Q6#F9(>hA5SRj2a%Y
zB1X~H#NF843oov;#kA+fCpbp9iOgjbwHD%9eJHL_x`cwjK9$oOn4GeqLhvt=#kfcV
zmQ{%$>(i+L#6#V8V>p_ht~dejP!6!Z$938TT(?<8Ncd50<(n`+^s}nrHZS3X+%06g
zGTT#964!WsfDJpts-}nyzfO~h!v_*L^y%{<0z2MTrw}JwyyN`sY!Ym}X{sudG`3zO
z{dKSTOu!ou_hOhUeZ{-;1<Q0v#fgF|xoT_};LlJ!77KzC&#4s-AL??vU4v+-!xsC-
z+GO?Fek5%sDi`kH&qa75d2=UFFYuMb89kj%&(|nJi84iWZCo<HRD3@|JT6k197H2u
zEY5p~(AC#Djq;<$ww-b25i`<{U=hxR9+fQj?w8p>uNGL?Wp5LCbS<2}`T*ong#enO
zXF(x5;X*u?p&Qg?=!hDTWD=f8<bSyjC`QJKN{R<GCTE1q_D8@F>TgUWD;n`-AsrL-
z5h`G)@4Nud5|+&s*Fr5qid2G?wNNy)3!r;Nab}S{IlOwfhY4k%<Ts&Iw@qas7lTeY
zHNkAlQ-5RH@BTqWDqGqn_i1S{*<xdLZeZV`jDcD9#q#mMk)D?7LqF-V4mEIxK3Srm
zBl*Mi!8X>Hwz0vL71=(>q`kD99zFhUf_92%OjpLpx=3x1D(_y%JH>z78?gS<P$7Aw
zU%FHedh%dka7|<EWxk^Kj<_4w3U+HOGf-0>)GX2$G<QQIy8-DwgUy%wn{N-8WZqtw
zmmS~+W-U@P(&A+VO4U{9&}{zwKZ3NLRBCyNfYz+HYm81TJChzIn7ZqX$+-uaZp@5&
zVbfD2Z8Gl=uKNlCvqb8x`VeXWb;ELXx<8m6?7jT<jgIJ{@k@fPt9=T9ZsWDeD=eo%
z2LEkK?c_Pk)Mvvt5D^m9uA6m-EGmejJzx3}E&CgDby{AdUOul`a->v7##u1-S|mn%
zlAeChUX)PbOVdd+pXVyDSHTPEz^!ZHxdK<;!IrdvienbsW`$p@ICZa>=*%nJs-*c;
zd@}2<p#d+}B6qtiaCtLiN2#con_@j%{1{0l`!BR}m;sDu5WWBki}3D`+~%b*n>;1S
zGBROA1+BQ!GH_AfL2vSAg3#jpTQJ+BkY$)^(ceYtV~9%A8+7B<%G40e52YJ&At2_k
zQtN}oH{x9$^MT_$BrURO_Key2!5W6a34Hh4P8U$2Ca7Lgv+9vPo9{8*B~<x~i2LFQ
zG&1LwU@UE`8xu^A4}?1&AtV!uwE37uQ_j7L;MhEwTgw)ozXbH>g$fCA0?ZXrUTW%X
z5+Z|xMbo~ZBy>>uQPmyv?0l9|dcglt$n*ScIy<6|cWQ#CHw2K`RN5*#VF4t<njzjV
zbjM=!&m`jI&6vj9yUlp>^W$f@^D%n%EtdKmiBptCSF=je1;NHC2Xjlma~Xk4%~PL~
zXYA+dJuqUqN)Ae_nTt*m<J}-bYDRyVjy6pj7zZW5BAdaN>OzOD&Q&NLwQ789tZ8K{
zT%Bi5vkA}(Oq2BM<=xfg$Ey$Phs~F-NE5iBpWog~`T23b!M%lPpWeZ1#%MrpIP;Uw
z5NzO~7S7fqUI()VDnT}AKiHt8kjhKj33sjl`xTL*E?CKe&VTq^l3e<6%WMGd!?TbW
z|H=SmaI2hIEHci=^GZt#v)PdG%Xl-AST?K|z3R)_a2s>Tf^dt{j>*^hx~90aU~8ey
zX~Tu@I^Z}W^yj~?D}vO9+9r9Yja($p(}p|bOto`da85wIp&gtZE`|(QVA8$e1uD9#
zIJ==}#N=r4_9!qLnzq|DTunhlxY&fmmEe_DNV>?ZBjRG}eh*1@F*&Zv=TjX7ra)+)
z!!(<`&I?SMrmE(3(A+o|IXQm5w&MDm2|kR^H-~h&C_(33IJB5CG-5P@yQQ*Cc{<=H
zJlg&6eeXl>fBw(j$;r;!@p!Fl+`avM30gGG|A_Tk{`k7iIO1%WK{AdcjctG6V-1b1
zS*U7VPWWTtu*}|AU}8b3+xT7Je|HCyjzA$#fi$z8WTm*$YH9L^QwXF`vA9g&#q*vg
zO#`%Nj1fUyIZ2>!IO4tSEz;3X(_mr({gBS#hZL%jiWqt{GxWI>Z=GD0%9D`G5$l~v
zW!b3VXbDn~D|2&ayL%I+PZKtKqBKWVAVS`hQ|9hy+TdGYJ<6A#wH^bhIK(m(6S&n3
z#Z=AAJ_uWIaboGTgDGe?0ZGoMbqe%Aj3m<ZG!p`j@Mcas7?iSr!t0e6P`H=uMrct%
z;dN9{SeD9zWtePCpvPt2=OK4_LhN*@9!@xihzC*_aX+~Lx!0%j`yKr>p=`$&QVm46
z7PMhCF)poHoLu^tVwD>}Jt&UcK$qqDw2eb-)MrO;%i(bL69SXlP3mbUz2b+FC$Ge{
z8lsQThb{XsLM=xSJT)5CS;%J?wBpC6f!Gpjn!cmmtD<U%5R^LAiJZx~p`Z;zy-c#D
z;hxl8BoMN5K>|(c3`r)<ccUs4sNN|OiD{^B#MZmNbZ-W)H?sMDEvAedI2hWlQYQsS
z4>LX<2?G#>!&xuZx&o;)Q67|YG&+c?^pftR<{>QAS8&Ry{!E?$))B|-!~@ryAe74L
zWUHq07wdi_;mC3F0mhyv+im*{r+W}on9{E%tWa7-87zf5;oWr^tki1HX&#z5Ho8^t
zXg8JsTq~5~R&H{d{3DVw9vTiE&mLTyE``+KV5yUNH+(zU<v;Rlupe-12#`{8yQ@GK
z5LF<){|^@3ZUYgJIb;PsItfs%Rg`)((o(E&M+dEQY=n^Sp{s>eKhVSJ%9c)gfOezX
zL!C=ejxDu&9*9l>Ey40*TwxSBmC~iA(_chc*58vz*Z>D2-BgSTi!0rgX#y}5vyvHK
zXUeIY1bb+zNf}A1m?Ae&>SjXS#^v5PR#32*W__gj=9qTfq#sNmUyNcVI*;tq&nYyD
zpg4g>aBX?6>w&>%N4#>r))>WlxRN+H#bm%S1@9nM)QJrr8<1lDO~`fb-p?Re=XZvW
z54Z0w|GK&O+NFsXWughNOB0`f`dAWlgvcS*1n<Sn1(UGE8Zt|4Pdq_frCY#jy}N)n
z7`$IgKUzMm0BI<Rz{nY<$dfxfI>KQOPY&qJG-uhq(664_0_G|5v<xwwuGrHm1xTI!
zD9()B@DQmP$na^{RQO2!?*%r^hZ35Eu0~D5di@B0!mkf^>j#`Ip=~FtR9Q<abSCMl
zv020nH{mZZSwgt0;K8=S)z7|8euSjx^m$j_pZRiB%}@)dL9>;d5UcFqj>H+U$_}oL
zN?9$J=XS1I*wS<3L|mDwG;_^8m0)^No&d}|yl_f;aXAAb-qj3LUWu3jO4O33l`T67
z)RmxJft;m9Oi_xi-RH-?@~{o+02xx0p!#4Th)H+p+%It_K)JJ#)V}N06cY>GBW>%j
zQsTs1pP!xl#E9ww8!-PS+H}!2nO*+a`@f`i%68(0mscWcDV@~lr;%rF#kceZOi&AF
zqAA>xkh+FW{)YOY(Qd%>{jIa+ccs@Y=P-|9#Ogz*gWUhja(!{iz3aP8T21FHq(LR2
z!9gi{Q(6khHZd5(90FtjOs2o}{*M&+CW|G`x)WzF3R@1td#0FeL~Odg`($ou5(^A1
zA$bN2x0_}IO-_K+S?iHpM8&%Dq_M52fo)6DRx@$idg&$7`@C!)f6l(~8-P6>9SZc4
zmh*|-rnEZMZnH!?cAt|R5bPy#u7IaP_<*HHDrS=OyaL;FVga(B-+Ven$X$a1lis$v
z*!1F&;iKPljp6GuOx;1h%!CKdvKe_>!_-~4h?7!mU_LnQQiMA(PwwXk!%7l^!uJtv
z>U+E(3B~{8$;t4i$rv_QrU0XSdI(J@+~-m0W%BmLt6u5}nQpj7QBWwfp1cL?i08tl
z*_|h<1xxDHBXTRu7&{ux(ubFg^(fVKI(vIkiE(KXGFa2c;ez#~ps|nBufEiSHNjWc
z2*&2d^>j&=<4X<cJ2{t1DYIN%%$X0b<P*~So1OF(m8OnwEikf%se8>}oF1BYC_F8V
zGI{KzBSTziF!|g9DnT}s8@iko^QmQu@?smg=A3tkR8u}$tj>|gu~ha_>F;`9oM<)#
zXZE<cO(R@&(pbcAm}mV04&*Sg)WdJXZN}geApQVW91rZ+jUSS8@&#laBA1Ie&Gzuc
zZnlR9cC$VFuAA-QZQX2tg)=@De{>AdCZVvdv?_(=d{AL+1+eKVqcW_J-s@gx84OIL
z1azDqho~s)j4C)^Lz2*6G_Act_YBla{lGTXg>y-=YR7}6gAQ(xFw2x>ju$|xkGH-5
z0~$X&?~#4v!Pa~D^7U@>x%Wp|4KDt*2NNB=xsw#s4$0JWfqPG-Q+evHry@D?mcUyq
zJ#Pp1!lxHo0!~2Ay}Zzt7&4)=otXRZceZD8*>&3b^VYLSj7Nx-LTPre#ffqpRXDx8
zc~L%#j_*o?gbKdd)i|K?i?=LE0StA~uy5J_u%;;JL6xi>9_9tw=}qm)qGS$D<yK%a
zT)_VWe~feW4eL>mj*QJtLL><#NH%puu7>}{X75lVR^4<r)+eciM5&X0C~!S#oIEGL
zCrl*n7a;qTB96*43VKwPrH<Cr7}G!K+#?C5$H6no(<sfjK4gpa1WWhUsecHN-yeHO
z%*qzhY-rcUL%T<q2m^zE$kaY$f3RZ}RZx0uc7`ZNR(_tH&EahQ77nZ1V6*dqsS9zu
zze|-ioa>f?+yMG|4b^N<Zb<SAk+<vHo6o&J98}m=xsMteiiPRMLI>q{xoTkGag6Cw
z@8jcgf{rxz5sTCW>#1f4kknL{FoPJS20b}AW$t~-=+lr!Qb=G|kKzS#rZm6Bk~;`9
z1k^(Y)Ga02F5fi8wkFhW!AWbbB=q|2OWC6{7x_I{UhOUA86BxDJrsy^pkQ|gr)nXY
zin1A*2Vo=oz?Nr!f@q<@Gxk#-<t~HKI5bzLl64OgYBJ+^j10F#)UY1a%)nDUHGXXb
z5s4@)LPbZq4a`>x>IKW|uDg9&426Rp^U<jQNU*$|jp~W!{aqC;02PGhE9x)mPU&{C
zPhQB^c97zD-ohU@APuAH@$4^yI-FA|m5L?^?lWXwu++CwoWTDKqqfuBtXxC`ce8hY
zeBc@v*cwyl#};>dBBp!eLj$dI>G&PWmcILYI5iX1x_C9Caa$ps{F?500mO^aH!Rq^
zK{{1T1-VxvJVwc#aN)$GT(5A6gg7)eF<#{mAu7O|38LEqr`jM<3QnzO_N4K*iBT=E
z)~4Wf$E)lhRAMk4&f&X^bb#}-!l#+5S+wgDtX73mp262UmFmDY#%Sh{f8Wip<8V~r
zgs_Rw$RohhRI#Yy!NZj(!9M0@Gnv1ofI>H8{6}vnEHp#DtULmGqGHz&B};cDnTQ|v
zUtq?&I{LD9b~-~1(ey;Fr4@ZS9i79&<N{SickPe8MlDwE4zw_La<UjN+S<+K6x5QD
z(IXy>?<Q$4o`*yTf6v1}XYtJ<gr;=yO4NR#*)3>KsL$nS;q1}^u40Sn5H--64Z53t
zsc^P|2Oj<fiI<mt+2Gi~lsBF;&2k}rynX!ndb4}*!|Q{+7tdcDJb!i29~``Rez1AA
zKRBqWKac_cFY+Y1MJx&VHrU=NWA~flT@BMNpwKfuUdZ@@-=hI8GI{d3l71r@6-rH}
z8$SlTrRH#9ec`^}ReBI<BeqBS;JX??9h^u!w1qy)`d`AtJz4VC<&XV#p|%VvK6GGP
z&||n{Ls^avSt^sRaj7r@>Lzq%JUy_Ks7oqrmfcBFy^DJIAwoCIIo)zX=a)nSw=Q-v
zWeKLwPvj6ksA9P|na?JS2Wzs9PjpQ4fLNS8i_J0quDEtw#zug>8}5FE2BTnLy1-q=
zhMK!@F;@Wr*%|?{2P;7BGx!o}aiO}!HX6nmqCJT)fqh_U3KM{u>lMXYIw0b|9F$TK
z>eFQBbOescY4+00h;eW$TST&QrPLnz%L~h-FdVW=Wt=D`2`Ju#3TGn(qu(Q&pRSD7
zl<J2A@pqsL^FxX9$Q*@D5=<nHxIz8yO2tG&P$9^Kott-=qL%z)VHl~)o+;!zIU<^U
zr0#();lv>BwGM(RCZH2;N1?}c8ofyFz9uNUt=%u$(_&f~67nNX%L^`l;>L=S@{W8V
zmUMMVI|AljawP}^tWmZ&IV?ypD4yGMg1e;e#C&)(p_7p(G~lJ2j^wpAx7<@*p(F-^
z?E;lrlovxTErpE+u}JRT5bkj9HI?}4uot^ZGF@u&h%iucPQI;&H<#D9pQlo`t}V5#
zBH#^b4P~D&TZ1?*P*PgQBM`_h^>9s)tH+ZhSRNM%miJh81$_Y>uC`ZhTA(c{R9H@7
z`<^f93APe6M&cn5BqkDLP5Md*?R5@j>O<zwkdtFk>?oZ{4Rq$7suX8MWK*T0QUPFk
zRnw1+Q%+hF#RsW@^X)S^LP8KPM(BGbs8XX4q04@8A4(QFn%6>4x6e6_?n)}6d4I8a
zpikSEtNVLo=rokd6ORo=+;1+2HCyK_RWb4g9IB^T)IB9oYYnvqwkm5Bi_qmuOc3}E
zcmq^1WIh>O)DEb~2JHyb>1@&z)ro`|rk9iN0hM2@FEHKpo~}TN0xYID5~rtgI}y{B
z(8qVs`t<T1W{UN4^KXw3a;`3~*Ne@E&DF0PY98C23aCDxAt8!lb~cG3DL=*%h7OK8
zzB7T+cY0h2*0-`^a0(JAb&lY#;?!!auThdlBl#61`N(Gtg-p{s|J|xv-6Hms2RNw4
zIWp2=0`OpPh!}Zd*>Oykz5;_B3}BS8F;YCr>~{{;U}FoRG$*1L&)}hGFJgq8NR(UK
zi`VC`nqC}vcdkf!6huDeP#(GMt}q#Oc1e?t3LfOHauFzZvf_7Sn7T_Kg;0h}MBug>
z18o3x!&6)-S<b(MCsnx3DUG619N||lno^6+nQ@?lE>xQ)m_Dn}l_6fc#>^U~?zB{_
zKVdV$h3cVPpJY;__+frY;0sUYCvRbrKSX_`uyK698x{2qW%)-@y<IobpHHVUcpUcr
z36l54_XNcgpgH!GHviPak^Ox)mk-SVY_bKb-#x2kH_p9bba=~mx&>sQ=0Wq0g_xrF
zKs{+CL|sWI=&S=Fadfbhc0OP7=ADk1(ZTj`(m^f@Vbwy`&|E73Z7)uJhCPp$k$V$6
zqgYAkLZJLC)c&qNwZ-&^+{T!+4+GROsOm_m$IERS=c<@y*h1;2Ap1;LxzR45ou1~p
z1HnnfZ+zB$hl)k4JLtu+-@_=5l-)Ss{a&}hcK6Zk8n`ixRWjO4UoqMjjpOj|XFUD~
zR42xGP*VYPVp_8roeF@yNVGSQ(THzc374E?<5>&LRLS?@QawuE3t#^_iMAx61;y=7
zBINF*ZuatesiO%P0(@R?H@V+tJ6%uD%-8ye$}Vdu^q_*UXn*AL*ip^b*$C<zI19v-
z?E7NZKurq=MSo+{Q6Z^2JQh0I^zI~19I&b`lMEbK5z44R+0{XBAp&D&!4HWqvY&cp
z;1I=AWVi^0W1U{13#hx-e>vN~f4J<wQt<HT@&*k3!`<!m_2%w1l(HX@n*GaWvUr31
zG5tQkt8d4f%a5D8$^6YPvFF7_9U|jZta)nCD}2?(_yVVpho8;G$=J~$&FuMdG&?~m
zwDSeU7=&w0Osb^-56LzS9!3O?{2Wt|5AnQLlt-~<9e;PP@E-Cay}VaoP^7|+g${na
zn1Me>>MrPNt<0vy<js@$)CC$5C6Qo&G%ourRIndH1B{O*5xzib93I7;twA7pz<ETz
zxs{q8xLud)w5rSXnsvDXB}Yp*ZQ?T!Urb4`+6}Hda6yscso^7}0-URpQ;Sy>6JJM(
z)g3g*7&eo^gaau#I4pvAlrqz2<s?%1YOpJPViDN{O(o*RNBoUb=N*#X!DY7_vYJ?w
z_0i_x?dHS7?H$Afg<Yoxn^Cie`i%O8P_~uIVm&^;fa<(VYqGZog<sTOhLhQoTCWDY
zDH(Z`UY3R=R^{0@!HnjlID5*&CtJMOL$gnHEv@<RjIN!SD}cHd=a*-%YA>)IZ)I|;
zM5v@Y0q?YLJ~Am$d6WmwaJ?;#f2;iGqj4vN8m8`r7yw^P$6HeR=*uXV<r{H*B}J*2
z4B@jKFst#gD>2Jpa_$Y<VqjSN@qz_$Q5-9!5~+3wm?PLzq3AO*gsANxf+Hv(5mSgw
zJr6QiGzqJC8qvLeIYaGX4A1>N>Uyq7)#OH;1L~+OG!gz(+r(azvT88yibM#<Ae^93
zrF?|cZuWLsVZjbvoL~}<7Uvgp9W7Oh?Gq2Vpi)tS7<F%;#4spA#6#I$>~-dn>nXjB
zxKQBU@sb(7t1Hcd(@=cz3}q}|>^*<}S|6wrF2xqU=uFCtI<JU=k|G|mpb29*3MYpM
zs@dFs7=HM$xxX*4MCZR3$grFnJU5;r<k|U+;0<6=)6jAjLeHq>C6VH)9D!Ny`aisU
z{qn`@{r>*Js~3a){_~fcKkV<lI@yWwC~|AxPVI>DGAV^<2d)9fA#l%PU=JXC2)AKb
zMhITs?&gbQ-sHr6hijAMV-5>}_;RY>|NC9NSU=~#?&@WCJ>}{p5#${bA)ddJX4#bm
zW6NjL1_bHmVL0&M9*-IldE6P#U+up-K(egkpXg1j@UK7?i6_I@pmwD-)p4b`hVxP1
zcc;a+k<r|yt#846zj(U7uwKWdV-FQ4tOeek&aMNR*qox2lHqFvJ1u5F7Fd{)VF&f%
z3|Y7ZGF13tu6{Bf%Mm~ZUQciOzO#At9wddF50bIYPT+TpI)S@psr-KM!(gy?aPVU9
z;Pv479`-?h105+jj&I8c<WSgQ{w<*7`0CdyFpmBpRf)14l%BM0D_KGbsc<~wD$bjo
z`R4BG>o2pL4?C>;2j?F<RA)C=56g$U#}5xXUoNk1^mdvx*h`M*JI8;UUf=$0^l(iW
zmA*TN2z}Xk{|Q{J(m`HcU;ljh;jcTVn=gDkb##zme$o#qz24oS4AdMC*A-IaVKMnh
z+|cLuABs=lOBFu0Wm=JXY=_n(%*w3y>n(ClTwQN^A8v2%AM(TbXnv|a$QI)7o;rR3
z$H?j9hj|EuzNehh;rOSWqt$$2#ipA*ox<lSSlxd9e62Z<+8XD;TB{w8A6?&m_$x1V
z&MboB*W0U)y?^?i8O4qd_q8I~`&iFCf8%Sai0U0=wlVyfBP++lZ;m&Wtvq4Qc5C_g
z>JA(rHP>Q*um4&s&KasT?fmlL@}}RI4Mb%vRy&{V^{4M;v(n_LpZ3h+8wVGoJ>45F
zcHZ6IeLUIRe17<4XZ4NPw7mNF%?@t&BN~&xL+A8UrW@sYY7&HU>*LFtj}W<Vs`{XT
z!kf!4jF}pK{0RS;drcb`5)Z_lM*J0@H>3;vjqkESvCBBx_`0vFZ-<YcKFuHQgyg6F
z<IC$$qp#Nwqri0g-q9^G>E<CCStwV&pcX9u`;)KN`10X$czyNx<_i?u*!F4c^T+G!
z9mpF;i*jqkXZ`YcdG~OTr=G+jVC(hAtNTkhLaeXu{%z;9kLe{D;rJDv2W-&C*u2GE
z%deZw$L0WRYx0{;`_-U{xF?RK<IN|qLP*N=b~1k9L$K*E$Gzq4<K2giMnSA?>?4r@
ztp}eecO0Pa#PBEY4-qee%7U_kM_C_k2`3ZfZB9?j#<sKk4Tgj-+E{Lf%X6nki%9XA
z`C~_h@G(IE((y1)kv^I_(CFdRMP)hD_9BUYzV~wf)$>>QgVJ|&Mgfmwg!$r(8TlvU
zozX9sH#eJW(oNgK9D1fPHgfKO)i1#4Uv95IVi}h!Xf|ApNIr0{-)Ht_%jzL~ZDA|z
zCttaz`O%r`#}F`?a*E#pDZaV}Nxi*ON4DD}<5#g&Fe#^8iZlK*-#PykJNFX#f39vm
z3+e10+mN%HkDG5KMf4=oo{hJ1tVUvhQodre|8q-YpI!ZYr!t^#FRvdrJD!e3>%ap#
z;ZCu`w3<Ks@Gnfp^e@Z15C6jB?1vAW-Fm}mhD9#YDjr@weq4|$EFW&aGDG6d(b+|B
zgiI6t{tx><^fApiw2>ye_w37uuaAHHaC`T#`S$F~0j@vc`qS5651!qBefF{cf-Tp#
zmk-Y_f4=(TFPC>8(eUug<CmZD_ww$;FMqte`||6{&9g6m`1G~+?DKx_+4)}Y+5N-E
zKYqS>#0#H&`t*1s3jFNeDDgeoK7wSF*Y^)NaGyQiUw+;I`r)?^*SB9VUmu=*xW!6r
zzVQI~x~Rz5@MnB<qF|hUL*~mnQlVcy;_JQ{a>Np`?ZMk{dgtw#aWtr%d=%4kl6bU9
zhar91-lz9p>t#g4c$1pA%ymn7gG1F@baAI#`TK`2`-4vh-@dJXf%)*u{a2s?-z&P~
z@8CJMb9OpQN67^zb9(uB{g9e$l0K}iz}zUm*C}c)#?jOL!m9_oYl#G4(d`&0P(StX
z@xE^0rdB3Gd@z)#$32`AHy@X8(=$NH_zmeAD1CZ)gU?MZZ=vuDf(QH;(YyExtij2N
z2)xD4*X!#q{O9Y=2yR&QY>7^;)1+YlGdRrbjOG`!G4HuI`gnReWg|*!>>N&Uz#u<7
z-ieAu*t2{l4jg)>epvAw;(fn<xRu+HsEJeK_&EPqEg&7kcw85E<6S($s!x5u@%Q-k
zUx51j8{fP4^4~u{eEY$6>~Pr|{ILIO2Rq@f>c^$Pq0Q8RH$s6LrJ&zhOx|LYWG|+F
z5qXW3;Nl0JMb?)ys!O1)F&ZxI*mCnQzq`66w{>)P`}mavP-wP!z|8$^utP@^@rTdt
z14alqnUBk&53Vc$fciQEL*`&Ie%h7nHo9@yFKjo)_hT%;zVRK5;&=D|l97imw^k9r
zw4&SwSXFFW2-l)~{yelmMWB{Fe*<PN1|?e?R4II4iKFGrpkk4nXfZGJWK!R=+Z!11
z|4KBN!3LS;9<xm}=Hod)_$|QOlMk<k|9cil>ud(d!usfw$8eF_`pB;(n%OSS1BNX~
z?^fvhdmp}LaC3e68xGVXdX~I<1AUD;nvPRHV?PS9&86G=JpN5@0d<1cSUj_sWS`7p
zA=)keUDVd-W&9+cx#`{J-xNqLfP1$GwFYkZ!}#e)+%rM`8&)GwXC-aptiyuiXtixg
zmluZ?1Q5uMw-cZDO5`>XVEK6e6{Jdo=66nRxacFCL7SU<o!_GkSXz!HPb538W}`P!
zA4UebP^|m9?)t`1^}lDmutO{SyuKegwBx_*K%vfPF2CDvwkzLDj%vJlvAKWzve8FV
zJLx;h-0W?(FqeHK)_+4y-D_*|Nwt~JSmZaOpYL(qx>_93O2OOVud9314k1GqjUl|j
z2o9H)m!m*nAI9nEczp5`=tFcNfxr=Pd-t220u&?cxp7Ecfrqme4$yI%3O2_DpeNi;
z<GYY!ojalNQJmH%P{fqpbp0r>*=K`K0@92{TKz23D=wxeH^^d5zqiTj^~^p7`2nqc
z-kPT0eMih|i<ZPh7i;0J42}gEnL(Q~3LsS_C(=oWey6W$Ahuur0m^F?L=bwIY8cL7
zx|M3n{Gx)26zk>8jP2`%-B+wfoI6I3920$YASS%U@j+4F$d>4`TXG;MP{b>EB7G7F
z8_o-qp3PT__xUV|)5QmXF};EpUfv2$pUk+(nIik{joN-bfx6Kr!<)8XBGhVIAW#zH
z%x0w+s3m*<v9%khU7y`p-23Tn19n5%nWwrfMjj{edhK&xtXrlK$S+b*0`L(eMxySN
z+QEnvYv`-3{E<6|IsP^ErTC<UNF1fEG?T?zNB=k|ssl6#ZGn$UJf$UY3J5!f9vsJ>
zE=X8>ZHQ1!hDf{v%XK;~%*G?^dox2_Lj-D}sy~a*mK?z;2;L-M;u-w(`r9ScIl{-F
zWc-Y=X+c^ikjyIjZo_rWwT|h8%^XnBYGg^Hu?GL@o-V2r#Mus>)I-dh#)^{-oTV(*
zVWEOi;-Vavzm7(Jdl42HndugYbzLFIQWP2Q(P8N#a&fjp=b*2{QoT@)G+p`b*6GGF
zPq&YzqQYQFlNaBnSD$X-oqT<=`4zf{yHEYQPuG{9?{~hMqk>-Qombyhcmf#dFJE^)
z-EB74y2V_ZhmcW!)e)cWSbaOayt@AR7AbODvL>Hs@9v-8f99D0ZaGP#_Q=!AhYwIt
zQ)9qU@Rr#<9tv$9WF5Z;BKpUfDXsD|_omRCrKiQs`Fn^D*PDmU_AZ0^lRsgC%F&Xa
zoqasM`uxj|eXC!@s~{WSJ?z{Y%$F))n00_5iA4jI3^-aBI9_tw^=9++iO*||;K96%
zAE4#nl<&aXZ*zC|_!YW~hkIYrcww4|z1CweP-;YfzWe#=;Vbxx)OB<3BbE9!o&?ru
z^B@)M&Ly=fvfls!Y0h+$9D=^msC>n%)tTK~5_LAS)qUz`Inkzfw_g_DfF5Zch`@$^
z@c}|%$B3QDw}%2104ly7JA7j(9=F!UifFY@-0MKf=poEleOu5W8D@rPwpF$j-_dTU
zhUDFsT-S8Z>|WQ_8+&iBu~2@TV<B(vK2Yr)FZ12DIlKM;+B^T?$gZo-ztPy4acmD0
z#{okKw8zGgY*`*@#^bSLC)P-s8D&O4B58g&v3YJut&uWPOX+TnG;y2+2#HBdDnND#
zTZT;vwg{<El`MgBmXJ+$!{ThQkOelt77L*^1%^M^P|Jp0NG<#Mo_p_m_r31c%!K^0
zRl7Yk>OSwDcYmCF&bjBFbKZTem8F%1qTKlt<#1@ED|uUx!%fs$nH|s*!8;L{`Ski$
z*4AjvCJ2r#w1!vQi+3{TdGEyP`h0a&IwGlsMy`2dn$mCYpOHZ0zNaB4@}2`{7pgcE
zTvweSs=E%Bdvusod+$u2U9DcKnJ~KIW7T^8+-Ej`gGFKgCc13?KRHT<k2&wKo(FZi
zpJaA(ex`N-yUH&{iOS5;VT<HgT{D~Qu_tj2Dv%M@P*(|4l+5TEkYSF{wC^GReJDp|
zhC?+4|3g?ZqIqt~A!2u`Gmdp#CllYxvF)1tJ_NK1brzvH76Rp!VTU-sM>5`2sHD~~
zpHDUj^~|Yw4TM<T?6HpBPFUM!T<($Wr8%ZkekD4w0Tn|>5|ttA$5(2&z_Ui=e#slj
zF4MM`FAdeIRaqcPrdveTY#bNlzoDa}6UUMn7uL`r1EcgCnZ=D;vjO6v;-veG>gFl-
z1XU7XGINa75KWnVGiCPerc8K&BXm94DAfk_8GSIa{32p3Gg>RKOg7Y!)mpU?(SQSK
z(o5zr*Ye*KYtj9Y>cX<?zPjLM-FZa3m7mq;d~~Mc(P+vIA!r<)WXZ7nAT+blBpEHt
zv`p*-RhuVsxXQ3fGqNiMHes<rt+zJW$C~}*vbuwTsv}JD+ZA$B?099J^=ZXIlPl{B
zn+<bYU%TjD*jQOdaJ~5!nzW93zmZ-dtijr~8L~I?$Ti*2s}AyF8(So2g7J^)R%gV>
zMwgd4!cpD2?3KNq#&&H@6Gg4)))8w!I50C&naH5<7pIBG44M&})#feV+1c!7?~RGB
zP#tq@-eJ4BdAUjCVBsRh-CHbJM`y@8$ZC)r)6$S3t7*!&ljGQnvS^sTYo~u>VFB{v
z9Znb4>q{#aLbE;y7luPae$+-Eat4etdcR)!Ad<;dcMNToxRYn~h=jw1te$v4HhN$8
z#_`iEbM=MGiPcwV<!G|8)mT`)xUgKUUm#3sZSrJ5oGesqlN7?J&{b(nluhh#+!4J$
zJDWlaWZANmKkbybWs1PF-DW7{6PJV0B3aw*h471&vY(pUo~o~2E-ro@@3xJ3dX6pD
zR9&-uh6k~1oe#T-3Bn{R(~WiM2)UXRThD5m+3wPMd&_hxwX2C~EVH5|VS^@TLsn<0
ztucaI6PvACW|um;c#}ktM%R0OIQwTMm?j%$u^PIW2=Sw1Rk8-Y32s(M9(JDDCXpd0
z08LL<H=E9U;{l*_mUZeFYlyQ&3LWk^MA`Bk#@LyzM!%`L8|*@3P~ppLF6?Tie8XiP
zQ}t{%w?0lHg;7o6qUuqpX1hI`8e&ozMRWGco0!>wC8@-AJ2vF8`XXr{nkWp0tPM96
zv>`@I6o&MMwh|v_#?GJ1Tax;+os?Ba-FeeFk{?*xg=`qu4Us~%s*HresuiLLB|#hA
zR5aD`w;WB@AH_u-MHmr#<S?T8eA=if>de+QZEUBaXGS^SElEb+HOKm4R>F#q!B!l)
zqmF9cw#P2v?=4KJrV83P4#;U^w-*qjA-ToD_sY#iTWO#O+?Xsh4h7Dz7D8Fvy}(q)
zPGJ;nycV;Qm)Z_g3H29LNvPB5jDX^3Toh?Yl9O4SVm|-GZIvc!t>yJ7@x>7;PVg~d
z9mQj?(DErtYFeUPRCUp^p3}X%k}cCB?_xH6CWV7XObo3`@mNr9kWNhIS!;vUDXD3%
z=sY;}%{4i9nrXsQDyQr*l?O(ub#EZLjc)T0s%Y#|(%6=`IaI?uRBbkE4LvbPM%^Nh
zt1R%U%e920lkvsvWPJk@pP<6s*{?@J70Jrt_KqzM9%iL)wo-Bct&ZATcs_>86M913
zX%hOaZg=T*xsH*;V{6OHJB_n^M_o_ls8!dQMhzXr%1_D%PlocsSB{iZuKLVyZ*6;{
z(O1#mxNKtfgq8HKH81eEdZkwhdVRf>+dckWcX6@Vsy_5kfsnnR_g8f0^y#rQ)h~M>
zH0|rJ4B|;{yKA|++UoU%eY`Tv%=xsX#GR|BPL<KvSi`j4{>U}ly|FR2axIh{99(J6
zY<n()wRT{>`{&sh*TE6d^@_AW`IFPrm5AD&rdLnpJ2YMY7&`k&6ZxZl__XlR$~BO0
zWXM<(%lP!ld{gNPB;}Bj)FdSdSI2!4gMo#Ojl^iN6Sc}LyjX*BPH3|J3`QOIboI>4
zN#CQrF#BS^W9XcicD1kax=POap5PA|Q}Ph#)eGWKL9Bv|XKLb}dlFqs3PQ0%{YJf=
z$|d+on^xQ5jxrTtZ{yLc*ECL+a$@NabsYOBgp9mpt<ZtQc7tP6Qz4S>AfJysl0-7(
z8E^t+QEjdzOBZUbg(RKC#hq@}3Aiud0<0~<le1^0wY4DBKZ9X1!pY5C)V`{P5mIZc
zFZFKsH~ZI6S5LVd={#jRHJt)RZ*SAmjPHFdcz37iHb>g_Zu8^<-VdJc;azXX9}^0%
zJv7akSHZ@p!L7RGUa;4fmhcTzW3#`q*4Ou%r~9nuI^lpVCLTO{<$`lhq!>zX*(BAt
znbx)!RyUjYgL?-C2KuN+`_Yud$aPtI@TD)d>&<ZABJsSl=<S&kv%EzYhCNPRB**j8
zSaXR#r0<QK9zTW3O=sQF-#m0k+59G@7~<N_WjOXCfMaJk4x9Cz#|);XXHiCDW2d;6
zSKEQggmZ2c)V!=7I%v?qB;8VSJ2=*FY`<2oehIHpV?V>>MMZa68Q8Ov$Bw(O5D$r0
zn|Q?6YN_>Z;Zkdr%>?m*ky+wL{&cuzAB&5!^r?4Q$@X-VLq9mUWtLN{&yDbupmJJ!
zd9{TOQ_<JGuTAmYEa+>#*=VhAEi_4*f~ZVP1J0{M!-e(riz~JMG+nCqRY*K6UZ$<3
zIulQ9q0)PIUvFREL7*l4FdTrKUx<pC3D+;ZVj-Owo*X@Vw3pXJ`XiLX5OAYW<=tsR
z%%)=4twBc{hmZ2NNmlZk4n9GduYq~s$o7NnNP}%igY8H|ZAe1}q&4=k#pd*Ox>9q7
zRA|nSip?2Pp*ce;Hpfmg8W|7V6gq>Yx0u%TuI5K7RQ_~jYgtb?^zs}4BD)5=Eod&8
zQ8$-%6^fxCyo6*Db2S2$hGf&SJgpu%Ty^~D<`WKs&)~M5_^i~ozJw=d>Qy@3RA#^D
zjJb&tlOhtVx}N_TrWBpLtq8LsOXOOo74#l1ew3b$;bo|q>;|z#{80uHa@XJ4@e`9+
z>~>Vtkly(|JUcNtJTcb0K!<9Q&hzZ%I7HZ9$&J0l3%z)opx(T7eEd8*rDBNONG|e)
zdb+s2RS)t%ze&(+rCuzlT-FTD4r9nDPw=3r4W2;{Dq06t%JfqgE%{&Cxvyfi+s`CL
zRj_5OrI_?dDqd2BQ!{$hUPrJ2&GW>;qN)DrDbBxC{u~GYc$&m&sj{utMP4=ytgs#x
zF<kYGnt-NzHyZ0L&U>i1?_@!)WNWxUzhh^Pmu5@zKvFHLDwB22$t0VLc{M@z6JQs0
z1*@zu!~MA;YprQr5p%3BRqpP!`;q?wI<_zkvAH9JfuhtN#m$3MS$s(oa2gR2$5mu*
zYr6HQAj6#;JI6aq(~~63L;fWsii^@tuAJltm~3=xgeN=4Wb92sU9;1rRL4gu*#%kn
zw3?)K)76evBRrTkd1ksd^~%@28AmFj);Bkbgfg0JEmvFpvg-Ra`hG1NS5}cLOE4>H
zQa9@)EIldIr-SLUYn5Kr*|$c@>-s{ks<wsP)NLSMz@|jaO2-tm4B4A?Bv4D~*1~c`
zC%ET<CHH|s!;@1G?=+7xK+;P~O-x&sR!5K%V@M-!*ug9jr`eKpS9wv2xLpglTO=Fg
z81M{FmnF1NiipfNSSd3-SQN|64cNq_OY31UchVH0>%-`YUIf+0rF(jN9qzq@eSLTJ
zzC8x5cbj!6da>DAr@F$fx)d`<S><}0p(u;C#+}N89~G2KtJPSU$D2vV=u;>$n}*aG
z)VvmKSx$i^i#OTO>gy|Yp1z<Cb=78u*OOq?%&}@>6v^_Lo$&U?QN+I>U=(KBv|tIL
zPhfw}42BilyxOA9Sw<sH((SDXS6b4&2?APc{bIUWZE9sBMfdb+zwTu=N;a1RvP*ch
z3dFGHcSJH<5@gu49d(Oy4A$lyb9Aq;gtcRhYxA<9u2f?Q>k2jI4BWksF`I*Rr5dlU
zlV%TQW4S_|1?zFAj+PO3taod{44JGGUFN)uc7-|%)=~GqmQ0l^(KVPu&Q5&w;|E_|
z<lab`IaVyF)ZpbferA%jL^j6U++(RAoneyVJ&WW^hg!dJY-Va~)JfS>&O(-5+#+d;
z>hIDfhn~D9E+I0L6%7`PSk|+mA&Q<x<cZ~Frpf4IES0<)Y<Om7_%SRB&e@a7XsxAd
zB!{MK(KeLtut?WS`s&h3b7g*Il?NcuUk4UzOL~0fKp$#|r=qlJmE5uqLgCq_)?7ZL
zW5>>%;KXr~)aCWTBgT_K)@<(r`k~n`O)Cc+euH{$Ea)md&{rzsMn7Itu{$cR3Ryzn
z7=a3CwBgPpNtL|7+gx;Hv@T{FTw99GeCc&dXmNok?R@>Sxi&vqx>(`Z5V@<#CASn3
z30S|RMu>)I7My$tMg!hLl?~q(YiCT#B5WgaRPL59nuHY;ih~g@uce;uz5MQ9A<?a$
z$3pN;s;1_eCT4&Vu2l|H?ofH<K)-%+v2x(iNBQOOsg3l~#g&Ct%1%>T?+w)vmQ_H!
z;k|Yl=cVfeR&c{Q?HE{_@JV2*LMhMlH9axc%O)5@Q-2{&oz#(f3sZpzd^*DW<7Y9;
zobQh_8s?xW5B&9c*VIJrZRkBPe{rK#IdF$V$WK-qaXWuFmNV8*&P<)7&k>vY6|%M5
zSl_Y*a*2pHp*aj<j*%^zeR@bY<)j=;7ew^T45vMcU+8a;P*|1M^0rxea2pN|hRt?L
zoF@yDeX=YMeIdK%q32jrXNb%BcChjgknyRvYY-Ij8q62s?^3DObQ_}4$!m%+_C*}F
zH1e3=;oKiO==R<I$y|<aW(v&p43A(T$Y~U*n(zcKN6{q2t|f*Y_FCA*vII;n`mZb_
z_Skw5jg`7KrkQ;ac59P(+U2~Fp7ET+e(l6?d24u~y0%tj_jsYsFLBlK%Hm?J4&9;|
zmf=)XL=MaJP?|d1h)I-*L=_xcDbEW#G%O*G%a}{?nz7G;9XOE1_KI~J5VmJUs<|WB
zSH)&Km|kq$xlv1Wy1Ig)69!kDltI<GMKD;xJHOt+475Ts=IrIG93a6Ne0HFcDP|(e
zi^aZ}J<C;R0eVaSioP}Plg%6k#*7fN;8;s%Paio9y>z~hA5SGki)=P((tD<gNQ=P{
zm9pj1ekz|-PR?l)6*xi@IXgDx{9i-bj+zvhTt+fr%+ENBZnTbAiB=ojkyMpA7Msf2
zTI_7FyE1FGyGzkArk=^Wf3~y<UfV#VH}2=S#HE%VaN?A5(>(mJZ3OLh*5u~I$h0^o
z)Sc6w9CrbCVz1APA3KBc87EPT*oZ6vRAbESMs~Zl(Mm6neSkM0oxki_Gb(1D(=vjn
z9<TbjI|64Uo@4sK95a!;_X0l!LqhkVoYeuVxz)IwRu{}|d&ODW0hj8gj?GS;<~TCi
z(o4&WFst(MVH|Maxs^}b*rDEfe`ku)H7BYmC>1t$jFY|RdEAd?$vkCyjs6OrOZW3>
z91_}o$O;lUX}_dQ9FbK~?$kB|0k``q>uTodwu=>aHORVihD=O5<IQWg*cr06k$XV&
z4!MPnK9IEy93Qc+_BGNe$Cs|1Y#r#@Ty3p}51JIG{)%(hXVqr++8SbR7L1eW$7aS)
zoSf@zcQ`v=acJKy^<|fbnW!RMPEzNLaEyFx47<-9EwjPCJ1}yf@>GHWm+Lrt)mAXl
zwibN^;bJ0{(aQ#1{=^Hm+oqw+c!Vw^XE<Gz_r%9$WP}l4$G6C#3e`oic2z1E13_T{
z9heJSv=;ClX#KwT-d<b3w<-^_V!sZ=<`%9WtR6QH&O0s_LVpE(yfW(LLwLvCeH)mg
zR_MWd?tvA>TG_H^`+znz8AizA)o37T)uAJaXUAavl}#^l@M$WmdJc!}DcqVY-QF>!
zFBDh%mRvWPuU-d0xd(a=&i5%Fsy&9eSexIxaGzT{ERMOfRg4;R3nmo92tKrMg<t}f
z=w&G%yxmt;=N`AKAI9tZtEkEJT^HAQ=8BeCVtIk&P&(%+bBtBs5(C_Pd$Uh3jMkbr
zGxIjL^hr%=GjL`Sn{(u(y=Evjwm0i=Bl5~VrI*QJse#q&&NC;q2p{GWX0D@9Xl8?B
zE<dG;L6kVa#aZNHrgEp<+ig%0L47K&zg_SW98ITjF=^wN_iSms!4VSdRvJreC0X~X
z{qucVP?|DIF_)EtGGvtCTmjBRQHs@>k-4zz6Ny|w;A)P+lkzUgOXduv=4}0UmUuS{
zz%iAXJ}jYSqsK2G7CksbfbI;3_njD>n;Nbpq>YeplcY|Sp#{^Ck}7jnpnAzj!LF}s
z!0s#$w@~K<@?Jl}e?}g+d@%-d7-Hw8q;A``w{*)^wNWP+EK4w8+r-<7HdKk{z?!fP
zthWx;v*Baor^oR@OwSCTAbD*1%&gXVakTU8XZpY*Z}zNjb$($HZt<>kza!CHX4btk
z8Bl*P!Lbz*Jz9xE!Y=;cec|A{&9wam%Gdagw8@KetI5pcEP=<iy;xmURxGOXJ6_>v
zlj{m_)?_6Fp0k2{CoDNIqGt6rtzrw+=QsOltPF5i%Yg7n^&4<|Y4fy)=85R8ytVT9
zfddsPs2t!&p_pa=(#rZ~^8n2jWL4zuD65Kzg6tVH^VoR*dz!8C45Pl@tm4?mYFe|0
z#F-;r@+kLjXpG526%}R3`Ilf<MNt-Ty{xg38$7}ZTzMoV?2lxTSu~$R7{_PlATH!s
z2-}`yT2YwA75okN@#6qIL;g!^6KBqw-c<KLpLoKjgdlos_qBoH>vcY@%I%H){zQ6M
zQ99elMk!PnGO=T=zjBA_$S68Ii+7C(P<sd~3b$+8rJWRhTwS@yrhQE@`~IbsMzh6U
zm*2)!MK`@yYaHsA->u{>e=`<gez%#CZumsaw^kN97@UP-FQw)lnVLL4j-SXGPm(k3
z%|vnxwF%yf$ZJ|9#uB)~R+&+ClJY6J+x)8FLh4%U4;?xv*M(On5VfRhyqbv?7Az9I
zQ&Al$F{^Eic$xrWHnp~dpX{`WBm|>JaU=Cv`bHD5MEuXKo#+fjXUZ-UY$`ie+AOEx
zN%A6y)j5C2>im+}Q5Gcbi_8XOQ}3OEf$4Jtr_^V+7!sBj5qQPpFdhN9ee4*gaQDQq
z8EtP_kh&*X<j#EZ_JW)1#OWzsI`2ka>Afp#os}ER?$IZYI2~|q#6s*lHBxYf_a$Uy
z+G3PB?v|>nM9+5g+*u|;(NW=?ajp}=8E0Nv)(0FUZV&AZ8*WFb*DfY#_DdE7E%YhS
z>)eR41$G`v9-tBB<!)Z&;FWaKY9$%d9-C0cLyibuVe=R^i{d69ECXeBM5#0FTNn~P
z3I3~#nV-)&e((ckj=n4d!<#46$9`Oo=5V7kl1+B(jFiElLx<J*>?q3cgKN1S*24un
zD51r2d~9qC37(rH9dvARbbNS{tL&PX$g(*v6`h;&*>0^(ZD+b)9r3#@>9R_jB!{h-
z>7;Dg4o*29#TuEGE+LrVohcTQq1IUSXcRto!mZdYkHWgj5wn~?-huMzskQ2M#Uj##
z`t3U<;?02yht%ukYBOD`@kCLhraBK|WvwfXs}Q)RpjV|`7m1E*M6cWRDs$<8ad^d1
zq0-#s3AY-?AAUlbg8jCP{UWQ`ovEx7kcHvwebN<z+3!rjofX&2Os=@hnTHEzeDb8d
zU;Fgb6lXzC!4AjpDw{?m9K=G6#R+d9JTflvQ+SUx7nHFg8r-2n_2}|t*JVouGcO}P
zBj*Zus>14zjJm7}^M6QBqG<1S&RH2GPUORlaoEX4iQ0JN?C^|o?j&x*%8RKs)f@A9
z*-v;Gng%7HibHRpe~4R!UxQDCUqk!?!MkeWZbdHYj+Y0so3!9%RZv+}U!f>8;x9%d
z$l5xRK2V@dR&caaYnma`h`xjPONTpH9e&pxB8hO6YnsKB`jv5Zs<bfKVj7YMz;}CP
z*x^#kRAd}#j`mQMlH6~QE{O3+1-1s~dznGINpGe_!JS6IkWn<sYaYbwJkF|zSVES3
zZe-)L&SG=0An7J1(7I~2wxUXf4w!9cMVK+YiaME(4u>|G1^pGWK51{InLAEhl4S@x
z6-q40%8?E2I62j>3$@+KNNbE8Tya;Itsuv4AUUp^EdL<C&Q;4*3_f7N;-wG}7G^Me
z^0Hz)xTye9ech=JXY6o+ew&I=w~zD31!N^_T9XbR)x1bI%lRb78)=(39I}hmt*n5H
zWE~;>ZYc%VqGp=e*~!zV%;$WNdL1c8&axU!w$aihqKfadS-!@QR=cCP6w>ldTk4ok
z){~`f@uko&73vCNoo`Ls{FqUypL1f)a(s%0$O{3Ibbj@svk%*x*j<v0BG<LUpbk=!
zAYJB*$|5G6qYGJaxTC8_$`L^;4*Tl!Wn<bIrkOp$Ohj2U^e6V_OEHfU!#{uC;x9<k
zR`qf-1iwNQ3<)gArnX%L%n(3oTrkm2Th$8+-=-H=c#c3nc-Y7C)>I-OXbbswzWEK5
zIfuIMpU8m8vs%Q%=PZ@+;6aImYzO5EkRiIR$Y5kkP+DJi^UiUZtCyQAO%TkvmxW0{
zaIW99SzW4;$Ph3C<7=ZEGi$uB?8dFp4zrD2!~JqDktrW7(kPC?jatE6%ke#Ct(g1F
z?T;Cxj0Nq8X0;T#J7%@VN?nk^mSJ-NyNp@|dBqVVrju;fI&xS;wD2$a<{bjSZGkDh
z*u?gvaHy>z$7xIvurnu4vVN3Uj6KP!!ta|GmaXq*Eu@y8XX*4o(?{2(=jHnw9V1tU
z%zKhDOO-Cx6gnX{P7B+mW=KDD_PI;V*4}opRwLZFBnLHgLa~!>M-Dx|L#u`L#kwFf
z6S>e^@E{sy>b71->hlA6)PW2^IUH>tWxQnOSr=^*m03=VrQ*s_s<0m_xKZ0ew32LJ
zPw<Q2n{rUyJlYbL*&i}YLdgX0*SW%mG|Q-imvc8AJ2T#W;GT+L!I>N-)72vJCK;A_
zT^14zQw5N+QS-!fV&vk1T?X$LfuKfXDax}5W8w13UZzqMB+GJ$I!DSVF2~A3iX!7)
zquU`z^f<4(av^GqI{U>mS~m$wF#E)O^h1_F9`&&YIl{sVH-bo%$NUv{2lS15?lBJE
zIWSu&rH76z6UX!z$4(pO*xb{EIuFA)r*z%DJNm2?2_rPN%2-Pdp-|!%i=sZY6@d*d
z+goC=wowRi?OxU6ytKJLt>UkW4!j<R)L{if%y$#mk`?fRHZB%!B_X!a>gOpqCaN5t
zt=Q$l!$>YfYd6`{EE44F;2#feNjD_VsAuP7k(5K6&iXD$RM<g>jM;Qr<0j4q<FV(`
z7K#7xVs+cXnXw?a?PgcI2MwD`f-?g<N&$E!A@CJj%^JFFRC}0di6`2tqy&;dNGG+4
zBzhIt(5)Dpd(2~BHV96!o8o<Pc!95!02EvwJ`t|ZwHzugDzc%9o(-`?eCPbAcrggB
zX(N${T!@6hi$QM}u7^hO(p_1KB3q&`i##DxIh1U|Ysy?qZAtm&q|0vINw{JkgS}^|
zcI1e;A3JQgor@iQ!rwY-vf(o~+@lDPBxHZ9)1(6~aM)e7_044i#>s%E*#Y`zODs>p
zWpmO<Y<Hd;o|*J=iXPB8UA$>Rck(@JkFK!H9Tvcb%@)1G2W@Hh@xC*YdW+v?UA9|$
zv=44jP`fOGF8h(mb2~L^H-9E8DXEM30vR^e-M7_LK{AJhGU7qu1|~Nb3n$wmnK>o1
zLAeP$45S27nkr-};N=4Wd0OVYbbbX+b#{$^fGD#t!rs}1wdC09^w@!qG+=rA$V8iU
z#Y*IYtg_D8V7nNE+hU6o*jF}Etjzgp!<lAH?aza(_8uS>_K^KM;G#u@q*&wa0ZI9&
zr9bnnfNcYG$;^IxK(XD+T9^%U%bLXH53Ko6wbWwU+LDE_mC6GV-9mM+s~mz78zOK-
zNTJkaHBby+x9>|0&w0S}l&4G0;J<h3iDsDCmF6M`0Qwg7@XQsPD<S#EKOO%@D$kfa
zQ+dv=-#O*M$Ht;WHdezpac^mf$7+}9Y>~13b4|wD8WL+%P@eH7L)j+ul63Q2FO%8p
z0OrMB>pAuYz2gcYxwPb|B?&$^Hhc=Q7i<PaV{JM&>-i&WmH}*0o0GPgh#cl_N9MAE
zqd>&z$#N(nJg9z%C&EXvH?fW$jvn#u@TS(mBYGXw^zdT@dvLR|5gWr0x0lS@`&+Z8
z$&1x;=md{~AGE_R?CJ4NRUcY(2XP&@gEhyNd8?Kkx$54I)49Kc_Y)20EG*pL;Wm4N
z?1PNTUzkr=EcGD0dagqci2$CNoTGN$N^MQ3bjL=9h<>29LJQd-JB{L~!=2e4&yE$1
zNLnPzmEU{I?n}qL+TkQwv&BjVhb)Q4b*|~!az~hy@D4NB=_*M<)x}wCtEg9<#&MX%
z+#P&!T&X4zcB$H-c>c$hr^EYuIbjH8$eYflktKgBLh05AXv3d=;m=r!n(5Rj<34uq
zdVbSpaV)F46Z)W(NP#fjn2*B~rU!XDq|VWFCw$JKt96j~+Y9oc^Ap0r^xIWFzIfbL
z62*Ut<KfVWoO5>UYlm6v*4e=_KbB>3$A%6U<zOry#!k0o5<K{zJ3QD;ZlDs!B<hWO
zUDDnz5xduU9=u!Tz6G6G${8M=S%PM!uB0b+<eDOfF|C&*;}P4dVJ9A)IHp}jmP~oX
zCj)i5Zz$GPJ2P=M#7p={28!HOl(~d6RUDa<!3T7T(kxcRW;4*-&0{VL8A;oZE*crs
z*&kONx#MP2g&IRjv}9Elq?s|SY8<{?(9v0oMXC>W)E!-QQmNIBssf^2;-KbCnzNQW
zO~%!%39-)fLK>@V2?YlvmlhXRk|k2oI`(j|ZTWJN5?*5-W-Z*^q2q@|Va7T5fJDrZ
zCEUhQii;S|S>qjUAG}IU+;Jkx3~UD(*OKI>BuV~(&#t8BZToJzIr(m2eZFvAviF^Q
z5AWOio}TybI=1gC*A3siryc(`a1Qc+^!jA);T+#^E52--vd=_i`_5C`Gq-Q=@Xa@e
z`wzb)*}EL!sI5@;9A$H*vI?-;{TgMz8I|qpRo!p2x^MM3pV^b_eW~GG_nuu8m&bf3
zWq-r}7r>j&@b>Ko_51fR?3<7M#y&1575)qFw!O*T5Af}2GraF0m`_`i84ktC!!eF(
zn=Rsev{OBAE8=vlXU5@_$D#3lW>=CNy&>8A5^LLyH(Y;hm+PZluD`y^_36@e@r>F%
z%XJZIc%N(cn5SGQU%Wzjqf5E?K=r?qa*a9Ay%RsGt<Uu&$+O^UUPE7A@B5-_Dz^`H
zy7GM$W~XO8n(Q)d)rZ@5C&_g$P4<rRJMKd$Q=R8aW$KUa)2AD4b}FxMpUO|t?vwlu
z?HYI193O->J_=5+;W+w-F^BRmQLerQnv6#C6Z+7pyuv-9+{uUOgyDU+LAA8l2T)CJ
z%WcGUoCGHuhw6B|y$<1rI!<=z=atIE^WpxH4)@379P3annuYt1cPPJ7`~SC>Uupc;
zQhv336!;L*cI1(=%!!82qR3u^Z@+G`8u4Av*Ntfc4yeg-{%3sUw6~U+L^7{>^vU_c
zBxocO`D@1e%1z1M&y{q@??)9@Xix2acwe&j8GdJd6VJcH@qECcIQj81PS2<z#r=Q1
z;Yhws`U>k)jQ6e_Pr7Y8>Q-T#kLGyl)nlFTdcQ5%`z!f4ZH4{42r+K=y~X<89-$T5
zeRC17-VM*`ifp`3bi;c*uTTBE&<XF4_p>IT`<+~y&fk6Gt{gLrqvz!XJ3w@)=2%H#
z9H;Ykg_m~2n=Ilz*$uCbuFv>HcE#?0xyx}%vE6SaAJesOsa*X3`u6;z^vbo+FS1v6
z<kMWAo8BAi#(z$SX7cuUj91prl9zri&LJ-)Iek-npY*=)o&zslS5NqLHPoYVKg@qG
zpVHuSaXm3!)SmDP?ZtSb#rn>7tFP4VnSU(a)wKIO^q4F5uT6i5Zu&&?tnn7+C5-o`
zTa&#@;ClK=53Y6_N4<!*5#vd>gm(Kgyqot_{Ph;?xbgY*SUqxEt|Z_*56-vSy%Emw
ze9cq+zXi_G7)LABxgrk5wkOSWqS_k2dK~e67|Y(ME$tmDzU(Eh2zGJQ*AuRdz`LN@
ze$&zR<~@@gc=u6ou7-D?DdIg9(?0I6+b_62#r@^>#LbKEuO$BsS5K3Q?)QB4J^U`v
z_VwS|dIE3KOycI+bc<$jw%fSXwa_PxJD!71dnn<@J`A<_h5gJg^Lo_QQ)^T5u>0-1
z@>T;L=*j=g?Hk(*ekDh<^<MSqbCCajjvdt_|3Ikk{B6nJp&U<Ror$W;>U%GEhjTpD
zSD;C#50qH`+w^>e@?!rYKK6VO*X86gn}^Z3Z)IAF_WN()kG}aI_&@BaRIkcE$5_60
zT|RHly4vV*+~j0Uc%OI`{u-lo#JfFTHnfVbi?8HM{0}^^?<kb%aht@rKa!QupLh=!
z`rE0zpL<mPw(m{$K1)B2?W??N?+@>J&r6=U{ztBR@9y{E>l)toq}qF4L%2D#xA*p-
zBSg2G_k=x<+E9HJ%6p?ei*G~O$qr?KZrqae=Da6f>3Lr?Au-;f)t}AVQiPVZW%U_e
zt~bIMRCYD;QvvTf7J&`={m=NF&4cysWHwjA(dT3QFXBwM;rwPBPPGl^D>06^yys#Y
z&iBVS>d%`E#bhe<N8R!=DvUN;>{{{ejQRE8@J)Mqdw$fl>TL2*-)KADPj|xGX^&K)
z@1edYZ5)xDIC3O0&NpHllapo}&AQbi-U@A<&v|fLl>ZkIbH#WMmGJ&)gctYgf5-hg
zsT$wf)~|mR(@Wa9=MUO&{(W4Jjqk~;#)<p=<+!b9B*8s@W))F?-0y<kc~oc%ZS5V8
z>)H^`&lpbJUa##l{oH*(?P;sISMG>HdoRZ0v-Vco+FNXE?_+K4eb@Do41UepdnPE~
zxL@CD+4z60zI;vTypIa<v~Ba6*&Umam=tu?w;FFbZ&w<0ty{ZSi}!G`zH{B`+lej}
z>IifxtS6=y+Se1USJ`@^QAGBBsOPR&CQM_!zfEqAl<PU`1TgN;2g^7;V{P^PQH*1K
zUTKrRw;7Jjw|cx4(<yH6;ke(+VD|h(TV2z6UA<sb<GNy5{&zXvdDRqe3gb3oyTrVP
zQ|)wk((2lIt+^VUyUX=BQ=p*p4wi9zTr3{jhYcsAXU}*<gbHPW4+?c@wU1(K0q0Uo
z^P{5FuNVPzuW)WUknDZ&x-PchhkLkT_r)Hw2HWGG>hr-@@rRG&x2(@?zKek8`fPaW
z@f)I{nQpjNyhmv}vUdtT+zMr(z5|Bm=U6SD&iNqVIC+n79&5*$i|fHi-s9s?aa%`Y
z9JS?RmNC6#i%0#Q>O_aXxhvS!8C@r0ytvJ)8K2tEbc^~m;l@|q_XuzA_p<kVb!_*W
z^b~w&TK|N17`(k!xBA&R#(W;Uhrz34c(#U|D33>YkArvE@S?f!G}QgV(Wjs*HJ(UU
z3g-jV^IhN-#_UwC$z-VKN;n^<o@e8FBu7u>yrFuI_9lBjSjO@CRP+?iZ-O&wI5)j(
zw=xS{9OH?7H<@Xa^=W@!viG;*y2NKa^VVR+*Y(HX6!=V<H}W5;y>Gw!$~cqYOvi1h
z9%uHMJgT0b0q4BoWPDibG;d!AubWRL(BRg4f^RI-0fjwyz`Oe@@gBVbUYWNAfAx0a
z_1w3g-{o?x<<}uh%aotAG4FrZbw9lO-ON@;+=Jl0uq)Xsy*9mX|ND2J_^o}N>a9@z
zIJo#)_P)@Q>Dza|<UQ9vbKQ^Zey{2udFZ|~yvd+R9$8~`>%P%i^CC$z_qEpVZ7tXC
zU0YwT-?z2ixY*>;?V57U?rrhpS`$2uUQ>G7h+Zf~9#x~oTZ`@Cmdy<w4ka^f>F~h^
z-g=?6J<y~Z-98fGWOu@X!RHzJsqftho#pca^w9Ti{^|2ve}Jzm!5HIwel9D2NeRX|
zz~`e`xmBx675&+r+@LRgL`LA3>Pxh*=zDi^qrQ?4Ww2&2|LjiKWJI6cw(HL?>`uNd
z2l%zyHIrT2oxCjjtslD+930VSck=QGQn|EX{@I<pA_w@jJCVmJ|Ljh_!&BH@yDs_b
zfA~&*euA70ccsVl+7}|YLcwPv_+H>INAMu<??mt;z>qDgPxZ&}DZm#a{7IGjkNWc%
zzdzyUo7|{G_XmDRfLDQk#PdfFu<HA;hgJTAz?v_|NjF+~m~U2$<o%QfShuPEk4N|a
zGVm{!>L&*#8_(w{hdC;e)dYS}`+?t*WKW`fbAWdNt32?J@c#lhd;<L?!|qy7^7o;T
z?@%te4dtpY@PCqApWNUEYQ+KnbL5Z({8yC9b$^g2afrsRoU?$h@<+)V3-I@JxWAY2
zyK*=F=?GSR%1I0Ne;@b%wa*pPd<_BL54;S5;MW2FH1M2<)&53wzv@#S8()0feD{MN
zV3jL}Ex@|}gAuH9<*~)(FGjG+mCF{Fe_~G#t6X_(p?re=hEJfk^4CJS+P{_jvH<IT
z<*fx+<<CX1%9W26m-k2VQSH#4^2`Fh?pJ<U3@fiJhLuki!^$IzVdam-u=2%XSovWw
ztbDKlZ<P9{@$sqHU-YTq@Ampu{3f_Rg4KWJj5&NazaNj_AL>v)wob+2JN{!8@bC@B
z&&m~x>l=+=wWpk}xcs>Yw)u!)_4kDcR=M)I;`_fE!9P*zuke*e6YvFp<)$1~{m+r7
z5|=A)C5Dv;62r=;h+*YT1o-DWw68dEDE}<wXMj&~A?VK!Mdj+B;>7{~55fOwVA;C?
z|5H)9@D)!D_<sZbr-5U6X0Ml(3t#clfWL<&{$^msPgTFl73U1)ucUkvc+{7RUZ0A}
zt^E?L_-43Y<%%-~_-<!X7#QSN@v2a6{7FnDz`9>?r5INHD8R4lP@iHlp<MMPugqc9
zcT)tboIPNMukwc@Smhs&V3mI&f>pjuOocB#j(&=<1X$(YsN}HjS4<@?|LzD@xne4D
z`J)l6a>Z5R^5qDg?LZI3GXnlH<v06%f0%Fi0YbU@`v-UCu-f}-1grdOcje_<9op00
zHPrXc4&~ZghH}-fJ!F92*8yL9$55{J&quKC*Pbyhe>Q?uuDxJf{v~hUg!NZ@ytur-
zH-~k<_IIINu=a8>tUX%{YkwBQ+Ka`o_FXZoJyr~BFBQYuH^s2_M=`8@P=H0B!;yX$
zyd1$l(Sg3&4~6@GwnMr0L!n&teK>+Y*#SS;k3k+j6X8GK0sm7`x#;`32zKqdztR`~
zn)`$OD0}Zqz`@=_(<EOlz<ZLvEx<3a^^e;8cy<{KP;o8Xklf4`XV*)Uz1)@@K%Nhj
z;3FmY1hCdqRroU2*E6N^W#CuAU$R$K-+O>-tgnhk-U9p~;72I0`0`%@z8!h(_2n-B
z|2F#csE7XxaNNJI0gp%c*RvSM<*x#M9qnl+ruObDm7f5{(6!Hg=zEUeFN1&OgAo2t
z0{;N_Yo{gn=YbzXzYcl$)4*|iFO=XvD8YXP{Bh5ZYVYg7H_(64NA<syEo3vI&vybp
z81?`AfWv(6$NnA!j@utA!DoS=_AzhKzg{YT7WfyT|FgdRF9LsYkMoPDKmVzO|5w28
zWBi9b{w@d`?D_rRi_pK0J^xN$z8^U3KlZc#_;%p9zxM(EE%GkkiQ0RzRNe%>-RE<t
z{0D&l2l_Se$47vlp#PyiUoPGM=Oy^>fWNrQ@&7G7J;{x1$>aXqQGy>R!N=VezQVM@
z?>8i8OXX|8k|)d%E8hnGh|dF7|KAP#hG;&2s&xM^mf&9pj_LQiz<etDv!C|=a|!=1
zf&Uldlb=Q7`&-~Yy(zJLWwn13or}j?DZvkx;BjEtyKcNUCey%|*$;h&_Eq0P34aTC
z5AzlH`MtnlzbJnFPznDNz$@sxlfJ%x1N@!rM?T=;-znjL75I~0KdSw|ER}x)xX<S;
ztNdlSR6dl^>&E0efVCcoUv5WV4FZ1${1^1g_XB^D`4KF6Sp|;i_0AIfV<q?(fT2~!
zAD;rg9(_9M$Mb8zKL)?b@2dX&Y3csI27ZwB6`EW5ATFTY*t6_$4L%JV_a`mETfnhC
z{qa)y$4c<80>||EjZ*pVm*77u!RC_EV!=oH?Ava1>#yjm^<V&4{uiN0KfD%L`!ReN
zR(={d9#6FdZvcN1dsDeXqSw2CKh1g|&ywJel<+@Yg1=aT{|NYg=ntFN{Qmb+`EG<Q
z?$0Yr@Br}V(QmdsB3}=e%BO&1{j^>x|Dh86lfeHG`rPLG^RuP$UjqIQ@I&AqWVz74
zzXLvpJcyp6$1YreW08J&xnSf~^P%$FfaCEU1pX7BAFuK;;OC?DX{v-j4}6aL!}?t>
zmA?b{pCeD_eS04R{!#Gn^zbhO|5_x!zY07Be&Fvv2fl~$Fu%9b&@V*#;QQ3Dxxn=2
zrO5#BIP`mxi;~yZ0LSAyRf69L{0rdsdi<qQ`8!MS2Y~5YMf86e%>I+5@}DokpDn?E
zRD%Bs_%CQ*&$Wo&e-DhESkd48$*yEKF50;Nw*oW8zWj!ypY=DF*PD`8I+w1d-{^5C
zFk`D|eCqGrrTQKQ{ygiqa`r^8Nq4`*0sLLbn@afg68vu9;b?w-890`Qe_O);{Sy3Q
z38vG@sfb@+1{{z74&YZr?ah?R7fW!f1V0NL+XtTqehc=N@)1P;-v<7ZzFhzRed+#v
zxWwcB+*N{K3;b)?OQ=PwuS@J<J-M@$oL*nw7+K%AJjy9D<2>_h7kC_a^^LX0`h2sQ
zjC14#*K4UTlRJ4%xzTF2HkXzLbo|oTNzRzp8=T#XHh5;3V|UUEtLyW;p<=PM-r&U8
z&264-=7okejsYCdiCY~oc-wP*CFQ)U>gANzP&Rlcc7sE})5XoTwadx+{F`|(#{lPq
za%O9GnG=;b+a<myt=6jZE9vIy;>xA9^~C|6pWbvo7gr7oTD-Kjn6_4%{8p^S4hLAP
zu5d~~GI2gVF+Dz&8W8|^EP5~l&J54Y9d?k9-)wJlgym|w*4*IU{Mrh2Ce6#uR&6ar
zdbYO<7~EBcQ#+?1szo&~=w+U|m6rsZ<;c)kj(cdVtT%Xz=Lt?}+~A~+P;{buQFK>g
z)r{2_))#A`reyYVb8dxKb#f{TC!3VIaA9L*y{)f}g@v|jyx~ma7M0XbUl~l(Fbca<
zaO|gzloJ_NSLS(7_`U92O=iQxno%HFY{h-m`O?u@(M0R`CQg-XyB1xrSX&#KyE-$+
zD^ypjjkR=q<_+%njYe{Ec=lvE!@I4bYn=2tJ``UVo<26sQC16cI%Ol_trbUgYEN`W
zc-;PwKlW#-%CSz1W7DS=W(U)?#NvVzyg??kn&FSc$Kr5)!X-My%Lu4lQ#*3{)ZlSm
zm}3{qyr6yzmike;dB|=aofsbCPzMf;TDw2)^hw@McU&)o&AJ8VU?<FUf|K$HXTmNz
z(`Cow0j}m)gur`&9O|}-;5nGQHqDVo(`R`zc0NlST916@@Z2z`a&wpwf1|4$=BFdE
zViKN&ghm7%m@<1d8|mc4c=lT_(B-6Dw9jIK><^_g=aK)sF|os;_(DWwMlzxUs;muT
zjJcT;dih7H*+FsS)r2|kaHhhQPv}vT6U~ir#KFz`8BV6Bg@bVm85!r+FI-qPI;N=J
z?Ut!LSd9aUrP!^XzJkKQcIe_@$MaCehei(Z7Ws~yu)c;GI~*1=<PQt!cK%HF!*Vns
zg@MzJp>*tQ+zk%6Dy#@e#M=egHf=w1zEI!s=`(R%Ofp(sF@2lsWNMCgzRafQPC>(H
zf;YFMP&0X@V#!RSm7Hl-FVu>XW_&g~!mA{628raf&_hnDYue##jh0?T-83GbogObR
zDF-oT>zxUJns@5h9r2-AKa!3P7xb1`C_OgAYh}kL9xU`_1ObWq=EkN)LzJ)+-Mp^1
zk(B5sM&$iCbK|`6#iIowbE-HRYLNkXFDuJKuF$ig1m-_8%TjYB?wVmIcD+!SIw2wq
zFD}k)Pw;vVCV}^TNdVF}&Yhh!zAGLnv-3GmZAY)n)HuOCQzNuBSXLcc7YjN!8hC-@
z9DTJo+lULY(?Ma}Z)9Y(VBW4)$z0XJErDpPKK@uP48qg3OSRPmAsZ|SStL`%Dd~82
zjUAH|-BRFRZ)fGw;J6;049_#l!qjSgjF^++qk)SDi=v~2i^GjJ!nzgay#r0hSf=g$
z=-G@8pNyA%X`R9Q)1t~99xe1l<WuKNLOkc|T6yix?6`;=50r*ffKAHg&c`T0wGMil
z1JkkPIHDWJ6>4;<yQ9vO5q&Vxcppp)b%iE7XmdOINfuUFD~`>bY`Z3sz+qCC35u*Z
zWuA9B%ut6DpS&vOST)|-5>v<7m&rtJZGr>iFVwP0mC+wB1_d!Juz#jAnkx$nYwSK`
z9So+$S(rULl2t8=U9~ipPK|S#)ychfL_6A89ZqrUe%M&~%q5M{?De2h)0!WiO4I|J
zm*cY&1=iL)Ml$Dc7YsF;1P;oKvCf?vEm+pe+AkcIJQwC%74V+<GV6c_xg&e3pfP-_
zr9MgHJ1Vlv!(cTwF5H*aYysu`U^l7D>`VsT`cdeVMkraHYA$$5zL0J#)z7jYWpgWa
zh|Mt*k2X^7#TKvaEVy90te6-Y&y_5N<GeJsFdI?J1qM8}*(}-}woG1I=ZXiX`KgMi
zjsO>wbEMJ=eF@5=gJ84q>2fY&#;k5mchC*x(+b^k)op$X%T?6l!bryS^0rL6lK~EI
zZdK>`ZZ+KZa`?5<Y^0ZrF_Hl@xCa{R#$^M;GZO<?;JS^U$v|QMnhYT6-jR_E<c^SJ
zz}@UQbU-%CK+4NR8!1O1Dw9;4ZFOhIxPpPNWepb!cPkGSyNF}t{O{`gJg>COAUm<0
zI~-!8enGDT%;2@^LL<9#b){YlhzvLUG;d4*grj$#$ZdC3pI3r~%Mp*4een0~QeI>B
z2|r)W75yemW_gd#?Anz)dUuAV*oJ-X<!`7@@xK@D*_HgBFVk1RyWispS8<@5LJx$*
zC$#&h`@Qjld<*Zneix+k{mtqdqZ}6<kp&kA?Np!Ip5wn<s{!xls4w)1%l2FFll;de
zX?TjOf3yqUDmdz^>f=)pCGpE<pHR1EM0kE&`#bedH@%hra=NNM`FDl)EWg7i)b|c9
z1U&hDtv*eT|M+&29|NYYjc{Ff2Lr%&!25{*9m*aCZ={4L+>b@~sQ4Y={o!Zz%Y8z9
zzXBM3tK>Wh3TZ{Z+$WTM0Wkbl$@72GlRR%;XNMPl{%#3x<HerjpL7`Se=Xr%|KEC&
zpVA>e{uA2zS_$uGUVeRYzdG$d0q+~Y`W@)<y9B~tcsie9mFfQ;{^&b=o;z_%@__>Z
z%K83Qj~D9efAcL#El0CDRFD4Wy(ZQQ-jf7_ln3%V{1+eW=RaY=z<d1SJi;HmB{_}n
ZIebE&bV)oFK97FzmPF4nhfnzVe*lnIzzhHY

diff --git a/Debug/can-tests.list b/Debug/can-tests.list
deleted file mode 100644
index e8106bb..0000000
--- a/Debug/can-tests.list
+++ /dev/null
@@ -1,6978 +0,0 @@
-
-can-tests.elf:     file format elf32-littlearm
-
-Sections:
-Idx Name          Size      VMA       LMA       File off  Algn
-  0 .isr_vector   00000188  08000000  08000000  00010000  2**0
-                  CONTENTS, ALLOC, LOAD, READONLY, DATA
-  1 .text         00002a40  08000188  08000188  00010188  2**2
-                  CONTENTS, ALLOC, LOAD, READONLY, CODE
-  2 .rodata       000000d4  08002bc8  08002bc8  00012bc8  2**2
-                  CONTENTS, ALLOC, LOAD, READONLY, DATA
-  3 .ARM.extab    00000000  08002c9c  08002c9c  0002000c  2**0
-                  CONTENTS
-  4 .ARM          00000008  08002c9c  08002c9c  00012c9c  2**2
-                  CONTENTS, ALLOC, LOAD, READONLY, DATA
-  5 .preinit_array 00000000  08002ca4  08002ca4  0002000c  2**0
-                  CONTENTS, ALLOC, LOAD, DATA
-  6 .init_array   00000004  08002ca4  08002ca4  00012ca4  2**2
-                  CONTENTS, ALLOC, LOAD, DATA
-  7 .fini_array   00000004  08002ca8  08002ca8  00012ca8  2**2
-                  CONTENTS, ALLOC, LOAD, DATA
-  8 .data         0000000c  20000000  08002cac  00020000  2**2
-                  CONTENTS, ALLOC, LOAD, DATA
-  9 .ccmram       00000000  10000000  10000000  0002000c  2**0
-                  CONTENTS
- 10 .bss          0000008c  2000000c  2000000c  0002000c  2**2
-                  ALLOC
- 11 ._user_heap_stack 00000600  20000098  20000098  0002000c  2**0
-                  ALLOC
- 12 .ARM.attributes 00000030  00000000  00000000  0002000c  2**0
-                  CONTENTS, READONLY
- 13 .comment      00000043  00000000  00000000  0002003c  2**0
-                  CONTENTS, READONLY
- 14 .debug_info   0000bed9  00000000  00000000  0002007f  2**0
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
- 15 .debug_abbrev 0000205f  00000000  00000000  0002bf58  2**0
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
- 16 .debug_aranges 000008b8  00000000  00000000  0002dfb8  2**3
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
- 17 .debug_rnglists 00000695  00000000  00000000  0002e870  2**0
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
- 18 .debug_macro  00022499  00000000  00000000  0002ef05  2**0
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
- 19 .debug_line   0000b635  00000000  00000000  0005139e  2**0
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
- 20 .debug_str    000c7dc8  00000000  00000000  0005c9d3  2**0
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
- 21 .debug_frame  00002290  00000000  00000000  0012479c  2**2
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
- 22 .debug_line_str 00000065  00000000  00000000  00126a2c  2**0
-                  CONTENTS, READONLY, DEBUGGING, OCTETS
-
-Disassembly of section .text:
-
-08000188 <__do_global_dtors_aux>:
- 8000188:	b510      	push	{r4, lr}
- 800018a:	4c05      	ldr	r4, [pc, #20]	; (80001a0 <__do_global_dtors_aux+0x18>)
- 800018c:	7823      	ldrb	r3, [r4, #0]
- 800018e:	b933      	cbnz	r3, 800019e <__do_global_dtors_aux+0x16>
- 8000190:	4b04      	ldr	r3, [pc, #16]	; (80001a4 <__do_global_dtors_aux+0x1c>)
- 8000192:	b113      	cbz	r3, 800019a <__do_global_dtors_aux+0x12>
- 8000194:	4804      	ldr	r0, [pc, #16]	; (80001a8 <__do_global_dtors_aux+0x20>)
- 8000196:	f3af 8000 	nop.w
- 800019a:	2301      	movs	r3, #1
- 800019c:	7023      	strb	r3, [r4, #0]
- 800019e:	bd10      	pop	{r4, pc}
- 80001a0:	2000000c 	.word	0x2000000c
- 80001a4:	00000000 	.word	0x00000000
- 80001a8:	08002bb0 	.word	0x08002bb0
-
-080001ac <frame_dummy>:
- 80001ac:	b508      	push	{r3, lr}
- 80001ae:	4b03      	ldr	r3, [pc, #12]	; (80001bc <frame_dummy+0x10>)
- 80001b0:	b11b      	cbz	r3, 80001ba <frame_dummy+0xe>
- 80001b2:	4903      	ldr	r1, [pc, #12]	; (80001c0 <frame_dummy+0x14>)
- 80001b4:	4803      	ldr	r0, [pc, #12]	; (80001c4 <frame_dummy+0x18>)
- 80001b6:	f3af 8000 	nop.w
- 80001ba:	bd08      	pop	{r3, pc}
- 80001bc:	00000000 	.word	0x00000000
- 80001c0:	20000010 	.word	0x20000010
- 80001c4:	08002bb0 	.word	0x08002bb0
-
-080001c8 <__aeabi_uldivmod>:
- 80001c8:	b953      	cbnz	r3, 80001e0 <__aeabi_uldivmod+0x18>
- 80001ca:	b94a      	cbnz	r2, 80001e0 <__aeabi_uldivmod+0x18>
- 80001cc:	2900      	cmp	r1, #0
- 80001ce:	bf08      	it	eq
- 80001d0:	2800      	cmpeq	r0, #0
- 80001d2:	bf1c      	itt	ne
- 80001d4:	f04f 31ff 	movne.w	r1, #4294967295
- 80001d8:	f04f 30ff 	movne.w	r0, #4294967295
- 80001dc:	f000 b970 	b.w	80004c0 <__aeabi_idiv0>
- 80001e0:	f1ad 0c08 	sub.w	ip, sp, #8
- 80001e4:	e96d ce04 	strd	ip, lr, [sp, #-16]!
- 80001e8:	f000 f806 	bl	80001f8 <__udivmoddi4>
- 80001ec:	f8dd e004 	ldr.w	lr, [sp, #4]
- 80001f0:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
- 80001f4:	b004      	add	sp, #16
- 80001f6:	4770      	bx	lr
-
-080001f8 <__udivmoddi4>:
- 80001f8:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
- 80001fc:	9e08      	ldr	r6, [sp, #32]
- 80001fe:	460d      	mov	r5, r1
- 8000200:	4604      	mov	r4, r0
- 8000202:	460f      	mov	r7, r1
- 8000204:	2b00      	cmp	r3, #0
- 8000206:	d14a      	bne.n	800029e <__udivmoddi4+0xa6>
- 8000208:	428a      	cmp	r2, r1
- 800020a:	4694      	mov	ip, r2
- 800020c:	d965      	bls.n	80002da <__udivmoddi4+0xe2>
- 800020e:	fab2 f382 	clz	r3, r2
- 8000212:	b143      	cbz	r3, 8000226 <__udivmoddi4+0x2e>
- 8000214:	fa02 fc03 	lsl.w	ip, r2, r3
- 8000218:	f1c3 0220 	rsb	r2, r3, #32
- 800021c:	409f      	lsls	r7, r3
- 800021e:	fa20 f202 	lsr.w	r2, r0, r2
- 8000222:	4317      	orrs	r7, r2
- 8000224:	409c      	lsls	r4, r3
- 8000226:	ea4f 4e1c 	mov.w	lr, ip, lsr #16
- 800022a:	fa1f f58c 	uxth.w	r5, ip
- 800022e:	fbb7 f1fe 	udiv	r1, r7, lr
- 8000232:	0c22      	lsrs	r2, r4, #16
- 8000234:	fb0e 7711 	mls	r7, lr, r1, r7
- 8000238:	ea42 4207 	orr.w	r2, r2, r7, lsl #16
- 800023c:	fb01 f005 	mul.w	r0, r1, r5
- 8000240:	4290      	cmp	r0, r2
- 8000242:	d90a      	bls.n	800025a <__udivmoddi4+0x62>
- 8000244:	eb1c 0202 	adds.w	r2, ip, r2
- 8000248:	f101 37ff 	add.w	r7, r1, #4294967295
- 800024c:	f080 811c 	bcs.w	8000488 <__udivmoddi4+0x290>
- 8000250:	4290      	cmp	r0, r2
- 8000252:	f240 8119 	bls.w	8000488 <__udivmoddi4+0x290>
- 8000256:	3902      	subs	r1, #2
- 8000258:	4462      	add	r2, ip
- 800025a:	1a12      	subs	r2, r2, r0
- 800025c:	b2a4      	uxth	r4, r4
- 800025e:	fbb2 f0fe 	udiv	r0, r2, lr
- 8000262:	fb0e 2210 	mls	r2, lr, r0, r2
- 8000266:	ea44 4402 	orr.w	r4, r4, r2, lsl #16
- 800026a:	fb00 f505 	mul.w	r5, r0, r5
- 800026e:	42a5      	cmp	r5, r4
- 8000270:	d90a      	bls.n	8000288 <__udivmoddi4+0x90>
- 8000272:	eb1c 0404 	adds.w	r4, ip, r4
- 8000276:	f100 32ff 	add.w	r2, r0, #4294967295
- 800027a:	f080 8107 	bcs.w	800048c <__udivmoddi4+0x294>
- 800027e:	42a5      	cmp	r5, r4
- 8000280:	f240 8104 	bls.w	800048c <__udivmoddi4+0x294>
- 8000284:	4464      	add	r4, ip
- 8000286:	3802      	subs	r0, #2
- 8000288:	ea40 4001 	orr.w	r0, r0, r1, lsl #16
- 800028c:	1b64      	subs	r4, r4, r5
- 800028e:	2100      	movs	r1, #0
- 8000290:	b11e      	cbz	r6, 800029a <__udivmoddi4+0xa2>
- 8000292:	40dc      	lsrs	r4, r3
- 8000294:	2300      	movs	r3, #0
- 8000296:	e9c6 4300 	strd	r4, r3, [r6]
- 800029a:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 800029e:	428b      	cmp	r3, r1
- 80002a0:	d908      	bls.n	80002b4 <__udivmoddi4+0xbc>
- 80002a2:	2e00      	cmp	r6, #0
- 80002a4:	f000 80ed 	beq.w	8000482 <__udivmoddi4+0x28a>
- 80002a8:	2100      	movs	r1, #0
- 80002aa:	e9c6 0500 	strd	r0, r5, [r6]
- 80002ae:	4608      	mov	r0, r1
- 80002b0:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 80002b4:	fab3 f183 	clz	r1, r3
- 80002b8:	2900      	cmp	r1, #0
- 80002ba:	d149      	bne.n	8000350 <__udivmoddi4+0x158>
- 80002bc:	42ab      	cmp	r3, r5
- 80002be:	d302      	bcc.n	80002c6 <__udivmoddi4+0xce>
- 80002c0:	4282      	cmp	r2, r0
- 80002c2:	f200 80f8 	bhi.w	80004b6 <__udivmoddi4+0x2be>
- 80002c6:	1a84      	subs	r4, r0, r2
- 80002c8:	eb65 0203 	sbc.w	r2, r5, r3
- 80002cc:	2001      	movs	r0, #1
- 80002ce:	4617      	mov	r7, r2
- 80002d0:	2e00      	cmp	r6, #0
- 80002d2:	d0e2      	beq.n	800029a <__udivmoddi4+0xa2>
- 80002d4:	e9c6 4700 	strd	r4, r7, [r6]
- 80002d8:	e7df      	b.n	800029a <__udivmoddi4+0xa2>
- 80002da:	b902      	cbnz	r2, 80002de <__udivmoddi4+0xe6>
- 80002dc:	deff      	udf	#255	; 0xff
- 80002de:	fab2 f382 	clz	r3, r2
- 80002e2:	2b00      	cmp	r3, #0
- 80002e4:	f040 8090 	bne.w	8000408 <__udivmoddi4+0x210>
- 80002e8:	1a8a      	subs	r2, r1, r2
- 80002ea:	ea4f 471c 	mov.w	r7, ip, lsr #16
- 80002ee:	fa1f fe8c 	uxth.w	lr, ip
- 80002f2:	2101      	movs	r1, #1
- 80002f4:	fbb2 f5f7 	udiv	r5, r2, r7
- 80002f8:	fb07 2015 	mls	r0, r7, r5, r2
- 80002fc:	0c22      	lsrs	r2, r4, #16
- 80002fe:	ea42 4200 	orr.w	r2, r2, r0, lsl #16
- 8000302:	fb0e f005 	mul.w	r0, lr, r5
- 8000306:	4290      	cmp	r0, r2
- 8000308:	d908      	bls.n	800031c <__udivmoddi4+0x124>
- 800030a:	eb1c 0202 	adds.w	r2, ip, r2
- 800030e:	f105 38ff 	add.w	r8, r5, #4294967295
- 8000312:	d202      	bcs.n	800031a <__udivmoddi4+0x122>
- 8000314:	4290      	cmp	r0, r2
- 8000316:	f200 80cb 	bhi.w	80004b0 <__udivmoddi4+0x2b8>
- 800031a:	4645      	mov	r5, r8
- 800031c:	1a12      	subs	r2, r2, r0
- 800031e:	b2a4      	uxth	r4, r4
- 8000320:	fbb2 f0f7 	udiv	r0, r2, r7
- 8000324:	fb07 2210 	mls	r2, r7, r0, r2
- 8000328:	ea44 4402 	orr.w	r4, r4, r2, lsl #16
- 800032c:	fb0e fe00 	mul.w	lr, lr, r0
- 8000330:	45a6      	cmp	lr, r4
- 8000332:	d908      	bls.n	8000346 <__udivmoddi4+0x14e>
- 8000334:	eb1c 0404 	adds.w	r4, ip, r4
- 8000338:	f100 32ff 	add.w	r2, r0, #4294967295
- 800033c:	d202      	bcs.n	8000344 <__udivmoddi4+0x14c>
- 800033e:	45a6      	cmp	lr, r4
- 8000340:	f200 80bb 	bhi.w	80004ba <__udivmoddi4+0x2c2>
- 8000344:	4610      	mov	r0, r2
- 8000346:	eba4 040e 	sub.w	r4, r4, lr
- 800034a:	ea40 4005 	orr.w	r0, r0, r5, lsl #16
- 800034e:	e79f      	b.n	8000290 <__udivmoddi4+0x98>
- 8000350:	f1c1 0720 	rsb	r7, r1, #32
- 8000354:	408b      	lsls	r3, r1
- 8000356:	fa22 fc07 	lsr.w	ip, r2, r7
- 800035a:	ea4c 0c03 	orr.w	ip, ip, r3
- 800035e:	fa05 f401 	lsl.w	r4, r5, r1
- 8000362:	fa20 f307 	lsr.w	r3, r0, r7
- 8000366:	40fd      	lsrs	r5, r7
- 8000368:	ea4f 491c 	mov.w	r9, ip, lsr #16
- 800036c:	4323      	orrs	r3, r4
- 800036e:	fbb5 f8f9 	udiv	r8, r5, r9
- 8000372:	fa1f fe8c 	uxth.w	lr, ip
- 8000376:	fb09 5518 	mls	r5, r9, r8, r5
- 800037a:	0c1c      	lsrs	r4, r3, #16
- 800037c:	ea44 4405 	orr.w	r4, r4, r5, lsl #16
- 8000380:	fb08 f50e 	mul.w	r5, r8, lr
- 8000384:	42a5      	cmp	r5, r4
- 8000386:	fa02 f201 	lsl.w	r2, r2, r1
- 800038a:	fa00 f001 	lsl.w	r0, r0, r1
- 800038e:	d90b      	bls.n	80003a8 <__udivmoddi4+0x1b0>
- 8000390:	eb1c 0404 	adds.w	r4, ip, r4
- 8000394:	f108 3aff 	add.w	sl, r8, #4294967295
- 8000398:	f080 8088 	bcs.w	80004ac <__udivmoddi4+0x2b4>
- 800039c:	42a5      	cmp	r5, r4
- 800039e:	f240 8085 	bls.w	80004ac <__udivmoddi4+0x2b4>
- 80003a2:	f1a8 0802 	sub.w	r8, r8, #2
- 80003a6:	4464      	add	r4, ip
- 80003a8:	1b64      	subs	r4, r4, r5
- 80003aa:	b29d      	uxth	r5, r3
- 80003ac:	fbb4 f3f9 	udiv	r3, r4, r9
- 80003b0:	fb09 4413 	mls	r4, r9, r3, r4
- 80003b4:	ea45 4404 	orr.w	r4, r5, r4, lsl #16
- 80003b8:	fb03 fe0e 	mul.w	lr, r3, lr
- 80003bc:	45a6      	cmp	lr, r4
- 80003be:	d908      	bls.n	80003d2 <__udivmoddi4+0x1da>
- 80003c0:	eb1c 0404 	adds.w	r4, ip, r4
- 80003c4:	f103 35ff 	add.w	r5, r3, #4294967295
- 80003c8:	d26c      	bcs.n	80004a4 <__udivmoddi4+0x2ac>
- 80003ca:	45a6      	cmp	lr, r4
- 80003cc:	d96a      	bls.n	80004a4 <__udivmoddi4+0x2ac>
- 80003ce:	3b02      	subs	r3, #2
- 80003d0:	4464      	add	r4, ip
- 80003d2:	ea43 4308 	orr.w	r3, r3, r8, lsl #16
- 80003d6:	fba3 9502 	umull	r9, r5, r3, r2
- 80003da:	eba4 040e 	sub.w	r4, r4, lr
- 80003de:	42ac      	cmp	r4, r5
- 80003e0:	46c8      	mov	r8, r9
- 80003e2:	46ae      	mov	lr, r5
- 80003e4:	d356      	bcc.n	8000494 <__udivmoddi4+0x29c>
- 80003e6:	d053      	beq.n	8000490 <__udivmoddi4+0x298>
- 80003e8:	b156      	cbz	r6, 8000400 <__udivmoddi4+0x208>
- 80003ea:	ebb0 0208 	subs.w	r2, r0, r8
- 80003ee:	eb64 040e 	sbc.w	r4, r4, lr
- 80003f2:	fa04 f707 	lsl.w	r7, r4, r7
- 80003f6:	40ca      	lsrs	r2, r1
- 80003f8:	40cc      	lsrs	r4, r1
- 80003fa:	4317      	orrs	r7, r2
- 80003fc:	e9c6 7400 	strd	r7, r4, [r6]
- 8000400:	4618      	mov	r0, r3
- 8000402:	2100      	movs	r1, #0
- 8000404:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
- 8000408:	f1c3 0120 	rsb	r1, r3, #32
- 800040c:	fa02 fc03 	lsl.w	ip, r2, r3
- 8000410:	fa20 f201 	lsr.w	r2, r0, r1
- 8000414:	fa25 f101 	lsr.w	r1, r5, r1
- 8000418:	409d      	lsls	r5, r3
- 800041a:	432a      	orrs	r2, r5
- 800041c:	ea4f 471c 	mov.w	r7, ip, lsr #16
- 8000420:	fa1f fe8c 	uxth.w	lr, ip
- 8000424:	fbb1 f0f7 	udiv	r0, r1, r7
- 8000428:	fb07 1510 	mls	r5, r7, r0, r1
- 800042c:	0c11      	lsrs	r1, r2, #16
- 800042e:	ea41 4105 	orr.w	r1, r1, r5, lsl #16
- 8000432:	fb00 f50e 	mul.w	r5, r0, lr
- 8000436:	428d      	cmp	r5, r1
- 8000438:	fa04 f403 	lsl.w	r4, r4, r3
- 800043c:	d908      	bls.n	8000450 <__udivmoddi4+0x258>
- 800043e:	eb1c 0101 	adds.w	r1, ip, r1
- 8000442:	f100 38ff 	add.w	r8, r0, #4294967295
- 8000446:	d22f      	bcs.n	80004a8 <__udivmoddi4+0x2b0>
- 8000448:	428d      	cmp	r5, r1
- 800044a:	d92d      	bls.n	80004a8 <__udivmoddi4+0x2b0>
- 800044c:	3802      	subs	r0, #2
- 800044e:	4461      	add	r1, ip
- 8000450:	1b49      	subs	r1, r1, r5
- 8000452:	b292      	uxth	r2, r2
- 8000454:	fbb1 f5f7 	udiv	r5, r1, r7
- 8000458:	fb07 1115 	mls	r1, r7, r5, r1
- 800045c:	ea42 4201 	orr.w	r2, r2, r1, lsl #16
- 8000460:	fb05 f10e 	mul.w	r1, r5, lr
- 8000464:	4291      	cmp	r1, r2
- 8000466:	d908      	bls.n	800047a <__udivmoddi4+0x282>
- 8000468:	eb1c 0202 	adds.w	r2, ip, r2
- 800046c:	f105 38ff 	add.w	r8, r5, #4294967295
- 8000470:	d216      	bcs.n	80004a0 <__udivmoddi4+0x2a8>
- 8000472:	4291      	cmp	r1, r2
- 8000474:	d914      	bls.n	80004a0 <__udivmoddi4+0x2a8>
- 8000476:	3d02      	subs	r5, #2
- 8000478:	4462      	add	r2, ip
- 800047a:	1a52      	subs	r2, r2, r1
- 800047c:	ea45 4100 	orr.w	r1, r5, r0, lsl #16
- 8000480:	e738      	b.n	80002f4 <__udivmoddi4+0xfc>
- 8000482:	4631      	mov	r1, r6
- 8000484:	4630      	mov	r0, r6
- 8000486:	e708      	b.n	800029a <__udivmoddi4+0xa2>
- 8000488:	4639      	mov	r1, r7
- 800048a:	e6e6      	b.n	800025a <__udivmoddi4+0x62>
- 800048c:	4610      	mov	r0, r2
- 800048e:	e6fb      	b.n	8000288 <__udivmoddi4+0x90>
- 8000490:	4548      	cmp	r0, r9
- 8000492:	d2a9      	bcs.n	80003e8 <__udivmoddi4+0x1f0>
- 8000494:	ebb9 0802 	subs.w	r8, r9, r2
- 8000498:	eb65 0e0c 	sbc.w	lr, r5, ip
- 800049c:	3b01      	subs	r3, #1
- 800049e:	e7a3      	b.n	80003e8 <__udivmoddi4+0x1f0>
- 80004a0:	4645      	mov	r5, r8
- 80004a2:	e7ea      	b.n	800047a <__udivmoddi4+0x282>
- 80004a4:	462b      	mov	r3, r5
- 80004a6:	e794      	b.n	80003d2 <__udivmoddi4+0x1da>
- 80004a8:	4640      	mov	r0, r8
- 80004aa:	e7d1      	b.n	8000450 <__udivmoddi4+0x258>
- 80004ac:	46d0      	mov	r8, sl
- 80004ae:	e77b      	b.n	80003a8 <__udivmoddi4+0x1b0>
- 80004b0:	3d02      	subs	r5, #2
- 80004b2:	4462      	add	r2, ip
- 80004b4:	e732      	b.n	800031c <__udivmoddi4+0x124>
- 80004b6:	4608      	mov	r0, r1
- 80004b8:	e70a      	b.n	80002d0 <__udivmoddi4+0xd8>
- 80004ba:	4464      	add	r4, ip
- 80004bc:	3802      	subs	r0, #2
- 80004be:	e742      	b.n	8000346 <__udivmoddi4+0x14e>
-
-080004c0 <__aeabi_idiv0>:
- 80004c0:	4770      	bx	lr
- 80004c2:	bf00      	nop
-
-080004c4 <testCan>:
-#include <sta/devices/stm32/can.hpp>
-
-//extern STM32CanController(CAN_HandleTypeDef * handle);
-
-
-	extern "C" void testCan(CAN_HandleTypeDef * handle){
- 80004c4:	b580      	push	{r7, lr}
- 80004c6:	f5ad 7d16 	sub.w	sp, sp, #600	; 0x258
- 80004ca:	af00      	add	r7, sp, #0
- 80004cc:	f507 7316 	add.w	r3, r7, #600	; 0x258
- 80004d0:	f5a3 7315 	sub.w	r3, r3, #596	; 0x254
- 80004d4:	6018      	str	r0, [r3, #0]
-
-		sta::STM32CanController canController(handle);
- 80004d6:	f507 7316 	add.w	r3, r7, #600	; 0x258
- 80004da:	f5a3 7315 	sub.w	r3, r3, #596	; 0x254
- 80004de:	f107 0220 	add.w	r2, r7, #32
- 80004e2:	6819      	ldr	r1, [r3, #0]
- 80004e4:	4610      	mov	r0, r2
- 80004e6:	f002 f939 	bl	800275c <_ZN3sta18STM32CanControllerC1EP19__CAN_HandleTypeDef>
-
-		canController.start();
- 80004ea:	f107 0320 	add.w	r3, r7, #32
- 80004ee:	4618      	mov	r0, r3
- 80004f0:	f002 f94e 	bl	8002790 <_ZN3sta18STM32CanController5startEv>
-
-		// Create a CanTxHeader for your message
-		sta::CanTxHeader txHeader;
-		txHeader.id.format = sta::CanIdFormat::EXT; // Set to EXT for extended ID
- 80004f4:	f507 7316 	add.w	r3, r7, #600	; 0x258
- 80004f8:	f5a3 7312 	sub.w	r3, r3, #584	; 0x248
- 80004fc:	2201      	movs	r2, #1
- 80004fe:	701a      	strb	r2, [r3, #0]
-		txHeader.id.eid = 0xCAFE; // Set the standard ID or extended ID
- 8000500:	f507 7316 	add.w	r3, r7, #600	; 0x258
- 8000504:	f5a3 7312 	sub.w	r3, r3, #584	; 0x248
- 8000508:	f64c 22fe 	movw	r2, #51966	; 0xcafe
- 800050c:	609a      	str	r2, [r3, #8]
-		txHeader.payloadLength = 8; // Set the payload length (max 8 bytes)
- 800050e:	f507 7316 	add.w	r3, r7, #600	; 0x258
- 8000512:	f5a3 7312 	sub.w	r3, r3, #584	; 0x248
- 8000516:	2208      	movs	r2, #8
- 8000518:	731a      	strb	r2, [r3, #12]
-
-		// Create your message payload
-		uint8_t payload[8] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08};
- 800051a:	f507 7316 	add.w	r3, r7, #600	; 0x258
- 800051e:	f5a3 7314 	sub.w	r3, r3, #592	; 0x250
- 8000522:	4a07      	ldr	r2, [pc, #28]	; (8000540 <testCan+0x7c>)
- 8000524:	e892 0003 	ldmia.w	r2, {r0, r1}
- 8000528:	e883 0003 	stmia.w	r3, {r0, r1}
-
-		// Send the CAN message
-		while (true){
-			canController.sendFrame(txHeader, payload);
- 800052c:	f107 0208 	add.w	r2, r7, #8
- 8000530:	f107 0110 	add.w	r1, r7, #16
- 8000534:	f107 0320 	add.w	r3, r7, #32
- 8000538:	4618      	mov	r0, r3
- 800053a:	f002 f937 	bl	80027ac <_ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh>
- 800053e:	e7f5      	b.n	800052c <testCan+0x68>
- 8000540:	08002bc8 	.word	0x08002bc8
-
-08000544 <main>:
-/**
-  * @brief  The application entry point.
-  * @retval int
-  */
-int main(void)
-{
- 8000544:	b580      	push	{r7, lr}
- 8000546:	af00      	add	r7, sp, #0
-  /* USER CODE END 1 */
-
-  /* MCU Configuration--------------------------------------------------------*/
-
-  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
-  HAL_Init();
- 8000548:	f000 fa5c 	bl	8000a04 <HAL_Init>
-  /* USER CODE BEGIN Init */
-
-  /* USER CODE END Init */
-
-  /* Configure the system clock */
-  SystemClock_Config();
- 800054c:	f000 f814 	bl	8000578 <SystemClock_Config>
-  /* USER CODE BEGIN SysInit */
-
-  /* USER CODE END SysInit */
-
-  /* Initialize all configured peripherals */
-  MX_GPIO_Init();
- 8000550:	f000 f8ce 	bl	80006f0 <MX_GPIO_Init>
-  MX_CAN1_Init();
- 8000554:	f000 f86e 	bl	8000634 <MX_CAN1_Init>
-  MX_UART4_Init();
- 8000558:	f000 f8a0 	bl	800069c <MX_UART4_Init>
-  /* USER CODE BEGIN 2 */
-  testCan(&hcan1);
- 800055c:	4804      	ldr	r0, [pc, #16]	; (8000570 <main+0x2c>)
- 800055e:	f7ff ffb1 	bl	80004c4 <testCan>
-  HAL_GPIO_TogglePin(GPIOB,GPIO_PIN_12);
- 8000562:	f44f 5180 	mov.w	r1, #4096	; 0x1000
- 8000566:	4803      	ldr	r0, [pc, #12]	; (8000574 <main+0x30>)
- 8000568:	f001 f98f 	bl	800188a <HAL_GPIO_TogglePin>
-  /* USER CODE END 2 */
-
-  /* Infinite loop */
-  /* USER CODE BEGIN WHILE */
-  while (1)
- 800056c:	e7fe      	b.n	800056c <main+0x28>
- 800056e:	bf00      	nop
- 8000570:	20000028 	.word	0x20000028
- 8000574:	40020400 	.word	0x40020400
-
-08000578 <SystemClock_Config>:
-/**
-  * @brief System Clock Configuration
-  * @retval None
-  */
-void SystemClock_Config(void)
-{
- 8000578:	b580      	push	{r7, lr}
- 800057a:	b094      	sub	sp, #80	; 0x50
- 800057c:	af00      	add	r7, sp, #0
-  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 800057e:	f107 0320 	add.w	r3, r7, #32
- 8000582:	2230      	movs	r2, #48	; 0x30
- 8000584:	2100      	movs	r1, #0
- 8000586:	4618      	mov	r0, r3
- 8000588:	f002 fae5 	bl	8002b56 <memset>
-  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
- 800058c:	f107 030c 	add.w	r3, r7, #12
- 8000590:	2200      	movs	r2, #0
- 8000592:	601a      	str	r2, [r3, #0]
- 8000594:	605a      	str	r2, [r3, #4]
- 8000596:	609a      	str	r2, [r3, #8]
- 8000598:	60da      	str	r2, [r3, #12]
- 800059a:	611a      	str	r2, [r3, #16]
-
-  /** Configure the main internal regulator output voltage
-  */
-  __HAL_RCC_PWR_CLK_ENABLE();
- 800059c:	2300      	movs	r3, #0
- 800059e:	60bb      	str	r3, [r7, #8]
- 80005a0:	4b22      	ldr	r3, [pc, #136]	; (800062c <SystemClock_Config+0xb4>)
- 80005a2:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 80005a4:	4a21      	ldr	r2, [pc, #132]	; (800062c <SystemClock_Config+0xb4>)
- 80005a6:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
- 80005aa:	6413      	str	r3, [r2, #64]	; 0x40
- 80005ac:	4b1f      	ldr	r3, [pc, #124]	; (800062c <SystemClock_Config+0xb4>)
- 80005ae:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 80005b0:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
- 80005b4:	60bb      	str	r3, [r7, #8]
- 80005b6:	68bb      	ldr	r3, [r7, #8]
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
- 80005b8:	2300      	movs	r3, #0
- 80005ba:	607b      	str	r3, [r7, #4]
- 80005bc:	4b1c      	ldr	r3, [pc, #112]	; (8000630 <SystemClock_Config+0xb8>)
- 80005be:	681b      	ldr	r3, [r3, #0]
- 80005c0:	4a1b      	ldr	r2, [pc, #108]	; (8000630 <SystemClock_Config+0xb8>)
- 80005c2:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
- 80005c6:	6013      	str	r3, [r2, #0]
- 80005c8:	4b19      	ldr	r3, [pc, #100]	; (8000630 <SystemClock_Config+0xb8>)
- 80005ca:	681b      	ldr	r3, [r3, #0]
- 80005cc:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
- 80005d0:	607b      	str	r3, [r7, #4]
- 80005d2:	687b      	ldr	r3, [r7, #4]
-
-  /** Initializes the RCC Oscillators according to the specified parameters
-  * in the RCC_OscInitTypeDef structure.
-  */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- 80005d4:	2302      	movs	r3, #2
- 80005d6:	623b      	str	r3, [r7, #32]
-  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- 80005d8:	2301      	movs	r3, #1
- 80005da:	62fb      	str	r3, [r7, #44]	; 0x2c
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- 80005dc:	2310      	movs	r3, #16
- 80005de:	633b      	str	r3, [r7, #48]	; 0x30
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- 80005e0:	2300      	movs	r3, #0
- 80005e2:	63bb      	str	r3, [r7, #56]	; 0x38
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- 80005e4:	f107 0320 	add.w	r3, r7, #32
- 80005e8:	4618      	mov	r0, r3
- 80005ea:	f001 f969 	bl	80018c0 <HAL_RCC_OscConfig>
- 80005ee:	4603      	mov	r3, r0
- 80005f0:	2b00      	cmp	r3, #0
- 80005f2:	d001      	beq.n	80005f8 <SystemClock_Config+0x80>
-  {
-    Error_Handler();
- 80005f4:	f000 f8e2 	bl	80007bc <Error_Handler>
-  }
-
-  /** Initializes the CPU, AHB and APB buses clocks
-  */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- 80005f8:	230f      	movs	r3, #15
- 80005fa:	60fb      	str	r3, [r7, #12]
-                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
- 80005fc:	2300      	movs	r3, #0
- 80005fe:	613b      	str	r3, [r7, #16]
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
- 8000600:	2300      	movs	r3, #0
- 8000602:	617b      	str	r3, [r7, #20]
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
- 8000604:	2300      	movs	r3, #0
- 8000606:	61bb      	str	r3, [r7, #24]
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
- 8000608:	2300      	movs	r3, #0
- 800060a:	61fb      	str	r3, [r7, #28]
-
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
- 800060c:	f107 030c 	add.w	r3, r7, #12
- 8000610:	2100      	movs	r1, #0
- 8000612:	4618      	mov	r0, r3
- 8000614:	f001 fbcc 	bl	8001db0 <HAL_RCC_ClockConfig>
- 8000618:	4603      	mov	r3, r0
- 800061a:	2b00      	cmp	r3, #0
- 800061c:	d001      	beq.n	8000622 <SystemClock_Config+0xaa>
-  {
-    Error_Handler();
- 800061e:	f000 f8cd 	bl	80007bc <Error_Handler>
-  }
-}
- 8000622:	bf00      	nop
- 8000624:	3750      	adds	r7, #80	; 0x50
- 8000626:	46bd      	mov	sp, r7
- 8000628:	bd80      	pop	{r7, pc}
- 800062a:	bf00      	nop
- 800062c:	40023800 	.word	0x40023800
- 8000630:	40007000 	.word	0x40007000
-
-08000634 <MX_CAN1_Init>:
-  * @brief CAN1 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_CAN1_Init(void)
-{
- 8000634:	b580      	push	{r7, lr}
- 8000636:	af00      	add	r7, sp, #0
-  /* USER CODE END CAN1_Init 0 */
-
-  /* USER CODE BEGIN CAN1_Init 1 */
-
-  /* USER CODE END CAN1_Init 1 */
-  hcan1.Instance = CAN1;
- 8000638:	4b16      	ldr	r3, [pc, #88]	; (8000694 <MX_CAN1_Init+0x60>)
- 800063a:	4a17      	ldr	r2, [pc, #92]	; (8000698 <MX_CAN1_Init+0x64>)
- 800063c:	601a      	str	r2, [r3, #0]
-  hcan1.Init.Prescaler = 16;
- 800063e:	4b15      	ldr	r3, [pc, #84]	; (8000694 <MX_CAN1_Init+0x60>)
- 8000640:	2210      	movs	r2, #16
- 8000642:	605a      	str	r2, [r3, #4]
-  hcan1.Init.Mode = CAN_MODE_NORMAL;
- 8000644:	4b13      	ldr	r3, [pc, #76]	; (8000694 <MX_CAN1_Init+0x60>)
- 8000646:	2200      	movs	r2, #0
- 8000648:	609a      	str	r2, [r3, #8]
-  hcan1.Init.SyncJumpWidth = CAN_SJW_1TQ;
- 800064a:	4b12      	ldr	r3, [pc, #72]	; (8000694 <MX_CAN1_Init+0x60>)
- 800064c:	2200      	movs	r2, #0
- 800064e:	60da      	str	r2, [r3, #12]
-  hcan1.Init.TimeSeg1 = CAN_BS1_1TQ;
- 8000650:	4b10      	ldr	r3, [pc, #64]	; (8000694 <MX_CAN1_Init+0x60>)
- 8000652:	2200      	movs	r2, #0
- 8000654:	611a      	str	r2, [r3, #16]
-  hcan1.Init.TimeSeg2 = CAN_BS2_1TQ;
- 8000656:	4b0f      	ldr	r3, [pc, #60]	; (8000694 <MX_CAN1_Init+0x60>)
- 8000658:	2200      	movs	r2, #0
- 800065a:	615a      	str	r2, [r3, #20]
-  hcan1.Init.TimeTriggeredMode = DISABLE;
- 800065c:	4b0d      	ldr	r3, [pc, #52]	; (8000694 <MX_CAN1_Init+0x60>)
- 800065e:	2200      	movs	r2, #0
- 8000660:	761a      	strb	r2, [r3, #24]
-  hcan1.Init.AutoBusOff = DISABLE;
- 8000662:	4b0c      	ldr	r3, [pc, #48]	; (8000694 <MX_CAN1_Init+0x60>)
- 8000664:	2200      	movs	r2, #0
- 8000666:	765a      	strb	r2, [r3, #25]
-  hcan1.Init.AutoWakeUp = DISABLE;
- 8000668:	4b0a      	ldr	r3, [pc, #40]	; (8000694 <MX_CAN1_Init+0x60>)
- 800066a:	2200      	movs	r2, #0
- 800066c:	769a      	strb	r2, [r3, #26]
-  hcan1.Init.AutoRetransmission = DISABLE;
- 800066e:	4b09      	ldr	r3, [pc, #36]	; (8000694 <MX_CAN1_Init+0x60>)
- 8000670:	2200      	movs	r2, #0
- 8000672:	76da      	strb	r2, [r3, #27]
-  hcan1.Init.ReceiveFifoLocked = DISABLE;
- 8000674:	4b07      	ldr	r3, [pc, #28]	; (8000694 <MX_CAN1_Init+0x60>)
- 8000676:	2200      	movs	r2, #0
- 8000678:	771a      	strb	r2, [r3, #28]
-  hcan1.Init.TransmitFifoPriority = DISABLE;
- 800067a:	4b06      	ldr	r3, [pc, #24]	; (8000694 <MX_CAN1_Init+0x60>)
- 800067c:	2200      	movs	r2, #0
- 800067e:	775a      	strb	r2, [r3, #29]
-  if (HAL_CAN_Init(&hcan1) != HAL_OK)
- 8000680:	4804      	ldr	r0, [pc, #16]	; (8000694 <MX_CAN1_Init+0x60>)
- 8000682:	f000 fa31 	bl	8000ae8 <HAL_CAN_Init>
- 8000686:	4603      	mov	r3, r0
- 8000688:	2b00      	cmp	r3, #0
- 800068a:	d001      	beq.n	8000690 <MX_CAN1_Init+0x5c>
-  {
-    Error_Handler();
- 800068c:	f000 f896 	bl	80007bc <Error_Handler>
-  }
-  /* USER CODE BEGIN CAN1_Init 2 */
-
-  /* USER CODE END CAN1_Init 2 */
-
-}
- 8000690:	bf00      	nop
- 8000692:	bd80      	pop	{r7, pc}
- 8000694:	20000028 	.word	0x20000028
- 8000698:	40006400 	.word	0x40006400
-
-0800069c <MX_UART4_Init>:
-  * @brief UART4 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_UART4_Init(void)
-{
- 800069c:	b580      	push	{r7, lr}
- 800069e:	af00      	add	r7, sp, #0
-  /* USER CODE END UART4_Init 0 */
-
-  /* USER CODE BEGIN UART4_Init 1 */
-
-  /* USER CODE END UART4_Init 1 */
-  huart4.Instance = UART4;
- 80006a0:	4b11      	ldr	r3, [pc, #68]	; (80006e8 <MX_UART4_Init+0x4c>)
- 80006a2:	4a12      	ldr	r2, [pc, #72]	; (80006ec <MX_UART4_Init+0x50>)
- 80006a4:	601a      	str	r2, [r3, #0]
-  huart4.Init.BaudRate = 115200;
- 80006a6:	4b10      	ldr	r3, [pc, #64]	; (80006e8 <MX_UART4_Init+0x4c>)
- 80006a8:	f44f 32e1 	mov.w	r2, #115200	; 0x1c200
- 80006ac:	605a      	str	r2, [r3, #4]
-  huart4.Init.WordLength = UART_WORDLENGTH_8B;
- 80006ae:	4b0e      	ldr	r3, [pc, #56]	; (80006e8 <MX_UART4_Init+0x4c>)
- 80006b0:	2200      	movs	r2, #0
- 80006b2:	609a      	str	r2, [r3, #8]
-  huart4.Init.StopBits = UART_STOPBITS_1;
- 80006b4:	4b0c      	ldr	r3, [pc, #48]	; (80006e8 <MX_UART4_Init+0x4c>)
- 80006b6:	2200      	movs	r2, #0
- 80006b8:	60da      	str	r2, [r3, #12]
-  huart4.Init.Parity = UART_PARITY_NONE;
- 80006ba:	4b0b      	ldr	r3, [pc, #44]	; (80006e8 <MX_UART4_Init+0x4c>)
- 80006bc:	2200      	movs	r2, #0
- 80006be:	611a      	str	r2, [r3, #16]
-  huart4.Init.Mode = UART_MODE_TX_RX;
- 80006c0:	4b09      	ldr	r3, [pc, #36]	; (80006e8 <MX_UART4_Init+0x4c>)
- 80006c2:	220c      	movs	r2, #12
- 80006c4:	615a      	str	r2, [r3, #20]
-  huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- 80006c6:	4b08      	ldr	r3, [pc, #32]	; (80006e8 <MX_UART4_Init+0x4c>)
- 80006c8:	2200      	movs	r2, #0
- 80006ca:	619a      	str	r2, [r3, #24]
-  huart4.Init.OverSampling = UART_OVERSAMPLING_16;
- 80006cc:	4b06      	ldr	r3, [pc, #24]	; (80006e8 <MX_UART4_Init+0x4c>)
- 80006ce:	2200      	movs	r2, #0
- 80006d0:	61da      	str	r2, [r3, #28]
-  if (HAL_UART_Init(&huart4) != HAL_OK)
- 80006d2:	4805      	ldr	r0, [pc, #20]	; (80006e8 <MX_UART4_Init+0x4c>)
- 80006d4:	f001 fd4c 	bl	8002170 <HAL_UART_Init>
- 80006d8:	4603      	mov	r3, r0
- 80006da:	2b00      	cmp	r3, #0
- 80006dc:	d001      	beq.n	80006e2 <MX_UART4_Init+0x46>
-  {
-    Error_Handler();
- 80006de:	f000 f86d 	bl	80007bc <Error_Handler>
-  }
-  /* USER CODE BEGIN UART4_Init 2 */
-
-  /* USER CODE END UART4_Init 2 */
-
-}
- 80006e2:	bf00      	nop
- 80006e4:	bd80      	pop	{r7, pc}
- 80006e6:	bf00      	nop
- 80006e8:	20000050 	.word	0x20000050
- 80006ec:	40004c00 	.word	0x40004c00
-
-080006f0 <MX_GPIO_Init>:
-  * @brief GPIO Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_GPIO_Init(void)
-{
- 80006f0:	b580      	push	{r7, lr}
- 80006f2:	b088      	sub	sp, #32
- 80006f4:	af00      	add	r7, sp, #0
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
- 80006f6:	f107 030c 	add.w	r3, r7, #12
- 80006fa:	2200      	movs	r2, #0
- 80006fc:	601a      	str	r2, [r3, #0]
- 80006fe:	605a      	str	r2, [r3, #4]
- 8000700:	609a      	str	r2, [r3, #8]
- 8000702:	60da      	str	r2, [r3, #12]
- 8000704:	611a      	str	r2, [r3, #16]
-/* USER CODE BEGIN MX_GPIO_Init_1 */
-/* USER CODE END MX_GPIO_Init_1 */
-
-  /* GPIO Ports Clock Enable */
-  __HAL_RCC_GPIOA_CLK_ENABLE();
- 8000706:	2300      	movs	r3, #0
- 8000708:	60bb      	str	r3, [r7, #8]
- 800070a:	4b29      	ldr	r3, [pc, #164]	; (80007b0 <MX_GPIO_Init+0xc0>)
- 800070c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 800070e:	4a28      	ldr	r2, [pc, #160]	; (80007b0 <MX_GPIO_Init+0xc0>)
- 8000710:	f043 0301 	orr.w	r3, r3, #1
- 8000714:	6313      	str	r3, [r2, #48]	; 0x30
- 8000716:	4b26      	ldr	r3, [pc, #152]	; (80007b0 <MX_GPIO_Init+0xc0>)
- 8000718:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 800071a:	f003 0301 	and.w	r3, r3, #1
- 800071e:	60bb      	str	r3, [r7, #8]
- 8000720:	68bb      	ldr	r3, [r7, #8]
-  __HAL_RCC_GPIOB_CLK_ENABLE();
- 8000722:	2300      	movs	r3, #0
- 8000724:	607b      	str	r3, [r7, #4]
- 8000726:	4b22      	ldr	r3, [pc, #136]	; (80007b0 <MX_GPIO_Init+0xc0>)
- 8000728:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 800072a:	4a21      	ldr	r2, [pc, #132]	; (80007b0 <MX_GPIO_Init+0xc0>)
- 800072c:	f043 0302 	orr.w	r3, r3, #2
- 8000730:	6313      	str	r3, [r2, #48]	; 0x30
- 8000732:	4b1f      	ldr	r3, [pc, #124]	; (80007b0 <MX_GPIO_Init+0xc0>)
- 8000734:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8000736:	f003 0302 	and.w	r3, r3, #2
- 800073a:	607b      	str	r3, [r7, #4]
- 800073c:	687b      	ldr	r3, [r7, #4]
-  __HAL_RCC_GPIOC_CLK_ENABLE();
- 800073e:	2300      	movs	r3, #0
- 8000740:	603b      	str	r3, [r7, #0]
- 8000742:	4b1b      	ldr	r3, [pc, #108]	; (80007b0 <MX_GPIO_Init+0xc0>)
- 8000744:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8000746:	4a1a      	ldr	r2, [pc, #104]	; (80007b0 <MX_GPIO_Init+0xc0>)
- 8000748:	f043 0304 	orr.w	r3, r3, #4
- 800074c:	6313      	str	r3, [r2, #48]	; 0x30
- 800074e:	4b18      	ldr	r3, [pc, #96]	; (80007b0 <MX_GPIO_Init+0xc0>)
- 8000750:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 8000752:	f003 0304 	and.w	r3, r3, #4
- 8000756:	603b      	str	r3, [r7, #0]
- 8000758:	683b      	ldr	r3, [r7, #0]
-
-  /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(GPIOB, GPIO_PIN_12, GPIO_PIN_RESET);
- 800075a:	2200      	movs	r2, #0
- 800075c:	f44f 5180 	mov.w	r1, #4096	; 0x1000
- 8000760:	4814      	ldr	r0, [pc, #80]	; (80007b4 <MX_GPIO_Init+0xc4>)
- 8000762:	f001 f879 	bl	8001858 <HAL_GPIO_WritePin>
-
-  /*Configure GPIO pin : PB12 */
-  GPIO_InitStruct.Pin = GPIO_PIN_12;
- 8000766:	f44f 5380 	mov.w	r3, #4096	; 0x1000
- 800076a:	60fb      	str	r3, [r7, #12]
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- 800076c:	2301      	movs	r3, #1
- 800076e:	613b      	str	r3, [r7, #16]
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8000770:	2300      	movs	r3, #0
- 8000772:	617b      	str	r3, [r7, #20]
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 8000774:	2303      	movs	r3, #3
- 8000776:	61bb      	str	r3, [r7, #24]
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
- 8000778:	f107 030c 	add.w	r3, r7, #12
- 800077c:	4619      	mov	r1, r3
- 800077e:	480d      	ldr	r0, [pc, #52]	; (80007b4 <MX_GPIO_Init+0xc4>)
- 8000780:	f000 fece 	bl	8001520 <HAL_GPIO_Init>
-
-  /*Configure GPIO pins : PC10 PC11 PC12 */
-  GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12;
- 8000784:	f44f 53e0 	mov.w	r3, #7168	; 0x1c00
- 8000788:	60fb      	str	r3, [r7, #12]
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 800078a:	2302      	movs	r3, #2
- 800078c:	613b      	str	r3, [r7, #16]
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800078e:	2300      	movs	r3, #0
- 8000790:	617b      	str	r3, [r7, #20]
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 8000792:	2303      	movs	r3, #3
- 8000794:	61bb      	str	r3, [r7, #24]
-  GPIO_InitStruct.Alternate = GPIO_AF6_SPI3;
- 8000796:	2306      	movs	r3, #6
- 8000798:	61fb      	str	r3, [r7, #28]
-  HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
- 800079a:	f107 030c 	add.w	r3, r7, #12
- 800079e:	4619      	mov	r1, r3
- 80007a0:	4805      	ldr	r0, [pc, #20]	; (80007b8 <MX_GPIO_Init+0xc8>)
- 80007a2:	f000 febd 	bl	8001520 <HAL_GPIO_Init>
-
-/* USER CODE BEGIN MX_GPIO_Init_2 */
-/* USER CODE END MX_GPIO_Init_2 */
-}
- 80007a6:	bf00      	nop
- 80007a8:	3720      	adds	r7, #32
- 80007aa:	46bd      	mov	sp, r7
- 80007ac:	bd80      	pop	{r7, pc}
- 80007ae:	bf00      	nop
- 80007b0:	40023800 	.word	0x40023800
- 80007b4:	40020400 	.word	0x40020400
- 80007b8:	40020800 	.word	0x40020800
-
-080007bc <Error_Handler>:
-/**
-  * @brief  This function is executed in case of error occurrence.
-  * @retval None
-  */
-void Error_Handler(void)
-{
- 80007bc:	b480      	push	{r7}
- 80007be:	af00      	add	r7, sp, #0
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
- 80007c0:	b672      	cpsid	i
-}
- 80007c2:	bf00      	nop
-  /* USER CODE BEGIN Error_Handler_Debug */
-  /* User can add his own implementation to report the HAL error return state */
-  __disable_irq();
-  while (1)
- 80007c4:	e7fe      	b.n	80007c4 <Error_Handler+0x8>
-	...
-
-080007c8 <HAL_MspInit>:
-/* USER CODE END 0 */
-/**
-  * Initializes the Global MSP.
-  */
-void HAL_MspInit(void)
-{
- 80007c8:	b480      	push	{r7}
- 80007ca:	b083      	sub	sp, #12
- 80007cc:	af00      	add	r7, sp, #0
-  /* USER CODE BEGIN MspInit 0 */
-
-  /* USER CODE END MspInit 0 */
-
-  __HAL_RCC_SYSCFG_CLK_ENABLE();
- 80007ce:	2300      	movs	r3, #0
- 80007d0:	607b      	str	r3, [r7, #4]
- 80007d2:	4b10      	ldr	r3, [pc, #64]	; (8000814 <HAL_MspInit+0x4c>)
- 80007d4:	6c5b      	ldr	r3, [r3, #68]	; 0x44
- 80007d6:	4a0f      	ldr	r2, [pc, #60]	; (8000814 <HAL_MspInit+0x4c>)
- 80007d8:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
- 80007dc:	6453      	str	r3, [r2, #68]	; 0x44
- 80007de:	4b0d      	ldr	r3, [pc, #52]	; (8000814 <HAL_MspInit+0x4c>)
- 80007e0:	6c5b      	ldr	r3, [r3, #68]	; 0x44
- 80007e2:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
- 80007e6:	607b      	str	r3, [r7, #4]
- 80007e8:	687b      	ldr	r3, [r7, #4]
-  __HAL_RCC_PWR_CLK_ENABLE();
- 80007ea:	2300      	movs	r3, #0
- 80007ec:	603b      	str	r3, [r7, #0]
- 80007ee:	4b09      	ldr	r3, [pc, #36]	; (8000814 <HAL_MspInit+0x4c>)
- 80007f0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 80007f2:	4a08      	ldr	r2, [pc, #32]	; (8000814 <HAL_MspInit+0x4c>)
- 80007f4:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
- 80007f8:	6413      	str	r3, [r2, #64]	; 0x40
- 80007fa:	4b06      	ldr	r3, [pc, #24]	; (8000814 <HAL_MspInit+0x4c>)
- 80007fc:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 80007fe:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
- 8000802:	603b      	str	r3, [r7, #0]
- 8000804:	683b      	ldr	r3, [r7, #0]
-  /* System interrupt init*/
-
-  /* USER CODE BEGIN MspInit 1 */
-
-  /* USER CODE END MspInit 1 */
-}
- 8000806:	bf00      	nop
- 8000808:	370c      	adds	r7, #12
- 800080a:	46bd      	mov	sp, r7
- 800080c:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000810:	4770      	bx	lr
- 8000812:	bf00      	nop
- 8000814:	40023800 	.word	0x40023800
-
-08000818 <HAL_CAN_MspInit>:
-* This function configures the hardware resources used in this example
-* @param hcan: CAN handle pointer
-* @retval None
-*/
-void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
-{
- 8000818:	b580      	push	{r7, lr}
- 800081a:	b08a      	sub	sp, #40	; 0x28
- 800081c:	af00      	add	r7, sp, #0
- 800081e:	6078      	str	r0, [r7, #4]
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8000820:	f107 0314 	add.w	r3, r7, #20
- 8000824:	2200      	movs	r2, #0
- 8000826:	601a      	str	r2, [r3, #0]
- 8000828:	605a      	str	r2, [r3, #4]
- 800082a:	609a      	str	r2, [r3, #8]
- 800082c:	60da      	str	r2, [r3, #12]
- 800082e:	611a      	str	r2, [r3, #16]
-  if(hcan->Instance==CAN1)
- 8000830:	687b      	ldr	r3, [r7, #4]
- 8000832:	681b      	ldr	r3, [r3, #0]
- 8000834:	4a19      	ldr	r2, [pc, #100]	; (800089c <HAL_CAN_MspInit+0x84>)
- 8000836:	4293      	cmp	r3, r2
- 8000838:	d12c      	bne.n	8000894 <HAL_CAN_MspInit+0x7c>
-  {
-  /* USER CODE BEGIN CAN1_MspInit 0 */
-
-  /* USER CODE END CAN1_MspInit 0 */
-    /* Peripheral clock enable */
-    __HAL_RCC_CAN1_CLK_ENABLE();
- 800083a:	2300      	movs	r3, #0
- 800083c:	613b      	str	r3, [r7, #16]
- 800083e:	4b18      	ldr	r3, [pc, #96]	; (80008a0 <HAL_CAN_MspInit+0x88>)
- 8000840:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 8000842:	4a17      	ldr	r2, [pc, #92]	; (80008a0 <HAL_CAN_MspInit+0x88>)
- 8000844:	f043 7300 	orr.w	r3, r3, #33554432	; 0x2000000
- 8000848:	6413      	str	r3, [r2, #64]	; 0x40
- 800084a:	4b15      	ldr	r3, [pc, #84]	; (80008a0 <HAL_CAN_MspInit+0x88>)
- 800084c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 800084e:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
- 8000852:	613b      	str	r3, [r7, #16]
- 8000854:	693b      	ldr	r3, [r7, #16]
-
-    __HAL_RCC_GPIOA_CLK_ENABLE();
- 8000856:	2300      	movs	r3, #0
- 8000858:	60fb      	str	r3, [r7, #12]
- 800085a:	4b11      	ldr	r3, [pc, #68]	; (80008a0 <HAL_CAN_MspInit+0x88>)
- 800085c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 800085e:	4a10      	ldr	r2, [pc, #64]	; (80008a0 <HAL_CAN_MspInit+0x88>)
- 8000860:	f043 0301 	orr.w	r3, r3, #1
- 8000864:	6313      	str	r3, [r2, #48]	; 0x30
- 8000866:	4b0e      	ldr	r3, [pc, #56]	; (80008a0 <HAL_CAN_MspInit+0x88>)
- 8000868:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 800086a:	f003 0301 	and.w	r3, r3, #1
- 800086e:	60fb      	str	r3, [r7, #12]
- 8000870:	68fb      	ldr	r3, [r7, #12]
-    /**CAN1 GPIO Configuration
-    PA11     ------> CAN1_RX
-    PA12     ------> CAN1_TX
-    */
-    GPIO_InitStruct.Pin = GPIO_PIN_11|GPIO_PIN_12;
- 8000872:	f44f 53c0 	mov.w	r3, #6144	; 0x1800
- 8000876:	617b      	str	r3, [r7, #20]
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8000878:	2302      	movs	r3, #2
- 800087a:	61bb      	str	r3, [r7, #24]
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800087c:	2300      	movs	r3, #0
- 800087e:	61fb      	str	r3, [r7, #28]
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 8000880:	2303      	movs	r3, #3
- 8000882:	623b      	str	r3, [r7, #32]
-    GPIO_InitStruct.Alternate = GPIO_AF9_CAN1;
- 8000884:	2309      	movs	r3, #9
- 8000886:	627b      	str	r3, [r7, #36]	; 0x24
-    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 8000888:	f107 0314 	add.w	r3, r7, #20
- 800088c:	4619      	mov	r1, r3
- 800088e:	4805      	ldr	r0, [pc, #20]	; (80008a4 <HAL_CAN_MspInit+0x8c>)
- 8000890:	f000 fe46 	bl	8001520 <HAL_GPIO_Init>
-  /* USER CODE BEGIN CAN1_MspInit 1 */
-
-  /* USER CODE END CAN1_MspInit 1 */
-  }
-
-}
- 8000894:	bf00      	nop
- 8000896:	3728      	adds	r7, #40	; 0x28
- 8000898:	46bd      	mov	sp, r7
- 800089a:	bd80      	pop	{r7, pc}
- 800089c:	40006400 	.word	0x40006400
- 80008a0:	40023800 	.word	0x40023800
- 80008a4:	40020000 	.word	0x40020000
-
-080008a8 <HAL_UART_MspInit>:
-* This function configures the hardware resources used in this example
-* @param huart: UART handle pointer
-* @retval None
-*/
-void HAL_UART_MspInit(UART_HandleTypeDef* huart)
-{
- 80008a8:	b580      	push	{r7, lr}
- 80008aa:	b08a      	sub	sp, #40	; 0x28
- 80008ac:	af00      	add	r7, sp, #0
- 80008ae:	6078      	str	r0, [r7, #4]
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
- 80008b0:	f107 0314 	add.w	r3, r7, #20
- 80008b4:	2200      	movs	r2, #0
- 80008b6:	601a      	str	r2, [r3, #0]
- 80008b8:	605a      	str	r2, [r3, #4]
- 80008ba:	609a      	str	r2, [r3, #8]
- 80008bc:	60da      	str	r2, [r3, #12]
- 80008be:	611a      	str	r2, [r3, #16]
-  if(huart->Instance==UART4)
- 80008c0:	687b      	ldr	r3, [r7, #4]
- 80008c2:	681b      	ldr	r3, [r3, #0]
- 80008c4:	4a19      	ldr	r2, [pc, #100]	; (800092c <HAL_UART_MspInit+0x84>)
- 80008c6:	4293      	cmp	r3, r2
- 80008c8:	d12b      	bne.n	8000922 <HAL_UART_MspInit+0x7a>
-  {
-  /* USER CODE BEGIN UART4_MspInit 0 */
-
-  /* USER CODE END UART4_MspInit 0 */
-    /* Peripheral clock enable */
-    __HAL_RCC_UART4_CLK_ENABLE();
- 80008ca:	2300      	movs	r3, #0
- 80008cc:	613b      	str	r3, [r7, #16]
- 80008ce:	4b18      	ldr	r3, [pc, #96]	; (8000930 <HAL_UART_MspInit+0x88>)
- 80008d0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 80008d2:	4a17      	ldr	r2, [pc, #92]	; (8000930 <HAL_UART_MspInit+0x88>)
- 80008d4:	f443 2300 	orr.w	r3, r3, #524288	; 0x80000
- 80008d8:	6413      	str	r3, [r2, #64]	; 0x40
- 80008da:	4b15      	ldr	r3, [pc, #84]	; (8000930 <HAL_UART_MspInit+0x88>)
- 80008dc:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 80008de:	f403 2300 	and.w	r3, r3, #524288	; 0x80000
- 80008e2:	613b      	str	r3, [r7, #16]
- 80008e4:	693b      	ldr	r3, [r7, #16]
-
-    __HAL_RCC_GPIOA_CLK_ENABLE();
- 80008e6:	2300      	movs	r3, #0
- 80008e8:	60fb      	str	r3, [r7, #12]
- 80008ea:	4b11      	ldr	r3, [pc, #68]	; (8000930 <HAL_UART_MspInit+0x88>)
- 80008ec:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 80008ee:	4a10      	ldr	r2, [pc, #64]	; (8000930 <HAL_UART_MspInit+0x88>)
- 80008f0:	f043 0301 	orr.w	r3, r3, #1
- 80008f4:	6313      	str	r3, [r2, #48]	; 0x30
- 80008f6:	4b0e      	ldr	r3, [pc, #56]	; (8000930 <HAL_UART_MspInit+0x88>)
- 80008f8:	6b1b      	ldr	r3, [r3, #48]	; 0x30
- 80008fa:	f003 0301 	and.w	r3, r3, #1
- 80008fe:	60fb      	str	r3, [r7, #12]
- 8000900:	68fb      	ldr	r3, [r7, #12]
-    /**UART4 GPIO Configuration
-    PA0-WKUP     ------> UART4_TX
-    PA1     ------> UART4_RX
-    */
-    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1;
- 8000902:	2303      	movs	r3, #3
- 8000904:	617b      	str	r3, [r7, #20]
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8000906:	2302      	movs	r3, #2
- 8000908:	61bb      	str	r3, [r7, #24]
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
- 800090a:	2300      	movs	r3, #0
- 800090c:	61fb      	str	r3, [r7, #28]
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
- 800090e:	2303      	movs	r3, #3
- 8000910:	623b      	str	r3, [r7, #32]
-    GPIO_InitStruct.Alternate = GPIO_AF8_UART4;
- 8000912:	2308      	movs	r3, #8
- 8000914:	627b      	str	r3, [r7, #36]	; 0x24
-    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 8000916:	f107 0314 	add.w	r3, r7, #20
- 800091a:	4619      	mov	r1, r3
- 800091c:	4805      	ldr	r0, [pc, #20]	; (8000934 <HAL_UART_MspInit+0x8c>)
- 800091e:	f000 fdff 	bl	8001520 <HAL_GPIO_Init>
-  /* USER CODE BEGIN UART4_MspInit 1 */
-
-  /* USER CODE END UART4_MspInit 1 */
-  }
-
-}
- 8000922:	bf00      	nop
- 8000924:	3728      	adds	r7, #40	; 0x28
- 8000926:	46bd      	mov	sp, r7
- 8000928:	bd80      	pop	{r7, pc}
- 800092a:	bf00      	nop
- 800092c:	40004c00 	.word	0x40004c00
- 8000930:	40023800 	.word	0x40023800
- 8000934:	40020000 	.word	0x40020000
-
-08000938 <NMI_Handler>:
-/******************************************************************************/
-/**
-  * @brief This function handles Non maskable interrupt.
-  */
-void NMI_Handler(void)
-{
- 8000938:	b480      	push	{r7}
- 800093a:	af00      	add	r7, sp, #0
-  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
-
-  /* USER CODE END NonMaskableInt_IRQn 0 */
-  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
-  while (1)
- 800093c:	e7fe      	b.n	800093c <NMI_Handler+0x4>
-
-0800093e <HardFault_Handler>:
-
-/**
-  * @brief This function handles Hard fault interrupt.
-  */
-void HardFault_Handler(void)
-{
- 800093e:	b480      	push	{r7}
- 8000940:	af00      	add	r7, sp, #0
-  /* USER CODE BEGIN HardFault_IRQn 0 */
-
-  /* USER CODE END HardFault_IRQn 0 */
-  while (1)
- 8000942:	e7fe      	b.n	8000942 <HardFault_Handler+0x4>
-
-08000944 <MemManage_Handler>:
-
-/**
-  * @brief This function handles Memory management fault.
-  */
-void MemManage_Handler(void)
-{
- 8000944:	b480      	push	{r7}
- 8000946:	af00      	add	r7, sp, #0
-  /* USER CODE BEGIN MemoryManagement_IRQn 0 */
-
-  /* USER CODE END MemoryManagement_IRQn 0 */
-  while (1)
- 8000948:	e7fe      	b.n	8000948 <MemManage_Handler+0x4>
-
-0800094a <BusFault_Handler>:
-
-/**
-  * @brief This function handles Pre-fetch fault, memory access fault.
-  */
-void BusFault_Handler(void)
-{
- 800094a:	b480      	push	{r7}
- 800094c:	af00      	add	r7, sp, #0
-  /* USER CODE BEGIN BusFault_IRQn 0 */
-
-  /* USER CODE END BusFault_IRQn 0 */
-  while (1)
- 800094e:	e7fe      	b.n	800094e <BusFault_Handler+0x4>
-
-08000950 <UsageFault_Handler>:
-
-/**
-  * @brief This function handles Undefined instruction or illegal state.
-  */
-void UsageFault_Handler(void)
-{
- 8000950:	b480      	push	{r7}
- 8000952:	af00      	add	r7, sp, #0
-  /* USER CODE BEGIN UsageFault_IRQn 0 */
-
-  /* USER CODE END UsageFault_IRQn 0 */
-  while (1)
- 8000954:	e7fe      	b.n	8000954 <UsageFault_Handler+0x4>
-
-08000956 <SVC_Handler>:
-
-/**
-  * @brief This function handles System service call via SWI instruction.
-  */
-void SVC_Handler(void)
-{
- 8000956:	b480      	push	{r7}
- 8000958:	af00      	add	r7, sp, #0
-
-  /* USER CODE END SVCall_IRQn 0 */
-  /* USER CODE BEGIN SVCall_IRQn 1 */
-
-  /* USER CODE END SVCall_IRQn 1 */
-}
- 800095a:	bf00      	nop
- 800095c:	46bd      	mov	sp, r7
- 800095e:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000962:	4770      	bx	lr
-
-08000964 <DebugMon_Handler>:
-
-/**
-  * @brief This function handles Debug monitor.
-  */
-void DebugMon_Handler(void)
-{
- 8000964:	b480      	push	{r7}
- 8000966:	af00      	add	r7, sp, #0
-
-  /* USER CODE END DebugMonitor_IRQn 0 */
-  /* USER CODE BEGIN DebugMonitor_IRQn 1 */
-
-  /* USER CODE END DebugMonitor_IRQn 1 */
-}
- 8000968:	bf00      	nop
- 800096a:	46bd      	mov	sp, r7
- 800096c:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000970:	4770      	bx	lr
-
-08000972 <PendSV_Handler>:
-
-/**
-  * @brief This function handles Pendable request for system service.
-  */
-void PendSV_Handler(void)
-{
- 8000972:	b480      	push	{r7}
- 8000974:	af00      	add	r7, sp, #0
-
-  /* USER CODE END PendSV_IRQn 0 */
-  /* USER CODE BEGIN PendSV_IRQn 1 */
-
-  /* USER CODE END PendSV_IRQn 1 */
-}
- 8000976:	bf00      	nop
- 8000978:	46bd      	mov	sp, r7
- 800097a:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800097e:	4770      	bx	lr
-
-08000980 <SysTick_Handler>:
-
-/**
-  * @brief This function handles System tick timer.
-  */
-void SysTick_Handler(void)
-{
- 8000980:	b580      	push	{r7, lr}
- 8000982:	af00      	add	r7, sp, #0
-  /* USER CODE BEGIN SysTick_IRQn 0 */
-
-  /* USER CODE END SysTick_IRQn 0 */
-  HAL_IncTick();
- 8000984:	f000 f890 	bl	8000aa8 <HAL_IncTick>
-  /* USER CODE BEGIN SysTick_IRQn 1 */
-
-  /* USER CODE END SysTick_IRQn 1 */
-}
- 8000988:	bf00      	nop
- 800098a:	bd80      	pop	{r7, pc}
-
-0800098c <SystemInit>:
-  *         configuration.
-  * @param  None
-  * @retval None
-  */
-void SystemInit(void)
-{
- 800098c:	b480      	push	{r7}
- 800098e:	af00      	add	r7, sp, #0
-  /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
- 8000990:	4b06      	ldr	r3, [pc, #24]	; (80009ac <SystemInit+0x20>)
- 8000992:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
- 8000996:	4a05      	ldr	r2, [pc, #20]	; (80009ac <SystemInit+0x20>)
- 8000998:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
- 800099c:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88
-
-  /* Configure the Vector Table location -------------------------------------*/
-#if defined(USER_VECT_TAB_ADDRESS)
-  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#endif /* USER_VECT_TAB_ADDRESS */
-}
- 80009a0:	bf00      	nop
- 80009a2:	46bd      	mov	sp, r7
- 80009a4:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80009a8:	4770      	bx	lr
- 80009aa:	bf00      	nop
- 80009ac:	e000ed00 	.word	0xe000ed00
-
-080009b0 <Reset_Handler>:
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:  
-  ldr   sp, =_estack     /* set stack pointer */
- 80009b0:	f8df d034 	ldr.w	sp, [pc, #52]	; 80009e8 <LoopFillZerobss+0x12>
-
-/* Copy the data segment initializers from flash to SRAM */  
-  ldr r0, =_sdata
- 80009b4:	480d      	ldr	r0, [pc, #52]	; (80009ec <LoopFillZerobss+0x16>)
-  ldr r1, =_edata
- 80009b6:	490e      	ldr	r1, [pc, #56]	; (80009f0 <LoopFillZerobss+0x1a>)
-  ldr r2, =_sidata
- 80009b8:	4a0e      	ldr	r2, [pc, #56]	; (80009f4 <LoopFillZerobss+0x1e>)
-  movs r3, #0
- 80009ba:	2300      	movs	r3, #0
-  b LoopCopyDataInit
- 80009bc:	e002      	b.n	80009c4 <LoopCopyDataInit>
-
-080009be <CopyDataInit>:
-
-CopyDataInit:
-  ldr r4, [r2, r3]
- 80009be:	58d4      	ldr	r4, [r2, r3]
-  str r4, [r0, r3]
- 80009c0:	50c4      	str	r4, [r0, r3]
-  adds r3, r3, #4
- 80009c2:	3304      	adds	r3, #4
-
-080009c4 <LoopCopyDataInit>:
-
-LoopCopyDataInit:
-  adds r4, r0, r3
- 80009c4:	18c4      	adds	r4, r0, r3
-  cmp r4, r1
- 80009c6:	428c      	cmp	r4, r1
-  bcc CopyDataInit
- 80009c8:	d3f9      	bcc.n	80009be <CopyDataInit>
-  
-/* Zero fill the bss segment. */
-  ldr r2, =_sbss
- 80009ca:	4a0b      	ldr	r2, [pc, #44]	; (80009f8 <LoopFillZerobss+0x22>)
-  ldr r4, =_ebss
- 80009cc:	4c0b      	ldr	r4, [pc, #44]	; (80009fc <LoopFillZerobss+0x26>)
-  movs r3, #0
- 80009ce:	2300      	movs	r3, #0
-  b LoopFillZerobss
- 80009d0:	e001      	b.n	80009d6 <LoopFillZerobss>
-
-080009d2 <FillZerobss>:
-
-FillZerobss:
-  str  r3, [r2]
- 80009d2:	6013      	str	r3, [r2, #0]
-  adds r2, r2, #4
- 80009d4:	3204      	adds	r2, #4
-
-080009d6 <LoopFillZerobss>:
-
-LoopFillZerobss:
-  cmp r2, r4
- 80009d6:	42a2      	cmp	r2, r4
-  bcc FillZerobss
- 80009d8:	d3fb      	bcc.n	80009d2 <FillZerobss>
-
-/* Call the clock system initialization function.*/
-  bl  SystemInit   
- 80009da:	f7ff ffd7 	bl	800098c <SystemInit>
-/* Call static constructors */
-    bl __libc_init_array
- 80009de:	f002 f8c3 	bl	8002b68 <__libc_init_array>
-/* Call the application's entry point.*/
-  bl  main
- 80009e2:	f7ff fdaf 	bl	8000544 <main>
-  bx  lr    
- 80009e6:	4770      	bx	lr
-  ldr   sp, =_estack     /* set stack pointer */
- 80009e8:	20020000 	.word	0x20020000
-  ldr r0, =_sdata
- 80009ec:	20000000 	.word	0x20000000
-  ldr r1, =_edata
- 80009f0:	2000000c 	.word	0x2000000c
-  ldr r2, =_sidata
- 80009f4:	08002cac 	.word	0x08002cac
-  ldr r2, =_sbss
- 80009f8:	2000000c 	.word	0x2000000c
-  ldr r4, =_ebss
- 80009fc:	20000098 	.word	0x20000098
-
-08000a00 <ADC_IRQHandler>:
- * @retval None       
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
- 8000a00:	e7fe      	b.n	8000a00 <ADC_IRQHandler>
-	...
-
-08000a04 <HAL_Init>:
-  *         need to ensure that the SysTick time base is always set to 1 millisecond
-  *         to have correct HAL operation.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_Init(void)
-{
- 8000a04:	b580      	push	{r7, lr}
- 8000a06:	af00      	add	r7, sp, #0
-  /* Configure Flash prefetch, Instruction cache, Data cache */ 
-#if (INSTRUCTION_CACHE_ENABLE != 0U)
-  __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
- 8000a08:	4b0e      	ldr	r3, [pc, #56]	; (8000a44 <HAL_Init+0x40>)
- 8000a0a:	681b      	ldr	r3, [r3, #0]
- 8000a0c:	4a0d      	ldr	r2, [pc, #52]	; (8000a44 <HAL_Init+0x40>)
- 8000a0e:	f443 7300 	orr.w	r3, r3, #512	; 0x200
- 8000a12:	6013      	str	r3, [r2, #0]
-#endif /* INSTRUCTION_CACHE_ENABLE */
-
-#if (DATA_CACHE_ENABLE != 0U)
-  __HAL_FLASH_DATA_CACHE_ENABLE();
- 8000a14:	4b0b      	ldr	r3, [pc, #44]	; (8000a44 <HAL_Init+0x40>)
- 8000a16:	681b      	ldr	r3, [r3, #0]
- 8000a18:	4a0a      	ldr	r2, [pc, #40]	; (8000a44 <HAL_Init+0x40>)
- 8000a1a:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
- 8000a1e:	6013      	str	r3, [r2, #0]
-#endif /* DATA_CACHE_ENABLE */
-
-#if (PREFETCH_ENABLE != 0U)
-  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
- 8000a20:	4b08      	ldr	r3, [pc, #32]	; (8000a44 <HAL_Init+0x40>)
- 8000a22:	681b      	ldr	r3, [r3, #0]
- 8000a24:	4a07      	ldr	r2, [pc, #28]	; (8000a44 <HAL_Init+0x40>)
- 8000a26:	f443 7380 	orr.w	r3, r3, #256	; 0x100
- 8000a2a:	6013      	str	r3, [r2, #0]
-#endif /* PREFETCH_ENABLE */
-
-  /* Set Interrupt Group Priority */
-  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
- 8000a2c:	2003      	movs	r0, #3
- 8000a2e:	f000 fd43 	bl	80014b8 <HAL_NVIC_SetPriorityGrouping>
-
-  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
-  HAL_InitTick(TICK_INT_PRIORITY);
- 8000a32:	200f      	movs	r0, #15
- 8000a34:	f000 f808 	bl	8000a48 <HAL_InitTick>
-
-  /* Init the low level hardware */
-  HAL_MspInit();
- 8000a38:	f7ff fec6 	bl	80007c8 <HAL_MspInit>
-
-  /* Return function status */
-  return HAL_OK;
- 8000a3c:	2300      	movs	r3, #0
-}
- 8000a3e:	4618      	mov	r0, r3
- 8000a40:	bd80      	pop	{r7, pc}
- 8000a42:	bf00      	nop
- 8000a44:	40023c00 	.word	0x40023c00
-
-08000a48 <HAL_InitTick>:
-  *       implementation  in user file.
-  * @param TickPriority Tick interrupt priority.
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
- 8000a48:	b580      	push	{r7, lr}
- 8000a4a:	b082      	sub	sp, #8
- 8000a4c:	af00      	add	r7, sp, #0
- 8000a4e:	6078      	str	r0, [r7, #4]
-  /* Configure the SysTick to have interrupt in 1ms time basis*/
-  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
- 8000a50:	4b12      	ldr	r3, [pc, #72]	; (8000a9c <HAL_InitTick+0x54>)
- 8000a52:	681a      	ldr	r2, [r3, #0]
- 8000a54:	4b12      	ldr	r3, [pc, #72]	; (8000aa0 <HAL_InitTick+0x58>)
- 8000a56:	781b      	ldrb	r3, [r3, #0]
- 8000a58:	4619      	mov	r1, r3
- 8000a5a:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
- 8000a5e:	fbb3 f3f1 	udiv	r3, r3, r1
- 8000a62:	fbb2 f3f3 	udiv	r3, r2, r3
- 8000a66:	4618      	mov	r0, r3
- 8000a68:	f000 fd4d 	bl	8001506 <HAL_SYSTICK_Config>
- 8000a6c:	4603      	mov	r3, r0
- 8000a6e:	2b00      	cmp	r3, #0
- 8000a70:	d001      	beq.n	8000a76 <HAL_InitTick+0x2e>
-  {
-    return HAL_ERROR;
- 8000a72:	2301      	movs	r3, #1
- 8000a74:	e00e      	b.n	8000a94 <HAL_InitTick+0x4c>
-  }
-
-  /* Configure the SysTick IRQ priority */
-  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- 8000a76:	687b      	ldr	r3, [r7, #4]
- 8000a78:	2b0f      	cmp	r3, #15
- 8000a7a:	d80a      	bhi.n	8000a92 <HAL_InitTick+0x4a>
-  {
-    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- 8000a7c:	2200      	movs	r2, #0
- 8000a7e:	6879      	ldr	r1, [r7, #4]
- 8000a80:	f04f 30ff 	mov.w	r0, #4294967295
- 8000a84:	f000 fd23 	bl	80014ce <HAL_NVIC_SetPriority>
-    uwTickPrio = TickPriority;
- 8000a88:	4a06      	ldr	r2, [pc, #24]	; (8000aa4 <HAL_InitTick+0x5c>)
- 8000a8a:	687b      	ldr	r3, [r7, #4]
- 8000a8c:	6013      	str	r3, [r2, #0]
-  {
-    return HAL_ERROR;
-  }
-
-  /* Return function status */
-  return HAL_OK;
- 8000a8e:	2300      	movs	r3, #0
- 8000a90:	e000      	b.n	8000a94 <HAL_InitTick+0x4c>
-    return HAL_ERROR;
- 8000a92:	2301      	movs	r3, #1
-}
- 8000a94:	4618      	mov	r0, r3
- 8000a96:	3708      	adds	r7, #8
- 8000a98:	46bd      	mov	sp, r7
- 8000a9a:	bd80      	pop	{r7, pc}
- 8000a9c:	20000000 	.word	0x20000000
- 8000aa0:	20000008 	.word	0x20000008
- 8000aa4:	20000004 	.word	0x20000004
-
-08000aa8 <HAL_IncTick>:
- * @note This function is declared as __weak to be overwritten in case of other 
-  *      implementations in user file.
-  * @retval None
-  */
-__weak void HAL_IncTick(void)
-{
- 8000aa8:	b480      	push	{r7}
- 8000aaa:	af00      	add	r7, sp, #0
-  uwTick += uwTickFreq;
- 8000aac:	4b06      	ldr	r3, [pc, #24]	; (8000ac8 <HAL_IncTick+0x20>)
- 8000aae:	781b      	ldrb	r3, [r3, #0]
- 8000ab0:	461a      	mov	r2, r3
- 8000ab2:	4b06      	ldr	r3, [pc, #24]	; (8000acc <HAL_IncTick+0x24>)
- 8000ab4:	681b      	ldr	r3, [r3, #0]
- 8000ab6:	4413      	add	r3, r2
- 8000ab8:	4a04      	ldr	r2, [pc, #16]	; (8000acc <HAL_IncTick+0x24>)
- 8000aba:	6013      	str	r3, [r2, #0]
-}
- 8000abc:	bf00      	nop
- 8000abe:	46bd      	mov	sp, r7
- 8000ac0:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000ac4:	4770      	bx	lr
- 8000ac6:	bf00      	nop
- 8000ac8:	20000008 	.word	0x20000008
- 8000acc:	20000094 	.word	0x20000094
-
-08000ad0 <HAL_GetTick>:
-  * @note This function is declared as __weak to be overwritten in case of other 
-  *       implementations in user file.
-  * @retval tick value
-  */
-__weak uint32_t HAL_GetTick(void)
-{
- 8000ad0:	b480      	push	{r7}
- 8000ad2:	af00      	add	r7, sp, #0
-  return uwTick;
- 8000ad4:	4b03      	ldr	r3, [pc, #12]	; (8000ae4 <HAL_GetTick+0x14>)
- 8000ad6:	681b      	ldr	r3, [r3, #0]
-}
- 8000ad8:	4618      	mov	r0, r3
- 8000ada:	46bd      	mov	sp, r7
- 8000adc:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000ae0:	4770      	bx	lr
- 8000ae2:	bf00      	nop
- 8000ae4:	20000094 	.word	0x20000094
-
-08000ae8 <HAL_CAN_Init>:
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
-{
- 8000ae8:	b580      	push	{r7, lr}
- 8000aea:	b084      	sub	sp, #16
- 8000aec:	af00      	add	r7, sp, #0
- 8000aee:	6078      	str	r0, [r7, #4]
-  uint32_t tickstart;
-
-  /* Check CAN handle */
-  if (hcan == NULL)
- 8000af0:	687b      	ldr	r3, [r7, #4]
- 8000af2:	2b00      	cmp	r3, #0
- 8000af4:	d101      	bne.n	8000afa <HAL_CAN_Init+0x12>
-  {
-    return HAL_ERROR;
- 8000af6:	2301      	movs	r3, #1
- 8000af8:	e0ed      	b.n	8000cd6 <HAL_CAN_Init+0x1ee>
-    /* Init the low level hardware: CLOCK, NVIC */
-    hcan->MspInitCallback(hcan);
-  }
-
-#else
-  if (hcan->State == HAL_CAN_STATE_RESET)
- 8000afa:	687b      	ldr	r3, [r7, #4]
- 8000afc:	f893 3020 	ldrb.w	r3, [r3, #32]
- 8000b00:	b2db      	uxtb	r3, r3
- 8000b02:	2b00      	cmp	r3, #0
- 8000b04:	d102      	bne.n	8000b0c <HAL_CAN_Init+0x24>
-  {
-    /* Init the low level hardware: CLOCK, NVIC */
-    HAL_CAN_MspInit(hcan);
- 8000b06:	6878      	ldr	r0, [r7, #4]
- 8000b08:	f7ff fe86 	bl	8000818 <HAL_CAN_MspInit>
-  }
-#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
-
-  /* Request initialisation */
-  SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
- 8000b0c:	687b      	ldr	r3, [r7, #4]
- 8000b0e:	681b      	ldr	r3, [r3, #0]
- 8000b10:	681a      	ldr	r2, [r3, #0]
- 8000b12:	687b      	ldr	r3, [r7, #4]
- 8000b14:	681b      	ldr	r3, [r3, #0]
- 8000b16:	f042 0201 	orr.w	r2, r2, #1
- 8000b1a:	601a      	str	r2, [r3, #0]
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
- 8000b1c:	f7ff ffd8 	bl	8000ad0 <HAL_GetTick>
- 8000b20:	60f8      	str	r0, [r7, #12]
-
-  /* Wait initialisation acknowledge */
-  while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
- 8000b22:	e012      	b.n	8000b4a <HAL_CAN_Init+0x62>
-  {
-    if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
- 8000b24:	f7ff ffd4 	bl	8000ad0 <HAL_GetTick>
- 8000b28:	4602      	mov	r2, r0
- 8000b2a:	68fb      	ldr	r3, [r7, #12]
- 8000b2c:	1ad3      	subs	r3, r2, r3
- 8000b2e:	2b0a      	cmp	r3, #10
- 8000b30:	d90b      	bls.n	8000b4a <HAL_CAN_Init+0x62>
-    {
-      /* Update error code */
-      hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
- 8000b32:	687b      	ldr	r3, [r7, #4]
- 8000b34:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8000b36:	f443 3200 	orr.w	r2, r3, #131072	; 0x20000
- 8000b3a:	687b      	ldr	r3, [r7, #4]
- 8000b3c:	625a      	str	r2, [r3, #36]	; 0x24
-
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_ERROR;
- 8000b3e:	687b      	ldr	r3, [r7, #4]
- 8000b40:	2205      	movs	r2, #5
- 8000b42:	f883 2020 	strb.w	r2, [r3, #32]
-
-      return HAL_ERROR;
- 8000b46:	2301      	movs	r3, #1
- 8000b48:	e0c5      	b.n	8000cd6 <HAL_CAN_Init+0x1ee>
-  while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
- 8000b4a:	687b      	ldr	r3, [r7, #4]
- 8000b4c:	681b      	ldr	r3, [r3, #0]
- 8000b4e:	685b      	ldr	r3, [r3, #4]
- 8000b50:	f003 0301 	and.w	r3, r3, #1
- 8000b54:	2b00      	cmp	r3, #0
- 8000b56:	d0e5      	beq.n	8000b24 <HAL_CAN_Init+0x3c>
-    }
-  }
-
-  /* Exit from sleep mode */
-  CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
- 8000b58:	687b      	ldr	r3, [r7, #4]
- 8000b5a:	681b      	ldr	r3, [r3, #0]
- 8000b5c:	681a      	ldr	r2, [r3, #0]
- 8000b5e:	687b      	ldr	r3, [r7, #4]
- 8000b60:	681b      	ldr	r3, [r3, #0]
- 8000b62:	f022 0202 	bic.w	r2, r2, #2
- 8000b66:	601a      	str	r2, [r3, #0]
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
- 8000b68:	f7ff ffb2 	bl	8000ad0 <HAL_GetTick>
- 8000b6c:	60f8      	str	r0, [r7, #12]
-
-  /* Check Sleep mode leave acknowledge */
-  while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
- 8000b6e:	e012      	b.n	8000b96 <HAL_CAN_Init+0xae>
-  {
-    if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
- 8000b70:	f7ff ffae 	bl	8000ad0 <HAL_GetTick>
- 8000b74:	4602      	mov	r2, r0
- 8000b76:	68fb      	ldr	r3, [r7, #12]
- 8000b78:	1ad3      	subs	r3, r2, r3
- 8000b7a:	2b0a      	cmp	r3, #10
- 8000b7c:	d90b      	bls.n	8000b96 <HAL_CAN_Init+0xae>
-    {
-      /* Update error code */
-      hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
- 8000b7e:	687b      	ldr	r3, [r7, #4]
- 8000b80:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8000b82:	f443 3200 	orr.w	r2, r3, #131072	; 0x20000
- 8000b86:	687b      	ldr	r3, [r7, #4]
- 8000b88:	625a      	str	r2, [r3, #36]	; 0x24
-
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_ERROR;
- 8000b8a:	687b      	ldr	r3, [r7, #4]
- 8000b8c:	2205      	movs	r2, #5
- 8000b8e:	f883 2020 	strb.w	r2, [r3, #32]
-
-      return HAL_ERROR;
- 8000b92:	2301      	movs	r3, #1
- 8000b94:	e09f      	b.n	8000cd6 <HAL_CAN_Init+0x1ee>
-  while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
- 8000b96:	687b      	ldr	r3, [r7, #4]
- 8000b98:	681b      	ldr	r3, [r3, #0]
- 8000b9a:	685b      	ldr	r3, [r3, #4]
- 8000b9c:	f003 0302 	and.w	r3, r3, #2
- 8000ba0:	2b00      	cmp	r3, #0
- 8000ba2:	d1e5      	bne.n	8000b70 <HAL_CAN_Init+0x88>
-    }
-  }
-
-  /* Set the time triggered communication mode */
-  if (hcan->Init.TimeTriggeredMode == ENABLE)
- 8000ba4:	687b      	ldr	r3, [r7, #4]
- 8000ba6:	7e1b      	ldrb	r3, [r3, #24]
- 8000ba8:	2b01      	cmp	r3, #1
- 8000baa:	d108      	bne.n	8000bbe <HAL_CAN_Init+0xd6>
-  {
-    SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
- 8000bac:	687b      	ldr	r3, [r7, #4]
- 8000bae:	681b      	ldr	r3, [r3, #0]
- 8000bb0:	681a      	ldr	r2, [r3, #0]
- 8000bb2:	687b      	ldr	r3, [r7, #4]
- 8000bb4:	681b      	ldr	r3, [r3, #0]
- 8000bb6:	f042 0280 	orr.w	r2, r2, #128	; 0x80
- 8000bba:	601a      	str	r2, [r3, #0]
- 8000bbc:	e007      	b.n	8000bce <HAL_CAN_Init+0xe6>
-  }
-  else
-  {
-    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
- 8000bbe:	687b      	ldr	r3, [r7, #4]
- 8000bc0:	681b      	ldr	r3, [r3, #0]
- 8000bc2:	681a      	ldr	r2, [r3, #0]
- 8000bc4:	687b      	ldr	r3, [r7, #4]
- 8000bc6:	681b      	ldr	r3, [r3, #0]
- 8000bc8:	f022 0280 	bic.w	r2, r2, #128	; 0x80
- 8000bcc:	601a      	str	r2, [r3, #0]
-  }
-
-  /* Set the automatic bus-off management */
-  if (hcan->Init.AutoBusOff == ENABLE)
- 8000bce:	687b      	ldr	r3, [r7, #4]
- 8000bd0:	7e5b      	ldrb	r3, [r3, #25]
- 8000bd2:	2b01      	cmp	r3, #1
- 8000bd4:	d108      	bne.n	8000be8 <HAL_CAN_Init+0x100>
-  {
-    SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
- 8000bd6:	687b      	ldr	r3, [r7, #4]
- 8000bd8:	681b      	ldr	r3, [r3, #0]
- 8000bda:	681a      	ldr	r2, [r3, #0]
- 8000bdc:	687b      	ldr	r3, [r7, #4]
- 8000bde:	681b      	ldr	r3, [r3, #0]
- 8000be0:	f042 0240 	orr.w	r2, r2, #64	; 0x40
- 8000be4:	601a      	str	r2, [r3, #0]
- 8000be6:	e007      	b.n	8000bf8 <HAL_CAN_Init+0x110>
-  }
-  else
-  {
-    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
- 8000be8:	687b      	ldr	r3, [r7, #4]
- 8000bea:	681b      	ldr	r3, [r3, #0]
- 8000bec:	681a      	ldr	r2, [r3, #0]
- 8000bee:	687b      	ldr	r3, [r7, #4]
- 8000bf0:	681b      	ldr	r3, [r3, #0]
- 8000bf2:	f022 0240 	bic.w	r2, r2, #64	; 0x40
- 8000bf6:	601a      	str	r2, [r3, #0]
-  }
-
-  /* Set the automatic wake-up mode */
-  if (hcan->Init.AutoWakeUp == ENABLE)
- 8000bf8:	687b      	ldr	r3, [r7, #4]
- 8000bfa:	7e9b      	ldrb	r3, [r3, #26]
- 8000bfc:	2b01      	cmp	r3, #1
- 8000bfe:	d108      	bne.n	8000c12 <HAL_CAN_Init+0x12a>
-  {
-    SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
- 8000c00:	687b      	ldr	r3, [r7, #4]
- 8000c02:	681b      	ldr	r3, [r3, #0]
- 8000c04:	681a      	ldr	r2, [r3, #0]
- 8000c06:	687b      	ldr	r3, [r7, #4]
- 8000c08:	681b      	ldr	r3, [r3, #0]
- 8000c0a:	f042 0220 	orr.w	r2, r2, #32
- 8000c0e:	601a      	str	r2, [r3, #0]
- 8000c10:	e007      	b.n	8000c22 <HAL_CAN_Init+0x13a>
-  }
-  else
-  {
-    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
- 8000c12:	687b      	ldr	r3, [r7, #4]
- 8000c14:	681b      	ldr	r3, [r3, #0]
- 8000c16:	681a      	ldr	r2, [r3, #0]
- 8000c18:	687b      	ldr	r3, [r7, #4]
- 8000c1a:	681b      	ldr	r3, [r3, #0]
- 8000c1c:	f022 0220 	bic.w	r2, r2, #32
- 8000c20:	601a      	str	r2, [r3, #0]
-  }
-
-  /* Set the automatic retransmission */
-  if (hcan->Init.AutoRetransmission == ENABLE)
- 8000c22:	687b      	ldr	r3, [r7, #4]
- 8000c24:	7edb      	ldrb	r3, [r3, #27]
- 8000c26:	2b01      	cmp	r3, #1
- 8000c28:	d108      	bne.n	8000c3c <HAL_CAN_Init+0x154>
-  {
-    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
- 8000c2a:	687b      	ldr	r3, [r7, #4]
- 8000c2c:	681b      	ldr	r3, [r3, #0]
- 8000c2e:	681a      	ldr	r2, [r3, #0]
- 8000c30:	687b      	ldr	r3, [r7, #4]
- 8000c32:	681b      	ldr	r3, [r3, #0]
- 8000c34:	f022 0210 	bic.w	r2, r2, #16
- 8000c38:	601a      	str	r2, [r3, #0]
- 8000c3a:	e007      	b.n	8000c4c <HAL_CAN_Init+0x164>
-  }
-  else
-  {
-    SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
- 8000c3c:	687b      	ldr	r3, [r7, #4]
- 8000c3e:	681b      	ldr	r3, [r3, #0]
- 8000c40:	681a      	ldr	r2, [r3, #0]
- 8000c42:	687b      	ldr	r3, [r7, #4]
- 8000c44:	681b      	ldr	r3, [r3, #0]
- 8000c46:	f042 0210 	orr.w	r2, r2, #16
- 8000c4a:	601a      	str	r2, [r3, #0]
-  }
-
-  /* Set the receive FIFO locked mode */
-  if (hcan->Init.ReceiveFifoLocked == ENABLE)
- 8000c4c:	687b      	ldr	r3, [r7, #4]
- 8000c4e:	7f1b      	ldrb	r3, [r3, #28]
- 8000c50:	2b01      	cmp	r3, #1
- 8000c52:	d108      	bne.n	8000c66 <HAL_CAN_Init+0x17e>
-  {
-    SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
- 8000c54:	687b      	ldr	r3, [r7, #4]
- 8000c56:	681b      	ldr	r3, [r3, #0]
- 8000c58:	681a      	ldr	r2, [r3, #0]
- 8000c5a:	687b      	ldr	r3, [r7, #4]
- 8000c5c:	681b      	ldr	r3, [r3, #0]
- 8000c5e:	f042 0208 	orr.w	r2, r2, #8
- 8000c62:	601a      	str	r2, [r3, #0]
- 8000c64:	e007      	b.n	8000c76 <HAL_CAN_Init+0x18e>
-  }
-  else
-  {
-    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
- 8000c66:	687b      	ldr	r3, [r7, #4]
- 8000c68:	681b      	ldr	r3, [r3, #0]
- 8000c6a:	681a      	ldr	r2, [r3, #0]
- 8000c6c:	687b      	ldr	r3, [r7, #4]
- 8000c6e:	681b      	ldr	r3, [r3, #0]
- 8000c70:	f022 0208 	bic.w	r2, r2, #8
- 8000c74:	601a      	str	r2, [r3, #0]
-  }
-
-  /* Set the transmit FIFO priority */
-  if (hcan->Init.TransmitFifoPriority == ENABLE)
- 8000c76:	687b      	ldr	r3, [r7, #4]
- 8000c78:	7f5b      	ldrb	r3, [r3, #29]
- 8000c7a:	2b01      	cmp	r3, #1
- 8000c7c:	d108      	bne.n	8000c90 <HAL_CAN_Init+0x1a8>
-  {
-    SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
- 8000c7e:	687b      	ldr	r3, [r7, #4]
- 8000c80:	681b      	ldr	r3, [r3, #0]
- 8000c82:	681a      	ldr	r2, [r3, #0]
- 8000c84:	687b      	ldr	r3, [r7, #4]
- 8000c86:	681b      	ldr	r3, [r3, #0]
- 8000c88:	f042 0204 	orr.w	r2, r2, #4
- 8000c8c:	601a      	str	r2, [r3, #0]
- 8000c8e:	e007      	b.n	8000ca0 <HAL_CAN_Init+0x1b8>
-  }
-  else
-  {
-    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
- 8000c90:	687b      	ldr	r3, [r7, #4]
- 8000c92:	681b      	ldr	r3, [r3, #0]
- 8000c94:	681a      	ldr	r2, [r3, #0]
- 8000c96:	687b      	ldr	r3, [r7, #4]
- 8000c98:	681b      	ldr	r3, [r3, #0]
- 8000c9a:	f022 0204 	bic.w	r2, r2, #4
- 8000c9e:	601a      	str	r2, [r3, #0]
-  }
-
-  /* Set the bit timing register */
-  WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode           |
- 8000ca0:	687b      	ldr	r3, [r7, #4]
- 8000ca2:	689a      	ldr	r2, [r3, #8]
- 8000ca4:	687b      	ldr	r3, [r7, #4]
- 8000ca6:	68db      	ldr	r3, [r3, #12]
- 8000ca8:	431a      	orrs	r2, r3
- 8000caa:	687b      	ldr	r3, [r7, #4]
- 8000cac:	691b      	ldr	r3, [r3, #16]
- 8000cae:	431a      	orrs	r2, r3
- 8000cb0:	687b      	ldr	r3, [r7, #4]
- 8000cb2:	695b      	ldr	r3, [r3, #20]
- 8000cb4:	ea42 0103 	orr.w	r1, r2, r3
- 8000cb8:	687b      	ldr	r3, [r7, #4]
- 8000cba:	685b      	ldr	r3, [r3, #4]
- 8000cbc:	1e5a      	subs	r2, r3, #1
- 8000cbe:	687b      	ldr	r3, [r7, #4]
- 8000cc0:	681b      	ldr	r3, [r3, #0]
- 8000cc2:	430a      	orrs	r2, r1
- 8000cc4:	61da      	str	r2, [r3, #28]
-                                            hcan->Init.TimeSeg1       |
-                                            hcan->Init.TimeSeg2       |
-                                            (hcan->Init.Prescaler - 1U)));
-
-  /* Initialize the error code */
-  hcan->ErrorCode = HAL_CAN_ERROR_NONE;
- 8000cc6:	687b      	ldr	r3, [r7, #4]
- 8000cc8:	2200      	movs	r2, #0
- 8000cca:	625a      	str	r2, [r3, #36]	; 0x24
-
-  /* Initialize the CAN state */
-  hcan->State = HAL_CAN_STATE_READY;
- 8000ccc:	687b      	ldr	r3, [r7, #4]
- 8000cce:	2201      	movs	r2, #1
- 8000cd0:	f883 2020 	strb.w	r2, [r3, #32]
-
-  /* Return function status */
-  return HAL_OK;
- 8000cd4:	2300      	movs	r3, #0
-}
- 8000cd6:	4618      	mov	r0, r3
- 8000cd8:	3710      	adds	r7, #16
- 8000cda:	46bd      	mov	sp, r7
- 8000cdc:	bd80      	pop	{r7, pc}
-	...
-
-08000ce0 <HAL_CAN_ConfigFilter>:
-  * @param  sFilterConfig pointer to a CAN_FilterTypeDef structure that
-  *         contains the filter configuration information.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)
-{
- 8000ce0:	b480      	push	{r7}
- 8000ce2:	b087      	sub	sp, #28
- 8000ce4:	af00      	add	r7, sp, #0
- 8000ce6:	6078      	str	r0, [r7, #4]
- 8000ce8:	6039      	str	r1, [r7, #0]
-  uint32_t filternbrbitpos;
-  CAN_TypeDef *can_ip = hcan->Instance;
- 8000cea:	687b      	ldr	r3, [r7, #4]
- 8000cec:	681b      	ldr	r3, [r3, #0]
- 8000cee:	617b      	str	r3, [r7, #20]
-  HAL_CAN_StateTypeDef state = hcan->State;
- 8000cf0:	687b      	ldr	r3, [r7, #4]
- 8000cf2:	f893 3020 	ldrb.w	r3, [r3, #32]
- 8000cf6:	74fb      	strb	r3, [r7, #19]
-
-  if ((state == HAL_CAN_STATE_READY) ||
- 8000cf8:	7cfb      	ldrb	r3, [r7, #19]
- 8000cfa:	2b01      	cmp	r3, #1
- 8000cfc:	d003      	beq.n	8000d06 <HAL_CAN_ConfigFilter+0x26>
- 8000cfe:	7cfb      	ldrb	r3, [r7, #19]
- 8000d00:	2b02      	cmp	r3, #2
- 8000d02:	f040 80be 	bne.w	8000e82 <HAL_CAN_ConfigFilter+0x1a2>
-      assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
-    }
-#elif defined(CAN2)
-    /* CAN1 and CAN2 are dual instances with 28 common filters banks */
-    /* Select master instance to access the filter banks */
-    can_ip = CAN1;
- 8000d06:	4b65      	ldr	r3, [pc, #404]	; (8000e9c <HAL_CAN_ConfigFilter+0x1bc>)
- 8000d08:	617b      	str	r3, [r7, #20]
-    /* Check the parameters */
-    assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
-#endif
-
-    /* Initialisation mode for the filter */
-    SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
- 8000d0a:	697b      	ldr	r3, [r7, #20]
- 8000d0c:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
- 8000d10:	f043 0201 	orr.w	r2, r3, #1
- 8000d14:	697b      	ldr	r3, [r7, #20]
- 8000d16:	f8c3 2200 	str.w	r2, [r3, #512]	; 0x200
-      SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
-    }
-
-#elif defined(CAN2)
-    /* Select the start filter number of CAN2 slave instance */
-    CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
- 8000d1a:	697b      	ldr	r3, [r7, #20]
- 8000d1c:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
- 8000d20:	f423 527c 	bic.w	r2, r3, #16128	; 0x3f00
- 8000d24:	697b      	ldr	r3, [r7, #20]
- 8000d26:	f8c3 2200 	str.w	r2, [r3, #512]	; 0x200
-    SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
- 8000d2a:	697b      	ldr	r3, [r7, #20]
- 8000d2c:	f8d3 2200 	ldr.w	r2, [r3, #512]	; 0x200
- 8000d30:	683b      	ldr	r3, [r7, #0]
- 8000d32:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8000d34:	021b      	lsls	r3, r3, #8
- 8000d36:	431a      	orrs	r2, r3
- 8000d38:	697b      	ldr	r3, [r7, #20]
- 8000d3a:	f8c3 2200 	str.w	r2, [r3, #512]	; 0x200
-
-#endif
-    /* Convert filter number into bit position */
-    filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
- 8000d3e:	683b      	ldr	r3, [r7, #0]
- 8000d40:	695b      	ldr	r3, [r3, #20]
- 8000d42:	f003 031f 	and.w	r3, r3, #31
- 8000d46:	2201      	movs	r2, #1
- 8000d48:	fa02 f303 	lsl.w	r3, r2, r3
- 8000d4c:	60fb      	str	r3, [r7, #12]
-
-    /* Filter Deactivation */
-    CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
- 8000d4e:	697b      	ldr	r3, [r7, #20]
- 8000d50:	f8d3 221c 	ldr.w	r2, [r3, #540]	; 0x21c
- 8000d54:	68fb      	ldr	r3, [r7, #12]
- 8000d56:	43db      	mvns	r3, r3
- 8000d58:	401a      	ands	r2, r3
- 8000d5a:	697b      	ldr	r3, [r7, #20]
- 8000d5c:	f8c3 221c 	str.w	r2, [r3, #540]	; 0x21c
-
-    /* Filter Scale */
-    if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
- 8000d60:	683b      	ldr	r3, [r7, #0]
- 8000d62:	69db      	ldr	r3, [r3, #28]
- 8000d64:	2b00      	cmp	r3, #0
- 8000d66:	d123      	bne.n	8000db0 <HAL_CAN_ConfigFilter+0xd0>
-    {
-      /* 16-bit scale for the filter */
-      CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
- 8000d68:	697b      	ldr	r3, [r7, #20]
- 8000d6a:	f8d3 220c 	ldr.w	r2, [r3, #524]	; 0x20c
- 8000d6e:	68fb      	ldr	r3, [r7, #12]
- 8000d70:	43db      	mvns	r3, r3
- 8000d72:	401a      	ands	r2, r3
- 8000d74:	697b      	ldr	r3, [r7, #20]
- 8000d76:	f8c3 220c 	str.w	r2, [r3, #524]	; 0x20c
-
-      /* First 16-bit identifier and First 16-bit mask */
-      /* Or First 16-bit identifier and Second 16-bit identifier */
-      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
-        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
- 8000d7a:	683b      	ldr	r3, [r7, #0]
- 8000d7c:	68db      	ldr	r3, [r3, #12]
- 8000d7e:	0419      	lsls	r1, r3, #16
-        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
- 8000d80:	683b      	ldr	r3, [r7, #0]
- 8000d82:	685b      	ldr	r3, [r3, #4]
- 8000d84:	b29b      	uxth	r3, r3
-      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
- 8000d86:	683a      	ldr	r2, [r7, #0]
- 8000d88:	6952      	ldr	r2, [r2, #20]
-        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
- 8000d8a:	4319      	orrs	r1, r3
-      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
- 8000d8c:	697b      	ldr	r3, [r7, #20]
- 8000d8e:	3248      	adds	r2, #72	; 0x48
- 8000d90:	f843 1032 	str.w	r1, [r3, r2, lsl #3]
-
-      /* Second 16-bit identifier and Second 16-bit mask */
-      /* Or Third 16-bit identifier and Fourth 16-bit identifier */
-      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
-        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
- 8000d94:	683b      	ldr	r3, [r7, #0]
- 8000d96:	689b      	ldr	r3, [r3, #8]
- 8000d98:	0419      	lsls	r1, r3, #16
-        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
- 8000d9a:	683b      	ldr	r3, [r7, #0]
- 8000d9c:	681b      	ldr	r3, [r3, #0]
- 8000d9e:	b29a      	uxth	r2, r3
-      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
- 8000da0:	683b      	ldr	r3, [r7, #0]
- 8000da2:	695b      	ldr	r3, [r3, #20]
-        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
- 8000da4:	430a      	orrs	r2, r1
-      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
- 8000da6:	6979      	ldr	r1, [r7, #20]
- 8000da8:	3348      	adds	r3, #72	; 0x48
- 8000daa:	00db      	lsls	r3, r3, #3
- 8000dac:	440b      	add	r3, r1
- 8000dae:	605a      	str	r2, [r3, #4]
-    }
-
-    if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
- 8000db0:	683b      	ldr	r3, [r7, #0]
- 8000db2:	69db      	ldr	r3, [r3, #28]
- 8000db4:	2b01      	cmp	r3, #1
- 8000db6:	d122      	bne.n	8000dfe <HAL_CAN_ConfigFilter+0x11e>
-    {
-      /* 32-bit scale for the filter */
-      SET_BIT(can_ip->FS1R, filternbrbitpos);
- 8000db8:	697b      	ldr	r3, [r7, #20]
- 8000dba:	f8d3 220c 	ldr.w	r2, [r3, #524]	; 0x20c
- 8000dbe:	68fb      	ldr	r3, [r7, #12]
- 8000dc0:	431a      	orrs	r2, r3
- 8000dc2:	697b      	ldr	r3, [r7, #20]
- 8000dc4:	f8c3 220c 	str.w	r2, [r3, #524]	; 0x20c
-
-      /* 32-bit identifier or First 32-bit identifier */
-      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
-        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
- 8000dc8:	683b      	ldr	r3, [r7, #0]
- 8000dca:	681b      	ldr	r3, [r3, #0]
- 8000dcc:	0419      	lsls	r1, r3, #16
-        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
- 8000dce:	683b      	ldr	r3, [r7, #0]
- 8000dd0:	685b      	ldr	r3, [r3, #4]
- 8000dd2:	b29b      	uxth	r3, r3
-      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
- 8000dd4:	683a      	ldr	r2, [r7, #0]
- 8000dd6:	6952      	ldr	r2, [r2, #20]
-        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
- 8000dd8:	4319      	orrs	r1, r3
-      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
- 8000dda:	697b      	ldr	r3, [r7, #20]
- 8000ddc:	3248      	adds	r2, #72	; 0x48
- 8000dde:	f843 1032 	str.w	r1, [r3, r2, lsl #3]
-
-      /* 32-bit mask or Second 32-bit identifier */
-      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
-        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
- 8000de2:	683b      	ldr	r3, [r7, #0]
- 8000de4:	689b      	ldr	r3, [r3, #8]
- 8000de6:	0419      	lsls	r1, r3, #16
-        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
- 8000de8:	683b      	ldr	r3, [r7, #0]
- 8000dea:	68db      	ldr	r3, [r3, #12]
- 8000dec:	b29a      	uxth	r2, r3
-      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
- 8000dee:	683b      	ldr	r3, [r7, #0]
- 8000df0:	695b      	ldr	r3, [r3, #20]
-        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
- 8000df2:	430a      	orrs	r2, r1
-      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
- 8000df4:	6979      	ldr	r1, [r7, #20]
- 8000df6:	3348      	adds	r3, #72	; 0x48
- 8000df8:	00db      	lsls	r3, r3, #3
- 8000dfa:	440b      	add	r3, r1
- 8000dfc:	605a      	str	r2, [r3, #4]
-    }
-
-    /* Filter Mode */
-    if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
- 8000dfe:	683b      	ldr	r3, [r7, #0]
- 8000e00:	699b      	ldr	r3, [r3, #24]
- 8000e02:	2b00      	cmp	r3, #0
- 8000e04:	d109      	bne.n	8000e1a <HAL_CAN_ConfigFilter+0x13a>
-    {
-      /* Id/Mask mode for the filter*/
-      CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
- 8000e06:	697b      	ldr	r3, [r7, #20]
- 8000e08:	f8d3 2204 	ldr.w	r2, [r3, #516]	; 0x204
- 8000e0c:	68fb      	ldr	r3, [r7, #12]
- 8000e0e:	43db      	mvns	r3, r3
- 8000e10:	401a      	ands	r2, r3
- 8000e12:	697b      	ldr	r3, [r7, #20]
- 8000e14:	f8c3 2204 	str.w	r2, [r3, #516]	; 0x204
- 8000e18:	e007      	b.n	8000e2a <HAL_CAN_ConfigFilter+0x14a>
-    }
-    else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
-    {
-      /* Identifier list mode for the filter*/
-      SET_BIT(can_ip->FM1R, filternbrbitpos);
- 8000e1a:	697b      	ldr	r3, [r7, #20]
- 8000e1c:	f8d3 2204 	ldr.w	r2, [r3, #516]	; 0x204
- 8000e20:	68fb      	ldr	r3, [r7, #12]
- 8000e22:	431a      	orrs	r2, r3
- 8000e24:	697b      	ldr	r3, [r7, #20]
- 8000e26:	f8c3 2204 	str.w	r2, [r3, #516]	; 0x204
-    }
-
-    /* Filter FIFO assignment */
-    if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
- 8000e2a:	683b      	ldr	r3, [r7, #0]
- 8000e2c:	691b      	ldr	r3, [r3, #16]
- 8000e2e:	2b00      	cmp	r3, #0
- 8000e30:	d109      	bne.n	8000e46 <HAL_CAN_ConfigFilter+0x166>
-    {
-      /* FIFO 0 assignation for the filter */
-      CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
- 8000e32:	697b      	ldr	r3, [r7, #20]
- 8000e34:	f8d3 2214 	ldr.w	r2, [r3, #532]	; 0x214
- 8000e38:	68fb      	ldr	r3, [r7, #12]
- 8000e3a:	43db      	mvns	r3, r3
- 8000e3c:	401a      	ands	r2, r3
- 8000e3e:	697b      	ldr	r3, [r7, #20]
- 8000e40:	f8c3 2214 	str.w	r2, [r3, #532]	; 0x214
- 8000e44:	e007      	b.n	8000e56 <HAL_CAN_ConfigFilter+0x176>
-    }
-    else
-    {
-      /* FIFO 1 assignation for the filter */
-      SET_BIT(can_ip->FFA1R, filternbrbitpos);
- 8000e46:	697b      	ldr	r3, [r7, #20]
- 8000e48:	f8d3 2214 	ldr.w	r2, [r3, #532]	; 0x214
- 8000e4c:	68fb      	ldr	r3, [r7, #12]
- 8000e4e:	431a      	orrs	r2, r3
- 8000e50:	697b      	ldr	r3, [r7, #20]
- 8000e52:	f8c3 2214 	str.w	r2, [r3, #532]	; 0x214
-    }
-
-    /* Filter activation */
-    if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
- 8000e56:	683b      	ldr	r3, [r7, #0]
- 8000e58:	6a1b      	ldr	r3, [r3, #32]
- 8000e5a:	2b01      	cmp	r3, #1
- 8000e5c:	d107      	bne.n	8000e6e <HAL_CAN_ConfigFilter+0x18e>
-    {
-      SET_BIT(can_ip->FA1R, filternbrbitpos);
- 8000e5e:	697b      	ldr	r3, [r7, #20]
- 8000e60:	f8d3 221c 	ldr.w	r2, [r3, #540]	; 0x21c
- 8000e64:	68fb      	ldr	r3, [r7, #12]
- 8000e66:	431a      	orrs	r2, r3
- 8000e68:	697b      	ldr	r3, [r7, #20]
- 8000e6a:	f8c3 221c 	str.w	r2, [r3, #540]	; 0x21c
-    }
-
-    /* Leave the initialisation mode for the filter */
-    CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
- 8000e6e:	697b      	ldr	r3, [r7, #20]
- 8000e70:	f8d3 3200 	ldr.w	r3, [r3, #512]	; 0x200
- 8000e74:	f023 0201 	bic.w	r2, r3, #1
- 8000e78:	697b      	ldr	r3, [r7, #20]
- 8000e7a:	f8c3 2200 	str.w	r2, [r3, #512]	; 0x200
-
-    /* Return function status */
-    return HAL_OK;
- 8000e7e:	2300      	movs	r3, #0
- 8000e80:	e006      	b.n	8000e90 <HAL_CAN_ConfigFilter+0x1b0>
-  }
-  else
-  {
-    /* Update error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
- 8000e82:	687b      	ldr	r3, [r7, #4]
- 8000e84:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8000e86:	f443 2280 	orr.w	r2, r3, #262144	; 0x40000
- 8000e8a:	687b      	ldr	r3, [r7, #4]
- 8000e8c:	625a      	str	r2, [r3, #36]	; 0x24
-
-    return HAL_ERROR;
- 8000e8e:	2301      	movs	r3, #1
-  }
-}
- 8000e90:	4618      	mov	r0, r3
- 8000e92:	371c      	adds	r7, #28
- 8000e94:	46bd      	mov	sp, r7
- 8000e96:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8000e9a:	4770      	bx	lr
- 8000e9c:	40006400 	.word	0x40006400
-
-08000ea0 <HAL_CAN_Start>:
-  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
-{
- 8000ea0:	b580      	push	{r7, lr}
- 8000ea2:	b084      	sub	sp, #16
- 8000ea4:	af00      	add	r7, sp, #0
- 8000ea6:	6078      	str	r0, [r7, #4]
-  uint32_t tickstart;
-
-  if (hcan->State == HAL_CAN_STATE_READY)
- 8000ea8:	687b      	ldr	r3, [r7, #4]
- 8000eaa:	f893 3020 	ldrb.w	r3, [r3, #32]
- 8000eae:	b2db      	uxtb	r3, r3
- 8000eb0:	2b01      	cmp	r3, #1
- 8000eb2:	d12e      	bne.n	8000f12 <HAL_CAN_Start+0x72>
-  {
-    /* Change CAN peripheral state */
-    hcan->State = HAL_CAN_STATE_LISTENING;
- 8000eb4:	687b      	ldr	r3, [r7, #4]
- 8000eb6:	2202      	movs	r2, #2
- 8000eb8:	f883 2020 	strb.w	r2, [r3, #32]
-
-    /* Request leave initialisation */
-    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
- 8000ebc:	687b      	ldr	r3, [r7, #4]
- 8000ebe:	681b      	ldr	r3, [r3, #0]
- 8000ec0:	681a      	ldr	r2, [r3, #0]
- 8000ec2:	687b      	ldr	r3, [r7, #4]
- 8000ec4:	681b      	ldr	r3, [r3, #0]
- 8000ec6:	f022 0201 	bic.w	r2, r2, #1
- 8000eca:	601a      	str	r2, [r3, #0]
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
- 8000ecc:	f7ff fe00 	bl	8000ad0 <HAL_GetTick>
- 8000ed0:	60f8      	str	r0, [r7, #12]
-
-    /* Wait the acknowledge */
-    while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
- 8000ed2:	e012      	b.n	8000efa <HAL_CAN_Start+0x5a>
-    {
-      /* Check for the Timeout */
-      if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
- 8000ed4:	f7ff fdfc 	bl	8000ad0 <HAL_GetTick>
- 8000ed8:	4602      	mov	r2, r0
- 8000eda:	68fb      	ldr	r3, [r7, #12]
- 8000edc:	1ad3      	subs	r3, r2, r3
- 8000ede:	2b0a      	cmp	r3, #10
- 8000ee0:	d90b      	bls.n	8000efa <HAL_CAN_Start+0x5a>
-      {
-        /* Update error code */
-        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
- 8000ee2:	687b      	ldr	r3, [r7, #4]
- 8000ee4:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8000ee6:	f443 3200 	orr.w	r2, r3, #131072	; 0x20000
- 8000eea:	687b      	ldr	r3, [r7, #4]
- 8000eec:	625a      	str	r2, [r3, #36]	; 0x24
-
-        /* Change CAN state */
-        hcan->State = HAL_CAN_STATE_ERROR;
- 8000eee:	687b      	ldr	r3, [r7, #4]
- 8000ef0:	2205      	movs	r2, #5
- 8000ef2:	f883 2020 	strb.w	r2, [r3, #32]
-
-        return HAL_ERROR;
- 8000ef6:	2301      	movs	r3, #1
- 8000ef8:	e012      	b.n	8000f20 <HAL_CAN_Start+0x80>
-    while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
- 8000efa:	687b      	ldr	r3, [r7, #4]
- 8000efc:	681b      	ldr	r3, [r3, #0]
- 8000efe:	685b      	ldr	r3, [r3, #4]
- 8000f00:	f003 0301 	and.w	r3, r3, #1
- 8000f04:	2b00      	cmp	r3, #0
- 8000f06:	d1e5      	bne.n	8000ed4 <HAL_CAN_Start+0x34>
-      }
-    }
-
-    /* Reset the CAN ErrorCode */
-    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
- 8000f08:	687b      	ldr	r3, [r7, #4]
- 8000f0a:	2200      	movs	r2, #0
- 8000f0c:	625a      	str	r2, [r3, #36]	; 0x24
-
-    /* Return function status */
-    return HAL_OK;
- 8000f0e:	2300      	movs	r3, #0
- 8000f10:	e006      	b.n	8000f20 <HAL_CAN_Start+0x80>
-  }
-  else
-  {
-    /* Update error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
- 8000f12:	687b      	ldr	r3, [r7, #4]
- 8000f14:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8000f16:	f443 2200 	orr.w	r2, r3, #524288	; 0x80000
- 8000f1a:	687b      	ldr	r3, [r7, #4]
- 8000f1c:	625a      	str	r2, [r3, #36]	; 0x24
-
-    return HAL_ERROR;
- 8000f1e:	2301      	movs	r3, #1
-  }
-}
- 8000f20:	4618      	mov	r0, r3
- 8000f22:	3710      	adds	r7, #16
- 8000f24:	46bd      	mov	sp, r7
- 8000f26:	bd80      	pop	{r7, pc}
-
-08000f28 <HAL_CAN_AddTxMessage>:
-  *         the TxMailbox used to store the Tx message.
-  *         This parameter can be a value of @arg CAN_Tx_Mailboxes.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)
-{
- 8000f28:	b480      	push	{r7}
- 8000f2a:	b089      	sub	sp, #36	; 0x24
- 8000f2c:	af00      	add	r7, sp, #0
- 8000f2e:	60f8      	str	r0, [r7, #12]
- 8000f30:	60b9      	str	r1, [r7, #8]
- 8000f32:	607a      	str	r2, [r7, #4]
- 8000f34:	603b      	str	r3, [r7, #0]
-  uint32_t transmitmailbox;
-  HAL_CAN_StateTypeDef state = hcan->State;
- 8000f36:	68fb      	ldr	r3, [r7, #12]
- 8000f38:	f893 3020 	ldrb.w	r3, [r3, #32]
- 8000f3c:	77fb      	strb	r3, [r7, #31]
-  uint32_t tsr = READ_REG(hcan->Instance->TSR);
- 8000f3e:	68fb      	ldr	r3, [r7, #12]
- 8000f40:	681b      	ldr	r3, [r3, #0]
- 8000f42:	689b      	ldr	r3, [r3, #8]
- 8000f44:	61bb      	str	r3, [r7, #24]
-  {
-    assert_param(IS_CAN_EXTID(pHeader->ExtId));
-  }
-  assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
-
-  if ((state == HAL_CAN_STATE_READY) ||
- 8000f46:	7ffb      	ldrb	r3, [r7, #31]
- 8000f48:	2b01      	cmp	r3, #1
- 8000f4a:	d003      	beq.n	8000f54 <HAL_CAN_AddTxMessage+0x2c>
- 8000f4c:	7ffb      	ldrb	r3, [r7, #31]
- 8000f4e:	2b02      	cmp	r3, #2
- 8000f50:	f040 80b8 	bne.w	80010c4 <HAL_CAN_AddTxMessage+0x19c>
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    /* Check that all the Tx mailboxes are not full */
-    if (((tsr & CAN_TSR_TME0) != 0U) ||
- 8000f54:	69bb      	ldr	r3, [r7, #24]
- 8000f56:	f003 6380 	and.w	r3, r3, #67108864	; 0x4000000
- 8000f5a:	2b00      	cmp	r3, #0
- 8000f5c:	d10a      	bne.n	8000f74 <HAL_CAN_AddTxMessage+0x4c>
-        ((tsr & CAN_TSR_TME1) != 0U) ||
- 8000f5e:	69bb      	ldr	r3, [r7, #24]
- 8000f60:	f003 6300 	and.w	r3, r3, #134217728	; 0x8000000
-    if (((tsr & CAN_TSR_TME0) != 0U) ||
- 8000f64:	2b00      	cmp	r3, #0
- 8000f66:	d105      	bne.n	8000f74 <HAL_CAN_AddTxMessage+0x4c>
-        ((tsr & CAN_TSR_TME2) != 0U))
- 8000f68:	69bb      	ldr	r3, [r7, #24]
- 8000f6a:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
-        ((tsr & CAN_TSR_TME1) != 0U) ||
- 8000f6e:	2b00      	cmp	r3, #0
- 8000f70:	f000 80a0 	beq.w	80010b4 <HAL_CAN_AddTxMessage+0x18c>
-    {
-      /* Select an empty transmit mailbox */
-      transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
- 8000f74:	69bb      	ldr	r3, [r7, #24]
- 8000f76:	0e1b      	lsrs	r3, r3, #24
- 8000f78:	f003 0303 	and.w	r3, r3, #3
- 8000f7c:	617b      	str	r3, [r7, #20]
-
-      /* Check transmit mailbox value */
-      if (transmitmailbox > 2U)
- 8000f7e:	697b      	ldr	r3, [r7, #20]
- 8000f80:	2b02      	cmp	r3, #2
- 8000f82:	d907      	bls.n	8000f94 <HAL_CAN_AddTxMessage+0x6c>
-      {
-        /* Update error code */
-        hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL;
- 8000f84:	68fb      	ldr	r3, [r7, #12]
- 8000f86:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8000f88:	f443 0200 	orr.w	r2, r3, #8388608	; 0x800000
- 8000f8c:	68fb      	ldr	r3, [r7, #12]
- 8000f8e:	625a      	str	r2, [r3, #36]	; 0x24
-
-        return HAL_ERROR;
- 8000f90:	2301      	movs	r3, #1
- 8000f92:	e09e      	b.n	80010d2 <HAL_CAN_AddTxMessage+0x1aa>
-      }
-
-      /* Store the Tx mailbox */
-      *pTxMailbox = (uint32_t)1 << transmitmailbox;
- 8000f94:	2201      	movs	r2, #1
- 8000f96:	697b      	ldr	r3, [r7, #20]
- 8000f98:	409a      	lsls	r2, r3
- 8000f9a:	683b      	ldr	r3, [r7, #0]
- 8000f9c:	601a      	str	r2, [r3, #0]
-
-      /* Set up the Id */
-      if (pHeader->IDE == CAN_ID_STD)
- 8000f9e:	68bb      	ldr	r3, [r7, #8]
- 8000fa0:	689b      	ldr	r3, [r3, #8]
- 8000fa2:	2b00      	cmp	r3, #0
- 8000fa4:	d10d      	bne.n	8000fc2 <HAL_CAN_AddTxMessage+0x9a>
-      {
-        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
- 8000fa6:	68bb      	ldr	r3, [r7, #8]
- 8000fa8:	681b      	ldr	r3, [r3, #0]
- 8000faa:	055a      	lsls	r2, r3, #21
-                                                           pHeader->RTR);
- 8000fac:	68bb      	ldr	r3, [r7, #8]
- 8000fae:	68db      	ldr	r3, [r3, #12]
-        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
- 8000fb0:	68f9      	ldr	r1, [r7, #12]
- 8000fb2:	6809      	ldr	r1, [r1, #0]
- 8000fb4:	431a      	orrs	r2, r3
- 8000fb6:	697b      	ldr	r3, [r7, #20]
- 8000fb8:	3318      	adds	r3, #24
- 8000fba:	011b      	lsls	r3, r3, #4
- 8000fbc:	440b      	add	r3, r1
- 8000fbe:	601a      	str	r2, [r3, #0]
- 8000fc0:	e00f      	b.n	8000fe2 <HAL_CAN_AddTxMessage+0xba>
-      }
-      else
-      {
-        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
- 8000fc2:	68bb      	ldr	r3, [r7, #8]
- 8000fc4:	685b      	ldr	r3, [r3, #4]
- 8000fc6:	00da      	lsls	r2, r3, #3
-                                                           pHeader->IDE |
- 8000fc8:	68bb      	ldr	r3, [r7, #8]
- 8000fca:	689b      	ldr	r3, [r3, #8]
-        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
- 8000fcc:	431a      	orrs	r2, r3
-                                                           pHeader->RTR);
- 8000fce:	68bb      	ldr	r3, [r7, #8]
- 8000fd0:	68db      	ldr	r3, [r3, #12]
-        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
- 8000fd2:	68f9      	ldr	r1, [r7, #12]
- 8000fd4:	6809      	ldr	r1, [r1, #0]
-                                                           pHeader->IDE |
- 8000fd6:	431a      	orrs	r2, r3
-        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
- 8000fd8:	697b      	ldr	r3, [r7, #20]
- 8000fda:	3318      	adds	r3, #24
- 8000fdc:	011b      	lsls	r3, r3, #4
- 8000fde:	440b      	add	r3, r1
- 8000fe0:	601a      	str	r2, [r3, #0]
-      }
-
-      /* Set up the DLC */
-      hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
- 8000fe2:	68fb      	ldr	r3, [r7, #12]
- 8000fe4:	6819      	ldr	r1, [r3, #0]
- 8000fe6:	68bb      	ldr	r3, [r7, #8]
- 8000fe8:	691a      	ldr	r2, [r3, #16]
- 8000fea:	697b      	ldr	r3, [r7, #20]
- 8000fec:	3318      	adds	r3, #24
- 8000fee:	011b      	lsls	r3, r3, #4
- 8000ff0:	440b      	add	r3, r1
- 8000ff2:	3304      	adds	r3, #4
- 8000ff4:	601a      	str	r2, [r3, #0]
-
-      /* Set up the Transmit Global Time mode */
-      if (pHeader->TransmitGlobalTime == ENABLE)
- 8000ff6:	68bb      	ldr	r3, [r7, #8]
- 8000ff8:	7d1b      	ldrb	r3, [r3, #20]
- 8000ffa:	2b01      	cmp	r3, #1
- 8000ffc:	d111      	bne.n	8001022 <HAL_CAN_AddTxMessage+0xfa>
-      {
-        SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
- 8000ffe:	68fb      	ldr	r3, [r7, #12]
- 8001000:	681a      	ldr	r2, [r3, #0]
- 8001002:	697b      	ldr	r3, [r7, #20]
- 8001004:	3318      	adds	r3, #24
- 8001006:	011b      	lsls	r3, r3, #4
- 8001008:	4413      	add	r3, r2
- 800100a:	3304      	adds	r3, #4
- 800100c:	681b      	ldr	r3, [r3, #0]
- 800100e:	68fa      	ldr	r2, [r7, #12]
- 8001010:	6811      	ldr	r1, [r2, #0]
- 8001012:	f443 7280 	orr.w	r2, r3, #256	; 0x100
- 8001016:	697b      	ldr	r3, [r7, #20]
- 8001018:	3318      	adds	r3, #24
- 800101a:	011b      	lsls	r3, r3, #4
- 800101c:	440b      	add	r3, r1
- 800101e:	3304      	adds	r3, #4
- 8001020:	601a      	str	r2, [r3, #0]
-      }
-
-      /* Set up the data field */
-      WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
- 8001022:	687b      	ldr	r3, [r7, #4]
- 8001024:	3307      	adds	r3, #7
- 8001026:	781b      	ldrb	r3, [r3, #0]
- 8001028:	061a      	lsls	r2, r3, #24
- 800102a:	687b      	ldr	r3, [r7, #4]
- 800102c:	3306      	adds	r3, #6
- 800102e:	781b      	ldrb	r3, [r3, #0]
- 8001030:	041b      	lsls	r3, r3, #16
- 8001032:	431a      	orrs	r2, r3
- 8001034:	687b      	ldr	r3, [r7, #4]
- 8001036:	3305      	adds	r3, #5
- 8001038:	781b      	ldrb	r3, [r3, #0]
- 800103a:	021b      	lsls	r3, r3, #8
- 800103c:	4313      	orrs	r3, r2
- 800103e:	687a      	ldr	r2, [r7, #4]
- 8001040:	3204      	adds	r2, #4
- 8001042:	7812      	ldrb	r2, [r2, #0]
- 8001044:	4610      	mov	r0, r2
- 8001046:	68fa      	ldr	r2, [r7, #12]
- 8001048:	6811      	ldr	r1, [r2, #0]
- 800104a:	ea43 0200 	orr.w	r2, r3, r0
- 800104e:	697b      	ldr	r3, [r7, #20]
- 8001050:	011b      	lsls	r3, r3, #4
- 8001052:	440b      	add	r3, r1
- 8001054:	f503 73c6 	add.w	r3, r3, #396	; 0x18c
- 8001058:	601a      	str	r2, [r3, #0]
-                ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
-                ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
-                ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
-                ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
-      WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
- 800105a:	687b      	ldr	r3, [r7, #4]
- 800105c:	3303      	adds	r3, #3
- 800105e:	781b      	ldrb	r3, [r3, #0]
- 8001060:	061a      	lsls	r2, r3, #24
- 8001062:	687b      	ldr	r3, [r7, #4]
- 8001064:	3302      	adds	r3, #2
- 8001066:	781b      	ldrb	r3, [r3, #0]
- 8001068:	041b      	lsls	r3, r3, #16
- 800106a:	431a      	orrs	r2, r3
- 800106c:	687b      	ldr	r3, [r7, #4]
- 800106e:	3301      	adds	r3, #1
- 8001070:	781b      	ldrb	r3, [r3, #0]
- 8001072:	021b      	lsls	r3, r3, #8
- 8001074:	4313      	orrs	r3, r2
- 8001076:	687a      	ldr	r2, [r7, #4]
- 8001078:	7812      	ldrb	r2, [r2, #0]
- 800107a:	4610      	mov	r0, r2
- 800107c:	68fa      	ldr	r2, [r7, #12]
- 800107e:	6811      	ldr	r1, [r2, #0]
- 8001080:	ea43 0200 	orr.w	r2, r3, r0
- 8001084:	697b      	ldr	r3, [r7, #20]
- 8001086:	011b      	lsls	r3, r3, #4
- 8001088:	440b      	add	r3, r1
- 800108a:	f503 73c4 	add.w	r3, r3, #392	; 0x188
- 800108e:	601a      	str	r2, [r3, #0]
-                ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
-                ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
-                ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
-
-      /* Request transmission */
-      SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
- 8001090:	68fb      	ldr	r3, [r7, #12]
- 8001092:	681a      	ldr	r2, [r3, #0]
- 8001094:	697b      	ldr	r3, [r7, #20]
- 8001096:	3318      	adds	r3, #24
- 8001098:	011b      	lsls	r3, r3, #4
- 800109a:	4413      	add	r3, r2
- 800109c:	681b      	ldr	r3, [r3, #0]
- 800109e:	68fa      	ldr	r2, [r7, #12]
- 80010a0:	6811      	ldr	r1, [r2, #0]
- 80010a2:	f043 0201 	orr.w	r2, r3, #1
- 80010a6:	697b      	ldr	r3, [r7, #20]
- 80010a8:	3318      	adds	r3, #24
- 80010aa:	011b      	lsls	r3, r3, #4
- 80010ac:	440b      	add	r3, r1
- 80010ae:	601a      	str	r2, [r3, #0]
-
-      /* Return function status */
-      return HAL_OK;
- 80010b0:	2300      	movs	r3, #0
- 80010b2:	e00e      	b.n	80010d2 <HAL_CAN_AddTxMessage+0x1aa>
-    }
-    else
-    {
-      /* Update error code */
-      hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
- 80010b4:	68fb      	ldr	r3, [r7, #12]
- 80010b6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 80010b8:	f443 1200 	orr.w	r2, r3, #2097152	; 0x200000
- 80010bc:	68fb      	ldr	r3, [r7, #12]
- 80010be:	625a      	str	r2, [r3, #36]	; 0x24
-
-      return HAL_ERROR;
- 80010c0:	2301      	movs	r3, #1
- 80010c2:	e006      	b.n	80010d2 <HAL_CAN_AddTxMessage+0x1aa>
-    }
-  }
-  else
-  {
-    /* Update error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
- 80010c4:	68fb      	ldr	r3, [r7, #12]
- 80010c6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 80010c8:	f443 2280 	orr.w	r2, r3, #262144	; 0x40000
- 80010cc:	68fb      	ldr	r3, [r7, #12]
- 80010ce:	625a      	str	r2, [r3, #36]	; 0x24
-
-    return HAL_ERROR;
- 80010d0:	2301      	movs	r3, #1
-  }
-}
- 80010d2:	4618      	mov	r0, r3
- 80010d4:	3724      	adds	r7, #36	; 0x24
- 80010d6:	46bd      	mov	sp, r7
- 80010d8:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80010dc:	4770      	bx	lr
-
-080010de <HAL_CAN_GetRxMessage>:
-  *         of the Rx frame will be stored.
-  * @param  aData array where the payload of the Rx frame will be stored.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
-{
- 80010de:	b480      	push	{r7}
- 80010e0:	b087      	sub	sp, #28
- 80010e2:	af00      	add	r7, sp, #0
- 80010e4:	60f8      	str	r0, [r7, #12]
- 80010e6:	60b9      	str	r1, [r7, #8]
- 80010e8:	607a      	str	r2, [r7, #4]
- 80010ea:	603b      	str	r3, [r7, #0]
-  HAL_CAN_StateTypeDef state = hcan->State;
- 80010ec:	68fb      	ldr	r3, [r7, #12]
- 80010ee:	f893 3020 	ldrb.w	r3, [r3, #32]
- 80010f2:	75fb      	strb	r3, [r7, #23]
-
-  assert_param(IS_CAN_RX_FIFO(RxFifo));
-
-  if ((state == HAL_CAN_STATE_READY) ||
- 80010f4:	7dfb      	ldrb	r3, [r7, #23]
- 80010f6:	2b01      	cmp	r3, #1
- 80010f8:	d003      	beq.n	8001102 <HAL_CAN_GetRxMessage+0x24>
- 80010fa:	7dfb      	ldrb	r3, [r7, #23]
- 80010fc:	2b02      	cmp	r3, #2
- 80010fe:	f040 80f3 	bne.w	80012e8 <HAL_CAN_GetRxMessage+0x20a>
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    /* Check the Rx FIFO */
-    if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
- 8001102:	68bb      	ldr	r3, [r7, #8]
- 8001104:	2b00      	cmp	r3, #0
- 8001106:	d10e      	bne.n	8001126 <HAL_CAN_GetRxMessage+0x48>
-    {
-      /* Check that the Rx FIFO 0 is not empty */
-      if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
- 8001108:	68fb      	ldr	r3, [r7, #12]
- 800110a:	681b      	ldr	r3, [r3, #0]
- 800110c:	68db      	ldr	r3, [r3, #12]
- 800110e:	f003 0303 	and.w	r3, r3, #3
- 8001112:	2b00      	cmp	r3, #0
- 8001114:	d116      	bne.n	8001144 <HAL_CAN_GetRxMessage+0x66>
-      {
-        /* Update error code */
-        hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
- 8001116:	68fb      	ldr	r3, [r7, #12]
- 8001118:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 800111a:	f443 1200 	orr.w	r2, r3, #2097152	; 0x200000
- 800111e:	68fb      	ldr	r3, [r7, #12]
- 8001120:	625a      	str	r2, [r3, #36]	; 0x24
-
-        return HAL_ERROR;
- 8001122:	2301      	movs	r3, #1
- 8001124:	e0e7      	b.n	80012f6 <HAL_CAN_GetRxMessage+0x218>
-      }
-    }
-    else /* Rx element is assigned to Rx FIFO 1 */
-    {
-      /* Check that the Rx FIFO 1 is not empty */
-      if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
- 8001126:	68fb      	ldr	r3, [r7, #12]
- 8001128:	681b      	ldr	r3, [r3, #0]
- 800112a:	691b      	ldr	r3, [r3, #16]
- 800112c:	f003 0303 	and.w	r3, r3, #3
- 8001130:	2b00      	cmp	r3, #0
- 8001132:	d107      	bne.n	8001144 <HAL_CAN_GetRxMessage+0x66>
-      {
-        /* Update error code */
-        hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
- 8001134:	68fb      	ldr	r3, [r7, #12]
- 8001136:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8001138:	f443 1200 	orr.w	r2, r3, #2097152	; 0x200000
- 800113c:	68fb      	ldr	r3, [r7, #12]
- 800113e:	625a      	str	r2, [r3, #36]	; 0x24
-
-        return HAL_ERROR;
- 8001140:	2301      	movs	r3, #1
- 8001142:	e0d8      	b.n	80012f6 <HAL_CAN_GetRxMessage+0x218>
-      }
-    }
-
-    /* Get the header */
-    pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
- 8001144:	68fb      	ldr	r3, [r7, #12]
- 8001146:	681a      	ldr	r2, [r3, #0]
- 8001148:	68bb      	ldr	r3, [r7, #8]
- 800114a:	331b      	adds	r3, #27
- 800114c:	011b      	lsls	r3, r3, #4
- 800114e:	4413      	add	r3, r2
- 8001150:	681b      	ldr	r3, [r3, #0]
- 8001152:	f003 0204 	and.w	r2, r3, #4
- 8001156:	687b      	ldr	r3, [r7, #4]
- 8001158:	609a      	str	r2, [r3, #8]
-    if (pHeader->IDE == CAN_ID_STD)
- 800115a:	687b      	ldr	r3, [r7, #4]
- 800115c:	689b      	ldr	r3, [r3, #8]
- 800115e:	2b00      	cmp	r3, #0
- 8001160:	d10c      	bne.n	800117c <HAL_CAN_GetRxMessage+0x9e>
-    {
-      pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
- 8001162:	68fb      	ldr	r3, [r7, #12]
- 8001164:	681a      	ldr	r2, [r3, #0]
- 8001166:	68bb      	ldr	r3, [r7, #8]
- 8001168:	331b      	adds	r3, #27
- 800116a:	011b      	lsls	r3, r3, #4
- 800116c:	4413      	add	r3, r2
- 800116e:	681b      	ldr	r3, [r3, #0]
- 8001170:	0d5b      	lsrs	r3, r3, #21
- 8001172:	f3c3 020a 	ubfx	r2, r3, #0, #11
- 8001176:	687b      	ldr	r3, [r7, #4]
- 8001178:	601a      	str	r2, [r3, #0]
- 800117a:	e00b      	b.n	8001194 <HAL_CAN_GetRxMessage+0xb6>
-    }
-    else
-    {
-      pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
- 800117c:	68fb      	ldr	r3, [r7, #12]
- 800117e:	681a      	ldr	r2, [r3, #0]
- 8001180:	68bb      	ldr	r3, [r7, #8]
- 8001182:	331b      	adds	r3, #27
- 8001184:	011b      	lsls	r3, r3, #4
- 8001186:	4413      	add	r3, r2
- 8001188:	681b      	ldr	r3, [r3, #0]
- 800118a:	08db      	lsrs	r3, r3, #3
- 800118c:	f023 4260 	bic.w	r2, r3, #3758096384	; 0xe0000000
- 8001190:	687b      	ldr	r3, [r7, #4]
- 8001192:	605a      	str	r2, [r3, #4]
-    }
-    pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
- 8001194:	68fb      	ldr	r3, [r7, #12]
- 8001196:	681a      	ldr	r2, [r3, #0]
- 8001198:	68bb      	ldr	r3, [r7, #8]
- 800119a:	331b      	adds	r3, #27
- 800119c:	011b      	lsls	r3, r3, #4
- 800119e:	4413      	add	r3, r2
- 80011a0:	681b      	ldr	r3, [r3, #0]
- 80011a2:	f003 0202 	and.w	r2, r3, #2
- 80011a6:	687b      	ldr	r3, [r7, #4]
- 80011a8:	60da      	str	r2, [r3, #12]
-    pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
- 80011aa:	68fb      	ldr	r3, [r7, #12]
- 80011ac:	681a      	ldr	r2, [r3, #0]
- 80011ae:	68bb      	ldr	r3, [r7, #8]
- 80011b0:	331b      	adds	r3, #27
- 80011b2:	011b      	lsls	r3, r3, #4
- 80011b4:	4413      	add	r3, r2
- 80011b6:	3304      	adds	r3, #4
- 80011b8:	681b      	ldr	r3, [r3, #0]
- 80011ba:	f003 020f 	and.w	r2, r3, #15
- 80011be:	687b      	ldr	r3, [r7, #4]
- 80011c0:	611a      	str	r2, [r3, #16]
-    pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
- 80011c2:	68fb      	ldr	r3, [r7, #12]
- 80011c4:	681a      	ldr	r2, [r3, #0]
- 80011c6:	68bb      	ldr	r3, [r7, #8]
- 80011c8:	331b      	adds	r3, #27
- 80011ca:	011b      	lsls	r3, r3, #4
- 80011cc:	4413      	add	r3, r2
- 80011ce:	3304      	adds	r3, #4
- 80011d0:	681b      	ldr	r3, [r3, #0]
- 80011d2:	0a1b      	lsrs	r3, r3, #8
- 80011d4:	b2da      	uxtb	r2, r3
- 80011d6:	687b      	ldr	r3, [r7, #4]
- 80011d8:	619a      	str	r2, [r3, #24]
-    pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
- 80011da:	68fb      	ldr	r3, [r7, #12]
- 80011dc:	681a      	ldr	r2, [r3, #0]
- 80011de:	68bb      	ldr	r3, [r7, #8]
- 80011e0:	331b      	adds	r3, #27
- 80011e2:	011b      	lsls	r3, r3, #4
- 80011e4:	4413      	add	r3, r2
- 80011e6:	3304      	adds	r3, #4
- 80011e8:	681b      	ldr	r3, [r3, #0]
- 80011ea:	0c1b      	lsrs	r3, r3, #16
- 80011ec:	b29a      	uxth	r2, r3
- 80011ee:	687b      	ldr	r3, [r7, #4]
- 80011f0:	615a      	str	r2, [r3, #20]
-
-    /* Get the data */
-    aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
- 80011f2:	68fb      	ldr	r3, [r7, #12]
- 80011f4:	681a      	ldr	r2, [r3, #0]
- 80011f6:	68bb      	ldr	r3, [r7, #8]
- 80011f8:	011b      	lsls	r3, r3, #4
- 80011fa:	4413      	add	r3, r2
- 80011fc:	f503 73dc 	add.w	r3, r3, #440	; 0x1b8
- 8001200:	681b      	ldr	r3, [r3, #0]
- 8001202:	b2da      	uxtb	r2, r3
- 8001204:	683b      	ldr	r3, [r7, #0]
- 8001206:	701a      	strb	r2, [r3, #0]
-    aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
- 8001208:	68fb      	ldr	r3, [r7, #12]
- 800120a:	681a      	ldr	r2, [r3, #0]
- 800120c:	68bb      	ldr	r3, [r7, #8]
- 800120e:	011b      	lsls	r3, r3, #4
- 8001210:	4413      	add	r3, r2
- 8001212:	f503 73dc 	add.w	r3, r3, #440	; 0x1b8
- 8001216:	681b      	ldr	r3, [r3, #0]
- 8001218:	0a1a      	lsrs	r2, r3, #8
- 800121a:	683b      	ldr	r3, [r7, #0]
- 800121c:	3301      	adds	r3, #1
- 800121e:	b2d2      	uxtb	r2, r2
- 8001220:	701a      	strb	r2, [r3, #0]
-    aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
- 8001222:	68fb      	ldr	r3, [r7, #12]
- 8001224:	681a      	ldr	r2, [r3, #0]
- 8001226:	68bb      	ldr	r3, [r7, #8]
- 8001228:	011b      	lsls	r3, r3, #4
- 800122a:	4413      	add	r3, r2
- 800122c:	f503 73dc 	add.w	r3, r3, #440	; 0x1b8
- 8001230:	681b      	ldr	r3, [r3, #0]
- 8001232:	0c1a      	lsrs	r2, r3, #16
- 8001234:	683b      	ldr	r3, [r7, #0]
- 8001236:	3302      	adds	r3, #2
- 8001238:	b2d2      	uxtb	r2, r2
- 800123a:	701a      	strb	r2, [r3, #0]
-    aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
- 800123c:	68fb      	ldr	r3, [r7, #12]
- 800123e:	681a      	ldr	r2, [r3, #0]
- 8001240:	68bb      	ldr	r3, [r7, #8]
- 8001242:	011b      	lsls	r3, r3, #4
- 8001244:	4413      	add	r3, r2
- 8001246:	f503 73dc 	add.w	r3, r3, #440	; 0x1b8
- 800124a:	681b      	ldr	r3, [r3, #0]
- 800124c:	0e1a      	lsrs	r2, r3, #24
- 800124e:	683b      	ldr	r3, [r7, #0]
- 8001250:	3303      	adds	r3, #3
- 8001252:	b2d2      	uxtb	r2, r2
- 8001254:	701a      	strb	r2, [r3, #0]
-    aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
- 8001256:	68fb      	ldr	r3, [r7, #12]
- 8001258:	681a      	ldr	r2, [r3, #0]
- 800125a:	68bb      	ldr	r3, [r7, #8]
- 800125c:	011b      	lsls	r3, r3, #4
- 800125e:	4413      	add	r3, r2
- 8001260:	f503 73de 	add.w	r3, r3, #444	; 0x1bc
- 8001264:	681a      	ldr	r2, [r3, #0]
- 8001266:	683b      	ldr	r3, [r7, #0]
- 8001268:	3304      	adds	r3, #4
- 800126a:	b2d2      	uxtb	r2, r2
- 800126c:	701a      	strb	r2, [r3, #0]
-    aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
- 800126e:	68fb      	ldr	r3, [r7, #12]
- 8001270:	681a      	ldr	r2, [r3, #0]
- 8001272:	68bb      	ldr	r3, [r7, #8]
- 8001274:	011b      	lsls	r3, r3, #4
- 8001276:	4413      	add	r3, r2
- 8001278:	f503 73de 	add.w	r3, r3, #444	; 0x1bc
- 800127c:	681b      	ldr	r3, [r3, #0]
- 800127e:	0a1a      	lsrs	r2, r3, #8
- 8001280:	683b      	ldr	r3, [r7, #0]
- 8001282:	3305      	adds	r3, #5
- 8001284:	b2d2      	uxtb	r2, r2
- 8001286:	701a      	strb	r2, [r3, #0]
-    aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
- 8001288:	68fb      	ldr	r3, [r7, #12]
- 800128a:	681a      	ldr	r2, [r3, #0]
- 800128c:	68bb      	ldr	r3, [r7, #8]
- 800128e:	011b      	lsls	r3, r3, #4
- 8001290:	4413      	add	r3, r2
- 8001292:	f503 73de 	add.w	r3, r3, #444	; 0x1bc
- 8001296:	681b      	ldr	r3, [r3, #0]
- 8001298:	0c1a      	lsrs	r2, r3, #16
- 800129a:	683b      	ldr	r3, [r7, #0]
- 800129c:	3306      	adds	r3, #6
- 800129e:	b2d2      	uxtb	r2, r2
- 80012a0:	701a      	strb	r2, [r3, #0]
-    aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
- 80012a2:	68fb      	ldr	r3, [r7, #12]
- 80012a4:	681a      	ldr	r2, [r3, #0]
- 80012a6:	68bb      	ldr	r3, [r7, #8]
- 80012a8:	011b      	lsls	r3, r3, #4
- 80012aa:	4413      	add	r3, r2
- 80012ac:	f503 73de 	add.w	r3, r3, #444	; 0x1bc
- 80012b0:	681b      	ldr	r3, [r3, #0]
- 80012b2:	0e1a      	lsrs	r2, r3, #24
- 80012b4:	683b      	ldr	r3, [r7, #0]
- 80012b6:	3307      	adds	r3, #7
- 80012b8:	b2d2      	uxtb	r2, r2
- 80012ba:	701a      	strb	r2, [r3, #0]
-
-    /* Release the FIFO */
-    if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
- 80012bc:	68bb      	ldr	r3, [r7, #8]
- 80012be:	2b00      	cmp	r3, #0
- 80012c0:	d108      	bne.n	80012d4 <HAL_CAN_GetRxMessage+0x1f6>
-    {
-      /* Release RX FIFO 0 */
-      SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
- 80012c2:	68fb      	ldr	r3, [r7, #12]
- 80012c4:	681b      	ldr	r3, [r3, #0]
- 80012c6:	68da      	ldr	r2, [r3, #12]
- 80012c8:	68fb      	ldr	r3, [r7, #12]
- 80012ca:	681b      	ldr	r3, [r3, #0]
- 80012cc:	f042 0220 	orr.w	r2, r2, #32
- 80012d0:	60da      	str	r2, [r3, #12]
- 80012d2:	e007      	b.n	80012e4 <HAL_CAN_GetRxMessage+0x206>
-    }
-    else /* Rx element is assigned to Rx FIFO 1 */
-    {
-      /* Release RX FIFO 1 */
-      SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
- 80012d4:	68fb      	ldr	r3, [r7, #12]
- 80012d6:	681b      	ldr	r3, [r3, #0]
- 80012d8:	691a      	ldr	r2, [r3, #16]
- 80012da:	68fb      	ldr	r3, [r7, #12]
- 80012dc:	681b      	ldr	r3, [r3, #0]
- 80012de:	f042 0220 	orr.w	r2, r2, #32
- 80012e2:	611a      	str	r2, [r3, #16]
-    }
-
-    /* Return function status */
-    return HAL_OK;
- 80012e4:	2300      	movs	r3, #0
- 80012e6:	e006      	b.n	80012f6 <HAL_CAN_GetRxMessage+0x218>
-  }
-  else
-  {
-    /* Update error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
- 80012e8:	68fb      	ldr	r3, [r7, #12]
- 80012ea:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 80012ec:	f443 2280 	orr.w	r2, r3, #262144	; 0x40000
- 80012f0:	68fb      	ldr	r3, [r7, #12]
- 80012f2:	625a      	str	r2, [r3, #36]	; 0x24
-
-    return HAL_ERROR;
- 80012f4:	2301      	movs	r3, #1
-  }
-}
- 80012f6:	4618      	mov	r0, r3
- 80012f8:	371c      	adds	r7, #28
- 80012fa:	46bd      	mov	sp, r7
- 80012fc:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001300:	4770      	bx	lr
-
-08001302 <HAL_CAN_GetRxFifoFillLevel>:
-  * @param  RxFifo Rx FIFO.
-  *         This parameter can be a value of @arg CAN_receive_FIFO_number.
-  * @retval Number of messages available in Rx FIFO.
-  */
-uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
-{
- 8001302:	b480      	push	{r7}
- 8001304:	b085      	sub	sp, #20
- 8001306:	af00      	add	r7, sp, #0
- 8001308:	6078      	str	r0, [r7, #4]
- 800130a:	6039      	str	r1, [r7, #0]
-  uint32_t filllevel = 0U;
- 800130c:	2300      	movs	r3, #0
- 800130e:	60fb      	str	r3, [r7, #12]
-  HAL_CAN_StateTypeDef state = hcan->State;
- 8001310:	687b      	ldr	r3, [r7, #4]
- 8001312:	f893 3020 	ldrb.w	r3, [r3, #32]
- 8001316:	72fb      	strb	r3, [r7, #11]
-
-  /* Check function parameters */
-  assert_param(IS_CAN_RX_FIFO(RxFifo));
-
-  if ((state == HAL_CAN_STATE_READY) ||
- 8001318:	7afb      	ldrb	r3, [r7, #11]
- 800131a:	2b01      	cmp	r3, #1
- 800131c:	d002      	beq.n	8001324 <HAL_CAN_GetRxFifoFillLevel+0x22>
- 800131e:	7afb      	ldrb	r3, [r7, #11]
- 8001320:	2b02      	cmp	r3, #2
- 8001322:	d10f      	bne.n	8001344 <HAL_CAN_GetRxFifoFillLevel+0x42>
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    if (RxFifo == CAN_RX_FIFO0)
- 8001324:	683b      	ldr	r3, [r7, #0]
- 8001326:	2b00      	cmp	r3, #0
- 8001328:	d106      	bne.n	8001338 <HAL_CAN_GetRxFifoFillLevel+0x36>
-    {
-      filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0;
- 800132a:	687b      	ldr	r3, [r7, #4]
- 800132c:	681b      	ldr	r3, [r3, #0]
- 800132e:	68db      	ldr	r3, [r3, #12]
- 8001330:	f003 0303 	and.w	r3, r3, #3
- 8001334:	60fb      	str	r3, [r7, #12]
- 8001336:	e005      	b.n	8001344 <HAL_CAN_GetRxFifoFillLevel+0x42>
-    }
-    else /* RxFifo == CAN_RX_FIFO1 */
-    {
-      filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1;
- 8001338:	687b      	ldr	r3, [r7, #4]
- 800133a:	681b      	ldr	r3, [r3, #0]
- 800133c:	691b      	ldr	r3, [r3, #16]
- 800133e:	f003 0303 	and.w	r3, r3, #3
- 8001342:	60fb      	str	r3, [r7, #12]
-    }
-  }
-
-  /* Return Rx FIFO fill level */
-  return filllevel;
- 8001344:	68fb      	ldr	r3, [r7, #12]
-}
- 8001346:	4618      	mov	r0, r3
- 8001348:	3714      	adds	r7, #20
- 800134a:	46bd      	mov	sp, r7
- 800134c:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001350:	4770      	bx	lr
-	...
-
-08001354 <__NVIC_SetPriorityGrouping>:
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- 8001354:	b480      	push	{r7}
- 8001356:	b085      	sub	sp, #20
- 8001358:	af00      	add	r7, sp, #0
- 800135a:	6078      	str	r0, [r7, #4]
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
- 800135c:	687b      	ldr	r3, [r7, #4]
- 800135e:	f003 0307 	and.w	r3, r3, #7
- 8001362:	60fb      	str	r3, [r7, #12]
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
- 8001364:	4b0c      	ldr	r3, [pc, #48]	; (8001398 <__NVIC_SetPriorityGrouping+0x44>)
- 8001366:	68db      	ldr	r3, [r3, #12]
- 8001368:	60bb      	str	r3, [r7, #8]
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
- 800136a:	68ba      	ldr	r2, [r7, #8]
- 800136c:	f64f 03ff 	movw	r3, #63743	; 0xf8ff
- 8001370:	4013      	ands	r3, r2
- 8001372:	60bb      	str	r3, [r7, #8]
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
- 8001374:	68fb      	ldr	r3, [r7, #12]
- 8001376:	021a      	lsls	r2, r3, #8
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- 8001378:	68bb      	ldr	r3, [r7, #8]
- 800137a:	4313      	orrs	r3, r2
-  reg_value  =  (reg_value                                   |
- 800137c:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
- 8001380:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
- 8001384:	60bb      	str	r3, [r7, #8]
-  SCB->AIRCR =  reg_value;
- 8001386:	4a04      	ldr	r2, [pc, #16]	; (8001398 <__NVIC_SetPriorityGrouping+0x44>)
- 8001388:	68bb      	ldr	r3, [r7, #8]
- 800138a:	60d3      	str	r3, [r2, #12]
-}
- 800138c:	bf00      	nop
- 800138e:	3714      	adds	r7, #20
- 8001390:	46bd      	mov	sp, r7
- 8001392:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001396:	4770      	bx	lr
- 8001398:	e000ed00 	.word	0xe000ed00
-
-0800139c <__NVIC_GetPriorityGrouping>:
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
- 800139c:	b480      	push	{r7}
- 800139e:	af00      	add	r7, sp, #0
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
- 80013a0:	4b04      	ldr	r3, [pc, #16]	; (80013b4 <__NVIC_GetPriorityGrouping+0x18>)
- 80013a2:	68db      	ldr	r3, [r3, #12]
- 80013a4:	0a1b      	lsrs	r3, r3, #8
- 80013a6:	f003 0307 	and.w	r3, r3, #7
-}
- 80013aa:	4618      	mov	r0, r3
- 80013ac:	46bd      	mov	sp, r7
- 80013ae:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80013b2:	4770      	bx	lr
- 80013b4:	e000ed00 	.word	0xe000ed00
-
-080013b8 <__NVIC_SetPriority>:
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- 80013b8:	b480      	push	{r7}
- 80013ba:	b083      	sub	sp, #12
- 80013bc:	af00      	add	r7, sp, #0
- 80013be:	4603      	mov	r3, r0
- 80013c0:	6039      	str	r1, [r7, #0]
- 80013c2:	71fb      	strb	r3, [r7, #7]
-  if ((int32_t)(IRQn) >= 0)
- 80013c4:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 80013c8:	2b00      	cmp	r3, #0
- 80013ca:	db0a      	blt.n	80013e2 <__NVIC_SetPriority+0x2a>
-  {
-    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 80013cc:	683b      	ldr	r3, [r7, #0]
- 80013ce:	b2da      	uxtb	r2, r3
- 80013d0:	490c      	ldr	r1, [pc, #48]	; (8001404 <__NVIC_SetPriority+0x4c>)
- 80013d2:	f997 3007 	ldrsb.w	r3, [r7, #7]
- 80013d6:	0112      	lsls	r2, r2, #4
- 80013d8:	b2d2      	uxtb	r2, r2
- 80013da:	440b      	add	r3, r1
- 80013dc:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
-  }
-  else
-  {
-    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
- 80013e0:	e00a      	b.n	80013f8 <__NVIC_SetPriority+0x40>
-    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- 80013e2:	683b      	ldr	r3, [r7, #0]
- 80013e4:	b2da      	uxtb	r2, r3
- 80013e6:	4908      	ldr	r1, [pc, #32]	; (8001408 <__NVIC_SetPriority+0x50>)
- 80013e8:	79fb      	ldrb	r3, [r7, #7]
- 80013ea:	f003 030f 	and.w	r3, r3, #15
- 80013ee:	3b04      	subs	r3, #4
- 80013f0:	0112      	lsls	r2, r2, #4
- 80013f2:	b2d2      	uxtb	r2, r2
- 80013f4:	440b      	add	r3, r1
- 80013f6:	761a      	strb	r2, [r3, #24]
-}
- 80013f8:	bf00      	nop
- 80013fa:	370c      	adds	r7, #12
- 80013fc:	46bd      	mov	sp, r7
- 80013fe:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001402:	4770      	bx	lr
- 8001404:	e000e100 	.word	0xe000e100
- 8001408:	e000ed00 	.word	0xe000ed00
-
-0800140c <NVIC_EncodePriority>:
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- 800140c:	b480      	push	{r7}
- 800140e:	b089      	sub	sp, #36	; 0x24
- 8001410:	af00      	add	r7, sp, #0
- 8001412:	60f8      	str	r0, [r7, #12]
- 8001414:	60b9      	str	r1, [r7, #8]
- 8001416:	607a      	str	r2, [r7, #4]
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
- 8001418:	68fb      	ldr	r3, [r7, #12]
- 800141a:	f003 0307 	and.w	r3, r3, #7
- 800141e:	61fb      	str	r3, [r7, #28]
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- 8001420:	69fb      	ldr	r3, [r7, #28]
- 8001422:	f1c3 0307 	rsb	r3, r3, #7
- 8001426:	2b04      	cmp	r3, #4
- 8001428:	bf28      	it	cs
- 800142a:	2304      	movcs	r3, #4
- 800142c:	61bb      	str	r3, [r7, #24]
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
- 800142e:	69fb      	ldr	r3, [r7, #28]
- 8001430:	3304      	adds	r3, #4
- 8001432:	2b06      	cmp	r3, #6
- 8001434:	d902      	bls.n	800143c <NVIC_EncodePriority+0x30>
- 8001436:	69fb      	ldr	r3, [r7, #28]
- 8001438:	3b03      	subs	r3, #3
- 800143a:	e000      	b.n	800143e <NVIC_EncodePriority+0x32>
- 800143c:	2300      	movs	r3, #0
- 800143e:	617b      	str	r3, [r7, #20]
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8001440:	f04f 32ff 	mov.w	r2, #4294967295
- 8001444:	69bb      	ldr	r3, [r7, #24]
- 8001446:	fa02 f303 	lsl.w	r3, r2, r3
- 800144a:	43da      	mvns	r2, r3
- 800144c:	68bb      	ldr	r3, [r7, #8]
- 800144e:	401a      	ands	r2, r3
- 8001450:	697b      	ldr	r3, [r7, #20]
- 8001452:	409a      	lsls	r2, r3
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
- 8001454:	f04f 31ff 	mov.w	r1, #4294967295
- 8001458:	697b      	ldr	r3, [r7, #20]
- 800145a:	fa01 f303 	lsl.w	r3, r1, r3
- 800145e:	43d9      	mvns	r1, r3
- 8001460:	687b      	ldr	r3, [r7, #4]
- 8001462:	400b      	ands	r3, r1
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- 8001464:	4313      	orrs	r3, r2
-         );
-}
- 8001466:	4618      	mov	r0, r3
- 8001468:	3724      	adds	r7, #36	; 0x24
- 800146a:	46bd      	mov	sp, r7
- 800146c:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001470:	4770      	bx	lr
-	...
-
-08001474 <SysTick_Config>:
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- 8001474:	b580      	push	{r7, lr}
- 8001476:	b082      	sub	sp, #8
- 8001478:	af00      	add	r7, sp, #0
- 800147a:	6078      	str	r0, [r7, #4]
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- 800147c:	687b      	ldr	r3, [r7, #4]
- 800147e:	3b01      	subs	r3, #1
- 8001480:	f1b3 7f80 	cmp.w	r3, #16777216	; 0x1000000
- 8001484:	d301      	bcc.n	800148a <SysTick_Config+0x16>
-  {
-    return (1UL);                                                   /* Reload value impossible */
- 8001486:	2301      	movs	r3, #1
- 8001488:	e00f      	b.n	80014aa <SysTick_Config+0x36>
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
- 800148a:	4a0a      	ldr	r2, [pc, #40]	; (80014b4 <SysTick_Config+0x40>)
- 800148c:	687b      	ldr	r3, [r7, #4]
- 800148e:	3b01      	subs	r3, #1
- 8001490:	6053      	str	r3, [r2, #4]
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- 8001492:	210f      	movs	r1, #15
- 8001494:	f04f 30ff 	mov.w	r0, #4294967295
- 8001498:	f7ff ff8e 	bl	80013b8 <__NVIC_SetPriority>
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
- 800149c:	4b05      	ldr	r3, [pc, #20]	; (80014b4 <SysTick_Config+0x40>)
- 800149e:	2200      	movs	r2, #0
- 80014a0:	609a      	str	r2, [r3, #8]
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
- 80014a2:	4b04      	ldr	r3, [pc, #16]	; (80014b4 <SysTick_Config+0x40>)
- 80014a4:	2207      	movs	r2, #7
- 80014a6:	601a      	str	r2, [r3, #0]
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
- 80014a8:	2300      	movs	r3, #0
-}
- 80014aa:	4618      	mov	r0, r3
- 80014ac:	3708      	adds	r7, #8
- 80014ae:	46bd      	mov	sp, r7
- 80014b0:	bd80      	pop	{r7, pc}
- 80014b2:	bf00      	nop
- 80014b4:	e000e010 	.word	0xe000e010
-
-080014b8 <HAL_NVIC_SetPriorityGrouping>:
-  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
-  *         The pending IRQ priority will be managed only by the subpriority. 
-  * @retval None
-  */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- 80014b8:	b580      	push	{r7, lr}
- 80014ba:	b082      	sub	sp, #8
- 80014bc:	af00      	add	r7, sp, #0
- 80014be:	6078      	str	r0, [r7, #4]
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-  
-  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
-  NVIC_SetPriorityGrouping(PriorityGroup);
- 80014c0:	6878      	ldr	r0, [r7, #4]
- 80014c2:	f7ff ff47 	bl	8001354 <__NVIC_SetPriorityGrouping>
-}
- 80014c6:	bf00      	nop
- 80014c8:	3708      	adds	r7, #8
- 80014ca:	46bd      	mov	sp, r7
- 80014cc:	bd80      	pop	{r7, pc}
-
-080014ce <HAL_NVIC_SetPriority>:
-  *         This parameter can be a value between 0 and 15
-  *         A lower priority value indicates a higher priority.          
-  * @retval None
-  */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{ 
- 80014ce:	b580      	push	{r7, lr}
- 80014d0:	b086      	sub	sp, #24
- 80014d2:	af00      	add	r7, sp, #0
- 80014d4:	4603      	mov	r3, r0
- 80014d6:	60b9      	str	r1, [r7, #8]
- 80014d8:	607a      	str	r2, [r7, #4]
- 80014da:	73fb      	strb	r3, [r7, #15]
-  uint32_t prioritygroup = 0x00U;
- 80014dc:	2300      	movs	r3, #0
- 80014de:	617b      	str	r3, [r7, #20]
-  
-  /* Check the parameters */
-  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-  
-  prioritygroup = NVIC_GetPriorityGrouping();
- 80014e0:	f7ff ff5c 	bl	800139c <__NVIC_GetPriorityGrouping>
- 80014e4:	6178      	str	r0, [r7, #20]
-  
-  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
- 80014e6:	687a      	ldr	r2, [r7, #4]
- 80014e8:	68b9      	ldr	r1, [r7, #8]
- 80014ea:	6978      	ldr	r0, [r7, #20]
- 80014ec:	f7ff ff8e 	bl	800140c <NVIC_EncodePriority>
- 80014f0:	4602      	mov	r2, r0
- 80014f2:	f997 300f 	ldrsb.w	r3, [r7, #15]
- 80014f6:	4611      	mov	r1, r2
- 80014f8:	4618      	mov	r0, r3
- 80014fa:	f7ff ff5d 	bl	80013b8 <__NVIC_SetPriority>
-}
- 80014fe:	bf00      	nop
- 8001500:	3718      	adds	r7, #24
- 8001502:	46bd      	mov	sp, r7
- 8001504:	bd80      	pop	{r7, pc}
-
-08001506 <HAL_SYSTICK_Config>:
-  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
-  * @retval status:  - 0  Function succeeded.
-  *                  - 1  Function failed.
-  */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
- 8001506:	b580      	push	{r7, lr}
- 8001508:	b082      	sub	sp, #8
- 800150a:	af00      	add	r7, sp, #0
- 800150c:	6078      	str	r0, [r7, #4]
-   return SysTick_Config(TicksNumb);
- 800150e:	6878      	ldr	r0, [r7, #4]
- 8001510:	f7ff ffb0 	bl	8001474 <SysTick_Config>
- 8001514:	4603      	mov	r3, r0
-}
- 8001516:	4618      	mov	r0, r3
- 8001518:	3708      	adds	r7, #8
- 800151a:	46bd      	mov	sp, r7
- 800151c:	bd80      	pop	{r7, pc}
-	...
-
-08001520 <HAL_GPIO_Init>:
-  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
-  *         the configuration information for the specified GPIO peripheral.
-  * @retval None
-  */
-void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
- 8001520:	b480      	push	{r7}
- 8001522:	b089      	sub	sp, #36	; 0x24
- 8001524:	af00      	add	r7, sp, #0
- 8001526:	6078      	str	r0, [r7, #4]
- 8001528:	6039      	str	r1, [r7, #0]
-  uint32_t position;
-  uint32_t ioposition = 0x00U;
- 800152a:	2300      	movs	r3, #0
- 800152c:	617b      	str	r3, [r7, #20]
-  uint32_t iocurrent = 0x00U;
- 800152e:	2300      	movs	r3, #0
- 8001530:	613b      	str	r3, [r7, #16]
-  uint32_t temp = 0x00U;
- 8001532:	2300      	movs	r3, #0
- 8001534:	61bb      	str	r3, [r7, #24]
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
-  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
-
-  /* Configure the port pins */
-  for(position = 0U; position < GPIO_NUMBER; position++)
- 8001536:	2300      	movs	r3, #0
- 8001538:	61fb      	str	r3, [r7, #28]
- 800153a:	e16b      	b.n	8001814 <HAL_GPIO_Init+0x2f4>
-  {
-    /* Get the IO position */
-    ioposition = 0x01U << position;
- 800153c:	2201      	movs	r2, #1
- 800153e:	69fb      	ldr	r3, [r7, #28]
- 8001540:	fa02 f303 	lsl.w	r3, r2, r3
- 8001544:	617b      	str	r3, [r7, #20]
-    /* Get the current IO position */
-    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
- 8001546:	683b      	ldr	r3, [r7, #0]
- 8001548:	681b      	ldr	r3, [r3, #0]
- 800154a:	697a      	ldr	r2, [r7, #20]
- 800154c:	4013      	ands	r3, r2
- 800154e:	613b      	str	r3, [r7, #16]
-
-    if(iocurrent == ioposition)
- 8001550:	693a      	ldr	r2, [r7, #16]
- 8001552:	697b      	ldr	r3, [r7, #20]
- 8001554:	429a      	cmp	r2, r3
- 8001556:	f040 815a 	bne.w	800180e <HAL_GPIO_Init+0x2ee>
-    {
-      /*--------------------- GPIO Mode Configuration ------------------------*/
-      /* In case of Output or Alternate function mode selection */
-      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
- 800155a:	683b      	ldr	r3, [r7, #0]
- 800155c:	685b      	ldr	r3, [r3, #4]
- 800155e:	f003 0303 	and.w	r3, r3, #3
- 8001562:	2b01      	cmp	r3, #1
- 8001564:	d005      	beq.n	8001572 <HAL_GPIO_Init+0x52>
-          (GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
- 8001566:	683b      	ldr	r3, [r7, #0]
- 8001568:	685b      	ldr	r3, [r3, #4]
- 800156a:	f003 0303 	and.w	r3, r3, #3
-      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
- 800156e:	2b02      	cmp	r3, #2
- 8001570:	d130      	bne.n	80015d4 <HAL_GPIO_Init+0xb4>
-      {
-        /* Check the Speed parameter */
-        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
-        /* Configure the IO Speed */
-        temp = GPIOx->OSPEEDR; 
- 8001572:	687b      	ldr	r3, [r7, #4]
- 8001574:	689b      	ldr	r3, [r3, #8]
- 8001576:	61bb      	str	r3, [r7, #24]
-        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
- 8001578:	69fb      	ldr	r3, [r7, #28]
- 800157a:	005b      	lsls	r3, r3, #1
- 800157c:	2203      	movs	r2, #3
- 800157e:	fa02 f303 	lsl.w	r3, r2, r3
- 8001582:	43db      	mvns	r3, r3
- 8001584:	69ba      	ldr	r2, [r7, #24]
- 8001586:	4013      	ands	r3, r2
- 8001588:	61bb      	str	r3, [r7, #24]
-        temp |= (GPIO_Init->Speed << (position * 2U));
- 800158a:	683b      	ldr	r3, [r7, #0]
- 800158c:	68da      	ldr	r2, [r3, #12]
- 800158e:	69fb      	ldr	r3, [r7, #28]
- 8001590:	005b      	lsls	r3, r3, #1
- 8001592:	fa02 f303 	lsl.w	r3, r2, r3
- 8001596:	69ba      	ldr	r2, [r7, #24]
- 8001598:	4313      	orrs	r3, r2
- 800159a:	61bb      	str	r3, [r7, #24]
-        GPIOx->OSPEEDR = temp;
- 800159c:	687b      	ldr	r3, [r7, #4]
- 800159e:	69ba      	ldr	r2, [r7, #24]
- 80015a0:	609a      	str	r2, [r3, #8]
-
-        /* Configure the IO Output Type */
-        temp = GPIOx->OTYPER;
- 80015a2:	687b      	ldr	r3, [r7, #4]
- 80015a4:	685b      	ldr	r3, [r3, #4]
- 80015a6:	61bb      	str	r3, [r7, #24]
-        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
- 80015a8:	2201      	movs	r2, #1
- 80015aa:	69fb      	ldr	r3, [r7, #28]
- 80015ac:	fa02 f303 	lsl.w	r3, r2, r3
- 80015b0:	43db      	mvns	r3, r3
- 80015b2:	69ba      	ldr	r2, [r7, #24]
- 80015b4:	4013      	ands	r3, r2
- 80015b6:	61bb      	str	r3, [r7, #24]
-        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
- 80015b8:	683b      	ldr	r3, [r7, #0]
- 80015ba:	685b      	ldr	r3, [r3, #4]
- 80015bc:	091b      	lsrs	r3, r3, #4
- 80015be:	f003 0201 	and.w	r2, r3, #1
- 80015c2:	69fb      	ldr	r3, [r7, #28]
- 80015c4:	fa02 f303 	lsl.w	r3, r2, r3
- 80015c8:	69ba      	ldr	r2, [r7, #24]
- 80015ca:	4313      	orrs	r3, r2
- 80015cc:	61bb      	str	r3, [r7, #24]
-        GPIOx->OTYPER = temp;
- 80015ce:	687b      	ldr	r3, [r7, #4]
- 80015d0:	69ba      	ldr	r2, [r7, #24]
- 80015d2:	605a      	str	r2, [r3, #4]
-       }
-
-      if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
- 80015d4:	683b      	ldr	r3, [r7, #0]
- 80015d6:	685b      	ldr	r3, [r3, #4]
- 80015d8:	f003 0303 	and.w	r3, r3, #3
- 80015dc:	2b03      	cmp	r3, #3
- 80015de:	d017      	beq.n	8001610 <HAL_GPIO_Init+0xf0>
-      {
-        /* Check the parameters */
-        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-        
-        /* Activate the Pull-up or Pull down resistor for the current IO */
-        temp = GPIOx->PUPDR;
- 80015e0:	687b      	ldr	r3, [r7, #4]
- 80015e2:	68db      	ldr	r3, [r3, #12]
- 80015e4:	61bb      	str	r3, [r7, #24]
-        temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
- 80015e6:	69fb      	ldr	r3, [r7, #28]
- 80015e8:	005b      	lsls	r3, r3, #1
- 80015ea:	2203      	movs	r2, #3
- 80015ec:	fa02 f303 	lsl.w	r3, r2, r3
- 80015f0:	43db      	mvns	r3, r3
- 80015f2:	69ba      	ldr	r2, [r7, #24]
- 80015f4:	4013      	ands	r3, r2
- 80015f6:	61bb      	str	r3, [r7, #24]
-        temp |= ((GPIO_Init->Pull) << (position * 2U));
- 80015f8:	683b      	ldr	r3, [r7, #0]
- 80015fa:	689a      	ldr	r2, [r3, #8]
- 80015fc:	69fb      	ldr	r3, [r7, #28]
- 80015fe:	005b      	lsls	r3, r3, #1
- 8001600:	fa02 f303 	lsl.w	r3, r2, r3
- 8001604:	69ba      	ldr	r2, [r7, #24]
- 8001606:	4313      	orrs	r3, r2
- 8001608:	61bb      	str	r3, [r7, #24]
-        GPIOx->PUPDR = temp;
- 800160a:	687b      	ldr	r3, [r7, #4]
- 800160c:	69ba      	ldr	r2, [r7, #24]
- 800160e:	60da      	str	r2, [r3, #12]
-      }
-
-      /* In case of Alternate function mode selection */
-      if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
- 8001610:	683b      	ldr	r3, [r7, #0]
- 8001612:	685b      	ldr	r3, [r3, #4]
- 8001614:	f003 0303 	and.w	r3, r3, #3
- 8001618:	2b02      	cmp	r3, #2
- 800161a:	d123      	bne.n	8001664 <HAL_GPIO_Init+0x144>
-      {
-        /* Check the Alternate function parameter */
-        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-        /* Configure Alternate function mapped with the current IO */
-        temp = GPIOx->AFR[position >> 3U];
- 800161c:	69fb      	ldr	r3, [r7, #28]
- 800161e:	08da      	lsrs	r2, r3, #3
- 8001620:	687b      	ldr	r3, [r7, #4]
- 8001622:	3208      	adds	r2, #8
- 8001624:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
- 8001628:	61bb      	str	r3, [r7, #24]
-        temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
- 800162a:	69fb      	ldr	r3, [r7, #28]
- 800162c:	f003 0307 	and.w	r3, r3, #7
- 8001630:	009b      	lsls	r3, r3, #2
- 8001632:	220f      	movs	r2, #15
- 8001634:	fa02 f303 	lsl.w	r3, r2, r3
- 8001638:	43db      	mvns	r3, r3
- 800163a:	69ba      	ldr	r2, [r7, #24]
- 800163c:	4013      	ands	r3, r2
- 800163e:	61bb      	str	r3, [r7, #24]
-        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
- 8001640:	683b      	ldr	r3, [r7, #0]
- 8001642:	691a      	ldr	r2, [r3, #16]
- 8001644:	69fb      	ldr	r3, [r7, #28]
- 8001646:	f003 0307 	and.w	r3, r3, #7
- 800164a:	009b      	lsls	r3, r3, #2
- 800164c:	fa02 f303 	lsl.w	r3, r2, r3
- 8001650:	69ba      	ldr	r2, [r7, #24]
- 8001652:	4313      	orrs	r3, r2
- 8001654:	61bb      	str	r3, [r7, #24]
-        GPIOx->AFR[position >> 3U] = temp;
- 8001656:	69fb      	ldr	r3, [r7, #28]
- 8001658:	08da      	lsrs	r2, r3, #3
- 800165a:	687b      	ldr	r3, [r7, #4]
- 800165c:	3208      	adds	r2, #8
- 800165e:	69b9      	ldr	r1, [r7, #24]
- 8001660:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
-      }
-
-      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
-      temp = GPIOx->MODER;
- 8001664:	687b      	ldr	r3, [r7, #4]
- 8001666:	681b      	ldr	r3, [r3, #0]
- 8001668:	61bb      	str	r3, [r7, #24]
-      temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
- 800166a:	69fb      	ldr	r3, [r7, #28]
- 800166c:	005b      	lsls	r3, r3, #1
- 800166e:	2203      	movs	r2, #3
- 8001670:	fa02 f303 	lsl.w	r3, r2, r3
- 8001674:	43db      	mvns	r3, r3
- 8001676:	69ba      	ldr	r2, [r7, #24]
- 8001678:	4013      	ands	r3, r2
- 800167a:	61bb      	str	r3, [r7, #24]
-      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
- 800167c:	683b      	ldr	r3, [r7, #0]
- 800167e:	685b      	ldr	r3, [r3, #4]
- 8001680:	f003 0203 	and.w	r2, r3, #3
- 8001684:	69fb      	ldr	r3, [r7, #28]
- 8001686:	005b      	lsls	r3, r3, #1
- 8001688:	fa02 f303 	lsl.w	r3, r2, r3
- 800168c:	69ba      	ldr	r2, [r7, #24]
- 800168e:	4313      	orrs	r3, r2
- 8001690:	61bb      	str	r3, [r7, #24]
-      GPIOx->MODER = temp;
- 8001692:	687b      	ldr	r3, [r7, #4]
- 8001694:	69ba      	ldr	r2, [r7, #24]
- 8001696:	601a      	str	r2, [r3, #0]
-
-      /*--------------------- EXTI Mode Configuration ------------------------*/
-      /* Configure the External Interrupt or event for the current IO */
-      if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
- 8001698:	683b      	ldr	r3, [r7, #0]
- 800169a:	685b      	ldr	r3, [r3, #4]
- 800169c:	f403 3340 	and.w	r3, r3, #196608	; 0x30000
- 80016a0:	2b00      	cmp	r3, #0
- 80016a2:	f000 80b4 	beq.w	800180e <HAL_GPIO_Init+0x2ee>
-      {
-        /* Enable SYSCFG Clock */
-        __HAL_RCC_SYSCFG_CLK_ENABLE();
- 80016a6:	2300      	movs	r3, #0
- 80016a8:	60fb      	str	r3, [r7, #12]
- 80016aa:	4b60      	ldr	r3, [pc, #384]	; (800182c <HAL_GPIO_Init+0x30c>)
- 80016ac:	6c5b      	ldr	r3, [r3, #68]	; 0x44
- 80016ae:	4a5f      	ldr	r2, [pc, #380]	; (800182c <HAL_GPIO_Init+0x30c>)
- 80016b0:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
- 80016b4:	6453      	str	r3, [r2, #68]	; 0x44
- 80016b6:	4b5d      	ldr	r3, [pc, #372]	; (800182c <HAL_GPIO_Init+0x30c>)
- 80016b8:	6c5b      	ldr	r3, [r3, #68]	; 0x44
- 80016ba:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
- 80016be:	60fb      	str	r3, [r7, #12]
- 80016c0:	68fb      	ldr	r3, [r7, #12]
-
-        temp = SYSCFG->EXTICR[position >> 2U];
- 80016c2:	4a5b      	ldr	r2, [pc, #364]	; (8001830 <HAL_GPIO_Init+0x310>)
- 80016c4:	69fb      	ldr	r3, [r7, #28]
- 80016c6:	089b      	lsrs	r3, r3, #2
- 80016c8:	3302      	adds	r3, #2
- 80016ca:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
- 80016ce:	61bb      	str	r3, [r7, #24]
-        temp &= ~(0x0FU << (4U * (position & 0x03U)));
- 80016d0:	69fb      	ldr	r3, [r7, #28]
- 80016d2:	f003 0303 	and.w	r3, r3, #3
- 80016d6:	009b      	lsls	r3, r3, #2
- 80016d8:	220f      	movs	r2, #15
- 80016da:	fa02 f303 	lsl.w	r3, r2, r3
- 80016de:	43db      	mvns	r3, r3
- 80016e0:	69ba      	ldr	r2, [r7, #24]
- 80016e2:	4013      	ands	r3, r2
- 80016e4:	61bb      	str	r3, [r7, #24]
-        temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
- 80016e6:	687b      	ldr	r3, [r7, #4]
- 80016e8:	4a52      	ldr	r2, [pc, #328]	; (8001834 <HAL_GPIO_Init+0x314>)
- 80016ea:	4293      	cmp	r3, r2
- 80016ec:	d02b      	beq.n	8001746 <HAL_GPIO_Init+0x226>
- 80016ee:	687b      	ldr	r3, [r7, #4]
- 80016f0:	4a51      	ldr	r2, [pc, #324]	; (8001838 <HAL_GPIO_Init+0x318>)
- 80016f2:	4293      	cmp	r3, r2
- 80016f4:	d025      	beq.n	8001742 <HAL_GPIO_Init+0x222>
- 80016f6:	687b      	ldr	r3, [r7, #4]
- 80016f8:	4a50      	ldr	r2, [pc, #320]	; (800183c <HAL_GPIO_Init+0x31c>)
- 80016fa:	4293      	cmp	r3, r2
- 80016fc:	d01f      	beq.n	800173e <HAL_GPIO_Init+0x21e>
- 80016fe:	687b      	ldr	r3, [r7, #4]
- 8001700:	4a4f      	ldr	r2, [pc, #316]	; (8001840 <HAL_GPIO_Init+0x320>)
- 8001702:	4293      	cmp	r3, r2
- 8001704:	d019      	beq.n	800173a <HAL_GPIO_Init+0x21a>
- 8001706:	687b      	ldr	r3, [r7, #4]
- 8001708:	4a4e      	ldr	r2, [pc, #312]	; (8001844 <HAL_GPIO_Init+0x324>)
- 800170a:	4293      	cmp	r3, r2
- 800170c:	d013      	beq.n	8001736 <HAL_GPIO_Init+0x216>
- 800170e:	687b      	ldr	r3, [r7, #4]
- 8001710:	4a4d      	ldr	r2, [pc, #308]	; (8001848 <HAL_GPIO_Init+0x328>)
- 8001712:	4293      	cmp	r3, r2
- 8001714:	d00d      	beq.n	8001732 <HAL_GPIO_Init+0x212>
- 8001716:	687b      	ldr	r3, [r7, #4]
- 8001718:	4a4c      	ldr	r2, [pc, #304]	; (800184c <HAL_GPIO_Init+0x32c>)
- 800171a:	4293      	cmp	r3, r2
- 800171c:	d007      	beq.n	800172e <HAL_GPIO_Init+0x20e>
- 800171e:	687b      	ldr	r3, [r7, #4]
- 8001720:	4a4b      	ldr	r2, [pc, #300]	; (8001850 <HAL_GPIO_Init+0x330>)
- 8001722:	4293      	cmp	r3, r2
- 8001724:	d101      	bne.n	800172a <HAL_GPIO_Init+0x20a>
- 8001726:	2307      	movs	r3, #7
- 8001728:	e00e      	b.n	8001748 <HAL_GPIO_Init+0x228>
- 800172a:	2308      	movs	r3, #8
- 800172c:	e00c      	b.n	8001748 <HAL_GPIO_Init+0x228>
- 800172e:	2306      	movs	r3, #6
- 8001730:	e00a      	b.n	8001748 <HAL_GPIO_Init+0x228>
- 8001732:	2305      	movs	r3, #5
- 8001734:	e008      	b.n	8001748 <HAL_GPIO_Init+0x228>
- 8001736:	2304      	movs	r3, #4
- 8001738:	e006      	b.n	8001748 <HAL_GPIO_Init+0x228>
- 800173a:	2303      	movs	r3, #3
- 800173c:	e004      	b.n	8001748 <HAL_GPIO_Init+0x228>
- 800173e:	2302      	movs	r3, #2
- 8001740:	e002      	b.n	8001748 <HAL_GPIO_Init+0x228>
- 8001742:	2301      	movs	r3, #1
- 8001744:	e000      	b.n	8001748 <HAL_GPIO_Init+0x228>
- 8001746:	2300      	movs	r3, #0
- 8001748:	69fa      	ldr	r2, [r7, #28]
- 800174a:	f002 0203 	and.w	r2, r2, #3
- 800174e:	0092      	lsls	r2, r2, #2
- 8001750:	4093      	lsls	r3, r2
- 8001752:	69ba      	ldr	r2, [r7, #24]
- 8001754:	4313      	orrs	r3, r2
- 8001756:	61bb      	str	r3, [r7, #24]
-        SYSCFG->EXTICR[position >> 2U] = temp;
- 8001758:	4935      	ldr	r1, [pc, #212]	; (8001830 <HAL_GPIO_Init+0x310>)
- 800175a:	69fb      	ldr	r3, [r7, #28]
- 800175c:	089b      	lsrs	r3, r3, #2
- 800175e:	3302      	adds	r3, #2
- 8001760:	69ba      	ldr	r2, [r7, #24]
- 8001762:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
-
-        /* Clear Rising Falling edge configuration */
-        temp = EXTI->RTSR;
- 8001766:	4b3b      	ldr	r3, [pc, #236]	; (8001854 <HAL_GPIO_Init+0x334>)
- 8001768:	689b      	ldr	r3, [r3, #8]
- 800176a:	61bb      	str	r3, [r7, #24]
-        temp &= ~((uint32_t)iocurrent);
- 800176c:	693b      	ldr	r3, [r7, #16]
- 800176e:	43db      	mvns	r3, r3
- 8001770:	69ba      	ldr	r2, [r7, #24]
- 8001772:	4013      	ands	r3, r2
- 8001774:	61bb      	str	r3, [r7, #24]
-        if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
- 8001776:	683b      	ldr	r3, [r7, #0]
- 8001778:	685b      	ldr	r3, [r3, #4]
- 800177a:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
- 800177e:	2b00      	cmp	r3, #0
- 8001780:	d003      	beq.n	800178a <HAL_GPIO_Init+0x26a>
-        {
-          temp |= iocurrent;
- 8001782:	69ba      	ldr	r2, [r7, #24]
- 8001784:	693b      	ldr	r3, [r7, #16]
- 8001786:	4313      	orrs	r3, r2
- 8001788:	61bb      	str	r3, [r7, #24]
-        }
-        EXTI->RTSR = temp;
- 800178a:	4a32      	ldr	r2, [pc, #200]	; (8001854 <HAL_GPIO_Init+0x334>)
- 800178c:	69bb      	ldr	r3, [r7, #24]
- 800178e:	6093      	str	r3, [r2, #8]
-
-        temp = EXTI->FTSR;
- 8001790:	4b30      	ldr	r3, [pc, #192]	; (8001854 <HAL_GPIO_Init+0x334>)
- 8001792:	68db      	ldr	r3, [r3, #12]
- 8001794:	61bb      	str	r3, [r7, #24]
-        temp &= ~((uint32_t)iocurrent);
- 8001796:	693b      	ldr	r3, [r7, #16]
- 8001798:	43db      	mvns	r3, r3
- 800179a:	69ba      	ldr	r2, [r7, #24]
- 800179c:	4013      	ands	r3, r2
- 800179e:	61bb      	str	r3, [r7, #24]
-        if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
- 80017a0:	683b      	ldr	r3, [r7, #0]
- 80017a2:	685b      	ldr	r3, [r3, #4]
- 80017a4:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
- 80017a8:	2b00      	cmp	r3, #0
- 80017aa:	d003      	beq.n	80017b4 <HAL_GPIO_Init+0x294>
-        {
-          temp |= iocurrent;
- 80017ac:	69ba      	ldr	r2, [r7, #24]
- 80017ae:	693b      	ldr	r3, [r7, #16]
- 80017b0:	4313      	orrs	r3, r2
- 80017b2:	61bb      	str	r3, [r7, #24]
-        }
-        EXTI->FTSR = temp;
- 80017b4:	4a27      	ldr	r2, [pc, #156]	; (8001854 <HAL_GPIO_Init+0x334>)
- 80017b6:	69bb      	ldr	r3, [r7, #24]
- 80017b8:	60d3      	str	r3, [r2, #12]
-
-        temp = EXTI->EMR;
- 80017ba:	4b26      	ldr	r3, [pc, #152]	; (8001854 <HAL_GPIO_Init+0x334>)
- 80017bc:	685b      	ldr	r3, [r3, #4]
- 80017be:	61bb      	str	r3, [r7, #24]
-        temp &= ~((uint32_t)iocurrent);
- 80017c0:	693b      	ldr	r3, [r7, #16]
- 80017c2:	43db      	mvns	r3, r3
- 80017c4:	69ba      	ldr	r2, [r7, #24]
- 80017c6:	4013      	ands	r3, r2
- 80017c8:	61bb      	str	r3, [r7, #24]
-        if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
- 80017ca:	683b      	ldr	r3, [r7, #0]
- 80017cc:	685b      	ldr	r3, [r3, #4]
- 80017ce:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 80017d2:	2b00      	cmp	r3, #0
- 80017d4:	d003      	beq.n	80017de <HAL_GPIO_Init+0x2be>
-        {
-          temp |= iocurrent;
- 80017d6:	69ba      	ldr	r2, [r7, #24]
- 80017d8:	693b      	ldr	r3, [r7, #16]
- 80017da:	4313      	orrs	r3, r2
- 80017dc:	61bb      	str	r3, [r7, #24]
-        }
-        EXTI->EMR = temp;
- 80017de:	4a1d      	ldr	r2, [pc, #116]	; (8001854 <HAL_GPIO_Init+0x334>)
- 80017e0:	69bb      	ldr	r3, [r7, #24]
- 80017e2:	6053      	str	r3, [r2, #4]
-
-        /* Clear EXTI line configuration */
-        temp = EXTI->IMR;
- 80017e4:	4b1b      	ldr	r3, [pc, #108]	; (8001854 <HAL_GPIO_Init+0x334>)
- 80017e6:	681b      	ldr	r3, [r3, #0]
- 80017e8:	61bb      	str	r3, [r7, #24]
-        temp &= ~((uint32_t)iocurrent);
- 80017ea:	693b      	ldr	r3, [r7, #16]
- 80017ec:	43db      	mvns	r3, r3
- 80017ee:	69ba      	ldr	r2, [r7, #24]
- 80017f0:	4013      	ands	r3, r2
- 80017f2:	61bb      	str	r3, [r7, #24]
-        if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
- 80017f4:	683b      	ldr	r3, [r7, #0]
- 80017f6:	685b      	ldr	r3, [r3, #4]
- 80017f8:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
- 80017fc:	2b00      	cmp	r3, #0
- 80017fe:	d003      	beq.n	8001808 <HAL_GPIO_Init+0x2e8>
-        {
-          temp |= iocurrent;
- 8001800:	69ba      	ldr	r2, [r7, #24]
- 8001802:	693b      	ldr	r3, [r7, #16]
- 8001804:	4313      	orrs	r3, r2
- 8001806:	61bb      	str	r3, [r7, #24]
-        }
-        EXTI->IMR = temp;
- 8001808:	4a12      	ldr	r2, [pc, #72]	; (8001854 <HAL_GPIO_Init+0x334>)
- 800180a:	69bb      	ldr	r3, [r7, #24]
- 800180c:	6013      	str	r3, [r2, #0]
-  for(position = 0U; position < GPIO_NUMBER; position++)
- 800180e:	69fb      	ldr	r3, [r7, #28]
- 8001810:	3301      	adds	r3, #1
- 8001812:	61fb      	str	r3, [r7, #28]
- 8001814:	69fb      	ldr	r3, [r7, #28]
- 8001816:	2b0f      	cmp	r3, #15
- 8001818:	f67f ae90 	bls.w	800153c <HAL_GPIO_Init+0x1c>
-      }
-    }
-  }
-}
- 800181c:	bf00      	nop
- 800181e:	bf00      	nop
- 8001820:	3724      	adds	r7, #36	; 0x24
- 8001822:	46bd      	mov	sp, r7
- 8001824:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001828:	4770      	bx	lr
- 800182a:	bf00      	nop
- 800182c:	40023800 	.word	0x40023800
- 8001830:	40013800 	.word	0x40013800
- 8001834:	40020000 	.word	0x40020000
- 8001838:	40020400 	.word	0x40020400
- 800183c:	40020800 	.word	0x40020800
- 8001840:	40020c00 	.word	0x40020c00
- 8001844:	40021000 	.word	0x40021000
- 8001848:	40021400 	.word	0x40021400
- 800184c:	40021800 	.word	0x40021800
- 8001850:	40021c00 	.word	0x40021c00
- 8001854:	40013c00 	.word	0x40013c00
-
-08001858 <HAL_GPIO_WritePin>:
-  *            @arg GPIO_PIN_RESET: to clear the port pin
-  *            @arg GPIO_PIN_SET: to set the port pin
-  * @retval None
-  */
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
- 8001858:	b480      	push	{r7}
- 800185a:	b083      	sub	sp, #12
- 800185c:	af00      	add	r7, sp, #0
- 800185e:	6078      	str	r0, [r7, #4]
- 8001860:	460b      	mov	r3, r1
- 8001862:	807b      	strh	r3, [r7, #2]
- 8001864:	4613      	mov	r3, r2
- 8001866:	707b      	strb	r3, [r7, #1]
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-  assert_param(IS_GPIO_PIN_ACTION(PinState));
-
-  if(PinState != GPIO_PIN_RESET)
- 8001868:	787b      	ldrb	r3, [r7, #1]
- 800186a:	2b00      	cmp	r3, #0
- 800186c:	d003      	beq.n	8001876 <HAL_GPIO_WritePin+0x1e>
-  {
-    GPIOx->BSRR = GPIO_Pin;
- 800186e:	887a      	ldrh	r2, [r7, #2]
- 8001870:	687b      	ldr	r3, [r7, #4]
- 8001872:	619a      	str	r2, [r3, #24]
-  }
-  else
-  {
-    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
-  }
-}
- 8001874:	e003      	b.n	800187e <HAL_GPIO_WritePin+0x26>
-    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
- 8001876:	887b      	ldrh	r3, [r7, #2]
- 8001878:	041a      	lsls	r2, r3, #16
- 800187a:	687b      	ldr	r3, [r7, #4]
- 800187c:	619a      	str	r2, [r3, #24]
-}
- 800187e:	bf00      	nop
- 8001880:	370c      	adds	r7, #12
- 8001882:	46bd      	mov	sp, r7
- 8001884:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8001888:	4770      	bx	lr
-
-0800188a <HAL_GPIO_TogglePin>:
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
-  * @param  GPIO_Pin Specifies the pins to be toggled.
-  * @retval None
-  */
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- 800188a:	b480      	push	{r7}
- 800188c:	b085      	sub	sp, #20
- 800188e:	af00      	add	r7, sp, #0
- 8001890:	6078      	str	r0, [r7, #4]
- 8001892:	460b      	mov	r3, r1
- 8001894:	807b      	strh	r3, [r7, #2]
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  /* get current Output Data Register value */
-  odr = GPIOx->ODR;
- 8001896:	687b      	ldr	r3, [r7, #4]
- 8001898:	695b      	ldr	r3, [r3, #20]
- 800189a:	60fb      	str	r3, [r7, #12]
-
-  /* Set selected pins that were at low level, and reset ones that were high */
-  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
- 800189c:	887a      	ldrh	r2, [r7, #2]
- 800189e:	68fb      	ldr	r3, [r7, #12]
- 80018a0:	4013      	ands	r3, r2
- 80018a2:	041a      	lsls	r2, r3, #16
- 80018a4:	68fb      	ldr	r3, [r7, #12]
- 80018a6:	43d9      	mvns	r1, r3
- 80018a8:	887b      	ldrh	r3, [r7, #2]
- 80018aa:	400b      	ands	r3, r1
- 80018ac:	431a      	orrs	r2, r3
- 80018ae:	687b      	ldr	r3, [r7, #4]
- 80018b0:	619a      	str	r2, [r3, #24]
-}
- 80018b2:	bf00      	nop
- 80018b4:	3714      	adds	r7, #20
- 80018b6:	46bd      	mov	sp, r7
- 80018b8:	f85d 7b04 	ldr.w	r7, [sp], #4
- 80018bc:	4770      	bx	lr
-	...
-
-080018c0 <HAL_RCC_OscConfig>:
-  *         supported by this API. User should request a transition to HSE Off
-  *         first and then HSE On or HSE Bypass.
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
- 80018c0:	b580      	push	{r7, lr}
- 80018c2:	b086      	sub	sp, #24
- 80018c4:	af00      	add	r7, sp, #0
- 80018c6:	6078      	str	r0, [r7, #4]
-  uint32_t tickstart, pll_config;
-
-  /* Check Null pointer */
-  if(RCC_OscInitStruct == NULL)
- 80018c8:	687b      	ldr	r3, [r7, #4]
- 80018ca:	2b00      	cmp	r3, #0
- 80018cc:	d101      	bne.n	80018d2 <HAL_RCC_OscConfig+0x12>
-  {
-    return HAL_ERROR;
- 80018ce:	2301      	movs	r3, #1
- 80018d0:	e267      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
-  }
-
-  /* Check the parameters */
-  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-  /*------------------------------- HSE Configuration ------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- 80018d2:	687b      	ldr	r3, [r7, #4]
- 80018d4:	681b      	ldr	r3, [r3, #0]
- 80018d6:	f003 0301 	and.w	r3, r3, #1
- 80018da:	2b00      	cmp	r3, #0
- 80018dc:	d075      	beq.n	80019ca <HAL_RCC_OscConfig+0x10a>
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
- 80018de:	4b88      	ldr	r3, [pc, #544]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 80018e0:	689b      	ldr	r3, [r3, #8]
- 80018e2:	f003 030c 	and.w	r3, r3, #12
- 80018e6:	2b04      	cmp	r3, #4
- 80018e8:	d00c      	beq.n	8001904 <HAL_RCC_OscConfig+0x44>
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
- 80018ea:	4b85      	ldr	r3, [pc, #532]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 80018ec:	689b      	ldr	r3, [r3, #8]
- 80018ee:	f003 030c 	and.w	r3, r3, #12
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
- 80018f2:	2b08      	cmp	r3, #8
- 80018f4:	d112      	bne.n	800191c <HAL_RCC_OscConfig+0x5c>
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
- 80018f6:	4b82      	ldr	r3, [pc, #520]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 80018f8:	685b      	ldr	r3, [r3, #4]
- 80018fa:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
- 80018fe:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
- 8001902:	d10b      	bne.n	800191c <HAL_RCC_OscConfig+0x5c>
-    {
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 8001904:	4b7e      	ldr	r3, [pc, #504]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 8001906:	681b      	ldr	r3, [r3, #0]
- 8001908:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 800190c:	2b00      	cmp	r3, #0
- 800190e:	d05b      	beq.n	80019c8 <HAL_RCC_OscConfig+0x108>
- 8001910:	687b      	ldr	r3, [r7, #4]
- 8001912:	685b      	ldr	r3, [r3, #4]
- 8001914:	2b00      	cmp	r3, #0
- 8001916:	d157      	bne.n	80019c8 <HAL_RCC_OscConfig+0x108>
-      {
-        return HAL_ERROR;
- 8001918:	2301      	movs	r3, #1
- 800191a:	e242      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
-      }
-    }
-    else
-    {
-      /* Set the new HSE configuration ---------------------------------------*/
-      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- 800191c:	687b      	ldr	r3, [r7, #4]
- 800191e:	685b      	ldr	r3, [r3, #4]
- 8001920:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
- 8001924:	d106      	bne.n	8001934 <HAL_RCC_OscConfig+0x74>
- 8001926:	4b76      	ldr	r3, [pc, #472]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 8001928:	681b      	ldr	r3, [r3, #0]
- 800192a:	4a75      	ldr	r2, [pc, #468]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 800192c:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
- 8001930:	6013      	str	r3, [r2, #0]
- 8001932:	e01d      	b.n	8001970 <HAL_RCC_OscConfig+0xb0>
- 8001934:	687b      	ldr	r3, [r7, #4]
- 8001936:	685b      	ldr	r3, [r3, #4]
- 8001938:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
- 800193c:	d10c      	bne.n	8001958 <HAL_RCC_OscConfig+0x98>
- 800193e:	4b70      	ldr	r3, [pc, #448]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 8001940:	681b      	ldr	r3, [r3, #0]
- 8001942:	4a6f      	ldr	r2, [pc, #444]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 8001944:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
- 8001948:	6013      	str	r3, [r2, #0]
- 800194a:	4b6d      	ldr	r3, [pc, #436]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 800194c:	681b      	ldr	r3, [r3, #0]
- 800194e:	4a6c      	ldr	r2, [pc, #432]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 8001950:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
- 8001954:	6013      	str	r3, [r2, #0]
- 8001956:	e00b      	b.n	8001970 <HAL_RCC_OscConfig+0xb0>
- 8001958:	4b69      	ldr	r3, [pc, #420]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 800195a:	681b      	ldr	r3, [r3, #0]
- 800195c:	4a68      	ldr	r2, [pc, #416]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 800195e:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
- 8001962:	6013      	str	r3, [r2, #0]
- 8001964:	4b66      	ldr	r3, [pc, #408]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 8001966:	681b      	ldr	r3, [r3, #0]
- 8001968:	4a65      	ldr	r2, [pc, #404]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 800196a:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
- 800196e:	6013      	str	r3, [r2, #0]
-
-      /* Check the HSE State */
-      if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
- 8001970:	687b      	ldr	r3, [r7, #4]
- 8001972:	685b      	ldr	r3, [r3, #4]
- 8001974:	2b00      	cmp	r3, #0
- 8001976:	d013      	beq.n	80019a0 <HAL_RCC_OscConfig+0xe0>
-      {
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
- 8001978:	f7ff f8aa 	bl	8000ad0 <HAL_GetTick>
- 800197c:	6138      	str	r0, [r7, #16]
-
-        /* Wait till HSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 800197e:	e008      	b.n	8001992 <HAL_RCC_OscConfig+0xd2>
-        {
-          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 8001980:	f7ff f8a6 	bl	8000ad0 <HAL_GetTick>
- 8001984:	4602      	mov	r2, r0
- 8001986:	693b      	ldr	r3, [r7, #16]
- 8001988:	1ad3      	subs	r3, r2, r3
- 800198a:	2b64      	cmp	r3, #100	; 0x64
- 800198c:	d901      	bls.n	8001992 <HAL_RCC_OscConfig+0xd2>
-          {
-            return HAL_TIMEOUT;
- 800198e:	2303      	movs	r3, #3
- 8001990:	e207      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 8001992:	4b5b      	ldr	r3, [pc, #364]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 8001994:	681b      	ldr	r3, [r3, #0]
- 8001996:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 800199a:	2b00      	cmp	r3, #0
- 800199c:	d0f0      	beq.n	8001980 <HAL_RCC_OscConfig+0xc0>
- 800199e:	e014      	b.n	80019ca <HAL_RCC_OscConfig+0x10a>
-        }
-      }
-      else
-      {
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
- 80019a0:	f7ff f896 	bl	8000ad0 <HAL_GetTick>
- 80019a4:	6138      	str	r0, [r7, #16]
-
-        /* Wait till HSE is bypassed or disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 80019a6:	e008      	b.n	80019ba <HAL_RCC_OscConfig+0xfa>
-        {
-          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
- 80019a8:	f7ff f892 	bl	8000ad0 <HAL_GetTick>
- 80019ac:	4602      	mov	r2, r0
- 80019ae:	693b      	ldr	r3, [r7, #16]
- 80019b0:	1ad3      	subs	r3, r2, r3
- 80019b2:	2b64      	cmp	r3, #100	; 0x64
- 80019b4:	d901      	bls.n	80019ba <HAL_RCC_OscConfig+0xfa>
-          {
-            return HAL_TIMEOUT;
- 80019b6:	2303      	movs	r3, #3
- 80019b8:	e1f3      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
- 80019ba:	4b51      	ldr	r3, [pc, #324]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 80019bc:	681b      	ldr	r3, [r3, #0]
- 80019be:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 80019c2:	2b00      	cmp	r3, #0
- 80019c4:	d1f0      	bne.n	80019a8 <HAL_RCC_OscConfig+0xe8>
- 80019c6:	e000      	b.n	80019ca <HAL_RCC_OscConfig+0x10a>
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
- 80019c8:	bf00      	nop
-        }
-      }
-    }
-  }
-  /*----------------------------- HSI Configuration --------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- 80019ca:	687b      	ldr	r3, [r7, #4]
- 80019cc:	681b      	ldr	r3, [r3, #0]
- 80019ce:	f003 0302 	and.w	r3, r3, #2
- 80019d2:	2b00      	cmp	r3, #0
- 80019d4:	d063      	beq.n	8001a9e <HAL_RCC_OscConfig+0x1de>
-    /* Check the parameters */
-    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
-    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
-    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
- 80019d6:	4b4a      	ldr	r3, [pc, #296]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 80019d8:	689b      	ldr	r3, [r3, #8]
- 80019da:	f003 030c 	and.w	r3, r3, #12
- 80019de:	2b00      	cmp	r3, #0
- 80019e0:	d00b      	beq.n	80019fa <HAL_RCC_OscConfig+0x13a>
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
- 80019e2:	4b47      	ldr	r3, [pc, #284]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 80019e4:	689b      	ldr	r3, [r3, #8]
- 80019e6:	f003 030c 	and.w	r3, r3, #12
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
- 80019ea:	2b08      	cmp	r3, #8
- 80019ec:	d11c      	bne.n	8001a28 <HAL_RCC_OscConfig+0x168>
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
- 80019ee:	4b44      	ldr	r3, [pc, #272]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 80019f0:	685b      	ldr	r3, [r3, #4]
- 80019f2:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
- 80019f6:	2b00      	cmp	r3, #0
- 80019f8:	d116      	bne.n	8001a28 <HAL_RCC_OscConfig+0x168>
-    {
-      /* When HSI is used as system clock it will not disabled */
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 80019fa:	4b41      	ldr	r3, [pc, #260]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 80019fc:	681b      	ldr	r3, [r3, #0]
- 80019fe:	f003 0302 	and.w	r3, r3, #2
- 8001a02:	2b00      	cmp	r3, #0
- 8001a04:	d005      	beq.n	8001a12 <HAL_RCC_OscConfig+0x152>
- 8001a06:	687b      	ldr	r3, [r7, #4]
- 8001a08:	68db      	ldr	r3, [r3, #12]
- 8001a0a:	2b01      	cmp	r3, #1
- 8001a0c:	d001      	beq.n	8001a12 <HAL_RCC_OscConfig+0x152>
-      {
-        return HAL_ERROR;
- 8001a0e:	2301      	movs	r3, #1
- 8001a10:	e1c7      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
-      }
-      /* Otherwise, just the calibration is allowed */
-      else
-      {
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 8001a12:	4b3b      	ldr	r3, [pc, #236]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 8001a14:	681b      	ldr	r3, [r3, #0]
- 8001a16:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
- 8001a1a:	687b      	ldr	r3, [r7, #4]
- 8001a1c:	691b      	ldr	r3, [r3, #16]
- 8001a1e:	00db      	lsls	r3, r3, #3
- 8001a20:	4937      	ldr	r1, [pc, #220]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 8001a22:	4313      	orrs	r3, r2
- 8001a24:	600b      	str	r3, [r1, #0]
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
- 8001a26:	e03a      	b.n	8001a9e <HAL_RCC_OscConfig+0x1de>
-      }
-    }
-    else
-    {
-      /* Check the HSI State */
-      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
- 8001a28:	687b      	ldr	r3, [r7, #4]
- 8001a2a:	68db      	ldr	r3, [r3, #12]
- 8001a2c:	2b00      	cmp	r3, #0
- 8001a2e:	d020      	beq.n	8001a72 <HAL_RCC_OscConfig+0x1b2>
-      {
-        /* Enable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_ENABLE();
- 8001a30:	4b34      	ldr	r3, [pc, #208]	; (8001b04 <HAL_RCC_OscConfig+0x244>)
- 8001a32:	2201      	movs	r2, #1
- 8001a34:	601a      	str	r2, [r3, #0]
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 8001a36:	f7ff f84b 	bl	8000ad0 <HAL_GetTick>
- 8001a3a:	6138      	str	r0, [r7, #16]
-
-        /* Wait till HSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 8001a3c:	e008      	b.n	8001a50 <HAL_RCC_OscConfig+0x190>
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 8001a3e:	f7ff f847 	bl	8000ad0 <HAL_GetTick>
- 8001a42:	4602      	mov	r2, r0
- 8001a44:	693b      	ldr	r3, [r7, #16]
- 8001a46:	1ad3      	subs	r3, r2, r3
- 8001a48:	2b02      	cmp	r3, #2
- 8001a4a:	d901      	bls.n	8001a50 <HAL_RCC_OscConfig+0x190>
-          {
-            return HAL_TIMEOUT;
- 8001a4c:	2303      	movs	r3, #3
- 8001a4e:	e1a8      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 8001a50:	4b2b      	ldr	r3, [pc, #172]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 8001a52:	681b      	ldr	r3, [r3, #0]
- 8001a54:	f003 0302 	and.w	r3, r3, #2
- 8001a58:	2b00      	cmp	r3, #0
- 8001a5a:	d0f0      	beq.n	8001a3e <HAL_RCC_OscConfig+0x17e>
-          }
-        }
-
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 8001a5c:	4b28      	ldr	r3, [pc, #160]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 8001a5e:	681b      	ldr	r3, [r3, #0]
- 8001a60:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
- 8001a64:	687b      	ldr	r3, [r7, #4]
- 8001a66:	691b      	ldr	r3, [r3, #16]
- 8001a68:	00db      	lsls	r3, r3, #3
- 8001a6a:	4925      	ldr	r1, [pc, #148]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 8001a6c:	4313      	orrs	r3, r2
- 8001a6e:	600b      	str	r3, [r1, #0]
- 8001a70:	e015      	b.n	8001a9e <HAL_RCC_OscConfig+0x1de>
-      }
-      else
-      {
-        /* Disable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_DISABLE();
- 8001a72:	4b24      	ldr	r3, [pc, #144]	; (8001b04 <HAL_RCC_OscConfig+0x244>)
- 8001a74:	2200      	movs	r2, #0
- 8001a76:	601a      	str	r2, [r3, #0]
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 8001a78:	f7ff f82a 	bl	8000ad0 <HAL_GetTick>
- 8001a7c:	6138      	str	r0, [r7, #16]
-
-        /* Wait till HSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 8001a7e:	e008      	b.n	8001a92 <HAL_RCC_OscConfig+0x1d2>
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
- 8001a80:	f7ff f826 	bl	8000ad0 <HAL_GetTick>
- 8001a84:	4602      	mov	r2, r0
- 8001a86:	693b      	ldr	r3, [r7, #16]
- 8001a88:	1ad3      	subs	r3, r2, r3
- 8001a8a:	2b02      	cmp	r3, #2
- 8001a8c:	d901      	bls.n	8001a92 <HAL_RCC_OscConfig+0x1d2>
-          {
-            return HAL_TIMEOUT;
- 8001a8e:	2303      	movs	r3, #3
- 8001a90:	e187      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
- 8001a92:	4b1b      	ldr	r3, [pc, #108]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 8001a94:	681b      	ldr	r3, [r3, #0]
- 8001a96:	f003 0302 	and.w	r3, r3, #2
- 8001a9a:	2b00      	cmp	r3, #0
- 8001a9c:	d1f0      	bne.n	8001a80 <HAL_RCC_OscConfig+0x1c0>
-        }
-      }
-    }
-  }
-  /*------------------------------ LSI Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- 8001a9e:	687b      	ldr	r3, [r7, #4]
- 8001aa0:	681b      	ldr	r3, [r3, #0]
- 8001aa2:	f003 0308 	and.w	r3, r3, #8
- 8001aa6:	2b00      	cmp	r3, #0
- 8001aa8:	d036      	beq.n	8001b18 <HAL_RCC_OscConfig+0x258>
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
-    /* Check the LSI State */
-    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
- 8001aaa:	687b      	ldr	r3, [r7, #4]
- 8001aac:	695b      	ldr	r3, [r3, #20]
- 8001aae:	2b00      	cmp	r3, #0
- 8001ab0:	d016      	beq.n	8001ae0 <HAL_RCC_OscConfig+0x220>
-    {
-      /* Enable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_ENABLE();
- 8001ab2:	4b15      	ldr	r3, [pc, #84]	; (8001b08 <HAL_RCC_OscConfig+0x248>)
- 8001ab4:	2201      	movs	r2, #1
- 8001ab6:	601a      	str	r2, [r3, #0]
-
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
- 8001ab8:	f7ff f80a 	bl	8000ad0 <HAL_GetTick>
- 8001abc:	6138      	str	r0, [r7, #16]
-
-      /* Wait till LSI is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 8001abe:	e008      	b.n	8001ad2 <HAL_RCC_OscConfig+0x212>
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 8001ac0:	f7ff f806 	bl	8000ad0 <HAL_GetTick>
- 8001ac4:	4602      	mov	r2, r0
- 8001ac6:	693b      	ldr	r3, [r7, #16]
- 8001ac8:	1ad3      	subs	r3, r2, r3
- 8001aca:	2b02      	cmp	r3, #2
- 8001acc:	d901      	bls.n	8001ad2 <HAL_RCC_OscConfig+0x212>
-        {
-          return HAL_TIMEOUT;
- 8001ace:	2303      	movs	r3, #3
- 8001ad0:	e167      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
- 8001ad2:	4b0b      	ldr	r3, [pc, #44]	; (8001b00 <HAL_RCC_OscConfig+0x240>)
- 8001ad4:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 8001ad6:	f003 0302 	and.w	r3, r3, #2
- 8001ada:	2b00      	cmp	r3, #0
- 8001adc:	d0f0      	beq.n	8001ac0 <HAL_RCC_OscConfig+0x200>
- 8001ade:	e01b      	b.n	8001b18 <HAL_RCC_OscConfig+0x258>
-      }
-    }
-    else
-    {
-      /* Disable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_DISABLE();
- 8001ae0:	4b09      	ldr	r3, [pc, #36]	; (8001b08 <HAL_RCC_OscConfig+0x248>)
- 8001ae2:	2200      	movs	r2, #0
- 8001ae4:	601a      	str	r2, [r3, #0]
-
-      /* Get Start Tick */
-      tickstart = HAL_GetTick();
- 8001ae6:	f7fe fff3 	bl	8000ad0 <HAL_GetTick>
- 8001aea:	6138      	str	r0, [r7, #16]
-
-      /* Wait till LSI is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 8001aec:	e00e      	b.n	8001b0c <HAL_RCC_OscConfig+0x24c>
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
- 8001aee:	f7fe ffef 	bl	8000ad0 <HAL_GetTick>
- 8001af2:	4602      	mov	r2, r0
- 8001af4:	693b      	ldr	r3, [r7, #16]
- 8001af6:	1ad3      	subs	r3, r2, r3
- 8001af8:	2b02      	cmp	r3, #2
- 8001afa:	d907      	bls.n	8001b0c <HAL_RCC_OscConfig+0x24c>
-        {
-          return HAL_TIMEOUT;
- 8001afc:	2303      	movs	r3, #3
- 8001afe:	e150      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
- 8001b00:	40023800 	.word	0x40023800
- 8001b04:	42470000 	.word	0x42470000
- 8001b08:	42470e80 	.word	0x42470e80
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
- 8001b0c:	4b88      	ldr	r3, [pc, #544]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001b0e:	6f5b      	ldr	r3, [r3, #116]	; 0x74
- 8001b10:	f003 0302 	and.w	r3, r3, #2
- 8001b14:	2b00      	cmp	r3, #0
- 8001b16:	d1ea      	bne.n	8001aee <HAL_RCC_OscConfig+0x22e>
-        }
-      }
-    }
-  }
-  /*------------------------------ LSE Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- 8001b18:	687b      	ldr	r3, [r7, #4]
- 8001b1a:	681b      	ldr	r3, [r3, #0]
- 8001b1c:	f003 0304 	and.w	r3, r3, #4
- 8001b20:	2b00      	cmp	r3, #0
- 8001b22:	f000 8097 	beq.w	8001c54 <HAL_RCC_OscConfig+0x394>
-  {
-    FlagStatus       pwrclkchanged = RESET;
- 8001b26:	2300      	movs	r3, #0
- 8001b28:	75fb      	strb	r3, [r7, #23]
-    /* Check the parameters */
-    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
-    /* Update LSE configuration in Backup Domain control register    */
-    /* Requires to enable write access to Backup Domain of necessary */
-    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
- 8001b2a:	4b81      	ldr	r3, [pc, #516]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001b2c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 8001b2e:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
- 8001b32:	2b00      	cmp	r3, #0
- 8001b34:	d10f      	bne.n	8001b56 <HAL_RCC_OscConfig+0x296>
-    {
-      __HAL_RCC_PWR_CLK_ENABLE();
- 8001b36:	2300      	movs	r3, #0
- 8001b38:	60bb      	str	r3, [r7, #8]
- 8001b3a:	4b7d      	ldr	r3, [pc, #500]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001b3c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 8001b3e:	4a7c      	ldr	r2, [pc, #496]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001b40:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
- 8001b44:	6413      	str	r3, [r2, #64]	; 0x40
- 8001b46:	4b7a      	ldr	r3, [pc, #488]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001b48:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 8001b4a:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
- 8001b4e:	60bb      	str	r3, [r7, #8]
- 8001b50:	68bb      	ldr	r3, [r7, #8]
-      pwrclkchanged = SET;
- 8001b52:	2301      	movs	r3, #1
- 8001b54:	75fb      	strb	r3, [r7, #23]
-    }
-
-    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8001b56:	4b77      	ldr	r3, [pc, #476]	; (8001d34 <HAL_RCC_OscConfig+0x474>)
- 8001b58:	681b      	ldr	r3, [r3, #0]
- 8001b5a:	f403 7380 	and.w	r3, r3, #256	; 0x100
- 8001b5e:	2b00      	cmp	r3, #0
- 8001b60:	d118      	bne.n	8001b94 <HAL_RCC_OscConfig+0x2d4>
-    {
-      /* Enable write access to Backup domain */
-      SET_BIT(PWR->CR, PWR_CR_DBP);
- 8001b62:	4b74      	ldr	r3, [pc, #464]	; (8001d34 <HAL_RCC_OscConfig+0x474>)
- 8001b64:	681b      	ldr	r3, [r3, #0]
- 8001b66:	4a73      	ldr	r2, [pc, #460]	; (8001d34 <HAL_RCC_OscConfig+0x474>)
- 8001b68:	f443 7380 	orr.w	r3, r3, #256	; 0x100
- 8001b6c:	6013      	str	r3, [r2, #0]
-
-      /* Wait for Backup domain Write protection disable */
-      tickstart = HAL_GetTick();
- 8001b6e:	f7fe ffaf 	bl	8000ad0 <HAL_GetTick>
- 8001b72:	6138      	str	r0, [r7, #16]
-
-      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8001b74:	e008      	b.n	8001b88 <HAL_RCC_OscConfig+0x2c8>
-      {
-        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
- 8001b76:	f7fe ffab 	bl	8000ad0 <HAL_GetTick>
- 8001b7a:	4602      	mov	r2, r0
- 8001b7c:	693b      	ldr	r3, [r7, #16]
- 8001b7e:	1ad3      	subs	r3, r2, r3
- 8001b80:	2b02      	cmp	r3, #2
- 8001b82:	d901      	bls.n	8001b88 <HAL_RCC_OscConfig+0x2c8>
-        {
-          return HAL_TIMEOUT;
- 8001b84:	2303      	movs	r3, #3
- 8001b86:	e10c      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
-      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
- 8001b88:	4b6a      	ldr	r3, [pc, #424]	; (8001d34 <HAL_RCC_OscConfig+0x474>)
- 8001b8a:	681b      	ldr	r3, [r3, #0]
- 8001b8c:	f403 7380 	and.w	r3, r3, #256	; 0x100
- 8001b90:	2b00      	cmp	r3, #0
- 8001b92:	d0f0      	beq.n	8001b76 <HAL_RCC_OscConfig+0x2b6>
-        }
-      }
-    }
-
-    /* Set the new LSE configuration -----------------------------------------*/
-    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- 8001b94:	687b      	ldr	r3, [r7, #4]
- 8001b96:	689b      	ldr	r3, [r3, #8]
- 8001b98:	2b01      	cmp	r3, #1
- 8001b9a:	d106      	bne.n	8001baa <HAL_RCC_OscConfig+0x2ea>
- 8001b9c:	4b64      	ldr	r3, [pc, #400]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001b9e:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8001ba0:	4a63      	ldr	r2, [pc, #396]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001ba2:	f043 0301 	orr.w	r3, r3, #1
- 8001ba6:	6713      	str	r3, [r2, #112]	; 0x70
- 8001ba8:	e01c      	b.n	8001be4 <HAL_RCC_OscConfig+0x324>
- 8001baa:	687b      	ldr	r3, [r7, #4]
- 8001bac:	689b      	ldr	r3, [r3, #8]
- 8001bae:	2b05      	cmp	r3, #5
- 8001bb0:	d10c      	bne.n	8001bcc <HAL_RCC_OscConfig+0x30c>
- 8001bb2:	4b5f      	ldr	r3, [pc, #380]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001bb4:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8001bb6:	4a5e      	ldr	r2, [pc, #376]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001bb8:	f043 0304 	orr.w	r3, r3, #4
- 8001bbc:	6713      	str	r3, [r2, #112]	; 0x70
- 8001bbe:	4b5c      	ldr	r3, [pc, #368]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001bc0:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8001bc2:	4a5b      	ldr	r2, [pc, #364]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001bc4:	f043 0301 	orr.w	r3, r3, #1
- 8001bc8:	6713      	str	r3, [r2, #112]	; 0x70
- 8001bca:	e00b      	b.n	8001be4 <HAL_RCC_OscConfig+0x324>
- 8001bcc:	4b58      	ldr	r3, [pc, #352]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001bce:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8001bd0:	4a57      	ldr	r2, [pc, #348]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001bd2:	f023 0301 	bic.w	r3, r3, #1
- 8001bd6:	6713      	str	r3, [r2, #112]	; 0x70
- 8001bd8:	4b55      	ldr	r3, [pc, #340]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001bda:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8001bdc:	4a54      	ldr	r2, [pc, #336]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001bde:	f023 0304 	bic.w	r3, r3, #4
- 8001be2:	6713      	str	r3, [r2, #112]	; 0x70
-    /* Check the LSE State */
-    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
- 8001be4:	687b      	ldr	r3, [r7, #4]
- 8001be6:	689b      	ldr	r3, [r3, #8]
- 8001be8:	2b00      	cmp	r3, #0
- 8001bea:	d015      	beq.n	8001c18 <HAL_RCC_OscConfig+0x358>
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
- 8001bec:	f7fe ff70 	bl	8000ad0 <HAL_GetTick>
- 8001bf0:	6138      	str	r0, [r7, #16]
-
-      /* Wait till LSE is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8001bf2:	e00a      	b.n	8001c0a <HAL_RCC_OscConfig+0x34a>
-      {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8001bf4:	f7fe ff6c 	bl	8000ad0 <HAL_GetTick>
- 8001bf8:	4602      	mov	r2, r0
- 8001bfa:	693b      	ldr	r3, [r7, #16]
- 8001bfc:	1ad3      	subs	r3, r2, r3
- 8001bfe:	f241 3288 	movw	r2, #5000	; 0x1388
- 8001c02:	4293      	cmp	r3, r2
- 8001c04:	d901      	bls.n	8001c0a <HAL_RCC_OscConfig+0x34a>
-        {
-          return HAL_TIMEOUT;
- 8001c06:	2303      	movs	r3, #3
- 8001c08:	e0cb      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
- 8001c0a:	4b49      	ldr	r3, [pc, #292]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001c0c:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8001c0e:	f003 0302 	and.w	r3, r3, #2
- 8001c12:	2b00      	cmp	r3, #0
- 8001c14:	d0ee      	beq.n	8001bf4 <HAL_RCC_OscConfig+0x334>
- 8001c16:	e014      	b.n	8001c42 <HAL_RCC_OscConfig+0x382>
-      }
-    }
-    else
-    {
-      /* Get Start Tick */
-      tickstart = HAL_GetTick();
- 8001c18:	f7fe ff5a 	bl	8000ad0 <HAL_GetTick>
- 8001c1c:	6138      	str	r0, [r7, #16]
-
-      /* Wait till LSE is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 8001c1e:	e00a      	b.n	8001c36 <HAL_RCC_OscConfig+0x376>
-      {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
- 8001c20:	f7fe ff56 	bl	8000ad0 <HAL_GetTick>
- 8001c24:	4602      	mov	r2, r0
- 8001c26:	693b      	ldr	r3, [r7, #16]
- 8001c28:	1ad3      	subs	r3, r2, r3
- 8001c2a:	f241 3288 	movw	r2, #5000	; 0x1388
- 8001c2e:	4293      	cmp	r3, r2
- 8001c30:	d901      	bls.n	8001c36 <HAL_RCC_OscConfig+0x376>
-        {
-          return HAL_TIMEOUT;
- 8001c32:	2303      	movs	r3, #3
- 8001c34:	e0b5      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
- 8001c36:	4b3e      	ldr	r3, [pc, #248]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001c38:	6f1b      	ldr	r3, [r3, #112]	; 0x70
- 8001c3a:	f003 0302 	and.w	r3, r3, #2
- 8001c3e:	2b00      	cmp	r3, #0
- 8001c40:	d1ee      	bne.n	8001c20 <HAL_RCC_OscConfig+0x360>
-        }
-      }
-    }
-
-    /* Restore clock configuration if changed */
-    if(pwrclkchanged == SET)
- 8001c42:	7dfb      	ldrb	r3, [r7, #23]
- 8001c44:	2b01      	cmp	r3, #1
- 8001c46:	d105      	bne.n	8001c54 <HAL_RCC_OscConfig+0x394>
-    {
-      __HAL_RCC_PWR_CLK_DISABLE();
- 8001c48:	4b39      	ldr	r3, [pc, #228]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001c4a:	6c1b      	ldr	r3, [r3, #64]	; 0x40
- 8001c4c:	4a38      	ldr	r2, [pc, #224]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001c4e:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
- 8001c52:	6413      	str	r3, [r2, #64]	; 0x40
-    }
-  }
-  /*-------------------------------- PLL Configuration -----------------------*/
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
-  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
- 8001c54:	687b      	ldr	r3, [r7, #4]
- 8001c56:	699b      	ldr	r3, [r3, #24]
- 8001c58:	2b00      	cmp	r3, #0
- 8001c5a:	f000 80a1 	beq.w	8001da0 <HAL_RCC_OscConfig+0x4e0>
-  {
-    /* Check if the PLL is used as system clock or not */
-    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
- 8001c5e:	4b34      	ldr	r3, [pc, #208]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001c60:	689b      	ldr	r3, [r3, #8]
- 8001c62:	f003 030c 	and.w	r3, r3, #12
- 8001c66:	2b08      	cmp	r3, #8
- 8001c68:	d05c      	beq.n	8001d24 <HAL_RCC_OscConfig+0x464>
-    {
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
- 8001c6a:	687b      	ldr	r3, [r7, #4]
- 8001c6c:	699b      	ldr	r3, [r3, #24]
- 8001c6e:	2b02      	cmp	r3, #2
- 8001c70:	d141      	bne.n	8001cf6 <HAL_RCC_OscConfig+0x436>
-        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
-        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
-        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
-
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
- 8001c72:	4b31      	ldr	r3, [pc, #196]	; (8001d38 <HAL_RCC_OscConfig+0x478>)
- 8001c74:	2200      	movs	r2, #0
- 8001c76:	601a      	str	r2, [r3, #0]
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
- 8001c78:	f7fe ff2a 	bl	8000ad0 <HAL_GetTick>
- 8001c7c:	6138      	str	r0, [r7, #16]
-
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8001c7e:	e008      	b.n	8001c92 <HAL_RCC_OscConfig+0x3d2>
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8001c80:	f7fe ff26 	bl	8000ad0 <HAL_GetTick>
- 8001c84:	4602      	mov	r2, r0
- 8001c86:	693b      	ldr	r3, [r7, #16]
- 8001c88:	1ad3      	subs	r3, r2, r3
- 8001c8a:	2b02      	cmp	r3, #2
- 8001c8c:	d901      	bls.n	8001c92 <HAL_RCC_OscConfig+0x3d2>
-          {
-            return HAL_TIMEOUT;
- 8001c8e:	2303      	movs	r3, #3
- 8001c90:	e087      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8001c92:	4b27      	ldr	r3, [pc, #156]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001c94:	681b      	ldr	r3, [r3, #0]
- 8001c96:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
- 8001c9a:	2b00      	cmp	r3, #0
- 8001c9c:	d1f0      	bne.n	8001c80 <HAL_RCC_OscConfig+0x3c0>
-          }
-        }
-
-        /* Configure the main PLL clock source, multiplication and division factors. */
-        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \
- 8001c9e:	687b      	ldr	r3, [r7, #4]
- 8001ca0:	69da      	ldr	r2, [r3, #28]
- 8001ca2:	687b      	ldr	r3, [r7, #4]
- 8001ca4:	6a1b      	ldr	r3, [r3, #32]
- 8001ca6:	431a      	orrs	r2, r3
- 8001ca8:	687b      	ldr	r3, [r7, #4]
- 8001caa:	6a5b      	ldr	r3, [r3, #36]	; 0x24
- 8001cac:	019b      	lsls	r3, r3, #6
- 8001cae:	431a      	orrs	r2, r3
- 8001cb0:	687b      	ldr	r3, [r7, #4]
- 8001cb2:	6a9b      	ldr	r3, [r3, #40]	; 0x28
- 8001cb4:	085b      	lsrs	r3, r3, #1
- 8001cb6:	3b01      	subs	r3, #1
- 8001cb8:	041b      	lsls	r3, r3, #16
- 8001cba:	431a      	orrs	r2, r3
- 8001cbc:	687b      	ldr	r3, [r7, #4]
- 8001cbe:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8001cc0:	061b      	lsls	r3, r3, #24
- 8001cc2:	491b      	ldr	r1, [pc, #108]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001cc4:	4313      	orrs	r3, r2
- 8001cc6:	604b      	str	r3, [r1, #4]
-                                 RCC_OscInitStruct->PLL.PLLM                                                 | \
-                                 (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)             | \
-                                 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
-                                 (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
-        /* Enable the main PLL. */
-        __HAL_RCC_PLL_ENABLE();
- 8001cc8:	4b1b      	ldr	r3, [pc, #108]	; (8001d38 <HAL_RCC_OscConfig+0x478>)
- 8001cca:	2201      	movs	r2, #1
- 8001ccc:	601a      	str	r2, [r3, #0]
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
- 8001cce:	f7fe feff 	bl	8000ad0 <HAL_GetTick>
- 8001cd2:	6138      	str	r0, [r7, #16]
-
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 8001cd4:	e008      	b.n	8001ce8 <HAL_RCC_OscConfig+0x428>
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8001cd6:	f7fe fefb 	bl	8000ad0 <HAL_GetTick>
- 8001cda:	4602      	mov	r2, r0
- 8001cdc:	693b      	ldr	r3, [r7, #16]
- 8001cde:	1ad3      	subs	r3, r2, r3
- 8001ce0:	2b02      	cmp	r3, #2
- 8001ce2:	d901      	bls.n	8001ce8 <HAL_RCC_OscConfig+0x428>
-          {
-            return HAL_TIMEOUT;
- 8001ce4:	2303      	movs	r3, #3
- 8001ce6:	e05c      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 8001ce8:	4b11      	ldr	r3, [pc, #68]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001cea:	681b      	ldr	r3, [r3, #0]
- 8001cec:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
- 8001cf0:	2b00      	cmp	r3, #0
- 8001cf2:	d0f0      	beq.n	8001cd6 <HAL_RCC_OscConfig+0x416>
- 8001cf4:	e054      	b.n	8001da0 <HAL_RCC_OscConfig+0x4e0>
-        }
-      }
-      else
-      {
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
- 8001cf6:	4b10      	ldr	r3, [pc, #64]	; (8001d38 <HAL_RCC_OscConfig+0x478>)
- 8001cf8:	2200      	movs	r2, #0
- 8001cfa:	601a      	str	r2, [r3, #0]
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
- 8001cfc:	f7fe fee8 	bl	8000ad0 <HAL_GetTick>
- 8001d00:	6138      	str	r0, [r7, #16]
-
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8001d02:	e008      	b.n	8001d16 <HAL_RCC_OscConfig+0x456>
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
- 8001d04:	f7fe fee4 	bl	8000ad0 <HAL_GetTick>
- 8001d08:	4602      	mov	r2, r0
- 8001d0a:	693b      	ldr	r3, [r7, #16]
- 8001d0c:	1ad3      	subs	r3, r2, r3
- 8001d0e:	2b02      	cmp	r3, #2
- 8001d10:	d901      	bls.n	8001d16 <HAL_RCC_OscConfig+0x456>
-          {
-            return HAL_TIMEOUT;
- 8001d12:	2303      	movs	r3, #3
- 8001d14:	e045      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
- 8001d16:	4b06      	ldr	r3, [pc, #24]	; (8001d30 <HAL_RCC_OscConfig+0x470>)
- 8001d18:	681b      	ldr	r3, [r3, #0]
- 8001d1a:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
- 8001d1e:	2b00      	cmp	r3, #0
- 8001d20:	d1f0      	bne.n	8001d04 <HAL_RCC_OscConfig+0x444>
- 8001d22:	e03d      	b.n	8001da0 <HAL_RCC_OscConfig+0x4e0>
-      }
-    }
-    else
-    {
-      /* Check if there is a request to disable the PLL used as System clock source */
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
- 8001d24:	687b      	ldr	r3, [r7, #4]
- 8001d26:	699b      	ldr	r3, [r3, #24]
- 8001d28:	2b01      	cmp	r3, #1
- 8001d2a:	d107      	bne.n	8001d3c <HAL_RCC_OscConfig+0x47c>
-      {
-        return HAL_ERROR;
- 8001d2c:	2301      	movs	r3, #1
- 8001d2e:	e038      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
- 8001d30:	40023800 	.word	0x40023800
- 8001d34:	40007000 	.word	0x40007000
- 8001d38:	42470060 	.word	0x42470060
-      }
-      else
-      {
-        /* Do not return HAL_ERROR if request repeats the current configuration */
-        pll_config = RCC->PLLCFGR;
- 8001d3c:	4b1b      	ldr	r3, [pc, #108]	; (8001dac <HAL_RCC_OscConfig+0x4ec>)
- 8001d3e:	685b      	ldr	r3, [r3, #4]
- 8001d40:	60fb      	str	r3, [r7, #12]
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
-#else
-        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
- 8001d42:	687b      	ldr	r3, [r7, #4]
- 8001d44:	699b      	ldr	r3, [r3, #24]
- 8001d46:	2b01      	cmp	r3, #1
- 8001d48:	d028      	beq.n	8001d9c <HAL_RCC_OscConfig+0x4dc>
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
- 8001d4a:	68fb      	ldr	r3, [r7, #12]
- 8001d4c:	f403 0280 	and.w	r2, r3, #4194304	; 0x400000
- 8001d50:	687b      	ldr	r3, [r7, #4]
- 8001d52:	69db      	ldr	r3, [r3, #28]
-        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
- 8001d54:	429a      	cmp	r2, r3
- 8001d56:	d121      	bne.n	8001d9c <HAL_RCC_OscConfig+0x4dc>
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
- 8001d58:	68fb      	ldr	r3, [r7, #12]
- 8001d5a:	f003 023f 	and.w	r2, r3, #63	; 0x3f
- 8001d5e:	687b      	ldr	r3, [r7, #4]
- 8001d60:	6a1b      	ldr	r3, [r3, #32]
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
- 8001d62:	429a      	cmp	r2, r3
- 8001d64:	d11a      	bne.n	8001d9c <HAL_RCC_OscConfig+0x4dc>
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
- 8001d66:	68fa      	ldr	r2, [r7, #12]
- 8001d68:	f647 73c0 	movw	r3, #32704	; 0x7fc0
- 8001d6c:	4013      	ands	r3, r2
- 8001d6e:	687a      	ldr	r2, [r7, #4]
- 8001d70:	6a52      	ldr	r2, [r2, #36]	; 0x24
- 8001d72:	0192      	lsls	r2, r2, #6
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
- 8001d74:	4293      	cmp	r3, r2
- 8001d76:	d111      	bne.n	8001d9c <HAL_RCC_OscConfig+0x4dc>
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
- 8001d78:	68fb      	ldr	r3, [r7, #12]
- 8001d7a:	f403 3240 	and.w	r2, r3, #196608	; 0x30000
- 8001d7e:	687b      	ldr	r3, [r7, #4]
- 8001d80:	6a9b      	ldr	r3, [r3, #40]	; 0x28
- 8001d82:	085b      	lsrs	r3, r3, #1
- 8001d84:	3b01      	subs	r3, #1
- 8001d86:	041b      	lsls	r3, r3, #16
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
- 8001d88:	429a      	cmp	r2, r3
- 8001d8a:	d107      	bne.n	8001d9c <HAL_RCC_OscConfig+0x4dc>
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
- 8001d8c:	68fb      	ldr	r3, [r7, #12]
- 8001d8e:	f003 6270 	and.w	r2, r3, #251658240	; 0xf000000
- 8001d92:	687b      	ldr	r3, [r7, #4]
- 8001d94:	6adb      	ldr	r3, [r3, #44]	; 0x2c
- 8001d96:	061b      	lsls	r3, r3, #24
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
- 8001d98:	429a      	cmp	r2, r3
- 8001d9a:	d001      	beq.n	8001da0 <HAL_RCC_OscConfig+0x4e0>
-#endif
-        {
-          return HAL_ERROR;
- 8001d9c:	2301      	movs	r3, #1
- 8001d9e:	e000      	b.n	8001da2 <HAL_RCC_OscConfig+0x4e2>
-        }
-      }
-    }
-  }
-  return HAL_OK;
- 8001da0:	2300      	movs	r3, #0
-}
- 8001da2:	4618      	mov	r0, r3
- 8001da4:	3718      	adds	r7, #24
- 8001da6:	46bd      	mov	sp, r7
- 8001da8:	bd80      	pop	{r7, pc}
- 8001daa:	bf00      	nop
- 8001dac:	40023800 	.word	0x40023800
-
-08001db0 <HAL_RCC_ClockConfig>:
-  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
-  *         (for more details refer to section above "Initialization/de-initialization functions")
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
-{
- 8001db0:	b580      	push	{r7, lr}
- 8001db2:	b084      	sub	sp, #16
- 8001db4:	af00      	add	r7, sp, #0
- 8001db6:	6078      	str	r0, [r7, #4]
- 8001db8:	6039      	str	r1, [r7, #0]
-  uint32_t tickstart;
-
-  /* Check Null pointer */
-  if(RCC_ClkInitStruct == NULL)
- 8001dba:	687b      	ldr	r3, [r7, #4]
- 8001dbc:	2b00      	cmp	r3, #0
- 8001dbe:	d101      	bne.n	8001dc4 <HAL_RCC_ClockConfig+0x14>
-  {
-    return HAL_ERROR;
- 8001dc0:	2301      	movs	r3, #1
- 8001dc2:	e0cc      	b.n	8001f5e <HAL_RCC_ClockConfig+0x1ae>
-  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
-    must be correctly programmed according to the frequency of the CPU clock
-    (HCLK) and the supply voltage of the device. */
-
-  /* Increasing the number of wait states because of higher CPU frequency */
-  if(FLatency > __HAL_FLASH_GET_LATENCY())
- 8001dc4:	4b68      	ldr	r3, [pc, #416]	; (8001f68 <HAL_RCC_ClockConfig+0x1b8>)
- 8001dc6:	681b      	ldr	r3, [r3, #0]
- 8001dc8:	f003 0307 	and.w	r3, r3, #7
- 8001dcc:	683a      	ldr	r2, [r7, #0]
- 8001dce:	429a      	cmp	r2, r3
- 8001dd0:	d90c      	bls.n	8001dec <HAL_RCC_ClockConfig+0x3c>
-  {
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
- 8001dd2:	4b65      	ldr	r3, [pc, #404]	; (8001f68 <HAL_RCC_ClockConfig+0x1b8>)
- 8001dd4:	683a      	ldr	r2, [r7, #0]
- 8001dd6:	b2d2      	uxtb	r2, r2
- 8001dd8:	701a      	strb	r2, [r3, #0]
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 8001dda:	4b63      	ldr	r3, [pc, #396]	; (8001f68 <HAL_RCC_ClockConfig+0x1b8>)
- 8001ddc:	681b      	ldr	r3, [r3, #0]
- 8001dde:	f003 0307 	and.w	r3, r3, #7
- 8001de2:	683a      	ldr	r2, [r7, #0]
- 8001de4:	429a      	cmp	r2, r3
- 8001de6:	d001      	beq.n	8001dec <HAL_RCC_ClockConfig+0x3c>
-    {
-      return HAL_ERROR;
- 8001de8:	2301      	movs	r3, #1
- 8001dea:	e0b8      	b.n	8001f5e <HAL_RCC_ClockConfig+0x1ae>
-    }
-  }
-
-  /*-------------------------- HCLK Configuration --------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 8001dec:	687b      	ldr	r3, [r7, #4]
- 8001dee:	681b      	ldr	r3, [r3, #0]
- 8001df0:	f003 0302 	and.w	r3, r3, #2
- 8001df4:	2b00      	cmp	r3, #0
- 8001df6:	d020      	beq.n	8001e3a <HAL_RCC_ClockConfig+0x8a>
-  {
-    /* Set the highest APBx dividers in order to ensure that we do not go through
-       a non-spec phase whatever we decrease or increase HCLK. */
-    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8001df8:	687b      	ldr	r3, [r7, #4]
- 8001dfa:	681b      	ldr	r3, [r3, #0]
- 8001dfc:	f003 0304 	and.w	r3, r3, #4
- 8001e00:	2b00      	cmp	r3, #0
- 8001e02:	d005      	beq.n	8001e10 <HAL_RCC_ClockConfig+0x60>
-    {
-      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
- 8001e04:	4b59      	ldr	r3, [pc, #356]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001e06:	689b      	ldr	r3, [r3, #8]
- 8001e08:	4a58      	ldr	r2, [pc, #352]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001e0a:	f443 53e0 	orr.w	r3, r3, #7168	; 0x1c00
- 8001e0e:	6093      	str	r3, [r2, #8]
-    }
-
-    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8001e10:	687b      	ldr	r3, [r7, #4]
- 8001e12:	681b      	ldr	r3, [r3, #0]
- 8001e14:	f003 0308 	and.w	r3, r3, #8
- 8001e18:	2b00      	cmp	r3, #0
- 8001e1a:	d005      	beq.n	8001e28 <HAL_RCC_ClockConfig+0x78>
-    {
-      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
- 8001e1c:	4b53      	ldr	r3, [pc, #332]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001e1e:	689b      	ldr	r3, [r3, #8]
- 8001e20:	4a52      	ldr	r2, [pc, #328]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001e22:	f443 4360 	orr.w	r3, r3, #57344	; 0xe000
- 8001e26:	6093      	str	r3, [r2, #8]
-    }
-
-    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 8001e28:	4b50      	ldr	r3, [pc, #320]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001e2a:	689b      	ldr	r3, [r3, #8]
- 8001e2c:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
- 8001e30:	687b      	ldr	r3, [r7, #4]
- 8001e32:	689b      	ldr	r3, [r3, #8]
- 8001e34:	494d      	ldr	r1, [pc, #308]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001e36:	4313      	orrs	r3, r2
- 8001e38:	608b      	str	r3, [r1, #8]
-  }
-
-  /*------------------------- SYSCLK Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- 8001e3a:	687b      	ldr	r3, [r7, #4]
- 8001e3c:	681b      	ldr	r3, [r3, #0]
- 8001e3e:	f003 0301 	and.w	r3, r3, #1
- 8001e42:	2b00      	cmp	r3, #0
- 8001e44:	d044      	beq.n	8001ed0 <HAL_RCC_ClockConfig+0x120>
-  {
-    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
-    /* HSE is selected as System Clock Source */
-    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 8001e46:	687b      	ldr	r3, [r7, #4]
- 8001e48:	685b      	ldr	r3, [r3, #4]
- 8001e4a:	2b01      	cmp	r3, #1
- 8001e4c:	d107      	bne.n	8001e5e <HAL_RCC_ClockConfig+0xae>
-    {
-      /* Check the HSE ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
- 8001e4e:	4b47      	ldr	r3, [pc, #284]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001e50:	681b      	ldr	r3, [r3, #0]
- 8001e52:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
- 8001e56:	2b00      	cmp	r3, #0
- 8001e58:	d119      	bne.n	8001e8e <HAL_RCC_ClockConfig+0xde>
-      {
-        return HAL_ERROR;
- 8001e5a:	2301      	movs	r3, #1
- 8001e5c:	e07f      	b.n	8001f5e <HAL_RCC_ClockConfig+0x1ae>
-      }
-    }
-    /* PLL is selected as System Clock Source */
-    else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
- 8001e5e:	687b      	ldr	r3, [r7, #4]
- 8001e60:	685b      	ldr	r3, [r3, #4]
- 8001e62:	2b02      	cmp	r3, #2
- 8001e64:	d003      	beq.n	8001e6e <HAL_RCC_ClockConfig+0xbe>
-            (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
- 8001e66:	687b      	ldr	r3, [r7, #4]
- 8001e68:	685b      	ldr	r3, [r3, #4]
-    else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
- 8001e6a:	2b03      	cmp	r3, #3
- 8001e6c:	d107      	bne.n	8001e7e <HAL_RCC_ClockConfig+0xce>
-    {
-      /* Check the PLL ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
- 8001e6e:	4b3f      	ldr	r3, [pc, #252]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001e70:	681b      	ldr	r3, [r3, #0]
- 8001e72:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
- 8001e76:	2b00      	cmp	r3, #0
- 8001e78:	d109      	bne.n	8001e8e <HAL_RCC_ClockConfig+0xde>
-      {
-        return HAL_ERROR;
- 8001e7a:	2301      	movs	r3, #1
- 8001e7c:	e06f      	b.n	8001f5e <HAL_RCC_ClockConfig+0x1ae>
-    }
-    /* HSI is selected as System Clock Source */
-    else
-    {
-      /* Check the HSI ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
- 8001e7e:	4b3b      	ldr	r3, [pc, #236]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001e80:	681b      	ldr	r3, [r3, #0]
- 8001e82:	f003 0302 	and.w	r3, r3, #2
- 8001e86:	2b00      	cmp	r3, #0
- 8001e88:	d101      	bne.n	8001e8e <HAL_RCC_ClockConfig+0xde>
-      {
-        return HAL_ERROR;
- 8001e8a:	2301      	movs	r3, #1
- 8001e8c:	e067      	b.n	8001f5e <HAL_RCC_ClockConfig+0x1ae>
-      }
-    }
-
-    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- 8001e8e:	4b37      	ldr	r3, [pc, #220]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001e90:	689b      	ldr	r3, [r3, #8]
- 8001e92:	f023 0203 	bic.w	r2, r3, #3
- 8001e96:	687b      	ldr	r3, [r7, #4]
- 8001e98:	685b      	ldr	r3, [r3, #4]
- 8001e9a:	4934      	ldr	r1, [pc, #208]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001e9c:	4313      	orrs	r3, r2
- 8001e9e:	608b      	str	r3, [r1, #8]
-
-    /* Get Start Tick */
-    tickstart = HAL_GetTick();
- 8001ea0:	f7fe fe16 	bl	8000ad0 <HAL_GetTick>
- 8001ea4:	60f8      	str	r0, [r7, #12]
-
-    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 8001ea6:	e00a      	b.n	8001ebe <HAL_RCC_ClockConfig+0x10e>
-    {
-      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
- 8001ea8:	f7fe fe12 	bl	8000ad0 <HAL_GetTick>
- 8001eac:	4602      	mov	r2, r0
- 8001eae:	68fb      	ldr	r3, [r7, #12]
- 8001eb0:	1ad3      	subs	r3, r2, r3
- 8001eb2:	f241 3288 	movw	r2, #5000	; 0x1388
- 8001eb6:	4293      	cmp	r3, r2
- 8001eb8:	d901      	bls.n	8001ebe <HAL_RCC_ClockConfig+0x10e>
-      {
-        return HAL_TIMEOUT;
- 8001eba:	2303      	movs	r3, #3
- 8001ebc:	e04f      	b.n	8001f5e <HAL_RCC_ClockConfig+0x1ae>
-    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 8001ebe:	4b2b      	ldr	r3, [pc, #172]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001ec0:	689b      	ldr	r3, [r3, #8]
- 8001ec2:	f003 020c 	and.w	r2, r3, #12
- 8001ec6:	687b      	ldr	r3, [r7, #4]
- 8001ec8:	685b      	ldr	r3, [r3, #4]
- 8001eca:	009b      	lsls	r3, r3, #2
- 8001ecc:	429a      	cmp	r2, r3
- 8001ece:	d1eb      	bne.n	8001ea8 <HAL_RCC_ClockConfig+0xf8>
-      }
-    }
-  }
-
-  /* Decreasing the number of wait states because of lower CPU frequency */
-  if(FLatency < __HAL_FLASH_GET_LATENCY())
- 8001ed0:	4b25      	ldr	r3, [pc, #148]	; (8001f68 <HAL_RCC_ClockConfig+0x1b8>)
- 8001ed2:	681b      	ldr	r3, [r3, #0]
- 8001ed4:	f003 0307 	and.w	r3, r3, #7
- 8001ed8:	683a      	ldr	r2, [r7, #0]
- 8001eda:	429a      	cmp	r2, r3
- 8001edc:	d20c      	bcs.n	8001ef8 <HAL_RCC_ClockConfig+0x148>
-  {
-     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
- 8001ede:	4b22      	ldr	r3, [pc, #136]	; (8001f68 <HAL_RCC_ClockConfig+0x1b8>)
- 8001ee0:	683a      	ldr	r2, [r7, #0]
- 8001ee2:	b2d2      	uxtb	r2, r2
- 8001ee4:	701a      	strb	r2, [r3, #0]
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if(__HAL_FLASH_GET_LATENCY() != FLatency)
- 8001ee6:	4b20      	ldr	r3, [pc, #128]	; (8001f68 <HAL_RCC_ClockConfig+0x1b8>)
- 8001ee8:	681b      	ldr	r3, [r3, #0]
- 8001eea:	f003 0307 	and.w	r3, r3, #7
- 8001eee:	683a      	ldr	r2, [r7, #0]
- 8001ef0:	429a      	cmp	r2, r3
- 8001ef2:	d001      	beq.n	8001ef8 <HAL_RCC_ClockConfig+0x148>
-    {
-      return HAL_ERROR;
- 8001ef4:	2301      	movs	r3, #1
- 8001ef6:	e032      	b.n	8001f5e <HAL_RCC_ClockConfig+0x1ae>
-    }
-  }
-
-  /*-------------------------- PCLK1 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8001ef8:	687b      	ldr	r3, [r7, #4]
- 8001efa:	681b      	ldr	r3, [r3, #0]
- 8001efc:	f003 0304 	and.w	r3, r3, #4
- 8001f00:	2b00      	cmp	r3, #0
- 8001f02:	d008      	beq.n	8001f16 <HAL_RCC_ClockConfig+0x166>
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
- 8001f04:	4b19      	ldr	r3, [pc, #100]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001f06:	689b      	ldr	r3, [r3, #8]
- 8001f08:	f423 52e0 	bic.w	r2, r3, #7168	; 0x1c00
- 8001f0c:	687b      	ldr	r3, [r7, #4]
- 8001f0e:	68db      	ldr	r3, [r3, #12]
- 8001f10:	4916      	ldr	r1, [pc, #88]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001f12:	4313      	orrs	r3, r2
- 8001f14:	608b      	str	r3, [r1, #8]
-  }
-
-  /*-------------------------- PCLK2 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
- 8001f16:	687b      	ldr	r3, [r7, #4]
- 8001f18:	681b      	ldr	r3, [r3, #0]
- 8001f1a:	f003 0308 	and.w	r3, r3, #8
- 8001f1e:	2b00      	cmp	r3, #0
- 8001f20:	d009      	beq.n	8001f36 <HAL_RCC_ClockConfig+0x186>
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
- 8001f22:	4b12      	ldr	r3, [pc, #72]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001f24:	689b      	ldr	r3, [r3, #8]
- 8001f26:	f423 4260 	bic.w	r2, r3, #57344	; 0xe000
- 8001f2a:	687b      	ldr	r3, [r7, #4]
- 8001f2c:	691b      	ldr	r3, [r3, #16]
- 8001f2e:	00db      	lsls	r3, r3, #3
- 8001f30:	490e      	ldr	r1, [pc, #56]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001f32:	4313      	orrs	r3, r2
- 8001f34:	608b      	str	r3, [r1, #8]
-  }
-
-  /* Update the SystemCoreClock global variable */
-  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
- 8001f36:	f000 f821 	bl	8001f7c <HAL_RCC_GetSysClockFreq>
- 8001f3a:	4602      	mov	r2, r0
- 8001f3c:	4b0b      	ldr	r3, [pc, #44]	; (8001f6c <HAL_RCC_ClockConfig+0x1bc>)
- 8001f3e:	689b      	ldr	r3, [r3, #8]
- 8001f40:	091b      	lsrs	r3, r3, #4
- 8001f42:	f003 030f 	and.w	r3, r3, #15
- 8001f46:	490a      	ldr	r1, [pc, #40]	; (8001f70 <HAL_RCC_ClockConfig+0x1c0>)
- 8001f48:	5ccb      	ldrb	r3, [r1, r3]
- 8001f4a:	fa22 f303 	lsr.w	r3, r2, r3
- 8001f4e:	4a09      	ldr	r2, [pc, #36]	; (8001f74 <HAL_RCC_ClockConfig+0x1c4>)
- 8001f50:	6013      	str	r3, [r2, #0]
-
-  /* Configure the source of time base considering new system clocks settings */
-  HAL_InitTick (uwTickPrio);
- 8001f52:	4b09      	ldr	r3, [pc, #36]	; (8001f78 <HAL_RCC_ClockConfig+0x1c8>)
- 8001f54:	681b      	ldr	r3, [r3, #0]
- 8001f56:	4618      	mov	r0, r3
- 8001f58:	f7fe fd76 	bl	8000a48 <HAL_InitTick>
-
-  return HAL_OK;
- 8001f5c:	2300      	movs	r3, #0
-}
- 8001f5e:	4618      	mov	r0, r3
- 8001f60:	3710      	adds	r7, #16
- 8001f62:	46bd      	mov	sp, r7
- 8001f64:	bd80      	pop	{r7, pc}
- 8001f66:	bf00      	nop
- 8001f68:	40023c00 	.word	0x40023c00
- 8001f6c:	40023800 	.word	0x40023800
- 8001f70:	08002c1c 	.word	0x08002c1c
- 8001f74:	20000000 	.word	0x20000000
- 8001f78:	20000004 	.word	0x20000004
-
-08001f7c <HAL_RCC_GetSysClockFreq>:
-  *
-  *
-  * @retval SYSCLK frequency
-  */
-__weak uint32_t HAL_RCC_GetSysClockFreq(void)
-{
- 8001f7c:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
- 8001f80:	b090      	sub	sp, #64	; 0x40
- 8001f82:	af00      	add	r7, sp, #0
-  uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
- 8001f84:	2300      	movs	r3, #0
- 8001f86:	637b      	str	r3, [r7, #52]	; 0x34
- 8001f88:	2300      	movs	r3, #0
- 8001f8a:	63fb      	str	r3, [r7, #60]	; 0x3c
- 8001f8c:	2300      	movs	r3, #0
- 8001f8e:	633b      	str	r3, [r7, #48]	; 0x30
-  uint32_t sysclockfreq = 0U;
- 8001f90:	2300      	movs	r3, #0
- 8001f92:	63bb      	str	r3, [r7, #56]	; 0x38
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (RCC->CFGR & RCC_CFGR_SWS)
- 8001f94:	4b59      	ldr	r3, [pc, #356]	; (80020fc <HAL_RCC_GetSysClockFreq+0x180>)
- 8001f96:	689b      	ldr	r3, [r3, #8]
- 8001f98:	f003 030c 	and.w	r3, r3, #12
- 8001f9c:	2b08      	cmp	r3, #8
- 8001f9e:	d00d      	beq.n	8001fbc <HAL_RCC_GetSysClockFreq+0x40>
- 8001fa0:	2b08      	cmp	r3, #8
- 8001fa2:	f200 80a1 	bhi.w	80020e8 <HAL_RCC_GetSysClockFreq+0x16c>
- 8001fa6:	2b00      	cmp	r3, #0
- 8001fa8:	d002      	beq.n	8001fb0 <HAL_RCC_GetSysClockFreq+0x34>
- 8001faa:	2b04      	cmp	r3, #4
- 8001fac:	d003      	beq.n	8001fb6 <HAL_RCC_GetSysClockFreq+0x3a>
- 8001fae:	e09b      	b.n	80020e8 <HAL_RCC_GetSysClockFreq+0x16c>
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
-    {
-      sysclockfreq = HSI_VALUE;
- 8001fb0:	4b53      	ldr	r3, [pc, #332]	; (8002100 <HAL_RCC_GetSysClockFreq+0x184>)
- 8001fb2:	63bb      	str	r3, [r7, #56]	; 0x38
-       break;
- 8001fb4:	e09b      	b.n	80020ee <HAL_RCC_GetSysClockFreq+0x172>
-    }
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
-    {
-      sysclockfreq = HSE_VALUE;
- 8001fb6:	4b53      	ldr	r3, [pc, #332]	; (8002104 <HAL_RCC_GetSysClockFreq+0x188>)
- 8001fb8:	63bb      	str	r3, [r7, #56]	; 0x38
-      break;
- 8001fba:	e098      	b.n	80020ee <HAL_RCC_GetSysClockFreq+0x172>
-    }
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock  source */
-    {
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
-      SYSCLK = PLL_VCO / PLLP */
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
- 8001fbc:	4b4f      	ldr	r3, [pc, #316]	; (80020fc <HAL_RCC_GetSysClockFreq+0x180>)
- 8001fbe:	685b      	ldr	r3, [r3, #4]
- 8001fc0:	f003 033f 	and.w	r3, r3, #63	; 0x3f
- 8001fc4:	637b      	str	r3, [r7, #52]	; 0x34
-      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
- 8001fc6:	4b4d      	ldr	r3, [pc, #308]	; (80020fc <HAL_RCC_GetSysClockFreq+0x180>)
- 8001fc8:	685b      	ldr	r3, [r3, #4]
- 8001fca:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
- 8001fce:	2b00      	cmp	r3, #0
- 8001fd0:	d028      	beq.n	8002024 <HAL_RCC_GetSysClockFreq+0xa8>
-      {
-        /* HSE used as PLL clock source */
-        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 8001fd2:	4b4a      	ldr	r3, [pc, #296]	; (80020fc <HAL_RCC_GetSysClockFreq+0x180>)
- 8001fd4:	685b      	ldr	r3, [r3, #4]
- 8001fd6:	099b      	lsrs	r3, r3, #6
- 8001fd8:	2200      	movs	r2, #0
- 8001fda:	623b      	str	r3, [r7, #32]
- 8001fdc:	627a      	str	r2, [r7, #36]	; 0x24
- 8001fde:	6a3b      	ldr	r3, [r7, #32]
- 8001fe0:	f3c3 0008 	ubfx	r0, r3, #0, #9
- 8001fe4:	2100      	movs	r1, #0
- 8001fe6:	4b47      	ldr	r3, [pc, #284]	; (8002104 <HAL_RCC_GetSysClockFreq+0x188>)
- 8001fe8:	fb03 f201 	mul.w	r2, r3, r1
- 8001fec:	2300      	movs	r3, #0
- 8001fee:	fb00 f303 	mul.w	r3, r0, r3
- 8001ff2:	4413      	add	r3, r2
- 8001ff4:	4a43      	ldr	r2, [pc, #268]	; (8002104 <HAL_RCC_GetSysClockFreq+0x188>)
- 8001ff6:	fba0 1202 	umull	r1, r2, r0, r2
- 8001ffa:	62fa      	str	r2, [r7, #44]	; 0x2c
- 8001ffc:	460a      	mov	r2, r1
- 8001ffe:	62ba      	str	r2, [r7, #40]	; 0x28
- 8002000:	6afa      	ldr	r2, [r7, #44]	; 0x2c
- 8002002:	4413      	add	r3, r2
- 8002004:	62fb      	str	r3, [r7, #44]	; 0x2c
- 8002006:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 8002008:	2200      	movs	r2, #0
- 800200a:	61bb      	str	r3, [r7, #24]
- 800200c:	61fa      	str	r2, [r7, #28]
- 800200e:	e9d7 2306 	ldrd	r2, r3, [r7, #24]
- 8002012:	e9d7 010a 	ldrd	r0, r1, [r7, #40]	; 0x28
- 8002016:	f7fe f8d7 	bl	80001c8 <__aeabi_uldivmod>
- 800201a:	4602      	mov	r2, r0
- 800201c:	460b      	mov	r3, r1
- 800201e:	4613      	mov	r3, r2
- 8002020:	63fb      	str	r3, [r7, #60]	; 0x3c
- 8002022:	e053      	b.n	80020cc <HAL_RCC_GetSysClockFreq+0x150>
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
- 8002024:	4b35      	ldr	r3, [pc, #212]	; (80020fc <HAL_RCC_GetSysClockFreq+0x180>)
- 8002026:	685b      	ldr	r3, [r3, #4]
- 8002028:	099b      	lsrs	r3, r3, #6
- 800202a:	2200      	movs	r2, #0
- 800202c:	613b      	str	r3, [r7, #16]
- 800202e:	617a      	str	r2, [r7, #20]
- 8002030:	693b      	ldr	r3, [r7, #16]
- 8002032:	f3c3 0a08 	ubfx	sl, r3, #0, #9
- 8002036:	f04f 0b00 	mov.w	fp, #0
- 800203a:	4652      	mov	r2, sl
- 800203c:	465b      	mov	r3, fp
- 800203e:	f04f 0000 	mov.w	r0, #0
- 8002042:	f04f 0100 	mov.w	r1, #0
- 8002046:	0159      	lsls	r1, r3, #5
- 8002048:	ea41 61d2 	orr.w	r1, r1, r2, lsr #27
- 800204c:	0150      	lsls	r0, r2, #5
- 800204e:	4602      	mov	r2, r0
- 8002050:	460b      	mov	r3, r1
- 8002052:	ebb2 080a 	subs.w	r8, r2, sl
- 8002056:	eb63 090b 	sbc.w	r9, r3, fp
- 800205a:	f04f 0200 	mov.w	r2, #0
- 800205e:	f04f 0300 	mov.w	r3, #0
- 8002062:	ea4f 1389 	mov.w	r3, r9, lsl #6
- 8002066:	ea43 6398 	orr.w	r3, r3, r8, lsr #26
- 800206a:	ea4f 1288 	mov.w	r2, r8, lsl #6
- 800206e:	ebb2 0408 	subs.w	r4, r2, r8
- 8002072:	eb63 0509 	sbc.w	r5, r3, r9
- 8002076:	f04f 0200 	mov.w	r2, #0
- 800207a:	f04f 0300 	mov.w	r3, #0
- 800207e:	00eb      	lsls	r3, r5, #3
- 8002080:	ea43 7354 	orr.w	r3, r3, r4, lsr #29
- 8002084:	00e2      	lsls	r2, r4, #3
- 8002086:	4614      	mov	r4, r2
- 8002088:	461d      	mov	r5, r3
- 800208a:	eb14 030a 	adds.w	r3, r4, sl
- 800208e:	603b      	str	r3, [r7, #0]
- 8002090:	eb45 030b 	adc.w	r3, r5, fp
- 8002094:	607b      	str	r3, [r7, #4]
- 8002096:	f04f 0200 	mov.w	r2, #0
- 800209a:	f04f 0300 	mov.w	r3, #0
- 800209e:	e9d7 4500 	ldrd	r4, r5, [r7]
- 80020a2:	4629      	mov	r1, r5
- 80020a4:	028b      	lsls	r3, r1, #10
- 80020a6:	4621      	mov	r1, r4
- 80020a8:	ea43 5391 	orr.w	r3, r3, r1, lsr #22
- 80020ac:	4621      	mov	r1, r4
- 80020ae:	028a      	lsls	r2, r1, #10
- 80020b0:	4610      	mov	r0, r2
- 80020b2:	4619      	mov	r1, r3
- 80020b4:	6b7b      	ldr	r3, [r7, #52]	; 0x34
- 80020b6:	2200      	movs	r2, #0
- 80020b8:	60bb      	str	r3, [r7, #8]
- 80020ba:	60fa      	str	r2, [r7, #12]
- 80020bc:	e9d7 2302 	ldrd	r2, r3, [r7, #8]
- 80020c0:	f7fe f882 	bl	80001c8 <__aeabi_uldivmod>
- 80020c4:	4602      	mov	r2, r0
- 80020c6:	460b      	mov	r3, r1
- 80020c8:	4613      	mov	r3, r2
- 80020ca:	63fb      	str	r3, [r7, #60]	; 0x3c
-      }
-      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
- 80020cc:	4b0b      	ldr	r3, [pc, #44]	; (80020fc <HAL_RCC_GetSysClockFreq+0x180>)
- 80020ce:	685b      	ldr	r3, [r3, #4]
- 80020d0:	0c1b      	lsrs	r3, r3, #16
- 80020d2:	f003 0303 	and.w	r3, r3, #3
- 80020d6:	3301      	adds	r3, #1
- 80020d8:	005b      	lsls	r3, r3, #1
- 80020da:	633b      	str	r3, [r7, #48]	; 0x30
-
-      sysclockfreq = pllvco/pllp;
- 80020dc:	6bfa      	ldr	r2, [r7, #60]	; 0x3c
- 80020de:	6b3b      	ldr	r3, [r7, #48]	; 0x30
- 80020e0:	fbb2 f3f3 	udiv	r3, r2, r3
- 80020e4:	63bb      	str	r3, [r7, #56]	; 0x38
-      break;
- 80020e6:	e002      	b.n	80020ee <HAL_RCC_GetSysClockFreq+0x172>
-    }
-    default:
-    {
-      sysclockfreq = HSI_VALUE;
- 80020e8:	4b05      	ldr	r3, [pc, #20]	; (8002100 <HAL_RCC_GetSysClockFreq+0x184>)
- 80020ea:	63bb      	str	r3, [r7, #56]	; 0x38
-      break;
- 80020ec:	bf00      	nop
-    }
-  }
-  return sysclockfreq;
- 80020ee:	6bbb      	ldr	r3, [r7, #56]	; 0x38
-}
- 80020f0:	4618      	mov	r0, r3
- 80020f2:	3740      	adds	r7, #64	; 0x40
- 80020f4:	46bd      	mov	sp, r7
- 80020f6:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
- 80020fa:	bf00      	nop
- 80020fc:	40023800 	.word	0x40023800
- 8002100:	00f42400 	.word	0x00f42400
- 8002104:	017d7840 	.word	0x017d7840
-
-08002108 <HAL_RCC_GetHCLKFreq>:
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
-  *         and updated within this function
-  * @retval HCLK frequency
-  */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
- 8002108:	b480      	push	{r7}
- 800210a:	af00      	add	r7, sp, #0
-  return SystemCoreClock;
- 800210c:	4b03      	ldr	r3, [pc, #12]	; (800211c <HAL_RCC_GetHCLKFreq+0x14>)
- 800210e:	681b      	ldr	r3, [r3, #0]
-}
- 8002110:	4618      	mov	r0, r3
- 8002112:	46bd      	mov	sp, r7
- 8002114:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8002118:	4770      	bx	lr
- 800211a:	bf00      	nop
- 800211c:	20000000 	.word	0x20000000
-
-08002120 <HAL_RCC_GetPCLK1Freq>:
-  * @note   Each time PCLK1 changes, this function must be called to update the
-  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
-  * @retval PCLK1 frequency
-  */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
- 8002120:	b580      	push	{r7, lr}
- 8002122:	af00      	add	r7, sp, #0
-  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
- 8002124:	f7ff fff0 	bl	8002108 <HAL_RCC_GetHCLKFreq>
- 8002128:	4602      	mov	r2, r0
- 800212a:	4b05      	ldr	r3, [pc, #20]	; (8002140 <HAL_RCC_GetPCLK1Freq+0x20>)
- 800212c:	689b      	ldr	r3, [r3, #8]
- 800212e:	0a9b      	lsrs	r3, r3, #10
- 8002130:	f003 0307 	and.w	r3, r3, #7
- 8002134:	4903      	ldr	r1, [pc, #12]	; (8002144 <HAL_RCC_GetPCLK1Freq+0x24>)
- 8002136:	5ccb      	ldrb	r3, [r1, r3]
- 8002138:	fa22 f303 	lsr.w	r3, r2, r3
-}
- 800213c:	4618      	mov	r0, r3
- 800213e:	bd80      	pop	{r7, pc}
- 8002140:	40023800 	.word	0x40023800
- 8002144:	08002c2c 	.word	0x08002c2c
-
-08002148 <HAL_RCC_GetPCLK2Freq>:
-  * @note   Each time PCLK2 changes, this function must be called to update the
-  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
-  * @retval PCLK2 frequency
-  */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
- 8002148:	b580      	push	{r7, lr}
- 800214a:	af00      	add	r7, sp, #0
-  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
- 800214c:	f7ff ffdc 	bl	8002108 <HAL_RCC_GetHCLKFreq>
- 8002150:	4602      	mov	r2, r0
- 8002152:	4b05      	ldr	r3, [pc, #20]	; (8002168 <HAL_RCC_GetPCLK2Freq+0x20>)
- 8002154:	689b      	ldr	r3, [r3, #8]
- 8002156:	0b5b      	lsrs	r3, r3, #13
- 8002158:	f003 0307 	and.w	r3, r3, #7
- 800215c:	4903      	ldr	r1, [pc, #12]	; (800216c <HAL_RCC_GetPCLK2Freq+0x24>)
- 800215e:	5ccb      	ldrb	r3, [r1, r3]
- 8002160:	fa22 f303 	lsr.w	r3, r2, r3
-}
- 8002164:	4618      	mov	r0, r3
- 8002166:	bd80      	pop	{r7, pc}
- 8002168:	40023800 	.word	0x40023800
- 800216c:	08002c2c 	.word	0x08002c2c
-
-08002170 <HAL_UART_Init>:
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
- 8002170:	b580      	push	{r7, lr}
- 8002172:	b082      	sub	sp, #8
- 8002174:	af00      	add	r7, sp, #0
- 8002176:	6078      	str	r0, [r7, #4]
-  /* Check the UART handle allocation */
-  if (huart == NULL)
- 8002178:	687b      	ldr	r3, [r7, #4]
- 800217a:	2b00      	cmp	r3, #0
- 800217c:	d101      	bne.n	8002182 <HAL_UART_Init+0x12>
-  {
-    return HAL_ERROR;
- 800217e:	2301      	movs	r3, #1
- 8002180:	e03f      	b.n	8002202 <HAL_UART_Init+0x92>
-    assert_param(IS_UART_INSTANCE(huart->Instance));
-  }
-  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-
-  if (huart->gState == HAL_UART_STATE_RESET)
- 8002182:	687b      	ldr	r3, [r7, #4]
- 8002184:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
- 8002188:	b2db      	uxtb	r3, r3
- 800218a:	2b00      	cmp	r3, #0
- 800218c:	d106      	bne.n	800219c <HAL_UART_Init+0x2c>
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
- 800218e:	687b      	ldr	r3, [r7, #4]
- 8002190:	2200      	movs	r2, #0
- 8002192:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
-
-    /* Init the low level hardware */
-    huart->MspInitCallback(huart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
- 8002196:	6878      	ldr	r0, [r7, #4]
- 8002198:	f7fe fb86 	bl	80008a8 <HAL_UART_MspInit>
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
- 800219c:	687b      	ldr	r3, [r7, #4]
- 800219e:	2224      	movs	r2, #36	; 0x24
- 80021a0:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
- 80021a4:	687b      	ldr	r3, [r7, #4]
- 80021a6:	681b      	ldr	r3, [r3, #0]
- 80021a8:	68da      	ldr	r2, [r3, #12]
- 80021aa:	687b      	ldr	r3, [r7, #4]
- 80021ac:	681b      	ldr	r3, [r3, #0]
- 80021ae:	f422 5200 	bic.w	r2, r2, #8192	; 0x2000
- 80021b2:	60da      	str	r2, [r3, #12]
-
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
- 80021b4:	6878      	ldr	r0, [r7, #4]
- 80021b6:	f000 f829 	bl	800220c <UART_SetConfig>
-
-  /* In asynchronous mode, the following bits must be kept cleared:
-     - LINEN and CLKEN bits in the USART_CR2 register,
-     - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- 80021ba:	687b      	ldr	r3, [r7, #4]
- 80021bc:	681b      	ldr	r3, [r3, #0]
- 80021be:	691a      	ldr	r2, [r3, #16]
- 80021c0:	687b      	ldr	r3, [r7, #4]
- 80021c2:	681b      	ldr	r3, [r3, #0]
- 80021c4:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
- 80021c8:	611a      	str	r2, [r3, #16]
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
- 80021ca:	687b      	ldr	r3, [r7, #4]
- 80021cc:	681b      	ldr	r3, [r3, #0]
- 80021ce:	695a      	ldr	r2, [r3, #20]
- 80021d0:	687b      	ldr	r3, [r7, #4]
- 80021d2:	681b      	ldr	r3, [r3, #0]
- 80021d4:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
- 80021d8:	615a      	str	r2, [r3, #20]
-
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
- 80021da:	687b      	ldr	r3, [r7, #4]
- 80021dc:	681b      	ldr	r3, [r3, #0]
- 80021de:	68da      	ldr	r2, [r3, #12]
- 80021e0:	687b      	ldr	r3, [r7, #4]
- 80021e2:	681b      	ldr	r3, [r3, #0]
- 80021e4:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
- 80021e8:	60da      	str	r2, [r3, #12]
-
-  /* Initialize the UART state */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
- 80021ea:	687b      	ldr	r3, [r7, #4]
- 80021ec:	2200      	movs	r2, #0
- 80021ee:	641a      	str	r2, [r3, #64]	; 0x40
-  huart->gState = HAL_UART_STATE_READY;
- 80021f0:	687b      	ldr	r3, [r7, #4]
- 80021f2:	2220      	movs	r2, #32
- 80021f4:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
-  huart->RxState = HAL_UART_STATE_READY;
- 80021f8:	687b      	ldr	r3, [r7, #4]
- 80021fa:	2220      	movs	r2, #32
- 80021fc:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
-
-  return HAL_OK;
- 8002200:	2300      	movs	r3, #0
-}
- 8002202:	4618      	mov	r0, r3
- 8002204:	3708      	adds	r7, #8
- 8002206:	46bd      	mov	sp, r7
- 8002208:	bd80      	pop	{r7, pc}
-	...
-
-0800220c <UART_SetConfig>:
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-static void UART_SetConfig(UART_HandleTypeDef *huart)
-{
- 800220c:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
- 8002210:	b0c0      	sub	sp, #256	; 0x100
- 8002212:	af00      	add	r7, sp, #0
- 8002214:	f8c7 00f4 	str.w	r0, [r7, #244]	; 0xf4
-  assert_param(IS_UART_MODE(huart->Init.Mode));
-
-  /*-------------------------- USART CR2 Configuration -----------------------*/
-  /* Configure the UART Stop Bits: Set STOP[13:12] bits
-     according to huart->Init.StopBits value */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
- 8002218:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 800221c:	681b      	ldr	r3, [r3, #0]
- 800221e:	691b      	ldr	r3, [r3, #16]
- 8002220:	f423 5040 	bic.w	r0, r3, #12288	; 0x3000
- 8002224:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 8002228:	68d9      	ldr	r1, [r3, #12]
- 800222a:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 800222e:	681a      	ldr	r2, [r3, #0]
- 8002230:	ea40 0301 	orr.w	r3, r0, r1
- 8002234:	6113      	str	r3, [r2, #16]
-     Set the M bits according to huart->Init.WordLength value
-     Set PCE and PS bits according to huart->Init.Parity value
-     Set TE and RE bits according to huart->Init.Mode value
-     Set OVER8 bit according to huart->Init.OverSampling value */
-
-  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
- 8002236:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 800223a:	689a      	ldr	r2, [r3, #8]
- 800223c:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 8002240:	691b      	ldr	r3, [r3, #16]
- 8002242:	431a      	orrs	r2, r3
- 8002244:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 8002248:	695b      	ldr	r3, [r3, #20]
- 800224a:	431a      	orrs	r2, r3
- 800224c:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 8002250:	69db      	ldr	r3, [r3, #28]
- 8002252:	4313      	orrs	r3, r2
- 8002254:	f8c7 30f8 	str.w	r3, [r7, #248]	; 0xf8
-  MODIFY_REG(huart->Instance->CR1,
- 8002258:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 800225c:	681b      	ldr	r3, [r3, #0]
- 800225e:	68db      	ldr	r3, [r3, #12]
- 8002260:	f423 4116 	bic.w	r1, r3, #38400	; 0x9600
- 8002264:	f021 010c 	bic.w	r1, r1, #12
- 8002268:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 800226c:	681a      	ldr	r2, [r3, #0]
- 800226e:	f8d7 30f8 	ldr.w	r3, [r7, #248]	; 0xf8
- 8002272:	430b      	orrs	r3, r1
- 8002274:	60d3      	str	r3, [r2, #12]
-             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
-             tmpreg);
-
-  /*-------------------------- USART CR3 Configuration -----------------------*/
-  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
-  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
- 8002276:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 800227a:	681b      	ldr	r3, [r3, #0]
- 800227c:	695b      	ldr	r3, [r3, #20]
- 800227e:	f423 7040 	bic.w	r0, r3, #768	; 0x300
- 8002282:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 8002286:	6999      	ldr	r1, [r3, #24]
- 8002288:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 800228c:	681a      	ldr	r2, [r3, #0]
- 800228e:	ea40 0301 	orr.w	r3, r0, r1
- 8002292:	6153      	str	r3, [r2, #20]
-    if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
-    {
-      pclk = HAL_RCC_GetPCLK2Freq();
-    }
-#elif defined(USART6)
-    if ((huart->Instance == USART1) || (huart->Instance == USART6))
- 8002294:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 8002298:	681a      	ldr	r2, [r3, #0]
- 800229a:	4b8f      	ldr	r3, [pc, #572]	; (80024d8 <UART_SetConfig+0x2cc>)
- 800229c:	429a      	cmp	r2, r3
- 800229e:	d005      	beq.n	80022ac <UART_SetConfig+0xa0>
- 80022a0:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 80022a4:	681a      	ldr	r2, [r3, #0]
- 80022a6:	4b8d      	ldr	r3, [pc, #564]	; (80024dc <UART_SetConfig+0x2d0>)
- 80022a8:	429a      	cmp	r2, r3
- 80022aa:	d104      	bne.n	80022b6 <UART_SetConfig+0xaa>
-    {
-      pclk = HAL_RCC_GetPCLK2Freq();
- 80022ac:	f7ff ff4c 	bl	8002148 <HAL_RCC_GetPCLK2Freq>
- 80022b0:	f8c7 00fc 	str.w	r0, [r7, #252]	; 0xfc
- 80022b4:	e003      	b.n	80022be <UART_SetConfig+0xb2>
-      pclk = HAL_RCC_GetPCLK2Freq();
-    }
-#endif /* USART6 */
-    else
-    {
-      pclk = HAL_RCC_GetPCLK1Freq();
- 80022b6:	f7ff ff33 	bl	8002120 <HAL_RCC_GetPCLK1Freq>
- 80022ba:	f8c7 00fc 	str.w	r0, [r7, #252]	; 0xfc
-    }
-  /*-------------------------- USART BRR Configuration ---------------------*/
-  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
- 80022be:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 80022c2:	69db      	ldr	r3, [r3, #28]
- 80022c4:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
- 80022c8:	f040 810c 	bne.w	80024e4 <UART_SetConfig+0x2d8>
-  {
-    huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
- 80022cc:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
- 80022d0:	2200      	movs	r2, #0
- 80022d2:	f8c7 30e8 	str.w	r3, [r7, #232]	; 0xe8
- 80022d6:	f8c7 20ec 	str.w	r2, [r7, #236]	; 0xec
- 80022da:	e9d7 453a 	ldrd	r4, r5, [r7, #232]	; 0xe8
- 80022de:	4622      	mov	r2, r4
- 80022e0:	462b      	mov	r3, r5
- 80022e2:	1891      	adds	r1, r2, r2
- 80022e4:	65b9      	str	r1, [r7, #88]	; 0x58
- 80022e6:	415b      	adcs	r3, r3
- 80022e8:	65fb      	str	r3, [r7, #92]	; 0x5c
- 80022ea:	e9d7 2316 	ldrd	r2, r3, [r7, #88]	; 0x58
- 80022ee:	4621      	mov	r1, r4
- 80022f0:	eb12 0801 	adds.w	r8, r2, r1
- 80022f4:	4629      	mov	r1, r5
- 80022f6:	eb43 0901 	adc.w	r9, r3, r1
- 80022fa:	f04f 0200 	mov.w	r2, #0
- 80022fe:	f04f 0300 	mov.w	r3, #0
- 8002302:	ea4f 03c9 	mov.w	r3, r9, lsl #3
- 8002306:	ea43 7358 	orr.w	r3, r3, r8, lsr #29
- 800230a:	ea4f 02c8 	mov.w	r2, r8, lsl #3
- 800230e:	4690      	mov	r8, r2
- 8002310:	4699      	mov	r9, r3
- 8002312:	4623      	mov	r3, r4
- 8002314:	eb18 0303 	adds.w	r3, r8, r3
- 8002318:	f8c7 30e0 	str.w	r3, [r7, #224]	; 0xe0
- 800231c:	462b      	mov	r3, r5
- 800231e:	eb49 0303 	adc.w	r3, r9, r3
- 8002322:	f8c7 30e4 	str.w	r3, [r7, #228]	; 0xe4
- 8002326:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 800232a:	685b      	ldr	r3, [r3, #4]
- 800232c:	2200      	movs	r2, #0
- 800232e:	f8c7 30d8 	str.w	r3, [r7, #216]	; 0xd8
- 8002332:	f8c7 20dc 	str.w	r2, [r7, #220]	; 0xdc
- 8002336:	e9d7 1236 	ldrd	r1, r2, [r7, #216]	; 0xd8
- 800233a:	460b      	mov	r3, r1
- 800233c:	18db      	adds	r3, r3, r3
- 800233e:	653b      	str	r3, [r7, #80]	; 0x50
- 8002340:	4613      	mov	r3, r2
- 8002342:	eb42 0303 	adc.w	r3, r2, r3
- 8002346:	657b      	str	r3, [r7, #84]	; 0x54
- 8002348:	e9d7 2314 	ldrd	r2, r3, [r7, #80]	; 0x50
- 800234c:	e9d7 0138 	ldrd	r0, r1, [r7, #224]	; 0xe0
- 8002350:	f7fd ff3a 	bl	80001c8 <__aeabi_uldivmod>
- 8002354:	4602      	mov	r2, r0
- 8002356:	460b      	mov	r3, r1
- 8002358:	4b61      	ldr	r3, [pc, #388]	; (80024e0 <UART_SetConfig+0x2d4>)
- 800235a:	fba3 2302 	umull	r2, r3, r3, r2
- 800235e:	095b      	lsrs	r3, r3, #5
- 8002360:	011c      	lsls	r4, r3, #4
- 8002362:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
- 8002366:	2200      	movs	r2, #0
- 8002368:	f8c7 30d0 	str.w	r3, [r7, #208]	; 0xd0
- 800236c:	f8c7 20d4 	str.w	r2, [r7, #212]	; 0xd4
- 8002370:	e9d7 8934 	ldrd	r8, r9, [r7, #208]	; 0xd0
- 8002374:	4642      	mov	r2, r8
- 8002376:	464b      	mov	r3, r9
- 8002378:	1891      	adds	r1, r2, r2
- 800237a:	64b9      	str	r1, [r7, #72]	; 0x48
- 800237c:	415b      	adcs	r3, r3
- 800237e:	64fb      	str	r3, [r7, #76]	; 0x4c
- 8002380:	e9d7 2312 	ldrd	r2, r3, [r7, #72]	; 0x48
- 8002384:	4641      	mov	r1, r8
- 8002386:	eb12 0a01 	adds.w	sl, r2, r1
- 800238a:	4649      	mov	r1, r9
- 800238c:	eb43 0b01 	adc.w	fp, r3, r1
- 8002390:	f04f 0200 	mov.w	r2, #0
- 8002394:	f04f 0300 	mov.w	r3, #0
- 8002398:	ea4f 03cb 	mov.w	r3, fp, lsl #3
- 800239c:	ea43 735a 	orr.w	r3, r3, sl, lsr #29
- 80023a0:	ea4f 02ca 	mov.w	r2, sl, lsl #3
- 80023a4:	4692      	mov	sl, r2
- 80023a6:	469b      	mov	fp, r3
- 80023a8:	4643      	mov	r3, r8
- 80023aa:	eb1a 0303 	adds.w	r3, sl, r3
- 80023ae:	f8c7 30c8 	str.w	r3, [r7, #200]	; 0xc8
- 80023b2:	464b      	mov	r3, r9
- 80023b4:	eb4b 0303 	adc.w	r3, fp, r3
- 80023b8:	f8c7 30cc 	str.w	r3, [r7, #204]	; 0xcc
- 80023bc:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 80023c0:	685b      	ldr	r3, [r3, #4]
- 80023c2:	2200      	movs	r2, #0
- 80023c4:	f8c7 30c0 	str.w	r3, [r7, #192]	; 0xc0
- 80023c8:	f8c7 20c4 	str.w	r2, [r7, #196]	; 0xc4
- 80023cc:	e9d7 1230 	ldrd	r1, r2, [r7, #192]	; 0xc0
- 80023d0:	460b      	mov	r3, r1
- 80023d2:	18db      	adds	r3, r3, r3
- 80023d4:	643b      	str	r3, [r7, #64]	; 0x40
- 80023d6:	4613      	mov	r3, r2
- 80023d8:	eb42 0303 	adc.w	r3, r2, r3
- 80023dc:	647b      	str	r3, [r7, #68]	; 0x44
- 80023de:	e9d7 2310 	ldrd	r2, r3, [r7, #64]	; 0x40
- 80023e2:	e9d7 0132 	ldrd	r0, r1, [r7, #200]	; 0xc8
- 80023e6:	f7fd feef 	bl	80001c8 <__aeabi_uldivmod>
- 80023ea:	4602      	mov	r2, r0
- 80023ec:	460b      	mov	r3, r1
- 80023ee:	4611      	mov	r1, r2
- 80023f0:	4b3b      	ldr	r3, [pc, #236]	; (80024e0 <UART_SetConfig+0x2d4>)
- 80023f2:	fba3 2301 	umull	r2, r3, r3, r1
- 80023f6:	095b      	lsrs	r3, r3, #5
- 80023f8:	2264      	movs	r2, #100	; 0x64
- 80023fa:	fb02 f303 	mul.w	r3, r2, r3
- 80023fe:	1acb      	subs	r3, r1, r3
- 8002400:	00db      	lsls	r3, r3, #3
- 8002402:	f103 0232 	add.w	r2, r3, #50	; 0x32
- 8002406:	4b36      	ldr	r3, [pc, #216]	; (80024e0 <UART_SetConfig+0x2d4>)
- 8002408:	fba3 2302 	umull	r2, r3, r3, r2
- 800240c:	095b      	lsrs	r3, r3, #5
- 800240e:	005b      	lsls	r3, r3, #1
- 8002410:	f403 73f8 	and.w	r3, r3, #496	; 0x1f0
- 8002414:	441c      	add	r4, r3
- 8002416:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
- 800241a:	2200      	movs	r2, #0
- 800241c:	f8c7 30b8 	str.w	r3, [r7, #184]	; 0xb8
- 8002420:	f8c7 20bc 	str.w	r2, [r7, #188]	; 0xbc
- 8002424:	e9d7 892e 	ldrd	r8, r9, [r7, #184]	; 0xb8
- 8002428:	4642      	mov	r2, r8
- 800242a:	464b      	mov	r3, r9
- 800242c:	1891      	adds	r1, r2, r2
- 800242e:	63b9      	str	r1, [r7, #56]	; 0x38
- 8002430:	415b      	adcs	r3, r3
- 8002432:	63fb      	str	r3, [r7, #60]	; 0x3c
- 8002434:	e9d7 230e 	ldrd	r2, r3, [r7, #56]	; 0x38
- 8002438:	4641      	mov	r1, r8
- 800243a:	1851      	adds	r1, r2, r1
- 800243c:	6339      	str	r1, [r7, #48]	; 0x30
- 800243e:	4649      	mov	r1, r9
- 8002440:	414b      	adcs	r3, r1
- 8002442:	637b      	str	r3, [r7, #52]	; 0x34
- 8002444:	f04f 0200 	mov.w	r2, #0
- 8002448:	f04f 0300 	mov.w	r3, #0
- 800244c:	e9d7 ab0c 	ldrd	sl, fp, [r7, #48]	; 0x30
- 8002450:	4659      	mov	r1, fp
- 8002452:	00cb      	lsls	r3, r1, #3
- 8002454:	4651      	mov	r1, sl
- 8002456:	ea43 7351 	orr.w	r3, r3, r1, lsr #29
- 800245a:	4651      	mov	r1, sl
- 800245c:	00ca      	lsls	r2, r1, #3
- 800245e:	4610      	mov	r0, r2
- 8002460:	4619      	mov	r1, r3
- 8002462:	4603      	mov	r3, r0
- 8002464:	4642      	mov	r2, r8
- 8002466:	189b      	adds	r3, r3, r2
- 8002468:	f8c7 30b0 	str.w	r3, [r7, #176]	; 0xb0
- 800246c:	464b      	mov	r3, r9
- 800246e:	460a      	mov	r2, r1
- 8002470:	eb42 0303 	adc.w	r3, r2, r3
- 8002474:	f8c7 30b4 	str.w	r3, [r7, #180]	; 0xb4
- 8002478:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 800247c:	685b      	ldr	r3, [r3, #4]
- 800247e:	2200      	movs	r2, #0
- 8002480:	f8c7 30a8 	str.w	r3, [r7, #168]	; 0xa8
- 8002484:	f8c7 20ac 	str.w	r2, [r7, #172]	; 0xac
- 8002488:	e9d7 122a 	ldrd	r1, r2, [r7, #168]	; 0xa8
- 800248c:	460b      	mov	r3, r1
- 800248e:	18db      	adds	r3, r3, r3
- 8002490:	62bb      	str	r3, [r7, #40]	; 0x28
- 8002492:	4613      	mov	r3, r2
- 8002494:	eb42 0303 	adc.w	r3, r2, r3
- 8002498:	62fb      	str	r3, [r7, #44]	; 0x2c
- 800249a:	e9d7 230a 	ldrd	r2, r3, [r7, #40]	; 0x28
- 800249e:	e9d7 012c 	ldrd	r0, r1, [r7, #176]	; 0xb0
- 80024a2:	f7fd fe91 	bl	80001c8 <__aeabi_uldivmod>
- 80024a6:	4602      	mov	r2, r0
- 80024a8:	460b      	mov	r3, r1
- 80024aa:	4b0d      	ldr	r3, [pc, #52]	; (80024e0 <UART_SetConfig+0x2d4>)
- 80024ac:	fba3 1302 	umull	r1, r3, r3, r2
- 80024b0:	095b      	lsrs	r3, r3, #5
- 80024b2:	2164      	movs	r1, #100	; 0x64
- 80024b4:	fb01 f303 	mul.w	r3, r1, r3
- 80024b8:	1ad3      	subs	r3, r2, r3
- 80024ba:	00db      	lsls	r3, r3, #3
- 80024bc:	3332      	adds	r3, #50	; 0x32
- 80024be:	4a08      	ldr	r2, [pc, #32]	; (80024e0 <UART_SetConfig+0x2d4>)
- 80024c0:	fba2 2303 	umull	r2, r3, r2, r3
- 80024c4:	095b      	lsrs	r3, r3, #5
- 80024c6:	f003 0207 	and.w	r2, r3, #7
- 80024ca:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 80024ce:	681b      	ldr	r3, [r3, #0]
- 80024d0:	4422      	add	r2, r4
- 80024d2:	609a      	str	r2, [r3, #8]
-  }
-  else
-  {
-    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
-  }
-}
- 80024d4:	e106      	b.n	80026e4 <UART_SetConfig+0x4d8>
- 80024d6:	bf00      	nop
- 80024d8:	40011000 	.word	0x40011000
- 80024dc:	40011400 	.word	0x40011400
- 80024e0:	51eb851f 	.word	0x51eb851f
-    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
- 80024e4:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
- 80024e8:	2200      	movs	r2, #0
- 80024ea:	f8c7 30a0 	str.w	r3, [r7, #160]	; 0xa0
- 80024ee:	f8c7 20a4 	str.w	r2, [r7, #164]	; 0xa4
- 80024f2:	e9d7 8928 	ldrd	r8, r9, [r7, #160]	; 0xa0
- 80024f6:	4642      	mov	r2, r8
- 80024f8:	464b      	mov	r3, r9
- 80024fa:	1891      	adds	r1, r2, r2
- 80024fc:	6239      	str	r1, [r7, #32]
- 80024fe:	415b      	adcs	r3, r3
- 8002500:	627b      	str	r3, [r7, #36]	; 0x24
- 8002502:	e9d7 2308 	ldrd	r2, r3, [r7, #32]
- 8002506:	4641      	mov	r1, r8
- 8002508:	1854      	adds	r4, r2, r1
- 800250a:	4649      	mov	r1, r9
- 800250c:	eb43 0501 	adc.w	r5, r3, r1
- 8002510:	f04f 0200 	mov.w	r2, #0
- 8002514:	f04f 0300 	mov.w	r3, #0
- 8002518:	00eb      	lsls	r3, r5, #3
- 800251a:	ea43 7354 	orr.w	r3, r3, r4, lsr #29
- 800251e:	00e2      	lsls	r2, r4, #3
- 8002520:	4614      	mov	r4, r2
- 8002522:	461d      	mov	r5, r3
- 8002524:	4643      	mov	r3, r8
- 8002526:	18e3      	adds	r3, r4, r3
- 8002528:	f8c7 3098 	str.w	r3, [r7, #152]	; 0x98
- 800252c:	464b      	mov	r3, r9
- 800252e:	eb45 0303 	adc.w	r3, r5, r3
- 8002532:	f8c7 309c 	str.w	r3, [r7, #156]	; 0x9c
- 8002536:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 800253a:	685b      	ldr	r3, [r3, #4]
- 800253c:	2200      	movs	r2, #0
- 800253e:	f8c7 3090 	str.w	r3, [r7, #144]	; 0x90
- 8002542:	f8c7 2094 	str.w	r2, [r7, #148]	; 0x94
- 8002546:	f04f 0200 	mov.w	r2, #0
- 800254a:	f04f 0300 	mov.w	r3, #0
- 800254e:	e9d7 4524 	ldrd	r4, r5, [r7, #144]	; 0x90
- 8002552:	4629      	mov	r1, r5
- 8002554:	008b      	lsls	r3, r1, #2
- 8002556:	4621      	mov	r1, r4
- 8002558:	ea43 7391 	orr.w	r3, r3, r1, lsr #30
- 800255c:	4621      	mov	r1, r4
- 800255e:	008a      	lsls	r2, r1, #2
- 8002560:	e9d7 0126 	ldrd	r0, r1, [r7, #152]	; 0x98
- 8002564:	f7fd fe30 	bl	80001c8 <__aeabi_uldivmod>
- 8002568:	4602      	mov	r2, r0
- 800256a:	460b      	mov	r3, r1
- 800256c:	4b60      	ldr	r3, [pc, #384]	; (80026f0 <UART_SetConfig+0x4e4>)
- 800256e:	fba3 2302 	umull	r2, r3, r3, r2
- 8002572:	095b      	lsrs	r3, r3, #5
- 8002574:	011c      	lsls	r4, r3, #4
- 8002576:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
- 800257a:	2200      	movs	r2, #0
- 800257c:	f8c7 3088 	str.w	r3, [r7, #136]	; 0x88
- 8002580:	f8c7 208c 	str.w	r2, [r7, #140]	; 0x8c
- 8002584:	e9d7 8922 	ldrd	r8, r9, [r7, #136]	; 0x88
- 8002588:	4642      	mov	r2, r8
- 800258a:	464b      	mov	r3, r9
- 800258c:	1891      	adds	r1, r2, r2
- 800258e:	61b9      	str	r1, [r7, #24]
- 8002590:	415b      	adcs	r3, r3
- 8002592:	61fb      	str	r3, [r7, #28]
- 8002594:	e9d7 2306 	ldrd	r2, r3, [r7, #24]
- 8002598:	4641      	mov	r1, r8
- 800259a:	1851      	adds	r1, r2, r1
- 800259c:	6139      	str	r1, [r7, #16]
- 800259e:	4649      	mov	r1, r9
- 80025a0:	414b      	adcs	r3, r1
- 80025a2:	617b      	str	r3, [r7, #20]
- 80025a4:	f04f 0200 	mov.w	r2, #0
- 80025a8:	f04f 0300 	mov.w	r3, #0
- 80025ac:	e9d7 ab04 	ldrd	sl, fp, [r7, #16]
- 80025b0:	4659      	mov	r1, fp
- 80025b2:	00cb      	lsls	r3, r1, #3
- 80025b4:	4651      	mov	r1, sl
- 80025b6:	ea43 7351 	orr.w	r3, r3, r1, lsr #29
- 80025ba:	4651      	mov	r1, sl
- 80025bc:	00ca      	lsls	r2, r1, #3
- 80025be:	4610      	mov	r0, r2
- 80025c0:	4619      	mov	r1, r3
- 80025c2:	4603      	mov	r3, r0
- 80025c4:	4642      	mov	r2, r8
- 80025c6:	189b      	adds	r3, r3, r2
- 80025c8:	f8c7 3080 	str.w	r3, [r7, #128]	; 0x80
- 80025cc:	464b      	mov	r3, r9
- 80025ce:	460a      	mov	r2, r1
- 80025d0:	eb42 0303 	adc.w	r3, r2, r3
- 80025d4:	f8c7 3084 	str.w	r3, [r7, #132]	; 0x84
- 80025d8:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 80025dc:	685b      	ldr	r3, [r3, #4]
- 80025de:	2200      	movs	r2, #0
- 80025e0:	67bb      	str	r3, [r7, #120]	; 0x78
- 80025e2:	67fa      	str	r2, [r7, #124]	; 0x7c
- 80025e4:	f04f 0200 	mov.w	r2, #0
- 80025e8:	f04f 0300 	mov.w	r3, #0
- 80025ec:	e9d7 891e 	ldrd	r8, r9, [r7, #120]	; 0x78
- 80025f0:	4649      	mov	r1, r9
- 80025f2:	008b      	lsls	r3, r1, #2
- 80025f4:	4641      	mov	r1, r8
- 80025f6:	ea43 7391 	orr.w	r3, r3, r1, lsr #30
- 80025fa:	4641      	mov	r1, r8
- 80025fc:	008a      	lsls	r2, r1, #2
- 80025fe:	e9d7 0120 	ldrd	r0, r1, [r7, #128]	; 0x80
- 8002602:	f7fd fde1 	bl	80001c8 <__aeabi_uldivmod>
- 8002606:	4602      	mov	r2, r0
- 8002608:	460b      	mov	r3, r1
- 800260a:	4611      	mov	r1, r2
- 800260c:	4b38      	ldr	r3, [pc, #224]	; (80026f0 <UART_SetConfig+0x4e4>)
- 800260e:	fba3 2301 	umull	r2, r3, r3, r1
- 8002612:	095b      	lsrs	r3, r3, #5
- 8002614:	2264      	movs	r2, #100	; 0x64
- 8002616:	fb02 f303 	mul.w	r3, r2, r3
- 800261a:	1acb      	subs	r3, r1, r3
- 800261c:	011b      	lsls	r3, r3, #4
- 800261e:	3332      	adds	r3, #50	; 0x32
- 8002620:	4a33      	ldr	r2, [pc, #204]	; (80026f0 <UART_SetConfig+0x4e4>)
- 8002622:	fba2 2303 	umull	r2, r3, r2, r3
- 8002626:	095b      	lsrs	r3, r3, #5
- 8002628:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
- 800262c:	441c      	add	r4, r3
- 800262e:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
- 8002632:	2200      	movs	r2, #0
- 8002634:	673b      	str	r3, [r7, #112]	; 0x70
- 8002636:	677a      	str	r2, [r7, #116]	; 0x74
- 8002638:	e9d7 891c 	ldrd	r8, r9, [r7, #112]	; 0x70
- 800263c:	4642      	mov	r2, r8
- 800263e:	464b      	mov	r3, r9
- 8002640:	1891      	adds	r1, r2, r2
- 8002642:	60b9      	str	r1, [r7, #8]
- 8002644:	415b      	adcs	r3, r3
- 8002646:	60fb      	str	r3, [r7, #12]
- 8002648:	e9d7 2302 	ldrd	r2, r3, [r7, #8]
- 800264c:	4641      	mov	r1, r8
- 800264e:	1851      	adds	r1, r2, r1
- 8002650:	6039      	str	r1, [r7, #0]
- 8002652:	4649      	mov	r1, r9
- 8002654:	414b      	adcs	r3, r1
- 8002656:	607b      	str	r3, [r7, #4]
- 8002658:	f04f 0200 	mov.w	r2, #0
- 800265c:	f04f 0300 	mov.w	r3, #0
- 8002660:	e9d7 ab00 	ldrd	sl, fp, [r7]
- 8002664:	4659      	mov	r1, fp
- 8002666:	00cb      	lsls	r3, r1, #3
- 8002668:	4651      	mov	r1, sl
- 800266a:	ea43 7351 	orr.w	r3, r3, r1, lsr #29
- 800266e:	4651      	mov	r1, sl
- 8002670:	00ca      	lsls	r2, r1, #3
- 8002672:	4610      	mov	r0, r2
- 8002674:	4619      	mov	r1, r3
- 8002676:	4603      	mov	r3, r0
- 8002678:	4642      	mov	r2, r8
- 800267a:	189b      	adds	r3, r3, r2
- 800267c:	66bb      	str	r3, [r7, #104]	; 0x68
- 800267e:	464b      	mov	r3, r9
- 8002680:	460a      	mov	r2, r1
- 8002682:	eb42 0303 	adc.w	r3, r2, r3
- 8002686:	66fb      	str	r3, [r7, #108]	; 0x6c
- 8002688:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 800268c:	685b      	ldr	r3, [r3, #4]
- 800268e:	2200      	movs	r2, #0
- 8002690:	663b      	str	r3, [r7, #96]	; 0x60
- 8002692:	667a      	str	r2, [r7, #100]	; 0x64
- 8002694:	f04f 0200 	mov.w	r2, #0
- 8002698:	f04f 0300 	mov.w	r3, #0
- 800269c:	e9d7 8918 	ldrd	r8, r9, [r7, #96]	; 0x60
- 80026a0:	4649      	mov	r1, r9
- 80026a2:	008b      	lsls	r3, r1, #2
- 80026a4:	4641      	mov	r1, r8
- 80026a6:	ea43 7391 	orr.w	r3, r3, r1, lsr #30
- 80026aa:	4641      	mov	r1, r8
- 80026ac:	008a      	lsls	r2, r1, #2
- 80026ae:	e9d7 011a 	ldrd	r0, r1, [r7, #104]	; 0x68
- 80026b2:	f7fd fd89 	bl	80001c8 <__aeabi_uldivmod>
- 80026b6:	4602      	mov	r2, r0
- 80026b8:	460b      	mov	r3, r1
- 80026ba:	4b0d      	ldr	r3, [pc, #52]	; (80026f0 <UART_SetConfig+0x4e4>)
- 80026bc:	fba3 1302 	umull	r1, r3, r3, r2
- 80026c0:	095b      	lsrs	r3, r3, #5
- 80026c2:	2164      	movs	r1, #100	; 0x64
- 80026c4:	fb01 f303 	mul.w	r3, r1, r3
- 80026c8:	1ad3      	subs	r3, r2, r3
- 80026ca:	011b      	lsls	r3, r3, #4
- 80026cc:	3332      	adds	r3, #50	; 0x32
- 80026ce:	4a08      	ldr	r2, [pc, #32]	; (80026f0 <UART_SetConfig+0x4e4>)
- 80026d0:	fba2 2303 	umull	r2, r3, r2, r3
- 80026d4:	095b      	lsrs	r3, r3, #5
- 80026d6:	f003 020f 	and.w	r2, r3, #15
- 80026da:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
- 80026de:	681b      	ldr	r3, [r3, #0]
- 80026e0:	4422      	add	r2, r4
- 80026e2:	609a      	str	r2, [r3, #8]
-}
- 80026e4:	bf00      	nop
- 80026e6:	f507 7780 	add.w	r7, r7, #256	; 0x100
- 80026ea:	46bd      	mov	sp, r7
- 80026ec:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
- 80026f0:	51eb851f 	.word	0x51eb851f
-
-080026f4 <_ZN3sta17CanPendingRxFifosC1Emh>:
-        return ( (rxFlags_ >> idx_) & 0x1 );
-    }
-
-
-
-    CanPendingRxFifos::CanPendingRxFifos(uint32_t rxFlags, uint8_t numFifos)
- 80026f4:	b480      	push	{r7}
- 80026f6:	b085      	sub	sp, #20
- 80026f8:	af00      	add	r7, sp, #0
- 80026fa:	60f8      	str	r0, [r7, #12]
- 80026fc:	60b9      	str	r1, [r7, #8]
- 80026fe:	4613      	mov	r3, r2
- 8002700:	71fb      	strb	r3, [r7, #7]
-        : rxFlags_{rxFlags}, numFifos_{numFifos}
- 8002702:	68fb      	ldr	r3, [r7, #12]
- 8002704:	68ba      	ldr	r2, [r7, #8]
- 8002706:	601a      	str	r2, [r3, #0]
- 8002708:	68fb      	ldr	r3, [r7, #12]
- 800270a:	79fa      	ldrb	r2, [r7, #7]
- 800270c:	711a      	strb	r2, [r3, #4]
-    {}
- 800270e:	68fb      	ldr	r3, [r7, #12]
- 8002710:	4618      	mov	r0, r3
- 8002712:	3714      	adds	r7, #20
- 8002714:	46bd      	mov	sp, r7
- 8002716:	f85d 7b04 	ldr.w	r7, [sp], #4
- 800271a:	4770      	bx	lr
-
-0800271c <_ZN3sta13assert_failedEPKcS1_m>:
-
-namespace sta
-{
-    STA_WEAK
-    void assert_failed(const char * expr, const char * file, uint32_t line)
-    {
- 800271c:	b480      	push	{r7}
- 800271e:	b085      	sub	sp, #20
- 8002720:	af00      	add	r7, sp, #0
- 8002722:	60f8      	str	r0, [r7, #12]
- 8002724:	60b9      	str	r1, [r7, #8]
- 8002726:	607a      	str	r2, [r7, #4]
-        STA_DEBUG_PRINT(file);
-        STA_DEBUG_PRINT(':');
-        STA_DEBUG_PRINT(line);
-        STA_DEBUG_PRINT(": Assertion failed: ");
-        STA_DEBUG_PRINTLN(expr);
-    }
- 8002728:	bf00      	nop
- 800272a:	3714      	adds	r7, #20
- 800272c:	46bd      	mov	sp, r7
- 800272e:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8002732:	4770      	bx	lr
-
-08002734 <_ZN3sta11assert_haltEv>:
-
-    STA_WEAK
-    void assert_halt()
-    {
- 8002734:	b480      	push	{r7}
- 8002736:	af00      	add	r7, sp, #0
-        STA_BKPT();
- 8002738:	be00      	bkpt	0x0000
-        while (true);
- 800273a:	e7fe      	b.n	800273a <_ZN3sta11assert_haltEv+0x6>
-
-0800273c <_ZN3sta13CanControllerC1Ev>:
-    /**
-     * @brief CAN controller driver interface.
-     *
-     * @ingroup sta_core_can
-     */
-    class CanController
- 800273c:	b480      	push	{r7}
- 800273e:	b083      	sub	sp, #12
- 8002740:	af00      	add	r7, sp, #0
- 8002742:	6078      	str	r0, [r7, #4]
- 8002744:	4a04      	ldr	r2, [pc, #16]	; (8002758 <_ZN3sta13CanControllerC1Ev+0x1c>)
- 8002746:	687b      	ldr	r3, [r7, #4]
- 8002748:	601a      	str	r2, [r3, #0]
- 800274a:	687b      	ldr	r3, [r7, #4]
- 800274c:	4618      	mov	r0, r3
- 800274e:	370c      	adds	r7, #12
- 8002750:	46bd      	mov	sp, r7
- 8002752:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8002756:	4770      	bx	lr
- 8002758:	08002c70 	.word	0x08002c70
-
-0800275c <_ZN3sta18STM32CanControllerC1EP19__CAN_HandleTypeDef>:
-#include <sta/lang.hpp>
-
-
-namespace sta
-{
-    STM32CanController::STM32CanController(CAN_HandleTypeDef * handle)
- 800275c:	b580      	push	{r7, lr}
- 800275e:	b082      	sub	sp, #8
- 8002760:	af00      	add	r7, sp, #0
- 8002762:	6078      	str	r0, [r7, #4]
- 8002764:	6039      	str	r1, [r7, #0]
-        : handle_{handle}
- 8002766:	687b      	ldr	r3, [r7, #4]
- 8002768:	4618      	mov	r0, r3
- 800276a:	f7ff ffe7 	bl	800273c <_ZN3sta13CanControllerC1Ev>
- 800276e:	4a07      	ldr	r2, [pc, #28]	; (800278c <_ZN3sta18STM32CanControllerC1EP19__CAN_HandleTypeDef+0x30>)
- 8002770:	687b      	ldr	r3, [r7, #4]
- 8002772:	601a      	str	r2, [r3, #0]
- 8002774:	687b      	ldr	r3, [r7, #4]
- 8002776:	683a      	ldr	r2, [r7, #0]
- 8002778:	605a      	str	r2, [r3, #4]
-    {
-        initFilters();
- 800277a:	6878      	ldr	r0, [r7, #4]
- 800277c:	f000 f98f 	bl	8002a9e <_ZN3sta18STM32CanController11initFiltersEv>
-    }
- 8002780:	687b      	ldr	r3, [r7, #4]
- 8002782:	4618      	mov	r0, r3
- 8002784:	3708      	adds	r7, #8
- 8002786:	46bd      	mov	sp, r7
- 8002788:	bd80      	pop	{r7, pc}
- 800278a:	bf00      	nop
- 800278c:	08002c3c 	.word	0x08002c3c
-
-08002790 <_ZN3sta18STM32CanController5startEv>:
-        );
-    }
-
-
-    void STM32CanController::start()
-    {
- 8002790:	b580      	push	{r7, lr}
- 8002792:	b082      	sub	sp, #8
- 8002794:	af00      	add	r7, sp, #0
- 8002796:	6078      	str	r0, [r7, #4]
-        HAL_CAN_Start(handle_);
- 8002798:	687b      	ldr	r3, [r7, #4]
- 800279a:	685b      	ldr	r3, [r3, #4]
- 800279c:	4618      	mov	r0, r3
- 800279e:	f7fe fb7f 	bl	8000ea0 <HAL_CAN_Start>
-    }
- 80027a2:	bf00      	nop
- 80027a4:	3708      	adds	r7, #8
- 80027a6:	46bd      	mov	sp, r7
- 80027a8:	bd80      	pop	{r7, pc}
-	...
-
-080027ac <_ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh>:
-        HAL_CAN_Stop(handle_);
-    }
-
-
-    bool STM32CanController::sendFrame(const CanTxHeader & header, const uint8_t * payload)
-    {
- 80027ac:	b580      	push	{r7, lr}
- 80027ae:	b08c      	sub	sp, #48	; 0x30
- 80027b0:	af00      	add	r7, sp, #0
- 80027b2:	60f8      	str	r0, [r7, #12]
- 80027b4:	60b9      	str	r1, [r7, #8]
- 80027b6:	607a      	str	r2, [r7, #4]
-        STA_ASSERT_MSG(header.payloadLength <= 8, "CAN 2.0B payload size exceeded");
- 80027b8:	68bb      	ldr	r3, [r7, #8]
- 80027ba:	7b1b      	ldrb	r3, [r3, #12]
- 80027bc:	2b08      	cmp	r3, #8
- 80027be:	d906      	bls.n	80027ce <_ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh+0x22>
- 80027c0:	2226      	movs	r2, #38	; 0x26
- 80027c2:	491a      	ldr	r1, [pc, #104]	; (800282c <_ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh+0x80>)
- 80027c4:	481a      	ldr	r0, [pc, #104]	; (8002830 <_ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh+0x84>)
- 80027c6:	f7ff ffa9 	bl	800271c <_ZN3sta13assert_failedEPKcS1_m>
- 80027ca:	f7ff ffb3 	bl	8002734 <_ZN3sta11assert_haltEv>
-
-        CAN_TxHeaderTypeDef halHeader;
-
-        if (header.id.format == CanIdFormat::STD)
- 80027ce:	68bb      	ldr	r3, [r7, #8]
- 80027d0:	781b      	ldrb	r3, [r3, #0]
- 80027d2:	2b00      	cmp	r3, #0
- 80027d4:	d107      	bne.n	80027e6 <_ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh+0x3a>
-        {
-            halHeader.StdId = header.id.sid & 0x7FF;
- 80027d6:	68bb      	ldr	r3, [r7, #8]
- 80027d8:	685b      	ldr	r3, [r3, #4]
- 80027da:	f3c3 030a 	ubfx	r3, r3, #0, #11
- 80027de:	61bb      	str	r3, [r7, #24]
-            halHeader.IDE   = CAN_ID_STD;
- 80027e0:	2300      	movs	r3, #0
- 80027e2:	623b      	str	r3, [r7, #32]
- 80027e4:	e00c      	b.n	8002800 <_ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh+0x54>
-        }
-        else
-        {
-            // Combine SID and EID
-            halHeader.ExtId = ((header.id.sid & 0x7FF) << 18) | (header.id.eid & 0x3FFFF);
- 80027e6:	68bb      	ldr	r3, [r7, #8]
- 80027e8:	685b      	ldr	r3, [r3, #4]
- 80027ea:	049a      	lsls	r2, r3, #18
- 80027ec:	4b11      	ldr	r3, [pc, #68]	; (8002834 <_ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh+0x88>)
- 80027ee:	4013      	ands	r3, r2
- 80027f0:	68ba      	ldr	r2, [r7, #8]
- 80027f2:	6892      	ldr	r2, [r2, #8]
- 80027f4:	f3c2 0211 	ubfx	r2, r2, #0, #18
- 80027f8:	4313      	orrs	r3, r2
- 80027fa:	61fb      	str	r3, [r7, #28]
-            halHeader.IDE   = CAN_ID_EXT;
- 80027fc:	2304      	movs	r3, #4
- 80027fe:	623b      	str	r3, [r7, #32]
-        }
-
-        halHeader.DLC = header.payloadLength;
- 8002800:	68bb      	ldr	r3, [r7, #8]
- 8002802:	7b1b      	ldrb	r3, [r3, #12]
- 8002804:	62bb      	str	r3, [r7, #40]	; 0x28
-
-        uint32_t mailbox; // Don't care
-        return (HAL_OK == HAL_CAN_AddTxMessage(handle_, &halHeader, const_cast<uint8_t *>(payload), &mailbox));
- 8002806:	68fb      	ldr	r3, [r7, #12]
- 8002808:	6858      	ldr	r0, [r3, #4]
- 800280a:	f107 0314 	add.w	r3, r7, #20
- 800280e:	f107 0118 	add.w	r1, r7, #24
- 8002812:	687a      	ldr	r2, [r7, #4]
- 8002814:	f7fe fb88 	bl	8000f28 <HAL_CAN_AddTxMessage>
- 8002818:	4603      	mov	r3, r0
- 800281a:	2b00      	cmp	r3, #0
- 800281c:	bf0c      	ite	eq
- 800281e:	2301      	moveq	r3, #1
- 8002820:	2300      	movne	r3, #0
- 8002822:	b2db      	uxtb	r3, r3
-    }
- 8002824:	4618      	mov	r0, r3
- 8002826:	3730      	adds	r7, #48	; 0x30
- 8002828:	46bd      	mov	sp, r7
- 800282a:	bd80      	pop	{r7, pc}
- 800282c:	08002bd0 	.word	0x08002bd0
- 8002830:	08002bfc 	.word	0x08002bfc
- 8002834:	1ffc0000 	.word	0x1ffc0000
-
-08002838 <_ZN3sta18STM32CanController12receiveFrameEhPNS_11CanRxHeaderEPh>:
-
-    bool STM32CanController::receiveFrame(uint8_t fifo, CanRxHeader * header, uint8_t * payload)
-    {
- 8002838:	b580      	push	{r7, lr}
- 800283a:	b08c      	sub	sp, #48	; 0x30
- 800283c:	af00      	add	r7, sp, #0
- 800283e:	60f8      	str	r0, [r7, #12]
- 8002840:	607a      	str	r2, [r7, #4]
- 8002842:	603b      	str	r3, [r7, #0]
- 8002844:	460b      	mov	r3, r1
- 8002846:	72fb      	strb	r3, [r7, #11]
-        // Check if message is available
-        if (HAL_CAN_GetRxFifoFillLevel(handle_, fifo) == 0)
- 8002848:	68fb      	ldr	r3, [r7, #12]
- 800284a:	685b      	ldr	r3, [r3, #4]
- 800284c:	7afa      	ldrb	r2, [r7, #11]
- 800284e:	4611      	mov	r1, r2
- 8002850:	4618      	mov	r0, r3
- 8002852:	f7fe fd56 	bl	8001302 <HAL_CAN_GetRxFifoFillLevel>
- 8002856:	4603      	mov	r3, r0
- 8002858:	2b00      	cmp	r3, #0
- 800285a:	bf0c      	ite	eq
- 800285c:	2301      	moveq	r3, #1
- 800285e:	2300      	movne	r3, #0
- 8002860:	b2db      	uxtb	r3, r3
- 8002862:	2b00      	cmp	r3, #0
- 8002864:	d001      	beq.n	800286a <_ZN3sta18STM32CanController12receiveFrameEhPNS_11CanRxHeaderEPh+0x32>
-            return false;
- 8002866:	2300      	movs	r3, #0
- 8002868:	e02c      	b.n	80028c4 <_ZN3sta18STM32CanController12receiveFrameEhPNS_11CanRxHeaderEPh+0x8c>
-
-        // Retrieve message
-        CAN_RxHeaderTypeDef halHeader;
-        HAL_CAN_GetRxMessage(handle_, fifo, &halHeader, payload);
- 800286a:	68fb      	ldr	r3, [r7, #12]
- 800286c:	6858      	ldr	r0, [r3, #4]
- 800286e:	7af9      	ldrb	r1, [r7, #11]
- 8002870:	f107 0214 	add.w	r2, r7, #20
- 8002874:	683b      	ldr	r3, [r7, #0]
- 8002876:	f7fe fc32 	bl	80010de <HAL_CAN_GetRxMessage>
-
-        if (halHeader.IDE == CAN_ID_STD)
- 800287a:	69fb      	ldr	r3, [r7, #28]
- 800287c:	2b00      	cmp	r3, #0
- 800287e:	d109      	bne.n	8002894 <_ZN3sta18STM32CanController12receiveFrameEhPNS_11CanRxHeaderEPh+0x5c>
-        {
-            header->id.format   = CanIdFormat::STD;
- 8002880:	687b      	ldr	r3, [r7, #4]
- 8002882:	2200      	movs	r2, #0
- 8002884:	701a      	strb	r2, [r3, #0]
-            header->id.sid      = halHeader.StdId;
- 8002886:	697a      	ldr	r2, [r7, #20]
- 8002888:	687b      	ldr	r3, [r7, #4]
- 800288a:	605a      	str	r2, [r3, #4]
-            header->id.eid      = 0;
- 800288c:	687b      	ldr	r3, [r7, #4]
- 800288e:	2200      	movs	r2, #0
- 8002890:	609a      	str	r2, [r3, #8]
- 8002892:	e00b      	b.n	80028ac <_ZN3sta18STM32CanController12receiveFrameEhPNS_11CanRxHeaderEPh+0x74>
-        }
-        else
-        {
-            header->id.format   = CanIdFormat::EXT;
- 8002894:	687b      	ldr	r3, [r7, #4]
- 8002896:	2201      	movs	r2, #1
- 8002898:	701a      	strb	r2, [r3, #0]
-            // Separate SID and EID
-            header->id.sid      = (halHeader.ExtId >> 18);
- 800289a:	69bb      	ldr	r3, [r7, #24]
- 800289c:	0c9a      	lsrs	r2, r3, #18
- 800289e:	687b      	ldr	r3, [r7, #4]
- 80028a0:	605a      	str	r2, [r3, #4]
-            header->id.eid      = halHeader.ExtId & 0x3FFFF;
- 80028a2:	69bb      	ldr	r3, [r7, #24]
- 80028a4:	f3c3 0211 	ubfx	r2, r3, #0, #18
- 80028a8:	687b      	ldr	r3, [r7, #4]
- 80028aa:	609a      	str	r2, [r3, #8]
-        }
-        // No conversion required for CAN 2B standard
-        header->payloadLength  = halHeader.DLC;
- 80028ac:	6a7b      	ldr	r3, [r7, #36]	; 0x24
- 80028ae:	b2da      	uxtb	r2, r3
- 80028b0:	687b      	ldr	r3, [r7, #4]
- 80028b2:	731a      	strb	r2, [r3, #12]
-        header->timestamp      = halHeader.Timestamp;
- 80028b4:	6aba      	ldr	r2, [r7, #40]	; 0x28
- 80028b6:	687b      	ldr	r3, [r7, #4]
- 80028b8:	611a      	str	r2, [r3, #16]
-        header->filter         = halHeader.FilterMatchIndex;
- 80028ba:	6afb      	ldr	r3, [r7, #44]	; 0x2c
- 80028bc:	b2da      	uxtb	r2, r3
- 80028be:	687b      	ldr	r3, [r7, #4]
- 80028c0:	751a      	strb	r2, [r3, #20]
-
-        return true;
- 80028c2:	2301      	movs	r3, #1
-    }
- 80028c4:	4618      	mov	r0, r3
- 80028c6:	3730      	adds	r7, #48	; 0x30
- 80028c8:	46bd      	mov	sp, r7
- 80028ca:	bd80      	pop	{r7, pc}
-
-080028cc <_ZN3sta18STM32CanController14getRxFifoFlagsEv>:
-
-    uint32_t STM32CanController::getRxFifoFlags()
-    {
- 80028cc:	b590      	push	{r4, r7, lr}
- 80028ce:	b083      	sub	sp, #12
- 80028d0:	af00      	add	r7, sp, #0
- 80028d2:	6078      	str	r0, [r7, #4]
-        //
-        return (HAL_CAN_GetRxFifoFillLevel(handle_, CAN_RX_FIFO0) != 0)
- 80028d4:	687b      	ldr	r3, [r7, #4]
- 80028d6:	685b      	ldr	r3, [r3, #4]
- 80028d8:	2100      	movs	r1, #0
- 80028da:	4618      	mov	r0, r3
- 80028dc:	f7fe fd11 	bl	8001302 <HAL_CAN_GetRxFifoFillLevel>
- 80028e0:	4603      	mov	r3, r0
- 80028e2:	2b00      	cmp	r3, #0
- 80028e4:	bf14      	ite	ne
- 80028e6:	2301      	movne	r3, #1
- 80028e8:	2300      	moveq	r3, #0
- 80028ea:	b2db      	uxtb	r3, r3
- 80028ec:	461c      	mov	r4, r3
-                | (HAL_CAN_GetRxFifoFillLevel(handle_, CAN_RX_FIFO1) != 0) << 1;
- 80028ee:	687b      	ldr	r3, [r7, #4]
- 80028f0:	685b      	ldr	r3, [r3, #4]
- 80028f2:	2101      	movs	r1, #1
- 80028f4:	4618      	mov	r0, r3
- 80028f6:	f7fe fd04 	bl	8001302 <HAL_CAN_GetRxFifoFillLevel>
- 80028fa:	4603      	mov	r3, r0
- 80028fc:	2b00      	cmp	r3, #0
- 80028fe:	d001      	beq.n	8002904 <_ZN3sta18STM32CanController14getRxFifoFlagsEv+0x38>
- 8002900:	2302      	movs	r3, #2
- 8002902:	e000      	b.n	8002906 <_ZN3sta18STM32CanController14getRxFifoFlagsEv+0x3a>
- 8002904:	2300      	movs	r3, #0
- 8002906:	4323      	orrs	r3, r4
-    }
- 8002908:	4618      	mov	r0, r3
- 800290a:	370c      	adds	r7, #12
- 800290c:	46bd      	mov	sp, r7
- 800290e:	bd90      	pop	{r4, r7, pc}
-
-08002910 <_ZN3sta18STM32CanController15configureFilterEhRKNS_9CanFilterEb>:
-
-
-    void STM32CanController::configureFilter(uint8_t idx, const CanFilter & filter, bool active /* = false */)
-    {
- 8002910:	b580      	push	{r7, lr}
- 8002912:	b086      	sub	sp, #24
- 8002914:	af00      	add	r7, sp, #0
- 8002916:	60f8      	str	r0, [r7, #12]
- 8002918:	607a      	str	r2, [r7, #4]
- 800291a:	461a      	mov	r2, r3
- 800291c:	460b      	mov	r3, r1
- 800291e:	72fb      	strb	r3, [r7, #11]
- 8002920:	4613      	mov	r3, r2
- 8002922:	72bb      	strb	r3, [r7, #10]
-        CAN_FilterTypeDef * config = &filters_[idx];
- 8002924:	7afa      	ldrb	r2, [r7, #11]
- 8002926:	4613      	mov	r3, r2
- 8002928:	009b      	lsls	r3, r3, #2
- 800292a:	4413      	add	r3, r2
- 800292c:	00db      	lsls	r3, r3, #3
- 800292e:	3308      	adds	r3, #8
- 8002930:	68fa      	ldr	r2, [r7, #12]
- 8002932:	4413      	add	r3, r2
- 8002934:	617b      	str	r3, [r7, #20]
-
-        if (filter.type == CanFilterIdFormat::STD)
- 8002936:	687b      	ldr	r3, [r7, #4]
- 8002938:	691b      	ldr	r3, [r3, #16]
- 800293a:	2b01      	cmp	r3, #1
- 800293c:	d112      	bne.n	8002964 <_ZN3sta18STM32CanController15configureFilterEhRKNS_9CanFilterEb+0x54>
-        {
-            config->FilterIdHigh        = 0;
- 800293e:	697b      	ldr	r3, [r7, #20]
- 8002940:	2200      	movs	r2, #0
- 8002942:	601a      	str	r2, [r3, #0]
-            config->FilterIdLow         = filter.obj.sid & 0x7FF;
- 8002944:	687b      	ldr	r3, [r7, #4]
- 8002946:	681b      	ldr	r3, [r3, #0]
- 8002948:	f3c3 020a 	ubfx	r2, r3, #0, #11
- 800294c:	697b      	ldr	r3, [r7, #20]
- 800294e:	605a      	str	r2, [r3, #4]
-            config->FilterMaskIdHigh    = 0;
- 8002950:	697b      	ldr	r3, [r7, #20]
- 8002952:	2200      	movs	r2, #0
- 8002954:	609a      	str	r2, [r3, #8]
-            config->FilterMaskIdLow     = filter.mask.sid & 0x7FF;
- 8002956:	687b      	ldr	r3, [r7, #4]
- 8002958:	689b      	ldr	r3, [r3, #8]
- 800295a:	f3c3 020a 	ubfx	r2, r3, #0, #11
- 800295e:	697b      	ldr	r3, [r7, #20]
- 8002960:	60da      	str	r2, [r3, #12]
- 8002962:	e025      	b.n	80029b0 <_ZN3sta18STM32CanController15configureFilterEhRKNS_9CanFilterEb+0xa0>
-        }
-        else
-        {
-            config->FilterIdHigh        = ((filter.obj.sid & 0x7FF) << 2) | ((filter.obj.eid >> 16) & 0x3);
- 8002964:	687b      	ldr	r3, [r7, #4]
- 8002966:	681b      	ldr	r3, [r3, #0]
- 8002968:	009a      	lsls	r2, r3, #2
- 800296a:	f641 73fc 	movw	r3, #8188	; 0x1ffc
- 800296e:	4013      	ands	r3, r2
- 8002970:	687a      	ldr	r2, [r7, #4]
- 8002972:	6852      	ldr	r2, [r2, #4]
- 8002974:	0c12      	lsrs	r2, r2, #16
- 8002976:	f002 0203 	and.w	r2, r2, #3
- 800297a:	431a      	orrs	r2, r3
- 800297c:	697b      	ldr	r3, [r7, #20]
- 800297e:	601a      	str	r2, [r3, #0]
-            config->FilterIdLow         = filter.obj.eid & 0xFFFF;
- 8002980:	687b      	ldr	r3, [r7, #4]
- 8002982:	685b      	ldr	r3, [r3, #4]
- 8002984:	b29a      	uxth	r2, r3
- 8002986:	697b      	ldr	r3, [r7, #20]
- 8002988:	605a      	str	r2, [r3, #4]
-            config->FilterMaskIdHigh    = ((filter.mask.sid & 0x7FF) << 2) | ((filter.mask.eid >> 16) & 0x3);
- 800298a:	687b      	ldr	r3, [r7, #4]
- 800298c:	689b      	ldr	r3, [r3, #8]
- 800298e:	009a      	lsls	r2, r3, #2
- 8002990:	f641 73fc 	movw	r3, #8188	; 0x1ffc
- 8002994:	4013      	ands	r3, r2
- 8002996:	687a      	ldr	r2, [r7, #4]
- 8002998:	68d2      	ldr	r2, [r2, #12]
- 800299a:	0c12      	lsrs	r2, r2, #16
- 800299c:	f002 0203 	and.w	r2, r2, #3
- 80029a0:	431a      	orrs	r2, r3
- 80029a2:	697b      	ldr	r3, [r7, #20]
- 80029a4:	609a      	str	r2, [r3, #8]
-            config->FilterMaskIdLow     = filter.mask.eid & 0xFFFF;
- 80029a6:	687b      	ldr	r3, [r7, #4]
- 80029a8:	68db      	ldr	r3, [r3, #12]
- 80029aa:	b29a      	uxth	r2, r3
- 80029ac:	697b      	ldr	r3, [r7, #20]
- 80029ae:	60da      	str	r2, [r3, #12]
-        }
-
-        config->FilterFIFOAssignment    = filter.fifo;
- 80029b0:	687b      	ldr	r3, [r7, #4]
- 80029b2:	7d1b      	ldrb	r3, [r3, #20]
- 80029b4:	461a      	mov	r2, r3
- 80029b6:	697b      	ldr	r3, [r7, #20]
- 80029b8:	611a      	str	r2, [r3, #16]
-        config->FilterActivation        = (active ? CAN_FILTER_ENABLE : CAN_FILTER_DISABLE);
- 80029ba:	7abb      	ldrb	r3, [r7, #10]
- 80029bc:	2b00      	cmp	r3, #0
- 80029be:	d001      	beq.n	80029c4 <_ZN3sta18STM32CanController15configureFilterEhRKNS_9CanFilterEb+0xb4>
- 80029c0:	2201      	movs	r2, #1
- 80029c2:	e000      	b.n	80029c6 <_ZN3sta18STM32CanController15configureFilterEhRKNS_9CanFilterEb+0xb6>
- 80029c4:	2200      	movs	r2, #0
- 80029c6:	697b      	ldr	r3, [r7, #20]
- 80029c8:	621a      	str	r2, [r3, #32]
-
-        HAL_CAN_ConfigFilter(handle_, config);
- 80029ca:	68fb      	ldr	r3, [r7, #12]
- 80029cc:	685b      	ldr	r3, [r3, #4]
- 80029ce:	6979      	ldr	r1, [r7, #20]
- 80029d0:	4618      	mov	r0, r3
- 80029d2:	f7fe f985 	bl	8000ce0 <HAL_CAN_ConfigFilter>
-    }
- 80029d6:	bf00      	nop
- 80029d8:	3718      	adds	r7, #24
- 80029da:	46bd      	mov	sp, r7
- 80029dc:	bd80      	pop	{r7, pc}
-
-080029de <_ZN3sta18STM32CanController12enableFilterEh>:
-
-    void STM32CanController::enableFilter(uint8_t idx)
-    {
- 80029de:	b580      	push	{r7, lr}
- 80029e0:	b084      	sub	sp, #16
- 80029e2:	af00      	add	r7, sp, #0
- 80029e4:	6078      	str	r0, [r7, #4]
- 80029e6:	460b      	mov	r3, r1
- 80029e8:	70fb      	strb	r3, [r7, #3]
-        CAN_FilterTypeDef * config = &filters_[idx];
- 80029ea:	78fa      	ldrb	r2, [r7, #3]
- 80029ec:	4613      	mov	r3, r2
- 80029ee:	009b      	lsls	r3, r3, #2
- 80029f0:	4413      	add	r3, r2
- 80029f2:	00db      	lsls	r3, r3, #3
- 80029f4:	3308      	adds	r3, #8
- 80029f6:	687a      	ldr	r2, [r7, #4]
- 80029f8:	4413      	add	r3, r2
- 80029fa:	60fb      	str	r3, [r7, #12]
-
-        config->FilterActivation = CAN_FILTER_ENABLE;
- 80029fc:	68fb      	ldr	r3, [r7, #12]
- 80029fe:	2201      	movs	r2, #1
- 8002a00:	621a      	str	r2, [r3, #32]
-
-        HAL_CAN_ConfigFilter(handle_, config);
- 8002a02:	687b      	ldr	r3, [r7, #4]
- 8002a04:	685b      	ldr	r3, [r3, #4]
- 8002a06:	68f9      	ldr	r1, [r7, #12]
- 8002a08:	4618      	mov	r0, r3
- 8002a0a:	f7fe f969 	bl	8000ce0 <HAL_CAN_ConfigFilter>
-    }
- 8002a0e:	bf00      	nop
- 8002a10:	3710      	adds	r7, #16
- 8002a12:	46bd      	mov	sp, r7
- 8002a14:	bd80      	pop	{r7, pc}
-
-08002a16 <_ZN3sta18STM32CanController13disableFilterEh>:
-
-    void STM32CanController::disableFilter(uint8_t idx)
-    {
- 8002a16:	b580      	push	{r7, lr}
- 8002a18:	b084      	sub	sp, #16
- 8002a1a:	af00      	add	r7, sp, #0
- 8002a1c:	6078      	str	r0, [r7, #4]
- 8002a1e:	460b      	mov	r3, r1
- 8002a20:	70fb      	strb	r3, [r7, #3]
-        CAN_FilterTypeDef * config = &filters_[idx];
- 8002a22:	78fa      	ldrb	r2, [r7, #3]
- 8002a24:	4613      	mov	r3, r2
- 8002a26:	009b      	lsls	r3, r3, #2
- 8002a28:	4413      	add	r3, r2
- 8002a2a:	00db      	lsls	r3, r3, #3
- 8002a2c:	3308      	adds	r3, #8
- 8002a2e:	687a      	ldr	r2, [r7, #4]
- 8002a30:	4413      	add	r3, r2
- 8002a32:	60fb      	str	r3, [r7, #12]
-
-        config->FilterActivation = CAN_FILTER_DISABLE;
- 8002a34:	68fb      	ldr	r3, [r7, #12]
- 8002a36:	2200      	movs	r2, #0
- 8002a38:	621a      	str	r2, [r3, #32]
-
-        HAL_CAN_ConfigFilter(handle_, config);
- 8002a3a:	687b      	ldr	r3, [r7, #4]
- 8002a3c:	685b      	ldr	r3, [r3, #4]
- 8002a3e:	68f9      	ldr	r1, [r7, #12]
- 8002a40:	4618      	mov	r0, r3
- 8002a42:	f7fe f94d 	bl	8000ce0 <HAL_CAN_ConfigFilter>
-    }
- 8002a46:	bf00      	nop
- 8002a48:	3710      	adds	r7, #16
- 8002a4a:	46bd      	mov	sp, r7
- 8002a4c:	bd80      	pop	{r7, pc}
-
-08002a4e <_ZN3sta18STM32CanController12clearFiltersEv>:
-
-    void STM32CanController::clearFilters()
-    {
- 8002a4e:	b580      	push	{r7, lr}
- 8002a50:	b084      	sub	sp, #16
- 8002a52:	af00      	add	r7, sp, #0
- 8002a54:	6078      	str	r0, [r7, #4]
-        for (uint32_t i = 0; i < MAX_FILTER_COUNT; ++i)
- 8002a56:	2300      	movs	r3, #0
- 8002a58:	60fb      	str	r3, [r7, #12]
- 8002a5a:	e018      	b.n	8002a8e <_ZN3sta18STM32CanController12clearFiltersEv+0x40>
-        {
-            CAN_FilterTypeDef * config = &filters_[i];
- 8002a5c:	68fa      	ldr	r2, [r7, #12]
- 8002a5e:	4613      	mov	r3, r2
- 8002a60:	009b      	lsls	r3, r3, #2
- 8002a62:	4413      	add	r3, r2
- 8002a64:	00db      	lsls	r3, r3, #3
- 8002a66:	3308      	adds	r3, #8
- 8002a68:	687a      	ldr	r2, [r7, #4]
- 8002a6a:	4413      	add	r3, r2
- 8002a6c:	60bb      	str	r3, [r7, #8]
-
-            // Only disable active filters
-            if (config->FilterActivation == CAN_FILTER_ENABLE)
- 8002a6e:	68bb      	ldr	r3, [r7, #8]
- 8002a70:	6a1b      	ldr	r3, [r3, #32]
- 8002a72:	2b01      	cmp	r3, #1
- 8002a74:	d108      	bne.n	8002a88 <_ZN3sta18STM32CanController12clearFiltersEv+0x3a>
-            {
-                config->FilterActivation = CAN_FILTER_DISABLE;
- 8002a76:	68bb      	ldr	r3, [r7, #8]
- 8002a78:	2200      	movs	r2, #0
- 8002a7a:	621a      	str	r2, [r3, #32]
-                HAL_CAN_ConfigFilter(handle_, config);
- 8002a7c:	687b      	ldr	r3, [r7, #4]
- 8002a7e:	685b      	ldr	r3, [r3, #4]
- 8002a80:	68b9      	ldr	r1, [r7, #8]
- 8002a82:	4618      	mov	r0, r3
- 8002a84:	f7fe f92c 	bl	8000ce0 <HAL_CAN_ConfigFilter>
-        for (uint32_t i = 0; i < MAX_FILTER_COUNT; ++i)
- 8002a88:	68fb      	ldr	r3, [r7, #12]
- 8002a8a:	3301      	adds	r3, #1
- 8002a8c:	60fb      	str	r3, [r7, #12]
- 8002a8e:	68fb      	ldr	r3, [r7, #12]
- 8002a90:	2b0d      	cmp	r3, #13
- 8002a92:	d9e3      	bls.n	8002a5c <_ZN3sta18STM32CanController12clearFiltersEv+0xe>
-            }
-        }
-    }
- 8002a94:	bf00      	nop
- 8002a96:	bf00      	nop
- 8002a98:	3710      	adds	r7, #16
- 8002a9a:	46bd      	mov	sp, r7
- 8002a9c:	bd80      	pop	{r7, pc}
-
-08002a9e <_ZN3sta18STM32CanController11initFiltersEv>:
-
-
-    void STM32CanController::initFilters()
-    {
- 8002a9e:	b480      	push	{r7}
- 8002aa0:	b085      	sub	sp, #20
- 8002aa2:	af00      	add	r7, sp, #0
- 8002aa4:	6078      	str	r0, [r7, #4]
-        for (uint32_t i = 0; i < MAX_FILTER_COUNT; ++i)
- 8002aa6:	2300      	movs	r3, #0
- 8002aa8:	60fb      	str	r3, [r7, #12]
- 8002aaa:	e01a      	b.n	8002ae2 <_ZN3sta18STM32CanController11initFiltersEv+0x44>
-        {
-            CAN_FilterTypeDef * config = &filters_[i];
- 8002aac:	68fa      	ldr	r2, [r7, #12]
- 8002aae:	4613      	mov	r3, r2
- 8002ab0:	009b      	lsls	r3, r3, #2
- 8002ab2:	4413      	add	r3, r2
- 8002ab4:	00db      	lsls	r3, r3, #3
- 8002ab6:	3308      	adds	r3, #8
- 8002ab8:	687a      	ldr	r2, [r7, #4]
- 8002aba:	4413      	add	r3, r2
- 8002abc:	60bb      	str	r3, [r7, #8]
-
-            config->FilterBank           = i;
- 8002abe:	68bb      	ldr	r3, [r7, #8]
- 8002ac0:	68fa      	ldr	r2, [r7, #12]
- 8002ac2:	615a      	str	r2, [r3, #20]
-            config->FilterMode           = CAN_FILTERMODE_IDMASK;
- 8002ac4:	68bb      	ldr	r3, [r7, #8]
- 8002ac6:	2200      	movs	r2, #0
- 8002ac8:	619a      	str	r2, [r3, #24]
-            config->FilterScale          = CAN_FILTERSCALE_32BIT;
- 8002aca:	68bb      	ldr	r3, [r7, #8]
- 8002acc:	2201      	movs	r2, #1
- 8002ace:	61da      	str	r2, [r3, #28]
-            config->FilterActivation     = CAN_FILTER_DISABLE;
- 8002ad0:	68bb      	ldr	r3, [r7, #8]
- 8002ad2:	2200      	movs	r2, #0
- 8002ad4:	621a      	str	r2, [r3, #32]
-            config->SlaveStartFilterBank = MAX_FILTER_COUNT;
- 8002ad6:	68bb      	ldr	r3, [r7, #8]
- 8002ad8:	220e      	movs	r2, #14
- 8002ada:	625a      	str	r2, [r3, #36]	; 0x24
-        for (uint32_t i = 0; i < MAX_FILTER_COUNT; ++i)
- 8002adc:	68fb      	ldr	r3, [r7, #12]
- 8002ade:	3301      	adds	r3, #1
- 8002ae0:	60fb      	str	r3, [r7, #12]
- 8002ae2:	68fb      	ldr	r3, [r7, #12]
- 8002ae4:	2b0d      	cmp	r3, #13
- 8002ae6:	d9e1      	bls.n	8002aac <_ZN3sta18STM32CanController11initFiltersEv+0xe>
-        }
-    }
- 8002ae8:	bf00      	nop
- 8002aea:	bf00      	nop
- 8002aec:	3714      	adds	r7, #20
- 8002aee:	46bd      	mov	sp, r7
- 8002af0:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8002af4:	4770      	bx	lr
-
-08002af6 <_ZN3sta18STM32CanController17getPendingRxFifosEv>:
-
-    CanPendingRxFifos STM32CanController::getPendingRxFifos(){
- 8002af6:	b580      	push	{r7, lr}
- 8002af8:	b082      	sub	sp, #8
- 8002afa:	af00      	add	r7, sp, #0
- 8002afc:	6078      	str	r0, [r7, #4]
- 8002afe:	6039      	str	r1, [r7, #0]
-    	CanPendingRxFifos pendingFifos(42, 3);
- 8002b00:	2203      	movs	r2, #3
- 8002b02:	212a      	movs	r1, #42	; 0x2a
- 8002b04:	6878      	ldr	r0, [r7, #4]
- 8002b06:	f7ff fdf5 	bl	80026f4 <_ZN3sta17CanPendingRxFifosC1Emh>
-
-        // Example implementation:
-        //pendingFifos.fifo0Pending = HAL_CAN_GetRxFifoFillLevel(handle_, CAN_RX_FIFO0) != 0;
-        //pendingFifos.fifo1Pending = HAL_CAN_GetRxFifoFillLevel(handle_, CAN_RX_FIFO1) != 0;
-
-        return pendingFifos;
- 8002b0a:	bf00      	nop
-    }
- 8002b0c:	6878      	ldr	r0, [r7, #4]
- 8002b0e:	3708      	adds	r7, #8
- 8002b10:	46bd      	mov	sp, r7
- 8002b12:	bd80      	pop	{r7, pc}
-
-08002b14 <_ZNK3sta18STM32CanController14maxFilterCountEv>:
-
-    uint8_t STM32CanController::maxFilterCount() const{
- 8002b14:	b480      	push	{r7}
- 8002b16:	b083      	sub	sp, #12
- 8002b18:	af00      	add	r7, sp, #0
- 8002b1a:	6078      	str	r0, [r7, #4]
-        return MAX_FILTER_COUNT;
- 8002b1c:	230e      	movs	r3, #14
-    }
- 8002b1e:	4618      	mov	r0, r3
- 8002b20:	370c      	adds	r7, #12
- 8002b22:	46bd      	mov	sp, r7
- 8002b24:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8002b28:	4770      	bx	lr
-
-08002b2a <_ZNK3sta18STM32CanController12maxFifoCountEv>:
-
-    uint8_t STM32CanController::maxFifoCount() const {
- 8002b2a:	b480      	push	{r7}
- 8002b2c:	b083      	sub	sp, #12
- 8002b2e:	af00      	add	r7, sp, #0
- 8002b30:	6078      	str	r0, [r7, #4]
-        return MAX_FIFO_COUNT;
- 8002b32:	2302      	movs	r3, #2
-    }
- 8002b34:	4618      	mov	r0, r3
- 8002b36:	370c      	adds	r7, #12
- 8002b38:	46bd      	mov	sp, r7
- 8002b3a:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8002b3e:	4770      	bx	lr
-
-08002b40 <_ZNK3sta18STM32CanController14maxPayloadSizeEv>:
-
-    uint8_t STM32CanController::maxPayloadSize() const {
- 8002b40:	b480      	push	{r7}
- 8002b42:	b083      	sub	sp, #12
- 8002b44:	af00      	add	r7, sp, #0
- 8002b46:	6078      	str	r0, [r7, #4]
-        return MAX_PAYLOAD_SIZE;
- 8002b48:	2308      	movs	r3, #8
-    }
- 8002b4a:	4618      	mov	r0, r3
- 8002b4c:	370c      	adds	r7, #12
- 8002b4e:	46bd      	mov	sp, r7
- 8002b50:	f85d 7b04 	ldr.w	r7, [sp], #4
- 8002b54:	4770      	bx	lr
-
-08002b56 <memset>:
- 8002b56:	4402      	add	r2, r0
- 8002b58:	4603      	mov	r3, r0
- 8002b5a:	4293      	cmp	r3, r2
- 8002b5c:	d100      	bne.n	8002b60 <memset+0xa>
- 8002b5e:	4770      	bx	lr
- 8002b60:	f803 1b01 	strb.w	r1, [r3], #1
- 8002b64:	e7f9      	b.n	8002b5a <memset+0x4>
-	...
-
-08002b68 <__libc_init_array>:
- 8002b68:	b570      	push	{r4, r5, r6, lr}
- 8002b6a:	4d0d      	ldr	r5, [pc, #52]	; (8002ba0 <__libc_init_array+0x38>)
- 8002b6c:	4c0d      	ldr	r4, [pc, #52]	; (8002ba4 <__libc_init_array+0x3c>)
- 8002b6e:	1b64      	subs	r4, r4, r5
- 8002b70:	10a4      	asrs	r4, r4, #2
- 8002b72:	2600      	movs	r6, #0
- 8002b74:	42a6      	cmp	r6, r4
- 8002b76:	d109      	bne.n	8002b8c <__libc_init_array+0x24>
- 8002b78:	4d0b      	ldr	r5, [pc, #44]	; (8002ba8 <__libc_init_array+0x40>)
- 8002b7a:	4c0c      	ldr	r4, [pc, #48]	; (8002bac <__libc_init_array+0x44>)
- 8002b7c:	f000 f818 	bl	8002bb0 <_init>
- 8002b80:	1b64      	subs	r4, r4, r5
- 8002b82:	10a4      	asrs	r4, r4, #2
- 8002b84:	2600      	movs	r6, #0
- 8002b86:	42a6      	cmp	r6, r4
- 8002b88:	d105      	bne.n	8002b96 <__libc_init_array+0x2e>
- 8002b8a:	bd70      	pop	{r4, r5, r6, pc}
- 8002b8c:	f855 3b04 	ldr.w	r3, [r5], #4
- 8002b90:	4798      	blx	r3
- 8002b92:	3601      	adds	r6, #1
- 8002b94:	e7ee      	b.n	8002b74 <__libc_init_array+0xc>
- 8002b96:	f855 3b04 	ldr.w	r3, [r5], #4
- 8002b9a:	4798      	blx	r3
- 8002b9c:	3601      	adds	r6, #1
- 8002b9e:	e7f2      	b.n	8002b86 <__libc_init_array+0x1e>
- 8002ba0:	08002ca4 	.word	0x08002ca4
- 8002ba4:	08002ca4 	.word	0x08002ca4
- 8002ba8:	08002ca4 	.word	0x08002ca4
- 8002bac:	08002ca8 	.word	0x08002ca8
-
-08002bb0 <_init>:
- 8002bb0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 8002bb2:	bf00      	nop
- 8002bb4:	bcf8      	pop	{r3, r4, r5, r6, r7}
- 8002bb6:	bc08      	pop	{r3}
- 8002bb8:	469e      	mov	lr, r3
- 8002bba:	4770      	bx	lr
-
-08002bbc <_fini>:
- 8002bbc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 8002bbe:	bf00      	nop
- 8002bc0:	bcf8      	pop	{r3, r4, r5, r6, r7}
- 8002bc2:	bc08      	pop	{r3}
- 8002bc4:	469e      	mov	lr, r3
- 8002bc6:	4770      	bx	lr
diff --git a/Debug/can-tests.map b/Debug/can-tests.map
deleted file mode 100644
index ce86b8d..0000000
--- a/Debug/can-tests.map
+++ /dev/null
@@ -1,5926 +0,0 @@
-Archive member included to satisfy reference by file (symbol)
-
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(del_opv.o)
-                              ./Libs/sta-core/src/devices/stm32/bus/uart.o (operator delete[](void*))
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_opv.o)
-                              ./Libs/sta-core/src/devices/stm32/bus/uart.o (operator new[](unsigned int))
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(del_op.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(del_opv.o) (operator delete(void*))
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_op.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_opv.o) (operator new(unsigned int))
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_handler.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_op.o) (std::get_new_handler())
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-abort.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_op.o) (abort)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-exit.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o (exit)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-malloc.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_op.o) (malloc)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-malloc.o) (_malloc_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mlock.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o) (__malloc_lock)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-exit.o) (__stdio_exit_handler)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fwalk.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o) (_fwalk_sglue)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-printf.o)
-                              ./Libs/sta-core/src/debug/printing/printable_printf.o (printf)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-snprintf.o)
-                              ./Libs/sta-core/src/debug/printing/printable.o (snprintf)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-stdio.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o) (__sread)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memset.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o (memset)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signal.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-abort.o) (raise)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-closer.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-stdio.o) (_close_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reent.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-closer.o) (errno)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-impure.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-malloc.o) (_impure_ptr)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lseekr.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-stdio.o) (_lseek_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-readr.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-stdio.o) (_read_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signalr.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signal.o) (_kill_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-sbrkr.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o) (_sbrk_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-writer.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-stdio.o) (_write_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-errno.o)
-                              ./Core/Src/syscalls.o (__errno)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-init.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o (__libc_init_array)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o) (__retarget_lock_init_recursive)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-strlen.o)
-                              ./Libs/sta-core/src/debug/printing/printable.o (strlen)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-freer.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-malloc.o) (_free_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-snprintf.o) (_svfprintf_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-printf.o) (_vfprintf_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf_i.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o) (_printf_i)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fflush.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o) (_fflush_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fvwrite.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o) (__sfvwrite_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-wbuf.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o) (__swbuf_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-wsetup.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o) (__swsetup_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memmove.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o) (memmove)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memchr.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o) (memchr)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memcpy-stub.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o) (memcpy)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reallocr.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o) (_realloc_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-makebuf.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-wsetup.o) (__smakebuf_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fstatr.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-makebuf.o) (_fstat_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-isattyr.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-makebuf.o) (_isatty_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-msizer.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reallocr.o) (_malloc_usable_size_r)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_aeabi_uldivmod.o)
-                              ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o (__aeabi_uldivmod)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_aeabi_uldivmod.o) (__udivmoddi4)
-C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_dvmd_tls.o)
-                              C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_aeabi_uldivmod.o) (__aeabi_ldiv0)
-
-Discarded input sections
-
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crti.o
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crti.o
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crti.o
- .data          0x0000000000000000        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o
- .rodata        0x0000000000000000       0x24 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o
- .text          0x0000000000000000       0x7c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
- .ARM.extab     0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
- .ARM.exidx     0x0000000000000000       0x10 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
- .debug_line    0x0000000000000000       0x76 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
- .debug_line_str
-                0x0000000000000000       0xdd C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
- .debug_info    0x0000000000000000       0x24 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
- .debug_abbrev  0x0000000000000000       0x14 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
- .debug_aranges
-                0x0000000000000000       0x20 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
- .debug_str     0x0000000000000000       0xe2 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
- .ARM.attributes
-                0x0000000000000000       0x1c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .group         0x0000000000000000        0xc ./App/Src/test.o
- .text          0x0000000000000000        0x0 ./App/Src/test.o
- .data          0x0000000000000000        0x0 ./App/Src/test.o
- .bss           0x0000000000000000        0x0 ./App/Src/test.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/main.o
- .text          0x0000000000000000        0x0 ./Core/Src/main.o
- .data          0x0000000000000000        0x0 ./Core/Src/main.o
- .bss           0x0000000000000000        0x0 ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x29b ./Core/Src/main.o
- .debug_macro   0x0000000000000000       0x2e ./Core/Src/main.o
- .debug_macro   0x0000000000000000       0x2f ./Core/Src/main.o
- .debug_macro   0x0000000000000000       0x22 ./Core/Src/main.o
- .debug_macro   0x0000000000000000       0x8e ./Core/Src/main.o
- .debug_macro   0x0000000000000000       0x51 ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x103 ./Core/Src/main.o
- .debug_macro   0x0000000000000000       0x6a ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x1df ./Core/Src/main.o
- .debug_macro   0x0000000000000000       0x1c ./Core/Src/main.o
- .debug_macro   0x0000000000000000       0x22 ./Core/Src/main.o
- .debug_macro   0x0000000000000000       0xd9 ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x11f ./Core/Src/main.o
- .debug_macro   0x0000000000000000    0x15e82 ./Core/Src/main.o
- .debug_macro   0x0000000000000000       0x6d ./Core/Src/main.o
- .debug_macro   0x0000000000000000     0x367e ./Core/Src/main.o
- .debug_macro   0x0000000000000000       0x5c ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x96b ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x9fe ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x115 ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x13e ./Core/Src/main.o
- .debug_macro   0x0000000000000000       0xa5 ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x174 ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x287 ./Core/Src/main.o
- .debug_macro   0x0000000000000000       0x5f ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x236 ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x40f ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x12c ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x21e ./Core/Src/main.o
- .debug_macro   0x0000000000000000       0x2e ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x11a ./Core/Src/main.o
- .debug_macro   0x0000000000000000       0x7e ./Core/Src/main.o
- .debug_macro   0x0000000000000000       0x89 ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x295 ./Core/Src/main.o
- .debug_macro   0x0000000000000000      0x12d ./Core/Src/main.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_hal_msp.o
- .text          0x0000000000000000        0x0 ./Core/Src/stm32f4xx_hal_msp.o
- .data          0x0000000000000000        0x0 ./Core/Src/stm32f4xx_hal_msp.o
- .bss           0x0000000000000000        0x0 ./Core/Src/stm32f4xx_hal_msp.o
- .text.HAL_CAN_MspDeInit
-                0x0000000000000000       0x3c ./Core/Src/stm32f4xx_hal_msp.o
- .text.HAL_UART_MspDeInit
-                0x0000000000000000       0x3c ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0xaa8 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x29b ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000       0x2e ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000       0x2f ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000       0x22 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000       0x8e ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000       0x51 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x103 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000       0x6a ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x1df ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000       0x1c ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000       0x22 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000       0xd9 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000     0x102d ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x11f ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000    0x15e82 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000       0x6d ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000     0x367e ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x174 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000       0x5c ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x96b ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x9fe ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x115 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x13e ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000       0xa5 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x174 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x287 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000       0x5f ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x236 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x40f ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x12c ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x21e ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000       0x2e ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x11a ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000       0x7e ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000       0x89 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x295 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000000000      0x12d ./Core/Src/stm32f4xx_hal_msp.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/stm32f4xx_it.o
- .text          0x0000000000000000        0x0 ./Core/Src/stm32f4xx_it.o
- .data          0x0000000000000000        0x0 ./Core/Src/stm32f4xx_it.o
- .bss           0x0000000000000000        0x0 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0xaa8 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x29b ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000       0x2e ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000       0x2f ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000       0x22 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000       0x8e ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000       0x51 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x103 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000       0x6a ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x1df ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000       0x1c ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000       0x22 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000       0xd9 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000     0x102d ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x11f ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000    0x15e82 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000       0x6d ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000     0x367e ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x174 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000       0x5c ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x96b ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x9fe ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x115 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x13e ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000       0xa5 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x174 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x287 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000       0x5f ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x236 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x40f ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x12c ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x21e ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000       0x2e ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x11a ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000       0x7e ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000       0x89 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x295 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x0000000000000000      0x12d ./Core/Src/stm32f4xx_it.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/syscalls.o
- .text          0x0000000000000000        0x0 ./Core/Src/syscalls.o
- .data          0x0000000000000000        0x0 ./Core/Src/syscalls.o
- .bss           0x0000000000000000        0x0 ./Core/Src/syscalls.o
- .bss.__env     0x0000000000000000        0x4 ./Core/Src/syscalls.o
- .data.environ  0x0000000000000000        0x4 ./Core/Src/syscalls.o
- .text.initialise_monitor_handles
-                0x0000000000000000        0xe ./Core/Src/syscalls.o
- .text._getpid  0x0000000000000000       0x10 ./Core/Src/syscalls.o
- .text._kill    0x0000000000000000       0x20 ./Core/Src/syscalls.o
- .text._exit    0x0000000000000000       0x14 ./Core/Src/syscalls.o
- .text._read    0x0000000000000000       0x3a ./Core/Src/syscalls.o
- .text._write   0x0000000000000000       0x38 ./Core/Src/syscalls.o
- .text._close   0x0000000000000000       0x18 ./Core/Src/syscalls.o
- .text._fstat   0x0000000000000000       0x20 ./Core/Src/syscalls.o
- .text._isatty  0x0000000000000000       0x16 ./Core/Src/syscalls.o
- .text._lseek   0x0000000000000000       0x1a ./Core/Src/syscalls.o
- .text._open    0x0000000000000000       0x1c ./Core/Src/syscalls.o
- .text._wait    0x0000000000000000       0x1e ./Core/Src/syscalls.o
- .text._unlink  0x0000000000000000       0x1e ./Core/Src/syscalls.o
- .text._times   0x0000000000000000       0x18 ./Core/Src/syscalls.o
- .text._stat    0x0000000000000000       0x20 ./Core/Src/syscalls.o
- .text._link    0x0000000000000000       0x20 ./Core/Src/syscalls.o
- .text._fork    0x0000000000000000       0x16 ./Core/Src/syscalls.o
- .text._execve  0x0000000000000000       0x22 ./Core/Src/syscalls.o
- .debug_info    0x0000000000000000      0x6a3 ./Core/Src/syscalls.o
- .debug_abbrev  0x0000000000000000      0x1b6 ./Core/Src/syscalls.o
- .debug_aranges
-                0x0000000000000000       0xa8 ./Core/Src/syscalls.o
- .debug_rnglists
-                0x0000000000000000       0x79 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000      0x274 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000      0xaa8 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x22 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x5b ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x2a ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x94 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x43 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x34 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x57 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000      0x174 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000      0x369 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x16 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x43 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x34 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x10 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x58 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x8e ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x1c ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000      0x177 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x10 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x35 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x10 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x10 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x10 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x6a ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x1c ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x52 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x22 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x10 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x52 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0xcf ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x1c ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x3d ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x35 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000      0x12c ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x16 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x16 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x29 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x10 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000      0x242 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x1c ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x10 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x10 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x16 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000      0x147 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000      0x103 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000      0x1df ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000      0x18a ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0x16 ./Core/Src/syscalls.o
- .debug_macro   0x0000000000000000       0xce ./Core/Src/syscalls.o
- .debug_line    0x0000000000000000      0x8a8 ./Core/Src/syscalls.o
- .debug_str     0x0000000000000000     0x98a8 ./Core/Src/syscalls.o
- .comment       0x0000000000000000       0x44 ./Core/Src/syscalls.o
- .debug_frame   0x0000000000000000      0x2ac ./Core/Src/syscalls.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Core/Src/syscalls.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/sysmem.o
- .text          0x0000000000000000        0x0 ./Core/Src/sysmem.o
- .data          0x0000000000000000        0x0 ./Core/Src/sysmem.o
- .bss           0x0000000000000000        0x0 ./Core/Src/sysmem.o
- .bss.__sbrk_heap_end
-                0x0000000000000000        0x4 ./Core/Src/sysmem.o
- .text._sbrk    0x0000000000000000       0x6c ./Core/Src/sysmem.o
- .debug_info    0x0000000000000000      0x168 ./Core/Src/sysmem.o
- .debug_abbrev  0x0000000000000000       0xbc ./Core/Src/sysmem.o
- .debug_aranges
-                0x0000000000000000       0x20 ./Core/Src/sysmem.o
- .debug_rnglists
-                0x0000000000000000       0x13 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0xff ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000      0xaa8 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0x10 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0x22 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0x5b ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0x2a ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0x94 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0x43 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0x34 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000      0x174 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0x16 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0x43 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0x57 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0x34 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0x10 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0x58 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0x8e ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0x1c ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000      0x177 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000      0x23c ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000      0x103 ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000       0x6a ./Core/Src/sysmem.o
- .debug_macro   0x0000000000000000      0x1df ./Core/Src/sysmem.o
- .debug_line    0x0000000000000000      0x579 ./Core/Src/sysmem.o
- .debug_str     0x0000000000000000     0x605f ./Core/Src/sysmem.o
- .comment       0x0000000000000000       0x44 ./Core/Src/sysmem.o
- .debug_frame   0x0000000000000000       0x34 ./Core/Src/sysmem.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Core/Src/sysmem.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .group         0x0000000000000000        0xc ./Core/Src/system_stm32f4xx.o
- .text          0x0000000000000000        0x0 ./Core/Src/system_stm32f4xx.o
- .data          0x0000000000000000        0x0 ./Core/Src/system_stm32f4xx.o
- .bss           0x0000000000000000        0x0 ./Core/Src/system_stm32f4xx.o
- .text.SystemCoreClockUpdate
-                0x0000000000000000      0x100 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0xaa8 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000       0x2e ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000       0x2f ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000       0x22 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000       0x8e ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000       0x51 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x103 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000       0x6a ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x1df ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000       0x1c ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000       0x22 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000       0xd9 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000     0x102d ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x11f ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000    0x15e82 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000       0x6d ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x29b ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000     0x367e ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x174 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000       0x5c ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x96b ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x9fe ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x115 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x13e ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000       0xa5 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x174 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x287 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000       0x5f ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x236 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x40f ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x12c ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x21e ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000       0x2e ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x11a ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000       0x7e ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000       0x89 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x295 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x0000000000000000      0x12d ./Core/Src/system_stm32f4xx.o
- .text          0x0000000000000000       0x14 ./Core/Startup/startup_stm32f407zgtx.o
- .data          0x0000000000000000        0x0 ./Core/Startup/startup_stm32f407zgtx.o
- .bss           0x0000000000000000        0x0 ./Core/Startup/startup_stm32f407zgtx.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .data          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .bss           0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_DeInit
-                0x0000000000000000       0x58 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_MspInit
-                0x0000000000000000        0xe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_MspDeInit
-                0x0000000000000000        0xe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_GetTickPrio
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_SetTickFreq
-                0x0000000000000000       0x50 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_GetTickFreq
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_Delay
-                0x0000000000000000       0x48 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_SuspendTick
-                0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_ResumeTick
-                0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_GetHalVersion
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_GetREVID
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_GetDEVID
-                0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_DBGMCU_EnableDBGSleepMode
-                0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_DBGMCU_DisableDBGSleepMode
-                0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_DBGMCU_EnableDBGStopMode
-                0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_DBGMCU_DisableDBGStopMode
-                0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_DBGMCU_EnableDBGStandbyMode
-                0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_DBGMCU_DisableDBGStandbyMode
-                0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_EnableCompensationCell
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_DisableCompensationCell
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_GetUIDw0
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_GetUIDw1
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .text.HAL_GetUIDw2
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000       0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000       0xd9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000     0x102d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000    0x15e82 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000       0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000     0x367e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x96b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x9fe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x13e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000       0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x40f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x11a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000       0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000       0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .data          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .bss           0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_DeInit
-                0x0000000000000000       0x46 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_MspInit
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_MspDeInit
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_Stop
-                0x0000000000000000       0x92 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_RequestSleep
-                0x0000000000000000       0x4a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_WakeUp
-                0x0000000000000000       0x84 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_IsSleepActive
-                0x0000000000000000       0x40 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_AbortTxRequest
-                0x0000000000000000       0x8a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_GetTxMailboxesFreeLevel
-                0x0000000000000000       0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_IsTxMessagePending
-                0x0000000000000000       0x48 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_GetTxTimestamp
-                0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_ActivateNotification
-                0x0000000000000000       0x4c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_DeactivateNotification
-                0x0000000000000000       0x4e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_IRQHandler
-                0x0000000000000000      0x36e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_TxMailbox0CompleteCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_TxMailbox1CompleteCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_TxMailbox2CompleteCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_TxMailbox0AbortCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_TxMailbox1AbortCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_TxMailbox2AbortCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_RxFifo0MsgPendingCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_RxFifo0FullCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_RxFifo1MsgPendingCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_RxFifo1FullCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_SleepCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_WakeUpFromRxMsgCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_ErrorCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_GetState
-                0x0000000000000000       0x50 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_GetError
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .text.HAL_CAN_ResetError
-                0x0000000000000000       0x46 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000       0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000       0xd9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000     0x102d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000    0x15e82 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000       0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000     0x367e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x96b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x9fe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x13e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000       0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x40f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x11a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000       0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000       0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .data          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .bss           0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.__NVIC_EnableIRQ
-                0x0000000000000000       0x3c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.__NVIC_DisableIRQ
-                0x0000000000000000       0x48 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.__NVIC_GetPendingIRQ
-                0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.__NVIC_SetPendingIRQ
-                0x0000000000000000       0x3c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.__NVIC_ClearPendingIRQ
-                0x0000000000000000       0x3c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.__NVIC_GetActive
-                0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.__NVIC_GetPriority
-                0x0000000000000000       0x50 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.NVIC_DecodePriority
-                0x0000000000000000       0x6e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.__NVIC_SystemReset
-                0x0000000000000000       0x2c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.HAL_NVIC_EnableIRQ
-                0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.HAL_NVIC_DisableIRQ
-                0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.HAL_NVIC_SystemReset
-                0x0000000000000000        0x8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.HAL_MPU_Disable
-                0x0000000000000000       0x30 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.HAL_MPU_Enable
-                0x0000000000000000       0x40 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.HAL_MPU_ConfigRegion
-                0x0000000000000000       0x88 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.HAL_NVIC_GetPriorityGrouping
-                0x0000000000000000        0xe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.HAL_NVIC_GetPriority
-                0x0000000000000000       0x2c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.HAL_NVIC_SetPendingIRQ
-                0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.HAL_NVIC_GetPendingIRQ
-                0x0000000000000000       0x1e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.HAL_NVIC_ClearPendingIRQ
-                0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.HAL_NVIC_GetActive
-                0x0000000000000000       0x1e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.HAL_SYSTICK_CLKSourceConfig
-                0x0000000000000000       0x38 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.HAL_SYSTICK_IRQHandler
-                0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.HAL_SYSTICK_Callback
-                0x0000000000000000        0xe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000       0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000       0xd9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000     0x102d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000    0x15e82 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000       0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000     0x367e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x96b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x9fe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x13e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000       0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x40f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x11a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000       0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000       0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .text          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .data          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .bss           0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .text.HAL_DMA_Init
-                0x0000000000000000      0x15c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .text.HAL_DMA_DeInit
-                0x0000000000000000       0xbc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .text.HAL_DMA_Start
-                0x0000000000000000       0x76 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .text.HAL_DMA_Start_IT
-                0x0000000000000000       0xb0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .text.HAL_DMA_Abort
-                0x0000000000000000       0xe0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .text.HAL_DMA_Abort_IT
-                0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .text.HAL_DMA_PollForTransfer
-                0x0000000000000000      0x1be ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .text.HAL_DMA_IRQHandler
-                0x0000000000000000      0x314 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .text.HAL_DMA_RegisterCallback
-                0x0000000000000000       0xa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .text.HAL_DMA_UnRegisterCallback
-                0x0000000000000000       0xd4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .text.HAL_DMA_GetState
-                0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .text.HAL_DMA_GetError
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .text.DMA_SetConfig
-                0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .text.DMA_CalcBaseAndBitshift
-                0x0000000000000000       0x6c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .text.DMA_CheckFifoParam
-                0x0000000000000000       0xf8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .rodata.flagBitshiftOffset.0
-                0x0000000000000000        0x8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_info    0x0000000000000000      0x8e7 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_abbrev  0x0000000000000000      0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_aranges
-                0x0000000000000000       0x90 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_rnglists
-                0x0000000000000000       0x70 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x1ca ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000       0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000       0xd9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000     0x102d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000    0x15e82 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000       0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000     0x367e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x96b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x9fe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x13e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000       0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x40f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x11a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000       0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000       0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_line    0x0000000000000000      0xf78 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_str     0x0000000000000000    0xbeeb4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .comment       0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .debug_frame   0x0000000000000000      0x250 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .text          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .data          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .bss           0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .text.HAL_DMAEx_MultiBufferStart
-                0x0000000000000000       0x96 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .text.HAL_DMAEx_MultiBufferStart_IT
-                0x0000000000000000     0x1290 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .text.HAL_DMAEx_ChangeMemory
-                0x0000000000000000       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .text.DMA_MultiBufferSetConfig
-                0x0000000000000000       0x4c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_info    0x0000000000000000      0x4df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_abbrev  0x0000000000000000      0x1a3 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_aranges
-                0x0000000000000000       0x38 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_rnglists
-                0x0000000000000000       0x27 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000       0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000       0xd9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000     0x102d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000    0x15e82 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000       0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000     0x367e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x96b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x9fe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x13e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000       0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x40f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x11a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000       0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000       0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_line    0x0000000000000000     0x13a7 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_str     0x0000000000000000    0xbec6e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .comment       0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .debug_frame   0x0000000000000000       0xac ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .text          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .data          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .bss           0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .text.HAL_EXTI_SetConfigLine
-                0x0000000000000000      0x150 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .text.HAL_EXTI_GetConfigLine
-                0x0000000000000000       0xf4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .text.HAL_EXTI_ClearConfigLine
-                0x0000000000000000       0xc0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .text.HAL_EXTI_RegisterCallback
-                0x0000000000000000       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .text.HAL_EXTI_GetHandle
-                0x0000000000000000       0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .text.HAL_EXTI_IRQHandler
-                0x0000000000000000       0x48 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .text.HAL_EXTI_GetPending
-                0x0000000000000000       0x40 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .text.HAL_EXTI_ClearPending
-                0x0000000000000000       0x30 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .text.HAL_EXTI_GenerateSWI
-                0x0000000000000000       0x30 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_info    0x0000000000000000      0x4f4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_abbrev  0x0000000000000000      0x1c6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_aranges
-                0x0000000000000000       0x60 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_rnglists
-                0x0000000000000000       0x46 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000       0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000       0xd9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000     0x102d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000    0x15e82 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000       0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000     0x367e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x96b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x9fe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x13e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000       0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x40f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x11a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000       0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000       0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_line    0x0000000000000000      0xa03 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_str     0x0000000000000000    0xbeb06 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .comment       0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .debug_frame   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .data          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .bss           0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .bss.pFlash    0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.HAL_FLASH_Program
-                0x0000000000000000       0xa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.HAL_FLASH_Program_IT
-                0x0000000000000000       0x9c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.HAL_FLASH_IRQHandler
-                0x0000000000000000      0x140 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.HAL_FLASH_EndOfOperationCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.HAL_FLASH_OperationErrorCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.HAL_FLASH_Unlock
-                0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.HAL_FLASH_Lock
-                0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.HAL_FLASH_OB_Unlock
-                0x0000000000000000       0x38 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.HAL_FLASH_OB_Lock
-                0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.HAL_FLASH_OB_Launch
-                0x0000000000000000       0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.HAL_FLASH_GetError
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.FLASH_WaitForLastOperation
-                0x0000000000000000       0x80 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.FLASH_Program_DoubleWord
-                0x0000000000000000       0x64 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.FLASH_Program_Word
-                0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.FLASH_Program_HalfWord
-                0x0000000000000000       0x48 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.FLASH_Program_Byte
-                0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .text.FLASH_SetErrorCode
-                0x0000000000000000       0xac ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_info    0x0000000000000000      0x57d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_abbrev  0x0000000000000000      0x28c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_aranges
-                0x0000000000000000       0xa0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_rnglists
-                0x0000000000000000       0x78 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x1ca ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000       0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000       0xd9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000     0x102d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000    0x15e82 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000       0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000     0x367e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x96b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x9fe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x13e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000       0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x40f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x11a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000       0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000       0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_line    0x0000000000000000      0xaa9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_str     0x0000000000000000    0xbec8a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .comment       0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .debug_frame   0x0000000000000000      0x274 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .data          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .bss           0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text.HAL_FLASHEx_Erase
-                0x0000000000000000       0xe0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text.HAL_FLASHEx_Erase_IT
-                0x0000000000000000       0xac ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text.HAL_FLASHEx_OBProgram
-                0x0000000000000000       0xdc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text.HAL_FLASHEx_OBGetConfig
-                0x0000000000000000       0x46 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text.FLASH_MassErase
-                0x0000000000000000       0x48 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text.FLASH_Erase_Sector
-                0x0000000000000000       0x90 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text.FLASH_OB_EnableWRP
-                0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text.FLASH_OB_DisableWRP
-                0x0000000000000000       0x40 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text.FLASH_OB_RDP_LevelConfig
-                0x0000000000000000       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text.FLASH_OB_UserConfig
-                0x0000000000000000       0x60 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text.FLASH_OB_BOR_LevelConfig
-                0x0000000000000000       0x3c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text.FLASH_OB_GetUser
-                0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text.FLASH_OB_GetWRP
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text.FLASH_OB_GetRDP
-                0x0000000000000000       0x40 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text.FLASH_OB_GetBOR
-                0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .text.FLASH_FlushCaches
-                0x0000000000000000       0x8c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_info    0x0000000000000000      0x67f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_abbrev  0x0000000000000000      0x249 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_aranges
-                0x0000000000000000       0x98 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_rnglists
-                0x0000000000000000       0x72 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x1ca ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000       0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000       0xd9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000     0x102d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000    0x15e82 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000       0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000     0x367e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x96b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x9fe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x13e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000       0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x40f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x11a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000       0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000       0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_line    0x0000000000000000      0xac2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_str     0x0000000000000000    0xbecda ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .comment       0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .debug_frame   0x0000000000000000      0x250 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .text          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .data          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .bss           0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_info    0x0000000000000000       0x70 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_abbrev  0x0000000000000000       0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000       0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000       0xd9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000     0x102d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000    0x15e82 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000       0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000     0x367e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x96b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x9fe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x13e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000       0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x40f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x11a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000       0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000       0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_line    0x0000000000000000      0x72c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .debug_str     0x0000000000000000    0xbe8df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .comment       0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .text          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .data          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .bss           0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .text.HAL_GPIO_DeInit
-                0x0000000000000000      0x1f8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .text.HAL_GPIO_ReadPin
-                0x0000000000000000       0x30 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .text.HAL_GPIO_LockPin
-                0x0000000000000000       0x50 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .text.HAL_GPIO_EXTI_IRQHandler
-                0x0000000000000000       0x30 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .text.HAL_GPIO_EXTI_Callback
-                0x0000000000000000       0x16 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000       0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000       0xd9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000     0x102d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000    0x15e82 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000       0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000     0x367e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x96b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x9fe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x13e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000       0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x40f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x11a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000       0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000       0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .data          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .bss           0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_DeInit
-                0x0000000000000000       0x2c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_EnableBkUpAccess
-                0x0000000000000000       0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_DisableBkUpAccess
-                0x0000000000000000       0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_ConfigPVD
-                0x0000000000000000       0xc0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_EnablePVD
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_DisablePVD
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_EnableWakeUpPin
-                0x0000000000000000       0x24 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_DisableWakeUpPin
-                0x0000000000000000       0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_EnterSLEEPMode
-                0x0000000000000000       0x38 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_EnterSTOPMode
-                0x0000000000000000       0x58 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_EnterSTANDBYMode
-                0x0000000000000000       0x30 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_PVD_IRQHandler
-                0x0000000000000000       0x24 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_PVDCallback
-                0x0000000000000000        0xe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_EnableSleepOnExit
-                0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_DisableSleepOnExit
-                0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_EnableSEVOnPend
-                0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .text.HAL_PWR_DisableSEVOnPend
-                0x0000000000000000       0x20 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_info    0x0000000000000000      0x6f9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_abbrev  0x0000000000000000      0x19c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_aranges
-                0x0000000000000000       0xa0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_rnglists
-                0x0000000000000000       0x74 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x1dc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000       0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000       0xd9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000     0x102d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000    0x15e82 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000       0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000     0x367e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x96b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x9fe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x13e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000       0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x40f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x11a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000       0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000       0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_line    0x0000000000000000      0x920 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_str     0x0000000000000000    0xbecd0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .comment       0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .debug_frame   0x0000000000000000      0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .text          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .data          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .bss           0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .text.HAL_PWREx_EnableBkUpReg
-                0x0000000000000000       0x4c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .text.HAL_PWREx_DisableBkUpReg
-                0x0000000000000000       0x4c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .text.HAL_PWREx_EnableFlashPowerDown
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .text.HAL_PWREx_DisableFlashPowerDown
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .text.HAL_PWREx_GetVoltageRange
-                0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .text.HAL_PWREx_ControlVoltageScaling
-                0x0000000000000000       0x84 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_info    0x0000000000000000      0x3a3 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_abbrev  0x0000000000000000      0x180 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_aranges
-                0x0000000000000000       0x48 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_rnglists
-                0x0000000000000000       0x32 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x1dc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000       0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000       0xd9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000     0x102d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000    0x15e82 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000       0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000     0x367e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x96b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x9fe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x13e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000       0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x40f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x11a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000       0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000       0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_line    0x0000000000000000      0x81f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_str     0x0000000000000000    0xbeb99 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .comment       0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .debug_frame   0x0000000000000000       0xdc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .text          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .data          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .bss           0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .text.HAL_RCC_DeInit
-                0x0000000000000000       0x10 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .text.HAL_RCC_MCOConfig
-                0x0000000000000000       0xd0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .text.HAL_RCC_EnableCSS
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .text.HAL_RCC_DisableCSS
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .text.HAL_RCC_GetOscConfig
-                0x0000000000000000      0x128 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .text.HAL_RCC_GetClockConfig
-                0x0000000000000000       0x64 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .text.HAL_RCC_NMI_IRQHandler
-                0x0000000000000000       0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .text.HAL_RCC_CSSCallback
-                0x0000000000000000        0xe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000       0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000       0xd9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000     0x102d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000    0x15e82 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000       0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000     0x367e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x96b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x9fe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x13e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000       0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x40f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x11a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000       0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000       0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .text          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .data          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .bss           0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .text.HAL_RCCEx_PeriphCLKConfig
-                0x0000000000000000      0x1c4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .text.HAL_RCCEx_GetPeriphCLKConfig
-                0x0000000000000000       0x58 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .text.HAL_RCCEx_GetPeriphCLKFreq
-                0x0000000000000000       0xbc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .text.HAL_RCCEx_EnablePLLI2S
-                0x0000000000000000       0x88 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .text.HAL_RCCEx_DisablePLLI2S
-                0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .text.HAL_RCC_DeInit
-                0x0000000000000000      0x19c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_info    0x0000000000000000      0x53a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_abbrev  0x0000000000000000      0x1af ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_aranges
-                0x0000000000000000       0x48 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_rnglists
-                0x0000000000000000       0x35 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x1c4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000       0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000       0xd9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000     0x102d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000    0x15e82 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000       0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000     0x367e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x96b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x9fe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x13e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000       0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x40f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x11a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000       0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000       0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_line    0x0000000000000000      0xa2a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_str     0x0000000000000000    0xbebec ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .comment       0x0000000000000000       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .debug_frame   0x0000000000000000       0xf0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .data          0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .bss           0x0000000000000000        0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_HalfDuplex_Init
-                0x0000000000000000       0xaa ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_LIN_Init
-                0x0000000000000000       0xcc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_MultiProcessor_Init
-                0x0000000000000000       0xe0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_DeInit
-                0x0000000000000000       0x5e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_MspInit
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_MspDeInit
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_Transmit
-                0x0000000000000000      0x124 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_Receive
-                0x0000000000000000      0x144 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_Transmit_IT
-                0x0000000000000000       0x8a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_Receive_IT
-                0x0000000000000000       0x60 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_Transmit_DMA
-                0x0000000000000000       0xfc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_Receive_DMA
-                0x0000000000000000       0x60 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_DMAPause
-                0x0000000000000000      0x158 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_DMAResume
-                0x0000000000000000      0x13a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_DMAStop
-                0x0000000000000000       0xfe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UARTEx_ReceiveToIdle
-                0x0000000000000000      0x1ba ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UARTEx_ReceiveToIdle_IT
-                0x0000000000000000       0xca ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UARTEx_ReceiveToIdle_DMA
-                0x0000000000000000       0xca ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_Abort
-                0x0000000000000000      0x1d6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_AbortTransmit
-                0x0000000000000000       0xd0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_AbortReceive
-                0x0000000000000000      0x146 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_Abort_IT
-                0x0000000000000000      0x228 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_AbortTransmit_IT
-                0x0000000000000000       0xe8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_AbortReceive_IT
-                0x0000000000000000      0x164 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_IRQHandler
-                0x0000000000000000      0x51c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_TxCpltCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_TxHalfCpltCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_RxCpltCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_RxHalfCpltCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_ErrorCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_AbortCpltCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_AbortTransmitCpltCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_AbortReceiveCpltCallback
-                0x0000000000000000       0x14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UARTEx_RxEventCallback
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_LIN_SendBreak
-                0x0000000000000000       0x78 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_MultiProcessor_EnterMuteMode
-                0x0000000000000000       0x78 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_MultiProcessor_ExitMuteMode
-                0x0000000000000000       0x78 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_HalfDuplex_EnableTransmitter
-                0x0000000000000000       0x68 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_HalfDuplex_EnableReceiver
-                0x0000000000000000       0x68 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_GetState
-                0x0000000000000000       0x3c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.HAL_UART_GetError
-                0x0000000000000000       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_DMATransmitCplt
-                0x0000000000000000       0x9a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_DMATxHalfCplt
-                0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_DMAReceiveCplt
-                0x0000000000000000      0x126 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_DMARxHalfCplt
-                0x0000000000000000       0x36 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_DMAError
-                0x0000000000000000       0x94 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_WaitOnFlagUntilTimeout
-                0x0000000000000000       0xdc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_Start_Receive_IT
-                0x0000000000000000       0x7c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_Start_Receive_DMA
-                0x0000000000000000      0x13c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_EndTxTransfer
-                0x0000000000000000       0x50 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_EndRxTransfer
-                0x0000000000000000       0xc6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_DMAAbortOnError
-                0x0000000000000000       0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_DMATxAbortCallback
-                0x0000000000000000       0x60 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_DMARxAbortCallback
-                0x0000000000000000       0x60 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_DMATxOnlyAbortCallback
-                0x0000000000000000       0x2a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_DMARxOnlyAbortCallback
-                0x0000000000000000       0x30 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_Transmit_IT
-                0x0000000000000000       0xa0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_EndTransmit_IT
-                0x0000000000000000       0x30 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text.UART_Receive_IT
-                0x0000000000000000      0x176 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000       0x2f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000       0x8e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000       0x51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x103 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000       0x6a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x1df ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000       0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000       0xd9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000     0x102d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x11f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000    0x15e82 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000       0x6d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000     0x367e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000       0x5c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x96b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x9fe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x115 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x13e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000       0xa5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000       0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x40f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x12c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x21e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000       0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x11a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000       0x7e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000       0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000000000      0x12d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/atomic/mutex.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/atomic/mutex.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/atomic/mutex.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/atomic/mutex.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/atomic/mutex.o
- .debug_info    0x0000000000000000       0x22 ./Libs/sta-core/src/atomic/mutex.o
- .debug_abbrev  0x0000000000000000       0x12 ./Libs/sta-core/src/atomic/mutex.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Libs/sta-core/src/atomic/mutex.o
- .debug_macro   0x0000000000000000       0x24 ./Libs/sta-core/src/atomic/mutex.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/atomic/mutex.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/atomic/mutex.o
- .debug_line    0x0000000000000000       0xc9 ./Libs/sta-core/src/atomic/mutex.o
- .debug_str     0x0000000000000000     0x3280 ./Libs/sta-core/src/atomic/mutex.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/atomic/mutex.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/atomic/mutex.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/atomic/signal.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/atomic/signal.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/atomic/signal.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/atomic/signal.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/atomic/signal.o
- .debug_info    0x0000000000000000       0x22 ./Libs/sta-core/src/atomic/signal.o
- .debug_abbrev  0x0000000000000000       0x12 ./Libs/sta-core/src/atomic/signal.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Libs/sta-core/src/atomic/signal.o
- .debug_macro   0x0000000000000000       0x24 ./Libs/sta-core/src/atomic/signal.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/atomic/signal.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/atomic/signal.o
- .debug_line    0x0000000000000000       0xcb ./Libs/sta-core/src/atomic/signal.o
- .debug_str     0x0000000000000000     0x3282 ./Libs/sta-core/src/atomic/signal.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/atomic/signal.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/atomic/signal.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/device.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/device.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/device.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/bus/device.o
- .rodata        0x0000000000000000       0x66 ./Libs/sta-core/src/bus/device.o
- .text._ZN3sta6DeviceC2EPNS_9InterfaceE
-                0x0000000000000000       0x48 ./Libs/sta-core/src/bus/device.o
- .text._ZN3sta6Device17beginTransmissionEv
-                0x0000000000000000       0x32 ./Libs/sta-core/src/bus/device.o
- .text._ZN3sta6Device15endTransmissionEv
-                0x0000000000000000       0x34 ./Libs/sta-core/src/bus/device.o
- .text._ZN3sta6Device8transferEh
-                0x0000000000000000       0x74 ./Libs/sta-core/src/bus/device.o
- .text._ZN3sta6Device10transfer16Et
-                0x0000000000000000       0x74 ./Libs/sta-core/src/bus/device.o
- .text._ZN3sta6Device8transferEPKhj
-                0x0000000000000000       0x8c ./Libs/sta-core/src/bus/device.o
- .text._ZN3sta6Device7receiveEPhj
-                0x0000000000000000       0x8c ./Libs/sta-core/src/bus/device.o
- .text._ZN3sta6Device4fillEhj
-                0x0000000000000000       0x78 ./Libs/sta-core/src/bus/device.o
- .rodata._ZTVN3sta6DeviceE
-                0x0000000000000000       0x10 ./Libs/sta-core/src/bus/device.o
- .debug_info    0x0000000000000000      0x7f4 ./Libs/sta-core/src/bus/device.o
- .debug_abbrev  0x0000000000000000      0x25b ./Libs/sta-core/src/bus/device.o
- .debug_aranges
-                0x0000000000000000       0x58 ./Libs/sta-core/src/bus/device.o
- .debug_rnglists
-                0x0000000000000000       0x3f ./Libs/sta-core/src/bus/device.o
- .debug_macro   0x0000000000000000       0xdd ./Libs/sta-core/src/bus/device.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/bus/device.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/bus/device.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/bus/device.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/bus/device.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/bus/device.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/bus/device.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/bus/device.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/bus/device.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/bus/device.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/bus/device.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/bus/device.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/bus/device.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/bus/device.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/bus/device.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/bus/device.o
- .debug_line    0x0000000000000000      0x8b0 ./Libs/sta-core/src/bus/device.o
- .debug_str     0x0000000000000000     0x6574 ./Libs/sta-core/src/bus/device.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/bus/device.o
- .debug_frame   0x0000000000000000      0x130 ./Libs/sta-core/src/bus/device.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/bus/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/interface.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/interface.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/interface.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/interface.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/interface.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/interface.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/interface.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/interface.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/interface.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/interface.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/interface.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/interface.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/interface.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/interface.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/interface.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/interface.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/interface.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/bus/interface.o
- .rodata        0x0000000000000000       0x39 ./Libs/sta-core/src/bus/interface.o
- .text._ZN3sta9InterfaceC2EPNS_5MutexE
-                0x0000000000000000       0x48 ./Libs/sta-core/src/bus/interface.o
- .text._ZN3sta9Interface7acquireEv
-                0x0000000000000000       0x26 ./Libs/sta-core/src/bus/interface.o
- .text._ZN3sta9Interface7releaseEv
-                0x0000000000000000       0x28 ./Libs/sta-core/src/bus/interface.o
- .text._ZN3sta9Interface10isAcquiredEv
-                0x0000000000000000       0x18 ./Libs/sta-core/src/bus/interface.o
- .rodata._ZTVN3sta9InterfaceE
-                0x0000000000000000       0x24 ./Libs/sta-core/src/bus/interface.o
- .debug_info    0x0000000000000000      0x6ee ./Libs/sta-core/src/bus/interface.o
- .debug_abbrev  0x0000000000000000      0x226 ./Libs/sta-core/src/bus/interface.o
- .debug_aranges
-                0x0000000000000000       0x38 ./Libs/sta-core/src/bus/interface.o
- .debug_rnglists
-                0x0000000000000000       0x25 ./Libs/sta-core/src/bus/interface.o
- .debug_macro   0x0000000000000000       0xd3 ./Libs/sta-core/src/bus/interface.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/bus/interface.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/bus/interface.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/bus/interface.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/bus/interface.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/bus/interface.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/bus/interface.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/bus/interface.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/bus/interface.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/bus/interface.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/bus/interface.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/bus/interface.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/bus/interface.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/bus/interface.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/bus/interface.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/bus/interface.o
- .debug_line    0x0000000000000000      0x7d4 ./Libs/sta-core/src/bus/interface.o
- .debug_str     0x0000000000000000     0x64f4 ./Libs/sta-core/src/bus/interface.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/bus/interface.o
- .debug_frame   0x0000000000000000       0xa4 ./Libs/sta-core/src/bus/interface.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/bus/interface.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/device.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/i2c/device.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/i2c/device.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/bus/i2c/device.o
- .rodata        0x0000000000000000       0x38 ./Libs/sta-core/src/bus/i2c/device.o
- .text._ZN3sta9I2CDeviceC2EPNS_3I2CEibb
-                0x0000000000000000       0x60 ./Libs/sta-core/src/bus/i2c/device.o
- .text._ZN3sta9I2CDevice6selectEv
-                0x0000000000000000       0x3a ./Libs/sta-core/src/bus/i2c/device.o
- .text._ZN3sta9I2CDevice8deselectEv
-                0x0000000000000000       0x14 ./Libs/sta-core/src/bus/i2c/device.o
- .rodata._ZTVN3sta9I2CDeviceE
-                0x0000000000000000       0x10 ./Libs/sta-core/src/bus/i2c/device.o
- .debug_info    0x0000000000000000      0x888 ./Libs/sta-core/src/bus/i2c/device.o
- .debug_abbrev  0x0000000000000000      0x29f ./Libs/sta-core/src/bus/i2c/device.o
- .debug_aranges
-                0x0000000000000000       0x30 ./Libs/sta-core/src/bus/i2c/device.o
- .debug_rnglists
-                0x0000000000000000       0x1f ./Libs/sta-core/src/bus/i2c/device.o
- .debug_macro   0x0000000000000000       0xf1 ./Libs/sta-core/src/bus/i2c/device.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/bus/i2c/device.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/bus/i2c/device.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/bus/i2c/device.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/bus/i2c/device.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/bus/i2c/device.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/bus/i2c/device.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/bus/i2c/device.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/bus/i2c/device.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/bus/i2c/device.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/bus/i2c/device.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/bus/i2c/device.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/bus/i2c/device.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/bus/i2c/device.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/bus/i2c/device.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/bus/i2c/device.o
- .debug_line    0x0000000000000000      0x845 ./Libs/sta-core/src/bus/i2c/device.o
- .debug_str     0x0000000000000000     0x6692 ./Libs/sta-core/src/bus/i2c/device.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/bus/i2c/device.o
- .debug_frame   0x0000000000000000       0x80 ./Libs/sta-core/src/bus/i2c/device.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/bus/i2c/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/i2c/i2c.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/i2c/i2c.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/i2c/i2c.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/bus/i2c/i2c.o
- .text._ZN3sta3I2CC2EPNS_5MutexE
-                0x0000000000000000       0x28 ./Libs/sta-core/src/bus/i2c/i2c.o
- .text._ZN3sta3I2C11setSettingsEtbb
-                0x0000000000000000       0x38 ./Libs/sta-core/src/bus/i2c/i2c.o
- .rodata._ZTVN3sta3I2CE
-                0x0000000000000000       0x24 ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_info    0x0000000000000000      0x603 ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_abbrev  0x0000000000000000      0x231 ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_aranges
-                0x0000000000000000       0x28 ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_rnglists
-                0x0000000000000000       0x19 ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_macro   0x0000000000000000       0xc5 ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_line    0x0000000000000000      0x76f ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_str     0x0000000000000000     0x61d6 ./Libs/sta-core/src/bus/i2c/i2c.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/bus/i2c/i2c.o
- .debug_frame   0x0000000000000000       0x5c ./Libs/sta-core/src/bus/i2c/i2c.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/bus/i2c/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/device.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/spi/device.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/spi/device.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/bus/spi/device.o
- .rodata        0x0000000000000000       0x88 ./Libs/sta-core/src/bus/spi/device.o
- .text._ZN3sta9SPIDeviceC2EPNS_3SPIEPNS_7GpioPinE
-                0x0000000000000000       0x6c ./Libs/sta-core/src/bus/spi/device.o
- .text._ZN3sta9SPIDevice8transferEPKhPhj
-                0x0000000000000000       0x88 ./Libs/sta-core/src/bus/spi/device.o
- .text._ZNK3sta9SPIDevice8settingsEv
-                0x0000000000000000       0x1c ./Libs/sta-core/src/bus/spi/device.o
- .text._ZN3sta9SPIDevice6selectEv
-                0x0000000000000000       0x22 ./Libs/sta-core/src/bus/spi/device.o
- .text._ZN3sta9SPIDevice8deselectEv
-                0x0000000000000000       0x22 ./Libs/sta-core/src/bus/spi/device.o
- .rodata._ZTVN3sta9SPIDeviceE
-                0x0000000000000000       0x10 ./Libs/sta-core/src/bus/spi/device.o
- .debug_info    0x0000000000000000      0x9ec ./Libs/sta-core/src/bus/spi/device.o
- .debug_abbrev  0x0000000000000000      0x2ea ./Libs/sta-core/src/bus/spi/device.o
- .debug_aranges
-                0x0000000000000000       0x40 ./Libs/sta-core/src/bus/spi/device.o
- .debug_rnglists
-                0x0000000000000000       0x2c ./Libs/sta-core/src/bus/spi/device.o
- .debug_macro   0x0000000000000000      0x105 ./Libs/sta-core/src/bus/spi/device.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/bus/spi/device.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/bus/spi/device.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/bus/spi/device.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/bus/spi/device.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/bus/spi/device.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/bus/spi/device.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/bus/spi/device.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/bus/spi/device.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/bus/spi/device.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/bus/spi/device.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/bus/spi/device.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/bus/spi/device.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/bus/spi/device.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/bus/spi/device.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/bus/spi/device.o
- .debug_line    0x0000000000000000      0x8ac ./Libs/sta-core/src/bus/spi/device.o
- .debug_str     0x0000000000000000     0x67ca ./Libs/sta-core/src/bus/spi/device.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/bus/spi/device.o
- .debug_frame   0x0000000000000000       0xc8 ./Libs/sta-core/src/bus/spi/device.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/bus/spi/device.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/settings.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/settings.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/settings.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/settings.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/settings.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/settings.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/settings.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/settings.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/settings.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/settings.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/settings.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/settings.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/settings.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/settings.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/spi/settings.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/spi/settings.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/bus/spi/settings.o
- .rodata        0x0000000000000000       0x4e ./Libs/sta-core/src/bus/spi/settings.o
- .text._ZN3sta17getSPIClkPolarityENS_7SPIModeE
-                0x0000000000000000       0x48 ./Libs/sta-core/src/bus/spi/settings.o
- .text._ZN3sta14getSPIClkPhaseENS_7SPIModeE
-                0x0000000000000000       0x4c ./Libs/sta-core/src/bus/spi/settings.o
- .text._ZN3sta10getSPIModeENS_14SPIClkPolarityENS_11SPIClkPhaseE
-                0x0000000000000000       0x36 ./Libs/sta-core/src/bus/spi/settings.o
- .debug_info    0x0000000000000000      0x4cc ./Libs/sta-core/src/bus/spi/settings.o
- .debug_abbrev  0x0000000000000000      0x144 ./Libs/sta-core/src/bus/spi/settings.o
- .debug_aranges
-                0x0000000000000000       0x30 ./Libs/sta-core/src/bus/spi/settings.o
- .debug_rnglists
-                0x0000000000000000       0x1f ./Libs/sta-core/src/bus/spi/settings.o
- .debug_macro   0x0000000000000000       0xc0 ./Libs/sta-core/src/bus/spi/settings.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/bus/spi/settings.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/bus/spi/settings.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/bus/spi/settings.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/bus/spi/settings.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/bus/spi/settings.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/bus/spi/settings.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/bus/spi/settings.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/bus/spi/settings.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/bus/spi/settings.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/bus/spi/settings.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/bus/spi/settings.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/bus/spi/settings.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/bus/spi/settings.o
- .debug_macro   0x0000000000000000       0x46 ./Libs/sta-core/src/bus/spi/settings.o
- .debug_line    0x0000000000000000      0x7ad ./Libs/sta-core/src/bus/spi/settings.o
- .debug_str     0x0000000000000000     0x61e7 ./Libs/sta-core/src/bus/spi/settings.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/bus/spi/settings.o
- .debug_frame   0x0000000000000000       0x80 ./Libs/sta-core/src/bus/spi/settings.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/bus/spi/settings.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/spi/spi.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/spi/spi.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/spi/spi.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/bus/spi/spi.o
- .text._ZN3sta3SPIC2ERKNS_11SPISettingsEPNS_5MutexE
-                0x0000000000000000       0x3c ./Libs/sta-core/src/bus/spi/spi.o
- .text._ZN3sta3SPI8settingsEv
-                0x0000000000000000       0x18 ./Libs/sta-core/src/bus/spi/spi.o
- .rodata._ZTVN3sta3SPIE
-                0x0000000000000000       0x28 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_info    0x0000000000000000     0x1059 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_abbrev  0x0000000000000000      0x367 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_aranges
-                0x0000000000000000       0x28 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_rnglists
-                0x0000000000000000       0x19 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000      0x1b0 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x61 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x2a ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x43 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x34 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x35 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000      0x38c ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x43 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x34 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x58 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000      0x177 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000      0x139 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_macro   0x0000000000000000      0x11d ./Libs/sta-core/src/bus/spi/spi.o
- .debug_line    0x0000000000000000      0x8d7 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_str     0x0000000000000000     0x9e69 ./Libs/sta-core/src/bus/spi/spi.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/bus/spi/spi.o
- .debug_frame   0x0000000000000000       0x60 ./Libs/sta-core/src/bus/spi/spi.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/bus/spi/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/uart/settings.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/uart/settings.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/uart/settings.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/bus/uart/settings.o
- .debug_info    0x0000000000000000       0x22 ./Libs/sta-core/src/bus/uart/settings.o
- .debug_abbrev  0x0000000000000000       0x12 ./Libs/sta-core/src/bus/uart/settings.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Libs/sta-core/src/bus/uart/settings.o
- .debug_macro   0x0000000000000000       0x11 ./Libs/sta-core/src/bus/uart/settings.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/bus/uart/settings.o
- .debug_line    0x0000000000000000       0x4b ./Libs/sta-core/src/bus/uart/settings.o
- .debug_str     0x0000000000000000     0x31fb ./Libs/sta-core/src/bus/uart/settings.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/bus/uart/settings.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/bus/uart/settings.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/uart/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/uart/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/uart/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/uart/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/uart/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/uart/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/uart/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/uart/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/uart/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/uart/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/uart/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/uart/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/uart/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/bus/uart/uart.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/uart/uart.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/bus/uart/uart.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/bus/uart/uart.o
- .text._ZN3sta4UARTC2ERNS_12UARTSettingsEPNS_5MutexE
-                0x0000000000000000       0x34 ./Libs/sta-core/src/bus/uart/uart.o
- .text._ZN3sta4UART8settingsEv
-                0x0000000000000000       0x18 ./Libs/sta-core/src/bus/uart/uart.o
- .rodata._ZTVN3sta4UARTE
-                0x0000000000000000       0x24 ./Libs/sta-core/src/bus/uart/uart.o
- .debug_info    0x0000000000000000      0x614 ./Libs/sta-core/src/bus/uart/uart.o
- .debug_abbrev  0x0000000000000000      0x23e ./Libs/sta-core/src/bus/uart/uart.o
- .debug_aranges
-                0x0000000000000000       0x28 ./Libs/sta-core/src/bus/uart/uart.o
- .debug_rnglists
-                0x0000000000000000       0x19 ./Libs/sta-core/src/bus/uart/uart.o
- .debug_macro   0x0000000000000000       0xcf ./Libs/sta-core/src/bus/uart/uart.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/bus/uart/uart.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/bus/uart/uart.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/bus/uart/uart.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/bus/uart/uart.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/bus/uart/uart.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/bus/uart/uart.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/bus/uart/uart.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/bus/uart/uart.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/bus/uart/uart.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/bus/uart/uart.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/bus/uart/uart.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/bus/uart/uart.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/bus/uart/uart.o
- .debug_line    0x0000000000000000      0x780 ./Libs/sta-core/src/bus/uart/uart.o
- .debug_str     0x0000000000000000     0x6210 ./Libs/sta-core/src/bus/uart/uart.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/bus/uart/uart.o
- .debug_frame   0x0000000000000000       0x5c ./Libs/sta-core/src/bus/uart/uart.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/bus/uart/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/id.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/id.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/id.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/id.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/id.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/id.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/id.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/id.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/id.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/id.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/id.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/id.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/can/id.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/can/id.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/can/id.o
- .text._ZN3staeqERKNS_5CanIdES2_
-                0x0000000000000000       0x34 ./Libs/sta-core/src/can/id.o
- .text._ZN3staneERKNS_5CanIdES2_
-                0x0000000000000000       0x22 ./Libs/sta-core/src/can/id.o
- .text._ZN3staeqERKNS_10CanFrameIdES2_
-                0x0000000000000000       0x40 ./Libs/sta-core/src/can/id.o
- .text._ZN3staneERKNS_10CanFrameIdES2_
-                0x0000000000000000       0x22 ./Libs/sta-core/src/can/id.o
- .debug_info    0x0000000000000000      0x52d ./Libs/sta-core/src/can/id.o
- .debug_abbrev  0x0000000000000000      0x148 ./Libs/sta-core/src/can/id.o
- .debug_aranges
-                0x0000000000000000       0x38 ./Libs/sta-core/src/can/id.o
- .debug_rnglists
-                0x0000000000000000       0x25 ./Libs/sta-core/src/can/id.o
- .debug_macro   0x0000000000000000       0xa4 ./Libs/sta-core/src/can/id.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/can/id.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/can/id.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/can/id.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/can/id.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/can/id.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/can/id.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/can/id.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/can/id.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/can/id.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/can/id.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/can/id.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/can/id.o
- .debug_line    0x0000000000000000      0x727 ./Libs/sta-core/src/can/id.o
- .debug_str     0x0000000000000000     0x5d99 ./Libs/sta-core/src/can/id.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/can/id.o
- .debug_frame   0x0000000000000000       0xa8 ./Libs/sta-core/src/can/id.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/can/id.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/iter.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/iter.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/iter.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/iter.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/iter.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/iter.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/iter.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/iter.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/iter.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/iter.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/iter.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/iter.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/can/iter.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/can/iter.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/can/iter.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/can/iter.o
- .text._ZN3sta17CanPendingRxFifos14const_iteratorC2Emhh
-                0x0000000000000000       0x36 ./Libs/sta-core/src/can/iter.o
- .text._ZN3sta17CanPendingRxFifos14const_iteratorC2ERKS1_
-                0x0000000000000000       0x30 ./Libs/sta-core/src/can/iter.o
- .text._ZN3sta17CanPendingRxFifos14const_iteratoraSERKS1_
-                0x0000000000000000       0x30 ./Libs/sta-core/src/can/iter.o
- .text._ZNK3sta17CanPendingRxFifos14const_iteratoreqERKS1_
-                0x0000000000000000       0x40 ./Libs/sta-core/src/can/iter.o
- .text._ZNK3sta17CanPendingRxFifos14const_iteratorneERKS1_
-                0x0000000000000000       0x22 ./Libs/sta-core/src/can/iter.o
- .text._ZN3sta17CanPendingRxFifos14const_iteratorppEv
-                0x0000000000000000       0x3c ./Libs/sta-core/src/can/iter.o
- .text._ZN3sta17CanPendingRxFifos14const_iteratorppEi
-                0x0000000000000000       0x54 ./Libs/sta-core/src/can/iter.o
- .rodata        0x0000000000000000       0x49 ./Libs/sta-core/src/can/iter.o
- .text._ZNK3sta17CanPendingRxFifos14const_iteratordeEv
-                0x0000000000000000       0x38 ./Libs/sta-core/src/can/iter.o
- .text._ZNK3sta17CanPendingRxFifos14const_iterator11isRxPendingEv
-                0x0000000000000000       0x2c ./Libs/sta-core/src/can/iter.o
- .text._ZNK3sta17CanPendingRxFifos5beginEv
-                0x0000000000000000       0x22 ./Libs/sta-core/src/can/iter.o
- .text._ZNK3sta17CanPendingRxFifos3endEv
-                0x0000000000000000       0x24 ./Libs/sta-core/src/can/iter.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/can/iter.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/can/iter.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/can/iter.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/can/iter.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/can/iter.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/can/iter.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/can/iter.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/can/iter.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/can/iter.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/can/iter.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/can/iter.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/can/iter.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/can/iter.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/assert.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/debug/assert.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/debug/assert.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x46 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x61 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x2a ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x43 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x34 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000      0x38c ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x43 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x34 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x58 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000      0x177 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000      0x139 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000000000      0x11d ./Libs/sta-core/src/debug/assert.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/debug/printing/printable.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/debug/printing/printable.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable5printEc
-                0x0000000000000000       0x22 ./Libs/sta-core/src/debug/printing/printable.o
- .rodata        0x0000000000000000       0x60 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable5printEb
-                0x0000000000000000       0x30 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable5printEd
-                0x0000000000000000       0x38 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable5printEhNS_11IntegerBaseE
-                0x0000000000000000       0x38 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable5printEtNS_11IntegerBaseE
-                0x0000000000000000       0x38 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable5printEmNS_11IntegerBaseE
-                0x0000000000000000       0x38 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable5printEPKc
-                0x0000000000000000       0x28 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable7printlnEv
-                0x0000000000000000       0x24 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable7printlnEc
-                0x0000000000000000       0x28 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable7printlnEb
-                0x0000000000000000       0x24 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable7printlnEd
-                0x0000000000000000       0x24 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable7printlnEhNS_11IntegerBaseE
-                0x0000000000000000       0x28 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable7printlnEtNS_11IntegerBaseE
-                0x0000000000000000       0x28 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable7printlnEmNS_11IntegerBaseE
-                0x0000000000000000       0x24 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable7printlnEPKc
-                0x0000000000000000       0x24 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable7printlnEPKcj
-                0x0000000000000000       0x28 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable9printBaseEyNS_11IntegerBaseEPKcj
-                0x0000000000000000       0x70 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable8printDecEyPKc
-                0x0000000000000000       0x2e ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable8printBinEyj
-                0x0000000000000000       0x94 ./Libs/sta-core/src/debug/printing/printable.o
- .text._ZN3sta9Printable8printHexEyj
-                0x0000000000000000       0xbc ./Libs/sta-core/src/debug/printing/printable.o
- .debug_info    0x0000000000000000     0x1771 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_abbrev  0x0000000000000000      0x308 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_aranges
-                0x0000000000000000       0xb8 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_rnglists
-                0x0000000000000000       0x87 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000      0x20c ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x61 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x2a ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x43 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x3a ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x35 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000      0x460 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x43 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x34 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x58 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000      0x177 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000      0x38c ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x20 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000      0x139 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000      0x11d ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_macro   0x0000000000000000       0x46 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_line    0x0000000000000000      0xbd4 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_str     0x0000000000000000     0xb56e ./Libs/sta-core/src/debug/printing/printable.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/debug/printing/printable.o
- .debug_frame   0x0000000000000000      0x300 ./Libs/sta-core/src/debug/printing/printable.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/debug/printing/printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .text._ZN3sta9PrintableC2Ev
-                0x0000000000000000       0x20 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .text._ZN3sta15PrintablePrintfC2Ev
-                0x0000000000000000       0x24 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .rodata        0x0000000000000000       0x5d ./Libs/sta-core/src/debug/printing/printable_printf.o
- .text._ZN3sta15PrintablePrintf5printEPKcj
-                0x0000000000000000       0x58 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .rodata._ZTVN3sta15PrintablePrintfE
-                0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .rodata._ZTVN3sta9PrintableE
-                0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_info    0x0000000000000000     0x12cb ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_abbrev  0x0000000000000000      0x3ed ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_aranges
-                0x0000000000000000       0x30 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_rnglists
-                0x0000000000000000       0x1f ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000      0x1b4 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x61 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x2a ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x43 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x34 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x35 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000      0x38c ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x43 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x34 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x58 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000      0x177 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000      0x139 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_macro   0x0000000000000000      0x11d ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_line    0x0000000000000000      0x8e4 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_str     0x0000000000000000     0xa37a ./Libs/sta-core/src/debug/printing/printable_printf.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .debug_frame   0x0000000000000000       0x80 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/debug/printing/printable_printf.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .text._ZN3sta9PrintableC2Ev
-                0x0000000000000000       0x20 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .rodata        0x0000000000000000       0x9a ./Libs/sta-core/src/debug/printing/printable_uart.o
- .text._ZN3sta13PrintableUARTC2EPNS_4UARTE
-                0x0000000000000000       0x78 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .text._ZN3sta13PrintableUART5printEPKcj
-                0x0000000000000000       0x2a ./Libs/sta-core/src/debug/printing/printable_uart.o
- .rodata._ZTVN3sta13PrintableUARTE
-                0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .rodata._ZTVN3sta9PrintableE
-                0x0000000000000000        0xc ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_info    0x0000000000000000     0x1535 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_abbrev  0x0000000000000000      0x41b ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_aranges
-                0x0000000000000000       0x30 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_rnglists
-                0x0000000000000000       0x1f ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000      0x244 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x61 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x2a ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x43 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x34 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x35 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000      0x38c ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x43 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x34 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x58 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000      0x177 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000      0x139 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000      0x11d ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000      0x460 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x20 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_line    0x0000000000000000      0xa93 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_str     0x0000000000000000     0xb691 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .debug_frame   0x0000000000000000       0x80 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/debug/printing/printable_uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/arduino/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/arduino/bus/i2c.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/arduino/bus/i2c.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/arduino/bus/i2c.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/arduino/bus/i2c.o
- .debug_info    0x0000000000000000       0x22 ./Libs/sta-core/src/devices/arduino/bus/i2c.o
- .debug_abbrev  0x0000000000000000       0x12 ./Libs/sta-core/src/devices/arduino/bus/i2c.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Libs/sta-core/src/devices/arduino/bus/i2c.o
- .debug_macro   0x0000000000000000       0x24 ./Libs/sta-core/src/devices/arduino/bus/i2c.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/arduino/bus/i2c.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/arduino/bus/i2c.o
- .debug_line    0x0000000000000000       0xdf ./Libs/sta-core/src/devices/arduino/bus/i2c.o
- .debug_str     0x0000000000000000     0x328a ./Libs/sta-core/src/devices/arduino/bus/i2c.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/arduino/bus/i2c.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/arduino/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/arduino/bus/spi.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/arduino/bus/spi.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/arduino/bus/spi.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/arduino/bus/spi.o
- .debug_info    0x0000000000000000       0x22 ./Libs/sta-core/src/devices/arduino/bus/spi.o
- .debug_abbrev  0x0000000000000000       0x12 ./Libs/sta-core/src/devices/arduino/bus/spi.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Libs/sta-core/src/devices/arduino/bus/spi.o
- .debug_macro   0x0000000000000000       0x11 ./Libs/sta-core/src/devices/arduino/bus/spi.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/arduino/bus/spi.o
- .debug_line    0x0000000000000000       0x51 ./Libs/sta-core/src/devices/arduino/bus/spi.o
- .debug_str     0x0000000000000000     0x3201 ./Libs/sta-core/src/devices/arduino/bus/spi.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/arduino/bus/spi.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/arduino/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/arduino/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/arduino/delay.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/arduino/delay.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/arduino/delay.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/arduino/delay.o
- .debug_info    0x0000000000000000       0x22 ./Libs/sta-core/src/devices/arduino/delay.o
- .debug_abbrev  0x0000000000000000       0x12 ./Libs/sta-core/src/devices/arduino/delay.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Libs/sta-core/src/devices/arduino/delay.o
- .debug_macro   0x0000000000000000       0x24 ./Libs/sta-core/src/devices/arduino/delay.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/arduino/delay.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/arduino/delay.o
- .debug_line    0x0000000000000000       0xdb ./Libs/sta-core/src/devices/arduino/delay.o
- .debug_str     0x0000000000000000     0x328a ./Libs/sta-core/src/devices/arduino/delay.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/arduino/delay.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/arduino/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/arduino/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/arduino/gpio_pin.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/arduino/gpio_pin.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/arduino/gpio_pin.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/arduino/gpio_pin.o
- .debug_info    0x0000000000000000       0x22 ./Libs/sta-core/src/devices/arduino/gpio_pin.o
- .debug_abbrev  0x0000000000000000       0x12 ./Libs/sta-core/src/devices/arduino/gpio_pin.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Libs/sta-core/src/devices/arduino/gpio_pin.o
- .debug_macro   0x0000000000000000       0x24 ./Libs/sta-core/src/devices/arduino/gpio_pin.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/arduino/gpio_pin.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/arduino/gpio_pin.o
- .debug_line    0x0000000000000000       0xe1 ./Libs/sta-core/src/devices/arduino/gpio_pin.o
- .debug_str     0x0000000000000000     0x3290 ./Libs/sta-core/src/devices/arduino/gpio_pin.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/arduino/gpio_pin.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/arduino/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/raspi/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/raspi/bus/i2c.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/raspi/bus/i2c.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/raspi/bus/i2c.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/raspi/bus/i2c.o
- .debug_info    0x0000000000000000       0x22 ./Libs/sta-core/src/devices/raspi/bus/i2c.o
- .debug_abbrev  0x0000000000000000       0x12 ./Libs/sta-core/src/devices/raspi/bus/i2c.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Libs/sta-core/src/devices/raspi/bus/i2c.o
- .debug_macro   0x0000000000000000       0x24 ./Libs/sta-core/src/devices/raspi/bus/i2c.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/raspi/bus/i2c.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/raspi/bus/i2c.o
- .debug_line    0x0000000000000000       0xdb ./Libs/sta-core/src/devices/raspi/bus/i2c.o
- .debug_str     0x0000000000000000     0x3281 ./Libs/sta-core/src/devices/raspi/bus/i2c.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/raspi/bus/i2c.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/raspi/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/raspi/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/raspi/bus/spi.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/raspi/bus/spi.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/raspi/bus/spi.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/raspi/bus/spi.o
- .debug_info    0x0000000000000000       0x22 ./Libs/sta-core/src/devices/raspi/bus/spi.o
- .debug_abbrev  0x0000000000000000       0x12 ./Libs/sta-core/src/devices/raspi/bus/spi.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Libs/sta-core/src/devices/raspi/bus/spi.o
- .debug_macro   0x0000000000000000       0x24 ./Libs/sta-core/src/devices/raspi/bus/spi.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/raspi/bus/spi.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/raspi/bus/spi.o
- .debug_line    0x0000000000000000       0xdb ./Libs/sta-core/src/devices/raspi/bus/spi.o
- .debug_str     0x0000000000000000     0x3286 ./Libs/sta-core/src/devices/raspi/bus/spi.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/raspi/bus/spi.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/raspi/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/raspi/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/raspi/delay.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/raspi/delay.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/raspi/delay.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/raspi/delay.o
- .debug_info    0x0000000000000000       0x22 ./Libs/sta-core/src/devices/raspi/delay.o
- .debug_abbrev  0x0000000000000000       0x12 ./Libs/sta-core/src/devices/raspi/delay.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Libs/sta-core/src/devices/raspi/delay.o
- .debug_macro   0x0000000000000000       0x24 ./Libs/sta-core/src/devices/raspi/delay.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/raspi/delay.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/raspi/delay.o
- .debug_line    0x0000000000000000       0xd7 ./Libs/sta-core/src/devices/raspi/delay.o
- .debug_str     0x0000000000000000     0x3286 ./Libs/sta-core/src/devices/raspi/delay.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/raspi/delay.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/raspi/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/raspi/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/raspi/gpio_pin.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/raspi/gpio_pin.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/raspi/gpio_pin.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/raspi/gpio_pin.o
- .debug_info    0x0000000000000000       0x22 ./Libs/sta-core/src/devices/raspi/gpio_pin.o
- .debug_abbrev  0x0000000000000000       0x12 ./Libs/sta-core/src/devices/raspi/gpio_pin.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Libs/sta-core/src/devices/raspi/gpio_pin.o
- .debug_macro   0x0000000000000000       0x24 ./Libs/sta-core/src/devices/raspi/gpio_pin.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/raspi/gpio_pin.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/raspi/gpio_pin.o
- .debug_line    0x0000000000000000       0xdd ./Libs/sta-core/src/devices/raspi/gpio_pin.o
- .debug_str     0x0000000000000000     0x328c ./Libs/sta-core/src/devices/raspi/gpio_pin.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/raspi/gpio_pin.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/raspi/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/adc.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/adc.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/adc.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_info    0x0000000000000000       0x75 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_abbrev  0x0000000000000000       0x2f ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x1f0 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x29b ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0x2e ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0x2f ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0xd9 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000     0x102d ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x11f ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000    0x15e82 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0x6d ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000     0x367e ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0x5c ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x96b ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x9fe ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x115 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x13e ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0xa5 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x174 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x287 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0x5f ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x236 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x40f ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x12c ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x21e ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0x2e ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x11a ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0x7e ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000       0x89 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x295 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_macro   0x0000000000000000      0x12d ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_line    0x0000000000000000      0x7b2 ./Libs/sta-core/src/devices/stm32/adc.o
- .debug_str     0x0000000000000000    0xbede9 ./Libs/sta-core/src/devices/stm32/adc.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/stm32/adc.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/stm32/adc.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/can.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/can.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/can.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/can.o
- .text._ZN3sta18STM32CanController18enableRxInterruptsEv
-                0x0000000000000000       0x1c ./Libs/sta-core/src/devices/stm32/can.o
- .text._ZN3sta18STM32CanController4stopEv
-                0x0000000000000000       0x1a ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x29b ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x2e ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x2f ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0xd9 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000     0x102d ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x11f ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000    0x15e82 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x6d ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000     0x367e ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x5c ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x96b ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x9fe ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x115 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x13e ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0xa5 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x174 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x287 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x5f ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x236 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x40f ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x12c ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x21e ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x2e ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x11a ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x7e ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x89 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x295 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x12d ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x0000000000000000       0x46 ./Libs/sta-core/src/devices/stm32/can.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/delay.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/delay.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/delay.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/delay.o
- .text._ZN3sta7delayMsEm
-                0x0000000000000000       0x16 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_info    0x0000000000000000      0x3c2 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_abbrev  0x0000000000000000       0xbc ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_aranges
-                0x0000000000000000       0x20 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_rnglists
-                0x0000000000000000       0x13 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x238 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x29b ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x2e ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x2f ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0xd9 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000     0x102d ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x11f ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000    0x15e82 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x6d ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000     0x367e ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x5c ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x96b ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x9fe ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x115 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x13e ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0xa5 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x174 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x287 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x5f ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x236 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x40f ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x12c ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x21e ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x2e ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x11a ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x7e ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x89 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x295 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000      0x12d ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x40 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x2e ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_macro   0x0000000000000000       0x46 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_line    0x0000000000000000      0xa97 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_str     0x0000000000000000    0xc0fb3 ./Libs/sta-core/src/devices/stm32/delay.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/stm32/delay.o
- .debug_frame   0x0000000000000000       0x34 ./Libs/sta-core/src/devices/stm32/delay.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/stm32/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .text._ZN3sta7GpioPinC2Ev
-                0x0000000000000000       0x20 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .rodata        0x0000000000000000       0x46 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .text._ZN3sta12STM32GpioPinC2EP12GPIO_TypeDeft
-                0x0000000000000000       0x54 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .text._ZN3sta12STM32GpioPin8setStateENS_12GpioPinStateE
-                0x0000000000000000       0x2c ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .text._ZN3sta12STM32GpioPin8getStateEv
-                0x0000000000000000       0x2c ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .text._ZNK3sta12STM32GpioPin7getPortEv
-                0x0000000000000000       0x18 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .text._ZNK3sta12STM32GpioPin6getPinEv
-                0x0000000000000000       0x18 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .text._ZNK3sta12STM32GpioPin12getPortIndexEv
-                0x0000000000000000       0xa8 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .text._ZN3sta15isInterruptEdgeERKNS_12STM32GpioPinENS_13InterruptEdgeE
-                0x0000000000000000       0xf0 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .rodata._ZTVN3sta12STM32GpioPinE
-                0x0000000000000000       0x10 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .rodata._ZTVN3sta7GpioPinE
-                0x0000000000000000       0x10 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_info    0x0000000000000000      0x9ff ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_abbrev  0x0000000000000000      0x397 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_aranges
-                0x0000000000000000       0x58 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_rnglists
-                0x0000000000000000       0x3f ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x24a ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x29b ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x2e ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x2f ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0xd9 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000     0x102d ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x11f ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000    0x15e82 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x6d ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000     0x367e ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x5c ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x96b ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x9fe ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x115 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x13e ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0xa5 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x174 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x287 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x5f ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x236 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x40f ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x12c ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x21e ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x2e ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x11a ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x7e ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x89 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x295 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x12d ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_macro   0x0000000000000000       0x46 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_line    0x0000000000000000      0xc3d ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_str     0x0000000000000000    0xc1152 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .debug_frame   0x0000000000000000      0x140 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/stm32/gpio_pin.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/init.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/init.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/init.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/init.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/init.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/init.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/init.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/init.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/init.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/init.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/init.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/init.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/init.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/init.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/init.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/init.o
- .text._ZN3sta7initHALEv
-                0x0000000000000000        0xe ./Libs/sta-core/src/devices/stm32/init.o
- .debug_info    0x0000000000000000      0x38f ./Libs/sta-core/src/devices/stm32/init.o
- .debug_abbrev  0x0000000000000000       0x8a ./Libs/sta-core/src/devices/stm32/init.o
- .debug_aranges
-                0x0000000000000000       0x20 ./Libs/sta-core/src/devices/stm32/init.o
- .debug_rnglists
-                0x0000000000000000       0x13 ./Libs/sta-core/src/devices/stm32/init.o
- .debug_macro   0x0000000000000000       0xbd ./Libs/sta-core/src/devices/stm32/init.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/stm32/init.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/init.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/devices/stm32/init.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/devices/stm32/init.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/devices/stm32/init.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/devices/stm32/init.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/init.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/devices/stm32/init.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/devices/stm32/init.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/devices/stm32/init.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/devices/stm32/init.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/devices/stm32/init.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/init.o
- .debug_line    0x0000000000000000      0x705 ./Libs/sta-core/src/devices/stm32/init.o
- .debug_str     0x0000000000000000     0x5f23 ./Libs/sta-core/src/devices/stm32/init.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/stm32/init.o
- .debug_frame   0x0000000000000000       0x30 ./Libs/sta-core/src/devices/stm32/init.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/stm32/init.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_info    0x0000000000000000      0x42a ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_abbrev  0x0000000000000000       0x9c ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x302 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x29b ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x2e ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x2f ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0xd9 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000     0x102d ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x11f ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000    0x15e82 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x6d ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000     0x367e ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x5c ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x96b ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x9fe ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x115 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x13e ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0xa5 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x174 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x287 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x5f ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x236 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x40f ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x12c ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x21e ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x2e ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x11a ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x7e ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x89 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x295 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x12d ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x61 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x2a ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x43 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x34 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x43 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x34 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x58 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x177 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000      0x38c ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x35 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x20 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_line    0x0000000000000000      0xbe4 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .debug_str     0x0000000000000000    0xc3d84 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/stm32/bus/i2c.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_info    0x0000000000000000       0x75 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_abbrev  0x0000000000000000       0x2f ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x1f0 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x29b ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0x2e ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0x2f ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0xd9 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000     0x102d ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x11f ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000    0x15e82 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0x6d ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000     0x367e ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0x5c ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x96b ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x9fe ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x115 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x13e ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0xa5 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x174 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x287 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0x5f ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x236 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x40f ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x12c ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x21e ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0x2e ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x11a ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0x7e ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000       0x89 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x295 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_macro   0x0000000000000000      0x12d ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_line    0x0000000000000000      0x819 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .debug_str     0x0000000000000000    0xbeded ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/stm32/bus/spi.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .rodata        0x0000000000000000       0x56 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .text._ZN3sta9STM32UARTC2EP20__UART_HandleTypeDefRNS_12UARTSettingsEPNS_5MutexE
-                0x0000000000000000       0x50 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .text._ZN3sta9STM32UART8transferEh
-                0x0000000000000000       0x24 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .text._ZN3sta9STM32UART10transfer16Et
-                0x0000000000000000       0x24 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .text._ZN3sta9STM32UART8transferEPKhj
-                0x0000000000000000       0x44 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .text._ZN3sta9STM32UART7receiveEPhj
-                0x0000000000000000       0x44 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .text._ZN3sta9STM32UART4fillEhj
-                0x0000000000000000       0x4a ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .rodata._ZTVN3sta9STM32UARTE
-                0x0000000000000000       0x24 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_info    0x0000000000000000      0xed0 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_abbrev  0x0000000000000000      0x35d ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_aranges
-                0x0000000000000000       0x48 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_rnglists
-                0x0000000000000000       0x31 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x338 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x29b ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x2e ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x2f ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x51 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x103 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x6a ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x1df ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x1c ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0xd9 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000     0x102d ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x11f ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000    0x15e82 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x6d ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000     0x367e ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x17b ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x5c ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x96b ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x9fe ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x115 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x13e ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0xa5 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x174 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x287 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x5f ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x236 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x40f ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x12c ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x21e ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x2e ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x11a ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x7e ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x89 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x295 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x12d ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x1b2 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x3ed ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x28 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x2e ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x61 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x2a ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x43 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x34 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x43 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x34 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x58 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x16 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x177 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000      0x38c ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x10 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x35 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x20 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_macro   0x0000000000000000       0x8e ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_line    0x0000000000000000      0xde4 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_str     0x0000000000000000    0xc46bd ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .debug_frame   0x0000000000000000       0xe8 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/stm32/bus/uart.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/template/custom_printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/template/custom_printable.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/template/custom_printable.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/template/custom_printable.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/template/custom_printable.o
- .debug_info    0x0000000000000000       0x22 ./Libs/sta-core/src/devices/template/custom_printable.o
- .debug_abbrev  0x0000000000000000       0x12 ./Libs/sta-core/src/devices/template/custom_printable.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Libs/sta-core/src/devices/template/custom_printable.o
- .debug_macro   0x0000000000000000       0x24 ./Libs/sta-core/src/devices/template/custom_printable.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/template/custom_printable.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/template/custom_printable.o
- .debug_line    0x0000000000000000       0xf3 ./Libs/sta-core/src/devices/template/custom_printable.o
- .debug_str     0x0000000000000000     0x32a5 ./Libs/sta-core/src/devices/template/custom_printable.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/template/custom_printable.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/template/custom_printable.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/template/delay.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/devices/template/delay.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/template/delay.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/devices/template/delay.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/devices/template/delay.o
- .debug_info    0x0000000000000000       0x22 ./Libs/sta-core/src/devices/template/delay.o
- .debug_abbrev  0x0000000000000000       0x12 ./Libs/sta-core/src/devices/template/delay.o
- .debug_aranges
-                0x0000000000000000       0x18 ./Libs/sta-core/src/devices/template/delay.o
- .debug_macro   0x0000000000000000       0x24 ./Libs/sta-core/src/devices/template/delay.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/devices/template/delay.o
- .debug_macro   0x0000000000000000       0x22 ./Libs/sta-core/src/devices/template/delay.o
- .debug_line    0x0000000000000000       0xdd ./Libs/sta-core/src/devices/template/delay.o
- .debug_str     0x0000000000000000     0x328f ./Libs/sta-core/src/devices/template/delay.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/devices/template/delay.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/devices/template/delay.o
- .group         0x0000000000000000        0x8 ./Libs/sta-core/src/mutex.o
- .group         0x0000000000000000        0x8 ./Libs/sta-core/src/mutex.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/mutex.o
- .group         0x0000000000000000        0xc ./Libs/sta-core/src/mutex.o
- .text          0x0000000000000000        0x0 ./Libs/sta-core/src/mutex.o
- .data          0x0000000000000000        0x0 ./Libs/sta-core/src/mutex.o
- .bss           0x0000000000000000        0x0 ./Libs/sta-core/src/mutex.o
- .text._ZN3sta10DummyMutex7acquireEv
-                0x0000000000000000       0x14 ./Libs/sta-core/src/mutex.o
- .text._ZN3sta10DummyMutex7releaseEv
-                0x0000000000000000       0x14 ./Libs/sta-core/src/mutex.o
- .data._ZN3staL10dummyMutexE
-                0x0000000000000000        0x4 ./Libs/sta-core/src/mutex.o
- .data._ZN3sta5Mutex11ALWAYS_FREEE
-                0x0000000000000000        0x4 ./Libs/sta-core/src/mutex.o
- .rodata._ZTVN3sta10DummyMutexE
-                0x0000000000000000       0x10 ./Libs/sta-core/src/mutex.o
- .debug_info    0x0000000000000000      0x2a9 ./Libs/sta-core/src/mutex.o
- .debug_abbrev  0x0000000000000000      0x16c ./Libs/sta-core/src/mutex.o
- .debug_aranges
-                0x0000000000000000       0x28 ./Libs/sta-core/src/mutex.o
- .debug_rnglists
-                0x0000000000000000       0x19 ./Libs/sta-core/src/mutex.o
- .debug_macro   0x0000000000000000       0x1b ./Libs/sta-core/src/mutex.o
- .debug_macro   0x0000000000000000      0xb80 ./Libs/sta-core/src/mutex.o
- .debug_line    0x0000000000000000       0xc5 ./Libs/sta-core/src/mutex.o
- .debug_str     0x0000000000000000     0x33ad ./Libs/sta-core/src/mutex.o
- .comment       0x0000000000000000       0x44 ./Libs/sta-core/src/mutex.o
- .debug_frame   0x0000000000000000       0x60 ./Libs/sta-core/src/mutex.o
- .ARM.attributes
-                0x0000000000000000       0x34 ./Libs/sta-core/src/mutex.o
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(del_opv.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(del_opv.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(del_opv.o)
- .text._ZdaPv   0x0000000000000000        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(del_opv.o)
- .debug_frame   0x0000000000000000       0x20 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(del_opv.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(del_opv.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_opv.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_opv.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_opv.o)
- .text._Znaj    0x0000000000000000        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_opv.o)
- .debug_frame   0x0000000000000000       0x20 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_opv.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_opv.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(del_op.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(del_op.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(del_op.o)
- .text._ZdlPv   0x0000000000000000        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(del_op.o)
- .debug_frame   0x0000000000000000       0x20 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(del_op.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(del_op.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_op.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_op.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_op.o)
- .text._Znwj    0x0000000000000000       0x22 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_op.o)
- .debug_frame   0x0000000000000000       0x28 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_op.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_op.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_handler.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_handler.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_handler.o)
- .text._ZSt15set_new_handlerPFvvE
-                0x0000000000000000       0x20 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_handler.o)
- .text._ZSt15get_new_handlerv
-                0x0000000000000000       0x10 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_handler.o)
- .bss._ZN12_GLOBAL__N_113__new_handlerE
-                0x0000000000000000        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_handler.o)
- .rodata._ZSt7nothrow
-                0x0000000000000000        0x1 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_handler.o)
- .debug_frame   0x0000000000000000       0x30 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_handler.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a(new_handler.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-abort.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-abort.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-abort.o)
- .text.abort    0x0000000000000000        0xe C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-abort.o)
- .debug_frame   0x0000000000000000       0x28 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-abort.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-abort.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-exit.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-exit.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-exit.o)
- .text.exit     0x0000000000000000       0x24 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-exit.o)
- .debug_frame   0x0000000000000000       0x28 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-exit.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-exit.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-malloc.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-malloc.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-malloc.o)
- .text.malloc   0x0000000000000000       0x10 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-malloc.o)
- .text.free     0x0000000000000000       0x10 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-malloc.o)
- .debug_frame   0x0000000000000000       0x30 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-malloc.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-malloc.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o)
- .text.sbrk_aligned
-                0x0000000000000000       0x40 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o)
- .text._malloc_r
-                0x0000000000000000      0x100 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o)
- .bss.__malloc_free_list
-                0x0000000000000000        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o)
- .bss.__malloc_sbrk_start
-                0x0000000000000000        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o)
- .debug_frame   0x0000000000000000       0x50 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mlock.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mlock.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mlock.o)
- .text.__malloc_lock
-                0x0000000000000000        0xc C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mlock.o)
- .text.__malloc_unlock
-                0x0000000000000000        0xc C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mlock.o)
- .debug_frame   0x0000000000000000       0x30 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mlock.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mlock.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .text.std      0x0000000000000000       0x48 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .text.stdio_exit_handler
-                0x0000000000000000       0x18 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .text.cleanup_stdio
-                0x0000000000000000       0x40 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .text.__fp_lock
-                0x0000000000000000       0x18 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .text.__fp_unlock
-                0x0000000000000000       0x18 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .text.global_stdio_init.part.0
-                0x0000000000000000       0x3c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .text.__sfp_lock_acquire
-                0x0000000000000000        0xc C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .text.__sfp_lock_release
-                0x0000000000000000        0xc C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .text.__sfp    0x0000000000000000       0xa8 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .text.__sinit  0x0000000000000000       0x30 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .text.__fp_lock_all
-                0x0000000000000000       0x1c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .text.__fp_unlock_all
-                0x0000000000000000       0x1c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .bss.__sf      0x0000000000000000      0x138 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .bss.__stdio_exit_handler
-                0x0000000000000000        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .data.__sglue  0x0000000000000000        0xc C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .debug_frame   0x0000000000000000      0x13c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fwalk.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fwalk.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fwalk.o)
- .text._fwalk_sglue
-                0x0000000000000000       0x3c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fwalk.o)
- .debug_frame   0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fwalk.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fwalk.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-printf.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-printf.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-printf.o)
- .text._printf_r
-                0x0000000000000000       0x1c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-printf.o)
- .text.printf   0x0000000000000000       0x24 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-printf.o)
- .debug_frame   0x0000000000000000       0x6c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-printf.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-printf.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-snprintf.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-snprintf.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-snprintf.o)
- .text._snprintf_r
-                0x0000000000000000       0x5e C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-snprintf.o)
- .text.snprintf
-                0x0000000000000000       0x68 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-snprintf.o)
- .debug_frame   0x0000000000000000       0x7c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-snprintf.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-snprintf.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-stdio.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-stdio.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-stdio.o)
- .text.__sread  0x0000000000000000       0x22 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-stdio.o)
- .text.__seofread
-                0x0000000000000000        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-stdio.o)
- .text.__swrite
-                0x0000000000000000       0x38 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-stdio.o)
- .text.__sseek  0x0000000000000000       0x24 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-stdio.o)
- .text.__sclose
-                0x0000000000000000        0x8 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-stdio.o)
- .debug_frame   0x0000000000000000       0x88 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-stdio.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-stdio.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memset.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memset.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memset.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signal.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signal.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signal.o)
- .text._init_signal_r
-                0x0000000000000000       0x28 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signal.o)
- .text._signal_r
-                0x0000000000000000       0x30 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signal.o)
- .text._raise_r
-                0x0000000000000000       0x50 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signal.o)
- .text.__sigtramp_r
-                0x0000000000000000       0x48 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signal.o)
- .text.raise    0x0000000000000000       0x10 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signal.o)
- .text.signal   0x0000000000000000       0x10 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signal.o)
- .text._init_signal
-                0x0000000000000000        0xc C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signal.o)
- .text.__sigtramp
-                0x0000000000000000       0x10 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signal.o)
- .debug_frame   0x0000000000000000       0xcc C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signal.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signal.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-closer.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-closer.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-closer.o)
- .text._close_r
-                0x0000000000000000       0x20 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-closer.o)
- .debug_frame   0x0000000000000000       0x2c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-closer.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-closer.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reent.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reent.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reent.o)
- .text._reclaim_reent
-                0x0000000000000000       0xac C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reent.o)
- .bss.errno     0x0000000000000000        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reent.o)
- .debug_frame   0x0000000000000000       0x38 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reent.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reent.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-impure.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-impure.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-impure.o)
- .data._impure_data
-                0x0000000000000000       0x4c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-impure.o)
- .data._impure_ptr
-                0x0000000000000000        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-impure.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-impure.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lseekr.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lseekr.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lseekr.o)
- .text._lseek_r
-                0x0000000000000000       0x24 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lseekr.o)
- .debug_frame   0x0000000000000000       0x2c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lseekr.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lseekr.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-readr.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-readr.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-readr.o)
- .text._read_r  0x0000000000000000       0x24 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-readr.o)
- .debug_frame   0x0000000000000000       0x2c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-readr.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-readr.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signalr.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signalr.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signalr.o)
- .text._kill_r  0x0000000000000000       0x24 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signalr.o)
- .text._getpid_r
-                0x0000000000000000        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signalr.o)
- .debug_frame   0x0000000000000000       0x3c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signalr.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-signalr.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-sbrkr.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-sbrkr.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-sbrkr.o)
- .text._sbrk_r  0x0000000000000000       0x20 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-sbrkr.o)
- .debug_frame   0x0000000000000000       0x2c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-sbrkr.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-sbrkr.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-writer.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-writer.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-writer.o)
- .text._write_r
-                0x0000000000000000       0x24 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-writer.o)
- .debug_frame   0x0000000000000000       0x2c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-writer.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-writer.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-errno.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-errno.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-errno.o)
- .text.__errno  0x0000000000000000        0xc C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-errno.o)
- .debug_frame   0x0000000000000000       0x20 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-errno.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-errno.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-init.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-init.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-init.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .text.__retarget_lock_init
-                0x0000000000000000        0x2 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .text.__retarget_lock_init_recursive
-                0x0000000000000000        0x2 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .text.__retarget_lock_close
-                0x0000000000000000        0x2 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .text.__retarget_lock_close_recursive
-                0x0000000000000000        0x2 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .text.__retarget_lock_acquire
-                0x0000000000000000        0x2 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .text.__retarget_lock_acquire_recursive
-                0x0000000000000000        0x2 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .text.__retarget_lock_try_acquire
-                0x0000000000000000        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .text.__retarget_lock_try_acquire_recursive
-                0x0000000000000000        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .text.__retarget_lock_release
-                0x0000000000000000        0x2 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .text.__retarget_lock_release_recursive
-                0x0000000000000000        0x2 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .bss.__lock___arc4random_mutex
-                0x0000000000000000        0x1 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .bss.__lock___at_quick_exit_mutex
-                0x0000000000000000        0x1 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .bss.__lock___atexit_recursive_mutex
-                0x0000000000000000        0x1 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .bss.__lock___dd_hash_mutex
-                0x0000000000000000        0x1 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .bss.__lock___env_recursive_mutex
-                0x0000000000000000        0x1 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .bss.__lock___malloc_recursive_mutex
-                0x0000000000000000        0x1 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .bss.__lock___sfp_recursive_mutex
-                0x0000000000000000        0x1 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .bss.__lock___tz_mutex
-                0x0000000000000000        0x1 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .debug_frame   0x0000000000000000       0xb0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o)
- .text          0x0000000000000000       0x10 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-strlen.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-strlen.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-strlen.o)
- .ARM.attributes
-                0x0000000000000000       0x17 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-strlen.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-freer.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-freer.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-freer.o)
- .text._free_r  0x0000000000000000       0x98 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-freer.o)
- .debug_frame   0x0000000000000000       0x38 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-freer.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-freer.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o)
- .text.__ssputs_r
-                0x0000000000000000       0xb4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o)
- .text.__ssprint_r
-                0x0000000000000000       0xfa C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o)
- .rodata._svfprintf_r.str1.1
-                0x0000000000000000       0x11 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o)
- .text._svfprintf_r
-                0x0000000000000000      0x1fc C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o)
- .debug_frame   0x0000000000000000       0x90 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-svfprintf.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o)
- .text.__sfputc_r
-                0x0000000000000000       0x2e C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o)
- .text.__sfputs_r
-                0x0000000000000000       0x24 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o)
- .text.__sprint_r
-                0x0000000000000000       0x1a C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o)
- .rodata._vfprintf_r.str1.1
-                0x0000000000000000       0x11 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o)
- .text._vfprintf_r
-                0x0000000000000000      0x234 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o)
- .text.vfprintf
-                0x0000000000000000       0x14 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o)
- .debug_frame   0x0000000000000000       0xa8 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf_i.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf_i.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf_i.o)
- .text._printf_common
-                0x0000000000000000       0xda C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf_i.o)
- .rodata._printf_i.str1.1
-                0x0000000000000000       0x22 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf_i.o)
- .text._printf_i
-                0x0000000000000000      0x244 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf_i.o)
- .debug_frame   0x0000000000000000       0x60 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf_i.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-nano-vfprintf_i.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fflush.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fflush.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fflush.o)
- .text.__sflush_r
-                0x0000000000000000      0x10c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fflush.o)
- .text._fflush_r
-                0x0000000000000000       0x50 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fflush.o)
- .text.fflush   0x0000000000000000       0x28 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fflush.o)
- .debug_frame   0x0000000000000000       0x5c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fflush.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fflush.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fvwrite.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fvwrite.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fvwrite.o)
- .text.__sfvwrite_r
-                0x0000000000000000      0x294 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fvwrite.o)
- .debug_frame   0x0000000000000000       0x3c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fvwrite.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fvwrite.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-wbuf.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-wbuf.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-wbuf.o)
- .text.__swbuf_r
-                0x0000000000000000       0x7a C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-wbuf.o)
- .text.__swbuf  0x0000000000000000       0x10 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-wbuf.o)
- .debug_frame   0x0000000000000000       0x40 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-wbuf.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-wbuf.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-wsetup.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-wsetup.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-wsetup.o)
- .text.__swsetup_r
-                0x0000000000000000       0xb0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-wsetup.o)
- .debug_frame   0x0000000000000000       0x2c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-wsetup.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-wsetup.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memmove.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memmove.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memmove.o)
- .text.memmove  0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memmove.o)
- .debug_frame   0x0000000000000000       0x28 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memmove.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memmove.o)
- .text          0x0000000000000000       0xa0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memchr.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memchr.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memchr.o)
- .ARM.attributes
-                0x0000000000000000       0x1c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memchr.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memcpy-stub.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memcpy-stub.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memcpy-stub.o)
- .text.memcpy   0x0000000000000000       0x1c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memcpy-stub.o)
- .debug_frame   0x0000000000000000       0x28 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memcpy-stub.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memcpy-stub.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reallocr.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reallocr.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reallocr.o)
- .text._realloc_r
-                0x0000000000000000       0x5e C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reallocr.o)
- .debug_frame   0x0000000000000000       0x3c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reallocr.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reallocr.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-makebuf.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-makebuf.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-makebuf.o)
- .text.__swhatbuf_r
-                0x0000000000000000       0x4c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-makebuf.o)
- .text.__smakebuf_r
-                0x0000000000000000       0x78 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-makebuf.o)
- .debug_frame   0x0000000000000000       0x58 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-makebuf.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-makebuf.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fstatr.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fstatr.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fstatr.o)
- .text._fstat_r
-                0x0000000000000000       0x24 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fstatr.o)
- .debug_frame   0x0000000000000000       0x2c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fstatr.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-fstatr.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-isattyr.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-isattyr.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-isattyr.o)
- .text._isatty_r
-                0x0000000000000000       0x20 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-isattyr.o)
- .debug_frame   0x0000000000000000       0x2c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-isattyr.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-isattyr.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-msizer.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-msizer.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-msizer.o)
- .text._malloc_usable_size_r
-                0x0000000000000000       0x10 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-msizer.o)
- .debug_frame   0x0000000000000000       0x20 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-msizer.o)
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-msizer.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_aeabi_uldivmod.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_aeabi_uldivmod.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o)
- .ARM.extab     0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o)
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_dvmd_tls.o)
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_dvmd_tls.o)
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtend.o
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtend.o
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtend.o
- .rodata        0x0000000000000000       0x24 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtend.o
- .eh_frame      0x0000000000000000        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtend.o
- .comment       0x0000000000000000       0x44 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtend.o
- .ARM.attributes
-                0x0000000000000000       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtend.o
- .text          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtn.o
- .data          0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtn.o
- .bss           0x0000000000000000        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtn.o
-
-Memory Configuration
-
-Name             Origin             Length             Attributes
-CCMRAM           0x0000000010000000 0x0000000000010000 xrw
-RAM              0x0000000020000000 0x0000000000020000 xrw
-FLASH            0x0000000008000000 0x0000000000100000 xr
-*default*        0x0000000000000000 0xffffffffffffffff
-
-Linker script and memory map
-
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crti.o
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard/crt0.o
-LOAD ./App/Src/test.o
-LOAD ./Core/Src/main.o
-LOAD ./Core/Src/stm32f4xx_hal_msp.o
-LOAD ./Core/Src/stm32f4xx_it.o
-LOAD ./Core/Src/syscalls.o
-LOAD ./Core/Src/sysmem.o
-LOAD ./Core/Src/system_stm32f4xx.o
-LOAD ./Core/Startup/startup_stm32f407zgtx.o
-LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
-LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
-LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
-LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o
-LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o
-LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o
-LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o
-LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o
-LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o
-LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
-LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o
-LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o
-LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
-LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o
-LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
-LOAD ./Libs/sta-core/src/atomic/mutex.o
-LOAD ./Libs/sta-core/src/atomic/signal.o
-LOAD ./Libs/sta-core/src/bus/device.o
-LOAD ./Libs/sta-core/src/bus/interface.o
-LOAD ./Libs/sta-core/src/bus/i2c/device.o
-LOAD ./Libs/sta-core/src/bus/i2c/i2c.o
-LOAD ./Libs/sta-core/src/bus/spi/device.o
-LOAD ./Libs/sta-core/src/bus/spi/settings.o
-LOAD ./Libs/sta-core/src/bus/spi/spi.o
-LOAD ./Libs/sta-core/src/bus/uart/settings.o
-LOAD ./Libs/sta-core/src/bus/uart/uart.o
-LOAD ./Libs/sta-core/src/can/id.o
-LOAD ./Libs/sta-core/src/can/iter.o
-LOAD ./Libs/sta-core/src/debug/assert.o
-LOAD ./Libs/sta-core/src/debug/printing/printable.o
-LOAD ./Libs/sta-core/src/debug/printing/printable_printf.o
-LOAD ./Libs/sta-core/src/debug/printing/printable_uart.o
-LOAD ./Libs/sta-core/src/devices/arduino/bus/i2c.o
-LOAD ./Libs/sta-core/src/devices/arduino/bus/spi.o
-LOAD ./Libs/sta-core/src/devices/arduino/delay.o
-LOAD ./Libs/sta-core/src/devices/arduino/gpio_pin.o
-LOAD ./Libs/sta-core/src/devices/raspi/bus/i2c.o
-LOAD ./Libs/sta-core/src/devices/raspi/bus/spi.o
-LOAD ./Libs/sta-core/src/devices/raspi/delay.o
-LOAD ./Libs/sta-core/src/devices/raspi/gpio_pin.o
-LOAD ./Libs/sta-core/src/devices/stm32/adc.o
-LOAD ./Libs/sta-core/src/devices/stm32/can.o
-LOAD ./Libs/sta-core/src/devices/stm32/delay.o
-LOAD ./Libs/sta-core/src/devices/stm32/gpio_pin.o
-LOAD ./Libs/sta-core/src/devices/stm32/init.o
-LOAD ./Libs/sta-core/src/devices/stm32/bus/i2c.o
-LOAD ./Libs/sta-core/src/devices/stm32/bus/spi.o
-LOAD ./Libs/sta-core/src/devices/stm32/bus/uart.o
-LOAD ./Libs/sta-core/src/devices/template/custom_printable.o
-LOAD ./Libs/sta-core/src/devices/template/delay.o
-LOAD ./Libs/sta-core/src/mutex.o
-START GROUP
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libsupc++_nano.a
-END GROUP
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libstdc++_nano.a
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a
-START GROUP
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a
-END GROUP
-START GROUP
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a
-END GROUP
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtend.o
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtn.o
-                0x0000000020020000                _estack = (ORIGIN (RAM) + LENGTH (RAM))
-                0x0000000000000200                _Min_Heap_Size = 0x200
-                0x0000000000000400                _Min_Stack_Size = 0x400
-
-.isr_vector     0x0000000008000000      0x188
-                0x0000000008000000                . = ALIGN (0x4)
- *(.isr_vector)
- .isr_vector    0x0000000008000000      0x188 ./Core/Startup/startup_stm32f407zgtx.o
-                0x0000000008000000                g_pfnVectors
-                0x0000000008000188                . = ALIGN (0x4)
-
-.text           0x0000000008000188     0x2a40
-                0x0000000008000188                . = ALIGN (0x4)
- *(.text)
- .text          0x0000000008000188       0x40 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o
- .text          0x00000000080001c8       0x30 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_aeabi_uldivmod.o)
-                0x00000000080001c8                __aeabi_uldivmod
- .text          0x00000000080001f8      0x2c8 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o)
-                0x00000000080001f8                __udivmoddi4
- .text          0x00000000080004c0        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_dvmd_tls.o)
-                0x00000000080004c0                __aeabi_idiv0
-                0x00000000080004c0                __aeabi_ldiv0
- *(.text*)
- .text.testCan  0x00000000080004c4       0x80 ./App/Src/test.o
-                0x00000000080004c4                testCan
- .text.main     0x0000000008000544       0x34 ./Core/Src/main.o
-                0x0000000008000544                main
- .text.SystemClock_Config
-                0x0000000008000578       0xbc ./Core/Src/main.o
-                0x0000000008000578                SystemClock_Config
- .text.MX_CAN1_Init
-                0x0000000008000634       0x68 ./Core/Src/main.o
- .text.MX_UART4_Init
-                0x000000000800069c       0x54 ./Core/Src/main.o
- .text.MX_GPIO_Init
-                0x00000000080006f0       0xcc ./Core/Src/main.o
- .text.Error_Handler
-                0x00000000080007bc        0xa ./Core/Src/main.o
-                0x00000000080007bc                Error_Handler
- *fill*         0x00000000080007c6        0x2 
- .text.HAL_MspInit
-                0x00000000080007c8       0x50 ./Core/Src/stm32f4xx_hal_msp.o
-                0x00000000080007c8                HAL_MspInit
- .text.HAL_CAN_MspInit
-                0x0000000008000818       0x90 ./Core/Src/stm32f4xx_hal_msp.o
-                0x0000000008000818                HAL_CAN_MspInit
- .text.HAL_UART_MspInit
-                0x00000000080008a8       0x90 ./Core/Src/stm32f4xx_hal_msp.o
-                0x00000000080008a8                HAL_UART_MspInit
- .text.NMI_Handler
-                0x0000000008000938        0x6 ./Core/Src/stm32f4xx_it.o
-                0x0000000008000938                NMI_Handler
- .text.HardFault_Handler
-                0x000000000800093e        0x6 ./Core/Src/stm32f4xx_it.o
-                0x000000000800093e                HardFault_Handler
- .text.MemManage_Handler
-                0x0000000008000944        0x6 ./Core/Src/stm32f4xx_it.o
-                0x0000000008000944                MemManage_Handler
- .text.BusFault_Handler
-                0x000000000800094a        0x6 ./Core/Src/stm32f4xx_it.o
-                0x000000000800094a                BusFault_Handler
- .text.UsageFault_Handler
-                0x0000000008000950        0x6 ./Core/Src/stm32f4xx_it.o
-                0x0000000008000950                UsageFault_Handler
- .text.SVC_Handler
-                0x0000000008000956        0xe ./Core/Src/stm32f4xx_it.o
-                0x0000000008000956                SVC_Handler
- .text.DebugMon_Handler
-                0x0000000008000964        0xe ./Core/Src/stm32f4xx_it.o
-                0x0000000008000964                DebugMon_Handler
- .text.PendSV_Handler
-                0x0000000008000972        0xe ./Core/Src/stm32f4xx_it.o
-                0x0000000008000972                PendSV_Handler
- .text.SysTick_Handler
-                0x0000000008000980        0xc ./Core/Src/stm32f4xx_it.o
-                0x0000000008000980                SysTick_Handler
- .text.SystemInit
-                0x000000000800098c       0x24 ./Core/Src/system_stm32f4xx.o
-                0x000000000800098c                SystemInit
- .text.Reset_Handler
-                0x00000000080009b0       0x50 ./Core/Startup/startup_stm32f407zgtx.o
-                0x00000000080009b0                Reset_Handler
- .text.Default_Handler
-                0x0000000008000a00        0x2 ./Core/Startup/startup_stm32f407zgtx.o
-                0x0000000008000a00                RTC_Alarm_IRQHandler
-                0x0000000008000a00                HASH_RNG_IRQHandler
-                0x0000000008000a00                EXTI2_IRQHandler
-                0x0000000008000a00                TIM8_CC_IRQHandler
-                0x0000000008000a00                TIM1_CC_IRQHandler
-                0x0000000008000a00                DMA2_Stream5_IRQHandler
-                0x0000000008000a00                DMA1_Stream5_IRQHandler
-                0x0000000008000a00                PVD_IRQHandler
-                0x0000000008000a00                SDIO_IRQHandler
-                0x0000000008000a00                TAMP_STAMP_IRQHandler
-                0x0000000008000a00                CAN2_RX1_IRQHandler
-                0x0000000008000a00                EXTI3_IRQHandler
-                0x0000000008000a00                TIM8_TRG_COM_TIM14_IRQHandler
-                0x0000000008000a00                TIM1_UP_TIM10_IRQHandler
-                0x0000000008000a00                TIM8_UP_TIM13_IRQHandler
-                0x0000000008000a00                I2C3_ER_IRQHandler
-                0x0000000008000a00                EXTI0_IRQHandler
-                0x0000000008000a00                I2C2_EV_IRQHandler
-                0x0000000008000a00                DMA1_Stream2_IRQHandler
-                0x0000000008000a00                CAN1_RX0_IRQHandler
-                0x0000000008000a00                FPU_IRQHandler
-                0x0000000008000a00                OTG_HS_WKUP_IRQHandler
-                0x0000000008000a00                CAN2_SCE_IRQHandler
-                0x0000000008000a00                DMA2_Stream2_IRQHandler
-                0x0000000008000a00                SPI1_IRQHandler
-                0x0000000008000a00                TIM6_DAC_IRQHandler
-                0x0000000008000a00                TIM1_BRK_TIM9_IRQHandler
-                0x0000000008000a00                DCMI_IRQHandler
-                0x0000000008000a00                CAN2_RX0_IRQHandler
-                0x0000000008000a00                DMA2_Stream3_IRQHandler
-                0x0000000008000a00                USART6_IRQHandler
-                0x0000000008000a00                USART3_IRQHandler
-                0x0000000008000a00                CAN1_RX1_IRQHandler
-                0x0000000008000a00                UART5_IRQHandler
-                0x0000000008000a00                DMA2_Stream0_IRQHandler
-                0x0000000008000a00                TIM4_IRQHandler
-                0x0000000008000a00                I2C1_EV_IRQHandler
-                0x0000000008000a00                DMA1_Stream6_IRQHandler
-                0x0000000008000a00                DMA1_Stream1_IRQHandler
-                0x0000000008000a00                UART4_IRQHandler
-                0x0000000008000a00                TIM3_IRQHandler
-                0x0000000008000a00                RCC_IRQHandler
-                0x0000000008000a00                TIM8_BRK_TIM12_IRQHandler
-                0x0000000008000a00                Default_Handler
-                0x0000000008000a00                EXTI15_10_IRQHandler
-                0x0000000008000a00                ADC_IRQHandler
-                0x0000000008000a00                DMA1_Stream7_IRQHandler
-                0x0000000008000a00                TIM7_IRQHandler
-                0x0000000008000a00                CAN2_TX_IRQHandler
-                0x0000000008000a00                TIM5_IRQHandler
-                0x0000000008000a00                DMA2_Stream7_IRQHandler
-                0x0000000008000a00                I2C3_EV_IRQHandler
-                0x0000000008000a00                EXTI9_5_IRQHandler
-                0x0000000008000a00                RTC_WKUP_IRQHandler
-                0x0000000008000a00                ETH_WKUP_IRQHandler
-                0x0000000008000a00                SPI2_IRQHandler
-                0x0000000008000a00                OTG_HS_EP1_IN_IRQHandler
-                0x0000000008000a00                DMA1_Stream0_IRQHandler
-                0x0000000008000a00                CAN1_TX_IRQHandler
-                0x0000000008000a00                EXTI4_IRQHandler
-                0x0000000008000a00                FSMC_IRQHandler
-                0x0000000008000a00                ETH_IRQHandler
-                0x0000000008000a00                OTG_HS_EP1_OUT_IRQHandler
-                0x0000000008000a00                WWDG_IRQHandler
-                0x0000000008000a00                TIM2_IRQHandler
-                0x0000000008000a00                OTG_FS_WKUP_IRQHandler
-                0x0000000008000a00                TIM1_TRG_COM_TIM11_IRQHandler
-                0x0000000008000a00                OTG_HS_IRQHandler
-                0x0000000008000a00                EXTI1_IRQHandler
-                0x0000000008000a00                USART2_IRQHandler
-                0x0000000008000a00                I2C2_ER_IRQHandler
-                0x0000000008000a00                DMA2_Stream1_IRQHandler
-                0x0000000008000a00                CAN1_SCE_IRQHandler
-                0x0000000008000a00                FLASH_IRQHandler
-                0x0000000008000a00                DMA2_Stream4_IRQHandler
-                0x0000000008000a00                USART1_IRQHandler
-                0x0000000008000a00                OTG_FS_IRQHandler
-                0x0000000008000a00                SPI3_IRQHandler
-                0x0000000008000a00                DMA1_Stream4_IRQHandler
-                0x0000000008000a00                I2C1_ER_IRQHandler
-                0x0000000008000a00                DMA2_Stream6_IRQHandler
-                0x0000000008000a00                DMA1_Stream3_IRQHandler
- *fill*         0x0000000008000a02        0x2 
- .text.HAL_Init
-                0x0000000008000a04       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
-                0x0000000008000a04                HAL_Init
- .text.HAL_InitTick
-                0x0000000008000a48       0x60 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
-                0x0000000008000a48                HAL_InitTick
- .text.HAL_IncTick
-                0x0000000008000aa8       0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
-                0x0000000008000aa8                HAL_IncTick
- .text.HAL_GetTick
-                0x0000000008000ad0       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
-                0x0000000008000ad0                HAL_GetTick
- .text.HAL_CAN_Init
-                0x0000000008000ae8      0x1f6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
-                0x0000000008000ae8                HAL_CAN_Init
- *fill*         0x0000000008000cde        0x2 
- .text.HAL_CAN_ConfigFilter
-                0x0000000008000ce0      0x1c0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
-                0x0000000008000ce0                HAL_CAN_ConfigFilter
- .text.HAL_CAN_Start
-                0x0000000008000ea0       0x88 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
-                0x0000000008000ea0                HAL_CAN_Start
- .text.HAL_CAN_AddTxMessage
-                0x0000000008000f28      0x1b6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
-                0x0000000008000f28                HAL_CAN_AddTxMessage
- .text.HAL_CAN_GetRxMessage
-                0x00000000080010de      0x224 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
-                0x00000000080010de                HAL_CAN_GetRxMessage
- .text.HAL_CAN_GetRxFifoFillLevel
-                0x0000000008001302       0x50 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
-                0x0000000008001302                HAL_CAN_GetRxFifoFillLevel
- *fill*         0x0000000008001352        0x2 
- .text.__NVIC_SetPriorityGrouping
-                0x0000000008001354       0x48 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.__NVIC_GetPriorityGrouping
-                0x000000000800139c       0x1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.__NVIC_SetPriority
-                0x00000000080013b8       0x54 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.NVIC_EncodePriority
-                0x000000000800140c       0x66 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- *fill*         0x0000000008001472        0x2 
- .text.SysTick_Config
-                0x0000000008001474       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .text.HAL_NVIC_SetPriorityGrouping
-                0x00000000080014b8       0x16 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
-                0x00000000080014b8                HAL_NVIC_SetPriorityGrouping
- .text.HAL_NVIC_SetPriority
-                0x00000000080014ce       0x38 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
-                0x00000000080014ce                HAL_NVIC_SetPriority
- .text.HAL_SYSTICK_Config
-                0x0000000008001506       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
-                0x0000000008001506                HAL_SYSTICK_Config
- *fill*         0x000000000800151e        0x2 
- .text.HAL_GPIO_Init
-                0x0000000008001520      0x338 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
-                0x0000000008001520                HAL_GPIO_Init
- .text.HAL_GPIO_WritePin
-                0x0000000008001858       0x32 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
-                0x0000000008001858                HAL_GPIO_WritePin
- .text.HAL_GPIO_TogglePin
-                0x000000000800188a       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
-                0x000000000800188a                HAL_GPIO_TogglePin
- *fill*         0x00000000080018be        0x2 
- .text.HAL_RCC_OscConfig
-                0x00000000080018c0      0x4f0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
-                0x00000000080018c0                HAL_RCC_OscConfig
- .text.HAL_RCC_ClockConfig
-                0x0000000008001db0      0x1cc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
-                0x0000000008001db0                HAL_RCC_ClockConfig
- .text.HAL_RCC_GetSysClockFreq
-                0x0000000008001f7c      0x18c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
-                0x0000000008001f7c                HAL_RCC_GetSysClockFreq
- .text.HAL_RCC_GetHCLKFreq
-                0x0000000008002108       0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
-                0x0000000008002108                HAL_RCC_GetHCLKFreq
- .text.HAL_RCC_GetPCLK1Freq
-                0x0000000008002120       0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
-                0x0000000008002120                HAL_RCC_GetPCLK1Freq
- .text.HAL_RCC_GetPCLK2Freq
-                0x0000000008002148       0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
-                0x0000000008002148                HAL_RCC_GetPCLK2Freq
- .text.HAL_UART_Init
-                0x0000000008002170       0x9a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
-                0x0000000008002170                HAL_UART_Init
- *fill*         0x000000000800220a        0x2 
- .text.UART_SetConfig
-                0x000000000800220c      0x4e8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .text._ZN3sta17CanPendingRxFifosC2Emh
-                0x00000000080026f4       0x28 ./Libs/sta-core/src/can/iter.o
-                0x00000000080026f4                sta::CanPendingRxFifos::CanPendingRxFifos(unsigned long, unsigned char)
-                0x00000000080026f4                sta::CanPendingRxFifos::CanPendingRxFifos(unsigned long, unsigned char)
- .text._ZN3sta13assert_failedEPKcS1_m
-                0x000000000800271c       0x18 ./Libs/sta-core/src/debug/assert.o
-                0x000000000800271c                sta::assert_failed(char const*, char const*, unsigned long)
- .text._ZN3sta11assert_haltEv
-                0x0000000008002734        0x8 ./Libs/sta-core/src/debug/assert.o
-                0x0000000008002734                sta::assert_halt()
- .text._ZN3sta13CanControllerC2Ev
-                0x000000000800273c       0x20 ./Libs/sta-core/src/devices/stm32/can.o
-                0x000000000800273c                sta::CanController::CanController()
-                0x000000000800273c                sta::CanController::CanController()
- .text._ZN3sta18STM32CanControllerC2EP19__CAN_HandleTypeDef
-                0x000000000800275c       0x34 ./Libs/sta-core/src/devices/stm32/can.o
-                0x000000000800275c                sta::STM32CanController::STM32CanController(__CAN_HandleTypeDef*)
-                0x000000000800275c                sta::STM32CanController::STM32CanController(__CAN_HandleTypeDef*)
- .text._ZN3sta18STM32CanController5startEv
-                0x0000000008002790       0x1a ./Libs/sta-core/src/devices/stm32/can.o
-                0x0000000008002790                sta::STM32CanController::start()
- *fill*         0x00000000080027aa        0x2 
- .text._ZN3sta18STM32CanController9sendFrameERKNS_11CanTxHeaderEPKh
-                0x00000000080027ac       0x8c ./Libs/sta-core/src/devices/stm32/can.o
-                0x00000000080027ac                sta::STM32CanController::sendFrame(sta::CanTxHeader const&, unsigned char const*)
- .text._ZN3sta18STM32CanController12receiveFrameEhPNS_11CanRxHeaderEPh
-                0x0000000008002838       0x94 ./Libs/sta-core/src/devices/stm32/can.o
-                0x0000000008002838                sta::STM32CanController::receiveFrame(unsigned char, sta::CanRxHeader*, unsigned char*)
- .text._ZN3sta18STM32CanController14getRxFifoFlagsEv
-                0x00000000080028cc       0x44 ./Libs/sta-core/src/devices/stm32/can.o
-                0x00000000080028cc                sta::STM32CanController::getRxFifoFlags()
- .text._ZN3sta18STM32CanController15configureFilterEhRKNS_9CanFilterEb
-                0x0000000008002910       0xce ./Libs/sta-core/src/devices/stm32/can.o
-                0x0000000008002910                sta::STM32CanController::configureFilter(unsigned char, sta::CanFilter const&, bool)
- .text._ZN3sta18STM32CanController12enableFilterEh
-                0x00000000080029de       0x38 ./Libs/sta-core/src/devices/stm32/can.o
-                0x00000000080029de                sta::STM32CanController::enableFilter(unsigned char)
- .text._ZN3sta18STM32CanController13disableFilterEh
-                0x0000000008002a16       0x38 ./Libs/sta-core/src/devices/stm32/can.o
-                0x0000000008002a16                sta::STM32CanController::disableFilter(unsigned char)
- .text._ZN3sta18STM32CanController12clearFiltersEv
-                0x0000000008002a4e       0x50 ./Libs/sta-core/src/devices/stm32/can.o
-                0x0000000008002a4e                sta::STM32CanController::clearFilters()
- .text._ZN3sta18STM32CanController11initFiltersEv
-                0x0000000008002a9e       0x58 ./Libs/sta-core/src/devices/stm32/can.o
-                0x0000000008002a9e                sta::STM32CanController::initFilters()
- .text._ZN3sta18STM32CanController17getPendingRxFifosEv
-                0x0000000008002af6       0x1e ./Libs/sta-core/src/devices/stm32/can.o
-                0x0000000008002af6                sta::STM32CanController::getPendingRxFifos()
- .text._ZNK3sta18STM32CanController14maxFilterCountEv
-                0x0000000008002b14       0x16 ./Libs/sta-core/src/devices/stm32/can.o
-                0x0000000008002b14                sta::STM32CanController::maxFilterCount() const
- .text._ZNK3sta18STM32CanController12maxFifoCountEv
-                0x0000000008002b2a       0x16 ./Libs/sta-core/src/devices/stm32/can.o
-                0x0000000008002b2a                sta::STM32CanController::maxFifoCount() const
- .text._ZNK3sta18STM32CanController14maxPayloadSizeEv
-                0x0000000008002b40       0x16 ./Libs/sta-core/src/devices/stm32/can.o
-                0x0000000008002b40                sta::STM32CanController::maxPayloadSize() const
- .text.memset   0x0000000008002b56       0x10 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memset.o)
-                0x0000000008002b56                memset
- *fill*         0x0000000008002b66        0x2 
- .text.__libc_init_array
-                0x0000000008002b68       0x48 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-init.o)
-                0x0000000008002b68                __libc_init_array
- *(.glue_7)
- .glue_7        0x0000000008002bb0        0x0 linker stubs
- *(.glue_7t)
- .glue_7t       0x0000000008002bb0        0x0 linker stubs
- *(.eh_frame)
- .eh_frame      0x0000000008002bb0        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o
- *(.init)
- .init          0x0000000008002bb0        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crti.o
-                0x0000000008002bb0                _init
- .init          0x0000000008002bb4        0x8 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtn.o
- *(.fini)
- .fini          0x0000000008002bbc        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crti.o
-                0x0000000008002bbc                _fini
- .fini          0x0000000008002bc0        0x8 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtn.o
-                0x0000000008002bc8                . = ALIGN (0x4)
-                0x0000000008002bc8                _etext = .
-
-.vfp11_veneer   0x0000000008002bc8        0x0
- .vfp11_veneer  0x0000000008002bc8        0x0 linker stubs
-
-.v4_bx          0x0000000008002bc8        0x0
- .v4_bx         0x0000000008002bc8        0x0 linker stubs
-
-.iplt           0x0000000008002bc8        0x0
- .iplt          0x0000000008002bc8        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o
-
-.rodata         0x0000000008002bc8       0xd4
-                0x0000000008002bc8                . = ALIGN (0x4)
- *(.rodata)
- .rodata        0x0000000008002bc8        0x8 ./App/Src/test.o
- .rodata        0x0000000008002bd0       0x4b ./Libs/sta-core/src/devices/stm32/can.o
- *(.rodata*)
- *fill*         0x0000000008002c1b        0x1 
- .rodata.AHBPrescTable
-                0x0000000008002c1c       0x10 ./Core/Src/system_stm32f4xx.o
-                0x0000000008002c1c                AHBPrescTable
- .rodata.APBPrescTable
-                0x0000000008002c2c        0x8 ./Core/Src/system_stm32f4xx.o
-                0x0000000008002c2c                APBPrescTable
- .rodata._ZTVN3sta18STM32CanControllerE
-                0x0000000008002c34       0x34 ./Libs/sta-core/src/devices/stm32/can.o
-                0x0000000008002c34                vtable for sta::STM32CanController
- .rodata._ZTVN3sta13CanControllerE
-                0x0000000008002c68       0x34 ./Libs/sta-core/src/devices/stm32/can.o
-                0x0000000008002c68                vtable for sta::CanController
-                0x0000000008002c9c                . = ALIGN (0x4)
-
-.ARM.extab      0x0000000008002c9c        0x0
-                0x0000000008002c9c                . = ALIGN (0x4)
- *(.ARM.extab* .gnu.linkonce.armextab.*)
-                0x0000000008002c9c                . = ALIGN (0x4)
-
-.ARM            0x0000000008002c9c        0x8
-                0x0000000008002c9c                . = ALIGN (0x4)
-                0x0000000008002c9c                __exidx_start = .
- *(.ARM.exidx*)
- .ARM.exidx     0x0000000008002c9c        0x8 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o)
-                0x0000000008002ca4                __exidx_end = .
-                0x0000000008002ca4                . = ALIGN (0x4)
-
-.rel.dyn        0x0000000008002ca4        0x0
- .rel.iplt      0x0000000008002ca4        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o
-
-.preinit_array  0x0000000008002ca4        0x0
-                0x0000000008002ca4                . = ALIGN (0x4)
-                0x0000000008002ca4                PROVIDE (__preinit_array_start = .)
- *(.preinit_array*)
-                0x0000000008002ca4                PROVIDE (__preinit_array_end = .)
-                0x0000000008002ca4                . = ALIGN (0x4)
-
-.init_array     0x0000000008002ca4        0x4
-                0x0000000008002ca4                . = ALIGN (0x4)
-                0x0000000008002ca4                PROVIDE (__init_array_start = .)
- *(SORT_BY_NAME(.init_array.*))
- *(.init_array*)
- .init_array    0x0000000008002ca4        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o
-                0x0000000008002ca8                PROVIDE (__init_array_end = .)
-                0x0000000008002ca8                . = ALIGN (0x4)
-
-.fini_array     0x0000000008002ca8        0x4
-                0x0000000008002ca8                . = ALIGN (0x4)
-                [!provide]                        PROVIDE (__fini_array_start = .)
- *(SORT_BY_NAME(.fini_array.*))
- *(.fini_array*)
- .fini_array    0x0000000008002ca8        0x4 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o
-                [!provide]                        PROVIDE (__fini_array_end = .)
-                0x0000000008002cac                . = ALIGN (0x4)
-                0x0000000008002cac                _sidata = LOADADDR (.data)
-
-.data           0x0000000020000000        0xc load address 0x0000000008002cac
-                0x0000000020000000                . = ALIGN (0x4)
-                0x0000000020000000                _sdata = .
- *(.data)
- *(.data*)
- .data.SystemCoreClock
-                0x0000000020000000        0x4 ./Core/Src/system_stm32f4xx.o
-                0x0000000020000000                SystemCoreClock
- .data.uwTickPrio
-                0x0000000020000004        0x4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
-                0x0000000020000004                uwTickPrio
- .data.uwTickFreq
-                0x0000000020000008        0x1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
-                0x0000000020000008                uwTickFreq
- *(.RamFunc)
- *(.RamFunc*)
-                0x000000002000000c                . = ALIGN (0x4)
- *fill*         0x0000000020000009        0x3 
-                0x000000002000000c                _edata = .
-                0x0000000008002cb8                _siccmram = LOADADDR (.ccmram)
-
-.igot.plt       0x000000002000000c        0x0 load address 0x0000000008002cb8
- .igot.plt      0x000000002000000c        0x0 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o
-
-.ccmram         0x0000000010000000        0x0 load address 0x0000000008002cb8
-                0x0000000010000000                . = ALIGN (0x4)
-                0x0000000010000000                _sccmram = .
- *(.ccmram)
- *(.ccmram*)
-                0x0000000010000000                . = ALIGN (0x4)
-                0x0000000010000000                _eccmram = .
-                0x0000000010000000                . = ALIGN (0x4)
-
-.bss            0x000000002000000c       0x8c
-                0x000000002000000c                _sbss = .
-                0x000000002000000c                __bss_start__ = _sbss
- *(.bss)
- .bss           0x000000002000000c       0x1c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o
- *(.bss*)
- .bss.hcan1     0x0000000020000028       0x28 ./Core/Src/main.o
-                0x0000000020000028                hcan1
- .bss.huart4    0x0000000020000050       0x44 ./Core/Src/main.o
-                0x0000000020000050                huart4
- .bss.uwTick    0x0000000020000094        0x4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
-                0x0000000020000094                uwTick
- *(COMMON)
-                0x0000000020000098                . = ALIGN (0x4)
-                0x0000000020000098                _ebss = .
-                0x0000000020000098                __bss_end__ = _ebss
-
-._user_heap_stack
-                0x0000000020000098      0x600
-                0x0000000020000098                . = ALIGN (0x8)
-                [!provide]                        PROVIDE (end = .)
-                0x0000000020000098                PROVIDE (_end = .)
-                0x0000000020000298                . = (. + _Min_Heap_Size)
- *fill*         0x0000000020000098      0x200 
-                0x0000000020000698                . = (. + _Min_Stack_Size)
- *fill*         0x0000000020000298      0x400 
-                0x0000000020000698                . = ALIGN (0x8)
-
-/DISCARD/
- libc.a(*)
- libm.a(*)
- libgcc.a(*)
-
-.ARM.attributes
-                0x0000000000000000       0x30
- *(.ARM.attributes)
- .ARM.attributes
-                0x0000000000000000       0x1e C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crti.o
- .ARM.attributes
-                0x000000000000001e       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o
- .ARM.attributes
-                0x0000000000000052       0x34 ./App/Src/test.o
- .ARM.attributes
-                0x0000000000000086       0x34 ./Core/Src/main.o
- .ARM.attributes
-                0x00000000000000ba       0x34 ./Core/Src/stm32f4xx_hal_msp.o
- .ARM.attributes
-                0x00000000000000ee       0x34 ./Core/Src/stm32f4xx_it.o
- .ARM.attributes
-                0x0000000000000122       0x34 ./Core/Src/system_stm32f4xx.o
- .ARM.attributes
-                0x0000000000000156       0x21 ./Core/Startup/startup_stm32f407zgtx.o
- .ARM.attributes
-                0x0000000000000177       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .ARM.attributes
-                0x00000000000001ab       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .ARM.attributes
-                0x00000000000001df       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .ARM.attributes
-                0x0000000000000213       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .ARM.attributes
-                0x0000000000000247       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .ARM.attributes
-                0x000000000000027b       0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .ARM.attributes
-                0x00000000000002af       0x34 ./Libs/sta-core/src/can/iter.o
- .ARM.attributes
-                0x00000000000002e3       0x34 ./Libs/sta-core/src/debug/assert.o
- .ARM.attributes
-                0x0000000000000317       0x34 ./Libs/sta-core/src/devices/stm32/can.o
- .ARM.attributes
-                0x000000000000034b       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memset.o)
- .ARM.attributes
-                0x000000000000037f       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-init.o)
- .ARM.attributes
-                0x00000000000003b3       0x1e C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_aeabi_uldivmod.o)
- .ARM.attributes
-                0x00000000000003d1       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o)
- .ARM.attributes
-                0x0000000000000405       0x1e C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_dvmd_tls.o)
- .ARM.attributes
-                0x0000000000000423       0x1e C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtn.o
-OUTPUT(can-tests.elf elf32-littlearm)
-LOAD linker stubs
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc.a
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libm.a
-LOAD C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a
-
-.comment        0x0000000000000000       0x43
- .comment       0x0000000000000000       0x43 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o
-                                         0x44 (size before relaxing)
- .comment       0x0000000000000043       0x44 ./App/Src/test.o
- .comment       0x0000000000000043       0x44 ./Core/Src/main.o
- .comment       0x0000000000000043       0x44 ./Core/Src/stm32f4xx_hal_msp.o
- .comment       0x0000000000000043       0x44 ./Core/Src/stm32f4xx_it.o
- .comment       0x0000000000000043       0x44 ./Core/Src/system_stm32f4xx.o
- .comment       0x0000000000000043       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .comment       0x0000000000000043       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .comment       0x0000000000000043       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .comment       0x0000000000000043       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .comment       0x0000000000000043       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .comment       0x0000000000000043       0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .comment       0x0000000000000043       0x44 ./Libs/sta-core/src/can/iter.o
- .comment       0x0000000000000043       0x44 ./Libs/sta-core/src/debug/assert.o
- .comment       0x0000000000000043       0x44 ./Libs/sta-core/src/devices/stm32/can.o
-
-.debug_info     0x0000000000000000     0xbed9
- .debug_info    0x0000000000000000      0x8f4 ./App/Src/test.o
- .debug_info    0x00000000000008f4      0xfa1 ./Core/Src/main.o
- .debug_info    0x0000000000001895      0xd40 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_info    0x00000000000025d5      0x112 ./Core/Src/stm32f4xx_it.o
- .debug_info    0x00000000000026e7      0x512 ./Core/Src/system_stm32f4xx.o
- .debug_info    0x0000000000002bf9       0x23 ./Core/Startup/startup_stm32f407zgtx.o
- .debug_info    0x0000000000002c1c      0x948 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_info    0x0000000000003564      0xf03 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_info    0x0000000000004467      0xd46 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_info    0x00000000000051ad      0x6c3 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_info    0x0000000000005870      0x8b1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_info    0x0000000000006121     0x2fb8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_info    0x00000000000090d9      0x8be ./Libs/sta-core/src/can/iter.o
- .debug_info    0x0000000000009997      0xda4 ./Libs/sta-core/src/debug/assert.o
- .debug_info    0x000000000000a73b     0x179e ./Libs/sta-core/src/devices/stm32/can.o
-
-.debug_abbrev   0x0000000000000000     0x205f
- .debug_abbrev  0x0000000000000000      0x268 ./App/Src/test.o
- .debug_abbrev  0x0000000000000268      0x279 ./Core/Src/main.o
- .debug_abbrev  0x00000000000004e1      0x1dd ./Core/Src/stm32f4xx_hal_msp.o
- .debug_abbrev  0x00000000000006be       0x73 ./Core/Src/stm32f4xx_it.o
- .debug_abbrev  0x0000000000000731      0x11a ./Core/Src/system_stm32f4xx.o
- .debug_abbrev  0x000000000000084b       0x12 ./Core/Startup/startup_stm32f407zgtx.o
- .debug_abbrev  0x000000000000085d      0x213 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_abbrev  0x0000000000000a70      0x239 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_abbrev  0x0000000000000ca9      0x327 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_abbrev  0x0000000000000fd0      0x1d4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_abbrev  0x00000000000011a4      0x2b6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_abbrev  0x000000000000145a      0x30e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_abbrev  0x0000000000001768      0x232 ./Libs/sta-core/src/can/iter.o
- .debug_abbrev  0x000000000000199a      0x20f ./Libs/sta-core/src/debug/assert.o
- .debug_abbrev  0x0000000000001ba9      0x4b6 ./Libs/sta-core/src/devices/stm32/can.o
-
-.debug_aranges  0x0000000000000000      0x8b8
- .debug_aranges
-                0x0000000000000000       0x20 ./App/Src/test.o
- .debug_aranges
-                0x0000000000000020       0x48 ./Core/Src/main.o
- .debug_aranges
-                0x0000000000000068       0x40 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_aranges
-                0x00000000000000a8       0x60 ./Core/Src/stm32f4xx_it.o
- .debug_aranges
-                0x0000000000000108       0x28 ./Core/Src/system_stm32f4xx.o
- .debug_aranges
-                0x0000000000000130       0x28 ./Core/Startup/startup_stm32f407zgtx.o
- .debug_aranges
-                0x0000000000000158       0xf0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_aranges
-                0x0000000000000248      0x138 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_aranges
-                0x0000000000000380      0x118 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_aranges
-                0x0000000000000498       0x58 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_aranges
-                0x00000000000004f0       0x88 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_aranges
-                0x0000000000000578      0x200 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_aranges
-                0x0000000000000778       0x78 ./Libs/sta-core/src/can/iter.o
- .debug_aranges
-                0x00000000000007f0       0x28 ./Libs/sta-core/src/debug/assert.o
- .debug_aranges
-                0x0000000000000818       0xa0 ./Libs/sta-core/src/devices/stm32/can.o
-
-.debug_rnglists
-                0x0000000000000000      0x695
- .debug_rnglists
-                0x0000000000000000       0x14 ./App/Src/test.o
- .debug_rnglists
-                0x0000000000000014       0x33 ./Core/Src/main.o
- .debug_rnglists
-                0x0000000000000047       0x2d ./Core/Src/stm32f4xx_hal_msp.o
- .debug_rnglists
-                0x0000000000000074       0x43 ./Core/Src/stm32f4xx_it.o
- .debug_rnglists
-                0x00000000000000b7       0x1a ./Core/Src/system_stm32f4xx.o
- .debug_rnglists
-                0x00000000000000d1       0x19 ./Core/Startup/startup_stm32f407zgtx.o
- .debug_rnglists
-                0x00000000000000ea       0xaf ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_rnglists
-                0x0000000000000199       0xee ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_rnglists
-                0x0000000000000287       0xce ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_rnglists
-                0x0000000000000355       0x3f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_rnglists
-                0x0000000000000394       0x66 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_rnglists
-                0x00000000000003fa      0x1b7 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_rnglists
-                0x00000000000005b1       0x55 ./Libs/sta-core/src/can/iter.o
- .debug_rnglists
-                0x0000000000000606       0x19 ./Libs/sta-core/src/debug/assert.o
- .debug_rnglists
-                0x000000000000061f       0x76 ./Libs/sta-core/src/devices/stm32/can.o
-
-.debug_macro    0x0000000000000000    0x22499
- .debug_macro   0x0000000000000000      0x25a ./App/Src/test.o
- .debug_macro   0x000000000000025a      0xb80 ./App/Src/test.o
- .debug_macro   0x0000000000000dda       0x22 ./App/Src/test.o
- .debug_macro   0x0000000000000dfc      0x29b ./App/Src/test.o
- .debug_macro   0x0000000000001097       0x2e ./App/Src/test.o
- .debug_macro   0x00000000000010c5       0x2f ./App/Src/test.o
- .debug_macro   0x00000000000010f4       0x1c ./App/Src/test.o
- .debug_macro   0x0000000000001110       0x22 ./App/Src/test.o
- .debug_macro   0x0000000000001132       0x8e ./App/Src/test.o
- .debug_macro   0x00000000000011c0       0x51 ./App/Src/test.o
- .debug_macro   0x0000000000001211      0x103 ./App/Src/test.o
- .debug_macro   0x0000000000001314       0x6a ./App/Src/test.o
- .debug_macro   0x000000000000137e      0x1df ./App/Src/test.o
- .debug_macro   0x000000000000155d       0x1c ./App/Src/test.o
- .debug_macro   0x0000000000001579       0x22 ./App/Src/test.o
- .debug_macro   0x000000000000159b       0xd9 ./App/Src/test.o
- .debug_macro   0x0000000000001674     0x102d ./App/Src/test.o
- .debug_macro   0x00000000000026a1      0x11f ./App/Src/test.o
- .debug_macro   0x00000000000027c0    0x15e82 ./App/Src/test.o
- .debug_macro   0x0000000000018642       0x6d ./App/Src/test.o
- .debug_macro   0x00000000000186af     0x367e ./App/Src/test.o
- .debug_macro   0x000000000001bd2d      0x17b ./App/Src/test.o
- .debug_macro   0x000000000001bea8       0x5c ./App/Src/test.o
- .debug_macro   0x000000000001bf04      0x96b ./App/Src/test.o
- .debug_macro   0x000000000001c86f      0x9fe ./App/Src/test.o
- .debug_macro   0x000000000001d26d      0x115 ./App/Src/test.o
- .debug_macro   0x000000000001d382      0x13e ./App/Src/test.o
- .debug_macro   0x000000000001d4c0       0xa5 ./App/Src/test.o
- .debug_macro   0x000000000001d565      0x174 ./App/Src/test.o
- .debug_macro   0x000000000001d6d9      0x287 ./App/Src/test.o
- .debug_macro   0x000000000001d960       0x5f ./App/Src/test.o
- .debug_macro   0x000000000001d9bf      0x236 ./App/Src/test.o
- .debug_macro   0x000000000001dbf5      0x40f ./App/Src/test.o
- .debug_macro   0x000000000001e004      0x12c ./App/Src/test.o
- .debug_macro   0x000000000001e130      0x21e ./App/Src/test.o
- .debug_macro   0x000000000001e34e       0x2e ./App/Src/test.o
- .debug_macro   0x000000000001e37c      0x11a ./App/Src/test.o
- .debug_macro   0x000000000001e496       0x7e ./App/Src/test.o
- .debug_macro   0x000000000001e514       0x89 ./App/Src/test.o
- .debug_macro   0x000000000001e59d      0x295 ./App/Src/test.o
- .debug_macro   0x000000000001e832      0x12d ./App/Src/test.o
- .debug_macro   0x000000000001e95f      0x1b2 ./App/Src/test.o
- .debug_macro   0x000000000001eb11       0x10 ./App/Src/test.o
- .debug_macro   0x000000000001eb21      0x3ed ./App/Src/test.o
- .debug_macro   0x000000000001ef0e       0x10 ./App/Src/test.o
- .debug_macro   0x000000000001ef1e      0x1ce ./Core/Src/main.o
- .debug_macro   0x000000000001f0ec      0xaa8 ./Core/Src/main.o
- .debug_macro   0x000000000001fb94     0x102d ./Core/Src/main.o
- .debug_macro   0x0000000000020bc1      0x174 ./Core/Src/main.o
- .debug_macro   0x0000000000020d35      0x1ce ./Core/Src/stm32f4xx_hal_msp.o
- .debug_macro   0x0000000000020f03      0x1d8 ./Core/Src/stm32f4xx_it.o
- .debug_macro   0x00000000000210db      0x1c4 ./Core/Src/system_stm32f4xx.o
- .debug_macro   0x000000000002129f      0x224 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_macro   0x00000000000214c3      0x1cc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_macro   0x000000000002168f      0x1c4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_macro   0x0000000000021853      0x1ca ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_macro   0x0000000000021a1d      0x1e8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_macro   0x0000000000021c05      0x1c5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_macro   0x0000000000021dca       0xb7 ./Libs/sta-core/src/can/iter.o
- .debug_macro   0x0000000000021e81      0x1ab ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x000000000002202c       0x22 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x000000000002204e       0x16 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x0000000000022064       0x97 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x00000000000220fb      0x104 ./Libs/sta-core/src/debug/assert.o
- .debug_macro   0x00000000000221ff      0x26c ./Libs/sta-core/src/devices/stm32/can.o
- .debug_macro   0x000000000002246b       0x2e ./Libs/sta-core/src/devices/stm32/can.o
-
-.debug_line     0x0000000000000000     0xb635
- .debug_line    0x0000000000000000      0xa5b ./App/Src/test.o
- .debug_line    0x0000000000000a5b      0x84d ./Core/Src/main.o
- .debug_line    0x00000000000012a8      0x7c7 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_line    0x0000000000001a6f      0x7ef ./Core/Src/stm32f4xx_it.o
- .debug_line    0x000000000000225e      0x7ae ./Core/Src/system_stm32f4xx.o
- .debug_line    0x0000000000002a0c       0x7a ./Core/Startup/startup_stm32f407zgtx.o
- .debug_line    0x0000000000002a86      0xa14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_line    0x000000000000349a     0x1180 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_line    0x000000000000461a      0xcc3 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_line    0x00000000000052dd      0xb88 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_line    0x0000000000005e65      0xd8b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_line    0x0000000000006bf0     0x2ab6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_line    0x00000000000096a6      0x8c3 ./Libs/sta-core/src/can/iter.o
- .debug_line    0x0000000000009f69      0x87e ./Libs/sta-core/src/debug/assert.o
- .debug_line    0x000000000000a7e7      0xe4e ./Libs/sta-core/src/devices/stm32/can.o
-
-.debug_str      0x0000000000000000    0xc7dc8
- .debug_str     0x0000000000000000    0xc0a07 ./App/Src/test.o
-                                      0xc0e66 (size before relaxing)
- .debug_str     0x00000000000c0a07      0x94d ./Core/Src/main.o
-                                      0xbf325 (size before relaxing)
- .debug_str     0x00000000000c1354       0x8d ./Core/Src/stm32f4xx_hal_msp.o
-                                      0xbf143 (size before relaxing)
- .debug_str     0x00000000000c13e1       0xc9 ./Core/Src/stm32f4xx_it.o
-                                      0xbe970 (size before relaxing)
- .debug_str     0x00000000000c14aa       0xdb ./Core/Src/system_stm32f4xx.o
-                                      0xbea9a (size before relaxing)
- .debug_str     0x00000000000c1585       0x34 ./Core/Startup/startup_stm32f407zgtx.o
-                                         0x71 (size before relaxing)
- .debug_str     0x00000000000c15b9      0xb07 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
-                                      0xbf61e (size before relaxing)
- .debug_str     0x00000000000c20c0      0x527 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
-                                      0xbf186 (size before relaxing)
- .debug_str     0x00000000000c25e7      0x34a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
-                                      0xbf351 (size before relaxing)
- .debug_str     0x00000000000c2931      0x10e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
-                                      0xbec15 (size before relaxing)
- .debug_str     0x00000000000c2a3f      0x228 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
-                                      0xbeece (size before relaxing)
- .debug_str     0x00000000000c2c67      0x648 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
-                                      0xbf46d (size before relaxing)
- .debug_str     0x00000000000c32af      0x5c9 ./Libs/sta-core/src/can/iter.o
-                                       0x62da (size before relaxing)
- .debug_str     0x00000000000c3878     0x3d2a ./Libs/sta-core/src/debug/assert.o
-                                       0xa046 (size before relaxing)
- .debug_str     0x00000000000c75a2      0x826 ./Libs/sta-core/src/devices/stm32/can.o
-                                      0xc1eb4 (size before relaxing)
-
-.debug_frame    0x0000000000000000     0x2290
- .debug_frame   0x0000000000000000       0x30 ./App/Src/test.o
- .debug_frame   0x0000000000000030       0xc4 ./Core/Src/main.o
- .debug_frame   0x00000000000000f4       0xc8 ./Core/Src/stm32f4xx_hal_msp.o
- .debug_frame   0x00000000000001bc      0x104 ./Core/Src/stm32f4xx_it.o
- .debug_frame   0x00000000000002c0       0x58 ./Core/Src/system_stm32f4xx.o
- .debug_frame   0x0000000000000318      0x374 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o
- .debug_frame   0x000000000000068c      0x5a0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.o
- .debug_frame   0x0000000000000c2c      0x498 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o
- .debug_frame   0x00000000000010c4      0x14c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o
- .debug_frame   0x0000000000001210      0x1f4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o
- .debug_frame   0x0000000000001404      0x92c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o
- .debug_frame   0x0000000000001d30      0x1d8 ./Libs/sta-core/src/can/iter.o
- .debug_frame   0x0000000000001f08       0x50 ./Libs/sta-core/src/debug/assert.o
- .debug_frame   0x0000000000001f58      0x28c ./Libs/sta-core/src/devices/stm32/can.o
- .debug_frame   0x00000000000021e4       0x20 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memset.o)
- .debug_frame   0x0000000000002204       0x2c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-init.o)
- .debug_frame   0x0000000000002230       0x2c C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_aeabi_uldivmod.o)
- .debug_frame   0x000000000000225c       0x34 C:/ST/STM32CubeIDE_1.10.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o)
-
-.debug_line_str
-                0x0000000000000000       0x65
- .debug_line_str
-                0x0000000000000000       0x65 ./Core/Startup/startup_stm32f407zgtx.o
-                                         0x7d (size before relaxing)
diff --git a/Debug/makefile b/Debug/makefile
index 3840285..f6e1b1a 100644
--- a/Debug/makefile
+++ b/Debug/makefile
@@ -66,34 +66,34 @@ $(wildcard ../makefile.init) \
 $(wildcard ../makefile.targets) \
 
 
-BUILD_ARTIFACT_NAME := can-tests
+BUILD_ARTIFACT_NAME := CAN-Card_Module_Software
 BUILD_ARTIFACT_EXTENSION := elf
 BUILD_ARTIFACT_PREFIX :=
 BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),)
 
 # Add inputs and outputs from these tool invocations to the build variables 
 EXECUTABLES += \
-can-tests.elf \
+CAN-Card_Module_Software.elf \
 
 MAP_FILES += \
-can-tests.map \
+CAN-Card_Module_Software.map \
 
 SIZE_OUTPUT += \
 default.size.stdout \
 
 OBJDUMP_LIST += \
-can-tests.list \
+CAN-Card_Module_Software.list \
 
 
 # All Target
 all: main-build
 
 # Main-build Target
-main-build: can-tests.elf secondary-outputs
+main-build: CAN-Card_Module_Software.elf secondary-outputs
 
 # Tool invocations
-can-tests.elf can-tests.map: $(OBJS) $(USER_OBJS) C:\Users\carlw\Desktop\to-the-moon\workspace\can-tests\STM32F407ZGTX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS)
-	arm-none-eabi-g++ -o "can-tests.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"C:\Users\carlw\Desktop\to-the-moon\workspace\can-tests\STM32F407ZGTX_FLASH.ld" -Wl,-Map="can-tests.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group
+CAN-Card_Module_Software.elf CAN-Card_Module_Software.map: $(OBJS) $(USER_OBJS) /Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/STM32F407ZGTX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-g++ -o "CAN-Card_Module_Software.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"/Users/carlos/Documents/RWTH/space_team/CAN-Card_Module_Software/STM32F407ZGTX_FLASH.ld" -Wl,-Map="CAN-Card_Module_Software.map" -Wl,--gc-sections -static --specs=nano.specs -mfpu=fpv4-sp-d16 -mfloat-abi=hard -mthumb -Wl,--start-group -lc -lm -lstdc++ -lsupc++ -Wl,--end-group
 	@echo 'Finished building target: $@'
 	@echo ' '
 
@@ -102,14 +102,14 @@ default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
 	@echo 'Finished building: $@'
 	@echo ' '
 
-can-tests.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
-	arm-none-eabi-objdump -h -S $(EXECUTABLES) > "can-tests.list"
+CAN-Card_Module_Software.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS)
+	arm-none-eabi-objdump -h -S $(EXECUTABLES) > "CAN-Card_Module_Software.list"
 	@echo 'Finished building: $@'
 	@echo ' '
 
 # Other Targets
 clean:
-	-$(RM) can-tests.elf can-tests.list can-tests.map default.size.stdout
+	-$(RM) CAN-Card_Module_Software.elf CAN-Card_Module_Software.list CAN-Card_Module_Software.map default.size.stdout
 	-@echo ' '
 
 secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST)
diff --git a/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h
index 874659c..11adbcb 100644
--- a/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h
+++ b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f407xx.h
@@ -1,15607 +1,15607 @@
-/**
-  ******************************************************************************
-  * @file    stm32f407xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS STM32F407xx Device Peripheral Access Layer Header File.
-  *
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - peripherals registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS_Device
-  * @{
-  */
-
-/** @addtogroup stm32f407xx
-  * @{
-  */
-    
-#ifndef __STM32F407xx_H
-#define __STM32F407xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-
-/**
-  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
-  */
-#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
-#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
-#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
-#define __FPU_PRESENT             1U       /*!< FPU present                                   */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-typedef enum
-{
-/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
-  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
-/******  STM32 specific Interrupt Numbers **********************************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
-  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
-  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
-  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
-  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
-  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
-  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
-  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
-  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
-  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
-  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
-  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
-  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
-  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
-  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
-  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
-  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
-  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
-  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
-  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
-  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
-  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
-  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */
-  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
-  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */
-  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
-  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
-  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
-  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
-  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
-  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
-  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
-  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
-  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
-  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
-  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
-  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
-  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
-  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
-  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
-  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
-  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
-  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
-  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
-  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
-  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
-  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
-  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
-  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
-  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
-  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
-  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
-  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
-  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
-  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
-  RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */
-  FPU_IRQn                    = 81      /*!< FPU global interrupt                                               */
-} IRQn_Type;
-/* Legacy define */
-#define  HASH_RNG_IRQn      RNG_IRQn
-
-/**
-  * @}
-  */
-
-#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
-#include "system_stm32f4xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
-  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
-  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
-  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
-  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
-  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
-  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
-  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
-  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
-  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
-  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
-  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
-  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
-  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
-  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-} ADC_Common_TypeDef;
-
-
-/** 
-  * @brief Controller Area Network TxMailBox 
-  */
-
-typedef struct
-{
-  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
-  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
-  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
-  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FIFOMailBox 
-  */
-  
-typedef struct
-{
-  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
-  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
-  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
-  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/** 
-  * @brief Controller Area Network FilterRegister 
-  */
-  
-typedef struct
-{
-  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
-  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/** 
-  * @brief Controller Area Network 
-  */
-  
-typedef struct
-{
-  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
-  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
-  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
-  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
-  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
-  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
-  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
-  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
-  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
-  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
-  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
-  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
-  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
-  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
-  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
-  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
-  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
-  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
-  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
-  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
-  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
-  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
-} CAN_TypeDef;
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
-  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
-  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
-  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
-  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
-  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
-  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
-  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DCMI
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
-  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
-  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
-  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
-  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
-  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
-  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
-  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
-  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
-  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
-  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
-} DCMI_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
-  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
-  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
-  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
-  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
-  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
-} DMA_Stream_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
-  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
-  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
-  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
-} DMA_TypeDef;
-
-/** 
-  * @brief Ethernet MAC
-  */
-
-typedef struct
-{
-  __IO uint32_t MACCR;
-  __IO uint32_t MACFFR;
-  __IO uint32_t MACHTHR;
-  __IO uint32_t MACHTLR;
-  __IO uint32_t MACMIIAR;
-  __IO uint32_t MACMIIDR;
-  __IO uint32_t MACFCR;
-  __IO uint32_t MACVLANTR;             /*    8 */
-  uint32_t      RESERVED0[2];
-  __IO uint32_t MACRWUFFR;             /*   11 */
-  __IO uint32_t MACPMTCSR;
-  uint32_t      RESERVED1;
-  __IO uint32_t MACDBGR;
-  __IO uint32_t MACSR;                 /*   15 */
-  __IO uint32_t MACIMR;
-  __IO uint32_t MACA0HR;
-  __IO uint32_t MACA0LR;
-  __IO uint32_t MACA1HR;
-  __IO uint32_t MACA1LR;
-  __IO uint32_t MACA2HR;
-  __IO uint32_t MACA2LR;
-  __IO uint32_t MACA3HR;
-  __IO uint32_t MACA3LR;               /*   24 */
-  uint32_t      RESERVED2[40];
-  __IO uint32_t MMCCR;                 /*   65 */
-  __IO uint32_t MMCRIR;
-  __IO uint32_t MMCTIR;
-  __IO uint32_t MMCRIMR;
-  __IO uint32_t MMCTIMR;               /*   69 */
-  uint32_t      RESERVED3[14];
-  __IO uint32_t MMCTGFSCCR;            /*   84 */
-  __IO uint32_t MMCTGFMSCCR;
-  uint32_t      RESERVED4[5];
-  __IO uint32_t MMCTGFCR;
-  uint32_t      RESERVED5[10];
-  __IO uint32_t MMCRFCECR;
-  __IO uint32_t MMCRFAECR;
-  uint32_t      RESERVED6[10];
-  __IO uint32_t MMCRGUFCR;
-  uint32_t      RESERVED7[334];
-  __IO uint32_t PTPTSCR;
-  __IO uint32_t PTPSSIR;
-  __IO uint32_t PTPTSHR;
-  __IO uint32_t PTPTSLR;
-  __IO uint32_t PTPTSHUR;
-  __IO uint32_t PTPTSLUR;
-  __IO uint32_t PTPTSAR;
-  __IO uint32_t PTPTTHR;
-  __IO uint32_t PTPTTLR;
-  __IO uint32_t RESERVED8;
-  __IO uint32_t PTPTSSR;
-  uint32_t      RESERVED9[565];
-  __IO uint32_t DMABMR;
-  __IO uint32_t DMATPDR;
-  __IO uint32_t DMARPDR;
-  __IO uint32_t DMARDLAR;
-  __IO uint32_t DMATDLAR;
-  __IO uint32_t DMASR;
-  __IO uint32_t DMAOMR;
-  __IO uint32_t DMAIER;
-  __IO uint32_t DMAMFBOCR;
-  __IO uint32_t DMARSWTR;
-  uint32_t      RESERVED10[8];
-  __IO uint32_t DMACHTDR;
-  __IO uint32_t DMACHRDR;
-  __IO uint32_t DMACHTBAR;
-  __IO uint32_t DMACHRBAR;
-} ETH_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
-  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
-  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
-  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
-  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
-  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-
-typedef struct
-{
-  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
-  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
-  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
-  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
-  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
-  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
-} FLASH_TypeDef;
-
-
-
-/** 
-  * @brief Flexible Static Memory Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
-} FSMC_Bank1_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank1E
-  */
-
-typedef struct
-{
-  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
-} FSMC_Bank1E_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank2
-  */
-  
-typedef struct
-{
-  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
-  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
-  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
-  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
-  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
-  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
-  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
-  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
-  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
-  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
-  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
-  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
-  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
-  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
-} FSMC_Bank2_3_TypeDef;
-
-/** 
-  * @brief Flexible Static Memory Controller Bank4
-  */
-
-typedef struct
-{
-  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
-  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
-  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
-  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
-  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
-} FSMC_Bank4_TypeDef; 
-
-/** 
-  * @brief General Purpose I/O
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
-  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
-} GPIO_TypeDef;
-
-/** 
-  * @brief System configuration controller
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */
-  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
-  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
-  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
-  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
-  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
-  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
-  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
-  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-} IWDG_TypeDef;
-
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-
-typedef struct
-{
-  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
-  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
-  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
-  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
-  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
-  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
-  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
-  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
-  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
-  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
-  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
-  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
-  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
-  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
-  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
-  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
-  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
-  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
-  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
-  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
-  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
-  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
-  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
-  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
-  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
-  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
-  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
-  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
-  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
-  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
-  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
-  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
-  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
-  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
-  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
-  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
-  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
-} RTC_TypeDef;
-
-/** 
-  * @brief SD host Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */
-  __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */
-  __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */
-  __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */
-  __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
-  __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
-  __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
-  __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
-  __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
-  __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */
-  __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */
-  __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */
-  __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
-  __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
-  __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */
-  __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */
-  uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */
-  __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
-  uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */
-  __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */
-} SDIO_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-
-/** 
-  * @brief TIM
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
-  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
-  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
-  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
-  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
-  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
-  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief RNG
-  */
-  
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/** 
-  * @brief USB_OTG_Core_Registers
-  */
-typedef struct
-{
-  __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */
-  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
-  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
-  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
-  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
-  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
-  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
-  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
-  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
-  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
-  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
-  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
-  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
-  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
-  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
-  uint32_t  Reserved40[48];           /*!< Reserved                                0x40-0xFF */
-  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
-  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */
-} USB_OTG_GlobalTypeDef;
-
-/** 
-  * @brief USB_OTG_device_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
-  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
-  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
-  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
-  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
-  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
-  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
-  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
-  uint32_t  Reserved20;          /*!< Reserved                     820h */
-  uint32_t Reserved9;            /*!< Reserved                     824h */
-  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
-  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
-  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
-  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
-  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
-  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
-  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
-  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
-  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
-  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
-} USB_OTG_DeviceTypeDef;
-
-/** 
-  * @brief USB_OTG_IN_Endpoint-Specific_Register
-  */
-typedef struct 
-{
-  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
-  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
-  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
-  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
-  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
-} USB_OTG_INEndpointTypeDef;
-
-/** 
-  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
-  */
-typedef struct 
-{
-  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
-  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
-  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
-  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
-  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
-  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
-  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
-} USB_OTG_OUTEndpointTypeDef;
-
-/** 
-  * @brief USB_OTG_Host_Mode_Register_Structures
-  */
-typedef struct 
-{
-  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
-  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
-  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
-  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
-  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
-  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
-  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
-} USB_OTG_HostTypeDef;
-
-/** 
-  * @brief USB_OTG_Host_Channel_Specific_Registers
-  */
-typedef struct
-{
-  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
-  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
-  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
-  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
-  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
-  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
-  uint32_t Reserved[2];           /*!< Reserved                                      */
-} USB_OTG_HostChannelTypeDef;
-
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-#define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */
-#define CCMDATARAM_BASE       0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
-#define SRAM1_BASE            0x20000000UL /*!< SRAM1(112 KB) base address in the alias region                              */
-#define SRAM2_BASE            0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region                              */
-#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */
-#define BKPSRAM_BASE          0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region                         */
-#define FSMC_R_BASE           0xA0000000UL /*!< FSMC registers base address                                                */
-#define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region                          */
-#define SRAM2_BB_BASE         0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region                           */
-#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */
-#define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
-#define FLASH_END             0x080FFFFFUL /*!< FLASH end address                                                          */
-#define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */
-#define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */
-#define CCMDATARAM_END        0x1000FFFFUL /*!< CCM data RAM end address                                                   */
-
-/* Legacy defines */
-#define SRAM_BASE             SRAM1_BASE
-#define SRAM_BB_BASE          SRAM1_BB_BASE
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
-#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
-#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
-#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)
-#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)
-#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
-#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400UL)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
-#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000UL)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
-#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
-#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
-#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)
-#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
-
-/*!< APB2 peripherals */
-#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)
-#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
-#define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
-#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)
-#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)
-#define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300UL)
-/* Legacy define */
-#define ADC_BASE               ADC123_COMMON_BASE
-#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)
-
-/*!< AHB1 peripherals */
-#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
-#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
-#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
-#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)
-#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)
-#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)
-#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)
-#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
-#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000UL)
-#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
-#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)
-#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
-#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
-#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
-#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
-#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
-#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
-#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
-#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
-#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
-#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
-#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
-#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
-#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
-#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
-#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
-#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
-#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
-#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
-#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
-#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000UL)
-#define ETH_MAC_BASE          (ETH_BASE)
-#define ETH_MMC_BASE          (ETH_BASE + 0x0100UL)
-#define ETH_PTP_BASE          (ETH_BASE + 0x0700UL)
-#define ETH_DMA_BASE          (ETH_BASE + 0x1000UL)
-
-/*!< AHB2 peripherals */
-#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000UL)
-#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)
-
-/*!< FSMC Bankx registers base address */
-#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000UL)
-#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104UL)
-#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060UL)
-#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0UL)
-
-
-/*!< Debug MCU registers base address */
-#define DBGMCU_BASE           0xE0042000UL
-/*!< USB registers base address */
-#define USB_OTG_HS_PERIPH_BASE               0x40040000UL
-#define USB_OTG_FS_PERIPH_BASE               0x50000000UL
-
-#define USB_OTG_GLOBAL_BASE                  0x000UL
-#define USB_OTG_DEVICE_BASE                  0x800UL
-#define USB_OTG_IN_ENDPOINT_BASE             0x900UL
-#define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL
-#define USB_OTG_EP_REG_SIZE                  0x20UL
-#define USB_OTG_HOST_BASE                    0x400UL
-#define USB_OTG_HOST_PORT_BASE               0x440UL
-#define USB_OTG_HOST_CHANNEL_BASE            0x500UL
-#define USB_OTG_HOST_CHANNEL_SIZE            0x20UL
-#define USB_OTG_PCGCCTL_BASE                 0xE00UL
-#define USB_OTG_FIFO_BASE                    0x1000UL
-#define USB_OTG_FIFO_SIZE                    0x1000UL
-
-#define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */
-#define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */
-#define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */
-/**
-  * @}
-  */
-
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
-#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
-#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
-#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC1                ((DAC_TypeDef *) DAC_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
-#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
-#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define USART6              ((USART_TypeDef *) USART6_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
-#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
-#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
-/* Legacy define */
-#define ADC                  ADC123_COMMON
-#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
-#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
-#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
-#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
-#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
-#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
-#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
-#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
-#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
-#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
-#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
-#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
-#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
-#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
-#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
-#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
-#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
-#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
-#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
-#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
-#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-/** @addtogroup Hardware_Constant_Definition
-  * @{
-  */
-#define LSI_STARTUP_TIME                40U /*!< LSI Maximum startup time in us */
-/**
-  * @}
-  */
-
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers_Bits_Definition               */
-/******************************************************************************/
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Analog to Digital Converter                         */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
- */
-#define ADC_MULTIMODE_SUPPORT                                                  /*!<ADC Multimode feature available on specific devices */
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define ADC_SR_AWD_Pos            (0U)                                         
-#define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */
-#define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */
-#define ADC_SR_EOC_Pos            (1U)                                         
-#define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */
-#define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */
-#define ADC_SR_JEOC_Pos           (2U)                                         
-#define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */
-#define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */
-#define ADC_SR_JSTRT_Pos          (3U)                                         
-#define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */
-#define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */
-#define ADC_SR_STRT_Pos           (4U)                                         
-#define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */
-#define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */
-#define ADC_SR_OVR_Pos            (5U)                                         
-#define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */
-#define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define ADC_CR1_AWDCH_Pos         (0U)                                         
-#define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */
-#define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */
-#define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */
-#define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */
-#define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */
-#define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */
-#define ADC_CR1_EOCIE_Pos         (5U)                                         
-#define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */
-#define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */
-#define ADC_CR1_AWDIE_Pos         (6U)                                         
-#define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */
-#define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */
-#define ADC_CR1_JEOCIE_Pos        (7U)                                         
-#define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */
-#define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */
-#define ADC_CR1_SCAN_Pos          (8U)                                         
-#define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */
-#define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */
-#define ADC_CR1_AWDSGL_Pos        (9U)                                         
-#define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */
-#define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */
-#define ADC_CR1_JAUTO_Pos         (10U)                                        
-#define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */
-#define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */
-#define ADC_CR1_DISCEN_Pos        (11U)                                        
-#define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */
-#define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */
-#define ADC_CR1_JDISCEN_Pos       (12U)                                        
-#define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */
-#define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */
-#define ADC_CR1_DISCNUM_Pos       (13U)                                        
-#define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */
-#define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */
-#define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */
-#define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */
-#define ADC_CR1_JAWDEN_Pos        (22U)                                        
-#define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */
-#define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */
-#define ADC_CR1_AWDEN_Pos         (23U)                                        
-#define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */
-#define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */
-#define ADC_CR1_RES_Pos           (24U)                                        
-#define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */
-#define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */
-#define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */
-#define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */
-#define ADC_CR1_OVRIE_Pos         (26U)                                        
-#define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */
-#define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define ADC_CR2_ADON_Pos          (0U)                                         
-#define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */
-#define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */
-#define ADC_CR2_CONT_Pos          (1U)                                         
-#define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */
-#define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */
-#define ADC_CR2_DMA_Pos           (8U)                                         
-#define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */
-#define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */
-#define ADC_CR2_DDS_Pos           (9U)                                         
-#define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */
-#define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */
-#define ADC_CR2_EOCS_Pos          (10U)                                        
-#define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */
-#define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */
-#define ADC_CR2_ALIGN_Pos         (11U)                                        
-#define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */
-#define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */
-#define ADC_CR2_JEXTSEL_Pos       (16U)                                        
-#define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */
-#define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */
-#define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */
-#define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */
-#define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */
-#define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */
-#define ADC_CR2_JEXTEN_Pos        (20U)                                        
-#define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */
-#define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
-#define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */
-#define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */
-#define ADC_CR2_JSWSTART_Pos      (22U)                                        
-#define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */
-#define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */
-#define ADC_CR2_EXTSEL_Pos        (24U)                                        
-#define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */
-#define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
-#define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */
-#define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */
-#define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */
-#define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */
-#define ADC_CR2_EXTEN_Pos         (28U)                                        
-#define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */
-#define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
-#define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */
-#define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */
-#define ADC_CR2_SWSTART_Pos       (30U)                                        
-#define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */
-#define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define ADC_SMPR1_SMP10_Pos       (0U)                                         
-#define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */
-#define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */
-#define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */
-#define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */
-#define ADC_SMPR1_SMP11_Pos       (3U)                                         
-#define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */
-#define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */
-#define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */
-#define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */
-#define ADC_SMPR1_SMP12_Pos       (6U)                                         
-#define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */
-#define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */
-#define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */
-#define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */
-#define ADC_SMPR1_SMP13_Pos       (9U)                                         
-#define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */
-#define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */
-#define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */
-#define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */
-#define ADC_SMPR1_SMP14_Pos       (12U)                                        
-#define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */
-#define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */
-#define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */
-#define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */
-#define ADC_SMPR1_SMP15_Pos       (15U)                                        
-#define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */
-#define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */
-#define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */
-#define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */
-#define ADC_SMPR1_SMP16_Pos       (18U)                                        
-#define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */
-#define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */
-#define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */
-#define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */
-#define ADC_SMPR1_SMP17_Pos       (21U)                                        
-#define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */
-#define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */
-#define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */
-#define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */
-#define ADC_SMPR1_SMP18_Pos       (24U)                                        
-#define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */
-#define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */
-#define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */
-#define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define ADC_SMPR2_SMP0_Pos        (0U)                                         
-#define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */
-#define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */
-#define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */
-#define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */
-#define ADC_SMPR2_SMP1_Pos        (3U)                                         
-#define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */
-#define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */
-#define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */
-#define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */
-#define ADC_SMPR2_SMP2_Pos        (6U)                                         
-#define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */
-#define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */
-#define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */
-#define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */
-#define ADC_SMPR2_SMP3_Pos        (9U)                                         
-#define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */
-#define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */
-#define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */
-#define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */
-#define ADC_SMPR2_SMP4_Pos        (12U)                                        
-#define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */
-#define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */
-#define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */
-#define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */
-#define ADC_SMPR2_SMP5_Pos        (15U)                                        
-#define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */
-#define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */
-#define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */
-#define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */
-#define ADC_SMPR2_SMP6_Pos        (18U)                                        
-#define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */
-#define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */
-#define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */
-#define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */
-#define ADC_SMPR2_SMP7_Pos        (21U)                                        
-#define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */
-#define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */
-#define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */
-#define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */
-#define ADC_SMPR2_SMP8_Pos        (24U)                                        
-#define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */
-#define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */
-#define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */
-#define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */
-#define ADC_SMPR2_SMP9_Pos        (27U)                                        
-#define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */
-#define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */
-#define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */
-#define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define ADC_JOFR1_JOFFSET1_Pos    (0U)                                         
-#define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */
-#define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define ADC_JOFR2_JOFFSET2_Pos    (0U)                                         
-#define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */
-#define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define ADC_JOFR3_JOFFSET3_Pos    (0U)                                         
-#define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */
-#define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define ADC_JOFR4_JOFFSET4_Pos    (0U)                                         
-#define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */
-#define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define ADC_HTR_HT_Pos            (0U)                                         
-#define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */
-#define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define ADC_LTR_LT_Pos            (0U)                                         
-#define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */
-#define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define ADC_SQR1_SQ13_Pos         (0U)                                         
-#define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */
-#define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
-#define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */
-#define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */
-#define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */
-#define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */
-#define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */
-#define ADC_SQR1_SQ14_Pos         (5U)                                         
-#define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */
-#define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
-#define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */
-#define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */
-#define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */
-#define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */
-#define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */
-#define ADC_SQR1_SQ15_Pos         (10U)                                        
-#define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */
-#define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
-#define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */
-#define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */
-#define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */
-#define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */
-#define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */
-#define ADC_SQR1_SQ16_Pos         (15U)                                        
-#define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */
-#define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
-#define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */
-#define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */
-#define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */
-#define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */
-#define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */
-#define ADC_SQR1_L_Pos            (20U)                                        
-#define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */
-#define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */
-#define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */
-#define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */
-#define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */
-#define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define ADC_SQR2_SQ7_Pos          (0U)                                         
-#define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */
-#define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
-#define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */
-#define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */
-#define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */
-#define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */
-#define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */
-#define ADC_SQR2_SQ8_Pos          (5U)                                         
-#define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */
-#define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
-#define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */
-#define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */
-#define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */
-#define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */
-#define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */
-#define ADC_SQR2_SQ9_Pos          (10U)                                        
-#define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */
-#define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
-#define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */
-#define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */
-#define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */
-#define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */
-#define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */
-#define ADC_SQR2_SQ10_Pos         (15U)                                        
-#define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */
-#define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
-#define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */
-#define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */
-#define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */
-#define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */
-#define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */
-#define ADC_SQR2_SQ11_Pos         (20U)                                        
-#define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */
-#define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
-#define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */
-#define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */
-#define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */
-#define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */
-#define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */
-#define ADC_SQR2_SQ12_Pos         (25U)                                        
-#define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */
-#define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
-#define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */
-#define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */
-#define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */
-#define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */
-#define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define ADC_SQR3_SQ1_Pos          (0U)                                         
-#define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */
-#define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
-#define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */
-#define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */
-#define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */
-#define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */
-#define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */
-#define ADC_SQR3_SQ2_Pos          (5U)                                         
-#define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */
-#define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */
-#define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */
-#define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */
-#define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */
-#define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */
-#define ADC_SQR3_SQ3_Pos          (10U)                                        
-#define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */
-#define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */
-#define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */
-#define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */
-#define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */
-#define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */
-#define ADC_SQR3_SQ4_Pos          (15U)                                        
-#define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */
-#define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
-#define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */
-#define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */
-#define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */
-#define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */
-#define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */
-#define ADC_SQR3_SQ5_Pos          (20U)                                        
-#define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */
-#define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
-#define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */
-#define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */
-#define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */
-#define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */
-#define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */
-#define ADC_SQR3_SQ6_Pos          (25U)                                        
-#define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */
-#define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
-#define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */
-#define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */
-#define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */
-#define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */
-#define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define ADC_JSQR_JSQ1_Pos         (0U)                                         
-#define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */
-#define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */
-#define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */
-#define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */
-#define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */
-#define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */
-#define ADC_JSQR_JSQ2_Pos         (5U)                                         
-#define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */
-#define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */
-#define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */
-#define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */
-#define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */
-#define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */
-#define ADC_JSQR_JSQ3_Pos         (10U)                                        
-#define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */
-#define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */
-#define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */
-#define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */
-#define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */
-#define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */
-#define ADC_JSQR_JSQ4_Pos         (15U)                                        
-#define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */
-#define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */
-#define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */
-#define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */
-#define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */
-#define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */
-#define ADC_JSQR_JL_Pos           (20U)                                        
-#define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */
-#define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */
-#define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */
-#define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define ADC_JDR1_JDATA_Pos        (0U)                                         
-#define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */
-#define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define ADC_JDR2_JDATA_Pos        (0U)                                         
-#define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */
-#define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define ADC_JDR3_JDATA_Pos        (0U)                                         
-#define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */
-#define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define ADC_JDR4_JDATA_Pos        (0U)                                         
-#define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */
-#define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA_Pos           (0U)                                         
-#define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */
-#define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */
-#define ADC_DR_ADC2DATA_Pos       (16U)                                        
-#define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */
-#define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define ADC_CSR_AWD1_Pos          (0U)                                         
-#define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */
-#define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */
-#define ADC_CSR_EOC1_Pos          (1U)                                         
-#define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */
-#define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */
-#define ADC_CSR_JEOC1_Pos         (2U)                                         
-#define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */
-#define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */
-#define ADC_CSR_JSTRT1_Pos        (3U)                                         
-#define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */
-#define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */
-#define ADC_CSR_STRT1_Pos         (4U)                                         
-#define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */
-#define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */
-#define ADC_CSR_OVR1_Pos          (5U)                                         
-#define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */
-#define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */
-#define ADC_CSR_AWD2_Pos          (8U)                                         
-#define ADC_CSR_AWD2_Msk          (0x1UL << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */
-#define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag */
-#define ADC_CSR_EOC2_Pos          (9U)                                         
-#define ADC_CSR_EOC2_Msk          (0x1UL << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */
-#define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion */
-#define ADC_CSR_JEOC2_Pos         (10U)                                        
-#define ADC_CSR_JEOC2_Msk         (0x1UL << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */
-#define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */
-#define ADC_CSR_JSTRT2_Pos        (11U)                                        
-#define ADC_CSR_JSTRT2_Msk        (0x1UL << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */
-#define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag */
-#define ADC_CSR_STRT2_Pos         (12U)                                        
-#define ADC_CSR_STRT2_Msk         (0x1UL << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */
-#define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag */
-#define ADC_CSR_OVR2_Pos          (13U)                                        
-#define ADC_CSR_OVR2_Msk          (0x1UL << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */
-#define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 DMA overrun  flag */
-#define ADC_CSR_AWD3_Pos          (16U)                                        
-#define ADC_CSR_AWD3_Msk          (0x1UL << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */
-#define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag */
-#define ADC_CSR_EOC3_Pos          (17U)                                        
-#define ADC_CSR_EOC3_Msk          (0x1UL << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */
-#define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion */
-#define ADC_CSR_JEOC3_Pos         (18U)                                        
-#define ADC_CSR_JEOC3_Msk         (0x1UL << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */
-#define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */
-#define ADC_CSR_JSTRT3_Pos        (19U)                                        
-#define ADC_CSR_JSTRT3_Msk        (0x1UL << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */
-#define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag */
-#define ADC_CSR_STRT3_Pos         (20U)                                        
-#define ADC_CSR_STRT3_Msk         (0x1UL << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */
-#define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag */
-#define ADC_CSR_OVR3_Pos          (21U)                                        
-#define ADC_CSR_OVR3_Msk          (0x1UL << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */
-#define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 DMA overrun  flag */
-
-/* Legacy defines */
-#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
-#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
-#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_MULTI_Pos         (0U)                                         
-#define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */
-#define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
-#define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */
-#define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */
-#define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */
-#define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */
-#define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */
-#define ADC_CCR_DELAY_Pos         (8U)                                         
-#define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */
-#define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
-#define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */
-#define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */
-#define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */
-#define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */
-#define ADC_CCR_DDS_Pos           (13U)                                        
-#define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */
-#define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */
-#define ADC_CCR_DMA_Pos           (14U)                                        
-#define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */
-#define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
-#define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */
-#define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */
-#define ADC_CCR_ADCPRE_Pos        (16U)                                        
-#define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */
-#define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */  
-#define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */
-#define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */
-#define ADC_CCR_VBATE_Pos         (22U)                                        
-#define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */
-#define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */
-#define ADC_CCR_TSVREFE_Pos       (23U)                                        
-#define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */
-#define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */
-
-/*******************  Bit definition for ADC_CDR register  ********************/
-#define ADC_CDR_DATA1_Pos         (0U)                                         
-#define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */
-#define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */
-#define ADC_CDR_DATA2_Pos         (16U)                                        
-#define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */
-#define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */
-
-/* Legacy defines */
-#define ADC_CDR_RDATA_MST         ADC_CDR_DATA1
-#define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Controller Area Network                            */
-/*                                                                            */
-/******************************************************************************/
-/*!<CAN control and status registers */
-/*******************  Bit definition for CAN_MCR register  ********************/
-#define CAN_MCR_INRQ_Pos       (0U)                                            
-#define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
-#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
-#define CAN_MCR_SLEEP_Pos      (1U)                                            
-#define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
-#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
-#define CAN_MCR_TXFP_Pos       (2U)                                            
-#define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
-#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
-#define CAN_MCR_RFLM_Pos       (3U)                                            
-#define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
-#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
-#define CAN_MCR_NART_Pos       (4U)                                            
-#define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
-#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
-#define CAN_MCR_AWUM_Pos       (5U)                                            
-#define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
-#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
-#define CAN_MCR_ABOM_Pos       (6U)                                            
-#define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
-#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
-#define CAN_MCR_TTCM_Pos       (7U)                                            
-#define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
-#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
-#define CAN_MCR_RESET_Pos      (15U)                                           
-#define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
-#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
-#define CAN_MCR_DBF_Pos        (16U)                                           
-#define CAN_MCR_DBF_Msk        (0x1UL << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */
-#define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */
-/*******************  Bit definition for CAN_MSR register  ********************/
-#define CAN_MSR_INAK_Pos       (0U)                                            
-#define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
-#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
-#define CAN_MSR_SLAK_Pos       (1U)                                            
-#define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
-#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
-#define CAN_MSR_ERRI_Pos       (2U)                                            
-#define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
-#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
-#define CAN_MSR_WKUI_Pos       (3U)                                            
-#define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
-#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
-#define CAN_MSR_SLAKI_Pos      (4U)                                            
-#define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
-#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
-#define CAN_MSR_TXM_Pos        (8U)                                            
-#define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
-#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
-#define CAN_MSR_RXM_Pos        (9U)                                            
-#define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
-#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
-#define CAN_MSR_SAMP_Pos       (10U)                                           
-#define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
-#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
-#define CAN_MSR_RX_Pos         (11U)                                           
-#define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
-#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
-
-/*******************  Bit definition for CAN_TSR register  ********************/
-#define CAN_TSR_RQCP0_Pos      (0U)                                            
-#define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
-#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
-#define CAN_TSR_TXOK0_Pos      (1U)                                            
-#define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
-#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
-#define CAN_TSR_ALST0_Pos      (2U)                                            
-#define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
-#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
-#define CAN_TSR_TERR0_Pos      (3U)                                            
-#define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
-#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
-#define CAN_TSR_ABRQ0_Pos      (7U)                                            
-#define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
-#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
-#define CAN_TSR_RQCP1_Pos      (8U)                                            
-#define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
-#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
-#define CAN_TSR_TXOK1_Pos      (9U)                                            
-#define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
-#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
-#define CAN_TSR_ALST1_Pos      (10U)                                           
-#define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
-#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
-#define CAN_TSR_TERR1_Pos      (11U)                                           
-#define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
-#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
-#define CAN_TSR_ABRQ1_Pos      (15U)                                           
-#define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
-#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
-#define CAN_TSR_RQCP2_Pos      (16U)                                           
-#define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
-#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
-#define CAN_TSR_TXOK2_Pos      (17U)                                           
-#define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
-#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
-#define CAN_TSR_ALST2_Pos      (18U)                                           
-#define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
-#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
-#define CAN_TSR_TERR2_Pos      (19U)                                           
-#define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
-#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
-#define CAN_TSR_ABRQ2_Pos      (23U)                                           
-#define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
-#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
-#define CAN_TSR_CODE_Pos       (24U)                                           
-#define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
-#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
-
-#define CAN_TSR_TME_Pos        (26U)                                           
-#define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
-#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
-#define CAN_TSR_TME0_Pos       (26U)                                           
-#define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
-#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
-#define CAN_TSR_TME1_Pos       (27U)                                           
-#define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
-#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
-#define CAN_TSR_TME2_Pos       (28U)                                           
-#define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
-#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
-
-#define CAN_TSR_LOW_Pos        (29U)                                           
-#define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
-#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
-#define CAN_TSR_LOW0_Pos       (29U)                                           
-#define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
-#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
-#define CAN_TSR_LOW1_Pos       (30U)                                           
-#define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
-#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
-#define CAN_TSR_LOW2_Pos       (31U)                                           
-#define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
-#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
-
-/*******************  Bit definition for CAN_RF0R register  *******************/
-#define CAN_RF0R_FMP0_Pos      (0U)                                            
-#define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
-#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
-#define CAN_RF0R_FULL0_Pos     (3U)                                            
-#define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
-#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
-#define CAN_RF0R_FOVR0_Pos     (4U)                                            
-#define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
-#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
-#define CAN_RF0R_RFOM0_Pos     (5U)                                            
-#define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
-#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
-
-/*******************  Bit definition for CAN_RF1R register  *******************/
-#define CAN_RF1R_FMP1_Pos      (0U)                                            
-#define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
-#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
-#define CAN_RF1R_FULL1_Pos     (3U)                                            
-#define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
-#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
-#define CAN_RF1R_FOVR1_Pos     (4U)                                            
-#define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
-#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
-#define CAN_RF1R_RFOM1_Pos     (5U)                                            
-#define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
-#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
-
-/********************  Bit definition for CAN_IER register  *******************/
-#define CAN_IER_TMEIE_Pos      (0U)                                            
-#define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
-#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
-#define CAN_IER_FMPIE0_Pos     (1U)                                            
-#define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
-#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE0_Pos      (2U)                                            
-#define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
-#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE0_Pos     (3U)                                            
-#define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
-#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
-#define CAN_IER_FMPIE1_Pos     (4U)                                            
-#define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
-#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE1_Pos      (5U)                                            
-#define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
-#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE1_Pos     (6U)                                            
-#define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
-#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
-#define CAN_IER_EWGIE_Pos      (8U)                                            
-#define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
-#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
-#define CAN_IER_EPVIE_Pos      (9U)                                            
-#define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
-#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
-#define CAN_IER_BOFIE_Pos      (10U)                                           
-#define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
-#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
-#define CAN_IER_LECIE_Pos      (11U)                                           
-#define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
-#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
-#define CAN_IER_ERRIE_Pos      (15U)                                           
-#define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
-#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
-#define CAN_IER_WKUIE_Pos      (16U)                                           
-#define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
-#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
-#define CAN_IER_SLKIE_Pos      (17U)                                           
-#define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
-#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
-#define CAN_IER_EWGIE_Pos      (8U)                                            
-
-/********************  Bit definition for CAN_ESR register  *******************/
-#define CAN_ESR_EWGF_Pos       (0U)                                            
-#define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
-#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
-#define CAN_ESR_EPVF_Pos       (1U)                                            
-#define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
-#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
-#define CAN_ESR_BOFF_Pos       (2U)                                            
-#define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
-#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
-
-#define CAN_ESR_LEC_Pos        (4U)                                            
-#define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
-#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
-#define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
-#define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
-#define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
-
-#define CAN_ESR_TEC_Pos        (16U)                                           
-#define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
-#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define CAN_ESR_REC_Pos        (24U)                                           
-#define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
-#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
-
-/*******************  Bit definition for CAN_BTR register  ********************/
-#define CAN_BTR_BRP_Pos        (0U)                                            
-#define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
-#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
-#define CAN_BTR_TS1_Pos        (16U)                                           
-#define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
-#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
-#define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
-#define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
-#define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
-#define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
-#define CAN_BTR_TS2_Pos        (20U)                                           
-#define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
-#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
-#define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
-#define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
-#define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
-#define CAN_BTR_SJW_Pos        (24U)                                           
-#define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
-#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
-#define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
-#define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
-#define CAN_BTR_LBKM_Pos       (30U)                                           
-#define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
-#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
-#define CAN_BTR_SILM_Pos       (31U)                                           
-#define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
-#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
-
-
-/*!<Mailbox registers */
-/******************  Bit definition for CAN_TI0R register  ********************/
-#define CAN_TI0R_TXRQ_Pos      (0U)                                            
-#define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
-#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
-#define CAN_TI0R_RTR_Pos       (1U)                                            
-#define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
-#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
-#define CAN_TI0R_IDE_Pos       (2U)                                            
-#define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
-#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
-#define CAN_TI0R_EXID_Pos      (3U)                                            
-#define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
-#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
-#define CAN_TI0R_STID_Pos      (21U)                                           
-#define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
-#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
-
-/******************  Bit definition for CAN_TDT0R register  *******************/
-#define CAN_TDT0R_DLC_Pos      (0U)                                            
-#define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
-#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
-#define CAN_TDT0R_TGT_Pos      (8U)                                            
-#define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
-#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
-#define CAN_TDT0R_TIME_Pos     (16U)                                           
-#define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
-#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
-
-/******************  Bit definition for CAN_TDL0R register  *******************/
-#define CAN_TDL0R_DATA0_Pos    (0U)                                            
-#define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
-#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
-#define CAN_TDL0R_DATA1_Pos    (8U)                                            
-#define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
-#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
-#define CAN_TDL0R_DATA2_Pos    (16U)                                           
-#define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
-#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
-#define CAN_TDL0R_DATA3_Pos    (24U)                                           
-#define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
-#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
-
-/******************  Bit definition for CAN_TDH0R register  *******************/
-#define CAN_TDH0R_DATA4_Pos    (0U)                                            
-#define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
-#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
-#define CAN_TDH0R_DATA5_Pos    (8U)                                            
-#define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
-#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
-#define CAN_TDH0R_DATA6_Pos    (16U)                                           
-#define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
-#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
-#define CAN_TDH0R_DATA7_Pos    (24U)                                           
-#define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
-#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI1R register  *******************/
-#define CAN_TI1R_TXRQ_Pos      (0U)                                            
-#define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
-#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
-#define CAN_TI1R_RTR_Pos       (1U)                                            
-#define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
-#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
-#define CAN_TI1R_IDE_Pos       (2U)                                            
-#define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
-#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
-#define CAN_TI1R_EXID_Pos      (3U)                                            
-#define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
-#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
-#define CAN_TI1R_STID_Pos      (21U)                                           
-#define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
-#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT1R register  ******************/
-#define CAN_TDT1R_DLC_Pos      (0U)                                            
-#define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
-#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
-#define CAN_TDT1R_TGT_Pos      (8U)                                            
-#define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
-#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
-#define CAN_TDT1R_TIME_Pos     (16U)                                           
-#define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
-#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL1R register  ******************/
-#define CAN_TDL1R_DATA0_Pos    (0U)                                            
-#define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
-#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
-#define CAN_TDL1R_DATA1_Pos    (8U)                                            
-#define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
-#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
-#define CAN_TDL1R_DATA2_Pos    (16U)                                           
-#define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
-#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
-#define CAN_TDL1R_DATA3_Pos    (24U)                                           
-#define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
-#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH1R register  ******************/
-#define CAN_TDH1R_DATA4_Pos    (0U)                                            
-#define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
-#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
-#define CAN_TDH1R_DATA5_Pos    (8U)                                            
-#define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
-#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
-#define CAN_TDH1R_DATA6_Pos    (16U)                                           
-#define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
-#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
-#define CAN_TDH1R_DATA7_Pos    (24U)                                           
-#define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
-#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_TI2R register  *******************/
-#define CAN_TI2R_TXRQ_Pos      (0U)                                            
-#define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
-#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
-#define CAN_TI2R_RTR_Pos       (1U)                                            
-#define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
-#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
-#define CAN_TI2R_IDE_Pos       (2U)                                            
-#define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
-#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
-#define CAN_TI2R_EXID_Pos      (3U)                                            
-#define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
-#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
-#define CAN_TI2R_STID_Pos      (21U)                                           
-#define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
-#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_TDT2R register  ******************/  
-#define CAN_TDT2R_DLC_Pos      (0U)                                            
-#define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
-#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
-#define CAN_TDT2R_TGT_Pos      (8U)                                            
-#define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
-#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
-#define CAN_TDT2R_TIME_Pos     (16U)                                           
-#define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
-#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_TDL2R register  ******************/
-#define CAN_TDL2R_DATA0_Pos    (0U)                                            
-#define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
-#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
-#define CAN_TDL2R_DATA1_Pos    (8U)                                            
-#define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
-#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
-#define CAN_TDL2R_DATA2_Pos    (16U)                                           
-#define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
-#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
-#define CAN_TDL2R_DATA3_Pos    (24U)                                           
-#define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
-#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_TDH2R register  ******************/
-#define CAN_TDH2R_DATA4_Pos    (0U)                                            
-#define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
-#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
-#define CAN_TDH2R_DATA5_Pos    (8U)                                            
-#define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
-#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
-#define CAN_TDH2R_DATA6_Pos    (16U)                                           
-#define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
-#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
-#define CAN_TDH2R_DATA7_Pos    (24U)                                           
-#define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
-#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI0R register  *******************/
-#define CAN_RI0R_RTR_Pos       (1U)                                            
-#define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
-#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
-#define CAN_RI0R_IDE_Pos       (2U)                                            
-#define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
-#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
-#define CAN_RI0R_EXID_Pos      (3U)                                            
-#define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
-#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
-#define CAN_RI0R_STID_Pos      (21U)                                           
-#define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
-#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT0R register  ******************/
-#define CAN_RDT0R_DLC_Pos      (0U)                                            
-#define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
-#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
-#define CAN_RDT0R_FMI_Pos      (8U)                                            
-#define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
-#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
-#define CAN_RDT0R_TIME_Pos     (16U)                                           
-#define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
-#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL0R register  ******************/
-#define CAN_RDL0R_DATA0_Pos    (0U)                                            
-#define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
-#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
-#define CAN_RDL0R_DATA1_Pos    (8U)                                            
-#define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
-#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
-#define CAN_RDL0R_DATA2_Pos    (16U)                                           
-#define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
-#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
-#define CAN_RDL0R_DATA3_Pos    (24U)                                           
-#define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
-#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH0R register  ******************/
-#define CAN_RDH0R_DATA4_Pos    (0U)                                            
-#define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
-#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
-#define CAN_RDH0R_DATA5_Pos    (8U)                                            
-#define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
-#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
-#define CAN_RDH0R_DATA6_Pos    (16U)                                           
-#define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
-#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
-#define CAN_RDH0R_DATA7_Pos    (24U)                                           
-#define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
-#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
-
-/*******************  Bit definition for CAN_RI1R register  *******************/
-#define CAN_RI1R_RTR_Pos       (1U)                                            
-#define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
-#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
-#define CAN_RI1R_IDE_Pos       (2U)                                            
-#define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
-#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
-#define CAN_RI1R_EXID_Pos      (3U)                                            
-#define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
-#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
-#define CAN_RI1R_STID_Pos      (21U)                                           
-#define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
-#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
-
-/*******************  Bit definition for CAN_RDT1R register  ******************/
-#define CAN_RDT1R_DLC_Pos      (0U)                                            
-#define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
-#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
-#define CAN_RDT1R_FMI_Pos      (8U)                                            
-#define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
-#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
-#define CAN_RDT1R_TIME_Pos     (16U)                                           
-#define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
-#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
-
-/*******************  Bit definition for CAN_RDL1R register  ******************/
-#define CAN_RDL1R_DATA0_Pos    (0U)                                            
-#define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
-#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
-#define CAN_RDL1R_DATA1_Pos    (8U)                                            
-#define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
-#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
-#define CAN_RDL1R_DATA2_Pos    (16U)                                           
-#define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
-#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
-#define CAN_RDL1R_DATA3_Pos    (24U)                                           
-#define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
-#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
-
-/*******************  Bit definition for CAN_RDH1R register  ******************/
-#define CAN_RDH1R_DATA4_Pos    (0U)                                            
-#define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
-#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
-#define CAN_RDH1R_DATA5_Pos    (8U)                                            
-#define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
-#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
-#define CAN_RDH1R_DATA6_Pos    (16U)                                           
-#define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
-#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
-#define CAN_RDH1R_DATA7_Pos    (24U)                                           
-#define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
-#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/*******************  Bit definition for CAN_FMR register  ********************/
-#define CAN_FMR_FINIT_Pos      (0U)                                            
-#define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
-#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
-#define CAN_FMR_CAN2SB_Pos     (8U)                                            
-#define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */
-#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */
-
-/*******************  Bit definition for CAN_FM1R register  *******************/
-#define CAN_FM1R_FBM_Pos       (0U)                                            
-#define CAN_FM1R_FBM_Msk       (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */
-#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
-#define CAN_FM1R_FBM0_Pos      (0U)                                            
-#define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
-#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
-#define CAN_FM1R_FBM1_Pos      (1U)                                            
-#define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
-#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
-#define CAN_FM1R_FBM2_Pos      (2U)                                            
-#define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
-#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
-#define CAN_FM1R_FBM3_Pos      (3U)                                            
-#define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
-#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
-#define CAN_FM1R_FBM4_Pos      (4U)                                            
-#define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
-#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
-#define CAN_FM1R_FBM5_Pos      (5U)                                            
-#define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
-#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
-#define CAN_FM1R_FBM6_Pos      (6U)                                            
-#define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
-#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
-#define CAN_FM1R_FBM7_Pos      (7U)                                            
-#define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
-#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
-#define CAN_FM1R_FBM8_Pos      (8U)                                            
-#define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
-#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
-#define CAN_FM1R_FBM9_Pos      (9U)                                            
-#define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
-#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
-#define CAN_FM1R_FBM10_Pos     (10U)                                           
-#define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
-#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
-#define CAN_FM1R_FBM11_Pos     (11U)                                           
-#define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
-#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
-#define CAN_FM1R_FBM12_Pos     (12U)                                           
-#define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
-#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
-#define CAN_FM1R_FBM13_Pos     (13U)                                           
-#define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
-#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
-#define CAN_FM1R_FBM14_Pos     (14U)                                           
-#define CAN_FM1R_FBM14_Msk     (0x1UL << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */
-#define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */
-#define CAN_FM1R_FBM15_Pos     (15U)                                           
-#define CAN_FM1R_FBM15_Msk     (0x1UL << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */
-#define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */
-#define CAN_FM1R_FBM16_Pos     (16U)                                           
-#define CAN_FM1R_FBM16_Msk     (0x1UL << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */
-#define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */
-#define CAN_FM1R_FBM17_Pos     (17U)                                           
-#define CAN_FM1R_FBM17_Msk     (0x1UL << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */
-#define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */
-#define CAN_FM1R_FBM18_Pos     (18U)                                           
-#define CAN_FM1R_FBM18_Msk     (0x1UL << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */
-#define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */
-#define CAN_FM1R_FBM19_Pos     (19U)                                           
-#define CAN_FM1R_FBM19_Msk     (0x1UL << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */
-#define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */
-#define CAN_FM1R_FBM20_Pos     (20U)                                           
-#define CAN_FM1R_FBM20_Msk     (0x1UL << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */
-#define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */
-#define CAN_FM1R_FBM21_Pos     (21U)                                           
-#define CAN_FM1R_FBM21_Msk     (0x1UL << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */
-#define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */
-#define CAN_FM1R_FBM22_Pos     (22U)                                           
-#define CAN_FM1R_FBM22_Msk     (0x1UL << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */
-#define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */
-#define CAN_FM1R_FBM23_Pos     (23U)                                           
-#define CAN_FM1R_FBM23_Msk     (0x1UL << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */
-#define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */
-#define CAN_FM1R_FBM24_Pos     (24U)                                           
-#define CAN_FM1R_FBM24_Msk     (0x1UL << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */
-#define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */
-#define CAN_FM1R_FBM25_Pos     (25U)                                           
-#define CAN_FM1R_FBM25_Msk     (0x1UL << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */
-#define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */
-#define CAN_FM1R_FBM26_Pos     (26U)                                           
-#define CAN_FM1R_FBM26_Msk     (0x1UL << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */
-#define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */
-#define CAN_FM1R_FBM27_Pos     (27U)                                           
-#define CAN_FM1R_FBM27_Msk     (0x1UL << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */
-#define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */
-
-/*******************  Bit definition for CAN_FS1R register  *******************/
-#define CAN_FS1R_FSC_Pos       (0U)                                            
-#define CAN_FS1R_FSC_Msk       (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */
-#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
-#define CAN_FS1R_FSC0_Pos      (0U)                                            
-#define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
-#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
-#define CAN_FS1R_FSC1_Pos      (1U)                                            
-#define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
-#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
-#define CAN_FS1R_FSC2_Pos      (2U)                                            
-#define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
-#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
-#define CAN_FS1R_FSC3_Pos      (3U)                                            
-#define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
-#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
-#define CAN_FS1R_FSC4_Pos      (4U)                                            
-#define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
-#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
-#define CAN_FS1R_FSC5_Pos      (5U)                                            
-#define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
-#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
-#define CAN_FS1R_FSC6_Pos      (6U)                                            
-#define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
-#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
-#define CAN_FS1R_FSC7_Pos      (7U)                                            
-#define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
-#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
-#define CAN_FS1R_FSC8_Pos      (8U)                                            
-#define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
-#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
-#define CAN_FS1R_FSC9_Pos      (9U)                                            
-#define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
-#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
-#define CAN_FS1R_FSC10_Pos     (10U)                                           
-#define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
-#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
-#define CAN_FS1R_FSC11_Pos     (11U)                                           
-#define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
-#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
-#define CAN_FS1R_FSC12_Pos     (12U)                                           
-#define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
-#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
-#define CAN_FS1R_FSC13_Pos     (13U)                                           
-#define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
-#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
-#define CAN_FS1R_FSC14_Pos     (14U)                                           
-#define CAN_FS1R_FSC14_Msk     (0x1UL << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */
-#define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */
-#define CAN_FS1R_FSC15_Pos     (15U)                                           
-#define CAN_FS1R_FSC15_Msk     (0x1UL << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */
-#define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */
-#define CAN_FS1R_FSC16_Pos     (16U)                                           
-#define CAN_FS1R_FSC16_Msk     (0x1UL << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */
-#define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */
-#define CAN_FS1R_FSC17_Pos     (17U)                                           
-#define CAN_FS1R_FSC17_Msk     (0x1UL << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */
-#define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */
-#define CAN_FS1R_FSC18_Pos     (18U)                                           
-#define CAN_FS1R_FSC18_Msk     (0x1UL << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */
-#define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */
-#define CAN_FS1R_FSC19_Pos     (19U)                                           
-#define CAN_FS1R_FSC19_Msk     (0x1UL << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */
-#define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */
-#define CAN_FS1R_FSC20_Pos     (20U)                                           
-#define CAN_FS1R_FSC20_Msk     (0x1UL << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */
-#define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */
-#define CAN_FS1R_FSC21_Pos     (21U)                                           
-#define CAN_FS1R_FSC21_Msk     (0x1UL << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */
-#define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */
-#define CAN_FS1R_FSC22_Pos     (22U)                                           
-#define CAN_FS1R_FSC22_Msk     (0x1UL << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */
-#define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */
-#define CAN_FS1R_FSC23_Pos     (23U)                                           
-#define CAN_FS1R_FSC23_Msk     (0x1UL << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */
-#define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */
-#define CAN_FS1R_FSC24_Pos     (24U)                                           
-#define CAN_FS1R_FSC24_Msk     (0x1UL << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */
-#define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */
-#define CAN_FS1R_FSC25_Pos     (25U)                                           
-#define CAN_FS1R_FSC25_Msk     (0x1UL << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */
-#define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */
-#define CAN_FS1R_FSC26_Pos     (26U)                                           
-#define CAN_FS1R_FSC26_Msk     (0x1UL << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */
-#define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */
-#define CAN_FS1R_FSC27_Pos     (27U)                                           
-#define CAN_FS1R_FSC27_Msk     (0x1UL << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */
-#define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */
-
-/******************  Bit definition for CAN_FFA1R register  *******************/
-#define CAN_FFA1R_FFA_Pos      (0U)                                            
-#define CAN_FFA1R_FFA_Msk      (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */
-#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0_Pos     (0U)                                            
-#define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
-#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */
-#define CAN_FFA1R_FFA1_Pos     (1U)                                            
-#define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
-#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */
-#define CAN_FFA1R_FFA2_Pos     (2U)                                            
-#define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
-#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */
-#define CAN_FFA1R_FFA3_Pos     (3U)                                            
-#define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
-#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */
-#define CAN_FFA1R_FFA4_Pos     (4U)                                            
-#define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
-#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */
-#define CAN_FFA1R_FFA5_Pos     (5U)                                            
-#define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
-#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */
-#define CAN_FFA1R_FFA6_Pos     (6U)                                            
-#define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
-#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */
-#define CAN_FFA1R_FFA7_Pos     (7U)                                            
-#define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
-#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */
-#define CAN_FFA1R_FFA8_Pos     (8U)                                            
-#define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
-#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */
-#define CAN_FFA1R_FFA9_Pos     (9U)                                            
-#define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
-#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */
-#define CAN_FFA1R_FFA10_Pos    (10U)                                           
-#define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
-#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */
-#define CAN_FFA1R_FFA11_Pos    (11U)                                           
-#define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
-#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */
-#define CAN_FFA1R_FFA12_Pos    (12U)                                           
-#define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
-#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */
-#define CAN_FFA1R_FFA13_Pos    (13U)                                           
-#define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
-#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */
-#define CAN_FFA1R_FFA14_Pos    (14U)                                           
-#define CAN_FFA1R_FFA14_Msk    (0x1UL << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */
-#define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */
-#define CAN_FFA1R_FFA15_Pos    (15U)                                           
-#define CAN_FFA1R_FFA15_Msk    (0x1UL << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */
-#define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */
-#define CAN_FFA1R_FFA16_Pos    (16U)                                           
-#define CAN_FFA1R_FFA16_Msk    (0x1UL << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */
-#define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */
-#define CAN_FFA1R_FFA17_Pos    (17U)                                           
-#define CAN_FFA1R_FFA17_Msk    (0x1UL << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */
-#define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */
-#define CAN_FFA1R_FFA18_Pos    (18U)                                           
-#define CAN_FFA1R_FFA18_Msk    (0x1UL << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */
-#define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */
-#define CAN_FFA1R_FFA19_Pos    (19U)                                           
-#define CAN_FFA1R_FFA19_Msk    (0x1UL << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */
-#define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */
-#define CAN_FFA1R_FFA20_Pos    (20U)                                           
-#define CAN_FFA1R_FFA20_Msk    (0x1UL << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */
-#define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */
-#define CAN_FFA1R_FFA21_Pos    (21U)                                           
-#define CAN_FFA1R_FFA21_Msk    (0x1UL << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */
-#define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */
-#define CAN_FFA1R_FFA22_Pos    (22U)                                           
-#define CAN_FFA1R_FFA22_Msk    (0x1UL << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */
-#define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */
-#define CAN_FFA1R_FFA23_Pos    (23U)                                           
-#define CAN_FFA1R_FFA23_Msk    (0x1UL << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */
-#define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */
-#define CAN_FFA1R_FFA24_Pos    (24U)                                           
-#define CAN_FFA1R_FFA24_Msk    (0x1UL << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */
-#define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */
-#define CAN_FFA1R_FFA25_Pos    (25U)                                           
-#define CAN_FFA1R_FFA25_Msk    (0x1UL << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */
-#define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */
-#define CAN_FFA1R_FFA26_Pos    (26U)                                           
-#define CAN_FFA1R_FFA26_Msk    (0x1UL << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */
-#define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */
-#define CAN_FFA1R_FFA27_Pos    (27U)                                           
-#define CAN_FFA1R_FFA27_Msk    (0x1UL << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */
-#define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */
-
-/*******************  Bit definition for CAN_FA1R register  *******************/
-#define CAN_FA1R_FACT_Pos      (0U)                                            
-#define CAN_FA1R_FACT_Msk      (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */
-#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
-#define CAN_FA1R_FACT0_Pos     (0U)                                            
-#define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
-#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */
-#define CAN_FA1R_FACT1_Pos     (1U)                                            
-#define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
-#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */
-#define CAN_FA1R_FACT2_Pos     (2U)                                            
-#define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
-#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */
-#define CAN_FA1R_FACT3_Pos     (3U)                                            
-#define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
-#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */
-#define CAN_FA1R_FACT4_Pos     (4U)                                            
-#define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
-#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */
-#define CAN_FA1R_FACT5_Pos     (5U)                                            
-#define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
-#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */
-#define CAN_FA1R_FACT6_Pos     (6U)                                            
-#define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
-#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */
-#define CAN_FA1R_FACT7_Pos     (7U)                                            
-#define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
-#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */
-#define CAN_FA1R_FACT8_Pos     (8U)                                            
-#define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
-#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */
-#define CAN_FA1R_FACT9_Pos     (9U)                                            
-#define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
-#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */
-#define CAN_FA1R_FACT10_Pos    (10U)                                           
-#define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
-#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */
-#define CAN_FA1R_FACT11_Pos    (11U)                                           
-#define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
-#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */
-#define CAN_FA1R_FACT12_Pos    (12U)                                           
-#define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
-#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */
-#define CAN_FA1R_FACT13_Pos    (13U)                                           
-#define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
-#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */
-#define CAN_FA1R_FACT14_Pos    (14U)                                           
-#define CAN_FA1R_FACT14_Msk    (0x1UL << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */
-#define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */
-#define CAN_FA1R_FACT15_Pos    (15U)                                           
-#define CAN_FA1R_FACT15_Msk    (0x1UL << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */
-#define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */
-#define CAN_FA1R_FACT16_Pos    (16U)                                           
-#define CAN_FA1R_FACT16_Msk    (0x1UL << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */
-#define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */
-#define CAN_FA1R_FACT17_Pos    (17U)                                           
-#define CAN_FA1R_FACT17_Msk    (0x1UL << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */
-#define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */
-#define CAN_FA1R_FACT18_Pos    (18U)                                           
-#define CAN_FA1R_FACT18_Msk    (0x1UL << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */
-#define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */
-#define CAN_FA1R_FACT19_Pos    (19U)                                           
-#define CAN_FA1R_FACT19_Msk    (0x1UL << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */
-#define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */
-#define CAN_FA1R_FACT20_Pos    (20U)                                           
-#define CAN_FA1R_FACT20_Msk    (0x1UL << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */
-#define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */
-#define CAN_FA1R_FACT21_Pos    (21U)                                           
-#define CAN_FA1R_FACT21_Msk    (0x1UL << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */
-#define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */
-#define CAN_FA1R_FACT22_Pos    (22U)                                           
-#define CAN_FA1R_FACT22_Msk    (0x1UL << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */
-#define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */
-#define CAN_FA1R_FACT23_Pos    (23U)                                           
-#define CAN_FA1R_FACT23_Msk    (0x1UL << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */
-#define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */
-#define CAN_FA1R_FACT24_Pos    (24U)                                           
-#define CAN_FA1R_FACT24_Msk    (0x1UL << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */
-#define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */
-#define CAN_FA1R_FACT25_Pos    (25U)                                           
-#define CAN_FA1R_FACT25_Msk    (0x1UL << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */
-#define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */
-#define CAN_FA1R_FACT26_Pos    (26U)                                           
-#define CAN_FA1R_FACT26_Msk    (0x1UL << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */
-#define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */
-#define CAN_FA1R_FACT27_Pos    (27U)                                           
-#define CAN_FA1R_FACT27_Msk    (0x1UL << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */
-#define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */
-
-
-/*******************  Bit definition for CAN_F0R1 register  *******************/
-#define CAN_F0R1_FB0_Pos       (0U)                                            
-#define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F0R1_FB1_Pos       (1U)                                            
-#define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F0R1_FB2_Pos       (2U)                                            
-#define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F0R1_FB3_Pos       (3U)                                            
-#define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F0R1_FB4_Pos       (4U)                                            
-#define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F0R1_FB5_Pos       (5U)                                            
-#define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F0R1_FB6_Pos       (6U)                                            
-#define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F0R1_FB7_Pos       (7U)                                            
-#define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F0R1_FB8_Pos       (8U)                                            
-#define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F0R1_FB9_Pos       (9U)                                            
-#define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F0R1_FB10_Pos      (10U)                                           
-#define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F0R1_FB11_Pos      (11U)                                           
-#define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F0R1_FB12_Pos      (12U)                                           
-#define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F0R1_FB13_Pos      (13U)                                           
-#define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F0R1_FB14_Pos      (14U)                                           
-#define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F0R1_FB15_Pos      (15U)                                           
-#define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F0R1_FB16_Pos      (16U)                                           
-#define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F0R1_FB17_Pos      (17U)                                           
-#define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F0R1_FB18_Pos      (18U)                                           
-#define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F0R1_FB19_Pos      (19U)                                           
-#define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F0R1_FB20_Pos      (20U)                                           
-#define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F0R1_FB21_Pos      (21U)                                           
-#define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F0R1_FB22_Pos      (22U)                                           
-#define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F0R1_FB23_Pos      (23U)                                           
-#define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F0R1_FB24_Pos      (24U)                                           
-#define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F0R1_FB25_Pos      (25U)                                           
-#define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F0R1_FB26_Pos      (26U)                                           
-#define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F0R1_FB27_Pos      (27U)                                           
-#define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F0R1_FB28_Pos      (28U)                                           
-#define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F0R1_FB29_Pos      (29U)                                           
-#define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F0R1_FB30_Pos      (30U)                                           
-#define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F0R1_FB31_Pos      (31U)                                           
-#define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R1 register  *******************/
-#define CAN_F1R1_FB0_Pos       (0U)                                            
-#define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F1R1_FB1_Pos       (1U)                                            
-#define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F1R1_FB2_Pos       (2U)                                            
-#define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F1R1_FB3_Pos       (3U)                                            
-#define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F1R1_FB4_Pos       (4U)                                            
-#define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F1R1_FB5_Pos       (5U)                                            
-#define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F1R1_FB6_Pos       (6U)                                            
-#define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F1R1_FB7_Pos       (7U)                                            
-#define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F1R1_FB8_Pos       (8U)                                            
-#define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F1R1_FB9_Pos       (9U)                                            
-#define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F1R1_FB10_Pos      (10U)                                           
-#define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F1R1_FB11_Pos      (11U)                                           
-#define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F1R1_FB12_Pos      (12U)                                           
-#define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F1R1_FB13_Pos      (13U)                                           
-#define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F1R1_FB14_Pos      (14U)                                           
-#define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F1R1_FB15_Pos      (15U)                                           
-#define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F1R1_FB16_Pos      (16U)                                           
-#define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F1R1_FB17_Pos      (17U)                                           
-#define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F1R1_FB18_Pos      (18U)                                           
-#define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F1R1_FB19_Pos      (19U)                                           
-#define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F1R1_FB20_Pos      (20U)                                           
-#define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F1R1_FB21_Pos      (21U)                                           
-#define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F1R1_FB22_Pos      (22U)                                           
-#define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F1R1_FB23_Pos      (23U)                                           
-#define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F1R1_FB24_Pos      (24U)                                           
-#define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F1R1_FB25_Pos      (25U)                                           
-#define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F1R1_FB26_Pos      (26U)                                           
-#define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F1R1_FB27_Pos      (27U)                                           
-#define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F1R1_FB28_Pos      (28U)                                           
-#define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F1R1_FB29_Pos      (29U)                                           
-#define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F1R1_FB30_Pos      (30U)                                           
-#define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F1R1_FB31_Pos      (31U)                                           
-#define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R1 register  *******************/
-#define CAN_F2R1_FB0_Pos       (0U)                                            
-#define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F2R1_FB1_Pos       (1U)                                            
-#define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F2R1_FB2_Pos       (2U)                                            
-#define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F2R1_FB3_Pos       (3U)                                            
-#define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F2R1_FB4_Pos       (4U)                                            
-#define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F2R1_FB5_Pos       (5U)                                            
-#define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F2R1_FB6_Pos       (6U)                                            
-#define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F2R1_FB7_Pos       (7U)                                            
-#define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F2R1_FB8_Pos       (8U)                                            
-#define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F2R1_FB9_Pos       (9U)                                            
-#define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F2R1_FB10_Pos      (10U)                                           
-#define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F2R1_FB11_Pos      (11U)                                           
-#define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F2R1_FB12_Pos      (12U)                                           
-#define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F2R1_FB13_Pos      (13U)                                           
-#define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F2R1_FB14_Pos      (14U)                                           
-#define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F2R1_FB15_Pos      (15U)                                           
-#define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F2R1_FB16_Pos      (16U)                                           
-#define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F2R1_FB17_Pos      (17U)                                           
-#define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F2R1_FB18_Pos      (18U)                                           
-#define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F2R1_FB19_Pos      (19U)                                           
-#define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F2R1_FB20_Pos      (20U)                                           
-#define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F2R1_FB21_Pos      (21U)                                           
-#define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F2R1_FB22_Pos      (22U)                                           
-#define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F2R1_FB23_Pos      (23U)                                           
-#define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F2R1_FB24_Pos      (24U)                                           
-#define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F2R1_FB25_Pos      (25U)                                           
-#define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F2R1_FB26_Pos      (26U)                                           
-#define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F2R1_FB27_Pos      (27U)                                           
-#define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F2R1_FB28_Pos      (28U)                                           
-#define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F2R1_FB29_Pos      (29U)                                           
-#define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F2R1_FB30_Pos      (30U)                                           
-#define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F2R1_FB31_Pos      (31U)                                           
-#define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R1 register  *******************/
-#define CAN_F3R1_FB0_Pos       (0U)                                            
-#define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F3R1_FB1_Pos       (1U)                                            
-#define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F3R1_FB2_Pos       (2U)                                            
-#define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F3R1_FB3_Pos       (3U)                                            
-#define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F3R1_FB4_Pos       (4U)                                            
-#define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F3R1_FB5_Pos       (5U)                                            
-#define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F3R1_FB6_Pos       (6U)                                            
-#define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F3R1_FB7_Pos       (7U)                                            
-#define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F3R1_FB8_Pos       (8U)                                            
-#define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F3R1_FB9_Pos       (9U)                                            
-#define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F3R1_FB10_Pos      (10U)                                           
-#define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F3R1_FB11_Pos      (11U)                                           
-#define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F3R1_FB12_Pos      (12U)                                           
-#define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F3R1_FB13_Pos      (13U)                                           
-#define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F3R1_FB14_Pos      (14U)                                           
-#define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F3R1_FB15_Pos      (15U)                                           
-#define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F3R1_FB16_Pos      (16U)                                           
-#define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F3R1_FB17_Pos      (17U)                                           
-#define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F3R1_FB18_Pos      (18U)                                           
-#define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F3R1_FB19_Pos      (19U)                                           
-#define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F3R1_FB20_Pos      (20U)                                           
-#define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F3R1_FB21_Pos      (21U)                                           
-#define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F3R1_FB22_Pos      (22U)                                           
-#define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F3R1_FB23_Pos      (23U)                                           
-#define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F3R1_FB24_Pos      (24U)                                           
-#define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F3R1_FB25_Pos      (25U)                                           
-#define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F3R1_FB26_Pos      (26U)                                           
-#define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F3R1_FB27_Pos      (27U)                                           
-#define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F3R1_FB28_Pos      (28U)                                           
-#define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F3R1_FB29_Pos      (29U)                                           
-#define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F3R1_FB30_Pos      (30U)                                           
-#define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F3R1_FB31_Pos      (31U)                                           
-#define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R1 register  *******************/
-#define CAN_F4R1_FB0_Pos       (0U)                                            
-#define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F4R1_FB1_Pos       (1U)                                            
-#define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F4R1_FB2_Pos       (2U)                                            
-#define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F4R1_FB3_Pos       (3U)                                            
-#define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F4R1_FB4_Pos       (4U)                                            
-#define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F4R1_FB5_Pos       (5U)                                            
-#define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F4R1_FB6_Pos       (6U)                                            
-#define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F4R1_FB7_Pos       (7U)                                            
-#define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F4R1_FB8_Pos       (8U)                                            
-#define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F4R1_FB9_Pos       (9U)                                            
-#define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F4R1_FB10_Pos      (10U)                                           
-#define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F4R1_FB11_Pos      (11U)                                           
-#define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F4R1_FB12_Pos      (12U)                                           
-#define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F4R1_FB13_Pos      (13U)                                           
-#define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F4R1_FB14_Pos      (14U)                                           
-#define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F4R1_FB15_Pos      (15U)                                           
-#define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F4R1_FB16_Pos      (16U)                                           
-#define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F4R1_FB17_Pos      (17U)                                           
-#define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F4R1_FB18_Pos      (18U)                                           
-#define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F4R1_FB19_Pos      (19U)                                           
-#define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F4R1_FB20_Pos      (20U)                                           
-#define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F4R1_FB21_Pos      (21U)                                           
-#define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F4R1_FB22_Pos      (22U)                                           
-#define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F4R1_FB23_Pos      (23U)                                           
-#define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F4R1_FB24_Pos      (24U)                                           
-#define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F4R1_FB25_Pos      (25U)                                           
-#define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F4R1_FB26_Pos      (26U)                                           
-#define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F4R1_FB27_Pos      (27U)                                           
-#define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F4R1_FB28_Pos      (28U)                                           
-#define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F4R1_FB29_Pos      (29U)                                           
-#define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F4R1_FB30_Pos      (30U)                                           
-#define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F4R1_FB31_Pos      (31U)                                           
-#define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R1 register  *******************/
-#define CAN_F5R1_FB0_Pos       (0U)                                            
-#define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F5R1_FB1_Pos       (1U)                                            
-#define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F5R1_FB2_Pos       (2U)                                            
-#define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F5R1_FB3_Pos       (3U)                                            
-#define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F5R1_FB4_Pos       (4U)                                            
-#define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F5R1_FB5_Pos       (5U)                                            
-#define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F5R1_FB6_Pos       (6U)                                            
-#define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F5R1_FB7_Pos       (7U)                                            
-#define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F5R1_FB8_Pos       (8U)                                            
-#define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F5R1_FB9_Pos       (9U)                                            
-#define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F5R1_FB10_Pos      (10U)                                           
-#define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F5R1_FB11_Pos      (11U)                                           
-#define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F5R1_FB12_Pos      (12U)                                           
-#define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F5R1_FB13_Pos      (13U)                                           
-#define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F5R1_FB14_Pos      (14U)                                           
-#define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F5R1_FB15_Pos      (15U)                                           
-#define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F5R1_FB16_Pos      (16U)                                           
-#define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F5R1_FB17_Pos      (17U)                                           
-#define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F5R1_FB18_Pos      (18U)                                           
-#define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F5R1_FB19_Pos      (19U)                                           
-#define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F5R1_FB20_Pos      (20U)                                           
-#define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F5R1_FB21_Pos      (21U)                                           
-#define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F5R1_FB22_Pos      (22U)                                           
-#define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F5R1_FB23_Pos      (23U)                                           
-#define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F5R1_FB24_Pos      (24U)                                           
-#define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F5R1_FB25_Pos      (25U)                                           
-#define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F5R1_FB26_Pos      (26U)                                           
-#define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F5R1_FB27_Pos      (27U)                                           
-#define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F5R1_FB28_Pos      (28U)                                           
-#define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F5R1_FB29_Pos      (29U)                                           
-#define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F5R1_FB30_Pos      (30U)                                           
-#define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F5R1_FB31_Pos      (31U)                                           
-#define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R1 register  *******************/
-#define CAN_F6R1_FB0_Pos       (0U)                                            
-#define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F6R1_FB1_Pos       (1U)                                            
-#define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F6R1_FB2_Pos       (2U)                                            
-#define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F6R1_FB3_Pos       (3U)                                            
-#define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F6R1_FB4_Pos       (4U)                                            
-#define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F6R1_FB5_Pos       (5U)                                            
-#define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F6R1_FB6_Pos       (6U)                                            
-#define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F6R1_FB7_Pos       (7U)                                            
-#define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F6R1_FB8_Pos       (8U)                                            
-#define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F6R1_FB9_Pos       (9U)                                            
-#define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F6R1_FB10_Pos      (10U)                                           
-#define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F6R1_FB11_Pos      (11U)                                           
-#define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F6R1_FB12_Pos      (12U)                                           
-#define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F6R1_FB13_Pos      (13U)                                           
-#define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F6R1_FB14_Pos      (14U)                                           
-#define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F6R1_FB15_Pos      (15U)                                           
-#define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F6R1_FB16_Pos      (16U)                                           
-#define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F6R1_FB17_Pos      (17U)                                           
-#define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F6R1_FB18_Pos      (18U)                                           
-#define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F6R1_FB19_Pos      (19U)                                           
-#define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F6R1_FB20_Pos      (20U)                                           
-#define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F6R1_FB21_Pos      (21U)                                           
-#define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F6R1_FB22_Pos      (22U)                                           
-#define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F6R1_FB23_Pos      (23U)                                           
-#define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F6R1_FB24_Pos      (24U)                                           
-#define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F6R1_FB25_Pos      (25U)                                           
-#define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F6R1_FB26_Pos      (26U)                                           
-#define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F6R1_FB27_Pos      (27U)                                           
-#define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F6R1_FB28_Pos      (28U)                                           
-#define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F6R1_FB29_Pos      (29U)                                           
-#define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F6R1_FB30_Pos      (30U)                                           
-#define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F6R1_FB31_Pos      (31U)                                           
-#define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R1 register  *******************/
-#define CAN_F7R1_FB0_Pos       (0U)                                            
-#define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F7R1_FB1_Pos       (1U)                                            
-#define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F7R1_FB2_Pos       (2U)                                            
-#define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F7R1_FB3_Pos       (3U)                                            
-#define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F7R1_FB4_Pos       (4U)                                            
-#define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F7R1_FB5_Pos       (5U)                                            
-#define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F7R1_FB6_Pos       (6U)                                            
-#define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F7R1_FB7_Pos       (7U)                                            
-#define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F7R1_FB8_Pos       (8U)                                            
-#define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F7R1_FB9_Pos       (9U)                                            
-#define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F7R1_FB10_Pos      (10U)                                           
-#define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F7R1_FB11_Pos      (11U)                                           
-#define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F7R1_FB12_Pos      (12U)                                           
-#define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F7R1_FB13_Pos      (13U)                                           
-#define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F7R1_FB14_Pos      (14U)                                           
-#define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F7R1_FB15_Pos      (15U)                                           
-#define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F7R1_FB16_Pos      (16U)                                           
-#define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F7R1_FB17_Pos      (17U)                                           
-#define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F7R1_FB18_Pos      (18U)                                           
-#define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F7R1_FB19_Pos      (19U)                                           
-#define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F7R1_FB20_Pos      (20U)                                           
-#define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F7R1_FB21_Pos      (21U)                                           
-#define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F7R1_FB22_Pos      (22U)                                           
-#define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F7R1_FB23_Pos      (23U)                                           
-#define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F7R1_FB24_Pos      (24U)                                           
-#define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F7R1_FB25_Pos      (25U)                                           
-#define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F7R1_FB26_Pos      (26U)                                           
-#define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F7R1_FB27_Pos      (27U)                                           
-#define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F7R1_FB28_Pos      (28U)                                           
-#define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F7R1_FB29_Pos      (29U)                                           
-#define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F7R1_FB30_Pos      (30U)                                           
-#define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F7R1_FB31_Pos      (31U)                                           
-#define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R1 register  *******************/
-#define CAN_F8R1_FB0_Pos       (0U)                                            
-#define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F8R1_FB1_Pos       (1U)                                            
-#define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F8R1_FB2_Pos       (2U)                                            
-#define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F8R1_FB3_Pos       (3U)                                            
-#define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F8R1_FB4_Pos       (4U)                                            
-#define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F8R1_FB5_Pos       (5U)                                            
-#define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F8R1_FB6_Pos       (6U)                                            
-#define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F8R1_FB7_Pos       (7U)                                            
-#define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F8R1_FB8_Pos       (8U)                                            
-#define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F8R1_FB9_Pos       (9U)                                            
-#define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F8R1_FB10_Pos      (10U)                                           
-#define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F8R1_FB11_Pos      (11U)                                           
-#define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F8R1_FB12_Pos      (12U)                                           
-#define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F8R1_FB13_Pos      (13U)                                           
-#define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F8R1_FB14_Pos      (14U)                                           
-#define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F8R1_FB15_Pos      (15U)                                           
-#define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F8R1_FB16_Pos      (16U)                                           
-#define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F8R1_FB17_Pos      (17U)                                           
-#define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F8R1_FB18_Pos      (18U)                                           
-#define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F8R1_FB19_Pos      (19U)                                           
-#define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F8R1_FB20_Pos      (20U)                                           
-#define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F8R1_FB21_Pos      (21U)                                           
-#define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F8R1_FB22_Pos      (22U)                                           
-#define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F8R1_FB23_Pos      (23U)                                           
-#define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F8R1_FB24_Pos      (24U)                                           
-#define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F8R1_FB25_Pos      (25U)                                           
-#define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F8R1_FB26_Pos      (26U)                                           
-#define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F8R1_FB27_Pos      (27U)                                           
-#define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F8R1_FB28_Pos      (28U)                                           
-#define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F8R1_FB29_Pos      (29U)                                           
-#define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F8R1_FB30_Pos      (30U)                                           
-#define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F8R1_FB31_Pos      (31U)                                           
-#define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R1 register  *******************/
-#define CAN_F9R1_FB0_Pos       (0U)                                            
-#define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F9R1_FB1_Pos       (1U)                                            
-#define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F9R1_FB2_Pos       (2U)                                            
-#define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F9R1_FB3_Pos       (3U)                                            
-#define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F9R1_FB4_Pos       (4U)                                            
-#define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F9R1_FB5_Pos       (5U)                                            
-#define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F9R1_FB6_Pos       (6U)                                            
-#define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F9R1_FB7_Pos       (7U)                                            
-#define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F9R1_FB8_Pos       (8U)                                            
-#define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F9R1_FB9_Pos       (9U)                                            
-#define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F9R1_FB10_Pos      (10U)                                           
-#define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F9R1_FB11_Pos      (11U)                                           
-#define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F9R1_FB12_Pos      (12U)                                           
-#define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F9R1_FB13_Pos      (13U)                                           
-#define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F9R1_FB14_Pos      (14U)                                           
-#define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F9R1_FB15_Pos      (15U)                                           
-#define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F9R1_FB16_Pos      (16U)                                           
-#define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F9R1_FB17_Pos      (17U)                                           
-#define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F9R1_FB18_Pos      (18U)                                           
-#define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F9R1_FB19_Pos      (19U)                                           
-#define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F9R1_FB20_Pos      (20U)                                           
-#define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F9R1_FB21_Pos      (21U)                                           
-#define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F9R1_FB22_Pos      (22U)                                           
-#define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F9R1_FB23_Pos      (23U)                                           
-#define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F9R1_FB24_Pos      (24U)                                           
-#define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F9R1_FB25_Pos      (25U)                                           
-#define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F9R1_FB26_Pos      (26U)                                           
-#define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F9R1_FB27_Pos      (27U)                                           
-#define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F9R1_FB28_Pos      (28U)                                           
-#define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F9R1_FB29_Pos      (29U)                                           
-#define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F9R1_FB30_Pos      (30U)                                           
-#define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F9R1_FB31_Pos      (31U)                                           
-#define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R1 register  ******************/
-#define CAN_F10R1_FB0_Pos      (0U)                                            
-#define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
-#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
-#define CAN_F10R1_FB1_Pos      (1U)                                            
-#define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
-#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
-#define CAN_F10R1_FB2_Pos      (2U)                                            
-#define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
-#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
-#define CAN_F10R1_FB3_Pos      (3U)                                            
-#define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
-#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
-#define CAN_F10R1_FB4_Pos      (4U)                                            
-#define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
-#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
-#define CAN_F10R1_FB5_Pos      (5U)                                            
-#define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
-#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
-#define CAN_F10R1_FB6_Pos      (6U)                                            
-#define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
-#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
-#define CAN_F10R1_FB7_Pos      (7U)                                            
-#define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
-#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
-#define CAN_F10R1_FB8_Pos      (8U)                                            
-#define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
-#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
-#define CAN_F10R1_FB9_Pos      (9U)                                            
-#define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
-#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
-#define CAN_F10R1_FB10_Pos     (10U)                                           
-#define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
-#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
-#define CAN_F10R1_FB11_Pos     (11U)                                           
-#define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
-#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
-#define CAN_F10R1_FB12_Pos     (12U)                                           
-#define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
-#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
-#define CAN_F10R1_FB13_Pos     (13U)                                           
-#define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
-#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
-#define CAN_F10R1_FB14_Pos     (14U)                                           
-#define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
-#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
-#define CAN_F10R1_FB15_Pos     (15U)                                           
-#define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
-#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
-#define CAN_F10R1_FB16_Pos     (16U)                                           
-#define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
-#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
-#define CAN_F10R1_FB17_Pos     (17U)                                           
-#define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
-#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
-#define CAN_F10R1_FB18_Pos     (18U)                                           
-#define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
-#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
-#define CAN_F10R1_FB19_Pos     (19U)                                           
-#define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
-#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
-#define CAN_F10R1_FB20_Pos     (20U)                                           
-#define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
-#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
-#define CAN_F10R1_FB21_Pos     (21U)                                           
-#define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
-#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
-#define CAN_F10R1_FB22_Pos     (22U)                                           
-#define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
-#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
-#define CAN_F10R1_FB23_Pos     (23U)                                           
-#define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
-#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
-#define CAN_F10R1_FB24_Pos     (24U)                                           
-#define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
-#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
-#define CAN_F10R1_FB25_Pos     (25U)                                           
-#define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
-#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
-#define CAN_F10R1_FB26_Pos     (26U)                                           
-#define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
-#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
-#define CAN_F10R1_FB27_Pos     (27U)                                           
-#define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
-#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
-#define CAN_F10R1_FB28_Pos     (28U)                                           
-#define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
-#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
-#define CAN_F10R1_FB29_Pos     (29U)                                           
-#define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
-#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
-#define CAN_F10R1_FB30_Pos     (30U)                                           
-#define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
-#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
-#define CAN_F10R1_FB31_Pos     (31U)                                           
-#define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
-#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R1 register  ******************/
-#define CAN_F11R1_FB0_Pos      (0U)                                            
-#define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
-#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
-#define CAN_F11R1_FB1_Pos      (1U)                                            
-#define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
-#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
-#define CAN_F11R1_FB2_Pos      (2U)                                            
-#define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
-#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
-#define CAN_F11R1_FB3_Pos      (3U)                                            
-#define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
-#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
-#define CAN_F11R1_FB4_Pos      (4U)                                            
-#define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
-#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
-#define CAN_F11R1_FB5_Pos      (5U)                                            
-#define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
-#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
-#define CAN_F11R1_FB6_Pos      (6U)                                            
-#define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
-#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
-#define CAN_F11R1_FB7_Pos      (7U)                                            
-#define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
-#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
-#define CAN_F11R1_FB8_Pos      (8U)                                            
-#define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
-#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
-#define CAN_F11R1_FB9_Pos      (9U)                                            
-#define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
-#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
-#define CAN_F11R1_FB10_Pos     (10U)                                           
-#define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
-#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
-#define CAN_F11R1_FB11_Pos     (11U)                                           
-#define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
-#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
-#define CAN_F11R1_FB12_Pos     (12U)                                           
-#define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
-#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
-#define CAN_F11R1_FB13_Pos     (13U)                                           
-#define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
-#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
-#define CAN_F11R1_FB14_Pos     (14U)                                           
-#define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
-#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
-#define CAN_F11R1_FB15_Pos     (15U)                                           
-#define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
-#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
-#define CAN_F11R1_FB16_Pos     (16U)                                           
-#define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
-#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
-#define CAN_F11R1_FB17_Pos     (17U)                                           
-#define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
-#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
-#define CAN_F11R1_FB18_Pos     (18U)                                           
-#define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
-#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
-#define CAN_F11R1_FB19_Pos     (19U)                                           
-#define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
-#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
-#define CAN_F11R1_FB20_Pos     (20U)                                           
-#define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
-#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
-#define CAN_F11R1_FB21_Pos     (21U)                                           
-#define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
-#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
-#define CAN_F11R1_FB22_Pos     (22U)                                           
-#define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
-#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
-#define CAN_F11R1_FB23_Pos     (23U)                                           
-#define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
-#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
-#define CAN_F11R1_FB24_Pos     (24U)                                           
-#define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
-#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
-#define CAN_F11R1_FB25_Pos     (25U)                                           
-#define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
-#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
-#define CAN_F11R1_FB26_Pos     (26U)                                           
-#define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
-#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
-#define CAN_F11R1_FB27_Pos     (27U)                                           
-#define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
-#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
-#define CAN_F11R1_FB28_Pos     (28U)                                           
-#define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
-#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
-#define CAN_F11R1_FB29_Pos     (29U)                                           
-#define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
-#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
-#define CAN_F11R1_FB30_Pos     (30U)                                           
-#define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
-#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
-#define CAN_F11R1_FB31_Pos     (31U)                                           
-#define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
-#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R1 register  ******************/
-#define CAN_F12R1_FB0_Pos      (0U)                                            
-#define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
-#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
-#define CAN_F12R1_FB1_Pos      (1U)                                            
-#define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
-#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
-#define CAN_F12R1_FB2_Pos      (2U)                                            
-#define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
-#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
-#define CAN_F12R1_FB3_Pos      (3U)                                            
-#define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
-#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
-#define CAN_F12R1_FB4_Pos      (4U)                                            
-#define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
-#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
-#define CAN_F12R1_FB5_Pos      (5U)                                            
-#define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
-#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
-#define CAN_F12R1_FB6_Pos      (6U)                                            
-#define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
-#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
-#define CAN_F12R1_FB7_Pos      (7U)                                            
-#define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
-#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
-#define CAN_F12R1_FB8_Pos      (8U)                                            
-#define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
-#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
-#define CAN_F12R1_FB9_Pos      (9U)                                            
-#define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
-#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
-#define CAN_F12R1_FB10_Pos     (10U)                                           
-#define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
-#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
-#define CAN_F12R1_FB11_Pos     (11U)                                           
-#define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
-#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
-#define CAN_F12R1_FB12_Pos     (12U)                                           
-#define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
-#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
-#define CAN_F12R1_FB13_Pos     (13U)                                           
-#define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
-#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
-#define CAN_F12R1_FB14_Pos     (14U)                                           
-#define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
-#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
-#define CAN_F12R1_FB15_Pos     (15U)                                           
-#define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
-#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
-#define CAN_F12R1_FB16_Pos     (16U)                                           
-#define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
-#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
-#define CAN_F12R1_FB17_Pos     (17U)                                           
-#define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
-#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
-#define CAN_F12R1_FB18_Pos     (18U)                                           
-#define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
-#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
-#define CAN_F12R1_FB19_Pos     (19U)                                           
-#define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
-#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
-#define CAN_F12R1_FB20_Pos     (20U)                                           
-#define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
-#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
-#define CAN_F12R1_FB21_Pos     (21U)                                           
-#define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
-#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
-#define CAN_F12R1_FB22_Pos     (22U)                                           
-#define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
-#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
-#define CAN_F12R1_FB23_Pos     (23U)                                           
-#define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
-#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
-#define CAN_F12R1_FB24_Pos     (24U)                                           
-#define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
-#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
-#define CAN_F12R1_FB25_Pos     (25U)                                           
-#define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
-#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
-#define CAN_F12R1_FB26_Pos     (26U)                                           
-#define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
-#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
-#define CAN_F12R1_FB27_Pos     (27U)                                           
-#define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
-#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
-#define CAN_F12R1_FB28_Pos     (28U)                                           
-#define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
-#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
-#define CAN_F12R1_FB29_Pos     (29U)                                           
-#define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
-#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
-#define CAN_F12R1_FB30_Pos     (30U)                                           
-#define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
-#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
-#define CAN_F12R1_FB31_Pos     (31U)                                           
-#define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
-#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R1 register  ******************/
-#define CAN_F13R1_FB0_Pos      (0U)                                            
-#define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
-#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
-#define CAN_F13R1_FB1_Pos      (1U)                                            
-#define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
-#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
-#define CAN_F13R1_FB2_Pos      (2U)                                            
-#define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
-#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
-#define CAN_F13R1_FB3_Pos      (3U)                                            
-#define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
-#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
-#define CAN_F13R1_FB4_Pos      (4U)                                            
-#define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
-#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
-#define CAN_F13R1_FB5_Pos      (5U)                                            
-#define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
-#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
-#define CAN_F13R1_FB6_Pos      (6U)                                            
-#define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
-#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
-#define CAN_F13R1_FB7_Pos      (7U)                                            
-#define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
-#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
-#define CAN_F13R1_FB8_Pos      (8U)                                            
-#define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
-#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
-#define CAN_F13R1_FB9_Pos      (9U)                                            
-#define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
-#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
-#define CAN_F13R1_FB10_Pos     (10U)                                           
-#define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
-#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
-#define CAN_F13R1_FB11_Pos     (11U)                                           
-#define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
-#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
-#define CAN_F13R1_FB12_Pos     (12U)                                           
-#define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
-#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
-#define CAN_F13R1_FB13_Pos     (13U)                                           
-#define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
-#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
-#define CAN_F13R1_FB14_Pos     (14U)                                           
-#define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
-#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
-#define CAN_F13R1_FB15_Pos     (15U)                                           
-#define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
-#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
-#define CAN_F13R1_FB16_Pos     (16U)                                           
-#define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
-#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
-#define CAN_F13R1_FB17_Pos     (17U)                                           
-#define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
-#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
-#define CAN_F13R1_FB18_Pos     (18U)                                           
-#define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
-#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
-#define CAN_F13R1_FB19_Pos     (19U)                                           
-#define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
-#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
-#define CAN_F13R1_FB20_Pos     (20U)                                           
-#define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
-#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
-#define CAN_F13R1_FB21_Pos     (21U)                                           
-#define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
-#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
-#define CAN_F13R1_FB22_Pos     (22U)                                           
-#define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
-#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
-#define CAN_F13R1_FB23_Pos     (23U)                                           
-#define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
-#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
-#define CAN_F13R1_FB24_Pos     (24U)                                           
-#define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
-#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
-#define CAN_F13R1_FB25_Pos     (25U)                                           
-#define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
-#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
-#define CAN_F13R1_FB26_Pos     (26U)                                           
-#define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
-#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
-#define CAN_F13R1_FB27_Pos     (27U)                                           
-#define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
-#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
-#define CAN_F13R1_FB28_Pos     (28U)                                           
-#define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
-#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
-#define CAN_F13R1_FB29_Pos     (29U)                                           
-#define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
-#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
-#define CAN_F13R1_FB30_Pos     (30U)                                           
-#define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
-#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
-#define CAN_F13R1_FB31_Pos     (31U)                                           
-#define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
-#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F0R2 register  *******************/
-#define CAN_F0R2_FB0_Pos       (0U)                                            
-#define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F0R2_FB1_Pos       (1U)                                            
-#define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F0R2_FB2_Pos       (2U)                                            
-#define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F0R2_FB3_Pos       (3U)                                            
-#define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F0R2_FB4_Pos       (4U)                                            
-#define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F0R2_FB5_Pos       (5U)                                            
-#define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F0R2_FB6_Pos       (6U)                                            
-#define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F0R2_FB7_Pos       (7U)                                            
-#define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F0R2_FB8_Pos       (8U)                                            
-#define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F0R2_FB9_Pos       (9U)                                            
-#define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F0R2_FB10_Pos      (10U)                                           
-#define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F0R2_FB11_Pos      (11U)                                           
-#define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F0R2_FB12_Pos      (12U)                                           
-#define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F0R2_FB13_Pos      (13U)                                           
-#define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F0R2_FB14_Pos      (14U)                                           
-#define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F0R2_FB15_Pos      (15U)                                           
-#define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F0R2_FB16_Pos      (16U)                                           
-#define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F0R2_FB17_Pos      (17U)                                           
-#define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F0R2_FB18_Pos      (18U)                                           
-#define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F0R2_FB19_Pos      (19U)                                           
-#define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F0R2_FB20_Pos      (20U)                                           
-#define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F0R2_FB21_Pos      (21U)                                           
-#define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F0R2_FB22_Pos      (22U)                                           
-#define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F0R2_FB23_Pos      (23U)                                           
-#define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F0R2_FB24_Pos      (24U)                                           
-#define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F0R2_FB25_Pos      (25U)                                           
-#define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F0R2_FB26_Pos      (26U)                                           
-#define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F0R2_FB27_Pos      (27U)                                           
-#define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F0R2_FB28_Pos      (28U)                                           
-#define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F0R2_FB29_Pos      (29U)                                           
-#define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F0R2_FB30_Pos      (30U)                                           
-#define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F0R2_FB31_Pos      (31U)                                           
-#define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F1R2 register  *******************/
-#define CAN_F1R2_FB0_Pos       (0U)                                            
-#define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F1R2_FB1_Pos       (1U)                                            
-#define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F1R2_FB2_Pos       (2U)                                            
-#define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F1R2_FB3_Pos       (3U)                                            
-#define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F1R2_FB4_Pos       (4U)                                            
-#define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F1R2_FB5_Pos       (5U)                                            
-#define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F1R2_FB6_Pos       (6U)                                            
-#define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F1R2_FB7_Pos       (7U)                                            
-#define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F1R2_FB8_Pos       (8U)                                            
-#define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F1R2_FB9_Pos       (9U)                                            
-#define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F1R2_FB10_Pos      (10U)                                           
-#define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F1R2_FB11_Pos      (11U)                                           
-#define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F1R2_FB12_Pos      (12U)                                           
-#define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F1R2_FB13_Pos      (13U)                                           
-#define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F1R2_FB14_Pos      (14U)                                           
-#define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F1R2_FB15_Pos      (15U)                                           
-#define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F1R2_FB16_Pos      (16U)                                           
-#define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F1R2_FB17_Pos      (17U)                                           
-#define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F1R2_FB18_Pos      (18U)                                           
-#define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F1R2_FB19_Pos      (19U)                                           
-#define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F1R2_FB20_Pos      (20U)                                           
-#define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F1R2_FB21_Pos      (21U)                                           
-#define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F1R2_FB22_Pos      (22U)                                           
-#define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F1R2_FB23_Pos      (23U)                                           
-#define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F1R2_FB24_Pos      (24U)                                           
-#define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F1R2_FB25_Pos      (25U)                                           
-#define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F1R2_FB26_Pos      (26U)                                           
-#define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F1R2_FB27_Pos      (27U)                                           
-#define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F1R2_FB28_Pos      (28U)                                           
-#define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F1R2_FB29_Pos      (29U)                                           
-#define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F1R2_FB30_Pos      (30U)                                           
-#define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F1R2_FB31_Pos      (31U)                                           
-#define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F2R2 register  *******************/
-#define CAN_F2R2_FB0_Pos       (0U)                                            
-#define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F2R2_FB1_Pos       (1U)                                            
-#define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F2R2_FB2_Pos       (2U)                                            
-#define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F2R2_FB3_Pos       (3U)                                            
-#define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F2R2_FB4_Pos       (4U)                                            
-#define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F2R2_FB5_Pos       (5U)                                            
-#define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F2R2_FB6_Pos       (6U)                                            
-#define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F2R2_FB7_Pos       (7U)                                            
-#define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F2R2_FB8_Pos       (8U)                                            
-#define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F2R2_FB9_Pos       (9U)                                            
-#define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F2R2_FB10_Pos      (10U)                                           
-#define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F2R2_FB11_Pos      (11U)                                           
-#define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F2R2_FB12_Pos      (12U)                                           
-#define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F2R2_FB13_Pos      (13U)                                           
-#define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F2R2_FB14_Pos      (14U)                                           
-#define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F2R2_FB15_Pos      (15U)                                           
-#define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F2R2_FB16_Pos      (16U)                                           
-#define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F2R2_FB17_Pos      (17U)                                           
-#define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F2R2_FB18_Pos      (18U)                                           
-#define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F2R2_FB19_Pos      (19U)                                           
-#define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F2R2_FB20_Pos      (20U)                                           
-#define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F2R2_FB21_Pos      (21U)                                           
-#define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F2R2_FB22_Pos      (22U)                                           
-#define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F2R2_FB23_Pos      (23U)                                           
-#define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F2R2_FB24_Pos      (24U)                                           
-#define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F2R2_FB25_Pos      (25U)                                           
-#define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F2R2_FB26_Pos      (26U)                                           
-#define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F2R2_FB27_Pos      (27U)                                           
-#define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F2R2_FB28_Pos      (28U)                                           
-#define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F2R2_FB29_Pos      (29U)                                           
-#define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F2R2_FB30_Pos      (30U)                                           
-#define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F2R2_FB31_Pos      (31U)                                           
-#define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F3R2 register  *******************/
-#define CAN_F3R2_FB0_Pos       (0U)                                            
-#define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F3R2_FB1_Pos       (1U)                                            
-#define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F3R2_FB2_Pos       (2U)                                            
-#define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F3R2_FB3_Pos       (3U)                                            
-#define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F3R2_FB4_Pos       (4U)                                            
-#define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F3R2_FB5_Pos       (5U)                                            
-#define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F3R2_FB6_Pos       (6U)                                            
-#define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F3R2_FB7_Pos       (7U)                                            
-#define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F3R2_FB8_Pos       (8U)                                            
-#define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F3R2_FB9_Pos       (9U)                                            
-#define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F3R2_FB10_Pos      (10U)                                           
-#define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F3R2_FB11_Pos      (11U)                                           
-#define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F3R2_FB12_Pos      (12U)                                           
-#define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F3R2_FB13_Pos      (13U)                                           
-#define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F3R2_FB14_Pos      (14U)                                           
-#define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F3R2_FB15_Pos      (15U)                                           
-#define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F3R2_FB16_Pos      (16U)                                           
-#define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F3R2_FB17_Pos      (17U)                                           
-#define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F3R2_FB18_Pos      (18U)                                           
-#define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F3R2_FB19_Pos      (19U)                                           
-#define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F3R2_FB20_Pos      (20U)                                           
-#define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F3R2_FB21_Pos      (21U)                                           
-#define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F3R2_FB22_Pos      (22U)                                           
-#define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F3R2_FB23_Pos      (23U)                                           
-#define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F3R2_FB24_Pos      (24U)                                           
-#define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F3R2_FB25_Pos      (25U)                                           
-#define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F3R2_FB26_Pos      (26U)                                           
-#define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F3R2_FB27_Pos      (27U)                                           
-#define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F3R2_FB28_Pos      (28U)                                           
-#define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F3R2_FB29_Pos      (29U)                                           
-#define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F3R2_FB30_Pos      (30U)                                           
-#define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F3R2_FB31_Pos      (31U)                                           
-#define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F4R2 register  *******************/
-#define CAN_F4R2_FB0_Pos       (0U)                                            
-#define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F4R2_FB1_Pos       (1U)                                            
-#define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F4R2_FB2_Pos       (2U)                                            
-#define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F4R2_FB3_Pos       (3U)                                            
-#define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F4R2_FB4_Pos       (4U)                                            
-#define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F4R2_FB5_Pos       (5U)                                            
-#define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F4R2_FB6_Pos       (6U)                                            
-#define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F4R2_FB7_Pos       (7U)                                            
-#define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F4R2_FB8_Pos       (8U)                                            
-#define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F4R2_FB9_Pos       (9U)                                            
-#define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F4R2_FB10_Pos      (10U)                                           
-#define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F4R2_FB11_Pos      (11U)                                           
-#define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F4R2_FB12_Pos      (12U)                                           
-#define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F4R2_FB13_Pos      (13U)                                           
-#define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F4R2_FB14_Pos      (14U)                                           
-#define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F4R2_FB15_Pos      (15U)                                           
-#define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F4R2_FB16_Pos      (16U)                                           
-#define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F4R2_FB17_Pos      (17U)                                           
-#define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F4R2_FB18_Pos      (18U)                                           
-#define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F4R2_FB19_Pos      (19U)                                           
-#define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F4R2_FB20_Pos      (20U)                                           
-#define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F4R2_FB21_Pos      (21U)                                           
-#define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F4R2_FB22_Pos      (22U)                                           
-#define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F4R2_FB23_Pos      (23U)                                           
-#define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F4R2_FB24_Pos      (24U)                                           
-#define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F4R2_FB25_Pos      (25U)                                           
-#define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F4R2_FB26_Pos      (26U)                                           
-#define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F4R2_FB27_Pos      (27U)                                           
-#define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F4R2_FB28_Pos      (28U)                                           
-#define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F4R2_FB29_Pos      (29U)                                           
-#define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F4R2_FB30_Pos      (30U)                                           
-#define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F4R2_FB31_Pos      (31U)                                           
-#define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F5R2 register  *******************/
-#define CAN_F5R2_FB0_Pos       (0U)                                            
-#define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F5R2_FB1_Pos       (1U)                                            
-#define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F5R2_FB2_Pos       (2U)                                            
-#define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F5R2_FB3_Pos       (3U)                                            
-#define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F5R2_FB4_Pos       (4U)                                            
-#define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F5R2_FB5_Pos       (5U)                                            
-#define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F5R2_FB6_Pos       (6U)                                            
-#define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F5R2_FB7_Pos       (7U)                                            
-#define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F5R2_FB8_Pos       (8U)                                            
-#define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F5R2_FB9_Pos       (9U)                                            
-#define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F5R2_FB10_Pos      (10U)                                           
-#define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F5R2_FB11_Pos      (11U)                                           
-#define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F5R2_FB12_Pos      (12U)                                           
-#define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F5R2_FB13_Pos      (13U)                                           
-#define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F5R2_FB14_Pos      (14U)                                           
-#define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F5R2_FB15_Pos      (15U)                                           
-#define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F5R2_FB16_Pos      (16U)                                           
-#define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F5R2_FB17_Pos      (17U)                                           
-#define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F5R2_FB18_Pos      (18U)                                           
-#define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F5R2_FB19_Pos      (19U)                                           
-#define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F5R2_FB20_Pos      (20U)                                           
-#define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F5R2_FB21_Pos      (21U)                                           
-#define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F5R2_FB22_Pos      (22U)                                           
-#define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F5R2_FB23_Pos      (23U)                                           
-#define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F5R2_FB24_Pos      (24U)                                           
-#define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F5R2_FB25_Pos      (25U)                                           
-#define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F5R2_FB26_Pos      (26U)                                           
-#define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F5R2_FB27_Pos      (27U)                                           
-#define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F5R2_FB28_Pos      (28U)                                           
-#define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F5R2_FB29_Pos      (29U)                                           
-#define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F5R2_FB30_Pos      (30U)                                           
-#define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F5R2_FB31_Pos      (31U)                                           
-#define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F6R2 register  *******************/
-#define CAN_F6R2_FB0_Pos       (0U)                                            
-#define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F6R2_FB1_Pos       (1U)                                            
-#define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F6R2_FB2_Pos       (2U)                                            
-#define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F6R2_FB3_Pos       (3U)                                            
-#define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F6R2_FB4_Pos       (4U)                                            
-#define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F6R2_FB5_Pos       (5U)                                            
-#define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F6R2_FB6_Pos       (6U)                                            
-#define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F6R2_FB7_Pos       (7U)                                            
-#define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F6R2_FB8_Pos       (8U)                                            
-#define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F6R2_FB9_Pos       (9U)                                            
-#define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F6R2_FB10_Pos      (10U)                                           
-#define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F6R2_FB11_Pos      (11U)                                           
-#define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F6R2_FB12_Pos      (12U)                                           
-#define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F6R2_FB13_Pos      (13U)                                           
-#define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F6R2_FB14_Pos      (14U)                                           
-#define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F6R2_FB15_Pos      (15U)                                           
-#define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F6R2_FB16_Pos      (16U)                                           
-#define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F6R2_FB17_Pos      (17U)                                           
-#define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F6R2_FB18_Pos      (18U)                                           
-#define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F6R2_FB19_Pos      (19U)                                           
-#define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F6R2_FB20_Pos      (20U)                                           
-#define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F6R2_FB21_Pos      (21U)                                           
-#define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F6R2_FB22_Pos      (22U)                                           
-#define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F6R2_FB23_Pos      (23U)                                           
-#define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F6R2_FB24_Pos      (24U)                                           
-#define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F6R2_FB25_Pos      (25U)                                           
-#define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F6R2_FB26_Pos      (26U)                                           
-#define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F6R2_FB27_Pos      (27U)                                           
-#define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F6R2_FB28_Pos      (28U)                                           
-#define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F6R2_FB29_Pos      (29U)                                           
-#define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F6R2_FB30_Pos      (30U)                                           
-#define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F6R2_FB31_Pos      (31U)                                           
-#define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F7R2 register  *******************/
-#define CAN_F7R2_FB0_Pos       (0U)                                            
-#define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F7R2_FB1_Pos       (1U)                                            
-#define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F7R2_FB2_Pos       (2U)                                            
-#define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F7R2_FB3_Pos       (3U)                                            
-#define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F7R2_FB4_Pos       (4U)                                            
-#define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F7R2_FB5_Pos       (5U)                                            
-#define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F7R2_FB6_Pos       (6U)                                            
-#define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F7R2_FB7_Pos       (7U)                                            
-#define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F7R2_FB8_Pos       (8U)                                            
-#define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F7R2_FB9_Pos       (9U)                                            
-#define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F7R2_FB10_Pos      (10U)                                           
-#define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F7R2_FB11_Pos      (11U)                                           
-#define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F7R2_FB12_Pos      (12U)                                           
-#define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F7R2_FB13_Pos      (13U)                                           
-#define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F7R2_FB14_Pos      (14U)                                           
-#define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F7R2_FB15_Pos      (15U)                                           
-#define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F7R2_FB16_Pos      (16U)                                           
-#define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F7R2_FB17_Pos      (17U)                                           
-#define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F7R2_FB18_Pos      (18U)                                           
-#define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F7R2_FB19_Pos      (19U)                                           
-#define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F7R2_FB20_Pos      (20U)                                           
-#define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F7R2_FB21_Pos      (21U)                                           
-#define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F7R2_FB22_Pos      (22U)                                           
-#define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F7R2_FB23_Pos      (23U)                                           
-#define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F7R2_FB24_Pos      (24U)                                           
-#define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F7R2_FB25_Pos      (25U)                                           
-#define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F7R2_FB26_Pos      (26U)                                           
-#define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F7R2_FB27_Pos      (27U)                                           
-#define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F7R2_FB28_Pos      (28U)                                           
-#define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F7R2_FB29_Pos      (29U)                                           
-#define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F7R2_FB30_Pos      (30U)                                           
-#define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F7R2_FB31_Pos      (31U)                                           
-#define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F8R2 register  *******************/
-#define CAN_F8R2_FB0_Pos       (0U)                                            
-#define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F8R2_FB1_Pos       (1U)                                            
-#define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F8R2_FB2_Pos       (2U)                                            
-#define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F8R2_FB3_Pos       (3U)                                            
-#define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F8R2_FB4_Pos       (4U)                                            
-#define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F8R2_FB5_Pos       (5U)                                            
-#define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F8R2_FB6_Pos       (6U)                                            
-#define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F8R2_FB7_Pos       (7U)                                            
-#define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F8R2_FB8_Pos       (8U)                                            
-#define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F8R2_FB9_Pos       (9U)                                            
-#define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F8R2_FB10_Pos      (10U)                                           
-#define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F8R2_FB11_Pos      (11U)                                           
-#define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F8R2_FB12_Pos      (12U)                                           
-#define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F8R2_FB13_Pos      (13U)                                           
-#define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F8R2_FB14_Pos      (14U)                                           
-#define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F8R2_FB15_Pos      (15U)                                           
-#define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F8R2_FB16_Pos      (16U)                                           
-#define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F8R2_FB17_Pos      (17U)                                           
-#define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F8R2_FB18_Pos      (18U)                                           
-#define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F8R2_FB19_Pos      (19U)                                           
-#define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F8R2_FB20_Pos      (20U)                                           
-#define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F8R2_FB21_Pos      (21U)                                           
-#define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F8R2_FB22_Pos      (22U)                                           
-#define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F8R2_FB23_Pos      (23U)                                           
-#define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F8R2_FB24_Pos      (24U)                                           
-#define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F8R2_FB25_Pos      (25U)                                           
-#define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F8R2_FB26_Pos      (26U)                                           
-#define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F8R2_FB27_Pos      (27U)                                           
-#define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F8R2_FB28_Pos      (28U)                                           
-#define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F8R2_FB29_Pos      (29U)                                           
-#define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F8R2_FB30_Pos      (30U)                                           
-#define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F8R2_FB31_Pos      (31U)                                           
-#define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F9R2 register  *******************/
-#define CAN_F9R2_FB0_Pos       (0U)                                            
-#define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
-#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
-#define CAN_F9R2_FB1_Pos       (1U)                                            
-#define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
-#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
-#define CAN_F9R2_FB2_Pos       (2U)                                            
-#define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
-#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
-#define CAN_F9R2_FB3_Pos       (3U)                                            
-#define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
-#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
-#define CAN_F9R2_FB4_Pos       (4U)                                            
-#define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
-#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
-#define CAN_F9R2_FB5_Pos       (5U)                                            
-#define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
-#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
-#define CAN_F9R2_FB6_Pos       (6U)                                            
-#define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
-#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
-#define CAN_F9R2_FB7_Pos       (7U)                                            
-#define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
-#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
-#define CAN_F9R2_FB8_Pos       (8U)                                            
-#define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
-#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
-#define CAN_F9R2_FB9_Pos       (9U)                                            
-#define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
-#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
-#define CAN_F9R2_FB10_Pos      (10U)                                           
-#define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
-#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
-#define CAN_F9R2_FB11_Pos      (11U)                                           
-#define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
-#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
-#define CAN_F9R2_FB12_Pos      (12U)                                           
-#define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
-#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
-#define CAN_F9R2_FB13_Pos      (13U)                                           
-#define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
-#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
-#define CAN_F9R2_FB14_Pos      (14U)                                           
-#define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
-#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
-#define CAN_F9R2_FB15_Pos      (15U)                                           
-#define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
-#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
-#define CAN_F9R2_FB16_Pos      (16U)                                           
-#define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
-#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
-#define CAN_F9R2_FB17_Pos      (17U)                                           
-#define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
-#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
-#define CAN_F9R2_FB18_Pos      (18U)                                           
-#define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
-#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
-#define CAN_F9R2_FB19_Pos      (19U)                                           
-#define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
-#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
-#define CAN_F9R2_FB20_Pos      (20U)                                           
-#define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
-#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
-#define CAN_F9R2_FB21_Pos      (21U)                                           
-#define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
-#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
-#define CAN_F9R2_FB22_Pos      (22U)                                           
-#define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
-#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
-#define CAN_F9R2_FB23_Pos      (23U)                                           
-#define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
-#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
-#define CAN_F9R2_FB24_Pos      (24U)                                           
-#define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
-#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
-#define CAN_F9R2_FB25_Pos      (25U)                                           
-#define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
-#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
-#define CAN_F9R2_FB26_Pos      (26U)                                           
-#define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
-#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
-#define CAN_F9R2_FB27_Pos      (27U)                                           
-#define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
-#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
-#define CAN_F9R2_FB28_Pos      (28U)                                           
-#define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
-#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
-#define CAN_F9R2_FB29_Pos      (29U)                                           
-#define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
-#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
-#define CAN_F9R2_FB30_Pos      (30U)                                           
-#define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
-#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
-#define CAN_F9R2_FB31_Pos      (31U)                                           
-#define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
-#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F10R2 register  ******************/
-#define CAN_F10R2_FB0_Pos      (0U)                                            
-#define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
-#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
-#define CAN_F10R2_FB1_Pos      (1U)                                            
-#define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
-#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
-#define CAN_F10R2_FB2_Pos      (2U)                                            
-#define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
-#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
-#define CAN_F10R2_FB3_Pos      (3U)                                            
-#define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
-#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
-#define CAN_F10R2_FB4_Pos      (4U)                                            
-#define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
-#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
-#define CAN_F10R2_FB5_Pos      (5U)                                            
-#define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
-#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
-#define CAN_F10R2_FB6_Pos      (6U)                                            
-#define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
-#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
-#define CAN_F10R2_FB7_Pos      (7U)                                            
-#define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
-#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
-#define CAN_F10R2_FB8_Pos      (8U)                                            
-#define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
-#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
-#define CAN_F10R2_FB9_Pos      (9U)                                            
-#define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
-#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
-#define CAN_F10R2_FB10_Pos     (10U)                                           
-#define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
-#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
-#define CAN_F10R2_FB11_Pos     (11U)                                           
-#define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
-#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
-#define CAN_F10R2_FB12_Pos     (12U)                                           
-#define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
-#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
-#define CAN_F10R2_FB13_Pos     (13U)                                           
-#define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
-#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
-#define CAN_F10R2_FB14_Pos     (14U)                                           
-#define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
-#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
-#define CAN_F10R2_FB15_Pos     (15U)                                           
-#define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
-#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
-#define CAN_F10R2_FB16_Pos     (16U)                                           
-#define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
-#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
-#define CAN_F10R2_FB17_Pos     (17U)                                           
-#define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
-#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
-#define CAN_F10R2_FB18_Pos     (18U)                                           
-#define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
-#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
-#define CAN_F10R2_FB19_Pos     (19U)                                           
-#define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
-#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
-#define CAN_F10R2_FB20_Pos     (20U)                                           
-#define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
-#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
-#define CAN_F10R2_FB21_Pos     (21U)                                           
-#define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
-#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
-#define CAN_F10R2_FB22_Pos     (22U)                                           
-#define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
-#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
-#define CAN_F10R2_FB23_Pos     (23U)                                           
-#define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
-#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
-#define CAN_F10R2_FB24_Pos     (24U)                                           
-#define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
-#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
-#define CAN_F10R2_FB25_Pos     (25U)                                           
-#define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
-#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
-#define CAN_F10R2_FB26_Pos     (26U)                                           
-#define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
-#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
-#define CAN_F10R2_FB27_Pos     (27U)                                           
-#define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
-#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
-#define CAN_F10R2_FB28_Pos     (28U)                                           
-#define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
-#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
-#define CAN_F10R2_FB29_Pos     (29U)                                           
-#define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
-#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
-#define CAN_F10R2_FB30_Pos     (30U)                                           
-#define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
-#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
-#define CAN_F10R2_FB31_Pos     (31U)                                           
-#define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
-#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F11R2 register  ******************/
-#define CAN_F11R2_FB0_Pos      (0U)                                            
-#define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
-#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
-#define CAN_F11R2_FB1_Pos      (1U)                                            
-#define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
-#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
-#define CAN_F11R2_FB2_Pos      (2U)                                            
-#define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
-#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
-#define CAN_F11R2_FB3_Pos      (3U)                                            
-#define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
-#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
-#define CAN_F11R2_FB4_Pos      (4U)                                            
-#define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
-#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
-#define CAN_F11R2_FB5_Pos      (5U)                                            
-#define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
-#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
-#define CAN_F11R2_FB6_Pos      (6U)                                            
-#define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
-#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
-#define CAN_F11R2_FB7_Pos      (7U)                                            
-#define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
-#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
-#define CAN_F11R2_FB8_Pos      (8U)                                            
-#define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
-#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
-#define CAN_F11R2_FB9_Pos      (9U)                                            
-#define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
-#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
-#define CAN_F11R2_FB10_Pos     (10U)                                           
-#define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
-#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
-#define CAN_F11R2_FB11_Pos     (11U)                                           
-#define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
-#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
-#define CAN_F11R2_FB12_Pos     (12U)                                           
-#define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
-#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
-#define CAN_F11R2_FB13_Pos     (13U)                                           
-#define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
-#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
-#define CAN_F11R2_FB14_Pos     (14U)                                           
-#define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
-#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
-#define CAN_F11R2_FB15_Pos     (15U)                                           
-#define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
-#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
-#define CAN_F11R2_FB16_Pos     (16U)                                           
-#define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
-#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
-#define CAN_F11R2_FB17_Pos     (17U)                                           
-#define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
-#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
-#define CAN_F11R2_FB18_Pos     (18U)                                           
-#define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
-#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
-#define CAN_F11R2_FB19_Pos     (19U)                                           
-#define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
-#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
-#define CAN_F11R2_FB20_Pos     (20U)                                           
-#define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
-#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
-#define CAN_F11R2_FB21_Pos     (21U)                                           
-#define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
-#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
-#define CAN_F11R2_FB22_Pos     (22U)                                           
-#define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
-#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
-#define CAN_F11R2_FB23_Pos     (23U)                                           
-#define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
-#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
-#define CAN_F11R2_FB24_Pos     (24U)                                           
-#define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
-#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
-#define CAN_F11R2_FB25_Pos     (25U)                                           
-#define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
-#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
-#define CAN_F11R2_FB26_Pos     (26U)                                           
-#define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
-#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
-#define CAN_F11R2_FB27_Pos     (27U)                                           
-#define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
-#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
-#define CAN_F11R2_FB28_Pos     (28U)                                           
-#define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
-#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
-#define CAN_F11R2_FB29_Pos     (29U)                                           
-#define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
-#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
-#define CAN_F11R2_FB30_Pos     (30U)                                           
-#define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
-#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
-#define CAN_F11R2_FB31_Pos     (31U)                                           
-#define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
-#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F12R2 register  ******************/
-#define CAN_F12R2_FB0_Pos      (0U)                                            
-#define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
-#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
-#define CAN_F12R2_FB1_Pos      (1U)                                            
-#define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
-#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
-#define CAN_F12R2_FB2_Pos      (2U)                                            
-#define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
-#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
-#define CAN_F12R2_FB3_Pos      (3U)                                            
-#define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
-#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
-#define CAN_F12R2_FB4_Pos      (4U)                                            
-#define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
-#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
-#define CAN_F12R2_FB5_Pos      (5U)                                            
-#define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
-#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
-#define CAN_F12R2_FB6_Pos      (6U)                                            
-#define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
-#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
-#define CAN_F12R2_FB7_Pos      (7U)                                            
-#define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
-#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
-#define CAN_F12R2_FB8_Pos      (8U)                                            
-#define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
-#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
-#define CAN_F12R2_FB9_Pos      (9U)                                            
-#define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
-#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
-#define CAN_F12R2_FB10_Pos     (10U)                                           
-#define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
-#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
-#define CAN_F12R2_FB11_Pos     (11U)                                           
-#define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
-#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
-#define CAN_F12R2_FB12_Pos     (12U)                                           
-#define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
-#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
-#define CAN_F12R2_FB13_Pos     (13U)                                           
-#define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
-#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
-#define CAN_F12R2_FB14_Pos     (14U)                                           
-#define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
-#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
-#define CAN_F12R2_FB15_Pos     (15U)                                           
-#define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
-#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
-#define CAN_F12R2_FB16_Pos     (16U)                                           
-#define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
-#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
-#define CAN_F12R2_FB17_Pos     (17U)                                           
-#define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
-#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
-#define CAN_F12R2_FB18_Pos     (18U)                                           
-#define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
-#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
-#define CAN_F12R2_FB19_Pos     (19U)                                           
-#define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
-#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
-#define CAN_F12R2_FB20_Pos     (20U)                                           
-#define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
-#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
-#define CAN_F12R2_FB21_Pos     (21U)                                           
-#define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
-#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
-#define CAN_F12R2_FB22_Pos     (22U)                                           
-#define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
-#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
-#define CAN_F12R2_FB23_Pos     (23U)                                           
-#define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
-#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
-#define CAN_F12R2_FB24_Pos     (24U)                                           
-#define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
-#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
-#define CAN_F12R2_FB25_Pos     (25U)                                           
-#define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
-#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
-#define CAN_F12R2_FB26_Pos     (26U)                                           
-#define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
-#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
-#define CAN_F12R2_FB27_Pos     (27U)                                           
-#define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
-#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
-#define CAN_F12R2_FB28_Pos     (28U)                                           
-#define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
-#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
-#define CAN_F12R2_FB29_Pos     (29U)                                           
-#define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
-#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
-#define CAN_F12R2_FB30_Pos     (30U)                                           
-#define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
-#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
-#define CAN_F12R2_FB31_Pos     (31U)                                           
-#define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
-#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
-
-/*******************  Bit definition for CAN_F13R2 register  ******************/
-#define CAN_F13R2_FB0_Pos      (0U)                                            
-#define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
-#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
-#define CAN_F13R2_FB1_Pos      (1U)                                            
-#define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
-#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
-#define CAN_F13R2_FB2_Pos      (2U)                                            
-#define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
-#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
-#define CAN_F13R2_FB3_Pos      (3U)                                            
-#define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
-#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
-#define CAN_F13R2_FB4_Pos      (4U)                                            
-#define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
-#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
-#define CAN_F13R2_FB5_Pos      (5U)                                            
-#define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
-#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
-#define CAN_F13R2_FB6_Pos      (6U)                                            
-#define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
-#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
-#define CAN_F13R2_FB7_Pos      (7U)                                            
-#define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
-#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
-#define CAN_F13R2_FB8_Pos      (8U)                                            
-#define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
-#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
-#define CAN_F13R2_FB9_Pos      (9U)                                            
-#define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
-#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
-#define CAN_F13R2_FB10_Pos     (10U)                                           
-#define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
-#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
-#define CAN_F13R2_FB11_Pos     (11U)                                           
-#define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
-#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
-#define CAN_F13R2_FB12_Pos     (12U)                                           
-#define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
-#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
-#define CAN_F13R2_FB13_Pos     (13U)                                           
-#define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
-#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
-#define CAN_F13R2_FB14_Pos     (14U)                                           
-#define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
-#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
-#define CAN_F13R2_FB15_Pos     (15U)                                           
-#define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
-#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
-#define CAN_F13R2_FB16_Pos     (16U)                                           
-#define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
-#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
-#define CAN_F13R2_FB17_Pos     (17U)                                           
-#define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
-#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
-#define CAN_F13R2_FB18_Pos     (18U)                                           
-#define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
-#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
-#define CAN_F13R2_FB19_Pos     (19U)                                           
-#define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
-#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
-#define CAN_F13R2_FB20_Pos     (20U)                                           
-#define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
-#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
-#define CAN_F13R2_FB21_Pos     (21U)                                           
-#define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
-#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
-#define CAN_F13R2_FB22_Pos     (22U)                                           
-#define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
-#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
-#define CAN_F13R2_FB23_Pos     (23U)                                           
-#define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
-#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
-#define CAN_F13R2_FB24_Pos     (24U)                                           
-#define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
-#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
-#define CAN_F13R2_FB25_Pos     (25U)                                           
-#define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
-#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
-#define CAN_F13R2_FB26_Pos     (26U)                                           
-#define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
-#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
-#define CAN_F13R2_FB27_Pos     (27U)                                           
-#define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
-#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
-#define CAN_F13R2_FB28_Pos     (28U)                                           
-#define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
-#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
-#define CAN_F13R2_FB29_Pos     (29U)                                           
-#define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
-#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
-#define CAN_F13R2_FB30_Pos     (30U)                                           
-#define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
-#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
-#define CAN_F13R2_FB31_Pos     (31U)                                           
-#define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
-#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRC calculation unit                              */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR_Pos       (0U)                                               
-#define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */
-#define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */
-
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR_Pos     (0U)                                               
-#define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */
-#define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */
-
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET_Pos    (0U)                                               
-#define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */
-#define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Digital to Analog Converter                           */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
- */
-#define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1_Pos              (0U)                                       
-#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
-#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
-#define DAC_CR_BOFF1_Pos            (1U)                                       
-#define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
-#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */
-#define DAC_CR_TEN1_Pos             (2U)                                       
-#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
-#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1_Pos            (3U)                                       
-#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
-#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
-#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
-#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
-
-#define DAC_CR_WAVE1_Pos            (6U)                                       
-#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
-#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
-#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
-
-#define DAC_CR_MAMP1_Pos            (8U)                                       
-#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
-#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
-#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
-#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
-#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
-
-#define DAC_CR_DMAEN1_Pos           (12U)                                      
-#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
-#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      
-#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
-#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/
-#define DAC_CR_EN2_Pos              (16U)                                      
-#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
-#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
-#define DAC_CR_BOFF2_Pos            (17U)                                      
-#define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
-#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */
-#define DAC_CR_TEN2_Pos             (18U)                                      
-#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
-#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2_Pos            (19U)                                      
-#define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
-#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
-#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
-#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
-
-#define DAC_CR_WAVE2_Pos            (22U)                                      
-#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
-#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
-#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
-
-#define DAC_CR_MAMP2_Pos            (24U)                                      
-#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
-#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
-#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
-#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
-#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
-
-#define DAC_CR_DMAEN2_Pos           (28U)                                      
-#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
-#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2_Pos        (29U)                                      
-#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
-#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       
-#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
-#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)                                       
-#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
-#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       
-#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       
-#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       
-#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR_Pos    (0U)                                       
-#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR_Pos    (4U)                                       
-#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR_Pos     (0U)                                       
-#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR_Pos    (0U)                                       
-#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
-#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR_Pos    (16U)                                      
-#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
-#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR_Pos    (4U)                                       
-#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
-#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR_Pos    (20U)                                      
-#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
-#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR_Pos     (0U)                                       
-#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
-#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR_Pos     (8U)                                       
-#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
-#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR_Pos       (0U)                                       
-#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
-#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR_Pos       (0U)                                       
-#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
-#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1_Pos          (13U)                                      
-#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
-#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2_Pos          (29U)                                      
-#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
-#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    DCMI                                    */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DCMI_CR register  ******************/
-#define DCMI_CR_CAPTURE_Pos        (0U)                                        
-#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)               /*!< 0x00000001 */
-#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk                         
-#define DCMI_CR_CM_Pos             (1U)                                        
-#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                    /*!< 0x00000002 */
-#define DCMI_CR_CM                 DCMI_CR_CM_Msk                              
-#define DCMI_CR_CROP_Pos           (2U)                                        
-#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                  /*!< 0x00000004 */
-#define DCMI_CR_CROP               DCMI_CR_CROP_Msk                            
-#define DCMI_CR_JPEG_Pos           (3U)                                        
-#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                  /*!< 0x00000008 */
-#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk                            
-#define DCMI_CR_ESS_Pos            (4U)                                        
-#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                   /*!< 0x00000010 */
-#define DCMI_CR_ESS                DCMI_CR_ESS_Msk                             
-#define DCMI_CR_PCKPOL_Pos         (5U)                                        
-#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)                /*!< 0x00000020 */
-#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk                          
-#define DCMI_CR_HSPOL_Pos          (6U)                                        
-#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                 /*!< 0x00000040 */
-#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk                           
-#define DCMI_CR_VSPOL_Pos          (7U)                                        
-#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                 /*!< 0x00000080 */
-#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk                           
-#define DCMI_CR_FCRC_0             0x00000100U                                 
-#define DCMI_CR_FCRC_1             0x00000200U                                 
-#define DCMI_CR_EDM_0              0x00000400U                                 
-#define DCMI_CR_EDM_1              0x00000800U                                 
-#define DCMI_CR_CRE_Pos            (12U)                                       
-#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                   /*!< 0x00001000 */
-#define DCMI_CR_CRE                DCMI_CR_CRE_Msk                             
-#define DCMI_CR_ENABLE_Pos         (14U)                                       
-#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)                /*!< 0x00004000 */
-#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk                          
-
-/********************  Bits definition for DCMI_SR register  ******************/
-#define DCMI_SR_HSYNC_Pos          (0U)                                        
-#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                 /*!< 0x00000001 */
-#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk                           
-#define DCMI_SR_VSYNC_Pos          (1U)                                        
-#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                 /*!< 0x00000002 */
-#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk                           
-#define DCMI_SR_FNE_Pos            (2U)                                        
-#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                   /*!< 0x00000004 */
-#define DCMI_SR_FNE                DCMI_SR_FNE_Msk                             
-
-/********************  Bits definition for DCMI_RIS register  *****************/
-#define DCMI_RIS_FRAME_RIS_Pos     (0U)                                        
-#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)            /*!< 0x00000001 */
-#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk                      
-#define DCMI_RIS_OVR_RIS_Pos       (1U)                                        
-#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)              /*!< 0x00000002 */
-#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk                        
-#define DCMI_RIS_ERR_RIS_Pos       (2U)                                        
-#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)              /*!< 0x00000004 */
-#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk                        
-#define DCMI_RIS_VSYNC_RIS_Pos     (3U)                                        
-#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)            /*!< 0x00000008 */
-#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk                      
-#define DCMI_RIS_LINE_RIS_Pos      (4U)                                        
-#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)             /*!< 0x00000010 */
-#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk                       
-/* Legacy defines */
-#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
-#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
-#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
-#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
-#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
-#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
-
-/********************  Bits definition for DCMI_IER register  *****************/
-#define DCMI_IER_FRAME_IE_Pos      (0U)                                        
-#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)             /*!< 0x00000001 */
-#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk                       
-#define DCMI_IER_OVR_IE_Pos        (1U)                                        
-#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)               /*!< 0x00000002 */
-#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk                         
-#define DCMI_IER_ERR_IE_Pos        (2U)                                        
-#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)               /*!< 0x00000004 */
-#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk                         
-#define DCMI_IER_VSYNC_IE_Pos      (3U)                                        
-#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)             /*!< 0x00000008 */
-#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk                       
-#define DCMI_IER_LINE_IE_Pos       (4U)                                        
-#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)              /*!< 0x00000010 */
-#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk                        
-/* Legacy defines */
-#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
-
-/********************  Bits definition for DCMI_MIS register  *****************/
-#define DCMI_MIS_FRAME_MIS_Pos     (0U)                                        
-#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)            /*!< 0x00000001 */
-#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk                      
-#define DCMI_MIS_OVR_MIS_Pos       (1U)                                        
-#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)              /*!< 0x00000002 */
-#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk                        
-#define DCMI_MIS_ERR_MIS_Pos       (2U)                                        
-#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)              /*!< 0x00000004 */
-#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk                        
-#define DCMI_MIS_VSYNC_MIS_Pos     (3U)                                        
-#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)            /*!< 0x00000008 */
-#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk                      
-#define DCMI_MIS_LINE_MIS_Pos      (4U)                                        
-#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)             /*!< 0x00000010 */
-#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk                       
-
-/* Legacy defines */
-#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
-#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
-#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
-#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
-#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
-
-/********************  Bits definition for DCMI_ICR register  *****************/
-#define DCMI_ICR_FRAME_ISC_Pos     (0U)                                        
-#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)            /*!< 0x00000001 */
-#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk                      
-#define DCMI_ICR_OVR_ISC_Pos       (1U)                                        
-#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)              /*!< 0x00000002 */
-#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk                        
-#define DCMI_ICR_ERR_ISC_Pos       (2U)                                        
-#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)              /*!< 0x00000004 */
-#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk                        
-#define DCMI_ICR_VSYNC_ISC_Pos     (3U)                                        
-#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)            /*!< 0x00000008 */
-#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk                      
-#define DCMI_ICR_LINE_ISC_Pos      (4U)                                        
-#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)             /*!< 0x00000010 */
-#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk                       
-
-/* Legacy defines */
-#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
-
-/********************  Bits definition for DCMI_ESCR register  ******************/
-#define DCMI_ESCR_FSC_Pos          (0U)                                        
-#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)                /*!< 0x000000FF */
-#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk                           
-#define DCMI_ESCR_LSC_Pos          (8U)                                        
-#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)                /*!< 0x0000FF00 */
-#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk                           
-#define DCMI_ESCR_LEC_Pos          (16U)                                       
-#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)                /*!< 0x00FF0000 */
-#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk                           
-#define DCMI_ESCR_FEC_Pos          (24U)                                       
-#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)                /*!< 0xFF000000 */
-#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk                           
-
-/********************  Bits definition for DCMI_ESUR register  ******************/
-#define DCMI_ESUR_FSU_Pos          (0U)                                        
-#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)                /*!< 0x000000FF */
-#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk                           
-#define DCMI_ESUR_LSU_Pos          (8U)                                        
-#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)                /*!< 0x0000FF00 */
-#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk                           
-#define DCMI_ESUR_LEU_Pos          (16U)                                       
-#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)                /*!< 0x00FF0000 */
-#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk                           
-#define DCMI_ESUR_FEU_Pos          (24U)                                       
-#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)                /*!< 0xFF000000 */
-#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk                           
-
-/********************  Bits definition for DCMI_CWSTRT register  ******************/
-#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)                                        
-#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)        /*!< 0x00003FFF */
-#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk                     
-#define DCMI_CWSTRT_VST_Pos        (16U)                                       
-#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)            /*!< 0x1FFF0000 */
-#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk                         
-
-/********************  Bits definition for DCMI_CWSIZE register  ******************/
-#define DCMI_CWSIZE_CAPCNT_Pos     (0U)                                        
-#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)         /*!< 0x00003FFF */
-#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk                      
-#define DCMI_CWSIZE_VLINE_Pos      (16U)                                       
-#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)          /*!< 0x3FFF0000 */
-#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk                       
-
-/********************  Bits definition for DCMI_DR register  *********************/
-#define DCMI_DR_BYTE0_Pos          (0U)                                        
-#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)                /*!< 0x000000FF */
-#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk                           
-#define DCMI_DR_BYTE1_Pos          (8U)                                        
-#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)                /*!< 0x0000FF00 */
-#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk                           
-#define DCMI_DR_BYTE2_Pos          (16U)                                       
-#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)                /*!< 0x00FF0000 */
-#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk                           
-#define DCMI_DR_BYTE3_Pos          (24U)                                       
-#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)                /*!< 0xFF000000 */
-#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk                           
-
-/******************************************************************************/
-/*                                                                            */
-/*                             DMA Controller                                 */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for DMA_SxCR register  *****************/
-#define DMA_SxCR_CHSEL_Pos       (25U)                                         
-#define DMA_SxCR_CHSEL_Msk       (0x7UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */
-#define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk                            
-#define DMA_SxCR_CHSEL_0         0x02000000U                                   
-#define DMA_SxCR_CHSEL_1         0x04000000U                                   
-#define DMA_SxCR_CHSEL_2         0x08000000U                                   
-#define DMA_SxCR_MBURST_Pos      (23U)                                         
-#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */
-#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           
-#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
-#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
-#define DMA_SxCR_PBURST_Pos      (21U)                                         
-#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */
-#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           
-#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
-#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
-#define DMA_SxCR_CT_Pos          (19U)                                         
-#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */
-#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               
-#define DMA_SxCR_DBM_Pos         (18U)                                         
-#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */
-#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              
-#define DMA_SxCR_PL_Pos          (16U)                                         
-#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */
-#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               
-#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
-#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
-#define DMA_SxCR_PINCOS_Pos      (15U)                                         
-#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */
-#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           
-#define DMA_SxCR_MSIZE_Pos       (13U)                                         
-#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */
-#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            
-#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
-#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
-#define DMA_SxCR_PSIZE_Pos       (11U)                                         
-#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */
-#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            
-#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
-#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
-#define DMA_SxCR_MINC_Pos        (10U)                                         
-#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */
-#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             
-#define DMA_SxCR_PINC_Pos        (9U)                                          
-#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */
-#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             
-#define DMA_SxCR_CIRC_Pos        (8U)                                          
-#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */
-#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             
-#define DMA_SxCR_DIR_Pos         (6U)                                          
-#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */
-#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              
-#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
-#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
-#define DMA_SxCR_PFCTRL_Pos      (5U)                                          
-#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */
-#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           
-#define DMA_SxCR_TCIE_Pos        (4U)                                          
-#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */
-#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             
-#define DMA_SxCR_HTIE_Pos        (3U)                                          
-#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */
-#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             
-#define DMA_SxCR_TEIE_Pos        (2U)                                          
-#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */
-#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             
-#define DMA_SxCR_DMEIE_Pos       (1U)                                          
-#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */
-#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            
-#define DMA_SxCR_EN_Pos          (0U)                                          
-#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */
-#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               
-
-/* Legacy defines */
-#define DMA_SxCR_ACK_Pos         (20U)                                         
-#define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */
-#define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk                              
-
-/********************  Bits definition for DMA_SxCNDTR register  **************/
-#define DMA_SxNDT_Pos            (0U)                                          
-#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */
-#define DMA_SxNDT                DMA_SxNDT_Msk                                 
-#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
-#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
-#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
-#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
-#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
-#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
-#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
-#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
-#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
-#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
-#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
-#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
-#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
-#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
-#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
-#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
-
-/********************  Bits definition for DMA_SxFCR register  ****************/ 
-#define DMA_SxFCR_FEIE_Pos       (7U)                                          
-#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */
-#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            
-#define DMA_SxFCR_FS_Pos         (3U)                                          
-#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */
-#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              
-#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
-#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
-#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
-#define DMA_SxFCR_DMDIS_Pos      (2U)                                          
-#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */
-#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           
-#define DMA_SxFCR_FTH_Pos        (0U)                                          
-#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */
-#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             
-#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
-#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
-
-/********************  Bits definition for DMA_LISR register  *****************/ 
-#define DMA_LISR_TCIF3_Pos       (27U)                                         
-#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */
-#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            
-#define DMA_LISR_HTIF3_Pos       (26U)                                         
-#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */
-#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            
-#define DMA_LISR_TEIF3_Pos       (25U)                                         
-#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */
-#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            
-#define DMA_LISR_DMEIF3_Pos      (24U)                                         
-#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */
-#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           
-#define DMA_LISR_FEIF3_Pos       (22U)                                         
-#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */
-#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            
-#define DMA_LISR_TCIF2_Pos       (21U)                                         
-#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */
-#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            
-#define DMA_LISR_HTIF2_Pos       (20U)                                         
-#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */
-#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            
-#define DMA_LISR_TEIF2_Pos       (19U)                                         
-#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */
-#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            
-#define DMA_LISR_DMEIF2_Pos      (18U)                                         
-#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */
-#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           
-#define DMA_LISR_FEIF2_Pos       (16U)                                         
-#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */
-#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            
-#define DMA_LISR_TCIF1_Pos       (11U)                                         
-#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */
-#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            
-#define DMA_LISR_HTIF1_Pos       (10U)                                         
-#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */
-#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            
-#define DMA_LISR_TEIF1_Pos       (9U)                                          
-#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */
-#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            
-#define DMA_LISR_DMEIF1_Pos      (8U)                                          
-#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */
-#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           
-#define DMA_LISR_FEIF1_Pos       (6U)                                          
-#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */
-#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            
-#define DMA_LISR_TCIF0_Pos       (5U)                                          
-#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */
-#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            
-#define DMA_LISR_HTIF0_Pos       (4U)                                          
-#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */
-#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            
-#define DMA_LISR_TEIF0_Pos       (3U)                                          
-#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */
-#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            
-#define DMA_LISR_DMEIF0_Pos      (2U)                                          
-#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */
-#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           
-#define DMA_LISR_FEIF0_Pos       (0U)                                          
-#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */
-#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            
-
-/********************  Bits definition for DMA_HISR register  *****************/ 
-#define DMA_HISR_TCIF7_Pos       (27U)                                         
-#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */
-#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            
-#define DMA_HISR_HTIF7_Pos       (26U)                                         
-#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */
-#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            
-#define DMA_HISR_TEIF7_Pos       (25U)                                         
-#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */
-#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            
-#define DMA_HISR_DMEIF7_Pos      (24U)                                         
-#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */
-#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           
-#define DMA_HISR_FEIF7_Pos       (22U)                                         
-#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */
-#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            
-#define DMA_HISR_TCIF6_Pos       (21U)                                         
-#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */
-#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            
-#define DMA_HISR_HTIF6_Pos       (20U)                                         
-#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */
-#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            
-#define DMA_HISR_TEIF6_Pos       (19U)                                         
-#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */
-#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            
-#define DMA_HISR_DMEIF6_Pos      (18U)                                         
-#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */
-#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           
-#define DMA_HISR_FEIF6_Pos       (16U)                                         
-#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */
-#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            
-#define DMA_HISR_TCIF5_Pos       (11U)                                         
-#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */
-#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            
-#define DMA_HISR_HTIF5_Pos       (10U)                                         
-#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */
-#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            
-#define DMA_HISR_TEIF5_Pos       (9U)                                          
-#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */
-#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            
-#define DMA_HISR_DMEIF5_Pos      (8U)                                          
-#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */
-#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           
-#define DMA_HISR_FEIF5_Pos       (6U)                                          
-#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */
-#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            
-#define DMA_HISR_TCIF4_Pos       (5U)                                          
-#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */
-#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            
-#define DMA_HISR_HTIF4_Pos       (4U)                                          
-#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */
-#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            
-#define DMA_HISR_TEIF4_Pos       (3U)                                          
-#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */
-#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            
-#define DMA_HISR_DMEIF4_Pos      (2U)                                          
-#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */
-#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           
-#define DMA_HISR_FEIF4_Pos       (0U)                                          
-#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */
-#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            
-
-/********************  Bits definition for DMA_LIFCR register  ****************/ 
-#define DMA_LIFCR_CTCIF3_Pos     (27U)                                         
-#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */
-#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          
-#define DMA_LIFCR_CHTIF3_Pos     (26U)                                         
-#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */
-#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          
-#define DMA_LIFCR_CTEIF3_Pos     (25U)                                         
-#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */
-#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          
-#define DMA_LIFCR_CDMEIF3_Pos    (24U)                                         
-#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */
-#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         
-#define DMA_LIFCR_CFEIF3_Pos     (22U)                                         
-#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */
-#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          
-#define DMA_LIFCR_CTCIF2_Pos     (21U)                                         
-#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */
-#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          
-#define DMA_LIFCR_CHTIF2_Pos     (20U)                                         
-#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */
-#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          
-#define DMA_LIFCR_CTEIF2_Pos     (19U)                                         
-#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */
-#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          
-#define DMA_LIFCR_CDMEIF2_Pos    (18U)                                         
-#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */
-#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         
-#define DMA_LIFCR_CFEIF2_Pos     (16U)                                         
-#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */
-#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          
-#define DMA_LIFCR_CTCIF1_Pos     (11U)                                         
-#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */
-#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          
-#define DMA_LIFCR_CHTIF1_Pos     (10U)                                         
-#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */
-#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          
-#define DMA_LIFCR_CTEIF1_Pos     (9U)                                          
-#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */
-#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          
-#define DMA_LIFCR_CDMEIF1_Pos    (8U)                                          
-#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */
-#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         
-#define DMA_LIFCR_CFEIF1_Pos     (6U)                                          
-#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */
-#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          
-#define DMA_LIFCR_CTCIF0_Pos     (5U)                                          
-#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */
-#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          
-#define DMA_LIFCR_CHTIF0_Pos     (4U)                                          
-#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */
-#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          
-#define DMA_LIFCR_CTEIF0_Pos     (3U)                                          
-#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */
-#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          
-#define DMA_LIFCR_CDMEIF0_Pos    (2U)                                          
-#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */
-#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         
-#define DMA_LIFCR_CFEIF0_Pos     (0U)                                          
-#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */
-#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          
-
-/********************  Bits definition for DMA_HIFCR  register  ****************/ 
-#define DMA_HIFCR_CTCIF7_Pos     (27U)                                         
-#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */
-#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          
-#define DMA_HIFCR_CHTIF7_Pos     (26U)                                         
-#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */
-#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          
-#define DMA_HIFCR_CTEIF7_Pos     (25U)                                         
-#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */
-#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          
-#define DMA_HIFCR_CDMEIF7_Pos    (24U)                                         
-#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */
-#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         
-#define DMA_HIFCR_CFEIF7_Pos     (22U)                                         
-#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */
-#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          
-#define DMA_HIFCR_CTCIF6_Pos     (21U)                                         
-#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */
-#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          
-#define DMA_HIFCR_CHTIF6_Pos     (20U)                                         
-#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */
-#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          
-#define DMA_HIFCR_CTEIF6_Pos     (19U)                                         
-#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */
-#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          
-#define DMA_HIFCR_CDMEIF6_Pos    (18U)                                         
-#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */
-#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         
-#define DMA_HIFCR_CFEIF6_Pos     (16U)                                         
-#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */
-#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          
-#define DMA_HIFCR_CTCIF5_Pos     (11U)                                         
-#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */
-#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          
-#define DMA_HIFCR_CHTIF5_Pos     (10U)                                         
-#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */
-#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          
-#define DMA_HIFCR_CTEIF5_Pos     (9U)                                          
-#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */
-#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          
-#define DMA_HIFCR_CDMEIF5_Pos    (8U)                                          
-#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */
-#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         
-#define DMA_HIFCR_CFEIF5_Pos     (6U)                                          
-#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */
-#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          
-#define DMA_HIFCR_CTCIF4_Pos     (5U)                                          
-#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */
-#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          
-#define DMA_HIFCR_CHTIF4_Pos     (4U)                                          
-#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */
-#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          
-#define DMA_HIFCR_CTEIF4_Pos     (3U)                                          
-#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */
-#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          
-#define DMA_HIFCR_CDMEIF4_Pos    (2U)                                          
-#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */
-#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         
-#define DMA_HIFCR_CFEIF4_Pos     (0U)                                          
-#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */
-#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          
-
-/******************  Bit definition for DMA_SxPAR register  ********************/
-#define DMA_SxPAR_PA_Pos         (0U)                                          
-#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */
-#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_SxM0AR register  ********************/
-#define DMA_SxM0AR_M0A_Pos       (0U)                                          
-#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */
-#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */
-
-/******************  Bit definition for DMA_SxM1AR register  ********************/
-#define DMA_SxM1AR_M1A_Pos       (0U)                                          
-#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
-#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                    External Interrupt/Event Controller                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_MR0_Pos          (0U)                                         
-#define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */
-#define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1_Pos          (1U)                                         
-#define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */
-#define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2_Pos          (2U)                                         
-#define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */
-#define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3_Pos          (3U)                                         
-#define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */
-#define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4_Pos          (4U)                                         
-#define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */
-#define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5_Pos          (5U)                                         
-#define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */
-#define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6_Pos          (6U)                                         
-#define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */
-#define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7_Pos          (7U)                                         
-#define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */
-#define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8_Pos          (8U)                                         
-#define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */
-#define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9_Pos          (9U)                                         
-#define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */
-#define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10_Pos         (10U)                                        
-#define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */
-#define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11_Pos         (11U)                                        
-#define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */
-#define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12_Pos         (12U)                                        
-#define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */
-#define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13_Pos         (13U)                                        
-#define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */
-#define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14_Pos         (14U)                                        
-#define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */
-#define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15_Pos         (15U)                                        
-#define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */
-#define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16_Pos         (16U)                                        
-#define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */
-#define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17_Pos         (17U)                                        
-#define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */
-#define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18_Pos         (18U)                                        
-#define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */
-#define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19_Pos         (19U)                                        
-#define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */
-#define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20_Pos         (20U)                                        
-#define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */
-#define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21_Pos         (21U)                                        
-#define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */
-#define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22_Pos         (22U)                                        
-#define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */
-#define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */
-
-/* Reference Defines */
-#define  EXTI_IMR_IM0                        EXTI_IMR_MR0
-#define  EXTI_IMR_IM1                        EXTI_IMR_MR1
-#define  EXTI_IMR_IM2                        EXTI_IMR_MR2
-#define  EXTI_IMR_IM3                        EXTI_IMR_MR3
-#define  EXTI_IMR_IM4                        EXTI_IMR_MR4
-#define  EXTI_IMR_IM5                        EXTI_IMR_MR5
-#define  EXTI_IMR_IM6                        EXTI_IMR_MR6
-#define  EXTI_IMR_IM7                        EXTI_IMR_MR7
-#define  EXTI_IMR_IM8                        EXTI_IMR_MR8
-#define  EXTI_IMR_IM9                        EXTI_IMR_MR9
-#define  EXTI_IMR_IM10                       EXTI_IMR_MR10
-#define  EXTI_IMR_IM11                       EXTI_IMR_MR11
-#define  EXTI_IMR_IM12                       EXTI_IMR_MR12
-#define  EXTI_IMR_IM13                       EXTI_IMR_MR13
-#define  EXTI_IMR_IM14                       EXTI_IMR_MR14
-#define  EXTI_IMR_IM15                       EXTI_IMR_MR15
-#define  EXTI_IMR_IM16                       EXTI_IMR_MR16
-#define  EXTI_IMR_IM17                       EXTI_IMR_MR17
-#define  EXTI_IMR_IM18                       EXTI_IMR_MR18
-#define  EXTI_IMR_IM19                       EXTI_IMR_MR19
-#define  EXTI_IMR_IM20                       EXTI_IMR_MR20
-#define  EXTI_IMR_IM21                       EXTI_IMR_MR21
-#define  EXTI_IMR_IM22                       EXTI_IMR_MR22
-#define EXTI_IMR_IM_Pos           (0U)                                         
-#define EXTI_IMR_IM_Msk           (0x7FFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */
-#define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define EXTI_EMR_MR0_Pos          (0U)                                         
-#define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */
-#define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1_Pos          (1U)                                         
-#define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */
-#define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2_Pos          (2U)                                         
-#define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */
-#define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3_Pos          (3U)                                         
-#define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */
-#define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4_Pos          (4U)                                         
-#define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */
-#define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5_Pos          (5U)                                         
-#define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */
-#define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6_Pos          (6U)                                         
-#define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */
-#define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7_Pos          (7U)                                         
-#define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */
-#define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8_Pos          (8U)                                         
-#define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */
-#define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9_Pos          (9U)                                         
-#define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */
-#define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10_Pos         (10U)                                        
-#define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */
-#define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11_Pos         (11U)                                        
-#define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */
-#define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12_Pos         (12U)                                        
-#define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */
-#define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13_Pos         (13U)                                        
-#define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */
-#define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14_Pos         (14U)                                        
-#define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */
-#define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15_Pos         (15U)                                        
-#define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */
-#define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16_Pos         (16U)                                        
-#define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */
-#define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17_Pos         (17U)                                        
-#define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */
-#define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18_Pos         (18U)                                        
-#define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */
-#define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19_Pos         (19U)                                        
-#define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */
-#define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20_Pos         (20U)                                        
-#define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */
-#define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21_Pos         (21U)                                        
-#define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */
-#define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22_Pos         (22U)                                        
-#define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */
-#define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */
-
-/* Reference Defines */
-#define  EXTI_EMR_EM0                        EXTI_EMR_MR0
-#define  EXTI_EMR_EM1                        EXTI_EMR_MR1
-#define  EXTI_EMR_EM2                        EXTI_EMR_MR2
-#define  EXTI_EMR_EM3                        EXTI_EMR_MR3
-#define  EXTI_EMR_EM4                        EXTI_EMR_MR4
-#define  EXTI_EMR_EM5                        EXTI_EMR_MR5
-#define  EXTI_EMR_EM6                        EXTI_EMR_MR6
-#define  EXTI_EMR_EM7                        EXTI_EMR_MR7
-#define  EXTI_EMR_EM8                        EXTI_EMR_MR8
-#define  EXTI_EMR_EM9                        EXTI_EMR_MR9
-#define  EXTI_EMR_EM10                       EXTI_EMR_MR10
-#define  EXTI_EMR_EM11                       EXTI_EMR_MR11
-#define  EXTI_EMR_EM12                       EXTI_EMR_MR12
-#define  EXTI_EMR_EM13                       EXTI_EMR_MR13
-#define  EXTI_EMR_EM14                       EXTI_EMR_MR14
-#define  EXTI_EMR_EM15                       EXTI_EMR_MR15
-#define  EXTI_EMR_EM16                       EXTI_EMR_MR16
-#define  EXTI_EMR_EM17                       EXTI_EMR_MR17
-#define  EXTI_EMR_EM18                       EXTI_EMR_MR18
-#define  EXTI_EMR_EM19                       EXTI_EMR_MR19
-#define  EXTI_EMR_EM20                       EXTI_EMR_MR20
-#define  EXTI_EMR_EM21                       EXTI_EMR_MR21
-#define  EXTI_EMR_EM22                       EXTI_EMR_MR22
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define EXTI_RTSR_TR0_Pos         (0U)                                         
-#define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */
-#define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1_Pos         (1U)                                         
-#define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */
-#define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2_Pos         (2U)                                         
-#define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */
-#define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3_Pos         (3U)                                         
-#define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */
-#define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4_Pos         (4U)                                         
-#define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */
-#define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5_Pos         (5U)                                         
-#define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */
-#define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6_Pos         (6U)                                         
-#define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */
-#define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7_Pos         (7U)                                         
-#define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */
-#define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8_Pos         (8U)                                         
-#define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */
-#define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9_Pos         (9U)                                         
-#define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */
-#define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10_Pos        (10U)                                        
-#define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */
-#define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11_Pos        (11U)                                        
-#define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */
-#define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12_Pos        (12U)                                        
-#define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */
-#define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13_Pos        (13U)                                        
-#define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */
-#define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14_Pos        (14U)                                        
-#define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */
-#define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15_Pos        (15U)                                        
-#define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */
-#define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16_Pos        (16U)                                        
-#define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */
-#define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17_Pos        (17U)                                        
-#define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */
-#define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR18_Pos        (18U)                                        
-#define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */
-#define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
-#define EXTI_RTSR_TR19_Pos        (19U)                                        
-#define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */
-#define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20_Pos        (20U)                                        
-#define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */
-#define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21_Pos        (21U)                                        
-#define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */
-#define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22_Pos        (22U)                                        
-#define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */
-#define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define EXTI_FTSR_TR0_Pos         (0U)                                         
-#define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */
-#define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1_Pos         (1U)                                         
-#define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */
-#define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2_Pos         (2U)                                         
-#define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */
-#define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3_Pos         (3U)                                         
-#define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */
-#define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4_Pos         (4U)                                         
-#define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */
-#define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5_Pos         (5U)                                         
-#define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */
-#define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6_Pos         (6U)                                         
-#define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */
-#define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7_Pos         (7U)                                         
-#define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */
-#define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8_Pos         (8U)                                         
-#define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */
-#define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9_Pos         (9U)                                         
-#define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */
-#define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10_Pos        (10U)                                        
-#define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */
-#define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11_Pos        (11U)                                        
-#define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */
-#define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12_Pos        (12U)                                        
-#define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */
-#define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13_Pos        (13U)                                        
-#define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */
-#define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14_Pos        (14U)                                        
-#define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */
-#define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15_Pos        (15U)                                        
-#define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */
-#define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16_Pos        (16U)                                        
-#define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */
-#define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17_Pos        (17U)                                        
-#define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */
-#define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR18_Pos        (18U)                                        
-#define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */
-#define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
-#define EXTI_FTSR_TR19_Pos        (19U)                                        
-#define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */
-#define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20_Pos        (20U)                                        
-#define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */
-#define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21_Pos        (21U)                                        
-#define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */
-#define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22_Pos        (22U)                                        
-#define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */
-#define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define EXTI_SWIER_SWIER0_Pos     (0U)                                         
-#define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */
-#define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1_Pos     (1U)                                         
-#define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */
-#define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2_Pos     (2U)                                         
-#define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */
-#define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3_Pos     (3U)                                         
-#define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */
-#define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4_Pos     (4U)                                         
-#define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */
-#define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5_Pos     (5U)                                         
-#define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */
-#define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6_Pos     (6U)                                         
-#define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */
-#define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7_Pos     (7U)                                         
-#define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */
-#define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8_Pos     (8U)                                         
-#define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */
-#define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9_Pos     (9U)                                         
-#define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */
-#define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10_Pos    (10U)                                        
-#define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */
-#define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11_Pos    (11U)                                        
-#define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */
-#define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12_Pos    (12U)                                        
-#define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */
-#define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13_Pos    (13U)                                        
-#define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */
-#define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14_Pos    (14U)                                        
-#define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */
-#define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15_Pos    (15U)                                        
-#define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */
-#define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16_Pos    (16U)                                        
-#define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */
-#define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17_Pos    (17U)                                        
-#define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */
-#define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER18_Pos    (18U)                                        
-#define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */
-#define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */
-#define EXTI_SWIER_SWIER19_Pos    (19U)                                        
-#define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */
-#define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20_Pos    (20U)                                        
-#define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */
-#define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21_Pos    (21U)                                        
-#define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */
-#define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22_Pos    (22U)                                        
-#define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */
-#define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define EXTI_PR_PR0_Pos           (0U)                                         
-#define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */
-#define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */
-#define EXTI_PR_PR1_Pos           (1U)                                         
-#define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */
-#define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */
-#define EXTI_PR_PR2_Pos           (2U)                                         
-#define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */
-#define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */
-#define EXTI_PR_PR3_Pos           (3U)                                         
-#define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */
-#define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */
-#define EXTI_PR_PR4_Pos           (4U)                                         
-#define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */
-#define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */
-#define EXTI_PR_PR5_Pos           (5U)                                         
-#define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */
-#define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */
-#define EXTI_PR_PR6_Pos           (6U)                                         
-#define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */
-#define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */
-#define EXTI_PR_PR7_Pos           (7U)                                         
-#define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */
-#define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */
-#define EXTI_PR_PR8_Pos           (8U)                                         
-#define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */
-#define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */
-#define EXTI_PR_PR9_Pos           (9U)                                         
-#define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */
-#define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */
-#define EXTI_PR_PR10_Pos          (10U)                                        
-#define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */
-#define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */
-#define EXTI_PR_PR11_Pos          (11U)                                        
-#define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */
-#define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */
-#define EXTI_PR_PR12_Pos          (12U)                                        
-#define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */
-#define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */
-#define EXTI_PR_PR13_Pos          (13U)                                        
-#define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */
-#define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */
-#define EXTI_PR_PR14_Pos          (14U)                                        
-#define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */
-#define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */
-#define EXTI_PR_PR15_Pos          (15U)                                        
-#define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */
-#define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */
-#define EXTI_PR_PR16_Pos          (16U)                                        
-#define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */
-#define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */
-#define EXTI_PR_PR17_Pos          (17U)                                        
-#define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */
-#define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */
-#define EXTI_PR_PR18_Pos          (18U)                                        
-#define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */
-#define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */
-#define EXTI_PR_PR19_Pos          (19U)                                        
-#define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */
-#define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */
-#define EXTI_PR_PR20_Pos          (20U)                                        
-#define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */
-#define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */
-#define EXTI_PR_PR21_Pos          (21U)                                        
-#define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */
-#define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */
-#define EXTI_PR_PR22_Pos          (22U)                                        
-#define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */
-#define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    FLASH                                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bits definition for FLASH_ACR register  *****************/
-#define FLASH_ACR_LATENCY_Pos          (0U)
-#define FLASH_ACR_LATENCY_Msk          (0x7UL << FLASH_ACR_LATENCY_Pos)         /*!< 0x00000007 */
-#define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk
-#define FLASH_ACR_LATENCY_0WS          0x00000000U
-#define FLASH_ACR_LATENCY_1WS          0x00000001U
-#define FLASH_ACR_LATENCY_2WS          0x00000002U
-#define FLASH_ACR_LATENCY_3WS          0x00000003U
-#define FLASH_ACR_LATENCY_4WS          0x00000004U
-#define FLASH_ACR_LATENCY_5WS          0x00000005U
-#define FLASH_ACR_LATENCY_6WS          0x00000006U
-#define FLASH_ACR_LATENCY_7WS          0x00000007U
-
-
-#define FLASH_ACR_PRFTEN_Pos           (8U)                                    
-#define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */
-#define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk                    
-#define FLASH_ACR_ICEN_Pos             (9U)                                    
-#define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */
-#define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk                      
-#define FLASH_ACR_DCEN_Pos             (10U)                                   
-#define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */
-#define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk                      
-#define FLASH_ACR_ICRST_Pos            (11U)                                   
-#define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */
-#define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk                     
-#define FLASH_ACR_DCRST_Pos            (12U)                                   
-#define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */
-#define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk                     
-#define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)                                   
-#define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
-#define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk             
-#define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)                                    
-#define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
-#define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk             
-
-/*******************  Bits definition for FLASH_SR register  ******************/
-#define FLASH_SR_EOP_Pos               (0U)                                    
-#define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */
-#define FLASH_SR_EOP                   FLASH_SR_EOP_Msk                        
-#define FLASH_SR_SOP_Pos               (1U)                                    
-#define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */
-#define FLASH_SR_SOP                   FLASH_SR_SOP_Msk                        
-#define FLASH_SR_WRPERR_Pos            (4U)                                    
-#define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */
-#define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk                     
-#define FLASH_SR_PGAERR_Pos            (5U)                                    
-#define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */
-#define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk                     
-#define FLASH_SR_PGPERR_Pos            (6U)                                    
-#define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */
-#define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk                     
-#define FLASH_SR_PGSERR_Pos            (7U)                                    
-#define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */
-#define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk                     
-#define FLASH_SR_BSY_Pos               (16U)                                   
-#define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */
-#define FLASH_SR_BSY                   FLASH_SR_BSY_Msk                        
-
-/*******************  Bits definition for FLASH_CR register  ******************/
-#define FLASH_CR_PG_Pos                (0U)                                    
-#define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */
-#define FLASH_CR_PG                    FLASH_CR_PG_Msk                         
-#define FLASH_CR_SER_Pos               (1U)                                    
-#define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */
-#define FLASH_CR_SER                   FLASH_CR_SER_Msk                        
-#define FLASH_CR_MER_Pos               (2U)                                    
-#define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */
-#define FLASH_CR_MER                   FLASH_CR_MER_Msk                        
-#define FLASH_CR_SNB_Pos               (3U)                                    
-#define FLASH_CR_SNB_Msk               (0x1FUL << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */
-#define FLASH_CR_SNB                   FLASH_CR_SNB_Msk                        
-#define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */
-#define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */
-#define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */
-#define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */
-#define FLASH_CR_SNB_4                 (0x10UL << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */
-#define FLASH_CR_PSIZE_Pos             (8U)                                    
-#define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */
-#define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk                      
-#define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */
-#define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */
-#define FLASH_CR_STRT_Pos              (16U)                                   
-#define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */
-#define FLASH_CR_STRT                  FLASH_CR_STRT_Msk                       
-#define FLASH_CR_EOPIE_Pos             (24U)                                   
-#define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */
-#define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk                      
-#define FLASH_CR_ERRIE_Pos             (25U)
-#define FLASH_CR_ERRIE_Msk             (0x1UL << FLASH_CR_ERRIE_Pos)
-#define FLASH_CR_ERRIE                 FLASH_CR_ERRIE_Msk
-#define FLASH_CR_LOCK_Pos              (31U)                                   
-#define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */
-#define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk                       
-
-/*******************  Bits definition for FLASH_OPTCR register  ***************/
-#define FLASH_OPTCR_OPTLOCK_Pos        (0U)                                    
-#define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */
-#define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk                 
-#define FLASH_OPTCR_OPTSTRT_Pos        (1U)                                    
-#define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */
-#define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk                 
-
-#define FLASH_OPTCR_BOR_LEV_0          0x00000004U                             
-#define FLASH_OPTCR_BOR_LEV_1          0x00000008U                             
-#define FLASH_OPTCR_BOR_LEV_Pos        (2U)                                    
-#define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */
-#define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk                 
-#define FLASH_OPTCR_WDG_SW_Pos         (5U)                                    
-#define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */
-#define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk                  
-#define FLASH_OPTCR_nRST_STOP_Pos      (6U)                                    
-#define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */
-#define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk               
-#define FLASH_OPTCR_nRST_STDBY_Pos     (7U)                                    
-#define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */
-#define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk              
-#define FLASH_OPTCR_RDP_Pos            (8U)                                    
-#define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */
-#define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk                     
-#define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */
-#define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */
-#define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */
-#define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */
-#define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */
-#define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */
-#define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */
-#define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */
-#define FLASH_OPTCR_nWRP_Pos           (16U)                                   
-#define FLASH_OPTCR_nWRP_Msk           (0xFFFUL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */
-#define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk                    
-#define FLASH_OPTCR_nWRP_0             0x00010000U                             
-#define FLASH_OPTCR_nWRP_1             0x00020000U                             
-#define FLASH_OPTCR_nWRP_2             0x00040000U                             
-#define FLASH_OPTCR_nWRP_3             0x00080000U                             
-#define FLASH_OPTCR_nWRP_4             0x00100000U                             
-#define FLASH_OPTCR_nWRP_5             0x00200000U                             
-#define FLASH_OPTCR_nWRP_6             0x00400000U                             
-#define FLASH_OPTCR_nWRP_7             0x00800000U                             
-#define FLASH_OPTCR_nWRP_8             0x01000000U                             
-#define FLASH_OPTCR_nWRP_9             0x02000000U                             
-#define FLASH_OPTCR_nWRP_10            0x04000000U                             
-#define FLASH_OPTCR_nWRP_11            0x08000000U                             
-                                             
-/******************  Bits definition for FLASH_OPTCR1 register  ***************/
-#define FLASH_OPTCR1_nWRP_Pos          (16U)                                   
-#define FLASH_OPTCR1_nWRP_Msk          (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */
-#define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk                   
-#define FLASH_OPTCR1_nWRP_0            (0x001UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */
-#define FLASH_OPTCR1_nWRP_1            (0x002UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */
-#define FLASH_OPTCR1_nWRP_2            (0x004UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */
-#define FLASH_OPTCR1_nWRP_3            (0x008UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */
-#define FLASH_OPTCR1_nWRP_4            (0x010UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */
-#define FLASH_OPTCR1_nWRP_5            (0x020UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */
-#define FLASH_OPTCR1_nWRP_6            (0x040UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */
-#define FLASH_OPTCR1_nWRP_7            (0x080UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */
-#define FLASH_OPTCR1_nWRP_8            (0x100UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */
-#define FLASH_OPTCR1_nWRP_9            (0x200UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */
-#define FLASH_OPTCR1_nWRP_10           (0x400UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */
-#define FLASH_OPTCR1_nWRP_11           (0x800UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Flexible Static Memory Controller                        */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for FSMC_BCR1 register  *******************/
-#define FSMC_BCR1_MBKEN_Pos          (0U)                                      
-#define FSMC_BCR1_MBKEN_Msk          (0x1UL << FSMC_BCR1_MBKEN_Pos)             /*!< 0x00000001 */
-#define FSMC_BCR1_MBKEN              FSMC_BCR1_MBKEN_Msk                       /*!<Memory bank enable bit                 */
-#define FSMC_BCR1_MUXEN_Pos          (1U)                                      
-#define FSMC_BCR1_MUXEN_Msk          (0x1UL << FSMC_BCR1_MUXEN_Pos)             /*!< 0x00000002 */
-#define FSMC_BCR1_MUXEN              FSMC_BCR1_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */
-
-#define FSMC_BCR1_MTYP_Pos           (2U)                                      
-#define FSMC_BCR1_MTYP_Msk           (0x3UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x0000000C */
-#define FSMC_BCR1_MTYP               FSMC_BCR1_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */
-#define FSMC_BCR1_MTYP_0             (0x1UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000004 */
-#define FSMC_BCR1_MTYP_1             (0x2UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000008 */
-
-#define FSMC_BCR1_MWID_Pos           (4U)                                      
-#define FSMC_BCR1_MWID_Msk           (0x3UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000030 */
-#define FSMC_BCR1_MWID               FSMC_BCR1_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR1_MWID_0             (0x1UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000010 */
-#define FSMC_BCR1_MWID_1             (0x2UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000020 */
-
-#define FSMC_BCR1_FACCEN_Pos         (6U)                                      
-#define FSMC_BCR1_FACCEN_Msk         (0x1UL << FSMC_BCR1_FACCEN_Pos)            /*!< 0x00000040 */
-#define FSMC_BCR1_FACCEN             FSMC_BCR1_FACCEN_Msk                      /*!<Flash access enable                    */
-#define FSMC_BCR1_BURSTEN_Pos        (8U)                                      
-#define FSMC_BCR1_BURSTEN_Msk        (0x1UL << FSMC_BCR1_BURSTEN_Pos)           /*!< 0x00000100 */
-#define FSMC_BCR1_BURSTEN            FSMC_BCR1_BURSTEN_Msk                     /*!<Burst enable bit                       */
-#define FSMC_BCR1_WAITPOL_Pos        (9U)                                      
-#define FSMC_BCR1_WAITPOL_Msk        (0x1UL << FSMC_BCR1_WAITPOL_Pos)           /*!< 0x00000200 */
-#define FSMC_BCR1_WAITPOL            FSMC_BCR1_WAITPOL_Msk                     /*!<Wait signal polarity bit               */
-#define FSMC_BCR1_WRAPMOD_Pos        (10U)                                     
-#define FSMC_BCR1_WRAPMOD_Msk        (0x1UL << FSMC_BCR1_WRAPMOD_Pos)           /*!< 0x00000400 */
-#define FSMC_BCR1_WRAPMOD            FSMC_BCR1_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */
-#define FSMC_BCR1_WAITCFG_Pos        (11U)                                     
-#define FSMC_BCR1_WAITCFG_Msk        (0x1UL << FSMC_BCR1_WAITCFG_Pos)           /*!< 0x00000800 */
-#define FSMC_BCR1_WAITCFG            FSMC_BCR1_WAITCFG_Msk                     /*!<Wait timing configuration              */
-#define FSMC_BCR1_WREN_Pos           (12U)                                     
-#define FSMC_BCR1_WREN_Msk           (0x1UL << FSMC_BCR1_WREN_Pos)              /*!< 0x00001000 */
-#define FSMC_BCR1_WREN               FSMC_BCR1_WREN_Msk                        /*!<Write enable bit                       */
-#define FSMC_BCR1_WAITEN_Pos         (13U)                                     
-#define FSMC_BCR1_WAITEN_Msk         (0x1UL << FSMC_BCR1_WAITEN_Pos)            /*!< 0x00002000 */
-#define FSMC_BCR1_WAITEN             FSMC_BCR1_WAITEN_Msk                      /*!<Wait enable bit                        */
-#define FSMC_BCR1_EXTMOD_Pos         (14U)                                     
-#define FSMC_BCR1_EXTMOD_Msk         (0x1UL << FSMC_BCR1_EXTMOD_Pos)            /*!< 0x00004000 */
-#define FSMC_BCR1_EXTMOD             FSMC_BCR1_EXTMOD_Msk                      /*!<Extended mode enable                   */
-#define FSMC_BCR1_ASYNCWAIT_Pos      (15U)                                     
-#define FSMC_BCR1_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)         /*!< 0x00008000 */
-#define FSMC_BCR1_ASYNCWAIT          FSMC_BCR1_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */
-#define FSMC_BCR1_CPSIZE_Pos         (16U)                                     
-#define FSMC_BCR1_CPSIZE_Msk         (0x7UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00070000 */
-#define FSMC_BCR1_CPSIZE             FSMC_BCR1_CPSIZE_Msk                      /*!<CRAM page size */
-#define FSMC_BCR1_CPSIZE_0           (0x1UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00010000 */
-#define FSMC_BCR1_CPSIZE_1           (0x2UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00020000 */
-#define FSMC_BCR1_CPSIZE_2           (0x4UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00040000 */
-#define FSMC_BCR1_CBURSTRW_Pos       (19U)                                     
-#define FSMC_BCR1_CBURSTRW_Msk       (0x1UL << FSMC_BCR1_CBURSTRW_Pos)          /*!< 0x00080000 */
-#define FSMC_BCR1_CBURSTRW           FSMC_BCR1_CBURSTRW_Msk                    /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR2 register  *******************/
-#define FSMC_BCR2_MBKEN_Pos          (0U)                                      
-#define FSMC_BCR2_MBKEN_Msk          (0x1UL << FSMC_BCR2_MBKEN_Pos)             /*!< 0x00000001 */
-#define FSMC_BCR2_MBKEN              FSMC_BCR2_MBKEN_Msk                       /*!<Memory bank enable bit                */
-#define FSMC_BCR2_MUXEN_Pos          (1U)                                      
-#define FSMC_BCR2_MUXEN_Msk          (0x1UL << FSMC_BCR2_MUXEN_Pos)             /*!< 0x00000002 */
-#define FSMC_BCR2_MUXEN              FSMC_BCR2_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */
-
-#define FSMC_BCR2_MTYP_Pos           (2U)                                      
-#define FSMC_BCR2_MTYP_Msk           (0x3UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x0000000C */
-#define FSMC_BCR2_MTYP               FSMC_BCR2_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */
-#define FSMC_BCR2_MTYP_0             (0x1UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000004 */
-#define FSMC_BCR2_MTYP_1             (0x2UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000008 */
-
-#define FSMC_BCR2_MWID_Pos           (4U)                                      
-#define FSMC_BCR2_MWID_Msk           (0x3UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000030 */
-#define FSMC_BCR2_MWID               FSMC_BCR2_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR2_MWID_0             (0x1UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000010 */
-#define FSMC_BCR2_MWID_1             (0x2UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000020 */
-
-#define FSMC_BCR2_FACCEN_Pos         (6U)                                      
-#define FSMC_BCR2_FACCEN_Msk         (0x1UL << FSMC_BCR2_FACCEN_Pos)            /*!< 0x00000040 */
-#define FSMC_BCR2_FACCEN             FSMC_BCR2_FACCEN_Msk                      /*!<Flash access enable                    */
-#define FSMC_BCR2_BURSTEN_Pos        (8U)                                      
-#define FSMC_BCR2_BURSTEN_Msk        (0x1UL << FSMC_BCR2_BURSTEN_Pos)           /*!< 0x00000100 */
-#define FSMC_BCR2_BURSTEN            FSMC_BCR2_BURSTEN_Msk                     /*!<Burst enable bit                       */
-#define FSMC_BCR2_WAITPOL_Pos        (9U)                                      
-#define FSMC_BCR2_WAITPOL_Msk        (0x1UL << FSMC_BCR2_WAITPOL_Pos)           /*!< 0x00000200 */
-#define FSMC_BCR2_WAITPOL            FSMC_BCR2_WAITPOL_Msk                     /*!<Wait signal polarity bit               */
-#define FSMC_BCR2_WRAPMOD_Pos        (10U)                                     
-#define FSMC_BCR2_WRAPMOD_Msk        (0x1UL << FSMC_BCR2_WRAPMOD_Pos)           /*!< 0x00000400 */
-#define FSMC_BCR2_WRAPMOD            FSMC_BCR2_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */
-#define FSMC_BCR2_WAITCFG_Pos        (11U)                                     
-#define FSMC_BCR2_WAITCFG_Msk        (0x1UL << FSMC_BCR2_WAITCFG_Pos)           /*!< 0x00000800 */
-#define FSMC_BCR2_WAITCFG            FSMC_BCR2_WAITCFG_Msk                     /*!<Wait timing configuration              */
-#define FSMC_BCR2_WREN_Pos           (12U)                                     
-#define FSMC_BCR2_WREN_Msk           (0x1UL << FSMC_BCR2_WREN_Pos)              /*!< 0x00001000 */
-#define FSMC_BCR2_WREN               FSMC_BCR2_WREN_Msk                        /*!<Write enable bit                       */
-#define FSMC_BCR2_WAITEN_Pos         (13U)                                     
-#define FSMC_BCR2_WAITEN_Msk         (0x1UL << FSMC_BCR2_WAITEN_Pos)            /*!< 0x00002000 */
-#define FSMC_BCR2_WAITEN             FSMC_BCR2_WAITEN_Msk                      /*!<Wait enable bit                        */
-#define FSMC_BCR2_EXTMOD_Pos         (14U)                                     
-#define FSMC_BCR2_EXTMOD_Msk         (0x1UL << FSMC_BCR2_EXTMOD_Pos)            /*!< 0x00004000 */
-#define FSMC_BCR2_EXTMOD             FSMC_BCR2_EXTMOD_Msk                      /*!<Extended mode enable                   */
-#define FSMC_BCR2_ASYNCWAIT_Pos      (15U)                                     
-#define FSMC_BCR2_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)         /*!< 0x00008000 */
-#define FSMC_BCR2_ASYNCWAIT          FSMC_BCR2_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */
-#define FSMC_BCR2_CPSIZE_Pos         (16U)                                     
-#define FSMC_BCR2_CPSIZE_Msk         (0x7UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00070000 */
-#define FSMC_BCR2_CPSIZE             FSMC_BCR2_CPSIZE_Msk                      /*!<CRAM page size */
-#define FSMC_BCR2_CPSIZE_0           (0x1UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00010000 */
-#define FSMC_BCR2_CPSIZE_1           (0x2UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00020000 */
-#define FSMC_BCR2_CPSIZE_2           (0x4UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00040000 */
-#define FSMC_BCR2_CBURSTRW_Pos       (19U)                                     
-#define FSMC_BCR2_CBURSTRW_Msk       (0x1UL << FSMC_BCR2_CBURSTRW_Pos)          /*!< 0x00080000 */
-#define FSMC_BCR2_CBURSTRW           FSMC_BCR2_CBURSTRW_Msk                    /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR3 register  *******************/
-#define FSMC_BCR3_MBKEN_Pos          (0U)                                      
-#define FSMC_BCR3_MBKEN_Msk          (0x1UL << FSMC_BCR3_MBKEN_Pos)             /*!< 0x00000001 */
-#define FSMC_BCR3_MBKEN              FSMC_BCR3_MBKEN_Msk                       /*!<Memory bank enable bit                 */
-#define FSMC_BCR3_MUXEN_Pos          (1U)                                      
-#define FSMC_BCR3_MUXEN_Msk          (0x1UL << FSMC_BCR3_MUXEN_Pos)             /*!< 0x00000002 */
-#define FSMC_BCR3_MUXEN              FSMC_BCR3_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */
-
-#define FSMC_BCR3_MTYP_Pos           (2U)                                      
-#define FSMC_BCR3_MTYP_Msk           (0x3UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x0000000C */
-#define FSMC_BCR3_MTYP               FSMC_BCR3_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */
-#define FSMC_BCR3_MTYP_0             (0x1UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000004 */
-#define FSMC_BCR3_MTYP_1             (0x2UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000008 */
-
-#define FSMC_BCR3_MWID_Pos           (4U)                                      
-#define FSMC_BCR3_MWID_Msk           (0x3UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000030 */
-#define FSMC_BCR3_MWID               FSMC_BCR3_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR3_MWID_0             (0x1UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000010 */
-#define FSMC_BCR3_MWID_1             (0x2UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000020 */
-
-#define FSMC_BCR3_FACCEN_Pos         (6U)                                      
-#define FSMC_BCR3_FACCEN_Msk         (0x1UL << FSMC_BCR3_FACCEN_Pos)            /*!< 0x00000040 */
-#define FSMC_BCR3_FACCEN             FSMC_BCR3_FACCEN_Msk                      /*!<Flash access enable                    */
-#define FSMC_BCR3_BURSTEN_Pos        (8U)                                      
-#define FSMC_BCR3_BURSTEN_Msk        (0x1UL << FSMC_BCR3_BURSTEN_Pos)           /*!< 0x00000100 */
-#define FSMC_BCR3_BURSTEN            FSMC_BCR3_BURSTEN_Msk                     /*!<Burst enable bit                       */
-#define FSMC_BCR3_WAITPOL_Pos        (9U)                                      
-#define FSMC_BCR3_WAITPOL_Msk        (0x1UL << FSMC_BCR3_WAITPOL_Pos)           /*!< 0x00000200 */
-#define FSMC_BCR3_WAITPOL            FSMC_BCR3_WAITPOL_Msk                     /*!<Wait signal polarity bit               */
-#define FSMC_BCR3_WRAPMOD_Pos        (10U)                                     
-#define FSMC_BCR3_WRAPMOD_Msk        (0x1UL << FSMC_BCR3_WRAPMOD_Pos)           /*!< 0x00000400 */
-#define FSMC_BCR3_WRAPMOD            FSMC_BCR3_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */
-#define FSMC_BCR3_WAITCFG_Pos        (11U)                                     
-#define FSMC_BCR3_WAITCFG_Msk        (0x1UL << FSMC_BCR3_WAITCFG_Pos)           /*!< 0x00000800 */
-#define FSMC_BCR3_WAITCFG            FSMC_BCR3_WAITCFG_Msk                     /*!<Wait timing configuration              */
-#define FSMC_BCR3_WREN_Pos           (12U)                                     
-#define FSMC_BCR3_WREN_Msk           (0x1UL << FSMC_BCR3_WREN_Pos)              /*!< 0x00001000 */
-#define FSMC_BCR3_WREN               FSMC_BCR3_WREN_Msk                        /*!<Write enable bit                       */
-#define FSMC_BCR3_WAITEN_Pos         (13U)                                     
-#define FSMC_BCR3_WAITEN_Msk         (0x1UL << FSMC_BCR3_WAITEN_Pos)            /*!< 0x00002000 */
-#define FSMC_BCR3_WAITEN             FSMC_BCR3_WAITEN_Msk                      /*!<Wait enable bit                        */
-#define FSMC_BCR3_EXTMOD_Pos         (14U)                                     
-#define FSMC_BCR3_EXTMOD_Msk         (0x1UL << FSMC_BCR3_EXTMOD_Pos)            /*!< 0x00004000 */
-#define FSMC_BCR3_EXTMOD             FSMC_BCR3_EXTMOD_Msk                      /*!<Extended mode enable                   */
-#define FSMC_BCR3_ASYNCWAIT_Pos      (15U)                                     
-#define FSMC_BCR3_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)         /*!< 0x00008000 */
-#define FSMC_BCR3_ASYNCWAIT          FSMC_BCR3_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */
-#define FSMC_BCR3_CPSIZE_Pos         (16U)                                     
-#define FSMC_BCR3_CPSIZE_Msk         (0x7UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00070000 */
-#define FSMC_BCR3_CPSIZE             FSMC_BCR3_CPSIZE_Msk                      /*!<CRAM page size */
-#define FSMC_BCR3_CPSIZE_0           (0x1UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00010000 */
-#define FSMC_BCR3_CPSIZE_1           (0x2UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00020000 */
-#define FSMC_BCR3_CPSIZE_2           (0x4UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00040000 */
-#define FSMC_BCR3_CBURSTRW_Pos       (19U)                                     
-#define FSMC_BCR3_CBURSTRW_Msk       (0x1UL << FSMC_BCR3_CBURSTRW_Pos)          /*!< 0x00080000 */
-#define FSMC_BCR3_CBURSTRW           FSMC_BCR3_CBURSTRW_Msk                    /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BCR4 register  *******************/
-#define FSMC_BCR4_MBKEN_Pos          (0U)                                      
-#define FSMC_BCR4_MBKEN_Msk          (0x1UL << FSMC_BCR4_MBKEN_Pos)             /*!< 0x00000001 */
-#define FSMC_BCR4_MBKEN              FSMC_BCR4_MBKEN_Msk                       /*!<Memory bank enable bit */
-#define FSMC_BCR4_MUXEN_Pos          (1U)                                      
-#define FSMC_BCR4_MUXEN_Msk          (0x1UL << FSMC_BCR4_MUXEN_Pos)             /*!< 0x00000002 */
-#define FSMC_BCR4_MUXEN              FSMC_BCR4_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */
-
-#define FSMC_BCR4_MTYP_Pos           (2U)                                      
-#define FSMC_BCR4_MTYP_Msk           (0x3UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x0000000C */
-#define FSMC_BCR4_MTYP               FSMC_BCR4_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */
-#define FSMC_BCR4_MTYP_0             (0x1UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000004 */
-#define FSMC_BCR4_MTYP_1             (0x2UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000008 */
-
-#define FSMC_BCR4_MWID_Pos           (4U)                                      
-#define FSMC_BCR4_MWID_Msk           (0x3UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000030 */
-#define FSMC_BCR4_MWID               FSMC_BCR4_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */
-#define FSMC_BCR4_MWID_0             (0x1UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000010 */
-#define FSMC_BCR4_MWID_1             (0x2UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000020 */
-
-#define FSMC_BCR4_FACCEN_Pos         (6U)                                      
-#define FSMC_BCR4_FACCEN_Msk         (0x1UL << FSMC_BCR4_FACCEN_Pos)            /*!< 0x00000040 */
-#define FSMC_BCR4_FACCEN             FSMC_BCR4_FACCEN_Msk                      /*!<Flash access enable                    */
-#define FSMC_BCR4_BURSTEN_Pos        (8U)                                      
-#define FSMC_BCR4_BURSTEN_Msk        (0x1UL << FSMC_BCR4_BURSTEN_Pos)           /*!< 0x00000100 */
-#define FSMC_BCR4_BURSTEN            FSMC_BCR4_BURSTEN_Msk                     /*!<Burst enable bit                       */
-#define FSMC_BCR4_WAITPOL_Pos        (9U)                                      
-#define FSMC_BCR4_WAITPOL_Msk        (0x1UL << FSMC_BCR4_WAITPOL_Pos)           /*!< 0x00000200 */
-#define FSMC_BCR4_WAITPOL            FSMC_BCR4_WAITPOL_Msk                     /*!<Wait signal polarity bit               */
-#define FSMC_BCR4_WRAPMOD_Pos        (10U)                                     
-#define FSMC_BCR4_WRAPMOD_Msk        (0x1UL << FSMC_BCR4_WRAPMOD_Pos)           /*!< 0x00000400 */
-#define FSMC_BCR4_WRAPMOD            FSMC_BCR4_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */
-#define FSMC_BCR4_WAITCFG_Pos        (11U)                                     
-#define FSMC_BCR4_WAITCFG_Msk        (0x1UL << FSMC_BCR4_WAITCFG_Pos)           /*!< 0x00000800 */
-#define FSMC_BCR4_WAITCFG            FSMC_BCR4_WAITCFG_Msk                     /*!<Wait timing configuration              */
-#define FSMC_BCR4_WREN_Pos           (12U)                                     
-#define FSMC_BCR4_WREN_Msk           (0x1UL << FSMC_BCR4_WREN_Pos)              /*!< 0x00001000 */
-#define FSMC_BCR4_WREN               FSMC_BCR4_WREN_Msk                        /*!<Write enable bit                       */
-#define FSMC_BCR4_WAITEN_Pos         (13U)                                     
-#define FSMC_BCR4_WAITEN_Msk         (0x1UL << FSMC_BCR4_WAITEN_Pos)            /*!< 0x00002000 */
-#define FSMC_BCR4_WAITEN             FSMC_BCR4_WAITEN_Msk                      /*!<Wait enable bit                        */
-#define FSMC_BCR4_EXTMOD_Pos         (14U)                                     
-#define FSMC_BCR4_EXTMOD_Msk         (0x1UL << FSMC_BCR4_EXTMOD_Pos)            /*!< 0x00004000 */
-#define FSMC_BCR4_EXTMOD             FSMC_BCR4_EXTMOD_Msk                      /*!<Extended mode enable                   */
-#define FSMC_BCR4_ASYNCWAIT_Pos      (15U)                                     
-#define FSMC_BCR4_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)         /*!< 0x00008000 */
-#define FSMC_BCR4_ASYNCWAIT          FSMC_BCR4_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */
-#define FSMC_BCR4_CPSIZE_Pos         (16U)                                     
-#define FSMC_BCR4_CPSIZE_Msk         (0x7UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00070000 */
-#define FSMC_BCR4_CPSIZE             FSMC_BCR4_CPSIZE_Msk                      /*!<CRAM page size */
-#define FSMC_BCR4_CPSIZE_0           (0x1UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00010000 */
-#define FSMC_BCR4_CPSIZE_1           (0x2UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00020000 */
-#define FSMC_BCR4_CPSIZE_2           (0x4UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00040000 */
-#define FSMC_BCR4_CBURSTRW_Pos       (19U)                                     
-#define FSMC_BCR4_CBURSTRW_Msk       (0x1UL << FSMC_BCR4_CBURSTRW_Pos)          /*!< 0x00080000 */
-#define FSMC_BCR4_CBURSTRW           FSMC_BCR4_CBURSTRW_Msk                    /*!<Write burst enable                     */
-
-/******************  Bit definition for FSMC_BTR1 register  ******************/
-#define FSMC_BTR1_ADDSET_Pos         (0U)                                      
-#define FSMC_BTR1_ADDSET_Msk         (0xFUL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x0000000F */
-#define FSMC_BTR1_ADDSET             FSMC_BTR1_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR1_ADDSET_0           (0x1UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000001 */
-#define FSMC_BTR1_ADDSET_1           (0x2UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000002 */
-#define FSMC_BTR1_ADDSET_2           (0x4UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000004 */
-#define FSMC_BTR1_ADDSET_3           (0x8UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000008 */
-
-#define FSMC_BTR1_ADDHLD_Pos         (4U)                                      
-#define FSMC_BTR1_ADDHLD_Msk         (0xFUL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x000000F0 */
-#define FSMC_BTR1_ADDHLD             FSMC_BTR1_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR1_ADDHLD_0           (0x1UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000010 */
-#define FSMC_BTR1_ADDHLD_1           (0x2UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000020 */
-#define FSMC_BTR1_ADDHLD_2           (0x4UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000040 */
-#define FSMC_BTR1_ADDHLD_3           (0x8UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000080 */
-
-#define FSMC_BTR1_DATAST_Pos         (8U)                                      
-#define FSMC_BTR1_DATAST_Msk         (0xFFUL << FSMC_BTR1_DATAST_Pos)           /*!< 0x0000FF00 */
-#define FSMC_BTR1_DATAST             FSMC_BTR1_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */
-#define FSMC_BTR1_DATAST_0           (0x01UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000100 */
-#define FSMC_BTR1_DATAST_1           (0x02UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000200 */
-#define FSMC_BTR1_DATAST_2           (0x04UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000400 */
-#define FSMC_BTR1_DATAST_3           (0x08UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000800 */
-#define FSMC_BTR1_DATAST_4           (0x10UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00001000 */
-#define FSMC_BTR1_DATAST_5           (0x20UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00002000 */
-#define FSMC_BTR1_DATAST_6           (0x40UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00004000 */
-#define FSMC_BTR1_DATAST_7           (0x80UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00008000 */
-
-#define FSMC_BTR1_BUSTURN_Pos        (16U)                                     
-#define FSMC_BTR1_BUSTURN_Msk        (0xFUL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x000F0000 */
-#define FSMC_BTR1_BUSTURN            FSMC_BTR1_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR1_BUSTURN_0          (0x1UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00010000 */
-#define FSMC_BTR1_BUSTURN_1          (0x2UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00020000 */
-#define FSMC_BTR1_BUSTURN_2          (0x4UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00040000 */
-#define FSMC_BTR1_BUSTURN_3          (0x8UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00080000 */
-
-#define FSMC_BTR1_CLKDIV_Pos         (20U)                                     
-#define FSMC_BTR1_CLKDIV_Msk         (0xFUL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00F00000 */
-#define FSMC_BTR1_CLKDIV             FSMC_BTR1_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR1_CLKDIV_0           (0x1UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00100000 */
-#define FSMC_BTR1_CLKDIV_1           (0x2UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00200000 */
-#define FSMC_BTR1_CLKDIV_2           (0x4UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00400000 */
-#define FSMC_BTR1_CLKDIV_3           (0x8UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00800000 */
-
-#define FSMC_BTR1_DATLAT_Pos         (24U)                                     
-#define FSMC_BTR1_DATLAT_Msk         (0xFUL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x0F000000 */
-#define FSMC_BTR1_DATLAT             FSMC_BTR1_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR1_DATLAT_0           (0x1UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x01000000 */
-#define FSMC_BTR1_DATLAT_1           (0x2UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x02000000 */
-#define FSMC_BTR1_DATLAT_2           (0x4UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x04000000 */
-#define FSMC_BTR1_DATLAT_3           (0x8UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x08000000 */
-
-#define FSMC_BTR1_ACCMOD_Pos         (28U)                                     
-#define FSMC_BTR1_ACCMOD_Msk         (0x3UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x30000000 */
-#define FSMC_BTR1_ACCMOD             FSMC_BTR1_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR1_ACCMOD_0           (0x1UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x10000000 */
-#define FSMC_BTR1_ACCMOD_1           (0x2UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x20000000 */
-
-/******************  Bit definition for FSMC_BTR2 register  *******************/
-#define FSMC_BTR2_ADDSET_Pos         (0U)                                      
-#define FSMC_BTR2_ADDSET_Msk         (0xFUL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x0000000F */
-#define FSMC_BTR2_ADDSET             FSMC_BTR2_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR2_ADDSET_0           (0x1UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000001 */
-#define FSMC_BTR2_ADDSET_1           (0x2UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000002 */
-#define FSMC_BTR2_ADDSET_2           (0x4UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000004 */
-#define FSMC_BTR2_ADDSET_3           (0x8UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000008 */
-
-#define FSMC_BTR2_ADDHLD_Pos         (4U)                                      
-#define FSMC_BTR2_ADDHLD_Msk         (0xFUL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x000000F0 */
-#define FSMC_BTR2_ADDHLD             FSMC_BTR2_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR2_ADDHLD_0           (0x1UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000010 */
-#define FSMC_BTR2_ADDHLD_1           (0x2UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000020 */
-#define FSMC_BTR2_ADDHLD_2           (0x4UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000040 */
-#define FSMC_BTR2_ADDHLD_3           (0x8UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000080 */
-
-#define FSMC_BTR2_DATAST_Pos         (8U)                                      
-#define FSMC_BTR2_DATAST_Msk         (0xFFUL << FSMC_BTR2_DATAST_Pos)           /*!< 0x0000FF00 */
-#define FSMC_BTR2_DATAST             FSMC_BTR2_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */
-#define FSMC_BTR2_DATAST_0           (0x01UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000100 */
-#define FSMC_BTR2_DATAST_1           (0x02UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000200 */
-#define FSMC_BTR2_DATAST_2           (0x04UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000400 */
-#define FSMC_BTR2_DATAST_3           (0x08UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000800 */
-#define FSMC_BTR2_DATAST_4           (0x10UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00001000 */
-#define FSMC_BTR2_DATAST_5           (0x20UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00002000 */
-#define FSMC_BTR2_DATAST_6           (0x40UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00004000 */
-#define FSMC_BTR2_DATAST_7           (0x80UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00008000 */
-
-#define FSMC_BTR2_BUSTURN_Pos        (16U)                                     
-#define FSMC_BTR2_BUSTURN_Msk        (0xFUL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x000F0000 */
-#define FSMC_BTR2_BUSTURN            FSMC_BTR2_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR2_BUSTURN_0          (0x1UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00010000 */
-#define FSMC_BTR2_BUSTURN_1          (0x2UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00020000 */
-#define FSMC_BTR2_BUSTURN_2          (0x4UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00040000 */
-#define FSMC_BTR2_BUSTURN_3          (0x8UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00080000 */
-
-#define FSMC_BTR2_CLKDIV_Pos         (20U)                                     
-#define FSMC_BTR2_CLKDIV_Msk         (0xFUL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00F00000 */
-#define FSMC_BTR2_CLKDIV             FSMC_BTR2_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR2_CLKDIV_0           (0x1UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00100000 */
-#define FSMC_BTR2_CLKDIV_1           (0x2UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00200000 */
-#define FSMC_BTR2_CLKDIV_2           (0x4UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00400000 */
-#define FSMC_BTR2_CLKDIV_3           (0x8UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00800000 */
-
-#define FSMC_BTR2_DATLAT_Pos         (24U)                                     
-#define FSMC_BTR2_DATLAT_Msk         (0xFUL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x0F000000 */
-#define FSMC_BTR2_DATLAT             FSMC_BTR2_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR2_DATLAT_0           (0x1UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x01000000 */
-#define FSMC_BTR2_DATLAT_1           (0x2UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x02000000 */
-#define FSMC_BTR2_DATLAT_2           (0x4UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x04000000 */
-#define FSMC_BTR2_DATLAT_3           (0x8UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x08000000 */
-
-#define FSMC_BTR2_ACCMOD_Pos         (28U)                                     
-#define FSMC_BTR2_ACCMOD_Msk         (0x3UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x30000000 */
-#define FSMC_BTR2_ACCMOD             FSMC_BTR2_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR2_ACCMOD_0           (0x1UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x10000000 */
-#define FSMC_BTR2_ACCMOD_1           (0x2UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x20000000 */
-
-/*******************  Bit definition for FSMC_BTR3 register  *******************/
-#define FSMC_BTR3_ADDSET_Pos         (0U)                                      
-#define FSMC_BTR3_ADDSET_Msk         (0xFUL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x0000000F */
-#define FSMC_BTR3_ADDSET             FSMC_BTR3_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR3_ADDSET_0           (0x1UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000001 */
-#define FSMC_BTR3_ADDSET_1           (0x2UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000002 */
-#define FSMC_BTR3_ADDSET_2           (0x4UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000004 */
-#define FSMC_BTR3_ADDSET_3           (0x8UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000008 */
-
-#define FSMC_BTR3_ADDHLD_Pos         (4U)                                      
-#define FSMC_BTR3_ADDHLD_Msk         (0xFUL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x000000F0 */
-#define FSMC_BTR3_ADDHLD             FSMC_BTR3_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR3_ADDHLD_0           (0x1UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000010 */
-#define FSMC_BTR3_ADDHLD_1           (0x2UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000020 */
-#define FSMC_BTR3_ADDHLD_2           (0x4UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000040 */
-#define FSMC_BTR3_ADDHLD_3           (0x8UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000080 */
-
-#define FSMC_BTR3_DATAST_Pos         (8U)                                      
-#define FSMC_BTR3_DATAST_Msk         (0xFFUL << FSMC_BTR3_DATAST_Pos)           /*!< 0x0000FF00 */
-#define FSMC_BTR3_DATAST             FSMC_BTR3_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */
-#define FSMC_BTR3_DATAST_0           (0x01UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000100 */
-#define FSMC_BTR3_DATAST_1           (0x02UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000200 */
-#define FSMC_BTR3_DATAST_2           (0x04UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000400 */
-#define FSMC_BTR3_DATAST_3           (0x08UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000800 */
-#define FSMC_BTR3_DATAST_4           (0x10UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00001000 */
-#define FSMC_BTR3_DATAST_5           (0x20UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00002000 */
-#define FSMC_BTR3_DATAST_6           (0x40UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00004000 */
-#define FSMC_BTR3_DATAST_7           (0x80UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00008000 */
-
-#define FSMC_BTR3_BUSTURN_Pos        (16U)                                     
-#define FSMC_BTR3_BUSTURN_Msk        (0xFUL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x000F0000 */
-#define FSMC_BTR3_BUSTURN            FSMC_BTR3_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR3_BUSTURN_0          (0x1UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00010000 */
-#define FSMC_BTR3_BUSTURN_1          (0x2UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00020000 */
-#define FSMC_BTR3_BUSTURN_2          (0x4UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00040000 */
-#define FSMC_BTR3_BUSTURN_3          (0x8UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00080000 */
-
-#define FSMC_BTR3_CLKDIV_Pos         (20U)                                     
-#define FSMC_BTR3_CLKDIV_Msk         (0xFUL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00F00000 */
-#define FSMC_BTR3_CLKDIV             FSMC_BTR3_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR3_CLKDIV_0           (0x1UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00100000 */
-#define FSMC_BTR3_CLKDIV_1           (0x2UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00200000 */
-#define FSMC_BTR3_CLKDIV_2           (0x4UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00400000 */
-#define FSMC_BTR3_CLKDIV_3           (0x8UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00800000 */
-
-#define FSMC_BTR3_DATLAT_Pos         (24U)                                     
-#define FSMC_BTR3_DATLAT_Msk         (0xFUL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x0F000000 */
-#define FSMC_BTR3_DATLAT             FSMC_BTR3_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR3_DATLAT_0           (0x1UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x01000000 */
-#define FSMC_BTR3_DATLAT_1           (0x2UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x02000000 */
-#define FSMC_BTR3_DATLAT_2           (0x4UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x04000000 */
-#define FSMC_BTR3_DATLAT_3           (0x8UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x08000000 */
-
-#define FSMC_BTR3_ACCMOD_Pos         (28U)                                     
-#define FSMC_BTR3_ACCMOD_Msk         (0x3UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x30000000 */
-#define FSMC_BTR3_ACCMOD             FSMC_BTR3_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR3_ACCMOD_0           (0x1UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x10000000 */
-#define FSMC_BTR3_ACCMOD_1           (0x2UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x20000000 */
-
-/******************  Bit definition for FSMC_BTR4 register  *******************/
-#define FSMC_BTR4_ADDSET_Pos         (0U)                                      
-#define FSMC_BTR4_ADDSET_Msk         (0xFUL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x0000000F */
-#define FSMC_BTR4_ADDSET             FSMC_BTR4_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BTR4_ADDSET_0           (0x1UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000001 */
-#define FSMC_BTR4_ADDSET_1           (0x2UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000002 */
-#define FSMC_BTR4_ADDSET_2           (0x4UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000004 */
-#define FSMC_BTR4_ADDSET_3           (0x8UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000008 */
-
-#define FSMC_BTR4_ADDHLD_Pos         (4U)                                      
-#define FSMC_BTR4_ADDHLD_Msk         (0xFUL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x000000F0 */
-#define FSMC_BTR4_ADDHLD             FSMC_BTR4_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BTR4_ADDHLD_0           (0x1UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000010 */
-#define FSMC_BTR4_ADDHLD_1           (0x2UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000020 */
-#define FSMC_BTR4_ADDHLD_2           (0x4UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000040 */
-#define FSMC_BTR4_ADDHLD_3           (0x8UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000080 */
-
-#define FSMC_BTR4_DATAST_Pos         (8U)                                      
-#define FSMC_BTR4_DATAST_Msk         (0xFFUL << FSMC_BTR4_DATAST_Pos)           /*!< 0x0000FF00 */
-#define FSMC_BTR4_DATAST             FSMC_BTR4_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */
-#define FSMC_BTR4_DATAST_0           (0x01UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000100 */
-#define FSMC_BTR4_DATAST_1           (0x02UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000200 */
-#define FSMC_BTR4_DATAST_2           (0x04UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000400 */
-#define FSMC_BTR4_DATAST_3           (0x08UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000800 */
-#define FSMC_BTR4_DATAST_4           (0x10UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00001000 */
-#define FSMC_BTR4_DATAST_5           (0x20UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00002000 */
-#define FSMC_BTR4_DATAST_6           (0x40UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00004000 */
-#define FSMC_BTR4_DATAST_7           (0x80UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00008000 */
-
-#define FSMC_BTR4_BUSTURN_Pos        (16U)                                     
-#define FSMC_BTR4_BUSTURN_Msk        (0xFUL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x000F0000 */
-#define FSMC_BTR4_BUSTURN            FSMC_BTR4_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
-#define FSMC_BTR4_BUSTURN_0          (0x1UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00010000 */
-#define FSMC_BTR4_BUSTURN_1          (0x2UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00020000 */
-#define FSMC_BTR4_BUSTURN_2          (0x4UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00040000 */
-#define FSMC_BTR4_BUSTURN_3          (0x8UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00080000 */
-
-#define FSMC_BTR4_CLKDIV_Pos         (20U)                                     
-#define FSMC_BTR4_CLKDIV_Msk         (0xFUL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00F00000 */
-#define FSMC_BTR4_CLKDIV             FSMC_BTR4_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */
-#define FSMC_BTR4_CLKDIV_0           (0x1UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00100000 */
-#define FSMC_BTR4_CLKDIV_1           (0x2UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00200000 */
-#define FSMC_BTR4_CLKDIV_2           (0x4UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00400000 */
-#define FSMC_BTR4_CLKDIV_3           (0x8UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00800000 */
-
-#define FSMC_BTR4_DATLAT_Pos         (24U)                                     
-#define FSMC_BTR4_DATLAT_Msk         (0xFUL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x0F000000 */
-#define FSMC_BTR4_DATLAT             FSMC_BTR4_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */
-#define FSMC_BTR4_DATLAT_0           (0x1UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x01000000 */
-#define FSMC_BTR4_DATLAT_1           (0x2UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x02000000 */
-#define FSMC_BTR4_DATLAT_2           (0x4UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x04000000 */
-#define FSMC_BTR4_DATLAT_3           (0x8UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x08000000 */
-
-#define FSMC_BTR4_ACCMOD_Pos         (28U)                                     
-#define FSMC_BTR4_ACCMOD_Msk         (0x3UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x30000000 */
-#define FSMC_BTR4_ACCMOD             FSMC_BTR4_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BTR4_ACCMOD_0           (0x1UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x10000000 */
-#define FSMC_BTR4_ACCMOD_1           (0x2UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x20000000 */
-
-/******************  Bit definition for FSMC_BWTR1 register  ******************/
-#define FSMC_BWTR1_ADDSET_Pos        (0U)                                      
-#define FSMC_BWTR1_ADDSET_Msk        (0xFUL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x0000000F */
-#define FSMC_BWTR1_ADDSET            FSMC_BWTR1_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR1_ADDSET_0          (0x1UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000001 */
-#define FSMC_BWTR1_ADDSET_1          (0x2UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000002 */
-#define FSMC_BWTR1_ADDSET_2          (0x4UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000004 */
-#define FSMC_BWTR1_ADDSET_3          (0x8UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000008 */
-
-#define FSMC_BWTR1_ADDHLD_Pos        (4U)                                      
-#define FSMC_BWTR1_ADDHLD_Msk        (0xFUL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x000000F0 */
-#define FSMC_BWTR1_ADDHLD            FSMC_BWTR1_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR1_ADDHLD_0          (0x1UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000010 */
-#define FSMC_BWTR1_ADDHLD_1          (0x2UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000020 */
-#define FSMC_BWTR1_ADDHLD_2          (0x4UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000040 */
-#define FSMC_BWTR1_ADDHLD_3          (0x8UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000080 */
-
-#define FSMC_BWTR1_DATAST_Pos        (8U)                                      
-#define FSMC_BWTR1_DATAST_Msk        (0xFFUL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x0000FF00 */
-#define FSMC_BWTR1_DATAST            FSMC_BWTR1_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */
-#define FSMC_BWTR1_DATAST_0          (0x01UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000100 */
-#define FSMC_BWTR1_DATAST_1          (0x02UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000200 */
-#define FSMC_BWTR1_DATAST_2          (0x04UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000400 */
-#define FSMC_BWTR1_DATAST_3          (0x08UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000800 */
-#define FSMC_BWTR1_DATAST_4          (0x10UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00001000 */
-#define FSMC_BWTR1_DATAST_5          (0x20UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00002000 */
-#define FSMC_BWTR1_DATAST_6          (0x40UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00004000 */
-#define FSMC_BWTR1_DATAST_7          (0x80UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00008000 */
-
-#define FSMC_BWTR1_BUSTURN_Pos       (16U)                                     
-#define FSMC_BWTR1_BUSTURN_Msk       (0xFUL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x000F0000 */
-#define FSMC_BWTR1_BUSTURN           FSMC_BWTR1_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define FSMC_BWTR1_BUSTURN_0         (0x1UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00010000 */
-#define FSMC_BWTR1_BUSTURN_1         (0x2UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00020000 */
-#define FSMC_BWTR1_BUSTURN_2         (0x4UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00040000 */
-#define FSMC_BWTR1_BUSTURN_3         (0x8UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00080000 */
-
-#define FSMC_BWTR1_ACCMOD_Pos        (28U)                                     
-#define FSMC_BWTR1_ACCMOD_Msk        (0x3UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x30000000 */
-#define FSMC_BWTR1_ACCMOD            FSMC_BWTR1_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR1_ACCMOD_0          (0x1UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x10000000 */
-#define FSMC_BWTR1_ACCMOD_1          (0x2UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x20000000 */
-
-/******************  Bit definition for FSMC_BWTR2 register  ******************/
-#define FSMC_BWTR2_ADDSET_Pos        (0U)                                      
-#define FSMC_BWTR2_ADDSET_Msk        (0xFUL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x0000000F */
-#define FSMC_BWTR2_ADDSET            FSMC_BWTR2_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR2_ADDSET_0          (0x1UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000001 */
-#define FSMC_BWTR2_ADDSET_1          (0x2UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000002 */
-#define FSMC_BWTR2_ADDSET_2          (0x4UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000004 */
-#define FSMC_BWTR2_ADDSET_3          (0x8UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000008 */
-
-#define FSMC_BWTR2_ADDHLD_Pos        (4U)                                      
-#define FSMC_BWTR2_ADDHLD_Msk        (0xFUL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x000000F0 */
-#define FSMC_BWTR2_ADDHLD            FSMC_BWTR2_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR2_ADDHLD_0          (0x1UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000010 */
-#define FSMC_BWTR2_ADDHLD_1          (0x2UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000020 */
-#define FSMC_BWTR2_ADDHLD_2          (0x4UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000040 */
-#define FSMC_BWTR2_ADDHLD_3          (0x8UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000080 */
-
-#define FSMC_BWTR2_DATAST_Pos        (8U)                                      
-#define FSMC_BWTR2_DATAST_Msk        (0xFFUL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x0000FF00 */
-#define FSMC_BWTR2_DATAST            FSMC_BWTR2_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */
-#define FSMC_BWTR2_DATAST_0          (0x01UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000100 */
-#define FSMC_BWTR2_DATAST_1          (0x02UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000200 */
-#define FSMC_BWTR2_DATAST_2          (0x04UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000400 */
-#define FSMC_BWTR2_DATAST_3          (0x08UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000800 */
-#define FSMC_BWTR2_DATAST_4          (0x10UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00001000 */
-#define FSMC_BWTR2_DATAST_5          (0x20UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00002000 */
-#define FSMC_BWTR2_DATAST_6          (0x40UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00004000 */
-#define FSMC_BWTR2_DATAST_7          (0x80UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00008000 */
-
-#define FSMC_BWTR2_BUSTURN_Pos       (16U)                                     
-#define FSMC_BWTR2_BUSTURN_Msk       (0xFUL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x000F0000 */
-#define FSMC_BWTR2_BUSTURN           FSMC_BWTR2_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define FSMC_BWTR2_BUSTURN_0         (0x1UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00010000 */
-#define FSMC_BWTR2_BUSTURN_1         (0x2UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00020000 */
-#define FSMC_BWTR2_BUSTURN_2         (0x4UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00040000 */
-#define FSMC_BWTR2_BUSTURN_3         (0x8UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00080000 */
-
-#define FSMC_BWTR2_ACCMOD_Pos        (28U)                                     
-#define FSMC_BWTR2_ACCMOD_Msk        (0x3UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x30000000 */
-#define FSMC_BWTR2_ACCMOD            FSMC_BWTR2_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR2_ACCMOD_0          (0x1UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x10000000 */
-#define FSMC_BWTR2_ACCMOD_1          (0x2UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x20000000 */
-
-/******************  Bit definition for FSMC_BWTR3 register  ******************/
-#define FSMC_BWTR3_ADDSET_Pos        (0U)                                      
-#define FSMC_BWTR3_ADDSET_Msk        (0xFUL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x0000000F */
-#define FSMC_BWTR3_ADDSET            FSMC_BWTR3_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR3_ADDSET_0          (0x1UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000001 */
-#define FSMC_BWTR3_ADDSET_1          (0x2UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000002 */
-#define FSMC_BWTR3_ADDSET_2          (0x4UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000004 */
-#define FSMC_BWTR3_ADDSET_3          (0x8UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000008 */
-
-#define FSMC_BWTR3_ADDHLD_Pos        (4U)                                      
-#define FSMC_BWTR3_ADDHLD_Msk        (0xFUL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x000000F0 */
-#define FSMC_BWTR3_ADDHLD            FSMC_BWTR3_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR3_ADDHLD_0          (0x1UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000010 */
-#define FSMC_BWTR3_ADDHLD_1          (0x2UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000020 */
-#define FSMC_BWTR3_ADDHLD_2          (0x4UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000040 */
-#define FSMC_BWTR3_ADDHLD_3          (0x8UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000080 */
-
-#define FSMC_BWTR3_DATAST_Pos        (8U)                                      
-#define FSMC_BWTR3_DATAST_Msk        (0xFFUL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x0000FF00 */
-#define FSMC_BWTR3_DATAST            FSMC_BWTR3_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */
-#define FSMC_BWTR3_DATAST_0          (0x01UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000100 */
-#define FSMC_BWTR3_DATAST_1          (0x02UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000200 */
-#define FSMC_BWTR3_DATAST_2          (0x04UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000400 */
-#define FSMC_BWTR3_DATAST_3          (0x08UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000800 */
-#define FSMC_BWTR3_DATAST_4          (0x10UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00001000 */
-#define FSMC_BWTR3_DATAST_5          (0x20UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00002000 */
-#define FSMC_BWTR3_DATAST_6          (0x40UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00004000 */
-#define FSMC_BWTR3_DATAST_7          (0x80UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00008000 */
-
-#define FSMC_BWTR3_BUSTURN_Pos       (16U)                                     
-#define FSMC_BWTR3_BUSTURN_Msk       (0xFUL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x000F0000 */
-#define FSMC_BWTR3_BUSTURN           FSMC_BWTR3_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define FSMC_BWTR3_BUSTURN_0         (0x1UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00010000 */
-#define FSMC_BWTR3_BUSTURN_1         (0x2UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00020000 */
-#define FSMC_BWTR3_BUSTURN_2         (0x4UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00040000 */
-#define FSMC_BWTR3_BUSTURN_3         (0x8UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00080000 */
-
-#define FSMC_BWTR3_ACCMOD_Pos        (28U)                                     
-#define FSMC_BWTR3_ACCMOD_Msk        (0x3UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x30000000 */
-#define FSMC_BWTR3_ACCMOD            FSMC_BWTR3_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR3_ACCMOD_0          (0x1UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x10000000 */
-#define FSMC_BWTR3_ACCMOD_1          (0x2UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x20000000 */
-
-/******************  Bit definition for FSMC_BWTR4 register  ******************/
-#define FSMC_BWTR4_ADDSET_Pos        (0U)                                      
-#define FSMC_BWTR4_ADDSET_Msk        (0xFUL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x0000000F */
-#define FSMC_BWTR4_ADDSET            FSMC_BWTR4_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
-#define FSMC_BWTR4_ADDSET_0          (0x1UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000001 */
-#define FSMC_BWTR4_ADDSET_1          (0x2UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000002 */
-#define FSMC_BWTR4_ADDSET_2          (0x4UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000004 */
-#define FSMC_BWTR4_ADDSET_3          (0x8UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000008 */
-
-#define FSMC_BWTR4_ADDHLD_Pos        (4U)                                      
-#define FSMC_BWTR4_ADDHLD_Msk        (0xFUL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x000000F0 */
-#define FSMC_BWTR4_ADDHLD            FSMC_BWTR4_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
-#define FSMC_BWTR4_ADDHLD_0          (0x1UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000010 */
-#define FSMC_BWTR4_ADDHLD_1          (0x2UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000020 */
-#define FSMC_BWTR4_ADDHLD_2          (0x4UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000040 */
-#define FSMC_BWTR4_ADDHLD_3          (0x8UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000080 */
-
-#define FSMC_BWTR4_DATAST_Pos        (8U)                                      
-#define FSMC_BWTR4_DATAST_Msk        (0xFFUL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x0000FF00 */
-#define FSMC_BWTR4_DATAST            FSMC_BWTR4_DATAST_Msk                     /*!<DATAST [3:0] bits (Data-phase duration) */
-#define FSMC_BWTR4_DATAST_0          0x00000100U                               /*!<Bit 0 */
-#define FSMC_BWTR4_DATAST_1          0x00000200U                               /*!<Bit 1 */
-#define FSMC_BWTR4_DATAST_2          0x00000400U                               /*!<Bit 2 */
-#define FSMC_BWTR4_DATAST_3          0x00000800U                               /*!<Bit 3 */
-#define FSMC_BWTR4_DATAST_4          0x00001000U                               /*!<Bit 4 */
-#define FSMC_BWTR4_DATAST_5          0x00002000U                               /*!<Bit 5 */
-#define FSMC_BWTR4_DATAST_6          0x00004000U                               /*!<Bit 6 */
-#define FSMC_BWTR4_DATAST_7          0x00008000U                               /*!<Bit 7 */
-
-#define FSMC_BWTR4_BUSTURN_Pos       (16U)                                     
-#define FSMC_BWTR4_BUSTURN_Msk       (0xFUL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x000F0000 */
-#define FSMC_BWTR4_BUSTURN           FSMC_BWTR4_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
-#define FSMC_BWTR4_BUSTURN_0         (0x1UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00010000 */
-#define FSMC_BWTR4_BUSTURN_1         (0x2UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00020000 */
-#define FSMC_BWTR4_BUSTURN_2         (0x4UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00040000 */
-#define FSMC_BWTR4_BUSTURN_3         (0x8UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00080000 */
-
-#define FSMC_BWTR4_ACCMOD_Pos        (28U)                                     
-#define FSMC_BWTR4_ACCMOD_Msk        (0x3UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x30000000 */
-#define FSMC_BWTR4_ACCMOD            FSMC_BWTR4_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
-#define FSMC_BWTR4_ACCMOD_0          (0x1UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x10000000 */
-#define FSMC_BWTR4_ACCMOD_1          (0x2UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x20000000 */
-
-/******************  Bit definition for FSMC_PCR2 register  *******************/
-#define FSMC_PCR2_PWAITEN_Pos        (1U)                                      
-#define FSMC_PCR2_PWAITEN_Msk        (0x1UL << FSMC_PCR2_PWAITEN_Pos)           /*!< 0x00000002 */
-#define FSMC_PCR2_PWAITEN            FSMC_PCR2_PWAITEN_Msk                     /*!<Wait feature enable bit */
-#define FSMC_PCR2_PBKEN_Pos          (2U)                                      
-#define FSMC_PCR2_PBKEN_Msk          (0x1UL << FSMC_PCR2_PBKEN_Pos)             /*!< 0x00000004 */
-#define FSMC_PCR2_PBKEN              FSMC_PCR2_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */
-#define FSMC_PCR2_PTYP_Pos           (3U)                                      
-#define FSMC_PCR2_PTYP_Msk           (0x1UL << FSMC_PCR2_PTYP_Pos)              /*!< 0x00000008 */
-#define FSMC_PCR2_PTYP               FSMC_PCR2_PTYP_Msk                        /*!<Memory type */
-
-#define FSMC_PCR2_PWID_Pos           (4U)                                      
-#define FSMC_PCR2_PWID_Msk           (0x3UL << FSMC_PCR2_PWID_Pos)              /*!< 0x00000030 */
-#define FSMC_PCR2_PWID               FSMC_PCR2_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define FSMC_PCR2_PWID_0             (0x1UL << FSMC_PCR2_PWID_Pos)              /*!< 0x00000010 */
-#define FSMC_PCR2_PWID_1             (0x2UL << FSMC_PCR2_PWID_Pos)              /*!< 0x00000020 */
-
-#define FSMC_PCR2_ECCEN_Pos          (6U)                                      
-#define FSMC_PCR2_ECCEN_Msk          (0x1UL << FSMC_PCR2_ECCEN_Pos)             /*!< 0x00000040 */
-#define FSMC_PCR2_ECCEN              FSMC_PCR2_ECCEN_Msk                       /*!<ECC computation logic enable bit */
-
-#define FSMC_PCR2_TCLR_Pos           (9U)                                      
-#define FSMC_PCR2_TCLR_Msk           (0xFUL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00001E00 */
-#define FSMC_PCR2_TCLR               FSMC_PCR2_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define FSMC_PCR2_TCLR_0             (0x1UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000200 */
-#define FSMC_PCR2_TCLR_1             (0x2UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000400 */
-#define FSMC_PCR2_TCLR_2             (0x4UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000800 */
-#define FSMC_PCR2_TCLR_3             (0x8UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00001000 */
-
-#define FSMC_PCR2_TAR_Pos            (13U)                                     
-#define FSMC_PCR2_TAR_Msk            (0xFUL << FSMC_PCR2_TAR_Pos)               /*!< 0x0001E000 */
-#define FSMC_PCR2_TAR                FSMC_PCR2_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */
-#define FSMC_PCR2_TAR_0              (0x1UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00002000 */
-#define FSMC_PCR2_TAR_1              (0x2UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00004000 */
-#define FSMC_PCR2_TAR_2              (0x4UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00008000 */
-#define FSMC_PCR2_TAR_3              (0x8UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00010000 */
-
-#define FSMC_PCR2_ECCPS_Pos          (17U)                                     
-#define FSMC_PCR2_ECCPS_Msk          (0x7UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x000E0000 */
-#define FSMC_PCR2_ECCPS              FSMC_PCR2_ECCPS_Msk                       /*!<ECCPS[1:0] bits (ECC page size) */
-#define FSMC_PCR2_ECCPS_0            (0x1UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00020000 */
-#define FSMC_PCR2_ECCPS_1            (0x2UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00040000 */
-#define FSMC_PCR2_ECCPS_2            (0x4UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00080000 */
-
-/******************  Bit definition for FSMC_PCR3 register  *******************/
-#define FSMC_PCR3_PWAITEN_Pos        (1U)                                      
-#define FSMC_PCR3_PWAITEN_Msk        (0x1UL << FSMC_PCR3_PWAITEN_Pos)           /*!< 0x00000002 */
-#define FSMC_PCR3_PWAITEN            FSMC_PCR3_PWAITEN_Msk                     /*!<Wait feature enable bit */
-#define FSMC_PCR3_PBKEN_Pos          (2U)                                      
-#define FSMC_PCR3_PBKEN_Msk          (0x1UL << FSMC_PCR3_PBKEN_Pos)             /*!< 0x00000004 */
-#define FSMC_PCR3_PBKEN              FSMC_PCR3_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */
-#define FSMC_PCR3_PTYP_Pos           (3U)                                      
-#define FSMC_PCR3_PTYP_Msk           (0x1UL << FSMC_PCR3_PTYP_Pos)              /*!< 0x00000008 */
-#define FSMC_PCR3_PTYP               FSMC_PCR3_PTYP_Msk                        /*!<Memory type */
-
-#define FSMC_PCR3_PWID_Pos           (4U)                                      
-#define FSMC_PCR3_PWID_Msk           (0x3UL << FSMC_PCR3_PWID_Pos)              /*!< 0x00000030 */
-#define FSMC_PCR3_PWID               FSMC_PCR3_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define FSMC_PCR3_PWID_0             (0x1UL << FSMC_PCR3_PWID_Pos)              /*!< 0x00000010 */
-#define FSMC_PCR3_PWID_1             (0x2UL << FSMC_PCR3_PWID_Pos)              /*!< 0x00000020 */
-
-#define FSMC_PCR3_ECCEN_Pos          (6U)                                      
-#define FSMC_PCR3_ECCEN_Msk          (0x1UL << FSMC_PCR3_ECCEN_Pos)             /*!< 0x00000040 */
-#define FSMC_PCR3_ECCEN              FSMC_PCR3_ECCEN_Msk                       /*!<ECC computation logic enable bit */
-
-#define FSMC_PCR3_TCLR_Pos           (9U)                                      
-#define FSMC_PCR3_TCLR_Msk           (0xFUL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00001E00 */
-#define FSMC_PCR3_TCLR               FSMC_PCR3_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define FSMC_PCR3_TCLR_0             (0x1UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000200 */
-#define FSMC_PCR3_TCLR_1             (0x2UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000400 */
-#define FSMC_PCR3_TCLR_2             (0x4UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000800 */
-#define FSMC_PCR3_TCLR_3             (0x8UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00001000 */
-
-#define FSMC_PCR3_TAR_Pos            (13U)                                     
-#define FSMC_PCR3_TAR_Msk            (0xFUL << FSMC_PCR3_TAR_Pos)               /*!< 0x0001E000 */
-#define FSMC_PCR3_TAR                FSMC_PCR3_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */
-#define FSMC_PCR3_TAR_0              (0x1UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00002000 */
-#define FSMC_PCR3_TAR_1              (0x2UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00004000 */
-#define FSMC_PCR3_TAR_2              (0x4UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00008000 */
-#define FSMC_PCR3_TAR_3              (0x8UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00010000 */
-
-#define FSMC_PCR3_ECCPS_Pos          (17U)                                     
-#define FSMC_PCR3_ECCPS_Msk          (0x7UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x000E0000 */
-#define FSMC_PCR3_ECCPS              FSMC_PCR3_ECCPS_Msk                       /*!<ECCPS[2:0] bits (ECC page size) */
-#define FSMC_PCR3_ECCPS_0            (0x1UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00020000 */
-#define FSMC_PCR3_ECCPS_1            (0x2UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00040000 */
-#define FSMC_PCR3_ECCPS_2            (0x4UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00080000 */
-
-/******************  Bit definition for FSMC_PCR4 register  *******************/
-#define FSMC_PCR4_PWAITEN_Pos        (1U)                                      
-#define FSMC_PCR4_PWAITEN_Msk        (0x1UL << FSMC_PCR4_PWAITEN_Pos)           /*!< 0x00000002 */
-#define FSMC_PCR4_PWAITEN            FSMC_PCR4_PWAITEN_Msk                     /*!<Wait feature enable bit */
-#define FSMC_PCR4_PBKEN_Pos          (2U)                                      
-#define FSMC_PCR4_PBKEN_Msk          (0x1UL << FSMC_PCR4_PBKEN_Pos)             /*!< 0x00000004 */
-#define FSMC_PCR4_PBKEN              FSMC_PCR4_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */
-#define FSMC_PCR4_PTYP_Pos           (3U)                                      
-#define FSMC_PCR4_PTYP_Msk           (0x1UL << FSMC_PCR4_PTYP_Pos)              /*!< 0x00000008 */
-#define FSMC_PCR4_PTYP               FSMC_PCR4_PTYP_Msk                        /*!<Memory type */
-
-#define FSMC_PCR4_PWID_Pos           (4U)                                      
-#define FSMC_PCR4_PWID_Msk           (0x3UL << FSMC_PCR4_PWID_Pos)              /*!< 0x00000030 */
-#define FSMC_PCR4_PWID               FSMC_PCR4_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */
-#define FSMC_PCR4_PWID_0             (0x1UL << FSMC_PCR4_PWID_Pos)              /*!< 0x00000010 */
-#define FSMC_PCR4_PWID_1             (0x2UL << FSMC_PCR4_PWID_Pos)              /*!< 0x00000020 */
-
-#define FSMC_PCR4_ECCEN_Pos          (6U)                                      
-#define FSMC_PCR4_ECCEN_Msk          (0x1UL << FSMC_PCR4_ECCEN_Pos)             /*!< 0x00000040 */
-#define FSMC_PCR4_ECCEN              FSMC_PCR4_ECCEN_Msk                       /*!<ECC computation logic enable bit */
-
-#define FSMC_PCR4_TCLR_Pos           (9U)                                      
-#define FSMC_PCR4_TCLR_Msk           (0xFUL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00001E00 */
-#define FSMC_PCR4_TCLR               FSMC_PCR4_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */
-#define FSMC_PCR4_TCLR_0             (0x1UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000200 */
-#define FSMC_PCR4_TCLR_1             (0x2UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000400 */
-#define FSMC_PCR4_TCLR_2             (0x4UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000800 */
-#define FSMC_PCR4_TCLR_3             (0x8UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00001000 */
-
-#define FSMC_PCR4_TAR_Pos            (13U)                                     
-#define FSMC_PCR4_TAR_Msk            (0xFUL << FSMC_PCR4_TAR_Pos)               /*!< 0x0001E000 */
-#define FSMC_PCR4_TAR                FSMC_PCR4_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */
-#define FSMC_PCR4_TAR_0              (0x1UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00002000 */
-#define FSMC_PCR4_TAR_1              (0x2UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00004000 */
-#define FSMC_PCR4_TAR_2              (0x4UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00008000 */
-#define FSMC_PCR4_TAR_3              (0x8UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00010000 */
-
-#define FSMC_PCR4_ECCPS_Pos          (17U)                                     
-#define FSMC_PCR4_ECCPS_Msk          (0x7UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x000E0000 */
-#define FSMC_PCR4_ECCPS              FSMC_PCR4_ECCPS_Msk                       /*!<ECCPS[2:0] bits (ECC page size) */
-#define FSMC_PCR4_ECCPS_0            (0x1UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00020000 */
-#define FSMC_PCR4_ECCPS_1            (0x2UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00040000 */
-#define FSMC_PCR4_ECCPS_2            (0x4UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00080000 */
-
-/*******************  Bit definition for FSMC_SR2 register  *******************/
-#define FSMC_SR2_IRS_Pos             (0U)                                      
-#define FSMC_SR2_IRS_Msk             (0x1UL << FSMC_SR2_IRS_Pos)                /*!< 0x00000001 */
-#define FSMC_SR2_IRS                 FSMC_SR2_IRS_Msk                          /*!<Interrupt Rising Edge status                */
-#define FSMC_SR2_ILS_Pos             (1U)                                      
-#define FSMC_SR2_ILS_Msk             (0x1UL << FSMC_SR2_ILS_Pos)                /*!< 0x00000002 */
-#define FSMC_SR2_ILS                 FSMC_SR2_ILS_Msk                          /*!<Interrupt Level status                      */
-#define FSMC_SR2_IFS_Pos             (2U)                                      
-#define FSMC_SR2_IFS_Msk             (0x1UL << FSMC_SR2_IFS_Pos)                /*!< 0x00000004 */
-#define FSMC_SR2_IFS                 FSMC_SR2_IFS_Msk                          /*!<Interrupt Falling Edge status               */
-#define FSMC_SR2_IREN_Pos            (3U)                                      
-#define FSMC_SR2_IREN_Msk            (0x1UL << FSMC_SR2_IREN_Pos)               /*!< 0x00000008 */
-#define FSMC_SR2_IREN                FSMC_SR2_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit  */
-#define FSMC_SR2_ILEN_Pos            (4U)                                      
-#define FSMC_SR2_ILEN_Msk            (0x1UL << FSMC_SR2_ILEN_Pos)               /*!< 0x00000010 */
-#define FSMC_SR2_ILEN                FSMC_SR2_ILEN_Msk                         /*!<Interrupt Level detection Enable bit        */
-#define FSMC_SR2_IFEN_Pos            (5U)                                      
-#define FSMC_SR2_IFEN_Msk            (0x1UL << FSMC_SR2_IFEN_Pos)               /*!< 0x00000020 */
-#define FSMC_SR2_IFEN                FSMC_SR2_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit */
-#define FSMC_SR2_FEMPT_Pos           (6U)                                      
-#define FSMC_SR2_FEMPT_Msk           (0x1UL << FSMC_SR2_FEMPT_Pos)              /*!< 0x00000040 */
-#define FSMC_SR2_FEMPT               FSMC_SR2_FEMPT_Msk                        /*!<FIFO empty */
-
-/*******************  Bit definition for FSMC_SR3 register  *******************/
-#define FSMC_SR3_IRS_Pos             (0U)                                      
-#define FSMC_SR3_IRS_Msk             (0x1UL << FSMC_SR3_IRS_Pos)                /*!< 0x00000001 */
-#define FSMC_SR3_IRS                 FSMC_SR3_IRS_Msk                          /*!<Interrupt Rising Edge status                */
-#define FSMC_SR3_ILS_Pos             (1U)                                      
-#define FSMC_SR3_ILS_Msk             (0x1UL << FSMC_SR3_ILS_Pos)                /*!< 0x00000002 */
-#define FSMC_SR3_ILS                 FSMC_SR3_ILS_Msk                          /*!<Interrupt Level status                      */
-#define FSMC_SR3_IFS_Pos             (2U)                                      
-#define FSMC_SR3_IFS_Msk             (0x1UL << FSMC_SR3_IFS_Pos)                /*!< 0x00000004 */
-#define FSMC_SR3_IFS                 FSMC_SR3_IFS_Msk                          /*!<Interrupt Falling Edge status               */
-#define FSMC_SR3_IREN_Pos            (3U)                                      
-#define FSMC_SR3_IREN_Msk            (0x1UL << FSMC_SR3_IREN_Pos)               /*!< 0x00000008 */
-#define FSMC_SR3_IREN                FSMC_SR3_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit  */
-#define FSMC_SR3_ILEN_Pos            (4U)                                      
-#define FSMC_SR3_ILEN_Msk            (0x1UL << FSMC_SR3_ILEN_Pos)               /*!< 0x00000010 */
-#define FSMC_SR3_ILEN                FSMC_SR3_ILEN_Msk                         /*!<Interrupt Level detection Enable bit        */
-#define FSMC_SR3_IFEN_Pos            (5U)                                      
-#define FSMC_SR3_IFEN_Msk            (0x1UL << FSMC_SR3_IFEN_Pos)               /*!< 0x00000020 */
-#define FSMC_SR3_IFEN                FSMC_SR3_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit */
-#define FSMC_SR3_FEMPT_Pos           (6U)                                      
-#define FSMC_SR3_FEMPT_Msk           (0x1UL << FSMC_SR3_FEMPT_Pos)              /*!< 0x00000040 */
-#define FSMC_SR3_FEMPT               FSMC_SR3_FEMPT_Msk                        /*!<FIFO empty */
-
-/*******************  Bit definition for FSMC_SR4 register  *******************/
-#define FSMC_SR4_IRS_Pos             (0U)                                      
-#define FSMC_SR4_IRS_Msk             (0x1UL << FSMC_SR4_IRS_Pos)                /*!< 0x00000001 */
-#define FSMC_SR4_IRS                 FSMC_SR4_IRS_Msk                          /*!<Interrupt Rising Edge status                 */
-#define FSMC_SR4_ILS_Pos             (1U)                                      
-#define FSMC_SR4_ILS_Msk             (0x1UL << FSMC_SR4_ILS_Pos)                /*!< 0x00000002 */
-#define FSMC_SR4_ILS                 FSMC_SR4_ILS_Msk                          /*!<Interrupt Level status                       */
-#define FSMC_SR4_IFS_Pos             (2U)                                      
-#define FSMC_SR4_IFS_Msk             (0x1UL << FSMC_SR4_IFS_Pos)                /*!< 0x00000004 */
-#define FSMC_SR4_IFS                 FSMC_SR4_IFS_Msk                          /*!<Interrupt Falling Edge status                */
-#define FSMC_SR4_IREN_Pos            (3U)                                      
-#define FSMC_SR4_IREN_Msk            (0x1UL << FSMC_SR4_IREN_Pos)               /*!< 0x00000008 */
-#define FSMC_SR4_IREN                FSMC_SR4_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit   */
-#define FSMC_SR4_ILEN_Pos            (4U)                                      
-#define FSMC_SR4_ILEN_Msk            (0x1UL << FSMC_SR4_ILEN_Pos)               /*!< 0x00000010 */
-#define FSMC_SR4_ILEN                FSMC_SR4_ILEN_Msk                         /*!<Interrupt Level detection Enable bit         */
-#define FSMC_SR4_IFEN_Pos            (5U)                                      
-#define FSMC_SR4_IFEN_Msk            (0x1UL << FSMC_SR4_IFEN_Pos)               /*!< 0x00000020 */
-#define FSMC_SR4_IFEN                FSMC_SR4_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit  */
-#define FSMC_SR4_FEMPT_Pos           (6U)                                      
-#define FSMC_SR4_FEMPT_Msk           (0x1UL << FSMC_SR4_FEMPT_Pos)              /*!< 0x00000040 */
-#define FSMC_SR4_FEMPT               FSMC_SR4_FEMPT_Msk                        /*!<FIFO empty */
-
-/******************  Bit definition for FSMC_PMEM2 register  ******************/
-#define FSMC_PMEM2_MEMSET2_Pos       (0U)                                      
-#define FSMC_PMEM2_MEMSET2_Msk       (0xFFUL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x000000FF */
-#define FSMC_PMEM2_MEMSET2           FSMC_PMEM2_MEMSET2_Msk                    /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
-#define FSMC_PMEM2_MEMSET2_0         (0x01UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000001 */
-#define FSMC_PMEM2_MEMSET2_1         (0x02UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000002 */
-#define FSMC_PMEM2_MEMSET2_2         (0x04UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000004 */
-#define FSMC_PMEM2_MEMSET2_3         (0x08UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000008 */
-#define FSMC_PMEM2_MEMSET2_4         (0x10UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000010 */
-#define FSMC_PMEM2_MEMSET2_5         (0x20UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000020 */
-#define FSMC_PMEM2_MEMSET2_6         (0x40UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000040 */
-#define FSMC_PMEM2_MEMSET2_7         (0x80UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000080 */
-
-#define FSMC_PMEM2_MEMWAIT2_Pos      (8U)                                      
-#define FSMC_PMEM2_MEMWAIT2_Msk      (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x0000FF00 */
-#define FSMC_PMEM2_MEMWAIT2          FSMC_PMEM2_MEMWAIT2_Msk                   /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
-#define FSMC_PMEM2_MEMWAIT2_0        (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000100 */
-#define FSMC_PMEM2_MEMWAIT2_1        (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000200 */
-#define FSMC_PMEM2_MEMWAIT2_2        (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000400 */
-#define FSMC_PMEM2_MEMWAIT2_3        (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000800 */
-#define FSMC_PMEM2_MEMWAIT2_4        (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00001000 */
-#define FSMC_PMEM2_MEMWAIT2_5        (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00002000 */
-#define FSMC_PMEM2_MEMWAIT2_6        (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00004000 */
-#define FSMC_PMEM2_MEMWAIT2_7        (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00008000 */
-
-#define FSMC_PMEM2_MEMHOLD2_Pos      (16U)                                     
-#define FSMC_PMEM2_MEMHOLD2_Msk      (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00FF0000 */
-#define FSMC_PMEM2_MEMHOLD2          FSMC_PMEM2_MEMHOLD2_Msk                   /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
-#define FSMC_PMEM2_MEMHOLD2_0        (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00010000 */
-#define FSMC_PMEM2_MEMHOLD2_1        (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00020000 */
-#define FSMC_PMEM2_MEMHOLD2_2        (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00040000 */
-#define FSMC_PMEM2_MEMHOLD2_3        (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00080000 */
-#define FSMC_PMEM2_MEMHOLD2_4        (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00100000 */
-#define FSMC_PMEM2_MEMHOLD2_5        (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00200000 */
-#define FSMC_PMEM2_MEMHOLD2_6        (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00400000 */
-#define FSMC_PMEM2_MEMHOLD2_7        (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00800000 */
-
-#define FSMC_PMEM2_MEMHIZ2_Pos       (24U)                                     
-#define FSMC_PMEM2_MEMHIZ2_Msk       (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0xFF000000 */
-#define FSMC_PMEM2_MEMHIZ2           FSMC_PMEM2_MEMHIZ2_Msk                    /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
-#define FSMC_PMEM2_MEMHIZ2_0         (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x01000000 */
-#define FSMC_PMEM2_MEMHIZ2_1         (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x02000000 */
-#define FSMC_PMEM2_MEMHIZ2_2         (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x04000000 */
-#define FSMC_PMEM2_MEMHIZ2_3         (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x08000000 */
-#define FSMC_PMEM2_MEMHIZ2_4         (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x10000000 */
-#define FSMC_PMEM2_MEMHIZ2_5         (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x20000000 */
-#define FSMC_PMEM2_MEMHIZ2_6         (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x40000000 */
-#define FSMC_PMEM2_MEMHIZ2_7         (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x80000000 */
-
-/******************  Bit definition for FSMC_PMEM3 register  ******************/
-#define FSMC_PMEM3_MEMSET3_Pos       (0U)                                      
-#define FSMC_PMEM3_MEMSET3_Msk       (0xFFUL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x000000FF */
-#define FSMC_PMEM3_MEMSET3           FSMC_PMEM3_MEMSET3_Msk                    /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
-#define FSMC_PMEM3_MEMSET3_0         (0x01UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000001 */
-#define FSMC_PMEM3_MEMSET3_1         (0x02UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000002 */
-#define FSMC_PMEM3_MEMSET3_2         (0x04UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000004 */
-#define FSMC_PMEM3_MEMSET3_3         (0x08UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000008 */
-#define FSMC_PMEM3_MEMSET3_4         (0x10UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000010 */
-#define FSMC_PMEM3_MEMSET3_5         (0x20UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000020 */
-#define FSMC_PMEM3_MEMSET3_6         (0x40UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000040 */
-#define FSMC_PMEM3_MEMSET3_7         (0x80UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000080 */
-
-#define FSMC_PMEM3_MEMWAIT3_Pos      (8U)                                      
-#define FSMC_PMEM3_MEMWAIT3_Msk      (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x0000FF00 */
-#define FSMC_PMEM3_MEMWAIT3          FSMC_PMEM3_MEMWAIT3_Msk                   /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
-#define FSMC_PMEM3_MEMWAIT3_0        (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000100 */
-#define FSMC_PMEM3_MEMWAIT3_1        (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000200 */
-#define FSMC_PMEM3_MEMWAIT3_2        (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000400 */
-#define FSMC_PMEM3_MEMWAIT3_3        (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000800 */
-#define FSMC_PMEM3_MEMWAIT3_4        (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00001000 */
-#define FSMC_PMEM3_MEMWAIT3_5        (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00002000 */
-#define FSMC_PMEM3_MEMWAIT3_6        (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00004000 */
-#define FSMC_PMEM3_MEMWAIT3_7        (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00008000 */
-
-#define FSMC_PMEM3_MEMHOLD3_Pos      (16U)                                     
-#define FSMC_PMEM3_MEMHOLD3_Msk      (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00FF0000 */
-#define FSMC_PMEM3_MEMHOLD3          FSMC_PMEM3_MEMHOLD3_Msk                   /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
-#define FSMC_PMEM3_MEMHOLD3_0        (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00010000 */
-#define FSMC_PMEM3_MEMHOLD3_1        (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00020000 */
-#define FSMC_PMEM3_MEMHOLD3_2        (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00040000 */
-#define FSMC_PMEM3_MEMHOLD3_3        (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00080000 */
-#define FSMC_PMEM3_MEMHOLD3_4        (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00100000 */
-#define FSMC_PMEM3_MEMHOLD3_5        (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00200000 */
-#define FSMC_PMEM3_MEMHOLD3_6        (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00400000 */
-#define FSMC_PMEM3_MEMHOLD3_7        (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00800000 */
-
-#define FSMC_PMEM3_MEMHIZ3_Pos       (24U)                                     
-#define FSMC_PMEM3_MEMHIZ3_Msk       (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0xFF000000 */
-#define FSMC_PMEM3_MEMHIZ3           FSMC_PMEM3_MEMHIZ3_Msk                    /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
-#define FSMC_PMEM3_MEMHIZ3_0         (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x01000000 */
-#define FSMC_PMEM3_MEMHIZ3_1         (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x02000000 */
-#define FSMC_PMEM3_MEMHIZ3_2         (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x04000000 */
-#define FSMC_PMEM3_MEMHIZ3_3         (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x08000000 */
-#define FSMC_PMEM3_MEMHIZ3_4         (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x10000000 */
-#define FSMC_PMEM3_MEMHIZ3_5         (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x20000000 */
-#define FSMC_PMEM3_MEMHIZ3_6         (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x40000000 */
-#define FSMC_PMEM3_MEMHIZ3_7         (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x80000000 */
-
-/******************  Bit definition for FSMC_PMEM4 register  ******************/
-#define FSMC_PMEM4_MEMSET4_Pos       (0U)                                      
-#define FSMC_PMEM4_MEMSET4_Msk       (0xFFUL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x000000FF */
-#define FSMC_PMEM4_MEMSET4           FSMC_PMEM4_MEMSET4_Msk                    /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
-#define FSMC_PMEM4_MEMSET4_0         (0x01UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000001 */
-#define FSMC_PMEM4_MEMSET4_1         (0x02UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000002 */
-#define FSMC_PMEM4_MEMSET4_2         (0x04UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000004 */
-#define FSMC_PMEM4_MEMSET4_3         (0x08UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000008 */
-#define FSMC_PMEM4_MEMSET4_4         (0x10UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000010 */
-#define FSMC_PMEM4_MEMSET4_5         (0x20UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000020 */
-#define FSMC_PMEM4_MEMSET4_6         (0x40UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000040 */
-#define FSMC_PMEM4_MEMSET4_7         (0x80UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000080 */
-
-#define FSMC_PMEM4_MEMWAIT4_Pos      (8U)                                      
-#define FSMC_PMEM4_MEMWAIT4_Msk      (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x0000FF00 */
-#define FSMC_PMEM4_MEMWAIT4          FSMC_PMEM4_MEMWAIT4_Msk                   /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
-#define FSMC_PMEM4_MEMWAIT4_0        (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000100 */
-#define FSMC_PMEM4_MEMWAIT4_1        (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000200 */
-#define FSMC_PMEM4_MEMWAIT4_2        (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000400 */
-#define FSMC_PMEM4_MEMWAIT4_3        (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000800 */
-#define FSMC_PMEM4_MEMWAIT4_4        (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00001000 */
-#define FSMC_PMEM4_MEMWAIT4_5        (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00002000 */
-#define FSMC_PMEM4_MEMWAIT4_6        (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00004000 */
-#define FSMC_PMEM4_MEMWAIT4_7        (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00008000 */
-
-#define FSMC_PMEM4_MEMHOLD4_Pos      (16U)                                     
-#define FSMC_PMEM4_MEMHOLD4_Msk      (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00FF0000 */
-#define FSMC_PMEM4_MEMHOLD4          FSMC_PMEM4_MEMHOLD4_Msk                   /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
-#define FSMC_PMEM4_MEMHOLD4_0        (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00010000 */
-#define FSMC_PMEM4_MEMHOLD4_1        (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00020000 */
-#define FSMC_PMEM4_MEMHOLD4_2        (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00040000 */
-#define FSMC_PMEM4_MEMHOLD4_3        (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00080000 */
-#define FSMC_PMEM4_MEMHOLD4_4        (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00100000 */
-#define FSMC_PMEM4_MEMHOLD4_5        (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00200000 */
-#define FSMC_PMEM4_MEMHOLD4_6        (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00400000 */
-#define FSMC_PMEM4_MEMHOLD4_7        (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00800000 */
-
-#define FSMC_PMEM4_MEMHIZ4_Pos       (24U)                                     
-#define FSMC_PMEM4_MEMHIZ4_Msk       (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0xFF000000 */
-#define FSMC_PMEM4_MEMHIZ4           FSMC_PMEM4_MEMHIZ4_Msk                    /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
-#define FSMC_PMEM4_MEMHIZ4_0         (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x01000000 */
-#define FSMC_PMEM4_MEMHIZ4_1         (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x02000000 */
-#define FSMC_PMEM4_MEMHIZ4_2         (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x04000000 */
-#define FSMC_PMEM4_MEMHIZ4_3         (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x08000000 */
-#define FSMC_PMEM4_MEMHIZ4_4         (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x10000000 */
-#define FSMC_PMEM4_MEMHIZ4_5         (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x20000000 */
-#define FSMC_PMEM4_MEMHIZ4_6         (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x40000000 */
-#define FSMC_PMEM4_MEMHIZ4_7         (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x80000000 */
-
-/******************  Bit definition for FSMC_PATT2 register  ******************/
-#define FSMC_PATT2_ATTSET2_Pos       (0U)                                      
-#define FSMC_PATT2_ATTSET2_Msk       (0xFFUL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x000000FF */
-#define FSMC_PATT2_ATTSET2           FSMC_PATT2_ATTSET2_Msk                    /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
-#define FSMC_PATT2_ATTSET2_0         (0x01UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000001 */
-#define FSMC_PATT2_ATTSET2_1         (0x02UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000002 */
-#define FSMC_PATT2_ATTSET2_2         (0x04UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000004 */
-#define FSMC_PATT2_ATTSET2_3         (0x08UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000008 */
-#define FSMC_PATT2_ATTSET2_4         (0x10UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000010 */
-#define FSMC_PATT2_ATTSET2_5         (0x20UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000020 */
-#define FSMC_PATT2_ATTSET2_6         (0x40UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000040 */
-#define FSMC_PATT2_ATTSET2_7         (0x80UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000080 */
-
-#define FSMC_PATT2_ATTWAIT2_Pos      (8U)                                      
-#define FSMC_PATT2_ATTWAIT2_Msk      (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x0000FF00 */
-#define FSMC_PATT2_ATTWAIT2          FSMC_PATT2_ATTWAIT2_Msk                   /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
-#define FSMC_PATT2_ATTWAIT2_0        (0x01UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000100 */
-#define FSMC_PATT2_ATTWAIT2_1        (0x02UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000200 */
-#define FSMC_PATT2_ATTWAIT2_2        (0x04UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000400 */
-#define FSMC_PATT2_ATTWAIT2_3        (0x08UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000800 */
-#define FSMC_PATT2_ATTWAIT2_4        (0x10UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00001000 */
-#define FSMC_PATT2_ATTWAIT2_5        (0x20UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00002000 */
-#define FSMC_PATT2_ATTWAIT2_6        (0x40UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00004000 */
-#define FSMC_PATT2_ATTWAIT2_7        (0x80UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00008000 */
-
-#define FSMC_PATT2_ATTHOLD2_Pos      (16U)                                     
-#define FSMC_PATT2_ATTHOLD2_Msk      (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00FF0000 */
-#define FSMC_PATT2_ATTHOLD2          FSMC_PATT2_ATTHOLD2_Msk                   /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
-#define FSMC_PATT2_ATTHOLD2_0        (0x01UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00010000 */
-#define FSMC_PATT2_ATTHOLD2_1        (0x02UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00020000 */
-#define FSMC_PATT2_ATTHOLD2_2        (0x04UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00040000 */
-#define FSMC_PATT2_ATTHOLD2_3        (0x08UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00080000 */
-#define FSMC_PATT2_ATTHOLD2_4        (0x10UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00100000 */
-#define FSMC_PATT2_ATTHOLD2_5        (0x20UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00200000 */
-#define FSMC_PATT2_ATTHOLD2_6        (0x40UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00400000 */
-#define FSMC_PATT2_ATTHOLD2_7        (0x80UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00800000 */
-
-#define FSMC_PATT2_ATTHIZ2_Pos       (24U)                                     
-#define FSMC_PATT2_ATTHIZ2_Msk       (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0xFF000000 */
-#define FSMC_PATT2_ATTHIZ2           FSMC_PATT2_ATTHIZ2_Msk                    /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
-#define FSMC_PATT2_ATTHIZ2_0         (0x01UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x01000000 */
-#define FSMC_PATT2_ATTHIZ2_1         (0x02UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x02000000 */
-#define FSMC_PATT2_ATTHIZ2_2         (0x04UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x04000000 */
-#define FSMC_PATT2_ATTHIZ2_3         (0x08UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x08000000 */
-#define FSMC_PATT2_ATTHIZ2_4         (0x10UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x10000000 */
-#define FSMC_PATT2_ATTHIZ2_5         (0x20UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x20000000 */
-#define FSMC_PATT2_ATTHIZ2_6         (0x40UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x40000000 */
-#define FSMC_PATT2_ATTHIZ2_7         (0x80UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x80000000 */
-
-/******************  Bit definition for FSMC_PATT3 register  ******************/
-#define FSMC_PATT3_ATTSET3_Pos       (0U)                                      
-#define FSMC_PATT3_ATTSET3_Msk       (0xFFUL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x000000FF */
-#define FSMC_PATT3_ATTSET3           FSMC_PATT3_ATTSET3_Msk                    /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
-#define FSMC_PATT3_ATTSET3_0         (0x01UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000001 */
-#define FSMC_PATT3_ATTSET3_1         (0x02UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000002 */
-#define FSMC_PATT3_ATTSET3_2         (0x04UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000004 */
-#define FSMC_PATT3_ATTSET3_3         (0x08UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000008 */
-#define FSMC_PATT3_ATTSET3_4         (0x10UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000010 */
-#define FSMC_PATT3_ATTSET3_5         (0x20UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000020 */
-#define FSMC_PATT3_ATTSET3_6         (0x40UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000040 */
-#define FSMC_PATT3_ATTSET3_7         (0x80UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000080 */
-
-#define FSMC_PATT3_ATTWAIT3_Pos      (8U)                                      
-#define FSMC_PATT3_ATTWAIT3_Msk      (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x0000FF00 */
-#define FSMC_PATT3_ATTWAIT3          FSMC_PATT3_ATTWAIT3_Msk                   /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
-#define FSMC_PATT3_ATTWAIT3_0        (0x01UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000100 */
-#define FSMC_PATT3_ATTWAIT3_1        (0x02UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000200 */
-#define FSMC_PATT3_ATTWAIT3_2        (0x04UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000400 */
-#define FSMC_PATT3_ATTWAIT3_3        (0x08UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000800 */
-#define FSMC_PATT3_ATTWAIT3_4        (0x10UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00001000 */
-#define FSMC_PATT3_ATTWAIT3_5        (0x20UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00002000 */
-#define FSMC_PATT3_ATTWAIT3_6        (0x40UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00004000 */
-#define FSMC_PATT3_ATTWAIT3_7        (0x80UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00008000 */
-
-#define FSMC_PATT3_ATTHOLD3_Pos      (16U)                                     
-#define FSMC_PATT3_ATTHOLD3_Msk      (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00FF0000 */
-#define FSMC_PATT3_ATTHOLD3          FSMC_PATT3_ATTHOLD3_Msk                   /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
-#define FSMC_PATT3_ATTHOLD3_0        (0x01UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00010000 */
-#define FSMC_PATT3_ATTHOLD3_1        (0x02UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00020000 */
-#define FSMC_PATT3_ATTHOLD3_2        (0x04UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00040000 */
-#define FSMC_PATT3_ATTHOLD3_3        (0x08UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00080000 */
-#define FSMC_PATT3_ATTHOLD3_4        (0x10UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00100000 */
-#define FSMC_PATT3_ATTHOLD3_5        (0x20UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00200000 */
-#define FSMC_PATT3_ATTHOLD3_6        (0x40UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00400000 */
-#define FSMC_PATT3_ATTHOLD3_7        (0x80UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00800000 */
-
-#define FSMC_PATT3_ATTHIZ3_Pos       (24U)                                     
-#define FSMC_PATT3_ATTHIZ3_Msk       (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0xFF000000 */
-#define FSMC_PATT3_ATTHIZ3           FSMC_PATT3_ATTHIZ3_Msk                    /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
-#define FSMC_PATT3_ATTHIZ3_0         (0x01UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x01000000 */
-#define FSMC_PATT3_ATTHIZ3_1         (0x02UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x02000000 */
-#define FSMC_PATT3_ATTHIZ3_2         (0x04UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x04000000 */
-#define FSMC_PATT3_ATTHIZ3_3         (0x08UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x08000000 */
-#define FSMC_PATT3_ATTHIZ3_4         (0x10UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x10000000 */
-#define FSMC_PATT3_ATTHIZ3_5         (0x20UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x20000000 */
-#define FSMC_PATT3_ATTHIZ3_6         (0x40UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x40000000 */
-#define FSMC_PATT3_ATTHIZ3_7         (0x80UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x80000000 */
-
-/******************  Bit definition for FSMC_PATT4 register  ******************/
-#define FSMC_PATT4_ATTSET4_Pos       (0U)                                      
-#define FSMC_PATT4_ATTSET4_Msk       (0xFFUL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x000000FF */
-#define FSMC_PATT4_ATTSET4           FSMC_PATT4_ATTSET4_Msk                    /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
-#define FSMC_PATT4_ATTSET4_0         (0x01UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000001 */
-#define FSMC_PATT4_ATTSET4_1         (0x02UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000002 */
-#define FSMC_PATT4_ATTSET4_2         (0x04UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000004 */
-#define FSMC_PATT4_ATTSET4_3         (0x08UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000008 */
-#define FSMC_PATT4_ATTSET4_4         (0x10UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000010 */
-#define FSMC_PATT4_ATTSET4_5         (0x20UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000020 */
-#define FSMC_PATT4_ATTSET4_6         (0x40UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000040 */
-#define FSMC_PATT4_ATTSET4_7         (0x80UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000080 */
-
-#define FSMC_PATT4_ATTWAIT4_Pos      (8U)                                      
-#define FSMC_PATT4_ATTWAIT4_Msk      (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x0000FF00 */
-#define FSMC_PATT4_ATTWAIT4          FSMC_PATT4_ATTWAIT4_Msk                   /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
-#define FSMC_PATT4_ATTWAIT4_0        (0x01UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000100 */
-#define FSMC_PATT4_ATTWAIT4_1        (0x02UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000200 */
-#define FSMC_PATT4_ATTWAIT4_2        (0x04UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000400 */
-#define FSMC_PATT4_ATTWAIT4_3        (0x08UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000800 */
-#define FSMC_PATT4_ATTWAIT4_4        (0x10UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00001000 */
-#define FSMC_PATT4_ATTWAIT4_5        (0x20UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00002000 */
-#define FSMC_PATT4_ATTWAIT4_6        (0x40UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00004000 */
-#define FSMC_PATT4_ATTWAIT4_7        (0x80UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00008000 */
-
-#define FSMC_PATT4_ATTHOLD4_Pos      (16U)                                     
-#define FSMC_PATT4_ATTHOLD4_Msk      (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00FF0000 */
-#define FSMC_PATT4_ATTHOLD4          FSMC_PATT4_ATTHOLD4_Msk                   /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
-#define FSMC_PATT4_ATTHOLD4_0        (0x01UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00010000 */
-#define FSMC_PATT4_ATTHOLD4_1        (0x02UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00020000 */
-#define FSMC_PATT4_ATTHOLD4_2        (0x04UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00040000 */
-#define FSMC_PATT4_ATTHOLD4_3        (0x08UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00080000 */
-#define FSMC_PATT4_ATTHOLD4_4        (0x10UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00100000 */
-#define FSMC_PATT4_ATTHOLD4_5        (0x20UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00200000 */
-#define FSMC_PATT4_ATTHOLD4_6        (0x40UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00400000 */
-#define FSMC_PATT4_ATTHOLD4_7        (0x80UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00800000 */
-
-#define FSMC_PATT4_ATTHIZ4_Pos       (24U)                                     
-#define FSMC_PATT4_ATTHIZ4_Msk       (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0xFF000000 */
-#define FSMC_PATT4_ATTHIZ4           FSMC_PATT4_ATTHIZ4_Msk                    /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
-#define FSMC_PATT4_ATTHIZ4_0         (0x01UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x01000000 */
-#define FSMC_PATT4_ATTHIZ4_1         (0x02UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x02000000 */
-#define FSMC_PATT4_ATTHIZ4_2         (0x04UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x04000000 */
-#define FSMC_PATT4_ATTHIZ4_3         (0x08UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x08000000 */
-#define FSMC_PATT4_ATTHIZ4_4         (0x10UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x10000000 */
-#define FSMC_PATT4_ATTHIZ4_5         (0x20UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x20000000 */
-#define FSMC_PATT4_ATTHIZ4_6         (0x40UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x40000000 */
-#define FSMC_PATT4_ATTHIZ4_7         (0x80UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x80000000 */
-
-/******************  Bit definition for FSMC_PIO4 register  *******************/
-#define FSMC_PIO4_IOSET4_Pos         (0U)                                      
-#define FSMC_PIO4_IOSET4_Msk         (0xFFUL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x000000FF */
-#define FSMC_PIO4_IOSET4             FSMC_PIO4_IOSET4_Msk                      /*!<IOSET4[7:0] bits (I/O 4 setup time) */
-#define FSMC_PIO4_IOSET4_0           (0x01UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000001 */
-#define FSMC_PIO4_IOSET4_1           (0x02UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000002 */
-#define FSMC_PIO4_IOSET4_2           (0x04UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000004 */
-#define FSMC_PIO4_IOSET4_3           (0x08UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000008 */
-#define FSMC_PIO4_IOSET4_4           (0x10UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000010 */
-#define FSMC_PIO4_IOSET4_5           (0x20UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000020 */
-#define FSMC_PIO4_IOSET4_6           (0x40UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000040 */
-#define FSMC_PIO4_IOSET4_7           (0x80UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000080 */
-
-#define FSMC_PIO4_IOWAIT4_Pos        (8U)                                      
-#define FSMC_PIO4_IOWAIT4_Msk        (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x0000FF00 */
-#define FSMC_PIO4_IOWAIT4            FSMC_PIO4_IOWAIT4_Msk                     /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
-#define FSMC_PIO4_IOWAIT4_0          (0x01UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000100 */
-#define FSMC_PIO4_IOWAIT4_1          (0x02UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000200 */
-#define FSMC_PIO4_IOWAIT4_2          (0x04UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000400 */
-#define FSMC_PIO4_IOWAIT4_3          (0x08UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000800 */
-#define FSMC_PIO4_IOWAIT4_4          (0x10UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00001000 */
-#define FSMC_PIO4_IOWAIT4_5          (0x20UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00002000 */
-#define FSMC_PIO4_IOWAIT4_6          (0x40UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00004000 */
-#define FSMC_PIO4_IOWAIT4_7          (0x80UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00008000 */
-
-#define FSMC_PIO4_IOHOLD4_Pos        (16U)                                     
-#define FSMC_PIO4_IOHOLD4_Msk        (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00FF0000 */
-#define FSMC_PIO4_IOHOLD4            FSMC_PIO4_IOHOLD4_Msk                     /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
-#define FSMC_PIO4_IOHOLD4_0          (0x01UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00010000 */
-#define FSMC_PIO4_IOHOLD4_1          (0x02UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00020000 */
-#define FSMC_PIO4_IOHOLD4_2          (0x04UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00040000 */
-#define FSMC_PIO4_IOHOLD4_3          (0x08UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00080000 */
-#define FSMC_PIO4_IOHOLD4_4          (0x10UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00100000 */
-#define FSMC_PIO4_IOHOLD4_5          (0x20UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00200000 */
-#define FSMC_PIO4_IOHOLD4_6          (0x40UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00400000 */
-#define FSMC_PIO4_IOHOLD4_7          (0x80UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00800000 */
-
-#define FSMC_PIO4_IOHIZ4_Pos         (24U)                                     
-#define FSMC_PIO4_IOHIZ4_Msk         (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0xFF000000 */
-#define FSMC_PIO4_IOHIZ4             FSMC_PIO4_IOHIZ4_Msk                      /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
-#define FSMC_PIO4_IOHIZ4_0           (0x01UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x01000000 */
-#define FSMC_PIO4_IOHIZ4_1           (0x02UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x02000000 */
-#define FSMC_PIO4_IOHIZ4_2           (0x04UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x04000000 */
-#define FSMC_PIO4_IOHIZ4_3           (0x08UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x08000000 */
-#define FSMC_PIO4_IOHIZ4_4           (0x10UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x10000000 */
-#define FSMC_PIO4_IOHIZ4_5           (0x20UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x20000000 */
-#define FSMC_PIO4_IOHIZ4_6           (0x40UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x40000000 */
-#define FSMC_PIO4_IOHIZ4_7           (0x80UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x80000000 */
-
-/******************  Bit definition for FSMC_ECCR2 register  ******************/
-#define FSMC_ECCR2_ECC2_Pos          (0U)                                      
-#define FSMC_ECCR2_ECC2_Msk          (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos)      /*!< 0xFFFFFFFF */
-#define FSMC_ECCR2_ECC2              FSMC_ECCR2_ECC2_Msk                       /*!<ECC result */
-
-/******************  Bit definition for FSMC_ECCR3 register  ******************/
-#define FSMC_ECCR3_ECC3_Pos          (0U)                                      
-#define FSMC_ECCR3_ECC3_Msk          (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos)      /*!< 0xFFFFFFFF */
-#define FSMC_ECCR3_ECC3              FSMC_ECCR3_ECC3_Msk                       /*!<ECC result */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0_Pos            (0U)                                  
-#define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */
-#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk                 
-#define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */
-#define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */
-#define GPIO_MODER_MODER1_Pos            (2U)                                  
-#define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */
-#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk                 
-#define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */
-#define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */
-#define GPIO_MODER_MODER2_Pos            (4U)                                  
-#define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */
-#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk                 
-#define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */
-#define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */
-#define GPIO_MODER_MODER3_Pos            (6U)                                  
-#define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */
-#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk                 
-#define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */
-#define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */
-#define GPIO_MODER_MODER4_Pos            (8U)                                  
-#define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */
-#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk                 
-#define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */
-#define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */
-#define GPIO_MODER_MODER5_Pos            (10U)                                 
-#define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */
-#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk                 
-#define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */
-#define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */
-#define GPIO_MODER_MODER6_Pos            (12U)                                 
-#define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */
-#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk                 
-#define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */
-#define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */
-#define GPIO_MODER_MODER7_Pos            (14U)                                 
-#define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */
-#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk                 
-#define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */
-#define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */
-#define GPIO_MODER_MODER8_Pos            (16U)                                 
-#define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */
-#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk                 
-#define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */
-#define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */
-#define GPIO_MODER_MODER9_Pos            (18U)                                 
-#define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */
-#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk                 
-#define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */
-#define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */
-#define GPIO_MODER_MODER10_Pos           (20U)                                 
-#define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */
-#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk                
-#define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */
-#define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */
-#define GPIO_MODER_MODER11_Pos           (22U)                                 
-#define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */
-#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk                
-#define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */
-#define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */
-#define GPIO_MODER_MODER12_Pos           (24U)                                 
-#define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */
-#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk                
-#define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */
-#define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */
-#define GPIO_MODER_MODER13_Pos           (26U)                                 
-#define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */
-#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk                
-#define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */
-#define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */
-#define GPIO_MODER_MODER14_Pos           (28U)                                 
-#define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */
-#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk                
-#define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */
-#define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */
-#define GPIO_MODER_MODER15_Pos           (30U)                                 
-#define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */
-#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk                
-#define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */
-#define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */
-
-/* Legacy defines */
-#define GPIO_MODER_MODE0_Pos             GPIO_MODER_MODER0_Pos                                  
-#define GPIO_MODER_MODE0_Msk             GPIO_MODER_MODER0_Msk
-#define GPIO_MODER_MODE0                 GPIO_MODER_MODER0                 
-#define GPIO_MODER_MODE0_0               GPIO_MODER_MODER0_0
-#define GPIO_MODER_MODE0_1               GPIO_MODER_MODER0_1
-#define GPIO_MODER_MODE1_Pos             GPIO_MODER_MODER1_Pos                                  
-#define GPIO_MODER_MODE1_Msk             GPIO_MODER_MODER1_Msk
-#define GPIO_MODER_MODE1                 GPIO_MODER_MODER1                  
-#define GPIO_MODER_MODE1_0               GPIO_MODER_MODER1_0
-#define GPIO_MODER_MODE1_1               GPIO_MODER_MODER1_1
-#define GPIO_MODER_MODE2_Pos             GPIO_MODER_MODER2_Pos
-#define GPIO_MODER_MODE2_Msk             GPIO_MODER_MODER2_Msk
-#define GPIO_MODER_MODE2                 GPIO_MODER_MODER2                 
-#define GPIO_MODER_MODE2_0               GPIO_MODER_MODER2_0
-#define GPIO_MODER_MODE2_1               GPIO_MODER_MODER2_1
-#define GPIO_MODER_MODE3_Pos             GPIO_MODER_MODER3_Pos                                
-#define GPIO_MODER_MODE3_Msk             GPIO_MODER_MODER3_Msk
-#define GPIO_MODER_MODE3                 GPIO_MODER_MODER3
-#define GPIO_MODER_MODE3_0               GPIO_MODER_MODER3_0
-#define GPIO_MODER_MODE3_1               GPIO_MODER_MODER3_1
-#define GPIO_MODER_MODE4_Pos             GPIO_MODER_MODER4_Pos
-#define GPIO_MODER_MODE4_Msk             GPIO_MODER_MODER4_Msk
-#define GPIO_MODER_MODE4                 GPIO_MODER_MODER4
-#define GPIO_MODER_MODE4_0               GPIO_MODER_MODER4_0
-#define GPIO_MODER_MODE4_1               GPIO_MODER_MODER4_1
-#define GPIO_MODER_MODE5_Pos             GPIO_MODER_MODER5_Pos
-#define GPIO_MODER_MODE5_Msk             GPIO_MODER_MODER5_Msk
-#define GPIO_MODER_MODE5                 GPIO_MODER_MODER5
-#define GPIO_MODER_MODE5_0               GPIO_MODER_MODER5_0
-#define GPIO_MODER_MODE5_1               GPIO_MODER_MODER5_1
-#define GPIO_MODER_MODE6_Pos             GPIO_MODER_MODER6_Pos
-#define GPIO_MODER_MODE6_Msk             GPIO_MODER_MODER6_Msk
-#define GPIO_MODER_MODE6                 GPIO_MODER_MODER6
-#define GPIO_MODER_MODE6_0               GPIO_MODER_MODER6_0
-#define GPIO_MODER_MODE6_1               GPIO_MODER_MODER6_1
-#define GPIO_MODER_MODE7_Pos             GPIO_MODER_MODER7_Pos
-#define GPIO_MODER_MODE7_Msk             GPIO_MODER_MODER7_Msk
-#define GPIO_MODER_MODE7                 GPIO_MODER_MODER7
-#define GPIO_MODER_MODE7_0               GPIO_MODER_MODER7_0
-#define GPIO_MODER_MODE7_1               GPIO_MODER_MODER7_1
-#define GPIO_MODER_MODE8_Pos             GPIO_MODER_MODER8_Pos
-#define GPIO_MODER_MODE8_Msk             GPIO_MODER_MODER8_Msk
-#define GPIO_MODER_MODE8                 GPIO_MODER_MODER8
-#define GPIO_MODER_MODE8_0               GPIO_MODER_MODER8_0
-#define GPIO_MODER_MODE8_1               GPIO_MODER_MODER8_1
-#define GPIO_MODER_MODE9_Pos             GPIO_MODER_MODER9_Pos
-#define GPIO_MODER_MODE9_Msk             GPIO_MODER_MODER9_Msk
-#define GPIO_MODER_MODE9                 GPIO_MODER_MODER9
-#define GPIO_MODER_MODE9_0               GPIO_MODER_MODER9_0
-#define GPIO_MODER_MODE9_1               GPIO_MODER_MODER9_1
-#define GPIO_MODER_MODE10_Pos            GPIO_MODER_MODER10_Pos
-#define GPIO_MODER_MODE10_Msk            GPIO_MODER_MODER10_Msk
-#define GPIO_MODER_MODE10                GPIO_MODER_MODER10
-#define GPIO_MODER_MODE10_0              GPIO_MODER_MODER10_0
-#define GPIO_MODER_MODE10_1              GPIO_MODER_MODER10_1
-#define GPIO_MODER_MODE11_Pos            GPIO_MODER_MODER11_Pos
-#define GPIO_MODER_MODE11_Msk            GPIO_MODER_MODER11_Msk
-#define GPIO_MODER_MODE11                GPIO_MODER_MODER11
-#define GPIO_MODER_MODE11_0              GPIO_MODER_MODER11_0
-#define GPIO_MODER_MODE11_1              GPIO_MODER_MODER11_1
-#define GPIO_MODER_MODE12_Pos            GPIO_MODER_MODER12_Pos
-#define GPIO_MODER_MODE12_Msk            GPIO_MODER_MODER12_Msk
-#define GPIO_MODER_MODE12                GPIO_MODER_MODER12
-#define GPIO_MODER_MODE12_0              GPIO_MODER_MODER12_0
-#define GPIO_MODER_MODE12_1              GPIO_MODER_MODER12_1
-#define GPIO_MODER_MODE13_Pos            GPIO_MODER_MODER13_Pos
-#define GPIO_MODER_MODE13_Msk            GPIO_MODER_MODER13_Msk
-#define GPIO_MODER_MODE13                GPIO_MODER_MODER13
-#define GPIO_MODER_MODE13_0              GPIO_MODER_MODER13_0
-#define GPIO_MODER_MODE13_1              GPIO_MODER_MODER13_1
-#define GPIO_MODER_MODE14_Pos            GPIO_MODER_MODER14_Pos
-#define GPIO_MODER_MODE14_Msk            GPIO_MODER_MODER14_Msk
-#define GPIO_MODER_MODE14                GPIO_MODER_MODER14
-#define GPIO_MODER_MODE14_0              GPIO_MODER_MODER14_0
-#define GPIO_MODER_MODE14_1              GPIO_MODER_MODER14_1
-#define GPIO_MODER_MODE15_Pos            GPIO_MODER_MODER15_Pos
-#define GPIO_MODER_MODE15_Msk            GPIO_MODER_MODER15_Msk
-#define GPIO_MODER_MODE15                GPIO_MODER_MODER15
-#define GPIO_MODER_MODE15_0              GPIO_MODER_MODER15_0
-#define GPIO_MODER_MODE15_1              GPIO_MODER_MODER15_1
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT0_Pos              (0U)                                  
-#define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */
-#define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk                   
-#define GPIO_OTYPER_OT1_Pos              (1U)                                  
-#define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */
-#define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk                   
-#define GPIO_OTYPER_OT2_Pos              (2U)                                  
-#define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */
-#define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk                   
-#define GPIO_OTYPER_OT3_Pos              (3U)                                  
-#define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */
-#define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk                   
-#define GPIO_OTYPER_OT4_Pos              (4U)                                  
-#define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */
-#define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk                   
-#define GPIO_OTYPER_OT5_Pos              (5U)                                  
-#define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */
-#define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk                   
-#define GPIO_OTYPER_OT6_Pos              (6U)                                  
-#define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */
-#define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk                   
-#define GPIO_OTYPER_OT7_Pos              (7U)                                  
-#define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */
-#define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk                   
-#define GPIO_OTYPER_OT8_Pos              (8U)                                  
-#define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */
-#define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk                   
-#define GPIO_OTYPER_OT9_Pos              (9U)                                  
-#define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */
-#define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk                   
-#define GPIO_OTYPER_OT10_Pos             (10U)                                 
-#define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */
-#define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk                  
-#define GPIO_OTYPER_OT11_Pos             (11U)                                 
-#define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */
-#define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk                  
-#define GPIO_OTYPER_OT12_Pos             (12U)                                 
-#define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */
-#define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk                  
-#define GPIO_OTYPER_OT13_Pos             (13U)                                 
-#define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */
-#define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk                  
-#define GPIO_OTYPER_OT14_Pos             (14U)                                 
-#define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */
-#define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk                  
-#define GPIO_OTYPER_OT15_Pos             (15U)                                 
-#define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */
-#define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk                  
-
-/* Legacy defines */
-#define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0
-#define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1
-#define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2
-#define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3
-#define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4
-#define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5
-#define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6
-#define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7
-#define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8
-#define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9
-#define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10
-#define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11
-#define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12
-#define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13
-#define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14
-#define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDR_OSPEED0_Pos         (0U)                                  
-#define GPIO_OSPEEDR_OSPEED0_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */
-#define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk              
-#define GPIO_OSPEEDR_OSPEED0_0           (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */
-#define GPIO_OSPEEDR_OSPEED0_1           (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */
-#define GPIO_OSPEEDR_OSPEED1_Pos         (2U)                                  
-#define GPIO_OSPEEDR_OSPEED1_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */
-#define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk              
-#define GPIO_OSPEEDR_OSPEED1_0           (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */
-#define GPIO_OSPEEDR_OSPEED1_1           (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */
-#define GPIO_OSPEEDR_OSPEED2_Pos         (4U)                                  
-#define GPIO_OSPEEDR_OSPEED2_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */
-#define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk              
-#define GPIO_OSPEEDR_OSPEED2_0           (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */
-#define GPIO_OSPEEDR_OSPEED2_1           (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */
-#define GPIO_OSPEEDR_OSPEED3_Pos         (6U)                                  
-#define GPIO_OSPEEDR_OSPEED3_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */
-#define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk              
-#define GPIO_OSPEEDR_OSPEED3_0           (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */
-#define GPIO_OSPEEDR_OSPEED3_1           (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */
-#define GPIO_OSPEEDR_OSPEED4_Pos         (8U)                                  
-#define GPIO_OSPEEDR_OSPEED4_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */
-#define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk              
-#define GPIO_OSPEEDR_OSPEED4_0           (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */
-#define GPIO_OSPEEDR_OSPEED4_1           (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */
-#define GPIO_OSPEEDR_OSPEED5_Pos         (10U)                                 
-#define GPIO_OSPEEDR_OSPEED5_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */
-#define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk              
-#define GPIO_OSPEEDR_OSPEED5_0           (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */
-#define GPIO_OSPEEDR_OSPEED5_1           (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */
-#define GPIO_OSPEEDR_OSPEED6_Pos         (12U)                                 
-#define GPIO_OSPEEDR_OSPEED6_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */
-#define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk              
-#define GPIO_OSPEEDR_OSPEED6_0           (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */
-#define GPIO_OSPEEDR_OSPEED6_1           (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */
-#define GPIO_OSPEEDR_OSPEED7_Pos         (14U)                                 
-#define GPIO_OSPEEDR_OSPEED7_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */
-#define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk              
-#define GPIO_OSPEEDR_OSPEED7_0           (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */
-#define GPIO_OSPEEDR_OSPEED7_1           (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */
-#define GPIO_OSPEEDR_OSPEED8_Pos         (16U)                                 
-#define GPIO_OSPEEDR_OSPEED8_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */
-#define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk              
-#define GPIO_OSPEEDR_OSPEED8_0           (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */
-#define GPIO_OSPEEDR_OSPEED8_1           (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */
-#define GPIO_OSPEEDR_OSPEED9_Pos         (18U)                                 
-#define GPIO_OSPEEDR_OSPEED9_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */
-#define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk              
-#define GPIO_OSPEEDR_OSPEED9_0           (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */
-#define GPIO_OSPEEDR_OSPEED9_1           (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */
-#define GPIO_OSPEEDR_OSPEED10_Pos        (20U)                                 
-#define GPIO_OSPEEDR_OSPEED10_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */
-#define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk             
-#define GPIO_OSPEEDR_OSPEED10_0          (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */
-#define GPIO_OSPEEDR_OSPEED10_1          (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */
-#define GPIO_OSPEEDR_OSPEED11_Pos        (22U)                                 
-#define GPIO_OSPEEDR_OSPEED11_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */
-#define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk             
-#define GPIO_OSPEEDR_OSPEED11_0          (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */
-#define GPIO_OSPEEDR_OSPEED11_1          (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */
-#define GPIO_OSPEEDR_OSPEED12_Pos        (24U)                                 
-#define GPIO_OSPEEDR_OSPEED12_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */
-#define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk             
-#define GPIO_OSPEEDR_OSPEED12_0          (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */
-#define GPIO_OSPEEDR_OSPEED12_1          (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */
-#define GPIO_OSPEEDR_OSPEED13_Pos        (26U)                                 
-#define GPIO_OSPEEDR_OSPEED13_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */
-#define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk             
-#define GPIO_OSPEEDR_OSPEED13_0          (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */
-#define GPIO_OSPEEDR_OSPEED13_1          (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */
-#define GPIO_OSPEEDR_OSPEED14_Pos        (28U)                                 
-#define GPIO_OSPEEDR_OSPEED14_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */
-#define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk             
-#define GPIO_OSPEEDR_OSPEED14_0          (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */
-#define GPIO_OSPEEDR_OSPEED14_1          (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */
-#define GPIO_OSPEEDR_OSPEED15_Pos        (30U)                                 
-#define GPIO_OSPEEDR_OSPEED15_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */
-#define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk             
-#define GPIO_OSPEEDR_OSPEED15_0          (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */
-#define GPIO_OSPEEDR_OSPEED15_1          (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */
-
-/* Legacy defines */
-#define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDR_OSPEED0
-#define GPIO_OSPEEDER_OSPEEDR0_0         GPIO_OSPEEDR_OSPEED0_0
-#define GPIO_OSPEEDER_OSPEEDR0_1         GPIO_OSPEEDR_OSPEED0_1
-#define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDR_OSPEED1
-#define GPIO_OSPEEDER_OSPEEDR1_0         GPIO_OSPEEDR_OSPEED1_0
-#define GPIO_OSPEEDER_OSPEEDR1_1         GPIO_OSPEEDR_OSPEED1_1
-#define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDR_OSPEED2
-#define GPIO_OSPEEDER_OSPEEDR2_0         GPIO_OSPEEDR_OSPEED2_0
-#define GPIO_OSPEEDER_OSPEEDR2_1         GPIO_OSPEEDR_OSPEED2_1
-#define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDR_OSPEED3
-#define GPIO_OSPEEDER_OSPEEDR3_0         GPIO_OSPEEDR_OSPEED3_0
-#define GPIO_OSPEEDER_OSPEEDR3_1         GPIO_OSPEEDR_OSPEED3_1
-#define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDR_OSPEED4
-#define GPIO_OSPEEDER_OSPEEDR4_0         GPIO_OSPEEDR_OSPEED4_0
-#define GPIO_OSPEEDER_OSPEEDR4_1         GPIO_OSPEEDR_OSPEED4_1
-#define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDR_OSPEED5
-#define GPIO_OSPEEDER_OSPEEDR5_0         GPIO_OSPEEDR_OSPEED5_0
-#define GPIO_OSPEEDER_OSPEEDR5_1         GPIO_OSPEEDR_OSPEED5_1
-#define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDR_OSPEED6
-#define GPIO_OSPEEDER_OSPEEDR6_0         GPIO_OSPEEDR_OSPEED6_0
-#define GPIO_OSPEEDER_OSPEEDR6_1         GPIO_OSPEEDR_OSPEED6_1
-#define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDR_OSPEED7
-#define GPIO_OSPEEDER_OSPEEDR7_0         GPIO_OSPEEDR_OSPEED7_0
-#define GPIO_OSPEEDER_OSPEEDR7_1         GPIO_OSPEEDR_OSPEED7_1
-#define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDR_OSPEED8
-#define GPIO_OSPEEDER_OSPEEDR8_0         GPIO_OSPEEDR_OSPEED8_0
-#define GPIO_OSPEEDER_OSPEEDR8_1         GPIO_OSPEEDR_OSPEED8_1
-#define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDR_OSPEED9
-#define GPIO_OSPEEDER_OSPEEDR9_0         GPIO_OSPEEDR_OSPEED9_0
-#define GPIO_OSPEEDER_OSPEEDR9_1         GPIO_OSPEEDR_OSPEED9_1
-#define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDR_OSPEED10
-#define GPIO_OSPEEDER_OSPEEDR10_0        GPIO_OSPEEDR_OSPEED10_0
-#define GPIO_OSPEEDER_OSPEEDR10_1        GPIO_OSPEEDR_OSPEED10_1
-#define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDR_OSPEED11
-#define GPIO_OSPEEDER_OSPEEDR11_0        GPIO_OSPEEDR_OSPEED11_0
-#define GPIO_OSPEEDER_OSPEEDR11_1        GPIO_OSPEEDR_OSPEED11_1
-#define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDR_OSPEED12
-#define GPIO_OSPEEDER_OSPEEDR12_0        GPIO_OSPEEDR_OSPEED12_0
-#define GPIO_OSPEEDER_OSPEEDR12_1        GPIO_OSPEEDR_OSPEED12_1
-#define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDR_OSPEED13
-#define GPIO_OSPEEDER_OSPEEDR13_0        GPIO_OSPEEDR_OSPEED13_0
-#define GPIO_OSPEEDER_OSPEEDR13_1        GPIO_OSPEEDR_OSPEED13_1
-#define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDR_OSPEED14
-#define GPIO_OSPEEDER_OSPEEDR14_0        GPIO_OSPEEDR_OSPEED14_0
-#define GPIO_OSPEEDER_OSPEEDR14_1        GPIO_OSPEEDR_OSPEED14_1
-#define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDR_OSPEED15
-#define GPIO_OSPEEDER_OSPEEDR15_0        GPIO_OSPEEDR_OSPEED15_0
-#define GPIO_OSPEEDER_OSPEEDR15_1        GPIO_OSPEEDR_OSPEED15_1
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPD0_Pos             (0U)                                  
-#define GPIO_PUPDR_PUPD0_Msk             (0x3UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */
-#define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk                  
-#define GPIO_PUPDR_PUPD0_0               (0x1UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */
-#define GPIO_PUPDR_PUPD0_1               (0x2UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */
-#define GPIO_PUPDR_PUPD1_Pos             (2U)                                  
-#define GPIO_PUPDR_PUPD1_Msk             (0x3UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */
-#define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk                  
-#define GPIO_PUPDR_PUPD1_0               (0x1UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */
-#define GPIO_PUPDR_PUPD1_1               (0x2UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */
-#define GPIO_PUPDR_PUPD2_Pos             (4U)                                  
-#define GPIO_PUPDR_PUPD2_Msk             (0x3UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */
-#define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk                  
-#define GPIO_PUPDR_PUPD2_0               (0x1UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */
-#define GPIO_PUPDR_PUPD2_1               (0x2UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */
-#define GPIO_PUPDR_PUPD3_Pos             (6U)                                  
-#define GPIO_PUPDR_PUPD3_Msk             (0x3UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */
-#define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk                  
-#define GPIO_PUPDR_PUPD3_0               (0x1UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */
-#define GPIO_PUPDR_PUPD3_1               (0x2UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */
-#define GPIO_PUPDR_PUPD4_Pos             (8U)                                  
-#define GPIO_PUPDR_PUPD4_Msk             (0x3UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */
-#define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk                  
-#define GPIO_PUPDR_PUPD4_0               (0x1UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */
-#define GPIO_PUPDR_PUPD4_1               (0x2UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */
-#define GPIO_PUPDR_PUPD5_Pos             (10U)                                 
-#define GPIO_PUPDR_PUPD5_Msk             (0x3UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */
-#define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk                  
-#define GPIO_PUPDR_PUPD5_0               (0x1UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */
-#define GPIO_PUPDR_PUPD5_1               (0x2UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */
-#define GPIO_PUPDR_PUPD6_Pos             (12U)                                 
-#define GPIO_PUPDR_PUPD6_Msk             (0x3UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */
-#define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk                  
-#define GPIO_PUPDR_PUPD6_0               (0x1UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */
-#define GPIO_PUPDR_PUPD6_1               (0x2UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */
-#define GPIO_PUPDR_PUPD7_Pos             (14U)                                 
-#define GPIO_PUPDR_PUPD7_Msk             (0x3UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */
-#define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk                  
-#define GPIO_PUPDR_PUPD7_0               (0x1UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */
-#define GPIO_PUPDR_PUPD7_1               (0x2UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */
-#define GPIO_PUPDR_PUPD8_Pos             (16U)                                 
-#define GPIO_PUPDR_PUPD8_Msk             (0x3UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */
-#define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk                  
-#define GPIO_PUPDR_PUPD8_0               (0x1UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */
-#define GPIO_PUPDR_PUPD8_1               (0x2UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */
-#define GPIO_PUPDR_PUPD9_Pos             (18U)                                 
-#define GPIO_PUPDR_PUPD9_Msk             (0x3UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */
-#define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk                  
-#define GPIO_PUPDR_PUPD9_0               (0x1UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */
-#define GPIO_PUPDR_PUPD9_1               (0x2UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */
-#define GPIO_PUPDR_PUPD10_Pos            (20U)                                 
-#define GPIO_PUPDR_PUPD10_Msk            (0x3UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */
-#define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk                 
-#define GPIO_PUPDR_PUPD10_0              (0x1UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */
-#define GPIO_PUPDR_PUPD10_1              (0x2UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */
-#define GPIO_PUPDR_PUPD11_Pos            (22U)                                 
-#define GPIO_PUPDR_PUPD11_Msk            (0x3UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */
-#define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk                 
-#define GPIO_PUPDR_PUPD11_0              (0x1UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */
-#define GPIO_PUPDR_PUPD11_1              (0x2UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */
-#define GPIO_PUPDR_PUPD12_Pos            (24U)                                 
-#define GPIO_PUPDR_PUPD12_Msk            (0x3UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */
-#define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk                 
-#define GPIO_PUPDR_PUPD12_0              (0x1UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */
-#define GPIO_PUPDR_PUPD12_1              (0x2UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */
-#define GPIO_PUPDR_PUPD13_Pos            (26U)                                 
-#define GPIO_PUPDR_PUPD13_Msk            (0x3UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */
-#define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk                 
-#define GPIO_PUPDR_PUPD13_0              (0x1UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */
-#define GPIO_PUPDR_PUPD13_1              (0x2UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */
-#define GPIO_PUPDR_PUPD14_Pos            (28U)                                 
-#define GPIO_PUPDR_PUPD14_Msk            (0x3UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */
-#define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk                 
-#define GPIO_PUPDR_PUPD14_0              (0x1UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */
-#define GPIO_PUPDR_PUPD14_1              (0x2UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */
-#define GPIO_PUPDR_PUPD15_Pos            (30U)                                 
-#define GPIO_PUPDR_PUPD15_Msk            (0x3UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */
-#define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk                 
-#define GPIO_PUPDR_PUPD15_0              (0x1UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */
-#define GPIO_PUPDR_PUPD15_1              (0x2UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */
-
-/* Legacy defines */
-#define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPD0
-#define GPIO_PUPDR_PUPDR0_0              GPIO_PUPDR_PUPD0_0
-#define GPIO_PUPDR_PUPDR0_1              GPIO_PUPDR_PUPD0_1
-#define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPD1
-#define GPIO_PUPDR_PUPDR1_0              GPIO_PUPDR_PUPD1_0
-#define GPIO_PUPDR_PUPDR1_1              GPIO_PUPDR_PUPD1_1
-#define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPD2
-#define GPIO_PUPDR_PUPDR2_0              GPIO_PUPDR_PUPD2_0
-#define GPIO_PUPDR_PUPDR2_1              GPIO_PUPDR_PUPD2_1
-#define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPD3
-#define GPIO_PUPDR_PUPDR3_0              GPIO_PUPDR_PUPD3_0
-#define GPIO_PUPDR_PUPDR3_1              GPIO_PUPDR_PUPD3_1
-#define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPD4
-#define GPIO_PUPDR_PUPDR4_0              GPIO_PUPDR_PUPD4_0
-#define GPIO_PUPDR_PUPDR4_1              GPIO_PUPDR_PUPD4_1
-#define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPD5
-#define GPIO_PUPDR_PUPDR5_0              GPIO_PUPDR_PUPD5_0
-#define GPIO_PUPDR_PUPDR5_1              GPIO_PUPDR_PUPD5_1
-#define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPD6
-#define GPIO_PUPDR_PUPDR6_0              GPIO_PUPDR_PUPD6_0
-#define GPIO_PUPDR_PUPDR6_1              GPIO_PUPDR_PUPD6_1
-#define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPD7
-#define GPIO_PUPDR_PUPDR7_0              GPIO_PUPDR_PUPD7_0
-#define GPIO_PUPDR_PUPDR7_1              GPIO_PUPDR_PUPD7_1
-#define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPD8
-#define GPIO_PUPDR_PUPDR8_0              GPIO_PUPDR_PUPD8_0
-#define GPIO_PUPDR_PUPDR8_1              GPIO_PUPDR_PUPD8_1
-#define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPD9
-#define GPIO_PUPDR_PUPDR9_0              GPIO_PUPDR_PUPD9_0
-#define GPIO_PUPDR_PUPDR9_1              GPIO_PUPDR_PUPD9_1
-#define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPD10
-#define GPIO_PUPDR_PUPDR10_0             GPIO_PUPDR_PUPD10_0
-#define GPIO_PUPDR_PUPDR10_1             GPIO_PUPDR_PUPD10_1
-#define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPD11
-#define GPIO_PUPDR_PUPDR11_0             GPIO_PUPDR_PUPD11_0
-#define GPIO_PUPDR_PUPDR11_1             GPIO_PUPDR_PUPD11_1
-#define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPD12
-#define GPIO_PUPDR_PUPDR12_0             GPIO_PUPDR_PUPD12_0
-#define GPIO_PUPDR_PUPDR12_1             GPIO_PUPDR_PUPD12_1
-#define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPD13
-#define GPIO_PUPDR_PUPDR13_0             GPIO_PUPDR_PUPD13_0
-#define GPIO_PUPDR_PUPDR13_1             GPIO_PUPDR_PUPD13_1
-#define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPD14
-#define GPIO_PUPDR_PUPDR14_0             GPIO_PUPDR_PUPD14_0
-#define GPIO_PUPDR_PUPDR14_1             GPIO_PUPDR_PUPD14_1
-#define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPD15
-#define GPIO_PUPDR_PUPDR15_0             GPIO_PUPDR_PUPD15_0
-#define GPIO_PUPDR_PUPDR15_1             GPIO_PUPDR_PUPD15_1
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0_Pos                 (0U)                                  
-#define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */
-#define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk                      
-#define GPIO_IDR_ID1_Pos                 (1U)                                  
-#define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */
-#define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk                      
-#define GPIO_IDR_ID2_Pos                 (2U)                                  
-#define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */
-#define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk                      
-#define GPIO_IDR_ID3_Pos                 (3U)                                  
-#define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */
-#define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk                      
-#define GPIO_IDR_ID4_Pos                 (4U)                                  
-#define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */
-#define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk                      
-#define GPIO_IDR_ID5_Pos                 (5U)                                  
-#define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */
-#define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk                      
-#define GPIO_IDR_ID6_Pos                 (6U)                                  
-#define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */
-#define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk                      
-#define GPIO_IDR_ID7_Pos                 (7U)                                  
-#define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */
-#define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk                      
-#define GPIO_IDR_ID8_Pos                 (8U)                                  
-#define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */
-#define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk                      
-#define GPIO_IDR_ID9_Pos                 (9U)                                  
-#define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */
-#define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk                      
-#define GPIO_IDR_ID10_Pos                (10U)                                 
-#define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */
-#define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk                     
-#define GPIO_IDR_ID11_Pos                (11U)                                 
-#define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */
-#define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk                     
-#define GPIO_IDR_ID12_Pos                (12U)                                 
-#define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */
-#define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk                     
-#define GPIO_IDR_ID13_Pos                (13U)                                 
-#define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */
-#define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk                     
-#define GPIO_IDR_ID14_Pos                (14U)                                 
-#define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */
-#define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk                     
-#define GPIO_IDR_ID15_Pos                (15U)                                 
-#define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */
-#define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk                     
-
-/* Legacy defines */
-#define GPIO_IDR_IDR_0                   GPIO_IDR_ID0
-#define GPIO_IDR_IDR_1                   GPIO_IDR_ID1
-#define GPIO_IDR_IDR_2                   GPIO_IDR_ID2
-#define GPIO_IDR_IDR_3                   GPIO_IDR_ID3
-#define GPIO_IDR_IDR_4                   GPIO_IDR_ID4
-#define GPIO_IDR_IDR_5                   GPIO_IDR_ID5
-#define GPIO_IDR_IDR_6                   GPIO_IDR_ID6
-#define GPIO_IDR_IDR_7                   GPIO_IDR_ID7
-#define GPIO_IDR_IDR_8                   GPIO_IDR_ID8
-#define GPIO_IDR_IDR_9                   GPIO_IDR_ID9
-#define GPIO_IDR_IDR_10                  GPIO_IDR_ID10
-#define GPIO_IDR_IDR_11                  GPIO_IDR_ID11
-#define GPIO_IDR_IDR_12                  GPIO_IDR_ID12
-#define GPIO_IDR_IDR_13                  GPIO_IDR_ID13
-#define GPIO_IDR_IDR_14                  GPIO_IDR_ID14
-#define GPIO_IDR_IDR_15                  GPIO_IDR_ID15
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_OD0_Pos                 (0U)                                  
-#define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */
-#define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk                      
-#define GPIO_ODR_OD1_Pos                 (1U)                                  
-#define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */
-#define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk                      
-#define GPIO_ODR_OD2_Pos                 (2U)                                  
-#define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */
-#define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk                      
-#define GPIO_ODR_OD3_Pos                 (3U)                                  
-#define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */
-#define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk                      
-#define GPIO_ODR_OD4_Pos                 (4U)                                  
-#define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */
-#define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk                      
-#define GPIO_ODR_OD5_Pos                 (5U)                                  
-#define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */
-#define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk                      
-#define GPIO_ODR_OD6_Pos                 (6U)                                  
-#define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */
-#define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk                      
-#define GPIO_ODR_OD7_Pos                 (7U)                                  
-#define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */
-#define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk                      
-#define GPIO_ODR_OD8_Pos                 (8U)                                  
-#define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */
-#define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk                      
-#define GPIO_ODR_OD9_Pos                 (9U)                                  
-#define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */
-#define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk                      
-#define GPIO_ODR_OD10_Pos                (10U)                                 
-#define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */
-#define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk                     
-#define GPIO_ODR_OD11_Pos                (11U)                                 
-#define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */
-#define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk                     
-#define GPIO_ODR_OD12_Pos                (12U)                                 
-#define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */
-#define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk                     
-#define GPIO_ODR_OD13_Pos                (13U)                                 
-#define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */
-#define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk                     
-#define GPIO_ODR_OD14_Pos                (14U)                                 
-#define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */
-#define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk                     
-#define GPIO_ODR_OD15_Pos                (15U)                                 
-#define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */
-#define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk                     
-/* Legacy defines */
-#define GPIO_ODR_ODR_0                   GPIO_ODR_OD0
-#define GPIO_ODR_ODR_1                   GPIO_ODR_OD1
-#define GPIO_ODR_ODR_2                   GPIO_ODR_OD2
-#define GPIO_ODR_ODR_3                   GPIO_ODR_OD3
-#define GPIO_ODR_ODR_4                   GPIO_ODR_OD4
-#define GPIO_ODR_ODR_5                   GPIO_ODR_OD5
-#define GPIO_ODR_ODR_6                   GPIO_ODR_OD6
-#define GPIO_ODR_ODR_7                   GPIO_ODR_OD7
-#define GPIO_ODR_ODR_8                   GPIO_ODR_OD8
-#define GPIO_ODR_ODR_9                   GPIO_ODR_OD9
-#define GPIO_ODR_ODR_10                  GPIO_ODR_OD10
-#define GPIO_ODR_ODR_11                  GPIO_ODR_OD11
-#define GPIO_ODR_ODR_12                  GPIO_ODR_OD12
-#define GPIO_ODR_ODR_13                  GPIO_ODR_OD13
-#define GPIO_ODR_ODR_14                  GPIO_ODR_OD14
-#define GPIO_ODR_ODR_15                  GPIO_ODR_OD15
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS0_Pos                (0U)                                  
-#define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */
-#define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk                     
-#define GPIO_BSRR_BS1_Pos                (1U)                                  
-#define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */
-#define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk                     
-#define GPIO_BSRR_BS2_Pos                (2U)                                  
-#define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */
-#define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk                     
-#define GPIO_BSRR_BS3_Pos                (3U)                                  
-#define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */
-#define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk                     
-#define GPIO_BSRR_BS4_Pos                (4U)                                  
-#define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */
-#define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk                     
-#define GPIO_BSRR_BS5_Pos                (5U)                                  
-#define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */
-#define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk                     
-#define GPIO_BSRR_BS6_Pos                (6U)                                  
-#define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */
-#define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk                     
-#define GPIO_BSRR_BS7_Pos                (7U)                                  
-#define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */
-#define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk                     
-#define GPIO_BSRR_BS8_Pos                (8U)                                  
-#define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */
-#define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk                     
-#define GPIO_BSRR_BS9_Pos                (9U)                                  
-#define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */
-#define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk                     
-#define GPIO_BSRR_BS10_Pos               (10U)                                 
-#define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */
-#define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk                    
-#define GPIO_BSRR_BS11_Pos               (11U)                                 
-#define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */
-#define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk                    
-#define GPIO_BSRR_BS12_Pos               (12U)                                 
-#define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */
-#define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk                    
-#define GPIO_BSRR_BS13_Pos               (13U)                                 
-#define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */
-#define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk                    
-#define GPIO_BSRR_BS14_Pos               (14U)                                 
-#define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */
-#define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk                    
-#define GPIO_BSRR_BS15_Pos               (15U)                                 
-#define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */
-#define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk                    
-#define GPIO_BSRR_BR0_Pos                (16U)                                 
-#define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */
-#define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk                     
-#define GPIO_BSRR_BR1_Pos                (17U)                                 
-#define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */
-#define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk                     
-#define GPIO_BSRR_BR2_Pos                (18U)                                 
-#define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */
-#define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk                     
-#define GPIO_BSRR_BR3_Pos                (19U)                                 
-#define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */
-#define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk                     
-#define GPIO_BSRR_BR4_Pos                (20U)                                 
-#define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */
-#define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk                     
-#define GPIO_BSRR_BR5_Pos                (21U)                                 
-#define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */
-#define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk                     
-#define GPIO_BSRR_BR6_Pos                (22U)                                 
-#define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */
-#define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk                     
-#define GPIO_BSRR_BR7_Pos                (23U)                                 
-#define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */
-#define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk                     
-#define GPIO_BSRR_BR8_Pos                (24U)                                 
-#define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */
-#define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk                     
-#define GPIO_BSRR_BR9_Pos                (25U)                                 
-#define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */
-#define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk                     
-#define GPIO_BSRR_BR10_Pos               (26U)                                 
-#define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */
-#define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk                    
-#define GPIO_BSRR_BR11_Pos               (27U)                                 
-#define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */
-#define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk                    
-#define GPIO_BSRR_BR12_Pos               (28U)                                 
-#define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */
-#define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk                    
-#define GPIO_BSRR_BR13_Pos               (29U)                                 
-#define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */
-#define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk                    
-#define GPIO_BSRR_BR14_Pos               (30U)                                 
-#define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */
-#define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk                    
-#define GPIO_BSRR_BR15_Pos               (31U)                                 
-#define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */
-#define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk                    
-
-/* Legacy defines */
-#define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0
-#define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1
-#define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2
-#define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3
-#define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4
-#define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5
-#define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6
-#define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7
-#define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8
-#define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9
-#define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10
-#define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11
-#define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12
-#define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13
-#define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14
-#define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15
-#define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0
-#define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1
-#define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2
-#define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3
-#define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4
-#define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5
-#define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6
-#define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7
-#define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8
-#define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9
-#define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10
-#define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11
-#define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12
-#define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13
-#define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14
-#define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15
-#define GPIO_BRR_BR0                     GPIO_BSRR_BR0
-#define GPIO_BRR_BR0_Pos                 GPIO_BSRR_BR0_Pos
-#define GPIO_BRR_BR0_Msk                 GPIO_BSRR_BR0_Msk
-#define GPIO_BRR_BR1                     GPIO_BSRR_BR1
-#define GPIO_BRR_BR1_Pos                 GPIO_BSRR_BR1_Pos
-#define GPIO_BRR_BR1_Msk                 GPIO_BSRR_BR1_Msk
-#define GPIO_BRR_BR2                     GPIO_BSRR_BR2
-#define GPIO_BRR_BR2_Pos                 GPIO_BSRR_BR2_Pos
-#define GPIO_BRR_BR2_Msk                 GPIO_BSRR_BR2_Msk
-#define GPIO_BRR_BR3                     GPIO_BSRR_BR3
-#define GPIO_BRR_BR3_Pos                 GPIO_BSRR_BR3_Pos
-#define GPIO_BRR_BR3_Msk                 GPIO_BSRR_BR3_Msk
-#define GPIO_BRR_BR4                     GPIO_BSRR_BR4
-#define GPIO_BRR_BR4_Pos                 GPIO_BSRR_BR4_Pos
-#define GPIO_BRR_BR4_Msk                 GPIO_BSRR_BR4_Msk
-#define GPIO_BRR_BR5                     GPIO_BSRR_BR5
-#define GPIO_BRR_BR5_Pos                 GPIO_BSRR_BR5_Pos
-#define GPIO_BRR_BR5_Msk                 GPIO_BSRR_BR5_Msk
-#define GPIO_BRR_BR6                     GPIO_BSRR_BR6
-#define GPIO_BRR_BR6_Pos                 GPIO_BSRR_BR6_Pos
-#define GPIO_BRR_BR6_Msk                 GPIO_BSRR_BR6_Msk
-#define GPIO_BRR_BR7                     GPIO_BSRR_BR7
-#define GPIO_BRR_BR7_Pos                 GPIO_BSRR_BR7_Pos
-#define GPIO_BRR_BR7_Msk                 GPIO_BSRR_BR7_Msk
-#define GPIO_BRR_BR8                     GPIO_BSRR_BR8
-#define GPIO_BRR_BR8_Pos                 GPIO_BSRR_BR8_Pos
-#define GPIO_BRR_BR8_Msk                 GPIO_BSRR_BR8_Msk
-#define GPIO_BRR_BR9                     GPIO_BSRR_BR9
-#define GPIO_BRR_BR9_Pos                 GPIO_BSRR_BR9_Pos
-#define GPIO_BRR_BR9_Msk                 GPIO_BSRR_BR9_Msk
-#define GPIO_BRR_BR10                    GPIO_BSRR_BR10
-#define GPIO_BRR_BR10_Pos                GPIO_BSRR_BR10_Pos
-#define GPIO_BRR_BR10_Msk                GPIO_BSRR_BR10_Msk
-#define GPIO_BRR_BR11                    GPIO_BSRR_BR11
-#define GPIO_BRR_BR11_Pos                GPIO_BSRR_BR11_Pos
-#define GPIO_BRR_BR11_Msk                GPIO_BSRR_BR11_Msk
-#define GPIO_BRR_BR12                    GPIO_BSRR_BR12
-#define GPIO_BRR_BR12_Pos                GPIO_BSRR_BR12_Pos
-#define GPIO_BRR_BR12_Msk                GPIO_BSRR_BR12_Msk
-#define GPIO_BRR_BR13                    GPIO_BSRR_BR13
-#define GPIO_BRR_BR13_Pos                GPIO_BSRR_BR13_Pos
-#define GPIO_BRR_BR13_Msk                GPIO_BSRR_BR13_Msk
-#define GPIO_BRR_BR14                    GPIO_BSRR_BR14
-#define GPIO_BRR_BR14_Pos                GPIO_BSRR_BR14_Pos
-#define GPIO_BRR_BR14_Msk                GPIO_BSRR_BR14_Msk
-#define GPIO_BRR_BR15                    GPIO_BSRR_BR15
-#define GPIO_BRR_BR15_Pos                GPIO_BSRR_BR15_Pos
-#define GPIO_BRR_BR15_Msk                GPIO_BSRR_BR15_Msk 
-/****************** Bit definition for GPIO_LCKR register *********************/
-#define GPIO_LCKR_LCK0_Pos               (0U)                                  
-#define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */
-#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk                    
-#define GPIO_LCKR_LCK1_Pos               (1U)                                  
-#define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */
-#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk                    
-#define GPIO_LCKR_LCK2_Pos               (2U)                                  
-#define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */
-#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk                    
-#define GPIO_LCKR_LCK3_Pos               (3U)                                  
-#define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */
-#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk                    
-#define GPIO_LCKR_LCK4_Pos               (4U)                                  
-#define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */
-#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk                    
-#define GPIO_LCKR_LCK5_Pos               (5U)                                  
-#define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */
-#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk                    
-#define GPIO_LCKR_LCK6_Pos               (6U)                                  
-#define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */
-#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk                    
-#define GPIO_LCKR_LCK7_Pos               (7U)                                  
-#define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */
-#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk                    
-#define GPIO_LCKR_LCK8_Pos               (8U)                                  
-#define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */
-#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk                    
-#define GPIO_LCKR_LCK9_Pos               (9U)                                  
-#define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */
-#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk                    
-#define GPIO_LCKR_LCK10_Pos              (10U)                                 
-#define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */
-#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk                   
-#define GPIO_LCKR_LCK11_Pos              (11U)                                 
-#define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */
-#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk                   
-#define GPIO_LCKR_LCK12_Pos              (12U)                                 
-#define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */
-#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk                   
-#define GPIO_LCKR_LCK13_Pos              (13U)                                 
-#define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */
-#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk                   
-#define GPIO_LCKR_LCK14_Pos              (14U)                                 
-#define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */
-#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk                   
-#define GPIO_LCKR_LCK15_Pos              (15U)                                 
-#define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */
-#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk                   
-#define GPIO_LCKR_LCKK_Pos               (16U)                                 
-#define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */
-#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk                    
-/****************** Bit definition for GPIO_AFRL register *********************/
-#define GPIO_AFRL_AFSEL0_Pos             (0U)                                  
-#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */
-#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                  
-#define GPIO_AFRL_AFSEL0_0               (0x1UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */
-#define GPIO_AFRL_AFSEL0_1               (0x2UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */
-#define GPIO_AFRL_AFSEL0_2               (0x4UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */
-#define GPIO_AFRL_AFSEL0_3               (0x8UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */
-#define GPIO_AFRL_AFSEL1_Pos             (4U)                                  
-#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */
-#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                  
-#define GPIO_AFRL_AFSEL1_0               (0x1UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */
-#define GPIO_AFRL_AFSEL1_1               (0x2UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */
-#define GPIO_AFRL_AFSEL1_2               (0x4UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */
-#define GPIO_AFRL_AFSEL1_3               (0x8UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */
-#define GPIO_AFRL_AFSEL2_Pos             (8U)                                  
-#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */
-#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                  
-#define GPIO_AFRL_AFSEL2_0               (0x1UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */
-#define GPIO_AFRL_AFSEL2_1               (0x2UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */
-#define GPIO_AFRL_AFSEL2_2               (0x4UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */
-#define GPIO_AFRL_AFSEL2_3               (0x8UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */
-#define GPIO_AFRL_AFSEL3_Pos             (12U)                                 
-#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */
-#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                  
-#define GPIO_AFRL_AFSEL3_0               (0x1UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */
-#define GPIO_AFRL_AFSEL3_1               (0x2UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */
-#define GPIO_AFRL_AFSEL3_2               (0x4UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */
-#define GPIO_AFRL_AFSEL3_3               (0x8UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */
-#define GPIO_AFRL_AFSEL4_Pos             (16U)                                 
-#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */
-#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                  
-#define GPIO_AFRL_AFSEL4_0               (0x1UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */
-#define GPIO_AFRL_AFSEL4_1               (0x2UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */
-#define GPIO_AFRL_AFSEL4_2               (0x4UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */
-#define GPIO_AFRL_AFSEL4_3               (0x8UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */
-#define GPIO_AFRL_AFSEL5_Pos             (20U)                                 
-#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */
-#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                  
-#define GPIO_AFRL_AFSEL5_0               (0x1UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */
-#define GPIO_AFRL_AFSEL5_1               (0x2UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */
-#define GPIO_AFRL_AFSEL5_2               (0x4UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */
-#define GPIO_AFRL_AFSEL5_3               (0x8UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */
-#define GPIO_AFRL_AFSEL6_Pos             (24U)                                 
-#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */
-#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                  
-#define GPIO_AFRL_AFSEL6_0               (0x1UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */
-#define GPIO_AFRL_AFSEL6_1               (0x2UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */
-#define GPIO_AFRL_AFSEL6_2               (0x4UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */
-#define GPIO_AFRL_AFSEL6_3               (0x8UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */
-#define GPIO_AFRL_AFSEL7_Pos             (28U)                                 
-#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */
-#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                  
-#define GPIO_AFRL_AFSEL7_0               (0x1UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */
-#define GPIO_AFRL_AFSEL7_1               (0x2UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */
-#define GPIO_AFRL_AFSEL7_2               (0x4UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */
-#define GPIO_AFRL_AFSEL7_3               (0x8UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */
-
-/* Legacy defines */
-#define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFSEL0
-#define GPIO_AFRL_AFRL0_0                GPIO_AFRL_AFSEL0_0
-#define GPIO_AFRL_AFRL0_1                GPIO_AFRL_AFSEL0_1
-#define GPIO_AFRL_AFRL0_2                GPIO_AFRL_AFSEL0_2
-#define GPIO_AFRL_AFRL0_3                GPIO_AFRL_AFSEL0_3
-#define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFSEL1
-#define GPIO_AFRL_AFRL1_0                GPIO_AFRL_AFSEL1_0
-#define GPIO_AFRL_AFRL1_1                GPIO_AFRL_AFSEL1_1
-#define GPIO_AFRL_AFRL1_2                GPIO_AFRL_AFSEL1_2
-#define GPIO_AFRL_AFRL1_3                GPIO_AFRL_AFSEL1_3
-#define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFSEL2
-#define GPIO_AFRL_AFRL2_0                GPIO_AFRL_AFSEL2_0
-#define GPIO_AFRL_AFRL2_1                GPIO_AFRL_AFSEL2_1
-#define GPIO_AFRL_AFRL2_2                GPIO_AFRL_AFSEL2_2
-#define GPIO_AFRL_AFRL2_3                GPIO_AFRL_AFSEL2_3
-#define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFSEL3
-#define GPIO_AFRL_AFRL3_0                GPIO_AFRL_AFSEL3_0
-#define GPIO_AFRL_AFRL3_1                GPIO_AFRL_AFSEL3_1
-#define GPIO_AFRL_AFRL3_2                GPIO_AFRL_AFSEL3_2
-#define GPIO_AFRL_AFRL3_3                GPIO_AFRL_AFSEL3_3
-#define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFSEL4
-#define GPIO_AFRL_AFRL4_0                GPIO_AFRL_AFSEL4_0
-#define GPIO_AFRL_AFRL4_1                GPIO_AFRL_AFSEL4_1
-#define GPIO_AFRL_AFRL4_2                GPIO_AFRL_AFSEL4_2
-#define GPIO_AFRL_AFRL4_3                GPIO_AFRL_AFSEL4_3
-#define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFSEL5
-#define GPIO_AFRL_AFRL5_0                GPIO_AFRL_AFSEL5_0
-#define GPIO_AFRL_AFRL5_1                GPIO_AFRL_AFSEL5_1
-#define GPIO_AFRL_AFRL5_2                GPIO_AFRL_AFSEL5_2
-#define GPIO_AFRL_AFRL5_3                GPIO_AFRL_AFSEL5_3
-#define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFSEL6
-#define GPIO_AFRL_AFRL6_0                GPIO_AFRL_AFSEL6_0
-#define GPIO_AFRL_AFRL6_1                GPIO_AFRL_AFSEL6_1
-#define GPIO_AFRL_AFRL6_2                GPIO_AFRL_AFSEL6_2
-#define GPIO_AFRL_AFRL6_3                GPIO_AFRL_AFSEL6_3
-#define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFSEL7
-#define GPIO_AFRL_AFRL7_0                GPIO_AFRL_AFSEL7_0
-#define GPIO_AFRL_AFRL7_1                GPIO_AFRL_AFSEL7_1
-#define GPIO_AFRL_AFRL7_2                GPIO_AFRL_AFSEL7_2
-#define GPIO_AFRL_AFRL7_3                GPIO_AFRL_AFSEL7_3
-
-/****************** Bit definition for GPIO_AFRH register *********************/
-#define GPIO_AFRH_AFSEL8_Pos             (0U)                                  
-#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */
-#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                  
-#define GPIO_AFRH_AFSEL8_0               (0x1UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */
-#define GPIO_AFRH_AFSEL8_1               (0x2UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */
-#define GPIO_AFRH_AFSEL8_2               (0x4UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */
-#define GPIO_AFRH_AFSEL8_3               (0x8UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */
-#define GPIO_AFRH_AFSEL9_Pos             (4U)                                  
-#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */
-#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                  
-#define GPIO_AFRH_AFSEL9_0               (0x1UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */
-#define GPIO_AFRH_AFSEL9_1               (0x2UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */
-#define GPIO_AFRH_AFSEL9_2               (0x4UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */
-#define GPIO_AFRH_AFSEL9_3               (0x8UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */
-#define GPIO_AFRH_AFSEL10_Pos            (8U)                                  
-#define GPIO_AFRH_AFSEL10_Msk            (0xFUL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */
-#define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk                 
-#define GPIO_AFRH_AFSEL10_0              (0x1UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */
-#define GPIO_AFRH_AFSEL10_1              (0x2UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */
-#define GPIO_AFRH_AFSEL10_2              (0x4UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */
-#define GPIO_AFRH_AFSEL10_3              (0x8UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */
-#define GPIO_AFRH_AFSEL11_Pos            (12U)                                 
-#define GPIO_AFRH_AFSEL11_Msk            (0xFUL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */
-#define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk                 
-#define GPIO_AFRH_AFSEL11_0              (0x1UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */
-#define GPIO_AFRH_AFSEL11_1              (0x2UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */
-#define GPIO_AFRH_AFSEL11_2              (0x4UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */
-#define GPIO_AFRH_AFSEL11_3              (0x8UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */
-#define GPIO_AFRH_AFSEL12_Pos            (16U)                                 
-#define GPIO_AFRH_AFSEL12_Msk            (0xFUL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */
-#define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk                 
-#define GPIO_AFRH_AFSEL12_0              (0x1UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */
-#define GPIO_AFRH_AFSEL12_1              (0x2UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */
-#define GPIO_AFRH_AFSEL12_2              (0x4UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */
-#define GPIO_AFRH_AFSEL12_3              (0x8UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */
-#define GPIO_AFRH_AFSEL13_Pos            (20U)                                 
-#define GPIO_AFRH_AFSEL13_Msk            (0xFUL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */
-#define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk                 
-#define GPIO_AFRH_AFSEL13_0              (0x1UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */
-#define GPIO_AFRH_AFSEL13_1              (0x2UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */
-#define GPIO_AFRH_AFSEL13_2              (0x4UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */
-#define GPIO_AFRH_AFSEL13_3              (0x8UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */
-#define GPIO_AFRH_AFSEL14_Pos            (24U)                                 
-#define GPIO_AFRH_AFSEL14_Msk            (0xFUL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */
-#define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk                 
-#define GPIO_AFRH_AFSEL14_0              (0x1UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */
-#define GPIO_AFRH_AFSEL14_1              (0x2UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */
-#define GPIO_AFRH_AFSEL14_2              (0x4UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */
-#define GPIO_AFRH_AFSEL14_3              (0x8UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */
-#define GPIO_AFRH_AFSEL15_Pos            (28U)                                 
-#define GPIO_AFRH_AFSEL15_Msk            (0xFUL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */
-#define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk                 
-#define GPIO_AFRH_AFSEL15_0              (0x1UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */
-#define GPIO_AFRH_AFSEL15_1              (0x2UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */
-#define GPIO_AFRH_AFSEL15_2              (0x4UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */
-#define GPIO_AFRH_AFSEL15_3              (0x8UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */
-
-/* Legacy defines */
-#define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFSEL8
-#define GPIO_AFRH_AFRH0_0                GPIO_AFRH_AFSEL8_0
-#define GPIO_AFRH_AFRH0_1                GPIO_AFRH_AFSEL8_1
-#define GPIO_AFRH_AFRH0_2                GPIO_AFRH_AFSEL8_2
-#define GPIO_AFRH_AFRH0_3                GPIO_AFRH_AFSEL8_3
-#define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFSEL9
-#define GPIO_AFRH_AFRH1_0                GPIO_AFRH_AFSEL9_0
-#define GPIO_AFRH_AFRH1_1                GPIO_AFRH_AFSEL9_1
-#define GPIO_AFRH_AFRH1_2                GPIO_AFRH_AFSEL9_2
-#define GPIO_AFRH_AFRH1_3                GPIO_AFRH_AFSEL9_3
-#define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFSEL10
-#define GPIO_AFRH_AFRH2_0                GPIO_AFRH_AFSEL10_0
-#define GPIO_AFRH_AFRH2_1                GPIO_AFRH_AFSEL10_1
-#define GPIO_AFRH_AFRH2_2                GPIO_AFRH_AFSEL10_2
-#define GPIO_AFRH_AFRH2_3                GPIO_AFRH_AFSEL10_3
-#define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFSEL11
-#define GPIO_AFRH_AFRH3_0                GPIO_AFRH_AFSEL11_0
-#define GPIO_AFRH_AFRH3_1                GPIO_AFRH_AFSEL11_1
-#define GPIO_AFRH_AFRH3_2                GPIO_AFRH_AFSEL11_2
-#define GPIO_AFRH_AFRH3_3                GPIO_AFRH_AFSEL11_3
-#define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFSEL12
-#define GPIO_AFRH_AFRH4_0                GPIO_AFRH_AFSEL12_0
-#define GPIO_AFRH_AFRH4_1                GPIO_AFRH_AFSEL12_1
-#define GPIO_AFRH_AFRH4_2                GPIO_AFRH_AFSEL12_2
-#define GPIO_AFRH_AFRH4_3                GPIO_AFRH_AFSEL12_3
-#define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFSEL13
-#define GPIO_AFRH_AFRH5_0                GPIO_AFRH_AFSEL13_0
-#define GPIO_AFRH_AFRH5_1                GPIO_AFRH_AFSEL13_1
-#define GPIO_AFRH_AFRH5_2                GPIO_AFRH_AFSEL13_2
-#define GPIO_AFRH_AFRH5_3                GPIO_AFRH_AFSEL13_3
-#define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFSEL14
-#define GPIO_AFRH_AFRH6_0                GPIO_AFRH_AFSEL14_0
-#define GPIO_AFRH_AFRH6_1                GPIO_AFRH_AFSEL14_1
-#define GPIO_AFRH_AFRH6_2                GPIO_AFRH_AFSEL14_2
-#define GPIO_AFRH_AFRH6_3                GPIO_AFRH_AFSEL14_3
-#define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFSEL15
-#define GPIO_AFRH_AFRH7_0                GPIO_AFRH_AFSEL15_0
-#define GPIO_AFRH_AFRH7_1                GPIO_AFRH_AFSEL15_1
-#define GPIO_AFRH_AFRH7_2                GPIO_AFRH_AFSEL15_2
-#define GPIO_AFRH_AFRH7_3                GPIO_AFRH_AFSEL15_3
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Inter-integrated Circuit Interface                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define I2C_CR1_PE_Pos            (0U)                                         
-#define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */
-#define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */
-#define I2C_CR1_SMBUS_Pos         (1U)                                         
-#define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */
-#define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */
-#define I2C_CR1_SMBTYPE_Pos       (3U)                                         
-#define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */
-#define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */
-#define I2C_CR1_ENARP_Pos         (4U)                                         
-#define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */
-#define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */
-#define I2C_CR1_ENPEC_Pos         (5U)                                         
-#define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */
-#define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */
-#define I2C_CR1_ENGC_Pos          (6U)                                         
-#define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */
-#define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */
-#define I2C_CR1_NOSTRETCH_Pos     (7U)                                         
-#define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */
-#define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */
-#define I2C_CR1_START_Pos         (8U)                                         
-#define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */
-#define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */
-#define I2C_CR1_STOP_Pos          (9U)                                         
-#define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */
-#define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */
-#define I2C_CR1_ACK_Pos           (10U)                                        
-#define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */
-#define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */
-#define I2C_CR1_POS_Pos           (11U)                                        
-#define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */
-#define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */
-#define I2C_CR1_PEC_Pos           (12U)                                        
-#define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */
-#define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */
-#define I2C_CR1_ALERT_Pos         (13U)                                        
-#define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */
-#define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */
-#define I2C_CR1_SWRST_Pos         (15U)                                        
-#define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */
-#define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_FREQ_Pos          (0U)                                         
-#define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */
-#define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
-#define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */
-#define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */
-#define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */
-#define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */
-#define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */
-#define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */
-
-#define I2C_CR2_ITERREN_Pos       (8U)                                         
-#define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */
-#define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */
-#define I2C_CR2_ITEVTEN_Pos       (9U)                                         
-#define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */
-#define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */
-#define I2C_CR2_ITBUFEN_Pos       (10U)                                        
-#define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */
-#define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */
-#define I2C_CR2_DMAEN_Pos         (11U)                                        
-#define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */
-#define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */
-#define I2C_CR2_LAST_Pos          (12U)                                        
-#define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */
-#define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */
-#define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */
-
-#define I2C_OAR1_ADD0_Pos         (0U)                                         
-#define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */
-#define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */
-#define I2C_OAR1_ADD1_Pos         (1U)                                         
-#define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */
-#define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */
-#define I2C_OAR1_ADD2_Pos         (2U)                                         
-#define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */
-#define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */
-#define I2C_OAR1_ADD3_Pos         (3U)                                         
-#define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */
-#define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */
-#define I2C_OAR1_ADD4_Pos         (4U)                                         
-#define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */
-#define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */
-#define I2C_OAR1_ADD5_Pos         (5U)                                         
-#define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */
-#define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */
-#define I2C_OAR1_ADD6_Pos         (6U)                                         
-#define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */
-#define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */
-#define I2C_OAR1_ADD7_Pos         (7U)                                         
-#define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */
-#define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */
-#define I2C_OAR1_ADD8_Pos         (8U)                                         
-#define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */
-#define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */
-#define I2C_OAR1_ADD9_Pos         (9U)                                         
-#define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */
-#define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */
-
-#define I2C_OAR1_ADDMODE_Pos      (15U)                                        
-#define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */
-#define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define I2C_OAR2_ENDUAL_Pos       (0U)                                         
-#define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */
-#define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */
-#define I2C_OAR2_ADD2_Pos         (1U)                                         
-#define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */
-#define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define I2C_DR_DR_Pos             (0U)                                         
-#define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */
-#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define I2C_SR1_SB_Pos            (0U)                                         
-#define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */
-#define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */
-#define I2C_SR1_ADDR_Pos          (1U)                                         
-#define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */
-#define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */
-#define I2C_SR1_BTF_Pos           (2U)                                         
-#define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */
-#define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */
-#define I2C_SR1_ADD10_Pos         (3U)                                         
-#define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */
-#define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */
-#define I2C_SR1_STOPF_Pos         (4U)                                         
-#define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */
-#define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */
-#define I2C_SR1_RXNE_Pos          (6U)                                         
-#define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */
-#define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */
-#define I2C_SR1_TXE_Pos           (7U)                                         
-#define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */
-#define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */
-#define I2C_SR1_BERR_Pos          (8U)                                         
-#define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */
-#define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */
-#define I2C_SR1_ARLO_Pos          (9U)                                         
-#define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */
-#define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */
-#define I2C_SR1_AF_Pos            (10U)                                        
-#define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */
-#define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */
-#define I2C_SR1_OVR_Pos           (11U)                                        
-#define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */
-#define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */
-#define I2C_SR1_PECERR_Pos        (12U)                                        
-#define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */
-#define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */
-#define I2C_SR1_TIMEOUT_Pos       (14U)                                        
-#define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */
-#define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */
-#define I2C_SR1_SMBALERT_Pos      (15U)                                        
-#define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */
-#define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define I2C_SR2_MSL_Pos           (0U)                                         
-#define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */
-#define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */
-#define I2C_SR2_BUSY_Pos          (1U)                                         
-#define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */
-#define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */
-#define I2C_SR2_TRA_Pos           (2U)                                         
-#define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */
-#define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */
-#define I2C_SR2_GENCALL_Pos       (4U)                                         
-#define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */
-#define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */
-#define I2C_SR2_SMBDEFAULT_Pos    (5U)                                         
-#define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */
-#define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */
-#define I2C_SR2_SMBHOST_Pos       (6U)                                         
-#define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */
-#define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */
-#define I2C_SR2_DUALF_Pos         (7U)                                         
-#define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */
-#define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */
-#define I2C_SR2_PEC_Pos           (8U)                                         
-#define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */
-#define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define I2C_CCR_CCR_Pos           (0U)                                         
-#define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */
-#define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CCR_DUTY_Pos          (14U)                                        
-#define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */
-#define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */
-#define I2C_CCR_FS_Pos            (15U)                                        
-#define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */
-#define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define I2C_TRISE_TRISE_Pos       (0U)                                         
-#define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */
-#define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Independent WATCHDOG                             */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY_Pos     (0U)                                               
-#define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */
-#define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR_Pos      (0U)                                               
-#define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */
-#define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */
-#define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x01 */
-#define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x02 */
-#define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x04 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL_Pos     (0U)                                               
-#define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */
-#define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU_Pos     (0U)                                               
-#define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */
-#define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */
-#define IWDG_SR_RVU_Pos     (1U)                                               
-#define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */
-#define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */
-
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                             Power Control                                  */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPDS_Pos        (0U)                                            
-#define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */
-#define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */
-#define PWR_CR_PDDS_Pos        (1U)                                            
-#define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */
-#define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */
-#define PWR_CR_CWUF_Pos        (2U)                                            
-#define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */
-#define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */
-#define PWR_CR_CSBF_Pos        (3U)                                            
-#define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */
-#define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */
-#define PWR_CR_PVDE_Pos        (4U)                                            
-#define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */
-#define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */
-
-#define PWR_CR_PLS_Pos         (5U)                                            
-#define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */
-#define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */
-#define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */
-#define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */
-#define PWR_CR_DBP_Pos         (8U)                                            
-#define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */
-#define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */
-#define PWR_CR_FPDS_Pos        (9U)                                            
-#define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */
-#define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */
-#define PWR_CR_VOS_Pos         (14U)                                           
-#define PWR_CR_VOS_Msk         (0x1UL << PWR_CR_VOS_Pos)                        /*!< 0x00004000 */
-#define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS bit (Regulator voltage scaling output selection) */
-
-/* Legacy define */
-#define  PWR_CR_PMODE                        PWR_CR_VOS
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF_Pos        (0U)                                            
-#define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */
-#define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */
-#define PWR_CSR_SBF_Pos        (1U)                                            
-#define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */
-#define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */
-#define PWR_CSR_PVDO_Pos       (2U)                                            
-#define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */
-#define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */
-#define PWR_CSR_BRR_Pos        (3U)                                            
-#define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */
-#define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */
-#define PWR_CSR_EWUP_Pos       (8U)                                            
-#define PWR_CSR_EWUP_Msk       (0x1UL << PWR_CSR_EWUP_Pos)                      /*!< 0x00000100 */
-#define PWR_CSR_EWUP           PWR_CSR_EWUP_Msk                                /*!< Enable WKUP pin                                  */
-#define PWR_CSR_BRE_Pos        (9U)                                            
-#define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */
-#define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */
-#define PWR_CSR_VOSRDY_Pos     (14U)                                           
-#define PWR_CSR_VOSRDY_Msk     (0x1UL << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */
-#define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */
-
-/* Legacy define */
-#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION_Pos                   (0U)                                
-#define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */
-#define RCC_CR_HSION                       RCC_CR_HSION_Msk                    
-#define RCC_CR_HSIRDY_Pos                  (1U)                                
-#define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */
-#define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk                   
-
-#define RCC_CR_HSITRIM_Pos                 (3U)                                
-#define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */
-#define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk                  
-#define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */
-#define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */
-#define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */
-#define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */
-#define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */
-
-#define RCC_CR_HSICAL_Pos                  (8U)                                
-#define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */
-#define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk                   
-#define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */
-#define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */
-#define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */
-#define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */
-#define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */
-#define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */
-#define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */
-#define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */
-
-#define RCC_CR_HSEON_Pos                   (16U)                               
-#define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */
-#define RCC_CR_HSEON                       RCC_CR_HSEON_Msk                    
-#define RCC_CR_HSERDY_Pos                  (17U)                               
-#define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */
-#define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk                   
-#define RCC_CR_HSEBYP_Pos                  (18U)                               
-#define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */
-#define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk                   
-#define RCC_CR_CSSON_Pos                   (19U)                               
-#define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */
-#define RCC_CR_CSSON                       RCC_CR_CSSON_Msk                    
-#define RCC_CR_PLLON_Pos                   (24U)                               
-#define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */
-#define RCC_CR_PLLON                       RCC_CR_PLLON_Msk                    
-#define RCC_CR_PLLRDY_Pos                  (25U)                               
-#define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */
-#define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk                   
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
- */
-#define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */
-
-#define RCC_CR_PLLI2SON_Pos                (26U)                               
-#define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */
-#define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk                 
-#define RCC_CR_PLLI2SRDY_Pos               (27U)                               
-#define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */
-#define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk                
-
-/********************  Bit definition for RCC_PLLCFGR register  ***************/
-#define RCC_PLLCFGR_PLLM_Pos               (0U)                                
-#define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */
-#define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk                
-#define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */
-#define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */
-#define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */
-#define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */
-#define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */
-#define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */
-
-#define RCC_PLLCFGR_PLLN_Pos               (6U)                                
-#define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */
-#define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk                
-#define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */
-#define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */
-#define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */
-#define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */
-#define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */
-#define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */
-#define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */
-#define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */
-#define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */
-
-#define RCC_PLLCFGR_PLLP_Pos               (16U)                               
-#define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */
-#define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk                
-#define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */
-#define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */
-
-#define RCC_PLLCFGR_PLLSRC_Pos             (22U)                               
-#define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */
-#define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk              
-#define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)                               
-#define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
-#define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk          
-#define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U                         
-
-#define RCC_PLLCFGR_PLLQ_Pos               (24U)                               
-#define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */
-#define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk                
-#define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */
-#define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */
-#define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */
-#define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */
-
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW_Pos                    (0U)                                
-#define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */
-#define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
-#define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
-
-#define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS_Pos                   (2U)                                
-#define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */
-#define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */
-#define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
-
-#define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */
-#define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */
-#define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE_Pos                  (4U)                                
-#define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */
-#define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */
-#define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */
-#define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */
-#define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */
-
-#define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */
-#define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */
-#define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */
-#define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */
-#define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */
-#define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */
-#define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1_Pos                 (10U)                               
-#define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */
-#define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */
-#define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */
-#define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */
-
-#define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */
-#define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */
-#define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */
-#define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */
-#define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2_Pos                 (13U)                               
-#define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */
-#define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */
-#define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */
-#define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */
-
-#define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */
-#define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */
-#define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */
-#define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */
-#define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */
-
-/*!< RTCPRE configuration */
-#define RCC_CFGR_RTCPRE_Pos                (16U)                               
-#define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */
-#define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk                 
-#define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */
-#define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */
-#define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */
-#define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */
-#define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */
-
-/*!< MCO1 configuration */
-#define RCC_CFGR_MCO1_Pos                  (21U)                               
-#define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */
-#define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk                   
-#define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */
-#define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */
-
-#define RCC_CFGR_I2SSRC_Pos                (23U)                               
-#define RCC_CFGR_I2SSRC_Msk                (0x1UL << RCC_CFGR_I2SSRC_Pos)       /*!< 0x00800000 */
-#define RCC_CFGR_I2SSRC                    RCC_CFGR_I2SSRC_Msk                 
-
-#define RCC_CFGR_MCO1PRE_Pos               (24U)                               
-#define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */
-#define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk                
-#define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */
-#define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */
-#define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */
-
-#define RCC_CFGR_MCO2PRE_Pos               (27U)                               
-#define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */
-#define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk                
-#define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */
-#define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */
-#define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */
-
-#define RCC_CFGR_MCO2_Pos                  (30U)                               
-#define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */
-#define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk                   
-#define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */
-#define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */
-
-/********************  Bit definition for RCC_CIR register  *******************/
-#define RCC_CIR_LSIRDYF_Pos                (0U)                                
-#define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */
-#define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk                 
-#define RCC_CIR_LSERDYF_Pos                (1U)                                
-#define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */
-#define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk                 
-#define RCC_CIR_HSIRDYF_Pos                (2U)                                
-#define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */
-#define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk                 
-#define RCC_CIR_HSERDYF_Pos                (3U)                                
-#define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */
-#define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk                 
-#define RCC_CIR_PLLRDYF_Pos                (4U)                                
-#define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */
-#define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk                 
-#define RCC_CIR_PLLI2SRDYF_Pos             (5U)                                
-#define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */
-#define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk              
-
-#define RCC_CIR_CSSF_Pos                   (7U)                                
-#define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */
-#define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk                    
-#define RCC_CIR_LSIRDYIE_Pos               (8U)                                
-#define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */
-#define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk                
-#define RCC_CIR_LSERDYIE_Pos               (9U)                                
-#define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */
-#define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk                
-#define RCC_CIR_HSIRDYIE_Pos               (10U)                               
-#define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */
-#define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk                
-#define RCC_CIR_HSERDYIE_Pos               (11U)                               
-#define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */
-#define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk                
-#define RCC_CIR_PLLRDYIE_Pos               (12U)                               
-#define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */
-#define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk                
-#define RCC_CIR_PLLI2SRDYIE_Pos            (13U)                               
-#define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */
-#define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk             
-
-#define RCC_CIR_LSIRDYC_Pos                (16U)                               
-#define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */
-#define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk                 
-#define RCC_CIR_LSERDYC_Pos                (17U)                               
-#define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */
-#define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk                 
-#define RCC_CIR_HSIRDYC_Pos                (18U)                               
-#define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */
-#define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk                 
-#define RCC_CIR_HSERDYC_Pos                (19U)                               
-#define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */
-#define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk                 
-#define RCC_CIR_PLLRDYC_Pos                (20U)                               
-#define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */
-#define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk                 
-#define RCC_CIR_PLLI2SRDYC_Pos             (21U)                               
-#define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */
-#define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk              
-
-#define RCC_CIR_CSSC_Pos                   (23U)                               
-#define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */
-#define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk                    
-
-/********************  Bit definition for RCC_AHB1RSTR register  **************/
-#define RCC_AHB1RSTR_GPIOARST_Pos          (0U)                                
-#define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
-#define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk           
-#define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)                                
-#define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
-#define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk           
-#define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)                                
-#define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
-#define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk           
-#define RCC_AHB1RSTR_GPIODRST_Pos          (3U)                                
-#define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
-#define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk           
-#define RCC_AHB1RSTR_GPIOERST_Pos          (4U)                                
-#define RCC_AHB1RSTR_GPIOERST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
-#define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk           
-#define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)                                
-#define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
-#define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk           
-#define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)                                
-#define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
-#define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk           
-#define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)                                
-#define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
-#define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk           
-#define RCC_AHB1RSTR_GPIOIRST_Pos          (8U)                                
-#define RCC_AHB1RSTR_GPIOIRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
-#define RCC_AHB1RSTR_GPIOIRST              RCC_AHB1RSTR_GPIOIRST_Msk           
-#define RCC_AHB1RSTR_CRCRST_Pos            (12U)                               
-#define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */
-#define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk             
-#define RCC_AHB1RSTR_DMA1RST_Pos           (21U)                               
-#define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */
-#define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk            
-#define RCC_AHB1RSTR_DMA2RST_Pos           (22U)                               
-#define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */
-#define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk            
-#define RCC_AHB1RSTR_ETHMACRST_Pos         (25U)                               
-#define RCC_AHB1RSTR_ETHMACRST_Msk         (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
-#define RCC_AHB1RSTR_ETHMACRST             RCC_AHB1RSTR_ETHMACRST_Msk          
-#define RCC_AHB1RSTR_OTGHRST_Pos           (29U)                               
-#define RCC_AHB1RSTR_OTGHRST_Msk           (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */
-#define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk            
-
-/********************  Bit definition for RCC_AHB2RSTR register  **************/
-#define RCC_AHB2RSTR_DCMIRST_Pos           (0U)                                
-#define RCC_AHB2RSTR_DCMIRST_Msk           (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)  /*!< 0x00000001 */
-#define RCC_AHB2RSTR_DCMIRST               RCC_AHB2RSTR_DCMIRST_Msk            
-#define RCC_AHB2RSTR_RNGRST_Pos            (6U)                                
-#define RCC_AHB2RSTR_RNGRST_Msk            (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */
-#define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk             
-#define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)                                
-#define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
-#define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk           
-/********************  Bit definition for RCC_AHB3RSTR register  **************/
-#define RCC_AHB3RSTR_FSMCRST_Pos           (0U)                                
-#define RCC_AHB3RSTR_FSMCRST_Msk           (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)  /*!< 0x00000001 */
-#define RCC_AHB3RSTR_FSMCRST               RCC_AHB3RSTR_FSMCRST_Msk            
-
-
-/********************  Bit definition for RCC_APB1RSTR register  **************/
-#define RCC_APB1RSTR_TIM2RST_Pos           (0U)                                
-#define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */
-#define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk            
-#define RCC_APB1RSTR_TIM3RST_Pos           (1U)                                
-#define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */
-#define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk            
-#define RCC_APB1RSTR_TIM4RST_Pos           (2U)                                
-#define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */
-#define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk            
-#define RCC_APB1RSTR_TIM5RST_Pos           (3U)                                
-#define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */
-#define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk            
-#define RCC_APB1RSTR_TIM6RST_Pos           (4U)                                
-#define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */
-#define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk            
-#define RCC_APB1RSTR_TIM7RST_Pos           (5U)                                
-#define RCC_APB1RSTR_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */
-#define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk            
-#define RCC_APB1RSTR_TIM12RST_Pos          (6U)                                
-#define RCC_APB1RSTR_TIM12RST_Msk          (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
-#define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk           
-#define RCC_APB1RSTR_TIM13RST_Pos          (7U)                                
-#define RCC_APB1RSTR_TIM13RST_Msk          (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
-#define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk           
-#define RCC_APB1RSTR_TIM14RST_Pos          (8U)                                
-#define RCC_APB1RSTR_TIM14RST_Msk          (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
-#define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk           
-#define RCC_APB1RSTR_WWDGRST_Pos           (11U)                               
-#define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */
-#define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk            
-#define RCC_APB1RSTR_SPI2RST_Pos           (14U)                               
-#define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */
-#define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk            
-#define RCC_APB1RSTR_SPI3RST_Pos           (15U)                               
-#define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */
-#define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk            
-#define RCC_APB1RSTR_USART2RST_Pos         (17U)                               
-#define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
-#define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk          
-#define RCC_APB1RSTR_USART3RST_Pos         (18U)                               
-#define RCC_APB1RSTR_USART3RST_Msk         (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
-#define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk          
-#define RCC_APB1RSTR_UART4RST_Pos          (19U)                               
-#define RCC_APB1RSTR_UART4RST_Msk          (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
-#define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk           
-#define RCC_APB1RSTR_UART5RST_Pos          (20U)                               
-#define RCC_APB1RSTR_UART5RST_Msk          (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
-#define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk           
-#define RCC_APB1RSTR_I2C1RST_Pos           (21U)                               
-#define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */
-#define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk            
-#define RCC_APB1RSTR_I2C2RST_Pos           (22U)                               
-#define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */
-#define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk            
-#define RCC_APB1RSTR_I2C3RST_Pos           (23U)                               
-#define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */
-#define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk            
-#define RCC_APB1RSTR_CAN1RST_Pos           (25U)                               
-#define RCC_APB1RSTR_CAN1RST_Msk           (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */
-#define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk            
-#define RCC_APB1RSTR_CAN2RST_Pos           (26U)                               
-#define RCC_APB1RSTR_CAN2RST_Msk           (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */
-#define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk            
-#define RCC_APB1RSTR_PWRRST_Pos            (28U)                               
-#define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */
-#define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk             
-#define RCC_APB1RSTR_DACRST_Pos            (29U)                               
-#define RCC_APB1RSTR_DACRST_Msk            (0x1UL << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */
-#define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk             
-
-/********************  Bit definition for RCC_APB2RSTR register  **************/
-#define RCC_APB2RSTR_TIM1RST_Pos           (0U)                                
-#define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */
-#define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk            
-#define RCC_APB2RSTR_TIM8RST_Pos           (1U)                                
-#define RCC_APB2RSTR_TIM8RST_Msk           (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */
-#define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk            
-#define RCC_APB2RSTR_USART1RST_Pos         (4U)                                
-#define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
-#define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk          
-#define RCC_APB2RSTR_USART6RST_Pos         (5U)                                
-#define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
-#define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk          
-#define RCC_APB2RSTR_ADCRST_Pos            (8U)                                
-#define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */
-#define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk             
-#define RCC_APB2RSTR_SDIORST_Pos           (11U)                               
-#define RCC_APB2RSTR_SDIORST_Msk           (0x1UL << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */
-#define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk            
-#define RCC_APB2RSTR_SPI1RST_Pos           (12U)                               
-#define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */
-#define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk            
-#define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)                               
-#define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
-#define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk          
-#define RCC_APB2RSTR_TIM9RST_Pos           (16U)                               
-#define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */
-#define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk            
-#define RCC_APB2RSTR_TIM10RST_Pos          (17U)                               
-#define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
-#define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk           
-#define RCC_APB2RSTR_TIM11RST_Pos          (18U)                               
-#define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
-#define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk           
-
-/* Old SPI1RST bit definition, maintained for legacy purpose */
-#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
-
-/********************  Bit definition for RCC_AHB1ENR register  ***************/
-#define RCC_AHB1ENR_GPIOAEN_Pos            (0U)                                
-#define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */
-#define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk             
-#define RCC_AHB1ENR_GPIOBEN_Pos            (1U)                                
-#define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */
-#define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk             
-#define RCC_AHB1ENR_GPIOCEN_Pos            (2U)                                
-#define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */
-#define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk             
-#define RCC_AHB1ENR_GPIODEN_Pos            (3U)                                
-#define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */
-#define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk             
-#define RCC_AHB1ENR_GPIOEEN_Pos            (4U)                                
-#define RCC_AHB1ENR_GPIOEEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */
-#define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk             
-#define RCC_AHB1ENR_GPIOFEN_Pos            (5U)                                
-#define RCC_AHB1ENR_GPIOFEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */
-#define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk             
-#define RCC_AHB1ENR_GPIOGEN_Pos            (6U)                                
-#define RCC_AHB1ENR_GPIOGEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */
-#define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk             
-#define RCC_AHB1ENR_GPIOHEN_Pos            (7U)                                
-#define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */
-#define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk             
-#define RCC_AHB1ENR_GPIOIEN_Pos            (8U)                                
-#define RCC_AHB1ENR_GPIOIEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)   /*!< 0x00000100 */
-#define RCC_AHB1ENR_GPIOIEN                RCC_AHB1ENR_GPIOIEN_Msk             
-#define RCC_AHB1ENR_CRCEN_Pos              (12U)                               
-#define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */
-#define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk               
-#define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)                               
-#define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
-#define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk           
-#define RCC_AHB1ENR_CCMDATARAMEN_Pos       (20U)                               
-#define RCC_AHB1ENR_CCMDATARAMEN_Msk       (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
-#define RCC_AHB1ENR_CCMDATARAMEN           RCC_AHB1ENR_CCMDATARAMEN_Msk        
-#define RCC_AHB1ENR_DMA1EN_Pos             (21U)                               
-#define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */
-#define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk              
-#define RCC_AHB1ENR_DMA2EN_Pos             (22U)                               
-#define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */
-#define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk              
-#define RCC_AHB1ENR_ETHMACEN_Pos           (25U)                               
-#define RCC_AHB1ENR_ETHMACEN_Msk           (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)  /*!< 0x02000000 */
-#define RCC_AHB1ENR_ETHMACEN               RCC_AHB1ENR_ETHMACEN_Msk            
-#define RCC_AHB1ENR_ETHMACTXEN_Pos         (26U)                               
-#define RCC_AHB1ENR_ETHMACTXEN_Msk         (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
-#define RCC_AHB1ENR_ETHMACTXEN             RCC_AHB1ENR_ETHMACTXEN_Msk          
-#define RCC_AHB1ENR_ETHMACRXEN_Pos         (27U)                               
-#define RCC_AHB1ENR_ETHMACRXEN_Msk         (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
-#define RCC_AHB1ENR_ETHMACRXEN             RCC_AHB1ENR_ETHMACRXEN_Msk          
-#define RCC_AHB1ENR_ETHMACPTPEN_Pos        (28U)                               
-#define RCC_AHB1ENR_ETHMACPTPEN_Msk        (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
-#define RCC_AHB1ENR_ETHMACPTPEN            RCC_AHB1ENR_ETHMACPTPEN_Msk         
-#define RCC_AHB1ENR_OTGHSEN_Pos            (29U)                               
-#define RCC_AHB1ENR_OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */
-#define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk             
-#define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)                               
-#define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
-#define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk         
-/********************  Bit definition for RCC_AHB2ENR register  ***************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
- */
-#define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */
-
-#define RCC_AHB2ENR_DCMIEN_Pos             (0U)                                
-#define RCC_AHB2ENR_DCMIEN_Msk             (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHB2ENR_DCMIEN                 RCC_AHB2ENR_DCMIEN_Msk              
-#define RCC_AHB2ENR_RNGEN_Pos              (6U)                                
-#define RCC_AHB2ENR_RNGEN_Msk              (0x1UL << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */
-#define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk               
-#define RCC_AHB2ENR_OTGFSEN_Pos            (7U)                                
-#define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */
-#define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk             
-
-/********************  Bit definition for RCC_AHB3ENR register  ***************/
-/*
- * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
- */
-#define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */
-
-#define RCC_AHB3ENR_FSMCEN_Pos             (0U)                                
-#define RCC_AHB3ENR_FSMCEN_Msk             (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)    /*!< 0x00000001 */
-#define RCC_AHB3ENR_FSMCEN                 RCC_AHB3ENR_FSMCEN_Msk              
-
-/********************  Bit definition for RCC_APB1ENR register  ***************/
-#define RCC_APB1ENR_TIM2EN_Pos             (0U)                                
-#define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */
-#define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk              
-#define RCC_APB1ENR_TIM3EN_Pos             (1U)                                
-#define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */
-#define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk              
-#define RCC_APB1ENR_TIM4EN_Pos             (2U)                                
-#define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */
-#define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk              
-#define RCC_APB1ENR_TIM5EN_Pos             (3U)                                
-#define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */
-#define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk              
-#define RCC_APB1ENR_TIM6EN_Pos             (4U)                                
-#define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */
-#define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk              
-#define RCC_APB1ENR_TIM7EN_Pos             (5U)                                
-#define RCC_APB1ENR_TIM7EN_Msk             (0x1UL << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */
-#define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk              
-#define RCC_APB1ENR_TIM12EN_Pos            (6U)                                
-#define RCC_APB1ENR_TIM12EN_Msk            (0x1UL << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */
-#define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk             
-#define RCC_APB1ENR_TIM13EN_Pos            (7U)                                
-#define RCC_APB1ENR_TIM13EN_Msk            (0x1UL << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */
-#define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk             
-#define RCC_APB1ENR_TIM14EN_Pos            (8U)                                
-#define RCC_APB1ENR_TIM14EN_Msk            (0x1UL << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */
-#define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk             
-#define RCC_APB1ENR_WWDGEN_Pos             (11U)                               
-#define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */
-#define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk              
-#define RCC_APB1ENR_SPI2EN_Pos             (14U)                               
-#define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */
-#define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk              
-#define RCC_APB1ENR_SPI3EN_Pos             (15U)                               
-#define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */
-#define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk              
-#define RCC_APB1ENR_USART2EN_Pos           (17U)                               
-#define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */
-#define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk            
-#define RCC_APB1ENR_USART3EN_Pos           (18U)                               
-#define RCC_APB1ENR_USART3EN_Msk           (0x1UL << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */
-#define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk            
-#define RCC_APB1ENR_UART4EN_Pos            (19U)                               
-#define RCC_APB1ENR_UART4EN_Msk            (0x1UL << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */
-#define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk             
-#define RCC_APB1ENR_UART5EN_Pos            (20U)                               
-#define RCC_APB1ENR_UART5EN_Msk            (0x1UL << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */
-#define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk             
-#define RCC_APB1ENR_I2C1EN_Pos             (21U)                               
-#define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */
-#define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk              
-#define RCC_APB1ENR_I2C2EN_Pos             (22U)                               
-#define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */
-#define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk              
-#define RCC_APB1ENR_I2C3EN_Pos             (23U)                               
-#define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */
-#define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk              
-#define RCC_APB1ENR_CAN1EN_Pos             (25U)                               
-#define RCC_APB1ENR_CAN1EN_Msk             (0x1UL << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */
-#define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk              
-#define RCC_APB1ENR_CAN2EN_Pos             (26U)                               
-#define RCC_APB1ENR_CAN2EN_Msk             (0x1UL << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */
-#define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk              
-#define RCC_APB1ENR_PWREN_Pos              (28U)                               
-#define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */
-#define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk               
-#define RCC_APB1ENR_DACEN_Pos              (29U)                               
-#define RCC_APB1ENR_DACEN_Msk              (0x1UL << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */
-#define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk               
-
-/********************  Bit definition for RCC_APB2ENR register  ***************/
-#define RCC_APB2ENR_TIM1EN_Pos             (0U)                                
-#define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */
-#define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk              
-#define RCC_APB2ENR_TIM8EN_Pos             (1U)                                
-#define RCC_APB2ENR_TIM8EN_Msk             (0x1UL << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */
-#define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk              
-#define RCC_APB2ENR_USART1EN_Pos           (4U)                                
-#define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */
-#define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk            
-#define RCC_APB2ENR_USART6EN_Pos           (5U)                                
-#define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */
-#define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk            
-#define RCC_APB2ENR_ADC1EN_Pos             (8U)                                
-#define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */
-#define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk              
-#define RCC_APB2ENR_ADC2EN_Pos             (9U)                                
-#define RCC_APB2ENR_ADC2EN_Msk             (0x1UL << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */
-#define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk              
-#define RCC_APB2ENR_ADC3EN_Pos             (10U)                               
-#define RCC_APB2ENR_ADC3EN_Msk             (0x1UL << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */
-#define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk              
-#define RCC_APB2ENR_SDIOEN_Pos             (11U)                               
-#define RCC_APB2ENR_SDIOEN_Msk             (0x1UL << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */
-#define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk              
-#define RCC_APB2ENR_SPI1EN_Pos             (12U)                               
-#define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */
-#define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk              
-#define RCC_APB2ENR_SYSCFGEN_Pos           (14U)                               
-#define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */
-#define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk            
-#define RCC_APB2ENR_TIM9EN_Pos             (16U)                               
-#define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */
-#define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk              
-#define RCC_APB2ENR_TIM10EN_Pos            (17U)                               
-#define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */
-#define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk             
-#define RCC_APB2ENR_TIM11EN_Pos            (18U)                               
-#define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */
-#define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk             
-
-/********************  Bit definition for RCC_AHB1LPENR register  *************/
-#define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)                                
-#define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk         
-#define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)                                
-#define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
-#define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk         
-#define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)                                
-#define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
-#define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk         
-#define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)                                
-#define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
-#define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk         
-#define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)                                
-#define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
-#define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk         
-#define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)                                
-#define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
-#define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk         
-#define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)                                
-#define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
-#define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk         
-#define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)                                
-#define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
-#define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk         
-#define RCC_AHB1LPENR_GPIOILPEN_Pos        (8U)                                
-#define RCC_AHB1LPENR_GPIOILPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
-#define RCC_AHB1LPENR_GPIOILPEN            RCC_AHB1LPENR_GPIOILPEN_Msk         
-#define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)                               
-#define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
-#define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk           
-#define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)                               
-#define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
-#define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk         
-#define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)                               
-#define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
-#define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk         
-#define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)                               
-#define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk         
-#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)                               
-#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
-#define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk       
-#define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)                               
-#define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk          
-#define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)                               
-#define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk          
-
-#define RCC_AHB1LPENR_ETHMACLPEN_Pos       (25U)                               
-#define RCC_AHB1LPENR_ETHMACLPEN_Msk       (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
-#define RCC_AHB1LPENR_ETHMACLPEN           RCC_AHB1LPENR_ETHMACLPEN_Msk        
-#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos     (26U)                               
-#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk     (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
-#define RCC_AHB1LPENR_ETHMACTXLPEN         RCC_AHB1LPENR_ETHMACTXLPEN_Msk      
-#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos     (27U)                               
-#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk     (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
-#define RCC_AHB1LPENR_ETHMACRXLPEN         RCC_AHB1LPENR_ETHMACRXLPEN_Msk      
-#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos    (28U)                               
-#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk    (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
-#define RCC_AHB1LPENR_ETHMACPTPLPEN        RCC_AHB1LPENR_ETHMACPTPLPEN_Msk     
-#define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)                               
-#define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
-#define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk         
-#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)                               
-#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
-#define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk     
-
-/********************  Bit definition for RCC_AHB2LPENR register  *************/
-#define RCC_AHB2LPENR_DCMILPEN_Pos         (0U)                                
-#define RCC_AHB2LPENR_DCMILPEN_Msk         (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHB2LPENR_DCMILPEN             RCC_AHB2LPENR_DCMILPEN_Msk          
-#define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)                                
-#define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
-#define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk           
-#define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)                                
-#define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
-#define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk         
-
-/********************  Bit definition for RCC_AHB3LPENR register  *************/
-#define RCC_AHB3LPENR_FSMCLPEN_Pos         (0U)                                
-#define RCC_AHB3LPENR_FSMCLPEN_Msk         (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */
-#define RCC_AHB3LPENR_FSMCLPEN             RCC_AHB3LPENR_FSMCLPEN_Msk          
-
-/********************  Bit definition for RCC_APB1LPENR register  *************/
-#define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)                                
-#define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk          
-#define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)                                
-#define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk          
-#define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)                                
-#define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
-#define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk          
-#define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)                                
-#define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
-#define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk          
-#define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)                                
-#define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk          
-#define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)                                
-#define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk          
-#define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)                                
-#define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
-#define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk         
-#define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)                                
-#define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
-#define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk         
-#define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)                                
-#define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
-#define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk         
-#define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)                               
-#define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk          
-#define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)                               
-#define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk          
-#define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)                               
-#define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
-#define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk          
-#define RCC_APB1LPENR_USART2LPEN_Pos       (17U)                               
-#define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk        
-#define RCC_APB1LPENR_USART3LPEN_Pos       (18U)                               
-#define RCC_APB1LPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk        
-#define RCC_APB1LPENR_UART4LPEN_Pos        (19U)                               
-#define RCC_APB1LPENR_UART4LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
-#define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk         
-#define RCC_APB1LPENR_UART5LPEN_Pos        (20U)                               
-#define RCC_APB1LPENR_UART5LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
-#define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk         
-#define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)                               
-#define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
-#define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk          
-#define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)                               
-#define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
-#define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk          
-#define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)                               
-#define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
-#define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk          
-#define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)                               
-#define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
-#define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk          
-#define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)                               
-#define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
-#define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk          
-#define RCC_APB1LPENR_PWRLPEN_Pos          (28U)                               
-#define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
-#define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk           
-#define RCC_APB1LPENR_DACLPEN_Pos          (29U)                               
-#define RCC_APB1LPENR_DACLPEN_Msk          (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
-#define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk           
-
-/********************  Bit definition for RCC_APB2LPENR register  *************/
-#define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)                                
-#define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
-#define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk          
-#define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)                                
-#define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
-#define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk          
-#define RCC_APB2LPENR_USART1LPEN_Pos       (4U)                                
-#define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
-#define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk        
-#define RCC_APB2LPENR_USART6LPEN_Pos       (5U)                                
-#define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
-#define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk        
-#define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)                                
-#define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
-#define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk          
-#define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)                                
-#define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
-#define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk          
-#define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)                               
-#define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
-#define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk          
-#define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)                               
-#define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
-#define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk          
-#define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)                               
-#define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
-#define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk          
-#define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)                               
-#define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
-#define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk        
-#define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)                               
-#define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
-#define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk          
-#define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)                               
-#define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
-#define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk         
-#define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)                               
-#define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
-#define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk         
-
-/********************  Bit definition for RCC_BDCR register  ******************/
-#define RCC_BDCR_LSEON_Pos                 (0U)                                
-#define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */
-#define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk                  
-#define RCC_BDCR_LSERDY_Pos                (1U)                                
-#define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */
-#define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk                 
-#define RCC_BDCR_LSEBYP_Pos                (2U)                                
-#define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */
-#define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk                 
-
-#define RCC_BDCR_RTCSEL_Pos                (8U)                                
-#define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */
-#define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk                 
-#define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */
-#define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */
-
-#define RCC_BDCR_RTCEN_Pos                 (15U)                               
-#define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */
-#define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk                  
-#define RCC_BDCR_BDRST_Pos                 (16U)                               
-#define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */
-#define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk                  
-
-/********************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION_Pos                  (0U)                                
-#define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */
-#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk                   
-#define RCC_CSR_LSIRDY_Pos                 (1U)                                
-#define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */
-#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk                  
-#define RCC_CSR_RMVF_Pos                   (24U)                               
-#define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */
-#define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk                    
-#define RCC_CSR_BORRSTF_Pos                (25U)                               
-#define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */
-#define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk                 
-#define RCC_CSR_PINRSTF_Pos                (26U)
-#define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */
-#define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk
-#define RCC_CSR_PORRSTF_Pos                (27U)                               
-#define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */
-#define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk                 
-#define RCC_CSR_SFTRSTF_Pos                (28U)                               
-#define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */
-#define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk                 
-#define RCC_CSR_IWDGRSTF_Pos               (29U)
-#define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */
-#define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk
-#define RCC_CSR_WWDGRSTF_Pos               (30U)                               
-#define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */
-#define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk                
-#define RCC_CSR_LPWRRSTF_Pos               (31U)                               
-#define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */
-#define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk
-/* Legacy defines */
-#define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF
-#define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF
-
-/********************  Bit definition for RCC_SSCGR register  *****************/
-#define RCC_SSCGR_MODPER_Pos               (0U)                                
-#define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */
-#define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk                
-#define RCC_SSCGR_INCSTEP_Pos              (13U)                               
-#define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */
-#define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk               
-#define RCC_SSCGR_SPREADSEL_Pos            (30U)                               
-#define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */
-#define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk             
-#define RCC_SSCGR_SSCGEN_Pos               (31U)                               
-#define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */
-#define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk                
-
-/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
-#define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)                                
-#define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
-#define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk          
-#define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
-#define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
-#define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
-#define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
-#define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
-#define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
-#define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
-#define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
-#define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
-
-#define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)                               
-#define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
-#define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk          
-#define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
-#define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
-#define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN_Pos    (2U)                                               
-#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
-#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
-#define RNG_CR_IE_Pos       (3U)                                               
-#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
-#define RNG_CR_IE           RNG_CR_IE_Msk                                      
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY_Pos     (0U)                                               
-#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
-#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
-#define RNG_SR_CECS_Pos     (1U)                                               
-#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
-#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
-#define RNG_SR_SECS_Pos     (2U)                                               
-#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
-#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
-#define RNG_SR_CEIS_Pos     (5U)                                               
-#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
-#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
-#define RNG_SR_SEIS_Pos     (6U)                                               
-#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
-#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/*
- * @brief Specific device feature definitions  (not present on all devices in the STM32F4 serie)
- */
-#define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */
-#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM_Pos                 (22U)                                    
-#define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
-#define RTC_TR_PM                     RTC_TR_PM_Msk                            
-#define RTC_TR_HT_Pos                 (20U)                                    
-#define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
-#define RTC_TR_HT                     RTC_TR_HT_Msk                            
-#define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
-#define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
-#define RTC_TR_HU_Pos                 (16U)                                    
-#define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
-#define RTC_TR_HU                     RTC_TR_HU_Msk                            
-#define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
-#define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
-#define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
-#define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
-#define RTC_TR_MNT_Pos                (12U)                                    
-#define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
-#define RTC_TR_MNT                    RTC_TR_MNT_Msk                           
-#define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
-#define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
-#define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
-#define RTC_TR_MNU_Pos                (8U)                                     
-#define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
-#define RTC_TR_MNU                    RTC_TR_MNU_Msk                           
-#define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
-#define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
-#define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
-#define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
-#define RTC_TR_ST_Pos                 (4U)                                     
-#define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
-#define RTC_TR_ST                     RTC_TR_ST_Msk                            
-#define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
-#define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
-#define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
-#define RTC_TR_SU_Pos                 (0U)                                     
-#define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
-#define RTC_TR_SU                     RTC_TR_SU_Msk                            
-#define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
-#define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
-#define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
-#define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT_Pos                 (20U)                                    
-#define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
-#define RTC_DR_YT                     RTC_DR_YT_Msk                            
-#define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
-#define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
-#define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
-#define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
-#define RTC_DR_YU_Pos                 (16U)                                    
-#define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
-#define RTC_DR_YU                     RTC_DR_YU_Msk                            
-#define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
-#define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
-#define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
-#define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
-#define RTC_DR_WDU_Pos                (13U)                                    
-#define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
-#define RTC_DR_WDU                    RTC_DR_WDU_Msk                           
-#define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
-#define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
-#define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
-#define RTC_DR_MT_Pos                 (12U)                                    
-#define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
-#define RTC_DR_MT                     RTC_DR_MT_Msk                            
-#define RTC_DR_MU_Pos                 (8U)                                     
-#define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
-#define RTC_DR_MU                     RTC_DR_MU_Msk                            
-#define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
-#define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
-#define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
-#define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
-#define RTC_DR_DT_Pos                 (4U)                                     
-#define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
-#define RTC_DR_DT                     RTC_DR_DT_Msk                            
-#define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
-#define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
-#define RTC_DR_DU_Pos                 (0U)                                     
-#define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
-#define RTC_DR_DU                     RTC_DR_DU_Msk                            
-#define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
-#define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
-#define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
-#define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE_Pos                (23U)                                    
-#define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
-#define RTC_CR_COE                    RTC_CR_COE_Msk                           
-#define RTC_CR_OSEL_Pos               (21U)                                    
-#define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
-#define RTC_CR_OSEL                   RTC_CR_OSEL_Msk                          
-#define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
-#define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
-#define RTC_CR_POL_Pos                (20U)                                    
-#define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
-#define RTC_CR_POL                    RTC_CR_POL_Msk                           
-#define RTC_CR_COSEL_Pos              (19U)                                    
-#define RTC_CR_COSEL_Msk              (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
-#define RTC_CR_COSEL                  RTC_CR_COSEL_Msk                         
-#define RTC_CR_BKP_Pos                 (18U)                                   
-#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
-#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          
-#define RTC_CR_SUB1H_Pos              (17U)                                    
-#define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
-#define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk                         
-#define RTC_CR_ADD1H_Pos              (16U)                                    
-#define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
-#define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk                         
-#define RTC_CR_TSIE_Pos               (15U)                                    
-#define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
-#define RTC_CR_TSIE                   RTC_CR_TSIE_Msk                          
-#define RTC_CR_WUTIE_Pos              (14U)                                    
-#define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
-#define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk                         
-#define RTC_CR_ALRBIE_Pos             (13U)                                    
-#define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
-#define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk                        
-#define RTC_CR_ALRAIE_Pos             (12U)                                    
-#define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
-#define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk                        
-#define RTC_CR_TSE_Pos                (11U)                                    
-#define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
-#define RTC_CR_TSE                    RTC_CR_TSE_Msk                           
-#define RTC_CR_WUTE_Pos               (10U)                                    
-#define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
-#define RTC_CR_WUTE                   RTC_CR_WUTE_Msk                          
-#define RTC_CR_ALRBE_Pos              (9U)                                     
-#define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
-#define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk                         
-#define RTC_CR_ALRAE_Pos              (8U)                                     
-#define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
-#define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk                         
-#define RTC_CR_DCE_Pos                (7U)                                     
-#define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */
-#define RTC_CR_DCE                    RTC_CR_DCE_Msk                           
-#define RTC_CR_FMT_Pos                (6U)                                     
-#define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
-#define RTC_CR_FMT                    RTC_CR_FMT_Msk                           
-#define RTC_CR_BYPSHAD_Pos            (5U)                                     
-#define RTC_CR_BYPSHAD_Msk            (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
-#define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk                       
-#define RTC_CR_REFCKON_Pos            (4U)                                     
-#define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
-#define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk                       
-#define RTC_CR_TSEDGE_Pos             (3U)                                     
-#define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
-#define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk                        
-#define RTC_CR_WUCKSEL_Pos            (0U)                                     
-#define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
-#define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk                       
-#define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
-#define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
-#define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
-
-/* Legacy defines */
-#define RTC_CR_BCK                     RTC_CR_BKP
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF_Pos           (16U)                                    
-#define RTC_ISR_RECALPF_Msk           (0x1UL << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */
-#define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk                      
-#define RTC_ISR_TAMP1F_Pos            (13U)                                    
-#define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */
-#define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk                       
-#define RTC_ISR_TAMP2F_Pos            (14U)                                    
-#define RTC_ISR_TAMP2F_Msk            (0x1UL << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */
-#define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk                       
-#define RTC_ISR_TSOVF_Pos             (12U)                                    
-#define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */
-#define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk                        
-#define RTC_ISR_TSF_Pos               (11U)                                    
-#define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */
-#define RTC_ISR_TSF                   RTC_ISR_TSF_Msk                          
-#define RTC_ISR_WUTF_Pos              (10U)                                    
-#define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */
-#define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk                         
-#define RTC_ISR_ALRBF_Pos             (9U)                                     
-#define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */
-#define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk                        
-#define RTC_ISR_ALRAF_Pos             (8U)                                     
-#define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */
-#define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk                        
-#define RTC_ISR_INIT_Pos              (7U)                                     
-#define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */
-#define RTC_ISR_INIT                  RTC_ISR_INIT_Msk                         
-#define RTC_ISR_INITF_Pos             (6U)                                     
-#define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */
-#define RTC_ISR_INITF                 RTC_ISR_INITF_Msk                        
-#define RTC_ISR_RSF_Pos               (5U)                                     
-#define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */
-#define RTC_ISR_RSF                   RTC_ISR_RSF_Msk                          
-#define RTC_ISR_INITS_Pos             (4U)                                     
-#define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */
-#define RTC_ISR_INITS                 RTC_ISR_INITS_Msk                        
-#define RTC_ISR_SHPF_Pos              (3U)                                     
-#define RTC_ISR_SHPF_Msk              (0x1UL << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */
-#define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk                         
-#define RTC_ISR_WUTWF_Pos             (2U)                                     
-#define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */
-#define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk                        
-#define RTC_ISR_ALRBWF_Pos            (1U)                                     
-#define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */
-#define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk                       
-#define RTC_ISR_ALRAWF_Pos            (0U)                                     
-#define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */
-#define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk                       
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A_Pos         (16U)                                    
-#define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
-#define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk                    
-#define RTC_PRER_PREDIV_S_Pos         (0U)                                     
-#define RTC_PRER_PREDIV_S_Msk         (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
-#define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk                    
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT_Pos              (0U)                                     
-#define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
-#define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk                         
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS_Pos            (7U)                                     
-#define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */
-#define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk                       
-#define RTC_CALIBR_DC_Pos             (0U)                                     
-#define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */
-#define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk                        
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4_Pos           (31U)                                    
-#define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
-#define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk                      
-#define RTC_ALRMAR_WDSEL_Pos          (30U)                                    
-#define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
-#define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk                     
-#define RTC_ALRMAR_DT_Pos             (28U)                                    
-#define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
-#define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk                        
-#define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
-#define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
-#define RTC_ALRMAR_DU_Pos             (24U)                                    
-#define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
-#define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk                        
-#define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
-#define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
-#define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
-#define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
-#define RTC_ALRMAR_MSK3_Pos           (23U)                                    
-#define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
-#define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk                      
-#define RTC_ALRMAR_PM_Pos             (22U)                                    
-#define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
-#define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk                        
-#define RTC_ALRMAR_HT_Pos             (20U)                                    
-#define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
-#define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk                        
-#define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
-#define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
-#define RTC_ALRMAR_HU_Pos             (16U)                                    
-#define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
-#define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk                        
-#define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
-#define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
-#define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
-#define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
-#define RTC_ALRMAR_MSK2_Pos           (15U)                                    
-#define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
-#define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk                      
-#define RTC_ALRMAR_MNT_Pos            (12U)                                    
-#define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
-#define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk                       
-#define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
-#define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
-#define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
-#define RTC_ALRMAR_MNU_Pos            (8U)                                     
-#define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
-#define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk                       
-#define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
-#define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
-#define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
-#define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
-#define RTC_ALRMAR_MSK1_Pos           (7U)                                     
-#define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
-#define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk                      
-#define RTC_ALRMAR_ST_Pos             (4U)                                     
-#define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
-#define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk                        
-#define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
-#define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
-#define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
-#define RTC_ALRMAR_SU_Pos             (0U)                                     
-#define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
-#define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk                        
-#define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
-#define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
-#define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
-#define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4_Pos           (31U)                                    
-#define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
-#define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk                      
-#define RTC_ALRMBR_WDSEL_Pos          (30U)                                    
-#define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
-#define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk                     
-#define RTC_ALRMBR_DT_Pos             (28U)                                    
-#define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
-#define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk                        
-#define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
-#define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
-#define RTC_ALRMBR_DU_Pos             (24U)                                    
-#define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
-#define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk                        
-#define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
-#define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
-#define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
-#define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
-#define RTC_ALRMBR_MSK3_Pos           (23U)                                    
-#define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
-#define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk                      
-#define RTC_ALRMBR_PM_Pos             (22U)                                    
-#define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
-#define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk                        
-#define RTC_ALRMBR_HT_Pos             (20U)                                    
-#define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
-#define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk                        
-#define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
-#define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
-#define RTC_ALRMBR_HU_Pos             (16U)                                    
-#define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
-#define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk                        
-#define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
-#define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
-#define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
-#define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
-#define RTC_ALRMBR_MSK2_Pos           (15U)                                    
-#define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
-#define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk                      
-#define RTC_ALRMBR_MNT_Pos            (12U)                                    
-#define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
-#define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk                       
-#define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
-#define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
-#define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
-#define RTC_ALRMBR_MNU_Pos            (8U)                                     
-#define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
-#define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk                       
-#define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
-#define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
-#define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
-#define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
-#define RTC_ALRMBR_MSK1_Pos           (7U)                                     
-#define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
-#define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk                      
-#define RTC_ALRMBR_ST_Pos             (4U)                                     
-#define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
-#define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk                        
-#define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
-#define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
-#define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
-#define RTC_ALRMBR_SU_Pos             (0U)                                     
-#define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
-#define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk                        
-#define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
-#define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
-#define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
-#define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY_Pos               (0U)                                     
-#define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
-#define RTC_WPR_KEY                   RTC_WPR_KEY_Msk                          
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS_Pos                (0U)                                     
-#define RTC_SSR_SS_Msk                (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
-#define RTC_SSR_SS                    RTC_SSR_SS_Msk                           
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS_Pos          (0U)                                     
-#define RTC_SHIFTR_SUBFS_Msk          (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
-#define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk                     
-#define RTC_SHIFTR_ADD1S_Pos          (31U)                                    
-#define RTC_SHIFTR_ADD1S_Msk          (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
-#define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk                     
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM_Pos               (22U)                                    
-#define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
-#define RTC_TSTR_PM                   RTC_TSTR_PM_Msk                          
-#define RTC_TSTR_HT_Pos               (20U)                                    
-#define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
-#define RTC_TSTR_HT                   RTC_TSTR_HT_Msk                          
-#define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
-#define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
-#define RTC_TSTR_HU_Pos               (16U)                                    
-#define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
-#define RTC_TSTR_HU                   RTC_TSTR_HU_Msk                          
-#define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
-#define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
-#define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
-#define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
-#define RTC_TSTR_MNT_Pos              (12U)                                    
-#define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
-#define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk                         
-#define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
-#define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
-#define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
-#define RTC_TSTR_MNU_Pos              (8U)                                     
-#define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
-#define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk                         
-#define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
-#define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
-#define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
-#define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
-#define RTC_TSTR_ST_Pos               (4U)                                     
-#define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
-#define RTC_TSTR_ST                   RTC_TSTR_ST_Msk                          
-#define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
-#define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
-#define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
-#define RTC_TSTR_SU_Pos               (0U)                                     
-#define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
-#define RTC_TSTR_SU                   RTC_TSTR_SU_Msk                          
-#define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
-#define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
-#define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
-#define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU_Pos              (13U)                                    
-#define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
-#define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk                         
-#define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
-#define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
-#define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
-#define RTC_TSDR_MT_Pos               (12U)                                    
-#define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
-#define RTC_TSDR_MT                   RTC_TSDR_MT_Msk                          
-#define RTC_TSDR_MU_Pos               (8U)                                     
-#define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
-#define RTC_TSDR_MU                   RTC_TSDR_MU_Msk                          
-#define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
-#define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
-#define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
-#define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
-#define RTC_TSDR_DT_Pos               (4U)                                     
-#define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
-#define RTC_TSDR_DT                   RTC_TSDR_DT_Msk                          
-#define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
-#define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
-#define RTC_TSDR_DU_Pos               (0U)                                     
-#define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
-#define RTC_TSDR_DU                   RTC_TSDR_DU_Msk                          
-#define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
-#define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
-#define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
-#define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS_Pos              (0U)                                     
-#define RTC_TSSSR_SS_Msk              (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
-#define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk                         
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP_Pos             (15U)                                    
-#define RTC_CALR_CALP_Msk             (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
-#define RTC_CALR_CALP                 RTC_CALR_CALP_Msk                        
-#define RTC_CALR_CALW8_Pos            (14U)                                    
-#define RTC_CALR_CALW8_Msk            (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
-#define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk                       
-#define RTC_CALR_CALW16_Pos           (13U)                                    
-#define RTC_CALR_CALW16_Msk           (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
-#define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk                      
-#define RTC_CALR_CALM_Pos             (0U)                                     
-#define RTC_CALR_CALM_Msk             (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
-#define RTC_CALR_CALM                 RTC_CALR_CALM_Msk                        
-#define RTC_CALR_CALM_0               (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
-#define RTC_CALR_CALM_1               (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
-#define RTC_CALR_CALM_2               (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
-#define RTC_CALR_CALM_3               (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
-#define RTC_CALR_CALM_4               (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
-#define RTC_CALR_CALM_5               (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
-#define RTC_CALR_CALM_6               (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
-#define RTC_CALR_CALM_7               (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
-#define RTC_CALR_CALM_8               (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)                                    
-#define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */
-#define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk               
-#define RTC_TAFCR_TSINSEL_Pos         (17U)                                    
-#define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */
-#define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk                    
-#define RTC_TAFCR_TAMP1INSEL_Pos      (16U)                                    
-#define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */
-#define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk                  
-#define RTC_TAFCR_TAMPPUDIS_Pos       (15U)                                    
-#define RTC_TAFCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */
-#define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk                  
-#define RTC_TAFCR_TAMPPRCH_Pos        (13U)                                    
-#define RTC_TAFCR_TAMPPRCH_Msk        (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */
-#define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk                   
-#define RTC_TAFCR_TAMPPRCH_0          (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */
-#define RTC_TAFCR_TAMPPRCH_1          (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */
-#define RTC_TAFCR_TAMPFLT_Pos         (11U)                                    
-#define RTC_TAFCR_TAMPFLT_Msk         (0x3UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */
-#define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk                    
-#define RTC_TAFCR_TAMPFLT_0           (0x1UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */
-#define RTC_TAFCR_TAMPFLT_1           (0x2UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */
-#define RTC_TAFCR_TAMPFREQ_Pos        (8U)                                     
-#define RTC_TAFCR_TAMPFREQ_Msk        (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */
-#define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk                   
-#define RTC_TAFCR_TAMPFREQ_0          (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */
-#define RTC_TAFCR_TAMPFREQ_1          (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */
-#define RTC_TAFCR_TAMPFREQ_2          (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */
-#define RTC_TAFCR_TAMPTS_Pos          (7U)                                     
-#define RTC_TAFCR_TAMPTS_Msk          (0x1UL << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */
-#define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk                     
-#define RTC_TAFCR_TAMP2TRG_Pos        (4U)                                     
-#define RTC_TAFCR_TAMP2TRG_Msk        (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */
-#define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk                   
-#define RTC_TAFCR_TAMP2E_Pos          (3U)                                     
-#define RTC_TAFCR_TAMP2E_Msk          (0x1UL << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */
-#define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk                     
-#define RTC_TAFCR_TAMPIE_Pos          (2U)                                     
-#define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */
-#define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk                     
-#define RTC_TAFCR_TAMP1TRG_Pos        (1U)                                     
-#define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */
-#define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk                   
-#define RTC_TAFCR_TAMP1E_Pos          (0U)                                     
-#define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */
-#define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk                     
-
-/* Legacy defines */
-#define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS_Pos       (24U)                                    
-#define RTC_ALRMASSR_MASKSS_Msk       (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
-#define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk                  
-#define RTC_ALRMASSR_MASKSS_0         (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
-#define RTC_ALRMASSR_MASKSS_1         (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
-#define RTC_ALRMASSR_MASKSS_2         (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
-#define RTC_ALRMASSR_MASKSS_3         (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMASSR_SS_Pos           (0U)                                     
-#define RTC_ALRMASSR_SS_Msk           (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
-#define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk                      
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS_Pos       (24U)                                    
-#define RTC_ALRMBSSR_MASKSS_Msk       (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
-#define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk                  
-#define RTC_ALRMBSSR_MASKSS_0         (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
-#define RTC_ALRMBSSR_MASKSS_1         (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
-#define RTC_ALRMBSSR_MASKSS_2         (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
-#define RTC_ALRMBSSR_MASKSS_3         (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
-#define RTC_ALRMBSSR_SS_Pos           (0U)                                     
-#define RTC_ALRMBSSR_SS_Msk           (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
-#define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk                      
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R_Pos                 (0U)                                     
-#define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */
-#define RTC_BKP0R                     RTC_BKP0R_Msk                            
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R_Pos                 (0U)                                     
-#define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */
-#define RTC_BKP1R                     RTC_BKP1R_Msk                            
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R_Pos                 (0U)                                     
-#define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */
-#define RTC_BKP2R                     RTC_BKP2R_Msk                            
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R_Pos                 (0U)                                     
-#define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */
-#define RTC_BKP3R                     RTC_BKP3R_Msk                            
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R_Pos                 (0U)                                     
-#define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */
-#define RTC_BKP4R                     RTC_BKP4R_Msk                            
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R_Pos                 (0U)                                     
-#define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */
-#define RTC_BKP5R                     RTC_BKP5R_Msk                            
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R_Pos                 (0U)                                     
-#define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */
-#define RTC_BKP6R                     RTC_BKP6R_Msk                            
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R_Pos                 (0U)                                     
-#define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */
-#define RTC_BKP7R                     RTC_BKP7R_Msk                            
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R_Pos                 (0U)                                     
-#define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */
-#define RTC_BKP8R                     RTC_BKP8R_Msk                            
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R_Pos                 (0U)                                     
-#define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */
-#define RTC_BKP9R                     RTC_BKP9R_Msk                            
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R_Pos                (0U)                                     
-#define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP10R                    RTC_BKP10R_Msk                           
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R_Pos                (0U)                                     
-#define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP11R                    RTC_BKP11R_Msk                           
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R_Pos                (0U)                                     
-#define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP12R                    RTC_BKP12R_Msk                           
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R_Pos                (0U)                                     
-#define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP13R                    RTC_BKP13R_Msk                           
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R_Pos                (0U)                                     
-#define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP14R                    RTC_BKP14R_Msk                           
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R_Pos                (0U)                                     
-#define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP15R                    RTC_BKP15R_Msk                           
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R_Pos                (0U)                                     
-#define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP16R                    RTC_BKP16R_Msk                           
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R_Pos                (0U)                                     
-#define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP17R                    RTC_BKP17R_Msk                           
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R_Pos                (0U)                                     
-#define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP18R                    RTC_BKP18R_Msk                           
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R_Pos                (0U)                                     
-#define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */
-#define RTC_BKP19R                    RTC_BKP19R_Msk                           
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER                       0x000000014U
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          SD host Interface                                 */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SDIO_POWER register  ******************/
-#define SDIO_POWER_PWRCTRL_Pos         (0U)                                    
-#define SDIO_POWER_PWRCTRL_Msk         (0x3UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */
-#define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */
-#define SDIO_POWER_PWRCTRL_0           (0x1UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */
-#define SDIO_POWER_PWRCTRL_1           (0x2UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */
-
-/******************  Bit definition for SDIO_CLKCR register  ******************/
-#define SDIO_CLKCR_CLKDIV_Pos          (0U)                                    
-#define SDIO_CLKCR_CLKDIV_Msk          (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */
-#define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */
-#define SDIO_CLKCR_CLKEN_Pos           (8U)                                    
-#define SDIO_CLKCR_CLKEN_Msk           (0x1UL << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */
-#define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */
-#define SDIO_CLKCR_PWRSAV_Pos          (9U)                                    
-#define SDIO_CLKCR_PWRSAV_Msk          (0x1UL << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */
-#define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */
-#define SDIO_CLKCR_BYPASS_Pos          (10U)                                   
-#define SDIO_CLKCR_BYPASS_Msk          (0x1UL << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */
-#define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */
-
-#define SDIO_CLKCR_WIDBUS_Pos          (11U)                                   
-#define SDIO_CLKCR_WIDBUS_Msk          (0x3UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */
-#define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
-#define SDIO_CLKCR_WIDBUS_0            (0x1UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */
-#define SDIO_CLKCR_WIDBUS_1            (0x2UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */
-
-#define SDIO_CLKCR_NEGEDGE_Pos         (13U)                                   
-#define SDIO_CLKCR_NEGEDGE_Msk         (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */
-#define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */
-#define SDIO_CLKCR_HWFC_EN_Pos         (14U)                                   
-#define SDIO_CLKCR_HWFC_EN_Msk         (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */
-#define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */
-
-/*******************  Bit definition for SDIO_ARG register  *******************/
-#define SDIO_ARG_CMDARG_Pos            (0U)                                    
-#define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */
-#define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */
-
-/*******************  Bit definition for SDIO_CMD register  *******************/
-#define SDIO_CMD_CMDINDEX_Pos          (0U)                                    
-#define SDIO_CMD_CMDINDEX_Msk          (0x3FUL << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */
-#define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */
-
-#define SDIO_CMD_WAITRESP_Pos          (6U)                                    
-#define SDIO_CMD_WAITRESP_Msk          (0x3UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */
-#define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */
-#define SDIO_CMD_WAITRESP_0            (0x1UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */
-#define SDIO_CMD_WAITRESP_1            (0x2UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */
-
-#define SDIO_CMD_WAITINT_Pos           (8U)                                    
-#define SDIO_CMD_WAITINT_Msk           (0x1UL << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */
-#define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */
-#define SDIO_CMD_WAITPEND_Pos          (9U)                                    
-#define SDIO_CMD_WAITPEND_Msk          (0x1UL << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */
-#define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
-#define SDIO_CMD_CPSMEN_Pos            (10U)                                   
-#define SDIO_CMD_CPSMEN_Msk            (0x1UL << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */
-#define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */
-#define SDIO_CMD_SDIOSUSPEND_Pos       (11U)                                   
-#define SDIO_CMD_SDIOSUSPEND_Msk       (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */
-#define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */
-#define SDIO_CMD_ENCMDCOMPL_Pos        (12U)                                   
-#define SDIO_CMD_ENCMDCOMPL_Msk        (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)       /*!< 0x00001000 */
-#define SDIO_CMD_ENCMDCOMPL            SDIO_CMD_ENCMDCOMPL_Msk                 /*!<Enable CMD completion                                          */
-#define SDIO_CMD_NIEN_Pos              (13U)                                   
-#define SDIO_CMD_NIEN_Msk              (0x1UL << SDIO_CMD_NIEN_Pos)             /*!< 0x00002000 */
-#define SDIO_CMD_NIEN                  SDIO_CMD_NIEN_Msk                       /*!<Not Interrupt Enable                                           */
-#define SDIO_CMD_CEATACMD_Pos          (14U)                                   
-#define SDIO_CMD_CEATACMD_Msk          (0x1UL << SDIO_CMD_CEATACMD_Pos)         /*!< 0x00004000 */
-#define SDIO_CMD_CEATACMD              SDIO_CMD_CEATACMD_Msk                   /*!<CE-ATA command                                                 */
-
-/*****************  Bit definition for SDIO_RESPCMD register  *****************/
-#define SDIO_RESPCMD_RESPCMD_Pos       (0U)                                    
-#define SDIO_RESPCMD_RESPCMD_Msk       (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */
-#define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */
-
-/******************  Bit definition for SDIO_RESP0 register  ******************/
-#define SDIO_RESP0_CARDSTATUS0_Pos     (0U)                                    
-#define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP1 register  ******************/
-#define SDIO_RESP1_CARDSTATUS1_Pos     (0U)                                    
-#define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP2 register  ******************/
-#define SDIO_RESP2_CARDSTATUS2_Pos     (0U)                                    
-#define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP3 register  ******************/
-#define SDIO_RESP3_CARDSTATUS3_Pos     (0U)                                    
-#define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */
-
-/******************  Bit definition for SDIO_RESP4 register  ******************/
-#define SDIO_RESP4_CARDSTATUS4_Pos     (0U)                                    
-#define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */
-
-/******************  Bit definition for SDIO_DTIMER register  *****************/
-#define SDIO_DTIMER_DATATIME_Pos       (0U)                                    
-#define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */
-
-/******************  Bit definition for SDIO_DLEN register  *******************/
-#define SDIO_DLEN_DATALENGTH_Pos       (0U)                                    
-#define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
-#define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */
-
-/******************  Bit definition for SDIO_DCTRL register  ******************/
-#define SDIO_DCTRL_DTEN_Pos            (0U)                                    
-#define SDIO_DCTRL_DTEN_Msk            (0x1UL << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */
-#define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */
-#define SDIO_DCTRL_DTDIR_Pos           (1U)                                    
-#define SDIO_DCTRL_DTDIR_Msk           (0x1UL << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */
-#define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */
-#define SDIO_DCTRL_DTMODE_Pos          (2U)                                    
-#define SDIO_DCTRL_DTMODE_Msk          (0x1UL << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */
-#define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */
-#define SDIO_DCTRL_DMAEN_Pos           (3U)                                    
-#define SDIO_DCTRL_DMAEN_Msk           (0x1UL << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */
-#define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */
-
-#define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)                                    
-#define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */
-#define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */
-#define SDIO_DCTRL_DBLOCKSIZE_0        (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */
-#define SDIO_DCTRL_DBLOCKSIZE_1        (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */
-#define SDIO_DCTRL_DBLOCKSIZE_2        (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */
-#define SDIO_DCTRL_DBLOCKSIZE_3        (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */
-
-#define SDIO_DCTRL_RWSTART_Pos         (8U)                                    
-#define SDIO_DCTRL_RWSTART_Msk         (0x1UL << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */
-#define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */
-#define SDIO_DCTRL_RWSTOP_Pos          (9U)                                    
-#define SDIO_DCTRL_RWSTOP_Msk          (0x1UL << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */
-#define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */
-#define SDIO_DCTRL_RWMOD_Pos           (10U)                                   
-#define SDIO_DCTRL_RWMOD_Msk           (0x1UL << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */
-#define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */
-#define SDIO_DCTRL_SDIOEN_Pos          (11U)                                   
-#define SDIO_DCTRL_SDIOEN_Msk          (0x1UL << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */
-#define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */
-
-/******************  Bit definition for SDIO_DCOUNT register  *****************/
-#define SDIO_DCOUNT_DATACOUNT_Pos      (0U)                                    
-#define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
-#define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */
-
-/******************  Bit definition for SDIO_STA register  ********************/
-#define SDIO_STA_CCRCFAIL_Pos          (0U)                                    
-#define SDIO_STA_CCRCFAIL_Msk          (0x1UL << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */
-#define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */
-#define SDIO_STA_DCRCFAIL_Pos          (1U)                                    
-#define SDIO_STA_DCRCFAIL_Msk          (0x1UL << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */
-#define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */
-#define SDIO_STA_CTIMEOUT_Pos          (2U)                                    
-#define SDIO_STA_CTIMEOUT_Msk          (0x1UL << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */
-#define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */
-#define SDIO_STA_DTIMEOUT_Pos          (3U)                                    
-#define SDIO_STA_DTIMEOUT_Msk          (0x1UL << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */
-#define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */
-#define SDIO_STA_TXUNDERR_Pos          (4U)                                    
-#define SDIO_STA_TXUNDERR_Msk          (0x1UL << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */
-#define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */
-#define SDIO_STA_RXOVERR_Pos           (5U)                                    
-#define SDIO_STA_RXOVERR_Msk           (0x1UL << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */
-#define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */
-#define SDIO_STA_CMDREND_Pos           (6U)                                    
-#define SDIO_STA_CMDREND_Msk           (0x1UL << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */
-#define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */
-#define SDIO_STA_CMDSENT_Pos           (7U)                                    
-#define SDIO_STA_CMDSENT_Msk           (0x1UL << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */
-#define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */
-#define SDIO_STA_DATAEND_Pos           (8U)                                    
-#define SDIO_STA_DATAEND_Msk           (0x1UL << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */
-#define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */
-#define SDIO_STA_STBITERR_Pos          (9U)                                    
-#define SDIO_STA_STBITERR_Msk          (0x1UL << SDIO_STA_STBITERR_Pos)         /*!< 0x00000200 */
-#define SDIO_STA_STBITERR              SDIO_STA_STBITERR_Msk                   /*!<Start bit not detected on all data signals in wide bus mode */
-#define SDIO_STA_DBCKEND_Pos           (10U)                                   
-#define SDIO_STA_DBCKEND_Msk           (0x1UL << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */
-#define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */
-#define SDIO_STA_CMDACT_Pos            (11U)                                   
-#define SDIO_STA_CMDACT_Msk            (0x1UL << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */
-#define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */
-#define SDIO_STA_TXACT_Pos             (12U)                                   
-#define SDIO_STA_TXACT_Msk             (0x1UL << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */
-#define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */
-#define SDIO_STA_RXACT_Pos             (13U)                                   
-#define SDIO_STA_RXACT_Msk             (0x1UL << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */
-#define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */
-#define SDIO_STA_TXFIFOHE_Pos          (14U)                                   
-#define SDIO_STA_TXFIFOHE_Msk          (0x1UL << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */
-#define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
-#define SDIO_STA_RXFIFOHF_Pos          (15U)                                   
-#define SDIO_STA_RXFIFOHF_Msk          (0x1UL << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */
-#define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
-#define SDIO_STA_TXFIFOF_Pos           (16U)                                   
-#define SDIO_STA_TXFIFOF_Msk           (0x1UL << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */
-#define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */
-#define SDIO_STA_RXFIFOF_Pos           (17U)                                   
-#define SDIO_STA_RXFIFOF_Msk           (0x1UL << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */
-#define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */
-#define SDIO_STA_TXFIFOE_Pos           (18U)                                   
-#define SDIO_STA_TXFIFOE_Msk           (0x1UL << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */
-#define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */
-#define SDIO_STA_RXFIFOE_Pos           (19U)                                   
-#define SDIO_STA_RXFIFOE_Msk           (0x1UL << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */
-#define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */
-#define SDIO_STA_TXDAVL_Pos            (20U)                                   
-#define SDIO_STA_TXDAVL_Msk            (0x1UL << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */
-#define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */
-#define SDIO_STA_RXDAVL_Pos            (21U)                                   
-#define SDIO_STA_RXDAVL_Msk            (0x1UL << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */
-#define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */
-#define SDIO_STA_SDIOIT_Pos            (22U)                                   
-#define SDIO_STA_SDIOIT_Msk            (0x1UL << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */
-#define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */
-#define SDIO_STA_CEATAEND_Pos          (23U)                                   
-#define SDIO_STA_CEATAEND_Msk          (0x1UL << SDIO_STA_CEATAEND_Pos)         /*!< 0x00800000 */
-#define SDIO_STA_CEATAEND              SDIO_STA_CEATAEND_Msk                   /*!<CE-ATA command completion signal received for CMD61 */
-
-/*******************  Bit definition for SDIO_ICR register  *******************/
-#define SDIO_ICR_CCRCFAILC_Pos         (0U)                                    
-#define SDIO_ICR_CCRCFAILC_Msk         (0x1UL << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */
-#define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */
-#define SDIO_ICR_DCRCFAILC_Pos         (1U)                                    
-#define SDIO_ICR_DCRCFAILC_Msk         (0x1UL << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */
-#define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */
-#define SDIO_ICR_CTIMEOUTC_Pos         (2U)                                    
-#define SDIO_ICR_CTIMEOUTC_Msk         (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */
-#define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */
-#define SDIO_ICR_DTIMEOUTC_Pos         (3U)                                    
-#define SDIO_ICR_DTIMEOUTC_Msk         (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */
-#define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */
-#define SDIO_ICR_TXUNDERRC_Pos         (4U)                                    
-#define SDIO_ICR_TXUNDERRC_Msk         (0x1UL << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */
-#define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */
-#define SDIO_ICR_RXOVERRC_Pos          (5U)                                    
-#define SDIO_ICR_RXOVERRC_Msk          (0x1UL << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */
-#define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */
-#define SDIO_ICR_CMDRENDC_Pos          (6U)                                    
-#define SDIO_ICR_CMDRENDC_Msk          (0x1UL << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */
-#define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */
-#define SDIO_ICR_CMDSENTC_Pos          (7U)                                    
-#define SDIO_ICR_CMDSENTC_Msk          (0x1UL << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */
-#define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */
-#define SDIO_ICR_DATAENDC_Pos          (8U)                                    
-#define SDIO_ICR_DATAENDC_Msk          (0x1UL << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */
-#define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */
-#define SDIO_ICR_STBITERRC_Pos         (9U)                                    
-#define SDIO_ICR_STBITERRC_Msk         (0x1UL << SDIO_ICR_STBITERRC_Pos)        /*!< 0x00000200 */
-#define SDIO_ICR_STBITERRC             SDIO_ICR_STBITERRC_Msk                  /*!<STBITERR flag clear bit */
-#define SDIO_ICR_DBCKENDC_Pos          (10U)                                   
-#define SDIO_ICR_DBCKENDC_Msk          (0x1UL << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */
-#define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */
-#define SDIO_ICR_SDIOITC_Pos           (22U)                                   
-#define SDIO_ICR_SDIOITC_Msk           (0x1UL << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */
-#define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */
-#define SDIO_ICR_CEATAENDC_Pos         (23U)                                   
-#define SDIO_ICR_CEATAENDC_Msk         (0x1UL << SDIO_ICR_CEATAENDC_Pos)        /*!< 0x00800000 */
-#define SDIO_ICR_CEATAENDC             SDIO_ICR_CEATAENDC_Msk                  /*!<CEATAEND flag clear bit */
-
-/******************  Bit definition for SDIO_MASK register  *******************/
-#define SDIO_MASK_CCRCFAILIE_Pos       (0U)                                    
-#define SDIO_MASK_CCRCFAILIE_Msk       (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */
-#define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */
-#define SDIO_MASK_DCRCFAILIE_Pos       (1U)                                    
-#define SDIO_MASK_DCRCFAILIE_Msk       (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */
-#define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */
-#define SDIO_MASK_CTIMEOUTIE_Pos       (2U)                                    
-#define SDIO_MASK_CTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */
-#define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */
-#define SDIO_MASK_DTIMEOUTIE_Pos       (3U)                                    
-#define SDIO_MASK_DTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */
-#define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */
-#define SDIO_MASK_TXUNDERRIE_Pos       (4U)                                    
-#define SDIO_MASK_TXUNDERRIE_Msk       (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */
-#define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */
-#define SDIO_MASK_RXOVERRIE_Pos        (5U)                                    
-#define SDIO_MASK_RXOVERRIE_Msk        (0x1UL << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */
-#define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */
-#define SDIO_MASK_CMDRENDIE_Pos        (6U)                                    
-#define SDIO_MASK_CMDRENDIE_Msk        (0x1UL << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */
-#define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */
-#define SDIO_MASK_CMDSENTIE_Pos        (7U)                                    
-#define SDIO_MASK_CMDSENTIE_Msk        (0x1UL << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */
-#define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */
-#define SDIO_MASK_DATAENDIE_Pos        (8U)                                    
-#define SDIO_MASK_DATAENDIE_Msk        (0x1UL << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */
-#define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */
-#define SDIO_MASK_STBITERRIE_Pos       (9U)                                    
-#define SDIO_MASK_STBITERRIE_Msk       (0x1UL << SDIO_MASK_STBITERRIE_Pos)      /*!< 0x00000200 */
-#define SDIO_MASK_STBITERRIE           SDIO_MASK_STBITERRIE_Msk                /*!<Start Bit Error Interrupt Enable           */
-#define SDIO_MASK_DBCKENDIE_Pos        (10U)                                   
-#define SDIO_MASK_DBCKENDIE_Msk        (0x1UL << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */
-#define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */
-#define SDIO_MASK_CMDACTIE_Pos         (11U)                                   
-#define SDIO_MASK_CMDACTIE_Msk         (0x1UL << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */
-#define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */
-#define SDIO_MASK_TXACTIE_Pos          (12U)                                   
-#define SDIO_MASK_TXACTIE_Msk          (0x1UL << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */
-#define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */
-#define SDIO_MASK_RXACTIE_Pos          (13U)                                   
-#define SDIO_MASK_RXACTIE_Msk          (0x1UL << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */
-#define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */
-#define SDIO_MASK_TXFIFOHEIE_Pos       (14U)                                   
-#define SDIO_MASK_TXFIFOHEIE_Msk       (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */
-#define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */
-#define SDIO_MASK_RXFIFOHFIE_Pos       (15U)                                   
-#define SDIO_MASK_RXFIFOHFIE_Msk       (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */
-#define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */
-#define SDIO_MASK_TXFIFOFIE_Pos        (16U)                                   
-#define SDIO_MASK_TXFIFOFIE_Msk        (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */
-#define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */
-#define SDIO_MASK_RXFIFOFIE_Pos        (17U)                                   
-#define SDIO_MASK_RXFIFOFIE_Msk        (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */
-#define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */
-#define SDIO_MASK_TXFIFOEIE_Pos        (18U)                                   
-#define SDIO_MASK_TXFIFOEIE_Msk        (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */
-#define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */
-#define SDIO_MASK_RXFIFOEIE_Pos        (19U)                                   
-#define SDIO_MASK_RXFIFOEIE_Msk        (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */
-#define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */
-#define SDIO_MASK_TXDAVLIE_Pos         (20U)                                   
-#define SDIO_MASK_TXDAVLIE_Msk         (0x1UL << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */
-#define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */
-#define SDIO_MASK_RXDAVLIE_Pos         (21U)                                   
-#define SDIO_MASK_RXDAVLIE_Msk         (0x1UL << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */
-#define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */
-#define SDIO_MASK_SDIOITIE_Pos         (22U)                                   
-#define SDIO_MASK_SDIOITIE_Msk         (0x1UL << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */
-#define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */
-#define SDIO_MASK_CEATAENDIE_Pos       (23U)                                   
-#define SDIO_MASK_CEATAENDIE_Msk       (0x1UL << SDIO_MASK_CEATAENDIE_Pos)      /*!< 0x00800000 */
-#define SDIO_MASK_CEATAENDIE           SDIO_MASK_CEATAENDIE_Msk                /*!<CE-ATA command completion signal received Interrupt Enable */
-
-/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
-#define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)                                    
-#define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
-#define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */
-
-/******************  Bit definition for SDIO_FIFO register  *******************/
-#define SDIO_FIFO_FIFODATA_Pos         (0U)                                    
-#define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
-#define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface                         */
-/*                                                                            */
-/******************************************************************************/
-#define SPI_I2S_FULLDUPLEX_SUPPORT                                             /*!< I2S Full-Duplex support */
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA_Pos            (0U)                                       
-#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
-#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
-#define SPI_CR1_CPOL_Pos            (1U)                                       
-#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
-#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
-#define SPI_CR1_MSTR_Pos            (2U)                                       
-#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
-#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
-
-#define SPI_CR1_BR_Pos              (3U)                                       
-#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
-#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
-#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
-#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
-
-#define SPI_CR1_SPE_Pos             (6U)                                       
-#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
-#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
-#define SPI_CR1_LSBFIRST_Pos        (7U)                                       
-#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
-#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
-#define SPI_CR1_SSI_Pos             (8U)                                       
-#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
-#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
-#define SPI_CR1_SSM_Pos             (9U)                                       
-#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
-#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
-#define SPI_CR1_RXONLY_Pos          (10U)                                      
-#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
-#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
-#define SPI_CR1_DFF_Pos             (11U)                                      
-#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
-#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */
-#define SPI_CR1_CRCNEXT_Pos         (12U)                                      
-#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
-#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
-#define SPI_CR1_CRCEN_Pos           (13U)                                      
-#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
-#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
-#define SPI_CR1_BIDIOE_Pos          (14U)                                      
-#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
-#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE_Pos        (15U)                                      
-#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
-#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN_Pos         (0U)                                       
-#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
-#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */
-#define SPI_CR2_TXDMAEN_Pos         (1U)                                       
-#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
-#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */
-#define SPI_CR2_SSOE_Pos            (2U)                                       
-#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
-#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */
-#define SPI_CR2_FRF_Pos             (4U)                                       
-#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
-#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */
-#define SPI_CR2_ERRIE_Pos           (5U)                                       
-#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
-#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */
-#define SPI_CR2_RXNEIE_Pos          (6U)                                       
-#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
-#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE_Pos           (7U)                                       
-#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
-#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE_Pos             (0U)                                       
-#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
-#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */
-#define SPI_SR_TXE_Pos              (1U)                                       
-#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
-#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */
-#define SPI_SR_CHSIDE_Pos           (2U)                                       
-#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */
-#define SPI_SR_UDR_Pos              (3U)                                       
-#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */
-#define SPI_SR_CRCERR_Pos           (4U)                                       
-#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
-#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */
-#define SPI_SR_MODF_Pos             (5U)                                       
-#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
-#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */
-#define SPI_SR_OVR_Pos              (6U)                                       
-#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
-#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */
-#define SPI_SR_BSY_Pos              (7U)                                       
-#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
-#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */
-#define SPI_SR_FRE_Pos              (8U)                                       
-#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
-#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR_Pos               (0U)                                       
-#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
-#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY_Pos       (0U)                                       
-#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
-#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC_Pos        (0U)                                       
-#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC_Pos        (0U)                                       
-#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
-#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN_Pos       (0U)                                       
-#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
-#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
-
-#define SPI_I2SCFGR_DATLEN_Pos      (1U)                                       
-#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
-#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */
-#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
-#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
-
-#define SPI_I2SCFGR_CKPOL_Pos       (3U)                                       
-#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
-#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */
-
-#define SPI_I2SCFGR_I2SSTD_Pos      (4U)                                       
-#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
-#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
-#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
-
-#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)                                       
-#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
-#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */
-
-#define SPI_I2SCFGR_I2SCFG_Pos      (8U)                                       
-#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
-#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
-#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
-
-#define SPI_I2SCFGR_I2SE_Pos        (10U)                                      
-#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
-#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */
-#define SPI_I2SCFGR_I2SMOD_Pos      (11U)                                      
-#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
-#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV_Pos        (0U)                                       
-#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
-#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */
-#define SPI_I2SPR_ODD_Pos           (8U)                                       
-#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
-#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE_Pos         (9U)                                       
-#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
-#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                 SYSCFG                                     */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for SYSCFG_MEMRMP register  ***************/
-#define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)                              
-#define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
-#define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0             (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
-#define SYSCFG_MEMRMP_MEM_MODE_1             (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
-/******************  Bit definition for SYSCFG_PMC register  ******************/
-#define SYSCFG_PMC_MII_RMII_SEL_Pos          (23U)                             
-#define SYSCFG_PMC_MII_RMII_SEL_Msk          (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
-#define SYSCFG_PMC_MII_RMII_SEL              SYSCFG_PMC_MII_RMII_SEL_Msk       /*!<Ethernet PHY interface selection */
-/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
-#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL    
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0_Pos             (0U)                              
-#define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1_Pos             (4U)                              
-#define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2_Pos             (8U)                              
-#define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3_Pos             (12U)                             
-#define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */
-/**
-  * @brief   EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PI              0x0008U                           /*!<PI[0] pin */
-
-/**
-  * @brief   EXTI1 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PI              0x0080U                           /*!<PI[1] pin */
-
-/**
-  * @brief   EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PI              0x0800U                           /*!<PI[2] pin */
-
-/**
-  * @brief   EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PI              0x8000U                           /*!<PI[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
-#define SYSCFG_EXTICR2_EXTI4_Pos             (0U)                              
-#define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5_Pos             (4U)                              
-#define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6_Pos             (8U)                              
-#define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7_Pos             (12U)                             
-#define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */
-
-/**
-  * @brief   EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PI              0x0008U                           /*!<PI[4] pin */
-
-/**
-  * @brief   EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PI              0x0080U                           /*!<PI[5] pin */
-
-/**
-  * @brief   EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PI              0x0800U                           /*!<PI[6] pin */
-
-/**
-  * @brief   EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PI              0x8000U                           /*!<PI[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
-#define SYSCFG_EXTICR3_EXTI8_Pos             (0U)                              
-#define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9_Pos             (4U)                              
-#define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10_Pos            (8U)                              
-#define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11_Pos            (12U)                             
-#define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */
-
-/**
-  * @brief   EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PI              0x0008U                           /*!<PI[8] pin */
-
-/**
-  * @brief   EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PI              0x0080U                           /*!<PI[9] pin */
-
-/**
-  * @brief   EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PI             0x0800U                           /*!<PI[10] pin */
-
-/**
-  * @brief   EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PI             0x8000U                           /*!<PI[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
-#define SYSCFG_EXTICR4_EXTI12_Pos            (0U)                              
-#define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
-#define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13_Pos            (4U)                              
-#define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
-#define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14_Pos            (8U)                              
-#define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
-#define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15_Pos            (12U)                             
-#define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
-#define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */
-
-/**
-  * @brief   EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */
-
-/**
-  * @brief   EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */
-
-/**
-  * @brief   EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */
-
-/**
-  * @brief   EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */
-
-/******************  Bit definition for SYSCFG_CMPCR register  ****************/
-#define SYSCFG_CMPCR_CMP_PD_Pos              (0U)                              
-#define SYSCFG_CMPCR_CMP_PD_Msk              (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
-#define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */
-#define SYSCFG_CMPCR_READY_Pos               (8U)                              
-#define SYSCFG_CMPCR_READY_Msk               (0x1UL << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */
-#define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    TIM                                     */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN_Pos           (0U)                                         
-#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
-#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */
-#define TIM_CR1_UDIS_Pos          (1U)                                         
-#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
-#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */
-#define TIM_CR1_URS_Pos           (2U)                                         
-#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
-#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
-#define TIM_CR1_OPM_Pos           (3U)                                         
-#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
-#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */
-#define TIM_CR1_DIR_Pos           (4U)                                         
-#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
-#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */
-
-#define TIM_CR1_CMS_Pos           (5U)                                         
-#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
-#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */
-#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */
-
-#define TIM_CR1_ARPE_Pos          (7U)                                         
-#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
-#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */
-
-#define TIM_CR1_CKD_Pos           (8U)                                         
-#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
-#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */
-#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCPC_Pos          (0U)                                         
-#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
-#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */
-#define TIM_CR2_CCUS_Pos          (2U)                                         
-#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
-#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS_Pos          (3U)                                         
-#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
-#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */
-
-#define TIM_CR2_MMS_Pos           (4U)                                         
-#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
-#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */
-#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */
-#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */
-
-#define TIM_CR2_TI1S_Pos          (7U)                                         
-#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
-#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
-#define TIM_CR2_OIS1_Pos          (8U)                                         
-#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
-#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */
-#define TIM_CR2_OIS1N_Pos         (9U)                                         
-#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
-#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2_Pos          (10U)                                        
-#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
-#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */
-#define TIM_CR2_OIS2N_Pos         (11U)                                        
-#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
-#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3_Pos          (12U)                                        
-#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
-#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */
-#define TIM_CR2_OIS3N_Pos         (13U)                                        
-#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
-#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4_Pos          (14U)                                        
-#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
-#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS_Pos          (0U)                                         
-#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
-#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */
-#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */
-#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */
-#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */
-
-#define TIM_SMCR_TS_Pos           (4U)                                         
-#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
-#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */
-#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */
-#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */
-#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */
-
-#define TIM_SMCR_MSM_Pos          (7U)                                         
-#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
-#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */
-
-#define TIM_SMCR_ETF_Pos          (8U)                                         
-#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
-#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */
-#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */
-#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */
-#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */
-
-#define TIM_SMCR_ETPS_Pos         (12U)                                        
-#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
-#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */
-#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */
-
-#define TIM_SMCR_ECE_Pos          (14U)                                        
-#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
-#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */
-#define TIM_SMCR_ETP_Pos          (15U)                                        
-#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
-#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE_Pos          (0U)                                         
-#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
-#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE_Pos        (1U)                                         
-#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
-#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */
-#define TIM_DIER_CC2IE_Pos        (2U)                                         
-#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
-#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */
-#define TIM_DIER_CC3IE_Pos        (3U)                                         
-#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
-#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */
-#define TIM_DIER_CC4IE_Pos        (4U)                                         
-#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
-#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */
-#define TIM_DIER_COMIE_Pos        (5U)                                         
-#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
-#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */
-#define TIM_DIER_TIE_Pos          (6U)                                         
-#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
-#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */
-#define TIM_DIER_BIE_Pos          (7U)                                         
-#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
-#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */
-#define TIM_DIER_UDE_Pos          (8U)                                         
-#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
-#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */
-#define TIM_DIER_CC1DE_Pos        (9U)                                         
-#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
-#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE_Pos        (10U)                                        
-#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
-#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE_Pos        (11U)                                        
-#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
-#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE_Pos        (12U)                                        
-#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
-#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE_Pos        (13U)                                        
-#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
-#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */
-#define TIM_DIER_TDE_Pos          (14U)                                        
-#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
-#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF_Pos            (0U)                                         
-#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
-#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */
-#define TIM_SR_CC1IF_Pos          (1U)                                         
-#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
-#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */
-#define TIM_SR_CC2IF_Pos          (2U)                                         
-#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
-#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */
-#define TIM_SR_CC3IF_Pos          (3U)                                         
-#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
-#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */
-#define TIM_SR_CC4IF_Pos          (4U)                                         
-#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
-#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */
-#define TIM_SR_COMIF_Pos          (5U)                                         
-#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
-#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */
-#define TIM_SR_TIF_Pos            (6U)                                         
-#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
-#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */
-#define TIM_SR_BIF_Pos            (7U)                                         
-#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
-#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */
-#define TIM_SR_CC1OF_Pos          (9U)                                         
-#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
-#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF_Pos          (10U)                                        
-#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
-#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF_Pos          (11U)                                        
-#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
-#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF_Pos          (12U)                                        
-#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
-#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG_Pos            (0U)                                         
-#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
-#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */
-#define TIM_EGR_CC1G_Pos          (1U)                                         
-#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
-#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */
-#define TIM_EGR_CC2G_Pos          (2U)                                         
-#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
-#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */
-#define TIM_EGR_CC3G_Pos          (3U)                                         
-#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
-#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */
-#define TIM_EGR_CC4G_Pos          (4U)                                         
-#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
-#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */
-#define TIM_EGR_COMG_Pos          (5U)                                         
-#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
-#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG_Pos            (6U)                                         
-#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
-#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */
-#define TIM_EGR_BG_Pos            (7U)                                         
-#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
-#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S_Pos        (0U)                                         
-#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */
-#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */
-
-#define TIM_CCMR1_OC1FE_Pos       (2U)                                         
-#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */
-#define TIM_CCMR1_OC1PE_Pos       (3U)                                         
-#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */
-
-#define TIM_CCMR1_OC1M_Pos        (4U)                                         
-#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
-#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */
-#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */
-#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */
-
-#define TIM_CCMR1_OC1CE_Pos       (7U)                                         
-#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */
-
-#define TIM_CCMR1_CC2S_Pos        (8U)                                         
-#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */
-#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */
-
-#define TIM_CCMR1_OC2FE_Pos       (10U)                                        
-#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */
-#define TIM_CCMR1_OC2PE_Pos       (11U)                                        
-#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */
-
-#define TIM_CCMR1_OC2M_Pos        (12U)                                        
-#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
-#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */
-#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */
-#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */
-
-#define TIM_CCMR1_OC2CE_Pos       (15U)                                        
-#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         
-#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */
-#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */
-
-#define TIM_CCMR1_IC1F_Pos        (4U)                                         
-#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
-#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */
-#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */
-#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */
-#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */
-
-#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        
-#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
-#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */
-#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */
-
-#define TIM_CCMR1_IC2F_Pos        (12U)                                        
-#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
-#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */
-#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */
-#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */
-#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S_Pos        (0U)                                         
-#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
-#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
-#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */
-#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */
-
-#define TIM_CCMR2_OC3FE_Pos       (2U)                                         
-#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
-#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */
-#define TIM_CCMR2_OC3PE_Pos       (3U)                                         
-#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
-#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */
-
-#define TIM_CCMR2_OC3M_Pos        (4U)                                         
-#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
-#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */
-#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */
-#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */
-
-#define TIM_CCMR2_OC3CE_Pos       (7U)                                         
-#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
-#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S_Pos        (8U)                                         
-#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
-#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */
-#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */
-
-#define TIM_CCMR2_OC4FE_Pos       (10U)                                        
-#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
-#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */
-#define TIM_CCMR2_OC4PE_Pos       (11U)                                        
-#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
-#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M_Pos        (12U)                                        
-#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
-#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */
-#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */
-#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */
-
-#define TIM_CCMR2_OC4CE_Pos       (15U)                                        
-#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
-#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         
-#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
-#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */
-#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */
-
-#define TIM_CCMR2_IC3F_Pos        (4U)                                         
-#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
-#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */
-#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */
-#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */
-#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */
-
-#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        
-#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
-#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */
-#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */
-
-#define TIM_CCMR2_IC4F_Pos        (12U)                                        
-#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
-#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */
-#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */
-#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */
-#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E_Pos         (0U)                                         
-#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
-#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */
-#define TIM_CCER_CC1P_Pos         (1U)                                         
-#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
-#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */
-#define TIM_CCER_CC1NE_Pos        (2U)                                         
-#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
-#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */
-#define TIM_CCER_CC1NP_Pos        (3U)                                         
-#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
-#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E_Pos         (4U)                                         
-#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
-#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */
-#define TIM_CCER_CC2P_Pos         (5U)                                         
-#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
-#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */
-#define TIM_CCER_CC2NE_Pos        (6U)                                         
-#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
-#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */
-#define TIM_CCER_CC2NP_Pos        (7U)                                         
-#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
-#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E_Pos         (8U)                                         
-#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
-#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */
-#define TIM_CCER_CC3P_Pos         (9U)                                         
-#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
-#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */
-#define TIM_CCER_CC3NE_Pos        (10U)                                        
-#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
-#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */
-#define TIM_CCER_CC3NP_Pos        (11U)                                        
-#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
-#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E_Pos         (12U)                                        
-#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
-#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */
-#define TIM_CCER_CC4P_Pos         (13U)                                        
-#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
-#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */
-#define TIM_CCER_CC4NP_Pos        (15U)                                        
-#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
-#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT_Pos           (0U)                                             
-#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */
-#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC_Pos           (0U)                                         
-#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
-#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR_Pos           (0U)                                         
-#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
-#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define TIM_RCR_REP_Pos           (0U)                                         
-#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */
-#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1_Pos         (0U)                                         
-#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2_Pos         (0U)                                         
-#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3_Pos         (0U)                                         
-#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4_Pos         (0U)                                         
-#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
-#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define TIM_BDTR_DTG_Pos          (0U)                                         
-#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
-#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */
-#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */
-#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */
-#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */
-#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */
-#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */
-#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */
-#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */
-
-#define TIM_BDTR_LOCK_Pos         (8U)                                         
-#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
-#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */
-#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */
-
-#define TIM_BDTR_OSSI_Pos         (10U)                                        
-#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
-#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR_Pos         (11U)                                        
-#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
-#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */
-#define TIM_BDTR_BKE_Pos          (12U)                                        
-#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
-#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */
-#define TIM_BDTR_BKP_Pos          (13U)                                        
-#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
-#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */
-#define TIM_BDTR_AOE_Pos          (14U)                                        
-#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
-#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */
-#define TIM_BDTR_MOE_Pos          (15U)                                        
-#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
-#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA_Pos           (0U)                                         
-#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
-#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */
-#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */
-#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */
-#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */
-#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */
-
-#define TIM_DCR_DBL_Pos           (8U)                                         
-#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
-#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */
-#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */
-#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */
-#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */
-#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB_Pos         (0U)                                         
-#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
-#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM_OR_TI1_RMP_Pos        (0U)                                          
-#define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */
-#define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
-#define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */
-#define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */
-
-#define TIM_OR_TI4_RMP_Pos        (6U)                                         
-#define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */
-#define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
-#define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */
-#define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */
-#define TIM_OR_ITR1_RMP_Pos       (10U)                                        
-#define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */
-#define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
-#define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */
-#define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*         Universal Synchronous Asynchronous Receiver Transmitter            */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for USART_SR register  *******************/
-#define USART_SR_PE_Pos               (0U)                                     
-#define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */
-#define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */
-#define USART_SR_FE_Pos               (1U)                                     
-#define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */
-#define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */
-#define USART_SR_NE_Pos               (2U)                                     
-#define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */
-#define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */
-#define USART_SR_ORE_Pos              (3U)                                     
-#define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */
-#define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */
-#define USART_SR_IDLE_Pos             (4U)                                     
-#define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */
-#define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */
-#define USART_SR_RXNE_Pos             (5U)                                     
-#define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */
-#define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */
-#define USART_SR_TC_Pos               (6U)                                     
-#define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */
-#define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */
-#define USART_SR_TXE_Pos              (7U)                                     
-#define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */
-#define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */
-#define USART_SR_LBD_Pos              (8U)                                     
-#define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */
-#define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */
-#define USART_SR_CTS_Pos              (9U)                                     
-#define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */
-#define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define USART_DR_DR_Pos               (0U)                                     
-#define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */
-#define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_Fraction_Pos    (0U)                                     
-#define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */
-#define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */
-#define USART_BRR_DIV_Mantissa_Pos    (4U)                                     
-#define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */
-#define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_SBK_Pos             (0U)                                     
-#define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */
-#define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */
-#define USART_CR1_RWU_Pos             (1U)                                     
-#define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */
-#define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */
-#define USART_CR1_RE_Pos              (2U)                                     
-#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
-#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */
-#define USART_CR1_TE_Pos              (3U)                                     
-#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
-#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */
-#define USART_CR1_IDLEIE_Pos          (4U)                                     
-#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
-#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */
-#define USART_CR1_RXNEIE_Pos          (5U)                                     
-#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
-#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */
-#define USART_CR1_TCIE_Pos            (6U)                                     
-#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
-#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE_Pos           (7U)                                     
-#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
-#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */
-#define USART_CR1_PEIE_Pos            (8U)                                     
-#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
-#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */
-#define USART_CR1_PS_Pos              (9U)                                     
-#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
-#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */
-#define USART_CR1_PCE_Pos             (10U)                                    
-#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
-#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */
-#define USART_CR1_WAKE_Pos            (11U)                                    
-#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
-#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */
-#define USART_CR1_M_Pos               (12U)                                    
-#define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */
-#define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */
-#define USART_CR1_UE_Pos              (13U)                                    
-#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */
-#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */
-#define USART_CR1_OVER8_Pos           (15U)                                    
-#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
-#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADD_Pos             (0U)                                     
-#define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */
-#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */
-#define USART_CR2_LBDL_Pos            (5U)                                     
-#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
-#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */
-#define USART_CR2_LBDIE_Pos           (6U)                                     
-#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
-#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL_Pos            (8U)                                     
-#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
-#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */
-#define USART_CR2_CPHA_Pos            (9U)                                     
-#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
-#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */
-#define USART_CR2_CPOL_Pos            (10U)                                    
-#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
-#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */
-#define USART_CR2_CLKEN_Pos           (11U)                                    
-#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
-#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */
-
-#define USART_CR2_STOP_Pos            (12U)                                    
-#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
-#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x1000 */
-#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x2000 */
-
-#define USART_CR2_LINEN_Pos           (14U)                                    
-#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
-#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE_Pos             (0U)                                     
-#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
-#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */
-#define USART_CR3_IREN_Pos            (1U)                                     
-#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
-#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */
-#define USART_CR3_IRLP_Pos            (2U)                                     
-#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
-#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */
-#define USART_CR3_HDSEL_Pos           (3U)                                     
-#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
-#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */
-#define USART_CR3_NACK_Pos            (4U)                                     
-#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
-#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */
-#define USART_CR3_SCEN_Pos            (5U)                                     
-#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
-#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */
-#define USART_CR3_DMAR_Pos            (6U)                                     
-#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
-#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */
-#define USART_CR3_DMAT_Pos            (7U)                                     
-#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
-#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */
-#define USART_CR3_RTSE_Pos            (8U)                                     
-#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
-#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */
-#define USART_CR3_CTSE_Pos            (9U)                                     
-#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
-#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */
-#define USART_CR3_CTSIE_Pos           (10U)                                    
-#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
-#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */
-#define USART_CR3_ONEBIT_Pos          (11U)                                    
-#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
-#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC_Pos            (0U)                                     
-#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
-#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x0001 */
-#define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x0002 */
-#define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x0004 */
-#define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x0008 */
-#define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x0010 */
-#define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x0020 */
-#define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x0040 */
-#define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x0080 */
-
-#define USART_GTPR_GT_Pos             (8U)                                     
-#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
-#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            Window WATCHDOG                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T_Pos           (0U)                                           
-#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
-#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */
-#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */
-#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */
-#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */
-#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */
-#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */
-#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */
-/* Legacy defines */
-#define  WWDG_CR_T0                          WWDG_CR_T_0
-#define  WWDG_CR_T1                          WWDG_CR_T_1
-#define  WWDG_CR_T2                          WWDG_CR_T_2
-#define  WWDG_CR_T3                          WWDG_CR_T_3
-#define  WWDG_CR_T4                          WWDG_CR_T_4
-#define  WWDG_CR_T5                          WWDG_CR_T_5
-#define  WWDG_CR_T6                          WWDG_CR_T_6
-
-#define WWDG_CR_WDGA_Pos        (7U)                                           
-#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
-#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W_Pos          (0U)                                           
-#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
-#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */
-#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */
-#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */
-#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */
-#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */
-#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */
-#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */
-/* Legacy defines */
-#define  WWDG_CFR_W0                         WWDG_CFR_W_0
-#define  WWDG_CFR_W1                         WWDG_CFR_W_1
-#define  WWDG_CFR_W2                         WWDG_CFR_W_2
-#define  WWDG_CFR_W3                         WWDG_CFR_W_3
-#define  WWDG_CFR_W4                         WWDG_CFR_W_4
-#define  WWDG_CFR_W5                         WWDG_CFR_W_5
-#define  WWDG_CFR_W6                         WWDG_CFR_W_6
-
-#define WWDG_CFR_WDGTB_Pos      (7U)                                           
-#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
-#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */
-#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */
-/* Legacy defines */
-#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
-#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
-
-#define WWDG_CFR_EWI_Pos        (9U)                                           
-#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
-#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF_Pos        (0U)                                           
-#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
-#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                                DBG                                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DBGMCU_IDCODE register  *************/
-#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)                      
-#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
-#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk  
-#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)                     
-#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
-#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk  
-
-/********************  Bit definition for DBGMCU_CR register  *****************/
-#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)                      
-#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
-#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk   
-#define DBGMCU_CR_DBG_STOP_Pos                       (1U)                      
-#define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk    
-#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)                      
-#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
-#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk 
-#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)                      
-#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
-#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk  
-
-#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)                      
-#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
-#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk  
-#define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
-#define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
-
-/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)                      
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)                      
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)                      
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)                      
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)                      
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)                      
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)                      
-#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
-#define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)                      
-#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
-#define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)                      
-#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
-#define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)                     
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)                     
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)                     
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)                     
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk 
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)                     
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk 
-#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)                     
-#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
-#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk 
-#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)                     
-#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
-#define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk 
-#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)                     
-#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
-#define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk 
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */
-#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
-
-/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
-#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)                      
-#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
-#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk 
-#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)                      
-#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
-#define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk 
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)                     
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
-#define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk 
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)                     
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
-#define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk 
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)                     
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
-#define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk 
-
-/******************************************************************************/
-/*                                                                            */
-/*                Ethernet MAC Registers bits definitions                     */
-/*                                                                            */
-/******************************************************************************/
-/* Bit definition for Ethernet MAC Control Register register */
-#define ETH_MACCR_WD_Pos                              (23U)                    
-#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
-#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
-#define ETH_MACCR_JD_Pos                              (22U)                    
-#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
-#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
-#define ETH_MACCR_IFG_Pos                             (17U)                    
-#define ETH_MACCR_IFG_Msk                             (0x7UL << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
-#define ETH_MACCR_IFG                                 ETH_MACCR_IFG_Msk        /* Inter-frame gap */
-#define ETH_MACCR_IFG_96Bit                           0x00000000U              /* Minimum IFG between frames during transmission is 96Bit */
-#define ETH_MACCR_IFG_88Bit                           0x00020000U              /* Minimum IFG between frames during transmission is 88Bit */
-#define ETH_MACCR_IFG_80Bit                           0x00040000U              /* Minimum IFG between frames during transmission is 80Bit */
-#define ETH_MACCR_IFG_72Bit                           0x00060000U              /* Minimum IFG between frames during transmission is 72Bit */
-#define ETH_MACCR_IFG_64Bit                           0x00080000U              /* Minimum IFG between frames during transmission is 64Bit */
-#define ETH_MACCR_IFG_56Bit                           0x000A0000U              /* Minimum IFG between frames during transmission is 56Bit */
-#define ETH_MACCR_IFG_48Bit                           0x000C0000U              /* Minimum IFG between frames during transmission is 48Bit */
-#define ETH_MACCR_IFG_40Bit                           0x000E0000U              /* Minimum IFG between frames during transmission is 40Bit */
-#define ETH_MACCR_CSD_Pos                             (16U)                    
-#define ETH_MACCR_CSD_Msk                             (0x1UL << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
-#define ETH_MACCR_CSD                                 ETH_MACCR_CSD_Msk        /* Carrier sense disable (during transmission) */
-#define ETH_MACCR_FES_Pos                             (14U)                    
-#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
-#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
-#define ETH_MACCR_ROD_Pos                             (13U)                    
-#define ETH_MACCR_ROD_Msk                             (0x1UL << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
-#define ETH_MACCR_ROD                                 ETH_MACCR_ROD_Msk        /* Receive own disable */
-#define ETH_MACCR_LM_Pos                              (12U)                    
-#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
-#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
-#define ETH_MACCR_DM_Pos                              (11U)                    
-#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
-#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
-#define ETH_MACCR_IPCO_Pos                            (10U)                    
-#define ETH_MACCR_IPCO_Msk                            (0x1UL << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
-#define ETH_MACCR_IPCO                                ETH_MACCR_IPCO_Msk       /* IP Checksum offload */
-#define ETH_MACCR_RD_Pos                              (9U)                     
-#define ETH_MACCR_RD_Msk                              (0x1UL << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
-#define ETH_MACCR_RD                                  ETH_MACCR_RD_Msk         /* Retry disable */
-#define ETH_MACCR_APCS_Pos                            (7U)                     
-#define ETH_MACCR_APCS_Msk                            (0x1UL << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
-#define ETH_MACCR_APCS                                ETH_MACCR_APCS_Msk       /* Automatic Pad/CRC stripping */
-#define ETH_MACCR_BL_Pos                              (5U)                     
-#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
-#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit: random integer number (r) of slot time delays before rescheduling
-                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
-#define ETH_MACCR_BL_10                               0x00000000U              /* k = min (n, 10) */
-#define ETH_MACCR_BL_8                                0x00000020U              /* k = min (n, 8) */
-#define ETH_MACCR_BL_4                                0x00000040U              /* k = min (n, 4) */
-#define ETH_MACCR_BL_1                                0x00000060U              /* k = min (n, 1) */ 
-#define ETH_MACCR_DC_Pos                              (4U)                     
-#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
-#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
-#define ETH_MACCR_TE_Pos                              (3U)                     
-#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
-#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
-#define ETH_MACCR_RE_Pos                              (2U)                     
-#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
-#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
-
-/* Bit definition for Ethernet MAC Frame Filter Register */
-#define ETH_MACFFR_RA_Pos                             (31U)                    
-#define ETH_MACFFR_RA_Msk                             (0x1UL << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
-#define ETH_MACFFR_RA                                 ETH_MACFFR_RA_Msk        /* Receive all */
-#define ETH_MACFFR_HPF_Pos                            (10U)                    
-#define ETH_MACFFR_HPF_Msk                            (0x1UL << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
-#define ETH_MACFFR_HPF                                ETH_MACFFR_HPF_Msk       /* Hash or perfect filter */
-#define ETH_MACFFR_SAF_Pos                            (9U)                     
-#define ETH_MACFFR_SAF_Msk                            (0x1UL << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
-#define ETH_MACFFR_SAF                                ETH_MACFFR_SAF_Msk       /* Source address filter enable */
-#define ETH_MACFFR_SAIF_Pos                           (8U)                     
-#define ETH_MACFFR_SAIF_Msk                           (0x1UL << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
-#define ETH_MACFFR_SAIF                               ETH_MACFFR_SAIF_Msk      /* SA inverse filtering */ 
-#define ETH_MACFFR_PCF_Pos                            (6U)                     
-#define ETH_MACFFR_PCF_Msk                            (0x3UL << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
-#define ETH_MACFFR_PCF                                ETH_MACFFR_PCF_Msk       /* Pass control frames: 3 cases */
-#define ETH_MACFFR_PCF_BlockAll_Pos                   (6U)                     
-#define ETH_MACFFR_PCF_BlockAll_Msk                   (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
-#define ETH_MACFFR_PCF_BlockAll                       ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
-#define ETH_MACFFR_PCF_ForwardAll_Pos                 (7U)                     
-#define ETH_MACFFR_PCF_ForwardAll_Msk                 (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
-#define ETH_MACFFR_PCF_ForwardAll                     ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
-#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos    (6U)                     
-#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk    (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
-#define ETH_MACFFR_PCF_ForwardPassedAddrFilter        ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */ 
-#define ETH_MACFFR_BFD_Pos                            (5U)                     
-#define ETH_MACFFR_BFD_Msk                            (0x1UL << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
-#define ETH_MACFFR_BFD                                ETH_MACFFR_BFD_Msk       /* Broadcast frame disable */ 
-#define ETH_MACFFR_PAM_Pos                            (4U)                     
-#define ETH_MACFFR_PAM_Msk                            (0x1UL << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
-#define ETH_MACFFR_PAM                                ETH_MACFFR_PAM_Msk       /* Pass all mutlicast */
-#define ETH_MACFFR_DAIF_Pos                           (3U)                     
-#define ETH_MACFFR_DAIF_Msk                           (0x1UL << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
-#define ETH_MACFFR_DAIF                               ETH_MACFFR_DAIF_Msk      /* DA Inverse filtering */
-#define ETH_MACFFR_HM_Pos                             (2U)                     
-#define ETH_MACFFR_HM_Msk                             (0x1UL << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
-#define ETH_MACFFR_HM                                 ETH_MACFFR_HM_Msk        /* Hash multicast */ 
-#define ETH_MACFFR_HU_Pos                             (1U)                     
-#define ETH_MACFFR_HU_Msk                             (0x1UL << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
-#define ETH_MACFFR_HU                                 ETH_MACFFR_HU_Msk        /* Hash unicast */
-#define ETH_MACFFR_PM_Pos                             (0U)                     
-#define ETH_MACFFR_PM_Msk                             (0x1UL << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
-#define ETH_MACFFR_PM                                 ETH_MACFFR_PM_Msk        /* Promiscuous mode */
-
-/* Bit definition for Ethernet MAC Hash Table High Register */
-#define ETH_MACHTHR_HTH_Pos                           (0U)                     
-#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
-#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
-
-/* Bit definition for Ethernet MAC Hash Table Low Register */
-#define ETH_MACHTLR_HTL_Pos                           (0U)                     
-#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
-#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
-
-/* Bit definition for Ethernet MAC MII Address Register */
-#define ETH_MACMIIAR_PA_Pos                           (11U)                    
-#define ETH_MACMIIAR_PA_Msk                           (0x1FUL << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
-#define ETH_MACMIIAR_PA                               ETH_MACMIIAR_PA_Msk      /* Physical layer address */
-#define ETH_MACMIIAR_MR_Pos                           (6U)                     
-#define ETH_MACMIIAR_MR_Msk                           (0x1FUL << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
-#define ETH_MACMIIAR_MR                               ETH_MACMIIAR_MR_Msk      /* MII register in the selected PHY */
-#define ETH_MACMIIAR_CR_Pos                           (2U)                     
-#define ETH_MACMIIAR_CR_Msk                           (0x7UL << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
-#define ETH_MACMIIAR_CR                               ETH_MACMIIAR_CR_Msk      /* CR clock range: 6 cases */
-#define ETH_MACMIIAR_CR_Div42                         0x00000000U              /* HCLK:60-100 MHz; MDC clock= HCLK/42   */
-#define ETH_MACMIIAR_CR_Div62_Pos                     (2U)                     
-#define ETH_MACMIIAR_CR_Div62_Msk                     (0x1UL << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
-#define ETH_MACMIIAR_CR_Div62                         ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62  */
-#define ETH_MACMIIAR_CR_Div16_Pos                     (3U)                     
-#define ETH_MACMIIAR_CR_Div16_Msk                     (0x1UL << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
-#define ETH_MACMIIAR_CR_Div16                         ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16    */
-#define ETH_MACMIIAR_CR_Div26_Pos                     (2U)                     
-#define ETH_MACMIIAR_CR_Div26_Msk                     (0x3UL << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
-#define ETH_MACMIIAR_CR_Div26                         ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26    */
-#define ETH_MACMIIAR_CR_Div102_Pos                    (4U)                     
-#define ETH_MACMIIAR_CR_Div102_Msk                    (0x1UL << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
-#define ETH_MACMIIAR_CR_Div102                        ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
-#define ETH_MACMIIAR_MW_Pos                           (1U)                     
-#define ETH_MACMIIAR_MW_Msk                           (0x1UL << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
-#define ETH_MACMIIAR_MW                               ETH_MACMIIAR_MW_Msk      /* MII write */
-#define ETH_MACMIIAR_MB_Pos                           (0U)                     
-#define ETH_MACMIIAR_MB_Msk                           (0x1UL << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
-#define ETH_MACMIIAR_MB                               ETH_MACMIIAR_MB_Msk      /* MII busy  */
-
-/* Bit definition for Ethernet MAC MII Data Register */
-#define ETH_MACMIIDR_MD_Pos                           (0U)                     
-#define ETH_MACMIIDR_MD_Msk                           (0xFFFFUL << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
-#define ETH_MACMIIDR_MD                               ETH_MACMIIDR_MD_Msk      /* MII data: read/write data from/to PHY */
-
-/* Bit definition for Ethernet MAC Flow Control Register */
-#define ETH_MACFCR_PT_Pos                             (16U)                    
-#define ETH_MACFCR_PT_Msk                             (0xFFFFUL << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
-#define ETH_MACFCR_PT                                 ETH_MACFCR_PT_Msk        /* Pause time */
-#define ETH_MACFCR_ZQPD_Pos                           (7U)                     
-#define ETH_MACFCR_ZQPD_Msk                           (0x1UL << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
-#define ETH_MACFCR_ZQPD                               ETH_MACFCR_ZQPD_Msk      /* Zero-quanta pause disable */
-#define ETH_MACFCR_PLT_Pos                            (4U)                     
-#define ETH_MACFCR_PLT_Msk                            (0x3UL << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
-#define ETH_MACFCR_PLT                                ETH_MACFCR_PLT_Msk       /* Pause low threshold: 4 cases */
-#define ETH_MACFCR_PLT_Minus4                         0x00000000U              /* Pause time minus 4 slot times   */
-#define ETH_MACFCR_PLT_Minus28_Pos                    (4U)                     
-#define ETH_MACFCR_PLT_Minus28_Msk                    (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
-#define ETH_MACFCR_PLT_Minus28                        ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times  */
-#define ETH_MACFCR_PLT_Minus144_Pos                   (5U)                     
-#define ETH_MACFCR_PLT_Minus144_Msk                   (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
-#define ETH_MACFCR_PLT_Minus144                       ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
-#define ETH_MACFCR_PLT_Minus256_Pos                   (4U)                     
-#define ETH_MACFCR_PLT_Minus256_Msk                   (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
-#define ETH_MACFCR_PLT_Minus256                       ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
-#define ETH_MACFCR_UPFD_Pos                           (3U)                     
-#define ETH_MACFCR_UPFD_Msk                           (0x1UL << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
-#define ETH_MACFCR_UPFD                               ETH_MACFCR_UPFD_Msk      /* Unicast pause frame detect */
-#define ETH_MACFCR_RFCE_Pos                           (2U)                     
-#define ETH_MACFCR_RFCE_Msk                           (0x1UL << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
-#define ETH_MACFCR_RFCE                               ETH_MACFCR_RFCE_Msk      /* Receive flow control enable */
-#define ETH_MACFCR_TFCE_Pos                           (1U)                     
-#define ETH_MACFCR_TFCE_Msk                           (0x1UL << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
-#define ETH_MACFCR_TFCE                               ETH_MACFCR_TFCE_Msk      /* Transmit flow control enable */
-#define ETH_MACFCR_FCBBPA_Pos                         (0U)                     
-#define ETH_MACFCR_FCBBPA_Msk                         (0x1UL << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
-#define ETH_MACFCR_FCBBPA                             ETH_MACFCR_FCBBPA_Msk    /* Flow control busy/backpressure activate */
-
-/* Bit definition for Ethernet MAC VLAN Tag Register */
-#define ETH_MACVLANTR_VLANTC_Pos                      (16U)                    
-#define ETH_MACVLANTR_VLANTC_Msk                      (0x1UL << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
-#define ETH_MACVLANTR_VLANTC                          ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
-#define ETH_MACVLANTR_VLANTI_Pos                      (0U)                     
-#define ETH_MACVLANTR_VLANTI_Msk                      (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
-#define ETH_MACVLANTR_VLANTI                          ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
-
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
-#define ETH_MACRWUFFR_D_Pos                           (0U)                     
-#define ETH_MACRWUFFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
-#define ETH_MACRWUFFR_D                               ETH_MACRWUFFR_D_Msk      /* Wake-up frame filter register data */
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
-   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
-   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
-   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
-   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
-   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
-                              RSVD - Filter1 Command - RSVD - Filter0 Command
-   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
-   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
-   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
-
-/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
-#define ETH_MACPMTCSR_WFFRPR_Pos                      (31U)                    
-#define ETH_MACPMTCSR_WFFRPR_Msk                      (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
-#define ETH_MACPMTCSR_WFFRPR                          ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_MACPMTCSR_GU_Pos                          (9U)                     
-#define ETH_MACPMTCSR_GU_Msk                          (0x1UL << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
-#define ETH_MACPMTCSR_GU                              ETH_MACPMTCSR_GU_Msk     /* Global Unicast                              */
-#define ETH_MACPMTCSR_WFR_Pos                         (6U)                     
-#define ETH_MACPMTCSR_WFR_Msk                         (0x1UL << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
-#define ETH_MACPMTCSR_WFR                             ETH_MACPMTCSR_WFR_Msk    /* Wake-Up Frame Received                      */
-#define ETH_MACPMTCSR_MPR_Pos                         (5U)                     
-#define ETH_MACPMTCSR_MPR_Msk                         (0x1UL << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
-#define ETH_MACPMTCSR_MPR                             ETH_MACPMTCSR_MPR_Msk    /* Magic Packet Received                       */
-#define ETH_MACPMTCSR_WFE_Pos                         (2U)                     
-#define ETH_MACPMTCSR_WFE_Msk                         (0x1UL << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
-#define ETH_MACPMTCSR_WFE                             ETH_MACPMTCSR_WFE_Msk    /* Wake-Up Frame Enable                        */
-#define ETH_MACPMTCSR_MPE_Pos                         (1U)                     
-#define ETH_MACPMTCSR_MPE_Msk                         (0x1UL << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
-#define ETH_MACPMTCSR_MPE                             ETH_MACPMTCSR_MPE_Msk    /* Magic Packet Enable                         */
-#define ETH_MACPMTCSR_PD_Pos                          (0U)                     
-#define ETH_MACPMTCSR_PD_Msk                          (0x1UL << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
-#define ETH_MACPMTCSR_PD                              ETH_MACPMTCSR_PD_Msk     /* Power Down                                  */
-
-/* Bit definition for Ethernet MAC debug Register */
-#define ETH_MACDBGR_TFF_Pos                           (25U)                    
-#define ETH_MACDBGR_TFF_Msk                           (0x1UL << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
-#define ETH_MACDBGR_TFF                               ETH_MACDBGR_TFF_Msk      /* Tx FIFO full                                                            */
-#define ETH_MACDBGR_TFNE_Pos                          (24U)                    
-#define ETH_MACDBGR_TFNE_Msk                          (0x1UL << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
-#define ETH_MACDBGR_TFNE                              ETH_MACDBGR_TFNE_Msk     /* Tx FIFO not empty                                                       */
-#define ETH_MACDBGR_TFWA_Pos                          (22U)                    
-#define ETH_MACDBGR_TFWA_Msk                          (0x1UL << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
-#define ETH_MACDBGR_TFWA                              ETH_MACDBGR_TFWA_Msk     /* Tx FIFO write active                                                    */
-#define ETH_MACDBGR_TFRS_Pos                          (20U)                    
-#define ETH_MACDBGR_TFRS_Msk                          (0x3UL << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
-#define ETH_MACDBGR_TFRS                              ETH_MACDBGR_TFRS_Msk     /* Tx FIFO read status mask                                                */
-#define ETH_MACDBGR_TFRS_WRITING_Pos                  (20U)                    
-#define ETH_MACDBGR_TFRS_WRITING_Msk                  (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
-#define ETH_MACDBGR_TFRS_WRITING                      ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO                    */
-#define ETH_MACDBGR_TFRS_WAITING_Pos                  (21U)                    
-#define ETH_MACDBGR_TFRS_WAITING_Msk                  (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
-#define ETH_MACDBGR_TFRS_WAITING                      ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter                               */
-#define ETH_MACDBGR_TFRS_READ_Pos                     (20U)                    
-#define ETH_MACDBGR_TFRS_READ_Msk                     (0x1UL << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
-#define ETH_MACDBGR_TFRS_READ                         ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter)                   */
-#define ETH_MACDBGR_TFRS_IDLE                         0x00000000U              /* Idle state                                                              */
-#define ETH_MACDBGR_MTP_Pos                           (19U)                    
-#define ETH_MACDBGR_MTP_Msk                           (0x1UL << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
-#define ETH_MACDBGR_MTP                               ETH_MACDBGR_MTP_Msk      /* MAC transmitter in pause                                                */
-#define ETH_MACDBGR_MTFCS_Pos                         (17U)                    
-#define ETH_MACDBGR_MTFCS_Msk                         (0x3UL << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
-#define ETH_MACDBGR_MTFCS                             ETH_MACDBGR_MTFCS_Msk    /* MAC transmit frame controller status mask                               */
-#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos            (17U)                    
-#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk            (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
-#define ETH_MACDBGR_MTFCS_TRANSFERRING                ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission                               */
-#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos           (18U)                    
-#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk           (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
-#define ETH_MACDBGR_MTFCS_GENERATINGPCF               ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MACDBGR_MTFCS_WAITING_Pos                 (17U)                    
-#define ETH_MACDBGR_MTFCS_WAITING_Msk                 (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
-#define ETH_MACDBGR_MTFCS_WAITING                     ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over   */
-#define ETH_MACDBGR_MTFCS_IDLE                        0x00000000U              /* Idle                                                                    */
-#define ETH_MACDBGR_MMTEA_Pos                         (16U)                    
-#define ETH_MACDBGR_MMTEA_Msk                         (0x1UL << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
-#define ETH_MACDBGR_MMTEA                             ETH_MACDBGR_MMTEA_Msk    /* MAC MII transmit engine active                                          */
-#define ETH_MACDBGR_RFFL_Pos                          (8U)                     
-#define ETH_MACDBGR_RFFL_Msk                          (0x3UL << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
-#define ETH_MACDBGR_RFFL                              ETH_MACDBGR_RFFL_Msk     /* Rx FIFO fill level mask                                                 */
-#define ETH_MACDBGR_RFFL_FULL_Pos                     (8U)                     
-#define ETH_MACDBGR_RFFL_FULL_Msk                     (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
-#define ETH_MACDBGR_RFFL_FULL                         ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full                                                             */
-#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos                 (9U)                     
-#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk                 (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
-#define ETH_MACDBGR_RFFL_ABOVEFCT                     ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold                 */
-#define ETH_MACDBGR_RFFL_BELOWFCT_Pos                 (8U)                     
-#define ETH_MACDBGR_RFFL_BELOWFCT_Msk                 (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
-#define ETH_MACDBGR_RFFL_BELOWFCT                     ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold              */
-#define ETH_MACDBGR_RFFL_EMPTY                        0x00000000U              /* RxFIFO empty                                                            */
-#define ETH_MACDBGR_RFRCS_Pos                         (5U)                     
-#define ETH_MACDBGR_RFRCS_Msk                         (0x3UL << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
-#define ETH_MACDBGR_RFRCS                             ETH_MACDBGR_RFRCS_Msk    /* Rx FIFO read controller status mask                                     */
-#define ETH_MACDBGR_RFRCS_FLUSHING_Pos                (5U)                     
-#define ETH_MACDBGR_RFRCS_FLUSHING_Msk                (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
-#define ETH_MACDBGR_RFRCS_FLUSHING                    ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status                                      */
-#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos           (6U)                     
-#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk           (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
-#define ETH_MACDBGR_RFRCS_STATUSREADING               ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp)                                    */
-#define ETH_MACDBGR_RFRCS_DATAREADING_Pos             (5U)                     
-#define ETH_MACDBGR_RFRCS_DATAREADING_Msk             (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
-#define ETH_MACDBGR_RFRCS_DATAREADING                 ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data                                                      */
-#define ETH_MACDBGR_RFRCS_IDLE                        0x00000000U              /* IDLE state                                                              */
-#define ETH_MACDBGR_RFWRA_Pos                         (4U)                     
-#define ETH_MACDBGR_RFWRA_Msk                         (0x1UL << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
-#define ETH_MACDBGR_RFWRA                             ETH_MACDBGR_RFWRA_Msk    /* Rx FIFO write controller active                                         */
-#define ETH_MACDBGR_MSFRWCS_Pos                       (1U)                     
-#define ETH_MACDBGR_MSFRWCS_Msk                       (0x3UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
-#define ETH_MACDBGR_MSFRWCS                           ETH_MACDBGR_MSFRWCS_Msk  /* MAC small FIFO read / write controllers status  mask                    */
-#define ETH_MACDBGR_MSFRWCS_1                         (0x2UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
-#define ETH_MACDBGR_MSFRWCS_0                         (0x1UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
-#define ETH_MACDBGR_MMRPEA_Pos                        (0U)                     
-#define ETH_MACDBGR_MMRPEA_Msk                        (0x1UL << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
-#define ETH_MACDBGR_MMRPEA                            ETH_MACDBGR_MMRPEA_Msk   /* MAC MII receive protocol engine active                                  */
-
-/* Bit definition for Ethernet MAC Status Register */
-#define ETH_MACSR_TSTS_Pos                            (9U)                     
-#define ETH_MACSR_TSTS_Msk                            (0x1UL << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
-#define ETH_MACSR_TSTS                                ETH_MACSR_TSTS_Msk       /* Time stamp trigger status */
-#define ETH_MACSR_MMCTS_Pos                           (6U)                     
-#define ETH_MACSR_MMCTS_Msk                           (0x1UL << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
-#define ETH_MACSR_MMCTS                               ETH_MACSR_MMCTS_Msk      /* MMC transmit status       */
-#define ETH_MACSR_MMMCRS_Pos                          (5U)                     
-#define ETH_MACSR_MMMCRS_Msk                          (0x1UL << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
-#define ETH_MACSR_MMMCRS                              ETH_MACSR_MMMCRS_Msk     /* MMC receive status        */
-#define ETH_MACSR_MMCS_Pos                            (4U)                     
-#define ETH_MACSR_MMCS_Msk                            (0x1UL << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
-#define ETH_MACSR_MMCS                                ETH_MACSR_MMCS_Msk       /* MMC status                */
-#define ETH_MACSR_PMTS_Pos                            (3U)                     
-#define ETH_MACSR_PMTS_Msk                            (0x1UL << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
-#define ETH_MACSR_PMTS                                ETH_MACSR_PMTS_Msk       /* PMT status                */
-
-/* Bit definition for Ethernet MAC Interrupt Mask Register */
-#define ETH_MACIMR_TSTIM_Pos                          (9U)                     
-#define ETH_MACIMR_TSTIM_Msk                          (0x1UL << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
-#define ETH_MACIMR_TSTIM                              ETH_MACIMR_TSTIM_Msk     /* Time stamp trigger interrupt mask */
-#define ETH_MACIMR_PMTIM_Pos                          (3U)                     
-#define ETH_MACIMR_PMTIM_Msk                          (0x1UL << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
-#define ETH_MACIMR_PMTIM                              ETH_MACIMR_PMTIM_Msk     /* PMT interrupt mask                */
-
-/* Bit definition for Ethernet MAC Address0 High Register */
-#define ETH_MACA0HR_MACA0H_Pos                        (0U)                     
-#define ETH_MACA0HR_MACA0H_Msk                        (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
-#define ETH_MACA0HR_MACA0H                            ETH_MACA0HR_MACA0H_Msk   /* MAC address0 high */
-
-/* Bit definition for Ethernet MAC Address0 Low Register */
-#define ETH_MACA0LR_MACA0L_Pos                        (0U)                     
-#define ETH_MACA0LR_MACA0L_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
-#define ETH_MACA0LR_MACA0L                            ETH_MACA0LR_MACA0L_Msk   /* MAC address0 low */
-
-/* Bit definition for Ethernet MAC Address1 High Register */
-#define ETH_MACA1HR_AE_Pos                            (31U)                    
-#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
-#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk       /* Address enable */
-#define ETH_MACA1HR_SA_Pos                            (30U)                    
-#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
-#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk       /* Source address */
-#define ETH_MACA1HR_MBC_Pos                           (24U)                    
-#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
-#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk      /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
-#define ETH_MACA1HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACA1HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
-#define ETH_MACA1HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACA1HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACA1HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
-#define ETH_MACA1HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [7:0]   */
-#define ETH_MACA1HR_MACA1H_Pos                        (0U)                     
-#define ETH_MACA1HR_MACA1H_Msk                        (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
-#define ETH_MACA1HR_MACA1H                            ETH_MACA1HR_MACA1H_Msk   /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address1 Low Register */
-#define ETH_MACA1LR_MACA1L_Pos                        (0U)                     
-#define ETH_MACA1LR_MACA1L_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
-#define ETH_MACA1LR_MACA1L                            ETH_MACA1LR_MACA1L_Msk   /* MAC address1 low */
-
-/* Bit definition for Ethernet MAC Address2 High Register */
-#define ETH_MACA2HR_AE_Pos                            (31U)                    
-#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
-#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk       /* Address enable */
-#define ETH_MACA2HR_SA_Pos                            (30U)                    
-#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
-#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk       /* Source address */
-#define ETH_MACA2HR_MBC_Pos                           (24U)                    
-#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
-#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk      /* Mask byte control */
-#define ETH_MACA2HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACA2HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
-#define ETH_MACA2HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACA2HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACA2HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
-#define ETH_MACA2HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */
-#define ETH_MACA2HR_MACA2H_Pos                        (0U)                     
-#define ETH_MACA2HR_MACA2H_Msk                        (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
-#define ETH_MACA2HR_MACA2H                            ETH_MACA2HR_MACA2H_Msk   /* MAC address1 high */
-
-/* Bit definition for Ethernet MAC Address2 Low Register */
-#define ETH_MACA2LR_MACA2L_Pos                        (0U)                     
-#define ETH_MACA2LR_MACA2L_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
-#define ETH_MACA2LR_MACA2L                            ETH_MACA2LR_MACA2L_Msk   /* MAC address2 low */
-
-/* Bit definition for Ethernet MAC Address3 High Register */
-#define ETH_MACA3HR_AE_Pos                            (31U)                    
-#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
-#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk       /* Address enable */
-#define ETH_MACA3HR_SA_Pos                            (30U)                    
-#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
-#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk       /* Source address */
-#define ETH_MACA3HR_MBC_Pos                           (24U)                    
-#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
-#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk      /* Mask byte control */
-#define ETH_MACA3HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
-#define ETH_MACA3HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
-#define ETH_MACA3HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
-#define ETH_MACA3HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
-#define ETH_MACA3HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
-#define ETH_MACA3HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */
-#define ETH_MACA3HR_MACA3H_Pos                        (0U)                     
-#define ETH_MACA3HR_MACA3H_Msk                        (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
-#define ETH_MACA3HR_MACA3H                            ETH_MACA3HR_MACA3H_Msk   /* MAC address3 high */
-
-/* Bit definition for Ethernet MAC Address3 Low Register */
-#define ETH_MACA3LR_MACA3L_Pos                        (0U)                     
-#define ETH_MACA3LR_MACA3L_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
-#define ETH_MACA3LR_MACA3L                            ETH_MACA3LR_MACA3L_Msk   /* MAC address3 low */
-
-/******************************************************************************/
-/*                Ethernet MMC Registers bits definition                      */
-/******************************************************************************/
-
-/* Bit definition for Ethernet MMC Control Register */
-#define ETH_MMCCR_MCFHP_Pos                           (5U)                     
-#define ETH_MMCCR_MCFHP_Msk                           (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
-#define ETH_MMCCR_MCFHP                               ETH_MMCCR_MCFHP_Msk      /* MMC counter Full-Half preset */
-#define ETH_MMCCR_MCP_Pos                             (4U)                     
-#define ETH_MMCCR_MCP_Msk                             (0x1UL << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
-#define ETH_MMCCR_MCP                                 ETH_MMCCR_MCP_Msk        /* MMC counter preset           */
-#define ETH_MMCCR_MCF_Pos                             (3U)                     
-#define ETH_MMCCR_MCF_Msk                             (0x1UL << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
-#define ETH_MMCCR_MCF                                 ETH_MMCCR_MCF_Msk        /* MMC Counter Freeze           */
-#define ETH_MMCCR_ROR_Pos                             (2U)                     
-#define ETH_MMCCR_ROR_Msk                             (0x1UL << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
-#define ETH_MMCCR_ROR                                 ETH_MMCCR_ROR_Msk        /* Reset on Read                */
-#define ETH_MMCCR_CSR_Pos                             (1U)                     
-#define ETH_MMCCR_CSR_Msk                             (0x1UL << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
-#define ETH_MMCCR_CSR                                 ETH_MMCCR_CSR_Msk        /* Counter Stop Rollover        */
-#define ETH_MMCCR_CR_Pos                              (0U)                     
-#define ETH_MMCCR_CR_Msk                              (0x1UL << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
-#define ETH_MMCCR_CR                                  ETH_MMCCR_CR_Msk         /* Counters Reset               */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Register */
-#define ETH_MMCRIR_RGUFS_Pos                          (17U)                    
-#define ETH_MMCRIR_RGUFS_Msk                          (0x1UL << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
-#define ETH_MMCRIR_RGUFS                              ETH_MMCRIR_RGUFS_Msk     /* Set when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIR_RFAES_Pos                          (6U)                     
-#define ETH_MMCRIR_RFAES_Msk                          (0x1UL << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
-#define ETH_MMCRIR_RFAES                              ETH_MMCRIR_RFAES_Msk     /* Set when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIR_RFCES_Pos                          (5U)                     
-#define ETH_MMCRIR_RFCES_Msk                          (0x1UL << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
-#define ETH_MMCRIR_RFCES                              ETH_MMCRIR_RFCES_Msk     /* Set when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */
-#define ETH_MMCTIR_TGFS_Pos                           (21U)                    
-#define ETH_MMCTIR_TGFS_Msk                           (0x1UL << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
-#define ETH_MMCTIR_TGFS                               ETH_MMCTIR_TGFS_Msk      /* Set when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFMSCS_Pos                        (15U)                    
-#define ETH_MMCTIR_TGFMSCS_Msk                        (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
-#define ETH_MMCTIR_TGFMSCS                            ETH_MMCTIR_TGFMSCS_Msk   /* Set when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIR_TGFSCS_Pos                         (14U)                    
-#define ETH_MMCTIR_TGFSCS_Msk                         (0x1UL << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
-#define ETH_MMCTIR_TGFSCS                             ETH_MMCTIR_TGFSCS_Msk    /* Set when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
-#define ETH_MMCRIMR_RGUFM_Pos                         (17U)                    
-#define ETH_MMCRIMR_RGUFM_Msk                         (0x1UL << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
-#define ETH_MMCRIMR_RGUFM                             ETH_MMCRIMR_RGUFM_Msk    /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFAEM_Pos                         (6U)                     
-#define ETH_MMCRIMR_RFAEM_Msk                         (0x1UL << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
-#define ETH_MMCRIMR_RFAEM                             ETH_MMCRIMR_RFAEM_Msk    /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
-#define ETH_MMCRIMR_RFCEM_Pos                         (5U)                     
-#define ETH_MMCRIMR_RFCEM_Msk                         (0x1UL << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
-#define ETH_MMCRIMR_RFCEM                             ETH_MMCRIMR_RFCEM_Msk    /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
-#define ETH_MMCTIMR_TGFM_Pos                          (21U)                    
-#define ETH_MMCTIMR_TGFM_Msk                          (0x1UL << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
-#define ETH_MMCTIMR_TGFM                              ETH_MMCTIMR_TGFM_Msk     /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFMSCM_Pos                       (15U)                    
-#define ETH_MMCTIMR_TGFMSCM_Msk                       (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
-#define ETH_MMCTIMR_TGFMSCM                           ETH_MMCTIMR_TGFMSCM_Msk  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
-#define ETH_MMCTIMR_TGFSCM_Pos                        (14U)                    
-#define ETH_MMCTIMR_TGFSCM_Msk                        (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
-#define ETH_MMCTIMR_TGFSCM                            ETH_MMCTIMR_TGFSCM_Msk   /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
-#define ETH_MMCTGFSCCR_TGFSCC_Pos                     (0U)                     
-#define ETH_MMCTGFSCCR_TGFSCC_Msk                     (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
-#define ETH_MMCTGFSCCR_TGFSCC                         ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
-#define ETH_MMCTGFMSCCR_TGFMSCC_Pos                   (0U)                     
-#define ETH_MMCTGFMSCCR_TGFMSCC_Msk                   (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
-#define ETH_MMCTGFMSCCR_TGFMSCC                       ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
-
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
-#define ETH_MMCTGFCR_TGFC_Pos                         (0U)                     
-#define ETH_MMCTGFCR_TGFC_Msk                         (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
-#define ETH_MMCTGFCR_TGFC                             ETH_MMCTGFCR_TGFC_Msk    /* Number of good frames transmitted. */
-
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
-#define ETH_MMCRFCECR_RFCEC_Pos                       (0U)                     
-#define ETH_MMCRFCECR_RFCEC_Msk                       (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
-#define ETH_MMCRFCECR_RFCEC                           ETH_MMCRFCECR_RFCEC_Msk  /* Number of frames received with CRC error. */
-
-/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
-#define ETH_MMCRFAECR_RFAEC_Pos                       (0U)                     
-#define ETH_MMCRFAECR_RFAEC_Msk                       (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
-#define ETH_MMCRFAECR_RFAEC                           ETH_MMCRFAECR_RFAEC_Msk  /* Number of frames received with alignment (dribble) error */
-
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
-#define ETH_MMCRGUFCR_RGUFC_Pos                       (0U)                     
-#define ETH_MMCRGUFCR_RGUFC_Msk                       (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
-#define ETH_MMCRGUFCR_RGUFC                           ETH_MMCRGUFCR_RGUFC_Msk  /* Number of good unicast frames received. */
-
-/******************************************************************************/
-/*               Ethernet PTP Registers bits definition                       */
-/******************************************************************************/
-
-/* Bit definition for Ethernet PTP Time Stamp Control Register */
-#define ETH_PTPTSCR_TSPFFMAE_Pos                      (18U)
-#define ETH_PTPTSCR_TSPFFMAE_Msk                      (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
-#define ETH_PTPTSCR_TSPFFMAE                          ETH_PTPTSCR_TSPFFMAE_Msk  /* Time stamp PTP frame filtering MAC address enable */
-#define ETH_PTPTSCR_TSCNT_Pos                         (16U)                    
-#define ETH_PTPTSCR_TSCNT_Msk                         (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
-#define ETH_PTPTSCR_TSCNT                             ETH_PTPTSCR_TSCNT_Msk    /* Time stamp clock node type */
-#define ETH_PTPTSCR_TSSMRME_Pos                       (15U)                    
-#define ETH_PTPTSCR_TSSMRME_Msk                       (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
-#define ETH_PTPTSCR_TSSMRME                           ETH_PTPTSCR_TSSMRME_Msk  /* Time stamp snapshot for message relevant to master enable */
-#define ETH_PTPTSCR_TSSEME_Pos                        (14U)                    
-#define ETH_PTPTSCR_TSSEME_Msk                        (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
-#define ETH_PTPTSCR_TSSEME                            ETH_PTPTSCR_TSSEME_Msk   /* Time stamp snapshot for event message enable */
-#define ETH_PTPTSCR_TSSIPV4FE_Pos                     (13U)                    
-#define ETH_PTPTSCR_TSSIPV4FE_Msk                     (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
-#define ETH_PTPTSCR_TSSIPV4FE                         ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
-#define ETH_PTPTSCR_TSSIPV6FE_Pos                     (12U)                    
-#define ETH_PTPTSCR_TSSIPV6FE_Msk                     (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
-#define ETH_PTPTSCR_TSSIPV6FE                         ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
-#define ETH_PTPTSCR_TSSPTPOEFE_Pos                    (11U)                    
-#define ETH_PTPTSCR_TSSPTPOEFE_Msk                    (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
-#define ETH_PTPTSCR_TSSPTPOEFE                        ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
-#define ETH_PTPTSCR_TSPTPPSV2E_Pos                    (10U)                    
-#define ETH_PTPTSCR_TSPTPPSV2E_Msk                    (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
-#define ETH_PTPTSCR_TSPTPPSV2E                        ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
-#define ETH_PTPTSCR_TSSSR_Pos                         (9U)                     
-#define ETH_PTPTSCR_TSSSR_Msk                         (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
-#define ETH_PTPTSCR_TSSSR                             ETH_PTPTSCR_TSSSR_Msk    /* Time stamp Sub-seconds rollover */
-#define ETH_PTPTSCR_TSSARFE_Pos                       (8U)                     
-#define ETH_PTPTSCR_TSSARFE_Msk                       (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
-#define ETH_PTPTSCR_TSSARFE                           ETH_PTPTSCR_TSSARFE_Msk  /* Time stamp snapshot for all received frames enable */
-
-#define ETH_PTPTSCR_TSARU_Pos                         (5U)                     
-#define ETH_PTPTSCR_TSARU_Msk                         (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
-#define ETH_PTPTSCR_TSARU                             ETH_PTPTSCR_TSARU_Msk    /* Addend register update */
-#define ETH_PTPTSCR_TSITE_Pos                         (4U)                     
-#define ETH_PTPTSCR_TSITE_Msk                         (0x1UL << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
-#define ETH_PTPTSCR_TSITE                             ETH_PTPTSCR_TSITE_Msk    /* Time stamp interrupt trigger enable */
-#define ETH_PTPTSCR_TSSTU_Pos                         (3U)                     
-#define ETH_PTPTSCR_TSSTU_Msk                         (0x1UL << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
-#define ETH_PTPTSCR_TSSTU                             ETH_PTPTSCR_TSSTU_Msk    /* Time stamp update */
-#define ETH_PTPTSCR_TSSTI_Pos                         (2U)                     
-#define ETH_PTPTSCR_TSSTI_Msk                         (0x1UL << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
-#define ETH_PTPTSCR_TSSTI                             ETH_PTPTSCR_TSSTI_Msk    /* Time stamp initialize */
-#define ETH_PTPTSCR_TSFCU_Pos                         (1U)                     
-#define ETH_PTPTSCR_TSFCU_Msk                         (0x1UL << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
-#define ETH_PTPTSCR_TSFCU                             ETH_PTPTSCR_TSFCU_Msk    /* Time stamp fine or coarse update */
-#define ETH_PTPTSCR_TSE_Pos                           (0U)                     
-#define ETH_PTPTSCR_TSE_Msk                           (0x1UL << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
-#define ETH_PTPTSCR_TSE                               ETH_PTPTSCR_TSE_Msk      /* Time stamp enable */
-
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */
-#define ETH_PTPSSIR_STSSI_Pos                         (0U)                     
-#define ETH_PTPSSIR_STSSI_Msk                         (0xFFUL << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
-#define ETH_PTPSSIR_STSSI                             ETH_PTPSSIR_STSSI_Msk    /* System time Sub-second increment value */
-
-/* Bit definition for Ethernet PTP Time Stamp High Register */
-#define ETH_PTPTSHR_STS_Pos                           (0U)                     
-#define ETH_PTPTSHR_STS_Msk                           (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
-#define ETH_PTPTSHR_STS                               ETH_PTPTSHR_STS_Msk      /* System Time second */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Register */
-#define ETH_PTPTSLR_STPNS_Pos                         (31U)                    
-#define ETH_PTPTSLR_STPNS_Msk                         (0x1UL << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
-#define ETH_PTPTSLR_STPNS                             ETH_PTPTSLR_STPNS_Msk    /* System Time Positive or negative time */
-#define ETH_PTPTSLR_STSS_Pos                          (0U)                     
-#define ETH_PTPTSLR_STSS_Msk                          (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
-#define ETH_PTPTSLR_STSS                              ETH_PTPTSLR_STSS_Msk     /* System Time sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */
-#define ETH_PTPTSHUR_TSUS_Pos                         (0U)                     
-#define ETH_PTPTSHUR_TSUS_Msk                         (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
-#define ETH_PTPTSHUR_TSUS                             ETH_PTPTSHUR_TSUS_Msk    /* Time stamp update seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
-#define ETH_PTPTSLUR_TSUPNS_Pos                       (31U)                    
-#define ETH_PTPTSLUR_TSUPNS_Msk                       (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
-#define ETH_PTPTSLUR_TSUPNS                           ETH_PTPTSLUR_TSUPNS_Msk  /* Time stamp update Positive or negative time */
-#define ETH_PTPTSLUR_TSUSS_Pos                        (0U)                     
-#define ETH_PTPTSLUR_TSUSS_Msk                        (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
-#define ETH_PTPTSLUR_TSUSS                            ETH_PTPTSLUR_TSUSS_Msk   /* Time stamp update sub-seconds */
-
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */
-#define ETH_PTPTSAR_TSA_Pos                           (0U)                     
-#define ETH_PTPTSAR_TSA_Msk                           (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
-#define ETH_PTPTSAR_TSA                               ETH_PTPTSAR_TSA_Msk      /* Time stamp addend */
-
-/* Bit definition for Ethernet PTP Target Time High Register */
-#define ETH_PTPTTHR_TTSH_Pos                          (0U)                     
-#define ETH_PTPTTHR_TTSH_Msk                          (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
-#define ETH_PTPTTHR_TTSH                              ETH_PTPTTHR_TTSH_Msk     /* Target time stamp high */
-
-/* Bit definition for Ethernet PTP Target Time Low Register */
-#define ETH_PTPTTLR_TTSL_Pos                          (0U)                     
-#define ETH_PTPTTLR_TTSL_Msk                          (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
-#define ETH_PTPTTLR_TTSL                              ETH_PTPTTLR_TTSL_Msk     /* Target time stamp low */
-
-/* Bit definition for Ethernet PTP Time Stamp Status Register */
-#define ETH_PTPTSSR_TSTTR_Pos                         (5U)                     
-#define ETH_PTPTSSR_TSTTR_Msk                         (0x1UL << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
-#define ETH_PTPTSSR_TSTTR                             ETH_PTPTSSR_TSTTR_Msk    /* Time stamp target time reached */
-#define ETH_PTPTSSR_TSSO_Pos                          (4U)                     
-#define ETH_PTPTSSR_TSSO_Msk                          (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
-#define ETH_PTPTSSR_TSSO                              ETH_PTPTSSR_TSSO_Msk     /* Time stamp seconds overflow */
-
-/******************************************************************************/
-/*                 Ethernet DMA Registers bits definition                     */
-/******************************************************************************/
-
-/* Bit definition for Ethernet DMA Bus Mode Register */
-#define ETH_DMABMR_MB_Pos                             (26U)
-#define ETH_DMABMR_MB_Msk                             (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
-#define ETH_DMABMR_MB                                 ETH_DMABMR_MB_Msk       /* Mixed Burst */
-#define ETH_DMABMR_AAB_Pos                            (25U)                    
-#define ETH_DMABMR_AAB_Msk                            (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
-#define ETH_DMABMR_AAB                                ETH_DMABMR_AAB_Msk       /* Address-Aligned beats */
-#define ETH_DMABMR_FPM_Pos                            (24U)                    
-#define ETH_DMABMR_FPM_Msk                            (0x1UL << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
-#define ETH_DMABMR_FPM                                ETH_DMABMR_FPM_Msk       /* 4xPBL mode */
-#define ETH_DMABMR_USP_Pos                            (23U)                    
-#define ETH_DMABMR_USP_Msk                            (0x1UL << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
-#define ETH_DMABMR_USP                                ETH_DMABMR_USP_Msk       /* Use separate PBL */
-#define ETH_DMABMR_RDP_Pos                            (17U)                    
-#define ETH_DMABMR_RDP_Msk                            (0x3FUL << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
-#define ETH_DMABMR_RDP                                ETH_DMABMR_RDP_Msk       /* RxDMA PBL */
-#define ETH_DMABMR_RDP_1Beat                          0x00020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
-#define ETH_DMABMR_RDP_2Beat                          0x00040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
-#define ETH_DMABMR_RDP_4Beat                          0x00080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_DMABMR_RDP_8Beat                          0x00100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_DMABMR_RDP_16Beat                         0x00200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_DMABMR_RDP_32Beat                         0x00400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
-#define ETH_DMABMR_RDP_4xPBL_4Beat                    0x01020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_DMABMR_RDP_4xPBL_8Beat                    0x01040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_DMABMR_RDP_4xPBL_16Beat                   0x01080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_DMABMR_RDP_4xPBL_32Beat                   0x01100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_DMABMR_RDP_4xPBL_64Beat                   0x01200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
-#define ETH_DMABMR_RDP_4xPBL_128Beat                  0x01400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
-#define ETH_DMABMR_FB_Pos                             (16U)                    
-#define ETH_DMABMR_FB_Msk                             (0x1UL << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
-#define ETH_DMABMR_FB                                 ETH_DMABMR_FB_Msk        /* Fixed Burst */
-#define ETH_DMABMR_RTPR_Pos                           (14U)                    
-#define ETH_DMABMR_RTPR_Msk                           (0x3UL << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
-#define ETH_DMABMR_RTPR                               ETH_DMABMR_RTPR_Msk      /* Rx Tx priority ratio */
-#define ETH_DMABMR_RTPR_1_1                           0x00000000U              /* Rx Tx priority ratio */
-#define ETH_DMABMR_RTPR_2_1                           0x00004000U              /* Rx Tx priority ratio */
-#define ETH_DMABMR_RTPR_3_1                           0x00008000U              /* Rx Tx priority ratio */
-#define ETH_DMABMR_RTPR_4_1                           0x0000C000U              /* Rx Tx priority ratio */  
-#define ETH_DMABMR_PBL_Pos                            (8U)                     
-#define ETH_DMABMR_PBL_Msk                            (0x3FUL << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
-#define ETH_DMABMR_PBL                                ETH_DMABMR_PBL_Msk       /* Programmable burst length */
-#define ETH_DMABMR_PBL_1Beat                          0x00000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-#define ETH_DMABMR_PBL_2Beat                          0x00000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-#define ETH_DMABMR_PBL_4Beat                          0x00000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_DMABMR_PBL_8Beat                          0x00000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_DMABMR_PBL_16Beat                         0x00001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_DMABMR_PBL_32Beat                         0x00002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
-#define ETH_DMABMR_PBL_4xPBL_4Beat                    0x01000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_DMABMR_PBL_4xPBL_8Beat                    0x01000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_DMABMR_PBL_4xPBL_16Beat                   0x01000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_DMABMR_PBL_4xPBL_32Beat                   0x01000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-#define ETH_DMABMR_PBL_4xPBL_64Beat                   0x01001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-#define ETH_DMABMR_PBL_4xPBL_128Beat                  0x01002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
-#define ETH_DMABMR_EDE_Pos                            (7U)                     
-#define ETH_DMABMR_EDE_Msk                            (0x1UL << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
-#define ETH_DMABMR_EDE                                ETH_DMABMR_EDE_Msk       /* Enhanced Descriptor Enable */
-#define ETH_DMABMR_DSL_Pos                            (2U)                     
-#define ETH_DMABMR_DSL_Msk                            (0x1FUL << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
-#define ETH_DMABMR_DSL                                ETH_DMABMR_DSL_Msk       /* Descriptor Skip Length */
-#define ETH_DMABMR_DA_Pos                             (1U)                     
-#define ETH_DMABMR_DA_Msk                             (0x1UL << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
-#define ETH_DMABMR_DA                                 ETH_DMABMR_DA_Msk        /* DMA arbitration scheme */
-#define ETH_DMABMR_SR_Pos                             (0U)                     
-#define ETH_DMABMR_SR_Msk                             (0x1UL << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
-#define ETH_DMABMR_SR                                 ETH_DMABMR_SR_Msk        /* Software reset */
-
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
-#define ETH_DMATPDR_TPD_Pos                           (0U)                     
-#define ETH_DMATPDR_TPD_Msk                           (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
-#define ETH_DMATPDR_TPD                               ETH_DMATPDR_TPD_Msk      /* Transmit poll demand */
-
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */
-#define ETH_DMARPDR_RPD_Pos                           (0U)                     
-#define ETH_DMARPDR_RPD_Msk                           (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
-#define ETH_DMARPDR_RPD                               ETH_DMARPDR_RPD_Msk      /* Receive poll demand  */
-
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
-#define ETH_DMARDLAR_SRL_Pos                          (0U)                     
-#define ETH_DMARDLAR_SRL_Msk                          (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
-#define ETH_DMARDLAR_SRL                              ETH_DMARDLAR_SRL_Msk     /* Start of receive list */
-
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
-#define ETH_DMATDLAR_STL_Pos                          (0U)                     
-#define ETH_DMATDLAR_STL_Msk                          (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
-#define ETH_DMATDLAR_STL                              ETH_DMATDLAR_STL_Msk     /* Start of transmit list */
-
-/* Bit definition for Ethernet DMA Status Register */
-#define ETH_DMASR_TSTS_Pos                            (29U)                    
-#define ETH_DMASR_TSTS_Msk                            (0x1UL << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
-#define ETH_DMASR_TSTS                                ETH_DMASR_TSTS_Msk       /* Time-stamp trigger status */
-#define ETH_DMASR_PMTS_Pos                            (28U)                    
-#define ETH_DMASR_PMTS_Msk                            (0x1UL << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
-#define ETH_DMASR_PMTS                                ETH_DMASR_PMTS_Msk       /* PMT status */
-#define ETH_DMASR_MMCS_Pos                            (27U)                    
-#define ETH_DMASR_MMCS_Msk                            (0x1UL << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
-#define ETH_DMASR_MMCS                                ETH_DMASR_MMCS_Msk       /* MMC status */
-#define ETH_DMASR_EBS_Pos                             (23U)                    
-#define ETH_DMASR_EBS_Msk                             (0x7UL << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
-#define ETH_DMASR_EBS                                 ETH_DMASR_EBS_Msk        /* Error bits status */
-  /* combination with EBS[2:0] for GetFlagStatus function */
-#define ETH_DMASR_EBS_DescAccess_Pos                  (25U)                    
-#define ETH_DMASR_EBS_DescAccess_Msk                  (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
-#define ETH_DMASR_EBS_DescAccess                      ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
-#define ETH_DMASR_EBS_ReadTransf_Pos                  (24U)                    
-#define ETH_DMASR_EBS_ReadTransf_Msk                  (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
-#define ETH_DMASR_EBS_ReadTransf                      ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
-#define ETH_DMASR_EBS_DataTransfTx_Pos                (23U)                    
-#define ETH_DMASR_EBS_DataTransfTx_Msk                (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
-#define ETH_DMASR_EBS_DataTransfTx                    ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMASR_TPS_Pos                             (20U)                    
-#define ETH_DMASR_TPS_Msk                             (0x7UL << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
-#define ETH_DMASR_TPS                                 ETH_DMASR_TPS_Msk        /* Transmit process state */
-#define ETH_DMASR_TPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Tx Command issued  */
-#define ETH_DMASR_TPS_Fetching_Pos                    (20U)                    
-#define ETH_DMASR_TPS_Fetching_Msk                    (0x1UL << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
-#define ETH_DMASR_TPS_Fetching                        ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
-#define ETH_DMASR_TPS_Waiting_Pos                     (21U)                    
-#define ETH_DMASR_TPS_Waiting_Msk                     (0x1UL << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
-#define ETH_DMASR_TPS_Waiting                         ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
-#define ETH_DMASR_TPS_Reading_Pos                     (20U)                    
-#define ETH_DMASR_TPS_Reading_Msk                     (0x3UL << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
-#define ETH_DMASR_TPS_Reading                         ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
-#define ETH_DMASR_TPS_Suspended_Pos                   (21U)                    
-#define ETH_DMASR_TPS_Suspended_Msk                   (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
-#define ETH_DMASR_TPS_Suspended                       ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
-#define ETH_DMASR_TPS_Closing_Pos                     (20U)                    
-#define ETH_DMASR_TPS_Closing_Msk                     (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
-#define ETH_DMASR_TPS_Closing                         ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
-#define ETH_DMASR_RPS_Pos                             (17U)                    
-#define ETH_DMASR_RPS_Msk                             (0x7UL << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
-#define ETH_DMASR_RPS                                 ETH_DMASR_RPS_Msk        /* Receive process state */
-#define ETH_DMASR_RPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Rx Command issued */
-#define ETH_DMASR_RPS_Fetching_Pos                    (17U)                    
-#define ETH_DMASR_RPS_Fetching_Msk                    (0x1UL << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
-#define ETH_DMASR_RPS_Fetching                        ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
-#define ETH_DMASR_RPS_Waiting_Pos                     (17U)                    
-#define ETH_DMASR_RPS_Waiting_Msk                     (0x3UL << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
-#define ETH_DMASR_RPS_Waiting                         ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
-#define ETH_DMASR_RPS_Suspended_Pos                   (19U)                    
-#define ETH_DMASR_RPS_Suspended_Msk                   (0x1UL << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
-#define ETH_DMASR_RPS_Suspended                       ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
-#define ETH_DMASR_RPS_Closing_Pos                     (17U)                    
-#define ETH_DMASR_RPS_Closing_Msk                     (0x5UL << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
-#define ETH_DMASR_RPS_Closing                         ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
-#define ETH_DMASR_RPS_Queuing_Pos                     (17U)                    
-#define ETH_DMASR_RPS_Queuing_Msk                     (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
-#define ETH_DMASR_RPS_Queuing                         ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
-#define ETH_DMASR_NIS_Pos                             (16U)                    
-#define ETH_DMASR_NIS_Msk                             (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
-#define ETH_DMASR_NIS                                 ETH_DMASR_NIS_Msk        /* Normal interrupt summary */
-#define ETH_DMASR_AIS_Pos                             (15U)                    
-#define ETH_DMASR_AIS_Msk                             (0x1UL << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
-#define ETH_DMASR_AIS                                 ETH_DMASR_AIS_Msk        /* Abnormal interrupt summary */
-#define ETH_DMASR_ERS_Pos                             (14U)                    
-#define ETH_DMASR_ERS_Msk                             (0x1UL << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
-#define ETH_DMASR_ERS                                 ETH_DMASR_ERS_Msk        /* Early receive status */
-#define ETH_DMASR_FBES_Pos                            (13U)                    
-#define ETH_DMASR_FBES_Msk                            (0x1UL << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
-#define ETH_DMASR_FBES                                ETH_DMASR_FBES_Msk       /* Fatal bus error status */
-#define ETH_DMASR_ETS_Pos                             (10U)                    
-#define ETH_DMASR_ETS_Msk                             (0x1UL << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
-#define ETH_DMASR_ETS                                 ETH_DMASR_ETS_Msk        /* Early transmit status */
-#define ETH_DMASR_RWTS_Pos                            (9U)                     
-#define ETH_DMASR_RWTS_Msk                            (0x1UL << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
-#define ETH_DMASR_RWTS                                ETH_DMASR_RWTS_Msk       /* Receive watchdog timeout status */
-#define ETH_DMASR_RPSS_Pos                            (8U)                     
-#define ETH_DMASR_RPSS_Msk                            (0x1UL << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
-#define ETH_DMASR_RPSS                                ETH_DMASR_RPSS_Msk       /* Receive process stopped status */
-#define ETH_DMASR_RBUS_Pos                            (7U)                     
-#define ETH_DMASR_RBUS_Msk                            (0x1UL << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
-#define ETH_DMASR_RBUS                                ETH_DMASR_RBUS_Msk       /* Receive buffer unavailable status */
-#define ETH_DMASR_RS_Pos                              (6U)                     
-#define ETH_DMASR_RS_Msk                              (0x1UL << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
-#define ETH_DMASR_RS                                  ETH_DMASR_RS_Msk         /* Receive status */
-#define ETH_DMASR_TUS_Pos                             (5U)                     
-#define ETH_DMASR_TUS_Msk                             (0x1UL << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
-#define ETH_DMASR_TUS                                 ETH_DMASR_TUS_Msk        /* Transmit underflow status */
-#define ETH_DMASR_ROS_Pos                             (4U)                     
-#define ETH_DMASR_ROS_Msk                             (0x1UL << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
-#define ETH_DMASR_ROS                                 ETH_DMASR_ROS_Msk        /* Receive overflow status */
-#define ETH_DMASR_TJTS_Pos                            (3U)                     
-#define ETH_DMASR_TJTS_Msk                            (0x1UL << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
-#define ETH_DMASR_TJTS                                ETH_DMASR_TJTS_Msk       /* Transmit jabber timeout status */
-#define ETH_DMASR_TBUS_Pos                            (2U)                     
-#define ETH_DMASR_TBUS_Msk                            (0x1UL << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
-#define ETH_DMASR_TBUS                                ETH_DMASR_TBUS_Msk       /* Transmit buffer unavailable status */
-#define ETH_DMASR_TPSS_Pos                            (1U)                     
-#define ETH_DMASR_TPSS_Msk                            (0x1UL << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
-#define ETH_DMASR_TPSS                                ETH_DMASR_TPSS_Msk       /* Transmit process stopped status */
-#define ETH_DMASR_TS_Pos                              (0U)                     
-#define ETH_DMASR_TS_Msk                              (0x1UL << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
-#define ETH_DMASR_TS                                  ETH_DMASR_TS_Msk         /* Transmit status */
-
-/* Bit definition for Ethernet DMA Operation Mode Register */
-#define ETH_DMAOMR_DTCEFD_Pos                         (26U)                    
-#define ETH_DMAOMR_DTCEFD_Msk                         (0x1UL << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
-#define ETH_DMAOMR_DTCEFD                             ETH_DMAOMR_DTCEFD_Msk    /* Disable Dropping of TCP/IP checksum error frames */
-#define ETH_DMAOMR_RSF_Pos                            (25U)                    
-#define ETH_DMAOMR_RSF_Msk                            (0x1UL << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
-#define ETH_DMAOMR_RSF                                ETH_DMAOMR_RSF_Msk       /* Receive store and forward */
-#define ETH_DMAOMR_DFRF_Pos                           (24U)                    
-#define ETH_DMAOMR_DFRF_Msk                           (0x1UL << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
-#define ETH_DMAOMR_DFRF                               ETH_DMAOMR_DFRF_Msk      /* Disable flushing of received frames */
-#define ETH_DMAOMR_TSF_Pos                            (21U)                    
-#define ETH_DMAOMR_TSF_Msk                            (0x1UL << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
-#define ETH_DMAOMR_TSF                                ETH_DMAOMR_TSF_Msk       /* Transmit store and forward */
-#define ETH_DMAOMR_FTF_Pos                            (20U)                    
-#define ETH_DMAOMR_FTF_Msk                            (0x1UL << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
-#define ETH_DMAOMR_FTF                                ETH_DMAOMR_FTF_Msk       /* Flush transmit FIFO */
-#define ETH_DMAOMR_TTC_Pos                            (14U)                    
-#define ETH_DMAOMR_TTC_Msk                            (0x7UL << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
-#define ETH_DMAOMR_TTC                                ETH_DMAOMR_TTC_Msk       /* Transmit threshold control */
-#define ETH_DMAOMR_TTC_64Bytes                        0x00000000U              /* threshold level of the MTL Transmit FIFO is 64 Bytes */
-#define ETH_DMAOMR_TTC_128Bytes                       0x00004000U              /* threshold level of the MTL Transmit FIFO is 128 Bytes */
-#define ETH_DMAOMR_TTC_192Bytes                       0x00008000U              /* threshold level of the MTL Transmit FIFO is 192 Bytes */
-#define ETH_DMAOMR_TTC_256Bytes                       0x0000C000U              /* threshold level of the MTL Transmit FIFO is 256 Bytes */
-#define ETH_DMAOMR_TTC_40Bytes                        0x00010000U              /* threshold level of the MTL Transmit FIFO is 40 Bytes */
-#define ETH_DMAOMR_TTC_32Bytes                        0x00014000U              /* threshold level of the MTL Transmit FIFO is 32 Bytes */
-#define ETH_DMAOMR_TTC_24Bytes                        0x00018000U              /* threshold level of the MTL Transmit FIFO is 24 Bytes */
-#define ETH_DMAOMR_TTC_16Bytes                        0x0001C000U              /* threshold level of the MTL Transmit FIFO is 16 Bytes */
-#define ETH_DMAOMR_ST_Pos                             (13U)                    
-#define ETH_DMAOMR_ST_Msk                             (0x1UL << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
-#define ETH_DMAOMR_ST                                 ETH_DMAOMR_ST_Msk        /* Start/stop transmission command */
-#define ETH_DMAOMR_FEF_Pos                            (7U)                     
-#define ETH_DMAOMR_FEF_Msk                            (0x1UL << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
-#define ETH_DMAOMR_FEF                                ETH_DMAOMR_FEF_Msk       /* Forward error frames */
-#define ETH_DMAOMR_FUGF_Pos                           (6U)                     
-#define ETH_DMAOMR_FUGF_Msk                           (0x1UL << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
-#define ETH_DMAOMR_FUGF                               ETH_DMAOMR_FUGF_Msk      /* Forward undersized good frames */
-#define ETH_DMAOMR_RTC_Pos                            (3U)                     
-#define ETH_DMAOMR_RTC_Msk                            (0x3UL << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
-#define ETH_DMAOMR_RTC                                ETH_DMAOMR_RTC_Msk       /* receive threshold control */
-#define ETH_DMAOMR_RTC_64Bytes                        0x00000000U              /* threshold level of the MTL Receive FIFO is 64 Bytes */
-#define ETH_DMAOMR_RTC_32Bytes                        0x00000008U              /* threshold level of the MTL Receive FIFO is 32 Bytes */
-#define ETH_DMAOMR_RTC_96Bytes                        0x00000010U              /* threshold level of the MTL Receive FIFO is 96 Bytes */
-#define ETH_DMAOMR_RTC_128Bytes                       0x00000018U              /* threshold level of the MTL Receive FIFO is 128 Bytes */
-#define ETH_DMAOMR_OSF_Pos                            (2U)                     
-#define ETH_DMAOMR_OSF_Msk                            (0x1UL << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
-#define ETH_DMAOMR_OSF                                ETH_DMAOMR_OSF_Msk       /* operate on second frame */
-#define ETH_DMAOMR_SR_Pos                             (1U)                     
-#define ETH_DMAOMR_SR_Msk                             (0x1UL << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
-#define ETH_DMAOMR_SR                                 ETH_DMAOMR_SR_Msk        /* Start/stop receive */
-
-/* Bit definition for Ethernet DMA Interrupt Enable Register */
-#define ETH_DMAIER_NISE_Pos                           (16U)                    
-#define ETH_DMAIER_NISE_Msk                           (0x1UL << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
-#define ETH_DMAIER_NISE                               ETH_DMAIER_NISE_Msk      /* Normal interrupt summary enable */
-#define ETH_DMAIER_AISE_Pos                           (15U)                    
-#define ETH_DMAIER_AISE_Msk                           (0x1UL << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
-#define ETH_DMAIER_AISE                               ETH_DMAIER_AISE_Msk      /* Abnormal interrupt summary enable */
-#define ETH_DMAIER_ERIE_Pos                           (14U)                    
-#define ETH_DMAIER_ERIE_Msk                           (0x1UL << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
-#define ETH_DMAIER_ERIE                               ETH_DMAIER_ERIE_Msk      /* Early receive interrupt enable */
-#define ETH_DMAIER_FBEIE_Pos                          (13U)                    
-#define ETH_DMAIER_FBEIE_Msk                          (0x1UL << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
-#define ETH_DMAIER_FBEIE                              ETH_DMAIER_FBEIE_Msk     /* Fatal bus error interrupt enable */
-#define ETH_DMAIER_ETIE_Pos                           (10U)                    
-#define ETH_DMAIER_ETIE_Msk                           (0x1UL << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
-#define ETH_DMAIER_ETIE                               ETH_DMAIER_ETIE_Msk      /* Early transmit interrupt enable */
-#define ETH_DMAIER_RWTIE_Pos                          (9U)                     
-#define ETH_DMAIER_RWTIE_Msk                          (0x1UL << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
-#define ETH_DMAIER_RWTIE                              ETH_DMAIER_RWTIE_Msk     /* Receive watchdog timeout interrupt enable */
-#define ETH_DMAIER_RPSIE_Pos                          (8U)                     
-#define ETH_DMAIER_RPSIE_Msk                          (0x1UL << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
-#define ETH_DMAIER_RPSIE                              ETH_DMAIER_RPSIE_Msk     /* Receive process stopped interrupt enable */
-#define ETH_DMAIER_RBUIE_Pos                          (7U)                     
-#define ETH_DMAIER_RBUIE_Msk                          (0x1UL << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
-#define ETH_DMAIER_RBUIE                              ETH_DMAIER_RBUIE_Msk     /* Receive buffer unavailable interrupt enable */
-#define ETH_DMAIER_RIE_Pos                            (6U)                     
-#define ETH_DMAIER_RIE_Msk                            (0x1UL << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
-#define ETH_DMAIER_RIE                                ETH_DMAIER_RIE_Msk       /* Receive interrupt enable */
-#define ETH_DMAIER_TUIE_Pos                           (5U)                     
-#define ETH_DMAIER_TUIE_Msk                           (0x1UL << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
-#define ETH_DMAIER_TUIE                               ETH_DMAIER_TUIE_Msk      /* Transmit Underflow interrupt enable */
-#define ETH_DMAIER_ROIE_Pos                           (4U)                     
-#define ETH_DMAIER_ROIE_Msk                           (0x1UL << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
-#define ETH_DMAIER_ROIE                               ETH_DMAIER_ROIE_Msk      /* Receive Overflow interrupt enable */
-#define ETH_DMAIER_TJTIE_Pos                          (3U)                     
-#define ETH_DMAIER_TJTIE_Msk                          (0x1UL << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
-#define ETH_DMAIER_TJTIE                              ETH_DMAIER_TJTIE_Msk     /* Transmit jabber timeout interrupt enable */
-#define ETH_DMAIER_TBUIE_Pos                          (2U)                     
-#define ETH_DMAIER_TBUIE_Msk                          (0x1UL << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
-#define ETH_DMAIER_TBUIE                              ETH_DMAIER_TBUIE_Msk     /* Transmit buffer unavailable interrupt enable */
-#define ETH_DMAIER_TPSIE_Pos                          (1U)                     
-#define ETH_DMAIER_TPSIE_Msk                          (0x1UL << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
-#define ETH_DMAIER_TPSIE                              ETH_DMAIER_TPSIE_Msk     /* Transmit process stopped interrupt enable */
-#define ETH_DMAIER_TIE_Pos                            (0U)                     
-#define ETH_DMAIER_TIE_Msk                            (0x1UL << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
-#define ETH_DMAIER_TIE                                ETH_DMAIER_TIE_Msk       /* Transmit interrupt enable */
-
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
-#define ETH_DMAMFBOCR_OFOC_Pos                        (28U)                    
-#define ETH_DMAMFBOCR_OFOC_Msk                        (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
-#define ETH_DMAMFBOCR_OFOC                            ETH_DMAMFBOCR_OFOC_Msk   /* Overflow bit for FIFO overflow counter */
-#define ETH_DMAMFBOCR_MFA_Pos                         (17U)                    
-#define ETH_DMAMFBOCR_MFA_Msk                         (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
-#define ETH_DMAMFBOCR_MFA                             ETH_DMAMFBOCR_MFA_Msk    /* Number of frames missed by the application */
-#define ETH_DMAMFBOCR_OMFC_Pos                        (16U)                    
-#define ETH_DMAMFBOCR_OMFC_Msk                        (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
-#define ETH_DMAMFBOCR_OMFC                            ETH_DMAMFBOCR_OMFC_Msk   /* Overflow bit for missed frame counter */
-#define ETH_DMAMFBOCR_MFC_Pos                         (0U)                     
-#define ETH_DMAMFBOCR_MFC_Msk                         (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
-#define ETH_DMAMFBOCR_MFC                             ETH_DMAMFBOCR_MFC_Msk    /* Number of frames missed by the controller */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
-#define ETH_DMACHTDR_HTDAP_Pos                        (0U)                     
-#define ETH_DMACHTDR_HTDAP_Msk                        (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
-#define ETH_DMACHTDR_HTDAP                            ETH_DMACHTDR_HTDAP_Msk   /* Host transmit descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
-#define ETH_DMACHRDR_HRDAP_Pos                        (0U)                     
-#define ETH_DMACHRDR_HRDAP_Msk                        (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
-#define ETH_DMACHRDR_HRDAP                            ETH_DMACHRDR_HRDAP_Msk   /* Host receive descriptor address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
-#define ETH_DMACHTBAR_HTBAP_Pos                       (0U)                     
-#define ETH_DMACHTBAR_HTBAP_Msk                       (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
-#define ETH_DMACHTBAR_HTBAP                           ETH_DMACHTBAR_HTBAP_Msk  /* Host transmit buffer address pointer */
-
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
-#define ETH_DMACHRBAR_HRBAP_Pos                       (0U)                     
-#define ETH_DMACHRBAR_HRBAP_Msk                       (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
-#define ETH_DMACHRBAR_HRBAP                           ETH_DMACHRBAR_HRBAP_Msk  /* Host receive buffer address pointer */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                       USB_OTG                              */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
-#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)                          
-#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
-#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
-#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)                          
-#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
-#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
-#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)                          
-#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
-#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)                          
-#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
-#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
-#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)                         
-#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
-#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
-#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)                         
-#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
-#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
-#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)                         
-#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
-#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
-#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)                         
-#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
-#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
-#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)                         
-#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
-#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
-#define USB_OTG_GOTGCTL_BSVLD_Pos                (19U)                         
-#define USB_OTG_GOTGCTL_BSVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
-#define USB_OTG_GOTGCTL_BSVLD                    USB_OTG_GOTGCTL_BSVLD_Msk     /*!< B-session valid */
-
-/********************  Bit definition forUSB_OTG_HCFG register  ********************/
-
-#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)                          
-#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
-#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
-#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCFG_FSLSS_Pos                   (2U)                          
-#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
-
-/********************  Bit definition for USB_OTG_DCFG register  ********************/
-
-#define USB_OTG_DCFG_DSPD_Pos                    (0U)                          
-#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
-#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
-#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
-#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)                          
-#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
-#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
-
-#define USB_OTG_DCFG_DAD_Pos                     (4U)                          
-#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
-#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
-#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
-#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
-#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
-#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
-#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
-#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
-#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
-
-#define USB_OTG_DCFG_PFIVL_Pos                   (11U)                         
-#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
-#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
-#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
-#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
-
-#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)                         
-#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
-#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk        /*!< Transceiver delay */
-
-#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)                         
-#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
-#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk        /*!< Erratic error interrupt mask */
-
-#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)                         
-#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
-#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
-#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
-#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
-
-/********************  Bit definition for USB_OTG_PCGCR register  ********************/
-#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)                          
-#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
-#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
-#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)                          
-#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
-#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
-#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)                          
-#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
-#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
-
-/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
-#define USB_OTG_GOTGINT_SEDET_Pos                (2U)                          
-#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
-#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
-#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)                          
-#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
-#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
-#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)                          
-#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
-#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
-#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)                         
-#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
-#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
-#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)                         
-#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
-#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
-#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)                         
-#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
-#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
-
-/********************  Bit definition for USB_OTG_DCTL register  ********************/
-#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)                          
-#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
-#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
-#define USB_OTG_DCTL_SDIS_Pos                    (1U)                          
-#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
-#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
-#define USB_OTG_DCTL_GINSTS_Pos                  (2U)                          
-#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
-#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
-#define USB_OTG_DCTL_GONSTS_Pos                  (3U)                          
-#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
-#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
-
-#define USB_OTG_DCTL_TCTL_Pos                    (4U)                          
-#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
-#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
-#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
-#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
-#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
-#define USB_OTG_DCTL_SGINAK_Pos                  (7U)                          
-#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
-#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
-#define USB_OTG_DCTL_CGINAK_Pos                  (8U)                          
-#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
-#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
-#define USB_OTG_DCTL_SGONAK_Pos                  (9U)                          
-#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
-#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
-#define USB_OTG_DCTL_CGONAK_Pos                  (10U)                         
-#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
-#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
-#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)                         
-#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
-#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
-
-/********************  Bit definition for USB_OTG_HFIR register  ********************/
-#define USB_OTG_HFIR_FRIVL_Pos                   (0U)                          
-#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
-
-/********************  Bit definition for USB_OTG_HFNUM register  ********************/
-#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)                          
-#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
-#define USB_OTG_HFNUM_FTREM_Pos                  (16U)                         
-#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
-
-/********************  Bit definition for USB_OTG_DSTS register  ********************/
-#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)                          
-#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
-#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
-
-#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)                          
-#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
-#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
-#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
-#define USB_OTG_DSTS_EERR_Pos                    (3U)                          
-#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
-#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
-#define USB_OTG_DSTS_FNSOF_Pos                   (8U)                          
-#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
-#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
-
-/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
-#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)                          
-#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
-#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
-#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)                          
-#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
-#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
-#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
-#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
-#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
-#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
-#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
-#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)                          
-#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
-#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
-#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)                          
-#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
-#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
-#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)                          
-#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
-#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
-
-/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
-
-#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)                          
-#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
-#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
-#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
-#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
-#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
-#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)                          
-#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
-#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
-#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)                          
-#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
-#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
-#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)                          
-#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
-#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
-#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)                         
-#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
-#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
-#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
-#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
-#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
-#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
-#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)                         
-#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
-#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
-#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)                         
-#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
-#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
-#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)                         
-#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
-#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
-#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)                         
-#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
-#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)                         
-#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
-#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)                         
-#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
-#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
-#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)                         
-#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
-#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
-#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)                         
-#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
-#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
-#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)                         
-#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
-#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
-#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)                         
-#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
-#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
-#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)                         
-#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
-#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
-#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)                         
-#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
-#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
-#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)                         
-#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
-
-/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
-#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)                          
-#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
-#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
-#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)                          
-#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
-#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
-#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)                          
-#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
-#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
-#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)                          
-#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
-#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
-#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)                          
-#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
-#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
-
-
-#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)                          
-#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
-#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
-#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
-#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
-#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
-#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
-#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
-#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)                         
-#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
-#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
-#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)                         
-#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
-#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
-
-/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
-#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)                          
-#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)                          
-#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)                          
-#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)                          
-#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)                          
-#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)                          
-#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
-#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)                          
-#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)                          
-#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
-
-/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
-#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)                          
-#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
-#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)                         
-#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
-#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
-#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
-#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
-
-#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)                         
-#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
-#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
-#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
-
-/********************  Bit definition for USB_OTG_HAINT register  ********************/
-#define USB_OTG_HAINT_HAINT_Pos                  (0U)                          
-#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
-
-/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
-#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)                          
-#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask              */
-#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)                          
-#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
-#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
-#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
-#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
-#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)                          
-#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
-#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)                          
-#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
-#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
-#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)                          
-#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
-#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)                          
-#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
-#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
-#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)                          
-#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
-#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)                          
-#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
-#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
-#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
-#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
-#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
-#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
-#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
-#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
-#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
-#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
-/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
-#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)                          
-#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
-#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
-#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)                          
-#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
-#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
-#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)                          
-#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
-#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
-#define USB_OTG_GINTSTS_SOF_Pos                  (3U)                          
-#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
-#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
-#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)                          
-#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
-#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
-#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)                          
-#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
-#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
-#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)                          
-#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
-#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
-#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)                          
-#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
-#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
-#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)                         
-#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
-#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
-#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)                         
-#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
-#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
-#define USB_OTG_GINTSTS_USBRST_Pos               (12U)                         
-#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
-#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
-#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)                         
-#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
-#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
-#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)                         
-#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
-#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
-#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)                         
-#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
-#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
-#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)                         
-#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
-#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
-#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)                         
-#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
-#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
-#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)                         
-#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
-#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)                         
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
-#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
-#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)                         
-#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
-#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
-#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)                         
-#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
-#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
-#define USB_OTG_GINTSTS_HCINT_Pos                (25U)                         
-#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
-#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
-#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)                         
-#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
-#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
-#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)                         
-#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
-#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
-#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)                         
-#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
-#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
-#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)                         
-#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
-#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
-#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)                         
-#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
-#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
-
-/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
-#define USB_OTG_GINTMSK_MMISM_Pos                (1U)                          
-#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
-#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
-#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)                          
-#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
-#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
-#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)                          
-#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
-#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
-#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)                          
-#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
-#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
-#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)                          
-#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
-#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
-#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)                          
-#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
-#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
-#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)                          
-#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
-#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
-#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)                         
-#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
-#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
-#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)                         
-#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
-#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
-#define USB_OTG_GINTMSK_USBRST_Pos               (12U)                         
-#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
-#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
-#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)                         
-#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
-#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
-#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)                         
-#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
-#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
-#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)                         
-#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
-#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
-#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)                         
-#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
-#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
-#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)                         
-#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
-#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
-#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)                         
-#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
-#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
-#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)                         
-#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
-#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)                         
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
-#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
-#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)                         
-#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
-#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
-#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)                         
-#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
-#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
-#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)                         
-#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
-#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
-#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)                         
-#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
-#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
-#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)                         
-#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
-#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
-#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)                         
-#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
-#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
-#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)                         
-#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
-#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
-#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)                         
-#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
-#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
-
-/********************  Bit definition for USB_OTG_DAINT register  ********************/
-#define USB_OTG_DAINT_IEPINT_Pos                 (0U)                          
-#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
-#define USB_OTG_DAINT_OEPINT_Pos                 (16U)                         
-#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
-
-/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
-#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)                          
-#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
-
-/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
-#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)                          
-#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
-#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
-#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)                          
-#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
-#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)                         
-#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
-#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
-#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)                         
-#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
-#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
-#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)                          
-#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
-#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)                         
-#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
-#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)                          
-#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
-#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)                          
-#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
-
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_NPTXFSA_Pos                      (0U)                          
-#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
-#define USB_OTG_NPTXFD_Pos                       (16U)                         
-#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
-#define USB_OTG_TX0FSA_Pos                       (0U)                          
-#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
-#define USB_OTG_TX0FD_Pos                        (16U)                         
-#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
-
-/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
-#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)                          
-#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
-#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
-
-/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
-#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)                          
-#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
-
-#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)                         
-#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
-#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
-
-#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)                         
-#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
-#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
-
-/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
-#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)                          
-#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
-#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
-#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)                          
-#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
-#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
-
-#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)                          
-#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
-#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
-#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
-#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
-#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)                         
-#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
-#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
-
-#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)                         
-#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
-#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
-#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
-#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)                         
-#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
-#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
-
-/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)                          
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
-
-/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
-#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)                          
-#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
-#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
-#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)                         
-#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
-#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
-
-/********************  Bit definition for USB_OTG_GCCFG register  ********************/
-#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)                         
-#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
-#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
-#define USB_OTG_GCCFG_I2CPADEN_Pos               (17U)                         
-#define USB_OTG_GCCFG_I2CPADEN_Msk               (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
-#define USB_OTG_GCCFG_I2CPADEN                   USB_OTG_GCCFG_I2CPADEN_Msk    /*!< Enable I2C bus connection for the external I2C PHY interface*/ 
-#define USB_OTG_GCCFG_VBUSASEN_Pos               (18U)                         
-#define USB_OTG_GCCFG_VBUSASEN_Msk               (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
-#define USB_OTG_GCCFG_VBUSASEN                   USB_OTG_GCCFG_VBUSASEN_Msk    /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_VBUSBSEN_Pos               (19U)                         
-#define USB_OTG_GCCFG_VBUSBSEN_Msk               (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
-#define USB_OTG_GCCFG_VBUSBSEN                   USB_OTG_GCCFG_VBUSBSEN_Msk    /*!< Enable the VBUS sensing device */
-#define USB_OTG_GCCFG_SOFOUTEN_Pos               (20U)                         
-#define USB_OTG_GCCFG_SOFOUTEN_Msk               (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
-#define USB_OTG_GCCFG_SOFOUTEN                   USB_OTG_GCCFG_SOFOUTEN_Msk    /*!< SOF output enable */
-#define USB_OTG_GCCFG_NOVBUSSENS_Pos             (21U)                         
-#define USB_OTG_GCCFG_NOVBUSSENS_Msk             (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
-#define USB_OTG_GCCFG_NOVBUSSENS                 USB_OTG_GCCFG_NOVBUSSENS_Msk  /*!< VBUS sensing disable option*/ 
-
-/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
-#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)                          
-#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
-#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)                         
-#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
-#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
-
-/********************  Bit definition for USB_OTG_CID register  ********************/
-#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)                          
-#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
-#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
-
-/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
-#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)                          
-#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
-#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)                          
-#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
-#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)                          
-#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)                          
-#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)                          
-#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
-#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
-#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)                          
-#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */
-#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)                          
-#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */
-#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)                         
-#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
-#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */
-
-/********************  Bit definition for USB_OTG_HPRT register  ********************/
-#define USB_OTG_HPRT_PCSTS_Pos                   (0U)                          
-#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
-#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
-#define USB_OTG_HPRT_PCDET_Pos                   (1U)                          
-#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
-#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
-#define USB_OTG_HPRT_PENA_Pos                    (2U)                          
-#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
-#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
-#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)                          
-#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
-#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
-#define USB_OTG_HPRT_POCA_Pos                    (4U)                          
-#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
-#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
-#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)                          
-#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
-#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
-#define USB_OTG_HPRT_PRES_Pos                    (6U)                          
-#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
-#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */
-#define USB_OTG_HPRT_PSUSP_Pos                   (7U)                          
-#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
-#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */
-#define USB_OTG_HPRT_PRST_Pos                    (8U)                          
-#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
-#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */
-
-#define USB_OTG_HPRT_PLSTS_Pos                   (10U)                         
-#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
-#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */
-#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
-#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
-#define USB_OTG_HPRT_PPWR_Pos                    (12U)                         
-#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
-#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */
-
-#define USB_OTG_HPRT_PTCTL_Pos                   (13U)                         
-#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
-#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */
-#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
-#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
-#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
-#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
-
-#define USB_OTG_HPRT_PSPD_Pos                    (17U)                         
-#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
-#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */
-#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
-#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
-
-/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
-#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)                          
-#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */
-#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)                          
-#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
-#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */
-#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)                          
-#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
-#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
-#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)                          
-#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
-#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)                          
-#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
-#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */
-#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)                          
-#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
-#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */
-#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)                          
-#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
-#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)                         
-#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
-#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */
-#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)                         
-#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
-#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */
-#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)                         
-#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
-#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */
-
-/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
-#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)                          
-#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */
-#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)                         
-#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */
-
-/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
-#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)                          
-#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
-#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */
-#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)                         
-#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
-#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */
-#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)                         
-#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
-#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */
-#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)                         
-#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
-#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */
-
-#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)                         
-#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
-#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */
-#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
-#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
-#define USB_OTG_DIEPCTL_STALL_Pos                (21U)                         
-#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
-#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */
-
-#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)                         
-#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
-#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */
-#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
-#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
-#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
-#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
-#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)                         
-#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
-#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */
-#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)                         
-#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
-#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
-#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */
-#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)                         
-#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
-#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */
-#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)                         
-#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
-#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */
-#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)                         
-#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
-#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */
-
-/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
-#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)                          
-#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
-#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
-
-#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)                         
-#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
-#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
-#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
-#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
-#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
-#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
-#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)                         
-#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
-#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
-#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)                         
-#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
-#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
-
-#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)                         
-#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
-#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
-#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
-#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
-
-#define USB_OTG_HCCHAR_MC_Pos                    (20U)                         
-#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
-#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
-#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
-#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
-
-#define USB_OTG_HCCHAR_DAD_Pos                   (22U)                         
-#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
-#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
-#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
-#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
-#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
-#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
-#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
-#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
-#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
-#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)                         
-#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
-#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
-#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)                         
-#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
-#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
-#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)                         
-#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
-#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
-
-/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
-
-#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)                          
-#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
-#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
-#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
-#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
-#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
-#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
-
-#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)                          
-#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
-#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
-#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
-#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
-#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
-#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
-#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
-#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
-#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
-
-#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)                         
-#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
-#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
-#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
-#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
-#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)                         
-#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
-#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
-#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)                         
-#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
-#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
-
-/********************  Bit definition for USB_OTG_HCINT register  ********************/
-#define USB_OTG_HCINT_XFRC_Pos                   (0U)                          
-#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
-#define USB_OTG_HCINT_CHH_Pos                    (1U)                          
-#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
-#define USB_OTG_HCINT_AHBERR_Pos                 (2U)                          
-#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
-#define USB_OTG_HCINT_STALL_Pos                  (3U)                          
-#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
-#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
-#define USB_OTG_HCINT_NAK_Pos                    (4U)                          
-#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
-#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
-#define USB_OTG_HCINT_ACK_Pos                    (5U)                          
-#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
-#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
-#define USB_OTG_HCINT_NYET_Pos                   (6U)                          
-#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
-#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
-#define USB_OTG_HCINT_TXERR_Pos                  (7U)                          
-#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
-#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
-#define USB_OTG_HCINT_BBERR_Pos                  (8U)                          
-#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
-#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
-#define USB_OTG_HCINT_FRMOR_Pos                  (9U)                          
-#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
-#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
-#define USB_OTG_HCINT_DTERR_Pos                  (10U)                         
-#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
-#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
-
-/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
-#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)                          
-#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
-#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
-#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)                          
-#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
-#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
-#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
-#define USB_OTG_DIEPINT_TOC_Pos                  (3U)                          
-#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
-#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
-#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)                          
-#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
-#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
-#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
-#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
-#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
-#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)                          
-#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
-#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
-#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)                          
-#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
-#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
-#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)                          
-#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
-#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
-#define USB_OTG_DIEPINT_BNA_Pos                  (9U)                          
-#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
-#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
-#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)                         
-#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
-#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
-#define USB_OTG_DIEPINT_BERR_Pos                 (12U)                         
-#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
-#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
-#define USB_OTG_DIEPINT_NAK_Pos                  (13U)                         
-#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
-#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
-
-/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
-#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)                          
-#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
-#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
-#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)                          
-#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
-#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
-#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)                          
-#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
-#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)                          
-#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
-#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
-#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)                          
-#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
-#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
-#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)                          
-#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
-#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
-#define USB_OTG_HCINTMSK_NYET_Pos                (6U)                          
-#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
-#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
-#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)                          
-#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
-#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
-#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)                          
-#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
-#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
-#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)                          
-#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
-#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
-#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)                         
-#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
-#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
-
-/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
-
-#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)                          
-#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
-#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)                         
-#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
-#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)                         
-#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
-#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
-/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
-#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)                          
-#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
-#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)                         
-#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
-#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)                         
-#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
-#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
-#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)                         
-#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
-#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
-#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
-#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
-
-/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
-#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)                          
-#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
-#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_HCDMA register  ********************/
-#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)                          
-#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
-#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
-
-/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
-#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)                          
-#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
-
-/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
-#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)                          
-#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
-#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
-#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)                         
-#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
-#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
-
-/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
-
-#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)                          
-#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
-#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
-#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)                         
-#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
-#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
-#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)                         
-#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
-#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
-#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
-#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)                         
-#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
-#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
-#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)                         
-#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
-#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
-#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
-#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
-#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)                         
-#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
-#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
-#define USB_OTG_DOEPCTL_STALL_Pos                (21U)                         
-#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
-#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
-#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)                         
-#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
-#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
-#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)                         
-#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
-#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
-#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)                         
-#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
-#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
-#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)                         
-#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
-#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
-
-/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
-#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)                          
-#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
-#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
-#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)                          
-#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
-#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
-#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
-#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
-#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
-#define USB_OTG_DOEPINT_STUP_Pos                 (3U)                          
-#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
-#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
-#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)                          
-#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
-#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
-#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)                          
-#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
-#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
-#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)                          
-#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
-#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
-#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
-#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
-#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
-#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
-#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
-#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
-#define USB_OTG_DOEPINT_NYET_Pos                 (14U)                         
-#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
-#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
-#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
-#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
-#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
-/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
-
-#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)                          
-#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
-#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
-#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)                         
-#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
-#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
-
-#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)                         
-#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
-#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
-#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
-#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
-
-/********************  Bit definition for PCGCCTL register  ********************/
-#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)                          
-#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
-#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
-#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)                          
-#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
-#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
-#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)                          
-#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
-#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
-
-/* Legacy define */
-/********************  Bit definition for OTG register  ********************/
-#define USB_OTG_CHNUM_Pos                        (0U)                          
-#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
-#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
-#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
-#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
-#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
-#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
-#define USB_OTG_BCNT_Pos                         (4U)                          
-#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
-#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
-
-#define USB_OTG_DPID_Pos                         (15U)                         
-#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
-#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
-#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
-#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
-
-#define USB_OTG_PKTSTS_Pos                       (17U)                         
-#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
-#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
-#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
-#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
-#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
-#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
-
-#define USB_OTG_EPNUM_Pos                        (0U)                          
-#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
-#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
-#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
-#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
-#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
-#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
-
-#define USB_OTG_FRMNUM_Pos                       (21U)                         
-#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
-#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
-#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
-#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
-#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
-#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
-                                       ((INSTANCE) == ADC2) || \
-                                       ((INSTANCE) == ADC3))
-
-#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
-
-/******************************* CAN Instances ********************************/
-#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
-                                       ((INSTANCE) == CAN2))
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances ********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
-
-/******************************* DCMI Instances *******************************/
-#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
-
-/******************************** DMA Instances *******************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7) || \
-                                              ((INSTANCE) == DMA2_Stream0) || \
-                                              ((INSTANCE) == DMA2_Stream1) || \
-                                              ((INSTANCE) == DMA2_Stream2) || \
-                                              ((INSTANCE) == DMA2_Stream3) || \
-                                              ((INSTANCE) == DMA2_Stream4) || \
-                                              ((INSTANCE) == DMA2_Stream5) || \
-                                              ((INSTANCE) == DMA2_Stream6) || \
-                                              ((INSTANCE) == DMA2_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH) || \
-                                        ((INSTANCE) == GPIOI))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************* SMBUS Instances ******************************/
-#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE
-
-/******************************** I2S Instances *******************************/
-
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/*************************** I2S Extended Instances ***************************/
-#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
-                                           ((INSTANCE) == I2S3ext))
-/* Legacy Defines */
-#define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
-                                    ((INSTANCE) == TIM2) || \
-                                    ((INSTANCE) == TIM3) || \
-                                    ((INSTANCE) == TIM4) || \
-                                    ((INSTANCE) == TIM5) || \
-                                    ((INSTANCE) == TIM6) || \
-                                    ((INSTANCE) == TIM7) || \
-                                    ((INSTANCE) == TIM8) || \
-                                    ((INSTANCE) == TIM9) || \
-                                    ((INSTANCE) == TIM10)|| \
-                                    ((INSTANCE) == TIM11)|| \
-                                    ((INSTANCE) == TIM12)|| \
-                                    ((INSTANCE) == TIM13)|| \
-                                    ((INSTANCE) == TIM14))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
-                                         ((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM8)  || \
-                                         ((INSTANCE) == TIM9)  || \
-                                         ((INSTANCE) == TIM10) || \
-                                         ((INSTANCE) == TIM11) || \
-                                         ((INSTANCE) == TIM12) || \
-                                         ((INSTANCE) == TIM13) || \
-                                         ((INSTANCE) == TIM14))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8) || \
-                                       ((INSTANCE) == TIM9) || \
-                                       ((INSTANCE) == TIM12)) 
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                           ((INSTANCE) == TIM8))
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                       ((INSTANCE) == TIM2) || \
-                                       ((INSTANCE) == TIM3) || \
-                                       ((INSTANCE) == TIM4) || \
-                                       ((INSTANCE) == TIM5) || \
-                                       ((INSTANCE) == TIM6) || \
-                                       ((INSTANCE) == TIM7) || \
-                                       ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM2) || \
-                                          ((INSTANCE) == TIM3) || \
-                                          ((INSTANCE) == TIM4) || \
-                                          ((INSTANCE) == TIM5) || \
-                                          ((INSTANCE) == TIM8))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                             ((INSTANCE) == TIM2) || \
-                                             ((INSTANCE) == TIM3) || \
-                                             ((INSTANCE) == TIM4) || \
-                                             ((INSTANCE) == TIM5) || \
-                                             ((INSTANCE) == TIM8))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
-                                          ((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM8))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                         ((INSTANCE) == TIM2) || \
-                                         ((INSTANCE) == TIM3) || \
-                                         ((INSTANCE) == TIM4) || \
-                                         ((INSTANCE) == TIM5) || \
-                                         ((INSTANCE) == TIM8) || \
-                                         ((INSTANCE) == TIM9) || \
-                                         ((INSTANCE) == TIM12))
-/********************** TIM Instances : 32 bit Counter ************************/
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
-                                              ((INSTANCE) == TIM5))
-
-/***************** TIM Instances : external trigger input available ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                        ((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3) || \
-                                        ((INSTANCE) == TIM4) || \
-                                        ((INSTANCE) == TIM5) || \
-                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM11))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM1) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM8) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM12) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM13) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM14) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-/************ TIM Instances : complementary output(s) available ***************/
-#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
-   ((((INSTANCE) == TIM1) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3)))            \
-    ||                                          \
-    (((INSTANCE) == TIM8) &&                    \
-     (((CHANNEL) == TIM_CHANNEL_1) ||           \
-      ((CHANNEL) == TIM_CHANNEL_2) ||           \
-      ((CHANNEL) == TIM_CHANNEL_3))))
-
-/****************** TIM Instances : supporting counting mode selection ********/
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2) || \
-                                                        ((INSTANCE) == TIM3) || \
-                                                        ((INSTANCE) == TIM4) || \
-                                                        ((INSTANCE) == TIM5) || \
-                                                        ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : supporting clock division *****************/
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
-                                                  ((INSTANCE) == TIM2) || \
-                                                  ((INSTANCE) == TIM3) || \
-                                                  ((INSTANCE) == TIM4) || \
-                                                  ((INSTANCE) == TIM5) || \
-                                                  ((INSTANCE) == TIM8) || \
-                                                  ((INSTANCE) == TIM9) || \
-                                                  ((INSTANCE) == TIM10)|| \
-                                                  ((INSTANCE) == TIM11)|| \
-                                                  ((INSTANCE) == TIM12)|| \
-                                                  ((INSTANCE) == TIM13)|| \
-                                                  ((INSTANCE) == TIM14))
-
-/****************** TIM Instances : supporting commutation event generation ***/
-#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
-                                                     ((INSTANCE) == TIM8))
-
-
-/****************** TIM Instances : supporting OCxREF clear *******************/
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
-                                                       ((INSTANCE) == TIM2) || \
-                                                       ((INSTANCE) == TIM3) || \
-                                                       ((INSTANCE) == TIM4) || \
-                                                       ((INSTANCE) == TIM5) || \
-                                                       ((INSTANCE) == TIM8))
-
-/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2) || \
-                                                        ((INSTANCE) == TIM3) || \
-                                                        ((INSTANCE) == TIM4) || \
-                                                        ((INSTANCE) == TIM5) || \
-                                                        ((INSTANCE) == TIM8) || \
-                                                        ((INSTANCE) == TIM9) || \
-                                                        ((INSTANCE) == TIM12))
-
-/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2) || \
-                                                        ((INSTANCE) == TIM3) || \
-                                                        ((INSTANCE) == TIM4) || \
-                                                        ((INSTANCE) == TIM5) || \
-                                                        ((INSTANCE) == TIM8))
-
-/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2) || \
-                                                        ((INSTANCE) == TIM3) || \
-                                                        ((INSTANCE) == TIM4) || \
-                                                        ((INSTANCE) == TIM5) || \
-                                                        ((INSTANCE) == TIM8) || \
-                                                        ((INSTANCE) == TIM9) || \
-                                                        ((INSTANCE) == TIM12))
-
-/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
-                                                        ((INSTANCE) == TIM2) || \
-                                                        ((INSTANCE) == TIM3) || \
-                                                        ((INSTANCE) == TIM4) || \
-                                                        ((INSTANCE) == TIM5) || \
-                                                        ((INSTANCE) == TIM8) || \
-                                                        ((INSTANCE) == TIM9) || \
-                                                        ((INSTANCE) == TIM12))
-
-/****************** TIM Instances : supporting repetition counter *************/
-#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                                       ((INSTANCE) == TIM8))
-
-/****************** TIM Instances : supporting encoder interface **************/
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                                      ((INSTANCE) == TIM2) || \
-                                                      ((INSTANCE) == TIM3) || \
-                                                      ((INSTANCE) == TIM4) || \
-                                                      ((INSTANCE) == TIM5) || \
-                                                      ((INSTANCE) == TIM8) || \
-                                                      ((INSTANCE) == TIM9) || \
-                                                      ((INSTANCE) == TIM12))
-/****************** TIM Instances : supporting Hall sensor interface **********/
-#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                                          ((INSTANCE) == TIM2) || \
-                                                          ((INSTANCE) == TIM3) || \
-                                                          ((INSTANCE) == TIM4) || \
-                                                          ((INSTANCE) == TIM5) || \
-                                                          ((INSTANCE) == TIM8))
-/****************** TIM Instances : supporting the break function *************/
-#define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
-                                          ((INSTANCE) == TIM8))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3) || \
-                                     ((INSTANCE) == USART6))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                               ((INSTANCE) == USART2) || \
-                                               ((INSTANCE) == USART3) || \
-                                               ((INSTANCE) == UART4)  || \
-                                               ((INSTANCE) == UART5)  || \
-                                               ((INSTANCE) == USART6))
-
-/* Legacy defines */
-#define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3) || \
-                                           ((INSTANCE) == USART6))
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
-
-/********************* UART Instances : Smart card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3) || \
-                                         ((INSTANCE) == USART6))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5)  || \
-                                    ((INSTANCE) == USART6))
-
-
-/*********************** PCD Instances ****************************************/
-#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                       ((INSTANCE) == USB_OTG_HS))
-
-/*********************** HCD Instances ****************************************/
-#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
-                                       ((INSTANCE) == USB_OTG_HS))
-
-/****************************** SDIO Instances ********************************/
-#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** USB Exported Constants ************************/
-#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
-#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
-#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
-#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
-
-/*
- * @brief Specific devices reset values definitions
- */
-#define RCC_PLLCFGR_RST_VALUE              0x24003010U
-#define RCC_PLLI2SCFGR_RST_VALUE           0x20003000U
-
-#define RCC_MAX_FREQUENCY           168000000U         /*!< Max frequency of family in Hz*/
-#define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */
-#define RCC_MAX_FREQUENCY_SCALE2    144000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */
-#define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */
-#define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */
-#define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */
-#define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */
-
-#define RCC_PLLN_MIN_VALUE                 50U
-#define RCC_PLLN_MAX_VALUE                432U
-
-#define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
-#define FLASH_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
-#define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
-#define FLASH_SCALE1_LATENCY4_FREQ   120000000U     /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */
-#define FLASH_SCALE1_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */
-
-#define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
-#define FLASH_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
-#define FLASH_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
-#define FLASH_SCALE2_LATENCY4_FREQ   12000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */
-
-#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
-#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
-#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
-#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
-/******************************************************************************/
-/*  For a painless codes migration between the STM32F4xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */
-/*  product lines within the same STM32F4 Family                              */
-/******************************************************************************/
-/* Aliases for __IRQn */
-#define FMC_IRQn              FSMC_IRQn
-
-/* Aliases for __IRQHandler */
-#define FMC_IRQHandler        FSMC_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F407xx_H */
+/**
+  ******************************************************************************
+  * @file    stm32f407xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32F407xx Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - peripherals registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS_Device
+  * @{
+  */
+
+/** @addtogroup stm32f407xx
+  * @{
+  */
+    
+#ifndef __STM32F407xx_H
+#define __STM32F407xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
+  */
+#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
+#define __MPU_PRESENT             1U       /*!< STM32F4XX provides an MPU                     */
+#define __NVIC_PRIO_BITS          4U       /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
+#define __FPU_PRESENT             1U       /*!< FPU present                                   */
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare global interrupt                             */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
+  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
+  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
+  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
+  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */
+  FPU_IRQn                    = 81      /*!< FPU global interrupt                                               */
+} IRQn_Type;
+/* Legacy define */
+#define  HASH_RNG_IRQn      RNG_IRQn
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */
+  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
+  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
+  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
+  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
+  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
+  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
+  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
+  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
+  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
+  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
+  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
+  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
+                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+  
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+  
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+  
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
+  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
+  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
+  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/** 
+  * @brief Ethernet MAC
+  */
+
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACFFR;
+  __IO uint32_t MACHTHR;
+  __IO uint32_t MACHTLR;
+  __IO uint32_t MACMIIAR;
+  __IO uint32_t MACMIIDR;
+  __IO uint32_t MACFCR;
+  __IO uint32_t MACVLANTR;             /*    8 */
+  uint32_t      RESERVED0[2];
+  __IO uint32_t MACRWUFFR;             /*   11 */
+  __IO uint32_t MACPMTCSR;
+  uint32_t      RESERVED1;
+  __IO uint32_t MACDBGR;
+  __IO uint32_t MACSR;                 /*   15 */
+  __IO uint32_t MACIMR;
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;               /*   24 */
+  uint32_t      RESERVED2[40];
+  __IO uint32_t MMCCR;                 /*   65 */
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;               /*   69 */
+  uint32_t      RESERVED3[14];
+  __IO uint32_t MMCTGFSCCR;            /*   84 */
+  __IO uint32_t MMCTGFMSCCR;
+  uint32_t      RESERVED4[5];
+  __IO uint32_t MMCTGFCR;
+  uint32_t      RESERVED5[10];
+  __IO uint32_t MMCRFCECR;
+  __IO uint32_t MMCRFAECR;
+  uint32_t      RESERVED6[10];
+  __IO uint32_t MMCRGUFCR;
+  uint32_t      RESERVED7[334];
+  __IO uint32_t PTPTSCR;
+  __IO uint32_t PTPSSIR;
+  __IO uint32_t PTPTSHR;
+  __IO uint32_t PTPTSLR;
+  __IO uint32_t PTPTSHUR;
+  __IO uint32_t PTPTSLUR;
+  __IO uint32_t PTPTSAR;
+  __IO uint32_t PTPTTHR;
+  __IO uint32_t PTPTTLR;
+  __IO uint32_t RESERVED8;
+  __IO uint32_t PTPTSSR;
+  uint32_t      RESERVED9[565];
+  __IO uint32_t DMABMR;
+  __IO uint32_t DMATPDR;
+  __IO uint32_t DMARPDR;
+  __IO uint32_t DMARDLAR;
+  __IO uint32_t DMATDLAR;
+  __IO uint32_t DMASR;
+  __IO uint32_t DMAOMR;
+  __IO uint32_t DMAIER;
+  __IO uint32_t DMAMFBOCR;
+  __IO uint32_t DMARSWTR;
+  uint32_t      RESERVED10[8];
+  __IO uint32_t DMACHTDR;
+  __IO uint32_t DMACHRDR;
+  __IO uint32_t DMACHTBAR;
+  __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
+  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
+  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
+  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
+  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */
+  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */
+  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */
+  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */
+  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */
+} FLASH_TypeDef;
+
+
+
+/** 
+  * @brief Flexible Static Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
+} FSMC_Bank1_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller Bank1E
+  */
+
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller Bank2
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
+  uint32_t      RESERVED1;  /*!< Reserved, 0x78                                                            */
+  uint32_t      RESERVED2;  /*!< Reserved, 0x7C                                                            */
+  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
+  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
+  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
+  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+  uint32_t      RESERVED3;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
+} FSMC_Bank2_3_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller Bank4
+  */
+
+typedef struct
+{
+  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
+  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
+  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
+  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
+  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
+} FSMC_Bank4_TypeDef; 
+
+/** 
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
+} GPIO_TypeDef;
+
+/** 
+  * @brief System configuration controller
+  */
+
+typedef struct
+{
+  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */
+  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
+  __IO uint32_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
+  __IO uint32_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
+  __IO uint32_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
+  __IO uint32_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
+  __IO uint32_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
+  __IO uint32_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
+  __IO uint32_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
+} I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+} IWDG_TypeDef;
+
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
+  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
+  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
+  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
+  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
+  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
+  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
+  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
+  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
+  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
+  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
+  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
+  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
+  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
+  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
+  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
+  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
+  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
+  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
+  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
+  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
+  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
+  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
+  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
+  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
+  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
+  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */
+  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */
+  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */
+  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */
+  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
+  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */
+  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */
+  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */
+  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
+  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
+  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
+  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
+  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
+  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
+  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
+  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
+  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
+  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
+  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
+  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
+  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
+  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
+  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
+  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
+  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
+  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
+  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
+  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
+  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
+} RTC_TypeDef;
+
+/** 
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;                 /*!< SDIO power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;                 /*!< SDI clock control register,     Address offset: 0x04 */
+  __IO uint32_t ARG;                   /*!< SDIO argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;                   /*!< SDIO command register,          Address offset: 0x0C */
+  __IO const uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
+  __IO const uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
+  __IO const uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
+  __IO const uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
+  __IO const uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;                /*!< SDIO data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;                  /*!< SDIO data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;                 /*!< SDIO data control register,     Address offset: 0x2C */
+  __IO const uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
+  __IO const uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;                   /*!< SDIO interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;                  /*!< SDIO mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];          /*!< Reserved, 0x40-0x44                                  */
+  __IO const uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];         /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;                  /*!< SDIO data FIFO register,        Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
+  __IO uint32_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
+  __IO uint32_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
+  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
+  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+  __IO uint32_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
+  __IO uint32_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
+  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
+  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
+} SPI_TypeDef;
+
+
+/** 
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint32_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
+  __IO uint32_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  __IO uint32_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
+  __IO uint32_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint32_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
+  __IO uint32_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
+  __IO uint32_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  __IO uint32_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
+} TIM_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+ 
+typedef struct
+{
+  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
+  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
+  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
+  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
+  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
+  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
+  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+} USART_TypeDef;
+
+/** 
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/** 
+  * @brief RNG
+  */
+  
+typedef struct 
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/** 
+  * @brief USB_OTG_Core_Registers
+  */
+typedef struct
+{
+  __IO uint32_t GOTGCTL;              /*!< USB_OTG Control and Status Register          000h */
+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */
+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */
+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */
+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */
+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */
+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */
+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */
+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */
+  uint32_t  Reserved40[48];           /*!< Reserved                                0x40-0xFF */
+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */
+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO                        */
+} USB_OTG_GlobalTypeDef;
+
+/** 
+  * @brief USB_OTG_device_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */
+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */
+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */
+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */
+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */
+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */
+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */
+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */
+  uint32_t  Reserved20;          /*!< Reserved                     820h */
+  uint32_t Reserved9;            /*!< Reserved                     824h */
+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */
+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */
+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */
+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */
+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */
+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */
+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */
+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */
+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */
+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */
+} USB_OTG_DeviceTypeDef;
+
+/** 
+  * @brief USB_OTG_IN_Endpoint-Specific_Register
+  */
+typedef struct 
+{
+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */
+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
+} USB_OTG_INEndpointTypeDef;
+
+/** 
+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
+  */
+typedef struct 
+{
+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
+} USB_OTG_OUTEndpointTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Mode_Register_Structures
+  */
+typedef struct 
+{
+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */
+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */
+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */
+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */
+} USB_OTG_HostTypeDef;
+
+/** 
+  * @brief USB_OTG_Host_Channel_Specific_Registers
+  */
+typedef struct
+{
+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */
+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */
+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */
+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */
+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */
+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */
+  uint32_t Reserved[2];           /*!< Reserved                                      */
+} USB_OTG_HostChannelTypeDef;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+#define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */
+#define CCMDATARAM_BASE       0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
+#define SRAM1_BASE            0x20000000UL /*!< SRAM1(112 KB) base address in the alias region                              */
+#define SRAM2_BASE            0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region                              */
+#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */
+#define BKPSRAM_BASE          0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region                         */
+#define FSMC_R_BASE           0xA0000000UL /*!< FSMC registers base address                                                */
+#define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region                          */
+#define SRAM2_BB_BASE         0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region                           */
+#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */
+#define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
+#define FLASH_END             0x080FFFFFUL /*!< FLASH end address                                                          */
+#define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */
+#define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */
+#define CCMDATARAM_END        0x1000FFFFUL /*!< CCM data RAM end address                                                   */
+
+/* Legacy defines */
+#define SRAM_BASE             SRAM1_BASE
+#define SRAM_BB_BASE          SRAM1_BB_BASE
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000UL)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400UL)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800UL)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400UL)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800UL)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00UL)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000UL)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00UL)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000UL)
+#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400UL)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
+#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000UL)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000UL)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000UL)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400UL)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)
+#define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300UL)
+/* Legacy define */
+#define ADC_BASE               ADC123_COMMON_BASE
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00UL)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000UL)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400UL)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800UL)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000UL)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800UL)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
+#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000UL)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100UL)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700UL)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000UL)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000UL)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)
+
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000UL)
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104UL)
+#define FSMC_Bank2_3_R_BASE   (FSMC_R_BASE + 0x0060UL)
+#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0UL)
+
+
+/*!< Debug MCU registers base address */
+#define DBGMCU_BASE           0xE0042000UL
+/*!< USB registers base address */
+#define USB_OTG_HS_PERIPH_BASE               0x40040000UL
+#define USB_OTG_FS_PERIPH_BASE               0x50000000UL
+
+#define USB_OTG_GLOBAL_BASE                  0x000UL
+#define USB_OTG_DEVICE_BASE                  0x800UL
+#define USB_OTG_IN_ENDPOINT_BASE             0x900UL
+#define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL
+#define USB_OTG_EP_REG_SIZE                  0x20UL
+#define USB_OTG_HOST_BASE                    0x400UL
+#define USB_OTG_HOST_PORT_BASE               0x440UL
+#define USB_OTG_HOST_CHANNEL_BASE            0x500UL
+#define USB_OTG_HOST_CHANNEL_SIZE            0x20UL
+#define USB_OTG_PCGCCTL_BASE                 0xE00UL
+#define USB_OTG_FIFO_BASE                    0x1000UL
+#define USB_OTG_FIFO_SIZE                    0x1000UL
+
+#define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */
+#define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC1                ((DAC_TypeDef *) DAC_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
+/* Legacy define */
+#define ADC                  ADC123_COMMON
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2_3        ((FSMC_Bank2_3_TypeDef *) FSMC_Bank2_3_R_BASE)
+#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
+#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+
+/** @addtogroup Hardware_Constant_Definition
+  * @{
+  */
+#define LSI_STARTUP_TIME                40U /*!< LSI Maximum startup time in us */
+/**
+  * @}
+  */
+
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define ADC_MULTIMODE_SUPPORT                                                  /*!<ADC Multimode feature available on specific devices */
+
+/********************  Bit definition for ADC_SR register  ********************/
+#define ADC_SR_AWD_Pos            (0U)                                         
+#define ADC_SR_AWD_Msk            (0x1UL << ADC_SR_AWD_Pos)                     /*!< 0x00000001 */
+#define ADC_SR_AWD                ADC_SR_AWD_Msk                               /*!<Analog watchdog flag */
+#define ADC_SR_EOC_Pos            (1U)                                         
+#define ADC_SR_EOC_Msk            (0x1UL << ADC_SR_EOC_Pos)                     /*!< 0x00000002 */
+#define ADC_SR_EOC                ADC_SR_EOC_Msk                               /*!<End of conversion */
+#define ADC_SR_JEOC_Pos           (2U)                                         
+#define ADC_SR_JEOC_Msk           (0x1UL << ADC_SR_JEOC_Pos)                    /*!< 0x00000004 */
+#define ADC_SR_JEOC               ADC_SR_JEOC_Msk                              /*!<Injected channel end of conversion */
+#define ADC_SR_JSTRT_Pos          (3U)                                         
+#define ADC_SR_JSTRT_Msk          (0x1UL << ADC_SR_JSTRT_Pos)                   /*!< 0x00000008 */
+#define ADC_SR_JSTRT              ADC_SR_JSTRT_Msk                             /*!<Injected channel Start flag */
+#define ADC_SR_STRT_Pos           (4U)                                         
+#define ADC_SR_STRT_Msk           (0x1UL << ADC_SR_STRT_Pos)                    /*!< 0x00000010 */
+#define ADC_SR_STRT               ADC_SR_STRT_Msk                              /*!<Regular channel Start flag */
+#define ADC_SR_OVR_Pos            (5U)                                         
+#define ADC_SR_OVR_Msk            (0x1UL << ADC_SR_OVR_Pos)                     /*!< 0x00000020 */
+#define ADC_SR_OVR                ADC_SR_OVR_Msk                               /*!<Overrun flag */
+
+/*******************  Bit definition for ADC_CR1 register  ********************/
+#define ADC_CR1_AWDCH_Pos         (0U)                                         
+#define ADC_CR1_AWDCH_Msk         (0x1FUL << ADC_CR1_AWDCH_Pos)                 /*!< 0x0000001F */
+#define ADC_CR1_AWDCH             ADC_CR1_AWDCH_Msk                            /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_CR1_AWDCH_0           (0x01UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000001 */
+#define ADC_CR1_AWDCH_1           (0x02UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000002 */
+#define ADC_CR1_AWDCH_2           (0x04UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000004 */
+#define ADC_CR1_AWDCH_3           (0x08UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000008 */
+#define ADC_CR1_AWDCH_4           (0x10UL << ADC_CR1_AWDCH_Pos)                 /*!< 0x00000010 */
+#define ADC_CR1_EOCIE_Pos         (5U)                                         
+#define ADC_CR1_EOCIE_Msk         (0x1UL << ADC_CR1_EOCIE_Pos)                  /*!< 0x00000020 */
+#define ADC_CR1_EOCIE             ADC_CR1_EOCIE_Msk                            /*!<Interrupt enable for EOC */
+#define ADC_CR1_AWDIE_Pos         (6U)                                         
+#define ADC_CR1_AWDIE_Msk         (0x1UL << ADC_CR1_AWDIE_Pos)                  /*!< 0x00000040 */
+#define ADC_CR1_AWDIE             ADC_CR1_AWDIE_Msk                            /*!<AAnalog Watchdog interrupt enable */
+#define ADC_CR1_JEOCIE_Pos        (7U)                                         
+#define ADC_CR1_JEOCIE_Msk        (0x1UL << ADC_CR1_JEOCIE_Pos)                 /*!< 0x00000080 */
+#define ADC_CR1_JEOCIE            ADC_CR1_JEOCIE_Msk                           /*!<Interrupt enable for injected channels */
+#define ADC_CR1_SCAN_Pos          (8U)                                         
+#define ADC_CR1_SCAN_Msk          (0x1UL << ADC_CR1_SCAN_Pos)                   /*!< 0x00000100 */
+#define ADC_CR1_SCAN              ADC_CR1_SCAN_Msk                             /*!<Scan mode */
+#define ADC_CR1_AWDSGL_Pos        (9U)                                         
+#define ADC_CR1_AWDSGL_Msk        (0x1UL << ADC_CR1_AWDSGL_Pos)                 /*!< 0x00000200 */
+#define ADC_CR1_AWDSGL            ADC_CR1_AWDSGL_Msk                           /*!<Enable the watchdog on a single channel in scan mode */
+#define ADC_CR1_JAUTO_Pos         (10U)                                        
+#define ADC_CR1_JAUTO_Msk         (0x1UL << ADC_CR1_JAUTO_Pos)                  /*!< 0x00000400 */
+#define ADC_CR1_JAUTO             ADC_CR1_JAUTO_Msk                            /*!<Automatic injected group conversion */
+#define ADC_CR1_DISCEN_Pos        (11U)                                        
+#define ADC_CR1_DISCEN_Msk        (0x1UL << ADC_CR1_DISCEN_Pos)                 /*!< 0x00000800 */
+#define ADC_CR1_DISCEN            ADC_CR1_DISCEN_Msk                           /*!<Discontinuous mode on regular channels */
+#define ADC_CR1_JDISCEN_Pos       (12U)                                        
+#define ADC_CR1_JDISCEN_Msk       (0x1UL << ADC_CR1_JDISCEN_Pos)                /*!< 0x00001000 */
+#define ADC_CR1_JDISCEN           ADC_CR1_JDISCEN_Msk                          /*!<Discontinuous mode on injected channels */
+#define ADC_CR1_DISCNUM_Pos       (13U)                                        
+#define ADC_CR1_DISCNUM_Msk       (0x7UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x0000E000 */
+#define ADC_CR1_DISCNUM           ADC_CR1_DISCNUM_Msk                          /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_CR1_DISCNUM_0         (0x1UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00002000 */
+#define ADC_CR1_DISCNUM_1         (0x2UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00004000 */
+#define ADC_CR1_DISCNUM_2         (0x4UL << ADC_CR1_DISCNUM_Pos)                /*!< 0x00008000 */
+#define ADC_CR1_JAWDEN_Pos        (22U)                                        
+#define ADC_CR1_JAWDEN_Msk        (0x1UL << ADC_CR1_JAWDEN_Pos)                 /*!< 0x00400000 */
+#define ADC_CR1_JAWDEN            ADC_CR1_JAWDEN_Msk                           /*!<Analog watchdog enable on injected channels */
+#define ADC_CR1_AWDEN_Pos         (23U)                                        
+#define ADC_CR1_AWDEN_Msk         (0x1UL << ADC_CR1_AWDEN_Pos)                  /*!< 0x00800000 */
+#define ADC_CR1_AWDEN             ADC_CR1_AWDEN_Msk                            /*!<Analog watchdog enable on regular channels */
+#define ADC_CR1_RES_Pos           (24U)                                        
+#define ADC_CR1_RES_Msk           (0x3UL << ADC_CR1_RES_Pos)                    /*!< 0x03000000 */
+#define ADC_CR1_RES               ADC_CR1_RES_Msk                              /*!<RES[2:0] bits (Resolution) */
+#define ADC_CR1_RES_0             (0x1UL << ADC_CR1_RES_Pos)                    /*!< 0x01000000 */
+#define ADC_CR1_RES_1             (0x2UL << ADC_CR1_RES_Pos)                    /*!< 0x02000000 */
+#define ADC_CR1_OVRIE_Pos         (26U)                                        
+#define ADC_CR1_OVRIE_Msk         (0x1UL << ADC_CR1_OVRIE_Pos)                  /*!< 0x04000000 */
+#define ADC_CR1_OVRIE             ADC_CR1_OVRIE_Msk                            /*!<overrun interrupt enable */
+  
+/*******************  Bit definition for ADC_CR2 register  ********************/
+#define ADC_CR2_ADON_Pos          (0U)                                         
+#define ADC_CR2_ADON_Msk          (0x1UL << ADC_CR2_ADON_Pos)                   /*!< 0x00000001 */
+#define ADC_CR2_ADON              ADC_CR2_ADON_Msk                             /*!<A/D Converter ON / OFF */
+#define ADC_CR2_CONT_Pos          (1U)                                         
+#define ADC_CR2_CONT_Msk          (0x1UL << ADC_CR2_CONT_Pos)                   /*!< 0x00000002 */
+#define ADC_CR2_CONT              ADC_CR2_CONT_Msk                             /*!<Continuous Conversion */
+#define ADC_CR2_DMA_Pos           (8U)                                         
+#define ADC_CR2_DMA_Msk           (0x1UL << ADC_CR2_DMA_Pos)                    /*!< 0x00000100 */
+#define ADC_CR2_DMA               ADC_CR2_DMA_Msk                              /*!<Direct Memory access mode */
+#define ADC_CR2_DDS_Pos           (9U)                                         
+#define ADC_CR2_DDS_Msk           (0x1UL << ADC_CR2_DDS_Pos)                    /*!< 0x00000200 */
+#define ADC_CR2_DDS               ADC_CR2_DDS_Msk                              /*!<DMA disable selection (Single ADC) */
+#define ADC_CR2_EOCS_Pos          (10U)                                        
+#define ADC_CR2_EOCS_Msk          (0x1UL << ADC_CR2_EOCS_Pos)                   /*!< 0x00000400 */
+#define ADC_CR2_EOCS              ADC_CR2_EOCS_Msk                             /*!<End of conversion selection */
+#define ADC_CR2_ALIGN_Pos         (11U)                                        
+#define ADC_CR2_ALIGN_Msk         (0x1UL << ADC_CR2_ALIGN_Pos)                  /*!< 0x00000800 */
+#define ADC_CR2_ALIGN             ADC_CR2_ALIGN_Msk                            /*!<Data Alignment */
+#define ADC_CR2_JEXTSEL_Pos       (16U)                                        
+#define ADC_CR2_JEXTSEL_Msk       (0xFUL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x000F0000 */
+#define ADC_CR2_JEXTSEL           ADC_CR2_JEXTSEL_Msk                          /*!<JEXTSEL[3:0] bits (External event select for injected group) */
+#define ADC_CR2_JEXTSEL_0         (0x1UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00010000 */
+#define ADC_CR2_JEXTSEL_1         (0x2UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00020000 */
+#define ADC_CR2_JEXTSEL_2         (0x4UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00040000 */
+#define ADC_CR2_JEXTSEL_3         (0x8UL << ADC_CR2_JEXTSEL_Pos)                /*!< 0x00080000 */
+#define ADC_CR2_JEXTEN_Pos        (20U)                                        
+#define ADC_CR2_JEXTEN_Msk        (0x3UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00300000 */
+#define ADC_CR2_JEXTEN            ADC_CR2_JEXTEN_Msk                           /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
+#define ADC_CR2_JEXTEN_0          (0x1UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00100000 */
+#define ADC_CR2_JEXTEN_1          (0x2UL << ADC_CR2_JEXTEN_Pos)                 /*!< 0x00200000 */
+#define ADC_CR2_JSWSTART_Pos      (22U)                                        
+#define ADC_CR2_JSWSTART_Msk      (0x1UL << ADC_CR2_JSWSTART_Pos)               /*!< 0x00400000 */
+#define ADC_CR2_JSWSTART          ADC_CR2_JSWSTART_Msk                         /*!<Start Conversion of injected channels */
+#define ADC_CR2_EXTSEL_Pos        (24U)                                        
+#define ADC_CR2_EXTSEL_Msk        (0xFUL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x0F000000 */
+#define ADC_CR2_EXTSEL            ADC_CR2_EXTSEL_Msk                           /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
+#define ADC_CR2_EXTSEL_0          (0x1UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x01000000 */
+#define ADC_CR2_EXTSEL_1          (0x2UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x02000000 */
+#define ADC_CR2_EXTSEL_2          (0x4UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x04000000 */
+#define ADC_CR2_EXTSEL_3          (0x8UL << ADC_CR2_EXTSEL_Pos)                 /*!< 0x08000000 */
+#define ADC_CR2_EXTEN_Pos         (28U)                                        
+#define ADC_CR2_EXTEN_Msk         (0x3UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x30000000 */
+#define ADC_CR2_EXTEN             ADC_CR2_EXTEN_Msk                            /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
+#define ADC_CR2_EXTEN_0           (0x1UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x10000000 */
+#define ADC_CR2_EXTEN_1           (0x2UL << ADC_CR2_EXTEN_Pos)                  /*!< 0x20000000 */
+#define ADC_CR2_SWSTART_Pos       (30U)                                        
+#define ADC_CR2_SWSTART_Msk       (0x1UL << ADC_CR2_SWSTART_Pos)                /*!< 0x40000000 */
+#define ADC_CR2_SWSTART           ADC_CR2_SWSTART_Msk                          /*!<Start Conversion of regular channels */
+
+/******************  Bit definition for ADC_SMPR1 register  *******************/
+#define ADC_SMPR1_SMP10_Pos       (0U)                                         
+#define ADC_SMPR1_SMP10_Msk       (0x7UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000007 */
+#define ADC_SMPR1_SMP10           ADC_SMPR1_SMP10_Msk                          /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMPR1_SMP10_0         (0x1UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000001 */
+#define ADC_SMPR1_SMP10_1         (0x2UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000002 */
+#define ADC_SMPR1_SMP10_2         (0x4UL << ADC_SMPR1_SMP10_Pos)                /*!< 0x00000004 */
+#define ADC_SMPR1_SMP11_Pos       (3U)                                         
+#define ADC_SMPR1_SMP11_Msk       (0x7UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000038 */
+#define ADC_SMPR1_SMP11           ADC_SMPR1_SMP11_Msk                          /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMPR1_SMP11_0         (0x1UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000008 */
+#define ADC_SMPR1_SMP11_1         (0x2UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000010 */
+#define ADC_SMPR1_SMP11_2         (0x4UL << ADC_SMPR1_SMP11_Pos)                /*!< 0x00000020 */
+#define ADC_SMPR1_SMP12_Pos       (6U)                                         
+#define ADC_SMPR1_SMP12_Msk       (0x7UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP12           ADC_SMPR1_SMP12_Msk                          /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMPR1_SMP12_0         (0x1UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000040 */
+#define ADC_SMPR1_SMP12_1         (0x2UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000080 */
+#define ADC_SMPR1_SMP12_2         (0x4UL << ADC_SMPR1_SMP12_Pos)                /*!< 0x00000100 */
+#define ADC_SMPR1_SMP13_Pos       (9U)                                         
+#define ADC_SMPR1_SMP13_Msk       (0x7UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP13           ADC_SMPR1_SMP13_Msk                          /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMPR1_SMP13_0         (0x1UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000200 */
+#define ADC_SMPR1_SMP13_1         (0x2UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000400 */
+#define ADC_SMPR1_SMP13_2         (0x4UL << ADC_SMPR1_SMP13_Pos)                /*!< 0x00000800 */
+#define ADC_SMPR1_SMP14_Pos       (12U)                                        
+#define ADC_SMPR1_SMP14_Msk       (0x7UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00007000 */
+#define ADC_SMPR1_SMP14           ADC_SMPR1_SMP14_Msk                          /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMPR1_SMP14_0         (0x1UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00001000 */
+#define ADC_SMPR1_SMP14_1         (0x2UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00002000 */
+#define ADC_SMPR1_SMP14_2         (0x4UL << ADC_SMPR1_SMP14_Pos)                /*!< 0x00004000 */
+#define ADC_SMPR1_SMP15_Pos       (15U)                                        
+#define ADC_SMPR1_SMP15_Msk       (0x7UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00038000 */
+#define ADC_SMPR1_SMP15           ADC_SMPR1_SMP15_Msk                          /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMPR1_SMP15_0         (0x1UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00008000 */
+#define ADC_SMPR1_SMP15_1         (0x2UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00010000 */
+#define ADC_SMPR1_SMP15_2         (0x4UL << ADC_SMPR1_SMP15_Pos)                /*!< 0x00020000 */
+#define ADC_SMPR1_SMP16_Pos       (18U)                                        
+#define ADC_SMPR1_SMP16_Msk       (0x7UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP16           ADC_SMPR1_SMP16_Msk                          /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMPR1_SMP16_0         (0x1UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00040000 */
+#define ADC_SMPR1_SMP16_1         (0x2UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00080000 */
+#define ADC_SMPR1_SMP16_2         (0x4UL << ADC_SMPR1_SMP16_Pos)                /*!< 0x00100000 */
+#define ADC_SMPR1_SMP17_Pos       (21U)                                        
+#define ADC_SMPR1_SMP17_Msk       (0x7UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP17           ADC_SMPR1_SMP17_Msk                          /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMPR1_SMP17_0         (0x1UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00200000 */
+#define ADC_SMPR1_SMP17_1         (0x2UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00400000 */
+#define ADC_SMPR1_SMP17_2         (0x4UL << ADC_SMPR1_SMP17_Pos)                /*!< 0x00800000 */
+#define ADC_SMPR1_SMP18_Pos       (24U)                                        
+#define ADC_SMPR1_SMP18_Msk       (0x7UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x07000000 */
+#define ADC_SMPR1_SMP18           ADC_SMPR1_SMP18_Msk                          /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
+#define ADC_SMPR1_SMP18_0         (0x1UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x01000000 */
+#define ADC_SMPR1_SMP18_1         (0x2UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x02000000 */
+#define ADC_SMPR1_SMP18_2         (0x4UL << ADC_SMPR1_SMP18_Pos)                /*!< 0x04000000 */
+
+/******************  Bit definition for ADC_SMPR2 register  *******************/
+#define ADC_SMPR2_SMP0_Pos        (0U)                                         
+#define ADC_SMPR2_SMP0_Msk        (0x7UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000007 */
+#define ADC_SMPR2_SMP0            ADC_SMPR2_SMP0_Msk                           /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMPR2_SMP0_0          (0x1UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000001 */
+#define ADC_SMPR2_SMP0_1          (0x2UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000002 */
+#define ADC_SMPR2_SMP0_2          (0x4UL << ADC_SMPR2_SMP0_Pos)                 /*!< 0x00000004 */
+#define ADC_SMPR2_SMP1_Pos        (3U)                                         
+#define ADC_SMPR2_SMP1_Msk        (0x7UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000038 */
+#define ADC_SMPR2_SMP1            ADC_SMPR2_SMP1_Msk                           /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMPR2_SMP1_0          (0x1UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000008 */
+#define ADC_SMPR2_SMP1_1          (0x2UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000010 */
+#define ADC_SMPR2_SMP1_2          (0x4UL << ADC_SMPR2_SMP1_Pos)                 /*!< 0x00000020 */
+#define ADC_SMPR2_SMP2_Pos        (6U)                                         
+#define ADC_SMPR2_SMP2_Msk        (0x7UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP2            ADC_SMPR2_SMP2_Msk                           /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMPR2_SMP2_0          (0x1UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000040 */
+#define ADC_SMPR2_SMP2_1          (0x2UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000080 */
+#define ADC_SMPR2_SMP2_2          (0x4UL << ADC_SMPR2_SMP2_Pos)                 /*!< 0x00000100 */
+#define ADC_SMPR2_SMP3_Pos        (9U)                                         
+#define ADC_SMPR2_SMP3_Msk        (0x7UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP3            ADC_SMPR2_SMP3_Msk                           /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMPR2_SMP3_0          (0x1UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000200 */
+#define ADC_SMPR2_SMP3_1          (0x2UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000400 */
+#define ADC_SMPR2_SMP3_2          (0x4UL << ADC_SMPR2_SMP3_Pos)                 /*!< 0x00000800 */
+#define ADC_SMPR2_SMP4_Pos        (12U)                                        
+#define ADC_SMPR2_SMP4_Msk        (0x7UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00007000 */
+#define ADC_SMPR2_SMP4            ADC_SMPR2_SMP4_Msk                           /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMPR2_SMP4_0          (0x1UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00001000 */
+#define ADC_SMPR2_SMP4_1          (0x2UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00002000 */
+#define ADC_SMPR2_SMP4_2          (0x4UL << ADC_SMPR2_SMP4_Pos)                 /*!< 0x00004000 */
+#define ADC_SMPR2_SMP5_Pos        (15U)                                        
+#define ADC_SMPR2_SMP5_Msk        (0x7UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00038000 */
+#define ADC_SMPR2_SMP5            ADC_SMPR2_SMP5_Msk                           /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMPR2_SMP5_0          (0x1UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00008000 */
+#define ADC_SMPR2_SMP5_1          (0x2UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00010000 */
+#define ADC_SMPR2_SMP5_2          (0x4UL << ADC_SMPR2_SMP5_Pos)                 /*!< 0x00020000 */
+#define ADC_SMPR2_SMP6_Pos        (18U)                                        
+#define ADC_SMPR2_SMP6_Msk        (0x7UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP6            ADC_SMPR2_SMP6_Msk                           /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMPR2_SMP6_0          (0x1UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00040000 */
+#define ADC_SMPR2_SMP6_1          (0x2UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00080000 */
+#define ADC_SMPR2_SMP6_2          (0x4UL << ADC_SMPR2_SMP6_Pos)                 /*!< 0x00100000 */
+#define ADC_SMPR2_SMP7_Pos        (21U)                                        
+#define ADC_SMPR2_SMP7_Msk        (0x7UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP7            ADC_SMPR2_SMP7_Msk                           /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMPR2_SMP7_0          (0x1UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00200000 */
+#define ADC_SMPR2_SMP7_1          (0x2UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00400000 */
+#define ADC_SMPR2_SMP7_2          (0x4UL << ADC_SMPR2_SMP7_Pos)                 /*!< 0x00800000 */
+#define ADC_SMPR2_SMP8_Pos        (24U)                                        
+#define ADC_SMPR2_SMP8_Msk        (0x7UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x07000000 */
+#define ADC_SMPR2_SMP8            ADC_SMPR2_SMP8_Msk                           /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMPR2_SMP8_0          (0x1UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x01000000 */
+#define ADC_SMPR2_SMP8_1          (0x2UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x02000000 */
+#define ADC_SMPR2_SMP8_2          (0x4UL << ADC_SMPR2_SMP8_Pos)                 /*!< 0x04000000 */
+#define ADC_SMPR2_SMP9_Pos        (27U)                                        
+#define ADC_SMPR2_SMP9_Msk        (0x7UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x38000000 */
+#define ADC_SMPR2_SMP9            ADC_SMPR2_SMP9_Msk                           /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMPR2_SMP9_0          (0x1UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x08000000 */
+#define ADC_SMPR2_SMP9_1          (0x2UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x10000000 */
+#define ADC_SMPR2_SMP9_2          (0x4UL << ADC_SMPR2_SMP9_Pos)                 /*!< 0x20000000 */
+
+/******************  Bit definition for ADC_JOFR1 register  *******************/
+#define ADC_JOFR1_JOFFSET1_Pos    (0U)                                         
+#define ADC_JOFR1_JOFFSET1_Msk    (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)           /*!< 0x00000FFF */
+#define ADC_JOFR1_JOFFSET1        ADC_JOFR1_JOFFSET1_Msk                       /*!<Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_JOFR2 register  *******************/
+#define ADC_JOFR2_JOFFSET2_Pos    (0U)                                         
+#define ADC_JOFR2_JOFFSET2_Msk    (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)           /*!< 0x00000FFF */
+#define ADC_JOFR2_JOFFSET2        ADC_JOFR2_JOFFSET2_Msk                       /*!<Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_JOFR3 register  *******************/
+#define ADC_JOFR3_JOFFSET3_Pos    (0U)                                         
+#define ADC_JOFR3_JOFFSET3_Msk    (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)           /*!< 0x00000FFF */
+#define ADC_JOFR3_JOFFSET3        ADC_JOFR3_JOFFSET3_Msk                       /*!<Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_JOFR4 register  *******************/
+#define ADC_JOFR4_JOFFSET4_Pos    (0U)                                         
+#define ADC_JOFR4_JOFFSET4_Msk    (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)           /*!< 0x00000FFF */
+#define ADC_JOFR4_JOFFSET4        ADC_JOFR4_JOFFSET4_Msk                       /*!<Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_HTR register  ********************/
+#define ADC_HTR_HT_Pos            (0U)                                         
+#define ADC_HTR_HT_Msk            (0xFFFUL << ADC_HTR_HT_Pos)                   /*!< 0x00000FFF */
+#define ADC_HTR_HT                ADC_HTR_HT_Msk                               /*!<Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_LTR register  ********************/
+#define ADC_LTR_LT_Pos            (0U)                                         
+#define ADC_LTR_LT_Msk            (0xFFFUL << ADC_LTR_LT_Pos)                   /*!< 0x00000FFF */
+#define ADC_LTR_LT                ADC_LTR_LT_Msk                               /*!<Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_SQR1 register  *******************/
+#define ADC_SQR1_SQ13_Pos         (0U)                                         
+#define ADC_SQR1_SQ13_Msk         (0x1FUL << ADC_SQR1_SQ13_Pos)                 /*!< 0x0000001F */
+#define ADC_SQR1_SQ13             ADC_SQR1_SQ13_Msk                            /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQR1_SQ13_0           (0x01UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000001 */
+#define ADC_SQR1_SQ13_1           (0x02UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000002 */
+#define ADC_SQR1_SQ13_2           (0x04UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000004 */
+#define ADC_SQR1_SQ13_3           (0x08UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000008 */
+#define ADC_SQR1_SQ13_4           (0x10UL << ADC_SQR1_SQ13_Pos)                 /*!< 0x00000010 */
+#define ADC_SQR1_SQ14_Pos         (5U)                                         
+#define ADC_SQR1_SQ14_Msk         (0x1FUL << ADC_SQR1_SQ14_Pos)                 /*!< 0x000003E0 */
+#define ADC_SQR1_SQ14             ADC_SQR1_SQ14_Msk                            /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQR1_SQ14_0           (0x01UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000020 */
+#define ADC_SQR1_SQ14_1           (0x02UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000040 */
+#define ADC_SQR1_SQ14_2           (0x04UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000080 */
+#define ADC_SQR1_SQ14_3           (0x08UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000100 */
+#define ADC_SQR1_SQ14_4           (0x10UL << ADC_SQR1_SQ14_Pos)                 /*!< 0x00000200 */
+#define ADC_SQR1_SQ15_Pos         (10U)                                        
+#define ADC_SQR1_SQ15_Msk         (0x1FUL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00007C00 */
+#define ADC_SQR1_SQ15             ADC_SQR1_SQ15_Msk                            /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQR1_SQ15_0           (0x01UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000400 */
+#define ADC_SQR1_SQ15_1           (0x02UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00000800 */
+#define ADC_SQR1_SQ15_2           (0x04UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00001000 */
+#define ADC_SQR1_SQ15_3           (0x08UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00002000 */
+#define ADC_SQR1_SQ15_4           (0x10UL << ADC_SQR1_SQ15_Pos)                 /*!< 0x00004000 */
+#define ADC_SQR1_SQ16_Pos         (15U)                                        
+#define ADC_SQR1_SQ16_Msk         (0x1FUL << ADC_SQR1_SQ16_Pos)                 /*!< 0x000F8000 */
+#define ADC_SQR1_SQ16             ADC_SQR1_SQ16_Msk                            /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQR1_SQ16_0           (0x01UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00008000 */
+#define ADC_SQR1_SQ16_1           (0x02UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00010000 */
+#define ADC_SQR1_SQ16_2           (0x04UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00020000 */
+#define ADC_SQR1_SQ16_3           (0x08UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00040000 */
+#define ADC_SQR1_SQ16_4           (0x10UL << ADC_SQR1_SQ16_Pos)                 /*!< 0x00080000 */
+#define ADC_SQR1_L_Pos            (20U)                                        
+#define ADC_SQR1_L_Msk            (0xFUL << ADC_SQR1_L_Pos)                     /*!< 0x00F00000 */
+#define ADC_SQR1_L                ADC_SQR1_L_Msk                               /*!<L[3:0] bits (Regular channel sequence length) */
+#define ADC_SQR1_L_0              (0x1UL << ADC_SQR1_L_Pos)                     /*!< 0x00100000 */
+#define ADC_SQR1_L_1              (0x2UL << ADC_SQR1_L_Pos)                     /*!< 0x00200000 */
+#define ADC_SQR1_L_2              (0x4UL << ADC_SQR1_L_Pos)                     /*!< 0x00400000 */
+#define ADC_SQR1_L_3              (0x8UL << ADC_SQR1_L_Pos)                     /*!< 0x00800000 */
+
+/*******************  Bit definition for ADC_SQR2 register  *******************/
+#define ADC_SQR2_SQ7_Pos          (0U)                                         
+#define ADC_SQR2_SQ7_Msk          (0x1FUL << ADC_SQR2_SQ7_Pos)                  /*!< 0x0000001F */
+#define ADC_SQR2_SQ7              ADC_SQR2_SQ7_Msk                             /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQR2_SQ7_0            (0x01UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000001 */
+#define ADC_SQR2_SQ7_1            (0x02UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000002 */
+#define ADC_SQR2_SQ7_2            (0x04UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000004 */
+#define ADC_SQR2_SQ7_3            (0x08UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000008 */
+#define ADC_SQR2_SQ7_4            (0x10UL << ADC_SQR2_SQ7_Pos)                  /*!< 0x00000010 */
+#define ADC_SQR2_SQ8_Pos          (5U)                                         
+#define ADC_SQR2_SQ8_Msk          (0x1FUL << ADC_SQR2_SQ8_Pos)                  /*!< 0x000003E0 */
+#define ADC_SQR2_SQ8              ADC_SQR2_SQ8_Msk                             /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQR2_SQ8_0            (0x01UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000020 */
+#define ADC_SQR2_SQ8_1            (0x02UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000040 */
+#define ADC_SQR2_SQ8_2            (0x04UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000080 */
+#define ADC_SQR2_SQ8_3            (0x08UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000100 */
+#define ADC_SQR2_SQ8_4            (0x10UL << ADC_SQR2_SQ8_Pos)                  /*!< 0x00000200 */
+#define ADC_SQR2_SQ9_Pos          (10U)                                        
+#define ADC_SQR2_SQ9_Msk          (0x1FUL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00007C00 */
+#define ADC_SQR2_SQ9              ADC_SQR2_SQ9_Msk                             /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQR2_SQ9_0            (0x01UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000400 */
+#define ADC_SQR2_SQ9_1            (0x02UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00000800 */
+#define ADC_SQR2_SQ9_2            (0x04UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00001000 */
+#define ADC_SQR2_SQ9_3            (0x08UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00002000 */
+#define ADC_SQR2_SQ9_4            (0x10UL << ADC_SQR2_SQ9_Pos)                  /*!< 0x00004000 */
+#define ADC_SQR2_SQ10_Pos         (15U)                                        
+#define ADC_SQR2_SQ10_Msk         (0x1FUL << ADC_SQR2_SQ10_Pos)                 /*!< 0x000F8000 */
+#define ADC_SQR2_SQ10             ADC_SQR2_SQ10_Msk                            /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQR2_SQ10_0           (0x01UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00008000 */
+#define ADC_SQR2_SQ10_1           (0x02UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00010000 */
+#define ADC_SQR2_SQ10_2           (0x04UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00020000 */
+#define ADC_SQR2_SQ10_3           (0x08UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00040000 */
+#define ADC_SQR2_SQ10_4           (0x10UL << ADC_SQR2_SQ10_Pos)                 /*!< 0x00080000 */
+#define ADC_SQR2_SQ11_Pos         (20U)                                        
+#define ADC_SQR2_SQ11_Msk         (0x1FUL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01F00000 */
+#define ADC_SQR2_SQ11             ADC_SQR2_SQ11_Msk                            /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQR2_SQ11_0           (0x01UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00100000 */
+#define ADC_SQR2_SQ11_1           (0x02UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00200000 */
+#define ADC_SQR2_SQ11_2           (0x04UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00400000 */
+#define ADC_SQR2_SQ11_3           (0x08UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x00800000 */
+#define ADC_SQR2_SQ11_4           (0x10UL << ADC_SQR2_SQ11_Pos)                 /*!< 0x01000000 */
+#define ADC_SQR2_SQ12_Pos         (25U)                                        
+#define ADC_SQR2_SQ12_Msk         (0x1FUL << ADC_SQR2_SQ12_Pos)                 /*!< 0x3E000000 */
+#define ADC_SQR2_SQ12             ADC_SQR2_SQ12_Msk                            /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQR2_SQ12_0           (0x01UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x02000000 */
+#define ADC_SQR2_SQ12_1           (0x02UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x04000000 */
+#define ADC_SQR2_SQ12_2           (0x04UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x08000000 */
+#define ADC_SQR2_SQ12_3           (0x08UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x10000000 */
+#define ADC_SQR2_SQ12_4           (0x10UL << ADC_SQR2_SQ12_Pos)                 /*!< 0x20000000 */
+
+/*******************  Bit definition for ADC_SQR3 register  *******************/
+#define ADC_SQR3_SQ1_Pos          (0U)                                         
+#define ADC_SQR3_SQ1_Msk          (0x1FUL << ADC_SQR3_SQ1_Pos)                  /*!< 0x0000001F */
+#define ADC_SQR3_SQ1              ADC_SQR3_SQ1_Msk                             /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQR3_SQ1_0            (0x01UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000001 */
+#define ADC_SQR3_SQ1_1            (0x02UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000002 */
+#define ADC_SQR3_SQ1_2            (0x04UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000004 */
+#define ADC_SQR3_SQ1_3            (0x08UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000008 */
+#define ADC_SQR3_SQ1_4            (0x10UL << ADC_SQR3_SQ1_Pos)                  /*!< 0x00000010 */
+#define ADC_SQR3_SQ2_Pos          (5U)                                         
+#define ADC_SQR3_SQ2_Msk          (0x1FUL << ADC_SQR3_SQ2_Pos)                  /*!< 0x000003E0 */
+#define ADC_SQR3_SQ2              ADC_SQR3_SQ2_Msk                             /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQR3_SQ2_0            (0x01UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000020 */
+#define ADC_SQR3_SQ2_1            (0x02UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000040 */
+#define ADC_SQR3_SQ2_2            (0x04UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000080 */
+#define ADC_SQR3_SQ2_3            (0x08UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000100 */
+#define ADC_SQR3_SQ2_4            (0x10UL << ADC_SQR3_SQ2_Pos)                  /*!< 0x00000200 */
+#define ADC_SQR3_SQ3_Pos          (10U)                                        
+#define ADC_SQR3_SQ3_Msk          (0x1FUL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00007C00 */
+#define ADC_SQR3_SQ3              ADC_SQR3_SQ3_Msk                             /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQR3_SQ3_0            (0x01UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000400 */
+#define ADC_SQR3_SQ3_1            (0x02UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00000800 */
+#define ADC_SQR3_SQ3_2            (0x04UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00001000 */
+#define ADC_SQR3_SQ3_3            (0x08UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00002000 */
+#define ADC_SQR3_SQ3_4            (0x10UL << ADC_SQR3_SQ3_Pos)                  /*!< 0x00004000 */
+#define ADC_SQR3_SQ4_Pos          (15U)                                        
+#define ADC_SQR3_SQ4_Msk          (0x1FUL << ADC_SQR3_SQ4_Pos)                  /*!< 0x000F8000 */
+#define ADC_SQR3_SQ4              ADC_SQR3_SQ4_Msk                             /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQR3_SQ4_0            (0x01UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00008000 */
+#define ADC_SQR3_SQ4_1            (0x02UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00010000 */
+#define ADC_SQR3_SQ4_2            (0x04UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00020000 */
+#define ADC_SQR3_SQ4_3            (0x08UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00040000 */
+#define ADC_SQR3_SQ4_4            (0x10UL << ADC_SQR3_SQ4_Pos)                  /*!< 0x00080000 */
+#define ADC_SQR3_SQ5_Pos          (20U)                                        
+#define ADC_SQR3_SQ5_Msk          (0x1FUL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01F00000 */
+#define ADC_SQR3_SQ5              ADC_SQR3_SQ5_Msk                             /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQR3_SQ5_0            (0x01UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00100000 */
+#define ADC_SQR3_SQ5_1            (0x02UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00200000 */
+#define ADC_SQR3_SQ5_2            (0x04UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00400000 */
+#define ADC_SQR3_SQ5_3            (0x08UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x00800000 */
+#define ADC_SQR3_SQ5_4            (0x10UL << ADC_SQR3_SQ5_Pos)                  /*!< 0x01000000 */
+#define ADC_SQR3_SQ6_Pos          (25U)                                        
+#define ADC_SQR3_SQ6_Msk          (0x1FUL << ADC_SQR3_SQ6_Pos)                  /*!< 0x3E000000 */
+#define ADC_SQR3_SQ6              ADC_SQR3_SQ6_Msk                             /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQR3_SQ6_0            (0x01UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x02000000 */
+#define ADC_SQR3_SQ6_1            (0x02UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x04000000 */
+#define ADC_SQR3_SQ6_2            (0x04UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x08000000 */
+#define ADC_SQR3_SQ6_3            (0x08UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x10000000 */
+#define ADC_SQR3_SQ6_4            (0x10UL << ADC_SQR3_SQ6_Pos)                  /*!< 0x20000000 */
+
+/*******************  Bit definition for ADC_JSQR register  *******************/
+#define ADC_JSQR_JSQ1_Pos         (0U)                                         
+#define ADC_JSQR_JSQ1_Msk         (0x1FUL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x0000001F */
+#define ADC_JSQR_JSQ1             ADC_JSQR_JSQ1_Msk                            /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  
+#define ADC_JSQR_JSQ1_0           (0x01UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000001 */
+#define ADC_JSQR_JSQ1_1           (0x02UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000002 */
+#define ADC_JSQR_JSQ1_2           (0x04UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000004 */
+#define ADC_JSQR_JSQ1_3           (0x08UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000008 */
+#define ADC_JSQR_JSQ1_4           (0x10UL << ADC_JSQR_JSQ1_Pos)                 /*!< 0x00000010 */
+#define ADC_JSQR_JSQ2_Pos         (5U)                                         
+#define ADC_JSQR_JSQ2_Msk         (0x1FUL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x000003E0 */
+#define ADC_JSQR_JSQ2             ADC_JSQR_JSQ2_Msk                            /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQR_JSQ2_0           (0x01UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000020 */
+#define ADC_JSQR_JSQ2_1           (0x02UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000040 */
+#define ADC_JSQR_JSQ2_2           (0x04UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000080 */
+#define ADC_JSQR_JSQ2_3           (0x08UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000100 */
+#define ADC_JSQR_JSQ2_4           (0x10UL << ADC_JSQR_JSQ2_Pos)                 /*!< 0x00000200 */
+#define ADC_JSQR_JSQ3_Pos         (10U)                                        
+#define ADC_JSQR_JSQ3_Msk         (0x1FUL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00007C00 */
+#define ADC_JSQR_JSQ3             ADC_JSQR_JSQ3_Msk                            /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQR_JSQ3_0           (0x01UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000400 */
+#define ADC_JSQR_JSQ3_1           (0x02UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00000800 */
+#define ADC_JSQR_JSQ3_2           (0x04UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00001000 */
+#define ADC_JSQR_JSQ3_3           (0x08UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00002000 */
+#define ADC_JSQR_JSQ3_4           (0x10UL << ADC_JSQR_JSQ3_Pos)                 /*!< 0x00004000 */
+#define ADC_JSQR_JSQ4_Pos         (15U)                                        
+#define ADC_JSQR_JSQ4_Msk         (0x1FUL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x000F8000 */
+#define ADC_JSQR_JSQ4             ADC_JSQR_JSQ4_Msk                            /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQR_JSQ4_0           (0x01UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00008000 */
+#define ADC_JSQR_JSQ4_1           (0x02UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00010000 */
+#define ADC_JSQR_JSQ4_2           (0x04UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00020000 */
+#define ADC_JSQR_JSQ4_3           (0x08UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00040000 */
+#define ADC_JSQR_JSQ4_4           (0x10UL << ADC_JSQR_JSQ4_Pos)                 /*!< 0x00080000 */
+#define ADC_JSQR_JL_Pos           (20U)                                        
+#define ADC_JSQR_JL_Msk           (0x3UL << ADC_JSQR_JL_Pos)                    /*!< 0x00300000 */
+#define ADC_JSQR_JL               ADC_JSQR_JL_Msk                              /*!<JL[1:0] bits (Injected Sequence length) */
+#define ADC_JSQR_JL_0             (0x1UL << ADC_JSQR_JL_Pos)                    /*!< 0x00100000 */
+#define ADC_JSQR_JL_1             (0x2UL << ADC_JSQR_JL_Pos)                    /*!< 0x00200000 */
+
+/*******************  Bit definition for ADC_JDR1 register  *******************/
+#define ADC_JDR1_JDATA_Pos        (0U)                                         
+#define ADC_JDR1_JDATA_Msk        (0xFFFFUL << ADC_JDR1_JDATA_Pos)              /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA            ADC_JDR1_JDATA_Msk                           /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR2 register  *******************/
+#define ADC_JDR2_JDATA_Pos        (0U)                                         
+#define ADC_JDR2_JDATA_Msk        (0xFFFFUL << ADC_JDR2_JDATA_Pos)              /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA            ADC_JDR2_JDATA_Msk                           /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR3 register  *******************/
+#define ADC_JDR3_JDATA_Pos        (0U)                                         
+#define ADC_JDR3_JDATA_Msk        (0xFFFFUL << ADC_JDR3_JDATA_Pos)              /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA            ADC_JDR3_JDATA_Msk                           /*!<Injected data */
+
+/*******************  Bit definition for ADC_JDR4 register  *******************/
+#define ADC_JDR4_JDATA_Pos        (0U)                                         
+#define ADC_JDR4_JDATA_Msk        (0xFFFFUL << ADC_JDR4_JDATA_Pos)              /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA            ADC_JDR4_JDATA_Msk                           /*!<Injected data */
+
+/********************  Bit definition for ADC_DR register  ********************/
+#define ADC_DR_DATA_Pos           (0U)                                         
+#define ADC_DR_DATA_Msk           (0xFFFFUL << ADC_DR_DATA_Pos)                 /*!< 0x0000FFFF */
+#define ADC_DR_DATA               ADC_DR_DATA_Msk                              /*!<Regular data */
+#define ADC_DR_ADC2DATA_Pos       (16U)                                        
+#define ADC_DR_ADC2DATA_Msk       (0xFFFFUL << ADC_DR_ADC2DATA_Pos)             /*!< 0xFFFF0000 */
+#define ADC_DR_ADC2DATA           ADC_DR_ADC2DATA_Msk                          /*!<ADC2 data */
+
+/*******************  Bit definition for ADC_CSR register  ********************/
+#define ADC_CSR_AWD1_Pos          (0U)                                         
+#define ADC_CSR_AWD1_Msk          (0x1UL << ADC_CSR_AWD1_Pos)                   /*!< 0x00000001 */
+#define ADC_CSR_AWD1              ADC_CSR_AWD1_Msk                             /*!<ADC1 Analog watchdog flag */
+#define ADC_CSR_EOC1_Pos          (1U)                                         
+#define ADC_CSR_EOC1_Msk          (0x1UL << ADC_CSR_EOC1_Pos)                   /*!< 0x00000002 */
+#define ADC_CSR_EOC1              ADC_CSR_EOC1_Msk                             /*!<ADC1 End of conversion */
+#define ADC_CSR_JEOC1_Pos         (2U)                                         
+#define ADC_CSR_JEOC1_Msk         (0x1UL << ADC_CSR_JEOC1_Pos)                  /*!< 0x00000004 */
+#define ADC_CSR_JEOC1             ADC_CSR_JEOC1_Msk                            /*!<ADC1 Injected channel end of conversion */
+#define ADC_CSR_JSTRT1_Pos        (3U)                                         
+#define ADC_CSR_JSTRT1_Msk        (0x1UL << ADC_CSR_JSTRT1_Pos)                 /*!< 0x00000008 */
+#define ADC_CSR_JSTRT1            ADC_CSR_JSTRT1_Msk                           /*!<ADC1 Injected channel Start flag */
+#define ADC_CSR_STRT1_Pos         (4U)                                         
+#define ADC_CSR_STRT1_Msk         (0x1UL << ADC_CSR_STRT1_Pos)                  /*!< 0x00000010 */
+#define ADC_CSR_STRT1             ADC_CSR_STRT1_Msk                            /*!<ADC1 Regular channel Start flag */
+#define ADC_CSR_OVR1_Pos          (5U)                                         
+#define ADC_CSR_OVR1_Msk          (0x1UL << ADC_CSR_OVR1_Pos)                   /*!< 0x00000020 */
+#define ADC_CSR_OVR1              ADC_CSR_OVR1_Msk                             /*!<ADC1 DMA overrun  flag */
+#define ADC_CSR_AWD2_Pos          (8U)                                         
+#define ADC_CSR_AWD2_Msk          (0x1UL << ADC_CSR_AWD2_Pos)                   /*!< 0x00000100 */
+#define ADC_CSR_AWD2              ADC_CSR_AWD2_Msk                             /*!<ADC2 Analog watchdog flag */
+#define ADC_CSR_EOC2_Pos          (9U)                                         
+#define ADC_CSR_EOC2_Msk          (0x1UL << ADC_CSR_EOC2_Pos)                   /*!< 0x00000200 */
+#define ADC_CSR_EOC2              ADC_CSR_EOC2_Msk                             /*!<ADC2 End of conversion */
+#define ADC_CSR_JEOC2_Pos         (10U)                                        
+#define ADC_CSR_JEOC2_Msk         (0x1UL << ADC_CSR_JEOC2_Pos)                  /*!< 0x00000400 */
+#define ADC_CSR_JEOC2             ADC_CSR_JEOC2_Msk                            /*!<ADC2 Injected channel end of conversion */
+#define ADC_CSR_JSTRT2_Pos        (11U)                                        
+#define ADC_CSR_JSTRT2_Msk        (0x1UL << ADC_CSR_JSTRT2_Pos)                 /*!< 0x00000800 */
+#define ADC_CSR_JSTRT2            ADC_CSR_JSTRT2_Msk                           /*!<ADC2 Injected channel Start flag */
+#define ADC_CSR_STRT2_Pos         (12U)                                        
+#define ADC_CSR_STRT2_Msk         (0x1UL << ADC_CSR_STRT2_Pos)                  /*!< 0x00001000 */
+#define ADC_CSR_STRT2             ADC_CSR_STRT2_Msk                            /*!<ADC2 Regular channel Start flag */
+#define ADC_CSR_OVR2_Pos          (13U)                                        
+#define ADC_CSR_OVR2_Msk          (0x1UL << ADC_CSR_OVR2_Pos)                   /*!< 0x00002000 */
+#define ADC_CSR_OVR2              ADC_CSR_OVR2_Msk                             /*!<ADC2 DMA overrun  flag */
+#define ADC_CSR_AWD3_Pos          (16U)                                        
+#define ADC_CSR_AWD3_Msk          (0x1UL << ADC_CSR_AWD3_Pos)                   /*!< 0x00010000 */
+#define ADC_CSR_AWD3              ADC_CSR_AWD3_Msk                             /*!<ADC3 Analog watchdog flag */
+#define ADC_CSR_EOC3_Pos          (17U)                                        
+#define ADC_CSR_EOC3_Msk          (0x1UL << ADC_CSR_EOC3_Pos)                   /*!< 0x00020000 */
+#define ADC_CSR_EOC3              ADC_CSR_EOC3_Msk                             /*!<ADC3 End of conversion */
+#define ADC_CSR_JEOC3_Pos         (18U)                                        
+#define ADC_CSR_JEOC3_Msk         (0x1UL << ADC_CSR_JEOC3_Pos)                  /*!< 0x00040000 */
+#define ADC_CSR_JEOC3             ADC_CSR_JEOC3_Msk                            /*!<ADC3 Injected channel end of conversion */
+#define ADC_CSR_JSTRT3_Pos        (19U)                                        
+#define ADC_CSR_JSTRT3_Msk        (0x1UL << ADC_CSR_JSTRT3_Pos)                 /*!< 0x00080000 */
+#define ADC_CSR_JSTRT3            ADC_CSR_JSTRT3_Msk                           /*!<ADC3 Injected channel Start flag */
+#define ADC_CSR_STRT3_Pos         (20U)                                        
+#define ADC_CSR_STRT3_Msk         (0x1UL << ADC_CSR_STRT3_Pos)                  /*!< 0x00100000 */
+#define ADC_CSR_STRT3             ADC_CSR_STRT3_Msk                            /*!<ADC3 Regular channel Start flag */
+#define ADC_CSR_OVR3_Pos          (21U)                                        
+#define ADC_CSR_OVR3_Msk          (0x1UL << ADC_CSR_OVR3_Pos)                   /*!< 0x00200000 */
+#define ADC_CSR_OVR3              ADC_CSR_OVR3_Msk                             /*!<ADC3 DMA overrun  flag */
+
+/* Legacy defines */
+#define  ADC_CSR_DOVR1                        ADC_CSR_OVR1
+#define  ADC_CSR_DOVR2                        ADC_CSR_OVR2
+#define  ADC_CSR_DOVR3                        ADC_CSR_OVR3
+
+/*******************  Bit definition for ADC_CCR register  ********************/
+#define ADC_CCR_MULTI_Pos         (0U)                                         
+#define ADC_CCR_MULTI_Msk         (0x1FUL << ADC_CCR_MULTI_Pos)                 /*!< 0x0000001F */
+#define ADC_CCR_MULTI             ADC_CCR_MULTI_Msk                            /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  
+#define ADC_CCR_MULTI_0           (0x01UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000001 */
+#define ADC_CCR_MULTI_1           (0x02UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000002 */
+#define ADC_CCR_MULTI_2           (0x04UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000004 */
+#define ADC_CCR_MULTI_3           (0x08UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000008 */
+#define ADC_CCR_MULTI_4           (0x10UL << ADC_CCR_MULTI_Pos)                 /*!< 0x00000010 */
+#define ADC_CCR_DELAY_Pos         (8U)                                         
+#define ADC_CCR_DELAY_Msk         (0xFUL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000F00 */
+#define ADC_CCR_DELAY             ADC_CCR_DELAY_Msk                            /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  
+#define ADC_CCR_DELAY_0           (0x1UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000100 */
+#define ADC_CCR_DELAY_1           (0x2UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000200 */
+#define ADC_CCR_DELAY_2           (0x4UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000400 */
+#define ADC_CCR_DELAY_3           (0x8UL << ADC_CCR_DELAY_Pos)                  /*!< 0x00000800 */
+#define ADC_CCR_DDS_Pos           (13U)                                        
+#define ADC_CCR_DDS_Msk           (0x1UL << ADC_CCR_DDS_Pos)                    /*!< 0x00002000 */
+#define ADC_CCR_DDS               ADC_CCR_DDS_Msk                              /*!<DMA disable selection (Multi-ADC mode) */
+#define ADC_CCR_DMA_Pos           (14U)                                        
+#define ADC_CCR_DMA_Msk           (0x3UL << ADC_CCR_DMA_Pos)                    /*!< 0x0000C000 */
+#define ADC_CCR_DMA               ADC_CCR_DMA_Msk                              /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  
+#define ADC_CCR_DMA_0             (0x1UL << ADC_CCR_DMA_Pos)                    /*!< 0x00004000 */
+#define ADC_CCR_DMA_1             (0x2UL << ADC_CCR_DMA_Pos)                    /*!< 0x00008000 */
+#define ADC_CCR_ADCPRE_Pos        (16U)                                        
+#define ADC_CCR_ADCPRE_Msk        (0x3UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00030000 */
+#define ADC_CCR_ADCPRE            ADC_CCR_ADCPRE_Msk                           /*!<ADCPRE[1:0] bits (ADC prescaler) */  
+#define ADC_CCR_ADCPRE_0          (0x1UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00010000 */
+#define ADC_CCR_ADCPRE_1          (0x2UL << ADC_CCR_ADCPRE_Pos)                 /*!< 0x00020000 */
+#define ADC_CCR_VBATE_Pos         (22U)                                        
+#define ADC_CCR_VBATE_Msk         (0x1UL << ADC_CCR_VBATE_Pos)                  /*!< 0x00400000 */
+#define ADC_CCR_VBATE             ADC_CCR_VBATE_Msk                            /*!<VBAT Enable */
+#define ADC_CCR_TSVREFE_Pos       (23U)                                        
+#define ADC_CCR_TSVREFE_Msk       (0x1UL << ADC_CCR_TSVREFE_Pos)                /*!< 0x00800000 */
+#define ADC_CCR_TSVREFE           ADC_CCR_TSVREFE_Msk                          /*!<Temperature Sensor and VREFINT Enable */
+
+/*******************  Bit definition for ADC_CDR register  ********************/
+#define ADC_CDR_DATA1_Pos         (0U)                                         
+#define ADC_CDR_DATA1_Msk         (0xFFFFUL << ADC_CDR_DATA1_Pos)               /*!< 0x0000FFFF */
+#define ADC_CDR_DATA1             ADC_CDR_DATA1_Msk                            /*!<1st data of a pair of regular conversions */
+#define ADC_CDR_DATA2_Pos         (16U)                                        
+#define ADC_CDR_DATA2_Msk         (0xFFFFUL << ADC_CDR_DATA2_Pos)               /*!< 0xFFFF0000 */
+#define ADC_CDR_DATA2             ADC_CDR_DATA2_Msk                            /*!<2nd data of a pair of regular conversions */
+
+/* Legacy defines */
+#define ADC_CDR_RDATA_MST         ADC_CDR_DATA1
+#define ADC_CDR_RDATA_SLV         ADC_CDR_DATA2
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Controller Area Network                            */
+/*                                                                            */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/*******************  Bit definition for CAN_MCR register  ********************/
+#define CAN_MCR_INRQ_Pos       (0U)                                            
+#define CAN_MCR_INRQ_Msk       (0x1UL << CAN_MCR_INRQ_Pos)                      /*!< 0x00000001 */
+#define CAN_MCR_INRQ           CAN_MCR_INRQ_Msk                                /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos      (1U)                                            
+#define CAN_MCR_SLEEP_Msk      (0x1UL << CAN_MCR_SLEEP_Pos)                     /*!< 0x00000002 */
+#define CAN_MCR_SLEEP          CAN_MCR_SLEEP_Msk                               /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos       (2U)                                            
+#define CAN_MCR_TXFP_Msk       (0x1UL << CAN_MCR_TXFP_Pos)                      /*!< 0x00000004 */
+#define CAN_MCR_TXFP           CAN_MCR_TXFP_Msk                                /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos       (3U)                                            
+#define CAN_MCR_RFLM_Msk       (0x1UL << CAN_MCR_RFLM_Pos)                      /*!< 0x00000008 */
+#define CAN_MCR_RFLM           CAN_MCR_RFLM_Msk                                /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos       (4U)                                            
+#define CAN_MCR_NART_Msk       (0x1UL << CAN_MCR_NART_Pos)                      /*!< 0x00000010 */
+#define CAN_MCR_NART           CAN_MCR_NART_Msk                                /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos       (5U)                                            
+#define CAN_MCR_AWUM_Msk       (0x1UL << CAN_MCR_AWUM_Pos)                      /*!< 0x00000020 */
+#define CAN_MCR_AWUM           CAN_MCR_AWUM_Msk                                /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos       (6U)                                            
+#define CAN_MCR_ABOM_Msk       (0x1UL << CAN_MCR_ABOM_Pos)                      /*!< 0x00000040 */
+#define CAN_MCR_ABOM           CAN_MCR_ABOM_Msk                                /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos       (7U)                                            
+#define CAN_MCR_TTCM_Msk       (0x1UL << CAN_MCR_TTCM_Pos)                      /*!< 0x00000080 */
+#define CAN_MCR_TTCM           CAN_MCR_TTCM_Msk                                /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos      (15U)                                           
+#define CAN_MCR_RESET_Msk      (0x1UL << CAN_MCR_RESET_Pos)                     /*!< 0x00008000 */
+#define CAN_MCR_RESET          CAN_MCR_RESET_Msk                               /*!<bxCAN software master reset */
+#define CAN_MCR_DBF_Pos        (16U)                                           
+#define CAN_MCR_DBF_Msk        (0x1UL << CAN_MCR_DBF_Pos)                       /*!< 0x00010000 */
+#define CAN_MCR_DBF            CAN_MCR_DBF_Msk                                 /*!<bxCAN Debug freeze */
+/*******************  Bit definition for CAN_MSR register  ********************/
+#define CAN_MSR_INAK_Pos       (0U)                                            
+#define CAN_MSR_INAK_Msk       (0x1UL << CAN_MSR_INAK_Pos)                      /*!< 0x00000001 */
+#define CAN_MSR_INAK           CAN_MSR_INAK_Msk                                /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos       (1U)                                            
+#define CAN_MSR_SLAK_Msk       (0x1UL << CAN_MSR_SLAK_Pos)                      /*!< 0x00000002 */
+#define CAN_MSR_SLAK           CAN_MSR_SLAK_Msk                                /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos       (2U)                                            
+#define CAN_MSR_ERRI_Msk       (0x1UL << CAN_MSR_ERRI_Pos)                      /*!< 0x00000004 */
+#define CAN_MSR_ERRI           CAN_MSR_ERRI_Msk                                /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos       (3U)                                            
+#define CAN_MSR_WKUI_Msk       (0x1UL << CAN_MSR_WKUI_Pos)                      /*!< 0x00000008 */
+#define CAN_MSR_WKUI           CAN_MSR_WKUI_Msk                                /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos      (4U)                                            
+#define CAN_MSR_SLAKI_Msk      (0x1UL << CAN_MSR_SLAKI_Pos)                     /*!< 0x00000010 */
+#define CAN_MSR_SLAKI          CAN_MSR_SLAKI_Msk                               /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos        (8U)                                            
+#define CAN_MSR_TXM_Msk        (0x1UL << CAN_MSR_TXM_Pos)                       /*!< 0x00000100 */
+#define CAN_MSR_TXM            CAN_MSR_TXM_Msk                                 /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos        (9U)                                            
+#define CAN_MSR_RXM_Msk        (0x1UL << CAN_MSR_RXM_Pos)                       /*!< 0x00000200 */
+#define CAN_MSR_RXM            CAN_MSR_RXM_Msk                                 /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos       (10U)                                           
+#define CAN_MSR_SAMP_Msk       (0x1UL << CAN_MSR_SAMP_Pos)                      /*!< 0x00000400 */
+#define CAN_MSR_SAMP           CAN_MSR_SAMP_Msk                                /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos         (11U)                                           
+#define CAN_MSR_RX_Msk         (0x1UL << CAN_MSR_RX_Pos)                        /*!< 0x00000800 */
+#define CAN_MSR_RX             CAN_MSR_RX_Msk                                  /*!<CAN Rx Signal */
+
+/*******************  Bit definition for CAN_TSR register  ********************/
+#define CAN_TSR_RQCP0_Pos      (0U)                                            
+#define CAN_TSR_RQCP0_Msk      (0x1UL << CAN_TSR_RQCP0_Pos)                     /*!< 0x00000001 */
+#define CAN_TSR_RQCP0          CAN_TSR_RQCP0_Msk                               /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos      (1U)                                            
+#define CAN_TSR_TXOK0_Msk      (0x1UL << CAN_TSR_TXOK0_Pos)                     /*!< 0x00000002 */
+#define CAN_TSR_TXOK0          CAN_TSR_TXOK0_Msk                               /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos      (2U)                                            
+#define CAN_TSR_ALST0_Msk      (0x1UL << CAN_TSR_ALST0_Pos)                     /*!< 0x00000004 */
+#define CAN_TSR_ALST0          CAN_TSR_ALST0_Msk                               /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos      (3U)                                            
+#define CAN_TSR_TERR0_Msk      (0x1UL << CAN_TSR_TERR0_Pos)                     /*!< 0x00000008 */
+#define CAN_TSR_TERR0          CAN_TSR_TERR0_Msk                               /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos      (7U)                                            
+#define CAN_TSR_ABRQ0_Msk      (0x1UL << CAN_TSR_ABRQ0_Pos)                     /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0          CAN_TSR_ABRQ0_Msk                               /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos      (8U)                                            
+#define CAN_TSR_RQCP1_Msk      (0x1UL << CAN_TSR_RQCP1_Pos)                     /*!< 0x00000100 */
+#define CAN_TSR_RQCP1          CAN_TSR_RQCP1_Msk                               /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos      (9U)                                            
+#define CAN_TSR_TXOK1_Msk      (0x1UL << CAN_TSR_TXOK1_Pos)                     /*!< 0x00000200 */
+#define CAN_TSR_TXOK1          CAN_TSR_TXOK1_Msk                               /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos      (10U)                                           
+#define CAN_TSR_ALST1_Msk      (0x1UL << CAN_TSR_ALST1_Pos)                     /*!< 0x00000400 */
+#define CAN_TSR_ALST1          CAN_TSR_ALST1_Msk                               /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos      (11U)                                           
+#define CAN_TSR_TERR1_Msk      (0x1UL << CAN_TSR_TERR1_Pos)                     /*!< 0x00000800 */
+#define CAN_TSR_TERR1          CAN_TSR_TERR1_Msk                               /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos      (15U)                                           
+#define CAN_TSR_ABRQ1_Msk      (0x1UL << CAN_TSR_ABRQ1_Pos)                     /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1          CAN_TSR_ABRQ1_Msk                               /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos      (16U)                                           
+#define CAN_TSR_RQCP2_Msk      (0x1UL << CAN_TSR_RQCP2_Pos)                     /*!< 0x00010000 */
+#define CAN_TSR_RQCP2          CAN_TSR_RQCP2_Msk                               /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos      (17U)                                           
+#define CAN_TSR_TXOK2_Msk      (0x1UL << CAN_TSR_TXOK2_Pos)                     /*!< 0x00020000 */
+#define CAN_TSR_TXOK2          CAN_TSR_TXOK2_Msk                               /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos      (18U)                                           
+#define CAN_TSR_ALST2_Msk      (0x1UL << CAN_TSR_ALST2_Pos)                     /*!< 0x00040000 */
+#define CAN_TSR_ALST2          CAN_TSR_ALST2_Msk                               /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos      (19U)                                           
+#define CAN_TSR_TERR2_Msk      (0x1UL << CAN_TSR_TERR2_Pos)                     /*!< 0x00080000 */
+#define CAN_TSR_TERR2          CAN_TSR_TERR2_Msk                               /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos      (23U)                                           
+#define CAN_TSR_ABRQ2_Msk      (0x1UL << CAN_TSR_ABRQ2_Pos)                     /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2          CAN_TSR_ABRQ2_Msk                               /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos       (24U)                                           
+#define CAN_TSR_CODE_Msk       (0x3UL << CAN_TSR_CODE_Pos)                      /*!< 0x03000000 */
+#define CAN_TSR_CODE           CAN_TSR_CODE_Msk                                /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos        (26U)                                           
+#define CAN_TSR_TME_Msk        (0x7UL << CAN_TSR_TME_Pos)                       /*!< 0x1C000000 */
+#define CAN_TSR_TME            CAN_TSR_TME_Msk                                 /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos       (26U)                                           
+#define CAN_TSR_TME0_Msk       (0x1UL << CAN_TSR_TME0_Pos)                      /*!< 0x04000000 */
+#define CAN_TSR_TME0           CAN_TSR_TME0_Msk                                /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos       (27U)                                           
+#define CAN_TSR_TME1_Msk       (0x1UL << CAN_TSR_TME1_Pos)                      /*!< 0x08000000 */
+#define CAN_TSR_TME1           CAN_TSR_TME1_Msk                                /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos       (28U)                                           
+#define CAN_TSR_TME2_Msk       (0x1UL << CAN_TSR_TME2_Pos)                      /*!< 0x10000000 */
+#define CAN_TSR_TME2           CAN_TSR_TME2_Msk                                /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos        (29U)                                           
+#define CAN_TSR_LOW_Msk        (0x7UL << CAN_TSR_LOW_Pos)                       /*!< 0xE0000000 */
+#define CAN_TSR_LOW            CAN_TSR_LOW_Msk                                 /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos       (29U)                                           
+#define CAN_TSR_LOW0_Msk       (0x1UL << CAN_TSR_LOW0_Pos)                      /*!< 0x20000000 */
+#define CAN_TSR_LOW0           CAN_TSR_LOW0_Msk                                /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos       (30U)                                           
+#define CAN_TSR_LOW1_Msk       (0x1UL << CAN_TSR_LOW1_Pos)                      /*!< 0x40000000 */
+#define CAN_TSR_LOW1           CAN_TSR_LOW1_Msk                                /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos       (31U)                                           
+#define CAN_TSR_LOW2_Msk       (0x1UL << CAN_TSR_LOW2_Pos)                      /*!< 0x80000000 */
+#define CAN_TSR_LOW2           CAN_TSR_LOW2_Msk                                /*!<Lowest Priority Flag for Mailbox 2 */
+
+/*******************  Bit definition for CAN_RF0R register  *******************/
+#define CAN_RF0R_FMP0_Pos      (0U)                                            
+#define CAN_RF0R_FMP0_Msk      (0x3UL << CAN_RF0R_FMP0_Pos)                     /*!< 0x00000003 */
+#define CAN_RF0R_FMP0          CAN_RF0R_FMP0_Msk                               /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos     (3U)                                            
+#define CAN_RF0R_FULL0_Msk     (0x1UL << CAN_RF0R_FULL0_Pos)                    /*!< 0x00000008 */
+#define CAN_RF0R_FULL0         CAN_RF0R_FULL0_Msk                              /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos     (4U)                                            
+#define CAN_RF0R_FOVR0_Msk     (0x1UL << CAN_RF0R_FOVR0_Pos)                    /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0         CAN_RF0R_FOVR0_Msk                              /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos     (5U)                                            
+#define CAN_RF0R_RFOM0_Msk     (0x1UL << CAN_RF0R_RFOM0_Pos)                    /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0         CAN_RF0R_RFOM0_Msk                              /*!<Release FIFO 0 Output Mailbox */
+
+/*******************  Bit definition for CAN_RF1R register  *******************/
+#define CAN_RF1R_FMP1_Pos      (0U)                                            
+#define CAN_RF1R_FMP1_Msk      (0x3UL << CAN_RF1R_FMP1_Pos)                     /*!< 0x00000003 */
+#define CAN_RF1R_FMP1          CAN_RF1R_FMP1_Msk                               /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos     (3U)                                            
+#define CAN_RF1R_FULL1_Msk     (0x1UL << CAN_RF1R_FULL1_Pos)                    /*!< 0x00000008 */
+#define CAN_RF1R_FULL1         CAN_RF1R_FULL1_Msk                              /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos     (4U)                                            
+#define CAN_RF1R_FOVR1_Msk     (0x1UL << CAN_RF1R_FOVR1_Pos)                    /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1         CAN_RF1R_FOVR1_Msk                              /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos     (5U)                                            
+#define CAN_RF1R_RFOM1_Msk     (0x1UL << CAN_RF1R_RFOM1_Pos)                    /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1         CAN_RF1R_RFOM1_Msk                              /*!<Release FIFO 1 Output Mailbox */
+
+/********************  Bit definition for CAN_IER register  *******************/
+#define CAN_IER_TMEIE_Pos      (0U)                                            
+#define CAN_IER_TMEIE_Msk      (0x1UL << CAN_IER_TMEIE_Pos)                     /*!< 0x00000001 */
+#define CAN_IER_TMEIE          CAN_IER_TMEIE_Msk                               /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos     (1U)                                            
+#define CAN_IER_FMPIE0_Msk     (0x1UL << CAN_IER_FMPIE0_Pos)                    /*!< 0x00000002 */
+#define CAN_IER_FMPIE0         CAN_IER_FMPIE0_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos      (2U)                                            
+#define CAN_IER_FFIE0_Msk      (0x1UL << CAN_IER_FFIE0_Pos)                     /*!< 0x00000004 */
+#define CAN_IER_FFIE0          CAN_IER_FFIE0_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos     (3U)                                            
+#define CAN_IER_FOVIE0_Msk     (0x1UL << CAN_IER_FOVIE0_Pos)                    /*!< 0x00000008 */
+#define CAN_IER_FOVIE0         CAN_IER_FOVIE0_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos     (4U)                                            
+#define CAN_IER_FMPIE1_Msk     (0x1UL << CAN_IER_FMPIE1_Pos)                    /*!< 0x00000010 */
+#define CAN_IER_FMPIE1         CAN_IER_FMPIE1_Msk                              /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos      (5U)                                            
+#define CAN_IER_FFIE1_Msk      (0x1UL << CAN_IER_FFIE1_Pos)                     /*!< 0x00000020 */
+#define CAN_IER_FFIE1          CAN_IER_FFIE1_Msk                               /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos     (6U)                                            
+#define CAN_IER_FOVIE1_Msk     (0x1UL << CAN_IER_FOVIE1_Pos)                    /*!< 0x00000040 */
+#define CAN_IER_FOVIE1         CAN_IER_FOVIE1_Msk                              /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos      (8U)                                            
+#define CAN_IER_EWGIE_Msk      (0x1UL << CAN_IER_EWGIE_Pos)                     /*!< 0x00000100 */
+#define CAN_IER_EWGIE          CAN_IER_EWGIE_Msk                               /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos      (9U)                                            
+#define CAN_IER_EPVIE_Msk      (0x1UL << CAN_IER_EPVIE_Pos)                     /*!< 0x00000200 */
+#define CAN_IER_EPVIE          CAN_IER_EPVIE_Msk                               /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos      (10U)                                           
+#define CAN_IER_BOFIE_Msk      (0x1UL << CAN_IER_BOFIE_Pos)                     /*!< 0x00000400 */
+#define CAN_IER_BOFIE          CAN_IER_BOFIE_Msk                               /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos      (11U)                                           
+#define CAN_IER_LECIE_Msk      (0x1UL << CAN_IER_LECIE_Pos)                     /*!< 0x00000800 */
+#define CAN_IER_LECIE          CAN_IER_LECIE_Msk                               /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos      (15U)                                           
+#define CAN_IER_ERRIE_Msk      (0x1UL << CAN_IER_ERRIE_Pos)                     /*!< 0x00008000 */
+#define CAN_IER_ERRIE          CAN_IER_ERRIE_Msk                               /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos      (16U)                                           
+#define CAN_IER_WKUIE_Msk      (0x1UL << CAN_IER_WKUIE_Pos)                     /*!< 0x00010000 */
+#define CAN_IER_WKUIE          CAN_IER_WKUIE_Msk                               /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos      (17U)                                           
+#define CAN_IER_SLKIE_Msk      (0x1UL << CAN_IER_SLKIE_Pos)                     /*!< 0x00020000 */
+#define CAN_IER_SLKIE          CAN_IER_SLKIE_Msk                               /*!<Sleep Interrupt Enable */
+#define CAN_IER_EWGIE_Pos      (8U)                                            
+
+/********************  Bit definition for CAN_ESR register  *******************/
+#define CAN_ESR_EWGF_Pos       (0U)                                            
+#define CAN_ESR_EWGF_Msk       (0x1UL << CAN_ESR_EWGF_Pos)                      /*!< 0x00000001 */
+#define CAN_ESR_EWGF           CAN_ESR_EWGF_Msk                                /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos       (1U)                                            
+#define CAN_ESR_EPVF_Msk       (0x1UL << CAN_ESR_EPVF_Pos)                      /*!< 0x00000002 */
+#define CAN_ESR_EPVF           CAN_ESR_EPVF_Msk                                /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos       (2U)                                            
+#define CAN_ESR_BOFF_Msk       (0x1UL << CAN_ESR_BOFF_Pos)                      /*!< 0x00000004 */
+#define CAN_ESR_BOFF           CAN_ESR_BOFF_Msk                                /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos        (4U)                                            
+#define CAN_ESR_LEC_Msk        (0x7UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000070 */
+#define CAN_ESR_LEC            CAN_ESR_LEC_Msk                                 /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0          (0x1UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000010 */
+#define CAN_ESR_LEC_1          (0x2UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000020 */
+#define CAN_ESR_LEC_2          (0x4UL << CAN_ESR_LEC_Pos)                       /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos        (16U)                                           
+#define CAN_ESR_TEC_Msk        (0xFFUL << CAN_ESR_TEC_Pos)                      /*!< 0x00FF0000 */
+#define CAN_ESR_TEC            CAN_ESR_TEC_Msk                                 /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos        (24U)                                           
+#define CAN_ESR_REC_Msk        (0xFFUL << CAN_ESR_REC_Pos)                      /*!< 0xFF000000 */
+#define CAN_ESR_REC            CAN_ESR_REC_Msk                                 /*!<Receive Error Counter */
+
+/*******************  Bit definition for CAN_BTR register  ********************/
+#define CAN_BTR_BRP_Pos        (0U)                                            
+#define CAN_BTR_BRP_Msk        (0x3FFUL << CAN_BTR_BRP_Pos)                     /*!< 0x000003FF */
+#define CAN_BTR_BRP            CAN_BTR_BRP_Msk                                 /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos        (16U)                                           
+#define CAN_BTR_TS1_Msk        (0xFUL << CAN_BTR_TS1_Pos)                       /*!< 0x000F0000 */
+#define CAN_BTR_TS1            CAN_BTR_TS1_Msk                                 /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0          (0x1UL << CAN_BTR_TS1_Pos)                       /*!< 0x00010000 */
+#define CAN_BTR_TS1_1          (0x2UL << CAN_BTR_TS1_Pos)                       /*!< 0x00020000 */
+#define CAN_BTR_TS1_2          (0x4UL << CAN_BTR_TS1_Pos)                       /*!< 0x00040000 */
+#define CAN_BTR_TS1_3          (0x8UL << CAN_BTR_TS1_Pos)                       /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos        (20U)                                           
+#define CAN_BTR_TS2_Msk        (0x7UL << CAN_BTR_TS2_Pos)                       /*!< 0x00700000 */
+#define CAN_BTR_TS2            CAN_BTR_TS2_Msk                                 /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0          (0x1UL << CAN_BTR_TS2_Pos)                       /*!< 0x00100000 */
+#define CAN_BTR_TS2_1          (0x2UL << CAN_BTR_TS2_Pos)                       /*!< 0x00200000 */
+#define CAN_BTR_TS2_2          (0x4UL << CAN_BTR_TS2_Pos)                       /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos        (24U)                                           
+#define CAN_BTR_SJW_Msk        (0x3UL << CAN_BTR_SJW_Pos)                       /*!< 0x03000000 */
+#define CAN_BTR_SJW            CAN_BTR_SJW_Msk                                 /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0          (0x1UL << CAN_BTR_SJW_Pos)                       /*!< 0x01000000 */
+#define CAN_BTR_SJW_1          (0x2UL << CAN_BTR_SJW_Pos)                       /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos       (30U)                                           
+#define CAN_BTR_LBKM_Msk       (0x1UL << CAN_BTR_LBKM_Pos)                      /*!< 0x40000000 */
+#define CAN_BTR_LBKM           CAN_BTR_LBKM_Msk                                /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos       (31U)                                           
+#define CAN_BTR_SILM_Msk       (0x1UL << CAN_BTR_SILM_Pos)                      /*!< 0x80000000 */
+#define CAN_BTR_SILM           CAN_BTR_SILM_Msk                                /*!<Silent Mode */
+
+
+/*!<Mailbox registers */
+/******************  Bit definition for CAN_TI0R register  ********************/
+#define CAN_TI0R_TXRQ_Pos      (0U)                                            
+#define CAN_TI0R_TXRQ_Msk      (0x1UL << CAN_TI0R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ          CAN_TI0R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos       (1U)                                            
+#define CAN_TI0R_RTR_Msk       (0x1UL << CAN_TI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI0R_RTR           CAN_TI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos       (2U)                                            
+#define CAN_TI0R_IDE_Msk       (0x1UL << CAN_TI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI0R_IDE           CAN_TI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos      (3U)                                            
+#define CAN_TI0R_EXID_Msk      (0x3FFFFUL << CAN_TI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID          CAN_TI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos      (21U)                                           
+#define CAN_TI0R_STID_Msk      (0x7FFUL << CAN_TI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI0R_STID          CAN_TI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/******************  Bit definition for CAN_TDT0R register  *******************/
+#define CAN_TDT0R_DLC_Pos      (0U)                                            
+#define CAN_TDT0R_DLC_Msk      (0xFUL << CAN_TDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT0R_DLC          CAN_TDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos      (8U)                                            
+#define CAN_TDT0R_TGT_Msk      (0x1UL << CAN_TDT0R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT0R_TGT          CAN_TDT0R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos     (16U)                                           
+#define CAN_TDT0R_TIME_Msk     (0xFFFFUL << CAN_TDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME         CAN_TDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/******************  Bit definition for CAN_TDL0R register  *******************/
+#define CAN_TDL0R_DATA0_Pos    (0U)                                            
+#define CAN_TDL0R_DATA0_Msk    (0xFFUL << CAN_TDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0        CAN_TDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos    (8U)                                            
+#define CAN_TDL0R_DATA1_Msk    (0xFFUL << CAN_TDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1        CAN_TDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos    (16U)                                           
+#define CAN_TDL0R_DATA2_Msk    (0xFFUL << CAN_TDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2        CAN_TDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos    (24U)                                           
+#define CAN_TDL0R_DATA3_Msk    (0xFFUL << CAN_TDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3        CAN_TDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/******************  Bit definition for CAN_TDH0R register  *******************/
+#define CAN_TDH0R_DATA4_Pos    (0U)                                            
+#define CAN_TDH0R_DATA4_Msk    (0xFFUL << CAN_TDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4        CAN_TDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos    (8U)                                            
+#define CAN_TDH0R_DATA5_Msk    (0xFFUL << CAN_TDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5        CAN_TDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos    (16U)                                           
+#define CAN_TDH0R_DATA6_Msk    (0xFFUL << CAN_TDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6        CAN_TDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos    (24U)                                           
+#define CAN_TDH0R_DATA7_Msk    (0xFFUL << CAN_TDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7        CAN_TDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI1R register  *******************/
+#define CAN_TI1R_TXRQ_Pos      (0U)                                            
+#define CAN_TI1R_TXRQ_Msk      (0x1UL << CAN_TI1R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ          CAN_TI1R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos       (1U)                                            
+#define CAN_TI1R_RTR_Msk       (0x1UL << CAN_TI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI1R_RTR           CAN_TI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos       (2U)                                            
+#define CAN_TI1R_IDE_Msk       (0x1UL << CAN_TI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI1R_IDE           CAN_TI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos      (3U)                                            
+#define CAN_TI1R_EXID_Msk      (0x3FFFFUL << CAN_TI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID          CAN_TI1R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos      (21U)                                           
+#define CAN_TI1R_STID_Msk      (0x7FFUL << CAN_TI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI1R_STID          CAN_TI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT1R register  ******************/
+#define CAN_TDT1R_DLC_Pos      (0U)                                            
+#define CAN_TDT1R_DLC_Msk      (0xFUL << CAN_TDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT1R_DLC          CAN_TDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos      (8U)                                            
+#define CAN_TDT1R_TGT_Msk      (0x1UL << CAN_TDT1R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT1R_TGT          CAN_TDT1R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos     (16U)                                           
+#define CAN_TDT1R_TIME_Msk     (0xFFFFUL << CAN_TDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME         CAN_TDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL1R register  ******************/
+#define CAN_TDL1R_DATA0_Pos    (0U)                                            
+#define CAN_TDL1R_DATA0_Msk    (0xFFUL << CAN_TDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0        CAN_TDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos    (8U)                                            
+#define CAN_TDL1R_DATA1_Msk    (0xFFUL << CAN_TDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1        CAN_TDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos    (16U)                                           
+#define CAN_TDL1R_DATA2_Msk    (0xFFUL << CAN_TDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2        CAN_TDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos    (24U)                                           
+#define CAN_TDL1R_DATA3_Msk    (0xFFUL << CAN_TDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3        CAN_TDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH1R register  ******************/
+#define CAN_TDH1R_DATA4_Pos    (0U)                                            
+#define CAN_TDH1R_DATA4_Msk    (0xFFUL << CAN_TDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4        CAN_TDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos    (8U)                                            
+#define CAN_TDH1R_DATA5_Msk    (0xFFUL << CAN_TDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5        CAN_TDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos    (16U)                                           
+#define CAN_TDH1R_DATA6_Msk    (0xFFUL << CAN_TDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6        CAN_TDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos    (24U)                                           
+#define CAN_TDH1R_DATA7_Msk    (0xFFUL << CAN_TDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7        CAN_TDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_TI2R register  *******************/
+#define CAN_TI2R_TXRQ_Pos      (0U)                                            
+#define CAN_TI2R_TXRQ_Msk      (0x1UL << CAN_TI2R_TXRQ_Pos)                     /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ          CAN_TI2R_TXRQ_Msk                               /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos       (1U)                                            
+#define CAN_TI2R_RTR_Msk       (0x1UL << CAN_TI2R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_TI2R_RTR           CAN_TI2R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos       (2U)                                            
+#define CAN_TI2R_IDE_Msk       (0x1UL << CAN_TI2R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_TI2R_IDE           CAN_TI2R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos      (3U)                                            
+#define CAN_TI2R_EXID_Msk      (0x3FFFFUL << CAN_TI2R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID          CAN_TI2R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos      (21U)                                           
+#define CAN_TI2R_STID_Msk      (0x7FFUL << CAN_TI2R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_TI2R_STID          CAN_TI2R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_TDT2R register  ******************/  
+#define CAN_TDT2R_DLC_Pos      (0U)                                            
+#define CAN_TDT2R_DLC_Msk      (0xFUL << CAN_TDT2R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_TDT2R_DLC          CAN_TDT2R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos      (8U)                                            
+#define CAN_TDT2R_TGT_Msk      (0x1UL << CAN_TDT2R_TGT_Pos)                     /*!< 0x00000100 */
+#define CAN_TDT2R_TGT          CAN_TDT2R_TGT_Msk                               /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos     (16U)                                           
+#define CAN_TDT2R_TIME_Msk     (0xFFFFUL << CAN_TDT2R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME         CAN_TDT2R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_TDL2R register  ******************/
+#define CAN_TDL2R_DATA0_Pos    (0U)                                            
+#define CAN_TDL2R_DATA0_Msk    (0xFFUL << CAN_TDL2R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0        CAN_TDL2R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos    (8U)                                            
+#define CAN_TDL2R_DATA1_Msk    (0xFFUL << CAN_TDL2R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1        CAN_TDL2R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos    (16U)                                           
+#define CAN_TDL2R_DATA2_Msk    (0xFFUL << CAN_TDL2R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2        CAN_TDL2R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos    (24U)                                           
+#define CAN_TDL2R_DATA3_Msk    (0xFFUL << CAN_TDL2R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3        CAN_TDL2R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_TDH2R register  ******************/
+#define CAN_TDH2R_DATA4_Pos    (0U)                                            
+#define CAN_TDH2R_DATA4_Msk    (0xFFUL << CAN_TDH2R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4        CAN_TDH2R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos    (8U)                                            
+#define CAN_TDH2R_DATA5_Msk    (0xFFUL << CAN_TDH2R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5        CAN_TDH2R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos    (16U)                                           
+#define CAN_TDH2R_DATA6_Msk    (0xFFUL << CAN_TDH2R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6        CAN_TDH2R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos    (24U)                                           
+#define CAN_TDH2R_DATA7_Msk    (0xFFUL << CAN_TDH2R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7        CAN_TDH2R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI0R register  *******************/
+#define CAN_RI0R_RTR_Pos       (1U)                                            
+#define CAN_RI0R_RTR_Msk       (0x1UL << CAN_RI0R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI0R_RTR           CAN_RI0R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos       (2U)                                            
+#define CAN_RI0R_IDE_Msk       (0x1UL << CAN_RI0R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI0R_IDE           CAN_RI0R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos      (3U)                                            
+#define CAN_RI0R_EXID_Msk      (0x3FFFFUL << CAN_RI0R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID          CAN_RI0R_EXID_Msk                               /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos      (21U)                                           
+#define CAN_RI0R_STID_Msk      (0x7FFUL << CAN_RI0R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI0R_STID          CAN_RI0R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT0R register  ******************/
+#define CAN_RDT0R_DLC_Pos      (0U)                                            
+#define CAN_RDT0R_DLC_Msk      (0xFUL << CAN_RDT0R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT0R_DLC          CAN_RDT0R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos      (8U)                                            
+#define CAN_RDT0R_FMI_Msk      (0xFFUL << CAN_RDT0R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI          CAN_RDT0R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos     (16U)                                           
+#define CAN_RDT0R_TIME_Msk     (0xFFFFUL << CAN_RDT0R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME         CAN_RDT0R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL0R register  ******************/
+#define CAN_RDL0R_DATA0_Pos    (0U)                                            
+#define CAN_RDL0R_DATA0_Msk    (0xFFUL << CAN_RDL0R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0        CAN_RDL0R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos    (8U)                                            
+#define CAN_RDL0R_DATA1_Msk    (0xFFUL << CAN_RDL0R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1        CAN_RDL0R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos    (16U)                                           
+#define CAN_RDL0R_DATA2_Msk    (0xFFUL << CAN_RDL0R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2        CAN_RDL0R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos    (24U)                                           
+#define CAN_RDL0R_DATA3_Msk    (0xFFUL << CAN_RDL0R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3        CAN_RDL0R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH0R register  ******************/
+#define CAN_RDH0R_DATA4_Pos    (0U)                                            
+#define CAN_RDH0R_DATA4_Msk    (0xFFUL << CAN_RDH0R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4        CAN_RDH0R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos    (8U)                                            
+#define CAN_RDH0R_DATA5_Msk    (0xFFUL << CAN_RDH0R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5        CAN_RDH0R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos    (16U)                                           
+#define CAN_RDH0R_DATA6_Msk    (0xFFUL << CAN_RDH0R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6        CAN_RDH0R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos    (24U)                                           
+#define CAN_RDH0R_DATA7_Msk    (0xFFUL << CAN_RDH0R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7        CAN_RDH0R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*******************  Bit definition for CAN_RI1R register  *******************/
+#define CAN_RI1R_RTR_Pos       (1U)                                            
+#define CAN_RI1R_RTR_Msk       (0x1UL << CAN_RI1R_RTR_Pos)                      /*!< 0x00000002 */
+#define CAN_RI1R_RTR           CAN_RI1R_RTR_Msk                                /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos       (2U)                                            
+#define CAN_RI1R_IDE_Msk       (0x1UL << CAN_RI1R_IDE_Pos)                      /*!< 0x00000004 */
+#define CAN_RI1R_IDE           CAN_RI1R_IDE_Msk                                /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos      (3U)                                            
+#define CAN_RI1R_EXID_Msk      (0x3FFFFUL << CAN_RI1R_EXID_Pos)                 /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID          CAN_RI1R_EXID_Msk                               /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos      (21U)                                           
+#define CAN_RI1R_STID_Msk      (0x7FFUL << CAN_RI1R_STID_Pos)                   /*!< 0xFFE00000 */
+#define CAN_RI1R_STID          CAN_RI1R_STID_Msk                               /*!<Standard Identifier or Extended Identifier */
+
+/*******************  Bit definition for CAN_RDT1R register  ******************/
+#define CAN_RDT1R_DLC_Pos      (0U)                                            
+#define CAN_RDT1R_DLC_Msk      (0xFUL << CAN_RDT1R_DLC_Pos)                     /*!< 0x0000000F */
+#define CAN_RDT1R_DLC          CAN_RDT1R_DLC_Msk                               /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos      (8U)                                            
+#define CAN_RDT1R_FMI_Msk      (0xFFUL << CAN_RDT1R_FMI_Pos)                    /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI          CAN_RDT1R_FMI_Msk                               /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos     (16U)                                           
+#define CAN_RDT1R_TIME_Msk     (0xFFFFUL << CAN_RDT1R_TIME_Pos)                 /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME         CAN_RDT1R_TIME_Msk                              /*!<Message Time Stamp */
+
+/*******************  Bit definition for CAN_RDL1R register  ******************/
+#define CAN_RDL1R_DATA0_Pos    (0U)                                            
+#define CAN_RDL1R_DATA0_Msk    (0xFFUL << CAN_RDL1R_DATA0_Pos)                  /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0        CAN_RDL1R_DATA0_Msk                             /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos    (8U)                                            
+#define CAN_RDL1R_DATA1_Msk    (0xFFUL << CAN_RDL1R_DATA1_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1        CAN_RDL1R_DATA1_Msk                             /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos    (16U)                                           
+#define CAN_RDL1R_DATA2_Msk    (0xFFUL << CAN_RDL1R_DATA2_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2        CAN_RDL1R_DATA2_Msk                             /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos    (24U)                                           
+#define CAN_RDL1R_DATA3_Msk    (0xFFUL << CAN_RDL1R_DATA3_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3        CAN_RDL1R_DATA3_Msk                             /*!<Data byte 3 */
+
+/*******************  Bit definition for CAN_RDH1R register  ******************/
+#define CAN_RDH1R_DATA4_Pos    (0U)                                            
+#define CAN_RDH1R_DATA4_Msk    (0xFFUL << CAN_RDH1R_DATA4_Pos)                  /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4        CAN_RDH1R_DATA4_Msk                             /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos    (8U)                                            
+#define CAN_RDH1R_DATA5_Msk    (0xFFUL << CAN_RDH1R_DATA5_Pos)                  /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5        CAN_RDH1R_DATA5_Msk                             /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos    (16U)                                           
+#define CAN_RDH1R_DATA6_Msk    (0xFFUL << CAN_RDH1R_DATA6_Pos)                  /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6        CAN_RDH1R_DATA6_Msk                             /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos    (24U)                                           
+#define CAN_RDH1R_DATA7_Msk    (0xFFUL << CAN_RDH1R_DATA7_Pos)                  /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7        CAN_RDH1R_DATA7_Msk                             /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/*******************  Bit definition for CAN_FMR register  ********************/
+#define CAN_FMR_FINIT_Pos      (0U)                                            
+#define CAN_FMR_FINIT_Msk      (0x1UL << CAN_FMR_FINIT_Pos)                     /*!< 0x00000001 */
+#define CAN_FMR_FINIT          CAN_FMR_FINIT_Msk                               /*!<Filter Init Mode */
+#define CAN_FMR_CAN2SB_Pos     (8U)                                            
+#define CAN_FMR_CAN2SB_Msk     (0x3FUL << CAN_FMR_CAN2SB_Pos)                   /*!< 0x00003F00 */
+#define CAN_FMR_CAN2SB         CAN_FMR_CAN2SB_Msk                              /*!<CAN2 start bank */
+
+/*******************  Bit definition for CAN_FM1R register  *******************/
+#define CAN_FM1R_FBM_Pos       (0U)                                            
+#define CAN_FM1R_FBM_Msk       (0xFFFFFFFUL << CAN_FM1R_FBM_Pos)                /*!< 0x0FFFFFFF */
+#define CAN_FM1R_FBM           CAN_FM1R_FBM_Msk                                /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos      (0U)                                            
+#define CAN_FM1R_FBM0_Msk      (0x1UL << CAN_FM1R_FBM0_Pos)                     /*!< 0x00000001 */
+#define CAN_FM1R_FBM0          CAN_FM1R_FBM0_Msk                               /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos      (1U)                                            
+#define CAN_FM1R_FBM1_Msk      (0x1UL << CAN_FM1R_FBM1_Pos)                     /*!< 0x00000002 */
+#define CAN_FM1R_FBM1          CAN_FM1R_FBM1_Msk                               /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos      (2U)                                            
+#define CAN_FM1R_FBM2_Msk      (0x1UL << CAN_FM1R_FBM2_Pos)                     /*!< 0x00000004 */
+#define CAN_FM1R_FBM2          CAN_FM1R_FBM2_Msk                               /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos      (3U)                                            
+#define CAN_FM1R_FBM3_Msk      (0x1UL << CAN_FM1R_FBM3_Pos)                     /*!< 0x00000008 */
+#define CAN_FM1R_FBM3          CAN_FM1R_FBM3_Msk                               /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos      (4U)                                            
+#define CAN_FM1R_FBM4_Msk      (0x1UL << CAN_FM1R_FBM4_Pos)                     /*!< 0x00000010 */
+#define CAN_FM1R_FBM4          CAN_FM1R_FBM4_Msk                               /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos      (5U)                                            
+#define CAN_FM1R_FBM5_Msk      (0x1UL << CAN_FM1R_FBM5_Pos)                     /*!< 0x00000020 */
+#define CAN_FM1R_FBM5          CAN_FM1R_FBM5_Msk                               /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos      (6U)                                            
+#define CAN_FM1R_FBM6_Msk      (0x1UL << CAN_FM1R_FBM6_Pos)                     /*!< 0x00000040 */
+#define CAN_FM1R_FBM6          CAN_FM1R_FBM6_Msk                               /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos      (7U)                                            
+#define CAN_FM1R_FBM7_Msk      (0x1UL << CAN_FM1R_FBM7_Pos)                     /*!< 0x00000080 */
+#define CAN_FM1R_FBM7          CAN_FM1R_FBM7_Msk                               /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos      (8U)                                            
+#define CAN_FM1R_FBM8_Msk      (0x1UL << CAN_FM1R_FBM8_Pos)                     /*!< 0x00000100 */
+#define CAN_FM1R_FBM8          CAN_FM1R_FBM8_Msk                               /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos      (9U)                                            
+#define CAN_FM1R_FBM9_Msk      (0x1UL << CAN_FM1R_FBM9_Pos)                     /*!< 0x00000200 */
+#define CAN_FM1R_FBM9          CAN_FM1R_FBM9_Msk                               /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos     (10U)                                           
+#define CAN_FM1R_FBM10_Msk     (0x1UL << CAN_FM1R_FBM10_Pos)                    /*!< 0x00000400 */
+#define CAN_FM1R_FBM10         CAN_FM1R_FBM10_Msk                              /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos     (11U)                                           
+#define CAN_FM1R_FBM11_Msk     (0x1UL << CAN_FM1R_FBM11_Pos)                    /*!< 0x00000800 */
+#define CAN_FM1R_FBM11         CAN_FM1R_FBM11_Msk                              /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos     (12U)                                           
+#define CAN_FM1R_FBM12_Msk     (0x1UL << CAN_FM1R_FBM12_Pos)                    /*!< 0x00001000 */
+#define CAN_FM1R_FBM12         CAN_FM1R_FBM12_Msk                              /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos     (13U)                                           
+#define CAN_FM1R_FBM13_Msk     (0x1UL << CAN_FM1R_FBM13_Pos)                    /*!< 0x00002000 */
+#define CAN_FM1R_FBM13         CAN_FM1R_FBM13_Msk                              /*!<Filter Init Mode bit 13 */
+#define CAN_FM1R_FBM14_Pos     (14U)                                           
+#define CAN_FM1R_FBM14_Msk     (0x1UL << CAN_FM1R_FBM14_Pos)                    /*!< 0x00004000 */
+#define CAN_FM1R_FBM14         CAN_FM1R_FBM14_Msk                              /*!<Filter Init Mode bit 14 */
+#define CAN_FM1R_FBM15_Pos     (15U)                                           
+#define CAN_FM1R_FBM15_Msk     (0x1UL << CAN_FM1R_FBM15_Pos)                    /*!< 0x00008000 */
+#define CAN_FM1R_FBM15         CAN_FM1R_FBM15_Msk                              /*!<Filter Init Mode bit 15 */
+#define CAN_FM1R_FBM16_Pos     (16U)                                           
+#define CAN_FM1R_FBM16_Msk     (0x1UL << CAN_FM1R_FBM16_Pos)                    /*!< 0x00010000 */
+#define CAN_FM1R_FBM16         CAN_FM1R_FBM16_Msk                              /*!<Filter Init Mode bit 16 */
+#define CAN_FM1R_FBM17_Pos     (17U)                                           
+#define CAN_FM1R_FBM17_Msk     (0x1UL << CAN_FM1R_FBM17_Pos)                    /*!< 0x00020000 */
+#define CAN_FM1R_FBM17         CAN_FM1R_FBM17_Msk                              /*!<Filter Init Mode bit 17 */
+#define CAN_FM1R_FBM18_Pos     (18U)                                           
+#define CAN_FM1R_FBM18_Msk     (0x1UL << CAN_FM1R_FBM18_Pos)                    /*!< 0x00040000 */
+#define CAN_FM1R_FBM18         CAN_FM1R_FBM18_Msk                              /*!<Filter Init Mode bit 18 */
+#define CAN_FM1R_FBM19_Pos     (19U)                                           
+#define CAN_FM1R_FBM19_Msk     (0x1UL << CAN_FM1R_FBM19_Pos)                    /*!< 0x00080000 */
+#define CAN_FM1R_FBM19         CAN_FM1R_FBM19_Msk                              /*!<Filter Init Mode bit 19 */
+#define CAN_FM1R_FBM20_Pos     (20U)                                           
+#define CAN_FM1R_FBM20_Msk     (0x1UL << CAN_FM1R_FBM20_Pos)                    /*!< 0x00100000 */
+#define CAN_FM1R_FBM20         CAN_FM1R_FBM20_Msk                              /*!<Filter Init Mode bit 20 */
+#define CAN_FM1R_FBM21_Pos     (21U)                                           
+#define CAN_FM1R_FBM21_Msk     (0x1UL << CAN_FM1R_FBM21_Pos)                    /*!< 0x00200000 */
+#define CAN_FM1R_FBM21         CAN_FM1R_FBM21_Msk                              /*!<Filter Init Mode bit 21 */
+#define CAN_FM1R_FBM22_Pos     (22U)                                           
+#define CAN_FM1R_FBM22_Msk     (0x1UL << CAN_FM1R_FBM22_Pos)                    /*!< 0x00400000 */
+#define CAN_FM1R_FBM22         CAN_FM1R_FBM22_Msk                              /*!<Filter Init Mode bit 22 */
+#define CAN_FM1R_FBM23_Pos     (23U)                                           
+#define CAN_FM1R_FBM23_Msk     (0x1UL << CAN_FM1R_FBM23_Pos)                    /*!< 0x00800000 */
+#define CAN_FM1R_FBM23         CAN_FM1R_FBM23_Msk                              /*!<Filter Init Mode bit 23 */
+#define CAN_FM1R_FBM24_Pos     (24U)                                           
+#define CAN_FM1R_FBM24_Msk     (0x1UL << CAN_FM1R_FBM24_Pos)                    /*!< 0x01000000 */
+#define CAN_FM1R_FBM24         CAN_FM1R_FBM24_Msk                              /*!<Filter Init Mode bit 24 */
+#define CAN_FM1R_FBM25_Pos     (25U)                                           
+#define CAN_FM1R_FBM25_Msk     (0x1UL << CAN_FM1R_FBM25_Pos)                    /*!< 0x02000000 */
+#define CAN_FM1R_FBM25         CAN_FM1R_FBM25_Msk                              /*!<Filter Init Mode bit 25 */
+#define CAN_FM1R_FBM26_Pos     (26U)                                           
+#define CAN_FM1R_FBM26_Msk     (0x1UL << CAN_FM1R_FBM26_Pos)                    /*!< 0x04000000 */
+#define CAN_FM1R_FBM26         CAN_FM1R_FBM26_Msk                              /*!<Filter Init Mode bit 26 */
+#define CAN_FM1R_FBM27_Pos     (27U)                                           
+#define CAN_FM1R_FBM27_Msk     (0x1UL << CAN_FM1R_FBM27_Pos)                    /*!< 0x08000000 */
+#define CAN_FM1R_FBM27         CAN_FM1R_FBM27_Msk                              /*!<Filter Init Mode bit 27 */
+
+/*******************  Bit definition for CAN_FS1R register  *******************/
+#define CAN_FS1R_FSC_Pos       (0U)                                            
+#define CAN_FS1R_FSC_Msk       (0xFFFFFFFUL << CAN_FS1R_FSC_Pos)                /*!< 0x0FFFFFFF */
+#define CAN_FS1R_FSC           CAN_FS1R_FSC_Msk                                /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos      (0U)                                            
+#define CAN_FS1R_FSC0_Msk      (0x1UL << CAN_FS1R_FSC0_Pos)                     /*!< 0x00000001 */
+#define CAN_FS1R_FSC0          CAN_FS1R_FSC0_Msk                               /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos      (1U)                                            
+#define CAN_FS1R_FSC1_Msk      (0x1UL << CAN_FS1R_FSC1_Pos)                     /*!< 0x00000002 */
+#define CAN_FS1R_FSC1          CAN_FS1R_FSC1_Msk                               /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos      (2U)                                            
+#define CAN_FS1R_FSC2_Msk      (0x1UL << CAN_FS1R_FSC2_Pos)                     /*!< 0x00000004 */
+#define CAN_FS1R_FSC2          CAN_FS1R_FSC2_Msk                               /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos      (3U)                                            
+#define CAN_FS1R_FSC3_Msk      (0x1UL << CAN_FS1R_FSC3_Pos)                     /*!< 0x00000008 */
+#define CAN_FS1R_FSC3          CAN_FS1R_FSC3_Msk                               /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos      (4U)                                            
+#define CAN_FS1R_FSC4_Msk      (0x1UL << CAN_FS1R_FSC4_Pos)                     /*!< 0x00000010 */
+#define CAN_FS1R_FSC4          CAN_FS1R_FSC4_Msk                               /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos      (5U)                                            
+#define CAN_FS1R_FSC5_Msk      (0x1UL << CAN_FS1R_FSC5_Pos)                     /*!< 0x00000020 */
+#define CAN_FS1R_FSC5          CAN_FS1R_FSC5_Msk                               /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos      (6U)                                            
+#define CAN_FS1R_FSC6_Msk      (0x1UL << CAN_FS1R_FSC6_Pos)                     /*!< 0x00000040 */
+#define CAN_FS1R_FSC6          CAN_FS1R_FSC6_Msk                               /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos      (7U)                                            
+#define CAN_FS1R_FSC7_Msk      (0x1UL << CAN_FS1R_FSC7_Pos)                     /*!< 0x00000080 */
+#define CAN_FS1R_FSC7          CAN_FS1R_FSC7_Msk                               /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos      (8U)                                            
+#define CAN_FS1R_FSC8_Msk      (0x1UL << CAN_FS1R_FSC8_Pos)                     /*!< 0x00000100 */
+#define CAN_FS1R_FSC8          CAN_FS1R_FSC8_Msk                               /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos      (9U)                                            
+#define CAN_FS1R_FSC9_Msk      (0x1UL << CAN_FS1R_FSC9_Pos)                     /*!< 0x00000200 */
+#define CAN_FS1R_FSC9          CAN_FS1R_FSC9_Msk                               /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos     (10U)                                           
+#define CAN_FS1R_FSC10_Msk     (0x1UL << CAN_FS1R_FSC10_Pos)                    /*!< 0x00000400 */
+#define CAN_FS1R_FSC10         CAN_FS1R_FSC10_Msk                              /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos     (11U)                                           
+#define CAN_FS1R_FSC11_Msk     (0x1UL << CAN_FS1R_FSC11_Pos)                    /*!< 0x00000800 */
+#define CAN_FS1R_FSC11         CAN_FS1R_FSC11_Msk                              /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos     (12U)                                           
+#define CAN_FS1R_FSC12_Msk     (0x1UL << CAN_FS1R_FSC12_Pos)                    /*!< 0x00001000 */
+#define CAN_FS1R_FSC12         CAN_FS1R_FSC12_Msk                              /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos     (13U)                                           
+#define CAN_FS1R_FSC13_Msk     (0x1UL << CAN_FS1R_FSC13_Pos)                    /*!< 0x00002000 */
+#define CAN_FS1R_FSC13         CAN_FS1R_FSC13_Msk                              /*!<Filter Scale Configuration bit 13 */
+#define CAN_FS1R_FSC14_Pos     (14U)                                           
+#define CAN_FS1R_FSC14_Msk     (0x1UL << CAN_FS1R_FSC14_Pos)                    /*!< 0x00004000 */
+#define CAN_FS1R_FSC14         CAN_FS1R_FSC14_Msk                              /*!<Filter Scale Configuration bit 14 */
+#define CAN_FS1R_FSC15_Pos     (15U)                                           
+#define CAN_FS1R_FSC15_Msk     (0x1UL << CAN_FS1R_FSC15_Pos)                    /*!< 0x00008000 */
+#define CAN_FS1R_FSC15         CAN_FS1R_FSC15_Msk                              /*!<Filter Scale Configuration bit 15 */
+#define CAN_FS1R_FSC16_Pos     (16U)                                           
+#define CAN_FS1R_FSC16_Msk     (0x1UL << CAN_FS1R_FSC16_Pos)                    /*!< 0x00010000 */
+#define CAN_FS1R_FSC16         CAN_FS1R_FSC16_Msk                              /*!<Filter Scale Configuration bit 16 */
+#define CAN_FS1R_FSC17_Pos     (17U)                                           
+#define CAN_FS1R_FSC17_Msk     (0x1UL << CAN_FS1R_FSC17_Pos)                    /*!< 0x00020000 */
+#define CAN_FS1R_FSC17         CAN_FS1R_FSC17_Msk                              /*!<Filter Scale Configuration bit 17 */
+#define CAN_FS1R_FSC18_Pos     (18U)                                           
+#define CAN_FS1R_FSC18_Msk     (0x1UL << CAN_FS1R_FSC18_Pos)                    /*!< 0x00040000 */
+#define CAN_FS1R_FSC18         CAN_FS1R_FSC18_Msk                              /*!<Filter Scale Configuration bit 18 */
+#define CAN_FS1R_FSC19_Pos     (19U)                                           
+#define CAN_FS1R_FSC19_Msk     (0x1UL << CAN_FS1R_FSC19_Pos)                    /*!< 0x00080000 */
+#define CAN_FS1R_FSC19         CAN_FS1R_FSC19_Msk                              /*!<Filter Scale Configuration bit 19 */
+#define CAN_FS1R_FSC20_Pos     (20U)                                           
+#define CAN_FS1R_FSC20_Msk     (0x1UL << CAN_FS1R_FSC20_Pos)                    /*!< 0x00100000 */
+#define CAN_FS1R_FSC20         CAN_FS1R_FSC20_Msk                              /*!<Filter Scale Configuration bit 20 */
+#define CAN_FS1R_FSC21_Pos     (21U)                                           
+#define CAN_FS1R_FSC21_Msk     (0x1UL << CAN_FS1R_FSC21_Pos)                    /*!< 0x00200000 */
+#define CAN_FS1R_FSC21         CAN_FS1R_FSC21_Msk                              /*!<Filter Scale Configuration bit 21 */
+#define CAN_FS1R_FSC22_Pos     (22U)                                           
+#define CAN_FS1R_FSC22_Msk     (0x1UL << CAN_FS1R_FSC22_Pos)                    /*!< 0x00400000 */
+#define CAN_FS1R_FSC22         CAN_FS1R_FSC22_Msk                              /*!<Filter Scale Configuration bit 22 */
+#define CAN_FS1R_FSC23_Pos     (23U)                                           
+#define CAN_FS1R_FSC23_Msk     (0x1UL << CAN_FS1R_FSC23_Pos)                    /*!< 0x00800000 */
+#define CAN_FS1R_FSC23         CAN_FS1R_FSC23_Msk                              /*!<Filter Scale Configuration bit 23 */
+#define CAN_FS1R_FSC24_Pos     (24U)                                           
+#define CAN_FS1R_FSC24_Msk     (0x1UL << CAN_FS1R_FSC24_Pos)                    /*!< 0x01000000 */
+#define CAN_FS1R_FSC24         CAN_FS1R_FSC24_Msk                              /*!<Filter Scale Configuration bit 24 */
+#define CAN_FS1R_FSC25_Pos     (25U)                                           
+#define CAN_FS1R_FSC25_Msk     (0x1UL << CAN_FS1R_FSC25_Pos)                    /*!< 0x02000000 */
+#define CAN_FS1R_FSC25         CAN_FS1R_FSC25_Msk                              /*!<Filter Scale Configuration bit 25 */
+#define CAN_FS1R_FSC26_Pos     (26U)                                           
+#define CAN_FS1R_FSC26_Msk     (0x1UL << CAN_FS1R_FSC26_Pos)                    /*!< 0x04000000 */
+#define CAN_FS1R_FSC26         CAN_FS1R_FSC26_Msk                              /*!<Filter Scale Configuration bit 26 */
+#define CAN_FS1R_FSC27_Pos     (27U)                                           
+#define CAN_FS1R_FSC27_Msk     (0x1UL << CAN_FS1R_FSC27_Pos)                    /*!< 0x08000000 */
+#define CAN_FS1R_FSC27         CAN_FS1R_FSC27_Msk                              /*!<Filter Scale Configuration bit 27 */
+
+/******************  Bit definition for CAN_FFA1R register  *******************/
+#define CAN_FFA1R_FFA_Pos      (0U)                                            
+#define CAN_FFA1R_FFA_Msk      (0xFFFFFFFUL << CAN_FFA1R_FFA_Pos)               /*!< 0x0FFFFFFF */
+#define CAN_FFA1R_FFA          CAN_FFA1R_FFA_Msk                               /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos     (0U)                                            
+#define CAN_FFA1R_FFA0_Msk     (0x1UL << CAN_FFA1R_FFA0_Pos)                    /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0         CAN_FFA1R_FFA0_Msk                              /*!<Filter FIFO Assignment bit 0 */
+#define CAN_FFA1R_FFA1_Pos     (1U)                                            
+#define CAN_FFA1R_FFA1_Msk     (0x1UL << CAN_FFA1R_FFA1_Pos)                    /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1         CAN_FFA1R_FFA1_Msk                              /*!<Filter FIFO Assignment bit 1 */
+#define CAN_FFA1R_FFA2_Pos     (2U)                                            
+#define CAN_FFA1R_FFA2_Msk     (0x1UL << CAN_FFA1R_FFA2_Pos)                    /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2         CAN_FFA1R_FFA2_Msk                              /*!<Filter FIFO Assignment bit 2 */
+#define CAN_FFA1R_FFA3_Pos     (3U)                                            
+#define CAN_FFA1R_FFA3_Msk     (0x1UL << CAN_FFA1R_FFA3_Pos)                    /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3         CAN_FFA1R_FFA3_Msk                              /*!<Filter FIFO Assignment bit 3 */
+#define CAN_FFA1R_FFA4_Pos     (4U)                                            
+#define CAN_FFA1R_FFA4_Msk     (0x1UL << CAN_FFA1R_FFA4_Pos)                    /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4         CAN_FFA1R_FFA4_Msk                              /*!<Filter FIFO Assignment bit 4 */
+#define CAN_FFA1R_FFA5_Pos     (5U)                                            
+#define CAN_FFA1R_FFA5_Msk     (0x1UL << CAN_FFA1R_FFA5_Pos)                    /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5         CAN_FFA1R_FFA5_Msk                              /*!<Filter FIFO Assignment bit 5 */
+#define CAN_FFA1R_FFA6_Pos     (6U)                                            
+#define CAN_FFA1R_FFA6_Msk     (0x1UL << CAN_FFA1R_FFA6_Pos)                    /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6         CAN_FFA1R_FFA6_Msk                              /*!<Filter FIFO Assignment bit 6 */
+#define CAN_FFA1R_FFA7_Pos     (7U)                                            
+#define CAN_FFA1R_FFA7_Msk     (0x1UL << CAN_FFA1R_FFA7_Pos)                    /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7         CAN_FFA1R_FFA7_Msk                              /*!<Filter FIFO Assignment bit 7 */
+#define CAN_FFA1R_FFA8_Pos     (8U)                                            
+#define CAN_FFA1R_FFA8_Msk     (0x1UL << CAN_FFA1R_FFA8_Pos)                    /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8         CAN_FFA1R_FFA8_Msk                              /*!<Filter FIFO Assignment bit 8 */
+#define CAN_FFA1R_FFA9_Pos     (9U)                                            
+#define CAN_FFA1R_FFA9_Msk     (0x1UL << CAN_FFA1R_FFA9_Pos)                    /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9         CAN_FFA1R_FFA9_Msk                              /*!<Filter FIFO Assignment bit 9 */
+#define CAN_FFA1R_FFA10_Pos    (10U)                                           
+#define CAN_FFA1R_FFA10_Msk    (0x1UL << CAN_FFA1R_FFA10_Pos)                   /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10        CAN_FFA1R_FFA10_Msk                             /*!<Filter FIFO Assignment bit 10 */
+#define CAN_FFA1R_FFA11_Pos    (11U)                                           
+#define CAN_FFA1R_FFA11_Msk    (0x1UL << CAN_FFA1R_FFA11_Pos)                   /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11        CAN_FFA1R_FFA11_Msk                             /*!<Filter FIFO Assignment bit 11 */
+#define CAN_FFA1R_FFA12_Pos    (12U)                                           
+#define CAN_FFA1R_FFA12_Msk    (0x1UL << CAN_FFA1R_FFA12_Pos)                   /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12        CAN_FFA1R_FFA12_Msk                             /*!<Filter FIFO Assignment bit 12 */
+#define CAN_FFA1R_FFA13_Pos    (13U)                                           
+#define CAN_FFA1R_FFA13_Msk    (0x1UL << CAN_FFA1R_FFA13_Pos)                   /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13        CAN_FFA1R_FFA13_Msk                             /*!<Filter FIFO Assignment bit 13 */
+#define CAN_FFA1R_FFA14_Pos    (14U)                                           
+#define CAN_FFA1R_FFA14_Msk    (0x1UL << CAN_FFA1R_FFA14_Pos)                   /*!< 0x00004000 */
+#define CAN_FFA1R_FFA14        CAN_FFA1R_FFA14_Msk                             /*!<Filter FIFO Assignment bit 14 */
+#define CAN_FFA1R_FFA15_Pos    (15U)                                           
+#define CAN_FFA1R_FFA15_Msk    (0x1UL << CAN_FFA1R_FFA15_Pos)                   /*!< 0x00008000 */
+#define CAN_FFA1R_FFA15        CAN_FFA1R_FFA15_Msk                             /*!<Filter FIFO Assignment bit 15 */
+#define CAN_FFA1R_FFA16_Pos    (16U)                                           
+#define CAN_FFA1R_FFA16_Msk    (0x1UL << CAN_FFA1R_FFA16_Pos)                   /*!< 0x00010000 */
+#define CAN_FFA1R_FFA16        CAN_FFA1R_FFA16_Msk                             /*!<Filter FIFO Assignment bit 16 */
+#define CAN_FFA1R_FFA17_Pos    (17U)                                           
+#define CAN_FFA1R_FFA17_Msk    (0x1UL << CAN_FFA1R_FFA17_Pos)                   /*!< 0x00020000 */
+#define CAN_FFA1R_FFA17        CAN_FFA1R_FFA17_Msk                             /*!<Filter FIFO Assignment bit 17 */
+#define CAN_FFA1R_FFA18_Pos    (18U)                                           
+#define CAN_FFA1R_FFA18_Msk    (0x1UL << CAN_FFA1R_FFA18_Pos)                   /*!< 0x00040000 */
+#define CAN_FFA1R_FFA18        CAN_FFA1R_FFA18_Msk                             /*!<Filter FIFO Assignment bit 18 */
+#define CAN_FFA1R_FFA19_Pos    (19U)                                           
+#define CAN_FFA1R_FFA19_Msk    (0x1UL << CAN_FFA1R_FFA19_Pos)                   /*!< 0x00080000 */
+#define CAN_FFA1R_FFA19        CAN_FFA1R_FFA19_Msk                             /*!<Filter FIFO Assignment bit 19 */
+#define CAN_FFA1R_FFA20_Pos    (20U)                                           
+#define CAN_FFA1R_FFA20_Msk    (0x1UL << CAN_FFA1R_FFA20_Pos)                   /*!< 0x00100000 */
+#define CAN_FFA1R_FFA20        CAN_FFA1R_FFA20_Msk                             /*!<Filter FIFO Assignment bit 20 */
+#define CAN_FFA1R_FFA21_Pos    (21U)                                           
+#define CAN_FFA1R_FFA21_Msk    (0x1UL << CAN_FFA1R_FFA21_Pos)                   /*!< 0x00200000 */
+#define CAN_FFA1R_FFA21        CAN_FFA1R_FFA21_Msk                             /*!<Filter FIFO Assignment bit 21 */
+#define CAN_FFA1R_FFA22_Pos    (22U)                                           
+#define CAN_FFA1R_FFA22_Msk    (0x1UL << CAN_FFA1R_FFA22_Pos)                   /*!< 0x00400000 */
+#define CAN_FFA1R_FFA22        CAN_FFA1R_FFA22_Msk                             /*!<Filter FIFO Assignment bit 22 */
+#define CAN_FFA1R_FFA23_Pos    (23U)                                           
+#define CAN_FFA1R_FFA23_Msk    (0x1UL << CAN_FFA1R_FFA23_Pos)                   /*!< 0x00800000 */
+#define CAN_FFA1R_FFA23        CAN_FFA1R_FFA23_Msk                             /*!<Filter FIFO Assignment bit 23 */
+#define CAN_FFA1R_FFA24_Pos    (24U)                                           
+#define CAN_FFA1R_FFA24_Msk    (0x1UL << CAN_FFA1R_FFA24_Pos)                   /*!< 0x01000000 */
+#define CAN_FFA1R_FFA24        CAN_FFA1R_FFA24_Msk                             /*!<Filter FIFO Assignment bit 24 */
+#define CAN_FFA1R_FFA25_Pos    (25U)                                           
+#define CAN_FFA1R_FFA25_Msk    (0x1UL << CAN_FFA1R_FFA25_Pos)                   /*!< 0x02000000 */
+#define CAN_FFA1R_FFA25        CAN_FFA1R_FFA25_Msk                             /*!<Filter FIFO Assignment bit 25 */
+#define CAN_FFA1R_FFA26_Pos    (26U)                                           
+#define CAN_FFA1R_FFA26_Msk    (0x1UL << CAN_FFA1R_FFA26_Pos)                   /*!< 0x04000000 */
+#define CAN_FFA1R_FFA26        CAN_FFA1R_FFA26_Msk                             /*!<Filter FIFO Assignment bit 26 */
+#define CAN_FFA1R_FFA27_Pos    (27U)                                           
+#define CAN_FFA1R_FFA27_Msk    (0x1UL << CAN_FFA1R_FFA27_Pos)                   /*!< 0x08000000 */
+#define CAN_FFA1R_FFA27        CAN_FFA1R_FFA27_Msk                             /*!<Filter FIFO Assignment bit 27 */
+
+/*******************  Bit definition for CAN_FA1R register  *******************/
+#define CAN_FA1R_FACT_Pos      (0U)                                            
+#define CAN_FA1R_FACT_Msk      (0xFFFFFFFUL << CAN_FA1R_FACT_Pos)               /*!< 0x0FFFFFFF */
+#define CAN_FA1R_FACT          CAN_FA1R_FACT_Msk                               /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos     (0U)                                            
+#define CAN_FA1R_FACT0_Msk     (0x1UL << CAN_FA1R_FACT0_Pos)                    /*!< 0x00000001 */
+#define CAN_FA1R_FACT0         CAN_FA1R_FACT0_Msk                              /*!<Filter Active bit 0 */
+#define CAN_FA1R_FACT1_Pos     (1U)                                            
+#define CAN_FA1R_FACT1_Msk     (0x1UL << CAN_FA1R_FACT1_Pos)                    /*!< 0x00000002 */
+#define CAN_FA1R_FACT1         CAN_FA1R_FACT1_Msk                              /*!<Filter Active bit 1 */
+#define CAN_FA1R_FACT2_Pos     (2U)                                            
+#define CAN_FA1R_FACT2_Msk     (0x1UL << CAN_FA1R_FACT2_Pos)                    /*!< 0x00000004 */
+#define CAN_FA1R_FACT2         CAN_FA1R_FACT2_Msk                              /*!<Filter Active bit 2 */
+#define CAN_FA1R_FACT3_Pos     (3U)                                            
+#define CAN_FA1R_FACT3_Msk     (0x1UL << CAN_FA1R_FACT3_Pos)                    /*!< 0x00000008 */
+#define CAN_FA1R_FACT3         CAN_FA1R_FACT3_Msk                              /*!<Filter Active bit 3 */
+#define CAN_FA1R_FACT4_Pos     (4U)                                            
+#define CAN_FA1R_FACT4_Msk     (0x1UL << CAN_FA1R_FACT4_Pos)                    /*!< 0x00000010 */
+#define CAN_FA1R_FACT4         CAN_FA1R_FACT4_Msk                              /*!<Filter Active bit 4 */
+#define CAN_FA1R_FACT5_Pos     (5U)                                            
+#define CAN_FA1R_FACT5_Msk     (0x1UL << CAN_FA1R_FACT5_Pos)                    /*!< 0x00000020 */
+#define CAN_FA1R_FACT5         CAN_FA1R_FACT5_Msk                              /*!<Filter Active bit 5 */
+#define CAN_FA1R_FACT6_Pos     (6U)                                            
+#define CAN_FA1R_FACT6_Msk     (0x1UL << CAN_FA1R_FACT6_Pos)                    /*!< 0x00000040 */
+#define CAN_FA1R_FACT6         CAN_FA1R_FACT6_Msk                              /*!<Filter Active bit 6 */
+#define CAN_FA1R_FACT7_Pos     (7U)                                            
+#define CAN_FA1R_FACT7_Msk     (0x1UL << CAN_FA1R_FACT7_Pos)                    /*!< 0x00000080 */
+#define CAN_FA1R_FACT7         CAN_FA1R_FACT7_Msk                              /*!<Filter Active bit 7 */
+#define CAN_FA1R_FACT8_Pos     (8U)                                            
+#define CAN_FA1R_FACT8_Msk     (0x1UL << CAN_FA1R_FACT8_Pos)                    /*!< 0x00000100 */
+#define CAN_FA1R_FACT8         CAN_FA1R_FACT8_Msk                              /*!<Filter Active bit 8 */
+#define CAN_FA1R_FACT9_Pos     (9U)                                            
+#define CAN_FA1R_FACT9_Msk     (0x1UL << CAN_FA1R_FACT9_Pos)                    /*!< 0x00000200 */
+#define CAN_FA1R_FACT9         CAN_FA1R_FACT9_Msk                              /*!<Filter Active bit 9 */
+#define CAN_FA1R_FACT10_Pos    (10U)                                           
+#define CAN_FA1R_FACT10_Msk    (0x1UL << CAN_FA1R_FACT10_Pos)                   /*!< 0x00000400 */
+#define CAN_FA1R_FACT10        CAN_FA1R_FACT10_Msk                             /*!<Filter Active bit 10 */
+#define CAN_FA1R_FACT11_Pos    (11U)                                           
+#define CAN_FA1R_FACT11_Msk    (0x1UL << CAN_FA1R_FACT11_Pos)                   /*!< 0x00000800 */
+#define CAN_FA1R_FACT11        CAN_FA1R_FACT11_Msk                             /*!<Filter Active bit 11 */
+#define CAN_FA1R_FACT12_Pos    (12U)                                           
+#define CAN_FA1R_FACT12_Msk    (0x1UL << CAN_FA1R_FACT12_Pos)                   /*!< 0x00001000 */
+#define CAN_FA1R_FACT12        CAN_FA1R_FACT12_Msk                             /*!<Filter Active bit 12 */
+#define CAN_FA1R_FACT13_Pos    (13U)                                           
+#define CAN_FA1R_FACT13_Msk    (0x1UL << CAN_FA1R_FACT13_Pos)                   /*!< 0x00002000 */
+#define CAN_FA1R_FACT13        CAN_FA1R_FACT13_Msk                             /*!<Filter Active bit 13 */
+#define CAN_FA1R_FACT14_Pos    (14U)                                           
+#define CAN_FA1R_FACT14_Msk    (0x1UL << CAN_FA1R_FACT14_Pos)                   /*!< 0x00004000 */
+#define CAN_FA1R_FACT14        CAN_FA1R_FACT14_Msk                             /*!<Filter Active bit 14 */
+#define CAN_FA1R_FACT15_Pos    (15U)                                           
+#define CAN_FA1R_FACT15_Msk    (0x1UL << CAN_FA1R_FACT15_Pos)                   /*!< 0x00008000 */
+#define CAN_FA1R_FACT15        CAN_FA1R_FACT15_Msk                             /*!<Filter Active bit 15 */
+#define CAN_FA1R_FACT16_Pos    (16U)                                           
+#define CAN_FA1R_FACT16_Msk    (0x1UL << CAN_FA1R_FACT16_Pos)                   /*!< 0x00010000 */
+#define CAN_FA1R_FACT16        CAN_FA1R_FACT16_Msk                             /*!<Filter Active bit 16 */
+#define CAN_FA1R_FACT17_Pos    (17U)                                           
+#define CAN_FA1R_FACT17_Msk    (0x1UL << CAN_FA1R_FACT17_Pos)                   /*!< 0x00020000 */
+#define CAN_FA1R_FACT17        CAN_FA1R_FACT17_Msk                             /*!<Filter Active bit 17 */
+#define CAN_FA1R_FACT18_Pos    (18U)                                           
+#define CAN_FA1R_FACT18_Msk    (0x1UL << CAN_FA1R_FACT18_Pos)                   /*!< 0x00040000 */
+#define CAN_FA1R_FACT18        CAN_FA1R_FACT18_Msk                             /*!<Filter Active bit 18 */
+#define CAN_FA1R_FACT19_Pos    (19U)                                           
+#define CAN_FA1R_FACT19_Msk    (0x1UL << CAN_FA1R_FACT19_Pos)                   /*!< 0x00080000 */
+#define CAN_FA1R_FACT19        CAN_FA1R_FACT19_Msk                             /*!<Filter Active bit 19 */
+#define CAN_FA1R_FACT20_Pos    (20U)                                           
+#define CAN_FA1R_FACT20_Msk    (0x1UL << CAN_FA1R_FACT20_Pos)                   /*!< 0x00100000 */
+#define CAN_FA1R_FACT20        CAN_FA1R_FACT20_Msk                             /*!<Filter Active bit 20 */
+#define CAN_FA1R_FACT21_Pos    (21U)                                           
+#define CAN_FA1R_FACT21_Msk    (0x1UL << CAN_FA1R_FACT21_Pos)                   /*!< 0x00200000 */
+#define CAN_FA1R_FACT21        CAN_FA1R_FACT21_Msk                             /*!<Filter Active bit 21 */
+#define CAN_FA1R_FACT22_Pos    (22U)                                           
+#define CAN_FA1R_FACT22_Msk    (0x1UL << CAN_FA1R_FACT22_Pos)                   /*!< 0x00400000 */
+#define CAN_FA1R_FACT22        CAN_FA1R_FACT22_Msk                             /*!<Filter Active bit 22 */
+#define CAN_FA1R_FACT23_Pos    (23U)                                           
+#define CAN_FA1R_FACT23_Msk    (0x1UL << CAN_FA1R_FACT23_Pos)                   /*!< 0x00800000 */
+#define CAN_FA1R_FACT23        CAN_FA1R_FACT23_Msk                             /*!<Filter Active bit 23 */
+#define CAN_FA1R_FACT24_Pos    (24U)                                           
+#define CAN_FA1R_FACT24_Msk    (0x1UL << CAN_FA1R_FACT24_Pos)                   /*!< 0x01000000 */
+#define CAN_FA1R_FACT24        CAN_FA1R_FACT24_Msk                             /*!<Filter Active bit 24 */
+#define CAN_FA1R_FACT25_Pos    (25U)                                           
+#define CAN_FA1R_FACT25_Msk    (0x1UL << CAN_FA1R_FACT25_Pos)                   /*!< 0x02000000 */
+#define CAN_FA1R_FACT25        CAN_FA1R_FACT25_Msk                             /*!<Filter Active bit 25 */
+#define CAN_FA1R_FACT26_Pos    (26U)                                           
+#define CAN_FA1R_FACT26_Msk    (0x1UL << CAN_FA1R_FACT26_Pos)                   /*!< 0x04000000 */
+#define CAN_FA1R_FACT26        CAN_FA1R_FACT26_Msk                             /*!<Filter Active bit 26 */
+#define CAN_FA1R_FACT27_Pos    (27U)                                           
+#define CAN_FA1R_FACT27_Msk    (0x1UL << CAN_FA1R_FACT27_Pos)                   /*!< 0x08000000 */
+#define CAN_FA1R_FACT27        CAN_FA1R_FACT27_Msk                             /*!<Filter Active bit 27 */
+
+
+/*******************  Bit definition for CAN_F0R1 register  *******************/
+#define CAN_F0R1_FB0_Pos       (0U)                                            
+#define CAN_F0R1_FB0_Msk       (0x1UL << CAN_F0R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R1_FB0           CAN_F0R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos       (1U)                                            
+#define CAN_F0R1_FB1_Msk       (0x1UL << CAN_F0R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R1_FB1           CAN_F0R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos       (2U)                                            
+#define CAN_F0R1_FB2_Msk       (0x1UL << CAN_F0R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R1_FB2           CAN_F0R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos       (3U)                                            
+#define CAN_F0R1_FB3_Msk       (0x1UL << CAN_F0R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R1_FB3           CAN_F0R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos       (4U)                                            
+#define CAN_F0R1_FB4_Msk       (0x1UL << CAN_F0R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R1_FB4           CAN_F0R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos       (5U)                                            
+#define CAN_F0R1_FB5_Msk       (0x1UL << CAN_F0R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R1_FB5           CAN_F0R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos       (6U)                                            
+#define CAN_F0R1_FB6_Msk       (0x1UL << CAN_F0R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R1_FB6           CAN_F0R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos       (7U)                                            
+#define CAN_F0R1_FB7_Msk       (0x1UL << CAN_F0R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R1_FB7           CAN_F0R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos       (8U)                                            
+#define CAN_F0R1_FB8_Msk       (0x1UL << CAN_F0R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R1_FB8           CAN_F0R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos       (9U)                                            
+#define CAN_F0R1_FB9_Msk       (0x1UL << CAN_F0R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R1_FB9           CAN_F0R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos      (10U)                                           
+#define CAN_F0R1_FB10_Msk      (0x1UL << CAN_F0R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R1_FB10          CAN_F0R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos      (11U)                                           
+#define CAN_F0R1_FB11_Msk      (0x1UL << CAN_F0R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R1_FB11          CAN_F0R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos      (12U)                                           
+#define CAN_F0R1_FB12_Msk      (0x1UL << CAN_F0R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R1_FB12          CAN_F0R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos      (13U)                                           
+#define CAN_F0R1_FB13_Msk      (0x1UL << CAN_F0R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R1_FB13          CAN_F0R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos      (14U)                                           
+#define CAN_F0R1_FB14_Msk      (0x1UL << CAN_F0R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R1_FB14          CAN_F0R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos      (15U)                                           
+#define CAN_F0R1_FB15_Msk      (0x1UL << CAN_F0R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R1_FB15          CAN_F0R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos      (16U)                                           
+#define CAN_F0R1_FB16_Msk      (0x1UL << CAN_F0R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R1_FB16          CAN_F0R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos      (17U)                                           
+#define CAN_F0R1_FB17_Msk      (0x1UL << CAN_F0R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R1_FB17          CAN_F0R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos      (18U)                                           
+#define CAN_F0R1_FB18_Msk      (0x1UL << CAN_F0R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R1_FB18          CAN_F0R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos      (19U)                                           
+#define CAN_F0R1_FB19_Msk      (0x1UL << CAN_F0R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R1_FB19          CAN_F0R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos      (20U)                                           
+#define CAN_F0R1_FB20_Msk      (0x1UL << CAN_F0R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R1_FB20          CAN_F0R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos      (21U)                                           
+#define CAN_F0R1_FB21_Msk      (0x1UL << CAN_F0R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R1_FB21          CAN_F0R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos      (22U)                                           
+#define CAN_F0R1_FB22_Msk      (0x1UL << CAN_F0R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R1_FB22          CAN_F0R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos      (23U)                                           
+#define CAN_F0R1_FB23_Msk      (0x1UL << CAN_F0R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R1_FB23          CAN_F0R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos      (24U)                                           
+#define CAN_F0R1_FB24_Msk      (0x1UL << CAN_F0R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R1_FB24          CAN_F0R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos      (25U)                                           
+#define CAN_F0R1_FB25_Msk      (0x1UL << CAN_F0R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R1_FB25          CAN_F0R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos      (26U)                                           
+#define CAN_F0R1_FB26_Msk      (0x1UL << CAN_F0R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R1_FB26          CAN_F0R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos      (27U)                                           
+#define CAN_F0R1_FB27_Msk      (0x1UL << CAN_F0R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R1_FB27          CAN_F0R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos      (28U)                                           
+#define CAN_F0R1_FB28_Msk      (0x1UL << CAN_F0R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R1_FB28          CAN_F0R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos      (29U)                                           
+#define CAN_F0R1_FB29_Msk      (0x1UL << CAN_F0R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R1_FB29          CAN_F0R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos      (30U)                                           
+#define CAN_F0R1_FB30_Msk      (0x1UL << CAN_F0R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R1_FB30          CAN_F0R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos      (31U)                                           
+#define CAN_F0R1_FB31_Msk      (0x1UL << CAN_F0R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R1_FB31          CAN_F0R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R1 register  *******************/
+#define CAN_F1R1_FB0_Pos       (0U)                                            
+#define CAN_F1R1_FB0_Msk       (0x1UL << CAN_F1R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R1_FB0           CAN_F1R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos       (1U)                                            
+#define CAN_F1R1_FB1_Msk       (0x1UL << CAN_F1R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R1_FB1           CAN_F1R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos       (2U)                                            
+#define CAN_F1R1_FB2_Msk       (0x1UL << CAN_F1R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R1_FB2           CAN_F1R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos       (3U)                                            
+#define CAN_F1R1_FB3_Msk       (0x1UL << CAN_F1R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R1_FB3           CAN_F1R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos       (4U)                                            
+#define CAN_F1R1_FB4_Msk       (0x1UL << CAN_F1R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R1_FB4           CAN_F1R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos       (5U)                                            
+#define CAN_F1R1_FB5_Msk       (0x1UL << CAN_F1R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R1_FB5           CAN_F1R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos       (6U)                                            
+#define CAN_F1R1_FB6_Msk       (0x1UL << CAN_F1R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R1_FB6           CAN_F1R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos       (7U)                                            
+#define CAN_F1R1_FB7_Msk       (0x1UL << CAN_F1R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R1_FB7           CAN_F1R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos       (8U)                                            
+#define CAN_F1R1_FB8_Msk       (0x1UL << CAN_F1R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R1_FB8           CAN_F1R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos       (9U)                                            
+#define CAN_F1R1_FB9_Msk       (0x1UL << CAN_F1R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R1_FB9           CAN_F1R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos      (10U)                                           
+#define CAN_F1R1_FB10_Msk      (0x1UL << CAN_F1R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R1_FB10          CAN_F1R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos      (11U)                                           
+#define CAN_F1R1_FB11_Msk      (0x1UL << CAN_F1R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R1_FB11          CAN_F1R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos      (12U)                                           
+#define CAN_F1R1_FB12_Msk      (0x1UL << CAN_F1R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R1_FB12          CAN_F1R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos      (13U)                                           
+#define CAN_F1R1_FB13_Msk      (0x1UL << CAN_F1R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R1_FB13          CAN_F1R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos      (14U)                                           
+#define CAN_F1R1_FB14_Msk      (0x1UL << CAN_F1R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R1_FB14          CAN_F1R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos      (15U)                                           
+#define CAN_F1R1_FB15_Msk      (0x1UL << CAN_F1R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R1_FB15          CAN_F1R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos      (16U)                                           
+#define CAN_F1R1_FB16_Msk      (0x1UL << CAN_F1R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R1_FB16          CAN_F1R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos      (17U)                                           
+#define CAN_F1R1_FB17_Msk      (0x1UL << CAN_F1R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R1_FB17          CAN_F1R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos      (18U)                                           
+#define CAN_F1R1_FB18_Msk      (0x1UL << CAN_F1R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R1_FB18          CAN_F1R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos      (19U)                                           
+#define CAN_F1R1_FB19_Msk      (0x1UL << CAN_F1R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R1_FB19          CAN_F1R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos      (20U)                                           
+#define CAN_F1R1_FB20_Msk      (0x1UL << CAN_F1R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R1_FB20          CAN_F1R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos      (21U)                                           
+#define CAN_F1R1_FB21_Msk      (0x1UL << CAN_F1R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R1_FB21          CAN_F1R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos      (22U)                                           
+#define CAN_F1R1_FB22_Msk      (0x1UL << CAN_F1R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R1_FB22          CAN_F1R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos      (23U)                                           
+#define CAN_F1R1_FB23_Msk      (0x1UL << CAN_F1R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R1_FB23          CAN_F1R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos      (24U)                                           
+#define CAN_F1R1_FB24_Msk      (0x1UL << CAN_F1R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R1_FB24          CAN_F1R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos      (25U)                                           
+#define CAN_F1R1_FB25_Msk      (0x1UL << CAN_F1R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R1_FB25          CAN_F1R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos      (26U)                                           
+#define CAN_F1R1_FB26_Msk      (0x1UL << CAN_F1R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R1_FB26          CAN_F1R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos      (27U)                                           
+#define CAN_F1R1_FB27_Msk      (0x1UL << CAN_F1R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R1_FB27          CAN_F1R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos      (28U)                                           
+#define CAN_F1R1_FB28_Msk      (0x1UL << CAN_F1R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R1_FB28          CAN_F1R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos      (29U)                                           
+#define CAN_F1R1_FB29_Msk      (0x1UL << CAN_F1R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R1_FB29          CAN_F1R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos      (30U)                                           
+#define CAN_F1R1_FB30_Msk      (0x1UL << CAN_F1R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R1_FB30          CAN_F1R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos      (31U)                                           
+#define CAN_F1R1_FB31_Msk      (0x1UL << CAN_F1R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R1_FB31          CAN_F1R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R1 register  *******************/
+#define CAN_F2R1_FB0_Pos       (0U)                                            
+#define CAN_F2R1_FB0_Msk       (0x1UL << CAN_F2R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R1_FB0           CAN_F2R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos       (1U)                                            
+#define CAN_F2R1_FB1_Msk       (0x1UL << CAN_F2R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R1_FB1           CAN_F2R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos       (2U)                                            
+#define CAN_F2R1_FB2_Msk       (0x1UL << CAN_F2R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R1_FB2           CAN_F2R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos       (3U)                                            
+#define CAN_F2R1_FB3_Msk       (0x1UL << CAN_F2R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R1_FB3           CAN_F2R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos       (4U)                                            
+#define CAN_F2R1_FB4_Msk       (0x1UL << CAN_F2R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R1_FB4           CAN_F2R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos       (5U)                                            
+#define CAN_F2R1_FB5_Msk       (0x1UL << CAN_F2R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R1_FB5           CAN_F2R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos       (6U)                                            
+#define CAN_F2R1_FB6_Msk       (0x1UL << CAN_F2R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R1_FB6           CAN_F2R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos       (7U)                                            
+#define CAN_F2R1_FB7_Msk       (0x1UL << CAN_F2R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R1_FB7           CAN_F2R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos       (8U)                                            
+#define CAN_F2R1_FB8_Msk       (0x1UL << CAN_F2R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R1_FB8           CAN_F2R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos       (9U)                                            
+#define CAN_F2R1_FB9_Msk       (0x1UL << CAN_F2R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R1_FB9           CAN_F2R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos      (10U)                                           
+#define CAN_F2R1_FB10_Msk      (0x1UL << CAN_F2R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R1_FB10          CAN_F2R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos      (11U)                                           
+#define CAN_F2R1_FB11_Msk      (0x1UL << CAN_F2R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R1_FB11          CAN_F2R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos      (12U)                                           
+#define CAN_F2R1_FB12_Msk      (0x1UL << CAN_F2R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R1_FB12          CAN_F2R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos      (13U)                                           
+#define CAN_F2R1_FB13_Msk      (0x1UL << CAN_F2R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R1_FB13          CAN_F2R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos      (14U)                                           
+#define CAN_F2R1_FB14_Msk      (0x1UL << CAN_F2R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R1_FB14          CAN_F2R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos      (15U)                                           
+#define CAN_F2R1_FB15_Msk      (0x1UL << CAN_F2R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R1_FB15          CAN_F2R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos      (16U)                                           
+#define CAN_F2R1_FB16_Msk      (0x1UL << CAN_F2R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R1_FB16          CAN_F2R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos      (17U)                                           
+#define CAN_F2R1_FB17_Msk      (0x1UL << CAN_F2R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R1_FB17          CAN_F2R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos      (18U)                                           
+#define CAN_F2R1_FB18_Msk      (0x1UL << CAN_F2R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R1_FB18          CAN_F2R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos      (19U)                                           
+#define CAN_F2R1_FB19_Msk      (0x1UL << CAN_F2R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R1_FB19          CAN_F2R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos      (20U)                                           
+#define CAN_F2R1_FB20_Msk      (0x1UL << CAN_F2R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R1_FB20          CAN_F2R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos      (21U)                                           
+#define CAN_F2R1_FB21_Msk      (0x1UL << CAN_F2R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R1_FB21          CAN_F2R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos      (22U)                                           
+#define CAN_F2R1_FB22_Msk      (0x1UL << CAN_F2R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R1_FB22          CAN_F2R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos      (23U)                                           
+#define CAN_F2R1_FB23_Msk      (0x1UL << CAN_F2R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R1_FB23          CAN_F2R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos      (24U)                                           
+#define CAN_F2R1_FB24_Msk      (0x1UL << CAN_F2R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R1_FB24          CAN_F2R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos      (25U)                                           
+#define CAN_F2R1_FB25_Msk      (0x1UL << CAN_F2R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R1_FB25          CAN_F2R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos      (26U)                                           
+#define CAN_F2R1_FB26_Msk      (0x1UL << CAN_F2R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R1_FB26          CAN_F2R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos      (27U)                                           
+#define CAN_F2R1_FB27_Msk      (0x1UL << CAN_F2R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R1_FB27          CAN_F2R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos      (28U)                                           
+#define CAN_F2R1_FB28_Msk      (0x1UL << CAN_F2R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R1_FB28          CAN_F2R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos      (29U)                                           
+#define CAN_F2R1_FB29_Msk      (0x1UL << CAN_F2R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R1_FB29          CAN_F2R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos      (30U)                                           
+#define CAN_F2R1_FB30_Msk      (0x1UL << CAN_F2R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R1_FB30          CAN_F2R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos      (31U)                                           
+#define CAN_F2R1_FB31_Msk      (0x1UL << CAN_F2R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R1_FB31          CAN_F2R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R1 register  *******************/
+#define CAN_F3R1_FB0_Pos       (0U)                                            
+#define CAN_F3R1_FB0_Msk       (0x1UL << CAN_F3R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R1_FB0           CAN_F3R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos       (1U)                                            
+#define CAN_F3R1_FB1_Msk       (0x1UL << CAN_F3R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R1_FB1           CAN_F3R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos       (2U)                                            
+#define CAN_F3R1_FB2_Msk       (0x1UL << CAN_F3R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R1_FB2           CAN_F3R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos       (3U)                                            
+#define CAN_F3R1_FB3_Msk       (0x1UL << CAN_F3R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R1_FB3           CAN_F3R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos       (4U)                                            
+#define CAN_F3R1_FB4_Msk       (0x1UL << CAN_F3R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R1_FB4           CAN_F3R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos       (5U)                                            
+#define CAN_F3R1_FB5_Msk       (0x1UL << CAN_F3R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R1_FB5           CAN_F3R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos       (6U)                                            
+#define CAN_F3R1_FB6_Msk       (0x1UL << CAN_F3R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R1_FB6           CAN_F3R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos       (7U)                                            
+#define CAN_F3R1_FB7_Msk       (0x1UL << CAN_F3R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R1_FB7           CAN_F3R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos       (8U)                                            
+#define CAN_F3R1_FB8_Msk       (0x1UL << CAN_F3R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R1_FB8           CAN_F3R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos       (9U)                                            
+#define CAN_F3R1_FB9_Msk       (0x1UL << CAN_F3R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R1_FB9           CAN_F3R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos      (10U)                                           
+#define CAN_F3R1_FB10_Msk      (0x1UL << CAN_F3R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R1_FB10          CAN_F3R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos      (11U)                                           
+#define CAN_F3R1_FB11_Msk      (0x1UL << CAN_F3R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R1_FB11          CAN_F3R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos      (12U)                                           
+#define CAN_F3R1_FB12_Msk      (0x1UL << CAN_F3R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R1_FB12          CAN_F3R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos      (13U)                                           
+#define CAN_F3R1_FB13_Msk      (0x1UL << CAN_F3R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R1_FB13          CAN_F3R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos      (14U)                                           
+#define CAN_F3R1_FB14_Msk      (0x1UL << CAN_F3R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R1_FB14          CAN_F3R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos      (15U)                                           
+#define CAN_F3R1_FB15_Msk      (0x1UL << CAN_F3R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R1_FB15          CAN_F3R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos      (16U)                                           
+#define CAN_F3R1_FB16_Msk      (0x1UL << CAN_F3R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R1_FB16          CAN_F3R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos      (17U)                                           
+#define CAN_F3R1_FB17_Msk      (0x1UL << CAN_F3R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R1_FB17          CAN_F3R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos      (18U)                                           
+#define CAN_F3R1_FB18_Msk      (0x1UL << CAN_F3R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R1_FB18          CAN_F3R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos      (19U)                                           
+#define CAN_F3R1_FB19_Msk      (0x1UL << CAN_F3R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R1_FB19          CAN_F3R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos      (20U)                                           
+#define CAN_F3R1_FB20_Msk      (0x1UL << CAN_F3R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R1_FB20          CAN_F3R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos      (21U)                                           
+#define CAN_F3R1_FB21_Msk      (0x1UL << CAN_F3R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R1_FB21          CAN_F3R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos      (22U)                                           
+#define CAN_F3R1_FB22_Msk      (0x1UL << CAN_F3R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R1_FB22          CAN_F3R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos      (23U)                                           
+#define CAN_F3R1_FB23_Msk      (0x1UL << CAN_F3R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R1_FB23          CAN_F3R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos      (24U)                                           
+#define CAN_F3R1_FB24_Msk      (0x1UL << CAN_F3R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R1_FB24          CAN_F3R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos      (25U)                                           
+#define CAN_F3R1_FB25_Msk      (0x1UL << CAN_F3R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R1_FB25          CAN_F3R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos      (26U)                                           
+#define CAN_F3R1_FB26_Msk      (0x1UL << CAN_F3R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R1_FB26          CAN_F3R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos      (27U)                                           
+#define CAN_F3R1_FB27_Msk      (0x1UL << CAN_F3R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R1_FB27          CAN_F3R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos      (28U)                                           
+#define CAN_F3R1_FB28_Msk      (0x1UL << CAN_F3R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R1_FB28          CAN_F3R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos      (29U)                                           
+#define CAN_F3R1_FB29_Msk      (0x1UL << CAN_F3R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R1_FB29          CAN_F3R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos      (30U)                                           
+#define CAN_F3R1_FB30_Msk      (0x1UL << CAN_F3R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R1_FB30          CAN_F3R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos      (31U)                                           
+#define CAN_F3R1_FB31_Msk      (0x1UL << CAN_F3R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R1_FB31          CAN_F3R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R1 register  *******************/
+#define CAN_F4R1_FB0_Pos       (0U)                                            
+#define CAN_F4R1_FB0_Msk       (0x1UL << CAN_F4R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R1_FB0           CAN_F4R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos       (1U)                                            
+#define CAN_F4R1_FB1_Msk       (0x1UL << CAN_F4R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R1_FB1           CAN_F4R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos       (2U)                                            
+#define CAN_F4R1_FB2_Msk       (0x1UL << CAN_F4R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R1_FB2           CAN_F4R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos       (3U)                                            
+#define CAN_F4R1_FB3_Msk       (0x1UL << CAN_F4R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R1_FB3           CAN_F4R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos       (4U)                                            
+#define CAN_F4R1_FB4_Msk       (0x1UL << CAN_F4R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R1_FB4           CAN_F4R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos       (5U)                                            
+#define CAN_F4R1_FB5_Msk       (0x1UL << CAN_F4R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R1_FB5           CAN_F4R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos       (6U)                                            
+#define CAN_F4R1_FB6_Msk       (0x1UL << CAN_F4R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R1_FB6           CAN_F4R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos       (7U)                                            
+#define CAN_F4R1_FB7_Msk       (0x1UL << CAN_F4R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R1_FB7           CAN_F4R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos       (8U)                                            
+#define CAN_F4R1_FB8_Msk       (0x1UL << CAN_F4R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R1_FB8           CAN_F4R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos       (9U)                                            
+#define CAN_F4R1_FB9_Msk       (0x1UL << CAN_F4R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R1_FB9           CAN_F4R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos      (10U)                                           
+#define CAN_F4R1_FB10_Msk      (0x1UL << CAN_F4R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R1_FB10          CAN_F4R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos      (11U)                                           
+#define CAN_F4R1_FB11_Msk      (0x1UL << CAN_F4R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R1_FB11          CAN_F4R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos      (12U)                                           
+#define CAN_F4R1_FB12_Msk      (0x1UL << CAN_F4R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R1_FB12          CAN_F4R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos      (13U)                                           
+#define CAN_F4R1_FB13_Msk      (0x1UL << CAN_F4R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R1_FB13          CAN_F4R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos      (14U)                                           
+#define CAN_F4R1_FB14_Msk      (0x1UL << CAN_F4R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R1_FB14          CAN_F4R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos      (15U)                                           
+#define CAN_F4R1_FB15_Msk      (0x1UL << CAN_F4R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R1_FB15          CAN_F4R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos      (16U)                                           
+#define CAN_F4R1_FB16_Msk      (0x1UL << CAN_F4R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R1_FB16          CAN_F4R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos      (17U)                                           
+#define CAN_F4R1_FB17_Msk      (0x1UL << CAN_F4R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R1_FB17          CAN_F4R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos      (18U)                                           
+#define CAN_F4R1_FB18_Msk      (0x1UL << CAN_F4R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R1_FB18          CAN_F4R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos      (19U)                                           
+#define CAN_F4R1_FB19_Msk      (0x1UL << CAN_F4R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R1_FB19          CAN_F4R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos      (20U)                                           
+#define CAN_F4R1_FB20_Msk      (0x1UL << CAN_F4R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R1_FB20          CAN_F4R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos      (21U)                                           
+#define CAN_F4R1_FB21_Msk      (0x1UL << CAN_F4R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R1_FB21          CAN_F4R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos      (22U)                                           
+#define CAN_F4R1_FB22_Msk      (0x1UL << CAN_F4R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R1_FB22          CAN_F4R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos      (23U)                                           
+#define CAN_F4R1_FB23_Msk      (0x1UL << CAN_F4R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R1_FB23          CAN_F4R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos      (24U)                                           
+#define CAN_F4R1_FB24_Msk      (0x1UL << CAN_F4R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R1_FB24          CAN_F4R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos      (25U)                                           
+#define CAN_F4R1_FB25_Msk      (0x1UL << CAN_F4R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R1_FB25          CAN_F4R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos      (26U)                                           
+#define CAN_F4R1_FB26_Msk      (0x1UL << CAN_F4R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R1_FB26          CAN_F4R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos      (27U)                                           
+#define CAN_F4R1_FB27_Msk      (0x1UL << CAN_F4R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R1_FB27          CAN_F4R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos      (28U)                                           
+#define CAN_F4R1_FB28_Msk      (0x1UL << CAN_F4R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R1_FB28          CAN_F4R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos      (29U)                                           
+#define CAN_F4R1_FB29_Msk      (0x1UL << CAN_F4R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R1_FB29          CAN_F4R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos      (30U)                                           
+#define CAN_F4R1_FB30_Msk      (0x1UL << CAN_F4R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R1_FB30          CAN_F4R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos      (31U)                                           
+#define CAN_F4R1_FB31_Msk      (0x1UL << CAN_F4R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R1_FB31          CAN_F4R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R1 register  *******************/
+#define CAN_F5R1_FB0_Pos       (0U)                                            
+#define CAN_F5R1_FB0_Msk       (0x1UL << CAN_F5R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R1_FB0           CAN_F5R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos       (1U)                                            
+#define CAN_F5R1_FB1_Msk       (0x1UL << CAN_F5R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R1_FB1           CAN_F5R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos       (2U)                                            
+#define CAN_F5R1_FB2_Msk       (0x1UL << CAN_F5R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R1_FB2           CAN_F5R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos       (3U)                                            
+#define CAN_F5R1_FB3_Msk       (0x1UL << CAN_F5R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R1_FB3           CAN_F5R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos       (4U)                                            
+#define CAN_F5R1_FB4_Msk       (0x1UL << CAN_F5R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R1_FB4           CAN_F5R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos       (5U)                                            
+#define CAN_F5R1_FB5_Msk       (0x1UL << CAN_F5R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R1_FB5           CAN_F5R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos       (6U)                                            
+#define CAN_F5R1_FB6_Msk       (0x1UL << CAN_F5R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R1_FB6           CAN_F5R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos       (7U)                                            
+#define CAN_F5R1_FB7_Msk       (0x1UL << CAN_F5R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R1_FB7           CAN_F5R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos       (8U)                                            
+#define CAN_F5R1_FB8_Msk       (0x1UL << CAN_F5R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R1_FB8           CAN_F5R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos       (9U)                                            
+#define CAN_F5R1_FB9_Msk       (0x1UL << CAN_F5R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R1_FB9           CAN_F5R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos      (10U)                                           
+#define CAN_F5R1_FB10_Msk      (0x1UL << CAN_F5R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R1_FB10          CAN_F5R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos      (11U)                                           
+#define CAN_F5R1_FB11_Msk      (0x1UL << CAN_F5R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R1_FB11          CAN_F5R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos      (12U)                                           
+#define CAN_F5R1_FB12_Msk      (0x1UL << CAN_F5R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R1_FB12          CAN_F5R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos      (13U)                                           
+#define CAN_F5R1_FB13_Msk      (0x1UL << CAN_F5R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R1_FB13          CAN_F5R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos      (14U)                                           
+#define CAN_F5R1_FB14_Msk      (0x1UL << CAN_F5R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R1_FB14          CAN_F5R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos      (15U)                                           
+#define CAN_F5R1_FB15_Msk      (0x1UL << CAN_F5R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R1_FB15          CAN_F5R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos      (16U)                                           
+#define CAN_F5R1_FB16_Msk      (0x1UL << CAN_F5R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R1_FB16          CAN_F5R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos      (17U)                                           
+#define CAN_F5R1_FB17_Msk      (0x1UL << CAN_F5R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R1_FB17          CAN_F5R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos      (18U)                                           
+#define CAN_F5R1_FB18_Msk      (0x1UL << CAN_F5R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R1_FB18          CAN_F5R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos      (19U)                                           
+#define CAN_F5R1_FB19_Msk      (0x1UL << CAN_F5R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R1_FB19          CAN_F5R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos      (20U)                                           
+#define CAN_F5R1_FB20_Msk      (0x1UL << CAN_F5R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R1_FB20          CAN_F5R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos      (21U)                                           
+#define CAN_F5R1_FB21_Msk      (0x1UL << CAN_F5R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R1_FB21          CAN_F5R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos      (22U)                                           
+#define CAN_F5R1_FB22_Msk      (0x1UL << CAN_F5R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R1_FB22          CAN_F5R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos      (23U)                                           
+#define CAN_F5R1_FB23_Msk      (0x1UL << CAN_F5R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R1_FB23          CAN_F5R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos      (24U)                                           
+#define CAN_F5R1_FB24_Msk      (0x1UL << CAN_F5R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R1_FB24          CAN_F5R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos      (25U)                                           
+#define CAN_F5R1_FB25_Msk      (0x1UL << CAN_F5R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R1_FB25          CAN_F5R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos      (26U)                                           
+#define CAN_F5R1_FB26_Msk      (0x1UL << CAN_F5R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R1_FB26          CAN_F5R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos      (27U)                                           
+#define CAN_F5R1_FB27_Msk      (0x1UL << CAN_F5R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R1_FB27          CAN_F5R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos      (28U)                                           
+#define CAN_F5R1_FB28_Msk      (0x1UL << CAN_F5R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R1_FB28          CAN_F5R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos      (29U)                                           
+#define CAN_F5R1_FB29_Msk      (0x1UL << CAN_F5R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R1_FB29          CAN_F5R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos      (30U)                                           
+#define CAN_F5R1_FB30_Msk      (0x1UL << CAN_F5R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R1_FB30          CAN_F5R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos      (31U)                                           
+#define CAN_F5R1_FB31_Msk      (0x1UL << CAN_F5R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R1_FB31          CAN_F5R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R1 register  *******************/
+#define CAN_F6R1_FB0_Pos       (0U)                                            
+#define CAN_F6R1_FB0_Msk       (0x1UL << CAN_F6R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R1_FB0           CAN_F6R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos       (1U)                                            
+#define CAN_F6R1_FB1_Msk       (0x1UL << CAN_F6R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R1_FB1           CAN_F6R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos       (2U)                                            
+#define CAN_F6R1_FB2_Msk       (0x1UL << CAN_F6R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R1_FB2           CAN_F6R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos       (3U)                                            
+#define CAN_F6R1_FB3_Msk       (0x1UL << CAN_F6R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R1_FB3           CAN_F6R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos       (4U)                                            
+#define CAN_F6R1_FB4_Msk       (0x1UL << CAN_F6R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R1_FB4           CAN_F6R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos       (5U)                                            
+#define CAN_F6R1_FB5_Msk       (0x1UL << CAN_F6R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R1_FB5           CAN_F6R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos       (6U)                                            
+#define CAN_F6R1_FB6_Msk       (0x1UL << CAN_F6R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R1_FB6           CAN_F6R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos       (7U)                                            
+#define CAN_F6R1_FB7_Msk       (0x1UL << CAN_F6R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R1_FB7           CAN_F6R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos       (8U)                                            
+#define CAN_F6R1_FB8_Msk       (0x1UL << CAN_F6R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R1_FB8           CAN_F6R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos       (9U)                                            
+#define CAN_F6R1_FB9_Msk       (0x1UL << CAN_F6R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R1_FB9           CAN_F6R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos      (10U)                                           
+#define CAN_F6R1_FB10_Msk      (0x1UL << CAN_F6R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R1_FB10          CAN_F6R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos      (11U)                                           
+#define CAN_F6R1_FB11_Msk      (0x1UL << CAN_F6R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R1_FB11          CAN_F6R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos      (12U)                                           
+#define CAN_F6R1_FB12_Msk      (0x1UL << CAN_F6R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R1_FB12          CAN_F6R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos      (13U)                                           
+#define CAN_F6R1_FB13_Msk      (0x1UL << CAN_F6R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R1_FB13          CAN_F6R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos      (14U)                                           
+#define CAN_F6R1_FB14_Msk      (0x1UL << CAN_F6R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R1_FB14          CAN_F6R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos      (15U)                                           
+#define CAN_F6R1_FB15_Msk      (0x1UL << CAN_F6R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R1_FB15          CAN_F6R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos      (16U)                                           
+#define CAN_F6R1_FB16_Msk      (0x1UL << CAN_F6R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R1_FB16          CAN_F6R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos      (17U)                                           
+#define CAN_F6R1_FB17_Msk      (0x1UL << CAN_F6R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R1_FB17          CAN_F6R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos      (18U)                                           
+#define CAN_F6R1_FB18_Msk      (0x1UL << CAN_F6R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R1_FB18          CAN_F6R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos      (19U)                                           
+#define CAN_F6R1_FB19_Msk      (0x1UL << CAN_F6R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R1_FB19          CAN_F6R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos      (20U)                                           
+#define CAN_F6R1_FB20_Msk      (0x1UL << CAN_F6R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R1_FB20          CAN_F6R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos      (21U)                                           
+#define CAN_F6R1_FB21_Msk      (0x1UL << CAN_F6R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R1_FB21          CAN_F6R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos      (22U)                                           
+#define CAN_F6R1_FB22_Msk      (0x1UL << CAN_F6R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R1_FB22          CAN_F6R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos      (23U)                                           
+#define CAN_F6R1_FB23_Msk      (0x1UL << CAN_F6R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R1_FB23          CAN_F6R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos      (24U)                                           
+#define CAN_F6R1_FB24_Msk      (0x1UL << CAN_F6R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R1_FB24          CAN_F6R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos      (25U)                                           
+#define CAN_F6R1_FB25_Msk      (0x1UL << CAN_F6R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R1_FB25          CAN_F6R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos      (26U)                                           
+#define CAN_F6R1_FB26_Msk      (0x1UL << CAN_F6R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R1_FB26          CAN_F6R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos      (27U)                                           
+#define CAN_F6R1_FB27_Msk      (0x1UL << CAN_F6R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R1_FB27          CAN_F6R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos      (28U)                                           
+#define CAN_F6R1_FB28_Msk      (0x1UL << CAN_F6R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R1_FB28          CAN_F6R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos      (29U)                                           
+#define CAN_F6R1_FB29_Msk      (0x1UL << CAN_F6R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R1_FB29          CAN_F6R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos      (30U)                                           
+#define CAN_F6R1_FB30_Msk      (0x1UL << CAN_F6R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R1_FB30          CAN_F6R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos      (31U)                                           
+#define CAN_F6R1_FB31_Msk      (0x1UL << CAN_F6R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R1_FB31          CAN_F6R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R1 register  *******************/
+#define CAN_F7R1_FB0_Pos       (0U)                                            
+#define CAN_F7R1_FB0_Msk       (0x1UL << CAN_F7R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R1_FB0           CAN_F7R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos       (1U)                                            
+#define CAN_F7R1_FB1_Msk       (0x1UL << CAN_F7R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R1_FB1           CAN_F7R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos       (2U)                                            
+#define CAN_F7R1_FB2_Msk       (0x1UL << CAN_F7R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R1_FB2           CAN_F7R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos       (3U)                                            
+#define CAN_F7R1_FB3_Msk       (0x1UL << CAN_F7R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R1_FB3           CAN_F7R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos       (4U)                                            
+#define CAN_F7R1_FB4_Msk       (0x1UL << CAN_F7R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R1_FB4           CAN_F7R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos       (5U)                                            
+#define CAN_F7R1_FB5_Msk       (0x1UL << CAN_F7R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R1_FB5           CAN_F7R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos       (6U)                                            
+#define CAN_F7R1_FB6_Msk       (0x1UL << CAN_F7R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R1_FB6           CAN_F7R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos       (7U)                                            
+#define CAN_F7R1_FB7_Msk       (0x1UL << CAN_F7R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R1_FB7           CAN_F7R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos       (8U)                                            
+#define CAN_F7R1_FB8_Msk       (0x1UL << CAN_F7R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R1_FB8           CAN_F7R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos       (9U)                                            
+#define CAN_F7R1_FB9_Msk       (0x1UL << CAN_F7R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R1_FB9           CAN_F7R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos      (10U)                                           
+#define CAN_F7R1_FB10_Msk      (0x1UL << CAN_F7R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R1_FB10          CAN_F7R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos      (11U)                                           
+#define CAN_F7R1_FB11_Msk      (0x1UL << CAN_F7R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R1_FB11          CAN_F7R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos      (12U)                                           
+#define CAN_F7R1_FB12_Msk      (0x1UL << CAN_F7R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R1_FB12          CAN_F7R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos      (13U)                                           
+#define CAN_F7R1_FB13_Msk      (0x1UL << CAN_F7R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R1_FB13          CAN_F7R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos      (14U)                                           
+#define CAN_F7R1_FB14_Msk      (0x1UL << CAN_F7R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R1_FB14          CAN_F7R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos      (15U)                                           
+#define CAN_F7R1_FB15_Msk      (0x1UL << CAN_F7R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R1_FB15          CAN_F7R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos      (16U)                                           
+#define CAN_F7R1_FB16_Msk      (0x1UL << CAN_F7R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R1_FB16          CAN_F7R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos      (17U)                                           
+#define CAN_F7R1_FB17_Msk      (0x1UL << CAN_F7R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R1_FB17          CAN_F7R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos      (18U)                                           
+#define CAN_F7R1_FB18_Msk      (0x1UL << CAN_F7R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R1_FB18          CAN_F7R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos      (19U)                                           
+#define CAN_F7R1_FB19_Msk      (0x1UL << CAN_F7R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R1_FB19          CAN_F7R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos      (20U)                                           
+#define CAN_F7R1_FB20_Msk      (0x1UL << CAN_F7R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R1_FB20          CAN_F7R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos      (21U)                                           
+#define CAN_F7R1_FB21_Msk      (0x1UL << CAN_F7R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R1_FB21          CAN_F7R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos      (22U)                                           
+#define CAN_F7R1_FB22_Msk      (0x1UL << CAN_F7R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R1_FB22          CAN_F7R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos      (23U)                                           
+#define CAN_F7R1_FB23_Msk      (0x1UL << CAN_F7R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R1_FB23          CAN_F7R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos      (24U)                                           
+#define CAN_F7R1_FB24_Msk      (0x1UL << CAN_F7R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R1_FB24          CAN_F7R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos      (25U)                                           
+#define CAN_F7R1_FB25_Msk      (0x1UL << CAN_F7R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R1_FB25          CAN_F7R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos      (26U)                                           
+#define CAN_F7R1_FB26_Msk      (0x1UL << CAN_F7R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R1_FB26          CAN_F7R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos      (27U)                                           
+#define CAN_F7R1_FB27_Msk      (0x1UL << CAN_F7R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R1_FB27          CAN_F7R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos      (28U)                                           
+#define CAN_F7R1_FB28_Msk      (0x1UL << CAN_F7R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R1_FB28          CAN_F7R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos      (29U)                                           
+#define CAN_F7R1_FB29_Msk      (0x1UL << CAN_F7R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R1_FB29          CAN_F7R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos      (30U)                                           
+#define CAN_F7R1_FB30_Msk      (0x1UL << CAN_F7R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R1_FB30          CAN_F7R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos      (31U)                                           
+#define CAN_F7R1_FB31_Msk      (0x1UL << CAN_F7R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R1_FB31          CAN_F7R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R1 register  *******************/
+#define CAN_F8R1_FB0_Pos       (0U)                                            
+#define CAN_F8R1_FB0_Msk       (0x1UL << CAN_F8R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R1_FB0           CAN_F8R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos       (1U)                                            
+#define CAN_F8R1_FB1_Msk       (0x1UL << CAN_F8R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R1_FB1           CAN_F8R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos       (2U)                                            
+#define CAN_F8R1_FB2_Msk       (0x1UL << CAN_F8R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R1_FB2           CAN_F8R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos       (3U)                                            
+#define CAN_F8R1_FB3_Msk       (0x1UL << CAN_F8R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R1_FB3           CAN_F8R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos       (4U)                                            
+#define CAN_F8R1_FB4_Msk       (0x1UL << CAN_F8R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R1_FB4           CAN_F8R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos       (5U)                                            
+#define CAN_F8R1_FB5_Msk       (0x1UL << CAN_F8R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R1_FB5           CAN_F8R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos       (6U)                                            
+#define CAN_F8R1_FB6_Msk       (0x1UL << CAN_F8R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R1_FB6           CAN_F8R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos       (7U)                                            
+#define CAN_F8R1_FB7_Msk       (0x1UL << CAN_F8R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R1_FB7           CAN_F8R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos       (8U)                                            
+#define CAN_F8R1_FB8_Msk       (0x1UL << CAN_F8R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R1_FB8           CAN_F8R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos       (9U)                                            
+#define CAN_F8R1_FB9_Msk       (0x1UL << CAN_F8R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R1_FB9           CAN_F8R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos      (10U)                                           
+#define CAN_F8R1_FB10_Msk      (0x1UL << CAN_F8R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R1_FB10          CAN_F8R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos      (11U)                                           
+#define CAN_F8R1_FB11_Msk      (0x1UL << CAN_F8R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R1_FB11          CAN_F8R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos      (12U)                                           
+#define CAN_F8R1_FB12_Msk      (0x1UL << CAN_F8R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R1_FB12          CAN_F8R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos      (13U)                                           
+#define CAN_F8R1_FB13_Msk      (0x1UL << CAN_F8R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R1_FB13          CAN_F8R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos      (14U)                                           
+#define CAN_F8R1_FB14_Msk      (0x1UL << CAN_F8R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R1_FB14          CAN_F8R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos      (15U)                                           
+#define CAN_F8R1_FB15_Msk      (0x1UL << CAN_F8R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R1_FB15          CAN_F8R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos      (16U)                                           
+#define CAN_F8R1_FB16_Msk      (0x1UL << CAN_F8R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R1_FB16          CAN_F8R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos      (17U)                                           
+#define CAN_F8R1_FB17_Msk      (0x1UL << CAN_F8R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R1_FB17          CAN_F8R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos      (18U)                                           
+#define CAN_F8R1_FB18_Msk      (0x1UL << CAN_F8R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R1_FB18          CAN_F8R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos      (19U)                                           
+#define CAN_F8R1_FB19_Msk      (0x1UL << CAN_F8R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R1_FB19          CAN_F8R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos      (20U)                                           
+#define CAN_F8R1_FB20_Msk      (0x1UL << CAN_F8R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R1_FB20          CAN_F8R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos      (21U)                                           
+#define CAN_F8R1_FB21_Msk      (0x1UL << CAN_F8R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R1_FB21          CAN_F8R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos      (22U)                                           
+#define CAN_F8R1_FB22_Msk      (0x1UL << CAN_F8R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R1_FB22          CAN_F8R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos      (23U)                                           
+#define CAN_F8R1_FB23_Msk      (0x1UL << CAN_F8R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R1_FB23          CAN_F8R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos      (24U)                                           
+#define CAN_F8R1_FB24_Msk      (0x1UL << CAN_F8R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R1_FB24          CAN_F8R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos      (25U)                                           
+#define CAN_F8R1_FB25_Msk      (0x1UL << CAN_F8R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R1_FB25          CAN_F8R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos      (26U)                                           
+#define CAN_F8R1_FB26_Msk      (0x1UL << CAN_F8R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R1_FB26          CAN_F8R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos      (27U)                                           
+#define CAN_F8R1_FB27_Msk      (0x1UL << CAN_F8R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R1_FB27          CAN_F8R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos      (28U)                                           
+#define CAN_F8R1_FB28_Msk      (0x1UL << CAN_F8R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R1_FB28          CAN_F8R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos      (29U)                                           
+#define CAN_F8R1_FB29_Msk      (0x1UL << CAN_F8R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R1_FB29          CAN_F8R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos      (30U)                                           
+#define CAN_F8R1_FB30_Msk      (0x1UL << CAN_F8R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R1_FB30          CAN_F8R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos      (31U)                                           
+#define CAN_F8R1_FB31_Msk      (0x1UL << CAN_F8R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R1_FB31          CAN_F8R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R1 register  *******************/
+#define CAN_F9R1_FB0_Pos       (0U)                                            
+#define CAN_F9R1_FB0_Msk       (0x1UL << CAN_F9R1_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R1_FB0           CAN_F9R1_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos       (1U)                                            
+#define CAN_F9R1_FB1_Msk       (0x1UL << CAN_F9R1_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R1_FB1           CAN_F9R1_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos       (2U)                                            
+#define CAN_F9R1_FB2_Msk       (0x1UL << CAN_F9R1_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R1_FB2           CAN_F9R1_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos       (3U)                                            
+#define CAN_F9R1_FB3_Msk       (0x1UL << CAN_F9R1_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R1_FB3           CAN_F9R1_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos       (4U)                                            
+#define CAN_F9R1_FB4_Msk       (0x1UL << CAN_F9R1_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R1_FB4           CAN_F9R1_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos       (5U)                                            
+#define CAN_F9R1_FB5_Msk       (0x1UL << CAN_F9R1_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R1_FB5           CAN_F9R1_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos       (6U)                                            
+#define CAN_F9R1_FB6_Msk       (0x1UL << CAN_F9R1_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R1_FB6           CAN_F9R1_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos       (7U)                                            
+#define CAN_F9R1_FB7_Msk       (0x1UL << CAN_F9R1_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R1_FB7           CAN_F9R1_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos       (8U)                                            
+#define CAN_F9R1_FB8_Msk       (0x1UL << CAN_F9R1_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R1_FB8           CAN_F9R1_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos       (9U)                                            
+#define CAN_F9R1_FB9_Msk       (0x1UL << CAN_F9R1_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R1_FB9           CAN_F9R1_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos      (10U)                                           
+#define CAN_F9R1_FB10_Msk      (0x1UL << CAN_F9R1_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R1_FB10          CAN_F9R1_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos      (11U)                                           
+#define CAN_F9R1_FB11_Msk      (0x1UL << CAN_F9R1_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R1_FB11          CAN_F9R1_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos      (12U)                                           
+#define CAN_F9R1_FB12_Msk      (0x1UL << CAN_F9R1_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R1_FB12          CAN_F9R1_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos      (13U)                                           
+#define CAN_F9R1_FB13_Msk      (0x1UL << CAN_F9R1_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R1_FB13          CAN_F9R1_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos      (14U)                                           
+#define CAN_F9R1_FB14_Msk      (0x1UL << CAN_F9R1_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R1_FB14          CAN_F9R1_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos      (15U)                                           
+#define CAN_F9R1_FB15_Msk      (0x1UL << CAN_F9R1_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R1_FB15          CAN_F9R1_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos      (16U)                                           
+#define CAN_F9R1_FB16_Msk      (0x1UL << CAN_F9R1_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R1_FB16          CAN_F9R1_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos      (17U)                                           
+#define CAN_F9R1_FB17_Msk      (0x1UL << CAN_F9R1_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R1_FB17          CAN_F9R1_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos      (18U)                                           
+#define CAN_F9R1_FB18_Msk      (0x1UL << CAN_F9R1_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R1_FB18          CAN_F9R1_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos      (19U)                                           
+#define CAN_F9R1_FB19_Msk      (0x1UL << CAN_F9R1_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R1_FB19          CAN_F9R1_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos      (20U)                                           
+#define CAN_F9R1_FB20_Msk      (0x1UL << CAN_F9R1_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R1_FB20          CAN_F9R1_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos      (21U)                                           
+#define CAN_F9R1_FB21_Msk      (0x1UL << CAN_F9R1_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R1_FB21          CAN_F9R1_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos      (22U)                                           
+#define CAN_F9R1_FB22_Msk      (0x1UL << CAN_F9R1_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R1_FB22          CAN_F9R1_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos      (23U)                                           
+#define CAN_F9R1_FB23_Msk      (0x1UL << CAN_F9R1_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R1_FB23          CAN_F9R1_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos      (24U)                                           
+#define CAN_F9R1_FB24_Msk      (0x1UL << CAN_F9R1_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R1_FB24          CAN_F9R1_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos      (25U)                                           
+#define CAN_F9R1_FB25_Msk      (0x1UL << CAN_F9R1_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R1_FB25          CAN_F9R1_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos      (26U)                                           
+#define CAN_F9R1_FB26_Msk      (0x1UL << CAN_F9R1_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R1_FB26          CAN_F9R1_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos      (27U)                                           
+#define CAN_F9R1_FB27_Msk      (0x1UL << CAN_F9R1_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R1_FB27          CAN_F9R1_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos      (28U)                                           
+#define CAN_F9R1_FB28_Msk      (0x1UL << CAN_F9R1_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R1_FB28          CAN_F9R1_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos      (29U)                                           
+#define CAN_F9R1_FB29_Msk      (0x1UL << CAN_F9R1_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R1_FB29          CAN_F9R1_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos      (30U)                                           
+#define CAN_F9R1_FB30_Msk      (0x1UL << CAN_F9R1_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R1_FB30          CAN_F9R1_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos      (31U)                                           
+#define CAN_F9R1_FB31_Msk      (0x1UL << CAN_F9R1_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R1_FB31          CAN_F9R1_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R1 register  ******************/
+#define CAN_F10R1_FB0_Pos      (0U)                                            
+#define CAN_F10R1_FB0_Msk      (0x1UL << CAN_F10R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R1_FB0          CAN_F10R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos      (1U)                                            
+#define CAN_F10R1_FB1_Msk      (0x1UL << CAN_F10R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R1_FB1          CAN_F10R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos      (2U)                                            
+#define CAN_F10R1_FB2_Msk      (0x1UL << CAN_F10R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R1_FB2          CAN_F10R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos      (3U)                                            
+#define CAN_F10R1_FB3_Msk      (0x1UL << CAN_F10R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R1_FB3          CAN_F10R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos      (4U)                                            
+#define CAN_F10R1_FB4_Msk      (0x1UL << CAN_F10R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R1_FB4          CAN_F10R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos      (5U)                                            
+#define CAN_F10R1_FB5_Msk      (0x1UL << CAN_F10R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R1_FB5          CAN_F10R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos      (6U)                                            
+#define CAN_F10R1_FB6_Msk      (0x1UL << CAN_F10R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R1_FB6          CAN_F10R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos      (7U)                                            
+#define CAN_F10R1_FB7_Msk      (0x1UL << CAN_F10R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R1_FB7          CAN_F10R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos      (8U)                                            
+#define CAN_F10R1_FB8_Msk      (0x1UL << CAN_F10R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R1_FB8          CAN_F10R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos      (9U)                                            
+#define CAN_F10R1_FB9_Msk      (0x1UL << CAN_F10R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R1_FB9          CAN_F10R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos     (10U)                                           
+#define CAN_F10R1_FB10_Msk     (0x1UL << CAN_F10R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R1_FB10         CAN_F10R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos     (11U)                                           
+#define CAN_F10R1_FB11_Msk     (0x1UL << CAN_F10R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R1_FB11         CAN_F10R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos     (12U)                                           
+#define CAN_F10R1_FB12_Msk     (0x1UL << CAN_F10R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R1_FB12         CAN_F10R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos     (13U)                                           
+#define CAN_F10R1_FB13_Msk     (0x1UL << CAN_F10R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R1_FB13         CAN_F10R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos     (14U)                                           
+#define CAN_F10R1_FB14_Msk     (0x1UL << CAN_F10R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R1_FB14         CAN_F10R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos     (15U)                                           
+#define CAN_F10R1_FB15_Msk     (0x1UL << CAN_F10R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R1_FB15         CAN_F10R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos     (16U)                                           
+#define CAN_F10R1_FB16_Msk     (0x1UL << CAN_F10R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R1_FB16         CAN_F10R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos     (17U)                                           
+#define CAN_F10R1_FB17_Msk     (0x1UL << CAN_F10R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R1_FB17         CAN_F10R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos     (18U)                                           
+#define CAN_F10R1_FB18_Msk     (0x1UL << CAN_F10R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R1_FB18         CAN_F10R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos     (19U)                                           
+#define CAN_F10R1_FB19_Msk     (0x1UL << CAN_F10R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R1_FB19         CAN_F10R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos     (20U)                                           
+#define CAN_F10R1_FB20_Msk     (0x1UL << CAN_F10R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R1_FB20         CAN_F10R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos     (21U)                                           
+#define CAN_F10R1_FB21_Msk     (0x1UL << CAN_F10R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R1_FB21         CAN_F10R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos     (22U)                                           
+#define CAN_F10R1_FB22_Msk     (0x1UL << CAN_F10R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R1_FB22         CAN_F10R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos     (23U)                                           
+#define CAN_F10R1_FB23_Msk     (0x1UL << CAN_F10R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R1_FB23         CAN_F10R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos     (24U)                                           
+#define CAN_F10R1_FB24_Msk     (0x1UL << CAN_F10R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R1_FB24         CAN_F10R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos     (25U)                                           
+#define CAN_F10R1_FB25_Msk     (0x1UL << CAN_F10R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R1_FB25         CAN_F10R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos     (26U)                                           
+#define CAN_F10R1_FB26_Msk     (0x1UL << CAN_F10R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R1_FB26         CAN_F10R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos     (27U)                                           
+#define CAN_F10R1_FB27_Msk     (0x1UL << CAN_F10R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R1_FB27         CAN_F10R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos     (28U)                                           
+#define CAN_F10R1_FB28_Msk     (0x1UL << CAN_F10R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R1_FB28         CAN_F10R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos     (29U)                                           
+#define CAN_F10R1_FB29_Msk     (0x1UL << CAN_F10R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R1_FB29         CAN_F10R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos     (30U)                                           
+#define CAN_F10R1_FB30_Msk     (0x1UL << CAN_F10R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R1_FB30         CAN_F10R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos     (31U)                                           
+#define CAN_F10R1_FB31_Msk     (0x1UL << CAN_F10R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R1_FB31         CAN_F10R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R1 register  ******************/
+#define CAN_F11R1_FB0_Pos      (0U)                                            
+#define CAN_F11R1_FB0_Msk      (0x1UL << CAN_F11R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R1_FB0          CAN_F11R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos      (1U)                                            
+#define CAN_F11R1_FB1_Msk      (0x1UL << CAN_F11R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R1_FB1          CAN_F11R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos      (2U)                                            
+#define CAN_F11R1_FB2_Msk      (0x1UL << CAN_F11R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R1_FB2          CAN_F11R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos      (3U)                                            
+#define CAN_F11R1_FB3_Msk      (0x1UL << CAN_F11R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R1_FB3          CAN_F11R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos      (4U)                                            
+#define CAN_F11R1_FB4_Msk      (0x1UL << CAN_F11R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R1_FB4          CAN_F11R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos      (5U)                                            
+#define CAN_F11R1_FB5_Msk      (0x1UL << CAN_F11R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R1_FB5          CAN_F11R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos      (6U)                                            
+#define CAN_F11R1_FB6_Msk      (0x1UL << CAN_F11R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R1_FB6          CAN_F11R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos      (7U)                                            
+#define CAN_F11R1_FB7_Msk      (0x1UL << CAN_F11R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R1_FB7          CAN_F11R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos      (8U)                                            
+#define CAN_F11R1_FB8_Msk      (0x1UL << CAN_F11R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R1_FB8          CAN_F11R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos      (9U)                                            
+#define CAN_F11R1_FB9_Msk      (0x1UL << CAN_F11R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R1_FB9          CAN_F11R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos     (10U)                                           
+#define CAN_F11R1_FB10_Msk     (0x1UL << CAN_F11R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R1_FB10         CAN_F11R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos     (11U)                                           
+#define CAN_F11R1_FB11_Msk     (0x1UL << CAN_F11R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R1_FB11         CAN_F11R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos     (12U)                                           
+#define CAN_F11R1_FB12_Msk     (0x1UL << CAN_F11R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R1_FB12         CAN_F11R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos     (13U)                                           
+#define CAN_F11R1_FB13_Msk     (0x1UL << CAN_F11R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R1_FB13         CAN_F11R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos     (14U)                                           
+#define CAN_F11R1_FB14_Msk     (0x1UL << CAN_F11R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R1_FB14         CAN_F11R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos     (15U)                                           
+#define CAN_F11R1_FB15_Msk     (0x1UL << CAN_F11R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R1_FB15         CAN_F11R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos     (16U)                                           
+#define CAN_F11R1_FB16_Msk     (0x1UL << CAN_F11R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R1_FB16         CAN_F11R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos     (17U)                                           
+#define CAN_F11R1_FB17_Msk     (0x1UL << CAN_F11R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R1_FB17         CAN_F11R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos     (18U)                                           
+#define CAN_F11R1_FB18_Msk     (0x1UL << CAN_F11R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R1_FB18         CAN_F11R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos     (19U)                                           
+#define CAN_F11R1_FB19_Msk     (0x1UL << CAN_F11R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R1_FB19         CAN_F11R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos     (20U)                                           
+#define CAN_F11R1_FB20_Msk     (0x1UL << CAN_F11R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R1_FB20         CAN_F11R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos     (21U)                                           
+#define CAN_F11R1_FB21_Msk     (0x1UL << CAN_F11R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R1_FB21         CAN_F11R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos     (22U)                                           
+#define CAN_F11R1_FB22_Msk     (0x1UL << CAN_F11R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R1_FB22         CAN_F11R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos     (23U)                                           
+#define CAN_F11R1_FB23_Msk     (0x1UL << CAN_F11R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R1_FB23         CAN_F11R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos     (24U)                                           
+#define CAN_F11R1_FB24_Msk     (0x1UL << CAN_F11R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R1_FB24         CAN_F11R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos     (25U)                                           
+#define CAN_F11R1_FB25_Msk     (0x1UL << CAN_F11R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R1_FB25         CAN_F11R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos     (26U)                                           
+#define CAN_F11R1_FB26_Msk     (0x1UL << CAN_F11R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R1_FB26         CAN_F11R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos     (27U)                                           
+#define CAN_F11R1_FB27_Msk     (0x1UL << CAN_F11R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R1_FB27         CAN_F11R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos     (28U)                                           
+#define CAN_F11R1_FB28_Msk     (0x1UL << CAN_F11R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R1_FB28         CAN_F11R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos     (29U)                                           
+#define CAN_F11R1_FB29_Msk     (0x1UL << CAN_F11R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R1_FB29         CAN_F11R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos     (30U)                                           
+#define CAN_F11R1_FB30_Msk     (0x1UL << CAN_F11R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R1_FB30         CAN_F11R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos     (31U)                                           
+#define CAN_F11R1_FB31_Msk     (0x1UL << CAN_F11R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R1_FB31         CAN_F11R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R1 register  ******************/
+#define CAN_F12R1_FB0_Pos      (0U)                                            
+#define CAN_F12R1_FB0_Msk      (0x1UL << CAN_F12R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R1_FB0          CAN_F12R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos      (1U)                                            
+#define CAN_F12R1_FB1_Msk      (0x1UL << CAN_F12R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R1_FB1          CAN_F12R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos      (2U)                                            
+#define CAN_F12R1_FB2_Msk      (0x1UL << CAN_F12R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R1_FB2          CAN_F12R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos      (3U)                                            
+#define CAN_F12R1_FB3_Msk      (0x1UL << CAN_F12R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R1_FB3          CAN_F12R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos      (4U)                                            
+#define CAN_F12R1_FB4_Msk      (0x1UL << CAN_F12R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R1_FB4          CAN_F12R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos      (5U)                                            
+#define CAN_F12R1_FB5_Msk      (0x1UL << CAN_F12R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R1_FB5          CAN_F12R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos      (6U)                                            
+#define CAN_F12R1_FB6_Msk      (0x1UL << CAN_F12R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R1_FB6          CAN_F12R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos      (7U)                                            
+#define CAN_F12R1_FB7_Msk      (0x1UL << CAN_F12R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R1_FB7          CAN_F12R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos      (8U)                                            
+#define CAN_F12R1_FB8_Msk      (0x1UL << CAN_F12R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R1_FB8          CAN_F12R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos      (9U)                                            
+#define CAN_F12R1_FB9_Msk      (0x1UL << CAN_F12R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R1_FB9          CAN_F12R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos     (10U)                                           
+#define CAN_F12R1_FB10_Msk     (0x1UL << CAN_F12R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R1_FB10         CAN_F12R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos     (11U)                                           
+#define CAN_F12R1_FB11_Msk     (0x1UL << CAN_F12R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R1_FB11         CAN_F12R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos     (12U)                                           
+#define CAN_F12R1_FB12_Msk     (0x1UL << CAN_F12R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R1_FB12         CAN_F12R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos     (13U)                                           
+#define CAN_F12R1_FB13_Msk     (0x1UL << CAN_F12R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R1_FB13         CAN_F12R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos     (14U)                                           
+#define CAN_F12R1_FB14_Msk     (0x1UL << CAN_F12R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R1_FB14         CAN_F12R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos     (15U)                                           
+#define CAN_F12R1_FB15_Msk     (0x1UL << CAN_F12R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R1_FB15         CAN_F12R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos     (16U)                                           
+#define CAN_F12R1_FB16_Msk     (0x1UL << CAN_F12R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R1_FB16         CAN_F12R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos     (17U)                                           
+#define CAN_F12R1_FB17_Msk     (0x1UL << CAN_F12R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R1_FB17         CAN_F12R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos     (18U)                                           
+#define CAN_F12R1_FB18_Msk     (0x1UL << CAN_F12R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R1_FB18         CAN_F12R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos     (19U)                                           
+#define CAN_F12R1_FB19_Msk     (0x1UL << CAN_F12R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R1_FB19         CAN_F12R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos     (20U)                                           
+#define CAN_F12R1_FB20_Msk     (0x1UL << CAN_F12R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R1_FB20         CAN_F12R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos     (21U)                                           
+#define CAN_F12R1_FB21_Msk     (0x1UL << CAN_F12R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R1_FB21         CAN_F12R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos     (22U)                                           
+#define CAN_F12R1_FB22_Msk     (0x1UL << CAN_F12R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R1_FB22         CAN_F12R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos     (23U)                                           
+#define CAN_F12R1_FB23_Msk     (0x1UL << CAN_F12R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R1_FB23         CAN_F12R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos     (24U)                                           
+#define CAN_F12R1_FB24_Msk     (0x1UL << CAN_F12R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R1_FB24         CAN_F12R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos     (25U)                                           
+#define CAN_F12R1_FB25_Msk     (0x1UL << CAN_F12R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R1_FB25         CAN_F12R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos     (26U)                                           
+#define CAN_F12R1_FB26_Msk     (0x1UL << CAN_F12R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R1_FB26         CAN_F12R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos     (27U)                                           
+#define CAN_F12R1_FB27_Msk     (0x1UL << CAN_F12R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R1_FB27         CAN_F12R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos     (28U)                                           
+#define CAN_F12R1_FB28_Msk     (0x1UL << CAN_F12R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R1_FB28         CAN_F12R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos     (29U)                                           
+#define CAN_F12R1_FB29_Msk     (0x1UL << CAN_F12R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R1_FB29         CAN_F12R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos     (30U)                                           
+#define CAN_F12R1_FB30_Msk     (0x1UL << CAN_F12R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R1_FB30         CAN_F12R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos     (31U)                                           
+#define CAN_F12R1_FB31_Msk     (0x1UL << CAN_F12R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R1_FB31         CAN_F12R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R1 register  ******************/
+#define CAN_F13R1_FB0_Pos      (0U)                                            
+#define CAN_F13R1_FB0_Msk      (0x1UL << CAN_F13R1_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R1_FB0          CAN_F13R1_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos      (1U)                                            
+#define CAN_F13R1_FB1_Msk      (0x1UL << CAN_F13R1_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R1_FB1          CAN_F13R1_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos      (2U)                                            
+#define CAN_F13R1_FB2_Msk      (0x1UL << CAN_F13R1_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R1_FB2          CAN_F13R1_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos      (3U)                                            
+#define CAN_F13R1_FB3_Msk      (0x1UL << CAN_F13R1_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R1_FB3          CAN_F13R1_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos      (4U)                                            
+#define CAN_F13R1_FB4_Msk      (0x1UL << CAN_F13R1_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R1_FB4          CAN_F13R1_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos      (5U)                                            
+#define CAN_F13R1_FB5_Msk      (0x1UL << CAN_F13R1_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R1_FB5          CAN_F13R1_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos      (6U)                                            
+#define CAN_F13R1_FB6_Msk      (0x1UL << CAN_F13R1_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R1_FB6          CAN_F13R1_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos      (7U)                                            
+#define CAN_F13R1_FB7_Msk      (0x1UL << CAN_F13R1_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R1_FB7          CAN_F13R1_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos      (8U)                                            
+#define CAN_F13R1_FB8_Msk      (0x1UL << CAN_F13R1_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R1_FB8          CAN_F13R1_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos      (9U)                                            
+#define CAN_F13R1_FB9_Msk      (0x1UL << CAN_F13R1_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R1_FB9          CAN_F13R1_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos     (10U)                                           
+#define CAN_F13R1_FB10_Msk     (0x1UL << CAN_F13R1_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R1_FB10         CAN_F13R1_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos     (11U)                                           
+#define CAN_F13R1_FB11_Msk     (0x1UL << CAN_F13R1_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R1_FB11         CAN_F13R1_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos     (12U)                                           
+#define CAN_F13R1_FB12_Msk     (0x1UL << CAN_F13R1_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R1_FB12         CAN_F13R1_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos     (13U)                                           
+#define CAN_F13R1_FB13_Msk     (0x1UL << CAN_F13R1_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R1_FB13         CAN_F13R1_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos     (14U)                                           
+#define CAN_F13R1_FB14_Msk     (0x1UL << CAN_F13R1_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R1_FB14         CAN_F13R1_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos     (15U)                                           
+#define CAN_F13R1_FB15_Msk     (0x1UL << CAN_F13R1_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R1_FB15         CAN_F13R1_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos     (16U)                                           
+#define CAN_F13R1_FB16_Msk     (0x1UL << CAN_F13R1_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R1_FB16         CAN_F13R1_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos     (17U)                                           
+#define CAN_F13R1_FB17_Msk     (0x1UL << CAN_F13R1_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R1_FB17         CAN_F13R1_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos     (18U)                                           
+#define CAN_F13R1_FB18_Msk     (0x1UL << CAN_F13R1_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R1_FB18         CAN_F13R1_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos     (19U)                                           
+#define CAN_F13R1_FB19_Msk     (0x1UL << CAN_F13R1_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R1_FB19         CAN_F13R1_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos     (20U)                                           
+#define CAN_F13R1_FB20_Msk     (0x1UL << CAN_F13R1_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R1_FB20         CAN_F13R1_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos     (21U)                                           
+#define CAN_F13R1_FB21_Msk     (0x1UL << CAN_F13R1_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R1_FB21         CAN_F13R1_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos     (22U)                                           
+#define CAN_F13R1_FB22_Msk     (0x1UL << CAN_F13R1_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R1_FB22         CAN_F13R1_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos     (23U)                                           
+#define CAN_F13R1_FB23_Msk     (0x1UL << CAN_F13R1_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R1_FB23         CAN_F13R1_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos     (24U)                                           
+#define CAN_F13R1_FB24_Msk     (0x1UL << CAN_F13R1_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R1_FB24         CAN_F13R1_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos     (25U)                                           
+#define CAN_F13R1_FB25_Msk     (0x1UL << CAN_F13R1_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R1_FB25         CAN_F13R1_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos     (26U)                                           
+#define CAN_F13R1_FB26_Msk     (0x1UL << CAN_F13R1_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R1_FB26         CAN_F13R1_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos     (27U)                                           
+#define CAN_F13R1_FB27_Msk     (0x1UL << CAN_F13R1_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R1_FB27         CAN_F13R1_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos     (28U)                                           
+#define CAN_F13R1_FB28_Msk     (0x1UL << CAN_F13R1_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R1_FB28         CAN_F13R1_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos     (29U)                                           
+#define CAN_F13R1_FB29_Msk     (0x1UL << CAN_F13R1_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R1_FB29         CAN_F13R1_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R1_FB30_Pos     (30U)                                           
+#define CAN_F13R1_FB30_Msk     (0x1UL << CAN_F13R1_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R1_FB30         CAN_F13R1_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R1_FB31_Pos     (31U)                                           
+#define CAN_F13R1_FB31_Msk     (0x1UL << CAN_F13R1_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R1_FB31         CAN_F13R1_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F0R2 register  *******************/
+#define CAN_F0R2_FB0_Pos       (0U)                                            
+#define CAN_F0R2_FB0_Msk       (0x1UL << CAN_F0R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F0R2_FB0           CAN_F0R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F0R2_FB1_Pos       (1U)                                            
+#define CAN_F0R2_FB1_Msk       (0x1UL << CAN_F0R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F0R2_FB1           CAN_F0R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F0R2_FB2_Pos       (2U)                                            
+#define CAN_F0R2_FB2_Msk       (0x1UL << CAN_F0R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F0R2_FB2           CAN_F0R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F0R2_FB3_Pos       (3U)                                            
+#define CAN_F0R2_FB3_Msk       (0x1UL << CAN_F0R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F0R2_FB3           CAN_F0R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F0R2_FB4_Pos       (4U)                                            
+#define CAN_F0R2_FB4_Msk       (0x1UL << CAN_F0R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F0R2_FB4           CAN_F0R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F0R2_FB5_Pos       (5U)                                            
+#define CAN_F0R2_FB5_Msk       (0x1UL << CAN_F0R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F0R2_FB5           CAN_F0R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F0R2_FB6_Pos       (6U)                                            
+#define CAN_F0R2_FB6_Msk       (0x1UL << CAN_F0R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F0R2_FB6           CAN_F0R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F0R2_FB7_Pos       (7U)                                            
+#define CAN_F0R2_FB7_Msk       (0x1UL << CAN_F0R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F0R2_FB7           CAN_F0R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F0R2_FB8_Pos       (8U)                                            
+#define CAN_F0R2_FB8_Msk       (0x1UL << CAN_F0R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F0R2_FB8           CAN_F0R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F0R2_FB9_Pos       (9U)                                            
+#define CAN_F0R2_FB9_Msk       (0x1UL << CAN_F0R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F0R2_FB9           CAN_F0R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F0R2_FB10_Pos      (10U)                                           
+#define CAN_F0R2_FB10_Msk      (0x1UL << CAN_F0R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F0R2_FB10          CAN_F0R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F0R2_FB11_Pos      (11U)                                           
+#define CAN_F0R2_FB11_Msk      (0x1UL << CAN_F0R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F0R2_FB11          CAN_F0R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F0R2_FB12_Pos      (12U)                                           
+#define CAN_F0R2_FB12_Msk      (0x1UL << CAN_F0R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F0R2_FB12          CAN_F0R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F0R2_FB13_Pos      (13U)                                           
+#define CAN_F0R2_FB13_Msk      (0x1UL << CAN_F0R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F0R2_FB13          CAN_F0R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F0R2_FB14_Pos      (14U)                                           
+#define CAN_F0R2_FB14_Msk      (0x1UL << CAN_F0R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F0R2_FB14          CAN_F0R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F0R2_FB15_Pos      (15U)                                           
+#define CAN_F0R2_FB15_Msk      (0x1UL << CAN_F0R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F0R2_FB15          CAN_F0R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F0R2_FB16_Pos      (16U)                                           
+#define CAN_F0R2_FB16_Msk      (0x1UL << CAN_F0R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F0R2_FB16          CAN_F0R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F0R2_FB17_Pos      (17U)                                           
+#define CAN_F0R2_FB17_Msk      (0x1UL << CAN_F0R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F0R2_FB17          CAN_F0R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F0R2_FB18_Pos      (18U)                                           
+#define CAN_F0R2_FB18_Msk      (0x1UL << CAN_F0R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F0R2_FB18          CAN_F0R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F0R2_FB19_Pos      (19U)                                           
+#define CAN_F0R2_FB19_Msk      (0x1UL << CAN_F0R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F0R2_FB19          CAN_F0R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F0R2_FB20_Pos      (20U)                                           
+#define CAN_F0R2_FB20_Msk      (0x1UL << CAN_F0R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F0R2_FB20          CAN_F0R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F0R2_FB21_Pos      (21U)                                           
+#define CAN_F0R2_FB21_Msk      (0x1UL << CAN_F0R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F0R2_FB21          CAN_F0R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F0R2_FB22_Pos      (22U)                                           
+#define CAN_F0R2_FB22_Msk      (0x1UL << CAN_F0R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F0R2_FB22          CAN_F0R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F0R2_FB23_Pos      (23U)                                           
+#define CAN_F0R2_FB23_Msk      (0x1UL << CAN_F0R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F0R2_FB23          CAN_F0R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F0R2_FB24_Pos      (24U)                                           
+#define CAN_F0R2_FB24_Msk      (0x1UL << CAN_F0R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F0R2_FB24          CAN_F0R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F0R2_FB25_Pos      (25U)                                           
+#define CAN_F0R2_FB25_Msk      (0x1UL << CAN_F0R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F0R2_FB25          CAN_F0R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F0R2_FB26_Pos      (26U)                                           
+#define CAN_F0R2_FB26_Msk      (0x1UL << CAN_F0R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F0R2_FB26          CAN_F0R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F0R2_FB27_Pos      (27U)                                           
+#define CAN_F0R2_FB27_Msk      (0x1UL << CAN_F0R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F0R2_FB27          CAN_F0R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F0R2_FB28_Pos      (28U)                                           
+#define CAN_F0R2_FB28_Msk      (0x1UL << CAN_F0R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F0R2_FB28          CAN_F0R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F0R2_FB29_Pos      (29U)                                           
+#define CAN_F0R2_FB29_Msk      (0x1UL << CAN_F0R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F0R2_FB29          CAN_F0R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F0R2_FB30_Pos      (30U)                                           
+#define CAN_F0R2_FB30_Msk      (0x1UL << CAN_F0R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F0R2_FB30          CAN_F0R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F0R2_FB31_Pos      (31U)                                           
+#define CAN_F0R2_FB31_Msk      (0x1UL << CAN_F0R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F0R2_FB31          CAN_F0R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F1R2 register  *******************/
+#define CAN_F1R2_FB0_Pos       (0U)                                            
+#define CAN_F1R2_FB0_Msk       (0x1UL << CAN_F1R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F1R2_FB0           CAN_F1R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F1R2_FB1_Pos       (1U)                                            
+#define CAN_F1R2_FB1_Msk       (0x1UL << CAN_F1R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F1R2_FB1           CAN_F1R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F1R2_FB2_Pos       (2U)                                            
+#define CAN_F1R2_FB2_Msk       (0x1UL << CAN_F1R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F1R2_FB2           CAN_F1R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F1R2_FB3_Pos       (3U)                                            
+#define CAN_F1R2_FB3_Msk       (0x1UL << CAN_F1R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F1R2_FB3           CAN_F1R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F1R2_FB4_Pos       (4U)                                            
+#define CAN_F1R2_FB4_Msk       (0x1UL << CAN_F1R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F1R2_FB4           CAN_F1R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F1R2_FB5_Pos       (5U)                                            
+#define CAN_F1R2_FB5_Msk       (0x1UL << CAN_F1R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F1R2_FB5           CAN_F1R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F1R2_FB6_Pos       (6U)                                            
+#define CAN_F1R2_FB6_Msk       (0x1UL << CAN_F1R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F1R2_FB6           CAN_F1R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F1R2_FB7_Pos       (7U)                                            
+#define CAN_F1R2_FB7_Msk       (0x1UL << CAN_F1R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F1R2_FB7           CAN_F1R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F1R2_FB8_Pos       (8U)                                            
+#define CAN_F1R2_FB8_Msk       (0x1UL << CAN_F1R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F1R2_FB8           CAN_F1R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F1R2_FB9_Pos       (9U)                                            
+#define CAN_F1R2_FB9_Msk       (0x1UL << CAN_F1R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F1R2_FB9           CAN_F1R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F1R2_FB10_Pos      (10U)                                           
+#define CAN_F1R2_FB10_Msk      (0x1UL << CAN_F1R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F1R2_FB10          CAN_F1R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F1R2_FB11_Pos      (11U)                                           
+#define CAN_F1R2_FB11_Msk      (0x1UL << CAN_F1R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F1R2_FB11          CAN_F1R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F1R2_FB12_Pos      (12U)                                           
+#define CAN_F1R2_FB12_Msk      (0x1UL << CAN_F1R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F1R2_FB12          CAN_F1R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F1R2_FB13_Pos      (13U)                                           
+#define CAN_F1R2_FB13_Msk      (0x1UL << CAN_F1R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F1R2_FB13          CAN_F1R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F1R2_FB14_Pos      (14U)                                           
+#define CAN_F1R2_FB14_Msk      (0x1UL << CAN_F1R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F1R2_FB14          CAN_F1R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F1R2_FB15_Pos      (15U)                                           
+#define CAN_F1R2_FB15_Msk      (0x1UL << CAN_F1R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F1R2_FB15          CAN_F1R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F1R2_FB16_Pos      (16U)                                           
+#define CAN_F1R2_FB16_Msk      (0x1UL << CAN_F1R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F1R2_FB16          CAN_F1R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F1R2_FB17_Pos      (17U)                                           
+#define CAN_F1R2_FB17_Msk      (0x1UL << CAN_F1R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F1R2_FB17          CAN_F1R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F1R2_FB18_Pos      (18U)                                           
+#define CAN_F1R2_FB18_Msk      (0x1UL << CAN_F1R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F1R2_FB18          CAN_F1R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F1R2_FB19_Pos      (19U)                                           
+#define CAN_F1R2_FB19_Msk      (0x1UL << CAN_F1R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F1R2_FB19          CAN_F1R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F1R2_FB20_Pos      (20U)                                           
+#define CAN_F1R2_FB20_Msk      (0x1UL << CAN_F1R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F1R2_FB20          CAN_F1R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F1R2_FB21_Pos      (21U)                                           
+#define CAN_F1R2_FB21_Msk      (0x1UL << CAN_F1R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F1R2_FB21          CAN_F1R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F1R2_FB22_Pos      (22U)                                           
+#define CAN_F1R2_FB22_Msk      (0x1UL << CAN_F1R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F1R2_FB22          CAN_F1R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F1R2_FB23_Pos      (23U)                                           
+#define CAN_F1R2_FB23_Msk      (0x1UL << CAN_F1R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F1R2_FB23          CAN_F1R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F1R2_FB24_Pos      (24U)                                           
+#define CAN_F1R2_FB24_Msk      (0x1UL << CAN_F1R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F1R2_FB24          CAN_F1R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F1R2_FB25_Pos      (25U)                                           
+#define CAN_F1R2_FB25_Msk      (0x1UL << CAN_F1R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F1R2_FB25          CAN_F1R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F1R2_FB26_Pos      (26U)                                           
+#define CAN_F1R2_FB26_Msk      (0x1UL << CAN_F1R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F1R2_FB26          CAN_F1R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F1R2_FB27_Pos      (27U)                                           
+#define CAN_F1R2_FB27_Msk      (0x1UL << CAN_F1R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F1R2_FB27          CAN_F1R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F1R2_FB28_Pos      (28U)                                           
+#define CAN_F1R2_FB28_Msk      (0x1UL << CAN_F1R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F1R2_FB28          CAN_F1R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F1R2_FB29_Pos      (29U)                                           
+#define CAN_F1R2_FB29_Msk      (0x1UL << CAN_F1R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F1R2_FB29          CAN_F1R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F1R2_FB30_Pos      (30U)                                           
+#define CAN_F1R2_FB30_Msk      (0x1UL << CAN_F1R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F1R2_FB30          CAN_F1R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F1R2_FB31_Pos      (31U)                                           
+#define CAN_F1R2_FB31_Msk      (0x1UL << CAN_F1R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F1R2_FB31          CAN_F1R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F2R2 register  *******************/
+#define CAN_F2R2_FB0_Pos       (0U)                                            
+#define CAN_F2R2_FB0_Msk       (0x1UL << CAN_F2R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F2R2_FB0           CAN_F2R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F2R2_FB1_Pos       (1U)                                            
+#define CAN_F2R2_FB1_Msk       (0x1UL << CAN_F2R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F2R2_FB1           CAN_F2R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F2R2_FB2_Pos       (2U)                                            
+#define CAN_F2R2_FB2_Msk       (0x1UL << CAN_F2R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F2R2_FB2           CAN_F2R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F2R2_FB3_Pos       (3U)                                            
+#define CAN_F2R2_FB3_Msk       (0x1UL << CAN_F2R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F2R2_FB3           CAN_F2R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F2R2_FB4_Pos       (4U)                                            
+#define CAN_F2R2_FB4_Msk       (0x1UL << CAN_F2R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F2R2_FB4           CAN_F2R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F2R2_FB5_Pos       (5U)                                            
+#define CAN_F2R2_FB5_Msk       (0x1UL << CAN_F2R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F2R2_FB5           CAN_F2R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F2R2_FB6_Pos       (6U)                                            
+#define CAN_F2R2_FB6_Msk       (0x1UL << CAN_F2R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F2R2_FB6           CAN_F2R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F2R2_FB7_Pos       (7U)                                            
+#define CAN_F2R2_FB7_Msk       (0x1UL << CAN_F2R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F2R2_FB7           CAN_F2R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F2R2_FB8_Pos       (8U)                                            
+#define CAN_F2R2_FB8_Msk       (0x1UL << CAN_F2R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F2R2_FB8           CAN_F2R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F2R2_FB9_Pos       (9U)                                            
+#define CAN_F2R2_FB9_Msk       (0x1UL << CAN_F2R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F2R2_FB9           CAN_F2R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F2R2_FB10_Pos      (10U)                                           
+#define CAN_F2R2_FB10_Msk      (0x1UL << CAN_F2R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F2R2_FB10          CAN_F2R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F2R2_FB11_Pos      (11U)                                           
+#define CAN_F2R2_FB11_Msk      (0x1UL << CAN_F2R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F2R2_FB11          CAN_F2R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F2R2_FB12_Pos      (12U)                                           
+#define CAN_F2R2_FB12_Msk      (0x1UL << CAN_F2R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F2R2_FB12          CAN_F2R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F2R2_FB13_Pos      (13U)                                           
+#define CAN_F2R2_FB13_Msk      (0x1UL << CAN_F2R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F2R2_FB13          CAN_F2R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F2R2_FB14_Pos      (14U)                                           
+#define CAN_F2R2_FB14_Msk      (0x1UL << CAN_F2R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F2R2_FB14          CAN_F2R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F2R2_FB15_Pos      (15U)                                           
+#define CAN_F2R2_FB15_Msk      (0x1UL << CAN_F2R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F2R2_FB15          CAN_F2R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F2R2_FB16_Pos      (16U)                                           
+#define CAN_F2R2_FB16_Msk      (0x1UL << CAN_F2R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F2R2_FB16          CAN_F2R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F2R2_FB17_Pos      (17U)                                           
+#define CAN_F2R2_FB17_Msk      (0x1UL << CAN_F2R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F2R2_FB17          CAN_F2R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F2R2_FB18_Pos      (18U)                                           
+#define CAN_F2R2_FB18_Msk      (0x1UL << CAN_F2R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F2R2_FB18          CAN_F2R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F2R2_FB19_Pos      (19U)                                           
+#define CAN_F2R2_FB19_Msk      (0x1UL << CAN_F2R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F2R2_FB19          CAN_F2R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F2R2_FB20_Pos      (20U)                                           
+#define CAN_F2R2_FB20_Msk      (0x1UL << CAN_F2R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F2R2_FB20          CAN_F2R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F2R2_FB21_Pos      (21U)                                           
+#define CAN_F2R2_FB21_Msk      (0x1UL << CAN_F2R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F2R2_FB21          CAN_F2R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F2R2_FB22_Pos      (22U)                                           
+#define CAN_F2R2_FB22_Msk      (0x1UL << CAN_F2R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F2R2_FB22          CAN_F2R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F2R2_FB23_Pos      (23U)                                           
+#define CAN_F2R2_FB23_Msk      (0x1UL << CAN_F2R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F2R2_FB23          CAN_F2R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F2R2_FB24_Pos      (24U)                                           
+#define CAN_F2R2_FB24_Msk      (0x1UL << CAN_F2R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F2R2_FB24          CAN_F2R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F2R2_FB25_Pos      (25U)                                           
+#define CAN_F2R2_FB25_Msk      (0x1UL << CAN_F2R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F2R2_FB25          CAN_F2R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F2R2_FB26_Pos      (26U)                                           
+#define CAN_F2R2_FB26_Msk      (0x1UL << CAN_F2R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F2R2_FB26          CAN_F2R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F2R2_FB27_Pos      (27U)                                           
+#define CAN_F2R2_FB27_Msk      (0x1UL << CAN_F2R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F2R2_FB27          CAN_F2R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F2R2_FB28_Pos      (28U)                                           
+#define CAN_F2R2_FB28_Msk      (0x1UL << CAN_F2R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F2R2_FB28          CAN_F2R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F2R2_FB29_Pos      (29U)                                           
+#define CAN_F2R2_FB29_Msk      (0x1UL << CAN_F2R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F2R2_FB29          CAN_F2R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F2R2_FB30_Pos      (30U)                                           
+#define CAN_F2R2_FB30_Msk      (0x1UL << CAN_F2R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F2R2_FB30          CAN_F2R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F2R2_FB31_Pos      (31U)                                           
+#define CAN_F2R2_FB31_Msk      (0x1UL << CAN_F2R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F2R2_FB31          CAN_F2R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F3R2 register  *******************/
+#define CAN_F3R2_FB0_Pos       (0U)                                            
+#define CAN_F3R2_FB0_Msk       (0x1UL << CAN_F3R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F3R2_FB0           CAN_F3R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F3R2_FB1_Pos       (1U)                                            
+#define CAN_F3R2_FB1_Msk       (0x1UL << CAN_F3R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F3R2_FB1           CAN_F3R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F3R2_FB2_Pos       (2U)                                            
+#define CAN_F3R2_FB2_Msk       (0x1UL << CAN_F3R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F3R2_FB2           CAN_F3R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F3R2_FB3_Pos       (3U)                                            
+#define CAN_F3R2_FB3_Msk       (0x1UL << CAN_F3R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F3R2_FB3           CAN_F3R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F3R2_FB4_Pos       (4U)                                            
+#define CAN_F3R2_FB4_Msk       (0x1UL << CAN_F3R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F3R2_FB4           CAN_F3R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F3R2_FB5_Pos       (5U)                                            
+#define CAN_F3R2_FB5_Msk       (0x1UL << CAN_F3R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F3R2_FB5           CAN_F3R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F3R2_FB6_Pos       (6U)                                            
+#define CAN_F3R2_FB6_Msk       (0x1UL << CAN_F3R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F3R2_FB6           CAN_F3R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F3R2_FB7_Pos       (7U)                                            
+#define CAN_F3R2_FB7_Msk       (0x1UL << CAN_F3R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F3R2_FB7           CAN_F3R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F3R2_FB8_Pos       (8U)                                            
+#define CAN_F3R2_FB8_Msk       (0x1UL << CAN_F3R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F3R2_FB8           CAN_F3R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F3R2_FB9_Pos       (9U)                                            
+#define CAN_F3R2_FB9_Msk       (0x1UL << CAN_F3R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F3R2_FB9           CAN_F3R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F3R2_FB10_Pos      (10U)                                           
+#define CAN_F3R2_FB10_Msk      (0x1UL << CAN_F3R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F3R2_FB10          CAN_F3R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F3R2_FB11_Pos      (11U)                                           
+#define CAN_F3R2_FB11_Msk      (0x1UL << CAN_F3R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F3R2_FB11          CAN_F3R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F3R2_FB12_Pos      (12U)                                           
+#define CAN_F3R2_FB12_Msk      (0x1UL << CAN_F3R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F3R2_FB12          CAN_F3R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F3R2_FB13_Pos      (13U)                                           
+#define CAN_F3R2_FB13_Msk      (0x1UL << CAN_F3R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F3R2_FB13          CAN_F3R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F3R2_FB14_Pos      (14U)                                           
+#define CAN_F3R2_FB14_Msk      (0x1UL << CAN_F3R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F3R2_FB14          CAN_F3R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F3R2_FB15_Pos      (15U)                                           
+#define CAN_F3R2_FB15_Msk      (0x1UL << CAN_F3R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F3R2_FB15          CAN_F3R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F3R2_FB16_Pos      (16U)                                           
+#define CAN_F3R2_FB16_Msk      (0x1UL << CAN_F3R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F3R2_FB16          CAN_F3R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F3R2_FB17_Pos      (17U)                                           
+#define CAN_F3R2_FB17_Msk      (0x1UL << CAN_F3R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F3R2_FB17          CAN_F3R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F3R2_FB18_Pos      (18U)                                           
+#define CAN_F3R2_FB18_Msk      (0x1UL << CAN_F3R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F3R2_FB18          CAN_F3R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F3R2_FB19_Pos      (19U)                                           
+#define CAN_F3R2_FB19_Msk      (0x1UL << CAN_F3R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F3R2_FB19          CAN_F3R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F3R2_FB20_Pos      (20U)                                           
+#define CAN_F3R2_FB20_Msk      (0x1UL << CAN_F3R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F3R2_FB20          CAN_F3R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F3R2_FB21_Pos      (21U)                                           
+#define CAN_F3R2_FB21_Msk      (0x1UL << CAN_F3R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F3R2_FB21          CAN_F3R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F3R2_FB22_Pos      (22U)                                           
+#define CAN_F3R2_FB22_Msk      (0x1UL << CAN_F3R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F3R2_FB22          CAN_F3R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F3R2_FB23_Pos      (23U)                                           
+#define CAN_F3R2_FB23_Msk      (0x1UL << CAN_F3R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F3R2_FB23          CAN_F3R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F3R2_FB24_Pos      (24U)                                           
+#define CAN_F3R2_FB24_Msk      (0x1UL << CAN_F3R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F3R2_FB24          CAN_F3R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F3R2_FB25_Pos      (25U)                                           
+#define CAN_F3R2_FB25_Msk      (0x1UL << CAN_F3R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F3R2_FB25          CAN_F3R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F3R2_FB26_Pos      (26U)                                           
+#define CAN_F3R2_FB26_Msk      (0x1UL << CAN_F3R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F3R2_FB26          CAN_F3R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F3R2_FB27_Pos      (27U)                                           
+#define CAN_F3R2_FB27_Msk      (0x1UL << CAN_F3R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F3R2_FB27          CAN_F3R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F3R2_FB28_Pos      (28U)                                           
+#define CAN_F3R2_FB28_Msk      (0x1UL << CAN_F3R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F3R2_FB28          CAN_F3R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F3R2_FB29_Pos      (29U)                                           
+#define CAN_F3R2_FB29_Msk      (0x1UL << CAN_F3R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F3R2_FB29          CAN_F3R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F3R2_FB30_Pos      (30U)                                           
+#define CAN_F3R2_FB30_Msk      (0x1UL << CAN_F3R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F3R2_FB30          CAN_F3R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F3R2_FB31_Pos      (31U)                                           
+#define CAN_F3R2_FB31_Msk      (0x1UL << CAN_F3R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F3R2_FB31          CAN_F3R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F4R2 register  *******************/
+#define CAN_F4R2_FB0_Pos       (0U)                                            
+#define CAN_F4R2_FB0_Msk       (0x1UL << CAN_F4R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F4R2_FB0           CAN_F4R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F4R2_FB1_Pos       (1U)                                            
+#define CAN_F4R2_FB1_Msk       (0x1UL << CAN_F4R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F4R2_FB1           CAN_F4R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F4R2_FB2_Pos       (2U)                                            
+#define CAN_F4R2_FB2_Msk       (0x1UL << CAN_F4R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F4R2_FB2           CAN_F4R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F4R2_FB3_Pos       (3U)                                            
+#define CAN_F4R2_FB3_Msk       (0x1UL << CAN_F4R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F4R2_FB3           CAN_F4R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F4R2_FB4_Pos       (4U)                                            
+#define CAN_F4R2_FB4_Msk       (0x1UL << CAN_F4R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F4R2_FB4           CAN_F4R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F4R2_FB5_Pos       (5U)                                            
+#define CAN_F4R2_FB5_Msk       (0x1UL << CAN_F4R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F4R2_FB5           CAN_F4R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F4R2_FB6_Pos       (6U)                                            
+#define CAN_F4R2_FB6_Msk       (0x1UL << CAN_F4R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F4R2_FB6           CAN_F4R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F4R2_FB7_Pos       (7U)                                            
+#define CAN_F4R2_FB7_Msk       (0x1UL << CAN_F4R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F4R2_FB7           CAN_F4R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F4R2_FB8_Pos       (8U)                                            
+#define CAN_F4R2_FB8_Msk       (0x1UL << CAN_F4R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F4R2_FB8           CAN_F4R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F4R2_FB9_Pos       (9U)                                            
+#define CAN_F4R2_FB9_Msk       (0x1UL << CAN_F4R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F4R2_FB9           CAN_F4R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F4R2_FB10_Pos      (10U)                                           
+#define CAN_F4R2_FB10_Msk      (0x1UL << CAN_F4R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F4R2_FB10          CAN_F4R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F4R2_FB11_Pos      (11U)                                           
+#define CAN_F4R2_FB11_Msk      (0x1UL << CAN_F4R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F4R2_FB11          CAN_F4R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F4R2_FB12_Pos      (12U)                                           
+#define CAN_F4R2_FB12_Msk      (0x1UL << CAN_F4R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F4R2_FB12          CAN_F4R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F4R2_FB13_Pos      (13U)                                           
+#define CAN_F4R2_FB13_Msk      (0x1UL << CAN_F4R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F4R2_FB13          CAN_F4R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F4R2_FB14_Pos      (14U)                                           
+#define CAN_F4R2_FB14_Msk      (0x1UL << CAN_F4R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F4R2_FB14          CAN_F4R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F4R2_FB15_Pos      (15U)                                           
+#define CAN_F4R2_FB15_Msk      (0x1UL << CAN_F4R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F4R2_FB15          CAN_F4R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F4R2_FB16_Pos      (16U)                                           
+#define CAN_F4R2_FB16_Msk      (0x1UL << CAN_F4R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F4R2_FB16          CAN_F4R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F4R2_FB17_Pos      (17U)                                           
+#define CAN_F4R2_FB17_Msk      (0x1UL << CAN_F4R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F4R2_FB17          CAN_F4R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F4R2_FB18_Pos      (18U)                                           
+#define CAN_F4R2_FB18_Msk      (0x1UL << CAN_F4R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F4R2_FB18          CAN_F4R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F4R2_FB19_Pos      (19U)                                           
+#define CAN_F4R2_FB19_Msk      (0x1UL << CAN_F4R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F4R2_FB19          CAN_F4R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F4R2_FB20_Pos      (20U)                                           
+#define CAN_F4R2_FB20_Msk      (0x1UL << CAN_F4R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F4R2_FB20          CAN_F4R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F4R2_FB21_Pos      (21U)                                           
+#define CAN_F4R2_FB21_Msk      (0x1UL << CAN_F4R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F4R2_FB21          CAN_F4R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F4R2_FB22_Pos      (22U)                                           
+#define CAN_F4R2_FB22_Msk      (0x1UL << CAN_F4R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F4R2_FB22          CAN_F4R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F4R2_FB23_Pos      (23U)                                           
+#define CAN_F4R2_FB23_Msk      (0x1UL << CAN_F4R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F4R2_FB23          CAN_F4R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F4R2_FB24_Pos      (24U)                                           
+#define CAN_F4R2_FB24_Msk      (0x1UL << CAN_F4R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F4R2_FB24          CAN_F4R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F4R2_FB25_Pos      (25U)                                           
+#define CAN_F4R2_FB25_Msk      (0x1UL << CAN_F4R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F4R2_FB25          CAN_F4R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F4R2_FB26_Pos      (26U)                                           
+#define CAN_F4R2_FB26_Msk      (0x1UL << CAN_F4R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F4R2_FB26          CAN_F4R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F4R2_FB27_Pos      (27U)                                           
+#define CAN_F4R2_FB27_Msk      (0x1UL << CAN_F4R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F4R2_FB27          CAN_F4R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F4R2_FB28_Pos      (28U)                                           
+#define CAN_F4R2_FB28_Msk      (0x1UL << CAN_F4R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F4R2_FB28          CAN_F4R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F4R2_FB29_Pos      (29U)                                           
+#define CAN_F4R2_FB29_Msk      (0x1UL << CAN_F4R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F4R2_FB29          CAN_F4R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F4R2_FB30_Pos      (30U)                                           
+#define CAN_F4R2_FB30_Msk      (0x1UL << CAN_F4R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F4R2_FB30          CAN_F4R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F4R2_FB31_Pos      (31U)                                           
+#define CAN_F4R2_FB31_Msk      (0x1UL << CAN_F4R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F4R2_FB31          CAN_F4R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F5R2 register  *******************/
+#define CAN_F5R2_FB0_Pos       (0U)                                            
+#define CAN_F5R2_FB0_Msk       (0x1UL << CAN_F5R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F5R2_FB0           CAN_F5R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F5R2_FB1_Pos       (1U)                                            
+#define CAN_F5R2_FB1_Msk       (0x1UL << CAN_F5R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F5R2_FB1           CAN_F5R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F5R2_FB2_Pos       (2U)                                            
+#define CAN_F5R2_FB2_Msk       (0x1UL << CAN_F5R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F5R2_FB2           CAN_F5R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F5R2_FB3_Pos       (3U)                                            
+#define CAN_F5R2_FB3_Msk       (0x1UL << CAN_F5R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F5R2_FB3           CAN_F5R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F5R2_FB4_Pos       (4U)                                            
+#define CAN_F5R2_FB4_Msk       (0x1UL << CAN_F5R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F5R2_FB4           CAN_F5R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F5R2_FB5_Pos       (5U)                                            
+#define CAN_F5R2_FB5_Msk       (0x1UL << CAN_F5R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F5R2_FB5           CAN_F5R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F5R2_FB6_Pos       (6U)                                            
+#define CAN_F5R2_FB6_Msk       (0x1UL << CAN_F5R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F5R2_FB6           CAN_F5R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F5R2_FB7_Pos       (7U)                                            
+#define CAN_F5R2_FB7_Msk       (0x1UL << CAN_F5R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F5R2_FB7           CAN_F5R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F5R2_FB8_Pos       (8U)                                            
+#define CAN_F5R2_FB8_Msk       (0x1UL << CAN_F5R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F5R2_FB8           CAN_F5R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F5R2_FB9_Pos       (9U)                                            
+#define CAN_F5R2_FB9_Msk       (0x1UL << CAN_F5R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F5R2_FB9           CAN_F5R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F5R2_FB10_Pos      (10U)                                           
+#define CAN_F5R2_FB10_Msk      (0x1UL << CAN_F5R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F5R2_FB10          CAN_F5R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F5R2_FB11_Pos      (11U)                                           
+#define CAN_F5R2_FB11_Msk      (0x1UL << CAN_F5R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F5R2_FB11          CAN_F5R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F5R2_FB12_Pos      (12U)                                           
+#define CAN_F5R2_FB12_Msk      (0x1UL << CAN_F5R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F5R2_FB12          CAN_F5R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F5R2_FB13_Pos      (13U)                                           
+#define CAN_F5R2_FB13_Msk      (0x1UL << CAN_F5R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F5R2_FB13          CAN_F5R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F5R2_FB14_Pos      (14U)                                           
+#define CAN_F5R2_FB14_Msk      (0x1UL << CAN_F5R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F5R2_FB14          CAN_F5R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F5R2_FB15_Pos      (15U)                                           
+#define CAN_F5R2_FB15_Msk      (0x1UL << CAN_F5R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F5R2_FB15          CAN_F5R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F5R2_FB16_Pos      (16U)                                           
+#define CAN_F5R2_FB16_Msk      (0x1UL << CAN_F5R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F5R2_FB16          CAN_F5R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F5R2_FB17_Pos      (17U)                                           
+#define CAN_F5R2_FB17_Msk      (0x1UL << CAN_F5R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F5R2_FB17          CAN_F5R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F5R2_FB18_Pos      (18U)                                           
+#define CAN_F5R2_FB18_Msk      (0x1UL << CAN_F5R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F5R2_FB18          CAN_F5R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F5R2_FB19_Pos      (19U)                                           
+#define CAN_F5R2_FB19_Msk      (0x1UL << CAN_F5R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F5R2_FB19          CAN_F5R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F5R2_FB20_Pos      (20U)                                           
+#define CAN_F5R2_FB20_Msk      (0x1UL << CAN_F5R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F5R2_FB20          CAN_F5R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F5R2_FB21_Pos      (21U)                                           
+#define CAN_F5R2_FB21_Msk      (0x1UL << CAN_F5R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F5R2_FB21          CAN_F5R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F5R2_FB22_Pos      (22U)                                           
+#define CAN_F5R2_FB22_Msk      (0x1UL << CAN_F5R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F5R2_FB22          CAN_F5R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F5R2_FB23_Pos      (23U)                                           
+#define CAN_F5R2_FB23_Msk      (0x1UL << CAN_F5R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F5R2_FB23          CAN_F5R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F5R2_FB24_Pos      (24U)                                           
+#define CAN_F5R2_FB24_Msk      (0x1UL << CAN_F5R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F5R2_FB24          CAN_F5R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F5R2_FB25_Pos      (25U)                                           
+#define CAN_F5R2_FB25_Msk      (0x1UL << CAN_F5R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F5R2_FB25          CAN_F5R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F5R2_FB26_Pos      (26U)                                           
+#define CAN_F5R2_FB26_Msk      (0x1UL << CAN_F5R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F5R2_FB26          CAN_F5R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F5R2_FB27_Pos      (27U)                                           
+#define CAN_F5R2_FB27_Msk      (0x1UL << CAN_F5R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F5R2_FB27          CAN_F5R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F5R2_FB28_Pos      (28U)                                           
+#define CAN_F5R2_FB28_Msk      (0x1UL << CAN_F5R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F5R2_FB28          CAN_F5R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F5R2_FB29_Pos      (29U)                                           
+#define CAN_F5R2_FB29_Msk      (0x1UL << CAN_F5R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F5R2_FB29          CAN_F5R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F5R2_FB30_Pos      (30U)                                           
+#define CAN_F5R2_FB30_Msk      (0x1UL << CAN_F5R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F5R2_FB30          CAN_F5R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F5R2_FB31_Pos      (31U)                                           
+#define CAN_F5R2_FB31_Msk      (0x1UL << CAN_F5R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F5R2_FB31          CAN_F5R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F6R2 register  *******************/
+#define CAN_F6R2_FB0_Pos       (0U)                                            
+#define CAN_F6R2_FB0_Msk       (0x1UL << CAN_F6R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F6R2_FB0           CAN_F6R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F6R2_FB1_Pos       (1U)                                            
+#define CAN_F6R2_FB1_Msk       (0x1UL << CAN_F6R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F6R2_FB1           CAN_F6R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F6R2_FB2_Pos       (2U)                                            
+#define CAN_F6R2_FB2_Msk       (0x1UL << CAN_F6R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F6R2_FB2           CAN_F6R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F6R2_FB3_Pos       (3U)                                            
+#define CAN_F6R2_FB3_Msk       (0x1UL << CAN_F6R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F6R2_FB3           CAN_F6R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F6R2_FB4_Pos       (4U)                                            
+#define CAN_F6R2_FB4_Msk       (0x1UL << CAN_F6R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F6R2_FB4           CAN_F6R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F6R2_FB5_Pos       (5U)                                            
+#define CAN_F6R2_FB5_Msk       (0x1UL << CAN_F6R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F6R2_FB5           CAN_F6R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F6R2_FB6_Pos       (6U)                                            
+#define CAN_F6R2_FB6_Msk       (0x1UL << CAN_F6R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F6R2_FB6           CAN_F6R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F6R2_FB7_Pos       (7U)                                            
+#define CAN_F6R2_FB7_Msk       (0x1UL << CAN_F6R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F6R2_FB7           CAN_F6R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F6R2_FB8_Pos       (8U)                                            
+#define CAN_F6R2_FB8_Msk       (0x1UL << CAN_F6R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F6R2_FB8           CAN_F6R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F6R2_FB9_Pos       (9U)                                            
+#define CAN_F6R2_FB9_Msk       (0x1UL << CAN_F6R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F6R2_FB9           CAN_F6R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F6R2_FB10_Pos      (10U)                                           
+#define CAN_F6R2_FB10_Msk      (0x1UL << CAN_F6R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F6R2_FB10          CAN_F6R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F6R2_FB11_Pos      (11U)                                           
+#define CAN_F6R2_FB11_Msk      (0x1UL << CAN_F6R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F6R2_FB11          CAN_F6R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F6R2_FB12_Pos      (12U)                                           
+#define CAN_F6R2_FB12_Msk      (0x1UL << CAN_F6R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F6R2_FB12          CAN_F6R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F6R2_FB13_Pos      (13U)                                           
+#define CAN_F6R2_FB13_Msk      (0x1UL << CAN_F6R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F6R2_FB13          CAN_F6R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F6R2_FB14_Pos      (14U)                                           
+#define CAN_F6R2_FB14_Msk      (0x1UL << CAN_F6R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F6R2_FB14          CAN_F6R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F6R2_FB15_Pos      (15U)                                           
+#define CAN_F6R2_FB15_Msk      (0x1UL << CAN_F6R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F6R2_FB15          CAN_F6R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F6R2_FB16_Pos      (16U)                                           
+#define CAN_F6R2_FB16_Msk      (0x1UL << CAN_F6R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F6R2_FB16          CAN_F6R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F6R2_FB17_Pos      (17U)                                           
+#define CAN_F6R2_FB17_Msk      (0x1UL << CAN_F6R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F6R2_FB17          CAN_F6R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F6R2_FB18_Pos      (18U)                                           
+#define CAN_F6R2_FB18_Msk      (0x1UL << CAN_F6R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F6R2_FB18          CAN_F6R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F6R2_FB19_Pos      (19U)                                           
+#define CAN_F6R2_FB19_Msk      (0x1UL << CAN_F6R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F6R2_FB19          CAN_F6R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F6R2_FB20_Pos      (20U)                                           
+#define CAN_F6R2_FB20_Msk      (0x1UL << CAN_F6R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F6R2_FB20          CAN_F6R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F6R2_FB21_Pos      (21U)                                           
+#define CAN_F6R2_FB21_Msk      (0x1UL << CAN_F6R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F6R2_FB21          CAN_F6R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F6R2_FB22_Pos      (22U)                                           
+#define CAN_F6R2_FB22_Msk      (0x1UL << CAN_F6R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F6R2_FB22          CAN_F6R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F6R2_FB23_Pos      (23U)                                           
+#define CAN_F6R2_FB23_Msk      (0x1UL << CAN_F6R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F6R2_FB23          CAN_F6R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F6R2_FB24_Pos      (24U)                                           
+#define CAN_F6R2_FB24_Msk      (0x1UL << CAN_F6R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F6R2_FB24          CAN_F6R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F6R2_FB25_Pos      (25U)                                           
+#define CAN_F6R2_FB25_Msk      (0x1UL << CAN_F6R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F6R2_FB25          CAN_F6R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F6R2_FB26_Pos      (26U)                                           
+#define CAN_F6R2_FB26_Msk      (0x1UL << CAN_F6R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F6R2_FB26          CAN_F6R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F6R2_FB27_Pos      (27U)                                           
+#define CAN_F6R2_FB27_Msk      (0x1UL << CAN_F6R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F6R2_FB27          CAN_F6R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F6R2_FB28_Pos      (28U)                                           
+#define CAN_F6R2_FB28_Msk      (0x1UL << CAN_F6R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F6R2_FB28          CAN_F6R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F6R2_FB29_Pos      (29U)                                           
+#define CAN_F6R2_FB29_Msk      (0x1UL << CAN_F6R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F6R2_FB29          CAN_F6R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F6R2_FB30_Pos      (30U)                                           
+#define CAN_F6R2_FB30_Msk      (0x1UL << CAN_F6R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F6R2_FB30          CAN_F6R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F6R2_FB31_Pos      (31U)                                           
+#define CAN_F6R2_FB31_Msk      (0x1UL << CAN_F6R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F6R2_FB31          CAN_F6R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F7R2 register  *******************/
+#define CAN_F7R2_FB0_Pos       (0U)                                            
+#define CAN_F7R2_FB0_Msk       (0x1UL << CAN_F7R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F7R2_FB0           CAN_F7R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F7R2_FB1_Pos       (1U)                                            
+#define CAN_F7R2_FB1_Msk       (0x1UL << CAN_F7R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F7R2_FB1           CAN_F7R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F7R2_FB2_Pos       (2U)                                            
+#define CAN_F7R2_FB2_Msk       (0x1UL << CAN_F7R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F7R2_FB2           CAN_F7R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F7R2_FB3_Pos       (3U)                                            
+#define CAN_F7R2_FB3_Msk       (0x1UL << CAN_F7R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F7R2_FB3           CAN_F7R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F7R2_FB4_Pos       (4U)                                            
+#define CAN_F7R2_FB4_Msk       (0x1UL << CAN_F7R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F7R2_FB4           CAN_F7R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F7R2_FB5_Pos       (5U)                                            
+#define CAN_F7R2_FB5_Msk       (0x1UL << CAN_F7R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F7R2_FB5           CAN_F7R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F7R2_FB6_Pos       (6U)                                            
+#define CAN_F7R2_FB6_Msk       (0x1UL << CAN_F7R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F7R2_FB6           CAN_F7R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F7R2_FB7_Pos       (7U)                                            
+#define CAN_F7R2_FB7_Msk       (0x1UL << CAN_F7R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F7R2_FB7           CAN_F7R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F7R2_FB8_Pos       (8U)                                            
+#define CAN_F7R2_FB8_Msk       (0x1UL << CAN_F7R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F7R2_FB8           CAN_F7R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F7R2_FB9_Pos       (9U)                                            
+#define CAN_F7R2_FB9_Msk       (0x1UL << CAN_F7R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F7R2_FB9           CAN_F7R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F7R2_FB10_Pos      (10U)                                           
+#define CAN_F7R2_FB10_Msk      (0x1UL << CAN_F7R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F7R2_FB10          CAN_F7R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F7R2_FB11_Pos      (11U)                                           
+#define CAN_F7R2_FB11_Msk      (0x1UL << CAN_F7R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F7R2_FB11          CAN_F7R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F7R2_FB12_Pos      (12U)                                           
+#define CAN_F7R2_FB12_Msk      (0x1UL << CAN_F7R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F7R2_FB12          CAN_F7R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F7R2_FB13_Pos      (13U)                                           
+#define CAN_F7R2_FB13_Msk      (0x1UL << CAN_F7R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F7R2_FB13          CAN_F7R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F7R2_FB14_Pos      (14U)                                           
+#define CAN_F7R2_FB14_Msk      (0x1UL << CAN_F7R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F7R2_FB14          CAN_F7R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F7R2_FB15_Pos      (15U)                                           
+#define CAN_F7R2_FB15_Msk      (0x1UL << CAN_F7R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F7R2_FB15          CAN_F7R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F7R2_FB16_Pos      (16U)                                           
+#define CAN_F7R2_FB16_Msk      (0x1UL << CAN_F7R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F7R2_FB16          CAN_F7R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F7R2_FB17_Pos      (17U)                                           
+#define CAN_F7R2_FB17_Msk      (0x1UL << CAN_F7R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F7R2_FB17          CAN_F7R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F7R2_FB18_Pos      (18U)                                           
+#define CAN_F7R2_FB18_Msk      (0x1UL << CAN_F7R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F7R2_FB18          CAN_F7R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F7R2_FB19_Pos      (19U)                                           
+#define CAN_F7R2_FB19_Msk      (0x1UL << CAN_F7R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F7R2_FB19          CAN_F7R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F7R2_FB20_Pos      (20U)                                           
+#define CAN_F7R2_FB20_Msk      (0x1UL << CAN_F7R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F7R2_FB20          CAN_F7R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F7R2_FB21_Pos      (21U)                                           
+#define CAN_F7R2_FB21_Msk      (0x1UL << CAN_F7R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F7R2_FB21          CAN_F7R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F7R2_FB22_Pos      (22U)                                           
+#define CAN_F7R2_FB22_Msk      (0x1UL << CAN_F7R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F7R2_FB22          CAN_F7R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F7R2_FB23_Pos      (23U)                                           
+#define CAN_F7R2_FB23_Msk      (0x1UL << CAN_F7R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F7R2_FB23          CAN_F7R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F7R2_FB24_Pos      (24U)                                           
+#define CAN_F7R2_FB24_Msk      (0x1UL << CAN_F7R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F7R2_FB24          CAN_F7R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F7R2_FB25_Pos      (25U)                                           
+#define CAN_F7R2_FB25_Msk      (0x1UL << CAN_F7R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F7R2_FB25          CAN_F7R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F7R2_FB26_Pos      (26U)                                           
+#define CAN_F7R2_FB26_Msk      (0x1UL << CAN_F7R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F7R2_FB26          CAN_F7R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F7R2_FB27_Pos      (27U)                                           
+#define CAN_F7R2_FB27_Msk      (0x1UL << CAN_F7R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F7R2_FB27          CAN_F7R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F7R2_FB28_Pos      (28U)                                           
+#define CAN_F7R2_FB28_Msk      (0x1UL << CAN_F7R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F7R2_FB28          CAN_F7R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F7R2_FB29_Pos      (29U)                                           
+#define CAN_F7R2_FB29_Msk      (0x1UL << CAN_F7R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F7R2_FB29          CAN_F7R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F7R2_FB30_Pos      (30U)                                           
+#define CAN_F7R2_FB30_Msk      (0x1UL << CAN_F7R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F7R2_FB30          CAN_F7R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F7R2_FB31_Pos      (31U)                                           
+#define CAN_F7R2_FB31_Msk      (0x1UL << CAN_F7R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F7R2_FB31          CAN_F7R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F8R2 register  *******************/
+#define CAN_F8R2_FB0_Pos       (0U)                                            
+#define CAN_F8R2_FB0_Msk       (0x1UL << CAN_F8R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F8R2_FB0           CAN_F8R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F8R2_FB1_Pos       (1U)                                            
+#define CAN_F8R2_FB1_Msk       (0x1UL << CAN_F8R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F8R2_FB1           CAN_F8R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F8R2_FB2_Pos       (2U)                                            
+#define CAN_F8R2_FB2_Msk       (0x1UL << CAN_F8R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F8R2_FB2           CAN_F8R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F8R2_FB3_Pos       (3U)                                            
+#define CAN_F8R2_FB3_Msk       (0x1UL << CAN_F8R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F8R2_FB3           CAN_F8R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F8R2_FB4_Pos       (4U)                                            
+#define CAN_F8R2_FB4_Msk       (0x1UL << CAN_F8R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F8R2_FB4           CAN_F8R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F8R2_FB5_Pos       (5U)                                            
+#define CAN_F8R2_FB5_Msk       (0x1UL << CAN_F8R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F8R2_FB5           CAN_F8R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F8R2_FB6_Pos       (6U)                                            
+#define CAN_F8R2_FB6_Msk       (0x1UL << CAN_F8R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F8R2_FB6           CAN_F8R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F8R2_FB7_Pos       (7U)                                            
+#define CAN_F8R2_FB7_Msk       (0x1UL << CAN_F8R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F8R2_FB7           CAN_F8R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F8R2_FB8_Pos       (8U)                                            
+#define CAN_F8R2_FB8_Msk       (0x1UL << CAN_F8R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F8R2_FB8           CAN_F8R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F8R2_FB9_Pos       (9U)                                            
+#define CAN_F8R2_FB9_Msk       (0x1UL << CAN_F8R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F8R2_FB9           CAN_F8R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F8R2_FB10_Pos      (10U)                                           
+#define CAN_F8R2_FB10_Msk      (0x1UL << CAN_F8R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F8R2_FB10          CAN_F8R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F8R2_FB11_Pos      (11U)                                           
+#define CAN_F8R2_FB11_Msk      (0x1UL << CAN_F8R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F8R2_FB11          CAN_F8R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F8R2_FB12_Pos      (12U)                                           
+#define CAN_F8R2_FB12_Msk      (0x1UL << CAN_F8R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F8R2_FB12          CAN_F8R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F8R2_FB13_Pos      (13U)                                           
+#define CAN_F8R2_FB13_Msk      (0x1UL << CAN_F8R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F8R2_FB13          CAN_F8R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F8R2_FB14_Pos      (14U)                                           
+#define CAN_F8R2_FB14_Msk      (0x1UL << CAN_F8R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F8R2_FB14          CAN_F8R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F8R2_FB15_Pos      (15U)                                           
+#define CAN_F8R2_FB15_Msk      (0x1UL << CAN_F8R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F8R2_FB15          CAN_F8R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F8R2_FB16_Pos      (16U)                                           
+#define CAN_F8R2_FB16_Msk      (0x1UL << CAN_F8R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F8R2_FB16          CAN_F8R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F8R2_FB17_Pos      (17U)                                           
+#define CAN_F8R2_FB17_Msk      (0x1UL << CAN_F8R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F8R2_FB17          CAN_F8R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F8R2_FB18_Pos      (18U)                                           
+#define CAN_F8R2_FB18_Msk      (0x1UL << CAN_F8R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F8R2_FB18          CAN_F8R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F8R2_FB19_Pos      (19U)                                           
+#define CAN_F8R2_FB19_Msk      (0x1UL << CAN_F8R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F8R2_FB19          CAN_F8R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F8R2_FB20_Pos      (20U)                                           
+#define CAN_F8R2_FB20_Msk      (0x1UL << CAN_F8R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F8R2_FB20          CAN_F8R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F8R2_FB21_Pos      (21U)                                           
+#define CAN_F8R2_FB21_Msk      (0x1UL << CAN_F8R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F8R2_FB21          CAN_F8R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F8R2_FB22_Pos      (22U)                                           
+#define CAN_F8R2_FB22_Msk      (0x1UL << CAN_F8R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F8R2_FB22          CAN_F8R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F8R2_FB23_Pos      (23U)                                           
+#define CAN_F8R2_FB23_Msk      (0x1UL << CAN_F8R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F8R2_FB23          CAN_F8R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F8R2_FB24_Pos      (24U)                                           
+#define CAN_F8R2_FB24_Msk      (0x1UL << CAN_F8R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F8R2_FB24          CAN_F8R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F8R2_FB25_Pos      (25U)                                           
+#define CAN_F8R2_FB25_Msk      (0x1UL << CAN_F8R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F8R2_FB25          CAN_F8R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F8R2_FB26_Pos      (26U)                                           
+#define CAN_F8R2_FB26_Msk      (0x1UL << CAN_F8R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F8R2_FB26          CAN_F8R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F8R2_FB27_Pos      (27U)                                           
+#define CAN_F8R2_FB27_Msk      (0x1UL << CAN_F8R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F8R2_FB27          CAN_F8R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F8R2_FB28_Pos      (28U)                                           
+#define CAN_F8R2_FB28_Msk      (0x1UL << CAN_F8R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F8R2_FB28          CAN_F8R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F8R2_FB29_Pos      (29U)                                           
+#define CAN_F8R2_FB29_Msk      (0x1UL << CAN_F8R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F8R2_FB29          CAN_F8R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F8R2_FB30_Pos      (30U)                                           
+#define CAN_F8R2_FB30_Msk      (0x1UL << CAN_F8R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F8R2_FB30          CAN_F8R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F8R2_FB31_Pos      (31U)                                           
+#define CAN_F8R2_FB31_Msk      (0x1UL << CAN_F8R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F8R2_FB31          CAN_F8R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F9R2 register  *******************/
+#define CAN_F9R2_FB0_Pos       (0U)                                            
+#define CAN_F9R2_FB0_Msk       (0x1UL << CAN_F9R2_FB0_Pos)                      /*!< 0x00000001 */
+#define CAN_F9R2_FB0           CAN_F9R2_FB0_Msk                                /*!<Filter bit 0 */
+#define CAN_F9R2_FB1_Pos       (1U)                                            
+#define CAN_F9R2_FB1_Msk       (0x1UL << CAN_F9R2_FB1_Pos)                      /*!< 0x00000002 */
+#define CAN_F9R2_FB1           CAN_F9R2_FB1_Msk                                /*!<Filter bit 1 */
+#define CAN_F9R2_FB2_Pos       (2U)                                            
+#define CAN_F9R2_FB2_Msk       (0x1UL << CAN_F9R2_FB2_Pos)                      /*!< 0x00000004 */
+#define CAN_F9R2_FB2           CAN_F9R2_FB2_Msk                                /*!<Filter bit 2 */
+#define CAN_F9R2_FB3_Pos       (3U)                                            
+#define CAN_F9R2_FB3_Msk       (0x1UL << CAN_F9R2_FB3_Pos)                      /*!< 0x00000008 */
+#define CAN_F9R2_FB3           CAN_F9R2_FB3_Msk                                /*!<Filter bit 3 */
+#define CAN_F9R2_FB4_Pos       (4U)                                            
+#define CAN_F9R2_FB4_Msk       (0x1UL << CAN_F9R2_FB4_Pos)                      /*!< 0x00000010 */
+#define CAN_F9R2_FB4           CAN_F9R2_FB4_Msk                                /*!<Filter bit 4 */
+#define CAN_F9R2_FB5_Pos       (5U)                                            
+#define CAN_F9R2_FB5_Msk       (0x1UL << CAN_F9R2_FB5_Pos)                      /*!< 0x00000020 */
+#define CAN_F9R2_FB5           CAN_F9R2_FB5_Msk                                /*!<Filter bit 5 */
+#define CAN_F9R2_FB6_Pos       (6U)                                            
+#define CAN_F9R2_FB6_Msk       (0x1UL << CAN_F9R2_FB6_Pos)                      /*!< 0x00000040 */
+#define CAN_F9R2_FB6           CAN_F9R2_FB6_Msk                                /*!<Filter bit 6 */
+#define CAN_F9R2_FB7_Pos       (7U)                                            
+#define CAN_F9R2_FB7_Msk       (0x1UL << CAN_F9R2_FB7_Pos)                      /*!< 0x00000080 */
+#define CAN_F9R2_FB7           CAN_F9R2_FB7_Msk                                /*!<Filter bit 7 */
+#define CAN_F9R2_FB8_Pos       (8U)                                            
+#define CAN_F9R2_FB8_Msk       (0x1UL << CAN_F9R2_FB8_Pos)                      /*!< 0x00000100 */
+#define CAN_F9R2_FB8           CAN_F9R2_FB8_Msk                                /*!<Filter bit 8 */
+#define CAN_F9R2_FB9_Pos       (9U)                                            
+#define CAN_F9R2_FB9_Msk       (0x1UL << CAN_F9R2_FB9_Pos)                      /*!< 0x00000200 */
+#define CAN_F9R2_FB9           CAN_F9R2_FB9_Msk                                /*!<Filter bit 9 */
+#define CAN_F9R2_FB10_Pos      (10U)                                           
+#define CAN_F9R2_FB10_Msk      (0x1UL << CAN_F9R2_FB10_Pos)                     /*!< 0x00000400 */
+#define CAN_F9R2_FB10          CAN_F9R2_FB10_Msk                               /*!<Filter bit 10 */
+#define CAN_F9R2_FB11_Pos      (11U)                                           
+#define CAN_F9R2_FB11_Msk      (0x1UL << CAN_F9R2_FB11_Pos)                     /*!< 0x00000800 */
+#define CAN_F9R2_FB11          CAN_F9R2_FB11_Msk                               /*!<Filter bit 11 */
+#define CAN_F9R2_FB12_Pos      (12U)                                           
+#define CAN_F9R2_FB12_Msk      (0x1UL << CAN_F9R2_FB12_Pos)                     /*!< 0x00001000 */
+#define CAN_F9R2_FB12          CAN_F9R2_FB12_Msk                               /*!<Filter bit 12 */
+#define CAN_F9R2_FB13_Pos      (13U)                                           
+#define CAN_F9R2_FB13_Msk      (0x1UL << CAN_F9R2_FB13_Pos)                     /*!< 0x00002000 */
+#define CAN_F9R2_FB13          CAN_F9R2_FB13_Msk                               /*!<Filter bit 13 */
+#define CAN_F9R2_FB14_Pos      (14U)                                           
+#define CAN_F9R2_FB14_Msk      (0x1UL << CAN_F9R2_FB14_Pos)                     /*!< 0x00004000 */
+#define CAN_F9R2_FB14          CAN_F9R2_FB14_Msk                               /*!<Filter bit 14 */
+#define CAN_F9R2_FB15_Pos      (15U)                                           
+#define CAN_F9R2_FB15_Msk      (0x1UL << CAN_F9R2_FB15_Pos)                     /*!< 0x00008000 */
+#define CAN_F9R2_FB15          CAN_F9R2_FB15_Msk                               /*!<Filter bit 15 */
+#define CAN_F9R2_FB16_Pos      (16U)                                           
+#define CAN_F9R2_FB16_Msk      (0x1UL << CAN_F9R2_FB16_Pos)                     /*!< 0x00010000 */
+#define CAN_F9R2_FB16          CAN_F9R2_FB16_Msk                               /*!<Filter bit 16 */
+#define CAN_F9R2_FB17_Pos      (17U)                                           
+#define CAN_F9R2_FB17_Msk      (0x1UL << CAN_F9R2_FB17_Pos)                     /*!< 0x00020000 */
+#define CAN_F9R2_FB17          CAN_F9R2_FB17_Msk                               /*!<Filter bit 17 */
+#define CAN_F9R2_FB18_Pos      (18U)                                           
+#define CAN_F9R2_FB18_Msk      (0x1UL << CAN_F9R2_FB18_Pos)                     /*!< 0x00040000 */
+#define CAN_F9R2_FB18          CAN_F9R2_FB18_Msk                               /*!<Filter bit 18 */
+#define CAN_F9R2_FB19_Pos      (19U)                                           
+#define CAN_F9R2_FB19_Msk      (0x1UL << CAN_F9R2_FB19_Pos)                     /*!< 0x00080000 */
+#define CAN_F9R2_FB19          CAN_F9R2_FB19_Msk                               /*!<Filter bit 19 */
+#define CAN_F9R2_FB20_Pos      (20U)                                           
+#define CAN_F9R2_FB20_Msk      (0x1UL << CAN_F9R2_FB20_Pos)                     /*!< 0x00100000 */
+#define CAN_F9R2_FB20          CAN_F9R2_FB20_Msk                               /*!<Filter bit 20 */
+#define CAN_F9R2_FB21_Pos      (21U)                                           
+#define CAN_F9R2_FB21_Msk      (0x1UL << CAN_F9R2_FB21_Pos)                     /*!< 0x00200000 */
+#define CAN_F9R2_FB21          CAN_F9R2_FB21_Msk                               /*!<Filter bit 21 */
+#define CAN_F9R2_FB22_Pos      (22U)                                           
+#define CAN_F9R2_FB22_Msk      (0x1UL << CAN_F9R2_FB22_Pos)                     /*!< 0x00400000 */
+#define CAN_F9R2_FB22          CAN_F9R2_FB22_Msk                               /*!<Filter bit 22 */
+#define CAN_F9R2_FB23_Pos      (23U)                                           
+#define CAN_F9R2_FB23_Msk      (0x1UL << CAN_F9R2_FB23_Pos)                     /*!< 0x00800000 */
+#define CAN_F9R2_FB23          CAN_F9R2_FB23_Msk                               /*!<Filter bit 23 */
+#define CAN_F9R2_FB24_Pos      (24U)                                           
+#define CAN_F9R2_FB24_Msk      (0x1UL << CAN_F9R2_FB24_Pos)                     /*!< 0x01000000 */
+#define CAN_F9R2_FB24          CAN_F9R2_FB24_Msk                               /*!<Filter bit 24 */
+#define CAN_F9R2_FB25_Pos      (25U)                                           
+#define CAN_F9R2_FB25_Msk      (0x1UL << CAN_F9R2_FB25_Pos)                     /*!< 0x02000000 */
+#define CAN_F9R2_FB25          CAN_F9R2_FB25_Msk                               /*!<Filter bit 25 */
+#define CAN_F9R2_FB26_Pos      (26U)                                           
+#define CAN_F9R2_FB26_Msk      (0x1UL << CAN_F9R2_FB26_Pos)                     /*!< 0x04000000 */
+#define CAN_F9R2_FB26          CAN_F9R2_FB26_Msk                               /*!<Filter bit 26 */
+#define CAN_F9R2_FB27_Pos      (27U)                                           
+#define CAN_F9R2_FB27_Msk      (0x1UL << CAN_F9R2_FB27_Pos)                     /*!< 0x08000000 */
+#define CAN_F9R2_FB27          CAN_F9R2_FB27_Msk                               /*!<Filter bit 27 */
+#define CAN_F9R2_FB28_Pos      (28U)                                           
+#define CAN_F9R2_FB28_Msk      (0x1UL << CAN_F9R2_FB28_Pos)                     /*!< 0x10000000 */
+#define CAN_F9R2_FB28          CAN_F9R2_FB28_Msk                               /*!<Filter bit 28 */
+#define CAN_F9R2_FB29_Pos      (29U)                                           
+#define CAN_F9R2_FB29_Msk      (0x1UL << CAN_F9R2_FB29_Pos)                     /*!< 0x20000000 */
+#define CAN_F9R2_FB29          CAN_F9R2_FB29_Msk                               /*!<Filter bit 29 */
+#define CAN_F9R2_FB30_Pos      (30U)                                           
+#define CAN_F9R2_FB30_Msk      (0x1UL << CAN_F9R2_FB30_Pos)                     /*!< 0x40000000 */
+#define CAN_F9R2_FB30          CAN_F9R2_FB30_Msk                               /*!<Filter bit 30 */
+#define CAN_F9R2_FB31_Pos      (31U)                                           
+#define CAN_F9R2_FB31_Msk      (0x1UL << CAN_F9R2_FB31_Pos)                     /*!< 0x80000000 */
+#define CAN_F9R2_FB31          CAN_F9R2_FB31_Msk                               /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F10R2 register  ******************/
+#define CAN_F10R2_FB0_Pos      (0U)                                            
+#define CAN_F10R2_FB0_Msk      (0x1UL << CAN_F10R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F10R2_FB0          CAN_F10R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F10R2_FB1_Pos      (1U)                                            
+#define CAN_F10R2_FB1_Msk      (0x1UL << CAN_F10R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F10R2_FB1          CAN_F10R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F10R2_FB2_Pos      (2U)                                            
+#define CAN_F10R2_FB2_Msk      (0x1UL << CAN_F10R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F10R2_FB2          CAN_F10R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F10R2_FB3_Pos      (3U)                                            
+#define CAN_F10R2_FB3_Msk      (0x1UL << CAN_F10R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F10R2_FB3          CAN_F10R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F10R2_FB4_Pos      (4U)                                            
+#define CAN_F10R2_FB4_Msk      (0x1UL << CAN_F10R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F10R2_FB4          CAN_F10R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F10R2_FB5_Pos      (5U)                                            
+#define CAN_F10R2_FB5_Msk      (0x1UL << CAN_F10R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F10R2_FB5          CAN_F10R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F10R2_FB6_Pos      (6U)                                            
+#define CAN_F10R2_FB6_Msk      (0x1UL << CAN_F10R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F10R2_FB6          CAN_F10R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F10R2_FB7_Pos      (7U)                                            
+#define CAN_F10R2_FB7_Msk      (0x1UL << CAN_F10R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F10R2_FB7          CAN_F10R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F10R2_FB8_Pos      (8U)                                            
+#define CAN_F10R2_FB8_Msk      (0x1UL << CAN_F10R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F10R2_FB8          CAN_F10R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F10R2_FB9_Pos      (9U)                                            
+#define CAN_F10R2_FB9_Msk      (0x1UL << CAN_F10R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F10R2_FB9          CAN_F10R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F10R2_FB10_Pos     (10U)                                           
+#define CAN_F10R2_FB10_Msk     (0x1UL << CAN_F10R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F10R2_FB10         CAN_F10R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F10R2_FB11_Pos     (11U)                                           
+#define CAN_F10R2_FB11_Msk     (0x1UL << CAN_F10R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F10R2_FB11         CAN_F10R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F10R2_FB12_Pos     (12U)                                           
+#define CAN_F10R2_FB12_Msk     (0x1UL << CAN_F10R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F10R2_FB12         CAN_F10R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F10R2_FB13_Pos     (13U)                                           
+#define CAN_F10R2_FB13_Msk     (0x1UL << CAN_F10R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F10R2_FB13         CAN_F10R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F10R2_FB14_Pos     (14U)                                           
+#define CAN_F10R2_FB14_Msk     (0x1UL << CAN_F10R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F10R2_FB14         CAN_F10R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F10R2_FB15_Pos     (15U)                                           
+#define CAN_F10R2_FB15_Msk     (0x1UL << CAN_F10R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F10R2_FB15         CAN_F10R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F10R2_FB16_Pos     (16U)                                           
+#define CAN_F10R2_FB16_Msk     (0x1UL << CAN_F10R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F10R2_FB16         CAN_F10R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F10R2_FB17_Pos     (17U)                                           
+#define CAN_F10R2_FB17_Msk     (0x1UL << CAN_F10R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F10R2_FB17         CAN_F10R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F10R2_FB18_Pos     (18U)                                           
+#define CAN_F10R2_FB18_Msk     (0x1UL << CAN_F10R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F10R2_FB18         CAN_F10R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F10R2_FB19_Pos     (19U)                                           
+#define CAN_F10R2_FB19_Msk     (0x1UL << CAN_F10R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F10R2_FB19         CAN_F10R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F10R2_FB20_Pos     (20U)                                           
+#define CAN_F10R2_FB20_Msk     (0x1UL << CAN_F10R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F10R2_FB20         CAN_F10R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F10R2_FB21_Pos     (21U)                                           
+#define CAN_F10R2_FB21_Msk     (0x1UL << CAN_F10R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F10R2_FB21         CAN_F10R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F10R2_FB22_Pos     (22U)                                           
+#define CAN_F10R2_FB22_Msk     (0x1UL << CAN_F10R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F10R2_FB22         CAN_F10R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F10R2_FB23_Pos     (23U)                                           
+#define CAN_F10R2_FB23_Msk     (0x1UL << CAN_F10R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F10R2_FB23         CAN_F10R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F10R2_FB24_Pos     (24U)                                           
+#define CAN_F10R2_FB24_Msk     (0x1UL << CAN_F10R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F10R2_FB24         CAN_F10R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F10R2_FB25_Pos     (25U)                                           
+#define CAN_F10R2_FB25_Msk     (0x1UL << CAN_F10R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F10R2_FB25         CAN_F10R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F10R2_FB26_Pos     (26U)                                           
+#define CAN_F10R2_FB26_Msk     (0x1UL << CAN_F10R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F10R2_FB26         CAN_F10R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F10R2_FB27_Pos     (27U)                                           
+#define CAN_F10R2_FB27_Msk     (0x1UL << CAN_F10R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F10R2_FB27         CAN_F10R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F10R2_FB28_Pos     (28U)                                           
+#define CAN_F10R2_FB28_Msk     (0x1UL << CAN_F10R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F10R2_FB28         CAN_F10R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F10R2_FB29_Pos     (29U)                                           
+#define CAN_F10R2_FB29_Msk     (0x1UL << CAN_F10R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F10R2_FB29         CAN_F10R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F10R2_FB30_Pos     (30U)                                           
+#define CAN_F10R2_FB30_Msk     (0x1UL << CAN_F10R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F10R2_FB30         CAN_F10R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F10R2_FB31_Pos     (31U)                                           
+#define CAN_F10R2_FB31_Msk     (0x1UL << CAN_F10R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F10R2_FB31         CAN_F10R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F11R2 register  ******************/
+#define CAN_F11R2_FB0_Pos      (0U)                                            
+#define CAN_F11R2_FB0_Msk      (0x1UL << CAN_F11R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F11R2_FB0          CAN_F11R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F11R2_FB1_Pos      (1U)                                            
+#define CAN_F11R2_FB1_Msk      (0x1UL << CAN_F11R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F11R2_FB1          CAN_F11R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F11R2_FB2_Pos      (2U)                                            
+#define CAN_F11R2_FB2_Msk      (0x1UL << CAN_F11R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F11R2_FB2          CAN_F11R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F11R2_FB3_Pos      (3U)                                            
+#define CAN_F11R2_FB3_Msk      (0x1UL << CAN_F11R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F11R2_FB3          CAN_F11R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F11R2_FB4_Pos      (4U)                                            
+#define CAN_F11R2_FB4_Msk      (0x1UL << CAN_F11R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F11R2_FB4          CAN_F11R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F11R2_FB5_Pos      (5U)                                            
+#define CAN_F11R2_FB5_Msk      (0x1UL << CAN_F11R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F11R2_FB5          CAN_F11R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F11R2_FB6_Pos      (6U)                                            
+#define CAN_F11R2_FB6_Msk      (0x1UL << CAN_F11R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F11R2_FB6          CAN_F11R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F11R2_FB7_Pos      (7U)                                            
+#define CAN_F11R2_FB7_Msk      (0x1UL << CAN_F11R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F11R2_FB7          CAN_F11R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F11R2_FB8_Pos      (8U)                                            
+#define CAN_F11R2_FB8_Msk      (0x1UL << CAN_F11R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F11R2_FB8          CAN_F11R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F11R2_FB9_Pos      (9U)                                            
+#define CAN_F11R2_FB9_Msk      (0x1UL << CAN_F11R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F11R2_FB9          CAN_F11R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F11R2_FB10_Pos     (10U)                                           
+#define CAN_F11R2_FB10_Msk     (0x1UL << CAN_F11R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F11R2_FB10         CAN_F11R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F11R2_FB11_Pos     (11U)                                           
+#define CAN_F11R2_FB11_Msk     (0x1UL << CAN_F11R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F11R2_FB11         CAN_F11R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F11R2_FB12_Pos     (12U)                                           
+#define CAN_F11R2_FB12_Msk     (0x1UL << CAN_F11R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F11R2_FB12         CAN_F11R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F11R2_FB13_Pos     (13U)                                           
+#define CAN_F11R2_FB13_Msk     (0x1UL << CAN_F11R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F11R2_FB13         CAN_F11R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F11R2_FB14_Pos     (14U)                                           
+#define CAN_F11R2_FB14_Msk     (0x1UL << CAN_F11R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F11R2_FB14         CAN_F11R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F11R2_FB15_Pos     (15U)                                           
+#define CAN_F11R2_FB15_Msk     (0x1UL << CAN_F11R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F11R2_FB15         CAN_F11R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F11R2_FB16_Pos     (16U)                                           
+#define CAN_F11R2_FB16_Msk     (0x1UL << CAN_F11R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F11R2_FB16         CAN_F11R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F11R2_FB17_Pos     (17U)                                           
+#define CAN_F11R2_FB17_Msk     (0x1UL << CAN_F11R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F11R2_FB17         CAN_F11R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F11R2_FB18_Pos     (18U)                                           
+#define CAN_F11R2_FB18_Msk     (0x1UL << CAN_F11R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F11R2_FB18         CAN_F11R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F11R2_FB19_Pos     (19U)                                           
+#define CAN_F11R2_FB19_Msk     (0x1UL << CAN_F11R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F11R2_FB19         CAN_F11R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F11R2_FB20_Pos     (20U)                                           
+#define CAN_F11R2_FB20_Msk     (0x1UL << CAN_F11R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F11R2_FB20         CAN_F11R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F11R2_FB21_Pos     (21U)                                           
+#define CAN_F11R2_FB21_Msk     (0x1UL << CAN_F11R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F11R2_FB21         CAN_F11R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F11R2_FB22_Pos     (22U)                                           
+#define CAN_F11R2_FB22_Msk     (0x1UL << CAN_F11R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F11R2_FB22         CAN_F11R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F11R2_FB23_Pos     (23U)                                           
+#define CAN_F11R2_FB23_Msk     (0x1UL << CAN_F11R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F11R2_FB23         CAN_F11R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F11R2_FB24_Pos     (24U)                                           
+#define CAN_F11R2_FB24_Msk     (0x1UL << CAN_F11R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F11R2_FB24         CAN_F11R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F11R2_FB25_Pos     (25U)                                           
+#define CAN_F11R2_FB25_Msk     (0x1UL << CAN_F11R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F11R2_FB25         CAN_F11R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F11R2_FB26_Pos     (26U)                                           
+#define CAN_F11R2_FB26_Msk     (0x1UL << CAN_F11R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F11R2_FB26         CAN_F11R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F11R2_FB27_Pos     (27U)                                           
+#define CAN_F11R2_FB27_Msk     (0x1UL << CAN_F11R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F11R2_FB27         CAN_F11R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F11R2_FB28_Pos     (28U)                                           
+#define CAN_F11R2_FB28_Msk     (0x1UL << CAN_F11R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F11R2_FB28         CAN_F11R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F11R2_FB29_Pos     (29U)                                           
+#define CAN_F11R2_FB29_Msk     (0x1UL << CAN_F11R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F11R2_FB29         CAN_F11R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F11R2_FB30_Pos     (30U)                                           
+#define CAN_F11R2_FB30_Msk     (0x1UL << CAN_F11R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F11R2_FB30         CAN_F11R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F11R2_FB31_Pos     (31U)                                           
+#define CAN_F11R2_FB31_Msk     (0x1UL << CAN_F11R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F11R2_FB31         CAN_F11R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F12R2 register  ******************/
+#define CAN_F12R2_FB0_Pos      (0U)                                            
+#define CAN_F12R2_FB0_Msk      (0x1UL << CAN_F12R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F12R2_FB0          CAN_F12R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F12R2_FB1_Pos      (1U)                                            
+#define CAN_F12R2_FB1_Msk      (0x1UL << CAN_F12R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F12R2_FB1          CAN_F12R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F12R2_FB2_Pos      (2U)                                            
+#define CAN_F12R2_FB2_Msk      (0x1UL << CAN_F12R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F12R2_FB2          CAN_F12R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F12R2_FB3_Pos      (3U)                                            
+#define CAN_F12R2_FB3_Msk      (0x1UL << CAN_F12R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F12R2_FB3          CAN_F12R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F12R2_FB4_Pos      (4U)                                            
+#define CAN_F12R2_FB4_Msk      (0x1UL << CAN_F12R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F12R2_FB4          CAN_F12R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F12R2_FB5_Pos      (5U)                                            
+#define CAN_F12R2_FB5_Msk      (0x1UL << CAN_F12R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F12R2_FB5          CAN_F12R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F12R2_FB6_Pos      (6U)                                            
+#define CAN_F12R2_FB6_Msk      (0x1UL << CAN_F12R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F12R2_FB6          CAN_F12R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F12R2_FB7_Pos      (7U)                                            
+#define CAN_F12R2_FB7_Msk      (0x1UL << CAN_F12R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F12R2_FB7          CAN_F12R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F12R2_FB8_Pos      (8U)                                            
+#define CAN_F12R2_FB8_Msk      (0x1UL << CAN_F12R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F12R2_FB8          CAN_F12R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F12R2_FB9_Pos      (9U)                                            
+#define CAN_F12R2_FB9_Msk      (0x1UL << CAN_F12R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F12R2_FB9          CAN_F12R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F12R2_FB10_Pos     (10U)                                           
+#define CAN_F12R2_FB10_Msk     (0x1UL << CAN_F12R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F12R2_FB10         CAN_F12R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F12R2_FB11_Pos     (11U)                                           
+#define CAN_F12R2_FB11_Msk     (0x1UL << CAN_F12R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F12R2_FB11         CAN_F12R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F12R2_FB12_Pos     (12U)                                           
+#define CAN_F12R2_FB12_Msk     (0x1UL << CAN_F12R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F12R2_FB12         CAN_F12R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F12R2_FB13_Pos     (13U)                                           
+#define CAN_F12R2_FB13_Msk     (0x1UL << CAN_F12R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F12R2_FB13         CAN_F12R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F12R2_FB14_Pos     (14U)                                           
+#define CAN_F12R2_FB14_Msk     (0x1UL << CAN_F12R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F12R2_FB14         CAN_F12R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F12R2_FB15_Pos     (15U)                                           
+#define CAN_F12R2_FB15_Msk     (0x1UL << CAN_F12R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F12R2_FB15         CAN_F12R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F12R2_FB16_Pos     (16U)                                           
+#define CAN_F12R2_FB16_Msk     (0x1UL << CAN_F12R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F12R2_FB16         CAN_F12R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F12R2_FB17_Pos     (17U)                                           
+#define CAN_F12R2_FB17_Msk     (0x1UL << CAN_F12R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F12R2_FB17         CAN_F12R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F12R2_FB18_Pos     (18U)                                           
+#define CAN_F12R2_FB18_Msk     (0x1UL << CAN_F12R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F12R2_FB18         CAN_F12R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F12R2_FB19_Pos     (19U)                                           
+#define CAN_F12R2_FB19_Msk     (0x1UL << CAN_F12R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F12R2_FB19         CAN_F12R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F12R2_FB20_Pos     (20U)                                           
+#define CAN_F12R2_FB20_Msk     (0x1UL << CAN_F12R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F12R2_FB20         CAN_F12R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F12R2_FB21_Pos     (21U)                                           
+#define CAN_F12R2_FB21_Msk     (0x1UL << CAN_F12R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F12R2_FB21         CAN_F12R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F12R2_FB22_Pos     (22U)                                           
+#define CAN_F12R2_FB22_Msk     (0x1UL << CAN_F12R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F12R2_FB22         CAN_F12R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F12R2_FB23_Pos     (23U)                                           
+#define CAN_F12R2_FB23_Msk     (0x1UL << CAN_F12R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F12R2_FB23         CAN_F12R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F12R2_FB24_Pos     (24U)                                           
+#define CAN_F12R2_FB24_Msk     (0x1UL << CAN_F12R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F12R2_FB24         CAN_F12R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F12R2_FB25_Pos     (25U)                                           
+#define CAN_F12R2_FB25_Msk     (0x1UL << CAN_F12R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F12R2_FB25         CAN_F12R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F12R2_FB26_Pos     (26U)                                           
+#define CAN_F12R2_FB26_Msk     (0x1UL << CAN_F12R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F12R2_FB26         CAN_F12R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F12R2_FB27_Pos     (27U)                                           
+#define CAN_F12R2_FB27_Msk     (0x1UL << CAN_F12R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F12R2_FB27         CAN_F12R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F12R2_FB28_Pos     (28U)                                           
+#define CAN_F12R2_FB28_Msk     (0x1UL << CAN_F12R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F12R2_FB28         CAN_F12R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F12R2_FB29_Pos     (29U)                                           
+#define CAN_F12R2_FB29_Msk     (0x1UL << CAN_F12R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F12R2_FB29         CAN_F12R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F12R2_FB30_Pos     (30U)                                           
+#define CAN_F12R2_FB30_Msk     (0x1UL << CAN_F12R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F12R2_FB30         CAN_F12R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F12R2_FB31_Pos     (31U)                                           
+#define CAN_F12R2_FB31_Msk     (0x1UL << CAN_F12R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F12R2_FB31         CAN_F12R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/*******************  Bit definition for CAN_F13R2 register  ******************/
+#define CAN_F13R2_FB0_Pos      (0U)                                            
+#define CAN_F13R2_FB0_Msk      (0x1UL << CAN_F13R2_FB0_Pos)                     /*!< 0x00000001 */
+#define CAN_F13R2_FB0          CAN_F13R2_FB0_Msk                               /*!<Filter bit 0 */
+#define CAN_F13R2_FB1_Pos      (1U)                                            
+#define CAN_F13R2_FB1_Msk      (0x1UL << CAN_F13R2_FB1_Pos)                     /*!< 0x00000002 */
+#define CAN_F13R2_FB1          CAN_F13R2_FB1_Msk                               /*!<Filter bit 1 */
+#define CAN_F13R2_FB2_Pos      (2U)                                            
+#define CAN_F13R2_FB2_Msk      (0x1UL << CAN_F13R2_FB2_Pos)                     /*!< 0x00000004 */
+#define CAN_F13R2_FB2          CAN_F13R2_FB2_Msk                               /*!<Filter bit 2 */
+#define CAN_F13R2_FB3_Pos      (3U)                                            
+#define CAN_F13R2_FB3_Msk      (0x1UL << CAN_F13R2_FB3_Pos)                     /*!< 0x00000008 */
+#define CAN_F13R2_FB3          CAN_F13R2_FB3_Msk                               /*!<Filter bit 3 */
+#define CAN_F13R2_FB4_Pos      (4U)                                            
+#define CAN_F13R2_FB4_Msk      (0x1UL << CAN_F13R2_FB4_Pos)                     /*!< 0x00000010 */
+#define CAN_F13R2_FB4          CAN_F13R2_FB4_Msk                               /*!<Filter bit 4 */
+#define CAN_F13R2_FB5_Pos      (5U)                                            
+#define CAN_F13R2_FB5_Msk      (0x1UL << CAN_F13R2_FB5_Pos)                     /*!< 0x00000020 */
+#define CAN_F13R2_FB5          CAN_F13R2_FB5_Msk                               /*!<Filter bit 5 */
+#define CAN_F13R2_FB6_Pos      (6U)                                            
+#define CAN_F13R2_FB6_Msk      (0x1UL << CAN_F13R2_FB6_Pos)                     /*!< 0x00000040 */
+#define CAN_F13R2_FB6          CAN_F13R2_FB6_Msk                               /*!<Filter bit 6 */
+#define CAN_F13R2_FB7_Pos      (7U)                                            
+#define CAN_F13R2_FB7_Msk      (0x1UL << CAN_F13R2_FB7_Pos)                     /*!< 0x00000080 */
+#define CAN_F13R2_FB7          CAN_F13R2_FB7_Msk                               /*!<Filter bit 7 */
+#define CAN_F13R2_FB8_Pos      (8U)                                            
+#define CAN_F13R2_FB8_Msk      (0x1UL << CAN_F13R2_FB8_Pos)                     /*!< 0x00000100 */
+#define CAN_F13R2_FB8          CAN_F13R2_FB8_Msk                               /*!<Filter bit 8 */
+#define CAN_F13R2_FB9_Pos      (9U)                                            
+#define CAN_F13R2_FB9_Msk      (0x1UL << CAN_F13R2_FB9_Pos)                     /*!< 0x00000200 */
+#define CAN_F13R2_FB9          CAN_F13R2_FB9_Msk                               /*!<Filter bit 9 */
+#define CAN_F13R2_FB10_Pos     (10U)                                           
+#define CAN_F13R2_FB10_Msk     (0x1UL << CAN_F13R2_FB10_Pos)                    /*!< 0x00000400 */
+#define CAN_F13R2_FB10         CAN_F13R2_FB10_Msk                              /*!<Filter bit 10 */
+#define CAN_F13R2_FB11_Pos     (11U)                                           
+#define CAN_F13R2_FB11_Msk     (0x1UL << CAN_F13R2_FB11_Pos)                    /*!< 0x00000800 */
+#define CAN_F13R2_FB11         CAN_F13R2_FB11_Msk                              /*!<Filter bit 11 */
+#define CAN_F13R2_FB12_Pos     (12U)                                           
+#define CAN_F13R2_FB12_Msk     (0x1UL << CAN_F13R2_FB12_Pos)                    /*!< 0x00001000 */
+#define CAN_F13R2_FB12         CAN_F13R2_FB12_Msk                              /*!<Filter bit 12 */
+#define CAN_F13R2_FB13_Pos     (13U)                                           
+#define CAN_F13R2_FB13_Msk     (0x1UL << CAN_F13R2_FB13_Pos)                    /*!< 0x00002000 */
+#define CAN_F13R2_FB13         CAN_F13R2_FB13_Msk                              /*!<Filter bit 13 */
+#define CAN_F13R2_FB14_Pos     (14U)                                           
+#define CAN_F13R2_FB14_Msk     (0x1UL << CAN_F13R2_FB14_Pos)                    /*!< 0x00004000 */
+#define CAN_F13R2_FB14         CAN_F13R2_FB14_Msk                              /*!<Filter bit 14 */
+#define CAN_F13R2_FB15_Pos     (15U)                                           
+#define CAN_F13R2_FB15_Msk     (0x1UL << CAN_F13R2_FB15_Pos)                    /*!< 0x00008000 */
+#define CAN_F13R2_FB15         CAN_F13R2_FB15_Msk                              /*!<Filter bit 15 */
+#define CAN_F13R2_FB16_Pos     (16U)                                           
+#define CAN_F13R2_FB16_Msk     (0x1UL << CAN_F13R2_FB16_Pos)                    /*!< 0x00010000 */
+#define CAN_F13R2_FB16         CAN_F13R2_FB16_Msk                              /*!<Filter bit 16 */
+#define CAN_F13R2_FB17_Pos     (17U)                                           
+#define CAN_F13R2_FB17_Msk     (0x1UL << CAN_F13R2_FB17_Pos)                    /*!< 0x00020000 */
+#define CAN_F13R2_FB17         CAN_F13R2_FB17_Msk                              /*!<Filter bit 17 */
+#define CAN_F13R2_FB18_Pos     (18U)                                           
+#define CAN_F13R2_FB18_Msk     (0x1UL << CAN_F13R2_FB18_Pos)                    /*!< 0x00040000 */
+#define CAN_F13R2_FB18         CAN_F13R2_FB18_Msk                              /*!<Filter bit 18 */
+#define CAN_F13R2_FB19_Pos     (19U)                                           
+#define CAN_F13R2_FB19_Msk     (0x1UL << CAN_F13R2_FB19_Pos)                    /*!< 0x00080000 */
+#define CAN_F13R2_FB19         CAN_F13R2_FB19_Msk                              /*!<Filter bit 19 */
+#define CAN_F13R2_FB20_Pos     (20U)                                           
+#define CAN_F13R2_FB20_Msk     (0x1UL << CAN_F13R2_FB20_Pos)                    /*!< 0x00100000 */
+#define CAN_F13R2_FB20         CAN_F13R2_FB20_Msk                              /*!<Filter bit 20 */
+#define CAN_F13R2_FB21_Pos     (21U)                                           
+#define CAN_F13R2_FB21_Msk     (0x1UL << CAN_F13R2_FB21_Pos)                    /*!< 0x00200000 */
+#define CAN_F13R2_FB21         CAN_F13R2_FB21_Msk                              /*!<Filter bit 21 */
+#define CAN_F13R2_FB22_Pos     (22U)                                           
+#define CAN_F13R2_FB22_Msk     (0x1UL << CAN_F13R2_FB22_Pos)                    /*!< 0x00400000 */
+#define CAN_F13R2_FB22         CAN_F13R2_FB22_Msk                              /*!<Filter bit 22 */
+#define CAN_F13R2_FB23_Pos     (23U)                                           
+#define CAN_F13R2_FB23_Msk     (0x1UL << CAN_F13R2_FB23_Pos)                    /*!< 0x00800000 */
+#define CAN_F13R2_FB23         CAN_F13R2_FB23_Msk                              /*!<Filter bit 23 */
+#define CAN_F13R2_FB24_Pos     (24U)                                           
+#define CAN_F13R2_FB24_Msk     (0x1UL << CAN_F13R2_FB24_Pos)                    /*!< 0x01000000 */
+#define CAN_F13R2_FB24         CAN_F13R2_FB24_Msk                              /*!<Filter bit 24 */
+#define CAN_F13R2_FB25_Pos     (25U)                                           
+#define CAN_F13R2_FB25_Msk     (0x1UL << CAN_F13R2_FB25_Pos)                    /*!< 0x02000000 */
+#define CAN_F13R2_FB25         CAN_F13R2_FB25_Msk                              /*!<Filter bit 25 */
+#define CAN_F13R2_FB26_Pos     (26U)                                           
+#define CAN_F13R2_FB26_Msk     (0x1UL << CAN_F13R2_FB26_Pos)                    /*!< 0x04000000 */
+#define CAN_F13R2_FB26         CAN_F13R2_FB26_Msk                              /*!<Filter bit 26 */
+#define CAN_F13R2_FB27_Pos     (27U)                                           
+#define CAN_F13R2_FB27_Msk     (0x1UL << CAN_F13R2_FB27_Pos)                    /*!< 0x08000000 */
+#define CAN_F13R2_FB27         CAN_F13R2_FB27_Msk                              /*!<Filter bit 27 */
+#define CAN_F13R2_FB28_Pos     (28U)                                           
+#define CAN_F13R2_FB28_Msk     (0x1UL << CAN_F13R2_FB28_Pos)                    /*!< 0x10000000 */
+#define CAN_F13R2_FB28         CAN_F13R2_FB28_Msk                              /*!<Filter bit 28 */
+#define CAN_F13R2_FB29_Pos     (29U)                                           
+#define CAN_F13R2_FB29_Msk     (0x1UL << CAN_F13R2_FB29_Pos)                    /*!< 0x20000000 */
+#define CAN_F13R2_FB29         CAN_F13R2_FB29_Msk                              /*!<Filter bit 29 */
+#define CAN_F13R2_FB30_Pos     (30U)                                           
+#define CAN_F13R2_FB30_Msk     (0x1UL << CAN_F13R2_FB30_Pos)                    /*!< 0x40000000 */
+#define CAN_F13R2_FB30         CAN_F13R2_FB30_Msk                              /*!<Filter bit 30 */
+#define CAN_F13R2_FB31_Pos     (31U)                                           
+#define CAN_F13R2_FB31_Msk     (0x1UL << CAN_F13R2_FB31_Pos)                    /*!< 0x80000000 */
+#define CAN_F13R2_FB31         CAN_F13R2_FB31_Msk                              /*!<Filter bit 31 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                          CRC calculation unit                              */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for CRC_DR register  *********************/
+#define CRC_DR_DR_Pos       (0U)                                               
+#define CRC_DR_DR_Msk       (0xFFFFFFFFUL << CRC_DR_DR_Pos)                     /*!< 0xFFFFFFFF */
+#define CRC_DR_DR           CRC_DR_DR_Msk                                      /*!< Data register bits */
+
+
+/*******************  Bit definition for CRC_IDR register  ********************/
+#define CRC_IDR_IDR_Pos     (0U)                                               
+#define CRC_IDR_IDR_Msk     (0xFFUL << CRC_IDR_IDR_Pos)                         /*!< 0x000000FF */
+#define CRC_IDR_IDR         CRC_IDR_IDR_Msk                                    /*!< General-purpose 8-bit data register bits */
+
+
+/********************  Bit definition for CRC_CR register  ********************/
+#define CRC_CR_RESET_Pos    (0U)                                               
+#define CRC_CR_RESET_Msk    (0x1UL << CRC_CR_RESET_Pos)                         /*!< 0x00000001 */
+#define CRC_CR_RESET        CRC_CR_RESET_Msk                                   /*!< RESET bit */
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Digital to Analog Converter                           */
+/*                                                                            */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define DAC_CHANNEL2_SUPPORT                                    /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
+/********************  Bit definition for DAC_CR register  ********************/
+#define DAC_CR_EN1_Pos              (0U)                                       
+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                   /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+#define DAC_CR_BOFF1_Pos            (1U)                                       
+#define DAC_CR_BOFF1_Msk            (0x1UL << DAC_CR_BOFF1_Pos)                 /*!< 0x00000002 */
+#define DAC_CR_BOFF1                DAC_CR_BOFF1_Msk                           /*!<DAC channel1 output buffer disable */
+#define DAC_CR_TEN1_Pos             (2U)                                       
+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                  /*!< 0x00000004 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (3U)                                       
+#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000038 */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */
+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */
+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */
+
+#define DAC_CR_WAVE1_Pos            (6U)                                       
+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                 /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)                                       
+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)                                      
+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)                /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+#define DAC_CR_DMAUDRIE1_Pos        (13U)                                      
+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)             /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel1 DMA underrun interrupt enable*/
+#define DAC_CR_EN2_Pos              (16U)                                      
+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                   /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+#define DAC_CR_BOFF2_Pos            (17U)                                      
+#define DAC_CR_BOFF2_Msk            (0x1UL << DAC_CR_BOFF2_Pos)                 /*!< 0x00020000 */
+#define DAC_CR_BOFF2                DAC_CR_BOFF2_Msk                           /*!<DAC channel2 output buffer disable */
+#define DAC_CR_TEN2_Pos             (18U)                                      
+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                  /*!< 0x00040000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (19U)                                      
+#define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00380000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */
+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */
+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */
+
+#define DAC_CR_WAVE2_Pos            (22U)                                      
+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)                                      
+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                 /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)                                      
+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)                /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+#define DAC_CR_DMAUDRIE2_Pos        (29U)                                      
+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)             /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable*/
+
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)                                       
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)          /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)                                       
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)          /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)                                       
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)                                       
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)                                       
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)                                       
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)       /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)                                      
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)       /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)                                       
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)       /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)                                      
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)       /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)                                       
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)         /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)                                       
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)         /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)                                       
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)                                       
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)          /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_DMAUDR1_Pos          (13U)                                      
+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)               /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+#define DAC_SR_DMAUDR2_Pos          (29U)                                      
+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)               /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    DCMI                                    */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DCMI_CR register  ******************/
+#define DCMI_CR_CAPTURE_Pos        (0U)                                        
+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)               /*!< 0x00000001 */
+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk                         
+#define DCMI_CR_CM_Pos             (1U)                                        
+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                    /*!< 0x00000002 */
+#define DCMI_CR_CM                 DCMI_CR_CM_Msk                              
+#define DCMI_CR_CROP_Pos           (2U)                                        
+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                  /*!< 0x00000004 */
+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk                            
+#define DCMI_CR_JPEG_Pos           (3U)                                        
+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                  /*!< 0x00000008 */
+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk                            
+#define DCMI_CR_ESS_Pos            (4U)                                        
+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                   /*!< 0x00000010 */
+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk                             
+#define DCMI_CR_PCKPOL_Pos         (5U)                                        
+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)                /*!< 0x00000020 */
+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk                          
+#define DCMI_CR_HSPOL_Pos          (6U)                                        
+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                 /*!< 0x00000040 */
+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk                           
+#define DCMI_CR_VSPOL_Pos          (7U)                                        
+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                 /*!< 0x00000080 */
+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk                           
+#define DCMI_CR_FCRC_0             0x00000100U                                 
+#define DCMI_CR_FCRC_1             0x00000200U                                 
+#define DCMI_CR_EDM_0              0x00000400U                                 
+#define DCMI_CR_EDM_1              0x00000800U                                 
+#define DCMI_CR_CRE_Pos            (12U)                                       
+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                   /*!< 0x00001000 */
+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk                             
+#define DCMI_CR_ENABLE_Pos         (14U)                                       
+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)                /*!< 0x00004000 */
+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk                          
+
+/********************  Bits definition for DCMI_SR register  ******************/
+#define DCMI_SR_HSYNC_Pos          (0U)                                        
+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                 /*!< 0x00000001 */
+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk                           
+#define DCMI_SR_VSYNC_Pos          (1U)                                        
+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                 /*!< 0x00000002 */
+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk                           
+#define DCMI_SR_FNE_Pos            (2U)                                        
+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                   /*!< 0x00000004 */
+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk                             
+
+/********************  Bits definition for DCMI_RIS register  *****************/
+#define DCMI_RIS_FRAME_RIS_Pos     (0U)                                        
+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)            /*!< 0x00000001 */
+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk                      
+#define DCMI_RIS_OVR_RIS_Pos       (1U)                                        
+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)              /*!< 0x00000002 */
+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk                        
+#define DCMI_RIS_ERR_RIS_Pos       (2U)                                        
+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)              /*!< 0x00000004 */
+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk                        
+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)                                        
+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)            /*!< 0x00000008 */
+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk                      
+#define DCMI_RIS_LINE_RIS_Pos      (4U)                                        
+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)             /*!< 0x00000010 */
+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk                       
+/* Legacy defines */
+#define DCMI_RISR_FRAME_RIS                  DCMI_RIS_FRAME_RIS
+#define DCMI_RISR_OVR_RIS                    DCMI_RIS_OVR_RIS
+#define DCMI_RISR_ERR_RIS                    DCMI_RIS_ERR_RIS
+#define DCMI_RISR_VSYNC_RIS                  DCMI_RIS_VSYNC_RIS
+#define DCMI_RISR_LINE_RIS                   DCMI_RIS_LINE_RIS
+#define DCMI_RISR_OVF_RIS                    DCMI_RIS_OVR_RIS
+
+/********************  Bits definition for DCMI_IER register  *****************/
+#define DCMI_IER_FRAME_IE_Pos      (0U)                                        
+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)             /*!< 0x00000001 */
+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk                       
+#define DCMI_IER_OVR_IE_Pos        (1U)                                        
+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)               /*!< 0x00000002 */
+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk                         
+#define DCMI_IER_ERR_IE_Pos        (2U)                                        
+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)               /*!< 0x00000004 */
+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk                         
+#define DCMI_IER_VSYNC_IE_Pos      (3U)                                        
+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)             /*!< 0x00000008 */
+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk                       
+#define DCMI_IER_LINE_IE_Pos       (4U)                                        
+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)              /*!< 0x00000010 */
+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk                        
+/* Legacy defines */
+#define DCMI_IER_OVF_IE                      DCMI_IER_OVR_IE
+
+/********************  Bits definition for DCMI_MIS register  *****************/
+#define DCMI_MIS_FRAME_MIS_Pos     (0U)                                        
+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)            /*!< 0x00000001 */
+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk                      
+#define DCMI_MIS_OVR_MIS_Pos       (1U)                                        
+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)              /*!< 0x00000002 */
+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk                        
+#define DCMI_MIS_ERR_MIS_Pos       (2U)                                        
+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)              /*!< 0x00000004 */
+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk                        
+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)                                        
+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)            /*!< 0x00000008 */
+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk                      
+#define DCMI_MIS_LINE_MIS_Pos      (4U)                                        
+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)             /*!< 0x00000010 */
+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk                       
+
+/* Legacy defines */
+#define DCMI_MISR_FRAME_MIS                  DCMI_MIS_FRAME_MIS
+#define DCMI_MISR_OVF_MIS                    DCMI_MIS_OVR_MIS
+#define DCMI_MISR_ERR_MIS                    DCMI_MIS_ERR_MIS
+#define DCMI_MISR_VSYNC_MIS                  DCMI_MIS_VSYNC_MIS
+#define DCMI_MISR_LINE_MIS                   DCMI_MIS_LINE_MIS
+
+/********************  Bits definition for DCMI_ICR register  *****************/
+#define DCMI_ICR_FRAME_ISC_Pos     (0U)                                        
+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)            /*!< 0x00000001 */
+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk                      
+#define DCMI_ICR_OVR_ISC_Pos       (1U)                                        
+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)              /*!< 0x00000002 */
+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk                        
+#define DCMI_ICR_ERR_ISC_Pos       (2U)                                        
+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)              /*!< 0x00000004 */
+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk                        
+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)                                        
+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)            /*!< 0x00000008 */
+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk                      
+#define DCMI_ICR_LINE_ISC_Pos      (4U)                                        
+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)             /*!< 0x00000010 */
+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk                       
+
+/* Legacy defines */
+#define DCMI_ICR_OVF_ISC                     DCMI_ICR_OVR_ISC
+
+/********************  Bits definition for DCMI_ESCR register  ******************/
+#define DCMI_ESCR_FSC_Pos          (0U)                                        
+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)                /*!< 0x000000FF */
+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk                           
+#define DCMI_ESCR_LSC_Pos          (8U)                                        
+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)                /*!< 0x0000FF00 */
+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk                           
+#define DCMI_ESCR_LEC_Pos          (16U)                                       
+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)                /*!< 0x00FF0000 */
+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk                           
+#define DCMI_ESCR_FEC_Pos          (24U)                                       
+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)                /*!< 0xFF000000 */
+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk                           
+
+/********************  Bits definition for DCMI_ESUR register  ******************/
+#define DCMI_ESUR_FSU_Pos          (0U)                                        
+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)                /*!< 0x000000FF */
+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk                           
+#define DCMI_ESUR_LSU_Pos          (8U)                                        
+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)                /*!< 0x0000FF00 */
+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk                           
+#define DCMI_ESUR_LEU_Pos          (16U)                                       
+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)                /*!< 0x00FF0000 */
+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk                           
+#define DCMI_ESUR_FEU_Pos          (24U)                                       
+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)                /*!< 0xFF000000 */
+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk                           
+
+/********************  Bits definition for DCMI_CWSTRT register  ******************/
+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)                                        
+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)        /*!< 0x00003FFF */
+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk                     
+#define DCMI_CWSTRT_VST_Pos        (16U)                                       
+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)            /*!< 0x1FFF0000 */
+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk                         
+
+/********************  Bits definition for DCMI_CWSIZE register  ******************/
+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)                                        
+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)         /*!< 0x00003FFF */
+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk                      
+#define DCMI_CWSIZE_VLINE_Pos      (16U)                                       
+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)          /*!< 0x3FFF0000 */
+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk                       
+
+/********************  Bits definition for DCMI_DR register  *********************/
+#define DCMI_DR_BYTE0_Pos          (0U)                                        
+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)                /*!< 0x000000FF */
+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk                           
+#define DCMI_DR_BYTE1_Pos          (8U)                                        
+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)                /*!< 0x0000FF00 */
+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk                           
+#define DCMI_DR_BYTE2_Pos          (16U)                                       
+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)                /*!< 0x00FF0000 */
+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk                           
+#define DCMI_DR_BYTE3_Pos          (24U)                                       
+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)                /*!< 0xFF000000 */
+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk                           
+
+/******************************************************************************/
+/*                                                                            */
+/*                             DMA Controller                                 */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for DMA_SxCR register  *****************/
+#define DMA_SxCR_CHSEL_Pos       (25U)                                         
+#define DMA_SxCR_CHSEL_Msk       (0x7UL << DMA_SxCR_CHSEL_Pos)                  /*!< 0x0E000000 */
+#define DMA_SxCR_CHSEL           DMA_SxCR_CHSEL_Msk                            
+#define DMA_SxCR_CHSEL_0         0x02000000U                                   
+#define DMA_SxCR_CHSEL_1         0x04000000U                                   
+#define DMA_SxCR_CHSEL_2         0x08000000U                                   
+#define DMA_SxCR_MBURST_Pos      (23U)                                         
+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01800000 */
+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           
+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */
+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */
+#define DMA_SxCR_PBURST_Pos      (21U)                                         
+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00600000 */
+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           
+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */
+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */
+#define DMA_SxCR_CT_Pos          (19U)                                         
+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                     /*!< 0x00080000 */
+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               
+#define DMA_SxCR_DBM_Pos         (18U)                                         
+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                    /*!< 0x00040000 */
+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              
+#define DMA_SxCR_PL_Pos          (16U)                                         
+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                     /*!< 0x00030000 */
+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               
+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */
+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */
+#define DMA_SxCR_PINCOS_Pos      (15U)                                         
+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                 /*!< 0x00008000 */
+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           
+#define DMA_SxCR_MSIZE_Pos       (13U)                                         
+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00006000 */
+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            
+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */
+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */
+#define DMA_SxCR_PSIZE_Pos       (11U)                                         
+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001800 */
+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            
+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */
+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */
+#define DMA_SxCR_MINC_Pos        (10U)                                         
+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                   /*!< 0x00000400 */
+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             
+#define DMA_SxCR_PINC_Pos        (9U)                                          
+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                   /*!< 0x00000200 */
+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             
+#define DMA_SxCR_CIRC_Pos        (8U)                                          
+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                   /*!< 0x00000100 */
+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             
+#define DMA_SxCR_DIR_Pos         (6U)                                          
+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                    /*!< 0x000000C0 */
+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              
+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */
+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */
+#define DMA_SxCR_PFCTRL_Pos      (5U)                                          
+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                 /*!< 0x00000020 */
+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           
+#define DMA_SxCR_TCIE_Pos        (4U)                                          
+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                   /*!< 0x00000010 */
+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             
+#define DMA_SxCR_HTIE_Pos        (3U)                                          
+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                   /*!< 0x00000008 */
+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             
+#define DMA_SxCR_TEIE_Pos        (2U)                                          
+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                   /*!< 0x00000004 */
+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             
+#define DMA_SxCR_DMEIE_Pos       (1U)                                          
+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                  /*!< 0x00000002 */
+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            
+#define DMA_SxCR_EN_Pos          (0U)                                          
+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                     /*!< 0x00000001 */
+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               
+
+/* Legacy defines */
+#define DMA_SxCR_ACK_Pos         (20U)                                         
+#define DMA_SxCR_ACK_Msk         (0x1UL << DMA_SxCR_ACK_Pos)                    /*!< 0x00100000 */
+#define DMA_SxCR_ACK             DMA_SxCR_ACK_Msk                              
+
+/********************  Bits definition for DMA_SxCNDTR register  **************/
+#define DMA_SxNDT_Pos            (0U)                                          
+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                    /*!< 0x0000FFFF */
+#define DMA_SxNDT                DMA_SxNDT_Msk                                 
+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */
+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */
+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */
+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */
+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */
+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */
+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */
+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */
+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */
+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */
+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */
+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */
+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */
+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */
+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */
+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */
+
+/********************  Bits definition for DMA_SxFCR register  ****************/ 
+#define DMA_SxFCR_FEIE_Pos       (7U)                                          
+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                  /*!< 0x00000080 */
+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            
+#define DMA_SxFCR_FS_Pos         (3U)                                          
+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000038 */
+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              
+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */
+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */
+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */
+#define DMA_SxFCR_DMDIS_Pos      (2U)                                          
+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                 /*!< 0x00000004 */
+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           
+#define DMA_SxFCR_FTH_Pos        (0U)                                          
+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000003 */
+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             
+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */
+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */
+
+/********************  Bits definition for DMA_LISR register  *****************/ 
+#define DMA_LISR_TCIF3_Pos       (27U)                                         
+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                  /*!< 0x08000000 */
+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            
+#define DMA_LISR_HTIF3_Pos       (26U)                                         
+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                  /*!< 0x04000000 */
+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            
+#define DMA_LISR_TEIF3_Pos       (25U)                                         
+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                  /*!< 0x02000000 */
+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            
+#define DMA_LISR_DMEIF3_Pos      (24U)                                         
+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                 /*!< 0x01000000 */
+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           
+#define DMA_LISR_FEIF3_Pos       (22U)                                         
+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                  /*!< 0x00400000 */
+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            
+#define DMA_LISR_TCIF2_Pos       (21U)                                         
+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                  /*!< 0x00200000 */
+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            
+#define DMA_LISR_HTIF2_Pos       (20U)                                         
+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                  /*!< 0x00100000 */
+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            
+#define DMA_LISR_TEIF2_Pos       (19U)                                         
+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                  /*!< 0x00080000 */
+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            
+#define DMA_LISR_DMEIF2_Pos      (18U)                                         
+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                 /*!< 0x00040000 */
+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           
+#define DMA_LISR_FEIF2_Pos       (16U)                                         
+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                  /*!< 0x00010000 */
+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            
+#define DMA_LISR_TCIF1_Pos       (11U)                                         
+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                  /*!< 0x00000800 */
+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            
+#define DMA_LISR_HTIF1_Pos       (10U)                                         
+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                  /*!< 0x00000400 */
+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            
+#define DMA_LISR_TEIF1_Pos       (9U)                                          
+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                  /*!< 0x00000200 */
+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            
+#define DMA_LISR_DMEIF1_Pos      (8U)                                          
+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                 /*!< 0x00000100 */
+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           
+#define DMA_LISR_FEIF1_Pos       (6U)                                          
+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                  /*!< 0x00000040 */
+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            
+#define DMA_LISR_TCIF0_Pos       (5U)                                          
+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                  /*!< 0x00000020 */
+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            
+#define DMA_LISR_HTIF0_Pos       (4U)                                          
+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                  /*!< 0x00000010 */
+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            
+#define DMA_LISR_TEIF0_Pos       (3U)                                          
+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                  /*!< 0x00000008 */
+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            
+#define DMA_LISR_DMEIF0_Pos      (2U)                                          
+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                 /*!< 0x00000004 */
+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           
+#define DMA_LISR_FEIF0_Pos       (0U)                                          
+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                  /*!< 0x00000001 */
+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            
+
+/********************  Bits definition for DMA_HISR register  *****************/ 
+#define DMA_HISR_TCIF7_Pos       (27U)                                         
+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                  /*!< 0x08000000 */
+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            
+#define DMA_HISR_HTIF7_Pos       (26U)                                         
+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                  /*!< 0x04000000 */
+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            
+#define DMA_HISR_TEIF7_Pos       (25U)                                         
+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                  /*!< 0x02000000 */
+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            
+#define DMA_HISR_DMEIF7_Pos      (24U)                                         
+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                 /*!< 0x01000000 */
+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           
+#define DMA_HISR_FEIF7_Pos       (22U)                                         
+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                  /*!< 0x00400000 */
+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            
+#define DMA_HISR_TCIF6_Pos       (21U)                                         
+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                  /*!< 0x00200000 */
+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            
+#define DMA_HISR_HTIF6_Pos       (20U)                                         
+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                  /*!< 0x00100000 */
+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            
+#define DMA_HISR_TEIF6_Pos       (19U)                                         
+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                  /*!< 0x00080000 */
+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            
+#define DMA_HISR_DMEIF6_Pos      (18U)                                         
+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                 /*!< 0x00040000 */
+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           
+#define DMA_HISR_FEIF6_Pos       (16U)                                         
+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                  /*!< 0x00010000 */
+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            
+#define DMA_HISR_TCIF5_Pos       (11U)                                         
+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                  /*!< 0x00000800 */
+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            
+#define DMA_HISR_HTIF5_Pos       (10U)                                         
+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                  /*!< 0x00000400 */
+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            
+#define DMA_HISR_TEIF5_Pos       (9U)                                          
+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                  /*!< 0x00000200 */
+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            
+#define DMA_HISR_DMEIF5_Pos      (8U)                                          
+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                 /*!< 0x00000100 */
+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           
+#define DMA_HISR_FEIF5_Pos       (6U)                                          
+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                  /*!< 0x00000040 */
+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            
+#define DMA_HISR_TCIF4_Pos       (5U)                                          
+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                  /*!< 0x00000020 */
+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            
+#define DMA_HISR_HTIF4_Pos       (4U)                                          
+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                  /*!< 0x00000010 */
+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            
+#define DMA_HISR_TEIF4_Pos       (3U)                                          
+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                  /*!< 0x00000008 */
+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            
+#define DMA_HISR_DMEIF4_Pos      (2U)                                          
+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                 /*!< 0x00000004 */
+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           
+#define DMA_HISR_FEIF4_Pos       (0U)                                          
+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                  /*!< 0x00000001 */
+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            
+
+/********************  Bits definition for DMA_LIFCR register  ****************/ 
+#define DMA_LIFCR_CTCIF3_Pos     (27U)                                         
+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)                /*!< 0x08000000 */
+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          
+#define DMA_LIFCR_CHTIF3_Pos     (26U)                                         
+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)                /*!< 0x04000000 */
+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          
+#define DMA_LIFCR_CTEIF3_Pos     (25U)                                         
+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)                /*!< 0x02000000 */
+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          
+#define DMA_LIFCR_CDMEIF3_Pos    (24U)                                         
+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)               /*!< 0x01000000 */
+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         
+#define DMA_LIFCR_CFEIF3_Pos     (22U)                                         
+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)                /*!< 0x00400000 */
+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          
+#define DMA_LIFCR_CTCIF2_Pos     (21U)                                         
+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)                /*!< 0x00200000 */
+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          
+#define DMA_LIFCR_CHTIF2_Pos     (20U)                                         
+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)                /*!< 0x00100000 */
+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          
+#define DMA_LIFCR_CTEIF2_Pos     (19U)                                         
+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)                /*!< 0x00080000 */
+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          
+#define DMA_LIFCR_CDMEIF2_Pos    (18U)                                         
+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)               /*!< 0x00040000 */
+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         
+#define DMA_LIFCR_CFEIF2_Pos     (16U)                                         
+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)                /*!< 0x00010000 */
+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          
+#define DMA_LIFCR_CTCIF1_Pos     (11U)                                         
+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)                /*!< 0x00000800 */
+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          
+#define DMA_LIFCR_CHTIF1_Pos     (10U)                                         
+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)                /*!< 0x00000400 */
+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          
+#define DMA_LIFCR_CTEIF1_Pos     (9U)                                          
+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)                /*!< 0x00000200 */
+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          
+#define DMA_LIFCR_CDMEIF1_Pos    (8U)                                          
+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)               /*!< 0x00000100 */
+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         
+#define DMA_LIFCR_CFEIF1_Pos     (6U)                                          
+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)                /*!< 0x00000040 */
+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          
+#define DMA_LIFCR_CTCIF0_Pos     (5U)                                          
+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)                /*!< 0x00000020 */
+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          
+#define DMA_LIFCR_CHTIF0_Pos     (4U)                                          
+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)                /*!< 0x00000010 */
+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          
+#define DMA_LIFCR_CTEIF0_Pos     (3U)                                          
+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)                /*!< 0x00000008 */
+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          
+#define DMA_LIFCR_CDMEIF0_Pos    (2U)                                          
+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)               /*!< 0x00000004 */
+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         
+#define DMA_LIFCR_CFEIF0_Pos     (0U)                                          
+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)                /*!< 0x00000001 */
+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          
+
+/********************  Bits definition for DMA_HIFCR  register  ****************/ 
+#define DMA_HIFCR_CTCIF7_Pos     (27U)                                         
+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)                /*!< 0x08000000 */
+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          
+#define DMA_HIFCR_CHTIF7_Pos     (26U)                                         
+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)                /*!< 0x04000000 */
+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          
+#define DMA_HIFCR_CTEIF7_Pos     (25U)                                         
+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)                /*!< 0x02000000 */
+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          
+#define DMA_HIFCR_CDMEIF7_Pos    (24U)                                         
+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)               /*!< 0x01000000 */
+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         
+#define DMA_HIFCR_CFEIF7_Pos     (22U)                                         
+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)                /*!< 0x00400000 */
+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          
+#define DMA_HIFCR_CTCIF6_Pos     (21U)                                         
+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)                /*!< 0x00200000 */
+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          
+#define DMA_HIFCR_CHTIF6_Pos     (20U)                                         
+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)                /*!< 0x00100000 */
+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          
+#define DMA_HIFCR_CTEIF6_Pos     (19U)                                         
+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)                /*!< 0x00080000 */
+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          
+#define DMA_HIFCR_CDMEIF6_Pos    (18U)                                         
+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)               /*!< 0x00040000 */
+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         
+#define DMA_HIFCR_CFEIF6_Pos     (16U)                                         
+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)                /*!< 0x00010000 */
+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          
+#define DMA_HIFCR_CTCIF5_Pos     (11U)                                         
+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)                /*!< 0x00000800 */
+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          
+#define DMA_HIFCR_CHTIF5_Pos     (10U)                                         
+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)                /*!< 0x00000400 */
+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          
+#define DMA_HIFCR_CTEIF5_Pos     (9U)                                          
+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)                /*!< 0x00000200 */
+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          
+#define DMA_HIFCR_CDMEIF5_Pos    (8U)                                          
+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)               /*!< 0x00000100 */
+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         
+#define DMA_HIFCR_CFEIF5_Pos     (6U)                                          
+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)                /*!< 0x00000040 */
+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          
+#define DMA_HIFCR_CTCIF4_Pos     (5U)                                          
+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)                /*!< 0x00000020 */
+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          
+#define DMA_HIFCR_CHTIF4_Pos     (4U)                                          
+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)                /*!< 0x00000010 */
+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          
+#define DMA_HIFCR_CTEIF4_Pos     (3U)                                          
+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)                /*!< 0x00000008 */
+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          
+#define DMA_HIFCR_CDMEIF4_Pos    (2U)                                          
+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)               /*!< 0x00000004 */
+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         
+#define DMA_HIFCR_CFEIF4_Pos     (0U)                                          
+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)                /*!< 0x00000001 */
+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          
+
+/******************  Bit definition for DMA_SxPAR register  ********************/
+#define DMA_SxPAR_PA_Pos         (0U)                                          
+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)             /*!< 0xFFFFFFFF */
+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */
+
+/******************  Bit definition for DMA_SxM0AR register  ********************/
+#define DMA_SxM0AR_M0A_Pos       (0U)                                          
+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)           /*!< 0xFFFFFFFF */
+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory Address */
+
+/******************  Bit definition for DMA_SxM1AR register  ********************/
+#define DMA_SxM1AR_M1A_Pos       (0U)                                          
+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)           /*!< 0xFFFFFFFF */
+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory Address */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                    External Interrupt/Event Controller                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for EXTI_IMR register  *******************/
+#define EXTI_IMR_MR0_Pos          (0U)                                         
+#define EXTI_IMR_MR0_Msk          (0x1UL << EXTI_IMR_MR0_Pos)                   /*!< 0x00000001 */
+#define EXTI_IMR_MR0              EXTI_IMR_MR0_Msk                             /*!< Interrupt Mask on line 0 */
+#define EXTI_IMR_MR1_Pos          (1U)                                         
+#define EXTI_IMR_MR1_Msk          (0x1UL << EXTI_IMR_MR1_Pos)                   /*!< 0x00000002 */
+#define EXTI_IMR_MR1              EXTI_IMR_MR1_Msk                             /*!< Interrupt Mask on line 1 */
+#define EXTI_IMR_MR2_Pos          (2U)                                         
+#define EXTI_IMR_MR2_Msk          (0x1UL << EXTI_IMR_MR2_Pos)                   /*!< 0x00000004 */
+#define EXTI_IMR_MR2              EXTI_IMR_MR2_Msk                             /*!< Interrupt Mask on line 2 */
+#define EXTI_IMR_MR3_Pos          (3U)                                         
+#define EXTI_IMR_MR3_Msk          (0x1UL << EXTI_IMR_MR3_Pos)                   /*!< 0x00000008 */
+#define EXTI_IMR_MR3              EXTI_IMR_MR3_Msk                             /*!< Interrupt Mask on line 3 */
+#define EXTI_IMR_MR4_Pos          (4U)                                         
+#define EXTI_IMR_MR4_Msk          (0x1UL << EXTI_IMR_MR4_Pos)                   /*!< 0x00000010 */
+#define EXTI_IMR_MR4              EXTI_IMR_MR4_Msk                             /*!< Interrupt Mask on line 4 */
+#define EXTI_IMR_MR5_Pos          (5U)                                         
+#define EXTI_IMR_MR5_Msk          (0x1UL << EXTI_IMR_MR5_Pos)                   /*!< 0x00000020 */
+#define EXTI_IMR_MR5              EXTI_IMR_MR5_Msk                             /*!< Interrupt Mask on line 5 */
+#define EXTI_IMR_MR6_Pos          (6U)                                         
+#define EXTI_IMR_MR6_Msk          (0x1UL << EXTI_IMR_MR6_Pos)                   /*!< 0x00000040 */
+#define EXTI_IMR_MR6              EXTI_IMR_MR6_Msk                             /*!< Interrupt Mask on line 6 */
+#define EXTI_IMR_MR7_Pos          (7U)                                         
+#define EXTI_IMR_MR7_Msk          (0x1UL << EXTI_IMR_MR7_Pos)                   /*!< 0x00000080 */
+#define EXTI_IMR_MR7              EXTI_IMR_MR7_Msk                             /*!< Interrupt Mask on line 7 */
+#define EXTI_IMR_MR8_Pos          (8U)                                         
+#define EXTI_IMR_MR8_Msk          (0x1UL << EXTI_IMR_MR8_Pos)                   /*!< 0x00000100 */
+#define EXTI_IMR_MR8              EXTI_IMR_MR8_Msk                             /*!< Interrupt Mask on line 8 */
+#define EXTI_IMR_MR9_Pos          (9U)                                         
+#define EXTI_IMR_MR9_Msk          (0x1UL << EXTI_IMR_MR9_Pos)                   /*!< 0x00000200 */
+#define EXTI_IMR_MR9              EXTI_IMR_MR9_Msk                             /*!< Interrupt Mask on line 9 */
+#define EXTI_IMR_MR10_Pos         (10U)                                        
+#define EXTI_IMR_MR10_Msk         (0x1UL << EXTI_IMR_MR10_Pos)                  /*!< 0x00000400 */
+#define EXTI_IMR_MR10             EXTI_IMR_MR10_Msk                            /*!< Interrupt Mask on line 10 */
+#define EXTI_IMR_MR11_Pos         (11U)                                        
+#define EXTI_IMR_MR11_Msk         (0x1UL << EXTI_IMR_MR11_Pos)                  /*!< 0x00000800 */
+#define EXTI_IMR_MR11             EXTI_IMR_MR11_Msk                            /*!< Interrupt Mask on line 11 */
+#define EXTI_IMR_MR12_Pos         (12U)                                        
+#define EXTI_IMR_MR12_Msk         (0x1UL << EXTI_IMR_MR12_Pos)                  /*!< 0x00001000 */
+#define EXTI_IMR_MR12             EXTI_IMR_MR12_Msk                            /*!< Interrupt Mask on line 12 */
+#define EXTI_IMR_MR13_Pos         (13U)                                        
+#define EXTI_IMR_MR13_Msk         (0x1UL << EXTI_IMR_MR13_Pos)                  /*!< 0x00002000 */
+#define EXTI_IMR_MR13             EXTI_IMR_MR13_Msk                            /*!< Interrupt Mask on line 13 */
+#define EXTI_IMR_MR14_Pos         (14U)                                        
+#define EXTI_IMR_MR14_Msk         (0x1UL << EXTI_IMR_MR14_Pos)                  /*!< 0x00004000 */
+#define EXTI_IMR_MR14             EXTI_IMR_MR14_Msk                            /*!< Interrupt Mask on line 14 */
+#define EXTI_IMR_MR15_Pos         (15U)                                        
+#define EXTI_IMR_MR15_Msk         (0x1UL << EXTI_IMR_MR15_Pos)                  /*!< 0x00008000 */
+#define EXTI_IMR_MR15             EXTI_IMR_MR15_Msk                            /*!< Interrupt Mask on line 15 */
+#define EXTI_IMR_MR16_Pos         (16U)                                        
+#define EXTI_IMR_MR16_Msk         (0x1UL << EXTI_IMR_MR16_Pos)                  /*!< 0x00010000 */
+#define EXTI_IMR_MR16             EXTI_IMR_MR16_Msk                            /*!< Interrupt Mask on line 16 */
+#define EXTI_IMR_MR17_Pos         (17U)                                        
+#define EXTI_IMR_MR17_Msk         (0x1UL << EXTI_IMR_MR17_Pos)                  /*!< 0x00020000 */
+#define EXTI_IMR_MR17             EXTI_IMR_MR17_Msk                            /*!< Interrupt Mask on line 17 */
+#define EXTI_IMR_MR18_Pos         (18U)                                        
+#define EXTI_IMR_MR18_Msk         (0x1UL << EXTI_IMR_MR18_Pos)                  /*!< 0x00040000 */
+#define EXTI_IMR_MR18             EXTI_IMR_MR18_Msk                            /*!< Interrupt Mask on line 18 */
+#define EXTI_IMR_MR19_Pos         (19U)                                        
+#define EXTI_IMR_MR19_Msk         (0x1UL << EXTI_IMR_MR19_Pos)                  /*!< 0x00080000 */
+#define EXTI_IMR_MR19             EXTI_IMR_MR19_Msk                            /*!< Interrupt Mask on line 19 */
+#define EXTI_IMR_MR20_Pos         (20U)                                        
+#define EXTI_IMR_MR20_Msk         (0x1UL << EXTI_IMR_MR20_Pos)                  /*!< 0x00100000 */
+#define EXTI_IMR_MR20             EXTI_IMR_MR20_Msk                            /*!< Interrupt Mask on line 20 */
+#define EXTI_IMR_MR21_Pos         (21U)                                        
+#define EXTI_IMR_MR21_Msk         (0x1UL << EXTI_IMR_MR21_Pos)                  /*!< 0x00200000 */
+#define EXTI_IMR_MR21             EXTI_IMR_MR21_Msk                            /*!< Interrupt Mask on line 21 */
+#define EXTI_IMR_MR22_Pos         (22U)                                        
+#define EXTI_IMR_MR22_Msk         (0x1UL << EXTI_IMR_MR22_Pos)                  /*!< 0x00400000 */
+#define EXTI_IMR_MR22             EXTI_IMR_MR22_Msk                            /*!< Interrupt Mask on line 22 */
+
+/* Reference Defines */
+#define  EXTI_IMR_IM0                        EXTI_IMR_MR0
+#define  EXTI_IMR_IM1                        EXTI_IMR_MR1
+#define  EXTI_IMR_IM2                        EXTI_IMR_MR2
+#define  EXTI_IMR_IM3                        EXTI_IMR_MR3
+#define  EXTI_IMR_IM4                        EXTI_IMR_MR4
+#define  EXTI_IMR_IM5                        EXTI_IMR_MR5
+#define  EXTI_IMR_IM6                        EXTI_IMR_MR6
+#define  EXTI_IMR_IM7                        EXTI_IMR_MR7
+#define  EXTI_IMR_IM8                        EXTI_IMR_MR8
+#define  EXTI_IMR_IM9                        EXTI_IMR_MR9
+#define  EXTI_IMR_IM10                       EXTI_IMR_MR10
+#define  EXTI_IMR_IM11                       EXTI_IMR_MR11
+#define  EXTI_IMR_IM12                       EXTI_IMR_MR12
+#define  EXTI_IMR_IM13                       EXTI_IMR_MR13
+#define  EXTI_IMR_IM14                       EXTI_IMR_MR14
+#define  EXTI_IMR_IM15                       EXTI_IMR_MR15
+#define  EXTI_IMR_IM16                       EXTI_IMR_MR16
+#define  EXTI_IMR_IM17                       EXTI_IMR_MR17
+#define  EXTI_IMR_IM18                       EXTI_IMR_MR18
+#define  EXTI_IMR_IM19                       EXTI_IMR_MR19
+#define  EXTI_IMR_IM20                       EXTI_IMR_MR20
+#define  EXTI_IMR_IM21                       EXTI_IMR_MR21
+#define  EXTI_IMR_IM22                       EXTI_IMR_MR22
+#define EXTI_IMR_IM_Pos           (0U)                                         
+#define EXTI_IMR_IM_Msk           (0x7FFFFFUL << EXTI_IMR_IM_Pos)               /*!< 0x007FFFFF */
+#define EXTI_IMR_IM               EXTI_IMR_IM_Msk                              /*!< Interrupt Mask All */
+
+/*******************  Bit definition for EXTI_EMR register  *******************/
+#define EXTI_EMR_MR0_Pos          (0U)                                         
+#define EXTI_EMR_MR0_Msk          (0x1UL << EXTI_EMR_MR0_Pos)                   /*!< 0x00000001 */
+#define EXTI_EMR_MR0              EXTI_EMR_MR0_Msk                             /*!< Event Mask on line 0 */
+#define EXTI_EMR_MR1_Pos          (1U)                                         
+#define EXTI_EMR_MR1_Msk          (0x1UL << EXTI_EMR_MR1_Pos)                   /*!< 0x00000002 */
+#define EXTI_EMR_MR1              EXTI_EMR_MR1_Msk                             /*!< Event Mask on line 1 */
+#define EXTI_EMR_MR2_Pos          (2U)                                         
+#define EXTI_EMR_MR2_Msk          (0x1UL << EXTI_EMR_MR2_Pos)                   /*!< 0x00000004 */
+#define EXTI_EMR_MR2              EXTI_EMR_MR2_Msk                             /*!< Event Mask on line 2 */
+#define EXTI_EMR_MR3_Pos          (3U)                                         
+#define EXTI_EMR_MR3_Msk          (0x1UL << EXTI_EMR_MR3_Pos)                   /*!< 0x00000008 */
+#define EXTI_EMR_MR3              EXTI_EMR_MR3_Msk                             /*!< Event Mask on line 3 */
+#define EXTI_EMR_MR4_Pos          (4U)                                         
+#define EXTI_EMR_MR4_Msk          (0x1UL << EXTI_EMR_MR4_Pos)                   /*!< 0x00000010 */
+#define EXTI_EMR_MR4              EXTI_EMR_MR4_Msk                             /*!< Event Mask on line 4 */
+#define EXTI_EMR_MR5_Pos          (5U)                                         
+#define EXTI_EMR_MR5_Msk          (0x1UL << EXTI_EMR_MR5_Pos)                   /*!< 0x00000020 */
+#define EXTI_EMR_MR5              EXTI_EMR_MR5_Msk                             /*!< Event Mask on line 5 */
+#define EXTI_EMR_MR6_Pos          (6U)                                         
+#define EXTI_EMR_MR6_Msk          (0x1UL << EXTI_EMR_MR6_Pos)                   /*!< 0x00000040 */
+#define EXTI_EMR_MR6              EXTI_EMR_MR6_Msk                             /*!< Event Mask on line 6 */
+#define EXTI_EMR_MR7_Pos          (7U)                                         
+#define EXTI_EMR_MR7_Msk          (0x1UL << EXTI_EMR_MR7_Pos)                   /*!< 0x00000080 */
+#define EXTI_EMR_MR7              EXTI_EMR_MR7_Msk                             /*!< Event Mask on line 7 */
+#define EXTI_EMR_MR8_Pos          (8U)                                         
+#define EXTI_EMR_MR8_Msk          (0x1UL << EXTI_EMR_MR8_Pos)                   /*!< 0x00000100 */
+#define EXTI_EMR_MR8              EXTI_EMR_MR8_Msk                             /*!< Event Mask on line 8 */
+#define EXTI_EMR_MR9_Pos          (9U)                                         
+#define EXTI_EMR_MR9_Msk          (0x1UL << EXTI_EMR_MR9_Pos)                   /*!< 0x00000200 */
+#define EXTI_EMR_MR9              EXTI_EMR_MR9_Msk                             /*!< Event Mask on line 9 */
+#define EXTI_EMR_MR10_Pos         (10U)                                        
+#define EXTI_EMR_MR10_Msk         (0x1UL << EXTI_EMR_MR10_Pos)                  /*!< 0x00000400 */
+#define EXTI_EMR_MR10             EXTI_EMR_MR10_Msk                            /*!< Event Mask on line 10 */
+#define EXTI_EMR_MR11_Pos         (11U)                                        
+#define EXTI_EMR_MR11_Msk         (0x1UL << EXTI_EMR_MR11_Pos)                  /*!< 0x00000800 */
+#define EXTI_EMR_MR11             EXTI_EMR_MR11_Msk                            /*!< Event Mask on line 11 */
+#define EXTI_EMR_MR12_Pos         (12U)                                        
+#define EXTI_EMR_MR12_Msk         (0x1UL << EXTI_EMR_MR12_Pos)                  /*!< 0x00001000 */
+#define EXTI_EMR_MR12             EXTI_EMR_MR12_Msk                            /*!< Event Mask on line 12 */
+#define EXTI_EMR_MR13_Pos         (13U)                                        
+#define EXTI_EMR_MR13_Msk         (0x1UL << EXTI_EMR_MR13_Pos)                  /*!< 0x00002000 */
+#define EXTI_EMR_MR13             EXTI_EMR_MR13_Msk                            /*!< Event Mask on line 13 */
+#define EXTI_EMR_MR14_Pos         (14U)                                        
+#define EXTI_EMR_MR14_Msk         (0x1UL << EXTI_EMR_MR14_Pos)                  /*!< 0x00004000 */
+#define EXTI_EMR_MR14             EXTI_EMR_MR14_Msk                            /*!< Event Mask on line 14 */
+#define EXTI_EMR_MR15_Pos         (15U)                                        
+#define EXTI_EMR_MR15_Msk         (0x1UL << EXTI_EMR_MR15_Pos)                  /*!< 0x00008000 */
+#define EXTI_EMR_MR15             EXTI_EMR_MR15_Msk                            /*!< Event Mask on line 15 */
+#define EXTI_EMR_MR16_Pos         (16U)                                        
+#define EXTI_EMR_MR16_Msk         (0x1UL << EXTI_EMR_MR16_Pos)                  /*!< 0x00010000 */
+#define EXTI_EMR_MR16             EXTI_EMR_MR16_Msk                            /*!< Event Mask on line 16 */
+#define EXTI_EMR_MR17_Pos         (17U)                                        
+#define EXTI_EMR_MR17_Msk         (0x1UL << EXTI_EMR_MR17_Pos)                  /*!< 0x00020000 */
+#define EXTI_EMR_MR17             EXTI_EMR_MR17_Msk                            /*!< Event Mask on line 17 */
+#define EXTI_EMR_MR18_Pos         (18U)                                        
+#define EXTI_EMR_MR18_Msk         (0x1UL << EXTI_EMR_MR18_Pos)                  /*!< 0x00040000 */
+#define EXTI_EMR_MR18             EXTI_EMR_MR18_Msk                            /*!< Event Mask on line 18 */
+#define EXTI_EMR_MR19_Pos         (19U)                                        
+#define EXTI_EMR_MR19_Msk         (0x1UL << EXTI_EMR_MR19_Pos)                  /*!< 0x00080000 */
+#define EXTI_EMR_MR19             EXTI_EMR_MR19_Msk                            /*!< Event Mask on line 19 */
+#define EXTI_EMR_MR20_Pos         (20U)                                        
+#define EXTI_EMR_MR20_Msk         (0x1UL << EXTI_EMR_MR20_Pos)                  /*!< 0x00100000 */
+#define EXTI_EMR_MR20             EXTI_EMR_MR20_Msk                            /*!< Event Mask on line 20 */
+#define EXTI_EMR_MR21_Pos         (21U)                                        
+#define EXTI_EMR_MR21_Msk         (0x1UL << EXTI_EMR_MR21_Pos)                  /*!< 0x00200000 */
+#define EXTI_EMR_MR21             EXTI_EMR_MR21_Msk                            /*!< Event Mask on line 21 */
+#define EXTI_EMR_MR22_Pos         (22U)                                        
+#define EXTI_EMR_MR22_Msk         (0x1UL << EXTI_EMR_MR22_Pos)                  /*!< 0x00400000 */
+#define EXTI_EMR_MR22             EXTI_EMR_MR22_Msk                            /*!< Event Mask on line 22 */
+
+/* Reference Defines */
+#define  EXTI_EMR_EM0                        EXTI_EMR_MR0
+#define  EXTI_EMR_EM1                        EXTI_EMR_MR1
+#define  EXTI_EMR_EM2                        EXTI_EMR_MR2
+#define  EXTI_EMR_EM3                        EXTI_EMR_MR3
+#define  EXTI_EMR_EM4                        EXTI_EMR_MR4
+#define  EXTI_EMR_EM5                        EXTI_EMR_MR5
+#define  EXTI_EMR_EM6                        EXTI_EMR_MR6
+#define  EXTI_EMR_EM7                        EXTI_EMR_MR7
+#define  EXTI_EMR_EM8                        EXTI_EMR_MR8
+#define  EXTI_EMR_EM9                        EXTI_EMR_MR9
+#define  EXTI_EMR_EM10                       EXTI_EMR_MR10
+#define  EXTI_EMR_EM11                       EXTI_EMR_MR11
+#define  EXTI_EMR_EM12                       EXTI_EMR_MR12
+#define  EXTI_EMR_EM13                       EXTI_EMR_MR13
+#define  EXTI_EMR_EM14                       EXTI_EMR_MR14
+#define  EXTI_EMR_EM15                       EXTI_EMR_MR15
+#define  EXTI_EMR_EM16                       EXTI_EMR_MR16
+#define  EXTI_EMR_EM17                       EXTI_EMR_MR17
+#define  EXTI_EMR_EM18                       EXTI_EMR_MR18
+#define  EXTI_EMR_EM19                       EXTI_EMR_MR19
+#define  EXTI_EMR_EM20                       EXTI_EMR_MR20
+#define  EXTI_EMR_EM21                       EXTI_EMR_MR21
+#define  EXTI_EMR_EM22                       EXTI_EMR_MR22
+
+/******************  Bit definition for EXTI_RTSR register  *******************/
+#define EXTI_RTSR_TR0_Pos         (0U)                                         
+#define EXTI_RTSR_TR0_Msk         (0x1UL << EXTI_RTSR_TR0_Pos)                  /*!< 0x00000001 */
+#define EXTI_RTSR_TR0             EXTI_RTSR_TR0_Msk                            /*!< Rising trigger event configuration bit of line 0 */
+#define EXTI_RTSR_TR1_Pos         (1U)                                         
+#define EXTI_RTSR_TR1_Msk         (0x1UL << EXTI_RTSR_TR1_Pos)                  /*!< 0x00000002 */
+#define EXTI_RTSR_TR1             EXTI_RTSR_TR1_Msk                            /*!< Rising trigger event configuration bit of line 1 */
+#define EXTI_RTSR_TR2_Pos         (2U)                                         
+#define EXTI_RTSR_TR2_Msk         (0x1UL << EXTI_RTSR_TR2_Pos)                  /*!< 0x00000004 */
+#define EXTI_RTSR_TR2             EXTI_RTSR_TR2_Msk                            /*!< Rising trigger event configuration bit of line 2 */
+#define EXTI_RTSR_TR3_Pos         (3U)                                         
+#define EXTI_RTSR_TR3_Msk         (0x1UL << EXTI_RTSR_TR3_Pos)                  /*!< 0x00000008 */
+#define EXTI_RTSR_TR3             EXTI_RTSR_TR3_Msk                            /*!< Rising trigger event configuration bit of line 3 */
+#define EXTI_RTSR_TR4_Pos         (4U)                                         
+#define EXTI_RTSR_TR4_Msk         (0x1UL << EXTI_RTSR_TR4_Pos)                  /*!< 0x00000010 */
+#define EXTI_RTSR_TR4             EXTI_RTSR_TR4_Msk                            /*!< Rising trigger event configuration bit of line 4 */
+#define EXTI_RTSR_TR5_Pos         (5U)                                         
+#define EXTI_RTSR_TR5_Msk         (0x1UL << EXTI_RTSR_TR5_Pos)                  /*!< 0x00000020 */
+#define EXTI_RTSR_TR5             EXTI_RTSR_TR5_Msk                            /*!< Rising trigger event configuration bit of line 5 */
+#define EXTI_RTSR_TR6_Pos         (6U)                                         
+#define EXTI_RTSR_TR6_Msk         (0x1UL << EXTI_RTSR_TR6_Pos)                  /*!< 0x00000040 */
+#define EXTI_RTSR_TR6             EXTI_RTSR_TR6_Msk                            /*!< Rising trigger event configuration bit of line 6 */
+#define EXTI_RTSR_TR7_Pos         (7U)                                         
+#define EXTI_RTSR_TR7_Msk         (0x1UL << EXTI_RTSR_TR7_Pos)                  /*!< 0x00000080 */
+#define EXTI_RTSR_TR7             EXTI_RTSR_TR7_Msk                            /*!< Rising trigger event configuration bit of line 7 */
+#define EXTI_RTSR_TR8_Pos         (8U)                                         
+#define EXTI_RTSR_TR8_Msk         (0x1UL << EXTI_RTSR_TR8_Pos)                  /*!< 0x00000100 */
+#define EXTI_RTSR_TR8             EXTI_RTSR_TR8_Msk                            /*!< Rising trigger event configuration bit of line 8 */
+#define EXTI_RTSR_TR9_Pos         (9U)                                         
+#define EXTI_RTSR_TR9_Msk         (0x1UL << EXTI_RTSR_TR9_Pos)                  /*!< 0x00000200 */
+#define EXTI_RTSR_TR9             EXTI_RTSR_TR9_Msk                            /*!< Rising trigger event configuration bit of line 9 */
+#define EXTI_RTSR_TR10_Pos        (10U)                                        
+#define EXTI_RTSR_TR10_Msk        (0x1UL << EXTI_RTSR_TR10_Pos)                 /*!< 0x00000400 */
+#define EXTI_RTSR_TR10            EXTI_RTSR_TR10_Msk                           /*!< Rising trigger event configuration bit of line 10 */
+#define EXTI_RTSR_TR11_Pos        (11U)                                        
+#define EXTI_RTSR_TR11_Msk        (0x1UL << EXTI_RTSR_TR11_Pos)                 /*!< 0x00000800 */
+#define EXTI_RTSR_TR11            EXTI_RTSR_TR11_Msk                           /*!< Rising trigger event configuration bit of line 11 */
+#define EXTI_RTSR_TR12_Pos        (12U)                                        
+#define EXTI_RTSR_TR12_Msk        (0x1UL << EXTI_RTSR_TR12_Pos)                 /*!< 0x00001000 */
+#define EXTI_RTSR_TR12            EXTI_RTSR_TR12_Msk                           /*!< Rising trigger event configuration bit of line 12 */
+#define EXTI_RTSR_TR13_Pos        (13U)                                        
+#define EXTI_RTSR_TR13_Msk        (0x1UL << EXTI_RTSR_TR13_Pos)                 /*!< 0x00002000 */
+#define EXTI_RTSR_TR13            EXTI_RTSR_TR13_Msk                           /*!< Rising trigger event configuration bit of line 13 */
+#define EXTI_RTSR_TR14_Pos        (14U)                                        
+#define EXTI_RTSR_TR14_Msk        (0x1UL << EXTI_RTSR_TR14_Pos)                 /*!< 0x00004000 */
+#define EXTI_RTSR_TR14            EXTI_RTSR_TR14_Msk                           /*!< Rising trigger event configuration bit of line 14 */
+#define EXTI_RTSR_TR15_Pos        (15U)                                        
+#define EXTI_RTSR_TR15_Msk        (0x1UL << EXTI_RTSR_TR15_Pos)                 /*!< 0x00008000 */
+#define EXTI_RTSR_TR15            EXTI_RTSR_TR15_Msk                           /*!< Rising trigger event configuration bit of line 15 */
+#define EXTI_RTSR_TR16_Pos        (16U)                                        
+#define EXTI_RTSR_TR16_Msk        (0x1UL << EXTI_RTSR_TR16_Pos)                 /*!< 0x00010000 */
+#define EXTI_RTSR_TR16            EXTI_RTSR_TR16_Msk                           /*!< Rising trigger event configuration bit of line 16 */
+#define EXTI_RTSR_TR17_Pos        (17U)                                        
+#define EXTI_RTSR_TR17_Msk        (0x1UL << EXTI_RTSR_TR17_Pos)                 /*!< 0x00020000 */
+#define EXTI_RTSR_TR17            EXTI_RTSR_TR17_Msk                           /*!< Rising trigger event configuration bit of line 17 */
+#define EXTI_RTSR_TR18_Pos        (18U)                                        
+#define EXTI_RTSR_TR18_Msk        (0x1UL << EXTI_RTSR_TR18_Pos)                 /*!< 0x00040000 */
+#define EXTI_RTSR_TR18            EXTI_RTSR_TR18_Msk                           /*!< Rising trigger event configuration bit of line 18 */
+#define EXTI_RTSR_TR19_Pos        (19U)                                        
+#define EXTI_RTSR_TR19_Msk        (0x1UL << EXTI_RTSR_TR19_Pos)                 /*!< 0x00080000 */
+#define EXTI_RTSR_TR19            EXTI_RTSR_TR19_Msk                           /*!< Rising trigger event configuration bit of line 19 */
+#define EXTI_RTSR_TR20_Pos        (20U)                                        
+#define EXTI_RTSR_TR20_Msk        (0x1UL << EXTI_RTSR_TR20_Pos)                 /*!< 0x00100000 */
+#define EXTI_RTSR_TR20            EXTI_RTSR_TR20_Msk                           /*!< Rising trigger event configuration bit of line 20 */
+#define EXTI_RTSR_TR21_Pos        (21U)                                        
+#define EXTI_RTSR_TR21_Msk        (0x1UL << EXTI_RTSR_TR21_Pos)                 /*!< 0x00200000 */
+#define EXTI_RTSR_TR21            EXTI_RTSR_TR21_Msk                           /*!< Rising trigger event configuration bit of line 21 */
+#define EXTI_RTSR_TR22_Pos        (22U)                                        
+#define EXTI_RTSR_TR22_Msk        (0x1UL << EXTI_RTSR_TR22_Pos)                 /*!< 0x00400000 */
+#define EXTI_RTSR_TR22            EXTI_RTSR_TR22_Msk                           /*!< Rising trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_FTSR register  *******************/
+#define EXTI_FTSR_TR0_Pos         (0U)                                         
+#define EXTI_FTSR_TR0_Msk         (0x1UL << EXTI_FTSR_TR0_Pos)                  /*!< 0x00000001 */
+#define EXTI_FTSR_TR0             EXTI_FTSR_TR0_Msk                            /*!< Falling trigger event configuration bit of line 0 */
+#define EXTI_FTSR_TR1_Pos         (1U)                                         
+#define EXTI_FTSR_TR1_Msk         (0x1UL << EXTI_FTSR_TR1_Pos)                  /*!< 0x00000002 */
+#define EXTI_FTSR_TR1             EXTI_FTSR_TR1_Msk                            /*!< Falling trigger event configuration bit of line 1 */
+#define EXTI_FTSR_TR2_Pos         (2U)                                         
+#define EXTI_FTSR_TR2_Msk         (0x1UL << EXTI_FTSR_TR2_Pos)                  /*!< 0x00000004 */
+#define EXTI_FTSR_TR2             EXTI_FTSR_TR2_Msk                            /*!< Falling trigger event configuration bit of line 2 */
+#define EXTI_FTSR_TR3_Pos         (3U)                                         
+#define EXTI_FTSR_TR3_Msk         (0x1UL << EXTI_FTSR_TR3_Pos)                  /*!< 0x00000008 */
+#define EXTI_FTSR_TR3             EXTI_FTSR_TR3_Msk                            /*!< Falling trigger event configuration bit of line 3 */
+#define EXTI_FTSR_TR4_Pos         (4U)                                         
+#define EXTI_FTSR_TR4_Msk         (0x1UL << EXTI_FTSR_TR4_Pos)                  /*!< 0x00000010 */
+#define EXTI_FTSR_TR4             EXTI_FTSR_TR4_Msk                            /*!< Falling trigger event configuration bit of line 4 */
+#define EXTI_FTSR_TR5_Pos         (5U)                                         
+#define EXTI_FTSR_TR5_Msk         (0x1UL << EXTI_FTSR_TR5_Pos)                  /*!< 0x00000020 */
+#define EXTI_FTSR_TR5             EXTI_FTSR_TR5_Msk                            /*!< Falling trigger event configuration bit of line 5 */
+#define EXTI_FTSR_TR6_Pos         (6U)                                         
+#define EXTI_FTSR_TR6_Msk         (0x1UL << EXTI_FTSR_TR6_Pos)                  /*!< 0x00000040 */
+#define EXTI_FTSR_TR6             EXTI_FTSR_TR6_Msk                            /*!< Falling trigger event configuration bit of line 6 */
+#define EXTI_FTSR_TR7_Pos         (7U)                                         
+#define EXTI_FTSR_TR7_Msk         (0x1UL << EXTI_FTSR_TR7_Pos)                  /*!< 0x00000080 */
+#define EXTI_FTSR_TR7             EXTI_FTSR_TR7_Msk                            /*!< Falling trigger event configuration bit of line 7 */
+#define EXTI_FTSR_TR8_Pos         (8U)                                         
+#define EXTI_FTSR_TR8_Msk         (0x1UL << EXTI_FTSR_TR8_Pos)                  /*!< 0x00000100 */
+#define EXTI_FTSR_TR8             EXTI_FTSR_TR8_Msk                            /*!< Falling trigger event configuration bit of line 8 */
+#define EXTI_FTSR_TR9_Pos         (9U)                                         
+#define EXTI_FTSR_TR9_Msk         (0x1UL << EXTI_FTSR_TR9_Pos)                  /*!< 0x00000200 */
+#define EXTI_FTSR_TR9             EXTI_FTSR_TR9_Msk                            /*!< Falling trigger event configuration bit of line 9 */
+#define EXTI_FTSR_TR10_Pos        (10U)                                        
+#define EXTI_FTSR_TR10_Msk        (0x1UL << EXTI_FTSR_TR10_Pos)                 /*!< 0x00000400 */
+#define EXTI_FTSR_TR10            EXTI_FTSR_TR10_Msk                           /*!< Falling trigger event configuration bit of line 10 */
+#define EXTI_FTSR_TR11_Pos        (11U)                                        
+#define EXTI_FTSR_TR11_Msk        (0x1UL << EXTI_FTSR_TR11_Pos)                 /*!< 0x00000800 */
+#define EXTI_FTSR_TR11            EXTI_FTSR_TR11_Msk                           /*!< Falling trigger event configuration bit of line 11 */
+#define EXTI_FTSR_TR12_Pos        (12U)                                        
+#define EXTI_FTSR_TR12_Msk        (0x1UL << EXTI_FTSR_TR12_Pos)                 /*!< 0x00001000 */
+#define EXTI_FTSR_TR12            EXTI_FTSR_TR12_Msk                           /*!< Falling trigger event configuration bit of line 12 */
+#define EXTI_FTSR_TR13_Pos        (13U)                                        
+#define EXTI_FTSR_TR13_Msk        (0x1UL << EXTI_FTSR_TR13_Pos)                 /*!< 0x00002000 */
+#define EXTI_FTSR_TR13            EXTI_FTSR_TR13_Msk                           /*!< Falling trigger event configuration bit of line 13 */
+#define EXTI_FTSR_TR14_Pos        (14U)                                        
+#define EXTI_FTSR_TR14_Msk        (0x1UL << EXTI_FTSR_TR14_Pos)                 /*!< 0x00004000 */
+#define EXTI_FTSR_TR14            EXTI_FTSR_TR14_Msk                           /*!< Falling trigger event configuration bit of line 14 */
+#define EXTI_FTSR_TR15_Pos        (15U)                                        
+#define EXTI_FTSR_TR15_Msk        (0x1UL << EXTI_FTSR_TR15_Pos)                 /*!< 0x00008000 */
+#define EXTI_FTSR_TR15            EXTI_FTSR_TR15_Msk                           /*!< Falling trigger event configuration bit of line 15 */
+#define EXTI_FTSR_TR16_Pos        (16U)                                        
+#define EXTI_FTSR_TR16_Msk        (0x1UL << EXTI_FTSR_TR16_Pos)                 /*!< 0x00010000 */
+#define EXTI_FTSR_TR16            EXTI_FTSR_TR16_Msk                           /*!< Falling trigger event configuration bit of line 16 */
+#define EXTI_FTSR_TR17_Pos        (17U)                                        
+#define EXTI_FTSR_TR17_Msk        (0x1UL << EXTI_FTSR_TR17_Pos)                 /*!< 0x00020000 */
+#define EXTI_FTSR_TR17            EXTI_FTSR_TR17_Msk                           /*!< Falling trigger event configuration bit of line 17 */
+#define EXTI_FTSR_TR18_Pos        (18U)                                        
+#define EXTI_FTSR_TR18_Msk        (0x1UL << EXTI_FTSR_TR18_Pos)                 /*!< 0x00040000 */
+#define EXTI_FTSR_TR18            EXTI_FTSR_TR18_Msk                           /*!< Falling trigger event configuration bit of line 18 */
+#define EXTI_FTSR_TR19_Pos        (19U)                                        
+#define EXTI_FTSR_TR19_Msk        (0x1UL << EXTI_FTSR_TR19_Pos)                 /*!< 0x00080000 */
+#define EXTI_FTSR_TR19            EXTI_FTSR_TR19_Msk                           /*!< Falling trigger event configuration bit of line 19 */
+#define EXTI_FTSR_TR20_Pos        (20U)                                        
+#define EXTI_FTSR_TR20_Msk        (0x1UL << EXTI_FTSR_TR20_Pos)                 /*!< 0x00100000 */
+#define EXTI_FTSR_TR20            EXTI_FTSR_TR20_Msk                           /*!< Falling trigger event configuration bit of line 20 */
+#define EXTI_FTSR_TR21_Pos        (21U)                                        
+#define EXTI_FTSR_TR21_Msk        (0x1UL << EXTI_FTSR_TR21_Pos)                 /*!< 0x00200000 */
+#define EXTI_FTSR_TR21            EXTI_FTSR_TR21_Msk                           /*!< Falling trigger event configuration bit of line 21 */
+#define EXTI_FTSR_TR22_Pos        (22U)                                        
+#define EXTI_FTSR_TR22_Msk        (0x1UL << EXTI_FTSR_TR22_Pos)                 /*!< 0x00400000 */
+#define EXTI_FTSR_TR22            EXTI_FTSR_TR22_Msk                           /*!< Falling trigger event configuration bit of line 22 */
+
+/******************  Bit definition for EXTI_SWIER register  ******************/
+#define EXTI_SWIER_SWIER0_Pos     (0U)                                         
+#define EXTI_SWIER_SWIER0_Msk     (0x1UL << EXTI_SWIER_SWIER0_Pos)              /*!< 0x00000001 */
+#define EXTI_SWIER_SWIER0         EXTI_SWIER_SWIER0_Msk                        /*!< Software Interrupt on line 0 */
+#define EXTI_SWIER_SWIER1_Pos     (1U)                                         
+#define EXTI_SWIER_SWIER1_Msk     (0x1UL << EXTI_SWIER_SWIER1_Pos)              /*!< 0x00000002 */
+#define EXTI_SWIER_SWIER1         EXTI_SWIER_SWIER1_Msk                        /*!< Software Interrupt on line 1 */
+#define EXTI_SWIER_SWIER2_Pos     (2U)                                         
+#define EXTI_SWIER_SWIER2_Msk     (0x1UL << EXTI_SWIER_SWIER2_Pos)              /*!< 0x00000004 */
+#define EXTI_SWIER_SWIER2         EXTI_SWIER_SWIER2_Msk                        /*!< Software Interrupt on line 2 */
+#define EXTI_SWIER_SWIER3_Pos     (3U)                                         
+#define EXTI_SWIER_SWIER3_Msk     (0x1UL << EXTI_SWIER_SWIER3_Pos)              /*!< 0x00000008 */
+#define EXTI_SWIER_SWIER3         EXTI_SWIER_SWIER3_Msk                        /*!< Software Interrupt on line 3 */
+#define EXTI_SWIER_SWIER4_Pos     (4U)                                         
+#define EXTI_SWIER_SWIER4_Msk     (0x1UL << EXTI_SWIER_SWIER4_Pos)              /*!< 0x00000010 */
+#define EXTI_SWIER_SWIER4         EXTI_SWIER_SWIER4_Msk                        /*!< Software Interrupt on line 4 */
+#define EXTI_SWIER_SWIER5_Pos     (5U)                                         
+#define EXTI_SWIER_SWIER5_Msk     (0x1UL << EXTI_SWIER_SWIER5_Pos)              /*!< 0x00000020 */
+#define EXTI_SWIER_SWIER5         EXTI_SWIER_SWIER5_Msk                        /*!< Software Interrupt on line 5 */
+#define EXTI_SWIER_SWIER6_Pos     (6U)                                         
+#define EXTI_SWIER_SWIER6_Msk     (0x1UL << EXTI_SWIER_SWIER6_Pos)              /*!< 0x00000040 */
+#define EXTI_SWIER_SWIER6         EXTI_SWIER_SWIER6_Msk                        /*!< Software Interrupt on line 6 */
+#define EXTI_SWIER_SWIER7_Pos     (7U)                                         
+#define EXTI_SWIER_SWIER7_Msk     (0x1UL << EXTI_SWIER_SWIER7_Pos)              /*!< 0x00000080 */
+#define EXTI_SWIER_SWIER7         EXTI_SWIER_SWIER7_Msk                        /*!< Software Interrupt on line 7 */
+#define EXTI_SWIER_SWIER8_Pos     (8U)                                         
+#define EXTI_SWIER_SWIER8_Msk     (0x1UL << EXTI_SWIER_SWIER8_Pos)              /*!< 0x00000100 */
+#define EXTI_SWIER_SWIER8         EXTI_SWIER_SWIER8_Msk                        /*!< Software Interrupt on line 8 */
+#define EXTI_SWIER_SWIER9_Pos     (9U)                                         
+#define EXTI_SWIER_SWIER9_Msk     (0x1UL << EXTI_SWIER_SWIER9_Pos)              /*!< 0x00000200 */
+#define EXTI_SWIER_SWIER9         EXTI_SWIER_SWIER9_Msk                        /*!< Software Interrupt on line 9 */
+#define EXTI_SWIER_SWIER10_Pos    (10U)                                        
+#define EXTI_SWIER_SWIER10_Msk    (0x1UL << EXTI_SWIER_SWIER10_Pos)             /*!< 0x00000400 */
+#define EXTI_SWIER_SWIER10        EXTI_SWIER_SWIER10_Msk                       /*!< Software Interrupt on line 10 */
+#define EXTI_SWIER_SWIER11_Pos    (11U)                                        
+#define EXTI_SWIER_SWIER11_Msk    (0x1UL << EXTI_SWIER_SWIER11_Pos)             /*!< 0x00000800 */
+#define EXTI_SWIER_SWIER11        EXTI_SWIER_SWIER11_Msk                       /*!< Software Interrupt on line 11 */
+#define EXTI_SWIER_SWIER12_Pos    (12U)                                        
+#define EXTI_SWIER_SWIER12_Msk    (0x1UL << EXTI_SWIER_SWIER12_Pos)             /*!< 0x00001000 */
+#define EXTI_SWIER_SWIER12        EXTI_SWIER_SWIER12_Msk                       /*!< Software Interrupt on line 12 */
+#define EXTI_SWIER_SWIER13_Pos    (13U)                                        
+#define EXTI_SWIER_SWIER13_Msk    (0x1UL << EXTI_SWIER_SWIER13_Pos)             /*!< 0x00002000 */
+#define EXTI_SWIER_SWIER13        EXTI_SWIER_SWIER13_Msk                       /*!< Software Interrupt on line 13 */
+#define EXTI_SWIER_SWIER14_Pos    (14U)                                        
+#define EXTI_SWIER_SWIER14_Msk    (0x1UL << EXTI_SWIER_SWIER14_Pos)             /*!< 0x00004000 */
+#define EXTI_SWIER_SWIER14        EXTI_SWIER_SWIER14_Msk                       /*!< Software Interrupt on line 14 */
+#define EXTI_SWIER_SWIER15_Pos    (15U)                                        
+#define EXTI_SWIER_SWIER15_Msk    (0x1UL << EXTI_SWIER_SWIER15_Pos)             /*!< 0x00008000 */
+#define EXTI_SWIER_SWIER15        EXTI_SWIER_SWIER15_Msk                       /*!< Software Interrupt on line 15 */
+#define EXTI_SWIER_SWIER16_Pos    (16U)                                        
+#define EXTI_SWIER_SWIER16_Msk    (0x1UL << EXTI_SWIER_SWIER16_Pos)             /*!< 0x00010000 */
+#define EXTI_SWIER_SWIER16        EXTI_SWIER_SWIER16_Msk                       /*!< Software Interrupt on line 16 */
+#define EXTI_SWIER_SWIER17_Pos    (17U)                                        
+#define EXTI_SWIER_SWIER17_Msk    (0x1UL << EXTI_SWIER_SWIER17_Pos)             /*!< 0x00020000 */
+#define EXTI_SWIER_SWIER17        EXTI_SWIER_SWIER17_Msk                       /*!< Software Interrupt on line 17 */
+#define EXTI_SWIER_SWIER18_Pos    (18U)                                        
+#define EXTI_SWIER_SWIER18_Msk    (0x1UL << EXTI_SWIER_SWIER18_Pos)             /*!< 0x00040000 */
+#define EXTI_SWIER_SWIER18        EXTI_SWIER_SWIER18_Msk                       /*!< Software Interrupt on line 18 */
+#define EXTI_SWIER_SWIER19_Pos    (19U)                                        
+#define EXTI_SWIER_SWIER19_Msk    (0x1UL << EXTI_SWIER_SWIER19_Pos)             /*!< 0x00080000 */
+#define EXTI_SWIER_SWIER19        EXTI_SWIER_SWIER19_Msk                       /*!< Software Interrupt on line 19 */
+#define EXTI_SWIER_SWIER20_Pos    (20U)                                        
+#define EXTI_SWIER_SWIER20_Msk    (0x1UL << EXTI_SWIER_SWIER20_Pos)             /*!< 0x00100000 */
+#define EXTI_SWIER_SWIER20        EXTI_SWIER_SWIER20_Msk                       /*!< Software Interrupt on line 20 */
+#define EXTI_SWIER_SWIER21_Pos    (21U)                                        
+#define EXTI_SWIER_SWIER21_Msk    (0x1UL << EXTI_SWIER_SWIER21_Pos)             /*!< 0x00200000 */
+#define EXTI_SWIER_SWIER21        EXTI_SWIER_SWIER21_Msk                       /*!< Software Interrupt on line 21 */
+#define EXTI_SWIER_SWIER22_Pos    (22U)                                        
+#define EXTI_SWIER_SWIER22_Msk    (0x1UL << EXTI_SWIER_SWIER22_Pos)             /*!< 0x00400000 */
+#define EXTI_SWIER_SWIER22        EXTI_SWIER_SWIER22_Msk                       /*!< Software Interrupt on line 22 */
+
+/*******************  Bit definition for EXTI_PR register  ********************/
+#define EXTI_PR_PR0_Pos           (0U)                                         
+#define EXTI_PR_PR0_Msk           (0x1UL << EXTI_PR_PR0_Pos)                    /*!< 0x00000001 */
+#define EXTI_PR_PR0               EXTI_PR_PR0_Msk                              /*!< Pending bit for line 0 */
+#define EXTI_PR_PR1_Pos           (1U)                                         
+#define EXTI_PR_PR1_Msk           (0x1UL << EXTI_PR_PR1_Pos)                    /*!< 0x00000002 */
+#define EXTI_PR_PR1               EXTI_PR_PR1_Msk                              /*!< Pending bit for line 1 */
+#define EXTI_PR_PR2_Pos           (2U)                                         
+#define EXTI_PR_PR2_Msk           (0x1UL << EXTI_PR_PR2_Pos)                    /*!< 0x00000004 */
+#define EXTI_PR_PR2               EXTI_PR_PR2_Msk                              /*!< Pending bit for line 2 */
+#define EXTI_PR_PR3_Pos           (3U)                                         
+#define EXTI_PR_PR3_Msk           (0x1UL << EXTI_PR_PR3_Pos)                    /*!< 0x00000008 */
+#define EXTI_PR_PR3               EXTI_PR_PR3_Msk                              /*!< Pending bit for line 3 */
+#define EXTI_PR_PR4_Pos           (4U)                                         
+#define EXTI_PR_PR4_Msk           (0x1UL << EXTI_PR_PR4_Pos)                    /*!< 0x00000010 */
+#define EXTI_PR_PR4               EXTI_PR_PR4_Msk                              /*!< Pending bit for line 4 */
+#define EXTI_PR_PR5_Pos           (5U)                                         
+#define EXTI_PR_PR5_Msk           (0x1UL << EXTI_PR_PR5_Pos)                    /*!< 0x00000020 */
+#define EXTI_PR_PR5               EXTI_PR_PR5_Msk                              /*!< Pending bit for line 5 */
+#define EXTI_PR_PR6_Pos           (6U)                                         
+#define EXTI_PR_PR6_Msk           (0x1UL << EXTI_PR_PR6_Pos)                    /*!< 0x00000040 */
+#define EXTI_PR_PR6               EXTI_PR_PR6_Msk                              /*!< Pending bit for line 6 */
+#define EXTI_PR_PR7_Pos           (7U)                                         
+#define EXTI_PR_PR7_Msk           (0x1UL << EXTI_PR_PR7_Pos)                    /*!< 0x00000080 */
+#define EXTI_PR_PR7               EXTI_PR_PR7_Msk                              /*!< Pending bit for line 7 */
+#define EXTI_PR_PR8_Pos           (8U)                                         
+#define EXTI_PR_PR8_Msk           (0x1UL << EXTI_PR_PR8_Pos)                    /*!< 0x00000100 */
+#define EXTI_PR_PR8               EXTI_PR_PR8_Msk                              /*!< Pending bit for line 8 */
+#define EXTI_PR_PR9_Pos           (9U)                                         
+#define EXTI_PR_PR9_Msk           (0x1UL << EXTI_PR_PR9_Pos)                    /*!< 0x00000200 */
+#define EXTI_PR_PR9               EXTI_PR_PR9_Msk                              /*!< Pending bit for line 9 */
+#define EXTI_PR_PR10_Pos          (10U)                                        
+#define EXTI_PR_PR10_Msk          (0x1UL << EXTI_PR_PR10_Pos)                   /*!< 0x00000400 */
+#define EXTI_PR_PR10              EXTI_PR_PR10_Msk                             /*!< Pending bit for line 10 */
+#define EXTI_PR_PR11_Pos          (11U)                                        
+#define EXTI_PR_PR11_Msk          (0x1UL << EXTI_PR_PR11_Pos)                   /*!< 0x00000800 */
+#define EXTI_PR_PR11              EXTI_PR_PR11_Msk                             /*!< Pending bit for line 11 */
+#define EXTI_PR_PR12_Pos          (12U)                                        
+#define EXTI_PR_PR12_Msk          (0x1UL << EXTI_PR_PR12_Pos)                   /*!< 0x00001000 */
+#define EXTI_PR_PR12              EXTI_PR_PR12_Msk                             /*!< Pending bit for line 12 */
+#define EXTI_PR_PR13_Pos          (13U)                                        
+#define EXTI_PR_PR13_Msk          (0x1UL << EXTI_PR_PR13_Pos)                   /*!< 0x00002000 */
+#define EXTI_PR_PR13              EXTI_PR_PR13_Msk                             /*!< Pending bit for line 13 */
+#define EXTI_PR_PR14_Pos          (14U)                                        
+#define EXTI_PR_PR14_Msk          (0x1UL << EXTI_PR_PR14_Pos)                   /*!< 0x00004000 */
+#define EXTI_PR_PR14              EXTI_PR_PR14_Msk                             /*!< Pending bit for line 14 */
+#define EXTI_PR_PR15_Pos          (15U)                                        
+#define EXTI_PR_PR15_Msk          (0x1UL << EXTI_PR_PR15_Pos)                   /*!< 0x00008000 */
+#define EXTI_PR_PR15              EXTI_PR_PR15_Msk                             /*!< Pending bit for line 15 */
+#define EXTI_PR_PR16_Pos          (16U)                                        
+#define EXTI_PR_PR16_Msk          (0x1UL << EXTI_PR_PR16_Pos)                   /*!< 0x00010000 */
+#define EXTI_PR_PR16              EXTI_PR_PR16_Msk                             /*!< Pending bit for line 16 */
+#define EXTI_PR_PR17_Pos          (17U)                                        
+#define EXTI_PR_PR17_Msk          (0x1UL << EXTI_PR_PR17_Pos)                   /*!< 0x00020000 */
+#define EXTI_PR_PR17              EXTI_PR_PR17_Msk                             /*!< Pending bit for line 17 */
+#define EXTI_PR_PR18_Pos          (18U)                                        
+#define EXTI_PR_PR18_Msk          (0x1UL << EXTI_PR_PR18_Pos)                   /*!< 0x00040000 */
+#define EXTI_PR_PR18              EXTI_PR_PR18_Msk                             /*!< Pending bit for line 18 */
+#define EXTI_PR_PR19_Pos          (19U)                                        
+#define EXTI_PR_PR19_Msk          (0x1UL << EXTI_PR_PR19_Pos)                   /*!< 0x00080000 */
+#define EXTI_PR_PR19              EXTI_PR_PR19_Msk                             /*!< Pending bit for line 19 */
+#define EXTI_PR_PR20_Pos          (20U)                                        
+#define EXTI_PR_PR20_Msk          (0x1UL << EXTI_PR_PR20_Pos)                   /*!< 0x00100000 */
+#define EXTI_PR_PR20              EXTI_PR_PR20_Msk                             /*!< Pending bit for line 20 */
+#define EXTI_PR_PR21_Pos          (21U)                                        
+#define EXTI_PR_PR21_Msk          (0x1UL << EXTI_PR_PR21_Pos)                   /*!< 0x00200000 */
+#define EXTI_PR_PR21              EXTI_PR_PR21_Msk                             /*!< Pending bit for line 21 */
+#define EXTI_PR_PR22_Pos          (22U)                                        
+#define EXTI_PR_PR22_Msk          (0x1UL << EXTI_PR_PR22_Pos)                   /*!< 0x00400000 */
+#define EXTI_PR_PR22              EXTI_PR_PR22_Msk                             /*!< Pending bit for line 22 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    FLASH                                   */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bits definition for FLASH_ACR register  *****************/
+#define FLASH_ACR_LATENCY_Pos          (0U)
+#define FLASH_ACR_LATENCY_Msk          (0x7UL << FLASH_ACR_LATENCY_Pos)         /*!< 0x00000007 */
+#define FLASH_ACR_LATENCY              FLASH_ACR_LATENCY_Msk
+#define FLASH_ACR_LATENCY_0WS          0x00000000U
+#define FLASH_ACR_LATENCY_1WS          0x00000001U
+#define FLASH_ACR_LATENCY_2WS          0x00000002U
+#define FLASH_ACR_LATENCY_3WS          0x00000003U
+#define FLASH_ACR_LATENCY_4WS          0x00000004U
+#define FLASH_ACR_LATENCY_5WS          0x00000005U
+#define FLASH_ACR_LATENCY_6WS          0x00000006U
+#define FLASH_ACR_LATENCY_7WS          0x00000007U
+
+
+#define FLASH_ACR_PRFTEN_Pos           (8U)                                    
+#define FLASH_ACR_PRFTEN_Msk           (0x1UL << FLASH_ACR_PRFTEN_Pos)          /*!< 0x00000100 */
+#define FLASH_ACR_PRFTEN               FLASH_ACR_PRFTEN_Msk                    
+#define FLASH_ACR_ICEN_Pos             (9U)                                    
+#define FLASH_ACR_ICEN_Msk             (0x1UL << FLASH_ACR_ICEN_Pos)            /*!< 0x00000200 */
+#define FLASH_ACR_ICEN                 FLASH_ACR_ICEN_Msk                      
+#define FLASH_ACR_DCEN_Pos             (10U)                                   
+#define FLASH_ACR_DCEN_Msk             (0x1UL << FLASH_ACR_DCEN_Pos)            /*!< 0x00000400 */
+#define FLASH_ACR_DCEN                 FLASH_ACR_DCEN_Msk                      
+#define FLASH_ACR_ICRST_Pos            (11U)                                   
+#define FLASH_ACR_ICRST_Msk            (0x1UL << FLASH_ACR_ICRST_Pos)           /*!< 0x00000800 */
+#define FLASH_ACR_ICRST                FLASH_ACR_ICRST_Msk                     
+#define FLASH_ACR_DCRST_Pos            (12U)                                   
+#define FLASH_ACR_DCRST_Msk            (0x1UL << FLASH_ACR_DCRST_Pos)           /*!< 0x00001000 */
+#define FLASH_ACR_DCRST                FLASH_ACR_DCRST_Msk                     
+#define FLASH_ACR_BYTE0_ADDRESS_Pos    (10U)                                   
+#define FLASH_ACR_BYTE0_ADDRESS_Msk    (0x10008FUL << FLASH_ACR_BYTE0_ADDRESS_Pos) /*!< 0x40023C00 */
+#define FLASH_ACR_BYTE0_ADDRESS        FLASH_ACR_BYTE0_ADDRESS_Msk             
+#define FLASH_ACR_BYTE2_ADDRESS_Pos    (0U)                                    
+#define FLASH_ACR_BYTE2_ADDRESS_Msk    (0x40023C03UL << FLASH_ACR_BYTE2_ADDRESS_Pos) /*!< 0x40023C03 */
+#define FLASH_ACR_BYTE2_ADDRESS        FLASH_ACR_BYTE2_ADDRESS_Msk             
+
+/*******************  Bits definition for FLASH_SR register  ******************/
+#define FLASH_SR_EOP_Pos               (0U)                                    
+#define FLASH_SR_EOP_Msk               (0x1UL << FLASH_SR_EOP_Pos)              /*!< 0x00000001 */
+#define FLASH_SR_EOP                   FLASH_SR_EOP_Msk                        
+#define FLASH_SR_SOP_Pos               (1U)                                    
+#define FLASH_SR_SOP_Msk               (0x1UL << FLASH_SR_SOP_Pos)              /*!< 0x00000002 */
+#define FLASH_SR_SOP                   FLASH_SR_SOP_Msk                        
+#define FLASH_SR_WRPERR_Pos            (4U)                                    
+#define FLASH_SR_WRPERR_Msk            (0x1UL << FLASH_SR_WRPERR_Pos)           /*!< 0x00000010 */
+#define FLASH_SR_WRPERR                FLASH_SR_WRPERR_Msk                     
+#define FLASH_SR_PGAERR_Pos            (5U)                                    
+#define FLASH_SR_PGAERR_Msk            (0x1UL << FLASH_SR_PGAERR_Pos)           /*!< 0x00000020 */
+#define FLASH_SR_PGAERR                FLASH_SR_PGAERR_Msk                     
+#define FLASH_SR_PGPERR_Pos            (6U)                                    
+#define FLASH_SR_PGPERR_Msk            (0x1UL << FLASH_SR_PGPERR_Pos)           /*!< 0x00000040 */
+#define FLASH_SR_PGPERR                FLASH_SR_PGPERR_Msk                     
+#define FLASH_SR_PGSERR_Pos            (7U)                                    
+#define FLASH_SR_PGSERR_Msk            (0x1UL << FLASH_SR_PGSERR_Pos)           /*!< 0x00000080 */
+#define FLASH_SR_PGSERR                FLASH_SR_PGSERR_Msk                     
+#define FLASH_SR_BSY_Pos               (16U)                                   
+#define FLASH_SR_BSY_Msk               (0x1UL << FLASH_SR_BSY_Pos)              /*!< 0x00010000 */
+#define FLASH_SR_BSY                   FLASH_SR_BSY_Msk                        
+
+/*******************  Bits definition for FLASH_CR register  ******************/
+#define FLASH_CR_PG_Pos                (0U)                                    
+#define FLASH_CR_PG_Msk                (0x1UL << FLASH_CR_PG_Pos)               /*!< 0x00000001 */
+#define FLASH_CR_PG                    FLASH_CR_PG_Msk                         
+#define FLASH_CR_SER_Pos               (1U)                                    
+#define FLASH_CR_SER_Msk               (0x1UL << FLASH_CR_SER_Pos)              /*!< 0x00000002 */
+#define FLASH_CR_SER                   FLASH_CR_SER_Msk                        
+#define FLASH_CR_MER_Pos               (2U)                                    
+#define FLASH_CR_MER_Msk               (0x1UL << FLASH_CR_MER_Pos)              /*!< 0x00000004 */
+#define FLASH_CR_MER                   FLASH_CR_MER_Msk                        
+#define FLASH_CR_SNB_Pos               (3U)                                    
+#define FLASH_CR_SNB_Msk               (0x1FUL << FLASH_CR_SNB_Pos)             /*!< 0x000000F8 */
+#define FLASH_CR_SNB                   FLASH_CR_SNB_Msk                        
+#define FLASH_CR_SNB_0                 (0x01UL << FLASH_CR_SNB_Pos)             /*!< 0x00000008 */
+#define FLASH_CR_SNB_1                 (0x02UL << FLASH_CR_SNB_Pos)             /*!< 0x00000010 */
+#define FLASH_CR_SNB_2                 (0x04UL << FLASH_CR_SNB_Pos)             /*!< 0x00000020 */
+#define FLASH_CR_SNB_3                 (0x08UL << FLASH_CR_SNB_Pos)             /*!< 0x00000040 */
+#define FLASH_CR_SNB_4                 (0x10UL << FLASH_CR_SNB_Pos)             /*!< 0x00000080 */
+#define FLASH_CR_PSIZE_Pos             (8U)                                    
+#define FLASH_CR_PSIZE_Msk             (0x3UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000300 */
+#define FLASH_CR_PSIZE                 FLASH_CR_PSIZE_Msk                      
+#define FLASH_CR_PSIZE_0               (0x1UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000100 */
+#define FLASH_CR_PSIZE_1               (0x2UL << FLASH_CR_PSIZE_Pos)            /*!< 0x00000200 */
+#define FLASH_CR_STRT_Pos              (16U)                                   
+#define FLASH_CR_STRT_Msk              (0x1UL << FLASH_CR_STRT_Pos)             /*!< 0x00010000 */
+#define FLASH_CR_STRT                  FLASH_CR_STRT_Msk                       
+#define FLASH_CR_EOPIE_Pos             (24U)                                   
+#define FLASH_CR_EOPIE_Msk             (0x1UL << FLASH_CR_EOPIE_Pos)            /*!< 0x01000000 */
+#define FLASH_CR_EOPIE                 FLASH_CR_EOPIE_Msk                      
+#define FLASH_CR_ERRIE_Pos             (25U)
+#define FLASH_CR_ERRIE_Msk             (0x1UL << FLASH_CR_ERRIE_Pos)
+#define FLASH_CR_ERRIE                 FLASH_CR_ERRIE_Msk
+#define FLASH_CR_LOCK_Pos              (31U)                                   
+#define FLASH_CR_LOCK_Msk              (0x1UL << FLASH_CR_LOCK_Pos)             /*!< 0x80000000 */
+#define FLASH_CR_LOCK                  FLASH_CR_LOCK_Msk                       
+
+/*******************  Bits definition for FLASH_OPTCR register  ***************/
+#define FLASH_OPTCR_OPTLOCK_Pos        (0U)                                    
+#define FLASH_OPTCR_OPTLOCK_Msk        (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)       /*!< 0x00000001 */
+#define FLASH_OPTCR_OPTLOCK            FLASH_OPTCR_OPTLOCK_Msk                 
+#define FLASH_OPTCR_OPTSTRT_Pos        (1U)                                    
+#define FLASH_OPTCR_OPTSTRT_Msk        (0x1UL << FLASH_OPTCR_OPTSTRT_Pos)       /*!< 0x00000002 */
+#define FLASH_OPTCR_OPTSTRT            FLASH_OPTCR_OPTSTRT_Msk                 
+
+#define FLASH_OPTCR_BOR_LEV_0          0x00000004U                             
+#define FLASH_OPTCR_BOR_LEV_1          0x00000008U                             
+#define FLASH_OPTCR_BOR_LEV_Pos        (2U)                                    
+#define FLASH_OPTCR_BOR_LEV_Msk        (0x3UL << FLASH_OPTCR_BOR_LEV_Pos)       /*!< 0x0000000C */
+#define FLASH_OPTCR_BOR_LEV            FLASH_OPTCR_BOR_LEV_Msk                 
+#define FLASH_OPTCR_WDG_SW_Pos         (5U)                                    
+#define FLASH_OPTCR_WDG_SW_Msk         (0x1UL << FLASH_OPTCR_WDG_SW_Pos)        /*!< 0x00000020 */
+#define FLASH_OPTCR_WDG_SW             FLASH_OPTCR_WDG_SW_Msk                  
+#define FLASH_OPTCR_nRST_STOP_Pos      (6U)                                    
+#define FLASH_OPTCR_nRST_STOP_Msk      (0x1UL << FLASH_OPTCR_nRST_STOP_Pos)     /*!< 0x00000040 */
+#define FLASH_OPTCR_nRST_STOP          FLASH_OPTCR_nRST_STOP_Msk               
+#define FLASH_OPTCR_nRST_STDBY_Pos     (7U)                                    
+#define FLASH_OPTCR_nRST_STDBY_Msk     (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos)    /*!< 0x00000080 */
+#define FLASH_OPTCR_nRST_STDBY         FLASH_OPTCR_nRST_STDBY_Msk              
+#define FLASH_OPTCR_RDP_Pos            (8U)                                    
+#define FLASH_OPTCR_RDP_Msk            (0xFFUL << FLASH_OPTCR_RDP_Pos)          /*!< 0x0000FF00 */
+#define FLASH_OPTCR_RDP                FLASH_OPTCR_RDP_Msk                     
+#define FLASH_OPTCR_RDP_0              (0x01UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000100 */
+#define FLASH_OPTCR_RDP_1              (0x02UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000200 */
+#define FLASH_OPTCR_RDP_2              (0x04UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000400 */
+#define FLASH_OPTCR_RDP_3              (0x08UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00000800 */
+#define FLASH_OPTCR_RDP_4              (0x10UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00001000 */
+#define FLASH_OPTCR_RDP_5              (0x20UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00002000 */
+#define FLASH_OPTCR_RDP_6              (0x40UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00004000 */
+#define FLASH_OPTCR_RDP_7              (0x80UL << FLASH_OPTCR_RDP_Pos)          /*!< 0x00008000 */
+#define FLASH_OPTCR_nWRP_Pos           (16U)                                   
+#define FLASH_OPTCR_nWRP_Msk           (0xFFFUL << FLASH_OPTCR_nWRP_Pos)        /*!< 0x0FFF0000 */
+#define FLASH_OPTCR_nWRP               FLASH_OPTCR_nWRP_Msk                    
+#define FLASH_OPTCR_nWRP_0             0x00010000U                             
+#define FLASH_OPTCR_nWRP_1             0x00020000U                             
+#define FLASH_OPTCR_nWRP_2             0x00040000U                             
+#define FLASH_OPTCR_nWRP_3             0x00080000U                             
+#define FLASH_OPTCR_nWRP_4             0x00100000U                             
+#define FLASH_OPTCR_nWRP_5             0x00200000U                             
+#define FLASH_OPTCR_nWRP_6             0x00400000U                             
+#define FLASH_OPTCR_nWRP_7             0x00800000U                             
+#define FLASH_OPTCR_nWRP_8             0x01000000U                             
+#define FLASH_OPTCR_nWRP_9             0x02000000U                             
+#define FLASH_OPTCR_nWRP_10            0x04000000U                             
+#define FLASH_OPTCR_nWRP_11            0x08000000U                             
+                                             
+/******************  Bits definition for FLASH_OPTCR1 register  ***************/
+#define FLASH_OPTCR1_nWRP_Pos          (16U)                                   
+#define FLASH_OPTCR1_nWRP_Msk          (0xFFFUL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x0FFF0000 */
+#define FLASH_OPTCR1_nWRP              FLASH_OPTCR1_nWRP_Msk                   
+#define FLASH_OPTCR1_nWRP_0            (0x001UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00010000 */
+#define FLASH_OPTCR1_nWRP_1            (0x002UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00020000 */
+#define FLASH_OPTCR1_nWRP_2            (0x004UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00040000 */
+#define FLASH_OPTCR1_nWRP_3            (0x008UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00080000 */
+#define FLASH_OPTCR1_nWRP_4            (0x010UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00100000 */
+#define FLASH_OPTCR1_nWRP_5            (0x020UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00200000 */
+#define FLASH_OPTCR1_nWRP_6            (0x040UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00400000 */
+#define FLASH_OPTCR1_nWRP_7            (0x080UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x00800000 */
+#define FLASH_OPTCR1_nWRP_8            (0x100UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x01000000 */
+#define FLASH_OPTCR1_nWRP_9            (0x200UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x02000000 */
+#define FLASH_OPTCR1_nWRP_10           (0x400UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x04000000 */
+#define FLASH_OPTCR1_nWRP_11           (0x800UL << FLASH_OPTCR1_nWRP_Pos)       /*!< 0x08000000 */
+
+/******************************************************************************/
+/*                                                                            */
+/*                   Flexible Static Memory Controller                        */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for FSMC_BCR1 register  *******************/
+#define FSMC_BCR1_MBKEN_Pos          (0U)                                      
+#define FSMC_BCR1_MBKEN_Msk          (0x1UL << FSMC_BCR1_MBKEN_Pos)             /*!< 0x00000001 */
+#define FSMC_BCR1_MBKEN              FSMC_BCR1_MBKEN_Msk                       /*!<Memory bank enable bit                 */
+#define FSMC_BCR1_MUXEN_Pos          (1U)                                      
+#define FSMC_BCR1_MUXEN_Msk          (0x1UL << FSMC_BCR1_MUXEN_Pos)             /*!< 0x00000002 */
+#define FSMC_BCR1_MUXEN              FSMC_BCR1_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */
+
+#define FSMC_BCR1_MTYP_Pos           (2U)                                      
+#define FSMC_BCR1_MTYP_Msk           (0x3UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x0000000C */
+#define FSMC_BCR1_MTYP               FSMC_BCR1_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */
+#define FSMC_BCR1_MTYP_0             (0x1UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000004 */
+#define FSMC_BCR1_MTYP_1             (0x2UL << FSMC_BCR1_MTYP_Pos)              /*!< 0x00000008 */
+
+#define FSMC_BCR1_MWID_Pos           (4U)                                      
+#define FSMC_BCR1_MWID_Msk           (0x3UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000030 */
+#define FSMC_BCR1_MWID               FSMC_BCR1_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR1_MWID_0             (0x1UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000010 */
+#define FSMC_BCR1_MWID_1             (0x2UL << FSMC_BCR1_MWID_Pos)              /*!< 0x00000020 */
+
+#define FSMC_BCR1_FACCEN_Pos         (6U)                                      
+#define FSMC_BCR1_FACCEN_Msk         (0x1UL << FSMC_BCR1_FACCEN_Pos)            /*!< 0x00000040 */
+#define FSMC_BCR1_FACCEN             FSMC_BCR1_FACCEN_Msk                      /*!<Flash access enable                    */
+#define FSMC_BCR1_BURSTEN_Pos        (8U)                                      
+#define FSMC_BCR1_BURSTEN_Msk        (0x1UL << FSMC_BCR1_BURSTEN_Pos)           /*!< 0x00000100 */
+#define FSMC_BCR1_BURSTEN            FSMC_BCR1_BURSTEN_Msk                     /*!<Burst enable bit                       */
+#define FSMC_BCR1_WAITPOL_Pos        (9U)                                      
+#define FSMC_BCR1_WAITPOL_Msk        (0x1UL << FSMC_BCR1_WAITPOL_Pos)           /*!< 0x00000200 */
+#define FSMC_BCR1_WAITPOL            FSMC_BCR1_WAITPOL_Msk                     /*!<Wait signal polarity bit               */
+#define FSMC_BCR1_WRAPMOD_Pos        (10U)                                     
+#define FSMC_BCR1_WRAPMOD_Msk        (0x1UL << FSMC_BCR1_WRAPMOD_Pos)           /*!< 0x00000400 */
+#define FSMC_BCR1_WRAPMOD            FSMC_BCR1_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */
+#define FSMC_BCR1_WAITCFG_Pos        (11U)                                     
+#define FSMC_BCR1_WAITCFG_Msk        (0x1UL << FSMC_BCR1_WAITCFG_Pos)           /*!< 0x00000800 */
+#define FSMC_BCR1_WAITCFG            FSMC_BCR1_WAITCFG_Msk                     /*!<Wait timing configuration              */
+#define FSMC_BCR1_WREN_Pos           (12U)                                     
+#define FSMC_BCR1_WREN_Msk           (0x1UL << FSMC_BCR1_WREN_Pos)              /*!< 0x00001000 */
+#define FSMC_BCR1_WREN               FSMC_BCR1_WREN_Msk                        /*!<Write enable bit                       */
+#define FSMC_BCR1_WAITEN_Pos         (13U)                                     
+#define FSMC_BCR1_WAITEN_Msk         (0x1UL << FSMC_BCR1_WAITEN_Pos)            /*!< 0x00002000 */
+#define FSMC_BCR1_WAITEN             FSMC_BCR1_WAITEN_Msk                      /*!<Wait enable bit                        */
+#define FSMC_BCR1_EXTMOD_Pos         (14U)                                     
+#define FSMC_BCR1_EXTMOD_Msk         (0x1UL << FSMC_BCR1_EXTMOD_Pos)            /*!< 0x00004000 */
+#define FSMC_BCR1_EXTMOD             FSMC_BCR1_EXTMOD_Msk                      /*!<Extended mode enable                   */
+#define FSMC_BCR1_ASYNCWAIT_Pos      (15U)                                     
+#define FSMC_BCR1_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR1_ASYNCWAIT_Pos)         /*!< 0x00008000 */
+#define FSMC_BCR1_ASYNCWAIT          FSMC_BCR1_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */
+#define FSMC_BCR1_CPSIZE_Pos         (16U)                                     
+#define FSMC_BCR1_CPSIZE_Msk         (0x7UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00070000 */
+#define FSMC_BCR1_CPSIZE             FSMC_BCR1_CPSIZE_Msk                      /*!<CRAM page size */
+#define FSMC_BCR1_CPSIZE_0           (0x1UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00010000 */
+#define FSMC_BCR1_CPSIZE_1           (0x2UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00020000 */
+#define FSMC_BCR1_CPSIZE_2           (0x4UL << FSMC_BCR1_CPSIZE_Pos)            /*!< 0x00040000 */
+#define FSMC_BCR1_CBURSTRW_Pos       (19U)                                     
+#define FSMC_BCR1_CBURSTRW_Msk       (0x1UL << FSMC_BCR1_CBURSTRW_Pos)          /*!< 0x00080000 */
+#define FSMC_BCR1_CBURSTRW           FSMC_BCR1_CBURSTRW_Msk                    /*!<Write burst enable                     */
+
+/******************  Bit definition for FSMC_BCR2 register  *******************/
+#define FSMC_BCR2_MBKEN_Pos          (0U)                                      
+#define FSMC_BCR2_MBKEN_Msk          (0x1UL << FSMC_BCR2_MBKEN_Pos)             /*!< 0x00000001 */
+#define FSMC_BCR2_MBKEN              FSMC_BCR2_MBKEN_Msk                       /*!<Memory bank enable bit                */
+#define FSMC_BCR2_MUXEN_Pos          (1U)                                      
+#define FSMC_BCR2_MUXEN_Msk          (0x1UL << FSMC_BCR2_MUXEN_Pos)             /*!< 0x00000002 */
+#define FSMC_BCR2_MUXEN              FSMC_BCR2_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */
+
+#define FSMC_BCR2_MTYP_Pos           (2U)                                      
+#define FSMC_BCR2_MTYP_Msk           (0x3UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x0000000C */
+#define FSMC_BCR2_MTYP               FSMC_BCR2_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */
+#define FSMC_BCR2_MTYP_0             (0x1UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000004 */
+#define FSMC_BCR2_MTYP_1             (0x2UL << FSMC_BCR2_MTYP_Pos)              /*!< 0x00000008 */
+
+#define FSMC_BCR2_MWID_Pos           (4U)                                      
+#define FSMC_BCR2_MWID_Msk           (0x3UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000030 */
+#define FSMC_BCR2_MWID               FSMC_BCR2_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR2_MWID_0             (0x1UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000010 */
+#define FSMC_BCR2_MWID_1             (0x2UL << FSMC_BCR2_MWID_Pos)              /*!< 0x00000020 */
+
+#define FSMC_BCR2_FACCEN_Pos         (6U)                                      
+#define FSMC_BCR2_FACCEN_Msk         (0x1UL << FSMC_BCR2_FACCEN_Pos)            /*!< 0x00000040 */
+#define FSMC_BCR2_FACCEN             FSMC_BCR2_FACCEN_Msk                      /*!<Flash access enable                    */
+#define FSMC_BCR2_BURSTEN_Pos        (8U)                                      
+#define FSMC_BCR2_BURSTEN_Msk        (0x1UL << FSMC_BCR2_BURSTEN_Pos)           /*!< 0x00000100 */
+#define FSMC_BCR2_BURSTEN            FSMC_BCR2_BURSTEN_Msk                     /*!<Burst enable bit                       */
+#define FSMC_BCR2_WAITPOL_Pos        (9U)                                      
+#define FSMC_BCR2_WAITPOL_Msk        (0x1UL << FSMC_BCR2_WAITPOL_Pos)           /*!< 0x00000200 */
+#define FSMC_BCR2_WAITPOL            FSMC_BCR2_WAITPOL_Msk                     /*!<Wait signal polarity bit               */
+#define FSMC_BCR2_WRAPMOD_Pos        (10U)                                     
+#define FSMC_BCR2_WRAPMOD_Msk        (0x1UL << FSMC_BCR2_WRAPMOD_Pos)           /*!< 0x00000400 */
+#define FSMC_BCR2_WRAPMOD            FSMC_BCR2_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */
+#define FSMC_BCR2_WAITCFG_Pos        (11U)                                     
+#define FSMC_BCR2_WAITCFG_Msk        (0x1UL << FSMC_BCR2_WAITCFG_Pos)           /*!< 0x00000800 */
+#define FSMC_BCR2_WAITCFG            FSMC_BCR2_WAITCFG_Msk                     /*!<Wait timing configuration              */
+#define FSMC_BCR2_WREN_Pos           (12U)                                     
+#define FSMC_BCR2_WREN_Msk           (0x1UL << FSMC_BCR2_WREN_Pos)              /*!< 0x00001000 */
+#define FSMC_BCR2_WREN               FSMC_BCR2_WREN_Msk                        /*!<Write enable bit                       */
+#define FSMC_BCR2_WAITEN_Pos         (13U)                                     
+#define FSMC_BCR2_WAITEN_Msk         (0x1UL << FSMC_BCR2_WAITEN_Pos)            /*!< 0x00002000 */
+#define FSMC_BCR2_WAITEN             FSMC_BCR2_WAITEN_Msk                      /*!<Wait enable bit                        */
+#define FSMC_BCR2_EXTMOD_Pos         (14U)                                     
+#define FSMC_BCR2_EXTMOD_Msk         (0x1UL << FSMC_BCR2_EXTMOD_Pos)            /*!< 0x00004000 */
+#define FSMC_BCR2_EXTMOD             FSMC_BCR2_EXTMOD_Msk                      /*!<Extended mode enable                   */
+#define FSMC_BCR2_ASYNCWAIT_Pos      (15U)                                     
+#define FSMC_BCR2_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR2_ASYNCWAIT_Pos)         /*!< 0x00008000 */
+#define FSMC_BCR2_ASYNCWAIT          FSMC_BCR2_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */
+#define FSMC_BCR2_CPSIZE_Pos         (16U)                                     
+#define FSMC_BCR2_CPSIZE_Msk         (0x7UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00070000 */
+#define FSMC_BCR2_CPSIZE             FSMC_BCR2_CPSIZE_Msk                      /*!<CRAM page size */
+#define FSMC_BCR2_CPSIZE_0           (0x1UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00010000 */
+#define FSMC_BCR2_CPSIZE_1           (0x2UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00020000 */
+#define FSMC_BCR2_CPSIZE_2           (0x4UL << FSMC_BCR2_CPSIZE_Pos)            /*!< 0x00040000 */
+#define FSMC_BCR2_CBURSTRW_Pos       (19U)                                     
+#define FSMC_BCR2_CBURSTRW_Msk       (0x1UL << FSMC_BCR2_CBURSTRW_Pos)          /*!< 0x00080000 */
+#define FSMC_BCR2_CBURSTRW           FSMC_BCR2_CBURSTRW_Msk                    /*!<Write burst enable                     */
+
+/******************  Bit definition for FSMC_BCR3 register  *******************/
+#define FSMC_BCR3_MBKEN_Pos          (0U)                                      
+#define FSMC_BCR3_MBKEN_Msk          (0x1UL << FSMC_BCR3_MBKEN_Pos)             /*!< 0x00000001 */
+#define FSMC_BCR3_MBKEN              FSMC_BCR3_MBKEN_Msk                       /*!<Memory bank enable bit                 */
+#define FSMC_BCR3_MUXEN_Pos          (1U)                                      
+#define FSMC_BCR3_MUXEN_Msk          (0x1UL << FSMC_BCR3_MUXEN_Pos)             /*!< 0x00000002 */
+#define FSMC_BCR3_MUXEN              FSMC_BCR3_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */
+
+#define FSMC_BCR3_MTYP_Pos           (2U)                                      
+#define FSMC_BCR3_MTYP_Msk           (0x3UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x0000000C */
+#define FSMC_BCR3_MTYP               FSMC_BCR3_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */
+#define FSMC_BCR3_MTYP_0             (0x1UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000004 */
+#define FSMC_BCR3_MTYP_1             (0x2UL << FSMC_BCR3_MTYP_Pos)              /*!< 0x00000008 */
+
+#define FSMC_BCR3_MWID_Pos           (4U)                                      
+#define FSMC_BCR3_MWID_Msk           (0x3UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000030 */
+#define FSMC_BCR3_MWID               FSMC_BCR3_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR3_MWID_0             (0x1UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000010 */
+#define FSMC_BCR3_MWID_1             (0x2UL << FSMC_BCR3_MWID_Pos)              /*!< 0x00000020 */
+
+#define FSMC_BCR3_FACCEN_Pos         (6U)                                      
+#define FSMC_BCR3_FACCEN_Msk         (0x1UL << FSMC_BCR3_FACCEN_Pos)            /*!< 0x00000040 */
+#define FSMC_BCR3_FACCEN             FSMC_BCR3_FACCEN_Msk                      /*!<Flash access enable                    */
+#define FSMC_BCR3_BURSTEN_Pos        (8U)                                      
+#define FSMC_BCR3_BURSTEN_Msk        (0x1UL << FSMC_BCR3_BURSTEN_Pos)           /*!< 0x00000100 */
+#define FSMC_BCR3_BURSTEN            FSMC_BCR3_BURSTEN_Msk                     /*!<Burst enable bit                       */
+#define FSMC_BCR3_WAITPOL_Pos        (9U)                                      
+#define FSMC_BCR3_WAITPOL_Msk        (0x1UL << FSMC_BCR3_WAITPOL_Pos)           /*!< 0x00000200 */
+#define FSMC_BCR3_WAITPOL            FSMC_BCR3_WAITPOL_Msk                     /*!<Wait signal polarity bit               */
+#define FSMC_BCR3_WRAPMOD_Pos        (10U)                                     
+#define FSMC_BCR3_WRAPMOD_Msk        (0x1UL << FSMC_BCR3_WRAPMOD_Pos)           /*!< 0x00000400 */
+#define FSMC_BCR3_WRAPMOD            FSMC_BCR3_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */
+#define FSMC_BCR3_WAITCFG_Pos        (11U)                                     
+#define FSMC_BCR3_WAITCFG_Msk        (0x1UL << FSMC_BCR3_WAITCFG_Pos)           /*!< 0x00000800 */
+#define FSMC_BCR3_WAITCFG            FSMC_BCR3_WAITCFG_Msk                     /*!<Wait timing configuration              */
+#define FSMC_BCR3_WREN_Pos           (12U)                                     
+#define FSMC_BCR3_WREN_Msk           (0x1UL << FSMC_BCR3_WREN_Pos)              /*!< 0x00001000 */
+#define FSMC_BCR3_WREN               FSMC_BCR3_WREN_Msk                        /*!<Write enable bit                       */
+#define FSMC_BCR3_WAITEN_Pos         (13U)                                     
+#define FSMC_BCR3_WAITEN_Msk         (0x1UL << FSMC_BCR3_WAITEN_Pos)            /*!< 0x00002000 */
+#define FSMC_BCR3_WAITEN             FSMC_BCR3_WAITEN_Msk                      /*!<Wait enable bit                        */
+#define FSMC_BCR3_EXTMOD_Pos         (14U)                                     
+#define FSMC_BCR3_EXTMOD_Msk         (0x1UL << FSMC_BCR3_EXTMOD_Pos)            /*!< 0x00004000 */
+#define FSMC_BCR3_EXTMOD             FSMC_BCR3_EXTMOD_Msk                      /*!<Extended mode enable                   */
+#define FSMC_BCR3_ASYNCWAIT_Pos      (15U)                                     
+#define FSMC_BCR3_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR3_ASYNCWAIT_Pos)         /*!< 0x00008000 */
+#define FSMC_BCR3_ASYNCWAIT          FSMC_BCR3_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */
+#define FSMC_BCR3_CPSIZE_Pos         (16U)                                     
+#define FSMC_BCR3_CPSIZE_Msk         (0x7UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00070000 */
+#define FSMC_BCR3_CPSIZE             FSMC_BCR3_CPSIZE_Msk                      /*!<CRAM page size */
+#define FSMC_BCR3_CPSIZE_0           (0x1UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00010000 */
+#define FSMC_BCR3_CPSIZE_1           (0x2UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00020000 */
+#define FSMC_BCR3_CPSIZE_2           (0x4UL << FSMC_BCR3_CPSIZE_Pos)            /*!< 0x00040000 */
+#define FSMC_BCR3_CBURSTRW_Pos       (19U)                                     
+#define FSMC_BCR3_CBURSTRW_Msk       (0x1UL << FSMC_BCR3_CBURSTRW_Pos)          /*!< 0x00080000 */
+#define FSMC_BCR3_CBURSTRW           FSMC_BCR3_CBURSTRW_Msk                    /*!<Write burst enable                     */
+
+/******************  Bit definition for FSMC_BCR4 register  *******************/
+#define FSMC_BCR4_MBKEN_Pos          (0U)                                      
+#define FSMC_BCR4_MBKEN_Msk          (0x1UL << FSMC_BCR4_MBKEN_Pos)             /*!< 0x00000001 */
+#define FSMC_BCR4_MBKEN              FSMC_BCR4_MBKEN_Msk                       /*!<Memory bank enable bit */
+#define FSMC_BCR4_MUXEN_Pos          (1U)                                      
+#define FSMC_BCR4_MUXEN_Msk          (0x1UL << FSMC_BCR4_MUXEN_Pos)             /*!< 0x00000002 */
+#define FSMC_BCR4_MUXEN              FSMC_BCR4_MUXEN_Msk                       /*!<Address/data multiplexing enable bit   */
+
+#define FSMC_BCR4_MTYP_Pos           (2U)                                      
+#define FSMC_BCR4_MTYP_Msk           (0x3UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x0000000C */
+#define FSMC_BCR4_MTYP               FSMC_BCR4_MTYP_Msk                        /*!<MTYP[1:0] bits (Memory type)           */
+#define FSMC_BCR4_MTYP_0             (0x1UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000004 */
+#define FSMC_BCR4_MTYP_1             (0x2UL << FSMC_BCR4_MTYP_Pos)              /*!< 0x00000008 */
+
+#define FSMC_BCR4_MWID_Pos           (4U)                                      
+#define FSMC_BCR4_MWID_Msk           (0x3UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000030 */
+#define FSMC_BCR4_MWID               FSMC_BCR4_MWID_Msk                        /*!<MWID[1:0] bits (Memory data bus width) */
+#define FSMC_BCR4_MWID_0             (0x1UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000010 */
+#define FSMC_BCR4_MWID_1             (0x2UL << FSMC_BCR4_MWID_Pos)              /*!< 0x00000020 */
+
+#define FSMC_BCR4_FACCEN_Pos         (6U)                                      
+#define FSMC_BCR4_FACCEN_Msk         (0x1UL << FSMC_BCR4_FACCEN_Pos)            /*!< 0x00000040 */
+#define FSMC_BCR4_FACCEN             FSMC_BCR4_FACCEN_Msk                      /*!<Flash access enable                    */
+#define FSMC_BCR4_BURSTEN_Pos        (8U)                                      
+#define FSMC_BCR4_BURSTEN_Msk        (0x1UL << FSMC_BCR4_BURSTEN_Pos)           /*!< 0x00000100 */
+#define FSMC_BCR4_BURSTEN            FSMC_BCR4_BURSTEN_Msk                     /*!<Burst enable bit                       */
+#define FSMC_BCR4_WAITPOL_Pos        (9U)                                      
+#define FSMC_BCR4_WAITPOL_Msk        (0x1UL << FSMC_BCR4_WAITPOL_Pos)           /*!< 0x00000200 */
+#define FSMC_BCR4_WAITPOL            FSMC_BCR4_WAITPOL_Msk                     /*!<Wait signal polarity bit               */
+#define FSMC_BCR4_WRAPMOD_Pos        (10U)                                     
+#define FSMC_BCR4_WRAPMOD_Msk        (0x1UL << FSMC_BCR4_WRAPMOD_Pos)           /*!< 0x00000400 */
+#define FSMC_BCR4_WRAPMOD            FSMC_BCR4_WRAPMOD_Msk                     /*!<Wrapped burst mode support             */
+#define FSMC_BCR4_WAITCFG_Pos        (11U)                                     
+#define FSMC_BCR4_WAITCFG_Msk        (0x1UL << FSMC_BCR4_WAITCFG_Pos)           /*!< 0x00000800 */
+#define FSMC_BCR4_WAITCFG            FSMC_BCR4_WAITCFG_Msk                     /*!<Wait timing configuration              */
+#define FSMC_BCR4_WREN_Pos           (12U)                                     
+#define FSMC_BCR4_WREN_Msk           (0x1UL << FSMC_BCR4_WREN_Pos)              /*!< 0x00001000 */
+#define FSMC_BCR4_WREN               FSMC_BCR4_WREN_Msk                        /*!<Write enable bit                       */
+#define FSMC_BCR4_WAITEN_Pos         (13U)                                     
+#define FSMC_BCR4_WAITEN_Msk         (0x1UL << FSMC_BCR4_WAITEN_Pos)            /*!< 0x00002000 */
+#define FSMC_BCR4_WAITEN             FSMC_BCR4_WAITEN_Msk                      /*!<Wait enable bit                        */
+#define FSMC_BCR4_EXTMOD_Pos         (14U)                                     
+#define FSMC_BCR4_EXTMOD_Msk         (0x1UL << FSMC_BCR4_EXTMOD_Pos)            /*!< 0x00004000 */
+#define FSMC_BCR4_EXTMOD             FSMC_BCR4_EXTMOD_Msk                      /*!<Extended mode enable                   */
+#define FSMC_BCR4_ASYNCWAIT_Pos      (15U)                                     
+#define FSMC_BCR4_ASYNCWAIT_Msk      (0x1UL << FSMC_BCR4_ASYNCWAIT_Pos)         /*!< 0x00008000 */
+#define FSMC_BCR4_ASYNCWAIT          FSMC_BCR4_ASYNCWAIT_Msk                   /*!<Asynchronous wait                      */
+#define FSMC_BCR4_CPSIZE_Pos         (16U)                                     
+#define FSMC_BCR4_CPSIZE_Msk         (0x7UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00070000 */
+#define FSMC_BCR4_CPSIZE             FSMC_BCR4_CPSIZE_Msk                      /*!<CRAM page size */
+#define FSMC_BCR4_CPSIZE_0           (0x1UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00010000 */
+#define FSMC_BCR4_CPSIZE_1           (0x2UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00020000 */
+#define FSMC_BCR4_CPSIZE_2           (0x4UL << FSMC_BCR4_CPSIZE_Pos)            /*!< 0x00040000 */
+#define FSMC_BCR4_CBURSTRW_Pos       (19U)                                     
+#define FSMC_BCR4_CBURSTRW_Msk       (0x1UL << FSMC_BCR4_CBURSTRW_Pos)          /*!< 0x00080000 */
+#define FSMC_BCR4_CBURSTRW           FSMC_BCR4_CBURSTRW_Msk                    /*!<Write burst enable                     */
+
+/******************  Bit definition for FSMC_BTR1 register  ******************/
+#define FSMC_BTR1_ADDSET_Pos         (0U)                                      
+#define FSMC_BTR1_ADDSET_Msk         (0xFUL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x0000000F */
+#define FSMC_BTR1_ADDSET             FSMC_BTR1_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR1_ADDSET_0           (0x1UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000001 */
+#define FSMC_BTR1_ADDSET_1           (0x2UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000002 */
+#define FSMC_BTR1_ADDSET_2           (0x4UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000004 */
+#define FSMC_BTR1_ADDSET_3           (0x8UL << FSMC_BTR1_ADDSET_Pos)            /*!< 0x00000008 */
+
+#define FSMC_BTR1_ADDHLD_Pos         (4U)                                      
+#define FSMC_BTR1_ADDHLD_Msk         (0xFUL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x000000F0 */
+#define FSMC_BTR1_ADDHLD             FSMC_BTR1_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR1_ADDHLD_0           (0x1UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000010 */
+#define FSMC_BTR1_ADDHLD_1           (0x2UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000020 */
+#define FSMC_BTR1_ADDHLD_2           (0x4UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000040 */
+#define FSMC_BTR1_ADDHLD_3           (0x8UL << FSMC_BTR1_ADDHLD_Pos)            /*!< 0x00000080 */
+
+#define FSMC_BTR1_DATAST_Pos         (8U)                                      
+#define FSMC_BTR1_DATAST_Msk         (0xFFUL << FSMC_BTR1_DATAST_Pos)           /*!< 0x0000FF00 */
+#define FSMC_BTR1_DATAST             FSMC_BTR1_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR1_DATAST_0           (0x01UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000100 */
+#define FSMC_BTR1_DATAST_1           (0x02UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000200 */
+#define FSMC_BTR1_DATAST_2           (0x04UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000400 */
+#define FSMC_BTR1_DATAST_3           (0x08UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00000800 */
+#define FSMC_BTR1_DATAST_4           (0x10UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00001000 */
+#define FSMC_BTR1_DATAST_5           (0x20UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00002000 */
+#define FSMC_BTR1_DATAST_6           (0x40UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00004000 */
+#define FSMC_BTR1_DATAST_7           (0x80UL << FSMC_BTR1_DATAST_Pos)           /*!< 0x00008000 */
+
+#define FSMC_BTR1_BUSTURN_Pos        (16U)                                     
+#define FSMC_BTR1_BUSTURN_Msk        (0xFUL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x000F0000 */
+#define FSMC_BTR1_BUSTURN            FSMC_BTR1_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR1_BUSTURN_0          (0x1UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00010000 */
+#define FSMC_BTR1_BUSTURN_1          (0x2UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00020000 */
+#define FSMC_BTR1_BUSTURN_2          (0x4UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00040000 */
+#define FSMC_BTR1_BUSTURN_3          (0x8UL << FSMC_BTR1_BUSTURN_Pos)           /*!< 0x00080000 */
+
+#define FSMC_BTR1_CLKDIV_Pos         (20U)                                     
+#define FSMC_BTR1_CLKDIV_Msk         (0xFUL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00F00000 */
+#define FSMC_BTR1_CLKDIV             FSMC_BTR1_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR1_CLKDIV_0           (0x1UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00100000 */
+#define FSMC_BTR1_CLKDIV_1           (0x2UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00200000 */
+#define FSMC_BTR1_CLKDIV_2           (0x4UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00400000 */
+#define FSMC_BTR1_CLKDIV_3           (0x8UL << FSMC_BTR1_CLKDIV_Pos)            /*!< 0x00800000 */
+
+#define FSMC_BTR1_DATLAT_Pos         (24U)                                     
+#define FSMC_BTR1_DATLAT_Msk         (0xFUL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x0F000000 */
+#define FSMC_BTR1_DATLAT             FSMC_BTR1_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR1_DATLAT_0           (0x1UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x01000000 */
+#define FSMC_BTR1_DATLAT_1           (0x2UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x02000000 */
+#define FSMC_BTR1_DATLAT_2           (0x4UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x04000000 */
+#define FSMC_BTR1_DATLAT_3           (0x8UL << FSMC_BTR1_DATLAT_Pos)            /*!< 0x08000000 */
+
+#define FSMC_BTR1_ACCMOD_Pos         (28U)                                     
+#define FSMC_BTR1_ACCMOD_Msk         (0x3UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x30000000 */
+#define FSMC_BTR1_ACCMOD             FSMC_BTR1_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR1_ACCMOD_0           (0x1UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x10000000 */
+#define FSMC_BTR1_ACCMOD_1           (0x2UL << FSMC_BTR1_ACCMOD_Pos)            /*!< 0x20000000 */
+
+/******************  Bit definition for FSMC_BTR2 register  *******************/
+#define FSMC_BTR2_ADDSET_Pos         (0U)                                      
+#define FSMC_BTR2_ADDSET_Msk         (0xFUL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x0000000F */
+#define FSMC_BTR2_ADDSET             FSMC_BTR2_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR2_ADDSET_0           (0x1UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000001 */
+#define FSMC_BTR2_ADDSET_1           (0x2UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000002 */
+#define FSMC_BTR2_ADDSET_2           (0x4UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000004 */
+#define FSMC_BTR2_ADDSET_3           (0x8UL << FSMC_BTR2_ADDSET_Pos)            /*!< 0x00000008 */
+
+#define FSMC_BTR2_ADDHLD_Pos         (4U)                                      
+#define FSMC_BTR2_ADDHLD_Msk         (0xFUL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x000000F0 */
+#define FSMC_BTR2_ADDHLD             FSMC_BTR2_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR2_ADDHLD_0           (0x1UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000010 */
+#define FSMC_BTR2_ADDHLD_1           (0x2UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000020 */
+#define FSMC_BTR2_ADDHLD_2           (0x4UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000040 */
+#define FSMC_BTR2_ADDHLD_3           (0x8UL << FSMC_BTR2_ADDHLD_Pos)            /*!< 0x00000080 */
+
+#define FSMC_BTR2_DATAST_Pos         (8U)                                      
+#define FSMC_BTR2_DATAST_Msk         (0xFFUL << FSMC_BTR2_DATAST_Pos)           /*!< 0x0000FF00 */
+#define FSMC_BTR2_DATAST             FSMC_BTR2_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR2_DATAST_0           (0x01UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000100 */
+#define FSMC_BTR2_DATAST_1           (0x02UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000200 */
+#define FSMC_BTR2_DATAST_2           (0x04UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000400 */
+#define FSMC_BTR2_DATAST_3           (0x08UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00000800 */
+#define FSMC_BTR2_DATAST_4           (0x10UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00001000 */
+#define FSMC_BTR2_DATAST_5           (0x20UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00002000 */
+#define FSMC_BTR2_DATAST_6           (0x40UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00004000 */
+#define FSMC_BTR2_DATAST_7           (0x80UL << FSMC_BTR2_DATAST_Pos)           /*!< 0x00008000 */
+
+#define FSMC_BTR2_BUSTURN_Pos        (16U)                                     
+#define FSMC_BTR2_BUSTURN_Msk        (0xFUL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x000F0000 */
+#define FSMC_BTR2_BUSTURN            FSMC_BTR2_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR2_BUSTURN_0          (0x1UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00010000 */
+#define FSMC_BTR2_BUSTURN_1          (0x2UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00020000 */
+#define FSMC_BTR2_BUSTURN_2          (0x4UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00040000 */
+#define FSMC_BTR2_BUSTURN_3          (0x8UL << FSMC_BTR2_BUSTURN_Pos)           /*!< 0x00080000 */
+
+#define FSMC_BTR2_CLKDIV_Pos         (20U)                                     
+#define FSMC_BTR2_CLKDIV_Msk         (0xFUL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00F00000 */
+#define FSMC_BTR2_CLKDIV             FSMC_BTR2_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR2_CLKDIV_0           (0x1UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00100000 */
+#define FSMC_BTR2_CLKDIV_1           (0x2UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00200000 */
+#define FSMC_BTR2_CLKDIV_2           (0x4UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00400000 */
+#define FSMC_BTR2_CLKDIV_3           (0x8UL << FSMC_BTR2_CLKDIV_Pos)            /*!< 0x00800000 */
+
+#define FSMC_BTR2_DATLAT_Pos         (24U)                                     
+#define FSMC_BTR2_DATLAT_Msk         (0xFUL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x0F000000 */
+#define FSMC_BTR2_DATLAT             FSMC_BTR2_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR2_DATLAT_0           (0x1UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x01000000 */
+#define FSMC_BTR2_DATLAT_1           (0x2UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x02000000 */
+#define FSMC_BTR2_DATLAT_2           (0x4UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x04000000 */
+#define FSMC_BTR2_DATLAT_3           (0x8UL << FSMC_BTR2_DATLAT_Pos)            /*!< 0x08000000 */
+
+#define FSMC_BTR2_ACCMOD_Pos         (28U)                                     
+#define FSMC_BTR2_ACCMOD_Msk         (0x3UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x30000000 */
+#define FSMC_BTR2_ACCMOD             FSMC_BTR2_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR2_ACCMOD_0           (0x1UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x10000000 */
+#define FSMC_BTR2_ACCMOD_1           (0x2UL << FSMC_BTR2_ACCMOD_Pos)            /*!< 0x20000000 */
+
+/*******************  Bit definition for FSMC_BTR3 register  *******************/
+#define FSMC_BTR3_ADDSET_Pos         (0U)                                      
+#define FSMC_BTR3_ADDSET_Msk         (0xFUL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x0000000F */
+#define FSMC_BTR3_ADDSET             FSMC_BTR3_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR3_ADDSET_0           (0x1UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000001 */
+#define FSMC_BTR3_ADDSET_1           (0x2UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000002 */
+#define FSMC_BTR3_ADDSET_2           (0x4UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000004 */
+#define FSMC_BTR3_ADDSET_3           (0x8UL << FSMC_BTR3_ADDSET_Pos)            /*!< 0x00000008 */
+
+#define FSMC_BTR3_ADDHLD_Pos         (4U)                                      
+#define FSMC_BTR3_ADDHLD_Msk         (0xFUL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x000000F0 */
+#define FSMC_BTR3_ADDHLD             FSMC_BTR3_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR3_ADDHLD_0           (0x1UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000010 */
+#define FSMC_BTR3_ADDHLD_1           (0x2UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000020 */
+#define FSMC_BTR3_ADDHLD_2           (0x4UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000040 */
+#define FSMC_BTR3_ADDHLD_3           (0x8UL << FSMC_BTR3_ADDHLD_Pos)            /*!< 0x00000080 */
+
+#define FSMC_BTR3_DATAST_Pos         (8U)                                      
+#define FSMC_BTR3_DATAST_Msk         (0xFFUL << FSMC_BTR3_DATAST_Pos)           /*!< 0x0000FF00 */
+#define FSMC_BTR3_DATAST             FSMC_BTR3_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR3_DATAST_0           (0x01UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000100 */
+#define FSMC_BTR3_DATAST_1           (0x02UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000200 */
+#define FSMC_BTR3_DATAST_2           (0x04UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000400 */
+#define FSMC_BTR3_DATAST_3           (0x08UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00000800 */
+#define FSMC_BTR3_DATAST_4           (0x10UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00001000 */
+#define FSMC_BTR3_DATAST_5           (0x20UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00002000 */
+#define FSMC_BTR3_DATAST_6           (0x40UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00004000 */
+#define FSMC_BTR3_DATAST_7           (0x80UL << FSMC_BTR3_DATAST_Pos)           /*!< 0x00008000 */
+
+#define FSMC_BTR3_BUSTURN_Pos        (16U)                                     
+#define FSMC_BTR3_BUSTURN_Msk        (0xFUL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x000F0000 */
+#define FSMC_BTR3_BUSTURN            FSMC_BTR3_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR3_BUSTURN_0          (0x1UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00010000 */
+#define FSMC_BTR3_BUSTURN_1          (0x2UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00020000 */
+#define FSMC_BTR3_BUSTURN_2          (0x4UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00040000 */
+#define FSMC_BTR3_BUSTURN_3          (0x8UL << FSMC_BTR3_BUSTURN_Pos)           /*!< 0x00080000 */
+
+#define FSMC_BTR3_CLKDIV_Pos         (20U)                                     
+#define FSMC_BTR3_CLKDIV_Msk         (0xFUL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00F00000 */
+#define FSMC_BTR3_CLKDIV             FSMC_BTR3_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR3_CLKDIV_0           (0x1UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00100000 */
+#define FSMC_BTR3_CLKDIV_1           (0x2UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00200000 */
+#define FSMC_BTR3_CLKDIV_2           (0x4UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00400000 */
+#define FSMC_BTR3_CLKDIV_3           (0x8UL << FSMC_BTR3_CLKDIV_Pos)            /*!< 0x00800000 */
+
+#define FSMC_BTR3_DATLAT_Pos         (24U)                                     
+#define FSMC_BTR3_DATLAT_Msk         (0xFUL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x0F000000 */
+#define FSMC_BTR3_DATLAT             FSMC_BTR3_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR3_DATLAT_0           (0x1UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x01000000 */
+#define FSMC_BTR3_DATLAT_1           (0x2UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x02000000 */
+#define FSMC_BTR3_DATLAT_2           (0x4UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x04000000 */
+#define FSMC_BTR3_DATLAT_3           (0x8UL << FSMC_BTR3_DATLAT_Pos)            /*!< 0x08000000 */
+
+#define FSMC_BTR3_ACCMOD_Pos         (28U)                                     
+#define FSMC_BTR3_ACCMOD_Msk         (0x3UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x30000000 */
+#define FSMC_BTR3_ACCMOD             FSMC_BTR3_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR3_ACCMOD_0           (0x1UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x10000000 */
+#define FSMC_BTR3_ACCMOD_1           (0x2UL << FSMC_BTR3_ACCMOD_Pos)            /*!< 0x20000000 */
+
+/******************  Bit definition for FSMC_BTR4 register  *******************/
+#define FSMC_BTR4_ADDSET_Pos         (0U)                                      
+#define FSMC_BTR4_ADDSET_Msk         (0xFUL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x0000000F */
+#define FSMC_BTR4_ADDSET             FSMC_BTR4_ADDSET_Msk                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BTR4_ADDSET_0           (0x1UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000001 */
+#define FSMC_BTR4_ADDSET_1           (0x2UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000002 */
+#define FSMC_BTR4_ADDSET_2           (0x4UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000004 */
+#define FSMC_BTR4_ADDSET_3           (0x8UL << FSMC_BTR4_ADDSET_Pos)            /*!< 0x00000008 */
+
+#define FSMC_BTR4_ADDHLD_Pos         (4U)                                      
+#define FSMC_BTR4_ADDHLD_Msk         (0xFUL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x000000F0 */
+#define FSMC_BTR4_ADDHLD             FSMC_BTR4_ADDHLD_Msk                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BTR4_ADDHLD_0           (0x1UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000010 */
+#define FSMC_BTR4_ADDHLD_1           (0x2UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000020 */
+#define FSMC_BTR4_ADDHLD_2           (0x4UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000040 */
+#define FSMC_BTR4_ADDHLD_3           (0x8UL << FSMC_BTR4_ADDHLD_Pos)            /*!< 0x00000080 */
+
+#define FSMC_BTR4_DATAST_Pos         (8U)                                      
+#define FSMC_BTR4_DATAST_Msk         (0xFFUL << FSMC_BTR4_DATAST_Pos)           /*!< 0x0000FF00 */
+#define FSMC_BTR4_DATAST             FSMC_BTR4_DATAST_Msk                      /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BTR4_DATAST_0           (0x01UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000100 */
+#define FSMC_BTR4_DATAST_1           (0x02UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000200 */
+#define FSMC_BTR4_DATAST_2           (0x04UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000400 */
+#define FSMC_BTR4_DATAST_3           (0x08UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00000800 */
+#define FSMC_BTR4_DATAST_4           (0x10UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00001000 */
+#define FSMC_BTR4_DATAST_5           (0x20UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00002000 */
+#define FSMC_BTR4_DATAST_6           (0x40UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00004000 */
+#define FSMC_BTR4_DATAST_7           (0x80UL << FSMC_BTR4_DATAST_Pos)           /*!< 0x00008000 */
+
+#define FSMC_BTR4_BUSTURN_Pos        (16U)                                     
+#define FSMC_BTR4_BUSTURN_Msk        (0xFUL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x000F0000 */
+#define FSMC_BTR4_BUSTURN            FSMC_BTR4_BUSTURN_Msk                     /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
+#define FSMC_BTR4_BUSTURN_0          (0x1UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00010000 */
+#define FSMC_BTR4_BUSTURN_1          (0x2UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00020000 */
+#define FSMC_BTR4_BUSTURN_2          (0x4UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00040000 */
+#define FSMC_BTR4_BUSTURN_3          (0x8UL << FSMC_BTR4_BUSTURN_Pos)           /*!< 0x00080000 */
+
+#define FSMC_BTR4_CLKDIV_Pos         (20U)                                     
+#define FSMC_BTR4_CLKDIV_Msk         (0xFUL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00F00000 */
+#define FSMC_BTR4_CLKDIV             FSMC_BTR4_CLKDIV_Msk                      /*!<CLKDIV[3:0] bits (Clock divide ratio) */
+#define FSMC_BTR4_CLKDIV_0           (0x1UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00100000 */
+#define FSMC_BTR4_CLKDIV_1           (0x2UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00200000 */
+#define FSMC_BTR4_CLKDIV_2           (0x4UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00400000 */
+#define FSMC_BTR4_CLKDIV_3           (0x8UL << FSMC_BTR4_CLKDIV_Pos)            /*!< 0x00800000 */
+
+#define FSMC_BTR4_DATLAT_Pos         (24U)                                     
+#define FSMC_BTR4_DATLAT_Msk         (0xFUL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x0F000000 */
+#define FSMC_BTR4_DATLAT             FSMC_BTR4_DATLAT_Msk                      /*!<DATLA[3:0] bits (Data latency) */
+#define FSMC_BTR4_DATLAT_0           (0x1UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x01000000 */
+#define FSMC_BTR4_DATLAT_1           (0x2UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x02000000 */
+#define FSMC_BTR4_DATLAT_2           (0x4UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x04000000 */
+#define FSMC_BTR4_DATLAT_3           (0x8UL << FSMC_BTR4_DATLAT_Pos)            /*!< 0x08000000 */
+
+#define FSMC_BTR4_ACCMOD_Pos         (28U)                                     
+#define FSMC_BTR4_ACCMOD_Msk         (0x3UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x30000000 */
+#define FSMC_BTR4_ACCMOD             FSMC_BTR4_ACCMOD_Msk                      /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BTR4_ACCMOD_0           (0x1UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x10000000 */
+#define FSMC_BTR4_ACCMOD_1           (0x2UL << FSMC_BTR4_ACCMOD_Pos)            /*!< 0x20000000 */
+
+/******************  Bit definition for FSMC_BWTR1 register  ******************/
+#define FSMC_BWTR1_ADDSET_Pos        (0U)                                      
+#define FSMC_BWTR1_ADDSET_Msk        (0xFUL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x0000000F */
+#define FSMC_BWTR1_ADDSET            FSMC_BWTR1_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR1_ADDSET_0          (0x1UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000001 */
+#define FSMC_BWTR1_ADDSET_1          (0x2UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000002 */
+#define FSMC_BWTR1_ADDSET_2          (0x4UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000004 */
+#define FSMC_BWTR1_ADDSET_3          (0x8UL << FSMC_BWTR1_ADDSET_Pos)           /*!< 0x00000008 */
+
+#define FSMC_BWTR1_ADDHLD_Pos        (4U)                                      
+#define FSMC_BWTR1_ADDHLD_Msk        (0xFUL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x000000F0 */
+#define FSMC_BWTR1_ADDHLD            FSMC_BWTR1_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR1_ADDHLD_0          (0x1UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000010 */
+#define FSMC_BWTR1_ADDHLD_1          (0x2UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000020 */
+#define FSMC_BWTR1_ADDHLD_2          (0x4UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000040 */
+#define FSMC_BWTR1_ADDHLD_3          (0x8UL << FSMC_BWTR1_ADDHLD_Pos)           /*!< 0x00000080 */
+
+#define FSMC_BWTR1_DATAST_Pos        (8U)                                      
+#define FSMC_BWTR1_DATAST_Msk        (0xFFUL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x0000FF00 */
+#define FSMC_BWTR1_DATAST            FSMC_BWTR1_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR1_DATAST_0          (0x01UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000100 */
+#define FSMC_BWTR1_DATAST_1          (0x02UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000200 */
+#define FSMC_BWTR1_DATAST_2          (0x04UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000400 */
+#define FSMC_BWTR1_DATAST_3          (0x08UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00000800 */
+#define FSMC_BWTR1_DATAST_4          (0x10UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00001000 */
+#define FSMC_BWTR1_DATAST_5          (0x20UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00002000 */
+#define FSMC_BWTR1_DATAST_6          (0x40UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00004000 */
+#define FSMC_BWTR1_DATAST_7          (0x80UL << FSMC_BWTR1_DATAST_Pos)          /*!< 0x00008000 */
+
+#define FSMC_BWTR1_BUSTURN_Pos       (16U)                                     
+#define FSMC_BWTR1_BUSTURN_Msk       (0xFUL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x000F0000 */
+#define FSMC_BWTR1_BUSTURN           FSMC_BWTR1_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR1_BUSTURN_0         (0x1UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00010000 */
+#define FSMC_BWTR1_BUSTURN_1         (0x2UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00020000 */
+#define FSMC_BWTR1_BUSTURN_2         (0x4UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00040000 */
+#define FSMC_BWTR1_BUSTURN_3         (0x8UL << FSMC_BWTR1_BUSTURN_Pos)          /*!< 0x00080000 */
+
+#define FSMC_BWTR1_ACCMOD_Pos        (28U)                                     
+#define FSMC_BWTR1_ACCMOD_Msk        (0x3UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x30000000 */
+#define FSMC_BWTR1_ACCMOD            FSMC_BWTR1_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR1_ACCMOD_0          (0x1UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x10000000 */
+#define FSMC_BWTR1_ACCMOD_1          (0x2UL << FSMC_BWTR1_ACCMOD_Pos)           /*!< 0x20000000 */
+
+/******************  Bit definition for FSMC_BWTR2 register  ******************/
+#define FSMC_BWTR2_ADDSET_Pos        (0U)                                      
+#define FSMC_BWTR2_ADDSET_Msk        (0xFUL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x0000000F */
+#define FSMC_BWTR2_ADDSET            FSMC_BWTR2_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR2_ADDSET_0          (0x1UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000001 */
+#define FSMC_BWTR2_ADDSET_1          (0x2UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000002 */
+#define FSMC_BWTR2_ADDSET_2          (0x4UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000004 */
+#define FSMC_BWTR2_ADDSET_3          (0x8UL << FSMC_BWTR2_ADDSET_Pos)           /*!< 0x00000008 */
+
+#define FSMC_BWTR2_ADDHLD_Pos        (4U)                                      
+#define FSMC_BWTR2_ADDHLD_Msk        (0xFUL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x000000F0 */
+#define FSMC_BWTR2_ADDHLD            FSMC_BWTR2_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR2_ADDHLD_0          (0x1UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000010 */
+#define FSMC_BWTR2_ADDHLD_1          (0x2UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000020 */
+#define FSMC_BWTR2_ADDHLD_2          (0x4UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000040 */
+#define FSMC_BWTR2_ADDHLD_3          (0x8UL << FSMC_BWTR2_ADDHLD_Pos)           /*!< 0x00000080 */
+
+#define FSMC_BWTR2_DATAST_Pos        (8U)                                      
+#define FSMC_BWTR2_DATAST_Msk        (0xFFUL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x0000FF00 */
+#define FSMC_BWTR2_DATAST            FSMC_BWTR2_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR2_DATAST_0          (0x01UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000100 */
+#define FSMC_BWTR2_DATAST_1          (0x02UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000200 */
+#define FSMC_BWTR2_DATAST_2          (0x04UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000400 */
+#define FSMC_BWTR2_DATAST_3          (0x08UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00000800 */
+#define FSMC_BWTR2_DATAST_4          (0x10UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00001000 */
+#define FSMC_BWTR2_DATAST_5          (0x20UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00002000 */
+#define FSMC_BWTR2_DATAST_6          (0x40UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00004000 */
+#define FSMC_BWTR2_DATAST_7          (0x80UL << FSMC_BWTR2_DATAST_Pos)          /*!< 0x00008000 */
+
+#define FSMC_BWTR2_BUSTURN_Pos       (16U)                                     
+#define FSMC_BWTR2_BUSTURN_Msk       (0xFUL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x000F0000 */
+#define FSMC_BWTR2_BUSTURN           FSMC_BWTR2_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR2_BUSTURN_0         (0x1UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00010000 */
+#define FSMC_BWTR2_BUSTURN_1         (0x2UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00020000 */
+#define FSMC_BWTR2_BUSTURN_2         (0x4UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00040000 */
+#define FSMC_BWTR2_BUSTURN_3         (0x8UL << FSMC_BWTR2_BUSTURN_Pos)          /*!< 0x00080000 */
+
+#define FSMC_BWTR2_ACCMOD_Pos        (28U)                                     
+#define FSMC_BWTR2_ACCMOD_Msk        (0x3UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x30000000 */
+#define FSMC_BWTR2_ACCMOD            FSMC_BWTR2_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR2_ACCMOD_0          (0x1UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x10000000 */
+#define FSMC_BWTR2_ACCMOD_1          (0x2UL << FSMC_BWTR2_ACCMOD_Pos)           /*!< 0x20000000 */
+
+/******************  Bit definition for FSMC_BWTR3 register  ******************/
+#define FSMC_BWTR3_ADDSET_Pos        (0U)                                      
+#define FSMC_BWTR3_ADDSET_Msk        (0xFUL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x0000000F */
+#define FSMC_BWTR3_ADDSET            FSMC_BWTR3_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR3_ADDSET_0          (0x1UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000001 */
+#define FSMC_BWTR3_ADDSET_1          (0x2UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000002 */
+#define FSMC_BWTR3_ADDSET_2          (0x4UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000004 */
+#define FSMC_BWTR3_ADDSET_3          (0x8UL << FSMC_BWTR3_ADDSET_Pos)           /*!< 0x00000008 */
+
+#define FSMC_BWTR3_ADDHLD_Pos        (4U)                                      
+#define FSMC_BWTR3_ADDHLD_Msk        (0xFUL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x000000F0 */
+#define FSMC_BWTR3_ADDHLD            FSMC_BWTR3_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR3_ADDHLD_0          (0x1UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000010 */
+#define FSMC_BWTR3_ADDHLD_1          (0x2UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000020 */
+#define FSMC_BWTR3_ADDHLD_2          (0x4UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000040 */
+#define FSMC_BWTR3_ADDHLD_3          (0x8UL << FSMC_BWTR3_ADDHLD_Pos)           /*!< 0x00000080 */
+
+#define FSMC_BWTR3_DATAST_Pos        (8U)                                      
+#define FSMC_BWTR3_DATAST_Msk        (0xFFUL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x0000FF00 */
+#define FSMC_BWTR3_DATAST            FSMC_BWTR3_DATAST_Msk                     /*!<DATAST [7:0] bits (Data-phase duration) */
+#define FSMC_BWTR3_DATAST_0          (0x01UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000100 */
+#define FSMC_BWTR3_DATAST_1          (0x02UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000200 */
+#define FSMC_BWTR3_DATAST_2          (0x04UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000400 */
+#define FSMC_BWTR3_DATAST_3          (0x08UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00000800 */
+#define FSMC_BWTR3_DATAST_4          (0x10UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00001000 */
+#define FSMC_BWTR3_DATAST_5          (0x20UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00002000 */
+#define FSMC_BWTR3_DATAST_6          (0x40UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00004000 */
+#define FSMC_BWTR3_DATAST_7          (0x80UL << FSMC_BWTR3_DATAST_Pos)          /*!< 0x00008000 */
+
+#define FSMC_BWTR3_BUSTURN_Pos       (16U)                                     
+#define FSMC_BWTR3_BUSTURN_Msk       (0xFUL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x000F0000 */
+#define FSMC_BWTR3_BUSTURN           FSMC_BWTR3_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR3_BUSTURN_0         (0x1UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00010000 */
+#define FSMC_BWTR3_BUSTURN_1         (0x2UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00020000 */
+#define FSMC_BWTR3_BUSTURN_2         (0x4UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00040000 */
+#define FSMC_BWTR3_BUSTURN_3         (0x8UL << FSMC_BWTR3_BUSTURN_Pos)          /*!< 0x00080000 */
+
+#define FSMC_BWTR3_ACCMOD_Pos        (28U)                                     
+#define FSMC_BWTR3_ACCMOD_Msk        (0x3UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x30000000 */
+#define FSMC_BWTR3_ACCMOD            FSMC_BWTR3_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR3_ACCMOD_0          (0x1UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x10000000 */
+#define FSMC_BWTR3_ACCMOD_1          (0x2UL << FSMC_BWTR3_ACCMOD_Pos)           /*!< 0x20000000 */
+
+/******************  Bit definition for FSMC_BWTR4 register  ******************/
+#define FSMC_BWTR4_ADDSET_Pos        (0U)                                      
+#define FSMC_BWTR4_ADDSET_Msk        (0xFUL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x0000000F */
+#define FSMC_BWTR4_ADDSET            FSMC_BWTR4_ADDSET_Msk                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
+#define FSMC_BWTR4_ADDSET_0          (0x1UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000001 */
+#define FSMC_BWTR4_ADDSET_1          (0x2UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000002 */
+#define FSMC_BWTR4_ADDSET_2          (0x4UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000004 */
+#define FSMC_BWTR4_ADDSET_3          (0x8UL << FSMC_BWTR4_ADDSET_Pos)           /*!< 0x00000008 */
+
+#define FSMC_BWTR4_ADDHLD_Pos        (4U)                                      
+#define FSMC_BWTR4_ADDHLD_Msk        (0xFUL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x000000F0 */
+#define FSMC_BWTR4_ADDHLD            FSMC_BWTR4_ADDHLD_Msk                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
+#define FSMC_BWTR4_ADDHLD_0          (0x1UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000010 */
+#define FSMC_BWTR4_ADDHLD_1          (0x2UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000020 */
+#define FSMC_BWTR4_ADDHLD_2          (0x4UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000040 */
+#define FSMC_BWTR4_ADDHLD_3          (0x8UL << FSMC_BWTR4_ADDHLD_Pos)           /*!< 0x00000080 */
+
+#define FSMC_BWTR4_DATAST_Pos        (8U)                                      
+#define FSMC_BWTR4_DATAST_Msk        (0xFFUL << FSMC_BWTR4_DATAST_Pos)          /*!< 0x0000FF00 */
+#define FSMC_BWTR4_DATAST            FSMC_BWTR4_DATAST_Msk                     /*!<DATAST [3:0] bits (Data-phase duration) */
+#define FSMC_BWTR4_DATAST_0          0x00000100U                               /*!<Bit 0 */
+#define FSMC_BWTR4_DATAST_1          0x00000200U                               /*!<Bit 1 */
+#define FSMC_BWTR4_DATAST_2          0x00000400U                               /*!<Bit 2 */
+#define FSMC_BWTR4_DATAST_3          0x00000800U                               /*!<Bit 3 */
+#define FSMC_BWTR4_DATAST_4          0x00001000U                               /*!<Bit 4 */
+#define FSMC_BWTR4_DATAST_5          0x00002000U                               /*!<Bit 5 */
+#define FSMC_BWTR4_DATAST_6          0x00004000U                               /*!<Bit 6 */
+#define FSMC_BWTR4_DATAST_7          0x00008000U                               /*!<Bit 7 */
+
+#define FSMC_BWTR4_BUSTURN_Pos       (16U)                                     
+#define FSMC_BWTR4_BUSTURN_Msk       (0xFUL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x000F0000 */
+#define FSMC_BWTR4_BUSTURN           FSMC_BWTR4_BUSTURN_Msk                    /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
+#define FSMC_BWTR4_BUSTURN_0         (0x1UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00010000 */
+#define FSMC_BWTR4_BUSTURN_1         (0x2UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00020000 */
+#define FSMC_BWTR4_BUSTURN_2         (0x4UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00040000 */
+#define FSMC_BWTR4_BUSTURN_3         (0x8UL << FSMC_BWTR4_BUSTURN_Pos)          /*!< 0x00080000 */
+
+#define FSMC_BWTR4_ACCMOD_Pos        (28U)                                     
+#define FSMC_BWTR4_ACCMOD_Msk        (0x3UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x30000000 */
+#define FSMC_BWTR4_ACCMOD            FSMC_BWTR4_ACCMOD_Msk                     /*!<ACCMOD[1:0] bits (Access mode) */
+#define FSMC_BWTR4_ACCMOD_0          (0x1UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x10000000 */
+#define FSMC_BWTR4_ACCMOD_1          (0x2UL << FSMC_BWTR4_ACCMOD_Pos)           /*!< 0x20000000 */
+
+/******************  Bit definition for FSMC_PCR2 register  *******************/
+#define FSMC_PCR2_PWAITEN_Pos        (1U)                                      
+#define FSMC_PCR2_PWAITEN_Msk        (0x1UL << FSMC_PCR2_PWAITEN_Pos)           /*!< 0x00000002 */
+#define FSMC_PCR2_PWAITEN            FSMC_PCR2_PWAITEN_Msk                     /*!<Wait feature enable bit */
+#define FSMC_PCR2_PBKEN_Pos          (2U)                                      
+#define FSMC_PCR2_PBKEN_Msk          (0x1UL << FSMC_PCR2_PBKEN_Pos)             /*!< 0x00000004 */
+#define FSMC_PCR2_PBKEN              FSMC_PCR2_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR2_PTYP_Pos           (3U)                                      
+#define FSMC_PCR2_PTYP_Msk           (0x1UL << FSMC_PCR2_PTYP_Pos)              /*!< 0x00000008 */
+#define FSMC_PCR2_PTYP               FSMC_PCR2_PTYP_Msk                        /*!<Memory type */
+
+#define FSMC_PCR2_PWID_Pos           (4U)                                      
+#define FSMC_PCR2_PWID_Msk           (0x3UL << FSMC_PCR2_PWID_Pos)              /*!< 0x00000030 */
+#define FSMC_PCR2_PWID               FSMC_PCR2_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR2_PWID_0             (0x1UL << FSMC_PCR2_PWID_Pos)              /*!< 0x00000010 */
+#define FSMC_PCR2_PWID_1             (0x2UL << FSMC_PCR2_PWID_Pos)              /*!< 0x00000020 */
+
+#define FSMC_PCR2_ECCEN_Pos          (6U)                                      
+#define FSMC_PCR2_ECCEN_Msk          (0x1UL << FSMC_PCR2_ECCEN_Pos)             /*!< 0x00000040 */
+#define FSMC_PCR2_ECCEN              FSMC_PCR2_ECCEN_Msk                       /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR2_TCLR_Pos           (9U)                                      
+#define FSMC_PCR2_TCLR_Msk           (0xFUL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00001E00 */
+#define FSMC_PCR2_TCLR               FSMC_PCR2_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR2_TCLR_0             (0x1UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000200 */
+#define FSMC_PCR2_TCLR_1             (0x2UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000400 */
+#define FSMC_PCR2_TCLR_2             (0x4UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00000800 */
+#define FSMC_PCR2_TCLR_3             (0x8UL << FSMC_PCR2_TCLR_Pos)              /*!< 0x00001000 */
+
+#define FSMC_PCR2_TAR_Pos            (13U)                                     
+#define FSMC_PCR2_TAR_Msk            (0xFUL << FSMC_PCR2_TAR_Pos)               /*!< 0x0001E000 */
+#define FSMC_PCR2_TAR                FSMC_PCR2_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR2_TAR_0              (0x1UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00002000 */
+#define FSMC_PCR2_TAR_1              (0x2UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00004000 */
+#define FSMC_PCR2_TAR_2              (0x4UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00008000 */
+#define FSMC_PCR2_TAR_3              (0x8UL << FSMC_PCR2_TAR_Pos)               /*!< 0x00010000 */
+
+#define FSMC_PCR2_ECCPS_Pos          (17U)                                     
+#define FSMC_PCR2_ECCPS_Msk          (0x7UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x000E0000 */
+#define FSMC_PCR2_ECCPS              FSMC_PCR2_ECCPS_Msk                       /*!<ECCPS[1:0] bits (ECC page size) */
+#define FSMC_PCR2_ECCPS_0            (0x1UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00020000 */
+#define FSMC_PCR2_ECCPS_1            (0x2UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00040000 */
+#define FSMC_PCR2_ECCPS_2            (0x4UL << FSMC_PCR2_ECCPS_Pos)             /*!< 0x00080000 */
+
+/******************  Bit definition for FSMC_PCR3 register  *******************/
+#define FSMC_PCR3_PWAITEN_Pos        (1U)                                      
+#define FSMC_PCR3_PWAITEN_Msk        (0x1UL << FSMC_PCR3_PWAITEN_Pos)           /*!< 0x00000002 */
+#define FSMC_PCR3_PWAITEN            FSMC_PCR3_PWAITEN_Msk                     /*!<Wait feature enable bit */
+#define FSMC_PCR3_PBKEN_Pos          (2U)                                      
+#define FSMC_PCR3_PBKEN_Msk          (0x1UL << FSMC_PCR3_PBKEN_Pos)             /*!< 0x00000004 */
+#define FSMC_PCR3_PBKEN              FSMC_PCR3_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR3_PTYP_Pos           (3U)                                      
+#define FSMC_PCR3_PTYP_Msk           (0x1UL << FSMC_PCR3_PTYP_Pos)              /*!< 0x00000008 */
+#define FSMC_PCR3_PTYP               FSMC_PCR3_PTYP_Msk                        /*!<Memory type */
+
+#define FSMC_PCR3_PWID_Pos           (4U)                                      
+#define FSMC_PCR3_PWID_Msk           (0x3UL << FSMC_PCR3_PWID_Pos)              /*!< 0x00000030 */
+#define FSMC_PCR3_PWID               FSMC_PCR3_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR3_PWID_0             (0x1UL << FSMC_PCR3_PWID_Pos)              /*!< 0x00000010 */
+#define FSMC_PCR3_PWID_1             (0x2UL << FSMC_PCR3_PWID_Pos)              /*!< 0x00000020 */
+
+#define FSMC_PCR3_ECCEN_Pos          (6U)                                      
+#define FSMC_PCR3_ECCEN_Msk          (0x1UL << FSMC_PCR3_ECCEN_Pos)             /*!< 0x00000040 */
+#define FSMC_PCR3_ECCEN              FSMC_PCR3_ECCEN_Msk                       /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR3_TCLR_Pos           (9U)                                      
+#define FSMC_PCR3_TCLR_Msk           (0xFUL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00001E00 */
+#define FSMC_PCR3_TCLR               FSMC_PCR3_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR3_TCLR_0             (0x1UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000200 */
+#define FSMC_PCR3_TCLR_1             (0x2UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000400 */
+#define FSMC_PCR3_TCLR_2             (0x4UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00000800 */
+#define FSMC_PCR3_TCLR_3             (0x8UL << FSMC_PCR3_TCLR_Pos)              /*!< 0x00001000 */
+
+#define FSMC_PCR3_TAR_Pos            (13U)                                     
+#define FSMC_PCR3_TAR_Msk            (0xFUL << FSMC_PCR3_TAR_Pos)               /*!< 0x0001E000 */
+#define FSMC_PCR3_TAR                FSMC_PCR3_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR3_TAR_0              (0x1UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00002000 */
+#define FSMC_PCR3_TAR_1              (0x2UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00004000 */
+#define FSMC_PCR3_TAR_2              (0x4UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00008000 */
+#define FSMC_PCR3_TAR_3              (0x8UL << FSMC_PCR3_TAR_Pos)               /*!< 0x00010000 */
+
+#define FSMC_PCR3_ECCPS_Pos          (17U)                                     
+#define FSMC_PCR3_ECCPS_Msk          (0x7UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x000E0000 */
+#define FSMC_PCR3_ECCPS              FSMC_PCR3_ECCPS_Msk                       /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR3_ECCPS_0            (0x1UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00020000 */
+#define FSMC_PCR3_ECCPS_1            (0x2UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00040000 */
+#define FSMC_PCR3_ECCPS_2            (0x4UL << FSMC_PCR3_ECCPS_Pos)             /*!< 0x00080000 */
+
+/******************  Bit definition for FSMC_PCR4 register  *******************/
+#define FSMC_PCR4_PWAITEN_Pos        (1U)                                      
+#define FSMC_PCR4_PWAITEN_Msk        (0x1UL << FSMC_PCR4_PWAITEN_Pos)           /*!< 0x00000002 */
+#define FSMC_PCR4_PWAITEN            FSMC_PCR4_PWAITEN_Msk                     /*!<Wait feature enable bit */
+#define FSMC_PCR4_PBKEN_Pos          (2U)                                      
+#define FSMC_PCR4_PBKEN_Msk          (0x1UL << FSMC_PCR4_PBKEN_Pos)             /*!< 0x00000004 */
+#define FSMC_PCR4_PBKEN              FSMC_PCR4_PBKEN_Msk                       /*!<PC Card/NAND Flash memory bank enable bit */
+#define FSMC_PCR4_PTYP_Pos           (3U)                                      
+#define FSMC_PCR4_PTYP_Msk           (0x1UL << FSMC_PCR4_PTYP_Pos)              /*!< 0x00000008 */
+#define FSMC_PCR4_PTYP               FSMC_PCR4_PTYP_Msk                        /*!<Memory type */
+
+#define FSMC_PCR4_PWID_Pos           (4U)                                      
+#define FSMC_PCR4_PWID_Msk           (0x3UL << FSMC_PCR4_PWID_Pos)              /*!< 0x00000030 */
+#define FSMC_PCR4_PWID               FSMC_PCR4_PWID_Msk                        /*!<PWID[1:0] bits (NAND Flash databus width) */
+#define FSMC_PCR4_PWID_0             (0x1UL << FSMC_PCR4_PWID_Pos)              /*!< 0x00000010 */
+#define FSMC_PCR4_PWID_1             (0x2UL << FSMC_PCR4_PWID_Pos)              /*!< 0x00000020 */
+
+#define FSMC_PCR4_ECCEN_Pos          (6U)                                      
+#define FSMC_PCR4_ECCEN_Msk          (0x1UL << FSMC_PCR4_ECCEN_Pos)             /*!< 0x00000040 */
+#define FSMC_PCR4_ECCEN              FSMC_PCR4_ECCEN_Msk                       /*!<ECC computation logic enable bit */
+
+#define FSMC_PCR4_TCLR_Pos           (9U)                                      
+#define FSMC_PCR4_TCLR_Msk           (0xFUL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00001E00 */
+#define FSMC_PCR4_TCLR               FSMC_PCR4_TCLR_Msk                        /*!<TCLR[3:0] bits (CLE to RE delay) */
+#define FSMC_PCR4_TCLR_0             (0x1UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000200 */
+#define FSMC_PCR4_TCLR_1             (0x2UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000400 */
+#define FSMC_PCR4_TCLR_2             (0x4UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00000800 */
+#define FSMC_PCR4_TCLR_3             (0x8UL << FSMC_PCR4_TCLR_Pos)              /*!< 0x00001000 */
+
+#define FSMC_PCR4_TAR_Pos            (13U)                                     
+#define FSMC_PCR4_TAR_Msk            (0xFUL << FSMC_PCR4_TAR_Pos)               /*!< 0x0001E000 */
+#define FSMC_PCR4_TAR                FSMC_PCR4_TAR_Msk                         /*!<TAR[3:0] bits (ALE to RE delay) */
+#define FSMC_PCR4_TAR_0              (0x1UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00002000 */
+#define FSMC_PCR4_TAR_1              (0x2UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00004000 */
+#define FSMC_PCR4_TAR_2              (0x4UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00008000 */
+#define FSMC_PCR4_TAR_3              (0x8UL << FSMC_PCR4_TAR_Pos)               /*!< 0x00010000 */
+
+#define FSMC_PCR4_ECCPS_Pos          (17U)                                     
+#define FSMC_PCR4_ECCPS_Msk          (0x7UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x000E0000 */
+#define FSMC_PCR4_ECCPS              FSMC_PCR4_ECCPS_Msk                       /*!<ECCPS[2:0] bits (ECC page size) */
+#define FSMC_PCR4_ECCPS_0            (0x1UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00020000 */
+#define FSMC_PCR4_ECCPS_1            (0x2UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00040000 */
+#define FSMC_PCR4_ECCPS_2            (0x4UL << FSMC_PCR4_ECCPS_Pos)             /*!< 0x00080000 */
+
+/*******************  Bit definition for FSMC_SR2 register  *******************/
+#define FSMC_SR2_IRS_Pos             (0U)                                      
+#define FSMC_SR2_IRS_Msk             (0x1UL << FSMC_SR2_IRS_Pos)                /*!< 0x00000001 */
+#define FSMC_SR2_IRS                 FSMC_SR2_IRS_Msk                          /*!<Interrupt Rising Edge status                */
+#define FSMC_SR2_ILS_Pos             (1U)                                      
+#define FSMC_SR2_ILS_Msk             (0x1UL << FSMC_SR2_ILS_Pos)                /*!< 0x00000002 */
+#define FSMC_SR2_ILS                 FSMC_SR2_ILS_Msk                          /*!<Interrupt Level status                      */
+#define FSMC_SR2_IFS_Pos             (2U)                                      
+#define FSMC_SR2_IFS_Msk             (0x1UL << FSMC_SR2_IFS_Pos)                /*!< 0x00000004 */
+#define FSMC_SR2_IFS                 FSMC_SR2_IFS_Msk                          /*!<Interrupt Falling Edge status               */
+#define FSMC_SR2_IREN_Pos            (3U)                                      
+#define FSMC_SR2_IREN_Msk            (0x1UL << FSMC_SR2_IREN_Pos)               /*!< 0x00000008 */
+#define FSMC_SR2_IREN                FSMC_SR2_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit  */
+#define FSMC_SR2_ILEN_Pos            (4U)                                      
+#define FSMC_SR2_ILEN_Msk            (0x1UL << FSMC_SR2_ILEN_Pos)               /*!< 0x00000010 */
+#define FSMC_SR2_ILEN                FSMC_SR2_ILEN_Msk                         /*!<Interrupt Level detection Enable bit        */
+#define FSMC_SR2_IFEN_Pos            (5U)                                      
+#define FSMC_SR2_IFEN_Msk            (0x1UL << FSMC_SR2_IFEN_Pos)               /*!< 0x00000020 */
+#define FSMC_SR2_IFEN                FSMC_SR2_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR2_FEMPT_Pos           (6U)                                      
+#define FSMC_SR2_FEMPT_Msk           (0x1UL << FSMC_SR2_FEMPT_Pos)              /*!< 0x00000040 */
+#define FSMC_SR2_FEMPT               FSMC_SR2_FEMPT_Msk                        /*!<FIFO empty */
+
+/*******************  Bit definition for FSMC_SR3 register  *******************/
+#define FSMC_SR3_IRS_Pos             (0U)                                      
+#define FSMC_SR3_IRS_Msk             (0x1UL << FSMC_SR3_IRS_Pos)                /*!< 0x00000001 */
+#define FSMC_SR3_IRS                 FSMC_SR3_IRS_Msk                          /*!<Interrupt Rising Edge status                */
+#define FSMC_SR3_ILS_Pos             (1U)                                      
+#define FSMC_SR3_ILS_Msk             (0x1UL << FSMC_SR3_ILS_Pos)                /*!< 0x00000002 */
+#define FSMC_SR3_ILS                 FSMC_SR3_ILS_Msk                          /*!<Interrupt Level status                      */
+#define FSMC_SR3_IFS_Pos             (2U)                                      
+#define FSMC_SR3_IFS_Msk             (0x1UL << FSMC_SR3_IFS_Pos)                /*!< 0x00000004 */
+#define FSMC_SR3_IFS                 FSMC_SR3_IFS_Msk                          /*!<Interrupt Falling Edge status               */
+#define FSMC_SR3_IREN_Pos            (3U)                                      
+#define FSMC_SR3_IREN_Msk            (0x1UL << FSMC_SR3_IREN_Pos)               /*!< 0x00000008 */
+#define FSMC_SR3_IREN                FSMC_SR3_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit  */
+#define FSMC_SR3_ILEN_Pos            (4U)                                      
+#define FSMC_SR3_ILEN_Msk            (0x1UL << FSMC_SR3_ILEN_Pos)               /*!< 0x00000010 */
+#define FSMC_SR3_ILEN                FSMC_SR3_ILEN_Msk                         /*!<Interrupt Level detection Enable bit        */
+#define FSMC_SR3_IFEN_Pos            (5U)                                      
+#define FSMC_SR3_IFEN_Msk            (0x1UL << FSMC_SR3_IFEN_Pos)               /*!< 0x00000020 */
+#define FSMC_SR3_IFEN                FSMC_SR3_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit */
+#define FSMC_SR3_FEMPT_Pos           (6U)                                      
+#define FSMC_SR3_FEMPT_Msk           (0x1UL << FSMC_SR3_FEMPT_Pos)              /*!< 0x00000040 */
+#define FSMC_SR3_FEMPT               FSMC_SR3_FEMPT_Msk                        /*!<FIFO empty */
+
+/*******************  Bit definition for FSMC_SR4 register  *******************/
+#define FSMC_SR4_IRS_Pos             (0U)                                      
+#define FSMC_SR4_IRS_Msk             (0x1UL << FSMC_SR4_IRS_Pos)                /*!< 0x00000001 */
+#define FSMC_SR4_IRS                 FSMC_SR4_IRS_Msk                          /*!<Interrupt Rising Edge status                 */
+#define FSMC_SR4_ILS_Pos             (1U)                                      
+#define FSMC_SR4_ILS_Msk             (0x1UL << FSMC_SR4_ILS_Pos)                /*!< 0x00000002 */
+#define FSMC_SR4_ILS                 FSMC_SR4_ILS_Msk                          /*!<Interrupt Level status                       */
+#define FSMC_SR4_IFS_Pos             (2U)                                      
+#define FSMC_SR4_IFS_Msk             (0x1UL << FSMC_SR4_IFS_Pos)                /*!< 0x00000004 */
+#define FSMC_SR4_IFS                 FSMC_SR4_IFS_Msk                          /*!<Interrupt Falling Edge status                */
+#define FSMC_SR4_IREN_Pos            (3U)                                      
+#define FSMC_SR4_IREN_Msk            (0x1UL << FSMC_SR4_IREN_Pos)               /*!< 0x00000008 */
+#define FSMC_SR4_IREN                FSMC_SR4_IREN_Msk                         /*!<Interrupt Rising Edge detection Enable bit   */
+#define FSMC_SR4_ILEN_Pos            (4U)                                      
+#define FSMC_SR4_ILEN_Msk            (0x1UL << FSMC_SR4_ILEN_Pos)               /*!< 0x00000010 */
+#define FSMC_SR4_ILEN                FSMC_SR4_ILEN_Msk                         /*!<Interrupt Level detection Enable bit         */
+#define FSMC_SR4_IFEN_Pos            (5U)                                      
+#define FSMC_SR4_IFEN_Msk            (0x1UL << FSMC_SR4_IFEN_Pos)               /*!< 0x00000020 */
+#define FSMC_SR4_IFEN                FSMC_SR4_IFEN_Msk                         /*!<Interrupt Falling Edge detection Enable bit  */
+#define FSMC_SR4_FEMPT_Pos           (6U)                                      
+#define FSMC_SR4_FEMPT_Msk           (0x1UL << FSMC_SR4_FEMPT_Pos)              /*!< 0x00000040 */
+#define FSMC_SR4_FEMPT               FSMC_SR4_FEMPT_Msk                        /*!<FIFO empty */
+
+/******************  Bit definition for FSMC_PMEM2 register  ******************/
+#define FSMC_PMEM2_MEMSET2_Pos       (0U)                                      
+#define FSMC_PMEM2_MEMSET2_Msk       (0xFFUL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x000000FF */
+#define FSMC_PMEM2_MEMSET2           FSMC_PMEM2_MEMSET2_Msk                    /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
+#define FSMC_PMEM2_MEMSET2_0         (0x01UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000001 */
+#define FSMC_PMEM2_MEMSET2_1         (0x02UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000002 */
+#define FSMC_PMEM2_MEMSET2_2         (0x04UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000004 */
+#define FSMC_PMEM2_MEMSET2_3         (0x08UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000008 */
+#define FSMC_PMEM2_MEMSET2_4         (0x10UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000010 */
+#define FSMC_PMEM2_MEMSET2_5         (0x20UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000020 */
+#define FSMC_PMEM2_MEMSET2_6         (0x40UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000040 */
+#define FSMC_PMEM2_MEMSET2_7         (0x80UL << FSMC_PMEM2_MEMSET2_Pos)         /*!< 0x00000080 */
+
+#define FSMC_PMEM2_MEMWAIT2_Pos      (8U)                                      
+#define FSMC_PMEM2_MEMWAIT2_Msk      (0xFFUL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x0000FF00 */
+#define FSMC_PMEM2_MEMWAIT2          FSMC_PMEM2_MEMWAIT2_Msk                   /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
+#define FSMC_PMEM2_MEMWAIT2_0        (0x01UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000100 */
+#define FSMC_PMEM2_MEMWAIT2_1        (0x02UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000200 */
+#define FSMC_PMEM2_MEMWAIT2_2        (0x04UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000400 */
+#define FSMC_PMEM2_MEMWAIT2_3        (0x08UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00000800 */
+#define FSMC_PMEM2_MEMWAIT2_4        (0x10UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00001000 */
+#define FSMC_PMEM2_MEMWAIT2_5        (0x20UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00002000 */
+#define FSMC_PMEM2_MEMWAIT2_6        (0x40UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00004000 */
+#define FSMC_PMEM2_MEMWAIT2_7        (0x80UL << FSMC_PMEM2_MEMWAIT2_Pos)        /*!< 0x00008000 */
+
+#define FSMC_PMEM2_MEMHOLD2_Pos      (16U)                                     
+#define FSMC_PMEM2_MEMHOLD2_Msk      (0xFFUL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00FF0000 */
+#define FSMC_PMEM2_MEMHOLD2          FSMC_PMEM2_MEMHOLD2_Msk                   /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
+#define FSMC_PMEM2_MEMHOLD2_0        (0x01UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00010000 */
+#define FSMC_PMEM2_MEMHOLD2_1        (0x02UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00020000 */
+#define FSMC_PMEM2_MEMHOLD2_2        (0x04UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00040000 */
+#define FSMC_PMEM2_MEMHOLD2_3        (0x08UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00080000 */
+#define FSMC_PMEM2_MEMHOLD2_4        (0x10UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00100000 */
+#define FSMC_PMEM2_MEMHOLD2_5        (0x20UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00200000 */
+#define FSMC_PMEM2_MEMHOLD2_6        (0x40UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00400000 */
+#define FSMC_PMEM2_MEMHOLD2_7        (0x80UL << FSMC_PMEM2_MEMHOLD2_Pos)        /*!< 0x00800000 */
+
+#define FSMC_PMEM2_MEMHIZ2_Pos       (24U)                                     
+#define FSMC_PMEM2_MEMHIZ2_Msk       (0xFFUL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0xFF000000 */
+#define FSMC_PMEM2_MEMHIZ2           FSMC_PMEM2_MEMHIZ2_Msk                    /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
+#define FSMC_PMEM2_MEMHIZ2_0         (0x01UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x01000000 */
+#define FSMC_PMEM2_MEMHIZ2_1         (0x02UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x02000000 */
+#define FSMC_PMEM2_MEMHIZ2_2         (0x04UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x04000000 */
+#define FSMC_PMEM2_MEMHIZ2_3         (0x08UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x08000000 */
+#define FSMC_PMEM2_MEMHIZ2_4         (0x10UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x10000000 */
+#define FSMC_PMEM2_MEMHIZ2_5         (0x20UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x20000000 */
+#define FSMC_PMEM2_MEMHIZ2_6         (0x40UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x40000000 */
+#define FSMC_PMEM2_MEMHIZ2_7         (0x80UL << FSMC_PMEM2_MEMHIZ2_Pos)         /*!< 0x80000000 */
+
+/******************  Bit definition for FSMC_PMEM3 register  ******************/
+#define FSMC_PMEM3_MEMSET3_Pos       (0U)                                      
+#define FSMC_PMEM3_MEMSET3_Msk       (0xFFUL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x000000FF */
+#define FSMC_PMEM3_MEMSET3           FSMC_PMEM3_MEMSET3_Msk                    /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
+#define FSMC_PMEM3_MEMSET3_0         (0x01UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000001 */
+#define FSMC_PMEM3_MEMSET3_1         (0x02UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000002 */
+#define FSMC_PMEM3_MEMSET3_2         (0x04UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000004 */
+#define FSMC_PMEM3_MEMSET3_3         (0x08UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000008 */
+#define FSMC_PMEM3_MEMSET3_4         (0x10UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000010 */
+#define FSMC_PMEM3_MEMSET3_5         (0x20UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000020 */
+#define FSMC_PMEM3_MEMSET3_6         (0x40UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000040 */
+#define FSMC_PMEM3_MEMSET3_7         (0x80UL << FSMC_PMEM3_MEMSET3_Pos)         /*!< 0x00000080 */
+
+#define FSMC_PMEM3_MEMWAIT3_Pos      (8U)                                      
+#define FSMC_PMEM3_MEMWAIT3_Msk      (0xFFUL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x0000FF00 */
+#define FSMC_PMEM3_MEMWAIT3          FSMC_PMEM3_MEMWAIT3_Msk                   /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
+#define FSMC_PMEM3_MEMWAIT3_0        (0x01UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000100 */
+#define FSMC_PMEM3_MEMWAIT3_1        (0x02UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000200 */
+#define FSMC_PMEM3_MEMWAIT3_2        (0x04UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000400 */
+#define FSMC_PMEM3_MEMWAIT3_3        (0x08UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00000800 */
+#define FSMC_PMEM3_MEMWAIT3_4        (0x10UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00001000 */
+#define FSMC_PMEM3_MEMWAIT3_5        (0x20UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00002000 */
+#define FSMC_PMEM3_MEMWAIT3_6        (0x40UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00004000 */
+#define FSMC_PMEM3_MEMWAIT3_7        (0x80UL << FSMC_PMEM3_MEMWAIT3_Pos)        /*!< 0x00008000 */
+
+#define FSMC_PMEM3_MEMHOLD3_Pos      (16U)                                     
+#define FSMC_PMEM3_MEMHOLD3_Msk      (0xFFUL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00FF0000 */
+#define FSMC_PMEM3_MEMHOLD3          FSMC_PMEM3_MEMHOLD3_Msk                   /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
+#define FSMC_PMEM3_MEMHOLD3_0        (0x01UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00010000 */
+#define FSMC_PMEM3_MEMHOLD3_1        (0x02UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00020000 */
+#define FSMC_PMEM3_MEMHOLD3_2        (0x04UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00040000 */
+#define FSMC_PMEM3_MEMHOLD3_3        (0x08UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00080000 */
+#define FSMC_PMEM3_MEMHOLD3_4        (0x10UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00100000 */
+#define FSMC_PMEM3_MEMHOLD3_5        (0x20UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00200000 */
+#define FSMC_PMEM3_MEMHOLD3_6        (0x40UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00400000 */
+#define FSMC_PMEM3_MEMHOLD3_7        (0x80UL << FSMC_PMEM3_MEMHOLD3_Pos)        /*!< 0x00800000 */
+
+#define FSMC_PMEM3_MEMHIZ3_Pos       (24U)                                     
+#define FSMC_PMEM3_MEMHIZ3_Msk       (0xFFUL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0xFF000000 */
+#define FSMC_PMEM3_MEMHIZ3           FSMC_PMEM3_MEMHIZ3_Msk                    /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
+#define FSMC_PMEM3_MEMHIZ3_0         (0x01UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x01000000 */
+#define FSMC_PMEM3_MEMHIZ3_1         (0x02UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x02000000 */
+#define FSMC_PMEM3_MEMHIZ3_2         (0x04UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x04000000 */
+#define FSMC_PMEM3_MEMHIZ3_3         (0x08UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x08000000 */
+#define FSMC_PMEM3_MEMHIZ3_4         (0x10UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x10000000 */
+#define FSMC_PMEM3_MEMHIZ3_5         (0x20UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x20000000 */
+#define FSMC_PMEM3_MEMHIZ3_6         (0x40UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x40000000 */
+#define FSMC_PMEM3_MEMHIZ3_7         (0x80UL << FSMC_PMEM3_MEMHIZ3_Pos)         /*!< 0x80000000 */
+
+/******************  Bit definition for FSMC_PMEM4 register  ******************/
+#define FSMC_PMEM4_MEMSET4_Pos       (0U)                                      
+#define FSMC_PMEM4_MEMSET4_Msk       (0xFFUL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x000000FF */
+#define FSMC_PMEM4_MEMSET4           FSMC_PMEM4_MEMSET4_Msk                    /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
+#define FSMC_PMEM4_MEMSET4_0         (0x01UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000001 */
+#define FSMC_PMEM4_MEMSET4_1         (0x02UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000002 */
+#define FSMC_PMEM4_MEMSET4_2         (0x04UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000004 */
+#define FSMC_PMEM4_MEMSET4_3         (0x08UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000008 */
+#define FSMC_PMEM4_MEMSET4_4         (0x10UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000010 */
+#define FSMC_PMEM4_MEMSET4_5         (0x20UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000020 */
+#define FSMC_PMEM4_MEMSET4_6         (0x40UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000040 */
+#define FSMC_PMEM4_MEMSET4_7         (0x80UL << FSMC_PMEM4_MEMSET4_Pos)         /*!< 0x00000080 */
+
+#define FSMC_PMEM4_MEMWAIT4_Pos      (8U)                                      
+#define FSMC_PMEM4_MEMWAIT4_Msk      (0xFFUL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x0000FF00 */
+#define FSMC_PMEM4_MEMWAIT4          FSMC_PMEM4_MEMWAIT4_Msk                   /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
+#define FSMC_PMEM4_MEMWAIT4_0        (0x01UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000100 */
+#define FSMC_PMEM4_MEMWAIT4_1        (0x02UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000200 */
+#define FSMC_PMEM4_MEMWAIT4_2        (0x04UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000400 */
+#define FSMC_PMEM4_MEMWAIT4_3        (0x08UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00000800 */
+#define FSMC_PMEM4_MEMWAIT4_4        (0x10UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00001000 */
+#define FSMC_PMEM4_MEMWAIT4_5        (0x20UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00002000 */
+#define FSMC_PMEM4_MEMWAIT4_6        (0x40UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00004000 */
+#define FSMC_PMEM4_MEMWAIT4_7        (0x80UL << FSMC_PMEM4_MEMWAIT4_Pos)        /*!< 0x00008000 */
+
+#define FSMC_PMEM4_MEMHOLD4_Pos      (16U)                                     
+#define FSMC_PMEM4_MEMHOLD4_Msk      (0xFFUL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00FF0000 */
+#define FSMC_PMEM4_MEMHOLD4          FSMC_PMEM4_MEMHOLD4_Msk                   /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
+#define FSMC_PMEM4_MEMHOLD4_0        (0x01UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00010000 */
+#define FSMC_PMEM4_MEMHOLD4_1        (0x02UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00020000 */
+#define FSMC_PMEM4_MEMHOLD4_2        (0x04UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00040000 */
+#define FSMC_PMEM4_MEMHOLD4_3        (0x08UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00080000 */
+#define FSMC_PMEM4_MEMHOLD4_4        (0x10UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00100000 */
+#define FSMC_PMEM4_MEMHOLD4_5        (0x20UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00200000 */
+#define FSMC_PMEM4_MEMHOLD4_6        (0x40UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00400000 */
+#define FSMC_PMEM4_MEMHOLD4_7        (0x80UL << FSMC_PMEM4_MEMHOLD4_Pos)        /*!< 0x00800000 */
+
+#define FSMC_PMEM4_MEMHIZ4_Pos       (24U)                                     
+#define FSMC_PMEM4_MEMHIZ4_Msk       (0xFFUL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0xFF000000 */
+#define FSMC_PMEM4_MEMHIZ4           FSMC_PMEM4_MEMHIZ4_Msk                    /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
+#define FSMC_PMEM4_MEMHIZ4_0         (0x01UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x01000000 */
+#define FSMC_PMEM4_MEMHIZ4_1         (0x02UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x02000000 */
+#define FSMC_PMEM4_MEMHIZ4_2         (0x04UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x04000000 */
+#define FSMC_PMEM4_MEMHIZ4_3         (0x08UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x08000000 */
+#define FSMC_PMEM4_MEMHIZ4_4         (0x10UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x10000000 */
+#define FSMC_PMEM4_MEMHIZ4_5         (0x20UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x20000000 */
+#define FSMC_PMEM4_MEMHIZ4_6         (0x40UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x40000000 */
+#define FSMC_PMEM4_MEMHIZ4_7         (0x80UL << FSMC_PMEM4_MEMHIZ4_Pos)         /*!< 0x80000000 */
+
+/******************  Bit definition for FSMC_PATT2 register  ******************/
+#define FSMC_PATT2_ATTSET2_Pos       (0U)                                      
+#define FSMC_PATT2_ATTSET2_Msk       (0xFFUL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x000000FF */
+#define FSMC_PATT2_ATTSET2           FSMC_PATT2_ATTSET2_Msk                    /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
+#define FSMC_PATT2_ATTSET2_0         (0x01UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000001 */
+#define FSMC_PATT2_ATTSET2_1         (0x02UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000002 */
+#define FSMC_PATT2_ATTSET2_2         (0x04UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000004 */
+#define FSMC_PATT2_ATTSET2_3         (0x08UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000008 */
+#define FSMC_PATT2_ATTSET2_4         (0x10UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000010 */
+#define FSMC_PATT2_ATTSET2_5         (0x20UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000020 */
+#define FSMC_PATT2_ATTSET2_6         (0x40UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000040 */
+#define FSMC_PATT2_ATTSET2_7         (0x80UL << FSMC_PATT2_ATTSET2_Pos)         /*!< 0x00000080 */
+
+#define FSMC_PATT2_ATTWAIT2_Pos      (8U)                                      
+#define FSMC_PATT2_ATTWAIT2_Msk      (0xFFUL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x0000FF00 */
+#define FSMC_PATT2_ATTWAIT2          FSMC_PATT2_ATTWAIT2_Msk                   /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
+#define FSMC_PATT2_ATTWAIT2_0        (0x01UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000100 */
+#define FSMC_PATT2_ATTWAIT2_1        (0x02UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000200 */
+#define FSMC_PATT2_ATTWAIT2_2        (0x04UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000400 */
+#define FSMC_PATT2_ATTWAIT2_3        (0x08UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00000800 */
+#define FSMC_PATT2_ATTWAIT2_4        (0x10UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00001000 */
+#define FSMC_PATT2_ATTWAIT2_5        (0x20UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00002000 */
+#define FSMC_PATT2_ATTWAIT2_6        (0x40UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00004000 */
+#define FSMC_PATT2_ATTWAIT2_7        (0x80UL << FSMC_PATT2_ATTWAIT2_Pos)        /*!< 0x00008000 */
+
+#define FSMC_PATT2_ATTHOLD2_Pos      (16U)                                     
+#define FSMC_PATT2_ATTHOLD2_Msk      (0xFFUL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00FF0000 */
+#define FSMC_PATT2_ATTHOLD2          FSMC_PATT2_ATTHOLD2_Msk                   /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
+#define FSMC_PATT2_ATTHOLD2_0        (0x01UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00010000 */
+#define FSMC_PATT2_ATTHOLD2_1        (0x02UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00020000 */
+#define FSMC_PATT2_ATTHOLD2_2        (0x04UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00040000 */
+#define FSMC_PATT2_ATTHOLD2_3        (0x08UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00080000 */
+#define FSMC_PATT2_ATTHOLD2_4        (0x10UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00100000 */
+#define FSMC_PATT2_ATTHOLD2_5        (0x20UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00200000 */
+#define FSMC_PATT2_ATTHOLD2_6        (0x40UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00400000 */
+#define FSMC_PATT2_ATTHOLD2_7        (0x80UL << FSMC_PATT2_ATTHOLD2_Pos)        /*!< 0x00800000 */
+
+#define FSMC_PATT2_ATTHIZ2_Pos       (24U)                                     
+#define FSMC_PATT2_ATTHIZ2_Msk       (0xFFUL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0xFF000000 */
+#define FSMC_PATT2_ATTHIZ2           FSMC_PATT2_ATTHIZ2_Msk                    /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
+#define FSMC_PATT2_ATTHIZ2_0         (0x01UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x01000000 */
+#define FSMC_PATT2_ATTHIZ2_1         (0x02UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x02000000 */
+#define FSMC_PATT2_ATTHIZ2_2         (0x04UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x04000000 */
+#define FSMC_PATT2_ATTHIZ2_3         (0x08UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x08000000 */
+#define FSMC_PATT2_ATTHIZ2_4         (0x10UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x10000000 */
+#define FSMC_PATT2_ATTHIZ2_5         (0x20UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x20000000 */
+#define FSMC_PATT2_ATTHIZ2_6         (0x40UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x40000000 */
+#define FSMC_PATT2_ATTHIZ2_7         (0x80UL << FSMC_PATT2_ATTHIZ2_Pos)         /*!< 0x80000000 */
+
+/******************  Bit definition for FSMC_PATT3 register  ******************/
+#define FSMC_PATT3_ATTSET3_Pos       (0U)                                      
+#define FSMC_PATT3_ATTSET3_Msk       (0xFFUL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x000000FF */
+#define FSMC_PATT3_ATTSET3           FSMC_PATT3_ATTSET3_Msk                    /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
+#define FSMC_PATT3_ATTSET3_0         (0x01UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000001 */
+#define FSMC_PATT3_ATTSET3_1         (0x02UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000002 */
+#define FSMC_PATT3_ATTSET3_2         (0x04UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000004 */
+#define FSMC_PATT3_ATTSET3_3         (0x08UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000008 */
+#define FSMC_PATT3_ATTSET3_4         (0x10UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000010 */
+#define FSMC_PATT3_ATTSET3_5         (0x20UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000020 */
+#define FSMC_PATT3_ATTSET3_6         (0x40UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000040 */
+#define FSMC_PATT3_ATTSET3_7         (0x80UL << FSMC_PATT3_ATTSET3_Pos)         /*!< 0x00000080 */
+
+#define FSMC_PATT3_ATTWAIT3_Pos      (8U)                                      
+#define FSMC_PATT3_ATTWAIT3_Msk      (0xFFUL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x0000FF00 */
+#define FSMC_PATT3_ATTWAIT3          FSMC_PATT3_ATTWAIT3_Msk                   /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
+#define FSMC_PATT3_ATTWAIT3_0        (0x01UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000100 */
+#define FSMC_PATT3_ATTWAIT3_1        (0x02UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000200 */
+#define FSMC_PATT3_ATTWAIT3_2        (0x04UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000400 */
+#define FSMC_PATT3_ATTWAIT3_3        (0x08UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00000800 */
+#define FSMC_PATT3_ATTWAIT3_4        (0x10UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00001000 */
+#define FSMC_PATT3_ATTWAIT3_5        (0x20UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00002000 */
+#define FSMC_PATT3_ATTWAIT3_6        (0x40UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00004000 */
+#define FSMC_PATT3_ATTWAIT3_7        (0x80UL << FSMC_PATT3_ATTWAIT3_Pos)        /*!< 0x00008000 */
+
+#define FSMC_PATT3_ATTHOLD3_Pos      (16U)                                     
+#define FSMC_PATT3_ATTHOLD3_Msk      (0xFFUL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00FF0000 */
+#define FSMC_PATT3_ATTHOLD3          FSMC_PATT3_ATTHOLD3_Msk                   /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
+#define FSMC_PATT3_ATTHOLD3_0        (0x01UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00010000 */
+#define FSMC_PATT3_ATTHOLD3_1        (0x02UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00020000 */
+#define FSMC_PATT3_ATTHOLD3_2        (0x04UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00040000 */
+#define FSMC_PATT3_ATTHOLD3_3        (0x08UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00080000 */
+#define FSMC_PATT3_ATTHOLD3_4        (0x10UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00100000 */
+#define FSMC_PATT3_ATTHOLD3_5        (0x20UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00200000 */
+#define FSMC_PATT3_ATTHOLD3_6        (0x40UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00400000 */
+#define FSMC_PATT3_ATTHOLD3_7        (0x80UL << FSMC_PATT3_ATTHOLD3_Pos)        /*!< 0x00800000 */
+
+#define FSMC_PATT3_ATTHIZ3_Pos       (24U)                                     
+#define FSMC_PATT3_ATTHIZ3_Msk       (0xFFUL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0xFF000000 */
+#define FSMC_PATT3_ATTHIZ3           FSMC_PATT3_ATTHIZ3_Msk                    /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
+#define FSMC_PATT3_ATTHIZ3_0         (0x01UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x01000000 */
+#define FSMC_PATT3_ATTHIZ3_1         (0x02UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x02000000 */
+#define FSMC_PATT3_ATTHIZ3_2         (0x04UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x04000000 */
+#define FSMC_PATT3_ATTHIZ3_3         (0x08UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x08000000 */
+#define FSMC_PATT3_ATTHIZ3_4         (0x10UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x10000000 */
+#define FSMC_PATT3_ATTHIZ3_5         (0x20UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x20000000 */
+#define FSMC_PATT3_ATTHIZ3_6         (0x40UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x40000000 */
+#define FSMC_PATT3_ATTHIZ3_7         (0x80UL << FSMC_PATT3_ATTHIZ3_Pos)         /*!< 0x80000000 */
+
+/******************  Bit definition for FSMC_PATT4 register  ******************/
+#define FSMC_PATT4_ATTSET4_Pos       (0U)                                      
+#define FSMC_PATT4_ATTSET4_Msk       (0xFFUL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x000000FF */
+#define FSMC_PATT4_ATTSET4           FSMC_PATT4_ATTSET4_Msk                    /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
+#define FSMC_PATT4_ATTSET4_0         (0x01UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000001 */
+#define FSMC_PATT4_ATTSET4_1         (0x02UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000002 */
+#define FSMC_PATT4_ATTSET4_2         (0x04UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000004 */
+#define FSMC_PATT4_ATTSET4_3         (0x08UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000008 */
+#define FSMC_PATT4_ATTSET4_4         (0x10UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000010 */
+#define FSMC_PATT4_ATTSET4_5         (0x20UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000020 */
+#define FSMC_PATT4_ATTSET4_6         (0x40UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000040 */
+#define FSMC_PATT4_ATTSET4_7         (0x80UL << FSMC_PATT4_ATTSET4_Pos)         /*!< 0x00000080 */
+
+#define FSMC_PATT4_ATTWAIT4_Pos      (8U)                                      
+#define FSMC_PATT4_ATTWAIT4_Msk      (0xFFUL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x0000FF00 */
+#define FSMC_PATT4_ATTWAIT4          FSMC_PATT4_ATTWAIT4_Msk                   /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
+#define FSMC_PATT4_ATTWAIT4_0        (0x01UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000100 */
+#define FSMC_PATT4_ATTWAIT4_1        (0x02UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000200 */
+#define FSMC_PATT4_ATTWAIT4_2        (0x04UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000400 */
+#define FSMC_PATT4_ATTWAIT4_3        (0x08UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00000800 */
+#define FSMC_PATT4_ATTWAIT4_4        (0x10UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00001000 */
+#define FSMC_PATT4_ATTWAIT4_5        (0x20UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00002000 */
+#define FSMC_PATT4_ATTWAIT4_6        (0x40UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00004000 */
+#define FSMC_PATT4_ATTWAIT4_7        (0x80UL << FSMC_PATT4_ATTWAIT4_Pos)        /*!< 0x00008000 */
+
+#define FSMC_PATT4_ATTHOLD4_Pos      (16U)                                     
+#define FSMC_PATT4_ATTHOLD4_Msk      (0xFFUL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00FF0000 */
+#define FSMC_PATT4_ATTHOLD4          FSMC_PATT4_ATTHOLD4_Msk                   /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
+#define FSMC_PATT4_ATTHOLD4_0        (0x01UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00010000 */
+#define FSMC_PATT4_ATTHOLD4_1        (0x02UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00020000 */
+#define FSMC_PATT4_ATTHOLD4_2        (0x04UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00040000 */
+#define FSMC_PATT4_ATTHOLD4_3        (0x08UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00080000 */
+#define FSMC_PATT4_ATTHOLD4_4        (0x10UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00100000 */
+#define FSMC_PATT4_ATTHOLD4_5        (0x20UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00200000 */
+#define FSMC_PATT4_ATTHOLD4_6        (0x40UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00400000 */
+#define FSMC_PATT4_ATTHOLD4_7        (0x80UL << FSMC_PATT4_ATTHOLD4_Pos)        /*!< 0x00800000 */
+
+#define FSMC_PATT4_ATTHIZ4_Pos       (24U)                                     
+#define FSMC_PATT4_ATTHIZ4_Msk       (0xFFUL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0xFF000000 */
+#define FSMC_PATT4_ATTHIZ4           FSMC_PATT4_ATTHIZ4_Msk                    /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
+#define FSMC_PATT4_ATTHIZ4_0         (0x01UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x01000000 */
+#define FSMC_PATT4_ATTHIZ4_1         (0x02UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x02000000 */
+#define FSMC_PATT4_ATTHIZ4_2         (0x04UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x04000000 */
+#define FSMC_PATT4_ATTHIZ4_3         (0x08UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x08000000 */
+#define FSMC_PATT4_ATTHIZ4_4         (0x10UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x10000000 */
+#define FSMC_PATT4_ATTHIZ4_5         (0x20UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x20000000 */
+#define FSMC_PATT4_ATTHIZ4_6         (0x40UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x40000000 */
+#define FSMC_PATT4_ATTHIZ4_7         (0x80UL << FSMC_PATT4_ATTHIZ4_Pos)         /*!< 0x80000000 */
+
+/******************  Bit definition for FSMC_PIO4 register  *******************/
+#define FSMC_PIO4_IOSET4_Pos         (0U)                                      
+#define FSMC_PIO4_IOSET4_Msk         (0xFFUL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x000000FF */
+#define FSMC_PIO4_IOSET4             FSMC_PIO4_IOSET4_Msk                      /*!<IOSET4[7:0] bits (I/O 4 setup time) */
+#define FSMC_PIO4_IOSET4_0           (0x01UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000001 */
+#define FSMC_PIO4_IOSET4_1           (0x02UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000002 */
+#define FSMC_PIO4_IOSET4_2           (0x04UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000004 */
+#define FSMC_PIO4_IOSET4_3           (0x08UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000008 */
+#define FSMC_PIO4_IOSET4_4           (0x10UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000010 */
+#define FSMC_PIO4_IOSET4_5           (0x20UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000020 */
+#define FSMC_PIO4_IOSET4_6           (0x40UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000040 */
+#define FSMC_PIO4_IOSET4_7           (0x80UL << FSMC_PIO4_IOSET4_Pos)           /*!< 0x00000080 */
+
+#define FSMC_PIO4_IOWAIT4_Pos        (8U)                                      
+#define FSMC_PIO4_IOWAIT4_Msk        (0xFFUL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x0000FF00 */
+#define FSMC_PIO4_IOWAIT4            FSMC_PIO4_IOWAIT4_Msk                     /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
+#define FSMC_PIO4_IOWAIT4_0          (0x01UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000100 */
+#define FSMC_PIO4_IOWAIT4_1          (0x02UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000200 */
+#define FSMC_PIO4_IOWAIT4_2          (0x04UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000400 */
+#define FSMC_PIO4_IOWAIT4_3          (0x08UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00000800 */
+#define FSMC_PIO4_IOWAIT4_4          (0x10UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00001000 */
+#define FSMC_PIO4_IOWAIT4_5          (0x20UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00002000 */
+#define FSMC_PIO4_IOWAIT4_6          (0x40UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00004000 */
+#define FSMC_PIO4_IOWAIT4_7          (0x80UL << FSMC_PIO4_IOWAIT4_Pos)          /*!< 0x00008000 */
+
+#define FSMC_PIO4_IOHOLD4_Pos        (16U)                                     
+#define FSMC_PIO4_IOHOLD4_Msk        (0xFFUL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00FF0000 */
+#define FSMC_PIO4_IOHOLD4            FSMC_PIO4_IOHOLD4_Msk                     /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
+#define FSMC_PIO4_IOHOLD4_0          (0x01UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00010000 */
+#define FSMC_PIO4_IOHOLD4_1          (0x02UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00020000 */
+#define FSMC_PIO4_IOHOLD4_2          (0x04UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00040000 */
+#define FSMC_PIO4_IOHOLD4_3          (0x08UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00080000 */
+#define FSMC_PIO4_IOHOLD4_4          (0x10UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00100000 */
+#define FSMC_PIO4_IOHOLD4_5          (0x20UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00200000 */
+#define FSMC_PIO4_IOHOLD4_6          (0x40UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00400000 */
+#define FSMC_PIO4_IOHOLD4_7          (0x80UL << FSMC_PIO4_IOHOLD4_Pos)          /*!< 0x00800000 */
+
+#define FSMC_PIO4_IOHIZ4_Pos         (24U)                                     
+#define FSMC_PIO4_IOHIZ4_Msk         (0xFFUL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0xFF000000 */
+#define FSMC_PIO4_IOHIZ4             FSMC_PIO4_IOHIZ4_Msk                      /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
+#define FSMC_PIO4_IOHIZ4_0           (0x01UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x01000000 */
+#define FSMC_PIO4_IOHIZ4_1           (0x02UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x02000000 */
+#define FSMC_PIO4_IOHIZ4_2           (0x04UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x04000000 */
+#define FSMC_PIO4_IOHIZ4_3           (0x08UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x08000000 */
+#define FSMC_PIO4_IOHIZ4_4           (0x10UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x10000000 */
+#define FSMC_PIO4_IOHIZ4_5           (0x20UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x20000000 */
+#define FSMC_PIO4_IOHIZ4_6           (0x40UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x40000000 */
+#define FSMC_PIO4_IOHIZ4_7           (0x80UL << FSMC_PIO4_IOHIZ4_Pos)           /*!< 0x80000000 */
+
+/******************  Bit definition for FSMC_ECCR2 register  ******************/
+#define FSMC_ECCR2_ECC2_Pos          (0U)                                      
+#define FSMC_ECCR2_ECC2_Msk          (0xFFFFFFFFUL << FSMC_ECCR2_ECC2_Pos)      /*!< 0xFFFFFFFF */
+#define FSMC_ECCR2_ECC2              FSMC_ECCR2_ECC2_Msk                       /*!<ECC result */
+
+/******************  Bit definition for FSMC_ECCR3 register  ******************/
+#define FSMC_ECCR3_ECC3_Pos          (0U)                                      
+#define FSMC_ECCR3_ECC3_Msk          (0xFFFFFFFFUL << FSMC_ECCR3_ECC3_Pos)      /*!< 0xFFFFFFFF */
+#define FSMC_ECCR3_ECC3              FSMC_ECCR3_ECC3_Msk                       /*!<ECC result */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            General Purpose I/O                             */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bits definition for GPIO_MODER register  *****************/
+#define GPIO_MODER_MODER0_Pos            (0U)                                  
+#define GPIO_MODER_MODER0_Msk            (0x3UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000003 */
+#define GPIO_MODER_MODER0                GPIO_MODER_MODER0_Msk                 
+#define GPIO_MODER_MODER0_0              (0x1UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000001 */
+#define GPIO_MODER_MODER0_1              (0x2UL << GPIO_MODER_MODER0_Pos)       /*!< 0x00000002 */
+#define GPIO_MODER_MODER1_Pos            (2U)                                  
+#define GPIO_MODER_MODER1_Msk            (0x3UL << GPIO_MODER_MODER1_Pos)       /*!< 0x0000000C */
+#define GPIO_MODER_MODER1                GPIO_MODER_MODER1_Msk                 
+#define GPIO_MODER_MODER1_0              (0x1UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000004 */
+#define GPIO_MODER_MODER1_1              (0x2UL << GPIO_MODER_MODER1_Pos)       /*!< 0x00000008 */
+#define GPIO_MODER_MODER2_Pos            (4U)                                  
+#define GPIO_MODER_MODER2_Msk            (0x3UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000030 */
+#define GPIO_MODER_MODER2                GPIO_MODER_MODER2_Msk                 
+#define GPIO_MODER_MODER2_0              (0x1UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000010 */
+#define GPIO_MODER_MODER2_1              (0x2UL << GPIO_MODER_MODER2_Pos)       /*!< 0x00000020 */
+#define GPIO_MODER_MODER3_Pos            (6U)                                  
+#define GPIO_MODER_MODER3_Msk            (0x3UL << GPIO_MODER_MODER3_Pos)       /*!< 0x000000C0 */
+#define GPIO_MODER_MODER3                GPIO_MODER_MODER3_Msk                 
+#define GPIO_MODER_MODER3_0              (0x1UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000040 */
+#define GPIO_MODER_MODER3_1              (0x2UL << GPIO_MODER_MODER3_Pos)       /*!< 0x00000080 */
+#define GPIO_MODER_MODER4_Pos            (8U)                                  
+#define GPIO_MODER_MODER4_Msk            (0x3UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000300 */
+#define GPIO_MODER_MODER4                GPIO_MODER_MODER4_Msk                 
+#define GPIO_MODER_MODER4_0              (0x1UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000100 */
+#define GPIO_MODER_MODER4_1              (0x2UL << GPIO_MODER_MODER4_Pos)       /*!< 0x00000200 */
+#define GPIO_MODER_MODER5_Pos            (10U)                                 
+#define GPIO_MODER_MODER5_Msk            (0x3UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000C00 */
+#define GPIO_MODER_MODER5                GPIO_MODER_MODER5_Msk                 
+#define GPIO_MODER_MODER5_0              (0x1UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000400 */
+#define GPIO_MODER_MODER5_1              (0x2UL << GPIO_MODER_MODER5_Pos)       /*!< 0x00000800 */
+#define GPIO_MODER_MODER6_Pos            (12U)                                 
+#define GPIO_MODER_MODER6_Msk            (0x3UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00003000 */
+#define GPIO_MODER_MODER6                GPIO_MODER_MODER6_Msk                 
+#define GPIO_MODER_MODER6_0              (0x1UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00001000 */
+#define GPIO_MODER_MODER6_1              (0x2UL << GPIO_MODER_MODER6_Pos)       /*!< 0x00002000 */
+#define GPIO_MODER_MODER7_Pos            (14U)                                 
+#define GPIO_MODER_MODER7_Msk            (0x3UL << GPIO_MODER_MODER7_Pos)       /*!< 0x0000C000 */
+#define GPIO_MODER_MODER7                GPIO_MODER_MODER7_Msk                 
+#define GPIO_MODER_MODER7_0              (0x1UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00004000 */
+#define GPIO_MODER_MODER7_1              (0x2UL << GPIO_MODER_MODER7_Pos)       /*!< 0x00008000 */
+#define GPIO_MODER_MODER8_Pos            (16U)                                 
+#define GPIO_MODER_MODER8_Msk            (0x3UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00030000 */
+#define GPIO_MODER_MODER8                GPIO_MODER_MODER8_Msk                 
+#define GPIO_MODER_MODER8_0              (0x1UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00010000 */
+#define GPIO_MODER_MODER8_1              (0x2UL << GPIO_MODER_MODER8_Pos)       /*!< 0x00020000 */
+#define GPIO_MODER_MODER9_Pos            (18U)                                 
+#define GPIO_MODER_MODER9_Msk            (0x3UL << GPIO_MODER_MODER9_Pos)       /*!< 0x000C0000 */
+#define GPIO_MODER_MODER9                GPIO_MODER_MODER9_Msk                 
+#define GPIO_MODER_MODER9_0              (0x1UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00040000 */
+#define GPIO_MODER_MODER9_1              (0x2UL << GPIO_MODER_MODER9_Pos)       /*!< 0x00080000 */
+#define GPIO_MODER_MODER10_Pos           (20U)                                 
+#define GPIO_MODER_MODER10_Msk           (0x3UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00300000 */
+#define GPIO_MODER_MODER10               GPIO_MODER_MODER10_Msk                
+#define GPIO_MODER_MODER10_0             (0x1UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00100000 */
+#define GPIO_MODER_MODER10_1             (0x2UL << GPIO_MODER_MODER10_Pos)      /*!< 0x00200000 */
+#define GPIO_MODER_MODER11_Pos           (22U)                                 
+#define GPIO_MODER_MODER11_Msk           (0x3UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00C00000 */
+#define GPIO_MODER_MODER11               GPIO_MODER_MODER11_Msk                
+#define GPIO_MODER_MODER11_0             (0x1UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00400000 */
+#define GPIO_MODER_MODER11_1             (0x2UL << GPIO_MODER_MODER11_Pos)      /*!< 0x00800000 */
+#define GPIO_MODER_MODER12_Pos           (24U)                                 
+#define GPIO_MODER_MODER12_Msk           (0x3UL << GPIO_MODER_MODER12_Pos)      /*!< 0x03000000 */
+#define GPIO_MODER_MODER12               GPIO_MODER_MODER12_Msk                
+#define GPIO_MODER_MODER12_0             (0x1UL << GPIO_MODER_MODER12_Pos)      /*!< 0x01000000 */
+#define GPIO_MODER_MODER12_1             (0x2UL << GPIO_MODER_MODER12_Pos)      /*!< 0x02000000 */
+#define GPIO_MODER_MODER13_Pos           (26U)                                 
+#define GPIO_MODER_MODER13_Msk           (0x3UL << GPIO_MODER_MODER13_Pos)      /*!< 0x0C000000 */
+#define GPIO_MODER_MODER13               GPIO_MODER_MODER13_Msk                
+#define GPIO_MODER_MODER13_0             (0x1UL << GPIO_MODER_MODER13_Pos)      /*!< 0x04000000 */
+#define GPIO_MODER_MODER13_1             (0x2UL << GPIO_MODER_MODER13_Pos)      /*!< 0x08000000 */
+#define GPIO_MODER_MODER14_Pos           (28U)                                 
+#define GPIO_MODER_MODER14_Msk           (0x3UL << GPIO_MODER_MODER14_Pos)      /*!< 0x30000000 */
+#define GPIO_MODER_MODER14               GPIO_MODER_MODER14_Msk                
+#define GPIO_MODER_MODER14_0             (0x1UL << GPIO_MODER_MODER14_Pos)      /*!< 0x10000000 */
+#define GPIO_MODER_MODER14_1             (0x2UL << GPIO_MODER_MODER14_Pos)      /*!< 0x20000000 */
+#define GPIO_MODER_MODER15_Pos           (30U)                                 
+#define GPIO_MODER_MODER15_Msk           (0x3UL << GPIO_MODER_MODER15_Pos)      /*!< 0xC0000000 */
+#define GPIO_MODER_MODER15               GPIO_MODER_MODER15_Msk                
+#define GPIO_MODER_MODER15_0             (0x1UL << GPIO_MODER_MODER15_Pos)      /*!< 0x40000000 */
+#define GPIO_MODER_MODER15_1             (0x2UL << GPIO_MODER_MODER15_Pos)      /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_MODER_MODE0_Pos             GPIO_MODER_MODER0_Pos                                  
+#define GPIO_MODER_MODE0_Msk             GPIO_MODER_MODER0_Msk
+#define GPIO_MODER_MODE0                 GPIO_MODER_MODER0                 
+#define GPIO_MODER_MODE0_0               GPIO_MODER_MODER0_0
+#define GPIO_MODER_MODE0_1               GPIO_MODER_MODER0_1
+#define GPIO_MODER_MODE1_Pos             GPIO_MODER_MODER1_Pos                                  
+#define GPIO_MODER_MODE1_Msk             GPIO_MODER_MODER1_Msk
+#define GPIO_MODER_MODE1                 GPIO_MODER_MODER1                  
+#define GPIO_MODER_MODE1_0               GPIO_MODER_MODER1_0
+#define GPIO_MODER_MODE1_1               GPIO_MODER_MODER1_1
+#define GPIO_MODER_MODE2_Pos             GPIO_MODER_MODER2_Pos
+#define GPIO_MODER_MODE2_Msk             GPIO_MODER_MODER2_Msk
+#define GPIO_MODER_MODE2                 GPIO_MODER_MODER2                 
+#define GPIO_MODER_MODE2_0               GPIO_MODER_MODER2_0
+#define GPIO_MODER_MODE2_1               GPIO_MODER_MODER2_1
+#define GPIO_MODER_MODE3_Pos             GPIO_MODER_MODER3_Pos                                
+#define GPIO_MODER_MODE3_Msk             GPIO_MODER_MODER3_Msk
+#define GPIO_MODER_MODE3                 GPIO_MODER_MODER3
+#define GPIO_MODER_MODE3_0               GPIO_MODER_MODER3_0
+#define GPIO_MODER_MODE3_1               GPIO_MODER_MODER3_1
+#define GPIO_MODER_MODE4_Pos             GPIO_MODER_MODER4_Pos
+#define GPIO_MODER_MODE4_Msk             GPIO_MODER_MODER4_Msk
+#define GPIO_MODER_MODE4                 GPIO_MODER_MODER4
+#define GPIO_MODER_MODE4_0               GPIO_MODER_MODER4_0
+#define GPIO_MODER_MODE4_1               GPIO_MODER_MODER4_1
+#define GPIO_MODER_MODE5_Pos             GPIO_MODER_MODER5_Pos
+#define GPIO_MODER_MODE5_Msk             GPIO_MODER_MODER5_Msk
+#define GPIO_MODER_MODE5                 GPIO_MODER_MODER5
+#define GPIO_MODER_MODE5_0               GPIO_MODER_MODER5_0
+#define GPIO_MODER_MODE5_1               GPIO_MODER_MODER5_1
+#define GPIO_MODER_MODE6_Pos             GPIO_MODER_MODER6_Pos
+#define GPIO_MODER_MODE6_Msk             GPIO_MODER_MODER6_Msk
+#define GPIO_MODER_MODE6                 GPIO_MODER_MODER6
+#define GPIO_MODER_MODE6_0               GPIO_MODER_MODER6_0
+#define GPIO_MODER_MODE6_1               GPIO_MODER_MODER6_1
+#define GPIO_MODER_MODE7_Pos             GPIO_MODER_MODER7_Pos
+#define GPIO_MODER_MODE7_Msk             GPIO_MODER_MODER7_Msk
+#define GPIO_MODER_MODE7                 GPIO_MODER_MODER7
+#define GPIO_MODER_MODE7_0               GPIO_MODER_MODER7_0
+#define GPIO_MODER_MODE7_1               GPIO_MODER_MODER7_1
+#define GPIO_MODER_MODE8_Pos             GPIO_MODER_MODER8_Pos
+#define GPIO_MODER_MODE8_Msk             GPIO_MODER_MODER8_Msk
+#define GPIO_MODER_MODE8                 GPIO_MODER_MODER8
+#define GPIO_MODER_MODE8_0               GPIO_MODER_MODER8_0
+#define GPIO_MODER_MODE8_1               GPIO_MODER_MODER8_1
+#define GPIO_MODER_MODE9_Pos             GPIO_MODER_MODER9_Pos
+#define GPIO_MODER_MODE9_Msk             GPIO_MODER_MODER9_Msk
+#define GPIO_MODER_MODE9                 GPIO_MODER_MODER9
+#define GPIO_MODER_MODE9_0               GPIO_MODER_MODER9_0
+#define GPIO_MODER_MODE9_1               GPIO_MODER_MODER9_1
+#define GPIO_MODER_MODE10_Pos            GPIO_MODER_MODER10_Pos
+#define GPIO_MODER_MODE10_Msk            GPIO_MODER_MODER10_Msk
+#define GPIO_MODER_MODE10                GPIO_MODER_MODER10
+#define GPIO_MODER_MODE10_0              GPIO_MODER_MODER10_0
+#define GPIO_MODER_MODE10_1              GPIO_MODER_MODER10_1
+#define GPIO_MODER_MODE11_Pos            GPIO_MODER_MODER11_Pos
+#define GPIO_MODER_MODE11_Msk            GPIO_MODER_MODER11_Msk
+#define GPIO_MODER_MODE11                GPIO_MODER_MODER11
+#define GPIO_MODER_MODE11_0              GPIO_MODER_MODER11_0
+#define GPIO_MODER_MODE11_1              GPIO_MODER_MODER11_1
+#define GPIO_MODER_MODE12_Pos            GPIO_MODER_MODER12_Pos
+#define GPIO_MODER_MODE12_Msk            GPIO_MODER_MODER12_Msk
+#define GPIO_MODER_MODE12                GPIO_MODER_MODER12
+#define GPIO_MODER_MODE12_0              GPIO_MODER_MODER12_0
+#define GPIO_MODER_MODE12_1              GPIO_MODER_MODER12_1
+#define GPIO_MODER_MODE13_Pos            GPIO_MODER_MODER13_Pos
+#define GPIO_MODER_MODE13_Msk            GPIO_MODER_MODER13_Msk
+#define GPIO_MODER_MODE13                GPIO_MODER_MODER13
+#define GPIO_MODER_MODE13_0              GPIO_MODER_MODER13_0
+#define GPIO_MODER_MODE13_1              GPIO_MODER_MODER13_1
+#define GPIO_MODER_MODE14_Pos            GPIO_MODER_MODER14_Pos
+#define GPIO_MODER_MODE14_Msk            GPIO_MODER_MODER14_Msk
+#define GPIO_MODER_MODE14                GPIO_MODER_MODER14
+#define GPIO_MODER_MODE14_0              GPIO_MODER_MODER14_0
+#define GPIO_MODER_MODE14_1              GPIO_MODER_MODER14_1
+#define GPIO_MODER_MODE15_Pos            GPIO_MODER_MODER15_Pos
+#define GPIO_MODER_MODE15_Msk            GPIO_MODER_MODER15_Msk
+#define GPIO_MODER_MODE15                GPIO_MODER_MODER15
+#define GPIO_MODER_MODE15_0              GPIO_MODER_MODER15_0
+#define GPIO_MODER_MODE15_1              GPIO_MODER_MODER15_1
+
+/******************  Bits definition for GPIO_OTYPER register  ****************/
+#define GPIO_OTYPER_OT0_Pos              (0U)                                  
+#define GPIO_OTYPER_OT0_Msk              (0x1UL << GPIO_OTYPER_OT0_Pos)         /*!< 0x00000001 */
+#define GPIO_OTYPER_OT0                  GPIO_OTYPER_OT0_Msk                   
+#define GPIO_OTYPER_OT1_Pos              (1U)                                  
+#define GPIO_OTYPER_OT1_Msk              (0x1UL << GPIO_OTYPER_OT1_Pos)         /*!< 0x00000002 */
+#define GPIO_OTYPER_OT1                  GPIO_OTYPER_OT1_Msk                   
+#define GPIO_OTYPER_OT2_Pos              (2U)                                  
+#define GPIO_OTYPER_OT2_Msk              (0x1UL << GPIO_OTYPER_OT2_Pos)         /*!< 0x00000004 */
+#define GPIO_OTYPER_OT2                  GPIO_OTYPER_OT2_Msk                   
+#define GPIO_OTYPER_OT3_Pos              (3U)                                  
+#define GPIO_OTYPER_OT3_Msk              (0x1UL << GPIO_OTYPER_OT3_Pos)         /*!< 0x00000008 */
+#define GPIO_OTYPER_OT3                  GPIO_OTYPER_OT3_Msk                   
+#define GPIO_OTYPER_OT4_Pos              (4U)                                  
+#define GPIO_OTYPER_OT4_Msk              (0x1UL << GPIO_OTYPER_OT4_Pos)         /*!< 0x00000010 */
+#define GPIO_OTYPER_OT4                  GPIO_OTYPER_OT4_Msk                   
+#define GPIO_OTYPER_OT5_Pos              (5U)                                  
+#define GPIO_OTYPER_OT5_Msk              (0x1UL << GPIO_OTYPER_OT5_Pos)         /*!< 0x00000020 */
+#define GPIO_OTYPER_OT5                  GPIO_OTYPER_OT5_Msk                   
+#define GPIO_OTYPER_OT6_Pos              (6U)                                  
+#define GPIO_OTYPER_OT6_Msk              (0x1UL << GPIO_OTYPER_OT6_Pos)         /*!< 0x00000040 */
+#define GPIO_OTYPER_OT6                  GPIO_OTYPER_OT6_Msk                   
+#define GPIO_OTYPER_OT7_Pos              (7U)                                  
+#define GPIO_OTYPER_OT7_Msk              (0x1UL << GPIO_OTYPER_OT7_Pos)         /*!< 0x00000080 */
+#define GPIO_OTYPER_OT7                  GPIO_OTYPER_OT7_Msk                   
+#define GPIO_OTYPER_OT8_Pos              (8U)                                  
+#define GPIO_OTYPER_OT8_Msk              (0x1UL << GPIO_OTYPER_OT8_Pos)         /*!< 0x00000100 */
+#define GPIO_OTYPER_OT8                  GPIO_OTYPER_OT8_Msk                   
+#define GPIO_OTYPER_OT9_Pos              (9U)                                  
+#define GPIO_OTYPER_OT9_Msk              (0x1UL << GPIO_OTYPER_OT9_Pos)         /*!< 0x00000200 */
+#define GPIO_OTYPER_OT9                  GPIO_OTYPER_OT9_Msk                   
+#define GPIO_OTYPER_OT10_Pos             (10U)                                 
+#define GPIO_OTYPER_OT10_Msk             (0x1UL << GPIO_OTYPER_OT10_Pos)        /*!< 0x00000400 */
+#define GPIO_OTYPER_OT10                 GPIO_OTYPER_OT10_Msk                  
+#define GPIO_OTYPER_OT11_Pos             (11U)                                 
+#define GPIO_OTYPER_OT11_Msk             (0x1UL << GPIO_OTYPER_OT11_Pos)        /*!< 0x00000800 */
+#define GPIO_OTYPER_OT11                 GPIO_OTYPER_OT11_Msk                  
+#define GPIO_OTYPER_OT12_Pos             (12U)                                 
+#define GPIO_OTYPER_OT12_Msk             (0x1UL << GPIO_OTYPER_OT12_Pos)        /*!< 0x00001000 */
+#define GPIO_OTYPER_OT12                 GPIO_OTYPER_OT12_Msk                  
+#define GPIO_OTYPER_OT13_Pos             (13U)                                 
+#define GPIO_OTYPER_OT13_Msk             (0x1UL << GPIO_OTYPER_OT13_Pos)        /*!< 0x00002000 */
+#define GPIO_OTYPER_OT13                 GPIO_OTYPER_OT13_Msk                  
+#define GPIO_OTYPER_OT14_Pos             (14U)                                 
+#define GPIO_OTYPER_OT14_Msk             (0x1UL << GPIO_OTYPER_OT14_Pos)        /*!< 0x00004000 */
+#define GPIO_OTYPER_OT14                 GPIO_OTYPER_OT14_Msk                  
+#define GPIO_OTYPER_OT15_Pos             (15U)                                 
+#define GPIO_OTYPER_OT15_Msk             (0x1UL << GPIO_OTYPER_OT15_Pos)        /*!< 0x00008000 */
+#define GPIO_OTYPER_OT15                 GPIO_OTYPER_OT15_Msk                  
+
+/* Legacy defines */
+#define GPIO_OTYPER_OT_0                 GPIO_OTYPER_OT0
+#define GPIO_OTYPER_OT_1                 GPIO_OTYPER_OT1
+#define GPIO_OTYPER_OT_2                 GPIO_OTYPER_OT2
+#define GPIO_OTYPER_OT_3                 GPIO_OTYPER_OT3
+#define GPIO_OTYPER_OT_4                 GPIO_OTYPER_OT4
+#define GPIO_OTYPER_OT_5                 GPIO_OTYPER_OT5
+#define GPIO_OTYPER_OT_6                 GPIO_OTYPER_OT6
+#define GPIO_OTYPER_OT_7                 GPIO_OTYPER_OT7
+#define GPIO_OTYPER_OT_8                 GPIO_OTYPER_OT8
+#define GPIO_OTYPER_OT_9                 GPIO_OTYPER_OT9
+#define GPIO_OTYPER_OT_10                GPIO_OTYPER_OT10
+#define GPIO_OTYPER_OT_11                GPIO_OTYPER_OT11
+#define GPIO_OTYPER_OT_12                GPIO_OTYPER_OT12
+#define GPIO_OTYPER_OT_13                GPIO_OTYPER_OT13
+#define GPIO_OTYPER_OT_14                GPIO_OTYPER_OT14
+#define GPIO_OTYPER_OT_15                GPIO_OTYPER_OT15
+
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/
+#define GPIO_OSPEEDR_OSPEED0_Pos         (0U)                                  
+#define GPIO_OSPEEDR_OSPEED0_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000003 */
+#define GPIO_OSPEEDR_OSPEED0             GPIO_OSPEEDR_OSPEED0_Msk              
+#define GPIO_OSPEEDR_OSPEED0_0           (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000001 */
+#define GPIO_OSPEEDR_OSPEED0_1           (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)    /*!< 0x00000002 */
+#define GPIO_OSPEEDR_OSPEED1_Pos         (2U)                                  
+#define GPIO_OSPEEDR_OSPEED1_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x0000000C */
+#define GPIO_OSPEEDR_OSPEED1             GPIO_OSPEEDR_OSPEED1_Msk              
+#define GPIO_OSPEEDR_OSPEED1_0           (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000004 */
+#define GPIO_OSPEEDR_OSPEED1_1           (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)    /*!< 0x00000008 */
+#define GPIO_OSPEEDR_OSPEED2_Pos         (4U)                                  
+#define GPIO_OSPEEDR_OSPEED2_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000030 */
+#define GPIO_OSPEEDR_OSPEED2             GPIO_OSPEEDR_OSPEED2_Msk              
+#define GPIO_OSPEEDR_OSPEED2_0           (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000010 */
+#define GPIO_OSPEEDR_OSPEED2_1           (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)    /*!< 0x00000020 */
+#define GPIO_OSPEEDR_OSPEED3_Pos         (6U)                                  
+#define GPIO_OSPEEDR_OSPEED3_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x000000C0 */
+#define GPIO_OSPEEDR_OSPEED3             GPIO_OSPEEDR_OSPEED3_Msk              
+#define GPIO_OSPEEDR_OSPEED3_0           (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000040 */
+#define GPIO_OSPEEDR_OSPEED3_1           (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)    /*!< 0x00000080 */
+#define GPIO_OSPEEDR_OSPEED4_Pos         (8U)                                  
+#define GPIO_OSPEEDR_OSPEED4_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000300 */
+#define GPIO_OSPEEDR_OSPEED4             GPIO_OSPEEDR_OSPEED4_Msk              
+#define GPIO_OSPEEDR_OSPEED4_0           (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000100 */
+#define GPIO_OSPEEDR_OSPEED4_1           (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)    /*!< 0x00000200 */
+#define GPIO_OSPEEDR_OSPEED5_Pos         (10U)                                 
+#define GPIO_OSPEEDR_OSPEED5_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000C00 */
+#define GPIO_OSPEEDR_OSPEED5             GPIO_OSPEEDR_OSPEED5_Msk              
+#define GPIO_OSPEEDR_OSPEED5_0           (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000400 */
+#define GPIO_OSPEEDR_OSPEED5_1           (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)    /*!< 0x00000800 */
+#define GPIO_OSPEEDR_OSPEED6_Pos         (12U)                                 
+#define GPIO_OSPEEDR_OSPEED6_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00003000 */
+#define GPIO_OSPEEDR_OSPEED6             GPIO_OSPEEDR_OSPEED6_Msk              
+#define GPIO_OSPEEDR_OSPEED6_0           (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00001000 */
+#define GPIO_OSPEEDR_OSPEED6_1           (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)    /*!< 0x00002000 */
+#define GPIO_OSPEEDR_OSPEED7_Pos         (14U)                                 
+#define GPIO_OSPEEDR_OSPEED7_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x0000C000 */
+#define GPIO_OSPEEDR_OSPEED7             GPIO_OSPEEDR_OSPEED7_Msk              
+#define GPIO_OSPEEDR_OSPEED7_0           (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00004000 */
+#define GPIO_OSPEEDR_OSPEED7_1           (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)    /*!< 0x00008000 */
+#define GPIO_OSPEEDR_OSPEED8_Pos         (16U)                                 
+#define GPIO_OSPEEDR_OSPEED8_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00030000 */
+#define GPIO_OSPEEDR_OSPEED8             GPIO_OSPEEDR_OSPEED8_Msk              
+#define GPIO_OSPEEDR_OSPEED8_0           (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00010000 */
+#define GPIO_OSPEEDR_OSPEED8_1           (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)    /*!< 0x00020000 */
+#define GPIO_OSPEEDR_OSPEED9_Pos         (18U)                                 
+#define GPIO_OSPEEDR_OSPEED9_Msk         (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x000C0000 */
+#define GPIO_OSPEEDR_OSPEED9             GPIO_OSPEEDR_OSPEED9_Msk              
+#define GPIO_OSPEEDR_OSPEED9_0           (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00040000 */
+#define GPIO_OSPEEDR_OSPEED9_1           (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)    /*!< 0x00080000 */
+#define GPIO_OSPEEDR_OSPEED10_Pos        (20U)                                 
+#define GPIO_OSPEEDR_OSPEED10_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00300000 */
+#define GPIO_OSPEEDR_OSPEED10            GPIO_OSPEEDR_OSPEED10_Msk             
+#define GPIO_OSPEEDR_OSPEED10_0          (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00100000 */
+#define GPIO_OSPEEDR_OSPEED10_1          (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)   /*!< 0x00200000 */
+#define GPIO_OSPEEDR_OSPEED11_Pos        (22U)                                 
+#define GPIO_OSPEEDR_OSPEED11_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00C00000 */
+#define GPIO_OSPEEDR_OSPEED11            GPIO_OSPEEDR_OSPEED11_Msk             
+#define GPIO_OSPEEDR_OSPEED11_0          (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00400000 */
+#define GPIO_OSPEEDR_OSPEED11_1          (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)   /*!< 0x00800000 */
+#define GPIO_OSPEEDR_OSPEED12_Pos        (24U)                                 
+#define GPIO_OSPEEDR_OSPEED12_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x03000000 */
+#define GPIO_OSPEEDR_OSPEED12            GPIO_OSPEEDR_OSPEED12_Msk             
+#define GPIO_OSPEEDR_OSPEED12_0          (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x01000000 */
+#define GPIO_OSPEEDR_OSPEED12_1          (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)   /*!< 0x02000000 */
+#define GPIO_OSPEEDR_OSPEED13_Pos        (26U)                                 
+#define GPIO_OSPEEDR_OSPEED13_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x0C000000 */
+#define GPIO_OSPEEDR_OSPEED13            GPIO_OSPEEDR_OSPEED13_Msk             
+#define GPIO_OSPEEDR_OSPEED13_0          (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x04000000 */
+#define GPIO_OSPEEDR_OSPEED13_1          (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)   /*!< 0x08000000 */
+#define GPIO_OSPEEDR_OSPEED14_Pos        (28U)                                 
+#define GPIO_OSPEEDR_OSPEED14_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x30000000 */
+#define GPIO_OSPEEDR_OSPEED14            GPIO_OSPEEDR_OSPEED14_Msk             
+#define GPIO_OSPEEDR_OSPEED14_0          (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x10000000 */
+#define GPIO_OSPEEDR_OSPEED14_1          (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)   /*!< 0x20000000 */
+#define GPIO_OSPEEDR_OSPEED15_Pos        (30U)                                 
+#define GPIO_OSPEEDR_OSPEED15_Msk        (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0xC0000000 */
+#define GPIO_OSPEEDR_OSPEED15            GPIO_OSPEEDR_OSPEED15_Msk             
+#define GPIO_OSPEEDR_OSPEED15_0          (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x40000000 */
+#define GPIO_OSPEEDR_OSPEED15_1          (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)   /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_OSPEEDER_OSPEEDR0           GPIO_OSPEEDR_OSPEED0
+#define GPIO_OSPEEDER_OSPEEDR0_0         GPIO_OSPEEDR_OSPEED0_0
+#define GPIO_OSPEEDER_OSPEEDR0_1         GPIO_OSPEEDR_OSPEED0_1
+#define GPIO_OSPEEDER_OSPEEDR1           GPIO_OSPEEDR_OSPEED1
+#define GPIO_OSPEEDER_OSPEEDR1_0         GPIO_OSPEEDR_OSPEED1_0
+#define GPIO_OSPEEDER_OSPEEDR1_1         GPIO_OSPEEDR_OSPEED1_1
+#define GPIO_OSPEEDER_OSPEEDR2           GPIO_OSPEEDR_OSPEED2
+#define GPIO_OSPEEDER_OSPEEDR2_0         GPIO_OSPEEDR_OSPEED2_0
+#define GPIO_OSPEEDER_OSPEEDR2_1         GPIO_OSPEEDR_OSPEED2_1
+#define GPIO_OSPEEDER_OSPEEDR3           GPIO_OSPEEDR_OSPEED3
+#define GPIO_OSPEEDER_OSPEEDR3_0         GPIO_OSPEEDR_OSPEED3_0
+#define GPIO_OSPEEDER_OSPEEDR3_1         GPIO_OSPEEDR_OSPEED3_1
+#define GPIO_OSPEEDER_OSPEEDR4           GPIO_OSPEEDR_OSPEED4
+#define GPIO_OSPEEDER_OSPEEDR4_0         GPIO_OSPEEDR_OSPEED4_0
+#define GPIO_OSPEEDER_OSPEEDR4_1         GPIO_OSPEEDR_OSPEED4_1
+#define GPIO_OSPEEDER_OSPEEDR5           GPIO_OSPEEDR_OSPEED5
+#define GPIO_OSPEEDER_OSPEEDR5_0         GPIO_OSPEEDR_OSPEED5_0
+#define GPIO_OSPEEDER_OSPEEDR5_1         GPIO_OSPEEDR_OSPEED5_1
+#define GPIO_OSPEEDER_OSPEEDR6           GPIO_OSPEEDR_OSPEED6
+#define GPIO_OSPEEDER_OSPEEDR6_0         GPIO_OSPEEDR_OSPEED6_0
+#define GPIO_OSPEEDER_OSPEEDR6_1         GPIO_OSPEEDR_OSPEED6_1
+#define GPIO_OSPEEDER_OSPEEDR7           GPIO_OSPEEDR_OSPEED7
+#define GPIO_OSPEEDER_OSPEEDR7_0         GPIO_OSPEEDR_OSPEED7_0
+#define GPIO_OSPEEDER_OSPEEDR7_1         GPIO_OSPEEDR_OSPEED7_1
+#define GPIO_OSPEEDER_OSPEEDR8           GPIO_OSPEEDR_OSPEED8
+#define GPIO_OSPEEDER_OSPEEDR8_0         GPIO_OSPEEDR_OSPEED8_0
+#define GPIO_OSPEEDER_OSPEEDR8_1         GPIO_OSPEEDR_OSPEED8_1
+#define GPIO_OSPEEDER_OSPEEDR9           GPIO_OSPEEDR_OSPEED9
+#define GPIO_OSPEEDER_OSPEEDR9_0         GPIO_OSPEEDR_OSPEED9_0
+#define GPIO_OSPEEDER_OSPEEDR9_1         GPIO_OSPEEDR_OSPEED9_1
+#define GPIO_OSPEEDER_OSPEEDR10          GPIO_OSPEEDR_OSPEED10
+#define GPIO_OSPEEDER_OSPEEDR10_0        GPIO_OSPEEDR_OSPEED10_0
+#define GPIO_OSPEEDER_OSPEEDR10_1        GPIO_OSPEEDR_OSPEED10_1
+#define GPIO_OSPEEDER_OSPEEDR11          GPIO_OSPEEDR_OSPEED11
+#define GPIO_OSPEEDER_OSPEEDR11_0        GPIO_OSPEEDR_OSPEED11_0
+#define GPIO_OSPEEDER_OSPEEDR11_1        GPIO_OSPEEDR_OSPEED11_1
+#define GPIO_OSPEEDER_OSPEEDR12          GPIO_OSPEEDR_OSPEED12
+#define GPIO_OSPEEDER_OSPEEDR12_0        GPIO_OSPEEDR_OSPEED12_0
+#define GPIO_OSPEEDER_OSPEEDR12_1        GPIO_OSPEEDR_OSPEED12_1
+#define GPIO_OSPEEDER_OSPEEDR13          GPIO_OSPEEDR_OSPEED13
+#define GPIO_OSPEEDER_OSPEEDR13_0        GPIO_OSPEEDR_OSPEED13_0
+#define GPIO_OSPEEDER_OSPEEDR13_1        GPIO_OSPEEDR_OSPEED13_1
+#define GPIO_OSPEEDER_OSPEEDR14          GPIO_OSPEEDR_OSPEED14
+#define GPIO_OSPEEDER_OSPEEDR14_0        GPIO_OSPEEDR_OSPEED14_0
+#define GPIO_OSPEEDER_OSPEEDR14_1        GPIO_OSPEEDR_OSPEED14_1
+#define GPIO_OSPEEDER_OSPEEDR15          GPIO_OSPEEDR_OSPEED15
+#define GPIO_OSPEEDER_OSPEEDR15_0        GPIO_OSPEEDR_OSPEED15_0
+#define GPIO_OSPEEDER_OSPEEDR15_1        GPIO_OSPEEDR_OSPEED15_1
+
+/******************  Bits definition for GPIO_PUPDR register  *****************/
+#define GPIO_PUPDR_PUPD0_Pos             (0U)                                  
+#define GPIO_PUPDR_PUPD0_Msk             (0x3UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000003 */
+#define GPIO_PUPDR_PUPD0                 GPIO_PUPDR_PUPD0_Msk                  
+#define GPIO_PUPDR_PUPD0_0               (0x1UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000001 */
+#define GPIO_PUPDR_PUPD0_1               (0x2UL << GPIO_PUPDR_PUPD0_Pos)        /*!< 0x00000002 */
+#define GPIO_PUPDR_PUPD1_Pos             (2U)                                  
+#define GPIO_PUPDR_PUPD1_Msk             (0x3UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x0000000C */
+#define GPIO_PUPDR_PUPD1                 GPIO_PUPDR_PUPD1_Msk                  
+#define GPIO_PUPDR_PUPD1_0               (0x1UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000004 */
+#define GPIO_PUPDR_PUPD1_1               (0x2UL << GPIO_PUPDR_PUPD1_Pos)        /*!< 0x00000008 */
+#define GPIO_PUPDR_PUPD2_Pos             (4U)                                  
+#define GPIO_PUPDR_PUPD2_Msk             (0x3UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000030 */
+#define GPIO_PUPDR_PUPD2                 GPIO_PUPDR_PUPD2_Msk                  
+#define GPIO_PUPDR_PUPD2_0               (0x1UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000010 */
+#define GPIO_PUPDR_PUPD2_1               (0x2UL << GPIO_PUPDR_PUPD2_Pos)        /*!< 0x00000020 */
+#define GPIO_PUPDR_PUPD3_Pos             (6U)                                  
+#define GPIO_PUPDR_PUPD3_Msk             (0x3UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x000000C0 */
+#define GPIO_PUPDR_PUPD3                 GPIO_PUPDR_PUPD3_Msk                  
+#define GPIO_PUPDR_PUPD3_0               (0x1UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000040 */
+#define GPIO_PUPDR_PUPD3_1               (0x2UL << GPIO_PUPDR_PUPD3_Pos)        /*!< 0x00000080 */
+#define GPIO_PUPDR_PUPD4_Pos             (8U)                                  
+#define GPIO_PUPDR_PUPD4_Msk             (0x3UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000300 */
+#define GPIO_PUPDR_PUPD4                 GPIO_PUPDR_PUPD4_Msk                  
+#define GPIO_PUPDR_PUPD4_0               (0x1UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000100 */
+#define GPIO_PUPDR_PUPD4_1               (0x2UL << GPIO_PUPDR_PUPD4_Pos)        /*!< 0x00000200 */
+#define GPIO_PUPDR_PUPD5_Pos             (10U)                                 
+#define GPIO_PUPDR_PUPD5_Msk             (0x3UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000C00 */
+#define GPIO_PUPDR_PUPD5                 GPIO_PUPDR_PUPD5_Msk                  
+#define GPIO_PUPDR_PUPD5_0               (0x1UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000400 */
+#define GPIO_PUPDR_PUPD5_1               (0x2UL << GPIO_PUPDR_PUPD5_Pos)        /*!< 0x00000800 */
+#define GPIO_PUPDR_PUPD6_Pos             (12U)                                 
+#define GPIO_PUPDR_PUPD6_Msk             (0x3UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00003000 */
+#define GPIO_PUPDR_PUPD6                 GPIO_PUPDR_PUPD6_Msk                  
+#define GPIO_PUPDR_PUPD6_0               (0x1UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00001000 */
+#define GPIO_PUPDR_PUPD6_1               (0x2UL << GPIO_PUPDR_PUPD6_Pos)        /*!< 0x00002000 */
+#define GPIO_PUPDR_PUPD7_Pos             (14U)                                 
+#define GPIO_PUPDR_PUPD7_Msk             (0x3UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x0000C000 */
+#define GPIO_PUPDR_PUPD7                 GPIO_PUPDR_PUPD7_Msk                  
+#define GPIO_PUPDR_PUPD7_0               (0x1UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00004000 */
+#define GPIO_PUPDR_PUPD7_1               (0x2UL << GPIO_PUPDR_PUPD7_Pos)        /*!< 0x00008000 */
+#define GPIO_PUPDR_PUPD8_Pos             (16U)                                 
+#define GPIO_PUPDR_PUPD8_Msk             (0x3UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00030000 */
+#define GPIO_PUPDR_PUPD8                 GPIO_PUPDR_PUPD8_Msk                  
+#define GPIO_PUPDR_PUPD8_0               (0x1UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00010000 */
+#define GPIO_PUPDR_PUPD8_1               (0x2UL << GPIO_PUPDR_PUPD8_Pos)        /*!< 0x00020000 */
+#define GPIO_PUPDR_PUPD9_Pos             (18U)                                 
+#define GPIO_PUPDR_PUPD9_Msk             (0x3UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x000C0000 */
+#define GPIO_PUPDR_PUPD9                 GPIO_PUPDR_PUPD9_Msk                  
+#define GPIO_PUPDR_PUPD9_0               (0x1UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00040000 */
+#define GPIO_PUPDR_PUPD9_1               (0x2UL << GPIO_PUPDR_PUPD9_Pos)        /*!< 0x00080000 */
+#define GPIO_PUPDR_PUPD10_Pos            (20U)                                 
+#define GPIO_PUPDR_PUPD10_Msk            (0x3UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00300000 */
+#define GPIO_PUPDR_PUPD10                GPIO_PUPDR_PUPD10_Msk                 
+#define GPIO_PUPDR_PUPD10_0              (0x1UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00100000 */
+#define GPIO_PUPDR_PUPD10_1              (0x2UL << GPIO_PUPDR_PUPD10_Pos)       /*!< 0x00200000 */
+#define GPIO_PUPDR_PUPD11_Pos            (22U)                                 
+#define GPIO_PUPDR_PUPD11_Msk            (0x3UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00C00000 */
+#define GPIO_PUPDR_PUPD11                GPIO_PUPDR_PUPD11_Msk                 
+#define GPIO_PUPDR_PUPD11_0              (0x1UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00400000 */
+#define GPIO_PUPDR_PUPD11_1              (0x2UL << GPIO_PUPDR_PUPD11_Pos)       /*!< 0x00800000 */
+#define GPIO_PUPDR_PUPD12_Pos            (24U)                                 
+#define GPIO_PUPDR_PUPD12_Msk            (0x3UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x03000000 */
+#define GPIO_PUPDR_PUPD12                GPIO_PUPDR_PUPD12_Msk                 
+#define GPIO_PUPDR_PUPD12_0              (0x1UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x01000000 */
+#define GPIO_PUPDR_PUPD12_1              (0x2UL << GPIO_PUPDR_PUPD12_Pos)       /*!< 0x02000000 */
+#define GPIO_PUPDR_PUPD13_Pos            (26U)                                 
+#define GPIO_PUPDR_PUPD13_Msk            (0x3UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x0C000000 */
+#define GPIO_PUPDR_PUPD13                GPIO_PUPDR_PUPD13_Msk                 
+#define GPIO_PUPDR_PUPD13_0              (0x1UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x04000000 */
+#define GPIO_PUPDR_PUPD13_1              (0x2UL << GPIO_PUPDR_PUPD13_Pos)       /*!< 0x08000000 */
+#define GPIO_PUPDR_PUPD14_Pos            (28U)                                 
+#define GPIO_PUPDR_PUPD14_Msk            (0x3UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x30000000 */
+#define GPIO_PUPDR_PUPD14                GPIO_PUPDR_PUPD14_Msk                 
+#define GPIO_PUPDR_PUPD14_0              (0x1UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x10000000 */
+#define GPIO_PUPDR_PUPD14_1              (0x2UL << GPIO_PUPDR_PUPD14_Pos)       /*!< 0x20000000 */
+#define GPIO_PUPDR_PUPD15_Pos            (30U)                                 
+#define GPIO_PUPDR_PUPD15_Msk            (0x3UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0xC0000000 */
+#define GPIO_PUPDR_PUPD15                GPIO_PUPDR_PUPD15_Msk                 
+#define GPIO_PUPDR_PUPD15_0              (0x1UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x40000000 */
+#define GPIO_PUPDR_PUPD15_1              (0x2UL << GPIO_PUPDR_PUPD15_Pos)       /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_PUPDR_PUPDR0                GPIO_PUPDR_PUPD0
+#define GPIO_PUPDR_PUPDR0_0              GPIO_PUPDR_PUPD0_0
+#define GPIO_PUPDR_PUPDR0_1              GPIO_PUPDR_PUPD0_1
+#define GPIO_PUPDR_PUPDR1                GPIO_PUPDR_PUPD1
+#define GPIO_PUPDR_PUPDR1_0              GPIO_PUPDR_PUPD1_0
+#define GPIO_PUPDR_PUPDR1_1              GPIO_PUPDR_PUPD1_1
+#define GPIO_PUPDR_PUPDR2                GPIO_PUPDR_PUPD2
+#define GPIO_PUPDR_PUPDR2_0              GPIO_PUPDR_PUPD2_0
+#define GPIO_PUPDR_PUPDR2_1              GPIO_PUPDR_PUPD2_1
+#define GPIO_PUPDR_PUPDR3                GPIO_PUPDR_PUPD3
+#define GPIO_PUPDR_PUPDR3_0              GPIO_PUPDR_PUPD3_0
+#define GPIO_PUPDR_PUPDR3_1              GPIO_PUPDR_PUPD3_1
+#define GPIO_PUPDR_PUPDR4                GPIO_PUPDR_PUPD4
+#define GPIO_PUPDR_PUPDR4_0              GPIO_PUPDR_PUPD4_0
+#define GPIO_PUPDR_PUPDR4_1              GPIO_PUPDR_PUPD4_1
+#define GPIO_PUPDR_PUPDR5                GPIO_PUPDR_PUPD5
+#define GPIO_PUPDR_PUPDR5_0              GPIO_PUPDR_PUPD5_0
+#define GPIO_PUPDR_PUPDR5_1              GPIO_PUPDR_PUPD5_1
+#define GPIO_PUPDR_PUPDR6                GPIO_PUPDR_PUPD6
+#define GPIO_PUPDR_PUPDR6_0              GPIO_PUPDR_PUPD6_0
+#define GPIO_PUPDR_PUPDR6_1              GPIO_PUPDR_PUPD6_1
+#define GPIO_PUPDR_PUPDR7                GPIO_PUPDR_PUPD7
+#define GPIO_PUPDR_PUPDR7_0              GPIO_PUPDR_PUPD7_0
+#define GPIO_PUPDR_PUPDR7_1              GPIO_PUPDR_PUPD7_1
+#define GPIO_PUPDR_PUPDR8                GPIO_PUPDR_PUPD8
+#define GPIO_PUPDR_PUPDR8_0              GPIO_PUPDR_PUPD8_0
+#define GPIO_PUPDR_PUPDR8_1              GPIO_PUPDR_PUPD8_1
+#define GPIO_PUPDR_PUPDR9                GPIO_PUPDR_PUPD9
+#define GPIO_PUPDR_PUPDR9_0              GPIO_PUPDR_PUPD9_0
+#define GPIO_PUPDR_PUPDR9_1              GPIO_PUPDR_PUPD9_1
+#define GPIO_PUPDR_PUPDR10               GPIO_PUPDR_PUPD10
+#define GPIO_PUPDR_PUPDR10_0             GPIO_PUPDR_PUPD10_0
+#define GPIO_PUPDR_PUPDR10_1             GPIO_PUPDR_PUPD10_1
+#define GPIO_PUPDR_PUPDR11               GPIO_PUPDR_PUPD11
+#define GPIO_PUPDR_PUPDR11_0             GPIO_PUPDR_PUPD11_0
+#define GPIO_PUPDR_PUPDR11_1             GPIO_PUPDR_PUPD11_1
+#define GPIO_PUPDR_PUPDR12               GPIO_PUPDR_PUPD12
+#define GPIO_PUPDR_PUPDR12_0             GPIO_PUPDR_PUPD12_0
+#define GPIO_PUPDR_PUPDR12_1             GPIO_PUPDR_PUPD12_1
+#define GPIO_PUPDR_PUPDR13               GPIO_PUPDR_PUPD13
+#define GPIO_PUPDR_PUPDR13_0             GPIO_PUPDR_PUPD13_0
+#define GPIO_PUPDR_PUPDR13_1             GPIO_PUPDR_PUPD13_1
+#define GPIO_PUPDR_PUPDR14               GPIO_PUPDR_PUPD14
+#define GPIO_PUPDR_PUPDR14_0             GPIO_PUPDR_PUPD14_0
+#define GPIO_PUPDR_PUPDR14_1             GPIO_PUPDR_PUPD14_1
+#define GPIO_PUPDR_PUPDR15               GPIO_PUPDR_PUPD15
+#define GPIO_PUPDR_PUPDR15_0             GPIO_PUPDR_PUPD15_0
+#define GPIO_PUPDR_PUPDR15_1             GPIO_PUPDR_PUPD15_1
+
+/******************  Bits definition for GPIO_IDR register  *******************/
+#define GPIO_IDR_ID0_Pos                 (0U)                                  
+#define GPIO_IDR_ID0_Msk                 (0x1UL << GPIO_IDR_ID0_Pos)            /*!< 0x00000001 */
+#define GPIO_IDR_ID0                     GPIO_IDR_ID0_Msk                      
+#define GPIO_IDR_ID1_Pos                 (1U)                                  
+#define GPIO_IDR_ID1_Msk                 (0x1UL << GPIO_IDR_ID1_Pos)            /*!< 0x00000002 */
+#define GPIO_IDR_ID1                     GPIO_IDR_ID1_Msk                      
+#define GPIO_IDR_ID2_Pos                 (2U)                                  
+#define GPIO_IDR_ID2_Msk                 (0x1UL << GPIO_IDR_ID2_Pos)            /*!< 0x00000004 */
+#define GPIO_IDR_ID2                     GPIO_IDR_ID2_Msk                      
+#define GPIO_IDR_ID3_Pos                 (3U)                                  
+#define GPIO_IDR_ID3_Msk                 (0x1UL << GPIO_IDR_ID3_Pos)            /*!< 0x00000008 */
+#define GPIO_IDR_ID3                     GPIO_IDR_ID3_Msk                      
+#define GPIO_IDR_ID4_Pos                 (4U)                                  
+#define GPIO_IDR_ID4_Msk                 (0x1UL << GPIO_IDR_ID4_Pos)            /*!< 0x00000010 */
+#define GPIO_IDR_ID4                     GPIO_IDR_ID4_Msk                      
+#define GPIO_IDR_ID5_Pos                 (5U)                                  
+#define GPIO_IDR_ID5_Msk                 (0x1UL << GPIO_IDR_ID5_Pos)            /*!< 0x00000020 */
+#define GPIO_IDR_ID5                     GPIO_IDR_ID5_Msk                      
+#define GPIO_IDR_ID6_Pos                 (6U)                                  
+#define GPIO_IDR_ID6_Msk                 (0x1UL << GPIO_IDR_ID6_Pos)            /*!< 0x00000040 */
+#define GPIO_IDR_ID6                     GPIO_IDR_ID6_Msk                      
+#define GPIO_IDR_ID7_Pos                 (7U)                                  
+#define GPIO_IDR_ID7_Msk                 (0x1UL << GPIO_IDR_ID7_Pos)            /*!< 0x00000080 */
+#define GPIO_IDR_ID7                     GPIO_IDR_ID7_Msk                      
+#define GPIO_IDR_ID8_Pos                 (8U)                                  
+#define GPIO_IDR_ID8_Msk                 (0x1UL << GPIO_IDR_ID8_Pos)            /*!< 0x00000100 */
+#define GPIO_IDR_ID8                     GPIO_IDR_ID8_Msk                      
+#define GPIO_IDR_ID9_Pos                 (9U)                                  
+#define GPIO_IDR_ID9_Msk                 (0x1UL << GPIO_IDR_ID9_Pos)            /*!< 0x00000200 */
+#define GPIO_IDR_ID9                     GPIO_IDR_ID9_Msk                      
+#define GPIO_IDR_ID10_Pos                (10U)                                 
+#define GPIO_IDR_ID10_Msk                (0x1UL << GPIO_IDR_ID10_Pos)           /*!< 0x00000400 */
+#define GPIO_IDR_ID10                    GPIO_IDR_ID10_Msk                     
+#define GPIO_IDR_ID11_Pos                (11U)                                 
+#define GPIO_IDR_ID11_Msk                (0x1UL << GPIO_IDR_ID11_Pos)           /*!< 0x00000800 */
+#define GPIO_IDR_ID11                    GPIO_IDR_ID11_Msk                     
+#define GPIO_IDR_ID12_Pos                (12U)                                 
+#define GPIO_IDR_ID12_Msk                (0x1UL << GPIO_IDR_ID12_Pos)           /*!< 0x00001000 */
+#define GPIO_IDR_ID12                    GPIO_IDR_ID12_Msk                     
+#define GPIO_IDR_ID13_Pos                (13U)                                 
+#define GPIO_IDR_ID13_Msk                (0x1UL << GPIO_IDR_ID13_Pos)           /*!< 0x00002000 */
+#define GPIO_IDR_ID13                    GPIO_IDR_ID13_Msk                     
+#define GPIO_IDR_ID14_Pos                (14U)                                 
+#define GPIO_IDR_ID14_Msk                (0x1UL << GPIO_IDR_ID14_Pos)           /*!< 0x00004000 */
+#define GPIO_IDR_ID14                    GPIO_IDR_ID14_Msk                     
+#define GPIO_IDR_ID15_Pos                (15U)                                 
+#define GPIO_IDR_ID15_Msk                (0x1UL << GPIO_IDR_ID15_Pos)           /*!< 0x00008000 */
+#define GPIO_IDR_ID15                    GPIO_IDR_ID15_Msk                     
+
+/* Legacy defines */
+#define GPIO_IDR_IDR_0                   GPIO_IDR_ID0
+#define GPIO_IDR_IDR_1                   GPIO_IDR_ID1
+#define GPIO_IDR_IDR_2                   GPIO_IDR_ID2
+#define GPIO_IDR_IDR_3                   GPIO_IDR_ID3
+#define GPIO_IDR_IDR_4                   GPIO_IDR_ID4
+#define GPIO_IDR_IDR_5                   GPIO_IDR_ID5
+#define GPIO_IDR_IDR_6                   GPIO_IDR_ID6
+#define GPIO_IDR_IDR_7                   GPIO_IDR_ID7
+#define GPIO_IDR_IDR_8                   GPIO_IDR_ID8
+#define GPIO_IDR_IDR_9                   GPIO_IDR_ID9
+#define GPIO_IDR_IDR_10                  GPIO_IDR_ID10
+#define GPIO_IDR_IDR_11                  GPIO_IDR_ID11
+#define GPIO_IDR_IDR_12                  GPIO_IDR_ID12
+#define GPIO_IDR_IDR_13                  GPIO_IDR_ID13
+#define GPIO_IDR_IDR_14                  GPIO_IDR_ID14
+#define GPIO_IDR_IDR_15                  GPIO_IDR_ID15
+
+/******************  Bits definition for GPIO_ODR register  *******************/
+#define GPIO_ODR_OD0_Pos                 (0U)                                  
+#define GPIO_ODR_OD0_Msk                 (0x1UL << GPIO_ODR_OD0_Pos)            /*!< 0x00000001 */
+#define GPIO_ODR_OD0                     GPIO_ODR_OD0_Msk                      
+#define GPIO_ODR_OD1_Pos                 (1U)                                  
+#define GPIO_ODR_OD1_Msk                 (0x1UL << GPIO_ODR_OD1_Pos)            /*!< 0x00000002 */
+#define GPIO_ODR_OD1                     GPIO_ODR_OD1_Msk                      
+#define GPIO_ODR_OD2_Pos                 (2U)                                  
+#define GPIO_ODR_OD2_Msk                 (0x1UL << GPIO_ODR_OD2_Pos)            /*!< 0x00000004 */
+#define GPIO_ODR_OD2                     GPIO_ODR_OD2_Msk                      
+#define GPIO_ODR_OD3_Pos                 (3U)                                  
+#define GPIO_ODR_OD3_Msk                 (0x1UL << GPIO_ODR_OD3_Pos)            /*!< 0x00000008 */
+#define GPIO_ODR_OD3                     GPIO_ODR_OD3_Msk                      
+#define GPIO_ODR_OD4_Pos                 (4U)                                  
+#define GPIO_ODR_OD4_Msk                 (0x1UL << GPIO_ODR_OD4_Pos)            /*!< 0x00000010 */
+#define GPIO_ODR_OD4                     GPIO_ODR_OD4_Msk                      
+#define GPIO_ODR_OD5_Pos                 (5U)                                  
+#define GPIO_ODR_OD5_Msk                 (0x1UL << GPIO_ODR_OD5_Pos)            /*!< 0x00000020 */
+#define GPIO_ODR_OD5                     GPIO_ODR_OD5_Msk                      
+#define GPIO_ODR_OD6_Pos                 (6U)                                  
+#define GPIO_ODR_OD6_Msk                 (0x1UL << GPIO_ODR_OD6_Pos)            /*!< 0x00000040 */
+#define GPIO_ODR_OD6                     GPIO_ODR_OD6_Msk                      
+#define GPIO_ODR_OD7_Pos                 (7U)                                  
+#define GPIO_ODR_OD7_Msk                 (0x1UL << GPIO_ODR_OD7_Pos)            /*!< 0x00000080 */
+#define GPIO_ODR_OD7                     GPIO_ODR_OD7_Msk                      
+#define GPIO_ODR_OD8_Pos                 (8U)                                  
+#define GPIO_ODR_OD8_Msk                 (0x1UL << GPIO_ODR_OD8_Pos)            /*!< 0x00000100 */
+#define GPIO_ODR_OD8                     GPIO_ODR_OD8_Msk                      
+#define GPIO_ODR_OD9_Pos                 (9U)                                  
+#define GPIO_ODR_OD9_Msk                 (0x1UL << GPIO_ODR_OD9_Pos)            /*!< 0x00000200 */
+#define GPIO_ODR_OD9                     GPIO_ODR_OD9_Msk                      
+#define GPIO_ODR_OD10_Pos                (10U)                                 
+#define GPIO_ODR_OD10_Msk                (0x1UL << GPIO_ODR_OD10_Pos)           /*!< 0x00000400 */
+#define GPIO_ODR_OD10                    GPIO_ODR_OD10_Msk                     
+#define GPIO_ODR_OD11_Pos                (11U)                                 
+#define GPIO_ODR_OD11_Msk                (0x1UL << GPIO_ODR_OD11_Pos)           /*!< 0x00000800 */
+#define GPIO_ODR_OD11                    GPIO_ODR_OD11_Msk                     
+#define GPIO_ODR_OD12_Pos                (12U)                                 
+#define GPIO_ODR_OD12_Msk                (0x1UL << GPIO_ODR_OD12_Pos)           /*!< 0x00001000 */
+#define GPIO_ODR_OD12                    GPIO_ODR_OD12_Msk                     
+#define GPIO_ODR_OD13_Pos                (13U)                                 
+#define GPIO_ODR_OD13_Msk                (0x1UL << GPIO_ODR_OD13_Pos)           /*!< 0x00002000 */
+#define GPIO_ODR_OD13                    GPIO_ODR_OD13_Msk                     
+#define GPIO_ODR_OD14_Pos                (14U)                                 
+#define GPIO_ODR_OD14_Msk                (0x1UL << GPIO_ODR_OD14_Pos)           /*!< 0x00004000 */
+#define GPIO_ODR_OD14                    GPIO_ODR_OD14_Msk                     
+#define GPIO_ODR_OD15_Pos                (15U)                                 
+#define GPIO_ODR_OD15_Msk                (0x1UL << GPIO_ODR_OD15_Pos)           /*!< 0x00008000 */
+#define GPIO_ODR_OD15                    GPIO_ODR_OD15_Msk                     
+/* Legacy defines */
+#define GPIO_ODR_ODR_0                   GPIO_ODR_OD0
+#define GPIO_ODR_ODR_1                   GPIO_ODR_OD1
+#define GPIO_ODR_ODR_2                   GPIO_ODR_OD2
+#define GPIO_ODR_ODR_3                   GPIO_ODR_OD3
+#define GPIO_ODR_ODR_4                   GPIO_ODR_OD4
+#define GPIO_ODR_ODR_5                   GPIO_ODR_OD5
+#define GPIO_ODR_ODR_6                   GPIO_ODR_OD6
+#define GPIO_ODR_ODR_7                   GPIO_ODR_OD7
+#define GPIO_ODR_ODR_8                   GPIO_ODR_OD8
+#define GPIO_ODR_ODR_9                   GPIO_ODR_OD9
+#define GPIO_ODR_ODR_10                  GPIO_ODR_OD10
+#define GPIO_ODR_ODR_11                  GPIO_ODR_OD11
+#define GPIO_ODR_ODR_12                  GPIO_ODR_OD12
+#define GPIO_ODR_ODR_13                  GPIO_ODR_OD13
+#define GPIO_ODR_ODR_14                  GPIO_ODR_OD14
+#define GPIO_ODR_ODR_15                  GPIO_ODR_OD15
+
+/******************  Bits definition for GPIO_BSRR register  ******************/
+#define GPIO_BSRR_BS0_Pos                (0U)                                  
+#define GPIO_BSRR_BS0_Msk                (0x1UL << GPIO_BSRR_BS0_Pos)           /*!< 0x00000001 */
+#define GPIO_BSRR_BS0                    GPIO_BSRR_BS0_Msk                     
+#define GPIO_BSRR_BS1_Pos                (1U)                                  
+#define GPIO_BSRR_BS1_Msk                (0x1UL << GPIO_BSRR_BS1_Pos)           /*!< 0x00000002 */
+#define GPIO_BSRR_BS1                    GPIO_BSRR_BS1_Msk                     
+#define GPIO_BSRR_BS2_Pos                (2U)                                  
+#define GPIO_BSRR_BS2_Msk                (0x1UL << GPIO_BSRR_BS2_Pos)           /*!< 0x00000004 */
+#define GPIO_BSRR_BS2                    GPIO_BSRR_BS2_Msk                     
+#define GPIO_BSRR_BS3_Pos                (3U)                                  
+#define GPIO_BSRR_BS3_Msk                (0x1UL << GPIO_BSRR_BS3_Pos)           /*!< 0x00000008 */
+#define GPIO_BSRR_BS3                    GPIO_BSRR_BS3_Msk                     
+#define GPIO_BSRR_BS4_Pos                (4U)                                  
+#define GPIO_BSRR_BS4_Msk                (0x1UL << GPIO_BSRR_BS4_Pos)           /*!< 0x00000010 */
+#define GPIO_BSRR_BS4                    GPIO_BSRR_BS4_Msk                     
+#define GPIO_BSRR_BS5_Pos                (5U)                                  
+#define GPIO_BSRR_BS5_Msk                (0x1UL << GPIO_BSRR_BS5_Pos)           /*!< 0x00000020 */
+#define GPIO_BSRR_BS5                    GPIO_BSRR_BS5_Msk                     
+#define GPIO_BSRR_BS6_Pos                (6U)                                  
+#define GPIO_BSRR_BS6_Msk                (0x1UL << GPIO_BSRR_BS6_Pos)           /*!< 0x00000040 */
+#define GPIO_BSRR_BS6                    GPIO_BSRR_BS6_Msk                     
+#define GPIO_BSRR_BS7_Pos                (7U)                                  
+#define GPIO_BSRR_BS7_Msk                (0x1UL << GPIO_BSRR_BS7_Pos)           /*!< 0x00000080 */
+#define GPIO_BSRR_BS7                    GPIO_BSRR_BS7_Msk                     
+#define GPIO_BSRR_BS8_Pos                (8U)                                  
+#define GPIO_BSRR_BS8_Msk                (0x1UL << GPIO_BSRR_BS8_Pos)           /*!< 0x00000100 */
+#define GPIO_BSRR_BS8                    GPIO_BSRR_BS8_Msk                     
+#define GPIO_BSRR_BS9_Pos                (9U)                                  
+#define GPIO_BSRR_BS9_Msk                (0x1UL << GPIO_BSRR_BS9_Pos)           /*!< 0x00000200 */
+#define GPIO_BSRR_BS9                    GPIO_BSRR_BS9_Msk                     
+#define GPIO_BSRR_BS10_Pos               (10U)                                 
+#define GPIO_BSRR_BS10_Msk               (0x1UL << GPIO_BSRR_BS10_Pos)          /*!< 0x00000400 */
+#define GPIO_BSRR_BS10                   GPIO_BSRR_BS10_Msk                    
+#define GPIO_BSRR_BS11_Pos               (11U)                                 
+#define GPIO_BSRR_BS11_Msk               (0x1UL << GPIO_BSRR_BS11_Pos)          /*!< 0x00000800 */
+#define GPIO_BSRR_BS11                   GPIO_BSRR_BS11_Msk                    
+#define GPIO_BSRR_BS12_Pos               (12U)                                 
+#define GPIO_BSRR_BS12_Msk               (0x1UL << GPIO_BSRR_BS12_Pos)          /*!< 0x00001000 */
+#define GPIO_BSRR_BS12                   GPIO_BSRR_BS12_Msk                    
+#define GPIO_BSRR_BS13_Pos               (13U)                                 
+#define GPIO_BSRR_BS13_Msk               (0x1UL << GPIO_BSRR_BS13_Pos)          /*!< 0x00002000 */
+#define GPIO_BSRR_BS13                   GPIO_BSRR_BS13_Msk                    
+#define GPIO_BSRR_BS14_Pos               (14U)                                 
+#define GPIO_BSRR_BS14_Msk               (0x1UL << GPIO_BSRR_BS14_Pos)          /*!< 0x00004000 */
+#define GPIO_BSRR_BS14                   GPIO_BSRR_BS14_Msk                    
+#define GPIO_BSRR_BS15_Pos               (15U)                                 
+#define GPIO_BSRR_BS15_Msk               (0x1UL << GPIO_BSRR_BS15_Pos)          /*!< 0x00008000 */
+#define GPIO_BSRR_BS15                   GPIO_BSRR_BS15_Msk                    
+#define GPIO_BSRR_BR0_Pos                (16U)                                 
+#define GPIO_BSRR_BR0_Msk                (0x1UL << GPIO_BSRR_BR0_Pos)           /*!< 0x00010000 */
+#define GPIO_BSRR_BR0                    GPIO_BSRR_BR0_Msk                     
+#define GPIO_BSRR_BR1_Pos                (17U)                                 
+#define GPIO_BSRR_BR1_Msk                (0x1UL << GPIO_BSRR_BR1_Pos)           /*!< 0x00020000 */
+#define GPIO_BSRR_BR1                    GPIO_BSRR_BR1_Msk                     
+#define GPIO_BSRR_BR2_Pos                (18U)                                 
+#define GPIO_BSRR_BR2_Msk                (0x1UL << GPIO_BSRR_BR2_Pos)           /*!< 0x00040000 */
+#define GPIO_BSRR_BR2                    GPIO_BSRR_BR2_Msk                     
+#define GPIO_BSRR_BR3_Pos                (19U)                                 
+#define GPIO_BSRR_BR3_Msk                (0x1UL << GPIO_BSRR_BR3_Pos)           /*!< 0x00080000 */
+#define GPIO_BSRR_BR3                    GPIO_BSRR_BR3_Msk                     
+#define GPIO_BSRR_BR4_Pos                (20U)                                 
+#define GPIO_BSRR_BR4_Msk                (0x1UL << GPIO_BSRR_BR4_Pos)           /*!< 0x00100000 */
+#define GPIO_BSRR_BR4                    GPIO_BSRR_BR4_Msk                     
+#define GPIO_BSRR_BR5_Pos                (21U)                                 
+#define GPIO_BSRR_BR5_Msk                (0x1UL << GPIO_BSRR_BR5_Pos)           /*!< 0x00200000 */
+#define GPIO_BSRR_BR5                    GPIO_BSRR_BR5_Msk                     
+#define GPIO_BSRR_BR6_Pos                (22U)                                 
+#define GPIO_BSRR_BR6_Msk                (0x1UL << GPIO_BSRR_BR6_Pos)           /*!< 0x00400000 */
+#define GPIO_BSRR_BR6                    GPIO_BSRR_BR6_Msk                     
+#define GPIO_BSRR_BR7_Pos                (23U)                                 
+#define GPIO_BSRR_BR7_Msk                (0x1UL << GPIO_BSRR_BR7_Pos)           /*!< 0x00800000 */
+#define GPIO_BSRR_BR7                    GPIO_BSRR_BR7_Msk                     
+#define GPIO_BSRR_BR8_Pos                (24U)                                 
+#define GPIO_BSRR_BR8_Msk                (0x1UL << GPIO_BSRR_BR8_Pos)           /*!< 0x01000000 */
+#define GPIO_BSRR_BR8                    GPIO_BSRR_BR8_Msk                     
+#define GPIO_BSRR_BR9_Pos                (25U)                                 
+#define GPIO_BSRR_BR9_Msk                (0x1UL << GPIO_BSRR_BR9_Pos)           /*!< 0x02000000 */
+#define GPIO_BSRR_BR9                    GPIO_BSRR_BR9_Msk                     
+#define GPIO_BSRR_BR10_Pos               (26U)                                 
+#define GPIO_BSRR_BR10_Msk               (0x1UL << GPIO_BSRR_BR10_Pos)          /*!< 0x04000000 */
+#define GPIO_BSRR_BR10                   GPIO_BSRR_BR10_Msk                    
+#define GPIO_BSRR_BR11_Pos               (27U)                                 
+#define GPIO_BSRR_BR11_Msk               (0x1UL << GPIO_BSRR_BR11_Pos)          /*!< 0x08000000 */
+#define GPIO_BSRR_BR11                   GPIO_BSRR_BR11_Msk                    
+#define GPIO_BSRR_BR12_Pos               (28U)                                 
+#define GPIO_BSRR_BR12_Msk               (0x1UL << GPIO_BSRR_BR12_Pos)          /*!< 0x10000000 */
+#define GPIO_BSRR_BR12                   GPIO_BSRR_BR12_Msk                    
+#define GPIO_BSRR_BR13_Pos               (29U)                                 
+#define GPIO_BSRR_BR13_Msk               (0x1UL << GPIO_BSRR_BR13_Pos)          /*!< 0x20000000 */
+#define GPIO_BSRR_BR13                   GPIO_BSRR_BR13_Msk                    
+#define GPIO_BSRR_BR14_Pos               (30U)                                 
+#define GPIO_BSRR_BR14_Msk               (0x1UL << GPIO_BSRR_BR14_Pos)          /*!< 0x40000000 */
+#define GPIO_BSRR_BR14                   GPIO_BSRR_BR14_Msk                    
+#define GPIO_BSRR_BR15_Pos               (31U)                                 
+#define GPIO_BSRR_BR15_Msk               (0x1UL << GPIO_BSRR_BR15_Pos)          /*!< 0x80000000 */
+#define GPIO_BSRR_BR15                   GPIO_BSRR_BR15_Msk                    
+
+/* Legacy defines */
+#define GPIO_BSRR_BS_0                   GPIO_BSRR_BS0
+#define GPIO_BSRR_BS_1                   GPIO_BSRR_BS1
+#define GPIO_BSRR_BS_2                   GPIO_BSRR_BS2
+#define GPIO_BSRR_BS_3                   GPIO_BSRR_BS3
+#define GPIO_BSRR_BS_4                   GPIO_BSRR_BS4
+#define GPIO_BSRR_BS_5                   GPIO_BSRR_BS5
+#define GPIO_BSRR_BS_6                   GPIO_BSRR_BS6
+#define GPIO_BSRR_BS_7                   GPIO_BSRR_BS7
+#define GPIO_BSRR_BS_8                   GPIO_BSRR_BS8
+#define GPIO_BSRR_BS_9                   GPIO_BSRR_BS9
+#define GPIO_BSRR_BS_10                  GPIO_BSRR_BS10
+#define GPIO_BSRR_BS_11                  GPIO_BSRR_BS11
+#define GPIO_BSRR_BS_12                  GPIO_BSRR_BS12
+#define GPIO_BSRR_BS_13                  GPIO_BSRR_BS13
+#define GPIO_BSRR_BS_14                  GPIO_BSRR_BS14
+#define GPIO_BSRR_BS_15                  GPIO_BSRR_BS15
+#define GPIO_BSRR_BR_0                   GPIO_BSRR_BR0
+#define GPIO_BSRR_BR_1                   GPIO_BSRR_BR1
+#define GPIO_BSRR_BR_2                   GPIO_BSRR_BR2
+#define GPIO_BSRR_BR_3                   GPIO_BSRR_BR3
+#define GPIO_BSRR_BR_4                   GPIO_BSRR_BR4
+#define GPIO_BSRR_BR_5                   GPIO_BSRR_BR5
+#define GPIO_BSRR_BR_6                   GPIO_BSRR_BR6
+#define GPIO_BSRR_BR_7                   GPIO_BSRR_BR7
+#define GPIO_BSRR_BR_8                   GPIO_BSRR_BR8
+#define GPIO_BSRR_BR_9                   GPIO_BSRR_BR9
+#define GPIO_BSRR_BR_10                  GPIO_BSRR_BR10
+#define GPIO_BSRR_BR_11                  GPIO_BSRR_BR11
+#define GPIO_BSRR_BR_12                  GPIO_BSRR_BR12
+#define GPIO_BSRR_BR_13                  GPIO_BSRR_BR13
+#define GPIO_BSRR_BR_14                  GPIO_BSRR_BR14
+#define GPIO_BSRR_BR_15                  GPIO_BSRR_BR15
+#define GPIO_BRR_BR0                     GPIO_BSRR_BR0
+#define GPIO_BRR_BR0_Pos                 GPIO_BSRR_BR0_Pos
+#define GPIO_BRR_BR0_Msk                 GPIO_BSRR_BR0_Msk
+#define GPIO_BRR_BR1                     GPIO_BSRR_BR1
+#define GPIO_BRR_BR1_Pos                 GPIO_BSRR_BR1_Pos
+#define GPIO_BRR_BR1_Msk                 GPIO_BSRR_BR1_Msk
+#define GPIO_BRR_BR2                     GPIO_BSRR_BR2
+#define GPIO_BRR_BR2_Pos                 GPIO_BSRR_BR2_Pos
+#define GPIO_BRR_BR2_Msk                 GPIO_BSRR_BR2_Msk
+#define GPIO_BRR_BR3                     GPIO_BSRR_BR3
+#define GPIO_BRR_BR3_Pos                 GPIO_BSRR_BR3_Pos
+#define GPIO_BRR_BR3_Msk                 GPIO_BSRR_BR3_Msk
+#define GPIO_BRR_BR4                     GPIO_BSRR_BR4
+#define GPIO_BRR_BR4_Pos                 GPIO_BSRR_BR4_Pos
+#define GPIO_BRR_BR4_Msk                 GPIO_BSRR_BR4_Msk
+#define GPIO_BRR_BR5                     GPIO_BSRR_BR5
+#define GPIO_BRR_BR5_Pos                 GPIO_BSRR_BR5_Pos
+#define GPIO_BRR_BR5_Msk                 GPIO_BSRR_BR5_Msk
+#define GPIO_BRR_BR6                     GPIO_BSRR_BR6
+#define GPIO_BRR_BR6_Pos                 GPIO_BSRR_BR6_Pos
+#define GPIO_BRR_BR6_Msk                 GPIO_BSRR_BR6_Msk
+#define GPIO_BRR_BR7                     GPIO_BSRR_BR7
+#define GPIO_BRR_BR7_Pos                 GPIO_BSRR_BR7_Pos
+#define GPIO_BRR_BR7_Msk                 GPIO_BSRR_BR7_Msk
+#define GPIO_BRR_BR8                     GPIO_BSRR_BR8
+#define GPIO_BRR_BR8_Pos                 GPIO_BSRR_BR8_Pos
+#define GPIO_BRR_BR8_Msk                 GPIO_BSRR_BR8_Msk
+#define GPIO_BRR_BR9                     GPIO_BSRR_BR9
+#define GPIO_BRR_BR9_Pos                 GPIO_BSRR_BR9_Pos
+#define GPIO_BRR_BR9_Msk                 GPIO_BSRR_BR9_Msk
+#define GPIO_BRR_BR10                    GPIO_BSRR_BR10
+#define GPIO_BRR_BR10_Pos                GPIO_BSRR_BR10_Pos
+#define GPIO_BRR_BR10_Msk                GPIO_BSRR_BR10_Msk
+#define GPIO_BRR_BR11                    GPIO_BSRR_BR11
+#define GPIO_BRR_BR11_Pos                GPIO_BSRR_BR11_Pos
+#define GPIO_BRR_BR11_Msk                GPIO_BSRR_BR11_Msk
+#define GPIO_BRR_BR12                    GPIO_BSRR_BR12
+#define GPIO_BRR_BR12_Pos                GPIO_BSRR_BR12_Pos
+#define GPIO_BRR_BR12_Msk                GPIO_BSRR_BR12_Msk
+#define GPIO_BRR_BR13                    GPIO_BSRR_BR13
+#define GPIO_BRR_BR13_Pos                GPIO_BSRR_BR13_Pos
+#define GPIO_BRR_BR13_Msk                GPIO_BSRR_BR13_Msk
+#define GPIO_BRR_BR14                    GPIO_BSRR_BR14
+#define GPIO_BRR_BR14_Pos                GPIO_BSRR_BR14_Pos
+#define GPIO_BRR_BR14_Msk                GPIO_BSRR_BR14_Msk
+#define GPIO_BRR_BR15                    GPIO_BSRR_BR15
+#define GPIO_BRR_BR15_Pos                GPIO_BSRR_BR15_Pos
+#define GPIO_BRR_BR15_Msk                GPIO_BSRR_BR15_Msk 
+/****************** Bit definition for GPIO_LCKR register *********************/
+#define GPIO_LCKR_LCK0_Pos               (0U)                                  
+#define GPIO_LCKR_LCK0_Msk               (0x1UL << GPIO_LCKR_LCK0_Pos)          /*!< 0x00000001 */
+#define GPIO_LCKR_LCK0                   GPIO_LCKR_LCK0_Msk                    
+#define GPIO_LCKR_LCK1_Pos               (1U)                                  
+#define GPIO_LCKR_LCK1_Msk               (0x1UL << GPIO_LCKR_LCK1_Pos)          /*!< 0x00000002 */
+#define GPIO_LCKR_LCK1                   GPIO_LCKR_LCK1_Msk                    
+#define GPIO_LCKR_LCK2_Pos               (2U)                                  
+#define GPIO_LCKR_LCK2_Msk               (0x1UL << GPIO_LCKR_LCK2_Pos)          /*!< 0x00000004 */
+#define GPIO_LCKR_LCK2                   GPIO_LCKR_LCK2_Msk                    
+#define GPIO_LCKR_LCK3_Pos               (3U)                                  
+#define GPIO_LCKR_LCK3_Msk               (0x1UL << GPIO_LCKR_LCK3_Pos)          /*!< 0x00000008 */
+#define GPIO_LCKR_LCK3                   GPIO_LCKR_LCK3_Msk                    
+#define GPIO_LCKR_LCK4_Pos               (4U)                                  
+#define GPIO_LCKR_LCK4_Msk               (0x1UL << GPIO_LCKR_LCK4_Pos)          /*!< 0x00000010 */
+#define GPIO_LCKR_LCK4                   GPIO_LCKR_LCK4_Msk                    
+#define GPIO_LCKR_LCK5_Pos               (5U)                                  
+#define GPIO_LCKR_LCK5_Msk               (0x1UL << GPIO_LCKR_LCK5_Pos)          /*!< 0x00000020 */
+#define GPIO_LCKR_LCK5                   GPIO_LCKR_LCK5_Msk                    
+#define GPIO_LCKR_LCK6_Pos               (6U)                                  
+#define GPIO_LCKR_LCK6_Msk               (0x1UL << GPIO_LCKR_LCK6_Pos)          /*!< 0x00000040 */
+#define GPIO_LCKR_LCK6                   GPIO_LCKR_LCK6_Msk                    
+#define GPIO_LCKR_LCK7_Pos               (7U)                                  
+#define GPIO_LCKR_LCK7_Msk               (0x1UL << GPIO_LCKR_LCK7_Pos)          /*!< 0x00000080 */
+#define GPIO_LCKR_LCK7                   GPIO_LCKR_LCK7_Msk                    
+#define GPIO_LCKR_LCK8_Pos               (8U)                                  
+#define GPIO_LCKR_LCK8_Msk               (0x1UL << GPIO_LCKR_LCK8_Pos)          /*!< 0x00000100 */
+#define GPIO_LCKR_LCK8                   GPIO_LCKR_LCK8_Msk                    
+#define GPIO_LCKR_LCK9_Pos               (9U)                                  
+#define GPIO_LCKR_LCK9_Msk               (0x1UL << GPIO_LCKR_LCK9_Pos)          /*!< 0x00000200 */
+#define GPIO_LCKR_LCK9                   GPIO_LCKR_LCK9_Msk                    
+#define GPIO_LCKR_LCK10_Pos              (10U)                                 
+#define GPIO_LCKR_LCK10_Msk              (0x1UL << GPIO_LCKR_LCK10_Pos)         /*!< 0x00000400 */
+#define GPIO_LCKR_LCK10                  GPIO_LCKR_LCK10_Msk                   
+#define GPIO_LCKR_LCK11_Pos              (11U)                                 
+#define GPIO_LCKR_LCK11_Msk              (0x1UL << GPIO_LCKR_LCK11_Pos)         /*!< 0x00000800 */
+#define GPIO_LCKR_LCK11                  GPIO_LCKR_LCK11_Msk                   
+#define GPIO_LCKR_LCK12_Pos              (12U)                                 
+#define GPIO_LCKR_LCK12_Msk              (0x1UL << GPIO_LCKR_LCK12_Pos)         /*!< 0x00001000 */
+#define GPIO_LCKR_LCK12                  GPIO_LCKR_LCK12_Msk                   
+#define GPIO_LCKR_LCK13_Pos              (13U)                                 
+#define GPIO_LCKR_LCK13_Msk              (0x1UL << GPIO_LCKR_LCK13_Pos)         /*!< 0x00002000 */
+#define GPIO_LCKR_LCK13                  GPIO_LCKR_LCK13_Msk                   
+#define GPIO_LCKR_LCK14_Pos              (14U)                                 
+#define GPIO_LCKR_LCK14_Msk              (0x1UL << GPIO_LCKR_LCK14_Pos)         /*!< 0x00004000 */
+#define GPIO_LCKR_LCK14                  GPIO_LCKR_LCK14_Msk                   
+#define GPIO_LCKR_LCK15_Pos              (15U)                                 
+#define GPIO_LCKR_LCK15_Msk              (0x1UL << GPIO_LCKR_LCK15_Pos)         /*!< 0x00008000 */
+#define GPIO_LCKR_LCK15                  GPIO_LCKR_LCK15_Msk                   
+#define GPIO_LCKR_LCKK_Pos               (16U)                                 
+#define GPIO_LCKR_LCKK_Msk               (0x1UL << GPIO_LCKR_LCKK_Pos)          /*!< 0x00010000 */
+#define GPIO_LCKR_LCKK                   GPIO_LCKR_LCKK_Msk                    
+/****************** Bit definition for GPIO_AFRL register *********************/
+#define GPIO_AFRL_AFSEL0_Pos             (0U)                                  
+#define GPIO_AFRL_AFSEL0_Msk             (0xFUL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x0000000F */
+#define GPIO_AFRL_AFSEL0                 GPIO_AFRL_AFSEL0_Msk                  
+#define GPIO_AFRL_AFSEL0_0               (0x1UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000001 */
+#define GPIO_AFRL_AFSEL0_1               (0x2UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000002 */
+#define GPIO_AFRL_AFSEL0_2               (0x4UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000004 */
+#define GPIO_AFRL_AFSEL0_3               (0x8UL << GPIO_AFRL_AFSEL0_Pos)        /*!< 0x00000008 */
+#define GPIO_AFRL_AFSEL1_Pos             (4U)                                  
+#define GPIO_AFRL_AFSEL1_Msk             (0xFUL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x000000F0 */
+#define GPIO_AFRL_AFSEL1                 GPIO_AFRL_AFSEL1_Msk                  
+#define GPIO_AFRL_AFSEL1_0               (0x1UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000010 */
+#define GPIO_AFRL_AFSEL1_1               (0x2UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000020 */
+#define GPIO_AFRL_AFSEL1_2               (0x4UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000040 */
+#define GPIO_AFRL_AFSEL1_3               (0x8UL << GPIO_AFRL_AFSEL1_Pos)        /*!< 0x00000080 */
+#define GPIO_AFRL_AFSEL2_Pos             (8U)                                  
+#define GPIO_AFRL_AFSEL2_Msk             (0xFUL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000F00 */
+#define GPIO_AFRL_AFSEL2                 GPIO_AFRL_AFSEL2_Msk                  
+#define GPIO_AFRL_AFSEL2_0               (0x1UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000100 */
+#define GPIO_AFRL_AFSEL2_1               (0x2UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000200 */
+#define GPIO_AFRL_AFSEL2_2               (0x4UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000400 */
+#define GPIO_AFRL_AFSEL2_3               (0x8UL << GPIO_AFRL_AFSEL2_Pos)        /*!< 0x00000800 */
+#define GPIO_AFRL_AFSEL3_Pos             (12U)                                 
+#define GPIO_AFRL_AFSEL3_Msk             (0xFUL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x0000F000 */
+#define GPIO_AFRL_AFSEL3                 GPIO_AFRL_AFSEL3_Msk                  
+#define GPIO_AFRL_AFSEL3_0               (0x1UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00001000 */
+#define GPIO_AFRL_AFSEL3_1               (0x2UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00002000 */
+#define GPIO_AFRL_AFSEL3_2               (0x4UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00004000 */
+#define GPIO_AFRL_AFSEL3_3               (0x8UL << GPIO_AFRL_AFSEL3_Pos)        /*!< 0x00008000 */
+#define GPIO_AFRL_AFSEL4_Pos             (16U)                                 
+#define GPIO_AFRL_AFSEL4_Msk             (0xFUL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x000F0000 */
+#define GPIO_AFRL_AFSEL4                 GPIO_AFRL_AFSEL4_Msk                  
+#define GPIO_AFRL_AFSEL4_0               (0x1UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00010000 */
+#define GPIO_AFRL_AFSEL4_1               (0x2UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00020000 */
+#define GPIO_AFRL_AFSEL4_2               (0x4UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00040000 */
+#define GPIO_AFRL_AFSEL4_3               (0x8UL << GPIO_AFRL_AFSEL4_Pos)        /*!< 0x00080000 */
+#define GPIO_AFRL_AFSEL5_Pos             (20U)                                 
+#define GPIO_AFRL_AFSEL5_Msk             (0xFUL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00F00000 */
+#define GPIO_AFRL_AFSEL5                 GPIO_AFRL_AFSEL5_Msk                  
+#define GPIO_AFRL_AFSEL5_0               (0x1UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00100000 */
+#define GPIO_AFRL_AFSEL5_1               (0x2UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00200000 */
+#define GPIO_AFRL_AFSEL5_2               (0x4UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00400000 */
+#define GPIO_AFRL_AFSEL5_3               (0x8UL << GPIO_AFRL_AFSEL5_Pos)        /*!< 0x00800000 */
+#define GPIO_AFRL_AFSEL6_Pos             (24U)                                 
+#define GPIO_AFRL_AFSEL6_Msk             (0xFUL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x0F000000 */
+#define GPIO_AFRL_AFSEL6                 GPIO_AFRL_AFSEL6_Msk                  
+#define GPIO_AFRL_AFSEL6_0               (0x1UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x01000000 */
+#define GPIO_AFRL_AFSEL6_1               (0x2UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x02000000 */
+#define GPIO_AFRL_AFSEL6_2               (0x4UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x04000000 */
+#define GPIO_AFRL_AFSEL6_3               (0x8UL << GPIO_AFRL_AFSEL6_Pos)        /*!< 0x08000000 */
+#define GPIO_AFRL_AFSEL7_Pos             (28U)                                 
+#define GPIO_AFRL_AFSEL7_Msk             (0xFUL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0xF0000000 */
+#define GPIO_AFRL_AFSEL7                 GPIO_AFRL_AFSEL7_Msk                  
+#define GPIO_AFRL_AFSEL7_0               (0x1UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x10000000 */
+#define GPIO_AFRL_AFSEL7_1               (0x2UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x20000000 */
+#define GPIO_AFRL_AFSEL7_2               (0x4UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x40000000 */
+#define GPIO_AFRL_AFSEL7_3               (0x8UL << GPIO_AFRL_AFSEL7_Pos)        /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRL_AFRL0                  GPIO_AFRL_AFSEL0
+#define GPIO_AFRL_AFRL0_0                GPIO_AFRL_AFSEL0_0
+#define GPIO_AFRL_AFRL0_1                GPIO_AFRL_AFSEL0_1
+#define GPIO_AFRL_AFRL0_2                GPIO_AFRL_AFSEL0_2
+#define GPIO_AFRL_AFRL0_3                GPIO_AFRL_AFSEL0_3
+#define GPIO_AFRL_AFRL1                  GPIO_AFRL_AFSEL1
+#define GPIO_AFRL_AFRL1_0                GPIO_AFRL_AFSEL1_0
+#define GPIO_AFRL_AFRL1_1                GPIO_AFRL_AFSEL1_1
+#define GPIO_AFRL_AFRL1_2                GPIO_AFRL_AFSEL1_2
+#define GPIO_AFRL_AFRL1_3                GPIO_AFRL_AFSEL1_3
+#define GPIO_AFRL_AFRL2                  GPIO_AFRL_AFSEL2
+#define GPIO_AFRL_AFRL2_0                GPIO_AFRL_AFSEL2_0
+#define GPIO_AFRL_AFRL2_1                GPIO_AFRL_AFSEL2_1
+#define GPIO_AFRL_AFRL2_2                GPIO_AFRL_AFSEL2_2
+#define GPIO_AFRL_AFRL2_3                GPIO_AFRL_AFSEL2_3
+#define GPIO_AFRL_AFRL3                  GPIO_AFRL_AFSEL3
+#define GPIO_AFRL_AFRL3_0                GPIO_AFRL_AFSEL3_0
+#define GPIO_AFRL_AFRL3_1                GPIO_AFRL_AFSEL3_1
+#define GPIO_AFRL_AFRL3_2                GPIO_AFRL_AFSEL3_2
+#define GPIO_AFRL_AFRL3_3                GPIO_AFRL_AFSEL3_3
+#define GPIO_AFRL_AFRL4                  GPIO_AFRL_AFSEL4
+#define GPIO_AFRL_AFRL4_0                GPIO_AFRL_AFSEL4_0
+#define GPIO_AFRL_AFRL4_1                GPIO_AFRL_AFSEL4_1
+#define GPIO_AFRL_AFRL4_2                GPIO_AFRL_AFSEL4_2
+#define GPIO_AFRL_AFRL4_3                GPIO_AFRL_AFSEL4_3
+#define GPIO_AFRL_AFRL5                  GPIO_AFRL_AFSEL5
+#define GPIO_AFRL_AFRL5_0                GPIO_AFRL_AFSEL5_0
+#define GPIO_AFRL_AFRL5_1                GPIO_AFRL_AFSEL5_1
+#define GPIO_AFRL_AFRL5_2                GPIO_AFRL_AFSEL5_2
+#define GPIO_AFRL_AFRL5_3                GPIO_AFRL_AFSEL5_3
+#define GPIO_AFRL_AFRL6                  GPIO_AFRL_AFSEL6
+#define GPIO_AFRL_AFRL6_0                GPIO_AFRL_AFSEL6_0
+#define GPIO_AFRL_AFRL6_1                GPIO_AFRL_AFSEL6_1
+#define GPIO_AFRL_AFRL6_2                GPIO_AFRL_AFSEL6_2
+#define GPIO_AFRL_AFRL6_3                GPIO_AFRL_AFSEL6_3
+#define GPIO_AFRL_AFRL7                  GPIO_AFRL_AFSEL7
+#define GPIO_AFRL_AFRL7_0                GPIO_AFRL_AFSEL7_0
+#define GPIO_AFRL_AFRL7_1                GPIO_AFRL_AFSEL7_1
+#define GPIO_AFRL_AFRL7_2                GPIO_AFRL_AFSEL7_2
+#define GPIO_AFRL_AFRL7_3                GPIO_AFRL_AFSEL7_3
+
+/****************** Bit definition for GPIO_AFRH register *********************/
+#define GPIO_AFRH_AFSEL8_Pos             (0U)                                  
+#define GPIO_AFRH_AFSEL8_Msk             (0xFUL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x0000000F */
+#define GPIO_AFRH_AFSEL8                 GPIO_AFRH_AFSEL8_Msk                  
+#define GPIO_AFRH_AFSEL8_0               (0x1UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000001 */
+#define GPIO_AFRH_AFSEL8_1               (0x2UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000002 */
+#define GPIO_AFRH_AFSEL8_2               (0x4UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000004 */
+#define GPIO_AFRH_AFSEL8_3               (0x8UL << GPIO_AFRH_AFSEL8_Pos)        /*!< 0x00000008 */
+#define GPIO_AFRH_AFSEL9_Pos             (4U)                                  
+#define GPIO_AFRH_AFSEL9_Msk             (0xFUL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x000000F0 */
+#define GPIO_AFRH_AFSEL9                 GPIO_AFRH_AFSEL9_Msk                  
+#define GPIO_AFRH_AFSEL9_0               (0x1UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000010 */
+#define GPIO_AFRH_AFSEL9_1               (0x2UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000020 */
+#define GPIO_AFRH_AFSEL9_2               (0x4UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000040 */
+#define GPIO_AFRH_AFSEL9_3               (0x8UL << GPIO_AFRH_AFSEL9_Pos)        /*!< 0x00000080 */
+#define GPIO_AFRH_AFSEL10_Pos            (8U)                                  
+#define GPIO_AFRH_AFSEL10_Msk            (0xFUL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000F00 */
+#define GPIO_AFRH_AFSEL10                GPIO_AFRH_AFSEL10_Msk                 
+#define GPIO_AFRH_AFSEL10_0              (0x1UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000100 */
+#define GPIO_AFRH_AFSEL10_1              (0x2UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000200 */
+#define GPIO_AFRH_AFSEL10_2              (0x4UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000400 */
+#define GPIO_AFRH_AFSEL10_3              (0x8UL << GPIO_AFRH_AFSEL10_Pos)       /*!< 0x00000800 */
+#define GPIO_AFRH_AFSEL11_Pos            (12U)                                 
+#define GPIO_AFRH_AFSEL11_Msk            (0xFUL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x0000F000 */
+#define GPIO_AFRH_AFSEL11                GPIO_AFRH_AFSEL11_Msk                 
+#define GPIO_AFRH_AFSEL11_0              (0x1UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00001000 */
+#define GPIO_AFRH_AFSEL11_1              (0x2UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00002000 */
+#define GPIO_AFRH_AFSEL11_2              (0x4UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00004000 */
+#define GPIO_AFRH_AFSEL11_3              (0x8UL << GPIO_AFRH_AFSEL11_Pos)       /*!< 0x00008000 */
+#define GPIO_AFRH_AFSEL12_Pos            (16U)                                 
+#define GPIO_AFRH_AFSEL12_Msk            (0xFUL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x000F0000 */
+#define GPIO_AFRH_AFSEL12                GPIO_AFRH_AFSEL12_Msk                 
+#define GPIO_AFRH_AFSEL12_0              (0x1UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00010000 */
+#define GPIO_AFRH_AFSEL12_1              (0x2UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00020000 */
+#define GPIO_AFRH_AFSEL12_2              (0x4UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00040000 */
+#define GPIO_AFRH_AFSEL12_3              (0x8UL << GPIO_AFRH_AFSEL12_Pos)       /*!< 0x00080000 */
+#define GPIO_AFRH_AFSEL13_Pos            (20U)                                 
+#define GPIO_AFRH_AFSEL13_Msk            (0xFUL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00F00000 */
+#define GPIO_AFRH_AFSEL13                GPIO_AFRH_AFSEL13_Msk                 
+#define GPIO_AFRH_AFSEL13_0              (0x1UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00100000 */
+#define GPIO_AFRH_AFSEL13_1              (0x2UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00200000 */
+#define GPIO_AFRH_AFSEL13_2              (0x4UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00400000 */
+#define GPIO_AFRH_AFSEL13_3              (0x8UL << GPIO_AFRH_AFSEL13_Pos)       /*!< 0x00800000 */
+#define GPIO_AFRH_AFSEL14_Pos            (24U)                                 
+#define GPIO_AFRH_AFSEL14_Msk            (0xFUL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x0F000000 */
+#define GPIO_AFRH_AFSEL14                GPIO_AFRH_AFSEL14_Msk                 
+#define GPIO_AFRH_AFSEL14_0              (0x1UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x01000000 */
+#define GPIO_AFRH_AFSEL14_1              (0x2UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x02000000 */
+#define GPIO_AFRH_AFSEL14_2              (0x4UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x04000000 */
+#define GPIO_AFRH_AFSEL14_3              (0x8UL << GPIO_AFRH_AFSEL14_Pos)       /*!< 0x08000000 */
+#define GPIO_AFRH_AFSEL15_Pos            (28U)                                 
+#define GPIO_AFRH_AFSEL15_Msk            (0xFUL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0xF0000000 */
+#define GPIO_AFRH_AFSEL15                GPIO_AFRH_AFSEL15_Msk                 
+#define GPIO_AFRH_AFSEL15_0              (0x1UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x10000000 */
+#define GPIO_AFRH_AFSEL15_1              (0x2UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x20000000 */
+#define GPIO_AFRH_AFSEL15_2              (0x4UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x40000000 */
+#define GPIO_AFRH_AFSEL15_3              (0x8UL << GPIO_AFRH_AFSEL15_Pos)       /*!< 0x80000000 */
+
+/* Legacy defines */
+#define GPIO_AFRH_AFRH0                  GPIO_AFRH_AFSEL8
+#define GPIO_AFRH_AFRH0_0                GPIO_AFRH_AFSEL8_0
+#define GPIO_AFRH_AFRH0_1                GPIO_AFRH_AFSEL8_1
+#define GPIO_AFRH_AFRH0_2                GPIO_AFRH_AFSEL8_2
+#define GPIO_AFRH_AFRH0_3                GPIO_AFRH_AFSEL8_3
+#define GPIO_AFRH_AFRH1                  GPIO_AFRH_AFSEL9
+#define GPIO_AFRH_AFRH1_0                GPIO_AFRH_AFSEL9_0
+#define GPIO_AFRH_AFRH1_1                GPIO_AFRH_AFSEL9_1
+#define GPIO_AFRH_AFRH1_2                GPIO_AFRH_AFSEL9_2
+#define GPIO_AFRH_AFRH1_3                GPIO_AFRH_AFSEL9_3
+#define GPIO_AFRH_AFRH2                  GPIO_AFRH_AFSEL10
+#define GPIO_AFRH_AFRH2_0                GPIO_AFRH_AFSEL10_0
+#define GPIO_AFRH_AFRH2_1                GPIO_AFRH_AFSEL10_1
+#define GPIO_AFRH_AFRH2_2                GPIO_AFRH_AFSEL10_2
+#define GPIO_AFRH_AFRH2_3                GPIO_AFRH_AFSEL10_3
+#define GPIO_AFRH_AFRH3                  GPIO_AFRH_AFSEL11
+#define GPIO_AFRH_AFRH3_0                GPIO_AFRH_AFSEL11_0
+#define GPIO_AFRH_AFRH3_1                GPIO_AFRH_AFSEL11_1
+#define GPIO_AFRH_AFRH3_2                GPIO_AFRH_AFSEL11_2
+#define GPIO_AFRH_AFRH3_3                GPIO_AFRH_AFSEL11_3
+#define GPIO_AFRH_AFRH4                  GPIO_AFRH_AFSEL12
+#define GPIO_AFRH_AFRH4_0                GPIO_AFRH_AFSEL12_0
+#define GPIO_AFRH_AFRH4_1                GPIO_AFRH_AFSEL12_1
+#define GPIO_AFRH_AFRH4_2                GPIO_AFRH_AFSEL12_2
+#define GPIO_AFRH_AFRH4_3                GPIO_AFRH_AFSEL12_3
+#define GPIO_AFRH_AFRH5                  GPIO_AFRH_AFSEL13
+#define GPIO_AFRH_AFRH5_0                GPIO_AFRH_AFSEL13_0
+#define GPIO_AFRH_AFRH5_1                GPIO_AFRH_AFSEL13_1
+#define GPIO_AFRH_AFRH5_2                GPIO_AFRH_AFSEL13_2
+#define GPIO_AFRH_AFRH5_3                GPIO_AFRH_AFSEL13_3
+#define GPIO_AFRH_AFRH6                  GPIO_AFRH_AFSEL14
+#define GPIO_AFRH_AFRH6_0                GPIO_AFRH_AFSEL14_0
+#define GPIO_AFRH_AFRH6_1                GPIO_AFRH_AFSEL14_1
+#define GPIO_AFRH_AFRH6_2                GPIO_AFRH_AFSEL14_2
+#define GPIO_AFRH_AFRH6_3                GPIO_AFRH_AFSEL14_3
+#define GPIO_AFRH_AFRH7                  GPIO_AFRH_AFSEL15
+#define GPIO_AFRH_AFRH7_0                GPIO_AFRH_AFSEL15_0
+#define GPIO_AFRH_AFRH7_1                GPIO_AFRH_AFSEL15_1
+#define GPIO_AFRH_AFRH7_2                GPIO_AFRH_AFSEL15_2
+#define GPIO_AFRH_AFRH7_3                GPIO_AFRH_AFSEL15_3
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                      Inter-integrated Circuit Interface                    */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for I2C_CR1 register  ********************/
+#define I2C_CR1_PE_Pos            (0U)                                         
+#define I2C_CR1_PE_Msk            (0x1UL << I2C_CR1_PE_Pos)                     /*!< 0x00000001 */
+#define I2C_CR1_PE                I2C_CR1_PE_Msk                               /*!<Peripheral Enable                             */
+#define I2C_CR1_SMBUS_Pos         (1U)                                         
+#define I2C_CR1_SMBUS_Msk         (0x1UL << I2C_CR1_SMBUS_Pos)                  /*!< 0x00000002 */
+#define I2C_CR1_SMBUS             I2C_CR1_SMBUS_Msk                            /*!<SMBus Mode                                    */
+#define I2C_CR1_SMBTYPE_Pos       (3U)                                         
+#define I2C_CR1_SMBTYPE_Msk       (0x1UL << I2C_CR1_SMBTYPE_Pos)                /*!< 0x00000008 */
+#define I2C_CR1_SMBTYPE           I2C_CR1_SMBTYPE_Msk                          /*!<SMBus Type                                    */
+#define I2C_CR1_ENARP_Pos         (4U)                                         
+#define I2C_CR1_ENARP_Msk         (0x1UL << I2C_CR1_ENARP_Pos)                  /*!< 0x00000010 */
+#define I2C_CR1_ENARP             I2C_CR1_ENARP_Msk                            /*!<ARP Enable                                    */
+#define I2C_CR1_ENPEC_Pos         (5U)                                         
+#define I2C_CR1_ENPEC_Msk         (0x1UL << I2C_CR1_ENPEC_Pos)                  /*!< 0x00000020 */
+#define I2C_CR1_ENPEC             I2C_CR1_ENPEC_Msk                            /*!<PEC Enable                                    */
+#define I2C_CR1_ENGC_Pos          (6U)                                         
+#define I2C_CR1_ENGC_Msk          (0x1UL << I2C_CR1_ENGC_Pos)                   /*!< 0x00000040 */
+#define I2C_CR1_ENGC              I2C_CR1_ENGC_Msk                             /*!<General Call Enable                           */
+#define I2C_CR1_NOSTRETCH_Pos     (7U)                                         
+#define I2C_CR1_NOSTRETCH_Msk     (0x1UL << I2C_CR1_NOSTRETCH_Pos)              /*!< 0x00000080 */
+#define I2C_CR1_NOSTRETCH         I2C_CR1_NOSTRETCH_Msk                        /*!<Clock Stretching Disable (Slave mode)         */
+#define I2C_CR1_START_Pos         (8U)                                         
+#define I2C_CR1_START_Msk         (0x1UL << I2C_CR1_START_Pos)                  /*!< 0x00000100 */
+#define I2C_CR1_START             I2C_CR1_START_Msk                            /*!<Start Generation                              */
+#define I2C_CR1_STOP_Pos          (9U)                                         
+#define I2C_CR1_STOP_Msk          (0x1UL << I2C_CR1_STOP_Pos)                   /*!< 0x00000200 */
+#define I2C_CR1_STOP              I2C_CR1_STOP_Msk                             /*!<Stop Generation                               */
+#define I2C_CR1_ACK_Pos           (10U)                                        
+#define I2C_CR1_ACK_Msk           (0x1UL << I2C_CR1_ACK_Pos)                    /*!< 0x00000400 */
+#define I2C_CR1_ACK               I2C_CR1_ACK_Msk                              /*!<Acknowledge Enable                            */
+#define I2C_CR1_POS_Pos           (11U)                                        
+#define I2C_CR1_POS_Msk           (0x1UL << I2C_CR1_POS_Pos)                    /*!< 0x00000800 */
+#define I2C_CR1_POS               I2C_CR1_POS_Msk                              /*!<Acknowledge/PEC Position (for data reception) */
+#define I2C_CR1_PEC_Pos           (12U)                                        
+#define I2C_CR1_PEC_Msk           (0x1UL << I2C_CR1_PEC_Pos)                    /*!< 0x00001000 */
+#define I2C_CR1_PEC               I2C_CR1_PEC_Msk                              /*!<Packet Error Checking                         */
+#define I2C_CR1_ALERT_Pos         (13U)                                        
+#define I2C_CR1_ALERT_Msk         (0x1UL << I2C_CR1_ALERT_Pos)                  /*!< 0x00002000 */
+#define I2C_CR1_ALERT             I2C_CR1_ALERT_Msk                            /*!<SMBus Alert                                   */
+#define I2C_CR1_SWRST_Pos         (15U)                                        
+#define I2C_CR1_SWRST_Msk         (0x1UL << I2C_CR1_SWRST_Pos)                  /*!< 0x00008000 */
+#define I2C_CR1_SWRST             I2C_CR1_SWRST_Msk                            /*!<Software Reset                                */
+
+/*******************  Bit definition for I2C_CR2 register  ********************/
+#define I2C_CR2_FREQ_Pos          (0U)                                         
+#define I2C_CR2_FREQ_Msk          (0x3FUL << I2C_CR2_FREQ_Pos)                  /*!< 0x0000003F */
+#define I2C_CR2_FREQ              I2C_CR2_FREQ_Msk                             /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
+#define I2C_CR2_FREQ_0            (0x01UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000001 */
+#define I2C_CR2_FREQ_1            (0x02UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000002 */
+#define I2C_CR2_FREQ_2            (0x04UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000004 */
+#define I2C_CR2_FREQ_3            (0x08UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000008 */
+#define I2C_CR2_FREQ_4            (0x10UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000010 */
+#define I2C_CR2_FREQ_5            (0x20UL << I2C_CR2_FREQ_Pos)                  /*!< 0x00000020 */
+
+#define I2C_CR2_ITERREN_Pos       (8U)                                         
+#define I2C_CR2_ITERREN_Msk       (0x1UL << I2C_CR2_ITERREN_Pos)                /*!< 0x00000100 */
+#define I2C_CR2_ITERREN           I2C_CR2_ITERREN_Msk                          /*!<Error Interrupt Enable  */
+#define I2C_CR2_ITEVTEN_Pos       (9U)                                         
+#define I2C_CR2_ITEVTEN_Msk       (0x1UL << I2C_CR2_ITEVTEN_Pos)                /*!< 0x00000200 */
+#define I2C_CR2_ITEVTEN           I2C_CR2_ITEVTEN_Msk                          /*!<Event Interrupt Enable  */
+#define I2C_CR2_ITBUFEN_Pos       (10U)                                        
+#define I2C_CR2_ITBUFEN_Msk       (0x1UL << I2C_CR2_ITBUFEN_Pos)                /*!< 0x00000400 */
+#define I2C_CR2_ITBUFEN           I2C_CR2_ITBUFEN_Msk                          /*!<Buffer Interrupt Enable */
+#define I2C_CR2_DMAEN_Pos         (11U)                                        
+#define I2C_CR2_DMAEN_Msk         (0x1UL << I2C_CR2_DMAEN_Pos)                  /*!< 0x00000800 */
+#define I2C_CR2_DMAEN             I2C_CR2_DMAEN_Msk                            /*!<DMA Requests Enable     */
+#define I2C_CR2_LAST_Pos          (12U)                                        
+#define I2C_CR2_LAST_Msk          (0x1UL << I2C_CR2_LAST_Pos)                   /*!< 0x00001000 */
+#define I2C_CR2_LAST              I2C_CR2_LAST_Msk                             /*!<DMA Last Transfer       */
+
+/*******************  Bit definition for I2C_OAR1 register  *******************/
+#define I2C_OAR1_ADD1_7           0x000000FEU                                  /*!<Interface Address */
+#define I2C_OAR1_ADD8_9           0x00000300U                                  /*!<Interface Address */
+
+#define I2C_OAR1_ADD0_Pos         (0U)                                         
+#define I2C_OAR1_ADD0_Msk         (0x1UL << I2C_OAR1_ADD0_Pos)                  /*!< 0x00000001 */
+#define I2C_OAR1_ADD0             I2C_OAR1_ADD0_Msk                            /*!<Bit 0 */
+#define I2C_OAR1_ADD1_Pos         (1U)                                         
+#define I2C_OAR1_ADD1_Msk         (0x1UL << I2C_OAR1_ADD1_Pos)                  /*!< 0x00000002 */
+#define I2C_OAR1_ADD1             I2C_OAR1_ADD1_Msk                            /*!<Bit 1 */
+#define I2C_OAR1_ADD2_Pos         (2U)                                         
+#define I2C_OAR1_ADD2_Msk         (0x1UL << I2C_OAR1_ADD2_Pos)                  /*!< 0x00000004 */
+#define I2C_OAR1_ADD2             I2C_OAR1_ADD2_Msk                            /*!<Bit 2 */
+#define I2C_OAR1_ADD3_Pos         (3U)                                         
+#define I2C_OAR1_ADD3_Msk         (0x1UL << I2C_OAR1_ADD3_Pos)                  /*!< 0x00000008 */
+#define I2C_OAR1_ADD3             I2C_OAR1_ADD3_Msk                            /*!<Bit 3 */
+#define I2C_OAR1_ADD4_Pos         (4U)                                         
+#define I2C_OAR1_ADD4_Msk         (0x1UL << I2C_OAR1_ADD4_Pos)                  /*!< 0x00000010 */
+#define I2C_OAR1_ADD4             I2C_OAR1_ADD4_Msk                            /*!<Bit 4 */
+#define I2C_OAR1_ADD5_Pos         (5U)                                         
+#define I2C_OAR1_ADD5_Msk         (0x1UL << I2C_OAR1_ADD5_Pos)                  /*!< 0x00000020 */
+#define I2C_OAR1_ADD5             I2C_OAR1_ADD5_Msk                            /*!<Bit 5 */
+#define I2C_OAR1_ADD6_Pos         (6U)                                         
+#define I2C_OAR1_ADD6_Msk         (0x1UL << I2C_OAR1_ADD6_Pos)                  /*!< 0x00000040 */
+#define I2C_OAR1_ADD6             I2C_OAR1_ADD6_Msk                            /*!<Bit 6 */
+#define I2C_OAR1_ADD7_Pos         (7U)                                         
+#define I2C_OAR1_ADD7_Msk         (0x1UL << I2C_OAR1_ADD7_Pos)                  /*!< 0x00000080 */
+#define I2C_OAR1_ADD7             I2C_OAR1_ADD7_Msk                            /*!<Bit 7 */
+#define I2C_OAR1_ADD8_Pos         (8U)                                         
+#define I2C_OAR1_ADD8_Msk         (0x1UL << I2C_OAR1_ADD8_Pos)                  /*!< 0x00000100 */
+#define I2C_OAR1_ADD8             I2C_OAR1_ADD8_Msk                            /*!<Bit 8 */
+#define I2C_OAR1_ADD9_Pos         (9U)                                         
+#define I2C_OAR1_ADD9_Msk         (0x1UL << I2C_OAR1_ADD9_Pos)                  /*!< 0x00000200 */
+#define I2C_OAR1_ADD9             I2C_OAR1_ADD9_Msk                            /*!<Bit 9 */
+
+#define I2C_OAR1_ADDMODE_Pos      (15U)                                        
+#define I2C_OAR1_ADDMODE_Msk      (0x1UL << I2C_OAR1_ADDMODE_Pos)               /*!< 0x00008000 */
+#define I2C_OAR1_ADDMODE          I2C_OAR1_ADDMODE_Msk                         /*!<Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OAR2 register  *******************/
+#define I2C_OAR2_ENDUAL_Pos       (0U)                                         
+#define I2C_OAR2_ENDUAL_Msk       (0x1UL << I2C_OAR2_ENDUAL_Pos)                /*!< 0x00000001 */
+#define I2C_OAR2_ENDUAL           I2C_OAR2_ENDUAL_Msk                          /*!<Dual addressing mode enable */
+#define I2C_OAR2_ADD2_Pos         (1U)                                         
+#define I2C_OAR2_ADD2_Msk         (0x7FUL << I2C_OAR2_ADD2_Pos)                 /*!< 0x000000FE */
+#define I2C_OAR2_ADD2             I2C_OAR2_ADD2_Msk                            /*!<Interface address           */
+
+/********************  Bit definition for I2C_DR register  ********************/
+#define I2C_DR_DR_Pos             (0U)                                         
+#define I2C_DR_DR_Msk             (0xFFUL << I2C_DR_DR_Pos)                     /*!< 0x000000FF */
+#define I2C_DR_DR                 I2C_DR_DR_Msk                                /*!<8-bit Data Register         */
+
+/*******************  Bit definition for I2C_SR1 register  ********************/
+#define I2C_SR1_SB_Pos            (0U)                                         
+#define I2C_SR1_SB_Msk            (0x1UL << I2C_SR1_SB_Pos)                     /*!< 0x00000001 */
+#define I2C_SR1_SB                I2C_SR1_SB_Msk                               /*!<Start Bit (Master mode)                         */
+#define I2C_SR1_ADDR_Pos          (1U)                                         
+#define I2C_SR1_ADDR_Msk          (0x1UL << I2C_SR1_ADDR_Pos)                   /*!< 0x00000002 */
+#define I2C_SR1_ADDR              I2C_SR1_ADDR_Msk                             /*!<Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_BTF_Pos           (2U)                                         
+#define I2C_SR1_BTF_Msk           (0x1UL << I2C_SR1_BTF_Pos)                    /*!< 0x00000004 */
+#define I2C_SR1_BTF               I2C_SR1_BTF_Msk                              /*!<Byte Transfer Finished                          */
+#define I2C_SR1_ADD10_Pos         (3U)                                         
+#define I2C_SR1_ADD10_Msk         (0x1UL << I2C_SR1_ADD10_Pos)                  /*!< 0x00000008 */
+#define I2C_SR1_ADD10             I2C_SR1_ADD10_Msk                            /*!<10-bit header sent (Master mode)                */
+#define I2C_SR1_STOPF_Pos         (4U)                                         
+#define I2C_SR1_STOPF_Msk         (0x1UL << I2C_SR1_STOPF_Pos)                  /*!< 0x00000010 */
+#define I2C_SR1_STOPF             I2C_SR1_STOPF_Msk                            /*!<Stop detection (Slave mode)                     */
+#define I2C_SR1_RXNE_Pos          (6U)                                         
+#define I2C_SR1_RXNE_Msk          (0x1UL << I2C_SR1_RXNE_Pos)                   /*!< 0x00000040 */
+#define I2C_SR1_RXNE              I2C_SR1_RXNE_Msk                             /*!<Data Register not Empty (receivers)             */
+#define I2C_SR1_TXE_Pos           (7U)                                         
+#define I2C_SR1_TXE_Msk           (0x1UL << I2C_SR1_TXE_Pos)                    /*!< 0x00000080 */
+#define I2C_SR1_TXE               I2C_SR1_TXE_Msk                              /*!<Data Register Empty (transmitters)              */
+#define I2C_SR1_BERR_Pos          (8U)                                         
+#define I2C_SR1_BERR_Msk          (0x1UL << I2C_SR1_BERR_Pos)                   /*!< 0x00000100 */
+#define I2C_SR1_BERR              I2C_SR1_BERR_Msk                             /*!<Bus Error                                       */
+#define I2C_SR1_ARLO_Pos          (9U)                                         
+#define I2C_SR1_ARLO_Msk          (0x1UL << I2C_SR1_ARLO_Pos)                   /*!< 0x00000200 */
+#define I2C_SR1_ARLO              I2C_SR1_ARLO_Msk                             /*!<Arbitration Lost (master mode)                  */
+#define I2C_SR1_AF_Pos            (10U)                                        
+#define I2C_SR1_AF_Msk            (0x1UL << I2C_SR1_AF_Pos)                     /*!< 0x00000400 */
+#define I2C_SR1_AF                I2C_SR1_AF_Msk                               /*!<Acknowledge Failure                             */
+#define I2C_SR1_OVR_Pos           (11U)                                        
+#define I2C_SR1_OVR_Msk           (0x1UL << I2C_SR1_OVR_Pos)                    /*!< 0x00000800 */
+#define I2C_SR1_OVR               I2C_SR1_OVR_Msk                              /*!<Overrun/Underrun                                */
+#define I2C_SR1_PECERR_Pos        (12U)                                        
+#define I2C_SR1_PECERR_Msk        (0x1UL << I2C_SR1_PECERR_Pos)                 /*!< 0x00001000 */
+#define I2C_SR1_PECERR            I2C_SR1_PECERR_Msk                           /*!<PEC Error in reception                          */
+#define I2C_SR1_TIMEOUT_Pos       (14U)                                        
+#define I2C_SR1_TIMEOUT_Msk       (0x1UL << I2C_SR1_TIMEOUT_Pos)                /*!< 0x00004000 */
+#define I2C_SR1_TIMEOUT           I2C_SR1_TIMEOUT_Msk                          /*!<Timeout or Tlow Error                           */
+#define I2C_SR1_SMBALERT_Pos      (15U)                                        
+#define I2C_SR1_SMBALERT_Msk      (0x1UL << I2C_SR1_SMBALERT_Pos)               /*!< 0x00008000 */
+#define I2C_SR1_SMBALERT          I2C_SR1_SMBALERT_Msk                         /*!<SMBus Alert                                     */
+
+/*******************  Bit definition for I2C_SR2 register  ********************/
+#define I2C_SR2_MSL_Pos           (0U)                                         
+#define I2C_SR2_MSL_Msk           (0x1UL << I2C_SR2_MSL_Pos)                    /*!< 0x00000001 */
+#define I2C_SR2_MSL               I2C_SR2_MSL_Msk                              /*!<Master/Slave                                    */
+#define I2C_SR2_BUSY_Pos          (1U)                                         
+#define I2C_SR2_BUSY_Msk          (0x1UL << I2C_SR2_BUSY_Pos)                   /*!< 0x00000002 */
+#define I2C_SR2_BUSY              I2C_SR2_BUSY_Msk                             /*!<Bus Busy                                        */
+#define I2C_SR2_TRA_Pos           (2U)                                         
+#define I2C_SR2_TRA_Msk           (0x1UL << I2C_SR2_TRA_Pos)                    /*!< 0x00000004 */
+#define I2C_SR2_TRA               I2C_SR2_TRA_Msk                              /*!<Transmitter/Receiver                            */
+#define I2C_SR2_GENCALL_Pos       (4U)                                         
+#define I2C_SR2_GENCALL_Msk       (0x1UL << I2C_SR2_GENCALL_Pos)                /*!< 0x00000010 */
+#define I2C_SR2_GENCALL           I2C_SR2_GENCALL_Msk                          /*!<General Call Address (Slave mode)               */
+#define I2C_SR2_SMBDEFAULT_Pos    (5U)                                         
+#define I2C_SR2_SMBDEFAULT_Msk    (0x1UL << I2C_SR2_SMBDEFAULT_Pos)             /*!< 0x00000020 */
+#define I2C_SR2_SMBDEFAULT        I2C_SR2_SMBDEFAULT_Msk                       /*!<SMBus Device Default Address (Slave mode)       */
+#define I2C_SR2_SMBHOST_Pos       (6U)                                         
+#define I2C_SR2_SMBHOST_Msk       (0x1UL << I2C_SR2_SMBHOST_Pos)                /*!< 0x00000040 */
+#define I2C_SR2_SMBHOST           I2C_SR2_SMBHOST_Msk                          /*!<SMBus Host Header (Slave mode)                  */
+#define I2C_SR2_DUALF_Pos         (7U)                                         
+#define I2C_SR2_DUALF_Msk         (0x1UL << I2C_SR2_DUALF_Pos)                  /*!< 0x00000080 */
+#define I2C_SR2_DUALF             I2C_SR2_DUALF_Msk                            /*!<Dual Flag (Slave mode)                          */
+#define I2C_SR2_PEC_Pos           (8U)                                         
+#define I2C_SR2_PEC_Msk           (0xFFUL << I2C_SR2_PEC_Pos)                   /*!< 0x0000FF00 */
+#define I2C_SR2_PEC               I2C_SR2_PEC_Msk                              /*!<Packet Error Checking Register                  */
+
+/*******************  Bit definition for I2C_CCR register  ********************/
+#define I2C_CCR_CCR_Pos           (0U)                                         
+#define I2C_CCR_CCR_Msk           (0xFFFUL << I2C_CCR_CCR_Pos)                  /*!< 0x00000FFF */
+#define I2C_CCR_CCR               I2C_CCR_CCR_Msk                              /*!<Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CCR_DUTY_Pos          (14U)                                        
+#define I2C_CCR_DUTY_Msk          (0x1UL << I2C_CCR_DUTY_Pos)                   /*!< 0x00004000 */
+#define I2C_CCR_DUTY              I2C_CCR_DUTY_Msk                             /*!<Fast Mode Duty Cycle                                       */
+#define I2C_CCR_FS_Pos            (15U)                                        
+#define I2C_CCR_FS_Msk            (0x1UL << I2C_CCR_FS_Pos)                     /*!< 0x00008000 */
+#define I2C_CCR_FS                I2C_CCR_FS_Msk                               /*!<I2C Master Mode Selection                                  */
+
+/******************  Bit definition for I2C_TRISE register  *******************/
+#define I2C_TRISE_TRISE_Pos       (0U)                                         
+#define I2C_TRISE_TRISE_Msk       (0x3FUL << I2C_TRISE_TRISE_Pos)               /*!< 0x0000003F */
+#define I2C_TRISE_TRISE           I2C_TRISE_TRISE_Msk                          /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Independent WATCHDOG                             */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for IWDG_KR register  ********************/
+#define IWDG_KR_KEY_Pos     (0U)                                               
+#define IWDG_KR_KEY_Msk     (0xFFFFUL << IWDG_KR_KEY_Pos)                       /*!< 0x0000FFFF */
+#define IWDG_KR_KEY         IWDG_KR_KEY_Msk                                    /*!<Key value (write only, read 0000h)  */
+
+/*******************  Bit definition for IWDG_PR register  ********************/
+#define IWDG_PR_PR_Pos      (0U)                                               
+#define IWDG_PR_PR_Msk      (0x7UL << IWDG_PR_PR_Pos)                           /*!< 0x00000007 */
+#define IWDG_PR_PR          IWDG_PR_PR_Msk                                     /*!<PR[2:0] (Prescaler divider)         */
+#define IWDG_PR_PR_0        (0x1UL << IWDG_PR_PR_Pos)                           /*!< 0x01 */
+#define IWDG_PR_PR_1        (0x2UL << IWDG_PR_PR_Pos)                           /*!< 0x02 */
+#define IWDG_PR_PR_2        (0x4UL << IWDG_PR_PR_Pos)                           /*!< 0x04 */
+
+/*******************  Bit definition for IWDG_RLR register  *******************/
+#define IWDG_RLR_RL_Pos     (0U)                                               
+#define IWDG_RLR_RL_Msk     (0xFFFUL << IWDG_RLR_RL_Pos)                        /*!< 0x00000FFF */
+#define IWDG_RLR_RL         IWDG_RLR_RL_Msk                                    /*!<Watchdog counter reload value        */
+
+/*******************  Bit definition for IWDG_SR register  ********************/
+#define IWDG_SR_PVU_Pos     (0U)                                               
+#define IWDG_SR_PVU_Msk     (0x1UL << IWDG_SR_PVU_Pos)                          /*!< 0x00000001 */
+#define IWDG_SR_PVU         IWDG_SR_PVU_Msk                                    /*!<Watchdog prescaler value update      */
+#define IWDG_SR_RVU_Pos     (1U)                                               
+#define IWDG_SR_RVU_Msk     (0x1UL << IWDG_SR_RVU_Pos)                          /*!< 0x00000002 */
+#define IWDG_SR_RVU         IWDG_SR_RVU_Msk                                    /*!<Watchdog counter reload value update */
+
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                             Power Control                                  */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for PWR_CR register  ********************/
+#define PWR_CR_LPDS_Pos        (0U)                                            
+#define PWR_CR_LPDS_Msk        (0x1UL << PWR_CR_LPDS_Pos)                       /*!< 0x00000001 */
+#define PWR_CR_LPDS            PWR_CR_LPDS_Msk                                 /*!< Low-Power Deepsleep                 */
+#define PWR_CR_PDDS_Pos        (1U)                                            
+#define PWR_CR_PDDS_Msk        (0x1UL << PWR_CR_PDDS_Pos)                       /*!< 0x00000002 */
+#define PWR_CR_PDDS            PWR_CR_PDDS_Msk                                 /*!< Power Down Deepsleep                */
+#define PWR_CR_CWUF_Pos        (2U)                                            
+#define PWR_CR_CWUF_Msk        (0x1UL << PWR_CR_CWUF_Pos)                       /*!< 0x00000004 */
+#define PWR_CR_CWUF            PWR_CR_CWUF_Msk                                 /*!< Clear Wakeup Flag                   */
+#define PWR_CR_CSBF_Pos        (3U)                                            
+#define PWR_CR_CSBF_Msk        (0x1UL << PWR_CR_CSBF_Pos)                       /*!< 0x00000008 */
+#define PWR_CR_CSBF            PWR_CR_CSBF_Msk                                 /*!< Clear Standby Flag                  */
+#define PWR_CR_PVDE_Pos        (4U)                                            
+#define PWR_CR_PVDE_Msk        (0x1UL << PWR_CR_PVDE_Pos)                       /*!< 0x00000010 */
+#define PWR_CR_PVDE            PWR_CR_PVDE_Msk                                 /*!< Power Voltage Detector Enable       */
+
+#define PWR_CR_PLS_Pos         (5U)                                            
+#define PWR_CR_PLS_Msk         (0x7UL << PWR_CR_PLS_Pos)                        /*!< 0x000000E0 */
+#define PWR_CR_PLS             PWR_CR_PLS_Msk                                  /*!< PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CR_PLS_0           (0x1UL << PWR_CR_PLS_Pos)                        /*!< 0x00000020 */
+#define PWR_CR_PLS_1           (0x2UL << PWR_CR_PLS_Pos)                        /*!< 0x00000040 */
+#define PWR_CR_PLS_2           (0x4UL << PWR_CR_PLS_Pos)                        /*!< 0x00000080 */
+
+/*!< PVD level configuration */
+#define PWR_CR_PLS_LEV0        0x00000000U                                     /*!< PVD level 0 */
+#define PWR_CR_PLS_LEV1        0x00000020U                                     /*!< PVD level 1 */
+#define PWR_CR_PLS_LEV2        0x00000040U                                     /*!< PVD level 2 */
+#define PWR_CR_PLS_LEV3        0x00000060U                                     /*!< PVD level 3 */
+#define PWR_CR_PLS_LEV4        0x00000080U                                     /*!< PVD level 4 */
+#define PWR_CR_PLS_LEV5        0x000000A0U                                     /*!< PVD level 5 */
+#define PWR_CR_PLS_LEV6        0x000000C0U                                     /*!< PVD level 6 */
+#define PWR_CR_PLS_LEV7        0x000000E0U                                     /*!< PVD level 7 */
+#define PWR_CR_DBP_Pos         (8U)                                            
+#define PWR_CR_DBP_Msk         (0x1UL << PWR_CR_DBP_Pos)                        /*!< 0x00000100 */
+#define PWR_CR_DBP             PWR_CR_DBP_Msk                                  /*!< Disable Backup Domain write protection                     */
+#define PWR_CR_FPDS_Pos        (9U)                                            
+#define PWR_CR_FPDS_Msk        (0x1UL << PWR_CR_FPDS_Pos)                       /*!< 0x00000200 */
+#define PWR_CR_FPDS            PWR_CR_FPDS_Msk                                 /*!< Flash power down in Stop mode                              */
+#define PWR_CR_VOS_Pos         (14U)                                           
+#define PWR_CR_VOS_Msk         (0x1UL << PWR_CR_VOS_Pos)                        /*!< 0x00004000 */
+#define PWR_CR_VOS             PWR_CR_VOS_Msk                                  /*!< VOS bit (Regulator voltage scaling output selection) */
+
+/* Legacy define */
+#define  PWR_CR_PMODE                        PWR_CR_VOS
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define PWR_CSR_WUF_Pos        (0U)                                            
+#define PWR_CSR_WUF_Msk        (0x1UL << PWR_CSR_WUF_Pos)                       /*!< 0x00000001 */
+#define PWR_CSR_WUF            PWR_CSR_WUF_Msk                                 /*!< Wakeup Flag                                      */
+#define PWR_CSR_SBF_Pos        (1U)                                            
+#define PWR_CSR_SBF_Msk        (0x1UL << PWR_CSR_SBF_Pos)                       /*!< 0x00000002 */
+#define PWR_CSR_SBF            PWR_CSR_SBF_Msk                                 /*!< Standby Flag                                     */
+#define PWR_CSR_PVDO_Pos       (2U)                                            
+#define PWR_CSR_PVDO_Msk       (0x1UL << PWR_CSR_PVDO_Pos)                      /*!< 0x00000004 */
+#define PWR_CSR_PVDO           PWR_CSR_PVDO_Msk                                /*!< PVD Output                                       */
+#define PWR_CSR_BRR_Pos        (3U)                                            
+#define PWR_CSR_BRR_Msk        (0x1UL << PWR_CSR_BRR_Pos)                       /*!< 0x00000008 */
+#define PWR_CSR_BRR            PWR_CSR_BRR_Msk                                 /*!< Backup regulator ready                           */
+#define PWR_CSR_EWUP_Pos       (8U)                                            
+#define PWR_CSR_EWUP_Msk       (0x1UL << PWR_CSR_EWUP_Pos)                      /*!< 0x00000100 */
+#define PWR_CSR_EWUP           PWR_CSR_EWUP_Msk                                /*!< Enable WKUP pin                                  */
+#define PWR_CSR_BRE_Pos        (9U)                                            
+#define PWR_CSR_BRE_Msk        (0x1UL << PWR_CSR_BRE_Pos)                       /*!< 0x00000200 */
+#define PWR_CSR_BRE            PWR_CSR_BRE_Msk                                 /*!< Backup regulator enable                          */
+#define PWR_CSR_VOSRDY_Pos     (14U)                                           
+#define PWR_CSR_VOSRDY_Msk     (0x1UL << PWR_CSR_VOSRDY_Pos)                    /*!< 0x00004000 */
+#define PWR_CSR_VOSRDY         PWR_CSR_VOSRDY_Msk                              /*!< Regulator voltage scaling output selection ready */
+
+/* Legacy define */
+#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY
+
+/******************************************************************************/
+/*                                                                            */
+/*                         Reset and Clock Control                            */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for RCC_CR register  ********************/
+#define RCC_CR_HSION_Pos                   (0U)                                
+#define RCC_CR_HSION_Msk                   (0x1UL << RCC_CR_HSION_Pos)          /*!< 0x00000001 */
+#define RCC_CR_HSION                       RCC_CR_HSION_Msk                    
+#define RCC_CR_HSIRDY_Pos                  (1U)                                
+#define RCC_CR_HSIRDY_Msk                  (0x1UL << RCC_CR_HSIRDY_Pos)         /*!< 0x00000002 */
+#define RCC_CR_HSIRDY                      RCC_CR_HSIRDY_Msk                   
+
+#define RCC_CR_HSITRIM_Pos                 (3U)                                
+#define RCC_CR_HSITRIM_Msk                 (0x1FUL << RCC_CR_HSITRIM_Pos)       /*!< 0x000000F8 */
+#define RCC_CR_HSITRIM                     RCC_CR_HSITRIM_Msk                  
+#define RCC_CR_HSITRIM_0                   (0x01UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000008 */
+#define RCC_CR_HSITRIM_1                   (0x02UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000010 */
+#define RCC_CR_HSITRIM_2                   (0x04UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000020 */
+#define RCC_CR_HSITRIM_3                   (0x08UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000040 */
+#define RCC_CR_HSITRIM_4                   (0x10UL << RCC_CR_HSITRIM_Pos)       /*!< 0x00000080 */
+
+#define RCC_CR_HSICAL_Pos                  (8U)                                
+#define RCC_CR_HSICAL_Msk                  (0xFFUL << RCC_CR_HSICAL_Pos)        /*!< 0x0000FF00 */
+#define RCC_CR_HSICAL                      RCC_CR_HSICAL_Msk                   
+#define RCC_CR_HSICAL_0                    (0x01UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000100 */
+#define RCC_CR_HSICAL_1                    (0x02UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000200 */
+#define RCC_CR_HSICAL_2                    (0x04UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000400 */
+#define RCC_CR_HSICAL_3                    (0x08UL << RCC_CR_HSICAL_Pos)        /*!< 0x00000800 */
+#define RCC_CR_HSICAL_4                    (0x10UL << RCC_CR_HSICAL_Pos)        /*!< 0x00001000 */
+#define RCC_CR_HSICAL_5                    (0x20UL << RCC_CR_HSICAL_Pos)        /*!< 0x00002000 */
+#define RCC_CR_HSICAL_6                    (0x40UL << RCC_CR_HSICAL_Pos)        /*!< 0x00004000 */
+#define RCC_CR_HSICAL_7                    (0x80UL << RCC_CR_HSICAL_Pos)        /*!< 0x00008000 */
+
+#define RCC_CR_HSEON_Pos                   (16U)                               
+#define RCC_CR_HSEON_Msk                   (0x1UL << RCC_CR_HSEON_Pos)          /*!< 0x00010000 */
+#define RCC_CR_HSEON                       RCC_CR_HSEON_Msk                    
+#define RCC_CR_HSERDY_Pos                  (17U)                               
+#define RCC_CR_HSERDY_Msk                  (0x1UL << RCC_CR_HSERDY_Pos)         /*!< 0x00020000 */
+#define RCC_CR_HSERDY                      RCC_CR_HSERDY_Msk                   
+#define RCC_CR_HSEBYP_Pos                  (18U)                               
+#define RCC_CR_HSEBYP_Msk                  (0x1UL << RCC_CR_HSEBYP_Pos)         /*!< 0x00040000 */
+#define RCC_CR_HSEBYP                      RCC_CR_HSEBYP_Msk                   
+#define RCC_CR_CSSON_Pos                   (19U)                               
+#define RCC_CR_CSSON_Msk                   (0x1UL << RCC_CR_CSSON_Pos)          /*!< 0x00080000 */
+#define RCC_CR_CSSON                       RCC_CR_CSSON_Msk                    
+#define RCC_CR_PLLON_Pos                   (24U)                               
+#define RCC_CR_PLLON_Msk                   (0x1UL << RCC_CR_PLLON_Pos)          /*!< 0x01000000 */
+#define RCC_CR_PLLON                       RCC_CR_PLLON_Msk                    
+#define RCC_CR_PLLRDY_Pos                  (25U)                               
+#define RCC_CR_PLLRDY_Msk                  (0x1UL << RCC_CR_PLLRDY_Pos)         /*!< 0x02000000 */
+#define RCC_CR_PLLRDY                      RCC_CR_PLLRDY_Msk                   
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_PLLI2S_SUPPORT                                                     /*!< Support PLLI2S oscillator */
+
+#define RCC_CR_PLLI2SON_Pos                (26U)                               
+#define RCC_CR_PLLI2SON_Msk                (0x1UL << RCC_CR_PLLI2SON_Pos)       /*!< 0x04000000 */
+#define RCC_CR_PLLI2SON                    RCC_CR_PLLI2SON_Msk                 
+#define RCC_CR_PLLI2SRDY_Pos               (27U)                               
+#define RCC_CR_PLLI2SRDY_Msk               (0x1UL << RCC_CR_PLLI2SRDY_Pos)      /*!< 0x08000000 */
+#define RCC_CR_PLLI2SRDY                   RCC_CR_PLLI2SRDY_Msk                
+
+/********************  Bit definition for RCC_PLLCFGR register  ***************/
+#define RCC_PLLCFGR_PLLM_Pos               (0U)                                
+#define RCC_PLLCFGR_PLLM_Msk               (0x3FUL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x0000003F */
+#define RCC_PLLCFGR_PLLM                   RCC_PLLCFGR_PLLM_Msk                
+#define RCC_PLLCFGR_PLLM_0                 (0x01UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000001 */
+#define RCC_PLLCFGR_PLLM_1                 (0x02UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000002 */
+#define RCC_PLLCFGR_PLLM_2                 (0x04UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000004 */
+#define RCC_PLLCFGR_PLLM_3                 (0x08UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000008 */
+#define RCC_PLLCFGR_PLLM_4                 (0x10UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000010 */
+#define RCC_PLLCFGR_PLLM_5                 (0x20UL << RCC_PLLCFGR_PLLM_Pos)     /*!< 0x00000020 */
+
+#define RCC_PLLCFGR_PLLN_Pos               (6U)                                
+#define RCC_PLLCFGR_PLLN_Msk               (0x1FFUL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00007FC0 */
+#define RCC_PLLCFGR_PLLN                   RCC_PLLCFGR_PLLN_Msk                
+#define RCC_PLLCFGR_PLLN_0                 (0x001UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000040 */
+#define RCC_PLLCFGR_PLLN_1                 (0x002UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000080 */
+#define RCC_PLLCFGR_PLLN_2                 (0x004UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000100 */
+#define RCC_PLLCFGR_PLLN_3                 (0x008UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000200 */
+#define RCC_PLLCFGR_PLLN_4                 (0x010UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000400 */
+#define RCC_PLLCFGR_PLLN_5                 (0x020UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00000800 */
+#define RCC_PLLCFGR_PLLN_6                 (0x040UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00001000 */
+#define RCC_PLLCFGR_PLLN_7                 (0x080UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00002000 */
+#define RCC_PLLCFGR_PLLN_8                 (0x100UL << RCC_PLLCFGR_PLLN_Pos)    /*!< 0x00004000 */
+
+#define RCC_PLLCFGR_PLLP_Pos               (16U)                               
+#define RCC_PLLCFGR_PLLP_Msk               (0x3UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00030000 */
+#define RCC_PLLCFGR_PLLP                   RCC_PLLCFGR_PLLP_Msk                
+#define RCC_PLLCFGR_PLLP_0                 (0x1UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00010000 */
+#define RCC_PLLCFGR_PLLP_1                 (0x2UL << RCC_PLLCFGR_PLLP_Pos)      /*!< 0x00020000 */
+
+#define RCC_PLLCFGR_PLLSRC_Pos             (22U)                               
+#define RCC_PLLCFGR_PLLSRC_Msk             (0x1UL << RCC_PLLCFGR_PLLSRC_Pos)    /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC                 RCC_PLLCFGR_PLLSRC_Msk              
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos         (22U)                               
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk         (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */
+#define RCC_PLLCFGR_PLLSRC_HSE             RCC_PLLCFGR_PLLSRC_HSE_Msk          
+#define RCC_PLLCFGR_PLLSRC_HSI             0x00000000U                         
+
+#define RCC_PLLCFGR_PLLQ_Pos               (24U)                               
+#define RCC_PLLCFGR_PLLQ_Msk               (0xFUL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x0F000000 */
+#define RCC_PLLCFGR_PLLQ                   RCC_PLLCFGR_PLLQ_Msk                
+#define RCC_PLLCFGR_PLLQ_0                 (0x1UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x01000000 */
+#define RCC_PLLCFGR_PLLQ_1                 (0x2UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x02000000 */
+#define RCC_PLLCFGR_PLLQ_2                 (0x4UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x04000000 */
+#define RCC_PLLCFGR_PLLQ_3                 (0x8UL << RCC_PLLCFGR_PLLQ_Pos)      /*!< 0x08000000 */
+
+
+/********************  Bit definition for RCC_CFGR register  ******************/
+/*!< SW configuration */
+#define RCC_CFGR_SW_Pos                    (0U)                                
+#define RCC_CFGR_SW_Msk                    (0x3UL << RCC_CFGR_SW_Pos)           /*!< 0x00000003 */
+#define RCC_CFGR_SW                        RCC_CFGR_SW_Msk                     /*!< SW[1:0] bits (System clock Switch) */
+#define RCC_CFGR_SW_0                      (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */
+#define RCC_CFGR_SW_1                      (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */
+
+#define RCC_CFGR_SW_HSI                    0x00000000U                         /*!< HSI selected as system clock */
+#define RCC_CFGR_SW_HSE                    0x00000001U                         /*!< HSE selected as system clock */
+#define RCC_CFGR_SW_PLL                    0x00000002U                         /*!< PLL selected as system clock */
+
+/*!< SWS configuration */
+#define RCC_CFGR_SWS_Pos                   (2U)                                
+#define RCC_CFGR_SWS_Msk                   (0x3UL << RCC_CFGR_SWS_Pos)          /*!< 0x0000000C */
+#define RCC_CFGR_SWS                       RCC_CFGR_SWS_Msk                    /*!< SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_CFGR_SWS_0                     (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000004 */
+#define RCC_CFGR_SWS_1                     (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */
+
+#define RCC_CFGR_SWS_HSI                   0x00000000U                         /*!< HSI oscillator used as system clock        */
+#define RCC_CFGR_SWS_HSE                   0x00000004U                         /*!< HSE oscillator used as system clock        */
+#define RCC_CFGR_SWS_PLL                   0x00000008U                         /*!< PLL used as system clock                   */
+
+/*!< HPRE configuration */
+#define RCC_CFGR_HPRE_Pos                  (4U)                                
+#define RCC_CFGR_HPRE_Msk                  (0xFUL << RCC_CFGR_HPRE_Pos)         /*!< 0x000000F0 */
+#define RCC_CFGR_HPRE                      RCC_CFGR_HPRE_Msk                   /*!< HPRE[3:0] bits (AHB prescaler) */
+#define RCC_CFGR_HPRE_0                    (0x1UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000010 */
+#define RCC_CFGR_HPRE_1                    (0x2UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000020 */
+#define RCC_CFGR_HPRE_2                    (0x4UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000040 */
+#define RCC_CFGR_HPRE_3                    (0x8UL << RCC_CFGR_HPRE_Pos)         /*!< 0x00000080 */
+
+#define RCC_CFGR_HPRE_DIV1                 0x00000000U                         /*!< SYSCLK not divided    */
+#define RCC_CFGR_HPRE_DIV2                 0x00000080U                         /*!< SYSCLK divided by 2   */
+#define RCC_CFGR_HPRE_DIV4                 0x00000090U                         /*!< SYSCLK divided by 4   */
+#define RCC_CFGR_HPRE_DIV8                 0x000000A0U                         /*!< SYSCLK divided by 8   */
+#define RCC_CFGR_HPRE_DIV16                0x000000B0U                         /*!< SYSCLK divided by 16  */
+#define RCC_CFGR_HPRE_DIV64                0x000000C0U                         /*!< SYSCLK divided by 64  */
+#define RCC_CFGR_HPRE_DIV128               0x000000D0U                         /*!< SYSCLK divided by 128 */
+#define RCC_CFGR_HPRE_DIV256               0x000000E0U                         /*!< SYSCLK divided by 256 */
+#define RCC_CFGR_HPRE_DIV512               0x000000F0U                         /*!< SYSCLK divided by 512 */
+
+/*!< PPRE1 configuration */
+#define RCC_CFGR_PPRE1_Pos                 (10U)                               
+#define RCC_CFGR_PPRE1_Msk                 (0x7UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001C00 */
+#define RCC_CFGR_PPRE1                     RCC_CFGR_PPRE1_Msk                  /*!< PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_CFGR_PPRE1_0                   (0x1UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000400 */
+#define RCC_CFGR_PPRE1_1                   (0x2UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00000800 */
+#define RCC_CFGR_PPRE1_2                   (0x4UL << RCC_CFGR_PPRE1_Pos)        /*!< 0x00001000 */
+
+#define RCC_CFGR_PPRE1_DIV1                0x00000000U                         /*!< HCLK not divided   */
+#define RCC_CFGR_PPRE1_DIV2                0x00001000U                         /*!< HCLK divided by 2  */
+#define RCC_CFGR_PPRE1_DIV4                0x00001400U                         /*!< HCLK divided by 4  */
+#define RCC_CFGR_PPRE1_DIV8                0x00001800U                         /*!< HCLK divided by 8  */
+#define RCC_CFGR_PPRE1_DIV16               0x00001C00U                         /*!< HCLK divided by 16 */
+
+/*!< PPRE2 configuration */
+#define RCC_CFGR_PPRE2_Pos                 (13U)                               
+#define RCC_CFGR_PPRE2_Msk                 (0x7UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x0000E000 */
+#define RCC_CFGR_PPRE2                     RCC_CFGR_PPRE2_Msk                  /*!< PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_CFGR_PPRE2_0                   (0x1UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00002000 */
+#define RCC_CFGR_PPRE2_1                   (0x2UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00004000 */
+#define RCC_CFGR_PPRE2_2                   (0x4UL << RCC_CFGR_PPRE2_Pos)        /*!< 0x00008000 */
+
+#define RCC_CFGR_PPRE2_DIV1                0x00000000U                         /*!< HCLK not divided   */
+#define RCC_CFGR_PPRE2_DIV2                0x00008000U                         /*!< HCLK divided by 2  */
+#define RCC_CFGR_PPRE2_DIV4                0x0000A000U                         /*!< HCLK divided by 4  */
+#define RCC_CFGR_PPRE2_DIV8                0x0000C000U                         /*!< HCLK divided by 8  */
+#define RCC_CFGR_PPRE2_DIV16               0x0000E000U                         /*!< HCLK divided by 16 */
+
+/*!< RTCPRE configuration */
+#define RCC_CFGR_RTCPRE_Pos                (16U)                               
+#define RCC_CFGR_RTCPRE_Msk                (0x1FUL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x001F0000 */
+#define RCC_CFGR_RTCPRE                    RCC_CFGR_RTCPRE_Msk                 
+#define RCC_CFGR_RTCPRE_0                  (0x01UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00010000 */
+#define RCC_CFGR_RTCPRE_1                  (0x02UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00020000 */
+#define RCC_CFGR_RTCPRE_2                  (0x04UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00040000 */
+#define RCC_CFGR_RTCPRE_3                  (0x08UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00080000 */
+#define RCC_CFGR_RTCPRE_4                  (0x10UL << RCC_CFGR_RTCPRE_Pos)      /*!< 0x00100000 */
+
+/*!< MCO1 configuration */
+#define RCC_CFGR_MCO1_Pos                  (21U)                               
+#define RCC_CFGR_MCO1_Msk                  (0x3UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00600000 */
+#define RCC_CFGR_MCO1                      RCC_CFGR_MCO1_Msk                   
+#define RCC_CFGR_MCO1_0                    (0x1UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00200000 */
+#define RCC_CFGR_MCO1_1                    (0x2UL << RCC_CFGR_MCO1_Pos)         /*!< 0x00400000 */
+
+#define RCC_CFGR_I2SSRC_Pos                (23U)                               
+#define RCC_CFGR_I2SSRC_Msk                (0x1UL << RCC_CFGR_I2SSRC_Pos)       /*!< 0x00800000 */
+#define RCC_CFGR_I2SSRC                    RCC_CFGR_I2SSRC_Msk                 
+
+#define RCC_CFGR_MCO1PRE_Pos               (24U)                               
+#define RCC_CFGR_MCO1PRE_Msk               (0x7UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x07000000 */
+#define RCC_CFGR_MCO1PRE                   RCC_CFGR_MCO1PRE_Msk                
+#define RCC_CFGR_MCO1PRE_0                 (0x1UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x01000000 */
+#define RCC_CFGR_MCO1PRE_1                 (0x2UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x02000000 */
+#define RCC_CFGR_MCO1PRE_2                 (0x4UL << RCC_CFGR_MCO1PRE_Pos)      /*!< 0x04000000 */
+
+#define RCC_CFGR_MCO2PRE_Pos               (27U)                               
+#define RCC_CFGR_MCO2PRE_Msk               (0x7UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x38000000 */
+#define RCC_CFGR_MCO2PRE                   RCC_CFGR_MCO2PRE_Msk                
+#define RCC_CFGR_MCO2PRE_0                 (0x1UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x08000000 */
+#define RCC_CFGR_MCO2PRE_1                 (0x2UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x10000000 */
+#define RCC_CFGR_MCO2PRE_2                 (0x4UL << RCC_CFGR_MCO2PRE_Pos)      /*!< 0x20000000 */
+
+#define RCC_CFGR_MCO2_Pos                  (30U)                               
+#define RCC_CFGR_MCO2_Msk                  (0x3UL << RCC_CFGR_MCO2_Pos)         /*!< 0xC0000000 */
+#define RCC_CFGR_MCO2                      RCC_CFGR_MCO2_Msk                   
+#define RCC_CFGR_MCO2_0                    (0x1UL << RCC_CFGR_MCO2_Pos)         /*!< 0x40000000 */
+#define RCC_CFGR_MCO2_1                    (0x2UL << RCC_CFGR_MCO2_Pos)         /*!< 0x80000000 */
+
+/********************  Bit definition for RCC_CIR register  *******************/
+#define RCC_CIR_LSIRDYF_Pos                (0U)                                
+#define RCC_CIR_LSIRDYF_Msk                (0x1UL << RCC_CIR_LSIRDYF_Pos)       /*!< 0x00000001 */
+#define RCC_CIR_LSIRDYF                    RCC_CIR_LSIRDYF_Msk                 
+#define RCC_CIR_LSERDYF_Pos                (1U)                                
+#define RCC_CIR_LSERDYF_Msk                (0x1UL << RCC_CIR_LSERDYF_Pos)       /*!< 0x00000002 */
+#define RCC_CIR_LSERDYF                    RCC_CIR_LSERDYF_Msk                 
+#define RCC_CIR_HSIRDYF_Pos                (2U)                                
+#define RCC_CIR_HSIRDYF_Msk                (0x1UL << RCC_CIR_HSIRDYF_Pos)       /*!< 0x00000004 */
+#define RCC_CIR_HSIRDYF                    RCC_CIR_HSIRDYF_Msk                 
+#define RCC_CIR_HSERDYF_Pos                (3U)                                
+#define RCC_CIR_HSERDYF_Msk                (0x1UL << RCC_CIR_HSERDYF_Pos)       /*!< 0x00000008 */
+#define RCC_CIR_HSERDYF                    RCC_CIR_HSERDYF_Msk                 
+#define RCC_CIR_PLLRDYF_Pos                (4U)                                
+#define RCC_CIR_PLLRDYF_Msk                (0x1UL << RCC_CIR_PLLRDYF_Pos)       /*!< 0x00000010 */
+#define RCC_CIR_PLLRDYF                    RCC_CIR_PLLRDYF_Msk                 
+#define RCC_CIR_PLLI2SRDYF_Pos             (5U)                                
+#define RCC_CIR_PLLI2SRDYF_Msk             (0x1UL << RCC_CIR_PLLI2SRDYF_Pos)    /*!< 0x00000020 */
+#define RCC_CIR_PLLI2SRDYF                 RCC_CIR_PLLI2SRDYF_Msk              
+
+#define RCC_CIR_CSSF_Pos                   (7U)                                
+#define RCC_CIR_CSSF_Msk                   (0x1UL << RCC_CIR_CSSF_Pos)          /*!< 0x00000080 */
+#define RCC_CIR_CSSF                       RCC_CIR_CSSF_Msk                    
+#define RCC_CIR_LSIRDYIE_Pos               (8U)                                
+#define RCC_CIR_LSIRDYIE_Msk               (0x1UL << RCC_CIR_LSIRDYIE_Pos)      /*!< 0x00000100 */
+#define RCC_CIR_LSIRDYIE                   RCC_CIR_LSIRDYIE_Msk                
+#define RCC_CIR_LSERDYIE_Pos               (9U)                                
+#define RCC_CIR_LSERDYIE_Msk               (0x1UL << RCC_CIR_LSERDYIE_Pos)      /*!< 0x00000200 */
+#define RCC_CIR_LSERDYIE                   RCC_CIR_LSERDYIE_Msk                
+#define RCC_CIR_HSIRDYIE_Pos               (10U)                               
+#define RCC_CIR_HSIRDYIE_Msk               (0x1UL << RCC_CIR_HSIRDYIE_Pos)      /*!< 0x00000400 */
+#define RCC_CIR_HSIRDYIE                   RCC_CIR_HSIRDYIE_Msk                
+#define RCC_CIR_HSERDYIE_Pos               (11U)                               
+#define RCC_CIR_HSERDYIE_Msk               (0x1UL << RCC_CIR_HSERDYIE_Pos)      /*!< 0x00000800 */
+#define RCC_CIR_HSERDYIE                   RCC_CIR_HSERDYIE_Msk                
+#define RCC_CIR_PLLRDYIE_Pos               (12U)                               
+#define RCC_CIR_PLLRDYIE_Msk               (0x1UL << RCC_CIR_PLLRDYIE_Pos)      /*!< 0x00001000 */
+#define RCC_CIR_PLLRDYIE                   RCC_CIR_PLLRDYIE_Msk                
+#define RCC_CIR_PLLI2SRDYIE_Pos            (13U)                               
+#define RCC_CIR_PLLI2SRDYIE_Msk            (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos)   /*!< 0x00002000 */
+#define RCC_CIR_PLLI2SRDYIE                RCC_CIR_PLLI2SRDYIE_Msk             
+
+#define RCC_CIR_LSIRDYC_Pos                (16U)                               
+#define RCC_CIR_LSIRDYC_Msk                (0x1UL << RCC_CIR_LSIRDYC_Pos)       /*!< 0x00010000 */
+#define RCC_CIR_LSIRDYC                    RCC_CIR_LSIRDYC_Msk                 
+#define RCC_CIR_LSERDYC_Pos                (17U)                               
+#define RCC_CIR_LSERDYC_Msk                (0x1UL << RCC_CIR_LSERDYC_Pos)       /*!< 0x00020000 */
+#define RCC_CIR_LSERDYC                    RCC_CIR_LSERDYC_Msk                 
+#define RCC_CIR_HSIRDYC_Pos                (18U)                               
+#define RCC_CIR_HSIRDYC_Msk                (0x1UL << RCC_CIR_HSIRDYC_Pos)       /*!< 0x00040000 */
+#define RCC_CIR_HSIRDYC                    RCC_CIR_HSIRDYC_Msk                 
+#define RCC_CIR_HSERDYC_Pos                (19U)                               
+#define RCC_CIR_HSERDYC_Msk                (0x1UL << RCC_CIR_HSERDYC_Pos)       /*!< 0x00080000 */
+#define RCC_CIR_HSERDYC                    RCC_CIR_HSERDYC_Msk                 
+#define RCC_CIR_PLLRDYC_Pos                (20U)                               
+#define RCC_CIR_PLLRDYC_Msk                (0x1UL << RCC_CIR_PLLRDYC_Pos)       /*!< 0x00100000 */
+#define RCC_CIR_PLLRDYC                    RCC_CIR_PLLRDYC_Msk                 
+#define RCC_CIR_PLLI2SRDYC_Pos             (21U)                               
+#define RCC_CIR_PLLI2SRDYC_Msk             (0x1UL << RCC_CIR_PLLI2SRDYC_Pos)    /*!< 0x00200000 */
+#define RCC_CIR_PLLI2SRDYC                 RCC_CIR_PLLI2SRDYC_Msk              
+
+#define RCC_CIR_CSSC_Pos                   (23U)                               
+#define RCC_CIR_CSSC_Msk                   (0x1UL << RCC_CIR_CSSC_Pos)          /*!< 0x00800000 */
+#define RCC_CIR_CSSC                       RCC_CIR_CSSC_Msk                    
+
+/********************  Bit definition for RCC_AHB1RSTR register  **************/
+#define RCC_AHB1RSTR_GPIOARST_Pos          (0U)                                
+#define RCC_AHB1RSTR_GPIOARST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */
+#define RCC_AHB1RSTR_GPIOARST              RCC_AHB1RSTR_GPIOARST_Msk           
+#define RCC_AHB1RSTR_GPIOBRST_Pos          (1U)                                
+#define RCC_AHB1RSTR_GPIOBRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
+#define RCC_AHB1RSTR_GPIOBRST              RCC_AHB1RSTR_GPIOBRST_Msk           
+#define RCC_AHB1RSTR_GPIOCRST_Pos          (2U)                                
+#define RCC_AHB1RSTR_GPIOCRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
+#define RCC_AHB1RSTR_GPIOCRST              RCC_AHB1RSTR_GPIOCRST_Msk           
+#define RCC_AHB1RSTR_GPIODRST_Pos          (3U)                                
+#define RCC_AHB1RSTR_GPIODRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */
+#define RCC_AHB1RSTR_GPIODRST              RCC_AHB1RSTR_GPIODRST_Msk           
+#define RCC_AHB1RSTR_GPIOERST_Pos          (4U)                                
+#define RCC_AHB1RSTR_GPIOERST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */
+#define RCC_AHB1RSTR_GPIOERST              RCC_AHB1RSTR_GPIOERST_Msk           
+#define RCC_AHB1RSTR_GPIOFRST_Pos          (5U)                                
+#define RCC_AHB1RSTR_GPIOFRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
+#define RCC_AHB1RSTR_GPIOFRST              RCC_AHB1RSTR_GPIOFRST_Msk           
+#define RCC_AHB1RSTR_GPIOGRST_Pos          (6U)                                
+#define RCC_AHB1RSTR_GPIOGRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
+#define RCC_AHB1RSTR_GPIOGRST              RCC_AHB1RSTR_GPIOGRST_Msk           
+#define RCC_AHB1RSTR_GPIOHRST_Pos          (7U)                                
+#define RCC_AHB1RSTR_GPIOHRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB1RSTR_GPIOHRST              RCC_AHB1RSTR_GPIOHRST_Msk           
+#define RCC_AHB1RSTR_GPIOIRST_Pos          (8U)                                
+#define RCC_AHB1RSTR_GPIOIRST_Msk          (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
+#define RCC_AHB1RSTR_GPIOIRST              RCC_AHB1RSTR_GPIOIRST_Msk           
+#define RCC_AHB1RSTR_CRCRST_Pos            (12U)                               
+#define RCC_AHB1RSTR_CRCRST_Msk            (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)   /*!< 0x00001000 */
+#define RCC_AHB1RSTR_CRCRST                RCC_AHB1RSTR_CRCRST_Msk             
+#define RCC_AHB1RSTR_DMA1RST_Pos           (21U)                               
+#define RCC_AHB1RSTR_DMA1RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)  /*!< 0x00200000 */
+#define RCC_AHB1RSTR_DMA1RST               RCC_AHB1RSTR_DMA1RST_Msk            
+#define RCC_AHB1RSTR_DMA2RST_Pos           (22U)                               
+#define RCC_AHB1RSTR_DMA2RST_Msk           (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)  /*!< 0x00400000 */
+#define RCC_AHB1RSTR_DMA2RST               RCC_AHB1RSTR_DMA2RST_Msk            
+#define RCC_AHB1RSTR_ETHMACRST_Pos         (25U)                               
+#define RCC_AHB1RSTR_ETHMACRST_Msk         (0x1UL << RCC_AHB1RSTR_ETHMACRST_Pos) /*!< 0x02000000 */
+#define RCC_AHB1RSTR_ETHMACRST             RCC_AHB1RSTR_ETHMACRST_Msk          
+#define RCC_AHB1RSTR_OTGHRST_Pos           (29U)                               
+#define RCC_AHB1RSTR_OTGHRST_Msk           (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos)  /*!< 0x20000000 */
+#define RCC_AHB1RSTR_OTGHRST               RCC_AHB1RSTR_OTGHRST_Msk            
+
+/********************  Bit definition for RCC_AHB2RSTR register  **************/
+#define RCC_AHB2RSTR_DCMIRST_Pos           (0U)                                
+#define RCC_AHB2RSTR_DCMIRST_Msk           (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)  /*!< 0x00000001 */
+#define RCC_AHB2RSTR_DCMIRST               RCC_AHB2RSTR_DCMIRST_Msk            
+#define RCC_AHB2RSTR_RNGRST_Pos            (6U)                                
+#define RCC_AHB2RSTR_RNGRST_Msk            (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)   /*!< 0x00000040 */
+#define RCC_AHB2RSTR_RNGRST                RCC_AHB2RSTR_RNGRST_Msk             
+#define RCC_AHB2RSTR_OTGFSRST_Pos          (7U)                                
+#define RCC_AHB2RSTR_OTGFSRST_Msk          (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */
+#define RCC_AHB2RSTR_OTGFSRST              RCC_AHB2RSTR_OTGFSRST_Msk           
+/********************  Bit definition for RCC_AHB3RSTR register  **************/
+#define RCC_AHB3RSTR_FSMCRST_Pos           (0U)                                
+#define RCC_AHB3RSTR_FSMCRST_Msk           (0x1UL << RCC_AHB3RSTR_FSMCRST_Pos)  /*!< 0x00000001 */
+#define RCC_AHB3RSTR_FSMCRST               RCC_AHB3RSTR_FSMCRST_Msk            
+
+
+/********************  Bit definition for RCC_APB1RSTR register  **************/
+#define RCC_APB1RSTR_TIM2RST_Pos           (0U)                                
+#define RCC_APB1RSTR_TIM2RST_Msk           (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)  /*!< 0x00000001 */
+#define RCC_APB1RSTR_TIM2RST               RCC_APB1RSTR_TIM2RST_Msk            
+#define RCC_APB1RSTR_TIM3RST_Pos           (1U)                                
+#define RCC_APB1RSTR_TIM3RST_Msk           (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)  /*!< 0x00000002 */
+#define RCC_APB1RSTR_TIM3RST               RCC_APB1RSTR_TIM3RST_Msk            
+#define RCC_APB1RSTR_TIM4RST_Pos           (2U)                                
+#define RCC_APB1RSTR_TIM4RST_Msk           (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)  /*!< 0x00000004 */
+#define RCC_APB1RSTR_TIM4RST               RCC_APB1RSTR_TIM4RST_Msk            
+#define RCC_APB1RSTR_TIM5RST_Pos           (3U)                                
+#define RCC_APB1RSTR_TIM5RST_Msk           (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)  /*!< 0x00000008 */
+#define RCC_APB1RSTR_TIM5RST               RCC_APB1RSTR_TIM5RST_Msk            
+#define RCC_APB1RSTR_TIM6RST_Pos           (4U)                                
+#define RCC_APB1RSTR_TIM6RST_Msk           (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)  /*!< 0x00000010 */
+#define RCC_APB1RSTR_TIM6RST               RCC_APB1RSTR_TIM6RST_Msk            
+#define RCC_APB1RSTR_TIM7RST_Pos           (5U)                                
+#define RCC_APB1RSTR_TIM7RST_Msk           (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)  /*!< 0x00000020 */
+#define RCC_APB1RSTR_TIM7RST               RCC_APB1RSTR_TIM7RST_Msk            
+#define RCC_APB1RSTR_TIM12RST_Pos          (6U)                                
+#define RCC_APB1RSTR_TIM12RST_Msk          (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */
+#define RCC_APB1RSTR_TIM12RST              RCC_APB1RSTR_TIM12RST_Msk           
+#define RCC_APB1RSTR_TIM13RST_Pos          (7U)                                
+#define RCC_APB1RSTR_TIM13RST_Msk          (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */
+#define RCC_APB1RSTR_TIM13RST              RCC_APB1RSTR_TIM13RST_Msk           
+#define RCC_APB1RSTR_TIM14RST_Pos          (8U)                                
+#define RCC_APB1RSTR_TIM14RST_Msk          (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
+#define RCC_APB1RSTR_TIM14RST              RCC_APB1RSTR_TIM14RST_Msk           
+#define RCC_APB1RSTR_WWDGRST_Pos           (11U)                               
+#define RCC_APB1RSTR_WWDGRST_Msk           (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)  /*!< 0x00000800 */
+#define RCC_APB1RSTR_WWDGRST               RCC_APB1RSTR_WWDGRST_Msk            
+#define RCC_APB1RSTR_SPI2RST_Pos           (14U)                               
+#define RCC_APB1RSTR_SPI2RST_Msk           (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)  /*!< 0x00004000 */
+#define RCC_APB1RSTR_SPI2RST               RCC_APB1RSTR_SPI2RST_Msk            
+#define RCC_APB1RSTR_SPI3RST_Pos           (15U)                               
+#define RCC_APB1RSTR_SPI3RST_Msk           (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)  /*!< 0x00008000 */
+#define RCC_APB1RSTR_SPI3RST               RCC_APB1RSTR_SPI3RST_Msk            
+#define RCC_APB1RSTR_USART2RST_Pos         (17U)                               
+#define RCC_APB1RSTR_USART2RST_Msk         (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
+#define RCC_APB1RSTR_USART2RST             RCC_APB1RSTR_USART2RST_Msk          
+#define RCC_APB1RSTR_USART3RST_Pos         (18U)                               
+#define RCC_APB1RSTR_USART3RST_Msk         (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
+#define RCC_APB1RSTR_USART3RST             RCC_APB1RSTR_USART3RST_Msk          
+#define RCC_APB1RSTR_UART4RST_Pos          (19U)                               
+#define RCC_APB1RSTR_UART4RST_Msk          (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */
+#define RCC_APB1RSTR_UART4RST              RCC_APB1RSTR_UART4RST_Msk           
+#define RCC_APB1RSTR_UART5RST_Pos          (20U)                               
+#define RCC_APB1RSTR_UART5RST_Msk          (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */
+#define RCC_APB1RSTR_UART5RST              RCC_APB1RSTR_UART5RST_Msk           
+#define RCC_APB1RSTR_I2C1RST_Pos           (21U)                               
+#define RCC_APB1RSTR_I2C1RST_Msk           (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)  /*!< 0x00200000 */
+#define RCC_APB1RSTR_I2C1RST               RCC_APB1RSTR_I2C1RST_Msk            
+#define RCC_APB1RSTR_I2C2RST_Pos           (22U)                               
+#define RCC_APB1RSTR_I2C2RST_Msk           (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)  /*!< 0x00400000 */
+#define RCC_APB1RSTR_I2C2RST               RCC_APB1RSTR_I2C2RST_Msk            
+#define RCC_APB1RSTR_I2C3RST_Pos           (23U)                               
+#define RCC_APB1RSTR_I2C3RST_Msk           (0x1UL << RCC_APB1RSTR_I2C3RST_Pos)  /*!< 0x00800000 */
+#define RCC_APB1RSTR_I2C3RST               RCC_APB1RSTR_I2C3RST_Msk            
+#define RCC_APB1RSTR_CAN1RST_Pos           (25U)                               
+#define RCC_APB1RSTR_CAN1RST_Msk           (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)  /*!< 0x02000000 */
+#define RCC_APB1RSTR_CAN1RST               RCC_APB1RSTR_CAN1RST_Msk            
+#define RCC_APB1RSTR_CAN2RST_Pos           (26U)                               
+#define RCC_APB1RSTR_CAN2RST_Msk           (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)  /*!< 0x04000000 */
+#define RCC_APB1RSTR_CAN2RST               RCC_APB1RSTR_CAN2RST_Msk            
+#define RCC_APB1RSTR_PWRRST_Pos            (28U)                               
+#define RCC_APB1RSTR_PWRRST_Msk            (0x1UL << RCC_APB1RSTR_PWRRST_Pos)   /*!< 0x10000000 */
+#define RCC_APB1RSTR_PWRRST                RCC_APB1RSTR_PWRRST_Msk             
+#define RCC_APB1RSTR_DACRST_Pos            (29U)                               
+#define RCC_APB1RSTR_DACRST_Msk            (0x1UL << RCC_APB1RSTR_DACRST_Pos)   /*!< 0x20000000 */
+#define RCC_APB1RSTR_DACRST                RCC_APB1RSTR_DACRST_Msk             
+
+/********************  Bit definition for RCC_APB2RSTR register  **************/
+#define RCC_APB2RSTR_TIM1RST_Pos           (0U)                                
+#define RCC_APB2RSTR_TIM1RST_Msk           (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)  /*!< 0x00000001 */
+#define RCC_APB2RSTR_TIM1RST               RCC_APB2RSTR_TIM1RST_Msk            
+#define RCC_APB2RSTR_TIM8RST_Pos           (1U)                                
+#define RCC_APB2RSTR_TIM8RST_Msk           (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)  /*!< 0x00000002 */
+#define RCC_APB2RSTR_TIM8RST               RCC_APB2RSTR_TIM8RST_Msk            
+#define RCC_APB2RSTR_USART1RST_Pos         (4U)                                
+#define RCC_APB2RSTR_USART1RST_Msk         (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
+#define RCC_APB2RSTR_USART1RST             RCC_APB2RSTR_USART1RST_Msk          
+#define RCC_APB2RSTR_USART6RST_Pos         (5U)                                
+#define RCC_APB2RSTR_USART6RST_Msk         (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
+#define RCC_APB2RSTR_USART6RST             RCC_APB2RSTR_USART6RST_Msk          
+#define RCC_APB2RSTR_ADCRST_Pos            (8U)                                
+#define RCC_APB2RSTR_ADCRST_Msk            (0x1UL << RCC_APB2RSTR_ADCRST_Pos)   /*!< 0x00000100 */
+#define RCC_APB2RSTR_ADCRST                RCC_APB2RSTR_ADCRST_Msk             
+#define RCC_APB2RSTR_SDIORST_Pos           (11U)                               
+#define RCC_APB2RSTR_SDIORST_Msk           (0x1UL << RCC_APB2RSTR_SDIORST_Pos)  /*!< 0x00000800 */
+#define RCC_APB2RSTR_SDIORST               RCC_APB2RSTR_SDIORST_Msk            
+#define RCC_APB2RSTR_SPI1RST_Pos           (12U)                               
+#define RCC_APB2RSTR_SPI1RST_Msk           (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)  /*!< 0x00001000 */
+#define RCC_APB2RSTR_SPI1RST               RCC_APB2RSTR_SPI1RST_Msk            
+#define RCC_APB2RSTR_SYSCFGRST_Pos         (14U)                               
+#define RCC_APB2RSTR_SYSCFGRST_Msk         (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */
+#define RCC_APB2RSTR_SYSCFGRST             RCC_APB2RSTR_SYSCFGRST_Msk          
+#define RCC_APB2RSTR_TIM9RST_Pos           (16U)                               
+#define RCC_APB2RSTR_TIM9RST_Msk           (0x1UL << RCC_APB2RSTR_TIM9RST_Pos)  /*!< 0x00010000 */
+#define RCC_APB2RSTR_TIM9RST               RCC_APB2RSTR_TIM9RST_Msk            
+#define RCC_APB2RSTR_TIM10RST_Pos          (17U)                               
+#define RCC_APB2RSTR_TIM10RST_Msk          (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */
+#define RCC_APB2RSTR_TIM10RST              RCC_APB2RSTR_TIM10RST_Msk           
+#define RCC_APB2RSTR_TIM11RST_Pos          (18U)                               
+#define RCC_APB2RSTR_TIM11RST_Msk          (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */
+#define RCC_APB2RSTR_TIM11RST              RCC_APB2RSTR_TIM11RST_Msk           
+
+/* Old SPI1RST bit definition, maintained for legacy purpose */
+#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST
+
+/********************  Bit definition for RCC_AHB1ENR register  ***************/
+#define RCC_AHB1ENR_GPIOAEN_Pos            (0U)                                
+#define RCC_AHB1ENR_GPIOAEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos)   /*!< 0x00000001 */
+#define RCC_AHB1ENR_GPIOAEN                RCC_AHB1ENR_GPIOAEN_Msk             
+#define RCC_AHB1ENR_GPIOBEN_Pos            (1U)                                
+#define RCC_AHB1ENR_GPIOBEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos)   /*!< 0x00000002 */
+#define RCC_AHB1ENR_GPIOBEN                RCC_AHB1ENR_GPIOBEN_Msk             
+#define RCC_AHB1ENR_GPIOCEN_Pos            (2U)                                
+#define RCC_AHB1ENR_GPIOCEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos)   /*!< 0x00000004 */
+#define RCC_AHB1ENR_GPIOCEN                RCC_AHB1ENR_GPIOCEN_Msk             
+#define RCC_AHB1ENR_GPIODEN_Pos            (3U)                                
+#define RCC_AHB1ENR_GPIODEN_Msk            (0x1UL << RCC_AHB1ENR_GPIODEN_Pos)   /*!< 0x00000008 */
+#define RCC_AHB1ENR_GPIODEN                RCC_AHB1ENR_GPIODEN_Msk             
+#define RCC_AHB1ENR_GPIOEEN_Pos            (4U)                                
+#define RCC_AHB1ENR_GPIOEEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos)   /*!< 0x00000010 */
+#define RCC_AHB1ENR_GPIOEEN                RCC_AHB1ENR_GPIOEEN_Msk             
+#define RCC_AHB1ENR_GPIOFEN_Pos            (5U)                                
+#define RCC_AHB1ENR_GPIOFEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos)   /*!< 0x00000020 */
+#define RCC_AHB1ENR_GPIOFEN                RCC_AHB1ENR_GPIOFEN_Msk             
+#define RCC_AHB1ENR_GPIOGEN_Pos            (6U)                                
+#define RCC_AHB1ENR_GPIOGEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos)   /*!< 0x00000040 */
+#define RCC_AHB1ENR_GPIOGEN                RCC_AHB1ENR_GPIOGEN_Msk             
+#define RCC_AHB1ENR_GPIOHEN_Pos            (7U)                                
+#define RCC_AHB1ENR_GPIOHEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos)   /*!< 0x00000080 */
+#define RCC_AHB1ENR_GPIOHEN                RCC_AHB1ENR_GPIOHEN_Msk             
+#define RCC_AHB1ENR_GPIOIEN_Pos            (8U)                                
+#define RCC_AHB1ENR_GPIOIEN_Msk            (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos)   /*!< 0x00000100 */
+#define RCC_AHB1ENR_GPIOIEN                RCC_AHB1ENR_GPIOIEN_Msk             
+#define RCC_AHB1ENR_CRCEN_Pos              (12U)                               
+#define RCC_AHB1ENR_CRCEN_Msk              (0x1UL << RCC_AHB1ENR_CRCEN_Pos)     /*!< 0x00001000 */
+#define RCC_AHB1ENR_CRCEN                  RCC_AHB1ENR_CRCEN_Msk               
+#define RCC_AHB1ENR_BKPSRAMEN_Pos          (18U)                               
+#define RCC_AHB1ENR_BKPSRAMEN_Msk          (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1ENR_BKPSRAMEN              RCC_AHB1ENR_BKPSRAMEN_Msk           
+#define RCC_AHB1ENR_CCMDATARAMEN_Pos       (20U)                               
+#define RCC_AHB1ENR_CCMDATARAMEN_Msk       (0x1UL << RCC_AHB1ENR_CCMDATARAMEN_Pos) /*!< 0x00100000 */
+#define RCC_AHB1ENR_CCMDATARAMEN           RCC_AHB1ENR_CCMDATARAMEN_Msk        
+#define RCC_AHB1ENR_DMA1EN_Pos             (21U)                               
+#define RCC_AHB1ENR_DMA1EN_Msk             (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)    /*!< 0x00200000 */
+#define RCC_AHB1ENR_DMA1EN                 RCC_AHB1ENR_DMA1EN_Msk              
+#define RCC_AHB1ENR_DMA2EN_Pos             (22U)                               
+#define RCC_AHB1ENR_DMA2EN_Msk             (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)    /*!< 0x00400000 */
+#define RCC_AHB1ENR_DMA2EN                 RCC_AHB1ENR_DMA2EN_Msk              
+#define RCC_AHB1ENR_ETHMACEN_Pos           (25U)                               
+#define RCC_AHB1ENR_ETHMACEN_Msk           (0x1UL << RCC_AHB1ENR_ETHMACEN_Pos)  /*!< 0x02000000 */
+#define RCC_AHB1ENR_ETHMACEN               RCC_AHB1ENR_ETHMACEN_Msk            
+#define RCC_AHB1ENR_ETHMACTXEN_Pos         (26U)                               
+#define RCC_AHB1ENR_ETHMACTXEN_Msk         (0x1UL << RCC_AHB1ENR_ETHMACTXEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1ENR_ETHMACTXEN             RCC_AHB1ENR_ETHMACTXEN_Msk          
+#define RCC_AHB1ENR_ETHMACRXEN_Pos         (27U)                               
+#define RCC_AHB1ENR_ETHMACRXEN_Msk         (0x1UL << RCC_AHB1ENR_ETHMACRXEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1ENR_ETHMACRXEN             RCC_AHB1ENR_ETHMACRXEN_Msk          
+#define RCC_AHB1ENR_ETHMACPTPEN_Pos        (28U)                               
+#define RCC_AHB1ENR_ETHMACPTPEN_Msk        (0x1UL << RCC_AHB1ENR_ETHMACPTPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1ENR_ETHMACPTPEN            RCC_AHB1ENR_ETHMACPTPEN_Msk         
+#define RCC_AHB1ENR_OTGHSEN_Pos            (29U)                               
+#define RCC_AHB1ENR_OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos)   /*!< 0x20000000 */
+#define RCC_AHB1ENR_OTGHSEN                RCC_AHB1ENR_OTGHSEN_Msk             
+#define RCC_AHB1ENR_OTGHSULPIEN_Pos        (30U)                               
+#define RCC_AHB1ENR_OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1ENR_OTGHSULPIEN            RCC_AHB1ENR_OTGHSULPIEN_Msk         
+/********************  Bit definition for RCC_AHB2ENR register  ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB2_SUPPORT                   /*!< AHB2 Bus is supported */
+
+#define RCC_AHB2ENR_DCMIEN_Pos             (0U)                                
+#define RCC_AHB2ENR_DCMIEN_Msk             (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)    /*!< 0x00000001 */
+#define RCC_AHB2ENR_DCMIEN                 RCC_AHB2ENR_DCMIEN_Msk              
+#define RCC_AHB2ENR_RNGEN_Pos              (6U)                                
+#define RCC_AHB2ENR_RNGEN_Msk              (0x1UL << RCC_AHB2ENR_RNGEN_Pos)     /*!< 0x00000040 */
+#define RCC_AHB2ENR_RNGEN                  RCC_AHB2ENR_RNGEN_Msk               
+#define RCC_AHB2ENR_OTGFSEN_Pos            (7U)                                
+#define RCC_AHB2ENR_OTGFSEN_Msk            (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos)   /*!< 0x00000080 */
+#define RCC_AHB2ENR_OTGFSEN                RCC_AHB2ENR_OTGFSEN_Msk             
+
+/********************  Bit definition for RCC_AHB3ENR register  ***************/
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32F4 serie)
+ */
+#define RCC_AHB3_SUPPORT                   /*!< AHB3 Bus is supported */
+
+#define RCC_AHB3ENR_FSMCEN_Pos             (0U)                                
+#define RCC_AHB3ENR_FSMCEN_Msk             (0x1UL << RCC_AHB3ENR_FSMCEN_Pos)    /*!< 0x00000001 */
+#define RCC_AHB3ENR_FSMCEN                 RCC_AHB3ENR_FSMCEN_Msk              
+
+/********************  Bit definition for RCC_APB1ENR register  ***************/
+#define RCC_APB1ENR_TIM2EN_Pos             (0U)                                
+#define RCC_APB1ENR_TIM2EN_Msk             (0x1UL << RCC_APB1ENR_TIM2EN_Pos)    /*!< 0x00000001 */
+#define RCC_APB1ENR_TIM2EN                 RCC_APB1ENR_TIM2EN_Msk              
+#define RCC_APB1ENR_TIM3EN_Pos             (1U)                                
+#define RCC_APB1ENR_TIM3EN_Msk             (0x1UL << RCC_APB1ENR_TIM3EN_Pos)    /*!< 0x00000002 */
+#define RCC_APB1ENR_TIM3EN                 RCC_APB1ENR_TIM3EN_Msk              
+#define RCC_APB1ENR_TIM4EN_Pos             (2U)                                
+#define RCC_APB1ENR_TIM4EN_Msk             (0x1UL << RCC_APB1ENR_TIM4EN_Pos)    /*!< 0x00000004 */
+#define RCC_APB1ENR_TIM4EN                 RCC_APB1ENR_TIM4EN_Msk              
+#define RCC_APB1ENR_TIM5EN_Pos             (3U)                                
+#define RCC_APB1ENR_TIM5EN_Msk             (0x1UL << RCC_APB1ENR_TIM5EN_Pos)    /*!< 0x00000008 */
+#define RCC_APB1ENR_TIM5EN                 RCC_APB1ENR_TIM5EN_Msk              
+#define RCC_APB1ENR_TIM6EN_Pos             (4U)                                
+#define RCC_APB1ENR_TIM6EN_Msk             (0x1UL << RCC_APB1ENR_TIM6EN_Pos)    /*!< 0x00000010 */
+#define RCC_APB1ENR_TIM6EN                 RCC_APB1ENR_TIM6EN_Msk              
+#define RCC_APB1ENR_TIM7EN_Pos             (5U)                                
+#define RCC_APB1ENR_TIM7EN_Msk             (0x1UL << RCC_APB1ENR_TIM7EN_Pos)    /*!< 0x00000020 */
+#define RCC_APB1ENR_TIM7EN                 RCC_APB1ENR_TIM7EN_Msk              
+#define RCC_APB1ENR_TIM12EN_Pos            (6U)                                
+#define RCC_APB1ENR_TIM12EN_Msk            (0x1UL << RCC_APB1ENR_TIM12EN_Pos)   /*!< 0x00000040 */
+#define RCC_APB1ENR_TIM12EN                RCC_APB1ENR_TIM12EN_Msk             
+#define RCC_APB1ENR_TIM13EN_Pos            (7U)                                
+#define RCC_APB1ENR_TIM13EN_Msk            (0x1UL << RCC_APB1ENR_TIM13EN_Pos)   /*!< 0x00000080 */
+#define RCC_APB1ENR_TIM13EN                RCC_APB1ENR_TIM13EN_Msk             
+#define RCC_APB1ENR_TIM14EN_Pos            (8U)                                
+#define RCC_APB1ENR_TIM14EN_Msk            (0x1UL << RCC_APB1ENR_TIM14EN_Pos)   /*!< 0x00000100 */
+#define RCC_APB1ENR_TIM14EN                RCC_APB1ENR_TIM14EN_Msk             
+#define RCC_APB1ENR_WWDGEN_Pos             (11U)                               
+#define RCC_APB1ENR_WWDGEN_Msk             (0x1UL << RCC_APB1ENR_WWDGEN_Pos)    /*!< 0x00000800 */
+#define RCC_APB1ENR_WWDGEN                 RCC_APB1ENR_WWDGEN_Msk              
+#define RCC_APB1ENR_SPI2EN_Pos             (14U)                               
+#define RCC_APB1ENR_SPI2EN_Msk             (0x1UL << RCC_APB1ENR_SPI2EN_Pos)    /*!< 0x00004000 */
+#define RCC_APB1ENR_SPI2EN                 RCC_APB1ENR_SPI2EN_Msk              
+#define RCC_APB1ENR_SPI3EN_Pos             (15U)                               
+#define RCC_APB1ENR_SPI3EN_Msk             (0x1UL << RCC_APB1ENR_SPI3EN_Pos)    /*!< 0x00008000 */
+#define RCC_APB1ENR_SPI3EN                 RCC_APB1ENR_SPI3EN_Msk              
+#define RCC_APB1ENR_USART2EN_Pos           (17U)                               
+#define RCC_APB1ENR_USART2EN_Msk           (0x1UL << RCC_APB1ENR_USART2EN_Pos)  /*!< 0x00020000 */
+#define RCC_APB1ENR_USART2EN               RCC_APB1ENR_USART2EN_Msk            
+#define RCC_APB1ENR_USART3EN_Pos           (18U)                               
+#define RCC_APB1ENR_USART3EN_Msk           (0x1UL << RCC_APB1ENR_USART3EN_Pos)  /*!< 0x00040000 */
+#define RCC_APB1ENR_USART3EN               RCC_APB1ENR_USART3EN_Msk            
+#define RCC_APB1ENR_UART4EN_Pos            (19U)                               
+#define RCC_APB1ENR_UART4EN_Msk            (0x1UL << RCC_APB1ENR_UART4EN_Pos)   /*!< 0x00080000 */
+#define RCC_APB1ENR_UART4EN                RCC_APB1ENR_UART4EN_Msk             
+#define RCC_APB1ENR_UART5EN_Pos            (20U)                               
+#define RCC_APB1ENR_UART5EN_Msk            (0x1UL << RCC_APB1ENR_UART5EN_Pos)   /*!< 0x00100000 */
+#define RCC_APB1ENR_UART5EN                RCC_APB1ENR_UART5EN_Msk             
+#define RCC_APB1ENR_I2C1EN_Pos             (21U)                               
+#define RCC_APB1ENR_I2C1EN_Msk             (0x1UL << RCC_APB1ENR_I2C1EN_Pos)    /*!< 0x00200000 */
+#define RCC_APB1ENR_I2C1EN                 RCC_APB1ENR_I2C1EN_Msk              
+#define RCC_APB1ENR_I2C2EN_Pos             (22U)                               
+#define RCC_APB1ENR_I2C2EN_Msk             (0x1UL << RCC_APB1ENR_I2C2EN_Pos)    /*!< 0x00400000 */
+#define RCC_APB1ENR_I2C2EN                 RCC_APB1ENR_I2C2EN_Msk              
+#define RCC_APB1ENR_I2C3EN_Pos             (23U)                               
+#define RCC_APB1ENR_I2C3EN_Msk             (0x1UL << RCC_APB1ENR_I2C3EN_Pos)    /*!< 0x00800000 */
+#define RCC_APB1ENR_I2C3EN                 RCC_APB1ENR_I2C3EN_Msk              
+#define RCC_APB1ENR_CAN1EN_Pos             (25U)                               
+#define RCC_APB1ENR_CAN1EN_Msk             (0x1UL << RCC_APB1ENR_CAN1EN_Pos)    /*!< 0x02000000 */
+#define RCC_APB1ENR_CAN1EN                 RCC_APB1ENR_CAN1EN_Msk              
+#define RCC_APB1ENR_CAN2EN_Pos             (26U)                               
+#define RCC_APB1ENR_CAN2EN_Msk             (0x1UL << RCC_APB1ENR_CAN2EN_Pos)    /*!< 0x04000000 */
+#define RCC_APB1ENR_CAN2EN                 RCC_APB1ENR_CAN2EN_Msk              
+#define RCC_APB1ENR_PWREN_Pos              (28U)                               
+#define RCC_APB1ENR_PWREN_Msk              (0x1UL << RCC_APB1ENR_PWREN_Pos)     /*!< 0x10000000 */
+#define RCC_APB1ENR_PWREN                  RCC_APB1ENR_PWREN_Msk               
+#define RCC_APB1ENR_DACEN_Pos              (29U)                               
+#define RCC_APB1ENR_DACEN_Msk              (0x1UL << RCC_APB1ENR_DACEN_Pos)     /*!< 0x20000000 */
+#define RCC_APB1ENR_DACEN                  RCC_APB1ENR_DACEN_Msk               
+
+/********************  Bit definition for RCC_APB2ENR register  ***************/
+#define RCC_APB2ENR_TIM1EN_Pos             (0U)                                
+#define RCC_APB2ENR_TIM1EN_Msk             (0x1UL << RCC_APB2ENR_TIM1EN_Pos)    /*!< 0x00000001 */
+#define RCC_APB2ENR_TIM1EN                 RCC_APB2ENR_TIM1EN_Msk              
+#define RCC_APB2ENR_TIM8EN_Pos             (1U)                                
+#define RCC_APB2ENR_TIM8EN_Msk             (0x1UL << RCC_APB2ENR_TIM8EN_Pos)    /*!< 0x00000002 */
+#define RCC_APB2ENR_TIM8EN                 RCC_APB2ENR_TIM8EN_Msk              
+#define RCC_APB2ENR_USART1EN_Pos           (4U)                                
+#define RCC_APB2ENR_USART1EN_Msk           (0x1UL << RCC_APB2ENR_USART1EN_Pos)  /*!< 0x00000010 */
+#define RCC_APB2ENR_USART1EN               RCC_APB2ENR_USART1EN_Msk            
+#define RCC_APB2ENR_USART6EN_Pos           (5U)                                
+#define RCC_APB2ENR_USART6EN_Msk           (0x1UL << RCC_APB2ENR_USART6EN_Pos)  /*!< 0x00000020 */
+#define RCC_APB2ENR_USART6EN               RCC_APB2ENR_USART6EN_Msk            
+#define RCC_APB2ENR_ADC1EN_Pos             (8U)                                
+#define RCC_APB2ENR_ADC1EN_Msk             (0x1UL << RCC_APB2ENR_ADC1EN_Pos)    /*!< 0x00000100 */
+#define RCC_APB2ENR_ADC1EN                 RCC_APB2ENR_ADC1EN_Msk              
+#define RCC_APB2ENR_ADC2EN_Pos             (9U)                                
+#define RCC_APB2ENR_ADC2EN_Msk             (0x1UL << RCC_APB2ENR_ADC2EN_Pos)    /*!< 0x00000200 */
+#define RCC_APB2ENR_ADC2EN                 RCC_APB2ENR_ADC2EN_Msk              
+#define RCC_APB2ENR_ADC3EN_Pos             (10U)                               
+#define RCC_APB2ENR_ADC3EN_Msk             (0x1UL << RCC_APB2ENR_ADC3EN_Pos)    /*!< 0x00000400 */
+#define RCC_APB2ENR_ADC3EN                 RCC_APB2ENR_ADC3EN_Msk              
+#define RCC_APB2ENR_SDIOEN_Pos             (11U)                               
+#define RCC_APB2ENR_SDIOEN_Msk             (0x1UL << RCC_APB2ENR_SDIOEN_Pos)    /*!< 0x00000800 */
+#define RCC_APB2ENR_SDIOEN                 RCC_APB2ENR_SDIOEN_Msk              
+#define RCC_APB2ENR_SPI1EN_Pos             (12U)                               
+#define RCC_APB2ENR_SPI1EN_Msk             (0x1UL << RCC_APB2ENR_SPI1EN_Pos)    /*!< 0x00001000 */
+#define RCC_APB2ENR_SPI1EN                 RCC_APB2ENR_SPI1EN_Msk              
+#define RCC_APB2ENR_SYSCFGEN_Pos           (14U)                               
+#define RCC_APB2ENR_SYSCFGEN_Msk           (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)  /*!< 0x00004000 */
+#define RCC_APB2ENR_SYSCFGEN               RCC_APB2ENR_SYSCFGEN_Msk            
+#define RCC_APB2ENR_TIM9EN_Pos             (16U)                               
+#define RCC_APB2ENR_TIM9EN_Msk             (0x1UL << RCC_APB2ENR_TIM9EN_Pos)    /*!< 0x00010000 */
+#define RCC_APB2ENR_TIM9EN                 RCC_APB2ENR_TIM9EN_Msk              
+#define RCC_APB2ENR_TIM10EN_Pos            (17U)                               
+#define RCC_APB2ENR_TIM10EN_Msk            (0x1UL << RCC_APB2ENR_TIM10EN_Pos)   /*!< 0x00020000 */
+#define RCC_APB2ENR_TIM10EN                RCC_APB2ENR_TIM10EN_Msk             
+#define RCC_APB2ENR_TIM11EN_Pos            (18U)                               
+#define RCC_APB2ENR_TIM11EN_Msk            (0x1UL << RCC_APB2ENR_TIM11EN_Pos)   /*!< 0x00040000 */
+#define RCC_APB2ENR_TIM11EN                RCC_APB2ENR_TIM11EN_Msk             
+
+/********************  Bit definition for RCC_AHB1LPENR register  *************/
+#define RCC_AHB1LPENR_GPIOALPEN_Pos        (0U)                                
+#define RCC_AHB1LPENR_GPIOALPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB1LPENR_GPIOALPEN            RCC_AHB1LPENR_GPIOALPEN_Msk         
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos        (1U)                                
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
+#define RCC_AHB1LPENR_GPIOBLPEN            RCC_AHB1LPENR_GPIOBLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos        (2U)                                
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
+#define RCC_AHB1LPENR_GPIOCLPEN            RCC_AHB1LPENR_GPIOCLPEN_Msk         
+#define RCC_AHB1LPENR_GPIODLPEN_Pos        (3U)                                
+#define RCC_AHB1LPENR_GPIODLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
+#define RCC_AHB1LPENR_GPIODLPEN            RCC_AHB1LPENR_GPIODLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOELPEN_Pos        (4U)                                
+#define RCC_AHB1LPENR_GPIOELPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
+#define RCC_AHB1LPENR_GPIOELPEN            RCC_AHB1LPENR_GPIOELPEN_Msk         
+#define RCC_AHB1LPENR_GPIOFLPEN_Pos        (5U)                                
+#define RCC_AHB1LPENR_GPIOFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
+#define RCC_AHB1LPENR_GPIOFLPEN            RCC_AHB1LPENR_GPIOFLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOGLPEN_Pos        (6U)                                
+#define RCC_AHB1LPENR_GPIOGLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB1LPENR_GPIOGLPEN            RCC_AHB1LPENR_GPIOGLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos        (7U)                                
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB1LPENR_GPIOHLPEN            RCC_AHB1LPENR_GPIOHLPEN_Msk         
+#define RCC_AHB1LPENR_GPIOILPEN_Pos        (8U)                                
+#define RCC_AHB1LPENR_GPIOILPEN_Msk        (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
+#define RCC_AHB1LPENR_GPIOILPEN            RCC_AHB1LPENR_GPIOILPEN_Msk         
+#define RCC_AHB1LPENR_CRCLPEN_Pos          (12U)                               
+#define RCC_AHB1LPENR_CRCLPEN_Msk          (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */
+#define RCC_AHB1LPENR_CRCLPEN              RCC_AHB1LPENR_CRCLPEN_Msk           
+#define RCC_AHB1LPENR_FLITFLPEN_Pos        (15U)                               
+#define RCC_AHB1LPENR_FLITFLPEN_Msk        (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
+#define RCC_AHB1LPENR_FLITFLPEN            RCC_AHB1LPENR_FLITFLPEN_Msk         
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos        (16U)                               
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */
+#define RCC_AHB1LPENR_SRAM1LPEN            RCC_AHB1LPENR_SRAM1LPEN_Msk         
+#define RCC_AHB1LPENR_SRAM2LPEN_Pos        (17U)                               
+#define RCC_AHB1LPENR_SRAM2LPEN_Msk        (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_AHB1LPENR_SRAM2LPEN            RCC_AHB1LPENR_SRAM2LPEN_Msk         
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos      (18U)                               
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk      (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */
+#define RCC_AHB1LPENR_BKPSRAMLPEN          RCC_AHB1LPENR_BKPSRAMLPEN_Msk       
+#define RCC_AHB1LPENR_DMA1LPEN_Pos         (21U)                               
+#define RCC_AHB1LPENR_DMA1LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_AHB1LPENR_DMA1LPEN             RCC_AHB1LPENR_DMA1LPEN_Msk          
+#define RCC_AHB1LPENR_DMA2LPEN_Pos         (22U)                               
+#define RCC_AHB1LPENR_DMA2LPEN_Msk         (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_AHB1LPENR_DMA2LPEN             RCC_AHB1LPENR_DMA2LPEN_Msk          
+
+#define RCC_AHB1LPENR_ETHMACLPEN_Pos       (25U)                               
+#define RCC_AHB1LPENR_ETHMACLPEN_Msk       (0x1UL << RCC_AHB1LPENR_ETHMACLPEN_Pos) /*!< 0x02000000 */
+#define RCC_AHB1LPENR_ETHMACLPEN           RCC_AHB1LPENR_ETHMACLPEN_Msk        
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Pos     (26U)                               
+#define RCC_AHB1LPENR_ETHMACTXLPEN_Msk     (0x1UL << RCC_AHB1LPENR_ETHMACTXLPEN_Pos) /*!< 0x04000000 */
+#define RCC_AHB1LPENR_ETHMACTXLPEN         RCC_AHB1LPENR_ETHMACTXLPEN_Msk      
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Pos     (27U)                               
+#define RCC_AHB1LPENR_ETHMACRXLPEN_Msk     (0x1UL << RCC_AHB1LPENR_ETHMACRXLPEN_Pos) /*!< 0x08000000 */
+#define RCC_AHB1LPENR_ETHMACRXLPEN         RCC_AHB1LPENR_ETHMACRXLPEN_Msk      
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Pos    (28U)                               
+#define RCC_AHB1LPENR_ETHMACPTPLPEN_Msk    (0x1UL << RCC_AHB1LPENR_ETHMACPTPLPEN_Pos) /*!< 0x10000000 */
+#define RCC_AHB1LPENR_ETHMACPTPLPEN        RCC_AHB1LPENR_ETHMACPTPLPEN_Msk     
+#define RCC_AHB1LPENR_OTGHSLPEN_Pos        (29U)                               
+#define RCC_AHB1LPENR_OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */
+#define RCC_AHB1LPENR_OTGHSLPEN            RCC_AHB1LPENR_OTGHSLPEN_Msk         
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos    (30U)                               
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */
+#define RCC_AHB1LPENR_OTGHSULPILPEN        RCC_AHB1LPENR_OTGHSULPILPEN_Msk     
+
+/********************  Bit definition for RCC_AHB2LPENR register  *************/
+#define RCC_AHB2LPENR_DCMILPEN_Pos         (0U)                                
+#define RCC_AHB2LPENR_DCMILPEN_Msk         (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB2LPENR_DCMILPEN             RCC_AHB2LPENR_DCMILPEN_Msk          
+#define RCC_AHB2LPENR_RNGLPEN_Pos          (6U)                                
+#define RCC_AHB2LPENR_RNGLPEN_Msk          (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
+#define RCC_AHB2LPENR_RNGLPEN              RCC_AHB2LPENR_RNGLPEN_Msk           
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos        (7U)                                
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk        (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */
+#define RCC_AHB2LPENR_OTGFSLPEN            RCC_AHB2LPENR_OTGFSLPEN_Msk         
+
+/********************  Bit definition for RCC_AHB3LPENR register  *************/
+#define RCC_AHB3LPENR_FSMCLPEN_Pos         (0U)                                
+#define RCC_AHB3LPENR_FSMCLPEN_Msk         (0x1UL << RCC_AHB3LPENR_FSMCLPEN_Pos) /*!< 0x00000001 */
+#define RCC_AHB3LPENR_FSMCLPEN             RCC_AHB3LPENR_FSMCLPEN_Msk          
+
+/********************  Bit definition for RCC_APB1LPENR register  *************/
+#define RCC_APB1LPENR_TIM2LPEN_Pos         (0U)                                
+#define RCC_APB1LPENR_TIM2LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB1LPENR_TIM2LPEN             RCC_APB1LPENR_TIM2LPEN_Msk          
+#define RCC_APB1LPENR_TIM3LPEN_Pos         (1U)                                
+#define RCC_APB1LPENR_TIM3LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB1LPENR_TIM3LPEN             RCC_APB1LPENR_TIM3LPEN_Msk          
+#define RCC_APB1LPENR_TIM4LPEN_Pos         (2U)                                
+#define RCC_APB1LPENR_TIM4LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
+#define RCC_APB1LPENR_TIM4LPEN             RCC_APB1LPENR_TIM4LPEN_Msk          
+#define RCC_APB1LPENR_TIM5LPEN_Pos         (3U)                                
+#define RCC_APB1LPENR_TIM5LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
+#define RCC_APB1LPENR_TIM5LPEN             RCC_APB1LPENR_TIM5LPEN_Msk          
+#define RCC_APB1LPENR_TIM6LPEN_Pos         (4U)                                
+#define RCC_APB1LPENR_TIM6LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB1LPENR_TIM6LPEN             RCC_APB1LPENR_TIM6LPEN_Msk          
+#define RCC_APB1LPENR_TIM7LPEN_Pos         (5U)                                
+#define RCC_APB1LPENR_TIM7LPEN_Msk         (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB1LPENR_TIM7LPEN             RCC_APB1LPENR_TIM7LPEN_Msk          
+#define RCC_APB1LPENR_TIM12LPEN_Pos        (6U)                                
+#define RCC_APB1LPENR_TIM12LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
+#define RCC_APB1LPENR_TIM12LPEN            RCC_APB1LPENR_TIM12LPEN_Msk         
+#define RCC_APB1LPENR_TIM13LPEN_Pos        (7U)                                
+#define RCC_APB1LPENR_TIM13LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
+#define RCC_APB1LPENR_TIM13LPEN            RCC_APB1LPENR_TIM13LPEN_Msk         
+#define RCC_APB1LPENR_TIM14LPEN_Pos        (8U)                                
+#define RCC_APB1LPENR_TIM14LPEN_Msk        (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB1LPENR_TIM14LPEN            RCC_APB1LPENR_TIM14LPEN_Msk         
+#define RCC_APB1LPENR_WWDGLPEN_Pos         (11U)                               
+#define RCC_APB1LPENR_WWDGLPEN_Msk         (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB1LPENR_WWDGLPEN             RCC_APB1LPENR_WWDGLPEN_Msk          
+#define RCC_APB1LPENR_SPI2LPEN_Pos         (14U)                               
+#define RCC_APB1LPENR_SPI2LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB1LPENR_SPI2LPEN             RCC_APB1LPENR_SPI2LPEN_Msk          
+#define RCC_APB1LPENR_SPI3LPEN_Pos         (15U)                               
+#define RCC_APB1LPENR_SPI3LPEN_Msk         (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
+#define RCC_APB1LPENR_SPI3LPEN             RCC_APB1LPENR_SPI3LPEN_Msk          
+#define RCC_APB1LPENR_USART2LPEN_Pos       (17U)                               
+#define RCC_APB1LPENR_USART2LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB1LPENR_USART2LPEN           RCC_APB1LPENR_USART2LPEN_Msk        
+#define RCC_APB1LPENR_USART3LPEN_Pos       (18U)                               
+#define RCC_APB1LPENR_USART3LPEN_Msk       (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB1LPENR_USART3LPEN           RCC_APB1LPENR_USART3LPEN_Msk        
+#define RCC_APB1LPENR_UART4LPEN_Pos        (19U)                               
+#define RCC_APB1LPENR_UART4LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */
+#define RCC_APB1LPENR_UART4LPEN            RCC_APB1LPENR_UART4LPEN_Msk         
+#define RCC_APB1LPENR_UART5LPEN_Pos        (20U)                               
+#define RCC_APB1LPENR_UART5LPEN_Msk        (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */
+#define RCC_APB1LPENR_UART5LPEN            RCC_APB1LPENR_UART5LPEN_Msk         
+#define RCC_APB1LPENR_I2C1LPEN_Pos         (21U)                               
+#define RCC_APB1LPENR_I2C1LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
+#define RCC_APB1LPENR_I2C1LPEN             RCC_APB1LPENR_I2C1LPEN_Msk          
+#define RCC_APB1LPENR_I2C2LPEN_Pos         (22U)                               
+#define RCC_APB1LPENR_I2C2LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
+#define RCC_APB1LPENR_I2C2LPEN             RCC_APB1LPENR_I2C2LPEN_Msk          
+#define RCC_APB1LPENR_I2C3LPEN_Pos         (23U)                               
+#define RCC_APB1LPENR_I2C3LPEN_Msk         (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
+#define RCC_APB1LPENR_I2C3LPEN             RCC_APB1LPENR_I2C3LPEN_Msk          
+#define RCC_APB1LPENR_CAN1LPEN_Pos         (25U)                               
+#define RCC_APB1LPENR_CAN1LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */
+#define RCC_APB1LPENR_CAN1LPEN             RCC_APB1LPENR_CAN1LPEN_Msk          
+#define RCC_APB1LPENR_CAN2LPEN_Pos         (26U)                               
+#define RCC_APB1LPENR_CAN2LPEN_Msk         (0x1UL << RCC_APB1LPENR_CAN2LPEN_Pos) /*!< 0x04000000 */
+#define RCC_APB1LPENR_CAN2LPEN             RCC_APB1LPENR_CAN2LPEN_Msk          
+#define RCC_APB1LPENR_PWRLPEN_Pos          (28U)                               
+#define RCC_APB1LPENR_PWRLPEN_Msk          (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
+#define RCC_APB1LPENR_PWRLPEN              RCC_APB1LPENR_PWRLPEN_Msk           
+#define RCC_APB1LPENR_DACLPEN_Pos          (29U)                               
+#define RCC_APB1LPENR_DACLPEN_Msk          (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
+#define RCC_APB1LPENR_DACLPEN              RCC_APB1LPENR_DACLPEN_Msk           
+
+/********************  Bit definition for RCC_APB2LPENR register  *************/
+#define RCC_APB2LPENR_TIM1LPEN_Pos         (0U)                                
+#define RCC_APB2LPENR_TIM1LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
+#define RCC_APB2LPENR_TIM1LPEN             RCC_APB2LPENR_TIM1LPEN_Msk          
+#define RCC_APB2LPENR_TIM8LPEN_Pos         (1U)                                
+#define RCC_APB2LPENR_TIM8LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
+#define RCC_APB2LPENR_TIM8LPEN             RCC_APB2LPENR_TIM8LPEN_Msk          
+#define RCC_APB2LPENR_USART1LPEN_Pos       (4U)                                
+#define RCC_APB2LPENR_USART1LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
+#define RCC_APB2LPENR_USART1LPEN           RCC_APB2LPENR_USART1LPEN_Msk        
+#define RCC_APB2LPENR_USART6LPEN_Pos       (5U)                                
+#define RCC_APB2LPENR_USART6LPEN_Msk       (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
+#define RCC_APB2LPENR_USART6LPEN           RCC_APB2LPENR_USART6LPEN_Msk        
+#define RCC_APB2LPENR_ADC1LPEN_Pos         (8U)                                
+#define RCC_APB2LPENR_ADC1LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */
+#define RCC_APB2LPENR_ADC1LPEN             RCC_APB2LPENR_ADC1LPEN_Msk          
+#define RCC_APB2LPENR_ADC2LPEN_Pos         (9U)                                
+#define RCC_APB2LPENR_ADC2LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */
+#define RCC_APB2LPENR_ADC2LPEN             RCC_APB2LPENR_ADC2LPEN_Msk          
+#define RCC_APB2LPENR_ADC3LPEN_Pos         (10U)                               
+#define RCC_APB2LPENR_ADC3LPEN_Msk         (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */
+#define RCC_APB2LPENR_ADC3LPEN             RCC_APB2LPENR_ADC3LPEN_Msk          
+#define RCC_APB2LPENR_SDIOLPEN_Pos         (11U)                               
+#define RCC_APB2LPENR_SDIOLPEN_Msk         (0x1UL << RCC_APB2LPENR_SDIOLPEN_Pos) /*!< 0x00000800 */
+#define RCC_APB2LPENR_SDIOLPEN             RCC_APB2LPENR_SDIOLPEN_Msk          
+#define RCC_APB2LPENR_SPI1LPEN_Pos         (12U)                               
+#define RCC_APB2LPENR_SPI1LPEN_Msk         (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
+#define RCC_APB2LPENR_SPI1LPEN             RCC_APB2LPENR_SPI1LPEN_Msk          
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos       (14U)                               
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk       (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */
+#define RCC_APB2LPENR_SYSCFGLPEN           RCC_APB2LPENR_SYSCFGLPEN_Msk        
+#define RCC_APB2LPENR_TIM9LPEN_Pos         (16U)                               
+#define RCC_APB2LPENR_TIM9LPEN_Msk         (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */
+#define RCC_APB2LPENR_TIM9LPEN             RCC_APB2LPENR_TIM9LPEN_Msk          
+#define RCC_APB2LPENR_TIM10LPEN_Pos        (17U)                               
+#define RCC_APB2LPENR_TIM10LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */
+#define RCC_APB2LPENR_TIM10LPEN            RCC_APB2LPENR_TIM10LPEN_Msk         
+#define RCC_APB2LPENR_TIM11LPEN_Pos        (18U)                               
+#define RCC_APB2LPENR_TIM11LPEN_Msk        (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */
+#define RCC_APB2LPENR_TIM11LPEN            RCC_APB2LPENR_TIM11LPEN_Msk         
+
+/********************  Bit definition for RCC_BDCR register  ******************/
+#define RCC_BDCR_LSEON_Pos                 (0U)                                
+#define RCC_BDCR_LSEON_Msk                 (0x1UL << RCC_BDCR_LSEON_Pos)        /*!< 0x00000001 */
+#define RCC_BDCR_LSEON                     RCC_BDCR_LSEON_Msk                  
+#define RCC_BDCR_LSERDY_Pos                (1U)                                
+#define RCC_BDCR_LSERDY_Msk                (0x1UL << RCC_BDCR_LSERDY_Pos)       /*!< 0x00000002 */
+#define RCC_BDCR_LSERDY                    RCC_BDCR_LSERDY_Msk                 
+#define RCC_BDCR_LSEBYP_Pos                (2U)                                
+#define RCC_BDCR_LSEBYP_Msk                (0x1UL << RCC_BDCR_LSEBYP_Pos)       /*!< 0x00000004 */
+#define RCC_BDCR_LSEBYP                    RCC_BDCR_LSEBYP_Msk                 
+
+#define RCC_BDCR_RTCSEL_Pos                (8U)                                
+#define RCC_BDCR_RTCSEL_Msk                (0x3UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000300 */
+#define RCC_BDCR_RTCSEL                    RCC_BDCR_RTCSEL_Msk                 
+#define RCC_BDCR_RTCSEL_0                  (0x1UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000100 */
+#define RCC_BDCR_RTCSEL_1                  (0x2UL << RCC_BDCR_RTCSEL_Pos)       /*!< 0x00000200 */
+
+#define RCC_BDCR_RTCEN_Pos                 (15U)                               
+#define RCC_BDCR_RTCEN_Msk                 (0x1UL << RCC_BDCR_RTCEN_Pos)        /*!< 0x00008000 */
+#define RCC_BDCR_RTCEN                     RCC_BDCR_RTCEN_Msk                  
+#define RCC_BDCR_BDRST_Pos                 (16U)                               
+#define RCC_BDCR_BDRST_Msk                 (0x1UL << RCC_BDCR_BDRST_Pos)        /*!< 0x00010000 */
+#define RCC_BDCR_BDRST                     RCC_BDCR_BDRST_Msk                  
+
+/********************  Bit definition for RCC_CSR register  *******************/
+#define RCC_CSR_LSION_Pos                  (0U)                                
+#define RCC_CSR_LSION_Msk                  (0x1UL << RCC_CSR_LSION_Pos)         /*!< 0x00000001 */
+#define RCC_CSR_LSION                      RCC_CSR_LSION_Msk                   
+#define RCC_CSR_LSIRDY_Pos                 (1U)                                
+#define RCC_CSR_LSIRDY_Msk                 (0x1UL << RCC_CSR_LSIRDY_Pos)        /*!< 0x00000002 */
+#define RCC_CSR_LSIRDY                     RCC_CSR_LSIRDY_Msk                  
+#define RCC_CSR_RMVF_Pos                   (24U)                               
+#define RCC_CSR_RMVF_Msk                   (0x1UL << RCC_CSR_RMVF_Pos)          /*!< 0x01000000 */
+#define RCC_CSR_RMVF                       RCC_CSR_RMVF_Msk                    
+#define RCC_CSR_BORRSTF_Pos                (25U)                               
+#define RCC_CSR_BORRSTF_Msk                (0x1UL << RCC_CSR_BORRSTF_Pos)       /*!< 0x02000000 */
+#define RCC_CSR_BORRSTF                    RCC_CSR_BORRSTF_Msk                 
+#define RCC_CSR_PINRSTF_Pos                (26U)
+#define RCC_CSR_PINRSTF_Msk                (0x1UL << RCC_CSR_PINRSTF_Pos)       /*!< 0x04000000 */
+#define RCC_CSR_PINRSTF                    RCC_CSR_PINRSTF_Msk
+#define RCC_CSR_PORRSTF_Pos                (27U)                               
+#define RCC_CSR_PORRSTF_Msk                (0x1UL << RCC_CSR_PORRSTF_Pos)       /*!< 0x08000000 */
+#define RCC_CSR_PORRSTF                    RCC_CSR_PORRSTF_Msk                 
+#define RCC_CSR_SFTRSTF_Pos                (28U)                               
+#define RCC_CSR_SFTRSTF_Msk                (0x1UL << RCC_CSR_SFTRSTF_Pos)       /*!< 0x10000000 */
+#define RCC_CSR_SFTRSTF                    RCC_CSR_SFTRSTF_Msk                 
+#define RCC_CSR_IWDGRSTF_Pos               (29U)
+#define RCC_CSR_IWDGRSTF_Msk               (0x1UL << RCC_CSR_IWDGRSTF_Pos)      /*!< 0x20000000 */
+#define RCC_CSR_IWDGRSTF                   RCC_CSR_IWDGRSTF_Msk
+#define RCC_CSR_WWDGRSTF_Pos               (30U)                               
+#define RCC_CSR_WWDGRSTF_Msk               (0x1UL << RCC_CSR_WWDGRSTF_Pos)      /*!< 0x40000000 */
+#define RCC_CSR_WWDGRSTF                   RCC_CSR_WWDGRSTF_Msk                
+#define RCC_CSR_LPWRRSTF_Pos               (31U)                               
+#define RCC_CSR_LPWRRSTF_Msk               (0x1UL << RCC_CSR_LPWRRSTF_Pos)      /*!< 0x80000000 */
+#define RCC_CSR_LPWRRSTF                   RCC_CSR_LPWRRSTF_Msk
+/* Legacy defines */
+#define RCC_CSR_PADRSTF                    RCC_CSR_PINRSTF
+#define RCC_CSR_WDGRSTF                    RCC_CSR_IWDGRSTF
+
+/********************  Bit definition for RCC_SSCGR register  *****************/
+#define RCC_SSCGR_MODPER_Pos               (0U)                                
+#define RCC_SSCGR_MODPER_Msk               (0x1FFFUL << RCC_SSCGR_MODPER_Pos)   /*!< 0x00001FFF */
+#define RCC_SSCGR_MODPER                   RCC_SSCGR_MODPER_Msk                
+#define RCC_SSCGR_INCSTEP_Pos              (13U)                               
+#define RCC_SSCGR_INCSTEP_Msk              (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos)  /*!< 0x0FFFE000 */
+#define RCC_SSCGR_INCSTEP                  RCC_SSCGR_INCSTEP_Msk               
+#define RCC_SSCGR_SPREADSEL_Pos            (30U)                               
+#define RCC_SSCGR_SPREADSEL_Msk            (0x1UL << RCC_SSCGR_SPREADSEL_Pos)   /*!< 0x40000000 */
+#define RCC_SSCGR_SPREADSEL                RCC_SSCGR_SPREADSEL_Msk             
+#define RCC_SSCGR_SSCGEN_Pos               (31U)                               
+#define RCC_SSCGR_SSCGEN_Msk               (0x1UL << RCC_SSCGR_SSCGEN_Pos)      /*!< 0x80000000 */
+#define RCC_SSCGR_SSCGEN                   RCC_SSCGR_SSCGEN_Msk                
+
+/********************  Bit definition for RCC_PLLI2SCFGR register  ************/
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos         (6U)                                
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk         (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */
+#define RCC_PLLI2SCFGR_PLLI2SN             RCC_PLLI2SCFGR_PLLI2SN_Msk          
+#define RCC_PLLI2SCFGR_PLLI2SN_0           (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */
+#define RCC_PLLI2SCFGR_PLLI2SN_1           (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */
+#define RCC_PLLI2SCFGR_PLLI2SN_2           (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */
+#define RCC_PLLI2SCFGR_PLLI2SN_3           (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */
+#define RCC_PLLI2SCFGR_PLLI2SN_4           (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */
+#define RCC_PLLI2SCFGR_PLLI2SN_5           (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */
+#define RCC_PLLI2SCFGR_PLLI2SN_6           (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_7           (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */
+#define RCC_PLLI2SCFGR_PLLI2SN_8           (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */
+
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos         (28U)                               
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk         (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR             RCC_PLLI2SCFGR_PLLI2SR_Msk          
+#define RCC_PLLI2SCFGR_PLLI2SR_0           (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_1           (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */
+#define RCC_PLLI2SCFGR_PLLI2SR_2           (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    RNG                                     */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bits definition for RNG_CR register  *******************/
+#define RNG_CR_RNGEN_Pos    (2U)                                               
+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                         /*!< 0x00000004 */
+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk                                   
+#define RNG_CR_IE_Pos       (3U)                                               
+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                            /*!< 0x00000008 */
+#define RNG_CR_IE           RNG_CR_IE_Msk                                      
+
+/********************  Bits definition for RNG_SR register  *******************/
+#define RNG_SR_DRDY_Pos     (0U)                                               
+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                          /*!< 0x00000001 */
+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk                                    
+#define RNG_SR_CECS_Pos     (1U)                                               
+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                          /*!< 0x00000002 */
+#define RNG_SR_CECS         RNG_SR_CECS_Msk                                    
+#define RNG_SR_SECS_Pos     (2U)                                               
+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                          /*!< 0x00000004 */
+#define RNG_SR_SECS         RNG_SR_SECS_Msk                                    
+#define RNG_SR_CEIS_Pos     (5U)                                               
+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                          /*!< 0x00000020 */
+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk                                    
+#define RNG_SR_SEIS_Pos     (6U)                                               
+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                          /*!< 0x00000040 */
+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk                                    
+
+/******************************************************************************/
+/*                                                                            */
+/*                           Real-Time Clock (RTC)                            */
+/*                                                                            */
+/******************************************************************************/
+/*
+ * @brief Specific device feature definitions  (not present on all devices in the STM32F4 serie)
+ */
+#define RTC_TAMPER2_SUPPORT  /*!< TAMPER 2 feature support */
+#define RTC_AF2_SUPPORT /*!< RTC Alternate Function 2 mapping support */
+/********************  Bits definition for RTC_TR register  *******************/
+#define RTC_TR_PM_Pos                 (22U)                                    
+#define RTC_TR_PM_Msk                 (0x1UL << RTC_TR_PM_Pos)                  /*!< 0x00400000 */
+#define RTC_TR_PM                     RTC_TR_PM_Msk                            
+#define RTC_TR_HT_Pos                 (20U)                                    
+#define RTC_TR_HT_Msk                 (0x3UL << RTC_TR_HT_Pos)                  /*!< 0x00300000 */
+#define RTC_TR_HT                     RTC_TR_HT_Msk                            
+#define RTC_TR_HT_0                   (0x1UL << RTC_TR_HT_Pos)                  /*!< 0x00100000 */
+#define RTC_TR_HT_1                   (0x2UL << RTC_TR_HT_Pos)                  /*!< 0x00200000 */
+#define RTC_TR_HU_Pos                 (16U)                                    
+#define RTC_TR_HU_Msk                 (0xFUL << RTC_TR_HU_Pos)                  /*!< 0x000F0000 */
+#define RTC_TR_HU                     RTC_TR_HU_Msk                            
+#define RTC_TR_HU_0                   (0x1UL << RTC_TR_HU_Pos)                  /*!< 0x00010000 */
+#define RTC_TR_HU_1                   (0x2UL << RTC_TR_HU_Pos)                  /*!< 0x00020000 */
+#define RTC_TR_HU_2                   (0x4UL << RTC_TR_HU_Pos)                  /*!< 0x00040000 */
+#define RTC_TR_HU_3                   (0x8UL << RTC_TR_HU_Pos)                  /*!< 0x00080000 */
+#define RTC_TR_MNT_Pos                (12U)                                    
+#define RTC_TR_MNT_Msk                (0x7UL << RTC_TR_MNT_Pos)                 /*!< 0x00007000 */
+#define RTC_TR_MNT                    RTC_TR_MNT_Msk                           
+#define RTC_TR_MNT_0                  (0x1UL << RTC_TR_MNT_Pos)                 /*!< 0x00001000 */
+#define RTC_TR_MNT_1                  (0x2UL << RTC_TR_MNT_Pos)                 /*!< 0x00002000 */
+#define RTC_TR_MNT_2                  (0x4UL << RTC_TR_MNT_Pos)                 /*!< 0x00004000 */
+#define RTC_TR_MNU_Pos                (8U)                                     
+#define RTC_TR_MNU_Msk                (0xFUL << RTC_TR_MNU_Pos)                 /*!< 0x00000F00 */
+#define RTC_TR_MNU                    RTC_TR_MNU_Msk                           
+#define RTC_TR_MNU_0                  (0x1UL << RTC_TR_MNU_Pos)                 /*!< 0x00000100 */
+#define RTC_TR_MNU_1                  (0x2UL << RTC_TR_MNU_Pos)                 /*!< 0x00000200 */
+#define RTC_TR_MNU_2                  (0x4UL << RTC_TR_MNU_Pos)                 /*!< 0x00000400 */
+#define RTC_TR_MNU_3                  (0x8UL << RTC_TR_MNU_Pos)                 /*!< 0x00000800 */
+#define RTC_TR_ST_Pos                 (4U)                                     
+#define RTC_TR_ST_Msk                 (0x7UL << RTC_TR_ST_Pos)                  /*!< 0x00000070 */
+#define RTC_TR_ST                     RTC_TR_ST_Msk                            
+#define RTC_TR_ST_0                   (0x1UL << RTC_TR_ST_Pos)                  /*!< 0x00000010 */
+#define RTC_TR_ST_1                   (0x2UL << RTC_TR_ST_Pos)                  /*!< 0x00000020 */
+#define RTC_TR_ST_2                   (0x4UL << RTC_TR_ST_Pos)                  /*!< 0x00000040 */
+#define RTC_TR_SU_Pos                 (0U)                                     
+#define RTC_TR_SU_Msk                 (0xFUL << RTC_TR_SU_Pos)                  /*!< 0x0000000F */
+#define RTC_TR_SU                     RTC_TR_SU_Msk                            
+#define RTC_TR_SU_0                   (0x1UL << RTC_TR_SU_Pos)                  /*!< 0x00000001 */
+#define RTC_TR_SU_1                   (0x2UL << RTC_TR_SU_Pos)                  /*!< 0x00000002 */
+#define RTC_TR_SU_2                   (0x4UL << RTC_TR_SU_Pos)                  /*!< 0x00000004 */
+#define RTC_TR_SU_3                   (0x8UL << RTC_TR_SU_Pos)                  /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_DR register  *******************/
+#define RTC_DR_YT_Pos                 (20U)                                    
+#define RTC_DR_YT_Msk                 (0xFUL << RTC_DR_YT_Pos)                  /*!< 0x00F00000 */
+#define RTC_DR_YT                     RTC_DR_YT_Msk                            
+#define RTC_DR_YT_0                   (0x1UL << RTC_DR_YT_Pos)                  /*!< 0x00100000 */
+#define RTC_DR_YT_1                   (0x2UL << RTC_DR_YT_Pos)                  /*!< 0x00200000 */
+#define RTC_DR_YT_2                   (0x4UL << RTC_DR_YT_Pos)                  /*!< 0x00400000 */
+#define RTC_DR_YT_3                   (0x8UL << RTC_DR_YT_Pos)                  /*!< 0x00800000 */
+#define RTC_DR_YU_Pos                 (16U)                                    
+#define RTC_DR_YU_Msk                 (0xFUL << RTC_DR_YU_Pos)                  /*!< 0x000F0000 */
+#define RTC_DR_YU                     RTC_DR_YU_Msk                            
+#define RTC_DR_YU_0                   (0x1UL << RTC_DR_YU_Pos)                  /*!< 0x00010000 */
+#define RTC_DR_YU_1                   (0x2UL << RTC_DR_YU_Pos)                  /*!< 0x00020000 */
+#define RTC_DR_YU_2                   (0x4UL << RTC_DR_YU_Pos)                  /*!< 0x00040000 */
+#define RTC_DR_YU_3                   (0x8UL << RTC_DR_YU_Pos)                  /*!< 0x00080000 */
+#define RTC_DR_WDU_Pos                (13U)                                    
+#define RTC_DR_WDU_Msk                (0x7UL << RTC_DR_WDU_Pos)                 /*!< 0x0000E000 */
+#define RTC_DR_WDU                    RTC_DR_WDU_Msk                           
+#define RTC_DR_WDU_0                  (0x1UL << RTC_DR_WDU_Pos)                 /*!< 0x00002000 */
+#define RTC_DR_WDU_1                  (0x2UL << RTC_DR_WDU_Pos)                 /*!< 0x00004000 */
+#define RTC_DR_WDU_2                  (0x4UL << RTC_DR_WDU_Pos)                 /*!< 0x00008000 */
+#define RTC_DR_MT_Pos                 (12U)                                    
+#define RTC_DR_MT_Msk                 (0x1UL << RTC_DR_MT_Pos)                  /*!< 0x00001000 */
+#define RTC_DR_MT                     RTC_DR_MT_Msk                            
+#define RTC_DR_MU_Pos                 (8U)                                     
+#define RTC_DR_MU_Msk                 (0xFUL << RTC_DR_MU_Pos)                  /*!< 0x00000F00 */
+#define RTC_DR_MU                     RTC_DR_MU_Msk                            
+#define RTC_DR_MU_0                   (0x1UL << RTC_DR_MU_Pos)                  /*!< 0x00000100 */
+#define RTC_DR_MU_1                   (0x2UL << RTC_DR_MU_Pos)                  /*!< 0x00000200 */
+#define RTC_DR_MU_2                   (0x4UL << RTC_DR_MU_Pos)                  /*!< 0x00000400 */
+#define RTC_DR_MU_3                   (0x8UL << RTC_DR_MU_Pos)                  /*!< 0x00000800 */
+#define RTC_DR_DT_Pos                 (4U)                                     
+#define RTC_DR_DT_Msk                 (0x3UL << RTC_DR_DT_Pos)                  /*!< 0x00000030 */
+#define RTC_DR_DT                     RTC_DR_DT_Msk                            
+#define RTC_DR_DT_0                   (0x1UL << RTC_DR_DT_Pos)                  /*!< 0x00000010 */
+#define RTC_DR_DT_1                   (0x2UL << RTC_DR_DT_Pos)                  /*!< 0x00000020 */
+#define RTC_DR_DU_Pos                 (0U)                                     
+#define RTC_DR_DU_Msk                 (0xFUL << RTC_DR_DU_Pos)                  /*!< 0x0000000F */
+#define RTC_DR_DU                     RTC_DR_DU_Msk                            
+#define RTC_DR_DU_0                   (0x1UL << RTC_DR_DU_Pos)                  /*!< 0x00000001 */
+#define RTC_DR_DU_1                   (0x2UL << RTC_DR_DU_Pos)                  /*!< 0x00000002 */
+#define RTC_DR_DU_2                   (0x4UL << RTC_DR_DU_Pos)                  /*!< 0x00000004 */
+#define RTC_DR_DU_3                   (0x8UL << RTC_DR_DU_Pos)                  /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_CR register  *******************/
+#define RTC_CR_COE_Pos                (23U)                                    
+#define RTC_CR_COE_Msk                (0x1UL << RTC_CR_COE_Pos)                 /*!< 0x00800000 */
+#define RTC_CR_COE                    RTC_CR_COE_Msk                           
+#define RTC_CR_OSEL_Pos               (21U)                                    
+#define RTC_CR_OSEL_Msk               (0x3UL << RTC_CR_OSEL_Pos)                /*!< 0x00600000 */
+#define RTC_CR_OSEL                   RTC_CR_OSEL_Msk                          
+#define RTC_CR_OSEL_0                 (0x1UL << RTC_CR_OSEL_Pos)                /*!< 0x00200000 */
+#define RTC_CR_OSEL_1                 (0x2UL << RTC_CR_OSEL_Pos)                /*!< 0x00400000 */
+#define RTC_CR_POL_Pos                (20U)                                    
+#define RTC_CR_POL_Msk                (0x1UL << RTC_CR_POL_Pos)                 /*!< 0x00100000 */
+#define RTC_CR_POL                    RTC_CR_POL_Msk                           
+#define RTC_CR_COSEL_Pos              (19U)                                    
+#define RTC_CR_COSEL_Msk              (0x1UL << RTC_CR_COSEL_Pos)               /*!< 0x00080000 */
+#define RTC_CR_COSEL                  RTC_CR_COSEL_Msk                         
+#define RTC_CR_BKP_Pos                 (18U)                                   
+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)                /*!< 0x00040000 */
+#define RTC_CR_BKP                     RTC_CR_BKP_Msk                          
+#define RTC_CR_SUB1H_Pos              (17U)                                    
+#define RTC_CR_SUB1H_Msk              (0x1UL << RTC_CR_SUB1H_Pos)               /*!< 0x00020000 */
+#define RTC_CR_SUB1H                  RTC_CR_SUB1H_Msk                         
+#define RTC_CR_ADD1H_Pos              (16U)                                    
+#define RTC_CR_ADD1H_Msk              (0x1UL << RTC_CR_ADD1H_Pos)               /*!< 0x00010000 */
+#define RTC_CR_ADD1H                  RTC_CR_ADD1H_Msk                         
+#define RTC_CR_TSIE_Pos               (15U)                                    
+#define RTC_CR_TSIE_Msk               (0x1UL << RTC_CR_TSIE_Pos)                /*!< 0x00008000 */
+#define RTC_CR_TSIE                   RTC_CR_TSIE_Msk                          
+#define RTC_CR_WUTIE_Pos              (14U)                                    
+#define RTC_CR_WUTIE_Msk              (0x1UL << RTC_CR_WUTIE_Pos)               /*!< 0x00004000 */
+#define RTC_CR_WUTIE                  RTC_CR_WUTIE_Msk                         
+#define RTC_CR_ALRBIE_Pos             (13U)                                    
+#define RTC_CR_ALRBIE_Msk             (0x1UL << RTC_CR_ALRBIE_Pos)              /*!< 0x00002000 */
+#define RTC_CR_ALRBIE                 RTC_CR_ALRBIE_Msk                        
+#define RTC_CR_ALRAIE_Pos             (12U)                                    
+#define RTC_CR_ALRAIE_Msk             (0x1UL << RTC_CR_ALRAIE_Pos)              /*!< 0x00001000 */
+#define RTC_CR_ALRAIE                 RTC_CR_ALRAIE_Msk                        
+#define RTC_CR_TSE_Pos                (11U)                                    
+#define RTC_CR_TSE_Msk                (0x1UL << RTC_CR_TSE_Pos)                 /*!< 0x00000800 */
+#define RTC_CR_TSE                    RTC_CR_TSE_Msk                           
+#define RTC_CR_WUTE_Pos               (10U)                                    
+#define RTC_CR_WUTE_Msk               (0x1UL << RTC_CR_WUTE_Pos)                /*!< 0x00000400 */
+#define RTC_CR_WUTE                   RTC_CR_WUTE_Msk                          
+#define RTC_CR_ALRBE_Pos              (9U)                                     
+#define RTC_CR_ALRBE_Msk              (0x1UL << RTC_CR_ALRBE_Pos)               /*!< 0x00000200 */
+#define RTC_CR_ALRBE                  RTC_CR_ALRBE_Msk                         
+#define RTC_CR_ALRAE_Pos              (8U)                                     
+#define RTC_CR_ALRAE_Msk              (0x1UL << RTC_CR_ALRAE_Pos)               /*!< 0x00000100 */
+#define RTC_CR_ALRAE                  RTC_CR_ALRAE_Msk                         
+#define RTC_CR_DCE_Pos                (7U)                                     
+#define RTC_CR_DCE_Msk                (0x1UL << RTC_CR_DCE_Pos)                 /*!< 0x00000080 */
+#define RTC_CR_DCE                    RTC_CR_DCE_Msk                           
+#define RTC_CR_FMT_Pos                (6U)                                     
+#define RTC_CR_FMT_Msk                (0x1UL << RTC_CR_FMT_Pos)                 /*!< 0x00000040 */
+#define RTC_CR_FMT                    RTC_CR_FMT_Msk                           
+#define RTC_CR_BYPSHAD_Pos            (5U)                                     
+#define RTC_CR_BYPSHAD_Msk            (0x1UL << RTC_CR_BYPSHAD_Pos)             /*!< 0x00000020 */
+#define RTC_CR_BYPSHAD                RTC_CR_BYPSHAD_Msk                       
+#define RTC_CR_REFCKON_Pos            (4U)                                     
+#define RTC_CR_REFCKON_Msk            (0x1UL << RTC_CR_REFCKON_Pos)             /*!< 0x00000010 */
+#define RTC_CR_REFCKON                RTC_CR_REFCKON_Msk                       
+#define RTC_CR_TSEDGE_Pos             (3U)                                     
+#define RTC_CR_TSEDGE_Msk             (0x1UL << RTC_CR_TSEDGE_Pos)              /*!< 0x00000008 */
+#define RTC_CR_TSEDGE                 RTC_CR_TSEDGE_Msk                        
+#define RTC_CR_WUCKSEL_Pos            (0U)                                     
+#define RTC_CR_WUCKSEL_Msk            (0x7UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000007 */
+#define RTC_CR_WUCKSEL                RTC_CR_WUCKSEL_Msk                       
+#define RTC_CR_WUCKSEL_0              (0x1UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000001 */
+#define RTC_CR_WUCKSEL_1              (0x2UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000002 */
+#define RTC_CR_WUCKSEL_2              (0x4UL << RTC_CR_WUCKSEL_Pos)             /*!< 0x00000004 */
+
+/* Legacy defines */
+#define RTC_CR_BCK                     RTC_CR_BKP
+
+/********************  Bits definition for RTC_ISR register  ******************/
+#define RTC_ISR_RECALPF_Pos           (16U)                                    
+#define RTC_ISR_RECALPF_Msk           (0x1UL << RTC_ISR_RECALPF_Pos)            /*!< 0x00010000 */
+#define RTC_ISR_RECALPF               RTC_ISR_RECALPF_Msk                      
+#define RTC_ISR_TAMP1F_Pos            (13U)                                    
+#define RTC_ISR_TAMP1F_Msk            (0x1UL << RTC_ISR_TAMP1F_Pos)             /*!< 0x00002000 */
+#define RTC_ISR_TAMP1F                RTC_ISR_TAMP1F_Msk                       
+#define RTC_ISR_TAMP2F_Pos            (14U)                                    
+#define RTC_ISR_TAMP2F_Msk            (0x1UL << RTC_ISR_TAMP2F_Pos)             /*!< 0x00004000 */
+#define RTC_ISR_TAMP2F                RTC_ISR_TAMP2F_Msk                       
+#define RTC_ISR_TSOVF_Pos             (12U)                                    
+#define RTC_ISR_TSOVF_Msk             (0x1UL << RTC_ISR_TSOVF_Pos)              /*!< 0x00001000 */
+#define RTC_ISR_TSOVF                 RTC_ISR_TSOVF_Msk                        
+#define RTC_ISR_TSF_Pos               (11U)                                    
+#define RTC_ISR_TSF_Msk               (0x1UL << RTC_ISR_TSF_Pos)                /*!< 0x00000800 */
+#define RTC_ISR_TSF                   RTC_ISR_TSF_Msk                          
+#define RTC_ISR_WUTF_Pos              (10U)                                    
+#define RTC_ISR_WUTF_Msk              (0x1UL << RTC_ISR_WUTF_Pos)               /*!< 0x00000400 */
+#define RTC_ISR_WUTF                  RTC_ISR_WUTF_Msk                         
+#define RTC_ISR_ALRBF_Pos             (9U)                                     
+#define RTC_ISR_ALRBF_Msk             (0x1UL << RTC_ISR_ALRBF_Pos)              /*!< 0x00000200 */
+#define RTC_ISR_ALRBF                 RTC_ISR_ALRBF_Msk                        
+#define RTC_ISR_ALRAF_Pos             (8U)                                     
+#define RTC_ISR_ALRAF_Msk             (0x1UL << RTC_ISR_ALRAF_Pos)              /*!< 0x00000100 */
+#define RTC_ISR_ALRAF                 RTC_ISR_ALRAF_Msk                        
+#define RTC_ISR_INIT_Pos              (7U)                                     
+#define RTC_ISR_INIT_Msk              (0x1UL << RTC_ISR_INIT_Pos)               /*!< 0x00000080 */
+#define RTC_ISR_INIT                  RTC_ISR_INIT_Msk                         
+#define RTC_ISR_INITF_Pos             (6U)                                     
+#define RTC_ISR_INITF_Msk             (0x1UL << RTC_ISR_INITF_Pos)              /*!< 0x00000040 */
+#define RTC_ISR_INITF                 RTC_ISR_INITF_Msk                        
+#define RTC_ISR_RSF_Pos               (5U)                                     
+#define RTC_ISR_RSF_Msk               (0x1UL << RTC_ISR_RSF_Pos)                /*!< 0x00000020 */
+#define RTC_ISR_RSF                   RTC_ISR_RSF_Msk                          
+#define RTC_ISR_INITS_Pos             (4U)                                     
+#define RTC_ISR_INITS_Msk             (0x1UL << RTC_ISR_INITS_Pos)              /*!< 0x00000010 */
+#define RTC_ISR_INITS                 RTC_ISR_INITS_Msk                        
+#define RTC_ISR_SHPF_Pos              (3U)                                     
+#define RTC_ISR_SHPF_Msk              (0x1UL << RTC_ISR_SHPF_Pos)               /*!< 0x00000008 */
+#define RTC_ISR_SHPF                  RTC_ISR_SHPF_Msk                         
+#define RTC_ISR_WUTWF_Pos             (2U)                                     
+#define RTC_ISR_WUTWF_Msk             (0x1UL << RTC_ISR_WUTWF_Pos)              /*!< 0x00000004 */
+#define RTC_ISR_WUTWF                 RTC_ISR_WUTWF_Msk                        
+#define RTC_ISR_ALRBWF_Pos            (1U)                                     
+#define RTC_ISR_ALRBWF_Msk            (0x1UL << RTC_ISR_ALRBWF_Pos)             /*!< 0x00000002 */
+#define RTC_ISR_ALRBWF                RTC_ISR_ALRBWF_Msk                       
+#define RTC_ISR_ALRAWF_Pos            (0U)                                     
+#define RTC_ISR_ALRAWF_Msk            (0x1UL << RTC_ISR_ALRAWF_Pos)             /*!< 0x00000001 */
+#define RTC_ISR_ALRAWF                RTC_ISR_ALRAWF_Msk                       
+
+/********************  Bits definition for RTC_PRER register  *****************/
+#define RTC_PRER_PREDIV_A_Pos         (16U)                                    
+#define RTC_PRER_PREDIV_A_Msk         (0x7FUL << RTC_PRER_PREDIV_A_Pos)         /*!< 0x007F0000 */
+#define RTC_PRER_PREDIV_A             RTC_PRER_PREDIV_A_Msk                    
+#define RTC_PRER_PREDIV_S_Pos         (0U)                                     
+#define RTC_PRER_PREDIV_S_Msk         (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)       /*!< 0x00007FFF */
+#define RTC_PRER_PREDIV_S             RTC_PRER_PREDIV_S_Msk                    
+
+/********************  Bits definition for RTC_WUTR register  *****************/
+#define RTC_WUTR_WUT_Pos              (0U)                                     
+#define RTC_WUTR_WUT_Msk              (0xFFFFUL << RTC_WUTR_WUT_Pos)            /*!< 0x0000FFFF */
+#define RTC_WUTR_WUT                  RTC_WUTR_WUT_Msk                         
+
+/********************  Bits definition for RTC_CALIBR register  ***************/
+#define RTC_CALIBR_DCS_Pos            (7U)                                     
+#define RTC_CALIBR_DCS_Msk            (0x1UL << RTC_CALIBR_DCS_Pos)             /*!< 0x00000080 */
+#define RTC_CALIBR_DCS                RTC_CALIBR_DCS_Msk                       
+#define RTC_CALIBR_DC_Pos             (0U)                                     
+#define RTC_CALIBR_DC_Msk             (0x1FUL << RTC_CALIBR_DC_Pos)             /*!< 0x0000001F */
+#define RTC_CALIBR_DC                 RTC_CALIBR_DC_Msk                        
+
+/********************  Bits definition for RTC_ALRMAR register  ***************/
+#define RTC_ALRMAR_MSK4_Pos           (31U)                                    
+#define RTC_ALRMAR_MSK4_Msk           (0x1UL << RTC_ALRMAR_MSK4_Pos)            /*!< 0x80000000 */
+#define RTC_ALRMAR_MSK4               RTC_ALRMAR_MSK4_Msk                      
+#define RTC_ALRMAR_WDSEL_Pos          (30U)                                    
+#define RTC_ALRMAR_WDSEL_Msk          (0x1UL << RTC_ALRMAR_WDSEL_Pos)           /*!< 0x40000000 */
+#define RTC_ALRMAR_WDSEL              RTC_ALRMAR_WDSEL_Msk                     
+#define RTC_ALRMAR_DT_Pos             (28U)                                    
+#define RTC_ALRMAR_DT_Msk             (0x3UL << RTC_ALRMAR_DT_Pos)              /*!< 0x30000000 */
+#define RTC_ALRMAR_DT                 RTC_ALRMAR_DT_Msk                        
+#define RTC_ALRMAR_DT_0               (0x1UL << RTC_ALRMAR_DT_Pos)              /*!< 0x10000000 */
+#define RTC_ALRMAR_DT_1               (0x2UL << RTC_ALRMAR_DT_Pos)              /*!< 0x20000000 */
+#define RTC_ALRMAR_DU_Pos             (24U)                                    
+#define RTC_ALRMAR_DU_Msk             (0xFUL << RTC_ALRMAR_DU_Pos)              /*!< 0x0F000000 */
+#define RTC_ALRMAR_DU                 RTC_ALRMAR_DU_Msk                        
+#define RTC_ALRMAR_DU_0               (0x1UL << RTC_ALRMAR_DU_Pos)              /*!< 0x01000000 */
+#define RTC_ALRMAR_DU_1               (0x2UL << RTC_ALRMAR_DU_Pos)              /*!< 0x02000000 */
+#define RTC_ALRMAR_DU_2               (0x4UL << RTC_ALRMAR_DU_Pos)              /*!< 0x04000000 */
+#define RTC_ALRMAR_DU_3               (0x8UL << RTC_ALRMAR_DU_Pos)              /*!< 0x08000000 */
+#define RTC_ALRMAR_MSK3_Pos           (23U)                                    
+#define RTC_ALRMAR_MSK3_Msk           (0x1UL << RTC_ALRMAR_MSK3_Pos)            /*!< 0x00800000 */
+#define RTC_ALRMAR_MSK3               RTC_ALRMAR_MSK3_Msk                      
+#define RTC_ALRMAR_PM_Pos             (22U)                                    
+#define RTC_ALRMAR_PM_Msk             (0x1UL << RTC_ALRMAR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_ALRMAR_PM                 RTC_ALRMAR_PM_Msk                        
+#define RTC_ALRMAR_HT_Pos             (20U)                                    
+#define RTC_ALRMAR_HT_Msk             (0x3UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_ALRMAR_HT                 RTC_ALRMAR_HT_Msk                        
+#define RTC_ALRMAR_HT_0               (0x1UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00100000 */
+#define RTC_ALRMAR_HT_1               (0x2UL << RTC_ALRMAR_HT_Pos)              /*!< 0x00200000 */
+#define RTC_ALRMAR_HU_Pos             (16U)                                    
+#define RTC_ALRMAR_HU_Msk             (0xFUL << RTC_ALRMAR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_ALRMAR_HU                 RTC_ALRMAR_HU_Msk                        
+#define RTC_ALRMAR_HU_0               (0x1UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00010000 */
+#define RTC_ALRMAR_HU_1               (0x2UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00020000 */
+#define RTC_ALRMAR_HU_2               (0x4UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00040000 */
+#define RTC_ALRMAR_HU_3               (0x8UL << RTC_ALRMAR_HU_Pos)              /*!< 0x00080000 */
+#define RTC_ALRMAR_MSK2_Pos           (15U)                                    
+#define RTC_ALRMAR_MSK2_Msk           (0x1UL << RTC_ALRMAR_MSK2_Pos)            /*!< 0x00008000 */
+#define RTC_ALRMAR_MSK2               RTC_ALRMAR_MSK2_Msk                      
+#define RTC_ALRMAR_MNT_Pos            (12U)                                    
+#define RTC_ALRMAR_MNT_Msk            (0x7UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_ALRMAR_MNT                RTC_ALRMAR_MNT_Msk                       
+#define RTC_ALRMAR_MNT_0              (0x1UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00001000 */
+#define RTC_ALRMAR_MNT_1              (0x2UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00002000 */
+#define RTC_ALRMAR_MNT_2              (0x4UL << RTC_ALRMAR_MNT_Pos)             /*!< 0x00004000 */
+#define RTC_ALRMAR_MNU_Pos            (8U)                                     
+#define RTC_ALRMAR_MNU_Msk            (0xFUL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_ALRMAR_MNU                RTC_ALRMAR_MNU_Msk                       
+#define RTC_ALRMAR_MNU_0              (0x1UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000100 */
+#define RTC_ALRMAR_MNU_1              (0x2UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000200 */
+#define RTC_ALRMAR_MNU_2              (0x4UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000400 */
+#define RTC_ALRMAR_MNU_3              (0x8UL << RTC_ALRMAR_MNU_Pos)             /*!< 0x00000800 */
+#define RTC_ALRMAR_MSK1_Pos           (7U)                                     
+#define RTC_ALRMAR_MSK1_Msk           (0x1UL << RTC_ALRMAR_MSK1_Pos)            /*!< 0x00000080 */
+#define RTC_ALRMAR_MSK1               RTC_ALRMAR_MSK1_Msk                      
+#define RTC_ALRMAR_ST_Pos             (4U)                                     
+#define RTC_ALRMAR_ST_Msk             (0x7UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_ALRMAR_ST                 RTC_ALRMAR_ST_Msk                        
+#define RTC_ALRMAR_ST_0               (0x1UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000010 */
+#define RTC_ALRMAR_ST_1               (0x2UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000020 */
+#define RTC_ALRMAR_ST_2               (0x4UL << RTC_ALRMAR_ST_Pos)              /*!< 0x00000040 */
+#define RTC_ALRMAR_SU_Pos             (0U)                                     
+#define RTC_ALRMAR_SU_Msk             (0xFUL << RTC_ALRMAR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_ALRMAR_SU                 RTC_ALRMAR_SU_Msk                        
+#define RTC_ALRMAR_SU_0               (0x1UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000001 */
+#define RTC_ALRMAR_SU_1               (0x2UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000002 */
+#define RTC_ALRMAR_SU_2               (0x4UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000004 */
+#define RTC_ALRMAR_SU_3               (0x8UL << RTC_ALRMAR_SU_Pos)              /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_ALRMBR register  ***************/
+#define RTC_ALRMBR_MSK4_Pos           (31U)                                    
+#define RTC_ALRMBR_MSK4_Msk           (0x1UL << RTC_ALRMBR_MSK4_Pos)            /*!< 0x80000000 */
+#define RTC_ALRMBR_MSK4               RTC_ALRMBR_MSK4_Msk                      
+#define RTC_ALRMBR_WDSEL_Pos          (30U)                                    
+#define RTC_ALRMBR_WDSEL_Msk          (0x1UL << RTC_ALRMBR_WDSEL_Pos)           /*!< 0x40000000 */
+#define RTC_ALRMBR_WDSEL              RTC_ALRMBR_WDSEL_Msk                     
+#define RTC_ALRMBR_DT_Pos             (28U)                                    
+#define RTC_ALRMBR_DT_Msk             (0x3UL << RTC_ALRMBR_DT_Pos)              /*!< 0x30000000 */
+#define RTC_ALRMBR_DT                 RTC_ALRMBR_DT_Msk                        
+#define RTC_ALRMBR_DT_0               (0x1UL << RTC_ALRMBR_DT_Pos)              /*!< 0x10000000 */
+#define RTC_ALRMBR_DT_1               (0x2UL << RTC_ALRMBR_DT_Pos)              /*!< 0x20000000 */
+#define RTC_ALRMBR_DU_Pos             (24U)                                    
+#define RTC_ALRMBR_DU_Msk             (0xFUL << RTC_ALRMBR_DU_Pos)              /*!< 0x0F000000 */
+#define RTC_ALRMBR_DU                 RTC_ALRMBR_DU_Msk                        
+#define RTC_ALRMBR_DU_0               (0x1UL << RTC_ALRMBR_DU_Pos)              /*!< 0x01000000 */
+#define RTC_ALRMBR_DU_1               (0x2UL << RTC_ALRMBR_DU_Pos)              /*!< 0x02000000 */
+#define RTC_ALRMBR_DU_2               (0x4UL << RTC_ALRMBR_DU_Pos)              /*!< 0x04000000 */
+#define RTC_ALRMBR_DU_3               (0x8UL << RTC_ALRMBR_DU_Pos)              /*!< 0x08000000 */
+#define RTC_ALRMBR_MSK3_Pos           (23U)                                    
+#define RTC_ALRMBR_MSK3_Msk           (0x1UL << RTC_ALRMBR_MSK3_Pos)            /*!< 0x00800000 */
+#define RTC_ALRMBR_MSK3               RTC_ALRMBR_MSK3_Msk                      
+#define RTC_ALRMBR_PM_Pos             (22U)                                    
+#define RTC_ALRMBR_PM_Msk             (0x1UL << RTC_ALRMBR_PM_Pos)              /*!< 0x00400000 */
+#define RTC_ALRMBR_PM                 RTC_ALRMBR_PM_Msk                        
+#define RTC_ALRMBR_HT_Pos             (20U)                                    
+#define RTC_ALRMBR_HT_Msk             (0x3UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00300000 */
+#define RTC_ALRMBR_HT                 RTC_ALRMBR_HT_Msk                        
+#define RTC_ALRMBR_HT_0               (0x1UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00100000 */
+#define RTC_ALRMBR_HT_1               (0x2UL << RTC_ALRMBR_HT_Pos)              /*!< 0x00200000 */
+#define RTC_ALRMBR_HU_Pos             (16U)                                    
+#define RTC_ALRMBR_HU_Msk             (0xFUL << RTC_ALRMBR_HU_Pos)              /*!< 0x000F0000 */
+#define RTC_ALRMBR_HU                 RTC_ALRMBR_HU_Msk                        
+#define RTC_ALRMBR_HU_0               (0x1UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00010000 */
+#define RTC_ALRMBR_HU_1               (0x2UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00020000 */
+#define RTC_ALRMBR_HU_2               (0x4UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00040000 */
+#define RTC_ALRMBR_HU_3               (0x8UL << RTC_ALRMBR_HU_Pos)              /*!< 0x00080000 */
+#define RTC_ALRMBR_MSK2_Pos           (15U)                                    
+#define RTC_ALRMBR_MSK2_Msk           (0x1UL << RTC_ALRMBR_MSK2_Pos)            /*!< 0x00008000 */
+#define RTC_ALRMBR_MSK2               RTC_ALRMBR_MSK2_Msk                      
+#define RTC_ALRMBR_MNT_Pos            (12U)                                    
+#define RTC_ALRMBR_MNT_Msk            (0x7UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00007000 */
+#define RTC_ALRMBR_MNT                RTC_ALRMBR_MNT_Msk                       
+#define RTC_ALRMBR_MNT_0              (0x1UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00001000 */
+#define RTC_ALRMBR_MNT_1              (0x2UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00002000 */
+#define RTC_ALRMBR_MNT_2              (0x4UL << RTC_ALRMBR_MNT_Pos)             /*!< 0x00004000 */
+#define RTC_ALRMBR_MNU_Pos            (8U)                                     
+#define RTC_ALRMBR_MNU_Msk            (0xFUL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000F00 */
+#define RTC_ALRMBR_MNU                RTC_ALRMBR_MNU_Msk                       
+#define RTC_ALRMBR_MNU_0              (0x1UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000100 */
+#define RTC_ALRMBR_MNU_1              (0x2UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000200 */
+#define RTC_ALRMBR_MNU_2              (0x4UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000400 */
+#define RTC_ALRMBR_MNU_3              (0x8UL << RTC_ALRMBR_MNU_Pos)             /*!< 0x00000800 */
+#define RTC_ALRMBR_MSK1_Pos           (7U)                                     
+#define RTC_ALRMBR_MSK1_Msk           (0x1UL << RTC_ALRMBR_MSK1_Pos)            /*!< 0x00000080 */
+#define RTC_ALRMBR_MSK1               RTC_ALRMBR_MSK1_Msk                      
+#define RTC_ALRMBR_ST_Pos             (4U)                                     
+#define RTC_ALRMBR_ST_Msk             (0x7UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000070 */
+#define RTC_ALRMBR_ST                 RTC_ALRMBR_ST_Msk                        
+#define RTC_ALRMBR_ST_0               (0x1UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000010 */
+#define RTC_ALRMBR_ST_1               (0x2UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000020 */
+#define RTC_ALRMBR_ST_2               (0x4UL << RTC_ALRMBR_ST_Pos)              /*!< 0x00000040 */
+#define RTC_ALRMBR_SU_Pos             (0U)                                     
+#define RTC_ALRMBR_SU_Msk             (0xFUL << RTC_ALRMBR_SU_Pos)              /*!< 0x0000000F */
+#define RTC_ALRMBR_SU                 RTC_ALRMBR_SU_Msk                        
+#define RTC_ALRMBR_SU_0               (0x1UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000001 */
+#define RTC_ALRMBR_SU_1               (0x2UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000002 */
+#define RTC_ALRMBR_SU_2               (0x4UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000004 */
+#define RTC_ALRMBR_SU_3               (0x8UL << RTC_ALRMBR_SU_Pos)              /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_WPR register  ******************/
+#define RTC_WPR_KEY_Pos               (0U)                                     
+#define RTC_WPR_KEY_Msk               (0xFFUL << RTC_WPR_KEY_Pos)               /*!< 0x000000FF */
+#define RTC_WPR_KEY                   RTC_WPR_KEY_Msk                          
+
+/********************  Bits definition for RTC_SSR register  ******************/
+#define RTC_SSR_SS_Pos                (0U)                                     
+#define RTC_SSR_SS_Msk                (0xFFFFUL << RTC_SSR_SS_Pos)              /*!< 0x0000FFFF */
+#define RTC_SSR_SS                    RTC_SSR_SS_Msk                           
+
+/********************  Bits definition for RTC_SHIFTR register  ***************/
+#define RTC_SHIFTR_SUBFS_Pos          (0U)                                     
+#define RTC_SHIFTR_SUBFS_Msk          (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)        /*!< 0x00007FFF */
+#define RTC_SHIFTR_SUBFS              RTC_SHIFTR_SUBFS_Msk                     
+#define RTC_SHIFTR_ADD1S_Pos          (31U)                                    
+#define RTC_SHIFTR_ADD1S_Msk          (0x1UL << RTC_SHIFTR_ADD1S_Pos)           /*!< 0x80000000 */
+#define RTC_SHIFTR_ADD1S              RTC_SHIFTR_ADD1S_Msk                     
+
+/********************  Bits definition for RTC_TSTR register  *****************/
+#define RTC_TSTR_PM_Pos               (22U)                                    
+#define RTC_TSTR_PM_Msk               (0x1UL << RTC_TSTR_PM_Pos)                /*!< 0x00400000 */
+#define RTC_TSTR_PM                   RTC_TSTR_PM_Msk                          
+#define RTC_TSTR_HT_Pos               (20U)                                    
+#define RTC_TSTR_HT_Msk               (0x3UL << RTC_TSTR_HT_Pos)                /*!< 0x00300000 */
+#define RTC_TSTR_HT                   RTC_TSTR_HT_Msk                          
+#define RTC_TSTR_HT_0                 (0x1UL << RTC_TSTR_HT_Pos)                /*!< 0x00100000 */
+#define RTC_TSTR_HT_1                 (0x2UL << RTC_TSTR_HT_Pos)                /*!< 0x00200000 */
+#define RTC_TSTR_HU_Pos               (16U)                                    
+#define RTC_TSTR_HU_Msk               (0xFUL << RTC_TSTR_HU_Pos)                /*!< 0x000F0000 */
+#define RTC_TSTR_HU                   RTC_TSTR_HU_Msk                          
+#define RTC_TSTR_HU_0                 (0x1UL << RTC_TSTR_HU_Pos)                /*!< 0x00010000 */
+#define RTC_TSTR_HU_1                 (0x2UL << RTC_TSTR_HU_Pos)                /*!< 0x00020000 */
+#define RTC_TSTR_HU_2                 (0x4UL << RTC_TSTR_HU_Pos)                /*!< 0x00040000 */
+#define RTC_TSTR_HU_3                 (0x8UL << RTC_TSTR_HU_Pos)                /*!< 0x00080000 */
+#define RTC_TSTR_MNT_Pos              (12U)                                    
+#define RTC_TSTR_MNT_Msk              (0x7UL << RTC_TSTR_MNT_Pos)               /*!< 0x00007000 */
+#define RTC_TSTR_MNT                  RTC_TSTR_MNT_Msk                         
+#define RTC_TSTR_MNT_0                (0x1UL << RTC_TSTR_MNT_Pos)               /*!< 0x00001000 */
+#define RTC_TSTR_MNT_1                (0x2UL << RTC_TSTR_MNT_Pos)               /*!< 0x00002000 */
+#define RTC_TSTR_MNT_2                (0x4UL << RTC_TSTR_MNT_Pos)               /*!< 0x00004000 */
+#define RTC_TSTR_MNU_Pos              (8U)                                     
+#define RTC_TSTR_MNU_Msk              (0xFUL << RTC_TSTR_MNU_Pos)               /*!< 0x00000F00 */
+#define RTC_TSTR_MNU                  RTC_TSTR_MNU_Msk                         
+#define RTC_TSTR_MNU_0                (0x1UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000100 */
+#define RTC_TSTR_MNU_1                (0x2UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000200 */
+#define RTC_TSTR_MNU_2                (0x4UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000400 */
+#define RTC_TSTR_MNU_3                (0x8UL << RTC_TSTR_MNU_Pos)               /*!< 0x00000800 */
+#define RTC_TSTR_ST_Pos               (4U)                                     
+#define RTC_TSTR_ST_Msk               (0x7UL << RTC_TSTR_ST_Pos)                /*!< 0x00000070 */
+#define RTC_TSTR_ST                   RTC_TSTR_ST_Msk                          
+#define RTC_TSTR_ST_0                 (0x1UL << RTC_TSTR_ST_Pos)                /*!< 0x00000010 */
+#define RTC_TSTR_ST_1                 (0x2UL << RTC_TSTR_ST_Pos)                /*!< 0x00000020 */
+#define RTC_TSTR_ST_2                 (0x4UL << RTC_TSTR_ST_Pos)                /*!< 0x00000040 */
+#define RTC_TSTR_SU_Pos               (0U)                                     
+#define RTC_TSTR_SU_Msk               (0xFUL << RTC_TSTR_SU_Pos)                /*!< 0x0000000F */
+#define RTC_TSTR_SU                   RTC_TSTR_SU_Msk                          
+#define RTC_TSTR_SU_0                 (0x1UL << RTC_TSTR_SU_Pos)                /*!< 0x00000001 */
+#define RTC_TSTR_SU_1                 (0x2UL << RTC_TSTR_SU_Pos)                /*!< 0x00000002 */
+#define RTC_TSTR_SU_2                 (0x4UL << RTC_TSTR_SU_Pos)                /*!< 0x00000004 */
+#define RTC_TSTR_SU_3                 (0x8UL << RTC_TSTR_SU_Pos)                /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSDR register  *****************/
+#define RTC_TSDR_WDU_Pos              (13U)                                    
+#define RTC_TSDR_WDU_Msk              (0x7UL << RTC_TSDR_WDU_Pos)               /*!< 0x0000E000 */
+#define RTC_TSDR_WDU                  RTC_TSDR_WDU_Msk                         
+#define RTC_TSDR_WDU_0                (0x1UL << RTC_TSDR_WDU_Pos)               /*!< 0x00002000 */
+#define RTC_TSDR_WDU_1                (0x2UL << RTC_TSDR_WDU_Pos)               /*!< 0x00004000 */
+#define RTC_TSDR_WDU_2                (0x4UL << RTC_TSDR_WDU_Pos)               /*!< 0x00008000 */
+#define RTC_TSDR_MT_Pos               (12U)                                    
+#define RTC_TSDR_MT_Msk               (0x1UL << RTC_TSDR_MT_Pos)                /*!< 0x00001000 */
+#define RTC_TSDR_MT                   RTC_TSDR_MT_Msk                          
+#define RTC_TSDR_MU_Pos               (8U)                                     
+#define RTC_TSDR_MU_Msk               (0xFUL << RTC_TSDR_MU_Pos)                /*!< 0x00000F00 */
+#define RTC_TSDR_MU                   RTC_TSDR_MU_Msk                          
+#define RTC_TSDR_MU_0                 (0x1UL << RTC_TSDR_MU_Pos)                /*!< 0x00000100 */
+#define RTC_TSDR_MU_1                 (0x2UL << RTC_TSDR_MU_Pos)                /*!< 0x00000200 */
+#define RTC_TSDR_MU_2                 (0x4UL << RTC_TSDR_MU_Pos)                /*!< 0x00000400 */
+#define RTC_TSDR_MU_3                 (0x8UL << RTC_TSDR_MU_Pos)                /*!< 0x00000800 */
+#define RTC_TSDR_DT_Pos               (4U)                                     
+#define RTC_TSDR_DT_Msk               (0x3UL << RTC_TSDR_DT_Pos)                /*!< 0x00000030 */
+#define RTC_TSDR_DT                   RTC_TSDR_DT_Msk                          
+#define RTC_TSDR_DT_0                 (0x1UL << RTC_TSDR_DT_Pos)                /*!< 0x00000010 */
+#define RTC_TSDR_DT_1                 (0x2UL << RTC_TSDR_DT_Pos)                /*!< 0x00000020 */
+#define RTC_TSDR_DU_Pos               (0U)                                     
+#define RTC_TSDR_DU_Msk               (0xFUL << RTC_TSDR_DU_Pos)                /*!< 0x0000000F */
+#define RTC_TSDR_DU                   RTC_TSDR_DU_Msk                          
+#define RTC_TSDR_DU_0                 (0x1UL << RTC_TSDR_DU_Pos)                /*!< 0x00000001 */
+#define RTC_TSDR_DU_1                 (0x2UL << RTC_TSDR_DU_Pos)                /*!< 0x00000002 */
+#define RTC_TSDR_DU_2                 (0x4UL << RTC_TSDR_DU_Pos)                /*!< 0x00000004 */
+#define RTC_TSDR_DU_3                 (0x8UL << RTC_TSDR_DU_Pos)                /*!< 0x00000008 */
+
+/********************  Bits definition for RTC_TSSSR register  ****************/
+#define RTC_TSSSR_SS_Pos              (0U)                                     
+#define RTC_TSSSR_SS_Msk              (0xFFFFUL << RTC_TSSSR_SS_Pos)            /*!< 0x0000FFFF */
+#define RTC_TSSSR_SS                  RTC_TSSSR_SS_Msk                         
+
+/********************  Bits definition for RTC_CAL register  *****************/
+#define RTC_CALR_CALP_Pos             (15U)                                    
+#define RTC_CALR_CALP_Msk             (0x1UL << RTC_CALR_CALP_Pos)              /*!< 0x00008000 */
+#define RTC_CALR_CALP                 RTC_CALR_CALP_Msk                        
+#define RTC_CALR_CALW8_Pos            (14U)                                    
+#define RTC_CALR_CALW8_Msk            (0x1UL << RTC_CALR_CALW8_Pos)             /*!< 0x00004000 */
+#define RTC_CALR_CALW8                RTC_CALR_CALW8_Msk                       
+#define RTC_CALR_CALW16_Pos           (13U)                                    
+#define RTC_CALR_CALW16_Msk           (0x1UL << RTC_CALR_CALW16_Pos)            /*!< 0x00002000 */
+#define RTC_CALR_CALW16               RTC_CALR_CALW16_Msk                      
+#define RTC_CALR_CALM_Pos             (0U)                                     
+#define RTC_CALR_CALM_Msk             (0x1FFUL << RTC_CALR_CALM_Pos)            /*!< 0x000001FF */
+#define RTC_CALR_CALM                 RTC_CALR_CALM_Msk                        
+#define RTC_CALR_CALM_0               (0x001UL << RTC_CALR_CALM_Pos)            /*!< 0x00000001 */
+#define RTC_CALR_CALM_1               (0x002UL << RTC_CALR_CALM_Pos)            /*!< 0x00000002 */
+#define RTC_CALR_CALM_2               (0x004UL << RTC_CALR_CALM_Pos)            /*!< 0x00000004 */
+#define RTC_CALR_CALM_3               (0x008UL << RTC_CALR_CALM_Pos)            /*!< 0x00000008 */
+#define RTC_CALR_CALM_4               (0x010UL << RTC_CALR_CALM_Pos)            /*!< 0x00000010 */
+#define RTC_CALR_CALM_5               (0x020UL << RTC_CALR_CALM_Pos)            /*!< 0x00000020 */
+#define RTC_CALR_CALM_6               (0x040UL << RTC_CALR_CALM_Pos)            /*!< 0x00000040 */
+#define RTC_CALR_CALM_7               (0x080UL << RTC_CALR_CALM_Pos)            /*!< 0x00000080 */
+#define RTC_CALR_CALM_8               (0x100UL << RTC_CALR_CALM_Pos)            /*!< 0x00000100 */
+
+/********************  Bits definition for RTC_TAFCR register  ****************/
+#define RTC_TAFCR_ALARMOUTTYPE_Pos    (18U)                                    
+#define RTC_TAFCR_ALARMOUTTYPE_Msk    (0x1UL << RTC_TAFCR_ALARMOUTTYPE_Pos)     /*!< 0x00040000 */
+#define RTC_TAFCR_ALARMOUTTYPE        RTC_TAFCR_ALARMOUTTYPE_Msk               
+#define RTC_TAFCR_TSINSEL_Pos         (17U)                                    
+#define RTC_TAFCR_TSINSEL_Msk         (0x1UL << RTC_TAFCR_TSINSEL_Pos)          /*!< 0x00020000 */
+#define RTC_TAFCR_TSINSEL             RTC_TAFCR_TSINSEL_Msk                    
+#define RTC_TAFCR_TAMP1INSEL_Pos      (16U)                                    
+#define RTC_TAFCR_TAMP1INSEL_Msk      (0x1UL << RTC_TAFCR_TAMP1INSEL_Pos)        /*!< 0x00010000 */
+#define RTC_TAFCR_TAMP1INSEL          RTC_TAFCR_TAMP1INSEL_Msk                  
+#define RTC_TAFCR_TAMPPUDIS_Pos       (15U)                                    
+#define RTC_TAFCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAFCR_TAMPPUDIS_Pos)        /*!< 0x00008000 */
+#define RTC_TAFCR_TAMPPUDIS           RTC_TAFCR_TAMPPUDIS_Msk                  
+#define RTC_TAFCR_TAMPPRCH_Pos        (13U)                                    
+#define RTC_TAFCR_TAMPPRCH_Msk        (0x3UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00006000 */
+#define RTC_TAFCR_TAMPPRCH            RTC_TAFCR_TAMPPRCH_Msk                   
+#define RTC_TAFCR_TAMPPRCH_0          (0x1UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00002000 */
+#define RTC_TAFCR_TAMPPRCH_1          (0x2UL << RTC_TAFCR_TAMPPRCH_Pos)         /*!< 0x00004000 */
+#define RTC_TAFCR_TAMPFLT_Pos         (11U)                                    
+#define RTC_TAFCR_TAMPFLT_Msk         (0x3UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001800 */
+#define RTC_TAFCR_TAMPFLT             RTC_TAFCR_TAMPFLT_Msk                    
+#define RTC_TAFCR_TAMPFLT_0           (0x1UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00000800 */
+#define RTC_TAFCR_TAMPFLT_1           (0x2UL << RTC_TAFCR_TAMPFLT_Pos)          /*!< 0x00001000 */
+#define RTC_TAFCR_TAMPFREQ_Pos        (8U)                                     
+#define RTC_TAFCR_TAMPFREQ_Msk        (0x7UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000700 */
+#define RTC_TAFCR_TAMPFREQ            RTC_TAFCR_TAMPFREQ_Msk                   
+#define RTC_TAFCR_TAMPFREQ_0          (0x1UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000100 */
+#define RTC_TAFCR_TAMPFREQ_1          (0x2UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000200 */
+#define RTC_TAFCR_TAMPFREQ_2          (0x4UL << RTC_TAFCR_TAMPFREQ_Pos)         /*!< 0x00000400 */
+#define RTC_TAFCR_TAMPTS_Pos          (7U)                                     
+#define RTC_TAFCR_TAMPTS_Msk          (0x1UL << RTC_TAFCR_TAMPTS_Pos)           /*!< 0x00000080 */
+#define RTC_TAFCR_TAMPTS              RTC_TAFCR_TAMPTS_Msk                     
+#define RTC_TAFCR_TAMP2TRG_Pos        (4U)                                     
+#define RTC_TAFCR_TAMP2TRG_Msk        (0x1UL << RTC_TAFCR_TAMP2TRG_Pos)         /*!< 0x00000010 */
+#define RTC_TAFCR_TAMP2TRG            RTC_TAFCR_TAMP2TRG_Msk                   
+#define RTC_TAFCR_TAMP2E_Pos          (3U)                                     
+#define RTC_TAFCR_TAMP2E_Msk          (0x1UL << RTC_TAFCR_TAMP2E_Pos)           /*!< 0x00000008 */
+#define RTC_TAFCR_TAMP2E              RTC_TAFCR_TAMP2E_Msk                     
+#define RTC_TAFCR_TAMPIE_Pos          (2U)                                     
+#define RTC_TAFCR_TAMPIE_Msk          (0x1UL << RTC_TAFCR_TAMPIE_Pos)           /*!< 0x00000004 */
+#define RTC_TAFCR_TAMPIE              RTC_TAFCR_TAMPIE_Msk                     
+#define RTC_TAFCR_TAMP1TRG_Pos        (1U)                                     
+#define RTC_TAFCR_TAMP1TRG_Msk        (0x1UL << RTC_TAFCR_TAMP1TRG_Pos)         /*!< 0x00000002 */
+#define RTC_TAFCR_TAMP1TRG            RTC_TAFCR_TAMP1TRG_Msk                   
+#define RTC_TAFCR_TAMP1E_Pos          (0U)                                     
+#define RTC_TAFCR_TAMP1E_Msk          (0x1UL << RTC_TAFCR_TAMP1E_Pos)           /*!< 0x00000001 */
+#define RTC_TAFCR_TAMP1E              RTC_TAFCR_TAMP1E_Msk                     
+
+/* Legacy defines */
+#define RTC_TAFCR_TAMPINSEL           RTC_TAFCR_TAMP1INSEL
+
+/********************  Bits definition for RTC_ALRMASSR register  *************/
+#define RTC_ALRMASSR_MASKSS_Pos       (24U)                                    
+#define RTC_ALRMASSR_MASKSS_Msk       (0xFUL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x0F000000 */
+#define RTC_ALRMASSR_MASKSS           RTC_ALRMASSR_MASKSS_Msk                  
+#define RTC_ALRMASSR_MASKSS_0         (0x1UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x01000000 */
+#define RTC_ALRMASSR_MASKSS_1         (0x2UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x02000000 */
+#define RTC_ALRMASSR_MASKSS_2         (0x4UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x04000000 */
+#define RTC_ALRMASSR_MASKSS_3         (0x8UL << RTC_ALRMASSR_MASKSS_Pos)        /*!< 0x08000000 */
+#define RTC_ALRMASSR_SS_Pos           (0U)                                     
+#define RTC_ALRMASSR_SS_Msk           (0x7FFFUL << RTC_ALRMASSR_SS_Pos)         /*!< 0x00007FFF */
+#define RTC_ALRMASSR_SS               RTC_ALRMASSR_SS_Msk                      
+
+/********************  Bits definition for RTC_ALRMBSSR register  *************/
+#define RTC_ALRMBSSR_MASKSS_Pos       (24U)                                    
+#define RTC_ALRMBSSR_MASKSS_Msk       (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x0F000000 */
+#define RTC_ALRMBSSR_MASKSS           RTC_ALRMBSSR_MASKSS_Msk                  
+#define RTC_ALRMBSSR_MASKSS_0         (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x01000000 */
+#define RTC_ALRMBSSR_MASKSS_1         (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x02000000 */
+#define RTC_ALRMBSSR_MASKSS_2         (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x04000000 */
+#define RTC_ALRMBSSR_MASKSS_3         (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)        /*!< 0x08000000 */
+#define RTC_ALRMBSSR_SS_Pos           (0U)                                     
+#define RTC_ALRMBSSR_SS_Msk           (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)         /*!< 0x00007FFF */
+#define RTC_ALRMBSSR_SS               RTC_ALRMBSSR_SS_Msk                      
+
+/********************  Bits definition for RTC_BKP0R register  ****************/
+#define RTC_BKP0R_Pos                 (0U)                                     
+#define RTC_BKP0R_Msk                 (0xFFFFFFFFUL << RTC_BKP0R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP0R                     RTC_BKP0R_Msk                            
+
+/********************  Bits definition for RTC_BKP1R register  ****************/
+#define RTC_BKP1R_Pos                 (0U)                                     
+#define RTC_BKP1R_Msk                 (0xFFFFFFFFUL << RTC_BKP1R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP1R                     RTC_BKP1R_Msk                            
+
+/********************  Bits definition for RTC_BKP2R register  ****************/
+#define RTC_BKP2R_Pos                 (0U)                                     
+#define RTC_BKP2R_Msk                 (0xFFFFFFFFUL << RTC_BKP2R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP2R                     RTC_BKP2R_Msk                            
+
+/********************  Bits definition for RTC_BKP3R register  ****************/
+#define RTC_BKP3R_Pos                 (0U)                                     
+#define RTC_BKP3R_Msk                 (0xFFFFFFFFUL << RTC_BKP3R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP3R                     RTC_BKP3R_Msk                            
+
+/********************  Bits definition for RTC_BKP4R register  ****************/
+#define RTC_BKP4R_Pos                 (0U)                                     
+#define RTC_BKP4R_Msk                 (0xFFFFFFFFUL << RTC_BKP4R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP4R                     RTC_BKP4R_Msk                            
+
+/********************  Bits definition for RTC_BKP5R register  ****************/
+#define RTC_BKP5R_Pos                 (0U)                                     
+#define RTC_BKP5R_Msk                 (0xFFFFFFFFUL << RTC_BKP5R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP5R                     RTC_BKP5R_Msk                            
+
+/********************  Bits definition for RTC_BKP6R register  ****************/
+#define RTC_BKP6R_Pos                 (0U)                                     
+#define RTC_BKP6R_Msk                 (0xFFFFFFFFUL << RTC_BKP6R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP6R                     RTC_BKP6R_Msk                            
+
+/********************  Bits definition for RTC_BKP7R register  ****************/
+#define RTC_BKP7R_Pos                 (0U)                                     
+#define RTC_BKP7R_Msk                 (0xFFFFFFFFUL << RTC_BKP7R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP7R                     RTC_BKP7R_Msk                            
+
+/********************  Bits definition for RTC_BKP8R register  ****************/
+#define RTC_BKP8R_Pos                 (0U)                                     
+#define RTC_BKP8R_Msk                 (0xFFFFFFFFUL << RTC_BKP8R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP8R                     RTC_BKP8R_Msk                            
+
+/********************  Bits definition for RTC_BKP9R register  ****************/
+#define RTC_BKP9R_Pos                 (0U)                                     
+#define RTC_BKP9R_Msk                 (0xFFFFFFFFUL << RTC_BKP9R_Pos)           /*!< 0xFFFFFFFF */
+#define RTC_BKP9R                     RTC_BKP9R_Msk                            
+
+/********************  Bits definition for RTC_BKP10R register  ***************/
+#define RTC_BKP10R_Pos                (0U)                                     
+#define RTC_BKP10R_Msk                (0xFFFFFFFFUL << RTC_BKP10R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP10R                    RTC_BKP10R_Msk                           
+
+/********************  Bits definition for RTC_BKP11R register  ***************/
+#define RTC_BKP11R_Pos                (0U)                                     
+#define RTC_BKP11R_Msk                (0xFFFFFFFFUL << RTC_BKP11R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP11R                    RTC_BKP11R_Msk                           
+
+/********************  Bits definition for RTC_BKP12R register  ***************/
+#define RTC_BKP12R_Pos                (0U)                                     
+#define RTC_BKP12R_Msk                (0xFFFFFFFFUL << RTC_BKP12R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP12R                    RTC_BKP12R_Msk                           
+
+/********************  Bits definition for RTC_BKP13R register  ***************/
+#define RTC_BKP13R_Pos                (0U)                                     
+#define RTC_BKP13R_Msk                (0xFFFFFFFFUL << RTC_BKP13R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP13R                    RTC_BKP13R_Msk                           
+
+/********************  Bits definition for RTC_BKP14R register  ***************/
+#define RTC_BKP14R_Pos                (0U)                                     
+#define RTC_BKP14R_Msk                (0xFFFFFFFFUL << RTC_BKP14R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP14R                    RTC_BKP14R_Msk                           
+
+/********************  Bits definition for RTC_BKP15R register  ***************/
+#define RTC_BKP15R_Pos                (0U)                                     
+#define RTC_BKP15R_Msk                (0xFFFFFFFFUL << RTC_BKP15R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP15R                    RTC_BKP15R_Msk                           
+
+/********************  Bits definition for RTC_BKP16R register  ***************/
+#define RTC_BKP16R_Pos                (0U)                                     
+#define RTC_BKP16R_Msk                (0xFFFFFFFFUL << RTC_BKP16R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP16R                    RTC_BKP16R_Msk                           
+
+/********************  Bits definition for RTC_BKP17R register  ***************/
+#define RTC_BKP17R_Pos                (0U)                                     
+#define RTC_BKP17R_Msk                (0xFFFFFFFFUL << RTC_BKP17R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP17R                    RTC_BKP17R_Msk                           
+
+/********************  Bits definition for RTC_BKP18R register  ***************/
+#define RTC_BKP18R_Pos                (0U)                                     
+#define RTC_BKP18R_Msk                (0xFFFFFFFFUL << RTC_BKP18R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP18R                    RTC_BKP18R_Msk                           
+
+/********************  Bits definition for RTC_BKP19R register  ***************/
+#define RTC_BKP19R_Pos                (0U)                                     
+#define RTC_BKP19R_Msk                (0xFFFFFFFFUL << RTC_BKP19R_Pos)          /*!< 0xFFFFFFFF */
+#define RTC_BKP19R                    RTC_BKP19R_Msk                           
+
+/******************** Number of backup registers ******************************/
+#define RTC_BKP_NUMBER                       0x000000014U
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                          SD host Interface                                 */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SDIO_POWER register  ******************/
+#define SDIO_POWER_PWRCTRL_Pos         (0U)                                    
+#define SDIO_POWER_PWRCTRL_Msk         (0x3UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x00000003 */
+#define SDIO_POWER_PWRCTRL             SDIO_POWER_PWRCTRL_Msk                  /*!<PWRCTRL[1:0] bits (Power supply control bits) */
+#define SDIO_POWER_PWRCTRL_0           (0x1UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x01 */
+#define SDIO_POWER_PWRCTRL_1           (0x2UL << SDIO_POWER_PWRCTRL_Pos)        /*!< 0x02 */
+
+/******************  Bit definition for SDIO_CLKCR register  ******************/
+#define SDIO_CLKCR_CLKDIV_Pos          (0U)                                    
+#define SDIO_CLKCR_CLKDIV_Msk          (0xFFUL << SDIO_CLKCR_CLKDIV_Pos)        /*!< 0x000000FF */
+#define SDIO_CLKCR_CLKDIV              SDIO_CLKCR_CLKDIV_Msk                   /*!<Clock divide factor             */
+#define SDIO_CLKCR_CLKEN_Pos           (8U)                                    
+#define SDIO_CLKCR_CLKEN_Msk           (0x1UL << SDIO_CLKCR_CLKEN_Pos)          /*!< 0x00000100 */
+#define SDIO_CLKCR_CLKEN               SDIO_CLKCR_CLKEN_Msk                    /*!<Clock enable bit                */
+#define SDIO_CLKCR_PWRSAV_Pos          (9U)                                    
+#define SDIO_CLKCR_PWRSAV_Msk          (0x1UL << SDIO_CLKCR_PWRSAV_Pos)         /*!< 0x00000200 */
+#define SDIO_CLKCR_PWRSAV              SDIO_CLKCR_PWRSAV_Msk                   /*!<Power saving configuration bit  */
+#define SDIO_CLKCR_BYPASS_Pos          (10U)                                   
+#define SDIO_CLKCR_BYPASS_Msk          (0x1UL << SDIO_CLKCR_BYPASS_Pos)         /*!< 0x00000400 */
+#define SDIO_CLKCR_BYPASS              SDIO_CLKCR_BYPASS_Msk                   /*!<Clock divider bypass enable bit */
+
+#define SDIO_CLKCR_WIDBUS_Pos          (11U)                                   
+#define SDIO_CLKCR_WIDBUS_Msk          (0x3UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x00001800 */
+#define SDIO_CLKCR_WIDBUS              SDIO_CLKCR_WIDBUS_Msk                   /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
+#define SDIO_CLKCR_WIDBUS_0            (0x1UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x0800 */
+#define SDIO_CLKCR_WIDBUS_1            (0x2UL << SDIO_CLKCR_WIDBUS_Pos)         /*!< 0x1000 */
+
+#define SDIO_CLKCR_NEGEDGE_Pos         (13U)                                   
+#define SDIO_CLKCR_NEGEDGE_Msk         (0x1UL << SDIO_CLKCR_NEGEDGE_Pos)        /*!< 0x00002000 */
+#define SDIO_CLKCR_NEGEDGE             SDIO_CLKCR_NEGEDGE_Msk                  /*!<SDIO_CK dephasing selection bit */
+#define SDIO_CLKCR_HWFC_EN_Pos         (14U)                                   
+#define SDIO_CLKCR_HWFC_EN_Msk         (0x1UL << SDIO_CLKCR_HWFC_EN_Pos)        /*!< 0x00004000 */
+#define SDIO_CLKCR_HWFC_EN             SDIO_CLKCR_HWFC_EN_Msk                  /*!<HW Flow Control enable          */
+
+/*******************  Bit definition for SDIO_ARG register  *******************/
+#define SDIO_ARG_CMDARG_Pos            (0U)                                    
+#define SDIO_ARG_CMDARG_Msk            (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)    /*!< 0xFFFFFFFF */
+#define SDIO_ARG_CMDARG                SDIO_ARG_CMDARG_Msk                     /*!<Command argument */
+
+/*******************  Bit definition for SDIO_CMD register  *******************/
+#define SDIO_CMD_CMDINDEX_Pos          (0U)                                    
+#define SDIO_CMD_CMDINDEX_Msk          (0x3FUL << SDIO_CMD_CMDINDEX_Pos)        /*!< 0x0000003F */
+#define SDIO_CMD_CMDINDEX              SDIO_CMD_CMDINDEX_Msk                   /*!<Command Index                               */
+
+#define SDIO_CMD_WAITRESP_Pos          (6U)                                    
+#define SDIO_CMD_WAITRESP_Msk          (0x3UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x000000C0 */
+#define SDIO_CMD_WAITRESP              SDIO_CMD_WAITRESP_Msk                   /*!<WAITRESP[1:0] bits (Wait for response bits) */
+#define SDIO_CMD_WAITRESP_0            (0x1UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0040 */
+#define SDIO_CMD_WAITRESP_1            (0x2UL << SDIO_CMD_WAITRESP_Pos)         /*!< 0x0080 */
+
+#define SDIO_CMD_WAITINT_Pos           (8U)                                    
+#define SDIO_CMD_WAITINT_Msk           (0x1UL << SDIO_CMD_WAITINT_Pos)          /*!< 0x00000100 */
+#define SDIO_CMD_WAITINT               SDIO_CMD_WAITINT_Msk                    /*!<CPSM Waits for Interrupt Request                               */
+#define SDIO_CMD_WAITPEND_Pos          (9U)                                    
+#define SDIO_CMD_WAITPEND_Msk          (0x1UL << SDIO_CMD_WAITPEND_Pos)         /*!< 0x00000200 */
+#define SDIO_CMD_WAITPEND              SDIO_CMD_WAITPEND_Msk                   /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
+#define SDIO_CMD_CPSMEN_Pos            (10U)                                   
+#define SDIO_CMD_CPSMEN_Msk            (0x1UL << SDIO_CMD_CPSMEN_Pos)           /*!< 0x00000400 */
+#define SDIO_CMD_CPSMEN                SDIO_CMD_CPSMEN_Msk                     /*!<Command path state machine (CPSM) Enable bit                   */
+#define SDIO_CMD_SDIOSUSPEND_Pos       (11U)                                   
+#define SDIO_CMD_SDIOSUSPEND_Msk       (0x1UL << SDIO_CMD_SDIOSUSPEND_Pos)      /*!< 0x00000800 */
+#define SDIO_CMD_SDIOSUSPEND           SDIO_CMD_SDIOSUSPEND_Msk                /*!<SD I/O suspend command                                         */
+#define SDIO_CMD_ENCMDCOMPL_Pos        (12U)                                   
+#define SDIO_CMD_ENCMDCOMPL_Msk        (0x1UL << SDIO_CMD_ENCMDCOMPL_Pos)       /*!< 0x00001000 */
+#define SDIO_CMD_ENCMDCOMPL            SDIO_CMD_ENCMDCOMPL_Msk                 /*!<Enable CMD completion                                          */
+#define SDIO_CMD_NIEN_Pos              (13U)                                   
+#define SDIO_CMD_NIEN_Msk              (0x1UL << SDIO_CMD_NIEN_Pos)             /*!< 0x00002000 */
+#define SDIO_CMD_NIEN                  SDIO_CMD_NIEN_Msk                       /*!<Not Interrupt Enable                                           */
+#define SDIO_CMD_CEATACMD_Pos          (14U)                                   
+#define SDIO_CMD_CEATACMD_Msk          (0x1UL << SDIO_CMD_CEATACMD_Pos)         /*!< 0x00004000 */
+#define SDIO_CMD_CEATACMD              SDIO_CMD_CEATACMD_Msk                   /*!<CE-ATA command                                                 */
+
+/*****************  Bit definition for SDIO_RESPCMD register  *****************/
+#define SDIO_RESPCMD_RESPCMD_Pos       (0U)                                    
+#define SDIO_RESPCMD_RESPCMD_Msk       (0x3FUL << SDIO_RESPCMD_RESPCMD_Pos)     /*!< 0x0000003F */
+#define SDIO_RESPCMD_RESPCMD           SDIO_RESPCMD_RESPCMD_Msk                /*!<Response command index */
+
+/******************  Bit definition for SDIO_RESP0 register  ******************/
+#define SDIO_RESP0_CARDSTATUS0_Pos     (0U)                                    
+#define SDIO_RESP0_CARDSTATUS0_Msk     (0xFFFFFFFFUL << SDIO_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP0_CARDSTATUS0         SDIO_RESP0_CARDSTATUS0_Msk              /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP1 register  ******************/
+#define SDIO_RESP1_CARDSTATUS1_Pos     (0U)                                    
+#define SDIO_RESP1_CARDSTATUS1_Msk     (0xFFFFFFFFUL << SDIO_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP1_CARDSTATUS1         SDIO_RESP1_CARDSTATUS1_Msk              /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP2 register  ******************/
+#define SDIO_RESP2_CARDSTATUS2_Pos     (0U)                                    
+#define SDIO_RESP2_CARDSTATUS2_Msk     (0xFFFFFFFFUL << SDIO_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP2_CARDSTATUS2         SDIO_RESP2_CARDSTATUS2_Msk              /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP3 register  ******************/
+#define SDIO_RESP3_CARDSTATUS3_Pos     (0U)                                    
+#define SDIO_RESP3_CARDSTATUS3_Msk     (0xFFFFFFFFUL << SDIO_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP3_CARDSTATUS3         SDIO_RESP3_CARDSTATUS3_Msk              /*!<Card Status */
+
+/******************  Bit definition for SDIO_RESP4 register  ******************/
+#define SDIO_RESP4_CARDSTATUS4_Pos     (0U)                                    
+#define SDIO_RESP4_CARDSTATUS4_Msk     (0xFFFFFFFFUL << SDIO_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_RESP4_CARDSTATUS4         SDIO_RESP4_CARDSTATUS4_Msk              /*!<Card Status */
+
+/******************  Bit definition for SDIO_DTIMER register  *****************/
+#define SDIO_DTIMER_DATATIME_Pos       (0U)                                    
+#define SDIO_DTIMER_DATATIME_Msk       (0xFFFFFFFFUL << SDIO_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_DTIMER_DATATIME           SDIO_DTIMER_DATATIME_Msk                /*!<Data timeout period. */
+
+/******************  Bit definition for SDIO_DLEN register  *******************/
+#define SDIO_DLEN_DATALENGTH_Pos       (0U)                                    
+#define SDIO_DLEN_DATALENGTH_Msk       (0x1FFFFFFUL << SDIO_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DLEN_DATALENGTH           SDIO_DLEN_DATALENGTH_Msk                /*!<Data length value    */
+
+/******************  Bit definition for SDIO_DCTRL register  ******************/
+#define SDIO_DCTRL_DTEN_Pos            (0U)                                    
+#define SDIO_DCTRL_DTEN_Msk            (0x1UL << SDIO_DCTRL_DTEN_Pos)           /*!< 0x00000001 */
+#define SDIO_DCTRL_DTEN                SDIO_DCTRL_DTEN_Msk                     /*!<Data transfer enabled bit         */
+#define SDIO_DCTRL_DTDIR_Pos           (1U)                                    
+#define SDIO_DCTRL_DTDIR_Msk           (0x1UL << SDIO_DCTRL_DTDIR_Pos)          /*!< 0x00000002 */
+#define SDIO_DCTRL_DTDIR               SDIO_DCTRL_DTDIR_Msk                    /*!<Data transfer direction selection */
+#define SDIO_DCTRL_DTMODE_Pos          (2U)                                    
+#define SDIO_DCTRL_DTMODE_Msk          (0x1UL << SDIO_DCTRL_DTMODE_Pos)         /*!< 0x00000004 */
+#define SDIO_DCTRL_DTMODE              SDIO_DCTRL_DTMODE_Msk                   /*!<Data transfer mode selection      */
+#define SDIO_DCTRL_DMAEN_Pos           (3U)                                    
+#define SDIO_DCTRL_DMAEN_Msk           (0x1UL << SDIO_DCTRL_DMAEN_Pos)          /*!< 0x00000008 */
+#define SDIO_DCTRL_DMAEN               SDIO_DCTRL_DMAEN_Msk                    /*!<DMA enabled bit                   */
+
+#define SDIO_DCTRL_DBLOCKSIZE_Pos      (4U)                                    
+#define SDIO_DCTRL_DBLOCKSIZE_Msk      (0xFUL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x000000F0 */
+#define SDIO_DCTRL_DBLOCKSIZE          SDIO_DCTRL_DBLOCKSIZE_Msk               /*!<DBLOCKSIZE[3:0] bits (Data block size) */
+#define SDIO_DCTRL_DBLOCKSIZE_0        (0x1UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0010 */
+#define SDIO_DCTRL_DBLOCKSIZE_1        (0x2UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0020 */
+#define SDIO_DCTRL_DBLOCKSIZE_2        (0x4UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0040 */
+#define SDIO_DCTRL_DBLOCKSIZE_3        (0x8UL << SDIO_DCTRL_DBLOCKSIZE_Pos)     /*!< 0x0080 */
+
+#define SDIO_DCTRL_RWSTART_Pos         (8U)                                    
+#define SDIO_DCTRL_RWSTART_Msk         (0x1UL << SDIO_DCTRL_RWSTART_Pos)        /*!< 0x00000100 */
+#define SDIO_DCTRL_RWSTART             SDIO_DCTRL_RWSTART_Msk                  /*!<Read wait start         */
+#define SDIO_DCTRL_RWSTOP_Pos          (9U)                                    
+#define SDIO_DCTRL_RWSTOP_Msk          (0x1UL << SDIO_DCTRL_RWSTOP_Pos)         /*!< 0x00000200 */
+#define SDIO_DCTRL_RWSTOP              SDIO_DCTRL_RWSTOP_Msk                   /*!<Read wait stop          */
+#define SDIO_DCTRL_RWMOD_Pos           (10U)                                   
+#define SDIO_DCTRL_RWMOD_Msk           (0x1UL << SDIO_DCTRL_RWMOD_Pos)          /*!< 0x00000400 */
+#define SDIO_DCTRL_RWMOD               SDIO_DCTRL_RWMOD_Msk                    /*!<Read wait mode          */
+#define SDIO_DCTRL_SDIOEN_Pos          (11U)                                   
+#define SDIO_DCTRL_SDIOEN_Msk          (0x1UL << SDIO_DCTRL_SDIOEN_Pos)         /*!< 0x00000800 */
+#define SDIO_DCTRL_SDIOEN              SDIO_DCTRL_SDIOEN_Msk                   /*!<SD I/O enable functions */
+
+/******************  Bit definition for SDIO_DCOUNT register  *****************/
+#define SDIO_DCOUNT_DATACOUNT_Pos      (0U)                                    
+#define SDIO_DCOUNT_DATACOUNT_Msk      (0x1FFFFFFUL << SDIO_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
+#define SDIO_DCOUNT_DATACOUNT          SDIO_DCOUNT_DATACOUNT_Msk               /*!<Data count value */
+
+/******************  Bit definition for SDIO_STA register  ********************/
+#define SDIO_STA_CCRCFAIL_Pos          (0U)                                    
+#define SDIO_STA_CCRCFAIL_Msk          (0x1UL << SDIO_STA_CCRCFAIL_Pos)         /*!< 0x00000001 */
+#define SDIO_STA_CCRCFAIL              SDIO_STA_CCRCFAIL_Msk                   /*!<Command response received (CRC check failed)  */
+#define SDIO_STA_DCRCFAIL_Pos          (1U)                                    
+#define SDIO_STA_DCRCFAIL_Msk          (0x1UL << SDIO_STA_DCRCFAIL_Pos)         /*!< 0x00000002 */
+#define SDIO_STA_DCRCFAIL              SDIO_STA_DCRCFAIL_Msk                   /*!<Data block sent/received (CRC check failed)   */
+#define SDIO_STA_CTIMEOUT_Pos          (2U)                                    
+#define SDIO_STA_CTIMEOUT_Msk          (0x1UL << SDIO_STA_CTIMEOUT_Pos)         /*!< 0x00000004 */
+#define SDIO_STA_CTIMEOUT              SDIO_STA_CTIMEOUT_Msk                   /*!<Command response timeout                      */
+#define SDIO_STA_DTIMEOUT_Pos          (3U)                                    
+#define SDIO_STA_DTIMEOUT_Msk          (0x1UL << SDIO_STA_DTIMEOUT_Pos)         /*!< 0x00000008 */
+#define SDIO_STA_DTIMEOUT              SDIO_STA_DTIMEOUT_Msk                   /*!<Data timeout                                  */
+#define SDIO_STA_TXUNDERR_Pos          (4U)                                    
+#define SDIO_STA_TXUNDERR_Msk          (0x1UL << SDIO_STA_TXUNDERR_Pos)         /*!< 0x00000010 */
+#define SDIO_STA_TXUNDERR              SDIO_STA_TXUNDERR_Msk                   /*!<Transmit FIFO underrun error                  */
+#define SDIO_STA_RXOVERR_Pos           (5U)                                    
+#define SDIO_STA_RXOVERR_Msk           (0x1UL << SDIO_STA_RXOVERR_Pos)          /*!< 0x00000020 */
+#define SDIO_STA_RXOVERR               SDIO_STA_RXOVERR_Msk                    /*!<Received FIFO overrun error                   */
+#define SDIO_STA_CMDREND_Pos           (6U)                                    
+#define SDIO_STA_CMDREND_Msk           (0x1UL << SDIO_STA_CMDREND_Pos)          /*!< 0x00000040 */
+#define SDIO_STA_CMDREND               SDIO_STA_CMDREND_Msk                    /*!<Command response received (CRC check passed)  */
+#define SDIO_STA_CMDSENT_Pos           (7U)                                    
+#define SDIO_STA_CMDSENT_Msk           (0x1UL << SDIO_STA_CMDSENT_Pos)          /*!< 0x00000080 */
+#define SDIO_STA_CMDSENT               SDIO_STA_CMDSENT_Msk                    /*!<Command sent (no response required)           */
+#define SDIO_STA_DATAEND_Pos           (8U)                                    
+#define SDIO_STA_DATAEND_Msk           (0x1UL << SDIO_STA_DATAEND_Pos)          /*!< 0x00000100 */
+#define SDIO_STA_DATAEND               SDIO_STA_DATAEND_Msk                    /*!<Data end (data counter, SDIDCOUNT, is zero)   */
+#define SDIO_STA_STBITERR_Pos          (9U)                                    
+#define SDIO_STA_STBITERR_Msk          (0x1UL << SDIO_STA_STBITERR_Pos)         /*!< 0x00000200 */
+#define SDIO_STA_STBITERR              SDIO_STA_STBITERR_Msk                   /*!<Start bit not detected on all data signals in wide bus mode */
+#define SDIO_STA_DBCKEND_Pos           (10U)                                   
+#define SDIO_STA_DBCKEND_Msk           (0x1UL << SDIO_STA_DBCKEND_Pos)          /*!< 0x00000400 */
+#define SDIO_STA_DBCKEND               SDIO_STA_DBCKEND_Msk                    /*!<Data block sent/received (CRC check passed)   */
+#define SDIO_STA_CMDACT_Pos            (11U)                                   
+#define SDIO_STA_CMDACT_Msk            (0x1UL << SDIO_STA_CMDACT_Pos)           /*!< 0x00000800 */
+#define SDIO_STA_CMDACT                SDIO_STA_CMDACT_Msk                     /*!<Command transfer in progress                  */
+#define SDIO_STA_TXACT_Pos             (12U)                                   
+#define SDIO_STA_TXACT_Msk             (0x1UL << SDIO_STA_TXACT_Pos)            /*!< 0x00001000 */
+#define SDIO_STA_TXACT                 SDIO_STA_TXACT_Msk                      /*!<Data transmit in progress                     */
+#define SDIO_STA_RXACT_Pos             (13U)                                   
+#define SDIO_STA_RXACT_Msk             (0x1UL << SDIO_STA_RXACT_Pos)            /*!< 0x00002000 */
+#define SDIO_STA_RXACT                 SDIO_STA_RXACT_Msk                      /*!<Data receive in progress                      */
+#define SDIO_STA_TXFIFOHE_Pos          (14U)                                   
+#define SDIO_STA_TXFIFOHE_Msk          (0x1UL << SDIO_STA_TXFIFOHE_Pos)         /*!< 0x00004000 */
+#define SDIO_STA_TXFIFOHE              SDIO_STA_TXFIFOHE_Msk                   /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
+#define SDIO_STA_RXFIFOHF_Pos          (15U)                                   
+#define SDIO_STA_RXFIFOHF_Msk          (0x1UL << SDIO_STA_RXFIFOHF_Pos)         /*!< 0x00008000 */
+#define SDIO_STA_RXFIFOHF              SDIO_STA_RXFIFOHF_Msk                   /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
+#define SDIO_STA_TXFIFOF_Pos           (16U)                                   
+#define SDIO_STA_TXFIFOF_Msk           (0x1UL << SDIO_STA_TXFIFOF_Pos)          /*!< 0x00010000 */
+#define SDIO_STA_TXFIFOF               SDIO_STA_TXFIFOF_Msk                    /*!<Transmit FIFO full                            */
+#define SDIO_STA_RXFIFOF_Pos           (17U)                                   
+#define SDIO_STA_RXFIFOF_Msk           (0x1UL << SDIO_STA_RXFIFOF_Pos)          /*!< 0x00020000 */
+#define SDIO_STA_RXFIFOF               SDIO_STA_RXFIFOF_Msk                    /*!<Receive FIFO full                             */
+#define SDIO_STA_TXFIFOE_Pos           (18U)                                   
+#define SDIO_STA_TXFIFOE_Msk           (0x1UL << SDIO_STA_TXFIFOE_Pos)          /*!< 0x00040000 */
+#define SDIO_STA_TXFIFOE               SDIO_STA_TXFIFOE_Msk                    /*!<Transmit FIFO empty                           */
+#define SDIO_STA_RXFIFOE_Pos           (19U)                                   
+#define SDIO_STA_RXFIFOE_Msk           (0x1UL << SDIO_STA_RXFIFOE_Pos)          /*!< 0x00080000 */
+#define SDIO_STA_RXFIFOE               SDIO_STA_RXFIFOE_Msk                    /*!<Receive FIFO empty                            */
+#define SDIO_STA_TXDAVL_Pos            (20U)                                   
+#define SDIO_STA_TXDAVL_Msk            (0x1UL << SDIO_STA_TXDAVL_Pos)           /*!< 0x00100000 */
+#define SDIO_STA_TXDAVL                SDIO_STA_TXDAVL_Msk                     /*!<Data available in transmit FIFO               */
+#define SDIO_STA_RXDAVL_Pos            (21U)                                   
+#define SDIO_STA_RXDAVL_Msk            (0x1UL << SDIO_STA_RXDAVL_Pos)           /*!< 0x00200000 */
+#define SDIO_STA_RXDAVL                SDIO_STA_RXDAVL_Msk                     /*!<Data available in receive FIFO                */
+#define SDIO_STA_SDIOIT_Pos            (22U)                                   
+#define SDIO_STA_SDIOIT_Msk            (0x1UL << SDIO_STA_SDIOIT_Pos)           /*!< 0x00400000 */
+#define SDIO_STA_SDIOIT                SDIO_STA_SDIOIT_Msk                     /*!<SDIO interrupt received                       */
+#define SDIO_STA_CEATAEND_Pos          (23U)                                   
+#define SDIO_STA_CEATAEND_Msk          (0x1UL << SDIO_STA_CEATAEND_Pos)         /*!< 0x00800000 */
+#define SDIO_STA_CEATAEND              SDIO_STA_CEATAEND_Msk                   /*!<CE-ATA command completion signal received for CMD61 */
+
+/*******************  Bit definition for SDIO_ICR register  *******************/
+#define SDIO_ICR_CCRCFAILC_Pos         (0U)                                    
+#define SDIO_ICR_CCRCFAILC_Msk         (0x1UL << SDIO_ICR_CCRCFAILC_Pos)        /*!< 0x00000001 */
+#define SDIO_ICR_CCRCFAILC             SDIO_ICR_CCRCFAILC_Msk                  /*!<CCRCFAIL flag clear bit */
+#define SDIO_ICR_DCRCFAILC_Pos         (1U)                                    
+#define SDIO_ICR_DCRCFAILC_Msk         (0x1UL << SDIO_ICR_DCRCFAILC_Pos)        /*!< 0x00000002 */
+#define SDIO_ICR_DCRCFAILC             SDIO_ICR_DCRCFAILC_Msk                  /*!<DCRCFAIL flag clear bit */
+#define SDIO_ICR_CTIMEOUTC_Pos         (2U)                                    
+#define SDIO_ICR_CTIMEOUTC_Msk         (0x1UL << SDIO_ICR_CTIMEOUTC_Pos)        /*!< 0x00000004 */
+#define SDIO_ICR_CTIMEOUTC             SDIO_ICR_CTIMEOUTC_Msk                  /*!<CTIMEOUT flag clear bit */
+#define SDIO_ICR_DTIMEOUTC_Pos         (3U)                                    
+#define SDIO_ICR_DTIMEOUTC_Msk         (0x1UL << SDIO_ICR_DTIMEOUTC_Pos)        /*!< 0x00000008 */
+#define SDIO_ICR_DTIMEOUTC             SDIO_ICR_DTIMEOUTC_Msk                  /*!<DTIMEOUT flag clear bit */
+#define SDIO_ICR_TXUNDERRC_Pos         (4U)                                    
+#define SDIO_ICR_TXUNDERRC_Msk         (0x1UL << SDIO_ICR_TXUNDERRC_Pos)        /*!< 0x00000010 */
+#define SDIO_ICR_TXUNDERRC             SDIO_ICR_TXUNDERRC_Msk                  /*!<TXUNDERR flag clear bit */
+#define SDIO_ICR_RXOVERRC_Pos          (5U)                                    
+#define SDIO_ICR_RXOVERRC_Msk          (0x1UL << SDIO_ICR_RXOVERRC_Pos)         /*!< 0x00000020 */
+#define SDIO_ICR_RXOVERRC              SDIO_ICR_RXOVERRC_Msk                   /*!<RXOVERR flag clear bit  */
+#define SDIO_ICR_CMDRENDC_Pos          (6U)                                    
+#define SDIO_ICR_CMDRENDC_Msk          (0x1UL << SDIO_ICR_CMDRENDC_Pos)         /*!< 0x00000040 */
+#define SDIO_ICR_CMDRENDC              SDIO_ICR_CMDRENDC_Msk                   /*!<CMDREND flag clear bit  */
+#define SDIO_ICR_CMDSENTC_Pos          (7U)                                    
+#define SDIO_ICR_CMDSENTC_Msk          (0x1UL << SDIO_ICR_CMDSENTC_Pos)         /*!< 0x00000080 */
+#define SDIO_ICR_CMDSENTC              SDIO_ICR_CMDSENTC_Msk                   /*!<CMDSENT flag clear bit  */
+#define SDIO_ICR_DATAENDC_Pos          (8U)                                    
+#define SDIO_ICR_DATAENDC_Msk          (0x1UL << SDIO_ICR_DATAENDC_Pos)         /*!< 0x00000100 */
+#define SDIO_ICR_DATAENDC              SDIO_ICR_DATAENDC_Msk                   /*!<DATAEND flag clear bit  */
+#define SDIO_ICR_STBITERRC_Pos         (9U)                                    
+#define SDIO_ICR_STBITERRC_Msk         (0x1UL << SDIO_ICR_STBITERRC_Pos)        /*!< 0x00000200 */
+#define SDIO_ICR_STBITERRC             SDIO_ICR_STBITERRC_Msk                  /*!<STBITERR flag clear bit */
+#define SDIO_ICR_DBCKENDC_Pos          (10U)                                   
+#define SDIO_ICR_DBCKENDC_Msk          (0x1UL << SDIO_ICR_DBCKENDC_Pos)         /*!< 0x00000400 */
+#define SDIO_ICR_DBCKENDC              SDIO_ICR_DBCKENDC_Msk                   /*!<DBCKEND flag clear bit  */
+#define SDIO_ICR_SDIOITC_Pos           (22U)                                   
+#define SDIO_ICR_SDIOITC_Msk           (0x1UL << SDIO_ICR_SDIOITC_Pos)          /*!< 0x00400000 */
+#define SDIO_ICR_SDIOITC               SDIO_ICR_SDIOITC_Msk                    /*!<SDIOIT flag clear bit   */
+#define SDIO_ICR_CEATAENDC_Pos         (23U)                                   
+#define SDIO_ICR_CEATAENDC_Msk         (0x1UL << SDIO_ICR_CEATAENDC_Pos)        /*!< 0x00800000 */
+#define SDIO_ICR_CEATAENDC             SDIO_ICR_CEATAENDC_Msk                  /*!<CEATAEND flag clear bit */
+
+/******************  Bit definition for SDIO_MASK register  *******************/
+#define SDIO_MASK_CCRCFAILIE_Pos       (0U)                                    
+#define SDIO_MASK_CCRCFAILIE_Msk       (0x1UL << SDIO_MASK_CCRCFAILIE_Pos)      /*!< 0x00000001 */
+#define SDIO_MASK_CCRCFAILIE           SDIO_MASK_CCRCFAILIE_Msk                /*!<Command CRC Fail Interrupt Enable          */
+#define SDIO_MASK_DCRCFAILIE_Pos       (1U)                                    
+#define SDIO_MASK_DCRCFAILIE_Msk       (0x1UL << SDIO_MASK_DCRCFAILIE_Pos)      /*!< 0x00000002 */
+#define SDIO_MASK_DCRCFAILIE           SDIO_MASK_DCRCFAILIE_Msk                /*!<Data CRC Fail Interrupt Enable             */
+#define SDIO_MASK_CTIMEOUTIE_Pos       (2U)                                    
+#define SDIO_MASK_CTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_CTIMEOUTIE_Pos)      /*!< 0x00000004 */
+#define SDIO_MASK_CTIMEOUTIE           SDIO_MASK_CTIMEOUTIE_Msk                /*!<Command TimeOut Interrupt Enable           */
+#define SDIO_MASK_DTIMEOUTIE_Pos       (3U)                                    
+#define SDIO_MASK_DTIMEOUTIE_Msk       (0x1UL << SDIO_MASK_DTIMEOUTIE_Pos)      /*!< 0x00000008 */
+#define SDIO_MASK_DTIMEOUTIE           SDIO_MASK_DTIMEOUTIE_Msk                /*!<Data TimeOut Interrupt Enable              */
+#define SDIO_MASK_TXUNDERRIE_Pos       (4U)                                    
+#define SDIO_MASK_TXUNDERRIE_Msk       (0x1UL << SDIO_MASK_TXUNDERRIE_Pos)      /*!< 0x00000010 */
+#define SDIO_MASK_TXUNDERRIE           SDIO_MASK_TXUNDERRIE_Msk                /*!<Tx FIFO UnderRun Error Interrupt Enable    */
+#define SDIO_MASK_RXOVERRIE_Pos        (5U)                                    
+#define SDIO_MASK_RXOVERRIE_Msk        (0x1UL << SDIO_MASK_RXOVERRIE_Pos)       /*!< 0x00000020 */
+#define SDIO_MASK_RXOVERRIE            SDIO_MASK_RXOVERRIE_Msk                 /*!<Rx FIFO OverRun Error Interrupt Enable     */
+#define SDIO_MASK_CMDRENDIE_Pos        (6U)                                    
+#define SDIO_MASK_CMDRENDIE_Msk        (0x1UL << SDIO_MASK_CMDRENDIE_Pos)       /*!< 0x00000040 */
+#define SDIO_MASK_CMDRENDIE            SDIO_MASK_CMDRENDIE_Msk                 /*!<Command Response Received Interrupt Enable */
+#define SDIO_MASK_CMDSENTIE_Pos        (7U)                                    
+#define SDIO_MASK_CMDSENTIE_Msk        (0x1UL << SDIO_MASK_CMDSENTIE_Pos)       /*!< 0x00000080 */
+#define SDIO_MASK_CMDSENTIE            SDIO_MASK_CMDSENTIE_Msk                 /*!<Command Sent Interrupt Enable              */
+#define SDIO_MASK_DATAENDIE_Pos        (8U)                                    
+#define SDIO_MASK_DATAENDIE_Msk        (0x1UL << SDIO_MASK_DATAENDIE_Pos)       /*!< 0x00000100 */
+#define SDIO_MASK_DATAENDIE            SDIO_MASK_DATAENDIE_Msk                 /*!<Data End Interrupt Enable                  */
+#define SDIO_MASK_STBITERRIE_Pos       (9U)                                    
+#define SDIO_MASK_STBITERRIE_Msk       (0x1UL << SDIO_MASK_STBITERRIE_Pos)      /*!< 0x00000200 */
+#define SDIO_MASK_STBITERRIE           SDIO_MASK_STBITERRIE_Msk                /*!<Start Bit Error Interrupt Enable           */
+#define SDIO_MASK_DBCKENDIE_Pos        (10U)                                   
+#define SDIO_MASK_DBCKENDIE_Msk        (0x1UL << SDIO_MASK_DBCKENDIE_Pos)       /*!< 0x00000400 */
+#define SDIO_MASK_DBCKENDIE            SDIO_MASK_DBCKENDIE_Msk                 /*!<Data Block End Interrupt Enable            */
+#define SDIO_MASK_CMDACTIE_Pos         (11U)                                   
+#define SDIO_MASK_CMDACTIE_Msk         (0x1UL << SDIO_MASK_CMDACTIE_Pos)        /*!< 0x00000800 */
+#define SDIO_MASK_CMDACTIE             SDIO_MASK_CMDACTIE_Msk                  /*!<CCommand Acting Interrupt Enable           */
+#define SDIO_MASK_TXACTIE_Pos          (12U)                                   
+#define SDIO_MASK_TXACTIE_Msk          (0x1UL << SDIO_MASK_TXACTIE_Pos)         /*!< 0x00001000 */
+#define SDIO_MASK_TXACTIE              SDIO_MASK_TXACTIE_Msk                   /*!<Data Transmit Acting Interrupt Enable      */
+#define SDIO_MASK_RXACTIE_Pos          (13U)                                   
+#define SDIO_MASK_RXACTIE_Msk          (0x1UL << SDIO_MASK_RXACTIE_Pos)         /*!< 0x00002000 */
+#define SDIO_MASK_RXACTIE              SDIO_MASK_RXACTIE_Msk                   /*!<Data receive acting interrupt enabled      */
+#define SDIO_MASK_TXFIFOHEIE_Pos       (14U)                                   
+#define SDIO_MASK_TXFIFOHEIE_Msk       (0x1UL << SDIO_MASK_TXFIFOHEIE_Pos)      /*!< 0x00004000 */
+#define SDIO_MASK_TXFIFOHEIE           SDIO_MASK_TXFIFOHEIE_Msk                /*!<Tx FIFO Half Empty interrupt Enable        */
+#define SDIO_MASK_RXFIFOHFIE_Pos       (15U)                                   
+#define SDIO_MASK_RXFIFOHFIE_Msk       (0x1UL << SDIO_MASK_RXFIFOHFIE_Pos)      /*!< 0x00008000 */
+#define SDIO_MASK_RXFIFOHFIE           SDIO_MASK_RXFIFOHFIE_Msk                /*!<Rx FIFO Half Full interrupt Enable         */
+#define SDIO_MASK_TXFIFOFIE_Pos        (16U)                                   
+#define SDIO_MASK_TXFIFOFIE_Msk        (0x1UL << SDIO_MASK_TXFIFOFIE_Pos)       /*!< 0x00010000 */
+#define SDIO_MASK_TXFIFOFIE            SDIO_MASK_TXFIFOFIE_Msk                 /*!<Tx FIFO Full interrupt Enable              */
+#define SDIO_MASK_RXFIFOFIE_Pos        (17U)                                   
+#define SDIO_MASK_RXFIFOFIE_Msk        (0x1UL << SDIO_MASK_RXFIFOFIE_Pos)       /*!< 0x00020000 */
+#define SDIO_MASK_RXFIFOFIE            SDIO_MASK_RXFIFOFIE_Msk                 /*!<Rx FIFO Full interrupt Enable              */
+#define SDIO_MASK_TXFIFOEIE_Pos        (18U)                                   
+#define SDIO_MASK_TXFIFOEIE_Msk        (0x1UL << SDIO_MASK_TXFIFOEIE_Pos)       /*!< 0x00040000 */
+#define SDIO_MASK_TXFIFOEIE            SDIO_MASK_TXFIFOEIE_Msk                 /*!<Tx FIFO Empty interrupt Enable             */
+#define SDIO_MASK_RXFIFOEIE_Pos        (19U)                                   
+#define SDIO_MASK_RXFIFOEIE_Msk        (0x1UL << SDIO_MASK_RXFIFOEIE_Pos)       /*!< 0x00080000 */
+#define SDIO_MASK_RXFIFOEIE            SDIO_MASK_RXFIFOEIE_Msk                 /*!<Rx FIFO Empty interrupt Enable             */
+#define SDIO_MASK_TXDAVLIE_Pos         (20U)                                   
+#define SDIO_MASK_TXDAVLIE_Msk         (0x1UL << SDIO_MASK_TXDAVLIE_Pos)        /*!< 0x00100000 */
+#define SDIO_MASK_TXDAVLIE             SDIO_MASK_TXDAVLIE_Msk                  /*!<Data available in Tx FIFO interrupt Enable */
+#define SDIO_MASK_RXDAVLIE_Pos         (21U)                                   
+#define SDIO_MASK_RXDAVLIE_Msk         (0x1UL << SDIO_MASK_RXDAVLIE_Pos)        /*!< 0x00200000 */
+#define SDIO_MASK_RXDAVLIE             SDIO_MASK_RXDAVLIE_Msk                  /*!<Data available in Rx FIFO interrupt Enable */
+#define SDIO_MASK_SDIOITIE_Pos         (22U)                                   
+#define SDIO_MASK_SDIOITIE_Msk         (0x1UL << SDIO_MASK_SDIOITIE_Pos)        /*!< 0x00400000 */
+#define SDIO_MASK_SDIOITIE             SDIO_MASK_SDIOITIE_Msk                  /*!<SDIO Mode Interrupt Received interrupt Enable */
+#define SDIO_MASK_CEATAENDIE_Pos       (23U)                                   
+#define SDIO_MASK_CEATAENDIE_Msk       (0x1UL << SDIO_MASK_CEATAENDIE_Pos)      /*!< 0x00800000 */
+#define SDIO_MASK_CEATAENDIE           SDIO_MASK_CEATAENDIE_Msk                /*!<CE-ATA command completion signal received Interrupt Enable */
+
+/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
+#define SDIO_FIFOCNT_FIFOCOUNT_Pos     (0U)                                    
+#define SDIO_FIFOCNT_FIFOCOUNT_Msk     (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */
+#define SDIO_FIFOCNT_FIFOCOUNT         SDIO_FIFOCNT_FIFOCOUNT_Msk              /*!<Remaining number of words to be written to or read from the FIFO */
+
+/******************  Bit definition for SDIO_FIFO register  *******************/
+#define SDIO_FIFO_FIFODATA_Pos         (0U)                                    
+#define SDIO_FIFO_FIFODATA_Msk         (0xFFFFFFFFUL << SDIO_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
+#define SDIO_FIFO_FIFODATA             SDIO_FIFO_FIFODATA_Msk                  /*!<Receive and transmit FIFO data */
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Serial Peripheral Interface                         */
+/*                                                                            */
+/******************************************************************************/
+#define SPI_I2S_FULLDUPLEX_SUPPORT                                             /*!< I2S Full-Duplex support */
+
+/*******************  Bit definition for SPI_CR1 register  ********************/
+#define SPI_CR1_CPHA_Pos            (0U)                                       
+#define SPI_CR1_CPHA_Msk            (0x1UL << SPI_CR1_CPHA_Pos)                 /*!< 0x00000001 */
+#define SPI_CR1_CPHA                SPI_CR1_CPHA_Msk                           /*!<Clock Phase      */
+#define SPI_CR1_CPOL_Pos            (1U)                                       
+#define SPI_CR1_CPOL_Msk            (0x1UL << SPI_CR1_CPOL_Pos)                 /*!< 0x00000002 */
+#define SPI_CR1_CPOL                SPI_CR1_CPOL_Msk                           /*!<Clock Polarity   */
+#define SPI_CR1_MSTR_Pos            (2U)                                       
+#define SPI_CR1_MSTR_Msk            (0x1UL << SPI_CR1_MSTR_Pos)                 /*!< 0x00000004 */
+#define SPI_CR1_MSTR                SPI_CR1_MSTR_Msk                           /*!<Master Selection */
+
+#define SPI_CR1_BR_Pos              (3U)                                       
+#define SPI_CR1_BR_Msk              (0x7UL << SPI_CR1_BR_Pos)                   /*!< 0x00000038 */
+#define SPI_CR1_BR                  SPI_CR1_BR_Msk                             /*!<BR[2:0] bits (Baud Rate Control) */
+#define SPI_CR1_BR_0                (0x1UL << SPI_CR1_BR_Pos)                   /*!< 0x00000008 */
+#define SPI_CR1_BR_1                (0x2UL << SPI_CR1_BR_Pos)                   /*!< 0x00000010 */
+#define SPI_CR1_BR_2                (0x4UL << SPI_CR1_BR_Pos)                   /*!< 0x00000020 */
+
+#define SPI_CR1_SPE_Pos             (6U)                                       
+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                  /*!< 0x00000040 */
+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<SPI Enable                          */
+#define SPI_CR1_LSBFIRST_Pos        (7U)                                       
+#define SPI_CR1_LSBFIRST_Msk        (0x1UL << SPI_CR1_LSBFIRST_Pos)             /*!< 0x00000080 */
+#define SPI_CR1_LSBFIRST            SPI_CR1_LSBFIRST_Msk                       /*!<Frame Format                        */
+#define SPI_CR1_SSI_Pos             (8U)                                       
+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                  /*!< 0x00000100 */
+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal slave select               */
+#define SPI_CR1_SSM_Pos             (9U)                                       
+#define SPI_CR1_SSM_Msk             (0x1UL << SPI_CR1_SSM_Pos)                  /*!< 0x00000200 */
+#define SPI_CR1_SSM                 SPI_CR1_SSM_Msk                            /*!<Software slave management           */
+#define SPI_CR1_RXONLY_Pos          (10U)                                      
+#define SPI_CR1_RXONLY_Msk          (0x1UL << SPI_CR1_RXONLY_Pos)               /*!< 0x00000400 */
+#define SPI_CR1_RXONLY              SPI_CR1_RXONLY_Msk                         /*!<Receive only                        */
+#define SPI_CR1_DFF_Pos             (11U)                                      
+#define SPI_CR1_DFF_Msk             (0x1UL << SPI_CR1_DFF_Pos)                  /*!< 0x00000800 */
+#define SPI_CR1_DFF                 SPI_CR1_DFF_Msk                            /*!<Data Frame Format                   */
+#define SPI_CR1_CRCNEXT_Pos         (12U)                                      
+#define SPI_CR1_CRCNEXT_Msk         (0x1UL << SPI_CR1_CRCNEXT_Pos)              /*!< 0x00001000 */
+#define SPI_CR1_CRCNEXT             SPI_CR1_CRCNEXT_Msk                        /*!<Transmit CRC next                   */
+#define SPI_CR1_CRCEN_Pos           (13U)                                      
+#define SPI_CR1_CRCEN_Msk           (0x1UL << SPI_CR1_CRCEN_Pos)                /*!< 0x00002000 */
+#define SPI_CR1_CRCEN               SPI_CR1_CRCEN_Msk                          /*!<Hardware CRC calculation enable     */
+#define SPI_CR1_BIDIOE_Pos          (14U)                                      
+#define SPI_CR1_BIDIOE_Msk          (0x1UL << SPI_CR1_BIDIOE_Pos)               /*!< 0x00004000 */
+#define SPI_CR1_BIDIOE              SPI_CR1_BIDIOE_Msk                         /*!<Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE_Pos        (15U)                                      
+#define SPI_CR1_BIDIMODE_Msk        (0x1UL << SPI_CR1_BIDIMODE_Pos)             /*!< 0x00008000 */
+#define SPI_CR1_BIDIMODE            SPI_CR1_BIDIMODE_Msk                       /*!<Bidirectional data mode enable      */
+
+/*******************  Bit definition for SPI_CR2 register  ********************/
+#define SPI_CR2_RXDMAEN_Pos         (0U)                                       
+#define SPI_CR2_RXDMAEN_Msk         (0x1UL << SPI_CR2_RXDMAEN_Pos)              /*!< 0x00000001 */
+#define SPI_CR2_RXDMAEN             SPI_CR2_RXDMAEN_Msk                        /*!<Rx Buffer DMA Enable                 */
+#define SPI_CR2_TXDMAEN_Pos         (1U)                                       
+#define SPI_CR2_TXDMAEN_Msk         (0x1UL << SPI_CR2_TXDMAEN_Pos)              /*!< 0x00000002 */
+#define SPI_CR2_TXDMAEN             SPI_CR2_TXDMAEN_Msk                        /*!<Tx Buffer DMA Enable                 */
+#define SPI_CR2_SSOE_Pos            (2U)                                       
+#define SPI_CR2_SSOE_Msk            (0x1UL << SPI_CR2_SSOE_Pos)                 /*!< 0x00000004 */
+#define SPI_CR2_SSOE                SPI_CR2_SSOE_Msk                           /*!<SS Output Enable                     */
+#define SPI_CR2_FRF_Pos             (4U)                                       
+#define SPI_CR2_FRF_Msk             (0x1UL << SPI_CR2_FRF_Pos)                  /*!< 0x00000010 */
+#define SPI_CR2_FRF                 SPI_CR2_FRF_Msk                            /*!<Frame Format                         */
+#define SPI_CR2_ERRIE_Pos           (5U)                                       
+#define SPI_CR2_ERRIE_Msk           (0x1UL << SPI_CR2_ERRIE_Pos)                /*!< 0x00000020 */
+#define SPI_CR2_ERRIE               SPI_CR2_ERRIE_Msk                          /*!<Error Interrupt Enable               */
+#define SPI_CR2_RXNEIE_Pos          (6U)                                       
+#define SPI_CR2_RXNEIE_Msk          (0x1UL << SPI_CR2_RXNEIE_Pos)               /*!< 0x00000040 */
+#define SPI_CR2_RXNEIE              SPI_CR2_RXNEIE_Msk                         /*!<RX buffer Not Empty Interrupt Enable */
+#define SPI_CR2_TXEIE_Pos           (7U)                                       
+#define SPI_CR2_TXEIE_Msk           (0x1UL << SPI_CR2_TXEIE_Pos)                /*!< 0x00000080 */
+#define SPI_CR2_TXEIE               SPI_CR2_TXEIE_Msk                          /*!<Tx buffer Empty Interrupt Enable     */
+
+/********************  Bit definition for SPI_SR register  ********************/
+#define SPI_SR_RXNE_Pos             (0U)                                       
+#define SPI_SR_RXNE_Msk             (0x1UL << SPI_SR_RXNE_Pos)                  /*!< 0x00000001 */
+#define SPI_SR_RXNE                 SPI_SR_RXNE_Msk                            /*!<Receive buffer Not Empty */
+#define SPI_SR_TXE_Pos              (1U)                                       
+#define SPI_SR_TXE_Msk              (0x1UL << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
+#define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!<Transmit buffer Empty    */
+#define SPI_SR_CHSIDE_Pos           (2U)                                       
+#define SPI_SR_CHSIDE_Msk           (0x1UL << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
+#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!<Channel side             */
+#define SPI_SR_UDR_Pos              (3U)                                       
+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<Underrun flag            */
+#define SPI_SR_CRCERR_Pos           (4U)                                       
+#define SPI_SR_CRCERR_Msk           (0x1UL << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
+#define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!<CRC Error flag           */
+#define SPI_SR_MODF_Pos             (5U)                                       
+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                  /*!< 0x00000020 */
+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode fault               */
+#define SPI_SR_OVR_Pos              (6U)                                       
+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                   /*!< 0x00000040 */
+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Overrun flag             */
+#define SPI_SR_BSY_Pos              (7U)                                       
+#define SPI_SR_BSY_Msk              (0x1UL << SPI_SR_BSY_Pos)                   /*!< 0x00000080 */
+#define SPI_SR_BSY                  SPI_SR_BSY_Msk                             /*!<Busy flag                */
+#define SPI_SR_FRE_Pos              (8U)                                       
+#define SPI_SR_FRE_Msk              (0x1UL << SPI_SR_FRE_Pos)                   /*!< 0x00000100 */
+#define SPI_SR_FRE                  SPI_SR_FRE_Msk                             /*!<Frame format error flag  */
+
+/********************  Bit definition for SPI_DR register  ********************/
+#define SPI_DR_DR_Pos               (0U)                                       
+#define SPI_DR_DR_Msk               (0xFFFFUL << SPI_DR_DR_Pos)                 /*!< 0x0000FFFF */
+#define SPI_DR_DR                   SPI_DR_DR_Msk                              /*!<Data Register           */
+
+/*******************  Bit definition for SPI_CRCPR register  ******************/
+#define SPI_CRCPR_CRCPOLY_Pos       (0U)                                       
+#define SPI_CRCPR_CRCPOLY_Msk       (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)         /*!< 0x0000FFFF */
+#define SPI_CRCPR_CRCPOLY           SPI_CRCPR_CRCPOLY_Msk                      /*!<CRC polynomial register */
+
+/******************  Bit definition for SPI_RXCRCR register  ******************/
+#define SPI_RXCRCR_RXCRC_Pos        (0U)                                       
+#define SPI_RXCRCR_RXCRC_Msk        (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)          /*!< 0x0000FFFF */
+#define SPI_RXCRCR_RXCRC            SPI_RXCRCR_RXCRC_Msk                       /*!<Rx CRC Register         */
+
+/******************  Bit definition for SPI_TXCRCR register  ******************/
+#define SPI_TXCRCR_TXCRC_Pos        (0U)                                       
+#define SPI_TXCRCR_TXCRC_Msk        (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)          /*!< 0x0000FFFF */
+#define SPI_TXCRCR_TXCRC            SPI_TXCRCR_TXCRC_Msk                       /*!<Tx CRC Register         */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define SPI_I2SCFGR_CHLEN_Pos       (0U)                                       
+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)            /*!< 0x00000001 */
+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN_Pos      (1U)                                       
+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000006 */
+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] bits (Data length to be transferred)  */
+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000002 */
+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000004 */
+
+#define SPI_I2SCFGR_CKPOL_Pos       (3U)                                       
+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)            /*!< 0x00000008 */
+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<steady state clock polarity               */
+
+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)                                       
+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000030 */
+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */
+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */
+
+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)                                       
+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)          /*!< 0x00000080 */
+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                 */
+
+#define SPI_I2SCFGR_I2SCFG_Pos      (8U)                                       
+#define SPI_I2SCFGR_I2SCFG_Msk      (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000300 */
+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000100 */
+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000200 */
+
+#define SPI_I2SCFGR_I2SE_Pos        (10U)                                      
+#define SPI_I2SCFGR_I2SE_Msk        (0x1UL << SPI_I2SCFGR_I2SE_Pos)             /*!< 0x00000400 */
+#define SPI_I2SCFGR_I2SE            SPI_I2SCFGR_I2SE_Msk                       /*!<I2S Enable         */
+#define SPI_I2SCFGR_I2SMOD_Pos      (11U)                                      
+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)           /*!< 0x00000800 */
+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define SPI_I2SPR_I2SDIV_Pos        (0U)                                       
+#define SPI_I2SPR_I2SDIV_Msk        (0xFFUL << SPI_I2SPR_I2SDIV_Pos)            /*!< 0x000000FF */
+#define SPI_I2SPR_I2SDIV            SPI_I2SPR_I2SDIV_Msk                       /*!<I2S Linear prescaler         */
+#define SPI_I2SPR_ODD_Pos           (8U)                                       
+#define SPI_I2SPR_ODD_Msk           (0x1UL << SPI_I2SPR_ODD_Pos)                /*!< 0x00000100 */
+#define SPI_I2SPR_ODD               SPI_I2SPR_ODD_Msk                          /*!<Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE_Pos         (9U)                                       
+#define SPI_I2SPR_MCKOE_Msk         (0x1UL << SPI_I2SPR_MCKOE_Pos)              /*!< 0x00000200 */
+#define SPI_I2SPR_MCKOE             SPI_I2SPR_MCKOE_Msk                        /*!<Master Clock Output Enable   */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                 SYSCFG                                     */
+/*                                                                            */
+/******************************************************************************/
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/
+#define SYSCFG_MEMRMP_MEM_MODE_Pos           (0U)                              
+#define SYSCFG_MEMRMP_MEM_MODE_Msk           (0x3UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000003 */
+#define SYSCFG_MEMRMP_MEM_MODE               SYSCFG_MEMRMP_MEM_MODE_Msk        /*!< SYSCFG_Memory Remap Config */
+#define SYSCFG_MEMRMP_MEM_MODE_0             (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
+#define SYSCFG_MEMRMP_MEM_MODE_1             (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
+/******************  Bit definition for SYSCFG_PMC register  ******************/
+#define SYSCFG_PMC_MII_RMII_SEL_Pos          (23U)                             
+#define SYSCFG_PMC_MII_RMII_SEL_Msk          (0x1UL << SYSCFG_PMC_MII_RMII_SEL_Pos) /*!< 0x00800000 */
+#define SYSCFG_PMC_MII_RMII_SEL              SYSCFG_PMC_MII_RMII_SEL_Msk       /*!<Ethernet PHY interface selection */
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
+#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL    
+
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
+#define SYSCFG_EXTICR1_EXTI0_Pos             (0U)                              
+#define SYSCFG_EXTICR1_EXTI0_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR1_EXTI0                 SYSCFG_EXTICR1_EXTI0_Msk          /*!<EXTI 0 configuration */
+#define SYSCFG_EXTICR1_EXTI1_Pos             (4U)                              
+#define SYSCFG_EXTICR1_EXTI1_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR1_EXTI1                 SYSCFG_EXTICR1_EXTI1_Msk          /*!<EXTI 1 configuration */
+#define SYSCFG_EXTICR1_EXTI2_Pos             (8U)                              
+#define SYSCFG_EXTICR1_EXTI2_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR1_EXTI2                 SYSCFG_EXTICR1_EXTI2_Msk          /*!<EXTI 2 configuration */
+#define SYSCFG_EXTICR1_EXTI3_Pos             (12U)                             
+#define SYSCFG_EXTICR1_EXTI3_Msk             (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR1_EXTI3                 SYSCFG_EXTICR1_EXTI3_Msk          /*!<EXTI 3 configuration */
+/**
+  * @brief   EXTI0 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI0_PA              0x0000U                           /*!<PA[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PB              0x0001U                           /*!<PB[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PC              0x0002U                           /*!<PC[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PD              0x0003U                           /*!<PD[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PE              0x0004U                           /*!<PE[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PF              0x0005U                           /*!<PF[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PG              0x0006U                           /*!<PG[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PH              0x0007U                           /*!<PH[0] pin */
+#define SYSCFG_EXTICR1_EXTI0_PI              0x0008U                           /*!<PI[0] pin */
+
+/**
+  * @brief   EXTI1 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI1_PA              0x0000U                           /*!<PA[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PB              0x0010U                           /*!<PB[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PC              0x0020U                           /*!<PC[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PD              0x0030U                           /*!<PD[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PE              0x0040U                           /*!<PE[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PF              0x0050U                           /*!<PF[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PG              0x0060U                           /*!<PG[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PH              0x0070U                           /*!<PH[1] pin */
+#define SYSCFG_EXTICR1_EXTI1_PI              0x0080U                           /*!<PI[1] pin */
+
+/**
+  * @brief   EXTI2 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI2_PA              0x0000U                           /*!<PA[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PB              0x0100U                           /*!<PB[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PC              0x0200U                           /*!<PC[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PD              0x0300U                           /*!<PD[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PE              0x0400U                           /*!<PE[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PF              0x0500U                           /*!<PF[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PG              0x0600U                           /*!<PG[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PH              0x0700U                           /*!<PH[2] pin */
+#define SYSCFG_EXTICR1_EXTI2_PI              0x0800U                           /*!<PI[2] pin */
+
+/**
+  * @brief   EXTI3 configuration  
+  */
+#define SYSCFG_EXTICR1_EXTI3_PA              0x0000U                           /*!<PA[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PB              0x1000U                           /*!<PB[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PC              0x2000U                           /*!<PC[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PD              0x3000U                           /*!<PD[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PE              0x4000U                           /*!<PE[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PF              0x5000U                           /*!<PF[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PG              0x6000U                           /*!<PG[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PH              0x7000U                           /*!<PH[3] pin */
+#define SYSCFG_EXTICR1_EXTI3_PI              0x8000U                           /*!<PI[3] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/
+#define SYSCFG_EXTICR2_EXTI4_Pos             (0U)                              
+#define SYSCFG_EXTICR2_EXTI4_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR2_EXTI4                 SYSCFG_EXTICR2_EXTI4_Msk          /*!<EXTI 4 configuration */
+#define SYSCFG_EXTICR2_EXTI5_Pos             (4U)                              
+#define SYSCFG_EXTICR2_EXTI5_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR2_EXTI5                 SYSCFG_EXTICR2_EXTI5_Msk          /*!<EXTI 5 configuration */
+#define SYSCFG_EXTICR2_EXTI6_Pos             (8U)                              
+#define SYSCFG_EXTICR2_EXTI6_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR2_EXTI6                 SYSCFG_EXTICR2_EXTI6_Msk          /*!<EXTI 6 configuration */
+#define SYSCFG_EXTICR2_EXTI7_Pos             (12U)                             
+#define SYSCFG_EXTICR2_EXTI7_Msk             (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR2_EXTI7                 SYSCFG_EXTICR2_EXTI7_Msk          /*!<EXTI 7 configuration */
+
+/**
+  * @brief   EXTI4 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI4_PA              0x0000U                           /*!<PA[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PB              0x0001U                           /*!<PB[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PC              0x0002U                           /*!<PC[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PD              0x0003U                           /*!<PD[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PE              0x0004U                           /*!<PE[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PF              0x0005U                           /*!<PF[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PG              0x0006U                           /*!<PG[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PH              0x0007U                           /*!<PH[4] pin */
+#define SYSCFG_EXTICR2_EXTI4_PI              0x0008U                           /*!<PI[4] pin */
+
+/**
+  * @brief   EXTI5 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI5_PA              0x0000U                           /*!<PA[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PB              0x0010U                           /*!<PB[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PC              0x0020U                           /*!<PC[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PD              0x0030U                           /*!<PD[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PE              0x0040U                           /*!<PE[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PF              0x0050U                           /*!<PF[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PG              0x0060U                           /*!<PG[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PH              0x0070U                           /*!<PH[5] pin */
+#define SYSCFG_EXTICR2_EXTI5_PI              0x0080U                           /*!<PI[5] pin */
+
+/**
+  * @brief   EXTI6 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI6_PA              0x0000U                           /*!<PA[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PB              0x0100U                           /*!<PB[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PC              0x0200U                           /*!<PC[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PD              0x0300U                           /*!<PD[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PE              0x0400U                           /*!<PE[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PF              0x0500U                           /*!<PF[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PG              0x0600U                           /*!<PG[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PH              0x0700U                           /*!<PH[6] pin */
+#define SYSCFG_EXTICR2_EXTI6_PI              0x0800U                           /*!<PI[6] pin */
+
+/**
+  * @brief   EXTI7 configuration  
+  */
+#define SYSCFG_EXTICR2_EXTI7_PA              0x0000U                           /*!<PA[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PB              0x1000U                           /*!<PB[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PC              0x2000U                           /*!<PC[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PD              0x3000U                           /*!<PD[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PE              0x4000U                           /*!<PE[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PF              0x5000U                           /*!<PF[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PG              0x6000U                           /*!<PG[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PH              0x7000U                           /*!<PH[7] pin */
+#define SYSCFG_EXTICR2_EXTI7_PI              0x8000U                           /*!<PI[7] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/
+#define SYSCFG_EXTICR3_EXTI8_Pos             (0U)                              
+#define SYSCFG_EXTICR3_EXTI8_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR3_EXTI8                 SYSCFG_EXTICR3_EXTI8_Msk          /*!<EXTI 8 configuration */
+#define SYSCFG_EXTICR3_EXTI9_Pos             (4U)                              
+#define SYSCFG_EXTICR3_EXTI9_Msk             (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR3_EXTI9                 SYSCFG_EXTICR3_EXTI9_Msk          /*!<EXTI 9 configuration */
+#define SYSCFG_EXTICR3_EXTI10_Pos            (8U)                              
+#define SYSCFG_EXTICR3_EXTI10_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR3_EXTI10                SYSCFG_EXTICR3_EXTI10_Msk         /*!<EXTI 10 configuration */
+#define SYSCFG_EXTICR3_EXTI11_Pos            (12U)                             
+#define SYSCFG_EXTICR3_EXTI11_Msk            (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR3_EXTI11                SYSCFG_EXTICR3_EXTI11_Msk         /*!<EXTI 11 configuration */
+
+/**
+  * @brief   EXTI8 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI8_PA              0x0000U                           /*!<PA[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PB              0x0001U                           /*!<PB[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PC              0x0002U                           /*!<PC[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PD              0x0003U                           /*!<PD[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PE              0x0004U                           /*!<PE[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PF              0x0005U                           /*!<PF[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PG              0x0006U                           /*!<PG[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PH              0x0007U                           /*!<PH[8] pin */
+#define SYSCFG_EXTICR3_EXTI8_PI              0x0008U                           /*!<PI[8] pin */
+
+/**
+  * @brief   EXTI9 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI9_PA              0x0000U                           /*!<PA[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PB              0x0010U                           /*!<PB[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PC              0x0020U                           /*!<PC[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PD              0x0030U                           /*!<PD[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PE              0x0040U                           /*!<PE[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PF              0x0050U                           /*!<PF[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PG              0x0060U                           /*!<PG[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PH              0x0070U                           /*!<PH[9] pin */
+#define SYSCFG_EXTICR3_EXTI9_PI              0x0080U                           /*!<PI[9] pin */
+
+/**
+  * @brief   EXTI10 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI10_PA             0x0000U                           /*!<PA[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PB             0x0100U                           /*!<PB[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PC             0x0200U                           /*!<PC[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PD             0x0300U                           /*!<PD[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PE             0x0400U                           /*!<PE[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PF             0x0500U                           /*!<PF[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PG             0x0600U                           /*!<PG[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PH             0x0700U                           /*!<PH[10] pin */
+#define SYSCFG_EXTICR3_EXTI10_PI             0x0800U                           /*!<PI[10] pin */
+
+/**
+  * @brief   EXTI11 configuration  
+  */
+#define SYSCFG_EXTICR3_EXTI11_PA             0x0000U                           /*!<PA[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PB             0x1000U                           /*!<PB[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PC             0x2000U                           /*!<PC[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PD             0x3000U                           /*!<PD[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PE             0x4000U                           /*!<PE[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PF             0x5000U                           /*!<PF[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PG             0x6000U                           /*!<PG[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PH             0x7000U                           /*!<PH[11] pin */
+#define SYSCFG_EXTICR3_EXTI11_PI             0x8000U                           /*!<PI[11] pin */
+
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/
+#define SYSCFG_EXTICR4_EXTI12_Pos            (0U)                              
+#define SYSCFG_EXTICR4_EXTI12_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
+#define SYSCFG_EXTICR4_EXTI12                SYSCFG_EXTICR4_EXTI12_Msk         /*!<EXTI 12 configuration */
+#define SYSCFG_EXTICR4_EXTI13_Pos            (4U)                              
+#define SYSCFG_EXTICR4_EXTI13_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
+#define SYSCFG_EXTICR4_EXTI13                SYSCFG_EXTICR4_EXTI13_Msk         /*!<EXTI 13 configuration */
+#define SYSCFG_EXTICR4_EXTI14_Pos            (8U)                              
+#define SYSCFG_EXTICR4_EXTI14_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
+#define SYSCFG_EXTICR4_EXTI14                SYSCFG_EXTICR4_EXTI14_Msk         /*!<EXTI 14 configuration */
+#define SYSCFG_EXTICR4_EXTI15_Pos            (12U)                             
+#define SYSCFG_EXTICR4_EXTI15_Msk            (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
+#define SYSCFG_EXTICR4_EXTI15                SYSCFG_EXTICR4_EXTI15_Msk         /*!<EXTI 15 configuration */
+
+/**
+  * @brief   EXTI12 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI12_PA             0x0000U                           /*!<PA[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PB             0x0001U                           /*!<PB[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PC             0x0002U                           /*!<PC[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PD             0x0003U                           /*!<PD[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PE             0x0004U                           /*!<PE[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PF             0x0005U                           /*!<PF[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PG             0x0006U                           /*!<PG[12] pin */
+#define SYSCFG_EXTICR4_EXTI12_PH             0x0007U                           /*!<PH[12] pin */
+
+/**
+  * @brief   EXTI13 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI13_PA             0x0000U                           /*!<PA[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PB             0x0010U                           /*!<PB[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PC             0x0020U                           /*!<PC[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PD             0x0030U                           /*!<PD[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PE             0x0040U                           /*!<PE[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PF             0x0050U                           /*!<PF[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PG             0x0060U                           /*!<PG[13] pin */
+#define SYSCFG_EXTICR4_EXTI13_PH             0x0070U                           /*!<PH[13] pin */
+
+/**
+  * @brief   EXTI14 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI14_PA             0x0000U                           /*!<PA[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PB             0x0100U                           /*!<PB[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PC             0x0200U                           /*!<PC[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PD             0x0300U                           /*!<PD[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PE             0x0400U                           /*!<PE[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PF             0x0500U                           /*!<PF[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PG             0x0600U                           /*!<PG[14] pin */
+#define SYSCFG_EXTICR4_EXTI14_PH             0x0700U                           /*!<PH[14] pin */
+
+/**
+  * @brief   EXTI15 configuration  
+  */
+#define SYSCFG_EXTICR4_EXTI15_PA             0x0000U                           /*!<PA[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PB             0x1000U                           /*!<PB[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PC             0x2000U                           /*!<PC[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PD             0x3000U                           /*!<PD[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PE             0x4000U                           /*!<PE[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PF             0x5000U                           /*!<PF[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PG             0x6000U                           /*!<PG[15] pin */
+#define SYSCFG_EXTICR4_EXTI15_PH             0x7000U                           /*!<PH[15] pin */
+
+/******************  Bit definition for SYSCFG_CMPCR register  ****************/
+#define SYSCFG_CMPCR_CMP_PD_Pos              (0U)                              
+#define SYSCFG_CMPCR_CMP_PD_Msk              (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */
+#define SYSCFG_CMPCR_CMP_PD                  SYSCFG_CMPCR_CMP_PD_Msk           /*!<Compensation cell ready flag */
+#define SYSCFG_CMPCR_READY_Pos               (8U)                              
+#define SYSCFG_CMPCR_READY_Msk               (0x1UL << SYSCFG_CMPCR_READY_Pos)  /*!< 0x00000100 */
+#define SYSCFG_CMPCR_READY                   SYSCFG_CMPCR_READY_Msk            /*!<Compensation cell power-down */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                    TIM                                     */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for TIM_CR1 register  ********************/
+#define TIM_CR1_CEN_Pos           (0U)                                         
+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                    /*!< 0x00000001 */
+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable        */
+#define TIM_CR1_UDIS_Pos          (1U)                                         
+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                   /*!< 0x00000002 */
+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable        */
+#define TIM_CR1_URS_Pos           (2U)                                         
+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                    /*!< 0x00000004 */
+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */
+#define TIM_CR1_OPM_Pos           (3U)                                         
+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                    /*!< 0x00000008 */
+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode        */
+#define TIM_CR1_DIR_Pos           (4U)                                         
+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                    /*!< 0x00000010 */
+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction             */
+
+#define TIM_CR1_CMS_Pos           (5U)                                         
+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000060 */
+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x0020 */
+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x0040 */
+
+#define TIM_CR1_ARPE_Pos          (7U)                                         
+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                   /*!< 0x00000080 */
+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable     */
+
+#define TIM_CR1_CKD_Pos           (8U)                                         
+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000300 */
+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */
+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x0100 */
+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x0200 */
+
+/*******************  Bit definition for TIM_CR2 register  ********************/
+#define TIM_CR2_CCPC_Pos          (0U)                                         
+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                   /*!< 0x00000001 */
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control        */
+#define TIM_CR2_CCUS_Pos          (2U)                                         
+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                   /*!< 0x00000004 */
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */
+#define TIM_CR2_CCDS_Pos          (3U)                                         
+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                   /*!< 0x00000008 */
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection            */
+
+#define TIM_CR2_MMS_Pos           (4U)                                         
+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000070 */
+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */
+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x0010 */
+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x0020 */
+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x0040 */
+
+#define TIM_CR2_TI1S_Pos          (7U)                                         
+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                   /*!< 0x00000080 */
+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */
+#define TIM_CR2_OIS1_Pos          (8U)                                         
+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                   /*!< 0x00000100 */
+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output)  */
+#define TIM_CR2_OIS1N_Pos         (9U)                                         
+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                  /*!< 0x00000200 */
+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */
+#define TIM_CR2_OIS2_Pos          (10U)                                        
+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                   /*!< 0x00000400 */
+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output)  */
+#define TIM_CR2_OIS2N_Pos         (11U)                                        
+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                  /*!< 0x00000800 */
+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */
+#define TIM_CR2_OIS3_Pos          (12U)                                        
+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                   /*!< 0x00001000 */
+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output)  */
+#define TIM_CR2_OIS3N_Pos         (13U)                                        
+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                  /*!< 0x00002000 */
+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */
+#define TIM_CR2_OIS4_Pos          (14U)                                        
+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                   /*!< 0x00004000 */
+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output)  */
+
+/*******************  Bit definition for TIM_SMCR register  *******************/
+#define TIM_SMCR_SMS_Pos          (0U)                                         
+#define TIM_SMCR_SMS_Msk          (0x7UL << TIM_SMCR_SMS_Pos)                   /*!< 0x00000007 */
+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection)    */
+#define TIM_SMCR_SMS_0            (0x1UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0001 */
+#define TIM_SMCR_SMS_1            (0x2UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0002 */
+#define TIM_SMCR_SMS_2            (0x4UL << TIM_SMCR_SMS_Pos)                   /*!< 0x0004 */
+
+#define TIM_SMCR_TS_Pos           (4U)                                         
+#define TIM_SMCR_TS_Msk           (0x7UL << TIM_SMCR_TS_Pos)                    /*!< 0x00000070 */
+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[2:0] bits (Trigger selection)        */
+#define TIM_SMCR_TS_0             (0x1UL << TIM_SMCR_TS_Pos)                    /*!< 0x0010 */
+#define TIM_SMCR_TS_1             (0x2UL << TIM_SMCR_TS_Pos)                    /*!< 0x0020 */
+#define TIM_SMCR_TS_2             (0x4UL << TIM_SMCR_TS_Pos)                    /*!< 0x0040 */
+
+#define TIM_SMCR_MSM_Pos          (7U)                                         
+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                   /*!< 0x00000080 */
+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode                       */
+
+#define TIM_SMCR_ETF_Pos          (8U)                                         
+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000F00 */
+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */
+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0100 */
+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0200 */
+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0400 */
+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x0800 */
+
+#define TIM_SMCR_ETPS_Pos         (12U)                                        
+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00003000 */
+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x1000 */
+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x2000 */
+
+#define TIM_SMCR_ECE_Pos          (14U)                                        
+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                   /*!< 0x00004000 */
+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable     */
+#define TIM_SMCR_ETP_Pos          (15U)                                        
+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                   /*!< 0x00008000 */
+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */
+
+/*******************  Bit definition for TIM_DIER register  *******************/
+#define TIM_DIER_UIE_Pos          (0U)                                         
+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                   /*!< 0x00000001 */
+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */
+#define TIM_DIER_CC1IE_Pos        (1U)                                         
+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                 /*!< 0x00000002 */
+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable   */
+#define TIM_DIER_CC2IE_Pos        (2U)                                         
+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                 /*!< 0x00000004 */
+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable   */
+#define TIM_DIER_CC3IE_Pos        (3U)                                         
+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                 /*!< 0x00000008 */
+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable   */
+#define TIM_DIER_CC4IE_Pos        (4U)                                         
+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                 /*!< 0x00000010 */
+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable   */
+#define TIM_DIER_COMIE_Pos        (5U)                                         
+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                 /*!< 0x00000020 */
+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable                 */
+#define TIM_DIER_TIE_Pos          (6U)                                         
+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                   /*!< 0x00000040 */
+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable             */
+#define TIM_DIER_BIE_Pos          (7U)                                         
+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                   /*!< 0x00000080 */
+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable               */
+#define TIM_DIER_UDE_Pos          (8U)                                         
+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                   /*!< 0x00000100 */
+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable            */
+#define TIM_DIER_CC1DE_Pos        (9U)                                         
+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                 /*!< 0x00000200 */
+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */
+#define TIM_DIER_CC2DE_Pos        (10U)                                        
+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                 /*!< 0x00000400 */
+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */
+#define TIM_DIER_CC3DE_Pos        (11U)                                        
+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                 /*!< 0x00000800 */
+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */
+#define TIM_DIER_CC4DE_Pos        (12U)                                        
+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                 /*!< 0x00001000 */
+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */
+#define TIM_DIER_COMDE_Pos        (13U)                                        
+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                 /*!< 0x00002000 */
+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable               */
+#define TIM_DIER_TDE_Pos          (14U)                                        
+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                   /*!< 0x00004000 */
+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable           */
+
+/********************  Bit definition for TIM_SR register  ********************/
+#define TIM_SR_UIF_Pos            (0U)                                         
+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                     /*!< 0x00000001 */
+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag              */
+#define TIM_SR_CC1IF_Pos          (1U)                                         
+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                   /*!< 0x00000002 */
+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag   */
+#define TIM_SR_CC2IF_Pos          (2U)                                         
+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                   /*!< 0x00000004 */
+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag   */
+#define TIM_SR_CC3IF_Pos          (3U)                                         
+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                   /*!< 0x00000008 */
+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag   */
+#define TIM_SR_CC4IF_Pos          (4U)                                         
+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                   /*!< 0x00000010 */
+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag   */
+#define TIM_SR_COMIF_Pos          (5U)                                         
+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                   /*!< 0x00000020 */
+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag                 */
+#define TIM_SR_TIF_Pos            (6U)                                         
+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                     /*!< 0x00000040 */
+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag             */
+#define TIM_SR_BIF_Pos            (7U)                                         
+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                     /*!< 0x00000080 */
+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag               */
+#define TIM_SR_CC1OF_Pos          (9U)                                         
+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                   /*!< 0x00000200 */
+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */
+#define TIM_SR_CC2OF_Pos          (10U)                                        
+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                   /*!< 0x00000400 */
+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */
+#define TIM_SR_CC3OF_Pos          (11U)                                        
+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                   /*!< 0x00000800 */
+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */
+#define TIM_SR_CC4OF_Pos          (12U)                                        
+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                   /*!< 0x00001000 */
+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_EGR register  ********************/
+#define TIM_EGR_UG_Pos            (0U)                                         
+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                     /*!< 0x00000001 */
+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation                         */
+#define TIM_EGR_CC1G_Pos          (1U)                                         
+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                   /*!< 0x00000002 */
+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation              */
+#define TIM_EGR_CC2G_Pos          (2U)                                         
+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                   /*!< 0x00000004 */
+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation              */
+#define TIM_EGR_CC3G_Pos          (3U)                                         
+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                   /*!< 0x00000008 */
+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation              */
+#define TIM_EGR_CC4G_Pos          (4U)                                         
+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                   /*!< 0x00000010 */
+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation              */
+#define TIM_EGR_COMG_Pos          (5U)                                         
+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                   /*!< 0x00000020 */
+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */
+#define TIM_EGR_TG_Pos            (6U)                                         
+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                     /*!< 0x00000040 */
+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation                        */
+#define TIM_EGR_BG_Pos            (7U)                                         
+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                     /*!< 0x00000080 */
+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation                          */
+
+/******************  Bit definition for TIM_CCMR1 register  *******************/
+#define TIM_CCMR1_CC1S_Pos        (0U)                                         
+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0001 */
+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x0002 */
+
+#define TIM_CCMR1_OC1FE_Pos       (2U)                                         
+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable                 */
+#define TIM_CCMR1_OC1PE_Pos       (3U)                                         
+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable              */
+
+#define TIM_CCMR1_OC1M_Pos        (4U)                                         
+#define TIM_CCMR1_OC1M_Msk        (0x7UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x00000070 */
+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
+#define TIM_CCMR1_OC1M_0          (0x1UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0010 */
+#define TIM_CCMR1_OC1M_1          (0x2UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0020 */
+#define TIM_CCMR1_OC1M_2          (0x4UL << TIM_CCMR1_OC1M_Pos)                 /*!< 0x0040 */
+
+#define TIM_CCMR1_OC1CE_Pos       (7U)                                         
+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable                 */
+
+#define TIM_CCMR1_CC2S_Pos        (8U)                                         
+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0100 */
+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x0200 */
+
+#define TIM_CCMR1_OC2FE_Pos       (10U)                                        
+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable                 */
+#define TIM_CCMR1_OC2PE_Pos       (11U)                                        
+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable              */
+
+#define TIM_CCMR1_OC2M_Pos        (12U)                                        
+#define TIM_CCMR1_OC2M_Msk        (0x7UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x00007000 */
+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
+#define TIM_CCMR1_OC2M_0          (0x1UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x1000 */
+#define TIM_CCMR1_OC2M_1          (0x2UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x2000 */
+#define TIM_CCMR1_OC2M_2          (0x4UL << TIM_CCMR1_OC2M_Pos)                 /*!< 0x4000 */
+
+#define TIM_CCMR1_OC2CE_Pos       (15U)                                        
+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR1_IC1PSC_Pos      (2U)                                         
+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0004 */
+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x0008 */
+
+#define TIM_CCMR1_IC1F_Pos        (4U)                                         
+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0010 */
+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0020 */
+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0040 */
+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x0080 */
+
+#define TIM_CCMR1_IC2PSC_Pos      (10U)                                        
+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0400 */
+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x0800 */
+
+#define TIM_CCMR1_IC2F_Pos        (12U)                                        
+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x1000 */
+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x2000 */
+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x4000 */
+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x8000 */
+
+/******************  Bit definition for TIM_CCMR2 register  *******************/
+#define TIM_CCMR2_CC3S_Pos        (0U)                                         
+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000003 */
+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0001 */
+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x0002 */
+
+#define TIM_CCMR2_OC3FE_Pos       (2U)                                         
+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)                /*!< 0x00000004 */
+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable           */
+#define TIM_CCMR2_OC3PE_Pos       (3U)                                         
+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)                /*!< 0x00000008 */
+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable        */
+
+#define TIM_CCMR2_OC3M_Pos        (4U)                                         
+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000070 */
+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0010 */
+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0020 */
+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x0040 */
+
+#define TIM_CCMR2_OC3CE_Pos       (7U)                                         
+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)                /*!< 0x00000080 */
+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */
+
+#define TIM_CCMR2_CC4S_Pos        (8U)                                         
+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000300 */
+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0100 */
+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x0200 */
+
+#define TIM_CCMR2_OC4FE_Pos       (10U)                                        
+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)                /*!< 0x00000400 */
+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable    */
+#define TIM_CCMR2_OC4PE_Pos       (11U)                                        
+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)                /*!< 0x00000800 */
+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */
+
+#define TIM_CCMR2_OC4M_Pos        (12U)                                        
+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00007000 */
+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x1000 */
+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x2000 */
+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x4000 */
+
+#define TIM_CCMR2_OC4CE_Pos       (15U)                                        
+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)                /*!< 0x00008000 */
+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */
+
+/*----------------------------------------------------------------------------*/
+
+#define TIM_CCMR2_IC3PSC_Pos      (2U)                                         
+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0000000C */
+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0004 */
+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x0008 */
+
+#define TIM_CCMR2_IC3F_Pos        (4U)                                         
+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x000000F0 */
+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0010 */
+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0020 */
+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0040 */
+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x0080 */
+
+#define TIM_CCMR2_IC4PSC_Pos      (10U)                                        
+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000C00 */
+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0400 */
+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x0800 */
+
+#define TIM_CCMR2_IC4F_Pos        (12U)                                        
+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x0000F000 */
+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x1000 */
+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x2000 */
+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x4000 */
+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x8000 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CCER_CC1E_Pos         (0U)                                         
+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                  /*!< 0x00000001 */
+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable                 */
+#define TIM_CCER_CC1P_Pos         (1U)                                         
+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                  /*!< 0x00000002 */
+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity               */
+#define TIM_CCER_CC1NE_Pos        (2U)                                         
+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                 /*!< 0x00000004 */
+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable   */
+#define TIM_CCER_CC1NP_Pos        (3U)                                         
+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                 /*!< 0x00000008 */
+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */
+#define TIM_CCER_CC2E_Pos         (4U)                                         
+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                  /*!< 0x00000010 */
+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable                 */
+#define TIM_CCER_CC2P_Pos         (5U)                                         
+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                  /*!< 0x00000020 */
+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity               */
+#define TIM_CCER_CC2NE_Pos        (6U)                                         
+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                 /*!< 0x00000040 */
+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable   */
+#define TIM_CCER_CC2NP_Pos        (7U)                                         
+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                 /*!< 0x00000080 */
+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */
+#define TIM_CCER_CC3E_Pos         (8U)                                         
+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                  /*!< 0x00000100 */
+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable                 */
+#define TIM_CCER_CC3P_Pos         (9U)                                         
+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                  /*!< 0x00000200 */
+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity               */
+#define TIM_CCER_CC3NE_Pos        (10U)                                        
+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                 /*!< 0x00000400 */
+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable   */
+#define TIM_CCER_CC3NP_Pos        (11U)                                        
+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                 /*!< 0x00000800 */
+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */
+#define TIM_CCER_CC4E_Pos         (12U)                                        
+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                  /*!< 0x00001000 */
+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable                 */
+#define TIM_CCER_CC4P_Pos         (13U)                                        
+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                  /*!< 0x00002000 */
+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity               */
+#define TIM_CCER_CC4NP_Pos        (15U)                                        
+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                 /*!< 0x00008000 */
+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT_CNT_Pos           (0U)                                             
+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)                 /*!< 0xFFFFFFFF */
+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                                  /*!<Counter Value            */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC_PSC_Pos           (0U)                                         
+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                 /*!< 0x0000FFFF */
+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value          */
+
+/*******************  Bit definition for TIM_ARR register  ********************/
+#define TIM_ARR_ARR_Pos           (0U)                                         
+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)             /*!< 0xFFFFFFFF */
+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RCR register  ********************/
+#define TIM_RCR_REP_Pos           (0U)                                         
+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                   /*!< 0x000000FF */
+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CCR1 register  *******************/
+#define TIM_CCR1_CCR1_Pos         (0U)                                         
+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value  */
+
+/*******************  Bit definition for TIM_CCR2 register  *******************/
+#define TIM_CCR2_CCR2_Pos         (0U)                                         
+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value  */
+
+/*******************  Bit definition for TIM_CCR3 register  *******************/
+#define TIM_CCR3_CCR3_Pos         (0U)                                         
+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value  */
+
+/*******************  Bit definition for TIM_CCR4 register  *******************/
+#define TIM_CCR4_CCR4_Pos         (0U)                                         
+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)               /*!< 0x0000FFFF */
+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value  */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_BDTR_DTG_Pos          (0U)                                         
+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                  /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0001 */
+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0002 */
+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0004 */
+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0008 */
+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0010 */
+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0020 */
+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0040 */
+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x0080 */
+
+#define TIM_BDTR_LOCK_Pos         (8U)                                         
+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0100 */
+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x0200 */
+
+#define TIM_BDTR_OSSI_Pos         (10U)                                        
+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                  /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)                                        
+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                  /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode  */
+#define TIM_BDTR_BKE_Pos          (12U)                                        
+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                   /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable                      */
+#define TIM_BDTR_BKP_Pos          (13U)                                        
+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                   /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity                    */
+#define TIM_BDTR_AOE_Pos          (14U)                                        
+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                   /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable           */
+#define TIM_BDTR_MOE_Pos          (15U)                                        
+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                   /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable                */
+
+/*******************  Bit definition for TIM_DCR register  ********************/
+#define TIM_DCR_DBA_Pos           (0U)                                         
+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                   /*!< 0x0000001F */
+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */
+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x0001 */
+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x0002 */
+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x0004 */
+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x0008 */
+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x0010 */
+
+#define TIM_DCR_DBL_Pos           (8U)                                         
+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                   /*!< 0x00001F00 */
+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x0100 */
+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x0200 */
+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x0400 */
+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x0800 */
+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x1000 */
+
+/*******************  Bit definition for TIM_DMAR register  *******************/
+#define TIM_DMAR_DMAB_Pos         (0U)                                         
+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)               /*!< 0x0000FFFF */
+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses                    */
+
+/*******************  Bit definition for TIM_OR register  *********************/
+#define TIM_OR_TI1_RMP_Pos        (0U)                                          
+#define TIM_OR_TI1_RMP_Msk        (0x3UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000003 */
+#define TIM_OR_TI1_RMP            TIM_OR_TI1_RMP_Msk                           /*!< TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */
+#define TIM_OR_TI1_RMP_0          (0x1UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000001 */
+#define TIM_OR_TI1_RMP_1          (0x2UL << TIM_OR_TI1_RMP_Pos)                 /*!< 0x00000002 */
+
+#define TIM_OR_TI4_RMP_Pos        (6U)                                         
+#define TIM_OR_TI4_RMP_Msk        (0x3UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x000000C0 */
+#define TIM_OR_TI4_RMP            TIM_OR_TI4_RMP_Msk                           /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */
+#define TIM_OR_TI4_RMP_0          (0x1UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0040 */
+#define TIM_OR_TI4_RMP_1          (0x2UL << TIM_OR_TI4_RMP_Pos)                 /*!< 0x0080 */
+#define TIM_OR_ITR1_RMP_Pos       (10U)                                        
+#define TIM_OR_ITR1_RMP_Msk       (0x3UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x00000C00 */
+#define TIM_OR_ITR1_RMP           TIM_OR_ITR1_RMP_Msk                          /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
+#define TIM_OR_ITR1_RMP_0         (0x1UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0400 */
+#define TIM_OR_ITR1_RMP_1         (0x2UL << TIM_OR_ITR1_RMP_Pos)                /*!< 0x0800 */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for USART_SR register  *******************/
+#define USART_SR_PE_Pos               (0U)                                     
+#define USART_SR_PE_Msk               (0x1UL << USART_SR_PE_Pos)                /*!< 0x00000001 */
+#define USART_SR_PE                   USART_SR_PE_Msk                          /*!<Parity Error                 */
+#define USART_SR_FE_Pos               (1U)                                     
+#define USART_SR_FE_Msk               (0x1UL << USART_SR_FE_Pos)                /*!< 0x00000002 */
+#define USART_SR_FE                   USART_SR_FE_Msk                          /*!<Framing Error                */
+#define USART_SR_NE_Pos               (2U)                                     
+#define USART_SR_NE_Msk               (0x1UL << USART_SR_NE_Pos)                /*!< 0x00000004 */
+#define USART_SR_NE                   USART_SR_NE_Msk                          /*!<Noise Error Flag             */
+#define USART_SR_ORE_Pos              (3U)                                     
+#define USART_SR_ORE_Msk              (0x1UL << USART_SR_ORE_Pos)               /*!< 0x00000008 */
+#define USART_SR_ORE                  USART_SR_ORE_Msk                         /*!<OverRun Error                */
+#define USART_SR_IDLE_Pos             (4U)                                     
+#define USART_SR_IDLE_Msk             (0x1UL << USART_SR_IDLE_Pos)              /*!< 0x00000010 */
+#define USART_SR_IDLE                 USART_SR_IDLE_Msk                        /*!<IDLE line detected           */
+#define USART_SR_RXNE_Pos             (5U)                                     
+#define USART_SR_RXNE_Msk             (0x1UL << USART_SR_RXNE_Pos)              /*!< 0x00000020 */
+#define USART_SR_RXNE                 USART_SR_RXNE_Msk                        /*!<Read Data Register Not Empty */
+#define USART_SR_TC_Pos               (6U)                                     
+#define USART_SR_TC_Msk               (0x1UL << USART_SR_TC_Pos)                /*!< 0x00000040 */
+#define USART_SR_TC                   USART_SR_TC_Msk                          /*!<Transmission Complete        */
+#define USART_SR_TXE_Pos              (7U)                                     
+#define USART_SR_TXE_Msk              (0x1UL << USART_SR_TXE_Pos)               /*!< 0x00000080 */
+#define USART_SR_TXE                  USART_SR_TXE_Msk                         /*!<Transmit Data Register Empty */
+#define USART_SR_LBD_Pos              (8U)                                     
+#define USART_SR_LBD_Msk              (0x1UL << USART_SR_LBD_Pos)               /*!< 0x00000100 */
+#define USART_SR_LBD                  USART_SR_LBD_Msk                         /*!<LIN Break Detection Flag     */
+#define USART_SR_CTS_Pos              (9U)                                     
+#define USART_SR_CTS_Msk              (0x1UL << USART_SR_CTS_Pos)               /*!< 0x00000200 */
+#define USART_SR_CTS                  USART_SR_CTS_Msk                         /*!<CTS Flag                     */
+
+/*******************  Bit definition for USART_DR register  *******************/
+#define USART_DR_DR_Pos               (0U)                                     
+#define USART_DR_DR_Msk               (0x1FFUL << USART_DR_DR_Pos)              /*!< 0x000001FF */
+#define USART_DR_DR                   USART_DR_DR_Msk                          /*!<Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_Fraction_Pos    (0U)                                     
+#define USART_BRR_DIV_Fraction_Msk    (0xFUL << USART_BRR_DIV_Fraction_Pos)     /*!< 0x0000000F */
+#define USART_BRR_DIV_Fraction        USART_BRR_DIV_Fraction_Msk               /*!<Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa_Pos    (4U)                                     
+#define USART_BRR_DIV_Mantissa_Msk    (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)   /*!< 0x0000FFF0 */
+#define USART_BRR_DIV_Mantissa        USART_BRR_DIV_Mantissa_Msk               /*!<Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CR1 register  *******************/
+#define USART_CR1_SBK_Pos             (0U)                                     
+#define USART_CR1_SBK_Msk             (0x1UL << USART_CR1_SBK_Pos)              /*!< 0x00000001 */
+#define USART_CR1_SBK                 USART_CR1_SBK_Msk                        /*!<Send Break                             */
+#define USART_CR1_RWU_Pos             (1U)                                     
+#define USART_CR1_RWU_Msk             (0x1UL << USART_CR1_RWU_Pos)              /*!< 0x00000002 */
+#define USART_CR1_RWU                 USART_CR1_RWU_Msk                        /*!<Receiver wakeup                        */
+#define USART_CR1_RE_Pos              (2U)                                     
+#define USART_CR1_RE_Msk              (0x1UL << USART_CR1_RE_Pos)               /*!< 0x00000004 */
+#define USART_CR1_RE                  USART_CR1_RE_Msk                         /*!<Receiver Enable                        */
+#define USART_CR1_TE_Pos              (3U)                                     
+#define USART_CR1_TE_Msk              (0x1UL << USART_CR1_TE_Pos)               /*!< 0x00000008 */
+#define USART_CR1_TE                  USART_CR1_TE_Msk                         /*!<Transmitter Enable                     */
+#define USART_CR1_IDLEIE_Pos          (4U)                                     
+#define USART_CR1_IDLEIE_Msk          (0x1UL << USART_CR1_IDLEIE_Pos)           /*!< 0x00000010 */
+#define USART_CR1_IDLEIE              USART_CR1_IDLEIE_Msk                     /*!<IDLE Interrupt Enable                  */
+#define USART_CR1_RXNEIE_Pos          (5U)                                     
+#define USART_CR1_RXNEIE_Msk          (0x1UL << USART_CR1_RXNEIE_Pos)           /*!< 0x00000020 */
+#define USART_CR1_RXNEIE              USART_CR1_RXNEIE_Msk                     /*!<RXNE Interrupt Enable                  */
+#define USART_CR1_TCIE_Pos            (6U)                                     
+#define USART_CR1_TCIE_Msk            (0x1UL << USART_CR1_TCIE_Pos)             /*!< 0x00000040 */
+#define USART_CR1_TCIE                USART_CR1_TCIE_Msk                       /*!<Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE_Pos           (7U)                                     
+#define USART_CR1_TXEIE_Msk           (0x1UL << USART_CR1_TXEIE_Pos)            /*!< 0x00000080 */
+#define USART_CR1_TXEIE               USART_CR1_TXEIE_Msk                      /*!<TXE Interrupt Enable                   */
+#define USART_CR1_PEIE_Pos            (8U)                                     
+#define USART_CR1_PEIE_Msk            (0x1UL << USART_CR1_PEIE_Pos)             /*!< 0x00000100 */
+#define USART_CR1_PEIE                USART_CR1_PEIE_Msk                       /*!<PE Interrupt Enable                    */
+#define USART_CR1_PS_Pos              (9U)                                     
+#define USART_CR1_PS_Msk              (0x1UL << USART_CR1_PS_Pos)               /*!< 0x00000200 */
+#define USART_CR1_PS                  USART_CR1_PS_Msk                         /*!<Parity Selection                       */
+#define USART_CR1_PCE_Pos             (10U)                                    
+#define USART_CR1_PCE_Msk             (0x1UL << USART_CR1_PCE_Pos)              /*!< 0x00000400 */
+#define USART_CR1_PCE                 USART_CR1_PCE_Msk                        /*!<Parity Control Enable                  */
+#define USART_CR1_WAKE_Pos            (11U)                                    
+#define USART_CR1_WAKE_Msk            (0x1UL << USART_CR1_WAKE_Pos)             /*!< 0x00000800 */
+#define USART_CR1_WAKE                USART_CR1_WAKE_Msk                       /*!<Wakeup method                          */
+#define USART_CR1_M_Pos               (12U)                                    
+#define USART_CR1_M_Msk               (0x1UL << USART_CR1_M_Pos)                /*!< 0x00001000 */
+#define USART_CR1_M                   USART_CR1_M_Msk                          /*!<Word length                            */
+#define USART_CR1_UE_Pos              (13U)                                    
+#define USART_CR1_UE_Msk              (0x1UL << USART_CR1_UE_Pos)               /*!< 0x00002000 */
+#define USART_CR1_UE                  USART_CR1_UE_Msk                         /*!<USART Enable                           */
+#define USART_CR1_OVER8_Pos           (15U)                                    
+#define USART_CR1_OVER8_Msk           (0x1UL << USART_CR1_OVER8_Pos)            /*!< 0x00008000 */
+#define USART_CR1_OVER8               USART_CR1_OVER8_Msk                      /*!<USART Oversampling by 8 enable         */
+
+/******************  Bit definition for USART_CR2 register  *******************/
+#define USART_CR2_ADD_Pos             (0U)                                     
+#define USART_CR2_ADD_Msk             (0xFUL << USART_CR2_ADD_Pos)              /*!< 0x0000000F */
+#define USART_CR2_ADD                 USART_CR2_ADD_Msk                        /*!<Address of the USART node            */
+#define USART_CR2_LBDL_Pos            (5U)                                     
+#define USART_CR2_LBDL_Msk            (0x1UL << USART_CR2_LBDL_Pos)             /*!< 0x00000020 */
+#define USART_CR2_LBDL                USART_CR2_LBDL_Msk                       /*!<LIN Break Detection Length           */
+#define USART_CR2_LBDIE_Pos           (6U)                                     
+#define USART_CR2_LBDIE_Msk           (0x1UL << USART_CR2_LBDIE_Pos)            /*!< 0x00000040 */
+#define USART_CR2_LBDIE               USART_CR2_LBDIE_Msk                      /*!<LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL_Pos            (8U)                                     
+#define USART_CR2_LBCL_Msk            (0x1UL << USART_CR2_LBCL_Pos)             /*!< 0x00000100 */
+#define USART_CR2_LBCL                USART_CR2_LBCL_Msk                       /*!<Last Bit Clock pulse                 */
+#define USART_CR2_CPHA_Pos            (9U)                                     
+#define USART_CR2_CPHA_Msk            (0x1UL << USART_CR2_CPHA_Pos)             /*!< 0x00000200 */
+#define USART_CR2_CPHA                USART_CR2_CPHA_Msk                       /*!<Clock Phase                          */
+#define USART_CR2_CPOL_Pos            (10U)                                    
+#define USART_CR2_CPOL_Msk            (0x1UL << USART_CR2_CPOL_Pos)             /*!< 0x00000400 */
+#define USART_CR2_CPOL                USART_CR2_CPOL_Msk                       /*!<Clock Polarity                       */
+#define USART_CR2_CLKEN_Pos           (11U)                                    
+#define USART_CR2_CLKEN_Msk           (0x1UL << USART_CR2_CLKEN_Pos)            /*!< 0x00000800 */
+#define USART_CR2_CLKEN               USART_CR2_CLKEN_Msk                      /*!<Clock Enable                         */
+
+#define USART_CR2_STOP_Pos            (12U)                                    
+#define USART_CR2_STOP_Msk            (0x3UL << USART_CR2_STOP_Pos)             /*!< 0x00003000 */
+#define USART_CR2_STOP                USART_CR2_STOP_Msk                       /*!<STOP[1:0] bits (STOP bits) */
+#define USART_CR2_STOP_0              (0x1UL << USART_CR2_STOP_Pos)             /*!< 0x1000 */
+#define USART_CR2_STOP_1              (0x2UL << USART_CR2_STOP_Pos)             /*!< 0x2000 */
+
+#define USART_CR2_LINEN_Pos           (14U)                                    
+#define USART_CR2_LINEN_Msk           (0x1UL << USART_CR2_LINEN_Pos)            /*!< 0x00004000 */
+#define USART_CR2_LINEN               USART_CR2_LINEN_Msk                      /*!<LIN mode enable */
+
+/******************  Bit definition for USART_CR3 register  *******************/
+#define USART_CR3_EIE_Pos             (0U)                                     
+#define USART_CR3_EIE_Msk             (0x1UL << USART_CR3_EIE_Pos)              /*!< 0x00000001 */
+#define USART_CR3_EIE                 USART_CR3_EIE_Msk                        /*!<Error Interrupt Enable      */
+#define USART_CR3_IREN_Pos            (1U)                                     
+#define USART_CR3_IREN_Msk            (0x1UL << USART_CR3_IREN_Pos)             /*!< 0x00000002 */
+#define USART_CR3_IREN                USART_CR3_IREN_Msk                       /*!<IrDA mode Enable            */
+#define USART_CR3_IRLP_Pos            (2U)                                     
+#define USART_CR3_IRLP_Msk            (0x1UL << USART_CR3_IRLP_Pos)             /*!< 0x00000004 */
+#define USART_CR3_IRLP                USART_CR3_IRLP_Msk                       /*!<IrDA Low-Power              */
+#define USART_CR3_HDSEL_Pos           (3U)                                     
+#define USART_CR3_HDSEL_Msk           (0x1UL << USART_CR3_HDSEL_Pos)            /*!< 0x00000008 */
+#define USART_CR3_HDSEL               USART_CR3_HDSEL_Msk                      /*!<Half-Duplex Selection       */
+#define USART_CR3_NACK_Pos            (4U)                                     
+#define USART_CR3_NACK_Msk            (0x1UL << USART_CR3_NACK_Pos)             /*!< 0x00000010 */
+#define USART_CR3_NACK                USART_CR3_NACK_Msk                       /*!<Smartcard NACK enable       */
+#define USART_CR3_SCEN_Pos            (5U)                                     
+#define USART_CR3_SCEN_Msk            (0x1UL << USART_CR3_SCEN_Pos)             /*!< 0x00000020 */
+#define USART_CR3_SCEN                USART_CR3_SCEN_Msk                       /*!<Smartcard mode enable       */
+#define USART_CR3_DMAR_Pos            (6U)                                     
+#define USART_CR3_DMAR_Msk            (0x1UL << USART_CR3_DMAR_Pos)             /*!< 0x00000040 */
+#define USART_CR3_DMAR                USART_CR3_DMAR_Msk                       /*!<DMA Enable Receiver         */
+#define USART_CR3_DMAT_Pos            (7U)                                     
+#define USART_CR3_DMAT_Msk            (0x1UL << USART_CR3_DMAT_Pos)             /*!< 0x00000080 */
+#define USART_CR3_DMAT                USART_CR3_DMAT_Msk                       /*!<DMA Enable Transmitter      */
+#define USART_CR3_RTSE_Pos            (8U)                                     
+#define USART_CR3_RTSE_Msk            (0x1UL << USART_CR3_RTSE_Pos)             /*!< 0x00000100 */
+#define USART_CR3_RTSE                USART_CR3_RTSE_Msk                       /*!<RTS Enable                  */
+#define USART_CR3_CTSE_Pos            (9U)                                     
+#define USART_CR3_CTSE_Msk            (0x1UL << USART_CR3_CTSE_Pos)             /*!< 0x00000200 */
+#define USART_CR3_CTSE                USART_CR3_CTSE_Msk                       /*!<CTS Enable                  */
+#define USART_CR3_CTSIE_Pos           (10U)                                    
+#define USART_CR3_CTSIE_Msk           (0x1UL << USART_CR3_CTSIE_Pos)            /*!< 0x00000400 */
+#define USART_CR3_CTSIE               USART_CR3_CTSIE_Msk                      /*!<CTS Interrupt Enable        */
+#define USART_CR3_ONEBIT_Pos          (11U)                                    
+#define USART_CR3_ONEBIT_Msk          (0x1UL << USART_CR3_ONEBIT_Pos)           /*!< 0x00000800 */
+#define USART_CR3_ONEBIT              USART_CR3_ONEBIT_Msk                     /*!<USART One bit method enable */
+
+/******************  Bit definition for USART_GTPR register  ******************/
+#define USART_GTPR_PSC_Pos            (0U)                                     
+#define USART_GTPR_PSC_Msk            (0xFFUL << USART_GTPR_PSC_Pos)            /*!< 0x000000FF */
+#define USART_GTPR_PSC                USART_GTPR_PSC_Msk                       /*!<PSC[7:0] bits (Prescaler value) */
+#define USART_GTPR_PSC_0              (0x01UL << USART_GTPR_PSC_Pos)            /*!< 0x0001 */
+#define USART_GTPR_PSC_1              (0x02UL << USART_GTPR_PSC_Pos)            /*!< 0x0002 */
+#define USART_GTPR_PSC_2              (0x04UL << USART_GTPR_PSC_Pos)            /*!< 0x0004 */
+#define USART_GTPR_PSC_3              (0x08UL << USART_GTPR_PSC_Pos)            /*!< 0x0008 */
+#define USART_GTPR_PSC_4              (0x10UL << USART_GTPR_PSC_Pos)            /*!< 0x0010 */
+#define USART_GTPR_PSC_5              (0x20UL << USART_GTPR_PSC_Pos)            /*!< 0x0020 */
+#define USART_GTPR_PSC_6              (0x40UL << USART_GTPR_PSC_Pos)            /*!< 0x0040 */
+#define USART_GTPR_PSC_7              (0x80UL << USART_GTPR_PSC_Pos)            /*!< 0x0080 */
+
+#define USART_GTPR_GT_Pos             (8U)                                     
+#define USART_GTPR_GT_Msk             (0xFFUL << USART_GTPR_GT_Pos)             /*!< 0x0000FF00 */
+#define USART_GTPR_GT                 USART_GTPR_GT_Msk                        /*!<Guard time value */
+
+/******************************************************************************/
+/*                                                                            */
+/*                            Window WATCHDOG                                 */
+/*                                                                            */
+/******************************************************************************/
+/*******************  Bit definition for WWDG_CR register  ********************/
+#define WWDG_CR_T_Pos           (0U)                                           
+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                       /*!< 0x0000007F */
+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x01 */
+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x02 */
+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x04 */
+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x08 */
+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x10 */
+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x20 */
+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x40 */
+/* Legacy defines */
+#define  WWDG_CR_T0                          WWDG_CR_T_0
+#define  WWDG_CR_T1                          WWDG_CR_T_1
+#define  WWDG_CR_T2                          WWDG_CR_T_2
+#define  WWDG_CR_T3                          WWDG_CR_T_3
+#define  WWDG_CR_T4                          WWDG_CR_T_4
+#define  WWDG_CR_T5                          WWDG_CR_T_5
+#define  WWDG_CR_T6                          WWDG_CR_T_6
+
+#define WWDG_CR_WDGA_Pos        (7U)                                           
+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                     /*!< 0x00000080 */
+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */
+
+/*******************  Bit definition for WWDG_CFR register  *******************/
+#define WWDG_CFR_W_Pos          (0U)                                           
+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                      /*!< 0x0000007F */
+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */
+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x0001 */
+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x0002 */
+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x0004 */
+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x0008 */
+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x0010 */
+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x0020 */
+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x0040 */
+/* Legacy defines */
+#define  WWDG_CFR_W0                         WWDG_CFR_W_0
+#define  WWDG_CFR_W1                         WWDG_CFR_W_1
+#define  WWDG_CFR_W2                         WWDG_CFR_W_2
+#define  WWDG_CFR_W3                         WWDG_CFR_W_3
+#define  WWDG_CFR_W4                         WWDG_CFR_W_4
+#define  WWDG_CFR_W5                         WWDG_CFR_W_5
+#define  WWDG_CFR_W6                         WWDG_CFR_W_6
+
+#define WWDG_CFR_WDGTB_Pos      (7U)                                           
+#define WWDG_CFR_WDGTB_Msk      (0x3UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000180 */
+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0080 */
+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x0100 */
+/* Legacy defines */
+#define  WWDG_CFR_WDGTB0                     WWDG_CFR_WDGTB_0
+#define  WWDG_CFR_WDGTB1                     WWDG_CFR_WDGTB_1
+
+#define WWDG_CFR_EWI_Pos        (9U)                                           
+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                     /*!< 0x00000200 */
+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_SR register  ********************/
+#define WWDG_SR_EWIF_Pos        (0U)                                           
+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                     /*!< 0x00000001 */
+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */
+
+
+/******************************************************************************/
+/*                                                                            */
+/*                                DBG                                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for DBGMCU_IDCODE register  *************/
+#define DBGMCU_IDCODE_DEV_ID_Pos                     (0U)                      
+#define DBGMCU_IDCODE_DEV_ID_Msk                     (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
+#define DBGMCU_IDCODE_DEV_ID                         DBGMCU_IDCODE_DEV_ID_Msk  
+#define DBGMCU_IDCODE_REV_ID_Pos                     (16U)                     
+#define DBGMCU_IDCODE_REV_ID_Msk                     (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
+#define DBGMCU_IDCODE_REV_ID                         DBGMCU_IDCODE_REV_ID_Msk  
+
+/********************  Bit definition for DBGMCU_CR register  *****************/
+#define DBGMCU_CR_DBG_SLEEP_Pos                      (0U)                      
+#define DBGMCU_CR_DBG_SLEEP_Msk                      (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
+#define DBGMCU_CR_DBG_SLEEP                          DBGMCU_CR_DBG_SLEEP_Msk   
+#define DBGMCU_CR_DBG_STOP_Pos                       (1U)                      
+#define DBGMCU_CR_DBG_STOP_Msk                       (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_CR_DBG_STOP                           DBGMCU_CR_DBG_STOP_Msk    
+#define DBGMCU_CR_DBG_STANDBY_Pos                    (2U)                      
+#define DBGMCU_CR_DBG_STANDBY_Msk                    (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
+#define DBGMCU_CR_DBG_STANDBY                        DBGMCU_CR_DBG_STANDBY_Msk 
+#define DBGMCU_CR_TRACE_IOEN_Pos                     (5U)                      
+#define DBGMCU_CR_TRACE_IOEN_Msk                     (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
+#define DBGMCU_CR_TRACE_IOEN                         DBGMCU_CR_TRACE_IOEN_Msk  
+
+#define DBGMCU_CR_TRACE_MODE_Pos                     (6U)                      
+#define DBGMCU_CR_TRACE_MODE_Msk                     (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
+#define DBGMCU_CR_TRACE_MODE                         DBGMCU_CR_TRACE_MODE_Msk  
+#define DBGMCU_CR_TRACE_MODE_0                       (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
+#define DBGMCU_CR_TRACE_MODE_1                       (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
+
+/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos             (0U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP                 DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos             (1U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP                 DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos             (2U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP                 DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos             (3U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP                 DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos             (4U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP                 DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos             (5U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP                 DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos            (6U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP                DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos            (7U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP                DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos            (8U)                      
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk            (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP                DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos              (10U)                     
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk              (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP                  DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos             (11U)                     
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP                 DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos             (12U)                     
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP                 DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos    (21U)                     
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk 
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos    (22U)                     
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk 
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos    (23U)                     
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk    (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT        DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk 
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos             (25U)                     
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP                 DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk 
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos             (26U)                     
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk             (0x1UL << DBGMCU_APB1_FZ_DBG_CAN2_STOP_Pos) /*!< 0x04000000 */
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP                 DBGMCU_APB1_FZ_DBG_CAN2_STOP_Msk 
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */
+#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP
+
+/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos             (0U)                      
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP                 DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos             (1U)                      
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP                 DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos             (16U)                     
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk             (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP                 DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos            (17U)                     
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP                DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk 
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos            (18U)                     
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk            (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP                DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk 
+
+/******************************************************************************/
+/*                                                                            */
+/*                Ethernet MAC Registers bits definitions                     */
+/*                                                                            */
+/******************************************************************************/
+/* Bit definition for Ethernet MAC Control Register register */
+#define ETH_MACCR_WD_Pos                              (23U)                    
+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */
+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */
+#define ETH_MACCR_JD_Pos                              (22U)                    
+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00400000 */
+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */
+#define ETH_MACCR_IFG_Pos                             (17U)                    
+#define ETH_MACCR_IFG_Msk                             (0x7UL << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */
+#define ETH_MACCR_IFG                                 ETH_MACCR_IFG_Msk        /* Inter-frame gap */
+#define ETH_MACCR_IFG_96Bit                           0x00000000U              /* Minimum IFG between frames during transmission is 96Bit */
+#define ETH_MACCR_IFG_88Bit                           0x00020000U              /* Minimum IFG between frames during transmission is 88Bit */
+#define ETH_MACCR_IFG_80Bit                           0x00040000U              /* Minimum IFG between frames during transmission is 80Bit */
+#define ETH_MACCR_IFG_72Bit                           0x00060000U              /* Minimum IFG between frames during transmission is 72Bit */
+#define ETH_MACCR_IFG_64Bit                           0x00080000U              /* Minimum IFG between frames during transmission is 64Bit */
+#define ETH_MACCR_IFG_56Bit                           0x000A0000U              /* Minimum IFG between frames during transmission is 56Bit */
+#define ETH_MACCR_IFG_48Bit                           0x000C0000U              /* Minimum IFG between frames during transmission is 48Bit */
+#define ETH_MACCR_IFG_40Bit                           0x000E0000U              /* Minimum IFG between frames during transmission is 40Bit */
+#define ETH_MACCR_CSD_Pos                             (16U)                    
+#define ETH_MACCR_CSD_Msk                             (0x1UL << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */
+#define ETH_MACCR_CSD                                 ETH_MACCR_CSD_Msk        /* Carrier sense disable (during transmission) */
+#define ETH_MACCR_FES_Pos                             (14U)                    
+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */
+#define ETH_MACCR_ROD_Pos                             (13U)                    
+#define ETH_MACCR_ROD_Msk                             (0x1UL << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */
+#define ETH_MACCR_ROD                                 ETH_MACCR_ROD_Msk        /* Receive own disable */
+#define ETH_MACCR_LM_Pos                              (12U)                    
+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */
+#define ETH_MACCR_DM_Pos                              (11U)                    
+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00000800 */
+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */
+#define ETH_MACCR_IPCO_Pos                            (10U)                    
+#define ETH_MACCR_IPCO_Msk                            (0x1UL << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */
+#define ETH_MACCR_IPCO                                ETH_MACCR_IPCO_Msk       /* IP Checksum offload */
+#define ETH_MACCR_RD_Pos                              (9U)                     
+#define ETH_MACCR_RD_Msk                              (0x1UL << ETH_MACCR_RD_Pos) /*!< 0x00000200 */
+#define ETH_MACCR_RD                                  ETH_MACCR_RD_Msk         /* Retry disable */
+#define ETH_MACCR_APCS_Pos                            (7U)                     
+#define ETH_MACCR_APCS_Msk                            (0x1UL << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */
+#define ETH_MACCR_APCS                                ETH_MACCR_APCS_Msk       /* Automatic Pad/CRC stripping */
+#define ETH_MACCR_BL_Pos                              (5U)                     
+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit: random integer number (r) of slot time delays before rescheduling
+                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
+#define ETH_MACCR_BL_10                               0x00000000U              /* k = min (n, 10) */
+#define ETH_MACCR_BL_8                                0x00000020U              /* k = min (n, 8) */
+#define ETH_MACCR_BL_4                                0x00000040U              /* k = min (n, 4) */
+#define ETH_MACCR_BL_1                                0x00000060U              /* k = min (n, 1) */ 
+#define ETH_MACCR_DC_Pos                              (4U)                     
+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */
+#define ETH_MACCR_TE_Pos                              (3U)                     
+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000008 */
+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */
+#define ETH_MACCR_RE_Pos                              (2U)                     
+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000004 */
+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */
+
+/* Bit definition for Ethernet MAC Frame Filter Register */
+#define ETH_MACFFR_RA_Pos                             (31U)                    
+#define ETH_MACFFR_RA_Msk                             (0x1UL << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */
+#define ETH_MACFFR_RA                                 ETH_MACFFR_RA_Msk        /* Receive all */
+#define ETH_MACFFR_HPF_Pos                            (10U)                    
+#define ETH_MACFFR_HPF_Msk                            (0x1UL << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */
+#define ETH_MACFFR_HPF                                ETH_MACFFR_HPF_Msk       /* Hash or perfect filter */
+#define ETH_MACFFR_SAF_Pos                            (9U)                     
+#define ETH_MACFFR_SAF_Msk                            (0x1UL << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */
+#define ETH_MACFFR_SAF                                ETH_MACFFR_SAF_Msk       /* Source address filter enable */
+#define ETH_MACFFR_SAIF_Pos                           (8U)                     
+#define ETH_MACFFR_SAIF_Msk                           (0x1UL << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */
+#define ETH_MACFFR_SAIF                               ETH_MACFFR_SAIF_Msk      /* SA inverse filtering */ 
+#define ETH_MACFFR_PCF_Pos                            (6U)                     
+#define ETH_MACFFR_PCF_Msk                            (0x3UL << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF                                ETH_MACFFR_PCF_Msk       /* Pass control frames: 3 cases */
+#define ETH_MACFFR_PCF_BlockAll_Pos                   (6U)                     
+#define ETH_MACFFR_PCF_BlockAll_Msk                   (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */
+#define ETH_MACFFR_PCF_BlockAll                       ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */
+#define ETH_MACFFR_PCF_ForwardAll_Pos                 (7U)                     
+#define ETH_MACFFR_PCF_ForwardAll_Msk                 (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */
+#define ETH_MACFFR_PCF_ForwardAll                     ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos    (6U)                     
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk    (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */
+#define ETH_MACFFR_PCF_ForwardPassedAddrFilter        ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */ 
+#define ETH_MACFFR_BFD_Pos                            (5U)                     
+#define ETH_MACFFR_BFD_Msk                            (0x1UL << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */
+#define ETH_MACFFR_BFD                                ETH_MACFFR_BFD_Msk       /* Broadcast frame disable */ 
+#define ETH_MACFFR_PAM_Pos                            (4U)                     
+#define ETH_MACFFR_PAM_Msk                            (0x1UL << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */
+#define ETH_MACFFR_PAM                                ETH_MACFFR_PAM_Msk       /* Pass all mutlicast */
+#define ETH_MACFFR_DAIF_Pos                           (3U)                     
+#define ETH_MACFFR_DAIF_Msk                           (0x1UL << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */
+#define ETH_MACFFR_DAIF                               ETH_MACFFR_DAIF_Msk      /* DA Inverse filtering */
+#define ETH_MACFFR_HM_Pos                             (2U)                     
+#define ETH_MACFFR_HM_Msk                             (0x1UL << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */
+#define ETH_MACFFR_HM                                 ETH_MACFFR_HM_Msk        /* Hash multicast */ 
+#define ETH_MACFFR_HU_Pos                             (1U)                     
+#define ETH_MACFFR_HU_Msk                             (0x1UL << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */
+#define ETH_MACFFR_HU                                 ETH_MACFFR_HU_Msk        /* Hash unicast */
+#define ETH_MACFFR_PM_Pos                             (0U)                     
+#define ETH_MACFFR_PM_Msk                             (0x1UL << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */
+#define ETH_MACFFR_PM                                 ETH_MACFFR_PM_Msk        /* Promiscuous mode */
+
+/* Bit definition for Ethernet MAC Hash Table High Register */
+#define ETH_MACHTHR_HTH_Pos                           (0U)                     
+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */
+
+/* Bit definition for Ethernet MAC Hash Table Low Register */
+#define ETH_MACHTLR_HTL_Pos                           (0U)                     
+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */
+
+/* Bit definition for Ethernet MAC MII Address Register */
+#define ETH_MACMIIAR_PA_Pos                           (11U)                    
+#define ETH_MACMIIAR_PA_Msk                           (0x1FUL << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */
+#define ETH_MACMIIAR_PA                               ETH_MACMIIAR_PA_Msk      /* Physical layer address */
+#define ETH_MACMIIAR_MR_Pos                           (6U)                     
+#define ETH_MACMIIAR_MR_Msk                           (0x1FUL << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */
+#define ETH_MACMIIAR_MR                               ETH_MACMIIAR_MR_Msk      /* MII register in the selected PHY */
+#define ETH_MACMIIAR_CR_Pos                           (2U)                     
+#define ETH_MACMIIAR_CR_Msk                           (0x7UL << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */
+#define ETH_MACMIIAR_CR                               ETH_MACMIIAR_CR_Msk      /* CR clock range: 6 cases */
+#define ETH_MACMIIAR_CR_Div42                         0x00000000U              /* HCLK:60-100 MHz; MDC clock= HCLK/42   */
+#define ETH_MACMIIAR_CR_Div62_Pos                     (2U)                     
+#define ETH_MACMIIAR_CR_Div62_Msk                     (0x1UL << ETH_MACMIIAR_CR_Div62_Pos) /*!< 0x00000004 */
+#define ETH_MACMIIAR_CR_Div62                         ETH_MACMIIAR_CR_Div62_Msk /* HCLK:100-150 MHz; MDC clock= HCLK/62  */
+#define ETH_MACMIIAR_CR_Div16_Pos                     (3U)                     
+#define ETH_MACMIIAR_CR_Div16_Msk                     (0x1UL << ETH_MACMIIAR_CR_Div16_Pos) /*!< 0x00000008 */
+#define ETH_MACMIIAR_CR_Div16                         ETH_MACMIIAR_CR_Div16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16    */
+#define ETH_MACMIIAR_CR_Div26_Pos                     (2U)                     
+#define ETH_MACMIIAR_CR_Div26_Msk                     (0x3UL << ETH_MACMIIAR_CR_Div26_Pos) /*!< 0x0000000C */
+#define ETH_MACMIIAR_CR_Div26                         ETH_MACMIIAR_CR_Div26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26    */
+#define ETH_MACMIIAR_CR_Div102_Pos                    (4U)                     
+#define ETH_MACMIIAR_CR_Div102_Msk                    (0x1UL << ETH_MACMIIAR_CR_Div102_Pos) /*!< 0x00000010 */
+#define ETH_MACMIIAR_CR_Div102                        ETH_MACMIIAR_CR_Div102_Msk /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
+#define ETH_MACMIIAR_MW_Pos                           (1U)                     
+#define ETH_MACMIIAR_MW_Msk                           (0x1UL << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */
+#define ETH_MACMIIAR_MW                               ETH_MACMIIAR_MW_Msk      /* MII write */
+#define ETH_MACMIIAR_MB_Pos                           (0U)                     
+#define ETH_MACMIIAR_MB_Msk                           (0x1UL << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */
+#define ETH_MACMIIAR_MB                               ETH_MACMIIAR_MB_Msk      /* MII busy  */
+
+/* Bit definition for Ethernet MAC MII Data Register */
+#define ETH_MACMIIDR_MD_Pos                           (0U)                     
+#define ETH_MACMIIDR_MD_Msk                           (0xFFFFUL << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */
+#define ETH_MACMIIDR_MD                               ETH_MACMIIDR_MD_Msk      /* MII data: read/write data from/to PHY */
+
+/* Bit definition for Ethernet MAC Flow Control Register */
+#define ETH_MACFCR_PT_Pos                             (16U)                    
+#define ETH_MACFCR_PT_Msk                             (0xFFFFUL << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */
+#define ETH_MACFCR_PT                                 ETH_MACFCR_PT_Msk        /* Pause time */
+#define ETH_MACFCR_ZQPD_Pos                           (7U)                     
+#define ETH_MACFCR_ZQPD_Msk                           (0x1UL << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */
+#define ETH_MACFCR_ZQPD                               ETH_MACFCR_ZQPD_Msk      /* Zero-quanta pause disable */
+#define ETH_MACFCR_PLT_Pos                            (4U)                     
+#define ETH_MACFCR_PLT_Msk                            (0x3UL << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT                                ETH_MACFCR_PLT_Msk       /* Pause low threshold: 4 cases */
+#define ETH_MACFCR_PLT_Minus4                         0x00000000U              /* Pause time minus 4 slot times   */
+#define ETH_MACFCR_PLT_Minus28_Pos                    (4U)                     
+#define ETH_MACFCR_PLT_Minus28_Msk                    (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */
+#define ETH_MACFCR_PLT_Minus28                        ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times  */
+#define ETH_MACFCR_PLT_Minus144_Pos                   (5U)                     
+#define ETH_MACFCR_PLT_Minus144_Msk                   (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */
+#define ETH_MACFCR_PLT_Minus144                       ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */
+#define ETH_MACFCR_PLT_Minus256_Pos                   (4U)                     
+#define ETH_MACFCR_PLT_Minus256_Msk                   (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */
+#define ETH_MACFCR_PLT_Minus256                       ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */
+#define ETH_MACFCR_UPFD_Pos                           (3U)                     
+#define ETH_MACFCR_UPFD_Msk                           (0x1UL << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */
+#define ETH_MACFCR_UPFD                               ETH_MACFCR_UPFD_Msk      /* Unicast pause frame detect */
+#define ETH_MACFCR_RFCE_Pos                           (2U)                     
+#define ETH_MACFCR_RFCE_Msk                           (0x1UL << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */
+#define ETH_MACFCR_RFCE                               ETH_MACFCR_RFCE_Msk      /* Receive flow control enable */
+#define ETH_MACFCR_TFCE_Pos                           (1U)                     
+#define ETH_MACFCR_TFCE_Msk                           (0x1UL << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */
+#define ETH_MACFCR_TFCE                               ETH_MACFCR_TFCE_Msk      /* Transmit flow control enable */
+#define ETH_MACFCR_FCBBPA_Pos                         (0U)                     
+#define ETH_MACFCR_FCBBPA_Msk                         (0x1UL << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */
+#define ETH_MACFCR_FCBBPA                             ETH_MACFCR_FCBBPA_Msk    /* Flow control busy/backpressure activate */
+
+/* Bit definition for Ethernet MAC VLAN Tag Register */
+#define ETH_MACVLANTR_VLANTC_Pos                      (16U)                    
+#define ETH_MACVLANTR_VLANTC_Msk                      (0x1UL << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */
+#define ETH_MACVLANTR_VLANTC                          ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */
+#define ETH_MACVLANTR_VLANTI_Pos                      (0U)                     
+#define ETH_MACVLANTR_VLANTI_Msk                      (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */
+#define ETH_MACVLANTR_VLANTI                          ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */
+
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
+#define ETH_MACRWUFFR_D_Pos                           (0U)                     
+#define ETH_MACRWUFFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACRWUFFR_D                               ETH_MACRWUFFR_D_Msk      /* Wake-up frame filter register data */
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
+   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
+   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
+   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
+   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
+   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
+                              RSVD - Filter1 Command - RSVD - Filter0 Command
+   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
+   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
+   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
+
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
+#define ETH_MACPMTCSR_WFFRPR_Pos                      (31U)                    
+#define ETH_MACPMTCSR_WFFRPR_Msk                      (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */
+#define ETH_MACPMTCSR_WFFRPR                          ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_MACPMTCSR_GU_Pos                          (9U)                     
+#define ETH_MACPMTCSR_GU_Msk                          (0x1UL << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */
+#define ETH_MACPMTCSR_GU                              ETH_MACPMTCSR_GU_Msk     /* Global Unicast                              */
+#define ETH_MACPMTCSR_WFR_Pos                         (6U)                     
+#define ETH_MACPMTCSR_WFR_Msk                         (0x1UL << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */
+#define ETH_MACPMTCSR_WFR                             ETH_MACPMTCSR_WFR_Msk    /* Wake-Up Frame Received                      */
+#define ETH_MACPMTCSR_MPR_Pos                         (5U)                     
+#define ETH_MACPMTCSR_MPR_Msk                         (0x1UL << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */
+#define ETH_MACPMTCSR_MPR                             ETH_MACPMTCSR_MPR_Msk    /* Magic Packet Received                       */
+#define ETH_MACPMTCSR_WFE_Pos                         (2U)                     
+#define ETH_MACPMTCSR_WFE_Msk                         (0x1UL << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */
+#define ETH_MACPMTCSR_WFE                             ETH_MACPMTCSR_WFE_Msk    /* Wake-Up Frame Enable                        */
+#define ETH_MACPMTCSR_MPE_Pos                         (1U)                     
+#define ETH_MACPMTCSR_MPE_Msk                         (0x1UL << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */
+#define ETH_MACPMTCSR_MPE                             ETH_MACPMTCSR_MPE_Msk    /* Magic Packet Enable                         */
+#define ETH_MACPMTCSR_PD_Pos                          (0U)                     
+#define ETH_MACPMTCSR_PD_Msk                          (0x1UL << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */
+#define ETH_MACPMTCSR_PD                              ETH_MACPMTCSR_PD_Msk     /* Power Down                                  */
+
+/* Bit definition for Ethernet MAC debug Register */
+#define ETH_MACDBGR_TFF_Pos                           (25U)                    
+#define ETH_MACDBGR_TFF_Msk                           (0x1UL << ETH_MACDBGR_TFF_Pos) /*!< 0x02000000 */
+#define ETH_MACDBGR_TFF                               ETH_MACDBGR_TFF_Msk      /* Tx FIFO full                                                            */
+#define ETH_MACDBGR_TFNE_Pos                          (24U)                    
+#define ETH_MACDBGR_TFNE_Msk                          (0x1UL << ETH_MACDBGR_TFNE_Pos) /*!< 0x01000000 */
+#define ETH_MACDBGR_TFNE                              ETH_MACDBGR_TFNE_Msk     /* Tx FIFO not empty                                                       */
+#define ETH_MACDBGR_TFWA_Pos                          (22U)                    
+#define ETH_MACDBGR_TFWA_Msk                          (0x1UL << ETH_MACDBGR_TFWA_Pos) /*!< 0x00400000 */
+#define ETH_MACDBGR_TFWA                              ETH_MACDBGR_TFWA_Msk     /* Tx FIFO write active                                                    */
+#define ETH_MACDBGR_TFRS_Pos                          (20U)                    
+#define ETH_MACDBGR_TFRS_Msk                          (0x3UL << ETH_MACDBGR_TFRS_Pos) /*!< 0x00300000 */
+#define ETH_MACDBGR_TFRS                              ETH_MACDBGR_TFRS_Msk     /* Tx FIFO read status mask                                                */
+#define ETH_MACDBGR_TFRS_WRITING_Pos                  (20U)                    
+#define ETH_MACDBGR_TFRS_WRITING_Msk                  (0x3UL << ETH_MACDBGR_TFRS_WRITING_Pos) /*!< 0x00300000 */
+#define ETH_MACDBGR_TFRS_WRITING                      ETH_MACDBGR_TFRS_WRITING_Msk /* Writing the received TxStatus or flushing the TxFIFO                    */
+#define ETH_MACDBGR_TFRS_WAITING_Pos                  (21U)                    
+#define ETH_MACDBGR_TFRS_WAITING_Msk                  (0x1UL << ETH_MACDBGR_TFRS_WAITING_Pos) /*!< 0x00200000 */
+#define ETH_MACDBGR_TFRS_WAITING                      ETH_MACDBGR_TFRS_WAITING_Msk /* Waiting for TxStatus from MAC transmitter                               */
+#define ETH_MACDBGR_TFRS_READ_Pos                     (20U)                    
+#define ETH_MACDBGR_TFRS_READ_Msk                     (0x1UL << ETH_MACDBGR_TFRS_READ_Pos) /*!< 0x00100000 */
+#define ETH_MACDBGR_TFRS_READ                         ETH_MACDBGR_TFRS_READ_Msk /* Read state (transferring data to the MAC transmitter)                   */
+#define ETH_MACDBGR_TFRS_IDLE                         0x00000000U              /* Idle state                                                              */
+#define ETH_MACDBGR_MTP_Pos                           (19U)                    
+#define ETH_MACDBGR_MTP_Msk                           (0x1UL << ETH_MACDBGR_MTP_Pos) /*!< 0x00080000 */
+#define ETH_MACDBGR_MTP                               ETH_MACDBGR_MTP_Msk      /* MAC transmitter in pause                                                */
+#define ETH_MACDBGR_MTFCS_Pos                         (17U)                    
+#define ETH_MACDBGR_MTFCS_Msk                         (0x3UL << ETH_MACDBGR_MTFCS_Pos) /*!< 0x00060000 */
+#define ETH_MACDBGR_MTFCS                             ETH_MACDBGR_MTFCS_Msk    /* MAC transmit frame controller status mask                               */
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Pos            (17U)                    
+#define ETH_MACDBGR_MTFCS_TRANSFERRING_Msk            (0x3UL << ETH_MACDBGR_MTFCS_TRANSFERRING_Pos) /*!< 0x00060000 */
+#define ETH_MACDBGR_MTFCS_TRANSFERRING                ETH_MACDBGR_MTFCS_TRANSFERRING_Msk /* Transferring input frame for transmission                               */
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos           (18U)                    
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk           (0x1UL << ETH_MACDBGR_MTFCS_GENERATINGPCF_Pos) /*!< 0x00040000 */
+#define ETH_MACDBGR_MTFCS_GENERATINGPCF               ETH_MACDBGR_MTFCS_GENERATINGPCF_Msk /* Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MACDBGR_MTFCS_WAITING_Pos                 (17U)                    
+#define ETH_MACDBGR_MTFCS_WAITING_Msk                 (0x1UL << ETH_MACDBGR_MTFCS_WAITING_Pos) /*!< 0x00020000 */
+#define ETH_MACDBGR_MTFCS_WAITING                     ETH_MACDBGR_MTFCS_WAITING_Msk /* Waiting for Status of previous frame or IFG/backoff period to be over   */
+#define ETH_MACDBGR_MTFCS_IDLE                        0x00000000U              /* Idle                                                                    */
+#define ETH_MACDBGR_MMTEA_Pos                         (16U)                    
+#define ETH_MACDBGR_MMTEA_Msk                         (0x1UL << ETH_MACDBGR_MMTEA_Pos) /*!< 0x00010000 */
+#define ETH_MACDBGR_MMTEA                             ETH_MACDBGR_MMTEA_Msk    /* MAC MII transmit engine active                                          */
+#define ETH_MACDBGR_RFFL_Pos                          (8U)                     
+#define ETH_MACDBGR_RFFL_Msk                          (0x3UL << ETH_MACDBGR_RFFL_Pos) /*!< 0x00000300 */
+#define ETH_MACDBGR_RFFL                              ETH_MACDBGR_RFFL_Msk     /* Rx FIFO fill level mask                                                 */
+#define ETH_MACDBGR_RFFL_FULL_Pos                     (8U)                     
+#define ETH_MACDBGR_RFFL_FULL_Msk                     (0x3UL << ETH_MACDBGR_RFFL_FULL_Pos) /*!< 0x00000300 */
+#define ETH_MACDBGR_RFFL_FULL                         ETH_MACDBGR_RFFL_FULL_Msk /* RxFIFO full                                                             */
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Pos                 (9U)                     
+#define ETH_MACDBGR_RFFL_ABOVEFCT_Msk                 (0x1UL << ETH_MACDBGR_RFFL_ABOVEFCT_Pos) /*!< 0x00000200 */
+#define ETH_MACDBGR_RFFL_ABOVEFCT                     ETH_MACDBGR_RFFL_ABOVEFCT_Msk /* RxFIFO fill-level above flow-control activate threshold                 */
+#define ETH_MACDBGR_RFFL_BELOWFCT_Pos                 (8U)                     
+#define ETH_MACDBGR_RFFL_BELOWFCT_Msk                 (0x1UL << ETH_MACDBGR_RFFL_BELOWFCT_Pos) /*!< 0x00000100 */
+#define ETH_MACDBGR_RFFL_BELOWFCT                     ETH_MACDBGR_RFFL_BELOWFCT_Msk /* RxFIFO fill-level below flow-control de-activate threshold              */
+#define ETH_MACDBGR_RFFL_EMPTY                        0x00000000U              /* RxFIFO empty                                                            */
+#define ETH_MACDBGR_RFRCS_Pos                         (5U)                     
+#define ETH_MACDBGR_RFRCS_Msk                         (0x3UL << ETH_MACDBGR_RFRCS_Pos) /*!< 0x00000060 */
+#define ETH_MACDBGR_RFRCS                             ETH_MACDBGR_RFRCS_Msk    /* Rx FIFO read controller status mask                                     */
+#define ETH_MACDBGR_RFRCS_FLUSHING_Pos                (5U)                     
+#define ETH_MACDBGR_RFRCS_FLUSHING_Msk                (0x3UL << ETH_MACDBGR_RFRCS_FLUSHING_Pos) /*!< 0x00000060 */
+#define ETH_MACDBGR_RFRCS_FLUSHING                    ETH_MACDBGR_RFRCS_FLUSHING_Msk /* Flushing the frame data and status                                      */
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Pos           (6U)                     
+#define ETH_MACDBGR_RFRCS_STATUSREADING_Msk           (0x1UL << ETH_MACDBGR_RFRCS_STATUSREADING_Pos) /*!< 0x00000040 */
+#define ETH_MACDBGR_RFRCS_STATUSREADING               ETH_MACDBGR_RFRCS_STATUSREADING_Msk /* Reading frame status (or time-stamp)                                    */
+#define ETH_MACDBGR_RFRCS_DATAREADING_Pos             (5U)                     
+#define ETH_MACDBGR_RFRCS_DATAREADING_Msk             (0x1UL << ETH_MACDBGR_RFRCS_DATAREADING_Pos) /*!< 0x00000020 */
+#define ETH_MACDBGR_RFRCS_DATAREADING                 ETH_MACDBGR_RFRCS_DATAREADING_Msk /* Reading frame data                                                      */
+#define ETH_MACDBGR_RFRCS_IDLE                        0x00000000U              /* IDLE state                                                              */
+#define ETH_MACDBGR_RFWRA_Pos                         (4U)                     
+#define ETH_MACDBGR_RFWRA_Msk                         (0x1UL << ETH_MACDBGR_RFWRA_Pos) /*!< 0x00000010 */
+#define ETH_MACDBGR_RFWRA                             ETH_MACDBGR_RFWRA_Msk    /* Rx FIFO write controller active                                         */
+#define ETH_MACDBGR_MSFRWCS_Pos                       (1U)                     
+#define ETH_MACDBGR_MSFRWCS_Msk                       (0x3UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000006 */
+#define ETH_MACDBGR_MSFRWCS                           ETH_MACDBGR_MSFRWCS_Msk  /* MAC small FIFO read / write controllers status  mask                    */
+#define ETH_MACDBGR_MSFRWCS_1                         (0x2UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000004 */
+#define ETH_MACDBGR_MSFRWCS_0                         (0x1UL << ETH_MACDBGR_MSFRWCS_Pos) /*!< 0x00000002 */
+#define ETH_MACDBGR_MMRPEA_Pos                        (0U)                     
+#define ETH_MACDBGR_MMRPEA_Msk                        (0x1UL << ETH_MACDBGR_MMRPEA_Pos) /*!< 0x00000001 */
+#define ETH_MACDBGR_MMRPEA                            ETH_MACDBGR_MMRPEA_Msk   /* MAC MII receive protocol engine active                                  */
+
+/* Bit definition for Ethernet MAC Status Register */
+#define ETH_MACSR_TSTS_Pos                            (9U)                     
+#define ETH_MACSR_TSTS_Msk                            (0x1UL << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */
+#define ETH_MACSR_TSTS                                ETH_MACSR_TSTS_Msk       /* Time stamp trigger status */
+#define ETH_MACSR_MMCTS_Pos                           (6U)                     
+#define ETH_MACSR_MMCTS_Msk                           (0x1UL << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */
+#define ETH_MACSR_MMCTS                               ETH_MACSR_MMCTS_Msk      /* MMC transmit status       */
+#define ETH_MACSR_MMMCRS_Pos                          (5U)                     
+#define ETH_MACSR_MMMCRS_Msk                          (0x1UL << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */
+#define ETH_MACSR_MMMCRS                              ETH_MACSR_MMMCRS_Msk     /* MMC receive status        */
+#define ETH_MACSR_MMCS_Pos                            (4U)                     
+#define ETH_MACSR_MMCS_Msk                            (0x1UL << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */
+#define ETH_MACSR_MMCS                                ETH_MACSR_MMCS_Msk       /* MMC status                */
+#define ETH_MACSR_PMTS_Pos                            (3U)                     
+#define ETH_MACSR_PMTS_Msk                            (0x1UL << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */
+#define ETH_MACSR_PMTS                                ETH_MACSR_PMTS_Msk       /* PMT status                */
+
+/* Bit definition for Ethernet MAC Interrupt Mask Register */
+#define ETH_MACIMR_TSTIM_Pos                          (9U)                     
+#define ETH_MACIMR_TSTIM_Msk                          (0x1UL << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */
+#define ETH_MACIMR_TSTIM                              ETH_MACIMR_TSTIM_Msk     /* Time stamp trigger interrupt mask */
+#define ETH_MACIMR_PMTIM_Pos                          (3U)                     
+#define ETH_MACIMR_PMTIM_Msk                          (0x1UL << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */
+#define ETH_MACIMR_PMTIM                              ETH_MACIMR_PMTIM_Msk     /* PMT interrupt mask                */
+
+/* Bit definition for Ethernet MAC Address0 High Register */
+#define ETH_MACA0HR_MACA0H_Pos                        (0U)                     
+#define ETH_MACA0HR_MACA0H_Msk                        (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA0HR_MACA0H                            ETH_MACA0HR_MACA0H_Msk   /* MAC address0 high */
+
+/* Bit definition for Ethernet MAC Address0 Low Register */
+#define ETH_MACA0LR_MACA0L_Pos                        (0U)                     
+#define ETH_MACA0LR_MACA0L_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA0LR_MACA0L                            ETH_MACA0LR_MACA0L_Msk   /* MAC address0 low */
+
+/* Bit definition for Ethernet MAC Address1 High Register */
+#define ETH_MACA1HR_AE_Pos                            (31U)                    
+#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk       /* Address enable */
+#define ETH_MACA1HR_SA_Pos                            (30U)                    
+#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk       /* Source address */
+#define ETH_MACA1HR_MBC_Pos                           (24U)                    
+#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk      /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
+#define ETH_MACA1HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA1HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
+#define ETH_MACA1HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA1HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA1HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
+#define ETH_MACA1HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [7:0]   */
+#define ETH_MACA1HR_MACA1H_Pos                        (0U)                     
+#define ETH_MACA1HR_MACA1H_Msk                        (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA1HR_MACA1H                            ETH_MACA1HR_MACA1H_Msk   /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address1 Low Register */
+#define ETH_MACA1LR_MACA1L_Pos                        (0U)                     
+#define ETH_MACA1LR_MACA1L_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA1LR_MACA1L                            ETH_MACA1LR_MACA1L_Msk   /* MAC address1 low */
+
+/* Bit definition for Ethernet MAC Address2 High Register */
+#define ETH_MACA2HR_AE_Pos                            (31U)                    
+#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk       /* Address enable */
+#define ETH_MACA2HR_SA_Pos                            (30U)                    
+#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk       /* Source address */
+#define ETH_MACA2HR_MBC_Pos                           (24U)                    
+#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk      /* Mask byte control */
+#define ETH_MACA2HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA2HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
+#define ETH_MACA2HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA2HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA2HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
+#define ETH_MACA2HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */
+#define ETH_MACA2HR_MACA2H_Pos                        (0U)                     
+#define ETH_MACA2HR_MACA2H_Msk                        (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA2HR_MACA2H                            ETH_MACA2HR_MACA2H_Msk   /* MAC address1 high */
+
+/* Bit definition for Ethernet MAC Address2 Low Register */
+#define ETH_MACA2LR_MACA2L_Pos                        (0U)                     
+#define ETH_MACA2LR_MACA2L_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA2LR_MACA2L                            ETH_MACA2LR_MACA2L_Msk   /* MAC address2 low */
+
+/* Bit definition for Ethernet MAC Address3 High Register */
+#define ETH_MACA3HR_AE_Pos                            (31U)                    
+#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk       /* Address enable */
+#define ETH_MACA3HR_SA_Pos                            (30U)                    
+#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk       /* Source address */
+#define ETH_MACA3HR_MBC_Pos                           (24U)                    
+#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk      /* Mask byte control */
+#define ETH_MACA3HR_MBC_HBits15_8                     0x20000000U              /* Mask MAC Address high reg bits [15:8] */
+#define ETH_MACA3HR_MBC_HBits7_0                      0x10000000U              /* Mask MAC Address high reg bits [7:0]  */
+#define ETH_MACA3HR_MBC_LBits31_24                    0x08000000U              /* Mask MAC Address low reg bits [31:24] */
+#define ETH_MACA3HR_MBC_LBits23_16                    0x04000000U              /* Mask MAC Address low reg bits [23:16] */
+#define ETH_MACA3HR_MBC_LBits15_8                     0x02000000U              /* Mask MAC Address low reg bits [15:8]  */
+#define ETH_MACA3HR_MBC_LBits7_0                      0x01000000U              /* Mask MAC Address low reg bits [70]    */
+#define ETH_MACA3HR_MACA3H_Pos                        (0U)                     
+#define ETH_MACA3HR_MACA3H_Msk                        (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */
+#define ETH_MACA3HR_MACA3H                            ETH_MACA3HR_MACA3H_Msk   /* MAC address3 high */
+
+/* Bit definition for Ethernet MAC Address3 Low Register */
+#define ETH_MACA3LR_MACA3L_Pos                        (0U)                     
+#define ETH_MACA3LR_MACA3L_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MACA3LR_MACA3L                            ETH_MACA3LR_MACA3L_Msk   /* MAC address3 low */
+
+/******************************************************************************/
+/*                Ethernet MMC Registers bits definition                      */
+/******************************************************************************/
+
+/* Bit definition for Ethernet MMC Control Register */
+#define ETH_MMCCR_MCFHP_Pos                           (5U)                     
+#define ETH_MMCCR_MCFHP_Msk                           (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */
+#define ETH_MMCCR_MCFHP                               ETH_MMCCR_MCFHP_Msk      /* MMC counter Full-Half preset */
+#define ETH_MMCCR_MCP_Pos                             (4U)                     
+#define ETH_MMCCR_MCP_Msk                             (0x1UL << ETH_MMCCR_MCP_Pos) /*!< 0x00000010 */
+#define ETH_MMCCR_MCP                                 ETH_MMCCR_MCP_Msk        /* MMC counter preset           */
+#define ETH_MMCCR_MCF_Pos                             (3U)                     
+#define ETH_MMCCR_MCF_Msk                             (0x1UL << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */
+#define ETH_MMCCR_MCF                                 ETH_MMCCR_MCF_Msk        /* MMC Counter Freeze           */
+#define ETH_MMCCR_ROR_Pos                             (2U)                     
+#define ETH_MMCCR_ROR_Msk                             (0x1UL << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */
+#define ETH_MMCCR_ROR                                 ETH_MMCCR_ROR_Msk        /* Reset on Read                */
+#define ETH_MMCCR_CSR_Pos                             (1U)                     
+#define ETH_MMCCR_CSR_Msk                             (0x1UL << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */
+#define ETH_MMCCR_CSR                                 ETH_MMCCR_CSR_Msk        /* Counter Stop Rollover        */
+#define ETH_MMCCR_CR_Pos                              (0U)                     
+#define ETH_MMCCR_CR_Msk                              (0x1UL << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */
+#define ETH_MMCCR_CR                                  ETH_MMCCR_CR_Msk         /* Counters Reset               */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Register */
+#define ETH_MMCRIR_RGUFS_Pos                          (17U)                    
+#define ETH_MMCRIR_RGUFS_Msk                          (0x1UL << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIR_RGUFS                              ETH_MMCRIR_RGUFS_Msk     /* Set when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIR_RFAES_Pos                          (6U)                     
+#define ETH_MMCRIR_RFAES_Msk                          (0x1UL << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIR_RFAES                              ETH_MMCRIR_RFAES_Msk     /* Set when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIR_RFCES_Pos                          (5U)                     
+#define ETH_MMCRIR_RFCES_Msk                          (0x1UL << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIR_RFCES                              ETH_MMCRIR_RFCES_Msk     /* Set when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */
+#define ETH_MMCTIR_TGFS_Pos                           (21U)                    
+#define ETH_MMCTIR_TGFS_Msk                           (0x1UL << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIR_TGFS                               ETH_MMCTIR_TGFS_Msk      /* Set when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFMSCS_Pos                        (15U)                    
+#define ETH_MMCTIR_TGFMSCS_Msk                        (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIR_TGFMSCS                            ETH_MMCTIR_TGFMSCS_Msk   /* Set when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIR_TGFSCS_Pos                         (14U)                    
+#define ETH_MMCTIR_TGFSCS_Msk                         (0x1UL << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIR_TGFSCS                             ETH_MMCTIR_TGFSCS_Msk    /* Set when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
+#define ETH_MMCRIMR_RGUFM_Pos                         (17U)                    
+#define ETH_MMCRIMR_RGUFM_Msk                         (0x1UL << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */
+#define ETH_MMCRIMR_RGUFM                             ETH_MMCRIMR_RGUFM_Msk    /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFAEM_Pos                         (6U)                     
+#define ETH_MMCRIMR_RFAEM_Msk                         (0x1UL << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */
+#define ETH_MMCRIMR_RFAEM                             ETH_MMCRIMR_RFAEM_Msk    /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
+#define ETH_MMCRIMR_RFCEM_Pos                         (5U)                     
+#define ETH_MMCRIMR_RFCEM_Msk                         (0x1UL << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */
+#define ETH_MMCRIMR_RFCEM                             ETH_MMCRIMR_RFCEM_Msk    /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
+#define ETH_MMCTIMR_TGFM_Pos                          (21U)                    
+#define ETH_MMCTIMR_TGFM_Msk                          (0x1UL << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */
+#define ETH_MMCTIMR_TGFM                              ETH_MMCTIMR_TGFM_Msk     /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFMSCM_Pos                       (15U)                    
+#define ETH_MMCTIMR_TGFMSCM_Msk                       (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */
+#define ETH_MMCTIMR_TGFMSCM                           ETH_MMCTIMR_TGFMSCM_Msk  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
+#define ETH_MMCTIMR_TGFSCM_Pos                        (14U)                    
+#define ETH_MMCTIMR_TGFSCM_Msk                        (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */
+#define ETH_MMCTIMR_TGFSCM                            ETH_MMCTIMR_TGFSCM_Msk   /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
+#define ETH_MMCTGFSCCR_TGFSCC_Pos                     (0U)                     
+#define ETH_MMCTGFSCCR_TGFSCC_Msk                     (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFSCCR_TGFSCC                         ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
+#define ETH_MMCTGFMSCCR_TGFMSCC_Pos                   (0U)                     
+#define ETH_MMCTGFMSCCR_TGFMSCC_Msk                   (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFMSCCR_TGFMSCC                       ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
+
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
+#define ETH_MMCTGFCR_TGFC_Pos                         (0U)                     
+#define ETH_MMCTGFCR_TGFC_Msk                         (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCTGFCR_TGFC                             ETH_MMCTGFCR_TGFC_Msk    /* Number of good frames transmitted. */
+
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
+#define ETH_MMCRFCECR_RFCEC_Pos                       (0U)                     
+#define ETH_MMCRFCECR_RFCEC_Msk                       (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFCECR_RFCEC                           ETH_MMCRFCECR_RFCEC_Msk  /* Number of frames received with CRC error. */
+
+/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
+#define ETH_MMCRFAECR_RFAEC_Pos                       (0U)                     
+#define ETH_MMCRFAECR_RFAEC_Msk                       (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRFAECR_RFAEC                           ETH_MMCRFAECR_RFAEC_Msk  /* Number of frames received with alignment (dribble) error */
+
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
+#define ETH_MMCRGUFCR_RGUFC_Pos                       (0U)                     
+#define ETH_MMCRGUFCR_RGUFC_Msk                       (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */
+#define ETH_MMCRGUFCR_RGUFC                           ETH_MMCRGUFCR_RGUFC_Msk  /* Number of good unicast frames received. */
+
+/******************************************************************************/
+/*               Ethernet PTP Registers bits definition                       */
+/******************************************************************************/
+
+/* Bit definition for Ethernet PTP Time Stamp Control Register */
+#define ETH_PTPTSCR_TSPFFMAE_Pos                      (18U)
+#define ETH_PTPTSCR_TSPFFMAE_Msk                      (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */
+#define ETH_PTPTSCR_TSPFFMAE                          ETH_PTPTSCR_TSPFFMAE_Msk  /* Time stamp PTP frame filtering MAC address enable */
+#define ETH_PTPTSCR_TSCNT_Pos                         (16U)                    
+#define ETH_PTPTSCR_TSCNT_Msk                         (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */
+#define ETH_PTPTSCR_TSCNT                             ETH_PTPTSCR_TSCNT_Msk    /* Time stamp clock node type */
+#define ETH_PTPTSCR_TSSMRME_Pos                       (15U)                    
+#define ETH_PTPTSCR_TSSMRME_Msk                       (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */
+#define ETH_PTPTSCR_TSSMRME                           ETH_PTPTSCR_TSSMRME_Msk  /* Time stamp snapshot for message relevant to master enable */
+#define ETH_PTPTSCR_TSSEME_Pos                        (14U)                    
+#define ETH_PTPTSCR_TSSEME_Msk                        (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */
+#define ETH_PTPTSCR_TSSEME                            ETH_PTPTSCR_TSSEME_Msk   /* Time stamp snapshot for event message enable */
+#define ETH_PTPTSCR_TSSIPV4FE_Pos                     (13U)                    
+#define ETH_PTPTSCR_TSSIPV4FE_Msk                     (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */
+#define ETH_PTPTSCR_TSSIPV4FE                         ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */
+#define ETH_PTPTSCR_TSSIPV6FE_Pos                     (12U)                    
+#define ETH_PTPTSCR_TSSIPV6FE_Msk                     (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */
+#define ETH_PTPTSCR_TSSIPV6FE                         ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */
+#define ETH_PTPTSCR_TSSPTPOEFE_Pos                    (11U)                    
+#define ETH_PTPTSCR_TSSPTPOEFE_Msk                    (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */
+#define ETH_PTPTSCR_TSSPTPOEFE                        ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */
+#define ETH_PTPTSCR_TSPTPPSV2E_Pos                    (10U)                    
+#define ETH_PTPTSCR_TSPTPPSV2E_Msk                    (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */
+#define ETH_PTPTSCR_TSPTPPSV2E                        ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */
+#define ETH_PTPTSCR_TSSSR_Pos                         (9U)                     
+#define ETH_PTPTSCR_TSSSR_Msk                         (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */
+#define ETH_PTPTSCR_TSSSR                             ETH_PTPTSCR_TSSSR_Msk    /* Time stamp Sub-seconds rollover */
+#define ETH_PTPTSCR_TSSARFE_Pos                       (8U)                     
+#define ETH_PTPTSCR_TSSARFE_Msk                       (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */
+#define ETH_PTPTSCR_TSSARFE                           ETH_PTPTSCR_TSSARFE_Msk  /* Time stamp snapshot for all received frames enable */
+
+#define ETH_PTPTSCR_TSARU_Pos                         (5U)                     
+#define ETH_PTPTSCR_TSARU_Msk                         (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSCR_TSARU                             ETH_PTPTSCR_TSARU_Msk    /* Addend register update */
+#define ETH_PTPTSCR_TSITE_Pos                         (4U)                     
+#define ETH_PTPTSCR_TSITE_Msk                         (0x1UL << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSCR_TSITE                             ETH_PTPTSCR_TSITE_Msk    /* Time stamp interrupt trigger enable */
+#define ETH_PTPTSCR_TSSTU_Pos                         (3U)                     
+#define ETH_PTPTSCR_TSSTU_Msk                         (0x1UL << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */
+#define ETH_PTPTSCR_TSSTU                             ETH_PTPTSCR_TSSTU_Msk    /* Time stamp update */
+#define ETH_PTPTSCR_TSSTI_Pos                         (2U)                     
+#define ETH_PTPTSCR_TSSTI_Msk                         (0x1UL << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */
+#define ETH_PTPTSCR_TSSTI                             ETH_PTPTSCR_TSSTI_Msk    /* Time stamp initialize */
+#define ETH_PTPTSCR_TSFCU_Pos                         (1U)                     
+#define ETH_PTPTSCR_TSFCU_Msk                         (0x1UL << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */
+#define ETH_PTPTSCR_TSFCU                             ETH_PTPTSCR_TSFCU_Msk    /* Time stamp fine or coarse update */
+#define ETH_PTPTSCR_TSE_Pos                           (0U)                     
+#define ETH_PTPTSCR_TSE_Msk                           (0x1UL << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */
+#define ETH_PTPTSCR_TSE                               ETH_PTPTSCR_TSE_Msk      /* Time stamp enable */
+
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */
+#define ETH_PTPSSIR_STSSI_Pos                         (0U)                     
+#define ETH_PTPSSIR_STSSI_Msk                         (0xFFUL << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */
+#define ETH_PTPSSIR_STSSI                             ETH_PTPSSIR_STSSI_Msk    /* System time Sub-second increment value */
+
+/* Bit definition for Ethernet PTP Time Stamp High Register */
+#define ETH_PTPTSHR_STS_Pos                           (0U)                     
+#define ETH_PTPTSHR_STS_Msk                           (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHR_STS                               ETH_PTPTSHR_STS_Msk      /* System Time second */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Register */
+#define ETH_PTPTSLR_STPNS_Pos                         (31U)                    
+#define ETH_PTPTSLR_STPNS_Msk                         (0x1UL << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLR_STPNS                             ETH_PTPTSLR_STPNS_Msk    /* System Time Positive or negative time */
+#define ETH_PTPTSLR_STSS_Pos                          (0U)                     
+#define ETH_PTPTSLR_STSS_Msk                          (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLR_STSS                              ETH_PTPTSLR_STSS_Msk     /* System Time sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */
+#define ETH_PTPTSHUR_TSUS_Pos                         (0U)                     
+#define ETH_PTPTSHUR_TSUS_Msk                         (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSHUR_TSUS                             ETH_PTPTSHUR_TSUS_Msk    /* Time stamp update seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
+#define ETH_PTPTSLUR_TSUPNS_Pos                       (31U)                    
+#define ETH_PTPTSLUR_TSUPNS_Msk                       (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */
+#define ETH_PTPTSLUR_TSUPNS                           ETH_PTPTSLUR_TSUPNS_Msk  /* Time stamp update Positive or negative time */
+#define ETH_PTPTSLUR_TSUSS_Pos                        (0U)                     
+#define ETH_PTPTSLUR_TSUSS_Msk                        (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */
+#define ETH_PTPTSLUR_TSUSS                            ETH_PTPTSLUR_TSUSS_Msk   /* Time stamp update sub-seconds */
+
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */
+#define ETH_PTPTSAR_TSA_Pos                           (0U)                     
+#define ETH_PTPTSAR_TSA_Msk                           (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTSAR_TSA                               ETH_PTPTSAR_TSA_Msk      /* Time stamp addend */
+
+/* Bit definition for Ethernet PTP Target Time High Register */
+#define ETH_PTPTTHR_TTSH_Pos                          (0U)                     
+#define ETH_PTPTTHR_TTSH_Msk                          (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTHR_TTSH                              ETH_PTPTTHR_TTSH_Msk     /* Target time stamp high */
+
+/* Bit definition for Ethernet PTP Target Time Low Register */
+#define ETH_PTPTTLR_TTSL_Pos                          (0U)                     
+#define ETH_PTPTTLR_TTSL_Msk                          (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_PTPTTLR_TTSL                              ETH_PTPTTLR_TTSL_Msk     /* Target time stamp low */
+
+/* Bit definition for Ethernet PTP Time Stamp Status Register */
+#define ETH_PTPTSSR_TSTTR_Pos                         (5U)                     
+#define ETH_PTPTSSR_TSTTR_Msk                         (0x1UL << ETH_PTPTSSR_TSTTR_Pos) /*!< 0x00000020 */
+#define ETH_PTPTSSR_TSTTR                             ETH_PTPTSSR_TSTTR_Msk    /* Time stamp target time reached */
+#define ETH_PTPTSSR_TSSO_Pos                          (4U)                     
+#define ETH_PTPTSSR_TSSO_Msk                          (0x1UL << ETH_PTPTSSR_TSSO_Pos) /*!< 0x00000010 */
+#define ETH_PTPTSSR_TSSO                              ETH_PTPTSSR_TSSO_Msk     /* Time stamp seconds overflow */
+
+/******************************************************************************/
+/*                 Ethernet DMA Registers bits definition                     */
+/******************************************************************************/
+
+/* Bit definition for Ethernet DMA Bus Mode Register */
+#define ETH_DMABMR_MB_Pos                             (26U)
+#define ETH_DMABMR_MB_Msk                             (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */
+#define ETH_DMABMR_MB                                 ETH_DMABMR_MB_Msk       /* Mixed Burst */
+#define ETH_DMABMR_AAB_Pos                            (25U)                    
+#define ETH_DMABMR_AAB_Msk                            (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */
+#define ETH_DMABMR_AAB                                ETH_DMABMR_AAB_Msk       /* Address-Aligned beats */
+#define ETH_DMABMR_FPM_Pos                            (24U)                    
+#define ETH_DMABMR_FPM_Msk                            (0x1UL << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */
+#define ETH_DMABMR_FPM                                ETH_DMABMR_FPM_Msk       /* 4xPBL mode */
+#define ETH_DMABMR_USP_Pos                            (23U)                    
+#define ETH_DMABMR_USP_Msk                            (0x1UL << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */
+#define ETH_DMABMR_USP                                ETH_DMABMR_USP_Msk       /* Use separate PBL */
+#define ETH_DMABMR_RDP_Pos                            (17U)                    
+#define ETH_DMABMR_RDP_Msk                            (0x3FUL << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */
+#define ETH_DMABMR_RDP                                ETH_DMABMR_RDP_Msk       /* RxDMA PBL */
+#define ETH_DMABMR_RDP_1Beat                          0x00020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_DMABMR_RDP_2Beat                          0x00040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_DMABMR_RDP_4Beat                          0x00080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_8Beat                          0x00100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_16Beat                         0x00200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_32Beat                         0x00400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                
+#define ETH_DMABMR_RDP_4xPBL_4Beat                    0x01020000U              /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_DMABMR_RDP_4xPBL_8Beat                    0x01040000U              /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_DMABMR_RDP_4xPBL_16Beat                   0x01080000U              /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_DMABMR_RDP_4xPBL_32Beat                   0x01100000U              /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_DMABMR_RDP_4xPBL_64Beat                   0x01200000U              /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_DMABMR_RDP_4xPBL_128Beat                  0x01400000U              /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  
+#define ETH_DMABMR_FB_Pos                             (16U)                    
+#define ETH_DMABMR_FB_Msk                             (0x1UL << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */
+#define ETH_DMABMR_FB                                 ETH_DMABMR_FB_Msk        /* Fixed Burst */
+#define ETH_DMABMR_RTPR_Pos                           (14U)                    
+#define ETH_DMABMR_RTPR_Msk                           (0x3UL << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */
+#define ETH_DMABMR_RTPR                               ETH_DMABMR_RTPR_Msk      /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_1_1                           0x00000000U              /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_2_1                           0x00004000U              /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_3_1                           0x00008000U              /* Rx Tx priority ratio */
+#define ETH_DMABMR_RTPR_4_1                           0x0000C000U              /* Rx Tx priority ratio */  
+#define ETH_DMABMR_PBL_Pos                            (8U)                     
+#define ETH_DMABMR_PBL_Msk                            (0x3FUL << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */
+#define ETH_DMABMR_PBL                                ETH_DMABMR_PBL_Msk       /* Programmable burst length */
+#define ETH_DMABMR_PBL_1Beat                          0x00000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_DMABMR_PBL_2Beat                          0x00000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_DMABMR_PBL_4Beat                          0x00000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_8Beat                          0x00000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_16Beat                         0x00001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_32Beat                         0x00002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                
+#define ETH_DMABMR_PBL_4xPBL_4Beat                    0x01000100U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_DMABMR_PBL_4xPBL_8Beat                    0x01000200U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_DMABMR_PBL_4xPBL_16Beat                   0x01000400U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_DMABMR_PBL_4xPBL_32Beat                   0x01000800U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_DMABMR_PBL_4xPBL_64Beat                   0x01001000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_DMABMR_PBL_4xPBL_128Beat                  0x01002000U              /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_DMABMR_EDE_Pos                            (7U)                     
+#define ETH_DMABMR_EDE_Msk                            (0x1UL << ETH_DMABMR_EDE_Pos) /*!< 0x00000080 */
+#define ETH_DMABMR_EDE                                ETH_DMABMR_EDE_Msk       /* Enhanced Descriptor Enable */
+#define ETH_DMABMR_DSL_Pos                            (2U)                     
+#define ETH_DMABMR_DSL_Msk                            (0x1FUL << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */
+#define ETH_DMABMR_DSL                                ETH_DMABMR_DSL_Msk       /* Descriptor Skip Length */
+#define ETH_DMABMR_DA_Pos                             (1U)                     
+#define ETH_DMABMR_DA_Msk                             (0x1UL << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */
+#define ETH_DMABMR_DA                                 ETH_DMABMR_DA_Msk        /* DMA arbitration scheme */
+#define ETH_DMABMR_SR_Pos                             (0U)                     
+#define ETH_DMABMR_SR_Msk                             (0x1UL << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */
+#define ETH_DMABMR_SR                                 ETH_DMABMR_SR_Msk        /* Software reset */
+
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
+#define ETH_DMATPDR_TPD_Pos                           (0U)                     
+#define ETH_DMATPDR_TPD_Msk                           (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATPDR_TPD                               ETH_DMATPDR_TPD_Msk      /* Transmit poll demand */
+
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */
+#define ETH_DMARPDR_RPD_Pos                           (0U)                     
+#define ETH_DMARPDR_RPD_Msk                           (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARPDR_RPD                               ETH_DMARPDR_RPD_Msk      /* Receive poll demand  */
+
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
+#define ETH_DMARDLAR_SRL_Pos                          (0U)                     
+#define ETH_DMARDLAR_SRL_Msk                          (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMARDLAR_SRL                              ETH_DMARDLAR_SRL_Msk     /* Start of receive list */
+
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
+#define ETH_DMATDLAR_STL_Pos                          (0U)                     
+#define ETH_DMATDLAR_STL_Msk                          (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMATDLAR_STL                              ETH_DMATDLAR_STL_Msk     /* Start of transmit list */
+
+/* Bit definition for Ethernet DMA Status Register */
+#define ETH_DMASR_TSTS_Pos                            (29U)                    
+#define ETH_DMASR_TSTS_Msk                            (0x1UL << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */
+#define ETH_DMASR_TSTS                                ETH_DMASR_TSTS_Msk       /* Time-stamp trigger status */
+#define ETH_DMASR_PMTS_Pos                            (28U)                    
+#define ETH_DMASR_PMTS_Msk                            (0x1UL << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */
+#define ETH_DMASR_PMTS                                ETH_DMASR_PMTS_Msk       /* PMT status */
+#define ETH_DMASR_MMCS_Pos                            (27U)                    
+#define ETH_DMASR_MMCS_Msk                            (0x1UL << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */
+#define ETH_DMASR_MMCS                                ETH_DMASR_MMCS_Msk       /* MMC status */
+#define ETH_DMASR_EBS_Pos                             (23U)                    
+#define ETH_DMASR_EBS_Msk                             (0x7UL << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */
+#define ETH_DMASR_EBS                                 ETH_DMASR_EBS_Msk        /* Error bits status */
+  /* combination with EBS[2:0] for GetFlagStatus function */
+#define ETH_DMASR_EBS_DescAccess_Pos                  (25U)                    
+#define ETH_DMASR_EBS_DescAccess_Msk                  (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */
+#define ETH_DMASR_EBS_DescAccess                      ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMASR_EBS_ReadTransf_Pos                  (24U)                    
+#define ETH_DMASR_EBS_ReadTransf_Msk                  (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */
+#define ETH_DMASR_EBS_ReadTransf                      ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */
+#define ETH_DMASR_EBS_DataTransfTx_Pos                (23U)                    
+#define ETH_DMASR_EBS_DataTransfTx_Msk                (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */
+#define ETH_DMASR_EBS_DataTransfTx                    ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMASR_TPS_Pos                             (20U)                    
+#define ETH_DMASR_TPS_Msk                             (0x7UL << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS                                 ETH_DMASR_TPS_Msk        /* Transmit process state */
+#define ETH_DMASR_TPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Tx Command issued  */
+#define ETH_DMASR_TPS_Fetching_Pos                    (20U)                    
+#define ETH_DMASR_TPS_Fetching_Msk                    (0x1UL << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */
+#define ETH_DMASR_TPS_Fetching                        ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */
+#define ETH_DMASR_TPS_Waiting_Pos                     (21U)                    
+#define ETH_DMASR_TPS_Waiting_Msk                     (0x1UL << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */
+#define ETH_DMASR_TPS_Waiting                         ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */
+#define ETH_DMASR_TPS_Reading_Pos                     (20U)                    
+#define ETH_DMASR_TPS_Reading_Msk                     (0x3UL << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */
+#define ETH_DMASR_TPS_Reading                         ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */
+#define ETH_DMASR_TPS_Suspended_Pos                   (21U)                    
+#define ETH_DMASR_TPS_Suspended_Msk                   (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */
+#define ETH_DMASR_TPS_Suspended                       ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailable */
+#define ETH_DMASR_TPS_Closing_Pos                     (20U)                    
+#define ETH_DMASR_TPS_Closing_Msk                     (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */
+#define ETH_DMASR_TPS_Closing                         ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */
+#define ETH_DMASR_RPS_Pos                             (17U)                    
+#define ETH_DMASR_RPS_Msk                             (0x7UL << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS                                 ETH_DMASR_RPS_Msk        /* Receive process state */
+#define ETH_DMASR_RPS_Stopped                         0x00000000U              /* Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMASR_RPS_Fetching_Pos                    (17U)                    
+#define ETH_DMASR_RPS_Fetching_Msk                    (0x1UL << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */
+#define ETH_DMASR_RPS_Fetching                        ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */
+#define ETH_DMASR_RPS_Waiting_Pos                     (17U)                    
+#define ETH_DMASR_RPS_Waiting_Msk                     (0x3UL << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */
+#define ETH_DMASR_RPS_Waiting                         ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */
+#define ETH_DMASR_RPS_Suspended_Pos                   (19U)                    
+#define ETH_DMASR_RPS_Suspended_Msk                   (0x1UL << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */
+#define ETH_DMASR_RPS_Suspended                       ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */
+#define ETH_DMASR_RPS_Closing_Pos                     (17U)                    
+#define ETH_DMASR_RPS_Closing_Msk                     (0x5UL << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */
+#define ETH_DMASR_RPS_Closing                         ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */
+#define ETH_DMASR_RPS_Queuing_Pos                     (17U)                    
+#define ETH_DMASR_RPS_Queuing_Msk                     (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */
+#define ETH_DMASR_RPS_Queuing                         ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */
+#define ETH_DMASR_NIS_Pos                             (16U)                    
+#define ETH_DMASR_NIS_Msk                             (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */
+#define ETH_DMASR_NIS                                 ETH_DMASR_NIS_Msk        /* Normal interrupt summary */
+#define ETH_DMASR_AIS_Pos                             (15U)                    
+#define ETH_DMASR_AIS_Msk                             (0x1UL << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */
+#define ETH_DMASR_AIS                                 ETH_DMASR_AIS_Msk        /* Abnormal interrupt summary */
+#define ETH_DMASR_ERS_Pos                             (14U)                    
+#define ETH_DMASR_ERS_Msk                             (0x1UL << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */
+#define ETH_DMASR_ERS                                 ETH_DMASR_ERS_Msk        /* Early receive status */
+#define ETH_DMASR_FBES_Pos                            (13U)                    
+#define ETH_DMASR_FBES_Msk                            (0x1UL << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */
+#define ETH_DMASR_FBES                                ETH_DMASR_FBES_Msk       /* Fatal bus error status */
+#define ETH_DMASR_ETS_Pos                             (10U)                    
+#define ETH_DMASR_ETS_Msk                             (0x1UL << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */
+#define ETH_DMASR_ETS                                 ETH_DMASR_ETS_Msk        /* Early transmit status */
+#define ETH_DMASR_RWTS_Pos                            (9U)                     
+#define ETH_DMASR_RWTS_Msk                            (0x1UL << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */
+#define ETH_DMASR_RWTS                                ETH_DMASR_RWTS_Msk       /* Receive watchdog timeout status */
+#define ETH_DMASR_RPSS_Pos                            (8U)                     
+#define ETH_DMASR_RPSS_Msk                            (0x1UL << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */
+#define ETH_DMASR_RPSS                                ETH_DMASR_RPSS_Msk       /* Receive process stopped status */
+#define ETH_DMASR_RBUS_Pos                            (7U)                     
+#define ETH_DMASR_RBUS_Msk                            (0x1UL << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */
+#define ETH_DMASR_RBUS                                ETH_DMASR_RBUS_Msk       /* Receive buffer unavailable status */
+#define ETH_DMASR_RS_Pos                              (6U)                     
+#define ETH_DMASR_RS_Msk                              (0x1UL << ETH_DMASR_RS_Pos) /*!< 0x00000040 */
+#define ETH_DMASR_RS                                  ETH_DMASR_RS_Msk         /* Receive status */
+#define ETH_DMASR_TUS_Pos                             (5U)                     
+#define ETH_DMASR_TUS_Msk                             (0x1UL << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */
+#define ETH_DMASR_TUS                                 ETH_DMASR_TUS_Msk        /* Transmit underflow status */
+#define ETH_DMASR_ROS_Pos                             (4U)                     
+#define ETH_DMASR_ROS_Msk                             (0x1UL << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */
+#define ETH_DMASR_ROS                                 ETH_DMASR_ROS_Msk        /* Receive overflow status */
+#define ETH_DMASR_TJTS_Pos                            (3U)                     
+#define ETH_DMASR_TJTS_Msk                            (0x1UL << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */
+#define ETH_DMASR_TJTS                                ETH_DMASR_TJTS_Msk       /* Transmit jabber timeout status */
+#define ETH_DMASR_TBUS_Pos                            (2U)                     
+#define ETH_DMASR_TBUS_Msk                            (0x1UL << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */
+#define ETH_DMASR_TBUS                                ETH_DMASR_TBUS_Msk       /* Transmit buffer unavailable status */
+#define ETH_DMASR_TPSS_Pos                            (1U)                     
+#define ETH_DMASR_TPSS_Msk                            (0x1UL << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */
+#define ETH_DMASR_TPSS                                ETH_DMASR_TPSS_Msk       /* Transmit process stopped status */
+#define ETH_DMASR_TS_Pos                              (0U)                     
+#define ETH_DMASR_TS_Msk                              (0x1UL << ETH_DMASR_TS_Pos) /*!< 0x00000001 */
+#define ETH_DMASR_TS                                  ETH_DMASR_TS_Msk         /* Transmit status */
+
+/* Bit definition for Ethernet DMA Operation Mode Register */
+#define ETH_DMAOMR_DTCEFD_Pos                         (26U)                    
+#define ETH_DMAOMR_DTCEFD_Msk                         (0x1UL << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */
+#define ETH_DMAOMR_DTCEFD                             ETH_DMAOMR_DTCEFD_Msk    /* Disable Dropping of TCP/IP checksum error frames */
+#define ETH_DMAOMR_RSF_Pos                            (25U)                    
+#define ETH_DMAOMR_RSF_Msk                            (0x1UL << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */
+#define ETH_DMAOMR_RSF                                ETH_DMAOMR_RSF_Msk       /* Receive store and forward */
+#define ETH_DMAOMR_DFRF_Pos                           (24U)                    
+#define ETH_DMAOMR_DFRF_Msk                           (0x1UL << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */
+#define ETH_DMAOMR_DFRF                               ETH_DMAOMR_DFRF_Msk      /* Disable flushing of received frames */
+#define ETH_DMAOMR_TSF_Pos                            (21U)                    
+#define ETH_DMAOMR_TSF_Msk                            (0x1UL << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */
+#define ETH_DMAOMR_TSF                                ETH_DMAOMR_TSF_Msk       /* Transmit store and forward */
+#define ETH_DMAOMR_FTF_Pos                            (20U)                    
+#define ETH_DMAOMR_FTF_Msk                            (0x1UL << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */
+#define ETH_DMAOMR_FTF                                ETH_DMAOMR_FTF_Msk       /* Flush transmit FIFO */
+#define ETH_DMAOMR_TTC_Pos                            (14U)                    
+#define ETH_DMAOMR_TTC_Msk                            (0x7UL << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */
+#define ETH_DMAOMR_TTC                                ETH_DMAOMR_TTC_Msk       /* Transmit threshold control */
+#define ETH_DMAOMR_TTC_64Bytes                        0x00000000U              /* threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_DMAOMR_TTC_128Bytes                       0x00004000U              /* threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_DMAOMR_TTC_192Bytes                       0x00008000U              /* threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_DMAOMR_TTC_256Bytes                       0x0000C000U              /* threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_DMAOMR_TTC_40Bytes                        0x00010000U              /* threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_DMAOMR_TTC_32Bytes                        0x00014000U              /* threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_DMAOMR_TTC_24Bytes                        0x00018000U              /* threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_DMAOMR_TTC_16Bytes                        0x0001C000U              /* threshold level of the MTL Transmit FIFO is 16 Bytes */
+#define ETH_DMAOMR_ST_Pos                             (13U)                    
+#define ETH_DMAOMR_ST_Msk                             (0x1UL << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */
+#define ETH_DMAOMR_ST                                 ETH_DMAOMR_ST_Msk        /* Start/stop transmission command */
+#define ETH_DMAOMR_FEF_Pos                            (7U)                     
+#define ETH_DMAOMR_FEF_Msk                            (0x1UL << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */
+#define ETH_DMAOMR_FEF                                ETH_DMAOMR_FEF_Msk       /* Forward error frames */
+#define ETH_DMAOMR_FUGF_Pos                           (6U)                     
+#define ETH_DMAOMR_FUGF_Msk                           (0x1UL << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */
+#define ETH_DMAOMR_FUGF                               ETH_DMAOMR_FUGF_Msk      /* Forward undersized good frames */
+#define ETH_DMAOMR_RTC_Pos                            (3U)                     
+#define ETH_DMAOMR_RTC_Msk                            (0x3UL << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */
+#define ETH_DMAOMR_RTC                                ETH_DMAOMR_RTC_Msk       /* receive threshold control */
+#define ETH_DMAOMR_RTC_64Bytes                        0x00000000U              /* threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_DMAOMR_RTC_32Bytes                        0x00000008U              /* threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_DMAOMR_RTC_96Bytes                        0x00000010U              /* threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_DMAOMR_RTC_128Bytes                       0x00000018U              /* threshold level of the MTL Receive FIFO is 128 Bytes */
+#define ETH_DMAOMR_OSF_Pos                            (2U)                     
+#define ETH_DMAOMR_OSF_Msk                            (0x1UL << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */
+#define ETH_DMAOMR_OSF                                ETH_DMAOMR_OSF_Msk       /* operate on second frame */
+#define ETH_DMAOMR_SR_Pos                             (1U)                     
+#define ETH_DMAOMR_SR_Msk                             (0x1UL << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */
+#define ETH_DMAOMR_SR                                 ETH_DMAOMR_SR_Msk        /* Start/stop receive */
+
+/* Bit definition for Ethernet DMA Interrupt Enable Register */
+#define ETH_DMAIER_NISE_Pos                           (16U)                    
+#define ETH_DMAIER_NISE_Msk                           (0x1UL << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */
+#define ETH_DMAIER_NISE                               ETH_DMAIER_NISE_Msk      /* Normal interrupt summary enable */
+#define ETH_DMAIER_AISE_Pos                           (15U)                    
+#define ETH_DMAIER_AISE_Msk                           (0x1UL << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */
+#define ETH_DMAIER_AISE                               ETH_DMAIER_AISE_Msk      /* Abnormal interrupt summary enable */
+#define ETH_DMAIER_ERIE_Pos                           (14U)                    
+#define ETH_DMAIER_ERIE_Msk                           (0x1UL << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */
+#define ETH_DMAIER_ERIE                               ETH_DMAIER_ERIE_Msk      /* Early receive interrupt enable */
+#define ETH_DMAIER_FBEIE_Pos                          (13U)                    
+#define ETH_DMAIER_FBEIE_Msk                          (0x1UL << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */
+#define ETH_DMAIER_FBEIE                              ETH_DMAIER_FBEIE_Msk     /* Fatal bus error interrupt enable */
+#define ETH_DMAIER_ETIE_Pos                           (10U)                    
+#define ETH_DMAIER_ETIE_Msk                           (0x1UL << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */
+#define ETH_DMAIER_ETIE                               ETH_DMAIER_ETIE_Msk      /* Early transmit interrupt enable */
+#define ETH_DMAIER_RWTIE_Pos                          (9U)                     
+#define ETH_DMAIER_RWTIE_Msk                          (0x1UL << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */
+#define ETH_DMAIER_RWTIE                              ETH_DMAIER_RWTIE_Msk     /* Receive watchdog timeout interrupt enable */
+#define ETH_DMAIER_RPSIE_Pos                          (8U)                     
+#define ETH_DMAIER_RPSIE_Msk                          (0x1UL << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */
+#define ETH_DMAIER_RPSIE                              ETH_DMAIER_RPSIE_Msk     /* Receive process stopped interrupt enable */
+#define ETH_DMAIER_RBUIE_Pos                          (7U)                     
+#define ETH_DMAIER_RBUIE_Msk                          (0x1UL << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */
+#define ETH_DMAIER_RBUIE                              ETH_DMAIER_RBUIE_Msk     /* Receive buffer unavailable interrupt enable */
+#define ETH_DMAIER_RIE_Pos                            (6U)                     
+#define ETH_DMAIER_RIE_Msk                            (0x1UL << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */
+#define ETH_DMAIER_RIE                                ETH_DMAIER_RIE_Msk       /* Receive interrupt enable */
+#define ETH_DMAIER_TUIE_Pos                           (5U)                     
+#define ETH_DMAIER_TUIE_Msk                           (0x1UL << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */
+#define ETH_DMAIER_TUIE                               ETH_DMAIER_TUIE_Msk      /* Transmit Underflow interrupt enable */
+#define ETH_DMAIER_ROIE_Pos                           (4U)                     
+#define ETH_DMAIER_ROIE_Msk                           (0x1UL << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */
+#define ETH_DMAIER_ROIE                               ETH_DMAIER_ROIE_Msk      /* Receive Overflow interrupt enable */
+#define ETH_DMAIER_TJTIE_Pos                          (3U)                     
+#define ETH_DMAIER_TJTIE_Msk                          (0x1UL << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */
+#define ETH_DMAIER_TJTIE                              ETH_DMAIER_TJTIE_Msk     /* Transmit jabber timeout interrupt enable */
+#define ETH_DMAIER_TBUIE_Pos                          (2U)                     
+#define ETH_DMAIER_TBUIE_Msk                          (0x1UL << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */
+#define ETH_DMAIER_TBUIE                              ETH_DMAIER_TBUIE_Msk     /* Transmit buffer unavailable interrupt enable */
+#define ETH_DMAIER_TPSIE_Pos                          (1U)                     
+#define ETH_DMAIER_TPSIE_Msk                          (0x1UL << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */
+#define ETH_DMAIER_TPSIE                              ETH_DMAIER_TPSIE_Msk     /* Transmit process stopped interrupt enable */
+#define ETH_DMAIER_TIE_Pos                            (0U)                     
+#define ETH_DMAIER_TIE_Msk                            (0x1UL << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */
+#define ETH_DMAIER_TIE                                ETH_DMAIER_TIE_Msk       /* Transmit interrupt enable */
+
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
+#define ETH_DMAMFBOCR_OFOC_Pos                        (28U)                    
+#define ETH_DMAMFBOCR_OFOC_Msk                        (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */
+#define ETH_DMAMFBOCR_OFOC                            ETH_DMAMFBOCR_OFOC_Msk   /* Overflow bit for FIFO overflow counter */
+#define ETH_DMAMFBOCR_MFA_Pos                         (17U)                    
+#define ETH_DMAMFBOCR_MFA_Msk                         (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */
+#define ETH_DMAMFBOCR_MFA                             ETH_DMAMFBOCR_MFA_Msk    /* Number of frames missed by the application */
+#define ETH_DMAMFBOCR_OMFC_Pos                        (16U)                    
+#define ETH_DMAMFBOCR_OMFC_Msk                        (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */
+#define ETH_DMAMFBOCR_OMFC                            ETH_DMAMFBOCR_OMFC_Msk   /* Overflow bit for missed frame counter */
+#define ETH_DMAMFBOCR_MFC_Pos                         (0U)                     
+#define ETH_DMAMFBOCR_MFC_Msk                         (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */
+#define ETH_DMAMFBOCR_MFC                             ETH_DMAMFBOCR_MFC_Msk    /* Number of frames missed by the controller */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
+#define ETH_DMACHTDR_HTDAP_Pos                        (0U)                     
+#define ETH_DMACHTDR_HTDAP_Msk                        (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTDR_HTDAP                            ETH_DMACHTDR_HTDAP_Msk   /* Host transmit descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
+#define ETH_DMACHRDR_HRDAP_Pos                        (0U)                     
+#define ETH_DMACHRDR_HRDAP_Msk                        (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRDR_HRDAP                            ETH_DMACHRDR_HRDAP_Msk   /* Host receive descriptor address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
+#define ETH_DMACHTBAR_HTBAP_Pos                       (0U)                     
+#define ETH_DMACHTBAR_HTBAP_Msk                       (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHTBAR_HTBAP                           ETH_DMACHTBAR_HTBAP_Msk  /* Host transmit buffer address pointer */
+
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
+#define ETH_DMACHRBAR_HRBAP_Pos                       (0U)                     
+#define ETH_DMACHRBAR_HRBAP_Msk                       (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */
+#define ETH_DMACHRBAR_HRBAP                           ETH_DMACHRBAR_HRBAP_Msk  /* Host receive buffer address pointer */
+
+/******************************************************************************/
+/*                                                                            */
+/*                                       USB_OTG                              */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for USB_OTG_GOTGCTL register  ***********/
+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)                          
+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */
+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)                          
+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */
+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)                          
+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)                          
+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)                         
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */
+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)                         
+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */
+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)                         
+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */
+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)                         
+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */
+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)                         
+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */
+#define USB_OTG_GOTGCTL_BSVLD_Pos                (19U)                         
+#define USB_OTG_GOTGCTL_BSVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGCTL_BSVLD                    USB_OTG_GOTGCTL_BSVLD_Msk     /*!< B-session valid */
+
+/********************  Bit definition forUSB_OTG_HCFG register  ********************/
+
+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)                          
+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */
+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)                          
+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */
+
+/********************  Bit definition for USB_OTG_DCFG register  ********************/
+
+#define USB_OTG_DCFG_DSPD_Pos                    (0U)                          
+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */
+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)                          
+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */
+
+#define USB_OTG_DCFG_DAD_Pos                     (4U)                          
+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */
+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
+
+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)                         
+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */
+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
+
+#define USB_OTG_DCFG_XCVRDLY_Pos                 (14U)                         
+#define USB_OTG_DCFG_XCVRDLY_Msk                 (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
+#define USB_OTG_DCFG_XCVRDLY                     USB_OTG_DCFG_XCVRDLY_Msk        /*!< Transceiver delay */
+
+#define USB_OTG_DCFG_ERRATIM_Pos                 (15U)                         
+#define USB_OTG_DCFG_ERRATIM_Msk                 (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
+#define USB_OTG_DCFG_ERRATIM                     USB_OTG_DCFG_ERRATIM_Msk        /*!< Erratic error interrupt mask */
+
+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)                         
+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */
+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
+
+/********************  Bit definition for USB_OTG_PCGCR register  ********************/
+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)                          
+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */
+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)                          
+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */
+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)                          
+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */
+
+/********************  Bit definition for USB_OTG_GOTGINT register  ********************/
+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)                          
+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */
+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)                          
+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */
+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)                          
+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */
+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)                         
+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */
+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)                         
+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */
+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)                         
+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */
+
+/********************  Bit definition for USB_OTG_DCTL register  ********************/
+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)                          
+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */
+#define USB_OTG_DCTL_SDIS_Pos                    (1U)                          
+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */
+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)                          
+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */
+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)                          
+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */
+
+#define USB_OTG_DCTL_TCTL_Pos                    (4U)                          
+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */
+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)                          
+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */
+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)                          
+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */
+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)                          
+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */
+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)                         
+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */
+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)                         
+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */
+
+/********************  Bit definition for USB_OTG_HFIR register  ********************/
+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)                          
+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */
+
+/********************  Bit definition for USB_OTG_HFNUM register  ********************/
+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)                          
+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */
+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)                         
+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */
+
+/********************  Bit definition for USB_OTG_DSTS register  ********************/
+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)                          
+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */
+
+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)                          
+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */
+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
+#define USB_OTG_DSTS_EERR_Pos                    (3U)                          
+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */
+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)                          
+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */
+
+/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)                          
+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)                          
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */
+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)                          
+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */
+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)                          
+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)                          
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */
+
+/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/
+
+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)                          
+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */
+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)                          
+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)                          
+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */
+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)                          
+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */
+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)                         
+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */
+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)                         
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)                         
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */
+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)                         
+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */
+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)                         
+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)                         
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)                         
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */
+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)                         
+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */
+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)                         
+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */
+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)                         
+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)                         
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */
+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)                         
+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */
+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)                         
+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */
+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)                         
+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */
+
+/********************  Bit definition for USB_OTG_GRSTCTL register  ********************/
+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)                          
+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */
+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)                          
+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */
+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)                          
+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)                          
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)                          
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */
+
+
+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)                          
+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */
+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)                         
+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */
+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)                         
+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */
+
+/********************  Bit definition for USB_OTG_DIEPMSK register  ********************/
+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)                          
+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)                          
+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)                          
+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)                          
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)                          
+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)                          
+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)                          
+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)                          
+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */
+
+/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)                          
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)                         
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */
+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)                         
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */
+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
+
+/********************  Bit definition for USB_OTG_HAINT register  ********************/
+#define USB_OTG_HAINT_HAINT_Pos                  (0U)                          
+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */
+
+/********************  Bit definition for USB_OTG_DOEPMSK register  ********************/
+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)                          
+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask              */
+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)                          
+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */
+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)
+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk   /*!< OUT transaction AHB Error interrupt mask       */
+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)                          
+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */
+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)                          
+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)                          
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)                          
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */
+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)                          
+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */
+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)                          
+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */
+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)
+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask                   */
+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)
+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask                  */
+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)
+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk     /*!< NYET interrupt mask                            */
+/********************  Bit definition for USB_OTG_GINTSTS register  ********************/
+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)                          
+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */
+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)                          
+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */
+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)                          
+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */
+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)                          
+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */
+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)                          
+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */
+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)                          
+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */
+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)                          
+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)                          
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */
+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)                         
+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */
+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)                         
+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */
+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)                         
+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */
+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)                         
+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */
+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)                         
+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */
+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)                         
+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */
+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)                         
+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */
+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)                         
+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */
+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)                         
+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)                         
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)                         
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */
+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)                         
+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */
+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)                         
+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */
+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)                         
+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */
+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)                         
+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */
+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)                         
+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */
+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)                         
+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */
+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)                         
+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */
+
+/********************  Bit definition for USB_OTG_GINTMSK register  ********************/
+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)                          
+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */
+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)                          
+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */
+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)                          
+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */
+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)                          
+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */
+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)                          
+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)                          
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)                          
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */
+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)                         
+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */
+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)                         
+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */
+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)                         
+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)                         
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */
+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)                         
+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */
+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)                         
+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */
+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)                         
+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */
+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)                         
+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */
+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)                         
+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)                         
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)                         
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */
+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)                         
+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */
+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)                         
+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */
+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)                         
+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */
+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)                         
+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)                         
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */
+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)                         
+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */
+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)                         
+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */
+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)                         
+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */
+
+/********************  Bit definition for USB_OTG_DAINT register  ********************/
+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)                          
+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */
+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)                         
+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */
+
+/********************  Bit definition for USB_OTG_HAINTMSK register  ********************/
+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)                          
+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */
+
+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)                          
+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */
+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)                          
+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)                         
+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */
+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)                         
+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DAINTMSK register  ********************/
+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)                          
+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */
+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)                         
+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_GRXFSIZ register  ********************/
+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)                          
+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DVBUSDIS register  ********************/
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)                          
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */
+
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_NPTXFSA_Pos                      (0U)                          
+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */
+#define USB_OTG_NPTXFD_Pos                       (16U)                         
+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */
+#define USB_OTG_TX0FSA_Pos                       (0U)                          
+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */
+#define USB_OTG_TX0FD_Pos                        (16U)                         
+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */
+
+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)                          
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
+
+/********************  Bit definition for USB_OTG_GNPTXSTS register  ********************/
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)                          
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
+
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)                         
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
+
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)                         
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DTHRCTL register  ********************/
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)                          
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)                          
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */
+
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)                          
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */
+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)                         
+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */
+
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)                         
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */
+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)                         
+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */
+
+/********************  Bit definition for USB_OTG_DIEPEMPMSK register  ********************/
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)                          
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
+
+/********************  Bit definition for USB_OTG_DEACHINT register  ********************/
+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)                          
+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */
+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)                         
+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */
+
+/********************  Bit definition for USB_OTG_GCCFG register  ********************/
+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)                         
+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */
+#define USB_OTG_GCCFG_I2CPADEN_Pos               (17U)                         
+#define USB_OTG_GCCFG_I2CPADEN_Msk               (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */
+#define USB_OTG_GCCFG_I2CPADEN                   USB_OTG_GCCFG_I2CPADEN_Msk    /*!< Enable I2C bus connection for the external I2C PHY interface*/ 
+#define USB_OTG_GCCFG_VBUSASEN_Pos               (18U)                         
+#define USB_OTG_GCCFG_VBUSASEN_Msk               (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */
+#define USB_OTG_GCCFG_VBUSASEN                   USB_OTG_GCCFG_VBUSASEN_Msk    /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_VBUSBSEN_Pos               (19U)                         
+#define USB_OTG_GCCFG_VBUSBSEN_Msk               (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */
+#define USB_OTG_GCCFG_VBUSBSEN                   USB_OTG_GCCFG_VBUSBSEN_Msk    /*!< Enable the VBUS sensing device */
+#define USB_OTG_GCCFG_SOFOUTEN_Pos               (20U)                         
+#define USB_OTG_GCCFG_SOFOUTEN_Msk               (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */
+#define USB_OTG_GCCFG_SOFOUTEN                   USB_OTG_GCCFG_SOFOUTEN_Msk    /*!< SOF output enable */
+#define USB_OTG_GCCFG_NOVBUSSENS_Pos             (21U)                         
+#define USB_OTG_GCCFG_NOVBUSSENS_Msk             (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */
+#define USB_OTG_GCCFG_NOVBUSSENS                 USB_OTG_GCCFG_NOVBUSSENS_Msk  /*!< VBUS sensing disable option*/ 
+
+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)                          
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)                         
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
+
+/********************  Bit definition for USB_OTG_CID register  ********************/
+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)                          
+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */
+
+/********************  Bit definition for USB_OTG_DIEPEACHMSK1 register  ********************/
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)                          
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)                          
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)                          
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)                          
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)                          
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)                          
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask                                */
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)                          
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                                */
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)                         
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                                */
+
+/********************  Bit definition for USB_OTG_HPRT register  ********************/
+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)                          
+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */
+#define USB_OTG_HPRT_PCDET_Pos                   (1U)                          
+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */
+#define USB_OTG_HPRT_PENA_Pos                    (2U)                          
+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */
+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)                          
+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */
+#define USB_OTG_HPRT_POCA_Pos                    (4U)                          
+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */
+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)                          
+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */
+#define USB_OTG_HPRT_PRES_Pos                    (6U)                          
+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume                */
+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)                          
+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend               */
+#define USB_OTG_HPRT_PRST_Pos                    (8U)                          
+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset                 */
+
+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)                         
+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status           */
+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_HPRT_PPWR_Pos                    (12U)                         
+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power                 */
+
+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)                         
+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control          */
+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
+
+#define USB_OTG_HPRT_PSPD_Pos                    (17U)                         
+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed                 */
+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
+
+/********************  Bit definition for USB_OTG_DOEPEACHMSK1 register  ********************/
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)                          
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask         */
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)                          
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask          */
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)                          
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask                    */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)                          
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask  */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)                          
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask   */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)                          
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask            */
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)                          
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask                     */
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)                          
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)                         
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask               */
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)                         
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask                        */
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)                         
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask                       */
+
+/********************  Bit definition for USB_OTG_HPTXFSIZ register  ********************/
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)                          
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address            */
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)                         
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth                    */
+
+/********************  Bit definition for USB_OTG_DIEPCTL register  ********************/
+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)                          
+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size              */
+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)                         
+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint              */
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)                         
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame                   */
+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)                         
+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status                       */
+
+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)                         
+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type                    */
+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)                         
+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake                  */
+
+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)                         
+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number                    */
+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)                         
+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK                        */
+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)                         
+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID                    */
+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)                         
+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame                    */
+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)                         
+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable                 */
+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)                         
+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable                  */
+
+/********************  Bit definition for USB_OTG_HCCHAR register  ********************/
+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)                          
+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */
+
+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)                         
+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */
+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)                         
+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */
+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)                         
+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */
+
+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)                         
+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */
+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
+
+#define USB_OTG_HCCHAR_MC_Pos                    (20U)                         
+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */
+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
+
+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)                         
+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */
+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)                         
+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */
+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)                         
+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */
+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)                         
+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */
+
+/********************  Bit definition for USB_OTG_HCSPLT register  ********************/
+
+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)                          
+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */
+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
+
+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)                          
+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */
+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
+
+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)                         
+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */
+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)                         
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */
+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)                         
+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */
+
+/********************  Bit definition for USB_OTG_HCINT register  ********************/
+#define USB_OTG_HCINT_XFRC_Pos                   (0U)                          
+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */
+#define USB_OTG_HCINT_CHH_Pos                    (1U)                          
+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */
+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)                          
+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */
+#define USB_OTG_HCINT_STALL_Pos                  (3U)                          
+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */
+#define USB_OTG_HCINT_NAK_Pos                    (4U)                          
+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */
+#define USB_OTG_HCINT_ACK_Pos                    (5U)                          
+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */
+#define USB_OTG_HCINT_NYET_Pos                   (6U)                          
+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */
+#define USB_OTG_HCINT_TXERR_Pos                  (7U)                          
+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */
+#define USB_OTG_HCINT_BBERR_Pos                  (8U)                          
+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */
+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)                          
+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */
+#define USB_OTG_HCINT_DTERR_Pos                  (10U)                         
+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */
+
+/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)                          
+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)                          
+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */
+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)                          
+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */
+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)                          
+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */
+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)
+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */
+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */
+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)                          
+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */
+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)                          
+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)                          
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)                          
+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)                         
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)                         
+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */
+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)                         
+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */
+
+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/
+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)                          
+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */
+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)                          
+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */
+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)                          
+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */
+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)                          
+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */
+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)                          
+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */
+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)                          
+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */
+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)                          
+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */
+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)                          
+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */
+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)                          
+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */
+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)                          
+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */
+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)                         
+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */
+
+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/
+
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)                          
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)                         
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)                         
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */
+/********************  Bit definition for USB_OTG_HCTSIZ register  ********************/
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)                          
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */
+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)                         
+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */
+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)                         
+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */
+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)                         
+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */
+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)                          
+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_HCDMA register  ********************/
+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)                          
+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */
+
+/********************  Bit definition for USB_OTG_DTXFSTS register  ********************/
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)                          
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
+
+/********************  Bit definition for USB_OTG_DIEPTXF register  ********************/
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)                          
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)                         
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */
+
+/********************  Bit definition for USB_OTG_DOEPCTL register  ********************/
+
+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)                          
+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */
+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)                         
+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */
+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)                         
+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)                         
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)                         
+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */
+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)                         
+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */
+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)                         
+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */
+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)                         
+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */
+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)                         
+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */
+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)                         
+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */
+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)                         
+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */
+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)                         
+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */
+
+/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)                          
+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */
+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)                          
+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */
+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)
+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */
+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)                          
+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */
+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)                          
+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */
+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)                          
+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< Status Phase Received For Control Write */
+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)                          
+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */
+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)
+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */
+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)                         
+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */
+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)
+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */
+/********************  Bit definition for USB_OTG_DOEPTSIZ register  ********************/
+
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)                          
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)                         
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */
+
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)                         
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */
+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
+
+/********************  Bit definition for PCGCCTL register  ********************/
+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)                          
+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */
+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)                          
+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)                          
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */
+
+/* Legacy define */
+/********************  Bit definition for OTG register  ********************/
+#define USB_OTG_CHNUM_Pos                        (0U)                          
+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */
+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */
+#define USB_OTG_BCNT_Pos                         (4U)                          
+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos)  /*!< 0x00007FF0 */
+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */
+
+#define USB_OTG_DPID_Pos                         (15U)                         
+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)    /*!< 0x00018000 */
+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */
+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */
+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */
+
+#define USB_OTG_PKTSTS_Pos                       (17U)                         
+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos)  /*!< 0x001E0000 */
+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */
+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */
+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */
+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */
+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */
+
+#define USB_OTG_EPNUM_Pos                        (0U)                          
+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)   /*!< 0x0000000F */
+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */
+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */
+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */
+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */
+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */
+
+#define USB_OTG_FRMNUM_Pos                       (21U)                         
+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos)  /*!< 0x01E00000 */
+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */
+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */
+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */
+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */
+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+
+/******************************* ADC Instances ********************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
+                                       ((INSTANCE) == ADC2) || \
+                                       ((INSTANCE) == ADC3))
+
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
+
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)
+
+/******************************* CAN Instances ********************************/
+#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
+                                       ((INSTANCE) == CAN2))
+/******************************* CRC Instances ********************************/
+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
+
+/******************************* DAC Instances ********************************/
+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
+
+/******************************* DCMI Instances *******************************/
+#define IS_DCMI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCMI)
+
+/******************************** DMA Instances *******************************/
+#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
+                                              ((INSTANCE) == DMA1_Stream1) || \
+                                              ((INSTANCE) == DMA1_Stream2) || \
+                                              ((INSTANCE) == DMA1_Stream3) || \
+                                              ((INSTANCE) == DMA1_Stream4) || \
+                                              ((INSTANCE) == DMA1_Stream5) || \
+                                              ((INSTANCE) == DMA1_Stream6) || \
+                                              ((INSTANCE) == DMA1_Stream7) || \
+                                              ((INSTANCE) == DMA2_Stream0) || \
+                                              ((INSTANCE) == DMA2_Stream1) || \
+                                              ((INSTANCE) == DMA2_Stream2) || \
+                                              ((INSTANCE) == DMA2_Stream3) || \
+                                              ((INSTANCE) == DMA2_Stream4) || \
+                                              ((INSTANCE) == DMA2_Stream5) || \
+                                              ((INSTANCE) == DMA2_Stream6) || \
+                                              ((INSTANCE) == DMA2_Stream7))
+
+/******************************* GPIO Instances *******************************/
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF) || \
+                                        ((INSTANCE) == GPIOG) || \
+                                        ((INSTANCE) == GPIOH) || \
+                                        ((INSTANCE) == GPIOI))
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
+                                       ((INSTANCE) == I2C2) || \
+                                       ((INSTANCE) == I2C3))
+
+/******************************* SMBUS Instances ******************************/
+#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE
+
+/******************************** I2S Instances *******************************/
+
+#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3))
+
+/*************************** I2S Extended Instances ***************************/
+#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
+                                           ((INSTANCE) == I2S3ext))
+/* Legacy Defines */
+#define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE
+
+/******************************* RNG Instances ********************************/
+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
+
+/****************************** RTC Instances *********************************/
+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
+
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
+                                       ((INSTANCE) == SPI2) || \
+                                       ((INSTANCE) == SPI3))
+
+
+/****************** TIM Instances : All supported instances *******************/
+#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
+                                    ((INSTANCE) == TIM2) || \
+                                    ((INSTANCE) == TIM3) || \
+                                    ((INSTANCE) == TIM4) || \
+                                    ((INSTANCE) == TIM5) || \
+                                    ((INSTANCE) == TIM6) || \
+                                    ((INSTANCE) == TIM7) || \
+                                    ((INSTANCE) == TIM8) || \
+                                    ((INSTANCE) == TIM9) || \
+                                    ((INSTANCE) == TIM10)|| \
+                                    ((INSTANCE) == TIM11)|| \
+                                    ((INSTANCE) == TIM12)|| \
+                                    ((INSTANCE) == TIM13)|| \
+                                    ((INSTANCE) == TIM14))
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)  || \
+                                         ((INSTANCE) == TIM2)  || \
+                                         ((INSTANCE) == TIM3)  || \
+                                         ((INSTANCE) == TIM4)  || \
+                                         ((INSTANCE) == TIM5)  || \
+                                         ((INSTANCE) == TIM8)  || \
+                                         ((INSTANCE) == TIM9)  || \
+                                         ((INSTANCE) == TIM10) || \
+                                         ((INSTANCE) == TIM11) || \
+                                         ((INSTANCE) == TIM12) || \
+                                         ((INSTANCE) == TIM13) || \
+                                         ((INSTANCE) == TIM14))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                       ((INSTANCE) == TIM2) || \
+                                       ((INSTANCE) == TIM3) || \
+                                       ((INSTANCE) == TIM4) || \
+                                       ((INSTANCE) == TIM5) || \
+                                       ((INSTANCE) == TIM8) || \
+                                       ((INSTANCE) == TIM9) || \
+                                       ((INSTANCE) == TIM12)) 
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
+                                         ((INSTANCE) == TIM2) || \
+                                         ((INSTANCE) == TIM3) || \
+                                         ((INSTANCE) == TIM4) || \
+                                         ((INSTANCE) == TIM5) || \
+                                         ((INSTANCE) == TIM8))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                       ((INSTANCE) == TIM2) || \
+                                       ((INSTANCE) == TIM3) || \
+                                       ((INSTANCE) == TIM4) || \
+                                       ((INSTANCE) == TIM5) || \
+                                       ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : Advanced-control timers *****************/
+#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                           ((INSTANCE) == TIM8))
+
+/******************* TIM Instances : Timer input XOR function *****************/
+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || \
+                                         ((INSTANCE) == TIM2) || \
+                                         ((INSTANCE) == TIM3) || \
+                                         ((INSTANCE) == TIM4) || \
+                                         ((INSTANCE) == TIM5) || \
+                                         ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : DMA requests generation (UDE) *************/
+#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                       ((INSTANCE) == TIM2) || \
+                                       ((INSTANCE) == TIM3) || \
+                                       ((INSTANCE) == TIM4) || \
+                                       ((INSTANCE) == TIM5) || \
+                                       ((INSTANCE) == TIM6) || \
+                                       ((INSTANCE) == TIM7) || \
+                                       ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/
+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                          ((INSTANCE) == TIM2) || \
+                                          ((INSTANCE) == TIM3) || \
+                                          ((INSTANCE) == TIM4) || \
+                                          ((INSTANCE) == TIM5) || \
+                                          ((INSTANCE) == TIM8))
+
+/************ TIM Instances : DMA requests generation (COMDE) *****************/
+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                          ((INSTANCE) == TIM2) || \
+                                          ((INSTANCE) == TIM3) || \
+                                          ((INSTANCE) == TIM4) || \
+                                          ((INSTANCE) == TIM5) || \
+                                          ((INSTANCE) == TIM8))
+
+/******************** TIM Instances : DMA burst feature ***********************/
+#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                             ((INSTANCE) == TIM2) || \
+                                             ((INSTANCE) == TIM3) || \
+                                             ((INSTANCE) == TIM4) || \
+                                             ((INSTANCE) == TIM5) || \
+                                             ((INSTANCE) == TIM8))
+
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
+#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
+                                          ((INSTANCE) == TIM2)  || \
+                                          ((INSTANCE) == TIM3)  || \
+                                          ((INSTANCE) == TIM4)  || \
+                                          ((INSTANCE) == TIM5)  || \
+                                          ((INSTANCE) == TIM6)  || \
+                                          ((INSTANCE) == TIM7)  || \
+                                          ((INSTANCE) == TIM8))
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                         ((INSTANCE) == TIM2) || \
+                                         ((INSTANCE) == TIM3) || \
+                                         ((INSTANCE) == TIM4) || \
+                                         ((INSTANCE) == TIM5) || \
+                                         ((INSTANCE) == TIM8) || \
+                                         ((INSTANCE) == TIM9) || \
+                                         ((INSTANCE) == TIM12))
+/********************** TIM Instances : 32 bit Counter ************************/
+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \
+                                              ((INSTANCE) == TIM5))
+
+/***************** TIM Instances : external trigger input available ************/
+#define IS_TIM_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                        ((INSTANCE) == TIM2) || \
+                                        ((INSTANCE) == TIM3) || \
+                                        ((INSTANCE) == TIM4) || \
+                                        ((INSTANCE) == TIM5) || \
+                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : remapping capability **********************/
+#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
+                                         ((INSTANCE) == TIM5)  || \
+                                         ((INSTANCE) == TIM11))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ((((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM2) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM3) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM4) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM5) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM8) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)))           \
+    ||                                         \
+    (((INSTANCE) == TIM9) &&                   \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((INSTANCE) == TIM10) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((INSTANCE) == TIM11) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((INSTANCE) == TIM12) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)))           \
+    ||                                         \
+    (((INSTANCE) == TIM13) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1)))           \
+    ||                                         \
+    (((INSTANCE) == TIM14) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1))))
+
+/************ TIM Instances : complementary output(s) available ***************/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((((INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)))            \
+    ||                                          \
+    (((INSTANCE) == TIM8) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3))))
+
+/****************** TIM Instances : supporting counting mode selection ********/
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)  || \
+                                                  ((INSTANCE) == TIM2) || \
+                                                  ((INSTANCE) == TIM3) || \
+                                                  ((INSTANCE) == TIM4) || \
+                                                  ((INSTANCE) == TIM5) || \
+                                                  ((INSTANCE) == TIM8) || \
+                                                  ((INSTANCE) == TIM9) || \
+                                                  ((INSTANCE) == TIM10)|| \
+                                                  ((INSTANCE) == TIM11)|| \
+                                                  ((INSTANCE) == TIM12)|| \
+                                                  ((INSTANCE) == TIM13)|| \
+                                                  ((INSTANCE) == TIM14))
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)|| \
+                                                     ((INSTANCE) == TIM8))
+
+
+/****************** TIM Instances : supporting OCxREF clear *******************/
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TIM1) || \
+                                                       ((INSTANCE) == TIM2) || \
+                                                       ((INSTANCE) == TIM3) || \
+                                                       ((INSTANCE) == TIM4) || \
+                                                       ((INSTANCE) == TIM5) || \
+                                                       ((INSTANCE) == TIM8))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM9) || \
+                                                        ((INSTANCE) == TIM12))
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8))
+
+/****** TIM Instances : supporting external clock mode 1 for TIX inputs ******/
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM9) || \
+                                                        ((INSTANCE) == TIM12))
+
+/********** TIM Instances : supporting internal trigger inputs(ITRX) *********/
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) || \
+                                                        ((INSTANCE) == TIM3) || \
+                                                        ((INSTANCE) == TIM4) || \
+                                                        ((INSTANCE) == TIM5) || \
+                                                        ((INSTANCE) == TIM8) || \
+                                                        ((INSTANCE) == TIM9) || \
+                                                        ((INSTANCE) == TIM12))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                       ((INSTANCE) == TIM8))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                      ((INSTANCE) == TIM2) || \
+                                                      ((INSTANCE) == TIM3) || \
+                                                      ((INSTANCE) == TIM4) || \
+                                                      ((INSTANCE) == TIM5) || \
+                                                      ((INSTANCE) == TIM8) || \
+                                                      ((INSTANCE) == TIM9) || \
+                                                      ((INSTANCE) == TIM12))
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                                          ((INSTANCE) == TIM2) || \
+                                                          ((INSTANCE) == TIM3) || \
+                                                          ((INSTANCE) == TIM4) || \
+                                                          ((INSTANCE) == TIM5) || \
+                                                          ((INSTANCE) == TIM8))
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1) || \
+                                          ((INSTANCE) == TIM8))
+
+/******************** USART Instances : Synchronous mode **********************/
+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                     ((INSTANCE) == USART2) || \
+                                     ((INSTANCE) == USART3) || \
+                                     ((INSTANCE) == USART6))
+
+/******************** UART Instances : Half-Duplex mode **********************/
+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                               ((INSTANCE) == USART2) || \
+                                               ((INSTANCE) == USART3) || \
+                                               ((INSTANCE) == UART4)  || \
+                                               ((INSTANCE) == UART5)  || \
+                                               ((INSTANCE) == USART6))
+
+/* Legacy defines */
+#define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
+
+/****************** UART Instances : Hardware Flow control ********************/
+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                           ((INSTANCE) == USART2) || \
+                                           ((INSTANCE) == USART3) || \
+                                           ((INSTANCE) == USART6))
+/******************** UART Instances : LIN mode **********************/
+#define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE
+
+/********************* UART Instances : Smart card mode ***********************/
+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                         ((INSTANCE) == USART2) || \
+                                         ((INSTANCE) == USART3) || \
+                                         ((INSTANCE) == USART6))
+
+/*********************** UART Instances : IRDA mode ***************************/
+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
+                                    ((INSTANCE) == USART2) || \
+                                    ((INSTANCE) == USART3) || \
+                                    ((INSTANCE) == UART4)  || \
+                                    ((INSTANCE) == UART5)  || \
+                                    ((INSTANCE) == USART6))
+
+
+/*********************** PCD Instances ****************************************/
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                       ((INSTANCE) == USB_OTG_HS))
+
+/*********************** HCD Instances ****************************************/
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
+                                       ((INSTANCE) == USB_OTG_HS))
+
+/****************************** SDIO Instances ********************************/
+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)
+
+/****************************** IWDG Instances ********************************/
+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
+
+/****************************** WWDG Instances ********************************/
+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
+
+/****************************** USB Exported Constants ************************/
+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
+#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
+#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
+#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */
+
+/*
+ * @brief Specific devices reset values definitions
+ */
+#define RCC_PLLCFGR_RST_VALUE              0x24003010U
+#define RCC_PLLI2SCFGR_RST_VALUE           0x20003000U
+
+#define RCC_MAX_FREQUENCY           168000000U         /*!< Max frequency of family in Hz*/
+#define RCC_MAX_FREQUENCY_SCALE1    RCC_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */
+#define RCC_MAX_FREQUENCY_SCALE2    144000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */
+#define RCC_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */
+#define RCC_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */
+#define RCC_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */
+#define RCC_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */
+
+#define RCC_PLLN_MIN_VALUE                 50U
+#define RCC_PLLN_MAX_VALUE                432U
+
+#define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
+#define FLASH_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
+#define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
+#define FLASH_SCALE1_LATENCY4_FREQ   120000000U     /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */
+#define FLASH_SCALE1_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */
+
+#define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
+#define FLASH_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
+#define FLASH_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
+#define FLASH_SCALE2_LATENCY4_FREQ   12000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */
+
+#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
+#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
+#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
+#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
+/******************************************************************************/
+/*  For a painless codes migration between the STM32F4xx device product       */
+/*  lines, the aliases defined below are put in place to overcome the         */
+/*  differences in the interrupt handlers and IRQn definitions.               */
+/*  No need to update developed interrupt code when moving across             */
+/*  product lines within the same STM32F4 Family                              */
+/******************************************************************************/
+/* Aliases for __IRQn */
+#define FMC_IRQn              FSMC_IRQn
+
+/* Aliases for __IRQHandler */
+#define FMC_IRQHandler        FSMC_IRQHandler
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F407xx_H */
diff --git a/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
index 2c3482d..92fe3a7 100644
--- a/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
+++ b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h
@@ -1,301 +1,301 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
-  *            
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The STM32F4xx device used in the target application
-  *              - To use or not the peripheral's drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral's registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_HAL_DRIVER"
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f4xx
-  * @{
-  */
-    
-#ifndef __STM32F4xx_H
-#define __STM32F4xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-   
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-  
-/**
-  * @brief STM32 Family
-  */
-#if !defined  (STM32F4)
-#define STM32F4
-#endif /* STM32F4 */
-
-/* Uncomment the line below according to the target STM32 device used in your
-   application 
-  */
-#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
-    !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
-    !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
-    !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
-    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
-    !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
-  /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
-  /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
-  /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
-  /* #define STM32F417xx */   /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
-  /* #define STM32F427xx */   /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
-  /* #define STM32F437xx */   /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
-  /* #define STM32F429xx */   /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, 
-                                   STM32F439NI, STM32F429IG  and STM32F429II Devices */
-  /* #define STM32F439xx */   /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, 
-                                   STM32F439NI, STM32F439IG and STM32F439II Devices */
-  /* #define STM32F401xC */   /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
-  /* #define STM32F401xE */   /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
-  /* #define STM32F410Tx */   /*!< STM32F410T8 and STM32F410TB Devices */
-  /* #define STM32F410Cx */   /*!< STM32F410C8 and STM32F410CB Devices */
-  /* #define STM32F410Rx */   /*!< STM32F410R8 and STM32F410RB Devices */
-  /* #define STM32F411xE */   /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
-  /* #define STM32F446xx */   /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, 
-                                   and STM32F446ZE Devices */
-  /* #define STM32F469xx */   /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, 
-                                   STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
-  /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
-                                   and STM32F479NG Devices */
-  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
-  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
-  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
-  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
-  /* #define STM32F413xx */   /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
-                                   STM32F413RG, STM32F413VG and STM32F413ZG Devices */
-  /* #define STM32F423xx */   /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
-#endif
-   
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-#if !defined  (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-  /*#define USE_HAL_DRIVER */
-#endif /* USE_HAL_DRIVER */
-
-/**
-  * @brief CMSIS version number V2.6.8
-  */
-#define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
-#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x08U) /*!< [15:8]  sub2 version */
-#define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
-#define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
-                                         |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
-                                         |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
-                                         |(__STM32F4xx_CMSIS_VERSION_RC))
-
-/**
-  * @}
-  */
-
-/** @addtogroup Device_Included
-  * @{
-  */
-
-#if defined(STM32F405xx)
-  #include "stm32f405xx.h"
-#elif defined(STM32F415xx)
-  #include "stm32f415xx.h"
-#elif defined(STM32F407xx)
-  #include "stm32f407xx.h"
-#elif defined(STM32F417xx)
-  #include "stm32f417xx.h"
-#elif defined(STM32F427xx)
-  #include "stm32f427xx.h"
-#elif defined(STM32F437xx)
-  #include "stm32f437xx.h"
-#elif defined(STM32F429xx)
-  #include "stm32f429xx.h"
-#elif defined(STM32F439xx)
-  #include "stm32f439xx.h"
-#elif defined(STM32F401xC)
-  #include "stm32f401xc.h"
-#elif defined(STM32F401xE)
-  #include "stm32f401xe.h"
-#elif defined(STM32F410Tx)
-  #include "stm32f410tx.h"
-#elif defined(STM32F410Cx)
-  #include "stm32f410cx.h"
-#elif defined(STM32F410Rx)
-  #include "stm32f410rx.h"
-#elif defined(STM32F411xE)
-  #include "stm32f411xe.h"
-#elif defined(STM32F446xx)
-  #include "stm32f446xx.h"
-#elif defined(STM32F469xx)
-  #include "stm32f469xx.h"
-#elif defined(STM32F479xx)
-  #include "stm32f479xx.h"
-#elif defined(STM32F412Cx)
-  #include "stm32f412cx.h"
-#elif defined(STM32F412Zx)
-  #include "stm32f412zx.h"
-#elif defined(STM32F412Rx)
-  #include "stm32f412rx.h"
-#elif defined(STM32F412Vx)
-  #include "stm32f412vx.h"
-#elif defined(STM32F413xx)
-  #include "stm32f413xx.h"
-#elif defined(STM32F423xx)
-  #include "stm32f423xx.h"
-#else
- #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */ 
-typedef enum 
-{
-  RESET = 0U, 
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum 
-{
-  DISABLE = 0U, 
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum
-{
-  SUCCESS = 0U,
-  ERROR = !SUCCESS
-} ErrorStatus;
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
-
-/* Use of CMSIS compiler intrinsics for register exclusive access */
-/* Atomic 32-bit register access macro to set one or several bits */
-#define ATOMIC_SET_BIT(REG, BIT)                             \
-  do {                                                       \
-    uint32_t val;                                            \
-    do {                                                     \
-      val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT);       \
-    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
-  } while(0)
-
-/* Atomic 32-bit register access macro to clear one or several bits */
-#define ATOMIC_CLEAR_BIT(REG, BIT)                           \
-  do {                                                       \
-    uint32_t val;                                            \
-    do {                                                     \
-      val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT);      \
-    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
-  } while(0)
-
-/* Atomic 32-bit register access macro to clear and set one or several bits */
-#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)                          \
-  do {                                                                     \
-    uint32_t val;                                                          \
-    do {                                                                   \
-      val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
-    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U);               \
-  } while(0)
-
-/* Atomic 16-bit register access macro to set one or several bits */
-#define ATOMIC_SETH_BIT(REG, BIT)                            \
-  do {                                                       \
-    uint16_t val;                                            \
-    do {                                                     \
-      val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT);       \
-    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
-  } while(0)
-
-/* Atomic 16-bit register access macro to clear one or several bits */
-#define ATOMIC_CLEARH_BIT(REG, BIT)                          \
-  do {                                                       \
-    uint16_t val;                                            \
-    do {                                                     \
-      val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT);      \
-    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
-  } while(0)
-
-/* Atomic 16-bit register access macro to clear and set one or several bits */
-#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)                         \
-  do {                                                                     \
-    uint16_t val;                                                          \
-    do {                                                                   \
-      val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
-    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U);               \
-  } while(0)
-
-/**
-  * @}
-  */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32f4xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32F4xx_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS STM32F4xx Device Peripheral Access Layer Header File.
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32F4xx device used in the target application
+  *              - To use or not the peripheral's drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral's registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_HAL_DRIVER"
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx
+  * @{
+  */
+    
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+   
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/**
+  * @brief STM32 Family
+  */
+#if !defined  (STM32F4)
+#define STM32F4
+#endif /* STM32F4 */
+
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+#if !defined (STM32F405xx) && !defined (STM32F415xx) && !defined (STM32F407xx) && !defined (STM32F417xx) && \
+    !defined (STM32F427xx) && !defined (STM32F437xx) && !defined (STM32F429xx) && !defined (STM32F439xx) && \
+    !defined (STM32F401xC) && !defined (STM32F401xE) && !defined (STM32F410Tx) && !defined (STM32F410Cx) && \
+    !defined (STM32F410Rx) && !defined (STM32F411xE) && !defined (STM32F446xx) && !defined (STM32F469xx) && \
+    !defined (STM32F479xx) && !defined (STM32F412Cx) && !defined (STM32F412Rx) && !defined (STM32F412Vx) && \
+    !defined (STM32F412Zx) && !defined (STM32F413xx) && !defined (STM32F423xx)
+  /* #define STM32F405xx */   /*!< STM32F405RG, STM32F405VG and STM32F405ZG Devices */
+  /* #define STM32F415xx */   /*!< STM32F415RG, STM32F415VG and STM32F415ZG Devices */
+  /* #define STM32F407xx */   /*!< STM32F407VG, STM32F407VE, STM32F407ZG, STM32F407ZE, STM32F407IG  and STM32F407IE Devices */
+  /* #define STM32F417xx */   /*!< STM32F417VG, STM32F417VE, STM32F417ZG, STM32F417ZE, STM32F417IG and STM32F417IE Devices */
+  /* #define STM32F427xx */   /*!< STM32F427VG, STM32F427VI, STM32F427ZG, STM32F427ZI, STM32F427IG and STM32F427II Devices */
+  /* #define STM32F437xx */   /*!< STM32F437VG, STM32F437VI, STM32F437ZG, STM32F437ZI, STM32F437IG and STM32F437II Devices */
+  /* #define STM32F429xx */   /*!< STM32F429VG, STM32F429VI, STM32F429ZG, STM32F429ZI, STM32F429BG, STM32F429BI, STM32F429NG, 
+                                   STM32F439NI, STM32F429IG  and STM32F429II Devices */
+  /* #define STM32F439xx */   /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG, 
+                                   STM32F439NI, STM32F439IG and STM32F439II Devices */
+  /* #define STM32F401xC */   /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
+  /* #define STM32F401xE */   /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+  /* #define STM32F410Tx */   /*!< STM32F410T8 and STM32F410TB Devices */
+  /* #define STM32F410Cx */   /*!< STM32F410C8 and STM32F410CB Devices */
+  /* #define STM32F410Rx */   /*!< STM32F410R8 and STM32F410RB Devices */
+  /* #define STM32F411xE */   /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
+  /* #define STM32F446xx */   /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC, 
+                                   and STM32F446ZE Devices */
+  /* #define STM32F469xx */   /*!< STM32F469AI, STM32F469II, STM32F469BI, STM32F469NI, STM32F469AG, STM32F469IG, STM32F469BG, 
+                                   STM32F469NG, STM32F469AE, STM32F469IE, STM32F469BE and STM32F469NE Devices */
+  /* #define STM32F479xx */   /*!< STM32F479AI, STM32F479II, STM32F479BI, STM32F479NI, STM32F479AG, STM32F479IG, STM32F479BG 
+                                   and STM32F479NG Devices */
+  /* #define STM32F412Cx */   /*!< STM32F412CEU and STM32F412CGU Devices */
+  /* #define STM32F412Zx */   /*!< STM32F412ZET, STM32F412ZGT, STM32F412ZEJ and STM32F412ZGJ Devices */
+  /* #define STM32F412Vx */   /*!< STM32F412VET, STM32F412VGT, STM32F412VEH and STM32F412VGH Devices */
+  /* #define STM32F412Rx */   /*!< STM32F412RET, STM32F412RGT, STM32F412REY and STM32F412RGY Devices */
+  /* #define STM32F413xx */   /*!< STM32F413CH, STM32F413MH, STM32F413RH, STM32F413VH, STM32F413ZH, STM32F413CG, STM32F413MG,
+                                   STM32F413RG, STM32F413VG and STM32F413ZG Devices */
+  /* #define STM32F423xx */   /*!< STM32F423CH, STM32F423RH, STM32F423VH and STM32F423ZH Devices */
+#endif
+   
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS version number V2.6.8
+  */
+#define __STM32F4xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
+#define __STM32F4xx_CMSIS_VERSION_SUB1   (0x06U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2   (0x08U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
+#define __STM32F4xx_CMSIS_VERSION        ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
+                                         |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
+                                         |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\
+                                         |(__STM32F4xx_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32F405xx)
+  #include "stm32f405xx.h"
+#elif defined(STM32F415xx)
+  #include "stm32f415xx.h"
+#elif defined(STM32F407xx)
+  #include "stm32f407xx.h"
+#elif defined(STM32F417xx)
+  #include "stm32f417xx.h"
+#elif defined(STM32F427xx)
+  #include "stm32f427xx.h"
+#elif defined(STM32F437xx)
+  #include "stm32f437xx.h"
+#elif defined(STM32F429xx)
+  #include "stm32f429xx.h"
+#elif defined(STM32F439xx)
+  #include "stm32f439xx.h"
+#elif defined(STM32F401xC)
+  #include "stm32f401xc.h"
+#elif defined(STM32F401xE)
+  #include "stm32f401xe.h"
+#elif defined(STM32F410Tx)
+  #include "stm32f410tx.h"
+#elif defined(STM32F410Cx)
+  #include "stm32f410cx.h"
+#elif defined(STM32F410Rx)
+  #include "stm32f410rx.h"
+#elif defined(STM32F411xE)
+  #include "stm32f411xe.h"
+#elif defined(STM32F446xx)
+  #include "stm32f446xx.h"
+#elif defined(STM32F469xx)
+  #include "stm32f469xx.h"
+#elif defined(STM32F479xx)
+  #include "stm32f479xx.h"
+#elif defined(STM32F412Cx)
+  #include "stm32f412cx.h"
+#elif defined(STM32F412Zx)
+  #include "stm32f412zx.h"
+#elif defined(STM32F412Rx)
+  #include "stm32f412rx.h"
+#elif defined(STM32F412Vx)
+  #include "stm32f412vx.h"
+#elif defined(STM32F413xx)
+  #include "stm32f413xx.h"
+#elif defined(STM32F423xx)
+  #include "stm32f423xx.h"
+#else
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */ 
+typedef enum 
+{
+  RESET = 0U, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum 
+{
+  DISABLE = 0U, 
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  SUCCESS = 0U,
+  ERROR = !SUCCESS
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macro
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
+
+/* Use of CMSIS compiler intrinsics for register exclusive access */
+/* Atomic 32-bit register access macro to set one or several bits */
+#define ATOMIC_SET_BIT(REG, BIT)                             \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT);       \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEAR_BIT(REG, BIT)                           \
+  do {                                                       \
+    uint32_t val;                                            \
+    do {                                                     \
+      val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 32-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK)                          \
+  do {                                                                     \
+    uint32_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U);               \
+  } while(0)
+
+/* Atomic 16-bit register access macro to set one or several bits */
+#define ATOMIC_SETH_BIT(REG, BIT)                            \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT);       \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear one or several bits */
+#define ATOMIC_CLEARH_BIT(REG, BIT)                          \
+  do {                                                       \
+    uint16_t val;                                            \
+    do {                                                     \
+      val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT);      \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
+  } while(0)
+
+/* Atomic 16-bit register access macro to clear and set one or several bits */
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK)                         \
+  do {                                                                     \
+    uint16_t val;                                                          \
+    do {                                                                   \
+      val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
+    } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U);               \
+  } while(0)
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32f4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32F4xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h
index a979ef5..d92c6f1 100644
--- a/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h
+++ b/Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h
@@ -1,104 +1,104 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32f4xx.h
-  * @author  MCD Application Team
-  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************  
-  */ 
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32f4xx_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32F4XX_H
-#define __SYSTEM_STM32F4XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32F4xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32F4xx_System_Exported_types
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-
-extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
-extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32F4xx_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F4XX_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.h
+  * @author  MCD Application Team
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************  
+  */ 
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+  * @{
+  */
+  /* This variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
diff --git a/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt b/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt
index 872e82b..5306686 100644
--- a/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt
+++ b/Drivers/CMSIS/Device/ST/STM32F4xx/LICENSE.txt
@@ -1,6 +1,6 @@
-This software component is provided to you as part of a software package and
-applicable license terms are in the  Package_license file. If you received this
-software component outside of a package or without applicable license terms,
-the terms of the Apache-2.0 license shall apply. 
-You may obtain a copy of the Apache-2.0 at:
-https://opensource.org/licenses/Apache-2.0
+This software component is provided to you as part of a software package and
+applicable license terms are in the  Package_license file. If you received this
+software component outside of a package or without applicable license terms,
+the terms of the Apache-2.0 license shall apply. 
+You may obtain a copy of the Apache-2.0 at:
+https://opensource.org/licenses/Apache-2.0
diff --git a/Drivers/CMSIS/Include/cmsis_armcc.h b/Drivers/CMSIS/Include/cmsis_armcc.h
index 4d9d064..7d751fb 100644
--- a/Drivers/CMSIS/Include/cmsis_armcc.h
+++ b/Drivers/CMSIS/Include/cmsis_armcc.h
@@ -1,865 +1,865 @@
-/**************************************************************************//**
- * @file     cmsis_armcc.h
- * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
- * @version  V5.0.4
- * @date     10. January 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_ARMCC_H
-#define __CMSIS_ARMCC_H
-
-
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
-  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* CMSIS compiler control architecture macros */
-#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
-     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
-  #define __ARM_ARCH_6M__           1
-#endif
-
-#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
-  #define __ARM_ARCH_7M__           1
-#endif
-
-#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
-  #define __ARM_ARCH_7EM__          1
-#endif
-
-  /* __ARM_ARCH_8M_BASE__  not applicable */
-  /* __ARM_ARCH_8M_MAIN__  not applicable */
-
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-  #define __ASM                                  __asm
-#endif
-#ifndef   __INLINE
-  #define __INLINE                               __inline
-#endif
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE                        static __inline
-#endif
-#ifndef   __STATIC_FORCEINLINE                 
-  #define __STATIC_FORCEINLINE                   static __forceinline
-#endif           
-#ifndef   __NO_RETURN
-  #define __NO_RETURN                            __declspec(noreturn)
-#endif
-#ifndef   __USED
-  #define __USED                                 __attribute__((used))
-#endif
-#ifndef   __WEAK
-  #define __WEAK                                 __attribute__((weak))
-#endif
-#ifndef   __PACKED
-  #define __PACKED                               __attribute__((packed))
-#endif
-#ifndef   __PACKED_STRUCT
-  #define __PACKED_STRUCT                        __packed struct
-#endif
-#ifndef   __PACKED_UNION
-  #define __PACKED_UNION                         __packed union
-#endif
-#ifndef   __UNALIGNED_UINT32        /* deprecated */
-  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
-#endif
-#ifndef   __UNALIGNED_UINT16_WRITE
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT16_READ
-  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
-#endif
-#ifndef   __UNALIGNED_UINT32_WRITE
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT32_READ
-  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
-#endif
-#ifndef   __ALIGNED
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))
-#endif
-#ifndef   __RESTRICT
-  #define __RESTRICT                             __restrict
-#endif
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq();     */
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq();    */
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
-  register uint32_t __regControl         __ASM("control");
-  return(__regControl);
-}
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
-  register uint32_t __regControl         __ASM("control");
-  __regControl = control;
-}
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
-  register uint32_t __regIPSR          __ASM("ipsr");
-  return(__regIPSR);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
-  register uint32_t __regAPSR          __ASM("apsr");
-  return(__regAPSR);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
-  register uint32_t __regXPSR          __ASM("xpsr");
-  return(__regXPSR);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  return(__regProcessStackPointer);
-}
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  register uint32_t __regProcessStackPointer  __ASM("psp");
-  __regProcessStackPointer = topOfProcStack;
-}
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  return(__regMainStackPointer);
-}
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  register uint32_t __regMainStackPointer     __ASM("msp");
-  __regMainStackPointer = topOfMainStack;
-}
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  return(__regPriMask);
-}
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
-  register uint32_t __regPriMask         __ASM("primask");
-  __regPriMask = (priMask);
-}
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__STATIC_INLINE uint32_t  __get_BASEPRI(void)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  return(__regBasePri);
-}
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
-  register uint32_t __regBasePri         __ASM("basepri");
-  __regBasePri = (basePri & 0xFFU);
-}
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  register uint32_t __regBasePriMax      __ASM("basepri_max");
-  __regBasePriMax = (basePri & 0xFFU);
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  return(__regFaultMask);
-}
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  register uint32_t __regFaultMask       __ASM("faultmask");
-  __regFaultMask = (faultMask & (uint32_t)1U);
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  register uint32_t __regfpscr         __ASM("fpscr");
-  return(__regfpscr);
-#else
-   return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-  register uint32_t __regfpscr         __ASM("fpscr");
-  __regfpscr = (fpscr);
-#else
-  (void)fpscr;
-#endif
-}
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP                             __nop
-
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI                             __wfi
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE                             __wfe
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV                             __sev
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-#define __ISB() do {\
-                   __schedule_barrier();\
-                   __isb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() do {\
-                   __schedule_barrier();\
-                   __dsb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-#define __DMB() do {\
-                   __schedule_barrier();\
-                   __dmb(0xF);\
-                   __schedule_barrier();\
-                } while (0U)
-
-                  
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV                             __rev
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
-  rev16 r0, r0
-  bx lr
-}
-#endif
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
-{
-  revsh r0, r0
-  bx lr
-}
-#endif
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-#define __ROR                             __ror
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __breakpoint(value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-  #define __RBIT                          __rbit
-#else
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
-
-  result = value;                      /* r will be reversed bits of v; first get LSB of v */
-  for (value >>= 1U; value != 0U; value >>= 1U)
-  {
-    result <<= 1U;
-    result |= value & 1U;
-    s--;
-  }
-  result <<= s;                        /* shift when v's highest bits are zero */
-  return result;
-}
-#endif
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ                             __clz
-
-
-#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
-#else
-  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
-#else
-  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
-#else
-  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
-#else
-  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
-#else
-  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
-  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
-#else
-  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
-#endif
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX                           __clrex
-
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT                            __ssat
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT                            __usat
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
-{
-  rrx r0, r0
-  bx lr
-}
-#endif
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRBT(value, ptr)               __strt(value, ptr)
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRHT(value, ptr)               __strt(value, ptr)
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-#define __STRT(value, ptr)                __strt(value, ptr)
-
-#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
-{
-  if ((sat >= 1U) && (sat <= 32U))
-  {
-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
-    const int32_t min = -1 - max ;
-    if (val > max)
-    {
-      return max;
-    }
-    else if (val < min)
-    {
-      return min;
-    }
-  }
-  return val;
-}
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
-{
-  if (sat <= 31U)
-  {
-    const uint32_t max = ((1U << sat) - 1U);
-    if (val > (int32_t)max)
-    {
-      return max;
-    }
-    else if (val < 0)
-    {
-      return 0U;
-    }
-  }
-  return (uint32_t)val;
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
-           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
-
-#define __SADD8                           __sadd8
-#define __QADD8                           __qadd8
-#define __SHADD8                          __shadd8
-#define __UADD8                           __uadd8
-#define __UQADD8                          __uqadd8
-#define __UHADD8                          __uhadd8
-#define __SSUB8                           __ssub8
-#define __QSUB8                           __qsub8
-#define __SHSUB8                          __shsub8
-#define __USUB8                           __usub8
-#define __UQSUB8                          __uqsub8
-#define __UHSUB8                          __uhsub8
-#define __SADD16                          __sadd16
-#define __QADD16                          __qadd16
-#define __SHADD16                         __shadd16
-#define __UADD16                          __uadd16
-#define __UQADD16                         __uqadd16
-#define __UHADD16                         __uhadd16
-#define __SSUB16                          __ssub16
-#define __QSUB16                          __qsub16
-#define __SHSUB16                         __shsub16
-#define __USUB16                          __usub16
-#define __UQSUB16                         __uqsub16
-#define __UHSUB16                         __uhsub16
-#define __SASX                            __sasx
-#define __QASX                            __qasx
-#define __SHASX                           __shasx
-#define __UASX                            __uasx
-#define __UQASX                           __uqasx
-#define __UHASX                           __uhasx
-#define __SSAX                            __ssax
-#define __QSAX                            __qsax
-#define __SHSAX                           __shsax
-#define __USAX                            __usax
-#define __UQSAX                           __uqsax
-#define __UHSAX                           __uhsax
-#define __USAD8                           __usad8
-#define __USADA8                          __usada8
-#define __SSAT16                          __ssat16
-#define __USAT16                          __usat16
-#define __UXTB16                          __uxtb16
-#define __UXTAB16                         __uxtab16
-#define __SXTB16                          __sxtb16
-#define __SXTAB16                         __sxtab16
-#define __SMUAD                           __smuad
-#define __SMUADX                          __smuadx
-#define __SMLAD                           __smlad
-#define __SMLADX                          __smladx
-#define __SMLALD                          __smlald
-#define __SMLALDX                         __smlaldx
-#define __SMUSD                           __smusd
-#define __SMUSDX                          __smusdx
-#define __SMLSD                           __smlsd
-#define __SMLSDX                          __smlsdx
-#define __SMLSLD                          __smlsld
-#define __SMLSLDX                         __smlsldx
-#define __SEL                             __sel
-#define __QADD                            __qadd
-#define __QSUB                            __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
-                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
-
-#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCC_H */
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */
diff --git a/Drivers/CMSIS/Include/cmsis_armclang.h b/Drivers/CMSIS/Include/cmsis_armclang.h
index 162a400..d8031b0 100644
--- a/Drivers/CMSIS/Include/cmsis_armclang.h
+++ b/Drivers/CMSIS/Include/cmsis_armclang.h
@@ -1,1869 +1,1869 @@
-/**************************************************************************//**
- * @file     cmsis_armclang.h
- * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
- * @version  V5.0.4
- * @date     10. January 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
-
-#ifndef __CMSIS_ARMCLANG_H
-#define __CMSIS_ARMCLANG_H
-
-#pragma clang system_header   /* treat file as system include file */
-
-#ifndef __ARM_COMPAT_H
-#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-  #define __ASM                                  __asm
-#endif
-#ifndef   __INLINE
-  #define __INLINE                               __inline
-#endif
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE                        static __inline
-#endif
-#ifndef   __STATIC_FORCEINLINE                 
-  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
-#endif                                           
-#ifndef   __NO_RETURN
-  #define __NO_RETURN                            __attribute__((__noreturn__))
-#endif
-#ifndef   __USED
-  #define __USED                                 __attribute__((used))
-#endif
-#ifndef   __WEAK
-  #define __WEAK                                 __attribute__((weak))
-#endif
-#ifndef   __PACKED
-  #define __PACKED                               __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_STRUCT
-  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_UNION
-  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __UNALIGNED_UINT32        /* deprecated */
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
-  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __UNALIGNED_UINT16_WRITE
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
-  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT16_READ
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
-  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __UNALIGNED_UINT32_WRITE
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
-  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT32_READ
-  #pragma clang diagnostic push
-  #pragma clang diagnostic ignored "-Wpacked"
-/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
-  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-  #pragma clang diagnostic pop
-  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __ALIGNED
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))
-#endif
-#ifndef   __RESTRICT
-  #define __RESTRICT                             __restrict
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __enable_irq();  see arm_compat.h */
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-/* intrinsic void __disable_irq();  see arm_compat.h */
-
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Control Register (non-secure)
-  \details Returns the content of the non-secure Control Register when in secure mode.
-  \return               non-secure Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Control Register (non-secure)
-  \details Writes the given value to the non-secure Control Register when in secure state.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
-  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
-  \return               PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, msp" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Main Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
-  \return               MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Main Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
-  \return               SP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Set Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
-  \param [in]    topOfStack  Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
-{
-  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Priority Mask (non-secure)
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
-  \return               Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Priority Mask (non-secure)
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Base Priority (non-secure)
-  \details Returns the current value of the non-secure Base Priority register when in secure state.
-  \return               Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Base Priority (non-secure)
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Fault Mask (non-secure)
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.
-  \return               Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Fault Mask (non-secure)
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-/**
-  \brief   Get Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always in non-secure
-  mode.
-  
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
-  \return               PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure PSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-  return result;
-#endif
-}
-
-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always in non-secure
-  mode.
-
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \return               PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-  return result;
-#endif
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored in non-secure
-  mode.
-  
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  (void)ProcStackPtrLimit;
-#else
-  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored in non-secure
-  mode.
-
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  (void)ProcStackPtrLimit;
-#else
-  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-#endif
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always.
-
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
-  \return               MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-  return result;
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Get Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always.
-
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
-  \return               MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-  return result;
-#endif
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored.
-
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  (void)MainStackPtrLimit;
-#else
-  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Set Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored.
-
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  (void)MainStackPtrLimit;
-#else
-  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
-#else
-#define __get_FPSCR()      ((uint32_t)0U)
-#endif
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#define __set_FPSCR      __builtin_arm_set_fpscr
-#else
-#define __set_FPSCR(x)      ((void)(x))
-#endif
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP          __builtin_arm_nop
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI          __builtin_arm_wfi
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE          __builtin_arm_wfe
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV          __builtin_arm_sev
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-#define __ISB()        __builtin_arm_isb(0xF);
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB()        __builtin_arm_dsb(0xF);
-
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-#define __DMB()        __builtin_arm_dmb(0xF);
-
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV(value)   __builtin_bswap32(value)
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REV16(value) __ROR(__REV(value), 16)
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __REVSH(value) (int16_t)__builtin_bswap16(value)
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  op2 %= 32U;
-  if (op2 == 0U)
-  {
-    return op1;
-  }
-  return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)     __ASM volatile ("bkpt "#value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-#define __RBIT            __builtin_arm_rbit
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ             (uint8_t)__builtin_clz
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define __LDREXB        (uint8_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define __LDREXH        (uint16_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define __LDREXW        (uint32_t)__builtin_arm_ldrex
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXB        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXH        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define __STREXW        (uint32_t)__builtin_arm_strex
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-#define __CLREX             __builtin_arm_clrex
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT             __builtin_arm_ssat
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT             __builtin_arm_usat
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return(result);
-}
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
-  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
-  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
-  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
-{
-  if ((sat >= 1U) && (sat <= 32U))
-  {
-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
-    const int32_t min = -1 - max ;
-    if (val > max)
-    {
-      return max;
-    }
-    else if (val < min)
-    {
-      return min;
-    }
-  }
-  return val;
-}
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
-{
-  if (sat <= 31U)
-  {
-    const uint32_t max = ((1U << sat) - 1U);
-    if (val > (int32_t)max)
-    {
-      return max;
-    }
-    else if (val < 0)
-    {
-      return 0U;
-    }
-  }
-  return (uint32_t)val;
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   Load-Acquire (8 bit)
-  \details Executes a LDAB instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (16 bit)
-  \details Executes a LDAH instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (32 bit)
-  \details Executes a LDA instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
-  uint32_t result;
-
-  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
-  return(result);
-}
-
-
-/**
-  \brief   Store-Release (8 bit)
-  \details Executes a STLB instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
-  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (16 bit)
-  \details Executes a STLH instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
-  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (32 bit)
-  \details Executes a STL instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
-  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (8 bit)
-  \details Executes a LDAB exclusive instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Load-Acquire Exclusive (16 bit)
-  \details Executes a LDAH exclusive instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Load-Acquire Exclusive (32 bit)
-  \details Executes a LDA exclusive instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
-
-
-/**
-  \brief   Store-Release Exclusive (8 bit)
-  \details Executes a STLB exclusive instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
-
-
-/**
-  \brief   Store-Release Exclusive (16 bit)
-  \details Executes a STLH exclusive instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
-
-
-/**
-  \brief   Store-Release Exclusive (32 bit)
-  \details Executes a STL exclusive instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-#define     __STLEX                  (uint32_t)__builtin_arm_stlex
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
-
-__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  int32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
-  int32_t result;
-
-  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CMSIS_ARMCLANG_H */
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF);
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF);
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF);
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */
diff --git a/Drivers/CMSIS/Include/cmsis_compiler.h b/Drivers/CMSIS/Include/cmsis_compiler.h
index 94212eb..79a2cac 100644
--- a/Drivers/CMSIS/Include/cmsis_compiler.h
+++ b/Drivers/CMSIS/Include/cmsis_compiler.h
@@ -1,266 +1,266 @@
-/**************************************************************************//**
- * @file     cmsis_compiler.h
- * @brief    CMSIS compiler generic header file
- * @version  V5.0.4
- * @date     10. January 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_COMPILER_H
-#define __CMSIS_COMPILER_H
-
-#include <stdint.h>
-
-/*
- * Arm Compiler 4/5
- */
-#if   defined ( __CC_ARM )
-  #include "cmsis_armcc.h"
-
-
-/*
- * Arm Compiler 6 (armclang)
- */
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #include "cmsis_armclang.h"
-
-
-/*
- * GNU Compiler
- */
-#elif defined ( __GNUC__ )
-  #include "cmsis_gcc.h"
-
-
-/*
- * IAR Compiler
- */
-#elif defined ( __ICCARM__ )
-  #include <cmsis_iccarm.h>
-
-
-/*
- * TI Arm Compiler
- */
-#elif defined ( __TI_ARM__ )
-  #include <cmsis_ccs.h>
-
-  #ifndef   __ASM
-    #define __ASM                                  __asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __STATIC_FORCEINLINE
-    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-  #endif
-  #ifndef   __NO_RETURN
-    #define __NO_RETURN                            __attribute__((noreturn))
-  #endif
-  #ifndef   __USED
-    #define __USED                                 __attribute__((used))
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                                 __attribute__((weak))
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                               __attribute__((packed))
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT                        struct __attribute__((packed))
-  #endif
-  #ifndef   __PACKED_UNION
-    #define __PACKED_UNION                         union __attribute__((packed))
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #define __ALIGNED(x)                           __attribute__((aligned(x)))
-  #endif
-  #ifndef   __RESTRICT
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
-    #define __RESTRICT
-  #endif
-
-
-/*
- * TASKING Compiler
- */
-#elif defined ( __TASKING__ )
-  /*
-   * The CMSIS functions have been implemented as intrinsics in the compiler.
-   * Please use "carm -?i" to get an up to date list of all intrinsics,
-   * Including the CMSIS ones.
-   */
-
-  #ifndef   __ASM
-    #define __ASM                                  __asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __STATIC_FORCEINLINE
-    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-  #endif
-  #ifndef   __NO_RETURN
-    #define __NO_RETURN                            __attribute__((noreturn))
-  #endif
-  #ifndef   __USED
-    #define __USED                                 __attribute__((used))
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                                 __attribute__((weak))
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                               __packed__
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT                        struct __packed__
-  #endif
-  #ifndef   __PACKED_UNION
-    #define __PACKED_UNION                         union __packed__
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    struct __packed__ T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #define __ALIGNED(x)              __align(x)
-  #endif
-  #ifndef   __RESTRICT
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
-    #define __RESTRICT
-  #endif
-
-
-/*
- * COSMIC Compiler
- */
-#elif defined ( __CSMC__ )
-   #include <cmsis_csm.h>
-
- #ifndef   __ASM
-    #define __ASM                                  _asm
-  #endif
-  #ifndef   __INLINE
-    #define __INLINE                               inline
-  #endif
-  #ifndef   __STATIC_INLINE
-    #define __STATIC_INLINE                        static inline
-  #endif
-  #ifndef   __STATIC_FORCEINLINE
-    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
-  #endif
-  #ifndef   __NO_RETURN
-    // NO RETURN is automatically detected hence no warning here
-    #define __NO_RETURN
-  #endif
-  #ifndef   __USED
-    #warning No compiler specific solution for __USED. __USED is ignored.
-    #define __USED
-  #endif
-  #ifndef   __WEAK
-    #define __WEAK                                 __weak
-  #endif
-  #ifndef   __PACKED
-    #define __PACKED                               @packed
-  #endif
-  #ifndef   __PACKED_STRUCT
-    #define __PACKED_STRUCT                        @packed struct
-  #endif
-  #ifndef   __PACKED_UNION
-    #define __PACKED_UNION                         @packed union
-  #endif
-  #ifndef   __UNALIGNED_UINT32        /* deprecated */
-    @packed struct T_UINT32 { uint32_t v; };
-    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT16_WRITE
-    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT16_READ
-    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __UNALIGNED_UINT32_WRITE
-    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-  #endif
-  #ifndef   __UNALIGNED_UINT32_READ
-    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-  #endif
-  #ifndef   __ALIGNED
-    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
-    #define __ALIGNED(x)
-  #endif
-  #ifndef   __RESTRICT
-    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
-    #define __RESTRICT
-  #endif
-
-
-#else
-  #error Unknown compiler.
-#endif
-
-
-#endif /* __CMSIS_COMPILER_H */
-
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+
diff --git a/Drivers/CMSIS/Include/cmsis_gcc.h b/Drivers/CMSIS/Include/cmsis_gcc.h
index 2d9db15..1bd41a4 100644
--- a/Drivers/CMSIS/Include/cmsis_gcc.h
+++ b/Drivers/CMSIS/Include/cmsis_gcc.h
@@ -1,2085 +1,2085 @@
-/**************************************************************************//**
- * @file     cmsis_gcc.h
- * @brief    CMSIS compiler GCC header file
- * @version  V5.0.4
- * @date     09. April 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef __CMSIS_GCC_H
-#define __CMSIS_GCC_H
-
-/* ignore some GCC warnings */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wsign-conversion"
-#pragma GCC diagnostic ignored "-Wconversion"
-#pragma GCC diagnostic ignored "-Wunused-parameter"
-
-/* Fallback for __has_builtin */
-#ifndef __has_builtin
-  #define __has_builtin(x) (0)
-#endif
-
-/* CMSIS compiler specific defines */
-#ifndef   __ASM
-  #define __ASM                                  __asm
-#endif
-#ifndef   __INLINE
-  #define __INLINE                               inline
-#endif
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE                        static inline
-#endif
-#ifndef   __STATIC_FORCEINLINE                 
-  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
-#endif                                           
-#ifndef   __NO_RETURN
-  #define __NO_RETURN                            __attribute__((__noreturn__))
-#endif
-#ifndef   __USED
-  #define __USED                                 __attribute__((used))
-#endif
-#ifndef   __WEAK
-  #define __WEAK                                 __attribute__((weak))
-#endif
-#ifndef   __PACKED
-  #define __PACKED                               __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_STRUCT
-  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __PACKED_UNION
-  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
-#endif
-#ifndef   __UNALIGNED_UINT32        /* deprecated */
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
-#endif
-#ifndef   __UNALIGNED_UINT16_WRITE
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT16_READ
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __UNALIGNED_UINT32_WRITE
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
-#endif
-#ifndef   __UNALIGNED_UINT32_READ
-  #pragma GCC diagnostic push
-  #pragma GCC diagnostic ignored "-Wpacked"
-  #pragma GCC diagnostic ignored "-Wattributes"
-  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
-  #pragma GCC diagnostic pop
-  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
-#endif
-#ifndef   __ALIGNED
-  #define __ALIGNED(x)                           __attribute__((aligned(x)))
-#endif
-#ifndef   __RESTRICT
-  #define __RESTRICT                             __restrict
-#endif
-
-
-/* ###########################  Core Function Access  ########################### */
-/** \ingroup  CMSIS_Core_FunctionInterface
-    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
-  @{
- */
-
-/**
-  \brief   Enable IRQ Interrupts
-  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __enable_irq(void)
-{
-  __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/**
-  \brief   Disable IRQ Interrupts
-  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __disable_irq(void)
-{
-  __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/**
-  \brief   Get Control Register
-  \details Returns the content of the Control Register.
-  \return               Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Control Register (non-secure)
-  \details Returns the content of the non-secure Control Register when in secure mode.
-  \return               non-secure Control Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Control Register
-  \details Writes the given value to the Control Register.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
-{
-  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Control Register (non-secure)
-  \details Writes the given value to the non-secure Control Register when in secure state.
-  \param [in]    control  Control Register value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
-{
-  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Get IPSR Register
-  \details Returns the content of the IPSR Register.
-  \return               IPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get APSR Register
-  \details Returns the content of the APSR Register.
-  \return               APSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_APSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get xPSR Register
-  \details Returns the content of the xPSR Register.
-  \return               xPSR Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Get Process Stack Pointer
-  \details Returns the current value of the Process Stack Pointer (PSP).
-  \return               PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
-  \return               PSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer
-  \details Assigns the given value to the Process Stack Pointer (PSP).
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
-  \param [in]    topOfProcStack  Process Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
-{
-  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer
-  \details Returns the current value of the Main Stack Pointer (MSP).
-  \return               MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSP(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, msp" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Main Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
-  \return               MSP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer
-  \details Assigns the given value to the Main Stack Pointer (MSP).
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Main Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
-  \param [in]    topOfMainStack  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
-{
-  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
-}
-#endif
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Stack Pointer (non-secure)
-  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
-  \return               SP Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
-  return(result);
-}
-
-
-/**
-  \brief   Set Stack Pointer (non-secure)
-  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
-  \param [in]    topOfStack  Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
-{
-  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
-}
-#endif
-
-
-/**
-  \brief   Get Priority Mask
-  \details Returns the current state of the priority mask bit from the Priority Mask Register.
-  \return               Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Priority Mask (non-secure)
-  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
-  \return               Priority Mask value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Priority Mask
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Priority Mask (non-secure)
-  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
-}
-#endif
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __enable_fault_irq(void)
-{
-  __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
-           Can only be executed in Privileged modes.
- */
-__STATIC_FORCEINLINE void __disable_fault_irq(void)
-{
-  __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/**
-  \brief   Get Base Priority
-  \details Returns the current value of the Base Priority register.
-  \return               Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Base Priority (non-secure)
-  \details Returns the current value of the non-secure Base Priority register when in secure state.
-  \return               Base Priority register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority
-  \details Assigns the given value to the Base Priority register.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Base Priority (non-secure)
-  \details Assigns the given value to the non-secure Base Priority register when in secure state.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
-}
-#endif
-
-
-/**
-  \brief   Set Base Priority with condition
-  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
-           or the new value increases the BASEPRI priority level.
-  \param [in]    basePri  Base Priority value to set
- */
-__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
-{
-  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
-}
-
-
-/**
-  \brief   Get Fault Mask
-  \details Returns the current value of the Fault Mask register.
-  \return               Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
-  return(result);
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Fault Mask (non-secure)
-  \details Returns the current value of the non-secure Fault Mask register when in secure state.
-  \return               Fault Mask register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
-  return(result);
-}
-#endif
-
-
-/**
-  \brief   Set Fault Mask
-  \details Assigns the given value to the Fault Mask register.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Set Fault Mask (non-secure)
-  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
-  \param [in]    faultMask  Fault Mask value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
-{
-  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-/**
-  \brief   Get Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always in non-secure
-  mode.
-  
-  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
-  \return               PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure PSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
-  return result;
-#endif
-}
-
-#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
-/**
-  \brief   Get Process Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always.
-
-  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \return               PSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
-  return result;
-#endif
-}
-#endif
-
-
-/**
-  \brief   Set Process Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored in non-secure
-  mode.
-  
-  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  (void)ProcStackPtrLimit;
-#else
-  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Set Process Stack Pointer (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored.
-
-  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
-  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure PSPLIM is RAZ/WI
-  (void)ProcStackPtrLimit;
-#else
-  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
-#endif
-}
-#endif
-
-
-/**
-  \brief   Get Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always in non-secure
-  mode.
-
-  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
-  \return               MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
-  return result;
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Get Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence zero is returned always.
-
-  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
-  \return               MSPLIM Register value
- */
-__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  return 0U;
-#else
-  uint32_t result;
-  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
-  return result;
-#endif
-}
-#endif
-
-
-/**
-  \brief   Set Main Stack Pointer Limit
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored in non-secure
-  mode.
-
-  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
-  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
- */
-__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  (void)MainStackPtrLimit;
-#else
-  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-
-
-#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
-/**
-  \brief   Set Main Stack Pointer Limit (non-secure)
-  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
-  Stack Pointer Limit register hence the write is silently ignored.
-
-  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
-  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
- */
-__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
-{
-#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
-  // without main extensions, the non-secure MSPLIM is RAZ/WI
-  (void)MainStackPtrLimit;
-#else
-  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
-#endif
-}
-#endif
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-/**
-  \brief   Get FPSCR
-  \details Returns the current value of the Floating Point Status/Control register.
-  \return               Floating Point Status/Control register value
- */
-__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#if __has_builtin(__builtin_arm_get_fpscr) 
-// Re-enable using built-in when GCC has been fixed
-// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
-  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
-  return __builtin_arm_get_fpscr();
-#else
-  uint32_t result;
-
-  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
-  return(result);
-#endif
-#else
-  return(0U);
-#endif
-}
-
-
-/**
-  \brief   Set FPSCR
-  \details Assigns the given value to the Floating Point Status/Control register.
-  \param [in]    fpscr  Floating Point Status/Control value to set
- */
-__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-#if __has_builtin(__builtin_arm_set_fpscr)
-// Re-enable using built-in when GCC has been fixed
-// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
-  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
-  __builtin_arm_set_fpscr(fpscr);
-#else
-  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
-#endif
-#else
-  (void)fpscr;
-#endif
-}
-
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-/* ##########################  Core Instruction Access  ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
-  Access to dedicated instructions
-  @{
-*/
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constraint "l"
- * Otherwise, use general registers, specified by constraint "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_RW_REG(r) "+l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_RW_REG(r) "+r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/**
-  \brief   No Operation
-  \details No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP()                             __ASM volatile ("nop")
-
-/**
-  \brief   Wait For Interrupt
-  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
- */
-#define __WFI()                             __ASM volatile ("wfi")
-
-
-/**
-  \brief   Wait For Event
-  \details Wait For Event is a hint instruction that permits the processor to enter
-           a low-power state until one of a number of events occurs.
- */
-#define __WFE()                             __ASM volatile ("wfe")
-
-
-/**
-  \brief   Send Event
-  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV()                             __ASM volatile ("sev")
-
-
-/**
-  \brief   Instruction Synchronization Barrier
-  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
-           so that all instructions following the ISB are fetched from cache or memory,
-           after the instruction has been completed.
- */
-__STATIC_FORCEINLINE void __ISB(void)
-{
-  __ASM volatile ("isb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-__STATIC_FORCEINLINE void __DSB(void)
-{
-  __ASM volatile ("dsb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-__STATIC_FORCEINLINE void __DMB(void)
-{
-  __ASM volatile ("dmb 0xF":::"memory");
-}
-
-
-/**
-  \brief   Reverse byte order (32 bit)
-  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
-  return __builtin_bswap32(value);
-#else
-  uint32_t result;
-
-  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return result;
-#endif
-}
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return result;
-}
-
-
-/**
-  \brief   Reverse byte order (16 bit)
-  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-  return (int16_t)__builtin_bswap16(value);
-#else
-  int16_t result;
-
-  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return result;
-#endif
-}
-
-
-/**
-  \brief   Rotate Right in unsigned value (32 bit)
-  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-  \param [in]    op1  Value to rotate
-  \param [in]    op2  Number of Bits to rotate
-  \return               Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
-  op2 %= 32U;
-  if (op2 == 0U)
-  {
-    return op1;
-  }
-  return (op1 >> op2) | (op1 << (32U - op2));
-}
-
-
-/**
-  \brief   Breakpoint
-  \details Causes the processor to enter Debug state.
-           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-  \param [in]    value  is ignored by the processor.
-                 If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
-
-
-/**
-  \brief   Reverse bit order of value
-  \details Reverses the bit order of the given value.
-  \param [in]    value  Value to reverse
-  \return               Reversed value
- */
-__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
-{
-  uint32_t result;
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
-#else
-  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
-
-  result = value;                      /* r will be reversed bits of v; first get LSB of v */
-  for (value >>= 1U; value != 0U; value >>= 1U)
-  {
-    result <<= 1U;
-    result |= value & 1U;
-    s--;
-  }
-  result <<= s;                        /* shift when v's highest bits are zero */
-#endif
-  return result;
-}
-
-
-/**
-  \brief   Count leading zeros
-  \details Counts the number of leading zeros of a data value.
-  \param [in]  value  Value to count the leading zeros
-  \return             number of leading zeros in value
- */
-#define __CLZ             (uint8_t)__builtin_clz
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   LDR Exclusive (8 bit)
-  \details Executes a exclusive LDR instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDR Exclusive (16 bit)
-  \details Executes a exclusive LDR instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDR Exclusive (32 bit)
-  \details Executes a exclusive LDR instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (8 bit)
-  \details Executes a exclusive STR instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (16 bit)
-  \details Executes a exclusive STR instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   STR Exclusive (32 bit)
-  \details Executes a exclusive STR instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
-   uint32_t result;
-
-   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
-   return(result);
-}
-
-
-/**
-  \brief   Remove the exclusive lock
-  \details Removes the exclusive lock which is created by LDREX.
- */
-__STATIC_FORCEINLINE void __CLREX(void)
-{
-  __ASM volatile ("clrex" ::: "memory");
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  ARG1  Value to be saturated
-  \param [in]  ARG2  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-__extension__ \
-({                          \
-  int32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  ARG1  Value to be saturated
-  \param [in]  ARG2  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-#define __USAT(ARG1,ARG2) \
- __extension__ \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-
-/**
-  \brief   Rotate Right with Extend (32 bit)
-  \details Moves each bit of a bitstring right by one bit.
-           The carry input is shifted in at the left end of the bitstring.
-  \param [in]    value  Value to rotate
-  \return               Rotated value
- */
-__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
-{
-  uint32_t result;
-
-  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
-  return(result);
-}
-
-
-/**
-  \brief   LDRT Unprivileged (8 bit)
-  \details Executes a Unprivileged LDRT instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
-   return ((uint8_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (16 bit)
-  \details Executes a Unprivileged LDRT instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
-   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
-#else
-    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
-       accepted by assembler. So has to use following less efficient pattern.
-    */
-   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
-#endif
-   return ((uint16_t) result);    /* Add explicit type cast here */
-}
-
-
-/**
-  \brief   LDRT Unprivileged (32 bit)
-  \details Executes a Unprivileged LDRT instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return(result);
-}
-
-
-/**
-  \brief   STRT Unprivileged (8 bit)
-  \details Executes a Unprivileged STRT instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
-{
-   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (16 bit)
-  \details Executes a Unprivileged STRT instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
-{
-   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   STRT Unprivileged (32 bit)
-  \details Executes a Unprivileged STRT instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
-{
-   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
-}
-
-#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-/**
-  \brief   Signed Saturate
-  \details Saturates a signed value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (1..32)
-  \return             Saturated value
- */
-__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
-{
-  if ((sat >= 1U) && (sat <= 32U))
-  {
-    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
-    const int32_t min = -1 - max ;
-    if (val > max)
-    {
-      return max;
-    }
-    else if (val < min)
-    {
-      return min;
-    }
-  }
-  return val;
-}
-
-/**
-  \brief   Unsigned Saturate
-  \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
- */
-__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
-{
-  if (sat <= 31U)
-  {
-    const uint32_t max = ((1U << sat) - 1U);
-    if (val > (int32_t)max)
-    {
-      return max;
-    }
-    else if (val < 0)
-    {
-      return 0U;
-    }
-  }
-  return (uint32_t)val;
-}
-
-#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
-           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
-           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
-
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-/**
-  \brief   Load-Acquire (8 bit)
-  \details Executes a LDAB instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (16 bit)
-  \details Executes a LDAH instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire (32 bit)
-  \details Executes a LDA instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release (8 bit)
-  \details Executes a STLB instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
-{
-   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (16 bit)
-  \details Executes a STLH instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
-{
-   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Store-Release (32 bit)
-  \details Executes a STL instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
- */
-__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
-{
-   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (8 bit)
-  \details Executes a LDAB exclusive instruction for 8 bit value.
-  \param [in]    ptr  Pointer to data
-  \return             value of type uint8_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint8_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (16 bit)
-  \details Executes a LDAH exclusive instruction for 16 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint16_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return ((uint16_t) result);
-}
-
-
-/**
-  \brief   Load-Acquire Exclusive (32 bit)
-  \details Executes a LDA exclusive instruction for 32 bit values.
-  \param [in]    ptr  Pointer to data
-  \return        value of type uint32_t at (*ptr)
- */
-__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
-{
-    uint32_t result;
-
-   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (8 bit)
-  \details Executes a STLB exclusive instruction for 8 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (16 bit)
-  \details Executes a STLH exclusive instruction for 16 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-
-/**
-  \brief   Store-Release Exclusive (32 bit)
-  \details Executes a STL exclusive instruction for 32 bit values.
-  \param [in]  value  Value to store
-  \param [in]    ptr  Pointer to location
-  \return          0  Function succeeded
-  \return          1  Function failed
- */
-__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
-{
-   uint32_t result;
-
-   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
-   return(result);
-}
-
-#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-
-/* ###################  Compiler specific Intrinsics  ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
-  Access to dedicated SIMD instructions
-  @{
-*/
-
-#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
-
-__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-
-__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({                          \
-  int32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1); \
-  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
-  __RES; \
- })
-
-__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
-  uint32_t result;
-
-  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
-{
-  union llreg_u{
-    uint32_t w32[2];
-    uint64_t w64;
-  } llr;
-  llr.w64 = acc;
-
-#ifndef __ARMEB__   /* Little endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
-#else               /* Big endian */
-  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
-#endif
-
-  return(llr.w64);
-}
-
-__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
-{
-  uint32_t result;
-
-  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
-{
-  int32_t result;
-
-  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
-  return(result);
-}
-
-#if 0
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({                          \
-  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
-  if (ARG3 == 0) \
-    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
-  else \
-    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
-  __RES; \
- })
-#endif
-
-#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
-                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
-
-#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
-                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
-
-__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#endif /* (__ARM_FEATURE_DSP == 1) */
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#pragma GCC diagnostic pop
-
-#endif /* __CMSIS_GCC_H */
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.4
+ * @date     09. April 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) 
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             (uint8_t)__builtin_clz
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */
diff --git a/Drivers/CMSIS/Include/cmsis_iccarm.h b/Drivers/CMSIS/Include/cmsis_iccarm.h
index 11c4af0..3c90a2c 100644
--- a/Drivers/CMSIS/Include/cmsis_iccarm.h
+++ b/Drivers/CMSIS/Include/cmsis_iccarm.h
@@ -1,935 +1,935 @@
-/**************************************************************************//**
- * @file     cmsis_iccarm.h
- * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
- * @version  V5.0.7
- * @date     19. June 2018
- ******************************************************************************/
-
-//------------------------------------------------------------------------------
-//
-// Copyright (c) 2017-2018 IAR Systems
-//
-// Licensed under the Apache License, Version 2.0 (the "License")
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-//
-//------------------------------------------------------------------------------
-
-
-#ifndef __CMSIS_ICCARM_H__
-#define __CMSIS_ICCARM_H__
-
-#ifndef __ICCARM__
-  #error This file should only be compiled by ICCARM
-#endif
-
-#pragma system_include
-
-#define __IAR_FT _Pragma("inline=forced") __intrinsic
-
-#if (__VER__ >= 8000000)
-  #define __ICCARM_V8 1
-#else
-  #define __ICCARM_V8 0
-#endif
-
-#ifndef __ALIGNED
-  #if __ICCARM_V8
-    #define __ALIGNED(x) __attribute__((aligned(x)))
-  #elif (__VER__ >= 7080000)
-    /* Needs IAR language extensions */
-    #define __ALIGNED(x) __attribute__((aligned(x)))
-  #else
-    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
-    #define __ALIGNED(x)
-  #endif
-#endif
-
-
-/* Define compiler macros for CPU architecture, used in CMSIS 5.
- */
-#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
-/* Macros already defined */
-#else
-  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
-    #define __ARM_ARCH_8M_MAIN__ 1
-  #elif defined(__ARM8M_BASELINE__)
-    #define __ARM_ARCH_8M_BASE__ 1
-  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
-    #if __ARM_ARCH == 6
-      #define __ARM_ARCH_6M__ 1
-    #elif __ARM_ARCH == 7
-      #if __ARM_FEATURE_DSP
-        #define __ARM_ARCH_7EM__ 1
-      #else
-        #define __ARM_ARCH_7M__ 1
-      #endif
-    #endif /* __ARM_ARCH */
-  #endif /* __ARM_ARCH_PROFILE == 'M' */
-#endif
-
-/* Alternativ core deduction for older ICCARM's */
-#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
-    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
-  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
-    #define __ARM_ARCH_6M__ 1
-  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
-    #define __ARM_ARCH_7M__ 1
-  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
-    #define __ARM_ARCH_7EM__  1
-  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
-    #define __ARM_ARCH_8M_BASE__ 1
-  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
-    #define __ARM_ARCH_8M_MAIN__ 1
-  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
-    #define __ARM_ARCH_8M_MAIN__ 1
-  #else
-    #error "Unknown target."
-  #endif
-#endif
-
-
-
-#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
-  #define __IAR_M0_FAMILY  1
-#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
-  #define __IAR_M0_FAMILY  1
-#else
-  #define __IAR_M0_FAMILY  0
-#endif
-
-
-#ifndef __ASM
-  #define __ASM __asm
-#endif
-
-#ifndef __INLINE
-  #define __INLINE inline
-#endif
-
-#ifndef   __NO_RETURN
-  #if __ICCARM_V8
-    #define __NO_RETURN __attribute__((__noreturn__))
-  #else
-    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
-  #endif
-#endif
-
-#ifndef   __PACKED
-  #if __ICCARM_V8
-    #define __PACKED __attribute__((packed, aligned(1)))
-  #else
-    /* Needs IAR language extensions */
-    #define __PACKED __packed
-  #endif
-#endif
-
-#ifndef   __PACKED_STRUCT
-  #if __ICCARM_V8
-    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
-  #else
-    /* Needs IAR language extensions */
-    #define __PACKED_STRUCT __packed struct
-  #endif
-#endif
-
-#ifndef   __PACKED_UNION
-  #if __ICCARM_V8
-    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
-  #else
-    /* Needs IAR language extensions */
-    #define __PACKED_UNION __packed union
-  #endif
-#endif
-
-#ifndef   __RESTRICT
-  #define __RESTRICT            __restrict
-#endif
-
-#ifndef   __STATIC_INLINE
-  #define __STATIC_INLINE       static inline
-#endif
-
-#ifndef   __FORCEINLINE
-  #define __FORCEINLINE         _Pragma("inline=forced")
-#endif
-
-#ifndef   __STATIC_FORCEINLINE
-  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
-#endif
-
-#ifndef __UNALIGNED_UINT16_READ
-#pragma language=save
-#pragma language=extended
-__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
-{
-  return *(__packed uint16_t*)(ptr);
-}
-#pragma language=restore
-#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
-#endif
-
-
-#ifndef __UNALIGNED_UINT16_WRITE
-#pragma language=save
-#pragma language=extended
-__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
-{
-  *(__packed uint16_t*)(ptr) = val;;
-}
-#pragma language=restore
-#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
-#endif
-
-#ifndef __UNALIGNED_UINT32_READ
-#pragma language=save
-#pragma language=extended
-__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
-{
-  return *(__packed uint32_t*)(ptr);
-}
-#pragma language=restore
-#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
-#endif
-
-#ifndef __UNALIGNED_UINT32_WRITE
-#pragma language=save
-#pragma language=extended
-__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
-{
-  *(__packed uint32_t*)(ptr) = val;;
-}
-#pragma language=restore
-#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
-#endif
-
-#ifndef __UNALIGNED_UINT32   /* deprecated */
-#pragma language=save
-#pragma language=extended
-__packed struct  __iar_u32 { uint32_t v; };
-#pragma language=restore
-#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
-#endif
-
-#ifndef   __USED
-  #if __ICCARM_V8
-    #define __USED __attribute__((used))
-  #else
-    #define __USED _Pragma("__root")
-  #endif
-#endif
-
-#ifndef   __WEAK
-  #if __ICCARM_V8
-    #define __WEAK __attribute__((weak))
-  #else
-    #define __WEAK _Pragma("__weak")
-  #endif
-#endif
-
-
-#ifndef __ICCARM_INTRINSICS_VERSION__
-  #define __ICCARM_INTRINSICS_VERSION__  0
-#endif
-
-#if __ICCARM_INTRINSICS_VERSION__ == 2
-
-  #if defined(__CLZ)
-    #undef __CLZ
-  #endif
-  #if defined(__REVSH)
-    #undef __REVSH
-  #endif
-  #if defined(__RBIT)
-    #undef __RBIT
-  #endif
-  #if defined(__SSAT)
-    #undef __SSAT
-  #endif
-  #if defined(__USAT)
-    #undef __USAT
-  #endif
-
-  #include "iccarm_builtin.h"
-
-  #define __disable_fault_irq __iar_builtin_disable_fiq
-  #define __disable_irq       __iar_builtin_disable_interrupt
-  #define __enable_fault_irq  __iar_builtin_enable_fiq
-  #define __enable_irq        __iar_builtin_enable_interrupt
-  #define __arm_rsr           __iar_builtin_rsr
-  #define __arm_wsr           __iar_builtin_wsr
-
-
-  #define __get_APSR()                (__arm_rsr("APSR"))
-  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
-  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
-  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
-
-  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
-    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
-    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
-  #else
-    #define __get_FPSCR()             ( 0 )
-    #define __set_FPSCR(VALUE)        ((void)VALUE)
-  #endif
-
-  #define __get_IPSR()                (__arm_rsr("IPSR"))
-  #define __get_MSP()                 (__arm_rsr("MSP"))
-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure MSPLIM is RAZ/WI
-    #define __get_MSPLIM()            (0U)
-  #else
-    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
-  #endif
-  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
-  #define __get_PSP()                 (__arm_rsr("PSP"))
-
-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure PSPLIM is RAZ/WI
-    #define __get_PSPLIM()            (0U)
-  #else
-    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
-  #endif
-
-  #define __get_xPSR()                (__arm_rsr("xPSR"))
-
-  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
-  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
-  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
-  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
-  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
-
-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure MSPLIM is RAZ/WI
-    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
-  #else
-    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
-  #endif
-  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
-  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure PSPLIM is RAZ/WI
-    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
-  #else
-    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
-  #endif
-
-  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
-  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
-  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
-  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
-  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
-  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
-  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
-  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
-  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
-  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
-  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
-  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
-  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
-  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
-
-  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
-    // without main extensions, the non-secure PSPLIM is RAZ/WI
-    #define __TZ_get_PSPLIM_NS()      (0U)
-    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
-  #else
-    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
-    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
-  #endif
-
-  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
-  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
-
-  #define __NOP     __iar_builtin_no_operation
-
-  #define __CLZ     __iar_builtin_CLZ
-  #define __CLREX   __iar_builtin_CLREX
-
-  #define __DMB     __iar_builtin_DMB
-  #define __DSB     __iar_builtin_DSB
-  #define __ISB     __iar_builtin_ISB
-
-  #define __LDREXB  __iar_builtin_LDREXB
-  #define __LDREXH  __iar_builtin_LDREXH
-  #define __LDREXW  __iar_builtin_LDREX
-
-  #define __RBIT    __iar_builtin_RBIT
-  #define __REV     __iar_builtin_REV
-  #define __REV16   __iar_builtin_REV16
-
-  __IAR_FT int16_t __REVSH(int16_t val)
-  {
-    return (int16_t) __iar_builtin_REVSH(val);
-  }
-
-  #define __ROR     __iar_builtin_ROR
-  #define __RRX     __iar_builtin_RRX
-
-  #define __SEV     __iar_builtin_SEV
-
-  #if !__IAR_M0_FAMILY
-    #define __SSAT    __iar_builtin_SSAT
-  #endif
-
-  #define __STREXB  __iar_builtin_STREXB
-  #define __STREXH  __iar_builtin_STREXH
-  #define __STREXW  __iar_builtin_STREX
-
-  #if !__IAR_M0_FAMILY
-    #define __USAT    __iar_builtin_USAT
-  #endif
-
-  #define __WFE     __iar_builtin_WFE
-  #define __WFI     __iar_builtin_WFI
-
-  #if __ARM_MEDIA__
-    #define __SADD8   __iar_builtin_SADD8
-    #define __QADD8   __iar_builtin_QADD8
-    #define __SHADD8  __iar_builtin_SHADD8
-    #define __UADD8   __iar_builtin_UADD8
-    #define __UQADD8  __iar_builtin_UQADD8
-    #define __UHADD8  __iar_builtin_UHADD8
-    #define __SSUB8   __iar_builtin_SSUB8
-    #define __QSUB8   __iar_builtin_QSUB8
-    #define __SHSUB8  __iar_builtin_SHSUB8
-    #define __USUB8   __iar_builtin_USUB8
-    #define __UQSUB8  __iar_builtin_UQSUB8
-    #define __UHSUB8  __iar_builtin_UHSUB8
-    #define __SADD16  __iar_builtin_SADD16
-    #define __QADD16  __iar_builtin_QADD16
-    #define __SHADD16 __iar_builtin_SHADD16
-    #define __UADD16  __iar_builtin_UADD16
-    #define __UQADD16 __iar_builtin_UQADD16
-    #define __UHADD16 __iar_builtin_UHADD16
-    #define __SSUB16  __iar_builtin_SSUB16
-    #define __QSUB16  __iar_builtin_QSUB16
-    #define __SHSUB16 __iar_builtin_SHSUB16
-    #define __USUB16  __iar_builtin_USUB16
-    #define __UQSUB16 __iar_builtin_UQSUB16
-    #define __UHSUB16 __iar_builtin_UHSUB16
-    #define __SASX    __iar_builtin_SASX
-    #define __QASX    __iar_builtin_QASX
-    #define __SHASX   __iar_builtin_SHASX
-    #define __UASX    __iar_builtin_UASX
-    #define __UQASX   __iar_builtin_UQASX
-    #define __UHASX   __iar_builtin_UHASX
-    #define __SSAX    __iar_builtin_SSAX
-    #define __QSAX    __iar_builtin_QSAX
-    #define __SHSAX   __iar_builtin_SHSAX
-    #define __USAX    __iar_builtin_USAX
-    #define __UQSAX   __iar_builtin_UQSAX
-    #define __UHSAX   __iar_builtin_UHSAX
-    #define __USAD8   __iar_builtin_USAD8
-    #define __USADA8  __iar_builtin_USADA8
-    #define __SSAT16  __iar_builtin_SSAT16
-    #define __USAT16  __iar_builtin_USAT16
-    #define __UXTB16  __iar_builtin_UXTB16
-    #define __UXTAB16 __iar_builtin_UXTAB16
-    #define __SXTB16  __iar_builtin_SXTB16
-    #define __SXTAB16 __iar_builtin_SXTAB16
-    #define __SMUAD   __iar_builtin_SMUAD
-    #define __SMUADX  __iar_builtin_SMUADX
-    #define __SMMLA   __iar_builtin_SMMLA
-    #define __SMLAD   __iar_builtin_SMLAD
-    #define __SMLADX  __iar_builtin_SMLADX
-    #define __SMLALD  __iar_builtin_SMLALD
-    #define __SMLALDX __iar_builtin_SMLALDX
-    #define __SMUSD   __iar_builtin_SMUSD
-    #define __SMUSDX  __iar_builtin_SMUSDX
-    #define __SMLSD   __iar_builtin_SMLSD
-    #define __SMLSDX  __iar_builtin_SMLSDX
-    #define __SMLSLD  __iar_builtin_SMLSLD
-    #define __SMLSLDX __iar_builtin_SMLSLDX
-    #define __SEL     __iar_builtin_SEL
-    #define __QADD    __iar_builtin_QADD
-    #define __QSUB    __iar_builtin_QSUB
-    #define __PKHBT   __iar_builtin_PKHBT
-    #define __PKHTB   __iar_builtin_PKHTB
-  #endif
-
-#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
-
-  #if __IAR_M0_FAMILY
-   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
-    #define __CLZ  __cmsis_iar_clz_not_active
-    #define __SSAT __cmsis_iar_ssat_not_active
-    #define __USAT __cmsis_iar_usat_not_active
-    #define __RBIT __cmsis_iar_rbit_not_active
-    #define __get_APSR  __cmsis_iar_get_APSR_not_active
-  #endif
-
-
-  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
-    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
-    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
-  #endif
-
-  #ifdef __INTRINSICS_INCLUDED
-  #error intrinsics.h is already included previously!
-  #endif
-
-  #include <intrinsics.h>
-
-  #if __IAR_M0_FAMILY
-   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
-    #undef __CLZ
-    #undef __SSAT
-    #undef __USAT
-    #undef __RBIT
-    #undef __get_APSR
-
-    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
-    {
-      if (data == 0U) { return 32U; }
-
-      uint32_t count = 0U;
-      uint32_t mask = 0x80000000U;
-
-      while ((data & mask) == 0U)
-      {
-        count += 1U;
-        mask = mask >> 1U;
-      }
-      return count;
-    }
-
-    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
-    {
-      uint8_t sc = 31U;
-      uint32_t r = v;
-      for (v >>= 1U; v; v >>= 1U)
-      {
-        r <<= 1U;
-        r |= v & 1U;
-        sc--;
-      }
-      return (r << sc);
-    }
-
-    __STATIC_INLINE  uint32_t __get_APSR(void)
-    {
-      uint32_t res;
-      __asm("MRS      %0,APSR" : "=r" (res));
-      return res;
-    }
-
-  #endif
-
-  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
-         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
-    #undef __get_FPSCR
-    #undef __set_FPSCR
-    #define __get_FPSCR()       (0)
-    #define __set_FPSCR(VALUE)  ((void)VALUE)
-  #endif
-
-  #pragma diag_suppress=Pe940
-  #pragma diag_suppress=Pe177
-
-  #define __enable_irq    __enable_interrupt
-  #define __disable_irq   __disable_interrupt
-  #define __NOP           __no_operation
-
-  #define __get_xPSR      __get_PSR
-
-  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
-
-    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
-    {
-      return __LDREX((unsigned long *)ptr);
-    }
-
-    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
-    {
-      return __STREX(value, (unsigned long *)ptr);
-    }
-  #endif
-
-
-  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
-  #if (__CORTEX_M >= 0x03)
-
-    __IAR_FT uint32_t __RRX(uint32_t value)
-    {
-      uint32_t result;
-      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
-      return(result);
-    }
-
-    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
-    {
-      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
-    }
-
-
-    #define __enable_fault_irq  __enable_fiq
-    #define __disable_fault_irq __disable_fiq
-
-
-  #endif /* (__CORTEX_M >= 0x03) */
-
-  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
-  {
-    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
-  }
-
-  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-   __IAR_FT uint32_t __get_MSPLIM(void)
-    {
-      uint32_t res;
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
-      // without main extensions, the non-secure MSPLIM is RAZ/WI
-      res = 0U;
-    #else
-      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
-    #endif
-      return res;
-    }
-
-    __IAR_FT void   __set_MSPLIM(uint32_t value)
-    {
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
-      // without main extensions, the non-secure MSPLIM is RAZ/WI
-      (void)value;
-    #else
-      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
-    #endif
-    }
-
-    __IAR_FT uint32_t __get_PSPLIM(void)
-    {
-      uint32_t res;
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
-      // without main extensions, the non-secure PSPLIM is RAZ/WI
-      res = 0U;
-    #else
-      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
-    #endif
-      return res;
-    }
-
-    __IAR_FT void   __set_PSPLIM(uint32_t value)
-    {
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
-      // without main extensions, the non-secure PSPLIM is RAZ/WI
-      (void)value;
-    #else
-      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
-    #endif
-    }
-
-    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
-    {
-      uint32_t res;
-      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
-      return res;
-    }
-
-    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
-    {
-      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
-    }
-
-    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
-    {
-      uint32_t res;
-      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
-      return res;
-    }
-
-    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
-    {
-      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
-    }
-
-    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
-    {
-      uint32_t res;
-      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
-      return res;
-    }
-
-    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
-    {
-      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
-    }
-
-    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
-    {
-      uint32_t res;
-      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
-      return res;
-    }
-    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
-    {
-      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
-    }
-
-    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
-    {
-      uint32_t res;
-      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
-      return res;
-    }
-
-    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
-    {
-      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
-    }
-
-    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
-    {
-      uint32_t res;
-      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
-      return res;
-    }
-
-    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
-    {
-      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
-    }
-
-    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
-    {
-      uint32_t res;
-      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
-      return res;
-    }
-
-    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
-    {
-      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
-    }
-
-    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
-    {
-      uint32_t res;
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
-      // without main extensions, the non-secure PSPLIM is RAZ/WI
-      res = 0U;
-    #else
-      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
-    #endif
-      return res;
-    }
-
-    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
-    {
-    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
-         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
-      // without main extensions, the non-secure PSPLIM is RAZ/WI
-      (void)value;
-    #else
-      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
-    #endif
-    }
-
-    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
-    {
-      uint32_t res;
-      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
-      return res;
-    }
-
-    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
-    {
-      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
-    }
-
-  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
-
-#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
-
-#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
-
-#if __IAR_M0_FAMILY
-  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
-  {
-    if ((sat >= 1U) && (sat <= 32U))
-    {
-      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
-      const int32_t min = -1 - max ;
-      if (val > max)
-      {
-        return max;
-      }
-      else if (val < min)
-      {
-        return min;
-      }
-    }
-    return val;
-  }
-
-  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
-  {
-    if (sat <= 31U)
-    {
-      const uint32_t max = ((1U << sat) - 1U);
-      if (val > (int32_t)max)
-      {
-        return max;
-      }
-      else if (val < 0)
-      {
-        return 0U;
-      }
-    }
-    return (uint32_t)val;
-  }
-#endif
-
-#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
-
-  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
-  {
-    uint32_t res;
-    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
-    return ((uint8_t)res);
-  }
-
-  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
-  {
-    uint32_t res;
-    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
-    return ((uint16_t)res);
-  }
-
-  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
-  {
-    uint32_t res;
-    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
-    return res;
-  }
-
-  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
-  {
-    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
-  }
-
-  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
-  {
-    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
-  }
-
-  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
-  {
-    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
-  }
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
-     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
-
-
-  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
-    return ((uint8_t)res);
-  }
-
-  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
-    return ((uint16_t)res);
-  }
-
-  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
-    return res;
-  }
-
-  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
-  {
-    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
-  }
-
-  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
-  {
-    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
-  }
-
-  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
-  {
-    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
-  }
-
-  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
-    return ((uint8_t)res);
-  }
-
-  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
-    return ((uint16_t)res);
-  }
-
-  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
-    return res;
-  }
-
-  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
-    return res;
-  }
-
-  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
-    return res;
-  }
-
-  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
-  {
-    uint32_t res;
-    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
-    return res;
-  }
-
-#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
-
-#undef __IAR_FT
-#undef __IAR_M0_FAMILY
-#undef __ICCARM_V8
-
-#pragma diag_default=Pe940
-#pragma diag_default=Pe177
-
-#endif /* __CMSIS_ICCARM_H__ */
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.7
+ * @date     19. June 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #define __RESTRICT            __restrict
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */
diff --git a/Drivers/CMSIS/Include/cmsis_version.h b/Drivers/CMSIS/Include/cmsis_version.h
index 660f612..ae3f2e3 100644
--- a/Drivers/CMSIS/Include/cmsis_version.h
+++ b/Drivers/CMSIS/Include/cmsis_version.h
@@ -1,39 +1,39 @@
-/**************************************************************************//**
- * @file     cmsis_version.h
- * @brief    CMSIS Core(M) Version definitions
- * @version  V5.0.2
- * @date     19. April 2017
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CMSIS_VERSION_H
-#define __CMSIS_VERSION_H
-
-/*  CMSIS Version definitions */
-#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
-#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
-#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
-                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
-#endif
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif
diff --git a/Drivers/CMSIS/Include/core_armv8mbl.h b/Drivers/CMSIS/Include/core_armv8mbl.h
index 251e4ed..ec76ab2 100644
--- a/Drivers/CMSIS/Include/core_armv8mbl.h
+++ b/Drivers/CMSIS/Include/core_armv8mbl.h
@@ -1,1918 +1,1918 @@
-/**************************************************************************//**
- * @file     core_armv8mbl.h
- * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
- * @version  V5.0.7
- * @date     22. June 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_ARMV8MBL_H_GENERIC
-#define __CORE_ARMV8MBL_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_ARMv8MBL
-  @{
- */
-
-#include "cmsis_version.h"
-
-/*  CMSIS definitions */
-#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
-                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MBL_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_ARMV8MBL_H_DEPENDANT
-#define __CORE_ARMV8MBL_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __ARMv8MBL_REV
-    #define __ARMv8MBL_REV               0x0000U
-    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __SAUREGION_PRESENT
-    #define __SAUREGION_PRESENT       0U
-    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0U
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-
-  #ifndef __ETM_PRESENT
-    #define __ETM_PRESENT             0U
-    #warning "__ETM_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MTB_PRESENT
-    #define __MTB_PRESENT             0U
-    #warning "__MTB_PRESENT not defined in device header file; using default!"
-  #endif
-
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv8MBL */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[16U];
-  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[16U];
-  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[16U];
-  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[16U];
-  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[16U];
-  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-        uint32_t RESERVED5[16U];
-  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-#else
-        uint32_t RESERVED0;
-#endif
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
-#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-        uint32_t RESERVED0[6U];
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-        uint32_t RESERVED3[1U];
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-        uint32_t RESERVED5[1U];
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED6[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-        uint32_t RESERVED7[1U];
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-        uint32_t RESERVED9[1U];
-  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-        uint32_t RESERVED10[1U];
-  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-        uint32_t RESERVED11[1U];
-  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-        uint32_t RESERVED12[1U];
-  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-        uint32_t RESERVED13[1U];
-  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-        uint32_t RESERVED14[1U];
-  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-        uint32_t RESERVED15[1U];
-  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-        uint32_t RESERVED16[1U];
-  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-        uint32_t RESERVED17[1U];
-  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-        uint32_t RESERVED18[1U];
-  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-        uint32_t RESERVED19[1U];
-  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-        uint32_t RESERVED20[1U];
-  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-        uint32_t RESERVED21[1U];
-  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-        uint32_t RESERVED22[1U];
-  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-        uint32_t RESERVED23[1U];
-  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-        uint32_t RESERVED24[1U];
-  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-        uint32_t RESERVED25[1U];
-  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-        uint32_t RESERVED26[1U];
-  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-        uint32_t RESERVED27[1U];
-  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-        uint32_t RESERVED28[1U];
-  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-        uint32_t RESERVED29[1U];
-  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-        uint32_t RESERVED30[1U];
-  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-        uint32_t RESERVED31[1U];
-  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
-        uint32_t RESERVED3[809U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
-        uint32_t RESERVED4[4U];
-  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
-#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
-#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI Periodic Synchronization Control Register Definitions */
-#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
-#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
-
-/* TPI Software Lock Status Register Definitions */
-#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
-#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
-
-#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
-#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
-
-#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
-#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
-#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-        uint32_t RESERVED0[7U];
-  union {
-  __IOM uint32_t MAIR[2];
-  struct {
-  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-  };
-  };
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES                  1U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#endif
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-
-  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-  #endif
-
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-  #endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-  #endif
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
-
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
-#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
-
-/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
-#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
-#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
-#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
-#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
-#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
-#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
-#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
-
-/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
-#else
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
-#endif
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-#define __NVIC_SetPriorityGrouping(X) (void)(X)
-#define __NVIC_GetPriorityGrouping()  (0U)
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-           If VTOR is not present address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-  uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-  uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ##########################  MPU functions  #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv8.h"
-
-#endif
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                         /* Reload value impossible */
-  }
-
-  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                      SysTick_CTRL_TICKINT_Msk   |
-                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
+/**************************************************************************//**
+ * @file     core_armv8mbl.h
+ * @brief    CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MBL_H_GENERIC
+#define __CORE_ARMV8MBL_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MBL
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __ARMv8MBL_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MBL_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MBL_CMSIS_VERSION       ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MBL_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     ( 2U)                                            /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MBL_H_DEPENDANT
+#define __CORE_ARMV8MBL_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MBL_REV
+    #define __ARMv8MBL_REV               0x0000U
+    #warning "__ARMv8MBL_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MBL */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_armv8mml.h b/Drivers/CMSIS/Include/core_armv8mml.h
index 3a3148e..2d0f106 100644
--- a/Drivers/CMSIS/Include/core_armv8mml.h
+++ b/Drivers/CMSIS/Include/core_armv8mml.h
@@ -1,2927 +1,2927 @@
-/**************************************************************************//**
- * @file     core_armv8mml.h
- * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
- * @version  V5.0.7
- * @date     06. July 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_ARMV8MML_H_GENERIC
-#define __CORE_ARMV8MML_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_ARMv8MML
-  @{
- */
-
-#include "cmsis_version.h"
-
-/*  CMSIS Armv8MML definitions */
-#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
-                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-  #if defined(__ARM_FEATURE_DSP)
-    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
-      #define __DSP_USED       1U
-    #else
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U
-    #endif
-  #else
-    #define __DSP_USED         0U
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-  #if defined(__ARM_FEATURE_DSP)
-    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
-      #define __DSP_USED       1U
-    #else
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U
-    #endif
-  #else
-    #define __DSP_USED         0U
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-  #if defined(__ARM_FEATURE_DSP)
-    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
-      #define __DSP_USED       1U
-    #else
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U
-    #endif
-  #else
-    #define __DSP_USED         0U
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-  #if defined(__ARM_FEATURE_DSP)
-    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
-      #define __DSP_USED       1U
-    #else
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U
-    #endif
-  #else
-    #define __DSP_USED         0U
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MML_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_ARMV8MML_H_DEPENDANT
-#define __CORE_ARMV8MML_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __ARMv8MML_REV
-    #define __ARMv8MML_REV               0x0000U
-    #warning "__ARMv8MML_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __SAUREGION_PRESENT
-    #define __SAUREGION_PRESENT       0U
-    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __DSP_PRESENT
-    #define __DSP_PRESENT             0U
-    #warning "__DSP_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group ARMv8MML */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
-    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
-    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
-    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
-#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
-
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[16U];
-  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[16U];
-  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[16U];
-  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[16U];
-  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[16U];
-  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-        uint32_t RESERVED5[16U];
-  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED6[580U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
-  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
-  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
-  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
-        uint32_t RESERVED3[92U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
-        uint32_t RESERVED4[15U];
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
-        uint32_t RESERVED5[1U];
-  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
-        uint32_t RESERVED6[1U];
-  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
-  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
-  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
-  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
-  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
-  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
-  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
-  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
-        uint32_t RESERVED7[6U];
-  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
-  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
-  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
-  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
-  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
-#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
-#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
-
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
-#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
-#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Non-Secure Access Control Register Definitions */
-#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
-#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
-
-#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
-#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
-
-#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
-#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[1U];
-  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
-        uint32_t RESERVED6[4U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Stimulus Port Register Definitions */
-#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
-#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
-
-#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
-#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
-#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
-
-#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
-#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-        uint32_t RESERVED3[1U];
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-        uint32_t RESERVED5[1U];
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED6[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-        uint32_t RESERVED7[1U];
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-        uint32_t RESERVED9[1U];
-  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-        uint32_t RESERVED10[1U];
-  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-        uint32_t RESERVED11[1U];
-  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-        uint32_t RESERVED12[1U];
-  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-        uint32_t RESERVED13[1U];
-  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-        uint32_t RESERVED14[1U];
-  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-        uint32_t RESERVED15[1U];
-  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-        uint32_t RESERVED16[1U];
-  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-        uint32_t RESERVED17[1U];
-  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-        uint32_t RESERVED18[1U];
-  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-        uint32_t RESERVED19[1U];
-  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-        uint32_t RESERVED20[1U];
-  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-        uint32_t RESERVED21[1U];
-  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-        uint32_t RESERVED22[1U];
-  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-        uint32_t RESERVED23[1U];
-  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-        uint32_t RESERVED24[1U];
-  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-        uint32_t RESERVED25[1U];
-  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-        uint32_t RESERVED26[1U];
-  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-        uint32_t RESERVED27[1U];
-  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-        uint32_t RESERVED28[1U];
-  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-        uint32_t RESERVED29[1U];
-  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-        uint32_t RESERVED30[1U];
-  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-        uint32_t RESERVED31[1U];
-  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-        uint32_t RESERVED32[934U];
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
-        uint32_t RESERVED33[1U];
-  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
-#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
-        uint32_t RESERVED3[809U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
-        uint32_t RESERVED4[4U];
-  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
-#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
-#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI Periodic Synchronization Control Register Definitions */
-#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
-#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
-
-/* TPI Software Lock Status Register Definitions */
-#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
-#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
-
-#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
-#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
-
-#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
-#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
-#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
-  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
-  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
-  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
-        uint32_t RESERVED0[1];
-  union {
-  __IOM uint32_t MAIR[2];
-  struct {
-  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-  };
-  };
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES                  4U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#else
-        uint32_t RESERVED0[3];
-#endif
-  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
-  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/* Secure Fault Status Register Definitions */
-#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
-#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
-
-#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
-#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
-
-#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
-#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
-
-#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
-#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
-
-#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
-#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
-
-#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
-#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
-
-#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
-#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
-
-#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
-#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
-#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
-
-#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
-#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
-
-#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
-#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
-
-#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
-#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
-
-#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
-#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
-
-#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
-#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
-#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
-#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
-  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
-  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
-  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-  #endif
-
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-  #endif
-
-  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
-  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
-  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-  #endif
-
-  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
-  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
-
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
-#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
-
-/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
-#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
-#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
-#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
-#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
-#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
-#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
-#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
-
-/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
-#else
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
-#endif
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Set Priority Grouping (non-secure)
-  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB_NS->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping (non-secure)
-  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
-{
-  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ##########################  MPU functions  #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv8.h"
-
-#endif
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-  uint32_t mvfr0;
-
-  mvfr0 = FPU->MVFR0;
-  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
-  {
-    return 2U;           /* Double + Single precision FPU */
-  }
-  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
-  {
-    return 1U;           /* Single precision FPU */
-  }
-  else
-  {
-    return 0U;           /* No FPU */
-  }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                         /* Reload value impossible */
-  }
-
-  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                      SysTick_CTRL_TICKINT_Msk   |
-                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_ARMV8MML_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
+/**************************************************************************//**
+ * @file     core_armv8mml.h
+ * @brief    CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_ARMV8MML_H_GENERIC
+#define __CORE_ARMV8MML_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_ARMv8MML
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS Armv8MML definitions */
+#define __ARMv8MML_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __ARMv8MML_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __ARMv8MML_CMSIS_VERSION       ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \
+                                         __ARMv8MML_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                     (81U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined(__ARM_FEATURE_DSP)
+    #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_ARMV8MML_H_DEPENDANT
+#define __CORE_ARMV8MML_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __ARMv8MML_REV
+    #define __ARMv8MML_REV               0x0000U
+    #warning "__ARMv8MML_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group ARMv8MML */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Sizes Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Sizes Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[809U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  Software Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  Software Lock Status Register */
+        uint32_t RESERVED4[4U];
+  __IM  uint32_t TYPE;                   /*!< Offset: 0xFC8 (R/ )  Device Identifier Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_SWOSCALER_Pos              0U                                         /*!< TPI ACPR: SWOSCALER Position */
+#define TPI_ACPR_SWOSCALER_Msk             (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)    /*!< TPI ACPR: SWOSCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI Periodic Synchronization Control Register Definitions */
+#define TPI_PSCR_PSCount_Pos                0U                                         /*!< TPI PSCR: PSCount Position */
+#define TPI_PSCR_PSCount_Msk               (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/)        /*!< TPI PSCR: TPSCount Mask */
+
+/* TPI Software Lock Status Register Definitions */
+#define TPI_LSR_nTT_Pos                     1U                                         /*!< TPI LSR: Not thirty-two bit. Position */
+#define TPI_LSR_nTT_Msk                    (0x1UL << TPI_LSR_nTT_Pos)                  /*!< TPI LSR: Not thirty-two bit. Mask */
+
+#define TPI_LSR_SLK_Pos                     1U                                         /*!< TPI LSR: Software Lock status Position */
+#define TPI_LSR_SLK_Msk                    (0x1UL << TPI_LSR_SLK_Pos)                  /*!< TPI LSR: Software Lock status Mask */
+
+#define TPI_LSR_SLI_Pos                     0U                                         /*!< TPI LSR: Software Lock implemented Position */
+#define TPI_LSR_SLI_Msk                    (0x1UL /*<< TPI_LSR_SLI_Pos*/)              /*!< TPI LSR: Software Lock implemented Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFO depth Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFO depth Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk));             /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_ARMV8MML_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm0.h b/Drivers/CMSIS/Include/core_cm0.h
index f929bba..6f82227 100644
--- a/Drivers/CMSIS/Include/core_cm0.h
+++ b/Drivers/CMSIS/Include/core_cm0.h
@@ -1,949 +1,949 @@
-/**************************************************************************//**
- * @file     core_cm0.h
- * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version  V5.0.5
- * @date     28. May 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M0
-  @{
- */
-
-#include "cmsis_version.h"
- 
-/*  CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0_REV
-    #define __CM0_REV               0x0000U
-    #warning "__CM0_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-        uint32_t RESERVED0;
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the Cortex-M0 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-#define __NVIC_SetPriorityGrouping(X) (void)(X)
-#define __NVIC_GetPriorityGrouping()  (0U)
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           Address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)0x0U;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)0x0U;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M0
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM0_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (0U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000U
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M0 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm0plus.h b/Drivers/CMSIS/Include/core_cm0plus.h
index 424011a..b9377e8 100644
--- a/Drivers/CMSIS/Include/core_cm0plus.h
+++ b/Drivers/CMSIS/Include/core_cm0plus.h
@@ -1,1083 +1,1083 @@
-/**************************************************************************//**
- * @file     core_cm0plus.h
- * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version  V5.0.6
- * @date     28. May 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex-M0+
-  @{
- */
-
-#include "cmsis_version.h"
- 
-/*  CMSIS CM0+ definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
-                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM0PLUS_REV
-    #define __CM0PLUS_REV             0x0000U
-    #warning "__CM0PLUS_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0U
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-#else
-        uint32_t RESERVED0;
-#endif
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES                  1U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the Cortex-M0+ header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-#define __NVIC_SetPriorityGrouping(X) (void)(X)
-#define __NVIC_GetPriorityGrouping()  (0U)
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-           If VTOR is not present address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-    uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-  uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ##########################  MPU functions  #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv7.h"
-
-#endif
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
+/**************************************************************************//**
+ * @file     core_cm0plus.h
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM0PLUS_H_GENERIC
+#define __CORE_CM0PLUS_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex-M0+
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM0+ definitions */
+#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM0PLUS_CMSIS_VERSION_SUB  (__CM_CMSIS_VERSION_SUB)                   /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \
+                                       __CM0PLUS_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                   (0U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
+#define __CORE_CM0PLUS_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0PLUS_REV
+    #define __CM0PLUS_REV             0x0000U
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex-M0+ */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 8U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M0+ header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M0+ */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+    uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm1.h b/Drivers/CMSIS/Include/core_cm1.h
index 0ed678e..fd1c407 100644
--- a/Drivers/CMSIS/Include/core_cm1.h
+++ b/Drivers/CMSIS/Include/core_cm1.h
@@ -1,976 +1,976 @@
-/**************************************************************************//**
- * @file     core_cm1.h
- * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
- * @version  V1.0.0
- * @date     23. July 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM1_H_GENERIC
-#define __CORE_CM1_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M1
-  @{
- */
-
-#include "cmsis_version.h"
- 
-/*  CMSIS CM1 definitions */
-#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM1_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM1_H_DEPENDANT
-#define __CORE_CM1_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM1_REV
-    #define __CM1_REV               0x0100U
-    #warning "__CM1_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M1 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-        uint32_t RESERVED0;
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
-#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
-
-#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
-#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the Cortex-M1 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-#define __NVIC_SetPriorityGrouping(X) (void)(X)
-#define __NVIC_GetPriorityGrouping()  (0U)
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           Address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)0x0U;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)0x0U;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM1_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
+/**************************************************************************//**
+ * @file     core_cm1.h
+ * @brief    CMSIS Cortex-M1 Core Peripheral Access Layer Header File
+ * @version  V1.0.0
+ * @date     23. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM1_H_GENERIC
+#define __CORE_CM1_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M1
+  @{
+ */
+
+#include "cmsis_version.h"
+ 
+/*  CMSIS CM1 definitions */
+#define __CM1_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM1_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM1_CMSIS_VERSION       ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM1_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (1U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM1_H_DEPENDANT
+#define __CORE_CM1_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM1_REV
+    #define __CM1_REV               0x0100U
+    #warning "__CM1_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M1 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+        uint32_t RESERVED0;
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_ITCMUAEN_Pos            4U                                        /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMUAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)         /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
+
+#define SCnSCB_ACTLR_ITCMLAEN_Pos            3U                                        /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
+#define SCnSCB_ACTLR_ITCMLAEN_Msk           (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)         /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the Cortex-M1 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for Cortex-M1 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           Address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)0x0U;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM1_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm23.h b/Drivers/CMSIS/Include/core_cm23.h
index acbc5df..8202a8d 100644
--- a/Drivers/CMSIS/Include/core_cm23.h
+++ b/Drivers/CMSIS/Include/core_cm23.h
@@ -1,1993 +1,1993 @@
-/**************************************************************************//**
- * @file     core_cm23.h
- * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
- * @version  V5.0.7
- * @date     22. June 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM23_H_GENERIC
-#define __CORE_CM23_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M23
-  @{
- */
-
-#include "cmsis_version.h"
-
-/*  CMSIS definitions */
-#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
-                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM23_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM23_H_DEPENDANT
-#define __CORE_CM23_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM23_REV
-    #define __CM23_REV                0x0000U
-    #warning "__CM23_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __SAUREGION_PRESENT
-    #define __SAUREGION_PRESENT       0U
-    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __VTOR_PRESENT
-    #define __VTOR_PRESENT            0U
-    #warning "__VTOR_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-
-  #ifndef __ETM_PRESENT
-    #define __ETM_PRESENT             0U
-    #warning "__ETM_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MTB_PRESENT
-    #define __MTB_PRESENT             0U
-    #warning "__MTB_PRESENT not defined in device header file; using default!"
-  #endif
-
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M23 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[16U];
-  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[16U];
-  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[16U];
-  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[16U];
-  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[16U];
-  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-        uint32_t RESERVED5[16U];
-  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-#else
-        uint32_t RESERVED0;
-#endif
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED1;
-  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
-#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-        uint32_t RESERVED0[6U];
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-        uint32_t RESERVED3[1U];
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-        uint32_t RESERVED5[1U];
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED6[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-        uint32_t RESERVED7[1U];
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-        uint32_t RESERVED9[1U];
-  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-        uint32_t RESERVED10[1U];
-  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-        uint32_t RESERVED11[1U];
-  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-        uint32_t RESERVED12[1U];
-  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-        uint32_t RESERVED13[1U];
-  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-        uint32_t RESERVED14[1U];
-  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-        uint32_t RESERVED15[1U];
-  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-        uint32_t RESERVED16[1U];
-  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-        uint32_t RESERVED17[1U];
-  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-        uint32_t RESERVED18[1U];
-  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-        uint32_t RESERVED19[1U];
-  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-        uint32_t RESERVED20[1U];
-  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-        uint32_t RESERVED21[1U];
-  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-        uint32_t RESERVED22[1U];
-  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-        uint32_t RESERVED23[1U];
-  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-        uint32_t RESERVED24[1U];
-  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-        uint32_t RESERVED25[1U];
-  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-        uint32_t RESERVED26[1U];
-  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-        uint32_t RESERVED27[1U];
-  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-        uint32_t RESERVED28[1U];
-  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-        uint32_t RESERVED29[1U];
-  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-        uint32_t RESERVED30[1U];
-  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-        uint32_t RESERVED31[1U];
-  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
-  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
-  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
-  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
-#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration Test FIFO Test Data 0 Register Definitions */
-#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
-#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
-
-#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
-#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
-#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
-#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
-#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
-#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
-#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
-
-/* TPI Integration Test ATB Control Register 2 Register Definitions */
-#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
-#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
-
-#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
-#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
-
-#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
-#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
-
-#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
-#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
-
-/* TPI Integration Test FIFO Test Data 1 Register Definitions */
-#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
-#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
-#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
-
-#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
-#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
-
-#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
-#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
-#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
-#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
-#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
-
-/* TPI Integration Test ATB Control Register 0 Definitions */
-#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
-#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
-
-#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
-#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
-
-#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
-#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
-
-#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
-#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
-#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-        uint32_t RESERVED0[7U];
-  union {
-  __IOM uint32_t MAIR[2];
-  struct {
-  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-  };
-  };
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES                  1U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#endif
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
-#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-
-  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-  #endif
-
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-  #endif
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-  #endif
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
-
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
-#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
-
-/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
-#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
-#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
-#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
-#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
-#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
-#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
-#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
-
-/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
-#else 
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
-#endif
-
-	
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-#define __NVIC_SetPriorityGrouping(X) (void)(X)
-#define __NVIC_GetPriorityGrouping()  (0U)
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-           If VTOR is not present address 0 must be mapped to SRAM.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-  uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-#else
-  uint32_t *vectors = (uint32_t *)0x0U;
-#endif
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ##########################  MPU functions  #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv8.h"
-
-#endif
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                         /* Reload value impossible */
-  }
-
-  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                      SysTick_CTRL_TICKINT_Msk   |
-                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM23_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
+/**************************************************************************//**
+ * @file     core_cm23.h
+ * @brief    CMSIS Cortex-M23 Core Peripheral Access Layer Header File
+ * @version  V5.0.7
+ * @date     22. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM23_H_GENERIC
+#define __CORE_CM23_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M23
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS definitions */
+#define __CM23_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM23_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM23_CMSIS_VERSION       ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM23_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (23U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM23_H_DEPENDANT
+#define __CORE_CM23_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM23_REV
+    #define __CM23_REV                0x0000U
+    #warning "__CM23_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __VTOR_PRESENT
+    #define __VTOR_PRESENT            0U
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ETM_PRESENT
+    #define __ETM_PRESENT             0U
+    #warning "__ETM_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MTB_PRESENT
+    #define __MTB_PRESENT             0U
+    #warning "__MTB_PRESENT not defined in device header file; using default!"
+  #endif
+
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M23 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint32_t IPR[124U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+#else
+        uint32_t RESERVED0;
+#endif
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED1;
+  __IOM uint32_t SHPR[2U];               /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+        uint32_t RESERVED0[6U];
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x3UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+        uint32_t RESERVED0[7U];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  1U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: EN Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: EN Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#endif
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_DWTENA_Pos         24U                                            /*!< CoreDebug DEMCR: DWTENA Position */
+#define CoreDebug_DEMCR_DWTENA_Msk         (1UL << CoreDebug_DEMCR_DWTENA_Pos)            /*!< CoreDebug DEMCR: DWTENA Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for Cortex-M23 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for Cortex-M23 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+	
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+#define __NVIC_SetPriorityGrouping(X) (void)(X)
+#define __NVIC_GetPriorityGrouping()  (0U)
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+           If VTOR is not present address 0 must be mapped to SRAM.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+#else
+  uint32_t *vectors = (uint32_t *)0x0U;
+#endif
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM23_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm3.h b/Drivers/CMSIS/Include/core_cm3.h
index 74bff64..b0dfbd3 100644
--- a/Drivers/CMSIS/Include/core_cm3.h
+++ b/Drivers/CMSIS/Include/core_cm3.h
@@ -1,1941 +1,1941 @@
-/**************************************************************************//**
- * @file     core_cm3.h
- * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version  V5.0.8
- * @date     04. June 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M3
-  @{
- */
-
-#include "cmsis_version.h"
-
-/*  CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM3_REV
-    #define __CM3_REV               0x0200U
-    #warning "__CM3_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M3 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
-    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
-    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
-    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[24U];
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[24U];
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[24U];
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[24U];
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[56U];
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED5[644U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-        uint32_t RESERVED0[5U];
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-#else
-        uint32_t RESERVED1[1U];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[6U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
-#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
-
-#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
-#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
-#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
-
-#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
-#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES                  4U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ##########################  MPU functions  #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv7.h"
-
-#endif
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M3
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM3_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (3U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200U
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M3 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#if defined (__CM3_REV) && (__CM3_REV < 0x0201U)                   /* core r2p1 */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+#else
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+#endif
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+#if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+#else
+        uint32_t RESERVED1[1U];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm33.h b/Drivers/CMSIS/Include/core_cm33.h
index 6cd2db7..02f82e2 100644
--- a/Drivers/CMSIS/Include/core_cm33.h
+++ b/Drivers/CMSIS/Include/core_cm33.h
@@ -1,3002 +1,3002 @@
-/**************************************************************************//**
- * @file     core_cm33.h
- * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
- * @version  V5.0.9
- * @date     06. July 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM33_H_GENERIC
-#define __CORE_CM33_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M33
-  @{
- */
-
-#include "cmsis_version.h"
-
-/*  CMSIS CM33 definitions */
-#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
-                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined (__TARGET_FPU_VFP)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
-    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
-      #define __DSP_USED       1U
-    #else
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U
-    #endif
-  #else
-    #define __DSP_USED         0U
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined (__ARM_PCS_VFP)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
-    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
-      #define __DSP_USED       1U
-    #else
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U
-    #endif
-  #else
-    #define __DSP_USED         0U
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
-    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
-      #define __DSP_USED       1U
-    #else
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U
-    #endif
-  #else
-    #define __DSP_USED         0U
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined (__ARMVFP__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
-    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
-      #define __DSP_USED       1U
-    #else
-      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
-      #define __DSP_USED         0U
-    #endif
-  #else
-    #define __DSP_USED         0U
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined (__TI_VFP_SUPPORT__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined (__FPU_VFP__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM33_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM33_H_DEPENDANT
-#define __CORE_CM33_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM33_REV
-    #define __CM33_REV                0x0000U
-    #warning "__CM33_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __SAUREGION_PRESENT
-    #define __SAUREGION_PRESENT       0U
-    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __DSP_PRESENT
-    #define __DSP_PRESENT             0U
-    #warning "__DSP_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M33 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core SAU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
-#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
-    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
-    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
-    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
-#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
-
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[16U];
-  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[16U];
-  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[16U];
-  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[16U];
-  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[16U];
-  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
-        uint32_t RESERVED5[16U];
-  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED6[580U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
-  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
-  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
-  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
-        uint32_t RESERVED3[92U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
-        uint32_t RESERVED4[15U];
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
-        uint32_t RESERVED5[1U];
-  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
-        uint32_t RESERVED6[1U];
-  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
-  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
-  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
-  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
-  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
-  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
-  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
-  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
-        uint32_t RESERVED7[6U];
-  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
-  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
-  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
-  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
-  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
-#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
-
-#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
-#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
-
-#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
-#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
-#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
-#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
-
-#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
-#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
-#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
-#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
-
-#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
-
-#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
-
-#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
-#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
-#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
-#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
-
-#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
-#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
-
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
-#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
-
-#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
-#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
-#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
-#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Non-Secure Access Control Register Definitions */
-#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
-#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
-
-#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
-#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
-
-#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
-#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[1U];
-  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
-        uint32_t RESERVED6[4U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Stimulus Port Register Definitions */
-#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
-#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
-
-#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
-#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
-#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
-
-#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
-#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-        uint32_t RESERVED3[1U];
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-        uint32_t RESERVED5[1U];
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED6[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-        uint32_t RESERVED7[1U];
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
-        uint32_t RESERVED9[1U];
-  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
-        uint32_t RESERVED10[1U];
-  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
-        uint32_t RESERVED11[1U];
-  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
-        uint32_t RESERVED12[1U];
-  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
-        uint32_t RESERVED13[1U];
-  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
-        uint32_t RESERVED14[1U];
-  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
-        uint32_t RESERVED15[1U];
-  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
-        uint32_t RESERVED16[1U];
-  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
-        uint32_t RESERVED17[1U];
-  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
-        uint32_t RESERVED18[1U];
-  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
-        uint32_t RESERVED19[1U];
-  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
-        uint32_t RESERVED20[1U];
-  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
-        uint32_t RESERVED21[1U];
-  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
-        uint32_t RESERVED22[1U];
-  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
-        uint32_t RESERVED23[1U];
-  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
-        uint32_t RESERVED24[1U];
-  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
-        uint32_t RESERVED25[1U];
-  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
-        uint32_t RESERVED26[1U];
-  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
-        uint32_t RESERVED27[1U];
-  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
-        uint32_t RESERVED28[1U];
-  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
-        uint32_t RESERVED29[1U];
-  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
-        uint32_t RESERVED30[1U];
-  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
-        uint32_t RESERVED31[1U];
-  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
-        uint32_t RESERVED32[934U];
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
-        uint32_t RESERVED33[1U];
-  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
-#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
-#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
-
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
-#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
-
-#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
-#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
-  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
-  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
-  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
-#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration Test FIFO Test Data 0 Register Definitions */
-#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
-#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
-
-#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
-#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
-#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
-#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
-#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
-#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
-
-#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
-#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
-
-/* TPI Integration Test ATB Control Register 2 Register Definitions */
-#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
-#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
-
-#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
-#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
-
-#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
-#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
-
-#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
-#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
-
-/* TPI Integration Test FIFO Test Data 1 Register Definitions */
-#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
-#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
-#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
-
-#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
-#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
-
-#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
-#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
-#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
-#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
-
-#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
-#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
-
-/* TPI Integration Test ATB Control Register 0 Definitions */
-#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
-#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
-
-#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
-#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
-
-#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
-#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
-
-#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
-#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
-#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
-  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
-  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
-  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
-        uint32_t RESERVED0[1];
-  union {
-  __IOM uint32_t MAIR[2];
-  struct {
-  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
-  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
-  };
-  };
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES                  4U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
-#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
-
-#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
-#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
-
-#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
-#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
-
-#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
-#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
-
-/* MPU Region Limit Address Register Definitions */
-#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
-#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
-
-#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
-#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
-
-#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
-#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
-
-/* MPU Memory Attribute Indirection Register 0 Definitions */
-#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
-#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
-
-#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
-#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
-
-#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
-#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
-
-#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
-#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
-
-/* MPU Memory Attribute Indirection Register 1 Definitions */
-#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
-#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
-
-#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
-#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
-
-#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
-#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
-
-#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
-#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
-  \brief    Type definitions for the Security Attribution Unit (SAU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Security Attribution Unit (SAU).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
-  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
-#else
-        uint32_t RESERVED0[3];
-#endif
-  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
-  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
-} SAU_Type;
-
-/* SAU Control Register Definitions */
-#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
-#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
-
-#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
-#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
-
-/* SAU Type Register Definitions */
-#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
-#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
-
-#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
-/* SAU Region Number Register Definitions */
-#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
-#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
-
-/* SAU Region Base Address Register Definitions */
-#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
-#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
-
-/* SAU Region Limit Address Register Definitions */
-#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
-#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
-
-#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
-#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
-
-#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
-#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
-
-#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
-
-/* Secure Fault Status Register Definitions */
-#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
-#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
-
-#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
-#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
-
-#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
-#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
-
-#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
-#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
-
-#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
-#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
-
-#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
-#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
-
-#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
-#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
-
-#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
-#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
-
-/*@} end of group CMSIS_SAU */
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
-#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
-
-#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
-#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
-
-#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
-#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
-
-#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
-#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
-
-#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
-#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
-
-#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
-#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
-#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
-#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-        uint32_t RESERVED4[1U];
-  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
-  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
-#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/* Debug Authentication Control Register Definitions */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
-#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
-
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
-
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
-#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
-
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
-#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
-
-/* Debug Security Control and Status Register Definitions */
-#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
-#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
-
-#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
-#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
-
-#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
-#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
-  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
-  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
-  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
-  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
-  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
-  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
-  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
-
-  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
-  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
-  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
-  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
-  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
-  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
-  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
-  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
-    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
-  #endif
-
-  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
-    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
-  #endif
-
-  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
-  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
-  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
-  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
-  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
-  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
-
-  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
-  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
-  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
-  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
-  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
-
-  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
-    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
-  #endif
-
-  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
-  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
-
-/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
-#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
-
-/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
-#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
-#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
-#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
-#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
-#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
-#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
-#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
-
-/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
-#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
-#else 
-#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
-#endif
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priority group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Get Interrupt Target State
-  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-  \return             1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Target State
-  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Clear Interrupt Target State
-  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  if interrupt is assigned to Secure
-                      1  if interrupt is assigned to Non Secure
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
-    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   Set Priority Grouping (non-secure)
-  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
-  SCB_NS->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping (non-secure)
-  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
-{
-  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt (non-secure)
-  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status (non-secure)
-  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt (non-secure)
-  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt (non-secure)
-  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt (non-secure)
-  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt (non-secure)
-  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt (non-secure)
-  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority (non-secure)
-  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every non-secure processor exception.
- */
-__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority (non-secure)
-  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ##########################  MPU functions  #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv8.h"
-
-#endif
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-  uint32_t mvfr0;
-
-  mvfr0 = FPU->MVFR0;
-  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
-  {
-    return 2U;           /* Double + Single precision FPU */
-  }
-  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
-  {
-    return 1U;           /* Single precision FPU */
-  }
-  else
-  {
-    return 0U;           /* No FPU */
-  }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################   SAU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SAUFunctions SAU Functions
-  \brief    Functions that configure the SAU.
-  @{
- */
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-
-/**
-  \brief   Enable SAU
-  \details Enables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Enable(void)
-{
-    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
-}
-
-
-
-/**
-  \brief   Disable SAU
-  \details Disables the Security Attribution Unit (SAU).
- */
-__STATIC_INLINE void TZ_SAU_Disable(void)
-{
-    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
-}
-
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-/*@} end of CMSIS_Core_SAUFunctions */
-
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
-/**
-  \brief   System Tick Configuration (non-secure)
-  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                         /* Reload value impossible */
-  }
-
-  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
-  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
-  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                      SysTick_CTRL_TICKINT_Msk   |
-                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                           /* Function successful */
-}
-#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM33_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.0.9
+ * @date     06. July 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined (__TARGET_FPU_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined (__ARM_PCS_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined (__ARMVFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined (__TI_VFP_SUPPORT__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined (__FPU_VFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM33_REV
+    #define __CM33_REV                0x0000U
+    #warning "__CM33_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000002UL)     /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm4.h b/Drivers/CMSIS/Include/core_cm4.h
index 7d56873..308b868 100644
--- a/Drivers/CMSIS/Include/core_cm4.h
+++ b/Drivers/CMSIS/Include/core_cm4.h
@@ -1,2129 +1,2129 @@
-/**************************************************************************//**
- * @file     core_cm4.h
- * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version  V5.0.8
- * @date     04. June 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M4
-  @{
- */
-
-#include "cmsis_version.h"
-
-/* CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM4_REV
-    #define __CM4_REV               0x0000U
-    #warning "__CM4_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
-    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
-    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[24U];
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[24U];
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[24U];
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[24U];
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[56U];
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED5[644U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-        uint32_t RESERVED0[5U];
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[6U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
-#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
-
-#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
-#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
-#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
-
-#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
-#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES                  4U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
-#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
-#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
-#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
-#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ##########################  MPU functions  #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv7.h"
-
-#endif
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-  uint32_t mvfr0;
-
-  mvfr0 = FPU->MVFR0;
-  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
-  {
-    return 1U;           /* Single precision FPU */
-  }
-  else
-  {
-    return 0U;           /* No FPU */
-  }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)              /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)               /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (4U)                                   /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_cm7.h b/Drivers/CMSIS/Include/core_cm7.h
index a14dc62..ada6c2a 100644
--- a/Drivers/CMSIS/Include/core_cm7.h
+++ b/Drivers/CMSIS/Include/core_cm7.h
@@ -1,2671 +1,2671 @@
-/**************************************************************************//**
- * @file     core_cm7.h
- * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
- * @version  V5.0.8
- * @date     04. June 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM7_H_GENERIC
-#define __CORE_CM7_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup Cortex_M7
-  @{
- */
-
-#include "cmsis_version.h"
-
-/* CMSIS CM7 definitions */
-#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
-                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
-      #define __FPU_USED       1U
-    #else
-      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-      #define __FPU_USED       0U
-    #endif
-  #else
-    #define __FPU_USED         0U
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM7_H_DEPENDANT
-#define __CORE_CM7_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __CM7_REV
-    #define __CM7_REV               0x0000U
-    #warning "__CM7_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __FPU_PRESENT
-    #define __FPU_PRESENT             0U
-    #warning "__FPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __ICACHE_PRESENT
-    #define __ICACHE_PRESENT          0U
-    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __DCACHE_PRESENT
-    #define __DCACHE_PRESENT          0U
-    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __DTCM_PRESENT
-    #define __DTCM_PRESENT            0U
-    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M7 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
-  - Core FPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
-#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
-    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
-    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
-    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
-    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
-#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
-    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[24U];
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[24U];
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[24U];
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[24U];
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[56U];
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED5[644U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
-  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
-  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
-  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-        uint32_t RESERVED3[93U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
-        uint32_t RESERVED4[15U];
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
-        uint32_t RESERVED5[1U];
-  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
-        uint32_t RESERVED6[1U];
-  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
-  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
-  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
-  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
-  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
-  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
-  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
-  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
-        uint32_t RESERVED7[6U];
-  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
-  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
-  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
-  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
-  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
-        uint32_t RESERVED8[1U];
-  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
-#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
-
-#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
-#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
-
-#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
-#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
-
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
-#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
-#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/* SCB Cache Level ID Register Definitions */
-#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
-#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
-
-#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
-#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
-
-/* SCB Cache Type Register Definitions */
-#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
-#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
-
-#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
-#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
-
-#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
-#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
-
-#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
-#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
-
-#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
-#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
-
-/* SCB Cache Size ID Register Definitions */
-#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
-#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
-
-#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
-#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
-
-#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
-#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
-
-#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
-#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
-
-#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
-#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
-
-#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
-#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
-
-#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
-#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
-
-/* SCB Cache Size Selection Register Definitions */
-#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
-#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
-
-#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
-#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
-
-/* SCB Software Triggered Interrupt Register Definitions */
-#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
-#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
-
-/* SCB D-Cache Invalidate by Set-way Register Definitions */
-#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
-#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
-
-#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
-#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
-
-/* SCB D-Cache Clean by Set-way Register Definitions */
-#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
-#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
-
-#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
-#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
-
-/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
-#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
-#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
-
-#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
-#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
-
-/* Instruction Tightly-Coupled Memory Control Register Definitions */
-#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
-#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
-
-#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
-#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
-
-#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
-#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
-
-#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
-#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
-
-/* Data Tightly-Coupled Memory Control Register Definitions */
-#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
-#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
-
-#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
-#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
-
-#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
-#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
-
-#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
-#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
-
-/* AHBP Control Register Definitions */
-#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
-#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
-
-#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
-#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
-
-/* L1 Cache Control Register Definitions */
-#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
-#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
-
-#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
-#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
-
-#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
-#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
-
-/* AHBS Control Register Definitions */
-#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
-#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
-
-#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
-#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
-
-#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
-#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
-
-/* Auxiliary Bus Fault Status Register Definitions */
-#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
-#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
-
-#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
-#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
-
-#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
-#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
-
-#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
-#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
-
-#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
-#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
-
-#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
-#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
-#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
-
-#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
-#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
-
-#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
-#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[6U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-        uint32_t RESERVED3[981U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
-#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
-
-#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
-#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
-#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
-
-#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
-#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-#define MPU_TYPE_RALIASES                  4U
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
-  \brief    Type definitions for the Floating Point Unit (FPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
-  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
-  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
-  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
-  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
-  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
-
-/* Media and FP Feature Register 2 Definitions */
-
-/*@} end of group CMSIS_FPU */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
-#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
-#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
-#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
-#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-/* ##########################  MPU functions  #################################### */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-
-#include "mpu_armv7.h"
-
-#endif
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-  uint32_t mvfr0;
-
-  mvfr0 = SCB->MVFR0;
-  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
-  {
-    return 2U;           /* Double + Single precision FPU */
-  }
-  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
-  {
-    return 1U;           /* Single precision FPU */
-  }
-  else
-  {
-    return 0U;           /* No FPU */
-  }
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##########################  Cache functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_CacheFunctions Cache Functions
-  \brief    Functions that configure Instruction and Data cache.
-  @{
- */
-
-/* Cache Size ID Register Macros */
-#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
-#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
-
-
-/**
-  \brief   Enable I-Cache
-  \details Turns on I-Cache
-  */
-__STATIC_INLINE void SCB_EnableICache (void)
-{
-  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
-    __DSB();
-    __ISB();
-    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
-    __DSB();
-    __ISB();
-    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Disable I-Cache
-  \details Turns off I-Cache
-  */
-__STATIC_INLINE void SCB_DisableICache (void)
-{
-  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
-    __DSB();
-    __ISB();
-    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
-    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Invalidate I-Cache
-  \details Invalidates I-Cache
-  */
-__STATIC_INLINE void SCB_InvalidateICache (void)
-{
-  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
-    __DSB();
-    __ISB();
-    SCB->ICIALLU = 0UL;
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Enable D-Cache
-  \details Turns on D-Cache
-  */
-__STATIC_INLINE void SCB_EnableDCache (void)
-{
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-                                            /* invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-      do {
-        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
-                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
-        #if defined ( __CC_ARM )
-          __schedule_barrier();
-        #endif
-      } while (ways-- != 0U);
-    } while(sets-- != 0U);
-    __DSB();
-
-    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Disable D-Cache
-  \details Turns off D-Cache
-  */
-__STATIC_INLINE void SCB_DisableDCache (void)
-{
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-                                            /* clean & invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-      do {
-        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
-                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
-        #if defined ( __CC_ARM )
-          __schedule_barrier();
-        #endif
-      } while (ways-- != 0U);
-    } while(sets-- != 0U);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Invalidate D-Cache
-  \details Invalidates D-Cache
-  */
-__STATIC_INLINE void SCB_InvalidateDCache (void)
-{
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-                                            /* invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-      do {
-        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
-                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
-        #if defined ( __CC_ARM )
-          __schedule_barrier();
-        #endif
-      } while (ways-- != 0U);
-    } while(sets-- != 0U);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Clean D-Cache
-  \details Cleans D-Cache
-  */
-__STATIC_INLINE void SCB_CleanDCache (void)
-{
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-   __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-                                            /* clean D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-      do {
-        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
-                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
-        #if defined ( __CC_ARM )
-          __schedule_barrier();
-        #endif
-      } while (ways-- != 0U);
-    } while(sets-- != 0U);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   Clean & Invalidate D-Cache
-  \details Cleans and Invalidates D-Cache
-  */
-__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
-{
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-    uint32_t ccsidr;
-    uint32_t sets;
-    uint32_t ways;
-
-    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
-    __DSB();
-
-    ccsidr = SCB->CCSIDR;
-
-                                            /* clean & invalidate D-Cache */
-    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
-    do {
-      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
-      do {
-        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
-                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
-        #if defined ( __CC_ARM )
-          __schedule_barrier();
-        #endif
-      } while (ways-- != 0U);
-    } while(sets-- != 0U);
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   D-Cache Invalidate by address
-  \details Invalidates D-Cache for the given address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-     int32_t op_size = dsize;
-    uint32_t op_addr = (uint32_t)addr;
-     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
-    __DSB();
-
-    while (op_size > 0) {
-      SCB->DCIMVAC = op_addr;
-      op_addr += (uint32_t)linesize;
-      op_size -=           linesize;
-    }
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   D-Cache Clean by address
-  \details Cleans D-Cache for the given address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-     int32_t op_size = dsize;
-    uint32_t op_addr = (uint32_t) addr;
-     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
-    __DSB();
-
-    while (op_size > 0) {
-      SCB->DCCMVAC = op_addr;
-      op_addr += (uint32_t)linesize;
-      op_size -=           linesize;
-    }
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/**
-  \brief   D-Cache Clean and Invalidate by address
-  \details Cleans and invalidates D_Cache for the given address
-  \param[in]   addr    address (aligned to 32-byte boundary)
-  \param[in]   dsize   size of memory block (in number of bytes)
-*/
-__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
-{
-  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
-     int32_t op_size = dsize;
-    uint32_t op_addr = (uint32_t) addr;
-     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
-
-    __DSB();
-
-    while (op_size > 0) {
-      SCB->DCCIMVAC = op_addr;
-      op_addr += (uint32_t)linesize;
-      op_size -=           linesize;
-    }
-
-    __DSB();
-    __ISB();
-  #endif
-}
-
-
-/*@} end of CMSIS_Core_CacheFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM7_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
+/**************************************************************************//**
+ * @file     core_cm7.h
+ * @brief    CMSIS Cortex-M7 Core Peripheral Access Layer Header File
+ * @version  V5.0.8
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM7_H_GENERIC
+#define __CORE_CM7_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M7
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/* CMSIS CM7 definitions */
+#define __CM7_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                  /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM7_CMSIS_VERSION_SUB   ( __CM_CMSIS_VERSION_SUB)                  /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM7_CMSIS_VERSION       ((__CM7_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM7_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                (7U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM7_H_DEPENDANT
+#define __CORE_CM7_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM7_REV
+    #define __CM7_REV               0x0000U
+    #warning "__CM7_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __ICACHE_PRESENT
+    #define __ICACHE_PRESENT          0U
+    #warning "__ICACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DCACHE_PRESENT
+    #define __DCACHE_PRESENT          0U
+    #warning "__DCACHE_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DTCM_PRESENT
+    #define __DTCM_PRESENT            0U
+    #warning "__DTCM_PRESENT        not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M7 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_AFR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MFR[4U];             /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[5U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED3[93U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+        uint32_t RESERVED7[6U];
+  __IOM uint32_t ITCMCR;                 /*!< Offset: 0x290 (R/W)  Instruction Tightly-Coupled Memory Control Register */
+  __IOM uint32_t DTCMCR;                 /*!< Offset: 0x294 (R/W)  Data Tightly-Coupled Memory Control Registers */
+  __IOM uint32_t AHBPCR;                 /*!< Offset: 0x298 (R/W)  AHBP Control Register */
+  __IOM uint32_t CACR;                   /*!< Offset: 0x29C (R/W)  L1 Cache Control Register */
+  __IOM uint32_t AHBSCR;                 /*!< Offset: 0x2A0 (R/W)  AHB Slave Control Register */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t ABFSR;                  /*!< Offset: 0x2A8 (R/W)  Auxiliary Bus Fault Status Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                      18U                                           /*!< SCB CCR: Branch prediction enable bit Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: Branch prediction enable bit Mask */
+
+#define SCB_CCR_IC_Pos                      17U                                           /*!< SCB CCR: Instruction cache enable bit Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: Instruction cache enable bit Mask */
+
+#define SCB_CCR_DC_Pos                      16U                                           /*!< SCB CCR: Cache enable bit Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: Cache enable bit Mask */
+
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/* Instruction Tightly-Coupled Memory Control Register Definitions */
+#define SCB_ITCMCR_SZ_Pos                   3U                                            /*!< SCB ITCMCR: SZ Position */
+#define SCB_ITCMCR_SZ_Msk                  (0xFUL << SCB_ITCMCR_SZ_Pos)                   /*!< SCB ITCMCR: SZ Mask */
+
+#define SCB_ITCMCR_RETEN_Pos                2U                                            /*!< SCB ITCMCR: RETEN Position */
+#define SCB_ITCMCR_RETEN_Msk               (1UL << SCB_ITCMCR_RETEN_Pos)                  /*!< SCB ITCMCR: RETEN Mask */
+
+#define SCB_ITCMCR_RMW_Pos                  1U                                            /*!< SCB ITCMCR: RMW Position */
+#define SCB_ITCMCR_RMW_Msk                 (1UL << SCB_ITCMCR_RMW_Pos)                    /*!< SCB ITCMCR: RMW Mask */
+
+#define SCB_ITCMCR_EN_Pos                   0U                                            /*!< SCB ITCMCR: EN Position */
+#define SCB_ITCMCR_EN_Msk                  (1UL /*<< SCB_ITCMCR_EN_Pos*/)                 /*!< SCB ITCMCR: EN Mask */
+
+/* Data Tightly-Coupled Memory Control Register Definitions */
+#define SCB_DTCMCR_SZ_Pos                   3U                                            /*!< SCB DTCMCR: SZ Position */
+#define SCB_DTCMCR_SZ_Msk                  (0xFUL << SCB_DTCMCR_SZ_Pos)                   /*!< SCB DTCMCR: SZ Mask */
+
+#define SCB_DTCMCR_RETEN_Pos                2U                                            /*!< SCB DTCMCR: RETEN Position */
+#define SCB_DTCMCR_RETEN_Msk               (1UL << SCB_DTCMCR_RETEN_Pos)                   /*!< SCB DTCMCR: RETEN Mask */
+
+#define SCB_DTCMCR_RMW_Pos                  1U                                            /*!< SCB DTCMCR: RMW Position */
+#define SCB_DTCMCR_RMW_Msk                 (1UL << SCB_DTCMCR_RMW_Pos)                    /*!< SCB DTCMCR: RMW Mask */
+
+#define SCB_DTCMCR_EN_Pos                   0U                                            /*!< SCB DTCMCR: EN Position */
+#define SCB_DTCMCR_EN_Msk                  (1UL /*<< SCB_DTCMCR_EN_Pos*/)                 /*!< SCB DTCMCR: EN Mask */
+
+/* AHBP Control Register Definitions */
+#define SCB_AHBPCR_SZ_Pos                   1U                                            /*!< SCB AHBPCR: SZ Position */
+#define SCB_AHBPCR_SZ_Msk                  (7UL << SCB_AHBPCR_SZ_Pos)                     /*!< SCB AHBPCR: SZ Mask */
+
+#define SCB_AHBPCR_EN_Pos                   0U                                            /*!< SCB AHBPCR: EN Position */
+#define SCB_AHBPCR_EN_Msk                  (1UL /*<< SCB_AHBPCR_EN_Pos*/)                 /*!< SCB AHBPCR: EN Mask */
+
+/* L1 Cache Control Register Definitions */
+#define SCB_CACR_FORCEWT_Pos                2U                                            /*!< SCB CACR: FORCEWT Position */
+#define SCB_CACR_FORCEWT_Msk               (1UL << SCB_CACR_FORCEWT_Pos)                  /*!< SCB CACR: FORCEWT Mask */
+
+#define SCB_CACR_ECCEN_Pos                  1U                                            /*!< SCB CACR: ECCEN Position */
+#define SCB_CACR_ECCEN_Msk                 (1UL << SCB_CACR_ECCEN_Pos)                    /*!< SCB CACR: ECCEN Mask */
+
+#define SCB_CACR_SIWT_Pos                   0U                                            /*!< SCB CACR: SIWT Position */
+#define SCB_CACR_SIWT_Msk                  (1UL /*<< SCB_CACR_SIWT_Pos*/)                 /*!< SCB CACR: SIWT Mask */
+
+/* AHBS Control Register Definitions */
+#define SCB_AHBSCR_INITCOUNT_Pos           11U                                            /*!< SCB AHBSCR: INITCOUNT Position */
+#define SCB_AHBSCR_INITCOUNT_Msk           (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)           /*!< SCB AHBSCR: INITCOUNT Mask */
+
+#define SCB_AHBSCR_TPRI_Pos                 2U                                            /*!< SCB AHBSCR: TPRI Position */
+#define SCB_AHBSCR_TPRI_Msk                (0x1FFUL << SCB_AHBPCR_TPRI_Pos)               /*!< SCB AHBSCR: TPRI Mask */
+
+#define SCB_AHBSCR_CTL_Pos                  0U                                            /*!< SCB AHBSCR: CTL Position*/
+#define SCB_AHBSCR_CTL_Msk                 (3UL /*<< SCB_AHBPCR_CTL_Pos*/)                /*!< SCB AHBSCR: CTL Mask */
+
+/* Auxiliary Bus Fault Status Register Definitions */
+#define SCB_ABFSR_AXIMTYPE_Pos              8U                                            /*!< SCB ABFSR: AXIMTYPE Position*/
+#define SCB_ABFSR_AXIMTYPE_Msk             (3UL << SCB_ABFSR_AXIMTYPE_Pos)                /*!< SCB ABFSR: AXIMTYPE Mask */
+
+#define SCB_ABFSR_EPPB_Pos                  4U                                            /*!< SCB ABFSR: EPPB Position*/
+#define SCB_ABFSR_EPPB_Msk                 (1UL << SCB_ABFSR_EPPB_Pos)                    /*!< SCB ABFSR: EPPB Mask */
+
+#define SCB_ABFSR_AXIM_Pos                  3U                                            /*!< SCB ABFSR: AXIM Position*/
+#define SCB_ABFSR_AXIM_Msk                 (1UL << SCB_ABFSR_AXIM_Pos)                    /*!< SCB ABFSR: AXIM Mask */
+
+#define SCB_ABFSR_AHBP_Pos                  2U                                            /*!< SCB ABFSR: AHBP Position*/
+#define SCB_ABFSR_AHBP_Msk                 (1UL << SCB_ABFSR_AHBP_Pos)                    /*!< SCB ABFSR: AHBP Mask */
+
+#define SCB_ABFSR_DTCM_Pos                  1U                                            /*!< SCB ABFSR: DTCM Position*/
+#define SCB_ABFSR_DTCM_Msk                 (1UL << SCB_ABFSR_DTCM_Pos)                    /*!< SCB ABFSR: DTCM Mask */
+
+#define SCB_ABFSR_ITCM_Pos                  0U                                            /*!< SCB ABFSR: ITCM Position*/
+#define SCB_ABFSR_ITCM_Msk                 (1UL /*<< SCB_ABFSR_ITCM_Pos*/)                /*!< SCB ABFSR: ITCM Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos    12U                                         /*!< ACTLR: DISITMATBFLUSH Position */
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk    (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos)    /*!< ACTLR: DISITMATBFLUSH Mask */
+
+#define SCnSCB_ACTLR_DISRAMODE_Pos         11U                                         /*!< ACTLR: DISRAMODE Position */
+#define SCnSCB_ACTLR_DISRAMODE_Msk         (1UL << SCnSCB_ACTLR_DISRAMODE_Pos)         /*!< ACTLR: DISRAMODE Mask */
+
+#define SCnSCB_ACTLR_FPEXCODIS_Pos         10U                                         /*!< ACTLR: FPEXCODIS Position */
+#define SCnSCB_ACTLR_FPEXCODIS_Msk         (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos)         /*!< ACTLR: FPEXCODIS Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED3[981U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 (  W)  Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x018 (R/ )  Media and FP Feature Register 2 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/* Media and FP Feature Register 2 Definitions */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define FPU_BASE            (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+#define FPU                 ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+#define EXC_RETURN_HANDLER_FPU     (0xFFFFFFE1UL)     /* return to Handler mode, uses MSP after return, restore floating-point state */
+#define EXC_RETURN_THREAD_MSP_FPU  (0xFFFFFFE9UL)     /* return to Thread mode, uses MSP after return, restore floating-point state  */
+#define EXC_RETURN_THREAD_PSP_FPU  (0xFFFFFFEDUL)     /* return to Thread mode, uses PSP after return, restore floating-point state  */
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]                = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]                >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv7.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = SCB->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################  Cache functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_CacheFunctions Cache Functions
+  \brief    Functions that configure Instruction and Data cache.
+  @{
+ */
+
+/* Cache Size ID Register Macros */
+#define CCSIDR_WAYS(x)         (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
+#define CCSIDR_SETS(x)         (((x) & SCB_CCSIDR_NUMSETS_Msk      ) >> SCB_CCSIDR_NUMSETS_Pos      )
+
+
+/**
+  \brief   Enable I-Cache
+  \details Turns on I-Cache
+  */
+__STATIC_INLINE void SCB_EnableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable I-Cache
+  \details Turns off I-Cache
+  */
+__STATIC_INLINE void SCB_DisableICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
+    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate I-Cache
+  \details Invalidates I-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateICache (void)
+{
+  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+    __DSB();
+    __ISB();
+    SCB->ICIALLU = 0UL;
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Enable D-Cache
+  \details Turns on D-Cache
+  */
+__STATIC_INLINE void SCB_EnableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+    __DSB();
+
+    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Disable D-Cache
+  \details Turns off D-Cache
+  */
+__STATIC_INLINE void SCB_DisableDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Invalidate D-Cache
+  \details Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_InvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
+                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean D-Cache
+  \details Cleans D-Cache
+  */
+__STATIC_INLINE void SCB_CleanDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+   __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
+                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   Clean & Invalidate D-Cache
+  \details Cleans and Invalidates D-Cache
+  */
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    uint32_t ccsidr;
+    uint32_t sets;
+    uint32_t ways;
+
+    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
+    __DSB();
+
+    ccsidr = SCB->CCSIDR;
+
+                                            /* clean & invalidate D-Cache */
+    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
+    do {
+      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
+      do {
+        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
+                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
+        #if defined ( __CC_ARM )
+          __schedule_barrier();
+        #endif
+      } while (ways-- != 0U);
+    } while(sets-- != 0U);
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Invalidate by address
+  \details Invalidates D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t)addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean by address
+  \details Cleans D-Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/**
+  \brief   D-Cache Clean and Invalidate by address
+  \details Cleans and invalidates D_Cache for the given address
+  \param[in]   addr    address (aligned to 32-byte boundary)
+  \param[in]   dsize   size of memory block (in number of bytes)
+*/
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
+{
+  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+     int32_t op_size = dsize;
+    uint32_t op_addr = (uint32_t) addr;
+     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
+
+    __DSB();
+
+    while (op_size > 0) {
+      SCB->DCCIMVAC = op_addr;
+      op_addr += (uint32_t)linesize;
+      op_size -=           linesize;
+    }
+
+    __DSB();
+    __ISB();
+  #endif
+}
+
+
+/*@} end of CMSIS_Core_CacheFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM7_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_sc000.h b/Drivers/CMSIS/Include/core_sc000.h
index 9b67c92..9086c64 100644
--- a/Drivers/CMSIS/Include/core_sc000.h
+++ b/Drivers/CMSIS/Include/core_sc000.h
@@ -1,1022 +1,1022 @@
-/**************************************************************************//**
- * @file     core_sc000.h
- * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
- * @version  V5.0.5
- * @date     28. May 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_SC000_H_GENERIC
-#define __CORE_SC000_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup SC000
-  @{
- */
-
-#include "cmsis_version.h"
-
-/*  CMSIS SC000 definitions */
-#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
-                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC000_H_DEPENDANT
-#define __CORE_SC000_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __SC000_REV
-    #define __SC000_REV             0x0000U
-    #warning "__SC000_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          2U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group SC000 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
-    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[31U];
-  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[31U];
-  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[31U];
-  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[31U];
-        uint32_t RESERVED4[64U];
-  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
-}  NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-        uint32_t RESERVED1[154U];
-  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
-            Therefore they are not covered by the SC000 header file.
-  @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
-/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
-
-
-/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
-#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
-#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-  else
-  {
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC000_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
+/**************************************************************************//**
+ * @file     core_sc000.h
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
+ * @version  V5.0.5
+ * @date     28. May 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC000_H_GENERIC
+#define __CORE_SC000_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC000 definitions */
+#define __SC000_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC000_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC000_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (000U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC000_H_DEPENDANT
+#define __CORE_SC000_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC000_REV
+    #define __SC000_REV             0x0000U
+    #warning "__SC000_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC000 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[1U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[31U];
+  __IOM uint32_t ICER[1U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[31U];
+  __IOM uint32_t ISPR[1U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[31U];
+  __IOM uint32_t ICPR[1U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[31U];
+        uint32_t RESERVED4[64U];
+  __IOM uint32_t IP[8U];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t SHP[2U];                /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+        uint32_t RESERVED1[154U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   8U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
+            Therefore they are not covered by the SC000 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/*#define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping   not available for SC000 */
+/*#define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping   not available for SC000 */
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+/*#define NVIC_GetActive              __NVIC_GetActive             not available for SC000 */
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+/* Interrupt Priorities are WORD accessible only under Armv6-M                  */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+  else
+  {
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC000_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/core_sc300.h b/Drivers/CMSIS/Include/core_sc300.h
index 3e8a471..665822d 100644
--- a/Drivers/CMSIS/Include/core_sc300.h
+++ b/Drivers/CMSIS/Include/core_sc300.h
@@ -1,1915 +1,1915 @@
-/**************************************************************************//**
- * @file     core_sc300.h
- * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
- * @version  V5.0.6
- * @date     04. June 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef __CORE_SC300_H_GENERIC
-#define __CORE_SC300_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
-  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
-  CMSIS violates the following MISRA-C:2004 rules:
-
-   \li Required Rule 8.5, object/function definition in header file.<br>
-     Function definitions in header files are used to allow 'inlining'.
-
-   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
-     Unions are used for effective representation of core registers.
-
-   \li Advisory Rule 19.7, Function-like macro defined.<br>
-     Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- *                 CMSIS definitions
- ******************************************************************************/
-/**
-  \ingroup SC3000
-  @{
- */
-
-#include "cmsis_version.h"
-
-/*  CMSIS SC300 definitions */
-#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
-#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
-#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
-                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
-
-#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
-
-/** __FPU_USED indicates whether an FPU is used or not.
-    This core does not support an FPU at all
-*/
-#define __FPU_USED       0U
-
-#if defined ( __CC_ARM )
-  #if defined __TARGET_FPU_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-  #if defined __ARM_PCS_VFP
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __GNUC__ )
-  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __ICCARM__ )
-  #if defined __ARMVFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TI_ARM__ )
-  #if defined __TI_VFP_SUPPORT__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __TASKING__ )
-  #if defined __FPU_VFP__
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#elif defined ( __CSMC__ )
-  #if ( __CSMC__ & 0x400U)
-    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
-  #endif
-
-#endif
-
-#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC300_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC300_H_DEPENDANT
-#define __CORE_SC300_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
-  #ifndef __SC300_REV
-    #define __SC300_REV               0x0000U
-    #warning "__SC300_REV not defined in device header file; using default!"
-  #endif
-
-  #ifndef __MPU_PRESENT
-    #define __MPU_PRESENT             0U
-    #warning "__MPU_PRESENT not defined in device header file; using default!"
-  #endif
-
-  #ifndef __NVIC_PRIO_BITS
-    #define __NVIC_PRIO_BITS          3U
-    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
-  #endif
-
-  #ifndef __Vendor_SysTickConfig
-    #define __Vendor_SysTickConfig    0U
-    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
-  #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
-    \defgroup CMSIS_glob_defs CMSIS Global Defines
-
-    <strong>IO Type Qualifiers</strong> are used
-    \li to specify the access to peripheral variables.
-    \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
-  #define   __I     volatile             /*!< Defines 'read only' permissions */
-#else
-  #define   __I     volatile const       /*!< Defines 'read only' permissions */
-#endif
-#define     __O     volatile             /*!< Defines 'write only' permissions */
-#define     __IO    volatile             /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
-#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
-#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group SC300 */
-
-
-
-/*******************************************************************************
- *                 Register Abstraction
-  Core Register contain:
-  - Core Register
-  - Core NVIC Register
-  - Core SCB Register
-  - Core SysTick Register
-  - Core Debug Register
-  - Core MPU Register
- ******************************************************************************/
-/**
-  \defgroup CMSIS_core_register Defines and Type Definitions
-  \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_CORE  Status and Control Registers
-  \brief      Core Register type definitions.
-  @{
- */
-
-/**
-  \brief  Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
-#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
-
-#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
-#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
-
-#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
-#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
-
-#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
-#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
-
-#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
-#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
-
-
-/**
-  \brief  Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
-    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
-    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
-    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
-    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
-    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
-    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
-    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
-    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
-    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
-    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
-#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
-#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
-#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
-#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
-#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
-
-#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
-#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
-
-#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
-#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
-
-#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
-#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
-
-#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
-
-
-/**
-  \brief  Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
-  struct
-  {
-    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
-    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
-    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
-  } b;                                   /*!< Structure used for bit  access */
-  uint32_t w;                            /*!< Type      used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
-  \brief      Type definitions for the NVIC Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
-  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
-        uint32_t RESERVED0[24U];
-  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
-        uint32_t RSERVED1[24U];
-  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
-        uint32_t RESERVED2[24U];
-  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
-        uint32_t RESERVED3[24U];
-  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
-        uint32_t RESERVED4[56U];
-  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
-        uint32_t RESERVED5[644U];
-  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
-}  NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCB     System Control Block (SCB)
-  \brief    Type definitions for the System Control Block Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
-  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
-  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
-  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
-  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
-  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
-  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
-  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
-  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
-  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
-  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
-  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
-  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
-  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
-  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
-  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
-  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
-  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
-  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
-  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
-        uint32_t RESERVED0[5U];
-  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
-        uint32_t RESERVED1[129U];
-  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
-#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
-
-#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
-#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
-
-#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
-#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
-
-#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
-#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
-
-#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
-#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
-
-/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
-#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
-
-#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
-#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
-
-#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
-#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
-
-#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
-#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
-
-#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
-#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
-
-#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
-#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
-
-/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
-#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
-#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
-
-#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
-#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
-
-#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
-#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
-
-#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
-#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
-
-#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
-#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
-
-#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
-#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
-  \brief    Type definitions for the System Control and ID Register not in the SCB
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
-        uint32_t RESERVED0[1U];
-  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
-        uint32_t RESERVED1[1U];
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
-  \brief    Type definitions for the System Timer Registers.
-  @{
- */
-
-/**
-  \brief  Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
-  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
-  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
-  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
-  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
-  __OM  union
-  {
-    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
-    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
-    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
-  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
-        uint32_t RESERVED0[864U];
-  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
-        uint32_t RESERVED1[15U];
-  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
-        uint32_t RESERVED2[15U];
-  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
-        uint32_t RESERVED3[29U];
-  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
-  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
-  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
-        uint32_t RESERVED4[43U];
-  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
-  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
-        uint32_t RESERVED5[6U];
-  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
-  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
-  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
-  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
-  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
-  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
-  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
-  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
-  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
-  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
-  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
-  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
-  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
-  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
-  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
-  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
-  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
-  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
-  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
-  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
-  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
-  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
-  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
-        uint32_t RESERVED0[1U];
-  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
-  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
-  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
-        uint32_t RESERVED1[1U];
-  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
-  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
-  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
-        uint32_t RESERVED2[1U];
-  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
-  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
-  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
-  \brief    Type definitions for the Trace Port Interface (TPI)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
-  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
-  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
-        uint32_t RESERVED0[2U];
-  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
-        uint32_t RESERVED1[55U];
-  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
-        uint32_t RESERVED2[131U];
-  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
-  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
-  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
-        uint32_t RESERVED3[759U];
-  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
-  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
-  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
-        uint32_t RESERVED4[1U];
-  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
-  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
-  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
-        uint32_t RESERVED5[39U];
-  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
-  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
-        uint32_t RESERVED7[8U];
-  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
-  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
-#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
-
-#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
-#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
-#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
-
-#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
-#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
-  \brief    Type definitions for the Memory Protection Unit (MPU)
-  @{
- */
-
-/**
-  \brief  Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
-  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
-  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
-  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
-  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
-  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
-  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
-  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
-  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
-  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/**
-  \ingroup  CMSIS_core_register
-  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
-  \brief    Type definitions for the Core Debug Registers
-  @{
- */
-
-/**
-  \brief  Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
-  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
-  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
-  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
-  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_bitfield     Core register bit field macros
-  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
-  @{
- */
-
-/**
-  \brief   Mask and shift a bit field value for use in a register bit range.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted value.
-*/
-#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
-
-/**
-  \brief     Mask and shift a register value to extract a bit filed value.
-  \param[in] field  Name of the register bit field.
-  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
-  \return           Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
-  \ingroup    CMSIS_core_register
-  \defgroup   CMSIS_core_base     Core Definitions
-  \brief      Definitions for base addresses, unions, and structures.
-  @{
- */
-
-/* Memory mapping of Core Hardware */
-#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
-#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
-#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
-#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
-#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
-#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
-#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
-#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
-
-#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
-#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
-#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
-#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
-#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
-#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
-#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
-#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
-  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
-  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- *                Hardware Abstraction Layer
-  Core Function Interface contains:
-  - Core NVIC Functions
-  - Core SysTick Functions
-  - Core Debug Functions
-  - Core Register Access Functions
- ******************************************************************************/
-/**
-  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ##########################   NVIC functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
-  \brief    Functions that manage interrupts and exceptions via the NVIC.
-  @{
- */
-
-#ifdef CMSIS_NVIC_VIRTUAL
-  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
-    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
-  #endif
-  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
-  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
-  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
-  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
-  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
-  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
-  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
-  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
-  #define NVIC_GetActive              __NVIC_GetActive
-  #define NVIC_SetPriority            __NVIC_SetPriority
-  #define NVIC_GetPriority            __NVIC_GetPriority
-  #define NVIC_SystemReset            __NVIC_SystemReset
-#endif /* CMSIS_NVIC_VIRTUAL */
-
-#ifdef CMSIS_VECTAB_VIRTUAL
-  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
-  #endif
-  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
-#else
-  #define NVIC_SetVector              __NVIC_SetVector
-  #define NVIC_GetVector              __NVIC_GetVector
-#endif  /* (CMSIS_VECTAB_VIRTUAL) */
-
-#define NVIC_USER_IRQ_OFFSET          16
-
-
-/* The following EXC_RETURN values are saved the LR on exception entry */
-#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
-#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
-#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
-
-
-
-/**
-  \brief   Set Priority Grouping
-  \details Sets the priority grouping field using the required unlock sequence.
-           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
-           Only values from 0..7 are used.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]      PriorityGroup  Priority grouping field.
- */
-__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  uint32_t reg_value;
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
-
-  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
-  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
-  reg_value  =  (reg_value                                   |
-                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
-                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
-  SCB->AIRCR =  reg_value;
-}
-
-
-/**
-  \brief   Get Priority Grouping
-  \details Reads the priority grouping field from the NVIC Interrupt Controller.
-  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
-{
-  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
-  \brief   Enable Interrupt
-  \details Enables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Enable status
-  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt is not enabled.
-  \return             1  Interrupt is enabled.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Disable Interrupt
-  \details Disables a device specific interrupt in the NVIC interrupt controller.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-    __DSB();
-    __ISB();
-  }
-}
-
-
-/**
-  \brief   Get Pending Interrupt
-  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not pending.
-  \return             1  Interrupt status is pending.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Pending Interrupt
-  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
-  \param [in]      IRQn  Device specific interrupt number.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
-  }
-}
-
-
-/**
-  \brief   Get Active Interrupt
-  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
-  \param [in]      IRQn  Device specific interrupt number.
-  \return             0  Interrupt status is not active.
-  \return             1  Interrupt status is active.
-  \note    IRQn must not be negative.
- */
-__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-  }
-  else
-  {
-    return(0U);
-  }
-}
-
-
-/**
-  \brief   Set Interrupt Priority
-  \details Sets the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]      IRQn  Interrupt number.
-  \param [in]  priority  Priority to set.
-  \note    The priority cannot be set for every processor exception.
- */
-__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
-  if ((int32_t)(IRQn) >= 0)
-  {
-    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-  else
-  {
-    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
-  }
-}
-
-
-/**
-  \brief   Get Interrupt Priority
-  \details Reads the priority of a device specific interrupt or a processor exception.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn  Interrupt number.
-  \return             Interrupt Priority.
-                      Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
-{
-
-  if ((int32_t)(IRQn) >= 0)
-  {
-    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
-  }
-  else
-  {
-    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
-  }
-}
-
-
-/**
-  \brief   Encode Priority
-  \details Encodes the priority for an interrupt with the given priority group,
-           preemptive priority value, and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-  \param [in]     PriorityGroup  Used priority group.
-  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
-  \param [in]       SubPriority  Subpriority value (starting from 0).
-  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  return (
-           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
-           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
-         );
-}
-
-
-/**
-  \brief   Decode Priority
-  \details Decodes an interrupt priority value with a given priority group to
-           preemptive priority value and subpriority value.
-           In case of a conflict between priority grouping and available
-           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
-  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
-  \param [in]     PriorityGroup  Used priority group.
-  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
-  \param [out]     pSubPriority  Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
-  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
-  uint32_t PreemptPriorityBits;
-  uint32_t SubPriorityBits;
-
-  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
-  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
-  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
-  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
-}
-
-
-/**
-  \brief   Set Interrupt Vector
-  \details Sets an interrupt vector in SRAM based interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-           VTOR must been relocated to SRAM before.
-  \param [in]   IRQn      Interrupt number
-  \param [in]   vector    Address of interrupt handler function
- */
-__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-
-/**
-  \brief   Get Interrupt Vector
-  \details Reads an interrupt vector from interrupt vector table.
-           The interrupt number can be positive to specify a device specific interrupt,
-           or negative to specify a processor exception.
-  \param [in]   IRQn      Interrupt number.
-  \return                 Address of interrupt handler function
- */
-__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
-{
-  uint32_t *vectors = (uint32_t *)SCB->VTOR;
-  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
-}
-
-
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
-                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
-                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
-  }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-/* ##########################  FPU functions  #################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_FpuFunctions FPU Functions
-  \brief    Function that provides FPU type.
-  @{
- */
-
-/**
-  \brief   get FPU type
-  \details returns the FPU type
-  \returns
-   - \b  0: No FPU
-   - \b  1: Single precision FPU
-   - \b  2: Double + Single precision FPU
- */
-__STATIC_INLINE uint32_t SCB_GetFPUType(void)
-{
-    return 0U;           /* No FPU */
-}
-
-
-/*@} end of CMSIS_Core_FpuFunctions */
-
-
-
-/* ##################################    SysTick function  ############################################ */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
-  \brief    Functions that configure the System.
-  @{
- */
-
-#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
-
-/**
-  \brief   System Tick Configuration
-  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-           Counter is in free running mode to generate periodic interrupts.
-  \param [in]  ticks  Number of ticks between two interrupts.
-  \return          0  Function succeeded.
-  \return          1  Function failed.
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
-  {
-    return (1UL);                                                   /* Reload value impossible */
-  }
-
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
-  \ingroup  CMSIS_Core_FunctionInterface
-  \defgroup CMSIS_core_DebugFunctions ITM Functions
-  \brief    Functions that access the ITM debug interface.
-  @{
- */
-
-extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
-#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
-  \brief   ITM Send Character
-  \details Transmits a character via the ITM channel 0, and
-           \li Just returns when no debugger is connected that has booked the output.
-           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-  \param [in]     ch  Character to transmit.
-  \returns            Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
-  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
-      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
-  {
-    while (ITM->PORT[0U].u32 == 0UL)
-    {
-      __NOP();
-    }
-    ITM->PORT[0U].u8 = (uint8_t)ch;
-  }
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Receive Character
-  \details Inputs a character via the external variable \ref ITM_RxBuffer.
-  \return             Received character.
-  \return         -1  No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
-  int32_t ch = -1;                           /* no character available */
-
-  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
-  {
-    ch = ITM_RxBuffer;
-    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
-  }
-
-  return (ch);
-}
-
-
-/**
-  \brief   ITM Check Character
-  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-  \return          0  No character available.
-  \return          1  Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
-  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
-  {
-    return (0);                              /* no character available */
-  }
-  else
-  {
-    return (1);                              /*    character available */
-  }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_SC300_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
+/**************************************************************************//**
+ * @file     core_sc300.h
+ * @brief    CMSIS SC300 Core Peripheral Access Layer Header File
+ * @version  V5.0.6
+ * @date     04. June 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_SC300_H_GENERIC
+#define __CORE_SC300_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup SC3000
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS SC300 definitions */
+#define __SC300_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __SC300_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                 /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __SC300_CMSIS_VERSION       ((__SC300_CMSIS_VERSION_MAIN << 16U) | \
+                                      __SC300_CMSIS_VERSION_SUB           )  /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_SC                 (300U)                                   /*!< Cortex secure core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    This core does not support an FPU at all
+*/
+#define __FPU_USED       0U
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined __TI_VFP_SUPPORT__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_SC300_H_DEPENDANT
+#define __CORE_SC300_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __SC300_REV
+    #define __SC300_REV               0x0000U
+    #warning "__SC300_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group SC300 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:1;               /*!< bit:      9  Reserved */
+    uint32_t ICI_IT_1:6;                 /*!< bit: 10..15  ICI/IT part 1 */
+    uint32_t _reserved1:8;               /*!< bit: 16..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit */
+    uint32_t ICI_IT_2:2;                 /*!< bit: 25..26  ICI/IT part 2 */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_ICI_IT_2_Pos                  25U                                            /*!< xPSR: ICI/IT part 2 Position */
+#define xPSR_ICI_IT_2_Msk                  (3UL << xPSR_ICI_IT_2_Pos)                     /*!< xPSR: ICI/IT part 2 Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_ICI_IT_1_Pos                  10U                                            /*!< xPSR: ICI/IT part 1 Position */
+#define xPSR_ICI_IT_1_Msk                  (0x3FUL << xPSR_ICI_IT_1_Pos)                  /*!< xPSR: ICI/IT part 1 Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+        uint32_t RESERVED1[129U];
+  __IOM uint32_t SFCR;                   /*!< Offset: 0x290 (R/W)  Security Features Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29U                                            /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+        uint32_t RESERVED1[1U];
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY2 Position */
+#define TPI_ITATBCTR2_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)   /*!< TPI ITATBCTR2: ATREADY2 Mask */
+
+#define TPI_ITATBCTR2_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR2: ATREADY1 Position */
+#define TPI_ITATBCTR2_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)   /*!< TPI ITATBCTR2: ATREADY1 Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY2_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY2 Position */
+#define TPI_ITATBCTR0_ATREADY2_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)   /*!< TPI ITATBCTR0: ATREADY2 Mask */
+
+#define TPI_ITATBCTR0_ATREADY1_Pos          0U                                         /*!< TPI ITATBCTR0: ATREADY1 Position */
+#define TPI_ITATBCTR0_ATREADY1_Msk         (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)   /*!< TPI ITATBCTR0: ATREADY1 Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* The following EXC_RETURN values are saved the LR on exception entry */
+#define EXC_RETURN_HANDLER         (0xFFFFFFF1UL)     /* return to Handler mode, uses MSP after return                               */
+#define EXC_RETURN_THREAD_MSP      (0xFFFFFFF9UL)     /* return to Thread mode, uses MSP after return                                */
+#define EXC_RETURN_THREAD_PSP      (0xFFFFFFFDUL)     /* return to Thread mode, uses PSP after return                                */
+
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+    return 0U;           /* No FPU */
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_SC300_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
diff --git a/Drivers/CMSIS/Include/mpu_armv7.h b/Drivers/CMSIS/Include/mpu_armv7.h
index 0142203..7d4b600 100644
--- a/Drivers/CMSIS/Include/mpu_armv7.h
+++ b/Drivers/CMSIS/Include/mpu_armv7.h
@@ -1,270 +1,270 @@
-/******************************************************************************
- * @file     mpu_armv7.h
- * @brief    CMSIS MPU API for Armv7-M MPU
- * @version  V5.0.4
- * @date     10. January 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
- 
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header    /* treat file as system include file */
-#endif
- 
-#ifndef ARM_MPU_ARMV7_H
-#define ARM_MPU_ARMV7_H
-
-#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
-#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
-#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
-#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
-#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
-#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
-#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
-#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
-#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
-#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
-#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
-#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
-#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
-#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
-#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
-#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
-#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
-#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
-#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
-#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
-#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
-#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
-#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
-#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
-#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
-#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
-#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
-#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
-
-#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
-#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
-#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
-#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
-#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
-#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
-
-/** MPU Region Base Address Register Value
-*
-* \param Region The region to be configured, number 0 to 15.
-* \param BaseAddress The base address for the region.
-*/
-#define ARM_MPU_RBAR(Region, BaseAddress) \
-  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
-   ((Region) & MPU_RBAR_REGION_Msk)    |  \
-   (MPU_RBAR_VALID_Msk))
-
-/**
-* MPU Memory Access Attributes
-* 
-* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
-* \param IsShareable       Region is shareable between multiple bus masters.
-* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
-* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
-*/  
-#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
-  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
-   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
-   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
-   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
-
-/**
-* MPU Region Attribute and Size Register Value
-* 
-* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
-* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
-* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
-* \param SubRegionDisable  Sub-region disable field.
-* \param Size              Region size of the region to be configured, for example 4K, 8K.
-*/
-#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
-  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
-   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
-   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
-  
-/**
-* MPU Region Attribute and Size Register Value
-* 
-* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
-* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
-* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
-* \param IsShareable       Region is shareable between multiple bus masters.
-* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
-* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
-* \param SubRegionDisable  Sub-region disable field.
-* \param Size              Region size of the region to be configured, for example 4K, 8K.
-*/                         
-#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
-  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
-
-/**
-* MPU Memory Access Attribute for strongly ordered memory.
-*  - TEX: 000b
-*  - Shareable
-*  - Non-cacheable
-*  - Non-bufferable
-*/ 
-#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
-
-/**
-* MPU Memory Access Attribute for device memory.
-*  - TEX: 000b (if non-shareable) or 010b (if shareable)
-*  - Shareable or non-shareable
-*  - Non-cacheable
-*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
-*
-* \param IsShareable Configures the device memory as shareable or non-shareable.
-*/ 
-#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
-
-/**
-* MPU Memory Access Attribute for normal memory.
-*  - TEX: 1BBb (reflecting outer cacheability rules)
-*  - Shareable or non-shareable
-*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
-*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
-*
-* \param OuterCp Configures the outer cache policy.
-* \param InnerCp Configures the inner cache policy.
-* \param IsShareable Configures the memory as shareable or non-shareable.
-*/ 
-#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
-
-/**
-* MPU Memory Access Attribute non-cacheable policy.
-*/
-#define ARM_MPU_CACHEP_NOCACHE 0U
-
-/**
-* MPU Memory Access Attribute write-back, write and read allocate policy.
-*/
-#define ARM_MPU_CACHEP_WB_WRA 1U
-
-/**
-* MPU Memory Access Attribute write-through, no write allocate policy.
-*/
-#define ARM_MPU_CACHEP_WT_NWA 2U
-
-/**
-* MPU Memory Access Attribute write-back, no write allocate policy.
-*/
-#define ARM_MPU_CACHEP_WB_NWA 3U
-
-
-/**
-* Struct for a single MPU Region
-*/
-typedef struct {
-  uint32_t RBAR; //!< The region base address register value (RBAR)
-  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
-} ARM_MPU_Region_t;
-    
-/** Enable the MPU.
-* \param MPU_Control Default access permissions for unconfigured regions.
-*/
-__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
-{
-  __DSB();
-  __ISB();
-  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-}
-
-/** Disable the MPU.
-*/
-__STATIC_INLINE void ARM_MPU_Disable(void)
-{
-  __DSB();
-  __ISB();
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
-}
-
-/** Clear and disable the given MPU region.
-* \param rnr Region number to be cleared.
-*/
-__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
-{
-  MPU->RNR = rnr;
-  MPU->RASR = 0U;
-}
-
-/** Configure an MPU region.
-* \param rbar Value for RBAR register.
-* \param rsar Value for RSAR register.
-*/   
-__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
-{
-  MPU->RBAR = rbar;
-  MPU->RASR = rasr;
-}
-
-/** Configure the given MPU region.
-* \param rnr Region number to be configured.
-* \param rbar Value for RBAR register.
-* \param rsar Value for RSAR register.
-*/   
-__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
-{
-  MPU->RNR = rnr;
-  MPU->RBAR = rbar;
-  MPU->RASR = rasr;
-}
-
-/** Memcopy with strictly ordered memory access, e.g. for register targets.
-* \param dst Destination data is copied to.
-* \param src Source data is copied from.
-* \param len Amount of data words to be copied.
-*/
-__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
-{
-  uint32_t i;
-  for (i = 0U; i < len; ++i) 
-  {
-    dst[i] = src[i];
-  }
-}
-
-/** Load the given number of MPU regions from a table.
-* \param table Pointer to the MPU configuration table.
-* \param cnt Amount of regions to be configured.
-*/
-__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
-{
-  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
-  while (cnt > MPU_TYPE_RALIASES) {
-    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
-    table += MPU_TYPE_RALIASES;
-    cnt -= MPU_TYPE_RALIASES;
-  }
-  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
-}
-
-#endif
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                 | \
+   (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk)                      | \
+   (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk)                      | \
+   (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)      \
+  ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk)                                          | \
+   (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk)                                      | \
+   (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
+  
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if non-shareable) or 010b (if shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif
diff --git a/Drivers/CMSIS/Include/mpu_armv8.h b/Drivers/CMSIS/Include/mpu_armv8.h
index 62571da..99ee9f9 100644
--- a/Drivers/CMSIS/Include/mpu_armv8.h
+++ b/Drivers/CMSIS/Include/mpu_armv8.h
@@ -1,333 +1,333 @@
-/******************************************************************************
- * @file     mpu_armv8.h
- * @brief    CMSIS MPU API for Armv8-M MPU
- * @version  V5.0.4
- * @date     10. January 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header    /* treat file as system include file */
-#endif
-
-#ifndef ARM_MPU_ARMV8_H
-#define ARM_MPU_ARMV8_H
-
-/** \brief Attribute for device memory (outer only) */
-#define ARM_MPU_ATTR_DEVICE                           ( 0U )
-
-/** \brief Attribute for non-cacheable, normal memory */
-#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
-
-/** \brief Attribute for normal memory (outer and inner)
-* \param NT Non-Transient: Set to 1 for non-transient data.
-* \param WB Write-Back: Set to 1 to use write-back update policy.
-* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
-* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
-*/
-#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
-  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
-
-/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
-#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
-
-/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
-#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
-
-/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
-#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
-
-/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
-#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
-
-/** \brief Memory Attribute
-* \param O Outer memory attributes
-* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
-*/
-#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
-
-/** \brief Normal memory non-shareable  */
-#define ARM_MPU_SH_NON   (0U)
-
-/** \brief Normal memory outer shareable  */
-#define ARM_MPU_SH_OUTER (2U)
-
-/** \brief Normal memory inner shareable  */
-#define ARM_MPU_SH_INNER (3U)
-
-/** \brief Memory access permissions
-* \param RO Read-Only: Set to 1 for read-only memory.
-* \param NP Non-Privileged: Set to 1 for non-privileged memory.
-*/
-#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
-
-/** \brief Region Base Address Register value
-* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
-* \param SH Defines the Shareability domain for this memory region.
-* \param RO Read-Only: Set to 1 for a read-only memory region.
-* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
-* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
-*/
-#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
-  ((BASE & MPU_RBAR_BASE_Msk) | \
-  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
-  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
-  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
-
-/** \brief Region Limit Address Register value
-* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
-* \param IDX The attribute index to be associated with this memory region.
-*/
-#define ARM_MPU_RLAR(LIMIT, IDX) \
-  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
-  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
-  (MPU_RLAR_EN_Msk))
-
-/**
-* Struct for a single MPU Region
-*/
-typedef struct {
-  uint32_t RBAR;                   /*!< Region Base Address Register value */
-  uint32_t RLAR;                   /*!< Region Limit Address Register value */
-} ARM_MPU_Region_t;
-    
-/** Enable the MPU.
-* \param MPU_Control Default access permissions for unconfigured regions.
-*/
-__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
-{
-  __DSB();
-  __ISB();
-  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-}
-
-/** Disable the MPU.
-*/
-__STATIC_INLINE void ARM_MPU_Disable(void)
-{
-  __DSB();
-  __ISB();
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
-}
-
-#ifdef MPU_NS
-/** Enable the Non-secure MPU.
-* \param MPU_Control Default access permissions for unconfigured regions.
-*/
-__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
-{
-  __DSB();
-  __ISB();
-  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-}
-
-/** Disable the Non-secure MPU.
-*/
-__STATIC_INLINE void ARM_MPU_Disable_NS(void)
-{
-  __DSB();
-  __ISB();
-#ifdef SCB_SHCSR_MEMFAULTENA_Msk
-  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-#endif
-  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
-}
-#endif
-
-/** Set the memory attribute encoding to the given MPU.
-* \param mpu Pointer to the MPU to be configured.
-* \param idx The attribute index to be set [0-7]
-* \param attr The attribute value to be set.
-*/
-__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
-{
-  const uint8_t reg = idx / 4U;
-  const uint32_t pos = ((idx % 4U) * 8U);
-  const uint32_t mask = 0xFFU << pos;
-  
-  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
-    return; // invalid index
-  }
-  
-  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
-}
-
-/** Set the memory attribute encoding.
-* \param idx The attribute index to be set [0-7]
-* \param attr The attribute value to be set.
-*/
-__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
-{
-  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
-}
-
-#ifdef MPU_NS
-/** Set the memory attribute encoding to the Non-secure MPU.
-* \param idx The attribute index to be set [0-7]
-* \param attr The attribute value to be set.
-*/
-__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
-{
-  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
-}
-#endif
-
-/** Clear and disable the given MPU region of the given MPU.
-* \param mpu Pointer to MPU to be used.
-* \param rnr Region number to be cleared.
-*/
-__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
-{
-  mpu->RNR = rnr;
-  mpu->RLAR = 0U;
-}
-
-/** Clear and disable the given MPU region.
-* \param rnr Region number to be cleared.
-*/
-__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
-{
-  ARM_MPU_ClrRegionEx(MPU, rnr);
-}
-
-#ifdef MPU_NS
-/** Clear and disable the given Non-secure MPU region.
-* \param rnr Region number to be cleared.
-*/
-__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
-{  
-  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
-}
-#endif
-
-/** Configure the given MPU region of the given MPU.
-* \param mpu Pointer to MPU to be used.
-* \param rnr Region number to be configured.
-* \param rbar Value for RBAR register.
-* \param rlar Value for RLAR register.
-*/   
-__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
-{
-  mpu->RNR = rnr;
-  mpu->RBAR = rbar;
-  mpu->RLAR = rlar;
-}
-
-/** Configure the given MPU region.
-* \param rnr Region number to be configured.
-* \param rbar Value for RBAR register.
-* \param rlar Value for RLAR register.
-*/   
-__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
-{
-  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
-}
-
-#ifdef MPU_NS
-/** Configure the given Non-secure MPU region.
-* \param rnr Region number to be configured.
-* \param rbar Value for RBAR register.
-* \param rlar Value for RLAR register.
-*/   
-__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
-{
-  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
-}
-#endif
-
-/** Memcopy with strictly ordered memory access, e.g. for register targets.
-* \param dst Destination data is copied to.
-* \param src Source data is copied from.
-* \param len Amount of data words to be copied.
-*/
-__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
-{
-  uint32_t i;
-  for (i = 0U; i < len; ++i) 
-  {
-    dst[i] = src[i];
-  }
-}
-
-/** Load the given number of MPU regions from a table to the given MPU.
-* \param mpu Pointer to the MPU registers to be used.
-* \param rnr First region number to be configured.
-* \param table Pointer to the MPU configuration table.
-* \param cnt Amount of regions to be configured.
-*/
-__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
-{
-  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
-  if (cnt == 1U) {
-    mpu->RNR = rnr;
-    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
-  } else {
-    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
-    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
-    
-    mpu->RNR = rnrBase;
-    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
-      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
-      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
-      table += c;
-      cnt -= c;
-      rnrOffset = 0U;
-      rnrBase += MPU_TYPE_RALIASES;
-      mpu->RNR = rnrBase;
-    }
-    
-    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
-  }
-}
-
-/** Load the given number of MPU regions from a table.
-* \param rnr First region number to be configured.
-* \param table Pointer to the MPU configuration table.
-* \param cnt Amount of regions to be configured.
-*/
-__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
-{
-  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
-}
-
-#ifdef MPU_NS
-/** Load the given number of MPU regions from a table to the Non-secure MPU.
-* \param rnr First region number to be configured.
-* \param table Pointer to the MPU configuration table.
-* \param cnt Amount of regions to be configured.
-*/
-__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
-{
-  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
-}
-#endif
-
-#endif
-
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M MPU
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  __DSB();
+  __ISB();
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DSB();
+  __ISB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+
diff --git a/Drivers/CMSIS/Include/tz_context.h b/Drivers/CMSIS/Include/tz_context.h
index 0d09749..d4c1474 100644
--- a/Drivers/CMSIS/Include/tz_context.h
+++ b/Drivers/CMSIS/Include/tz_context.h
@@ -1,70 +1,70 @@
-/******************************************************************************
- * @file     tz_context.h
- * @brief    Context Management for Armv8-M TrustZone
- * @version  V1.0.1
- * @date     10. January 2018
- ******************************************************************************/
-/*
- * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the License); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an AS IS BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#if   defined ( __ICCARM__ )
-  #pragma system_include         /* treat file as system include file for MISRA check */
-#elif defined (__clang__)
-  #pragma clang system_header   /* treat file as system include file */
-#endif
-
-#ifndef TZ_CONTEXT_H
-#define TZ_CONTEXT_H
- 
-#include <stdint.h>
- 
-#ifndef TZ_MODULEID_T
-#define TZ_MODULEID_T
-/// \details Data type that identifies secure software modules called by a process.
-typedef uint32_t TZ_ModuleId_t;
-#endif
- 
-/// \details TZ Memory ID identifies an allocated memory slot.
-typedef uint32_t TZ_MemoryId_t;
-  
-/// Initialize secure context memory system
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_InitContextSystem_S (void);
- 
-/// Allocate context memory for calling secure software modules in TrustZone
-/// \param[in]  module   identifies software modules called from non-secure mode
-/// \return value != 0 id TrustZone memory slot identifier
-/// \return value 0    no memory available or internal error
-TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
- 
-/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
-/// \param[in]  id  TrustZone memory slot identifier
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
- 
-/// Load secure context (called on RTOS thread context switch)
-/// \param[in]  id  TrustZone memory slot identifier
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
- 
-/// Store secure context (called on RTOS thread context switch)
-/// \param[in]  id  TrustZone memory slot identifier
-/// \return execution status (1: success, 0: error)
-uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
- 
-#endif  // TZ_CONTEXT_H
+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H
diff --git a/Drivers/CMSIS/LICENSE.txt b/Drivers/CMSIS/LICENSE.txt
index 8dada3e..c0ee812 100644
--- a/Drivers/CMSIS/LICENSE.txt
+++ b/Drivers/CMSIS/LICENSE.txt
@@ -1,201 +1,201 @@
-                                 Apache License
-                           Version 2.0, January 2004
-                        http://www.apache.org/licenses/
-
-   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
-
-   1. Definitions.
-
-      "License" shall mean the terms and conditions for use, reproduction,
-      and distribution as defined by Sections 1 through 9 of this document.
-
-      "Licensor" shall mean the copyright owner or entity authorized by
-      the copyright owner that is granting the License.
-
-      "Legal Entity" shall mean the union of the acting entity and all
-      other entities that control, are controlled by, or are under common
-      control with that entity. For the purposes of this definition,
-      "control" means (i) the power, direct or indirect, to cause the
-      direction or management of such entity, whether by contract or
-      otherwise, or (ii) ownership of fifty percent (50%) or more of the
-      outstanding shares, or (iii) beneficial ownership of such entity.
-
-      "You" (or "Your") shall mean an individual or Legal Entity
-      exercising permissions granted by this License.
-
-      "Source" form shall mean the preferred form for making modifications,
-      including but not limited to software source code, documentation
-      source, and configuration files.
-
-      "Object" form shall mean any form resulting from mechanical
-      transformation or translation of a Source form, including but
-      not limited to compiled object code, generated documentation,
-      and conversions to other media types.
-
-      "Work" shall mean the work of authorship, whether in Source or
-      Object form, made available under the License, as indicated by a
-      copyright notice that is included in or attached to the work
-      (an example is provided in the Appendix below).
-
-      "Derivative Works" shall mean any work, whether in Source or Object
-      form, that is based on (or derived from) the Work and for which the
-      editorial revisions, annotations, elaborations, or other modifications
-      represent, as a whole, an original work of authorship. For the purposes
-      of this License, Derivative Works shall not include works that remain
-      separable from, or merely link (or bind by name) to the interfaces of,
-      the Work and Derivative Works thereof.
-
-      "Contribution" shall mean any work of authorship, including
-      the original version of the Work and any modifications or additions
-      to that Work or Derivative Works thereof, that is intentionally
-      submitted to Licensor for inclusion in the Work by the copyright owner
-      or by an individual or Legal Entity authorized to submit on behalf of
-      the copyright owner. For the purposes of this definition, "submitted"
-      means any form of electronic, verbal, or written communication sent
-      to the Licensor or its representatives, including but not limited to
-      communication on electronic mailing lists, source code control systems,
-      and issue tracking systems that are managed by, or on behalf of, the
-      Licensor for the purpose of discussing and improving the Work, but
-      excluding communication that is conspicuously marked or otherwise
-      designated in writing by the copyright owner as "Not a Contribution."
-
-      "Contributor" shall mean Licensor and any individual or Legal Entity
-      on behalf of whom a Contribution has been received by Licensor and
-      subsequently incorporated within the Work.
-
-   2. Grant of Copyright License. Subject to the terms and conditions of
-      this License, each Contributor hereby grants to You a perpetual,
-      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
-      copyright license to reproduce, prepare Derivative Works of,
-      publicly display, publicly perform, sublicense, and distribute the
-      Work and such Derivative Works in Source or Object form.
-
-   3. Grant of Patent License. Subject to the terms and conditions of
-      this License, each Contributor hereby grants to You a perpetual,
-      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
-      (except as stated in this section) patent license to make, have made,
-      use, offer to sell, sell, import, and otherwise transfer the Work,
-      where such license applies only to those patent claims licensable
-      by such Contributor that are necessarily infringed by their
-      Contribution(s) alone or by combination of their Contribution(s)
-      with the Work to which such Contribution(s) was submitted. If You
-      institute patent litigation against any entity (including a
-      cross-claim or counterclaim in a lawsuit) alleging that the Work
-      or a Contribution incorporated within the Work constitutes direct
-      or contributory patent infringement, then any patent licenses
-      granted to You under this License for that Work shall terminate
-      as of the date such litigation is filed.
-
-   4. Redistribution. You may reproduce and distribute copies of the
-      Work or Derivative Works thereof in any medium, with or without
-      modifications, and in Source or Object form, provided that You
-      meet the following conditions:
-
-      (a) You must give any other recipients of the Work or
-          Derivative Works a copy of this License; and
-
-      (b) You must cause any modified files to carry prominent notices
-          stating that You changed the files; and
-
-      (c) You must retain, in the Source form of any Derivative Works
-          that You distribute, all copyright, patent, trademark, and
-          attribution notices from the Source form of the Work,
-          excluding those notices that do not pertain to any part of
-          the Derivative Works; and
-
-      (d) If the Work includes a "NOTICE" text file as part of its
-          distribution, then any Derivative Works that You distribute must
-          include a readable copy of the attribution notices contained
-          within such NOTICE file, excluding those notices that do not
-          pertain to any part of the Derivative Works, in at least one
-          of the following places: within a NOTICE text file distributed
-          as part of the Derivative Works; within the Source form or
-          documentation, if provided along with the Derivative Works; or,
-          within a display generated by the Derivative Works, if and
-          wherever such third-party notices normally appear. The contents
-          of the NOTICE file are for informational purposes only and
-          do not modify the License. You may add Your own attribution
-          notices within Derivative Works that You distribute, alongside
-          or as an addendum to the NOTICE text from the Work, provided
-          that such additional attribution notices cannot be construed
-          as modifying the License.
-
-      You may add Your own copyright statement to Your modifications and
-      may provide additional or different license terms and conditions
-      for use, reproduction, or distribution of Your modifications, or
-      for any such Derivative Works as a whole, provided Your use,
-      reproduction, and distribution of the Work otherwise complies with
-      the conditions stated in this License.
-
-   5. Submission of Contributions. Unless You explicitly state otherwise,
-      any Contribution intentionally submitted for inclusion in the Work
-      by You to the Licensor shall be under the terms and conditions of
-      this License, without any additional terms or conditions.
-      Notwithstanding the above, nothing herein shall supersede or modify
-      the terms of any separate license agreement you may have executed
-      with Licensor regarding such Contributions.
-
-   6. Trademarks. This License does not grant permission to use the trade
-      names, trademarks, service marks, or product names of the Licensor,
-      except as required for reasonable and customary use in describing the
-      origin of the Work and reproducing the content of the NOTICE file.
-
-   7. Disclaimer of Warranty. Unless required by applicable law or
-      agreed to in writing, Licensor provides the Work (and each
-      Contributor provides its Contributions) on an "AS IS" BASIS,
-      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-      implied, including, without limitation, any warranties or conditions
-      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
-      PARTICULAR PURPOSE. You are solely responsible for determining the
-      appropriateness of using or redistributing the Work and assume any
-      risks associated with Your exercise of permissions under this License.
-
-   8. Limitation of Liability. In no event and under no legal theory,
-      whether in tort (including negligence), contract, or otherwise,
-      unless required by applicable law (such as deliberate and grossly
-      negligent acts) or agreed to in writing, shall any Contributor be
-      liable to You for damages, including any direct, indirect, special,
-      incidental, or consequential damages of any character arising as a
-      result of this License or out of the use or inability to use the
-      Work (including but not limited to damages for loss of goodwill,
-      work stoppage, computer failure or malfunction, or any and all
-      other commercial damages or losses), even if such Contributor
-      has been advised of the possibility of such damages.
-
-   9. Accepting Warranty or Additional Liability. While redistributing
-      the Work or Derivative Works thereof, You may choose to offer,
-      and charge a fee for, acceptance of support, warranty, indemnity,
-      or other liability obligations and/or rights consistent with this
-      License. However, in accepting such obligations, You may act only
-      on Your own behalf and on Your sole responsibility, not on behalf
-      of any other Contributor, and only if You agree to indemnify,
-      defend, and hold each Contributor harmless for any liability
-      incurred by, or claims asserted against, such Contributor by reason
-      of your accepting any such warranty or additional liability.
-
-   END OF TERMS AND CONDITIONS
-
-   APPENDIX: How to apply the Apache License to your work.
-
-      To apply the Apache License to your work, attach the following
-      boilerplate notice, with the fields enclosed by brackets "{}"
-      replaced with your own identifying information. (Don't include
-      the brackets!)  The text should be enclosed in the appropriate
-      comment syntax for the file format. We also recommend that a
-      file or class name and description of purpose be included on the
-      same "printed page" as the copyright notice for easier
-      identification within third-party archives.
-
-   Copyright {yyyy} {name of copyright owner}
-
-   Licensed under the Apache License, Version 2.0 (the "License");
-   you may not use this file except in compliance with the License.
-   You may obtain a copy of the License at
-
-       http://www.apache.org/licenses/LICENSE-2.0
-
-   Unless required by applicable law or agreed to in writing, software
-   distributed under the License is distributed on an "AS IS" BASIS,
-   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-   See the License for the specific language governing permissions and
-   limitations under the License.
+                                 Apache License
+                           Version 2.0, January 2004
+                        http://www.apache.org/licenses/
+
+   TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+   1. Definitions.
+
+      "License" shall mean the terms and conditions for use, reproduction,
+      and distribution as defined by Sections 1 through 9 of this document.
+
+      "Licensor" shall mean the copyright owner or entity authorized by
+      the copyright owner that is granting the License.
+
+      "Legal Entity" shall mean the union of the acting entity and all
+      other entities that control, are controlled by, or are under common
+      control with that entity. For the purposes of this definition,
+      "control" means (i) the power, direct or indirect, to cause the
+      direction or management of such entity, whether by contract or
+      otherwise, or (ii) ownership of fifty percent (50%) or more of the
+      outstanding shares, or (iii) beneficial ownership of such entity.
+
+      "You" (or "Your") shall mean an individual or Legal Entity
+      exercising permissions granted by this License.
+
+      "Source" form shall mean the preferred form for making modifications,
+      including but not limited to software source code, documentation
+      source, and configuration files.
+
+      "Object" form shall mean any form resulting from mechanical
+      transformation or translation of a Source form, including but
+      not limited to compiled object code, generated documentation,
+      and conversions to other media types.
+
+      "Work" shall mean the work of authorship, whether in Source or
+      Object form, made available under the License, as indicated by a
+      copyright notice that is included in or attached to the work
+      (an example is provided in the Appendix below).
+
+      "Derivative Works" shall mean any work, whether in Source or Object
+      form, that is based on (or derived from) the Work and for which the
+      editorial revisions, annotations, elaborations, or other modifications
+      represent, as a whole, an original work of authorship. For the purposes
+      of this License, Derivative Works shall not include works that remain
+      separable from, or merely link (or bind by name) to the interfaces of,
+      the Work and Derivative Works thereof.
+
+      "Contribution" shall mean any work of authorship, including
+      the original version of the Work and any modifications or additions
+      to that Work or Derivative Works thereof, that is intentionally
+      submitted to Licensor for inclusion in the Work by the copyright owner
+      or by an individual or Legal Entity authorized to submit on behalf of
+      the copyright owner. For the purposes of this definition, "submitted"
+      means any form of electronic, verbal, or written communication sent
+      to the Licensor or its representatives, including but not limited to
+      communication on electronic mailing lists, source code control systems,
+      and issue tracking systems that are managed by, or on behalf of, the
+      Licensor for the purpose of discussing and improving the Work, but
+      excluding communication that is conspicuously marked or otherwise
+      designated in writing by the copyright owner as "Not a Contribution."
+
+      "Contributor" shall mean Licensor and any individual or Legal Entity
+      on behalf of whom a Contribution has been received by Licensor and
+      subsequently incorporated within the Work.
+
+   2. Grant of Copyright License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      copyright license to reproduce, prepare Derivative Works of,
+      publicly display, publicly perform, sublicense, and distribute the
+      Work and such Derivative Works in Source or Object form.
+
+   3. Grant of Patent License. Subject to the terms and conditions of
+      this License, each Contributor hereby grants to You a perpetual,
+      worldwide, non-exclusive, no-charge, royalty-free, irrevocable
+      (except as stated in this section) patent license to make, have made,
+      use, offer to sell, sell, import, and otherwise transfer the Work,
+      where such license applies only to those patent claims licensable
+      by such Contributor that are necessarily infringed by their
+      Contribution(s) alone or by combination of their Contribution(s)
+      with the Work to which such Contribution(s) was submitted. If You
+      institute patent litigation against any entity (including a
+      cross-claim or counterclaim in a lawsuit) alleging that the Work
+      or a Contribution incorporated within the Work constitutes direct
+      or contributory patent infringement, then any patent licenses
+      granted to You under this License for that Work shall terminate
+      as of the date such litigation is filed.
+
+   4. Redistribution. You may reproduce and distribute copies of the
+      Work or Derivative Works thereof in any medium, with or without
+      modifications, and in Source or Object form, provided that You
+      meet the following conditions:
+
+      (a) You must give any other recipients of the Work or
+          Derivative Works a copy of this License; and
+
+      (b) You must cause any modified files to carry prominent notices
+          stating that You changed the files; and
+
+      (c) You must retain, in the Source form of any Derivative Works
+          that You distribute, all copyright, patent, trademark, and
+          attribution notices from the Source form of the Work,
+          excluding those notices that do not pertain to any part of
+          the Derivative Works; and
+
+      (d) If the Work includes a "NOTICE" text file as part of its
+          distribution, then any Derivative Works that You distribute must
+          include a readable copy of the attribution notices contained
+          within such NOTICE file, excluding those notices that do not
+          pertain to any part of the Derivative Works, in at least one
+          of the following places: within a NOTICE text file distributed
+          as part of the Derivative Works; within the Source form or
+          documentation, if provided along with the Derivative Works; or,
+          within a display generated by the Derivative Works, if and
+          wherever such third-party notices normally appear. The contents
+          of the NOTICE file are for informational purposes only and
+          do not modify the License. You may add Your own attribution
+          notices within Derivative Works that You distribute, alongside
+          or as an addendum to the NOTICE text from the Work, provided
+          that such additional attribution notices cannot be construed
+          as modifying the License.
+
+      You may add Your own copyright statement to Your modifications and
+      may provide additional or different license terms and conditions
+      for use, reproduction, or distribution of Your modifications, or
+      for any such Derivative Works as a whole, provided Your use,
+      reproduction, and distribution of the Work otherwise complies with
+      the conditions stated in this License.
+
+   5. Submission of Contributions. Unless You explicitly state otherwise,
+      any Contribution intentionally submitted for inclusion in the Work
+      by You to the Licensor shall be under the terms and conditions of
+      this License, without any additional terms or conditions.
+      Notwithstanding the above, nothing herein shall supersede or modify
+      the terms of any separate license agreement you may have executed
+      with Licensor regarding such Contributions.
+
+   6. Trademarks. This License does not grant permission to use the trade
+      names, trademarks, service marks, or product names of the Licensor,
+      except as required for reasonable and customary use in describing the
+      origin of the Work and reproducing the content of the NOTICE file.
+
+   7. Disclaimer of Warranty. Unless required by applicable law or
+      agreed to in writing, Licensor provides the Work (and each
+      Contributor provides its Contributions) on an "AS IS" BASIS,
+      WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+      implied, including, without limitation, any warranties or conditions
+      of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+      PARTICULAR PURPOSE. You are solely responsible for determining the
+      appropriateness of using or redistributing the Work and assume any
+      risks associated with Your exercise of permissions under this License.
+
+   8. Limitation of Liability. In no event and under no legal theory,
+      whether in tort (including negligence), contract, or otherwise,
+      unless required by applicable law (such as deliberate and grossly
+      negligent acts) or agreed to in writing, shall any Contributor be
+      liable to You for damages, including any direct, indirect, special,
+      incidental, or consequential damages of any character arising as a
+      result of this License or out of the use or inability to use the
+      Work (including but not limited to damages for loss of goodwill,
+      work stoppage, computer failure or malfunction, or any and all
+      other commercial damages or losses), even if such Contributor
+      has been advised of the possibility of such damages.
+
+   9. Accepting Warranty or Additional Liability. While redistributing
+      the Work or Derivative Works thereof, You may choose to offer,
+      and charge a fee for, acceptance of support, warranty, indemnity,
+      or other liability obligations and/or rights consistent with this
+      License. However, in accepting such obligations, You may act only
+      on Your own behalf and on Your sole responsibility, not on behalf
+      of any other Contributor, and only if You agree to indemnify,
+      defend, and hold each Contributor harmless for any liability
+      incurred by, or claims asserted against, such Contributor by reason
+      of your accepting any such warranty or additional liability.
+
+   END OF TERMS AND CONDITIONS
+
+   APPENDIX: How to apply the Apache License to your work.
+
+      To apply the Apache License to your work, attach the following
+      boilerplate notice, with the fields enclosed by brackets "{}"
+      replaced with your own identifying information. (Don't include
+      the brackets!)  The text should be enclosed in the appropriate
+      comment syntax for the file format. We also recommend that a
+      file or class name and description of purpose be included on the
+      same "printed page" as the copyright notice for easier
+      identification within third-party archives.
+
+   Copyright {yyyy} {name of copyright owner}
+
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       http://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
index 934f1f9..17b5cee 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h
@@ -1,4014 +1,4014 @@
-/**
-  ******************************************************************************
-  * @file    stm32_hal_legacy.h
-  * @author  MCD Application Team
-  * @brief   This file contains aliases definition for the STM32Cube HAL constants
-  *          macros and functions maintained for legacy purpose.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2021 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32_HAL_LEGACY
-#define STM32_HAL_LEGACY
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
-#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
-#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
-#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
-#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
-#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
-#define CRYP_DATATYPE_32B               CRYP_NO_SWAP
-#define CRYP_DATATYPE_16B               CRYP_HALFWORD_SWAP
-#define CRYP_DATATYPE_8B                CRYP_BYTE_SWAP
-#define CRYP_DATATYPE_1B                CRYP_BIT_SWAP
-#if defined(STM32U5)
-#define CRYP_CCF_CLEAR                  CRYP_CLEAR_CCF
-#define CRYP_ERR_CLEAR                  CRYP_CLEAR_RWEIF
-#endif /* STM32U5 */
-#endif /* STM32U5 || STM32H7 || STM32MP1 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
-#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
-#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
-#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
-#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
-#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
-#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
-#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
-#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
-#define REGULAR_GROUP                   ADC_REGULAR_GROUP
-#define INJECTED_GROUP                  ADC_INJECTED_GROUP
-#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
-#define AWD_EVENT                       ADC_AWD_EVENT
-#define AWD1_EVENT                      ADC_AWD1_EVENT
-#define AWD2_EVENT                      ADC_AWD2_EVENT
-#define AWD3_EVENT                      ADC_AWD3_EVENT
-#define OVR_EVENT                       ADC_OVR_EVENT
-#define JQOVF_EVENT                     ADC_JQOVF_EVENT
-#define ALL_CHANNELS                    ADC_ALL_CHANNELS
-#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
-#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
-#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
-#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
-#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
-#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
-#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
-#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
-#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
-#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
-#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
-#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
-#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
-#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
-#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
-#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
-#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
-#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
-#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
-#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
-
-#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
-#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
-#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
-#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
-#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
-#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
-
-#if defined(STM32H7)
-#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
-#endif /* STM32H7 */
-
-#if defined(STM32U5)
-#define ADC_SAMPLETIME_5CYCLE           ADC_SAMPLETIME_5CYCLES
-#define ADC_SAMPLETIME_391CYCLES_5      ADC_SAMPLETIME_391CYCLES
-#define ADC4_SAMPLETIME_160CYCLES_5     ADC4_SAMPLETIME_814CYCLES_5
-#endif /* STM32U5 */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
-#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
-#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
-#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
-#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
-#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
-#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
-#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
-#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
-#if defined(STM32L0)
-#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
-#endif
-#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
-#if defined(STM32F373xC) || defined(STM32F378xx)
-#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
-#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
-#endif /* STM32F373xC || STM32F378xx */
-
-#if defined(STM32L0) || defined(STM32L4)
-#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
-
-#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
-#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
-#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
-#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
-#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
-#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
-
-#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
-#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
-#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
-#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
-#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
-#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
-#if defined(STM32L0)
-/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
-/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
-/* to the second dedicated IO (only for COMP2).                               */
-#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
-#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
-#else
-#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
-#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
-#endif
-#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
-#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
-
-#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
-#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
-
-/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
-/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
-#if defined(COMP_CSR_LOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
-#elif defined(COMP_CSR_COMP1LOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
-#elif defined(COMP_CSR_COMPxLOCK)
-#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
-#endif
-
-#if defined(STM32L4)
-#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
-#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
-#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
-#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
-#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
-#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
-#endif
-
-#if defined(STM32L0)
-#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
-#else
-#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
-#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
-#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
-#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
-#endif
-
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
-#if defined(STM32U5)
-#define  MPU_DEVICE_nGnRnE          MPU_DEVICE_NGNRNE
-#define  MPU_DEVICE_nGnRE           MPU_DEVICE_NGNRE
-#define  MPU_DEVICE_nGRE            MPU_DEVICE_NGRE
-#endif /* STM32U5 */
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Aliases CRC API aliases
-  * @{
-  */
-#if defined(STM32C0)
-#else
-#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility  */
-#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
-#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
-#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
-#define DAC_WAVE_NONE                                   0x00000000U
-#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
-#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
-#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
-#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
-#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
-
-#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
-#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
-#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
-#endif
-
-#if defined(STM32U5)
-#define DAC_TRIGGER_STOP_LPTIM1_OUT  DAC_TRIGGER_STOP_LPTIM1_CH1
-#define DAC_TRIGGER_STOP_LPTIM3_OUT  DAC_TRIGGER_STOP_LPTIM3_CH1
-#define DAC_TRIGGER_LPTIM1_OUT       DAC_TRIGGER_LPTIM1_CH1
-#define DAC_TRIGGER_LPTIM3_OUT       DAC_TRIGGER_LPTIM3_CH1
-#endif
-
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
-#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
-#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
-#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
-#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
-#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
-#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
-#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
-#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
-#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
-#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
-#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
-
-#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
-#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
-#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
-
-#if defined(STM32L4)
-
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE
-#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT
-#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
-#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT
-
-#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT
-#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING
-#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
-#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
-#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
-#endif
-
-#endif /* STM32L4 */
-
-#if defined(STM32G0)
-#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1
-#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2
-#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM
-#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM
-
-#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM
-#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM
-#endif
-
-#if defined(STM32H7)
-
-#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
-#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
-
-#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
-#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
-
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
-#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
-#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
-
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
-#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
-#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
-#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
-#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
-#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
-#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
-#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
-#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
-#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
-
-#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
-#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
-#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
-#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
-
-#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
-#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
-#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
-
-#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT
-#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT
-
-#endif /* STM32H7 */
-
-#if defined(STM32U5)
-#define GPDMA1_REQUEST_DCMI                        GPDMA1_REQUEST_DCMI_PSSI
-#endif /* STM32U5 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
-#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
-#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
-#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
-#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
-#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
-#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
-#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
-#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
-#define OBEX_PCROP                    OPTIONBYTE_PCROP
-#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
-#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
-#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
-#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
-#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
-#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
-#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
-#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
-#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
-#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
-#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
-#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
-#define PAGESIZE                      FLASH_PAGE_SIZE
-#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
-#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
-#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
-#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
-#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
-#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
-#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
-#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
-#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
-#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
-#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
-#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
-#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
-#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
-#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
-#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
-#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
-#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
-#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
-#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
-#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
-#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
-#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
-#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
-#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
-#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
-#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
-#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
-#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
-#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
-#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
-#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
-#define OB_WDG_SW                     OB_IWDG_SW
-#define OB_WDG_HW                     OB_IWDG_HW
-#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
-#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
-#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
-#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
-#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
-#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
-#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
-#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
-#if defined(STM32G0) || defined(STM32C0)
-#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
-#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
-#else
-#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE
-#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
-#endif
-#if defined(STM32H7)
-#define FLASH_FLAG_SNECCE_BANK1RR     FLASH_FLAG_SNECCERR_BANK1
-#define FLASH_FLAG_DBECCE_BANK1RR     FLASH_FLAG_DBECCERR_BANK1
-#define FLASH_FLAG_STRBER_BANK1R      FLASH_FLAG_STRBERR_BANK1
-#define FLASH_FLAG_SNECCE_BANK2RR     FLASH_FLAG_SNECCERR_BANK2
-#define FLASH_FLAG_DBECCE_BANK2RR     FLASH_FLAG_DBECCERR_BANK2
-#define FLASH_FLAG_STRBER_BANK2R      FLASH_FLAG_STRBERR_BANK2
-#define FLASH_FLAG_WDW                FLASH_FLAG_WBNE
-#define OB_WRP_SECTOR_All             OB_WRP_SECTOR_ALL
-#endif /* STM32H7 */
-#if defined(STM32U5)
-#define OB_USER_nRST_STOP             OB_USER_NRST_STOP
-#define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
-#define OB_USER_nRST_SHDW             OB_USER_NRST_SHDW
-#define OB_USER_nSWBOOT0              OB_USER_NSWBOOT0
-#define OB_USER_nBOOT0                OB_USER_NBOOT0
-#define OB_nBOOT0_RESET               OB_NBOOT0_RESET
-#define OB_nBOOT0_SET                 OB_NBOOT0_SET
-#endif /* STM32U5 */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#if defined(STM32H7)
-#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
-#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
-#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
-#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
-#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
-#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
-#endif /* STM32H7 */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
-#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
-#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
-#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
-#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
-#if defined(STM32G4)
-
-#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
-#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
-#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
-#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
-#endif /* STM32G4 */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
-  * @{
-  */
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
-#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
-#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
-#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
-#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
-#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
-#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
-#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
-#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
-/**
-  * @}
-  */
-
-/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
-#define GET_GPIO_INDEX                            GPIO_GET_INDEX
-
-#if defined(STM32F4)
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
-#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
-#endif
-
-#if defined(STM32F7)
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32L4)
-#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
-#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
-#endif
-
-#if defined(STM32H7)
-#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1
-#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1
-#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1
-#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
-#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
-#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
-
-#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \
-    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)
-#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
-#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
-#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
-#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
-#endif /* STM32H7 */
-
-#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
-#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
-#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
-
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
-#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
-#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
-#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
-#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
-
-#if defined(STM32L1)
-#define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
-#define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
-#define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
-#define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L1 */
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
-#define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
-#define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
-#define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
-#endif /* STM32F0 || STM32F3 || STM32F1 */
-
-#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
-
-#if defined(STM32U5)
-#define GPIO_AF0_RTC_50Hz                         GPIO_AF0_RTC_50HZ
-#endif /* STM32U5 */
-#if defined(STM32U5)
-#define GPIO_AF0_S2DSTOP                          GPIO_AF0_SRDSTOP
-#define GPIO_AF11_LPGPIO                          GPIO_AF11_LPGPIO1
-#endif /* STM32U5 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#if defined(STM32U5)
-#define GTZC_PERIPH_DCMI                      GTZC_PERIPH_DCMI_PSSI
-#endif /* STM32U5 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
-#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
-#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-
-#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
-#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
-#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
-#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
-#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
-#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
-#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
-#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
-
-#if defined(STM32G4)
-#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
-#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
-#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
-#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
-#define HRTIM_TIMEEVENT_A                       HRTIM_EVENTCOUNTER_A
-#define HRTIM_TIMEEVENT_B                       HRTIM_EVENTCOUNTER_B
-#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL  HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
-#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL    HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
-#endif /* STM32G4 */
-
-#if defined(STM32H7)
-#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
-
-#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
-#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
-#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
-#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
-#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
-#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
-#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
-#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
-#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
-#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
-#endif /* STM32H7 */
-
-#if defined(STM32F3)
-/** @brief Constants defining available sources associated to external events.
-  */
-#define HRTIM_EVENTSRC_1              (0x00000000U)
-#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)
-#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)
-#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
-
-/** @brief Constants defining the DLL calibration periods (in micro seconds)
-  */
-#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
-#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
-#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
-#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
-
-#endif /* STM32F3 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
-#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
-#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
-#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
-#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
-#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
-#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
-#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
-#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
-#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
-#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
-#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
-#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
-#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
-#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
-#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
-#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
-
-#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
-#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
-#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
-
-#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
-#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-/* The following 3 definition have also been present in a temporary version of lptim.h */
-/* They need to be renamed also to the right name, just in case */
-#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
-
-
-/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_LPTIM_ReadCompare      HAL_LPTIM_ReadCapturedValue
-/**
-  * @}
-  */
-
-#if defined(STM32U5)
-#define LPTIM_ISR_CC1        LPTIM_ISR_CC1IF
-#define LPTIM_ISR_CC2        LPTIM_ISR_CC2IF
-#define LPTIM_CHANNEL_ALL    0x00000000U
-#endif /* STM32U5 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
-#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
-#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
-#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
-
-#define NAND_AddressTypedef             NAND_AddressTypeDef
-
-#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
-#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
-#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
-#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
-#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
-#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
-#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
-#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
-#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
-
-#define __NOR_WRITE                    NOR_WRITE
-#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
-/**
-  * @}
-  */
-
-/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
-#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
-#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
-#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
-
-#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
-#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
-#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
-
-#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
-#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
-
-#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
-#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
-
-#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
-#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
-#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
-#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
-#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
-#endif
-
-#if defined(STM32L4) || defined(STM32L5)
-#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALPOWER
-#elif defined(STM32G4)
-#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALSPEED
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
-
-#if defined(STM32H7)
-#define I2S_IT_TXE               I2S_IT_TXP
-#define I2S_IT_RXNE              I2S_IT_RXP
-
-#define I2S_FLAG_TXE             I2S_FLAG_TXP
-#define I2S_FLAG_RXNE            I2S_FLAG_RXP
-#endif
-
-#if defined(STM32F7)
-#define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-/* Compact Flash-ATA registers description */
-#define CF_DATA                       ATA_DATA
-#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
-#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
-#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
-#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
-#define CF_CARD_HEAD                  ATA_CARD_HEAD
-#define CF_STATUS_CMD                 ATA_STATUS_CMD
-#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
-
-/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
-#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
-#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
-#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
-
-#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
-#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
-#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
-#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
-#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define FORMAT_BIN                  RTC_FORMAT_BIN
-#define FORMAT_BCD                  RTC_FORMAT_BCD
-
-#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
-
-#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
-#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
-
-#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0   RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PI8   RTC_TIMESTAMPPIN_POS1
-#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
-
-#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
-#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
-#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
-
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
-#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
-#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
-
-#if defined(STM32F7)
-#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_ENABLE_BITS_MASK
-#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_IT_ENABLE_BITS_MASK
-#endif /* STM32F7 */
-
-#if defined(STM32H7)
-#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
-#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
-#endif /* STM32H7 */
-
-#if defined(STM32F7) || defined(STM32H7)
-#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
-#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
-#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
-#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMP
-#endif /* STM32F7 || STM32H7 */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
-#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
-
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
-#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
-
-#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
-#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
-
-#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
-#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
-#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
-#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
-#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
-#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
-#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
-#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
-#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
-#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
-#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
-#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
-#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
-
-#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
-#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
-
-#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
-#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
-
-#if defined(STM32H7)
-
-#define SPI_FLAG_TXE                    SPI_FLAG_TXP
-#define SPI_FLAG_RXNE                   SPI_FLAG_RXP
-
-#define SPI_IT_TXE                      SPI_IT_TXP
-#define SPI_IT_RXNE                     SPI_IT_RXP
-
-#define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET
-#define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET
-#define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET
-#define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET
-
-#endif /* STM32H7 */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
-#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
-
-#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
-#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
-#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
-#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
-#define TIM_DMABase_SR                   TIM_DMABASE_SR
-#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
-#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
-#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
-#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
-#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
-#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
-#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
-#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
-#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
-#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
-#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
-#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
-#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
-#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
-#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
-#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
-#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
-#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
-#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
-#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
-#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
-#define TIM_DMABase_OR                   TIM_DMABASE_OR
-
-#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
-#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
-#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
-#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
-#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
-#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
-#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
-#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
-#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
-
-#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
-#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
-#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
-#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
-#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
-#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
-#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
-#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
-#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
-#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
-#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
-#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
-#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
-#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
-#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
-#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
-#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
-#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
-
-#if defined(STM32L0)
-#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO
-#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO
-#endif
-
-#if defined(STM32F3)
-#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
-#endif
-
-#if defined(STM32H7)
-#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1
-#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2
-#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1
-#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2
-#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1
-#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2
-#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1
-#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1
-#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2
-#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1
-#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2
-#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2
-#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1
-#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2
-#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
-#endif
-
-#if defined(STM32U5) || defined(STM32MP2)
-#define OCREF_CLEAR_SELECT_Pos       OCREF_CLEAR_SELECT_POS
-#define OCREF_CLEAR_SELECT_Msk       OCREF_CLEAR_SELECT_MSK
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
-#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
-#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
-#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
-
-#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
-#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
-
-#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
-#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
-#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
-#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
-
-#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
-#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
-#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
-#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
-
-#define __DIV_LPUART                    UART_DIV_LPUART
-
-#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
-#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
-#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
-
-#define USARTNACK_ENABLED               USART_NACK_ENABLE
-#define USARTNACK_DISABLED              USART_NACK_DISABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CFR_BASE                    WWDG_CFR_BASE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
-#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
-#define CAN_IT_RQCP0                CAN_IT_TME
-#define CAN_IT_RQCP1                CAN_IT_TME
-#define CAN_IT_RQCP2                CAN_IT_TME
-#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
-#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
-#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
-#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-#define VLAN_TAG                ETH_VLAN_TAG
-#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
-#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
-#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
-#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
-#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
-#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
-#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
-
-#define ETH_MMCCR              0x00000100U
-#define ETH_MMCRIR             0x00000104U
-#define ETH_MMCTIR             0x00000108U
-#define ETH_MMCRIMR            0x0000010CU
-#define ETH_MMCTIMR            0x00000110U
-#define ETH_MMCTGFSCCR         0x0000014CU
-#define ETH_MMCTGFMSCCR        0x00000150U
-#define ETH_MMCTGFCR           0x00000168U
-#define ETH_MMCRFCECR          0x00000194U
-#define ETH_MMCRFAECR          0x00000198U
-#define ETH_MMCRGUFCR          0x000001C4U
-
-#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
-#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
-#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
-#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
-#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
-#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
-#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
-#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
-#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
-#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
-#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
-#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
-#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
-#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
-#if defined(STM32F1)
-#else
-#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
-#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
-#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#endif
-#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
-#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
-#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
-#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
-#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
-#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
-#define DCMI_IT_OVF             DCMI_IT_OVR
-#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
-#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
-
-#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
-#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
-#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
-
-/**
-  * @}
-  */
-
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
-  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
-  || defined(STM32H7)
-/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
-  * @{
-  */
-#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
-#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
-#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
-#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
-#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
-
-#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
-#define CM_RGB888               DMA2D_INPUT_RGB888
-#define CM_RGB565               DMA2D_INPUT_RGB565
-#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
-#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
-#define CM_L8                   DMA2D_INPUT_L8
-#define CM_AL44                 DMA2D_INPUT_AL44
-#define CM_AL88                 DMA2D_INPUT_AL88
-#define CM_L4                   DMA2D_INPUT_L4
-#define CM_A8                   DMA2D_INPUT_A8
-#define CM_A4                   DMA2D_INPUT_A4
-/**
-  * @}
-  */
-#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
-
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
-  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
-  || defined(STM32H7) || defined(STM32U5)
-/** @defgroup DMA2D_Aliases DMA2D API Aliases
-  * @{
-  */
-#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
-                                                                        for compatibility with legacy code */
-/**
-  * @}
-  */
-
-#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 || STM32U5 */
-
-/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
-  * @{
-  */
-
-#if defined(STM32U5)
-#define HAL_DCACHE_CleanInvalidateByAddr     HAL_DCACHE_CleanInvalidByAddr
-#define HAL_DCACHE_CleanInvalidateByAddr_IT  HAL_DCACHE_CleanInvalidByAddr_IT
-#endif /* STM32U5 */
-
-/**
-  * @}
-  */
-
-#if !defined(STM32F2)
-/** @defgroup HASH_alias HASH API alias
-  * @{
-  */
-#define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< Redirection for compatibility with legacy code */
-/**
-  *
-  * @}
-  */
-#endif /* STM32F2 */
-/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
-#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
-#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
-#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
-#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
-#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
-
-/*HASH Algorithm Selection*/
-
-#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
-#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
-#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
-#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
-
-#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
-#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
-
-#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
-#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
-
-#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
-
-#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
-#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
-#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT
-#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT
-
-#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt
-#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End
-#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT
-#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT
-
-#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt
-#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End
-#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT
-#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT
-
-#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt
-#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End
-#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
-#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
-
-#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
-#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
-#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
-#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
-#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
-#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
-#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
-                                              )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
-#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
-#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
-#if defined(STM32L0)
-#else
-#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
-#endif
-#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
-#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
-                                              )==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
-#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
-#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
-#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
-#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
-#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode
-#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
-#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
-#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
-#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
-#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
-#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
-#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
-
-/**
-  * @}
- */
-
-/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
-#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
-#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
-#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
-
-#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
-                                                                 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
-
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
-#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
-#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
-#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
-#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
-#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
-#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
-#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
-#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
-#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
-
-#if defined(STM32F4)
-#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
-#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT
-#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT
-#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT
-#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
-#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA
-#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA
-#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA
-#endif /* STM32F4 */
-/**
-  * @}
- */
-
-/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
-  * @{
-  */
-
-#if defined(STM32G0)
-#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD
-#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD
-#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD
-#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler
-#endif
-#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
-#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
-#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
-#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
-#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
-#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
-#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
-#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
-#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
-#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
-#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
-#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
-#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
-#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
-#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
-#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
-
-#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
-#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
-#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
-#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
-#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
-#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
-#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
-
-#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
-#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
-#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER
-#define CR_PMODE_BB                                   CR_VOS_BB
-
-#define DBP_BitNumber                                 DBP_BIT_NUMBER
-#define PVDE_BitNumber                                PVDE_BIT_NUMBER
-#define PMODE_BitNumber                               PMODE_BIT_NUMBER
-#define EWUP_BitNumber                                EWUP_BIT_NUMBER
-#define FPDS_BitNumber                                FPDS_BIT_NUMBER
-#define ODEN_BitNumber                                ODEN_BIT_NUMBER
-#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
-#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
-#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
-#define BRE_BitNumber                                 BRE_BIT_NUMBER
-
-#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
-
-#if defined (STM32U5)
-#define PWR_SRAM1_PAGE1_STOP_RETENTION                PWR_SRAM1_PAGE1_STOP
-#define PWR_SRAM1_PAGE2_STOP_RETENTION                PWR_SRAM1_PAGE2_STOP
-#define PWR_SRAM1_PAGE3_STOP_RETENTION                PWR_SRAM1_PAGE3_STOP
-#define PWR_SRAM1_PAGE4_STOP_RETENTION                PWR_SRAM1_PAGE4_STOP
-#define PWR_SRAM1_PAGE5_STOP_RETENTION                PWR_SRAM1_PAGE5_STOP
-#define PWR_SRAM1_PAGE6_STOP_RETENTION                PWR_SRAM1_PAGE6_STOP
-#define PWR_SRAM1_PAGE7_STOP_RETENTION                PWR_SRAM1_PAGE7_STOP
-#define PWR_SRAM1_PAGE8_STOP_RETENTION                PWR_SRAM1_PAGE8_STOP
-#define PWR_SRAM1_PAGE9_STOP_RETENTION                PWR_SRAM1_PAGE9_STOP
-#define PWR_SRAM1_PAGE10_STOP_RETENTION               PWR_SRAM1_PAGE10_STOP
-#define PWR_SRAM1_PAGE11_STOP_RETENTION               PWR_SRAM1_PAGE11_STOP
-#define PWR_SRAM1_PAGE12_STOP_RETENTION               PWR_SRAM1_PAGE12_STOP
-#define PWR_SRAM1_FULL_STOP_RETENTION                 PWR_SRAM1_FULL_STOP
-
-#define PWR_SRAM2_PAGE1_STOP_RETENTION                PWR_SRAM2_PAGE1_STOP
-#define PWR_SRAM2_PAGE2_STOP_RETENTION                PWR_SRAM2_PAGE2_STOP
-#define PWR_SRAM2_FULL_STOP_RETENTION                 PWR_SRAM2_FULL_STOP
-
-#define PWR_SRAM3_PAGE1_STOP_RETENTION                PWR_SRAM3_PAGE1_STOP
-#define PWR_SRAM3_PAGE2_STOP_RETENTION                PWR_SRAM3_PAGE2_STOP
-#define PWR_SRAM3_PAGE3_STOP_RETENTION                PWR_SRAM3_PAGE3_STOP
-#define PWR_SRAM3_PAGE4_STOP_RETENTION                PWR_SRAM3_PAGE4_STOP
-#define PWR_SRAM3_PAGE5_STOP_RETENTION                PWR_SRAM3_PAGE5_STOP
-#define PWR_SRAM3_PAGE6_STOP_RETENTION                PWR_SRAM3_PAGE6_STOP
-#define PWR_SRAM3_PAGE7_STOP_RETENTION                PWR_SRAM3_PAGE7_STOP
-#define PWR_SRAM3_PAGE8_STOP_RETENTION                PWR_SRAM3_PAGE8_STOP
-#define PWR_SRAM3_PAGE9_STOP_RETENTION                PWR_SRAM3_PAGE9_STOP
-#define PWR_SRAM3_PAGE10_STOP_RETENTION               PWR_SRAM3_PAGE10_STOP
-#define PWR_SRAM3_PAGE11_STOP_RETENTION               PWR_SRAM3_PAGE11_STOP
-#define PWR_SRAM3_PAGE12_STOP_RETENTION               PWR_SRAM3_PAGE12_STOP
-#define PWR_SRAM3_PAGE13_STOP_RETENTION               PWR_SRAM3_PAGE13_STOP
-#define PWR_SRAM3_FULL_STOP_RETENTION                 PWR_SRAM3_FULL_STOP
-
-#define PWR_SRAM4_FULL_STOP_RETENTION                 PWR_SRAM4_FULL_STOP
-
-#define PWR_SRAM5_PAGE1_STOP_RETENTION                PWR_SRAM5_PAGE1_STOP
-#define PWR_SRAM5_PAGE2_STOP_RETENTION                PWR_SRAM5_PAGE2_STOP
-#define PWR_SRAM5_PAGE3_STOP_RETENTION                PWR_SRAM5_PAGE3_STOP
-#define PWR_SRAM5_PAGE4_STOP_RETENTION                PWR_SRAM5_PAGE4_STOP
-#define PWR_SRAM5_PAGE5_STOP_RETENTION                PWR_SRAM5_PAGE5_STOP
-#define PWR_SRAM5_PAGE6_STOP_RETENTION                PWR_SRAM5_PAGE6_STOP
-#define PWR_SRAM5_PAGE7_STOP_RETENTION                PWR_SRAM5_PAGE7_STOP
-#define PWR_SRAM5_PAGE8_STOP_RETENTION                PWR_SRAM5_PAGE8_STOP
-#define PWR_SRAM5_PAGE9_STOP_RETENTION                PWR_SRAM5_PAGE9_STOP
-#define PWR_SRAM5_PAGE10_STOP_RETENTION               PWR_SRAM5_PAGE10_STOP
-#define PWR_SRAM5_PAGE11_STOP_RETENTION               PWR_SRAM5_PAGE11_STOP
-#define PWR_SRAM5_PAGE12_STOP_RETENTION               PWR_SRAM5_PAGE12_STOP
-#define PWR_SRAM5_PAGE13_STOP_RETENTION               PWR_SRAM5_PAGE13_STOP
-#define PWR_SRAM5_FULL_STOP_RETENTION                 PWR_SRAM5_FULL_STOP
-
-#define PWR_ICACHE_FULL_STOP_RETENTION                PWR_ICACHE_FULL_STOP
-#define PWR_DCACHE1_FULL_STOP_RETENTION               PWR_DCACHE1_FULL_STOP
-#define PWR_DCACHE2_FULL_STOP_RETENTION               PWR_DCACHE2_FULL_STOP
-#define PWR_DMA2DRAM_FULL_STOP_RETENTION              PWR_DMA2DRAM_FULL_STOP
-#define PWR_PERIPHRAM_FULL_STOP_RETENTION             PWR_PERIPHRAM_FULL_STOP
-#define PWR_PKA32RAM_FULL_STOP_RETENTION              PWR_PKA32RAM_FULL_STOP
-#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION           PWR_GRAPHICPRAM_FULL_STOP
-#define PWR_DSIRAM_FULL_STOP_RETENTION                PWR_DSIRAM_FULL_STOP
-
-#define PWR_SRAM2_PAGE1_STANDBY_RETENTION             PWR_SRAM2_PAGE1_STANDBY
-#define PWR_SRAM2_PAGE2_STANDBY_RETENTION             PWR_SRAM2_PAGE2_STANDBY
-#define PWR_SRAM2_FULL_STANDBY_RETENTION              PWR_SRAM2_FULL_STANDBY
-
-#define PWR_SRAM1_FULL_RUN_RETENTION                  PWR_SRAM1_FULL_RUN
-#define PWR_SRAM2_FULL_RUN_RETENTION                  PWR_SRAM2_FULL_RUN
-#define PWR_SRAM3_FULL_RUN_RETENTION                  PWR_SRAM3_FULL_RUN
-#define PWR_SRAM4_FULL_RUN_RETENTION                  PWR_SRAM4_FULL_RUN
-#define PWR_SRAM5_FULL_RUN_RETENTION                  PWR_SRAM5_FULL_RUN
-
-#define PWR_ALL_RAM_RUN_RETENTION_MASK                PWR_ALL_RAM_RUN_MASK
-#endif
-
-/**
-  * @}
- */
-
-/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
-#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
-#define HAL_TIM_DMAError                                TIM_DMAError
-#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
-#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
-#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
-#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
-#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
-#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
-#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
-#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
-#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
-#define HAL_LTDC_Relaod           HAL_LTDC_Reload
-#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
-#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros ------------------------------------------------------------*/
-
-/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define AES_IT_CC                      CRYP_IT_CC
-#define AES_IT_ERR                     CRYP_IT_ERR
-#define AES_FLAG_CCF                   CRYP_FLAG_CCF
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
-#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
-#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
-#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
-#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
-#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
-#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
-#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
-#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
-#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
-#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
-#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
-#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
-
-#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
-#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
-#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
-#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
-#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
-#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
-#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
-#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
-#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
-#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
-#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
-#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
-#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
-
-#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
-#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
-#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
-#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
-#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
-#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
-#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
-#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
-#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
-#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
-#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
-#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
-#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
-#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
-#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
-#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
-#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
-#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
-
-#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
-#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
-#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
-#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
-#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
-#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
-#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
-#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
-
-#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
-#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
-#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
-#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
-#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
-#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
-#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
-#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
-
-#define __HAL_ADC_SQR1                                   ADC_SQR1
-#define __HAL_ADC_SMPR1                                  ADC_SMPR1
-#define __HAL_ADC_SMPR2                                  ADC_SMPR2
-#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
-#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
-#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
-#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
-#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
-#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
-#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
-#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
-#define __HAL_ADC_JSQR                                   ADC_JSQR
-
-#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
-#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
-#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
-#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
-#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
-#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
-#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
-#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
-#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
-#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
-#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
-#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
-#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
-#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
-#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
-#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
-#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
-#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
-#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
-#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
-#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
-#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
-#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
-#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
-#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
-#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
-
-#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
-#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
-#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
-#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
-#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
-#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
-#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
-#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
-#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
-#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
-#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
-#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
-#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
-#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
-
-
-#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
-#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
-#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
-#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
-#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
-#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
-#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
-#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
-#if defined(STM32H7)
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
-#else
-#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
-#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
-#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
-#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
-#endif /* STM32H7 */
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
-#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
-#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
-#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
-#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
-#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
-#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
-#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
-#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined(STM32F3)
-#define COMP_START                                       __HAL_COMP_ENABLE
-#define COMP_STOP                                        __HAL_COMP_DISABLE
-#define COMP_LOCK                                        __HAL_COMP_LOCK
-
-#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F302xE) || defined(STM32F302xC)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
-                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
-                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
-# endif
-# if defined(STM32F373xC) ||defined(STM32F378xx)
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-# endif
-#else
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
-                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
-                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
-#endif
-
-#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
-
-#if defined(STM32L0) || defined(STM32L4)
-/* Note: On these STM32 families, the only argument of this macro             */
-/*       is COMP_FLAG_LOCK.                                                   */
-/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
-/*       argument.                                                            */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
-#endif
-/**
-  * @}
-  */
-
-#if defined(STM32L0) || defined(STM32L4)
-/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
-/**
-  * @}
-  */
-#endif
-
-/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
-                           ((WAVE) == DAC_WAVE_NOISE)|| \
-                           ((WAVE) == DAC_WAVE_TRIANGLE))
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_WRPAREA          IS_OB_WRPAREA
-#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
-#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
-#define IS_TYPEERASE        IS_FLASH_TYPEERASE
-#define IS_NBSECTORS        IS_FLASH_NBSECTORS
-#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
-#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
-#if defined(STM32F1)
-#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
-#else
-#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
-#endif /* STM32F1 */
-#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
-#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
-#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
-#define __HAL_I2C_SPEED                 I2C_SPEED
-#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
-#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
-#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
-#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
-#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
-#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
-#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
-#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
-#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
-
-#if defined(STM32H7)
-#define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG
-#endif
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
-#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
-
-#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
-#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
-#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
-#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
-
-#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
-
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
-#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
-#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
-#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
-#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
-#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
-#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
-#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
-#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
-#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
-#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
-#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
-#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
-#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
-#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
-#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
-#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
-#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
-#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
-#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
-#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
-#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
-#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
-#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
-#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
-#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
-#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
-#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
-
-#if defined (STM32F4)
-#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
-#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
-#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
-#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
-#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
-#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
-#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
-#endif /* STM32F4 */
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
-  * @{
-  */
-
-#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
-#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
-
-#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
-#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
-                                         )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-
-#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
-#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
-#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
-#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
-#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
-#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
-#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
-#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
-#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
-#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
-#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
-#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
-#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
-#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
-#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
-#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
-#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
-#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
-#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
-#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
-#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
-#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
-#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
-#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
-#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
-#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
-#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
-#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
-#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
-#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
-#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
-#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
-#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
-#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
-#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
-#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
-#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
-#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
-#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
-#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
-#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
-#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
-#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
-#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
-#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
-#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
-#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
-#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
-#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
-#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
-#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
-#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
-#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
-#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
-#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
-#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
-#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
-#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
-#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
-#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
-#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
-#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
-#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
-#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
-#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
-#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
-#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
-#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
-#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
-#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
-#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
-#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
-#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
-#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
-#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
-#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
-#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
-#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
-#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
-#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
-#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
-#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
-#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
-#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
-#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
-#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
-#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
-#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
-#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
-#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
-#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
-#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
-#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
-#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
-#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
-#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
-#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
-#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
-#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
-#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
-#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
-#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
-#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
-#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
-#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
-#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
-#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
-#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
-#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
-#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
-#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
-#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
-#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
-#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
-#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
-#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
-#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
-#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
-#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
-#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
-#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
-#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
-#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
-#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
-#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
-#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
-#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
-#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
-#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
-#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
-#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
-#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
-#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
-#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
-#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
-#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
-#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
-#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
-#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
-#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
-#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
-#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
-#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
-#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
-#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
-#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
-#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
-#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
-#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
-#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
-#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
-#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
-#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
-#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
-#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
-#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
-#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
-#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
-#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
-#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
-#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
-#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
-#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
-#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
-#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
-#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
-#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
-#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
-#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
-#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
-#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
-#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
-#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
-#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
-#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
-#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
-#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
-#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
-#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
-#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
-#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
-#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
-#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
-#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
-#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
-#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
-#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
-#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
-#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
-#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
-#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
-#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
-#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
-#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
-#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
-#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
-#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
-#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
-#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
-#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
-#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
-#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
-#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
-#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
-#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
-#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
-#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
-#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
-#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
-#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
-#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
-#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
-#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
-#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
-#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
-#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
-#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
-#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
-#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
-#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
-#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
-#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
-#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
-#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
-#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
-#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
-#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
-#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
-#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
-#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
-#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
-#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
-#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
-#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
-#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
-#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
-#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
-#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
-#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
-
-#if defined(STM32WB)
-#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
-#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
-#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
-#define QSPI_IRQHandler QUADSPI_IRQHandler
-#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
-
-#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
-#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
-#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
-#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
-#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
-#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
-#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
-#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
-#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
-#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
-#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
-#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
-#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
-#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
-#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
-#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
-#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
-#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
-#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
-#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
-#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
-#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
-#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
-#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
-#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
-#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
-#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
-#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
-#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
-#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
-#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
-#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
-#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
-#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
-#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
-#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
-#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
-#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
-#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
-#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
-#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
-#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
-#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
-#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
-#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
-#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
-#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
-#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
-#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
-#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
-#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
-#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
-#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
-#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
-#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
-#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
-#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
-#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
-#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
-#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
-#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
-#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
-#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
-#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
-#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
-#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
-#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
-#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
-#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
-#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
-#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
-#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
-#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
-#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
-#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
-#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
-#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
-#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
-#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
-#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
-#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
-#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
-#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
-#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
-#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
-#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
-#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
-#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
-#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
-#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
-#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
-#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
-#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
-#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
-#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
-#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
-#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
-#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
-#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
-#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
-#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
-#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
-#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
-#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
-#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
-#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
-#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
-#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
-#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
-#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
-#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
-#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
-#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
-#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
-#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
-#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
-#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
-#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
-#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
-#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
-#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
-#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
-#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
-#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
-#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
-#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
-#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
-#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
-#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
-#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
-#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
-#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
-#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
-#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
-#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
-#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
-#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
-#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
-#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
-#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
-#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
-#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
-#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
-#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
-#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
-#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
-#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
-#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
-#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
-#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
-#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
-#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
-#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
-#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
-#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
-#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
-#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
-#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
-#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
-#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
-#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
-#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
-#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
-#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
-#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
-#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
-#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
-#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
-#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
-#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
-#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
-#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
-#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
-#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
-#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
-#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
-#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
-#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
-#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
-#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
-#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
-#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
-#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
-#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
-#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
-#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
-#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
-#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
-#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
-#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
-#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
-#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
-#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
-#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
-#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
-#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
-#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
-#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
-#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
-#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
-#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
-#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
-#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
-#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
-#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
-#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
-#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
-#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
-#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
-#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
-
-#if defined(STM32H7)
-#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE
-#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
-
-#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/
-#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
-
-
-#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
-#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
-#endif
-
-#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
-#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
-#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
-#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
-#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
-#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
-
-#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
-#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
-#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
-#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
-#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
-#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
-#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
-#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
-#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
-#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
-#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
-#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
-#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
-#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
-#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
-#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
-#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
-#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
-#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
-#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
-
-#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
-#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
-#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
-#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
-#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
-#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
-#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
-#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
-#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
-#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
-#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
-#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
-#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
-#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
-#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
-#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
-#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
-#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
-#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
-#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
-#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
-#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
-#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
-#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
-#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
-#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
-#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
-#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
-#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
-#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
-#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
-#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
-#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
-#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
-#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
-#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
-#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
-#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
-#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
-#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
-#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
-#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
-#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
-#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
-#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
-#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
-#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
-#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
-#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
-#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
-#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
-#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
-#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
-#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
-#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
-#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
-#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
-#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
-#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
-#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
-#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
-#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
-#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
-#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
-#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
-#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
-#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
-#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
-#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
-#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
-#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
-#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
-#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
-#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
-#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
-#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
-#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
-#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
-#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
-#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
-#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
-#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
-#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
-#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
-#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
-#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
-#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
-#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
-#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
-#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
-#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
-#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
-#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
-
-/* alias define maintained for legacy */
-#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
-#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
-
-#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
-#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
-#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
-#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
-#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
-#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
-#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
-#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
-#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
-#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
-#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
-#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
-#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
-#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
-#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
-#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
-#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
-#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
-#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
-
-#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
-#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
-#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
-#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
-#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
-#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
-#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
-#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
-#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
-#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
-#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
-#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
-#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
-#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
-#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
-#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
-#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
-#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
-#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
-
-#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
-#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
-#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
-#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
-#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
-#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
-#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
-#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
-#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
-#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
-#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
-#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
-#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
-#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
-#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
-#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
-#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
-#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
-#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
-#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
-#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
-#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
-#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
-#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
-#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
-#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
-#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
-#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
-#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
-#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
-#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
-#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
-#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
-#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
-#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
-#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
-#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
-#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
-#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
-#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
-#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
-#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
-#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
-#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
-#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
-#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
-#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
-#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
-#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
-#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
-#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
-#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
-#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
-#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
-#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
-#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
-#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
-#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
-#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
-#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
-#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
-#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
-#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
-#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
-#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
-#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
-#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
-#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
-#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
-#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
-#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
-#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
-#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
-#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
-#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
-#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
-#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
-#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
-#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
-#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
-#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
-#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
-#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
-#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
-#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
-#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
-#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
-#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
-#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
-#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
-#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
-#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
-#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
-#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
-#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
-#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
-#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
-#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
-#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
-#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
-#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
-#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
-#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
-#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
-#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
-#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
-#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
-#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
-#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
-#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
-#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
-#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
-#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
-#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
-
-#if defined(STM32L1)
-#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE
-#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE
-#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE
-#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE
-#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET
-#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET
-#endif /* STM32L1 */
-
-#if defined(STM32F4)
-#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
-#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
-#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
-#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
-#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
-#define Sdmmc1ClockSelection               SdioClockSelection
-#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
-#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
-#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
-#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
-#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
-#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
-#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
-#define SdioClockSelection                 Sdmmc1ClockSelection
-#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
-#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
-#endif
-
-#if defined(STM32F7)
-#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
-#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
-#endif
-
-#if defined(STM32H7)
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
-
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
-#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
-#endif
-
-#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
-#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
-
-#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
-
-#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
-#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
-#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
-#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
-#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
-
-#define RCC_IT_HSI14                RCC_IT_HSI14RDY
-
-#define RCC_IT_CSSLSE               RCC_IT_LSECSS
-#define RCC_IT_CSSHSE               RCC_IT_CSS
-
-#define RCC_PLLMUL_3                RCC_PLL_MUL3
-#define RCC_PLLMUL_4                RCC_PLL_MUL4
-#define RCC_PLLMUL_6                RCC_PLL_MUL6
-#define RCC_PLLMUL_8                RCC_PLL_MUL8
-#define RCC_PLLMUL_12               RCC_PLL_MUL12
-#define RCC_PLLMUL_16               RCC_PLL_MUL16
-#define RCC_PLLMUL_24               RCC_PLL_MUL24
-#define RCC_PLLMUL_32               RCC_PLL_MUL32
-#define RCC_PLLMUL_48               RCC_PLL_MUL48
-
-#define RCC_PLLDIV_2                RCC_PLL_DIV2
-#define RCC_PLLDIV_3                RCC_PLL_DIV3
-#define RCC_PLLDIV_4                RCC_PLL_DIV4
-
-#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
-#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
-#define RCC_MCO_NODIV               RCC_MCODIV_1
-#define RCC_MCO_DIV1                RCC_MCODIV_1
-#define RCC_MCO_DIV2                RCC_MCODIV_2
-#define RCC_MCO_DIV4                RCC_MCODIV_4
-#define RCC_MCO_DIV8                RCC_MCODIV_8
-#define RCC_MCO_DIV16               RCC_MCODIV_16
-#define RCC_MCO_DIV32               RCC_MCODIV_32
-#define RCC_MCO_DIV64               RCC_MCODIV_64
-#define RCC_MCO_DIV128              RCC_MCODIV_128
-#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
-#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
-#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
-#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
-#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
-#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
-#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
-#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
-#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
-#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
-
-#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0)
-#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
-#else
-#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
-#endif
-
-#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
-#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
-#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
-#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
-#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
-#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
-#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
-
-#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
-#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
-#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
-#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
-#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
-#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
-#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
-#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
-#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
-#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
-#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
-#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
-#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
-#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
-#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
-#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
-#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
-#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
-#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
-#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
-#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
-#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
-#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
-#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
-#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
-#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
-#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
-#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
-#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
-#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
-#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
-#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
-
-#define CR_HSION_BB            RCC_CR_HSION_BB
-#define CR_CSSON_BB            RCC_CR_CSSON_BB
-#define CR_PLLON_BB            RCC_CR_PLLON_BB
-#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
-#define CR_MSION_BB            RCC_CR_MSION_BB
-#define CSR_LSION_BB           RCC_CSR_LSION_BB
-#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
-#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
-#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
-#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
-#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
-#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
-#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
-#define CR_HSEON_BB            RCC_CR_HSEON_BB
-#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
-#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
-#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
-
-#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
-#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
-#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
-#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
-#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
-
-#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
-
-#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
-#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
-
-#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
-#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
-#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
-#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
-#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
-#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
-
-#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
-#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
-#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
-#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
-#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
-#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
-#define DfsdmClockSelection         Dfsdm1ClockSelection
-#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
-#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
-#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
-#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
-#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
-#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
-#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
-
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
-#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
-#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
-#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
-#if defined(STM32U5)
-#define MSIKPLLModeSEL                        RCC_MSIKPLL_MODE_SEL
-#define MSISPLLModeSEL                        RCC_MSISPLL_MODE_SEL
-#define __HAL_RCC_AHB21_CLK_DISABLE           __HAL_RCC_AHB2_1_CLK_DISABLE
-#define __HAL_RCC_AHB22_CLK_DISABLE           __HAL_RCC_AHB2_2_CLK_DISABLE
-#define __HAL_RCC_AHB1_CLK_Disable_Clear      __HAL_RCC_AHB1_CLK_ENABLE
-#define __HAL_RCC_AHB21_CLK_Disable_Clear     __HAL_RCC_AHB2_1_CLK_ENABLE
-#define __HAL_RCC_AHB22_CLK_Disable_Clear     __HAL_RCC_AHB2_2_CLK_ENABLE
-#define __HAL_RCC_AHB3_CLK_Disable_Clear      __HAL_RCC_AHB3_CLK_ENABLE
-#define __HAL_RCC_APB1_CLK_Disable_Clear      __HAL_RCC_APB1_CLK_ENABLE
-#define __HAL_RCC_APB2_CLK_Disable_Clear      __HAL_RCC_APB2_CLK_ENABLE
-#define __HAL_RCC_APB3_CLK_Disable_Clear      __HAL_RCC_APB3_CLK_ENABLE
-#define IS_RCC_MSIPLLModeSelection            IS_RCC_MSIPLLMODE_SELECT
-#define RCC_PERIPHCLK_CLK48                   RCC_PERIPHCLK_ICLK
-#define RCC_CLK48CLKSOURCE_HSI48              RCC_ICLK_CLKSOURCE_HSI48
-#define RCC_CLK48CLKSOURCE_PLL2               RCC_ICLK_CLKSOURCE_PLL2
-#define RCC_CLK48CLKSOURCE_PLL1               RCC_ICLK_CLKSOURCE_PLL1
-#define RCC_CLK48CLKSOURCE_MSIK               RCC_ICLK_CLKSOURCE_MSIK
-#define __HAL_RCC_ADC1_CLK_ENABLE             __HAL_RCC_ADC12_CLK_ENABLE
-#define __HAL_RCC_ADC1_CLK_DISABLE            __HAL_RCC_ADC12_CLK_DISABLE
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED         __HAL_RCC_ADC12_IS_CLK_ENABLED
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED        __HAL_RCC_ADC12_IS_CLK_DISABLED
-#define __HAL_RCC_ADC1_FORCE_RESET            __HAL_RCC_ADC12_FORCE_RESET
-#define __HAL_RCC_ADC1_RELEASE_RESET          __HAL_RCC_ADC12_RELEASE_RESET
-#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE       __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
-#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE      __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
-#define __HAL_RCC_GET_CLK48_SOURCE            __HAL_RCC_GET_ICLK_SOURCE
-#define __HAL_RCC_PLLFRACN_ENABLE             __HAL_RCC_PLL_FRACN_ENABLE
-#define __HAL_RCC_PLLFRACN_DISABLE            __HAL_RCC_PLL_FRACN_DISABLE
-#define __HAL_RCC_PLLFRACN_CONFIG             __HAL_RCC_PLL_FRACN_CONFIG
-#define IS_RCC_PLLFRACN_VALUE                 IS_RCC_PLL_FRACN_VALUE
-#endif /* STM32U5 */
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \
-    defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
-    defined (STM32C0)
-#else
-#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
-#endif
-#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
-#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
-
-#if defined (STM32F1)
-#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
-
-#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
-
-#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
-
-#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
-
-#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
-#else
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
-                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
-                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
-                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
-#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
-                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
-                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
-                                                       (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
-                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
-#endif   /* STM32F1 */
-
-#define IS_ALARM                                  IS_RTC_ALARM
-#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
-#define IS_TAMPER                                 IS_RTC_TAMPER
-#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
-#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
-#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
-#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
-#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
-#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
-#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
-#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
-#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
-
-#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
-#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
-#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
-
-#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
-#define eMMC_HIGH_VOLTAGE_RANGE     EMMC_HIGH_VOLTAGE_RANGE
-#define eMMC_DUAL_VOLTAGE_RANGE     EMMC_DUAL_VOLTAGE_RANGE
-#define eMMC_LOW_VOLTAGE_RANGE      EMMC_LOW_VOLTAGE_RANGE
-
-#define SDMMC_NSpeed_CLK_DIV        SDMMC_NSPEED_CLK_DIV
-#define SDMMC_HSpeed_CLK_DIV        SDMMC_HSPEED_CLK_DIV
-#endif
-
-#if defined(STM32F4) || defined(STM32F2)
-#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
-#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
-#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
-#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
-#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
-#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
-#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
-#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
-#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
-#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
-#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
-#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
-#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
-#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
-#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
-#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
-#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
-#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
-#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
-#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
-/* alias CMSIS */
-#define  SDMMC1_IRQn                SDIO_IRQn
-#define  SDMMC1_IRQHandler          SDIO_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32L4)
-#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
-#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
-#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
-#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
-#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
-#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
-#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
-#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
-#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
-#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
-#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
-#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
-#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
-#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
-#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
-#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
-#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
-#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS
-#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT
-#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND
-/* alias CMSIS for compatibilities */
-#define  SDIO_IRQn                  SDMMC1_IRQn
-#define  SDIO_IRQHandler            SDMMC1_IRQHandler
-#endif
-
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
-#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
-#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
-#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
-#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
-#endif
-
-#if defined(STM32H7) || defined(STM32L5)
-#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
-#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
-#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
-#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
-#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
-#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
-#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
-#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
-#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
-#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
-#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
-#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
-#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
-#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
-
-#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
-#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
-
-#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
-#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
-#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
-#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
-#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
-#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
-#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
-#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
-#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
-#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
-#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
-#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
-#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
-
-#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
-
-#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
-#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
-
-/**
-  * @}
-  */
-
-
-/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
-#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
-#define __USART_ENABLE                  __HAL_USART_ENABLE
-#define __USART_DISABLE                 __HAL_USART_DISABLE
-
-#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
-#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
-
-#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
-#define USART_OVERSAMPLING_16               0x00000000U
-#define USART_OVERSAMPLING_8                USART_CR1_OVER8
-
-#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
-                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))
-#endif /* STM32F0 || STM32F3 || STM32F7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
-
-#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
-#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
-
-#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
-#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
-#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
-#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
-
-#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-
-#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
-#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
-#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
-
-#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
-#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
-
-#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
-#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
-/**
-  * @}
-  */
-
-/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
-#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
-
-#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
-#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
-
-#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
-
-#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
-#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
-#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
-#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
-#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
-#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
-#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
-#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
-#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
-#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
-#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
-#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
-
-#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
-/**
-  * @}
-  */
-
-/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
-#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
-#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
-#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
-#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
-#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
-
-#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
-#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
-#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define __HAL_LTDC_LAYER LTDC_LAYER
-#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
-#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
-#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
-#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
-#define SAI_STREOMODE                     SAI_STEREOMODE
-#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
-#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
-#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
-#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
-#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
-#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
-#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
-#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
-#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined(STM32H7)
-#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
-#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
-#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
-  * @{
-  */
-#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
-#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT
-#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA
-#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart
-#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT
-#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA
-#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
-#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
-#endif /* STM32L4 || STM32F4 || STM32F7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
-  * @{
-  */
-#if defined (STM32F7)
-#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
-#endif /* STM32F7 */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32_HAL_LEGACY */
-
-
+/**
+  ******************************************************************************
+  * @file    stm32_hal_legacy.h
+  * @author  MCD Application Team
+  * @brief   This file contains aliases definition for the STM32Cube HAL constants
+  *          macros and functions maintained for legacy purpose.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2021 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32_HAL_LEGACY
+#define STM32_HAL_LEGACY
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
+#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
+#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
+#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
+#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
+#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
+#define CRYP_DATATYPE_32B               CRYP_NO_SWAP
+#define CRYP_DATATYPE_16B               CRYP_HALFWORD_SWAP
+#define CRYP_DATATYPE_8B                CRYP_BYTE_SWAP
+#define CRYP_DATATYPE_1B                CRYP_BIT_SWAP
+#if defined(STM32U5)
+#define CRYP_CCF_CLEAR                  CRYP_CLEAR_CCF
+#define CRYP_ERR_CLEAR                  CRYP_CLEAR_RWEIF
+#endif /* STM32U5 */
+#endif /* STM32U5 || STM32H7 || STM32MP1 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
+#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
+#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
+#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
+#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
+#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
+#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
+#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
+#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
+#define REGULAR_GROUP                   ADC_REGULAR_GROUP
+#define INJECTED_GROUP                  ADC_INJECTED_GROUP
+#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
+#define AWD_EVENT                       ADC_AWD_EVENT
+#define AWD1_EVENT                      ADC_AWD1_EVENT
+#define AWD2_EVENT                      ADC_AWD2_EVENT
+#define AWD3_EVENT                      ADC_AWD3_EVENT
+#define OVR_EVENT                       ADC_OVR_EVENT
+#define JQOVF_EVENT                     ADC_JQOVF_EVENT
+#define ALL_CHANNELS                    ADC_ALL_CHANNELS
+#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
+#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
+#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
+#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
+#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
+#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
+#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
+#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
+#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
+#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
+#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
+#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
+#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
+#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
+#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
+#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
+
+#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
+#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
+#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
+#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
+#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
+#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
+#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
+
+#if defined(STM32H7)
+#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
+#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define ADC_SAMPLETIME_5CYCLE           ADC_SAMPLETIME_5CYCLES
+#define ADC_SAMPLETIME_391CYCLES_5      ADC_SAMPLETIME_391CYCLES
+#define ADC4_SAMPLETIME_160CYCLES_5     ADC4_SAMPLETIME_814CYCLES_5
+#endif /* STM32U5 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
+#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
+#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
+#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
+#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
+#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
+#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
+#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
+#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
+#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
+#if defined(STM32F373xC) || defined(STM32F378xx)
+#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
+#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
+#endif /* STM32F373xC || STM32F378xx */
+
+#if defined(STM32L0) || defined(STM32L4)
+#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
+
+#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
+#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
+#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
+#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
+#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
+#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
+
+#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
+#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
+#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
+#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
+#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
+#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
+#if defined(STM32L0)
+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
+/* to the second dedicated IO (only for COMP2).                               */
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
+#else
+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
+#endif
+#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
+#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
+
+#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
+#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
+
+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
+/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
+#if defined(COMP_CSR_LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
+#elif defined(COMP_CSR_COMP1LOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
+#elif defined(COMP_CSR_COMPxLOCK)
+#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
+#endif
+
+#if defined(STM32L4)
+#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
+#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
+#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
+#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
+#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
+#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
+#endif
+
+#if defined(STM32L0)
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
+#else
+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
+#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
+#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
+#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
+#endif
+
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
+#if defined(STM32U5)
+#define  MPU_DEVICE_nGnRnE          MPU_DEVICE_NGNRNE
+#define  MPU_DEVICE_nGnRE           MPU_DEVICE_NGNRE
+#define  MPU_DEVICE_nGRE            MPU_DEVICE_NGRE
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup CRC_Aliases CRC API aliases
+  * @{
+  */
+#if defined(STM32C0)
+#else
+#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility  */
+#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
+#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
+#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
+#define DAC_WAVE_NONE                                   0x00000000U
+#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
+#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
+#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
+#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
+#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
+
+#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
+#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32U5)
+#define DAC_TRIGGER_STOP_LPTIM1_OUT  DAC_TRIGGER_STOP_LPTIM1_CH1
+#define DAC_TRIGGER_STOP_LPTIM3_OUT  DAC_TRIGGER_STOP_LPTIM3_CH1
+#define DAC_TRIGGER_LPTIM1_OUT       DAC_TRIGGER_LPTIM1_CH1
+#define DAC_TRIGGER_LPTIM3_OUT       DAC_TRIGGER_LPTIM3_CH1
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
+#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
+#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
+#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
+#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
+#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
+#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
+
+#if defined(STM32L4)
+
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE
+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
+#endif
+
+#endif /* STM32L4 */
+
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2
+#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM
+#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM
+
+#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM
+#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM
+#endif
+
+#if defined(STM32H7)
+
+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
+#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
+#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
+
+#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT
+
+#endif /* STM32H7 */
+
+#if defined(STM32U5)
+#define GPDMA1_REQUEST_DCMI                        GPDMA1_REQUEST_DCMI_PSSI
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
+#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
+#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
+#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
+#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
+#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
+#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
+#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
+#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
+#define OBEX_PCROP                    OPTIONBYTE_PCROP
+#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
+#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
+#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
+#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
+#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
+#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
+#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
+#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
+#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
+#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
+#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
+#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
+#define PAGESIZE                      FLASH_PAGE_SIZE
+#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
+#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
+#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
+#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
+#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
+#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
+#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
+#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
+#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
+#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
+#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
+#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
+#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
+#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
+#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
+#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
+#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
+#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
+#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
+#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
+#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
+#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
+#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
+#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
+#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
+#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
+#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
+#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
+#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
+#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
+#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
+#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
+#define OB_WDG_SW                     OB_IWDG_SW
+#define OB_WDG_HW                     OB_IWDG_HW
+#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
+#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
+#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
+#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
+#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
+#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
+#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
+#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
+#if defined(STM32G0) || defined(STM32C0)
+#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
+#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
+#else
+#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE
+#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
+#endif
+#if defined(STM32H7)
+#define FLASH_FLAG_SNECCE_BANK1RR     FLASH_FLAG_SNECCERR_BANK1
+#define FLASH_FLAG_DBECCE_BANK1RR     FLASH_FLAG_DBECCERR_BANK1
+#define FLASH_FLAG_STRBER_BANK1R      FLASH_FLAG_STRBERR_BANK1
+#define FLASH_FLAG_SNECCE_BANK2RR     FLASH_FLAG_SNECCERR_BANK2
+#define FLASH_FLAG_DBECCE_BANK2RR     FLASH_FLAG_DBECCERR_BANK2
+#define FLASH_FLAG_STRBER_BANK2R      FLASH_FLAG_STRBERR_BANK2
+#define FLASH_FLAG_WDW                FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All             OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
+#if defined(STM32U5)
+#define OB_USER_nRST_STOP             OB_USER_NRST_STOP
+#define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
+#define OB_USER_nRST_SHDW             OB_USER_NRST_SHDW
+#define OB_USER_nSWBOOT0              OB_USER_NSWBOOT0
+#define OB_USER_nBOOT0                OB_USER_NBOOT0
+#define OB_nBOOT0_RESET               OB_NBOOT0_RESET
+#define OB_nBOOT0_SET                 OB_NBOOT0_SET
+#endif /* STM32U5 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32H7)
+#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
+#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
+#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
+#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
+#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
+#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
+#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
+
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
+  * @{
+  */
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
+#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
+#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
+#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
+#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
+#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
+/**
+  * @}
+  */
+
+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
+#define GET_GPIO_INDEX                            GPIO_GET_INDEX
+
+#if defined(STM32F4)
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
+#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
+#endif
+
+#if defined(STM32F7)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32L4)
+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
+#endif
+
+#if defined(STM32H7)
+#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1
+#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1
+#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1
+#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
+#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
+#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
+
+#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \
+    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
+
+#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
+#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
+#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
+
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
+#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
+#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
+
+#if defined(STM32L1)
+#define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
+#define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L1 */
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
+#define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
+#define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
+#endif /* STM32F0 || STM32F3 || STM32F1 */
+
+#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
+
+#if defined(STM32U5)
+#define GPIO_AF0_RTC_50Hz                         GPIO_AF0_RTC_50HZ
+#endif /* STM32U5 */
+#if defined(STM32U5)
+#define GPIO_AF0_S2DSTOP                          GPIO_AF0_SRDSTOP
+#define GPIO_AF11_LPGPIO                          GPIO_AF11_LPGPIO1
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32U5)
+#define GTZC_PERIPH_DCMI                      GTZC_PERIPH_DCMI_PSSI
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
+
+#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
+#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
+#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
+#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
+#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
+#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
+
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
+#define HRTIM_TIMEEVENT_A                       HRTIM_EVENTCOUNTER_A
+#define HRTIM_TIMEEVENT_B                       HRTIM_EVENTCOUNTER_B
+#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL  HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
+#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL    HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+  */
+#define HRTIM_EVENTSRC_1              (0x00000000U)
+#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+  */
+#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
+#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
+#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
+#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
+#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
+#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
+#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
+#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
+#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
+#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
+#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
+#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
+#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
+#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
+#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
+#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
+
+#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
+#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
+
+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+/* The following 3 definition have also been present in a temporary version of lptim.h */
+/* They need to be renamed also to the right name, just in case */
+#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+
+
+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_LPTIM_ReadCompare      HAL_LPTIM_ReadCapturedValue
+/**
+  * @}
+  */
+
+#if defined(STM32U5)
+#define LPTIM_ISR_CC1        LPTIM_ISR_CC1IF
+#define LPTIM_ISR_CC2        LPTIM_ISR_CC2IF
+#define LPTIM_CHANNEL_ALL    0x00000000U
+#endif /* STM32U5 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
+#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
+#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
+#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
+
+#define NAND_AddressTypedef             NAND_AddressTypeDef
+
+#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
+#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
+#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
+#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
+#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
+#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
+#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
+#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
+#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
+
+#define __NOR_WRITE                    NOR_WRITE
+#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
+/**
+  * @}
+  */
+
+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
+#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
+#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
+#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
+
+#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
+#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
+#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
+
+#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
+#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
+
+#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
+#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
+
+#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
+#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
+
+#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
+#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
+#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
+#endif
+
+#if defined(STM32L4) || defined(STM32L5)
+#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALPOWER
+#elif defined(STM32G4)
+#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALSPEED
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
+
+#if defined(STM32H7)
+#define I2S_IT_TXE               I2S_IT_TXP
+#define I2S_IT_RXNE              I2S_IT_RXP
+
+#define I2S_FLAG_TXE             I2S_FLAG_TXP
+#define I2S_FLAG_RXNE            I2S_FLAG_RXP
+#endif
+
+#if defined(STM32F7)
+#define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/* Compact Flash-ATA registers description */
+#define CF_DATA                       ATA_DATA
+#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD                  ATA_CARD_HEAD
+#define CF_STATUS_CMD                 ATA_STATUS_CMD
+#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
+#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
+
+/* Compact Flash-ATA commands */
+#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
+#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
+#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
+#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
+
+#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
+#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
+#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
+#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
+#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define FORMAT_BIN                  RTC_FORMAT_BIN
+#define FORMAT_BCD                  RTC_FORMAT_BCD
+
+#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
+#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
+#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
+
+#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
+#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
+
+#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
+#define RTC_TIMESTAMPPIN_PA0   RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PI8   RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
+
+#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
+#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
+#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
+
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
+
+#if defined(STM32F7)
+#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_ENABLE_BITS_MASK
+#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_IT_ENABLE_BITS_MASK
+#endif /* STM32F7 */
+
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
+#endif /* STM32H7 */
+
+#if defined(STM32F7) || defined(STM32H7)
+#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMP
+#endif /* STM32F7 || STM32H7 */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
+#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
+
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
+
+#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
+#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
+
+#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
+#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
+#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
+#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
+#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
+#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
+#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
+#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
+#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
+#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
+#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
+#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
+#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
+
+#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
+#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
+
+#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
+#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
+
+#if defined(STM32H7)
+
+#define SPI_FLAG_TXE                    SPI_FLAG_TXP
+#define SPI_FLAG_RXNE                   SPI_FLAG_RXP
+
+#define SPI_IT_TXE                      SPI_IT_TXP
+#define SPI_IT_RXNE                     SPI_IT_RXP
+
+#define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET
+#define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET
+#define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET
+#define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET
+
+#endif /* STM32H7 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
+#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
+
+#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
+#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
+#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
+#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
+#define TIM_DMABase_SR                   TIM_DMABASE_SR
+#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
+#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
+#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
+#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
+#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
+#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
+#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
+#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
+#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
+#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
+#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
+#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
+#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
+#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
+#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
+#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
+#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
+#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
+#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
+#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
+#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
+#define TIM_DMABase_OR                   TIM_DMABASE_OR
+
+#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
+#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
+#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
+#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
+#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
+#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
+#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
+#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
+#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
+
+#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
+#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
+#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
+#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
+#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
+#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
+#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
+#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
+#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
+#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
+#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
+#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
+#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
+#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
+#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
+#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
+#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
+#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
+
+#if defined(STM32L0)
+#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO
+#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO
+#endif
+
+#if defined(STM32F3)
+#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
+#endif
+
+#if defined(STM32H7)
+#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1
+#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2
+#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1
+#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2
+#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1
+#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2
+#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1
+#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1
+#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2
+#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1
+#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2
+#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2
+#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1
+#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2
+#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
+#endif
+
+#if defined(STM32U5) || defined(STM32MP2)
+#define OCREF_CLEAR_SELECT_Pos       OCREF_CLEAR_SELECT_POS
+#define OCREF_CLEAR_SELECT_Msk       OCREF_CLEAR_SELECT_MSK
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
+#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
+#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
+#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
+
+#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
+#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
+
+#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
+#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
+#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
+#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
+
+#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
+#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
+#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
+#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
+
+#define __DIV_LPUART                    UART_DIV_LPUART
+
+#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
+#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
+#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
+
+#define USARTNACK_ENABLED               USART_NACK_ENABLE
+#define USARTNACK_DISABLED              USART_NACK_DISABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CFR_BASE                    WWDG_CFR_BASE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
+#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
+#define CAN_IT_RQCP0                CAN_IT_TME
+#define CAN_IT_RQCP1                CAN_IT_TME
+#define CAN_IT_RQCP2                CAN_IT_TME
+#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
+#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
+#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
+#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+#define VLAN_TAG                ETH_VLAN_TAG
+#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
+#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
+#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
+#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
+#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
+#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
+#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
+
+#define ETH_MMCCR              0x00000100U
+#define ETH_MMCRIR             0x00000104U
+#define ETH_MMCTIR             0x00000108U
+#define ETH_MMCRIMR            0x0000010CU
+#define ETH_MMCTIMR            0x00000110U
+#define ETH_MMCTGFSCCR         0x0000014CU
+#define ETH_MMCTGFMSCCR        0x00000150U
+#define ETH_MMCTGFCR           0x00000168U
+#define ETH_MMCRFCECR          0x00000194U
+#define ETH_MMCRFAECR          0x00000198U
+#define ETH_MMCRGUFCR          0x000001C4U
+
+#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
+#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
+#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
+#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
+#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
+#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
+#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
+#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
+#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
+#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
+#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
+#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
+#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
+#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
+#define DCMI_IT_OVF             DCMI_IT_OVR
+#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
+#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
+
+#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
+#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
+#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
+
+/**
+  * @}
+  */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+  || defined(STM32H7)
+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
+  * @{
+  */
+#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
+#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
+#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
+#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
+
+#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
+#define CM_RGB888               DMA2D_INPUT_RGB888
+#define CM_RGB565               DMA2D_INPUT_RGB565
+#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
+#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
+#define CM_L8                   DMA2D_INPUT_L8
+#define CM_AL44                 DMA2D_INPUT_AL44
+#define CM_AL88                 DMA2D_INPUT_AL88
+#define CM_L4                   DMA2D_INPUT_L4
+#define CM_A8                   DMA2D_INPUT_A8
+#define CM_A4                   DMA2D_INPUT_A4
+/**
+  * @}
+  */
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
+  || defined(STM32H7) || defined(STM32U5)
+/** @defgroup DMA2D_Aliases DMA2D API Aliases
+  * @{
+  */
+#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
+                                                                        for compatibility with legacy code */
+/**
+  * @}
+  */
+
+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 || STM32U5 */
+
+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32U5)
+#define HAL_DCACHE_CleanInvalidateByAddr     HAL_DCACHE_CleanInvalidByAddr
+#define HAL_DCACHE_CleanInvalidateByAddr_IT  HAL_DCACHE_CleanInvalidByAddr_IT
+#endif /* STM32U5 */
+
+/**
+  * @}
+  */
+
+#if !defined(STM32F2)
+/** @defgroup HASH_alias HASH API alias
+  * @{
+  */
+#define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< Redirection for compatibility with legacy code */
+/**
+  *
+  * @}
+  */
+#endif /* STM32F2 */
+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
+#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
+#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
+#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
+#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
+#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
+
+/*HASH Algorithm Selection*/
+
+#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
+#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
+#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
+
+#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
+
+#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
+#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
+                                              )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
+#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
+#if defined(STM32L0)
+#else
+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
+#endif
+#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
+                                              )==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
+#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
+#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
+#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
+#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
+#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
+#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
+
+/**
+  * @}
+ */
+
+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
+#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
+#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
+#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
+
+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
+                                                                 )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
+
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
+#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
+#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
+#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
+#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
+#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
+#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
+
+#if defined(STM32F4)
+#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
+#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT
+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT
+#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT
+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
+#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA
+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA
+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA
+#endif /* STM32F4 */
+/**
+  * @}
+ */
+
+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
+  * @{
+  */
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler
+#endif
+#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
+#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
+#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
+#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
+#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
+#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
+#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
+#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
+#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
+#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
+#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
+#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
+#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
+#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
+#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
+#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
+
+#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
+#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
+#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
+#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
+#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
+#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
+#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
+
+#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
+#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER
+#define CR_PMODE_BB                                   CR_VOS_BB
+
+#define DBP_BitNumber                                 DBP_BIT_NUMBER
+#define PVDE_BitNumber                                PVDE_BIT_NUMBER
+#define PMODE_BitNumber                               PMODE_BIT_NUMBER
+#define EWUP_BitNumber                                EWUP_BIT_NUMBER
+#define FPDS_BitNumber                                FPDS_BIT_NUMBER
+#define ODEN_BitNumber                                ODEN_BIT_NUMBER
+#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
+#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
+#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
+#define BRE_BitNumber                                 BRE_BIT_NUMBER
+
+#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
+
+#if defined (STM32U5)
+#define PWR_SRAM1_PAGE1_STOP_RETENTION                PWR_SRAM1_PAGE1_STOP
+#define PWR_SRAM1_PAGE2_STOP_RETENTION                PWR_SRAM1_PAGE2_STOP
+#define PWR_SRAM1_PAGE3_STOP_RETENTION                PWR_SRAM1_PAGE3_STOP
+#define PWR_SRAM1_PAGE4_STOP_RETENTION                PWR_SRAM1_PAGE4_STOP
+#define PWR_SRAM1_PAGE5_STOP_RETENTION                PWR_SRAM1_PAGE5_STOP
+#define PWR_SRAM1_PAGE6_STOP_RETENTION                PWR_SRAM1_PAGE6_STOP
+#define PWR_SRAM1_PAGE7_STOP_RETENTION                PWR_SRAM1_PAGE7_STOP
+#define PWR_SRAM1_PAGE8_STOP_RETENTION                PWR_SRAM1_PAGE8_STOP
+#define PWR_SRAM1_PAGE9_STOP_RETENTION                PWR_SRAM1_PAGE9_STOP
+#define PWR_SRAM1_PAGE10_STOP_RETENTION               PWR_SRAM1_PAGE10_STOP
+#define PWR_SRAM1_PAGE11_STOP_RETENTION               PWR_SRAM1_PAGE11_STOP
+#define PWR_SRAM1_PAGE12_STOP_RETENTION               PWR_SRAM1_PAGE12_STOP
+#define PWR_SRAM1_FULL_STOP_RETENTION                 PWR_SRAM1_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STOP_RETENTION                PWR_SRAM2_PAGE1_STOP
+#define PWR_SRAM2_PAGE2_STOP_RETENTION                PWR_SRAM2_PAGE2_STOP
+#define PWR_SRAM2_FULL_STOP_RETENTION                 PWR_SRAM2_FULL_STOP
+
+#define PWR_SRAM3_PAGE1_STOP_RETENTION                PWR_SRAM3_PAGE1_STOP
+#define PWR_SRAM3_PAGE2_STOP_RETENTION                PWR_SRAM3_PAGE2_STOP
+#define PWR_SRAM3_PAGE3_STOP_RETENTION                PWR_SRAM3_PAGE3_STOP
+#define PWR_SRAM3_PAGE4_STOP_RETENTION                PWR_SRAM3_PAGE4_STOP
+#define PWR_SRAM3_PAGE5_STOP_RETENTION                PWR_SRAM3_PAGE5_STOP
+#define PWR_SRAM3_PAGE6_STOP_RETENTION                PWR_SRAM3_PAGE6_STOP
+#define PWR_SRAM3_PAGE7_STOP_RETENTION                PWR_SRAM3_PAGE7_STOP
+#define PWR_SRAM3_PAGE8_STOP_RETENTION                PWR_SRAM3_PAGE8_STOP
+#define PWR_SRAM3_PAGE9_STOP_RETENTION                PWR_SRAM3_PAGE9_STOP
+#define PWR_SRAM3_PAGE10_STOP_RETENTION               PWR_SRAM3_PAGE10_STOP
+#define PWR_SRAM3_PAGE11_STOP_RETENTION               PWR_SRAM3_PAGE11_STOP
+#define PWR_SRAM3_PAGE12_STOP_RETENTION               PWR_SRAM3_PAGE12_STOP
+#define PWR_SRAM3_PAGE13_STOP_RETENTION               PWR_SRAM3_PAGE13_STOP
+#define PWR_SRAM3_FULL_STOP_RETENTION                 PWR_SRAM3_FULL_STOP
+
+#define PWR_SRAM4_FULL_STOP_RETENTION                 PWR_SRAM4_FULL_STOP
+
+#define PWR_SRAM5_PAGE1_STOP_RETENTION                PWR_SRAM5_PAGE1_STOP
+#define PWR_SRAM5_PAGE2_STOP_RETENTION                PWR_SRAM5_PAGE2_STOP
+#define PWR_SRAM5_PAGE3_STOP_RETENTION                PWR_SRAM5_PAGE3_STOP
+#define PWR_SRAM5_PAGE4_STOP_RETENTION                PWR_SRAM5_PAGE4_STOP
+#define PWR_SRAM5_PAGE5_STOP_RETENTION                PWR_SRAM5_PAGE5_STOP
+#define PWR_SRAM5_PAGE6_STOP_RETENTION                PWR_SRAM5_PAGE6_STOP
+#define PWR_SRAM5_PAGE7_STOP_RETENTION                PWR_SRAM5_PAGE7_STOP
+#define PWR_SRAM5_PAGE8_STOP_RETENTION                PWR_SRAM5_PAGE8_STOP
+#define PWR_SRAM5_PAGE9_STOP_RETENTION                PWR_SRAM5_PAGE9_STOP
+#define PWR_SRAM5_PAGE10_STOP_RETENTION               PWR_SRAM5_PAGE10_STOP
+#define PWR_SRAM5_PAGE11_STOP_RETENTION               PWR_SRAM5_PAGE11_STOP
+#define PWR_SRAM5_PAGE12_STOP_RETENTION               PWR_SRAM5_PAGE12_STOP
+#define PWR_SRAM5_PAGE13_STOP_RETENTION               PWR_SRAM5_PAGE13_STOP
+#define PWR_SRAM5_FULL_STOP_RETENTION                 PWR_SRAM5_FULL_STOP
+
+#define PWR_ICACHE_FULL_STOP_RETENTION                PWR_ICACHE_FULL_STOP
+#define PWR_DCACHE1_FULL_STOP_RETENTION               PWR_DCACHE1_FULL_STOP
+#define PWR_DCACHE2_FULL_STOP_RETENTION               PWR_DCACHE2_FULL_STOP
+#define PWR_DMA2DRAM_FULL_STOP_RETENTION              PWR_DMA2DRAM_FULL_STOP
+#define PWR_PERIPHRAM_FULL_STOP_RETENTION             PWR_PERIPHRAM_FULL_STOP
+#define PWR_PKA32RAM_FULL_STOP_RETENTION              PWR_PKA32RAM_FULL_STOP
+#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION           PWR_GRAPHICPRAM_FULL_STOP
+#define PWR_DSIRAM_FULL_STOP_RETENTION                PWR_DSIRAM_FULL_STOP
+
+#define PWR_SRAM2_PAGE1_STANDBY_RETENTION             PWR_SRAM2_PAGE1_STANDBY
+#define PWR_SRAM2_PAGE2_STANDBY_RETENTION             PWR_SRAM2_PAGE2_STANDBY
+#define PWR_SRAM2_FULL_STANDBY_RETENTION              PWR_SRAM2_FULL_STANDBY
+
+#define PWR_SRAM1_FULL_RUN_RETENTION                  PWR_SRAM1_FULL_RUN
+#define PWR_SRAM2_FULL_RUN_RETENTION                  PWR_SRAM2_FULL_RUN
+#define PWR_SRAM3_FULL_RUN_RETENTION                  PWR_SRAM3_FULL_RUN
+#define PWR_SRAM4_FULL_RUN_RETENTION                  PWR_SRAM4_FULL_RUN
+#define PWR_SRAM5_FULL_RUN_RETENTION                  PWR_SRAM5_FULL_RUN
+
+#define PWR_ALL_RAM_RUN_RETENTION_MASK                PWR_ALL_RAM_RUN_MASK
+#endif
+
+/**
+  * @}
+ */
+
+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
+#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
+#define HAL_TIM_DMAError                                TIM_DMAError
+#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
+#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
+#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
+#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
+#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
+#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
+#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod           HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+
+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define AES_IT_CC                      CRYP_IT_CC
+#define AES_IT_ERR                     CRYP_IT_ERR
+#define AES_FLAG_CCF                   CRYP_FLAG_CCF
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
+#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
+#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
+#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
+#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
+#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
+#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
+#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
+#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
+#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
+#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
+#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
+
+#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
+#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
+#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
+#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
+#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
+#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
+#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
+#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
+#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
+#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
+#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
+#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
+
+#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
+#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
+#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
+#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
+#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
+#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
+#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
+#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
+#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
+#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
+#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
+#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
+#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
+#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
+#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
+
+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
+#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
+#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
+#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
+#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
+#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
+#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
+
+#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
+#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
+#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
+#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
+#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
+#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
+#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
+
+#define __HAL_ADC_SQR1                                   ADC_SQR1
+#define __HAL_ADC_SMPR1                                  ADC_SMPR1
+#define __HAL_ADC_SMPR2                                  ADC_SMPR2
+#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
+#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
+#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
+#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
+#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
+#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
+#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
+#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
+#define __HAL_ADC_JSQR                                   ADC_JSQR
+
+#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
+#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
+#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
+#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
+#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
+#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
+#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
+#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
+#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
+#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
+
+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
+
+
+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
+#if defined(STM32H7)
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
+#else
+#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
+#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
+#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
+#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
+#endif /* STM32H7 */
+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32F3)
+#define COMP_START                                       __HAL_COMP_ENABLE
+#define COMP_STOP                                        __HAL_COMP_DISABLE
+#define COMP_LOCK                                        __HAL_COMP_LOCK
+
+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F302xE) || defined(STM32F302xC)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
+# endif
+# if defined(STM32F373xC) ||defined(STM32F378xx)
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+# endif
+#else
+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
+#endif
+
+#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
+
+#if defined(STM32L0) || defined(STM32L4)
+/* Note: On these STM32 families, the only argument of this macro             */
+/*       is COMP_FLAG_LOCK.                                                   */
+/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
+/*       argument.                                                            */
+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
+#endif
+/**
+  * @}
+  */
+
+#if defined(STM32L0) || defined(STM32L4)
+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
+/**
+  * @}
+  */
+#endif
+
+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
+                           ((WAVE) == DAC_WAVE_NOISE)|| \
+                           ((WAVE) == DAC_WAVE_TRIANGLE))
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_WRPAREA          IS_OB_WRPAREA
+#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
+#define IS_TYPEERASE        IS_FLASH_TYPEERASE
+#define IS_NBSECTORS        IS_FLASH_NBSECTORS
+#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
+#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
+#else
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
+#endif /* STM32F1 */
+#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
+#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
+#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
+#define __HAL_I2C_SPEED                 I2C_SPEED
+#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
+#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
+#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
+#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
+#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
+#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
+#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
+#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
+#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
+
+#if defined(STM32H7)
+#define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
+#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
+
+#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
+#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
+#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
+#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
+
+#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
+#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
+#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
+#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
+#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
+#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
+#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
+#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
+#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
+#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
+#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
+#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
+#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
+#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
+#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
+#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
+#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
+#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
+#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
+#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
+#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
+#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
+#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
+
+#if defined (STM32F4)
+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
+#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
+#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
+#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
+#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
+#endif /* STM32F4 */
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
+  * @{
+  */
+
+#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
+#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
+
+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
+                                         )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
+
+#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
+#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
+#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
+#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
+#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
+#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
+#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
+#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
+#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
+#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
+#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
+#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
+#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
+#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
+#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
+#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
+#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
+#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
+#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
+#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
+#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
+#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
+#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
+#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
+#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
+#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
+#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
+#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
+#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
+#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
+#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
+#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
+#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
+#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
+#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
+#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
+#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
+#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
+#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
+#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
+#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
+#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
+#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
+#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
+#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
+#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
+#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
+
+#if defined(STM32H7)
+#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE
+#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
+
+#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/
+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
+
+
+#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
+#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
+#endif
+
+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
+
+#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
+#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
+#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
+#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
+#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
+#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
+#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
+#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
+#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
+#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
+#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
+#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
+
+#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
+#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
+#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
+#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
+#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
+#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
+#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
+#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
+#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
+#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
+#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
+#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
+#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
+#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
+#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
+#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
+#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
+#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
+#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
+#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
+#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
+#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
+#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
+#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
+#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
+#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
+#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
+#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
+#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
+#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
+#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
+#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
+#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
+#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
+#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
+#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
+#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
+#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
+#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
+#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
+#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
+#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
+#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
+#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
+#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
+#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
+#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
+#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
+#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
+#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
+#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
+#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
+#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
+#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
+#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
+#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
+#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
+#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
+#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
+#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
+#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
+#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
+#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
+#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
+#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
+#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
+#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
+#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
+#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
+#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
+#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
+#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
+#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
+#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
+#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
+#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
+#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
+#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
+#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
+#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
+#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
+#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
+#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
+#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
+#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
+#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
+#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
+#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
+#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
+#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
+#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
+
+/* alias define maintained for legacy */
+#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
+#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
+
+#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
+#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
+#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
+#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
+#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
+#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
+#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
+#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
+#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
+#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
+#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
+#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
+#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
+#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
+#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
+#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
+#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
+#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
+#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
+#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
+
+#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
+#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
+#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
+#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
+#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
+#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
+#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
+#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
+#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
+#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
+#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
+#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
+#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
+#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
+#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
+#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
+#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
+#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
+#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
+#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
+
+#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
+#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
+#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
+#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
+#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
+#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
+#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
+#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
+#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
+#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
+#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
+#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
+#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
+#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
+#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
+#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
+#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
+#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
+#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
+#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
+#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
+#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
+#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
+#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
+#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
+#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
+#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
+#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
+#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
+#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
+#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
+#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
+#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
+#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
+#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
+#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
+#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
+#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
+#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
+#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
+#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
+#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
+#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
+#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
+#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
+#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
+#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
+#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
+#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
+#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
+#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
+#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
+#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
+#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
+#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
+#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
+#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
+#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
+#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
+#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
+#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
+#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
+#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
+#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
+#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
+#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
+#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
+#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
+#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
+#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
+#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
+#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
+#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
+#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
+#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
+#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
+#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
+#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
+#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
+#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
+#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
+#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
+#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
+#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
+#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
+#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
+#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
+#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
+#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
+#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
+#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
+#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
+#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
+#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
+#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
+#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
+#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
+#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
+#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
+#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
+#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
+#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
+#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
+#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
+#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
+#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
+#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
+#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
+#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
+#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
+#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
+#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
+#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
+#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
+
+#if defined(STM32L1)
+#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE
+#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE
+#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET
+#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET
+#endif /* STM32L1 */
+
+#if defined(STM32F4)
+#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
+#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
+#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
+#define Sdmmc1ClockSelection               SdioClockSelection
+#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
+#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
+#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
+#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
+#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
+#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
+#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
+#define SdioClockSelection                 Sdmmc1ClockSelection
+#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
+#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
+#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
+#endif
+
+#if defined(STM32F7)
+#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
+#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
+#endif
+
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
+#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
+#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
+
+#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
+
+#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
+#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
+#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
+#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
+#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
+
+#define RCC_IT_HSI14                RCC_IT_HSI14RDY
+
+#define RCC_IT_CSSLSE               RCC_IT_LSECSS
+#define RCC_IT_CSSHSE               RCC_IT_CSS
+
+#define RCC_PLLMUL_3                RCC_PLL_MUL3
+#define RCC_PLLMUL_4                RCC_PLL_MUL4
+#define RCC_PLLMUL_6                RCC_PLL_MUL6
+#define RCC_PLLMUL_8                RCC_PLL_MUL8
+#define RCC_PLLMUL_12               RCC_PLL_MUL12
+#define RCC_PLLMUL_16               RCC_PLL_MUL16
+#define RCC_PLLMUL_24               RCC_PLL_MUL24
+#define RCC_PLLMUL_32               RCC_PLL_MUL32
+#define RCC_PLLMUL_48               RCC_PLL_MUL48
+
+#define RCC_PLLDIV_2                RCC_PLL_DIV2
+#define RCC_PLLDIV_3                RCC_PLL_DIV3
+#define RCC_PLLDIV_4                RCC_PLL_DIV4
+
+#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
+#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
+#define RCC_MCO_NODIV               RCC_MCODIV_1
+#define RCC_MCO_DIV1                RCC_MCODIV_1
+#define RCC_MCO_DIV2                RCC_MCODIV_2
+#define RCC_MCO_DIV4                RCC_MCODIV_4
+#define RCC_MCO_DIV8                RCC_MCODIV_8
+#define RCC_MCO_DIV16               RCC_MCODIV_16
+#define RCC_MCO_DIV32               RCC_MCODIV_32
+#define RCC_MCO_DIV64               RCC_MCODIV_64
+#define RCC_MCO_DIV128              RCC_MCODIV_128
+#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
+#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
+#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
+#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
+#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
+#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
+#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
+#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
+#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
+#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
+
+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0)
+#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
+#else
+#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
+#endif
+
+#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
+#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
+#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
+#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
+#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
+#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
+#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
+
+#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
+#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
+#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
+#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
+#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
+#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
+#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
+#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
+#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
+#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
+#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
+#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
+#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
+#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
+#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
+#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
+#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
+#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
+#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
+#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
+#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
+#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
+#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
+#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
+#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
+#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
+#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
+#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
+#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
+#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
+#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
+
+#define CR_HSION_BB            RCC_CR_HSION_BB
+#define CR_CSSON_BB            RCC_CR_CSSON_BB
+#define CR_PLLON_BB            RCC_CR_PLLON_BB
+#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
+#define CR_MSION_BB            RCC_CR_MSION_BB
+#define CSR_LSION_BB           RCC_CSR_LSION_BB
+#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
+#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
+#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
+#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
+#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
+#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
+#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
+#define CR_HSEON_BB            RCC_CR_HSEON_BB
+#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
+#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
+#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
+
+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
+
+#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
+
+#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
+#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
+
+#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
+#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
+#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
+#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
+#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
+#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
+
+#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
+#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
+#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
+#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
+#define DfsdmClockSelection         Dfsdm1ClockSelection
+#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
+#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
+#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
+#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
+#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
+#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
+#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
+#if defined(STM32U5)
+#define MSIKPLLModeSEL                        RCC_MSIKPLL_MODE_SEL
+#define MSISPLLModeSEL                        RCC_MSISPLL_MODE_SEL
+#define __HAL_RCC_AHB21_CLK_DISABLE           __HAL_RCC_AHB2_1_CLK_DISABLE
+#define __HAL_RCC_AHB22_CLK_DISABLE           __HAL_RCC_AHB2_2_CLK_DISABLE
+#define __HAL_RCC_AHB1_CLK_Disable_Clear      __HAL_RCC_AHB1_CLK_ENABLE
+#define __HAL_RCC_AHB21_CLK_Disable_Clear     __HAL_RCC_AHB2_1_CLK_ENABLE
+#define __HAL_RCC_AHB22_CLK_Disable_Clear     __HAL_RCC_AHB2_2_CLK_ENABLE
+#define __HAL_RCC_AHB3_CLK_Disable_Clear      __HAL_RCC_AHB3_CLK_ENABLE
+#define __HAL_RCC_APB1_CLK_Disable_Clear      __HAL_RCC_APB1_CLK_ENABLE
+#define __HAL_RCC_APB2_CLK_Disable_Clear      __HAL_RCC_APB2_CLK_ENABLE
+#define __HAL_RCC_APB3_CLK_Disable_Clear      __HAL_RCC_APB3_CLK_ENABLE
+#define IS_RCC_MSIPLLModeSelection            IS_RCC_MSIPLLMODE_SELECT
+#define RCC_PERIPHCLK_CLK48                   RCC_PERIPHCLK_ICLK
+#define RCC_CLK48CLKSOURCE_HSI48              RCC_ICLK_CLKSOURCE_HSI48
+#define RCC_CLK48CLKSOURCE_PLL2               RCC_ICLK_CLKSOURCE_PLL2
+#define RCC_CLK48CLKSOURCE_PLL1               RCC_ICLK_CLKSOURCE_PLL1
+#define RCC_CLK48CLKSOURCE_MSIK               RCC_ICLK_CLKSOURCE_MSIK
+#define __HAL_RCC_ADC1_CLK_ENABLE             __HAL_RCC_ADC12_CLK_ENABLE
+#define __HAL_RCC_ADC1_CLK_DISABLE            __HAL_RCC_ADC12_CLK_DISABLE
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED         __HAL_RCC_ADC12_IS_CLK_ENABLED
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED        __HAL_RCC_ADC12_IS_CLK_DISABLED
+#define __HAL_RCC_ADC1_FORCE_RESET            __HAL_RCC_ADC12_FORCE_RESET
+#define __HAL_RCC_ADC1_RELEASE_RESET          __HAL_RCC_ADC12_RELEASE_RESET
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE       __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE      __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
+#define __HAL_RCC_GET_CLK48_SOURCE            __HAL_RCC_GET_ICLK_SOURCE
+#define __HAL_RCC_PLLFRACN_ENABLE             __HAL_RCC_PLL_FRACN_ENABLE
+#define __HAL_RCC_PLLFRACN_DISABLE            __HAL_RCC_PLL_FRACN_DISABLE
+#define __HAL_RCC_PLLFRACN_CONFIG             __HAL_RCC_PLL_FRACN_CONFIG
+#define IS_RCC_PLLFRACN_VALUE                 IS_RCC_PLL_FRACN_VALUE
+#endif /* STM32U5 */
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \
+    defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
+    defined (STM32C0)
+#else
+#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
+#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
+#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
+
+#if defined (STM32F1)
+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
+
+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
+
+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
+
+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
+
+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
+#else
+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
+                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
+                                                       (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
+                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
+#endif   /* STM32F1 */
+
+#define IS_ALARM                                  IS_RTC_ALARM
+#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
+#define IS_TAMPER                                 IS_RTC_TAMPER
+#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
+#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
+#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
+#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
+#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
+#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
+#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
+#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
+#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
+
+#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
+#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
+#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
+
+#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
+#define eMMC_HIGH_VOLTAGE_RANGE     EMMC_HIGH_VOLTAGE_RANGE
+#define eMMC_DUAL_VOLTAGE_RANGE     EMMC_DUAL_VOLTAGE_RANGE
+#define eMMC_LOW_VOLTAGE_RANGE      EMMC_LOW_VOLTAGE_RANGE
+
+#define SDMMC_NSpeed_CLK_DIV        SDMMC_NSPEED_CLK_DIV
+#define SDMMC_HSpeed_CLK_DIV        SDMMC_HSPEED_CLK_DIV
+#endif
+
+#if defined(STM32F4) || defined(STM32F2)
+#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
+#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
+#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
+#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
+#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
+#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
+#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
+#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
+#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
+#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
+#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
+#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
+#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
+#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
+#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
+#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
+#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
+#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
+#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
+/* alias CMSIS */
+#define  SDMMC1_IRQn                SDIO_IRQn
+#define  SDMMC1_IRQHandler          SDIO_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32L4)
+#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
+#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
+#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
+#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
+#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
+#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
+#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
+#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
+#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
+#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
+#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
+#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
+#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
+#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
+#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
+#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
+#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
+#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS
+#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT
+#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND
+/* alias CMSIS for compatibilities */
+#define  SDIO_IRQn                  SDMMC1_IRQn
+#define  SDIO_IRQHandler            SDMMC1_IRQHandler
+#endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
+#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
+#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
+#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
+#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
+#endif
+
+#if defined(STM32H7) || defined(STM32L5)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
+#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
+#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
+#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
+#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
+
+#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
+#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
+
+#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
+#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
+#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
+#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
+#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
+#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
+#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
+#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
+#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
+#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
+#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
+#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
+#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
+
+#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
+
+#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
+
+/**
+  * @}
+  */
+
+
+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
+#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
+#define __USART_ENABLE                  __HAL_USART_ENABLE
+#define __USART_DISABLE                 __HAL_USART_DISABLE
+
+#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
+#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
+
+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
+#define USART_OVERSAMPLING_16               0x00000000U
+#define USART_OVERSAMPLING_8                USART_CR1_OVER8
+
+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
+                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))
+#endif /* STM32F0 || STM32F3 || STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
+
+#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
+#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+
+#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
+#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
+#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
+
+#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
+#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
+
+#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
+#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
+/**
+  * @}
+  */
+
+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
+
+#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
+#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
+
+#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
+
+#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
+#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
+#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
+#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
+#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
+#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
+#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
+#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
+#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
+#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
+#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
+#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
+
+#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
+/**
+  * @}
+  */
+
+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
+#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
+#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
+#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
+
+#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
+#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
+#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
+#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
+#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
+#define SAI_STREOMODE                     SAI_STEREOMODE
+#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
+#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
+#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
+#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
+#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
+#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
+#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
+#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
+#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
+#endif /* STM32L4 || STM32F4 || STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
+  * @{
+  */
+#if defined (STM32F7)
+#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
+#endif /* STM32F7 */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_LEGACY */
+
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h
index f7eb847..5d8cdd3 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h
@@ -1,297 +1,297 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal.h
-  * @author  MCD Application Team
-  * @brief   This file contains all the functions prototypes for the HAL 
-  *          module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_H
-#define __STM32F4xx_HAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_conf.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup HAL
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Constants HAL Exported Constants
-  * @{
-  */
-
-/** @defgroup HAL_TICK_FREQ Tick Frequency
-  * @{
-  */
-typedef enum
-{
-  HAL_TICK_FREQ_10HZ         = 100U,
-  HAL_TICK_FREQ_100HZ        = 10U,
-  HAL_TICK_FREQ_1KHZ         = 1U,
-  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
-} HAL_TickFreqTypeDef;
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-   
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup HAL_Exported_Macros HAL Exported Macros
-  * @{
-  */
-
-/** @brief  Freeze/Unfreeze Peripherals in Debug mode 
-  */
-#define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
-#define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
-#define __HAL_DBGMCU_FREEZE_WWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
-#define __HAL_DBGMCU_FREEZE_IWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
-#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_FREEZE_CAN1()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
-#define __HAL_DBGMCU_FREEZE_CAN2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM9()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM10()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
-#define __HAL_DBGMCU_FREEZE_TIM11()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
-
-#define __HAL_DBGMCU_UNFREEZE_TIM2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM3()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM4()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM5()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM6()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM7()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM12()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM13()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM14()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
-#define __HAL_DBGMCU_UNFREEZE_RTC()            (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
-#define __HAL_DBGMCU_UNFREEZE_WWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
-#define __HAL_DBGMCU_UNFREEZE_IWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
-#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
-#define __HAL_DBGMCU_UNFREEZE_CAN1()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
-#define __HAL_DBGMCU_UNFREEZE_CAN2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM1()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM8()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM9()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM10()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
-#define __HAL_DBGMCU_UNFREEZE_TIM11()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
-
-/** @brief  Main Flash memory mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_FLASH()             (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
-
-/** @brief  System Flash memory mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
-                                                         SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
-                                                        }while(0);
-
-/** @brief  Embedded SRAM mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_SRAM()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
-                                                  SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
-                                                 }while(0);
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
-/** @brief  FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_FSMC()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
-                                                  SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
-                                                 }while(0);
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-/** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_FMC()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
-                                                 SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
-                                                }while(0);
-
-/** @brief  FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
-  */
-#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
-                                                       SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
-                                                      }while(0);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
-/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
-  * @{
-  */
-/** @brief  SYSCFG Break Lockup lock
-  *         Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input
-  * @note   The selected configuration is locked and can be unlocked by system reset
-  */
-#define __HAL_SYSCFG_BREAK_PVD_LOCK()      do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
-                                               SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK;    \
-                                              }while(0)
-/**
- * @}
- */
-
-/** @defgroup PVD_Lock_Enable PVD Lock
-  * @{
-  */
-/** @brief  SYSCFG Break PVD lock
-  *         Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
-  * @note   The selected configuration is locked and can be unlocked by system reset
-  */
-#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
-                                                 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK;    \
-                                                }while(0)
-/**
- * @}
- */
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Private_Macros HAL Private Macros
-  * @{
-  */
-#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
-                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
-                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
-/**
-  * @}
-  */
-
-/* Exported variables --------------------------------------------------------*/
-
-/** @addtogroup HAL_Exported_Variables
-  * @{
-  */
-extern __IO uint32_t uwTick;
-extern uint32_t uwTickPrio;
-extern HAL_TickFreqTypeDef uwTickFreq;
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup HAL_Exported_Functions
-  * @{
-  */
-/** @addtogroup HAL_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and Configuration functions  ******************************/
-HAL_StatusTypeDef HAL_Init(void);
-HAL_StatusTypeDef HAL_DeInit(void);
-void HAL_MspInit(void);
-void HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
-/**
-  * @}
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions  ************************************************/
-void HAL_IncTick(void);
-void HAL_Delay(uint32_t Delay);
-uint32_t HAL_GetTick(void);
-uint32_t HAL_GetTickPrio(void);
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
-HAL_TickFreqTypeDef HAL_GetTickFreq(void);
-void HAL_SuspendTick(void);
-void HAL_ResumeTick(void);
-uint32_t HAL_GetHalVersion(void);
-uint32_t HAL_GetREVID(void);
-uint32_t HAL_GetDEVID(void);
-void HAL_DBGMCU_EnableDBGSleepMode(void);
-void HAL_DBGMCU_DisableDBGSleepMode(void);
-void HAL_DBGMCU_EnableDBGStopMode(void);
-void HAL_DBGMCU_DisableDBGStopMode(void);
-void HAL_DBGMCU_EnableDBGStandbyMode(void);
-void HAL_DBGMCU_DisableDBGStandbyMode(void);
-void HAL_EnableCompensationCell(void);
-void HAL_DisableCompensationCell(void);
-uint32_t HAL_GetUIDw0(void);
-uint32_t HAL_GetUIDw1(void);
-uint32_t HAL_GetUIDw2(void);
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-void HAL_EnableMemorySwappingBank(void);
-void HAL_DisableMemorySwappingBank(void);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Variables HAL Private Variables
-  * @{
-  */
-/**
-  * @}
-  */
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup HAL_Private_Constants HAL Private Constants
-  * @{
-  */
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_H */
-
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal.h
+  * @author  MCD Application Team
+  * @brief   This file contains all the functions prototypes for the HAL 
+  *          module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_H
+#define __STM32F4xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_conf.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HAL
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+  * @{
+  */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+  * @{
+  */
+typedef enum
+{
+  HAL_TICK_FREQ_10HZ         = 100U,
+  HAL_TICK_FREQ_100HZ        = 10U,
+  HAL_TICK_FREQ_1KHZ         = 1U,
+  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+   
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HAL_Exported_Macros HAL Exported Macros
+  * @{
+  */
+
+/** @brief  Freeze/Unfreeze Peripherals in Debug mode 
+  */
+#define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_DBGMCU_FREEZE_WWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_DBGMCU_FREEZE_IWDG()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_FREEZE_CAN1()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_DBGMCU_FREEZE_CAN2()           (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM9()           (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM10()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_DBGMCU_FREEZE_TIM11()          (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+
+#define __HAL_DBGMCU_UNFREEZE_TIM2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM3()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM4()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM5()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM6()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM7()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM12()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM13()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM14()          (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
+#define __HAL_DBGMCU_UNFREEZE_RTC()            (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
+#define __HAL_DBGMCU_UNFREEZE_WWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_IWDG()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT()   (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
+#define __HAL_DBGMCU_UNFREEZE_CAN1()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
+#define __HAL_DBGMCU_UNFREEZE_CAN2()           (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM1()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM8()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM9()           (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM10()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
+#define __HAL_DBGMCU_UNFREEZE_TIM11()          (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
+
+/** @brief  Main Flash memory mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH()             (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
+
+/** @brief  System Flash memory mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+                                                         SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
+                                                        }while(0);
+
+/** @brief  Embedded SRAM mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+                                                  SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
+                                                 }while(0);
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+/** @brief  FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FSMC()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+                                                  SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
+                                                 }while(0);
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FMC()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+                                                 SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
+                                                }while(0);
+
+/** @brief  FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM()       do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
+                                                       SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
+                                                      }while(0);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
+  * @{
+  */
+/** @brief  SYSCFG Break Lockup lock
+  *         Enables and locks the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8 input
+  * @note   The selected configuration is locked and can be unlocked by system reset
+  */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK()      do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
+                                               SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK;    \
+                                              }while(0)
+/**
+ * @}
+ */
+
+/** @defgroup PVD_Lock_Enable PVD Lock
+  * @{
+  */
+/** @brief  SYSCFG Break PVD lock
+  *         Enables and locks the PVD connection with Timer1/8 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
+  * @note   The selected configuration is locked and can be unlocked by system reset
+  */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
+                                                 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK;    \
+                                                }while(0)
+/**
+ * @}
+ */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx || STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Private_Macros HAL Private Macros
+  * @{
+  */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \
+                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+                           ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+  * @}
+  */
+
+/* Exported variables --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Variables
+  * @{
+  */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HAL_Exported_Functions
+  * @{
+  */
+/** @addtogroup HAL_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and Configuration functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+void HAL_EnableCompensationCell(void);
+void HAL_DisableCompensationCell(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+void HAL_EnableMemorySwappingBank(void);
+void HAL_DisableMemorySwappingBank(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Variables HAL Private Variables
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HAL_Private_Constants HAL Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_H */
+
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h
index aa4a40d..728b61c 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_can.h
@@ -1,844 +1,844 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_can.h
-  * @author  MCD Application Team
-  * @brief   Header file of CAN HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32F4xx_HAL_CAN_H
-#define STM32F4xx_HAL_CAN_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-#if defined (CAN1)
-/** @addtogroup CAN
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CAN_Exported_Types CAN Exported Types
-  * @{
-  */
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_CAN_STATE_RESET             = 0x00U,  /*!< CAN not yet initialized or disabled */
-  HAL_CAN_STATE_READY             = 0x01U,  /*!< CAN initialized and ready for use   */
-  HAL_CAN_STATE_LISTENING         = 0x02U,  /*!< CAN receive process is ongoing      */
-  HAL_CAN_STATE_SLEEP_PENDING     = 0x03U,  /*!< CAN sleep request is pending        */
-  HAL_CAN_STATE_SLEEP_ACTIVE      = 0x04U,  /*!< CAN sleep mode is active            */
-  HAL_CAN_STATE_ERROR             = 0x05U   /*!< CAN error state                     */
-
-} HAL_CAN_StateTypeDef;
-
-/**
-  * @brief  CAN init structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;                  /*!< Specifies the length of a time quantum.
-                                            This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
-
-  uint32_t Mode;                       /*!< Specifies the CAN operating mode.
-                                            This parameter can be a value of @ref CAN_operating_mode */
-
-  uint32_t SyncJumpWidth;              /*!< Specifies the maximum number of time quanta the CAN hardware
-                                            is allowed to lengthen or shorten a bit to perform resynchronization.
-                                            This parameter can be a value of @ref CAN_synchronisation_jump_width */
-
-  uint32_t TimeSeg1;                   /*!< Specifies the number of time quanta in Bit Segment 1.
-                                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
-
-  uint32_t TimeSeg2;                   /*!< Specifies the number of time quanta in Bit Segment 2.
-                                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
-  FunctionalState TimeTriggeredMode;   /*!< Enable or disable the time triggered communication mode.
-                                            This parameter can be set to ENABLE or DISABLE. */
-
-  FunctionalState AutoBusOff;          /*!< Enable or disable the automatic bus-off management.
-                                            This parameter can be set to ENABLE or DISABLE. */
-
-  FunctionalState AutoWakeUp;          /*!< Enable or disable the automatic wake-up mode.
-                                            This parameter can be set to ENABLE or DISABLE. */
-
-  FunctionalState AutoRetransmission;  /*!< Enable or disable the non-automatic retransmission mode.
-                                            This parameter can be set to ENABLE or DISABLE. */
-
-  FunctionalState ReceiveFifoLocked;   /*!< Enable or disable the Receive FIFO Locked mode.
-                                            This parameter can be set to ENABLE or DISABLE. */
-
-  FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.
-                                            This parameter can be set to ENABLE or DISABLE. */
-
-} CAN_InitTypeDef;
-
-/**
-  * @brief  CAN filter configuration structure definition
-  */
-typedef struct
-{
-  uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
-                                       configuration, first one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
-  uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
-                                       configuration, second one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
-  uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
-                                       according to the mode (MSBs for a 32-bit configuration,
-                                       first one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
-  uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
-                                       according to the mode (LSBs for a 32-bit configuration,
-                                       second one for a 16-bit configuration).
-                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
-
-  uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
-                                       This parameter can be a value of @ref CAN_filter_FIFO */
-
-  uint32_t FilterBank;            /*!< Specifies the filter bank which will be initialized.
-                                       For single CAN instance(14 dedicated filter banks),
-                                       this parameter must be a number between Min_Data = 0 and Max_Data = 13.
-                                       For dual CAN instances(28 filter banks shared),
-                                       this parameter must be a number between Min_Data = 0 and Max_Data = 27. */
-
-  uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
-                                       This parameter can be a value of @ref CAN_filter_mode */
-
-  uint32_t FilterScale;           /*!< Specifies the filter scale.
-                                       This parameter can be a value of @ref CAN_filter_scale */
-
-  uint32_t FilterActivation;      /*!< Enable or disable the filter.
-                                       This parameter can be a value of @ref CAN_filter_activation */
-
-  uint32_t SlaveStartFilterBank;  /*!< Select the start filter bank for the slave CAN instance.
-                                       For single CAN instances, this parameter is meaningless.
-                                       For dual CAN instances, all filter banks with lower index are assigned to master
-                                       CAN instance, whereas all filter banks with greater index are assigned to slave
-                                       CAN instance.
-                                       This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
-
-} CAN_FilterTypeDef;
-
-/**
-  * @brief  CAN Tx message header structure definition
-  */
-typedef struct
-{
-  uint32_t StdId;    /*!< Specifies the standard identifier.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
-
-  uint32_t ExtId;    /*!< Specifies the extended identifier.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
-
-  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
-                          This parameter can be a value of @ref CAN_identifier_type */
-
-  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
-                          This parameter can be a value of @ref CAN_remote_transmission_request */
-
-  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
-
-  FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start
-                          of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7].
-                          @note: Time Triggered Communication Mode must be enabled.
-                          @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent.
-                          This parameter can be set to ENABLE or DISABLE. */
-
-} CAN_TxHeaderTypeDef;
-
-/**
-  * @brief  CAN Rx message header structure definition
-  */
-typedef struct
-{
-  uint32_t StdId;    /*!< Specifies the standard identifier.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
-
-  uint32_t ExtId;    /*!< Specifies the extended identifier.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
-
-  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
-                          This parameter can be a value of @ref CAN_identifier_type */
-
-  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
-                          This parameter can be a value of @ref CAN_remote_transmission_request */
-
-  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
-
-  uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.
-                          @note: Time Triggered Communication Mode must be enabled.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */
-
-  uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.
-                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
-
-} CAN_RxHeaderTypeDef;
-
-/**
-  * @brief  CAN handle Structure definition
-  */
-typedef struct __CAN_HandleTypeDef
-{
-  CAN_TypeDef                 *Instance;                 /*!< Register base address */
-
-  CAN_InitTypeDef             Init;                      /*!< CAN required parameters */
-
-  __IO HAL_CAN_StateTypeDef   State;                     /*!< CAN communication state */
-
-  __IO uint32_t               ErrorCode;                 /*!< CAN Error code.
-                                                              This parameter can be a value of @ref CAN_Error_Code */
-
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-  void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback    */
-  void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback    */
-  void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback    */
-  void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan);   /*!< CAN Tx Mailbox 0 abort callback       */
-  void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan);   /*!< CAN Tx Mailbox 1 abort callback       */
-  void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan);   /*!< CAN Tx Mailbox 2 abort callback       */
-  void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback    */
-  void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan);       /*!< CAN Rx FIFO 0 full callback           */
-  void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback    */
-  void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan);       /*!< CAN Rx FIFO 1 full callback           */
-  void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan);             /*!< CAN Sleep callback                    */
-  void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan);   /*!< CAN Wake Up from Rx msg callback      */
-  void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan);             /*!< CAN Error callback                    */
-
-  void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan);           /*!< CAN Msp Init callback                 */
-  void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan);         /*!< CAN Msp DeInit callback               */
-
-#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
-} CAN_HandleTypeDef;
-
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-/**
-  * @brief  HAL CAN common Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID       = 0x00U,    /*!< CAN Tx Mailbox 0 complete callback ID         */
-  HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID       = 0x01U,    /*!< CAN Tx Mailbox 1 complete callback ID         */
-  HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID       = 0x02U,    /*!< CAN Tx Mailbox 2 complete callback ID         */
-  HAL_CAN_TX_MAILBOX0_ABORT_CB_ID          = 0x03U,    /*!< CAN Tx Mailbox 0 abort callback ID            */
-  HAL_CAN_TX_MAILBOX1_ABORT_CB_ID          = 0x04U,    /*!< CAN Tx Mailbox 1 abort callback ID            */
-  HAL_CAN_TX_MAILBOX2_ABORT_CB_ID          = 0x05U,    /*!< CAN Tx Mailbox 2 abort callback ID            */
-  HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID       = 0x06U,    /*!< CAN Rx FIFO 0 message pending callback ID     */
-  HAL_CAN_RX_FIFO0_FULL_CB_ID              = 0x07U,    /*!< CAN Rx FIFO 0 full callback ID                */
-  HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID       = 0x08U,    /*!< CAN Rx FIFO 1 message pending callback ID     */
-  HAL_CAN_RX_FIFO1_FULL_CB_ID              = 0x09U,    /*!< CAN Rx FIFO 1 full callback ID                */
-  HAL_CAN_SLEEP_CB_ID                      = 0x0AU,    /*!< CAN Sleep callback ID                         */
-  HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID         = 0x0BU,    /*!< CAN Wake Up from Rx msg callback ID          */
-  HAL_CAN_ERROR_CB_ID                      = 0x0CU,    /*!< CAN Error callback ID                         */
-
-  HAL_CAN_MSPINIT_CB_ID                    = 0x0DU,    /*!< CAN MspInit callback ID                       */
-  HAL_CAN_MSPDEINIT_CB_ID                  = 0x0EU,    /*!< CAN MspDeInit callback ID                     */
-
-} HAL_CAN_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL CAN Callback pointer definition
-  */
-typedef  void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function   */
-
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CAN_Exported_Constants CAN Exported Constants
-  * @{
-  */
-
-/** @defgroup CAN_Error_Code CAN Error Code
-  * @{
-  */
-#define HAL_CAN_ERROR_NONE            (0x00000000U)  /*!< No error                                             */
-#define HAL_CAN_ERROR_EWG             (0x00000001U)  /*!< Protocol Error Warning                               */
-#define HAL_CAN_ERROR_EPV             (0x00000002U)  /*!< Error Passive                                        */
-#define HAL_CAN_ERROR_BOF             (0x00000004U)  /*!< Bus-off error                                        */
-#define HAL_CAN_ERROR_STF             (0x00000008U)  /*!< Stuff error                                          */
-#define HAL_CAN_ERROR_FOR             (0x00000010U)  /*!< Form error                                           */
-#define HAL_CAN_ERROR_ACK             (0x00000020U)  /*!< Acknowledgment error                                 */
-#define HAL_CAN_ERROR_BR              (0x00000040U)  /*!< Bit recessive error                                  */
-#define HAL_CAN_ERROR_BD              (0x00000080U)  /*!< Bit dominant error                                   */
-#define HAL_CAN_ERROR_CRC             (0x00000100U)  /*!< CRC error                                            */
-#define HAL_CAN_ERROR_RX_FOV0         (0x00000200U)  /*!< Rx FIFO0 overrun error                               */
-#define HAL_CAN_ERROR_RX_FOV1         (0x00000400U)  /*!< Rx FIFO1 overrun error                               */
-#define HAL_CAN_ERROR_TX_ALST0        (0x00000800U)  /*!< TxMailbox 0 transmit failure due to arbitration lost */
-#define HAL_CAN_ERROR_TX_TERR0        (0x00001000U)  /*!< TxMailbox 0 transmit failure due to transmit error    */
-#define HAL_CAN_ERROR_TX_ALST1        (0x00002000U)  /*!< TxMailbox 1 transmit failure due to arbitration lost */
-#define HAL_CAN_ERROR_TX_TERR1        (0x00004000U)  /*!< TxMailbox 1 transmit failure due to transmit error    */
-#define HAL_CAN_ERROR_TX_ALST2        (0x00008000U)  /*!< TxMailbox 2 transmit failure due to arbitration lost */
-#define HAL_CAN_ERROR_TX_TERR2        (0x00010000U)  /*!< TxMailbox 2 transmit failure due to transmit error    */
-#define HAL_CAN_ERROR_TIMEOUT         (0x00020000U)  /*!< Timeout error                                        */
-#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U)  /*!< Peripheral not initialized                           */
-#define HAL_CAN_ERROR_NOT_READY       (0x00080000U)  /*!< Peripheral not ready                                 */
-#define HAL_CAN_ERROR_NOT_STARTED     (0x00100000U)  /*!< Peripheral not started                               */
-#define HAL_CAN_ERROR_PARAM           (0x00200000U)  /*!< Parameter error                                      */
-
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error                               */
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-#define HAL_CAN_ERROR_INTERNAL        (0x00800000U)  /*!< Internal error                                       */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_InitStatus CAN InitStatus
-  * @{
-  */
-#define CAN_INITSTATUS_FAILED       (0x00000000U)  /*!< CAN initialization failed */
-#define CAN_INITSTATUS_SUCCESS      (0x00000001U)  /*!< CAN initialization OK     */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_operating_mode CAN Operating Mode
-  * @{
-  */
-#define CAN_MODE_NORMAL             (0x00000000U)                              /*!< Normal mode   */
-#define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
-#define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
-#define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
-/**
-  * @}
-  */
-
-
-/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
-  * @{
-  */
-#define CAN_SJW_1TQ                 (0x00000000U)              /*!< 1 time quantum */
-#define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
-#define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
-#define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
-  * @{
-  */
-#define CAN_BS1_1TQ                 (0x00000000U)                                                /*!< 1 time quantum  */
-#define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
-#define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
-#define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
-#define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */
-#define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */
-#define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */
-#define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */
-#define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */
-#define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */
-#define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */
-#define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */
-#define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */
-#define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
-#define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
-#define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
-  * @{
-  */
-#define CAN_BS2_1TQ                 (0x00000000U)                                /*!< 1 time quantum */
-#define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
-#define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
-#define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
-#define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */
-#define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
-#define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
-#define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_mode CAN Filter Mode
-  * @{
-  */
-#define CAN_FILTERMODE_IDMASK       (0x00000000U)  /*!< Identifier mask mode */
-#define CAN_FILTERMODE_IDLIST       (0x00000001U)  /*!< Identifier list mode */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_scale CAN Filter Scale
-  * @{
-  */
-#define CAN_FILTERSCALE_16BIT       (0x00000000U)  /*!< Two 16-bit filters */
-#define CAN_FILTERSCALE_32BIT       (0x00000001U)  /*!< One 32-bit filter  */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_activation CAN Filter Activation
-  * @{
-  */
-#define CAN_FILTER_DISABLE          (0x00000000U)  /*!< Disable filter */
-#define CAN_FILTER_ENABLE           (0x00000001U)  /*!< Enable filter  */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_filter_FIFO CAN Filter FIFO
-  * @{
-  */
-#define CAN_FILTER_FIFO0            (0x00000000U)  /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_FILTER_FIFO1            (0x00000001U)  /*!< Filter FIFO 1 assignment for filter x */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_identifier_type CAN Identifier Type
-  * @{
-  */
-#define CAN_ID_STD                  (0x00000000U)  /*!< Standard Id */
-#define CAN_ID_EXT                  (0x00000004U)  /*!< Extended Id */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
-  * @{
-  */
-#define CAN_RTR_DATA                (0x00000000U)  /*!< Data frame   */
-#define CAN_RTR_REMOTE              (0x00000002U)  /*!< Remote frame */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
-  * @{
-  */
-#define CAN_RX_FIFO0                (0x00000000U)  /*!< CAN receive FIFO 0 */
-#define CAN_RX_FIFO1                (0x00000001U)  /*!< CAN receive FIFO 1 */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes
-  * @{
-  */
-#define CAN_TX_MAILBOX0             (0x00000001U)  /*!< Tx Mailbox 0  */
-#define CAN_TX_MAILBOX1             (0x00000002U)  /*!< Tx Mailbox 1  */
-#define CAN_TX_MAILBOX2             (0x00000004U)  /*!< Tx Mailbox 2  */
-/**
-  * @}
-  */
-
-/** @defgroup CAN_flags CAN Flags
-  * @{
-  */
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0              (0x00000500U)  /*!< Request complete MailBox 0 flag   */
-#define CAN_FLAG_TXOK0              (0x00000501U)  /*!< Transmission OK MailBox 0 flag    */
-#define CAN_FLAG_ALST0              (0x00000502U)  /*!< Arbitration Lost MailBox 0 flag   */
-#define CAN_FLAG_TERR0              (0x00000503U)  /*!< Transmission error MailBox 0 flag */
-#define CAN_FLAG_RQCP1              (0x00000508U)  /*!< Request complete MailBox1 flag    */
-#define CAN_FLAG_TXOK1              (0x00000509U)  /*!< Transmission OK MailBox 1 flag    */
-#define CAN_FLAG_ALST1              (0x0000050AU)  /*!< Arbitration Lost MailBox 1 flag   */
-#define CAN_FLAG_TERR1              (0x0000050BU)  /*!< Transmission error MailBox 1 flag */
-#define CAN_FLAG_RQCP2              (0x00000510U)  /*!< Request complete MailBox2 flag    */
-#define CAN_FLAG_TXOK2              (0x00000511U)  /*!< Transmission OK MailBox 2 flag    */
-#define CAN_FLAG_ALST2              (0x00000512U)  /*!< Arbitration Lost MailBox 2 flag   */
-#define CAN_FLAG_TERR2              (0x00000513U)  /*!< Transmission error MailBox 2 flag */
-#define CAN_FLAG_TME0               (0x0000051AU)  /*!< Transmit mailbox 0 empty flag     */
-#define CAN_FLAG_TME1               (0x0000051BU)  /*!< Transmit mailbox 1 empty flag     */
-#define CAN_FLAG_TME2               (0x0000051CU)  /*!< Transmit mailbox 2 empty flag     */
-#define CAN_FLAG_LOW0               (0x0000051DU)  /*!< Lowest priority mailbox 0 flag    */
-#define CAN_FLAG_LOW1               (0x0000051EU)  /*!< Lowest priority mailbox 1 flag    */
-#define CAN_FLAG_LOW2               (0x0000051FU)  /*!< Lowest priority mailbox 2 flag    */
-
-/* Receive Flags */
-#define CAN_FLAG_FF0                (0x00000203U)  /*!< RX FIFO 0 Full flag               */
-#define CAN_FLAG_FOV0               (0x00000204U)  /*!< RX FIFO 0 Overrun flag            */
-#define CAN_FLAG_FF1                (0x00000403U)  /*!< RX FIFO 1 Full flag               */
-#define CAN_FLAG_FOV1               (0x00000404U)  /*!< RX FIFO 1 Overrun flag            */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_INAK               (0x00000100U)  /*!< Initialization acknowledge flag   */
-#define CAN_FLAG_SLAK               (0x00000101U)  /*!< Sleep acknowledge flag            */
-#define CAN_FLAG_ERRI               (0x00000102U)  /*!< Error flag                        */
-#define CAN_FLAG_WKU                (0x00000103U)  /*!< Wake up interrupt flag            */
-#define CAN_FLAG_SLAKI              (0x00000104U)  /*!< Sleep acknowledge interrupt flag  */
-
-/* Error Flags */
-#define CAN_FLAG_EWG                (0x00000300U)  /*!< Error warning flag                */
-#define CAN_FLAG_EPV                (0x00000301U)  /*!< Error passive flag                */
-#define CAN_FLAG_BOF                (0x00000302U)  /*!< Bus-Off flag                      */
-/**
-  * @}
-  */
-
-
-/** @defgroup CAN_Interrupts CAN Interrupts
-  * @{
-  */
-/* Transmit Interrupt */
-#define CAN_IT_TX_MAILBOX_EMPTY     ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
-
-/* Receive Interrupts */
-#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
-#define CAN_IT_RX_FIFO0_FULL        ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
-#define CAN_IT_RX_FIFO0_OVERRUN     ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
-#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
-#define CAN_IT_RX_FIFO1_FULL        ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
-#define CAN_IT_RX_FIFO1_OVERRUN     ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WAKEUP               ((uint32_t)CAN_IER_WKUIE)   /*!< Wake-up interrupt                */
-#define CAN_IT_SLEEP_ACK            ((uint32_t)CAN_IER_SLKIE)   /*!< Sleep acknowledge interrupt      */
-
-/* Error Interrupts */
-#define CAN_IT_ERROR_WARNING        ((uint32_t)CAN_IER_EWGIE)   /*!< Error warning interrupt          */
-#define CAN_IT_ERROR_PASSIVE        ((uint32_t)CAN_IER_EPVIE)   /*!< Error passive interrupt          */
-#define CAN_IT_BUSOFF               ((uint32_t)CAN_IER_BOFIE)   /*!< Bus-off interrupt                */
-#define CAN_IT_LAST_ERROR_CODE      ((uint32_t)CAN_IER_LECIE)   /*!< Last error code interrupt        */
-#define CAN_IT_ERROR                ((uint32_t)CAN_IER_ERRIE)   /*!< Error Interrupt                  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup CAN_Exported_Macros CAN Exported Macros
-  * @{
-  */
-
-/** @brief  Reset CAN handle state
-  * @param  __HANDLE__ CAN handle.
-  * @retval None
-  */
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{                                              \
-                                                     (__HANDLE__)->State = HAL_CAN_STATE_RESET;   \
-                                                     (__HANDLE__)->MspInitCallback = NULL;        \
-                                                     (__HANDLE__)->MspDeInitCallback = NULL;      \
-                                                   } while(0)
-#else
-#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
-#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */
-
-/**
-  * @brief  Enable the specified CAN interrupts.
-  * @param  __HANDLE__ CAN handle.
-  * @param  __INTERRUPT__ CAN Interrupt sources to enable.
-  *           This parameter can be any combination of @arg CAN_Interrupts
-  * @retval None
-  */
-#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified CAN interrupts.
-  * @param  __HANDLE__ CAN handle.
-  * @param  __INTERRUPT__ CAN Interrupt sources to disable.
-  *           This parameter can be any combination of @arg CAN_Interrupts
-  * @retval None
-  */
-#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-
-/** @brief  Check if the specified CAN interrupt source is enabled or disabled.
-  * @param  __HANDLE__ specifies the CAN Handle.
-  * @param  __INTERRUPT__ specifies the CAN interrupt source to check.
-  *           This parameter can be a value of @arg CAN_Interrupts
-  * @retval The state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__))
-
-/** @brief  Check whether the specified CAN flag is set or not.
-  * @param  __HANDLE__ specifies the CAN Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of @arg CAN_flags
-  * @retval The state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
-  ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
-   (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
-   (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
-   (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
-   (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
-
-/** @brief  Clear the specified CAN pending flag.
-  * @param  __HANDLE__ specifies the CAN Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag
-  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag
-  *            @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag
-  *            @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag
-  *            @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag
-  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag
-  *            @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag
-  *            @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag
-  *            @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag
-  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag
-  *            @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag
-  *            @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag
-  *            @arg CAN_FLAG_FF0:   RX FIFO 0 Full Flag
-  *            @arg CAN_FLAG_FOV0:  RX FIFO 0 Overrun Flag
-  *            @arg CAN_FLAG_FF1:   RX FIFO 1 Full Flag
-  *            @arg CAN_FLAG_FOV1:  RX FIFO 1 Overrun Flag
-  *            @arg CAN_FLAG_WKUI:  Wake up Interrupt Flag
-  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag
-  * @retval None
-  */
-#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-  ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
-   (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
-   (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
-   (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
-
-/**
- * @}
- */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CAN_Exported_Functions CAN Exported Functions
-  * @{
-  */
-
-/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- * @{
- */
-
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
-void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
-void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
-
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-/* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan));
-HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);
-
-#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions
- *  @brief    Configuration functions
- * @{
- */
-
-/* Configuration functions ****************************************************/
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);
-
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group3 Control functions
- *  @brief    Control functions
- * @{
- */
-
-/* Control functions **********************************************************/
-HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
-uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);
-HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
-uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);
-uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
-uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
-HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
-uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);
-
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management
- *  @brief    Interrupts management
- * @{
- */
-/* Interrupts management ******************************************************/
-HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs);
-HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs);
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
-
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group5 Callback functions
- *  @brief    Callback functions
- * @{
- */
-/* Callbacks functions ********************************************************/
-
-void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan);
-void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
-
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
- *  @brief   CAN Peripheral State functions
- * @{
- */
-/* Peripheral State and Error functions ***************************************/
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Private types -------------------------------------------------------------*/
-/** @defgroup CAN_Private_Types CAN Private Types
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Variables CAN Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Constants CAN Private Constants
-  * @{
-  */
-#define CAN_FLAG_MASK  (0x000000FFU)
-/**
-  * @}
-  */
-
-/* Private Macros -----------------------------------------------------------*/
-/** @defgroup CAN_Private_Macros CAN Private Macros
-  * @{
-  */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
-                           ((MODE) == CAN_MODE_LOOPBACK)|| \
-                           ((MODE) == CAN_MODE_SILENT) || \
-                           ((MODE) == CAN_MODE_SILENT_LOOPBACK))
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \
-                         ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
-#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \
-                         ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \
-                         ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \
-                         ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \
-                         ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \
-                         ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \
-                         ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \
-                         ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ))
-#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \
-                         ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \
-                         ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \
-                         ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
-#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)
-#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U)
-#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
-                                  ((MODE) == CAN_FILTERMODE_IDLIST))
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
-                                    ((SCALE) == CAN_FILTERSCALE_32BIT))
-#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \
-                                              ((ACTIVATION) == CAN_FILTER_ENABLE))
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
-                                  ((FIFO) == CAN_FILTER_FIFO1))
-#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
-                                            ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
-                                            ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
-#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))
-#define IS_CAN_STDID(STDID)   ((STDID) <= 0x7FFU)
-#define IS_CAN_EXTID(EXTID)   ((EXTID) <= 0x1FFFFFFFU)
-#define IS_CAN_DLC(DLC)       ((DLC) <= 8U)
-#define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
-                                ((IDTYPE) == CAN_ID_EXT))
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1))
-#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY     | CAN_IT_RX_FIFO0_MSG_PENDING      | \
-                                CAN_IT_RX_FIFO0_FULL        | CAN_IT_RX_FIFO0_OVERRUN          | \
-                                CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL             | \
-                                CAN_IT_RX_FIFO1_OVERRUN     | CAN_IT_WAKEUP                    | \
-                                CAN_IT_SLEEP_ACK            | CAN_IT_ERROR_WARNING             | \
-                                CAN_IT_ERROR_PASSIVE        | CAN_IT_BUSOFF                    | \
-                                CAN_IT_LAST_ERROR_CODE      | CAN_IT_ERROR))
-
-/**
-  * @}
-  */
-/* End of private macros -----------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-
-#endif /* CAN1 */
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32F4xx_HAL_CAN_H */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_can.h
+  * @author  MCD Application Team
+  * @brief   Header file of CAN HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32F4xx_HAL_CAN_H
+#define STM32F4xx_HAL_CAN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+#if defined (CAN1)
+/** @addtogroup CAN
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Types CAN Exported Types
+  * @{
+  */
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_CAN_STATE_RESET             = 0x00U,  /*!< CAN not yet initialized or disabled */
+  HAL_CAN_STATE_READY             = 0x01U,  /*!< CAN initialized and ready for use   */
+  HAL_CAN_STATE_LISTENING         = 0x02U,  /*!< CAN receive process is ongoing      */
+  HAL_CAN_STATE_SLEEP_PENDING     = 0x03U,  /*!< CAN sleep request is pending        */
+  HAL_CAN_STATE_SLEEP_ACTIVE      = 0x04U,  /*!< CAN sleep mode is active            */
+  HAL_CAN_STATE_ERROR             = 0x05U   /*!< CAN error state                     */
+
+} HAL_CAN_StateTypeDef;
+
+/**
+  * @brief  CAN init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;                  /*!< Specifies the length of a time quantum.
+                                            This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
+
+  uint32_t Mode;                       /*!< Specifies the CAN operating mode.
+                                            This parameter can be a value of @ref CAN_operating_mode */
+
+  uint32_t SyncJumpWidth;              /*!< Specifies the maximum number of time quanta the CAN hardware
+                                            is allowed to lengthen or shorten a bit to perform resynchronization.
+                                            This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+  uint32_t TimeSeg1;                   /*!< Specifies the number of time quanta in Bit Segment 1.
+                                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+  uint32_t TimeSeg2;                   /*!< Specifies the number of time quanta in Bit Segment 2.
+                                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+  FunctionalState TimeTriggeredMode;   /*!< Enable or disable the time triggered communication mode.
+                                            This parameter can be set to ENABLE or DISABLE. */
+
+  FunctionalState AutoBusOff;          /*!< Enable or disable the automatic bus-off management.
+                                            This parameter can be set to ENABLE or DISABLE. */
+
+  FunctionalState AutoWakeUp;          /*!< Enable or disable the automatic wake-up mode.
+                                            This parameter can be set to ENABLE or DISABLE. */
+
+  FunctionalState AutoRetransmission;  /*!< Enable or disable the non-automatic retransmission mode.
+                                            This parameter can be set to ENABLE or DISABLE. */
+
+  FunctionalState ReceiveFifoLocked;   /*!< Enable or disable the Receive FIFO Locked mode.
+                                            This parameter can be set to ENABLE or DISABLE. */
+
+  FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.
+                                            This parameter can be set to ENABLE or DISABLE. */
+
+} CAN_InitTypeDef;
+
+/**
+  * @brief  CAN filter configuration structure definition
+  */
+typedef struct
+{
+  uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
+                                       configuration, first one for a 16-bit configuration).
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+  uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
+                                       configuration, second one for a 16-bit configuration).
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+  uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
+                                       according to the mode (MSBs for a 32-bit configuration,
+                                       first one for a 16-bit configuration).
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+  uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
+                                       according to the mode (LSBs for a 32-bit configuration,
+                                       second one for a 16-bit configuration).
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
+
+  uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
+                                       This parameter can be a value of @ref CAN_filter_FIFO */
+
+  uint32_t FilterBank;            /*!< Specifies the filter bank which will be initialized.
+                                       For single CAN instance(14 dedicated filter banks),
+                                       this parameter must be a number between Min_Data = 0 and Max_Data = 13.
+                                       For dual CAN instances(28 filter banks shared),
+                                       this parameter must be a number between Min_Data = 0 and Max_Data = 27. */
+
+  uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
+                                       This parameter can be a value of @ref CAN_filter_mode */
+
+  uint32_t FilterScale;           /*!< Specifies the filter scale.
+                                       This parameter can be a value of @ref CAN_filter_scale */
+
+  uint32_t FilterActivation;      /*!< Enable or disable the filter.
+                                       This parameter can be a value of @ref CAN_filter_activation */
+
+  uint32_t SlaveStartFilterBank;  /*!< Select the start filter bank for the slave CAN instance.
+                                       For single CAN instances, this parameter is meaningless.
+                                       For dual CAN instances, all filter banks with lower index are assigned to master
+                                       CAN instance, whereas all filter banks with greater index are assigned to slave
+                                       CAN instance.
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
+
+} CAN_FilterTypeDef;
+
+/**
+  * @brief  CAN Tx message header structure definition
+  */
+typedef struct
+{
+  uint32_t StdId;    /*!< Specifies the standard identifier.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
+
+  uint32_t ExtId;    /*!< Specifies the extended identifier.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
+
+  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
+                          This parameter can be a value of @ref CAN_identifier_type */
+
+  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
+                          This parameter can be a value of @ref CAN_remote_transmission_request */
+
+  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
+
+  FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start
+                          of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7].
+                          @note: Time Triggered Communication Mode must be enabled.
+                          @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent.
+                          This parameter can be set to ENABLE or DISABLE. */
+
+} CAN_TxHeaderTypeDef;
+
+/**
+  * @brief  CAN Rx message header structure definition
+  */
+typedef struct
+{
+  uint32_t StdId;    /*!< Specifies the standard identifier.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
+
+  uint32_t ExtId;    /*!< Specifies the extended identifier.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
+
+  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
+                          This parameter can be a value of @ref CAN_identifier_type */
+
+  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
+                          This parameter can be a value of @ref CAN_remote_transmission_request */
+
+  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
+
+  uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.
+                          @note: Time Triggered Communication Mode must be enabled.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */
+
+  uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
+
+} CAN_RxHeaderTypeDef;
+
+/**
+  * @brief  CAN handle Structure definition
+  */
+typedef struct __CAN_HandleTypeDef
+{
+  CAN_TypeDef                 *Instance;                 /*!< Register base address */
+
+  CAN_InitTypeDef             Init;                      /*!< CAN required parameters */
+
+  __IO HAL_CAN_StateTypeDef   State;                     /*!< CAN communication state */
+
+  __IO uint32_t               ErrorCode;                 /*!< CAN Error code.
+                                                              This parameter can be a value of @ref CAN_Error_Code */
+
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+  void (* TxMailbox0CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 0 complete callback    */
+  void (* TxMailbox1CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 1 complete callback    */
+  void (* TxMailbox2CompleteCallback)(struct __CAN_HandleTypeDef *hcan);/*!< CAN Tx Mailbox 2 complete callback    */
+  void (* TxMailbox0AbortCallback)(struct __CAN_HandleTypeDef *hcan);   /*!< CAN Tx Mailbox 0 abort callback       */
+  void (* TxMailbox1AbortCallback)(struct __CAN_HandleTypeDef *hcan);   /*!< CAN Tx Mailbox 1 abort callback       */
+  void (* TxMailbox2AbortCallback)(struct __CAN_HandleTypeDef *hcan);   /*!< CAN Tx Mailbox 2 abort callback       */
+  void (* RxFifo0MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 0 msg pending callback    */
+  void (* RxFifo0FullCallback)(struct __CAN_HandleTypeDef *hcan);       /*!< CAN Rx FIFO 0 full callback           */
+  void (* RxFifo1MsgPendingCallback)(struct __CAN_HandleTypeDef *hcan); /*!< CAN Rx FIFO 1 msg pending callback    */
+  void (* RxFifo1FullCallback)(struct __CAN_HandleTypeDef *hcan);       /*!< CAN Rx FIFO 1 full callback           */
+  void (* SleepCallback)(struct __CAN_HandleTypeDef *hcan);             /*!< CAN Sleep callback                    */
+  void (* WakeUpFromRxMsgCallback)(struct __CAN_HandleTypeDef *hcan);   /*!< CAN Wake Up from Rx msg callback      */
+  void (* ErrorCallback)(struct __CAN_HandleTypeDef *hcan);             /*!< CAN Error callback                    */
+
+  void (* MspInitCallback)(struct __CAN_HandleTypeDef *hcan);           /*!< CAN Msp Init callback                 */
+  void (* MspDeInitCallback)(struct __CAN_HandleTypeDef *hcan);         /*!< CAN Msp DeInit callback               */
+
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
+} CAN_HandleTypeDef;
+
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+/**
+  * @brief  HAL CAN common Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID       = 0x00U,    /*!< CAN Tx Mailbox 0 complete callback ID         */
+  HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID       = 0x01U,    /*!< CAN Tx Mailbox 1 complete callback ID         */
+  HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID       = 0x02U,    /*!< CAN Tx Mailbox 2 complete callback ID         */
+  HAL_CAN_TX_MAILBOX0_ABORT_CB_ID          = 0x03U,    /*!< CAN Tx Mailbox 0 abort callback ID            */
+  HAL_CAN_TX_MAILBOX1_ABORT_CB_ID          = 0x04U,    /*!< CAN Tx Mailbox 1 abort callback ID            */
+  HAL_CAN_TX_MAILBOX2_ABORT_CB_ID          = 0x05U,    /*!< CAN Tx Mailbox 2 abort callback ID            */
+  HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID       = 0x06U,    /*!< CAN Rx FIFO 0 message pending callback ID     */
+  HAL_CAN_RX_FIFO0_FULL_CB_ID              = 0x07U,    /*!< CAN Rx FIFO 0 full callback ID                */
+  HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID       = 0x08U,    /*!< CAN Rx FIFO 1 message pending callback ID     */
+  HAL_CAN_RX_FIFO1_FULL_CB_ID              = 0x09U,    /*!< CAN Rx FIFO 1 full callback ID                */
+  HAL_CAN_SLEEP_CB_ID                      = 0x0AU,    /*!< CAN Sleep callback ID                         */
+  HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID         = 0x0BU,    /*!< CAN Wake Up from Rx msg callback ID          */
+  HAL_CAN_ERROR_CB_ID                      = 0x0CU,    /*!< CAN Error callback ID                         */
+
+  HAL_CAN_MSPINIT_CB_ID                    = 0x0DU,    /*!< CAN MspInit callback ID                       */
+  HAL_CAN_MSPDEINIT_CB_ID                  = 0x0EU,    /*!< CAN MspDeInit callback ID                     */
+
+} HAL_CAN_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL CAN Callback pointer definition
+  */
+typedef  void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to a CAN callback function   */
+
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants CAN Exported Constants
+  * @{
+  */
+
+/** @defgroup CAN_Error_Code CAN Error Code
+  * @{
+  */
+#define HAL_CAN_ERROR_NONE            (0x00000000U)  /*!< No error                                             */
+#define HAL_CAN_ERROR_EWG             (0x00000001U)  /*!< Protocol Error Warning                               */
+#define HAL_CAN_ERROR_EPV             (0x00000002U)  /*!< Error Passive                                        */
+#define HAL_CAN_ERROR_BOF             (0x00000004U)  /*!< Bus-off error                                        */
+#define HAL_CAN_ERROR_STF             (0x00000008U)  /*!< Stuff error                                          */
+#define HAL_CAN_ERROR_FOR             (0x00000010U)  /*!< Form error                                           */
+#define HAL_CAN_ERROR_ACK             (0x00000020U)  /*!< Acknowledgment error                                 */
+#define HAL_CAN_ERROR_BR              (0x00000040U)  /*!< Bit recessive error                                  */
+#define HAL_CAN_ERROR_BD              (0x00000080U)  /*!< Bit dominant error                                   */
+#define HAL_CAN_ERROR_CRC             (0x00000100U)  /*!< CRC error                                            */
+#define HAL_CAN_ERROR_RX_FOV0         (0x00000200U)  /*!< Rx FIFO0 overrun error                               */
+#define HAL_CAN_ERROR_RX_FOV1         (0x00000400U)  /*!< Rx FIFO1 overrun error                               */
+#define HAL_CAN_ERROR_TX_ALST0        (0x00000800U)  /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR0        (0x00001000U)  /*!< TxMailbox 0 transmit failure due to transmit error    */
+#define HAL_CAN_ERROR_TX_ALST1        (0x00002000U)  /*!< TxMailbox 1 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR1        (0x00004000U)  /*!< TxMailbox 1 transmit failure due to transmit error    */
+#define HAL_CAN_ERROR_TX_ALST2        (0x00008000U)  /*!< TxMailbox 2 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR2        (0x00010000U)  /*!< TxMailbox 2 transmit failure due to transmit error    */
+#define HAL_CAN_ERROR_TIMEOUT         (0x00020000U)  /*!< Timeout error                                        */
+#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U)  /*!< Peripheral not initialized                           */
+#define HAL_CAN_ERROR_NOT_READY       (0x00080000U)  /*!< Peripheral not ready                                 */
+#define HAL_CAN_ERROR_NOT_STARTED     (0x00100000U)  /*!< Peripheral not started                               */
+#define HAL_CAN_ERROR_PARAM           (0x00200000U)  /*!< Parameter error                                      */
+
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+#define HAL_CAN_ERROR_INVALID_CALLBACK (0x00400000U) /*!< Invalid Callback error                               */
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+#define HAL_CAN_ERROR_INTERNAL        (0x00800000U)  /*!< Internal error                                       */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_InitStatus CAN InitStatus
+  * @{
+  */
+#define CAN_INITSTATUS_FAILED       (0x00000000U)  /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS      (0x00000001U)  /*!< CAN initialization OK     */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_operating_mode CAN Operating Mode
+  * @{
+  */
+#define CAN_MODE_NORMAL             (0x00000000U)                              /*!< Normal mode   */
+#define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
+#define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
+#define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
+  * @{
+  */
+#define CAN_SJW_1TQ                 (0x00000000U)              /*!< 1 time quantum */
+#define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
+#define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
+#define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
+  * @{
+  */
+#define CAN_BS1_1TQ                 (0x00000000U)                                                /*!< 1 time quantum  */
+#define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
+#define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
+#define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
+#define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */
+#define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */
+#define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */
+#define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */
+#define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */
+#define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */
+#define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */
+#define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */
+#define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */
+#define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
+#define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
+#define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
+  * @{
+  */
+#define CAN_BS2_1TQ                 (0x00000000U)                                /*!< 1 time quantum */
+#define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
+#define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
+#define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
+#define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */
+#define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
+#define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
+#define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_mode CAN Filter Mode
+  * @{
+  */
+#define CAN_FILTERMODE_IDMASK       (0x00000000U)  /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST       (0x00000001U)  /*!< Identifier list mode */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_scale CAN Filter Scale
+  * @{
+  */
+#define CAN_FILTERSCALE_16BIT       (0x00000000U)  /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT       (0x00000001U)  /*!< One 32-bit filter  */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_activation CAN Filter Activation
+  * @{
+  */
+#define CAN_FILTER_DISABLE          (0x00000000U)  /*!< Disable filter */
+#define CAN_FILTER_ENABLE           (0x00000001U)  /*!< Enable filter  */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_FIFO CAN Filter FIFO
+  * @{
+  */
+#define CAN_FILTER_FIFO0            (0x00000000U)  /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1            (0x00000001U)  /*!< Filter FIFO 1 assignment for filter x */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_identifier_type CAN Identifier Type
+  * @{
+  */
+#define CAN_ID_STD                  (0x00000000U)  /*!< Standard Id */
+#define CAN_ID_EXT                  (0x00000004U)  /*!< Extended Id */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
+  * @{
+  */
+#define CAN_RTR_DATA                (0x00000000U)  /*!< Data frame   */
+#define CAN_RTR_REMOTE              (0x00000002U)  /*!< Remote frame */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
+  * @{
+  */
+#define CAN_RX_FIFO0                (0x00000000U)  /*!< CAN receive FIFO 0 */
+#define CAN_RX_FIFO1                (0x00000001U)  /*!< CAN receive FIFO 1 */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes
+  * @{
+  */
+#define CAN_TX_MAILBOX0             (0x00000001U)  /*!< Tx Mailbox 0  */
+#define CAN_TX_MAILBOX1             (0x00000002U)  /*!< Tx Mailbox 1  */
+#define CAN_TX_MAILBOX2             (0x00000004U)  /*!< Tx Mailbox 2  */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_flags CAN Flags
+  * @{
+  */
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0              (0x00000500U)  /*!< Request complete MailBox 0 flag   */
+#define CAN_FLAG_TXOK0              (0x00000501U)  /*!< Transmission OK MailBox 0 flag    */
+#define CAN_FLAG_ALST0              (0x00000502U)  /*!< Arbitration Lost MailBox 0 flag   */
+#define CAN_FLAG_TERR0              (0x00000503U)  /*!< Transmission error MailBox 0 flag */
+#define CAN_FLAG_RQCP1              (0x00000508U)  /*!< Request complete MailBox1 flag    */
+#define CAN_FLAG_TXOK1              (0x00000509U)  /*!< Transmission OK MailBox 1 flag    */
+#define CAN_FLAG_ALST1              (0x0000050AU)  /*!< Arbitration Lost MailBox 1 flag   */
+#define CAN_FLAG_TERR1              (0x0000050BU)  /*!< Transmission error MailBox 1 flag */
+#define CAN_FLAG_RQCP2              (0x00000510U)  /*!< Request complete MailBox2 flag    */
+#define CAN_FLAG_TXOK2              (0x00000511U)  /*!< Transmission OK MailBox 2 flag    */
+#define CAN_FLAG_ALST2              (0x00000512U)  /*!< Arbitration Lost MailBox 2 flag   */
+#define CAN_FLAG_TERR2              (0x00000513U)  /*!< Transmission error MailBox 2 flag */
+#define CAN_FLAG_TME0               (0x0000051AU)  /*!< Transmit mailbox 0 empty flag     */
+#define CAN_FLAG_TME1               (0x0000051BU)  /*!< Transmit mailbox 1 empty flag     */
+#define CAN_FLAG_TME2               (0x0000051CU)  /*!< Transmit mailbox 2 empty flag     */
+#define CAN_FLAG_LOW0               (0x0000051DU)  /*!< Lowest priority mailbox 0 flag    */
+#define CAN_FLAG_LOW1               (0x0000051EU)  /*!< Lowest priority mailbox 1 flag    */
+#define CAN_FLAG_LOW2               (0x0000051FU)  /*!< Lowest priority mailbox 2 flag    */
+
+/* Receive Flags */
+#define CAN_FLAG_FF0                (0x00000203U)  /*!< RX FIFO 0 Full flag               */
+#define CAN_FLAG_FOV0               (0x00000204U)  /*!< RX FIFO 0 Overrun flag            */
+#define CAN_FLAG_FF1                (0x00000403U)  /*!< RX FIFO 1 Full flag               */
+#define CAN_FLAG_FOV1               (0x00000404U)  /*!< RX FIFO 1 Overrun flag            */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_INAK               (0x00000100U)  /*!< Initialization acknowledge flag   */
+#define CAN_FLAG_SLAK               (0x00000101U)  /*!< Sleep acknowledge flag            */
+#define CAN_FLAG_ERRI               (0x00000102U)  /*!< Error flag                        */
+#define CAN_FLAG_WKU                (0x00000103U)  /*!< Wake up interrupt flag            */
+#define CAN_FLAG_SLAKI              (0x00000104U)  /*!< Sleep acknowledge interrupt flag  */
+
+/* Error Flags */
+#define CAN_FLAG_EWG                (0x00000300U)  /*!< Error warning flag                */
+#define CAN_FLAG_EPV                (0x00000301U)  /*!< Error passive flag                */
+#define CAN_FLAG_BOF                (0x00000302U)  /*!< Bus-Off flag                      */
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_Interrupts CAN Interrupts
+  * @{
+  */
+/* Transmit Interrupt */
+#define CAN_IT_TX_MAILBOX_EMPTY     ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
+
+/* Receive Interrupts */
+#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_RX_FIFO0_FULL        ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
+#define CAN_IT_RX_FIFO0_OVERRUN     ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
+#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_RX_FIFO1_FULL        ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
+#define CAN_IT_RX_FIFO1_OVERRUN     ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WAKEUP               ((uint32_t)CAN_IER_WKUIE)   /*!< Wake-up interrupt                */
+#define CAN_IT_SLEEP_ACK            ((uint32_t)CAN_IER_SLKIE)   /*!< Sleep acknowledge interrupt      */
+
+/* Error Interrupts */
+#define CAN_IT_ERROR_WARNING        ((uint32_t)CAN_IER_EWGIE)   /*!< Error warning interrupt          */
+#define CAN_IT_ERROR_PASSIVE        ((uint32_t)CAN_IER_EPVIE)   /*!< Error passive interrupt          */
+#define CAN_IT_BUSOFF               ((uint32_t)CAN_IER_BOFIE)   /*!< Bus-off interrupt                */
+#define CAN_IT_LAST_ERROR_CODE      ((uint32_t)CAN_IER_LECIE)   /*!< Last error code interrupt        */
+#define CAN_IT_ERROR                ((uint32_t)CAN_IER_ERRIE)   /*!< Error Interrupt                  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CAN_Exported_Macros CAN Exported Macros
+  * @{
+  */
+
+/** @brief  Reset CAN handle state
+  * @param  __HANDLE__ CAN handle.
+  * @retval None
+  */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) do{                                              \
+                                                     (__HANDLE__)->State = HAL_CAN_STATE_RESET;   \
+                                                     (__HANDLE__)->MspInitCallback = NULL;        \
+                                                     (__HANDLE__)->MspDeInitCallback = NULL;      \
+                                                   } while(0)
+#else
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+#endif /*USE_HAL_CAN_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable the specified CAN interrupts.
+  * @param  __HANDLE__ CAN handle.
+  * @param  __INTERRUPT__ CAN Interrupt sources to enable.
+  *           This parameter can be any combination of @arg CAN_Interrupts
+  * @retval None
+  */
+#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified CAN interrupts.
+  * @param  __HANDLE__ CAN handle.
+  * @param  __INTERRUPT__ CAN Interrupt sources to disable.
+  *           This parameter can be any combination of @arg CAN_Interrupts
+  * @retval None
+  */
+#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/** @brief  Check if the specified CAN interrupt source is enabled or disabled.
+  * @param  __HANDLE__ specifies the CAN Handle.
+  * @param  __INTERRUPT__ specifies the CAN interrupt source to check.
+  *           This parameter can be a value of @arg CAN_Interrupts
+  * @retval The state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__))
+
+/** @brief  Check whether the specified CAN flag is set or not.
+  * @param  __HANDLE__ specifies the CAN Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of @arg CAN_flags
+  * @retval The state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
+  ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+   (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+   (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+   (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+   (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
+
+/** @brief  Clear the specified CAN pending flag.
+  * @param  __HANDLE__ specifies the CAN Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag
+  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag
+  *            @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag
+  *            @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag
+  *            @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag
+  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag
+  *            @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag
+  *            @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag
+  *            @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag
+  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag
+  *            @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag
+  *            @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag
+  *            @arg CAN_FLAG_FF0:   RX FIFO 0 Full Flag
+  *            @arg CAN_FLAG_FOV0:  RX FIFO 0 Overrun Flag
+  *            @arg CAN_FLAG_FF1:   RX FIFO 1 Full Flag
+  *            @arg CAN_FLAG_FOV1:  RX FIFO 1 Overrun Flag
+  *            @arg CAN_FLAG_WKUI:  Wake up Interrupt Flag
+  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag
+  * @retval None
+  */
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+  ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+   (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+   (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+   (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CAN_Exported_Functions CAN Exported Functions
+  * @{
+  */
+
+/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
+
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan));
+HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID);
+
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions
+ *  @brief    Configuration functions
+ * @{
+ */
+
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group3 Control functions
+ *  @brief    Control functions
+ * @{
+ */
+
+/* Control functions **********************************************************/
+HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);
+HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
+uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);
+uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
+uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
+HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
+uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management
+ *  @brief    Interrupts management
+ * @{
+ */
+/* Interrupts management ******************************************************/
+HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs);
+HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs);
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group5 Callback functions
+ *  @brief    Callback functions
+ * @{
+ */
+/* Callbacks functions ********************************************************/
+
+void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
+ *  @brief   CAN Peripheral State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CAN_Private_Types CAN Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Variables CAN Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+  * @{
+  */
+#define CAN_FLAG_MASK  (0x000000FFU)
+/**
+  * @}
+  */
+
+/* Private Macros -----------------------------------------------------------*/
+/** @defgroup CAN_Private_Macros CAN Private Macros
+  * @{
+  */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+                           ((MODE) == CAN_MODE_LOOPBACK)|| \
+                           ((MODE) == CAN_MODE_SILENT) || \
+                           ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \
+                         ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \
+                         ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \
+                         ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \
+                         ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \
+                         ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \
+                         ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \
+                         ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \
+                         ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ))
+#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \
+                         ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \
+                         ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \
+                         ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
+#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)
+#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U)
+#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+                                  ((MODE) == CAN_FILTERMODE_IDLIST))
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+                                    ((SCALE) == CAN_FILTERSCALE_32BIT))
+#define IS_CAN_FILTER_ACTIVATION(ACTIVATION) (((ACTIVATION) == CAN_FILTER_DISABLE) || \
+                                              ((ACTIVATION) == CAN_FILTER_ENABLE))
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+                                  ((FIFO) == CAN_FILTER_FIFO1))
+#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
+                                            ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
+                                            ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
+#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))
+#define IS_CAN_STDID(STDID)   ((STDID) <= 0x7FFU)
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= 0x1FFFFFFFU)
+#define IS_CAN_DLC(DLC)       ((DLC) <= 8U)
+#define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
+                                ((IDTYPE) == CAN_ID_EXT))
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1))
+#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY     | CAN_IT_RX_FIFO0_MSG_PENDING      | \
+                                CAN_IT_RX_FIFO0_FULL        | CAN_IT_RX_FIFO0_OVERRUN          | \
+                                CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL             | \
+                                CAN_IT_RX_FIFO1_OVERRUN     | CAN_IT_WAKEUP                    | \
+                                CAN_IT_SLEEP_ACK            | CAN_IT_ERROR_WARNING             | \
+                                CAN_IT_ERROR_PASSIVE        | CAN_IT_BUSOFF                    | \
+                                CAN_IT_LAST_ERROR_CODE      | CAN_IT_ERROR))
+
+/**
+  * @}
+  */
+/* End of private macros -----------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+
+#endif /* CAN1 */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32F4xx_HAL_CAN_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h
index fdc96b5..935be05 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h
@@ -1,407 +1,407 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_cortex.h
-  * @author  MCD Application Team
-  * @brief   Header file of CORTEX HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CORTEX_H
-#define __STM32F4xx_HAL_CORTEX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CORTEX
-  * @{
-  */ 
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Types Cortex Exported Types
-  * @{
-  */
-
-#if (__MPU_PRESENT == 1U)
-/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
-  * @brief  MPU Region initialization structure 
-  * @{
-  */
-typedef struct
-{
-  uint8_t                Enable;                /*!< Specifies the status of the region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
-  uint8_t                Number;                /*!< Specifies the number of the region to protect. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
-  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
-  uint8_t                Size;                  /*!< Specifies the size of the region to protect. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
-  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. 
-                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */         
-  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
-                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */                 
-  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
-  uint8_t                DisableExec;           /*!< Specifies the instruction access status. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
-  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
-  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
-  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. 
-                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
-}MPU_Region_InitTypeDef;
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
-  * @{
-  */
-
-/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
-  * @{
-  */
-#define NVIC_PRIORITYGROUP_0         0x00000007U /*!< 0 bits for pre-emption priority
-                                                      4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1         0x00000006U /*!< 1 bits for pre-emption priority
-                                                      3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2         0x00000005U /*!< 2 bits for pre-emption priority
-                                                      2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3         0x00000004U /*!< 3 bits for pre-emption priority
-                                                      1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4         0x00000003U /*!< 4 bits for pre-emption priority
-                                                      0 bits for subpriority */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source 
-  * @{
-  */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8    0x00000000U
-#define SYSTICK_CLKSOURCE_HCLK         0x00000004U
-
-/**
-  * @}
-  */
-
-#if (__MPU_PRESENT == 1)
-/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
-  * @{
-  */
-#define  MPU_HFNMI_PRIVDEF_NONE           0x00000000U
-#define  MPU_HARDFAULT_NMI                MPU_CTRL_HFNMIENA_Msk
-#define  MPU_PRIVILEGED_DEFAULT           MPU_CTRL_PRIVDEFENA_Msk
-#define  MPU_HFNMI_PRIVDEF               (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
-  * @{
-  */
-#define  MPU_REGION_ENABLE     ((uint8_t)0x01)
-#define  MPU_REGION_DISABLE    ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
-  * @{
-  */
-#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
-#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
-  * @{
-  */
-#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
-  * @{
-  */
-#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
-  * @{
-  */
-#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
-#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
-  * @{
-  */
-#define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
-#define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
-#define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
-  * @{
-  */
-#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
-#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
-#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
-#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
-#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
-#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
-#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
-#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
-#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
-#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
-#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
-#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
-#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
-#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
-#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
-#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
-#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
-#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
-#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
-#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
-#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
-#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
-#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
-#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
-#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
-#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
-#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
-#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
-/**
-  * @}
-  */
-   
-/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
-  * @{
-  */
-#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
-#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
-#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
-#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
-#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
-#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
-  * @{
-  */
-#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
-#define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
-#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
-#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
-#define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
-#define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
-#define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
-#define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-
-/**
-  * @}
-  */
-
-
-/* Exported Macros -----------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CORTEX_Exported_Functions
-  * @{
-  */
-  
-/** @addtogroup CORTEX_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-/**
-  * @}
-  */
-
-/** @addtogroup CORTEX_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_NVIC_GetPriorityGrouping(void);
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void HAL_SYSTICK_IRQHandler(void);
-void HAL_SYSTICK_Callback(void);
-
-#if (__MPU_PRESENT == 1U)
-void HAL_MPU_Enable(uint32_t MPU_Control);
-void HAL_MPU_Disable(void);
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
-#endif /* __MPU_PRESENT */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
-  * @{
-  */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)
-
-#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= (IRQn_Type)0x00U)
-
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
-                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-
-#if (__MPU_PRESENT == 1U)
-#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
-                                     ((STATE) == MPU_REGION_DISABLE))
-
-#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
-                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
-
-#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
-
-#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
-
-#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
-                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
-
-#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
-                                ((TYPE) == MPU_TEX_LEVEL1)  || \
-                                ((TYPE) == MPU_TEX_LEVEL2))
-
-#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
-                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
-                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
-
-#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
-                                         ((NUMBER) == MPU_REGION_NUMBER7))
-
-#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
-                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
-                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
-                                     ((SIZE) == MPU_REGION_SIZE_4GB))
-
-#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
-#endif /* __MPU_PRESENT */
-
-/**                                                                          
-  * @}                                                                  
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_CORTEX_H */
- 
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CORTEX_H
+#define __STM32F4xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CORTEX
+  * @{
+  */ 
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types Cortex Exported Types
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1U)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+  * @brief  MPU Region initialization structure 
+  * @{
+  */
+typedef struct
+{
+  uint8_t                Enable;                /*!< Specifies the status of the region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
+  uint8_t                Number;                /*!< Specifies the number of the region to protect. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
+  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
+  uint8_t                Size;                  /*!< Specifies the size of the region to protect. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
+  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. 
+                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */         
+  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
+                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */                 
+  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
+  uint8_t                DisableExec;           /*!< Specifies the instruction access status. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
+  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
+  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
+  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
+}MPU_Region_InitTypeDef;
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+  * @{
+  */
+#define NVIC_PRIORITYGROUP_0         0x00000007U /*!< 0 bits for pre-emption priority
+                                                      4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         0x00000006U /*!< 1 bits for pre-emption priority
+                                                      3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         0x00000005U /*!< 2 bits for pre-emption priority
+                                                      2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         0x00000004U /*!< 3 bits for pre-emption priority
+                                                      1 bits for subpriority */
+#define NVIC_PRIORITYGROUP_4         0x00000003U /*!< 4 bits for pre-emption priority
+                                                      0 bits for subpriority */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source 
+  * @{
+  */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    0x00000000U
+#define SYSTICK_CLKSOURCE_HCLK         0x00000004U
+
+/**
+  * @}
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
+  * @{
+  */
+#define  MPU_HFNMI_PRIVDEF_NONE           0x00000000U
+#define  MPU_HARDFAULT_NMI                MPU_CTRL_HFNMIENA_Msk
+#define  MPU_PRIVILEGED_DEFAULT           MPU_CTRL_PRIVDEFENA_Msk
+#define  MPU_HFNMI_PRIVDEF               (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+  * @{
+  */
+#define  MPU_REGION_ENABLE     ((uint8_t)0x01)
+#define  MPU_REGION_DISABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+  * @{
+  */
+#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
+#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+  * @{
+  */
+#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+  * @{
+  */
+#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+  * @{
+  */
+#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
+  * @{
+  */
+#define  MPU_TEX_LEVEL0    ((uint8_t)0x00)
+#define  MPU_TEX_LEVEL1    ((uint8_t)0x01)
+#define  MPU_TEX_LEVEL2    ((uint8_t)0x02)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+  * @{
+  */
+#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)
+#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)
+#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)
+#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)
+#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)
+#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)
+#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)
+#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)
+#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)
+#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)
+#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)
+#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)
+#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)
+#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)
+#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)
+#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)
+#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)
+#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)
+#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)
+#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)
+#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)
+#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)
+#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)
+#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)
+#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)
+#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)
+#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)
+#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)
+/**
+  * @}
+  */
+   
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
+  * @{
+  */
+#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)
+#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)
+#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)
+#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)
+#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)
+#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+  * @{
+  */
+#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)
+#define  MPU_REGION_NUMBER1    ((uint8_t)0x01)
+#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)
+#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)
+#define  MPU_REGION_NUMBER4    ((uint8_t)0x04)
+#define  MPU_REGION_NUMBER5    ((uint8_t)0x05)
+#define  MPU_REGION_NUMBER6    ((uint8_t)0x06)
+#define  MPU_REGION_NUMBER7    ((uint8_t)0x07)
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+
+/* Exported Macros -----------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CORTEX_Exported_Functions
+  * @{
+  */
+  
+/** @addtogroup CORTEX_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+/**
+  * @}
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+
+#if (__MPU_PRESENT == 1U)
+void HAL_MPU_Enable(uint32_t MPU_Control);
+void HAL_MPU_Disable(void);
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+  * @{
+  */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10U)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= (IRQn_Type)0x00U)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1U)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+                                     ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
+                                ((TYPE) == MPU_TEX_LEVEL1)  || \
+                                ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**                                                                          
+  * @}                                                                  
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CORTEX_H */
+ 
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h
index f9bbec2..094b411 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h
@@ -1,210 +1,210 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_def.h
-  * @author  MCD Application Team
-  * @brief   This file contains HAL common defines, enumeration, macros and 
-  *          structures definitions. 
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_DEF
-#define __STM32F4xx_HAL_DEF
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-#include "Legacy/stm32_hal_legacy.h"
-#include <stddef.h>
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  HAL Status structures definition  
-  */  
-typedef enum 
-{
-  HAL_OK       = 0x00U,
-  HAL_ERROR    = 0x01U,
-  HAL_BUSY     = 0x02U,
-  HAL_TIMEOUT  = 0x03U
-} HAL_StatusTypeDef;
-
-/** 
-  * @brief  HAL Lock structures definition  
-  */
-typedef enum 
-{
-  HAL_UNLOCKED = 0x00U,
-  HAL_LOCKED   = 0x01U  
-} HAL_LockTypeDef;
-
-/* Exported macro ------------------------------------------------------------*/
-
-#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
-
-#define HAL_MAX_DELAY      0xFFFFFFFFU
-
-#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
-#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
-
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
-                        do{                                                      \
-                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
-                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
-                          } while(0U)
-
-/** @brief Reset the Handle's State field.
-  * @param __HANDLE__ specifies the Peripheral Handle.
-  * @note  This macro can be used for the following purpose: 
-  *          - When the Handle is declared as local variable; before passing it as parameter
-  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
-  *            to set to 0 the Handle's "State" field.
-  *            Otherwise, "State" field may have any random value and the first time the function 
-  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
-  *            (i.e. HAL_PPP_MspInit() will not be executed).
-  *          - When there is a need to reconfigure the low level hardware: instead of calling
-  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
-  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
-  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
-  * @retval None
-  */
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
-
-#if (USE_RTOS == 1U)
-  /* Reserved for future use */
-  #error "USE_RTOS should be 0 in the current HAL release"
-#else
-  #define __HAL_LOCK(__HANDLE__)                                           \
-                                do{                                        \
-                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
-                                    {                                      \
-                                       return HAL_BUSY;                    \
-                                    }                                      \
-                                    else                                   \
-                                    {                                      \
-                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
-                                    }                                      \
-                                  }while (0U)
-
-  #define __HAL_UNLOCK(__HANDLE__)                                          \
-                                  do{                                       \
-                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
-                                    }while (0U)
-#endif /* USE_RTOS */
-
-#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
-  #ifndef __weak
-    #define __weak  __attribute__((weak))
-  #endif
-  #ifndef __packed
-    #define __packed  __attribute__((packed))
-  #endif
-#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
-  #ifndef __weak
-    #define __weak   __attribute__((weak))
-  #endif /* __weak */
-  #ifndef __packed
-    #define __packed __attribute__((__packed__))
-  #endif /* __packed */
-#endif /* __GNUC__ */
-
-
-/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
-  #ifndef __ALIGN_BEGIN
-    #define __ALIGN_BEGIN
-  #endif
-  #ifndef __ALIGN_END
-    #define __ALIGN_END      __attribute__ ((aligned (4)))
-  #endif
-#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
-  #ifndef __ALIGN_END
-#define __ALIGN_END    __attribute__ ((aligned (4)))
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN  
-    #define __ALIGN_BEGIN
-  #endif /* __ALIGN_BEGIN */
-#else
-  #ifndef __ALIGN_END
-    #define __ALIGN_END
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN      
-    #if defined   (__CC_ARM)      /* ARM Compiler V5*/
-#define __ALIGN_BEGIN    __align(4)
-    #elif defined (__ICCARM__)    /* IAR Compiler */
-      #define __ALIGN_BEGIN 
-    #endif /* __CC_ARM */
-  #endif /* __ALIGN_BEGIN */
-#endif /* __GNUC__ */
-
-
-/** 
-  * @brief  __RAM_FUNC definition
-  */ 
-#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
-/* ARM Compiler V4/V5 and V6
-   --------------------------
-   RAM functions are defined using the toolchain options. 
-   Functions that are executed in RAM should reside in a separate source module.
-   Using the 'Options for File' dialog you can simply change the 'Code / Const' 
-   area of a module to a memory space in physical RAM.
-   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
-   dialog. 
-*/
-#define __RAM_FUNC
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-   RAM functions are defined using a specific toolchain keyword "__ramfunc". 
-*/
-#define __RAM_FUNC __ramfunc
-
-#elif defined   (  __GNUC__  )
-/* GNU Compiler
-   ------------
-  RAM functions are defined using a specific toolchain attribute 
-   "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC __attribute__((section(".RamFunc")))
-
-#endif
-
-/** 
-  * @brief  __NOINLINE definition
-  */ 
-#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined   (  __GNUC__  )
-/* ARM V4/V5 and V6 & GNU Compiler
-   -------------------------------
-*/
-#define __NOINLINE __attribute__ ( (noinline) )
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-*/
-#define __NOINLINE _Pragma("optimize = no_inline")
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32F4xx_HAL_DEF */
-
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_def.h
+  * @author  MCD Application Team
+  * @brief   This file contains HAL common defines, enumeration, macros and 
+  *          structures definitions. 
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DEF
+#define __STM32F4xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+#include "Legacy/stm32_hal_legacy.h"
+#include <stddef.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  HAL Status structures definition  
+  */  
+typedef enum 
+{
+  HAL_OK       = 0x00U,
+  HAL_ERROR    = 0x01U,
+  HAL_BUSY     = 0x02U,
+  HAL_TIMEOUT  = 0x03U
+} HAL_StatusTypeDef;
+
+/** 
+  * @brief  HAL Lock structures definition  
+  */
+typedef enum 
+{
+  HAL_UNLOCKED = 0x00U,
+  HAL_LOCKED   = 0x01U  
+} HAL_LockTypeDef;
+
+/* Exported macro ------------------------------------------------------------*/
+
+#define UNUSED(X) (void)X      /* To avoid gcc/g++ warnings */
+
+#define HAL_MAX_DELAY      0xFFFFFFFFU
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \
+                        do{                                                      \
+                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \
+                          } while(0U)
+
+/** @brief Reset the Handle's State field.
+  * @param __HANDLE__ specifies the Peripheral Handle.
+  * @note  This macro can be used for the following purpose: 
+  *          - When the Handle is declared as local variable; before passing it as parameter
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
+  *            to set to 0 the Handle's "State" field.
+  *            Otherwise, "State" field may have any random value and the first time the function 
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+  * @retval None
+  */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
+
+#if (USE_RTOS == 1U)
+  /* Reserved for future use */
+  #error "USE_RTOS should be 0 in the current HAL release"
+#else
+  #define __HAL_LOCK(__HANDLE__)                                           \
+                                do{                                        \
+                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
+                                    {                                      \
+                                       return HAL_BUSY;                    \
+                                    }                                      \
+                                    else                                   \
+                                    {                                      \
+                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
+                                    }                                      \
+                                  }while (0U)
+
+  #define __HAL_UNLOCK(__HANDLE__)                                          \
+                                  do{                                       \
+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
+                                    }while (0U)
+#endif /* USE_RTOS */
+
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+  #ifndef __weak
+    #define __weak  __attribute__((weak))
+  #endif
+  #ifndef __packed
+    #define __packed  __attribute__((packed))
+  #endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+  #ifndef __weak
+    #define __weak   __attribute__((weak))
+  #endif /* __weak */
+  #ifndef __packed
+    #define __packed __attribute__((__packed__))
+  #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+  #ifndef __ALIGN_BEGIN
+    #define __ALIGN_BEGIN
+  #endif
+  #ifndef __ALIGN_END
+    #define __ALIGN_END      __attribute__ ((aligned (4)))
+  #endif
+#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
+  #ifndef __ALIGN_END
+#define __ALIGN_END    __attribute__ ((aligned (4)))
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN  
+    #define __ALIGN_BEGIN
+  #endif /* __ALIGN_BEGIN */
+#else
+  #ifndef __ALIGN_END
+    #define __ALIGN_END
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN      
+    #if defined   (__CC_ARM)      /* ARM Compiler V5*/
+#define __ALIGN_BEGIN    __align(4)
+    #elif defined (__ICCARM__)    /* IAR Compiler */
+      #define __ALIGN_BEGIN 
+    #endif /* __CC_ARM */
+  #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+
+/** 
+  * @brief  __RAM_FUNC definition
+  */ 
+#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+/* ARM Compiler V4/V5 and V6
+   --------------------------
+   RAM functions are defined using the toolchain options. 
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const' 
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog. 
+*/
+#define __RAM_FUNC
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc". 
+*/
+#define __RAM_FUNC __ramfunc
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute 
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC __attribute__((section(".RamFunc")))
+
+#endif
+
+/** 
+  * @brief  __NOINLINE definition
+  */ 
+#if defined ( __CC_ARM   ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined   (  __GNUC__  )
+/* ARM V4/V5 and V6 & GNU Compiler
+   -------------------------------
+*/
+#define __NOINLINE __attribute__ ( (noinline) )
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32F4xx_HAL_DEF */
+
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h
index 7ff3836..336b2bb 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h
@@ -1,802 +1,802 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_dma.h
-  * @author  MCD Application Team
-  * @brief   Header file of DMA HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_DMA_H
-#define __STM32F4xx_HAL_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DMA
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Types DMA Exported Types
-  * @brief    DMA Exported Types 
-  * @{
-  */
-   
-/** 
-  * @brief  DMA Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Channel;              /*!< Specifies the channel used for the specified stream. 
-                                      This parameter can be a value of @ref DMA_Channel_selection                    */
-
-  uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral, 
-                                      from memory to memory or from peripheral to memory.
-                                      This parameter can be a value of @ref DMA_Data_transfer_direction              */
-
-  uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
-                                      This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
-
-  uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
-                                      This parameter can be a value of @ref DMA_Memory_incremented_mode              */
-
-  uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
-                                      This parameter can be a value of @ref DMA_Peripheral_data_size                 */
-
-  uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
-                                      This parameter can be a value of @ref DMA_Memory_data_size                     */
-
-  uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
-                                      This parameter can be a value of @ref DMA_mode
-                                      @note The circular buffer mode cannot be used if the memory-to-memory
-                                            data transfer is configured on the selected Stream                        */
-
-  uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
-                                      This parameter can be a value of @ref DMA_Priority_level                       */
-
-  uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
-                                      This parameter can be a value of @ref DMA_FIFO_direct_mode
-                                      @note The Direct mode (FIFO mode disabled) cannot be used if the 
-                                            memory-to-memory data transfer is configured on the selected stream       */
-
-  uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
-                                      This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
-
-  uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers. 
-                                      It specifies the amount of data to be transferred in a single non interruptible
-                                      transaction.
-                                      This parameter can be a value of @ref DMA_Memory_burst 
-                                      @note The burst mode is possible only if the address Increment mode is enabled. */
-
-  uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
-                                      It specifies the amount of data to be transferred in a single non interruptible 
-                                      transaction. 
-                                      This parameter can be a value of @ref DMA_Peripheral_burst
-                                      @note The burst mode is possible only if the address Increment mode is enabled. */
-}DMA_InitTypeDef;
-
-
-/** 
-  * @brief  HAL DMA State structures definition
-  */
-typedef enum
-{
-  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
-  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
-  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
-  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                   */
-  HAL_DMA_STATE_ERROR             = 0x04U,  /*!< DMA error state                     */
-  HAL_DMA_STATE_ABORT             = 0x05U,  /*!< DMA Abort state                     */
-}HAL_DMA_StateTypeDef;
-
-/** 
-  * @brief  HAL DMA Error Code structure definition
-  */
-typedef enum
-{
-  HAL_DMA_FULL_TRANSFER           = 0x00U,  /*!< Full transfer     */
-  HAL_DMA_HALF_TRANSFER           = 0x01U   /*!< Half Transfer     */
-}HAL_DMA_LevelCompleteTypeDef;
-
-/** 
-  * @brief  HAL DMA Error Code structure definition
-  */
-typedef enum
-{
-  HAL_DMA_XFER_CPLT_CB_ID         = 0x00U,  /*!< Full transfer     */
-  HAL_DMA_XFER_HALFCPLT_CB_ID     = 0x01U,  /*!< Half Transfer     */
-  HAL_DMA_XFER_M1CPLT_CB_ID       = 0x02U,  /*!< M1 Full Transfer  */
-  HAL_DMA_XFER_M1HALFCPLT_CB_ID   = 0x03U,  /*!< M1 Half Transfer  */
-  HAL_DMA_XFER_ERROR_CB_ID        = 0x04U,  /*!< Error             */
-  HAL_DMA_XFER_ABORT_CB_ID        = 0x05U,  /*!< Abort             */
-  HAL_DMA_XFER_ALL_CB_ID          = 0x06U   /*!< All               */
-}HAL_DMA_CallbackIDTypeDef;
-
-/** 
-  * @brief  DMA handle Structure definition
-  */
-typedef struct __DMA_HandleTypeDef
-{
-  DMA_Stream_TypeDef         *Instance;                                                        /*!< Register base address                  */
-
-  DMA_InitTypeDef            Init;                                                             /*!< DMA communication parameters           */ 
-
-  HAL_LockTypeDef            Lock;                                                             /*!< DMA locking object                     */  
-
-  __IO HAL_DMA_StateTypeDef  State;                                                            /*!< DMA transfer state                     */
-
-  void                       *Parent;                                                          /*!< Parent object state                    */ 
-
-  void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);         /*!< DMA transfer complete callback         */
-
-  void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA Half transfer complete callback    */
-
-  void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer complete Memory1 callback */
-  
-  void                       (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback */
-  
-  void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer error callback            */
-  
-  void                       (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer Abort callback            */  
-
-  __IO uint32_t              ErrorCode;                                                        /*!< DMA Error code                          */
-  
-  uint32_t                   StreamBaseAddress;                                                /*!< DMA Stream Base Address                */
-
-  uint32_t                   StreamIndex;                                                      /*!< DMA Stream Index                       */
- 
-}DMA_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
-  * @brief    DMA Exported constants 
-  * @{
-  */
-
-/** @defgroup DMA_Error_Code DMA Error Code
-  * @brief    DMA Error Code 
-  * @{
-  */ 
-#define HAL_DMA_ERROR_NONE            0x00000000U    /*!< No error                               */
-#define HAL_DMA_ERROR_TE              0x00000001U    /*!< Transfer error                         */
-#define HAL_DMA_ERROR_FE              0x00000002U    /*!< FIFO error                             */
-#define HAL_DMA_ERROR_DME             0x00000004U    /*!< Direct Mode error                      */
-#define HAL_DMA_ERROR_TIMEOUT         0x00000020U    /*!< Timeout error                          */
-#define HAL_DMA_ERROR_PARAM           0x00000040U    /*!< Parameter error                        */
-#define HAL_DMA_ERROR_NO_XFER         0x00000080U    /*!< Abort requested with no Xfer ongoing   */
-#define HAL_DMA_ERROR_NOT_SUPPORTED   0x00000100U    /*!< Not supported mode                     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Channel_selection DMA Channel selection
-  * @brief    DMA channel selection 
-  * @{
-  */ 
-#define DMA_CHANNEL_0                 0x00000000U    /*!< DMA Channel 0 */
-#define DMA_CHANNEL_1                 0x02000000U    /*!< DMA Channel 1 */
-#define DMA_CHANNEL_2                 0x04000000U    /*!< DMA Channel 2 */
-#define DMA_CHANNEL_3                 0x06000000U    /*!< DMA Channel 3 */
-#define DMA_CHANNEL_4                 0x08000000U    /*!< DMA Channel 4 */
-#define DMA_CHANNEL_5                 0x0A000000U    /*!< DMA Channel 5 */
-#define DMA_CHANNEL_6                 0x0C000000U    /*!< DMA Channel 6 */
-#define DMA_CHANNEL_7                 0x0E000000U    /*!< DMA Channel 7 */
-#if defined (DMA_SxCR_CHSEL_3)
-#define DMA_CHANNEL_8                 0x10000000U    /*!< DMA Channel 8 */
-#define DMA_CHANNEL_9                 0x12000000U    /*!< DMA Channel 9 */
-#define DMA_CHANNEL_10                0x14000000U    /*!< DMA Channel 10 */
-#define DMA_CHANNEL_11                0x16000000U    /*!< DMA Channel 11 */
-#define DMA_CHANNEL_12                0x18000000U    /*!< DMA Channel 12 */
-#define DMA_CHANNEL_13                0x1A000000U    /*!< DMA Channel 13 */
-#define DMA_CHANNEL_14                0x1C000000U    /*!< DMA Channel 14 */
-#define DMA_CHANNEL_15                0x1E000000U    /*!< DMA Channel 15 */
-#endif /* DMA_SxCR_CHSEL_3 */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
-  * @brief    DMA data transfer direction 
-  * @{
-  */ 
-#define DMA_PERIPH_TO_MEMORY          0x00000000U                 /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH          ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY          ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
-/**
-  * @}
-  */
-        
-/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
-  * @brief    DMA peripheral incremented mode 
-  * @{
-  */ 
-#define DMA_PINC_ENABLE               ((uint32_t)DMA_SxCR_PINC)   /*!< Peripheral increment mode enable  */
-#define DMA_PINC_DISABLE              0x00000000U                 /*!< Peripheral increment mode disable */
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
-  * @brief    DMA memory incremented mode 
-  * @{
-  */ 
-#define DMA_MINC_ENABLE               ((uint32_t)DMA_SxCR_MINC)   /*!< Memory increment mode enable  */
-#define DMA_MINC_DISABLE              0x00000000U                 /*!< Memory increment mode disable */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
-  * @brief    DMA peripheral data size 
-  * @{
-  */ 
-#define DMA_PDATAALIGN_BYTE           0x00000000U                  /*!< Peripheral data alignment: Byte     */
-#define DMA_PDATAALIGN_HALFWORD       ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
-#define DMA_PDATAALIGN_WORD           ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word     */
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_Memory_data_size DMA Memory data size
-  * @brief    DMA memory data size 
-  * @{ 
-  */
-#define DMA_MDATAALIGN_BYTE           0x00000000U                  /*!< Memory data alignment: Byte     */
-#define DMA_MDATAALIGN_HALFWORD       ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
-#define DMA_MDATAALIGN_WORD           ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_mode DMA mode
-  * @brief    DMA mode 
-  * @{
-  */ 
-#define DMA_NORMAL                    0x00000000U                  /*!< Normal mode                  */
-#define DMA_CIRCULAR                  ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */
-#define DMA_PFCTRL                    ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Priority_level DMA Priority level
-  * @brief    DMA priority levels 
-  * @{
-  */
-#define DMA_PRIORITY_LOW              0x00000000U                 /*!< Priority level: Low       */
-#define DMA_PRIORITY_MEDIUM           ((uint32_t)DMA_SxCR_PL_0)   /*!< Priority level: Medium    */
-#define DMA_PRIORITY_HIGH             ((uint32_t)DMA_SxCR_PL_1)   /*!< Priority level: High      */
-#define DMA_PRIORITY_VERY_HIGH        ((uint32_t)DMA_SxCR_PL)     /*!< Priority level: Very High */
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
-  * @brief    DMA FIFO direct mode
-  * @{
-  */
-#define DMA_FIFOMODE_DISABLE          0x00000000U                 /*!< FIFO mode disable */
-#define DMA_FIFOMODE_ENABLE           ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable  */
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
-  * @brief    DMA FIFO level 
-  * @{
-  */
-#define DMA_FIFO_THRESHOLD_1QUARTERFULL       0x00000000U                  /*!< FIFO threshold 1 quart full configuration  */
-#define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
-#define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
-#define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_Memory_burst DMA Memory burst
-  * @brief    DMA memory burst 
-  * @{
-  */ 
-#define DMA_MBURST_SINGLE             0x00000000U
-#define DMA_MBURST_INC4               ((uint32_t)DMA_SxCR_MBURST_0)  
-#define DMA_MBURST_INC8               ((uint32_t)DMA_SxCR_MBURST_1)  
-#define DMA_MBURST_INC16              ((uint32_t)DMA_SxCR_MBURST)  
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
-  * @brief    DMA peripheral burst 
-  * @{
-  */ 
-#define DMA_PBURST_SINGLE             0x00000000U
-#define DMA_PBURST_INC4               ((uint32_t)DMA_SxCR_PBURST_0)
-#define DMA_PBURST_INC8               ((uint32_t)DMA_SxCR_PBURST_1)
-#define DMA_PBURST_INC16              ((uint32_t)DMA_SxCR_PBURST)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
-  * @brief    DMA interrupts definition 
-  * @{
-  */
-#define DMA_IT_TC                     ((uint32_t)DMA_SxCR_TCIE)
-#define DMA_IT_HT                     ((uint32_t)DMA_SxCR_HTIE)
-#define DMA_IT_TE                     ((uint32_t)DMA_SxCR_TEIE)
-#define DMA_IT_DME                    ((uint32_t)DMA_SxCR_DMEIE)
-#define DMA_IT_FE                     0x00000080U
-/**
-  * @}
-  */
-
-/** @defgroup DMA_flag_definitions DMA flag definitions
-  * @brief    DMA flag definitions 
-  * @{
-  */ 
-#define DMA_FLAG_FEIF0_4              0x00000001U
-#define DMA_FLAG_DMEIF0_4             0x00000004U
-#define DMA_FLAG_TEIF0_4              0x00000008U
-#define DMA_FLAG_HTIF0_4              0x00000010U
-#define DMA_FLAG_TCIF0_4              0x00000020U
-#define DMA_FLAG_FEIF1_5              0x00000040U
-#define DMA_FLAG_DMEIF1_5             0x00000100U
-#define DMA_FLAG_TEIF1_5              0x00000200U
-#define DMA_FLAG_HTIF1_5              0x00000400U
-#define DMA_FLAG_TCIF1_5              0x00000800U
-#define DMA_FLAG_FEIF2_6              0x00010000U
-#define DMA_FLAG_DMEIF2_6             0x00040000U
-#define DMA_FLAG_TEIF2_6              0x00080000U
-#define DMA_FLAG_HTIF2_6              0x00100000U
-#define DMA_FLAG_TCIF2_6              0x00200000U
-#define DMA_FLAG_FEIF3_7              0x00400000U
-#define DMA_FLAG_DMEIF3_7             0x01000000U
-#define DMA_FLAG_TEIF3_7              0x02000000U
-#define DMA_FLAG_HTIF3_7              0x04000000U
-#define DMA_FLAG_TCIF3_7              0x08000000U
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
- 
-/* Exported macro ------------------------------------------------------------*/
-
-/** @brief Reset DMA handle state
-  * @param  __HANDLE__ specifies the DMA handle.
-  * @retval None
-  */
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
-
-/**
-  * @brief  Return the current DMA Stream FIFO filled level.
-  * @param  __HANDLE__ DMA handle
-  * @retval The FIFO filling state.
-  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 
-  *                                              and not empty.
-  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
-  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
-  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
-  *           - DMA_FIFOStatus_Empty: when FIFO is empty
-  *           - DMA_FIFOStatus_Full: when FIFO is full
-  */
-#define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
-
-/**
-  * @brief  Enable the specified DMA Stream.
-  * @param  __HANDLE__ DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)
-
-/**
-  * @brief  Disable the specified DMA Stream.
-  * @param  __HANDLE__ DMA handle
-  * @retval None
-  */
-#define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)
-
-/* Interrupt & Flag management */
-
-/**
-  * @brief  Return the current DMA Stream transfer complete flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified transfer complete flag index.
-  */
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
-   DMA_FLAG_TCIF3_7)
-
-/**
-  * @brief  Return the current DMA Stream half transfer complete flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified half transfer complete flag index.
-  */      
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
-   DMA_FLAG_HTIF3_7)
-
-/**
-  * @brief  Return the current DMA Stream transfer error flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
-   DMA_FLAG_TEIF3_7)
-
-/**
-  * @brief  Return the current DMA Stream FIFO error flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified FIFO error flag index.
-  */
-#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
-   DMA_FLAG_FEIF3_7)
-
-/**
-  * @brief  Return the current DMA Stream direct mode error flag.
-  * @param  __HANDLE__ DMA handle
-  * @retval The specified direct mode error flag index.
-  */
-#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
-   DMA_FLAG_DMEIF3_7)
-
-/**
-  * @brief  Get the DMA Stream pending flags.
-  * @param  __HANDLE__ DMA handle
-  * @param  __FLAG__ Get the specified flag.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
-  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
-  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
-  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
-  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
-  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   
-  * @retval The state of FLAG (SET or RESET).
-  */
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
-
-/**
-  * @brief  Clear the DMA Stream pending flags.
-  * @param  __HANDLE__ DMA handle
-  * @param  __FLAG__ specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
-  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
-  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
-  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
-  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
-  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   
-  * @retval None
-  */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
- ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
-
-/**
-  * @brief  Enable the specified DMA Stream interrupts.
-  * @param  __HANDLE__ DMA handle
-  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
-  *        This parameter can be any combination of the following values:
-  *           @arg DMA_IT_TC: Transfer complete interrupt mask.
-  *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
-  *           @arg DMA_IT_TE: Transfer error interrupt mask.
-  *           @arg DMA_IT_FE: FIFO error interrupt mask.
-  *           @arg DMA_IT_DME: Direct mode error interrupt.
-  * @retval None
-  */
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
-((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
-
-/**
-  * @brief  Disable the specified DMA Stream interrupts.
-  * @param  __HANDLE__ DMA handle
-  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
-  *         This parameter can be any combination of the following values:
-  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
-  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
-  *            @arg DMA_IT_TE: Transfer error interrupt mask.
-  *            @arg DMA_IT_FE: FIFO error interrupt mask.
-  *            @arg DMA_IT_DME: Direct mode error interrupt.
-  * @retval None
-  */
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
-((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
-
-/**
-  * @brief  Check whether the specified DMA Stream interrupt is enabled or disabled.
-  * @param  __HANDLE__ DMA handle
-  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
-  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
-  *            @arg DMA_IT_TE: Transfer error interrupt mask.
-  *            @arg DMA_IT_FE: FIFO error interrupt mask.
-  *            @arg DMA_IT_DME: Direct mode error interrupt.
-  * @retval The state of DMA_IT.
-  */
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
-                                                        ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
-                                                        ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
-
-/**
-  * @brief  Writes the number of data units to be transferred on the DMA Stream.
-  * @param  __HANDLE__ DMA handle
-  * @param  __COUNTER__ Number of data units to be transferred (from 0 to 65535) 
-  *          Number of data items depends only on the Peripheral data format.
-  *            
-  * @note   If Peripheral data format is Bytes: number of data units is equal 
-  *         to total number of bytes to be transferred.
-  *           
-  * @note   If Peripheral data format is Half-Word: number of data units is  
-  *         equal to total number of bytes to be transferred / 2.
-  *           
-  * @note   If Peripheral data format is Word: number of data units is equal 
-  *         to total  number of bytes to be transferred / 4.
-  *      
-  * @retval The number of remaining data units in the current DMAy Streamx transfer.
-  */
-#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
-
-/**
-  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
-  * @param  __HANDLE__ DMA handle
-  *   
-  * @retval The number of remaining data units in the current DMA Stream transfer.
-  */
-#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
-
-
-/* Include DMA HAL Extension module */
-#include "stm32f4xx_hal_dma_ex.h"   
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Functions DMA Exported Functions
-  * @brief    DMA Exported functions 
-  * @{
-  */
-
-/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @brief   Initialization and de-initialization functions 
-  * @{
-  */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
-  * @brief   I/O operation functions  
-  * @{
-  */
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
-void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
-
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
-  * @brief    Peripheral State functions 
-  * @{
-  */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */ 
-/**
-  * @}
-  */ 
-/* Private Constants -------------------------------------------------------------*/
-/** @defgroup DMA_Private_Constants DMA Private Constants
-  * @brief    DMA private defines and constants 
-  * @{
-  */
-/**
-  * @}
-  */ 
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Macros DMA Private Macros
-  * @brief    DMA private macros 
-  * @{
-  */
-#if defined (DMA_SxCR_CHSEL_3)
-#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
-                                 ((CHANNEL) == DMA_CHANNEL_1) || \
-                                 ((CHANNEL) == DMA_CHANNEL_2) || \
-                                 ((CHANNEL) == DMA_CHANNEL_3) || \
-                                 ((CHANNEL) == DMA_CHANNEL_4) || \
-                                 ((CHANNEL) == DMA_CHANNEL_5) || \
-                                 ((CHANNEL) == DMA_CHANNEL_6) || \
-                                 ((CHANNEL) == DMA_CHANNEL_7) || \
-                                 ((CHANNEL) == DMA_CHANNEL_8) || \
-                                 ((CHANNEL) == DMA_CHANNEL_9) || \
-                                 ((CHANNEL) == DMA_CHANNEL_10)|| \
-                                 ((CHANNEL) == DMA_CHANNEL_11)|| \
-                                 ((CHANNEL) == DMA_CHANNEL_12)|| \
-                                 ((CHANNEL) == DMA_CHANNEL_13)|| \
-                                 ((CHANNEL) == DMA_CHANNEL_14)|| \
-                                 ((CHANNEL) == DMA_CHANNEL_15))
-#else
-#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
-                                 ((CHANNEL) == DMA_CHANNEL_1) || \
-                                 ((CHANNEL) == DMA_CHANNEL_2) || \
-                                 ((CHANNEL) == DMA_CHANNEL_3) || \
-                                 ((CHANNEL) == DMA_CHANNEL_4) || \
-                                 ((CHANNEL) == DMA_CHANNEL_5) || \
-                                 ((CHANNEL) == DMA_CHANNEL_6) || \
-                                 ((CHANNEL) == DMA_CHANNEL_7))
-#endif /* DMA_SxCR_CHSEL_3 */
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
-                                            ((STATE) == DMA_PINC_DISABLE))
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
-                                        ((STATE) == DMA_MINC_DISABLE))
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
-                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
-                                           ((SIZE) == DMA_PDATAALIGN_WORD))
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
-                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
-                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
-                           ((MODE) == DMA_CIRCULAR) || \
-                           ((MODE) == DMA_PFCTRL)) 
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
-                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
-                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
-                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 
-
-#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
-                                       ((STATE) == DMA_FIFOMODE_ENABLE))
-
-#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
-                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
-                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
-                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
-
-#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
-                                    ((BURST) == DMA_MBURST_INC4)   || \
-                                    ((BURST) == DMA_MBURST_INC8)   || \
-                                    ((BURST) == DMA_MBURST_INC16))
-
-#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
-                                        ((BURST) == DMA_PBURST_INC4)   || \
-                                        ((BURST) == DMA_PBURST_INC8)   || \
-                                        ((BURST) == DMA_PBURST_INC16))
-/**
-  * @}
-  */ 
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
-  * @brief    DMA private  functions 
-  * @{
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_DMA_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DMA_H
+#define __STM32F4xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Types DMA Exported Types
+  * @brief    DMA Exported Types 
+  * @{
+  */
+   
+/** 
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Channel;              /*!< Specifies the channel used for the specified stream. 
+                                      This parameter can be a value of @ref DMA_Channel_selection                    */
+
+  uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral, 
+                                      from memory to memory or from peripheral to memory.
+                                      This parameter can be a value of @ref DMA_Data_transfer_direction              */
+
+  uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                      This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */
+
+  uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.
+                                      This parameter can be a value of @ref DMA_Memory_incremented_mode              */
+
+  uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.
+                                      This parameter can be a value of @ref DMA_Peripheral_data_size                 */
+
+  uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.
+                                      This parameter can be a value of @ref DMA_Memory_data_size                     */
+
+  uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.
+                                      This parameter can be a value of @ref DMA_mode
+                                      @note The circular buffer mode cannot be used if the memory-to-memory
+                                            data transfer is configured on the selected Stream                        */
+
+  uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.
+                                      This parameter can be a value of @ref DMA_Priority_level                       */
+
+  uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+                                      This parameter can be a value of @ref DMA_FIFO_direct_mode
+                                      @note The Direct mode (FIFO mode disabled) cannot be used if the 
+                                            memory-to-memory data transfer is configured on the selected stream       */
+
+  uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.
+                                      This parameter can be a value of @ref DMA_FIFO_threshold_level                  */
+
+  uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers. 
+                                      It specifies the amount of data to be transferred in a single non interruptible
+                                      transaction.
+                                      This parameter can be a value of @ref DMA_Memory_burst 
+                                      @note The burst mode is possible only if the address Increment mode is enabled. */
+
+  uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
+                                      It specifies the amount of data to be transferred in a single non interruptible 
+                                      transaction. 
+                                      This parameter can be a value of @ref DMA_Peripheral_burst
+                                      @note The burst mode is possible only if the address Increment mode is enabled. */
+}DMA_InitTypeDef;
+
+
+/** 
+  * @brief  HAL DMA State structures definition
+  */
+typedef enum
+{
+  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */
+  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */
+  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */
+  HAL_DMA_STATE_TIMEOUT           = 0x03U,  /*!< DMA timeout state                   */
+  HAL_DMA_STATE_ERROR             = 0x04U,  /*!< DMA error state                     */
+  HAL_DMA_STATE_ABORT             = 0x05U,  /*!< DMA Abort state                     */
+}HAL_DMA_StateTypeDef;
+
+/** 
+  * @brief  HAL DMA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_DMA_FULL_TRANSFER           = 0x00U,  /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER           = 0x01U   /*!< Half Transfer     */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/** 
+  * @brief  HAL DMA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_DMA_XFER_CPLT_CB_ID         = 0x00U,  /*!< Full transfer     */
+  HAL_DMA_XFER_HALFCPLT_CB_ID     = 0x01U,  /*!< Half Transfer     */
+  HAL_DMA_XFER_M1CPLT_CB_ID       = 0x02U,  /*!< M1 Full Transfer  */
+  HAL_DMA_XFER_M1HALFCPLT_CB_ID   = 0x03U,  /*!< M1 Half Transfer  */
+  HAL_DMA_XFER_ERROR_CB_ID        = 0x04U,  /*!< Error             */
+  HAL_DMA_XFER_ABORT_CB_ID        = 0x05U,  /*!< Abort             */
+  HAL_DMA_XFER_ALL_CB_ID          = 0x06U   /*!< All               */
+}HAL_DMA_CallbackIDTypeDef;
+
+/** 
+  * @brief  DMA handle Structure definition
+  */
+typedef struct __DMA_HandleTypeDef
+{
+  DMA_Stream_TypeDef         *Instance;                                                        /*!< Register base address                  */
+
+  DMA_InitTypeDef            Init;                                                             /*!< DMA communication parameters           */ 
+
+  HAL_LockTypeDef            Lock;                                                             /*!< DMA locking object                     */  
+
+  __IO HAL_DMA_StateTypeDef  State;                                                            /*!< DMA transfer state                     */
+
+  void                       *Parent;                                                          /*!< Parent object state                    */ 
+
+  void                       (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);         /*!< DMA transfer complete callback         */
+
+  void                       (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA Half transfer complete callback    */
+
+  void                       (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer complete Memory1 callback */
+  
+  void                       (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback */
+  
+  void                       (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer error callback            */
+  
+  void                       (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer Abort callback            */  
+
+  __IO uint32_t              ErrorCode;                                                        /*!< DMA Error code                          */
+  
+  uint32_t                   StreamBaseAddress;                                                /*!< DMA Stream Base Address                */
+
+  uint32_t                   StreamIndex;                                                      /*!< DMA Stream Index                       */
+ 
+}DMA_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+  * @brief    DMA Exported constants 
+  * @{
+  */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+  * @brief    DMA Error Code 
+  * @{
+  */ 
+#define HAL_DMA_ERROR_NONE            0x00000000U    /*!< No error                               */
+#define HAL_DMA_ERROR_TE              0x00000001U    /*!< Transfer error                         */
+#define HAL_DMA_ERROR_FE              0x00000002U    /*!< FIFO error                             */
+#define HAL_DMA_ERROR_DME             0x00000004U    /*!< Direct Mode error                      */
+#define HAL_DMA_ERROR_TIMEOUT         0x00000020U    /*!< Timeout error                          */
+#define HAL_DMA_ERROR_PARAM           0x00000040U    /*!< Parameter error                        */
+#define HAL_DMA_ERROR_NO_XFER         0x00000080U    /*!< Abort requested with no Xfer ongoing   */
+#define HAL_DMA_ERROR_NOT_SUPPORTED   0x00000100U    /*!< Not supported mode                     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Channel_selection DMA Channel selection
+  * @brief    DMA channel selection 
+  * @{
+  */ 
+#define DMA_CHANNEL_0                 0x00000000U    /*!< DMA Channel 0 */
+#define DMA_CHANNEL_1                 0x02000000U    /*!< DMA Channel 1 */
+#define DMA_CHANNEL_2                 0x04000000U    /*!< DMA Channel 2 */
+#define DMA_CHANNEL_3                 0x06000000U    /*!< DMA Channel 3 */
+#define DMA_CHANNEL_4                 0x08000000U    /*!< DMA Channel 4 */
+#define DMA_CHANNEL_5                 0x0A000000U    /*!< DMA Channel 5 */
+#define DMA_CHANNEL_6                 0x0C000000U    /*!< DMA Channel 6 */
+#define DMA_CHANNEL_7                 0x0E000000U    /*!< DMA Channel 7 */
+#if defined (DMA_SxCR_CHSEL_3)
+#define DMA_CHANNEL_8                 0x10000000U    /*!< DMA Channel 8 */
+#define DMA_CHANNEL_9                 0x12000000U    /*!< DMA Channel 9 */
+#define DMA_CHANNEL_10                0x14000000U    /*!< DMA Channel 10 */
+#define DMA_CHANNEL_11                0x16000000U    /*!< DMA Channel 11 */
+#define DMA_CHANNEL_12                0x18000000U    /*!< DMA Channel 12 */
+#define DMA_CHANNEL_13                0x1A000000U    /*!< DMA Channel 13 */
+#define DMA_CHANNEL_14                0x1C000000U    /*!< DMA Channel 14 */
+#define DMA_CHANNEL_15                0x1E000000U    /*!< DMA Channel 15 */
+#endif /* DMA_SxCR_CHSEL_3 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+  * @brief    DMA data transfer direction 
+  * @{
+  */ 
+#define DMA_PERIPH_TO_MEMORY          0x00000000U                 /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH          ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY          ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+        
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+  * @brief    DMA peripheral incremented mode 
+  * @{
+  */ 
+#define DMA_PINC_ENABLE               ((uint32_t)DMA_SxCR_PINC)   /*!< Peripheral increment mode enable  */
+#define DMA_PINC_DISABLE              0x00000000U                 /*!< Peripheral increment mode disable */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+  * @brief    DMA memory incremented mode 
+  * @{
+  */ 
+#define DMA_MINC_ENABLE               ((uint32_t)DMA_SxCR_MINC)   /*!< Memory increment mode enable  */
+#define DMA_MINC_DISABLE              0x00000000U                 /*!< Memory increment mode disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+  * @brief    DMA peripheral data size 
+  * @{
+  */ 
+#define DMA_PDATAALIGN_BYTE           0x00000000U                  /*!< Peripheral data alignment: Byte     */
+#define DMA_PDATAALIGN_HALFWORD       ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
+#define DMA_PDATAALIGN_WORD           ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word     */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+  * @brief    DMA memory data size 
+  * @{ 
+  */
+#define DMA_MDATAALIGN_BYTE           0x00000000U                  /*!< Memory data alignment: Byte     */
+#define DMA_MDATAALIGN_HALFWORD       ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD           ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_mode DMA mode
+  * @brief    DMA mode 
+  * @{
+  */ 
+#define DMA_NORMAL                    0x00000000U                  /*!< Normal mode                  */
+#define DMA_CIRCULAR                  ((uint32_t)DMA_SxCR_CIRC)    /*!< Circular mode                */
+#define DMA_PFCTRL                    ((uint32_t)DMA_SxCR_PFCTRL)  /*!< Peripheral flow control mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+  * @brief    DMA priority levels 
+  * @{
+  */
+#define DMA_PRIORITY_LOW              0x00000000U                 /*!< Priority level: Low       */
+#define DMA_PRIORITY_MEDIUM           ((uint32_t)DMA_SxCR_PL_0)   /*!< Priority level: Medium    */
+#define DMA_PRIORITY_HIGH             ((uint32_t)DMA_SxCR_PL_1)   /*!< Priority level: High      */
+#define DMA_PRIORITY_VERY_HIGH        ((uint32_t)DMA_SxCR_PL)     /*!< Priority level: Very High */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
+  * @brief    DMA FIFO direct mode
+  * @{
+  */
+#define DMA_FIFOMODE_DISABLE          0x00000000U                 /*!< FIFO mode disable */
+#define DMA_FIFOMODE_ENABLE           ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable  */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
+  * @brief    DMA FIFO level 
+  * @{
+  */
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL       0x00000000U                  /*!< FIFO threshold 1 quart full configuration  */
+#define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */
+#define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Memory_burst DMA Memory burst
+  * @brief    DMA memory burst 
+  * @{
+  */ 
+#define DMA_MBURST_SINGLE             0x00000000U
+#define DMA_MBURST_INC4               ((uint32_t)DMA_SxCR_MBURST_0)  
+#define DMA_MBURST_INC8               ((uint32_t)DMA_SxCR_MBURST_1)  
+#define DMA_MBURST_INC16              ((uint32_t)DMA_SxCR_MBURST)  
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
+  * @brief    DMA peripheral burst 
+  * @{
+  */ 
+#define DMA_PBURST_SINGLE             0x00000000U
+#define DMA_PBURST_INC4               ((uint32_t)DMA_SxCR_PBURST_0)
+#define DMA_PBURST_INC8               ((uint32_t)DMA_SxCR_PBURST_1)
+#define DMA_PBURST_INC16              ((uint32_t)DMA_SxCR_PBURST)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+  * @brief    DMA interrupts definition 
+  * @{
+  */
+#define DMA_IT_TC                     ((uint32_t)DMA_SxCR_TCIE)
+#define DMA_IT_HT                     ((uint32_t)DMA_SxCR_HTIE)
+#define DMA_IT_TE                     ((uint32_t)DMA_SxCR_TEIE)
+#define DMA_IT_DME                    ((uint32_t)DMA_SxCR_DMEIE)
+#define DMA_IT_FE                     0x00000080U
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+  * @brief    DMA flag definitions 
+  * @{
+  */ 
+#define DMA_FLAG_FEIF0_4              0x00000001U
+#define DMA_FLAG_DMEIF0_4             0x00000004U
+#define DMA_FLAG_TEIF0_4              0x00000008U
+#define DMA_FLAG_HTIF0_4              0x00000010U
+#define DMA_FLAG_TCIF0_4              0x00000020U
+#define DMA_FLAG_FEIF1_5              0x00000040U
+#define DMA_FLAG_DMEIF1_5             0x00000100U
+#define DMA_FLAG_TEIF1_5              0x00000200U
+#define DMA_FLAG_HTIF1_5              0x00000400U
+#define DMA_FLAG_TCIF1_5              0x00000800U
+#define DMA_FLAG_FEIF2_6              0x00010000U
+#define DMA_FLAG_DMEIF2_6             0x00040000U
+#define DMA_FLAG_TEIF2_6              0x00080000U
+#define DMA_FLAG_HTIF2_6              0x00100000U
+#define DMA_FLAG_TCIF2_6              0x00200000U
+#define DMA_FLAG_FEIF3_7              0x00400000U
+#define DMA_FLAG_DMEIF3_7             0x01000000U
+#define DMA_FLAG_TEIF3_7              0x02000000U
+#define DMA_FLAG_HTIF3_7              0x04000000U
+#define DMA_FLAG_TCIF3_7              0x08000000U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+ 
+/* Exported macro ------------------------------------------------------------*/
+
+/** @brief Reset DMA handle state
+  * @param  __HANDLE__ specifies the DMA handle.
+  * @retval None
+  */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+  * @brief  Return the current DMA Stream FIFO filled level.
+  * @param  __HANDLE__ DMA handle
+  * @retval The FIFO filling state.
+  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 
+  *                                              and not empty.
+  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
+  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
+  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
+  *           - DMA_FIFOStatus_Empty: when FIFO is empty
+  *           - DMA_FIFOStatus_Full: when FIFO is full
+  */
+#define __HAL_DMA_GET_FS(__HANDLE__)      (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
+
+/**
+  * @brief  Enable the specified DMA Stream.
+  * @param  __HANDLE__ DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  DMA_SxCR_EN)
+
+/**
+  * @brief  Disable the specified DMA Stream.
+  * @param  __HANDLE__ DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE(__HANDLE__)     ((__HANDLE__)->Instance->CR &=  ~DMA_SxCR_EN)
+
+/* Interrupt & Flag management */
+
+/**
+  * @brief  Return the current DMA Stream transfer complete flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified transfer complete flag index.
+  */
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+   DMA_FLAG_TCIF3_7)
+
+/**
+  * @brief  Return the current DMA Stream half transfer complete flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified half transfer complete flag index.
+  */      
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+   DMA_FLAG_HTIF3_7)
+
+/**
+  * @brief  Return the current DMA Stream transfer error flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+   DMA_FLAG_TEIF3_7)
+
+/**
+  * @brief  Return the current DMA Stream FIFO error flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified FIFO error flag index.
+  */
+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
+   DMA_FLAG_FEIF3_7)
+
+/**
+  * @brief  Return the current DMA Stream direct mode error flag.
+  * @param  __HANDLE__ DMA handle
+  * @retval The specified direct mode error flag index.
+  */
+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
+   DMA_FLAG_DMEIF3_7)
+
+/**
+  * @brief  Get the DMA Stream pending flags.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+
+/**
+  * @brief  Clear the DMA Stream pending flags.
+  * @param  __HANDLE__ DMA handle
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.
+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.
+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.
+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.
+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.   
+  * @retval None
+  */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
+
+/**
+  * @brief  Enable the specified DMA Stream interrupts.
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
+  *        This parameter can be any combination of the following values:
+  *           @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *           @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *           @arg DMA_IT_TE: Transfer error interrupt mask.
+  *           @arg DMA_IT_FE: FIFO error interrupt mask.
+  *           @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \
+((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
+
+/**
+  * @brief  Disable the specified DMA Stream interrupts.
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
+  *         This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *            @arg DMA_IT_TE: Transfer error interrupt mask.
+  *            @arg DMA_IT_FE: FIFO error interrupt mask.
+  *            @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
+((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
+
+/**
+  * @brief  Check whether the specified DMA Stream interrupt is enabled or disabled.
+  * @param  __HANDLE__ DMA handle
+  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.
+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.
+  *            @arg DMA_IT_TE: Transfer error interrupt mask.
+  *            @arg DMA_IT_FE: FIFO error interrupt mask.
+  *            @arg DMA_IT_DME: Direct mode error interrupt.
+  * @retval The state of DMA_IT.
+  */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \
+                                                        ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
+                                                        ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
+
+/**
+  * @brief  Writes the number of data units to be transferred on the DMA Stream.
+  * @param  __HANDLE__ DMA handle
+  * @param  __COUNTER__ Number of data units to be transferred (from 0 to 65535) 
+  *          Number of data items depends only on the Peripheral data format.
+  *            
+  * @note   If Peripheral data format is Bytes: number of data units is equal 
+  *         to total number of bytes to be transferred.
+  *           
+  * @note   If Peripheral data format is Half-Word: number of data units is  
+  *         equal to total number of bytes to be transferred / 2.
+  *           
+  * @note   If Peripheral data format is Word: number of data units is equal 
+  *         to total  number of bytes to be transferred / 4.
+  *      
+  * @retval The number of remaining data units in the current DMAy Streamx transfer.
+  */
+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
+
+/**
+  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
+  * @param  __HANDLE__ DMA handle
+  *   
+  * @retval The number of remaining data units in the current DMA Stream transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
+
+
+/* Include DMA HAL Extension module */
+#include "stm32f4xx_hal_dma_ex.h"   
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+  * @brief    DMA Exported functions 
+  * @{
+  */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief   Initialization and de-initialization functions 
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
+  * @brief   I/O operation functions  
+  * @{
+  */
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
+void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
+
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
+  * @brief    Peripheral State functions 
+  * @{
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */ 
+/**
+  * @}
+  */ 
+/* Private Constants -------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+  * @brief    DMA private defines and constants 
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+  * @brief    DMA private macros 
+  * @{
+  */
+#if defined (DMA_SxCR_CHSEL_3)
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
+                                 ((CHANNEL) == DMA_CHANNEL_1) || \
+                                 ((CHANNEL) == DMA_CHANNEL_2) || \
+                                 ((CHANNEL) == DMA_CHANNEL_3) || \
+                                 ((CHANNEL) == DMA_CHANNEL_4) || \
+                                 ((CHANNEL) == DMA_CHANNEL_5) || \
+                                 ((CHANNEL) == DMA_CHANNEL_6) || \
+                                 ((CHANNEL) == DMA_CHANNEL_7) || \
+                                 ((CHANNEL) == DMA_CHANNEL_8) || \
+                                 ((CHANNEL) == DMA_CHANNEL_9) || \
+                                 ((CHANNEL) == DMA_CHANNEL_10)|| \
+                                 ((CHANNEL) == DMA_CHANNEL_11)|| \
+                                 ((CHANNEL) == DMA_CHANNEL_12)|| \
+                                 ((CHANNEL) == DMA_CHANNEL_13)|| \
+                                 ((CHANNEL) == DMA_CHANNEL_14)|| \
+                                 ((CHANNEL) == DMA_CHANNEL_15))
+#else
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
+                                 ((CHANNEL) == DMA_CHANNEL_1) || \
+                                 ((CHANNEL) == DMA_CHANNEL_2) || \
+                                 ((CHANNEL) == DMA_CHANNEL_3) || \
+                                 ((CHANNEL) == DMA_CHANNEL_4) || \
+                                 ((CHANNEL) == DMA_CHANNEL_5) || \
+                                 ((CHANNEL) == DMA_CHANNEL_6) || \
+                                 ((CHANNEL) == DMA_CHANNEL_7))
+#endif /* DMA_SxCR_CHSEL_3 */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+                                            ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
+                                        ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+                                           ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
+                           ((MODE) == DMA_CIRCULAR) || \
+                           ((MODE) == DMA_PFCTRL)) 
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
+                                       ((STATE) == DMA_FIFOMODE_ENABLE))
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
+                                    ((BURST) == DMA_MBURST_INC4)   || \
+                                    ((BURST) == DMA_MBURST_INC8)   || \
+                                    ((BURST) == DMA_MBURST_INC16))
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
+                                        ((BURST) == DMA_PBURST_INC4)   || \
+                                        ((BURST) == DMA_PBURST_INC8)   || \
+                                        ((BURST) == DMA_PBURST_INC16))
+/**
+  * @}
+  */ 
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+  * @brief    DMA private  functions 
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_DMA_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h
index 9858c74..266c1fa 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h
@@ -1,102 +1,102 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_dma_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of DMA HAL extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_DMA_EX_H
-#define __STM32F4xx_HAL_DMA_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DMAEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
-  * @brief DMAEx Exported types
-  * @{
-  */
-   
-/** 
-  * @brief  HAL DMA Memory definition  
-  */ 
-typedef enum
-{
-  MEMORY0      = 0x00U,    /*!< Memory 0     */
-  MEMORY1      = 0x01U     /*!< Memory 1     */
-}HAL_DMA_MemoryTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
-  * @brief   DMAEx Exported functions
-  * @{
-  */
-
-/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
-  * @brief   Extended features functions
-  * @{
-  */
-
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
-
-/**
-  * @}
-  */
-/**
-  * @}
-  */
-         
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
-  * @brief DMAEx Private functions
-  * @{
-  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_HAL_DMA_EX_H*/
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dma_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA HAL extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_DMA_EX_H
+#define __STM32F4xx_HAL_DMA_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMAEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
+  * @brief DMAEx Exported types
+  * @{
+  */
+   
+/** 
+  * @brief  HAL DMA Memory definition  
+  */ 
+typedef enum
+{
+  MEMORY0      = 0x00U,    /*!< Memory 0     */
+  MEMORY1      = 0x01U     /*!< Memory 1     */
+}HAL_DMA_MemoryTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
+  * @brief   DMAEx Exported functions
+  * @{
+  */
+
+/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions
+  * @brief   Extended features functions
+  * @{
+  */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+         
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
+  * @brief DMAEx Private functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_HAL_DMA_EX_H*/
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h
index b18a228..a7af121 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h
@@ -1,366 +1,366 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_exti.h
-  * @author  MCD Application Team
-  * @brief   Header file of EXTI HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32f4xx_HAL_EXTI_H
-#define STM32f4xx_HAL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup EXTI EXTI
-  * @brief EXTI HAL module driver
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup EXTI_Exported_Types EXTI Exported Types
-  * @{
-  */
-typedef enum
-{
-  HAL_EXTI_COMMON_CB_ID          = 0x00U
-} EXTI_CallbackIDTypeDef;
-
-/**
-  * @brief  EXTI Handle structure definition
-  */
-typedef struct
-{
-  uint32_t Line;                    /*!<  Exti line number */
-  void (* PendingCallback)(void);   /*!<  Exti pending callback */
-} EXTI_HandleTypeDef;
-
-/**
-  * @brief  EXTI Configuration structure definition
-  */
-typedef struct
-{
-  uint32_t Line;      /*!< The Exti line to be configured. This parameter
-                           can be a value of @ref EXTI_Line */
-  uint32_t Mode;      /*!< The Exit Mode to be configured for a core.
-                           This parameter can be a combination of @ref EXTI_Mode */
-  uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter
-                           can be a value of @ref EXTI_Trigger */
-  uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.
-                           This parameter is only possible for line 0 to 15. It
-                           can be a value of @ref EXTI_GPIOSel */
-} EXTI_ConfigTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
-  * @{
-  */
-
-/** @defgroup EXTI_Line  EXTI Line
-  * @{
-  */
-#define EXTI_LINE_0                        (EXTI_GPIO       | 0x00u)    /*!< External interrupt line 0 */
-#define EXTI_LINE_1                        (EXTI_GPIO       | 0x01u)    /*!< External interrupt line 1 */
-#define EXTI_LINE_2                        (EXTI_GPIO       | 0x02u)    /*!< External interrupt line 2 */
-#define EXTI_LINE_3                        (EXTI_GPIO       | 0x03u)    /*!< External interrupt line 3 */
-#define EXTI_LINE_4                        (EXTI_GPIO       | 0x04u)    /*!< External interrupt line 4 */
-#define EXTI_LINE_5                        (EXTI_GPIO       | 0x05u)    /*!< External interrupt line 5 */
-#define EXTI_LINE_6                        (EXTI_GPIO       | 0x06u)    /*!< External interrupt line 6 */
-#define EXTI_LINE_7                        (EXTI_GPIO       | 0x07u)    /*!< External interrupt line 7 */
-#define EXTI_LINE_8                        (EXTI_GPIO       | 0x08u)    /*!< External interrupt line 8 */
-#define EXTI_LINE_9                        (EXTI_GPIO       | 0x09u)    /*!< External interrupt line 9 */
-#define EXTI_LINE_10                       (EXTI_GPIO       | 0x0Au)    /*!< External interrupt line 10 */
-#define EXTI_LINE_11                       (EXTI_GPIO       | 0x0Bu)    /*!< External interrupt line 11 */
-#define EXTI_LINE_12                       (EXTI_GPIO       | 0x0Cu)    /*!< External interrupt line 12 */
-#define EXTI_LINE_13                       (EXTI_GPIO       | 0x0Du)    /*!< External interrupt line 13 */
-#define EXTI_LINE_14                       (EXTI_GPIO       | 0x0Eu)    /*!< External interrupt line 14 */
-#define EXTI_LINE_15                       (EXTI_GPIO       | 0x0Fu)    /*!< External interrupt line 15 */
-#define EXTI_LINE_16                       (EXTI_CONFIG     | 0x10u)    /*!< External interrupt line 16 Connected to the PVD Output */
-#define EXTI_LINE_17                       (EXTI_CONFIG     | 0x11u)    /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#if defined(EXTI_IMR_IM18)
-#define EXTI_LINE_18                       (EXTI_CONFIG     | 0x12u)    /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
-#else
-#define EXTI_LINE_18                       (EXTI_RESERVED   | 0x12u)    /*!< No interrupt supported in this line */
-#endif /* EXTI_IMR_IM18 */
-#if defined(EXTI_IMR_IM19)
-#define EXTI_LINE_19                       (EXTI_CONFIG     | 0x13u)    /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
-#else
-#define EXTI_LINE_19                       (EXTI_RESERVED   | 0x13u)    /*!< No interrupt supported in this line */
-#endif /* EXTI_IMR_IM19 */
-#if defined(EXTI_IMR_IM20)
-#define EXTI_LINE_20                       (EXTI_CONFIG     | 0x14u)    /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event  */
-#else
-#define EXTI_LINE_20                       (EXTI_RESERVED   | 0x14u)    /*!< No interrupt supported in this line */
-#endif /* EXTI_IMR_IM20 */
-#define EXTI_LINE_21                       (EXTI_CONFIG     | 0x15u)    /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
-#define EXTI_LINE_22                       (EXTI_CONFIG     | 0x16u)    /*!< External interrupt line 22 Connected to the RTC Wakeup event */
-#if defined(EXTI_IMR_IM23)
-#define EXTI_LINE_23                       (EXTI_CONFIG     | 0x17u)    /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */
-#endif /* EXTI_IMR_IM23 */
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Mode  EXTI Mode
-  * @{
-  */
-#define EXTI_MODE_NONE                      0x00000000u
-#define EXTI_MODE_INTERRUPT                 0x00000001u
-#define EXTI_MODE_EVENT                     0x00000002u
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Trigger  EXTI Trigger
-  * @{
-  */
-
-#define EXTI_TRIGGER_NONE                   0x00000000u
-#define EXTI_TRIGGER_RISING                 0x00000001u
-#define EXTI_TRIGGER_FALLING                0x00000002u
-#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
-  * @brief
-  * @{
-  */
-#define EXTI_GPIOA                          0x00000000u
-#define EXTI_GPIOB                          0x00000001u
-#define EXTI_GPIOC                          0x00000002u
-#if defined (GPIOD)
-#define EXTI_GPIOD                          0x00000003u
-#endif /* GPIOD */
-#if defined (GPIOE)
-#define EXTI_GPIOE                          0x00000004u
-#endif /* GPIOE */
-#if defined (GPIOF)
-#define EXTI_GPIOF                          0x00000005u
-#endif /* GPIOF */
-#if defined (GPIOG)
-#define EXTI_GPIOG                          0x00000006u
-#endif /* GPIOG */
-#if defined (GPIOH)
-#define EXTI_GPIOH                          0x00000007u
-#endif /* GPIOH */
-#if defined (GPIOI)
-#define EXTI_GPIOI                          0x00000008u
-#endif /* GPIOI */
-#if defined (GPIOJ)
-#define EXTI_GPIOJ                          0x00000009u
-#endif /* GPIOJ */
-#if defined (GPIOK)
-#define EXTI_GPIOK                          0x0000000Au
-#endif /* GPIOK */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants --------------------------------------------------------*/
-/** @defgroup EXTI_Private_Constants EXTI Private Constants
-  * @{
-  */
-/**
-  * @brief  EXTI Line property definition
-  */
-#define EXTI_PROPERTY_SHIFT                  24u
-#define EXTI_CONFIG                         (0x02uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_GPIO                           ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
-#define EXTI_RESERVED                       (0x08uL << EXTI_PROPERTY_SHIFT)
-#define EXTI_PROPERTY_MASK                  (EXTI_CONFIG | EXTI_GPIO)
-
-/**
-  * @brief  EXTI bit usage
-  */
-#define EXTI_PIN_MASK                       0x0000001Fu
-
-/**
-  * @brief  EXTI Mask for interrupt & event mode
-  */
-#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
-
-/**
-  * @brief  EXTI Mask for trigger possibilities
-  */
-#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
-
-/**
-  * @brief  EXTI Line number
-  */
-#if defined(EXTI_IMR_IM23)
-#define EXTI_LINE_NB                        24UL
-#else
-#define EXTI_LINE_NB                        23UL
-#endif /* EXTI_IMR_IM23 */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup EXTI_Private_Macros EXTI Private Macros
-  * @{
-  */
-#define IS_EXTI_LINE(__EXTI_LINE__)          ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
-                                             ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)              || \
-                                              (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))               && \
-                                              (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
-
-#define IS_EXTI_MODE(__EXTI_LINE__)          ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
-                                              (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
-
-#define IS_EXTI_TRIGGER(__EXTI_LINE__)       (((__EXTI_LINE__)  & ~EXTI_TRIGGER_MASK) == 0x00u)
-
-#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__)  ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
-
-#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__)   (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
-
-#if !defined (GPIOD)
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
-                                         ((__PORT__) == EXTI_GPIOB) || \
-                                         ((__PORT__) == EXTI_GPIOC) || \
-                                         ((__PORT__) == EXTI_GPIOH))
-#elif !defined (GPIOE)
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
-                                         ((__PORT__) == EXTI_GPIOB) || \
-                                         ((__PORT__) == EXTI_GPIOC) || \
-                                         ((__PORT__) == EXTI_GPIOD) || \
-                                         ((__PORT__) == EXTI_GPIOH))
-#elif !defined (GPIOF)
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
-                                         ((__PORT__) == EXTI_GPIOB) || \
-                                         ((__PORT__) == EXTI_GPIOC) || \
-                                         ((__PORT__) == EXTI_GPIOD) || \
-                                         ((__PORT__) == EXTI_GPIOE) || \
-                                         ((__PORT__) == EXTI_GPIOH))
-#elif !defined (GPIOI)
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
-                                         ((__PORT__) == EXTI_GPIOB) || \
-                                         ((__PORT__) == EXTI_GPIOC) || \
-                                         ((__PORT__) == EXTI_GPIOD) || \
-                                         ((__PORT__) == EXTI_GPIOE) || \
-                                         ((__PORT__) == EXTI_GPIOF) || \
-                                         ((__PORT__) == EXTI_GPIOG) || \
-                                         ((__PORT__) == EXTI_GPIOH))
-#elif !defined (GPIOJ)
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
-                                         ((__PORT__) == EXTI_GPIOB) || \
-                                         ((__PORT__) == EXTI_GPIOC) || \
-                                         ((__PORT__) == EXTI_GPIOD) || \
-                                         ((__PORT__) == EXTI_GPIOE) || \
-                                         ((__PORT__) == EXTI_GPIOF) || \
-                                         ((__PORT__) == EXTI_GPIOG) || \
-                                         ((__PORT__) == EXTI_GPIOH) || \
-                                         ((__PORT__) == EXTI_GPIOI))
-#else
-#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
-                                         ((__PORT__) == EXTI_GPIOB) || \
-                                         ((__PORT__) == EXTI_GPIOC) || \
-                                         ((__PORT__) == EXTI_GPIOD) || \
-                                         ((__PORT__) == EXTI_GPIOE) || \
-                                         ((__PORT__) == EXTI_GPIOF) || \
-                                         ((__PORT__) == EXTI_GPIOG) || \
-                                         ((__PORT__) == EXTI_GPIOH) || \
-                                         ((__PORT__) == EXTI_GPIOI) || \
-                                         ((__PORT__) == EXTI_GPIOJ) || \
-                                         ((__PORT__) == EXTI_GPIOK))
-#endif /* GPIOD */
-
-#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16U)
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
-  * @brief    EXTI Exported Functions
-  * @{
-  */
-
-/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
-  * @brief    Configuration functions
-  * @{
-  */
-/* Configuration functions ****************************************************/
-HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
-HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
-HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
-HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
-  * @brief    IO operation functions
-  * @{
-  */
-/* IO operation functions *****************************************************/
-void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
-uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
-void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
-void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32f4xx_HAL_EXTI_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32f4xx_HAL_EXTI_H
+#define STM32f4xx_HAL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup EXTI EXTI
+  * @brief EXTI HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Types EXTI Exported Types
+  * @{
+  */
+typedef enum
+{
+  HAL_EXTI_COMMON_CB_ID          = 0x00U
+} EXTI_CallbackIDTypeDef;
+
+/**
+  * @brief  EXTI Handle structure definition
+  */
+typedef struct
+{
+  uint32_t Line;                    /*!<  Exti line number */
+  void (* PendingCallback)(void);   /*!<  Exti pending callback */
+} EXTI_HandleTypeDef;
+
+/**
+  * @brief  EXTI Configuration structure definition
+  */
+typedef struct
+{
+  uint32_t Line;      /*!< The Exti line to be configured. This parameter
+                           can be a value of @ref EXTI_Line */
+  uint32_t Mode;      /*!< The Exit Mode to be configured for a core.
+                           This parameter can be a combination of @ref EXTI_Mode */
+  uint32_t Trigger;   /*!< The Exti Trigger to be configured. This parameter
+                           can be a value of @ref EXTI_Trigger */
+  uint32_t GPIOSel;   /*!< The Exti GPIO multiplexer selection to be configured.
+                           This parameter is only possible for line 0 to 15. It
+                           can be a value of @ref EXTI_GPIOSel */
+} EXTI_ConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Line  EXTI Line
+  * @{
+  */
+#define EXTI_LINE_0                        (EXTI_GPIO       | 0x00u)    /*!< External interrupt line 0 */
+#define EXTI_LINE_1                        (EXTI_GPIO       | 0x01u)    /*!< External interrupt line 1 */
+#define EXTI_LINE_2                        (EXTI_GPIO       | 0x02u)    /*!< External interrupt line 2 */
+#define EXTI_LINE_3                        (EXTI_GPIO       | 0x03u)    /*!< External interrupt line 3 */
+#define EXTI_LINE_4                        (EXTI_GPIO       | 0x04u)    /*!< External interrupt line 4 */
+#define EXTI_LINE_5                        (EXTI_GPIO       | 0x05u)    /*!< External interrupt line 5 */
+#define EXTI_LINE_6                        (EXTI_GPIO       | 0x06u)    /*!< External interrupt line 6 */
+#define EXTI_LINE_7                        (EXTI_GPIO       | 0x07u)    /*!< External interrupt line 7 */
+#define EXTI_LINE_8                        (EXTI_GPIO       | 0x08u)    /*!< External interrupt line 8 */
+#define EXTI_LINE_9                        (EXTI_GPIO       | 0x09u)    /*!< External interrupt line 9 */
+#define EXTI_LINE_10                       (EXTI_GPIO       | 0x0Au)    /*!< External interrupt line 10 */
+#define EXTI_LINE_11                       (EXTI_GPIO       | 0x0Bu)    /*!< External interrupt line 11 */
+#define EXTI_LINE_12                       (EXTI_GPIO       | 0x0Cu)    /*!< External interrupt line 12 */
+#define EXTI_LINE_13                       (EXTI_GPIO       | 0x0Du)    /*!< External interrupt line 13 */
+#define EXTI_LINE_14                       (EXTI_GPIO       | 0x0Eu)    /*!< External interrupt line 14 */
+#define EXTI_LINE_15                       (EXTI_GPIO       | 0x0Fu)    /*!< External interrupt line 15 */
+#define EXTI_LINE_16                       (EXTI_CONFIG     | 0x10u)    /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_LINE_17                       (EXTI_CONFIG     | 0x11u)    /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#if defined(EXTI_IMR_IM18)
+#define EXTI_LINE_18                       (EXTI_CONFIG     | 0x12u)    /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
+#else
+#define EXTI_LINE_18                       (EXTI_RESERVED   | 0x12u)    /*!< No interrupt supported in this line */
+#endif /* EXTI_IMR_IM18 */
+#if defined(EXTI_IMR_IM19)
+#define EXTI_LINE_19                       (EXTI_CONFIG     | 0x13u)    /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+#else
+#define EXTI_LINE_19                       (EXTI_RESERVED   | 0x13u)    /*!< No interrupt supported in this line */
+#endif /* EXTI_IMR_IM19 */
+#if defined(EXTI_IMR_IM20)
+#define EXTI_LINE_20                       (EXTI_CONFIG     | 0x14u)    /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event  */
+#else
+#define EXTI_LINE_20                       (EXTI_RESERVED   | 0x14u)    /*!< No interrupt supported in this line */
+#endif /* EXTI_IMR_IM20 */
+#define EXTI_LINE_21                       (EXTI_CONFIG     | 0x15u)    /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
+#define EXTI_LINE_22                       (EXTI_CONFIG     | 0x16u)    /*!< External interrupt line 22 Connected to the RTC Wakeup event */
+#if defined(EXTI_IMR_IM23)
+#define EXTI_LINE_23                       (EXTI_CONFIG     | 0x17u)    /*!< External interrupt line 23 Connected to the LPTIM1 asynchronous event */
+#endif /* EXTI_IMR_IM23 */
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Mode  EXTI Mode
+  * @{
+  */
+#define EXTI_MODE_NONE                      0x00000000u
+#define EXTI_MODE_INTERRUPT                 0x00000001u
+#define EXTI_MODE_EVENT                     0x00000002u
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Trigger  EXTI Trigger
+  * @{
+  */
+
+#define EXTI_TRIGGER_NONE                   0x00000000u
+#define EXTI_TRIGGER_RISING                 0x00000001u
+#define EXTI_TRIGGER_FALLING                0x00000002u
+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
+  * @brief
+  * @{
+  */
+#define EXTI_GPIOA                          0x00000000u
+#define EXTI_GPIOB                          0x00000001u
+#define EXTI_GPIOC                          0x00000002u
+#if defined (GPIOD)
+#define EXTI_GPIOD                          0x00000003u
+#endif /* GPIOD */
+#if defined (GPIOE)
+#define EXTI_GPIOE                          0x00000004u
+#endif /* GPIOE */
+#if defined (GPIOF)
+#define EXTI_GPIOF                          0x00000005u
+#endif /* GPIOF */
+#if defined (GPIOG)
+#define EXTI_GPIOG                          0x00000006u
+#endif /* GPIOG */
+#if defined (GPIOH)
+#define EXTI_GPIOH                          0x00000007u
+#endif /* GPIOH */
+#if defined (GPIOI)
+#define EXTI_GPIOI                          0x00000008u
+#endif /* GPIOI */
+#if defined (GPIOJ)
+#define EXTI_GPIOJ                          0x00000009u
+#endif /* GPIOJ */
+#if defined (GPIOK)
+#define EXTI_GPIOK                          0x0000000Au
+#endif /* GPIOK */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+/**
+  * @brief  EXTI Line property definition
+  */
+#define EXTI_PROPERTY_SHIFT                  24u
+#define EXTI_CONFIG                         (0x02uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_GPIO                           ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
+#define EXTI_RESERVED                       (0x08uL << EXTI_PROPERTY_SHIFT)
+#define EXTI_PROPERTY_MASK                  (EXTI_CONFIG | EXTI_GPIO)
+
+/**
+  * @brief  EXTI bit usage
+  */
+#define EXTI_PIN_MASK                       0x0000001Fu
+
+/**
+  * @brief  EXTI Mask for interrupt & event mode
+  */
+#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
+
+/**
+  * @brief  EXTI Mask for trigger possibilities
+  */
+#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+
+/**
+  * @brief  EXTI Line number
+  */
+#if defined(EXTI_IMR_IM23)
+#define EXTI_LINE_NB                        24UL
+#else
+#define EXTI_LINE_NB                        23UL
+#endif /* EXTI_IMR_IM23 */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup EXTI_Private_Macros EXTI Private Macros
+  * @{
+  */
+#define IS_EXTI_LINE(__EXTI_LINE__)          ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_PIN_MASK)) == 0x00u) && \
+                                             ((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)              || \
+                                              (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))               && \
+                                              (((__EXTI_LINE__) & EXTI_PIN_MASK) < EXTI_LINE_NB))
+
+#define IS_EXTI_MODE(__EXTI_LINE__)          ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00u) && \
+                                              (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00u))
+
+#define IS_EXTI_TRIGGER(__EXTI_LINE__)       (((__EXTI_LINE__)  & ~EXTI_TRIGGER_MASK) == 0x00u)
+
+#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__)  ((__EXTI_LINE__) == EXTI_TRIGGER_RISING_FALLING)
+
+#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__)   (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00u)
+
+#if !defined (GPIOD)
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOE)
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOF)
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOI)
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOF) || \
+                                         ((__PORT__) == EXTI_GPIOG) || \
+                                         ((__PORT__) == EXTI_GPIOH))
+#elif !defined (GPIOJ)
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOF) || \
+                                         ((__PORT__) == EXTI_GPIOG) || \
+                                         ((__PORT__) == EXTI_GPIOH) || \
+                                         ((__PORT__) == EXTI_GPIOI))
+#else
+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \
+                                         ((__PORT__) == EXTI_GPIOB) || \
+                                         ((__PORT__) == EXTI_GPIOC) || \
+                                         ((__PORT__) == EXTI_GPIOD) || \
+                                         ((__PORT__) == EXTI_GPIOE) || \
+                                         ((__PORT__) == EXTI_GPIOF) || \
+                                         ((__PORT__) == EXTI_GPIOG) || \
+                                         ((__PORT__) == EXTI_GPIOH) || \
+                                         ((__PORT__) == EXTI_GPIOI) || \
+                                         ((__PORT__) == EXTI_GPIOJ) || \
+                                         ((__PORT__) == EXTI_GPIOK))
+#endif /* GPIOD */
+
+#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16U)
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
+  * @brief    EXTI Exported Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
+  * @brief    Configuration functions
+  * @{
+  */
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
+  * @brief    IO operation functions
+  * @{
+  */
+/* IO operation functions *****************************************************/
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32f4xx_HAL_EXTI_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h
index 26d789e..a047e82 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h
@@ -1,425 +1,425 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_flash.h
-  * @author  MCD Application Team
-  * @brief   Header file of FLASH HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_FLASH_H
-#define __STM32F4xx_HAL_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Types FLASH Exported Types
-  * @{
-  */
- 
-/**
-  * @brief  FLASH Procedure structure definition
-  */
-typedef enum 
-{
-  FLASH_PROC_NONE = 0U, 
-  FLASH_PROC_SECTERASE,
-  FLASH_PROC_MASSERASE,
-  FLASH_PROC_PROGRAM
-} FLASH_ProcedureTypeDef;
-
-/** 
-  * @brief  FLASH handle Structure definition  
-  */
-typedef struct
-{
-  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /*Internal variable to indicate which procedure is ongoing or not in IT context*/
-  
-  __IO uint32_t               NbSectorsToErase;   /*Internal variable to save the remaining sectors to erase in IT context*/
-  
-  __IO uint8_t                VoltageForErase;    /*Internal variable to provide voltage range selected by user in IT context*/
-  
-  __IO uint32_t               Sector;             /*Internal variable to define the current sector which is erasing*/
-  
-  __IO uint32_t               Bank;               /*Internal variable to save current bank selected during mass erase*/
-  
-  __IO uint32_t               Address;            /*Internal variable to save address selected for program*/
-  
-  HAL_LockTypeDef             Lock;               /* FLASH locking object                */
-
-  __IO uint32_t               ErrorCode;          /* FLASH error code                    */
-
-}FLASH_ProcessTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
-  * @{
-  */  
-/** @defgroup FLASH_Error_Code FLASH Error Code
-  * @brief    FLASH Error Code 
-  * @{
-  */ 
-#define HAL_FLASH_ERROR_NONE         0x00000000U    /*!< No error                      */
-#define HAL_FLASH_ERROR_RD           0x00000001U    /*!< Read Protection error         */
-#define HAL_FLASH_ERROR_PGS          0x00000002U    /*!< Programming Sequence error    */
-#define HAL_FLASH_ERROR_PGP          0x00000004U    /*!< Programming Parallelism error */
-#define HAL_FLASH_ERROR_PGA          0x00000008U    /*!< Programming Alignment error   */
-#define HAL_FLASH_ERROR_WRP          0x00000010U    /*!< Write protection error        */
-#define HAL_FLASH_ERROR_OPERATION    0x00000020U    /*!< Operation Error               */
-/**
-  * @}
-  */
-  
-/** @defgroup FLASH_Type_Program FLASH Type Program
-  * @{
-  */ 
-#define FLASH_TYPEPROGRAM_BYTE        0x00000000U  /*!< Program byte (8-bit) at a specified address           */
-#define FLASH_TYPEPROGRAM_HALFWORD    0x00000001U  /*!< Program a half-word (16-bit) at a specified address   */
-#define FLASH_TYPEPROGRAM_WORD        0x00000002U  /*!< Program a word (32-bit) at a specified address        */
-#define FLASH_TYPEPROGRAM_DOUBLEWORD  0x00000003U  /*!< Program a double word (64-bit) at a specified address */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Flag_definition FLASH Flag definition
-  * @brief Flag definition
-  * @{
-  */ 
-#define FLASH_FLAG_EOP                 FLASH_SR_EOP            /*!< FLASH End of Operation flag               */
-#define FLASH_FLAG_OPERR               FLASH_SR_SOP            /*!< FLASH operation Error flag                */
-#define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR         /*!< FLASH Write protected error flag          */
-#define FLASH_FLAG_PGAERR              FLASH_SR_PGAERR         /*!< FLASH Programming Alignment error flag    */
-#define FLASH_FLAG_PGPERR              FLASH_SR_PGPERR         /*!< FLASH Programming Parallelism error flag  */
-#define FLASH_FLAG_PGSERR              FLASH_SR_PGSERR         /*!< FLASH Programming Sequence error flag     */
-#if defined(FLASH_SR_RDERR)
-#define FLASH_FLAG_RDERR               FLASH_SR_RDERR          /*!< Read Protection error flag (PCROP)        */
-#endif /* FLASH_SR_RDERR */
-#define FLASH_FLAG_BSY                 FLASH_SR_BSY            /*!< FLASH Busy flag                           */ 
-/**
-  * @}
-  */
-  
-/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
-  * @brief FLASH Interrupt definition
-  * @{
-  */ 
-#define FLASH_IT_EOP                   FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */
-#define FLASH_IT_ERR                   0x02000000U             /*!< Error Interrupt source                  */
-/**
-  * @}
-  */  
-
-/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
-  * @{
-  */
-#define FLASH_PSIZE_BYTE           0x00000000U
-#define FLASH_PSIZE_HALF_WORD      0x00000100U
-#define FLASH_PSIZE_WORD           0x00000200U
-#define FLASH_PSIZE_DOUBLE_WORD    0x00000300U
-#define CR_PSIZE_MASK              0xFFFFFCFFU
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Keys FLASH Keys
-  * @{
-  */ 
-#define RDP_KEY                  ((uint16_t)0x00A5)
-#define FLASH_KEY1               0x45670123U
-#define FLASH_KEY2               0xCDEF89ABU
-#define FLASH_OPT_KEY1           0x08192A3BU
-#define FLASH_OPT_KEY2           0x4C5D6E7FU
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
-  * @{
-  */
-/**
-  * @brief  Set the FLASH Latency.
-  * @param  __LATENCY__ FLASH Latency
-  *         The value of this parameter depend on device used within the same series
-  * @retval none
-  */ 
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
-
-/**
-  * @brief  Get the FLASH Latency.
-  * @retval FLASH Latency
-  *          The value of this parameter depend on device used within the same series
-  */ 
-#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
-
-/**
-  * @brief  Enable the FLASH prefetch buffer.
-  * @retval none
-  */ 
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()  (FLASH->ACR |= FLASH_ACR_PRFTEN)
-
-/**
-  * @brief  Disable the FLASH prefetch buffer.
-  * @retval none
-  */ 
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
-
-/**
-  * @brief  Enable the FLASH instruction cache.
-  * @retval none
-  */ 
-#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  (FLASH->ACR |= FLASH_ACR_ICEN)
-
-/**
-  * @brief  Disable the FLASH instruction cache.
-  * @retval none
-  */ 
-#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_ICEN))
-
-/**
-  * @brief  Enable the FLASH data cache.
-  * @retval none
-  */ 
-#define __HAL_FLASH_DATA_CACHE_ENABLE()  (FLASH->ACR |= FLASH_ACR_DCEN)
-
-/**
-  * @brief  Disable the FLASH data cache.
-  * @retval none
-  */ 
-#define __HAL_FLASH_DATA_CACHE_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_DCEN))
-
-/**
-  * @brief  Resets the FLASH instruction Cache.
-  * @note   This function must be used only when the Instruction Cache is disabled.  
-  * @retval None
-  */
-#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST;  \
-                                                  FLASH->ACR &= ~FLASH_ACR_ICRST; \
-                                                 }while(0U)
-
-/**
-  * @brief  Resets the FLASH data Cache.
-  * @note   This function must be used only when the data Cache is disabled.  
-  * @retval None
-  */
-#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST;  \
-                                           FLASH->ACR &= ~FLASH_ACR_DCRST; \
-                                          }while(0U)
-/**
-  * @brief  Enable the specified FLASH interrupt.
-  * @param  __INTERRUPT__  FLASH interrupt 
-  *         This parameter can be any combination of the following values:
-  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
-  *     @arg FLASH_IT_ERR: Error Interrupt    
-  * @retval none
-  */  
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified FLASH interrupt.
-  * @param  __INTERRUPT__  FLASH interrupt 
-  *         This parameter can be any combination of the following values:
-  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
-  *     @arg FLASH_IT_ERR: Error Interrupt    
-  * @retval none
-  */  
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
-
-/**
-  * @brief  Get the specified FLASH flag status. 
-  * @param  __FLAG__ specifies the FLASH flags to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag 
-  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag 
-  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
-  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
-  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
-  *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
-  *            @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*)
-  *            @arg FLASH_FLAG_BSY   : FLASH Busy flag
-  *           (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices                             
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__)))
-
-/**
-  * @brief  Clear the specified FLASH flags.
-  * @param  __FLAG__ specifies the FLASH flags to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag 
-  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag 
-  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
-  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag 
-  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
-  *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
-  *            @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*)
-  *           (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices   
-  * @retval none
-  */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   (FLASH->SR = (__FLAG__))
-/**
-  * @}
-  */
-
-/* Include FLASH HAL Extension module */
-#include "stm32f4xx_hal_flash_ex.h"
-#include "stm32f4xx_hal_flash_ramfunc.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_Exported_Functions
-  * @{
-  */
-/** @addtogroup FLASH_Exported_Functions_Group1
-  * @{
-  */
-/* Program operation functions  ***********************************************/
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-/* FLASH IRQ handler method */
-void HAL_FLASH_IRQHandler(void);
-/* Callbacks in non blocking modes */ 
-void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions  **********************************************/
-HAL_StatusTypeDef HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_Lock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
-/* Option bytes control */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State functions  ************************************************/
-uint32_t HAL_FLASH_GetError(void);
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Variables FLASH Private Variables
-  * @{
-  */
-
-/**
-  * @}
-  */
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Constants FLASH Private Constants
-  * @{
-  */
-
-/** 
-  * @brief   ACR register byte 0 (Bits[7:0]) base address  
-  */ 
-#define ACR_BYTE0_ADDRESS           0x40023C00U 
-/** 
-  * @brief   OPTCR register byte 0 (Bits[7:0]) base address  
-  */ 
-#define OPTCR_BYTE0_ADDRESS         0x40023C14U
-/** 
-  * @brief   OPTCR register byte 1 (Bits[15:8]) base address  
-  */ 
-#define OPTCR_BYTE1_ADDRESS         0x40023C15U
-/** 
-  * @brief   OPTCR register byte 2 (Bits[23:16]) base address  
-  */ 
-#define OPTCR_BYTE2_ADDRESS         0x40023C16U
-/** 
-  * @brief   OPTCR register byte 3 (Bits[31:24]) base address  
-  */ 
-#define OPTCR_BYTE3_ADDRESS         0x40023C17U
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FLASH_Private_Macros FLASH Private Macros
-  * @{
-  */
-
-/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters
-  * @{
-  */
-#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
-                                    ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
-                                    ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
-                                    ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FLASH_Private_Functions FLASH Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_FLASH_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_flash.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FLASH_H
+#define __STM32F4xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+  * @{
+  */
+ 
+/**
+  * @brief  FLASH Procedure structure definition
+  */
+typedef enum 
+{
+  FLASH_PROC_NONE = 0U, 
+  FLASH_PROC_SECTERASE,
+  FLASH_PROC_MASSERASE,
+  FLASH_PROC_PROGRAM
+} FLASH_ProcedureTypeDef;
+
+/** 
+  * @brief  FLASH handle Structure definition  
+  */
+typedef struct
+{
+  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /*Internal variable to indicate which procedure is ongoing or not in IT context*/
+  
+  __IO uint32_t               NbSectorsToErase;   /*Internal variable to save the remaining sectors to erase in IT context*/
+  
+  __IO uint8_t                VoltageForErase;    /*Internal variable to provide voltage range selected by user in IT context*/
+  
+  __IO uint32_t               Sector;             /*Internal variable to define the current sector which is erasing*/
+  
+  __IO uint32_t               Bank;               /*Internal variable to save current bank selected during mass erase*/
+  
+  __IO uint32_t               Address;            /*Internal variable to save address selected for program*/
+  
+  HAL_LockTypeDef             Lock;               /* FLASH locking object                */
+
+  __IO uint32_t               ErrorCode;          /* FLASH error code                    */
+
+}FLASH_ProcessTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+  * @{
+  */  
+/** @defgroup FLASH_Error_Code FLASH Error Code
+  * @brief    FLASH Error Code 
+  * @{
+  */ 
+#define HAL_FLASH_ERROR_NONE         0x00000000U    /*!< No error                      */
+#define HAL_FLASH_ERROR_RD           0x00000001U    /*!< Read Protection error         */
+#define HAL_FLASH_ERROR_PGS          0x00000002U    /*!< Programming Sequence error    */
+#define HAL_FLASH_ERROR_PGP          0x00000004U    /*!< Programming Parallelism error */
+#define HAL_FLASH_ERROR_PGA          0x00000008U    /*!< Programming Alignment error   */
+#define HAL_FLASH_ERROR_WRP          0x00000010U    /*!< Write protection error        */
+#define HAL_FLASH_ERROR_OPERATION    0x00000020U    /*!< Operation Error               */
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Type_Program FLASH Type Program
+  * @{
+  */ 
+#define FLASH_TYPEPROGRAM_BYTE        0x00000000U  /*!< Program byte (8-bit) at a specified address           */
+#define FLASH_TYPEPROGRAM_HALFWORD    0x00000001U  /*!< Program a half-word (16-bit) at a specified address   */
+#define FLASH_TYPEPROGRAM_WORD        0x00000002U  /*!< Program a word (32-bit) at a specified address        */
+#define FLASH_TYPEPROGRAM_DOUBLEWORD  0x00000003U  /*!< Program a double word (64-bit) at a specified address */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flag_definition FLASH Flag definition
+  * @brief Flag definition
+  * @{
+  */ 
+#define FLASH_FLAG_EOP                 FLASH_SR_EOP            /*!< FLASH End of Operation flag               */
+#define FLASH_FLAG_OPERR               FLASH_SR_SOP            /*!< FLASH operation Error flag                */
+#define FLASH_FLAG_WRPERR              FLASH_SR_WRPERR         /*!< FLASH Write protected error flag          */
+#define FLASH_FLAG_PGAERR              FLASH_SR_PGAERR         /*!< FLASH Programming Alignment error flag    */
+#define FLASH_FLAG_PGPERR              FLASH_SR_PGPERR         /*!< FLASH Programming Parallelism error flag  */
+#define FLASH_FLAG_PGSERR              FLASH_SR_PGSERR         /*!< FLASH Programming Sequence error flag     */
+#if defined(FLASH_SR_RDERR)
+#define FLASH_FLAG_RDERR               FLASH_SR_RDERR          /*!< Read Protection error flag (PCROP)        */
+#endif /* FLASH_SR_RDERR */
+#define FLASH_FLAG_BSY                 FLASH_SR_BSY            /*!< FLASH Busy flag                           */ 
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition
+  * @brief FLASH Interrupt definition
+  * @{
+  */ 
+#define FLASH_IT_EOP                   FLASH_CR_EOPIE          /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_ERR                   0x02000000U             /*!< Error Interrupt source                  */
+/**
+  * @}
+  */  
+
+/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
+  * @{
+  */
+#define FLASH_PSIZE_BYTE           0x00000000U
+#define FLASH_PSIZE_HALF_WORD      0x00000100U
+#define FLASH_PSIZE_WORD           0x00000200U
+#define FLASH_PSIZE_DOUBLE_WORD    0x00000300U
+#define CR_PSIZE_MASK              0xFFFFFCFFU
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Keys FLASH Keys
+  * @{
+  */ 
+#define RDP_KEY                  ((uint16_t)0x00A5)
+#define FLASH_KEY1               0x45670123U
+#define FLASH_KEY2               0xCDEF89ABU
+#define FLASH_OPT_KEY1           0x08192A3BU
+#define FLASH_OPT_KEY2           0x4C5D6E7FU
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+  * @{
+  */
+/**
+  * @brief  Set the FLASH Latency.
+  * @param  __LATENCY__ FLASH Latency
+  *         The value of this parameter depend on device used within the same series
+  * @retval none
+  */ 
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) (*(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)(__LATENCY__))
+
+/**
+  * @brief  Get the FLASH Latency.
+  * @retval FLASH Latency
+  *          The value of this parameter depend on device used within the same series
+  */ 
+#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
+
+/**
+  * @brief  Enable the FLASH prefetch buffer.
+  * @retval none
+  */ 
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()  (FLASH->ACR |= FLASH_ACR_PRFTEN)
+
+/**
+  * @brief  Disable the FLASH prefetch buffer.
+  * @retval none
+  */ 
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_PRFTEN))
+
+/**
+  * @brief  Enable the FLASH instruction cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  (FLASH->ACR |= FLASH_ACR_ICEN)
+
+/**
+  * @brief  Disable the FLASH instruction cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_ICEN))
+
+/**
+  * @brief  Enable the FLASH data cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_DATA_CACHE_ENABLE()  (FLASH->ACR |= FLASH_ACR_DCEN)
+
+/**
+  * @brief  Disable the FLASH data cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_DATA_CACHE_DISABLE()   (FLASH->ACR &= (~FLASH_ACR_DCEN))
+
+/**
+  * @brief  Resets the FLASH instruction Cache.
+  * @note   This function must be used only when the Instruction Cache is disabled.  
+  * @retval None
+  */
+#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_ICRST;  \
+                                                  FLASH->ACR &= ~FLASH_ACR_ICRST; \
+                                                 }while(0U)
+
+/**
+  * @brief  Resets the FLASH data Cache.
+  * @note   This function must be used only when the data Cache is disabled.  
+  * @retval None
+  */
+#define __HAL_FLASH_DATA_CACHE_RESET() do {FLASH->ACR |= FLASH_ACR_DCRST;  \
+                                           FLASH->ACR &= ~FLASH_ACR_DCRST; \
+                                          }while(0U)
+/**
+  * @brief  Enable the specified FLASH interrupt.
+  * @param  __INTERRUPT__  FLASH interrupt 
+  *         This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+  *     @arg FLASH_IT_ERR: Error Interrupt    
+  * @retval none
+  */  
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  (FLASH->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified FLASH interrupt.
+  * @param  __INTERRUPT__  FLASH interrupt 
+  *         This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+  *     @arg FLASH_IT_ERR: Error Interrupt    
+  * @retval none
+  */  
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (FLASH->CR &= ~(uint32_t)(__INTERRUPT__))
+
+/**
+  * @brief  Get the specified FLASH flag status. 
+  * @param  __FLAG__ specifies the FLASH flags to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag 
+  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag 
+  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
+  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
+  *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+  *            @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*)
+  *            @arg FLASH_FLAG_BSY   : FLASH Busy flag
+  *           (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices                             
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define __HAL_FLASH_GET_FLAG(__FLAG__)   ((FLASH->SR & (__FLAG__)))
+
+/**
+  * @brief  Clear the specified FLASH flags.
+  * @param  __FLAG__ specifies the FLASH flags to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg FLASH_FLAG_EOP   : FLASH End of Operation flag 
+  *            @arg FLASH_FLAG_OPERR : FLASH operation Error flag 
+  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
+  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag 
+  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
+  *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+  *            @arg FLASH_FLAG_RDERR : FLASH Read Protection error flag (PCROP) (*)
+  *           (*) FLASH_FLAG_RDERR is not available for STM32F405xx/407xx/415xx/417xx devices   
+  * @retval none
+  */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   (FLASH->SR = (__FLAG__))
+/**
+  * @}
+  */
+
+/* Include FLASH HAL Extension module */
+#include "stm32f4xx_hal_flash_ex.h"
+#include "stm32f4xx_hal_flash_ramfunc.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_Exported_Functions
+  * @{
+  */
+/** @addtogroup FLASH_Exported_Functions_Group1
+  * @{
+  */
+/* Program operation functions  ***********************************************/
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+/* FLASH IRQ handler method */
+void HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */ 
+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_Lock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
+/* Option bytes control */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
+/**
+  * @}
+  */
+
+/** @addtogroup FLASH_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State functions  ************************************************/
+uint32_t HAL_FLASH_GetError(void);
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+  * @{
+  */
+
+/** 
+  * @brief   ACR register byte 0 (Bits[7:0]) base address  
+  */ 
+#define ACR_BYTE0_ADDRESS           0x40023C00U 
+/** 
+  * @brief   OPTCR register byte 0 (Bits[7:0]) base address  
+  */ 
+#define OPTCR_BYTE0_ADDRESS         0x40023C14U
+/** 
+  * @brief   OPTCR register byte 1 (Bits[15:8]) base address  
+  */ 
+#define OPTCR_BYTE1_ADDRESS         0x40023C15U
+/** 
+  * @brief   OPTCR register byte 2 (Bits[23:16]) base address  
+  */ 
+#define OPTCR_BYTE2_ADDRESS         0x40023C16U
+/** 
+  * @brief   OPTCR register byte 3 (Bits[31:24]) base address  
+  */ 
+#define OPTCR_BYTE3_ADDRESS         0x40023C17U
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+  * @{
+  */
+
+/** @defgroup FLASH_IS_FLASH_Definitions FLASH Private macros to check input parameters
+  * @{
+  */
+#define IS_FLASH_TYPEPROGRAM(VALUE)(((VALUE) == FLASH_TYPEPROGRAM_BYTE) || \
+                                    ((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \
+                                    ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \
+                                    ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD))  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_FLASH_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h
index 1cf8c45..908fd5e 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h
@@ -1,1063 +1,1063 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_flash_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of FLASH HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_FLASH_EX_H
-#define __STM32F4xx_HAL_FLASH_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASHEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
-  * @{
-  */
-
-/**
-  * @brief  FLASH Erase structure definition
-  */
-typedef struct
-{
-  uint32_t TypeErase;   /*!< Mass erase or sector Erase.
-                             This parameter can be a value of @ref FLASHEx_Type_Erase */
-
-  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
-                             This parameter must be a value of @ref FLASHEx_Banks */
-
-  uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
-                             This parameter must be a value of @ref FLASHEx_Sectors */
-
-  uint32_t NbSectors;   /*!< Number of sectors to be erased.
-                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
-
-  uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
-                             This parameter must be a value of @ref FLASHEx_Voltage_Range */
-
-} FLASH_EraseInitTypeDef;
-
-/**
-  * @brief  FLASH Option Bytes Program structure definition
-  */
-typedef struct
-{
-  uint32_t OptionType;   /*!< Option byte to be configured.
-                              This parameter can be a value of @ref FLASHEx_Option_Type */
-
-  uint32_t WRPState;     /*!< Write protection activation or deactivation.
-                              This parameter can be a value of @ref FLASHEx_WRP_State */
-
-  uint32_t WRPSector;         /*!< Specifies the sector(s) to be write protected.
-                              The value of this parameter depend on device used within the same series */
-
-  uint32_t Banks;        /*!< Select banks for WRP activation/deactivation of all sectors.
-                              This parameter must be a value of @ref FLASHEx_Banks */        
-
-  uint32_t RDPLevel;     /*!< Set the read protection level.
-                              This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
-
-  uint32_t BORLevel;     /*!< Set the BOR Level.
-                              This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
-
-  uint8_t  USERConfig;   /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */
-
-} FLASH_OBProgramInitTypeDef;
-
-/**
-  * @brief  FLASH Advanced Option Bytes Program structure definition
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-typedef struct
-{
-  uint32_t OptionType;     /*!< Option byte to be configured for extension.
-                                This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */
-
-  uint32_t PCROPState;     /*!< PCROP activation or deactivation.
-                                This parameter can be a value of @ref FLASHEx_PCROP_State */
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-  uint16_t Sectors;        /*!< specifies the sector(s) set for PCROP.
-                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\
-          STM32F412Cx || STM32F413xx || STM32F423xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-  uint32_t Banks;          /*!< Select banks for PCROP activation/deactivation of all sectors.
-                                This parameter must be a value of @ref FLASHEx_Banks */
-
-  uint16_t SectorsBank1;   /*!< Specifies the sector(s) set for PCROP for Bank1.
-                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
-
-  uint16_t SectorsBank2;   /*!< Specifies the sector(s) set for PCROP for Bank2.
-                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
-
-  uint8_t BootConfig;      /*!< Specifies Option bytes for boot config.
-                                This parameter can be a value of @ref FLASHEx_Dual_Boot */
-
-#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-}FLASH_AdvOBProgramInitTypeDef;
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx ||
-          STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
-  * @{
-  */
-
-/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
-  * @{
-  */ 
-#define FLASH_TYPEERASE_SECTORS         0x00000000U  /*!< Sectors erase only          */
-#define FLASH_TYPEERASE_MASSERASE       0x00000001U  /*!< Flash Mass erase activation */
-/**
-  * @}
-  */
-  
-/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
-  * @{
-  */ 
-#define FLASH_VOLTAGE_RANGE_1        0x00000000U  /*!< Device operating range: 1.8V to 2.1V                */
-#define FLASH_VOLTAGE_RANGE_2        0x00000001U  /*!< Device operating range: 2.1V to 2.7V                */
-#define FLASH_VOLTAGE_RANGE_3        0x00000002U  /*!< Device operating range: 2.7V to 3.6V                */
-#define FLASH_VOLTAGE_RANGE_4        0x00000003U  /*!< Device operating range: 2.7V to 3.6V + External Vpp */
-/**
-  * @}
-  */
-  
-/** @defgroup FLASHEx_WRP_State FLASH WRP State
-  * @{
-  */ 
-#define OB_WRPSTATE_DISABLE       0x00000000U  /*!< Disable the write protection of the desired bank 1 sectors */
-#define OB_WRPSTATE_ENABLE        0x00000001U  /*!< Enable the write protection of the desired bank 1 sectors  */
-/**
-  * @}
-  */
-  
-/** @defgroup FLASHEx_Option_Type FLASH Option Type
-  * @{
-  */ 
-#define OPTIONBYTE_WRP        0x00000001U  /*!< WRP option byte configuration  */
-#define OPTIONBYTE_RDP        0x00000002U  /*!< RDP option byte configuration  */
-#define OPTIONBYTE_USER       0x00000004U  /*!< USER option byte configuration */
-#define OPTIONBYTE_BOR        0x00000008U  /*!< BOR option byte configuration  */
-/**
-  * @}
-  */
-  
-/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
-  * @{
-  */
-#define OB_RDP_LEVEL_0   ((uint8_t)0xAA)
-#define OB_RDP_LEVEL_1   ((uint8_t)0x55)
-#define OB_RDP_LEVEL_2   ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2 
-                                              it s no more possible to go back to level 1 or 0 */
-/**
-  * @}
-  */ 
-  
-/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
-  * @{
-  */ 
-#define OB_IWDG_SW                     ((uint8_t)0x20)  /*!< Software IWDG selected */
-#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware IWDG selected */
-/**
-  * @}
-  */ 
-  
-/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
-  * @{
-  */ 
-#define OB_STOP_NO_RST                 ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP    */
-/**
-  * @}
-  */ 
-
-
-/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
-  * @{
-  */ 
-#define OB_STDBY_NO_RST                ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY    */
-/**
-  * @}
-  */    
-
-/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
-  * @{
-  */  
-#define OB_BOR_LEVEL3          ((uint8_t)0x00)  /*!< Supply voltage ranges from 2.70 to 3.60 V */
-#define OB_BOR_LEVEL2          ((uint8_t)0x04)  /*!< Supply voltage ranges from 2.40 to 2.70 V */
-#define OB_BOR_LEVEL1          ((uint8_t)0x08)  /*!< Supply voltage ranges from 2.10 to 2.40 V */
-#define OB_BOR_OFF             ((uint8_t)0x0C)  /*!< Supply voltage ranges from 1.62 to 2.10 V */
-/**
-  * @}
-  */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
-  * @{
-  */ 
-#define OB_PCROP_STATE_DISABLE       0x00000000U  /*!< Disable PCROP */
-#define OB_PCROP_STATE_ENABLE        0x00000001U  /*!< Enable PCROP  */
-/**
-  * @}
-  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type
-  * @{
-  */ 
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-#define OPTIONBYTE_PCROP        0x00000001U  /*!< PCROP option byte configuration      */
-#define OPTIONBYTE_BOOTCONFIG   0x00000002U  /*!< BOOTConfig option byte configuration */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
-    defined(STM32F423xx)
-#define OPTIONBYTE_PCROP        0x00000001U  /*!<PCROP option byte configuration */
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
-          STM32F413xx || STM32F423xx */
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Latency FLASH Latency
-  * @{
-  */
-/*------------------------- STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx ----------------------*/  
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
-#define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
-#define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
-#define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
-#define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
-#define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
-#define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
-#define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
-#define FLASH_LATENCY_8                FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycles    */
-#define FLASH_LATENCY_9                FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycles     */
-#define FLASH_LATENCY_10               FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */
-#define FLASH_LATENCY_11               FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */
-#define FLASH_LATENCY_12               FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */
-#define FLASH_LATENCY_13               FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */
-#define FLASH_LATENCY_14               FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */
-#define FLASH_LATENCY_15               FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-/*--------------------------------------------------------------------------------------------------------------*/
-
-/*-------------------------- STM32F40xxx/STM32F41xxx/STM32F401xx/STM32F411xx/STM32F423xx -----------------------*/ 
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
-    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-     
-#define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
-#define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
-#define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
-#define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
-#define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
-#define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
-#define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
-#define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
-          STM32F413xx || STM32F423xx */
-/*--------------------------------------------------------------------------------------------------------------*/
-
-/**
-  * @}
-  */ 
-  
-
-/** @defgroup FLASHEx_Banks FLASH Banks
-  * @{
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-#define FLASH_BANK_1     1U /*!< Bank 1   */
-#define FLASH_BANK_2     2U /*!< Bank 2   */
-#define FLASH_BANK_BOTH  ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
-    defined(STM32F423xx)
-#define FLASH_BANK_1     1U /*!< Bank 1   */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
-          STM32F413xx || STM32F423xx */
-/**
-  * @}
-  */ 
-    
-/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
-  * @{
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-#define FLASH_MER_BIT     (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits here to clear */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
-    defined(STM32F423xx)
-#define FLASH_MER_BIT     (FLASH_CR_MER) /*!< only 1 MER Bit */
-#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
-          STM32F413xx || STM32F423xx */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASHEx_Sectors FLASH Sectors
-  * @{
-  */
-/*-------------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx ------------------------------------*/   
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-#define FLASH_SECTOR_0     0U  /*!< Sector Number 0   */
-#define FLASH_SECTOR_1     1U  /*!< Sector Number 1   */
-#define FLASH_SECTOR_2     2U  /*!< Sector Number 2   */
-#define FLASH_SECTOR_3     3U  /*!< Sector Number 3   */
-#define FLASH_SECTOR_4     4U  /*!< Sector Number 4   */
-#define FLASH_SECTOR_5     5U  /*!< Sector Number 5   */
-#define FLASH_SECTOR_6     6U  /*!< Sector Number 6   */
-#define FLASH_SECTOR_7     7U  /*!< Sector Number 7   */
-#define FLASH_SECTOR_8     8U  /*!< Sector Number 8   */
-#define FLASH_SECTOR_9     9U  /*!< Sector Number 9   */
-#define FLASH_SECTOR_10    10U /*!< Sector Number 10  */
-#define FLASH_SECTOR_11    11U /*!< Sector Number 11  */
-#define FLASH_SECTOR_12    12U /*!< Sector Number 12  */
-#define FLASH_SECTOR_13    13U /*!< Sector Number 13  */
-#define FLASH_SECTOR_14    14U /*!< Sector Number 14  */
-#define FLASH_SECTOR_15    15U /*!< Sector Number 15  */
-#define FLASH_SECTOR_16    16U /*!< Sector Number 16  */
-#define FLASH_SECTOR_17    17U /*!< Sector Number 17  */
-#define FLASH_SECTOR_18    18U /*!< Sector Number 18  */
-#define FLASH_SECTOR_19    19U /*!< Sector Number 19  */
-#define FLASH_SECTOR_20    20U /*!< Sector Number 20  */
-#define FLASH_SECTOR_21    21U /*!< Sector Number 21  */
-#define FLASH_SECTOR_22    22U /*!< Sector Number 22  */
-#define FLASH_SECTOR_23    23U /*!< Sector Number 23  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*-------------------------------------- STM32F413xx/STM32F423xx --------------------------------------*/   
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define FLASH_SECTOR_0     0U  /*!< Sector Number 0   */
-#define FLASH_SECTOR_1     1U  /*!< Sector Number 1   */
-#define FLASH_SECTOR_2     2U  /*!< Sector Number 2   */
-#define FLASH_SECTOR_3     3U  /*!< Sector Number 3   */
-#define FLASH_SECTOR_4     4U  /*!< Sector Number 4   */
-#define FLASH_SECTOR_5     5U  /*!< Sector Number 5   */
-#define FLASH_SECTOR_6     6U  /*!< Sector Number 6   */
-#define FLASH_SECTOR_7     7U  /*!< Sector Number 7   */
-#define FLASH_SECTOR_8     8U  /*!< Sector Number 8   */
-#define FLASH_SECTOR_9     9U  /*!< Sector Number 9   */
-#define FLASH_SECTOR_10    10U /*!< Sector Number 10  */
-#define FLASH_SECTOR_11    11U /*!< Sector Number 11  */
-#define FLASH_SECTOR_12    12U /*!< Sector Number 12  */
-#define FLASH_SECTOR_13    13U /*!< Sector Number 13  */
-#define FLASH_SECTOR_14    14U /*!< Sector Number 14  */
-#define FLASH_SECTOR_15    15U /*!< Sector Number 15  */
-#endif /* STM32F413xx || STM32F423xx */
-/*-----------------------------------------------------------------------------------------------------*/      
-
-/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ 
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define FLASH_SECTOR_0     0U  /*!< Sector Number 0   */
-#define FLASH_SECTOR_1     1U  /*!< Sector Number 1   */
-#define FLASH_SECTOR_2     2U  /*!< Sector Number 2   */
-#define FLASH_SECTOR_3     3U  /*!< Sector Number 3   */
-#define FLASH_SECTOR_4     4U  /*!< Sector Number 4   */
-#define FLASH_SECTOR_5     5U  /*!< Sector Number 5   */
-#define FLASH_SECTOR_6     6U  /*!< Sector Number 6   */
-#define FLASH_SECTOR_7     7U  /*!< Sector Number 7   */
-#define FLASH_SECTOR_8     8U  /*!< Sector Number 8   */
-#define FLASH_SECTOR_9     9U  /*!< Sector Number 9   */
-#define FLASH_SECTOR_10    10U /*!< Sector Number 10  */
-#define FLASH_SECTOR_11    11U /*!< Sector Number 11  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*--------------------------------------------- STM32F401xC -------------------------------------------*/ 
-#if defined(STM32F401xC)
-#define FLASH_SECTOR_0     0U /*!< Sector Number 0   */
-#define FLASH_SECTOR_1     1U /*!< Sector Number 1   */
-#define FLASH_SECTOR_2     2U /*!< Sector Number 2   */
-#define FLASH_SECTOR_3     3U /*!< Sector Number 3   */
-#define FLASH_SECTOR_4     4U /*!< Sector Number 4   */
-#define FLASH_SECTOR_5     5U /*!< Sector Number 5   */
-#endif /* STM32F401xC */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*--------------------------------------------- STM32F410xx -------------------------------------------*/ 
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define FLASH_SECTOR_0     0U /*!< Sector Number 0   */
-#define FLASH_SECTOR_1     1U /*!< Sector Number 1   */
-#define FLASH_SECTOR_2     2U /*!< Sector Number 2   */
-#define FLASH_SECTOR_3     3U /*!< Sector Number 3   */
-#define FLASH_SECTOR_4     4U /*!< Sector Number 4   */
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
-#define FLASH_SECTOR_0     0U /*!< Sector Number 0   */
-#define FLASH_SECTOR_1     1U /*!< Sector Number 1   */
-#define FLASH_SECTOR_2     2U /*!< Sector Number 2   */
-#define FLASH_SECTOR_3     3U /*!< Sector Number 3   */
-#define FLASH_SECTOR_4     4U /*!< Sector Number 4   */
-#define FLASH_SECTOR_5     5U /*!< Sector Number 5   */
-#define FLASH_SECTOR_6     6U /*!< Sector Number 6   */
-#define FLASH_SECTOR_7     7U /*!< Sector Number 7   */
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
-  * @{
-  */
-/*--------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx -------------------------*/  
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx) 
-#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
-#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
-#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
-#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
-#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
-#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */
-#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */
-#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */
-#define OB_WRP_SECTOR_8       0x00000100U /*!< Write protection of Sector8     */
-#define OB_WRP_SECTOR_9       0x00000200U /*!< Write protection of Sector9     */
-#define OB_WRP_SECTOR_10      0x00000400U /*!< Write protection of Sector10    */
-#define OB_WRP_SECTOR_11      0x00000800U /*!< Write protection of Sector11    */
-#define OB_WRP_SECTOR_12      0x00000001U << 12U /*!< Write protection of Sector12    */
-#define OB_WRP_SECTOR_13      0x00000002U << 12U /*!< Write protection of Sector13    */
-#define OB_WRP_SECTOR_14      0x00000004U << 12U /*!< Write protection of Sector14    */
-#define OB_WRP_SECTOR_15      0x00000008U << 12U /*!< Write protection of Sector15    */
-#define OB_WRP_SECTOR_16      0x00000010U << 12U /*!< Write protection of Sector16    */
-#define OB_WRP_SECTOR_17      0x00000020U << 12U /*!< Write protection of Sector17    */
-#define OB_WRP_SECTOR_18      0x00000040U << 12U /*!< Write protection of Sector18    */
-#define OB_WRP_SECTOR_19      0x00000080U << 12U /*!< Write protection of Sector19    */
-#define OB_WRP_SECTOR_20      0x00000100U << 12U /*!< Write protection of Sector20    */
-#define OB_WRP_SECTOR_21      0x00000200U << 12U /*!< Write protection of Sector21    */
-#define OB_WRP_SECTOR_22      0x00000400U << 12U /*!< Write protection of Sector22    */
-#define OB_WRP_SECTOR_23      0x00000800U << 12U /*!< Write protection of Sector23    */
-#define OB_WRP_SECTOR_All     0x00000FFFU << 12U /*!< Write protection of all Sectors */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*--------------------------------------- STM32F413xx/STM32F423xx -------------------------------------*/ 
-#if defined(STM32F413xx) || defined(STM32F423xx)  
-#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
-#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
-#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
-#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
-#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
-#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */
-#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */
-#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */
-#define OB_WRP_SECTOR_8       0x00000100U /*!< Write protection of Sector8     */
-#define OB_WRP_SECTOR_9       0x00000200U /*!< Write protection of Sector9     */
-#define OB_WRP_SECTOR_10      0x00000400U /*!< Write protection of Sector10    */
-#define OB_WRP_SECTOR_11      0x00000800U /*!< Write protection of Sector11    */
-#define OB_WRP_SECTOR_12      0x00001000U /*!< Write protection of Sector12    */
-#define OB_WRP_SECTOR_13      0x00002000U /*!< Write protection of Sector13    */
-#define OB_WRP_SECTOR_14      0x00004000U /*!< Write protection of Sector14    */
-#define OB_WRP_SECTOR_15      0x00004000U /*!< Write protection of Sector15    */      
-#define OB_WRP_SECTOR_All     0x00007FFFU /*!< Write protection of all Sectors */
-#endif /* STM32F413xx || STM32F423xx */
-/*-----------------------------------------------------------------------------------------------------*/    
-      
-/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ 
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
-#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
-#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
-#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
-#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
-#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */
-#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */
-#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */
-#define OB_WRP_SECTOR_8       0x00000100U /*!< Write protection of Sector8     */
-#define OB_WRP_SECTOR_9       0x00000200U /*!< Write protection of Sector9     */
-#define OB_WRP_SECTOR_10      0x00000400U /*!< Write protection of Sector10    */
-#define OB_WRP_SECTOR_11      0x00000800U /*!< Write protection of Sector11    */
-#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*--------------------------------------------- STM32F401xC -------------------------------------------*/
-#if defined(STM32F401xC)
-#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
-#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
-#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
-#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
-#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
-#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */
-#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */
-#endif /* STM32F401xC */
-/*-----------------------------------------------------------------------------------------------------*/
- 
-/*--------------------------------------------- STM32F410xx -------------------------------------------*/
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
-#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
-#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
-#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
-#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
-#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
-#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
-#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
-#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
-#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
-#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
-#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */
-#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */
-#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */
-#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
-/*-----------------------------------------------------------------------------------------------------*/
-/**
-  * @}
-  */
-  
-/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection
-  * @{
-  */
-/*-------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx ---------------------------*/   
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx) 
-#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */
-#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */
-#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */
-#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */
-#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */
-#define OB_PCROP_SECTOR_5        0x00000020U /*!< PC Read/Write protection of Sector5      */
-#define OB_PCROP_SECTOR_6        0x00000040U /*!< PC Read/Write protection of Sector6      */
-#define OB_PCROP_SECTOR_7        0x00000080U /*!< PC Read/Write protection of Sector7      */
-#define OB_PCROP_SECTOR_8        0x00000100U /*!< PC Read/Write protection of Sector8      */
-#define OB_PCROP_SECTOR_9        0x00000200U /*!< PC Read/Write protection of Sector9      */
-#define OB_PCROP_SECTOR_10       0x00000400U /*!< PC Read/Write protection of Sector10     */
-#define OB_PCROP_SECTOR_11       0x00000800U /*!< PC Read/Write protection of Sector11     */
-#define OB_PCROP_SECTOR_12       0x00000001U /*!< PC Read/Write protection of Sector12     */
-#define OB_PCROP_SECTOR_13       0x00000002U /*!< PC Read/Write protection of Sector13     */
-#define OB_PCROP_SECTOR_14       0x00000004U /*!< PC Read/Write protection of Sector14     */
-#define OB_PCROP_SECTOR_15       0x00000008U /*!< PC Read/Write protection of Sector15     */
-#define OB_PCROP_SECTOR_16       0x00000010U /*!< PC Read/Write protection of Sector16     */
-#define OB_PCROP_SECTOR_17       0x00000020U /*!< PC Read/Write protection of Sector17     */
-#define OB_PCROP_SECTOR_18       0x00000040U /*!< PC Read/Write protection of Sector18     */
-#define OB_PCROP_SECTOR_19       0x00000080U /*!< PC Read/Write protection of Sector19     */
-#define OB_PCROP_SECTOR_20       0x00000100U /*!< PC Read/Write protection of Sector20     */
-#define OB_PCROP_SECTOR_21       0x00000200U /*!< PC Read/Write protection of Sector21     */
-#define OB_PCROP_SECTOR_22       0x00000400U /*!< PC Read/Write protection of Sector22     */
-#define OB_PCROP_SECTOR_23       0x00000800U /*!< PC Read/Write protection of Sector23     */
-#define OB_PCROP_SECTOR_All      0x00000FFFU /*!< PC Read/Write protection of all Sectors  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-/*-----------------------------------------------------------------------------------------------------*/
-      
-/*------------------------------------- STM32F413xx/STM32F423xx ---------------------------------------*/
-#if defined(STM32F413xx) || defined(STM32F423xx)  
-#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */
-#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */
-#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */
-#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */
-#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */
-#define OB_PCROP_SECTOR_5        0x00000020U /*!< PC Read/Write protection of Sector5      */
-#define OB_PCROP_SECTOR_6        0x00000040U /*!< PC Read/Write protection of Sector6      */
-#define OB_PCROP_SECTOR_7        0x00000080U /*!< PC Read/Write protection of Sector7      */
-#define OB_PCROP_SECTOR_8        0x00000100U /*!< PC Read/Write protection of Sector8      */
-#define OB_PCROP_SECTOR_9        0x00000200U /*!< PC Read/Write protection of Sector9      */
-#define OB_PCROP_SECTOR_10       0x00000400U /*!< PC Read/Write protection of Sector10     */
-#define OB_PCROP_SECTOR_11       0x00000800U /*!< PC Read/Write protection of Sector11     */
-#define OB_PCROP_SECTOR_12       0x00001000U /*!< PC Read/Write protection of Sector12     */
-#define OB_PCROP_SECTOR_13       0x00002000U /*!< PC Read/Write protection of Sector13     */
-#define OB_PCROP_SECTOR_14       0x00004000U /*!< PC Read/Write protection of Sector14     */
-#define OB_PCROP_SECTOR_15       0x00004000U /*!< PC Read/Write protection of Sector15     */      
-#define OB_PCROP_SECTOR_All      0x00007FFFU /*!< PC Read/Write protection of all Sectors  */
-#endif /* STM32F413xx || STM32F423xx */
-/*-----------------------------------------------------------------------------------------------------*/      
-
-/*--------------------------------------------- STM32F401xC -------------------------------------------*/
-#if defined(STM32F401xC)
-#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */
-#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */
-#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */
-#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */
-#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */
-#define OB_PCROP_SECTOR_5        0x00000020U /*!< PC Read/Write protection of Sector5      */
-#define OB_PCROP_SECTOR_All      0x00000FFFU /*!< PC Read/Write protection of all Sectors  */
-#endif /* STM32F401xC */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*--------------------------------------------- STM32F410xx -------------------------------------------*/
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */
-#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */
-#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */
-#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */
-#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */
-#define OB_PCROP_SECTOR_All      0x00000FFFU /*!< PC Read/Write protection of all Sectors  */
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/*-------------- STM32F401xE/STM32F411xE/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F446xx --*/
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */
-#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */
-#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */
-#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */
-#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */
-#define OB_PCROP_SECTOR_5        0x00000020U /*!< PC Read/Write protection of Sector5      */
-#define OB_PCROP_SECTOR_6        0x00000040U /*!< PC Read/Write protection of Sector6      */
-#define OB_PCROP_SECTOR_7        0x00000080U /*!< PC Read/Write protection of Sector7      */
-#define OB_PCROP_SECTOR_All      0x00000FFFU /*!< PC Read/Write protection of all Sectors  */
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/*-----------------------------------------------------------------------------------------------------*/
-
-/**
-  * @}
-  */
-  
-/** @defgroup FLASHEx_Dual_Boot FLASH Dual Boot
-  * @{
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx) 
-#define OB_DUAL_BOOT_ENABLE   ((uint8_t)0x10) /*!< Dual Bank Boot Enable                             */
-#define OB_DUAL_BOOT_DISABLE  ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/** @defgroup  FLASHEx_Selection_Protection_Mode FLASH Selection Protection Mode
-  * @{
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define OB_PCROP_DESELECTED     ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
-#define OB_PCROP_SELECTED       ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i   */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASHEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group1
-  * @{
-  */
-/* Extension Program operation functions  *************************************/
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
-void              HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
-HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
-HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Constants FLASH Private Constants
-  * @{
-  */
-/*--------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx---------------------*/ 
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define FLASH_SECTOR_TOTAL  24U
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-/*-------------------------------------- STM32F413xx/STM32F423xx ---------------------------------------*/
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define FLASH_SECTOR_TOTAL  16U
-#endif /* STM32F413xx || STM32F423xx */
-
-/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ 
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define FLASH_SECTOR_TOTAL  12U
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-/*--------------------------------------------- STM32F401xC -------------------------------------------*/ 
-#if defined(STM32F401xC)
-#define FLASH_SECTOR_TOTAL  6U
-#endif /* STM32F401xC */
-
-/*--------------------------------------------- STM32F410xx -------------------------------------------*/ 
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define FLASH_SECTOR_TOTAL  5U
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-/*--------------------------------- STM32F401xE/STM32F411xE/STM32F412xG/STM32F446xx -------------------*/
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
-#define FLASH_SECTOR_TOTAL  8U
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
-
-/** 
-  * @brief OPTCR1 register byte 2 (Bits[23:16]) base address  
-  */ 
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)  
-#define OPTCR1_BYTE2_ADDRESS         0x40023C1AU
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
-  * @{
-  */
-
-/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
-  * @{
-  */
-
-#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
-                                  ((VALUE) == FLASH_TYPEERASE_MASSERASE))  
-
-#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
-                               ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
-                               ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
-                               ((RANGE) == FLASH_VOLTAGE_RANGE_4))  
-
-#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
-                           ((VALUE) == OB_WRPSTATE_ENABLE))  
-
-#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
-
-#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
-                                ((LEVEL) == OB_RDP_LEVEL_1) ||\
-                                ((LEVEL) == OB_RDP_LEVEL_2))
-
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
-
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
-
-#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
-                                ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) || \
-                             ((VALUE) == OB_PCROP_STATE_ENABLE))  
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP) || \
-                       ((VALUE) == OPTIONBYTE_BOOTCONFIG))  
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
-    defined(STM32F423xx)
-#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP))  
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-  
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
-                                   ((LATENCY) == FLASH_LATENCY_1)  || \
-                                   ((LATENCY) == FLASH_LATENCY_2)  || \
-                                   ((LATENCY) == FLASH_LATENCY_3)  || \
-                                   ((LATENCY) == FLASH_LATENCY_4)  || \
-                                   ((LATENCY) == FLASH_LATENCY_5)  || \
-                                   ((LATENCY) == FLASH_LATENCY_6)  || \
-                                   ((LATENCY) == FLASH_LATENCY_7)  || \
-                                   ((LATENCY) == FLASH_LATENCY_8)  || \
-                                   ((LATENCY) == FLASH_LATENCY_9)  || \
-                                   ((LATENCY) == FLASH_LATENCY_10) || \
-                                   ((LATENCY) == FLASH_LATENCY_11) || \
-                                   ((LATENCY) == FLASH_LATENCY_12) || \
-                                   ((LATENCY) == FLASH_LATENCY_13) || \
-                                   ((LATENCY) == FLASH_LATENCY_14) || \
-                                   ((LATENCY) == FLASH_LATENCY_15))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
-    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
-                                   ((LATENCY) == FLASH_LATENCY_1)  || \
-                                   ((LATENCY) == FLASH_LATENCY_2)  || \
-                                   ((LATENCY) == FLASH_LATENCY_3)  || \
-                                   ((LATENCY) == FLASH_LATENCY_4)  || \
-                                   ((LATENCY) == FLASH_LATENCY_5)  || \
-                                   ((LATENCY) == FLASH_LATENCY_6)  || \
-                                   ((LATENCY) == FLASH_LATENCY_7))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx ||\
-          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)  || \
-                             ((BANK) == FLASH_BANK_2)  || \
-                             ((BANK) == FLASH_BANK_BOTH))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
-    defined(STM32F423xx)
-#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx ||\
-          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
- 
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
-                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
-                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
-                                  ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
-                                  ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
-                                  ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11)  ||\
-                                  ((SECTOR) == FLASH_SECTOR_12)  || ((SECTOR) == FLASH_SECTOR_13)  ||\
-                                  ((SECTOR) == FLASH_SECTOR_14)  || ((SECTOR) == FLASH_SECTOR_15)  ||\
-                                  ((SECTOR) == FLASH_SECTOR_16)  || ((SECTOR) == FLASH_SECTOR_17)  ||\
-                                  ((SECTOR) == FLASH_SECTOR_18)  || ((SECTOR) == FLASH_SECTOR_19)  ||\
-                                  ((SECTOR) == FLASH_SECTOR_20)  || ((SECTOR) == FLASH_SECTOR_21)  ||\
-                                  ((SECTOR) == FLASH_SECTOR_22)  || ((SECTOR) == FLASH_SECTOR_23))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
-                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
-                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
-                                  ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
-                                  ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
-                                  ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11)  ||\
-                                  ((SECTOR) == FLASH_SECTOR_12)  || ((SECTOR) == FLASH_SECTOR_13)  ||\
-                                  ((SECTOR) == FLASH_SECTOR_14)  || ((SECTOR) == FLASH_SECTOR_15))
-#endif /* STM32F413xx || STM32F423xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F401xC)
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5))
-#endif /* STM32F401xC */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_4))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
-
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
-                                   (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))
-
-#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
-  
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFF000000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F413xx) || defined(STM32F423xx) 
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F413xx || STM32F423xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-
-#if defined(STM32F401xC)
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F401xC */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
-    defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-   
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))      
-#endif /* STM32F413xx || STM32F423xx */
-
-#if defined(STM32F401xC)
-#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F401xC */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
-    defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
-#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx) 
-#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup FLASHEx_Private_Functions FLASH Private Functions
-  * @{
-  */
-void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
-void FLASH_FlushCaches(void);
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_FLASH_EX_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_flash_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_FLASH_EX_H
+#define __STM32F4xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASHEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Erase structure definition
+  */
+typedef struct
+{
+  uint32_t TypeErase;   /*!< Mass erase or sector Erase.
+                             This parameter can be a value of @ref FLASHEx_Type_Erase */
+
+  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.
+                             This parameter must be a value of @ref FLASHEx_Banks */
+
+  uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled
+                             This parameter must be a value of @ref FLASHEx_Sectors */
+
+  uint32_t NbSectors;   /*!< Number of sectors to be erased.
+                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+
+  uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism
+                             This parameter must be a value of @ref FLASHEx_Voltage_Range */
+
+} FLASH_EraseInitTypeDef;
+
+/**
+  * @brief  FLASH Option Bytes Program structure definition
+  */
+typedef struct
+{
+  uint32_t OptionType;   /*!< Option byte to be configured.
+                              This parameter can be a value of @ref FLASHEx_Option_Type */
+
+  uint32_t WRPState;     /*!< Write protection activation or deactivation.
+                              This parameter can be a value of @ref FLASHEx_WRP_State */
+
+  uint32_t WRPSector;         /*!< Specifies the sector(s) to be write protected.
+                              The value of this parameter depend on device used within the same series */
+
+  uint32_t Banks;        /*!< Select banks for WRP activation/deactivation of all sectors.
+                              This parameter must be a value of @ref FLASHEx_Banks */        
+
+  uint32_t RDPLevel;     /*!< Set the read protection level.
+                              This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
+
+  uint32_t BORLevel;     /*!< Set the BOR Level.
+                              This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
+
+  uint8_t  USERConfig;   /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. */
+
+} FLASH_OBProgramInitTypeDef;
+
+/**
+  * @brief  FLASH Advanced Option Bytes Program structure definition
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+typedef struct
+{
+  uint32_t OptionType;     /*!< Option byte to be configured for extension.
+                                This parameter can be a value of @ref FLASHEx_Advanced_Option_Type */
+
+  uint32_t PCROPState;     /*!< PCROP activation or deactivation.
+                                This parameter can be a value of @ref FLASHEx_PCROP_State */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+  uint16_t Sectors;        /*!< specifies the sector(s) set for PCROP.
+                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx ||\
+          STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+  uint32_t Banks;          /*!< Select banks for PCROP activation/deactivation of all sectors.
+                                This parameter must be a value of @ref FLASHEx_Banks */
+
+  uint16_t SectorsBank1;   /*!< Specifies the sector(s) set for PCROP for Bank1.
+                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+
+  uint16_t SectorsBank2;   /*!< Specifies the sector(s) set for PCROP for Bank2.
+                                This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */
+
+  uint8_t BootConfig;      /*!< Specifies Option bytes for boot config.
+                                This parameter can be a value of @ref FLASHEx_Dual_Boot */
+
+#endif /*STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+}FLASH_AdvOBProgramInitTypeDef;
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx ||
+          STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
+  * @{
+  */ 
+#define FLASH_TYPEERASE_SECTORS         0x00000000U  /*!< Sectors erase only          */
+#define FLASH_TYPEERASE_MASSERASE       0x00000001U  /*!< Flash Mass erase activation */
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
+  * @{
+  */ 
+#define FLASH_VOLTAGE_RANGE_1        0x00000000U  /*!< Device operating range: 1.8V to 2.1V                */
+#define FLASH_VOLTAGE_RANGE_2        0x00000001U  /*!< Device operating range: 2.1V to 2.7V                */
+#define FLASH_VOLTAGE_RANGE_3        0x00000002U  /*!< Device operating range: 2.7V to 3.6V                */
+#define FLASH_VOLTAGE_RANGE_4        0x00000003U  /*!< Device operating range: 2.7V to 3.6V + External Vpp */
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_WRP_State FLASH WRP State
+  * @{
+  */ 
+#define OB_WRPSTATE_DISABLE       0x00000000U  /*!< Disable the write protection of the desired bank 1 sectors */
+#define OB_WRPSTATE_ENABLE        0x00000001U  /*!< Enable the write protection of the desired bank 1 sectors  */
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_Option_Type FLASH Option Type
+  * @{
+  */ 
+#define OPTIONBYTE_WRP        0x00000001U  /*!< WRP option byte configuration  */
+#define OPTIONBYTE_RDP        0x00000002U  /*!< RDP option byte configuration  */
+#define OPTIONBYTE_USER       0x00000004U  /*!< USER option byte configuration */
+#define OPTIONBYTE_BOR        0x00000008U  /*!< BOR option byte configuration  */
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
+  * @{
+  */
+#define OB_RDP_LEVEL_0   ((uint8_t)0xAA)
+#define OB_RDP_LEVEL_1   ((uint8_t)0x55)
+#define OB_RDP_LEVEL_2   ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2 
+                                              it s no more possible to go back to level 1 or 0 */
+/**
+  * @}
+  */ 
+  
+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
+  * @{
+  */ 
+#define OB_IWDG_SW                     ((uint8_t)0x20)  /*!< Software IWDG selected */
+#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware IWDG selected */
+/**
+  * @}
+  */ 
+  
+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
+  * @{
+  */ 
+#define OB_STOP_NO_RST                 ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP    */
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
+  * @{
+  */ 
+#define OB_STDBY_NO_RST                ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY    */
+/**
+  * @}
+  */    
+
+/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
+  * @{
+  */  
+#define OB_BOR_LEVEL3          ((uint8_t)0x00)  /*!< Supply voltage ranges from 2.70 to 3.60 V */
+#define OB_BOR_LEVEL2          ((uint8_t)0x04)  /*!< Supply voltage ranges from 2.40 to 2.70 V */
+#define OB_BOR_LEVEL1          ((uint8_t)0x08)  /*!< Supply voltage ranges from 2.10 to 2.40 V */
+#define OB_BOR_OFF             ((uint8_t)0x0C)  /*!< Supply voltage ranges from 1.62 to 2.10 V */
+/**
+  * @}
+  */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup FLASHEx_PCROP_State FLASH PCROP State
+  * @{
+  */ 
+#define OB_PCROP_STATE_DISABLE       0x00000000U  /*!< Disable PCROP */
+#define OB_PCROP_STATE_ENABLE        0x00000001U  /*!< Enable PCROP  */
+/**
+  * @}
+  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/** @defgroup FLASHEx_Advanced_Option_Type FLASH Advanced Option Type
+  * @{
+  */ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+#define OPTIONBYTE_PCROP        0x00000001U  /*!< PCROP option byte configuration      */
+#define OPTIONBYTE_BOOTCONFIG   0x00000002U  /*!< BOOTConfig option byte configuration */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+#define OPTIONBYTE_PCROP        0x00000001U  /*!<PCROP option byte configuration */
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+          STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Latency FLASH Latency
+  * @{
+  */
+/*------------------------- STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx ----------------------*/  
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
+#define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
+#define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
+#define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
+#define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
+#define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
+#define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
+#define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
+#define FLASH_LATENCY_8                FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycles    */
+#define FLASH_LATENCY_9                FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycles     */
+#define FLASH_LATENCY_10               FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */
+#define FLASH_LATENCY_11               FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */
+#define FLASH_LATENCY_12               FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */
+#define FLASH_LATENCY_13               FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */
+#define FLASH_LATENCY_14               FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */
+#define FLASH_LATENCY_15               FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/*--------------------------------------------------------------------------------------------------------------*/
+
+/*-------------------------- STM32F40xxx/STM32F41xxx/STM32F401xx/STM32F411xx/STM32F423xx -----------------------*/ 
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+     
+#define FLASH_LATENCY_0                FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */
+#define FLASH_LATENCY_1                FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */
+#define FLASH_LATENCY_2                FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */
+#define FLASH_LATENCY_3                FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */
+#define FLASH_LATENCY_4                FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */
+#define FLASH_LATENCY_5                FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */
+#define FLASH_LATENCY_6                FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */
+#define FLASH_LATENCY_7                FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+          STM32F413xx || STM32F423xx */
+/*--------------------------------------------------------------------------------------------------------------*/
+
+/**
+  * @}
+  */ 
+  
+
+/** @defgroup FLASHEx_Banks FLASH Banks
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+#define FLASH_BANK_1     1U /*!< Bank 1   */
+#define FLASH_BANK_2     2U /*!< Bank 2   */
+#define FLASH_BANK_BOTH  ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+#define FLASH_BANK_1     1U /*!< Bank 1   */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
+          STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */ 
+    
+/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+#define FLASH_MER_BIT     (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits here to clear */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+#define FLASH_MER_BIT     (FLASH_CR_MER) /*!< only 1 MER Bit */
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
+          STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASHEx_Sectors FLASH Sectors
+  * @{
+  */
+/*-------------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx ------------------------------------*/   
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+#define FLASH_SECTOR_0     0U  /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     1U  /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     2U  /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     3U  /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     4U  /*!< Sector Number 4   */
+#define FLASH_SECTOR_5     5U  /*!< Sector Number 5   */
+#define FLASH_SECTOR_6     6U  /*!< Sector Number 6   */
+#define FLASH_SECTOR_7     7U  /*!< Sector Number 7   */
+#define FLASH_SECTOR_8     8U  /*!< Sector Number 8   */
+#define FLASH_SECTOR_9     9U  /*!< Sector Number 9   */
+#define FLASH_SECTOR_10    10U /*!< Sector Number 10  */
+#define FLASH_SECTOR_11    11U /*!< Sector Number 11  */
+#define FLASH_SECTOR_12    12U /*!< Sector Number 12  */
+#define FLASH_SECTOR_13    13U /*!< Sector Number 13  */
+#define FLASH_SECTOR_14    14U /*!< Sector Number 14  */
+#define FLASH_SECTOR_15    15U /*!< Sector Number 15  */
+#define FLASH_SECTOR_16    16U /*!< Sector Number 16  */
+#define FLASH_SECTOR_17    17U /*!< Sector Number 17  */
+#define FLASH_SECTOR_18    18U /*!< Sector Number 18  */
+#define FLASH_SECTOR_19    19U /*!< Sector Number 19  */
+#define FLASH_SECTOR_20    20U /*!< Sector Number 20  */
+#define FLASH_SECTOR_21    21U /*!< Sector Number 21  */
+#define FLASH_SECTOR_22    22U /*!< Sector Number 22  */
+#define FLASH_SECTOR_23    23U /*!< Sector Number 23  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*-------------------------------------- STM32F413xx/STM32F423xx --------------------------------------*/   
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define FLASH_SECTOR_0     0U  /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     1U  /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     2U  /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     3U  /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     4U  /*!< Sector Number 4   */
+#define FLASH_SECTOR_5     5U  /*!< Sector Number 5   */
+#define FLASH_SECTOR_6     6U  /*!< Sector Number 6   */
+#define FLASH_SECTOR_7     7U  /*!< Sector Number 7   */
+#define FLASH_SECTOR_8     8U  /*!< Sector Number 8   */
+#define FLASH_SECTOR_9     9U  /*!< Sector Number 9   */
+#define FLASH_SECTOR_10    10U /*!< Sector Number 10  */
+#define FLASH_SECTOR_11    11U /*!< Sector Number 11  */
+#define FLASH_SECTOR_12    12U /*!< Sector Number 12  */
+#define FLASH_SECTOR_13    13U /*!< Sector Number 13  */
+#define FLASH_SECTOR_14    14U /*!< Sector Number 14  */
+#define FLASH_SECTOR_15    15U /*!< Sector Number 15  */
+#endif /* STM32F413xx || STM32F423xx */
+/*-----------------------------------------------------------------------------------------------------*/      
+
+/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ 
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define FLASH_SECTOR_0     0U  /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     1U  /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     2U  /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     3U  /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     4U  /*!< Sector Number 4   */
+#define FLASH_SECTOR_5     5U  /*!< Sector Number 5   */
+#define FLASH_SECTOR_6     6U  /*!< Sector Number 6   */
+#define FLASH_SECTOR_7     7U  /*!< Sector Number 7   */
+#define FLASH_SECTOR_8     8U  /*!< Sector Number 8   */
+#define FLASH_SECTOR_9     9U  /*!< Sector Number 9   */
+#define FLASH_SECTOR_10    10U /*!< Sector Number 10  */
+#define FLASH_SECTOR_11    11U /*!< Sector Number 11  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------------- STM32F401xC -------------------------------------------*/ 
+#if defined(STM32F401xC)
+#define FLASH_SECTOR_0     0U /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     1U /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     2U /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     3U /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     4U /*!< Sector Number 4   */
+#define FLASH_SECTOR_5     5U /*!< Sector Number 5   */
+#endif /* STM32F401xC */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------------- STM32F410xx -------------------------------------------*/ 
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define FLASH_SECTOR_0     0U /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     1U /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     2U /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     3U /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     4U /*!< Sector Number 4   */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define FLASH_SECTOR_0     0U /*!< Sector Number 0   */
+#define FLASH_SECTOR_1     1U /*!< Sector Number 1   */
+#define FLASH_SECTOR_2     2U /*!< Sector Number 2   */
+#define FLASH_SECTOR_3     3U /*!< Sector Number 3   */
+#define FLASH_SECTOR_4     4U /*!< Sector Number 4   */
+#define FLASH_SECTOR_5     5U /*!< Sector Number 5   */
+#define FLASH_SECTOR_6     6U /*!< Sector Number 6   */
+#define FLASH_SECTOR_7     7U /*!< Sector Number 7   */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
+  * @{
+  */
+/*--------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx -------------------------*/  
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx) 
+#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */
+#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */
+#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */
+#define OB_WRP_SECTOR_8       0x00000100U /*!< Write protection of Sector8     */
+#define OB_WRP_SECTOR_9       0x00000200U /*!< Write protection of Sector9     */
+#define OB_WRP_SECTOR_10      0x00000400U /*!< Write protection of Sector10    */
+#define OB_WRP_SECTOR_11      0x00000800U /*!< Write protection of Sector11    */
+#define OB_WRP_SECTOR_12      0x00000001U << 12U /*!< Write protection of Sector12    */
+#define OB_WRP_SECTOR_13      0x00000002U << 12U /*!< Write protection of Sector13    */
+#define OB_WRP_SECTOR_14      0x00000004U << 12U /*!< Write protection of Sector14    */
+#define OB_WRP_SECTOR_15      0x00000008U << 12U /*!< Write protection of Sector15    */
+#define OB_WRP_SECTOR_16      0x00000010U << 12U /*!< Write protection of Sector16    */
+#define OB_WRP_SECTOR_17      0x00000020U << 12U /*!< Write protection of Sector17    */
+#define OB_WRP_SECTOR_18      0x00000040U << 12U /*!< Write protection of Sector18    */
+#define OB_WRP_SECTOR_19      0x00000080U << 12U /*!< Write protection of Sector19    */
+#define OB_WRP_SECTOR_20      0x00000100U << 12U /*!< Write protection of Sector20    */
+#define OB_WRP_SECTOR_21      0x00000200U << 12U /*!< Write protection of Sector21    */
+#define OB_WRP_SECTOR_22      0x00000400U << 12U /*!< Write protection of Sector22    */
+#define OB_WRP_SECTOR_23      0x00000800U << 12U /*!< Write protection of Sector23    */
+#define OB_WRP_SECTOR_All     0x00000FFFU << 12U /*!< Write protection of all Sectors */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------- STM32F413xx/STM32F423xx -------------------------------------*/ 
+#if defined(STM32F413xx) || defined(STM32F423xx)  
+#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */
+#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */
+#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */
+#define OB_WRP_SECTOR_8       0x00000100U /*!< Write protection of Sector8     */
+#define OB_WRP_SECTOR_9       0x00000200U /*!< Write protection of Sector9     */
+#define OB_WRP_SECTOR_10      0x00000400U /*!< Write protection of Sector10    */
+#define OB_WRP_SECTOR_11      0x00000800U /*!< Write protection of Sector11    */
+#define OB_WRP_SECTOR_12      0x00001000U /*!< Write protection of Sector12    */
+#define OB_WRP_SECTOR_13      0x00002000U /*!< Write protection of Sector13    */
+#define OB_WRP_SECTOR_14      0x00004000U /*!< Write protection of Sector14    */
+#define OB_WRP_SECTOR_15      0x00004000U /*!< Write protection of Sector15    */      
+#define OB_WRP_SECTOR_All     0x00007FFFU /*!< Write protection of all Sectors */
+#endif /* STM32F413xx || STM32F423xx */
+/*-----------------------------------------------------------------------------------------------------*/    
+      
+/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ 
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */
+#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */
+#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */
+#define OB_WRP_SECTOR_8       0x00000100U /*!< Write protection of Sector8     */
+#define OB_WRP_SECTOR_9       0x00000200U /*!< Write protection of Sector9     */
+#define OB_WRP_SECTOR_10      0x00000400U /*!< Write protection of Sector10    */
+#define OB_WRP_SECTOR_11      0x00000800U /*!< Write protection of Sector11    */
+#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------------- STM32F401xC -------------------------------------------*/
+#if defined(STM32F401xC)
+#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */
+#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */
+#endif /* STM32F401xC */
+/*-----------------------------------------------------------------------------------------------------*/
+ 
+/*--------------------------------------------- STM32F410xx -------------------------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F401xE/STM32F411xE/STM32F446xx ------------------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
+#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
+#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
+#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
+#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
+#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */
+#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */
+#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */
+#define OB_WRP_SECTOR_All     0x00000FFFU /*!< Write protection of all Sectors */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+/*-----------------------------------------------------------------------------------------------------*/
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection FLASH Option Bytes PC ReadWrite Protection
+  * @{
+  */
+/*-------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx ---------------------------*/   
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx) 
+#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */
+#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */
+#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */
+#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */
+#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */
+#define OB_PCROP_SECTOR_5        0x00000020U /*!< PC Read/Write protection of Sector5      */
+#define OB_PCROP_SECTOR_6        0x00000040U /*!< PC Read/Write protection of Sector6      */
+#define OB_PCROP_SECTOR_7        0x00000080U /*!< PC Read/Write protection of Sector7      */
+#define OB_PCROP_SECTOR_8        0x00000100U /*!< PC Read/Write protection of Sector8      */
+#define OB_PCROP_SECTOR_9        0x00000200U /*!< PC Read/Write protection of Sector9      */
+#define OB_PCROP_SECTOR_10       0x00000400U /*!< PC Read/Write protection of Sector10     */
+#define OB_PCROP_SECTOR_11       0x00000800U /*!< PC Read/Write protection of Sector11     */
+#define OB_PCROP_SECTOR_12       0x00000001U /*!< PC Read/Write protection of Sector12     */
+#define OB_PCROP_SECTOR_13       0x00000002U /*!< PC Read/Write protection of Sector13     */
+#define OB_PCROP_SECTOR_14       0x00000004U /*!< PC Read/Write protection of Sector14     */
+#define OB_PCROP_SECTOR_15       0x00000008U /*!< PC Read/Write protection of Sector15     */
+#define OB_PCROP_SECTOR_16       0x00000010U /*!< PC Read/Write protection of Sector16     */
+#define OB_PCROP_SECTOR_17       0x00000020U /*!< PC Read/Write protection of Sector17     */
+#define OB_PCROP_SECTOR_18       0x00000040U /*!< PC Read/Write protection of Sector18     */
+#define OB_PCROP_SECTOR_19       0x00000080U /*!< PC Read/Write protection of Sector19     */
+#define OB_PCROP_SECTOR_20       0x00000100U /*!< PC Read/Write protection of Sector20     */
+#define OB_PCROP_SECTOR_21       0x00000200U /*!< PC Read/Write protection of Sector21     */
+#define OB_PCROP_SECTOR_22       0x00000400U /*!< PC Read/Write protection of Sector22     */
+#define OB_PCROP_SECTOR_23       0x00000800U /*!< PC Read/Write protection of Sector23     */
+#define OB_PCROP_SECTOR_All      0x00000FFFU /*!< PC Read/Write protection of all Sectors  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/*-----------------------------------------------------------------------------------------------------*/
+      
+/*------------------------------------- STM32F413xx/STM32F423xx ---------------------------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)  
+#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */
+#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */
+#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */
+#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */
+#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */
+#define OB_PCROP_SECTOR_5        0x00000020U /*!< PC Read/Write protection of Sector5      */
+#define OB_PCROP_SECTOR_6        0x00000040U /*!< PC Read/Write protection of Sector6      */
+#define OB_PCROP_SECTOR_7        0x00000080U /*!< PC Read/Write protection of Sector7      */
+#define OB_PCROP_SECTOR_8        0x00000100U /*!< PC Read/Write protection of Sector8      */
+#define OB_PCROP_SECTOR_9        0x00000200U /*!< PC Read/Write protection of Sector9      */
+#define OB_PCROP_SECTOR_10       0x00000400U /*!< PC Read/Write protection of Sector10     */
+#define OB_PCROP_SECTOR_11       0x00000800U /*!< PC Read/Write protection of Sector11     */
+#define OB_PCROP_SECTOR_12       0x00001000U /*!< PC Read/Write protection of Sector12     */
+#define OB_PCROP_SECTOR_13       0x00002000U /*!< PC Read/Write protection of Sector13     */
+#define OB_PCROP_SECTOR_14       0x00004000U /*!< PC Read/Write protection of Sector14     */
+#define OB_PCROP_SECTOR_15       0x00004000U /*!< PC Read/Write protection of Sector15     */      
+#define OB_PCROP_SECTOR_All      0x00007FFFU /*!< PC Read/Write protection of all Sectors  */
+#endif /* STM32F413xx || STM32F423xx */
+/*-----------------------------------------------------------------------------------------------------*/      
+
+/*--------------------------------------------- STM32F401xC -------------------------------------------*/
+#if defined(STM32F401xC)
+#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */
+#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */
+#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */
+#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */
+#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */
+#define OB_PCROP_SECTOR_5        0x00000020U /*!< PC Read/Write protection of Sector5      */
+#define OB_PCROP_SECTOR_All      0x00000FFFU /*!< PC Read/Write protection of all Sectors  */
+#endif /* STM32F401xC */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*--------------------------------------------- STM32F410xx -------------------------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */
+#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */
+#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */
+#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */
+#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */
+#define OB_PCROP_SECTOR_All      0x00000FFFU /*!< PC Read/Write protection of all Sectors  */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/*-------------- STM32F401xE/STM32F411xE/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F446xx --*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define OB_PCROP_SECTOR_0        0x00000001U /*!< PC Read/Write protection of Sector0      */
+#define OB_PCROP_SECTOR_1        0x00000002U /*!< PC Read/Write protection of Sector1      */
+#define OB_PCROP_SECTOR_2        0x00000004U /*!< PC Read/Write protection of Sector2      */
+#define OB_PCROP_SECTOR_3        0x00000008U /*!< PC Read/Write protection of Sector3      */
+#define OB_PCROP_SECTOR_4        0x00000010U /*!< PC Read/Write protection of Sector4      */
+#define OB_PCROP_SECTOR_5        0x00000020U /*!< PC Read/Write protection of Sector5      */
+#define OB_PCROP_SECTOR_6        0x00000040U /*!< PC Read/Write protection of Sector6      */
+#define OB_PCROP_SECTOR_7        0x00000080U /*!< PC Read/Write protection of Sector7      */
+#define OB_PCROP_SECTOR_All      0x00000FFFU /*!< PC Read/Write protection of all Sectors  */
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*-----------------------------------------------------------------------------------------------------*/
+
+/**
+  * @}
+  */
+  
+/** @defgroup FLASHEx_Dual_Boot FLASH Dual Boot
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx) 
+#define OB_DUAL_BOOT_ENABLE   ((uint8_t)0x10) /*!< Dual Bank Boot Enable                             */
+#define OB_DUAL_BOOT_DISABLE  ((uint8_t)0x00) /*!< Dual Bank Boot Disable, always boot on User Flash */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/** @defgroup  FLASHEx_Selection_Protection_Mode FLASH Selection Protection Mode
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define OB_PCROP_DESELECTED     ((uint8_t)0x00) /*!< Disabled PcROP, nWPRi bits used for Write Protection on sector i */
+#define OB_PCROP_SELECTED       ((uint8_t)0x80) /*!< Enable PcROP, nWPRi bits used for PCRoP Protection on sector i   */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASHEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+  * @{
+  */
+/* Extension Program operation functions  *************************************/
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
+void              HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
+HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
+HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+uint16_t          HAL_FLASHEx_OB_GetBank2WRP(void);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Constants FLASH Private Constants
+  * @{
+  */
+/*--------------------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx---------------------*/ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define FLASH_SECTOR_TOTAL  24U
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+/*-------------------------------------- STM32F413xx/STM32F423xx ---------------------------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define FLASH_SECTOR_TOTAL  16U
+#endif /* STM32F413xx || STM32F423xx */
+
+/*--------------------------------------- STM32F40xxx/STM32F41xxx -------------------------------------*/ 
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define FLASH_SECTOR_TOTAL  12U
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+/*--------------------------------------------- STM32F401xC -------------------------------------------*/ 
+#if defined(STM32F401xC)
+#define FLASH_SECTOR_TOTAL  6U
+#endif /* STM32F401xC */
+
+/*--------------------------------------------- STM32F410xx -------------------------------------------*/ 
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define FLASH_SECTOR_TOTAL  5U
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/*--------------------------------- STM32F401xE/STM32F411xE/STM32F412xG/STM32F446xx -------------------*/
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define FLASH_SECTOR_TOTAL  8U
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+
+/** 
+  * @brief OPTCR1 register byte 2 (Bits[23:16]) base address  
+  */ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)  
+#define OPTCR1_BYTE2_ADDRESS         0x40023C1AU
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
+  * @{
+  */
+
+/** @defgroup FLASHEx_IS_FLASH_Definitions FLASH Private macros to check input parameters
+  * @{
+  */
+
+#define IS_FLASH_TYPEERASE(VALUE)(((VALUE) == FLASH_TYPEERASE_SECTORS) || \
+                                  ((VALUE) == FLASH_TYPEERASE_MASSERASE))  
+
+#define IS_VOLTAGERANGE(RANGE)(((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
+                               ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
+                               ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
+                               ((RANGE) == FLASH_VOLTAGE_RANGE_4))  
+
+#define IS_WRPSTATE(VALUE)(((VALUE) == OB_WRPSTATE_DISABLE) || \
+                           ((VALUE) == OB_WRPSTATE_ENABLE))  
+
+#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
+
+#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
+                                ((LEVEL) == OB_RDP_LEVEL_1) ||\
+                                ((LEVEL) == OB_RDP_LEVEL_2))
+
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+
+#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
+                                ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) || \
+                             ((VALUE) == OB_PCROP_STATE_ENABLE))  
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP) || \
+                       ((VALUE) == OPTIONBYTE_BOOTCONFIG))  
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+#define IS_OBEX(VALUE)(((VALUE) == OPTIONBYTE_PCROP))  
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+  
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
+                                   ((LATENCY) == FLASH_LATENCY_1)  || \
+                                   ((LATENCY) == FLASH_LATENCY_2)  || \
+                                   ((LATENCY) == FLASH_LATENCY_3)  || \
+                                   ((LATENCY) == FLASH_LATENCY_4)  || \
+                                   ((LATENCY) == FLASH_LATENCY_5)  || \
+                                   ((LATENCY) == FLASH_LATENCY_6)  || \
+                                   ((LATENCY) == FLASH_LATENCY_7)  || \
+                                   ((LATENCY) == FLASH_LATENCY_8)  || \
+                                   ((LATENCY) == FLASH_LATENCY_9)  || \
+                                   ((LATENCY) == FLASH_LATENCY_10) || \
+                                   ((LATENCY) == FLASH_LATENCY_11) || \
+                                   ((LATENCY) == FLASH_LATENCY_12) || \
+                                   ((LATENCY) == FLASH_LATENCY_13) || \
+                                   ((LATENCY) == FLASH_LATENCY_14) || \
+                                   ((LATENCY) == FLASH_LATENCY_15))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
+                                   ((LATENCY) == FLASH_LATENCY_1)  || \
+                                   ((LATENCY) == FLASH_LATENCY_2)  || \
+                                   ((LATENCY) == FLASH_LATENCY_3)  || \
+                                   ((LATENCY) == FLASH_LATENCY_4)  || \
+                                   ((LATENCY) == FLASH_LATENCY_5)  || \
+                                   ((LATENCY) == FLASH_LATENCY_6)  || \
+                                   ((LATENCY) == FLASH_LATENCY_7))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Vx ||\
+          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1)  || \
+                             ((BANK) == FLASH_BANK_2)  || \
+                             ((BANK) == FLASH_BANK_BOTH))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx ||\
+          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+ 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_12)  || ((SECTOR) == FLASH_SECTOR_13)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_14)  || ((SECTOR) == FLASH_SECTOR_15)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_16)  || ((SECTOR) == FLASH_SECTOR_17)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_18)  || ((SECTOR) == FLASH_SECTOR_19)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_20)  || ((SECTOR) == FLASH_SECTOR_21)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_22)  || ((SECTOR) == FLASH_SECTOR_23))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_FLASH_SECTOR(SECTOR) ( ((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
+                                  ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_12)  || ((SECTOR) == FLASH_SECTOR_13)  ||\
+                                  ((SECTOR) == FLASH_SECTOR_14)  || ((SECTOR) == FLASH_SECTOR_15))
+#endif /* STM32F413xx || STM32F423xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_8)   || ((SECTOR) == FLASH_SECTOR_9)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_10)  || ((SECTOR) == FLASH_SECTOR_11))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F401xC)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5))
+#endif /* STM32F401xC */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_4))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
+#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
+                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx */
+
+#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
+                                   (((ADDRESS) >= FLASH_OTP_BASE) && ((ADDRESS) <= FLASH_OTP_END)))
+
+#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
+  
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFF000000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F413xx) || defined(STM32F423xx) 
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F413xx || STM32F423xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F401xC */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+    defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define IS_OB_WRP_SECTOR(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+   
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFF8000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))      
+#endif /* STM32F413xx || STM32F423xx */
+
+#if defined(STM32F401xC)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F401xC */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+    defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define IS_OB_PCROP(SECTOR)((((SECTOR) & 0xFFFFF000U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#endif /* STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx) 
+#define IS_OB_BOOT(BOOT) (((BOOT) == OB_DUAL_BOOT_ENABLE) || ((BOOT) == OB_DUAL_BOOT_DISABLE))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_OB_PCROP_SELECT(PCROP) (((PCROP) == OB_PCROP_SELECTED) || ((PCROP) == OB_PCROP_DESELECTED))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASH Private Functions
+  * @{
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange);
+void FLASH_FlushCaches(void);
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_FLASH_EX_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h
index 05917ec..b4d5f60 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h
@@ -1,76 +1,76 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_flash_ramfunc.h
-  * @author  MCD Application Team
-  * @brief   Header file of FLASH RAMFUNC driver.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_FLASH_RAMFUNC_H
-#define __STM32F4xx_FLASH_RAMFUNC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH_RAMFUNC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
-  * @{
-  */   
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void);
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void);
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void);
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void);
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */  
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F4xx_FLASH_RAMFUNC_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_flash_ramfunc.h
+  * @author  MCD Application Team
+  * @brief   Header file of FLASH RAMFUNC driver.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_FLASH_RAMFUNC_H
+#define __STM32F4xx_FLASH_RAMFUNC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH_RAMFUNC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
+  * @{
+  */   
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void);
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void);
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void);
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void);
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_FLASH_RAMFUNC_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h
index 5f3d749..661400f 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h
@@ -1,325 +1,325 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_gpio.h
-  * @author  MCD Application Team
-  * @brief   Header file of GPIO HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_GPIO_H
-#define __STM32F4xx_HAL_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup GPIO
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Types GPIO Exported Types
-  * @{
-  */
-
-/** 
-  * @brief GPIO Init structure definition  
-  */ 
-typedef struct
-{
-  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
-                           This parameter can be any value of @ref GPIO_pins_define */
-
-  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref GPIO_mode_define */
-
-  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
-                           This parameter can be a value of @ref GPIO_pull_define */
-
-  uint32_t Speed;     /*!< Specifies the speed for the selected pins.
-                           This parameter can be a value of @ref GPIO_speed_define */
-
-  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins. 
-                            This parameter can be a value of @ref GPIO_Alternate_function_selection */
-}GPIO_InitTypeDef;
-
-/** 
-  * @brief  GPIO Bit SET and Bit RESET enumeration 
-  */
-typedef enum
-{
-  GPIO_PIN_RESET = 0,
-  GPIO_PIN_SET
-}GPIO_PinState;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
-  * @{
-  */ 
-
-/** @defgroup GPIO_pins_define GPIO pins define
-  * @{
-  */
-#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
-#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
-#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
-#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
-#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
-#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
-#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
-#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
-#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
-#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
-#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
-#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
-#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
-#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
-#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
-#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
-#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
-
-#define GPIO_PIN_MASK              0x0000FFFFU /* PIN mask for assert test */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_mode_define GPIO mode define
-  * @brief GPIO Configuration Mode
-  *        Elements values convention: 0x00WX00YZ
-  *           - W  : EXTI trigger detection on 3 bits
-  *           - X  : EXTI mode (IT or Event) on 2 bits
-  *           - Y  : Output type (Push Pull or Open Drain) on 1 bit
-  *           - Z  : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
-  * @{
-  */ 
-#define  GPIO_MODE_INPUT                        MODE_INPUT                                                  /*!< Input Floating Mode                   */
-#define  GPIO_MODE_OUTPUT_PP                    (MODE_OUTPUT | OUTPUT_PP)                                   /*!< Output Push Pull Mode                 */
-#define  GPIO_MODE_OUTPUT_OD                    (MODE_OUTPUT | OUTPUT_OD)                                   /*!< Output Open Drain Mode                */
-#define  GPIO_MODE_AF_PP                        (MODE_AF | OUTPUT_PP)                                       /*!< Alternate Function Push Pull Mode     */
-#define  GPIO_MODE_AF_OD                        (MODE_AF | OUTPUT_OD)                                       /*!< Alternate Function Open Drain Mode    */
-
-#define  GPIO_MODE_ANALOG                       MODE_ANALOG                                                 /*!< Analog Mode  */
-    
-#define  GPIO_MODE_IT_RISING                    (MODE_INPUT | EXTI_IT | TRIGGER_RISING)                     /*!< External Interrupt Mode with Rising edge trigger detection          */
-#define  GPIO_MODE_IT_FALLING                   (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)                    /*!< External Interrupt Mode with Falling edge trigger detection         */
-#define  GPIO_MODE_IT_RISING_FALLING            (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
- 
-#define  GPIO_MODE_EVT_RISING                   (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)                     /*!< External Event Mode with Rising edge trigger detection             */
-#define  GPIO_MODE_EVT_FALLING                  (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)                    /*!< External Event Mode with Falling edge trigger detection            */
-#define  GPIO_MODE_EVT_RISING_FALLING           (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Event Mode with Rising/Falling edge trigger detection     */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_speed_define  GPIO speed define
-  * @brief GPIO Output Maximum frequency
-  * @{
-  */
-#define  GPIO_SPEED_FREQ_LOW         0x00000000U  /*!< IO works at 2 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_MEDIUM      0x00000001U  /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
-#define  GPIO_SPEED_FREQ_HIGH        0x00000002U  /*!< range 25 MHz to 100 MHz, please refer to the product datasheet  */
-#define  GPIO_SPEED_FREQ_VERY_HIGH   0x00000003U  /*!< range 50 MHz to 200 MHz, please refer to the product datasheet  */
-/**
-  * @}
-  */
-
- /** @defgroup GPIO_pull_define GPIO pull define
-   * @brief GPIO Pull-Up or Pull-Down Activation
-   * @{
-   */  
-#define  GPIO_NOPULL        0x00000000U   /*!< No Pull-up or Pull-down activation  */
-#define  GPIO_PULLUP        0x00000001U   /*!< Pull-up activation                  */
-#define  GPIO_PULLDOWN      0x00000002U   /*!< Pull-down activation                */
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Checks whether the specified EXTI line flag is set or not.
-  * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
-  *         This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
-/**
-  * @brief  Clears the EXTI's line pending flags.
-  * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.
-  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
-  * @brief  Checks whether the specified EXTI line is asserted or not.
-  * @param  __EXTI_LINE__ specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
-
-/**
-  * @brief  Clears the EXTI's line pending bits.
-  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
-  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
-  * @brief  Generates a Software interrupt on selected EXTI line.
-  * @param  __EXTI_LINE__ specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
-/**
-  * @}
-  */
-
-/* Include GPIO HAL Extension module */
-#include "stm32f4xx_hal_gpio_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup GPIO_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup GPIO_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/
-void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
-void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
-/**
-  * @}
-  */
-
-/** @addtogroup GPIO_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *****************************************************/
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup GPIO_Private_Constants GPIO Private Constants
-  * @{
-  */
-#define GPIO_MODE_Pos                           0U
-#define GPIO_MODE                               (0x3UL << GPIO_MODE_Pos)
-#define MODE_INPUT                              (0x0UL << GPIO_MODE_Pos)
-#define MODE_OUTPUT                             (0x1UL << GPIO_MODE_Pos)
-#define MODE_AF                                 (0x2UL << GPIO_MODE_Pos)
-#define MODE_ANALOG                             (0x3UL << GPIO_MODE_Pos)
-#define OUTPUT_TYPE_Pos                         4U
-#define OUTPUT_TYPE                             (0x1UL << OUTPUT_TYPE_Pos)
-#define OUTPUT_PP                               (0x0UL << OUTPUT_TYPE_Pos)
-#define OUTPUT_OD                               (0x1UL << OUTPUT_TYPE_Pos)
-#define EXTI_MODE_Pos                           16U
-#define EXTI_MODE                               (0x3UL << EXTI_MODE_Pos)
-#define EXTI_IT                                 (0x1UL << EXTI_MODE_Pos)
-#define EXTI_EVT                                (0x2UL << EXTI_MODE_Pos)
-#define TRIGGER_MODE_Pos                         20U
-#define TRIGGER_MODE                            (0x7UL << TRIGGER_MODE_Pos)
-#define TRIGGER_RISING                          (0x1UL << TRIGGER_MODE_Pos)
-#define TRIGGER_FALLING                         (0x2UL << TRIGGER_MODE_Pos)
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIO_Private_Macros GPIO Private Macros
-  * @{
-  */
-#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-#define IS_GPIO_PIN(PIN)           (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
-                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
-                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
-                            ((MODE) == GPIO_MODE_AF_PP)              ||\
-                            ((MODE) == GPIO_MODE_AF_OD)              ||\
-                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
-                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
-                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
-                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
-                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
-                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
-                            ((MODE) == GPIO_MODE_ANALOG))
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
-                              ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
-#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
-                            ((PULL) == GPIO_PULLDOWN))
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup GPIO_Private_Functions GPIO Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_GPIO_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_GPIO_H
+#define __STM32F4xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+  * @{
+  */
+
+/** 
+  * @brief GPIO Init structure definition  
+  */ 
+typedef struct
+{
+  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
+                           This parameter can be any value of @ref GPIO_pins_define */
+
+  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref GPIO_mode_define */
+
+  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                           This parameter can be a value of @ref GPIO_pull_define */
+
+  uint32_t Speed;     /*!< Specifies the speed for the selected pins.
+                           This parameter can be a value of @ref GPIO_speed_define */
+
+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins. 
+                            This parameter can be a value of @ref GPIO_Alternate_function_selection */
+}GPIO_InitTypeDef;
+
+/** 
+  * @brief  GPIO Bit SET and Bit RESET enumeration 
+  */
+typedef enum
+{
+  GPIO_PIN_RESET = 0,
+  GPIO_PIN_SET
+}GPIO_PinState;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * @{
+  */ 
+
+/** @defgroup GPIO_pins_define GPIO pins define
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
+#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define GPIO_PIN_MASK              0x0000FFFFU /* PIN mask for assert test */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_mode_define GPIO mode define
+  * @brief GPIO Configuration Mode
+  *        Elements values convention: 0x00WX00YZ
+  *           - W  : EXTI trigger detection on 3 bits
+  *           - X  : EXTI mode (IT or Event) on 2 bits
+  *           - Y  : Output type (Push Pull or Open Drain) on 1 bit
+  *           - Z  : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
+  * @{
+  */ 
+#define  GPIO_MODE_INPUT                        MODE_INPUT                                                  /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                    (MODE_OUTPUT | OUTPUT_PP)                                   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                    (MODE_OUTPUT | OUTPUT_OD)                                   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                        (MODE_AF | OUTPUT_PP)                                       /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                        (MODE_AF | OUTPUT_OD)                                       /*!< Alternate Function Open Drain Mode    */
+
+#define  GPIO_MODE_ANALOG                       MODE_ANALOG                                                 /*!< Analog Mode  */
+    
+#define  GPIO_MODE_IT_RISING                    (MODE_INPUT | EXTI_IT | TRIGGER_RISING)                     /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING                   (MODE_INPUT | EXTI_IT | TRIGGER_FALLING)                    /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING            (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+ 
+#define  GPIO_MODE_EVT_RISING                   (MODE_INPUT | EXTI_EVT | TRIGGER_RISING)                     /*!< External Event Mode with Rising edge trigger detection             */
+#define  GPIO_MODE_EVT_FALLING                  (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING)                    /*!< External Event Mode with Falling edge trigger detection            */
+#define  GPIO_MODE_EVT_RISING_FALLING           (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING)   /*!< External Event Mode with Rising/Falling edge trigger detection     */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_speed_define  GPIO speed define
+  * @brief GPIO Output Maximum frequency
+  * @{
+  */
+#define  GPIO_SPEED_FREQ_LOW         0x00000000U  /*!< IO works at 2 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_MEDIUM      0x00000001U  /*!< range 12,5 MHz to 50 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_HIGH        0x00000002U  /*!< range 25 MHz to 100 MHz, please refer to the product datasheet  */
+#define  GPIO_SPEED_FREQ_VERY_HIGH   0x00000003U  /*!< range 50 MHz to 200 MHz, please refer to the product datasheet  */
+/**
+  * @}
+  */
+
+ /** @defgroup GPIO_pull_define GPIO pull define
+   * @brief GPIO Pull-Up or Pull-Down Activation
+   * @{
+   */  
+#define  GPIO_NOPULL        0x00000000U   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        0x00000001U   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      0x00000002U   /*!< Pull-down activation                */
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
+/**
+  * @}
+  */
+
+/* Include GPIO HAL Extension module */
+#include "stm32f4xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GPIO_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
+/**
+  * @}
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+#define GPIO_MODE_Pos                           0U
+#define GPIO_MODE                               (0x3UL << GPIO_MODE_Pos)
+#define MODE_INPUT                              (0x0UL << GPIO_MODE_Pos)
+#define MODE_OUTPUT                             (0x1UL << GPIO_MODE_Pos)
+#define MODE_AF                                 (0x2UL << GPIO_MODE_Pos)
+#define MODE_ANALOG                             (0x3UL << GPIO_MODE_Pos)
+#define OUTPUT_TYPE_Pos                         4U
+#define OUTPUT_TYPE                             (0x1UL << OUTPUT_TYPE_Pos)
+#define OUTPUT_PP                               (0x0UL << OUTPUT_TYPE_Pos)
+#define OUTPUT_OD                               (0x1UL << OUTPUT_TYPE_Pos)
+#define EXTI_MODE_Pos                           16U
+#define EXTI_MODE                               (0x3UL << EXTI_MODE_Pos)
+#define EXTI_IT                                 (0x1UL << EXTI_MODE_Pos)
+#define EXTI_EVT                                (0x2UL << EXTI_MODE_Pos)
+#define TRIGGER_MODE_Pos                         20U
+#define TRIGGER_MODE                            (0x7UL << TRIGGER_MODE_Pos)
+#define TRIGGER_RISING                          (0x1UL << TRIGGER_MODE_Pos)
+#define TRIGGER_FALLING                         (0x2UL << TRIGGER_MODE_Pos)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+  * @{
+  */
+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+#define IS_GPIO_PIN(PIN)           (((((uint32_t)PIN) & GPIO_PIN_MASK ) != 0x00U) && ((((uint32_t)PIN) & ~GPIO_PIN_MASK) == 0x00U))
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
+                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
+                            ((MODE) == GPIO_MODE_AF_PP)              ||\
+                            ((MODE) == GPIO_MODE_AF_OD)              ||\
+                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
+                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
+                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
+                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
+                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
+                            ((MODE) == GPIO_MODE_ANALOG))
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \
+                              ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))
+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
+                            ((PULL) == GPIO_PULLDOWN))
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIO_Private_Functions GPIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_GPIO_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h
index 5e0b7cc..393f388 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h
@@ -1,1590 +1,1590 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_gpio_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of GPIO HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_GPIO_EX_H
-#define __STM32F4xx_HAL_GPIO_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIOEx GPIOEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
-  * @{
-  */
-  
-/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
-  * @{
-  */
-
-/*------------------------------------------ STM32F429xx/STM32F439xx ---------*/
-#if defined(STM32F429xx) || defined(STM32F439xx)
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
-#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
-#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping        */
-#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping        */
-#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
-#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
-#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */
-#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
-#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping    */
-#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */
-#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
-#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LCD-TFT Alternate Function mapping */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
-
-/** 
-  * @brief   AF 11 selection  
-  */ 
-#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping                      */
-#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
-
-/** 
-  * @brief   AF 13 selection  
-  */ 
-#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
-
-/** 
-  * @brief   AF 14 selection  
-  */
-#define GPIO_AF14_LTDC          ((uint8_t)0x0E)  /* LCD-TFT Alternate Function mapping */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F429xx || STM32F439xx */
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F427xx/STM32F437xx------------------*/
-#if defined(STM32F427xx) || defined(STM32F437xx)
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
-#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
-#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping        */
-#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping        */
-/** @brief  GPIO_Legacy 
-  */
-#define GPIO_AF5_I2S3ext       GPIO_AF5_SPI3   /* I2S3ext_SD Alternate Function mapping  */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
-#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
-#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */
-#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
-#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
-#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
-#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
-
-/** 
-  * @brief   AF 11 selection  
-  */ 
-#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping                      */
-#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
-
-/** 
-  * @brief   AF 13 selection  
-  */ 
-#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F427xx || STM32F437xx */
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F407xx/STM32F417xx------------------*/
-#if defined(STM32F407xx) || defined(STM32F417xx)
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
-#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
-#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
-#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
-
-/** 
-  * @brief   AF 11 selection  
-  */ 
-#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FSMC Alternate Function mapping                     */
-#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
-
-/** 
-  * @brief   AF 13 selection  
-  */ 
-#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F407xx || STM32F417xx */
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F405xx/STM32F415xx------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx)
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
-#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
-#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
-#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FSMC Alternate Function mapping                     */
-#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F405xx || STM32F415xx */
-
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------------- STM32F401xx------------------------*/
-#if defined(STM32F401xC) || defined(STM32F401xE) 
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3 Alternate Function mapping        */
-#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
-#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping  */
-#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping  */
-
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping  */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F401xC || STM32F401xE */
-/*----------------------------------------------------------------------------*/
-
-/*--------------- STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-------------*/
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)   
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping    */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping    */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping    */
-#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04)  /* FMPI2C1 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
-#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4/I2S4 Alternate Function mapping   */
-#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
-
-/** 
-  * @brief   AF 6 selection  
-  */
-#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* I2S2 Alternate Function mapping       */
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /* SPI4/I2S4 Alternate Function mapping  */
-#define GPIO_AF6_SPI5          ((uint8_t)0x06)  /* SPI5/I2S5 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
-#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping     */
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
-#define GPIO_AF8_USART3        ((uint8_t)0x08)  /* USART3 Alternate Function mapping */
-#define GPIO_AF8_DFSDM1        ((uint8_t)0x08)  /* DFSDM1 Alternate Function mapping */
-#define GPIO_AF8_CAN1          ((uint8_t)0x08)  /* CAN1 Alternate Function mapping   */
-
-/** 
-  * @brief   AF 9 selection 
-  */
-#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */
-#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
-#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping    */
-#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping    */
-#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09)  /* FMPI2C1 Alternate Function mapping */
-#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
-#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */  
-#define GPIO_AF9_QSPI          ((uint8_t)0x09)  /* QSPI Alternate Function mapping    */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_DFSDM1        ((uint8_t)0x0A)  /* DFSDM1 Alternate Function mapping */
-#define GPIO_AF10_QSPI          ((uint8_t)0x0A)  /* QSPI Alternate Function mapping   */
-#define GPIO_AF10_FMC           ((uint8_t)0x0A)  /* FMC Alternate Function mapping    */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping  */
-#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping   */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-/*----------------------------------------------------------------------------*/
-
-/*--------------- STM32F413xx/STM32F423xx-------------------------------------*/
-#if defined(STM32F413xx) || defined(STM32F423xx)   
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
-#define GPIO_AF3_DFSDM2        ((uint8_t)0x03)  /* DFSDM2 Alternate Function mapping */   
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping    */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping    */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping    */
-#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04)  /* FMPI2C1 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
-#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4/I2S4 Alternate Function mapping   */
-#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
-
-/** 
-  * @brief   AF 6 selection  
-  */
-#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* I2S2 Alternate Function mapping       */
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /* SPI4/I2S4 Alternate Function mapping  */
-#define GPIO_AF6_SPI5          ((uint8_t)0x06)  /* SPI5/I2S5 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
-#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping     */
-#define GPIO_AF6_DFSDM2        ((uint8_t)0x06)  /* DFSDM2 Alternate Function mapping     */   
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF7_SAI1          ((uint8_t)0x07)  /* SAI1 Alternate Function mapping       */
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
-#define GPIO_AF7_DFSDM2        ((uint8_t)0x07)  /* DFSDM2 Alternate Function mapping     */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
-#define GPIO_AF8_USART3        ((uint8_t)0x08)  /* USART3 Alternate Function mapping */
-#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
-#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
-#define GPIO_AF8_DFSDM1        ((uint8_t)0x08)  /* DFSDM1 Alternate Function mapping */
-#define GPIO_AF8_CAN1          ((uint8_t)0x08)  /* CAN1 Alternate Function mapping   */
-
-/** 
-  * @brief   AF 9 selection 
-  */
-#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */
-#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
-#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping    */
-#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping    */
-#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09)  /* FMPI2C1 Alternate Function mapping */
-#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
-#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
-#define GPIO_AF9_QSPI          ((uint8_t)0x09)  /* QSPI Alternate Function mapping    */
-
-/** 
-  * @brief   AF 10 selection  
-  */
-#define GPIO_AF10_SAI1          ((uint8_t)0x0A)  /* SAI1 Alternate Function mapping   */
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_DFSDM1        ((uint8_t)0x0A)  /* DFSDM1 Alternate Function mapping */
-#define GPIO_AF10_DFSDM2        ((uint8_t)0x0A)  /* DFSDM2 Alternate Function mapping */
-#define GPIO_AF10_QSPI          ((uint8_t)0x0A)  /* QSPI Alternate Function mapping   */
-#define GPIO_AF10_FSMC          ((uint8_t)0x0A)  /* FSMC Alternate Function mapping   */
-
-/** 
-  * @brief   AF 11 selection  
-  */
-#define GPIO_AF11_UART4         ((uint8_t)0x0B)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF11_UART5         ((uint8_t)0x0B)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF11_UART9         ((uint8_t)0x0B)  /* UART9 Alternate Function mapping  */
-#define GPIO_AF11_UART10        ((uint8_t)0x0B)  /* UART10 Alternate Function mapping */
-#define GPIO_AF11_CAN3          ((uint8_t)0x0B)  /* CAN3 Alternate Function mapping   */
-   
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping  */
-#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping   */
-
-/** 
-  * @brief   AF 14 selection  
-  */ 
-#define GPIO_AF14_RNG           ((uint8_t)0x0E)  /* RNG Alternate Function mapping  */
-   
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F413xx || STM32F423xx */
-
-/*---------------------------------------- STM32F411xx------------------------*/
-#if defined(STM32F411xE) 
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
-#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
-#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
-
-/** 
-  * @brief   AF 6 selection  
-  */
-#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* I2S2 Alternate Function mapping       */
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /* SPI4/I2S4 Alternate Function mapping  */
-#define GPIO_AF6_SPI5          ((uint8_t)0x06)  /* SPI5/I2S5 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
-#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping  */
-#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping  */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping  */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F411xE */
-
-/*---------------------------------------- STM32F410xx------------------------*/
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04)  /* FMPI2C1 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */
-#if defined(STM32F410Cx) || defined(STM32F410Rx)  
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
-#endif /* STM32F410Cx || STM32F410Rx */   
-
-/** 
-  * @brief   AF 6 selection  
-  */
-#define GPIO_AF6_SPI1          ((uint8_t)0x06)  /* SPI1 Alternate Function mapping  */
-#if defined(STM32F410Cx) || defined(STM32F410Rx)   
-#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* I2S2 Alternate Function mapping       */
-#endif /* STM32F410Cx || STM32F410Rx */   
-#define GPIO_AF6_SPI5          ((uint8_t)0x06)  /* SPI5/I2S5 Alternate Function mapping  */
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping  */
-#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09)  /* FMPI2C1 Alternate Function mapping */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-/*---------------------------------------- STM32F446xx -----------------------*/
-#if defined(STM32F446xx)
-/**
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
-#define GPIO_AF3_CEC           ((uint8_t)0x03)  /* CEC Alternate Function mapping   */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
-#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04)  /* FMPI2C1 Alternate Function mapping */
-#define GPIO_AF4_CEC           ((uint8_t)0x04)  /* CEC Alternate Function mapping  */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
-#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* SPI2/I2S2 Alternate Function mapping  */
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /* SPI4 Alternate Function mapping       */
-#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
-#define GPIO_AF7_UART5         ((uint8_t)0x07)  /* UART5 Alternate Function mapping      */
-#define GPIO_AF7_SPI2          ((uint8_t)0x07)  /* SPI2/I2S2 Alternate Function mapping  */
-#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF7_SPDIFRX       ((uint8_t)0x07)  /* SPDIFRX Alternate Function mapping      */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
-#define GPIO_AF8_SPDIFRX       ((uint8_t)0x08)  /* SPDIFRX Alternate Function mapping  */
-#define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping   */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
-#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
-#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
-#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
-#define GPIO_AF9_QSPI          ((uint8_t)0x09)  /* QSPI Alternate Function mapping  */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
-#define GPIO_AF10_SAI2          ((uint8_t)0x0A)  /* SAI2 Alternate Function mapping   */
-#define GPIO_AF10_QSPI          ((uint8_t)0x0A)  /* QSPI Alternate Function mapping  */
-
-/** 
-  * @brief   AF 11 selection  
-  */ 
-#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping                      */
-#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
-
-/** 
-  * @brief   AF 13 selection  
-  */ 
-#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
-
-#endif /* STM32F446xx */
-/*----------------------------------------------------------------------------*/
-
-/*-------------------------------- STM32F469xx/STM32F479xx--------------------*/
-#if defined(STM32F469xx) || defined(STM32F479xx)
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
-
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
-#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
-#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
-#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
-#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
-#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
-#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping        */
-#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping        */
-#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
-#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
-#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
-#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
-#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */
-#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
-#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping    */
-#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */
-#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
-#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LCD-TFT Alternate Function mapping */
-#define GPIO_AF9_QSPI          ((uint8_t)0x09)  /* QSPI Alternate Function mapping    */
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
-#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
-#define GPIO_AF10_QSPI          ((uint8_t)0x0A)  /* QSPI Alternate Function mapping   */
-
-/** 
-  * @brief   AF 11 selection  
-  */ 
-#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping                      */
-#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
-#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
-
-/** 
-  * @brief   AF 13 selection  
-  */ 
-#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
-#define GPIO_AF13_DSI           ((uint8_t)0x0D)  /* DSI Alternate Function mapping  */
-
-/** 
-  * @brief   AF 14 selection  
-  */
-#define GPIO_AF14_LTDC          ((uint8_t)0x0E)  /* LCD-TFT Alternate Function mapping */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
-
-#endif /* STM32F469xx || STM32F479xx */
-/*----------------------------------------------------------------------------*/
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
-  * @{
-  */
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
-  * @{
-  */
-/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
-  * @{
-  */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
-#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
-                                               ((__GPIOx__) == (GPIOB))? 1U :\
-                                               ((__GPIOx__) == (GPIOC))? 2U :\
-                                               ((__GPIOx__) == (GPIOD))? 3U :\
-                                               ((__GPIOx__) == (GPIOE))? 4U :\
-                                               ((__GPIOx__) == (GPIOF))? 5U :\
-                                               ((__GPIOx__) == (GPIOG))? 6U :\
-                                               ((__GPIOx__) == (GPIOH))? 7U : 8U)
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
-                                               ((__GPIOx__) == (GPIOB))? 1U :\
-                                               ((__GPIOx__) == (GPIOC))? 2U :\
-                                               ((__GPIOx__) == (GPIOD))? 3U :\
-                                               ((__GPIOx__) == (GPIOE))? 4U :\
-                                               ((__GPIOx__) == (GPIOF))? 5U :\
-                                               ((__GPIOx__) == (GPIOG))? 6U :\
-                                               ((__GPIOx__) == (GPIOH))? 7U :\
-                                               ((__GPIOx__) == (GPIOI))? 8U :\
-                                               ((__GPIOx__) == (GPIOJ))? 9U : 10U)
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 
-#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
-                                               ((__GPIOx__) == (GPIOB))? 1U :\
-                                               ((__GPIOx__) == (GPIOC))? 2U : 7U)
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
-#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
-                                               ((__GPIOx__) == (GPIOB))? 1U :\
-                                               ((__GPIOx__) == (GPIOC))? 2U :\
-                                               ((__GPIOx__) == (GPIOD))? 3U :\
-                                               ((__GPIOx__) == (GPIOE))? 4U : 7U)
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
-
-#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 
-#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
-                                               ((__GPIOx__) == (GPIOB))? 1U :\
-                                               ((__GPIOx__) == (GPIOC))? 2U :\
-                                               ((__GPIOx__) == (GPIOD))? 3U :\
-                                               ((__GPIOx__) == (GPIOE))? 4U :\
-                                               ((__GPIOx__) == (GPIOF))? 5U :\
-                                               ((__GPIOx__) == (GPIOG))? 6U : 7U)
-#endif /* STM32F446xx || STM32F412Zx  || STM32F413xx || STM32F423xx */
-#if defined(STM32F412Vx)
-#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
-                                               ((__GPIOx__) == (GPIOB))? 1U :\
-                                               ((__GPIOx__) == (GPIOC))? 2U :\
-                                               ((__GPIOx__) == (GPIOD))? 3U :\
-                                               ((__GPIOx__) == (GPIOE))? 4U : 7U)
-#endif /* STM32F412Vx */
-#if defined(STM32F412Rx)
-#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
-                                               ((__GPIOx__) == (GPIOB))? 1U :\
-                                               ((__GPIOx__) == (GPIOC))? 2U :\
-                                               ((__GPIOx__) == (GPIOD))? 3U : 7U)
-#endif /* STM32F412Rx */
-#if defined(STM32F412Cx)
-#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
-                                               ((__GPIOx__) == (GPIOB))? 1U :\
-                                               ((__GPIOx__) == (GPIOC))? 2U : 7U)
-#endif /* STM32F412Cx */
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
-  * @{
-  */  
-/*------------------------- STM32F429xx/STM32F439xx---------------------------*/
-#if defined(STM32F429xx) || defined(STM32F439xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
-                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
-                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
-                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
-                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
-                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
-                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
-                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1)      || \
-                          ((AF) == GPIO_AF14_LTDC))
-
-#endif /* STM32F429xx || STM32F439xx */
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F427xx/STM32F437xx------------------*/
-#if defined(STM32F427xx) || defined(STM32F437xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
-                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
-                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
-                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
-                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
-                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
-                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
-                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1))
-
-#endif /* STM32F427xx || STM32F437xx */
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F407xx/STM32F417xx------------------*/
-#if defined(STM32F407xx) || defined(STM32F417xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
-                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
-                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
-                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
-                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
-                          ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))
-
-#endif /* STM32F407xx || STM32F417xx */
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F405xx/STM32F415xx------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
-                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
-                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
-                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
-                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO)      || \
-                          ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))
-
-#endif /* STM32F405xx || STM32F415xx */
-
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------------- STM32F401xx------------------------*/
-#if defined(STM32F401xC) || defined(STM32F401xE)
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF12_SDIO)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM9)       || \
-                          ((AF) == GPIO_AF3_TIM10)      || ((AF) == GPIO_AF3_TIM11)      || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
-                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF7_USART1)     || \
-                          ((AF) == GPIO_AF7_USART2)     || ((AF) == GPIO_AF8_USART6)     || \
-                          ((AF) == GPIO_AF9_I2C2)       || ((AF) == GPIO_AF9_I2C3)       || \
-                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF15_EVENTOUT))
-#endif /* STM32F401xC || STM32F401xE */
-/*----------------------------------------------------------------------------*/
-/*---------------------------------------- STM32F410xx------------------------*/
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 
-#define IS_GPIO_AF(AF)   (((AF) < 10U) || ((AF) == 15U))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-/*---------------------------------------- STM32F411xx------------------------*/
-#if defined(STM32F411xE) 
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF4_I2C1)       || \
-                          ((AF) == GPIO_AF4_I2C2)       || ((AF) == GPIO_AF4_I2C3)       || \
-                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
-                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF6_SPI4)       || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF6_SPI5)       || ((AF) == GPIO_AF7_SPI3)       || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF8_USART6)     || ((AF) == GPIO_AF10_OTG_FS)    || \
-                          ((AF) == GPIO_AF9_I2C2)       || ((AF) == GPIO_AF9_I2C3)       || \
-                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF15_EVENTOUT))
-
-#endif /* STM32F411xE */
-/*----------------------------------------------------------------------------*/
-
-/*----------------------------------------------- STM32F446xx ----------------*/
-#if defined(STM32F446xx) 
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
-                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
-                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
-                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
-                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
-                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1)      || \
-                          ((AF) == GPIO_AF3_CEC)        ||  ((AF) == GPIO_AF4_CEC)       || \
-                          ((AF) == GPIO_AF5_SPI3)       ||  ((AF) == GPIO_AF6_SPI2)      || \
-                          ((AF) == GPIO_AF6_SPI4)       ||  ((AF) == GPIO_AF7_UART5)     || \
-                          ((AF) == GPIO_AF7_SPI2)       ||  ((AF) == GPIO_AF7_SPI3)      || \
-                          ((AF) == GPIO_AF7_SPDIFRX)    ||  ((AF) == GPIO_AF8_SPDIFRX)   || \
-                          ((AF) == GPIO_AF8_SAI2)       ||  ((AF) == GPIO_AF9_QSPI)      || \
-                          ((AF) == GPIO_AF10_SAI2)      ||  ((AF) == GPIO_AF10_QSPI))
-
-#endif /* STM32F446xx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------------------------------- STM32F469xx/STM32F479xx --------*/
-#if defined(STM32F469xx) || defined(STM32F479xx) 
-#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
-                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
-                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
-                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
-                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
-                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
-                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
-                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
-                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
-                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
-                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
-                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
-                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
-                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
-                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
-                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
-                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
-                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
-                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
-                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
-                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF6_SAI1)       || \
-                          ((AF) == GPIO_AF14_LTDC)      || ((AF) == GPIO_AF13_DSI)      || \
-                          ((AF) == GPIO_AF9_QSPI)       || ((AF) == GPIO_AF10_QSPI))
-
-#endif /* STM32F469xx || STM32F479xx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-----------*/
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
-#define IS_GPIO_AF(AF)   (((AF) < 16U) && ((AF) != 11U) && ((AF) != 14U) && ((AF) != 13U))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------STM32F413xx/STM32F423xx-----------------------------------*/
-#if defined(STM32F413xx) || defined(STM32F423xx)  
-#define IS_GPIO_AF(AF)   (((AF) < 16U) && ((AF) != 13U))
-#endif /* STM32F413xx || STM32F423xx */
-/*----------------------------------------------------------------------------*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_GPIO_EX_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_gpio_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_GPIO_EX_H
+#define __STM32F4xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIOEx GPIOEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+  
+/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
+  * @{
+  */
+
+/*------------------------------------------ STM32F429xx/STM32F439xx ---------*/
+#if defined(STM32F429xx) || defined(STM32F439xx)
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
+#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping        */
+#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping        */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping    */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
+#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LCD-TFT Alternate Function mapping */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
+
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping                      */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
+
+/** 
+  * @brief   AF 14 selection  
+  */
+#define GPIO_AF14_LTDC          ((uint8_t)0x0E)  /* LCD-TFT Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F429xx || STM32F439xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F427xx/STM32F437xx------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx)
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
+#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping        */
+#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping        */
+/** @brief  GPIO_Legacy 
+  */
+#define GPIO_AF5_I2S3ext       GPIO_AF5_SPI3   /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
+
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping                      */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F427xx || STM32F437xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F407xx/STM32F417xx------------------*/
+#if defined(STM32F407xx) || defined(STM32F417xx)
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
+
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FSMC Alternate Function mapping                     */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F407xx || STM32F417xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F405xx/STM32F415xx------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx)
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FSMC Alternate Function mapping                     */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F405xx || STM32F415xx */
+
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------------- STM32F401xx------------------------*/
+#if defined(STM32F401xC) || defined(STM32F401xE) 
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3 Alternate Function mapping        */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping  */
+#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping  */
+
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping  */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F401xC || STM32F401xE */
+/*----------------------------------------------------------------------------*/
+
+/*--------------- STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-------------*/
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)   
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping    */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping    */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping    */
+#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04)  /* FMPI2C1 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4/I2S4 Alternate Function mapping   */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */
+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* I2S2 Alternate Function mapping       */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /* SPI4/I2S4 Alternate Function mapping  */
+#define GPIO_AF6_SPI5          ((uint8_t)0x06)  /* SPI5/I2S5 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping     */
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_USART3        ((uint8_t)0x08)  /* USART3 Alternate Function mapping */
+#define GPIO_AF8_DFSDM1        ((uint8_t)0x08)  /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF8_CAN1          ((uint8_t)0x08)  /* CAN1 Alternate Function mapping   */
+
+/** 
+  * @brief   AF 9 selection 
+  */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
+#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping    */
+#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping    */
+#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09)  /* FMPI2C1 Alternate Function mapping */
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */  
+#define GPIO_AF9_QSPI          ((uint8_t)0x09)  /* QSPI Alternate Function mapping    */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_DFSDM1        ((uint8_t)0x0A)  /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF10_QSPI          ((uint8_t)0x0A)  /* QSPI Alternate Function mapping   */
+#define GPIO_AF10_FMC           ((uint8_t)0x0A)  /* FMC Alternate Function mapping    */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping  */
+#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping   */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+/*----------------------------------------------------------------------------*/
+
+/*--------------- STM32F413xx/STM32F423xx-------------------------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)   
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+#define GPIO_AF3_DFSDM2        ((uint8_t)0x03)  /* DFSDM2 Alternate Function mapping */   
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping    */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping    */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping    */
+#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04)  /* FMPI2C1 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4/I2S4 Alternate Function mapping   */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */
+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* I2S2 Alternate Function mapping       */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /* SPI4/I2S4 Alternate Function mapping  */
+#define GPIO_AF6_SPI5          ((uint8_t)0x06)  /* SPI5/I2S5 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM1 Alternate Function mapping     */
+#define GPIO_AF6_DFSDM2        ((uint8_t)0x06)  /* DFSDM2 Alternate Function mapping     */   
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF7_SAI1          ((uint8_t)0x07)  /* SAI1 Alternate Function mapping       */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+#define GPIO_AF7_DFSDM2        ((uint8_t)0x07)  /* DFSDM2 Alternate Function mapping     */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_USART3        ((uint8_t)0x08)  /* USART3 Alternate Function mapping */
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+#define GPIO_AF8_DFSDM1        ((uint8_t)0x08)  /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF8_CAN1          ((uint8_t)0x08)  /* CAN1 Alternate Function mapping   */
+
+/** 
+  * @brief   AF 9 selection 
+  */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
+#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping    */
+#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping    */
+#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09)  /* FMPI2C1 Alternate Function mapping */
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_QSPI          ((uint8_t)0x09)  /* QSPI Alternate Function mapping    */
+
+/** 
+  * @brief   AF 10 selection  
+  */
+#define GPIO_AF10_SAI1          ((uint8_t)0x0A)  /* SAI1 Alternate Function mapping   */
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_DFSDM1        ((uint8_t)0x0A)  /* DFSDM1 Alternate Function mapping */
+#define GPIO_AF10_DFSDM2        ((uint8_t)0x0A)  /* DFSDM2 Alternate Function mapping */
+#define GPIO_AF10_QSPI          ((uint8_t)0x0A)  /* QSPI Alternate Function mapping   */
+#define GPIO_AF10_FSMC          ((uint8_t)0x0A)  /* FSMC Alternate Function mapping   */
+
+/** 
+  * @brief   AF 11 selection  
+  */
+#define GPIO_AF11_UART4         ((uint8_t)0x0B)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF11_UART5         ((uint8_t)0x0B)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF11_UART9         ((uint8_t)0x0B)  /* UART9 Alternate Function mapping  */
+#define GPIO_AF11_UART10        ((uint8_t)0x0B)  /* UART10 Alternate Function mapping */
+#define GPIO_AF11_CAN3          ((uint8_t)0x0B)  /* CAN3 Alternate Function mapping   */
+   
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping  */
+#define GPIO_AF12_FSMC          ((uint8_t)0x0C)  /* FMC Alternate Function mapping   */
+
+/** 
+  * @brief   AF 14 selection  
+  */ 
+#define GPIO_AF14_RNG           ((uint8_t)0x0E)  /* RNG Alternate Function mapping  */
+   
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F413xx || STM32F423xx */
+
+/*---------------------------------------- STM32F411xx------------------------*/
+#if defined(STM32F411xE) 
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */
+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* I2S2 Alternate Function mapping       */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /* SPI4/I2S4 Alternate Function mapping  */
+#define GPIO_AF6_SPI5          ((uint8_t)0x06)  /* SPI5/I2S5 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping  */
+#define GPIO_AF9_I2C3          ((uint8_t)0x09)  /* I2C3 Alternate Function mapping  */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping  */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F411xE */
+
+/*---------------------------------------- STM32F410xx------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04)  /* FMPI2C1 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */
+#if defined(STM32F410Cx) || defined(STM32F410Rx)  
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#endif /* STM32F410Cx || STM32F410Rx */   
+
+/** 
+  * @brief   AF 6 selection  
+  */
+#define GPIO_AF6_SPI1          ((uint8_t)0x06)  /* SPI1 Alternate Function mapping  */
+#if defined(STM32F410Cx) || defined(STM32F410Rx)   
+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* I2S2 Alternate Function mapping       */
+#endif /* STM32F410Cx || STM32F410Rx */   
+#define GPIO_AF6_SPI5          ((uint8_t)0x06)  /* SPI5/I2S5 Alternate Function mapping  */
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_I2C2          ((uint8_t)0x09)  /* I2C2 Alternate Function mapping  */
+#define GPIO_AF9_FMPI2C1       ((uint8_t)0x09)  /* FMPI2C1 Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/*---------------------------------------- STM32F446xx -----------------------*/
+#if defined(STM32F446xx)
+/**
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+#define GPIO_AF3_CEC           ((uint8_t)0x03)  /* CEC Alternate Function mapping   */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+#define GPIO_AF4_FMPI2C1       ((uint8_t)0x04)  /* FMPI2C1 Alternate Function mapping */
+#define GPIO_AF4_CEC           ((uint8_t)0x04)  /* CEC Alternate Function mapping  */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* SPI2/I2S2 Alternate Function mapping  */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_SPI4          ((uint8_t)0x06)  /* SPI4 Alternate Function mapping       */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_UART5         ((uint8_t)0x07)  /* UART5 Alternate Function mapping      */
+#define GPIO_AF7_SPI2          ((uint8_t)0x07)  /* SPI2/I2S2 Alternate Function mapping  */
+#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF7_SPDIFRX       ((uint8_t)0x07)  /* SPDIFRX Alternate Function mapping      */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_SPDIFRX       ((uint8_t)0x08)  /* SPDIFRX Alternate Function mapping  */
+#define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping   */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping  */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+#define GPIO_AF9_QSPI          ((uint8_t)0x09)  /* QSPI Alternate Function mapping  */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
+#define GPIO_AF10_SAI2          ((uint8_t)0x0A)  /* SAI2 Alternate Function mapping   */
+#define GPIO_AF10_QSPI          ((uint8_t)0x0A)  /* QSPI Alternate Function mapping  */
+
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping                      */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#endif /* STM32F446xx */
+/*----------------------------------------------------------------------------*/
+
+/*-------------------------------- STM32F469xx/STM32F479xx--------------------*/
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping  */
+#define GPIO_AF3_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF3_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping        */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping   */
+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3/I2S3 Alternate Function mapping   */
+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping        */
+#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping        */
+#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping        */
+#define GPIO_AF5_I2S3ext       ((uint8_t)0x05)  /* I2S3ext_SD Alternate Function mapping  */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping  */
+#define GPIO_AF6_I2S2ext       ((uint8_t)0x06)  /* I2S2ext_SD Alternate Function mapping */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping       */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+#define GPIO_AF7_I2S3ext       ((uint8_t)0x07)  /* I2S3ext_SD Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+#define GPIO_AF8_UART7         ((uint8_t)0x08)  /* UART7 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping    */
+#define GPIO_AF9_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping    */
+#define GPIO_AF9_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
+#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LCD-TFT Alternate Function mapping */
+#define GPIO_AF9_QSPI          ((uint8_t)0x09)  /* QSPI Alternate Function mapping    */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF10_OTG_FS        ((uint8_t)0x0A)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF10_OTG_HS        ((uint8_t)0x0A)  /* OTG_HS Alternate Function mapping */
+#define GPIO_AF10_QSPI          ((uint8_t)0x0A)  /* QSPI Alternate Function mapping   */
+
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping                      */
+#define GPIO_AF12_OTG_HS_FS     ((uint8_t)0x0C)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF12_SDIO          ((uint8_t)0x0C)  /* SDIO Alternate Function mapping                     */
+
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
+#define GPIO_AF13_DSI           ((uint8_t)0x0D)  /* DSI Alternate Function mapping  */
+
+/** 
+  * @brief   AF 14 selection  
+  */
+#define GPIO_AF14_LTDC          ((uint8_t)0x0E)  /* LCD-TFT Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#endif /* STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Constants GPIO Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros
+  * @{
+  */
+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index
+  * @{
+  */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                               ((__GPIOx__) == (GPIOB))? 1U :\
+                                               ((__GPIOx__) == (GPIOC))? 2U :\
+                                               ((__GPIOx__) == (GPIOD))? 3U :\
+                                               ((__GPIOx__) == (GPIOE))? 4U :\
+                                               ((__GPIOx__) == (GPIOF))? 5U :\
+                                               ((__GPIOx__) == (GPIOG))? 6U :\
+                                               ((__GPIOx__) == (GPIOH))? 7U : 8U)
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                               ((__GPIOx__) == (GPIOB))? 1U :\
+                                               ((__GPIOx__) == (GPIOC))? 2U :\
+                                               ((__GPIOx__) == (GPIOD))? 3U :\
+                                               ((__GPIOx__) == (GPIOE))? 4U :\
+                                               ((__GPIOx__) == (GPIOF))? 5U :\
+                                               ((__GPIOx__) == (GPIOG))? 6U :\
+                                               ((__GPIOx__) == (GPIOH))? 7U :\
+                                               ((__GPIOx__) == (GPIOI))? 8U :\
+                                               ((__GPIOx__) == (GPIOJ))? 9U : 10U)
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 
+#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                               ((__GPIOx__) == (GPIOB))? 1U :\
+                                               ((__GPIOx__) == (GPIOC))? 2U : 7U)
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
+#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                               ((__GPIOx__) == (GPIOB))? 1U :\
+                                               ((__GPIOx__) == (GPIOC))? 2U :\
+                                               ((__GPIOx__) == (GPIOD))? 3U :\
+                                               ((__GPIOx__) == (GPIOE))? 4U : 7U)
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+
+#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 
+#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                               ((__GPIOx__) == (GPIOB))? 1U :\
+                                               ((__GPIOx__) == (GPIOC))? 2U :\
+                                               ((__GPIOx__) == (GPIOD))? 3U :\
+                                               ((__GPIOx__) == (GPIOE))? 4U :\
+                                               ((__GPIOx__) == (GPIOF))? 5U :\
+                                               ((__GPIOx__) == (GPIOG))? 6U : 7U)
+#endif /* STM32F446xx || STM32F412Zx  || STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx)
+#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                               ((__GPIOx__) == (GPIOB))? 1U :\
+                                               ((__GPIOx__) == (GPIOC))? 2U :\
+                                               ((__GPIOx__) == (GPIOD))? 3U :\
+                                               ((__GPIOx__) == (GPIOE))? 4U : 7U)
+#endif /* STM32F412Vx */
+#if defined(STM32F412Rx)
+#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                               ((__GPIOx__) == (GPIOB))? 1U :\
+                                               ((__GPIOx__) == (GPIOC))? 2U :\
+                                               ((__GPIOx__) == (GPIOD))? 3U : 7U)
+#endif /* STM32F412Rx */
+#if defined(STM32F412Cx)
+#define GPIO_GET_INDEX(__GPIOx__)    (uint8_t)(((__GPIOx__) == (GPIOA))? 0U :\
+                                               ((__GPIOx__) == (GPIOB))? 1U :\
+                                               ((__GPIOx__) == (GPIOC))? 2U : 7U)
+#endif /* STM32F412Cx */
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function
+  * @{
+  */  
+/*------------------------- STM32F429xx/STM32F439xx---------------------------*/
+#if defined(STM32F429xx) || defined(STM32F439xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
+                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
+                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
+                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
+                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1)      || \
+                          ((AF) == GPIO_AF14_LTDC))
+
+#endif /* STM32F429xx || STM32F439xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F427xx/STM32F437xx------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
+                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
+                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
+                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
+                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1))
+
+#endif /* STM32F427xx || STM32F437xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F407xx/STM32F417xx------------------*/
+#if defined(STM32F407xx) || defined(STM32F417xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
+                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
+                          ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F407xx || STM32F417xx */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F405xx/STM32F415xx------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
+                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDIO)      || \
+                          ((AF) == GPIO_AF12_FSMC)      || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F405xx || STM32F415xx */
+
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------------- STM32F401xx------------------------*/
+#if defined(STM32F401xC) || defined(STM32F401xE)
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF12_SDIO)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM9)       || \
+                          ((AF) == GPIO_AF3_TIM10)      || ((AF) == GPIO_AF3_TIM11)      || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF7_USART1)     || \
+                          ((AF) == GPIO_AF7_USART2)     || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_I2C2)       || ((AF) == GPIO_AF9_I2C3)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF15_EVENTOUT))
+#endif /* STM32F401xC || STM32F401xE */
+/*----------------------------------------------------------------------------*/
+/*---------------------------------------- STM32F410xx------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 
+#define IS_GPIO_AF(AF)   (((AF) < 10U) || ((AF) == 15U))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/*---------------------------------------- STM32F411xx------------------------*/
+#if defined(STM32F411xE) 
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF4_I2C1)       || \
+                          ((AF) == GPIO_AF4_I2C2)       || ((AF) == GPIO_AF4_I2C3)       || \
+                          ((AF) == GPIO_AF5_SPI1)       || ((AF) == GPIO_AF5_SPI2)       || \
+                          ((AF) == GPIO_AF5_SPI3)       || ((AF) == GPIO_AF6_SPI4)       || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF6_SPI5)       || ((AF) == GPIO_AF7_SPI3)       || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF8_USART6)     || ((AF) == GPIO_AF10_OTG_FS)    || \
+                          ((AF) == GPIO_AF9_I2C2)       || ((AF) == GPIO_AF9_I2C3)       || \
+                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF15_EVENTOUT))
+
+#endif /* STM32F411xE */
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------- STM32F446xx ----------------*/
+#if defined(STM32F446xx) 
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
+                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
+                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF12_FMC)       ||  ((AF) == GPIO_AF6_SAI1)      || \
+                          ((AF) == GPIO_AF3_CEC)        ||  ((AF) == GPIO_AF4_CEC)       || \
+                          ((AF) == GPIO_AF5_SPI3)       ||  ((AF) == GPIO_AF6_SPI2)      || \
+                          ((AF) == GPIO_AF6_SPI4)       ||  ((AF) == GPIO_AF7_UART5)     || \
+                          ((AF) == GPIO_AF7_SPI2)       ||  ((AF) == GPIO_AF7_SPI3)      || \
+                          ((AF) == GPIO_AF7_SPDIFRX)    ||  ((AF) == GPIO_AF8_SPDIFRX)   || \
+                          ((AF) == GPIO_AF8_SAI2)       ||  ((AF) == GPIO_AF9_QSPI)      || \
+                          ((AF) == GPIO_AF10_SAI2)      ||  ((AF) == GPIO_AF10_QSPI))
+
+#endif /* STM32F446xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------------------------------- STM32F469xx/STM32F479xx --------*/
+#if defined(STM32F469xx) || defined(STM32F479xx) 
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF0_RTC_50Hz)   || ((AF) == GPIO_AF9_TIM14)      || \
+                          ((AF) == GPIO_AF0_MCO)        || ((AF) == GPIO_AF0_TAMPER)     || \
+                          ((AF) == GPIO_AF0_SWJ)        || ((AF) == GPIO_AF0_TRACE)      || \
+                          ((AF) == GPIO_AF1_TIM1)       || ((AF) == GPIO_AF1_TIM2)       || \
+                          ((AF) == GPIO_AF2_TIM3)       || ((AF) == GPIO_AF2_TIM4)       || \
+                          ((AF) == GPIO_AF2_TIM5)       || ((AF) == GPIO_AF3_TIM8)       || \
+                          ((AF) == GPIO_AF4_I2C1)       || ((AF) == GPIO_AF4_I2C2)       || \
+                          ((AF) == GPIO_AF4_I2C3)       || ((AF) == GPIO_AF5_SPI1)       || \
+                          ((AF) == GPIO_AF5_SPI2)       || ((AF) == GPIO_AF9_TIM13)      || \
+                          ((AF) == GPIO_AF6_SPI3)       || ((AF) == GPIO_AF9_TIM12)      || \
+                          ((AF) == GPIO_AF7_USART1)     || ((AF) == GPIO_AF7_USART2)     || \
+                          ((AF) == GPIO_AF7_USART3)     || ((AF) == GPIO_AF8_UART4)      || \
+                          ((AF) == GPIO_AF8_UART5)      || ((AF) == GPIO_AF8_USART6)     || \
+                          ((AF) == GPIO_AF9_CAN1)       || ((AF) == GPIO_AF9_CAN2)       || \
+                          ((AF) == GPIO_AF10_OTG_FS)    || ((AF) == GPIO_AF10_OTG_HS)    || \
+                          ((AF) == GPIO_AF11_ETH)       || ((AF) == GPIO_AF12_OTG_HS_FS) || \
+                          ((AF) == GPIO_AF12_SDIO)      || ((AF) == GPIO_AF13_DCMI)      || \
+                          ((AF) == GPIO_AF15_EVENTOUT)  || ((AF) == GPIO_AF5_SPI4)       || \
+                          ((AF) == GPIO_AF5_SPI5)       || ((AF) == GPIO_AF5_SPI6)       || \
+                          ((AF) == GPIO_AF8_UART7)      || ((AF) == GPIO_AF8_UART8)      || \
+                          ((AF) == GPIO_AF12_FMC)       || ((AF) == GPIO_AF6_SAI1)       || \
+                          ((AF) == GPIO_AF14_LTDC)      || ((AF) == GPIO_AF13_DSI)      || \
+                          ((AF) == GPIO_AF9_QSPI)       || ((AF) == GPIO_AF10_QSPI))
+
+#endif /* STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx-----------*/
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)  
+#define IS_GPIO_AF(AF)   (((AF) < 16U) && ((AF) != 11U) && ((AF) != 14U) && ((AF) != 13U))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------STM32F413xx/STM32F423xx-----------------------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)  
+#define IS_GPIO_AF(AF)   (((AF) < 16U) && ((AF) != 13U))
+#endif /* STM32F413xx || STM32F423xx */
+/*----------------------------------------------------------------------------*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup GPIOEx_Private_Functions GPIO Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_GPIO_EX_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h
index d97f255..ab0412d 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h
@@ -1,427 +1,427 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_pwr.h
-  * @author  MCD Application Team
-  * @brief   Header file of PWR HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_PWR_H
-#define __STM32F4xx_HAL_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PWR
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Types PWR Exported Types
-  * @{
-  */
-   
-/**
-  * @brief  PWR PVD configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
-                            This parameter can be a value of @ref PWR_PVD_detection_level */
-
-  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref PWR_PVD_Mode */
-}PWR_PVDTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_Exported_Constants PWR Exported Constants
-  * @{
-  */
-  
-/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
-  * @{
-  */
-#define PWR_WAKEUP_PIN1                 0x00000100U
-/**
-  * @}
-  */
-
-/** @defgroup PWR_PVD_detection_level PWR PVD detection level
-  * @{
-  */ 
-#define PWR_PVDLEVEL_0                  PWR_CR_PLS_LEV0
-#define PWR_PVDLEVEL_1                  PWR_CR_PLS_LEV1
-#define PWR_PVDLEVEL_2                  PWR_CR_PLS_LEV2
-#define PWR_PVDLEVEL_3                  PWR_CR_PLS_LEV3
-#define PWR_PVDLEVEL_4                  PWR_CR_PLS_LEV4
-#define PWR_PVDLEVEL_5                  PWR_CR_PLS_LEV5
-#define PWR_PVDLEVEL_6                  PWR_CR_PLS_LEV6
-#define PWR_PVDLEVEL_7                  PWR_CR_PLS_LEV7/* External input analog voltage 
-                                                          (Compare internally to VREFINT) */
-/**
-  * @}
-  */   
- 
-/** @defgroup PWR_PVD_Mode PWR PVD Mode
-  * @{
-  */
-#define PWR_PVD_MODE_NORMAL                 0x00000000U   /*!< basic mode is used */
-#define PWR_PVD_MODE_IT_RISING              0x00010001U   /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING             0x00010002U   /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING      0x00010003U   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING           0x00020001U   /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING          0x00020002U   /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING   0x00020003U   /*!< Event Mode with Rising/Falling edge trigger detection */
-/**
-  * @}
-  */
-
-
-/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
-  * @{
-  */
-#define PWR_MAINREGULATOR_ON                        0x00000000U
-#define PWR_LOWPOWERREGULATOR_ON                    PWR_CR_LPDS
-/**
-  * @}
-  */
-    
-/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
-  * @{
-  */
-#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)
-#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)
-/**
-  * @}
-  */
-
-/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
-  * @{
-  */
-#define PWR_STOPENTRY_WFI               ((uint8_t)0x01)
-#define PWR_STOPENTRY_WFE               ((uint8_t)0x02)
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Flag PWR Flag
-  * @{
-  */
-#define PWR_FLAG_WU                     PWR_CSR_WUF
-#define PWR_FLAG_SB                     PWR_CSR_SBF
-#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
-#define PWR_FLAG_BRR                    PWR_CSR_BRR
-#define PWR_FLAG_VOSRDY                 PWR_CSR_VOSRDY
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_Exported_Macro PWR Exported Macro
-  * @{
-  */
-
-/** @brief  Check PWR flag is set or not.
-  * @param  __FLAG__ specifies the flag to check.
-  *           This parameter can be one of the following values:
-  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 
-  *                  was received from the WKUP pin or from the RTC alarm (Alarm A 
-  *                  or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
-  *                  An additional wakeup event is detected if the WKUP pin is enabled 
-  *                  (by setting the EWUP bit) when the WKUP pin level is already high.  
-  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
-  *                  resumed from StandBy mode.    
-  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 
-  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode 
-  *                  For this reason, this bit is equal to 0 after Standby or reset
-  *                  until the PVDE bit is set.
-  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset 
-  *                  when the device wakes up from Standby mode or by a system reset 
-  *                  or power reset.  
-  *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage 
-  *                 scaling output selection is ready.
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the PWR's pending flags.
-  * @param  __FLAG__ specifies the flag to clear.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_FLAG_WU: Wake Up flag
-  *            @arg PWR_FLAG_SB: StandBy flag
-  */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |=  (__FLAG__) << 2U)
-
-/**
-  * @brief Enable the PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT()   (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Disable the PVD EXTI Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT()  (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Enable event on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Disable event on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Enable the PVD Extended Interrupt Rising Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Disable the PVD Extended Interrupt Rising Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Enable the PVD Extended Interrupt Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-
-/**
-  * @brief Disable the PVD Extended Interrupt Falling Trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
-
-
-/**
-  * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
-                                                             __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
-                                                            }while(0U)
-
-/**
-  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
-  * This parameter can be:
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
-                                                             __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
-                                                            }while(0U) 
-
-/**
-  * @brief checks whether the specified PVD Exti interrupt flag is set or not.
-  * @retval EXTI PVD Line Status.
-  */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR & (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Clear the PVD Exti flag.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  (EXTI->PR = (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief  Generates a Software interrupt on PVD EXTI line.
-  * @retval None
-  */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
-
-/**
-  * @}
-  */
-
-/* Include PWR HAL Extension module */
-#include "stm32f4xx_hal_pwr_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWR_Exported_Functions PWR Exported Functions
-  * @{
-  */
-  
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @{
-  */
-/* Initialization and de-initialization functions *****************************/
-void HAL_PWR_DeInit(void);
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
-/**
-  * @}
-  */
-
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 
-  * @{
-  */
-/* Peripheral Control functions  **********************************************/
-/* PVD configuration */
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
-
-/* WakeUp pins configuration */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
-
-/* Low Power modes entry */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
-
-/* Power PVD IRQ Handler */
-void HAL_PWR_PVD_IRQHandler(void);
-void HAL_PWR_PVDCallback(void);
-
-/* Cortex System Control functions  *******************************************/
-void HAL_PWR_EnableSleepOnExit(void);
-void HAL_PWR_DisableSleepOnExit(void);
-void HAL_PWR_EnableSEVOnPend(void);
-void HAL_PWR_DisableSEVOnPend(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PWR_Private_Constants PWR Private Constants
-  * @{
-  */
-
-/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
-  * @{
-  */
-#define PWR_EXTI_LINE_PVD  ((uint32_t)EXTI_IMR_MR16)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_register_alias_address PWR Register alias address
-  * @{
-  */
-/* ------------- PWR registers bit address in the alias region ---------------*/
-#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
-#define PWR_CR_OFFSET            0x00U
-#define PWR_CSR_OFFSET           0x04U
-#define PWR_CR_OFFSET_BB         (PWR_OFFSET + PWR_CR_OFFSET)
-#define PWR_CSR_OFFSET_BB        (PWR_OFFSET + PWR_CSR_OFFSET)
-/**
-  * @}
-  */
-
-/** @defgroup PWR_CR_register_alias PWR CR Register alias address
-  * @{
-  */
-/* --- CR Register ---*/
-/* Alias word address of DBP bit */
-#define DBP_BIT_NUMBER   PWR_CR_DBP_Pos
-#define CR_DBP_BB        (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BIT_NUMBER  PWR_CR_PVDE_Pos
-#define CR_PVDE_BB       (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
-
-/* Alias word address of VOS bit */
-#define VOS_BIT_NUMBER  PWR_CR_VOS_Pos
-#define CR_VOS_BB      (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U))
-/**
-  * @}
-  */
-
-/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
-  * @{
-  */
-/* --- CSR Register ---*/
-/* Alias word address of EWUP bit */
-#define EWUP_BIT_NUMBER  PWR_CSR_EWUP_Pos
-#define CSR_EWUP_BB      (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PWR_Private_Macros PWR Private Macros
-  * @{
-  */
-
-/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
-  * @{
-  */
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
-                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
-                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
-                              ((MODE) == PWR_PVD_MODE_NORMAL))
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
-                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F4xx_HAL_PWR_H */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PWR_H
+#define __STM32F4xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+  * @{
+  */
+   
+/**
+  * @brief  PWR PVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
+                            This parameter can be a value of @ref PWR_PVD_detection_level */
+
+  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref PWR_PVD_Mode */
+}PWR_PVDTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+  * @{
+  */
+  
+/** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
+  * @{
+  */
+#define PWR_WAKEUP_PIN1                 0x00000100U
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_detection_level PWR PVD detection level
+  * @{
+  */ 
+#define PWR_PVDLEVEL_0                  PWR_CR_PLS_LEV0
+#define PWR_PVDLEVEL_1                  PWR_CR_PLS_LEV1
+#define PWR_PVDLEVEL_2                  PWR_CR_PLS_LEV2
+#define PWR_PVDLEVEL_3                  PWR_CR_PLS_LEV3
+#define PWR_PVDLEVEL_4                  PWR_CR_PLS_LEV4
+#define PWR_PVDLEVEL_5                  PWR_CR_PLS_LEV5
+#define PWR_PVDLEVEL_6                  PWR_CR_PLS_LEV6
+#define PWR_PVDLEVEL_7                  PWR_CR_PLS_LEV7/* External input analog voltage 
+                                                          (Compare internally to VREFINT) */
+/**
+  * @}
+  */   
+ 
+/** @defgroup PWR_PVD_Mode PWR PVD Mode
+  * @{
+  */
+#define PWR_PVD_MODE_NORMAL                 0x00000000U   /*!< basic mode is used */
+#define PWR_PVD_MODE_IT_RISING              0x00010001U   /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING             0x00010002U   /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING      0x00010003U   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING           0x00020001U   /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING          0x00020002U   /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING   0x00020003U   /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+  * @}
+  */
+
+
+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
+  * @{
+  */
+#define PWR_MAINREGULATOR_ON                        0x00000000U
+#define PWR_LOWPOWERREGULATOR_ON                    PWR_CR_LPDS
+/**
+  * @}
+  */
+    
+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
+  * @{
+  */
+#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)
+#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
+  * @{
+  */
+#define PWR_STOPENTRY_WFI               ((uint8_t)0x01)
+#define PWR_STOPENTRY_WFE               ((uint8_t)0x02)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag PWR Flag
+  * @{
+  */
+#define PWR_FLAG_WU                     PWR_CSR_WUF
+#define PWR_FLAG_SB                     PWR_CSR_SBF
+#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
+#define PWR_FLAG_BRR                    PWR_CSR_BRR
+#define PWR_FLAG_VOSRDY                 PWR_CSR_VOSRDY
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macro PWR Exported Macro
+  * @{
+  */
+
+/** @brief  Check PWR flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 
+  *                  was received from the WKUP pin or from the RTC alarm (Alarm A 
+  *                  or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
+  *                  An additional wakeup event is detected if the WKUP pin is enabled 
+  *                  (by setting the EWUP bit) when the WKUP pin level is already high.  
+  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+  *                  resumed from StandBy mode.    
+  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 
+  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode 
+  *                  For this reason, this bit is equal to 0 after Standby or reset
+  *                  until the PVDE bit is set.
+  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset 
+  *                  when the device wakes up from Standby mode or by a system reset 
+  *                  or power reset.  
+  *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage 
+  *                 scaling output selection is ready.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the PWR's pending flags.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag
+  *            @arg PWR_FLAG_SB: StandBy flag
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |=  (__FLAG__) << 2U)
+
+/**
+  * @brief Enable the PVD Exti Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT()   (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Disable the PVD EXTI Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT()  (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Enable event on PVD Exti Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Disable event on PVD Exti Line 16.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Enable the PVD Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Rising Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+
+/**
+  * @brief Disable the PVD Extended Interrupt Falling Trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
+
+
+/**
+  * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()   do{__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();\
+                                                             __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();\
+                                                            }while(0U)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+  * This parameter can be:
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  do{__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();\
+                                                             __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();\
+                                                            }while(0U) 
+
+/**
+  * @brief checks whether the specified PVD Exti interrupt flag is set or not.
+  * @retval EXTI PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR & (PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief Clear the PVD Exti flag.
+  * @retval None.
+  */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  (EXTI->PR = (PWR_EXTI_LINE_PVD))
+
+/**
+  * @brief  Generates a Software interrupt on PVD EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
+
+/**
+  * @}
+  */
+
+/* Include PWR HAL Extension module */
+#include "stm32f4xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+  
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 
+  * @{
+  */
+/* Peripheral Control functions  **********************************************/
+/* PVD configuration */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+/* WakeUp pins configuration */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes entry */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+/* Power PVD IRQ Handler */
+void HAL_PWR_PVD_IRQHandler(void);
+void HAL_PWR_PVDCallback(void);
+
+/* Cortex System Control functions  *******************************************/
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWR_Private_Constants PWR Private Constants
+  * @{
+  */
+
+/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
+  * @{
+  */
+#define PWR_EXTI_LINE_PVD  ((uint32_t)EXTI_IMR_MR16)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_register_alias_address PWR Register alias address
+  * @{
+  */
+/* ------------- PWR registers bit address in the alias region ---------------*/
+#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
+#define PWR_CR_OFFSET            0x00U
+#define PWR_CSR_OFFSET           0x04U
+#define PWR_CR_OFFSET_BB         (PWR_OFFSET + PWR_CR_OFFSET)
+#define PWR_CSR_OFFSET_BB        (PWR_OFFSET + PWR_CSR_OFFSET)
+/**
+  * @}
+  */
+
+/** @defgroup PWR_CR_register_alias PWR CR Register alias address
+  * @{
+  */
+/* --- CR Register ---*/
+/* Alias word address of DBP bit */
+#define DBP_BIT_NUMBER   PWR_CR_DBP_Pos
+#define CR_DBP_BB        (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BIT_NUMBER  PWR_CR_PVDE_Pos
+#define CR_PVDE_BB       (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U))
+
+/* Alias word address of VOS bit */
+#define VOS_BIT_NUMBER  PWR_CR_VOS_Pos
+#define CR_VOS_BB      (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
+  * @{
+  */
+/* --- CSR Register ---*/
+/* Alias word address of EWUP bit */
+#define EWUP_BIT_NUMBER  PWR_CSR_EWUP_Pos
+#define CSR_EWUP_BB      (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWR_Private_Macros PWR Private Macros
+  * @{
+  */
+
+/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
+  * @{
+  */
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
+                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
+                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
+                              ((MODE) == PWR_PVD_MODE_NORMAL))
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PWR_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h
index 57fd4d9..7b632a5 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h
@@ -1,340 +1,340 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_pwr_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of PWR HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_PWR_EX_H
-#define __STM32F4xx_HAL_PWR_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PWREx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
-  * @{
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-   
-/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
-  * @{
-  */
-#define PWR_MAINREGULATOR_UNDERDRIVE_ON                       PWR_CR_MRUDS
-#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON                   ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
-/**
-  * @}
-  */ 
-  
-/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
-  * @{
-  */
-#define PWR_FLAG_ODRDY                  PWR_CSR_ODRDY
-#define PWR_FLAG_ODSWRDY                PWR_CSR_ODSWRDY
-#define PWR_FLAG_UDRDY                  PWR_CSR_UDSWRDY
-/**
-  * @}
-  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
-  * @{
-  */
-#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)   
-#define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR_VOS             /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */
-#define PWR_REGULATOR_VOLTAGE_SCALE2         0x00000000U            /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
-#else
-#define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR_VOS             /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to
-                                                                       180 MHz by activating the over-drive mode. */
-#define PWR_REGULATOR_VOLTAGE_SCALE2         PWR_CR_VOS_1           /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to
-                                                                       168 MHz by activating the over-drive mode. */
-#define PWR_REGULATOR_VOLTAGE_SCALE3         PWR_CR_VOS_0           /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */
-#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ 
-/**
-  * @}
-  */
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-/** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins
-  * @{
-  */
-#define PWR_WAKEUP_PIN2                 0x00000080U
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 
-#define PWR_WAKEUP_PIN3                 0x00000040U
-#endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \
-          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-/**
-  * @}
-  */   
-#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
-          STM32F413xx || STM32F423xx */
-
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
-  *  @{
-  */
-
-#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
-/** @brief  macros configure the main internal regulator output voltage.
-  * @param  __REGULATOR__ specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption when the device does
-  *         not operate at the maximum frequency (refer to the datasheets for more details).
-  *          This parameter can be one of the following values:
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
-  * @retval None
-  */
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
-                                                            __IO uint32_t tmpreg = 0x00U;                        \
-                                                            MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__));   \
-                                                            /* Delay after an RCC peripheral clock enabling */  \
-                                                            tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS);             \
-                                                            UNUSED(tmpreg);                                     \
-                                                          } while(0U)
-#else
-/** @brief  macros configure the main internal regulator output voltage.
-  * @param  __REGULATOR__ specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption when the device does
-  *         not operate at the maximum frequency (refer to the datasheets for more details).
-  *          This parameter can be one of the following values:
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
-  * @retval None
-  */
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
-                                                            __IO uint32_t tmpreg = 0x00U;                        \
-                                                            MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__));   \
-                                                            /* Delay after an RCC peripheral clock enabling */  \
-                                                            tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS);             \
-                                                            UNUSED(tmpreg);                                     \
-                                                          } while(0U)
-#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ 
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @brief Macros to enable or disable the Over drive mode.
-  * @note  These macros can be used only for STM32F42xx/STM3243xx devices.
-  */
-#define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)
-#define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
-
-/** @brief Macros to enable or disable the Over drive switching.
-  * @note  These macros can be used only for STM32F42xx/STM3243xx devices. 
-  */
-#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
-#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
-
-/** @brief Macros to enable or disable the Under drive mode.
-  * @note  This mode is enabled only with STOP low power mode.
-  *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
-  *        mode is only available when the main regulator or the low power regulator 
-  *        is in low voltage mode.      
-  * @note  If the Under-drive mode was enabled, it is automatically disabled after 
-  *        exiting Stop mode. 
-  *        When the voltage regulator operates in Under-drive mode, an additional  
-  *        startup delay is induced when waking up from Stop mode.
-  */
-#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
-#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))
-
-/** @brief  Check PWR flag is set or not.
-  * @note   These macros can be used only for STM32F42xx/STM3243xx devices.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
-  *                                 is ready 
-  *            @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
-  *                                   switching is ready  
-  *            @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
-  *                                 is enabled in Stop mode
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clear the Under-Drive Ready flag.
-  * @note  These macros can be used only for STM32F42xx/STM3243xx devices.
-  */
-#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
-  *  @{
-  */
- 
-/** @addtogroup PWREx_Exported_Functions_Group1
-  * @{
-  */
-void HAL_PWREx_EnableFlashPowerDown(void);
-void HAL_PWREx_DisableFlashPowerDown(void); 
-HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
-HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); 
-uint32_t HAL_PWREx_GetVoltageRange(void);
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
-    defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
-    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
-void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
-void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
-void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
-#endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F412Zx || STM32F412Vx ||\
-          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
-HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
-HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup PWREx_Private_Constants PWREx Private Constants
-  * @{
-  */
-
-/** @defgroup PWREx_register_alias_address PWREx Register alias address
-  * @{
-  */
-/* ------------- PWR registers bit address in the alias region ---------------*/
-/* --- CR Register ---*/
-/* Alias word address of FPDS bit */
-#define FPDS_BIT_NUMBER          PWR_CR_FPDS_Pos
-#define CR_FPDS_BB               (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
-
-/* Alias word address of ODEN bit   */
-#define ODEN_BIT_NUMBER          PWR_CR_ODEN_Pos
-#define CR_ODEN_BB               (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))
-
-/* Alias word address of ODSWEN bit */
-#define ODSWEN_BIT_NUMBER        PWR_CR_ODSWEN_Pos
-#define CR_ODSWEN_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))
-    
-/* Alias word address of MRLVDS bit */
-#define MRLVDS_BIT_NUMBER        PWR_CR_MRLVDS_Pos
-#define CR_MRLVDS_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))
-
-/* Alias word address of LPLVDS bit */
-#define LPLVDS_BIT_NUMBER        PWR_CR_LPLVDS_Pos
-#define CR_LPLVDS_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))
-
- /**
-  * @}
-  */
-
-/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
-  * @{
-  */  
-/* --- CSR Register ---*/
-/* Alias word address of BRE bit */
-#define BRE_BIT_NUMBER   PWR_CSR_BRE_Pos
-#define CSR_BRE_BB      (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup PWREx_Private_Macros PWREx Private Macros
-  * @{
-  */
-
-/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
-  * @{
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
-                                                ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
-#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
-                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
-#else
-#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
-                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
-                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
-#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ 
-
-#if defined(STM32F446xx)
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
-#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) ||\
-      defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
-      defined(STM32F423xx)
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
-                                ((PIN) == PWR_WAKEUP_PIN3))
-#else
-#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
-#endif /* STM32F446xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32F4xx_HAL_PWR_EX_H */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_pwr_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_PWR_EX_H
+#define __STM32F4xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWREx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+   
+/** @defgroup PWREx_Regulator_state_in_UnderDrive_mode PWREx Regulator state in UnderDrive mode
+  * @{
+  */
+#define PWR_MAINREGULATOR_UNDERDRIVE_ON                       PWR_CR_MRUDS
+#define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON                   ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
+/**
+  * @}
+  */ 
+  
+/** @defgroup PWREx_Over_Under_Drive_Flag PWREx Over Under Drive Flag
+  * @{
+  */
+#define PWR_FLAG_ODRDY                  PWR_CSR_ODRDY
+#define PWR_FLAG_ODSWRDY                PWR_CSR_ODSWRDY
+#define PWR_FLAG_UDRDY                  PWR_CSR_UDSWRDY
+/**
+  * @}
+  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
+  * @{
+  */
+#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)   
+#define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR_VOS             /* Scale 1 mode(default value at reset): the maximum value of fHCLK = 168 MHz. */
+#define PWR_REGULATOR_VOLTAGE_SCALE2         0x00000000U            /* Scale 2 mode: the maximum value of fHCLK = 144 MHz. */
+#else
+#define PWR_REGULATOR_VOLTAGE_SCALE1         PWR_CR_VOS             /* Scale 1 mode(default value at reset): the maximum value of fHCLK is 168 MHz. It can be extended to
+                                                                       180 MHz by activating the over-drive mode. */
+#define PWR_REGULATOR_VOLTAGE_SCALE2         PWR_CR_VOS_1           /* Scale 2 mode: the maximum value of fHCLK is 144 MHz. It can be extended to
+                                                                       168 MHz by activating the over-drive mode. */
+#define PWR_REGULATOR_VOLTAGE_SCALE3         PWR_CR_VOS_0           /* Scale 3 mode: the maximum value of fHCLK is 120 MHz. */
+#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ 
+/**
+  * @}
+  */
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup PWREx_WakeUp_Pins PWREx WakeUp Pins
+  * @{
+  */
+#define PWR_WAKEUP_PIN2                 0x00000080U
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 
+#define PWR_WAKEUP_PIN3                 0x00000040U
+#endif /* STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Zx || STM32F412Vx || \
+          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/**
+  * @}
+  */   
+#endif /* STM32F410xx || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+          STM32F413xx || STM32F423xx */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
+  *  @{
+  */
+
+#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
+/** @brief  macros configure the main internal regulator output voltage.
+  * @param  __REGULATOR__ specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption when the device does
+  *         not operate at the maximum frequency (refer to the datasheets for more details).
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+  * @retval None
+  */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
+                                                            __IO uint32_t tmpreg = 0x00U;                        \
+                                                            MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__));   \
+                                                            /* Delay after an RCC peripheral clock enabling */  \
+                                                            tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS);             \
+                                                            UNUSED(tmpreg);                                     \
+                                                          } while(0U)
+#else
+/** @brief  macros configure the main internal regulator output voltage.
+  * @param  __REGULATOR__ specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption when the device does
+  *         not operate at the maximum frequency (refer to the datasheets for more details).
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
+  * @retval None
+  */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
+                                                            __IO uint32_t tmpreg = 0x00U;                        \
+                                                            MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__));   \
+                                                            /* Delay after an RCC peripheral clock enabling */  \
+                                                            tmpreg = READ_BIT(PWR->CR, PWR_CR_VOS);             \
+                                                            UNUSED(tmpreg);                                     \
+                                                          } while(0U)
+#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ 
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief Macros to enable or disable the Over drive mode.
+  * @note  These macros can be used only for STM32F42xx/STM3243xx devices.
+  */
+#define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)
+#define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
+
+/** @brief Macros to enable or disable the Over drive switching.
+  * @note  These macros can be used only for STM32F42xx/STM3243xx devices. 
+  */
+#define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
+#define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
+
+/** @brief Macros to enable or disable the Under drive mode.
+  * @note  This mode is enabled only with STOP low power mode.
+  *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
+  *        mode is only available when the main regulator or the low power regulator 
+  *        is in low voltage mode.      
+  * @note  If the Under-drive mode was enabled, it is automatically disabled after 
+  *        exiting Stop mode. 
+  *        When the voltage regulator operates in Under-drive mode, an additional  
+  *        startup delay is induced when waking up from Stop mode.
+  */
+#define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
+#define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))
+
+/** @brief  Check PWR flag is set or not.
+  * @note   These macros can be used only for STM32F42xx/STM3243xx devices.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
+  *                                 is ready 
+  *            @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
+  *                                   switching is ready  
+  *            @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
+  *                                 is enabled in Stop mode
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the Under-Drive Ready flag.
+  * @note  These macros can be used only for STM32F42xx/STM3243xx devices.
+  */
+#define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
+  *  @{
+  */
+ 
+/** @addtogroup PWREx_Exported_Functions_Group1
+  * @{
+  */
+void HAL_PWREx_EnableFlashPowerDown(void);
+void HAL_PWREx_DisableFlashPowerDown(void); 
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void); 
+uint32_t HAL_PWREx_GetVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
+    defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) ||\
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
+void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
+void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
+void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
+#endif /* STM32F410xx || STM32F401xC || STM32F401xE || STM32F411xE || STM32F412Zx || STM32F412Vx ||\
+          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void);
+HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void);
+HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup PWREx_Private_Constants PWREx Private Constants
+  * @{
+  */
+
+/** @defgroup PWREx_register_alias_address PWREx Register alias address
+  * @{
+  */
+/* ------------- PWR registers bit address in the alias region ---------------*/
+/* --- CR Register ---*/
+/* Alias word address of FPDS bit */
+#define FPDS_BIT_NUMBER          PWR_CR_FPDS_Pos
+#define CR_FPDS_BB               (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
+
+/* Alias word address of ODEN bit   */
+#define ODEN_BIT_NUMBER          PWR_CR_ODEN_Pos
+#define CR_ODEN_BB               (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))
+
+/* Alias word address of ODSWEN bit */
+#define ODSWEN_BIT_NUMBER        PWR_CR_ODSWEN_Pos
+#define CR_ODSWEN_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))
+    
+/* Alias word address of MRLVDS bit */
+#define MRLVDS_BIT_NUMBER        PWR_CR_MRLVDS_Pos
+#define CR_MRLVDS_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))
+
+/* Alias word address of LPLVDS bit */
+#define LPLVDS_BIT_NUMBER        PWR_CR_LPLVDS_Pos
+#define CR_LPLVDS_BB             (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))
+
+ /**
+  * @}
+  */
+
+/** @defgroup PWREx_CSR_register_alias PWRx CSR Register alias address
+  * @{
+  */  
+/* --- CSR Register ---*/
+/* Alias word address of BRE bit */
+#define BRE_BIT_NUMBER   PWR_CSR_BRE_Pos
+#define CSR_BRE_BB      (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PWREx_Private_Macros PWREx Private Macros
+  * @{
+  */
+
+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
+                                                ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
+#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
+#else
+#define IS_PWR_VOLTAGE_SCALING_RANGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
+                                               ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
+#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx */ 
+
+#if defined(STM32F446xx)
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2))
+#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F412Zx) ||\
+      defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+      defined(STM32F423xx)
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) || \
+                                ((PIN) == PWR_WAKEUP_PIN3))
+#else
+#define IS_PWR_WAKEUP_PIN(PIN) ((PIN) == PWR_WAKEUP_PIN1)
+#endif /* STM32F446xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F4xx_HAL_PWR_EX_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h
index dcf5814..908432d 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h
@@ -1,1459 +1,1459 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_rcc.h
-  * @author  MCD Application Team
-  * @brief   Header file of RCC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_RCC_H
-#define __STM32F4xx_HAL_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/* Include RCC HAL Extended module */
-/* (include on top of file since RCC structures are defined in extended file) */
-#include "stm32f4xx_hal_rcc_ex.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RCC_Exported_Types RCC Exported Types
-  * @{
-  */
-
-/**
-  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
-  */
-typedef struct
-{
-  uint32_t OscillatorType;       /*!< The oscillators to be configured.
-                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */
-
-  uint32_t HSEState;             /*!< The new state of the HSE.
-                                      This parameter can be a value of @ref RCC_HSE_Config                        */
-
-  uint32_t LSEState;             /*!< The new state of the LSE.
-                                      This parameter can be a value of @ref RCC_LSE_Config                        */
-
-  uint32_t HSIState;             /*!< The new state of the HSI.
-                                      This parameter can be a value of @ref RCC_HSI_Config                        */
-
-  uint32_t HSICalibrationValue;  /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
-                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
-
-  uint32_t LSIState;             /*!< The new state of the LSI.
-                                      This parameter can be a value of @ref RCC_LSI_Config                        */
-
-  RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */
-}RCC_OscInitTypeDef;
-
-/**
-  * @brief  RCC System, AHB and APB busses clock configuration structure definition
-  */
-typedef struct
-{
-  uint32_t ClockType;             /*!< The clock to be configured.
-                                       This parameter can be a value of @ref RCC_System_Clock_Type      */
-
-  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
-                                       This parameter can be a value of @ref RCC_System_Clock_Source    */
-
-  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_AHB_Clock_Source       */
-
-  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
-  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
-}RCC_ClkInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants RCC Exported Constants
-  * @{
-  */
-
-/** @defgroup RCC_Oscillator_Type Oscillator Type
-  * @{
-  */
-#define RCC_OSCILLATORTYPE_NONE            0x00000000U
-#define RCC_OSCILLATORTYPE_HSE             0x00000001U
-#define RCC_OSCILLATORTYPE_HSI             0x00000002U
-#define RCC_OSCILLATORTYPE_LSE             0x00000004U
-#define RCC_OSCILLATORTYPE_LSI             0x00000008U
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSE_Config HSE Config
-  * @{
-  */
-#define RCC_HSE_OFF                      0x00000000U
-#define RCC_HSE_ON                       RCC_CR_HSEON
-#define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSE_Config LSE Config
-  * @{
-  */
-#define RCC_LSE_OFF                    0x00000000U
-#define RCC_LSE_ON                     RCC_BDCR_LSEON
-#define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSI_Config HSI Config
-  * @{
-  */
-#define RCC_HSI_OFF                      ((uint8_t)0x00)
-#define RCC_HSI_ON                       ((uint8_t)0x01)
-
-#define RCC_HSICALIBRATION_DEFAULT       0x10U         /* Default HSI calibration trimming value */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSI_Config LSI Config
-  * @{
-  */
-#define RCC_LSI_OFF                      ((uint8_t)0x00)
-#define RCC_LSI_ON                       ((uint8_t)0x01)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Config PLL Config
-  * @{
-  */
-#define RCC_PLL_NONE                      ((uint8_t)0x00)
-#define RCC_PLL_OFF                       ((uint8_t)0x01)
-#define RCC_PLL_ON                        ((uint8_t)0x02)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
-  * @{
-  */
-#define RCC_PLLP_DIV2                  0x00000002U
-#define RCC_PLLP_DIV4                  0x00000004U
-#define RCC_PLLP_DIV6                  0x00000006U
-#define RCC_PLLP_DIV8                  0x00000008U
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
-  * @{
-  */
-#define RCC_PLLSOURCE_HSI                RCC_PLLCFGR_PLLSRC_HSI
-#define RCC_PLLSOURCE_HSE                RCC_PLLCFGR_PLLSRC_HSE
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Type System Clock Type
-  * @{
-  */
-#define RCC_CLOCKTYPE_SYSCLK             0x00000001U
-#define RCC_CLOCKTYPE_HCLK               0x00000002U
-#define RCC_CLOCKTYPE_PCLK1              0x00000004U
-#define RCC_CLOCKTYPE_PCLK2              0x00000008U
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Source System Clock Source
-  * @note     The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for
-  *           STM32F446xx devices.
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI
-#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE
-#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL
-#define RCC_SYSCLKSOURCE_PLLRCLK         ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
-  * @note     The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for
-  *           STM32F446xx devices.
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_STATUS_HSI     RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_HSE     RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLCLK  RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
-#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1))   /*!< PLLR used as system clock */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
-  * @{
-  */
-#define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1
-#define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2
-#define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4
-#define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8
-#define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16
-#define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64
-#define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128
-#define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256
-#define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
-  * @{
-  */
-#define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1
-#define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2
-#define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4
-#define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8
-#define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16
-/**
-  * @}
-  */
-
-/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
-  * @{
-  */
-#define RCC_RTCCLKSOURCE_NO_CLK          0x00000000U
-#define RCC_RTCCLKSOURCE_LSE             0x00000100U
-#define RCC_RTCCLKSOURCE_LSI             0x00000200U
-#define RCC_RTCCLKSOURCE_HSE_DIVX        0x00000300U
-#define RCC_RTCCLKSOURCE_HSE_DIV2        0x00020300U
-#define RCC_RTCCLKSOURCE_HSE_DIV3        0x00030300U
-#define RCC_RTCCLKSOURCE_HSE_DIV4        0x00040300U
-#define RCC_RTCCLKSOURCE_HSE_DIV5        0x00050300U
-#define RCC_RTCCLKSOURCE_HSE_DIV6        0x00060300U
-#define RCC_RTCCLKSOURCE_HSE_DIV7        0x00070300U
-#define RCC_RTCCLKSOURCE_HSE_DIV8        0x00080300U
-#define RCC_RTCCLKSOURCE_HSE_DIV9        0x00090300U
-#define RCC_RTCCLKSOURCE_HSE_DIV10       0x000A0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV11       0x000B0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV12       0x000C0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV13       0x000D0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV14       0x000E0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV15       0x000F0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV16       0x00100300U
-#define RCC_RTCCLKSOURCE_HSE_DIV17       0x00110300U
-#define RCC_RTCCLKSOURCE_HSE_DIV18       0x00120300U
-#define RCC_RTCCLKSOURCE_HSE_DIV19       0x00130300U
-#define RCC_RTCCLKSOURCE_HSE_DIV20       0x00140300U
-#define RCC_RTCCLKSOURCE_HSE_DIV21       0x00150300U
-#define RCC_RTCCLKSOURCE_HSE_DIV22       0x00160300U
-#define RCC_RTCCLKSOURCE_HSE_DIV23       0x00170300U
-#define RCC_RTCCLKSOURCE_HSE_DIV24       0x00180300U
-#define RCC_RTCCLKSOURCE_HSE_DIV25       0x00190300U
-#define RCC_RTCCLKSOURCE_HSE_DIV26       0x001A0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV27       0x001B0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV28       0x001C0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV29       0x001D0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV30       0x001E0300U
-#define RCC_RTCCLKSOURCE_HSE_DIV31       0x001F0300U
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCO_Index MCO Index
-  * @{
-  */
-#define RCC_MCO1                         0x00000000U
-#define RCC_MCO2                         0x00000001U
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
-  * @{
-  */
-#define RCC_MCO1SOURCE_HSI               0x00000000U
-#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0
-#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1
-#define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO1
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
-  * @{
-  */
-#define RCC_MCODIV_1                    0x00000000U
-#define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_2
-#define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
-#define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
-#define RCC_MCODIV_5                    RCC_CFGR_MCO1PRE
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Interrupt Interrupts
-  * @{
-  */
-#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
-#define RCC_IT_LSERDY                    ((uint8_t)0x02)
-#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
-#define RCC_IT_HSERDY                    ((uint8_t)0x08)
-#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
-#define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20)
-#define RCC_IT_CSS                       ((uint8_t)0x80)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Flag Flags
-  *        Elements values convention: 0XXYYYYYb
-  *           - YYYYY  : Flag position in the register
-  *           - 0XX  : Register index
-  *                 - 01: CR register
-  *                 - 10: BDCR register
-  *                 - 11: CSR register
-  * @{
-  */
-/* Flags in the CR register */
-#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
-#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
-#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
-#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3B)
-
-/* Flags in the BDCR register */
-#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
-
-/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
-#define RCC_FLAG_BORRST                  ((uint8_t)0x79)
-#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
-#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
-#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
-#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
-#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
-#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCC_Exported_Macros RCC Exported Macros
-  * @{
-  */
-
-/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-#define __HAL_RCC_GPIOC_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-#define __HAL_RCC_GPIOH_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
-                                        UNUSED(tmpreg); \
-                                         } while(0U)
-#define __HAL_RCC_DMA1_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
-                                        UNUSED(tmpreg); \
-                                         } while(0U)
-#define __HAL_RCC_DMA2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-
-#define __HAL_RCC_GPIOA_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
-#define __HAL_RCC_GPIOB_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
-#define __HAL_RCC_GPIOC_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
-#define __HAL_RCC_GPIOH_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
-#define __HAL_RCC_DMA1_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
-#define __HAL_RCC_DMA2_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
-#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED()         ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED()         ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
-
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
-#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
-#define __HAL_RCC_DMA1_IS_CLK_DISABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM5_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-#define __HAL_RCC_WWDG_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-#define __HAL_RCC_SPI2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-#define __HAL_RCC_USART2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-#define __HAL_RCC_I2C1_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-#define __HAL_RCC_I2C2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-#define __HAL_RCC_PWR_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-
-#define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
-#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
-#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
-#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
-#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_PWR_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
-#define __HAL_RCC_WWDG_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
-#define __HAL_RCC_SPI2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
-#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
-#define __HAL_RCC_I2C1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
-#define __HAL_RCC_I2C2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
-#define __HAL_RCC_PWR_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
-
-#define __HAL_RCC_TIM5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
-#define __HAL_RCC_WWDG_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
-#define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
-#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
-#define __HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
-#define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
-#define __HAL_RCC_PWR_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM1_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-#define __HAL_RCC_USART1_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-#define __HAL_RCC_USART6_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-#define __HAL_RCC_ADC1_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-#define __HAL_RCC_SPI1_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-#define __HAL_RCC_TIM9_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-#define __HAL_RCC_TIM11_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
-                                        UNUSED(tmpreg); \
-                                          } while(0U)
-
-#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
-#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
-#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
-#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
-#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
-#define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
-#define __HAL_RCC_TIM11_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
-#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
-#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
-#define __HAL_RCC_ADC1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
-#define __HAL_RCC_SPI1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
-#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
-#define __HAL_RCC_TIM9_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
-#define __HAL_RCC_TIM11_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
-
-#define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
-#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
-#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
-#define __HAL_RCC_ADC1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
-#define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
-#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
-#define __HAL_RCC_TIM9_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
-#define __HAL_RCC_TIM11_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_GPIOA_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
-#define __HAL_RCC_GPIOB_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
-#define __HAL_RCC_GPIOC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
-#define __HAL_RCC_GPIOH_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
-#define __HAL_RCC_DMA1_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
-#define __HAL_RCC_DMA2_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
-
-#define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00U)
-#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
-#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
-#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
-#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
-#define __HAL_RCC_DMA1_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
-#define __HAL_RCC_DMA2_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_TIM5_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_WWDG_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_PWR_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
-
-#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U)
-#define __HAL_RCC_TIM5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
-#define __HAL_RCC_WWDG_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
-#define __HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
-#define __HAL_RCC_I2C1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
-#define __HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
-#define __HAL_RCC_PWR_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_TIM1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
-#define __HAL_RCC_USART1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-#define __HAL_RCC_USART6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
-#define __HAL_RCC_ADC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
-#define __HAL_RCC_SPI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_SYSCFG_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
-#define __HAL_RCC_TIM9_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM11_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
-
-#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)
-#define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
-#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
-#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
-#define __HAL_RCC_ADC_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
-#define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
-#define __HAL_RCC_TIM9_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
-#define __HAL_RCC_TIM11_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
-#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
-#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
-#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
-#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
-#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
-
-#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
-#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
-#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
-#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
-#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
-#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
-#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
-#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
-
-#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
-#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
-#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
-#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
-#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
-#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
-#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
-#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
-#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
-#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
-#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
-#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
-#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
-
-#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
-#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
-#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
-#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
-#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
-#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
-#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
-#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSI_Configuration HSI Configuration
-  * @{
-  */
-
-/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
-  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
-  *         It is used (enabled by hardware) as system clock source after startup
-  *         from Reset, wake-up from STOP and STANDBY mode, or in case of failure
-  *         of the HSE used directly or indirectly as system clock (if the Clock
-  *         Security System CSS is enabled).
-  * @note   HSI can not be stopped if it is used as system clock source. In this case,
-  *         you have to select another source of the system clock then stop the HSI.
-  * @note   After enabling the HSI, the application software should wait on HSIRDY
-  *         flag to be set indicating that HSI clock is stable and can be used as
-  *         system clock source.
-  *         This parameter can be: ENABLE or DISABLE.
-  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
-  *         clock cycles.
-  */
-#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
-#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
-
-/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
-  * @note   The calibration is used to compensate for the variations in voltage
-  *         and temperature that influence the frequency of the internal HSI RC.
-  * @param  __HSICalibrationValue__ specifies the calibration trimming value.
-  *         (default is RCC_HSICALIBRATION_DEFAULT).
-  *         This parameter must be a number between 0 and 0x1F.
-  */
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
-        RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSI_Configuration LSI Configuration
-  * @{
-  */
-
-/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
-  * @note   After enabling the LSI, the application software should wait on
-  *         LSIRDY flag to be set indicating that LSI clock is stable and can
-  *         be used to clock the IWDG and/or the RTC.
-  * @note   LSI can not be disabled if the IWDG is running.
-  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
-  *         clock cycles.
-  */
-#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
-#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSE_Configuration HSE Configuration
-  * @{
-  */
-
-/**
-  * @brief  Macro to configure the External High Speed oscillator (HSE).
-  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
-  *         User should request a transition to HSE Off first and then HSE On or HSE Bypass.
-  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
-  *         software should wait on HSERDY flag to be set indicating that HSE clock
-  *         is stable and can be used to clock the PLL and/or system clock.
-  * @note   HSE state can not be changed if it is used directly or through the
-  *         PLL as system clock. In this case, you have to select another source
-  *         of the system clock then change the HSE state (ex. disable it).
-  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
-  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
-  *         was previously enabled you have to enable it again after calling this
-  *         function.
-  * @param  __STATE__ specifies the new state of the HSE.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
-  *                              6 HSE oscillator clock cycles.
-  *            @arg RCC_HSE_ON: turn ON the HSE oscillator.
-  *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
-  */
-#define __HAL_RCC_HSE_CONFIG(__STATE__)                         \
-                    do {                                        \
-                      if ((__STATE__) == RCC_HSE_ON)            \
-                      {                                         \
-                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
-                      }                                         \
-                      else if ((__STATE__) == RCC_HSE_BYPASS)   \
-                      {                                         \
-                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \
-                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
-                      }                                         \
-                      else                                      \
-                      {                                         \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
-                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
-                      }                                         \
-                    } while(0U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSE_Configuration LSE Configuration
-  * @{
-  */
-
-/**
-  * @brief  Macro to configure the External Low Speed oscillator (LSE).
-  * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
-  *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.
-  * @note   As the LSE is in the Backup domain and write access is denied to
-  *         this domain after reset, you have to enable write access using
-  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
-  *         (to be done once after reset).
-  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
-  *         software should wait on LSERDY flag to be set indicating that LSE clock
-  *         is stable and can be used to clock the RTC.
-  * @param  __STATE__ specifies the new state of the LSE.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
-  *                              6 LSE oscillator clock cycles.
-  *            @arg RCC_LSE_ON: turn ON the LSE oscillator.
-  *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
-  */
-#define __HAL_RCC_LSE_CONFIG(__STATE__) \
-                    do {                                       \
-                      if((__STATE__) == RCC_LSE_ON)            \
-                      {                                        \
-                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
-                      }                                        \
-                      else if((__STATE__) == RCC_LSE_BYPASS)   \
-                      {                                        \
-                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
-                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
-                      }                                        \
-                      else                                     \
-                      {                                        \
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
-                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
-                      }                                        \
-                    } while(0U)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
-  * @{
-  */
-
-/** @brief  Macros to enable or disable the RTC clock.
-  * @note   These macros must be used only after the RTC clock source was selected.
-  */
-#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
-#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
-
-/** @brief  Macros to configure the RTC clock (RTCCLK).
-  * @note   As the RTC clock configuration bits are in the Backup domain and write
-  *         access is denied to this domain after reset, you have to enable write
-  *         access using the Power Backup Access macro before to configure
-  *         the RTC clock source (to be done once after reset).
-  * @note   Once the RTC clock is configured it can't be changed unless the
-  *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
-  *         a Power On Reset (POR).
-  * @param  __RTCCLKSource__ specifies the RTC clock source.
-  *         This parameter can be one of the following values:
-  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK : No clock selected as RTC clock.
-  *            @arg @ref RCC_RTCCLKSOURCE_LSE : LSE selected as RTC clock.
-  *            @arg @ref RCC_RTCCLKSOURCE_LSI : LSI selected as RTC clock.
-  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
-  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
-  *         work in STOP and STANDBY modes, and can be used as wake-up source.
-  *         However, when the HSE clock is used as RTC clock source, the RTC
-  *         cannot be used in STOP and STANDBY modes.
-  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
-  *         RTC clock source).
-  */
-#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
-                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
-
-#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
-                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \
-                                                   } while(0U)
-
-/** @brief Macro to get the RTC clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
-  *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
-  *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
-  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
-  */
-#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
-
-/**
-  * @brief   Get the RTC and HSE clock divider (RTCPRE).
-  * @retval Returned value can be one of the following values:
- *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
-  */
-#define  __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
-
-/** @brief  Macros to force or release the Backup domain reset.
-  * @note   This function resets the RTC peripheral (including the backup registers)
-  *         and the RTC clock source selection in RCC_CSR register.
-  * @note   The BKPSRAM is not affected by this reset.
-  */
-#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
-#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Configuration PLL Configuration
-  * @{
-  */
-
-/** @brief  Macros to enable or disable the main PLL.
-  * @note   After enabling the main PLL, the application software should wait on
-  *         PLLRDY flag to be set indicating that PLL clock is stable and can
-  *         be used as system clock source.
-  * @note   The main PLL can not be disabled if it is used as system clock source
-  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
-  */
-#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
-#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
-
-/** @brief  Macro to configure the PLL clock source.
-  * @note   This function must be used only when the main PLL is disabled.
-  * @param  __PLLSOURCE__ specifies the PLL entry clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
-  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
-  *
-  */
-#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
-
-/** @brief  Macro to configure the PLL multiplication factor.
-  * @note   This function must be used only when the main PLL is disabled.
-  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 2 MHz to limit PLL jitter.
-  *
-  */
-#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Get_Clock_source Get Clock source
-  * @{
-  */
-/**
-  * @brief Macro to configure the system clock source.
-  * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
-  * This parameter can be one of the following values:
-  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
-  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
-  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
-  *              - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This
-  *                parameter is available only for STM32F446xx devices.
-  */
-#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
-
-/** @brief  Macro to get the clock source used as system clock.
-  * @retval The clock source used as system clock. The returned value can be one
-  *         of the following:
-  *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
-  *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
-  *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
-  *              - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter
-  *                is available only for STM32F446xx devices.
-  */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
-
-/** @brief  Macro to get the oscillator used as PLL clock source.
-  * @retval The oscillator used as PLL clock source. The returned value can be one
-  *         of the following:
-  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
-  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
-  */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
-  * @{
-  */
-
-/** @brief  Macro to configure the MCO1 clock.
-  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
-  * @param  __MCODIV__ specifies the MCO clock prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
-  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
-  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
-  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
-  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
-  */
-#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
-                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
-
-/** @brief  Macro to configure the MCO2 clock.
-  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
-  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
-  *            @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
-  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
-  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
-  * @param  __MCODIV__ specifies the MCO clock prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
-  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
-  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
-  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
-  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
-  * @note  For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
-  *        at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
-  */
-#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
-    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
-  * @brief macros to manage the specified RCC Flags and interrupts.
-  * @{
-  */
-
-/** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
-  *         the selected interrupts).
-  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
-  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
-  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
-  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
-  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
-  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
-  */
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
-
-/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
-  *        the selected interrupts).
-  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
-  *         This parameter can be any combination of the following values:
-  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
-  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
-  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
-  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
-  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
-  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
-  */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
-
-/** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
-  *         bits to clear the selected interrupt pending bits.
-  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
-  *         This parameter can be any combination of the following values:
-  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
-  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
-  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
-  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
-  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
-  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
-  *            @arg RCC_IT_CSS: Clock Security System interrupt
-  */
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
-
-/** @brief  Check the RCC's interrupt has occurred or not.
-  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
-  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
-  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
-  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
-  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
-  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
-  *            @arg RCC_IT_CSS: Clock Security System interrupt
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
-  *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
-  */
-#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
-
-/** @brief  Check RCC flag is set or not.
-  * @param  __FLAG__ specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
-  *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
-  *            @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
-  *            @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
-  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
-  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
-  *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
-  *            @arg RCC_FLAG_PINRST: Pin reset.
-  *            @arg RCC_FLAG_PORRST: POR/PDR reset.
-  *            @arg RCC_FLAG_SFTRST: Software reset.
-  *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
-  *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
-  *            @arg RCC_FLAG_LPWRRST: Low Power reset.
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define RCC_FLAG_MASK  ((uint8_t)0x1FU)
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
- /** @addtogroup RCC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup RCC_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization and de-initialization functions  ******************************/
-HAL_StatusTypeDef HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions  ************************************************/
-void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-void     HAL_RCC_EnableCSS(void);
-void     HAL_RCC_DisableCSS(void);
-uint32_t HAL_RCC_GetSysClockFreq(void);
-uint32_t HAL_RCC_GetHCLKFreq(void);
-uint32_t HAL_RCC_GetPCLK1Freq(void);
-uint32_t HAL_RCC_GetPCLK2Freq(void);
-void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
-void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
-
-/* CSS NMI IRQ handler */
-void HAL_RCC_NMI_IRQHandler(void);
-
-/* User Callbacks in non blocking mode (IT mode) */
-void HAL_RCC_CSSCallback(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Constants RCC Private Constants
-  * @{
-  */
-
-/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
-  * @brief RCC registers bit address in the alias region
-  * @{
-  */
-#define RCC_OFFSET                 (RCC_BASE - PERIPH_BASE)
-/* --- CR Register --- */
-/* Alias word address of HSION bit */
-#define RCC_CR_OFFSET              (RCC_OFFSET + 0x00U)
-#define RCC_HSION_BIT_NUMBER       0x00U
-#define RCC_CR_HSION_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
-/* Alias word address of CSSON bit */
-#define RCC_CSSON_BIT_NUMBER       0x13U
-#define RCC_CR_CSSON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
-/* Alias word address of PLLON bit */
-#define RCC_PLLON_BIT_NUMBER       0x18U
-#define RCC_CR_PLLON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
-
-/* --- BDCR Register --- */
-/* Alias word address of RTCEN bit */
-#define RCC_BDCR_OFFSET            (RCC_OFFSET + 0x70U)
-#define RCC_RTCEN_BIT_NUMBER       0x0FU
-#define RCC_BDCR_RTCEN_BB          (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
-/* Alias word address of BDRST bit */
-#define RCC_BDRST_BIT_NUMBER       0x10U
-#define RCC_BDCR_BDRST_BB          (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
-
-/* --- CSR Register --- */
-/* Alias word address of LSION bit */
-#define RCC_CSR_OFFSET             (RCC_OFFSET + 0x74U)
-#define RCC_LSION_BIT_NUMBER        0x00U
-#define RCC_CSR_LSION_BB           (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
-
-/* CR register byte 3 (Bits[23:16]) base address */
-#define RCC_CR_BYTE2_ADDRESS       0x40023802U
-
-/* CIR register byte 2 (Bits[15:8]) base address */
-#define RCC_CIR_BYTE1_ADDRESS      ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
-
-/* CIR register byte 3 (Bits[23:16]) base address */
-#define RCC_CIR_BYTE2_ADDRESS      ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
-
-/* BDCR register base address */
-#define RCC_BDCR_BYTE0_ADDRESS     (PERIPH_BASE + RCC_BDCR_OFFSET)
-
-#define RCC_DBP_TIMEOUT_VALUE      2U
-#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
-
-#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE          2U  /* 2 ms */
-#define LSI_TIMEOUT_VALUE          2U  /* 2 ms */
-#define CLOCKSWITCH_TIMEOUT_VALUE  5000U /* 5 s */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RCC_Private_Macros RCC Private Macros
-  * @{
-  */
-
-/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
-  * @{
-  */
-#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
-
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
-                         ((HSE) == RCC_HSE_BYPASS))
-
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
-                         ((LSE) == RCC_LSE_BYPASS))
-
-#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
-
-#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
-
-#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
-
-#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
-                                  ((SOURCE) == RCC_PLLSOURCE_HSE))
-
-#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
-                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
-                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
-                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
-
-#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
-                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
-
-#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
-
-#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
-
-#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
-
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1)   || ((HCLK) == RCC_SYSCLK_DIV2)   || \
-                           ((HCLK) == RCC_SYSCLK_DIV4)   || ((HCLK) == RCC_SYSCLK_DIV8)   || \
-                           ((HCLK) == RCC_SYSCLK_DIV16)  || ((HCLK) == RCC_SYSCLK_DIV64)  || \
-                           ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
-                           ((HCLK) == RCC_SYSCLK_DIV512))
-
-#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
-
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
-                           ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
-                           ((PCLK) == RCC_HCLK_DIV16))
-
-#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
-
-#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
-                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
-
-#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2) || \
-                             ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
-                             ((DIV) == RCC_MCODIV_5))
-#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_RCC_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rcc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RCC_H
+#define __STM32F4xx_HAL_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/* Include RCC HAL Extended module */
+/* (include on top of file since RCC structures are defined in extended file) */
+#include "stm32f4xx_hal_rcc_ex.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCC_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
+  */
+typedef struct
+{
+  uint32_t OscillatorType;       /*!< The oscillators to be configured.
+                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */
+
+  uint32_t HSEState;             /*!< The new state of the HSE.
+                                      This parameter can be a value of @ref RCC_HSE_Config                        */
+
+  uint32_t LSEState;             /*!< The new state of the LSE.
+                                      This parameter can be a value of @ref RCC_LSE_Config                        */
+
+  uint32_t HSIState;             /*!< The new state of the HSI.
+                                      This parameter can be a value of @ref RCC_HSI_Config                        */
+
+  uint32_t HSICalibrationValue;  /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
+                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
+
+  uint32_t LSIState;             /*!< The new state of the LSI.
+                                      This parameter can be a value of @ref RCC_LSI_Config                        */
+
+  RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */
+}RCC_OscInitTypeDef;
+
+/**
+  * @brief  RCC System, AHB and APB busses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t ClockType;             /*!< The clock to be configured.
+                                       This parameter can be a value of @ref RCC_System_Clock_Type      */
+
+  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
+                                       This parameter can be a value of @ref RCC_System_Clock_Source    */
+
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_AHB_Clock_Source       */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
+
+}RCC_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_Oscillator_Type Oscillator Type
+  * @{
+  */
+#define RCC_OSCILLATORTYPE_NONE            0x00000000U
+#define RCC_OSCILLATORTYPE_HSE             0x00000001U
+#define RCC_OSCILLATORTYPE_HSI             0x00000002U
+#define RCC_OSCILLATORTYPE_LSE             0x00000004U
+#define RCC_OSCILLATORTYPE_LSI             0x00000008U
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSE_Config HSE Config
+  * @{
+  */
+#define RCC_HSE_OFF                      0x00000000U
+#define RCC_HSE_ON                       RCC_CR_HSEON
+#define RCC_HSE_BYPASS                   ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Config LSE Config
+  * @{
+  */
+#define RCC_LSE_OFF                    0x00000000U
+#define RCC_LSE_ON                     RCC_BDCR_LSEON
+#define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI_Config HSI Config
+  * @{
+  */
+#define RCC_HSI_OFF                      ((uint8_t)0x00)
+#define RCC_HSI_ON                       ((uint8_t)0x01)
+
+#define RCC_HSICALIBRATION_DEFAULT       0x10U         /* Default HSI calibration trimming value */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSI_Config LSI Config
+  * @{
+  */
+#define RCC_LSI_OFF                      ((uint8_t)0x00)
+#define RCC_LSI_ON                       ((uint8_t)0x01)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Config PLL Config
+  * @{
+  */
+#define RCC_PLL_NONE                      ((uint8_t)0x00)
+#define RCC_PLL_OFF                       ((uint8_t)0x01)
+#define RCC_PLL_ON                        ((uint8_t)0x02)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
+  * @{
+  */
+#define RCC_PLLP_DIV2                  0x00000002U
+#define RCC_PLLP_DIV4                  0x00000004U
+#define RCC_PLLP_DIV6                  0x00000006U
+#define RCC_PLLP_DIV8                  0x00000008U
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
+  * @{
+  */
+#define RCC_PLLSOURCE_HSI                RCC_PLLCFGR_PLLSRC_HSI
+#define RCC_PLLSOURCE_HSE                RCC_PLLCFGR_PLLSRC_HSE
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Type System Clock Type
+  * @{
+  */
+#define RCC_CLOCKTYPE_SYSCLK             0x00000001U
+#define RCC_CLOCKTYPE_HCLK               0x00000002U
+#define RCC_CLOCKTYPE_PCLK1              0x00000004U
+#define RCC_CLOCKTYPE_PCLK2              0x00000008U
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source System Clock Source
+  * @note     The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for
+  *           STM32F446xx devices.
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_HSI             RCC_CFGR_SW_HSI
+#define RCC_SYSCLKSOURCE_HSE             RCC_CFGR_SW_HSE
+#define RCC_SYSCLKSOURCE_PLLCLK          RCC_CFGR_SW_PLL
+#define RCC_SYSCLKSOURCE_PLLRCLK         ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
+  * @note     The RCC_SYSCLKSOURCE_STATUS_PLLRCLK parameter is available only for
+  *           STM32F446xx devices.
+  * @{
+  */
+#define RCC_SYSCLKSOURCE_STATUS_HSI     RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_HSE     RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK  RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
+#define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SWS_0 | RCC_CFGR_SWS_1))   /*!< PLLR used as system clock */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
+  * @{
+  */
+#define RCC_SYSCLK_DIV1                  RCC_CFGR_HPRE_DIV1
+#define RCC_SYSCLK_DIV2                  RCC_CFGR_HPRE_DIV2
+#define RCC_SYSCLK_DIV4                  RCC_CFGR_HPRE_DIV4
+#define RCC_SYSCLK_DIV8                  RCC_CFGR_HPRE_DIV8
+#define RCC_SYSCLK_DIV16                 RCC_CFGR_HPRE_DIV16
+#define RCC_SYSCLK_DIV64                 RCC_CFGR_HPRE_DIV64
+#define RCC_SYSCLK_DIV128                RCC_CFGR_HPRE_DIV128
+#define RCC_SYSCLK_DIV256                RCC_CFGR_HPRE_DIV256
+#define RCC_SYSCLK_DIV512                RCC_CFGR_HPRE_DIV512
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
+  * @{
+  */
+#define RCC_HCLK_DIV1                    RCC_CFGR_PPRE1_DIV1
+#define RCC_HCLK_DIV2                    RCC_CFGR_PPRE1_DIV2
+#define RCC_HCLK_DIV4                    RCC_CFGR_PPRE1_DIV4
+#define RCC_HCLK_DIV8                    RCC_CFGR_PPRE1_DIV8
+#define RCC_HCLK_DIV16                   RCC_CFGR_PPRE1_DIV16
+/**
+  * @}
+  */
+
+/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
+  * @{
+  */
+#define RCC_RTCCLKSOURCE_NO_CLK          0x00000000U
+#define RCC_RTCCLKSOURCE_LSE             0x00000100U
+#define RCC_RTCCLKSOURCE_LSI             0x00000200U
+#define RCC_RTCCLKSOURCE_HSE_DIVX        0x00000300U
+#define RCC_RTCCLKSOURCE_HSE_DIV2        0x00020300U
+#define RCC_RTCCLKSOURCE_HSE_DIV3        0x00030300U
+#define RCC_RTCCLKSOURCE_HSE_DIV4        0x00040300U
+#define RCC_RTCCLKSOURCE_HSE_DIV5        0x00050300U
+#define RCC_RTCCLKSOURCE_HSE_DIV6        0x00060300U
+#define RCC_RTCCLKSOURCE_HSE_DIV7        0x00070300U
+#define RCC_RTCCLKSOURCE_HSE_DIV8        0x00080300U
+#define RCC_RTCCLKSOURCE_HSE_DIV9        0x00090300U
+#define RCC_RTCCLKSOURCE_HSE_DIV10       0x000A0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV11       0x000B0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV12       0x000C0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV13       0x000D0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV14       0x000E0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV15       0x000F0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV16       0x00100300U
+#define RCC_RTCCLKSOURCE_HSE_DIV17       0x00110300U
+#define RCC_RTCCLKSOURCE_HSE_DIV18       0x00120300U
+#define RCC_RTCCLKSOURCE_HSE_DIV19       0x00130300U
+#define RCC_RTCCLKSOURCE_HSE_DIV20       0x00140300U
+#define RCC_RTCCLKSOURCE_HSE_DIV21       0x00150300U
+#define RCC_RTCCLKSOURCE_HSE_DIV22       0x00160300U
+#define RCC_RTCCLKSOURCE_HSE_DIV23       0x00170300U
+#define RCC_RTCCLKSOURCE_HSE_DIV24       0x00180300U
+#define RCC_RTCCLKSOURCE_HSE_DIV25       0x00190300U
+#define RCC_RTCCLKSOURCE_HSE_DIV26       0x001A0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV27       0x001B0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV28       0x001C0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV29       0x001D0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV30       0x001E0300U
+#define RCC_RTCCLKSOURCE_HSE_DIV31       0x001F0300U
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO_Index MCO Index
+  * @{
+  */
+#define RCC_MCO1                         0x00000000U
+#define RCC_MCO2                         0x00000001U
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
+  * @{
+  */
+#define RCC_MCO1SOURCE_HSI               0x00000000U
+#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0
+#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1
+#define RCC_MCO1SOURCE_PLLCLK            RCC_CFGR_MCO1
+/**
+  * @}
+  */
+
+/** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
+  * @{
+  */
+#define RCC_MCODIV_1                    0x00000000U
+#define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_2
+#define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
+#define RCC_MCODIV_5                    RCC_CFGR_MCO1PRE
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Interrupt Interrupts
+  * @{
+  */
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
+#define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20)
+#define RCC_IT_CSS                       ((uint8_t)0x80)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flag Flags
+  *        Elements values convention: 0XXYYYYYb
+  *           - YYYYY  : Flag position in the register
+  *           - 0XX  : Register index
+  *                 - 01: CR register
+  *                 - 10: BDCR register
+  *                 - 11: CSR register
+  * @{
+  */
+/* Flags in the CR register */
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
+#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3B)
+
+/* Flags in the BDCR register */
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
+
+/* Flags in the CSR register */
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
+#define RCC_FLAG_BORRST                  ((uint8_t)0x79)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_GPIOC_CLK_ENABLE()  do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_GPIOH_CLK_ENABLE()  do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
+                                        UNUSED(tmpreg); \
+                                         } while(0U)
+#define __HAL_RCC_DMA1_CLK_ENABLE()  do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
+                                        UNUSED(tmpreg); \
+                                         } while(0U)
+#define __HAL_RCC_DMA2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+
+#define __HAL_RCC_GPIOA_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
+#define __HAL_RCC_GPIOB_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
+#define __HAL_RCC_GPIOC_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
+#define __HAL_RCC_GPIOH_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
+#define __HAL_RCC_DMA1_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
+#define __HAL_RCC_DMA2_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED()         ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED()         ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
+
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()       ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
+#define __HAL_RCC_DMA1_IS_CLK_DISABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED()        ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM5_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_WWDG_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_SPI2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_USART2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_I2C1_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_I2C2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_PWR_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+
+#define __HAL_RCC_TIM5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
+#define __HAL_RCC_WWDG_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
+#define __HAL_RCC_SPI2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
+#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
+#define __HAL_RCC_I2C1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
+#define __HAL_RCC_I2C2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
+#define __HAL_RCC_PWR_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
+#define __HAL_RCC_WWDG_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
+#define __HAL_RCC_SPI2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
+#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
+#define __HAL_RCC_I2C1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
+#define __HAL_RCC_I2C2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
+#define __HAL_RCC_PWR_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
+
+#define __HAL_RCC_TIM5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
+#define __HAL_RCC_WWDG_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
+#define __HAL_RCC_SPI2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
+#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
+#define __HAL_RCC_I2C1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
+#define __HAL_RCC_I2C2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
+#define __HAL_RCC_PWR_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM1_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_USART1_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_USART6_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_ADC1_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_SPI1_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_TIM9_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+#define __HAL_RCC_TIM11_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
+                                        UNUSED(tmpreg); \
+                                          } while(0U)
+
+#define __HAL_RCC_TIM1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
+#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
+#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
+#define __HAL_RCC_ADC1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
+#define __HAL_RCC_SPI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
+#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
+#define __HAL_RCC_TIM9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
+#define __HAL_RCC_TIM11_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
+#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
+#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
+#define __HAL_RCC_ADC1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
+#define __HAL_RCC_SPI1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
+#define __HAL_RCC_TIM9_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
+#define __HAL_RCC_TIM11_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
+
+#define __HAL_RCC_TIM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
+#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
+#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
+#define __HAL_RCC_ADC1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
+#define __HAL_RCC_SPI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
+#define __HAL_RCC_TIM9_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
+#define __HAL_RCC_TIM11_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_GPIOA_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
+#define __HAL_RCC_GPIOH_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
+#define __HAL_RCC_DMA1_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
+
+#define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00U)
+#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
+#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
+#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
+#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
+#define __HAL_RCC_DMA1_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
+#define __HAL_RCC_DMA2_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM5_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_WWDG_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_SPI2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_USART2_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_I2C1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_PWR_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
+
+#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U)
+#define __HAL_RCC_TIM5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
+#define __HAL_RCC_WWDG_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
+#define __HAL_RCC_SPI2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
+#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
+#define __HAL_RCC_I2C1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
+#define __HAL_RCC_I2C2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
+#define __HAL_RCC_PWR_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_TIM1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_USART1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_USART6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
+#define __HAL_RCC_ADC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
+#define __HAL_RCC_SPI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_SYSCFG_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_TIM9_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
+#define __HAL_RCC_TIM11_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
+
+#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)
+#define __HAL_RCC_TIM1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
+#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
+#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
+#define __HAL_RCC_ADC_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
+#define __HAL_RCC_SPI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
+#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
+#define __HAL_RCC_TIM9_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
+#define __HAL_RCC_TIM11_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
+
+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
+#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
+
+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
+#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
+#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
+#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
+#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
+
+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
+#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
+#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
+#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSI_Configuration HSI Configuration
+  * @{
+  */
+
+/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  *         It is used (enabled by hardware) as system clock source after startup
+  *         from Reset, wake-up from STOP and STANDBY mode, or in case of failure
+  *         of the HSE used directly or indirectly as system clock (if the Clock
+  *         Security System CSS is enabled).
+  * @note   HSI can not be stopped if it is used as system clock source. In this case,
+  *         you have to select another source of the system clock then stop the HSI.
+  * @note   After enabling the HSI, the application software should wait on HSIRDY
+  *         flag to be set indicating that HSI clock is stable and can be used as
+  *         system clock source.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
+#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
+
+/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  * @param  __HSICalibrationValue__ specifies the calibration trimming value.
+  *         (default is RCC_HSICALIBRATION_DEFAULT).
+  *         This parameter must be a number between 0 and 0x1F.
+  */
+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
+        RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSI_Configuration LSI Configuration
+  * @{
+  */
+
+/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).
+  * @note   After enabling the LSI, the application software should wait on
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
+  *         be used to clock the IWDG and/or the RTC.
+  * @note   LSI can not be disabled if the IWDG is running.
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+  *         clock cycles.
+  */
+#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
+#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_HSE_Configuration HSE Configuration
+  * @{
+  */
+
+/**
+  * @brief  Macro to configure the External High Speed oscillator (HSE).
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
+  *         User should request a transition to HSE Off first and then HSE On or HSE Bypass.
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+  *         software should wait on HSERDY flag to be set indicating that HSE clock
+  *         is stable and can be used to clock the PLL and/or system clock.
+  * @note   HSE state can not be changed if it is used directly or through the
+  *         PLL as system clock. In this case, you have to select another source
+  *         of the system clock then change the HSE state (ex. disable it).
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
+  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
+  *         was previously enabled you have to enable it again after calling this
+  *         function.
+  * @param  __STATE__ specifies the new state of the HSE.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+  *                              6 HSE oscillator clock cycles.
+  *            @arg RCC_HSE_ON: turn ON the HSE oscillator.
+  *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
+  */
+#define __HAL_RCC_HSE_CONFIG(__STATE__)                         \
+                    do {                                        \
+                      if ((__STATE__) == RCC_HSE_ON)            \
+                      {                                         \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
+                      }                                         \
+                      else if ((__STATE__) == RCC_HSE_BYPASS)   \
+                      {                                         \
+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \
+                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \
+                      }                                         \
+                      else                                      \
+                      {                                         \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \
+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \
+                      }                                         \
+                    } while(0U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LSE_Configuration LSE Configuration
+  * @{
+  */
+
+/**
+  * @brief  Macro to configure the External Low Speed oscillator (LSE).
+  * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
+  *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using
+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE
+  *         (to be done once after reset).
+  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
+  *         is stable and can be used to clock the RTC.
+  * @param  __STATE__ specifies the new state of the LSE.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+  *                              6 LSE oscillator clock cycles.
+  *            @arg RCC_LSE_ON: turn ON the LSE oscillator.
+  *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
+  */
+#define __HAL_RCC_LSE_CONFIG(__STATE__) \
+                    do {                                       \
+                      if((__STATE__) == RCC_LSE_ON)            \
+                      {                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
+                      }                                        \
+                      else if((__STATE__) == RCC_LSE_BYPASS)   \
+                      {                                        \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \
+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \
+                      }                                        \
+                      else                                     \
+                      {                                        \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \
+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
+                      }                                        \
+                    } while(0U)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
+  * @{
+  */
+
+/** @brief  Macros to enable or disable the RTC clock.
+  * @note   These macros must be used only after the RTC clock source was selected.
+  */
+#define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
+#define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
+
+/** @brief  Macros to configure the RTC clock (RTCCLK).
+  * @note   As the RTC clock configuration bits are in the Backup domain and write
+  *         access is denied to this domain after reset, you have to enable write
+  *         access using the Power Backup Access macro before to configure
+  *         the RTC clock source (to be done once after reset).
+  * @note   Once the RTC clock is configured it can't be changed unless the
+  *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
+  *         a Power On Reset (POR).
+  * @param  __RTCCLKSource__ specifies the RTC clock source.
+  *         This parameter can be one of the following values:
+  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK : No clock selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_LSE : LSE selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_LSI : LSI selected as RTC clock.
+  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
+  *         work in STOP and STANDBY modes, and can be used as wake-up source.
+  *         However, when the HSE clock is used as RTC clock source, the RTC
+  *         cannot be used in STOP and STANDBY modes.
+  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
+  *         RTC clock source).
+  */
+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \
+                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
+
+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \
+                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \
+                                                   } while(0U)
+
+/** @brief Macro to get the RTC clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
+  *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
+  *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
+  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
+  */
+#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
+
+/**
+  * @brief   Get the RTC and HSE clock divider (RTCPRE).
+  * @retval Returned value can be one of the following values:
+ *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
+  */
+#define  __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
+
+/** @brief  Macros to force or release the Backup domain reset.
+  * @note   This function resets the RTC peripheral (including the backup registers)
+  *         and the RTC clock source selection in RCC_CSR register.
+  * @note   The BKPSRAM is not affected by this reset.
+  */
+#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
+#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_PLL_Configuration PLL Configuration
+  * @{
+  */
+
+/** @brief  Macros to enable or disable the main PLL.
+  * @note   After enabling the main PLL, the application software should wait on
+  *         PLLRDY flag to be set indicating that PLL clock is stable and can
+  *         be used as system clock source.
+  * @note   The main PLL can not be disabled if it is used as system clock source
+  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
+#define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
+
+/** @brief  Macro to configure the PLL clock source.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __PLLSOURCE__ specifies the PLL entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  *
+  */
+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
+
+/** @brief  Macro to configure the PLL multiplication factor.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 2 MHz to limit PLL jitter.
+  *
+  */
+#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Get_Clock_source Get Clock source
+  * @{
+  */
+/**
+  * @brief Macro to configure the system clock source.
+  * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
+  * This parameter can be one of the following values:
+  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
+  *              - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This
+  *                parameter is available only for STM32F446xx devices.
+  */
+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
+
+/** @brief  Macro to get the clock source used as system clock.
+  * @retval The clock source used as system clock. The returned value can be one
+  *         of the following:
+  *              - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
+  *              - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
+  *              - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
+  *              - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter
+  *                is available only for STM32F446xx devices.
+  */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
+
+/** @brief  Macro to get the oscillator used as PLL clock source.
+  * @retval The oscillator used as PLL clock source. The returned value can be one
+  *         of the following:
+  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
+  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
+  */
+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
+  * @{
+  */
+
+/** @brief  Macro to configure the MCO1 clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
+  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+  */
+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
+
+/** @brief  Macro to configure the MCO2 clock.
+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
+  *            @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
+  * @param  __MCODIV__ specifies the MCO clock prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
+  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+  * @note  For STM32F410Rx devices, to output I2SCLK clock on MCO2, you should have
+  *        at least one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
+  */
+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 3U)));
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
+  * @brief macros to manage the specified RCC Flags and interrupts.
+  * @{
+  */
+
+/** @brief  Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
+  *         the selected interrupts).
+  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
+  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+  */
+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
+
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
+  *        the selected interrupts).
+  * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
+  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+  */
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
+
+/** @brief  Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
+  *         bits to clear the selected interrupt pending bits.
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *         This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
+  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+  *            @arg RCC_IT_CSS: Clock Security System interrupt
+  */
+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
+
+/** @brief  Check the RCC's interrupt has occurred or not.
+  * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
+  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+  *            @arg RCC_IT_CSS: Clock Security System interrupt
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
+  *        RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
+  */
+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
+
+/** @brief  Check RCC flag is set or not.
+  * @param  __FLAG__ specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
+  *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
+  *            @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
+  *            @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
+  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
+  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
+  *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
+  *            @arg RCC_FLAG_PINRST: Pin reset.
+  *            @arg RCC_FLAG_PORRST: POR/PDR reset.
+  *            @arg RCC_FLAG_SFTRST: Software reset.
+  *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
+  *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
+  *            @arg RCC_FLAG_LPWRRST: Low Power reset.
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define RCC_FLAG_MASK  ((uint8_t)0x1FU)
+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR :((((__FLAG__) >> 5U) == 3U)? RCC->CSR :RCC->CIR))) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+ /** @addtogroup RCC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
+/**
+  * @}
+  */
+
+/** @addtogroup RCC_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
+void     HAL_RCC_EnableCSS(void);
+void     HAL_RCC_DisableCSS(void);
+uint32_t HAL_RCC_GetSysClockFreq(void);
+uint32_t HAL_RCC_GetHCLKFreq(void);
+uint32_t HAL_RCC_GetPCLK1Freq(void);
+uint32_t HAL_RCC_GetPCLK2Freq(void);
+void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
+void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
+
+/* CSS NMI IRQ handler */
+void HAL_RCC_NMI_IRQHandler(void);
+
+/* User Callbacks in non blocking mode (IT mode) */
+void HAL_RCC_CSSCallback(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Constants RCC Private Constants
+  * @{
+  */
+
+/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
+  * @brief RCC registers bit address in the alias region
+  * @{
+  */
+#define RCC_OFFSET                 (RCC_BASE - PERIPH_BASE)
+/* --- CR Register --- */
+/* Alias word address of HSION bit */
+#define RCC_CR_OFFSET              (RCC_OFFSET + 0x00U)
+#define RCC_HSION_BIT_NUMBER       0x00U
+#define RCC_CR_HSION_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_HSION_BIT_NUMBER * 4U))
+/* Alias word address of CSSON bit */
+#define RCC_CSSON_BIT_NUMBER       0x13U
+#define RCC_CR_CSSON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))
+/* Alias word address of PLLON bit */
+#define RCC_PLLON_BIT_NUMBER       0x18U
+#define RCC_CR_PLLON_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
+
+/* --- BDCR Register --- */
+/* Alias word address of RTCEN bit */
+#define RCC_BDCR_OFFSET            (RCC_OFFSET + 0x70U)
+#define RCC_RTCEN_BIT_NUMBER       0x0FU
+#define RCC_BDCR_RTCEN_BB          (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))
+/* Alias word address of BDRST bit */
+#define RCC_BDRST_BIT_NUMBER       0x10U
+#define RCC_BDCR_BDRST_BB          (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
+
+/* --- CSR Register --- */
+/* Alias word address of LSION bit */
+#define RCC_CSR_OFFSET             (RCC_OFFSET + 0x74U)
+#define RCC_LSION_BIT_NUMBER        0x00U
+#define RCC_CSR_LSION_BB           (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32U) + (RCC_LSION_BIT_NUMBER * 4U))
+
+/* CR register byte 3 (Bits[23:16]) base address */
+#define RCC_CR_BYTE2_ADDRESS       0x40023802U
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define RCC_CIR_BYTE1_ADDRESS      ((uint32_t)(RCC_BASE + 0x0CU + 0x01U))
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define RCC_CIR_BYTE2_ADDRESS      ((uint32_t)(RCC_BASE + 0x0CU + 0x02U))
+
+/* BDCR register base address */
+#define RCC_BDCR_BYTE0_ADDRESS     (PERIPH_BASE + RCC_BDCR_OFFSET)
+
+#define RCC_DBP_TIMEOUT_VALUE      2U
+#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
+
+#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
+#define HSI_TIMEOUT_VALUE          2U  /* 2 ms */
+#define LSI_TIMEOUT_VALUE          2U  /* 2 ms */
+#define CLOCKSWITCH_TIMEOUT_VALUE  5000U /* 5 s */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RCC_Private_Macros RCC Private Macros
+  * @{
+  */
+
+/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
+  * @{
+  */
+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
+
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_BYPASS))
+
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_BYPASS))
+
+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
+
+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
+
+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
+
+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
+                                  ((SOURCE) == RCC_PLLSOURCE_HSE))
+
+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
+                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
+
+#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV3) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV5) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV6) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV7) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV9) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV10) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV11) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV12) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV13) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV14) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV15) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV17) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV18) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV19) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV20) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV21) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV22) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV23) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV24) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV25) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV26) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV27) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV28) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
+                                         ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
+
+#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
+
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
+
+#define IS_RCC_PLLQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
+
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1)   || ((HCLK) == RCC_SYSCLK_DIV2)   || \
+                           ((HCLK) == RCC_SYSCLK_DIV4)   || ((HCLK) == RCC_SYSCLK_DIV8)   || \
+                           ((HCLK) == RCC_SYSCLK_DIV16)  || ((HCLK) == RCC_SYSCLK_DIV64)  || \
+                           ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
+                           ((HCLK) == RCC_SYSCLK_DIV512))
+
+#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 15U))
+
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
+                           ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
+                           ((PCLK) == RCC_HCLK_DIV16))
+
+#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
+
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
+                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
+
+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2) || \
+                             ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
+                             ((DIV) == RCC_MCODIV_5))
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RCC_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h
index 909a717..1ac56e1 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h
@@ -1,7111 +1,7111 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_rcc_ex.h
-  * @author  MCD Application Team
-  * @brief   Header file of RCC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_RCC_EX_H
-#define __STM32F4xx_HAL_RCC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCCEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
-  * @{
-  */
-
-/**
-  * @brief  RCC PLL configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PLLState;   /*!< The new state of the PLL.
-                            This parameter can be a value of @ref RCC_PLL_Config                      */
-
-  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
-                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */
-
-  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 63    */
-
-  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432 
-                            except for STM32F411xE devices where the Min_Data = 192 */
-
-  uint32_t PLLP;       /*!< PLLP: Division factor for main system clock (SYSCLK).
-                            This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
-
-  uint32_t PLLQ;       /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 15    */
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
-    defined(STM32F413xx) || defined(STM32F423xx)
-  uint32_t PLLR;       /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
-                            This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx
-                            and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. 
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 7     */
-#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 
-}RCC_PLLInitTypeDef;
-
-#if defined(STM32F446xx)
-/** 
-  * @brief  PLLI2S Clock structure definition  
-  */
-typedef struct
-{
-  uint32_t PLLI2SM;    /*!< Specifies division factor for PLL VCO input clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 63       */
-
-  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432    */
-
-  uint32_t PLLI2SP;    /*!< Specifies division factor for SPDIFRX Clock.
-                            This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider           */
-
-  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */
-                           
-  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source I2S */
-}RCC_PLLI2SInitTypeDef;
-
-/** 
-  * @brief  PLLSAI Clock structure definition  
-  */
-typedef struct
-{
-  uint32_t PLLSAIM;    /*!< Specifies division factor for PLL VCO input clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 63       */
-
-  uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432    */
-
-  uint32_t PLLSAIP;    /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
-                            This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider           */
-                                                             
-  uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-                            This parameter will be used only when PLLSAI is selected as Clock Source SAI */
-}RCC_PLLSAIInitTypeDef;
-
-/** 
-  * @brief  RCC extended clocks structure definition  
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
-                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. 
-                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-  RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters. 
-                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
-
-  uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
-                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */
-
-  uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
-                                      This parameter will be used only when PLLSAI is selected as Clock Source SAI */
-
-  uint32_t Sai1ClockSelection;    /*!< Specifies SAI1 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
-
-  uint32_t Sai2ClockSelection;    /*!< Specifies SAI2 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
-                                      
-  uint32_t I2sApb1ClockSelection;    /*!< Specifies I2S APB1 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
-
-  uint32_t I2sApb2ClockSelection;    /*!< Specifies I2S APB2 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
-
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection. 
-                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
-  uint32_t SdioClockSelection;    /*!< Specifies SDIO Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
-
-  uint32_t CecClockSelection;      /*!< Specifies CEC Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
-
-  uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
-
-  uint32_t SpdifClockSelection;    /*!< Specifies SPDIFRX Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
-
-  uint32_t Clk48ClockSelection;     /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 
-                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
-  
-  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F446xx */   
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/** 
-  * @brief  RCC extended clocks structure definition
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
-                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  uint32_t I2SClockSelection;      /*!< Specifies RTC Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
-                                      
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection. 
-                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
-  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
-  
-  uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
-
-  uint8_t TIMPresSelection;        /*!< Specifies TIM Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-/** 
-  * @brief  PLLI2S Clock structure definition  
-  */
-typedef struct
-{
-  uint32_t PLLI2SM;    /*!< Specifies division factor for PLL VCO input clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 63       */
-
-  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432    */
-
-  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */
-                           
-  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source I2S */
-}RCC_PLLI2SInitTypeDef;
-
-/** 
-  * @brief  RCC extended clocks structure definition
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
-                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. 
-                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S */
-  
-#if defined(STM32F413xx) || defined(STM32F423xx)
-  uint32_t PLLDivR;              /*!< Specifies the PLL division factor for SAI1 clock.
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
-                                      This parameter will be used only when PLL is selected as Clock Source SAI */
-
-  uint32_t PLLI2SDivR;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
-                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */
-#endif /* STM32F413xx || STM32F423xx */  
-                                      
-  uint32_t I2sApb1ClockSelection;    /*!< Specifies I2S APB1 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
-
-  uint32_t I2sApb2ClockSelection;    /*!< Specifies I2S APB2 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
-
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection. 
-                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
-  uint32_t SdioClockSelection;    /*!< Specifies SDIO Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
-
-  uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
-
-  uint32_t Clk48ClockSelection;     /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
-                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
-  
-  uint32_t Dfsdm1ClockSelection;    /*!< Specifies DFSDM1 Clock Selection.
-                                      This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
-
-  uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.
-                                      This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
-  
-#if defined(STM32F413xx) || defined(STM32F423xx)
-  uint32_t Dfsdm2ClockSelection;    /*!< Specifies DFSDM2 Clock Selection.
-                                      This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */
-
-  uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection.
-                                      This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */
-  
-  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
-  
-  uint32_t SaiAClockSelection;     /*!< Specifies SAI1_A Clock Prescalers Selection
-                                        This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */
-
-  uint32_t SaiBClockSelection;     /*!< Specifies SAI1_B Clock Prescalers Selection
-                                        This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */
-#endif /* STM32F413xx || STM32F423xx */
-
-  uint32_t PLLI2SSelection;      /*!< Specifies PLL I2S Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */
-
-  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-
-/** 
-  * @brief  PLLI2S Clock structure definition  
-  */
-typedef struct
-{
-  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI1 clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */
-}RCC_PLLI2SInitTypeDef;
-
-/** 
-  * @brief  PLLSAI Clock structure definition  
-  */
-typedef struct
-{
-  uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 
-#if defined(STM32F469xx) || defined(STM32F479xx)
-  uint32_t PLLSAIP;    /*!< Specifies division factor for OTG FS and SDIO clocks.
-                            This parameter is only available in STM32F469xx/STM32F479xx devices.
-                            This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider  */  
-#endif /* STM32F469xx || STM32F479xx */
-                                 
-  uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI1 clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
-                              
-  uint32_t PLLSAIR;    /*!< specifies the division factor for LTDC clock
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-                            This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
-
-}RCC_PLLSAIInitTypeDef;
-
-/** 
-  * @brief  RCC extended clocks structure definition  
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
-                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. 
-                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-  RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters. 
-                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
-
-  uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
-                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */
-
-  uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
-                                      This parameter will be used only when PLLSAI is selected as Clock Source SAI */
-
-  uint32_t PLLSAIDivR;           /*!< Specifies the PLLSAI division factor for LTDC clock.
-                                      This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
-
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection. 
-                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
-
-  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Prescalers Selection. 
-                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
-#if defined(STM32F469xx) || defined(STM32F479xx)
-  uint32_t Clk48ClockSelection;  /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 
-                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
-
-  uint32_t SdioClockSelection;   /*!< Specifies SDIO Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */  
-#endif /* STM32F469xx || STM32F479xx */  
-}RCC_PeriphCLKInitTypeDef;
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
-/** 
-  * @brief  PLLI2S Clock structure definition  
-  */
-typedef struct
-{
-#if defined(STM32F411xE)
-  uint32_t PLLI2SM;    /*!< PLLM: Division factor for PLLI2S VCO input clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 62  */
-#endif /* STM32F411xE */
-                                
-  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
-                            This parameter must be a number between Min_Data = 50 and Max_Data = 432
-                            Except for STM32F411xE devices where the Min_Data = 192. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
-                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
-                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-}RCC_PLLI2SInitTypeDef;
- 
-/** 
-  * @brief  RCC extended clocks structure definition  
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
-                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters.
-                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
-
-  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection.
-                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
-  uint8_t TIMPresSelection;        /*!< Specifies TIM Clock Source Selection. 
-                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
-}RCC_PeriphCLKInitTypeDef;
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
-/**
-  * @}
-  */ 
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
-  * @{
-  */
-
-/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
-  * @{
-  */
-/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
-    defined(STM32F413xx) || defined(STM32F423xx)
-#define RCC_PERIPHCLK_I2S_APB1        0x00000001U
-#define RCC_PERIPHCLK_I2S_APB2        0x00000002U
-#define RCC_PERIPHCLK_TIM             0x00000004U
-#define RCC_PERIPHCLK_RTC             0x00000008U
-#define RCC_PERIPHCLK_FMPI2C1         0x00000010U
-#define RCC_PERIPHCLK_CLK48           0x00000020U
-#define RCC_PERIPHCLK_SDIO            0x00000040U
-#define RCC_PERIPHCLK_PLLI2S          0x00000080U
-#define RCC_PERIPHCLK_DFSDM1          0x00000100U
-#define RCC_PERIPHCLK_DFSDM1_AUDIO    0x00000200U
-#endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define RCC_PERIPHCLK_DFSDM2          0x00000400U
-#define RCC_PERIPHCLK_DFSDM2_AUDIO    0x00000800U
-#define RCC_PERIPHCLK_LPTIM1          0x00001000U
-#define RCC_PERIPHCLK_SAIA            0x00002000U
-#define RCC_PERIPHCLK_SAIB            0x00004000U
-#endif /* STM32F413xx || STM32F423xx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------- Peripheral Clock source for STM32F410xx ----------------*/
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define RCC_PERIPHCLK_I2S             0x00000001U
-#define RCC_PERIPHCLK_TIM             0x00000002U
-#define RCC_PERIPHCLK_RTC             0x00000004U
-#define RCC_PERIPHCLK_FMPI2C1         0x00000008U
-#define RCC_PERIPHCLK_LPTIM1          0x00000010U
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------- Peripheral Clock source for STM32F446xx ----------------*/
-#if defined(STM32F446xx)
-#define RCC_PERIPHCLK_I2S_APB1        0x00000001U
-#define RCC_PERIPHCLK_I2S_APB2        0x00000002U
-#define RCC_PERIPHCLK_SAI1            0x00000004U
-#define RCC_PERIPHCLK_SAI2            0x00000008U
-#define RCC_PERIPHCLK_TIM             0x00000010U
-#define RCC_PERIPHCLK_RTC             0x00000020U
-#define RCC_PERIPHCLK_CEC             0x00000040U
-#define RCC_PERIPHCLK_FMPI2C1         0x00000080U
-#define RCC_PERIPHCLK_CLK48           0x00000100U
-#define RCC_PERIPHCLK_SDIO            0x00000200U
-#define RCC_PERIPHCLK_SPDIFRX         0x00000400U
-#define RCC_PERIPHCLK_PLLI2S          0x00000800U
-#endif /* STM32F446xx */
-/*-----------------------------------------------------------------------------*/
-    
-/*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define RCC_PERIPHCLK_I2S             0x00000001U
-#define RCC_PERIPHCLK_SAI_PLLI2S      0x00000002U
-#define RCC_PERIPHCLK_SAI_PLLSAI      0x00000004U
-#define RCC_PERIPHCLK_LTDC            0x00000008U
-#define RCC_PERIPHCLK_TIM             0x00000010U
-#define RCC_PERIPHCLK_RTC             0x00000020U
-#define RCC_PERIPHCLK_PLLI2S          0x00000040U
-#define RCC_PERIPHCLK_CLK48           0x00000080U
-#define RCC_PERIPHCLK_SDIO            0x00000100U
-#endif /* STM32F469xx || STM32F479xx */
-/*----------------------------------------------------------------------------*/
-
-/*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-#define RCC_PERIPHCLK_I2S             0x00000001U
-#define RCC_PERIPHCLK_SAI_PLLI2S      0x00000002U
-#define RCC_PERIPHCLK_SAI_PLLSAI      0x00000004U
-#define RCC_PERIPHCLK_LTDC            0x00000008U
-#define RCC_PERIPHCLK_TIM             0x00000010U
-#define RCC_PERIPHCLK_RTC             0x00000020U
-#define RCC_PERIPHCLK_PLLI2S          0x00000040U
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-/*----------------------------------------------------------------------------*/
-
-/*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
-#define RCC_PERIPHCLK_I2S             0x00000001U
-#define RCC_PERIPHCLK_RTC             0x00000002U
-#define RCC_PERIPHCLK_PLLI2S          0x00000004U
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
-#define RCC_PERIPHCLK_TIM             0x00000008U
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */      
-/*----------------------------------------------------------------------------*/
-/**
-  * @}
-  */
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
-    defined(STM32F479xx) 
-/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
-  * @{
-  */
-#define RCC_I2SCLKSOURCE_PLLI2S         0x00000000U
-#define RCC_I2SCLKSOURCE_EXT            0x00000001U
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
-
-/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
-  * @{
-  */
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx) 
-#define RCC_PLLSAIDIVR_2                0x00000000U
-#define RCC_PLLSAIDIVR_4                0x00010000U
-#define RCC_PLLSAIDIVR_8                0x00020000U
-#define RCC_PLLSAIDIVR_16               0x00030000U
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
-  * @{
-  */
-#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-#define RCC_PLLI2SP_DIV2                  0x00000002U
-#define RCC_PLLI2SP_DIV4                  0x00000004U
-#define RCC_PLLI2SP_DIV6                  0x00000006U
-#define RCC_PLLI2SP_DIV8                  0x00000008U
-#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
-  * @{
-  */
-#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 
-#define RCC_PLLSAIP_DIV2                  0x00000002U
-#define RCC_PLLSAIP_DIV4                  0x00000004U
-#define RCC_PLLSAIP_DIV6                  0x00000006U
-#define RCC_PLLSAIP_DIV8                  0x00000008U
-#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @defgroup RCCEx_SAI_BlockA_Clock_Source  RCC SAI BlockA Clock Source
-  * @{
-  */
-#define RCC_SAIACLKSOURCE_PLLSAI             0x00000000U
-#define RCC_SAIACLKSOURCE_PLLI2S             0x00100000U
-#define RCC_SAIACLKSOURCE_EXT                0x00200000U
-/**
-  * @}
-  */ 
-
-/** @defgroup RCCEx_SAI_BlockB_Clock_Source  RCC SAI BlockB Clock Source
-  * @{
-  */
-#define RCC_SAIBCLKSOURCE_PLLSAI             0x00000000U
-#define RCC_SAIBCLKSOURCE_PLLI2S             0x00400000U
-#define RCC_SAIBCLKSOURCE_EXT                0x00800000U
-/**
-  * @}
-  */ 
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-      
-#if defined(STM32F469xx) || defined(STM32F479xx)
-/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source
-  * @{
-  */
-#define RCC_CLK48CLKSOURCE_PLLQ              0x00000000U
-#define RCC_CLK48CLKSOURCE_PLLSAIP           ((uint32_t)RCC_DCKCFGR_CK48MSEL)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
-  * @{
-  */
-#define RCC_SDIOCLKSOURCE_CLK48             0x00000000U
-#define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR_SDIOSEL)
-/**
-  * @}
-  */    
-  
-/** @defgroup RCCEx_DSI_Clock_Source  RCC DSI Clock Source
-  * @{
-  */
-#define RCC_DSICLKSOURCE_DSIPHY             0x00000000U
-#define RCC_DSICLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_DSISEL)
-/**
-  * @}
-  */
-#endif /* STM32F469xx || STM32F479xx */
-
-#if defined(STM32F446xx)
-/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source 
-  * @{
-  */
-#define RCC_SAI1CLKSOURCE_PLLSAI             0x00000000U
-#define RCC_SAI1CLKSOURCE_PLLI2S             ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
-#define RCC_SAI1CLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
-#define RCC_SAI1CLKSOURCE_EXT                ((uint32_t)RCC_DCKCFGR_SAI1SRC)
-/**
-  * @}
-  */ 
-
-/** @defgroup RCCEx_SAI2_Clock_Source  RCC SAI2 Clock Source
-  * @{
-  */
-#define RCC_SAI2CLKSOURCE_PLLSAI             0x00000000U
-#define RCC_SAI2CLKSOURCE_PLLI2S             ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
-#define RCC_SAI2CLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
-#define RCC_SAI2CLKSOURCE_PLLSRC             ((uint32_t)RCC_DCKCFGR_SAI2SRC)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2SAPB1_Clock_Source  RCC I2S APB1 Clock Source
-  * @{
-  */
-#define RCC_I2SAPB1CLKSOURCE_PLLI2S          0x00000000U
-#define RCC_I2SAPB1CLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
-#define RCC_I2SAPB1CLKSOURCE_PLLR            ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
-#define RCC_I2SAPB1CLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2S1SRC)
-/**
-  * @}
-  */ 
-
-/** @defgroup RCCEx_I2SAPB2_Clock_Source  RCC I2S APB2 Clock Source
-  * @{
-  */
-#define RCC_I2SAPB2CLKSOURCE_PLLI2S          0x00000000U
-#define RCC_I2SAPB2CLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
-#define RCC_I2SAPB2CLKSOURCE_PLLR            ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
-#define RCC_I2SAPB2CLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2S2SRC)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source
-  * @{
-  */
-#define RCC_FMPI2C1CLKSOURCE_PCLK1            0x00000000U
-#define RCC_FMPI2C1CLKSOURCE_SYSCLK           ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
-#define RCC_FMPI2C1CLKSOURCE_HSI              ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CEC_Clock_Source  RCC CEC Clock Source
-  * @{
-  */
-#define RCC_CECCLKSOURCE_HSI                0x00000000U
-#define RCC_CECCLKSOURCE_LSE                ((uint32_t)RCC_DCKCFGR2_CECSEL)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source
-  * @{
-  */
-#define RCC_CLK48CLKSOURCE_PLLQ              0x00000000U
-#define RCC_CLK48CLKSOURCE_PLLSAIP           ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
-  * @{
-  */
-#define RCC_SDIOCLKSOURCE_CLK48             0x00000000U
-#define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_SPDIFRX_Clock_Source   RCC SPDIFRX Clock Source
-  * @{
-  */
-#define RCC_SPDIFRXCLKSOURCE_PLLR           0x00000000U
-#define RCC_SPDIFRXCLKSOURCE_PLLI2SP        ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
-/**
-  * @}
-  */
-
-#endif /* STM32F446xx */
-
-#if defined(STM32F413xx) || defined(STM32F423xx)
-/** @defgroup RCCEx_SAI1_BlockA_Clock_Source  RCC SAI BlockA Clock Source
-  * @{
-  */
-#define RCC_SAIACLKSOURCE_PLLI2SR            0x00000000U
-#define RCC_SAIACLKSOURCE_EXT                ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0)
-#define RCC_SAIACLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1)
-#define RCC_SAIACLKSOURCE_PLLSRC             ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1)
-/**
-  * @}
-  */ 
-
-/** @defgroup RCCEx_SAI1_BlockB_Clock_Source  RCC SAI BlockB Clock Source
-  * @{
-  */
-#define RCC_SAIBCLKSOURCE_PLLI2SR            0x00000000U
-#define RCC_SAIBCLKSOURCE_EXT                ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0)
-#define RCC_SAIBCLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1)
-#define RCC_SAIBCLKSOURCE_PLLSRC             ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1)
-/**
-  * @}
-  */ 
-      
-/** @defgroup RCCEx_LPTIM1_Clock_Source  RCC LPTIM1 Clock Source
-  * @{
-  */
-#define RCC_LPTIM1CLKSOURCE_PCLK1           0x00000000U
-#define RCC_LPTIM1CLKSOURCE_HSI             ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
-#define RCC_LPTIM1CLKSOURCE_LSI             ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
-#define RCC_LPTIM1CLKSOURCE_LSE             ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
-/**
-  * @}
-  */
-      
-
-/** @defgroup RCCEx_DFSDM2_Audio_Clock_Source  RCC DFSDM2 Audio Clock Source
-  * @{
-  */
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2S1       0x00000000U
-#define RCC_DFSDM2AUDIOCLKSOURCE_I2S2       ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source  RCC DFSDM2 Kernel Clock Source
-  * @{
-  */
-#define RCC_DFSDM2CLKSOURCE_PCLK2           0x00000000U
-#define RCC_DFSDM2CLKSOURCE_SYSCLK          ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
-/**
-  * @}
-  */
-
-#endif /* STM32F413xx || STM32F423xx */
-
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source
-  * @{
-  */
-#define RCC_PLLI2SCLKSOURCE_PLLSRC          0x00000000U 
-#define RCC_PLLI2SCLKSOURCE_EXT             ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source  RCC DFSDM1 Audio Clock Source
-  * @{
-  */
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2S1       0x00000000U
-#define RCC_DFSDM1AUDIOCLKSOURCE_I2S2       ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source  RCC DFSDM1 Kernel Clock Source
-  * @{
-  */
-#define RCC_DFSDM1CLKSOURCE_PCLK2           0x00000000U
-#define RCC_DFSDM1CLKSOURCE_SYSCLK          ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2SAPB1_Clock_Source  RCC I2S APB1 Clock Source
-  * @{
-  */
-#define RCC_I2SAPB1CLKSOURCE_PLLI2S         0x00000000U
-#define RCC_I2SAPB1CLKSOURCE_EXT            ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
-#define RCC_I2SAPB1CLKSOURCE_PLLR           ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
-#define RCC_I2SAPB1CLKSOURCE_PLLSRC         ((uint32_t)RCC_DCKCFGR_I2S1SRC)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_I2SAPB2_Clock_Source  RCC I2S APB2 Clock Source
-  * @{
-  */
-#define RCC_I2SAPB2CLKSOURCE_PLLI2S         0x00000000U
-#define RCC_I2SAPB2CLKSOURCE_EXT            ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
-#define RCC_I2SAPB2CLKSOURCE_PLLR           ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
-#define RCC_I2SAPB2CLKSOURCE_PLLSRC         ((uint32_t)RCC_DCKCFGR_I2S2SRC)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source
-  * @{
-  */
-#define RCC_FMPI2C1CLKSOURCE_PCLK1          0x00000000U
-#define RCC_FMPI2C1CLKSOURCE_SYSCLK         ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
-#define RCC_FMPI2C1CLKSOURCE_HSI            ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source
-  * @{
-  */
-#define RCC_CLK48CLKSOURCE_PLLQ             0x00000000U
-#define RCC_CLK48CLKSOURCE_PLLI2SQ          ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
-  * @{
-  */
-#define RCC_SDIOCLKSOURCE_CLK48             0x00000000U
-#define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
-/**
-  * @}
-  */
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-
-/** @defgroup RCCEx_I2S_APB_Clock_Source  RCC I2S APB Clock Source
-  * @{
-  */
-#define RCC_I2SAPBCLKSOURCE_PLLR            0x00000000U
-#define RCC_I2SAPBCLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
-#define RCC_I2SAPBCLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source
-  * @{
-  */
-#define RCC_FMPI2C1CLKSOURCE_PCLK1              0x00000000U
-#define RCC_FMPI2C1CLKSOURCE_SYSCLK             ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
-#define RCC_FMPI2C1CLKSOURCE_HSI                ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_LPTIM1_Clock_Source  RCC LPTIM1 Clock Source
-  * @{
-  */
-#define RCC_LPTIM1CLKSOURCE_PCLK1          0x00000000U
-#define RCC_LPTIM1CLKSOURCE_HSI            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
-#define RCC_LPTIM1CLKSOURCE_LSI            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
-#define RCC_LPTIM1CLKSOURCE_LSE            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
-/**
-  * @}
-  */
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-/** @defgroup RCCEx_TIM_PRescaler_Selection  RCC TIM PRescaler Selection
-  * @{
-  */
-#define RCC_TIMPRES_DESACTIVATED        ((uint8_t)0x00)
-#define RCC_TIMPRES_ACTIVATED           ((uint8_t)0x01)
-/**
-  * @}
-  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
-          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
-    defined(STM32F423xx)
-/** @defgroup RCCEx_LSE_Dual_Mode_Selection  RCC LSE Dual Mode Selection
-  * @{
-  */
-#define RCC_LSE_LOWPOWER_MODE           ((uint8_t)0x00)
-#define RCC_LSE_HIGHDRIVE_MODE          ((uint8_t)0x01)
-/**
-  * @}
-  */
-#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\
-          STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
-/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
-  * @{
-  */
-#define RCC_MCO2SOURCE_SYSCLK            0x00000000U
-#define RCC_MCO2SOURCE_PLLI2SCLK         RCC_CFGR_MCO2_0
-#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
-#define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
-          STM32F412Rx || STM32F413xx | STM32F423xx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
-  * @{
-  */
-#define RCC_MCO2SOURCE_SYSCLK            0x00000000U
-#define RCC_MCO2SOURCE_I2SCLK            RCC_CFGR_MCO2_0
-#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
-#define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2
-/**
-  * @}
-  */
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-/**
-  * @}
-  */
-     
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
-  * @{
-  */
-/*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_GPIOI_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_GPIOF_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_GPIOG_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_GPIOJ_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_GPIOK_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_DMA2D_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_ETHMAC_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
-                                         UNUSED(tmpreg); \
-                                         } while(0U)
-#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
-                                         __IO uint32_t tmpreg = 0x00U; \
-                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
-                                         /* Delay after an RCC peripheral clock enabling */ \
-                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
-                                         UNUSED(tmpreg); \
-                                         } while(0U)
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
-#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
-#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
-#define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
-#define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
-#define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
-#define __HAL_RCC_ETHMAC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
-#define __HAL_RCC_ETHMACTX_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
-#define __HAL_RCC_ETHMACRX_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
-#define __HAL_RCC_ETHMACPTP_CLK_DISABLE()       (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
-#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
-#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
-#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-
-/**
-  * @brief  Enable ETHERNET clock.
-  */
-#define __HAL_RCC_ETH_CLK_ENABLE() do {                                     \
-                                        __HAL_RCC_ETHMAC_CLK_ENABLE();      \
-                                        __HAL_RCC_ETHMACTX_CLK_ENABLE();    \
-                                        __HAL_RCC_ETHMACRX_CLK_ENABLE();    \
-                                      } while(0U)
-/**
-  * @brief  Disable ETHERNET clock.
-  */
-#define __HAL_RCC_ETH_CLK_DISABLE()  do {                                      \
-                                          __HAL_RCC_ETHMACTX_CLK_DISABLE();    \
-                                          __HAL_RCC_ETHMACRX_CLK_DISABLE();    \
-                                          __HAL_RCC_ETHMAC_CLK_DISABLE();      \
-                                        } while(0U)
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
-#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) 
-#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) 
-#define __HAL_RCC_GPIOK_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
-#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) 
-#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) 
-#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
-#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
-#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
-#define __HAL_RCC_ETH_IS_CLK_ENABLED()             (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
-                                                    __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
-                                                    __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 
-
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
-#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) 
-#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) 
-#define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
-#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) 
-#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) 
-#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
-#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
-#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
-#define __HAL_RCC_ETH_IS_CLK_DISABLED()             (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
-                                                     __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
-                                                     __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
- #define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
-
-#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
-#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_HASH_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-
-#define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
-#define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
-#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
-
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
-                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
-                                              }while(0U)
-                                        
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
-
-#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */ 
-#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
-#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
-
-#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
-#define __HAL_RCC_CRYP_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
-#define __HAL_RCC_CRYP_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
-
-#define __HAL_RCC_HASH_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
-#define __HAL_RCC_HASH_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
-#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
-
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
-
-#define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 
-#define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)     
-/**
-  * @}
-  */   
-
-/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{  
-  */
-#define __HAL_RCC_FMC_CLK_ENABLE()    do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_FMC_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_QSPI_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
-#endif /* STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-
-/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
-#define __HAL_RCC_FMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
-#endif /* STM32F469xx || STM32F479xx */  
-/**
-  * @}
-  */
-    
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_USART3_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_UART4_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_UART5_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_DAC_CLK_ENABLE()    do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_UART7_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_UART8_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
-#define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
-#define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-#define __HAL_RCC_UART7_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
-#define __HAL_RCC_UART8_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)  
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)  
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 
-#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 
-#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 
-#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 
-#define __HAL_RCC_UART7_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
-#define __HAL_RCC_UART8_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)  
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)  
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 
-#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 
-#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 
-#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
-#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 
-#define __HAL_RCC_UART7_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
-#define __HAL_RCC_UART8_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) 
-/**
-  * @}
-  */
-    
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPI6_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
-#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
-#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
-#define __HAL_RCC_SPI6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
-#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
-
-#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_LTDC_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-
-#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
-#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_DSI_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-
-#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
-#endif /* STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */  
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
-#define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
-#define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 
-#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 
-#define __HAL_RCC_SPI6_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) 
-#define __HAL_RCC_SAI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
-#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)  
-
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
-#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
-#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
-#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
-#define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
-#define __HAL_RCC_SPI6_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
-#define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
-
-#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_LTDC_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
-#define __HAL_RCC_LTDC_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
-#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_DSI_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
-#define __HAL_RCC_DSI_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
-#endif /* STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_GPIOI_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
-#define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
-#define __HAL_RCC_GPIOJ_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
-#define __HAL_RCC_GPIOK_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
-#define __HAL_RCC_DMA2D_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
-#define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-
-#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_GPIOI_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
-#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
-#define __HAL_RCC_GPIOJ_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
-#define __HAL_RCC_GPIOK_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
-#define __HAL_RCC_DMA2D_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
-#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
-  * @brief  Force or release AHB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) 
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
-
-#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
-
-#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 
-#define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
-#define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
-
-#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
-#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
-#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
-  * @brief  Force or release AHB3 peripheral reset.
-  * @{
-  */ 
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
-#define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
-#define __HAL_RCC_FMC_RELEASE_RESET()  (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
-#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))  
-#endif /* STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */ 
-#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_UART7_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
-#define __HAL_RCC_UART8_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
-#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-
-#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_UART7_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
-#define __HAL_RCC_UART8_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM8_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_SPI5_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
-#define __HAL_RCC_SPI6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
-#define __HAL_RCC_SAI1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
-#define __HAL_RCC_SDIO_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-
-#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
-#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
-#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
-
-#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_LTDC_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
-#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
-#endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_DSI_FORCE_RESET()   (RCC->APB2RSTR |=  (RCC_APB2RSTR_DSIRST))
-#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
-#endif /* STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
-#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
-#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
-#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
-#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
-#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
-#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
-
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
-#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
-#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
-#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
-#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
-#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
-
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
-
-#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
-#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
-
-#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 
-#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
-#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
-
-#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
-#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
-#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
-#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
-#endif /* STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */  
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
-#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
-#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
-#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
-/**
-  * @}
-  */
-                                        
-/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */ 
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
-#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
-#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
-#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
-#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
-#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
-#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
-#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
-#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
-
-#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
-
-#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
-#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |=  (RCC_APB2LPENR_DSILPEN))
-#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
-#endif /* STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-/*----------------------------------------------------------------------------*/
-
-/*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
-/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00U; \
-                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
-                                       /* Delay after an RCC peripheral clock enabling */ \
-                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
-                                       UNUSED(tmpreg); \
-                                       } while(0U)
-#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00U; \
-                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                       /* Delay after an RCC peripheral clock enabling */ \
-                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                       UNUSED(tmpreg); \
-                                       } while(0U)
-#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00U; \
-                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                       /* Delay after an RCC peripheral clock enabling */ \
-                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                       UNUSED(tmpreg); \
-                                       } while(0U)
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00U; \
-                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
-                                       /* Delay after an RCC peripheral clock enabling */ \
-                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
-                                       UNUSED(tmpreg); \
-                                       } while(0U)
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
-                                       __IO uint32_t tmpreg = 0x00U; \
-                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
-                                       /* Delay after an RCC peripheral clock enabling */ \
-                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
-                                       UNUSED(tmpreg); \
-                                       } while(0U)
-#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
-#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
-#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
-#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
-#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
-#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-#if defined(STM32F407xx)|| defined(STM32F417xx)
-/**
-  * @brief  Enable ETHERNET clock.
-  */
-#define __HAL_RCC_ETHMAC_CLK_ENABLE()  do { \
-                                       __IO uint32_t tmpreg = 0x00U; \
-                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
-                                       /* Delay after an RCC peripheral clock enabling */ \
-                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
-                                       UNUSED(tmpreg); \
-                                       } while(0U)
-#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_ETH_CLK_ENABLE()      do {                            \
-                                        __HAL_RCC_ETHMAC_CLK_ENABLE();      \
-                                        __HAL_RCC_ETHMACTX_CLK_ENABLE();    \
-                                        __HAL_RCC_ETHMACRX_CLK_ENABLE();    \
-                                        } while(0U)
-
-/**
-  * @brief  Disable ETHERNET clock.
-  */
-#define __HAL_RCC_ETHMAC_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
-#define __HAL_RCC_ETHMACTX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
-#define __HAL_RCC_ETHMACRX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
-#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))  
-#define __HAL_RCC_ETH_CLK_DISABLE()       do {                             \
-                                           __HAL_RCC_ETHMACTX_CLK_DISABLE();    \
-                                           __HAL_RCC_ETHMACRX_CLK_DISABLE();    \
-                                           __HAL_RCC_ETHMAC_CLK_DISABLE();      \
-                                          } while(0U)
-#endif /* STM32F407xx || STM32F417xx */
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */  
-#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
-#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
-
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
-#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
-#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
-#if defined(STM32F407xx)|| defined(STM32F417xx)
-/**
-  * @brief  Enable ETHERNET clock.
-  */
-#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
-#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
-#define __HAL_RCC_ETH_IS_CLK_ENABLED()        (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
-                                               __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
-                                               __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
-/**
-  * @brief  Disable ETHERNET clock.
-  */
-#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
-#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
-#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
-#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
-#define __HAL_RCC_ETH_IS_CLK_DISABLED()        (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
-                                                __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
-                                                __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
-#endif /* STM32F407xx || STM32F417xx */
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 
-  * @brief  Enable or disable the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
-                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
-                                              }while(0U)
-                                        
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
-
-#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
-
-#if defined(STM32F407xx)|| defined(STM32F417xx) 
-#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
-#endif /* STM32F407xx || STM32F417xx */
-
-#if defined(STM32F415xx) || defined(STM32F417xx)
-#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_HASH_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
-#define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
-#endif /* STM32F415xx || STM32F417xx */
-/**
-  * @}
-  */
-
-
-/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 
-
-#define __HAL_RCC_RNG_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)   
-#define __HAL_RCC_RNG_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 
-
-#if defined(STM32F407xx)|| defined(STM32F417xx) 
-#define __HAL_RCC_DCMI_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 
-#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 
-#endif /* STM32F407xx || STM32F417xx */
-
-#if defined(STM32F415xx) || defined(STM32F417xx)
-#define __HAL_RCC_CRYP_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) 
-#define __HAL_RCC_HASH_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) 
-
-#define __HAL_RCC_CRYP_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) 
-#define __HAL_RCC_HASH_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) 
-#endif /* STM32F415xx || STM32F417xx */  
-/**
-  * @}
-  */  
-  
-/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{  
-  */
-#define __HAL_RCC_FSMC_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_FSMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 
-#define __HAL_RCC_FSMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) 
-/**
-  * @}
-  */   
-   
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{  
-  */
-#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_USART3_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_UART4_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_UART5_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_DAC_CLK_ENABLE()    do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
-#define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
-#define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-/**
-  * @}
-  */
- 
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */ 
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)  
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 
-#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 
-#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 
-#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)  
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 
-#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 
-#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 
-#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 
-#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 
-  /**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */ 
-#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-
-#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
-#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)  
-#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)  
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 
-#define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 
-#define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
-  
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)  
-#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)  
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 
-#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 
-#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
-/**
-  * @}
-  */
-    
-/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_GPIOI_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
-#define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
-#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-
-#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_GPIOI_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
-#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
-#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
-  * @brief  Force or release AHB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()         (RCC->AHB2RSTR = 0xFFFFFFFFU) 
-#define __HAL_RCC_AHB2_RELEASE_RESET()       (RCC->AHB2RSTR = 0x00U)
-
-#if defined(STM32F407xx)|| defined(STM32F417xx)  
-#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
-#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
-#endif /* STM32F407xx || STM32F417xx */
-
-#if defined(STM32F415xx) || defined(STM32F417xx) 
-#define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
-#define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
-
-#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
-#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
-#endif /* STM32F415xx || STM32F417xx */
-   
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-
-#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
-  * @brief  Force or release AHB3 peripheral reset.
-  * @{
-  */ 
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
-
-#define __HAL_RCC_FSMC_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
-#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-
-#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM8_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_SDIO_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-                                          
-#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-/**
-  * @}
-  */
-                                        
-/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
-#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
-#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
-#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
-
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
-#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
-#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
-#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
-#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
-#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
-
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
-
-#if defined(STM32F407xx)|| defined(STM32F417xx) 
-#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
-#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
-#endif /* STM32F407xx || STM32F417xx */
-
-#if defined(STM32F415xx) || defined(STM32F417xx) 
-#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
-#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
-
-#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
-#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
-#endif /* STM32F415xx || STM32F417xx */
-/**
-  * @}
-  */
-                                        
-/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
-#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
-/**
-  * @}
-  */
-                                        
-/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-/**
-  * @}
-  */
-                                        
-/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
-#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
-#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
-/**
-  * @}
-  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------------- STM32F401xE/STM32F401xC --------------------------*/
-#if defined(STM32F401xC) || defined(STM32F401xE)
-/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.   
-  * @{
-  */
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_CRC_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE()  do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-
-#define __HAL_RCC_GPIOD_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#define __HAL_RCC_GPIOE_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
-#define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)  
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)  
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)  
-
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)  
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)  
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)  
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
-                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
-                                              }while(0U)
-                                        
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
-/**
-  * @}
-  */  
-  
-/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-
-#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)  
-#define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)   
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)  
-
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
-#define __HAL_RCC_SPI4_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 
-/**
-  * @}
-  */
-/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */  
-#define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-
-#define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00U)
-#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
-  * @brief  Force or release AHB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) 
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-
-#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)  
-#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-
-#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U) 
-#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)  
-#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-
-#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)
-#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
-  * @brief  Force or release AHB3 peripheral reset.
-  * @{
-  */ 
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-/**
-  * @}
-  */
-#endif /* STM32F401xC || STM32F401xE*/
-/*----------------------------------------------------------------------------*/
-
-/*-------------------------------- STM32F410xx -------------------------------*/
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable     
-  * @brief  Enables or disables the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_RNG_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_CRC_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-#define __HAL_RCC_RNG_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
-#define __HAL_RCC_RNG_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET)
-      
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
-#define __HAL_RCC_RNG_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable  
-  * @brief  Enable or disable the High Speed APB (APB1) peripheral clock.
-  * @{
-  */
-#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_RTCAPB_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U) 
-#define __HAL_RCC_DAC_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-                                        
-#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_RTCAPB_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
-#define __HAL_RCC_LPTIM1_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
-#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
-#define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */  
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 
-#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
-#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 
-#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)  
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 
-
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 
-#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
-#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 
-#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)  
-#define __HAL_RCC_DAC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)  
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable  
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @{
-  */  
-#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_EXTIT_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPI5_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
-#define __HAL_RCC_EXTIT_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)  
-#define __HAL_RCC_EXTIT_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)  
-  
-#define __HAL_RCC_SPI5_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)  
-#define __HAL_RCC_EXTIT_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)  
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-#define __HAL_RCC_RNG_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST))
-#define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-#define __HAL_RCC_RNG_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
-  * @brief  Force or release AHB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()
-#define __HAL_RCC_AHB2_RELEASE_RESET()
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
-  * @brief  Force or release AHB3 peripheral reset.
-  * @{
-  */ 
-#define __HAL_RCC_AHB3_FORCE_RESET()
-#define __HAL_RCC_AHB3_RELEASE_RESET()
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM6_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_LPTIM1_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_FMPI2C1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
-#define __HAL_RCC_DAC_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-
-#define __HAL_RCC_TIM6_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_LPTIM1_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
-#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
-#define __HAL_RCC_DAC_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_SPI5_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
-#define __HAL_RCC_SPI5_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))                                        
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable  
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable                                         
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @{
-  */
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
-#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
-
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
-#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable                                         
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @{
-  */
-#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
-#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))                                
-#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))                                        
-#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
-/**
-  * @}
-  */
-
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-/*----------------------------------------------------------------------------*/
-
-/*-------------------------------- STM32F411xx -------------------------------*/
-#if defined(STM32F411xE)
-/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
-#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
-#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */  
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 
-
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
-                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
-                                              }while(0U)
-
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
-/**
-  * @}
-  */  
-
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it. 
-  * @{
-  */
-#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @{
-  */
-#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)  
-#define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)   
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)  
-#define __HAL_RCC_SPI5_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 
-
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)  
-#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)   
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)  
-#define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)   
-/**
-  * @}
-  */  
-  
-/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */ 
-#define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-
-#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
-  * @brief  Force or release AHB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) 
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-
-#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
-  * @brief  Force or release AHB3 peripheral reset.
-  * @{
-  */ 
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-
-#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
-#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-
-#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-                                        
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))                                        
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @{
-  */
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @{
-  */
-#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
-/**
-  * @}
-  */
-#endif /* STM32F411xE */
-/*----------------------------------------------------------------------------*/
-
-/*---------------------------------- STM32F446xx -----------------------------*/
-#if defined(STM32F446xx)
-/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                        UNUSED(tmpreg); \
-                                        } while(0U)
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_GPIOF_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_GPIOG_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
-#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
-#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
-#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
-#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)  
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 
-#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)  
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)  
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 
-
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 
-#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)  
-#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 
-#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)  
-#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)  
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 
-/**
-  * @}
-  */  
-  
-/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
-                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
-                                              }while(0U)
-                                        
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
-
-#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
-#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
-
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
-
-#define __HAL_RCC_RNG_IS_CLK_ENABLED()    ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 
-#define __HAL_RCC_RNG_IS_CLK_DISABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it. 
-  * @{
-  */
-#define __HAL_RCC_FMC_CLK_ENABLE()    do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-
-#define __HAL_RCC_FMC_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
-#define __HAL_RCC_QSPI_CLK_DISABLE()   (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
-
-#define __HAL_RCC_FMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it. 
-  * @{
-  */
-#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_USART3_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_UART4_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_UART5_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_CEC_CLK_ENABLE()    do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_DAC_CLK_ENABLE()    do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_TIM12_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
-#define __HAL_RCC_SPDIFRX_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
-#define __HAL_RCC_USART3_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
-#define __HAL_RCC_CAN1_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
-#define __HAL_RCC_CAN2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
-#define __HAL_RCC_CEC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
-#define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)  
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
-#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
-#define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
-#define __HAL_RCC_UART4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
-#define __HAL_RCC_UART5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
-#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
-#define __HAL_RCC_CEC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)  
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
-#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
-#define __HAL_RCC_USART3_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
-#define __HAL_RCC_UART4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
-#define __HAL_RCC_UART5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
-#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
-#define __HAL_RCC_CEC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
-#define __HAL_RCC_DAC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SAI2_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
-#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
-#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
-#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
-#define __HAL_RCC_SAI2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 
-#define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)  
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
-#define __HAL_RCC_ADC2_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 
-#define __HAL_RCC_ADC3_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 
-#define __HAL_RCC_SAI1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
-#define __HAL_RCC_SAI2_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
-
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 
-#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)  
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
-#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 
-#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 
-#define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
-#define __HAL_RCC_SAI2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) 
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
-#define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-
-#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
-#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
-#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
-  * @brief  Force or release AHB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) 
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
-
-#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
-  * @brief  Force or release AHB3 peripheral reset.
-  * @{
-  */ 
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
-
-#define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
-#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
-
-#define __HAL_RCC_FMC_RELEASE_RESET()    (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
-#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_SPDIFRX_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
-#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_FMPI2C1_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
-#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_CEC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
-#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
-                                          
-#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
-#define __HAL_RCC_SPDIFRX_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
-#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
-#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
-#define __HAL_RCC_CEC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
-#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_SAI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 
-#define __HAL_RCC_SAI2_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
-#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-
-#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-#define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
-#define __HAL_RCC_SAI2_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) 
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
-
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
-#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
-#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
-
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
-
-#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
-#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()   (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
-
-#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()   (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */ 
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
-#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
-#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
-#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
-#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
-#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
-#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
-#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
-#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
-#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
-#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
-#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
-/**
-  * @}
-  */
-
-#endif /* STM32F446xx */
-/*----------------------------------------------------------------------------*/
-
-/*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 
-/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 
-#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
-#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 
-#define __HAL_RCC_GPIOE_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
-#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)                                        
-#define __HAL_RCC_GPIOF_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_GPIOG_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */                                       
-#define __HAL_RCC_CRC_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)                                        
-#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 
-#define __HAL_RCC_GPIOD_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
-#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
-#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 
-#define __HAL_RCC_GPIOE_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
-#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
-#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_GPIOF_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
-#define __HAL_RCC_GPIOG_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
-#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */
-#define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
-#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
-#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
-#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
-#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
-#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */
-#define __HAL_RCC_CRC_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
-
-#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
-#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
-#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
-#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
-#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
-#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
-#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */
-#define __HAL_RCC_CRC_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#if defined(STM32F423xx)
-#define __HAL_RCC_AES_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-
-#define __HAL_RCC_AES_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
-#endif /* STM32F423xx */
-                                        
-#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
-                                     
-#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
-                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
-                                              }while(0U)
-                                        
-#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(STM32F423xx)
-#define __HAL_RCC_AES_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
-#define __HAL_RCC_AES_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
-#endif /* STM32F423xx */
-                                        
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
-#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
-          
-#define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)   
-#define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)   
-/**
-  * @}
-  */  
-
-/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
-  * @brief  Enables or disables the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it. 
-  * @{
-  */
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_FSMC_CLK_ENABLE()    do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-
-#define __HAL_RCC_FSMC_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
-#define __HAL_RCC_QSPI_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_FSMC_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 
-#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 
-
-#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
-#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
-
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it. 
-  * @{
-  */
-#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#if defined(STM32F413xx) || defined(STM32F423xx)                                        
-#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#endif /* STM32F413xx || STM32F423xx */  
-#define __HAL_RCC_RTCAPB_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_USART3_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_UART4_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_UART5_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#endif /* STM32F413xx || STM32F423xx */
-                                        
-#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_CAN3_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#endif /* STM32F413xx || STM32F423xx */
-#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_DAC_CLK_ENABLE()    do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_UART7_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_UART8_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#endif /* STM32F413xx || STM32F423xx */
-                                        
-#define __HAL_RCC_TIM2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __HAL_RCC_TIM3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __HAL_RCC_TIM4_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __HAL_RCC_TIM7_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __HAL_RCC_TIM12_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
-#define __HAL_RCC_TIM13_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
-#define __HAL_RCC_TIM14_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 
-#if defined(STM32F413xx) || defined(STM32F423xx)                 
-#define __HAL_RCC_LPTIM1_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
-#endif /* STM32F413xx || STM32F423xx */
-#define __HAL_RCC_RTCAPB_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))                                       
-#define __HAL_RCC_SPI3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-#define __HAL_RCC_USART3_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#if defined(STM32F413xx) || defined(STM32F423xx)   
-#define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_I2C3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
-#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
-#define __HAL_RCC_CAN1_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
-#define __HAL_RCC_CAN2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_CAN3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))                                        
-#define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-#define __HAL_RCC_UART7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
-#define __HAL_RCC_UART8_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
-#endif /* STM32F413xx || STM32F423xx */                                        
-                                        
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 
-#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
-#define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
-#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
-#define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
-#define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
-#define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
-#define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 
-#endif /* STM32F413xx || STM32F423xx */                                            
-#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)                                    
-#define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
-#define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 
-#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
-#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
-#define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
-#define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_CAN3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
-#define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 
-#define __HAL_RCC_UART7_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
-#define __HAL_RCC_UART8_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 
-#endif /* STM32F413xx || STM32F423xx */                                         
-
-#define __HAL_RCC_TIM2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 
-#define __HAL_RCC_TIM3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
-#define __HAL_RCC_TIM4_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
-#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
-#define __HAL_RCC_TIM7_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
-#define __HAL_RCC_TIM12_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
-#define __HAL_RCC_TIM13_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
-#define __HAL_RCC_TIM14_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
-#if defined(STM32F413xx) || defined(STM32F423xx)                                          
-#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 
-#endif /* STM32F413xx || STM32F423xx */                                         
-#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)                                        
-#define __HAL_RCC_SPI3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
-#define __HAL_RCC_USART3_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
-#if defined(STM32F413xx) || defined(STM32F423xx)                                           
-#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 
-#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 
-#endif /* STM32F413xx || STM32F423xx */                                          
-#define __HAL_RCC_I2C3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
-#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
-#define __HAL_RCC_CAN1_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
-#define __HAL_RCC_CAN2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
-#if defined(STM32F413xx) || defined(STM32F423xx)                                        
-#define __HAL_RCC_CAN3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
-#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 
-#define __HAL_RCC_UART7_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
-#define __HAL_RCC_UART8_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
-#endif /* STM32F413xx || STM32F423xx */                                         
-/**
-  * @}
-  */  
-/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
-  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_UART9_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_UART10_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)                                          
-#endif /* STM32F413xx || STM32F423xx */                                   
-#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U) 
-#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U)
-#define __HAL_RCC_EXTIT_CLK_ENABLE()  do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)                                        
-#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
-                                        __IO uint32_t tmpreg = 0x00U; \
-                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        /* Delay after an RCC peripheral clock enabling */ \
-                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
-                                        UNUSED(tmpreg); \
-                                      } while(0U) 
-#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)                                         
-#endif /* STM32F413xx || STM32F423xx */                                          
-#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \
-                                      __IO uint32_t tmpreg = 0x00U; \
-                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
-                                      /* Delay after an RCC peripheral clock enabling */ \
-                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
-                                      UNUSED(tmpreg); \
-                                      } while(0U)                                        
-#endif /* STM32F413xx || STM32F423xx */                                        
- 
-#define __HAL_RCC_TIM8_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_UART9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN))
-#define __HAL_RCC_UART10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN))                                        
-#endif /* STM32F413xx || STM32F423xx */                                         
-#define __HAL_RCC_SDIO_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-#define __HAL_RCC_SPI4_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
-#define __HAL_RCC_EXTIT_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
-#define __HAL_RCC_TIM10_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __HAL_RCC_SPI5_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_SAI1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))                                        
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_DFSDM1_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_DFSDM2_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN))                                      
-#endif /* STM32F413xx || STM32F423xx */                                         
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
-  * @brief  Get the enable or disable status of the APB2 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before
-  *         using it.
-  * @{
-  */
-#define __HAL_RCC_TIM8_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_UART9_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET)
-#define __HAL_RCC_UART10_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET)                                        
-#endif /* STM32F413xx || STM32F423xx */                                          
-#define __HAL_RCC_SDIO_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 
-#define __HAL_RCC_SPI4_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
-#define __HAL_RCC_EXTIT_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
-#define __HAL_RCC_TIM10_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
-#define __HAL_RCC_SPI5_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_SAI1_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)                                    
-#endif /* STM32F413xx || STM32F423xx */                                         
-#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET)                                  
-#endif /* STM32F413xx || STM32F423xx */                                         
-
-#define __HAL_RCC_TIM8_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_UART9_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET) 
-#define __HAL_RCC_UART10_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET)                                         
-#endif /* STM32F413xx || STM32F423xx */                                         
-#define __HAL_RCC_SDIO_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 
-#define __HAL_RCC_SPI4_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
-#define __HAL_RCC_EXTIT_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
-#define __HAL_RCC_TIM10_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
-#define __HAL_RCC_SPI5_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_SAI1_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)                                       
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET)                                       
-#endif /* STM32F413xx || STM32F423xx */                                         
-/**
-  * @}
-  */
-  
-/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
-  * @brief  Force or release AHB1 peripheral reset.
-  * @{
-  */
-#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
-#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
-#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
-#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
-#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
-#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */
-#define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
-
-#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
-#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
-#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
-#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
-#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
-#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
-#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */
-#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
-  * @brief  Force or release AHB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
-
-#if defined(STM32F423xx)
-#define __HAL_RCC_AES_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST))
-#define __HAL_RCC_AES_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))                                        
-#endif /* STM32F423xx */ 
-                                        
-#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
-#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
-
-#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
-#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
-  * @brief  Force or release AHB3 peripheral reset.
-  * @{
-  */ 
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
-#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
-
-#define __HAL_RCC_FSMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
-#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
-
-#define __HAL_RCC_FSMC_RELEASE_RESET()    (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
-#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 
-#if defined(STM32F412Cx)
-#define __HAL_RCC_AHB3_FORCE_RESET()
-#define __HAL_RCC_AHB3_RELEASE_RESET()
-
-#define __HAL_RCC_FSMC_FORCE_RESET()
-#define __HAL_RCC_QSPI_FORCE_RESET()
-
-#define __HAL_RCC_FSMC_RELEASE_RESET()
-#define __HAL_RCC_QSPI_RELEASE_RESET()
-#endif /* STM32F412Cx */
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
-  * @brief  Force or release APB1 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 
-#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))                                        
-#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_LPTIM1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) 
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))                                        
-#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))                                        
-#endif /* STM32F413xx || STM32F423xx */                                          
-#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))                                        
-#define __HAL_RCC_FMPI2C1_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
-#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_CAN3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))
-#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_UART7_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
-#define __HAL_RCC_UART8_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))                                        
-#endif /* STM32F413xx || STM32F423xx */                                        
-
-#define __HAL_RCC_TIM2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __HAL_RCC_TIM3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __HAL_RCC_TIM4_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __HAL_RCC_TIM6_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __HAL_RCC_TIM7_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __HAL_RCC_TIM12_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
-#define __HAL_RCC_TIM13_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
-#define __HAL_RCC_TIM14_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_LPTIM1_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_SPI3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-#define __HAL_RCC_USART3_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_UART4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __HAL_RCC_UART5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_I2C3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))                                        
-#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
-#define __HAL_RCC_CAN1_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
-#define __HAL_RCC_CAN2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_CAN3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
-#define __HAL_RCC_DAC_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-#define __HAL_RCC_UART7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
-#define __HAL_RCC_UART8_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))                                      
-#endif /* STM32F413xx || STM32F423xx */                                         
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
-  * @brief  Force or release APB2 peripheral reset.
-  * @{
-  */
-#define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_UART9_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST))
-#define __HAL_RCC_UART10_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_UART10RST))                                        
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))                                        
-#define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_SAI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
-#endif /* STM32F413xx || STM32F423xx */                                         
-#define __HAL_RCC_DFSDM1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_DFSDM2_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM2RST))
-#endif /* STM32F413xx || STM32F423xx */                                        
-
-#define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_UART9_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST))
-#define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST))                                        
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
-#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST))
-#endif /* STM32F413xx || STM32F423xx */                                        
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
-#endif /* STM32F413xx || STM32F423xx */                                        
-
-#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
-#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
-#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
-#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
-#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
-#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
-#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
-#endif /* STM32F413xx || STM32F423xx */                                        
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(STM32F423xx)
-#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()      (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN))                                        
-#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()     (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))
-#endif /* STM32F423xx */
-                                        
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
-#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
-
-#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
-#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()   (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
-#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
-
-#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE()   (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
-#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))                                        
-#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))                                       
-#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))                                        
-#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
-#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
-#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))                                        
-#endif /* STM32F413xx || STM32F423xx */                                        
-
-#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
-#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
-#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
-#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
-#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))                                        
-#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
-#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
-#endif /* STM32F413xx || STM32F423xx */                                
-#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))                                        
-#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
-#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
-#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
-#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
-#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))                                        
-#endif /* STM32F413xx || STM32F423xx */                                     
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
-  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_UART9LPEN))
-#define __HAL_RCC_UART10_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_UART10LPEN))                                        
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))  
-#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) 
-#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))                                        
-#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM2LPEN))
-#endif /* STM32F413xx || STM32F423xx */
-                                        
-#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN))
-#define __HAL_RCC_UART10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN))                                        
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
-#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
-#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))    
-#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
-#endif /* STM32F413xx || STM32F423xx */                                        
-#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN))
-#endif /* STM32F413xx || STM32F423xx */                                        
-/**
-  * @}
-  */
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------------------- PLL Configuration --------------------------*/
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
-  * @note   This function must be used only when the main PLL is disabled.
-  * @param  __RCC_PLLSource__ specifies the PLL entry clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
-  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
-  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  
-  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 2 MHz to limit PLL jitter.
-  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
-  *         output frequency is between 100 and 432 MHz.
-  *   
-  * @param  __PLLP__ specifies the division factor for main system clock (SYSCLK)
-  *         This parameter must be a number in the range {2, 4, 6, or 8}.
-  *           
-  * @param  __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  * @note   If the USB OTG FS is used in your application, you have to set the
-  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
-  *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
-  *         correctly.
-  *     
-  * @param  __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/
-            STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
-  *      
-  */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__)  \
-                            (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__)                   | \
-                            ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos)                      | \
-                            ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos)          | \
-                            ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)                      | \
-                            ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))
-#else
-/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
-  * @note   This function must be used only when the main PLL is disabled.
-  * @param  __RCC_PLLSource__ specifies the PLL entry clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
-  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
-  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  
-  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 2 MHz to limit PLL jitter.
-  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432
-  *         Except for STM32F411xE devices where Min_Data = 192.
-  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
-  *         output frequency is between 100 and 432 MHz, Except for STM32F411xE devices
-  *         where frequency is between 192 and 432 MHz.
-  * @param  __PLLP__ specifies the division factor for main system clock (SYSCLK)
-  *         This parameter must be a number in the range {2, 4, 6, or 8}.
-  *           
-  * @param  __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  * @note   If the USB OTG FS is used in your application, you have to set the
-  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
-  *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
-  *         correctly.
-  *      
-  */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)     \
-                            (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \
-                            ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos)                | \
-                            ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos)    | \
-                            ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
- #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-/*----------------------------------------------------------------------------*/
-                             
-/*----------------------------PLLI2S Configuration ---------------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-
-/** @brief Macros to enable or disable the PLLI2S. 
-  * @note  The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
-  */
-#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
-#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 
-          STM32F412Rx || STM32F412Cx */
-#if defined(STM32F446xx)
-/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
-  * @note   This macro must be used only when the PLLI2S is disabled.
-  * @note   PLLI2S clock source is common with the main PLL (configured in 
-  *         HAL_RCC_ClockConfig() API).
-  * @param  __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 1 MHz to limit PLLI2S jitter.
-  *
-  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
-  *
-  * @param  __PLLI2SP__ specifies division factor for SPDIFRX Clock.
-  *         This parameter must be a number in the range {2, 4, 6, or 8}.
-  * @note   the PLLI2SP parameter is only available with STM32F446xx Devices
-  *                 
-  * @param  __PLLI2SR__ specifies the division factor for I2S clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
-  *         on the I2S clock frequency.
-  *   
-  * @param  __PLLI2SQ__ specifies the division factor for SAI clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  */
-#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__)    \
-                               (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                   |\
-                               ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)             |\
-                               ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\
-                               ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos)             |\
-                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
-#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
-      defined(STM32F413xx) || defined(STM32F423xx)
-/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
-  * @note   This macro must be used only when the PLLI2S is disabled.
-  * @note   PLLI2S clock source is common with the main PLL (configured in 
-  *         HAL_RCC_ClockConfig() API).
-  * @param  __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 1 MHz to limit PLLI2S jitter.
-  *
-  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
-  *
-  * @param  __PLLI2SR__ specifies the division factor for I2S clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
-  *         on the I2S clock frequency.
-  *
-  * @param  __PLLI2SQ__ specifies the division factor for SAI clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  */
-#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__)    \
-                               (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                   |\
-                               ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)             |\
-                               ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos)             |\
-                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
-#else
-/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
-  * @note   This macro must be used only when the PLLI2S is disabled.
-  * @note   PLLI2S clock source is common with the main PLL (configured in 
-  *         HAL_RCC_ClockConfig() API).
-  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
-  *
-  * @param  __PLLI2SR__ specifies the division factor for I2S clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
-  *         on the I2S clock frequency.
-  *
-  */
-#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__)                                                    \
-                               (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)  |\
-                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
-#endif /* STM32F446xx */
-
-#if defined(STM32F411xE)
-/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
-  * @note   This macro must be used only when the PLLI2S is disabled.
-  * @note   This macro must be used only when the PLLI2S is disabled.
-  * @note   PLLI2S clock source is common with the main PLL (configured in 
-  *         HAL_RCC_ClockConfig() API).
-  * @param  __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
-  * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 2 MHz to limit PLLI2S jitter.    
-  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
-  *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.
-  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
-  * @param  __PLLI2SR__ specifies the division factor for I2S clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
-  *         on the I2S clock frequency.
-  */
-#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                                       |\
-                                                                                                  ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)             |\
-                                                                                                  ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
-#endif /* STM32F411xE */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @brief  Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
-  * @note   This macro must be used only when the PLLI2S is disabled.
-  * @note   PLLI2S clock source is common with the main PLL (configured in 
-  *         HAL_RCC_ClockConfig() API)             
-  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
-  * @param  __PLLI2SQ__ specifies the division factor for SAI1 clock.
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
-  * @note   the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx 
-  *         Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
-  * @param  __PLLI2SR__ specifies the division factor for I2S clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
-  *         on the I2S clock frequency.
-  */
-#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U)  |\
-                                                                                                 ((__PLLI2SQ__) << 24U) |\
-                                                                                                 ((__PLLI2SR__) << 28U))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */   
-/*----------------------------------------------------------------------------*/
-
-/*------------------------------ PLLSAI Configuration ------------------------*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @brief Macros to Enable or Disable the PLLISAI. 
-  * @note  The PLLSAI is only available with STM32F429x/439x Devices.
-  * @note  The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. 
-  */
-#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE)
-#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE)
-
-#if defined(STM32F446xx)
-/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
-  *
-  * @param  __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
-  * @note   You have to set the PLLSAIM parameter correctly to ensure that the VCO input
-  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
-  *         of 1 MHz to limit PLLI2S jitter.
-  * @note   The PLLSAIM parameter is only used with STM32F446xx Devices
-  *             
-  * @param  __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
-  *
-  * @param  __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks.
-  *         This parameter must be a number in the range {2, 4, 6, or 8}.
-  * @note   the PLLSAIP parameter is only available with STM32F446xx Devices
-  *                 
-  * @param  __PLLSAIQ__ specifies the division factor for SAI clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  *           
-  * @param  __PLLSAIR__ specifies the division factor for LTDC clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices  
-  */
-#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)     \
-                               (RCC->PLLSAICFGR = ((__PLLSAIM__)                                   | \
-                               ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos)             | \
-                               ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \
-                               ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))) 
-#endif /* STM32F446xx */
-                                 
-#if defined(STM32F469xx) || defined(STM32F479xx)
-/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
-  *             
-  * @param  __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
-  *
-  * @param  __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks.
-  *         This parameter must be a number in the range {2, 4, 6, or 8}.
-  *                 
-  * @param  __PLLSAIQ__ specifies the division factor for SAI clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  *           
-  * @param  __PLLSAIR__ specifies the division factor for LTDC clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.  
-  */
-#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
-                               (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos)             |\
-                                                   ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\
-                                                   ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)             |\
-                                                   ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
-#endif /* STM32F469xx || STM32F479xx */                                 
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
-  *             
-  * @param  __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
-  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
-  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
-  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
-  *
-  * @param  __PLLSAIQ__ specifies the division factor for SAI clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
-  *           
-  * @param  __PLLSAIR__ specifies the division factor for LTDC clock
-  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
-  * @note   the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices  
-  */
-#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__)                                        \
-                               (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos)  | \
-                               ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)                      | \
-                               ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/
-#if defined(STM32F413xx) || defined(STM32F423xx)
-/** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.
-  * @note   This function must be called before enabling the PLLI2S.
-  * @param  __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock.
-  *          This parameter must be a number between 1 and 32.
-  *          SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__ 
-  */
-#define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U))
-
-/** @brief  Macro to configure the SAI clock Divider coming from PLL.
-  * @param  __PLLDivR__ specifies the PLL division factor for SAI1 clock.
-  *          This parameter must be a number between 1 and 32.
-  *          SAI1 clock frequency = f(PLLR) / __PLLDivR__ 
-  */
-#define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U))                                 
-#endif /* STM32F413xx || STM32F423xx */  
-                                 
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)  || defined(STM32F446xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-/** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.
-  * @note   This function must be called before enabling the PLLI2S.
-  * @param  __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock.
-  *          This parameter must be a number between 1 and 32.
-  *          SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ 
-  */
-#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U))
-
-/** @brief  Macro to configure the SAI clock Divider coming from PLLSAI.
-  * @note   This function must be called before enabling the PLLSAI.
-  * @param  __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock .
-  *         This parameter must be a number between Min_Data = 1 and Max_Data = 32.
-  *         SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__  
-  */
-#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @brief  Macro to configure the LTDC clock Divider coming from PLLSAI.
-  * 
-  * @note   The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
-  * @note   This function must be called before enabling the PLLSAI. 
-  * @param  __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock .
-  *          This parameter must be a number between Min_Data = 2 and Max_Data = 16.
-  *          LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ 
-  */
-#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-/*----------------------------------------------------------------------------*/
-
-/*------------------------- Peripheral Clock selection -----------------------*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
-    defined(STM32F479xx)
-/** @brief  Macro to configure the I2S clock source (I2SCLK).
-  * @note   This function must be called before enabling the I2S APB clock.
-  * @param  __SOURCE__ specifies the I2S clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
-  *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
-  *                                       used as I2S clock source.
-  */
-#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
-
-
-/** @brief  Macro to get the I2S clock source (I2SCLK).
-  * @retval The clock source can be one of the following values:
-  *            @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
-  *            @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
-  *                                        used as I2S clock source
-  */
-#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
-#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
-                                 
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-                                 
-/** @brief  Macro to configure SAI1BlockA clock source selection.
-  * @note   The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.      
-  * @note   This function must be called before enabling PLLSAI, PLLI2S and  
-  *         the SAI clock.
-  * @param  __SOURCE__ specifies the SAI Block A clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 
-  *                                           as SAI1 Block A clock. 
-  *            @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 
-  *                                           as SAI1 Block A clock.
-  *            @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
-  *                                        used as SAI1 Block A clock.
-  */
-#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
-
-/** @brief  Macro to configure SAI1BlockB clock source selection.
-  * @note   The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
-  * @note   This function must be called before enabling PLLSAI, PLLI2S and  
-  *         the SAI clock.
-  * @param  __SOURCE__ specifies the SAI Block B clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 
-  *                                           as SAI1 Block B clock. 
-  *            @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 
-  *                                           as SAI1 Block B clock. 
-  *            @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
-  *                                        used as SAI1 Block B clock.
-  */
-#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F446xx)
-/** @brief  Macro to configure SAI1 clock source selection.
-  * @note   This configuration is only available with STM32F446xx Devices.
-  * @note   This function must be called before enabling PLL, PLLSAI, PLLI2S and  
-  *         the SAI clock.
-  * @param  __SOURCE__ specifies the SAI1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 
-  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
-  *            @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.  
-  *            @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
-  */
-#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
-
-/** @brief  Macro to Get SAI1 clock source selection.
-  * @note   This configuration is only available with STM32F446xx Devices.      
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 
-  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
-  *            @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.  
-  *            @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
-  */
-#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
-
-/** @brief  Macro to configure SAI2 clock source selection.
-  * @note   This configuration is only available with STM32F446xx Devices.      
-  * @note   This function must be called before enabling PLL, PLLSAI, PLLI2S and  
-  *         the SAI clock.
-  * @param  __SOURCE__ specifies the SAI2 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 
-  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
-  *            @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.  
-  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
-  */
-#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
-
-/** @brief  Macro to Get SAI2 clock source selection.
-  * @note   This configuration is only available with STM32F446xx Devices.      
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 
-  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
-  *            @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.  
-  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
-  */
-#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
-
-/** @brief  Macro to configure I2S APB1 clock source selection.
-  * @note   This function must be called before enabling PLL, PLLI2S and the I2S clock.
-  * @param  __SOURCE__ specifies the I2S APB1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 
-  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.  
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
-
-/** @brief  Macro to Get I2S APB1 clock source selection.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 
-  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.  
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
-
-/** @brief  Macro to configure I2S APB2 clock source selection.
-  * @note   This function must be called before enabling PLL, PLLI2S and the I2S clock.
-  * @param  __SOURCE__ specifies the SAI Block A clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 
-  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.  
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
-
-/** @brief  Macro to Get I2S APB2 clock source selection.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 
-  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.  
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
-
-/** @brief  Macro to configure the CEC clock.
-  * @param  __SOURCE__ specifies the CEC clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
-  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
-  */
-#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the CEC clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
-  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
-  */
-#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
-
-/** @brief  Macro to configure the FMPI2C1 clock.
-  * @param  __SOURCE__ specifies the FMPI2C1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
-  */
-#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the FMPI2C1 clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
-  */
-#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
-
-/** @brief  Macro to configure the CLK48 clock.
-  * @param  __SOURCE__ specifies the CLK48 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
-  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
-  */
-#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the CLK48 clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
-  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
-  */
-#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
-
-/** @brief  Macro to configure the SDIO clock.
-  * @param  __SOURCE__ specifies the SDIO clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
-  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
-  */
-#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the SDIO clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
-  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
-  */
-#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
-
-/** @brief  Macro to configure the SPDIFRX clock.
-  * @param  __SOURCE__ specifies the SPDIFRX clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.  
-  *            @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 
-  */
-#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the SPDIFRX clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.  
-  *            @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 
-  */
-#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
-#endif /* STM32F446xx */
-      
-#if defined(STM32F469xx) || defined(STM32F479xx)
-      
-/** @brief  Macro to configure the CLK48 clock.
-  * @param  __SOURCE__ specifies the CLK48 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
-  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
-  */
-#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the CLK48 clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
-  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
-  */
-#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
-
-/** @brief  Macro to configure the SDIO clock.
-  * @param  __SOURCE__ specifies the SDIO clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
-  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
-  */
-#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the SDIO clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
-  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
-  */
-#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))  
-      
-/** @brief  Macro to configure the DSI clock.
-  * @param  __SOURCE__ specifies the DSI clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 
-  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 
-  */
-#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the DSI clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 
-  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 
-  */
-#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))       
-      
-#endif /* STM32F469xx || STM32F479xx */
-
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
-    defined(STM32F413xx) || defined(STM32F423xx)
- /** @brief  Macro to configure the DFSDM1 clock.
-  * @param  __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 
-  *            @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock.
-  * @retval None
-  */
-#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__)  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
-
-/** @brief  Macro to get the DFSDM1 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 
-  *            @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock.
-  */
-#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
-
-/** @brief  Macro to configure DFSDM1 Audio clock source selection.
-  * @note   This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
-            STM32F413xx/STM32F423xx Devices.
-  * @param  __SOURCE__ specifies the DFSDM1 Audio clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
-  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
-  */
-#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
-
-/** @brief  Macro to Get DFSDM1 Audio clock source selection.
-  * @note   This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
-            STM32F413xx/STM32F423xx Devices.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
-  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
-  */
-#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
-
-#if defined(STM32F413xx) || defined(STM32F423xx)
- /** @brief  Macro to configure the DFSDM2 clock.
-  * @param  __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 
-  *            @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock.
-  * @retval None
-  */
-#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__)  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__))
-
-/** @brief  Macro to get the DFSDM2 clock source.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 
-  *            @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock.
-  */
-#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
-
-/** @brief  Macro to configure DFSDM1 Audio clock source selection.
-  * @note   This configuration is only available with STM32F413xx/STM32F423xx Devices.
-  * @param  __SOURCE__ specifies the DFSDM2 Audio clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
-  *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
-  */
-#define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__)))
-
-/** @brief  Macro to Get DFSDM2 Audio clock source selection.
-  * @note   This configuration is only available with STM32F413xx/STM32F423xx Devices.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
-  *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
-  */
-#define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL))
-      
-/** @brief  Macro to configure SAI1BlockA clock source selection.
-  * @note   The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.      
-  * @note   This function must be called before enabling PLLSAI, PLLI2S and  
-  *         the SAI clock.
-  * @param  __SOURCE__ specifies the SAI Block A clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
-  *            @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
-  *            @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
-  *            @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
-      
-/** @brief  Macro to Get SAI1 BlockA clock source selection.
-  * @note   This configuration is only available with STM32F413xx/STM32F423xx Devices.      
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
-  *            @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
-  *            @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
-  *            @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC))
-
-/** @brief  Macro to configure SAI1 BlockB clock source selection.
-  * @note   The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
-  * @note   This function must be called before enabling PLLSAI, PLLI2S and  
-  *         the SAI clock.
-  * @param  __SOURCE__ specifies the SAI Block B clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
-  *            @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
-  *            @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
-  *            @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
-      
-/** @brief  Macro to Get SAI1 BlockB clock source selection.
-  * @note   This configuration is only available with STM32F413xx/STM32F423xx Devices.      
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
-  *            @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
-  *            @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
-  *            @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC))
-
-/** @brief  Macro to configure the LPTIM1 clock.
-  * @param  __SOURCE__ specifies the LPTIM1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
-  */
-#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the LPTIM1 clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
-  */
-#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))      
-#endif /* STM32F413xx || STM32F423xx */
-      
-/** @brief  Macro to configure I2S APB1 clock source selection.
-  * @param  __SOURCE__ specifies the I2S APB1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
-  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
-
-/** @brief  Macro to Get I2S APB1 clock source selection.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
-  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
-  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
-
-/** @brief  Macro to configure I2S APB2 clock source selection.
-  * @param  __SOURCE__ specifies the I2S APB2 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
-  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
-
-/** @brief  Macro to Get I2S APB2 clock source selection.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
-  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
-  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  */
-#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
-
-/** @brief  Macro to configure the PLL I2S clock source (PLLI2SCLK).
-  * @note   This macro must be called before enabling the I2S APB clock.
-  * @param  __SOURCE__ specifies the I2S clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
-  *            @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
-  *                                       used as I2S clock source.
-  */
-#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
-      
-/** @brief  Macro to configure the FMPI2C1 clock.
-  * @param  __SOURCE__ specifies the FMPI2C1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
-  */
-#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the FMPI2C1 clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
-  */
-#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
-
-/** @brief  Macro to configure the CLK48 clock.
-  * @param  __SOURCE__ specifies the CLK48 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
-  *            @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.
-  */
-#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the CLK48 clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
-  *            @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock
-  */
-#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
-
-/** @brief  Macro to configure the SDIO clock.
-  * @param  __SOURCE__ specifies the SDIO clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
-  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
-  */
-#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the SDIO clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
-  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
-  */
-#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
-
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/** @brief  Macro to configure I2S clock source selection.
-  * @param  __SOURCE__ specifies the I2S clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
-  *            @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
-  *            @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
-  */
-#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
-
-/** @brief  Macro to Get I2S clock source selection.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
-  *            @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
-  *            @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
-  */
-#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
-
-/** @brief  Macro to configure the FMPI2C1 clock.
-  * @param  __SOURCE__ specifies the FMPI2C1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
-  */
-#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the FMPI2C1 clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
-  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
-  */
-#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
-
-/** @brief  Macro to configure the LPTIM1 clock.
-  * @param  __SOURCE__ specifies the LPTIM1 clock source.
-  *         This parameter can be one of the following values:
-  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
-  */
-#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
-
-/** @brief  Macro to Get the LPTIM1 clock.
-  * @retval The clock source can be one of the following values:
-  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
-  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
-  */
-#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-      
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-/** @brief  Macro to configure the Timers clocks prescalers 
-  * @note   This feature is only available with STM32F429x/439x Devices.  
-  * @param  __PRESC__  specifies the Timers clocks prescalers selection
-  *         This parameter can be one of the following values:
-  *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is 
-  *                 equal to HPRE if PPREx is corresponding to division by 1 or 2, 
-  *                 else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to 
-  *                 division by 4 or more.       
-  *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 
-  *                 equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, 
-  *                 else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding 
-  *                 to division by 8 or more.
-  */     
-#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\
-          STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx  || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx ||\
-          STM32F423xx */
-
-/*----------------------------------------------------------------------------*/
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/** @brief Enable PLLSAI_RDY interrupt.
-  */
-#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
-
-/** @brief Disable PLLSAI_RDY interrupt.
-  */
-#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
-
-/** @brief Clear the PLLSAI RDY interrupt pending bits.
-  */
-#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
-
-/** @brief Check the PLLSAI RDY interrupt has occurred or not.
-  * @retval The new state (TRUE or FALSE).
-  */
-#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
-
-/** @brief  Check PLLSAI RDY flag is set or not.
-  * @retval The new state (TRUE or FALSE).
-  */
-#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/** @brief  Macros to enable or disable the RCC MCO1 feature.
-  */
-#define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE)
-#define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE)
-
-/** @brief  Macros to enable or disable the RCC MCO2 feature.
-  */
-#define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE)
-#define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE)
-
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCCEx_Exported_Functions
-  *  @{
-  */
-
-/** @addtogroup RCCEx_Exported_Functions_Group1
-  *  @{
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
-    defined(STM32F423xx)
-void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
-#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-#if defined(RCC_PLLI2S_SUPPORT)
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit);
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
-#endif /* RCC_PLLI2S_SUPPORT */
-#if defined(RCC_PLLSAI_SUPPORT)
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef  *PLLSAIInit);
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
-#endif /* RCC_PLLSAI_SUPPORT */
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
-  * @{
-  */
-
-/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
-  * @brief RCC registers bit address in the alias region
-  * @{
-  */
-/* --- CR Register ---*/  
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/* Alias word address of PLLSAION bit */
-#define RCC_PLLSAION_BIT_NUMBER       0x1CU
-#define RCC_CR_PLLSAION_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U))
-
-#define PLLSAI_TIMEOUT_VALUE          2U  /* Timeout value fixed to 2 ms  */
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-/* Alias word address of PLLI2SON bit */
-#define RCC_PLLI2SON_BIT_NUMBER    0x1AU
-#define RCC_CR_PLLI2SON_BB         (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
-          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-/* --- DCKCFGR Register ---*/
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
-    defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-/* Alias word address of TIMPRE bit */
-#define RCC_DCKCFGR_OFFSET            (RCC_OFFSET + 0x8CU)
-#define RCC_TIMPRE_BIT_NUMBER          0x18U
-#define RCC_DCKCFGR_TIMPRE_BB         (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\
-          STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
-          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-/* --- CFGR Register ---*/
-#define RCC_CFGR_OFFSET            (RCC_OFFSET + 0x08U)
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx)
-/* Alias word address of I2SSRC bit */
-#define RCC_I2SSRC_BIT_NUMBER      0x17U
-#define RCC_CFGR_I2SSRC_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
-      
-#define PLLI2S_TIMEOUT_VALUE       2U  /* Timeout value fixed to 2 ms  */
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
-      
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
-    defined(STM32F413xx) || defined(STM32F423xx)
-/* --- PLLI2SCFGR Register ---*/
-#define RCC_PLLI2SCFGR_OFFSET         (RCC_OFFSET + 0x84U)
-/* Alias word address of PLLI2SSRC bit */
-#define RCC_PLLI2SSRC_BIT_NUMBER      0x16U
-#define RCC_PLLI2SCFGR_PLLI2SSRC_BB         (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U))
-      
-#define PLLI2S_TIMEOUT_VALUE          2U  /* Timeout value fixed to 2 ms */
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx | STM32F423xx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/* Alias word address of MCO1EN bit */
-#define RCC_MCO1EN_BIT_NUMBER      0x8U
-#define RCC_CFGR_MCO1EN_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U))
-
-/* Alias word address of MCO2EN bit */
-#define RCC_MCO2EN_BIT_NUMBER      0x9U
-#define RCC_CFGR_MCO2EN_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#define PLL_TIMEOUT_VALUE          2U  /* 2 ms */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
-  * @{
-  */
-/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
-  * @{
-  */
-#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
-#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
-      
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) 
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F446xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
-#endif /* STM32F446xx */
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
-#endif /* STM32F469xx || STM32F479xx */
-
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-      
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU))
-#endif /* STM32F413xx || STM32F423xx */
-      
-#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_RCC_PLLI2SQ_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 15U))
-
-#define IS_RCC_PLLSAIN_VALUE(VALUE)     ((50U <= (VALUE)) && ((VALUE) <= 432U))
-
-#define IS_RCC_PLLSAIQ_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 15U))
-
-#define IS_RCC_PLLSAIR_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 7U))
-
-#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
-
-#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
-
-#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2)  ||\
-                                         ((VALUE) == RCC_PLLSAIDIVR_4)  ||\
-                                         ((VALUE) == RCC_PLLSAIDIVR_8)  ||\
-                                         ((VALUE) == RCC_PLLSAIDIVR_16))
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-#define IS_RCC_PLLI2SM_VALUE(VALUE)   ((2U <= (VALUE)) && ((VALUE) <= 63U))
- 
-#define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
-                                         ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
-#endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx  */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
-
-#define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
-                                         ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
-
-#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1)    ||\
-                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
-                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
-
-#define IS_RCC_LPTIM1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\
-                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\
-                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\
-                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
-
-#define IS_RCC_I2SAPBCLKSOURCE(SOURCE)      (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR)    ||\
-                                             ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT)    ||\
-                                             ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F446xx)
-#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
-  
-#define IS_RCC_PLLI2SP_VALUE(VALUE)       (((VALUE) == RCC_PLLI2SP_DIV2) ||\
-                                           ((VALUE) == RCC_PLLI2SP_DIV4) ||\
-                                           ((VALUE) == RCC_PLLI2SP_DIV6) ||\
-                                           ((VALUE) == RCC_PLLI2SP_DIV8))
-
-#define IS_RCC_PLLSAIM_VALUE(VALUE)       ((VALUE) <= 63U)
-  
-#define IS_RCC_PLLSAIP_VALUE(VALUE)       (((VALUE) == RCC_PLLSAIP_DIV2) ||\
-                                           ((VALUE) == RCC_PLLSAIP_DIV4) ||\
-                                           ((VALUE) == RCC_PLLSAIP_DIV6) ||\
-                                           ((VALUE) == RCC_PLLSAIP_DIV8))
-
-#define IS_RCC_SAI1CLKSOURCE(SOURCE)      (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\
-                                           ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\
-                                           ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR)   ||\
-                                           ((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
-
-#define IS_RCC_SAI2CLKSOURCE(SOURCE)      (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\
-                                           ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\
-                                           ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR)   ||\
-                                           ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
- 
-#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
-                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT)    ||\
-                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR)   ||\
-                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
-                                              
- #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
-                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT)    ||\
-                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR)   ||\
-                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
-
-#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1)    ||\
-                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
-                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
-
-#define IS_RCC_CECCLKSOURCE(SOURCE)       (((SOURCE) == RCC_CECCLKSOURCE_HSI)   ||\
-                                           ((SOURCE) == RCC_CECCLKSOURCE_LSE))
-
-#define IS_RCC_CLK48CLKSOURCE(SOURCE)      (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
-                                            ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
-
-#define IS_RCC_SDIOCLKSOURCE(SOURCE)      (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
-                                           ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
-
-#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)   (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\
-                                           ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))  
-#endif /* STM32F446xx */
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-#define IS_RCC_PLLR_VALUE(VALUE)            ((2U <= (VALUE)) && ((VALUE) <= 7U))
-
-#define IS_RCC_PLLSAIP_VALUE(VALUE)         (((VALUE) == RCC_PLLSAIP_DIV2) ||\
-                                             ((VALUE) == RCC_PLLSAIP_DIV4) ||\
-                                             ((VALUE) == RCC_PLLSAIP_DIV6) ||\
-                                             ((VALUE) == RCC_PLLSAIP_DIV8))
- 
-#define IS_RCC_CLK48CLKSOURCE(SOURCE)        (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
-                                              ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
-
-#define IS_RCC_SDIOCLKSOURCE(SOURCE)        (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
-                                             ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
-
-#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR)  ||\
-                                             ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
-
-#define IS_RCC_LSE_MODE(MODE)               (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
-                                             ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
-#endif /* STM32F469xx || STM32F479xx */
-
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
-    defined(STM32F413xx) || defined(STM32F423xx)
-#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
-    
-#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
-
-#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \
-                                            ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
- 
-#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
-                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT)    ||\
-                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR)   ||\
-                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
-                                              
- #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
-                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT)    ||\
-                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR)   ||\
-                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
-
-#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1)    ||\
-                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
-                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
-
-#define IS_RCC_CLK48CLKSOURCE(SOURCE)      (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
-                                            ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
-
-#define IS_RCC_SDIOCLKSOURCE(SOURCE)      (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
-                                           ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
-
-#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \
-                                            ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
-
-#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) || \
-                                                 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2))
-
-#if defined(STM32F413xx) || defined(STM32F423xx)
-#define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) || \
-                                            ((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK))
-
-#define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) || \
-                                                 ((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2))
-
-#define IS_RCC_LPTIM1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\
-                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI)  ||\
-                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)  ||\
-                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
-
-#define IS_RCC_SAIACLKSOURCE(SOURCE)     (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) ||\
-                                          ((SOURCE) == RCC_SAIACLKSOURCE_EXT)     ||\
-                                          ((SOURCE) == RCC_SAIACLKSOURCE_PLLR)    ||\
-                                          ((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC))
-
-#define IS_RCC_SAIBCLKSOURCE(SOURCE)     (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) ||\
-                                          ((SOURCE) == RCC_SAIBCLKSOURCE_EXT)     ||\
-                                          ((SOURCE) == RCC_SAIBCLKSOURCE_PLLR)    ||\
-                                          ((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC))
-
-#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
-
-#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
-
-#endif /* STM32F413xx || STM32F423xx */
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
-    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
-    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
-      
-#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
-                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
-          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \
-          STM32F412Rx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)      
-#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \
-                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_RCC_EX_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rcc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_RCC_EX_H
+#define __STM32F4xx_HAL_RCC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RCCEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  RCC PLL configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PLLState;   /*!< The new state of the PLL.
+                            This parameter can be a value of @ref RCC_PLL_Config                      */
+
+  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.
+                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */
+
+  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.
+                            This parameter must be a number between Min_Data = 0 and Max_Data = 63    */
+
+  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432 
+                            except for STM32F411xE devices where the Min_Data = 192 */
+
+  uint32_t PLLP;       /*!< PLLP: Division factor for main system clock (SYSCLK).
+                            This parameter must be a value of @ref RCC_PLLP_Clock_Divider             */
+
+  uint32_t PLLQ;       /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15    */
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+    defined(STM32F413xx) || defined(STM32F423xx)
+  uint32_t PLLR;       /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
+                            This parameter is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx
+                            and STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices. 
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7     */
+#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 
+}RCC_PLLInitTypeDef;
+
+#if defined(STM32F446xx)
+/** 
+  * @brief  PLLI2S Clock structure definition  
+  */
+typedef struct
+{
+  uint32_t PLLI2SM;    /*!< Specifies division factor for PLL VCO input clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 63       */
+
+  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432    */
+
+  uint32_t PLLI2SP;    /*!< Specifies division factor for SPDIFRX Clock.
+                            This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider           */
+
+  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+                           
+  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S */
+}RCC_PLLI2SInitTypeDef;
+
+/** 
+  * @brief  PLLSAI Clock structure definition  
+  */
+typedef struct
+{
+  uint32_t PLLSAIM;    /*!< Specifies division factor for PLL VCO input clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 63       */
+
+  uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432    */
+
+  uint32_t PLLSAIP;    /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
+                            This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider           */
+                                                             
+  uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+                            This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+}RCC_PLLSAIInitTypeDef;
+
+/** 
+  * @brief  RCC extended clocks structure definition  
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. 
+                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters. 
+                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
+
+  uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
+                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+  uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
+                                      This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+
+  uint32_t Sai1ClockSelection;    /*!< Specifies SAI1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
+
+  uint32_t Sai2ClockSelection;    /*!< Specifies SAI2 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
+                                      
+  uint32_t I2sApb1ClockSelection;    /*!< Specifies I2S APB1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
+
+  uint32_t I2sApb2ClockSelection;    /*!< Specifies I2S APB2 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection. 
+                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+  uint32_t SdioClockSelection;    /*!< Specifies SDIO Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
+
+  uint32_t CecClockSelection;      /*!< Specifies CEC Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
+
+  uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
+
+  uint32_t SpdifClockSelection;    /*!< Specifies SPDIFRX Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
+
+  uint32_t Clk48ClockSelection;     /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 
+                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
+  
+  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F446xx */   
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** 
+  * @brief  RCC extended clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.
+                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  uint32_t I2SClockSelection;      /*!< Specifies RTC Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_I2S_APB_Clock_Source */
+                                      
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection. 
+                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
+  
+  uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
+
+  uint8_t TIMPresSelection;        /*!< Specifies TIM Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** 
+  * @brief  PLLI2S Clock structure definition  
+  */
+typedef struct
+{
+  uint32_t PLLI2SM;    /*!< Specifies division factor for PLL VCO input clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 63       */
+
+  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432    */
+
+  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+                           
+  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S */
+}RCC_PLLI2SInitTypeDef;
+
+/** 
+  * @brief  RCC extended clocks structure definition
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. 
+                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S */
+  
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  uint32_t PLLDivR;              /*!< Specifies the PLL division factor for SAI1 clock.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
+                                      This parameter will be used only when PLL is selected as Clock Source SAI */
+
+  uint32_t PLLI2SDivR;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
+                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+#endif /* STM32F413xx || STM32F423xx */  
+                                      
+  uint32_t I2sApb1ClockSelection;    /*!< Specifies I2S APB1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
+
+  uint32_t I2sApb2ClockSelection;    /*!< Specifies I2S APB2 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Source Selection. 
+                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+  uint32_t SdioClockSelection;    /*!< Specifies SDIO Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
+
+  uint32_t Fmpi2c1ClockSelection;  /*!< Specifies FMPI2C1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
+
+  uint32_t Clk48ClockSelection;     /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
+                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
+  
+  uint32_t Dfsdm1ClockSelection;    /*!< Specifies DFSDM1 Clock Selection.
+                                      This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
+
+  uint32_t Dfsdm1AudioClockSelection;/*!< Specifies DFSDM1 Audio Clock Selection.
+                                      This parameter can be a value of @ref RCCEx_DFSDM1_Audio_Clock_Source */
+  
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  uint32_t Dfsdm2ClockSelection;    /*!< Specifies DFSDM2 Clock Selection.
+                                      This parameter can be a value of @ref RCCEx_DFSDM2_Kernel_Clock_Source */
+
+  uint32_t Dfsdm2AudioClockSelection;/*!< Specifies DFSDM2 Audio Clock Selection.
+                                      This parameter can be a value of @ref RCCEx_DFSDM2_Audio_Clock_Source */
+  
+  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
+  
+  uint32_t SaiAClockSelection;     /*!< Specifies SAI1_A Clock Prescalers Selection
+                                        This parameter can be a value of @ref RCCEx_SAI1_BlockA_Clock_Source */
+
+  uint32_t SaiBClockSelection;     /*!< Specifies SAI1_B Clock Prescalers Selection
+                                        This parameter can be a value of @ref RCCEx_SAI1_BlockB_Clock_Source */
+#endif /* STM32F413xx || STM32F423xx */
+
+  uint32_t PLLI2SSelection;      /*!< Specifies PLL I2S Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_PLL_I2S_Clock_Source */
+
+  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
+/** 
+  * @brief  PLLI2S Clock structure definition  
+  */
+typedef struct
+{
+  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  uint32_t PLLI2SQ;    /*!< Specifies the division factor for SAI1 clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+}RCC_PLLI2SInitTypeDef;
+
+/** 
+  * @brief  PLLSAI Clock structure definition  
+  */
+typedef struct
+{
+  uint32_t PLLSAIN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */ 
+#if defined(STM32F469xx) || defined(STM32F479xx)
+  uint32_t PLLSAIP;    /*!< Specifies division factor for OTG FS and SDIO clocks.
+                            This parameter is only available in STM32F469xx/STM32F479xx devices.
+                            This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider  */  
+#endif /* STM32F469xx || STM32F479xx */
+                                 
+  uint32_t PLLSAIQ;    /*!< Specifies the division factor for SAI1 clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+                            This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
+                              
+  uint32_t PLLSAIR;    /*!< specifies the division factor for LTDC clock
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+                            This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
+
+}RCC_PLLSAIInitTypeDef;
+
+/** 
+  * @brief  RCC extended clocks structure definition  
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters. 
+                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  RCC_PLLSAIInitTypeDef PLLSAI;  /*!< PLL SAI structure parameters. 
+                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
+
+  uint32_t PLLI2SDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
+                                      This parameter will be used only when PLLI2S is selected as Clock Source SAI */
+
+  uint32_t PLLSAIDivQ;           /*!< Specifies the PLLI2S division factor for SAI1 clock.
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 32
+                                      This parameter will be used only when PLLSAI is selected as Clock Source SAI */
+
+  uint32_t PLLSAIDivR;           /*!< Specifies the PLLSAI division factor for LTDC clock.
+                                      This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection. 
+                                      This parameter can be a value of @ref RCC_RTC_Clock_Source */
+
+  uint8_t TIMPresSelection;      /*!< Specifies TIM Clock Prescalers Selection. 
+                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+#if defined(STM32F469xx) || defined(STM32F479xx)
+  uint32_t Clk48ClockSelection;  /*!< Specifies CLK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks. 
+                                      This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
+
+  uint32_t SdioClockSelection;   /*!< Specifies SDIO Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */  
+#endif /* STM32F469xx || STM32F479xx */  
+}RCC_PeriphCLKInitTypeDef;
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+/** 
+  * @brief  PLLI2S Clock structure definition  
+  */
+typedef struct
+{
+#if defined(STM32F411xE)
+  uint32_t PLLI2SM;    /*!< PLLM: Division factor for PLLI2S VCO input clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 62  */
+#endif /* STM32F411xE */
+                                
+  uint32_t PLLI2SN;    /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
+                            This parameter must be a number between Min_Data = 50 and Max_Data = 432
+                            Except for STM32F411xE devices where the Min_Data = 192. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  uint32_t PLLI2SR;    /*!< Specifies the division factor for I2S clock.
+                            This parameter must be a number between Min_Data = 2 and Max_Data = 7. 
+                            This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+}RCC_PLLI2SInitTypeDef;
+ 
+/** 
+  * @brief  RCC extended clocks structure definition  
+  */
+typedef struct
+{
+  uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
+                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
+
+  RCC_PLLI2SInitTypeDef PLLI2S;  /*!< PLL I2S structure parameters.
+                                      This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
+
+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock Prescalers Selection.
+                                       This parameter can be a value of @ref RCC_RTC_Clock_Source */
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
+  uint8_t TIMPresSelection;        /*!< Specifies TIM Clock Source Selection. 
+                                      This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+}RCC_PeriphCLKInitTypeDef;
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+/**
+  * @}
+  */ 
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
+  * @{
+  */
+
+/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
+  * @{
+  */
+/* Peripheral Clock source for STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+    defined(STM32F413xx) || defined(STM32F423xx)
+#define RCC_PERIPHCLK_I2S_APB1        0x00000001U
+#define RCC_PERIPHCLK_I2S_APB2        0x00000002U
+#define RCC_PERIPHCLK_TIM             0x00000004U
+#define RCC_PERIPHCLK_RTC             0x00000008U
+#define RCC_PERIPHCLK_FMPI2C1         0x00000010U
+#define RCC_PERIPHCLK_CLK48           0x00000020U
+#define RCC_PERIPHCLK_SDIO            0x00000040U
+#define RCC_PERIPHCLK_PLLI2S          0x00000080U
+#define RCC_PERIPHCLK_DFSDM1          0x00000100U
+#define RCC_PERIPHCLK_DFSDM1_AUDIO    0x00000200U
+#endif /* STM32F412Zx || STM32F412Vx) || STM32F412Rx || STM32F412Cx */
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define RCC_PERIPHCLK_DFSDM2          0x00000400U
+#define RCC_PERIPHCLK_DFSDM2_AUDIO    0x00000800U
+#define RCC_PERIPHCLK_LPTIM1          0x00001000U
+#define RCC_PERIPHCLK_SAIA            0x00002000U
+#define RCC_PERIPHCLK_SAIB            0x00004000U
+#endif /* STM32F413xx || STM32F423xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------- Peripheral Clock source for STM32F410xx ----------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define RCC_PERIPHCLK_I2S             0x00000001U
+#define RCC_PERIPHCLK_TIM             0x00000002U
+#define RCC_PERIPHCLK_RTC             0x00000004U
+#define RCC_PERIPHCLK_FMPI2C1         0x00000008U
+#define RCC_PERIPHCLK_LPTIM1          0x00000010U
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------- Peripheral Clock source for STM32F446xx ----------------*/
+#if defined(STM32F446xx)
+#define RCC_PERIPHCLK_I2S_APB1        0x00000001U
+#define RCC_PERIPHCLK_I2S_APB2        0x00000002U
+#define RCC_PERIPHCLK_SAI1            0x00000004U
+#define RCC_PERIPHCLK_SAI2            0x00000008U
+#define RCC_PERIPHCLK_TIM             0x00000010U
+#define RCC_PERIPHCLK_RTC             0x00000020U
+#define RCC_PERIPHCLK_CEC             0x00000040U
+#define RCC_PERIPHCLK_FMPI2C1         0x00000080U
+#define RCC_PERIPHCLK_CLK48           0x00000100U
+#define RCC_PERIPHCLK_SDIO            0x00000200U
+#define RCC_PERIPHCLK_SPDIFRX         0x00000400U
+#define RCC_PERIPHCLK_PLLI2S          0x00000800U
+#endif /* STM32F446xx */
+/*-----------------------------------------------------------------------------*/
+    
+/*----------- Peripheral Clock source for STM32F469xx/STM32F479xx -------------*/
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define RCC_PERIPHCLK_I2S             0x00000001U
+#define RCC_PERIPHCLK_SAI_PLLI2S      0x00000002U
+#define RCC_PERIPHCLK_SAI_PLLSAI      0x00000004U
+#define RCC_PERIPHCLK_LTDC            0x00000008U
+#define RCC_PERIPHCLK_TIM             0x00000010U
+#define RCC_PERIPHCLK_RTC             0x00000020U
+#define RCC_PERIPHCLK_PLLI2S          0x00000040U
+#define RCC_PERIPHCLK_CLK48           0x00000080U
+#define RCC_PERIPHCLK_SDIO            0x00000100U
+#endif /* STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*-------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+#define RCC_PERIPHCLK_I2S             0x00000001U
+#define RCC_PERIPHCLK_SAI_PLLI2S      0x00000002U
+#define RCC_PERIPHCLK_SAI_PLLSAI      0x00000004U
+#define RCC_PERIPHCLK_LTDC            0x00000008U
+#define RCC_PERIPHCLK_TIM             0x00000010U
+#define RCC_PERIPHCLK_RTC             0x00000020U
+#define RCC_PERIPHCLK_PLLI2S          0x00000040U
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+/*----------------------------------------------------------------------------*/
+
+/*-------- Peripheral Clock source for STM32F40xxx/STM32F41xxx ---------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
+#define RCC_PERIPHCLK_I2S             0x00000001U
+#define RCC_PERIPHCLK_RTC             0x00000002U
+#define RCC_PERIPHCLK_PLLI2S          0x00000004U
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+#define RCC_PERIPHCLK_TIM             0x00000008U
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */      
+/*----------------------------------------------------------------------------*/
+/**
+  * @}
+  */
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || \
+    defined(STM32F479xx) 
+/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
+  * @{
+  */
+#define RCC_I2SCLKSOURCE_PLLI2S         0x00000000U
+#define RCC_I2SCLKSOURCE_EXT            0x00000001U
+/**
+  * @}
+  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */
+
+/** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
+  * @{
+  */
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx) 
+#define RCC_PLLSAIDIVR_2                0x00000000U
+#define RCC_PLLSAIDIVR_4                0x00010000U
+#define RCC_PLLSAIDIVR_8                0x00020000U
+#define RCC_PLLSAIDIVR_16               0x00030000U
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
+  * @{
+  */
+#if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
+#define RCC_PLLI2SP_DIV2                  0x00000002U
+#define RCC_PLLI2SP_DIV4                  0x00000004U
+#define RCC_PLLI2SP_DIV6                  0x00000006U
+#define RCC_PLLI2SP_DIV8                  0x00000008U
+#endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
+  * @{
+  */
+#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 
+#define RCC_PLLSAIP_DIV2                  0x00000002U
+#define RCC_PLLSAIP_DIV4                  0x00000004U
+#define RCC_PLLSAIP_DIV6                  0x00000006U
+#define RCC_PLLSAIP_DIV8                  0x00000008U
+#endif /* STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup RCCEx_SAI_BlockA_Clock_Source  RCC SAI BlockA Clock Source
+  * @{
+  */
+#define RCC_SAIACLKSOURCE_PLLSAI             0x00000000U
+#define RCC_SAIACLKSOURCE_PLLI2S             0x00100000U
+#define RCC_SAIACLKSOURCE_EXT                0x00200000U
+/**
+  * @}
+  */ 
+
+/** @defgroup RCCEx_SAI_BlockB_Clock_Source  RCC SAI BlockB Clock Source
+  * @{
+  */
+#define RCC_SAIBCLKSOURCE_PLLSAI             0x00000000U
+#define RCC_SAIBCLKSOURCE_PLLI2S             0x00400000U
+#define RCC_SAIBCLKSOURCE_EXT                0x00800000U
+/**
+  * @}
+  */ 
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+      
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source
+  * @{
+  */
+#define RCC_CLK48CLKSOURCE_PLLQ              0x00000000U
+#define RCC_CLK48CLKSOURCE_PLLSAIP           ((uint32_t)RCC_DCKCFGR_CK48MSEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
+  * @{
+  */
+#define RCC_SDIOCLKSOURCE_CLK48             0x00000000U
+#define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR_SDIOSEL)
+/**
+  * @}
+  */    
+  
+/** @defgroup RCCEx_DSI_Clock_Source  RCC DSI Clock Source
+  * @{
+  */
+#define RCC_DSICLKSOURCE_DSIPHY             0x00000000U
+#define RCC_DSICLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_DSISEL)
+/**
+  * @}
+  */
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F446xx)
+/** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source 
+  * @{
+  */
+#define RCC_SAI1CLKSOURCE_PLLSAI             0x00000000U
+#define RCC_SAI1CLKSOURCE_PLLI2S             ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
+#define RCC_SAI1CLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
+#define RCC_SAI1CLKSOURCE_EXT                ((uint32_t)RCC_DCKCFGR_SAI1SRC)
+/**
+  * @}
+  */ 
+
+/** @defgroup RCCEx_SAI2_Clock_Source  RCC SAI2 Clock Source
+  * @{
+  */
+#define RCC_SAI2CLKSOURCE_PLLSAI             0x00000000U
+#define RCC_SAI2CLKSOURCE_PLLI2S             ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
+#define RCC_SAI2CLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
+#define RCC_SAI2CLKSOURCE_PLLSRC             ((uint32_t)RCC_DCKCFGR_SAI2SRC)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2SAPB1_Clock_Source  RCC I2S APB1 Clock Source
+  * @{
+  */
+#define RCC_I2SAPB1CLKSOURCE_PLLI2S          0x00000000U
+#define RCC_I2SAPB1CLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
+#define RCC_I2SAPB1CLKSOURCE_PLLR            ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
+#define RCC_I2SAPB1CLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2S1SRC)
+/**
+  * @}
+  */ 
+
+/** @defgroup RCCEx_I2SAPB2_Clock_Source  RCC I2S APB2 Clock Source
+  * @{
+  */
+#define RCC_I2SAPB2CLKSOURCE_PLLI2S          0x00000000U
+#define RCC_I2SAPB2CLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
+#define RCC_I2SAPB2CLKSOURCE_PLLR            ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
+#define RCC_I2SAPB2CLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2S2SRC)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source
+  * @{
+  */
+#define RCC_FMPI2C1CLKSOURCE_PCLK1            0x00000000U
+#define RCC_FMPI2C1CLKSOURCE_SYSCLK           ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
+#define RCC_FMPI2C1CLKSOURCE_HSI              ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CEC_Clock_Source  RCC CEC Clock Source
+  * @{
+  */
+#define RCC_CECCLKSOURCE_HSI                0x00000000U
+#define RCC_CECCLKSOURCE_LSE                ((uint32_t)RCC_DCKCFGR2_CECSEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source
+  * @{
+  */
+#define RCC_CLK48CLKSOURCE_PLLQ              0x00000000U
+#define RCC_CLK48CLKSOURCE_PLLSAIP           ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
+  * @{
+  */
+#define RCC_SDIOCLKSOURCE_CLK48             0x00000000U
+#define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SPDIFRX_Clock_Source   RCC SPDIFRX Clock Source
+  * @{
+  */
+#define RCC_SPDIFRXCLKSOURCE_PLLR           0x00000000U
+#define RCC_SPDIFRXCLKSOURCE_PLLI2SP        ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
+/**
+  * @}
+  */
+
+#endif /* STM32F446xx */
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup RCCEx_SAI1_BlockA_Clock_Source  RCC SAI BlockA Clock Source
+  * @{
+  */
+#define RCC_SAIACLKSOURCE_PLLI2SR            0x00000000U
+#define RCC_SAIACLKSOURCE_EXT                ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0)
+#define RCC_SAIACLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI1ASRC_1)
+#define RCC_SAIACLKSOURCE_PLLSRC             ((uint32_t)RCC_DCKCFGR_SAI1ASRC_0 | RCC_DCKCFGR_SAI1ASRC_1)
+/**
+  * @}
+  */ 
+
+/** @defgroup RCCEx_SAI1_BlockB_Clock_Source  RCC SAI BlockB Clock Source
+  * @{
+  */
+#define RCC_SAIBCLKSOURCE_PLLI2SR            0x00000000U
+#define RCC_SAIBCLKSOURCE_EXT                ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0)
+#define RCC_SAIBCLKSOURCE_PLLR               ((uint32_t)RCC_DCKCFGR_SAI1BSRC_1)
+#define RCC_SAIBCLKSOURCE_PLLSRC             ((uint32_t)RCC_DCKCFGR_SAI1BSRC_0 | RCC_DCKCFGR_SAI1BSRC_1)
+/**
+  * @}
+  */ 
+      
+/** @defgroup RCCEx_LPTIM1_Clock_Source  RCC LPTIM1 Clock Source
+  * @{
+  */
+#define RCC_LPTIM1CLKSOURCE_PCLK1           0x00000000U
+#define RCC_LPTIM1CLKSOURCE_HSI             ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
+#define RCC_LPTIM1CLKSOURCE_LSI             ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSE             ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
+/**
+  * @}
+  */
+      
+
+/** @defgroup RCCEx_DFSDM2_Audio_Clock_Source  RCC DFSDM2 Audio Clock Source
+  * @{
+  */
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2S1       0x00000000U
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2S2       ((uint32_t)RCC_DCKCFGR_CKDFSDM2ASEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_DFSDM2_Kernel_Clock_Source  RCC DFSDM2 Kernel Clock Source
+  * @{
+  */
+#define RCC_DFSDM2CLKSOURCE_PCLK2           0x00000000U
+#define RCC_DFSDM2CLKSOURCE_SYSCLK          ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
+/**
+  * @}
+  */
+
+#endif /* STM32F413xx || STM32F423xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup RCCEx_PLL_I2S_Clock_Source PLL I2S Clock Source
+  * @{
+  */
+#define RCC_PLLI2SCLKSOURCE_PLLSRC          0x00000000U 
+#define RCC_PLLI2SCLKSOURCE_EXT             ((uint32_t)RCC_PLLI2SCFGR_PLLI2SSRC)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_DFSDM1_Audio_Clock_Source  RCC DFSDM1 Audio Clock Source
+  * @{
+  */
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2S1       0x00000000U
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2S2       ((uint32_t)RCC_DCKCFGR_CKDFSDM1ASEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source  RCC DFSDM1 Kernel Clock Source
+  * @{
+  */
+#define RCC_DFSDM1CLKSOURCE_PCLK2           0x00000000U
+#define RCC_DFSDM1CLKSOURCE_SYSCLK          ((uint32_t)RCC_DCKCFGR_CKDFSDM1SEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2SAPB1_Clock_Source  RCC I2S APB1 Clock Source
+  * @{
+  */
+#define RCC_I2SAPB1CLKSOURCE_PLLI2S         0x00000000U
+#define RCC_I2SAPB1CLKSOURCE_EXT            ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
+#define RCC_I2SAPB1CLKSOURCE_PLLR           ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
+#define RCC_I2SAPB1CLKSOURCE_PLLSRC         ((uint32_t)RCC_DCKCFGR_I2S1SRC)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_I2SAPB2_Clock_Source  RCC I2S APB2 Clock Source
+  * @{
+  */
+#define RCC_I2SAPB2CLKSOURCE_PLLI2S         0x00000000U
+#define RCC_I2SAPB2CLKSOURCE_EXT            ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
+#define RCC_I2SAPB2CLKSOURCE_PLLR           ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
+#define RCC_I2SAPB2CLKSOURCE_PLLSRC         ((uint32_t)RCC_DCKCFGR_I2S2SRC)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source
+  * @{
+  */
+#define RCC_FMPI2C1CLKSOURCE_PCLK1          0x00000000U
+#define RCC_FMPI2C1CLKSOURCE_SYSCLK         ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
+#define RCC_FMPI2C1CLKSOURCE_HSI            ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_CLK48_Clock_Source  RCC CLK48 Clock Source
+  * @{
+  */
+#define RCC_CLK48CLKSOURCE_PLLQ             0x00000000U
+#define RCC_CLK48CLKSOURCE_PLLI2SQ          ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_SDIO_Clock_Source  RCC SDIO Clock Source
+  * @{
+  */
+#define RCC_SDIOCLKSOURCE_CLK48             0x00000000U
+#define RCC_SDIOCLKSOURCE_SYSCLK            ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
+/**
+  * @}
+  */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+
+/** @defgroup RCCEx_I2S_APB_Clock_Source  RCC I2S APB Clock Source
+  * @{
+  */
+#define RCC_I2SAPBCLKSOURCE_PLLR            0x00000000U
+#define RCC_I2SAPBCLKSOURCE_EXT             ((uint32_t)RCC_DCKCFGR_I2SSRC_0)
+#define RCC_I2SAPBCLKSOURCE_PLLSRC          ((uint32_t)RCC_DCKCFGR_I2SSRC_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_FMPI2C1_Clock_Source  RCC FMPI2C1 Clock Source
+  * @{
+  */
+#define RCC_FMPI2C1CLKSOURCE_PCLK1              0x00000000U
+#define RCC_FMPI2C1CLKSOURCE_SYSCLK             ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
+#define RCC_FMPI2C1CLKSOURCE_HSI                ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_LPTIM1_Clock_Source  RCC LPTIM1 Clock Source
+  * @{
+  */
+#define RCC_LPTIM1CLKSOURCE_PCLK1          0x00000000U
+#define RCC_LPTIM1CLKSOURCE_HSI            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0)
+#define RCC_LPTIM1CLKSOURCE_LSI            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_1)
+#define RCC_LPTIM1CLKSOURCE_LSE            ((uint32_t)RCC_DCKCFGR2_LPTIM1SEL_0 | RCC_DCKCFGR2_LPTIM1SEL_1)
+/**
+  * @}
+  */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup RCCEx_TIM_PRescaler_Selection  RCC TIM PRescaler Selection
+  * @{
+  */
+#define RCC_TIMPRES_DESACTIVATED        ((uint8_t)0x00)
+#define RCC_TIMPRES_ACTIVATED           ((uint8_t)0x01)
+/**
+  * @}
+  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE ||\
+          STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+/** @defgroup RCCEx_LSE_Dual_Mode_Selection  RCC LSE Dual Mode Selection
+  * @{
+  */
+#define RCC_LSE_LOWPOWER_MODE           ((uint8_t)0x00)
+#define RCC_LSE_HIGHDRIVE_MODE          ((uint8_t)0x01)
+/**
+  * @}
+  */
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||\
+          STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
+  * @{
+  */
+#define RCC_MCO2SOURCE_SYSCLK            0x00000000U
+#define RCC_MCO2SOURCE_PLLI2SCLK         RCC_CFGR_MCO2_0
+#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
+#define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2
+/**
+  * @}
+  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+          STM32F412Rx || STM32F413xx | STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
+  * @{
+  */
+#define RCC_MCO2SOURCE_SYSCLK            0x00000000U
+#define RCC_MCO2SOURCE_I2SCLK            RCC_CFGR_MCO2_0
+#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1
+#define RCC_MCO2SOURCE_PLLCLK            RCC_CFGR_MCO2
+/**
+  * @}
+  */
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/**
+  * @}
+  */
+     
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
+  * @{
+  */
+/*------------------- STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx --------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOI_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOF_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOG_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOJ_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOK_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_DMA2D_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_ETHMAC_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+                                         UNUSED(tmpreg); \
+                                         } while(0U)
+#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
+                                         __IO uint32_t tmpreg = 0x00U; \
+                                         SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+                                         /* Delay after an RCC peripheral clock enabling */ \
+                                         tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+                                         UNUSED(tmpreg); \
+                                         } while(0U)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
+#define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
+#define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
+#define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
+#define __HAL_RCC_ETHMAC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
+#define __HAL_RCC_ETHMACTX_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
+#define __HAL_RCC_ETHMACRX_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
+#define __HAL_RCC_ETHMACPTP_CLK_DISABLE()       (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+
+/**
+  * @brief  Enable ETHERNET clock.
+  */
+#define __HAL_RCC_ETH_CLK_ENABLE() do {                                     \
+                                        __HAL_RCC_ETHMAC_CLK_ENABLE();      \
+                                        __HAL_RCC_ETHMACTX_CLK_ENABLE();    \
+                                        __HAL_RCC_ETHMACRX_CLK_ENABLE();    \
+                                      } while(0U)
+/**
+  * @brief  Disable ETHERNET clock.
+  */
+#define __HAL_RCC_ETH_CLK_DISABLE()  do {                                      \
+                                          __HAL_RCC_ETHMACTX_CLK_DISABLE();    \
+                                          __HAL_RCC_ETHMACRX_CLK_DISABLE();    \
+                                          __HAL_RCC_ETHMAC_CLK_DISABLE();      \
+                                        } while(0U)
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET) 
+#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET) 
+#define __HAL_RCC_GPIOK_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET) 
+#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET) 
+#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
+#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+#define __HAL_RCC_ETH_IS_CLK_ENABLED()             (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
+                                                    __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
+                                                    __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()) 
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET) 
+#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET) 
+#define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
+#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET) 
+#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET) 
+#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
+#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+#define __HAL_RCC_ETH_IS_CLK_DISABLED()             (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
+                                                     __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
+                                                     __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+ #define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+
+#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
+#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_HASH_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
+#define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
+                                              }while(0U)
+                                        
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+
+#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */ 
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
+
+#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx)
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
+#define __HAL_RCC_CRYP_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
+
+#define __HAL_RCC_HASH_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
+#define __HAL_RCC_HASH_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)     
+/**
+  * @}
+  */   
+
+/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{  
+  */
+#define __HAL_RCC_FMC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_FMC_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_QSPI_CLK_DISABLE()  (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+
+/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
+#define __HAL_RCC_FMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
+#endif /* STM32F469xx || STM32F479xx */  
+/**
+  * @}
+  */
+    
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART4_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART5_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_DAC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART7_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART8_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#define __HAL_RCC_UART7_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
+#define __HAL_RCC_UART8_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)  
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)  
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 
+#define __HAL_RCC_UART7_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
+#define __HAL_RCC_UART8_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)  
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)  
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 
+#define __HAL_RCC_UART7_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
+#define __HAL_RCC_UART8_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET) 
+/**
+  * @}
+  */
+    
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI6_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+#define __HAL_RCC_SPI6_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
+#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
+
+#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_LTDC_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
+#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_DSI_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */  
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
+#define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 
+#define __HAL_RCC_SPI6_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) 
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) 
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))!= RESET)  
+
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN))== RESET)
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
+#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
+#define __HAL_RCC_SPI6_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
+
+#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_LTDC_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
+#define __HAL_RCC_LTDC_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
+#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_DSI_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
+#define __HAL_RCC_DSI_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
+#endif /* STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOI_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_GPIOJ_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
+#define __HAL_RCC_GPIOK_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
+#define __HAL_RCC_DMA2D_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
+#define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOI_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_GPIOJ_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
+#define __HAL_RCC_GPIOK_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
+#define __HAL_RCC_DMA2D_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
+#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) 
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+
+#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 
+#define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+
+#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */ 
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
+#define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_FMC_RELEASE_RESET()  (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))  
+#endif /* STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */ 
+#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_UART7_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
+#define __HAL_RCC_UART8_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
+#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_UART7_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
+#define __HAL_RCC_UART8_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM8_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SPI5_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SPI6_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
+#define __HAL_RCC_SAI1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
+#define __HAL_RCC_SDIO_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
+#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
+
+#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_LTDC_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
+#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
+#endif /* STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_DSI_FORCE_RESET()   (RCC->APB2RSTR |=  (RCC_APB2RSTR_DSIRST))
+#define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
+#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+
+#if defined(STM32F437xx)|| defined(STM32F439xx) || defined(STM32F479xx) 
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
+#endif /* STM32F437xx || STM32F439xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */  
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
+/**
+  * @}
+  */
+                                        
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */ 
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
+
+#if defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
+
+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
+#endif /* STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |=  (RCC_APB2LPENR_DSILPEN))
+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
+#endif /* STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------- STM32F40xxx/STM32F41xxx-----------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \
+                                       __IO uint32_t tmpreg = 0x00U; \
+                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+                                       /* Delay after an RCC peripheral clock enabling */ \
+                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
+                                       UNUSED(tmpreg); \
+                                       } while(0U)
+#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \
+                                       __IO uint32_t tmpreg = 0x00U; \
+                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                       /* Delay after an RCC peripheral clock enabling */ \
+                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                       UNUSED(tmpreg); \
+                                       } while(0U)
+#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \
+                                       __IO uint32_t tmpreg = 0x00U; \
+                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                       /* Delay after an RCC peripheral clock enabling */ \
+                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                       UNUSED(tmpreg); \
+                                       } while(0U)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \
+                                       __IO uint32_t tmpreg = 0x00U; \
+                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+                                       /* Delay after an RCC peripheral clock enabling */ \
+                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+                                       UNUSED(tmpreg); \
+                                       } while(0U)
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                       __IO uint32_t tmpreg = 0x00U; \
+                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+                                       /* Delay after an RCC peripheral clock enabling */ \
+                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+                                       UNUSED(tmpreg); \
+                                       } while(0U)
+#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#if defined(STM32F407xx)|| defined(STM32F417xx)
+/**
+  * @brief  Enable ETHERNET clock.
+  */
+#define __HAL_RCC_ETHMAC_CLK_ENABLE()  do { \
+                                       __IO uint32_t tmpreg = 0x00U; \
+                                       SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+                                       /* Delay after an RCC peripheral clock enabling */ \
+                                       tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
+                                       UNUSED(tmpreg); \
+                                       } while(0U)
+#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_ETH_CLK_ENABLE()      do {                            \
+                                        __HAL_RCC_ETHMAC_CLK_ENABLE();      \
+                                        __HAL_RCC_ETHMACTX_CLK_ENABLE();    \
+                                        __HAL_RCC_ETHMACRX_CLK_ENABLE();    \
+                                        } while(0U)
+
+/**
+  * @brief  Disable ETHERNET clock.
+  */
+#define __HAL_RCC_ETHMAC_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
+#define __HAL_RCC_ETHMACTX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
+#define __HAL_RCC_ETHMACRX_CLK_DISABLE()  (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
+#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))  
+#define __HAL_RCC_ETH_CLK_DISABLE()       do {                             \
+                                           __HAL_RCC_ETHMACTX_CLK_DISABLE();    \
+                                           __HAL_RCC_ETHMACRX_CLK_DISABLE();    \
+                                           __HAL_RCC_ETHMAC_CLK_DISABLE();      \
+                                          } while(0U)
+#endif /* STM32F407xx || STM32F417xx */
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */  
+#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN))== RESET)
+#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+#if defined(STM32F407xx)|| defined(STM32F417xx)
+/**
+  * @brief  Enable ETHERNET clock.
+  */
+#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED()   ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
+#define __HAL_RCC_ETH_IS_CLK_ENABLED()        (__HAL_RCC_ETHMAC_IS_CLK_ENABLED()   && \
+                                               __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
+                                               __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
+/**
+  * @brief  Disable ETHERNET clock.
+  */
+#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
+#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
+#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
+#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
+#define __HAL_RCC_ETH_IS_CLK_DISABLED()        (__HAL_RCC_ETHMAC_IS_CLK_DISABLED()   && \
+                                                __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
+                                                __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
+#endif /* STM32F407xx || STM32F417xx */
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable 
+  * @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
+                                              }while(0U)
+                                        
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+
+#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+
+#if defined(STM32F407xx)|| defined(STM32F417xx) 
+#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+#endif /* STM32F407xx || STM32F417xx */
+
+#if defined(STM32F415xx) || defined(STM32F417xx)
+#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_HASH_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CRYP_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
+#define __HAL_RCC_HASH_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
+#endif /* STM32F415xx || STM32F417xx */
+/**
+  * @}
+  */
+
+
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET) 
+
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)   
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 
+
+#if defined(STM32F407xx)|| defined(STM32F417xx) 
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET) 
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET) 
+#endif /* STM32F407xx || STM32F417xx */
+
+#if defined(STM32F415xx) || defined(STM32F417xx)
+#define __HAL_RCC_CRYP_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET) 
+#define __HAL_RCC_HASH_IS_CLK_ENABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET) 
+
+#define __HAL_RCC_CRYP_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET) 
+#define __HAL_RCC_HASH_IS_CLK_DISABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET) 
+#endif /* STM32F415xx || STM32F417xx */  
+/**
+  * @}
+  */  
+  
+/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{  
+  */
+#define __HAL_RCC_FSMC_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_FSMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 
+#define __HAL_RCC_FSMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET) 
+/**
+  * @}
+  */   
+   
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{  
+  */
+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART4_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART5_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_DAC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __HAL_RCC_DAC_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+/**
+  * @}
+  */
+ 
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */ 
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)  
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET) 
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET) 
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET) 
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET) 
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 
+#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET) 
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET) 
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET) 
+#define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)  
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET) 
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET) 
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET) 
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET) 
+#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET) 
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET) 
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET) 
+#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 
+  /**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */ 
+#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)  
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)  
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET) 
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET) 
+#define __HAL_RCC_ADC2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
+  
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)  
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)  
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) 
+#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
+/**
+  * @}
+  */
+    
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOI_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_ETHMAC_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_GPIOI_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
+#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()         (RCC->AHB2RSTR = 0xFFFFFFFFU) 
+#define __HAL_RCC_AHB2_RELEASE_RESET()       (RCC->AHB2RSTR = 0x00U)
+
+#if defined(STM32F407xx)|| defined(STM32F417xx)  
+#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+#endif /* STM32F407xx || STM32F417xx */
+
+#if defined(STM32F415xx) || defined(STM32F417xx) 
+#define __HAL_RCC_CRYP_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
+
+#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
+#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
+#endif /* STM32F415xx || STM32F417xx */
+   
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */ 
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
+
+#define __HAL_RCC_FSMC_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
+#define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM8_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SDIO_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET()  (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+                                          
+#define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()(RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+/**
+  * @}
+  */
+                                        
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE()     (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE()   (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE()    (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
+#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
+#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE()  (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
+#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+
+#if defined(STM32F407xx)|| defined(STM32F417xx) 
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+#endif /* STM32F407xx || STM32F417xx */
+
+#if defined(STM32F415xx) || defined(STM32F417xx) 
+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
+
+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
+#endif /* STM32F415xx || STM32F417xx */
+/**
+  * @}
+  */
+                                        
+/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
+#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
+/**
+  * @}
+  */
+                                        
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+/**
+  * @}
+  */
+                                        
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+/**
+  * @}
+  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------------- STM32F401xE/STM32F401xC --------------------------*/
+#if defined(STM32F401xC) || defined(STM32F401xE)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.   
+  * @{
+  */
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE()  do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_GPIOD_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)  
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)  
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET)  
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()        ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)  
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)  
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)  
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
+                                              }while(0U)
+                                        
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+/**
+  * @}
+  */  
+  
+/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)  
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)   
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)  
+
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET) 
+/**
+  * @}
+  */
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */  
+#define __HAL_RCC_AHB1_FORCE_RESET()    (RCC->AHB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_AHB1_RELEASE_RESET()  (RCC->AHB1RSTR = 0x00U)
+#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) 
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_APB1_FORCE_RESET()     (RCC->APB1RSTR = 0xFFFFFFFFU)  
+#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_APB1_RELEASE_RESET()   (RCC->APB1RSTR = 0x00U) 
+#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_APB2_FORCE_RESET()     (RCC->APB2RSTR = 0xFFFFFFFFU)  
+#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_APB2_RELEASE_RESET()   (RCC->APB2RSTR = 0x00U)
+#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */ 
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+/**
+  * @}
+  */
+#endif /* STM32F401xC || STM32F401xE*/
+/*----------------------------------------------------------------------------*/
+
+/*-------------------------------- STM32F410xx -------------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable     
+  * @brief  Enables or disables the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_RNG_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_CRC_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+#define __HAL_RCC_RNG_CLK_DISABLE()     (RCC->AHB1ENR &= ~(RCC_AHB1ENR_RNGEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) != RESET)
+      
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_RNGEN)) == RESET)
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable  
+  * @brief  Enable or disable the High Speed APB (APB1) peripheral clock.
+  * @{
+  */
+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_RTCAPB_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U) 
+#define __HAL_RCC_DAC_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+                                        
+#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_RTCAPB_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))
+#define __HAL_RCC_LPTIM1_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
+#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
+#define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */  
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET) 
+#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 
+#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)  
+#define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 
+
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET) 
+#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 
+#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)  
+#define __HAL_RCC_DAC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)  
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable  
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @{
+  */  
+#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_EXTIT_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI5_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+#define __HAL_RCC_EXTIT_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)  
+#define __HAL_RCC_EXTIT_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)  
+  
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)  
+#define __HAL_RCC_EXTIT_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)  
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+#define __HAL_RCC_RNG_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_RNGRST))
+#define __HAL_RCC_CRC_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+#define __HAL_RCC_RNG_RELEASE_RESET()   (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_RNGRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()
+#define __HAL_RCC_AHB2_RELEASE_RESET()
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */ 
+#define __HAL_RCC_AHB3_FORCE_RESET()
+#define __HAL_RCC_AHB3_RELEASE_RESET()
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM6_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_LPTIM1_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_FMPI2C1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_DAC_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+
+#define __HAL_RCC_TIM6_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_LPTIM1_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
+#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_DAC_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_SPI5_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))                                        
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable  
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_RNGLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_RNGLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable                                         
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @{
+  */
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable                                         
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @{
+  */
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN))                                
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))                                        
+#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
+/**
+  * @}
+  */
+
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/*----------------------------------------------------------------------------*/
+
+/*-------------------------------- STM32F411xx -------------------------------*/
+#if defined(STM32F411xE)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */  
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) != RESET) 
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET) 
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEX_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
+                                              }while(0U)
+
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+/**
+  * @}
+  */  
+
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @{
+  */
+#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) 
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET) 
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) 
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET) 
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET) 
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @{
+  */
+#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_SPI5_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET)  
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)   
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)  
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET) 
+
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET)  
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)   
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)  
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)   
+/**
+  * @}
+  */  
+  
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */ 
+#define __HAL_RCC_GPIOD_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_CRC_FORCE_RESET()     (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) 
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */ 
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+
+#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+                                        
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))                                        
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable 
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @{
+  */
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable 
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @{
+  */
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+/**
+  * @}
+  */
+#endif /* STM32F411xE */
+/*----------------------------------------------------------------------------*/
+
+/*---------------------------------- STM32F446xx -----------------------------*/
+#if defined(STM32F446xx)
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_CRC_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                        UNUSED(tmpreg); \
+                                        } while(0U)
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_GPIOF_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_GPIOG_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
+#define __HAL_RCC_BKPSRAM_CLK_DISABLE()         (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
+#define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE()    (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
+#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET) 
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET) 
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET) 
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET) 
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)  
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET) 
+#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED()          ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)  
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN))!= RESET)  
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET) 
+
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET) 
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET) 
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET) 
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET) 
+#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)  
+#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET) 
+#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED()         ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)  
+#define __HAL_RCC_CCMDATARAMEN_IS_CLK_DISABLED()    ((RCC->AHB1ENR & (RCC_AHB1ENR_CCMDATARAMEN)) == RESET)  
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET) 
+/**
+  * @}
+  */  
+  
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_DCMI_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
+                                              }while(0U)
+                                        
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+
+#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
+
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()    ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET) 
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()   ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET) 
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @{
+  */
+#define __HAL_RCC_FMC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_FMC_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
+#define __HAL_RCC_QSPI_CLK_DISABLE()   (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_FMC_IS_CLK_ENABLED()   ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
+
+#define __HAL_RCC_FMC_IS_CLK_DISABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @{
+  */
+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART4_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART5_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CEC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_DAC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM2_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_SPI3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_I2C3_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
+#define __HAL_RCC_SPDIFRX_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
+#define __HAL_RCC_USART3_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#define __HAL_RCC_CEC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
+#define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)  
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET) 
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
+#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
+#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
+#define __HAL_RCC_CEC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)  
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET) 
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
+#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
+#define __HAL_RCC_CEC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED()     ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_ADC2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SAI2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SDIO_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_TIM10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_TIM8_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#define __HAL_RCC_ADC2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
+#define __HAL_RCC_ADC3_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
+#define __HAL_RCC_SAI1_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
+#define __HAL_RCC_SAI2_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET) 
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)  
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
+#define __HAL_RCC_ADC2_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET) 
+#define __HAL_RCC_ADC3_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET) 
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
+#define __HAL_RCC_SAI2_IS_CLK_ENABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
+
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET) 
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED()  ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)  
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
+#define __HAL_RCC_ADC2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET) 
+#define __HAL_RCC_ADC3_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET) 
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
+#define __HAL_RCC_SAI2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) 
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
+#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU) 
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_DCMI_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
+
+#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */ 
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
+
+#define __HAL_RCC_FMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+
+#define __HAL_RCC_FMC_RELEASE_RESET()    (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
+#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_SPDIFRX_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
+#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_FMPI2C1_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_CEC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
+#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
+                                          
+#define __HAL_RCC_TIM2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_SPI3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_I2C3_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
+#define __HAL_RCC_SPDIFRX_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
+#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#define __HAL_RCC_UART4_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#define __HAL_RCC_CEC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
+#define __HAL_RCC_DAC_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset 
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SAI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) 
+#define __HAL_RCC_SAI2_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
+#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
+
+#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
+#define __HAL_RCC_SAI2_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) 
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable 
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()  (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE()    (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE()   (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+
+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()   (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+
+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()   (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */ 
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()(RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
+
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()(RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
+/**
+  * @}
+  */
+
+#endif /* STM32F446xx */
+/*----------------------------------------------------------------------------*/
+
+/*-------STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx-------*/
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 
+/** @defgroup RCCEx_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 
+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 
+#define __HAL_RCC_GPIOE_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)                                        
+#define __HAL_RCC_GPIOF_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_GPIOG_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */                                       
+#define __HAL_RCC_CRC_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)                                        
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 
+#define __HAL_RCC_GPIOD_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) 
+#define __HAL_RCC_GPIOE_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
+#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOF_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
+#define __HAL_RCC_GPIOG_CLK_DISABLE()        (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
+#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */
+#define __HAL_RCC_CRC_CLK_DISABLE()          (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
+#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
+#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */
+#define __HAL_RCC_CRC_IS_CLK_ENABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) != RESET)
+
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
+#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()     ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
+#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */
+#define __HAL_RCC_CRC_IS_CLK_DISABLED()       ((RCC->AHB1ENR & (RCC_AHB1ENR_CRCEN)) == RESET)
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#if defined(STM32F423xx)
+#define __HAL_RCC_AES_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_AES_CLK_DISABLE()  (RCC->AHB2ENR &= ~(RCC_AHB2ENR_AESEN))
+#endif /* STM32F423xx */
+                                        
+#define __HAL_RCC_RNG_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_RNG_CLK_DISABLE()   (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
+                                     
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()  do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
+                                               __HAL_RCC_SYSCFG_CLK_ENABLE();\
+                                              }while(0U)
+                                        
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#if defined(STM32F423xx)
+#define __HAL_RCC_AES_IS_CLK_ENABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) != RESET)
+#define __HAL_RCC_AES_IS_CLK_DISABLED()       ((RCC->AHB2ENR & (RCC_AHB2ENR_AESEN)) == RESET)
+#endif /* STM32F423xx */
+                                        
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED()  ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
+#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
+          
+#define __HAL_RCC_RNG_IS_CLK_ENABLED()         ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)   
+#define __HAL_RCC_RNG_IS_CLK_DISABLED()        ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)   
+/**
+  * @}
+  */  
+
+/** @defgroup RCCEx_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
+  * @brief  Enables or disables the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @{
+  */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_FSMC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+
+#define __HAL_RCC_FSMC_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
+#define __HAL_RCC_QSPI_CLK_DISABLE()    (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_FSMC_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) != RESET) 
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()  ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET) 
+
+#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FSMCEN)) == RESET)
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @{
+  */
+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM12_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM13_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM14_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)                                        
+#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#endif /* STM32F413xx || STM32F423xx */  
+#define __HAL_RCC_RTCAPB_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCAPBEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_USART3_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART5_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#endif /* STM32F413xx || STM32F423xx */
+                                        
+#define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CAN1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_CAN2_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_TIM2_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_TIM4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_SPI3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_I2C3_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DAC_CLK_ENABLE()    do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART7_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART8_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#endif /* STM32F413xx || STM32F423xx */
+                                        
+#define __HAL_RCC_TIM2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
+#define __HAL_RCC_TIM3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
+#define __HAL_RCC_TIM4_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
+#define __HAL_RCC_TIM6_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
+#define __HAL_RCC_TIM7_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
+#define __HAL_RCC_TIM12_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
+#define __HAL_RCC_TIM13_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
+#define __HAL_RCC_TIM14_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN)) 
+#if defined(STM32F413xx) || defined(STM32F423xx)                 
+#define __HAL_RCC_LPTIM1_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
+#endif /* STM32F413xx || STM32F423xx */
+#define __HAL_RCC_RTCAPB_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCAPBEN))                                       
+#define __HAL_RCC_SPI3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
+#define __HAL_RCC_USART3_CLK_DISABLE()  (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
+#if defined(STM32F413xx) || defined(STM32F423xx)   
+#define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
+#define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_I2C3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
+#define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
+#define __HAL_RCC_CAN1_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
+#define __HAL_RCC_CAN2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))                                        
+#define __HAL_RCC_DAC_CLK_DISABLE()     (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
+#define __HAL_RCC_UART7_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
+#define __HAL_RCC_UART8_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+                                        
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) 
+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET) 
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET) 
+#endif /* STM32F413xx || STM32F423xx */                                            
+#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) != RESET)                                    
+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
+#define __HAL_RCC_USART3_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET) 
+#define __HAL_RCC_UART5_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET) 
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
+#define __HAL_RCC_FMPI2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) != RESET)
+#define __HAL_RCC_CAN1_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN))!= RESET)
+#define __HAL_RCC_CAN2_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_IS_CLK_ENABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
+#define __HAL_RCC_DAC_IS_CLK_ENABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET) 
+#define __HAL_RCC_UART7_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
+#define __HAL_RCC_UART8_IS_CLK_ENABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET) 
+#endif /* STM32F413xx || STM32F423xx */                                         
+
+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) 
+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
+#define __HAL_RCC_TIM12_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
+#define __HAL_RCC_TIM13_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
+#define __HAL_RCC_TIM14_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)                                          
+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET) 
+#endif /* STM32F413xx || STM32F423xx */                                         
+#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_RTCAPBEN)) == RESET)                                        
+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
+#define __HAL_RCC_USART3_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)                                           
+#define __HAL_RCC_UART4_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET) 
+#define __HAL_RCC_UART5_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET) 
+#endif /* STM32F413xx || STM32F423xx */                                          
+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
+#define __HAL_RCC_FMPI2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_FMPI2C1EN)) == RESET)
+#define __HAL_RCC_CAN1_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
+#define __HAL_RCC_CAN2_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)                                        
+#define __HAL_RCC_CAN3_IS_CLK_DISABLED()   ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
+#define __HAL_RCC_DAC_IS_CLK_DISABLED()    ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET) 
+#define __HAL_RCC_UART7_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
+#define __HAL_RCC_UART8_IS_CLK_DISABLED()  ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
+#endif /* STM32F413xx || STM32F423xx */                                         
+/**
+  * @}
+  */  
+/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
+  * @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_UART10_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART10EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)                                          
+#endif /* STM32F413xx || STM32F423xx */                                   
+#define __HAL_RCC_SDIO_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U) 
+#define __HAL_RCC_SPI4_CLK_ENABLE()     do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U)
+#define __HAL_RCC_EXTIT_CLK_ENABLE()  do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_EXTITEN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)                                        
+#define __HAL_RCC_TIM10_CLK_ENABLE()    do { \
+                                        __IO uint32_t tmpreg = 0x00U; \
+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        /* Delay after an RCC peripheral clock enabling */ \
+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
+                                        UNUSED(tmpreg); \
+                                      } while(0U) 
+#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)                                         
+#endif /* STM32F413xx || STM32F423xx */                                          
+#define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_CLK_ENABLE() do { \
+                                      __IO uint32_t tmpreg = 0x00U; \
+                                      SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
+                                      /* Delay after an RCC peripheral clock enabling */ \
+                                      tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM2EN);\
+                                      UNUSED(tmpreg); \
+                                      } while(0U)                                        
+#endif /* STM32F413xx || STM32F423xx */                                        
+ 
+#define __HAL_RCC_TIM8_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_UART9EN))
+#define __HAL_RCC_UART10_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_UART10EN))                                        
+#endif /* STM32F413xx || STM32F423xx */                                         
+#define __HAL_RCC_SDIO_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
+#define __HAL_RCC_SPI4_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
+#define __HAL_RCC_EXTIT_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_EXTITEN))
+#define __HAL_RCC_TIM10_CLK_DISABLE()   (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
+#define __HAL_RCC_SPI5_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))                                        
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_DFSDM1_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_CLK_DISABLE()  (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM2EN))                                      
+#endif /* STM32F413xx || STM32F423xx */                                         
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
+  * @brief  Get the enable or disable status of the APB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before
+  *         using it.
+  * @{
+  */
+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) != RESET)
+#define __HAL_RCC_UART10_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) != RESET)                                        
+#endif /* STM32F413xx || STM32F423xx */                                          
+#define __HAL_RCC_SDIO_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != RESET) 
+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
+#define __HAL_RCC_EXTIT_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) != RESET)
+#define __HAL_RCC_TIM10_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
+#define __HAL_RCC_SPI5_IS_CLK_ENABLED()      ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_IS_CLK_ENABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)                                    
+#endif /* STM32F413xx || STM32F423xx */                                         
+#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) != RESET)                                  
+#endif /* STM32F413xx || STM32F423xx */                                         
+
+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_UART9EN)) == RESET) 
+#define __HAL_RCC_UART10_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_UART10EN)) == RESET)                                         
+#endif /* STM32F413xx || STM32F423xx */                                         
+#define __HAL_RCC_SDIO_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == RESET) 
+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
+#define __HAL_RCC_EXTIT_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_EXTITEN)) == RESET)
+#define __HAL_RCC_TIM10_IS_CLK_DISABLED()    ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
+#define __HAL_RCC_SPI5_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_IS_CLK_DISABLED()     ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)                                       
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED()   ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM2EN)) == RESET)                                       
+#endif /* STM32F413xx || STM32F423xx */                                         
+/**
+  * @}
+  */
+  
+/** @defgroup RCCEx_AHB1_Force_Release_Reset AHB1 Force Release Reset 
+  * @brief  Force or release AHB1 peripheral reset.
+  * @{
+  */
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOD_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOE_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
+#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOF_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_FORCE_RESET()    (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
+#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */
+#define __HAL_RCC_CRC_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
+
+#if defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOD_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
+#endif /* STM32F412Rx || STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOE_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
+#endif /* STM32F412Vx || STM32F412Zx ||  STM32F413xx || STM32F423xx */
+#if defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_GPIOF_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
+#define __HAL_RCC_GPIOG_RELEASE_RESET()  (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
+#endif /*  STM32F412Zx || STM32F413xx || STM32F423xx */
+#define __HAL_RCC_CRC_RELEASE_RESET()    (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_Force_Release_Reset AHB2 Force Release Reset 
+  * @brief  Force or release AHB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_AHB2_FORCE_RESET()    (RCC->AHB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB2_RELEASE_RESET()  (RCC->AHB2RSTR = 0x00U)
+
+#if defined(STM32F423xx)
+#define __HAL_RCC_AES_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_AESRST))
+#define __HAL_RCC_AES_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_AESRST))                                        
+#endif /* STM32F423xx */ 
+                                        
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()   (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
+
+#define __HAL_RCC_RNG_FORCE_RESET()    (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
+#define __HAL_RCC_RNG_RELEASE_RESET()  (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_Force_Release_Reset AHB3 Force Release Reset 
+  * @brief  Force or release AHB3 peripheral reset.
+  * @{
+  */ 
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U) 
+
+#define __HAL_RCC_FSMC_FORCE_RESET()    (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
+#define __HAL_RCC_QSPI_FORCE_RESET()   (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
+
+#define __HAL_RCC_FSMC_RELEASE_RESET()    (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
+#define __HAL_RCC_QSPI_RELEASE_RESET()   (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ 
+#if defined(STM32F412Cx)
+#define __HAL_RCC_AHB3_FORCE_RESET()
+#define __HAL_RCC_AHB3_RELEASE_RESET()
+
+#define __HAL_RCC_FSMC_FORCE_RESET()
+#define __HAL_RCC_QSPI_FORCE_RESET()
+
+#define __HAL_RCC_FSMC_RELEASE_RESET()
+#define __HAL_RCC_QSPI_RELEASE_RESET()
+#endif /* STM32F412Cx */
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset 
+  * @brief  Force or release APB1 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) 
+#define __HAL_RCC_TIM4_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))                                        
+#define __HAL_RCC_TIM6_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST)) 
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) 
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_SPI3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))                                        
+#define __HAL_RCC_USART3_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))                                        
+#endif /* STM32F413xx || STM32F423xx */                                          
+#define __HAL_RCC_I2C3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))                                        
+#define __HAL_RCC_FMPI2C1_FORCE_RESET()  (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))
+#define __HAL_RCC_DAC_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_UART7_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
+#define __HAL_RCC_UART8_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))                                        
+#endif /* STM32F413xx || STM32F423xx */                                        
+
+#define __HAL_RCC_TIM2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
+#define __HAL_RCC_TIM3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
+#define __HAL_RCC_TIM4_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
+#define __HAL_RCC_TIM6_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
+#define __HAL_RCC_TIM7_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
+#define __HAL_RCC_TIM12_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
+#define __HAL_RCC_TIM13_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
+#define __HAL_RCC_TIM14_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST)) 
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_SPI3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
+#define __HAL_RCC_USART3_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
+#define __HAL_RCC_UART5_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_I2C3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))                                        
+#define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
+#define __HAL_RCC_CAN1_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
+#define __HAL_RCC_CAN2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
+#define __HAL_RCC_DAC_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
+#define __HAL_RCC_UART7_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
+#define __HAL_RCC_UART8_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))                                      
+#endif /* STM32F413xx || STM32F423xx */                                         
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
+  * @brief  Force or release APB2 peripheral reset.
+  * @{
+  */
+#define __HAL_RCC_TIM8_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_UART9RST))
+#define __HAL_RCC_UART10_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_UART10RST))                                        
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_SDIO_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))                                        
+#define __HAL_RCC_SPI5_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
+#endif /* STM32F413xx || STM32F423xx */                                         
+#define __HAL_RCC_DFSDM1_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_FORCE_RESET()   (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM2RST))
+#endif /* STM32F413xx || STM32F423xx */                                        
+
+#define __HAL_RCC_TIM8_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART9RST))
+#define __HAL_RCC_UART10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_UART10RST))                                        
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_SDIO_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
+#define __HAL_RCC_SPI4_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
+#define __HAL_RCC_TIM10_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
+#define __HAL_RCC_SPI5_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM2RST))
+#endif /* STM32F413xx || STM32F423xx */                                        
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()        (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+
+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()       (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
+#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
+#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE()     (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wake-up from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#if defined(STM32F423xx)
+#define __HAL_RCC_AES_CLK_SLEEP_ENABLE()      (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AESLPEN))                                        
+#define __HAL_RCC_AES_CLK_SLEEP_DISABLE()     (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_AESLPEN))
+#endif /* STM32F423xx */
+                                        
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()  (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()   (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
+
+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()   (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()  (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_AHB3_LowPower_Enable_Disable AHB3 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()   (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()  (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
+
+#define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE()   (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()  (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))                                        
+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCAPBLPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))                                       
+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))                                        
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))                                        
+#endif /* STM32F413xx || STM32F423xx */                                        
+
+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCAPBLPEN))
+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))                                        
+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                
+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))                                        
+#define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
+#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
+#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
+#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))                                        
+#endif /* STM32F413xx || STM32F423xx */                                     
+/**
+  * @}
+  */
+
+/** @defgroup RCCEx_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
+  * @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @{
+  */
+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_UART9LPEN))
+#define __HAL_RCC_UART10_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_UART10LPEN))                                        
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))  
+#define __HAL_RCC_EXTIT_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_EXTITLPEN)) 
+#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))                                        
+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE()  (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM2LPEN))
+#endif /* STM32F413xx || STM32F423xx */
+                                        
+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART9LPEN))
+#define __HAL_RCC_UART10_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_UART10LPEN))                                        
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
+#define __HAL_RCC_EXTIT_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_EXTITLPEN))
+#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))    
+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM2LPEN))
+#endif /* STM32F413xx || STM32F423xx */                                        
+/**
+  * @}
+  */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------------------- PLL Configuration --------------------------*/
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __RCC_PLLSource__ specifies the PLL entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 2 MHz to limit PLL jitter.
+  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
+  *         output frequency is between 100 and 432 MHz.
+  *   
+  * @param  __PLLP__ specifies the division factor for main system clock (SYSCLK)
+  *         This parameter must be a number in the range {2, 4, 6, or 8}.
+  *           
+  * @param  __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  * @note   If the USB OTG FS is used in your application, you have to set the
+  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+  *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+  *         correctly.
+  *     
+  * @param  __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/
+            STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
+  *      
+  */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__)  \
+                            (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__)                   | \
+                            ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos)                      | \
+                            ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos)          | \
+                            ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)                      | \
+                            ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))
+#else
+/** @brief  Macro to configure the main PLL clock source, multiplication and division factors.
+  * @note   This function must be used only when the main PLL is disabled.
+  * @param  __RCC_PLLSource__ specifies the PLL entry clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
+  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  
+  * @param  __PLLM__ specifies the division factor for PLL VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 2 MHz to limit PLL jitter.
+  * @param  __PLLN__ specifies the multiplication factor for PLL VCO output clock
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432
+  *         Except for STM32F411xE devices where Min_Data = 192.
+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
+  *         output frequency is between 100 and 432 MHz, Except for STM32F411xE devices
+  *         where frequency is between 192 and 432 MHz.
+  * @param  __PLLP__ specifies the division factor for main system clock (SYSCLK)
+  *         This parameter must be a number in the range {2, 4, 6, or 8}.
+  *           
+  * @param  __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  * @note   If the USB OTG FS is used in your application, you have to set the
+  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+  *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+  *         correctly.
+  *      
+  */
+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)     \
+                            (RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \
+                            ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos)                | \
+                            ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos)    | \
+                            ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
+ #endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+/*----------------------------------------------------------------------------*/
+                             
+/*----------------------------PLLI2S Configuration ---------------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+
+/** @brief Macros to enable or disable the PLLI2S. 
+  * @note  The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
+  */
+#define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
+#define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || 
+          STM32F412Rx || STM32F412Cx */
+#if defined(STM32F446xx)
+/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   PLLI2S clock source is common with the main PLL (configured in 
+  *         HAL_RCC_ClockConfig() API).
+  * @param  __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 1 MHz to limit PLLI2S jitter.
+  *
+  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  *
+  * @param  __PLLI2SP__ specifies division factor for SPDIFRX Clock.
+  *         This parameter must be a number in the range {2, 4, 6, or 8}.
+  * @note   the PLLI2SP parameter is only available with STM32F446xx Devices
+  *                 
+  * @param  __PLLI2SR__ specifies the division factor for I2S clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+  *         on the I2S clock frequency.
+  *   
+  * @param  __PLLI2SQ__ specifies the division factor for SAI clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__)    \
+                               (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                   |\
+                               ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)             |\
+                               ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\
+                               ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos)             |\
+                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
+#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+      defined(STM32F413xx) || defined(STM32F423xx)
+/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   PLLI2S clock source is common with the main PLL (configured in 
+  *         HAL_RCC_ClockConfig() API).
+  * @param  __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 1 MHz to limit PLLI2S jitter.
+  *
+  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  *
+  * @param  __PLLI2SR__ specifies the division factor for I2S clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+  *         on the I2S clock frequency.
+  *
+  * @param  __PLLI2SQ__ specifies the division factor for SAI clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__)    \
+                               (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                   |\
+                               ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)             |\
+                               ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos)             |\
+                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
+#else
+/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   PLLI2S clock source is common with the main PLL (configured in 
+  *         HAL_RCC_ClockConfig() API).
+  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  *
+  * @param  __PLLI2SR__ specifies the division factor for I2S clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+  *         on the I2S clock frequency.
+  *
+  */
+#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__)                                                    \
+                               (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)  |\
+                               ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
+#endif /* STM32F446xx */
+
+#if defined(STM32F411xE)
+/** @brief  Macro to configure the PLLI2S clock multiplication and division factors .
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   PLLI2S clock source is common with the main PLL (configured in 
+  *         HAL_RCC_ClockConfig() API).
+  * @param  __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
+  * @note   You have to set the PLLI2SM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 2 MHz to limit PLLI2S jitter.    
+  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
+  *         This parameter must be a number between Min_Data = 192 and Max_Data = 432.
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
+  * @param  __PLLI2SR__ specifies the division factor for I2S clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+  *         on the I2S clock frequency.
+  */
+#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__)                                                       |\
+                                                                                                  ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos)             |\
+                                                                                                  ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
+#endif /* STM32F411xE */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief  Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
+  * @note   This macro must be used only when the PLLI2S is disabled.
+  * @note   PLLI2S clock source is common with the main PLL (configured in 
+  *         HAL_RCC_ClockConfig() API)             
+  * @param  __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  * @param  __PLLI2SQ__ specifies the division factor for SAI1 clock.
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15. 
+  * @note   the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx 
+  *         Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
+  * @param  __PLLI2SR__ specifies the division factor for I2S clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+  *         on the I2S clock frequency.
+  */
+#define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6U)  |\
+                                                                                                 ((__PLLI2SQ__) << 24U) |\
+                                                                                                 ((__PLLI2SR__) << 28U))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */   
+/*----------------------------------------------------------------------------*/
+
+/*------------------------------ PLLSAI Configuration ------------------------*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief Macros to Enable or Disable the PLLISAI. 
+  * @note  The PLLSAI is only available with STM32F429x/439x Devices.
+  * @note  The PLLSAI is disabled by hardware when entering STOP and STANDBY modes. 
+  */
+#define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE)
+#define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE)
+
+#if defined(STM32F446xx)
+/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
+  *
+  * @param  __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 63.
+  * @note   You have to set the PLLSAIM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 1 MHz to limit PLLI2S jitter.
+  * @note   The PLLSAIM parameter is only used with STM32F446xx Devices
+  *             
+  * @param  __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  *
+  * @param  __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks.
+  *         This parameter must be a number in the range {2, 4, 6, or 8}.
+  * @note   the PLLSAIP parameter is only available with STM32F446xx Devices
+  *                 
+  * @param  __PLLSAIQ__ specifies the division factor for SAI clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  *           
+  * @param  __PLLSAIR__ specifies the division factor for LTDC clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices  
+  */
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__)     \
+                               (RCC->PLLSAICFGR = ((__PLLSAIM__)                                   | \
+                               ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos)             | \
+                               ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \
+                               ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))) 
+#endif /* STM32F446xx */
+                                 
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
+  *             
+  * @param  __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  *
+  * @param  __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks.
+  *         This parameter must be a number in the range {2, 4, 6, or 8}.
+  *                 
+  * @param  __PLLSAIQ__ specifies the division factor for SAI clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  *           
+  * @param  __PLLSAIR__ specifies the division factor for LTDC clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.  
+  */
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
+                               (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos)             |\
+                                                   ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\
+                                                   ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)             |\
+                                                   ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
+#endif /* STM32F469xx || STM32F479xx */                                 
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/** @brief  Macro to configure the PLLSAI clock multiplication and division factors.
+  *             
+  * @param  __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
+  *         This parameter must be a number between Min_Data = 50 and Max_Data = 432.
+  * @note   You have to set the PLLSAIN parameter correctly to ensure that the VCO 
+  *         output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
+  *
+  * @param  __PLLSAIQ__ specifies the division factor for SAI clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 15.
+  *           
+  * @param  __PLLSAIR__ specifies the division factor for LTDC clock
+  *         This parameter must be a number between Min_Data = 2 and Max_Data = 7.
+  * @note   the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices  
+  */
+#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__)                                        \
+                               (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos)  | \
+                               ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)                      | \
+                               ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------- PLLSAI/PLLI2S Dividers Configuration -------------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)
+/** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.
+  * @note   This function must be called before enabling the PLLI2S.
+  * @param  __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock.
+  *          This parameter must be a number between 1 and 32.
+  *          SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__ 
+  */
+#define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U))
+
+/** @brief  Macro to configure the SAI clock Divider coming from PLL.
+  * @param  __PLLDivR__ specifies the PLL division factor for SAI1 clock.
+  *          This parameter must be a number between 1 and 32.
+  *          SAI1 clock frequency = f(PLLR) / __PLLDivR__ 
+  */
+#define __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(__PLLDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, ((__PLLDivR__)-1U)<<8U))                                 
+#endif /* STM32F413xx || STM32F423xx */  
+                                 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)  || defined(STM32F446xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief  Macro to configure the SAI clock Divider coming from PLLI2S.
+  * @note   This function must be called before enabling the PLLI2S.
+  * @param  __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock.
+  *          This parameter must be a number between 1 and 32.
+  *          SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__ 
+  */
+#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1U))
+
+/** @brief  Macro to configure the SAI clock Divider coming from PLLSAI.
+  * @note   This function must be called before enabling the PLLSAI.
+  * @param  __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock .
+  *         This parameter must be a number between Min_Data = 1 and Max_Data = 32.
+  *         SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__  
+  */
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1U)<<8U))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief  Macro to configure the LTDC clock Divider coming from PLLSAI.
+  * 
+  * @note   The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
+  * @note   This function must be called before enabling the PLLSAI. 
+  * @param  __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock .
+  *          This parameter must be a number between Min_Data = 2 and Max_Data = 16.
+  *          LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__ 
+  */
+#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+/*----------------------------------------------------------------------------*/
+
+/*------------------------- Peripheral Clock selection -----------------------*/
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) ||\
+    defined(STM32F479xx)
+/** @brief  Macro to configure the I2S clock source (I2SCLK).
+  * @note   This function must be called before enabling the I2S APB clock.
+  * @param  __SOURCE__ specifies the I2S clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
+  *            @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
+  *                                       used as I2S clock source.
+  */
+#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
+
+
+/** @brief  Macro to get the I2S clock source (I2SCLK).
+  * @retval The clock source can be one of the following values:
+  *            @arg @ref RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
+  *            @arg @ref RCC_I2SCLKSOURCE_EXT External clock mapped on the I2S_CKIN pin
+  *                                        used as I2S clock source
+  */
+#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
+#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */
+                                 
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+                                 
+/** @brief  Macro to configure SAI1BlockA clock source selection.
+  * @note   The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.      
+  * @note   This function must be called before enabling PLLSAI, PLLI2S and  
+  *         the SAI clock.
+  * @param  __SOURCE__ specifies the SAI Block A clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 
+  *                                           as SAI1 Block A clock. 
+  *            @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 
+  *                                           as SAI1 Block A clock.
+  *            @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
+  *                                        used as SAI1 Block A clock.
+  */
+#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
+
+/** @brief  Macro to configure SAI1BlockB clock source selection.
+  * @note   The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
+  * @note   This function must be called before enabling PLLSAI, PLLI2S and  
+  *         the SAI clock.
+  * @param  __SOURCE__ specifies the SAI Block B clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used 
+  *                                           as SAI1 Block B clock. 
+  *            @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used 
+  *                                           as SAI1 Block B clock. 
+  *            @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
+  *                                        used as SAI1 Block B clock.
+  */
+#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F446xx)
+/** @brief  Macro to configure SAI1 clock source selection.
+  * @note   This configuration is only available with STM32F446xx Devices.
+  * @note   This function must be called before enabling PLL, PLLSAI, PLLI2S and  
+  *         the SAI clock.
+  * @param  __SOURCE__ specifies the SAI1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 
+  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
+  *            @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.  
+  *            @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+  */
+#define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
+
+/** @brief  Macro to Get SAI1 clock source selection.
+  * @note   This configuration is only available with STM32F446xx Devices.      
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock. 
+  *            @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
+  *            @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.  
+  *            @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
+  */
+#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
+
+/** @brief  Macro to configure SAI2 clock source selection.
+  * @note   This configuration is only available with STM32F446xx Devices.      
+  * @note   This function must be called before enabling PLL, PLLSAI, PLLI2S and  
+  *         the SAI clock.
+  * @param  __SOURCE__ specifies the SAI2 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 
+  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
+  *            @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.  
+  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
+  */
+#define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
+
+/** @brief  Macro to Get SAI2 clock source selection.
+  * @note   This configuration is only available with STM32F446xx Devices.      
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock. 
+  *            @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
+  *            @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.  
+  *            @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
+  */
+#define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
+
+/** @brief  Macro to configure I2S APB1 clock source selection.
+  * @note   This function must be called before enabling PLL, PLLI2S and the I2S clock.
+  * @param  __SOURCE__ specifies the I2S APB1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 
+  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.  
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
+
+/** @brief  Macro to Get I2S APB1 clock source selection.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 
+  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB1 clock.  
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
+
+/** @brief  Macro to configure I2S APB2 clock source selection.
+  * @note   This function must be called before enabling PLL, PLLI2S and the I2S clock.
+  * @param  __SOURCE__ specifies the SAI Block A clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 
+  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.  
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
+
+/** @brief  Macro to Get I2S APB2 clock source selection.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock. 
+  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as I2S APB2 clock.  
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
+
+/** @brief  Macro to configure the CEC clock.
+  * @param  __SOURCE__ specifies the CEC clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+  */
+#define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the CEC clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
+  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
+  */
+#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
+
+/** @brief  Macro to configure the FMPI2C1 clock.
+  * @param  __SOURCE__ specifies the FMPI2C1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+  */
+#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the FMPI2C1 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+  */
+#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
+
+/** @brief  Macro to configure the CLK48 clock.
+  * @param  __SOURCE__ specifies the CLK48 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
+  */
+#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the CLK48 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
+  */
+#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
+
+/** @brief  Macro to configure the SDIO clock.
+  * @param  __SOURCE__ specifies the SDIO clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
+  */
+#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the SDIO clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
+  */
+#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
+
+/** @brief  Macro to configure the SPDIFRX clock.
+  * @param  __SOURCE__ specifies the SPDIFRX clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.  
+  *            @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 
+  */
+#define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the SPDIFRX clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.  
+  *            @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock. 
+  */
+#define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
+#endif /* STM32F446xx */
+      
+#if defined(STM32F469xx) || defined(STM32F479xx)
+      
+/** @brief  Macro to configure the CLK48 clock.
+  * @param  __SOURCE__ specifies the CLK48 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
+  */
+#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the CLK48 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock. 
+  */
+#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
+
+/** @brief  Macro to configure the SDIO clock.
+  * @param  __SOURCE__ specifies the SDIO clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
+  */
+#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the SDIO clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
+  */
+#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))  
+      
+/** @brief  Macro to configure the DSI clock.
+  * @param  __SOURCE__ specifies the DSI clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 
+  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 
+  */
+#define __HAL_RCC_DSI_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the DSI clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock. 
+  *            @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock. 
+  */
+#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL))       
+      
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+    defined(STM32F413xx) || defined(STM32F423xx)
+ /** @brief  Macro to configure the DFSDM1 clock.
+  * @param  __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 
+  *            @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock.
+  * @retval None
+  */
+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__)  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM1_CLKSOURCE__))
+
+/** @brief  Macro to get the DFSDM1 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 
+  *            @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernel clock.
+  */
+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
+
+/** @brief  Macro to configure DFSDM1 Audio clock source selection.
+  * @note   This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
+            STM32F413xx/STM32F423xx Devices.
+  * @param  __SOURCE__ specifies the DFSDM1 Audio clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
+  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
+  */
+#define __HAL_RCC_DFSDM1AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL, (__SOURCE__)))
+
+/** @brief  Macro to Get DFSDM1 Audio clock source selection.
+  * @note   This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
+            STM32F413xx/STM32F423xx Devices.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
+  *            @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
+  */
+#define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1ASEL))
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+ /** @brief  Macro to configure the DFSDM2 clock.
+  * @param  __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 
+  *            @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock.
+  * @retval None
+  */
+#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2_CLKSOURCE__)  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, (__DFSDM2_CLKSOURCE__))
+
+/** @brief  Macro to get the DFSDM2 clock source.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock. 
+  *            @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernel clock.
+  */
+#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL)))
+
+/** @brief  Macro to configure DFSDM1 Audio clock source selection.
+  * @note   This configuration is only available with STM32F413xx/STM32F423xx Devices.
+  * @param  __SOURCE__ specifies the DFSDM2 Audio clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
+  *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
+  */
+#define __HAL_RCC_DFSDM2AUDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL, (__SOURCE__)))
+
+/** @brief  Macro to Get DFSDM2 Audio clock source selection.
+  * @note   This configuration is only available with STM32F413xx/STM32F423xx Devices.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
+  *            @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
+  */
+#define __HAL_RCC_GET_DFSDM2AUDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM2ASEL))
+      
+/** @brief  Macro to configure SAI1BlockA clock source selection.
+  * @note   The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.      
+  * @note   This function must be called before enabling PLLSAI, PLLI2S and  
+  *         the SAI clock.
+  * @param  __SOURCE__ specifies the SAI Block A clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
+  *            @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
+  *            @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
+  *            @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
+      
+/** @brief  Macro to Get SAI1 BlockA clock source selection.
+  * @note   This configuration is only available with STM32F413xx/STM32F423xx Devices.      
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
+  *            @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
+  *            @arg RCC_SAIACLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
+  *            @arg RCC_SAIACLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_GET_SAI_BLOCKA_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC))
+
+/** @brief  Macro to configure SAI1 BlockB clock source selection.
+  * @note   The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
+  * @note   This function must be called before enabling PLLSAI, PLLI2S and  
+  *         the SAI clock.
+  * @param  __SOURCE__ specifies the SAI Block B clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
+  *            @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
+  *            @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
+  *            @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
+      
+/** @brief  Macro to Get SAI1 BlockB clock source selection.
+  * @note   This configuration is only available with STM32F413xx/STM32F423xx Devices.      
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
+  *            @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
+  *            @arg RCC_SAIBCLKSOURCE_PLLR: PLL_R clock divided (R1) used as SAI1 Block A clock.
+  *            @arg RCC_SAIBCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC))
+
+/** @brief  Macro to configure the LPTIM1 clock.
+  * @param  __SOURCE__ specifies the LPTIM1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  */
+#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the LPTIM1 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  */
+#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))      
+#endif /* STM32F413xx || STM32F423xx */
+      
+/** @brief  Macro to configure I2S APB1 clock source selection.
+  * @param  __SOURCE__ specifies the I2S APB1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
+  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
+
+/** @brief  Macro to Get I2S APB1 clock source selection.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
+  *            @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
+  *            @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
+
+/** @brief  Macro to configure I2S APB2 clock source selection.
+  * @param  __SOURCE__ specifies the I2S APB2 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
+  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
+
+/** @brief  Macro to Get I2S APB2 clock source selection.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
+  *            @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR.
+  *            @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  */
+#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
+
+/** @brief  Macro to configure the PLL I2S clock source (PLLI2SCLK).
+  * @note   This macro must be called before enabling the I2S APB clock.
+  * @param  __SOURCE__ specifies the I2S clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
+  *            @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
+  *                                       used as I2S clock source.
+  */
+#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
+      
+/** @brief  Macro to configure the FMPI2C1 clock.
+  * @param  __SOURCE__ specifies the FMPI2C1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+  */
+#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the FMPI2C1 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+  */
+#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
+
+/** @brief  Macro to configure the CLK48 clock.
+  * @param  __SOURCE__ specifies the CLK48 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.
+  */
+#define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the CLK48 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock. 
+  *            @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock
+  */
+#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
+
+/** @brief  Macro to configure the SDIO clock.
+  * @param  __SOURCE__ specifies the SDIO clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
+  */
+#define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the SDIO clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock. 
+  *            @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock. 
+  */
+#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
+
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @brief  Macro to configure I2S clock source selection.
+  * @param  __SOURCE__ specifies the I2S clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
+  *            @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+  *            @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
+  */
+#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC, (__SOURCE__)))
+
+/** @brief  Macro to Get I2S clock source selection.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
+  *            @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
+  *            @arg RCC_I2SAPBCLKSOURCE_PLLSRC: HSI/HSE depends on PLLSRC.
+  */
+#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
+
+/** @brief  Macro to configure the FMPI2C1 clock.
+  * @param  __SOURCE__ specifies the FMPI2C1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+  */
+#define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the FMPI2C1 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
+  *            @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as FMPI2C1 clock
+  */
+#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
+
+/** @brief  Macro to configure the LPTIM1 clock.
+  * @param  __SOURCE__ specifies the LPTIM1 clock source.
+  *         This parameter can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  */
+#define __HAL_RCC_LPTIM1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__SOURCE__)))
+
+/** @brief  Macro to Get the LPTIM1 clock.
+  * @retval The clock source can be one of the following values:
+  *            @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
+  */
+#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+      
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/** @brief  Macro to configure the Timers clocks prescalers 
+  * @note   This feature is only available with STM32F429x/439x Devices.  
+  * @param  __PRESC__  specifies the Timers clocks prescalers selection
+  *         This parameter can be one of the following values:
+  *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is 
+  *                 equal to HPRE if PPREx is corresponding to division by 1 or 2, 
+  *                 else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to 
+  *                 division by 4 or more.       
+  *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is 
+  *                 equal to HPRE if PPREx is corresponding to division by 1, 2 or 4, 
+  *                 else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding 
+  *                 to division by 8 or more.
+  */     
+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE ||\
+          STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx  || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx ||\
+          STM32F423xx */
+
+/*----------------------------------------------------------------------------*/
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/** @brief Enable PLLSAI_RDY interrupt.
+  */
+#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Disable PLLSAI_RDY interrupt.
+  */
+#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
+
+/** @brief Clear the PLLSAI RDY interrupt pending bits.
+  */
+#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
+
+/** @brief Check the PLLSAI RDY interrupt has occurred or not.
+  * @retval The new state (TRUE or FALSE).
+  */
+#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
+
+/** @brief  Check PLLSAI RDY flag is set or not.
+  * @retval The new state (TRUE or FALSE).
+  */
+#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/** @brief  Macros to enable or disable the RCC MCO1 feature.
+  */
+#define __HAL_RCC_MCO1_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = ENABLE)
+#define __HAL_RCC_MCO1_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO1EN_BB = DISABLE)
+
+/** @brief  Macros to enable or disable the RCC MCO2 feature.
+  */
+#define __HAL_RCC_MCO2_ENABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = ENABLE)
+#define __HAL_RCC_MCO2_DISABLE() (*(__IO uint32_t *) RCC_CFGR_MCO2EN_BB = DISABLE)
+
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RCCEx_Exported_Functions
+  *  @{
+  */
+
+/** @addtogroup RCCEx_Exported_Functions_Group1
+  *  @{
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
+
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#if defined(RCC_PLLI2S_SUPPORT)
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
+#endif /* RCC_PLLI2S_SUPPORT */
+#if defined(RCC_PLLSAI_SUPPORT)
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef  *PLLSAIInit);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
+#endif /* RCC_PLLSAI_SUPPORT */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Constants RCCEx Private Constants
+  * @{
+  */
+
+/** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
+  * @brief RCC registers bit address in the alias region
+  * @{
+  */
+/* --- CR Register ---*/  
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/* Alias word address of PLLSAION bit */
+#define RCC_PLLSAION_BIT_NUMBER       0x1CU
+#define RCC_CR_PLLSAION_BB            (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLSAION_BIT_NUMBER * 4U))
+
+#define PLLSAI_TIMEOUT_VALUE          2U  /* Timeout value fixed to 2 ms  */
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Alias word address of PLLI2SON bit */
+#define RCC_PLLI2SON_BIT_NUMBER    0x1AU
+#define RCC_CR_PLLI2SON_BB         (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLI2SON_BIT_NUMBER * 4U))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
+          STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/* --- DCKCFGR Register ---*/
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F401xC) ||\
+    defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/* Alias word address of TIMPRE bit */
+#define RCC_DCKCFGR_OFFSET            (RCC_OFFSET + 0x8CU)
+#define RCC_TIMPRE_BIT_NUMBER          0x18U
+#define RCC_DCKCFGR_TIMPRE_BB         (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32U) + (RCC_TIMPRE_BIT_NUMBER * 4U))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F410xx || STM32F401xC ||\
+          STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+          STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/* --- CFGR Register ---*/
+#define RCC_CFGR_OFFSET            (RCC_OFFSET + 0x08U)
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+    defined(STM32F469xx) || defined(STM32F479xx)
+/* Alias word address of I2SSRC bit */
+#define RCC_I2SSRC_BIT_NUMBER      0x17U
+#define RCC_CFGR_I2SSRC_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_I2SSRC_BIT_NUMBER * 4U))
+      
+#define PLLI2S_TIMEOUT_VALUE       2U  /* Timeout value fixed to 2 ms  */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx */
+      
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+    defined(STM32F413xx) || defined(STM32F423xx)
+/* --- PLLI2SCFGR Register ---*/
+#define RCC_PLLI2SCFGR_OFFSET         (RCC_OFFSET + 0x84U)
+/* Alias word address of PLLI2SSRC bit */
+#define RCC_PLLI2SSRC_BIT_NUMBER      0x16U
+#define RCC_PLLI2SCFGR_PLLI2SSRC_BB         (PERIPH_BB_BASE + (RCC_PLLI2SCFGR_OFFSET * 32U) + (RCC_PLLI2SSRC_BIT_NUMBER * 4U))
+      
+#define PLLI2S_TIMEOUT_VALUE          2U  /* Timeout value fixed to 2 ms */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx | STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/* Alias word address of MCO1EN bit */
+#define RCC_MCO1EN_BIT_NUMBER      0x8U
+#define RCC_CFGR_MCO1EN_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO1EN_BIT_NUMBER * 4U))
+
+/* Alias word address of MCO2EN bit */
+#define RCC_MCO2EN_BIT_NUMBER      0x9U
+#define RCC_CFGR_MCO2EN_BB         (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32U) + (RCC_MCO2EN_BIT_NUMBER * 4U))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#define PLL_TIMEOUT_VALUE          2U  /* 2 ms */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
+  * @{
+  */
+/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
+  * @{
+  */
+#define IS_RCC_PLLN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50U <= (VALUE)) && ((VALUE) <= 432U))
+      
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000007FU))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) 
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000007U))
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) 
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000000FU))
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x0000001FU))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F446xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00000FFFU))
+#endif /* STM32F446xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000001FFU))
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x000003FFU))
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+      
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_RCC_PERIPHCLOCK(SELECTION) ((1U <= (SELECTION)) && ((SELECTION) <= 0x00007FFFU))
+#endif /* STM32F413xx || STM32F423xx */
+      
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_RCC_PLLI2SQ_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 15U))
+
+#define IS_RCC_PLLSAIN_VALUE(VALUE)     ((50U <= (VALUE)) && ((VALUE) <= 432U))
+
+#define IS_RCC_PLLSAIQ_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 15U))
+
+#define IS_RCC_PLLSAIR_VALUE(VALUE)     ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
+
+#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
+
+#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2)  ||\
+                                         ((VALUE) == RCC_PLLSAIDIVR_4)  ||\
+                                         ((VALUE) == RCC_PLLSAIDIVR_8)  ||\
+                                         ((VALUE) == RCC_PLLSAIDIVR_16))
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_RCC_PLLI2SM_VALUE(VALUE)   ((2U <= (VALUE)) && ((VALUE) <= 63U))
+ 
+#define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
+                                         ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
+#endif /* STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx  */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#define IS_RCC_LSE_MODE(MODE)           (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
+                                         ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
+
+#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1)    ||\
+                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
+                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
+
+#define IS_RCC_LPTIM1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\
+                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) ||\
+                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) ||\
+                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
+
+#define IS_RCC_I2SAPBCLKSOURCE(SOURCE)      (((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLR)    ||\
+                                             ((SOURCE) == RCC_I2SAPBCLKSOURCE_EXT)    ||\
+                                             ((SOURCE) == RCC_I2SAPBCLKSOURCE_PLLSRC))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F446xx)
+#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
+  
+#define IS_RCC_PLLI2SP_VALUE(VALUE)       (((VALUE) == RCC_PLLI2SP_DIV2) ||\
+                                           ((VALUE) == RCC_PLLI2SP_DIV4) ||\
+                                           ((VALUE) == RCC_PLLI2SP_DIV6) ||\
+                                           ((VALUE) == RCC_PLLI2SP_DIV8))
+
+#define IS_RCC_PLLSAIM_VALUE(VALUE)       ((VALUE) <= 63U)
+  
+#define IS_RCC_PLLSAIP_VALUE(VALUE)       (((VALUE) == RCC_PLLSAIP_DIV2) ||\
+                                           ((VALUE) == RCC_PLLSAIP_DIV4) ||\
+                                           ((VALUE) == RCC_PLLSAIP_DIV6) ||\
+                                           ((VALUE) == RCC_PLLSAIP_DIV8))
+
+#define IS_RCC_SAI1CLKSOURCE(SOURCE)      (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\
+                                           ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\
+                                           ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR)   ||\
+                                           ((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
+
+#define IS_RCC_SAI2CLKSOURCE(SOURCE)      (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\
+                                           ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\
+                                           ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR)   ||\
+                                           ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
+ 
+#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
+                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT)    ||\
+                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR)   ||\
+                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
+                                              
+ #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
+                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT)    ||\
+                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR)   ||\
+                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
+
+#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1)    ||\
+                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
+                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
+
+#define IS_RCC_CECCLKSOURCE(SOURCE)       (((SOURCE) == RCC_CECCLKSOURCE_HSI)   ||\
+                                           ((SOURCE) == RCC_CECCLKSOURCE_LSE))
+
+#define IS_RCC_CLK48CLKSOURCE(SOURCE)      (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
+                                            ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
+
+#define IS_RCC_SDIOCLKSOURCE(SOURCE)      (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
+                                           ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
+
+#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)   (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\
+                                           ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))  
+#endif /* STM32F446xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+#define IS_RCC_PLLR_VALUE(VALUE)            ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#define IS_RCC_PLLSAIP_VALUE(VALUE)         (((VALUE) == RCC_PLLSAIP_DIV2) ||\
+                                             ((VALUE) == RCC_PLLSAIP_DIV4) ||\
+                                             ((VALUE) == RCC_PLLSAIP_DIV6) ||\
+                                             ((VALUE) == RCC_PLLSAIP_DIV8))
+ 
+#define IS_RCC_CLK48CLKSOURCE(SOURCE)        (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
+                                              ((SOURCE) == RCC_CLK48CLKSOURCE_PLLSAIP))
+
+#define IS_RCC_SDIOCLKSOURCE(SOURCE)        (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
+                                             ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
+
+#define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR)  ||\
+                                             ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
+
+#define IS_RCC_LSE_MODE(MODE)               (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
+                                             ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+    defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 15U))
+    
+#define IS_RCC_PLLR_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 7U))
+
+#define IS_RCC_PLLI2SCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLI2SCLKSOURCE_PLLSRC) || \
+                                            ((__SOURCE__) == RCC_PLLI2SCLKSOURCE_EXT))
+ 
+#define IS_RCC_I2SAPB1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
+                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT)    ||\
+                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR)   ||\
+                                           ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
+                                              
+ #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
+                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT)    ||\
+                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR)   ||\
+                                           ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
+
+#define IS_RCC_FMPI2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_FMPI2C1CLKSOURCE_PCLK1)    ||\
+                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
+                                           ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
+
+#define IS_RCC_CLK48CLKSOURCE(SOURCE)      (((SOURCE) == RCC_CLK48CLKSOURCE_PLLQ) ||\
+                                            ((SOURCE) == RCC_CLK48CLKSOURCE_PLLI2SQ))
+
+#define IS_RCC_SDIOCLKSOURCE(SOURCE)      (((SOURCE) == RCC_SDIOCLKSOURCE_CLK48) ||\
+                                           ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
+
+#define IS_RCC_DFSDM1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1CLKSOURCE_PCLK2) || \
+                                            ((__SOURCE__) == RCC_DFSDM1CLKSOURCE_SYSCLK))
+
+#define IS_RCC_DFSDM1AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S1) || \
+                                                 ((__SOURCE__) == RCC_DFSDM1AUDIOCLKSOURCE_I2S2))
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define IS_RCC_DFSDM2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2CLKSOURCE_PCLK2) || \
+                                            ((__SOURCE__) == RCC_DFSDM2CLKSOURCE_SYSCLK))
+
+#define IS_RCC_DFSDM2AUDIOCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S1) || \
+                                                 ((__SOURCE__) == RCC_DFSDM2AUDIOCLKSOURCE_I2S2))
+
+#define IS_RCC_LPTIM1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK1) ||\
+                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI)  ||\
+                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)  ||\
+                                          ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
+
+#define IS_RCC_SAIACLKSOURCE(SOURCE)     (((SOURCE) == RCC_SAIACLKSOURCE_PLLI2SR) ||\
+                                          ((SOURCE) == RCC_SAIACLKSOURCE_EXT)     ||\
+                                          ((SOURCE) == RCC_SAIACLKSOURCE_PLLR)    ||\
+                                          ((SOURCE) == RCC_SAIACLKSOURCE_PLLSRC))
+
+#define IS_RCC_SAIBCLKSOURCE(SOURCE)     (((SOURCE) == RCC_SAIBCLKSOURCE_PLLI2SR) ||\
+                                          ((SOURCE) == RCC_SAIBCLKSOURCE_EXT)     ||\
+                                          ((SOURCE) == RCC_SAIBCLKSOURCE_PLLR)    ||\
+                                          ((SOURCE) == RCC_SAIBCLKSOURCE_PLLSRC))
+
+#define IS_RCC_PLL_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
+
+#define IS_RCC_PLLI2S_DIVR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 32U))
+
+#endif /* STM32F413xx || STM32F423xx */
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
+    defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
+    defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
+      
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
+                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
+          STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || \
+          STM32F412Rx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)      
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_I2SCLK)|| \
+                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)    || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_RCC_EX_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
index c5f5d3e..543ebcc 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h
@@ -1,884 +1,884 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_uart.h
-  * @author  MCD Application Team
-  * @brief   Header file of UART HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_UART_H
-#define __STM32F4xx_HAL_UART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup UART
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Types UART Exported Types
-  * @{
-  */
-
-/**
-  * @brief UART Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                           - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
-                                           Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref UART_Word_Length */
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref UART_Stop_Bits */
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref UART_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
-
-  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref UART_Mode */
-
-  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled or disabled.
-                                           This parameter can be a value of @ref UART_Hardware_Flow_Control */
-
-  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
-                                           This parameter can be a value of @ref UART_Over_Sampling */
-} UART_InitTypeDef;
-
-/**
-  * @brief HAL UART State structures definition
-  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.
-  *        - gState contains UART state information related to global Handle management
-  *          and also information related to Tx operations.
-  *          gState value coding follow below described bitmap :
-  *          b7-b6  Error information
-  *             00 : No Error
-  *             01 : (Not Used)
-  *             10 : Timeout
-  *             11 : Error
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral initialized. HAL UART Init function already called)
-  *          b4-b3  (not used)
-  *             xx : Should be set to 00
-  *          b2     Intrinsic process state
-  *             0  : Ready
-  *             1  : Busy (Peripheral busy with some configuration or internal operations)
-  *          b1     (not used)
-  *             x  : Should be set to 0
-  *          b0     Tx state
-  *             0  : Ready (no Tx operation ongoing)
-  *             1  : Busy (Tx operation ongoing)
-  *        - RxState contains information related to Rx operations.
-  *          RxState value coding follow below described bitmap :
-  *          b7-b6  (not used)
-  *             xx : Should be set to 00
-  *          b5     Peripheral initialization status
-  *             0  : Reset (Peripheral not initialized)
-  *             1  : Init done (Peripheral initialized)
-  *          b4-b2  (not used)
-  *            xxx : Should be set to 000
-  *          b1     Rx state
-  *             0  : Ready (no Rx operation ongoing)
-  *             1  : Busy (Rx operation ongoing)
-  *          b0     (not used)
-  *             x  : Should be set to 0.
-  */
-typedef enum
-{
-  HAL_UART_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
-                                                   Value is allowed for gState and RxState */
-  HAL_UART_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
-                                                   Value is allowed for gState and RxState */
-  HAL_UART_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
-                                                   Value is allowed for gState only */
-  HAL_UART_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
-                                                   Value is allowed for gState only */
-  HAL_UART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
-                                                   Value is allowed for RxState only */
-  HAL_UART_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
-                                                   Not to be used for neither gState nor RxState.
-                                                   Value is result of combination (Or) between gState and RxState values */
-  HAL_UART_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
-                                                   Value is allowed for gState only */
-  HAL_UART_STATE_ERROR             = 0xE0U     /*!< Error
-                                                   Value is allowed for gState only */
-} HAL_UART_StateTypeDef;
-
-/**
-  * @brief HAL UART Reception type definition
-  * @note  HAL UART Reception type value aims to identify which type of Reception is ongoing.
-  *        It is expected to admit following values :
-  *           HAL_UART_RECEPTION_STANDARD         = 0x00U,
-  *           HAL_UART_RECEPTION_TOIDLE           = 0x01U,
-  */
-typedef uint32_t HAL_UART_RxTypeTypeDef;
-
-/**
-  * @brief  UART handle Structure definition
-  */
-typedef struct __UART_HandleTypeDef
-{
-  USART_TypeDef                 *Instance;        /*!< UART registers base address        */
-
-  UART_InitTypeDef              Init;             /*!< UART communication parameters      */
-
-  const uint8_t                 *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
-
-  uint16_t                      TxXferSize;       /*!< UART Tx Transfer size              */
-
-  __IO uint16_t                 TxXferCount;      /*!< UART Tx Transfer Counter           */
-
-  uint8_t                       *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
-
-  uint16_t                      RxXferSize;       /*!< UART Rx Transfer size              */
-
-  __IO uint16_t                 RxXferCount;      /*!< UART Rx Transfer Counter           */
-
-  __IO HAL_UART_RxTypeTypeDef ReceptionType;      /*!< Type of ongoing reception          */
-
-  DMA_HandleTypeDef             *hdmatx;          /*!< UART Tx DMA Handle parameters      */
-
-  DMA_HandleTypeDef             *hdmarx;          /*!< UART Rx DMA Handle parameters      */
-
-  HAL_LockTypeDef               Lock;             /*!< Locking object                     */
-
-  __IO HAL_UART_StateTypeDef    gState;           /*!< UART state information related to global Handle management
-                                                       and also related to Tx operations.
-                                                       This parameter can be a value of @ref HAL_UART_StateTypeDef */
-
-  __IO HAL_UART_StateTypeDef    RxState;          /*!< UART state information related to Rx operations.
-                                                       This parameter can be a value of @ref HAL_UART_StateTypeDef */
-
-  __IO uint32_t                 ErrorCode;        /*!< UART Error code                    */
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
-  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
-  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
-  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
-  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
-  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
-  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
-  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
-  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
-  void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback     */
-
-  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
-  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
-#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-} UART_HandleTypeDef;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  HAL UART Callback ID enumeration definition
-  */
-typedef enum
-{
-  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
-  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
-  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
-  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
-  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
-  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
-  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
-  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
-  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
-
-  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
-  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
-
-} HAL_UART_CallbackIDTypeDef;
-
-/**
-  * @brief  HAL UART Callback pointer definition
-  */
-typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer to an UART callback function */
-typedef  void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos);   /*!< pointer to a UART Rx Event specific callback function */
-
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported Constants
-  * @{
-  */
-
-/** @defgroup UART_Error_Code UART Error Code
-  * @{
-  */
-#define HAL_UART_ERROR_NONE              0x00000000U   /*!< No error            */
-#define HAL_UART_ERROR_PE                0x00000001U   /*!< Parity error        */
-#define HAL_UART_ERROR_NE                0x00000002U   /*!< Noise error         */
-#define HAL_UART_ERROR_FE                0x00000004U   /*!< Frame error         */
-#define HAL_UART_ERROR_ORE               0x00000008U   /*!< Overrun error       */
-#define HAL_UART_ERROR_DMA               0x00000010U   /*!< DMA transfer error  */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-#define  HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U   /*!< Invalid Callback error  */
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-/**
-  * @}
-  */
-
-/** @defgroup UART_Word_Length UART Word Length
-  * @{
-  */
-#define UART_WORDLENGTH_8B                  0x00000000U
-#define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Stop_Bits UART Number of Stop Bits
-  * @{
-  */
-#define UART_STOPBITS_1                     0x00000000U
-#define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Parity UART Parity
-  * @{
-  */
-#define UART_PARITY_NONE                    0x00000000U
-#define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
-#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
-/**
-  * @}
-  */
-
-/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
-  * @{
-  */
-#define UART_HWCONTROL_NONE                  0x00000000U
-#define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)
-#define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)
-#define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-/**
-  * @}
-  */
-
-/** @defgroup UART_Mode UART Transfer Mode
-  * @{
-  */
-#define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)
-#define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)
-#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
-/**
-  * @}
-  */
-
-/** @defgroup UART_State UART State
-  * @{
-  */
-#define UART_STATE_DISABLE                  0x00000000U
-#define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Over_Sampling UART Over Sampling
-  * @{
-  */
-#define UART_OVERSAMPLING_16                    0x00000000U
-#define UART_OVERSAMPLING_8                     ((uint32_t)USART_CR1_OVER8)
-/**
-  * @}
-  */
-
-/** @defgroup UART_LIN_Break_Detection_Length  UART LIN Break Detection Length
-  * @{
-  */
-#define UART_LINBREAKDETECTLENGTH_10B      0x00000000U
-#define UART_LINBREAKDETECTLENGTH_11B      ((uint32_t)USART_CR2_LBDL)
-/**
-  * @}
-  */
-
-/** @defgroup UART_WakeUp_functions  UART Wakeup Functions
-  * @{
-  */
-#define UART_WAKEUPMETHOD_IDLELINE                0x00000000U
-#define UART_WAKEUPMETHOD_ADDRESSMARK             ((uint32_t)USART_CR1_WAKE)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Flags   UART FLags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the SR register
-  * @{
-  */
-#define UART_FLAG_CTS                       ((uint32_t)USART_SR_CTS)
-#define UART_FLAG_LBD                       ((uint32_t)USART_SR_LBD)
-#define UART_FLAG_TXE                       ((uint32_t)USART_SR_TXE)
-#define UART_FLAG_TC                        ((uint32_t)USART_SR_TC)
-#define UART_FLAG_RXNE                      ((uint32_t)USART_SR_RXNE)
-#define UART_FLAG_IDLE                      ((uint32_t)USART_SR_IDLE)
-#define UART_FLAG_ORE                       ((uint32_t)USART_SR_ORE)
-#define UART_FLAG_NE                        ((uint32_t)USART_SR_NE)
-#define UART_FLAG_FE                        ((uint32_t)USART_SR_FE)
-#define UART_FLAG_PE                        ((uint32_t)USART_SR_PE)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Interrupt_definition  UART Interrupt Definitions
-  *        Elements values convention: 0xY000XXXX
-  *           - XXXX  : Interrupt mask (16 bits) in the Y register
-  *           - Y  : Interrupt source register (2bits)
-  *                   - 0001: CR1 register
-  *                   - 0010: CR2 register
-  *                   - 0011: CR3 register
-  * @{
-  */
-
-#define UART_IT_PE                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
-#define UART_IT_TXE                      ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
-#define UART_IT_TC                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
-#define UART_IT_RXNE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
-#define UART_IT_IDLE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
-
-#define UART_IT_LBD                      ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
-
-#define UART_IT_CTS                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
-#define UART_IT_ERR                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
-/**
-  * @}
-  */
-
-/** @defgroup UART_RECEPTION_TYPE_Values  UART Reception type values
-  * @{
-  */
-#define HAL_UART_RECEPTION_STANDARD          (0x00000000U)             /*!< Standard reception                       */
-#define HAL_UART_RECEPTION_TOIDLE            (0x00000001U)             /*!< Reception till completion or IDLE event  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Macros UART Exported Macros
-  * @{
-  */
-
-/** @brief Reset UART handle gstate & RxState
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
-                                                       (__HANDLE__)->MspInitCallback = NULL;             \
-                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
-                                                     } while(0U)
-#else
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
-                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
-                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
-                                                     } while(0U)
-#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
-
-/** @brief  Flushes the UART DR register
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  */
-#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
-/** @brief  Checks whether the specified UART flag is set or not.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
-  *            @arg UART_FLAG_LBD:  LIN Break detection flag
-  *            @arg UART_FLAG_TXE:  Transmit data register empty flag
-  *            @arg UART_FLAG_TC:   Transmission Complete flag
-  *            @arg UART_FLAG_RXNE: Receive data register not empty flag
-  *            @arg UART_FLAG_IDLE: Idle Line detection flag
-  *            @arg UART_FLAG_ORE:  Overrun Error flag
-  *            @arg UART_FLAG_NE:   Noise Error flag
-  *            @arg UART_FLAG_FE:   Framing Error flag
-  *            @arg UART_FLAG_PE:   Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clears the specified UART pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __FLAG__ specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
-  *            @arg UART_FLAG_LBD:  LIN Break detection flag.
-  *            @arg UART_FLAG_TC:   Transmission Complete flag.
-  *            @arg UART_FLAG_RXNE: Receive data register not empty flag.
-  *
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
-  *          error) and IDLE (Idle line detected) flags are cleared by software
-  *          sequence: a read operation to USART_SR register followed by a read
-  *          operation to USART_DR register.
-  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to
-  *          USART_SR register followed by a write operation to USART_DR register.
-  * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Clears the UART PE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)     \
-  do{                                           \
-    __IO uint32_t tmpreg = 0x00U;               \
-    tmpreg = (__HANDLE__)->Instance->SR;        \
-    tmpreg = (__HANDLE__)->Instance->DR;        \
-    UNUSED(tmpreg);                             \
-  } while(0U)
-
-/** @brief  Clears the UART FE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clears the UART NE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clears the UART ORE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clears the UART IDLE pending flag.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Enable the specified UART interrupt.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CTS:  CTS change interrupt
-  *            @arg UART_IT_LBD:  LIN Break detection interrupt
-  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:   Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_PE:   Parity Error interrupt
-  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
-
-/** @brief  Disable the specified UART interrupt.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CTS:  CTS change interrupt
-  *            @arg UART_IT_LBD:  LIN Break detection interrupt
-  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:   Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_PE:   Parity Error interrupt
-  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
-
-/** @brief  Checks whether the specified UART interrupt source is enabled or not.
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         UART Handle selects the USARTx or UARTy peripheral
-  *         (USART,UART availability and x,y values depending on device).
-  * @param  __IT__ specifies the UART interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
-  *            @arg UART_IT_LBD: LIN Break detection interrupt
-  *            @arg UART_IT_TXE: Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:  Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_ERR: Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \
-                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
-
-/** @brief  Enable CTS flow control
-  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
-  *         It is used to select the USART peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
-  do{                                                      \
-    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
-  } while(0U)
-
-/** @brief  Disable CTS flow control
-  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
-  *         It is used to select the USART peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
-  do{                                                       \
-    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
-  } while(0U)
-
-/** @brief  Enable RTS flow control
-  *         This macro allows to enable RTS hardware flow control for a given UART instance,
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
-  *         It is used to select the USART peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
-  do{                                                     \
-    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
-    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
-  } while(0U)
-
-/** @brief  Disable RTS flow control
-  *         This macro allows to disable RTS hardware flow control for a given UART instance,
-  *         without need to call HAL_UART_Init() function.
-  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
-  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
-  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
-  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
-  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
-  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
-  * @param  __HANDLE__ specifies the UART Handle.
-  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
-  *         It is used to select the USART peripheral (USART availability and x value depending on device).
-  * @retval None
-  */
-#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
-  do{                                                      \
-    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
-    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
-  } while(0U)
-
-/** @brief  Macro to enable the UART's one bit sample method
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-
-/** @brief  Macro to disable the UART's one bit sample method
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
-                                                       &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
-
-/** @brief  Enable UART
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
-
-/** @brief  Disable UART
-  * @param  __HANDLE__ specifies the UART Handle.
-  * @retval None
-  */
-#define __HAL_UART_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup UART_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
-
-/* Callbacks Register/UnRegister functions  ***********************************/
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
-                                            pUART_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
-
-HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
-  * @{
-  */
-
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
-
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
-                                           uint32_t Timeout);
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-
-/* Transfer Abort functions */
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
-
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
-void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
-
-void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control functions  ************************************************/
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group4
-  * @{
-  */
-/* Peripheral State functions  **************************************************/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup UART_Private_Constants UART Private Constants
-  * @{
-  */
-/** @brief UART interruptions flag mask
-  *
-  */
-#define UART_IT_MASK                     0x0000FFFFU
-
-#define UART_CR1_REG_INDEX               1U
-#define UART_CR2_REG_INDEX               2U
-#define UART_CR3_REG_INDEX               3U
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UART_Private_Macros UART Private Macros
-  * @{
-  */
-#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
-                                     ((LENGTH) == UART_WORDLENGTH_9B))
-#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
-#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
-                                    ((STOPBITS) == UART_STOPBITS_2))
-#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
-                                ((PARITY) == UART_PARITY_EVEN) || \
-                                ((PARITY) == UART_PARITY_ODD))
-#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
-                              (((CONTROL) == UART_HWCONTROL_NONE) || \
-                               ((CONTROL) == UART_HWCONTROL_RTS) || \
-                               ((CONTROL) == UART_HWCONTROL_CTS) || \
-                               ((CONTROL) == UART_HWCONTROL_RTS_CTS))
-#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
-#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
-                              ((STATE) == UART_STATE_ENABLE))
-#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
-                                        ((SAMPLING) == UART_OVERSAMPLING_8))
-#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
-                                                 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
-#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
-                                      ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
-#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 10500000U)
-#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
-
-#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)            ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*((uint64_t)(_BAUD_)))))
-#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_)        (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
-#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_)        ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U)\
-                                                         + 50U) / 100U)
-/* UART BRR = mantissa + overflow + fraction
-            = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
-#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_)            ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
-                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U) + \
-                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
-
-#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)             ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(2U*((uint64_t)(_BAUD_)))))
-#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_)         (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
-#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_)         ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U)\
-                                                         + 50U) / 100U)
-/* UART BRR = mantissa + overflow + fraction
-            = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
-#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_)             ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
-                                                        ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U) + \
-                                                        (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup UART_Private_Functions UART Private Functions
-  * @{
-  */
-
-HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_HAL_UART_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_uart.h
+  * @author  MCD Application Team
+  * @brief   Header file of UART HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_UART_H
+#define __STM32F4xx_HAL_UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UART
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+  * @{
+  */
+
+/**
+  * @brief UART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                           - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
+                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
+                                           Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
+
+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref UART_Word_Length */
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref UART_Stop_Bits */
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref UART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+
+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref UART_Mode */
+
+  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref UART_Hardware_Flow_Control */
+
+  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
+                                           This parameter can be a value of @ref UART_Over_Sampling */
+} UART_InitTypeDef;
+
+/**
+  * @brief HAL UART State structures definition
+  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState.
+  *        - gState contains UART state information related to global Handle management
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized. HAL UART Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (Peripheral busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef enum
+{
+  HAL_UART_STATE_RESET             = 0x00U,    /*!< Peripheral is not yet Initialized
+                                                   Value is allowed for gState and RxState */
+  HAL_UART_STATE_READY             = 0x20U,    /*!< Peripheral Initialized and ready for use
+                                                   Value is allowed for gState and RxState */
+  HAL_UART_STATE_BUSY              = 0x24U,    /*!< an internal process is ongoing
+                                                   Value is allowed for gState only */
+  HAL_UART_STATE_BUSY_TX           = 0x21U,    /*!< Data Transmission process is ongoing
+                                                   Value is allowed for gState only */
+  HAL_UART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing
+                                                   Value is allowed for RxState only */
+  HAL_UART_STATE_BUSY_TX_RX        = 0x23U,    /*!< Data Transmission and Reception process is ongoing
+                                                   Not to be used for neither gState nor RxState.
+                                                   Value is result of combination (Or) between gState and RxState values */
+  HAL_UART_STATE_TIMEOUT           = 0xA0U,    /*!< Timeout state
+                                                   Value is allowed for gState only */
+  HAL_UART_STATE_ERROR             = 0xE0U     /*!< Error
+                                                   Value is allowed for gState only */
+} HAL_UART_StateTypeDef;
+
+/**
+  * @brief HAL UART Reception type definition
+  * @note  HAL UART Reception type value aims to identify which type of Reception is ongoing.
+  *        It is expected to admit following values :
+  *           HAL_UART_RECEPTION_STANDARD         = 0x00U,
+  *           HAL_UART_RECEPTION_TOIDLE           = 0x01U,
+  */
+typedef uint32_t HAL_UART_RxTypeTypeDef;
+
+/**
+  * @brief  UART handle Structure definition
+  */
+typedef struct __UART_HandleTypeDef
+{
+  USART_TypeDef                 *Instance;        /*!< UART registers base address        */
+
+  UART_InitTypeDef              Init;             /*!< UART communication parameters      */
+
+  const uint8_t                 *pTxBuffPtr;      /*!< Pointer to UART Tx transfer Buffer */
+
+  uint16_t                      TxXferSize;       /*!< UART Tx Transfer size              */
+
+  __IO uint16_t                 TxXferCount;      /*!< UART Tx Transfer Counter           */
+
+  uint8_t                       *pRxBuffPtr;      /*!< Pointer to UART Rx transfer Buffer */
+
+  uint16_t                      RxXferSize;       /*!< UART Rx Transfer size              */
+
+  __IO uint16_t                 RxXferCount;      /*!< UART Rx Transfer Counter           */
+
+  __IO HAL_UART_RxTypeTypeDef ReceptionType;      /*!< Type of ongoing reception          */
+
+  DMA_HandleTypeDef             *hdmatx;          /*!< UART Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef             *hdmarx;          /*!< UART Rx DMA Handle parameters      */
+
+  HAL_LockTypeDef               Lock;             /*!< Locking object                     */
+
+  __IO HAL_UART_StateTypeDef    gState;           /*!< UART state information related to global Handle management
+                                                       and also related to Tx operations.
+                                                       This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO HAL_UART_StateTypeDef    RxState;          /*!< UART state information related to Rx operations.
+                                                       This parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO uint32_t                 ErrorCode;        /*!< UART Error code                    */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
+  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
+  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
+  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
+  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
+  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
+  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
+  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
+  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
+  void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback     */
+
+  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
+  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
+#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+} UART_HandleTypeDef;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL UART Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
+  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
+  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
+  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
+  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
+  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
+  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
+  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
+  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
+
+  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
+  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
+
+} HAL_UART_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL UART Callback pointer definition
+  */
+typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer to an UART callback function */
+typedef  void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos);   /*!< pointer to a UART Rx Event specific callback function */
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported Constants
+  * @{
+  */
+
+/** @defgroup UART_Error_Code UART Error Code
+  * @{
+  */
+#define HAL_UART_ERROR_NONE              0x00000000U   /*!< No error            */
+#define HAL_UART_ERROR_PE                0x00000001U   /*!< Parity error        */
+#define HAL_UART_ERROR_NE                0x00000002U   /*!< Noise error         */
+#define HAL_UART_ERROR_FE                0x00000004U   /*!< Frame error         */
+#define HAL_UART_ERROR_ORE               0x00000008U   /*!< Overrun error       */
+#define HAL_UART_ERROR_DMA               0x00000010U   /*!< DMA transfer error  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define  HAL_UART_ERROR_INVALID_CALLBACK 0x00000020U   /*!< Invalid Callback error  */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Word_Length UART Word Length
+  * @{
+  */
+#define UART_WORDLENGTH_8B                  0x00000000U
+#define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
+/**
+  * @}
+  */
+
+/** @defgroup UART_Stop_Bits UART Number of Stop Bits
+  * @{
+  */
+#define UART_STOPBITS_1                     0x00000000U
+#define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
+/**
+  * @}
+  */
+
+/** @defgroup UART_Parity UART Parity
+  * @{
+  */
+#define UART_PARITY_NONE                    0x00000000U
+#define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
+#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
+/**
+  * @}
+  */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+  * @{
+  */
+#define UART_HWCONTROL_NONE                  0x00000000U
+#define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)
+#define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)
+#define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mode UART Transfer Mode
+  * @{
+  */
+#define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)
+#define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)
+#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE | USART_CR1_RE))
+/**
+  * @}
+  */
+
+/** @defgroup UART_State UART State
+  * @{
+  */
+#define UART_STATE_DISABLE                  0x00000000U
+#define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)
+/**
+  * @}
+  */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+  * @{
+  */
+#define UART_OVERSAMPLING_16                    0x00000000U
+#define UART_OVERSAMPLING_8                     ((uint32_t)USART_CR1_OVER8)
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN_Break_Detection_Length  UART LIN Break Detection Length
+  * @{
+  */
+#define UART_LINBREAKDETECTLENGTH_10B      0x00000000U
+#define UART_LINBREAKDETECTLENGTH_11B      ((uint32_t)USART_CR2_LBDL)
+/**
+  * @}
+  */
+
+/** @defgroup UART_WakeUp_functions  UART Wakeup Functions
+  * @{
+  */
+#define UART_WAKEUPMETHOD_IDLELINE                0x00000000U
+#define UART_WAKEUPMETHOD_ADDRESSMARK             ((uint32_t)USART_CR1_WAKE)
+/**
+  * @}
+  */
+
+/** @defgroup UART_Flags   UART FLags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the SR register
+  * @{
+  */
+#define UART_FLAG_CTS                       ((uint32_t)USART_SR_CTS)
+#define UART_FLAG_LBD                       ((uint32_t)USART_SR_LBD)
+#define UART_FLAG_TXE                       ((uint32_t)USART_SR_TXE)
+#define UART_FLAG_TC                        ((uint32_t)USART_SR_TC)
+#define UART_FLAG_RXNE                      ((uint32_t)USART_SR_RXNE)
+#define UART_FLAG_IDLE                      ((uint32_t)USART_SR_IDLE)
+#define UART_FLAG_ORE                       ((uint32_t)USART_SR_ORE)
+#define UART_FLAG_NE                        ((uint32_t)USART_SR_NE)
+#define UART_FLAG_FE                        ((uint32_t)USART_SR_FE)
+#define UART_FLAG_PE                        ((uint32_t)USART_SR_PE)
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interrupt_definition  UART Interrupt Definitions
+  *        Elements values convention: 0xY000XXXX
+  *           - XXXX  : Interrupt mask (16 bits) in the Y register
+  *           - Y  : Interrupt source register (2bits)
+  *                   - 0001: CR1 register
+  *                   - 0010: CR2 register
+  *                   - 0011: CR3 register
+  * @{
+  */
+
+#define UART_IT_PE                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_PEIE))
+#define UART_IT_TXE                      ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TXEIE))
+#define UART_IT_TC                       ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_TCIE))
+#define UART_IT_RXNE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_RXNEIE))
+#define UART_IT_IDLE                     ((uint32_t)(UART_CR1_REG_INDEX << 28U | USART_CR1_IDLEIE))
+
+#define UART_IT_LBD                      ((uint32_t)(UART_CR2_REG_INDEX << 28U | USART_CR2_LBDIE))
+
+#define UART_IT_CTS                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_CTSIE))
+#define UART_IT_ERR                      ((uint32_t)(UART_CR3_REG_INDEX << 28U | USART_CR3_EIE))
+/**
+  * @}
+  */
+
+/** @defgroup UART_RECEPTION_TYPE_Values  UART Reception type values
+  * @{
+  */
+#define HAL_UART_RECEPTION_STANDARD          (0x00000000U)             /*!< Standard reception                       */
+#define HAL_UART_RECEPTION_TOIDLE            (0x00000001U)             /*!< Reception till completion or IDLE event  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+  * @{
+  */
+
+/** @brief Reset UART handle gstate & RxState
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @retval None
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                       (__HANDLE__)->MspInitCallback = NULL;             \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
+                                                     } while(0U)
+#else
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                     } while(0U)
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
+
+/** @brief  Flushes the UART DR register
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
+
+/** @brief  Checks whether the specified UART flag is set or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
+  *            @arg UART_FLAG_LBD:  LIN Break detection flag
+  *            @arg UART_FLAG_TXE:  Transmit data register empty flag
+  *            @arg UART_FLAG_TC:   Transmission Complete flag
+  *            @arg UART_FLAG_RXNE: Receive data register not empty flag
+  *            @arg UART_FLAG_IDLE: Idle Line detection flag
+  *            @arg UART_FLAG_ORE:  Overrun Error flag
+  *            @arg UART_FLAG_NE:   Noise Error flag
+  *            @arg UART_FLAG_FE:   Framing Error flag
+  *            @arg UART_FLAG_PE:   Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clears the specified UART pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
+  *            @arg UART_FLAG_LBD:  LIN Break detection flag.
+  *            @arg UART_FLAG_TC:   Transmission Complete flag.
+  *            @arg UART_FLAG_RXNE: Receive data register not empty flag.
+  *
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (Overrun
+  *          error) and IDLE (Idle line detected) flags are cleared by software
+  *          sequence: a read operation to USART_SR register followed by a read
+  *          operation to USART_DR register.
+  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
+  * @note   TC flag can be also cleared by software sequence: a read operation to
+  *          USART_SR register followed by a write operation to USART_DR register.
+  * @note   TXE flag is cleared only by a write to the USART_DR register.
+  *
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+
+/** @brief  Clears the UART PE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)     \
+  do{                                           \
+    __IO uint32_t tmpreg = 0x00U;               \
+    tmpreg = (__HANDLE__)->Instance->SR;        \
+    tmpreg = (__HANDLE__)->Instance->DR;        \
+    UNUSED(tmpreg);                             \
+  } while(0U)
+
+/** @brief  Clears the UART FE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief  Clears the UART NE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief  Clears the UART ORE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief  Clears the UART IDLE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
+
+/** @brief  Enable the specified UART interrupt.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg UART_IT_CTS:  CTS change interrupt
+  *            @arg UART_IT_LBD:  LIN Break detection interrupt
+  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
+  *            @arg UART_IT_TC:   Transmission complete interrupt
+  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg UART_IT_IDLE: Idle line detection interrupt
+  *            @arg UART_IT_PE:   Parity Error interrupt
+  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+                                                           (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
+                                                           ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
+
+/** @brief  Disable the specified UART interrupt.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg UART_IT_CTS:  CTS change interrupt
+  *            @arg UART_IT_LBD:  LIN Break detection interrupt
+  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
+  *            @arg UART_IT_TC:   Transmission complete interrupt
+  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg UART_IT_IDLE: Idle line detection interrupt
+  *            @arg UART_IT_PE:   Parity Error interrupt
+  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28U) == UART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+                                                           (((__INTERRUPT__) >> 28U) == UART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
+                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
+
+/** @brief  Checks whether the specified UART interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         UART Handle selects the USARTx or UARTy peripheral
+  *         (USART,UART availability and x,y values depending on device).
+  * @param  __IT__ specifies the UART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
+  *            @arg UART_IT_LBD: LIN Break detection interrupt
+  *            @arg UART_IT_TXE: Transmit Data Register empty interrupt
+  *            @arg UART_IT_TC:  Transmission complete interrupt
+  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg UART_IT_IDLE: Idle line detection interrupt
+  *            @arg UART_IT_ERR: Error interrupt
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \
+                                                       (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
+
+/** @brief  Enable CTS flow control
+  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
+  *         It is used to select the USART peripheral (USART availability and x value depending on device).
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \
+  do{                                                      \
+    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \
+  } while(0U)
+
+/** @brief  Disable CTS flow control
+  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
+  *         It is used to select the USART peripheral (USART availability and x value depending on device).
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \
+  do{                                                       \
+    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \
+  } while(0U)
+
+/** @brief  Enable RTS flow control
+  *         This macro allows to enable RTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
+  *         It is used to select the USART peripheral (USART availability and x value depending on device).
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \
+  do{                                                     \
+    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \
+  } while(0U)
+
+/** @brief  Disable RTS flow control
+  *         This macro allows to disable RTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
+  *             and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  *         The Handle Instance can be any USARTx (supporting the HW Flow control feature).
+  *         It is used to select the USART peripheral (USART availability and x value depending on device).
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \
+  do{                                                      \
+    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \
+  } while(0U)
+
+/** @brief  Macro to enable the UART's one bit sample method
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Macro to disable the UART's one bit sample method
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
+                                                       &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
+
+/** @brief  Enable UART
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
+
+/** @brief  Disable UART
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+                                           uint32_t Timeout);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group4
+  * @{
+  */
+/* Peripheral State functions  **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+  * @{
+  */
+/** @brief UART interruptions flag mask
+  *
+  */
+#define UART_IT_MASK                     0x0000FFFFU
+
+#define UART_CR1_REG_INDEX               1U
+#define UART_CR2_REG_INDEX               2U
+#define UART_CR3_REG_INDEX               3U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UART_Private_Macros UART Private Macros
+  * @{
+  */
+#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
+                                     ((LENGTH) == UART_WORDLENGTH_9B))
+#define IS_UART_LIN_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B))
+#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
+                                    ((STOPBITS) == UART_STOPBITS_2))
+#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
+                                ((PARITY) == UART_PARITY_EVEN) || \
+                                ((PARITY) == UART_PARITY_ODD))
+#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                              (((CONTROL) == UART_HWCONTROL_NONE) || \
+                               ((CONTROL) == UART_HWCONTROL_RTS) || \
+                               ((CONTROL) == UART_HWCONTROL_CTS) || \
+                               ((CONTROL) == UART_HWCONTROL_RTS_CTS))
+#define IS_UART_MODE(MODE) ((((MODE) & 0x0000FFF3U) == 0x00U) && ((MODE) != 0x00U))
+#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
+                              ((STATE) == UART_STATE_ENABLE))
+#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
+                                        ((SAMPLING) == UART_OVERSAMPLING_8))
+#define IS_UART_LIN_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16))
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
+                                                 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
+#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
+                                      ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
+#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) <= 10500000U)
+#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0x0FU)
+
+#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)            ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*((uint64_t)(_BAUD_)))))
+#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_)        (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U)
+#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_)        ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U)\
+                                                         + 50U) / 100U)
+/* UART BRR = mantissa + overflow + fraction
+            = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */
+#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_)            ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \
+                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0xF0U) + \
+                                                        (UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0FU))
+
+#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)             ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(2U*((uint64_t)(_BAUD_)))))
+#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_)         (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U)
+#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_)         ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U)\
+                                                         + 50U) / 100U)
+/* UART BRR = mantissa + overflow + fraction
+            = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */
+#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_)             ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \
+                                                        ((UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0xF8U) << 1U) + \
+                                                        (UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x07U))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_UART_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h
index 5083c10..460edfc 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_bus.h
@@ -1,2105 +1,2105 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_ll_bus.h
-  * @author  MCD Application Team
-  * @brief   Header file of BUS LL module.
-
-  @verbatim
-                      ##### RCC Limitations #####
-  ==============================================================================
-    [..]
-      A delay between an RCC peripheral clock enable and the effective peripheral
-      enabling should be taken into account in order to manage the peripheral read/write
-      from/to registers.
-      (+) This delay depends on the peripheral mapping.
-        (++) AHB & APB peripherals, 1 dummy read is necessary
-
-    [..]
-      Workarounds:
-      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
-          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_BUS_H
-#define __STM32F4xx_LL_BUS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_LL_Driver
-  * @{
-  */
-
-#if defined(RCC)
-
-/** @defgroup BUS_LL BUS
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
-  * @{
-  */
-
-/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
-  * @{
-  */
-#define LL_AHB1_GRP1_PERIPH_ALL             0xFFFFFFFFU
-#define LL_AHB1_GRP1_PERIPH_GPIOA           RCC_AHB1ENR_GPIOAEN
-#define LL_AHB1_GRP1_PERIPH_GPIOB           RCC_AHB1ENR_GPIOBEN
-#define LL_AHB1_GRP1_PERIPH_GPIOC           RCC_AHB1ENR_GPIOCEN
-#if defined(GPIOD)
-#define LL_AHB1_GRP1_PERIPH_GPIOD           RCC_AHB1ENR_GPIODEN
-#endif /* GPIOD */
-#if defined(GPIOE)
-#define LL_AHB1_GRP1_PERIPH_GPIOE           RCC_AHB1ENR_GPIOEEN
-#endif /* GPIOE */
-#if defined(GPIOF)
-#define LL_AHB1_GRP1_PERIPH_GPIOF           RCC_AHB1ENR_GPIOFEN
-#endif /* GPIOF */
-#if defined(GPIOG)
-#define LL_AHB1_GRP1_PERIPH_GPIOG           RCC_AHB1ENR_GPIOGEN
-#endif /* GPIOG */
-#if defined(GPIOH)
-#define LL_AHB1_GRP1_PERIPH_GPIOH           RCC_AHB1ENR_GPIOHEN
-#endif /* GPIOH */
-#if defined(GPIOI)
-#define LL_AHB1_GRP1_PERIPH_GPIOI           RCC_AHB1ENR_GPIOIEN
-#endif /* GPIOI */
-#if defined(GPIOJ)
-#define LL_AHB1_GRP1_PERIPH_GPIOJ           RCC_AHB1ENR_GPIOJEN
-#endif /* GPIOJ */
-#if defined(GPIOK)
-#define LL_AHB1_GRP1_PERIPH_GPIOK           RCC_AHB1ENR_GPIOKEN
-#endif /* GPIOK */
-#define LL_AHB1_GRP1_PERIPH_CRC             RCC_AHB1ENR_CRCEN
-#if defined(RCC_AHB1ENR_BKPSRAMEN)
-#define LL_AHB1_GRP1_PERIPH_BKPSRAM         RCC_AHB1ENR_BKPSRAMEN
-#endif /* RCC_AHB1ENR_BKPSRAMEN */
-#if defined(RCC_AHB1ENR_CCMDATARAMEN)
-#define LL_AHB1_GRP1_PERIPH_CCMDATARAM      RCC_AHB1ENR_CCMDATARAMEN
-#endif /* RCC_AHB1ENR_CCMDATARAMEN */
-#define LL_AHB1_GRP1_PERIPH_DMA1            RCC_AHB1ENR_DMA1EN
-#define LL_AHB1_GRP1_PERIPH_DMA2            RCC_AHB1ENR_DMA2EN
-#if defined(RCC_AHB1ENR_RNGEN)
-#define LL_AHB1_GRP1_PERIPH_RNG             RCC_AHB1ENR_RNGEN
-#endif /* RCC_AHB1ENR_RNGEN */
-#if defined(DMA2D)
-#define LL_AHB1_GRP1_PERIPH_DMA2D           RCC_AHB1ENR_DMA2DEN
-#endif /* DMA2D */
-#if defined(ETH)
-#define LL_AHB1_GRP1_PERIPH_ETHMAC          RCC_AHB1ENR_ETHMACEN
-#define LL_AHB1_GRP1_PERIPH_ETHMACTX        RCC_AHB1ENR_ETHMACTXEN
-#define LL_AHB1_GRP1_PERIPH_ETHMACRX        RCC_AHB1ENR_ETHMACRXEN
-#define LL_AHB1_GRP1_PERIPH_ETHMACPTP       RCC_AHB1ENR_ETHMACPTPEN
-#endif /* ETH */
-#if defined(USB_OTG_HS)
-#define LL_AHB1_GRP1_PERIPH_OTGHS           RCC_AHB1ENR_OTGHSEN
-#define LL_AHB1_GRP1_PERIPH_OTGHSULPI       RCC_AHB1ENR_OTGHSULPIEN
-#endif /* USB_OTG_HS */
-#define LL_AHB1_GRP1_PERIPH_FLITF           RCC_AHB1LPENR_FLITFLPEN
-#define LL_AHB1_GRP1_PERIPH_SRAM1           RCC_AHB1LPENR_SRAM1LPEN
-#if defined(RCC_AHB1LPENR_SRAM2LPEN)
-#define LL_AHB1_GRP1_PERIPH_SRAM2           RCC_AHB1LPENR_SRAM2LPEN
-#endif /* RCC_AHB1LPENR_SRAM2LPEN */
-#if defined(RCC_AHB1LPENR_SRAM3LPEN)
-#define LL_AHB1_GRP1_PERIPH_SRAM3           RCC_AHB1LPENR_SRAM3LPEN
-#endif /* RCC_AHB1LPENR_SRAM3LPEN */
-/**
-  * @}
-  */
-
-#if defined(RCC_AHB2_SUPPORT)
-/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
-  * @{
-  */
-#define LL_AHB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
-#if defined(DCMI)
-#define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN
-#endif /* DCMI */
-#if defined(CRYP)
-#define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN
-#endif /* CRYP */
-#if defined(AES)
-#define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN
-#endif /* AES */
-#if defined(HASH)
-#define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN
-#endif /* HASH */
-#if defined(RCC_AHB2ENR_RNGEN)
-#define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
-#endif /* RCC_AHB2ENR_RNGEN */
-#if defined(USB_OTG_FS)
-#define LL_AHB2_GRP1_PERIPH_OTGFS          RCC_AHB2ENR_OTGFSEN
-#endif /* USB_OTG_FS */
-/**
-  * @}
-  */
-#endif /* RCC_AHB2_SUPPORT */
-
-#if defined(RCC_AHB3_SUPPORT)
-/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
-  * @{
-  */
-#define LL_AHB3_GRP1_PERIPH_ALL            0xFFFFFFFFU
-#if defined(FSMC_Bank1)
-#define LL_AHB3_GRP1_PERIPH_FSMC           RCC_AHB3ENR_FSMCEN
-#endif /* FSMC_Bank1 */
-#if defined(FMC_Bank1)
-#define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
-#endif /* FMC_Bank1 */
-#if defined(QUADSPI)
-#define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
-#endif /* QUADSPI */
-/**
-  * @}
-  */
-#endif /* RCC_AHB3_SUPPORT */
-
-/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
-  * @{
-  */
-#define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
-#if defined(TIM2)
-#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN
-#endif /* TIM2 */
-#if defined(TIM3)
-#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN
-#endif /* TIM3 */
-#if defined(TIM4)
-#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR_TIM4EN
-#endif /* TIM4 */
-#define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR_TIM5EN
-#if defined(TIM6)
-#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN
-#endif /* TIM6 */
-#if defined(TIM7)
-#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN
-#endif /* TIM7 */
-#if defined(TIM12)
-#define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1ENR_TIM12EN
-#endif /* TIM12 */
-#if defined(TIM13)
-#define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1ENR_TIM13EN
-#endif /* TIM13 */
-#if defined(TIM14)
-#define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1ENR_TIM14EN
-#endif /* TIM14 */
-#if defined(LPTIM1)
-#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR_LPTIM1EN
-#endif /* LPTIM1 */
-#if defined(RCC_APB1ENR_RTCAPBEN)
-#define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR_RTCAPBEN
-#endif /* RCC_APB1ENR_RTCAPBEN */
-#define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN
-#if defined(SPI2)
-#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN
-#endif /* SPI2 */
-#if defined(SPI3)
-#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR_SPI3EN
-#endif /* SPI3 */
-#if defined(SPDIFRX)
-#define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1ENR_SPDIFRXEN
-#endif /* SPDIFRX */
-#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN
-#if defined(USART3)
-#define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR_USART3EN
-#endif /* USART3 */
-#if defined(UART4)
-#define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR_UART4EN
-#endif /* UART4 */
-#if defined(UART5)
-#define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR_UART5EN
-#endif /* UART5 */
-#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN
-#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN
-#if defined(I2C3)
-#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR_I2C3EN
-#endif /* I2C3 */
-#if defined(FMPI2C1)
-#define LL_APB1_GRP1_PERIPH_FMPI2C1        RCC_APB1ENR_FMPI2C1EN
-#endif /* FMPI2C1 */
-#if defined(CAN1)
-#define LL_APB1_GRP1_PERIPH_CAN1           RCC_APB1ENR_CAN1EN
-#endif /* CAN1 */
-#if defined(CAN2)
-#define LL_APB1_GRP1_PERIPH_CAN2           RCC_APB1ENR_CAN2EN
-#endif /* CAN2 */
-#if defined(CAN3)
-#define LL_APB1_GRP1_PERIPH_CAN3           RCC_APB1ENR_CAN3EN
-#endif /* CAN3 */
-#if defined(CEC)
-#define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1ENR_CECEN
-#endif /* CEC */
-#define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN
-#if defined(DAC1)
-#define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN
-#endif /* DAC1 */
-#if defined(UART7)
-#define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1ENR_UART7EN
-#endif /* UART7 */
-#if defined(UART8)
-#define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1ENR_UART8EN
-#endif /* UART8 */
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
-  * @{
-  */
-#define LL_APB2_GRP1_PERIPH_ALL          0xFFFFFFFFU
-#define LL_APB2_GRP1_PERIPH_TIM1         RCC_APB2ENR_TIM1EN
-#if defined(TIM8)
-#define LL_APB2_GRP1_PERIPH_TIM8         RCC_APB2ENR_TIM8EN
-#endif /* TIM8 */
-#define LL_APB2_GRP1_PERIPH_USART1       RCC_APB2ENR_USART1EN
-#if defined(USART6)
-#define LL_APB2_GRP1_PERIPH_USART6       RCC_APB2ENR_USART6EN
-#endif /* USART6 */
-#if defined(UART9)
-#define LL_APB2_GRP1_PERIPH_UART9        RCC_APB2ENR_UART9EN
-#endif /* UART9 */
-#if defined(UART10)
-#define LL_APB2_GRP1_PERIPH_UART10       RCC_APB2ENR_UART10EN
-#endif /* UART10 */
-#define LL_APB2_GRP1_PERIPH_ADC1         RCC_APB2ENR_ADC1EN
-#if defined(ADC2)
-#define LL_APB2_GRP1_PERIPH_ADC2         RCC_APB2ENR_ADC2EN
-#endif /* ADC2 */
-#if defined(ADC3)
-#define LL_APB2_GRP1_PERIPH_ADC3         RCC_APB2ENR_ADC3EN
-#endif /* ADC3 */
-#if defined(SDIO)
-#define LL_APB2_GRP1_PERIPH_SDIO         RCC_APB2ENR_SDIOEN
-#endif /* SDIO */
-#define LL_APB2_GRP1_PERIPH_SPI1         RCC_APB2ENR_SPI1EN
-#if defined(SPI4)
-#define LL_APB2_GRP1_PERIPH_SPI4         RCC_APB2ENR_SPI4EN
-#endif /* SPI4 */
-#define LL_APB2_GRP1_PERIPH_SYSCFG       RCC_APB2ENR_SYSCFGEN
-#if defined(RCC_APB2ENR_EXTITEN)
-#define LL_APB2_GRP1_PERIPH_EXTI         RCC_APB2ENR_EXTITEN
-#endif /* RCC_APB2ENR_EXTITEN */
-#define LL_APB2_GRP1_PERIPH_TIM9         RCC_APB2ENR_TIM9EN
-#if defined(TIM10)
-#define LL_APB2_GRP1_PERIPH_TIM10        RCC_APB2ENR_TIM10EN
-#endif /* TIM10 */
-#define LL_APB2_GRP1_PERIPH_TIM11        RCC_APB2ENR_TIM11EN
-#if defined(SPI5)
-#define LL_APB2_GRP1_PERIPH_SPI5         RCC_APB2ENR_SPI5EN
-#endif /* SPI5 */
-#if defined(SPI6)
-#define LL_APB2_GRP1_PERIPH_SPI6         RCC_APB2ENR_SPI6EN
-#endif /* SPI6 */
-#if defined(SAI1)
-#define LL_APB2_GRP1_PERIPH_SAI1         RCC_APB2ENR_SAI1EN
-#endif /* SAI1 */
-#if defined(SAI2)
-#define LL_APB2_GRP1_PERIPH_SAI2         RCC_APB2ENR_SAI2EN
-#endif /* SAI2 */
-#if defined(LTDC)
-#define LL_APB2_GRP1_PERIPH_LTDC         RCC_APB2ENR_LTDCEN
-#endif /* LTDC */
-#if defined(DSI)
-#define LL_APB2_GRP1_PERIPH_DSI          RCC_APB2ENR_DSIEN
-#endif /* DSI */
-#if defined(DFSDM1_Channel0)
-#define LL_APB2_GRP1_PERIPH_DFSDM1       RCC_APB2ENR_DFSDM1EN
-#endif /* DFSDM1_Channel0 */
-#if defined(DFSDM2_Channel0)
-#define LL_APB2_GRP1_PERIPH_DFSDM2       RCC_APB2ENR_DFSDM2EN
-#endif /* DFSDM2_Channel0 */
-#define LL_APB2_GRP1_PERIPH_ADC          RCC_APB2RSTR_ADCRST
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
-  * @{
-  */
-
-/** @defgroup BUS_LL_EF_AHB1 AHB1
-  * @{
-  */
-
-/**
-  * @brief  Enable AHB1 peripherals clock.
-  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      CCMDATARAMEN       LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      RNGEN              LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_EnableClock\n
-  *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHB1ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if AHB1 peripheral clock is enabled or not
-  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      CCMDATARAMEN       LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      RNGEN              LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_IsEnabledClock\n
-  *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
-}
-
-/**
-  * @brief  Disable AHB1 peripherals clock.
-  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      CCMDATARAMEN       LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      RNGEN              LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_DisableClock\n
-  *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB1ENR, Periphs);
-}
-
-/**
-  * @brief  Force AHB1 peripherals reset.
-  * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     RNGRST        LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ForceReset\n
-  *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->AHB1RSTR, Periphs);
-}
-
-/**
-  * @brief  Release AHB1 peripherals reset.
-  * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     RNGRST        LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ReleaseReset\n
-  *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB1RSTR, Periphs);
-}
-
-/**
-  * @brief  Enable AHB1 peripheral clocks in low-power mode
-  * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    SRAM3LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    RNGLPEN        LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
-  *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockLowPower
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHB1LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable AHB1 peripheral clocks in low-power mode
-  * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    SRAM3LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    RNGLPEN        LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
-  *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockLowPower
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
-  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB1LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-#if defined(RCC_AHB2_SUPPORT)
-/** @defgroup BUS_LL_EF_AHB2 AHB2
-  * @{
-  */
-
-/**
-  * @brief  Enable AHB2 peripherals clock.
-  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      AESEN        LL_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_EnableClock\n
-  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHB2ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if AHB2 peripheral clock is enabled or not
-  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      AESEN        LL_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_IsEnabledClock\n
-  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
-}
-
-/**
-  * @brief  Disable AHB2 peripherals clock.
-  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      AESEN        LL_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_DisableClock\n
-  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB2ENR, Periphs);
-}
-
-/**
-  * @brief  Force AHB2 peripherals reset.
-  * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ForceReset\n
-  *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ForceReset\n
-  *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ForceReset\n
-  *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ForceReset\n
-  *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ForceReset\n
-  *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->AHB2RSTR, Periphs);
-}
-
-/**
-  * @brief  Release AHB2 peripherals reset.
-  * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ReleaseReset\n
-  *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ReleaseReset\n
-  *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ReleaseReset\n
-  *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ReleaseReset\n
-  *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ReleaseReset\n
-  *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB2RSTR, Periphs);
-}
-
-/**
-  * @brief  Enable AHB2 peripheral clocks in low-power mode
-  * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_EnableClockLowPower\n
-  *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
-  *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_EnableClockLowPower\n
-  *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
-  *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_EnableClockLowPower\n
-  *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_EnableClockLowPower
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHB2LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable AHB2 peripheral clocks in low-power mode
-  * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_DisableClockLowPower\n
-  *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
-  *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_DisableClockLowPower\n
-  *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
-  *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_DisableClockLowPower\n
-  *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_DisableClockLowPower
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB2LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-#endif /* RCC_AHB2_SUPPORT */
-
-#if defined(RCC_AHB3_SUPPORT)
-/** @defgroup BUS_LL_EF_AHB3 AHB3
-  * @{
-  */
-
-/**
-  * @brief  Enable AHB3 peripherals clock.
-  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      FSMCEN        LL_AHB3_GRP1_EnableClock\n
-  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHB3ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if AHB3 peripheral clock is enabled or not
-  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      FSMCEN        LL_AHB3_GRP1_IsEnabledClock\n
-  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
-}
-
-/**
-  * @brief  Disable AHB3 peripherals clock.
-  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      FSMCEN        LL_AHB3_GRP1_DisableClock\n
-  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB3ENR, Periphs);
-}
-
-/**
-  * @brief  Force AHB3 peripherals reset.
-  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n
-  *         AHB3RSTR     FSMCRST       LL_AHB3_GRP1_ForceReset\n
-  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->AHB3RSTR, Periphs);
-}
-
-/**
-  * @brief  Release AHB3 peripherals reset.
-  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
-  *         AHB3RSTR     FSMCRST       LL_AHB3_GRP1_ReleaseReset\n
-  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB3RSTR, Periphs);
-}
-
-/**
-  * @brief  Enable AHB3 peripheral clocks in low-power mode
-  * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockLowPower\n
-  *         AHB3LPENR    FSMCLPEN      LL_AHB3_GRP1_EnableClockLowPower\n
-  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockLowPower
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->AHB3LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable AHB3 peripheral clocks in low-power mode
-  * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockLowPower\n
-  *         AHB3LPENR    FSMCLPEN      LL_AHB3_GRP1_DisableClockLowPower\n
-  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockLowPower
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
-  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->AHB3LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-#endif /* RCC_AHB3_SUPPORT */
-
-/** @defgroup BUS_LL_EF_APB1 APB1
-  * @{
-  */
-
-/**
-  * @brief  Enable APB1 peripherals clock.
-  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     TIM3EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     TIM4EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     TIM5EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     TIM6EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     TIM7EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     TIM12EN       LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     TIM13EN       LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     TIM14EN       LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     WWDGEN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     SPI2EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     SPI3EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     USART2EN      LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     USART3EN      LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     UART4EN       LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     UART5EN       LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     I2C1EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     I2C2EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     I2C3EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     FMPI2C1EN     LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     CAN1EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     CAN2EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     CAN3EN        LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     CECEN         LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     PWREN         LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     DACEN         LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     UART7EN       LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     UART8EN       LL_APB1_GRP1_EnableClock\n
-  *         APB1ENR     RTCAPBEN      LL_APB1_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB1ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if APB1 peripheral clock is enabled or not
-  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     FMPI2C1EN     LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     CAN1EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     CAN2EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     CAN3EN        LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     CECEN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     PWREN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     DACEN         LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     UART8EN       LL_APB1_GRP1_IsEnabledClock\n
-  *         APB1ENR     RTCAPBEN      LL_APB1_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
-}
-
-/**
-  * @brief  Disable APB1 peripherals clock.
-  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     TIM3EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     TIM4EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     TIM5EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     TIM6EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     TIM7EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     TIM12EN       LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     TIM13EN       LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     TIM14EN       LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     WWDGEN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     SPI2EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     SPI3EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     USART2EN      LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     USART3EN      LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     UART4EN       LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     UART5EN       LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     I2C1EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     I2C2EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     I2C3EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     FMPI2C1EN     LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     CAN1EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     CAN2EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     CAN3EN        LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     CECEN         LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     PWREN         LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     DACEN         LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     UART7EN       LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     UART8EN       LL_APB1_GRP1_DisableClock\n
-  *         APB1ENR     RTCAPBEN      LL_APB1_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB1ENR, Periphs);
-}
-
-/**
-  * @brief  Force APB1 peripherals reset.
-  * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     USART2RST      LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     USART3RST      LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     UART4RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     UART5RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     FMPI2C1RST     LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     CECRST         LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     PWRRST         LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     DACRST         LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     UART7RST       LL_APB1_GRP1_ForceReset\n
-  *         APB1RSTR     UART8RST       LL_APB1_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->APB1RSTR, Periphs);
-}
-
-/**
-  * @brief  Release APB1 peripherals reset.
-  * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     USART2RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     USART3RST      LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     UART4RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     UART5RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     FMPI2C1RST     LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     CECRST         LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     PWRRST         LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     DACRST         LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     UART7RST       LL_APB1_GRP1_ReleaseReset\n
-  *         APB1RSTR     UART8RST       LL_APB1_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB1RSTR, Periphs);
-}
-
-/**
-  * @brief  Enable APB1 peripheral clocks in low-power mode
-  * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     FMPI2C1LPEN     LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     CECLPEN         LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     DACLPEN         LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_EnableClockLowPower\n
-  *         APB1LPENR     RTCAPBLPEN      LL_APB1_GRP1_EnableClockLowPower
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB1LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable APB1 peripheral clocks in low-power mode
-  * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     FMPI2C1LPEN     LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     CECLPEN         LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     DACLPEN         LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_DisableClockLowPower\n
-  *         APB1LPENR     RTCAPBLPEN      LL_APB1_GRP1_DisableClockLowPower
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
-  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
-  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
-  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB1LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup BUS_LL_EF_APB2 APB2
-  * @{
-  */
-
-/**
-  * @brief  Enable APB2 peripherals clock.
-  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     TIM8EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     USART1EN      LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     USART6EN      LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     UART9EN       LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     UART10EN      LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     ADC1EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     ADC2EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     ADC3EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     SDIOEN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     SPI1EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     SPI4EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     EXTITEN       LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     TIM9EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     TIM10EN       LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     TIM11EN       LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     SPI5EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     SPI6EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     SAI1EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     SAI2EN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     LTDCEN        LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     DSIEN         LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_EnableClock\n
-  *         APB2ENR     DFSDM2EN      LL_APB2_GRP1_EnableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
-
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB2ENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Check if APB2 peripheral clock is enabled or not
-  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     USART1EN      LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     USART6EN      LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     UART9EN       LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     UART10EN      LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     ADC1EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     ADC2EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     ADC3EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     SDIOEN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     SPI4EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     EXTITEN       LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     TIM9EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     TIM10EN       LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     TIM11EN       LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     SPI5EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     SPI6EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     SAI2EN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     LTDCEN        LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     DSIEN         LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\n
-  *         APB2ENR     DFSDM2EN      LL_APB2_GRP1_IsEnabledClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval State of Periphs (1 or 0).
-*/
-__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
-{
-  return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
-}
-
-/**
-  * @brief  Disable APB2 peripherals clock.
-  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     TIM8EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     USART1EN      LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     USART6EN      LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     UART9EN       LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     UART10EN      LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     ADC1EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     ADC2EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     ADC3EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     SDIOEN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     SPI1EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     SPI4EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     EXTITEN       LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     TIM9EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     TIM10EN       LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     TIM11EN       LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     SPI5EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     SPI6EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     SAI1EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     SAI2EN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     LTDCEN        LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     DSIEN         LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_DisableClock\n
-  *         APB2ENR     DFSDM2EN      LL_APB2_GRP1_DisableClock
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB2ENR, Periphs);
-}
-
-/**
-  * @brief  Force APB2 peripherals reset.
-  * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     USART1RST      LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     USART6RST      LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     UART9RST       LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     UART10RST      LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     ADCRST         LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     SDIORST        LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     DSIRST         LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ForceReset\n
-  *         APB2RSTR     DFSDM2RST      LL_APB2_GRP1_ForceReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
-{
-  SET_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
-  * @brief  Release APB2 peripherals reset.
-  * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     USART1RST      LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     USART6RST      LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     UART9RST       LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     UART10RST      LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     ADCRST         LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     SDIORST        LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     DSIRST         LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ReleaseReset\n
-  *         APB2RSTR     DFSDM2RST      LL_APB2_GRP1_ReleaseReset
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB2RSTR, Periphs);
-}
-
-/**
-  * @brief  Enable APB2 peripheral clocks in low-power mode
-  * @rmtoll APB2LPENR     TIM1LPEN        LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     TIM8LPEN        LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     USART1LPEN      LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     USART6LPEN      LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     UART9LPEN       LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     UART10LPEN      LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     ADC1LPEN        LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     ADC2LPEN        LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     ADC3LPEN        LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     SDIOLPEN        LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     SPI1LPEN        LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     SPI4LPEN        LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     SYSCFGLPEN      LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     EXTITLPEN       LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     TIM9LPEN        LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     TIM10LPEN       LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     TIM11LPEN       LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     SPI5LPEN        LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     SPI6LPEN        LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     SAI1LPEN        LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     SAI2LPEN        LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     LTDCLPEN        LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     DFSDM1LPEN      LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_EnableClockLowPower\n
-  *         APB2LPENR     DFSDM2LPEN      LL_APB2_GRP1_EnableClockLowPower
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
-{
-  __IO uint32_t tmpreg;
-  SET_BIT(RCC->APB2LPENR, Periphs);
-  /* Delay after an RCC peripheral clock enabling */
-  tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
-  (void)tmpreg;
-}
-
-/**
-  * @brief  Disable APB2 peripheral clocks in low-power mode
-  * @rmtoll APB2LPENR     TIM1LPEN        LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     TIM8LPEN        LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     USART1LPEN      LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     USART6LPEN      LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     UART9LPEN       LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     UART10LPEN      LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     ADC1LPEN        LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     ADC2LPEN        LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     ADC3LPEN        LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     SDIOLPEN        LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     SPI1LPEN        LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     SPI4LPEN        LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     SYSCFGLPEN      LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     EXTITLPEN       LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     TIM9LPEN        LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     TIM10LPEN       LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     TIM11LPEN       LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     SPI5LPEN        LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     SPI6LPEN        LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     SAI1LPEN        LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     SAI2LPEN        LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     LTDCLPEN        LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     DFSDM1LPEN      LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_DisableClockLowPower\n
-  *         APB2LPENR     DFSDM2LPEN      LL_APB2_GRP1_DisableClockLowPower
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
-  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
-  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-*/
-__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
-{
-  CLEAR_BIT(RCC->APB2LPENR, Periphs);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(RCC) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_LL_BUS_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_bus.h
+  * @author  MCD Application Team
+  * @brief   Header file of BUS LL module.
+
+  @verbatim
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+        (++) AHB & APB peripherals, 1 dummy read is necessary
+
+    [..]
+      Workarounds:
+      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_BUS_H
+#define __STM32F4xx_LL_BUS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup BUS_LL BUS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
+  * @{
+  */
+
+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB1_GRP1_PERIPH_ALL             0xFFFFFFFFU
+#define LL_AHB1_GRP1_PERIPH_GPIOA           RCC_AHB1ENR_GPIOAEN
+#define LL_AHB1_GRP1_PERIPH_GPIOB           RCC_AHB1ENR_GPIOBEN
+#define LL_AHB1_GRP1_PERIPH_GPIOC           RCC_AHB1ENR_GPIOCEN
+#if defined(GPIOD)
+#define LL_AHB1_GRP1_PERIPH_GPIOD           RCC_AHB1ENR_GPIODEN
+#endif /* GPIOD */
+#if defined(GPIOE)
+#define LL_AHB1_GRP1_PERIPH_GPIOE           RCC_AHB1ENR_GPIOEEN
+#endif /* GPIOE */
+#if defined(GPIOF)
+#define LL_AHB1_GRP1_PERIPH_GPIOF           RCC_AHB1ENR_GPIOFEN
+#endif /* GPIOF */
+#if defined(GPIOG)
+#define LL_AHB1_GRP1_PERIPH_GPIOG           RCC_AHB1ENR_GPIOGEN
+#endif /* GPIOG */
+#if defined(GPIOH)
+#define LL_AHB1_GRP1_PERIPH_GPIOH           RCC_AHB1ENR_GPIOHEN
+#endif /* GPIOH */
+#if defined(GPIOI)
+#define LL_AHB1_GRP1_PERIPH_GPIOI           RCC_AHB1ENR_GPIOIEN
+#endif /* GPIOI */
+#if defined(GPIOJ)
+#define LL_AHB1_GRP1_PERIPH_GPIOJ           RCC_AHB1ENR_GPIOJEN
+#endif /* GPIOJ */
+#if defined(GPIOK)
+#define LL_AHB1_GRP1_PERIPH_GPIOK           RCC_AHB1ENR_GPIOKEN
+#endif /* GPIOK */
+#define LL_AHB1_GRP1_PERIPH_CRC             RCC_AHB1ENR_CRCEN
+#if defined(RCC_AHB1ENR_BKPSRAMEN)
+#define LL_AHB1_GRP1_PERIPH_BKPSRAM         RCC_AHB1ENR_BKPSRAMEN
+#endif /* RCC_AHB1ENR_BKPSRAMEN */
+#if defined(RCC_AHB1ENR_CCMDATARAMEN)
+#define LL_AHB1_GRP1_PERIPH_CCMDATARAM      RCC_AHB1ENR_CCMDATARAMEN
+#endif /* RCC_AHB1ENR_CCMDATARAMEN */
+#define LL_AHB1_GRP1_PERIPH_DMA1            RCC_AHB1ENR_DMA1EN
+#define LL_AHB1_GRP1_PERIPH_DMA2            RCC_AHB1ENR_DMA2EN
+#if defined(RCC_AHB1ENR_RNGEN)
+#define LL_AHB1_GRP1_PERIPH_RNG             RCC_AHB1ENR_RNGEN
+#endif /* RCC_AHB1ENR_RNGEN */
+#if defined(DMA2D)
+#define LL_AHB1_GRP1_PERIPH_DMA2D           RCC_AHB1ENR_DMA2DEN
+#endif /* DMA2D */
+#if defined(ETH)
+#define LL_AHB1_GRP1_PERIPH_ETHMAC          RCC_AHB1ENR_ETHMACEN
+#define LL_AHB1_GRP1_PERIPH_ETHMACTX        RCC_AHB1ENR_ETHMACTXEN
+#define LL_AHB1_GRP1_PERIPH_ETHMACRX        RCC_AHB1ENR_ETHMACRXEN
+#define LL_AHB1_GRP1_PERIPH_ETHMACPTP       RCC_AHB1ENR_ETHMACPTPEN
+#endif /* ETH */
+#if defined(USB_OTG_HS)
+#define LL_AHB1_GRP1_PERIPH_OTGHS           RCC_AHB1ENR_OTGHSEN
+#define LL_AHB1_GRP1_PERIPH_OTGHSULPI       RCC_AHB1ENR_OTGHSULPIEN
+#endif /* USB_OTG_HS */
+#define LL_AHB1_GRP1_PERIPH_FLITF           RCC_AHB1LPENR_FLITFLPEN
+#define LL_AHB1_GRP1_PERIPH_SRAM1           RCC_AHB1LPENR_SRAM1LPEN
+#if defined(RCC_AHB1LPENR_SRAM2LPEN)
+#define LL_AHB1_GRP1_PERIPH_SRAM2           RCC_AHB1LPENR_SRAM2LPEN
+#endif /* RCC_AHB1LPENR_SRAM2LPEN */
+#if defined(RCC_AHB1LPENR_SRAM3LPEN)
+#define LL_AHB1_GRP1_PERIPH_SRAM3           RCC_AHB1LPENR_SRAM3LPEN
+#endif /* RCC_AHB1LPENR_SRAM3LPEN */
+/**
+  * @}
+  */
+
+#if defined(RCC_AHB2_SUPPORT)
+/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB2_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#if defined(DCMI)
+#define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN
+#endif /* DCMI */
+#if defined(CRYP)
+#define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN
+#endif /* CRYP */
+#if defined(AES)
+#define LL_AHB2_GRP1_PERIPH_AES            RCC_AHB2ENR_AESEN
+#endif /* AES */
+#if defined(HASH)
+#define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN
+#endif /* HASH */
+#if defined(RCC_AHB2ENR_RNGEN)
+#define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN
+#endif /* RCC_AHB2ENR_RNGEN */
+#if defined(USB_OTG_FS)
+#define LL_AHB2_GRP1_PERIPH_OTGFS          RCC_AHB2ENR_OTGFSEN
+#endif /* USB_OTG_FS */
+/**
+  * @}
+  */
+#endif /* RCC_AHB2_SUPPORT */
+
+#if defined(RCC_AHB3_SUPPORT)
+/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH
+  * @{
+  */
+#define LL_AHB3_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#if defined(FSMC_Bank1)
+#define LL_AHB3_GRP1_PERIPH_FSMC           RCC_AHB3ENR_FSMCEN
+#endif /* FSMC_Bank1 */
+#if defined(FMC_Bank1)
+#define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN
+#endif /* FMC_Bank1 */
+#if defined(QUADSPI)
+#define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN
+#endif /* QUADSPI */
+/**
+  * @}
+  */
+#endif /* RCC_AHB3_SUPPORT */
+
+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB1_GRP1_PERIPH_ALL            0xFFFFFFFFU
+#if defined(TIM2)
+#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN
+#endif /* TIM2 */
+#if defined(TIM3)
+#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN
+#endif /* TIM3 */
+#if defined(TIM4)
+#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1ENR_TIM4EN
+#endif /* TIM4 */
+#define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1ENR_TIM5EN
+#if defined(TIM6)
+#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN
+#endif /* TIM6 */
+#if defined(TIM7)
+#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN
+#endif /* TIM7 */
+#if defined(TIM12)
+#define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1ENR_TIM12EN
+#endif /* TIM12 */
+#if defined(TIM13)
+#define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1ENR_TIM13EN
+#endif /* TIM13 */
+#if defined(TIM14)
+#define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1ENR_TIM14EN
+#endif /* TIM14 */
+#if defined(LPTIM1)
+#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR_LPTIM1EN
+#endif /* LPTIM1 */
+#if defined(RCC_APB1ENR_RTCAPBEN)
+#define LL_APB1_GRP1_PERIPH_RTCAPB         RCC_APB1ENR_RTCAPBEN
+#endif /* RCC_APB1ENR_RTCAPBEN */
+#define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN
+#if defined(SPI2)
+#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN
+#endif /* SPI2 */
+#if defined(SPI3)
+#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1ENR_SPI3EN
+#endif /* SPI3 */
+#if defined(SPDIFRX)
+#define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1ENR_SPDIFRXEN
+#endif /* SPDIFRX */
+#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN
+#if defined(USART3)
+#define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1ENR_USART3EN
+#endif /* USART3 */
+#if defined(UART4)
+#define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1ENR_UART4EN
+#endif /* UART4 */
+#if defined(UART5)
+#define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1ENR_UART5EN
+#endif /* UART5 */
+#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN
+#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN
+#if defined(I2C3)
+#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR_I2C3EN
+#endif /* I2C3 */
+#if defined(FMPI2C1)
+#define LL_APB1_GRP1_PERIPH_FMPI2C1        RCC_APB1ENR_FMPI2C1EN
+#endif /* FMPI2C1 */
+#if defined(CAN1)
+#define LL_APB1_GRP1_PERIPH_CAN1           RCC_APB1ENR_CAN1EN
+#endif /* CAN1 */
+#if defined(CAN2)
+#define LL_APB1_GRP1_PERIPH_CAN2           RCC_APB1ENR_CAN2EN
+#endif /* CAN2 */
+#if defined(CAN3)
+#define LL_APB1_GRP1_PERIPH_CAN3           RCC_APB1ENR_CAN3EN
+#endif /* CAN3 */
+#if defined(CEC)
+#define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1ENR_CECEN
+#endif /* CEC */
+#define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN
+#if defined(DAC1)
+#define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN
+#endif /* DAC1 */
+#if defined(UART7)
+#define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1ENR_UART7EN
+#endif /* UART7 */
+#if defined(UART8)
+#define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1ENR_UART8EN
+#endif /* UART8 */
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH
+  * @{
+  */
+#define LL_APB2_GRP1_PERIPH_ALL          0xFFFFFFFFU
+#define LL_APB2_GRP1_PERIPH_TIM1         RCC_APB2ENR_TIM1EN
+#if defined(TIM8)
+#define LL_APB2_GRP1_PERIPH_TIM8         RCC_APB2ENR_TIM8EN
+#endif /* TIM8 */
+#define LL_APB2_GRP1_PERIPH_USART1       RCC_APB2ENR_USART1EN
+#if defined(USART6)
+#define LL_APB2_GRP1_PERIPH_USART6       RCC_APB2ENR_USART6EN
+#endif /* USART6 */
+#if defined(UART9)
+#define LL_APB2_GRP1_PERIPH_UART9        RCC_APB2ENR_UART9EN
+#endif /* UART9 */
+#if defined(UART10)
+#define LL_APB2_GRP1_PERIPH_UART10       RCC_APB2ENR_UART10EN
+#endif /* UART10 */
+#define LL_APB2_GRP1_PERIPH_ADC1         RCC_APB2ENR_ADC1EN
+#if defined(ADC2)
+#define LL_APB2_GRP1_PERIPH_ADC2         RCC_APB2ENR_ADC2EN
+#endif /* ADC2 */
+#if defined(ADC3)
+#define LL_APB2_GRP1_PERIPH_ADC3         RCC_APB2ENR_ADC3EN
+#endif /* ADC3 */
+#if defined(SDIO)
+#define LL_APB2_GRP1_PERIPH_SDIO         RCC_APB2ENR_SDIOEN
+#endif /* SDIO */
+#define LL_APB2_GRP1_PERIPH_SPI1         RCC_APB2ENR_SPI1EN
+#if defined(SPI4)
+#define LL_APB2_GRP1_PERIPH_SPI4         RCC_APB2ENR_SPI4EN
+#endif /* SPI4 */
+#define LL_APB2_GRP1_PERIPH_SYSCFG       RCC_APB2ENR_SYSCFGEN
+#if defined(RCC_APB2ENR_EXTITEN)
+#define LL_APB2_GRP1_PERIPH_EXTI         RCC_APB2ENR_EXTITEN
+#endif /* RCC_APB2ENR_EXTITEN */
+#define LL_APB2_GRP1_PERIPH_TIM9         RCC_APB2ENR_TIM9EN
+#if defined(TIM10)
+#define LL_APB2_GRP1_PERIPH_TIM10        RCC_APB2ENR_TIM10EN
+#endif /* TIM10 */
+#define LL_APB2_GRP1_PERIPH_TIM11        RCC_APB2ENR_TIM11EN
+#if defined(SPI5)
+#define LL_APB2_GRP1_PERIPH_SPI5         RCC_APB2ENR_SPI5EN
+#endif /* SPI5 */
+#if defined(SPI6)
+#define LL_APB2_GRP1_PERIPH_SPI6         RCC_APB2ENR_SPI6EN
+#endif /* SPI6 */
+#if defined(SAI1)
+#define LL_APB2_GRP1_PERIPH_SAI1         RCC_APB2ENR_SAI1EN
+#endif /* SAI1 */
+#if defined(SAI2)
+#define LL_APB2_GRP1_PERIPH_SAI2         RCC_APB2ENR_SAI2EN
+#endif /* SAI2 */
+#if defined(LTDC)
+#define LL_APB2_GRP1_PERIPH_LTDC         RCC_APB2ENR_LTDCEN
+#endif /* LTDC */
+#if defined(DSI)
+#define LL_APB2_GRP1_PERIPH_DSI          RCC_APB2ENR_DSIEN
+#endif /* DSI */
+#if defined(DFSDM1_Channel0)
+#define LL_APB2_GRP1_PERIPH_DFSDM1       RCC_APB2ENR_DFSDM1EN
+#endif /* DFSDM1_Channel0 */
+#if defined(DFSDM2_Channel0)
+#define LL_APB2_GRP1_PERIPH_DFSDM2       RCC_APB2ENR_DFSDM2EN
+#endif /* DFSDM2_Channel0 */
+#define LL_APB2_GRP1_PERIPH_ADC          RCC_APB2RSTR_ADCRST
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
+  * @{
+  */
+
+/** @defgroup BUS_LL_EF_AHB1 AHB1
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      CCMDATARAMEN       LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      RNGEN              LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_EnableClock\n
+  *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB1 peripheral clock is enabled or not
+  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      CCMDATARAMEN       LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      RNGEN              LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_IsEnabledClock\n
+  *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable AHB1 peripherals clock.
+  * @rmtoll AHB1ENR      GPIOAEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOBEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOCEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIODEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOEEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOFEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOGEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOHEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOIEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOJEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      GPIOKEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      CRCEN              LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      BKPSRAMEN          LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      CCMDATARAMEN       LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA1EN             LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2EN             LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      RNGEN              LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      DMA2DEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETHMACEN           LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETHMACTXEN         LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETHMACRXEN         LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      ETHMACPTPEN        LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      OTGHSEN            LL_AHB1_GRP1_DisableClock\n
+  *         AHB1ENR      OTGHSULPIEN        LL_AHB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CCMDATARAM (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB1 peripherals reset.
+  * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     RNGRST        LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ForceReset\n
+  *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB1 peripherals reset.
+  * @rmtoll AHB1RSTR     GPIOARST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOBRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOCRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIODRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOERST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOFRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOGRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOHRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOIRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOJRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     GPIOKRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     RNGRST        LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     DMA2DRST      LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     ETHMACRST     LL_AHB1_GRP1_ReleaseReset\n
+  *         AHB1RSTR     OTGHSRST      LL_AHB1_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB1 peripheral clocks in low-power mode
+  * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    SRAM3LPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    RNGLPEN        LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_EnableClockLowPower\n
+  *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB1LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB1 peripheral clocks in low-power mode
+  * @rmtoll AHB1LPENR    GPIOALPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOBLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOCLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIODLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOELPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOFLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOGLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOHLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOILPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOJLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    GPIOKLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    CRCLPEN        LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    FLITFLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    SRAM1LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    SRAM2LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    SRAM3LPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    BKPSRAMLPEN    LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    DMA1LPEN       LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    DMA2LPEN       LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    DMA2DLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    RNGLPEN        LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    ETHMACLPEN     LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    ETHMACTXLPEN   LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    ETHMACRXLPEN   LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    ETHMACPTPLPEN  LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    OTGHSLPEN      LL_AHB1_GRP1_DisableClockLowPower\n
+  *         AHB1LPENR    OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2 (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM3 (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS (*)
+  *         @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB1LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+#if defined(RCC_AHB2_SUPPORT)
+/** @defgroup BUS_LL_EF_AHB2 AHB2
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      AESEN        LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_EnableClock\n
+  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB2 peripheral clock is enabled or not
+  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      AESEN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_IsEnabledClock\n
+  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable AHB2 peripherals clock.
+  * @rmtoll AHB2ENR      DCMIEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      CRYPEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      AESEN        LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      HASHEN       LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      RNGEN        LL_AHB2_GRP1_DisableClock\n
+  *         AHB2ENR      OTGFSEN      LL_AHB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB2 peripherals reset.
+  * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ForceReset\n
+  *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB2 peripherals reset.
+  * @rmtoll AHB2RSTR     DCMIRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     CRYPRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     AESRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     HASHRST      LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     RNGRST       LL_AHB2_GRP1_ReleaseReset\n
+  *         AHB2RSTR     OTGFSRST     LL_AHB2_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB2 peripheral clocks in low-power mode
+  * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_EnableClockLowPower\n
+  *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB2 peripheral clocks in low-power mode
+  * @rmtoll AHB2LPENR    DCMILPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENR    CRYPLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENR    AESLPEN      LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENR    HASHLPEN     LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENR    RNGLPEN      LL_AHB2_GRP1_DisableClockLowPower\n
+  *         AHB2LPENR    OTGFSLPEN    LL_AHB2_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_AES  (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG (*)
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+#endif /* RCC_AHB2_SUPPORT */
+
+#if defined(RCC_AHB3_SUPPORT)
+/** @defgroup BUS_LL_EF_AHB3 AHB3
+  * @{
+  */
+
+/**
+  * @brief  Enable AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      FSMCEN        LL_AHB3_GRP1_EnableClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB3ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if AHB3 peripheral clock is enabled or not
+  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      FSMCEN        LL_AHB3_GRP1_IsEnabledClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable AHB3 peripherals clock.
+  * @rmtoll AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      FSMCEN        LL_AHB3_GRP1_DisableClock\n
+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3ENR, Periphs);
+}
+
+/**
+  * @brief  Force AHB3 peripherals reset.
+  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     FSMCRST       LL_AHB3_GRP1_ForceReset\n
+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Release AHB3 peripherals reset.
+  * @rmtoll AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     FSMCRST       LL_AHB3_GRP1_ReleaseReset\n
+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable AHB3 peripheral clocks in low-power mode
+  * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockLowPower\n
+  *         AHB3LPENR    FSMCLPEN      LL_AHB3_GRP1_EnableClockLowPower\n
+  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->AHB3LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable AHB3 peripheral clocks in low-power mode
+  * @rmtoll AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockLowPower\n
+  *         AHB3LPENR    FSMCLPEN      LL_AHB3_GRP1_DisableClockLowPower\n
+  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FSMC (*)
+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->AHB3LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+#endif /* RCC_AHB3_SUPPORT */
+
+/** @defgroup BUS_LL_EF_APB1 APB1
+  * @{
+  */
+
+/**
+  * @brief  Enable APB1 peripherals clock.
+  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM4EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM5EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM6EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM7EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM12EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM13EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     TIM14EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     WWDGEN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     SPI2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     SPI3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     USART2EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     USART3EN      LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     UART4EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     UART5EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     I2C1EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     I2C2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     I2C3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     FMPI2C1EN     LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     CAN1EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     CAN2EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     CAN3EN        LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     CECEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     PWREN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     DACEN         LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     UART7EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     UART8EN       LL_APB1_GRP1_EnableClock\n
+  *         APB1ENR     RTCAPBEN      LL_APB1_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC  (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB1 peripheral clock is enabled or not
+  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     FMPI2C1EN     LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     CAN1EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     CAN2EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     CAN3EN        LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     CECEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     PWREN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     DACEN         LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     UART8EN       LL_APB1_GRP1_IsEnabledClock\n
+  *         APB1ENR     RTCAPBEN      LL_APB1_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable APB1 peripherals clock.
+  * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM4EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM5EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM6EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM7EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM12EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM13EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     TIM14EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     WWDGEN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     SPI2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     SPI3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     USART2EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     USART3EN      LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     UART4EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     UART5EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     I2C1EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     I2C2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     I2C3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     FMPI2C1EN     LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     CAN1EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     CAN2EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     CAN3EN        LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     CECEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     PWREN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     DACEN         LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     UART7EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     UART8EN       LL_APB1_GRP1_DisableClock\n
+  *         APB1ENR     RTCAPBEN      LL_APB1_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB1 peripherals reset.
+  * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     USART2RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     USART3RST      LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     UART4RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     UART5RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     FMPI2C1RST     LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     CECRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     PWRRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     DACRST         LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     UART7RST       LL_APB1_GRP1_ForceReset\n
+  *         APB1RSTR     UART8RST       LL_APB1_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB1 peripherals reset.
+  * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM4RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM5RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM12RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM13RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     TIM14RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     SPI3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     SPDIFRXRST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     USART2RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     USART3RST      LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     UART4RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     UART5RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     FMPI2C1RST     LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     CAN1RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     CAN2RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     CAN3RST        LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     CECRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     PWRRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     DACRST         LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     UART7RST       LL_APB1_GRP1_ReleaseReset\n
+  *         APB1RSTR     UART8RST       LL_APB1_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB1 peripheral clocks in low-power mode
+  * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     FMPI2C1LPEN     LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     CECLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     DACLPEN         LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_EnableClockLowPower\n
+  *         APB1LPENR     RTCAPBLPEN      LL_APB1_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB1LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB1 peripheral clocks in low-power mode
+  * @rmtoll APB1LPENR     TIM2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM4LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM5LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM6LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM7LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM12LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM13LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     TIM14LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     LPTIM1LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     WWDGLPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     SPI2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     SPI3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     SPDIFRXLPEN     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     USART2LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     USART3LPEN      LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     UART4LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     UART5LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     I2C1LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     I2C2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     I2C3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     FMPI2C1LPEN     LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     CAN1LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     CAN2LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     CAN3LPEN        LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     CECLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     PWRLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     DACLPEN         LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     UART7LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     UART8LPEN       LL_APB1_GRP1_DisableClockLowPower\n
+  *         APB1LPENR     RTCAPBLPEN      LL_APB1_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2
+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_FMPI2C1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_PWR
+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8 (*)
+  *         @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB1LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup BUS_LL_EF_APB2 APB2
+  * @{
+  */
+
+/**
+  * @brief  Enable APB2 peripherals clock.
+  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     TIM8EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     USART1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     USART6EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     UART9EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     UART10EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     ADC1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     ADC2EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     ADC3EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SDIOEN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SPI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SPI4EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     EXTITEN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     TIM9EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     TIM10EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     TIM11EN       LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SPI5EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SPI6EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SAI1EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     SAI2EN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     LTDCEN        LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     DSIEN         LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_EnableClock\n
+  *         APB2ENR     DFSDM2EN      LL_APB2_GRP1_EnableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2ENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Check if APB2 peripheral clock is enabled or not
+  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     TIM8EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     USART1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     USART6EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     UART9EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     UART10EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     ADC1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     ADC2EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     ADC3EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SDIOEN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SPI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SPI4EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     EXTITEN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     TIM9EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     TIM10EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     TIM11EN       LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SPI5EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SPI6EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SAI1EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     SAI2EN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     LTDCEN        LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     DSIEN         LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\n
+  *         APB2ENR     DFSDM2EN      LL_APB2_GRP1_IsEnabledClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval State of Periphs (1 or 0).
+*/
+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
+{
+  return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
+}
+
+/**
+  * @brief  Disable APB2 peripherals clock.
+  * @rmtoll APB2ENR     TIM1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     TIM8EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     USART1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     USART6EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     UART9EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     UART10EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     ADC1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     ADC2EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     ADC3EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SDIOEN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SPI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SPI4EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SYSCFGEN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     EXTITEN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     TIM9EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     TIM10EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     TIM11EN       LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SPI5EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SPI6EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SAI1EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     SAI2EN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     LTDCEN        LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     DSIEN         LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     DFSDM1EN      LL_APB2_GRP1_DisableClock\n
+  *         APB2ENR     DFSDM2EN      LL_APB2_GRP1_DisableClock
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2ENR, Periphs);
+}
+
+/**
+  * @brief  Force APB2 peripherals reset.
+  * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     USART1RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     USART6RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     UART9RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     UART10RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     ADCRST         LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SDIORST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     DSIRST         LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ForceReset\n
+  *         APB2RSTR     DFSDM2RST      LL_APB2_GRP1_ForceReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
+{
+  SET_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Release APB2 peripherals reset.
+  * @rmtoll APB2RSTR     TIM1RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM8RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     USART1RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     USART6RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     UART9RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     UART10RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     ADCRST         LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SDIORST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI1RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI4RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SYSCFGRST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM9RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM10RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     TIM11RST       LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI5RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SPI6RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI1RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     SAI2RST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     LTDCRST        LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     DSIRST         LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     DFSDM1RST      LL_APB2_GRP1_ReleaseReset\n
+  *         APB2RSTR     DFSDM2RST      LL_APB2_GRP1_ReleaseReset
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ALL
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2RSTR, Periphs);
+}
+
+/**
+  * @brief  Enable APB2 peripheral clocks in low-power mode
+  * @rmtoll APB2LPENR     TIM1LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     TIM8LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     USART1LPEN      LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     USART6LPEN      LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     UART9LPEN       LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     UART10LPEN      LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     ADC1LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     ADC2LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     ADC3LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SDIOLPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SPI1LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SPI4LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SYSCFGLPEN      LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     EXTITLPEN       LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     TIM9LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     TIM10LPEN       LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     TIM11LPEN       LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SPI5LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SPI6LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SAI1LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     SAI2LPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     LTDCLPEN        LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     DFSDM1LPEN      LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_EnableClockLowPower\n
+  *         APB2LPENR     DFSDM2LPEN      LL_APB2_GRP1_EnableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
+{
+  __IO uint32_t tmpreg;
+  SET_BIT(RCC->APB2LPENR, Periphs);
+  /* Delay after an RCC peripheral clock enabling */
+  tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
+  (void)tmpreg;
+}
+
+/**
+  * @brief  Disable APB2 peripheral clocks in low-power mode
+  * @rmtoll APB2LPENR     TIM1LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     TIM8LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     USART1LPEN      LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     USART6LPEN      LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     UART9LPEN       LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     UART10LPEN      LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     ADC1LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     ADC2LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     ADC3LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SDIOLPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SPI1LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SPI4LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SYSCFGLPEN      LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     EXTITLPEN       LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     TIM9LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     TIM10LPEN       LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     TIM11LPEN       LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SPI5LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SPI6LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SAI1LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     SAI2LPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     LTDCLPEN        LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     DFSDM1LPEN      LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     DSILPEN         LL_APB2_GRP1_DisableClockLowPower\n
+  *         APB2LPENR     DFSDM2LPEN      LL_APB2_GRP1_DisableClockLowPower
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
+  *         @arg @ref LL_APB2_GRP1_PERIPH_EXTI (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM9
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM11
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DSI  (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+*/
+__STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
+{
+  CLEAR_BIT(RCC->APB2LPENR, Periphs);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_BUS_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h
index d478e13..4b11b73 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_cortex.h
@@ -1,637 +1,637 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_ll_cortex.h
-  * @author  MCD Application Team
-  * @brief   Header file of CORTEX LL module.
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The LL CORTEX driver contains a set of generic APIs that can be
-    used by user:
-      (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
-          functions
-      (+) Low power mode configuration (SCB register of Cortex-MCU)
-      (+) MPU API to configure and enable regions
-          (MPU services provided only on some devices)
-      (+) API to access to MCU info (CPUID register)
-      (+) API to enable fault handler (SHCSR accesses)
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_CORTEX_H
-#define __STM32F4xx_LL_CORTEX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_LL_Driver
-  * @{
-  */
-
-/** @defgroup CORTEX_LL CORTEX
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
-  * @{
-  */
-
-/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
-  * @{
-  */
-#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
-#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
-  * @{
-  */
-#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
-#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
-#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
-/**
-  * @}
-  */
-
-#if __MPU_PRESENT
-
-/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
-  * @{
-  */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
-#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
-#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
-#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
-  * @{
-  */
-#define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
-#define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
-#define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
-#define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
-#define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
-#define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
-#define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
-#define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
-  * @{
-  */
-#define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
-#define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
-  * @{
-  */
-#define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
-#define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
-#define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
-#define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
-#define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
-#define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
-  * @{
-  */
-#define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
-#define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
-#define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
-#define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
-  * @{
-  */
-#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
-#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
-  * @{
-  */
-#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
-#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
-  * @{
-  */
-#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
-#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
-  * @{
-  */
-#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
-#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
-/**
-  * @}
-  */
-#endif /* __MPU_PRESENT */
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
-  * @{
-  */
-
-/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
-  * @{
-  */
-
-/**
-  * @brief  This function checks if the Systick counter flag is active or not.
-  * @note   It can be used in timeout function on application side.
-  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
-{
-  return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
-}
-
-/**
-  * @brief  Configures the SysTick clock source
-  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
-{
-  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
-  {
-    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-  }
-  else
-  {
-    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-  }
-}
-
-/**
-  * @brief  Get the SysTick clock source
-  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
-  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
-  */
-__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
-{
-  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
-}
-
-/**
-  * @brief  Enable SysTick exception request
-  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
-{
-  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
-  * @brief  Disable SysTick exception request
-  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
-{
-  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
-  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
-  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
-{
-  return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
-  * @{
-  */
-
-/**
-  * @brief  Processor uses sleep as its low power mode
-  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableSleep(void)
-{
-  /* Clear SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
-  * @brief  Processor uses deep sleep as its low power mode
-  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
-{
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
-  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
-  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
-  *         empty main application.
-  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
-{
-  /* Set SLEEPONEXIT bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
-  * @brief  Do not sleep when returning to Thread mode.
-  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
-{
-  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
-  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
-  *         processor.
-  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
-{
-  /* Set SEVEONPEND bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
-  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
-  *         excluded
-  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
-  * @retval None
-  */
-__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
-{
-  /* Clear SEVEONPEND bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
-  * @{
-  */
-
-/**
-  * @brief  Enable a fault in System handler control register (SHCSR)
-  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
-  * @param  Fault This parameter can be a combination of the following values:
-  *         @arg @ref LL_HANDLER_FAULT_USG
-  *         @arg @ref LL_HANDLER_FAULT_BUS
-  *         @arg @ref LL_HANDLER_FAULT_MEM
-  * @retval None
-  */
-__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
-{
-  /* Enable the system handler fault */
-  SET_BIT(SCB->SHCSR, Fault);
-}
-
-/**
-  * @brief  Disable a fault in System handler control register (SHCSR)
-  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
-  * @param  Fault This parameter can be a combination of the following values:
-  *         @arg @ref LL_HANDLER_FAULT_USG
-  *         @arg @ref LL_HANDLER_FAULT_BUS
-  *         @arg @ref LL_HANDLER_FAULT_MEM
-  * @retval None
-  */
-__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
-{
-  /* Disable the system handler fault */
-  CLEAR_BIT(SCB->SHCSR, Fault);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
-  * @{
-  */
-
-/**
-  * @brief  Get Implementer code
-  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
-  * @retval Value should be equal to 0x41 for ARM
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
-}
-
-/**
-  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
-  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
-  * @retval Value between 0 and 255 (0x0: revision 0)
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
-}
-
-/**
-  * @brief  Get Constant number
-  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
-  * @retval Value should be equal to 0xF for Cortex-M4 devices
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
-}
-
-/**
-  * @brief  Get Part number
-  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
-  * @retval Value should be equal to 0xC24 for Cortex-M4
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
-}
-
-/**
-  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
-  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
-  * @retval Value between 0 and 255 (0x1: patch 1)
-  */
-__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
-{
-  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
-}
-
-/**
-  * @}
-  */
-
-#if __MPU_PRESENT
-/** @defgroup CORTEX_LL_EF_MPU MPU
-  * @{
-  */
-
-/**
-  * @brief  Enable MPU with input options
-  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
-  * @param  Options This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
-  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
-  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
-  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
-{
-  /* Enable the MPU*/
-  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
-  /* Ensure MPU settings take effects */
-  __DSB();
-  /* Sequence instruction fetches using update settings */
-  __ISB();
-}
-
-/**
-  * @brief  Disable MPU
-  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_Disable(void)
-{
-  /* Make sure outstanding transfers are done */
-  __DMB();
-  /* Disable MPU*/
-  WRITE_REG(MPU->CTRL, 0U);
-}
-
-/**
-  * @brief  Check if MPU is enabled or not
-  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
-{
-  return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
-}
-
-/**
-  * @brief  Enable a MPU region
-  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
-  * @param  Region This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_REGION_NUMBER0
-  *         @arg @ref LL_MPU_REGION_NUMBER1
-  *         @arg @ref LL_MPU_REGION_NUMBER2
-  *         @arg @ref LL_MPU_REGION_NUMBER3
-  *         @arg @ref LL_MPU_REGION_NUMBER4
-  *         @arg @ref LL_MPU_REGION_NUMBER5
-  *         @arg @ref LL_MPU_REGION_NUMBER6
-  *         @arg @ref LL_MPU_REGION_NUMBER7
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
-{
-  /* Set Region number */
-  WRITE_REG(MPU->RNR, Region);
-  /* Enable the MPU region */
-  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
-  * @brief  Configure and enable a region
-  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
-  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
-  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
-  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
-  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
-  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
-  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
-  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
-  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
-  * @param  Region This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_REGION_NUMBER0
-  *         @arg @ref LL_MPU_REGION_NUMBER1
-  *         @arg @ref LL_MPU_REGION_NUMBER2
-  *         @arg @ref LL_MPU_REGION_NUMBER3
-  *         @arg @ref LL_MPU_REGION_NUMBER4
-  *         @arg @ref LL_MPU_REGION_NUMBER5
-  *         @arg @ref LL_MPU_REGION_NUMBER6
-  *         @arg @ref LL_MPU_REGION_NUMBER7
-  * @param  Address Value of region base address
-  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
-  * @param  Attributes This parameter can be a combination of the following values:
-  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
-  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
-  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
-  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
-  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
-  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
-  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
-  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
-  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
-  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
-  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
-  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
-  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
-{
-  /* Set Region number */
-  WRITE_REG(MPU->RNR, Region);
-  /* Set base address */
-  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
-  /* Configure MPU */
-  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
-}
-
-/**
-  * @brief  Disable a region
-  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
-  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
-  * @param  Region This parameter can be one of the following values:
-  *         @arg @ref LL_MPU_REGION_NUMBER0
-  *         @arg @ref LL_MPU_REGION_NUMBER1
-  *         @arg @ref LL_MPU_REGION_NUMBER2
-  *         @arg @ref LL_MPU_REGION_NUMBER3
-  *         @arg @ref LL_MPU_REGION_NUMBER4
-  *         @arg @ref LL_MPU_REGION_NUMBER5
-  *         @arg @ref LL_MPU_REGION_NUMBER6
-  *         @arg @ref LL_MPU_REGION_NUMBER7
-  * @retval None
-  */
-__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
-{
-  /* Set Region number */
-  WRITE_REG(MPU->RNR, Region);
-  /* Disable the MPU region */
-  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
-}
-
-/**
-  * @}
-  */
-
-#endif /* __MPU_PRESENT */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_LL_CORTEX_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_cortex.h
+  * @author  MCD Application Team
+  * @brief   Header file of CORTEX LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL CORTEX driver contains a set of generic APIs that can be
+    used by user:
+      (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
+          functions
+      (+) Low power mode configuration (SCB register of Cortex-MCU)
+      (+) MPU API to configure and enable regions
+          (MPU services provided only on some devices)
+      (+) API to access to MCU info (CPUID register)
+      (+) API to enable fault handler (SHCSR accesses)
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_CORTEX_H
+#define __STM32F4xx_LL_CORTEX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX_LL CORTEX
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
+  * @{
+  */
+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
+#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
+  * @{
+  */
+#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
+#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
+#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+
+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
+  * @{
+  */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
+#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
+#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
+  * @{
+  */
+#define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
+#define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
+#define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
+#define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
+#define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
+#define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
+#define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
+#define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
+  * @{
+  */
+#define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
+#define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
+  * @{
+  */
+#define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
+#define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
+#define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
+#define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
+#define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
+#define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
+  * @{
+  */
+#define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
+#define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
+#define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
+#define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
+  * @{
+  */
+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
+#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
+#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
+  * @{
+  */
+#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
+#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
+  * @{
+  */
+
+/**
+  * @brief  This function checks if the Systick counter flag is active or not.
+  * @note   It can be used in timeout function on application side.
+  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
+{
+  return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
+}
+
+/**
+  * @brief  Configures the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
+{
+  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
+  {
+    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+  }
+  else
+  {
+    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+  }
+}
+
+/**
+  * @brief  Get the SysTick clock source
+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
+{
+  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
+}
+
+/**
+  * @brief  Enable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
+{
+  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Disable SysTick exception request
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
+{
+  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+}
+
+/**
+  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
+{
+  return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
+  * @{
+  */
+
+/**
+  * @brief  Processor uses sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleep(void)
+{
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+  * @brief  Processor uses deep sleep as its low power mode
+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
+{
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+}
+
+/**
+  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
+  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
+  *         empty main application.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief  Do not sleep when returning to Thread mode.
+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
+  *         processor.
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
+{
+  /* Set SEVEONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
+  *         excluded
+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
+{
+  /* Clear SEVEONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
+  * @{
+  */
+
+/**
+  * @brief  Enable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
+{
+  /* Enable the system handler fault */
+  SET_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @brief  Disable a fault in System handler control register (SHCSR)
+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
+  * @param  Fault This parameter can be a combination of the following values:
+  *         @arg @ref LL_HANDLER_FAULT_USG
+  *         @arg @ref LL_HANDLER_FAULT_BUS
+  *         @arg @ref LL_HANDLER_FAULT_MEM
+  * @retval None
+  */
+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
+{
+  /* Disable the system handler fault */
+  CLEAR_BIT(SCB->SHCSR, Fault);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
+  * @{
+  */
+
+/**
+  * @brief  Get Implementer code
+  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
+  * @retval Value should be equal to 0x41 for ARM
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
+}
+
+/**
+  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
+  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
+  * @retval Value between 0 and 255 (0x0: revision 0)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
+}
+
+/**
+  * @brief  Get Constant number
+  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
+  * @retval Value should be equal to 0xF for Cortex-M4 devices
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
+}
+
+/**
+  * @brief  Get Part number
+  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
+  * @retval Value should be equal to 0xC24 for Cortex-M4
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
+}
+
+/**
+  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
+  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
+  * @retval Value between 0 and 255 (0x1: patch 1)
+  */
+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
+{
+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
+}
+
+/**
+  * @}
+  */
+
+#if __MPU_PRESENT
+/** @defgroup CORTEX_LL_EF_MPU MPU
+  * @{
+  */
+
+/**
+  * @brief  Enable MPU with input options
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
+  * @param  Options This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
+  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
+  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
+{
+  /* Enable the MPU*/
+  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
+  /* Ensure MPU settings take effects */
+  __DSB();
+  /* Sequence instruction fetches using update settings */
+  __ISB();
+}
+
+/**
+  * @brief  Disable MPU
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+  /* Disable MPU*/
+  WRITE_REG(MPU->CTRL, 0U);
+}
+
+/**
+  * @brief  Check if MPU is enabled or not
+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
+{
+  return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
+}
+
+/**
+  * @brief  Enable a MPU region
+  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Enable the MPU region */
+  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @brief  Configure and enable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
+  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
+  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
+  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
+  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @param  Address Value of region base address
+  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
+  * @param  Attributes This parameter can be a combination of the following values:
+  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
+  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
+  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
+  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
+  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
+  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
+  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
+  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
+  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
+  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
+  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
+  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
+  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Set base address */
+  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
+  /* Configure MPU */
+  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
+}
+
+/**
+  * @brief  Disable a region
+  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
+  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
+  * @param  Region This parameter can be one of the following values:
+  *         @arg @ref LL_MPU_REGION_NUMBER0
+  *         @arg @ref LL_MPU_REGION_NUMBER1
+  *         @arg @ref LL_MPU_REGION_NUMBER2
+  *         @arg @ref LL_MPU_REGION_NUMBER3
+  *         @arg @ref LL_MPU_REGION_NUMBER4
+  *         @arg @ref LL_MPU_REGION_NUMBER5
+  *         @arg @ref LL_MPU_REGION_NUMBER6
+  *         @arg @ref LL_MPU_REGION_NUMBER7
+  * @retval None
+  */
+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
+{
+  /* Set Region number */
+  WRITE_REG(MPU->RNR, Region);
+  /* Disable the MPU region */
+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
+}
+
+/**
+  * @}
+  */
+
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_CORTEX_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h
index 76444fc..c04ac76 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_dma.h
@@ -1,2868 +1,2868 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_ll_dma.h
-  * @author  MCD Application Team
-  * @brief   Header file of DMA LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_DMA_H
-#define __STM32F4xx_LL_DMA_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_LL_Driver
-  * @{
-  */
-
-#if defined (DMA1) || defined (DMA2)
-
-/** @defgroup DMA_LL DMA
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup DMA_LL_Private_Variables DMA Private Variables
-  * @{
-  */
-/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
-static const uint8_t STREAM_OFFSET_TAB[] =
-{
-  (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
-  (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
-};
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup DMA_LL_Private_Constants DMA Private Constants
-  * @{
-  */
-/**
-  * @}
-  */
-
-
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
-  * @{
-  */
-typedef struct
-{
-  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
-                                        or as Source base address in case of memory to memory transfer direction.
-
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
-  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
-                                        or as Destination base address in case of memory to memory transfer direction.
-
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
-
-  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
-                                        from memory to memory or from peripheral to memory.
-                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
-
-  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
-                                        This parameter can be a value of @ref DMA_LL_EC_MODE
-                                        @note The circular buffer mode cannot be used if the memory to memory
-                                              data transfer direction is configured on the selected Stream
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
-
-  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
-                                        is incremented or not.
-                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
-
-  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
-                                        is incremented or not.
-                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
-
-  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
-                                        in case of memory to memory transfer direction.
-                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
-
-  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
-                                        in case of memory to memory transfer direction.
-                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
-
-  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
-                                        The data unit is equal to the source buffer configuration set in PeripheralSize
-                                        or MemorySize parameters depending in the transfer direction.
-                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
-
-  uint32_t Channel;                /*!< Specifies the peripheral channel.
-                                        This parameter can be a value of @ref DMA_LL_EC_CHANNEL
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
-
-  uint32_t Priority;               /*!< Specifies the channel priority level.
-                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
-                                        
-  uint32_t FIFOMode;               /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
-                                        This parameter can be a value of @ref DMA_LL_FIFOMODE
-                                        @note The Direct mode (FIFO mode disabled) cannot be used if the 
-                                        memory-to-memory data transfer is configured on the selected stream
-
-                                        This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
-
-  uint32_t FIFOThreshold;          /*!< Specifies the FIFO threshold level.
-                                        This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
-
-  uint32_t MemBurst;               /*!< Specifies the Burst transfer configuration for the memory transfers. 
-                                        It specifies the amount of data to be transferred in a single non interruptible
-                                        transaction.
-                                        This parameter can be a value of @ref DMA_LL_EC_MBURST 
-                                        @note The burst mode is possible only if the address Increment mode is enabled. 
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
-
-  uint32_t PeriphBurst;            /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
-                                        It specifies the amount of data to be transferred in a single non interruptible 
-                                        transaction. 
-                                        This parameter can be a value of @ref DMA_LL_EC_PBURST
-                                        @note The burst mode is possible only if the address Increment mode is enabled. 
-
-                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
-
-} LL_DMA_InitTypeDef;
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
-  * @{
-  */
-
-/** @defgroup DMA_LL_EC_STREAM STREAM
-  * @{
-  */
-#define LL_DMA_STREAM_0                   0x00000000U
-#define LL_DMA_STREAM_1                   0x00000001U
-#define LL_DMA_STREAM_2                   0x00000002U
-#define LL_DMA_STREAM_3                   0x00000003U
-#define LL_DMA_STREAM_4                   0x00000004U
-#define LL_DMA_STREAM_5                   0x00000005U
-#define LL_DMA_STREAM_6                   0x00000006U
-#define LL_DMA_STREAM_7                   0x00000007U
-#define LL_DMA_STREAM_ALL                 0xFFFF0000U
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
-  * @{
-  */
-#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U               /*!< Peripheral to memory direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0            /*!< Memory to peripheral direction */
-#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1            /*!< Memory to memory direction     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_MODE MODE
-  * @{
-  */
-#define LL_DMA_MODE_NORMAL                0x00000000U               /*!< Normal Mode                  */
-#define LL_DMA_MODE_CIRCULAR              DMA_SxCR_CIRC             /*!< Circular Mode                */
-#define LL_DMA_MODE_PFCTRL                DMA_SxCR_PFCTRL           /*!< Peripheral flow control mode */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE
-  * @{
-  */
-#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U               /*!< Disable double buffering mode */
-#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE   DMA_SxCR_DBM              /*!< Enable double buffering mode  */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PERIPH PERIPH
-  * @{
-  */
-#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U               /*!< Peripheral increment mode Disable */
-#define LL_DMA_PERIPH_INCREMENT           DMA_SxCR_PINC             /*!< Peripheral increment mode Enable  */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_MEMORY MEMORY
-  * @{
-  */
-#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U               /*!< Memory increment mode Disable */
-#define LL_DMA_MEMORY_INCREMENT           DMA_SxCR_MINC             /*!< Memory increment mode Enable  */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
-  * @{
-  */
-#define LL_DMA_PDATAALIGN_BYTE            0x00000000U               /*!< Peripheral data alignment : Byte     */
-#define LL_DMA_PDATAALIGN_HALFWORD        DMA_SxCR_PSIZE_0          /*!< Peripheral data alignment : HalfWord */
-#define LL_DMA_PDATAALIGN_WORD            DMA_SxCR_PSIZE_1          /*!< Peripheral data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
-  * @{
-  */
-#define LL_DMA_MDATAALIGN_BYTE            0x00000000U               /*!< Memory data alignment : Byte     */
-#define LL_DMA_MDATAALIGN_HALFWORD        DMA_SxCR_MSIZE_0          /*!< Memory data alignment : HalfWord */
-#define LL_DMA_MDATAALIGN_WORD            DMA_SxCR_MSIZE_1          /*!< Memory data alignment : Word     */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
-  * @{
-  */
-#define LL_DMA_OFFSETSIZE_PSIZE           0x00000000U               /*!< Peripheral increment offset size is linked to the PSIZE */
-#define LL_DMA_OFFSETSIZE_FIXEDTO4        DMA_SxCR_PINCOS           /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
-  * @{
-  */
-#define LL_DMA_PRIORITY_LOW               0x00000000U               /*!< Priority level : Low       */
-#define LL_DMA_PRIORITY_MEDIUM            DMA_SxCR_PL_0             /*!< Priority level : Medium    */
-#define LL_DMA_PRIORITY_HIGH              DMA_SxCR_PL_1             /*!< Priority level : High      */
-#define LL_DMA_PRIORITY_VERYHIGH          DMA_SxCR_PL               /*!< Priority level : Very_High */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
-  * @{
-  */
-#define LL_DMA_CHANNEL_0                  0x00000000U                                                                   /* Select Channel0 of DMA Instance */
-#define LL_DMA_CHANNEL_1                  DMA_SxCR_CHSEL_0                                                              /* Select Channel1 of DMA Instance */
-#define LL_DMA_CHANNEL_2                  DMA_SxCR_CHSEL_1                                                              /* Select Channel2 of DMA Instance */
-#define LL_DMA_CHANNEL_3                  (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1)                                         /* Select Channel3 of DMA Instance */
-#define LL_DMA_CHANNEL_4                  DMA_SxCR_CHSEL_2                                                              /* Select Channel4 of DMA Instance */
-#define LL_DMA_CHANNEL_5                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0)                                         /* Select Channel5 of DMA Instance */
-#define LL_DMA_CHANNEL_6                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1)                                         /* Select Channel6 of DMA Instance */
-#define LL_DMA_CHANNEL_7                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0)                      /* Select Channel7 of DMA Instance */
-#if defined (DMA_SxCR_CHSEL_3)
-#define LL_DMA_CHANNEL_8                  DMA_SxCR_CHSEL_3                                                              /* Select Channel8 of DMA Instance */
-#define LL_DMA_CHANNEL_9                  (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0)                                         /* Select Channel9 of DMA Instance */
-#define LL_DMA_CHANNEL_10                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1)                                         /* Select Channel10 of DMA Instance */
-#define LL_DMA_CHANNEL_11                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0)                      /* Select Channel11 of DMA Instance */
-#define LL_DMA_CHANNEL_12                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2)                                         /* Select Channel12 of DMA Instance */
-#define LL_DMA_CHANNEL_13                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0)                      /* Select Channel13 of DMA Instance */
-#define LL_DMA_CHANNEL_14                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1)                      /* Select Channel14 of DMA Instance */
-#define LL_DMA_CHANNEL_15                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0)   /* Select Channel15 of DMA Instance */
-#endif /* DMA_SxCR_CHSEL_3 */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_MBURST MBURST
-  * @{
-  */
-#define LL_DMA_MBURST_SINGLE              0x00000000U                             /*!< Memory burst single transfer configuration */
-#define LL_DMA_MBURST_INC4                DMA_SxCR_MBURST_0                       /*!< Memory burst of 4 beats transfer configuration */
-#define LL_DMA_MBURST_INC8                DMA_SxCR_MBURST_1                       /*!< Memory burst of 8 beats transfer configuration */
-#define LL_DMA_MBURST_INC16               (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_PBURST PBURST
-  * @{
-  */
-#define LL_DMA_PBURST_SINGLE              0x00000000U                             /*!< Peripheral burst single transfer configuration */
-#define LL_DMA_PBURST_INC4                DMA_SxCR_PBURST_0                       /*!< Peripheral burst of 4 beats transfer configuration */
-#define LL_DMA_PBURST_INC8                DMA_SxCR_PBURST_1                       /*!< Peripheral burst of 8 beats transfer configuration */
-#define LL_DMA_PBURST_INC16               (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
-/**
-  * @}
-  */
-  
-/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
-  * @{
-  */
-#define LL_DMA_FIFOMODE_DISABLE           0x00000000U                             /*!< FIFO mode disable (direct mode is enabled) */
-#define LL_DMA_FIFOMODE_ENABLE            DMA_SxFCR_DMDIS                         /*!< FIFO mode enable  */
-/**
-  * @}
-  */  
-
-/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
-  * @{
-  */
-#define LL_DMA_FIFOSTATUS_0_25            0x00000000U                             /*!< 0 < fifo_level < 1/4    */
-#define LL_DMA_FIFOSTATUS_25_50           DMA_SxFCR_FS_0                          /*!< 1/4 < fifo_level < 1/2  */
-#define LL_DMA_FIFOSTATUS_50_75           DMA_SxFCR_FS_1                          /*!< 1/2 < fifo_level < 3/4  */
-#define LL_DMA_FIFOSTATUS_75_100          (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)       /*!< 3/4 < fifo_level < full */
-#define LL_DMA_FIFOSTATUS_EMPTY           DMA_SxFCR_FS_2                          /*!< FIFO is empty           */
-#define LL_DMA_FIFOSTATUS_FULL            (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)       /*!< FIFO is full            */
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
-  * @{
-  */
-#define LL_DMA_FIFOTHRESHOLD_1_4          0x00000000U                             /*!< FIFO threshold 1 quart full configuration  */
-#define LL_DMA_FIFOTHRESHOLD_1_2          DMA_SxFCR_FTH_0                         /*!< FIFO threshold half full configuration     */
-#define LL_DMA_FIFOTHRESHOLD_3_4          DMA_SxFCR_FTH_1                         /*!< FIFO threshold 3 quarts full configuration */
-#define LL_DMA_FIFOTHRESHOLD_FULL         DMA_SxFCR_FTH                           /*!< FIFO threshold full configuration          */
-/**
-  * @}
-  */
-    
-/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
-  * @{
-  */
-#define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             /*!< Set CurrentTarget Memory to Memory 0  */
-#define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             /*!< Set CurrentTarget Memory to Memory 1  */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
-  * @{
-  */
-
-/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
-  * @{
-  */
-/**
-  * @brief  Write a value in DMA register
-  * @param  __INSTANCE__ DMA Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in DMA register
-  * @param  __INSTANCE__ DMA Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
-  * @{
-  */
-/**
-  * @brief  Convert DMAx_Streamy into DMAx
-  * @param  __STREAM_INSTANCE__ DMAx_Streamy
-  * @retval DMAx
-  */
-#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__)   \
-(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ?  DMA2 : DMA1)
-
-/**
-  * @brief  Convert DMAx_Streamy into LL_DMA_STREAM_y
-  * @param  __STREAM_INSTANCE__ DMAx_Streamy
-  * @retval LL_DMA_CHANNEL_y
-  */
-#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)   \
-(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
- ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
- LL_DMA_STREAM_7)
-
-/**
-  * @brief  Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
-  * @param  __DMA_INSTANCE__ DMAx
-  * @param  __STREAM__ LL_DMA_STREAM_y
-  * @retval DMAx_Streamy
-  */
-#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)   \
-((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
- (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
- DMA2_Stream7)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
- /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
-  * @{
-  */
-
-/** @defgroup DMA_LL_EF_Configuration Configuration
-  * @{
-  */
-/**
-  * @brief Enable DMA stream.
-  * @rmtoll CR          EN            LL_DMA_EnableStream
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
-}
-
-/**
-  * @brief Disable DMA stream.
-  * @rmtoll CR          EN            LL_DMA_DisableStream
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
-}
-
-/**
-  * @brief Check if DMA stream is enabled or disabled.
-  * @rmtoll CR          EN            LL_DMA_IsEnabledStream
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
-}
-
-/**
-  * @brief  Configure all parameters linked to DMA transfer.
-  * @rmtoll CR          DIR           LL_DMA_ConfigTransfer\n
-  *         CR          CIRC          LL_DMA_ConfigTransfer\n
-  *         CR          PINC          LL_DMA_ConfigTransfer\n
-  *         CR          MINC          LL_DMA_ConfigTransfer\n
-  *         CR          PSIZE         LL_DMA_ConfigTransfer\n
-  *         CR          MSIZE         LL_DMA_ConfigTransfer\n
-  *         CR          PL            LL_DMA_ConfigTransfer\n
-  *         CR          PFCTRL        LL_DMA_ConfigTransfer
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Configuration This parameter must be a combination of all the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR  or @ref LL_DMA_MODE_PFCTRL
-  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
-  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
-  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
-  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
-  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
-  *@retval None
-  */
-__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
-{
-  MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
-             DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
-             Configuration);
-}
-
-/**
-  * @brief Set Data transfer direction (read from peripheral or from memory).
-  * @rmtoll CR          DIR           LL_DMA_SetDataTransferDirection
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Direction)
-{
-  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
-}
-
-/**
-  * @brief Get Data transfer direction (read from peripheral or from memory).
-  * @rmtoll CR          DIR           LL_DMA_GetDataTransferDirection
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
-}
-
-/**
-  * @brief Set DMA mode normal, circular or peripheral flow control.
-  * @rmtoll CR          CIRC           LL_DMA_SetMode\n
-  *         CR          PFCTRL         LL_DMA_SetMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MODE_NORMAL
-  *         @arg @ref LL_DMA_MODE_CIRCULAR
-  *         @arg @ref LL_DMA_MODE_PFCTRL
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
-{
-  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
-}
-
-/**
-  * @brief Get DMA mode normal, circular or peripheral flow control.
-  * @rmtoll CR          CIRC           LL_DMA_GetMode\n
-  *         CR          PFCTRL         LL_DMA_GetMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MODE_NORMAL
-  *         @arg @ref LL_DMA_MODE_CIRCULAR
-  *         @arg @ref LL_DMA_MODE_PFCTRL
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
-}
-
-/**
-  * @brief Set Peripheral increment mode.
-  * @rmtoll CR          PINC           LL_DMA_SetPeriphIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  IncrementMode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
-  *         @arg @ref LL_DMA_PERIPH_INCREMENT
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
-{
-  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
-}
-
-/**
-  * @brief Get Peripheral increment mode.
-  * @rmtoll CR          PINC           LL_DMA_GetPeriphIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
-  *         @arg @ref LL_DMA_PERIPH_INCREMENT
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
-}
-
-/**
-  * @brief Set Memory increment mode.
-  * @rmtoll CR          MINC           LL_DMA_SetMemoryIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  IncrementMode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
-  *         @arg @ref LL_DMA_MEMORY_INCREMENT
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
-{
-  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
-}
-
-/**
-  * @brief Get Memory increment mode.
-  * @rmtoll CR          MINC           LL_DMA_GetMemoryIncMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
-  *         @arg @ref LL_DMA_MEMORY_INCREMENT
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
-}
-
-/**
-  * @brief Set Peripheral size.
-  * @rmtoll CR          PSIZE           LL_DMA_SetPeriphSize
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Size This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_PDATAALIGN_WORD
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
-{
-  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
-}
-
-/**
-  * @brief Get Peripheral size.
-  * @rmtoll CR          PSIZE           LL_DMA_GetPeriphSize
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_PDATAALIGN_WORD
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
-}
-
-/**
-  * @brief Set Memory size.
-  * @rmtoll CR          MSIZE           LL_DMA_SetMemorySize
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Size This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_MDATAALIGN_WORD
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
-{
-  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
-}
-
-/**
-  * @brief Get Memory size.
-  * @rmtoll CR          MSIZE           LL_DMA_GetMemorySize
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
-  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
-  *         @arg @ref LL_DMA_MDATAALIGN_WORD
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
-}
-
-/**
-  * @brief Set Peripheral increment offset size.
-  * @rmtoll CR          PINCOS           LL_DMA_SetIncOffsetSize
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  OffsetSize This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
-  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
-{
-  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
-}
-
-/**
-  * @brief Get Peripheral increment offset size.
-  * @rmtoll CR          PINCOS           LL_DMA_GetIncOffsetSize
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
-  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
-}
-
-/**
-  * @brief Set Stream priority level.
-  * @rmtoll CR          PL           LL_DMA_SetStreamPriorityLevel
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Priority This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PRIORITY_LOW
-  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
-  *         @arg @ref LL_DMA_PRIORITY_HIGH
-  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Priority)
-{
-  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
-}
-
-/**
-  * @brief Get Stream priority level.
-  * @rmtoll CR          PL           LL_DMA_GetStreamPriorityLevel
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PRIORITY_LOW
-  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
-  *         @arg @ref LL_DMA_PRIORITY_HIGH
-  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
-}
-
-/**
-  * @brief Set Number of data to transfer.
-  * @rmtoll NDTR          NDT           LL_DMA_SetDataLength
-  * @note   This action has no effect if
-  *         stream is enabled.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  NbData Between 0 to 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
-{
-  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
-}
-
-/**
-  * @brief Get Number of data to transfer.
-  * @rmtoll NDTR          NDT           LL_DMA_GetDataLength
-  * @note   Once the stream is enabled, the return value indicate the
-  *         remaining bytes to be transmitted.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Between 0 to 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
-}
-
-/**
-  * @brief Select Channel number associated to the Stream.
-  * @rmtoll CR          CHSEL           LL_DMA_SetChannelSelection
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Channel This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_0
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
-{
-  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
-}
-
-/**
-  * @brief Get the Channel number associated to the Stream.
-  * @rmtoll CR          CHSEL           LL_DMA_GetChannelSelection
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_CHANNEL_0
-  *         @arg @ref LL_DMA_CHANNEL_1
-  *         @arg @ref LL_DMA_CHANNEL_2
-  *         @arg @ref LL_DMA_CHANNEL_3
-  *         @arg @ref LL_DMA_CHANNEL_4
-  *         @arg @ref LL_DMA_CHANNEL_5
-  *         @arg @ref LL_DMA_CHANNEL_6
-  *         @arg @ref LL_DMA_CHANNEL_7
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
-}
-
-/**
-  * @brief Set Memory burst transfer configuration.
-  * @rmtoll CR          MBURST           LL_DMA_SetMemoryBurstxfer
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Mburst This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_MBURST_SINGLE
-  *         @arg @ref LL_DMA_MBURST_INC4
-  *         @arg @ref LL_DMA_MBURST_INC8
-  *         @arg @ref LL_DMA_MBURST_INC16
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
-{
-  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
-}
-
-/**
-  * @brief Get Memory burst transfer configuration.
-  * @rmtoll CR          MBURST           LL_DMA_GetMemoryBurstxfer
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_MBURST_SINGLE
-  *         @arg @ref LL_DMA_MBURST_INC4
-  *         @arg @ref LL_DMA_MBURST_INC8
-  *         @arg @ref LL_DMA_MBURST_INC16
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
-}
-
-/**
-  * @brief Set  Peripheral burst transfer configuration.
-  * @rmtoll CR          PBURST           LL_DMA_SetPeriphBurstxfer
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Pburst This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_PBURST_SINGLE
-  *         @arg @ref LL_DMA_PBURST_INC4
-  *         @arg @ref LL_DMA_PBURST_INC8
-  *         @arg @ref LL_DMA_PBURST_INC16
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
-{
-  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
-}
-
-/**
-  * @brief Get Peripheral burst transfer configuration.
-  * @rmtoll CR          PBURST           LL_DMA_GetPeriphBurstxfer
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_PBURST_SINGLE
-  *         @arg @ref LL_DMA_PBURST_INC4
-  *         @arg @ref LL_DMA_PBURST_INC8
-  *         @arg @ref LL_DMA_PBURST_INC16
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
-}
-
-/**
-  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
-  * @rmtoll CR          CT           LL_DMA_SetCurrentTargetMem 
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param CurrentMemory This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_CURRENTTARGETMEM0
-  *         @arg @ref LL_DMA_CURRENTTARGETMEM1
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
-{
-   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
-}
-
-/**
-  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
-  * @rmtoll CR          CT           LL_DMA_GetCurrentTargetMem 
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_CURRENTTARGETMEM0
-  *         @arg @ref LL_DMA_CURRENTTARGETMEM1
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
-}
-
-/**
-  * @brief Enable the double buffer mode.
-  * @rmtoll CR          DBM           LL_DMA_EnableDoubleBufferMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
-}
-
-/**
-  * @brief Disable the double buffer mode.
-  * @rmtoll CR          DBM           LL_DMA_DisableDoubleBufferMode 
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
-}
-
-/**
-  * @brief Get FIFO status.
-  * @rmtoll FCR          FS          LL_DMA_GetFIFOStatus
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_FIFOSTATUS_0_25
-  *         @arg @ref LL_DMA_FIFOSTATUS_25_50
-  *         @arg @ref LL_DMA_FIFOSTATUS_50_75
-  *         @arg @ref LL_DMA_FIFOSTATUS_75_100
-  *         @arg @ref LL_DMA_FIFOSTATUS_EMPTY
-  *         @arg @ref LL_DMA_FIFOSTATUS_FULL
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
-}
-
-/**
-  * @brief Disable Fifo mode.
-  * @rmtoll FCR          DMDIS          LL_DMA_DisableFifoMode
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
-}
-
-/**
-  * @brief Enable Fifo mode.
-  * @rmtoll FCR          DMDIS          LL_DMA_EnableFifoMode 
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
-}
-
-/**
-  * @brief Select FIFO threshold.
-  * @rmtoll FCR         FTH          LL_DMA_SetFIFOThreshold
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Threshold This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
-{
-  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
-}
-
-/**
-  * @brief Get FIFO threshold.
-  * @rmtoll FCR         FTH          LL_DMA_GetFIFOThreshold
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
-}
-
-/**
-  * @brief Configure the FIFO .
-  * @rmtoll FCR         FTH          LL_DMA_ConfigFifo\n
-  *         FCR         DMDIS        LL_DMA_ConfigFifo
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  FifoMode This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_FIFOMODE_ENABLE
-  *         @arg @ref LL_DMA_FIFOMODE_DISABLE
-  * @param  FifoThreshold This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
-  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
-{
-  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold);
-}
-
-/**
-  * @brief Configure the Source and Destination addresses.
-  * @note   This API must not be called when the DMA stream is enabled.
-  * @rmtoll M0AR        M0A         LL_DMA_ConfigAddresses\n 
-  *         PAR         PA          LL_DMA_ConfigAddresses
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  SrcAddress Between 0 to 0xFFFFFFFF
-  * @param  DstAddress Between 0 to 0xFFFFFFFF
-  * @param  Direction This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
-  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
-{
-  /* Direction Memory to Periph */
-  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
-  {
-    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
-    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
-  }
-  /* Direction Periph to Memory and Memory to Memory */
-  else
-  {
-    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
-    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
-  }
-}
-
-/**
-  * @brief  Set the Memory address.
-  * @rmtoll M0AR        M0A         LL_DMA_SetMemoryAddress
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
-{
-  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
-}
-
-/**
-  * @brief  Set the Peripheral address.
-  * @rmtoll PAR        PA         LL_DMA_SetPeriphAddress
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  PeriphAddress Between 0 to 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
-{
-  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
-}
-
-/**
-  * @brief  Get the Memory address.
-  * @rmtoll M0AR        M0A         LL_DMA_GetMemoryAddress
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Between 0 to 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
-{
-  return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
-}
-
-/**
-  * @brief  Get the Peripheral address.
-  * @rmtoll PAR        PA         LL_DMA_GetPeriphAddress
-  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Between 0 to 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
-{
-  return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
-}
-
-/**
-  * @brief  Set the Memory to Memory Source address.
-  * @rmtoll PAR        PA         LL_DMA_SetM2MSrcAddress
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
-{
-  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
-}
-
-/**
-  * @brief  Set the Memory to Memory Destination address.
-  * @rmtoll M0AR        M0A         LL_DMA_SetM2MDstAddress
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @note   This API must not be called when the DMA channel is enabled.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
-  {
-    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
-  }
-
-/**
-  * @brief  Get the Memory to Memory Source address.
-  * @rmtoll PAR        PA         LL_DMA_GetM2MSrcAddress
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Between 0 to 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
-  {
-   return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
-  }
-
-/**
-  * @brief  Get the Memory to Memory Destination address.
-  * @rmtoll M0AR        M0A         LL_DMA_GetM2MDstAddress
-  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Between 0 to 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
-{
- return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
-}
-
-/**
-  * @brief Set Memory 1 address (used in case of Double buffer mode).
-  * @rmtoll M1AR        M1A         LL_DMA_SetMemory1Address
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @param  Address Between 0 to 0xFFFFFFFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
-{
-  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
-}
-
-/**
-  * @brief Get Memory 1 address (used in case of Double buffer mode).
-  * @rmtoll M1AR        M1A         LL_DMA_GetMemory1Address
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval Between 0 to 0xFFFFFFFF
-  */
-__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief Get Stream 0 half transfer flag.
-  * @rmtoll LISR  HTIF0    LL_DMA_IsActiveFlag_HT0
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
-}
-
-/**
-  * @brief Get Stream 1 half transfer flag.
-  * @rmtoll LISR  HTIF1    LL_DMA_IsActiveFlag_HT1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
-}
-
-/**
-  * @brief Get Stream 2 half transfer flag.
-  * @rmtoll LISR  HTIF2    LL_DMA_IsActiveFlag_HT2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
-}
-
-/**
-  * @brief Get Stream 3 half transfer flag.
-  * @rmtoll LISR  HTIF3    LL_DMA_IsActiveFlag_HT3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
-}
-
-/**
-  * @brief Get Stream 4 half transfer flag.
-  * @rmtoll HISR  HTIF4    LL_DMA_IsActiveFlag_HT4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
-}
-
-/**
-  * @brief Get Stream 5 half transfer flag.
-  * @rmtoll HISR  HTIF0    LL_DMA_IsActiveFlag_HT5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
-}
-
-/**
-  * @brief Get Stream 6 half transfer flag.
-  * @rmtoll HISR  HTIF6    LL_DMA_IsActiveFlag_HT6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
-}
-
-/**
-  * @brief Get Stream 7 half transfer flag.
-  * @rmtoll HISR  HTIF7    LL_DMA_IsActiveFlag_HT7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
-} 
-
-/**
-  * @brief Get Stream 0 transfer complete flag.
-  * @rmtoll LISR  TCIF0    LL_DMA_IsActiveFlag_TC0
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
-}
-
-/**
-  * @brief Get Stream 1 transfer complete flag.
-  * @rmtoll LISR  TCIF1    LL_DMA_IsActiveFlag_TC1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
-}
-
-/**
-  * @brief Get Stream 2 transfer complete flag.
-  * @rmtoll LISR  TCIF2    LL_DMA_IsActiveFlag_TC2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
-}
-
-/**
-  * @brief Get Stream 3 transfer complete flag.
-  * @rmtoll LISR  TCIF3    LL_DMA_IsActiveFlag_TC3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
-}
-
-/**
-  * @brief Get Stream 4 transfer complete flag.
-  * @rmtoll HISR  TCIF4    LL_DMA_IsActiveFlag_TC4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
-}
-
-/**
-  * @brief Get Stream 5 transfer complete flag.
-  * @rmtoll HISR  TCIF0    LL_DMA_IsActiveFlag_TC5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
-}
-
-/**
-  * @brief Get Stream 6 transfer complete flag.
-  * @rmtoll HISR  TCIF6    LL_DMA_IsActiveFlag_TC6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
-}
-
-/**
-  * @brief Get Stream 7 transfer complete flag.
-  * @rmtoll HISR  TCIF7    LL_DMA_IsActiveFlag_TC7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
-} 
-
-/**
-  * @brief Get Stream 0 transfer error flag.
-  * @rmtoll LISR  TEIF0    LL_DMA_IsActiveFlag_TE0
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
-}
-
-/**
-  * @brief Get Stream 1 transfer error flag.
-  * @rmtoll LISR  TEIF1    LL_DMA_IsActiveFlag_TE1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
-}
-
-/**
-  * @brief Get Stream 2 transfer error flag.
-  * @rmtoll LISR  TEIF2    LL_DMA_IsActiveFlag_TE2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
-}
-
-/**
-  * @brief Get Stream 3 transfer error flag.
-  * @rmtoll LISR  TEIF3    LL_DMA_IsActiveFlag_TE3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
-}
-
-/**
-  * @brief Get Stream 4 transfer error flag.
-  * @rmtoll HISR  TEIF4    LL_DMA_IsActiveFlag_TE4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
-}
-
-/**
-  * @brief Get Stream 5 transfer error flag.
-  * @rmtoll HISR  TEIF0    LL_DMA_IsActiveFlag_TE5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
-}
-
-/**
-  * @brief Get Stream 6 transfer error flag.
-  * @rmtoll HISR  TEIF6    LL_DMA_IsActiveFlag_TE6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
-}
-
-/**
-  * @brief Get Stream 7 transfer error flag.
-  * @rmtoll HISR  TEIF7    LL_DMA_IsActiveFlag_TE7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
-} 
-
-/**
-  * @brief Get Stream 0 direct mode error flag.
-  * @rmtoll LISR  DMEIF0    LL_DMA_IsActiveFlag_DME0
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
-}
-
-/**
-  * @brief Get Stream 1 direct mode error flag.
-  * @rmtoll LISR  DMEIF1    LL_DMA_IsActiveFlag_DME1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
-}
-
-/**
-  * @brief Get Stream 2 direct mode error flag.
-  * @rmtoll LISR  DMEIF2    LL_DMA_IsActiveFlag_DME2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
-}
-
-/**
-  * @brief Get Stream 3 direct mode error flag.
-  * @rmtoll LISR  DMEIF3    LL_DMA_IsActiveFlag_DME3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
-}
-
-/**
-  * @brief Get Stream 4 direct mode error flag.
-  * @rmtoll HISR  DMEIF4    LL_DMA_IsActiveFlag_DME4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
-}
-
-/**
-  * @brief Get Stream 5 direct mode error flag.
-  * @rmtoll HISR  DMEIF0    LL_DMA_IsActiveFlag_DME5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
-}
-
-/**
-  * @brief Get Stream 6 direct mode error flag.
-  * @rmtoll HISR  DMEIF6    LL_DMA_IsActiveFlag_DME6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
-}
-
-/**
-  * @brief Get Stream 7 direct mode error flag.
-  * @rmtoll HISR  DMEIF7    LL_DMA_IsActiveFlag_DME7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
-}
-
-/**
-  * @brief Get Stream 0 FIFO error flag.
-  * @rmtoll LISR  FEIF0    LL_DMA_IsActiveFlag_FE0
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
-}
-
-/**
-  * @brief Get Stream 1 FIFO error flag.
-  * @rmtoll LISR  FEIF1    LL_DMA_IsActiveFlag_FE1
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
-}
-
-/**
-  * @brief Get Stream 2 FIFO error flag.
-  * @rmtoll LISR  FEIF2    LL_DMA_IsActiveFlag_FE2
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
-}
-
-/**
-  * @brief Get Stream 3 FIFO error flag.
-  * @rmtoll LISR  FEIF3    LL_DMA_IsActiveFlag_FE3
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
-}
-
-/**
-  * @brief Get Stream 4 FIFO error flag.
-  * @rmtoll HISR  FEIF4    LL_DMA_IsActiveFlag_FE4
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
-}
-
-/**
-  * @brief Get Stream 5 FIFO error flag.
-  * @rmtoll HISR  FEIF0    LL_DMA_IsActiveFlag_FE5
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
-}
-
-/**
-  * @brief Get Stream 6 FIFO error flag.
-  * @rmtoll HISR  FEIF6    LL_DMA_IsActiveFlag_FE6
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
-}
-
-/**
-  * @brief Get Stream 7 FIFO error flag.
-  * @rmtoll HISR  FEIF7    LL_DMA_IsActiveFlag_FE7
-  * @param  DMAx DMAx Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
-{
-  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
-}
-
-/**
-  * @brief Clear Stream 0 half transfer flag.
-  * @rmtoll LIFCR  CHTIF0    LL_DMA_ClearFlag_HT0
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
-}
-
-/**
-  * @brief Clear Stream 1 half transfer flag.
-  * @rmtoll LIFCR  CHTIF1    LL_DMA_ClearFlag_HT1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
-}
-
-/**
-  * @brief Clear Stream 2 half transfer flag.
-  * @rmtoll LIFCR  CHTIF2    LL_DMA_ClearFlag_HT2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
-}
-
-/**
-  * @brief Clear Stream 3 half transfer flag.
-  * @rmtoll LIFCR  CHTIF3    LL_DMA_ClearFlag_HT3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
-}
-
-/**
-  * @brief Clear Stream 4 half transfer flag.
-  * @rmtoll HIFCR  CHTIF4    LL_DMA_ClearFlag_HT4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
-}
-
-/**
-  * @brief Clear Stream 5 half transfer flag.
-  * @rmtoll HIFCR  CHTIF5    LL_DMA_ClearFlag_HT5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
-}
-
-/**
-  * @brief Clear Stream 6 half transfer flag.
-  * @rmtoll HIFCR  CHTIF6    LL_DMA_ClearFlag_HT6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
-}
-
-/**
-  * @brief Clear Stream 7 half transfer flag.
-  * @rmtoll HIFCR  CHTIF7    LL_DMA_ClearFlag_HT7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
-}
-
-/**
-  * @brief Clear Stream 0 transfer complete flag.
-  * @rmtoll LIFCR  CTCIF0    LL_DMA_ClearFlag_TC0
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
-}
-
-/**
-  * @brief Clear Stream 1 transfer complete flag.
-  * @rmtoll LIFCR  CTCIF1    LL_DMA_ClearFlag_TC1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
-}
-
-/**
-  * @brief Clear Stream 2 transfer complete flag.
-  * @rmtoll LIFCR  CTCIF2    LL_DMA_ClearFlag_TC2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
-}
-
-/**
-  * @brief Clear Stream 3 transfer complete flag.
-  * @rmtoll LIFCR  CTCIF3    LL_DMA_ClearFlag_TC3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
-}
-
-/**
-  * @brief Clear Stream 4 transfer complete flag.
-  * @rmtoll HIFCR  CTCIF4    LL_DMA_ClearFlag_TC4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
-}
-
-/**
-  * @brief Clear Stream 5 transfer complete flag.
-  * @rmtoll HIFCR  CTCIF5    LL_DMA_ClearFlag_TC5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
-}
-
-/**
-  * @brief Clear Stream 6 transfer complete flag.
-  * @rmtoll HIFCR  CTCIF6    LL_DMA_ClearFlag_TC6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
-}
-
-/**
-  * @brief Clear Stream 7 transfer complete flag.
-  * @rmtoll HIFCR  CTCIF7    LL_DMA_ClearFlag_TC7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
-}
-
-/**
-  * @brief Clear Stream 0 transfer error flag.
-  * @rmtoll LIFCR  CTEIF0    LL_DMA_ClearFlag_TE0
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
-}
-
-/**
-  * @brief Clear Stream 1 transfer error flag.
-  * @rmtoll LIFCR  CTEIF1    LL_DMA_ClearFlag_TE1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
-}
-
-/**
-  * @brief Clear Stream 2 transfer error flag.
-  * @rmtoll LIFCR  CTEIF2    LL_DMA_ClearFlag_TE2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
-}
-
-/**
-  * @brief Clear Stream 3 transfer error flag.
-  * @rmtoll LIFCR  CTEIF3    LL_DMA_ClearFlag_TE3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
-}
-
-/**
-  * @brief Clear Stream 4 transfer error flag.
-  * @rmtoll HIFCR  CTEIF4    LL_DMA_ClearFlag_TE4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
-}
-
-/**
-  * @brief Clear Stream 5 transfer error flag.
-  * @rmtoll HIFCR  CTEIF5    LL_DMA_ClearFlag_TE5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
-}
-
-/**
-  * @brief Clear Stream 6 transfer error flag.
-  * @rmtoll HIFCR  CTEIF6    LL_DMA_ClearFlag_TE6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
-}
-
-/**
-  * @brief Clear Stream 7 transfer error flag.
-  * @rmtoll HIFCR  CTEIF7    LL_DMA_ClearFlag_TE7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
-}
-
-/**
-  * @brief Clear Stream 0 direct mode error flag.
-  * @rmtoll LIFCR  CDMEIF0    LL_DMA_ClearFlag_DME0
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
-}
-
-/**
-  * @brief Clear Stream 1 direct mode error flag.
-  * @rmtoll LIFCR  CDMEIF1    LL_DMA_ClearFlag_DME1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
-}
-
-/**
-  * @brief Clear Stream 2 direct mode error flag.
-  * @rmtoll LIFCR  CDMEIF2    LL_DMA_ClearFlag_DME2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
-}
-
-/**
-  * @brief Clear Stream 3 direct mode error flag.
-  * @rmtoll LIFCR  CDMEIF3    LL_DMA_ClearFlag_DME3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
-}
-
-/**
-  * @brief Clear Stream 4 direct mode error flag.
-  * @rmtoll HIFCR  CDMEIF4    LL_DMA_ClearFlag_DME4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
-}
-
-/**
-  * @brief Clear Stream 5 direct mode error flag.
-  * @rmtoll HIFCR  CDMEIF5    LL_DMA_ClearFlag_DME5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
-}
-
-/**
-  * @brief Clear Stream 6 direct mode error flag.
-  * @rmtoll HIFCR  CDMEIF6    LL_DMA_ClearFlag_DME6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
-}
-
-/**
-  * @brief Clear Stream 7 direct mode error flag.
-  * @rmtoll HIFCR  CDMEIF7    LL_DMA_ClearFlag_DME7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
-}
-
-/**
-  * @brief Clear Stream 0 FIFO error flag.
-  * @rmtoll LIFCR  CFEIF0    LL_DMA_ClearFlag_FE0
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
-}
-
-/**
-  * @brief Clear Stream 1 FIFO error flag.
-  * @rmtoll LIFCR  CFEIF1    LL_DMA_ClearFlag_FE1
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
-}
-
-/**
-  * @brief Clear Stream 2 FIFO error flag.
-  * @rmtoll LIFCR  CFEIF2    LL_DMA_ClearFlag_FE2
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
-}
-
-/**
-  * @brief Clear Stream 3 FIFO error flag.
-  * @rmtoll LIFCR  CFEIF3    LL_DMA_ClearFlag_FE3
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
-}
-
-/**
-  * @brief Clear Stream 4 FIFO error flag.
-  * @rmtoll HIFCR  CFEIF4    LL_DMA_ClearFlag_FE4
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
-}
-
-/**
-  * @brief Clear Stream 5 FIFO error flag.
-  * @rmtoll HIFCR  CFEIF5    LL_DMA_ClearFlag_FE5
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
-}
-
-/**
-  * @brief Clear Stream 6 FIFO error flag.
-  * @rmtoll HIFCR  CFEIF6    LL_DMA_ClearFlag_FE6
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
-}
-
-/**
-  * @brief Clear Stream 7 FIFO error flag.
-  * @rmtoll HIFCR  CFEIF7    LL_DMA_ClearFlag_FE7
-  * @param  DMAx DMAx Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
-{
-  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief Enable Half transfer interrupt.
-  * @rmtoll CR        HTIE         LL_DMA_EnableIT_HT
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
-}
-
-/**
-  * @brief Enable Transfer error interrupt.
-  * @rmtoll CR        TEIE         LL_DMA_EnableIT_TE
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
-}
-
-/**
-  * @brief Enable Transfer complete interrupt.
-  * @rmtoll CR        TCIE         LL_DMA_EnableIT_TC
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
-}
-
-/**
-  * @brief Enable Direct mode error interrupt.
-  * @rmtoll CR        DMEIE         LL_DMA_EnableIT_DME
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
-}
-
-/**
-  * @brief Enable FIFO error interrupt.
-  * @rmtoll FCR        FEIE         LL_DMA_EnableIT_FE
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
-}
-
-/**
-  * @brief Disable Half transfer interrupt.
-  * @rmtoll CR        HTIE         LL_DMA_DisableIT_HT
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
-}
-
-/**
-  * @brief Disable Transfer error interrupt.
-  * @rmtoll CR        TEIE         LL_DMA_DisableIT_TE
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
-}
-
-/**
-  * @brief Disable Transfer complete interrupt.
-  * @rmtoll CR        TCIE         LL_DMA_DisableIT_TC
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
-}
-
-/**
-  * @brief Disable Direct mode error interrupt.
-  * @rmtoll CR        DMEIE         LL_DMA_DisableIT_DME
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
-}
-
-/**
-  * @brief Disable FIFO error interrupt.
-  * @rmtoll FCR        FEIE         LL_DMA_DisableIT_FE
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
-}
-
-/**
-  * @brief Check if Half transfer interrupt is enabled.
-  * @rmtoll CR        HTIE         LL_DMA_IsEnabledIT_HT
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
-}
-
-/**
-  * @brief Check if Transfer error nterrup is enabled.
-  * @rmtoll CR        TEIE         LL_DMA_IsEnabledIT_TE
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
-}
-
-/**
-  * @brief Check if Transfer complete interrupt is enabled.
-  * @rmtoll CR        TCIE         LL_DMA_IsEnabledIT_TC
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
-}
-
-/**
-  * @brief Check if Direct mode error interrupt is enabled.
-  * @rmtoll CR        DMEIE         LL_DMA_IsEnabledIT_DME
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
-}
-
-/**
-  * @brief Check if FIFO error interrupt is enabled.
-  * @rmtoll FCR        FEIE         LL_DMA_IsEnabledIT_FE
-  * @param  DMAx DMAx Instance
-  * @param  Stream This parameter can be one of the following values:
-  *         @arg @ref LL_DMA_STREAM_0
-  *         @arg @ref LL_DMA_STREAM_1
-  *         @arg @ref LL_DMA_STREAM_2
-  *         @arg @ref LL_DMA_STREAM_3
-  *         @arg @ref LL_DMA_STREAM_4
-  *         @arg @ref LL_DMA_STREAM_5
-  *         @arg @ref LL_DMA_STREAM_6
-  *         @arg @ref LL_DMA_STREAM_7
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
-{
-  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
-uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
-void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* DMA1 || DMA2 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_LL_DMA_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_dma.h
+  * @author  MCD Application Team
+  * @brief   Header file of DMA LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_DMA_H
+#define __STM32F4xx_LL_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined (DMA1) || defined (DMA2)
+
+/** @defgroup DMA_LL DMA
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Variables DMA Private Variables
+  * @{
+  */
+/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
+static const uint8_t STREAM_OFFSET_TAB[] =
+{
+  (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
+  (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
+};
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DMA_LL_Private_Constants DMA Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
+  * @{
+  */
+typedef struct
+{
+  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer
+                                        or as Source base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer
+                                        or as Destination base address in case of memory to memory transfer direction.
+
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
+
+  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,
+                                        from memory to memory or from peripheral to memory.
+                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
+
+  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.
+                                        This parameter can be a value of @ref DMA_LL_EC_MODE
+                                        @note The circular buffer mode cannot be used if the memory to memory
+                                              data transfer direction is configured on the selected Stream
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
+
+  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
+
+  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
+                                        is incremented or not.
+                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
+
+  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
+
+  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
+                                        in case of memory to memory transfer direction.
+                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
+
+  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.
+                                        The data unit is equal to the source buffer configuration set in PeripheralSize
+                                        or MemorySize parameters depending in the transfer direction.
+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
+
+  uint32_t Channel;                /*!< Specifies the peripheral channel.
+                                        This parameter can be a value of @ref DMA_LL_EC_CHANNEL
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
+
+  uint32_t Priority;               /*!< Specifies the channel priority level.
+                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
+                                        
+  uint32_t FIFOMode;               /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
+                                        This parameter can be a value of @ref DMA_LL_FIFOMODE
+                                        @note The Direct mode (FIFO mode disabled) cannot be used if the 
+                                        memory-to-memory data transfer is configured on the selected stream
+
+                                        This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
+
+  uint32_t FIFOThreshold;          /*!< Specifies the FIFO threshold level.
+                                        This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
+
+  uint32_t MemBurst;               /*!< Specifies the Burst transfer configuration for the memory transfers. 
+                                        It specifies the amount of data to be transferred in a single non interruptible
+                                        transaction.
+                                        This parameter can be a value of @ref DMA_LL_EC_MBURST 
+                                        @note The burst mode is possible only if the address Increment mode is enabled. 
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
+
+  uint32_t PeriphBurst;            /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
+                                        It specifies the amount of data to be transferred in a single non interruptible 
+                                        transaction. 
+                                        This parameter can be a value of @ref DMA_LL_EC_PBURST
+                                        @note The burst mode is possible only if the address Increment mode is enabled. 
+
+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
+
+} LL_DMA_InitTypeDef;
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA_LL_EC_STREAM STREAM
+  * @{
+  */
+#define LL_DMA_STREAM_0                   0x00000000U
+#define LL_DMA_STREAM_1                   0x00000001U
+#define LL_DMA_STREAM_2                   0x00000002U
+#define LL_DMA_STREAM_3                   0x00000003U
+#define LL_DMA_STREAM_4                   0x00000004U
+#define LL_DMA_STREAM_5                   0x00000005U
+#define LL_DMA_STREAM_6                   0x00000006U
+#define LL_DMA_STREAM_7                   0x00000007U
+#define LL_DMA_STREAM_ALL                 0xFFFF0000U
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DIRECTION DIRECTION
+  * @{
+  */
+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U               /*!< Peripheral to memory direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0            /*!< Memory to peripheral direction */
+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1            /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MODE MODE
+  * @{
+  */
+#define LL_DMA_MODE_NORMAL                0x00000000U               /*!< Normal Mode                  */
+#define LL_DMA_MODE_CIRCULAR              DMA_SxCR_CIRC             /*!< Circular Mode                */
+#define LL_DMA_MODE_PFCTRL                DMA_SxCR_PFCTRL           /*!< Peripheral flow control mode */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE
+  * @{
+  */
+#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U               /*!< Disable double buffering mode */
+#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE   DMA_SxCR_DBM              /*!< Enable double buffering mode  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PERIPH PERIPH
+  * @{
+  */
+#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U               /*!< Peripheral increment mode Disable */
+#define LL_DMA_PERIPH_INCREMENT           DMA_SxCR_PINC             /*!< Peripheral increment mode Enable  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MEMORY MEMORY
+  * @{
+  */
+#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U               /*!< Memory increment mode Disable */
+#define LL_DMA_MEMORY_INCREMENT           DMA_SxCR_MINC             /*!< Memory increment mode Enable  */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
+  * @{
+  */
+#define LL_DMA_PDATAALIGN_BYTE            0x00000000U               /*!< Peripheral data alignment : Byte     */
+#define LL_DMA_PDATAALIGN_HALFWORD        DMA_SxCR_PSIZE_0          /*!< Peripheral data alignment : HalfWord */
+#define LL_DMA_PDATAALIGN_WORD            DMA_SxCR_PSIZE_1          /*!< Peripheral data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
+  * @{
+  */
+#define LL_DMA_MDATAALIGN_BYTE            0x00000000U               /*!< Memory data alignment : Byte     */
+#define LL_DMA_MDATAALIGN_HALFWORD        DMA_SxCR_MSIZE_0          /*!< Memory data alignment : HalfWord */
+#define LL_DMA_MDATAALIGN_WORD            DMA_SxCR_MSIZE_1          /*!< Memory data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
+  * @{
+  */
+#define LL_DMA_OFFSETSIZE_PSIZE           0x00000000U               /*!< Peripheral increment offset size is linked to the PSIZE */
+#define LL_DMA_OFFSETSIZE_FIXEDTO4        DMA_SxCR_PINCOS           /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PRIORITY PRIORITY
+  * @{
+  */
+#define LL_DMA_PRIORITY_LOW               0x00000000U               /*!< Priority level : Low       */
+#define LL_DMA_PRIORITY_MEDIUM            DMA_SxCR_PL_0             /*!< Priority level : Medium    */
+#define LL_DMA_PRIORITY_HIGH              DMA_SxCR_PL_1             /*!< Priority level : High      */
+#define LL_DMA_PRIORITY_VERYHIGH          DMA_SxCR_PL               /*!< Priority level : Very_High */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
+  * @{
+  */
+#define LL_DMA_CHANNEL_0                  0x00000000U                                                                   /* Select Channel0 of DMA Instance */
+#define LL_DMA_CHANNEL_1                  DMA_SxCR_CHSEL_0                                                              /* Select Channel1 of DMA Instance */
+#define LL_DMA_CHANNEL_2                  DMA_SxCR_CHSEL_1                                                              /* Select Channel2 of DMA Instance */
+#define LL_DMA_CHANNEL_3                  (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1)                                         /* Select Channel3 of DMA Instance */
+#define LL_DMA_CHANNEL_4                  DMA_SxCR_CHSEL_2                                                              /* Select Channel4 of DMA Instance */
+#define LL_DMA_CHANNEL_5                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0)                                         /* Select Channel5 of DMA Instance */
+#define LL_DMA_CHANNEL_6                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1)                                         /* Select Channel6 of DMA Instance */
+#define LL_DMA_CHANNEL_7                  (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0)                      /* Select Channel7 of DMA Instance */
+#if defined (DMA_SxCR_CHSEL_3)
+#define LL_DMA_CHANNEL_8                  DMA_SxCR_CHSEL_3                                                              /* Select Channel8 of DMA Instance */
+#define LL_DMA_CHANNEL_9                  (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0)                                         /* Select Channel9 of DMA Instance */
+#define LL_DMA_CHANNEL_10                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1)                                         /* Select Channel10 of DMA Instance */
+#define LL_DMA_CHANNEL_11                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0)                      /* Select Channel11 of DMA Instance */
+#define LL_DMA_CHANNEL_12                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2)                                         /* Select Channel12 of DMA Instance */
+#define LL_DMA_CHANNEL_13                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0)                      /* Select Channel13 of DMA Instance */
+#define LL_DMA_CHANNEL_14                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1)                      /* Select Channel14 of DMA Instance */
+#define LL_DMA_CHANNEL_15                 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0)   /* Select Channel15 of DMA Instance */
+#endif /* DMA_SxCR_CHSEL_3 */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_MBURST MBURST
+  * @{
+  */
+#define LL_DMA_MBURST_SINGLE              0x00000000U                             /*!< Memory burst single transfer configuration */
+#define LL_DMA_MBURST_INC4                DMA_SxCR_MBURST_0                       /*!< Memory burst of 4 beats transfer configuration */
+#define LL_DMA_MBURST_INC8                DMA_SxCR_MBURST_1                       /*!< Memory burst of 8 beats transfer configuration */
+#define LL_DMA_MBURST_INC16               (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_PBURST PBURST
+  * @{
+  */
+#define LL_DMA_PBURST_SINGLE              0x00000000U                             /*!< Peripheral burst single transfer configuration */
+#define LL_DMA_PBURST_INC4                DMA_SxCR_PBURST_0                       /*!< Peripheral burst of 4 beats transfer configuration */
+#define LL_DMA_PBURST_INC8                DMA_SxCR_PBURST_1                       /*!< Peripheral burst of 8 beats transfer configuration */
+#define LL_DMA_PBURST_INC16               (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
+/**
+  * @}
+  */
+  
+/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
+  * @{
+  */
+#define LL_DMA_FIFOMODE_DISABLE           0x00000000U                             /*!< FIFO mode disable (direct mode is enabled) */
+#define LL_DMA_FIFOMODE_ENABLE            DMA_SxFCR_DMDIS                         /*!< FIFO mode enable  */
+/**
+  * @}
+  */  
+
+/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
+  * @{
+  */
+#define LL_DMA_FIFOSTATUS_0_25            0x00000000U                             /*!< 0 < fifo_level < 1/4    */
+#define LL_DMA_FIFOSTATUS_25_50           DMA_SxFCR_FS_0                          /*!< 1/4 < fifo_level < 1/2  */
+#define LL_DMA_FIFOSTATUS_50_75           DMA_SxFCR_FS_1                          /*!< 1/2 < fifo_level < 3/4  */
+#define LL_DMA_FIFOSTATUS_75_100          (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)       /*!< 3/4 < fifo_level < full */
+#define LL_DMA_FIFOSTATUS_EMPTY           DMA_SxFCR_FS_2                          /*!< FIFO is empty           */
+#define LL_DMA_FIFOSTATUS_FULL            (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)       /*!< FIFO is full            */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
+  * @{
+  */
+#define LL_DMA_FIFOTHRESHOLD_1_4          0x00000000U                             /*!< FIFO threshold 1 quart full configuration  */
+#define LL_DMA_FIFOTHRESHOLD_1_2          DMA_SxFCR_FTH_0                         /*!< FIFO threshold half full configuration     */
+#define LL_DMA_FIFOTHRESHOLD_3_4          DMA_SxFCR_FTH_1                         /*!< FIFO threshold 3 quarts full configuration */
+#define LL_DMA_FIFOTHRESHOLD_FULL         DMA_SxFCR_FTH                           /*!< FIFO threshold full configuration          */
+/**
+  * @}
+  */
+    
+/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
+  * @{
+  */
+#define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             /*!< Set CurrentTarget Memory to Memory 0  */
+#define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             /*!< Set CurrentTarget Memory to Memory 1  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
+  * @{
+  */
+/**
+  * @brief  Write a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DMA register
+  * @param  __INSTANCE__ DMA Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
+  * @{
+  */
+/**
+  * @brief  Convert DMAx_Streamy into DMAx
+  * @param  __STREAM_INSTANCE__ DMAx_Streamy
+  * @retval DMAx
+  */
+#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__)   \
+(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ?  DMA2 : DMA1)
+
+/**
+  * @brief  Convert DMAx_Streamy into LL_DMA_STREAM_y
+  * @param  __STREAM_INSTANCE__ DMAx_Streamy
+  * @retval LL_DMA_CHANNEL_y
+  */
+#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)   \
+(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
+ LL_DMA_STREAM_7)
+
+/**
+  * @brief  Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
+  * @param  __DMA_INSTANCE__ DMAx
+  * @param  __STREAM__ LL_DMA_STREAM_y
+  * @retval DMAx_Streamy
+  */
+#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)   \
+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
+ DMA2_Stream7)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+ /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
+  * @{
+  */
+
+/** @defgroup DMA_LL_EF_Configuration Configuration
+  * @{
+  */
+/**
+  * @brief Enable DMA stream.
+  * @rmtoll CR          EN            LL_DMA_EnableStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
+}
+
+/**
+  * @brief Disable DMA stream.
+  * @rmtoll CR          EN            LL_DMA_DisableStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
+}
+
+/**
+  * @brief Check if DMA stream is enabled or disabled.
+  * @rmtoll CR          EN            LL_DMA_IsEnabledStream
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
+}
+
+/**
+  * @brief  Configure all parameters linked to DMA transfer.
+  * @rmtoll CR          DIR           LL_DMA_ConfigTransfer\n
+  *         CR          CIRC          LL_DMA_ConfigTransfer\n
+  *         CR          PINC          LL_DMA_ConfigTransfer\n
+  *         CR          MINC          LL_DMA_ConfigTransfer\n
+  *         CR          PSIZE         LL_DMA_ConfigTransfer\n
+  *         CR          MSIZE         LL_DMA_ConfigTransfer\n
+  *         CR          PL            LL_DMA_ConfigTransfer\n
+  *         CR          PFCTRL        LL_DMA_ConfigTransfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR  or @ref LL_DMA_MODE_PFCTRL
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
+  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
+  *@retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
+             DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
+             Configuration);
+}
+
+/**
+  * @brief Set Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CR          DIR           LL_DMA_SetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Direction)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
+}
+
+/**
+  * @brief Get Data transfer direction (read from peripheral or from memory).
+  * @rmtoll CR          DIR           LL_DMA_GetDataTransferDirection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
+}
+
+/**
+  * @brief Set DMA mode normal, circular or peripheral flow control.
+  * @rmtoll CR          CIRC           LL_DMA_SetMode\n
+  *         CR          PFCTRL         LL_DMA_SetMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  *         @arg @ref LL_DMA_MODE_PFCTRL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
+}
+
+/**
+  * @brief Get DMA mode normal, circular or peripheral flow control.
+  * @rmtoll CR          CIRC           LL_DMA_GetMode\n
+  *         CR          PFCTRL         LL_DMA_GetMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MODE_NORMAL
+  *         @arg @ref LL_DMA_MODE_CIRCULAR
+  *         @arg @ref LL_DMA_MODE_PFCTRL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
+}
+
+/**
+  * @brief Set Peripheral increment mode.
+  * @rmtoll CR          PINC           LL_DMA_SetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  IncrementMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
+}
+
+/**
+  * @brief Get Peripheral increment mode.
+  * @rmtoll CR          PINC           LL_DMA_GetPeriphIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT
+  *         @arg @ref LL_DMA_PERIPH_INCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
+}
+
+/**
+  * @brief Set Memory increment mode.
+  * @rmtoll CR          MINC           LL_DMA_SetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  IncrementMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
+}
+
+/**
+  * @brief Get Memory increment mode.
+  * @rmtoll CR          MINC           LL_DMA_GetMemoryIncMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT
+  *         @arg @ref LL_DMA_MEMORY_INCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
+}
+
+/**
+  * @brief Set Peripheral size.
+  * @rmtoll CR          PSIZE           LL_DMA_SetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Size This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
+}
+
+/**
+  * @brief Get Peripheral size.
+  * @rmtoll CR          PSIZE           LL_DMA_GetPeriphSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_PDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
+}
+
+/**
+  * @brief Set Memory size.
+  * @rmtoll CR          MSIZE           LL_DMA_SetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Size This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
+}
+
+/**
+  * @brief Get Memory size.
+  * @rmtoll CR          MSIZE           LL_DMA_GetMemorySize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE
+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD
+  *         @arg @ref LL_DMA_MDATAALIGN_WORD
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
+}
+
+/**
+  * @brief Set Peripheral increment offset size.
+  * @rmtoll CR          PINCOS           LL_DMA_SetIncOffsetSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  OffsetSize This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
+}
+
+/**
+  * @brief Get Peripheral increment offset size.
+  * @rmtoll CR          PINCOS           LL_DMA_GetIncOffsetSize
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE
+  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
+}
+
+/**
+  * @brief Set Stream priority level.
+  * @rmtoll CR          PL           LL_DMA_SetStreamPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Priority This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Priority)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
+}
+
+/**
+  * @brief Get Stream priority level.
+  * @rmtoll CR          PL           LL_DMA_GetStreamPriorityLevel
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PRIORITY_LOW
+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM
+  *         @arg @ref LL_DMA_PRIORITY_HIGH
+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
+}
+
+/**
+  * @brief Set Number of data to transfer.
+  * @rmtoll NDTR          NDT           LL_DMA_SetDataLength
+  * @note   This action has no effect if
+  *         stream is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  NbData Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
+}
+
+/**
+  * @brief Get Number of data to transfer.
+  * @rmtoll NDTR          NDT           LL_DMA_GetDataLength
+  * @note   Once the stream is enabled, the return value indicate the
+  *         remaining bytes to be transmitted.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
+}
+
+/**
+  * @brief Select Channel number associated to the Stream.
+  * @rmtoll CR          CHSEL           LL_DMA_SetChannelSelection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
+}
+
+/**
+  * @brief Get the Channel number associated to the Stream.
+  * @rmtoll CR          CHSEL           LL_DMA_GetChannelSelection
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_CHANNEL_0
+  *         @arg @ref LL_DMA_CHANNEL_1
+  *         @arg @ref LL_DMA_CHANNEL_2
+  *         @arg @ref LL_DMA_CHANNEL_3
+  *         @arg @ref LL_DMA_CHANNEL_4
+  *         @arg @ref LL_DMA_CHANNEL_5
+  *         @arg @ref LL_DMA_CHANNEL_6
+  *         @arg @ref LL_DMA_CHANNEL_7
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
+}
+
+/**
+  * @brief Set Memory burst transfer configuration.
+  * @rmtoll CR          MBURST           LL_DMA_SetMemoryBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Mburst This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_MBURST_SINGLE
+  *         @arg @ref LL_DMA_MBURST_INC4
+  *         @arg @ref LL_DMA_MBURST_INC8
+  *         @arg @ref LL_DMA_MBURST_INC16
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
+}
+
+/**
+  * @brief Get Memory burst transfer configuration.
+  * @rmtoll CR          MBURST           LL_DMA_GetMemoryBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_MBURST_SINGLE
+  *         @arg @ref LL_DMA_MBURST_INC4
+  *         @arg @ref LL_DMA_MBURST_INC8
+  *         @arg @ref LL_DMA_MBURST_INC16
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
+}
+
+/**
+  * @brief Set  Peripheral burst transfer configuration.
+  * @rmtoll CR          PBURST           LL_DMA_SetPeriphBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Pburst This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_PBURST_SINGLE
+  *         @arg @ref LL_DMA_PBURST_INC4
+  *         @arg @ref LL_DMA_PBURST_INC8
+  *         @arg @ref LL_DMA_PBURST_INC16
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
+}
+
+/**
+  * @brief Get Peripheral burst transfer configuration.
+  * @rmtoll CR          PBURST           LL_DMA_GetPeriphBurstxfer
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_PBURST_SINGLE
+  *         @arg @ref LL_DMA_PBURST_INC4
+  *         @arg @ref LL_DMA_PBURST_INC8
+  *         @arg @ref LL_DMA_PBURST_INC16
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
+}
+
+/**
+  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+  * @rmtoll CR          CT           LL_DMA_SetCurrentTargetMem 
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param CurrentMemory This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
+{
+   MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
+}
+
+/**
+  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
+  * @rmtoll CR          CT           LL_DMA_GetCurrentTargetMem 
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM0
+  *         @arg @ref LL_DMA_CURRENTTARGETMEM1
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
+}
+
+/**
+  * @brief Enable the double buffer mode.
+  * @rmtoll CR          DBM           LL_DMA_EnableDoubleBufferMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
+}
+
+/**
+  * @brief Disable the double buffer mode.
+  * @rmtoll CR          DBM           LL_DMA_DisableDoubleBufferMode 
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
+}
+
+/**
+  * @brief Get FIFO status.
+  * @rmtoll FCR          FS          LL_DMA_GetFIFOStatus
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOSTATUS_0_25
+  *         @arg @ref LL_DMA_FIFOSTATUS_25_50
+  *         @arg @ref LL_DMA_FIFOSTATUS_50_75
+  *         @arg @ref LL_DMA_FIFOSTATUS_75_100
+  *         @arg @ref LL_DMA_FIFOSTATUS_EMPTY
+  *         @arg @ref LL_DMA_FIFOSTATUS_FULL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
+}
+
+/**
+  * @brief Disable Fifo mode.
+  * @rmtoll FCR          DMDIS          LL_DMA_DisableFifoMode
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
+}
+
+/**
+  * @brief Enable Fifo mode.
+  * @rmtoll FCR          DMDIS          LL_DMA_EnableFifoMode 
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
+}
+
+/**
+  * @brief Select FIFO threshold.
+  * @rmtoll FCR         FTH          LL_DMA_SetFIFOThreshold
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
+}
+
+/**
+  * @brief Get FIFO threshold.
+  * @rmtoll FCR         FTH          LL_DMA_GetFIFOThreshold
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
+}
+
+/**
+  * @brief Configure the FIFO .
+  * @rmtoll FCR         FTH          LL_DMA_ConfigFifo\n
+  *         FCR         DMDIS        LL_DMA_ConfigFifo
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  FifoMode This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOMODE_ENABLE
+  *         @arg @ref LL_DMA_FIFOMODE_DISABLE
+  * @param  FifoThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold);
+}
+
+/**
+  * @brief Configure the Source and Destination addresses.
+  * @note   This API must not be called when the DMA stream is enabled.
+  * @rmtoll M0AR        M0A         LL_DMA_ConfigAddresses\n 
+  *         PAR         PA          LL_DMA_ConfigAddresses
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  SrcAddress Between 0 to 0xFFFFFFFF
+  * @param  DstAddress Between 0 to 0xFFFFFFFF
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
+{
+  /* Direction Memory to Periph */
+  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
+  {
+    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
+    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
+  }
+  /* Direction Periph to Memory and Memory to Memory */
+  else
+  {
+    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
+    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
+  }
+}
+
+/**
+  * @brief  Set the Memory address.
+  * @rmtoll M0AR        M0A         LL_DMA_SetMemoryAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
+}
+
+/**
+  * @brief  Set the Peripheral address.
+  * @rmtoll PAR        PA         LL_DMA_SetPeriphAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  PeriphAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
+{
+  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
+}
+
+/**
+  * @brief  Get the Memory address.
+  * @rmtoll M0AR        M0A         LL_DMA_GetMemoryAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+  return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
+}
+
+/**
+  * @brief  Get the Peripheral address.
+  * @rmtoll PAR        PA         LL_DMA_GetPeriphAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+  return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
+}
+
+/**
+  * @brief  Set the Memory to Memory Source address.
+  * @rmtoll PAR        PA         LL_DMA_SetM2MSrcAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
+{
+  WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
+}
+
+/**
+  * @brief  Set the Memory to Memory Destination address.
+  * @rmtoll M0AR        M0A         LL_DMA_SetM2MDstAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @note   This API must not be called when the DMA channel is enabled.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
+  {
+    WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
+  }
+
+/**
+  * @brief  Get the Memory to Memory Source address.
+  * @rmtoll PAR        PA         LL_DMA_GetM2MSrcAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+  {
+   return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
+  }
+
+/**
+  * @brief  Get the Memory to Memory Destination address.
+  * @rmtoll M0AR        M0A         LL_DMA_GetM2MDstAddress
+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
+{
+ return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
+}
+
+/**
+  * @brief Set Memory 1 address (used in case of Double buffer mode).
+  * @rmtoll M1AR        M1A         LL_DMA_SetMemory1Address
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @param  Address Between 0 to 0xFFFFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
+{
+  MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
+}
+
+/**
+  * @brief Get Memory 1 address (used in case of Double buffer mode).
+  * @rmtoll M1AR        M1A         LL_DMA_GetMemory1Address
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval Between 0 to 0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief Get Stream 0 half transfer flag.
+  * @rmtoll LISR  HTIF0    LL_DMA_IsActiveFlag_HT0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
+}
+
+/**
+  * @brief Get Stream 1 half transfer flag.
+  * @rmtoll LISR  HTIF1    LL_DMA_IsActiveFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
+}
+
+/**
+  * @brief Get Stream 2 half transfer flag.
+  * @rmtoll LISR  HTIF2    LL_DMA_IsActiveFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
+}
+
+/**
+  * @brief Get Stream 3 half transfer flag.
+  * @rmtoll LISR  HTIF3    LL_DMA_IsActiveFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
+}
+
+/**
+  * @brief Get Stream 4 half transfer flag.
+  * @rmtoll HISR  HTIF4    LL_DMA_IsActiveFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
+}
+
+/**
+  * @brief Get Stream 5 half transfer flag.
+  * @rmtoll HISR  HTIF0    LL_DMA_IsActiveFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
+}
+
+/**
+  * @brief Get Stream 6 half transfer flag.
+  * @rmtoll HISR  HTIF6    LL_DMA_IsActiveFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
+}
+
+/**
+  * @brief Get Stream 7 half transfer flag.
+  * @rmtoll HISR  HTIF7    LL_DMA_IsActiveFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
+} 
+
+/**
+  * @brief Get Stream 0 transfer complete flag.
+  * @rmtoll LISR  TCIF0    LL_DMA_IsActiveFlag_TC0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
+}
+
+/**
+  * @brief Get Stream 1 transfer complete flag.
+  * @rmtoll LISR  TCIF1    LL_DMA_IsActiveFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
+}
+
+/**
+  * @brief Get Stream 2 transfer complete flag.
+  * @rmtoll LISR  TCIF2    LL_DMA_IsActiveFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
+}
+
+/**
+  * @brief Get Stream 3 transfer complete flag.
+  * @rmtoll LISR  TCIF3    LL_DMA_IsActiveFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
+}
+
+/**
+  * @brief Get Stream 4 transfer complete flag.
+  * @rmtoll HISR  TCIF4    LL_DMA_IsActiveFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
+}
+
+/**
+  * @brief Get Stream 5 transfer complete flag.
+  * @rmtoll HISR  TCIF0    LL_DMA_IsActiveFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
+}
+
+/**
+  * @brief Get Stream 6 transfer complete flag.
+  * @rmtoll HISR  TCIF6    LL_DMA_IsActiveFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
+}
+
+/**
+  * @brief Get Stream 7 transfer complete flag.
+  * @rmtoll HISR  TCIF7    LL_DMA_IsActiveFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
+} 
+
+/**
+  * @brief Get Stream 0 transfer error flag.
+  * @rmtoll LISR  TEIF0    LL_DMA_IsActiveFlag_TE0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
+}
+
+/**
+  * @brief Get Stream 1 transfer error flag.
+  * @rmtoll LISR  TEIF1    LL_DMA_IsActiveFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
+}
+
+/**
+  * @brief Get Stream 2 transfer error flag.
+  * @rmtoll LISR  TEIF2    LL_DMA_IsActiveFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
+}
+
+/**
+  * @brief Get Stream 3 transfer error flag.
+  * @rmtoll LISR  TEIF3    LL_DMA_IsActiveFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
+}
+
+/**
+  * @brief Get Stream 4 transfer error flag.
+  * @rmtoll HISR  TEIF4    LL_DMA_IsActiveFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
+}
+
+/**
+  * @brief Get Stream 5 transfer error flag.
+  * @rmtoll HISR  TEIF0    LL_DMA_IsActiveFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
+}
+
+/**
+  * @brief Get Stream 6 transfer error flag.
+  * @rmtoll HISR  TEIF6    LL_DMA_IsActiveFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
+}
+
+/**
+  * @brief Get Stream 7 transfer error flag.
+  * @rmtoll HISR  TEIF7    LL_DMA_IsActiveFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
+} 
+
+/**
+  * @brief Get Stream 0 direct mode error flag.
+  * @rmtoll LISR  DMEIF0    LL_DMA_IsActiveFlag_DME0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
+}
+
+/**
+  * @brief Get Stream 1 direct mode error flag.
+  * @rmtoll LISR  DMEIF1    LL_DMA_IsActiveFlag_DME1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
+}
+
+/**
+  * @brief Get Stream 2 direct mode error flag.
+  * @rmtoll LISR  DMEIF2    LL_DMA_IsActiveFlag_DME2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
+}
+
+/**
+  * @brief Get Stream 3 direct mode error flag.
+  * @rmtoll LISR  DMEIF3    LL_DMA_IsActiveFlag_DME3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
+}
+
+/**
+  * @brief Get Stream 4 direct mode error flag.
+  * @rmtoll HISR  DMEIF4    LL_DMA_IsActiveFlag_DME4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
+}
+
+/**
+  * @brief Get Stream 5 direct mode error flag.
+  * @rmtoll HISR  DMEIF0    LL_DMA_IsActiveFlag_DME5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
+}
+
+/**
+  * @brief Get Stream 6 direct mode error flag.
+  * @rmtoll HISR  DMEIF6    LL_DMA_IsActiveFlag_DME6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
+}
+
+/**
+  * @brief Get Stream 7 direct mode error flag.
+  * @rmtoll HISR  DMEIF7    LL_DMA_IsActiveFlag_DME7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
+}
+
+/**
+  * @brief Get Stream 0 FIFO error flag.
+  * @rmtoll LISR  FEIF0    LL_DMA_IsActiveFlag_FE0
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
+}
+
+/**
+  * @brief Get Stream 1 FIFO error flag.
+  * @rmtoll LISR  FEIF1    LL_DMA_IsActiveFlag_FE1
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
+}
+
+/**
+  * @brief Get Stream 2 FIFO error flag.
+  * @rmtoll LISR  FEIF2    LL_DMA_IsActiveFlag_FE2
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
+}
+
+/**
+  * @brief Get Stream 3 FIFO error flag.
+  * @rmtoll LISR  FEIF3    LL_DMA_IsActiveFlag_FE3
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
+}
+
+/**
+  * @brief Get Stream 4 FIFO error flag.
+  * @rmtoll HISR  FEIF4    LL_DMA_IsActiveFlag_FE4
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
+}
+
+/**
+  * @brief Get Stream 5 FIFO error flag.
+  * @rmtoll HISR  FEIF0    LL_DMA_IsActiveFlag_FE5
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
+}
+
+/**
+  * @brief Get Stream 6 FIFO error flag.
+  * @rmtoll HISR  FEIF6    LL_DMA_IsActiveFlag_FE6
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
+}
+
+/**
+  * @brief Get Stream 7 FIFO error flag.
+  * @rmtoll HISR  FEIF7    LL_DMA_IsActiveFlag_FE7
+  * @param  DMAx DMAx Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
+{
+  return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
+}
+
+/**
+  * @brief Clear Stream 0 half transfer flag.
+  * @rmtoll LIFCR  CHTIF0    LL_DMA_ClearFlag_HT0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
+}
+
+/**
+  * @brief Clear Stream 1 half transfer flag.
+  * @rmtoll LIFCR  CHTIF1    LL_DMA_ClearFlag_HT1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
+}
+
+/**
+  * @brief Clear Stream 2 half transfer flag.
+  * @rmtoll LIFCR  CHTIF2    LL_DMA_ClearFlag_HT2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
+}
+
+/**
+  * @brief Clear Stream 3 half transfer flag.
+  * @rmtoll LIFCR  CHTIF3    LL_DMA_ClearFlag_HT3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
+}
+
+/**
+  * @brief Clear Stream 4 half transfer flag.
+  * @rmtoll HIFCR  CHTIF4    LL_DMA_ClearFlag_HT4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
+}
+
+/**
+  * @brief Clear Stream 5 half transfer flag.
+  * @rmtoll HIFCR  CHTIF5    LL_DMA_ClearFlag_HT5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
+}
+
+/**
+  * @brief Clear Stream 6 half transfer flag.
+  * @rmtoll HIFCR  CHTIF6    LL_DMA_ClearFlag_HT6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
+}
+
+/**
+  * @brief Clear Stream 7 half transfer flag.
+  * @rmtoll HIFCR  CHTIF7    LL_DMA_ClearFlag_HT7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
+}
+
+/**
+  * @brief Clear Stream 0 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF0    LL_DMA_ClearFlag_TC0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
+}
+
+/**
+  * @brief Clear Stream 1 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF1    LL_DMA_ClearFlag_TC1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
+}
+
+/**
+  * @brief Clear Stream 2 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF2    LL_DMA_ClearFlag_TC2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
+}
+
+/**
+  * @brief Clear Stream 3 transfer complete flag.
+  * @rmtoll LIFCR  CTCIF3    LL_DMA_ClearFlag_TC3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
+}
+
+/**
+  * @brief Clear Stream 4 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF4    LL_DMA_ClearFlag_TC4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
+}
+
+/**
+  * @brief Clear Stream 5 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF5    LL_DMA_ClearFlag_TC5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
+}
+
+/**
+  * @brief Clear Stream 6 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF6    LL_DMA_ClearFlag_TC6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
+}
+
+/**
+  * @brief Clear Stream 7 transfer complete flag.
+  * @rmtoll HIFCR  CTCIF7    LL_DMA_ClearFlag_TC7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
+}
+
+/**
+  * @brief Clear Stream 0 transfer error flag.
+  * @rmtoll LIFCR  CTEIF0    LL_DMA_ClearFlag_TE0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 transfer error flag.
+  * @rmtoll LIFCR  CTEIF1    LL_DMA_ClearFlag_TE1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 transfer error flag.
+  * @rmtoll LIFCR  CTEIF2    LL_DMA_ClearFlag_TE2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 transfer error flag.
+  * @rmtoll LIFCR  CTEIF3    LL_DMA_ClearFlag_TE3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 transfer error flag.
+  * @rmtoll HIFCR  CTEIF4    LL_DMA_ClearFlag_TE4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 transfer error flag.
+  * @rmtoll HIFCR  CTEIF5    LL_DMA_ClearFlag_TE5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 transfer error flag.
+  * @rmtoll HIFCR  CTEIF6    LL_DMA_ClearFlag_TE6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 transfer error flag.
+  * @rmtoll HIFCR  CTEIF7    LL_DMA_ClearFlag_TE7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
+}
+
+/**
+  * @brief Clear Stream 0 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF0    LL_DMA_ClearFlag_DME0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF1    LL_DMA_ClearFlag_DME1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF2    LL_DMA_ClearFlag_DME2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 direct mode error flag.
+  * @rmtoll LIFCR  CDMEIF3    LL_DMA_ClearFlag_DME3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF4    LL_DMA_ClearFlag_DME4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF5    LL_DMA_ClearFlag_DME5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF6    LL_DMA_ClearFlag_DME6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 direct mode error flag.
+  * @rmtoll HIFCR  CDMEIF7    LL_DMA_ClearFlag_DME7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
+}
+
+/**
+  * @brief Clear Stream 0 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF0    LL_DMA_ClearFlag_FE0
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
+}
+
+/**
+  * @brief Clear Stream 1 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF1    LL_DMA_ClearFlag_FE1
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
+}
+
+/**
+  * @brief Clear Stream 2 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF2    LL_DMA_ClearFlag_FE2
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
+}
+
+/**
+  * @brief Clear Stream 3 FIFO error flag.
+  * @rmtoll LIFCR  CFEIF3    LL_DMA_ClearFlag_FE3
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
+}
+
+/**
+  * @brief Clear Stream 4 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF4    LL_DMA_ClearFlag_FE4
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
+}
+
+/**
+  * @brief Clear Stream 5 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF5    LL_DMA_ClearFlag_FE5
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
+}
+
+/**
+  * @brief Clear Stream 6 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF6    LL_DMA_ClearFlag_FE6
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
+}
+
+/**
+  * @brief Clear Stream 7 FIFO error flag.
+  * @rmtoll HIFCR  CFEIF7    LL_DMA_ClearFlag_FE7
+  * @param  DMAx DMAx Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
+{
+  WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief Enable Half transfer interrupt.
+  * @rmtoll CR        HTIE         LL_DMA_EnableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
+}
+
+/**
+  * @brief Enable Transfer error interrupt.
+  * @rmtoll CR        TEIE         LL_DMA_EnableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
+}
+
+/**
+  * @brief Enable Transfer complete interrupt.
+  * @rmtoll CR        TCIE         LL_DMA_EnableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
+}
+
+/**
+  * @brief Enable Direct mode error interrupt.
+  * @rmtoll CR        DMEIE         LL_DMA_EnableIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
+}
+
+/**
+  * @brief Enable FIFO error interrupt.
+  * @rmtoll FCR        FEIE         LL_DMA_EnableIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
+}
+
+/**
+  * @brief Disable Half transfer interrupt.
+  * @rmtoll CR        HTIE         LL_DMA_DisableIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
+}
+
+/**
+  * @brief Disable Transfer error interrupt.
+  * @rmtoll CR        TEIE         LL_DMA_DisableIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
+}
+
+/**
+  * @brief Disable Transfer complete interrupt.
+  * @rmtoll CR        TCIE         LL_DMA_DisableIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
+}
+
+/**
+  * @brief Disable Direct mode error interrupt.
+  * @rmtoll CR        DMEIE         LL_DMA_DisableIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
+}
+
+/**
+  * @brief Disable FIFO error interrupt.
+  * @rmtoll FCR        FEIE         LL_DMA_DisableIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
+}
+
+/**
+  * @brief Check if Half transfer interrupt is enabled.
+  * @rmtoll CR        HTIE         LL_DMA_IsEnabledIT_HT
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
+}
+
+/**
+  * @brief Check if Transfer error nterrup is enabled.
+  * @rmtoll CR        TEIE         LL_DMA_IsEnabledIT_TE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
+}
+
+/**
+  * @brief Check if Transfer complete interrupt is enabled.
+  * @rmtoll CR        TCIE         LL_DMA_IsEnabledIT_TC
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
+}
+
+/**
+  * @brief Check if Direct mode error interrupt is enabled.
+  * @rmtoll CR        DMEIE         LL_DMA_IsEnabledIT_DME
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
+}
+
+/**
+  * @brief Check if FIFO error interrupt is enabled.
+  * @rmtoll FCR        FEIE         LL_DMA_IsEnabledIT_FE
+  * @param  DMAx DMAx Instance
+  * @param  Stream This parameter can be one of the following values:
+  *         @arg @ref LL_DMA_STREAM_0
+  *         @arg @ref LL_DMA_STREAM_1
+  *         @arg @ref LL_DMA_STREAM_2
+  *         @arg @ref LL_DMA_STREAM_3
+  *         @arg @ref LL_DMA_STREAM_4
+  *         @arg @ref LL_DMA_STREAM_5
+  *         @arg @ref LL_DMA_STREAM_6
+  *         @arg @ref LL_DMA_STREAM_7
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
+{
+  return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DMA1 || DMA2 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_DMA_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h
index 65ab691..bef8894 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_exti.h
@@ -1,954 +1,954 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_ll_exti.h
-  * @author  MCD Application Team
-  * @brief   Header file of EXTI LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.Clause
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_EXTI_H
-#define __STM32F4xx_LL_EXTI_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_LL_Driver
-  * @{
-  */
-
-#if defined (EXTI)
-
-/** @defgroup EXTI_LL EXTI
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private Macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
-  * @{
-  */
-typedef struct
-{
-
-  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
-                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
-
-  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
-                                     This parameter can be set either to ENABLE or DISABLE */
-
-  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
-                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */
-
-  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
-                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
-} LL_EXTI_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
-  * @{
-  */
-
-/** @defgroup EXTI_LL_EC_LINE LINE
-  * @{
-  */
-#define LL_EXTI_LINE_0                 EXTI_IMR_IM0           /*!< Extended line 0 */
-#define LL_EXTI_LINE_1                 EXTI_IMR_IM1           /*!< Extended line 1 */
-#define LL_EXTI_LINE_2                 EXTI_IMR_IM2           /*!< Extended line 2 */
-#define LL_EXTI_LINE_3                 EXTI_IMR_IM3           /*!< Extended line 3 */
-#define LL_EXTI_LINE_4                 EXTI_IMR_IM4           /*!< Extended line 4 */
-#define LL_EXTI_LINE_5                 EXTI_IMR_IM5           /*!< Extended line 5 */
-#define LL_EXTI_LINE_6                 EXTI_IMR_IM6           /*!< Extended line 6 */
-#define LL_EXTI_LINE_7                 EXTI_IMR_IM7           /*!< Extended line 7 */
-#define LL_EXTI_LINE_8                 EXTI_IMR_IM8           /*!< Extended line 8 */
-#define LL_EXTI_LINE_9                 EXTI_IMR_IM9           /*!< Extended line 9 */
-#define LL_EXTI_LINE_10                EXTI_IMR_IM10          /*!< Extended line 10 */
-#define LL_EXTI_LINE_11                EXTI_IMR_IM11          /*!< Extended line 11 */
-#define LL_EXTI_LINE_12                EXTI_IMR_IM12          /*!< Extended line 12 */
-#define LL_EXTI_LINE_13                EXTI_IMR_IM13          /*!< Extended line 13 */
-#define LL_EXTI_LINE_14                EXTI_IMR_IM14          /*!< Extended line 14 */
-#define LL_EXTI_LINE_15                EXTI_IMR_IM15          /*!< Extended line 15 */
-#if defined(EXTI_IMR_IM16)
-#define LL_EXTI_LINE_16                EXTI_IMR_IM16          /*!< Extended line 16 */
-#endif
-#define LL_EXTI_LINE_17                EXTI_IMR_IM17          /*!< Extended line 17 */
-#if defined(EXTI_IMR_IM18)
-#define LL_EXTI_LINE_18                EXTI_IMR_IM18          /*!< Extended line 18 */
-#endif
-#define LL_EXTI_LINE_19                EXTI_IMR_IM19          /*!< Extended line 19 */
-#if defined(EXTI_IMR_IM20)
-#define LL_EXTI_LINE_20                EXTI_IMR_IM20          /*!< Extended line 20 */
-#endif
-#if defined(EXTI_IMR_IM21)
-#define LL_EXTI_LINE_21                EXTI_IMR_IM21          /*!< Extended line 21 */
-#endif
-#if defined(EXTI_IMR_IM22)
-#define LL_EXTI_LINE_22                EXTI_IMR_IM22          /*!< Extended line 22 */
-#endif
-#if defined(EXTI_IMR_IM23)
-#define LL_EXTI_LINE_23                EXTI_IMR_IM23          /*!< Extended line 23 */
-#endif
-#if defined(EXTI_IMR_IM24)
-#define LL_EXTI_LINE_24                EXTI_IMR_IM24          /*!< Extended line 24 */
-#endif
-#if defined(EXTI_IMR_IM25)
-#define LL_EXTI_LINE_25                EXTI_IMR_IM25          /*!< Extended line 25 */
-#endif
-#if defined(EXTI_IMR_IM26)
-#define LL_EXTI_LINE_26                EXTI_IMR_IM26          /*!< Extended line 26 */
-#endif
-#if defined(EXTI_IMR_IM27)
-#define LL_EXTI_LINE_27                EXTI_IMR_IM27          /*!< Extended line 27 */
-#endif
-#if defined(EXTI_IMR_IM28)
-#define LL_EXTI_LINE_28                EXTI_IMR_IM28          /*!< Extended line 28 */
-#endif
-#if defined(EXTI_IMR_IM29)
-#define LL_EXTI_LINE_29                EXTI_IMR_IM29          /*!< Extended line 29 */
-#endif
-#if defined(EXTI_IMR_IM30)
-#define LL_EXTI_LINE_30                EXTI_IMR_IM30          /*!< Extended line 30 */
-#endif
-#if defined(EXTI_IMR_IM31)
-#define LL_EXTI_LINE_31                EXTI_IMR_IM31          /*!< Extended line 31 */
-#endif
-#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR_IM            /*!< All Extended line not reserved*/
-
-
-#define LL_EXTI_LINE_ALL               ((uint32_t)0xFFFFFFFFU)  /*!< All Extended line */
-
-#if defined(USE_FULL_LL_DRIVER)
-#define LL_EXTI_LINE_NONE              ((uint32_t)0x00000000U)  /*!< None Extended line */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/**
-  * @}
-  */
-#if defined(USE_FULL_LL_DRIVER)
-
-/** @defgroup EXTI_LL_EC_MODE Mode
-  * @{
-  */
-#define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
-#define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
-#define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
-  * @{
-  */
-#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
-#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
-#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
-#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
-
-/**
-  * @}
-  */
-
-
-#endif /*USE_FULL_LL_DRIVER*/
-
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
-  * @{
-  */
-
-/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in EXTI register
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in EXTI register
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
- * @{
- */
-/** @defgroup EXTI_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
-  * @note The reset value for the direct or internal lines (see RM)
-  *       is set to 1 in order to enable the interrupt by default.
-  *       Bits are set automatically at Power on.
-  * @rmtoll IMR         IMx           LL_EXTI_EnableIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19(*)
-  *         @arg @ref LL_EXTI_LINE_20(*)
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23(*)
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   (*): Available in some devices
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->IMR, ExtiLine);
-}
-
-/**
-  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
-  * @note The reset value for the direct or internal lines (see RM)
-  *       is set to 1 in order to enable the interrupt by default.
-  *       Bits are set automatically at Power on.
-  * @rmtoll IMR         IMx           LL_EXTI_DisableIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19(*)
-  *         @arg @ref LL_EXTI_LINE_20(*)
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23(*)
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   (*): Available in some devices
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->IMR, ExtiLine);
-}
-
-
-/**
-  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
-  * @note The reset value for the direct or internal lines (see RM)
-  *       is set to 1 in order to enable the interrupt by default.
-  *       Bits are set automatically at Power on.
-  * @rmtoll IMR         IMx           LL_EXTI_IsEnabledIT_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19(*)
-  *         @arg @ref LL_EXTI_LINE_20(*)
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23(*)
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   (*): Available in some devices
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Event_Management Event_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
-  * @rmtoll EMR         EMx           LL_EXTI_EnableEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19(*)
-  *         @arg @ref LL_EXTI_LINE_20(*)
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23(*)
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   (*): Available in some devices
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->EMR, ExtiLine);
-
-}
-
-
-/**
-  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
-  * @rmtoll EMR         EMx           LL_EXTI_DisableEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19(*)
-  *         @arg @ref LL_EXTI_LINE_20(*)
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23(*)
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   (*): Available in some devices
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->EMR, ExtiLine);
-}
-
-
-/**
-  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
-  * @rmtoll EMR         EMx           LL_EXTI_IsEnabledEvent_0_31
-  * @param  ExtiLine This parameter can be one of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_17
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19(*)
-  *         @arg @ref LL_EXTI_LINE_20(*)
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  *         @arg @ref LL_EXTI_LINE_23(*)
-  *         @arg @ref LL_EXTI_LINE_ALL_0_31
-  * @note   (*): Available in some devices
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
-
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a rising edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_RTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll RTSR        RTx           LL_EXTI_EnableRisingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19(*)
-  *         @arg @ref LL_EXTI_LINE_20(*)
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  * @note   (*): Available in some devices
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->RTSR, ExtiLine);
-
-}
-
-
-/**
-  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a rising edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_RTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll RTSR        RTx           LL_EXTI_DisableRisingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19(*)
-  *         @arg @ref LL_EXTI_LINE_20(*)
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  * @note   (*): Available in some devices
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->RTSR, ExtiLine);
-
-}
-
-
-/**
-  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
-  * @rmtoll RTSR        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19(*)
-  *         @arg @ref LL_EXTI_LINE_20(*)
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  * @note   (*): Available in some devices
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a falling edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_FTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for
-  *       the same interrupt line. In this case, both generate a trigger
-  *       condition.
-  * @rmtoll FTSR        FTx           LL_EXTI_EnableFallingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19(*)
-  *         @arg @ref LL_EXTI_LINE_20(*)
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  * @note   (*): Available in some devices
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->FTSR, ExtiLine);
-}
-
-
-/**
-  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
-  * @note The configurable wakeup lines are edge-triggered. No glitch must be
-  *       generated on these lines. If a Falling edge on a configurable interrupt
-  *       line occurs during a write operation in the EXTI_FTSR register, the
-  *       pending bit is not set.
-  *       Rising and falling edge triggers can be set for the same interrupt line.
-  *       In this case, both generate a trigger condition.
-  * @rmtoll FTSR        FTx           LL_EXTI_DisableFallingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19(*)
-  *         @arg @ref LL_EXTI_LINE_20(*)
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  * @note   (*): Available in some devices
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
-{
-  CLEAR_BIT(EXTI->FTSR, ExtiLine);
-}
-
-
-/**
-  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
-  * @rmtoll FTSR        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19(*)
-  *         @arg @ref LL_EXTI_LINE_20(*)
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  * @note   (*): Available in some devices
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
-  * @{
-  */
-
-/**
-  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
-  * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
-  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
-  *       resulting in an interrupt request generation.
-  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
-  *       register (by writing a 1 into the bit)
-  * @rmtoll SWIER       SWIx          LL_EXTI_GenerateSWI_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19(*)
-  *         @arg @ref LL_EXTI_LINE_20(*)
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  * @note   (*): Available in some devices
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
-{
-  SET_BIT(EXTI->SWIER, ExtiLine);
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
-  * @{
-  */
-
-/**
-  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR          PIFx           LL_EXTI_IsActiveFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19(*)
-  *         @arg @ref LL_EXTI_LINE_20(*)
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  * @note   (*): Available in some devices
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
-{
-  return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
-}
-
-
-/**
-  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR          PIFx           LL_EXTI_ReadFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19(*)
-  *         @arg @ref LL_EXTI_LINE_20(*)
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  * @note   (*): Available in some devices
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval @note This bit is set when the selected edge event arrives on the interrupt
-  */
-__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
-{
-  return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
-}
-
-
-/**
-  * @brief  Clear ExtLine Flags  for Lines in range 0 to 31
-  * @note This bit is set when the selected edge event arrives on the interrupt
-  *       line. This bit is cleared by writing a 1 to the bit.
-  * @rmtoll PR          PIFx           LL_EXTI_ClearFlag_0_31
-  * @param  ExtiLine This parameter can be a combination of the following values:
-  *         @arg @ref LL_EXTI_LINE_0
-  *         @arg @ref LL_EXTI_LINE_1
-  *         @arg @ref LL_EXTI_LINE_2
-  *         @arg @ref LL_EXTI_LINE_3
-  *         @arg @ref LL_EXTI_LINE_4
-  *         @arg @ref LL_EXTI_LINE_5
-  *         @arg @ref LL_EXTI_LINE_6
-  *         @arg @ref LL_EXTI_LINE_7
-  *         @arg @ref LL_EXTI_LINE_8
-  *         @arg @ref LL_EXTI_LINE_9
-  *         @arg @ref LL_EXTI_LINE_10
-  *         @arg @ref LL_EXTI_LINE_11
-  *         @arg @ref LL_EXTI_LINE_12
-  *         @arg @ref LL_EXTI_LINE_13
-  *         @arg @ref LL_EXTI_LINE_14
-  *         @arg @ref LL_EXTI_LINE_15
-  *         @arg @ref LL_EXTI_LINE_16
-  *         @arg @ref LL_EXTI_LINE_18
-  *         @arg @ref LL_EXTI_LINE_19(*)
-  *         @arg @ref LL_EXTI_LINE_20(*)
-  *         @arg @ref LL_EXTI_LINE_21
-  *         @arg @ref LL_EXTI_LINE_22
-  * @note   (*): Available in some devices
-  * @note   Please check each device line mapping for EXTI Line availability
-  * @retval None
-  */
-__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
-{
-  WRITE_REG(EXTI->PR, ExtiLine);
-}
-
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-uint32_t LL_EXTI_DeInit(void);
-void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
-
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* EXTI */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_LL_EXTI_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_exti.h
+  * @author  MCD Application Team
+  * @brief   Header file of EXTI LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_EXTI_H
+#define __STM32F4xx_LL_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined (EXTI)
+
+/** @defgroup EXTI_LL EXTI
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private Macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
+  * @{
+  */
+typedef struct
+{
+
+  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */
+
+  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.
+                                     This parameter can be set either to ENABLE or DISABLE */
+
+  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */
+
+  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
+} LL_EXTI_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EC_LINE LINE
+  * @{
+  */
+#define LL_EXTI_LINE_0                 EXTI_IMR_IM0           /*!< Extended line 0 */
+#define LL_EXTI_LINE_1                 EXTI_IMR_IM1           /*!< Extended line 1 */
+#define LL_EXTI_LINE_2                 EXTI_IMR_IM2           /*!< Extended line 2 */
+#define LL_EXTI_LINE_3                 EXTI_IMR_IM3           /*!< Extended line 3 */
+#define LL_EXTI_LINE_4                 EXTI_IMR_IM4           /*!< Extended line 4 */
+#define LL_EXTI_LINE_5                 EXTI_IMR_IM5           /*!< Extended line 5 */
+#define LL_EXTI_LINE_6                 EXTI_IMR_IM6           /*!< Extended line 6 */
+#define LL_EXTI_LINE_7                 EXTI_IMR_IM7           /*!< Extended line 7 */
+#define LL_EXTI_LINE_8                 EXTI_IMR_IM8           /*!< Extended line 8 */
+#define LL_EXTI_LINE_9                 EXTI_IMR_IM9           /*!< Extended line 9 */
+#define LL_EXTI_LINE_10                EXTI_IMR_IM10          /*!< Extended line 10 */
+#define LL_EXTI_LINE_11                EXTI_IMR_IM11          /*!< Extended line 11 */
+#define LL_EXTI_LINE_12                EXTI_IMR_IM12          /*!< Extended line 12 */
+#define LL_EXTI_LINE_13                EXTI_IMR_IM13          /*!< Extended line 13 */
+#define LL_EXTI_LINE_14                EXTI_IMR_IM14          /*!< Extended line 14 */
+#define LL_EXTI_LINE_15                EXTI_IMR_IM15          /*!< Extended line 15 */
+#if defined(EXTI_IMR_IM16)
+#define LL_EXTI_LINE_16                EXTI_IMR_IM16          /*!< Extended line 16 */
+#endif
+#define LL_EXTI_LINE_17                EXTI_IMR_IM17          /*!< Extended line 17 */
+#if defined(EXTI_IMR_IM18)
+#define LL_EXTI_LINE_18                EXTI_IMR_IM18          /*!< Extended line 18 */
+#endif
+#define LL_EXTI_LINE_19                EXTI_IMR_IM19          /*!< Extended line 19 */
+#if defined(EXTI_IMR_IM20)
+#define LL_EXTI_LINE_20                EXTI_IMR_IM20          /*!< Extended line 20 */
+#endif
+#if defined(EXTI_IMR_IM21)
+#define LL_EXTI_LINE_21                EXTI_IMR_IM21          /*!< Extended line 21 */
+#endif
+#if defined(EXTI_IMR_IM22)
+#define LL_EXTI_LINE_22                EXTI_IMR_IM22          /*!< Extended line 22 */
+#endif
+#if defined(EXTI_IMR_IM23)
+#define LL_EXTI_LINE_23                EXTI_IMR_IM23          /*!< Extended line 23 */
+#endif
+#if defined(EXTI_IMR_IM24)
+#define LL_EXTI_LINE_24                EXTI_IMR_IM24          /*!< Extended line 24 */
+#endif
+#if defined(EXTI_IMR_IM25)
+#define LL_EXTI_LINE_25                EXTI_IMR_IM25          /*!< Extended line 25 */
+#endif
+#if defined(EXTI_IMR_IM26)
+#define LL_EXTI_LINE_26                EXTI_IMR_IM26          /*!< Extended line 26 */
+#endif
+#if defined(EXTI_IMR_IM27)
+#define LL_EXTI_LINE_27                EXTI_IMR_IM27          /*!< Extended line 27 */
+#endif
+#if defined(EXTI_IMR_IM28)
+#define LL_EXTI_LINE_28                EXTI_IMR_IM28          /*!< Extended line 28 */
+#endif
+#if defined(EXTI_IMR_IM29)
+#define LL_EXTI_LINE_29                EXTI_IMR_IM29          /*!< Extended line 29 */
+#endif
+#if defined(EXTI_IMR_IM30)
+#define LL_EXTI_LINE_30                EXTI_IMR_IM30          /*!< Extended line 30 */
+#endif
+#if defined(EXTI_IMR_IM31)
+#define LL_EXTI_LINE_31                EXTI_IMR_IM31          /*!< Extended line 31 */
+#endif
+#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR_IM            /*!< All Extended line not reserved*/
+
+
+#define LL_EXTI_LINE_ALL               ((uint32_t)0xFFFFFFFFU)  /*!< All Extended line */
+
+#if defined(USE_FULL_LL_DRIVER)
+#define LL_EXTI_LINE_NONE              ((uint32_t)0x00000000U)  /*!< None Extended line */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/**
+  * @}
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/** @defgroup EXTI_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_EXTI_MODE_IT                 ((uint8_t)0x00U) /*!< Interrupt Mode */
+#define LL_EXTI_MODE_EVENT              ((uint8_t)0x01U) /*!< Event Mode */
+#define LL_EXTI_MODE_IT_EVENT           ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
+  * @{
+  */
+#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */
+#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */
+#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */
+#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
+
+/**
+  * @}
+  */
+
+
+#endif /*USE_FULL_LL_DRIVER*/
+
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
+  * @{
+  */
+
+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in EXTI register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in EXTI register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
+ * @{
+ */
+/** @defgroup EXTI_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR         IMx           LL_EXTI_EnableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->IMR, ExtiLine);
+}
+
+/**
+  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR         IMx           LL_EXTI_DisableIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->IMR, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
+  * @note The reset value for the direct or internal lines (see RM)
+  *       is set to 1 in order to enable the interrupt by default.
+  *       Bits are set automatically at Power on.
+  * @rmtoll IMR         IMx           LL_EXTI_IsEnabledIT_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Event_Management Event_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR         EMx           LL_EXTI_EnableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->EMR, ExtiLine);
+
+}
+
+
+/**
+  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31
+  * @rmtoll EMR         EMx           LL_EXTI_DisableEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->EMR, ExtiLine);
+}
+
+
+/**
+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
+  * @rmtoll EMR         EMx           LL_EXTI_IsEnabledEvent_0_31
+  * @param  ExtiLine This parameter can be one of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_17
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  *         @arg @ref LL_EXTI_LINE_23(*)
+  *         @arg @ref LL_EXTI_LINE_ALL_0_31
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine));
+
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR        RTx           LL_EXTI_EnableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+
+/**
+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a rising edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_RTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll RTSR        RTx           LL_EXTI_DisableRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->RTSR, ExtiLine);
+
+}
+
+
+/**
+  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll RTSR        RTx           LL_EXTI_IsEnabledRisingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for
+  *       the same interrupt line. In this case, both generate a trigger
+  *       condition.
+  * @rmtoll FTSR        FTx           LL_EXTI_EnableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->FTSR, ExtiLine);
+}
+
+
+/**
+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
+  * @note The configurable wakeup lines are edge-triggered. No glitch must be
+  *       generated on these lines. If a Falling edge on a configurable interrupt
+  *       line occurs during a write operation in the EXTI_FTSR register, the
+  *       pending bit is not set.
+  *       Rising and falling edge triggers can be set for the same interrupt line.
+  *       In this case, both generate a trigger condition.
+  * @rmtoll FTSR        FTx           LL_EXTI_DisableFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
+{
+  CLEAR_BIT(EXTI->FTSR, ExtiLine);
+}
+
+
+/**
+  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31
+  * @rmtoll FTSR        FTx           LL_EXTI_IsEnabledFallingTrig_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
+  * @{
+  */
+
+/**
+  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31
+  * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to
+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR
+  *       resulting in an interrupt request generation.
+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR
+  *       register (by writing a 1 into the bit)
+  * @rmtoll SWIER       SWIx          LL_EXTI_GenerateSWI_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
+{
+  SET_BIT(EXTI->SWIER, ExtiLine);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR          PIFx           LL_EXTI_IsActiveFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
+{
+  return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine));
+}
+
+
+/**
+  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR          PIFx           LL_EXTI_ReadFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval @note This bit is set when the selected edge event arrives on the interrupt
+  */
+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
+{
+  return (uint32_t)(READ_BIT(EXTI->PR, ExtiLine));
+}
+
+
+/**
+  * @brief  Clear ExtLine Flags  for Lines in range 0 to 31
+  * @note This bit is set when the selected edge event arrives on the interrupt
+  *       line. This bit is cleared by writing a 1 to the bit.
+  * @rmtoll PR          PIFx           LL_EXTI_ClearFlag_0_31
+  * @param  ExtiLine This parameter can be a combination of the following values:
+  *         @arg @ref LL_EXTI_LINE_0
+  *         @arg @ref LL_EXTI_LINE_1
+  *         @arg @ref LL_EXTI_LINE_2
+  *         @arg @ref LL_EXTI_LINE_3
+  *         @arg @ref LL_EXTI_LINE_4
+  *         @arg @ref LL_EXTI_LINE_5
+  *         @arg @ref LL_EXTI_LINE_6
+  *         @arg @ref LL_EXTI_LINE_7
+  *         @arg @ref LL_EXTI_LINE_8
+  *         @arg @ref LL_EXTI_LINE_9
+  *         @arg @ref LL_EXTI_LINE_10
+  *         @arg @ref LL_EXTI_LINE_11
+  *         @arg @ref LL_EXTI_LINE_12
+  *         @arg @ref LL_EXTI_LINE_13
+  *         @arg @ref LL_EXTI_LINE_14
+  *         @arg @ref LL_EXTI_LINE_15
+  *         @arg @ref LL_EXTI_LINE_16
+  *         @arg @ref LL_EXTI_LINE_18
+  *         @arg @ref LL_EXTI_LINE_19(*)
+  *         @arg @ref LL_EXTI_LINE_20(*)
+  *         @arg @ref LL_EXTI_LINE_21
+  *         @arg @ref LL_EXTI_LINE_22
+  * @note   (*): Available in some devices
+  * @note   Please check each device line mapping for EXTI Line availability
+  * @retval None
+  */
+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
+{
+  WRITE_REG(EXTI->PR, ExtiLine);
+}
+
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+uint32_t LL_EXTI_DeInit(void);
+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
+
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* EXTI */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_EXTI_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h
index 6bee7fd..9d5b34c 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_gpio.h
@@ -1,981 +1,981 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_ll_gpio.h
-  * @author  MCD Application Team
-  * @brief   Header file of GPIO LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_GPIO_H
-#define __STM32F4xx_LL_GPIO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_LL_Driver
-  * @{
-  */
-
-#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
-
-/** @defgroup GPIO_LL GPIO
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
-  * @{
-  */
-
-/**
-  * @brief LL GPIO Init Structure definition
-  */
-typedef struct
-{
-  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
-                              This parameter can be any value of @ref GPIO_LL_EC_PIN */
-
-  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_MODE.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
-
-  uint32_t Speed;        /*!< Specifies the speed for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
-
-  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
-
-  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_PULL.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
-
-  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
-                              This parameter can be a value of @ref GPIO_LL_EC_AF.
-
-                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
-} LL_GPIO_InitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
-  * @{
-  */
-
-/** @defgroup GPIO_LL_EC_PIN PIN
-  * @{
-  */
-#define LL_GPIO_PIN_0                      GPIO_BSRR_BS_0 /*!< Select pin 0 */
-#define LL_GPIO_PIN_1                      GPIO_BSRR_BS_1 /*!< Select pin 1 */
-#define LL_GPIO_PIN_2                      GPIO_BSRR_BS_2 /*!< Select pin 2 */
-#define LL_GPIO_PIN_3                      GPIO_BSRR_BS_3 /*!< Select pin 3 */
-#define LL_GPIO_PIN_4                      GPIO_BSRR_BS_4 /*!< Select pin 4 */
-#define LL_GPIO_PIN_5                      GPIO_BSRR_BS_5 /*!< Select pin 5 */
-#define LL_GPIO_PIN_6                      GPIO_BSRR_BS_6 /*!< Select pin 6 */
-#define LL_GPIO_PIN_7                      GPIO_BSRR_BS_7 /*!< Select pin 7 */
-#define LL_GPIO_PIN_8                      GPIO_BSRR_BS_8 /*!< Select pin 8 */
-#define LL_GPIO_PIN_9                      GPIO_BSRR_BS_9 /*!< Select pin 9 */
-#define LL_GPIO_PIN_10                     GPIO_BSRR_BS_10 /*!< Select pin 10 */
-#define LL_GPIO_PIN_11                     GPIO_BSRR_BS_11 /*!< Select pin 11 */
-#define LL_GPIO_PIN_12                     GPIO_BSRR_BS_12 /*!< Select pin 12 */
-#define LL_GPIO_PIN_13                     GPIO_BSRR_BS_13 /*!< Select pin 13 */
-#define LL_GPIO_PIN_14                     GPIO_BSRR_BS_14 /*!< Select pin 14 */
-#define LL_GPIO_PIN_15                     GPIO_BSRR_BS_15 /*!< Select pin 15 */
-#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1  | GPIO_BSRR_BS_2  | \
-                                           GPIO_BSRR_BS_3  | GPIO_BSRR_BS_4  | GPIO_BSRR_BS_5  | \
-                                           GPIO_BSRR_BS_6  | GPIO_BSRR_BS_7  | GPIO_BSRR_BS_8  | \
-                                           GPIO_BSRR_BS_9  | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
-                                           GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
-                                           GPIO_BSRR_BS_15) /*!< Select all pins */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_MODE Mode
-  * @{
-  */
-#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
-#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODER0_0  /*!< Select output mode */
-#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODER0_1  /*!< Select alternate function mode */
-#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODER0    /*!< Select analog mode */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_OUTPUT Output Type
-  * @{
-  */
-#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
-#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_SPEED Output Speed
-  * @{
-  */
-#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
-#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
-#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed   */
-#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDER_OSPEEDR0   /*!< Select I/O high output speed   */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
-  * @{
-  */
-#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
-#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
-#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EC_AF Alternate Function
-  * @{
-  */
-#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
-#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
-#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
-#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
-#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
-#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
-#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
-#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
-#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
-#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
-#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
-#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
-#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
-#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
-#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
-#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
-  * @{
-  */
-
-/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in GPIO register
-  * @param  __INSTANCE__ GPIO Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in GPIO register
-  * @param  __INSTANCE__ GPIO Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
-  * @{
-  */
-
-/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
-  * @{
-  */
-
-/**
-  * @brief  Configure gpio mode for a dedicated pin on dedicated port.
-  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Mode This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_MODE_INPUT
-  *         @arg @ref LL_GPIO_MODE_OUTPUT
-  *         @arg @ref LL_GPIO_MODE_ALTERNATE
-  *         @arg @ref LL_GPIO_MODE_ANALOG
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
-{
-  MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
-}
-
-/**
-  * @brief  Return gpio mode for a dedicated pin on dedicated port.
-  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_MODE_INPUT
-  *         @arg @ref LL_GPIO_MODE_OUTPUT
-  *         @arg @ref LL_GPIO_MODE_ALTERNATE
-  *         @arg @ref LL_GPIO_MODE_ANALOG
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->MODER,
-                             (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
-}
-
-/**
-  * @brief  Configure gpio output type for several pins on dedicated port.
-  * @note   Output type as to be set when gpio pin is in output or
-  *         alternate modes. Possible type are Push-pull or Open-drain.
-  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @param  OutputType This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
-  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
-{
-  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
-}
-
-/**
-  * @brief  Return gpio output type for several pins on dedicated port.
-  * @note   Output type as to be set when gpio pin is in output or
-  *         alternate modes. Possible type are Push-pull or Open-drain.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
-  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
-}
-
-/**
-  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
-  * @note   I/O speed can be Low, Medium, Fast or High speed.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @note   Refer to datasheet for frequency specifications and the power
-  *         supply and load conditions for each speed.
-  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Speed This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
-  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
-  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
-  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
-{
-  MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
-             (Speed << (POSITION_VAL(Pin) * 2U)));
-}
-
-/**
-  * @brief  Return gpio speed for a dedicated pin on dedicated port.
-  * @note   I/O speed can be Low, Medium, Fast or High speed.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @note   Refer to datasheet for frequency specifications and the power
-  *         supply and load conditions for each speed.
-  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
-  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
-  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
-  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
-                             (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
-}
-
-/**
-  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Pull This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PULL_NO
-  *         @arg @ref LL_GPIO_PULL_UP
-  *         @arg @ref LL_GPIO_PULL_DOWN
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
-{
-  MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
-}
-
-/**
-  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_PULL_NO
-  *         @arg @ref LL_GPIO_PULL_UP
-  *         @arg @ref LL_GPIO_PULL_DOWN
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->PUPDR,
-                             (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
-}
-
-/**
-  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
-  * @note   Possible values are from AF0 to AF15 depending on target.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  * @param  Alternate This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  *         @arg @ref LL_GPIO_AF_8
-  *         @arg @ref LL_GPIO_AF_9
-  *         @arg @ref LL_GPIO_AF_10
-  *         @arg @ref LL_GPIO_AF_11
-  *         @arg @ref LL_GPIO_AF_12
-  *         @arg @ref LL_GPIO_AF_13
-  *         @arg @ref LL_GPIO_AF_14
-  *         @arg @ref LL_GPIO_AF_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
-{
-  MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
-             (Alternate << (POSITION_VAL(Pin) * 4U)));
-}
-
-/**
-  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
-  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  *         @arg @ref LL_GPIO_AF_8
-  *         @arg @ref LL_GPIO_AF_9
-  *         @arg @ref LL_GPIO_AF_10
-  *         @arg @ref LL_GPIO_AF_11
-  *         @arg @ref LL_GPIO_AF_12
-  *         @arg @ref LL_GPIO_AF_13
-  *         @arg @ref LL_GPIO_AF_14
-  *         @arg @ref LL_GPIO_AF_15
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->AFR[0],
-                             (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
-}
-
-/**
-  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
-  * @note   Possible values are from AF0 to AF15 depending on target.
-  * @note   Warning: only one pin can be passed as parameter.
-  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @param  Alternate This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  *         @arg @ref LL_GPIO_AF_8
-  *         @arg @ref LL_GPIO_AF_9
-  *         @arg @ref LL_GPIO_AF_10
-  *         @arg @ref LL_GPIO_AF_11
-  *         @arg @ref LL_GPIO_AF_12
-  *         @arg @ref LL_GPIO_AF_13
-  *         @arg @ref LL_GPIO_AF_14
-  *         @arg @ref LL_GPIO_AF_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
-{
-  MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
-             (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
-}
-
-/**
-  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
-  * @note   Possible values are from AF0 to AF15 depending on target.
-  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
-  * @param  GPIOx GPIO Port
-  * @param  Pin This parameter can be one of the following values:
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_GPIO_AF_0
-  *         @arg @ref LL_GPIO_AF_1
-  *         @arg @ref LL_GPIO_AF_2
-  *         @arg @ref LL_GPIO_AF_3
-  *         @arg @ref LL_GPIO_AF_4
-  *         @arg @ref LL_GPIO_AF_5
-  *         @arg @ref LL_GPIO_AF_6
-  *         @arg @ref LL_GPIO_AF_7
-  *         @arg @ref LL_GPIO_AF_8
-  *         @arg @ref LL_GPIO_AF_9
-  *         @arg @ref LL_GPIO_AF_10
-  *         @arg @ref LL_GPIO_AF_11
-  *         @arg @ref LL_GPIO_AF_12
-  *         @arg @ref LL_GPIO_AF_13
-  *         @arg @ref LL_GPIO_AF_14
-  *         @arg @ref LL_GPIO_AF_15
-  */
-__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
-{
-  return (uint32_t)(READ_BIT(GPIOx->AFR[1],
-                             (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
-}
-
-
-/**
-  * @brief  Lock configuration of several pins for a dedicated port.
-  * @note   When the lock sequence has been applied on a port bit, the
-  *         value of this port bit can no longer be modified until the
-  *         next reset.
-  * @note   Each lock bit freezes a specific configuration register
-  *         (control and alternate function registers).
-  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  __IO uint32_t temp;
-  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
-  WRITE_REG(GPIOx->LCKR, PinMask);
-  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
-  temp = READ_REG(GPIOx->LCKR);
-  (void) temp;
-}
-
-/**
-  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
-  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
-}
-
-/**
-  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
-  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
-  * @param  GPIOx GPIO Port
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
-{
-  return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_LL_EF_Data_Access Data Access
-  * @{
-  */
-
-/**
-  * @brief  Return full input data register value for a dedicated port.
-  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
-  * @param  GPIOx GPIO Port
-  * @retval Input data register value of port
-  */
-__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
-{
-  return (uint32_t)(READ_REG(GPIOx->IDR));
-}
-
-/**
-  * @brief  Return if input data level for several pins of dedicated port is high or low.
-  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
-}
-
-/**
-  * @brief  Write output data register for the port.
-  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
-  * @param  GPIOx GPIO Port
-  * @param  PortValue Level value for each pin of the port
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
-{
-  WRITE_REG(GPIOx->ODR, PortValue);
-}
-
-/**
-  * @brief  Return full output data register value for a dedicated port.
-  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
-  * @param  GPIOx GPIO Port
-  * @retval Output data register value of port
-  */
-__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
-{
-  return (uint32_t)(READ_REG(GPIOx->ODR));
-}
-
-/**
-  * @brief  Return if input data level for several pins of dedicated port is high or low.
-  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
-}
-
-/**
-  * @brief  Set several pins to high level on dedicated gpio port.
-  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  WRITE_REG(GPIOx->BSRR, PinMask);
-}
-
-/**
-  * @brief  Set several pins to low level on dedicated gpio port.
-  * @rmtoll BSRR         BRy           LL_GPIO_ResetOutputPin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  WRITE_REG(GPIOx->BSRR, (PinMask << 16));
-}
-
-/**
-  * @brief  Toggle data value for several pin of dedicated port.
-  * @rmtoll ODR          ODy           LL_GPIO_TogglePin
-  * @param  GPIOx GPIO Port
-  * @param  PinMask This parameter can be a combination of the following values:
-  *         @arg @ref LL_GPIO_PIN_0
-  *         @arg @ref LL_GPIO_PIN_1
-  *         @arg @ref LL_GPIO_PIN_2
-  *         @arg @ref LL_GPIO_PIN_3
-  *         @arg @ref LL_GPIO_PIN_4
-  *         @arg @ref LL_GPIO_PIN_5
-  *         @arg @ref LL_GPIO_PIN_6
-  *         @arg @ref LL_GPIO_PIN_7
-  *         @arg @ref LL_GPIO_PIN_8
-  *         @arg @ref LL_GPIO_PIN_9
-  *         @arg @ref LL_GPIO_PIN_10
-  *         @arg @ref LL_GPIO_PIN_11
-  *         @arg @ref LL_GPIO_PIN_12
-  *         @arg @ref LL_GPIO_PIN_13
-  *         @arg @ref LL_GPIO_PIN_14
-  *         @arg @ref LL_GPIO_PIN_15
-  *         @arg @ref LL_GPIO_PIN_ALL
-  * @retval None
-  */
-__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
-{
-  uint32_t odr = READ_REG(GPIOx->ODR);
-  WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-
-ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
-ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
-void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_LL_GPIO_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_gpio.h
+  * @author  MCD Application Team
+  * @brief   Header file of GPIO LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_GPIO_H
+#define __STM32F4xx_LL_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)
+
+/** @defgroup GPIO_LL GPIO
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL GPIO Init Structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.
+                              This parameter can be any value of @ref GPIO_LL_EC_PIN */
+
+  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_MODE.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
+
+  uint32_t Speed;        /*!< Specifies the speed for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
+
+  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
+
+  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_PULL.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
+
+  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.
+                              This parameter can be a value of @ref GPIO_LL_EC_AF.
+
+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
+} LL_GPIO_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EC_PIN PIN
+  * @{
+  */
+#define LL_GPIO_PIN_0                      GPIO_BSRR_BS_0 /*!< Select pin 0 */
+#define LL_GPIO_PIN_1                      GPIO_BSRR_BS_1 /*!< Select pin 1 */
+#define LL_GPIO_PIN_2                      GPIO_BSRR_BS_2 /*!< Select pin 2 */
+#define LL_GPIO_PIN_3                      GPIO_BSRR_BS_3 /*!< Select pin 3 */
+#define LL_GPIO_PIN_4                      GPIO_BSRR_BS_4 /*!< Select pin 4 */
+#define LL_GPIO_PIN_5                      GPIO_BSRR_BS_5 /*!< Select pin 5 */
+#define LL_GPIO_PIN_6                      GPIO_BSRR_BS_6 /*!< Select pin 6 */
+#define LL_GPIO_PIN_7                      GPIO_BSRR_BS_7 /*!< Select pin 7 */
+#define LL_GPIO_PIN_8                      GPIO_BSRR_BS_8 /*!< Select pin 8 */
+#define LL_GPIO_PIN_9                      GPIO_BSRR_BS_9 /*!< Select pin 9 */
+#define LL_GPIO_PIN_10                     GPIO_BSRR_BS_10 /*!< Select pin 10 */
+#define LL_GPIO_PIN_11                     GPIO_BSRR_BS_11 /*!< Select pin 11 */
+#define LL_GPIO_PIN_12                     GPIO_BSRR_BS_12 /*!< Select pin 12 */
+#define LL_GPIO_PIN_13                     GPIO_BSRR_BS_13 /*!< Select pin 13 */
+#define LL_GPIO_PIN_14                     GPIO_BSRR_BS_14 /*!< Select pin 14 */
+#define LL_GPIO_PIN_15                     GPIO_BSRR_BS_15 /*!< Select pin 15 */
+#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS_0 | GPIO_BSRR_BS_1  | GPIO_BSRR_BS_2  | \
+                                           GPIO_BSRR_BS_3  | GPIO_BSRR_BS_4  | GPIO_BSRR_BS_5  | \
+                                           GPIO_BSRR_BS_6  | GPIO_BSRR_BS_7  | GPIO_BSRR_BS_8  | \
+                                           GPIO_BSRR_BS_9  | GPIO_BSRR_BS_10 | GPIO_BSRR_BS_11 | \
+                                           GPIO_BSRR_BS_12 | GPIO_BSRR_BS_13 | GPIO_BSRR_BS_14 | \
+                                           GPIO_BSRR_BS_15) /*!< Select all pins */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_MODE Mode
+  * @{
+  */
+#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */
+#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODER0_0  /*!< Select output mode */
+#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODER0_1  /*!< Select alternate function mode */
+#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODER0    /*!< Select analog mode */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_OUTPUT Output Type
+  * @{
+  */
+#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */
+#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT_0 /*!< Select open-drain as output type */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_SPEED Output Speed
+  * @{
+  */
+#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */
+#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDER_OSPEEDR0_0 /*!< Select I/O medium output speed */
+#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDER_OSPEEDR0_1 /*!< Select I/O fast output speed   */
+#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDER_OSPEEDR0   /*!< Select I/O high output speed   */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
+  * @{
+  */
+#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */
+#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPDR0_0 /*!< Select I/O pull up */
+#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPDR0_1 /*!< Select I/O pull down */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EC_AF Alternate Function
+  * @{
+  */
+#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */
+#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */
+#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */
+#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */
+#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */
+#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */
+#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */
+#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */
+#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */
+#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */
+#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */
+#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */
+#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */
+#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */
+#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */
+#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in GPIO register
+  * @param  __INSTANCE__ GPIO Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
+  * @{
+  */
+
+/**
+  * @brief  Configure gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
+{
+  MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+  * @brief  Return gpio mode for a dedicated pin on dedicated port.
+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_MODE_INPUT
+  *         @arg @ref LL_GPIO_MODE_OUTPUT
+  *         @arg @ref LL_GPIO_MODE_ALTERNATE
+  *         @arg @ref LL_GPIO_MODE_ANALOG
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->MODER,
+                             (GPIO_MODER_MODER0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+  * @brief  Configure gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @param  OutputType This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
+{
+  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
+}
+
+/**
+  * @brief  Return gpio output type for several pins on dedicated port.
+  * @note   Output type as to be set when gpio pin is in output or
+  *         alternate modes. Possible type are Push-pull or Open-drain.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
+}
+
+/**
+  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Speed This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
+{
+  MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U)),
+             (Speed << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+  * @brief  Return gpio speed for a dedicated pin on dedicated port.
+  * @note   I/O speed can be Low, Medium, Fast or High speed.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @note   Refer to datasheet for frequency specifications and the power
+  *         supply and load conditions for each speed.
+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW
+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
+                             (GPIO_OSPEEDER_OSPEEDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Pull This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
+{
+  MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
+}
+
+/**
+  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_PULL_NO
+  *         @arg @ref LL_GPIO_PULL_UP
+  *         @arg @ref LL_GPIO_PULL_DOWN
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->PUPDR,
+                             (GPIO_PUPDR_PUPDR0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
+             (Alternate << (POSITION_VAL(Pin) * 4U)));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
+  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[0],
+                             (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
+}
+
+/**
+  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @note   Warning: only one pin can be passed as parameter.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @param  Alternate This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
+{
+  MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
+             (Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
+}
+
+/**
+  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
+  * @note   Possible values are from AF0 to AF15 depending on target.
+  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15
+  * @param  GPIOx GPIO Port
+  * @param  Pin This parameter can be one of the following values:
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_GPIO_AF_0
+  *         @arg @ref LL_GPIO_AF_1
+  *         @arg @ref LL_GPIO_AF_2
+  *         @arg @ref LL_GPIO_AF_3
+  *         @arg @ref LL_GPIO_AF_4
+  *         @arg @ref LL_GPIO_AF_5
+  *         @arg @ref LL_GPIO_AF_6
+  *         @arg @ref LL_GPIO_AF_7
+  *         @arg @ref LL_GPIO_AF_8
+  *         @arg @ref LL_GPIO_AF_9
+  *         @arg @ref LL_GPIO_AF_10
+  *         @arg @ref LL_GPIO_AF_11
+  *         @arg @ref LL_GPIO_AF_12
+  *         @arg @ref LL_GPIO_AF_13
+  *         @arg @ref LL_GPIO_AF_14
+  *         @arg @ref LL_GPIO_AF_15
+  */
+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
+{
+  return (uint32_t)(READ_BIT(GPIOx->AFR[1],
+                             (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
+}
+
+
+/**
+  * @brief  Lock configuration of several pins for a dedicated port.
+  * @note   When the lock sequence has been applied on a port bit, the
+  *         value of this port bit can no longer be modified until the
+  *         next reset.
+  * @note   Each lock bit freezes a specific configuration register
+  *         (control and alternate function registers).
+  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  __IO uint32_t temp;
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  WRITE_REG(GPIOx->LCKR, PinMask);
+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
+  temp = READ_REG(GPIOx->LCKR);
+  (void) temp;
+}
+
+/**
+  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
+  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask));
+}
+
+/**
+  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.
+  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked
+  * @param  GPIOx GPIO Port
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
+{
+  return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_LL_EF_Data_Access Data Access
+  * @{
+  */
+
+/**
+  * @brief  Return full input data register value for a dedicated port.
+  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort
+  * @param  GPIOx GPIO Port
+  * @retval Input data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->IDR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask));
+}
+
+/**
+  * @brief  Write output data register for the port.
+  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort
+  * @param  GPIOx GPIO Port
+  * @param  PortValue Level value for each pin of the port
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
+{
+  WRITE_REG(GPIOx->ODR, PortValue);
+}
+
+/**
+  * @brief  Return full output data register value for a dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort
+  * @param  GPIOx GPIO Port
+  * @retval Output data register value of port
+  */
+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
+{
+  return (uint32_t)(READ_REG(GPIOx->ODR));
+}
+
+/**
+  * @brief  Return if input data level for several pins of dedicated port is high or low.
+  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask));
+}
+
+/**
+  * @brief  Set several pins to high level on dedicated gpio port.
+  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BSRR, PinMask);
+}
+
+/**
+  * @brief  Set several pins to low level on dedicated gpio port.
+  * @rmtoll BSRR         BRy           LL_GPIO_ResetOutputPin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  WRITE_REG(GPIOx->BSRR, (PinMask << 16));
+}
+
+/**
+  * @brief  Toggle data value for several pin of dedicated port.
+  * @rmtoll ODR          ODy           LL_GPIO_TogglePin
+  * @param  GPIOx GPIO Port
+  * @param  PinMask This parameter can be a combination of the following values:
+  *         @arg @ref LL_GPIO_PIN_0
+  *         @arg @ref LL_GPIO_PIN_1
+  *         @arg @ref LL_GPIO_PIN_2
+  *         @arg @ref LL_GPIO_PIN_3
+  *         @arg @ref LL_GPIO_PIN_4
+  *         @arg @ref LL_GPIO_PIN_5
+  *         @arg @ref LL_GPIO_PIN_6
+  *         @arg @ref LL_GPIO_PIN_7
+  *         @arg @ref LL_GPIO_PIN_8
+  *         @arg @ref LL_GPIO_PIN_9
+  *         @arg @ref LL_GPIO_PIN_10
+  *         @arg @ref LL_GPIO_PIN_11
+  *         @arg @ref LL_GPIO_PIN_12
+  *         @arg @ref LL_GPIO_PIN_13
+  *         @arg @ref LL_GPIO_PIN_14
+  *         @arg @ref LL_GPIO_PIN_15
+  *         @arg @ref LL_GPIO_PIN_ALL
+  * @retval None
+  */
+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
+{
+  uint32_t odr = READ_REG(GPIOx->ODR);
+  WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
+void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_GPIO_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h
index ea23dc5..f40e079 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_pwr.h
@@ -1,985 +1,985 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_ll_pwr.h
-  * @author  MCD Application Team
-  * @brief   Header file of PWR LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_PWR_H
-#define __STM32F4xx_LL_PWR_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_LL_Driver
-  * @{
-  */
-
-#if defined(PWR)
-
-/** @defgroup PWR_LL PWR
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
-  * @{
-  */
-
-/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
-  * @{
-  */
-#define LL_PWR_CR_CSBF                     PWR_CR_CSBF            /*!< Clear standby flag */
-#define LL_PWR_CR_CWUF                     PWR_CR_CWUF            /*!< Clear wakeup flag */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_PWR_ReadReg function
-  * @{
-  */
-#define LL_PWR_CSR_WUF                     PWR_CSR_WUF            /*!< Wakeup flag */
-#define LL_PWR_CSR_SBF                     PWR_CSR_SBF            /*!< Standby flag */
-#define LL_PWR_CSR_PVDO                    PWR_CSR_PVDO           /*!< Power voltage detector output flag */
-#define LL_PWR_CSR_VOS                     PWR_CSR_VOSRDY            /*!< Voltage scaling select flag */
-#if defined(PWR_CSR_EWUP)
-#define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP           /*!< Enable WKUP pin */
-#elif defined(PWR_CSR_EWUP1)
-#define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP1          /*!< Enable WKUP pin 1 */
-#endif /* PWR_CSR_EWUP */
-#if defined(PWR_CSR_EWUP2)
-#define LL_PWR_CSR_EWUP2                   PWR_CSR_EWUP2          /*!< Enable WKUP pin 2 */
-#endif /* PWR_CSR_EWUP2 */
-#if defined(PWR_CSR_EWUP3)
-#define LL_PWR_CSR_EWUP3                   PWR_CSR_EWUP3          /*!< Enable WKUP pin 3 */
-#endif /* PWR_CSR_EWUP3 */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
-  * @{
-  */
-#if defined(PWR_CR_VOS_0)
-#define LL_PWR_REGU_VOLTAGE_SCALE3         (PWR_CR_VOS_0)
-#define LL_PWR_REGU_VOLTAGE_SCALE2         (PWR_CR_VOS_1)
-#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */
-#else
-#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR_VOS)
-#define LL_PWR_REGU_VOLTAGE_SCALE2         0x00000000U
-#endif /* PWR_CR_VOS_0 */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
-  * @{
-  */
-#define LL_PWR_MODE_STOP_MAINREGU             0x00000000U                    /*!< Enter Stop mode when the CPU enters deepsleep */
-#define LL_PWR_MODE_STOP_LPREGU               (PWR_CR_LPDS)                  /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
-#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
-#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE  (PWR_CR_MRUDS | PWR_CR_FPDS)                 /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */
-#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE    (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS)   /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */
-#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
-#if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
-#define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP  (PWR_CR_MRLVDS | PWR_CR_FPDS)                 /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */
-#define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP    (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS)   /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */
-#endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */
-#define LL_PWR_MODE_STANDBY                   (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
- * @{
- */
-#define LL_PWR_REGU_DSMODE_MAIN        0x00000000U           /*!< Voltage Regulator in main mode during deepsleep mode */
-#define LL_PWR_REGU_DSMODE_LOW_POWER   (PWR_CR_LPDS)         /*!< Voltage Regulator in low-power mode during deepsleep mode */
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
-  * @{
-  */
-#define LL_PWR_PVDLEVEL_0                  (PWR_CR_PLS_LEV0)      /*!< Voltage threshold detected by PVD 2.2 V */
-#define LL_PWR_PVDLEVEL_1                  (PWR_CR_PLS_LEV1)      /*!< Voltage threshold detected by PVD 2.3 V */
-#define LL_PWR_PVDLEVEL_2                  (PWR_CR_PLS_LEV2)      /*!< Voltage threshold detected by PVD 2.4 V */
-#define LL_PWR_PVDLEVEL_3                  (PWR_CR_PLS_LEV3)      /*!< Voltage threshold detected by PVD 2.5 V */
-#define LL_PWR_PVDLEVEL_4                  (PWR_CR_PLS_LEV4)      /*!< Voltage threshold detected by PVD 2.6 V */
-#define LL_PWR_PVDLEVEL_5                  (PWR_CR_PLS_LEV5)      /*!< Voltage threshold detected by PVD 2.7 V */
-#define LL_PWR_PVDLEVEL_6                  (PWR_CR_PLS_LEV6)      /*!< Voltage threshold detected by PVD 2.8 V */
-#define LL_PWR_PVDLEVEL_7                  (PWR_CR_PLS_LEV7)      /*!< Voltage threshold detected by PVD 2.9 V */
-/**
-  * @}
-  */
-/** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
-  * @{
-  */
-#if defined(PWR_CSR_EWUP)
-#define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP)         /*!< WKUP pin : PA0 */
-#endif /* PWR_CSR_EWUP */
-#if defined(PWR_CSR_EWUP1)
-#define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP1)        /*!< WKUP pin 1 : PA0 */
-#endif /* PWR_CSR_EWUP1 */
-#if defined(PWR_CSR_EWUP2)
-#define LL_PWR_WAKEUP_PIN2                 (PWR_CSR_EWUP2)        /*!< WKUP pin 2 : PC0 or PC13 according to device */
-#endif /* PWR_CSR_EWUP2 */
-#if defined(PWR_CSR_EWUP3)
-#define LL_PWR_WAKEUP_PIN3                 (PWR_CSR_EWUP3)        /*!< WKUP pin 3 : PC1 */
-#endif /* PWR_CSR_EWUP3 */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
-  * @{
-  */
-
-/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in PWR register
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in PWR register
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
-  * @{
-  */
-
-/** @defgroup PWR_LL_EF_Configuration Configuration
-  * @{
-  */
-#if defined(PWR_CR_FISSR)
-/**
-  * @brief  Enable FLASH interface STOP while system Run is ON
-  * @rmtoll CR    FISSR       LL_PWR_EnableFLASHInterfaceSTOP
-  * @note  This mode is enabled only with STOP low power mode.
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_FISSR);
-}
-
-/**
-  * @brief  Disable FLASH Interface STOP while system Run is ON
-  * @rmtoll CR    FISSR       LL_PWR_DisableFLASHInterfaceSTOP
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
-}
-
-/**
-  * @brief  Check if FLASH Interface STOP while system Run feature is enabled
-  * @rmtoll CR    FISSR       LL_PWR_IsEnabledFLASHInterfaceSTOP
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR));
-}
-#endif /* PWR_CR_FISSR */
-
-#if defined(PWR_CR_FMSSR)
-/**
-  * @brief  Enable FLASH Memory STOP while system Run is ON
-  * @rmtoll CR    FMSSR       LL_PWR_EnableFLASHMemorySTOP
-  * @note  This mode is enabled only with STOP low power mode.
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_FMSSR);
-}
-
-/**
-  * @brief  Disable FLASH Memory STOP while system Run is ON
-  * @rmtoll CR    FMSSR       LL_PWR_DisableFLASHMemorySTOP
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
-}
-
-/**
-  * @brief  Check if FLASH Memory STOP while system Run feature is enabled
-  * @rmtoll CR    FMSSR       LL_PWR_IsEnabledFLASHMemorySTOP
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR));
-}
-#endif /* PWR_CR_FMSSR */
-#if defined(PWR_CR_UDEN)
-/**
-  * @brief  Enable Under Drive Mode
-  * @rmtoll CR    UDEN       LL_PWR_EnableUnderDriveMode
-  * @note  This mode is enabled only with STOP low power mode.
-  *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
-  *        mode is only available when the main Regulator or the low power Regulator 
-  *        is in low voltage mode.      
-  * @note  If the Under-drive mode was enabled, it is automatically disabled after 
-  *        exiting Stop mode. 
-  *        When the voltage Regulator operates in Under-drive mode, an additional  
-  *        startup delay is induced when waking up from Stop mode.
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_UDEN);
-}
-
-/**
-  * @brief  Disable Under Drive Mode
-  * @rmtoll CR    UDEN       LL_PWR_DisableUnderDriveMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_UDEN);
-}
-
-/**
-  * @brief  Check if Under Drive Mode is enabled
-  * @rmtoll CR    UDEN       LL_PWR_IsEnabledUnderDriveMode
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN));
-}
-#endif /* PWR_CR_UDEN */
-
-#if defined(PWR_CR_ODSWEN)
-/**
-  * @brief  Enable Over drive switching
-  * @rmtoll CR    ODSWEN       LL_PWR_EnableOverDriveSwitching
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_ODSWEN);
-}
-
-/**
-  * @brief  Disable Over drive switching
-  * @rmtoll CR    ODSWEN       LL_PWR_DisableOverDriveSwitching
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN);
-}
-
-/**
-  * @brief  Check if Over drive switching is enabled
-  * @rmtoll CR    ODSWEN       LL_PWR_IsEnabledOverDriveSwitching
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN));
-}
-#endif /* PWR_CR_ODSWEN */
-#if defined(PWR_CR_ODEN)
-/**
-  * @brief  Enable Over drive Mode
-  * @rmtoll CR    ODEN       LL_PWR_EnableOverDriveMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_ODEN);
-}
-
-/**
-  * @brief  Disable Over drive Mode
-  * @rmtoll CR    ODEN       LL_PWR_DisableOverDriveMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_ODEN);
-}
-
-/**
-  * @brief  Check if Over drive switching is enabled
-  * @rmtoll CR    ODEN       LL_PWR_IsEnabledOverDriveMode
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN));
-}
-#endif /* PWR_CR_ODEN */
-#if defined(PWR_CR_MRUDS)
-/**
-  * @brief  Enable Main Regulator in deepsleep under-drive Mode
-  * @rmtoll CR    MRUDS       LL_PWR_EnableMainRegulatorDeepSleepUDMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_MRUDS);
-}
-
-/**
-  * @brief  Disable Main Regulator in deepsleep under-drive Mode
-  * @rmtoll CR    MRUDS       LL_PWR_DisableMainRegulatorDeepSleepUDMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_MRUDS);
-}
-
-/**
-  * @brief  Check if Main Regulator in deepsleep under-drive Mode is enabled
-  * @rmtoll CR    MRUDS       LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS));
-}
-#endif /* PWR_CR_MRUDS */
-
-#if defined(PWR_CR_LPUDS)
-/**
-  * @brief  Enable Low Power Regulator in deepsleep under-drive Mode
-  * @rmtoll CR    LPUDS       LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_LPUDS);
-}
-
-/**
-  * @brief  Disable Low Power Regulator in deepsleep under-drive Mode
-  * @rmtoll CR    LPUDS       LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_LPUDS);
-}
-
-/**
-  * @brief  Check if Low Power Regulator in deepsleep under-drive Mode is enabled
-  * @rmtoll CR    LPUDS       LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS));
-}
-#endif /* PWR_CR_LPUDS */
-
-#if defined(PWR_CR_MRLVDS)
-/**
-  * @brief  Enable Main Regulator low voltage Mode
-  * @rmtoll CR    MRLVDS       LL_PWR_EnableMainRegulatorLowVoltageMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_MRLVDS);
-}
-
-/**
-  * @brief  Disable Main Regulator low voltage Mode
-  * @rmtoll CR    MRLVDS       LL_PWR_DisableMainRegulatorLowVoltageMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS);
-}
-
-/**
-  * @brief  Check if Main Regulator low voltage Mode is enabled
-  * @rmtoll CR    MRLVDS       LL_PWR_IsEnabledMainRegulatorLowVoltageMode
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS));
-}
-#endif /* PWR_CR_MRLVDS */
-
-#if defined(PWR_CR_LPLVDS)
-/**
-  * @brief  Enable Low Power Regulator low voltage Mode
-  * @rmtoll CR    LPLVDS       LL_PWR_EnableLowPowerRegulatorLowVoltageMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_LPLVDS);
-}
-
-/**
-  * @brief  Disable Low Power Regulator low voltage Mode
-  * @rmtoll CR    LPLVDS       LL_PWR_DisableLowPowerRegulatorLowVoltageMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS);
-}
-
-/**
-  * @brief  Check if Low Power Regulator low voltage Mode is enabled
-  * @rmtoll CR    LPLVDS       LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS));
-}
-#endif /* PWR_CR_LPLVDS */
-/**
-  * @brief  Set the main internal Regulator output voltage
-  * @rmtoll CR    VOS       LL_PWR_SetRegulVoltageScaling
-  * @param  VoltageScaling This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
-  *         (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
-{
-  MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
-}
-
-/**
-  * @brief  Get the main internal Regulator output voltage
-  * @rmtoll CR    VOS       LL_PWR_GetRegulVoltageScaling
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
-  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
-  *         (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
-}
-/**
-  * @brief  Enable the Flash Power Down in Stop Mode
-  * @rmtoll CR    FPDS       LL_PWR_EnableFlashPowerDown
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_FPDS);
-}
-
-/**
-  * @brief  Disable the Flash Power Down in Stop Mode
-  * @rmtoll CR    FPDS       LL_PWR_DisableFlashPowerDown
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_FPDS);
-}
-
-/**
-  * @brief  Check if the Flash Power Down in Stop Mode is enabled
-  * @rmtoll CR    FPDS       LL_PWR_IsEnabledFlashPowerDown
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));
-}
-
-/**
-  * @brief  Enable access to the backup domain
-  * @rmtoll CR    DBP       LL_PWR_EnableBkUpAccess
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
-  * @brief  Disable access to the backup domain
-  * @rmtoll CR    DBP       LL_PWR_DisableBkUpAccess
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_DBP);
-}
-
-/**
-  * @brief  Check if the backup domain is enabled
-  * @rmtoll CR    DBP       LL_PWR_IsEnabledBkUpAccess
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
-}
-/**
-  * @brief  Enable the backup Regulator
-  * @rmtoll CSR    BRE       LL_PWR_EnableBkUpRegulator
-  * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
-  * The LL_PWR_EnableBkUpAccess() must be called before using this API.
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
-{
-  SET_BIT(PWR->CSR, PWR_CSR_BRE);
-}
-
-/**
-  * @brief  Disable the backup Regulator
-  * @rmtoll CSR    BRE       LL_PWR_DisableBkUpRegulator
-  * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
-  * The LL_PWR_EnableBkUpAccess() must be called before using this API.
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
-{
-  CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);
-}
-
-/**
-  * @brief  Check if the backup Regulator is enabled
-  * @rmtoll CSR    BRE       LL_PWR_IsEnabledBkUpRegulator
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
-{
-  return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));
-}
-
-/**
-  * @brief  Set voltage Regulator mode during deep sleep mode
-  * @rmtoll CR    LPDS         LL_PWR_SetRegulModeDS
-  * @param  RegulMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
-  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
-{
-  MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
-}
-
-/**
-  * @brief  Get voltage Regulator mode during deep sleep mode
-  * @rmtoll CR    LPDS         LL_PWR_GetRegulModeDS
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
-  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
-}
-
-/**
-  * @brief  Set Power Down mode when CPU enters deepsleep
-  * @rmtoll CR    PDDS         LL_PWR_SetPowerMode\n
-  * @rmtoll CR    MRUDS        LL_PWR_SetPowerMode\n
-  * @rmtoll CR    LPUDS        LL_PWR_SetPowerMode\n
-  * @rmtoll CR    FPDS         LL_PWR_SetPowerMode\n
-  * @rmtoll CR    MRLVDS       LL_PWR_SetPowerMode\n
-  * @rmtoll CR    LPlVDS       LL_PWR_SetPowerMode\n
-  * @rmtoll CR    FPDS         LL_PWR_SetPowerMode\n
-  * @rmtoll CR    LPDS         LL_PWR_SetPowerMode
-  * @param  PDMode This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
-  *         @arg @ref LL_PWR_MODE_STOP_LPREGU
-  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
-  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
-  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
-  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
-  *
-  *         (*) not available on all devices
-  *         @arg @ref LL_PWR_MODE_STANDBY
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
-{
-#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
-  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode);
-#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
-  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode);
-#else
-  MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
-#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
-}
-
-/**
-  * @brief  Get Power Down mode when CPU enters deepsleep
-  * @rmtoll CR    PDDS         LL_PWR_GetPowerMode\n
-  * @rmtoll CR    MRUDS        LL_PWR_GetPowerMode\n
-  * @rmtoll CR    LPUDS        LL_PWR_GetPowerMode\n
-  * @rmtoll CR    FPDS         LL_PWR_GetPowerMode\n
-  * @rmtoll CR    MRLVDS       LL_PWR_GetPowerMode\n
-  * @rmtoll CR    LPLVDS       LL_PWR_GetPowerMode\n
-  * @rmtoll CR    FPDS         LL_PWR_GetPowerMode\n
-  * @rmtoll CR    LPDS         LL_PWR_GetPowerMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
-  *         @arg @ref LL_PWR_MODE_STOP_LPREGU
-  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
-  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
-  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
-  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
-  *
-  *         (*) not available on all devices
-  *         @arg @ref LL_PWR_MODE_STANDBY
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
-{
-#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
-  return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS)));
-#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
-  return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS)));
-#else
-  return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
-#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
-}
-
-/**
-  * @brief  Configure the voltage threshold detected by the Power Voltage Detector
-  * @rmtoll CR    PLS       LL_PWR_SetPVDLevel
-  * @param  PVDLevel This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_PVDLEVEL_0
-  *         @arg @ref LL_PWR_PVDLEVEL_1
-  *         @arg @ref LL_PWR_PVDLEVEL_2
-  *         @arg @ref LL_PWR_PVDLEVEL_3
-  *         @arg @ref LL_PWR_PVDLEVEL_4
-  *         @arg @ref LL_PWR_PVDLEVEL_5
-  *         @arg @ref LL_PWR_PVDLEVEL_6
-  *         @arg @ref LL_PWR_PVDLEVEL_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
-{
-  MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
-}
-
-/**
-  * @brief  Get the voltage threshold detection
-  * @rmtoll CR    PLS       LL_PWR_GetPVDLevel
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_PWR_PVDLEVEL_0
-  *         @arg @ref LL_PWR_PVDLEVEL_1
-  *         @arg @ref LL_PWR_PVDLEVEL_2
-  *         @arg @ref LL_PWR_PVDLEVEL_3
-  *         @arg @ref LL_PWR_PVDLEVEL_4
-  *         @arg @ref LL_PWR_PVDLEVEL_5
-  *         @arg @ref LL_PWR_PVDLEVEL_6
-  *         @arg @ref LL_PWR_PVDLEVEL_7
-  */
-__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
-{
-  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
-}
-
-/**
-  * @brief  Enable Power Voltage Detector
-  * @rmtoll CR    PVDE       LL_PWR_EnablePVD
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnablePVD(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
-  * @brief  Disable Power Voltage Detector
-  * @rmtoll CR    PVDE       LL_PWR_DisablePVD
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisablePVD(void)
-{
-  CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
-}
-
-/**
-  * @brief  Check if Power Voltage Detector is enabled
-  * @rmtoll CR    PVDE       LL_PWR_IsEnabledPVD
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
-{
-  return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
-}
-
-/**
-  * @brief  Enable the WakeUp PINx functionality
-  * @rmtoll CSR   EWUP        LL_PWR_EnableWakeUpPin\n
-  * @rmtoll CSR   EWUP1       LL_PWR_EnableWakeUpPin\n
-  * @rmtoll CSR   EWUP2       LL_PWR_EnableWakeUpPin\n
-  * @rmtoll CSR   EWUP3       LL_PWR_EnableWakeUpPin
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *
-  *         (*) not available on all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
-{
-  SET_BIT(PWR->CSR, WakeUpPin);
-}
-
-/**
-  * @brief  Disable the WakeUp PINx functionality
-  * @rmtoll CSR   EWUP        LL_PWR_DisableWakeUpPin\n
-  * @rmtoll CSR   EWUP1       LL_PWR_DisableWakeUpPin\n
-  * @rmtoll CSR   EWUP2       LL_PWR_DisableWakeUpPin\n
-  * @rmtoll CSR   EWUP3       LL_PWR_DisableWakeUpPin
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *
-  *         (*) not available on all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
-{
-  CLEAR_BIT(PWR->CSR, WakeUpPin);
-}
-
-/**
-  * @brief  Check if the WakeUp PINx functionality is enabled
-  * @rmtoll CSR   EWUP        LL_PWR_IsEnabledWakeUpPin\n
-  * @rmtoll CSR   EWUP1       LL_PWR_IsEnabledWakeUpPin\n
-  * @rmtoll CSR   EWUP2       LL_PWR_IsEnabledWakeUpPin\n
-  * @rmtoll CSR   EWUP3       LL_PWR_IsEnabledWakeUpPin
-  * @param  WakeUpPin This parameter can be one of the following values:
-  *         @arg @ref LL_PWR_WAKEUP_PIN1
-  *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
-  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
-  *
-  *         (*) not available on all devices
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
-{
-  return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Get Wake-up Flag
-  * @rmtoll CSR   WUF       LL_PWR_IsActiveFlag_WU
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
-{
-  return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
-}
-
-/**
-  * @brief  Get Standby Flag
-  * @rmtoll CSR   SBF       LL_PWR_IsActiveFlag_SB
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
-{
-  return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
-}
-
-/**
-  * @brief  Get Backup Regulator ready Flag
-  * @rmtoll CSR   BRR       LL_PWR_IsActiveFlag_BRR
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
-{
-  return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));
-}
-/**
-  * @brief  Indicate whether VDD voltage is below the selected PVD threshold
-  * @rmtoll CSR   PVDO       LL_PWR_IsActiveFlag_PVDO
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
-{
-  return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
-}
-
-/**
-  * @brief  Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
-  * @rmtoll CSR   VOS       LL_PWR_IsActiveFlag_VOS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
-{
-  return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
-}
-#if defined(PWR_CR_ODEN)
-/**
-  * @brief  Indicate whether the Over-Drive mode is ready or not
-  * @rmtoll CSR   ODRDY       LL_PWR_IsActiveFlag_OD
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
-{
-  return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY));
-}
-#endif /* PWR_CR_ODEN */
-
-#if defined(PWR_CR_ODSWEN)
-/**
-  * @brief  Indicate whether the Over-Drive mode switching is ready or not
-  * @rmtoll CSR   ODSWRDY       LL_PWR_IsActiveFlag_ODSW
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
-{
-  return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY));
-}
-#endif /* PWR_CR_ODSWEN */
-
-#if defined(PWR_CR_UDEN)
-/**
-  * @brief  Indicate whether the Under-Drive mode is ready or not
-  * @rmtoll CSR   UDRDY       LL_PWR_IsActiveFlag_UD
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
-{
-  return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY));
-}
-#endif /* PWR_CR_UDEN */
-/**
-  * @brief  Clear Standby Flag
-  * @rmtoll CR   CSBF       LL_PWR_ClearFlag_SB
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_CSBF);
-}
-
-/**
-  * @brief  Clear Wake-up Flags
-  * @rmtoll CR   CWUF       LL_PWR_ClearFlag_WU
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
-{
-  SET_BIT(PWR->CR, PWR_CR_CWUF);
-}
-#if defined(PWR_CSR_UDRDY)
-/**
-  * @brief  Clear Under-Drive ready Flag
-  * @rmtoll CSR          UDRDY         LL_PWR_ClearFlag_UD
-  * @retval None
-  */
-__STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
-{
-  WRITE_REG(PWR->CSR, PWR_CSR_UDRDY);
-}
-#endif /* PWR_CSR_UDRDY */
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup PWR_LL_EF_Init De-initialization function
-  * @{
-  */
-ErrorStatus LL_PWR_DeInit(void);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(PWR) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_LL_PWR_H */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_pwr.h
+  * @author  MCD Application Team
+  * @brief   Header file of PWR LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_PWR_H
+#define __STM32F4xx_LL_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined(PWR)
+
+/** @defgroup PWR_LL PWR
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_WriteReg function
+  * @{
+  */
+#define LL_PWR_CR_CSBF                     PWR_CR_CSBF            /*!< Clear standby flag */
+#define LL_PWR_CR_CWUF                     PWR_CR_CWUF            /*!< Clear wakeup flag */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_PWR_ReadReg function
+  * @{
+  */
+#define LL_PWR_CSR_WUF                     PWR_CSR_WUF            /*!< Wakeup flag */
+#define LL_PWR_CSR_SBF                     PWR_CSR_SBF            /*!< Standby flag */
+#define LL_PWR_CSR_PVDO                    PWR_CSR_PVDO           /*!< Power voltage detector output flag */
+#define LL_PWR_CSR_VOS                     PWR_CSR_VOSRDY            /*!< Voltage scaling select flag */
+#if defined(PWR_CSR_EWUP)
+#define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP           /*!< Enable WKUP pin */
+#elif defined(PWR_CSR_EWUP1)
+#define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP1          /*!< Enable WKUP pin 1 */
+#endif /* PWR_CSR_EWUP */
+#if defined(PWR_CSR_EWUP2)
+#define LL_PWR_CSR_EWUP2                   PWR_CSR_EWUP2          /*!< Enable WKUP pin 2 */
+#endif /* PWR_CSR_EWUP2 */
+#if defined(PWR_CSR_EWUP3)
+#define LL_PWR_CSR_EWUP3                   PWR_CSR_EWUP3          /*!< Enable WKUP pin 3 */
+#endif /* PWR_CSR_EWUP3 */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_VOLTAGE Regulator Voltage
+  * @{
+  */
+#if defined(PWR_CR_VOS_0)
+#define LL_PWR_REGU_VOLTAGE_SCALE3         (PWR_CR_VOS_0)
+#define LL_PWR_REGU_VOLTAGE_SCALE2         (PWR_CR_VOS_1)
+#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */
+#else
+#define LL_PWR_REGU_VOLTAGE_SCALE1         (PWR_CR_VOS)
+#define LL_PWR_REGU_VOLTAGE_SCALE2         0x00000000U
+#endif /* PWR_CR_VOS_0 */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_MODE_PWR Mode Power
+  * @{
+  */
+#define LL_PWR_MODE_STOP_MAINREGU             0x00000000U                    /*!< Enter Stop mode when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU               (PWR_CR_LPDS)                  /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
+#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
+#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE  (PWR_CR_MRUDS | PWR_CR_FPDS)                 /*!< Enter Stop mode (with main Regulator in under-drive mode) when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE    (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS)   /*!< Enter Stop mode (with low power Regulator in under-drive mode) when the CPU enters deepsleep */
+#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
+#if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
+#define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP  (PWR_CR_MRLVDS | PWR_CR_FPDS)                 /*!< Enter Stop mode (with main Regulator in Deep Sleep mode) when the CPU enters deepsleep */
+#define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP    (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS)   /*!< Enter Stop mode (with low power Regulator in Deep Sleep mode) when the CPU enters deepsleep */
+#endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */
+#define LL_PWR_MODE_STANDBY                   (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
+ * @{
+ */
+#define LL_PWR_REGU_DSMODE_MAIN        0x00000000U           /*!< Voltage Regulator in main mode during deepsleep mode */
+#define LL_PWR_REGU_DSMODE_LOW_POWER   (PWR_CR_LPDS)         /*!< Voltage Regulator in low-power mode during deepsleep mode */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
+  * @{
+  */
+#define LL_PWR_PVDLEVEL_0                  (PWR_CR_PLS_LEV0)      /*!< Voltage threshold detected by PVD 2.2 V */
+#define LL_PWR_PVDLEVEL_1                  (PWR_CR_PLS_LEV1)      /*!< Voltage threshold detected by PVD 2.3 V */
+#define LL_PWR_PVDLEVEL_2                  (PWR_CR_PLS_LEV2)      /*!< Voltage threshold detected by PVD 2.4 V */
+#define LL_PWR_PVDLEVEL_3                  (PWR_CR_PLS_LEV3)      /*!< Voltage threshold detected by PVD 2.5 V */
+#define LL_PWR_PVDLEVEL_4                  (PWR_CR_PLS_LEV4)      /*!< Voltage threshold detected by PVD 2.6 V */
+#define LL_PWR_PVDLEVEL_5                  (PWR_CR_PLS_LEV5)      /*!< Voltage threshold detected by PVD 2.7 V */
+#define LL_PWR_PVDLEVEL_6                  (PWR_CR_PLS_LEV6)      /*!< Voltage threshold detected by PVD 2.8 V */
+#define LL_PWR_PVDLEVEL_7                  (PWR_CR_PLS_LEV7)      /*!< Voltage threshold detected by PVD 2.9 V */
+/**
+  * @}
+  */
+/** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
+  * @{
+  */
+#if defined(PWR_CSR_EWUP)
+#define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP)         /*!< WKUP pin : PA0 */
+#endif /* PWR_CSR_EWUP */
+#if defined(PWR_CSR_EWUP1)
+#define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP1)        /*!< WKUP pin 1 : PA0 */
+#endif /* PWR_CSR_EWUP1 */
+#if defined(PWR_CSR_EWUP2)
+#define LL_PWR_WAKEUP_PIN2                 (PWR_CSR_EWUP2)        /*!< WKUP pin 2 : PC0 or PC13 according to device */
+#endif /* PWR_CSR_EWUP2 */
+#if defined(PWR_CSR_EWUP3)
+#define LL_PWR_WAKEUP_PIN3                 (PWR_CSR_EWUP3)        /*!< WKUP pin 3 : PC1 */
+#endif /* PWR_CSR_EWUP3 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
+  * @{
+  */
+
+/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in PWR register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in PWR register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_LL_EF_Configuration Configuration
+  * @{
+  */
+#if defined(PWR_CR_FISSR)
+/**
+  * @brief  Enable FLASH interface STOP while system Run is ON
+  * @rmtoll CR    FISSR       LL_PWR_EnableFLASHInterfaceSTOP
+  * @note  This mode is enabled only with STOP low power mode.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_FISSR);
+}
+
+/**
+  * @brief  Disable FLASH Interface STOP while system Run is ON
+  * @rmtoll CR    FISSR       LL_PWR_DisableFLASHInterfaceSTOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
+}
+
+/**
+  * @brief  Check if FLASH Interface STOP while system Run feature is enabled
+  * @rmtoll CR    FISSR       LL_PWR_IsEnabledFLASHInterfaceSTOP
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR));
+}
+#endif /* PWR_CR_FISSR */
+
+#if defined(PWR_CR_FMSSR)
+/**
+  * @brief  Enable FLASH Memory STOP while system Run is ON
+  * @rmtoll CR    FMSSR       LL_PWR_EnableFLASHMemorySTOP
+  * @note  This mode is enabled only with STOP low power mode.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_FMSSR);
+}
+
+/**
+  * @brief  Disable FLASH Memory STOP while system Run is ON
+  * @rmtoll CR    FMSSR       LL_PWR_DisableFLASHMemorySTOP
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
+}
+
+/**
+  * @brief  Check if FLASH Memory STOP while system Run feature is enabled
+  * @rmtoll CR    FMSSR       LL_PWR_IsEnabledFLASHMemorySTOP
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR));
+}
+#endif /* PWR_CR_FMSSR */
+#if defined(PWR_CR_UDEN)
+/**
+  * @brief  Enable Under Drive Mode
+  * @rmtoll CR    UDEN       LL_PWR_EnableUnderDriveMode
+  * @note  This mode is enabled only with STOP low power mode.
+  *        In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
+  *        mode is only available when the main Regulator or the low power Regulator 
+  *        is in low voltage mode.      
+  * @note  If the Under-drive mode was enabled, it is automatically disabled after 
+  *        exiting Stop mode. 
+  *        When the voltage Regulator operates in Under-drive mode, an additional  
+  *        startup delay is induced when waking up from Stop mode.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_UDEN);
+}
+
+/**
+  * @brief  Disable Under Drive Mode
+  * @rmtoll CR    UDEN       LL_PWR_DisableUnderDriveMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_UDEN);
+}
+
+/**
+  * @brief  Check if Under Drive Mode is enabled
+  * @rmtoll CR    UDEN       LL_PWR_IsEnabledUnderDriveMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN));
+}
+#endif /* PWR_CR_UDEN */
+
+#if defined(PWR_CR_ODSWEN)
+/**
+  * @brief  Enable Over drive switching
+  * @rmtoll CR    ODSWEN       LL_PWR_EnableOverDriveSwitching
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_ODSWEN);
+}
+
+/**
+  * @brief  Disable Over drive switching
+  * @rmtoll CR    ODSWEN       LL_PWR_DisableOverDriveSwitching
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN);
+}
+
+/**
+  * @brief  Check if Over drive switching is enabled
+  * @rmtoll CR    ODSWEN       LL_PWR_IsEnabledOverDriveSwitching
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN));
+}
+#endif /* PWR_CR_ODSWEN */
+#if defined(PWR_CR_ODEN)
+/**
+  * @brief  Enable Over drive Mode
+  * @rmtoll CR    ODEN       LL_PWR_EnableOverDriveMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_ODEN);
+}
+
+/**
+  * @brief  Disable Over drive Mode
+  * @rmtoll CR    ODEN       LL_PWR_DisableOverDriveMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_ODEN);
+}
+
+/**
+  * @brief  Check if Over drive switching is enabled
+  * @rmtoll CR    ODEN       LL_PWR_IsEnabledOverDriveMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN));
+}
+#endif /* PWR_CR_ODEN */
+#if defined(PWR_CR_MRUDS)
+/**
+  * @brief  Enable Main Regulator in deepsleep under-drive Mode
+  * @rmtoll CR    MRUDS       LL_PWR_EnableMainRegulatorDeepSleepUDMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_MRUDS);
+}
+
+/**
+  * @brief  Disable Main Regulator in deepsleep under-drive Mode
+  * @rmtoll CR    MRUDS       LL_PWR_DisableMainRegulatorDeepSleepUDMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_MRUDS);
+}
+
+/**
+  * @brief  Check if Main Regulator in deepsleep under-drive Mode is enabled
+  * @rmtoll CR    MRUDS       LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS));
+}
+#endif /* PWR_CR_MRUDS */
+
+#if defined(PWR_CR_LPUDS)
+/**
+  * @brief  Enable Low Power Regulator in deepsleep under-drive Mode
+  * @rmtoll CR    LPUDS       LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_LPUDS);
+}
+
+/**
+  * @brief  Disable Low Power Regulator in deepsleep under-drive Mode
+  * @rmtoll CR    LPUDS       LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_LPUDS);
+}
+
+/**
+  * @brief  Check if Low Power Regulator in deepsleep under-drive Mode is enabled
+  * @rmtoll CR    LPUDS       LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS));
+}
+#endif /* PWR_CR_LPUDS */
+
+#if defined(PWR_CR_MRLVDS)
+/**
+  * @brief  Enable Main Regulator low voltage Mode
+  * @rmtoll CR    MRLVDS       LL_PWR_EnableMainRegulatorLowVoltageMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_MRLVDS);
+}
+
+/**
+  * @brief  Disable Main Regulator low voltage Mode
+  * @rmtoll CR    MRLVDS       LL_PWR_DisableMainRegulatorLowVoltageMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS);
+}
+
+/**
+  * @brief  Check if Main Regulator low voltage Mode is enabled
+  * @rmtoll CR    MRLVDS       LL_PWR_IsEnabledMainRegulatorLowVoltageMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS));
+}
+#endif /* PWR_CR_MRLVDS */
+
+#if defined(PWR_CR_LPLVDS)
+/**
+  * @brief  Enable Low Power Regulator low voltage Mode
+  * @rmtoll CR    LPLVDS       LL_PWR_EnableLowPowerRegulatorLowVoltageMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_LPLVDS);
+}
+
+/**
+  * @brief  Disable Low Power Regulator low voltage Mode
+  * @rmtoll CR    LPLVDS       LL_PWR_DisableLowPowerRegulatorLowVoltageMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS);
+}
+
+/**
+  * @brief  Check if Low Power Regulator low voltage Mode is enabled
+  * @rmtoll CR    LPLVDS       LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS));
+}
+#endif /* PWR_CR_LPLVDS */
+/**
+  * @brief  Set the main internal Regulator output voltage
+  * @rmtoll CR    VOS       LL_PWR_SetRegulVoltageScaling
+  * @param  VoltageScaling This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+  *         (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
+{
+  MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
+}
+
+/**
+  * @brief  Get the main internal Regulator output voltage
+  * @rmtoll CR    VOS       LL_PWR_GetRegulVoltageScaling
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 (*)
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
+  *         (*) LL_PWR_REGU_VOLTAGE_SCALE1 is not available for STM32F401xx devices
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
+}
+/**
+  * @brief  Enable the Flash Power Down in Stop Mode
+  * @rmtoll CR    FPDS       LL_PWR_EnableFlashPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_FPDS);
+}
+
+/**
+  * @brief  Disable the Flash Power Down in Stop Mode
+  * @rmtoll CR    FPDS       LL_PWR_DisableFlashPowerDown
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_FPDS);
+}
+
+/**
+  * @brief  Check if the Flash Power Down in Stop Mode is enabled
+  * @rmtoll CR    FPDS       LL_PWR_IsEnabledFlashPowerDown
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));
+}
+
+/**
+  * @brief  Enable access to the backup domain
+  * @rmtoll CR    DBP       LL_PWR_EnableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+  * @brief  Disable access to the backup domain
+  * @rmtoll CR    DBP       LL_PWR_DisableBkUpAccess
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_DBP);
+}
+
+/**
+  * @brief  Check if the backup domain is enabled
+  * @rmtoll CR    DBP       LL_PWR_IsEnabledBkUpAccess
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
+}
+/**
+  * @brief  Enable the backup Regulator
+  * @rmtoll CSR    BRE       LL_PWR_EnableBkUpRegulator
+  * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
+  * The LL_PWR_EnableBkUpAccess() must be called before using this API.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
+{
+  SET_BIT(PWR->CSR, PWR_CSR_BRE);
+}
+
+/**
+  * @brief  Disable the backup Regulator
+  * @rmtoll CSR    BRE       LL_PWR_DisableBkUpRegulator
+  * @note The BRE bit of the PWR_CSR register is protected against parasitic write access.
+  * The LL_PWR_EnableBkUpAccess() must be called before using this API.
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
+{
+  CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);
+}
+
+/**
+  * @brief  Check if the backup Regulator is enabled
+  * @rmtoll CSR    BRE       LL_PWR_IsEnabledBkUpRegulator
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));
+}
+
+/**
+  * @brief  Set voltage Regulator mode during deep sleep mode
+  * @rmtoll CR    LPDS         LL_PWR_SetRegulModeDS
+  * @param  RegulMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
+  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
+{
+  MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
+}
+
+/**
+  * @brief  Get voltage Regulator mode during deep sleep mode
+  * @rmtoll CR    LPDS         LL_PWR_GetRegulModeDS
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
+  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
+}
+
+/**
+  * @brief  Set Power Down mode when CPU enters deepsleep
+  * @rmtoll CR    PDDS         LL_PWR_SetPowerMode\n
+  * @rmtoll CR    MRUDS        LL_PWR_SetPowerMode\n
+  * @rmtoll CR    LPUDS        LL_PWR_SetPowerMode\n
+  * @rmtoll CR    FPDS         LL_PWR_SetPowerMode\n
+  * @rmtoll CR    MRLVDS       LL_PWR_SetPowerMode\n
+  * @rmtoll CR    LPlVDS       LL_PWR_SetPowerMode\n
+  * @rmtoll CR    FPDS         LL_PWR_SetPowerMode\n
+  * @rmtoll CR    LPDS         LL_PWR_SetPowerMode
+  * @param  PDMode This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
+  *         @arg @ref LL_PWR_MODE_STOP_LPREGU
+  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
+  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
+  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
+  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
+  *
+  *         (*) not available on all devices
+  *         @arg @ref LL_PWR_MODE_STANDBY
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
+{
+#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
+  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode);
+#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
+  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode);
+#else
+  MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
+#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
+}
+
+/**
+  * @brief  Get Power Down mode when CPU enters deepsleep
+  * @rmtoll CR    PDDS         LL_PWR_GetPowerMode\n
+  * @rmtoll CR    MRUDS        LL_PWR_GetPowerMode\n
+  * @rmtoll CR    LPUDS        LL_PWR_GetPowerMode\n
+  * @rmtoll CR    FPDS         LL_PWR_GetPowerMode\n
+  * @rmtoll CR    MRLVDS       LL_PWR_GetPowerMode\n
+  * @rmtoll CR    LPLVDS       LL_PWR_GetPowerMode\n
+  * @rmtoll CR    FPDS         LL_PWR_GetPowerMode\n
+  * @rmtoll CR    LPDS         LL_PWR_GetPowerMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
+  *         @arg @ref LL_PWR_MODE_STOP_LPREGU
+  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (*)
+  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (*)
+  *         @arg @ref LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (*)
+  *         @arg @ref LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (*)
+  *
+  *         (*) not available on all devices
+  *         @arg @ref LL_PWR_MODE_STANDBY
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
+{
+#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
+  return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS)));
+#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
+  return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS)));
+#else
+  return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
+#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
+}
+
+/**
+  * @brief  Configure the voltage threshold detected by the Power Voltage Detector
+  * @rmtoll CR    PLS       LL_PWR_SetPVDLevel
+  * @param  PVDLevel This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
+{
+  MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
+}
+
+/**
+  * @brief  Get the voltage threshold detection
+  * @rmtoll CR    PLS       LL_PWR_GetPVDLevel
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_PWR_PVDLEVEL_0
+  *         @arg @ref LL_PWR_PVDLEVEL_1
+  *         @arg @ref LL_PWR_PVDLEVEL_2
+  *         @arg @ref LL_PWR_PVDLEVEL_3
+  *         @arg @ref LL_PWR_PVDLEVEL_4
+  *         @arg @ref LL_PWR_PVDLEVEL_5
+  *         @arg @ref LL_PWR_PVDLEVEL_6
+  *         @arg @ref LL_PWR_PVDLEVEL_7
+  */
+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
+{
+  return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
+}
+
+/**
+  * @brief  Enable Power Voltage Detector
+  * @rmtoll CR    PVDE       LL_PWR_EnablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnablePVD(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+  * @brief  Disable Power Voltage Detector
+  * @rmtoll CR    PVDE       LL_PWR_DisablePVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisablePVD(void)
+{
+  CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
+}
+
+/**
+  * @brief  Check if Power Voltage Detector is enabled
+  * @rmtoll CR    PVDE       LL_PWR_IsEnabledPVD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
+{
+  return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
+}
+
+/**
+  * @brief  Enable the WakeUp PINx functionality
+  * @rmtoll CSR   EWUP        LL_PWR_EnableWakeUpPin\n
+  * @rmtoll CSR   EWUP1       LL_PWR_EnableWakeUpPin\n
+  * @rmtoll CSR   EWUP2       LL_PWR_EnableWakeUpPin\n
+  * @rmtoll CSR   EWUP3       LL_PWR_EnableWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *
+  *         (*) not available on all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
+{
+  SET_BIT(PWR->CSR, WakeUpPin);
+}
+
+/**
+  * @brief  Disable the WakeUp PINx functionality
+  * @rmtoll CSR   EWUP        LL_PWR_DisableWakeUpPin\n
+  * @rmtoll CSR   EWUP1       LL_PWR_DisableWakeUpPin\n
+  * @rmtoll CSR   EWUP2       LL_PWR_DisableWakeUpPin\n
+  * @rmtoll CSR   EWUP3       LL_PWR_DisableWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *
+  *         (*) not available on all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
+{
+  CLEAR_BIT(PWR->CSR, WakeUpPin);
+}
+
+/**
+  * @brief  Check if the WakeUp PINx functionality is enabled
+  * @rmtoll CSR   EWUP        LL_PWR_IsEnabledWakeUpPin\n
+  * @rmtoll CSR   EWUP1       LL_PWR_IsEnabledWakeUpPin\n
+  * @rmtoll CSR   EWUP2       LL_PWR_IsEnabledWakeUpPin\n
+  * @rmtoll CSR   EWUP3       LL_PWR_IsEnabledWakeUpPin
+  * @param  WakeUpPin This parameter can be one of the following values:
+  *         @arg @ref LL_PWR_WAKEUP_PIN1
+  *         @arg @ref LL_PWR_WAKEUP_PIN2 (*)
+  *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
+  *
+  *         (*) not available on all devices
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
+{
+  return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Get Wake-up Flag
+  * @rmtoll CSR   WUF       LL_PWR_IsActiveFlag_WU
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
+}
+
+/**
+  * @brief  Get Standby Flag
+  * @rmtoll CSR   SBF       LL_PWR_IsActiveFlag_SB
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
+}
+
+/**
+  * @brief  Get Backup Regulator ready Flag
+  * @rmtoll CSR   BRR       LL_PWR_IsActiveFlag_BRR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));
+}
+/**
+  * @brief  Indicate whether VDD voltage is below the selected PVD threshold
+  * @rmtoll CSR   PVDO       LL_PWR_IsActiveFlag_PVDO
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
+}
+
+/**
+  * @brief  Indicate whether the Regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
+  * @rmtoll CSR   VOS       LL_PWR_IsActiveFlag_VOS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
+{
+  return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
+}
+#if defined(PWR_CR_ODEN)
+/**
+  * @brief  Indicate whether the Over-Drive mode is ready or not
+  * @rmtoll CSR   ODRDY       LL_PWR_IsActiveFlag_OD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY));
+}
+#endif /* PWR_CR_ODEN */
+
+#if defined(PWR_CR_ODSWEN)
+/**
+  * @brief  Indicate whether the Over-Drive mode switching is ready or not
+  * @rmtoll CSR   ODSWRDY       LL_PWR_IsActiveFlag_ODSW
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY));
+}
+#endif /* PWR_CR_ODSWEN */
+
+#if defined(PWR_CR_UDEN)
+/**
+  * @brief  Indicate whether the Under-Drive mode is ready or not
+  * @rmtoll CSR   UDRDY       LL_PWR_IsActiveFlag_UD
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
+{
+  return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY));
+}
+#endif /* PWR_CR_UDEN */
+/**
+  * @brief  Clear Standby Flag
+  * @rmtoll CR   CSBF       LL_PWR_ClearFlag_SB
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_CSBF);
+}
+
+/**
+  * @brief  Clear Wake-up Flags
+  * @rmtoll CR   CWUF       LL_PWR_ClearFlag_WU
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
+{
+  SET_BIT(PWR->CR, PWR_CR_CWUF);
+}
+#if defined(PWR_CSR_UDRDY)
+/**
+  * @brief  Clear Under-Drive ready Flag
+  * @rmtoll CSR          UDRDY         LL_PWR_ClearFlag_UD
+  * @retval None
+  */
+__STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
+{
+  WRITE_REG(PWR->CSR, PWR_CSR_UDRDY);
+}
+#endif /* PWR_CSR_UDRDY */
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup PWR_LL_EF_Init De-initialization function
+  * @{
+  */
+ErrorStatus LL_PWR_DeInit(void);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(PWR) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_PWR_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h
index 1df1b58..1f2a91d 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_rcc.h
@@ -1,7096 +1,7096 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_ll_rcc.h
-  * @author  MCD Application Team
-  * @brief   Header file of RCC LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_RCC_H
-#define __STM32F4xx_LL_RCC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_LL_Driver
-  * @{
-  */
-
-#if defined(RCC)
-
-/** @defgroup RCC_LL RCC
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_LL_Private_Variables RCC Private Variables
-  * @{
-  */
-
-#if defined(RCC_DCKCFGR_PLLSAIDIVR)
-static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
-#endif /* RCC_DCKCFGR_PLLSAIDIVR */
-
-/**
-  * @}
-  */
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Private_Macros RCC Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_Exported_Types RCC Exported Types
-  * @{
-  */
-
-/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
-  * @{
-  */
-
-/**
-  * @brief  RCC Clocks Frequency Structure
-  */
-typedef struct
-{
-  uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
-  uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
-  uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
-  uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
-} LL_RCC_ClocksTypeDef;
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
-  * @{
-  */
-
-/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
-  * @brief    Defines used to adapt values of different oscillators
-  * @note     These values could be modified in the user environment according to 
-  *           HW set-up.
-  * @{
-  */
-#if !defined  (HSE_VALUE)
-#define HSE_VALUE    25000000U  /*!< Value of the HSE oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-#define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */
-#endif /* HSI_VALUE */
-
-#if !defined  (LSE_VALUE)
-#define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
-#endif /* LSE_VALUE */
-
-#if !defined  (LSI_VALUE)
-#define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
-#endif /* LSI_VALUE */
-
-#if !defined  (EXTERNAL_CLOCK_VALUE)
-#define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
-#endif /* EXTERNAL_CLOCK_VALUE */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
-  * @brief    Flags defines which can be used with LL_RCC_WriteReg function
-  * @{
-  */
-#define LL_RCC_CIR_LSIRDYC                RCC_CIR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
-#define LL_RCC_CIR_LSERDYC                RCC_CIR_LSERDYC     /*!< LSE Ready Interrupt Clear */
-#define LL_RCC_CIR_HSIRDYC                RCC_CIR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
-#define LL_RCC_CIR_HSERDYC                RCC_CIR_HSERDYC     /*!< HSE Ready Interrupt Clear */
-#define LL_RCC_CIR_PLLRDYC                RCC_CIR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
-#if defined(RCC_PLLI2S_SUPPORT)
-#define LL_RCC_CIR_PLLI2SRDYC             RCC_CIR_PLLI2SRDYC  /*!< PLLI2S Ready Interrupt Clear */
-#endif /* RCC_PLLI2S_SUPPORT */
-#if defined(RCC_PLLSAI_SUPPORT)
-#define LL_RCC_CIR_PLLSAIRDYC             RCC_CIR_PLLSAIRDYC  /*!< PLLSAI Ready Interrupt Clear */
-#endif /* RCC_PLLSAI_SUPPORT */
-#define LL_RCC_CIR_CSSC                   RCC_CIR_CSSC        /*!< Clock Security System Interrupt Clear */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_RCC_ReadReg function
-  * @{
-  */
-#define LL_RCC_CIR_LSIRDYF                RCC_CIR_LSIRDYF     /*!< LSI Ready Interrupt flag */
-#define LL_RCC_CIR_LSERDYF                RCC_CIR_LSERDYF     /*!< LSE Ready Interrupt flag */
-#define LL_RCC_CIR_HSIRDYF                RCC_CIR_HSIRDYF     /*!< HSI Ready Interrupt flag */
-#define LL_RCC_CIR_HSERDYF                RCC_CIR_HSERDYF     /*!< HSE Ready Interrupt flag */
-#define LL_RCC_CIR_PLLRDYF                RCC_CIR_PLLRDYF     /*!< PLL Ready Interrupt flag */
-#if defined(RCC_PLLI2S_SUPPORT)
-#define LL_RCC_CIR_PLLI2SRDYF             RCC_CIR_PLLI2SRDYF  /*!< PLLI2S Ready Interrupt flag */
-#endif /* RCC_PLLI2S_SUPPORT */
-#if defined(RCC_PLLSAI_SUPPORT)
-#define LL_RCC_CIR_PLLSAIRDYF             RCC_CIR_PLLSAIRDYF  /*!< PLLSAI Ready Interrupt flag */
-#endif /* RCC_PLLSAI_SUPPORT */
-#define LL_RCC_CIR_CSSF                   RCC_CIR_CSSF        /*!< Clock Security System Interrupt flag */
-#define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF   /*!< Low-Power reset flag */
-#define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF    /*!< PIN reset flag */
-#define LL_RCC_CSR_PORRSTF                 RCC_CSR_PORRSTF    /*!< POR/PDR reset flag */
-#define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF    /*!< Software Reset flag */
-#define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag */
-#define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */
-#if defined(RCC_CSR_BORRSTF)
-#define LL_RCC_CSR_BORRSTF                 RCC_CSR_BORRSTF    /*!< BOR reset flag */
-#endif /* RCC_CSR_BORRSTF */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
-  * @{
-  */
-#define LL_RCC_CIR_LSIRDYIE               RCC_CIR_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
-#define LL_RCC_CIR_LSERDYIE               RCC_CIR_LSERDYIE      /*!< LSE Ready Interrupt Enable */
-#define LL_RCC_CIR_HSIRDYIE               RCC_CIR_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
-#define LL_RCC_CIR_HSERDYIE               RCC_CIR_HSERDYIE      /*!< HSE Ready Interrupt Enable */
-#define LL_RCC_CIR_PLLRDYIE               RCC_CIR_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
-#if defined(RCC_PLLI2S_SUPPORT)
-#define LL_RCC_CIR_PLLI2SRDYIE            RCC_CIR_PLLI2SRDYIE   /*!< PLLI2S Ready Interrupt Enable */
-#endif /* RCC_PLLI2S_SUPPORT */
-#if defined(RCC_PLLSAI_SUPPORT)
-#define LL_RCC_CIR_PLLSAIRDYIE            RCC_CIR_PLLSAIRDYIE   /*!< PLLSAI Ready Interrupt Enable */
-#endif /* RCC_PLLSAI_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
-  * @{
-  */
-#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
-#define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
-#if defined(RCC_CFGR_SW_PLLR)
-#define LL_RCC_SYS_CLKSOURCE_PLLR          RCC_CFGR_SW_PLLR   /*!< PLLR selection as system clock */
-#endif /* RCC_CFGR_SW_PLLR */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
-  * @{
-  */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
-#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
-#if defined(RCC_PLLR_SYSCLK_SUPPORT)
-#define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR   RCC_CFGR_SWS_PLLR  /*!< PLLR used as system clock */
-#endif /* RCC_PLLR_SYSCLK_SUPPORT */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
-  * @{
-  */
-#define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
-#define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
-#define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
-#define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
-#define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
-#define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
-#define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
-#define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
-#define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
-  * @{
-  */
-#define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
-#define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
-#define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
-#define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
-#define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
-  * @{
-  */
-#define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
-#define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
-#define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
-#define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
-#define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_MCOxSOURCE  MCO source selection
-  * @{
-  */
-#define LL_RCC_MCO1SOURCE_HSI              (uint32_t)(RCC_CFGR_MCO1|0x00000000U)                    /*!< HSI selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_LSE              (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U))       /*!< LSE selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_HSE              (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U))       /*!< HSE selection as MCO1 source */
-#define LL_RCC_MCO1SOURCE_PLLCLK           (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U))       /*!< PLLCLK selection as MCO1 source */
-#if defined(RCC_CFGR_MCO2)
-#define LL_RCC_MCO2SOURCE_SYSCLK           (uint32_t)(RCC_CFGR_MCO2|0x00000000U)                    /*!< SYSCLK selection as MCO2 source */
-#define LL_RCC_MCO2SOURCE_PLLI2S           (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U))       /*!< PLLI2S selection as MCO2 source */
-#define LL_RCC_MCO2SOURCE_HSE              (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U))       /*!< HSE selection as MCO2 source */
-#define LL_RCC_MCO2SOURCE_PLLCLK           (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U))       /*!< PLLCLK selection as MCO2 source */
-#endif /* RCC_CFGR_MCO2 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_MCOx_DIV  MCO prescaler
-  * @{
-  */
-#define LL_RCC_MCO1_DIV_1                  (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U)                       /*!< MCO1 not divided */
-#define LL_RCC_MCO1_DIV_2                  (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U))       /*!< MCO1 divided by 2 */
-#define LL_RCC_MCO1_DIV_3                  (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U))       /*!< MCO1 divided by 3 */
-#define LL_RCC_MCO1_DIV_4                  (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U))       /*!< MCO1 divided by 4 */
-#define LL_RCC_MCO1_DIV_5                  (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U))         /*!< MCO1 divided by 5 */
-#if defined(RCC_CFGR_MCO2PRE)
-#define LL_RCC_MCO2_DIV_1                  (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U)                       /*!< MCO2 not divided */
-#define LL_RCC_MCO2_DIV_2                  (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U))       /*!< MCO2 divided by 2 */
-#define LL_RCC_MCO2_DIV_3                  (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U))       /*!< MCO2 divided by 3 */
-#define LL_RCC_MCO2_DIV_4                  (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U))       /*!< MCO2 divided by 4 */
-#define LL_RCC_MCO2_DIV_5                  (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U))         /*!< MCO2 divided by 5 */
-#endif /* RCC_CFGR_MCO2PRE */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_RTC_HSEDIV  HSE prescaler for RTC clock
-  * @{
-  */
-#define LL_RCC_RTC_NOCLOCK                  0x00000000U             /*!< HSE not divided */
-#define LL_RCC_RTC_HSE_DIV_2                RCC_CFGR_RTCPRE_1       /*!< HSE clock divided by 2 */
-#define LL_RCC_RTC_HSE_DIV_3                (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 3 */
-#define LL_RCC_RTC_HSE_DIV_4                RCC_CFGR_RTCPRE_2       /*!< HSE clock divided by 4 */
-#define LL_RCC_RTC_HSE_DIV_5                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 5 */
-#define LL_RCC_RTC_HSE_DIV_6                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 6 */
-#define LL_RCC_RTC_HSE_DIV_7                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 7 */
-#define LL_RCC_RTC_HSE_DIV_8                RCC_CFGR_RTCPRE_3       /*!< HSE clock divided by 8 */
-#define LL_RCC_RTC_HSE_DIV_9                (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 9 */
-#define LL_RCC_RTC_HSE_DIV_10               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 10 */
-#define LL_RCC_RTC_HSE_DIV_11               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 11 */
-#define LL_RCC_RTC_HSE_DIV_12               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 12 */
-#define LL_RCC_RTC_HSE_DIV_13               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 13 */
-#define LL_RCC_RTC_HSE_DIV_14               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 14 */
-#define LL_RCC_RTC_HSE_DIV_15               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 15 */
-#define LL_RCC_RTC_HSE_DIV_16               RCC_CFGR_RTCPRE_4       /*!< HSE clock divided by 16 */
-#define LL_RCC_RTC_HSE_DIV_17               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 17 */
-#define LL_RCC_RTC_HSE_DIV_18               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 18 */
-#define LL_RCC_RTC_HSE_DIV_19               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 19 */
-#define LL_RCC_RTC_HSE_DIV_20               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 20 */
-#define LL_RCC_RTC_HSE_DIV_21               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 21 */
-#define LL_RCC_RTC_HSE_DIV_22               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 22 */
-#define LL_RCC_RTC_HSE_DIV_23               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 23 */
-#define LL_RCC_RTC_HSE_DIV_24               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)       /*!< HSE clock divided by 24 */
-#define LL_RCC_RTC_HSE_DIV_25               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 25 */
-#define LL_RCC_RTC_HSE_DIV_26               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 26 */
-#define LL_RCC_RTC_HSE_DIV_27               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 27 */
-#define LL_RCC_RTC_HSE_DIV_28               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 28 */
-#define LL_RCC_RTC_HSE_DIV_29               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 29 */
-#define LL_RCC_RTC_HSE_DIV_30               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 30 */
-#define LL_RCC_RTC_HSE_DIV_31               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 31 */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
-  * @{
-  */
-#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */
-#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-#if defined(FMPI2C1)
-/** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE  Peripheral FMPI2C clock source selection
-  * @{
-  */
-#define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1        0x00000000U               /*!< PCLK1 clock used as FMPI2C1 clock source */
-#define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK       RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */
-#define LL_RCC_FMPI2C1_CLKSOURCE_HSI          RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */
-/**
-  * @}
-  */
-#endif /* FMPI2C1 */
-
-#if defined(LPTIM1)
-/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE  Peripheral LPTIM clock source selection
-  * @{
-  */
-#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1       0x00000000U                 /*!< PCLK1 clock used as LPTIM1 clock */
-#define LL_RCC_LPTIM1_CLKSOURCE_HSI         RCC_DCKCFGR2_LPTIM1SEL_0    /*!< LSI oscillator clock used as LPTIM1 clock */
-#define LL_RCC_LPTIM1_CLKSOURCE_LSI         RCC_DCKCFGR2_LPTIM1SEL_1    /*!< HSI oscillator clock used as LPTIM1 clock */
-#define LL_RCC_LPTIM1_CLKSOURCE_LSE         (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0)      /*!< LSE oscillator clock used as LPTIM1 clock */
-/**
-  * @}
-  */
-#endif /* LPTIM1 */
-
-#if defined(SAI1)
-/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection
-  * @{
-  */
-#if defined(RCC_DCKCFGR_SAI1SRC)
-#define LL_RCC_SAI1_CLKSOURCE_PLLSAI       (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U)                     /*!< PLLSAI clock used as SAI1 clock source */
-#define LL_RCC_SAI1_CLKSOURCE_PLLI2S       (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16))   /*!< PLLI2S clock used as SAI1 clock source */
-#define LL_RCC_SAI1_CLKSOURCE_PLL          (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16))   /*!< PLL clock used as SAI1 clock source */
-#define LL_RCC_SAI1_CLKSOURCE_PIN          (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16))     /*!< External pin clock used as SAI1 clock source */
-#endif /* RCC_DCKCFGR_SAI1SRC */
-#if defined(RCC_DCKCFGR_SAI2SRC)
-#define LL_RCC_SAI2_CLKSOURCE_PLLSAI       (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U)                     /*!< PLLSAI clock used as SAI2 clock source */
-#define LL_RCC_SAI2_CLKSOURCE_PLLI2S       (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16))   /*!< PLLI2S clock used as SAI2 clock source */
-#define LL_RCC_SAI2_CLKSOURCE_PLL          (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16))   /*!< PLL clock used as SAI2 clock source */
-#define LL_RCC_SAI2_CLKSOURCE_PLLSRC       (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16))     /*!< PLL Main clock used as SAI2 clock source */
-#endif /* RCC_DCKCFGR_SAI2SRC */
-#if defined(RCC_DCKCFGR_SAI1ASRC)
-#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
-#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U)                    /*!< PLLI2S clock used as SAI1 block A clock source */
-#define LL_RCC_SAI1_A_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */
-#define LL_RCC_SAI1_A_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */
-#define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16))   /*!< PLL Main clock used as SAI1 block A clock source */
-#else
-#define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U)                    /*!< PLLSAI clock used as SAI1 block A clock source */
-#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */
-#define LL_RCC_SAI1_A_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */
-#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
-#endif /* RCC_DCKCFGR_SAI1ASRC */
-#if defined(RCC_DCKCFGR_SAI1BSRC)
-#if defined(RCC_SAI1B_PLLSOURCE_SUPPORT)
-#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U)                    /*!< PLLI2S clock used as SAI1 block B clock source */
-#define LL_RCC_SAI1_B_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */
-#define LL_RCC_SAI1_B_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */
-#define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16))   /*!< PLL Main clock used as SAI1 block B clock source */
-#else
-#define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U)                    /*!< PLLSAI clock used as SAI1 block B clock source */
-#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */
-#define LL_RCC_SAI1_B_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */
-#endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */
-#endif /* RCC_DCKCFGR_SAI1BSRC */
-/**
-  * @}
-  */
-#endif /* SAI1 */
-
-#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
-/** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE  Peripheral SDIO clock source selection
-  * @{
-  */
-#define LL_RCC_SDIO_CLKSOURCE_PLL48CLK       0x00000000U                 /*!< PLL 48M domain clock used as SDIO clock */
-#if defined(RCC_DCKCFGR_SDIOSEL)
-#define LL_RCC_SDIO_CLKSOURCE_SYSCLK         RCC_DCKCFGR_SDIOSEL         /*!< System clock clock used as SDIO clock */
-#else
-#define LL_RCC_SDIO_CLKSOURCE_SYSCLK         RCC_DCKCFGR2_SDIOSEL        /*!< System clock clock used as SDIO clock */
-#endif /* RCC_DCKCFGR_SDIOSEL */
-/**
-  * @}
-  */
-#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
-
-#if defined(DSI)
-/** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI clock source selection
-  * @{
-  */
-#define LL_RCC_DSI_CLKSOURCE_PHY          0x00000000U                       /*!< DSI-PHY clock used as DSI byte lane clock source */
-#define LL_RCC_DSI_CLKSOURCE_PLL          RCC_DCKCFGR_DSISEL                /*!< PLL clock used as DSI byte lane clock source */
-/**
-  * @}
-  */
-#endif /* DSI */
-
-#if defined(CEC)
-/** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection
-  * @{
-  */
-#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488    0x00000000U                /*!< HSI oscillator clock divided by 488 used as CEC clock */
-#define LL_RCC_CEC_CLKSOURCE_LSE           RCC_DCKCFGR2_CECSEL        /*!< LSE oscillator clock used as CEC clock */
-/**
-  * @}
-  */
-#endif /* CEC */
-
-/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE  Peripheral I2S clock source selection
-  * @{
-  */
-#if defined(RCC_CFGR_I2SSRC)
-#define LL_RCC_I2S1_CLKSOURCE_PLLI2S     0x00000000U                /*!< I2S oscillator clock used as I2S1 clock */
-#define LL_RCC_I2S1_CLKSOURCE_PIN        RCC_CFGR_I2SSRC            /*!< External pin clock used as I2S1 clock */
-#endif /* RCC_CFGR_I2SSRC */
-#if defined(RCC_DCKCFGR_I2SSRC)
-#define LL_RCC_I2S1_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U)                    /*!< PLL clock used as I2S1 clock source */
-#define LL_RCC_I2S1_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16))   /*!< External pin used as I2S1 clock source */
-#define LL_RCC_I2S1_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16))   /*!< PLL Main clock used as I2S1 clock source */
-#endif /* RCC_DCKCFGR_I2SSRC */
-#if defined(RCC_DCKCFGR_I2S1SRC)
-#define LL_RCC_I2S1_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U)                   /*!< PLLI2S clock used as I2S1 clock source */
-#define LL_RCC_I2S1_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */
-#define LL_RCC_I2S1_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */
-#define LL_RCC_I2S1_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16))   /*!< PLL Main clock used as I2S1 clock source */
-#endif /* RCC_DCKCFGR_I2S1SRC */
-#if defined(RCC_DCKCFGR_I2S2SRC)
-#define LL_RCC_I2S2_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U)                   /*!< PLLI2S clock used as I2S2 clock source */
-#define LL_RCC_I2S2_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */
-#define LL_RCC_I2S2_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */
-#define LL_RCC_I2S2_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16))   /*!< PLL Main clock used as I2S2 clock source */
-#endif /* RCC_DCKCFGR_I2S2SRC */
-/**
-  * @}
-  */
-
-#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
-/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE  Peripheral 48Mhz domain clock source selection
-  * @{
-  */
-#if defined(RCC_DCKCFGR_CK48MSEL)
-#define LL_RCC_CK48M_CLKSOURCE_PLL         0x00000000U                /*!< PLL oscillator clock used as 48Mhz domain clock */
-#define LL_RCC_CK48M_CLKSOURCE_PLLSAI      RCC_DCKCFGR_CK48MSEL       /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
-#endif /* RCC_DCKCFGR_CK48MSEL */
-#if defined(RCC_DCKCFGR2_CK48MSEL)
-#define LL_RCC_CK48M_CLKSOURCE_PLL         0x00000000U                /*!< PLL oscillator clock used as 48Mhz domain clock */
-#if defined(RCC_PLLSAI_SUPPORT)
-#define LL_RCC_CK48M_CLKSOURCE_PLLSAI      RCC_DCKCFGR2_CK48MSEL      /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
-#endif /* RCC_PLLSAI_SUPPORT */
-#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
-#define LL_RCC_CK48M_CLKSOURCE_PLLI2S      RCC_DCKCFGR2_CK48MSEL      /*!< PLLI2S oscillator clock used as 48Mhz domain clock */
-#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
-#endif /* RCC_DCKCFGR2_CK48MSEL */
-/**
-  * @}
-  */
-
-#if defined(RNG)
-/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
-  * @{
-  */
-#define LL_RCC_RNG_CLKSOURCE_PLL          LL_RCC_CK48M_CLKSOURCE_PLL        /*!< PLL clock used as RNG clock source */
-#if defined(RCC_PLLSAI_SUPPORT)
-#define LL_RCC_RNG_CLKSOURCE_PLLSAI       LL_RCC_CK48M_CLKSOURCE_PLLSAI     /*!< PLLSAI clock used as RNG clock source */
-#endif /* RCC_PLLSAI_SUPPORT */
-#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
-#define LL_RCC_RNG_CLKSOURCE_PLLI2S       LL_RCC_CK48M_CLKSOURCE_PLLI2S     /*!< PLLI2S clock used as RNG clock source */
-#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
-/**
-  * @}
-  */
-#endif /* RNG */
-
-#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
-/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
-  * @{
-  */
-#define LL_RCC_USB_CLKSOURCE_PLL          LL_RCC_CK48M_CLKSOURCE_PLL        /*!< PLL clock used as USB clock source */
-#if defined(RCC_PLLSAI_SUPPORT)
-#define LL_RCC_USB_CLKSOURCE_PLLSAI       LL_RCC_CK48M_CLKSOURCE_PLLSAI     /*!< PLLSAI clock used as USB clock source */
-#endif /* RCC_PLLSAI_SUPPORT */
-#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
-#define LL_RCC_USB_CLKSOURCE_PLLI2S       LL_RCC_CK48M_CLKSOURCE_PLLI2S     /*!< PLLI2S clock used as USB clock source */
-#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
-/**
-  * @}
-  */
-#endif /* USB_OTG_FS || USB_OTG_HS */
-
-#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
-
-#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
-/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE  Peripheral DFSDM Audio clock source selection
-  * @{
-  */
-#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1     (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U)                      /*!< I2S1 clock used as DFSDM1 Audio clock source */
-#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2     (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */
-#if defined(DFSDM2_Channel0)
-#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1     (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U)                      /*!< I2S1 clock used as DFSDM2 Audio clock source */
-#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2     (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */
-#endif /* DFSDM2_Channel0 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE  Peripheral DFSDM clock source selection
-  * @{
-  */
-#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          0x00000000U                /*!< PCLK2 clock used as DFSDM1 clock */
-#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         RCC_DCKCFGR_CKDFSDM1SEL    /*!< System clock used as DFSDM1 clock */
-#if defined(DFSDM2_Channel0)
-#define LL_RCC_DFSDM2_CLKSOURCE_PCLK2          0x00000000U                /*!< PCLK2 clock used as DFSDM2 clock */
-#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK         RCC_DCKCFGR_CKDFSDM1SEL    /*!< System clock used as DFSDM2 clock */
-#endif /* DFSDM2_Channel0 */
-/**
-  * @}
-  */
-#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
-
-#if defined(FMPI2C1)
-/** @defgroup RCC_LL_EC_FMPI2C1  Peripheral FMPI2C get clock source
-  * @{
-  */
-#define LL_RCC_FMPI2C1_CLKSOURCE              RCC_DCKCFGR2_FMPI2C1SEL  /*!< FMPI2C1 Clock source selection */
-/**
-  * @}
-  */
-#endif /* FMPI2C1 */
-
-#if defined(SPDIFRX)
-/** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE  Peripheral SPDIFRX clock source selection
-  * @{
-  */
-#define LL_RCC_SPDIFRX1_CLKSOURCE_PLL          0x00000000U             /*!< PLL clock used as SPDIFRX clock source */
-#define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S       RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */
-/**
-  * @}
-  */
-#endif /* SPDIFRX */
-
-#if defined(LPTIM1)
-/** @defgroup RCC_LL_EC_LPTIM1  Peripheral LPTIM get clock source
-  * @{
-  */
-#define LL_RCC_LPTIM1_CLKSOURCE            RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */
-/**
-  * @}
-  */
-#endif /* LPTIM1 */
-
-#if defined(SAI1)
-/** @defgroup RCC_LL_EC_SAIx  Peripheral SAI get clock source
-  * @{
-  */
-#if defined(RCC_DCKCFGR_SAI1ASRC)
-#define LL_RCC_SAI1_A_CLKSOURCE            RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */
-#endif /* RCC_DCKCFGR_SAI1ASRC */
-#if defined(RCC_DCKCFGR_SAI1BSRC)
-#define LL_RCC_SAI1_B_CLKSOURCE            RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */
-#endif /* RCC_DCKCFGR_SAI1BSRC */
-#if defined(RCC_DCKCFGR_SAI1SRC)
-#define LL_RCC_SAI1_CLKSOURCE              RCC_DCKCFGR_SAI1SRC  /*!< SAI1 Clock source selection */
-#endif /* RCC_DCKCFGR_SAI1SRC */
-#if defined(RCC_DCKCFGR_SAI2SRC)
-#define LL_RCC_SAI2_CLKSOURCE              RCC_DCKCFGR_SAI2SRC  /*!< SAI2 Clock source selection */
-#endif /* RCC_DCKCFGR_SAI2SRC */
-/**
-  * @}
-  */
-#endif /* SAI1 */
-
-#if defined(SDIO)
-/** @defgroup RCC_LL_EC_SDIOx  Peripheral SDIO get clock source
-  * @{
-  */
-#if defined(RCC_DCKCFGR_SDIOSEL)
-#define LL_RCC_SDIO_CLKSOURCE            RCC_DCKCFGR_SDIOSEL   /*!< SDIO Clock source selection */
-#elif defined(RCC_DCKCFGR2_SDIOSEL)
-#define LL_RCC_SDIO_CLKSOURCE            RCC_DCKCFGR2_SDIOSEL  /*!< SDIO Clock source selection */
-#else
-#define LL_RCC_SDIO_CLKSOURCE            RCC_PLLCFGR_PLLQ      /*!< SDIO Clock source selection */
-#endif
-/**
-  * @}
-  */
-#endif /* SDIO */
-
-#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
-/** @defgroup RCC_LL_EC_CK48M  Peripheral CK48M get clock source
-  * @{
-  */
-#if defined(RCC_DCKCFGR_CK48MSEL)
-#define LL_RCC_CK48M_CLKSOURCE             RCC_DCKCFGR_CK48MSEL  /*!< CK48M Domain clock source selection */
-#endif /* RCC_DCKCFGR_CK48MSEL */
-#if defined(RCC_DCKCFGR2_CK48MSEL)
-#define LL_RCC_CK48M_CLKSOURCE             RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */
-#endif /* RCC_DCKCFGR_CK48MSEL */
-/**
-  * @}
-  */
-#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
-
-#if defined(RNG)
-/** @defgroup RCC_LL_EC_RNG  Peripheral RNG get clock source
-  * @{
-  */
-#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
-#define LL_RCC_RNG_CLKSOURCE               LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */
-#else
-#define LL_RCC_RNG_CLKSOURCE               RCC_PLLCFGR_PLLQ       /*!< RNG Clock source selection */
-#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
-/**
-  * @}
-  */
-#endif /* RNG */
-
-#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
-/** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
-  * @{
-  */
-#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
-#define LL_RCC_USB_CLKSOURCE               LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */
-#else
-#define LL_RCC_USB_CLKSOURCE               RCC_PLLCFGR_PLLQ       /*!< USB Clock source selection */
-#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
-/**
-  * @}
-  */
-#endif /* USB_OTG_FS || USB_OTG_HS */
-
-#if defined(CEC)
-/** @defgroup RCC_LL_EC_CEC  Peripheral CEC get clock source
-  * @{
-  */
-#define LL_RCC_CEC_CLKSOURCE               RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */
-/**
-  * @}
-  */
-#endif /* CEC */
-
-/** @defgroup RCC_LL_EC_I2S1  Peripheral I2S get clock source
-  * @{
-  */
-#if defined(RCC_CFGR_I2SSRC)
-#define LL_RCC_I2S1_CLKSOURCE              RCC_CFGR_I2SSRC     /*!< I2S1 Clock source selection */
-#endif /* RCC_CFGR_I2SSRC */
-#if defined(RCC_DCKCFGR_I2SSRC)
-#define LL_RCC_I2S1_CLKSOURCE              RCC_DCKCFGR_I2SSRC  /*!< I2S1 Clock source selection */
-#endif /* RCC_DCKCFGR_I2SSRC */
-#if defined(RCC_DCKCFGR_I2S1SRC)
-#define LL_RCC_I2S1_CLKSOURCE              RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */
-#endif /* RCC_DCKCFGR_I2S1SRC */
-#if defined(RCC_DCKCFGR_I2S2SRC)
-#define LL_RCC_I2S2_CLKSOURCE              RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */
-#endif /* RCC_DCKCFGR_I2S2SRC */
-/**
-  * @}
-  */
-
-#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
-/** @defgroup RCC_LL_EC_DFSDM_AUDIO  Peripheral DFSDM Audio get clock source
-  * @{
-  */
-#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE      RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */
-#if defined(DFSDM2_Channel0)
-#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE      RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */
-#endif /* DFSDM2_Channel0 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_DFSDM  Peripheral DFSDM get clock source
-  * @{
-  */
-#define LL_RCC_DFSDM1_CLKSOURCE            RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */
-#if defined(DFSDM2_Channel0)
-#define LL_RCC_DFSDM2_CLKSOURCE            RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */
-#endif /* DFSDM2_Channel0 */
-/**
-  * @}
-  */
-#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
-
-#if defined(SPDIFRX)
-/** @defgroup RCC_LL_EC_SPDIFRX  Peripheral SPDIFRX get clock source
-  * @{
-  */
-#define LL_RCC_SPDIFRX1_CLKSOURCE          RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */
-/**
-  * @}
-  */
-#endif /* SPDIFRX */
-
-#if defined(DSI)
-/** @defgroup RCC_LL_EC_DSI  Peripheral DSI get clock source
-  * @{
-  */
-#define LL_RCC_DSI_CLKSOURCE               RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */
-/**
-  * @}
-  */
-#endif /* DSI */
-
-#if defined(LTDC)
-/** @defgroup RCC_LL_EC_LTDC  Peripheral LTDC get clock source
-  * @{
-  */
-#define LL_RCC_LTDC_CLKSOURCE              RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */
-/**
-  * @}
-  */
-#endif /* LTDC */
-
-
-/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
-  * @{
-  */
-#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
-#define LL_RCC_RTC_CLKSOURCE_HSE           RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */
-/**
-  * @}
-  */
-
-#if defined(RCC_DCKCFGR_TIMPRE)
-/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER  Timers clocks prescalers selection
-  * @{
-  */
-#define LL_RCC_TIM_PRESCALER_TWICE          0x00000000U                  /*!< Timers clock to twice PCLK */
-#define LL_RCC_TIM_PRESCALER_FOUR_TIMES     RCC_DCKCFGR_TIMPRE          /*!< Timers clock to four time PCLK */
-/**
-  * @}
-  */
-#endif /* RCC_DCKCFGR_TIMPRE */
-
-/** @defgroup RCC_LL_EC_PLLSOURCE  PLL, PLLI2S and PLLSAI entry clock source
-  * @{
-  */
-#define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI16 clock selected as PLL entry clock source */
-#define LL_RCC_PLLSOURCE_HSE               RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
-#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
-#define LL_RCC_PLLI2SSOURCE_PIN            (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U)  /*!< I2S External pin input clock selected as PLLI2S entry clock source */
-#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_PLLM_DIV  PLL, PLLI2S and PLLSAI division factor
-  * @{
-  */
-#define LL_RCC_PLLM_DIV_2                  (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */
-#define LL_RCC_PLLM_DIV_3                  (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */
-#define LL_RCC_PLLM_DIV_4                  (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */
-#define LL_RCC_PLLM_DIV_5                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */
-#define LL_RCC_PLLM_DIV_6                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */
-#define LL_RCC_PLLM_DIV_7                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */
-#define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */
-#define LL_RCC_PLLM_DIV_9                  (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */
-#define LL_RCC_PLLM_DIV_10                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */
-#define LL_RCC_PLLM_DIV_11                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */
-#define LL_RCC_PLLM_DIV_12                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */
-#define LL_RCC_PLLM_DIV_13                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */
-#define LL_RCC_PLLM_DIV_14                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */
-#define LL_RCC_PLLM_DIV_15                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */
-#define LL_RCC_PLLM_DIV_16                 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */
-#define LL_RCC_PLLM_DIV_17                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */
-#define LL_RCC_PLLM_DIV_18                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */
-#define LL_RCC_PLLM_DIV_19                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */
-#define LL_RCC_PLLM_DIV_20                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */
-#define LL_RCC_PLLM_DIV_21                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */
-#define LL_RCC_PLLM_DIV_22                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */
-#define LL_RCC_PLLM_DIV_23                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */
-#define LL_RCC_PLLM_DIV_24                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */
-#define LL_RCC_PLLM_DIV_25                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */
-#define LL_RCC_PLLM_DIV_26                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */
-#define LL_RCC_PLLM_DIV_27                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */
-#define LL_RCC_PLLM_DIV_28                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */
-#define LL_RCC_PLLM_DIV_29                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */
-#define LL_RCC_PLLM_DIV_30                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */
-#define LL_RCC_PLLM_DIV_31                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */
-#define LL_RCC_PLLM_DIV_32                 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */
-#define LL_RCC_PLLM_DIV_33                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */
-#define LL_RCC_PLLM_DIV_34                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */
-#define LL_RCC_PLLM_DIV_35                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */
-#define LL_RCC_PLLM_DIV_36                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */
-#define LL_RCC_PLLM_DIV_37                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */
-#define LL_RCC_PLLM_DIV_38                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */
-#define LL_RCC_PLLM_DIV_39                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */
-#define LL_RCC_PLLM_DIV_40                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */
-#define LL_RCC_PLLM_DIV_41                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */
-#define LL_RCC_PLLM_DIV_42                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */
-#define LL_RCC_PLLM_DIV_43                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */
-#define LL_RCC_PLLM_DIV_44                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */
-#define LL_RCC_PLLM_DIV_45                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */
-#define LL_RCC_PLLM_DIV_46                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */
-#define LL_RCC_PLLM_DIV_47                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */
-#define LL_RCC_PLLM_DIV_48                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */
-#define LL_RCC_PLLM_DIV_49                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */
-#define LL_RCC_PLLM_DIV_50                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */
-#define LL_RCC_PLLM_DIV_51                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */
-#define LL_RCC_PLLM_DIV_52                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */
-#define LL_RCC_PLLM_DIV_53                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */
-#define LL_RCC_PLLM_DIV_54                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */
-#define LL_RCC_PLLM_DIV_55                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */
-#define LL_RCC_PLLM_DIV_56                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */
-#define LL_RCC_PLLM_DIV_57                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */
-#define LL_RCC_PLLM_DIV_58                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */
-#define LL_RCC_PLLM_DIV_59                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */
-#define LL_RCC_PLLM_DIV_60                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */
-#define LL_RCC_PLLM_DIV_61                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */
-#define LL_RCC_PLLM_DIV_62                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */
-#define LL_RCC_PLLM_DIV_63                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */
-/**
-  * @}
-  */
-
-#if defined(RCC_PLLCFGR_PLLR)
-/** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)
-  * @{
-  */
-#define LL_RCC_PLLR_DIV_2                  (RCC_PLLCFGR_PLLR_1)                     /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
-#define LL_RCC_PLLR_DIV_3                  (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
-#define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_2)                     /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
-#define LL_RCC_PLLR_DIV_5                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
-#define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)  /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
-#define LL_RCC_PLLR_DIV_7                  (RCC_PLLCFGR_PLLR)                       /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
-/**
-  * @}
-  */
-#endif /* RCC_PLLCFGR_PLLR */
-
-#if defined(RCC_DCKCFGR_PLLDIVR)
-/** @defgroup RCC_LL_EC_PLLDIVR  PLLDIVR division factor (PLLDIVR)
-  * @{
-  */
-#define LL_RCC_PLLDIVR_DIV_1           (RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 1 */
-#define LL_RCC_PLLDIVR_DIV_2           (RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 2 */
-#define LL_RCC_PLLDIVR_DIV_3           (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 3 */
-#define LL_RCC_PLLDIVR_DIV_4           (RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 4 */
-#define LL_RCC_PLLDIVR_DIV_5           (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 5 */
-#define LL_RCC_PLLDIVR_DIV_6           (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 6 */
-#define LL_RCC_PLLDIVR_DIV_7           (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 7 */
-#define LL_RCC_PLLDIVR_DIV_8           (RCC_DCKCFGR_PLLDIVR_3)        /*!< PLL division factor for PLLDIVR output by 8 */
-#define LL_RCC_PLLDIVR_DIV_9           (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 9 */
-#define LL_RCC_PLLDIVR_DIV_10          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 10 */
-#define LL_RCC_PLLDIVR_DIV_11          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 11 */
-#define LL_RCC_PLLDIVR_DIV_12          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 12 */
-#define LL_RCC_PLLDIVR_DIV_13          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 13 */
-#define LL_RCC_PLLDIVR_DIV_14          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 14 */
-#define LL_RCC_PLLDIVR_DIV_15          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 15 */
-#define LL_RCC_PLLDIVR_DIV_16          (RCC_DCKCFGR_PLLDIVR_4)             /*!< PLL division factor for PLLDIVR output by 16 */
-#define LL_RCC_PLLDIVR_DIV_17          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 17 */
-#define LL_RCC_PLLDIVR_DIV_18          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 18 */
-#define LL_RCC_PLLDIVR_DIV_19          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 19 */
-#define LL_RCC_PLLDIVR_DIV_20          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 20 */
-#define LL_RCC_PLLDIVR_DIV_21          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 21 */
-#define LL_RCC_PLLDIVR_DIV_22          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 22 */
-#define LL_RCC_PLLDIVR_DIV_23          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 23 */
-#define LL_RCC_PLLDIVR_DIV_24          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3)        /*!< PLL division factor for PLLDIVR output by 24 */
-#define LL_RCC_PLLDIVR_DIV_25          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 25 */
-#define LL_RCC_PLLDIVR_DIV_26          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 26 */
-#define LL_RCC_PLLDIVR_DIV_27          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 27 */
-#define LL_RCC_PLLDIVR_DIV_28          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 28 */
-#define LL_RCC_PLLDIVR_DIV_29          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 29 */
-#define LL_RCC_PLLDIVR_DIV_30          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 30 */
-#define LL_RCC_PLLDIVR_DIV_31          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 31 */
-/**
-  * @}
-  */
-#endif /* RCC_DCKCFGR_PLLDIVR */
-
-/** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)
-  * @{
-  */
-#define LL_RCC_PLLP_DIV_2                  0x00000000U            /*!< Main PLL division factor for PLLP output by 2 */
-#define LL_RCC_PLLP_DIV_4                  RCC_PLLCFGR_PLLP_0     /*!< Main PLL division factor for PLLP output by 4 */
-#define LL_RCC_PLLP_DIV_6                  RCC_PLLCFGR_PLLP_1     /*!< Main PLL division factor for PLLP output by 6 */
-#define LL_RCC_PLLP_DIV_8                  (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)   /*!< Main PLL division factor for PLLP output by 8 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)
-  * @{
-  */
-#define LL_RCC_PLLQ_DIV_2                  RCC_PLLCFGR_PLLQ_1                      /*!< Main PLL division factor for PLLQ output by 2 */
-#define LL_RCC_PLLQ_DIV_3                  (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */
-#define LL_RCC_PLLQ_DIV_4                  RCC_PLLCFGR_PLLQ_2                      /*!< Main PLL division factor for PLLQ output by 4 */
-#define LL_RCC_PLLQ_DIV_5                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */
-#define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
-#define LL_RCC_PLLQ_DIV_7                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */
-#define LL_RCC_PLLQ_DIV_8                  RCC_PLLCFGR_PLLQ_3                      /*!< Main PLL division factor for PLLQ output by 8 */
-#define LL_RCC_PLLQ_DIV_9                  (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */
-#define LL_RCC_PLLQ_DIV_10                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */
-#define LL_RCC_PLLQ_DIV_11                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */
-#define LL_RCC_PLLQ_DIV_12                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */
-#define LL_RCC_PLLQ_DIV_13                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */
-#define LL_RCC_PLLQ_DIV_14                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */
-#define LL_RCC_PLLQ_DIV_15                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_PLL_SPRE_SEL  PLL Spread Spectrum Selection
-  * @{
-  */
-#define LL_RCC_SPREAD_SELECT_CENTER        0x00000000U                   /*!< PLL center spread spectrum selection */
-#define LL_RCC_SPREAD_SELECT_DOWN          RCC_SSCGR_SPREADSEL           /*!< PLL down spread spectrum selection */
-/**
-  * @}
-  */
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/** @defgroup RCC_LL_EC_PLLI2SM  PLLI2SM division factor (PLLI2SM)
-  * @{
-  */
-#if defined(RCC_PLLI2SCFGR_PLLI2SM)
-#define LL_RCC_PLLI2SM_DIV_2             (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */
-#define LL_RCC_PLLI2SM_DIV_3             (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */
-#define LL_RCC_PLLI2SM_DIV_4             (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */
-#define LL_RCC_PLLI2SM_DIV_5             (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */
-#define LL_RCC_PLLI2SM_DIV_6             (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */
-#define LL_RCC_PLLI2SM_DIV_7             (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */
-#define LL_RCC_PLLI2SM_DIV_8             (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */
-#define LL_RCC_PLLI2SM_DIV_9             (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */
-#define LL_RCC_PLLI2SM_DIV_10            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */
-#define LL_RCC_PLLI2SM_DIV_11            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */
-#define LL_RCC_PLLI2SM_DIV_12            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */
-#define LL_RCC_PLLI2SM_DIV_13            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */
-#define LL_RCC_PLLI2SM_DIV_14            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */
-#define LL_RCC_PLLI2SM_DIV_15            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */
-#define LL_RCC_PLLI2SM_DIV_16            (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */
-#define LL_RCC_PLLI2SM_DIV_17            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */
-#define LL_RCC_PLLI2SM_DIV_18            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */
-#define LL_RCC_PLLI2SM_DIV_19            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */
-#define LL_RCC_PLLI2SM_DIV_20            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */
-#define LL_RCC_PLLI2SM_DIV_21            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */
-#define LL_RCC_PLLI2SM_DIV_22            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */
-#define LL_RCC_PLLI2SM_DIV_23            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */
-#define LL_RCC_PLLI2SM_DIV_24            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */
-#define LL_RCC_PLLI2SM_DIV_25            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */
-#define LL_RCC_PLLI2SM_DIV_26            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */
-#define LL_RCC_PLLI2SM_DIV_27            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */
-#define LL_RCC_PLLI2SM_DIV_28            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */
-#define LL_RCC_PLLI2SM_DIV_29            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */
-#define LL_RCC_PLLI2SM_DIV_30            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */
-#define LL_RCC_PLLI2SM_DIV_31            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */
-#define LL_RCC_PLLI2SM_DIV_32            (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */
-#define LL_RCC_PLLI2SM_DIV_33            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */
-#define LL_RCC_PLLI2SM_DIV_34            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */
-#define LL_RCC_PLLI2SM_DIV_35            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */
-#define LL_RCC_PLLI2SM_DIV_36            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */
-#define LL_RCC_PLLI2SM_DIV_37            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */
-#define LL_RCC_PLLI2SM_DIV_38            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */
-#define LL_RCC_PLLI2SM_DIV_39            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */
-#define LL_RCC_PLLI2SM_DIV_40            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */
-#define LL_RCC_PLLI2SM_DIV_41            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */
-#define LL_RCC_PLLI2SM_DIV_42            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */
-#define LL_RCC_PLLI2SM_DIV_43            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */
-#define LL_RCC_PLLI2SM_DIV_44            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */
-#define LL_RCC_PLLI2SM_DIV_45            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */
-#define LL_RCC_PLLI2SM_DIV_46            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */
-#define LL_RCC_PLLI2SM_DIV_47            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */
-#define LL_RCC_PLLI2SM_DIV_48            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */
-#define LL_RCC_PLLI2SM_DIV_49            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */
-#define LL_RCC_PLLI2SM_DIV_50            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */
-#define LL_RCC_PLLI2SM_DIV_51            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */
-#define LL_RCC_PLLI2SM_DIV_52            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */
-#define LL_RCC_PLLI2SM_DIV_53            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */
-#define LL_RCC_PLLI2SM_DIV_54            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */
-#define LL_RCC_PLLI2SM_DIV_55            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */
-#define LL_RCC_PLLI2SM_DIV_56            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */
-#define LL_RCC_PLLI2SM_DIV_57            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */
-#define LL_RCC_PLLI2SM_DIV_58            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */
-#define LL_RCC_PLLI2SM_DIV_59            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */
-#define LL_RCC_PLLI2SM_DIV_60            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */
-#define LL_RCC_PLLI2SM_DIV_61            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */
-#define LL_RCC_PLLI2SM_DIV_62            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */
-#define LL_RCC_PLLI2SM_DIV_63            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */
-#else
-#define LL_RCC_PLLI2SM_DIV_2              LL_RCC_PLLM_DIV_2      /*!< PLLI2S division factor for PLLI2SM output by 2 */
-#define LL_RCC_PLLI2SM_DIV_3              LL_RCC_PLLM_DIV_3      /*!< PLLI2S division factor for PLLI2SM output by 3 */
-#define LL_RCC_PLLI2SM_DIV_4              LL_RCC_PLLM_DIV_4      /*!< PLLI2S division factor for PLLI2SM output by 4 */
-#define LL_RCC_PLLI2SM_DIV_5              LL_RCC_PLLM_DIV_5      /*!< PLLI2S division factor for PLLI2SM output by 5 */
-#define LL_RCC_PLLI2SM_DIV_6              LL_RCC_PLLM_DIV_6      /*!< PLLI2S division factor for PLLI2SM output by 6 */
-#define LL_RCC_PLLI2SM_DIV_7              LL_RCC_PLLM_DIV_7      /*!< PLLI2S division factor for PLLI2SM output by 7 */
-#define LL_RCC_PLLI2SM_DIV_8              LL_RCC_PLLM_DIV_8      /*!< PLLI2S division factor for PLLI2SM output by 8 */
-#define LL_RCC_PLLI2SM_DIV_9              LL_RCC_PLLM_DIV_9      /*!< PLLI2S division factor for PLLI2SM output by 9 */
-#define LL_RCC_PLLI2SM_DIV_10             LL_RCC_PLLM_DIV_10     /*!< PLLI2S division factor for PLLI2SM output by 10 */
-#define LL_RCC_PLLI2SM_DIV_11             LL_RCC_PLLM_DIV_11     /*!< PLLI2S division factor for PLLI2SM output by 11 */
-#define LL_RCC_PLLI2SM_DIV_12             LL_RCC_PLLM_DIV_12     /*!< PLLI2S division factor for PLLI2SM output by 12 */
-#define LL_RCC_PLLI2SM_DIV_13             LL_RCC_PLLM_DIV_13     /*!< PLLI2S division factor for PLLI2SM output by 13 */
-#define LL_RCC_PLLI2SM_DIV_14             LL_RCC_PLLM_DIV_14     /*!< PLLI2S division factor for PLLI2SM output by 14 */
-#define LL_RCC_PLLI2SM_DIV_15             LL_RCC_PLLM_DIV_15     /*!< PLLI2S division factor for PLLI2SM output by 15 */
-#define LL_RCC_PLLI2SM_DIV_16             LL_RCC_PLLM_DIV_16     /*!< PLLI2S division factor for PLLI2SM output by 16 */
-#define LL_RCC_PLLI2SM_DIV_17             LL_RCC_PLLM_DIV_17     /*!< PLLI2S division factor for PLLI2SM output by 17 */
-#define LL_RCC_PLLI2SM_DIV_18             LL_RCC_PLLM_DIV_18     /*!< PLLI2S division factor for PLLI2SM output by 18 */
-#define LL_RCC_PLLI2SM_DIV_19             LL_RCC_PLLM_DIV_19     /*!< PLLI2S division factor for PLLI2SM output by 19 */
-#define LL_RCC_PLLI2SM_DIV_20             LL_RCC_PLLM_DIV_20     /*!< PLLI2S division factor for PLLI2SM output by 20 */
-#define LL_RCC_PLLI2SM_DIV_21             LL_RCC_PLLM_DIV_21     /*!< PLLI2S division factor for PLLI2SM output by 21 */
-#define LL_RCC_PLLI2SM_DIV_22             LL_RCC_PLLM_DIV_22     /*!< PLLI2S division factor for PLLI2SM output by 22 */
-#define LL_RCC_PLLI2SM_DIV_23             LL_RCC_PLLM_DIV_23     /*!< PLLI2S division factor for PLLI2SM output by 23 */
-#define LL_RCC_PLLI2SM_DIV_24             LL_RCC_PLLM_DIV_24     /*!< PLLI2S division factor for PLLI2SM output by 24 */
-#define LL_RCC_PLLI2SM_DIV_25             LL_RCC_PLLM_DIV_25     /*!< PLLI2S division factor for PLLI2SM output by 25 */
-#define LL_RCC_PLLI2SM_DIV_26             LL_RCC_PLLM_DIV_26     /*!< PLLI2S division factor for PLLI2SM output by 26 */
-#define LL_RCC_PLLI2SM_DIV_27             LL_RCC_PLLM_DIV_27     /*!< PLLI2S division factor for PLLI2SM output by 27 */
-#define LL_RCC_PLLI2SM_DIV_28             LL_RCC_PLLM_DIV_28     /*!< PLLI2S division factor for PLLI2SM output by 28 */
-#define LL_RCC_PLLI2SM_DIV_29             LL_RCC_PLLM_DIV_29     /*!< PLLI2S division factor for PLLI2SM output by 29 */
-#define LL_RCC_PLLI2SM_DIV_30             LL_RCC_PLLM_DIV_30     /*!< PLLI2S division factor for PLLI2SM output by 30 */
-#define LL_RCC_PLLI2SM_DIV_31             LL_RCC_PLLM_DIV_31     /*!< PLLI2S division factor for PLLI2SM output by 31 */
-#define LL_RCC_PLLI2SM_DIV_32             LL_RCC_PLLM_DIV_32     /*!< PLLI2S division factor for PLLI2SM output by 32 */
-#define LL_RCC_PLLI2SM_DIV_33             LL_RCC_PLLM_DIV_33     /*!< PLLI2S division factor for PLLI2SM output by 33 */
-#define LL_RCC_PLLI2SM_DIV_34             LL_RCC_PLLM_DIV_34     /*!< PLLI2S division factor for PLLI2SM output by 34 */
-#define LL_RCC_PLLI2SM_DIV_35             LL_RCC_PLLM_DIV_35     /*!< PLLI2S division factor for PLLI2SM output by 35 */
-#define LL_RCC_PLLI2SM_DIV_36             LL_RCC_PLLM_DIV_36     /*!< PLLI2S division factor for PLLI2SM output by 36 */
-#define LL_RCC_PLLI2SM_DIV_37             LL_RCC_PLLM_DIV_37     /*!< PLLI2S division factor for PLLI2SM output by 37 */
-#define LL_RCC_PLLI2SM_DIV_38             LL_RCC_PLLM_DIV_38     /*!< PLLI2S division factor for PLLI2SM output by 38 */
-#define LL_RCC_PLLI2SM_DIV_39             LL_RCC_PLLM_DIV_39     /*!< PLLI2S division factor for PLLI2SM output by 39 */
-#define LL_RCC_PLLI2SM_DIV_40             LL_RCC_PLLM_DIV_40     /*!< PLLI2S division factor for PLLI2SM output by 40 */
-#define LL_RCC_PLLI2SM_DIV_41             LL_RCC_PLLM_DIV_41     /*!< PLLI2S division factor for PLLI2SM output by 41 */
-#define LL_RCC_PLLI2SM_DIV_42             LL_RCC_PLLM_DIV_42     /*!< PLLI2S division factor for PLLI2SM output by 42 */
-#define LL_RCC_PLLI2SM_DIV_43             LL_RCC_PLLM_DIV_43     /*!< PLLI2S division factor for PLLI2SM output by 43 */
-#define LL_RCC_PLLI2SM_DIV_44             LL_RCC_PLLM_DIV_44     /*!< PLLI2S division factor for PLLI2SM output by 44 */
-#define LL_RCC_PLLI2SM_DIV_45             LL_RCC_PLLM_DIV_45     /*!< PLLI2S division factor for PLLI2SM output by 45 */
-#define LL_RCC_PLLI2SM_DIV_46             LL_RCC_PLLM_DIV_46     /*!< PLLI2S division factor for PLLI2SM output by 46 */
-#define LL_RCC_PLLI2SM_DIV_47             LL_RCC_PLLM_DIV_47     /*!< PLLI2S division factor for PLLI2SM output by 47 */
-#define LL_RCC_PLLI2SM_DIV_48             LL_RCC_PLLM_DIV_48     /*!< PLLI2S division factor for PLLI2SM output by 48 */
-#define LL_RCC_PLLI2SM_DIV_49             LL_RCC_PLLM_DIV_49     /*!< PLLI2S division factor for PLLI2SM output by 49 */
-#define LL_RCC_PLLI2SM_DIV_50             LL_RCC_PLLM_DIV_50     /*!< PLLI2S division factor for PLLI2SM output by 50 */
-#define LL_RCC_PLLI2SM_DIV_51             LL_RCC_PLLM_DIV_51     /*!< PLLI2S division factor for PLLI2SM output by 51 */
-#define LL_RCC_PLLI2SM_DIV_52             LL_RCC_PLLM_DIV_52     /*!< PLLI2S division factor for PLLI2SM output by 52 */
-#define LL_RCC_PLLI2SM_DIV_53             LL_RCC_PLLM_DIV_53     /*!< PLLI2S division factor for PLLI2SM output by 53 */
-#define LL_RCC_PLLI2SM_DIV_54             LL_RCC_PLLM_DIV_54     /*!< PLLI2S division factor for PLLI2SM output by 54 */
-#define LL_RCC_PLLI2SM_DIV_55             LL_RCC_PLLM_DIV_55     /*!< PLLI2S division factor for PLLI2SM output by 55 */
-#define LL_RCC_PLLI2SM_DIV_56             LL_RCC_PLLM_DIV_56     /*!< PLLI2S division factor for PLLI2SM output by 56 */
-#define LL_RCC_PLLI2SM_DIV_57             LL_RCC_PLLM_DIV_57     /*!< PLLI2S division factor for PLLI2SM output by 57 */
-#define LL_RCC_PLLI2SM_DIV_58             LL_RCC_PLLM_DIV_58     /*!< PLLI2S division factor for PLLI2SM output by 58 */
-#define LL_RCC_PLLI2SM_DIV_59             LL_RCC_PLLM_DIV_59     /*!< PLLI2S division factor for PLLI2SM output by 59 */
-#define LL_RCC_PLLI2SM_DIV_60             LL_RCC_PLLM_DIV_60     /*!< PLLI2S division factor for PLLI2SM output by 60 */
-#define LL_RCC_PLLI2SM_DIV_61             LL_RCC_PLLM_DIV_61     /*!< PLLI2S division factor for PLLI2SM output by 61 */
-#define LL_RCC_PLLI2SM_DIV_62             LL_RCC_PLLM_DIV_62     /*!< PLLI2S division factor for PLLI2SM output by 62 */
-#define LL_RCC_PLLI2SM_DIV_63             LL_RCC_PLLM_DIV_63     /*!< PLLI2S division factor for PLLI2SM output by 63 */
-#endif /* RCC_PLLI2SCFGR_PLLI2SM */
-/**
-  * @}
-  */
-
-#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
-/** @defgroup RCC_LL_EC_PLLI2SQ  PLLI2SQ division factor (PLLI2SQ)
-  * @{
-  */
-#define LL_RCC_PLLI2SQ_DIV_2              RCC_PLLI2SCFGR_PLLI2SQ_1        /*!< PLLI2S division factor for PLLI2SQ output by 2 */
-#define LL_RCC_PLLI2SQ_DIV_3              (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 3 */
-#define LL_RCC_PLLI2SQ_DIV_4              RCC_PLLI2SCFGR_PLLI2SQ_2        /*!< PLLI2S division factor for PLLI2SQ output by 4 */
-#define LL_RCC_PLLI2SQ_DIV_5              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 5 */
-#define LL_RCC_PLLI2SQ_DIV_6              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 6 */
-#define LL_RCC_PLLI2SQ_DIV_7              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 7 */
-#define LL_RCC_PLLI2SQ_DIV_8              RCC_PLLI2SCFGR_PLLI2SQ_3        /*!< PLLI2S division factor for PLLI2SQ output by 8 */
-#define LL_RCC_PLLI2SQ_DIV_9              (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 9 */
-#define LL_RCC_PLLI2SQ_DIV_10             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 10 */
-#define LL_RCC_PLLI2SQ_DIV_11             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 11 */
-#define LL_RCC_PLLI2SQ_DIV_12             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2)        /*!< PLLI2S division factor for PLLI2SQ output by 12 */
-#define LL_RCC_PLLI2SQ_DIV_13             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 13 */
-#define LL_RCC_PLLI2SQ_DIV_14             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 14 */
-#define LL_RCC_PLLI2SQ_DIV_15             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 15 */
-/**
-  * @}
-  */
-#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
-
-#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
-/** @defgroup RCC_LL_EC_PLLI2SDIVQ  PLLI2SDIVQ division factor (PLLI2SDIVQ)
-  * @{
-  */
-#define LL_RCC_PLLI2SDIVQ_DIV_1           0x00000000U                        /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */
-#define LL_RCC_PLLI2SDIVQ_DIV_2           RCC_DCKCFGR_PLLI2SDIVQ_0          /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */
-#define LL_RCC_PLLI2SDIVQ_DIV_3           RCC_DCKCFGR_PLLI2SDIVQ_1          /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */
-#define LL_RCC_PLLI2SDIVQ_DIV_4           (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */
-#define LL_RCC_PLLI2SDIVQ_DIV_5           RCC_DCKCFGR_PLLI2SDIVQ_2          /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */
-#define LL_RCC_PLLI2SDIVQ_DIV_6           (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */
-#define LL_RCC_PLLI2SDIVQ_DIV_7           (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */
-#define LL_RCC_PLLI2SDIVQ_DIV_8           (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */
-#define LL_RCC_PLLI2SDIVQ_DIV_9           RCC_DCKCFGR_PLLI2SDIVQ_3          /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */
-#define LL_RCC_PLLI2SDIVQ_DIV_10          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */
-#define LL_RCC_PLLI2SDIVQ_DIV_11          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */
-#define LL_RCC_PLLI2SDIVQ_DIV_12          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */
-#define LL_RCC_PLLI2SDIVQ_DIV_13          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */
-#define LL_RCC_PLLI2SDIVQ_DIV_14          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */
-#define LL_RCC_PLLI2SDIVQ_DIV_15          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */
-#define LL_RCC_PLLI2SDIVQ_DIV_16          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */
-#define LL_RCC_PLLI2SDIVQ_DIV_17          RCC_DCKCFGR_PLLI2SDIVQ_4          /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */
-#define LL_RCC_PLLI2SDIVQ_DIV_18          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */
-#define LL_RCC_PLLI2SDIVQ_DIV_19          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */
-#define LL_RCC_PLLI2SDIVQ_DIV_20          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */
-#define LL_RCC_PLLI2SDIVQ_DIV_21          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */
-#define LL_RCC_PLLI2SDIVQ_DIV_22          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */
-#define LL_RCC_PLLI2SDIVQ_DIV_23          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */
-#define LL_RCC_PLLI2SDIVQ_DIV_24          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */
-#define LL_RCC_PLLI2SDIVQ_DIV_25          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */
-#define LL_RCC_PLLI2SDIVQ_DIV_26          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */
-#define LL_RCC_PLLI2SDIVQ_DIV_27          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */
-#define LL_RCC_PLLI2SDIVQ_DIV_28          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */
-#define LL_RCC_PLLI2SDIVQ_DIV_29          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */
-#define LL_RCC_PLLI2SDIVQ_DIV_30          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */
-#define LL_RCC_PLLI2SDIVQ_DIV_31          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */
-#define LL_RCC_PLLI2SDIVQ_DIV_32          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */
-/**
-  * @}
-  */
-#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
-
-#if defined(RCC_DCKCFGR_PLLI2SDIVR)
-/** @defgroup RCC_LL_EC_PLLI2SDIVR  PLLI2SDIVR division factor (PLLI2SDIVR)
-  * @{
-  */
-#define LL_RCC_PLLI2SDIVR_DIV_1           (RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */
-#define LL_RCC_PLLI2SDIVR_DIV_2           (RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */
-#define LL_RCC_PLLI2SDIVR_DIV_3           (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */
-#define LL_RCC_PLLI2SDIVR_DIV_4           (RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */
-#define LL_RCC_PLLI2SDIVR_DIV_5           (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */
-#define LL_RCC_PLLI2SDIVR_DIV_6           (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */
-#define LL_RCC_PLLI2SDIVR_DIV_7           (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */
-#define LL_RCC_PLLI2SDIVR_DIV_8           (RCC_DCKCFGR_PLLI2SDIVR_3)        /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */
-#define LL_RCC_PLLI2SDIVR_DIV_9           (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */
-#define LL_RCC_PLLI2SDIVR_DIV_10          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */
-#define LL_RCC_PLLI2SDIVR_DIV_11          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */
-#define LL_RCC_PLLI2SDIVR_DIV_12          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */
-#define LL_RCC_PLLI2SDIVR_DIV_13          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */
-#define LL_RCC_PLLI2SDIVR_DIV_14          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */
-#define LL_RCC_PLLI2SDIVR_DIV_15          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */
-#define LL_RCC_PLLI2SDIVR_DIV_16          (RCC_DCKCFGR_PLLI2SDIVR_4)             /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */
-#define LL_RCC_PLLI2SDIVR_DIV_17          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */
-#define LL_RCC_PLLI2SDIVR_DIV_18          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */
-#define LL_RCC_PLLI2SDIVR_DIV_19          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */
-#define LL_RCC_PLLI2SDIVR_DIV_20          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */
-#define LL_RCC_PLLI2SDIVR_DIV_21          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */
-#define LL_RCC_PLLI2SDIVR_DIV_22          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */
-#define LL_RCC_PLLI2SDIVR_DIV_23          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */
-#define LL_RCC_PLLI2SDIVR_DIV_24          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3)        /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */
-#define LL_RCC_PLLI2SDIVR_DIV_25          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */
-#define LL_RCC_PLLI2SDIVR_DIV_26          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */
-#define LL_RCC_PLLI2SDIVR_DIV_27          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */
-#define LL_RCC_PLLI2SDIVR_DIV_28          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */
-#define LL_RCC_PLLI2SDIVR_DIV_29          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */
-#define LL_RCC_PLLI2SDIVR_DIV_30          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */
-#define LL_RCC_PLLI2SDIVR_DIV_31          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */
-/**
-  * @}
-  */
-#endif /* RCC_DCKCFGR_PLLI2SDIVR */
-
-/** @defgroup RCC_LL_EC_PLLI2SR  PLLI2SR division factor (PLLI2SR)
-  * @{
-  */
-#define LL_RCC_PLLI2SR_DIV_2              RCC_PLLI2SCFGR_PLLI2SR_1                                     /*!< PLLI2S division factor for PLLI2SR output by 2 */
-#define LL_RCC_PLLI2SR_DIV_3              (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 3 */
-#define LL_RCC_PLLI2SR_DIV_4              RCC_PLLI2SCFGR_PLLI2SR_2                                     /*!< PLLI2S division factor for PLLI2SR output by 4 */
-#define LL_RCC_PLLI2SR_DIV_5              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 5 */
-#define LL_RCC_PLLI2SR_DIV_6              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1)        /*!< PLLI2S division factor for PLLI2SR output by 6 */
-#define LL_RCC_PLLI2SR_DIV_7              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 7 */
-/**
-  * @}
-  */
-
-#if defined(RCC_PLLI2SCFGR_PLLI2SP)
-/** @defgroup RCC_LL_EC_PLLI2SP  PLLI2SP division factor (PLLI2SP)
-  * @{
-  */
-#define LL_RCC_PLLI2SP_DIV_2              0x00000000U            /*!< PLLI2S division factor for PLLI2SP output by 2 */
-#define LL_RCC_PLLI2SP_DIV_4              RCC_PLLI2SCFGR_PLLI2SP_0        /*!< PLLI2S division factor for PLLI2SP output by 4 */
-#define LL_RCC_PLLI2SP_DIV_6              RCC_PLLI2SCFGR_PLLI2SP_1        /*!< PLLI2S division factor for PLLI2SP output by 6 */
-#define LL_RCC_PLLI2SP_DIV_8              (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0)        /*!< PLLI2S division factor for PLLI2SP output by 8 */
-/**
-  * @}
-  */
-#endif /* RCC_PLLI2SCFGR_PLLI2SP */
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLLSAI_SUPPORT)
-/** @defgroup RCC_LL_EC_PLLSAIM  PLLSAIM division factor (PLLSAIM or PLLM)
-  * @{
-  */
-#if defined(RCC_PLLSAICFGR_PLLSAIM)
-#define LL_RCC_PLLSAIM_DIV_2             (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */
-#define LL_RCC_PLLSAIM_DIV_3             (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */
-#define LL_RCC_PLLSAIM_DIV_4             (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */
-#define LL_RCC_PLLSAIM_DIV_5             (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */
-#define LL_RCC_PLLSAIM_DIV_6             (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */
-#define LL_RCC_PLLSAIM_DIV_7             (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */
-#define LL_RCC_PLLSAIM_DIV_8             (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */
-#define LL_RCC_PLLSAIM_DIV_9             (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */
-#define LL_RCC_PLLSAIM_DIV_10            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */
-#define LL_RCC_PLLSAIM_DIV_11            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */
-#define LL_RCC_PLLSAIM_DIV_12            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */
-#define LL_RCC_PLLSAIM_DIV_13            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */
-#define LL_RCC_PLLSAIM_DIV_14            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */
-#define LL_RCC_PLLSAIM_DIV_15            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */
-#define LL_RCC_PLLSAIM_DIV_16            (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */
-#define LL_RCC_PLLSAIM_DIV_17            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */
-#define LL_RCC_PLLSAIM_DIV_18            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */
-#define LL_RCC_PLLSAIM_DIV_19            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */
-#define LL_RCC_PLLSAIM_DIV_20            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */
-#define LL_RCC_PLLSAIM_DIV_21            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */
-#define LL_RCC_PLLSAIM_DIV_22            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */
-#define LL_RCC_PLLSAIM_DIV_23            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */
-#define LL_RCC_PLLSAIM_DIV_24            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */
-#define LL_RCC_PLLSAIM_DIV_25            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */
-#define LL_RCC_PLLSAIM_DIV_26            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */
-#define LL_RCC_PLLSAIM_DIV_27            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */
-#define LL_RCC_PLLSAIM_DIV_28            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */
-#define LL_RCC_PLLSAIM_DIV_29            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */
-#define LL_RCC_PLLSAIM_DIV_30            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */
-#define LL_RCC_PLLSAIM_DIV_31            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */
-#define LL_RCC_PLLSAIM_DIV_32            (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */
-#define LL_RCC_PLLSAIM_DIV_33            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */
-#define LL_RCC_PLLSAIM_DIV_34            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */
-#define LL_RCC_PLLSAIM_DIV_35            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */
-#define LL_RCC_PLLSAIM_DIV_36            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */
-#define LL_RCC_PLLSAIM_DIV_37            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */
-#define LL_RCC_PLLSAIM_DIV_38            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */
-#define LL_RCC_PLLSAIM_DIV_39            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */
-#define LL_RCC_PLLSAIM_DIV_40            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */
-#define LL_RCC_PLLSAIM_DIV_41            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */
-#define LL_RCC_PLLSAIM_DIV_42            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */
-#define LL_RCC_PLLSAIM_DIV_43            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */
-#define LL_RCC_PLLSAIM_DIV_44            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */
-#define LL_RCC_PLLSAIM_DIV_45            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */
-#define LL_RCC_PLLSAIM_DIV_46            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */
-#define LL_RCC_PLLSAIM_DIV_47            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */
-#define LL_RCC_PLLSAIM_DIV_48            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */
-#define LL_RCC_PLLSAIM_DIV_49            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */
-#define LL_RCC_PLLSAIM_DIV_50            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */
-#define LL_RCC_PLLSAIM_DIV_51            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */
-#define LL_RCC_PLLSAIM_DIV_52            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */
-#define LL_RCC_PLLSAIM_DIV_53            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */
-#define LL_RCC_PLLSAIM_DIV_54            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */
-#define LL_RCC_PLLSAIM_DIV_55            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */
-#define LL_RCC_PLLSAIM_DIV_56            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */
-#define LL_RCC_PLLSAIM_DIV_57            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */
-#define LL_RCC_PLLSAIM_DIV_58            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */
-#define LL_RCC_PLLSAIM_DIV_59            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */
-#define LL_RCC_PLLSAIM_DIV_60            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */
-#define LL_RCC_PLLSAIM_DIV_61            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */
-#define LL_RCC_PLLSAIM_DIV_62            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */
-#define LL_RCC_PLLSAIM_DIV_63            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */
-#else
-#define LL_RCC_PLLSAIM_DIV_2              LL_RCC_PLLM_DIV_2      /*!< PLLSAI division factor for PLLSAIM output by 2 */
-#define LL_RCC_PLLSAIM_DIV_3              LL_RCC_PLLM_DIV_3      /*!< PLLSAI division factor for PLLSAIM output by 3 */
-#define LL_RCC_PLLSAIM_DIV_4              LL_RCC_PLLM_DIV_4      /*!< PLLSAI division factor for PLLSAIM output by 4 */
-#define LL_RCC_PLLSAIM_DIV_5              LL_RCC_PLLM_DIV_5      /*!< PLLSAI division factor for PLLSAIM output by 5 */
-#define LL_RCC_PLLSAIM_DIV_6              LL_RCC_PLLM_DIV_6      /*!< PLLSAI division factor for PLLSAIM output by 6 */
-#define LL_RCC_PLLSAIM_DIV_7              LL_RCC_PLLM_DIV_7      /*!< PLLSAI division factor for PLLSAIM output by 7 */
-#define LL_RCC_PLLSAIM_DIV_8              LL_RCC_PLLM_DIV_8      /*!< PLLSAI division factor for PLLSAIM output by 8 */
-#define LL_RCC_PLLSAIM_DIV_9              LL_RCC_PLLM_DIV_9      /*!< PLLSAI division factor for PLLSAIM output by 9 */
-#define LL_RCC_PLLSAIM_DIV_10             LL_RCC_PLLM_DIV_10     /*!< PLLSAI division factor for PLLSAIM output by 10 */
-#define LL_RCC_PLLSAIM_DIV_11             LL_RCC_PLLM_DIV_11     /*!< PLLSAI division factor for PLLSAIM output by 11 */
-#define LL_RCC_PLLSAIM_DIV_12             LL_RCC_PLLM_DIV_12     /*!< PLLSAI division factor for PLLSAIM output by 12 */
-#define LL_RCC_PLLSAIM_DIV_13             LL_RCC_PLLM_DIV_13     /*!< PLLSAI division factor for PLLSAIM output by 13 */
-#define LL_RCC_PLLSAIM_DIV_14             LL_RCC_PLLM_DIV_14     /*!< PLLSAI division factor for PLLSAIM output by 14 */
-#define LL_RCC_PLLSAIM_DIV_15             LL_RCC_PLLM_DIV_15     /*!< PLLSAI division factor for PLLSAIM output by 15 */
-#define LL_RCC_PLLSAIM_DIV_16             LL_RCC_PLLM_DIV_16     /*!< PLLSAI division factor for PLLSAIM output by 16 */
-#define LL_RCC_PLLSAIM_DIV_17             LL_RCC_PLLM_DIV_17     /*!< PLLSAI division factor for PLLSAIM output by 17 */
-#define LL_RCC_PLLSAIM_DIV_18             LL_RCC_PLLM_DIV_18     /*!< PLLSAI division factor for PLLSAIM output by 18 */
-#define LL_RCC_PLLSAIM_DIV_19             LL_RCC_PLLM_DIV_19     /*!< PLLSAI division factor for PLLSAIM output by 19 */
-#define LL_RCC_PLLSAIM_DIV_20             LL_RCC_PLLM_DIV_20     /*!< PLLSAI division factor for PLLSAIM output by 20 */
-#define LL_RCC_PLLSAIM_DIV_21             LL_RCC_PLLM_DIV_21     /*!< PLLSAI division factor for PLLSAIM output by 21 */
-#define LL_RCC_PLLSAIM_DIV_22             LL_RCC_PLLM_DIV_22     /*!< PLLSAI division factor for PLLSAIM output by 22 */
-#define LL_RCC_PLLSAIM_DIV_23             LL_RCC_PLLM_DIV_23     /*!< PLLSAI division factor for PLLSAIM output by 23 */
-#define LL_RCC_PLLSAIM_DIV_24             LL_RCC_PLLM_DIV_24     /*!< PLLSAI division factor for PLLSAIM output by 24 */
-#define LL_RCC_PLLSAIM_DIV_25             LL_RCC_PLLM_DIV_25     /*!< PLLSAI division factor for PLLSAIM output by 25 */
-#define LL_RCC_PLLSAIM_DIV_26             LL_RCC_PLLM_DIV_26     /*!< PLLSAI division factor for PLLSAIM output by 26 */
-#define LL_RCC_PLLSAIM_DIV_27             LL_RCC_PLLM_DIV_27     /*!< PLLSAI division factor for PLLSAIM output by 27 */
-#define LL_RCC_PLLSAIM_DIV_28             LL_RCC_PLLM_DIV_28     /*!< PLLSAI division factor for PLLSAIM output by 28 */
-#define LL_RCC_PLLSAIM_DIV_29             LL_RCC_PLLM_DIV_29     /*!< PLLSAI division factor for PLLSAIM output by 29 */
-#define LL_RCC_PLLSAIM_DIV_30             LL_RCC_PLLM_DIV_30     /*!< PLLSAI division factor for PLLSAIM output by 30 */
-#define LL_RCC_PLLSAIM_DIV_31             LL_RCC_PLLM_DIV_31     /*!< PLLSAI division factor for PLLSAIM output by 31 */
-#define LL_RCC_PLLSAIM_DIV_32             LL_RCC_PLLM_DIV_32     /*!< PLLSAI division factor for PLLSAIM output by 32 */
-#define LL_RCC_PLLSAIM_DIV_33             LL_RCC_PLLM_DIV_33     /*!< PLLSAI division factor for PLLSAIM output by 33 */
-#define LL_RCC_PLLSAIM_DIV_34             LL_RCC_PLLM_DIV_34     /*!< PLLSAI division factor for PLLSAIM output by 34 */
-#define LL_RCC_PLLSAIM_DIV_35             LL_RCC_PLLM_DIV_35     /*!< PLLSAI division factor for PLLSAIM output by 35 */
-#define LL_RCC_PLLSAIM_DIV_36             LL_RCC_PLLM_DIV_36     /*!< PLLSAI division factor for PLLSAIM output by 36 */
-#define LL_RCC_PLLSAIM_DIV_37             LL_RCC_PLLM_DIV_37     /*!< PLLSAI division factor for PLLSAIM output by 37 */
-#define LL_RCC_PLLSAIM_DIV_38             LL_RCC_PLLM_DIV_38     /*!< PLLSAI division factor for PLLSAIM output by 38 */
-#define LL_RCC_PLLSAIM_DIV_39             LL_RCC_PLLM_DIV_39     /*!< PLLSAI division factor for PLLSAIM output by 39 */
-#define LL_RCC_PLLSAIM_DIV_40             LL_RCC_PLLM_DIV_40     /*!< PLLSAI division factor for PLLSAIM output by 40 */
-#define LL_RCC_PLLSAIM_DIV_41             LL_RCC_PLLM_DIV_41     /*!< PLLSAI division factor for PLLSAIM output by 41 */
-#define LL_RCC_PLLSAIM_DIV_42             LL_RCC_PLLM_DIV_42     /*!< PLLSAI division factor for PLLSAIM output by 42 */
-#define LL_RCC_PLLSAIM_DIV_43             LL_RCC_PLLM_DIV_43     /*!< PLLSAI division factor for PLLSAIM output by 43 */
-#define LL_RCC_PLLSAIM_DIV_44             LL_RCC_PLLM_DIV_44     /*!< PLLSAI division factor for PLLSAIM output by 44 */
-#define LL_RCC_PLLSAIM_DIV_45             LL_RCC_PLLM_DIV_45     /*!< PLLSAI division factor for PLLSAIM output by 45 */
-#define LL_RCC_PLLSAIM_DIV_46             LL_RCC_PLLM_DIV_46     /*!< PLLSAI division factor for PLLSAIM output by 46 */
-#define LL_RCC_PLLSAIM_DIV_47             LL_RCC_PLLM_DIV_47     /*!< PLLSAI division factor for PLLSAIM output by 47 */
-#define LL_RCC_PLLSAIM_DIV_48             LL_RCC_PLLM_DIV_48     /*!< PLLSAI division factor for PLLSAIM output by 48 */
-#define LL_RCC_PLLSAIM_DIV_49             LL_RCC_PLLM_DIV_49     /*!< PLLSAI division factor for PLLSAIM output by 49 */
-#define LL_RCC_PLLSAIM_DIV_50             LL_RCC_PLLM_DIV_50     /*!< PLLSAI division factor for PLLSAIM output by 50 */
-#define LL_RCC_PLLSAIM_DIV_51             LL_RCC_PLLM_DIV_51     /*!< PLLSAI division factor for PLLSAIM output by 51 */
-#define LL_RCC_PLLSAIM_DIV_52             LL_RCC_PLLM_DIV_52     /*!< PLLSAI division factor for PLLSAIM output by 52 */
-#define LL_RCC_PLLSAIM_DIV_53             LL_RCC_PLLM_DIV_53     /*!< PLLSAI division factor for PLLSAIM output by 53 */
-#define LL_RCC_PLLSAIM_DIV_54             LL_RCC_PLLM_DIV_54     /*!< PLLSAI division factor for PLLSAIM output by 54 */
-#define LL_RCC_PLLSAIM_DIV_55             LL_RCC_PLLM_DIV_55     /*!< PLLSAI division factor for PLLSAIM output by 55 */
-#define LL_RCC_PLLSAIM_DIV_56             LL_RCC_PLLM_DIV_56     /*!< PLLSAI division factor for PLLSAIM output by 56 */
-#define LL_RCC_PLLSAIM_DIV_57             LL_RCC_PLLM_DIV_57     /*!< PLLSAI division factor for PLLSAIM output by 57 */
-#define LL_RCC_PLLSAIM_DIV_58             LL_RCC_PLLM_DIV_58     /*!< PLLSAI division factor for PLLSAIM output by 58 */
-#define LL_RCC_PLLSAIM_DIV_59             LL_RCC_PLLM_DIV_59     /*!< PLLSAI division factor for PLLSAIM output by 59 */
-#define LL_RCC_PLLSAIM_DIV_60             LL_RCC_PLLM_DIV_60     /*!< PLLSAI division factor for PLLSAIM output by 60 */
-#define LL_RCC_PLLSAIM_DIV_61             LL_RCC_PLLM_DIV_61     /*!< PLLSAI division factor for PLLSAIM output by 61 */
-#define LL_RCC_PLLSAIM_DIV_62             LL_RCC_PLLM_DIV_62     /*!< PLLSAI division factor for PLLSAIM output by 62 */
-#define LL_RCC_PLLSAIM_DIV_63             LL_RCC_PLLM_DIV_63     /*!< PLLSAI division factor for PLLSAIM output by 63 */
-#endif /* RCC_PLLSAICFGR_PLLSAIM */
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EC_PLLSAIQ  PLLSAIQ division factor (PLLSAIQ)
-  * @{
-  */
-#define LL_RCC_PLLSAIQ_DIV_2              RCC_PLLSAICFGR_PLLSAIQ_1        /*!< PLLSAI division factor for PLLSAIQ output by 2 */
-#define LL_RCC_PLLSAIQ_DIV_3              (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 3 */
-#define LL_RCC_PLLSAIQ_DIV_4              RCC_PLLSAICFGR_PLLSAIQ_2        /*!< PLLSAI division factor for PLLSAIQ output by 4 */
-#define LL_RCC_PLLSAIQ_DIV_5              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 5 */
-#define LL_RCC_PLLSAIQ_DIV_6              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 6 */
-#define LL_RCC_PLLSAIQ_DIV_7              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 7 */
-#define LL_RCC_PLLSAIQ_DIV_8              RCC_PLLSAICFGR_PLLSAIQ_3        /*!< PLLSAI division factor for PLLSAIQ output by 8 */
-#define LL_RCC_PLLSAIQ_DIV_9              (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 9 */
-#define LL_RCC_PLLSAIQ_DIV_10             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 10 */
-#define LL_RCC_PLLSAIQ_DIV_11             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 11 */
-#define LL_RCC_PLLSAIQ_DIV_12             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2)        /*!< PLLSAI division factor for PLLSAIQ output by 12 */
-#define LL_RCC_PLLSAIQ_DIV_13             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 13 */
-#define LL_RCC_PLLSAIQ_DIV_14             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 14 */
-#define LL_RCC_PLLSAIQ_DIV_15             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 15 */
-/**
-  * @}
-  */
-
-#if defined(RCC_DCKCFGR_PLLSAIDIVQ)
-/** @defgroup RCC_LL_EC_PLLSAIDIVQ  PLLSAIDIVQ division factor (PLLSAIDIVQ)
-  * @{
-  */
-#define LL_RCC_PLLSAIDIVQ_DIV_1           0x00000000U               /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */
-#define LL_RCC_PLLSAIDIVQ_DIV_2           RCC_DCKCFGR_PLLSAIDIVQ_0          /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */
-#define LL_RCC_PLLSAIDIVQ_DIV_3           RCC_DCKCFGR_PLLSAIDIVQ_1          /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */
-#define LL_RCC_PLLSAIDIVQ_DIV_4           (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */
-#define LL_RCC_PLLSAIDIVQ_DIV_5           RCC_DCKCFGR_PLLSAIDIVQ_2          /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */
-#define LL_RCC_PLLSAIDIVQ_DIV_6           (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */
-#define LL_RCC_PLLSAIDIVQ_DIV_7           (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */
-#define LL_RCC_PLLSAIDIVQ_DIV_8           (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */
-#define LL_RCC_PLLSAIDIVQ_DIV_9           RCC_DCKCFGR_PLLSAIDIVQ_3          /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */
-#define LL_RCC_PLLSAIDIVQ_DIV_10          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */
-#define LL_RCC_PLLSAIDIVQ_DIV_11          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */
-#define LL_RCC_PLLSAIDIVQ_DIV_12          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */
-#define LL_RCC_PLLSAIDIVQ_DIV_13          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */
-#define LL_RCC_PLLSAIDIVQ_DIV_14          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */
-#define LL_RCC_PLLSAIDIVQ_DIV_15          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */
-#define LL_RCC_PLLSAIDIVQ_DIV_16          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */
-#define LL_RCC_PLLSAIDIVQ_DIV_17          RCC_DCKCFGR_PLLSAIDIVQ_4         /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */
-#define LL_RCC_PLLSAIDIVQ_DIV_18          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */
-#define LL_RCC_PLLSAIDIVQ_DIV_19          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */
-#define LL_RCC_PLLSAIDIVQ_DIV_20          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */
-#define LL_RCC_PLLSAIDIVQ_DIV_21          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */
-#define LL_RCC_PLLSAIDIVQ_DIV_22          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */
-#define LL_RCC_PLLSAIDIVQ_DIV_23          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */
-#define LL_RCC_PLLSAIDIVQ_DIV_24          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */
-#define LL_RCC_PLLSAIDIVQ_DIV_25          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */
-#define LL_RCC_PLLSAIDIVQ_DIV_26          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */
-#define LL_RCC_PLLSAIDIVQ_DIV_27          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */
-#define LL_RCC_PLLSAIDIVQ_DIV_28          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */
-#define LL_RCC_PLLSAIDIVQ_DIV_29          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */
-#define LL_RCC_PLLSAIDIVQ_DIV_30          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */
-#define LL_RCC_PLLSAIDIVQ_DIV_31          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */
-#define LL_RCC_PLLSAIDIVQ_DIV_32          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */
-/**
-  * @}
-  */
-#endif /* RCC_DCKCFGR_PLLSAIDIVQ */
-
-#if defined(RCC_PLLSAICFGR_PLLSAIR)
-/** @defgroup RCC_LL_EC_PLLSAIR  PLLSAIR division factor (PLLSAIR)
-  * @{
-  */
-#define LL_RCC_PLLSAIR_DIV_2              RCC_PLLSAICFGR_PLLSAIR_1                                     /*!< PLLSAI division factor for PLLSAIR output by 2 */
-#define LL_RCC_PLLSAIR_DIV_3              (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 3 */
-#define LL_RCC_PLLSAIR_DIV_4              RCC_PLLSAICFGR_PLLSAIR_2                                     /*!< PLLSAI division factor for PLLSAIR output by 4 */
-#define LL_RCC_PLLSAIR_DIV_5              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 5 */
-#define LL_RCC_PLLSAIR_DIV_6              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1)        /*!< PLLSAI division factor for PLLSAIR output by 6 */
-#define LL_RCC_PLLSAIR_DIV_7              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 7 */
-/**
-  * @}
-  */
-#endif /* RCC_PLLSAICFGR_PLLSAIR */
-
-#if defined(RCC_DCKCFGR_PLLSAIDIVR)
-/** @defgroup RCC_LL_EC_PLLSAIDIVR  PLLSAIDIVR division factor (PLLSAIDIVR)
-  * @{
-  */
-#define LL_RCC_PLLSAIDIVR_DIV_2           0x00000000U             /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */
-#define LL_RCC_PLLSAIDIVR_DIV_4           RCC_DCKCFGR_PLLSAIDIVR_0        /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */
-#define LL_RCC_PLLSAIDIVR_DIV_8           RCC_DCKCFGR_PLLSAIDIVR_1        /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */
-#define LL_RCC_PLLSAIDIVR_DIV_16          (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0)        /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */
-/**
-  * @}
-  */
-#endif /* RCC_DCKCFGR_PLLSAIDIVR */
-
-#if defined(RCC_PLLSAICFGR_PLLSAIP)
-/** @defgroup RCC_LL_EC_PLLSAIP  PLLSAIP division factor (PLLSAIP)
-  * @{
-  */
-#define LL_RCC_PLLSAIP_DIV_2              0x00000000U               /*!< PLLSAI division factor for PLLSAIP output by 2 */
-#define LL_RCC_PLLSAIP_DIV_4              RCC_PLLSAICFGR_PLLSAIP_0        /*!< PLLSAI division factor for PLLSAIP output by 4 */
-#define LL_RCC_PLLSAIP_DIV_6              RCC_PLLSAICFGR_PLLSAIP_1        /*!< PLLSAI division factor for PLLSAIP output by 6 */
-#define LL_RCC_PLLSAIP_DIV_8              (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0)        /*!< PLLSAI division factor for PLLSAIP output by 8 */
-/**
-  * @}
-  */
-#endif /* RCC_PLLSAICFGR_PLLSAIP */
-#endif /* RCC_PLLSAI_SUPPORT */
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
-  * @{
-  */
-
-/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in RCC register
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in RCC register
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
-  * @{
-  */
-
-/**
-  * @brief  Helper macro to calculate the PLLCLK frequency on system domain
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
-  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  *         @arg @ref LL_RCC_PLLM_DIV_9
-  *         @arg @ref LL_RCC_PLLM_DIV_10
-  *         @arg @ref LL_RCC_PLLM_DIV_11
-  *         @arg @ref LL_RCC_PLLM_DIV_12
-  *         @arg @ref LL_RCC_PLLM_DIV_13
-  *         @arg @ref LL_RCC_PLLM_DIV_14
-  *         @arg @ref LL_RCC_PLLM_DIV_15
-  *         @arg @ref LL_RCC_PLLM_DIV_16
-  *         @arg @ref LL_RCC_PLLM_DIV_17
-  *         @arg @ref LL_RCC_PLLM_DIV_18
-  *         @arg @ref LL_RCC_PLLM_DIV_19
-  *         @arg @ref LL_RCC_PLLM_DIV_20
-  *         @arg @ref LL_RCC_PLLM_DIV_21
-  *         @arg @ref LL_RCC_PLLM_DIV_22
-  *         @arg @ref LL_RCC_PLLM_DIV_23
-  *         @arg @ref LL_RCC_PLLM_DIV_24
-  *         @arg @ref LL_RCC_PLLM_DIV_25
-  *         @arg @ref LL_RCC_PLLM_DIV_26
-  *         @arg @ref LL_RCC_PLLM_DIV_27
-  *         @arg @ref LL_RCC_PLLM_DIV_28
-  *         @arg @ref LL_RCC_PLLM_DIV_29
-  *         @arg @ref LL_RCC_PLLM_DIV_30
-  *         @arg @ref LL_RCC_PLLM_DIV_31
-  *         @arg @ref LL_RCC_PLLM_DIV_32
-  *         @arg @ref LL_RCC_PLLM_DIV_33
-  *         @arg @ref LL_RCC_PLLM_DIV_34
-  *         @arg @ref LL_RCC_PLLM_DIV_35
-  *         @arg @ref LL_RCC_PLLM_DIV_36
-  *         @arg @ref LL_RCC_PLLM_DIV_37
-  *         @arg @ref LL_RCC_PLLM_DIV_38
-  *         @arg @ref LL_RCC_PLLM_DIV_39
-  *         @arg @ref LL_RCC_PLLM_DIV_40
-  *         @arg @ref LL_RCC_PLLM_DIV_41
-  *         @arg @ref LL_RCC_PLLM_DIV_42
-  *         @arg @ref LL_RCC_PLLM_DIV_43
-  *         @arg @ref LL_RCC_PLLM_DIV_44
-  *         @arg @ref LL_RCC_PLLM_DIV_45
-  *         @arg @ref LL_RCC_PLLM_DIV_46
-  *         @arg @ref LL_RCC_PLLM_DIV_47
-  *         @arg @ref LL_RCC_PLLM_DIV_48
-  *         @arg @ref LL_RCC_PLLM_DIV_49
-  *         @arg @ref LL_RCC_PLLM_DIV_50
-  *         @arg @ref LL_RCC_PLLM_DIV_51
-  *         @arg @ref LL_RCC_PLLM_DIV_52
-  *         @arg @ref LL_RCC_PLLM_DIV_53
-  *         @arg @ref LL_RCC_PLLM_DIV_54
-  *         @arg @ref LL_RCC_PLLM_DIV_55
-  *         @arg @ref LL_RCC_PLLM_DIV_56
-  *         @arg @ref LL_RCC_PLLM_DIV_57
-  *         @arg @ref LL_RCC_PLLM_DIV_58
-  *         @arg @ref LL_RCC_PLLM_DIV_59
-  *         @arg @ref LL_RCC_PLLM_DIV_60
-  *         @arg @ref LL_RCC_PLLM_DIV_61
-  *         @arg @ref LL_RCC_PLLM_DIV_62
-  *         @arg @ref LL_RCC_PLLM_DIV_63
-  * @param  __PLLN__ Between 50/192(*) and 432
-  *
-  *         (*) value not defined in all devices.
-  * @param  __PLLP__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLP_DIV_2
-  *         @arg @ref LL_RCC_PLLP_DIV_4
-  *         @arg @ref LL_RCC_PLLP_DIV_6
-  *         @arg @ref LL_RCC_PLLP_DIV_8
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
-                   ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
-
-#if defined(RCC_PLLR_SYSCLK_SUPPORT)
-/**
-  * @brief  Helper macro to calculate the PLLRCLK frequency on system domain
-  * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
-  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  *         @arg @ref LL_RCC_PLLM_DIV_9
-  *         @arg @ref LL_RCC_PLLM_DIV_10
-  *         @arg @ref LL_RCC_PLLM_DIV_11
-  *         @arg @ref LL_RCC_PLLM_DIV_12
-  *         @arg @ref LL_RCC_PLLM_DIV_13
-  *         @arg @ref LL_RCC_PLLM_DIV_14
-  *         @arg @ref LL_RCC_PLLM_DIV_15
-  *         @arg @ref LL_RCC_PLLM_DIV_16
-  *         @arg @ref LL_RCC_PLLM_DIV_17
-  *         @arg @ref LL_RCC_PLLM_DIV_18
-  *         @arg @ref LL_RCC_PLLM_DIV_19
-  *         @arg @ref LL_RCC_PLLM_DIV_20
-  *         @arg @ref LL_RCC_PLLM_DIV_21
-  *         @arg @ref LL_RCC_PLLM_DIV_22
-  *         @arg @ref LL_RCC_PLLM_DIV_23
-  *         @arg @ref LL_RCC_PLLM_DIV_24
-  *         @arg @ref LL_RCC_PLLM_DIV_25
-  *         @arg @ref LL_RCC_PLLM_DIV_26
-  *         @arg @ref LL_RCC_PLLM_DIV_27
-  *         @arg @ref LL_RCC_PLLM_DIV_28
-  *         @arg @ref LL_RCC_PLLM_DIV_29
-  *         @arg @ref LL_RCC_PLLM_DIV_30
-  *         @arg @ref LL_RCC_PLLM_DIV_31
-  *         @arg @ref LL_RCC_PLLM_DIV_32
-  *         @arg @ref LL_RCC_PLLM_DIV_33
-  *         @arg @ref LL_RCC_PLLM_DIV_34
-  *         @arg @ref LL_RCC_PLLM_DIV_35
-  *         @arg @ref LL_RCC_PLLM_DIV_36
-  *         @arg @ref LL_RCC_PLLM_DIV_37
-  *         @arg @ref LL_RCC_PLLM_DIV_38
-  *         @arg @ref LL_RCC_PLLM_DIV_39
-  *         @arg @ref LL_RCC_PLLM_DIV_40
-  *         @arg @ref LL_RCC_PLLM_DIV_41
-  *         @arg @ref LL_RCC_PLLM_DIV_42
-  *         @arg @ref LL_RCC_PLLM_DIV_43
-  *         @arg @ref LL_RCC_PLLM_DIV_44
-  *         @arg @ref LL_RCC_PLLM_DIV_45
-  *         @arg @ref LL_RCC_PLLM_DIV_46
-  *         @arg @ref LL_RCC_PLLM_DIV_47
-  *         @arg @ref LL_RCC_PLLM_DIV_48
-  *         @arg @ref LL_RCC_PLLM_DIV_49
-  *         @arg @ref LL_RCC_PLLM_DIV_50
-  *         @arg @ref LL_RCC_PLLM_DIV_51
-  *         @arg @ref LL_RCC_PLLM_DIV_52
-  *         @arg @ref LL_RCC_PLLM_DIV_53
-  *         @arg @ref LL_RCC_PLLM_DIV_54
-  *         @arg @ref LL_RCC_PLLM_DIV_55
-  *         @arg @ref LL_RCC_PLLM_DIV_56
-  *         @arg @ref LL_RCC_PLLM_DIV_57
-  *         @arg @ref LL_RCC_PLLM_DIV_58
-  *         @arg @ref LL_RCC_PLLM_DIV_59
-  *         @arg @ref LL_RCC_PLLM_DIV_60
-  *         @arg @ref LL_RCC_PLLM_DIV_61
-  *         @arg @ref LL_RCC_PLLM_DIV_62
-  *         @arg @ref LL_RCC_PLLM_DIV_63
-  * @param  __PLLN__ Between 50 and 432
-  * @param  __PLLR__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLR_DIV_2
-  *         @arg @ref LL_RCC_PLLR_DIV_3
-  *         @arg @ref LL_RCC_PLLR_DIV_4
-  *         @arg @ref LL_RCC_PLLR_DIV_5
-  *         @arg @ref LL_RCC_PLLR_DIV_6
-  *         @arg @ref LL_RCC_PLLR_DIV_7
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
-                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
-
-#endif /* RCC_PLLR_SYSCLK_SUPPORT */
-
-/**
-  * @brief  Helper macro to calculate the PLLCLK frequency used on 48M domain
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
-  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  *         @arg @ref LL_RCC_PLLM_DIV_9
-  *         @arg @ref LL_RCC_PLLM_DIV_10
-  *         @arg @ref LL_RCC_PLLM_DIV_11
-  *         @arg @ref LL_RCC_PLLM_DIV_12
-  *         @arg @ref LL_RCC_PLLM_DIV_13
-  *         @arg @ref LL_RCC_PLLM_DIV_14
-  *         @arg @ref LL_RCC_PLLM_DIV_15
-  *         @arg @ref LL_RCC_PLLM_DIV_16
-  *         @arg @ref LL_RCC_PLLM_DIV_17
-  *         @arg @ref LL_RCC_PLLM_DIV_18
-  *         @arg @ref LL_RCC_PLLM_DIV_19
-  *         @arg @ref LL_RCC_PLLM_DIV_20
-  *         @arg @ref LL_RCC_PLLM_DIV_21
-  *         @arg @ref LL_RCC_PLLM_DIV_22
-  *         @arg @ref LL_RCC_PLLM_DIV_23
-  *         @arg @ref LL_RCC_PLLM_DIV_24
-  *         @arg @ref LL_RCC_PLLM_DIV_25
-  *         @arg @ref LL_RCC_PLLM_DIV_26
-  *         @arg @ref LL_RCC_PLLM_DIV_27
-  *         @arg @ref LL_RCC_PLLM_DIV_28
-  *         @arg @ref LL_RCC_PLLM_DIV_29
-  *         @arg @ref LL_RCC_PLLM_DIV_30
-  *         @arg @ref LL_RCC_PLLM_DIV_31
-  *         @arg @ref LL_RCC_PLLM_DIV_32
-  *         @arg @ref LL_RCC_PLLM_DIV_33
-  *         @arg @ref LL_RCC_PLLM_DIV_34
-  *         @arg @ref LL_RCC_PLLM_DIV_35
-  *         @arg @ref LL_RCC_PLLM_DIV_36
-  *         @arg @ref LL_RCC_PLLM_DIV_37
-  *         @arg @ref LL_RCC_PLLM_DIV_38
-  *         @arg @ref LL_RCC_PLLM_DIV_39
-  *         @arg @ref LL_RCC_PLLM_DIV_40
-  *         @arg @ref LL_RCC_PLLM_DIV_41
-  *         @arg @ref LL_RCC_PLLM_DIV_42
-  *         @arg @ref LL_RCC_PLLM_DIV_43
-  *         @arg @ref LL_RCC_PLLM_DIV_44
-  *         @arg @ref LL_RCC_PLLM_DIV_45
-  *         @arg @ref LL_RCC_PLLM_DIV_46
-  *         @arg @ref LL_RCC_PLLM_DIV_47
-  *         @arg @ref LL_RCC_PLLM_DIV_48
-  *         @arg @ref LL_RCC_PLLM_DIV_49
-  *         @arg @ref LL_RCC_PLLM_DIV_50
-  *         @arg @ref LL_RCC_PLLM_DIV_51
-  *         @arg @ref LL_RCC_PLLM_DIV_52
-  *         @arg @ref LL_RCC_PLLM_DIV_53
-  *         @arg @ref LL_RCC_PLLM_DIV_54
-  *         @arg @ref LL_RCC_PLLM_DIV_55
-  *         @arg @ref LL_RCC_PLLM_DIV_56
-  *         @arg @ref LL_RCC_PLLM_DIV_57
-  *         @arg @ref LL_RCC_PLLM_DIV_58
-  *         @arg @ref LL_RCC_PLLM_DIV_59
-  *         @arg @ref LL_RCC_PLLM_DIV_60
-  *         @arg @ref LL_RCC_PLLM_DIV_61
-  *         @arg @ref LL_RCC_PLLM_DIV_62
-  *         @arg @ref LL_RCC_PLLM_DIV_63
-  * @param  __PLLN__ Between 50/192(*) and 432
-  *
-  *         (*) value not defined in all devices.
-  * @param  __PLLQ__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLQ_DIV_2
-  *         @arg @ref LL_RCC_PLLQ_DIV_3
-  *         @arg @ref LL_RCC_PLLQ_DIV_4
-  *         @arg @ref LL_RCC_PLLQ_DIV_5
-  *         @arg @ref LL_RCC_PLLQ_DIV_6
-  *         @arg @ref LL_RCC_PLLQ_DIV_7
-  *         @arg @ref LL_RCC_PLLQ_DIV_8
-  *         @arg @ref LL_RCC_PLLQ_DIV_9
-  *         @arg @ref LL_RCC_PLLQ_DIV_10
-  *         @arg @ref LL_RCC_PLLQ_DIV_11
-  *         @arg @ref LL_RCC_PLLQ_DIV_12
-  *         @arg @ref LL_RCC_PLLQ_DIV_13
-  *         @arg @ref LL_RCC_PLLQ_DIV_14
-  *         @arg @ref LL_RCC_PLLQ_DIV_15
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
-                   ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
-
-#if defined(DSI)
-/**
-  * @brief  Helper macro to calculate the PLLCLK frequency used on DSI
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
-  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  *         @arg @ref LL_RCC_PLLM_DIV_9
-  *         @arg @ref LL_RCC_PLLM_DIV_10
-  *         @arg @ref LL_RCC_PLLM_DIV_11
-  *         @arg @ref LL_RCC_PLLM_DIV_12
-  *         @arg @ref LL_RCC_PLLM_DIV_13
-  *         @arg @ref LL_RCC_PLLM_DIV_14
-  *         @arg @ref LL_RCC_PLLM_DIV_15
-  *         @arg @ref LL_RCC_PLLM_DIV_16
-  *         @arg @ref LL_RCC_PLLM_DIV_17
-  *         @arg @ref LL_RCC_PLLM_DIV_18
-  *         @arg @ref LL_RCC_PLLM_DIV_19
-  *         @arg @ref LL_RCC_PLLM_DIV_20
-  *         @arg @ref LL_RCC_PLLM_DIV_21
-  *         @arg @ref LL_RCC_PLLM_DIV_22
-  *         @arg @ref LL_RCC_PLLM_DIV_23
-  *         @arg @ref LL_RCC_PLLM_DIV_24
-  *         @arg @ref LL_RCC_PLLM_DIV_25
-  *         @arg @ref LL_RCC_PLLM_DIV_26
-  *         @arg @ref LL_RCC_PLLM_DIV_27
-  *         @arg @ref LL_RCC_PLLM_DIV_28
-  *         @arg @ref LL_RCC_PLLM_DIV_29
-  *         @arg @ref LL_RCC_PLLM_DIV_30
-  *         @arg @ref LL_RCC_PLLM_DIV_31
-  *         @arg @ref LL_RCC_PLLM_DIV_32
-  *         @arg @ref LL_RCC_PLLM_DIV_33
-  *         @arg @ref LL_RCC_PLLM_DIV_34
-  *         @arg @ref LL_RCC_PLLM_DIV_35
-  *         @arg @ref LL_RCC_PLLM_DIV_36
-  *         @arg @ref LL_RCC_PLLM_DIV_37
-  *         @arg @ref LL_RCC_PLLM_DIV_38
-  *         @arg @ref LL_RCC_PLLM_DIV_39
-  *         @arg @ref LL_RCC_PLLM_DIV_40
-  *         @arg @ref LL_RCC_PLLM_DIV_41
-  *         @arg @ref LL_RCC_PLLM_DIV_42
-  *         @arg @ref LL_RCC_PLLM_DIV_43
-  *         @arg @ref LL_RCC_PLLM_DIV_44
-  *         @arg @ref LL_RCC_PLLM_DIV_45
-  *         @arg @ref LL_RCC_PLLM_DIV_46
-  *         @arg @ref LL_RCC_PLLM_DIV_47
-  *         @arg @ref LL_RCC_PLLM_DIV_48
-  *         @arg @ref LL_RCC_PLLM_DIV_49
-  *         @arg @ref LL_RCC_PLLM_DIV_50
-  *         @arg @ref LL_RCC_PLLM_DIV_51
-  *         @arg @ref LL_RCC_PLLM_DIV_52
-  *         @arg @ref LL_RCC_PLLM_DIV_53
-  *         @arg @ref LL_RCC_PLLM_DIV_54
-  *         @arg @ref LL_RCC_PLLM_DIV_55
-  *         @arg @ref LL_RCC_PLLM_DIV_56
-  *         @arg @ref LL_RCC_PLLM_DIV_57
-  *         @arg @ref LL_RCC_PLLM_DIV_58
-  *         @arg @ref LL_RCC_PLLM_DIV_59
-  *         @arg @ref LL_RCC_PLLM_DIV_60
-  *         @arg @ref LL_RCC_PLLM_DIV_61
-  *         @arg @ref LL_RCC_PLLM_DIV_62
-  *         @arg @ref LL_RCC_PLLM_DIV_63
-  * @param  __PLLN__ Between 50 and 432
-  * @param  __PLLR__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLR_DIV_2
-  *         @arg @ref LL_RCC_PLLR_DIV_3
-  *         @arg @ref LL_RCC_PLLR_DIV_4
-  *         @arg @ref LL_RCC_PLLR_DIV_5
-  *         @arg @ref LL_RCC_PLLR_DIV_6
-  *         @arg @ref LL_RCC_PLLR_DIV_7
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
-                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
-#endif /* DSI */
-
-#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
-/**
-  * @brief  Helper macro to calculate the PLLCLK frequency used on I2S
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
-  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  *         @arg @ref LL_RCC_PLLM_DIV_9
-  *         @arg @ref LL_RCC_PLLM_DIV_10
-  *         @arg @ref LL_RCC_PLLM_DIV_11
-  *         @arg @ref LL_RCC_PLLM_DIV_12
-  *         @arg @ref LL_RCC_PLLM_DIV_13
-  *         @arg @ref LL_RCC_PLLM_DIV_14
-  *         @arg @ref LL_RCC_PLLM_DIV_15
-  *         @arg @ref LL_RCC_PLLM_DIV_16
-  *         @arg @ref LL_RCC_PLLM_DIV_17
-  *         @arg @ref LL_RCC_PLLM_DIV_18
-  *         @arg @ref LL_RCC_PLLM_DIV_19
-  *         @arg @ref LL_RCC_PLLM_DIV_20
-  *         @arg @ref LL_RCC_PLLM_DIV_21
-  *         @arg @ref LL_RCC_PLLM_DIV_22
-  *         @arg @ref LL_RCC_PLLM_DIV_23
-  *         @arg @ref LL_RCC_PLLM_DIV_24
-  *         @arg @ref LL_RCC_PLLM_DIV_25
-  *         @arg @ref LL_RCC_PLLM_DIV_26
-  *         @arg @ref LL_RCC_PLLM_DIV_27
-  *         @arg @ref LL_RCC_PLLM_DIV_28
-  *         @arg @ref LL_RCC_PLLM_DIV_29
-  *         @arg @ref LL_RCC_PLLM_DIV_30
-  *         @arg @ref LL_RCC_PLLM_DIV_31
-  *         @arg @ref LL_RCC_PLLM_DIV_32
-  *         @arg @ref LL_RCC_PLLM_DIV_33
-  *         @arg @ref LL_RCC_PLLM_DIV_34
-  *         @arg @ref LL_RCC_PLLM_DIV_35
-  *         @arg @ref LL_RCC_PLLM_DIV_36
-  *         @arg @ref LL_RCC_PLLM_DIV_37
-  *         @arg @ref LL_RCC_PLLM_DIV_38
-  *         @arg @ref LL_RCC_PLLM_DIV_39
-  *         @arg @ref LL_RCC_PLLM_DIV_40
-  *         @arg @ref LL_RCC_PLLM_DIV_41
-  *         @arg @ref LL_RCC_PLLM_DIV_42
-  *         @arg @ref LL_RCC_PLLM_DIV_43
-  *         @arg @ref LL_RCC_PLLM_DIV_44
-  *         @arg @ref LL_RCC_PLLM_DIV_45
-  *         @arg @ref LL_RCC_PLLM_DIV_46
-  *         @arg @ref LL_RCC_PLLM_DIV_47
-  *         @arg @ref LL_RCC_PLLM_DIV_48
-  *         @arg @ref LL_RCC_PLLM_DIV_49
-  *         @arg @ref LL_RCC_PLLM_DIV_50
-  *         @arg @ref LL_RCC_PLLM_DIV_51
-  *         @arg @ref LL_RCC_PLLM_DIV_52
-  *         @arg @ref LL_RCC_PLLM_DIV_53
-  *         @arg @ref LL_RCC_PLLM_DIV_54
-  *         @arg @ref LL_RCC_PLLM_DIV_55
-  *         @arg @ref LL_RCC_PLLM_DIV_56
-  *         @arg @ref LL_RCC_PLLM_DIV_57
-  *         @arg @ref LL_RCC_PLLM_DIV_58
-  *         @arg @ref LL_RCC_PLLM_DIV_59
-  *         @arg @ref LL_RCC_PLLM_DIV_60
-  *         @arg @ref LL_RCC_PLLM_DIV_61
-  *         @arg @ref LL_RCC_PLLM_DIV_62
-  *         @arg @ref LL_RCC_PLLM_DIV_63
-  * @param  __PLLN__ Between 50 and 432
-  * @param  __PLLR__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLR_DIV_2
-  *         @arg @ref LL_RCC_PLLR_DIV_3
-  *         @arg @ref LL_RCC_PLLR_DIV_4
-  *         @arg @ref LL_RCC_PLLR_DIV_5
-  *         @arg @ref LL_RCC_PLLR_DIV_6
-  *         @arg @ref LL_RCC_PLLR_DIV_7
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
-                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
-#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
-
-#if defined(SPDIFRX)
-/**
-  * @brief  Helper macro to calculate the PLLCLK frequency used on SPDIFRX
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
-  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  *         @arg @ref LL_RCC_PLLM_DIV_9
-  *         @arg @ref LL_RCC_PLLM_DIV_10
-  *         @arg @ref LL_RCC_PLLM_DIV_11
-  *         @arg @ref LL_RCC_PLLM_DIV_12
-  *         @arg @ref LL_RCC_PLLM_DIV_13
-  *         @arg @ref LL_RCC_PLLM_DIV_14
-  *         @arg @ref LL_RCC_PLLM_DIV_15
-  *         @arg @ref LL_RCC_PLLM_DIV_16
-  *         @arg @ref LL_RCC_PLLM_DIV_17
-  *         @arg @ref LL_RCC_PLLM_DIV_18
-  *         @arg @ref LL_RCC_PLLM_DIV_19
-  *         @arg @ref LL_RCC_PLLM_DIV_20
-  *         @arg @ref LL_RCC_PLLM_DIV_21
-  *         @arg @ref LL_RCC_PLLM_DIV_22
-  *         @arg @ref LL_RCC_PLLM_DIV_23
-  *         @arg @ref LL_RCC_PLLM_DIV_24
-  *         @arg @ref LL_RCC_PLLM_DIV_25
-  *         @arg @ref LL_RCC_PLLM_DIV_26
-  *         @arg @ref LL_RCC_PLLM_DIV_27
-  *         @arg @ref LL_RCC_PLLM_DIV_28
-  *         @arg @ref LL_RCC_PLLM_DIV_29
-  *         @arg @ref LL_RCC_PLLM_DIV_30
-  *         @arg @ref LL_RCC_PLLM_DIV_31
-  *         @arg @ref LL_RCC_PLLM_DIV_32
-  *         @arg @ref LL_RCC_PLLM_DIV_33
-  *         @arg @ref LL_RCC_PLLM_DIV_34
-  *         @arg @ref LL_RCC_PLLM_DIV_35
-  *         @arg @ref LL_RCC_PLLM_DIV_36
-  *         @arg @ref LL_RCC_PLLM_DIV_37
-  *         @arg @ref LL_RCC_PLLM_DIV_38
-  *         @arg @ref LL_RCC_PLLM_DIV_39
-  *         @arg @ref LL_RCC_PLLM_DIV_40
-  *         @arg @ref LL_RCC_PLLM_DIV_41
-  *         @arg @ref LL_RCC_PLLM_DIV_42
-  *         @arg @ref LL_RCC_PLLM_DIV_43
-  *         @arg @ref LL_RCC_PLLM_DIV_44
-  *         @arg @ref LL_RCC_PLLM_DIV_45
-  *         @arg @ref LL_RCC_PLLM_DIV_46
-  *         @arg @ref LL_RCC_PLLM_DIV_47
-  *         @arg @ref LL_RCC_PLLM_DIV_48
-  *         @arg @ref LL_RCC_PLLM_DIV_49
-  *         @arg @ref LL_RCC_PLLM_DIV_50
-  *         @arg @ref LL_RCC_PLLM_DIV_51
-  *         @arg @ref LL_RCC_PLLM_DIV_52
-  *         @arg @ref LL_RCC_PLLM_DIV_53
-  *         @arg @ref LL_RCC_PLLM_DIV_54
-  *         @arg @ref LL_RCC_PLLM_DIV_55
-  *         @arg @ref LL_RCC_PLLM_DIV_56
-  *         @arg @ref LL_RCC_PLLM_DIV_57
-  *         @arg @ref LL_RCC_PLLM_DIV_58
-  *         @arg @ref LL_RCC_PLLM_DIV_59
-  *         @arg @ref LL_RCC_PLLM_DIV_60
-  *         @arg @ref LL_RCC_PLLM_DIV_61
-  *         @arg @ref LL_RCC_PLLM_DIV_62
-  *         @arg @ref LL_RCC_PLLM_DIV_63
-  * @param  __PLLN__ Between 50 and 432
-  * @param  __PLLR__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLR_DIV_2
-  *         @arg @ref LL_RCC_PLLR_DIV_3
-  *         @arg @ref LL_RCC_PLLR_DIV_4
-  *         @arg @ref LL_RCC_PLLR_DIV_5
-  *         @arg @ref LL_RCC_PLLR_DIV_6
-  *         @arg @ref LL_RCC_PLLR_DIV_7
-  * @retval PLL clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
-                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
-#endif /* SPDIFRX */
-
-#if defined(RCC_PLLCFGR_PLLR)
-#if defined(SAI1)
-/**
-  * @brief  Helper macro to calculate the PLLCLK frequency used on SAI
-  * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
-  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  *         @arg @ref LL_RCC_PLLM_DIV_9
-  *         @arg @ref LL_RCC_PLLM_DIV_10
-  *         @arg @ref LL_RCC_PLLM_DIV_11
-  *         @arg @ref LL_RCC_PLLM_DIV_12
-  *         @arg @ref LL_RCC_PLLM_DIV_13
-  *         @arg @ref LL_RCC_PLLM_DIV_14
-  *         @arg @ref LL_RCC_PLLM_DIV_15
-  *         @arg @ref LL_RCC_PLLM_DIV_16
-  *         @arg @ref LL_RCC_PLLM_DIV_17
-  *         @arg @ref LL_RCC_PLLM_DIV_18
-  *         @arg @ref LL_RCC_PLLM_DIV_19
-  *         @arg @ref LL_RCC_PLLM_DIV_20
-  *         @arg @ref LL_RCC_PLLM_DIV_21
-  *         @arg @ref LL_RCC_PLLM_DIV_22
-  *         @arg @ref LL_RCC_PLLM_DIV_23
-  *         @arg @ref LL_RCC_PLLM_DIV_24
-  *         @arg @ref LL_RCC_PLLM_DIV_25
-  *         @arg @ref LL_RCC_PLLM_DIV_26
-  *         @arg @ref LL_RCC_PLLM_DIV_27
-  *         @arg @ref LL_RCC_PLLM_DIV_28
-  *         @arg @ref LL_RCC_PLLM_DIV_29
-  *         @arg @ref LL_RCC_PLLM_DIV_30
-  *         @arg @ref LL_RCC_PLLM_DIV_31
-  *         @arg @ref LL_RCC_PLLM_DIV_32
-  *         @arg @ref LL_RCC_PLLM_DIV_33
-  *         @arg @ref LL_RCC_PLLM_DIV_34
-  *         @arg @ref LL_RCC_PLLM_DIV_35
-  *         @arg @ref LL_RCC_PLLM_DIV_36
-  *         @arg @ref LL_RCC_PLLM_DIV_37
-  *         @arg @ref LL_RCC_PLLM_DIV_38
-  *         @arg @ref LL_RCC_PLLM_DIV_39
-  *         @arg @ref LL_RCC_PLLM_DIV_40
-  *         @arg @ref LL_RCC_PLLM_DIV_41
-  *         @arg @ref LL_RCC_PLLM_DIV_42
-  *         @arg @ref LL_RCC_PLLM_DIV_43
-  *         @arg @ref LL_RCC_PLLM_DIV_44
-  *         @arg @ref LL_RCC_PLLM_DIV_45
-  *         @arg @ref LL_RCC_PLLM_DIV_46
-  *         @arg @ref LL_RCC_PLLM_DIV_47
-  *         @arg @ref LL_RCC_PLLM_DIV_48
-  *         @arg @ref LL_RCC_PLLM_DIV_49
-  *         @arg @ref LL_RCC_PLLM_DIV_50
-  *         @arg @ref LL_RCC_PLLM_DIV_51
-  *         @arg @ref LL_RCC_PLLM_DIV_52
-  *         @arg @ref LL_RCC_PLLM_DIV_53
-  *         @arg @ref LL_RCC_PLLM_DIV_54
-  *         @arg @ref LL_RCC_PLLM_DIV_55
-  *         @arg @ref LL_RCC_PLLM_DIV_56
-  *         @arg @ref LL_RCC_PLLM_DIV_57
-  *         @arg @ref LL_RCC_PLLM_DIV_58
-  *         @arg @ref LL_RCC_PLLM_DIV_59
-  *         @arg @ref LL_RCC_PLLM_DIV_60
-  *         @arg @ref LL_RCC_PLLM_DIV_61
-  *         @arg @ref LL_RCC_PLLM_DIV_62
-  *         @arg @ref LL_RCC_PLLM_DIV_63
-  * @param  __PLLN__ Between 50 and 432
-  * @param  __PLLR__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLR_DIV_2
-  *         @arg @ref LL_RCC_PLLR_DIV_3
-  *         @arg @ref LL_RCC_PLLR_DIV_4
-  *         @arg @ref LL_RCC_PLLR_DIV_5
-  *         @arg @ref LL_RCC_PLLR_DIV_6
-  *         @arg @ref LL_RCC_PLLR_DIV_7
-  * @param  __PLLDIVR__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval PLL clock frequency (in Hz)
-  */
-#if defined(RCC_DCKCFGR_PLLDIVR)
-#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
-                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))
-#else
-#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
-                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
-#endif /* RCC_DCKCFGR_PLLDIVR */
-#endif /* SAI1 */
-#endif /* RCC_PLLCFGR_PLLR */
-
-#if defined(RCC_PLLSAI_SUPPORT)
-/**
-  * @brief  Helper macro to calculate the PLLSAI frequency used for SAI domain
-  * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
-  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
-  * @param  __PLLSAIN__ Between 49/50(*) and 432
-  *
-  *         (*) value not defined in all devices.
-  * @param  __PLLSAIQ__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15
-  * @param  __PLLSAIDIVQ__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
-  * @retval PLLSAI clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
-                   (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))
-
-#if defined(RCC_PLLSAICFGR_PLLSAIP)
-/**
-  * @brief  Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
-  * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
-  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
-  * @param  __PLLSAIN__ Between 50 and 432
-  * @param  __PLLSAIP__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIP_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIP_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIP_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIP_DIV_8
-  * @retval PLLSAI clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
-                   ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U))
-#endif /* RCC_PLLSAICFGR_PLLSAIP */
-
-#if defined(LTDC)
-/**
-  * @brief  Helper macro to calculate the PLLSAI frequency used for LTDC domain
-  * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
-  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
-  * @param  __PLLSAIN__ Between 49/50(*) and 432
-  *
-  *         (*) value not defined in all devices.
-  * @param  __PLLSAIR__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_3
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_5
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_7
-  * @param  __PLLSAIDIVR__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
-  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
-  * @retval PLLSAI clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
-                   (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))
-#endif /* LTDC */
-#endif /* RCC_PLLSAI_SUPPORT */
-
-#if defined(RCC_PLLI2S_SUPPORT)
-#if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)
-/**
-  * @brief  Helper macro to calculate the PLLI2S frequency used for SAI domain
-  * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
-  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
-  * @param  __PLLI2SN__ Between 50/192(*) and 432
-  *
-  *         (*) value not defined in all devices.
-  * @param  __PLLI2SQ_R__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @param  __PLLI2SDIVQ_R__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval PLLI2S clock frequency (in Hz)
-  */
-#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
-#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
-                   (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))
-#else
-#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
-                   (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos)))
-
-#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
-#endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */
-
-#if defined(SPDIFRX)
-/**
-  * @brief  Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
-  * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
-  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
-  * @param  __PLLI2SN__ Between 50 and 432
-  * @param  __PLLI2SP__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SP_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SP_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SP_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SP_DIV_8
-  * @retval PLLI2S clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
-                   ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
-
-#endif /* SPDIFRX */
-
-/**
-  * @brief  Helper macro to calculate the PLLI2S frequency used for I2S domain
-  * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
-  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
-  * @param  __PLLI2SN__ Between 50/192(*) and 432
-  *
-  *         (*) value not defined in all devices.
-  * @param  __PLLI2SR__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_7
-  * @retval PLLI2S clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
-                   ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
-
-#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
-/**
-  * @brief  Helper macro to calculate the PLLI2S frequency used for 48Mhz domain
-  * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
-  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ());
-  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
-  * @param  __PLLM__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
-  * @param  __PLLI2SN__ Between 50 and 432
-  * @param  __PLLI2SQ__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
-  * @retval PLLI2S clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
-                   ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos))
-
-#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
-#endif /* RCC_PLLI2S_SUPPORT */
-
-/**
-  * @brief  Helper macro to calculate the HCLK frequency
-  * @param  __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
-  * @param  __AHBPRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SYSCLK_DIV_1
-  *         @arg @ref LL_RCC_SYSCLK_DIV_2
-  *         @arg @ref LL_RCC_SYSCLK_DIV_4
-  *         @arg @ref LL_RCC_SYSCLK_DIV_8
-  *         @arg @ref LL_RCC_SYSCLK_DIV_16
-  *         @arg @ref LL_RCC_SYSCLK_DIV_64
-  *         @arg @ref LL_RCC_SYSCLK_DIV_128
-  *         @arg @ref LL_RCC_SYSCLK_DIV_256
-  *         @arg @ref LL_RCC_SYSCLK_DIV_512
-  * @retval HCLK clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])
-
-/**
-  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
-  * @param  __HCLKFREQ__ HCLK frequency
-  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB1_DIV_1
-  *         @arg @ref LL_RCC_APB1_DIV_2
-  *         @arg @ref LL_RCC_APB1_DIV_4
-  *         @arg @ref LL_RCC_APB1_DIV_8
-  *         @arg @ref LL_RCC_APB1_DIV_16
-  * @retval PCLK1 clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos])
-
-/**
-  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
-  * @param  __HCLKFREQ__ HCLK frequency
-  * @param  __APB2PRESCALER__ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB2_DIV_1
-  *         @arg @ref LL_RCC_APB2_DIV_2
-  *         @arg @ref LL_RCC_APB2_DIV_4
-  *         @arg @ref LL_RCC_APB2_DIV_8
-  *         @arg @ref LL_RCC_APB2_DIV_16
-  * @retval PCLK2 clock frequency (in Hz)
-  */
-#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos])
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
-  * @{
-  */
-
-/** @defgroup RCC_LL_EF_HSE HSE
-  * @{
-  */
-
-/**
-  * @brief  Enable the Clock Security System.
-  * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_CSSON);
-}
-
-/**
-  * @brief  Enable HSE external oscillator (HSE Bypass)
-  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
-  * @brief  Disable HSE external oscillator (HSE Bypass)
-  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-}
-
-/**
-  * @brief  Enable HSE crystal oscillator (HSE ON)
-  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
-  * @brief  Disable HSE crystal oscillator (HSE ON)
-  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSE_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
-}
-
-/**
-  * @brief  Check if HSE oscillator Ready
-  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
-{
-  return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_HSI HSI
-  * @{
-  */
-
-/**
-  * @brief  Enable HSI oscillator
-  * @rmtoll CR           HSION         LL_RCC_HSI_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
-  * @brief  Disable HSI oscillator
-  * @rmtoll CR           HSION         LL_RCC_HSI_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
-}
-
-/**
-  * @brief  Check if HSI clock is ready
-  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
-{
-  return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
-}
-
-/**
-  * @brief  Get HSI Calibration value
-  * @note When HSITRIM is written, HSICAL is updated with the sum of
-  *       HSITRIM and the factory trim value
-  * @rmtoll CR        HSICAL        LL_RCC_HSI_GetCalibration
-  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
-}
-
-/**
-  * @brief  Set HSI Calibration trimming
-  * @note user-programmable trimming value that is added to the HSICAL
-  * @note Default value is 16, which, when added to the HSICAL value,
-  *       should trim the HSI to 16 MHz +/- 1 %
-  * @rmtoll CR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
-  * @param  Value Between Min_Data = 0 and Max_Data = 31
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
-{
-  MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
-}
-
-/**
-  * @brief  Get HSI Calibration trimming
-  * @rmtoll CR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
-  * @retval Between Min_Data = 0 and Max_Data = 31
-  */
-__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_LSE LSE
-  * @{
-  */
-
-/**
-  * @brief  Enable  Low Speed External (LSE) crystal.
-  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_Enable(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
-}
-
-/**
-  * @brief  Disable  Low Speed External (LSE) crystal.
-  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_Disable(void)
-{
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
-}
-
-/**
-  * @brief  Enable external clock source (LSE bypass).
-  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
-}
-
-/**
-  * @brief  Disable external clock source (LSE bypass).
-  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
-{
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
-}
-
-/**
-  * @brief  Check if LSE oscillator Ready
-  * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
-{
-  return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
-}
-
-#if defined(RCC_BDCR_LSEMOD)
-/**
-  * @brief  Enable LSE high drive mode.
-  * @note LSE high drive mode can be enabled only when the LSE clock is disabled
-  * @rmtoll BDCR         LSEMOD      LL_RCC_LSE_EnableHighDriveMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
-}
-
-/**
-  * @brief  Disable LSE high drive mode.
-  * @note LSE high drive mode can be disabled only when the LSE clock is disabled
-  * @rmtoll BDCR         LSEMOD      LL_RCC_LSE_DisableHighDriveMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void)
-{
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
-}
-#endif /* RCC_BDCR_LSEMOD */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_LSI LSI
-  * @{
-  */
-
-/**
-  * @brief  Enable LSI Oscillator
-  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSI_Enable(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
-  * @brief  Disable LSI Oscillator
-  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_LSI_Disable(void)
-{
-  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
-}
-
-/**
-  * @brief  Check if LSI is Ready
-  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
-{
-  return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_System System
-  * @{
-  */
-
-/**
-  * @brief  Configure the system clock source
-  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
-}
-
-/**
-  * @brief  Get the system clock source
-  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
-  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*)
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
-}
-
-/**
-  * @brief  Set AHB prescaler
-  * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SYSCLK_DIV_1
-  *         @arg @ref LL_RCC_SYSCLK_DIV_2
-  *         @arg @ref LL_RCC_SYSCLK_DIV_4
-  *         @arg @ref LL_RCC_SYSCLK_DIV_8
-  *         @arg @ref LL_RCC_SYSCLK_DIV_16
-  *         @arg @ref LL_RCC_SYSCLK_DIV_64
-  *         @arg @ref LL_RCC_SYSCLK_DIV_128
-  *         @arg @ref LL_RCC_SYSCLK_DIV_256
-  *         @arg @ref LL_RCC_SYSCLK_DIV_512
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
-}
-
-/**
-  * @brief  Set APB1 prescaler
-  * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB1_DIV_1
-  *         @arg @ref LL_RCC_APB1_DIV_2
-  *         @arg @ref LL_RCC_APB1_DIV_4
-  *         @arg @ref LL_RCC_APB1_DIV_8
-  *         @arg @ref LL_RCC_APB1_DIV_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
-}
-
-/**
-  * @brief  Set APB2 prescaler
-  * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_APB2_DIV_1
-  *         @arg @ref LL_RCC_APB2_DIV_2
-  *         @arg @ref LL_RCC_APB2_DIV_4
-  *         @arg @ref LL_RCC_APB2_DIV_8
-  *         @arg @ref LL_RCC_APB2_DIV_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
-}
-
-/**
-  * @brief  Get AHB prescaler
-  * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SYSCLK_DIV_1
-  *         @arg @ref LL_RCC_SYSCLK_DIV_2
-  *         @arg @ref LL_RCC_SYSCLK_DIV_4
-  *         @arg @ref LL_RCC_SYSCLK_DIV_8
-  *         @arg @ref LL_RCC_SYSCLK_DIV_16
-  *         @arg @ref LL_RCC_SYSCLK_DIV_64
-  *         @arg @ref LL_RCC_SYSCLK_DIV_128
-  *         @arg @ref LL_RCC_SYSCLK_DIV_256
-  *         @arg @ref LL_RCC_SYSCLK_DIV_512
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
-}
-
-/**
-  * @brief  Get APB1 prescaler
-  * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_APB1_DIV_1
-  *         @arg @ref LL_RCC_APB1_DIV_2
-  *         @arg @ref LL_RCC_APB1_DIV_4
-  *         @arg @ref LL_RCC_APB1_DIV_8
-  *         @arg @ref LL_RCC_APB1_DIV_16
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
-}
-
-/**
-  * @brief  Get APB2 prescaler
-  * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_APB2_DIV_1
-  *         @arg @ref LL_RCC_APB2_DIV_2
-  *         @arg @ref LL_RCC_APB2_DIV_4
-  *         @arg @ref LL_RCC_APB2_DIV_8
-  *         @arg @ref LL_RCC_APB2_DIV_16
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_MCO MCO
-  * @{
-  */
-
-#if defined(RCC_CFGR_MCO1EN)
-/**
-  * @brief  Enable MCO1 output
-  * @rmtoll CFGR           RCC_CFGR_MCO1EN         LL_RCC_MCO1_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_MCO1_Enable(void)
-{
-  SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
-}
-
-/**
-  * @brief  Disable MCO1 output
-  * @rmtoll CFGR           RCC_CFGR_MCO1EN         LL_RCC_MCO1_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_MCO1_Disable(void)
-{
-  CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
-}
-#endif /* RCC_CFGR_MCO1EN */
-
-#if defined(RCC_CFGR_MCO2EN)
-/**
-  * @brief  Enable MCO2 output
-  * @rmtoll CFGR           RCC_CFGR_MCO2EN         LL_RCC_MCO2_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_MCO2_Enable(void)
-{
-  SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
-}
-
-/**
-  * @brief  Disable MCO2 output
-  * @rmtoll CFGR           RCC_CFGR_MCO2EN         LL_RCC_MCO2_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_MCO2_Disable(void)
-{
-  CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
-}
-#endif /* RCC_CFGR_MCO2EN */
-
-/**
-  * @brief  Configure MCOx
-  * @rmtoll CFGR         MCO1          LL_RCC_ConfigMCO\n
-  *         CFGR         MCO1PRE       LL_RCC_ConfigMCO\n
-  *         CFGR         MCO2          LL_RCC_ConfigMCO\n
-  *         CFGR         MCO2PRE       LL_RCC_ConfigMCO
-  * @param  MCOxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
-  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
-  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
-  *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
-  *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
-  *         @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
-  *         @arg @ref LL_RCC_MCO2SOURCE_HSE
-  *         @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
-  * @param  MCOxPrescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_MCO1_DIV_1
-  *         @arg @ref LL_RCC_MCO1_DIV_2
-  *         @arg @ref LL_RCC_MCO1_DIV_3
-  *         @arg @ref LL_RCC_MCO1_DIV_4
-  *         @arg @ref LL_RCC_MCO1_DIV_5
-  *         @arg @ref LL_RCC_MCO2_DIV_1
-  *         @arg @ref LL_RCC_MCO2_DIV_2
-  *         @arg @ref LL_RCC_MCO2_DIV_3
-  *         @arg @ref LL_RCC_MCO2_DIV_4
-  *         @arg @ref LL_RCC_MCO2_DIV_5
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
-{
-  MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U),  (MCOxSource << 16U) | (MCOxPrescaler << 16U));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
-  * @{
-  */
-#if defined(FMPI2C1)
-/**
-  * @brief  Configure FMPI2C clock source
-  * @rmtoll DCKCFGR2        FMPI2C1SEL       LL_RCC_SetFMPI2CClockSource
-  * @param  FMPI2CxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)
-{
-  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource);
-}
-#endif /* FMPI2C1 */
-
-#if defined(LPTIM1)
-/**
-  * @brief  Configure LPTIMx clock source
-  * @rmtoll DCKCFGR2        LPTIM1SEL     LL_RCC_SetLPTIMClockSource
-  * @param  LPTIMxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
-{
-  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
-}
-#endif /* LPTIM1 */
-
-#if defined(SAI1)
-/**
-  * @brief  Configure SAIx clock source
-  * @rmtoll DCKCFGR        SAI1SRC       LL_RCC_SetSAIClockSource\n
-  *         DCKCFGR        SAI2SRC       LL_RCC_SetSAIClockSource\n
-  *         DCKCFGR        SAI1ASRC      LL_RCC_SetSAIClockSource\n
-  *         DCKCFGR        SAI1BSRC      LL_RCC_SetSAIClockSource
-  * @param  SAIxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
-  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
-  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
-  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL  (*)
-  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
-  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
-  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
-  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
-  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
-  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
-  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
-  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
-  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
-  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL  (*)
-  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
-{
-  MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
-}
-#endif /* SAI1 */
-
-#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
-/**
-  * @brief  Configure SDIO clock source
-  * @rmtoll DCKCFGR         SDIOSEL      LL_RCC_SetSDIOClockSource\n
-  *         DCKCFGR2        SDIOSEL      LL_RCC_SetSDIOClockSource
-  * @param  SDIOxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
-  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)
-{
-#if defined(RCC_DCKCFGR_SDIOSEL)
-  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource);
-#else
-  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource);
-#endif /* RCC_DCKCFGR_SDIOSEL */
-}
-#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
-
-#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
-/**
-  * @brief  Configure 48Mhz domain clock source
-  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_SetCK48MClockSource\n
-  *         DCKCFGR2        CK48MSEL      LL_RCC_SetCK48MClockSource
-  * @param  CK48MxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
-  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
-{
-#if defined(RCC_DCKCFGR_CK48MSEL)
-  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource);
-#else
-  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
-#endif /* RCC_DCKCFGR_CK48MSEL */
-}
-
-#if defined(RNG)
-/**
-  * @brief  Configure RNG clock source
-  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_SetRNGClockSource\n
-  *         DCKCFGR2        CK48MSEL      LL_RCC_SetRNGClockSource
-  * @param  RNGxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
-{
-#if defined(RCC_DCKCFGR_CK48MSEL)
-  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource);
-#else
-  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
-#endif /* RCC_DCKCFGR_CK48MSEL */
-}
-#endif /* RNG */
-
-#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
-/**
-  * @brief  Configure USB clock source
-  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_SetUSBClockSource\n
-  *         DCKCFGR2        CK48MSEL      LL_RCC_SetUSBClockSource
-  * @param  USBxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
-{
-#if defined(RCC_DCKCFGR_CK48MSEL)
-  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource);
-#else
-  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
-#endif /* RCC_DCKCFGR_CK48MSEL */
-}
-#endif /* USB_OTG_FS || USB_OTG_HS */
-#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
-
-#if defined(CEC)
-/**
-  * @brief  Configure CEC clock source
-  * @rmtoll DCKCFGR2         CECSEL        LL_RCC_SetCECClockSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
-}
-#endif /* CEC */
-
-/**
-  * @brief  Configure I2S clock source
-  * @rmtoll CFGR         I2SSRC        LL_RCC_SetI2SClockSource\n
-  *         DCKCFGR      I2SSRC        LL_RCC_SetI2SClockSource\n
-  *         DCKCFGR      I2S1SRC       LL_RCC_SetI2SClockSource\n
-  *         DCKCFGR      I2S2SRC       LL_RCC_SetI2SClockSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
-{
-#if defined(RCC_CFGR_I2SSRC)
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
-#else
-  MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U));
-#endif /* RCC_CFGR_I2SSRC */
-}
-
-#if defined(DSI)
-/**
-  * @brief  Configure DSI clock source
-  * @rmtoll DCKCFGR         DSISEL        LL_RCC_SetDSIClockSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
-  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source);
-}
-#endif /* DSI */
-
-#if defined(DFSDM1_Channel0)
-/**
-  * @brief  Configure DFSDM Audio clock source
-  * @rmtoll DCKCFGR          CKDFSDM1ASEL        LL_RCC_SetDFSDMAudioClockSource\n
-  *         DCKCFGR          CKDFSDM2ASEL        LL_RCC_SetDFSDMAudioClockSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
-  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
-  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
-  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U));
-}
-
-/**
-  * @brief  Configure DFSDM Kernel clock source
-  * @rmtoll DCKCFGR         CKDFSDM1SEL        LL_RCC_SetDFSDMClockSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
-  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
-  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source);
-}
-#endif /* DFSDM1_Channel0 */
-
-#if defined(SPDIFRX)
-/**
-  * @brief  Configure SPDIFRX clock source
-  * @rmtoll DCKCFGR2         SPDIFRXSEL      LL_RCC_SetSPDIFRXClockSource
-  * @param  SPDIFRXxSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)
-{
-  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource);
-}
-#endif /* SPDIFRX */
-
-#if defined(FMPI2C1)
-/**
-  * @brief  Get FMPI2C clock source
-  * @rmtoll DCKCFGR2        FMPI2C1SEL       LL_RCC_GetFMPI2CClockSource
-  * @param  FMPI2Cx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
- */
-__STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)
-{
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx));
-}
-#endif /* FMPI2C1 */
-
-#if defined(LPTIM1)
-/**
-  * @brief  Get LPTIMx clock source
-  * @rmtoll DCKCFGR2        LPTIM1SEL     LL_RCC_GetLPTIMClockSource
-  * @param  LPTIMx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
-{
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
-}
-#endif /* LPTIM1 */
-
-#if defined(SAI1)
-/**
-  * @brief  Get SAIx clock source
-  * @rmtoll DCKCFGR         SAI1SEL       LL_RCC_GetSAIClockSource\n
-  *         DCKCFGR         SAI2SEL       LL_RCC_GetSAIClockSource\n
-  *         DCKCFGR         SAI1ASRC      LL_RCC_GetSAIClockSource\n
-  *         DCKCFGR         SAI1BSRC      LL_RCC_GetSAIClockSource
-  * @param  SAIx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
-  *         @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
-  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
-  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
-  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
-  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
-  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
-  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL  (*)
-  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
-  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
-  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
-  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
-  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
-  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
-  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
-  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
-  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
-  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL  (*)
-  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
-{
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx);
-}
-#endif /* SAI1 */
-
-#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
-/**
-  * @brief  Get SDIOx clock source
-  * @rmtoll DCKCFGR        SDIOSEL      LL_RCC_GetSDIOClockSource\n
-  *         DCKCFGR2       SDIOSEL      LL_RCC_GetSDIOClockSource
-  * @param  SDIOx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SDIO_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
-  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx)
-{
-#if defined(RCC_DCKCFGR_SDIOSEL)
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx));
-#else
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx));
-#endif /* RCC_DCKCFGR_SDIOSEL */
-}
-#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
-
-#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
-/**
-  * @brief  Get 48Mhz domain clock source
-  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_GetCK48MClockSource\n
-  *         DCKCFGR2        CK48MSEL      LL_RCC_GetCK48MClockSource
-  * @param  CK48Mx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_CK48M_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
-  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
-{
-#if defined(RCC_DCKCFGR_CK48MSEL)
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx));
-#else
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
-#endif /* RCC_DCKCFGR_CK48MSEL */
-}
-
-#if defined(RNG)
-/**
-  * @brief  Get RNGx clock source
-  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_GetRNGClockSource\n
-  *         DCKCFGR2        CK48MSEL      LL_RCC_GetRNGClockSource
-  * @param  RNGx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
-  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
-{
-#if defined(RCC_DCKCFGR_CK48MSEL)
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx));
-#else
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
-#endif /* RCC_DCKCFGR_CK48MSEL */
-}
-#endif /* RNG */
-
-#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
-/**
-  * @brief  Get USBx clock source
-  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_GetUSBClockSource\n
-  *         DCKCFGR2        CK48MSEL      LL_RCC_GetUSBClockSource
-  * @param  USBx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_USB_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
-  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
-{
-#if defined(RCC_DCKCFGR_CK48MSEL)
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx));
-#else
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
-#endif /* RCC_DCKCFGR_CK48MSEL */
-}
-#endif /* USB_OTG_FS || USB_OTG_HS */
-#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
-
-#if defined(CEC)
-/**
-  * @brief  Get CEC Clock Source
-  * @rmtoll DCKCFGR2         CECSEL        LL_RCC_GetCECClockSource
-  * @param  CECx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
-  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
-{
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
-}
-#endif /* CEC */
-
-/**
-  * @brief  Get I2S Clock Source
-  * @rmtoll CFGR         I2SSRC        LL_RCC_GetI2SClockSource\n
-  *         DCKCFGR      I2SSRC        LL_RCC_GetI2SClockSource\n
-  *         DCKCFGR      I2S1SRC       LL_RCC_GetI2SClockSource\n
-  *         DCKCFGR      I2S2SRC       LL_RCC_GetI2SClockSource
-  * @param  I2Sx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
-  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
-  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
-{
-#if defined(RCC_CFGR_I2SSRC)
-  return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
-#else
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx);
-#endif /* RCC_CFGR_I2SSRC */
-}
-
-#if defined(DFSDM1_Channel0)
-/**
-  * @brief  Get DFSDM Audio Clock Source
-  * @rmtoll DCKCFGR          CKDFSDM1ASEL        LL_RCC_GetDFSDMAudioClockSource\n
-  *         DCKCFGR          CKDFSDM2ASEL        LL_RCC_GetDFSDMAudioClockSource
-  * @param  DFSDMx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
-  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
-  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
-  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
-  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
-{
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx);
-}
-
-/**
-  * @brief  Get DFSDM Audio Clock Source
-  * @rmtoll DCKCFGR         CKDFSDM1SEL        LL_RCC_GetDFSDMClockSource
-  * @param  DFSDMx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
-  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
-  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
-  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
-  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
-{
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx));
-}
-#endif /* DFSDM1_Channel0 */
-
-#if defined(SPDIFRX)
-/**
-  * @brief  Get SPDIFRX clock source
-  * @rmtoll DCKCFGR2         SPDIFRXSEL      LL_RCC_GetSPDIFRXClockSource
-  * @param  SPDIFRXx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
-  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)
-{
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx));
-}
-#endif /* SPDIFRX */
-
-#if defined(DSI)
-/**
-  * @brief  Get DSI Clock Source
-  * @rmtoll DCKCFGR         DSISEL        LL_RCC_GetDSIClockSource
-  * @param  DSIx This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_DSI_CLKSOURCE
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
-  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
-{
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx));
-}
-#endif /* DSI */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_RTC RTC
-  * @{
-  */
-
-/**
-  * @brief  Set RTC Clock Source
-  * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
-  *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
-  *       set). The BDRST bit can be used to reset them.
-  * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
-{
-  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
-}
-
-/**
-  * @brief  Get RTC Clock Source
-  * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
-  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
-}
-
-/**
-  * @brief  Enable RTC
-  * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableRTC(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
-}
-
-/**
-  * @brief  Disable RTC
-  * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableRTC(void)
-{
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
-}
-
-/**
-  * @brief  Check if RTC has been enabled or not
-  * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
-{
-  return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
-}
-
-/**
-  * @brief  Force the Backup domain reset
-  * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
-{
-  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
-}
-
-/**
-  * @brief  Release the Backup domain reset
-  * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
-{
-  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
-}
-
-/**
-  * @brief  Set HSE Prescalers for RTC Clock
-  * @rmtoll CFGR         RTCPRE        LL_RCC_SetRTC_HSEPrescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_NOCLOCK
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
-{
-  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
-}
-
-/**
-  * @brief  Get HSE Prescalers for RTC Clock
-  * @rmtoll CFGR         RTCPRE        LL_RCC_GetRTC_HSEPrescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_RTC_NOCLOCK
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
-  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
-}
-
-/**
-  * @}
-  */
-
-#if defined(RCC_DCKCFGR_TIMPRE)
-/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
-  * @{
-  */
-
-/**
-  * @brief  Set Timers Clock Prescalers
-  * @rmtoll DCKCFGR         TIMPRE        LL_RCC_SetTIMPrescaler
-  * @param  Prescaler This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
-  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
-{
-  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler);
-}
-
-/**
-  * @brief  Get Timers Clock Prescalers
-  * @rmtoll DCKCFGR         TIMPRE        LL_RCC_GetTIMPrescaler
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
-  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
-  */
-__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
-{
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE));
-}
-
-/**
-  * @}
-  */
-#endif /* RCC_DCKCFGR_TIMPRE */
-
-/** @defgroup RCC_LL_EF_PLL PLL
-  * @{
-  */
-
-/**
-  * @brief  Enable PLL
-  * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
-  * @brief  Disable PLL
-  * @note Cannot be disabled if the PLL clock is used as the system clock
-  * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
-}
-
-/**
-  * @brief  Check if PLL Ready
-  * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
-{
-  return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
-}
-
-/**
-  * @brief  Configure PLL used for SYSCLK Domain
-  * @note PLL Source and PLLM Divider can be written only when PLL,
-  *       PLLI2S and PLLSAI(*) are disabled
-  * @note PLLN/PLLP can be written only when PLL is disabled
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
-  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\n
-  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\n
-  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SYS\n
-  *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_SYS
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  *         @arg @ref LL_RCC_PLLM_DIV_9
-  *         @arg @ref LL_RCC_PLLM_DIV_10
-  *         @arg @ref LL_RCC_PLLM_DIV_11
-  *         @arg @ref LL_RCC_PLLM_DIV_12
-  *         @arg @ref LL_RCC_PLLM_DIV_13
-  *         @arg @ref LL_RCC_PLLM_DIV_14
-  *         @arg @ref LL_RCC_PLLM_DIV_15
-  *         @arg @ref LL_RCC_PLLM_DIV_16
-  *         @arg @ref LL_RCC_PLLM_DIV_17
-  *         @arg @ref LL_RCC_PLLM_DIV_18
-  *         @arg @ref LL_RCC_PLLM_DIV_19
-  *         @arg @ref LL_RCC_PLLM_DIV_20
-  *         @arg @ref LL_RCC_PLLM_DIV_21
-  *         @arg @ref LL_RCC_PLLM_DIV_22
-  *         @arg @ref LL_RCC_PLLM_DIV_23
-  *         @arg @ref LL_RCC_PLLM_DIV_24
-  *         @arg @ref LL_RCC_PLLM_DIV_25
-  *         @arg @ref LL_RCC_PLLM_DIV_26
-  *         @arg @ref LL_RCC_PLLM_DIV_27
-  *         @arg @ref LL_RCC_PLLM_DIV_28
-  *         @arg @ref LL_RCC_PLLM_DIV_29
-  *         @arg @ref LL_RCC_PLLM_DIV_30
-  *         @arg @ref LL_RCC_PLLM_DIV_31
-  *         @arg @ref LL_RCC_PLLM_DIV_32
-  *         @arg @ref LL_RCC_PLLM_DIV_33
-  *         @arg @ref LL_RCC_PLLM_DIV_34
-  *         @arg @ref LL_RCC_PLLM_DIV_35
-  *         @arg @ref LL_RCC_PLLM_DIV_36
-  *         @arg @ref LL_RCC_PLLM_DIV_37
-  *         @arg @ref LL_RCC_PLLM_DIV_38
-  *         @arg @ref LL_RCC_PLLM_DIV_39
-  *         @arg @ref LL_RCC_PLLM_DIV_40
-  *         @arg @ref LL_RCC_PLLM_DIV_41
-  *         @arg @ref LL_RCC_PLLM_DIV_42
-  *         @arg @ref LL_RCC_PLLM_DIV_43
-  *         @arg @ref LL_RCC_PLLM_DIV_44
-  *         @arg @ref LL_RCC_PLLM_DIV_45
-  *         @arg @ref LL_RCC_PLLM_DIV_46
-  *         @arg @ref LL_RCC_PLLM_DIV_47
-  *         @arg @ref LL_RCC_PLLM_DIV_48
-  *         @arg @ref LL_RCC_PLLM_DIV_49
-  *         @arg @ref LL_RCC_PLLM_DIV_50
-  *         @arg @ref LL_RCC_PLLM_DIV_51
-  *         @arg @ref LL_RCC_PLLM_DIV_52
-  *         @arg @ref LL_RCC_PLLM_DIV_53
-  *         @arg @ref LL_RCC_PLLM_DIV_54
-  *         @arg @ref LL_RCC_PLLM_DIV_55
-  *         @arg @ref LL_RCC_PLLM_DIV_56
-  *         @arg @ref LL_RCC_PLLM_DIV_57
-  *         @arg @ref LL_RCC_PLLM_DIV_58
-  *         @arg @ref LL_RCC_PLLM_DIV_59
-  *         @arg @ref LL_RCC_PLLM_DIV_60
-  *         @arg @ref LL_RCC_PLLM_DIV_61
-  *         @arg @ref LL_RCC_PLLM_DIV_62
-  *         @arg @ref LL_RCC_PLLM_DIV_63
-  * @param  PLLN Between 50/192(*) and 432
-  *
-  *         (*) value not defined in all devices.
-  * @param  PLLP_R This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLP_DIV_2
-  *         @arg @ref LL_RCC_PLLP_DIV_4
-  *         @arg @ref LL_RCC_PLLP_DIV_6
-  *         @arg @ref LL_RCC_PLLP_DIV_8
-  *         @arg @ref LL_RCC_PLLR_DIV_2 (*)
-  *         @arg @ref LL_RCC_PLLR_DIV_3 (*)
-  *         @arg @ref LL_RCC_PLLR_DIV_4 (*)
-  *         @arg @ref LL_RCC_PLLR_DIV_5 (*)
-  *         @arg @ref LL_RCC_PLLR_DIV_6 (*)
-  *         @arg @ref LL_RCC_PLLR_DIV_7 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN,
-             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos);
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R);
-#if defined(RCC_PLLR_SYSCLK_SUPPORT)
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R);
-#endif /* RCC_PLLR_SYSCLK_SUPPORT */
-}
-
-/**
-  * @brief  Configure PLL used for 48Mhz domain clock
-  * @note PLL Source and PLLM Divider can be written only when PLL,
-  *       PLLI2S and PLLSAI(*) are disabled
-  * @note PLLN/PLLQ can be written only when PLL is disabled
-  * @note This  can be selected for USB, RNG, SDIO
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_48M\n
-  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_48M\n
-  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_48M\n
-  *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_48M
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  *         @arg @ref LL_RCC_PLLM_DIV_9
-  *         @arg @ref LL_RCC_PLLM_DIV_10
-  *         @arg @ref LL_RCC_PLLM_DIV_11
-  *         @arg @ref LL_RCC_PLLM_DIV_12
-  *         @arg @ref LL_RCC_PLLM_DIV_13
-  *         @arg @ref LL_RCC_PLLM_DIV_14
-  *         @arg @ref LL_RCC_PLLM_DIV_15
-  *         @arg @ref LL_RCC_PLLM_DIV_16
-  *         @arg @ref LL_RCC_PLLM_DIV_17
-  *         @arg @ref LL_RCC_PLLM_DIV_18
-  *         @arg @ref LL_RCC_PLLM_DIV_19
-  *         @arg @ref LL_RCC_PLLM_DIV_20
-  *         @arg @ref LL_RCC_PLLM_DIV_21
-  *         @arg @ref LL_RCC_PLLM_DIV_22
-  *         @arg @ref LL_RCC_PLLM_DIV_23
-  *         @arg @ref LL_RCC_PLLM_DIV_24
-  *         @arg @ref LL_RCC_PLLM_DIV_25
-  *         @arg @ref LL_RCC_PLLM_DIV_26
-  *         @arg @ref LL_RCC_PLLM_DIV_27
-  *         @arg @ref LL_RCC_PLLM_DIV_28
-  *         @arg @ref LL_RCC_PLLM_DIV_29
-  *         @arg @ref LL_RCC_PLLM_DIV_30
-  *         @arg @ref LL_RCC_PLLM_DIV_31
-  *         @arg @ref LL_RCC_PLLM_DIV_32
-  *         @arg @ref LL_RCC_PLLM_DIV_33
-  *         @arg @ref LL_RCC_PLLM_DIV_34
-  *         @arg @ref LL_RCC_PLLM_DIV_35
-  *         @arg @ref LL_RCC_PLLM_DIV_36
-  *         @arg @ref LL_RCC_PLLM_DIV_37
-  *         @arg @ref LL_RCC_PLLM_DIV_38
-  *         @arg @ref LL_RCC_PLLM_DIV_39
-  *         @arg @ref LL_RCC_PLLM_DIV_40
-  *         @arg @ref LL_RCC_PLLM_DIV_41
-  *         @arg @ref LL_RCC_PLLM_DIV_42
-  *         @arg @ref LL_RCC_PLLM_DIV_43
-  *         @arg @ref LL_RCC_PLLM_DIV_44
-  *         @arg @ref LL_RCC_PLLM_DIV_45
-  *         @arg @ref LL_RCC_PLLM_DIV_46
-  *         @arg @ref LL_RCC_PLLM_DIV_47
-  *         @arg @ref LL_RCC_PLLM_DIV_48
-  *         @arg @ref LL_RCC_PLLM_DIV_49
-  *         @arg @ref LL_RCC_PLLM_DIV_50
-  *         @arg @ref LL_RCC_PLLM_DIV_51
-  *         @arg @ref LL_RCC_PLLM_DIV_52
-  *         @arg @ref LL_RCC_PLLM_DIV_53
-  *         @arg @ref LL_RCC_PLLM_DIV_54
-  *         @arg @ref LL_RCC_PLLM_DIV_55
-  *         @arg @ref LL_RCC_PLLM_DIV_56
-  *         @arg @ref LL_RCC_PLLM_DIV_57
-  *         @arg @ref LL_RCC_PLLM_DIV_58
-  *         @arg @ref LL_RCC_PLLM_DIV_59
-  *         @arg @ref LL_RCC_PLLM_DIV_60
-  *         @arg @ref LL_RCC_PLLM_DIV_61
-  *         @arg @ref LL_RCC_PLLM_DIV_62
-  *         @arg @ref LL_RCC_PLLM_DIV_63
-  * @param  PLLN Between 50/192(*) and 432
-  *
-  *         (*) value not defined in all devices.
-  * @param  PLLQ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLQ_DIV_2
-  *         @arg @ref LL_RCC_PLLQ_DIV_3
-  *         @arg @ref LL_RCC_PLLQ_DIV_4
-  *         @arg @ref LL_RCC_PLLQ_DIV_5
-  *         @arg @ref LL_RCC_PLLQ_DIV_6
-  *         @arg @ref LL_RCC_PLLQ_DIV_7
-  *         @arg @ref LL_RCC_PLLQ_DIV_8
-  *         @arg @ref LL_RCC_PLLQ_DIV_9
-  *         @arg @ref LL_RCC_PLLQ_DIV_10
-  *         @arg @ref LL_RCC_PLLQ_DIV_11
-  *         @arg @ref LL_RCC_PLLQ_DIV_12
-  *         @arg @ref LL_RCC_PLLQ_DIV_13
-  *         @arg @ref LL_RCC_PLLQ_DIV_14
-  *         @arg @ref LL_RCC_PLLQ_DIV_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
-             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
-}
-
-#if defined(DSI)
-/**
-  * @brief  Configure PLL used for DSI clock
-  * @note PLL Source and PLLM Divider can be written only when PLL,
-  *       PLLI2S and PLLSAI are disabled
-  * @note PLLN/PLLR can be written only when PLL is disabled
-  * @note This  can be selected for DSI
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_DSI\n
-  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_DSI\n
-  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_DSI\n
-  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_DSI
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  *         @arg @ref LL_RCC_PLLM_DIV_9
-  *         @arg @ref LL_RCC_PLLM_DIV_10
-  *         @arg @ref LL_RCC_PLLM_DIV_11
-  *         @arg @ref LL_RCC_PLLM_DIV_12
-  *         @arg @ref LL_RCC_PLLM_DIV_13
-  *         @arg @ref LL_RCC_PLLM_DIV_14
-  *         @arg @ref LL_RCC_PLLM_DIV_15
-  *         @arg @ref LL_RCC_PLLM_DIV_16
-  *         @arg @ref LL_RCC_PLLM_DIV_17
-  *         @arg @ref LL_RCC_PLLM_DIV_18
-  *         @arg @ref LL_RCC_PLLM_DIV_19
-  *         @arg @ref LL_RCC_PLLM_DIV_20
-  *         @arg @ref LL_RCC_PLLM_DIV_21
-  *         @arg @ref LL_RCC_PLLM_DIV_22
-  *         @arg @ref LL_RCC_PLLM_DIV_23
-  *         @arg @ref LL_RCC_PLLM_DIV_24
-  *         @arg @ref LL_RCC_PLLM_DIV_25
-  *         @arg @ref LL_RCC_PLLM_DIV_26
-  *         @arg @ref LL_RCC_PLLM_DIV_27
-  *         @arg @ref LL_RCC_PLLM_DIV_28
-  *         @arg @ref LL_RCC_PLLM_DIV_29
-  *         @arg @ref LL_RCC_PLLM_DIV_30
-  *         @arg @ref LL_RCC_PLLM_DIV_31
-  *         @arg @ref LL_RCC_PLLM_DIV_32
-  *         @arg @ref LL_RCC_PLLM_DIV_33
-  *         @arg @ref LL_RCC_PLLM_DIV_34
-  *         @arg @ref LL_RCC_PLLM_DIV_35
-  *         @arg @ref LL_RCC_PLLM_DIV_36
-  *         @arg @ref LL_RCC_PLLM_DIV_37
-  *         @arg @ref LL_RCC_PLLM_DIV_38
-  *         @arg @ref LL_RCC_PLLM_DIV_39
-  *         @arg @ref LL_RCC_PLLM_DIV_40
-  *         @arg @ref LL_RCC_PLLM_DIV_41
-  *         @arg @ref LL_RCC_PLLM_DIV_42
-  *         @arg @ref LL_RCC_PLLM_DIV_43
-  *         @arg @ref LL_RCC_PLLM_DIV_44
-  *         @arg @ref LL_RCC_PLLM_DIV_45
-  *         @arg @ref LL_RCC_PLLM_DIV_46
-  *         @arg @ref LL_RCC_PLLM_DIV_47
-  *         @arg @ref LL_RCC_PLLM_DIV_48
-  *         @arg @ref LL_RCC_PLLM_DIV_49
-  *         @arg @ref LL_RCC_PLLM_DIV_50
-  *         @arg @ref LL_RCC_PLLM_DIV_51
-  *         @arg @ref LL_RCC_PLLM_DIV_52
-  *         @arg @ref LL_RCC_PLLM_DIV_53
-  *         @arg @ref LL_RCC_PLLM_DIV_54
-  *         @arg @ref LL_RCC_PLLM_DIV_55
-  *         @arg @ref LL_RCC_PLLM_DIV_56
-  *         @arg @ref LL_RCC_PLLM_DIV_57
-  *         @arg @ref LL_RCC_PLLM_DIV_58
-  *         @arg @ref LL_RCC_PLLM_DIV_59
-  *         @arg @ref LL_RCC_PLLM_DIV_60
-  *         @arg @ref LL_RCC_PLLM_DIV_61
-  *         @arg @ref LL_RCC_PLLM_DIV_62
-  *         @arg @ref LL_RCC_PLLM_DIV_63
-  * @param  PLLN Between 50 and 432
-  * @param  PLLR This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLR_DIV_2
-  *         @arg @ref LL_RCC_PLLR_DIV_3
-  *         @arg @ref LL_RCC_PLLR_DIV_4
-  *         @arg @ref LL_RCC_PLLR_DIV_5
-  *         @arg @ref LL_RCC_PLLR_DIV_6
-  *         @arg @ref LL_RCC_PLLR_DIV_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
-             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
-}
-#endif /* DSI */
-
-#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
-/**
-  * @brief  Configure PLL used for I2S clock
-  * @note PLL Source and PLLM Divider can be written only when PLL,
-  *       PLLI2S and PLLSAI are disabled
-  * @note PLLN/PLLR can be written only when PLL is disabled
-  * @note This  can be selected for I2S
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_I2S\n
-  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_I2S\n
-  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_I2S\n
-  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_I2S
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  *         @arg @ref LL_RCC_PLLM_DIV_9
-  *         @arg @ref LL_RCC_PLLM_DIV_10
-  *         @arg @ref LL_RCC_PLLM_DIV_11
-  *         @arg @ref LL_RCC_PLLM_DIV_12
-  *         @arg @ref LL_RCC_PLLM_DIV_13
-  *         @arg @ref LL_RCC_PLLM_DIV_14
-  *         @arg @ref LL_RCC_PLLM_DIV_15
-  *         @arg @ref LL_RCC_PLLM_DIV_16
-  *         @arg @ref LL_RCC_PLLM_DIV_17
-  *         @arg @ref LL_RCC_PLLM_DIV_18
-  *         @arg @ref LL_RCC_PLLM_DIV_19
-  *         @arg @ref LL_RCC_PLLM_DIV_20
-  *         @arg @ref LL_RCC_PLLM_DIV_21
-  *         @arg @ref LL_RCC_PLLM_DIV_22
-  *         @arg @ref LL_RCC_PLLM_DIV_23
-  *         @arg @ref LL_RCC_PLLM_DIV_24
-  *         @arg @ref LL_RCC_PLLM_DIV_25
-  *         @arg @ref LL_RCC_PLLM_DIV_26
-  *         @arg @ref LL_RCC_PLLM_DIV_27
-  *         @arg @ref LL_RCC_PLLM_DIV_28
-  *         @arg @ref LL_RCC_PLLM_DIV_29
-  *         @arg @ref LL_RCC_PLLM_DIV_30
-  *         @arg @ref LL_RCC_PLLM_DIV_31
-  *         @arg @ref LL_RCC_PLLM_DIV_32
-  *         @arg @ref LL_RCC_PLLM_DIV_33
-  *         @arg @ref LL_RCC_PLLM_DIV_34
-  *         @arg @ref LL_RCC_PLLM_DIV_35
-  *         @arg @ref LL_RCC_PLLM_DIV_36
-  *         @arg @ref LL_RCC_PLLM_DIV_37
-  *         @arg @ref LL_RCC_PLLM_DIV_38
-  *         @arg @ref LL_RCC_PLLM_DIV_39
-  *         @arg @ref LL_RCC_PLLM_DIV_40
-  *         @arg @ref LL_RCC_PLLM_DIV_41
-  *         @arg @ref LL_RCC_PLLM_DIV_42
-  *         @arg @ref LL_RCC_PLLM_DIV_43
-  *         @arg @ref LL_RCC_PLLM_DIV_44
-  *         @arg @ref LL_RCC_PLLM_DIV_45
-  *         @arg @ref LL_RCC_PLLM_DIV_46
-  *         @arg @ref LL_RCC_PLLM_DIV_47
-  *         @arg @ref LL_RCC_PLLM_DIV_48
-  *         @arg @ref LL_RCC_PLLM_DIV_49
-  *         @arg @ref LL_RCC_PLLM_DIV_50
-  *         @arg @ref LL_RCC_PLLM_DIV_51
-  *         @arg @ref LL_RCC_PLLM_DIV_52
-  *         @arg @ref LL_RCC_PLLM_DIV_53
-  *         @arg @ref LL_RCC_PLLM_DIV_54
-  *         @arg @ref LL_RCC_PLLM_DIV_55
-  *         @arg @ref LL_RCC_PLLM_DIV_56
-  *         @arg @ref LL_RCC_PLLM_DIV_57
-  *         @arg @ref LL_RCC_PLLM_DIV_58
-  *         @arg @ref LL_RCC_PLLM_DIV_59
-  *         @arg @ref LL_RCC_PLLM_DIV_60
-  *         @arg @ref LL_RCC_PLLM_DIV_61
-  *         @arg @ref LL_RCC_PLLM_DIV_62
-  *         @arg @ref LL_RCC_PLLM_DIV_63
-  * @param  PLLN Between 50 and 432
-  * @param  PLLR This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLR_DIV_2
-  *         @arg @ref LL_RCC_PLLR_DIV_3
-  *         @arg @ref LL_RCC_PLLR_DIV_4
-  *         @arg @ref LL_RCC_PLLR_DIV_5
-  *         @arg @ref LL_RCC_PLLR_DIV_6
-  *         @arg @ref LL_RCC_PLLR_DIV_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
-             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
-}
-#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
-
-#if defined(SPDIFRX)
-/**
-  * @brief  Configure PLL used for SPDIFRX clock
-  * @note PLL Source and PLLM Divider can be written only when PLL,
-  *       PLLI2S and PLLSAI are disabled
-  * @note PLLN/PLLR can be written only when PLL is disabled
-  * @note This  can be selected for SPDIFRX
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SPDIFRX\n
-  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SPDIFRX\n
-  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SPDIFRX\n
-  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SPDIFRX
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  *         @arg @ref LL_RCC_PLLM_DIV_9
-  *         @arg @ref LL_RCC_PLLM_DIV_10
-  *         @arg @ref LL_RCC_PLLM_DIV_11
-  *         @arg @ref LL_RCC_PLLM_DIV_12
-  *         @arg @ref LL_RCC_PLLM_DIV_13
-  *         @arg @ref LL_RCC_PLLM_DIV_14
-  *         @arg @ref LL_RCC_PLLM_DIV_15
-  *         @arg @ref LL_RCC_PLLM_DIV_16
-  *         @arg @ref LL_RCC_PLLM_DIV_17
-  *         @arg @ref LL_RCC_PLLM_DIV_18
-  *         @arg @ref LL_RCC_PLLM_DIV_19
-  *         @arg @ref LL_RCC_PLLM_DIV_20
-  *         @arg @ref LL_RCC_PLLM_DIV_21
-  *         @arg @ref LL_RCC_PLLM_DIV_22
-  *         @arg @ref LL_RCC_PLLM_DIV_23
-  *         @arg @ref LL_RCC_PLLM_DIV_24
-  *         @arg @ref LL_RCC_PLLM_DIV_25
-  *         @arg @ref LL_RCC_PLLM_DIV_26
-  *         @arg @ref LL_RCC_PLLM_DIV_27
-  *         @arg @ref LL_RCC_PLLM_DIV_28
-  *         @arg @ref LL_RCC_PLLM_DIV_29
-  *         @arg @ref LL_RCC_PLLM_DIV_30
-  *         @arg @ref LL_RCC_PLLM_DIV_31
-  *         @arg @ref LL_RCC_PLLM_DIV_32
-  *         @arg @ref LL_RCC_PLLM_DIV_33
-  *         @arg @ref LL_RCC_PLLM_DIV_34
-  *         @arg @ref LL_RCC_PLLM_DIV_35
-  *         @arg @ref LL_RCC_PLLM_DIV_36
-  *         @arg @ref LL_RCC_PLLM_DIV_37
-  *         @arg @ref LL_RCC_PLLM_DIV_38
-  *         @arg @ref LL_RCC_PLLM_DIV_39
-  *         @arg @ref LL_RCC_PLLM_DIV_40
-  *         @arg @ref LL_RCC_PLLM_DIV_41
-  *         @arg @ref LL_RCC_PLLM_DIV_42
-  *         @arg @ref LL_RCC_PLLM_DIV_43
-  *         @arg @ref LL_RCC_PLLM_DIV_44
-  *         @arg @ref LL_RCC_PLLM_DIV_45
-  *         @arg @ref LL_RCC_PLLM_DIV_46
-  *         @arg @ref LL_RCC_PLLM_DIV_47
-  *         @arg @ref LL_RCC_PLLM_DIV_48
-  *         @arg @ref LL_RCC_PLLM_DIV_49
-  *         @arg @ref LL_RCC_PLLM_DIV_50
-  *         @arg @ref LL_RCC_PLLM_DIV_51
-  *         @arg @ref LL_RCC_PLLM_DIV_52
-  *         @arg @ref LL_RCC_PLLM_DIV_53
-  *         @arg @ref LL_RCC_PLLM_DIV_54
-  *         @arg @ref LL_RCC_PLLM_DIV_55
-  *         @arg @ref LL_RCC_PLLM_DIV_56
-  *         @arg @ref LL_RCC_PLLM_DIV_57
-  *         @arg @ref LL_RCC_PLLM_DIV_58
-  *         @arg @ref LL_RCC_PLLM_DIV_59
-  *         @arg @ref LL_RCC_PLLM_DIV_60
-  *         @arg @ref LL_RCC_PLLM_DIV_61
-  *         @arg @ref LL_RCC_PLLM_DIV_62
-  *         @arg @ref LL_RCC_PLLM_DIV_63
-  * @param  PLLN Between 50 and 432
-  * @param  PLLR This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLR_DIV_2
-  *         @arg @ref LL_RCC_PLLR_DIV_3
-  *         @arg @ref LL_RCC_PLLR_DIV_4
-  *         @arg @ref LL_RCC_PLLR_DIV_5
-  *         @arg @ref LL_RCC_PLLR_DIV_6
-  *         @arg @ref LL_RCC_PLLR_DIV_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
-             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
-}
-#endif /* SPDIFRX */
-
-#if defined(RCC_PLLCFGR_PLLR)
-#if defined(SAI1)
-/**
-  * @brief  Configure PLL used for SAI clock
-  * @note PLL Source and PLLM Divider can be written only when PLL,
-  *       PLLI2S and PLLSAI are disabled
-  * @note PLLN/PLLR can be written only when PLL is disabled
-  * @note This  can be selected for SAI
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SAI\n
-  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SAI\n
-  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SAI\n
-  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SAI\n
-  *         DCKCFGR      PLLDIVR       LL_RCC_PLL_ConfigDomain_SAI
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  *         @arg @ref LL_RCC_PLLM_DIV_9
-  *         @arg @ref LL_RCC_PLLM_DIV_10
-  *         @arg @ref LL_RCC_PLLM_DIV_11
-  *         @arg @ref LL_RCC_PLLM_DIV_12
-  *         @arg @ref LL_RCC_PLLM_DIV_13
-  *         @arg @ref LL_RCC_PLLM_DIV_14
-  *         @arg @ref LL_RCC_PLLM_DIV_15
-  *         @arg @ref LL_RCC_PLLM_DIV_16
-  *         @arg @ref LL_RCC_PLLM_DIV_17
-  *         @arg @ref LL_RCC_PLLM_DIV_18
-  *         @arg @ref LL_RCC_PLLM_DIV_19
-  *         @arg @ref LL_RCC_PLLM_DIV_20
-  *         @arg @ref LL_RCC_PLLM_DIV_21
-  *         @arg @ref LL_RCC_PLLM_DIV_22
-  *         @arg @ref LL_RCC_PLLM_DIV_23
-  *         @arg @ref LL_RCC_PLLM_DIV_24
-  *         @arg @ref LL_RCC_PLLM_DIV_25
-  *         @arg @ref LL_RCC_PLLM_DIV_26
-  *         @arg @ref LL_RCC_PLLM_DIV_27
-  *         @arg @ref LL_RCC_PLLM_DIV_28
-  *         @arg @ref LL_RCC_PLLM_DIV_29
-  *         @arg @ref LL_RCC_PLLM_DIV_30
-  *         @arg @ref LL_RCC_PLLM_DIV_31
-  *         @arg @ref LL_RCC_PLLM_DIV_32
-  *         @arg @ref LL_RCC_PLLM_DIV_33
-  *         @arg @ref LL_RCC_PLLM_DIV_34
-  *         @arg @ref LL_RCC_PLLM_DIV_35
-  *         @arg @ref LL_RCC_PLLM_DIV_36
-  *         @arg @ref LL_RCC_PLLM_DIV_37
-  *         @arg @ref LL_RCC_PLLM_DIV_38
-  *         @arg @ref LL_RCC_PLLM_DIV_39
-  *         @arg @ref LL_RCC_PLLM_DIV_40
-  *         @arg @ref LL_RCC_PLLM_DIV_41
-  *         @arg @ref LL_RCC_PLLM_DIV_42
-  *         @arg @ref LL_RCC_PLLM_DIV_43
-  *         @arg @ref LL_RCC_PLLM_DIV_44
-  *         @arg @ref LL_RCC_PLLM_DIV_45
-  *         @arg @ref LL_RCC_PLLM_DIV_46
-  *         @arg @ref LL_RCC_PLLM_DIV_47
-  *         @arg @ref LL_RCC_PLLM_DIV_48
-  *         @arg @ref LL_RCC_PLLM_DIV_49
-  *         @arg @ref LL_RCC_PLLM_DIV_50
-  *         @arg @ref LL_RCC_PLLM_DIV_51
-  *         @arg @ref LL_RCC_PLLM_DIV_52
-  *         @arg @ref LL_RCC_PLLM_DIV_53
-  *         @arg @ref LL_RCC_PLLM_DIV_54
-  *         @arg @ref LL_RCC_PLLM_DIV_55
-  *         @arg @ref LL_RCC_PLLM_DIV_56
-  *         @arg @ref LL_RCC_PLLM_DIV_57
-  *         @arg @ref LL_RCC_PLLM_DIV_58
-  *         @arg @ref LL_RCC_PLLM_DIV_59
-  *         @arg @ref LL_RCC_PLLM_DIV_60
-  *         @arg @ref LL_RCC_PLLM_DIV_61
-  *         @arg @ref LL_RCC_PLLM_DIV_62
-  *         @arg @ref LL_RCC_PLLM_DIV_63
-  * @param  PLLN Between 50 and 432
-  * @param  PLLR This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLR_DIV_2
-  *         @arg @ref LL_RCC_PLLR_DIV_3
-  *         @arg @ref LL_RCC_PLLR_DIV_4
-  *         @arg @ref LL_RCC_PLLR_DIV_5
-  *         @arg @ref LL_RCC_PLLR_DIV_6
-  *         @arg @ref LL_RCC_PLLR_DIV_7
-  * @param  PLLDIVR This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-#if defined(RCC_DCKCFGR_PLLDIVR)
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
-#else
-__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
-#endif /* RCC_DCKCFGR_PLLDIVR */
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
-             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
-#if defined(RCC_DCKCFGR_PLLDIVR)
-  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR);
-#endif /* RCC_DCKCFGR_PLLDIVR */
-}
-#endif /* SAI1 */
-#endif /* RCC_PLLCFGR_PLLR */
-
-/**
-  * @brief  Configure PLL clock source
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_SetMainSource
-  * @param PLLSource This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
-}
-
-/**
-  * @brief  Get the oscillator used as PLL clock source.
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
-}
-
-/**
-  * @brief  Get Main PLL multiplication factor for VCO
-  * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN
-  * @retval Between 50/192(*) and 432
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_PLLCFGR_PLLN_Pos);
-}
-
-/**
-  * @brief  Get Main PLL division factor for PLLP 
-  * @rmtoll PLLCFGR      PLLP       LL_RCC_PLL_GetP
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLP_DIV_2
-  *         @arg @ref LL_RCC_PLLP_DIV_4
-  *         @arg @ref LL_RCC_PLLP_DIV_6
-  *         @arg @ref LL_RCC_PLLP_DIV_8
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
-}
-
-/**
-  * @brief  Get Main PLL division factor for PLLQ
-  * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
-  * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLQ_DIV_2
-  *         @arg @ref LL_RCC_PLLQ_DIV_3
-  *         @arg @ref LL_RCC_PLLQ_DIV_4
-  *         @arg @ref LL_RCC_PLLQ_DIV_5
-  *         @arg @ref LL_RCC_PLLQ_DIV_6
-  *         @arg @ref LL_RCC_PLLQ_DIV_7
-  *         @arg @ref LL_RCC_PLLQ_DIV_8
-  *         @arg @ref LL_RCC_PLLQ_DIV_9
-  *         @arg @ref LL_RCC_PLLQ_DIV_10
-  *         @arg @ref LL_RCC_PLLQ_DIV_11
-  *         @arg @ref LL_RCC_PLLQ_DIV_12
-  *         @arg @ref LL_RCC_PLLQ_DIV_13
-  *         @arg @ref LL_RCC_PLLQ_DIV_14
-  *         @arg @ref LL_RCC_PLLQ_DIV_15
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
-}
-
-#if defined(RCC_PLLCFGR_PLLR)
-/**
-  * @brief  Get Main PLL division factor for PLLR
-  * @note used for PLLCLK (system clock)
-  * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLR_DIV_2
-  *         @arg @ref LL_RCC_PLLR_DIV_3
-  *         @arg @ref LL_RCC_PLLR_DIV_4
-  *         @arg @ref LL_RCC_PLLR_DIV_5
-  *         @arg @ref LL_RCC_PLLR_DIV_6
-  *         @arg @ref LL_RCC_PLLR_DIV_7
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
-}
-#endif /* RCC_PLLCFGR_PLLR */
-
-#if defined(RCC_DCKCFGR_PLLDIVR)
-/**
-  * @brief  Get Main PLL division factor for PLLDIVR
-  * @note used for PLLSAICLK (SAI1 and SAI2 clock)
-  * @rmtoll DCKCFGR      PLLDIVR          LL_RCC_PLL_GetDIVR
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_1
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_2
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_3
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_4
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_5
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_6
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_7
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_8
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_9
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_10
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_11
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_12
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_13
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_14
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_15
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_16
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_17
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_18
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_19
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_20
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_21
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_22
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_23
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_24
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_25
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_26
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_27
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_28
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_29
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_30
-  *         @arg @ref LL_RCC_PLLDIVR_DIV_31
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void)
-{
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR));
-}
-#endif /* RCC_DCKCFGR_PLLDIVR */
-
-/**
-  * @brief  Get Division factor for the main PLL and other PLL
-  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLM_DIV_2
-  *         @arg @ref LL_RCC_PLLM_DIV_3
-  *         @arg @ref LL_RCC_PLLM_DIV_4
-  *         @arg @ref LL_RCC_PLLM_DIV_5
-  *         @arg @ref LL_RCC_PLLM_DIV_6
-  *         @arg @ref LL_RCC_PLLM_DIV_7
-  *         @arg @ref LL_RCC_PLLM_DIV_8
-  *         @arg @ref LL_RCC_PLLM_DIV_9
-  *         @arg @ref LL_RCC_PLLM_DIV_10
-  *         @arg @ref LL_RCC_PLLM_DIV_11
-  *         @arg @ref LL_RCC_PLLM_DIV_12
-  *         @arg @ref LL_RCC_PLLM_DIV_13
-  *         @arg @ref LL_RCC_PLLM_DIV_14
-  *         @arg @ref LL_RCC_PLLM_DIV_15
-  *         @arg @ref LL_RCC_PLLM_DIV_16
-  *         @arg @ref LL_RCC_PLLM_DIV_17
-  *         @arg @ref LL_RCC_PLLM_DIV_18
-  *         @arg @ref LL_RCC_PLLM_DIV_19
-  *         @arg @ref LL_RCC_PLLM_DIV_20
-  *         @arg @ref LL_RCC_PLLM_DIV_21
-  *         @arg @ref LL_RCC_PLLM_DIV_22
-  *         @arg @ref LL_RCC_PLLM_DIV_23
-  *         @arg @ref LL_RCC_PLLM_DIV_24
-  *         @arg @ref LL_RCC_PLLM_DIV_25
-  *         @arg @ref LL_RCC_PLLM_DIV_26
-  *         @arg @ref LL_RCC_PLLM_DIV_27
-  *         @arg @ref LL_RCC_PLLM_DIV_28
-  *         @arg @ref LL_RCC_PLLM_DIV_29
-  *         @arg @ref LL_RCC_PLLM_DIV_30
-  *         @arg @ref LL_RCC_PLLM_DIV_31
-  *         @arg @ref LL_RCC_PLLM_DIV_32
-  *         @arg @ref LL_RCC_PLLM_DIV_33
-  *         @arg @ref LL_RCC_PLLM_DIV_34
-  *         @arg @ref LL_RCC_PLLM_DIV_35
-  *         @arg @ref LL_RCC_PLLM_DIV_36
-  *         @arg @ref LL_RCC_PLLM_DIV_37
-  *         @arg @ref LL_RCC_PLLM_DIV_38
-  *         @arg @ref LL_RCC_PLLM_DIV_39
-  *         @arg @ref LL_RCC_PLLM_DIV_40
-  *         @arg @ref LL_RCC_PLLM_DIV_41
-  *         @arg @ref LL_RCC_PLLM_DIV_42
-  *         @arg @ref LL_RCC_PLLM_DIV_43
-  *         @arg @ref LL_RCC_PLLM_DIV_44
-  *         @arg @ref LL_RCC_PLLM_DIV_45
-  *         @arg @ref LL_RCC_PLLM_DIV_46
-  *         @arg @ref LL_RCC_PLLM_DIV_47
-  *         @arg @ref LL_RCC_PLLM_DIV_48
-  *         @arg @ref LL_RCC_PLLM_DIV_49
-  *         @arg @ref LL_RCC_PLLM_DIV_50
-  *         @arg @ref LL_RCC_PLLM_DIV_51
-  *         @arg @ref LL_RCC_PLLM_DIV_52
-  *         @arg @ref LL_RCC_PLLM_DIV_53
-  *         @arg @ref LL_RCC_PLLM_DIV_54
-  *         @arg @ref LL_RCC_PLLM_DIV_55
-  *         @arg @ref LL_RCC_PLLM_DIV_56
-  *         @arg @ref LL_RCC_PLLM_DIV_57
-  *         @arg @ref LL_RCC_PLLM_DIV_58
-  *         @arg @ref LL_RCC_PLLM_DIV_59
-  *         @arg @ref LL_RCC_PLLM_DIV_60
-  *         @arg @ref LL_RCC_PLLM_DIV_61
-  *         @arg @ref LL_RCC_PLLM_DIV_62
-  *         @arg @ref LL_RCC_PLLM_DIV_63
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
-}
-
-/**
-  * @brief  Configure Spread Spectrum used for PLL
-  * @note These bits must be written before enabling PLL
-  * @rmtoll SSCGR        MODPER        LL_RCC_PLL_ConfigSpreadSpectrum\n
-  *         SSCGR        INCSTEP       LL_RCC_PLL_ConfigSpreadSpectrum\n
-  *         SSCGR        SPREADSEL     LL_RCC_PLL_ConfigSpreadSpectrum
-  * @param  Mod Between Min_Data=0 and Max_Data=8191
-  * @param  Inc Between Min_Data=0 and Max_Data=32767
-  * @param  Sel This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_SPREAD_SELECT_CENTER
-  *         @arg @ref LL_RCC_SPREAD_SELECT_DOWN
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
-{
-  MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
-}
-
-/**
-  * @brief  Get Spread Spectrum Modulation Period for PLL
-  * @rmtoll SSCGR         MODPER        LL_RCC_PLL_GetPeriodModulation
-  * @retval Between Min_Data=0 and Max_Data=8191
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
-{
-  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
-}
-
-/**
-  * @brief  Get Spread Spectrum Incrementation Step for PLL
-  * @note Must be written before enabling PLL
-  * @rmtoll SSCGR         INCSTEP        LL_RCC_PLL_GetStepIncrementation
-  * @retval Between Min_Data=0 and Max_Data=32767
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
-{
-  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
-}
-
-/**
-  * @brief  Get Spread Spectrum Selection for PLL
-  * @note Must be written before enabling PLL
-  * @rmtoll SSCGR         SPREADSEL        LL_RCC_PLL_GetSpreadSelection
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_SPREAD_SELECT_CENTER
-  *         @arg @ref LL_RCC_SPREAD_SELECT_DOWN
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
-{
-  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
-}
-
-/**
-  * @brief  Enable Spread Spectrum for PLL.
-  * @rmtoll SSCGR         SSCGEN         LL_RCC_PLL_SpreadSpectrum_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
-{
-  SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
-}
-
-/**
-  * @brief  Disable Spread Spectrum for PLL.
-  * @rmtoll SSCGR         SSCGEN         LL_RCC_PLL_SpreadSpectrum_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
-{
-  CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
-}
-
-/**
-  * @}
-  */
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
-  * @{
-  */
-
-/**
-  * @brief  Enable PLLI2S
-  * @rmtoll CR           PLLI2SON     LL_RCC_PLLI2S_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
-}
-
-/**
-  * @brief  Disable PLLI2S
-  * @rmtoll CR           PLLI2SON     LL_RCC_PLLI2S_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
-}
-
-/**
-  * @brief  Check if PLLI2S Ready
-  * @rmtoll CR           PLLI2SRDY    LL_RCC_PLLI2S_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
-{
-  return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
-}
-
-#if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR))
-/**
-  * @brief  Configure PLLI2S used for SAI domain clock
-  * @note PLL Source and PLLM Divider can be written only when PLL,
-  *       PLLI2S and PLLSAI(*) are disabled
-  * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled
-  * @note This can be selected for SAI
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_SAI\n
-  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_ConfigDomain_SAI\n
-  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_SAI\n
-  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_SAI\n
-  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_SAI\n
-  *         PLLI2SCFGR   PLLI2SQ       LL_RCC_PLLI2S_ConfigDomain_SAI\n
-  *         PLLI2SCFGR   PLLI2SR       LL_RCC_PLLI2S_ConfigDomain_SAI\n
-  *         DCKCFGR      PLLI2SDIVQ    LL_RCC_PLLI2S_ConfigDomain_SAI\n
-  *         DCKCFGR      PLLI2SDIVR    LL_RCC_PLLI2S_ConfigDomain_SAI
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
-  *
-  *         (*) value not defined in all devices.
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
-  * @param  PLLN Between 50/192(*) and 432
-  *
-  *         (*) value not defined in all devices.
-  * @param  PLLQ_R This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @param  PLLDIVQ_R This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
-{
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
-  MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
-#if defined(RCC_PLLI2SCFGR_PLLI2SM)
-  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
-#else
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
-#endif /* RCC_PLLI2SCFGR_PLLI2SM */
-  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos);
-#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
-  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R);
-  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R);
-#else
-  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R);
-  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R);
-#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
-}
-#endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */
-
-#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
-/**
-  * @brief  Configure PLLI2S used for 48Mhz domain clock
-  * @note PLL Source and PLLM Divider can be written only when PLL,
-  *       PLLI2S and PLLSAI(*) are disabled
-  * @note PLLN/PLLQ can be written only when PLLI2S is disabled
-  * @note This can be selected for RNG, USB, SDIO
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_48M\n
-  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_ConfigDomain_48M\n
-  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_48M\n
-  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_48M\n
-  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_48M\n
-  *         PLLI2SCFGR   PLLI2SQ       LL_RCC_PLLI2S_ConfigDomain_48M
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
-  *
-  *         (*) value not defined in all devices.
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
-  * @param  PLLN Between 50 and 432
-  * @param  PLLQ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
-{
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
-  MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
-#if defined(RCC_PLLI2SCFGR_PLLI2SM)
-  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
-#else
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
-#endif /* RCC_PLLI2SCFGR_PLLI2SM */
-  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ);
-}
-#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
-
-#if defined(SPDIFRX)
-/**
-  * @brief Configure PLLI2S used for SPDIFRX domain clock
-  * @note PLL Source and PLLM Divider can be written only when PLL,
-  *       PLLI2S and PLLSAI(*) are disabled
-  * @note PLLN/PLLP can be written only when PLLI2S is disabled
-  * @note This  can be selected for SPDIFRX
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
-  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
-  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
-  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
-  *         PLLI2SCFGR   PLLI2SP       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
-  * @param  PLLN Between 50 and 432
-  * @param  PLLP This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SP_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SP_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SP_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SP_DIV_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
-#if defined(RCC_PLLI2SCFGR_PLLI2SM)
-  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
-#else
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
-#endif /* RCC_PLLI2SCFGR_PLLI2SM */
-  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP);
-}
-#endif /* SPDIFRX */
-
-/**
-  * @brief  Configure PLLI2S used for I2S1 domain clock
-  * @note PLL Source and PLLM Divider can be written only when PLL,
-  *       PLLI2S and PLLSAI(*) are disabled
-  * @note PLLN/PLLR can be written only when PLLI2S is disabled
-  * @note This  can be selected for I2S
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_I2S\n
-  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_I2S\n
-  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_ConfigDomain_I2S\n
-  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_I2S\n
-  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_I2S\n
-  *         PLLI2SCFGR   PLLI2SR       LL_RCC_PLLI2S_ConfigDomain_I2S
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
-  *
-  *         (*) value not defined in all devices.
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
-  * @param  PLLN Between 50/192(*) and 432
-  *
-  *         (*) value not defined in all devices.
-  * @param  PLLR This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_7
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
-{
-  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
-  MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
-#if defined(RCC_PLLI2SCFGR_PLLI2SM)
-  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
-#else
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
-#endif /* RCC_PLLI2SCFGR_PLLI2SM */
-  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
-}
-
-/**
-  * @brief  Get I2SPLL multiplication factor for VCO
-  * @rmtoll PLLI2SCFGR  PLLI2SN      LL_RCC_PLLI2S_GetN
-  * @retval Between 50/192(*) and 432
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
-}
-
-#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
-/**
-  * @brief  Get I2SPLL division factor for PLLI2SQ
-  * @rmtoll PLLI2SCFGR  PLLI2SQ      LL_RCC_PLLI2S_GetQ
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
-  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
-}
-#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
-
-/**
-  * @brief  Get I2SPLL division factor for PLLI2SR
-  * @note used for PLLI2SCLK (I2S clock)
-  * @rmtoll PLLI2SCFGR  PLLI2SR      LL_RCC_PLLI2S_GetR
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SR_DIV_7
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
-}
-
-#if defined(RCC_PLLI2SCFGR_PLLI2SP)
-/**
-  * @brief  Get I2SPLL division factor for PLLI2SP
-  * @note used for PLLSPDIFRXCLK (SPDIFRX clock)
-  * @rmtoll PLLI2SCFGR  PLLI2SP      LL_RCC_PLLI2S_GetP
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SP_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SP_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SP_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SP_DIV_8
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
-}
-#endif /* RCC_PLLI2SCFGR_PLLI2SP */
-
-#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
-/**
-  * @brief  Get I2SPLL division factor for PLLI2SDIVQ
-  * @note used PLLSAICLK selected (SAI clock)
-  * @rmtoll DCKCFGR   PLLI2SDIVQ      LL_RCC_PLLI2S_GetDIVQ
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
-  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
-{
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ));
-}
-#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
-
-#if defined(RCC_DCKCFGR_PLLI2SDIVR)
-/**
-  * @brief  Get I2SPLL division factor for PLLI2SDIVR
-  * @note used PLLSAICLK selected (SAI clock)
-  * @rmtoll DCKCFGR   PLLI2SDIVR      LL_RCC_PLLI2S_GetDIVR
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_1
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_7
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_8
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_9
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_10
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_11
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_12
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_13
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_14
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_15
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_16
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_17
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_18
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_19
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_20
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_21
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_22
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_23
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_24
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_25
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_26
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_27
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_28
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_29
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_30
-  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_31
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void)
-{
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR));
-}
-#endif /* RCC_DCKCFGR_PLLI2SDIVR */
-
-/**
-  * @brief  Get division factor for PLLI2S input clock
-  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLLI2S_GetDivider\n
-  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_GetDivider
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
-  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)
-{
-#if defined(RCC_PLLI2SCFGR_PLLI2SM)
-  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM));
-#else
-  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
-#endif /* RCC_PLLI2SCFGR_PLLI2SM */
-}
-
-/**
-  * @brief  Get the oscillator used as PLL clock source.
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_GetMainSource\n
-  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_GetMainSource
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)
-{
-#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
-  uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
-  uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
-  uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
-  return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1);
-#else
-  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
-#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
-}
-
-/**
-  * @}
-  */
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLLSAI_SUPPORT)
-/** @defgroup RCC_LL_EF_PLLSAI PLLSAI
-  * @{
-  */
-
-/**
-  * @brief  Enable PLLSAI
-  * @rmtoll CR           PLLSAION     LL_RCC_PLLSAI_Enable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
-{
-  SET_BIT(RCC->CR, RCC_CR_PLLSAION);
-}
-
-/**
-  * @brief  Disable PLLSAI
-  * @rmtoll CR           PLLSAION     LL_RCC_PLLSAI_Disable
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
-{
-  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
-}
-
-/**
-  * @brief  Check if PLLSAI Ready
-  * @rmtoll CR           PLLSAIRDY    LL_RCC_PLLSAI_IsReady
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
-{
-  return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
-}
-
-/**
-  * @brief  Configure PLLSAI used for SAI domain clock
-  * @note PLL Source and PLLM Divider can be written only when PLL,
-  *       PLLI2S and PLLSAI(*) are disabled
-  * @note PLLN/PLLQ can be written only when PLLSAI is disabled
-  * @note This can be selected for SAI
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_SAI\n
-  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_SAI\n
-  *         PLLSAICFGR   PLLSAIM       LL_RCC_PLLSAI_ConfigDomain_SAI\n
-  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_SAI\n
-  *         PLLSAICFGR   PLLSAIQ       LL_RCC_PLLSAI_ConfigDomain_SAI\n
-  *         DCKCFGR      PLLSAIDIVQ    LL_RCC_PLLSAI_ConfigDomain_SAI
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
-  * @param  PLLN Between 49/50(*) and 432
-  *
-  *         (*) value not defined in all devices.
-  * @param  PLLQ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15
-  * @param  PLLDIVQ This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
-#if defined(RCC_PLLSAICFGR_PLLSAIM)
-  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
-#else
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
-#endif /* RCC_PLLSAICFGR_PLLSAIM */
-  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ);
-  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ);
-}
-
-#if defined(RCC_PLLSAICFGR_PLLSAIP)
-/**
-  * @brief Configure PLLSAI used for 48Mhz domain clock
-  * @note PLL Source and PLLM Divider can be written only when PLL,
-  *       PLLI2S and PLLSAI(*) are disabled
-  * @note PLLN/PLLP can be written only when PLLSAI is disabled
-  * @note This  can be selected for USB, RNG, SDIO
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_48M\n
-  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_48M\n
-  *         PLLSAICFGR   PLLSAIM       LL_RCC_PLLSAI_ConfigDomain_48M\n
-  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_48M\n
-  *         PLLSAICFGR   PLLSAIP       LL_RCC_PLLSAI_ConfigDomain_48M
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
-  * @param  PLLN Between 50 and 432
-  * @param  PLLP This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIP_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIP_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIP_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIP_DIV_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
-#if defined(RCC_PLLSAICFGR_PLLSAIM)
-  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
-#else
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
-#endif /* RCC_PLLSAICFGR_PLLSAIM */
-  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP);
-}
-#endif /* RCC_PLLSAICFGR_PLLSAIP */
-
-#if defined(LTDC)
-/**
-  * @brief  Configure PLLSAI used for LTDC domain clock
-  * @note PLL Source and PLLM Divider can be written only when PLL,
-  *       PLLI2S and PLLSAI(*) are disabled
-  * @note PLLN/PLLR can be written only when PLLSAI is disabled
-  * @note This  can be selected for LTDC
-  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_LTDC\n
-  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_LTDC\n
-  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_LTDC\n
-  *         PLLSAICFGR   PLLSAIR       LL_RCC_PLLSAI_ConfigDomain_LTDC\n
-  *         DCKCFGR      PLLSAIDIVR    LL_RCC_PLLSAI_ConfigDomain_LTDC
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSOURCE_HSI
-  *         @arg @ref LL_RCC_PLLSOURCE_HSE
-  * @param  PLLM This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
-  * @param  PLLN Between 49/50(*) and 432
-  *
-  *         (*) value not defined in all devices.
-  * @param  PLLR This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_3
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_5
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_7
-  * @param  PLLDIVR This parameter can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
-  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
-{
-  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
-  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR);
-  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR);
-}
-#endif /* LTDC */
-
-/**
-  * @brief  Get division factor for PLLSAI input clock
-  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLLSAI_GetDivider\n
-  *         PLLSAICFGR   PLLSAIM       LL_RCC_PLLSAI_GetDivider
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
-  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void)
-{
-#if defined(RCC_PLLSAICFGR_PLLSAIM)
-  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM));
-#else
-  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
-#endif /* RCC_PLLSAICFGR_PLLSAIM */
-}
-
-/**
-  * @brief  Get SAIPLL multiplication factor for VCO
-  * @rmtoll PLLSAICFGR  PLLSAIN      LL_RCC_PLLSAI_GetN
-  * @retval Between 49/50(*) and 432
-  *
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
-}
-
-/**
-  * @brief  Get SAIPLL division factor for PLLSAIQ
-  * @rmtoll PLLSAICFGR  PLLSAIQ      LL_RCC_PLLSAI_GetQ
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14
-  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
-}
-
-#if defined(RCC_PLLSAICFGR_PLLSAIR)
-/**
-  * @brief  Get SAIPLL division factor for PLLSAIR
-  * @note used for PLLSAICLK (SAI clock)
-  * @rmtoll PLLSAICFGR  PLLSAIR      LL_RCC_PLLSAI_GetR
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_3
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_5
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIR_DIV_7
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
-}
-#endif /* RCC_PLLSAICFGR_PLLSAIR */
-
-#if defined(RCC_PLLSAICFGR_PLLSAIP)
-/**
-  * @brief  Get SAIPLL division factor for PLLSAIP
-  * @note used for PLL48MCLK (48M domain clock)
-  * @rmtoll PLLSAICFGR  PLLSAIP      LL_RCC_PLLSAI_GetP
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIP_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIP_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIP_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIP_DIV_8
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
-{
-  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
-}
-#endif /* RCC_PLLSAICFGR_PLLSAIP */
-
-/**
-  * @brief  Get SAIPLL division factor for PLLSAIDIVQ
-  * @note used PLLSAICLK selected (SAI clock)
-  * @rmtoll DCKCFGR   PLLSAIDIVQ      LL_RCC_PLLSAI_GetDIVQ
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
-  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
-{
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ));
-}
-
-#if defined(RCC_DCKCFGR_PLLSAIDIVR)
-/**
-  * @brief  Get SAIPLL division factor for PLLSAIDIVR
-  * @note used for LTDC domain clock
-  * @rmtoll DCKCFGR  PLLSAIDIVR      LL_RCC_PLLSAI_GetDIVR
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
-  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
-  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
-  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
-  */
-__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
-{
-  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR));
-}
-#endif /* RCC_DCKCFGR_PLLSAIDIVR */
-
-/**
-  * @}
-  */
-#endif /* RCC_PLLSAI_SUPPORT */
-
-/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
-  * @{
-  */
-
-/**
-  * @brief  Clear LSI ready interrupt flag
-  * @rmtoll CIR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
-}
-
-/**
-  * @brief  Clear LSE ready interrupt flag
-  * @rmtoll CIR         LSERDYC       LL_RCC_ClearFlag_LSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
-}
-
-/**
-  * @brief  Clear HSI ready interrupt flag
-  * @rmtoll CIR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
-}
-
-/**
-  * @brief  Clear HSE ready interrupt flag
-  * @rmtoll CIR         HSERDYC       LL_RCC_ClearFlag_HSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
-}
-
-/**
-  * @brief  Clear PLL ready interrupt flag
-  * @rmtoll CIR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
-}
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
-  * @brief  Clear PLLI2S ready interrupt flag
-  * @rmtoll CIR         PLLI2SRDYC   LL_RCC_ClearFlag_PLLI2SRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
-}
-
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLLSAI_SUPPORT)
-/**
-  * @brief  Clear PLLSAI ready interrupt flag
-  * @rmtoll CIR         PLLSAIRDYC   LL_RCC_ClearFlag_PLLSAIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
-}
-
-#endif /* RCC_PLLSAI_SUPPORT */
-
-/**
-  * @brief  Clear Clock security system interrupt flag
-  * @rmtoll CIR         CSSC          LL_RCC_ClearFlag_HSECSS
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_CSSC);
-}
-
-/**
-  * @brief  Check if LSI ready interrupt occurred or not
-  * @rmtoll CIR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
-{
-  return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
-}
-
-/**
-  * @brief  Check if LSE ready interrupt occurred or not
-  * @rmtoll CIR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
-{
-  return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
-}
-
-/**
-  * @brief  Check if HSI ready interrupt occurred or not
-  * @rmtoll CIR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
-{
-  return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
-}
-
-/**
-  * @brief  Check if HSE ready interrupt occurred or not
-  * @rmtoll CIR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
-{
-  return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
-}
-
-/**
-  * @brief  Check if PLL ready interrupt occurred or not
-  * @rmtoll CIR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
-{
-  return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
-}
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
-  * @brief  Check if PLLI2S ready interrupt occurred or not
-  * @rmtoll CIR         PLLI2SRDYF   LL_RCC_IsActiveFlag_PLLI2SRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
-{
-  return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
-}
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLLSAI_SUPPORT)
-/**
-  * @brief  Check if PLLSAI ready interrupt occurred or not
-  * @rmtoll CIR         PLLSAIRDYF   LL_RCC_IsActiveFlag_PLLSAIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
-{
-  return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
-}
-#endif /* RCC_PLLSAI_SUPPORT */
-
-/**
-  * @brief  Check if Clock security system interrupt occurred or not
-  * @rmtoll CIR         CSSF          LL_RCC_IsActiveFlag_HSECSS
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
-{
-  return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
-}
-
-/**
-  * @brief  Check if RCC flag Independent Watchdog reset is set or not.
-  * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
-{
-  return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
-}
-
-/**
-  * @brief  Check if RCC flag Low Power reset is set or not.
-  * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
-{
-  return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
-}
-
-/**
-  * @brief  Check if RCC flag Pin reset is set or not.
-  * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
-{
-  return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
-}
-
-/**
-  * @brief  Check if RCC flag POR/PDR reset is set or not.
-  * @rmtoll CSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
-{
-  return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
-}
-
-/**
-  * @brief  Check if RCC flag Software reset is set or not.
-  * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
-{
-  return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
-}
-
-/**
-  * @brief  Check if RCC flag Window Watchdog reset is set or not.
-  * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
-{
-  return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
-}
-
-#if defined(RCC_CSR_BORRSTF)
-/**
-  * @brief  Check if RCC flag BOR reset is set or not.
-  * @rmtoll CSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
-{
-  return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
-}
-#endif /* RCC_CSR_BORRSTF */
-
-/**
-  * @brief  Set RMVF bit to clear the reset flags.
-  * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
-{
-  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_IT_Management IT Management
-  * @{
-  */
-
-/**
-  * @brief  Enable LSI ready interrupt
-  * @rmtoll CIR         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
-}
-
-/**
-  * @brief  Enable LSE ready interrupt
-  * @rmtoll CIR         LSERDYIE      LL_RCC_EnableIT_LSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
-}
-
-/**
-  * @brief  Enable HSI ready interrupt
-  * @rmtoll CIR         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
-}
-
-/**
-  * @brief  Enable HSE ready interrupt
-  * @rmtoll CIR         HSERDYIE      LL_RCC_EnableIT_HSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
-}
-
-/**
-  * @brief  Enable PLL ready interrupt
-  * @rmtoll CIR         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
-}
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
-  * @brief  Enable PLLI2S ready interrupt
-  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_EnableIT_PLLI2SRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
-}
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLLSAI_SUPPORT)
-/**
-  * @brief  Enable PLLSAI ready interrupt
-  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_EnableIT_PLLSAIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
-{
-  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
-}
-#endif /* RCC_PLLSAI_SUPPORT */
-
-/**
-  * @brief  Disable LSI ready interrupt
-  * @rmtoll CIR         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
-{
-  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
-}
-
-/**
-  * @brief  Disable LSE ready interrupt
-  * @rmtoll CIR         LSERDYIE      LL_RCC_DisableIT_LSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
-{
-  CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
-}
-
-/**
-  * @brief  Disable HSI ready interrupt
-  * @rmtoll CIR         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
-{
-  CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
-}
-
-/**
-  * @brief  Disable HSE ready interrupt
-  * @rmtoll CIR         HSERDYIE      LL_RCC_DisableIT_HSERDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
-{
-  CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
-}
-
-/**
-  * @brief  Disable PLL ready interrupt
-  * @rmtoll CIR         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
-{
-  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
-}
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
-  * @brief  Disable PLLI2S ready interrupt
-  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_DisableIT_PLLI2SRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
-{
-  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
-}
-
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLLSAI_SUPPORT)
-/**
-  * @brief  Disable PLLSAI ready interrupt
-  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_DisableIT_PLLSAIRDY
-  * @retval None
-  */
-__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
-{
-  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
-}
-#endif /* RCC_PLLSAI_SUPPORT */
-
-/**
-  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
-  * @rmtoll CIR         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
-{
-  return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
-}
-
-/**
-  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
-  * @rmtoll CIR         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
-{
-  return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
-}
-
-/**
-  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
-  * @rmtoll CIR         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
-{
-  return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
-}
-
-/**
-  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
-  * @rmtoll CIR         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
-{
-  return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
-}
-
-/**
-  * @brief  Checks if PLL ready interrupt source is enabled or disabled.
-  * @rmtoll CIR         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
-{
-  return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
-}
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
-  * @brief  Checks if PLLI2S ready interrupt source is enabled or disabled.
-  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_IsEnabledIT_PLLI2SRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
-{
-  return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
-}
-
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLLSAI_SUPPORT)
-/**
-  * @brief  Checks if PLLSAI ready interrupt source is enabled or disabled.
-  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_IsEnabledIT_PLLSAIRDY
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
-{
-  return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
-}
-#endif /* RCC_PLLSAI_SUPPORT */
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup RCC_LL_EF_Init De-initialization function
-  * @{
-  */
-ErrorStatus LL_RCC_DeInit(void);
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
-  * @{
-  */
-void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
-#if defined(FMPI2C1)
-uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource);
-#endif /* FMPI2C1 */
-#if defined(LPTIM1)
-uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
-#endif /* LPTIM1 */
-#if defined(SAI1)
-uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
-#endif /* SAI1 */
-#if defined(SDIO)
-uint32_t    LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource);
-#endif /* SDIO */
-#if defined(RNG)
-uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
-#endif /* RNG */
-#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
-uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
-#endif /* USB_OTG_FS || USB_OTG_HS */
-#if defined(DFSDM1_Channel0)
-uint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
-uint32_t    LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
-#endif /* DFSDM1_Channel0 */
-uint32_t    LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
-#if defined(CEC)
-uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);
-#endif /* CEC */
-#if defined(LTDC)
-uint32_t    LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
-#endif /* LTDC */
-#if defined(SPDIFRX)
-uint32_t    LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
-#endif /* SPDIFRX */
-#if defined(DSI)
-uint32_t    LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
-#endif /* DSI */
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined(RCC) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_LL_RCC_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_rcc.h
+  * @author  MCD Application Team
+  * @brief   Header file of RCC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_RCC_H
+#define __STM32F4xx_LL_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined(RCC)
+
+/** @defgroup RCC_LL RCC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_LL_Private_Variables RCC Private Variables
+  * @{
+  */
+
+#if defined(RCC_DCKCFGR_PLLSAIDIVR)
+static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
+#endif /* RCC_DCKCFGR_PLLSAIDIVR */
+
+/**
+  * @}
+  */
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Private_Macros RCC Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_Exported_Types RCC Exported Types
+  * @{
+  */
+
+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
+  * @{
+  */
+
+/**
+  * @brief  RCC Clocks Frequency Structure
+  */
+typedef struct
+{
+  uint32_t SYSCLK_Frequency;        /*!< SYSCLK clock frequency */
+  uint32_t HCLK_Frequency;          /*!< HCLK clock frequency */
+  uint32_t PCLK1_Frequency;         /*!< PCLK1 clock frequency */
+  uint32_t PCLK2_Frequency;         /*!< PCLK2 clock frequency */
+} LL_RCC_ClocksTypeDef;
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
+  * @{
+  */
+
+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
+  * @brief    Defines used to adapt values of different oscillators
+  * @note     These values could be modified in the user environment according to 
+  *           HW set-up.
+  * @{
+  */
+#if !defined  (HSE_VALUE)
+#define HSE_VALUE    25000000U  /*!< Value of the HSE oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined  (HSI_VALUE)
+#define HSI_VALUE    16000000U  /*!< Value of the HSI oscillator in Hz */
+#endif /* HSI_VALUE */
+
+#if !defined  (LSE_VALUE)
+#define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */
+#endif /* LSE_VALUE */
+
+#if !defined  (LSI_VALUE)
+#define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */
+#endif /* LSI_VALUE */
+
+#if !defined  (EXTERNAL_CLOCK_VALUE)
+#define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
+#endif /* EXTERNAL_CLOCK_VALUE */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_RCC_WriteReg function
+  * @{
+  */
+#define LL_RCC_CIR_LSIRDYC                RCC_CIR_LSIRDYC     /*!< LSI Ready Interrupt Clear */
+#define LL_RCC_CIR_LSERDYC                RCC_CIR_LSERDYC     /*!< LSE Ready Interrupt Clear */
+#define LL_RCC_CIR_HSIRDYC                RCC_CIR_HSIRDYC     /*!< HSI Ready Interrupt Clear */
+#define LL_RCC_CIR_HSERDYC                RCC_CIR_HSERDYC     /*!< HSE Ready Interrupt Clear */
+#define LL_RCC_CIR_PLLRDYC                RCC_CIR_PLLRDYC     /*!< PLL Ready Interrupt Clear */
+#if defined(RCC_PLLI2S_SUPPORT)
+#define LL_RCC_CIR_PLLI2SRDYC             RCC_CIR_PLLI2SRDYC  /*!< PLLI2S Ready Interrupt Clear */
+#endif /* RCC_PLLI2S_SUPPORT */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_CIR_PLLSAIRDYC             RCC_CIR_PLLSAIRDYC  /*!< PLLSAI Ready Interrupt Clear */
+#endif /* RCC_PLLSAI_SUPPORT */
+#define LL_RCC_CIR_CSSC                   RCC_CIR_CSSC        /*!< Clock Security System Interrupt Clear */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_RCC_ReadReg function
+  * @{
+  */
+#define LL_RCC_CIR_LSIRDYF                RCC_CIR_LSIRDYF     /*!< LSI Ready Interrupt flag */
+#define LL_RCC_CIR_LSERDYF                RCC_CIR_LSERDYF     /*!< LSE Ready Interrupt flag */
+#define LL_RCC_CIR_HSIRDYF                RCC_CIR_HSIRDYF     /*!< HSI Ready Interrupt flag */
+#define LL_RCC_CIR_HSERDYF                RCC_CIR_HSERDYF     /*!< HSE Ready Interrupt flag */
+#define LL_RCC_CIR_PLLRDYF                RCC_CIR_PLLRDYF     /*!< PLL Ready Interrupt flag */
+#if defined(RCC_PLLI2S_SUPPORT)
+#define LL_RCC_CIR_PLLI2SRDYF             RCC_CIR_PLLI2SRDYF  /*!< PLLI2S Ready Interrupt flag */
+#endif /* RCC_PLLI2S_SUPPORT */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_CIR_PLLSAIRDYF             RCC_CIR_PLLSAIRDYF  /*!< PLLSAI Ready Interrupt flag */
+#endif /* RCC_PLLSAI_SUPPORT */
+#define LL_RCC_CIR_CSSF                   RCC_CIR_CSSF        /*!< Clock Security System Interrupt flag */
+#define LL_RCC_CSR_LPWRRSTF                RCC_CSR_LPWRRSTF   /*!< Low-Power reset flag */
+#define LL_RCC_CSR_PINRSTF                 RCC_CSR_PINRSTF    /*!< PIN reset flag */
+#define LL_RCC_CSR_PORRSTF                 RCC_CSR_PORRSTF    /*!< POR/PDR reset flag */
+#define LL_RCC_CSR_SFTRSTF                 RCC_CSR_SFTRSTF    /*!< Software Reset flag */
+#define LL_RCC_CSR_IWDGRSTF                RCC_CSR_IWDGRSTF   /*!< Independent Watchdog reset flag */
+#define LL_RCC_CSR_WWDGRSTF                RCC_CSR_WWDGRSTF   /*!< Window watchdog reset flag */
+#if defined(RCC_CSR_BORRSTF)
+#define LL_RCC_CSR_BORRSTF                 RCC_CSR_BORRSTF    /*!< BOR reset flag */
+#endif /* RCC_CSR_BORRSTF */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_RCC_ReadReg and  LL_RCC_WriteReg functions
+  * @{
+  */
+#define LL_RCC_CIR_LSIRDYIE               RCC_CIR_LSIRDYIE      /*!< LSI Ready Interrupt Enable */
+#define LL_RCC_CIR_LSERDYIE               RCC_CIR_LSERDYIE      /*!< LSE Ready Interrupt Enable */
+#define LL_RCC_CIR_HSIRDYIE               RCC_CIR_HSIRDYIE      /*!< HSI Ready Interrupt Enable */
+#define LL_RCC_CIR_HSERDYIE               RCC_CIR_HSERDYIE      /*!< HSE Ready Interrupt Enable */
+#define LL_RCC_CIR_PLLRDYIE               RCC_CIR_PLLRDYIE      /*!< PLL Ready Interrupt Enable */
+#if defined(RCC_PLLI2S_SUPPORT)
+#define LL_RCC_CIR_PLLI2SRDYIE            RCC_CIR_PLLI2SRDYIE   /*!< PLLI2S Ready Interrupt Enable */
+#endif /* RCC_PLLI2S_SUPPORT */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_CIR_PLLSAIRDYIE            RCC_CIR_PLLSAIRDYIE   /*!< PLLSAI Ready Interrupt Enable */
+#endif /* RCC_PLLSAI_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI    /*!< HSI selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE    /*!< HSE selection as system clock */
+#define LL_RCC_SYS_CLKSOURCE_PLL           RCC_CFGR_SW_PLL    /*!< PLL selection as system clock */
+#if defined(RCC_CFGR_SW_PLLR)
+#define LL_RCC_SYS_CLKSOURCE_PLLR          RCC_CFGR_SW_PLLR   /*!< PLLR selection as system clock */
+#endif /* RCC_CFGR_SW_PLLR */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status
+  * @{
+  */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL    RCC_CFGR_SWS_PLL   /*!< PLL used as system clock */
+#if defined(RCC_PLLR_SYSCLK_SUPPORT)
+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR   RCC_CFGR_SWS_PLLR  /*!< PLLR used as system clock */
+#endif /* RCC_PLLR_SYSCLK_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_SYSCLK_DIV  AHB prescaler
+  * @{
+  */
+#define LL_RCC_SYSCLK_DIV_1                RCC_CFGR_HPRE_DIV1   /*!< SYSCLK not divided */
+#define LL_RCC_SYSCLK_DIV_2                RCC_CFGR_HPRE_DIV2   /*!< SYSCLK divided by 2 */
+#define LL_RCC_SYSCLK_DIV_4                RCC_CFGR_HPRE_DIV4   /*!< SYSCLK divided by 4 */
+#define LL_RCC_SYSCLK_DIV_8                RCC_CFGR_HPRE_DIV8   /*!< SYSCLK divided by 8 */
+#define LL_RCC_SYSCLK_DIV_16               RCC_CFGR_HPRE_DIV16  /*!< SYSCLK divided by 16 */
+#define LL_RCC_SYSCLK_DIV_64               RCC_CFGR_HPRE_DIV64  /*!< SYSCLK divided by 64 */
+#define LL_RCC_SYSCLK_DIV_128              RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
+#define LL_RCC_SYSCLK_DIV_256              RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
+#define LL_RCC_SYSCLK_DIV_512              RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)
+  * @{
+  */
+#define LL_RCC_APB1_DIV_1                  RCC_CFGR_PPRE1_DIV1  /*!< HCLK not divided */
+#define LL_RCC_APB1_DIV_2                  RCC_CFGR_PPRE1_DIV2  /*!< HCLK divided by 2 */
+#define LL_RCC_APB1_DIV_4                  RCC_CFGR_PPRE1_DIV4  /*!< HCLK divided by 4 */
+#define LL_RCC_APB1_DIV_8                  RCC_CFGR_PPRE1_DIV8  /*!< HCLK divided by 8 */
+#define LL_RCC_APB1_DIV_16                 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_APB2_DIV  APB high-speed prescaler (APB2)
+  * @{
+  */
+#define LL_RCC_APB2_DIV_1                  RCC_CFGR_PPRE2_DIV1  /*!< HCLK not divided */
+#define LL_RCC_APB2_DIV_2                  RCC_CFGR_PPRE2_DIV2  /*!< HCLK divided by 2 */
+#define LL_RCC_APB2_DIV_4                  RCC_CFGR_PPRE2_DIV4  /*!< HCLK divided by 4 */
+#define LL_RCC_APB2_DIV_8                  RCC_CFGR_PPRE2_DIV8  /*!< HCLK divided by 8 */
+#define LL_RCC_APB2_DIV_16                 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCOxSOURCE  MCO source selection
+  * @{
+  */
+#define LL_RCC_MCO1SOURCE_HSI              (uint32_t)(RCC_CFGR_MCO1|0x00000000U)                    /*!< HSI selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_LSE              (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U))       /*!< LSE selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_HSE              (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U))       /*!< HSE selection as MCO1 source */
+#define LL_RCC_MCO1SOURCE_PLLCLK           (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U))       /*!< PLLCLK selection as MCO1 source */
+#if defined(RCC_CFGR_MCO2)
+#define LL_RCC_MCO2SOURCE_SYSCLK           (uint32_t)(RCC_CFGR_MCO2|0x00000000U)                    /*!< SYSCLK selection as MCO2 source */
+#define LL_RCC_MCO2SOURCE_PLLI2S           (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U))       /*!< PLLI2S selection as MCO2 source */
+#define LL_RCC_MCO2SOURCE_HSE              (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U))       /*!< HSE selection as MCO2 source */
+#define LL_RCC_MCO2SOURCE_PLLCLK           (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U))       /*!< PLLCLK selection as MCO2 source */
+#endif /* RCC_CFGR_MCO2 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_MCOx_DIV  MCO prescaler
+  * @{
+  */
+#define LL_RCC_MCO1_DIV_1                  (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U)                       /*!< MCO1 not divided */
+#define LL_RCC_MCO1_DIV_2                  (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U))       /*!< MCO1 divided by 2 */
+#define LL_RCC_MCO1_DIV_3                  (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U))       /*!< MCO1 divided by 3 */
+#define LL_RCC_MCO1_DIV_4                  (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U))       /*!< MCO1 divided by 4 */
+#define LL_RCC_MCO1_DIV_5                  (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U))         /*!< MCO1 divided by 5 */
+#if defined(RCC_CFGR_MCO2PRE)
+#define LL_RCC_MCO2_DIV_1                  (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U)                       /*!< MCO2 not divided */
+#define LL_RCC_MCO2_DIV_2                  (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U))       /*!< MCO2 divided by 2 */
+#define LL_RCC_MCO2_DIV_3                  (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U))       /*!< MCO2 divided by 3 */
+#define LL_RCC_MCO2_DIV_4                  (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U))       /*!< MCO2 divided by 4 */
+#define LL_RCC_MCO2_DIV_5                  (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U))         /*!< MCO2 divided by 5 */
+#endif /* RCC_CFGR_MCO2PRE */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_RTC_HSEDIV  HSE prescaler for RTC clock
+  * @{
+  */
+#define LL_RCC_RTC_NOCLOCK                  0x00000000U             /*!< HSE not divided */
+#define LL_RCC_RTC_HSE_DIV_2                RCC_CFGR_RTCPRE_1       /*!< HSE clock divided by 2 */
+#define LL_RCC_RTC_HSE_DIV_3                (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 3 */
+#define LL_RCC_RTC_HSE_DIV_4                RCC_CFGR_RTCPRE_2       /*!< HSE clock divided by 4 */
+#define LL_RCC_RTC_HSE_DIV_5                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 5 */
+#define LL_RCC_RTC_HSE_DIV_6                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 6 */
+#define LL_RCC_RTC_HSE_DIV_7                (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 7 */
+#define LL_RCC_RTC_HSE_DIV_8                RCC_CFGR_RTCPRE_3       /*!< HSE clock divided by 8 */
+#define LL_RCC_RTC_HSE_DIV_9                (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 9 */
+#define LL_RCC_RTC_HSE_DIV_10               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 10 */
+#define LL_RCC_RTC_HSE_DIV_11               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 11 */
+#define LL_RCC_RTC_HSE_DIV_12               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 12 */
+#define LL_RCC_RTC_HSE_DIV_13               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 13 */
+#define LL_RCC_RTC_HSE_DIV_14               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 14 */
+#define LL_RCC_RTC_HSE_DIV_15               (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 15 */
+#define LL_RCC_RTC_HSE_DIV_16               RCC_CFGR_RTCPRE_4       /*!< HSE clock divided by 16 */
+#define LL_RCC_RTC_HSE_DIV_17               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 17 */
+#define LL_RCC_RTC_HSE_DIV_18               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 18 */
+#define LL_RCC_RTC_HSE_DIV_19               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 19 */
+#define LL_RCC_RTC_HSE_DIV_20               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 20 */
+#define LL_RCC_RTC_HSE_DIV_21               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 21 */
+#define LL_RCC_RTC_HSE_DIV_22               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 22 */
+#define LL_RCC_RTC_HSE_DIV_23               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 23 */
+#define LL_RCC_RTC_HSE_DIV_24               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)       /*!< HSE clock divided by 24 */
+#define LL_RCC_RTC_HSE_DIV_25               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 25 */
+#define LL_RCC_RTC_HSE_DIV_26               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 26 */
+#define LL_RCC_RTC_HSE_DIV_27               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 27 */
+#define LL_RCC_RTC_HSE_DIV_28               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)       /*!< HSE clock divided by 28 */
+#define LL_RCC_RTC_HSE_DIV_29               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 29 */
+#define LL_RCC_RTC_HSE_DIV_30               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)       /*!< HSE clock divided by 30 */
+#define LL_RCC_RTC_HSE_DIV_31               (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)       /*!< HSE clock divided by 31 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
+  * @{
+  */
+#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */
+#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+#if defined(FMPI2C1)
+/** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE  Peripheral FMPI2C clock source selection
+  * @{
+  */
+#define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1        0x00000000U               /*!< PCLK1 clock used as FMPI2C1 clock source */
+#define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK       RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */
+#define LL_RCC_FMPI2C1_CLKSOURCE_HSI          RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */
+/**
+  * @}
+  */
+#endif /* FMPI2C1 */
+
+#if defined(LPTIM1)
+/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE  Peripheral LPTIM clock source selection
+  * @{
+  */
+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1       0x00000000U                 /*!< PCLK1 clock used as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_HSI         RCC_DCKCFGR2_LPTIM1SEL_0    /*!< LSI oscillator clock used as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSI         RCC_DCKCFGR2_LPTIM1SEL_1    /*!< HSI oscillator clock used as LPTIM1 clock */
+#define LL_RCC_LPTIM1_CLKSOURCE_LSE         (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0)      /*!< LSE oscillator clock used as LPTIM1 clock */
+/**
+  * @}
+  */
+#endif /* LPTIM1 */
+
+#if defined(SAI1)
+/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection
+  * @{
+  */
+#if defined(RCC_DCKCFGR_SAI1SRC)
+#define LL_RCC_SAI1_CLKSOURCE_PLLSAI       (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U)                     /*!< PLLSAI clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLLI2S       (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16))   /*!< PLLI2S clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PLL          (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16))   /*!< PLL clock used as SAI1 clock source */
+#define LL_RCC_SAI1_CLKSOURCE_PIN          (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16))     /*!< External pin clock used as SAI1 clock source */
+#endif /* RCC_DCKCFGR_SAI1SRC */
+#if defined(RCC_DCKCFGR_SAI2SRC)
+#define LL_RCC_SAI2_CLKSOURCE_PLLSAI       (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U)                     /*!< PLLSAI clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLLI2S       (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16))   /*!< PLLI2S clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLL          (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16))   /*!< PLL clock used as SAI2 clock source */
+#define LL_RCC_SAI2_CLKSOURCE_PLLSRC       (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16))     /*!< PLL Main clock used as SAI2 clock source */
+#endif /* RCC_DCKCFGR_SAI2SRC */
+#if defined(RCC_DCKCFGR_SAI1ASRC)
+#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
+#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U)                    /*!< PLLI2S clock used as SAI1 block A clock source */
+#define LL_RCC_SAI1_A_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */
+#define LL_RCC_SAI1_A_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */
+#define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16))   /*!< PLL Main clock used as SAI1 block A clock source */
+#else
+#define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U)                    /*!< PLLSAI clock used as SAI1 block A clock source */
+#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */
+#define LL_RCC_SAI1_A_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */
+#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
+#endif /* RCC_DCKCFGR_SAI1ASRC */
+#if defined(RCC_DCKCFGR_SAI1BSRC)
+#if defined(RCC_SAI1B_PLLSOURCE_SUPPORT)
+#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U)                    /*!< PLLI2S clock used as SAI1 block B clock source */
+#define LL_RCC_SAI1_B_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */
+#define LL_RCC_SAI1_B_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */
+#define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16))   /*!< PLL Main clock used as SAI1 block B clock source */
+#else
+#define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U)                    /*!< PLLSAI clock used as SAI1 block B clock source */
+#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */
+#define LL_RCC_SAI1_B_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */
+#endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */
+#endif /* RCC_DCKCFGR_SAI1BSRC */
+/**
+  * @}
+  */
+#endif /* SAI1 */
+
+#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
+/** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE  Peripheral SDIO clock source selection
+  * @{
+  */
+#define LL_RCC_SDIO_CLKSOURCE_PLL48CLK       0x00000000U                 /*!< PLL 48M domain clock used as SDIO clock */
+#if defined(RCC_DCKCFGR_SDIOSEL)
+#define LL_RCC_SDIO_CLKSOURCE_SYSCLK         RCC_DCKCFGR_SDIOSEL         /*!< System clock clock used as SDIO clock */
+#else
+#define LL_RCC_SDIO_CLKSOURCE_SYSCLK         RCC_DCKCFGR2_SDIOSEL        /*!< System clock clock used as SDIO clock */
+#endif /* RCC_DCKCFGR_SDIOSEL */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
+
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI clock source selection
+  * @{
+  */
+#define LL_RCC_DSI_CLKSOURCE_PHY          0x00000000U                       /*!< DSI-PHY clock used as DSI byte lane clock source */
+#define LL_RCC_DSI_CLKSOURCE_PLL          RCC_DCKCFGR_DSISEL                /*!< PLL clock used as DSI byte lane clock source */
+/**
+  * @}
+  */
+#endif /* DSI */
+
+#if defined(CEC)
+/** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection
+  * @{
+  */
+#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488    0x00000000U                /*!< HSI oscillator clock divided by 488 used as CEC clock */
+#define LL_RCC_CEC_CLKSOURCE_LSE           RCC_DCKCFGR2_CECSEL        /*!< LSE oscillator clock used as CEC clock */
+/**
+  * @}
+  */
+#endif /* CEC */
+
+/** @defgroup RCC_LL_EC_I2S1_CLKSOURCE  Peripheral I2S clock source selection
+  * @{
+  */
+#if defined(RCC_CFGR_I2SSRC)
+#define LL_RCC_I2S1_CLKSOURCE_PLLI2S     0x00000000U                /*!< I2S oscillator clock used as I2S1 clock */
+#define LL_RCC_I2S1_CLKSOURCE_PIN        RCC_CFGR_I2SSRC            /*!< External pin clock used as I2S1 clock */
+#endif /* RCC_CFGR_I2SSRC */
+#if defined(RCC_DCKCFGR_I2SSRC)
+#define LL_RCC_I2S1_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U)                    /*!< PLL clock used as I2S1 clock source */
+#define LL_RCC_I2S1_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16))   /*!< External pin used as I2S1 clock source */
+#define LL_RCC_I2S1_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16))   /*!< PLL Main clock used as I2S1 clock source */
+#endif /* RCC_DCKCFGR_I2SSRC */
+#if defined(RCC_DCKCFGR_I2S1SRC)
+#define LL_RCC_I2S1_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U)                   /*!< PLLI2S clock used as I2S1 clock source */
+#define LL_RCC_I2S1_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */
+#define LL_RCC_I2S1_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */
+#define LL_RCC_I2S1_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16))   /*!< PLL Main clock used as I2S1 clock source */
+#endif /* RCC_DCKCFGR_I2S1SRC */
+#if defined(RCC_DCKCFGR_I2S2SRC)
+#define LL_RCC_I2S2_CLKSOURCE_PLLI2S     (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U)                   /*!< PLLI2S clock used as I2S2 clock source */
+#define LL_RCC_I2S2_CLKSOURCE_PIN        (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */
+#define LL_RCC_I2S2_CLKSOURCE_PLL        (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */
+#define LL_RCC_I2S2_CLKSOURCE_PLLSRC     (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16))   /*!< PLL Main clock used as I2S2 clock source */
+#endif /* RCC_DCKCFGR_I2S2SRC */
+/**
+  * @}
+  */
+
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+/** @defgroup RCC_LL_EC_CK48M_CLKSOURCE  Peripheral 48Mhz domain clock source selection
+  * @{
+  */
+#if defined(RCC_DCKCFGR_CK48MSEL)
+#define LL_RCC_CK48M_CLKSOURCE_PLL         0x00000000U                /*!< PLL oscillator clock used as 48Mhz domain clock */
+#define LL_RCC_CK48M_CLKSOURCE_PLLSAI      RCC_DCKCFGR_CK48MSEL       /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
+#endif /* RCC_DCKCFGR_CK48MSEL */
+#if defined(RCC_DCKCFGR2_CK48MSEL)
+#define LL_RCC_CK48M_CLKSOURCE_PLL         0x00000000U                /*!< PLL oscillator clock used as 48Mhz domain clock */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_CK48M_CLKSOURCE_PLLSAI      RCC_DCKCFGR2_CK48MSEL      /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
+#endif /* RCC_PLLSAI_SUPPORT */
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+#define LL_RCC_CK48M_CLKSOURCE_PLLI2S      RCC_DCKCFGR2_CK48MSEL      /*!< PLLI2S oscillator clock used as 48Mhz domain clock */
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+#endif /* RCC_DCKCFGR2_CK48MSEL */
+/**
+  * @}
+  */
+
+#if defined(RNG)
+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection
+  * @{
+  */
+#define LL_RCC_RNG_CLKSOURCE_PLL          LL_RCC_CK48M_CLKSOURCE_PLL        /*!< PLL clock used as RNG clock source */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_RNG_CLKSOURCE_PLLSAI       LL_RCC_CK48M_CLKSOURCE_PLLSAI     /*!< PLLSAI clock used as RNG clock source */
+#endif /* RCC_PLLSAI_SUPPORT */
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+#define LL_RCC_RNG_CLKSOURCE_PLLI2S       LL_RCC_CK48M_CLKSOURCE_PLLI2S     /*!< PLLI2S clock used as RNG clock source */
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+/**
+  * @}
+  */
+#endif /* RNG */
+
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection
+  * @{
+  */
+#define LL_RCC_USB_CLKSOURCE_PLL          LL_RCC_CK48M_CLKSOURCE_PLL        /*!< PLL clock used as USB clock source */
+#if defined(RCC_PLLSAI_SUPPORT)
+#define LL_RCC_USB_CLKSOURCE_PLLSAI       LL_RCC_CK48M_CLKSOURCE_PLLSAI     /*!< PLLSAI clock used as USB clock source */
+#endif /* RCC_PLLSAI_SUPPORT */
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+#define LL_RCC_USB_CLKSOURCE_PLLI2S       LL_RCC_CK48M_CLKSOURCE_PLLI2S     /*!< PLLI2S clock used as USB clock source */
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+/**
+  * @}
+  */
+#endif /* USB_OTG_FS || USB_OTG_HS */
+
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+
+#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
+/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE  Peripheral DFSDM Audio clock source selection
+  * @{
+  */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1     (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U)                      /*!< I2S1 clock used as DFSDM1 Audio clock source */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2     (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */
+#if defined(DFSDM2_Channel0)
+#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1     (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U)                      /*!< I2S1 clock used as DFSDM2 Audio clock source */
+#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2     (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */
+#endif /* DFSDM2_Channel0 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE  Peripheral DFSDM clock source selection
+  * @{
+  */
+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          0x00000000U                /*!< PCLK2 clock used as DFSDM1 clock */
+#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         RCC_DCKCFGR_CKDFSDM1SEL    /*!< System clock used as DFSDM1 clock */
+#if defined(DFSDM2_Channel0)
+#define LL_RCC_DFSDM2_CLKSOURCE_PCLK2          0x00000000U                /*!< PCLK2 clock used as DFSDM2 clock */
+#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK         RCC_DCKCFGR_CKDFSDM1SEL    /*!< System clock used as DFSDM2 clock */
+#endif /* DFSDM2_Channel0 */
+/**
+  * @}
+  */
+#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
+
+#if defined(FMPI2C1)
+/** @defgroup RCC_LL_EC_FMPI2C1  Peripheral FMPI2C get clock source
+  * @{
+  */
+#define LL_RCC_FMPI2C1_CLKSOURCE              RCC_DCKCFGR2_FMPI2C1SEL  /*!< FMPI2C1 Clock source selection */
+/**
+  * @}
+  */
+#endif /* FMPI2C1 */
+
+#if defined(SPDIFRX)
+/** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE  Peripheral SPDIFRX clock source selection
+  * @{
+  */
+#define LL_RCC_SPDIFRX1_CLKSOURCE_PLL          0x00000000U             /*!< PLL clock used as SPDIFRX clock source */
+#define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S       RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */
+/**
+  * @}
+  */
+#endif /* SPDIFRX */
+
+#if defined(LPTIM1)
+/** @defgroup RCC_LL_EC_LPTIM1  Peripheral LPTIM get clock source
+  * @{
+  */
+#define LL_RCC_LPTIM1_CLKSOURCE            RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */
+/**
+  * @}
+  */
+#endif /* LPTIM1 */
+
+#if defined(SAI1)
+/** @defgroup RCC_LL_EC_SAIx  Peripheral SAI get clock source
+  * @{
+  */
+#if defined(RCC_DCKCFGR_SAI1ASRC)
+#define LL_RCC_SAI1_A_CLKSOURCE            RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */
+#endif /* RCC_DCKCFGR_SAI1ASRC */
+#if defined(RCC_DCKCFGR_SAI1BSRC)
+#define LL_RCC_SAI1_B_CLKSOURCE            RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */
+#endif /* RCC_DCKCFGR_SAI1BSRC */
+#if defined(RCC_DCKCFGR_SAI1SRC)
+#define LL_RCC_SAI1_CLKSOURCE              RCC_DCKCFGR_SAI1SRC  /*!< SAI1 Clock source selection */
+#endif /* RCC_DCKCFGR_SAI1SRC */
+#if defined(RCC_DCKCFGR_SAI2SRC)
+#define LL_RCC_SAI2_CLKSOURCE              RCC_DCKCFGR_SAI2SRC  /*!< SAI2 Clock source selection */
+#endif /* RCC_DCKCFGR_SAI2SRC */
+/**
+  * @}
+  */
+#endif /* SAI1 */
+
+#if defined(SDIO)
+/** @defgroup RCC_LL_EC_SDIOx  Peripheral SDIO get clock source
+  * @{
+  */
+#if defined(RCC_DCKCFGR_SDIOSEL)
+#define LL_RCC_SDIO_CLKSOURCE            RCC_DCKCFGR_SDIOSEL   /*!< SDIO Clock source selection */
+#elif defined(RCC_DCKCFGR2_SDIOSEL)
+#define LL_RCC_SDIO_CLKSOURCE            RCC_DCKCFGR2_SDIOSEL  /*!< SDIO Clock source selection */
+#else
+#define LL_RCC_SDIO_CLKSOURCE            RCC_PLLCFGR_PLLQ      /*!< SDIO Clock source selection */
+#endif
+/**
+  * @}
+  */
+#endif /* SDIO */
+
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+/** @defgroup RCC_LL_EC_CK48M  Peripheral CK48M get clock source
+  * @{
+  */
+#if defined(RCC_DCKCFGR_CK48MSEL)
+#define LL_RCC_CK48M_CLKSOURCE             RCC_DCKCFGR_CK48MSEL  /*!< CK48M Domain clock source selection */
+#endif /* RCC_DCKCFGR_CK48MSEL */
+#if defined(RCC_DCKCFGR2_CK48MSEL)
+#define LL_RCC_CK48M_CLKSOURCE             RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */
+#endif /* RCC_DCKCFGR_CK48MSEL */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+
+#if defined(RNG)
+/** @defgroup RCC_LL_EC_RNG  Peripheral RNG get clock source
+  * @{
+  */
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+#define LL_RCC_RNG_CLKSOURCE               LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */
+#else
+#define LL_RCC_RNG_CLKSOURCE               RCC_PLLCFGR_PLLQ       /*!< RNG Clock source selection */
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+/**
+  * @}
+  */
+#endif /* RNG */
+
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+/** @defgroup RCC_LL_EC_USB  Peripheral USB get clock source
+  * @{
+  */
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+#define LL_RCC_USB_CLKSOURCE               LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */
+#else
+#define LL_RCC_USB_CLKSOURCE               RCC_PLLCFGR_PLLQ       /*!< USB Clock source selection */
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+/**
+  * @}
+  */
+#endif /* USB_OTG_FS || USB_OTG_HS */
+
+#if defined(CEC)
+/** @defgroup RCC_LL_EC_CEC  Peripheral CEC get clock source
+  * @{
+  */
+#define LL_RCC_CEC_CLKSOURCE               RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */
+/**
+  * @}
+  */
+#endif /* CEC */
+
+/** @defgroup RCC_LL_EC_I2S1  Peripheral I2S get clock source
+  * @{
+  */
+#if defined(RCC_CFGR_I2SSRC)
+#define LL_RCC_I2S1_CLKSOURCE              RCC_CFGR_I2SSRC     /*!< I2S1 Clock source selection */
+#endif /* RCC_CFGR_I2SSRC */
+#if defined(RCC_DCKCFGR_I2SSRC)
+#define LL_RCC_I2S1_CLKSOURCE              RCC_DCKCFGR_I2SSRC  /*!< I2S1 Clock source selection */
+#endif /* RCC_DCKCFGR_I2SSRC */
+#if defined(RCC_DCKCFGR_I2S1SRC)
+#define LL_RCC_I2S1_CLKSOURCE              RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */
+#endif /* RCC_DCKCFGR_I2S1SRC */
+#if defined(RCC_DCKCFGR_I2S2SRC)
+#define LL_RCC_I2S2_CLKSOURCE              RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */
+#endif /* RCC_DCKCFGR_I2S2SRC */
+/**
+  * @}
+  */
+
+#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
+/** @defgroup RCC_LL_EC_DFSDM_AUDIO  Peripheral DFSDM Audio get clock source
+  * @{
+  */
+#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE      RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */
+#if defined(DFSDM2_Channel0)
+#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE      RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */
+#endif /* DFSDM2_Channel0 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_DFSDM  Peripheral DFSDM get clock source
+  * @{
+  */
+#define LL_RCC_DFSDM1_CLKSOURCE            RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */
+#if defined(DFSDM2_Channel0)
+#define LL_RCC_DFSDM2_CLKSOURCE            RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */
+#endif /* DFSDM2_Channel0 */
+/**
+  * @}
+  */
+#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
+
+#if defined(SPDIFRX)
+/** @defgroup RCC_LL_EC_SPDIFRX  Peripheral SPDIFRX get clock source
+  * @{
+  */
+#define LL_RCC_SPDIFRX1_CLKSOURCE          RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */
+/**
+  * @}
+  */
+#endif /* SPDIFRX */
+
+#if defined(DSI)
+/** @defgroup RCC_LL_EC_DSI  Peripheral DSI get clock source
+  * @{
+  */
+#define LL_RCC_DSI_CLKSOURCE               RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */
+/**
+  * @}
+  */
+#endif /* DSI */
+
+#if defined(LTDC)
+/** @defgroup RCC_LL_EC_LTDC  Peripheral LTDC get clock source
+  * @{
+  */
+#define LL_RCC_LTDC_CLKSOURCE              RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */
+/**
+  * @}
+  */
+#endif /* LTDC */
+
+
+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection
+  * @{
+  */
+#define LL_RCC_RTC_CLKSOURCE_NONE          0x00000000U                   /*!< No clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSE           RCC_BDCR_RTCSEL_0       /*!< LSE oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_LSI           RCC_BDCR_RTCSEL_1       /*!< LSI oscillator clock used as RTC clock */
+#define LL_RCC_RTC_CLKSOURCE_HSE           RCC_BDCR_RTCSEL         /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */
+/**
+  * @}
+  */
+
+#if defined(RCC_DCKCFGR_TIMPRE)
+/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER  Timers clocks prescalers selection
+  * @{
+  */
+#define LL_RCC_TIM_PRESCALER_TWICE          0x00000000U                  /*!< Timers clock to twice PCLK */
+#define LL_RCC_TIM_PRESCALER_FOUR_TIMES     RCC_DCKCFGR_TIMPRE          /*!< Timers clock to four time PCLK */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_TIMPRE */
+
+/** @defgroup RCC_LL_EC_PLLSOURCE  PLL, PLLI2S and PLLSAI entry clock source
+  * @{
+  */
+#define LL_RCC_PLLSOURCE_HSI               RCC_PLLCFGR_PLLSRC_HSI  /*!< HSI16 clock selected as PLL entry clock source */
+#define LL_RCC_PLLSOURCE_HSE               RCC_PLLCFGR_PLLSRC_HSE  /*!< HSE clock selected as PLL entry clock source */
+#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
+#define LL_RCC_PLLI2SSOURCE_PIN            (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U)  /*!< I2S External pin input clock selected as PLLI2S entry clock source */
+#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLM_DIV  PLL, PLLI2S and PLLSAI division factor
+  * @{
+  */
+#define LL_RCC_PLLM_DIV_2                  (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */
+#define LL_RCC_PLLM_DIV_3                  (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */
+#define LL_RCC_PLLM_DIV_4                  (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */
+#define LL_RCC_PLLM_DIV_5                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */
+#define LL_RCC_PLLM_DIV_6                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */
+#define LL_RCC_PLLM_DIV_7                  (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */
+#define LL_RCC_PLLM_DIV_8                  (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */
+#define LL_RCC_PLLM_DIV_9                  (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */
+#define LL_RCC_PLLM_DIV_10                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */
+#define LL_RCC_PLLM_DIV_11                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */
+#define LL_RCC_PLLM_DIV_12                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */
+#define LL_RCC_PLLM_DIV_13                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */
+#define LL_RCC_PLLM_DIV_14                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */
+#define LL_RCC_PLLM_DIV_15                 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */
+#define LL_RCC_PLLM_DIV_16                 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */
+#define LL_RCC_PLLM_DIV_17                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */
+#define LL_RCC_PLLM_DIV_18                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */
+#define LL_RCC_PLLM_DIV_19                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */
+#define LL_RCC_PLLM_DIV_20                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */
+#define LL_RCC_PLLM_DIV_21                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */
+#define LL_RCC_PLLM_DIV_22                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */
+#define LL_RCC_PLLM_DIV_23                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */
+#define LL_RCC_PLLM_DIV_24                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */
+#define LL_RCC_PLLM_DIV_25                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */
+#define LL_RCC_PLLM_DIV_26                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */
+#define LL_RCC_PLLM_DIV_27                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */
+#define LL_RCC_PLLM_DIV_28                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */
+#define LL_RCC_PLLM_DIV_29                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */
+#define LL_RCC_PLLM_DIV_30                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */
+#define LL_RCC_PLLM_DIV_31                 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */
+#define LL_RCC_PLLM_DIV_32                 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */
+#define LL_RCC_PLLM_DIV_33                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */
+#define LL_RCC_PLLM_DIV_34                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */
+#define LL_RCC_PLLM_DIV_35                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */
+#define LL_RCC_PLLM_DIV_36                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */
+#define LL_RCC_PLLM_DIV_37                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */
+#define LL_RCC_PLLM_DIV_38                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */
+#define LL_RCC_PLLM_DIV_39                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */
+#define LL_RCC_PLLM_DIV_40                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */
+#define LL_RCC_PLLM_DIV_41                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */
+#define LL_RCC_PLLM_DIV_42                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */
+#define LL_RCC_PLLM_DIV_43                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */
+#define LL_RCC_PLLM_DIV_44                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */
+#define LL_RCC_PLLM_DIV_45                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */
+#define LL_RCC_PLLM_DIV_46                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */
+#define LL_RCC_PLLM_DIV_47                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */
+#define LL_RCC_PLLM_DIV_48                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */
+#define LL_RCC_PLLM_DIV_49                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */
+#define LL_RCC_PLLM_DIV_50                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */
+#define LL_RCC_PLLM_DIV_51                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */
+#define LL_RCC_PLLM_DIV_52                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */
+#define LL_RCC_PLLM_DIV_53                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */
+#define LL_RCC_PLLM_DIV_54                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */
+#define LL_RCC_PLLM_DIV_55                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */
+#define LL_RCC_PLLM_DIV_56                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */
+#define LL_RCC_PLLM_DIV_57                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */
+#define LL_RCC_PLLM_DIV_58                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */
+#define LL_RCC_PLLM_DIV_59                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */
+#define LL_RCC_PLLM_DIV_60                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */
+#define LL_RCC_PLLM_DIV_61                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */
+#define LL_RCC_PLLM_DIV_62                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */
+#define LL_RCC_PLLM_DIV_63                 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */
+/**
+  * @}
+  */
+
+#if defined(RCC_PLLCFGR_PLLR)
+/** @defgroup RCC_LL_EC_PLLR_DIV  PLL division factor (PLLR)
+  * @{
+  */
+#define LL_RCC_PLLR_DIV_2                  (RCC_PLLCFGR_PLLR_1)                     /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
+#define LL_RCC_PLLR_DIV_3                  (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
+#define LL_RCC_PLLR_DIV_4                  (RCC_PLLCFGR_PLLR_2)                     /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
+#define LL_RCC_PLLR_DIV_5                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)  /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
+#define LL_RCC_PLLR_DIV_6                  (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)  /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
+#define LL_RCC_PLLR_DIV_7                  (RCC_PLLCFGR_PLLR)                       /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
+/**
+  * @}
+  */
+#endif /* RCC_PLLCFGR_PLLR */
+
+#if defined(RCC_DCKCFGR_PLLDIVR)
+/** @defgroup RCC_LL_EC_PLLDIVR  PLLDIVR division factor (PLLDIVR)
+  * @{
+  */
+#define LL_RCC_PLLDIVR_DIV_1           (RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 1 */
+#define LL_RCC_PLLDIVR_DIV_2           (RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 2 */
+#define LL_RCC_PLLDIVR_DIV_3           (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 3 */
+#define LL_RCC_PLLDIVR_DIV_4           (RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 4 */
+#define LL_RCC_PLLDIVR_DIV_5           (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 5 */
+#define LL_RCC_PLLDIVR_DIV_6           (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 6 */
+#define LL_RCC_PLLDIVR_DIV_7           (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 7 */
+#define LL_RCC_PLLDIVR_DIV_8           (RCC_DCKCFGR_PLLDIVR_3)        /*!< PLL division factor for PLLDIVR output by 8 */
+#define LL_RCC_PLLDIVR_DIV_9           (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 9 */
+#define LL_RCC_PLLDIVR_DIV_10          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 10 */
+#define LL_RCC_PLLDIVR_DIV_11          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 11 */
+#define LL_RCC_PLLDIVR_DIV_12          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 12 */
+#define LL_RCC_PLLDIVR_DIV_13          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 13 */
+#define LL_RCC_PLLDIVR_DIV_14          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 14 */
+#define LL_RCC_PLLDIVR_DIV_15          (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 15 */
+#define LL_RCC_PLLDIVR_DIV_16          (RCC_DCKCFGR_PLLDIVR_4)             /*!< PLL division factor for PLLDIVR output by 16 */
+#define LL_RCC_PLLDIVR_DIV_17          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 17 */
+#define LL_RCC_PLLDIVR_DIV_18          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 18 */
+#define LL_RCC_PLLDIVR_DIV_19          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 19 */
+#define LL_RCC_PLLDIVR_DIV_20          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 20 */
+#define LL_RCC_PLLDIVR_DIV_21          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 21 */
+#define LL_RCC_PLLDIVR_DIV_22          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 22 */
+#define LL_RCC_PLLDIVR_DIV_23          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 23 */
+#define LL_RCC_PLLDIVR_DIV_24          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3)        /*!< PLL division factor for PLLDIVR output by 24 */
+#define LL_RCC_PLLDIVR_DIV_25          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 25 */
+#define LL_RCC_PLLDIVR_DIV_26          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 26 */
+#define LL_RCC_PLLDIVR_DIV_27          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 27 */
+#define LL_RCC_PLLDIVR_DIV_28          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2)        /*!< PLL division factor for PLLDIVR output by 28 */
+#define LL_RCC_PLLDIVR_DIV_29          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 29 */
+#define LL_RCC_PLLDIVR_DIV_30          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)        /*!< PLL division factor for PLLDIVR output by 30 */
+#define LL_RCC_PLLDIVR_DIV_31          (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)        /*!< PLL division factor for PLLDIVR output by 31 */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_PLLDIVR */
+
+/** @defgroup RCC_LL_EC_PLLP_DIV  PLL division factor (PLLP)
+  * @{
+  */
+#define LL_RCC_PLLP_DIV_2                  0x00000000U            /*!< Main PLL division factor for PLLP output by 2 */
+#define LL_RCC_PLLP_DIV_4                  RCC_PLLCFGR_PLLP_0     /*!< Main PLL division factor for PLLP output by 4 */
+#define LL_RCC_PLLP_DIV_6                  RCC_PLLCFGR_PLLP_1     /*!< Main PLL division factor for PLLP output by 6 */
+#define LL_RCC_PLLP_DIV_8                  (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)   /*!< Main PLL division factor for PLLP output by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLQ_DIV  PLL division factor (PLLQ)
+  * @{
+  */
+#define LL_RCC_PLLQ_DIV_2                  RCC_PLLCFGR_PLLQ_1                      /*!< Main PLL division factor for PLLQ output by 2 */
+#define LL_RCC_PLLQ_DIV_3                  (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */
+#define LL_RCC_PLLQ_DIV_4                  RCC_PLLCFGR_PLLQ_2                      /*!< Main PLL division factor for PLLQ output by 4 */
+#define LL_RCC_PLLQ_DIV_5                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */
+#define LL_RCC_PLLQ_DIV_6                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
+#define LL_RCC_PLLQ_DIV_7                  (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */
+#define LL_RCC_PLLQ_DIV_8                  RCC_PLLCFGR_PLLQ_3                      /*!< Main PLL division factor for PLLQ output by 8 */
+#define LL_RCC_PLLQ_DIV_9                  (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */
+#define LL_RCC_PLLQ_DIV_10                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */
+#define LL_RCC_PLLQ_DIV_11                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */
+#define LL_RCC_PLLQ_DIV_12                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */
+#define LL_RCC_PLLQ_DIV_13                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */
+#define LL_RCC_PLLQ_DIV_14                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */
+#define LL_RCC_PLLQ_DIV_15                 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLL_SPRE_SEL  PLL Spread Spectrum Selection
+  * @{
+  */
+#define LL_RCC_SPREAD_SELECT_CENTER        0x00000000U                   /*!< PLL center spread spectrum selection */
+#define LL_RCC_SPREAD_SELECT_DOWN          RCC_SSCGR_SPREADSEL           /*!< PLL down spread spectrum selection */
+/**
+  * @}
+  */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLI2SM  PLLI2SM division factor (PLLI2SM)
+  * @{
+  */
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+#define LL_RCC_PLLI2SM_DIV_2             (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */
+#define LL_RCC_PLLI2SM_DIV_3             (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */
+#define LL_RCC_PLLI2SM_DIV_4             (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */
+#define LL_RCC_PLLI2SM_DIV_5             (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */
+#define LL_RCC_PLLI2SM_DIV_6             (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */
+#define LL_RCC_PLLI2SM_DIV_7             (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */
+#define LL_RCC_PLLI2SM_DIV_8             (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */
+#define LL_RCC_PLLI2SM_DIV_9             (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */
+#define LL_RCC_PLLI2SM_DIV_10            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */
+#define LL_RCC_PLLI2SM_DIV_11            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */
+#define LL_RCC_PLLI2SM_DIV_12            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */
+#define LL_RCC_PLLI2SM_DIV_13            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */
+#define LL_RCC_PLLI2SM_DIV_14            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */
+#define LL_RCC_PLLI2SM_DIV_15            (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */
+#define LL_RCC_PLLI2SM_DIV_16            (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */
+#define LL_RCC_PLLI2SM_DIV_17            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */
+#define LL_RCC_PLLI2SM_DIV_18            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */
+#define LL_RCC_PLLI2SM_DIV_19            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */
+#define LL_RCC_PLLI2SM_DIV_20            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */
+#define LL_RCC_PLLI2SM_DIV_21            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */
+#define LL_RCC_PLLI2SM_DIV_22            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */
+#define LL_RCC_PLLI2SM_DIV_23            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */
+#define LL_RCC_PLLI2SM_DIV_24            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */
+#define LL_RCC_PLLI2SM_DIV_25            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */
+#define LL_RCC_PLLI2SM_DIV_26            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */
+#define LL_RCC_PLLI2SM_DIV_27            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */
+#define LL_RCC_PLLI2SM_DIV_28            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */
+#define LL_RCC_PLLI2SM_DIV_29            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */
+#define LL_RCC_PLLI2SM_DIV_30            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */
+#define LL_RCC_PLLI2SM_DIV_31            (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */
+#define LL_RCC_PLLI2SM_DIV_32            (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */
+#define LL_RCC_PLLI2SM_DIV_33            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */
+#define LL_RCC_PLLI2SM_DIV_34            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */
+#define LL_RCC_PLLI2SM_DIV_35            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */
+#define LL_RCC_PLLI2SM_DIV_36            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */
+#define LL_RCC_PLLI2SM_DIV_37            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */
+#define LL_RCC_PLLI2SM_DIV_38            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */
+#define LL_RCC_PLLI2SM_DIV_39            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */
+#define LL_RCC_PLLI2SM_DIV_40            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */
+#define LL_RCC_PLLI2SM_DIV_41            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */
+#define LL_RCC_PLLI2SM_DIV_42            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */
+#define LL_RCC_PLLI2SM_DIV_43            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */
+#define LL_RCC_PLLI2SM_DIV_44            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */
+#define LL_RCC_PLLI2SM_DIV_45            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */
+#define LL_RCC_PLLI2SM_DIV_46            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */
+#define LL_RCC_PLLI2SM_DIV_47            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */
+#define LL_RCC_PLLI2SM_DIV_48            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */
+#define LL_RCC_PLLI2SM_DIV_49            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */
+#define LL_RCC_PLLI2SM_DIV_50            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */
+#define LL_RCC_PLLI2SM_DIV_51            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */
+#define LL_RCC_PLLI2SM_DIV_52            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */
+#define LL_RCC_PLLI2SM_DIV_53            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */
+#define LL_RCC_PLLI2SM_DIV_54            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */
+#define LL_RCC_PLLI2SM_DIV_55            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */
+#define LL_RCC_PLLI2SM_DIV_56            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */
+#define LL_RCC_PLLI2SM_DIV_57            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */
+#define LL_RCC_PLLI2SM_DIV_58            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */
+#define LL_RCC_PLLI2SM_DIV_59            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */
+#define LL_RCC_PLLI2SM_DIV_60            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */
+#define LL_RCC_PLLI2SM_DIV_61            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */
+#define LL_RCC_PLLI2SM_DIV_62            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */
+#define LL_RCC_PLLI2SM_DIV_63            (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */
+#else
+#define LL_RCC_PLLI2SM_DIV_2              LL_RCC_PLLM_DIV_2      /*!< PLLI2S division factor for PLLI2SM output by 2 */
+#define LL_RCC_PLLI2SM_DIV_3              LL_RCC_PLLM_DIV_3      /*!< PLLI2S division factor for PLLI2SM output by 3 */
+#define LL_RCC_PLLI2SM_DIV_4              LL_RCC_PLLM_DIV_4      /*!< PLLI2S division factor for PLLI2SM output by 4 */
+#define LL_RCC_PLLI2SM_DIV_5              LL_RCC_PLLM_DIV_5      /*!< PLLI2S division factor for PLLI2SM output by 5 */
+#define LL_RCC_PLLI2SM_DIV_6              LL_RCC_PLLM_DIV_6      /*!< PLLI2S division factor for PLLI2SM output by 6 */
+#define LL_RCC_PLLI2SM_DIV_7              LL_RCC_PLLM_DIV_7      /*!< PLLI2S division factor for PLLI2SM output by 7 */
+#define LL_RCC_PLLI2SM_DIV_8              LL_RCC_PLLM_DIV_8      /*!< PLLI2S division factor for PLLI2SM output by 8 */
+#define LL_RCC_PLLI2SM_DIV_9              LL_RCC_PLLM_DIV_9      /*!< PLLI2S division factor for PLLI2SM output by 9 */
+#define LL_RCC_PLLI2SM_DIV_10             LL_RCC_PLLM_DIV_10     /*!< PLLI2S division factor for PLLI2SM output by 10 */
+#define LL_RCC_PLLI2SM_DIV_11             LL_RCC_PLLM_DIV_11     /*!< PLLI2S division factor for PLLI2SM output by 11 */
+#define LL_RCC_PLLI2SM_DIV_12             LL_RCC_PLLM_DIV_12     /*!< PLLI2S division factor for PLLI2SM output by 12 */
+#define LL_RCC_PLLI2SM_DIV_13             LL_RCC_PLLM_DIV_13     /*!< PLLI2S division factor for PLLI2SM output by 13 */
+#define LL_RCC_PLLI2SM_DIV_14             LL_RCC_PLLM_DIV_14     /*!< PLLI2S division factor for PLLI2SM output by 14 */
+#define LL_RCC_PLLI2SM_DIV_15             LL_RCC_PLLM_DIV_15     /*!< PLLI2S division factor for PLLI2SM output by 15 */
+#define LL_RCC_PLLI2SM_DIV_16             LL_RCC_PLLM_DIV_16     /*!< PLLI2S division factor for PLLI2SM output by 16 */
+#define LL_RCC_PLLI2SM_DIV_17             LL_RCC_PLLM_DIV_17     /*!< PLLI2S division factor for PLLI2SM output by 17 */
+#define LL_RCC_PLLI2SM_DIV_18             LL_RCC_PLLM_DIV_18     /*!< PLLI2S division factor for PLLI2SM output by 18 */
+#define LL_RCC_PLLI2SM_DIV_19             LL_RCC_PLLM_DIV_19     /*!< PLLI2S division factor for PLLI2SM output by 19 */
+#define LL_RCC_PLLI2SM_DIV_20             LL_RCC_PLLM_DIV_20     /*!< PLLI2S division factor for PLLI2SM output by 20 */
+#define LL_RCC_PLLI2SM_DIV_21             LL_RCC_PLLM_DIV_21     /*!< PLLI2S division factor for PLLI2SM output by 21 */
+#define LL_RCC_PLLI2SM_DIV_22             LL_RCC_PLLM_DIV_22     /*!< PLLI2S division factor for PLLI2SM output by 22 */
+#define LL_RCC_PLLI2SM_DIV_23             LL_RCC_PLLM_DIV_23     /*!< PLLI2S division factor for PLLI2SM output by 23 */
+#define LL_RCC_PLLI2SM_DIV_24             LL_RCC_PLLM_DIV_24     /*!< PLLI2S division factor for PLLI2SM output by 24 */
+#define LL_RCC_PLLI2SM_DIV_25             LL_RCC_PLLM_DIV_25     /*!< PLLI2S division factor for PLLI2SM output by 25 */
+#define LL_RCC_PLLI2SM_DIV_26             LL_RCC_PLLM_DIV_26     /*!< PLLI2S division factor for PLLI2SM output by 26 */
+#define LL_RCC_PLLI2SM_DIV_27             LL_RCC_PLLM_DIV_27     /*!< PLLI2S division factor for PLLI2SM output by 27 */
+#define LL_RCC_PLLI2SM_DIV_28             LL_RCC_PLLM_DIV_28     /*!< PLLI2S division factor for PLLI2SM output by 28 */
+#define LL_RCC_PLLI2SM_DIV_29             LL_RCC_PLLM_DIV_29     /*!< PLLI2S division factor for PLLI2SM output by 29 */
+#define LL_RCC_PLLI2SM_DIV_30             LL_RCC_PLLM_DIV_30     /*!< PLLI2S division factor for PLLI2SM output by 30 */
+#define LL_RCC_PLLI2SM_DIV_31             LL_RCC_PLLM_DIV_31     /*!< PLLI2S division factor for PLLI2SM output by 31 */
+#define LL_RCC_PLLI2SM_DIV_32             LL_RCC_PLLM_DIV_32     /*!< PLLI2S division factor for PLLI2SM output by 32 */
+#define LL_RCC_PLLI2SM_DIV_33             LL_RCC_PLLM_DIV_33     /*!< PLLI2S division factor for PLLI2SM output by 33 */
+#define LL_RCC_PLLI2SM_DIV_34             LL_RCC_PLLM_DIV_34     /*!< PLLI2S division factor for PLLI2SM output by 34 */
+#define LL_RCC_PLLI2SM_DIV_35             LL_RCC_PLLM_DIV_35     /*!< PLLI2S division factor for PLLI2SM output by 35 */
+#define LL_RCC_PLLI2SM_DIV_36             LL_RCC_PLLM_DIV_36     /*!< PLLI2S division factor for PLLI2SM output by 36 */
+#define LL_RCC_PLLI2SM_DIV_37             LL_RCC_PLLM_DIV_37     /*!< PLLI2S division factor for PLLI2SM output by 37 */
+#define LL_RCC_PLLI2SM_DIV_38             LL_RCC_PLLM_DIV_38     /*!< PLLI2S division factor for PLLI2SM output by 38 */
+#define LL_RCC_PLLI2SM_DIV_39             LL_RCC_PLLM_DIV_39     /*!< PLLI2S division factor for PLLI2SM output by 39 */
+#define LL_RCC_PLLI2SM_DIV_40             LL_RCC_PLLM_DIV_40     /*!< PLLI2S division factor for PLLI2SM output by 40 */
+#define LL_RCC_PLLI2SM_DIV_41             LL_RCC_PLLM_DIV_41     /*!< PLLI2S division factor for PLLI2SM output by 41 */
+#define LL_RCC_PLLI2SM_DIV_42             LL_RCC_PLLM_DIV_42     /*!< PLLI2S division factor for PLLI2SM output by 42 */
+#define LL_RCC_PLLI2SM_DIV_43             LL_RCC_PLLM_DIV_43     /*!< PLLI2S division factor for PLLI2SM output by 43 */
+#define LL_RCC_PLLI2SM_DIV_44             LL_RCC_PLLM_DIV_44     /*!< PLLI2S division factor for PLLI2SM output by 44 */
+#define LL_RCC_PLLI2SM_DIV_45             LL_RCC_PLLM_DIV_45     /*!< PLLI2S division factor for PLLI2SM output by 45 */
+#define LL_RCC_PLLI2SM_DIV_46             LL_RCC_PLLM_DIV_46     /*!< PLLI2S division factor for PLLI2SM output by 46 */
+#define LL_RCC_PLLI2SM_DIV_47             LL_RCC_PLLM_DIV_47     /*!< PLLI2S division factor for PLLI2SM output by 47 */
+#define LL_RCC_PLLI2SM_DIV_48             LL_RCC_PLLM_DIV_48     /*!< PLLI2S division factor for PLLI2SM output by 48 */
+#define LL_RCC_PLLI2SM_DIV_49             LL_RCC_PLLM_DIV_49     /*!< PLLI2S division factor for PLLI2SM output by 49 */
+#define LL_RCC_PLLI2SM_DIV_50             LL_RCC_PLLM_DIV_50     /*!< PLLI2S division factor for PLLI2SM output by 50 */
+#define LL_RCC_PLLI2SM_DIV_51             LL_RCC_PLLM_DIV_51     /*!< PLLI2S division factor for PLLI2SM output by 51 */
+#define LL_RCC_PLLI2SM_DIV_52             LL_RCC_PLLM_DIV_52     /*!< PLLI2S division factor for PLLI2SM output by 52 */
+#define LL_RCC_PLLI2SM_DIV_53             LL_RCC_PLLM_DIV_53     /*!< PLLI2S division factor for PLLI2SM output by 53 */
+#define LL_RCC_PLLI2SM_DIV_54             LL_RCC_PLLM_DIV_54     /*!< PLLI2S division factor for PLLI2SM output by 54 */
+#define LL_RCC_PLLI2SM_DIV_55             LL_RCC_PLLM_DIV_55     /*!< PLLI2S division factor for PLLI2SM output by 55 */
+#define LL_RCC_PLLI2SM_DIV_56             LL_RCC_PLLM_DIV_56     /*!< PLLI2S division factor for PLLI2SM output by 56 */
+#define LL_RCC_PLLI2SM_DIV_57             LL_RCC_PLLM_DIV_57     /*!< PLLI2S division factor for PLLI2SM output by 57 */
+#define LL_RCC_PLLI2SM_DIV_58             LL_RCC_PLLM_DIV_58     /*!< PLLI2S division factor for PLLI2SM output by 58 */
+#define LL_RCC_PLLI2SM_DIV_59             LL_RCC_PLLM_DIV_59     /*!< PLLI2S division factor for PLLI2SM output by 59 */
+#define LL_RCC_PLLI2SM_DIV_60             LL_RCC_PLLM_DIV_60     /*!< PLLI2S division factor for PLLI2SM output by 60 */
+#define LL_RCC_PLLI2SM_DIV_61             LL_RCC_PLLM_DIV_61     /*!< PLLI2S division factor for PLLI2SM output by 61 */
+#define LL_RCC_PLLI2SM_DIV_62             LL_RCC_PLLM_DIV_62     /*!< PLLI2S division factor for PLLI2SM output by 62 */
+#define LL_RCC_PLLI2SM_DIV_63             LL_RCC_PLLM_DIV_63     /*!< PLLI2S division factor for PLLI2SM output by 63 */
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+/**
+  * @}
+  */
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
+/** @defgroup RCC_LL_EC_PLLI2SQ  PLLI2SQ division factor (PLLI2SQ)
+  * @{
+  */
+#define LL_RCC_PLLI2SQ_DIV_2              RCC_PLLI2SCFGR_PLLI2SQ_1        /*!< PLLI2S division factor for PLLI2SQ output by 2 */
+#define LL_RCC_PLLI2SQ_DIV_3              (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 3 */
+#define LL_RCC_PLLI2SQ_DIV_4              RCC_PLLI2SCFGR_PLLI2SQ_2        /*!< PLLI2S division factor for PLLI2SQ output by 4 */
+#define LL_RCC_PLLI2SQ_DIV_5              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 5 */
+#define LL_RCC_PLLI2SQ_DIV_6              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 6 */
+#define LL_RCC_PLLI2SQ_DIV_7              (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 7 */
+#define LL_RCC_PLLI2SQ_DIV_8              RCC_PLLI2SCFGR_PLLI2SQ_3        /*!< PLLI2S division factor for PLLI2SQ output by 8 */
+#define LL_RCC_PLLI2SQ_DIV_9              (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 9 */
+#define LL_RCC_PLLI2SQ_DIV_10             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 10 */
+#define LL_RCC_PLLI2SQ_DIV_11             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 11 */
+#define LL_RCC_PLLI2SQ_DIV_12             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2)        /*!< PLLI2S division factor for PLLI2SQ output by 12 */
+#define LL_RCC_PLLI2SQ_DIV_13             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 13 */
+#define LL_RCC_PLLI2SQ_DIV_14             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1)        /*!< PLLI2S division factor for PLLI2SQ output by 14 */
+#define LL_RCC_PLLI2SQ_DIV_15             (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)        /*!< PLLI2S division factor for PLLI2SQ output by 15 */
+/**
+  * @}
+  */
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
+
+#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
+/** @defgroup RCC_LL_EC_PLLI2SDIVQ  PLLI2SDIVQ division factor (PLLI2SDIVQ)
+  * @{
+  */
+#define LL_RCC_PLLI2SDIVQ_DIV_1           0x00000000U                        /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */
+#define LL_RCC_PLLI2SDIVQ_DIV_2           RCC_DCKCFGR_PLLI2SDIVQ_0          /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */
+#define LL_RCC_PLLI2SDIVQ_DIV_3           RCC_DCKCFGR_PLLI2SDIVQ_1          /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */
+#define LL_RCC_PLLI2SDIVQ_DIV_4           (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */
+#define LL_RCC_PLLI2SDIVQ_DIV_5           RCC_DCKCFGR_PLLI2SDIVQ_2          /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */
+#define LL_RCC_PLLI2SDIVQ_DIV_6           (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */
+#define LL_RCC_PLLI2SDIVQ_DIV_7           (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */
+#define LL_RCC_PLLI2SDIVQ_DIV_8           (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */
+#define LL_RCC_PLLI2SDIVQ_DIV_9           RCC_DCKCFGR_PLLI2SDIVQ_3          /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */
+#define LL_RCC_PLLI2SDIVQ_DIV_10          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */
+#define LL_RCC_PLLI2SDIVQ_DIV_11          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */
+#define LL_RCC_PLLI2SDIVQ_DIV_12          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */
+#define LL_RCC_PLLI2SDIVQ_DIV_13          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */
+#define LL_RCC_PLLI2SDIVQ_DIV_14          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */
+#define LL_RCC_PLLI2SDIVQ_DIV_15          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */
+#define LL_RCC_PLLI2SDIVQ_DIV_16          (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */
+#define LL_RCC_PLLI2SDIVQ_DIV_17          RCC_DCKCFGR_PLLI2SDIVQ_4          /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */
+#define LL_RCC_PLLI2SDIVQ_DIV_18          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */
+#define LL_RCC_PLLI2SDIVQ_DIV_19          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */
+#define LL_RCC_PLLI2SDIVQ_DIV_20          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */
+#define LL_RCC_PLLI2SDIVQ_DIV_21          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */
+#define LL_RCC_PLLI2SDIVQ_DIV_22          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */
+#define LL_RCC_PLLI2SDIVQ_DIV_23          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */
+#define LL_RCC_PLLI2SDIVQ_DIV_24          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */
+#define LL_RCC_PLLI2SDIVQ_DIV_25          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */
+#define LL_RCC_PLLI2SDIVQ_DIV_26          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */
+#define LL_RCC_PLLI2SDIVQ_DIV_27          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */
+#define LL_RCC_PLLI2SDIVQ_DIV_28          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */
+#define LL_RCC_PLLI2SDIVQ_DIV_29          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */
+#define LL_RCC_PLLI2SDIVQ_DIV_30          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */
+#define LL_RCC_PLLI2SDIVQ_DIV_31          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */
+#define LL_RCC_PLLI2SDIVQ_DIV_32          (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)        /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
+
+#if defined(RCC_DCKCFGR_PLLI2SDIVR)
+/** @defgroup RCC_LL_EC_PLLI2SDIVR  PLLI2SDIVR division factor (PLLI2SDIVR)
+  * @{
+  */
+#define LL_RCC_PLLI2SDIVR_DIV_1           (RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */
+#define LL_RCC_PLLI2SDIVR_DIV_2           (RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */
+#define LL_RCC_PLLI2SDIVR_DIV_3           (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */
+#define LL_RCC_PLLI2SDIVR_DIV_4           (RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */
+#define LL_RCC_PLLI2SDIVR_DIV_5           (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */
+#define LL_RCC_PLLI2SDIVR_DIV_6           (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */
+#define LL_RCC_PLLI2SDIVR_DIV_7           (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */
+#define LL_RCC_PLLI2SDIVR_DIV_8           (RCC_DCKCFGR_PLLI2SDIVR_3)        /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */
+#define LL_RCC_PLLI2SDIVR_DIV_9           (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */
+#define LL_RCC_PLLI2SDIVR_DIV_10          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */
+#define LL_RCC_PLLI2SDIVR_DIV_11          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */
+#define LL_RCC_PLLI2SDIVR_DIV_12          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */
+#define LL_RCC_PLLI2SDIVR_DIV_13          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */
+#define LL_RCC_PLLI2SDIVR_DIV_14          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */
+#define LL_RCC_PLLI2SDIVR_DIV_15          (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */
+#define LL_RCC_PLLI2SDIVR_DIV_16          (RCC_DCKCFGR_PLLI2SDIVR_4)             /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */
+#define LL_RCC_PLLI2SDIVR_DIV_17          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */
+#define LL_RCC_PLLI2SDIVR_DIV_18          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */
+#define LL_RCC_PLLI2SDIVR_DIV_19          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */
+#define LL_RCC_PLLI2SDIVR_DIV_20          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */
+#define LL_RCC_PLLI2SDIVR_DIV_21          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */
+#define LL_RCC_PLLI2SDIVR_DIV_22          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */
+#define LL_RCC_PLLI2SDIVR_DIV_23          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */
+#define LL_RCC_PLLI2SDIVR_DIV_24          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3)        /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */
+#define LL_RCC_PLLI2SDIVR_DIV_25          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */
+#define LL_RCC_PLLI2SDIVR_DIV_26          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */
+#define LL_RCC_PLLI2SDIVR_DIV_27          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */
+#define LL_RCC_PLLI2SDIVR_DIV_28          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2)        /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */
+#define LL_RCC_PLLI2SDIVR_DIV_29          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */
+#define LL_RCC_PLLI2SDIVR_DIV_30          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)        /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */
+#define LL_RCC_PLLI2SDIVR_DIV_31          (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)        /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_PLLI2SDIVR */
+
+/** @defgroup RCC_LL_EC_PLLI2SR  PLLI2SR division factor (PLLI2SR)
+  * @{
+  */
+#define LL_RCC_PLLI2SR_DIV_2              RCC_PLLI2SCFGR_PLLI2SR_1                                     /*!< PLLI2S division factor for PLLI2SR output by 2 */
+#define LL_RCC_PLLI2SR_DIV_3              (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 3 */
+#define LL_RCC_PLLI2SR_DIV_4              RCC_PLLI2SCFGR_PLLI2SR_2                                     /*!< PLLI2S division factor for PLLI2SR output by 4 */
+#define LL_RCC_PLLI2SR_DIV_5              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 5 */
+#define LL_RCC_PLLI2SR_DIV_6              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1)        /*!< PLLI2S division factor for PLLI2SR output by 6 */
+#define LL_RCC_PLLI2SR_DIV_7              (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0)        /*!< PLLI2S division factor for PLLI2SR output by 7 */
+/**
+  * @}
+  */
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SP)
+/** @defgroup RCC_LL_EC_PLLI2SP  PLLI2SP division factor (PLLI2SP)
+  * @{
+  */
+#define LL_RCC_PLLI2SP_DIV_2              0x00000000U            /*!< PLLI2S division factor for PLLI2SP output by 2 */
+#define LL_RCC_PLLI2SP_DIV_4              RCC_PLLI2SCFGR_PLLI2SP_0        /*!< PLLI2S division factor for PLLI2SP output by 4 */
+#define LL_RCC_PLLI2SP_DIV_6              RCC_PLLI2SCFGR_PLLI2SP_1        /*!< PLLI2S division factor for PLLI2SP output by 6 */
+#define LL_RCC_PLLI2SP_DIV_8              (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0)        /*!< PLLI2S division factor for PLLI2SP output by 8 */
+/**
+  * @}
+  */
+#endif /* RCC_PLLI2SCFGR_PLLI2SP */
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/** @defgroup RCC_LL_EC_PLLSAIM  PLLSAIM division factor (PLLSAIM or PLLM)
+  * @{
+  */
+#if defined(RCC_PLLSAICFGR_PLLSAIM)
+#define LL_RCC_PLLSAIM_DIV_2             (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */
+#define LL_RCC_PLLSAIM_DIV_3             (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */
+#define LL_RCC_PLLSAIM_DIV_4             (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */
+#define LL_RCC_PLLSAIM_DIV_5             (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */
+#define LL_RCC_PLLSAIM_DIV_6             (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */
+#define LL_RCC_PLLSAIM_DIV_7             (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */
+#define LL_RCC_PLLSAIM_DIV_8             (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */
+#define LL_RCC_PLLSAIM_DIV_9             (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */
+#define LL_RCC_PLLSAIM_DIV_10            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */
+#define LL_RCC_PLLSAIM_DIV_11            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */
+#define LL_RCC_PLLSAIM_DIV_12            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */
+#define LL_RCC_PLLSAIM_DIV_13            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */
+#define LL_RCC_PLLSAIM_DIV_14            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */
+#define LL_RCC_PLLSAIM_DIV_15            (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */
+#define LL_RCC_PLLSAIM_DIV_16            (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */
+#define LL_RCC_PLLSAIM_DIV_17            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */
+#define LL_RCC_PLLSAIM_DIV_18            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */
+#define LL_RCC_PLLSAIM_DIV_19            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */
+#define LL_RCC_PLLSAIM_DIV_20            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */
+#define LL_RCC_PLLSAIM_DIV_21            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */
+#define LL_RCC_PLLSAIM_DIV_22            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */
+#define LL_RCC_PLLSAIM_DIV_23            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */
+#define LL_RCC_PLLSAIM_DIV_24            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */
+#define LL_RCC_PLLSAIM_DIV_25            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */
+#define LL_RCC_PLLSAIM_DIV_26            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */
+#define LL_RCC_PLLSAIM_DIV_27            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */
+#define LL_RCC_PLLSAIM_DIV_28            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */
+#define LL_RCC_PLLSAIM_DIV_29            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */
+#define LL_RCC_PLLSAIM_DIV_30            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */
+#define LL_RCC_PLLSAIM_DIV_31            (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */
+#define LL_RCC_PLLSAIM_DIV_32            (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */
+#define LL_RCC_PLLSAIM_DIV_33            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */
+#define LL_RCC_PLLSAIM_DIV_34            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */
+#define LL_RCC_PLLSAIM_DIV_35            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */
+#define LL_RCC_PLLSAIM_DIV_36            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */
+#define LL_RCC_PLLSAIM_DIV_37            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */
+#define LL_RCC_PLLSAIM_DIV_38            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */
+#define LL_RCC_PLLSAIM_DIV_39            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */
+#define LL_RCC_PLLSAIM_DIV_40            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */
+#define LL_RCC_PLLSAIM_DIV_41            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */
+#define LL_RCC_PLLSAIM_DIV_42            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */
+#define LL_RCC_PLLSAIM_DIV_43            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */
+#define LL_RCC_PLLSAIM_DIV_44            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */
+#define LL_RCC_PLLSAIM_DIV_45            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */
+#define LL_RCC_PLLSAIM_DIV_46            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */
+#define LL_RCC_PLLSAIM_DIV_47            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */
+#define LL_RCC_PLLSAIM_DIV_48            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */
+#define LL_RCC_PLLSAIM_DIV_49            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */
+#define LL_RCC_PLLSAIM_DIV_50            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */
+#define LL_RCC_PLLSAIM_DIV_51            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */
+#define LL_RCC_PLLSAIM_DIV_52            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */
+#define LL_RCC_PLLSAIM_DIV_53            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */
+#define LL_RCC_PLLSAIM_DIV_54            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */
+#define LL_RCC_PLLSAIM_DIV_55            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */
+#define LL_RCC_PLLSAIM_DIV_56            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */
+#define LL_RCC_PLLSAIM_DIV_57            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */
+#define LL_RCC_PLLSAIM_DIV_58            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */
+#define LL_RCC_PLLSAIM_DIV_59            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */
+#define LL_RCC_PLLSAIM_DIV_60            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */
+#define LL_RCC_PLLSAIM_DIV_61            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */
+#define LL_RCC_PLLSAIM_DIV_62            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */
+#define LL_RCC_PLLSAIM_DIV_63            (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */
+#else
+#define LL_RCC_PLLSAIM_DIV_2              LL_RCC_PLLM_DIV_2      /*!< PLLSAI division factor for PLLSAIM output by 2 */
+#define LL_RCC_PLLSAIM_DIV_3              LL_RCC_PLLM_DIV_3      /*!< PLLSAI division factor for PLLSAIM output by 3 */
+#define LL_RCC_PLLSAIM_DIV_4              LL_RCC_PLLM_DIV_4      /*!< PLLSAI division factor for PLLSAIM output by 4 */
+#define LL_RCC_PLLSAIM_DIV_5              LL_RCC_PLLM_DIV_5      /*!< PLLSAI division factor for PLLSAIM output by 5 */
+#define LL_RCC_PLLSAIM_DIV_6              LL_RCC_PLLM_DIV_6      /*!< PLLSAI division factor for PLLSAIM output by 6 */
+#define LL_RCC_PLLSAIM_DIV_7              LL_RCC_PLLM_DIV_7      /*!< PLLSAI division factor for PLLSAIM output by 7 */
+#define LL_RCC_PLLSAIM_DIV_8              LL_RCC_PLLM_DIV_8      /*!< PLLSAI division factor for PLLSAIM output by 8 */
+#define LL_RCC_PLLSAIM_DIV_9              LL_RCC_PLLM_DIV_9      /*!< PLLSAI division factor for PLLSAIM output by 9 */
+#define LL_RCC_PLLSAIM_DIV_10             LL_RCC_PLLM_DIV_10     /*!< PLLSAI division factor for PLLSAIM output by 10 */
+#define LL_RCC_PLLSAIM_DIV_11             LL_RCC_PLLM_DIV_11     /*!< PLLSAI division factor for PLLSAIM output by 11 */
+#define LL_RCC_PLLSAIM_DIV_12             LL_RCC_PLLM_DIV_12     /*!< PLLSAI division factor for PLLSAIM output by 12 */
+#define LL_RCC_PLLSAIM_DIV_13             LL_RCC_PLLM_DIV_13     /*!< PLLSAI division factor for PLLSAIM output by 13 */
+#define LL_RCC_PLLSAIM_DIV_14             LL_RCC_PLLM_DIV_14     /*!< PLLSAI division factor for PLLSAIM output by 14 */
+#define LL_RCC_PLLSAIM_DIV_15             LL_RCC_PLLM_DIV_15     /*!< PLLSAI division factor for PLLSAIM output by 15 */
+#define LL_RCC_PLLSAIM_DIV_16             LL_RCC_PLLM_DIV_16     /*!< PLLSAI division factor for PLLSAIM output by 16 */
+#define LL_RCC_PLLSAIM_DIV_17             LL_RCC_PLLM_DIV_17     /*!< PLLSAI division factor for PLLSAIM output by 17 */
+#define LL_RCC_PLLSAIM_DIV_18             LL_RCC_PLLM_DIV_18     /*!< PLLSAI division factor for PLLSAIM output by 18 */
+#define LL_RCC_PLLSAIM_DIV_19             LL_RCC_PLLM_DIV_19     /*!< PLLSAI division factor for PLLSAIM output by 19 */
+#define LL_RCC_PLLSAIM_DIV_20             LL_RCC_PLLM_DIV_20     /*!< PLLSAI division factor for PLLSAIM output by 20 */
+#define LL_RCC_PLLSAIM_DIV_21             LL_RCC_PLLM_DIV_21     /*!< PLLSAI division factor for PLLSAIM output by 21 */
+#define LL_RCC_PLLSAIM_DIV_22             LL_RCC_PLLM_DIV_22     /*!< PLLSAI division factor for PLLSAIM output by 22 */
+#define LL_RCC_PLLSAIM_DIV_23             LL_RCC_PLLM_DIV_23     /*!< PLLSAI division factor for PLLSAIM output by 23 */
+#define LL_RCC_PLLSAIM_DIV_24             LL_RCC_PLLM_DIV_24     /*!< PLLSAI division factor for PLLSAIM output by 24 */
+#define LL_RCC_PLLSAIM_DIV_25             LL_RCC_PLLM_DIV_25     /*!< PLLSAI division factor for PLLSAIM output by 25 */
+#define LL_RCC_PLLSAIM_DIV_26             LL_RCC_PLLM_DIV_26     /*!< PLLSAI division factor for PLLSAIM output by 26 */
+#define LL_RCC_PLLSAIM_DIV_27             LL_RCC_PLLM_DIV_27     /*!< PLLSAI division factor for PLLSAIM output by 27 */
+#define LL_RCC_PLLSAIM_DIV_28             LL_RCC_PLLM_DIV_28     /*!< PLLSAI division factor for PLLSAIM output by 28 */
+#define LL_RCC_PLLSAIM_DIV_29             LL_RCC_PLLM_DIV_29     /*!< PLLSAI division factor for PLLSAIM output by 29 */
+#define LL_RCC_PLLSAIM_DIV_30             LL_RCC_PLLM_DIV_30     /*!< PLLSAI division factor for PLLSAIM output by 30 */
+#define LL_RCC_PLLSAIM_DIV_31             LL_RCC_PLLM_DIV_31     /*!< PLLSAI division factor for PLLSAIM output by 31 */
+#define LL_RCC_PLLSAIM_DIV_32             LL_RCC_PLLM_DIV_32     /*!< PLLSAI division factor for PLLSAIM output by 32 */
+#define LL_RCC_PLLSAIM_DIV_33             LL_RCC_PLLM_DIV_33     /*!< PLLSAI division factor for PLLSAIM output by 33 */
+#define LL_RCC_PLLSAIM_DIV_34             LL_RCC_PLLM_DIV_34     /*!< PLLSAI division factor for PLLSAIM output by 34 */
+#define LL_RCC_PLLSAIM_DIV_35             LL_RCC_PLLM_DIV_35     /*!< PLLSAI division factor for PLLSAIM output by 35 */
+#define LL_RCC_PLLSAIM_DIV_36             LL_RCC_PLLM_DIV_36     /*!< PLLSAI division factor for PLLSAIM output by 36 */
+#define LL_RCC_PLLSAIM_DIV_37             LL_RCC_PLLM_DIV_37     /*!< PLLSAI division factor for PLLSAIM output by 37 */
+#define LL_RCC_PLLSAIM_DIV_38             LL_RCC_PLLM_DIV_38     /*!< PLLSAI division factor for PLLSAIM output by 38 */
+#define LL_RCC_PLLSAIM_DIV_39             LL_RCC_PLLM_DIV_39     /*!< PLLSAI division factor for PLLSAIM output by 39 */
+#define LL_RCC_PLLSAIM_DIV_40             LL_RCC_PLLM_DIV_40     /*!< PLLSAI division factor for PLLSAIM output by 40 */
+#define LL_RCC_PLLSAIM_DIV_41             LL_RCC_PLLM_DIV_41     /*!< PLLSAI division factor for PLLSAIM output by 41 */
+#define LL_RCC_PLLSAIM_DIV_42             LL_RCC_PLLM_DIV_42     /*!< PLLSAI division factor for PLLSAIM output by 42 */
+#define LL_RCC_PLLSAIM_DIV_43             LL_RCC_PLLM_DIV_43     /*!< PLLSAI division factor for PLLSAIM output by 43 */
+#define LL_RCC_PLLSAIM_DIV_44             LL_RCC_PLLM_DIV_44     /*!< PLLSAI division factor for PLLSAIM output by 44 */
+#define LL_RCC_PLLSAIM_DIV_45             LL_RCC_PLLM_DIV_45     /*!< PLLSAI division factor for PLLSAIM output by 45 */
+#define LL_RCC_PLLSAIM_DIV_46             LL_RCC_PLLM_DIV_46     /*!< PLLSAI division factor for PLLSAIM output by 46 */
+#define LL_RCC_PLLSAIM_DIV_47             LL_RCC_PLLM_DIV_47     /*!< PLLSAI division factor for PLLSAIM output by 47 */
+#define LL_RCC_PLLSAIM_DIV_48             LL_RCC_PLLM_DIV_48     /*!< PLLSAI division factor for PLLSAIM output by 48 */
+#define LL_RCC_PLLSAIM_DIV_49             LL_RCC_PLLM_DIV_49     /*!< PLLSAI division factor for PLLSAIM output by 49 */
+#define LL_RCC_PLLSAIM_DIV_50             LL_RCC_PLLM_DIV_50     /*!< PLLSAI division factor for PLLSAIM output by 50 */
+#define LL_RCC_PLLSAIM_DIV_51             LL_RCC_PLLM_DIV_51     /*!< PLLSAI division factor for PLLSAIM output by 51 */
+#define LL_RCC_PLLSAIM_DIV_52             LL_RCC_PLLM_DIV_52     /*!< PLLSAI division factor for PLLSAIM output by 52 */
+#define LL_RCC_PLLSAIM_DIV_53             LL_RCC_PLLM_DIV_53     /*!< PLLSAI division factor for PLLSAIM output by 53 */
+#define LL_RCC_PLLSAIM_DIV_54             LL_RCC_PLLM_DIV_54     /*!< PLLSAI division factor for PLLSAIM output by 54 */
+#define LL_RCC_PLLSAIM_DIV_55             LL_RCC_PLLM_DIV_55     /*!< PLLSAI division factor for PLLSAIM output by 55 */
+#define LL_RCC_PLLSAIM_DIV_56             LL_RCC_PLLM_DIV_56     /*!< PLLSAI division factor for PLLSAIM output by 56 */
+#define LL_RCC_PLLSAIM_DIV_57             LL_RCC_PLLM_DIV_57     /*!< PLLSAI division factor for PLLSAIM output by 57 */
+#define LL_RCC_PLLSAIM_DIV_58             LL_RCC_PLLM_DIV_58     /*!< PLLSAI division factor for PLLSAIM output by 58 */
+#define LL_RCC_PLLSAIM_DIV_59             LL_RCC_PLLM_DIV_59     /*!< PLLSAI division factor for PLLSAIM output by 59 */
+#define LL_RCC_PLLSAIM_DIV_60             LL_RCC_PLLM_DIV_60     /*!< PLLSAI division factor for PLLSAIM output by 60 */
+#define LL_RCC_PLLSAIM_DIV_61             LL_RCC_PLLM_DIV_61     /*!< PLLSAI division factor for PLLSAIM output by 61 */
+#define LL_RCC_PLLSAIM_DIV_62             LL_RCC_PLLM_DIV_62     /*!< PLLSAI division factor for PLLSAIM output by 62 */
+#define LL_RCC_PLLSAIM_DIV_63             LL_RCC_PLLM_DIV_63     /*!< PLLSAI division factor for PLLSAIM output by 63 */
+#endif /* RCC_PLLSAICFGR_PLLSAIM */
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EC_PLLSAIQ  PLLSAIQ division factor (PLLSAIQ)
+  * @{
+  */
+#define LL_RCC_PLLSAIQ_DIV_2              RCC_PLLSAICFGR_PLLSAIQ_1        /*!< PLLSAI division factor for PLLSAIQ output by 2 */
+#define LL_RCC_PLLSAIQ_DIV_3              (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 3 */
+#define LL_RCC_PLLSAIQ_DIV_4              RCC_PLLSAICFGR_PLLSAIQ_2        /*!< PLLSAI division factor for PLLSAIQ output by 4 */
+#define LL_RCC_PLLSAIQ_DIV_5              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 5 */
+#define LL_RCC_PLLSAIQ_DIV_6              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 6 */
+#define LL_RCC_PLLSAIQ_DIV_7              (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 7 */
+#define LL_RCC_PLLSAIQ_DIV_8              RCC_PLLSAICFGR_PLLSAIQ_3        /*!< PLLSAI division factor for PLLSAIQ output by 8 */
+#define LL_RCC_PLLSAIQ_DIV_9              (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 9 */
+#define LL_RCC_PLLSAIQ_DIV_10             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 10 */
+#define LL_RCC_PLLSAIQ_DIV_11             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 11 */
+#define LL_RCC_PLLSAIQ_DIV_12             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2)        /*!< PLLSAI division factor for PLLSAIQ output by 12 */
+#define LL_RCC_PLLSAIQ_DIV_13             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 13 */
+#define LL_RCC_PLLSAIQ_DIV_14             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1)        /*!< PLLSAI division factor for PLLSAIQ output by 14 */
+#define LL_RCC_PLLSAIQ_DIV_15             (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)        /*!< PLLSAI division factor for PLLSAIQ output by 15 */
+/**
+  * @}
+  */
+
+#if defined(RCC_DCKCFGR_PLLSAIDIVQ)
+/** @defgroup RCC_LL_EC_PLLSAIDIVQ  PLLSAIDIVQ division factor (PLLSAIDIVQ)
+  * @{
+  */
+#define LL_RCC_PLLSAIDIVQ_DIV_1           0x00000000U               /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */
+#define LL_RCC_PLLSAIDIVQ_DIV_2           RCC_DCKCFGR_PLLSAIDIVQ_0          /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */
+#define LL_RCC_PLLSAIDIVQ_DIV_3           RCC_DCKCFGR_PLLSAIDIVQ_1          /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */
+#define LL_RCC_PLLSAIDIVQ_DIV_4           (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */
+#define LL_RCC_PLLSAIDIVQ_DIV_5           RCC_DCKCFGR_PLLSAIDIVQ_2          /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */
+#define LL_RCC_PLLSAIDIVQ_DIV_6           (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */
+#define LL_RCC_PLLSAIDIVQ_DIV_7           (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */
+#define LL_RCC_PLLSAIDIVQ_DIV_8           (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */
+#define LL_RCC_PLLSAIDIVQ_DIV_9           RCC_DCKCFGR_PLLSAIDIVQ_3          /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */
+#define LL_RCC_PLLSAIDIVQ_DIV_10          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */
+#define LL_RCC_PLLSAIDIVQ_DIV_11          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */
+#define LL_RCC_PLLSAIDIVQ_DIV_12          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */
+#define LL_RCC_PLLSAIDIVQ_DIV_13          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */
+#define LL_RCC_PLLSAIDIVQ_DIV_14          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */
+#define LL_RCC_PLLSAIDIVQ_DIV_15          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */
+#define LL_RCC_PLLSAIDIVQ_DIV_16          (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */
+#define LL_RCC_PLLSAIDIVQ_DIV_17          RCC_DCKCFGR_PLLSAIDIVQ_4         /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */
+#define LL_RCC_PLLSAIDIVQ_DIV_18          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */
+#define LL_RCC_PLLSAIDIVQ_DIV_19          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */
+#define LL_RCC_PLLSAIDIVQ_DIV_20          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */
+#define LL_RCC_PLLSAIDIVQ_DIV_21          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */
+#define LL_RCC_PLLSAIDIVQ_DIV_22          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */
+#define LL_RCC_PLLSAIDIVQ_DIV_23          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */
+#define LL_RCC_PLLSAIDIVQ_DIV_24          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */
+#define LL_RCC_PLLSAIDIVQ_DIV_25          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */
+#define LL_RCC_PLLSAIDIVQ_DIV_26          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */
+#define LL_RCC_PLLSAIDIVQ_DIV_27          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */
+#define LL_RCC_PLLSAIDIVQ_DIV_28          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */
+#define LL_RCC_PLLSAIDIVQ_DIV_29          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */
+#define LL_RCC_PLLSAIDIVQ_DIV_30          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */
+#define LL_RCC_PLLSAIDIVQ_DIV_31          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */
+#define LL_RCC_PLLSAIDIVQ_DIV_32          (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)        /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_PLLSAIDIVQ */
+
+#if defined(RCC_PLLSAICFGR_PLLSAIR)
+/** @defgroup RCC_LL_EC_PLLSAIR  PLLSAIR division factor (PLLSAIR)
+  * @{
+  */
+#define LL_RCC_PLLSAIR_DIV_2              RCC_PLLSAICFGR_PLLSAIR_1                                     /*!< PLLSAI division factor for PLLSAIR output by 2 */
+#define LL_RCC_PLLSAIR_DIV_3              (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 3 */
+#define LL_RCC_PLLSAIR_DIV_4              RCC_PLLSAICFGR_PLLSAIR_2                                     /*!< PLLSAI division factor for PLLSAIR output by 4 */
+#define LL_RCC_PLLSAIR_DIV_5              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 5 */
+#define LL_RCC_PLLSAIR_DIV_6              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1)        /*!< PLLSAI division factor for PLLSAIR output by 6 */
+#define LL_RCC_PLLSAIR_DIV_7              (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0)        /*!< PLLSAI division factor for PLLSAIR output by 7 */
+/**
+  * @}
+  */
+#endif /* RCC_PLLSAICFGR_PLLSAIR */
+
+#if defined(RCC_DCKCFGR_PLLSAIDIVR)
+/** @defgroup RCC_LL_EC_PLLSAIDIVR  PLLSAIDIVR division factor (PLLSAIDIVR)
+  * @{
+  */
+#define LL_RCC_PLLSAIDIVR_DIV_2           0x00000000U             /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */
+#define LL_RCC_PLLSAIDIVR_DIV_4           RCC_DCKCFGR_PLLSAIDIVR_0        /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */
+#define LL_RCC_PLLSAIDIVR_DIV_8           RCC_DCKCFGR_PLLSAIDIVR_1        /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */
+#define LL_RCC_PLLSAIDIVR_DIV_16          (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0)        /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_PLLSAIDIVR */
+
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+/** @defgroup RCC_LL_EC_PLLSAIP  PLLSAIP division factor (PLLSAIP)
+  * @{
+  */
+#define LL_RCC_PLLSAIP_DIV_2              0x00000000U               /*!< PLLSAI division factor for PLLSAIP output by 2 */
+#define LL_RCC_PLLSAIP_DIV_4              RCC_PLLSAICFGR_PLLSAIP_0        /*!< PLLSAI division factor for PLLSAIP output by 4 */
+#define LL_RCC_PLLSAIP_DIV_6              RCC_PLLSAICFGR_PLLSAIP_1        /*!< PLLSAI division factor for PLLSAIP output by 6 */
+#define LL_RCC_PLLSAIP_DIV_8              (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0)        /*!< PLLSAI division factor for PLLSAIP output by 8 */
+/**
+  * @}
+  */
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+#endif /* RCC_PLLSAI_SUPPORT */
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
+  * @{
+  */
+
+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in RCC register
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in RCC register
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency on system domain
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  __PLLP__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_2
+  *         @arg @ref LL_RCC_PLLP_DIV_4
+  *         @arg @ref LL_RCC_PLLP_DIV_6
+  *         @arg @ref LL_RCC_PLLP_DIV_8
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
+
+#if defined(RCC_PLLR_SYSCLK_SUPPORT)
+/**
+  * @brief  Helper macro to calculate the PLLRCLK frequency on system domain
+  * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50 and 432
+  * @param  __PLLR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+
+#endif /* RCC_PLLR_SYSCLK_SUPPORT */
+
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on 48M domain
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  __PLLQ__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLQ_DIV_2
+  *         @arg @ref LL_RCC_PLLQ_DIV_3
+  *         @arg @ref LL_RCC_PLLQ_DIV_4
+  *         @arg @ref LL_RCC_PLLQ_DIV_5
+  *         @arg @ref LL_RCC_PLLQ_DIV_6
+  *         @arg @ref LL_RCC_PLLQ_DIV_7
+  *         @arg @ref LL_RCC_PLLQ_DIV_8
+  *         @arg @ref LL_RCC_PLLQ_DIV_9
+  *         @arg @ref LL_RCC_PLLQ_DIV_10
+  *         @arg @ref LL_RCC_PLLQ_DIV_11
+  *         @arg @ref LL_RCC_PLLQ_DIV_12
+  *         @arg @ref LL_RCC_PLLQ_DIV_13
+  *         @arg @ref LL_RCC_PLLQ_DIV_14
+  *         @arg @ref LL_RCC_PLLQ_DIV_15
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
+
+#if defined(DSI)
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on DSI
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50 and 432
+  * @param  __PLLR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+#endif /* DSI */
+
+#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on I2S
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50 and 432
+  * @param  __PLLR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
+
+#if defined(SPDIFRX)
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on SPDIFRX
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50 and 432
+  * @param  __PLLR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @retval PLL clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+#endif /* SPDIFRX */
+
+#if defined(RCC_PLLCFGR_PLLR)
+#if defined(SAI1)
+/**
+  * @brief  Helper macro to calculate the PLLCLK frequency used on SAI
+  * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
+  *             @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  __PLLN__ Between 50 and 432
+  * @param  __PLLR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @param  __PLLDIVR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval PLL clock frequency (in Hz)
+  */
+#if defined(RCC_DCKCFGR_PLLDIVR)
+#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))
+#else
+#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
+                   ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
+#endif /* RCC_DCKCFGR_PLLDIVR */
+#endif /* SAI1 */
+#endif /* RCC_PLLCFGR_PLLR */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+  * @brief  Helper macro to calculate the PLLSAI frequency used for SAI domain
+  * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
+  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
+  * @param  __PLLSAIN__ Between 49/50(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  __PLLSAIQ__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15
+  * @param  __PLLSAIDIVQ__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
+  * @retval PLLSAI clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
+                   (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))
+
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+/**
+  * @brief  Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
+  * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
+  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
+  * @param  __PLLSAIN__ Between 50 and 432
+  * @param  __PLLSAIP__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_8
+  * @retval PLLSAI clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
+                   ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U))
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+
+#if defined(LTDC)
+/**
+  * @brief  Helper macro to calculate the PLLSAI frequency used for LTDC domain
+  * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (),
+  *             @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
+  * @param  __PLLSAIN__ Between 49/50(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  __PLLSAIR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_7
+  * @param  __PLLSAIDIVR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
+  * @retval PLLSAI clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
+                   (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))
+#endif /* LTDC */
+#endif /* RCC_PLLSAI_SUPPORT */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+#if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)
+/**
+  * @brief  Helper macro to calculate the PLLI2S frequency used for SAI domain
+  * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
+  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  * @param  __PLLI2SN__ Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  __PLLI2SQ_R__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @param  __PLLI2SDIVQ_R__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval PLLI2S clock frequency (in Hz)
+  */
+#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
+#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+                   (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))
+#else
+#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+                   (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos)))
+
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */
+
+#if defined(SPDIFRX)
+/**
+  * @brief  Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
+  * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
+  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  * @param  __PLLI2SN__ Between 50 and 432
+  * @param  __PLLI2SP__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_8
+  * @retval PLLI2S clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+                   ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
+
+#endif /* SPDIFRX */
+
+/**
+  * @brief  Helper macro to calculate the PLLI2S frequency used for I2S domain
+  * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
+  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  * @param  __PLLI2SN__ Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  __PLLI2SR__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_7
+  * @retval PLLI2S clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+                   ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+/**
+  * @brief  Helper macro to calculate the PLLI2S frequency used for 48Mhz domain
+  * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (),
+  *             @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ());
+  * @param  __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
+  * @param  __PLLM__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  * @param  __PLLI2SN__ Between 50 and 432
+  * @param  __PLLI2SQ__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
+  * @retval PLLI2S clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
+                   ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos))
+
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+#endif /* RCC_PLLI2S_SUPPORT */
+
+/**
+  * @brief  Helper macro to calculate the HCLK frequency
+  * @param  __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
+  * @param  __AHBPRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval HCLK clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >>  RCC_CFGR_HPRE_Pos])
+
+/**
+  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB1PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval PCLK1 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >>  RCC_CFGR_PPRE1_Pos])
+
+/**
+  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)
+  * @param  __HCLKFREQ__ HCLK frequency
+  * @param  __APB2PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval PCLK2 clock frequency (in Hz)
+  */
+#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >>  RCC_CFGR_PPRE2_Pos])
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
+  * @{
+  */
+
+/** @defgroup RCC_LL_EF_HSE HSE
+  * @{
+  */
+
+/**
+  * @brief  Enable the Clock Security System.
+  * @rmtoll CR           CSSON         LL_RCC_HSE_EnableCSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_CSSON);
+}
+
+/**
+  * @brief  Enable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+  * @brief  Disable HSE external oscillator (HSE Bypass)
+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
+}
+
+/**
+  * @brief  Enable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Disable HSE crystal oscillator (HSE ON)
+  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSE_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
+}
+
+/**
+  * @brief  Check if HSE oscillator Ready
+  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_HSI HSI
+  * @{
+  */
+
+/**
+  * @brief  Enable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Disable HSI oscillator
+  * @rmtoll CR           HSION         LL_RCC_HSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_HSION);
+}
+
+/**
+  * @brief  Check if HSI clock is ready
+  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
+}
+
+/**
+  * @brief  Get HSI Calibration value
+  * @note When HSITRIM is written, HSICAL is updated with the sum of
+  *       HSITRIM and the factory trim value
+  * @rmtoll CR        HSICAL        LL_RCC_HSI_GetCalibration
+  * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
+}
+
+/**
+  * @brief  Set HSI Calibration trimming
+  * @note user-programmable trimming value that is added to the HSICAL
+  * @note Default value is 16, which, when added to the HSICAL value,
+  *       should trim the HSI to 16 MHz +/- 1 %
+  * @rmtoll CR        HSITRIM       LL_RCC_HSI_SetCalibTrimming
+  * @param  Value Between Min_Data = 0 and Max_Data = 31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
+{
+  MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
+}
+
+/**
+  * @brief  Get HSI Calibration trimming
+  * @rmtoll CR        HSITRIM       LL_RCC_HSI_GetCalibTrimming
+  * @retval Between Min_Data = 0 and Max_Data = 31
+  */
+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSE LSE
+  * @{
+  */
+
+/**
+  * @brief  Enable  Low Speed External (LSE) crystal.
+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Enable(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+  * @brief  Disable  Low Speed External (LSE) crystal.
+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_Disable(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
+}
+
+/**
+  * @brief  Enable external clock source (LSE bypass).
+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+  * @brief  Disable external clock source (LSE bypass).
+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
+}
+
+/**
+  * @brief  Check if LSE oscillator Ready
+  * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
+{
+  return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
+}
+
+#if defined(RCC_BDCR_LSEMOD)
+/**
+  * @brief  Enable LSE high drive mode.
+  * @note LSE high drive mode can be enabled only when the LSE clock is disabled
+  * @rmtoll BDCR         LSEMOD      LL_RCC_LSE_EnableHighDriveMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
+}
+
+/**
+  * @brief  Disable LSE high drive mode.
+  * @note LSE high drive mode can be disabled only when the LSE clock is disabled
+  * @rmtoll BDCR         LSEMOD      LL_RCC_LSE_DisableHighDriveMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
+}
+#endif /* RCC_BDCR_LSEMOD */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_LSI LSI
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Enable(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Disable LSI Oscillator
+  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_LSI_Disable(void)
+{
+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+}
+
+/**
+  * @brief  Check if LSI is Ready
+  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_System System
+  * @{
+  */
+
+/**
+  * @brief  Configure the system clock source
+  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
+}
+
+/**
+  * @brief  Get the system clock source
+  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
+}
+
+/**
+  * @brief  Set AHB prescaler
+  * @rmtoll CFGR         HPRE          LL_RCC_SetAHBPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
+}
+
+/**
+  * @brief  Set APB1 prescaler
+  * @rmtoll CFGR         PPRE1         LL_RCC_SetAPB1Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
+}
+
+/**
+  * @brief  Set APB2 prescaler
+  * @rmtoll CFGR         PPRE2         LL_RCC_SetAPB2Prescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
+}
+
+/**
+  * @brief  Get AHB prescaler
+  * @rmtoll CFGR         HPRE          LL_RCC_GetAHBPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SYSCLK_DIV_1
+  *         @arg @ref LL_RCC_SYSCLK_DIV_2
+  *         @arg @ref LL_RCC_SYSCLK_DIV_4
+  *         @arg @ref LL_RCC_SYSCLK_DIV_8
+  *         @arg @ref LL_RCC_SYSCLK_DIV_16
+  *         @arg @ref LL_RCC_SYSCLK_DIV_64
+  *         @arg @ref LL_RCC_SYSCLK_DIV_128
+  *         @arg @ref LL_RCC_SYSCLK_DIV_256
+  *         @arg @ref LL_RCC_SYSCLK_DIV_512
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
+}
+
+/**
+  * @brief  Get APB1 prescaler
+  * @rmtoll CFGR         PPRE1         LL_RCC_GetAPB1Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB1_DIV_1
+  *         @arg @ref LL_RCC_APB1_DIV_2
+  *         @arg @ref LL_RCC_APB1_DIV_4
+  *         @arg @ref LL_RCC_APB1_DIV_8
+  *         @arg @ref LL_RCC_APB1_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
+}
+
+/**
+  * @brief  Get APB2 prescaler
+  * @rmtoll CFGR         PPRE2         LL_RCC_GetAPB2Prescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_APB2_DIV_1
+  *         @arg @ref LL_RCC_APB2_DIV_2
+  *         @arg @ref LL_RCC_APB2_DIV_4
+  *         @arg @ref LL_RCC_APB2_DIV_8
+  *         @arg @ref LL_RCC_APB2_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_MCO MCO
+  * @{
+  */
+
+#if defined(RCC_CFGR_MCO1EN)
+/**
+  * @brief  Enable MCO1 output
+  * @rmtoll CFGR           RCC_CFGR_MCO1EN         LL_RCC_MCO1_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MCO1_Enable(void)
+{
+  SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
+}
+
+/**
+  * @brief  Disable MCO1 output
+  * @rmtoll CFGR           RCC_CFGR_MCO1EN         LL_RCC_MCO1_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MCO1_Disable(void)
+{
+  CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
+}
+#endif /* RCC_CFGR_MCO1EN */
+
+#if defined(RCC_CFGR_MCO2EN)
+/**
+  * @brief  Enable MCO2 output
+  * @rmtoll CFGR           RCC_CFGR_MCO2EN         LL_RCC_MCO2_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MCO2_Enable(void)
+{
+  SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
+}
+
+/**
+  * @brief  Disable MCO2 output
+  * @rmtoll CFGR           RCC_CFGR_MCO2EN         LL_RCC_MCO2_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_MCO2_Disable(void)
+{
+  CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
+}
+#endif /* RCC_CFGR_MCO2EN */
+
+/**
+  * @brief  Configure MCOx
+  * @rmtoll CFGR         MCO1          LL_RCC_ConfigMCO\n
+  *         CFGR         MCO1PRE       LL_RCC_ConfigMCO\n
+  *         CFGR         MCO2          LL_RCC_ConfigMCO\n
+  *         CFGR         MCO2PRE       LL_RCC_ConfigMCO
+  * @param  MCOxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI
+  *         @arg @ref LL_RCC_MCO1SOURCE_LSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
+  *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
+  *         @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
+  *         @arg @ref LL_RCC_MCO2SOURCE_HSE
+  *         @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
+  * @param  MCOxPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_MCO1_DIV_1
+  *         @arg @ref LL_RCC_MCO1_DIV_2
+  *         @arg @ref LL_RCC_MCO1_DIV_3
+  *         @arg @ref LL_RCC_MCO1_DIV_4
+  *         @arg @ref LL_RCC_MCO1_DIV_5
+  *         @arg @ref LL_RCC_MCO2_DIV_1
+  *         @arg @ref LL_RCC_MCO2_DIV_2
+  *         @arg @ref LL_RCC_MCO2_DIV_3
+  *         @arg @ref LL_RCC_MCO2_DIV_4
+  *         @arg @ref LL_RCC_MCO2_DIV_5
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
+{
+  MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U),  (MCOxSource << 16U) | (MCOxPrescaler << 16U));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
+  * @{
+  */
+#if defined(FMPI2C1)
+/**
+  * @brief  Configure FMPI2C clock source
+  * @rmtoll DCKCFGR2        FMPI2C1SEL       LL_RCC_SetFMPI2CClockSource
+  * @param  FMPI2CxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource);
+}
+#endif /* FMPI2C1 */
+
+#if defined(LPTIM1)
+/**
+  * @brief  Configure LPTIMx clock source
+  * @rmtoll DCKCFGR2        LPTIM1SEL     LL_RCC_SetLPTIMClockSource
+  * @param  LPTIMxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
+}
+#endif /* LPTIM1 */
+
+#if defined(SAI1)
+/**
+  * @brief  Configure SAIx clock source
+  * @rmtoll DCKCFGR        SAI1SRC       LL_RCC_SetSAIClockSource\n
+  *         DCKCFGR        SAI2SRC       LL_RCC_SetSAIClockSource\n
+  *         DCKCFGR        SAI1ASRC      LL_RCC_SetSAIClockSource\n
+  *         DCKCFGR        SAI1BSRC      LL_RCC_SetSAIClockSource
+  * @param  SAIxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL  (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL  (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
+}
+#endif /* SAI1 */
+
+#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
+/**
+  * @brief  Configure SDIO clock source
+  * @rmtoll DCKCFGR         SDIOSEL      LL_RCC_SetSDIOClockSource\n
+  *         DCKCFGR2        SDIOSEL      LL_RCC_SetSDIOClockSource
+  * @param  SDIOxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
+  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)
+{
+#if defined(RCC_DCKCFGR_SDIOSEL)
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource);
+#else
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource);
+#endif /* RCC_DCKCFGR_SDIOSEL */
+}
+#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
+
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+/**
+  * @brief  Configure 48Mhz domain clock source
+  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_SetCK48MClockSource\n
+  *         DCKCFGR2        CK48MSEL      LL_RCC_SetCK48MClockSource
+  * @param  CK48MxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource);
+#else
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+
+#if defined(RNG)
+/**
+  * @brief  Configure RNG clock source
+  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_SetRNGClockSource\n
+  *         DCKCFGR2        CK48MSEL      LL_RCC_SetRNGClockSource
+  * @param  RNGxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource);
+#else
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+#endif /* RNG */
+
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+/**
+  * @brief  Configure USB clock source
+  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_SetUSBClockSource\n
+  *         DCKCFGR2        CK48MSEL      LL_RCC_SetUSBClockSource
+  * @param  USBxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource);
+#else
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+#endif /* USB_OTG_FS || USB_OTG_HS */
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+
+#if defined(CEC)
+/**
+  * @brief  Configure CEC clock source
+  * @rmtoll DCKCFGR2         CECSEL        LL_RCC_SetCECClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
+}
+#endif /* CEC */
+
+/**
+  * @brief  Configure I2S clock source
+  * @rmtoll CFGR         I2SSRC        LL_RCC_SetI2SClockSource\n
+  *         DCKCFGR      I2SSRC        LL_RCC_SetI2SClockSource\n
+  *         DCKCFGR      I2S1SRC       LL_RCC_SetI2SClockSource\n
+  *         DCKCFGR      I2S2SRC       LL_RCC_SetI2SClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
+{
+#if defined(RCC_CFGR_I2SSRC)
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
+#else
+  MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U));
+#endif /* RCC_CFGR_I2SSRC */
+}
+
+#if defined(DSI)
+/**
+  * @brief  Configure DSI clock source
+  * @rmtoll DCKCFGR         DSISEL        LL_RCC_SetDSIClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source);
+}
+#endif /* DSI */
+
+#if defined(DFSDM1_Channel0)
+/**
+  * @brief  Configure DFSDM Audio clock source
+  * @rmtoll DCKCFGR          CKDFSDM1ASEL        LL_RCC_SetDFSDMAudioClockSource\n
+  *         DCKCFGR          CKDFSDM2ASEL        LL_RCC_SetDFSDMAudioClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
+  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
+  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
+  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U));
+}
+
+/**
+  * @brief  Configure DFSDM Kernel clock source
+  * @rmtoll DCKCFGR         CKDFSDM1SEL        LL_RCC_SetDFSDMClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source);
+}
+#endif /* DFSDM1_Channel0 */
+
+#if defined(SPDIFRX)
+/**
+  * @brief  Configure SPDIFRX clock source
+  * @rmtoll DCKCFGR2         SPDIFRXSEL      LL_RCC_SetSPDIFRXClockSource
+  * @param  SPDIFRXxSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)
+{
+  MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource);
+}
+#endif /* SPDIFRX */
+
+#if defined(FMPI2C1)
+/**
+  * @brief  Get FMPI2C clock source
+  * @rmtoll DCKCFGR2        FMPI2C1SEL       LL_RCC_GetFMPI2CClockSource
+  * @param  FMPI2Cx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI
+ */
+__STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx));
+}
+#endif /* FMPI2C1 */
+
+#if defined(LPTIM1)
+/**
+  * @brief  Get LPTIMx clock source
+  * @rmtoll DCKCFGR2        LPTIM1SEL     LL_RCC_GetLPTIMClockSource
+  * @param  LPTIMx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
+}
+#endif /* LPTIM1 */
+
+#if defined(SAI1)
+/**
+  * @brief  Get SAIx clock source
+  * @rmtoll DCKCFGR         SAI1SEL       LL_RCC_GetSAIClockSource\n
+  *         DCKCFGR         SAI2SEL       LL_RCC_GetSAIClockSource\n
+  *         DCKCFGR         SAI1ASRC      LL_RCC_GetSAIClockSource\n
+  *         DCKCFGR         SAI1BSRC      LL_RCC_GetSAIClockSource
+  * @param  SAIx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL  (*)
+  *         @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL  (*)
+  *         @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx);
+}
+#endif /* SAI1 */
+
+#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
+/**
+  * @brief  Get SDIOx clock source
+  * @rmtoll DCKCFGR        SDIOSEL      LL_RCC_GetSDIOClockSource\n
+  *         DCKCFGR2       SDIOSEL      LL_RCC_GetSDIOClockSource
+  * @param  SDIOx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SDIO_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK
+  *         @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx)
+{
+#if defined(RCC_DCKCFGR_SDIOSEL)
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx));
+#else
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx));
+#endif /* RCC_DCKCFGR_SDIOSEL */
+}
+#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
+
+#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
+/**
+  * @brief  Get 48Mhz domain clock source
+  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_GetCK48MClockSource\n
+  *         DCKCFGR2        CK48MSEL      LL_RCC_GetCK48MClockSource
+  * @param  CK48Mx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx));
+#else
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+
+#if defined(RNG)
+/**
+  * @brief  Get RNGx clock source
+  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_GetRNGClockSource\n
+  *         DCKCFGR2        CK48MSEL      LL_RCC_GetRNGClockSource
+  * @param  RNGx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx));
+#else
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+#endif /* RNG */
+
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+/**
+  * @brief  Get USBx clock source
+  * @rmtoll DCKCFGR         CK48MSEL      LL_RCC_GetUSBClockSource\n
+  *         DCKCFGR2        CK48MSEL      LL_RCC_GetUSBClockSource
+  * @param  USBx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*)
+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
+{
+#if defined(RCC_DCKCFGR_CK48MSEL)
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx));
+#else
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
+#endif /* RCC_DCKCFGR_CK48MSEL */
+}
+#endif /* USB_OTG_FS || USB_OTG_HS */
+#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
+
+#if defined(CEC)
+/**
+  * @brief  Get CEC Clock Source
+  * @rmtoll DCKCFGR2         CECSEL        LL_RCC_GetCECClockSource
+  * @param  CECx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
+}
+#endif /* CEC */
+
+/**
+  * @brief  Get I2S Clock Source
+  * @rmtoll CFGR         I2SSRC        LL_RCC_GetI2SClockSource\n
+  *         DCKCFGR      I2SSRC        LL_RCC_GetI2SClockSource\n
+  *         DCKCFGR      I2S1SRC       LL_RCC_GetI2SClockSource\n
+  *         DCKCFGR      I2S2SRC       LL_RCC_GetI2SClockSource
+  * @param  I2Sx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*)
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*)
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*)
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*)
+  *         @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
+{
+#if defined(RCC_CFGR_I2SSRC)
+  return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
+#else
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx);
+#endif /* RCC_CFGR_I2SSRC */
+}
+
+#if defined(DFSDM1_Channel0)
+/**
+  * @brief  Get DFSDM Audio Clock Source
+  * @rmtoll DCKCFGR          CKDFSDM1ASEL        LL_RCC_GetDFSDMAudioClockSource\n
+  *         DCKCFGR          CKDFSDM2ASEL        LL_RCC_GetDFSDMAudioClockSource
+  * @param  DFSDMx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
+  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1
+  *         @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2
+  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*)
+  *         @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx);
+}
+
+/**
+  * @brief  Get DFSDM Audio Clock Source
+  * @rmtoll DCKCFGR         CKDFSDM1SEL        LL_RCC_GetDFSDMClockSource
+  * @param  DFSDMx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*)
+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx));
+}
+#endif /* DFSDM1_Channel0 */
+
+#if defined(SPDIFRX)
+/**
+  * @brief  Get SPDIFRX clock source
+  * @rmtoll DCKCFGR2         SPDIFRXSEL      LL_RCC_GetSPDIFRXClockSource
+  * @param  SPDIFRXx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL
+  *         @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx));
+}
+#endif /* SPDIFRX */
+
+#if defined(DSI)
+/**
+  * @brief  Get DSI Clock Source
+  * @rmtoll DCKCFGR         DSISEL        LL_RCC_GetDSIClockSource
+  * @param  DSIx This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx));
+}
+#endif /* DSI */
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_RTC RTC
+  * @{
+  */
+
+/**
+  * @brief  Set RTC Clock Source
+  * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
+  *       the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
+  *       set). The BDRST bit can be used to reset them.
+  * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
+{
+  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
+}
+
+/**
+  * @brief  Get RTC Clock Source
+  * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
+}
+
+/**
+  * @brief  Enable RTC
+  * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableRTC(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+  * @brief  Disable RTC
+  * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableRTC(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
+}
+
+/**
+  * @brief  Check if RTC has been enabled or not
+  * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
+{
+  return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
+}
+
+/**
+  * @brief  Force the Backup domain reset
+  * @rmtoll BDCR         BDRST         LL_RCC_ForceBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
+{
+  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+  * @brief  Release the Backup domain reset
+  * @rmtoll BDCR         BDRST         LL_RCC_ReleaseBackupDomainReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
+{
+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
+}
+
+/**
+  * @brief  Set HSE Prescalers for RTC Clock
+  * @rmtoll CFGR         RTCPRE        LL_RCC_SetRTC_HSEPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_NOCLOCK
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
+}
+
+/**
+  * @brief  Get HSE Prescalers for RTC Clock
+  * @rmtoll CFGR         RTCPRE        LL_RCC_GetRTC_HSEPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_RTC_NOCLOCK
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_3
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_5
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_6
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_7
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_9
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_10
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_11
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_12
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_13
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_14
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_15
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_17
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_18
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_19
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_20
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_21
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_22
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_23
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_24
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_25
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_26
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_27
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_28
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_29
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_30
+  *         @arg @ref LL_RCC_RTC_HSE_DIV_31
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
+}
+
+/**
+  * @}
+  */
+
+#if defined(RCC_DCKCFGR_TIMPRE)
+/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
+  * @{
+  */
+
+/**
+  * @brief  Set Timers Clock Prescalers
+  * @rmtoll DCKCFGR         TIMPRE        LL_RCC_SetTIMPrescaler
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
+{
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler);
+}
+
+/**
+  * @brief  Get Timers Clock Prescalers
+  * @rmtoll DCKCFGR         TIMPRE        LL_RCC_GetTIMPrescaler
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE
+  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
+  */
+__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE));
+}
+
+/**
+  * @}
+  */
+#endif /* RCC_DCKCFGR_TIMPRE */
+
+/** @defgroup RCC_LL_EF_PLL PLL
+  * @{
+  */
+
+/**
+  * @brief  Enable PLL
+  * @rmtoll CR           PLLON         LL_RCC_PLL_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+  * @brief  Disable PLL
+  * @note Cannot be disabled if the PLL clock is used as the system clock
+  * @rmtoll CR           PLLON         LL_RCC_PLL_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+}
+
+/**
+  * @brief  Check if PLL Ready
+  * @rmtoll CR           PLLRDY        LL_RCC_PLL_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
+}
+
+/**
+  * @brief  Configure PLL used for SYSCLK Domain
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLP can be written only when PLL is disabled
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SYS\n
+  *         PLLCFGR      PLLP          LL_RCC_PLL_ConfigDomain_SYS
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLP_R This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_2
+  *         @arg @ref LL_RCC_PLLP_DIV_4
+  *         @arg @ref LL_RCC_PLLP_DIV_6
+  *         @arg @ref LL_RCC_PLLP_DIV_8
+  *         @arg @ref LL_RCC_PLLR_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLR_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLR_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLR_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLR_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLR_DIV_7 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos);
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R);
+#if defined(RCC_PLLR_SYSCLK_SUPPORT)
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R);
+#endif /* RCC_PLLR_SYSCLK_SUPPORT */
+}
+
+/**
+  * @brief  Configure PLL used for 48Mhz domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLQ can be written only when PLL is disabled
+  * @note This  can be selected for USB, RNG, SDIO
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_48M\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_48M\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_48M\n
+  *         PLLCFGR      PLLQ          LL_RCC_PLL_ConfigDomain_48M
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLQ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLQ_DIV_2
+  *         @arg @ref LL_RCC_PLLQ_DIV_3
+  *         @arg @ref LL_RCC_PLLQ_DIV_4
+  *         @arg @ref LL_RCC_PLLQ_DIV_5
+  *         @arg @ref LL_RCC_PLLQ_DIV_6
+  *         @arg @ref LL_RCC_PLLQ_DIV_7
+  *         @arg @ref LL_RCC_PLLQ_DIV_8
+  *         @arg @ref LL_RCC_PLLQ_DIV_9
+  *         @arg @ref LL_RCC_PLLQ_DIV_10
+  *         @arg @ref LL_RCC_PLLQ_DIV_11
+  *         @arg @ref LL_RCC_PLLQ_DIV_12
+  *         @arg @ref LL_RCC_PLLQ_DIV_13
+  *         @arg @ref LL_RCC_PLLQ_DIV_14
+  *         @arg @ref LL_RCC_PLLQ_DIV_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
+}
+
+#if defined(DSI)
+/**
+  * @brief  Configure PLL used for DSI clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLR can be written only when PLL is disabled
+  * @note This  can be selected for DSI
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_DSI\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_DSI\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_DSI\n
+  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_DSI
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
+}
+#endif /* DSI */
+
+#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
+/**
+  * @brief  Configure PLL used for I2S clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLR can be written only when PLL is disabled
+  * @note This  can be selected for I2S
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_I2S\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_I2S\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_I2S\n
+  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_I2S
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
+}
+#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
+
+#if defined(SPDIFRX)
+/**
+  * @brief  Configure PLL used for SPDIFRX clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLR can be written only when PLL is disabled
+  * @note This  can be selected for SPDIFRX
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SPDIFRX\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SPDIFRX\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SPDIFRX\n
+  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SPDIFRX
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
+}
+#endif /* SPDIFRX */
+
+#if defined(RCC_PLLCFGR_PLLR)
+#if defined(SAI1)
+/**
+  * @brief  Configure PLL used for SAI clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI are disabled
+  * @note PLLN/PLLR can be written only when PLL is disabled
+  * @note This  can be selected for SAI
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLM          LL_RCC_PLL_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLN          LL_RCC_PLL_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLR          LL_RCC_PLL_ConfigDomain_SAI\n
+  *         DCKCFGR      PLLDIVR       LL_RCC_PLL_ConfigDomain_SAI
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  * @param  PLLDIVR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_1 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_7 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_8 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_9 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_10 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_11 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_12 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_13 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_14 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_15 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_16 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_17 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_18 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_19 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_20 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_21 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_22 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_23 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_24 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_25 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_26 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_27 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_28 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_29 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_30 (*)
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_31 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+#if defined(RCC_DCKCFGR_PLLDIVR)
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
+#else
+__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+#endif /* RCC_DCKCFGR_PLLDIVR */
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
+             Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
+#if defined(RCC_DCKCFGR_PLLDIVR)
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR);
+#endif /* RCC_DCKCFGR_PLLDIVR */
+}
+#endif /* SAI1 */
+#endif /* RCC_PLLCFGR_PLLR */
+
+/**
+  * @brief  Configure PLL clock source
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_SetMainSource
+  * @param PLLSource This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
+}
+
+/**
+  * @brief  Get the oscillator used as PLL clock source.
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLL_GetMainSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
+}
+
+/**
+  * @brief  Get Main PLL multiplication factor for VCO
+  * @rmtoll PLLCFGR      PLLN          LL_RCC_PLL_GetN
+  * @retval Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >>  RCC_PLLCFGR_PLLN_Pos);
+}
+
+/**
+  * @brief  Get Main PLL division factor for PLLP 
+  * @rmtoll PLLCFGR      PLLP       LL_RCC_PLL_GetP
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLP_DIV_2
+  *         @arg @ref LL_RCC_PLLP_DIV_4
+  *         @arg @ref LL_RCC_PLLP_DIV_6
+  *         @arg @ref LL_RCC_PLLP_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
+}
+
+/**
+  * @brief  Get Main PLL division factor for PLLQ
+  * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock)
+  * @rmtoll PLLCFGR      PLLQ          LL_RCC_PLL_GetQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLQ_DIV_2
+  *         @arg @ref LL_RCC_PLLQ_DIV_3
+  *         @arg @ref LL_RCC_PLLQ_DIV_4
+  *         @arg @ref LL_RCC_PLLQ_DIV_5
+  *         @arg @ref LL_RCC_PLLQ_DIV_6
+  *         @arg @ref LL_RCC_PLLQ_DIV_7
+  *         @arg @ref LL_RCC_PLLQ_DIV_8
+  *         @arg @ref LL_RCC_PLLQ_DIV_9
+  *         @arg @ref LL_RCC_PLLQ_DIV_10
+  *         @arg @ref LL_RCC_PLLQ_DIV_11
+  *         @arg @ref LL_RCC_PLLQ_DIV_12
+  *         @arg @ref LL_RCC_PLLQ_DIV_13
+  *         @arg @ref LL_RCC_PLLQ_DIV_14
+  *         @arg @ref LL_RCC_PLLQ_DIV_15
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
+}
+
+#if defined(RCC_PLLCFGR_PLLR)
+/**
+  * @brief  Get Main PLL division factor for PLLR
+  * @note used for PLLCLK (system clock)
+  * @rmtoll PLLCFGR      PLLR          LL_RCC_PLL_GetR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLR_DIV_2
+  *         @arg @ref LL_RCC_PLLR_DIV_3
+  *         @arg @ref LL_RCC_PLLR_DIV_4
+  *         @arg @ref LL_RCC_PLLR_DIV_5
+  *         @arg @ref LL_RCC_PLLR_DIV_6
+  *         @arg @ref LL_RCC_PLLR_DIV_7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
+}
+#endif /* RCC_PLLCFGR_PLLR */
+
+#if defined(RCC_DCKCFGR_PLLDIVR)
+/**
+  * @brief  Get Main PLL division factor for PLLDIVR
+  * @note used for PLLSAICLK (SAI1 and SAI2 clock)
+  * @rmtoll DCKCFGR      PLLDIVR          LL_RCC_PLL_GetDIVR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_1
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_2
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_3
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_4
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_5
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_6
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_7
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_8
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_9
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_10
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_11
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_12
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_13
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_14
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_15
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_16
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_17
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_18
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_19
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_20
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_21
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_22
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_23
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_24
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_25
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_26
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_27
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_28
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_29
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_30
+  *         @arg @ref LL_RCC_PLLDIVR_DIV_31
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR));
+}
+#endif /* RCC_DCKCFGR_PLLDIVR */
+
+/**
+  * @brief  Get Division factor for the main PLL and other PLL
+  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLL_GetDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLM_DIV_2
+  *         @arg @ref LL_RCC_PLLM_DIV_3
+  *         @arg @ref LL_RCC_PLLM_DIV_4
+  *         @arg @ref LL_RCC_PLLM_DIV_5
+  *         @arg @ref LL_RCC_PLLM_DIV_6
+  *         @arg @ref LL_RCC_PLLM_DIV_7
+  *         @arg @ref LL_RCC_PLLM_DIV_8
+  *         @arg @ref LL_RCC_PLLM_DIV_9
+  *         @arg @ref LL_RCC_PLLM_DIV_10
+  *         @arg @ref LL_RCC_PLLM_DIV_11
+  *         @arg @ref LL_RCC_PLLM_DIV_12
+  *         @arg @ref LL_RCC_PLLM_DIV_13
+  *         @arg @ref LL_RCC_PLLM_DIV_14
+  *         @arg @ref LL_RCC_PLLM_DIV_15
+  *         @arg @ref LL_RCC_PLLM_DIV_16
+  *         @arg @ref LL_RCC_PLLM_DIV_17
+  *         @arg @ref LL_RCC_PLLM_DIV_18
+  *         @arg @ref LL_RCC_PLLM_DIV_19
+  *         @arg @ref LL_RCC_PLLM_DIV_20
+  *         @arg @ref LL_RCC_PLLM_DIV_21
+  *         @arg @ref LL_RCC_PLLM_DIV_22
+  *         @arg @ref LL_RCC_PLLM_DIV_23
+  *         @arg @ref LL_RCC_PLLM_DIV_24
+  *         @arg @ref LL_RCC_PLLM_DIV_25
+  *         @arg @ref LL_RCC_PLLM_DIV_26
+  *         @arg @ref LL_RCC_PLLM_DIV_27
+  *         @arg @ref LL_RCC_PLLM_DIV_28
+  *         @arg @ref LL_RCC_PLLM_DIV_29
+  *         @arg @ref LL_RCC_PLLM_DIV_30
+  *         @arg @ref LL_RCC_PLLM_DIV_31
+  *         @arg @ref LL_RCC_PLLM_DIV_32
+  *         @arg @ref LL_RCC_PLLM_DIV_33
+  *         @arg @ref LL_RCC_PLLM_DIV_34
+  *         @arg @ref LL_RCC_PLLM_DIV_35
+  *         @arg @ref LL_RCC_PLLM_DIV_36
+  *         @arg @ref LL_RCC_PLLM_DIV_37
+  *         @arg @ref LL_RCC_PLLM_DIV_38
+  *         @arg @ref LL_RCC_PLLM_DIV_39
+  *         @arg @ref LL_RCC_PLLM_DIV_40
+  *         @arg @ref LL_RCC_PLLM_DIV_41
+  *         @arg @ref LL_RCC_PLLM_DIV_42
+  *         @arg @ref LL_RCC_PLLM_DIV_43
+  *         @arg @ref LL_RCC_PLLM_DIV_44
+  *         @arg @ref LL_RCC_PLLM_DIV_45
+  *         @arg @ref LL_RCC_PLLM_DIV_46
+  *         @arg @ref LL_RCC_PLLM_DIV_47
+  *         @arg @ref LL_RCC_PLLM_DIV_48
+  *         @arg @ref LL_RCC_PLLM_DIV_49
+  *         @arg @ref LL_RCC_PLLM_DIV_50
+  *         @arg @ref LL_RCC_PLLM_DIV_51
+  *         @arg @ref LL_RCC_PLLM_DIV_52
+  *         @arg @ref LL_RCC_PLLM_DIV_53
+  *         @arg @ref LL_RCC_PLLM_DIV_54
+  *         @arg @ref LL_RCC_PLLM_DIV_55
+  *         @arg @ref LL_RCC_PLLM_DIV_56
+  *         @arg @ref LL_RCC_PLLM_DIV_57
+  *         @arg @ref LL_RCC_PLLM_DIV_58
+  *         @arg @ref LL_RCC_PLLM_DIV_59
+  *         @arg @ref LL_RCC_PLLM_DIV_60
+  *         @arg @ref LL_RCC_PLLM_DIV_61
+  *         @arg @ref LL_RCC_PLLM_DIV_62
+  *         @arg @ref LL_RCC_PLLM_DIV_63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
+}
+
+/**
+  * @brief  Configure Spread Spectrum used for PLL
+  * @note These bits must be written before enabling PLL
+  * @rmtoll SSCGR        MODPER        LL_RCC_PLL_ConfigSpreadSpectrum\n
+  *         SSCGR        INCSTEP       LL_RCC_PLL_ConfigSpreadSpectrum\n
+  *         SSCGR        SPREADSEL     LL_RCC_PLL_ConfigSpreadSpectrum
+  * @param  Mod Between Min_Data=0 and Max_Data=8191
+  * @param  Inc Between Min_Data=0 and Max_Data=32767
+  * @param  Sel This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_SPREAD_SELECT_CENTER
+  *         @arg @ref LL_RCC_SPREAD_SELECT_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
+{
+  MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
+}
+
+/**
+  * @brief  Get Spread Spectrum Modulation Period for PLL
+  * @rmtoll SSCGR         MODPER        LL_RCC_PLL_GetPeriodModulation
+  * @retval Between Min_Data=0 and Max_Data=8191
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
+{
+  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
+}
+
+/**
+  * @brief  Get Spread Spectrum Incrementation Step for PLL
+  * @note Must be written before enabling PLL
+  * @rmtoll SSCGR         INCSTEP        LL_RCC_PLL_GetStepIncrementation
+  * @retval Between Min_Data=0 and Max_Data=32767
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
+{
+  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
+}
+
+/**
+  * @brief  Get Spread Spectrum Selection for PLL
+  * @note Must be written before enabling PLL
+  * @rmtoll SSCGR         SPREADSEL        LL_RCC_PLL_GetSpreadSelection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_SPREAD_SELECT_CENTER
+  *         @arg @ref LL_RCC_SPREAD_SELECT_DOWN
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
+{
+  return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
+}
+
+/**
+  * @brief  Enable Spread Spectrum for PLL.
+  * @rmtoll SSCGR         SSCGEN         LL_RCC_PLL_SpreadSpectrum_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
+{
+  SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
+}
+
+/**
+  * @brief  Disable Spread Spectrum for PLL.
+  * @rmtoll SSCGR         SSCGEN         LL_RCC_PLL_SpreadSpectrum_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
+{
+  CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
+}
+
+/**
+  * @}
+  */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
+  * @{
+  */
+
+/**
+  * @brief  Enable PLLI2S
+  * @rmtoll CR           PLLI2SON     LL_RCC_PLLI2S_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
+}
+
+/**
+  * @brief  Disable PLLI2S
+  * @rmtoll CR           PLLI2SON     LL_RCC_PLLI2S_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
+}
+
+/**
+  * @brief  Check if PLLI2S Ready
+  * @rmtoll CR           PLLI2SRDY    LL_RCC_PLLI2S_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
+}
+
+#if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR))
+/**
+  * @brief  Configure PLLI2S used for SAI domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled
+  * @note This can be selected for SAI
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         PLLI2SCFGR   PLLI2SQ       LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         PLLI2SCFGR   PLLI2SR       LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         DCKCFGR      PLLI2SDIVQ    LL_RCC_PLLI2S_ConfigDomain_SAI\n
+  *         DCKCFGR      PLLI2SDIVR    LL_RCC_PLLI2S_ConfigDomain_SAI
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  * @param  PLLN Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLQ_R This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*)
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_7 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLDIVQ_R This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*)
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
+  MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
+#else
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos);
+#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R);
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R);
+#else
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R);
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R);
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
+}
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
+/**
+  * @brief  Configure PLLI2S used for 48Mhz domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLQ can be written only when PLLI2S is disabled
+  * @note This can be selected for RNG, USB, SDIO
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_48M\n
+  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_ConfigDomain_48M\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_48M\n
+  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_48M\n
+  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_48M\n
+  *         PLLI2SCFGR   PLLI2SQ       LL_RCC_PLLI2S_ConfigDomain_48M
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLQ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
+  MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
+#else
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ);
+}
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
+
+#if defined(SPDIFRX)
+/**
+  * @brief Configure PLLI2S used for SPDIFRX domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLP can be written only when PLLI2S is disabled
+  * @note This  can be selected for SPDIFRX
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
+  *         PLLI2SCFGR   PLLI2SP       LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLP This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
+#else
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP);
+}
+#endif /* SPDIFRX */
+
+/**
+  * @brief  Configure PLLI2S used for I2S1 domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLR can be written only when PLLI2S is disabled
+  * @note This  can be selected for I2S
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_ConfigDomain_I2S\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLI2S_ConfigDomain_I2S\n
+  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_ConfigDomain_I2S\n
+  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_ConfigDomain_I2S\n
+  *         PLLI2SCFGR   PLLI2SN       LL_RCC_PLLI2S_ConfigDomain_I2S\n
+  *         PLLI2SCFGR   PLLI2SR       LL_RCC_PLLI2S_ConfigDomain_I2S
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  * @param  PLLN Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_7
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
+  MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
+#else
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+  MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
+}
+
+/**
+  * @brief  Get I2SPLL multiplication factor for VCO
+  * @rmtoll PLLI2SCFGR  PLLI2SN      LL_RCC_PLLI2S_GetN
+  * @retval Between 50/192(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+}
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
+/**
+  * @brief  Get I2SPLL division factor for PLLI2SQ
+  * @rmtoll PLLI2SCFGR  PLLI2SQ      LL_RCC_PLLI2S_GetQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SQ_DIV_15
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
+}
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
+
+/**
+  * @brief  Get I2SPLL division factor for PLLI2SR
+  * @note used for PLLI2SCLK (I2S clock)
+  * @rmtoll PLLI2SCFGR  PLLI2SR      LL_RCC_PLLI2S_GetR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SR_DIV_7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
+}
+
+#if defined(RCC_PLLI2SCFGR_PLLI2SP)
+/**
+  * @brief  Get I2SPLL division factor for PLLI2SP
+  * @note used for PLLSPDIFRXCLK (SPDIFRX clock)
+  * @rmtoll PLLI2SCFGR  PLLI2SP      LL_RCC_PLLI2S_GetP
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SP_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
+}
+#endif /* RCC_PLLI2SCFGR_PLLI2SP */
+
+#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
+/**
+  * @brief  Get I2SPLL division factor for PLLI2SDIVQ
+  * @note used PLLSAICLK selected (SAI clock)
+  * @rmtoll DCKCFGR   PLLI2SDIVQ      LL_RCC_PLLI2S_GetDIVQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ));
+}
+#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
+
+#if defined(RCC_DCKCFGR_PLLI2SDIVR)
+/**
+  * @brief  Get I2SPLL division factor for PLLI2SDIVR
+  * @note used PLLSAICLK selected (SAI clock)
+  * @rmtoll DCKCFGR   PLLI2SDIVR      LL_RCC_PLLI2S_GetDIVR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_1
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SDIVR_DIV_31
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR));
+}
+#endif /* RCC_DCKCFGR_PLLI2SDIVR */
+
+/**
+  * @brief  Get division factor for PLLI2S input clock
+  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLLI2S_GetDivider\n
+  *         PLLI2SCFGR   PLLI2SM       LL_RCC_PLLI2S_GetDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_2
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_3
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_4
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_5
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_6
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_7
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_8
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_9
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_10
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_11
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_12
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_13
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_14
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_15
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_16
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_17
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_18
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_19
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_20
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_21
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_22
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_23
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_24
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_25
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_26
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_27
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_28
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_29
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_30
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_31
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_32
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_33
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_34
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_35
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_36
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_37
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_38
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_39
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_40
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_41
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_42
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_43
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_44
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_45
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_46
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_47
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_48
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_49
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_50
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_51
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_52
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_53
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_54
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_55
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_56
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_57
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_58
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_59
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_60
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_61
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_62
+  *         @arg @ref LL_RCC_PLLI2SM_DIV_63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)
+{
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+  return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM));
+#else
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+}
+
+/**
+  * @brief  Get the oscillator used as PLL clock source.
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLI2S_GetMainSource\n
+  *         PLLI2SCFGR   PLLI2SSRC     LL_RCC_PLLI2S_GetMainSource
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  *         @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*)
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)
+{
+#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
+  uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
+  uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
+  uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
+  return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1);
+#else
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
+#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
+}
+
+/**
+  * @}
+  */
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/** @defgroup RCC_LL_EF_PLLSAI PLLSAI
+  * @{
+  */
+
+/**
+  * @brief  Enable PLLSAI
+  * @rmtoll CR           PLLSAION     LL_RCC_PLLSAI_Enable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
+{
+  SET_BIT(RCC->CR, RCC_CR_PLLSAION);
+}
+
+/**
+  * @brief  Disable PLLSAI
+  * @rmtoll CR           PLLSAION     LL_RCC_PLLSAI_Disable
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
+{
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
+}
+
+/**
+  * @brief  Check if PLLSAI Ready
+  * @rmtoll CR           PLLSAIRDY    LL_RCC_PLLSAI_IsReady
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
+{
+  return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
+}
+
+/**
+  * @brief  Configure PLLSAI used for SAI domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLQ can be written only when PLLSAI is disabled
+  * @note This can be selected for SAI
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_SAI\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_SAI\n
+  *         PLLSAICFGR   PLLSAIM       LL_RCC_PLLSAI_ConfigDomain_SAI\n
+  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_SAI\n
+  *         PLLSAICFGR   PLLSAIQ       LL_RCC_PLLSAI_ConfigDomain_SAI\n
+  *         DCKCFGR      PLLSAIDIVQ    LL_RCC_PLLSAI_ConfigDomain_SAI
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
+  * @param  PLLN Between 49/50(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLQ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15
+  * @param  PLLDIVQ This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+#if defined(RCC_PLLSAICFGR_PLLSAIM)
+  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
+#else
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLSAICFGR_PLLSAIM */
+  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ);
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ);
+}
+
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+/**
+  * @brief Configure PLLSAI used for 48Mhz domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLP can be written only when PLLSAI is disabled
+  * @note This  can be selected for USB, RNG, SDIO
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_48M\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_48M\n
+  *         PLLSAICFGR   PLLSAIM       LL_RCC_PLLSAI_ConfigDomain_48M\n
+  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_48M\n
+  *         PLLSAICFGR   PLLSAIP       LL_RCC_PLLSAI_ConfigDomain_48M
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
+  * @param  PLLN Between 50 and 432
+  * @param  PLLP This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
+#if defined(RCC_PLLSAICFGR_PLLSAIM)
+  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
+#else
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
+#endif /* RCC_PLLSAICFGR_PLLSAIM */
+  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP);
+}
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+
+#if defined(LTDC)
+/**
+  * @brief  Configure PLLSAI used for LTDC domain clock
+  * @note PLL Source and PLLM Divider can be written only when PLL,
+  *       PLLI2S and PLLSAI(*) are disabled
+  * @note PLLN/PLLR can be written only when PLLSAI is disabled
+  * @note This  can be selected for LTDC
+  * @rmtoll PLLCFGR      PLLSRC        LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+  *         PLLCFGR      PLLM          LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+  *         PLLSAICFGR   PLLSAIN       LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+  *         PLLSAICFGR   PLLSAIR       LL_RCC_PLLSAI_ConfigDomain_LTDC\n
+  *         DCKCFGR      PLLSAIDIVR    LL_RCC_PLLSAI_ConfigDomain_LTDC
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSOURCE_HSI
+  *         @arg @ref LL_RCC_PLLSOURCE_HSE
+  * @param  PLLM This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
+  * @param  PLLN Between 49/50(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  * @param  PLLR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_7
+  * @param  PLLDIVR This parameter can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
+{
+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
+  MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR);
+  MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR);
+}
+#endif /* LTDC */
+
+/**
+  * @brief  Get division factor for PLLSAI input clock
+  * @rmtoll PLLCFGR      PLLM          LL_RCC_PLLSAI_GetDivider\n
+  *         PLLSAICFGR   PLLSAIM       LL_RCC_PLLSAI_GetDivider
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_32
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_33
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_34
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_35
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_36
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_37
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_38
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_39
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_40
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_41
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_42
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_43
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_44
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_45
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_46
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_47
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_48
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_49
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_50
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_51
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_52
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_53
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_54
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_55
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_56
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_57
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_58
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_59
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_60
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_61
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_62
+  *         @arg @ref LL_RCC_PLLSAIM_DIV_63
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void)
+{
+#if defined(RCC_PLLSAICFGR_PLLSAIM)
+  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM));
+#else
+  return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
+#endif /* RCC_PLLSAICFGR_PLLSAIM */
+}
+
+/**
+  * @brief  Get SAIPLL multiplication factor for VCO
+  * @rmtoll PLLSAICFGR  PLLSAIN      LL_RCC_PLLSAI_GetN
+  * @retval Between 49/50(*) and 432
+  *
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+}
+
+/**
+  * @brief  Get SAIPLL division factor for PLLSAIQ
+  * @rmtoll PLLSAICFGR  PLLSAIQ      LL_RCC_PLLSAI_GetQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIQ_DIV_15
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
+}
+
+#if defined(RCC_PLLSAICFGR_PLLSAIR)
+/**
+  * @brief  Get SAIPLL division factor for PLLSAIR
+  * @note used for PLLSAICLK (SAI clock)
+  * @rmtoll PLLSAICFGR  PLLSAIR      LL_RCC_PLLSAI_GetR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIR_DIV_7
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
+}
+#endif /* RCC_PLLSAICFGR_PLLSAIR */
+
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+/**
+  * @brief  Get SAIPLL division factor for PLLSAIP
+  * @note used for PLL48MCLK (48M domain clock)
+  * @rmtoll PLLSAICFGR  PLLSAIP      LL_RCC_PLLSAI_GetP
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIP_DIV_8
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
+{
+  return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
+}
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+
+/**
+  * @brief  Get SAIPLL division factor for PLLSAIDIVQ
+  * @note used PLLSAICLK selected (SAI clock)
+  * @rmtoll DCKCFGR   PLLSAIDIVQ      LL_RCC_PLLSAI_GetDIVQ
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
+  *         @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ));
+}
+
+#if defined(RCC_DCKCFGR_PLLSAIDIVR)
+/**
+  * @brief  Get SAIPLL division factor for PLLSAIDIVR
+  * @note used for LTDC domain clock
+  * @rmtoll DCKCFGR  PLLSAIDIVR      LL_RCC_PLLSAI_GetDIVR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
+  *         @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
+  */
+__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
+{
+  return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR));
+}
+#endif /* RCC_DCKCFGR_PLLSAIDIVR */
+
+/**
+  * @}
+  */
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Clear LSI ready interrupt flag
+  * @rmtoll CIR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
+}
+
+/**
+  * @brief  Clear LSE ready interrupt flag
+  * @rmtoll CIR         LSERDYC       LL_RCC_ClearFlag_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
+}
+
+/**
+  * @brief  Clear HSI ready interrupt flag
+  * @rmtoll CIR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
+}
+
+/**
+  * @brief  Clear HSE ready interrupt flag
+  * @rmtoll CIR         HSERDYC       LL_RCC_ClearFlag_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
+}
+
+/**
+  * @brief  Clear PLL ready interrupt flag
+  * @rmtoll CIR         PLLRDYC       LL_RCC_ClearFlag_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+  * @brief  Clear PLLI2S ready interrupt flag
+  * @rmtoll CIR         PLLI2SRDYC   LL_RCC_ClearFlag_PLLI2SRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
+}
+
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+  * @brief  Clear PLLSAI ready interrupt flag
+  * @rmtoll CIR         PLLSAIRDYC   LL_RCC_ClearFlag_PLLSAIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
+}
+
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+  * @brief  Clear Clock security system interrupt flag
+  * @rmtoll CIR         CSSC          LL_RCC_ClearFlag_HSECSS
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_CSSC);
+}
+
+/**
+  * @brief  Check if LSI ready interrupt occurred or not
+  * @rmtoll CIR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
+}
+
+/**
+  * @brief  Check if LSE ready interrupt occurred or not
+  * @rmtoll CIR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
+}
+
+/**
+  * @brief  Check if HSI ready interrupt occurred or not
+  * @rmtoll CIR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
+}
+
+/**
+  * @brief  Check if HSE ready interrupt occurred or not
+  * @rmtoll CIR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
+}
+
+/**
+  * @brief  Check if PLL ready interrupt occurred or not
+  * @rmtoll CIR         PLLRDYF       LL_RCC_IsActiveFlag_PLLRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+  * @brief  Check if PLLI2S ready interrupt occurred or not
+  * @rmtoll CIR         PLLI2SRDYF   LL_RCC_IsActiveFlag_PLLI2SRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+  * @brief  Check if PLLSAI ready interrupt occurred or not
+  * @rmtoll CIR         PLLSAIRDYF   LL_RCC_IsActiveFlag_PLLSAIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
+}
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+  * @brief  Check if Clock security system interrupt occurred or not
+  * @rmtoll CIR         CSSF          LL_RCC_IsActiveFlag_HSECSS
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
+}
+
+/**
+  * @brief  Check if RCC flag Independent Watchdog reset is set or not.
+  * @rmtoll CSR          IWDGRSTF      LL_RCC_IsActiveFlag_IWDGRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Low Power reset is set or not.
+  * @rmtoll CSR          LPWRRSTF      LL_RCC_IsActiveFlag_LPWRRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Pin reset is set or not.
+  * @rmtoll CSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag POR/PDR reset is set or not.
+  * @rmtoll CSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Software reset is set or not.
+  * @rmtoll CSR          SFTRSTF       LL_RCC_IsActiveFlag_SFTRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
+}
+
+/**
+  * @brief  Check if RCC flag Window Watchdog reset is set or not.
+  * @rmtoll CSR          WWDGRSTF      LL_RCC_IsActiveFlag_WWDGRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
+}
+
+#if defined(RCC_CSR_BORRSTF)
+/**
+  * @brief  Check if RCC flag BOR reset is set or not.
+  * @rmtoll CSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
+{
+  return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
+}
+#endif /* RCC_CSR_BORRSTF */
+
+/**
+  * @brief  Set RMVF bit to clear the reset flags.
+  * @rmtoll CSR          RMVF          LL_RCC_ClearResetFlags
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
+{
+  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_IT_Management IT Management
+  * @{
+  */
+
+/**
+  * @brief  Enable LSI ready interrupt
+  * @rmtoll CIR         LSIRDYIE      LL_RCC_EnableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
+}
+
+/**
+  * @brief  Enable LSE ready interrupt
+  * @rmtoll CIR         LSERDYIE      LL_RCC_EnableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
+}
+
+/**
+  * @brief  Enable HSI ready interrupt
+  * @rmtoll CIR         HSIRDYIE      LL_RCC_EnableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
+}
+
+/**
+  * @brief  Enable HSE ready interrupt
+  * @rmtoll CIR         HSERDYIE      LL_RCC_EnableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
+}
+
+/**
+  * @brief  Enable PLL ready interrupt
+  * @rmtoll CIR         PLLRDYIE      LL_RCC_EnableIT_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+  * @brief  Enable PLLI2S ready interrupt
+  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_EnableIT_PLLI2SRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
+}
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+  * @brief  Enable PLLSAI ready interrupt
+  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_EnableIT_PLLSAIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
+{
+  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
+}
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+  * @brief  Disable LSI ready interrupt
+  * @rmtoll CIR         LSIRDYIE      LL_RCC_DisableIT_LSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
+}
+
+/**
+  * @brief  Disable LSE ready interrupt
+  * @rmtoll CIR         LSERDYIE      LL_RCC_DisableIT_LSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
+}
+
+/**
+  * @brief  Disable HSI ready interrupt
+  * @rmtoll CIR         HSIRDYIE      LL_RCC_DisableIT_HSIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
+}
+
+/**
+  * @brief  Disable HSE ready interrupt
+  * @rmtoll CIR         HSERDYIE      LL_RCC_DisableIT_HSERDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
+}
+
+/**
+  * @brief  Disable PLL ready interrupt
+  * @rmtoll CIR         PLLRDYIE      LL_RCC_DisableIT_PLLRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+  * @brief  Disable PLLI2S ready interrupt
+  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_DisableIT_PLLI2SRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
+}
+
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+  * @brief  Disable PLLSAI ready interrupt
+  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_DisableIT_PLLSAIRDY
+  * @retval None
+  */
+__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
+{
+  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
+}
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+  * @brief  Checks if LSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         LSIRDYIE      LL_RCC_IsEnabledIT_LSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
+}
+
+/**
+  * @brief  Checks if LSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         LSERDYIE      LL_RCC_IsEnabledIT_LSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
+}
+
+/**
+  * @brief  Checks if HSI ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         HSIRDYIE      LL_RCC_IsEnabledIT_HSIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
+}
+
+/**
+  * @brief  Checks if HSE ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         HSERDYIE      LL_RCC_IsEnabledIT_HSERDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
+}
+
+/**
+  * @brief  Checks if PLL ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         PLLRDYIE      LL_RCC_IsEnabledIT_PLLRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
+}
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+  * @brief  Checks if PLLI2S ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         PLLI2SRDYIE  LL_RCC_IsEnabledIT_PLLI2SRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
+}
+
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+  * @brief  Checks if PLLSAI ready interrupt source is enabled or disabled.
+  * @rmtoll CIR         PLLSAIRDYIE  LL_RCC_IsEnabledIT_PLLSAIRDY
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
+{
+  return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
+}
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup RCC_LL_EF_Init De-initialization function
+  * @{
+  */
+ErrorStatus LL_RCC_DeInit(void);
+/**
+  * @}
+  */
+
+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
+  * @{
+  */
+void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
+#if defined(FMPI2C1)
+uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource);
+#endif /* FMPI2C1 */
+#if defined(LPTIM1)
+uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
+#endif /* LPTIM1 */
+#if defined(SAI1)
+uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
+#endif /* SAI1 */
+#if defined(SDIO)
+uint32_t    LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource);
+#endif /* SDIO */
+#if defined(RNG)
+uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
+#endif /* RNG */
+#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
+uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
+#endif /* USB_OTG_FS || USB_OTG_HS */
+#if defined(DFSDM1_Channel0)
+uint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
+uint32_t    LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
+#endif /* DFSDM1_Channel0 */
+uint32_t    LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
+#if defined(CEC)
+uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);
+#endif /* CEC */
+#if defined(LTDC)
+uint32_t    LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
+#endif /* LTDC */
+#if defined(SPDIFRX)
+uint32_t    LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
+#endif /* SPDIFRX */
+#if defined(DSI)
+uint32_t    LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
+#endif /* DSI */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined(RCC) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_RCC_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h
index 84ea5c4..48bcc1a 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_system.h
@@ -1,1711 +1,1711 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_ll_system.h
-  * @author  MCD Application Team
-  * @brief   Header file of SYSTEM LL module.
-  *
-  ******************************************************************************
-  * @attention
-  *
-  *Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The LL SYSTEM driver contains a set of generic APIs that can be
-    used by user:
-      (+) Some of the FLASH features need to be handled in the SYSTEM file.
-      (+) Access to DBGCMU registers
-      (+) Access to SYSCFG registers
-
-  @endverbatim
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_SYSTEM_H
-#define __STM32F4xx_LL_SYSTEM_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_LL_Driver
-  * @{
-  */
-
-#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
-
-/** @defgroup SYSTEM_LL SYSTEM
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
-  * @{
-  */
-
-/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
-* @{
-*/
-#define LL_SYSCFG_REMAP_FLASH              (uint32_t)0x00000000                                  /*!< Main Flash memory mapped at 0x00000000              */
-#define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0                              /*!< System Flash memory mapped at 0x00000000            */
-#if defined(FSMC_Bank1)
-#define LL_SYSCFG_REMAP_FSMC               SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000        */
-#endif /* FSMC_Bank1 */
-#if defined(FMC_Bank1)
-#define LL_SYSCFG_REMAP_FMC                SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000         */
-#define LL_SYSCFG_REMAP_SDRAM              SYSCFG_MEMRMP_MEM_MODE_2                              /*!< FMC/SDRAM mapped at 0x00000000                      */
-#endif /* FMC_Bank1 */
-#define LL_SYSCFG_REMAP_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000                          */
-
-/**
-  * @}
-  */
-
-#if defined(SYSCFG_PMC_MII_RMII_SEL)
- /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
-* @{
-*/
-#define LL_SYSCFG_PMC_ETHMII               (uint32_t)0x00000000                                /*!< ETH Media MII interface */
-#define LL_SYSCFG_PMC_ETHRMII              (uint32_t)SYSCFG_PMC_MII_RMII_SEL                   /*!< ETH Media RMII interface */
-
-/**
-  * @}
-  */
-#endif /* SYSCFG_PMC_MII_RMII_SEL */
-
-
-
-#if defined(SYSCFG_MEMRMP_UFB_MODE)
-/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
-  * @{
-  */
-#define LL_SYSCFG_BANKMODE_BANK1          (uint32_t)0x00000000       /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)
-                                                                      and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/
-#define LL_SYSCFG_BANKMODE_BANK2          SYSCFG_MEMRMP_UFB_MODE     /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)
-                                                                      and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */
-/**
-  * @}
-  */
-#endif /* SYSCFG_MEMRMP_UFB_MODE */
-/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
-  * @{
-  */ 
-#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
-#define LL_SYSCFG_I2C_FASTMODEPLUS_SCL         SYSCFG_CFGR_FMPI2C1_SCL   /*!< Enable Fast Mode Plus on FMPI2C_SCL pin */
-#define LL_SYSCFG_I2C_FASTMODEPLUS_SDA         SYSCFG_CFGR_FMPI2C1_SDA   /*!< Enable Fast Mode Plus on FMPI2C_SDA pin*/
-#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
-  * @{
-  */
-#define LL_SYSCFG_EXTI_PORTA               (uint32_t)0               /*!< EXTI PORT A                        */
-#define LL_SYSCFG_EXTI_PORTB               (uint32_t)1               /*!< EXTI PORT B                        */
-#define LL_SYSCFG_EXTI_PORTC               (uint32_t)2               /*!< EXTI PORT C                        */
-#define LL_SYSCFG_EXTI_PORTD               (uint32_t)3               /*!< EXTI PORT D                        */
-#define LL_SYSCFG_EXTI_PORTE               (uint32_t)4               /*!< EXTI PORT E                        */
-#if defined(GPIOF)
-#define LL_SYSCFG_EXTI_PORTF               (uint32_t)5               /*!< EXTI PORT F                        */
-#endif /* GPIOF */
-#if defined(GPIOG)
-#define LL_SYSCFG_EXTI_PORTG               (uint32_t)6               /*!< EXTI PORT G                        */
-#endif /* GPIOG */
-#define LL_SYSCFG_EXTI_PORTH               (uint32_t)7               /*!< EXTI PORT H                        */
-#if defined(GPIOI)
-#define LL_SYSCFG_EXTI_PORTI               (uint32_t)8               /*!< EXTI PORT I                        */
-#endif /* GPIOI */
-#if defined(GPIOJ)
-#define LL_SYSCFG_EXTI_PORTJ               (uint32_t)9               /*!< EXTI PORT J                        */
-#endif /* GPIOJ */
-#if defined(GPIOK)
-#define LL_SYSCFG_EXTI_PORTK               (uint32_t)10              /*!< EXTI PORT k                        */
-#endif /* GPIOK */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
-  * @{
-  */
-#define LL_SYSCFG_EXTI_LINE0               (uint32_t)(0x000FU << 16 | 0)  /*!< EXTI_POSITION_0  | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE1               (uint32_t)(0x00F0U << 16 | 0)  /*!< EXTI_POSITION_4  | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE2               (uint32_t)(0x0F00U << 16 | 0)  /*!< EXTI_POSITION_8  | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE3               (uint32_t)(0xF000U << 16 | 0)  /*!< EXTI_POSITION_12 | EXTICR[0] */
-#define LL_SYSCFG_EXTI_LINE4               (uint32_t)(0x000FU << 16 | 1)  /*!< EXTI_POSITION_0  | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE5               (uint32_t)(0x00F0U << 16 | 1)  /*!< EXTI_POSITION_4  | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE6               (uint32_t)(0x0F00U << 16 | 1)  /*!< EXTI_POSITION_8  | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE7               (uint32_t)(0xF000U << 16 | 1)  /*!< EXTI_POSITION_12 | EXTICR[1] */
-#define LL_SYSCFG_EXTI_LINE8               (uint32_t)(0x000FU << 16 | 2)  /*!< EXTI_POSITION_0  | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE9               (uint32_t)(0x00F0U << 16 | 2)  /*!< EXTI_POSITION_4  | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE10              (uint32_t)(0x0F00U << 16 | 2)  /*!< EXTI_POSITION_8  | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE11              (uint32_t)(0xF000U << 16 | 2)  /*!< EXTI_POSITION_12 | EXTICR[2] */
-#define LL_SYSCFG_EXTI_LINE12              (uint32_t)(0x000FU << 16 | 3)  /*!< EXTI_POSITION_0  | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE13              (uint32_t)(0x00F0U << 16 | 3)  /*!< EXTI_POSITION_4  | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE14              (uint32_t)(0x0F00U << 16 | 3)  /*!< EXTI_POSITION_8  | EXTICR[3] */
-#define LL_SYSCFG_EXTI_LINE15              (uint32_t)(0xF000U << 16 | 3)  /*!< EXTI_POSITION_12 | EXTICR[3] */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
-  * @{
-  */
-#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
-#define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_LOCKUP_LOCK   /*!< Enables and locks the LOCKUP output of CortexM4 
-                                                                      with Break Input of TIM1/8                                    */
-#define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVD_LOCK      /*!< Enables and locks the PVD connection with TIM1/8 Break Input 
-                                                                      and also the PVDE and PLS bits of the Power Control Interface  */
-#endif /* SYSCFG_CFGR2_CLL */
-/**
-  * @}
-  */
-
-#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
-/** @defgroup SYSTEM_LL_DFSDM_BitStream_ClockSource SYSCFG MCHDLY BCKKSEL
-  * @{
-  */
-#define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1          (uint32_t)0x00000000
-#define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2           SYSCFG_MCHDLYCR_BSCKSEL
-/**
-  * @}
-  */
-/** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN              SYSCFG MCHDLY MCHDLYEN
-  * @{
-  */  
-#define LL_SYSCFG_DFSDM1_MCHDLYEN                  SYSCFG_MCHDLYCR_MCHDLY1EN
-#define LL_SYSCFG_DFSDM2_MCHDLYEN                  SYSCFG_MCHDLYCR_MCHDLY2EN
-/**
-  * @}
-  */
-/** @defgroup SYSTEM_LL_DFSDM_DataIn0_Source       SYSCFG MCHDLY DFSDMD0SEL
-  * @{
-  */
-#define LL_SYSCFG_DFSDM1_DataIn0                   SYSCFG_MCHDLYCR_DFSDM1D0SEL
-#define LL_SYSCFG_DFSDM2_DataIn0                   SYSCFG_MCHDLYCR_DFSDM2D0SEL
-
-#define LL_SYSCFG_DFSDM1_DataIn0_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | 0x00000000)
-#define LL_SYSCFG_DFSDM1_DataIn0_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D0SEL)
-#define LL_SYSCFG_DFSDM2_DataIn0_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | 0x00000000)
-#define LL_SYSCFG_DFSDM2_DataIn0_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D0SEL)
-/**
-  * @}
-  */
-/** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source       SYSCFG MCHDLY DFSDMD2SEL
-  * @{
-  */   
-#define LL_SYSCFG_DFSDM1_DataIn2                   SYSCFG_MCHDLYCR_DFSDM1D2SEL
-#define LL_SYSCFG_DFSDM2_DataIn2                   SYSCFG_MCHDLYCR_DFSDM2D2SEL
-
-#define LL_SYSCFG_DFSDM1_DataIn2_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | 0x00000000)
-#define LL_SYSCFG_DFSDM1_DataIn2_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D2SEL)
-#define LL_SYSCFG_DFSDM2_DataIn2_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | 0x00000000)
-#define LL_SYSCFG_DFSDM2_DataIn2_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D2SEL)
-/**
-  * @}
-  */
-/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution  SYSCFG MCHDLY DFSDM1CK02SEL
-  * @{
-  */ 
-#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0           (uint32_t)0x00000000
-#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2           SYSCFG_MCHDLYCR_DFSDM1CK02SEL
-/**
-  * @}
-  */
-/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution  SYSCFG MCHDLY DFSDM1CK13SEL
-  * @{
-  */ 
-#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1           (uint32_t)0x00000000
-#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3           SYSCFG_MCHDLYCR_DFSDM1CK13SEL
-/**
-  * @}
-  */
-/** @defgroup SYSTEM_LL_DFSDM1_CLKIN_SourceSelection SYSCFG MCHDLY DFSDMCFG
-  * @{
-  */
-#define LL_SYSCFG_DFSDM1_CKIN_PAD                 (uint32_t)0x00000000
-#define LL_SYSCFG_DFSDM1_CKIN_DM                  SYSCFG_MCHDLYCR_DFSDM1CFG
-/**
-  * @}
-  */
-/** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL
-  * @{
-  */ 
-#define LL_SYSCFG_DFSDM1_CKOUT                    (uint32_t)0x00000000
-#define LL_SYSCFG_DFSDM1_CKOUT_M27                SYSCFG_MCHDLYCR_DFSDM1CKOSEL
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL
-  * @{
-  */ 
-#define LL_SYSCFG_DFSDM2_DataIn4_PAD              (uint32_t)0x00000000
-#define LL_SYSCFG_DFSDM2_DataIn4_DM               SYSCFG_MCHDLYCR_DFSDM2D4SEL
-/**
-  * @}
-  */
-/** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL
-  * @{
-  */ 
-#define LL_SYSCFG_DFSDM2_DataIn6_PAD              (uint32_t)0x00000000
-#define LL_SYSCFG_DFSDM2_DataIn6_DM               SYSCFG_MCHDLYCR_DFSDM2D6SEL
-/**
-  * @}
-  */
-/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK04SEL
-  * @{
-  */ 
-#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0           (uint32_t)0x00000000
-#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4           SYSCFG_MCHDLYCR_DFSDM2CK04SEL
-/**
-  * @}
-  */
-/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK15SEL
-  * @{
-  */ 
-#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1           (uint32_t)0x00000000
-#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5           SYSCFG_MCHDLYCR_DFSDM2CK15SEL
-/**
-  * @}
-  */
-/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK26SEL
-  * @{
-  */ 
-#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2           (uint32_t)0x00000000
-#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6           SYSCFG_MCHDLYCR_DFSDM2CK26SEL
-/**
-  * @}
-  */
-/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK37SEL
-  * @{
-  */ 
-#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3           (uint32_t)0x00000000
-#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7           SYSCFG_MCHDLYCR_DFSDM2CK37SEL
-/**
-  * @}
-  */
-/** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG
-  * @{
-  */ 
-#define LL_SYSCFG_DFSDM2_CKIN_PAD                 (uint32_t)0x00000000
-#define LL_SYSCFG_DFSDM2_CKIN_DM                  SYSCFG_MCHDLYCR_DFSDM2CFG
-/**
-  * @}
-  */
-/** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL
-  * @{
-  */ 
-#define LL_SYSCFG_DFSDM2_CKOUT                    (uint32_t)0x00000000
-#define LL_SYSCFG_DFSDM2_CKOUT_M27                SYSCFG_MCHDLYCR_DFSDM2CKOSEL
-/**
-  * @}
-  */ 
-#endif /* SYSCFG_MCHDLYCR_BSCKSEL */  
-
-/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
-  * @{
-  */
-#define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
-#define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
-#define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
-  * @{
-  */
-#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1_FZ_DBG_TIM2_STOP          /*!< TIM2 counter stopped when core is halted */
-#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
-#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1_FZ_DBG_TIM3_STOP          /*!< TIM3 counter stopped when core is halted */
-#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
-#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1_FZ_DBG_TIM4_STOP          /*!< TIM4 counter stopped when core is halted */
-#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
-#define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1_FZ_DBG_TIM5_STOP          /*!< TIM5 counter stopped when core is halted */
-#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1_FZ_DBG_TIM6_STOP          /*!< TIM6 counter stopped when core is halted */
-#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
-#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1_FZ_DBG_TIM7_STOP          /*!< TIM7 counter stopped when core is halted */
-#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
-#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_APB1_FZ_DBG_TIM12_STOP         /*!< TIM12 counter stopped when core is halted */
-#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
-#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_APB1_FZ_DBG_TIM13_STOP         /*!< TIM13 counter stopped when core is halted */
-#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
-#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
-#define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_APB1_FZ_DBG_TIM14_STOP         /*!< TIM14 counter stopped when core is halted */
-#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
-#if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP)
-#define LL_DBGMCU_APB1_GRP1_LPTIM_STOP     DBGMCU_APB1_FZ_DBG_LPTIM_STOP         /*!< LPTIM counter stopped when core is halted */
-#endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */
-#define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1_FZ_DBG_RTC_STOP           /*!< RTC counter stopped when core is halted */
-#define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1_FZ_DBG_WWDG_STOP          /*!< Debug Window Watchdog stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1_FZ_DBG_IWDG_STOP          /*!< Debug Independent Watchdog stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
-#define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
-#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
-#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
-#define LL_DBGMCU_APB1_GRP1_I2C4_STOP      DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when Core is halted */
-#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
-#if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP)
-#define LL_DBGMCU_APB1_GRP1_CAN1_STOP      DBGMCU_APB1_FZ_DBG_CAN1_STOP          /*!< CAN1 debug stopped when Core is halted  */
-#endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */
-#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
-#define LL_DBGMCU_APB1_GRP1_CAN2_STOP      DBGMCU_APB1_FZ_DBG_CAN2_STOP          /*!< CAN2 debug stopped when Core is halted  */
-#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
-#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
-#define LL_DBGMCU_APB1_GRP1_CAN3_STOP      DBGMCU_APB1_FZ_DBG_CAN3_STOP          /*!< CAN3 debug stopped when Core is halted  */
-#endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
-  * @{
-  */
-#define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2_FZ_DBG_TIM1_STOP   /*!< TIM1 counter stopped when core is halted */
-#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2_FZ_DBG_TIM8_STOP   /*!< TIM8 counter stopped when core is halted */
-#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
-#define LL_DBGMCU_APB2_GRP1_TIM9_STOP      DBGMCU_APB2_FZ_DBG_TIM9_STOP   /*!< TIM9 counter stopped when core is halted */
-#if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP)
-#define LL_DBGMCU_APB2_GRP1_TIM10_STOP     DBGMCU_APB2_FZ_DBG_TIM10_STOP   /*!< TIM10 counter stopped when core is halted */
-#endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */
-#define LL_DBGMCU_APB2_GRP1_TIM11_STOP     DBGMCU_APB2_FZ_DBG_TIM11_STOP   /*!< TIM11 counter stopped when core is halted */
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
-  * @{
-  */
-#define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
-#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
-#define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
-#define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
-#define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
-#define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */
-#define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */
-#define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */
-#define LL_FLASH_LATENCY_8                 FLASH_ACR_LATENCY_8WS   /*!< FLASH eight wait states */
-#define LL_FLASH_LATENCY_9                 FLASH_ACR_LATENCY_9WS   /*!< FLASH nine wait states */
-#define LL_FLASH_LATENCY_10                FLASH_ACR_LATENCY_10WS   /*!< FLASH ten wait states */
-#define LL_FLASH_LATENCY_11                FLASH_ACR_LATENCY_11WS   /*!< FLASH eleven wait states */
-#define LL_FLASH_LATENCY_12                FLASH_ACR_LATENCY_12WS   /*!< FLASH twelve wait states */
-#define LL_FLASH_LATENCY_13                FLASH_ACR_LATENCY_13WS   /*!< FLASH thirteen wait states */
-#define LL_FLASH_LATENCY_14                FLASH_ACR_LATENCY_14WS   /*!< FLASH fourteen wait states */
-#define LL_FLASH_LATENCY_15                FLASH_ACR_LATENCY_15WS   /*!< FLASH fifteen wait states */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
-  * @{
-  */
-
-/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
-  * @{
-  */
-/**
-  * @brief  Set memory mapping at address 0x00000000
-  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_SetRemapMemory
-  * @param  Memory This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_REMAP_FLASH
-  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
-  *         @arg @ref LL_SYSCFG_REMAP_SRAM
-  *         @arg @ref LL_SYSCFG_REMAP_FSMC (*)
-  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
-{
-  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
-}
-
-/**
-  * @brief  Get memory mapping at address 0x00000000
-  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_GetRemapMemory
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_REMAP_FLASH
-  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
-  *         @arg @ref LL_SYSCFG_REMAP_SRAM
-  *         @arg @ref LL_SYSCFG_REMAP_FSMC (*)
-  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
-}
-
-#if defined(SYSCFG_MEMRMP_SWP_FMC)
-/**
-  * @brief  Enables the FMC Memory Mapping Swapping
-  * @rmtoll SYSCFG_MEMRMP SWP_FMC      LL_SYSCFG_EnableFMCMemorySwapping
-  * @note   SDRAM is accessible at 0x60000000 and NOR/RAM 
-  *         is accessible at 0xC0000000   
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
-{
-  SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);
-}
-
-/**
-  * @brief  Disables the FMC Memory Mapping Swapping
-  * @rmtoll SYSCFG_MEMRMP SWP_FMC      LL_SYSCFG_DisableFMCMemorySwapping
-  * @note   SDRAM is accessible at 0xC0000000 (default mapping)  
-  *         and NOR/RAM is accessible at 0x60000000 (default mapping)
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)
-{
-  CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);
-}
-
-#endif /* SYSCFG_MEMRMP_SWP_FMC */
-/**
-  * @brief  Enables the Compensation cell Power Down
-  * @rmtoll SYSCFG_CMPCR CMP_PD      LL_SYSCFG_EnableCompensationCell
-  * @note   The I/O compensation cell can be used only when the device supply
-  *         voltage ranges from 2.4 to 3.6 V
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
-{
-  SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
-}
-
-/**
-  * @brief  Disables the Compensation cell Power Down
-  * @rmtoll SYSCFG_CMPCR CMP_PD      LL_SYSCFG_DisableCompensationCell
-  * @note   The I/O compensation cell can be used only when the device supply
-  *         voltage ranges from 2.4 to 3.6 V
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
-{
-  CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
-}
-
-/**
-  * @brief  Get Compensation Cell ready Flag
-  * @rmtoll SYSCFG_CMPCR READY  LL_SYSCFG_IsActiveFlag_CMPCR
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
-{
-  return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
-}
-
-#if defined(SYSCFG_PMC_MII_RMII_SEL)
-/**
-  * @brief  Select Ethernet PHY interface 
-  * @rmtoll SYSCFG_PMC MII_RMII_SEL       LL_SYSCFG_SetPHYInterface
-  * @param  Interface This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_PMC_ETHMII
-  *         @arg @ref LL_SYSCFG_PMC_ETHRMII
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
-{
-  MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
-}
-
-/**
-  * @brief  Get Ethernet PHY interface 
-  * @rmtoll SYSCFG_PMC MII_RMII_SEL       LL_SYSCFG_GetPHYInterface
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_PMC_ETHMII
-  *         @arg @ref LL_SYSCFG_PMC_ETHRMII
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
-}
-#endif /* SYSCFG_PMC_MII_RMII_SEL */
- 
-
-
-#if defined(SYSCFG_MEMRMP_UFB_MODE)
-/**
-  * @brief  Select Flash bank mode (Bank flashed at 0x08000000)
-  * @rmtoll SYSCFG_MEMRMP UFB_MODE       LL_SYSCFG_SetFlashBankMode
-  * @param  Bank This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
-  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
-{ 
-  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank);
-}
-
-/**
-  * @brief  Get Flash bank mode (Bank flashed at 0x08000000)
-  * @rmtoll SYSCFG_MEMRMP UFB_MODE       LL_SYSCFG_GetFlashBankMode
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
-  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE));
-}
-#endif /* SYSCFG_MEMRMP_UFB_MODE */
-
-#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
-/**
-  * @brief  Enable the I2C fast mode plus driving capability.
-  * @rmtoll SYSCFG_CFGR FMPI2C1_SCL   LL_SYSCFG_EnableFastModePlus\n
-  *         SYSCFG_CFGR FMPI2C1_SDA   LL_SYSCFG_EnableFastModePlus
-  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
-{
-  SET_BIT(SYSCFG->CFGR, ConfigFastModePlus);
-}
-
-/**
-  * @brief  Disable the I2C fast mode plus driving capability.
-  * @rmtoll SYSCFG_CFGR FMPI2C1_SCL  LL_SYSCFG_DisableFastModePlus\n
-  *         SYSCFG_CFGR FMPI2C1_SDA  LL_SYSCFG_DisableFastModePlus\n
-  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
-  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
-  *         (*) value not defined in all devices
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
-{
-  CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus);
-}
-#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
-
-/**
-  * @brief  Configure source input for the EXTI external interrupt.
-  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
-  * @param  Port This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_EXTI_PORTA
-  *         @arg @ref LL_SYSCFG_EXTI_PORTB
-  *         @arg @ref LL_SYSCFG_EXTI_PORTC
-  *         @arg @ref LL_SYSCFG_EXTI_PORTD
-  *         @arg @ref LL_SYSCFG_EXTI_PORTE
-  *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
-  *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
-  *         @arg @ref LL_SYSCFG_EXTI_PORTH
-  *
-  *         (*) value not defined in all devices
-  * @param  Line This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_EXTI_LINE0
-  *         @arg @ref LL_SYSCFG_EXTI_LINE1
-  *         @arg @ref LL_SYSCFG_EXTI_LINE2
-  *         @arg @ref LL_SYSCFG_EXTI_LINE3
-  *         @arg @ref LL_SYSCFG_EXTI_LINE4
-  *         @arg @ref LL_SYSCFG_EXTI_LINE5
-  *         @arg @ref LL_SYSCFG_EXTI_LINE6
-  *         @arg @ref LL_SYSCFG_EXTI_LINE7
-  *         @arg @ref LL_SYSCFG_EXTI_LINE8
-  *         @arg @ref LL_SYSCFG_EXTI_LINE9
-  *         @arg @ref LL_SYSCFG_EXTI_LINE10
-  *         @arg @ref LL_SYSCFG_EXTI_LINE11
-  *         @arg @ref LL_SYSCFG_EXTI_LINE12
-  *         @arg @ref LL_SYSCFG_EXTI_LINE13
-  *         @arg @ref LL_SYSCFG_EXTI_LINE14
-  *         @arg @ref LL_SYSCFG_EXTI_LINE15
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
-{
-  MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
-}
-
-/**
-  * @brief  Get the configured defined for specific EXTI Line
-  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
-  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
-  * @param  Line This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_EXTI_LINE0
-  *         @arg @ref LL_SYSCFG_EXTI_LINE1
-  *         @arg @ref LL_SYSCFG_EXTI_LINE2
-  *         @arg @ref LL_SYSCFG_EXTI_LINE3
-  *         @arg @ref LL_SYSCFG_EXTI_LINE4
-  *         @arg @ref LL_SYSCFG_EXTI_LINE5
-  *         @arg @ref LL_SYSCFG_EXTI_LINE6
-  *         @arg @ref LL_SYSCFG_EXTI_LINE7
-  *         @arg @ref LL_SYSCFG_EXTI_LINE8
-  *         @arg @ref LL_SYSCFG_EXTI_LINE9
-  *         @arg @ref LL_SYSCFG_EXTI_LINE10
-  *         @arg @ref LL_SYSCFG_EXTI_LINE11
-  *         @arg @ref LL_SYSCFG_EXTI_LINE12
-  *         @arg @ref LL_SYSCFG_EXTI_LINE13
-  *         @arg @ref LL_SYSCFG_EXTI_LINE14
-  *         @arg @ref LL_SYSCFG_EXTI_LINE15
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_EXTI_PORTA
-  *         @arg @ref LL_SYSCFG_EXTI_PORTB
-  *         @arg @ref LL_SYSCFG_EXTI_PORTC
-  *         @arg @ref LL_SYSCFG_EXTI_PORTD
-  *         @arg @ref LL_SYSCFG_EXTI_PORTE
-  *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
-  *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
-  *         @arg @ref LL_SYSCFG_EXTI_PORTH
-  *         (*) value not defined in all devices
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
-}
-
-#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
-/**
-  * @brief  Set connections to TIM1/8 break inputs
-  * @rmtoll SYSCFG_CFGR2 LockUp Lock           LL_SYSCFG_SetTIMBreakInputs \n
-  *         SYSCFG_CFGR2 PVD Lock              LL_SYSCFG_SetTIMBreakInputs
-  * @param  Break This parameter can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
-  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
-{
-  MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break);
-}
-
-/**
-  * @brief  Get connections to TIM1/8 Break inputs
-  * @rmtoll SYSCFG_CFGR2 LockUp Lock           LL_SYSCFG_SetTIMBreakInputs \n
-  *         SYSCFG_CFGR2 PVD Lock              LL_SYSCFG_SetTIMBreakInputs
-  * @retval Returned value can be can be a combination of the following values:
-  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
-  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
-{   
-  return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK));
-}
-#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
-#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
-/**
-  * @brief  Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
-  * @rmtoll SYSCFG_MCHDLYCR BSCKSEL        LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection
-  * @param  ClockSource This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
-  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource);
-}
-/**
-  * @brief  Get the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
-  * @rmtoll SYSCFG_MCHDLYCR BSCKSEL       LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
-  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL));
-}
-/**
-  * @brief  Enables the DFSDM1 or DFSDM2 Delay clock
-  * @rmtoll SYSCFG_MCHDLYCR MCHDLYEN      LL_SYSCFG_DFSDM_EnableDelayClock
-  * @param MCHDLY This parameter can be one of the following values
-  *         @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
-  *         @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY)
-{
-  SET_BIT(SYSCFG->MCHDLYCR, MCHDLY);
-}
-
-/**
-  * @brief  Disables the DFSDM1 or the DFSDM2 Delay clock
-  * @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN      LL_SYSCFG_DFSDM1_DisableDelayClock
-  * @param MCHDLY This parameter can be one of the following values
-  *         @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
-  *         @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY)
-{
-  CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY);
-}
-
-/**
-  * @brief  Select the source for DFSDM1 or DFSDM2 DatIn0 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL        LL_SYSCFG_DFSDM_SetDataIn0Source
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
-}
-/**
-  * @brief  Get the source for DFSDM1 or DFSDM2 DatIn0.
-  * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL       LL_SYSCFG_DFSDM_GetDataIn0Source
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
-}
-/**
-  * @brief  Select the source for DFSDM1 or DFSDM2 DatIn2 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL        LL_SYSCFG_DFSDM_SetDataIn2Source
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
-}
-/**
-  * @brief  Get the source for DFSDM1 or DFSDM2 DatIn2.
-  * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL       LL_SYSCFG_DFSDM_GetDataIn2Source
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
-}
-
-/**
-  * @brief  Select the distribution of the bitsream lock gated by TIM4 OC2 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL        LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
-  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source);
-}
-/**
-  * @brief  Get the distribution of the bitsream lock gated by TIM4 OC2 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL       LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
-  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL));
-}
-
-/**
-  * @brief  Select the distribution of the bitsream lock gated by TIM4 OC1 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL        LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
-  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source);
-}
-/**
-  * @brief  Get the distribution of the bitsream lock gated by TIM4 OC1 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL       LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
-  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL));
-}
-
-/**
-  * @brief  Select the DFSDM1 Clock In 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG        LL_SYSCFG_DFSDM1_SetClockInSourceSelection
-  * @param  ClockSource This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource);
-}
-/**
-  * @brief  GET the DFSDM1 Clock In
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG       LL_SYSCFG_DFSDM1_GetClockInSourceSelection
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG));
-}
-
-/**
-  * @brief  Select the DFSDM1 Clock Out 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL        LL_SYSCFG_DFSDM1_SetClockOutSourceSelection
-  * @param  ClockSource This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT
-  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource);
-}
-/**
-  * @brief  GET the DFSDM1 Clock Out
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL       LL_SYSCFG_DFSDM1_GetClockOutSourceSelection
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT
-  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL));
-}
-
-/**
-  * @brief  Enables the DFSDM2 Delay clock
-  * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN      LL_SYSCFG_DFSDM2_EnableDelayClock
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void)
-{
-  SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
-}
-
-/**
-  * @brief  Disables the DFSDM2 Delay clock
-  * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN      LL_SYSCFG_DFSDM2_DisableDelayClock
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void)
-{
-  CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
-}
-/**
-  * @brief  Select the source for DFSDM2 DatIn0 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL        LL_SYSCFG_DFSDM2_SetDataIn0Source
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source);
-}
-/**
-  * @brief  Get the source for DFSDM2 DatIn0.
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL       LL_SYSCFG_DFSDM2_GetDataIn0Source
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL));
-}
-
-/**
-  * @brief  Select the source for DFSDM2 DatIn2 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL        LL_SYSCFG_DFSDM2_SetDataIn2Source
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source);
-}
-/**
-  * @brief  Get the source for DFSDM2 DatIn2.
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL       LL_SYSCFG_DFSDM2_GetDataIn2Source
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL));
-}
-
-/**
-  * @brief  Select the source for DFSDM2 DatIn4 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL        LL_SYSCFG_DFSDM2_SetDataIn4Source
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source);
-}
-/**
-  * @brief  Get the source for DFSDM2 DatIn4.
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL       LL_SYSCFG_DFSDM2_GetDataIn4Source
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL));
-}
-
-/**
-  * @brief  Select the source for DFSDM2 DatIn6 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL        LL_SYSCFG_DFSDM2_SetDataIn6Source
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source);
-}
-/**
-  * @brief  Get the source for DFSDM2 DatIn6.
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL       LL_SYSCFG_DFSDM2_GetDataIn6Source
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL));
-}
-
-/**
-  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC4 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL        LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
-  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source);
-}
-/**
-  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC4 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
-  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL));
-}
-
-/**
-  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC3 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL        LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
-  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source);
-}
-/**
-  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC4 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
-  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL));
-}
-
-/**
-  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC2 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL        LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
-  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source);
-}
-/**
-  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC2 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
-  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL));
-}
-
-/**
-  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC1 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL        LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution
-  * @param  Source This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
-  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source);
-}
-/**
-  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC1 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL       LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
-  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL));
-}
-
-/**
-  * @brief  Select the DFSDM2 Clock In 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG        LL_SYSCFG_DFSDM2_SetClockInSourceSelection
-  * @param  ClockSource This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource);
-}
-/**
-  * @brief  GET the DFSDM2 Clock In
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG       LL_SYSCFG_DFSDM2_GetClockInSourceSelection
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
-  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG));
-}
-
-/**
-  * @brief  Select the DFSDM2 Clock Out 
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL        LL_SYSCFG_DFSDM2_SetClockOutSourceSelection
-  * @param  ClockSource This parameter can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT
-  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
-  * @retval None
-  */
-__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource)
-{
-  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource);
-}
-/**
-  * @brief  GET the DFSDM2 Clock Out
-  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL       LL_SYSCFG_DFSDM2_GetClockOutSourceSelection
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT
-  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
-  * @retval None
-  */
-__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void)
-{
-  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL));
-}
-
-#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
-/**
-  * @}
-  */
-
-
-/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
-  * @{
-  */
-
-/**
-  * @brief  Return the device identifier
-  * @note For STM32F405/407xx and STM32F415/417xx devices, the device ID is 0x413
-  * @note For STM32F42xxx and STM32F43xxx devices, the device ID is 0x419
-  * @note For STM32F401xx devices, the device ID is 0x423
-  * @note For STM32F401xx devices, the device ID is 0x433
-  * @note For STM32F411xx devices, the device ID is 0x431
-  * @note For STM32F410xx devices, the device ID is 0x458
-  * @note For STM32F412xx devices, the device ID is 0x441
-  * @note For STM32F413xx and STM32423xx devices, the device ID is 0x463
-  * @note For STM32F446xx devices, the device ID is 0x421
-  * @note For STM32F469xx and STM32F479xx devices, the device ID is 0x434
-  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
-  * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
-  */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
-{
-  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
-}
-
-/**
-  * @brief  Return the device revision identifier
-  * @note This field indicates the revision of the device.
-          For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001, rev1 -> 0x1003, rev2 ->0x1007, revY -> 0x100F for STM32F405/407xx and STM32F415/417xx devices
-          For example, it is read as RevA -> 0x1000, Cat 2 revY -> 0x1003, rev1 -> 0x1007, rev3 ->0x2001 for STM32F42xxx and STM32F43xxx devices
-          For example, it is read as RevZ -> 0x1000, Cat 2 revA -> 0x1001 for STM32F401xB/C devices
-          For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 for STM32F401xD/E devices
-          For example, it is read as RevA -> 0x1000 for STM32F411xx,STM32F413/423xx,STM32F469/423xx, STM32F446xx and STM32F410xx devices
-          For example, it is read as RevZ -> 0x1001, Cat 2 revB -> 0x2000, revC -> 0x3000 for STM32F412xx devices
-  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
-  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
-  */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
-{
-  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
-}
-
-/**
-  * @brief  Enable the Debug Module during SLEEP mode
-  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Disable the Debug Module during SLEEP mode
-  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STOP mode
-  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Disable the Debug Module during STOP mode
-  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STANDBY mode
-  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Disable the Debug Module during STANDBY mode
-  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Set Trace pin assignment control
-  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
-  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
-  * @param  PinAssignment This parameter can be one of the following values:
-  *         @arg @ref LL_DBGMCU_TRACE_NONE
-  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
-  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
-  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
-  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
-{
-  MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
-}
-
-/**
-  * @brief  Get Trace pin assignment control
-  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
-  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_DBGMCU_TRACE_NONE
-  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
-  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
-  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
-  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
-  */
-__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
-{
-  return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
-}
-
-/**
-  * @brief  Freeze APB1 peripherals (group1 peripherals)
-  * @rmtoll DBGMCU_APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_LPTIM_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_I2C4_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_CAN3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP 
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
-  *         
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
-{
-  SET_BIT(DBGMCU->APB1FZ, Periphs);
-}
-
-/**
-  * @brief  Unfreeze APB1 peripherals (group1 peripherals)
-  * @rmtoll DBGMCU_APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_LPTIM_STOP         LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_I2C4_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB1_FZ      DBG_CAN3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP 
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
-  *         
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
-  CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
-}
-
-/**
-  * @brief  Freeze APB2 peripherals
-  * @rmtoll DBGMCU_APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         DBGMCU_APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         DBGMCU_APB2_FZ      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         DBGMCU_APB2_FZ      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
-  *         DBGMCU_APB2_FZ      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
-{
-  SET_BIT(DBGMCU->APB2FZ, Periphs);
-}
-
-/**
-  * @brief  Unfreeze APB2 peripherals
-  * @rmtoll DBGMCU_APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB2_FZ      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB2_FZ      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
-  *         DBGMCU_APB2_FZ      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph
-  * @param  Periphs This parameter can be a combination of the following values:
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
-  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
-  *
-  *         (*) value not defined in all devices.
-  * @retval None
-  */
-__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
-{
-  CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
-}
-/**
-  * @}
-  */
-
-/** @defgroup SYSTEM_LL_EF_FLASH FLASH
-  * @{
-  */
-
-/**
-  * @brief  Set FLASH Latency
-  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
-  * @param  Latency This parameter can be one of the following values:
-  *         @arg @ref LL_FLASH_LATENCY_0
-  *         @arg @ref LL_FLASH_LATENCY_1
-  *         @arg @ref LL_FLASH_LATENCY_2
-  *         @arg @ref LL_FLASH_LATENCY_3
-  *         @arg @ref LL_FLASH_LATENCY_4
-  *         @arg @ref LL_FLASH_LATENCY_5
-  *         @arg @ref LL_FLASH_LATENCY_6
-  *         @arg @ref LL_FLASH_LATENCY_7
-  *         @arg @ref LL_FLASH_LATENCY_8
-  *         @arg @ref LL_FLASH_LATENCY_9
-  *         @arg @ref LL_FLASH_LATENCY_10
-  *         @arg @ref LL_FLASH_LATENCY_11
-  *         @arg @ref LL_FLASH_LATENCY_12
-  *         @arg @ref LL_FLASH_LATENCY_13
-  *         @arg @ref LL_FLASH_LATENCY_14
-  *         @arg @ref LL_FLASH_LATENCY_15
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
-{
-  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
-}
-
-/**
-  * @brief  Get FLASH Latency
-  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_FLASH_LATENCY_0
-  *         @arg @ref LL_FLASH_LATENCY_1
-  *         @arg @ref LL_FLASH_LATENCY_2
-  *         @arg @ref LL_FLASH_LATENCY_3
-  *         @arg @ref LL_FLASH_LATENCY_4
-  *         @arg @ref LL_FLASH_LATENCY_5
-  *         @arg @ref LL_FLASH_LATENCY_6
-  *         @arg @ref LL_FLASH_LATENCY_7
-  *         @arg @ref LL_FLASH_LATENCY_8
-  *         @arg @ref LL_FLASH_LATENCY_9
-  *         @arg @ref LL_FLASH_LATENCY_10
-  *         @arg @ref LL_FLASH_LATENCY_11
-  *         @arg @ref LL_FLASH_LATENCY_12
-  *         @arg @ref LL_FLASH_LATENCY_13
-  *         @arg @ref LL_FLASH_LATENCY_14
-  *         @arg @ref LL_FLASH_LATENCY_15
-  */
-__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
-{
-  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
-}
-
-/**
-  * @brief  Enable Prefetch
-  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
-{
-  SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
-}
-
-/**
-  * @brief  Disable Prefetch
-  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
-{
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
-}
-
-/**
-  * @brief  Check if Prefetch buffer is enabled
-  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
-{
-  return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
-}
-
-/**
-  * @brief  Enable Instruction cache
-  * @rmtoll FLASH_ACR    ICEN          LL_FLASH_EnableInstCache
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
-{
-  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
-}
-
-/**
-  * @brief  Disable Instruction cache
-  * @rmtoll FLASH_ACR    ICEN          LL_FLASH_DisableInstCache
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
-{
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
-}
-
-/**
-  * @brief  Enable Data cache
-  * @rmtoll FLASH_ACR    DCEN          LL_FLASH_EnableDataCache
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
-{
-  SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
-}
-
-/**
-  * @brief  Disable Data cache
-  * @rmtoll FLASH_ACR    DCEN          LL_FLASH_DisableDataCache
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
-{
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
-}
-
-/**
-  * @brief  Enable Instruction cache reset
-  * @note  bit can be written only when the instruction cache is disabled
-  * @rmtoll FLASH_ACR    ICRST         LL_FLASH_EnableInstCacheReset
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
-{
-  SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
-}
-
-/**
-  * @brief  Disable Instruction cache reset
-  * @rmtoll FLASH_ACR    ICRST         LL_FLASH_DisableInstCacheReset
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
-{
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
-}
-
-/**
-  * @brief  Enable Data cache reset
-  * @note bit can be written only when the data cache is disabled
-  * @rmtoll FLASH_ACR    DCRST         LL_FLASH_EnableDataCacheReset
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
-{
-  SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
-}
-
-/**
-  * @brief  Disable Data cache reset
-  * @rmtoll FLASH_ACR    DCRST         LL_FLASH_DisableDataCacheReset
-  * @retval None
-  */
-__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
-{
-  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
-}
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_LL_SYSTEM_H */
-
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_system.h
+  * @author  MCD Application Team
+  * @brief   Header file of SYSTEM LL module.
+  *
+  ******************************************************************************
+  * @attention
+  *
+  *Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL SYSTEM driver contains a set of generic APIs that can be
+    used by user:
+      (+) Some of the FLASH features need to be handled in the SYSTEM file.
+      (+) Access to DBGCMU registers
+      (+) Access to SYSCFG registers
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_SYSTEM_H
+#define __STM32F4xx_LL_SYSTEM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
+
+/** @defgroup SYSTEM_LL SYSTEM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
+* @{
+*/
+#define LL_SYSCFG_REMAP_FLASH              (uint32_t)0x00000000                                  /*!< Main Flash memory mapped at 0x00000000              */
+#define LL_SYSCFG_REMAP_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0                              /*!< System Flash memory mapped at 0x00000000            */
+#if defined(FSMC_Bank1)
+#define LL_SYSCFG_REMAP_FSMC               SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000        */
+#endif /* FSMC_Bank1 */
+#if defined(FMC_Bank1)
+#define LL_SYSCFG_REMAP_FMC                SYSCFG_MEMRMP_MEM_MODE_1                              /*!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000         */
+#define LL_SYSCFG_REMAP_SDRAM              SYSCFG_MEMRMP_MEM_MODE_2                              /*!< FMC/SDRAM mapped at 0x00000000                      */
+#endif /* FMC_Bank1 */
+#define LL_SYSCFG_REMAP_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000                          */
+
+/**
+  * @}
+  */
+
+#if defined(SYSCFG_PMC_MII_RMII_SEL)
+ /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
+* @{
+*/
+#define LL_SYSCFG_PMC_ETHMII               (uint32_t)0x00000000                                /*!< ETH Media MII interface */
+#define LL_SYSCFG_PMC_ETHRMII              (uint32_t)SYSCFG_PMC_MII_RMII_SEL                   /*!< ETH Media RMII interface */
+
+/**
+  * @}
+  */
+#endif /* SYSCFG_PMC_MII_RMII_SEL */
+
+
+
+#if defined(SYSCFG_MEMRMP_UFB_MODE)
+/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
+  * @{
+  */
+#define LL_SYSCFG_BANKMODE_BANK1          (uint32_t)0x00000000       /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)
+                                                                      and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/
+#define LL_SYSCFG_BANKMODE_BANK2          SYSCFG_MEMRMP_UFB_MODE     /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)
+                                                                      and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */
+/**
+  * @}
+  */
+#endif /* SYSCFG_MEMRMP_UFB_MODE */
+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
+  * @{
+  */ 
+#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
+#define LL_SYSCFG_I2C_FASTMODEPLUS_SCL         SYSCFG_CFGR_FMPI2C1_SCL   /*!< Enable Fast Mode Plus on FMPI2C_SCL pin */
+#define LL_SYSCFG_I2C_FASTMODEPLUS_SDA         SYSCFG_CFGR_FMPI2C1_SDA   /*!< Enable Fast Mode Plus on FMPI2C_SDA pin*/
+#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
+  * @{
+  */
+#define LL_SYSCFG_EXTI_PORTA               (uint32_t)0               /*!< EXTI PORT A                        */
+#define LL_SYSCFG_EXTI_PORTB               (uint32_t)1               /*!< EXTI PORT B                        */
+#define LL_SYSCFG_EXTI_PORTC               (uint32_t)2               /*!< EXTI PORT C                        */
+#define LL_SYSCFG_EXTI_PORTD               (uint32_t)3               /*!< EXTI PORT D                        */
+#define LL_SYSCFG_EXTI_PORTE               (uint32_t)4               /*!< EXTI PORT E                        */
+#if defined(GPIOF)
+#define LL_SYSCFG_EXTI_PORTF               (uint32_t)5               /*!< EXTI PORT F                        */
+#endif /* GPIOF */
+#if defined(GPIOG)
+#define LL_SYSCFG_EXTI_PORTG               (uint32_t)6               /*!< EXTI PORT G                        */
+#endif /* GPIOG */
+#define LL_SYSCFG_EXTI_PORTH               (uint32_t)7               /*!< EXTI PORT H                        */
+#if defined(GPIOI)
+#define LL_SYSCFG_EXTI_PORTI               (uint32_t)8               /*!< EXTI PORT I                        */
+#endif /* GPIOI */
+#if defined(GPIOJ)
+#define LL_SYSCFG_EXTI_PORTJ               (uint32_t)9               /*!< EXTI PORT J                        */
+#endif /* GPIOJ */
+#if defined(GPIOK)
+#define LL_SYSCFG_EXTI_PORTK               (uint32_t)10              /*!< EXTI PORT k                        */
+#endif /* GPIOK */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
+  * @{
+  */
+#define LL_SYSCFG_EXTI_LINE0               (uint32_t)(0x000FU << 16 | 0)  /*!< EXTI_POSITION_0  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE1               (uint32_t)(0x00F0U << 16 | 0)  /*!< EXTI_POSITION_4  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE2               (uint32_t)(0x0F00U << 16 | 0)  /*!< EXTI_POSITION_8  | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE3               (uint32_t)(0xF000U << 16 | 0)  /*!< EXTI_POSITION_12 | EXTICR[0] */
+#define LL_SYSCFG_EXTI_LINE4               (uint32_t)(0x000FU << 16 | 1)  /*!< EXTI_POSITION_0  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE5               (uint32_t)(0x00F0U << 16 | 1)  /*!< EXTI_POSITION_4  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE6               (uint32_t)(0x0F00U << 16 | 1)  /*!< EXTI_POSITION_8  | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE7               (uint32_t)(0xF000U << 16 | 1)  /*!< EXTI_POSITION_12 | EXTICR[1] */
+#define LL_SYSCFG_EXTI_LINE8               (uint32_t)(0x000FU << 16 | 2)  /*!< EXTI_POSITION_0  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE9               (uint32_t)(0x00F0U << 16 | 2)  /*!< EXTI_POSITION_4  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE10              (uint32_t)(0x0F00U << 16 | 2)  /*!< EXTI_POSITION_8  | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE11              (uint32_t)(0xF000U << 16 | 2)  /*!< EXTI_POSITION_12 | EXTICR[2] */
+#define LL_SYSCFG_EXTI_LINE12              (uint32_t)(0x000FU << 16 | 3)  /*!< EXTI_POSITION_0  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE13              (uint32_t)(0x00F0U << 16 | 3)  /*!< EXTI_POSITION_4  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE14              (uint32_t)(0x0F00U << 16 | 3)  /*!< EXTI_POSITION_8  | EXTICR[3] */
+#define LL_SYSCFG_EXTI_LINE15              (uint32_t)(0xF000U << 16 | 3)  /*!< EXTI_POSITION_12 | EXTICR[3] */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
+  * @{
+  */
+#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
+#define LL_SYSCFG_TIMBREAK_LOCKUP          SYSCFG_CFGR2_LOCKUP_LOCK   /*!< Enables and locks the LOCKUP output of CortexM4 
+                                                                      with Break Input of TIM1/8                                    */
+#define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR2_PVD_LOCK      /*!< Enables and locks the PVD connection with TIM1/8 Break Input 
+                                                                      and also the PVDE and PLS bits of the Power Control Interface  */
+#endif /* SYSCFG_CFGR2_CLL */
+/**
+  * @}
+  */
+
+#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
+/** @defgroup SYSTEM_LL_DFSDM_BitStream_ClockSource SYSCFG MCHDLY BCKKSEL
+  * @{
+  */
+#define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1          (uint32_t)0x00000000
+#define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2           SYSCFG_MCHDLYCR_BSCKSEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM_MCHDLYEN              SYSCFG MCHDLY MCHDLYEN
+  * @{
+  */  
+#define LL_SYSCFG_DFSDM1_MCHDLYEN                  SYSCFG_MCHDLYCR_MCHDLY1EN
+#define LL_SYSCFG_DFSDM2_MCHDLYEN                  SYSCFG_MCHDLYCR_MCHDLY2EN
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM_DataIn0_Source       SYSCFG MCHDLY DFSDMD0SEL
+  * @{
+  */
+#define LL_SYSCFG_DFSDM1_DataIn0                   SYSCFG_MCHDLYCR_DFSDM1D0SEL
+#define LL_SYSCFG_DFSDM2_DataIn0                   SYSCFG_MCHDLYCR_DFSDM2D0SEL
+
+#define LL_SYSCFG_DFSDM1_DataIn0_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | 0x00000000)
+#define LL_SYSCFG_DFSDM1_DataIn0_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D0SEL)
+#define LL_SYSCFG_DFSDM2_DataIn0_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | 0x00000000)
+#define LL_SYSCFG_DFSDM2_DataIn0_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D0SEL)
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM_DataIn2_Source       SYSCFG MCHDLY DFSDMD2SEL
+  * @{
+  */   
+#define LL_SYSCFG_DFSDM1_DataIn2                   SYSCFG_MCHDLYCR_DFSDM1D2SEL
+#define LL_SYSCFG_DFSDM2_DataIn2                   SYSCFG_MCHDLYCR_DFSDM2D2SEL
+
+#define LL_SYSCFG_DFSDM1_DataIn2_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | 0x00000000)
+#define LL_SYSCFG_DFSDM1_DataIn2_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D2SEL)
+#define LL_SYSCFG_DFSDM2_DataIn2_PAD               (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | 0x00000000)
+#define LL_SYSCFG_DFSDM2_DataIn2_DM                (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D2SEL)
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC2_BitstreamDistribution  SYSCFG MCHDLY DFSDM1CK02SEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0           (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2           SYSCFG_MCHDLYCR_DFSDM1CK02SEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM1_TIM4OC1_BitstreamDistribution  SYSCFG MCHDLY DFSDM1CK13SEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1           (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3           SYSCFG_MCHDLYCR_DFSDM1CK13SEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM1_CLKIN_SourceSelection SYSCFG MCHDLY DFSDMCFG
+  * @{
+  */
+#define LL_SYSCFG_DFSDM1_CKIN_PAD                 (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM1_CKIN_DM                  SYSCFG_MCHDLYCR_DFSDM1CFG
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM1_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM1CKOSEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM1_CKOUT                    (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM1_CKOUT_M27                SYSCFG_MCHDLYCR_DFSDM1CKOSEL
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_DFSDM2_DataIn4_SourceSelection SYSCFG MCHDLY DFSDM2D4SEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM2_DataIn4_PAD              (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_DataIn4_DM               SYSCFG_MCHDLYCR_DFSDM2D4SEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM2_DataIn6_SourceSelection SYSCFG MCHDLY DFSDM2D6SEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM2_DataIn6_PAD              (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_DataIn6_DM               SYSCFG_MCHDLYCR_DFSDM2D6SEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC4_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK04SEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0           (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4           SYSCFG_MCHDLYCR_DFSDM2CK04SEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC3_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK15SEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1           (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5           SYSCFG_MCHDLYCR_DFSDM2CK15SEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC2_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK26SEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2           (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6           SYSCFG_MCHDLYCR_DFSDM2CK26SEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM2_TIM3OC1_BitstreamDistribution  SYSCFG MCHDLY DFSDM2CK37SEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3           (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7           SYSCFG_MCHDLYCR_DFSDM2CK37SEL
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM2_CLKIN_SourceSelection SYSCFG MCHDLY DFSDM2CFG
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM2_CKIN_PAD                 (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_CKIN_DM                  SYSCFG_MCHDLYCR_DFSDM2CFG
+/**
+  * @}
+  */
+/** @defgroup SYSTEM_LL_DFSDM2_CLKOUT_SourceSelection SYSCFG MCHDLY DFSDM2CKOSEL
+  * @{
+  */ 
+#define LL_SYSCFG_DFSDM2_CKOUT                    (uint32_t)0x00000000
+#define LL_SYSCFG_DFSDM2_CKOUT_M27                SYSCFG_MCHDLYCR_DFSDM2CKOSEL
+/**
+  * @}
+  */ 
+#endif /* SYSCFG_MCHDLYCR_BSCKSEL */  
+
+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
+  * @{
+  */
+#define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */
+#define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
+#define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
+  * @{
+  */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1_FZ_DBG_TIM2_STOP          /*!< TIM2 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1_FZ_DBG_TIM3_STOP          /*!< TIM3 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1_FZ_DBG_TIM4_STOP          /*!< TIM4 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1_FZ_DBG_TIM5_STOP          /*!< TIM5 counter stopped when core is halted */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1_FZ_DBG_TIM6_STOP          /*!< TIM6 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1_FZ_DBG_TIM7_STOP          /*!< TIM7 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_APB1_FZ_DBG_TIM12_STOP         /*!< TIM12 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_APB1_FZ_DBG_TIM13_STOP         /*!< TIM13 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
+#define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_APB1_FZ_DBG_TIM14_STOP         /*!< TIM14 counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP)
+#define LL_DBGMCU_APB1_GRP1_LPTIM_STOP     DBGMCU_APB1_FZ_DBG_LPTIM_STOP         /*!< LPTIM counter stopped when core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */
+#define LL_DBGMCU_APB1_GRP1_RTC_STOP       DBGMCU_APB1_FZ_DBG_RTC_STOP           /*!< RTC counter stopped when core is halted */
+#define LL_DBGMCU_APB1_GRP1_WWDG_STOP      DBGMCU_APB1_FZ_DBG_WWDG_STOP          /*!< Debug Window Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_IWDG_STOP      DBGMCU_APB1_FZ_DBG_IWDG_STOP          /*!< Debug Independent Watchdog stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
+#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
+#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
+#define LL_DBGMCU_APB1_GRP1_I2C4_STOP      DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when Core is halted */
+#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
+#if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN1_STOP      DBGMCU_APB1_FZ_DBG_CAN1_STOP          /*!< CAN1 debug stopped when Core is halted  */
+#endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN2_STOP      DBGMCU_APB1_FZ_DBG_CAN2_STOP          /*!< CAN2 debug stopped when Core is halted  */
+#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
+#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
+#define LL_DBGMCU_APB1_GRP1_CAN3_STOP      DBGMCU_APB1_FZ_DBG_CAN3_STOP          /*!< CAN3 debug stopped when Core is halted  */
+#endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
+  * @{
+  */
+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2_FZ_DBG_TIM1_STOP   /*!< TIM1 counter stopped when core is halted */
+#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2_FZ_DBG_TIM8_STOP   /*!< TIM8 counter stopped when core is halted */
+#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
+#define LL_DBGMCU_APB2_GRP1_TIM9_STOP      DBGMCU_APB2_FZ_DBG_TIM9_STOP   /*!< TIM9 counter stopped when core is halted */
+#if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP)
+#define LL_DBGMCU_APB2_GRP1_TIM10_STOP     DBGMCU_APB2_FZ_DBG_TIM10_STOP   /*!< TIM10 counter stopped when core is halted */
+#endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */
+#define LL_DBGMCU_APB2_GRP1_TIM11_STOP     DBGMCU_APB2_FZ_DBG_TIM11_STOP   /*!< TIM11 counter stopped when core is halted */
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
+  * @{
+  */
+#define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */
+#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */
+#define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */
+#define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */
+#define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */
+#define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */
+#define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */
+#define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */
+#define LL_FLASH_LATENCY_8                 FLASH_ACR_LATENCY_8WS   /*!< FLASH eight wait states */
+#define LL_FLASH_LATENCY_9                 FLASH_ACR_LATENCY_9WS   /*!< FLASH nine wait states */
+#define LL_FLASH_LATENCY_10                FLASH_ACR_LATENCY_10WS   /*!< FLASH ten wait states */
+#define LL_FLASH_LATENCY_11                FLASH_ACR_LATENCY_11WS   /*!< FLASH eleven wait states */
+#define LL_FLASH_LATENCY_12                FLASH_ACR_LATENCY_12WS   /*!< FLASH twelve wait states */
+#define LL_FLASH_LATENCY_13                FLASH_ACR_LATENCY_13WS   /*!< FLASH thirteen wait states */
+#define LL_FLASH_LATENCY_14                FLASH_ACR_LATENCY_14WS   /*!< FLASH fourteen wait states */
+#define LL_FLASH_LATENCY_15                FLASH_ACR_LATENCY_15WS   /*!< FLASH fifteen wait states */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
+  * @{
+  */
+
+/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
+  * @{
+  */
+/**
+  * @brief  Set memory mapping at address 0x00000000
+  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_SetRemapMemory
+  * @param  Memory This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_REMAP_FLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SRAM
+  *         @arg @ref LL_SYSCFG_REMAP_FSMC (*)
+  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
+{
+  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
+}
+
+/**
+  * @brief  Get memory mapping at address 0x00000000
+  * @rmtoll SYSCFG_MEMRMP MEM_MODE      LL_SYSCFG_GetRemapMemory
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_REMAP_FLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
+  *         @arg @ref LL_SYSCFG_REMAP_SRAM
+  *         @arg @ref LL_SYSCFG_REMAP_FSMC (*)
+  *         @arg @ref LL_SYSCFG_REMAP_FMC (*)
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
+}
+
+#if defined(SYSCFG_MEMRMP_SWP_FMC)
+/**
+  * @brief  Enables the FMC Memory Mapping Swapping
+  * @rmtoll SYSCFG_MEMRMP SWP_FMC      LL_SYSCFG_EnableFMCMemorySwapping
+  * @note   SDRAM is accessible at 0x60000000 and NOR/RAM 
+  *         is accessible at 0xC0000000   
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
+{
+  SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);
+}
+
+/**
+  * @brief  Disables the FMC Memory Mapping Swapping
+  * @rmtoll SYSCFG_MEMRMP SWP_FMC      LL_SYSCFG_DisableFMCMemorySwapping
+  * @note   SDRAM is accessible at 0xC0000000 (default mapping)  
+  *         and NOR/RAM is accessible at 0x60000000 (default mapping)
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)
+{
+  CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);
+}
+
+#endif /* SYSCFG_MEMRMP_SWP_FMC */
+/**
+  * @brief  Enables the Compensation cell Power Down
+  * @rmtoll SYSCFG_CMPCR CMP_PD      LL_SYSCFG_EnableCompensationCell
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
+{
+  SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
+}
+
+/**
+  * @brief  Disables the Compensation cell Power Down
+  * @rmtoll SYSCFG_CMPCR CMP_PD      LL_SYSCFG_DisableCompensationCell
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
+{
+  CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
+}
+
+/**
+  * @brief  Get Compensation Cell ready Flag
+  * @rmtoll SYSCFG_CMPCR READY  LL_SYSCFG_IsActiveFlag_CMPCR
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
+{
+  return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
+}
+
+#if defined(SYSCFG_PMC_MII_RMII_SEL)
+/**
+  * @brief  Select Ethernet PHY interface 
+  * @rmtoll SYSCFG_PMC MII_RMII_SEL       LL_SYSCFG_SetPHYInterface
+  * @param  Interface This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_PMC_ETHMII
+  *         @arg @ref LL_SYSCFG_PMC_ETHRMII
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
+{
+  MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
+}
+
+/**
+  * @brief  Get Ethernet PHY interface 
+  * @rmtoll SYSCFG_PMC MII_RMII_SEL       LL_SYSCFG_GetPHYInterface
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_PMC_ETHMII
+  *         @arg @ref LL_SYSCFG_PMC_ETHRMII
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
+}
+#endif /* SYSCFG_PMC_MII_RMII_SEL */
+ 
+
+
+#if defined(SYSCFG_MEMRMP_UFB_MODE)
+/**
+  * @brief  Select Flash bank mode (Bank flashed at 0x08000000)
+  * @rmtoll SYSCFG_MEMRMP UFB_MODE       LL_SYSCFG_SetFlashBankMode
+  * @param  Bank This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
+{ 
+  MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank);
+}
+
+/**
+  * @brief  Get Flash bank mode (Bank flashed at 0x08000000)
+  * @rmtoll SYSCFG_MEMRMP UFB_MODE       LL_SYSCFG_GetFlashBankMode
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK1
+  *         @arg @ref LL_SYSCFG_BANKMODE_BANK2
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE));
+}
+#endif /* SYSCFG_MEMRMP_UFB_MODE */
+
+#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
+/**
+  * @brief  Enable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_CFGR FMPI2C1_SCL   LL_SYSCFG_EnableFastModePlus\n
+  *         SYSCFG_CFGR FMPI2C1_SDA   LL_SYSCFG_EnableFastModePlus
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  SET_BIT(SYSCFG->CFGR, ConfigFastModePlus);
+}
+
+/**
+  * @brief  Disable the I2C fast mode plus driving capability.
+  * @rmtoll SYSCFG_CFGR FMPI2C1_SCL  LL_SYSCFG_DisableFastModePlus\n
+  *         SYSCFG_CFGR FMPI2C1_SDA  LL_SYSCFG_DisableFastModePlus\n
+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SCL
+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_SDA
+  *         (*) value not defined in all devices
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus);
+}
+#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
+
+/**
+  * @brief  Configure source input for the EXTI external interrupt.
+  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource
+  * @param  Port This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE
+  *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTH
+  *
+  *         (*) value not defined in all devices
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
+{
+  MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
+}
+
+/**
+  * @brief  Get the configured defined for specific EXTI Line
+  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n
+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource
+  * @param  Line This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_LINE0
+  *         @arg @ref LL_SYSCFG_EXTI_LINE1
+  *         @arg @ref LL_SYSCFG_EXTI_LINE2
+  *         @arg @ref LL_SYSCFG_EXTI_LINE3
+  *         @arg @ref LL_SYSCFG_EXTI_LINE4
+  *         @arg @ref LL_SYSCFG_EXTI_LINE5
+  *         @arg @ref LL_SYSCFG_EXTI_LINE6
+  *         @arg @ref LL_SYSCFG_EXTI_LINE7
+  *         @arg @ref LL_SYSCFG_EXTI_LINE8
+  *         @arg @ref LL_SYSCFG_EXTI_LINE9
+  *         @arg @ref LL_SYSCFG_EXTI_LINE10
+  *         @arg @ref LL_SYSCFG_EXTI_LINE11
+  *         @arg @ref LL_SYSCFG_EXTI_LINE12
+  *         @arg @ref LL_SYSCFG_EXTI_LINE13
+  *         @arg @ref LL_SYSCFG_EXTI_LINE14
+  *         @arg @ref LL_SYSCFG_EXTI_LINE15
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_EXTI_PORTA
+  *         @arg @ref LL_SYSCFG_EXTI_PORTB
+  *         @arg @ref LL_SYSCFG_EXTI_PORTC
+  *         @arg @ref LL_SYSCFG_EXTI_PORTD
+  *         @arg @ref LL_SYSCFG_EXTI_PORTE
+  *         @arg @ref LL_SYSCFG_EXTI_PORTF (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTG (*)
+  *         @arg @ref LL_SYSCFG_EXTI_PORTH
+  *         (*) value not defined in all devices
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
+}
+
+#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
+/**
+  * @brief  Set connections to TIM1/8 break inputs
+  * @rmtoll SYSCFG_CFGR2 LockUp Lock           LL_SYSCFG_SetTIMBreakInputs \n
+  *         SYSCFG_CFGR2 PVD Lock              LL_SYSCFG_SetTIMBreakInputs
+  * @param  Break This parameter can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
+{
+  MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break);
+}
+
+/**
+  * @brief  Get connections to TIM1/8 Break inputs
+  * @rmtoll SYSCFG_CFGR2 LockUp Lock           LL_SYSCFG_SetTIMBreakInputs \n
+  *         SYSCFG_CFGR2 PVD Lock              LL_SYSCFG_SetTIMBreakInputs
+  * @retval Returned value can be can be a combination of the following values:
+  *         @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
+{   
+  return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK));
+}
+#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
+#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
+/**
+  * @brief  Select the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
+  * @rmtoll SYSCFG_MCHDLYCR BSCKSEL        LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
+  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource);
+}
+/**
+  * @brief  Get the DFSDM2 or TIM2_OC1 as clock source for the bitstream clock.
+  * @rmtoll SYSCFG_MCHDLYCR BSCKSEL       LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2
+  *         @arg @ref LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL));
+}
+/**
+  * @brief  Enables the DFSDM1 or DFSDM2 Delay clock
+  * @rmtoll SYSCFG_MCHDLYCR MCHDLYEN      LL_SYSCFG_DFSDM_EnableDelayClock
+  * @param MCHDLY This parameter can be one of the following values
+  *         @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
+  *         @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY)
+{
+  SET_BIT(SYSCFG->MCHDLYCR, MCHDLY);
+}
+
+/**
+  * @brief  Disables the DFSDM1 or the DFSDM2 Delay clock
+  * @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN      LL_SYSCFG_DFSDM1_DisableDelayClock
+  * @param MCHDLY This parameter can be one of the following values
+  *         @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN
+  *         @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY)
+{
+  CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY);
+}
+
+/**
+  * @brief  Select the source for DFSDM1 or DFSDM2 DatIn0 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL        LL_SYSCFG_DFSDM_SetDataIn0Source
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
+}
+/**
+  * @brief  Get the source for DFSDM1 or DFSDM2 DatIn0.
+  * @rmtoll SYSCFG_MCHDLYCR DFSDMD0SEL       LL_SYSCFG_DFSDM_GetDataIn0Source
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn0_DM
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
+}
+/**
+  * @brief  Select the source for DFSDM1 or DFSDM2 DatIn2 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL        LL_SYSCFG_DFSDM_SetDataIn2Source
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
+}
+/**
+  * @brief  Get the source for DFSDM1 or DFSDM2 DatIn2.
+  * @rmtoll SYSCFG_MCHDLYCR DFSDMD2SEL       LL_SYSCFG_DFSDM_GetDataIn2Source
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM1_DataIn2_DM
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
+}
+
+/**
+  * @brief  Select the distribution of the bitsream lock gated by TIM4 OC2 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK02SEL        LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
+  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source);
+}
+/**
+  * @brief  Get the distribution of the bitsream lock gated by TIM4 OC2 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL       LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0
+  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL));
+}
+
+/**
+  * @brief  Select the distribution of the bitsream lock gated by TIM4 OC1 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CK13SEL        LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
+  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source);
+}
+/**
+  * @brief  Get the distribution of the bitsream lock gated by TIM4 OC1 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM1D2SEL       LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1
+  *         @arg @ref LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL));
+}
+
+/**
+  * @brief  Select the DFSDM1 Clock In 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG        LL_SYSCFG_DFSDM1_SetClockInSourceSelection
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource);
+}
+/**
+  * @brief  GET the DFSDM1 Clock In
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CFG       LL_SYSCFG_DFSDM1_GetClockInSourceSelection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM1_CKIN_DM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG));
+}
+
+/**
+  * @brief  Select the DFSDM1 Clock Out 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL        LL_SYSCFG_DFSDM1_SetClockOutSourceSelection
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT
+  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource);
+}
+/**
+  * @brief  GET the DFSDM1 Clock Out
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM1CKOSEL       LL_SYSCFG_DFSDM1_GetClockOutSourceSelection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT
+  *         @arg @ref LL_SYSCFG_DFSDM1_CKOUT_M27
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL));
+}
+
+/**
+  * @brief  Enables the DFSDM2 Delay clock
+  * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN      LL_SYSCFG_DFSDM2_EnableDelayClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void)
+{
+  SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
+}
+
+/**
+  * @brief  Disables the DFSDM2 Delay clock
+  * @rmtoll SYSCFG_MCHDLYCR MCHDLY2EN      LL_SYSCFG_DFSDM2_DisableDelayClock
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void)
+{
+  CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
+}
+/**
+  * @brief  Select the source for DFSDM2 DatIn0 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL        LL_SYSCFG_DFSDM2_SetDataIn0Source
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source);
+}
+/**
+  * @brief  Get the source for DFSDM2 DatIn0.
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D0SEL       LL_SYSCFG_DFSDM2_GetDataIn0Source
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn0_DM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL));
+}
+
+/**
+  * @brief  Select the source for DFSDM2 DatIn2 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL        LL_SYSCFG_DFSDM2_SetDataIn2Source
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source);
+}
+/**
+  * @brief  Get the source for DFSDM2 DatIn2.
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D2SEL       LL_SYSCFG_DFSDM2_GetDataIn2Source
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn2_DM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL));
+}
+
+/**
+  * @brief  Select the source for DFSDM2 DatIn4 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL        LL_SYSCFG_DFSDM2_SetDataIn4Source
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source);
+}
+/**
+  * @brief  Get the source for DFSDM2 DatIn4.
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D4SEL       LL_SYSCFG_DFSDM2_GetDataIn4Source
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn4_DM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL));
+}
+
+/**
+  * @brief  Select the source for DFSDM2 DatIn6 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL        LL_SYSCFG_DFSDM2_SetDataIn6Source
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source);
+}
+/**
+  * @brief  Get the source for DFSDM2 DatIn6.
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2D6SEL       LL_SYSCFG_DFSDM2_GetDataIn6Source
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_DataIn6_DM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL));
+}
+
+/**
+  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC4 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL        LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source);
+}
+/**
+  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC4 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL));
+}
+
+/**
+  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC3 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK15SEL        LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source);
+}
+/**
+  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC4 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL));
+}
+
+/**
+  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC2 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK26SEL        LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source);
+}
+/**
+  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC2 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK04SEL       LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL));
+}
+
+/**
+  * @brief  Select the distribution of the bitsream lock gated by TIM3 OC1 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL        LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source);
+}
+/**
+  * @brief  Get the distribution of the bitsream lock gated by TIM3 OC1 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CK37SEL       LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3
+  *         @arg @ref LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL));
+}
+
+/**
+  * @brief  Select the DFSDM2 Clock In 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG        LL_SYSCFG_DFSDM2_SetClockInSourceSelection
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource);
+}
+/**
+  * @brief  GET the DFSDM2 Clock In
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CFG       LL_SYSCFG_DFSDM2_GetClockInSourceSelection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_PAD
+  *         @arg @ref LL_SYSCFG_DFSDM2_CKIN_DM
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG));
+}
+
+/**
+  * @brief  Select the DFSDM2 Clock Out 
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL        LL_SYSCFG_DFSDM2_SetClockOutSourceSelection
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT
+  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
+  * @retval None
+  */
+__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource)
+{
+  MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource);
+}
+/**
+  * @brief  GET the DFSDM2 Clock Out
+  * @rmtoll SYSCFG_MCHDLYCR DFSDM2CKOSEL       LL_SYSCFG_DFSDM2_GetClockOutSourceSelection
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT
+  *         @arg @ref LL_SYSCFG_DFSDM2_CKOUT_M27
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void)
+{
+  return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL));
+}
+
+#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
+/**
+  * @}
+  */
+
+
+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
+  * @{
+  */
+
+/**
+  * @brief  Return the device identifier
+  * @note For STM32F405/407xx and STM32F415/417xx devices, the device ID is 0x413
+  * @note For STM32F42xxx and STM32F43xxx devices, the device ID is 0x419
+  * @note For STM32F401xx devices, the device ID is 0x423
+  * @note For STM32F401xx devices, the device ID is 0x433
+  * @note For STM32F411xx devices, the device ID is 0x431
+  * @note For STM32F410xx devices, the device ID is 0x458
+  * @note For STM32F412xx devices, the device ID is 0x441
+  * @note For STM32F413xx and STM32423xx devices, the device ID is 0x463
+  * @note For STM32F446xx devices, the device ID is 0x421
+  * @note For STM32F469xx and STM32F479xx devices, the device ID is 0x434
+  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID
+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
+}
+
+/**
+  * @brief  Return the device revision identifier
+  * @note This field indicates the revision of the device.
+          For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001, rev1 -> 0x1003, rev2 ->0x1007, revY -> 0x100F for STM32F405/407xx and STM32F415/417xx devices
+          For example, it is read as RevA -> 0x1000, Cat 2 revY -> 0x1003, rev1 -> 0x1007, rev3 ->0x2001 for STM32F42xxx and STM32F43xxx devices
+          For example, it is read as RevZ -> 0x1000, Cat 2 revA -> 0x1001 for STM32F401xB/C devices
+          For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001 for STM32F401xD/E devices
+          For example, it is read as RevA -> 0x1000 for STM32F411xx,STM32F413/423xx,STM32F469/423xx, STM32F446xx and STM32F410xx devices
+          For example, it is read as RevZ -> 0x1001, Cat 2 revB -> 0x2000, revC -> 0x3000 for STM32F412xx devices
+  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID
+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
+}
+
+/**
+  * @brief  Enable the Debug Module during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_EnableDBGSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Disable the Debug Module during SLEEP mode
+  * @rmtoll DBGMCU_CR    DBG_SLEEP     LL_DBGMCU_DisableDBGSleepMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STOP mode
+  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_EnableDBGStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Disable the Debug Module during STOP mode
+  * @rmtoll DBGMCU_CR    DBG_STOP      LL_DBGMCU_DisableDBGStopMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_EnableDBGStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Disable the Debug Module during STANDBY mode
+  * @rmtoll DBGMCU_CR    DBG_STANDBY   LL_DBGMCU_DisableDBGStandbyMode
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Set Trace pin assignment control
+  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_SetTracePinAssignment\n
+  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_SetTracePinAssignment
+  * @param  PinAssignment This parameter can be one of the following values:
+  *         @arg @ref LL_DBGMCU_TRACE_NONE
+  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
+{
+  MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
+}
+
+/**
+  * @brief  Get Trace pin assignment control
+  * @rmtoll DBGMCU_CR    TRACE_IOEN    LL_DBGMCU_GetTracePinAssignment\n
+  *         DBGMCU_CR    TRACE_MODE    LL_DBGMCU_GetTracePinAssignment
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DBGMCU_TRACE_NONE
+  *         @arg @ref LL_DBGMCU_TRACE_ASYNCH
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
+  *         @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
+  */
+__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
+{
+  return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
+}
+
+/**
+  * @brief  Freeze APB1 peripherals (group1 peripherals)
+  * @rmtoll DBGMCU_APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_LPTIM_STOP          LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C4_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN3_STOP           LL_DBGMCU_APB1_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP 
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
+  *         
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB1FZ, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB1 peripherals (group1 peripherals)
+  * @rmtoll DBGMCU_APB1_FZ      DBG_TIM2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM4_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM5_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM6_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM7_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM12_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM13_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_TIM14_STOP          LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_LPTIM_STOP         LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_RTC_STOP            LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_WWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_IWDG_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C1_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C2_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C3_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_I2C4_SMBUS_TIMEOUT  LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN1_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN2_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB1_FZ      DBG_CAN3_STOP           LL_DBGMCU_APB1_GRP1_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP 
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
+  *         
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
+}
+
+/**
+  * @brief  Freeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_FreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
+{
+  SET_BIT(DBGMCU->APB2FZ, Periphs);
+}
+
+/**
+  * @brief  Unfreeze APB2 peripherals
+  * @rmtoll DBGMCU_APB2_FZ      DBG_TIM1_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM8_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM9_STOP    LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM10_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
+  *         DBGMCU_APB2_FZ      DBG_TIM11_STOP   LL_DBGMCU_APB2_GRP1_UnFreezePeriph
+  * @param  Periphs This parameter can be a combination of the following values:
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*)
+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*)
+  *
+  *         (*) value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
+{
+  CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
+}
+/**
+  * @}
+  */
+
+/** @defgroup SYSTEM_LL_EF_FLASH FLASH
+  * @{
+  */
+
+/**
+  * @brief  Set FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency
+  * @param  Latency This parameter can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  *         @arg @ref LL_FLASH_LATENCY_2
+  *         @arg @ref LL_FLASH_LATENCY_3
+  *         @arg @ref LL_FLASH_LATENCY_4
+  *         @arg @ref LL_FLASH_LATENCY_5
+  *         @arg @ref LL_FLASH_LATENCY_6
+  *         @arg @ref LL_FLASH_LATENCY_7
+  *         @arg @ref LL_FLASH_LATENCY_8
+  *         @arg @ref LL_FLASH_LATENCY_9
+  *         @arg @ref LL_FLASH_LATENCY_10
+  *         @arg @ref LL_FLASH_LATENCY_11
+  *         @arg @ref LL_FLASH_LATENCY_12
+  *         @arg @ref LL_FLASH_LATENCY_13
+  *         @arg @ref LL_FLASH_LATENCY_14
+  *         @arg @ref LL_FLASH_LATENCY_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
+{
+  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
+}
+
+/**
+  * @brief  Get FLASH Latency
+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_FLASH_LATENCY_0
+  *         @arg @ref LL_FLASH_LATENCY_1
+  *         @arg @ref LL_FLASH_LATENCY_2
+  *         @arg @ref LL_FLASH_LATENCY_3
+  *         @arg @ref LL_FLASH_LATENCY_4
+  *         @arg @ref LL_FLASH_LATENCY_5
+  *         @arg @ref LL_FLASH_LATENCY_6
+  *         @arg @ref LL_FLASH_LATENCY_7
+  *         @arg @ref LL_FLASH_LATENCY_8
+  *         @arg @ref LL_FLASH_LATENCY_9
+  *         @arg @ref LL_FLASH_LATENCY_10
+  *         @arg @ref LL_FLASH_LATENCY_11
+  *         @arg @ref LL_FLASH_LATENCY_12
+  *         @arg @ref LL_FLASH_LATENCY_13
+  *         @arg @ref LL_FLASH_LATENCY_14
+  *         @arg @ref LL_FLASH_LATENCY_15
+  */
+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
+{
+  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
+}
+
+/**
+  * @brief  Enable Prefetch
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_EnablePrefetch
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+  * @brief  Disable Prefetch
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_DisablePrefetch
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
+}
+
+/**
+  * @brief  Check if Prefetch buffer is enabled
+  * @rmtoll FLASH_ACR    PRFTEN        LL_FLASH_IsPrefetchEnabled
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
+{
+  return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
+}
+
+/**
+  * @brief  Enable Instruction cache
+  * @rmtoll FLASH_ACR    ICEN          LL_FLASH_EnableInstCache
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
+}
+
+/**
+  * @brief  Disable Instruction cache
+  * @rmtoll FLASH_ACR    ICEN          LL_FLASH_DisableInstCache
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
+}
+
+/**
+  * @brief  Enable Data cache
+  * @rmtoll FLASH_ACR    DCEN          LL_FLASH_EnableDataCache
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
+}
+
+/**
+  * @brief  Disable Data cache
+  * @rmtoll FLASH_ACR    DCEN          LL_FLASH_DisableDataCache
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
+}
+
+/**
+  * @brief  Enable Instruction cache reset
+  * @note  bit can be written only when the instruction cache is disabled
+  * @rmtoll FLASH_ACR    ICRST         LL_FLASH_EnableInstCacheReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
+}
+
+/**
+  * @brief  Disable Instruction cache reset
+  * @rmtoll FLASH_ACR    ICRST         LL_FLASH_DisableInstCacheReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
+}
+
+/**
+  * @brief  Enable Data cache reset
+  * @note bit can be written only when the data cache is disabled
+  * @rmtoll FLASH_ACR    DCRST         LL_FLASH_EnableDataCacheReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
+{
+  SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
+}
+
+/**
+  * @brief  Disable Data cache reset
+  * @rmtoll FLASH_ACR    DCRST         LL_FLASH_DisableDataCacheReset
+  * @retval None
+  */
+__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
+{
+  CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_SYSTEM_H */
+
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h
index e07c232..64f59b0 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_usart.h
@@ -1,2521 +1,2521 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_ll_usart.h
-  * @author  MCD Application Team
-  * @brief   Header file of USART LL module.
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_USART_H
-#define __STM32F4xx_LL_USART_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_LL_Driver
-  * @{
-  */
-
-#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10)
-
-/** @defgroup USART_LL USART
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup USART_LL_Private_Constants USART Private Constants
-  * @{
-  */
-
-/* Defines used for the bit position in the register and perform offsets*/
-#define USART_POSITION_GTPR_GT                  USART_GTPR_GT_Pos
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_Private_Macros USART Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/* Exported types ------------------------------------------------------------*/
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_ES_INIT USART Exported Init structures
-  * @{
-  */
-
-/**
-  * @brief LL USART Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
-
-                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
-
-  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
-
-                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
-
-                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
-
-                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
-
-  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
-
-                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
-
-  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
-
-                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
-
-  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
-                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
-
-                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
-
-} LL_USART_InitTypeDef;
-
-/**
-  * @brief LL USART Clock Init Structure definition
-  */
-typedef struct
-{
-  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
-                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
-
-                                           USART HW configuration can be modified afterwards using unitary functions
-                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
-                                           For more details, refer to description of this function. */
-
-  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
-                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
-
-                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
-                                           For more details, refer to description of this function. */
-
-  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
-                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
-
-                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
-                                           For more details, refer to description of this function. */
-
-  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
-
-                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
-                                           For more details, refer to description of this function. */
-
-} LL_USART_ClockInitTypeDef;
-
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Constants USART Exported Constants
-  * @{
-  */
-
-/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
-  * @brief    Flags defines which can be used with LL_USART_ReadReg function
-  * @{
-  */
-#define LL_USART_SR_PE                          USART_SR_PE                   /*!< Parity error flag */
-#define LL_USART_SR_FE                          USART_SR_FE                   /*!< Framing error flag */
-#define LL_USART_SR_NE                          USART_SR_NE                   /*!< Noise detected flag */
-#define LL_USART_SR_ORE                         USART_SR_ORE                  /*!< Overrun error flag */
-#define LL_USART_SR_IDLE                        USART_SR_IDLE                 /*!< Idle line detected flag */
-#define LL_USART_SR_RXNE                        USART_SR_RXNE                 /*!< Read data register not empty flag */
-#define LL_USART_SR_TC                          USART_SR_TC                   /*!< Transmission complete flag */
-#define LL_USART_SR_TXE                         USART_SR_TXE                  /*!< Transmit data register empty flag */
-#define LL_USART_SR_LBD                         USART_SR_LBD                  /*!< LIN break detection flag */
-#define LL_USART_SR_CTS                         USART_SR_CTS                  /*!< CTS flag */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_IT IT Defines
-  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
-  * @{
-  */
-#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
-#define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */
-#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
-#define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */
-#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
-#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
-#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
-#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_DIRECTION Communication Direction
-  * @{
-  */
-#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
-#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
-#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
-#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_PARITY Parity Control
-  * @{
-  */
-#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
-#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
-#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_WAKEUP Wakeup
-  * @{
-  */
-#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
-#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
-  * @{
-  */
-#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
-#define LL_USART_DATAWIDTH_9B                   USART_CR1_M             /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
-  * @{
-  */
-#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
-#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EC_CLOCK Clock Signal
-  * @{
-  */
-
-#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
-#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
-/**
-  * @}
-  */
-#endif /*USE_FULL_LL_DRIVER*/
-
-/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
-  * @{
-  */
-#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
-#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_PHASE Clock Phase
-  * @{
-  */
-#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
-#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_POLARITY Clock Polarity
-  * @{
-  */
-#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
-#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_STOPBITS Stop Bits
-  * @{
-  */
-#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
-#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
-#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
-#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
-  * @{
-  */
-#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
-#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
-#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
-#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
-  * @{
-  */
-#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
-#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
-  * @{
-  */
-#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
-#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup USART_LL_Exported_Macros USART Exported Macros
-  * @{
-  */
-
-/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
-  * @{
-  */
-
-/**
-  * @brief  Write a value in USART register
-  * @param  __INSTANCE__ USART Instance
-  * @param  __REG__ Register to be written
-  * @param  __VALUE__ Value to be written in the register
-  * @retval None
-  */
-#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
-
-/**
-  * @brief  Read a value in USART register
-  * @param  __INSTANCE__ USART Instance
-  * @param  __REG__ Register to be read
-  * @retval Register value
-  */
-#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
-  * @{
-  */
-
-/**
-  * @brief  Compute USARTDIV value according to Peripheral Clock and
-  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
-  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
-  * @param  __BAUDRATE__ Baud rate value to achieve
-  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
-  */
-#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__)      ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(2*((uint64_t)(__BAUDRATE__)))))
-#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)      (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)
-#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)      ((((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8)\
-                                                                         + 50) / 100)
-/* UART BRR = mantissa + overflow + fraction
-            = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */
-#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)             (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
-                                                                            ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \
-                                                                           (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07))
-
-/**
-  * @brief  Compute USARTDIV value according to Peripheral Clock and
-  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
-  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
-  * @param  __BAUDRATE__ Baud rate value to achieve
-  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
-  */
-#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__)     ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(4*((uint64_t)(__BAUDRATE__)))))
-#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)     (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
-#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)     ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16)\
-                                                                         + 50) / 100)
-/* USART BRR = mantissa + overflow + fraction
-            = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
-#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)            (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
-                                                                            (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \
-                                                                           (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F))
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup USART_LL_Exported_Functions USART Exported Functions
-  * @{
-  */
-
-/** @defgroup USART_LL_EF_Configuration Configuration functions
-  * @{
-  */
-
-/**
-  * @brief  USART Enable
-  * @rmtoll CR1          UE            LL_USART_Enable
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
-  * @brief  USART Disable (all USART prescalers and outputs are disabled)
-  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
-  *         and current operations are discarded. The configuration of the USART is kept, but all the status
-  *         flags, in the USARTx_SR are set to their default values.
-  * @rmtoll CR1          UE            LL_USART_Disable
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
-}
-
-/**
-  * @brief  Indicate if USART is enabled
-  * @rmtoll CR1          UE            LL_USART_IsEnabled
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
-}
-
-/**
-  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
-  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
-  * @brief  Receiver Disable
-  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
-}
-
-/**
-  * @brief  Transmitter Enable
-  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
-  * @brief  Transmitter Disable
-  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
-}
-
-/**
-  * @brief  Configure simultaneously enabled/disabled states
-  *         of Transmitter and Receiver
-  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
-  *         CR1          TE            LL_USART_SetTransferDirection
-  * @param  USARTx USART Instance
-  * @param  TransferDirection This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DIRECTION_NONE
-  *         @arg @ref LL_USART_DIRECTION_RX
-  *         @arg @ref LL_USART_DIRECTION_TX
-  *         @arg @ref LL_USART_DIRECTION_TX_RX
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
-{
-  ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
-}
-
-/**
-  * @brief  Return enabled/disabled states of Transmitter and Receiver
-  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
-  *         CR1          TE            LL_USART_GetTransferDirection
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_DIRECTION_NONE
-  *         @arg @ref LL_USART_DIRECTION_RX
-  *         @arg @ref LL_USART_DIRECTION_TX
-  *         @arg @ref LL_USART_DIRECTION_TX_RX
-  */
-__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
-}
-
-/**
-  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
-  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
-  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
-  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
-  * @rmtoll CR1          PS            LL_USART_SetParity\n
-  *         CR1          PCE           LL_USART_SetParity
-  * @param  USARTx USART Instance
-  * @param  Parity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PARITY_NONE
-  *         @arg @ref LL_USART_PARITY_EVEN
-  *         @arg @ref LL_USART_PARITY_ODD
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
-}
-
-/**
-  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
-  * @rmtoll CR1          PS            LL_USART_GetParity\n
-  *         CR1          PCE           LL_USART_GetParity
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_PARITY_NONE
-  *         @arg @ref LL_USART_PARITY_EVEN
-  *         @arg @ref LL_USART_PARITY_ODD
-  */
-__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
-}
-
-/**
-  * @brief  Set Receiver Wake Up method from Mute mode.
-  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
-  * @param  USARTx USART Instance
-  * @param  Method This parameter can be one of the following values:
-  *         @arg @ref LL_USART_WAKEUP_IDLELINE
-  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
-}
-
-/**
-  * @brief  Return Receiver Wake Up method from Mute mode
-  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_WAKEUP_IDLELINE
-  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
-  */
-__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
-}
-
-/**
-  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
-  * @rmtoll CR1          M             LL_USART_SetDataWidth
-  * @param  USARTx USART Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DATAWIDTH_8B
-  *         @arg @ref LL_USART_DATAWIDTH_9B
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
-}
-
-/**
-  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
-  * @rmtoll CR1          M             LL_USART_GetDataWidth
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_DATAWIDTH_8B
-  *         @arg @ref LL_USART_DATAWIDTH_9B
-  */
-__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
-}
-
-/**
-  * @brief  Set Oversampling to 8-bit or 16-bit mode
-  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
-  * @param  USARTx USART Instance
-  * @param  OverSampling This parameter can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
-}
-
-/**
-  * @brief  Return Oversampling mode
-  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  */
-__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
-}
-
-/**
-  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
-  * @param  USARTx USART Instance
-  * @param  LastBitClockPulse This parameter can be one of the following values:
-  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
-  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
-}
-
-/**
-  * @brief  Retrieve Clock pulse of the last data bit output configuration
-  *         (Last bit Clock pulse output to the SCLK pin or not)
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
-  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
-  */
-__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
-}
-
-/**
-  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
-  * @param  USARTx USART Instance
-  * @param  ClockPhase This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PHASE_1EDGE
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
-}
-
-/**
-  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_PHASE_1EDGE
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  */
-__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
-}
-
-/**
-  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
-  * @param  USARTx USART Instance
-  * @param  ClockPolarity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_POLARITY_LOW
-  *         @arg @ref LL_USART_POLARITY_HIGH
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
-}
-
-/**
-  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_POLARITY_LOW
-  *         @arg @ref LL_USART_POLARITY_HIGH
-  */
-__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
-}
-
-/**
-  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
-  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
-  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
-  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
-  *         CR2          CPOL          LL_USART_ConfigClock\n
-  *         CR2          LBCL          LL_USART_ConfigClock
-  * @param  USARTx USART Instance
-  * @param  Phase This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PHASE_1EDGE
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  * @param  Polarity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_POLARITY_LOW
-  *         @arg @ref LL_USART_POLARITY_HIGH
-  * @param  LBCPOutput This parameter can be one of the following values:
-  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
-  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
-}
-
-/**
-  * @brief  Enable Clock output on SCLK pin
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
-  * @brief  Disable Clock output on SCLK pin
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
-  * @brief  Indicate if Clock output on SCLK pin is enabled
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
-}
-
-/**
-  * @brief  Set the length of the stop bits
-  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
-  * @param  USARTx USART Instance
-  * @param  StopBits This parameter can be one of the following values:
-  *         @arg @ref LL_USART_STOPBITS_0_5
-  *         @arg @ref LL_USART_STOPBITS_1
-  *         @arg @ref LL_USART_STOPBITS_1_5
-  *         @arg @ref LL_USART_STOPBITS_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
-  * @brief  Retrieve the length of the stop bits
-  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_STOPBITS_0_5
-  *         @arg @ref LL_USART_STOPBITS_1
-  *         @arg @ref LL_USART_STOPBITS_1_5
-  *         @arg @ref LL_USART_STOPBITS_2
-  */
-__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
-}
-
-/**
-  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
-  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
-  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
-  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
-  *         CR1          PCE           LL_USART_ConfigCharacter\n
-  *         CR1          M             LL_USART_ConfigCharacter\n
-  *         CR2          STOP          LL_USART_ConfigCharacter
-  * @param  USARTx USART Instance
-  * @param  DataWidth This parameter can be one of the following values:
-  *         @arg @ref LL_USART_DATAWIDTH_8B
-  *         @arg @ref LL_USART_DATAWIDTH_9B
-  * @param  Parity This parameter can be one of the following values:
-  *         @arg @ref LL_USART_PARITY_NONE
-  *         @arg @ref LL_USART_PARITY_EVEN
-  *         @arg @ref LL_USART_PARITY_ODD
-  * @param  StopBits This parameter can be one of the following values:
-  *         @arg @ref LL_USART_STOPBITS_0_5
-  *         @arg @ref LL_USART_STOPBITS_1
-  *         @arg @ref LL_USART_STOPBITS_1_5
-  *         @arg @ref LL_USART_STOPBITS_2
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
-                                              uint32_t StopBits)
-{
-  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
-  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
-}
-
-/**
-  * @brief  Set Address of the USART node.
-  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
-  *         for wake up with address mark detection.
-  * @rmtoll CR2          ADD           LL_USART_SetNodeAddress
-  * @param  USARTx USART Instance
-  * @param  NodeAddress 4 bit Address of the USART node.
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD));
-}
-
-/**
-  * @brief  Return 4 bit Address of the USART node as set in ADD field of CR2.
-  * @note   only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
-  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
-  * @param  USARTx USART Instance
-  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD));
-}
-
-/**
-  * @brief  Enable RTS HW Flow Control
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
-  * @brief  Disable RTS HW Flow Control
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
-}
-
-/**
-  * @brief  Enable CTS HW Flow Control
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
-  * @brief  Disable CTS HW Flow Control
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
-}
-
-/**
-  * @brief  Configure HW Flow Control mode (both CTS and RTS)
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
-  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @param  HardwareFlowControl This parameter can be one of the following values:
-  *         @arg @ref LL_USART_HWCONTROL_NONE
-  *         @arg @ref LL_USART_HWCONTROL_RTS
-  *         @arg @ref LL_USART_HWCONTROL_CTS
-  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
-}
-
-/**
-  * @brief  Return HW Flow Control configuration (both CTS and RTS)
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
-  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_HWCONTROL_NONE
-  *         @arg @ref LL_USART_HWCONTROL_RTS
-  *         @arg @ref LL_USART_HWCONTROL_CTS
-  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
-  */
-__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
-}
-
-/**
-  * @brief  Enable One bit sampling method
-  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
-  * @brief  Disable One bit sampling method
-  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
-}
-
-/**
-  * @brief  Indicate if One bit sampling method is enabled
-  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
-}
-
-/**
-  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
-  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
-  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
-  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
-  *         (Baud rate value != 0)
-  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
-  * @param  USARTx USART Instance
-  * @param  PeriphClk Peripheral Clock
-  * @param  OverSampling This parameter can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  * @param  BaudRate Baud Rate
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
-                                          uint32_t BaudRate)
-{
-  if (OverSampling == LL_USART_OVERSAMPLING_8)
-  {
-    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
-  }
-  else
-  {
-    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
-  }
-}
-
-/**
-  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
-  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
-  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
-  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
-  * @param  USARTx USART Instance
-  * @param  PeriphClk Peripheral Clock
-  * @param  OverSampling This parameter can be one of the following values:
-  *         @arg @ref LL_USART_OVERSAMPLING_16
-  *         @arg @ref LL_USART_OVERSAMPLING_8
-  * @retval Baud Rate
-  */
-__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
-{
-  uint32_t usartdiv = 0x0U;
-  uint32_t brrresult = 0x0U;
-
-  usartdiv = USARTx->BRR;
-
-  if (OverSampling == LL_USART_OVERSAMPLING_8)
-  {
-    if ((usartdiv & 0xFFF7U) != 0U)
-    {
-      usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
-      brrresult = (PeriphClk * 2U) / usartdiv;
-    }
-  }
-  else
-  {
-    if ((usartdiv & 0xFFFFU) != 0U)
-    {
-      brrresult = PeriphClk / usartdiv;
-    }
-  }
-  return (brrresult);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
-  * @{
-  */
-
-/**
-  * @brief  Enable IrDA mode
-  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IREN          LL_USART_EnableIrda
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
-  * @brief  Disable IrDA mode
-  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IREN          LL_USART_DisableIrda
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
-  * @brief  Indicate if IrDA mode is enabled
-  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
-}
-
-/**
-  * @brief  Configure IrDA Power Mode (Normal or Low Power)
-  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
-  * @param  USARTx USART Instance
-  * @param  PowerMode This parameter can be one of the following values:
-  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
-  *         @arg @ref LL_USART_IRDA_POWER_LOW
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
-{
-  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
-}
-
-/**
-  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
-  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
-  *         @arg @ref LL_USART_PHASE_2EDGE
-  */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
-}
-
-/**
-  * @brief  Set Irda prescaler value, used for dividing the USART clock source
-  *         to achieve the Irda Low Power frequency (8 bits value)
-  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
-  * @param  USARTx USART Instance
-  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
-  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
-}
-
-/**
-  * @brief  Return Irda prescaler value, used for dividing the USART clock source
-  *         to achieve the Irda Low Power frequency (8 bits value)
-  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
-  * @param  USARTx USART Instance
-  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
-  * @{
-  */
-
-/**
-  * @brief  Enable Smartcard NACK transmission
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
-  * @brief  Disable Smartcard NACK transmission
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
-}
-
-/**
-  * @brief  Indicate if Smartcard NACK transmission is enabled
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
-}
-
-/**
-  * @brief  Enable Smartcard mode
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
-  * @brief  Disable Smartcard mode
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
-  * @brief  Indicate if Smartcard mode is enabled
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
-}
-
-/**
-  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
-  *         source to provide the SMARTCARD Clock (5 bits value)
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
-  * @param  USARTx USART Instance
-  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
-{
-  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
-}
-
-/**
-  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
-  *         source to provide the SMARTCARD Clock (5 bits value)
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
-  * @param  USARTx USART Instance
-  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
-}
-
-/**
-  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
-  *         (GT[7:0] bits : Guard time value)
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
-  * @param  USARTx USART Instance
-  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
-{
-  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);
-}
-
-/**
-  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
-  *         (GT[7:0] bits : Guard time value)
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
-  * @param  USARTx USART Instance
-  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
-  */
-__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
-  * @{
-  */
-
-/**
-  * @brief  Enable Single Wire Half-Duplex mode
-  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Disable Single Wire Half-Duplex mode
-  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
-  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
-  * @{
-  */
-
-/**
-  * @brief  Set LIN Break Detection Length
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
-  * @param  USARTx USART Instance
-  * @param  LINBDLength This parameter can be one of the following values:
-  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
-  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
-{
-  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
-}
-
-/**
-  * @brief  Return LIN Break Detection Length
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
-  * @param  USARTx USART Instance
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
-  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
-  */
-__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
-{
-  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
-}
-
-/**
-  * @brief  Enable LIN mode
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
-  * @brief  Disable LIN mode
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
-  * @brief  Indicate if LIN mode is enabled
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
-  * @{
-  */
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
-  * @note   In UART mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - CLKEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  * @note   Other remaining configurations items related to Asynchronous Mode
-  *         (as Baud Rate, Word length, Parity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
-  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
-  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
-  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
-  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
-{
-  /* In Asynchronous mode, the following bits must be kept cleared:
-  - LINEN, CLKEN bits in the USART_CR2 register,
-  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
-  * @note   In Synchronous mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also sets the USART in Synchronous mode.
-  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
-  *         Synchronous mode is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
-  * @note   Other remaining configurations items related to Synchronous Mode
-  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
-  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
-  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
-  *         CR3          IREN          LL_USART_ConfigSyncMode\n
-  *         CR3          HDSEL         LL_USART_ConfigSyncMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
-{
-  /* In Synchronous mode, the following bits must be kept cleared:
-  - LINEN bit in the USART_CR2 register,
-  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
-  /* set the UART/USART in Synchronous mode */
-  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
-  * @note   In LIN mode, the following bits must be kept cleared:
-  *           - STOP and CLKEN bits in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also set the UART/USART in LIN mode.
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
-  * @note   Other remaining configurations items related to LIN Mode
-  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
-  *         CR2          STOP          LL_USART_ConfigLINMode\n
-  *         CR2          LINEN         LL_USART_ConfigLINMode\n
-  *         CR3          IREN          LL_USART_ConfigLINMode\n
-  *         CR3          SCEN          LL_USART_ConfigLINMode\n
-  *         CR3          HDSEL         LL_USART_ConfigLINMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
-{
-  /* In LIN mode, the following bits must be kept cleared:
-  - STOP and CLKEN bits in the USART_CR2 register,
-  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
-  /* Set the UART/USART in LIN mode */
-  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
-  * @note   In Half Duplex mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - CLKEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *         This function also sets the UART/USART in Half Duplex mode.
-  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
-  *         Half-Duplex mode is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
-  * @note   Other remaining configurations items related to Half Duplex Mode
-  *         (as Baud Rate, Word length, Parity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
-  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
-  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
-  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
-  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
-{
-  /* In Half Duplex mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN and IREN bits in the USART_CR3 register.*/
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
-  /* set the UART/USART in Half Duplex mode */
-  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
-  * @note   In Smartcard mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also configures Stop bits to 1.5 bits and
-  *         sets the USART in Smartcard mode (SCEN bit).
-  *         Clock Output is also enabled (CLKEN).
-  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
-  *         Smartcard feature is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
-  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
-  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
-  * @note   Other remaining configurations items related to Smartcard Mode
-  *         (as Baud Rate, Word length, Parity, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
-  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
-  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
-  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
-  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
-{
-  /* In Smartcard mode, the following bits must be kept cleared:
-  - LINEN bit in the USART_CR2 register,
-  - IREN and HDSEL bits in the USART_CR3 register.*/
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
-  /* Configure Stop bits to 1.5 bits */
-  /* Synchronous mode is activated by default */
-  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
-  /* set the UART/USART in Smartcard mode */
-  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
-  * @note   In IRDA mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - STOP and CLKEN bits in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  *         This function also sets the UART/USART in IRDA mode (IREN bit).
-  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
-  *         IrDA feature is supported by the USARTx instance.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
-  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
-  * @note   Other remaining configurations items related to Irda Mode
-  *         (as Baud Rate, Word length, Power mode, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
-  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
-  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
-  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
-  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
-  *         CR3          IREN          LL_USART_ConfigIrdaMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
-{
-  /* In IRDA mode, the following bits must be kept cleared:
-  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
-  - SCEN and HDSEL bits in the USART_CR3 register.*/
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-  /* set the UART/USART in IRDA mode */
-  SET_BIT(USARTx->CR3, USART_CR3_IREN);
-}
-
-/**
-  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
-  *         (several USARTs connected in a network, one of the USARTs can be the master,
-  *         its TX output connected to the RX inputs of the other slaves USARTs).
-  * @note   In MultiProcessor mode, the following bits must be kept cleared:
-  *           - LINEN bit in the USART_CR2 register,
-  *           - CLKEN bit in the USART_CR2 register,
-  *           - SCEN bit in the USART_CR3 register,
-  *           - IREN bit in the USART_CR3 register,
-  *           - HDSEL bit in the USART_CR3 register.
-  * @note   Call of this function is equivalent to following function call sequence :
-  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
-  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
-  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
-  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
-  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
-  * @note   Other remaining configurations items related to Multi processor Mode
-  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
-  *         dedicated functions
-  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
-  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
-  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
-  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
-  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
-{
-  /* In Multi Processor mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
-  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
-  * @{
-  */
-
-/**
-  * @brief  Check if the USART Parity Error Flag is set or not
-  * @rmtoll SR           PE            LL_USART_IsActiveFlag_PE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE));
-}
-
-/**
-  * @brief  Check if the USART Framing Error Flag is set or not
-  * @rmtoll SR           FE            LL_USART_IsActiveFlag_FE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE));
-}
-
-/**
-  * @brief  Check if the USART Noise error detected Flag is set or not
-  * @rmtoll SR           NF            LL_USART_IsActiveFlag_NE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE));
-}
-
-/**
-  * @brief  Check if the USART OverRun Error Flag is set or not
-  * @rmtoll SR           ORE           LL_USART_IsActiveFlag_ORE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE));
-}
-
-/**
-  * @brief  Check if the USART IDLE line detected Flag is set or not
-  * @rmtoll SR           IDLE          LL_USART_IsActiveFlag_IDLE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE));
-}
-
-/**
-  * @brief  Check if the USART Read Data Register Not Empty Flag is set or not
-  * @rmtoll SR           RXNE          LL_USART_IsActiveFlag_RXNE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE));
-}
-
-/**
-  * @brief  Check if the USART Transmission Complete Flag is set or not
-  * @rmtoll SR           TC            LL_USART_IsActiveFlag_TC
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC));
-}
-
-/**
-  * @brief  Check if the USART Transmit Data Register Empty Flag is set or not
-  * @rmtoll SR           TXE           LL_USART_IsActiveFlag_TXE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE));
-}
-
-/**
-  * @brief  Check if the USART LIN Break Detection Flag is set or not
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll SR           LBD           LL_USART_IsActiveFlag_LBD
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD));
-}
-
-/**
-  * @brief  Check if the USART CTS Flag is set or not
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll SR           CTS           LL_USART_IsActiveFlag_nCTS
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS));
-}
-
-/**
-  * @brief  Check if the USART Send Break Flag is set or not
-  * @rmtoll CR1          SBK           LL_USART_IsActiveFlag_SBK
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK));
-}
-
-/**
-  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
-  * @rmtoll CR1          RWU           LL_USART_IsActiveFlag_RWU
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU));
-}
-
-/**
-  * @brief  Clear Parity Error Flag
-  * @note   Clearing this flag is done by a read access to the USARTx_SR
-  *         register followed by a read access to the USARTx_DR register.
-  * @note   Please also consider that when clearing this flag, other flags as
-  *         NE, FE, ORE, IDLE would also be cleared.
-  * @rmtoll SR           PE            LL_USART_ClearFlag_PE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = USARTx->SR;
-  (void) tmpreg;
-  tmpreg = USARTx->DR;
-  (void) tmpreg;
-}
-
-/**
-  * @brief  Clear Framing Error Flag
-  * @note   Clearing this flag is done by a read access to the USARTx_SR
-  *         register followed by a read access to the USARTx_DR register.
-  * @note   Please also consider that when clearing this flag, other flags as
-  *         PE, NE, ORE, IDLE would also be cleared.
-  * @rmtoll SR           FE            LL_USART_ClearFlag_FE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = USARTx->SR;
-  (void) tmpreg;
-  tmpreg = USARTx->DR;
-  (void) tmpreg;
-}
-
-/**
-  * @brief  Clear Noise detected Flag
-  * @note   Clearing this flag is done by a read access to the USARTx_SR
-  *         register followed by a read access to the USARTx_DR register.
-  * @note   Please also consider that when clearing this flag, other flags as
-  *         PE, FE, ORE, IDLE would also be cleared.
-  * @rmtoll SR           NF            LL_USART_ClearFlag_NE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = USARTx->SR;
-  (void) tmpreg;
-  tmpreg = USARTx->DR;
-  (void) tmpreg;
-}
-
-/**
-  * @brief  Clear OverRun Error Flag
-  * @note   Clearing this flag is done by a read access to the USARTx_SR
-  *         register followed by a read access to the USARTx_DR register.
-  * @note   Please also consider that when clearing this flag, other flags as
-  *         PE, NE, FE, IDLE would also be cleared.
-  * @rmtoll SR           ORE           LL_USART_ClearFlag_ORE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = USARTx->SR;
-  (void) tmpreg;
-  tmpreg = USARTx->DR;
-  (void) tmpreg;
-}
-
-/**
-  * @brief  Clear IDLE line detected Flag
-  * @note   Clearing this flag is done by a read access to the USARTx_SR
-  *         register followed by a read access to the USARTx_DR register.
-  * @note   Please also consider that when clearing this flag, other flags as
-  *         PE, NE, FE, ORE would also be cleared.
-  * @rmtoll SR           IDLE          LL_USART_ClearFlag_IDLE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
-{
-  __IO uint32_t tmpreg;
-  tmpreg = USARTx->SR;
-  (void) tmpreg;
-  tmpreg = USARTx->DR;
-  (void) tmpreg;
-}
-
-/**
-  * @brief  Clear Transmission Complete Flag
-  * @rmtoll SR           TC            LL_USART_ClearFlag_TC
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->SR, ~(USART_SR_TC));
-}
-
-/**
-  * @brief  Clear RX Not Empty Flag
-  * @rmtoll SR           RXNE          LL_USART_ClearFlag_RXNE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->SR, ~(USART_SR_RXNE));
-}
-
-/**
-  * @brief  Clear LIN Break Detection Flag
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll SR           LBD           LL_USART_ClearFlag_LBD
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->SR, ~(USART_SR_LBD));
-}
-
-/**
-  * @brief  Clear CTS Interrupt Flag
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll SR           CTS           LL_USART_ClearFlag_nCTS
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
-{
-  WRITE_REG(USARTx->SR, ~(USART_SR_CTS));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_IT_Management IT_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable IDLE Interrupt
-  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/**
-  * @brief  Enable RX Not Empty Interrupt
-  * @rmtoll CR1          RXNEIE        LL_USART_EnableIT_RXNE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
-}
-
-/**
-  * @brief  Enable Transmission Complete Interrupt
-  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/**
-  * @brief  Enable TX Empty Interrupt
-  * @rmtoll CR1          TXEIE         LL_USART_EnableIT_TXE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
-}
-
-/**
-  * @brief  Enable Parity Error Interrupt
-  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
-  * @brief  Enable LIN Break Detection Interrupt
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
-  * @brief  Enable Error Interrupt
-  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
-  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
-  *           0: Interrupt is inhibited
-  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
-  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
-  * @brief  Enable CTS Interrupt
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
-  * @brief  Disable IDLE Interrupt
-  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
-}
-
-/**
-  * @brief  Disable RX Not Empty Interrupt
-  * @rmtoll CR1          RXNEIE        LL_USART_DisableIT_RXNE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
-}
-
-/**
-  * @brief  Disable Transmission Complete Interrupt
-  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
-}
-
-/**
-  * @brief  Disable TX Empty Interrupt
-  * @rmtoll CR1          TXEIE         LL_USART_DisableIT_TXE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
-}
-
-/**
-  * @brief  Disable Parity Error Interrupt
-  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
-}
-
-/**
-  * @brief  Disable LIN Break Detection Interrupt
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
-}
-
-/**
-  * @brief  Disable Error Interrupt
-  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
-  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
-  *           0: Interrupt is inhibited
-  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
-  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
-}
-
-/**
-  * @brief  Disable CTS Interrupt
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
-}
-
-/**
-  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
-  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
-}
-
-/**
-  * @brief  Check if the USART RX Not Empty Interrupt is enabled or disabled.
-  * @rmtoll CR1          RXNEIE        LL_USART_IsEnabledIT_RXNE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
-}
-
-/**
-  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
-  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
-}
-
-/**
-  * @brief  Check if the USART TX Empty Interrupt is enabled or disabled.
-  * @rmtoll CR1          TXEIE         LL_USART_IsEnabledIT_TXE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
-}
-
-/**
-  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
-  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
-}
-
-/**
-  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
-  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
-  *         LIN feature is supported by the USARTx instance.
-  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
-}
-
-/**
-  * @brief  Check if the USART Error Interrupt is enabled or disabled.
-  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
-}
-
-/**
-  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
-  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
-  *         Hardware Flow control feature is supported by the USARTx instance.
-  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_DMA_Management DMA_Management
-  * @{
-  */
-
-/**
-  * @brief  Enable DMA Mode for reception
-  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
-  * @brief  Disable DMA Mode for reception
-  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
-}
-
-/**
-  * @brief  Check if DMA Mode is enabled for reception
-  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
-}
-
-/**
-  * @brief  Enable DMA Mode for transmission
-  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
-{
-  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
-  * @brief  Disable DMA Mode for transmission
-  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
-{
-  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
-}
-
-/**
-  * @brief  Check if DMA Mode is enabled for transmission
-  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
-  * @param  USARTx USART Instance
-  * @retval State of bit (1 or 0).
-  */
-__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
-{
-  return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
-}
-
-/**
-  * @brief  Get the data register address used for DMA transfer
-  * @rmtoll DR           DR            LL_USART_DMA_GetRegAddr
-  * @note   Address of Data Register is valid for both Transmit and Receive transfers.
-  * @param  USARTx USART Instance
-  * @retval Address of data register
-  */
-__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)
-{
-  /* return address of DR register */
-  return ((uint32_t) &(USARTx->DR));
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Data_Management Data_Management
-  * @{
-  */
-
-/**
-  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
-  * @rmtoll DR           DR            LL_USART_ReceiveData8
-  * @param  USARTx USART Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
-  */
-__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
-{
-  return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR));
-}
-
-/**
-  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
-  * @rmtoll DR           DR            LL_USART_ReceiveData9
-  * @param  USARTx USART Instance
-  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
-  */
-__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
-{
-  return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR));
-}
-
-/**
-  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
-  * @rmtoll DR           DR            LL_USART_TransmitData8
-  * @param  USARTx USART Instance
-  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
-{
-  USARTx->DR = Value;
-}
-
-/**
-  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
-  * @rmtoll DR           DR            LL_USART_TransmitData9
-  * @param  USARTx USART Instance
-  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
-{
-  USARTx->DR = Value & 0x1FFU;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_LL_EF_Execution Execution
-  * @{
-  */
-
-/**
-  * @brief  Request Break sending
-  * @rmtoll CR1          SBK           LL_USART_RequestBreakSending
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_SBK);
-}
-
-/**
-  * @brief  Put USART in Mute mode
-  * @rmtoll CR1          RWU           LL_USART_RequestEnterMuteMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
-{
-  SET_BIT(USARTx->CR1, USART_CR1_RWU);
-}
-
-/**
-  * @brief  Put USART in Active mode
-  * @rmtoll CR1          RWU           LL_USART_RequestExitMuteMode
-  * @param  USARTx USART Instance
-  * @retval None
-  */
-__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx)
-{
-  CLEAR_BIT(USARTx->CR1, USART_CR1_RWU);
-}
-
-/**
-  * @}
-  */
-
-#if defined(USE_FULL_LL_DRIVER)
-/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
-  * @{
-  */
-ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
-ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
-void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
-ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
-/**
-  * @}
-  */
-#endif /* USE_FULL_LL_DRIVER */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_LL_USART_H */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_usart.h
+  * @author  MCD Application Team
+  * @brief   Header file of USART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_USART_H
+#define __STM32F4xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10)
+
+/** @defgroup USART_LL USART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Constants USART Private Constants
+  * @{
+  */
+
+/* Defines used for the bit position in the register and perform offsets*/
+#define USART_POSITION_GTPR_GT                  USART_GTPR_GT_Pos
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL USART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/
+
+  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
+                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+  * @brief LL USART Clock Init Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+                                           USART HW configuration can be modified afterwards using unitary functions
+                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().
+                                           For more details, refer to description of this function. */
+
+  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().
+                                           For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+  * @{
+  */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_ReadReg function
+  * @{
+  */
+#define LL_USART_SR_PE                          USART_SR_PE                   /*!< Parity error flag */
+#define LL_USART_SR_FE                          USART_SR_FE                   /*!< Framing error flag */
+#define LL_USART_SR_NE                          USART_SR_NE                   /*!< Noise detected flag */
+#define LL_USART_SR_ORE                         USART_SR_ORE                  /*!< Overrun error flag */
+#define LL_USART_SR_IDLE                        USART_SR_IDLE                 /*!< Idle line detected flag */
+#define LL_USART_SR_RXNE                        USART_SR_RXNE                 /*!< Read data register not empty flag */
+#define LL_USART_SR_TC                          USART_SR_TC                   /*!< Transmission complete flag */
+#define LL_USART_SR_TXE                         USART_SR_TXE                  /*!< Transmit data register empty flag */
+#define LL_USART_SR_LBD                         USART_SR_LBD                  /*!< LIN break detection flag */
+#define LL_USART_SR_CTS                         USART_SR_CTS                  /*!< CTS flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
+  * @{
+  */
+#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE                     USART_CR1_RXNEIE              /*!< Read data register not empty interrupt enable */
+#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE                      USART_CR1_TXEIE               /*!< Transmit data register empty interrupt enable */
+#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
+#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+  * @{
+  */
+#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B                   USART_CR1_M             /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+  * @{
+  */
+#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+  * @{
+  */
+
+#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+  * @{
+  */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+  * @{
+  */
+#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+  * @{
+  */
+#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+  * @{
+  */
+#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+  * @{
+  */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+  * @{
+  */
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+  */
+#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__)      ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(2*((uint64_t)(__BAUDRATE__)))))
+#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)      (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)
+#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)      ((((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8)\
+                                                                         + 50) / 100)
+/* UART BRR = mantissa + overflow + fraction
+            = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__)             (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
+                                                                            ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \
+                                                                           (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07))
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+  */
+#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__)     ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(4*((uint64_t)(__BAUDRATE__)))))
+#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)     (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
+#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)     ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16)\
+                                                                         + 50) / 100)
+/* USART BRR = mantissa + overflow + fraction
+            = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__)            (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
+                                                                            (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \
+                                                                           (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  USART Enable
+  * @rmtoll CR1          UE            LL_USART_Enable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  USART Disable (all USART prescalers and outputs are disabled)
+  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the USART is kept, but all the status
+  *         flags, in the USARTx_SR are set to their default values.
+  * @rmtoll CR1          UE            LL_USART_Disable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if USART is enabled
+  * @rmtoll CR1          UE            LL_USART_IsEnabled
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
+  *         CR1          TE            LL_USART_SetTransferDirection
+  * @param  USARTx USART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
+  *         CR1          TE            LL_USART_GetTransferDirection
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_USART_SetParity\n
+  *         CR1          PCE           LL_USART_SetParity
+  * @param  USARTx USART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_USART_GetParity\n
+  *         CR1          PCE           LL_USART_GetParity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_USART_SetDataWidth
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_USART_GetDataWidth
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Set Oversampling to 8-bit or 16-bit mode
+  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
+  * @param  USARTx USART Instance
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+  * @brief  Return Oversampling mode
+  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @param  LastBitClockPulse This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+  * @brief  Retrieve Clock pulse of the last data bit output configuration
+  *         (Last bit Clock pulse output to the SCLK pin or not)
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
+  * @param  USARTx USART Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
+  * @param  USARTx USART Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
+  *         CR2          CPOL          LL_USART_ConfigClock\n
+  *         CR2          LBCL          LL_USART_ConfigClock
+  * @param  USARTx USART Instance
+  * @param  Phase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @param  LBCPOutput This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+  * @brief  Enable Clock output on SCLK pin
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Disable Clock output on SCLK pin
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Indicate if Clock output on SCLK pin is enabled
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
+  * @param  USARTx USART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
+  *         CR1          PCE           LL_USART_ConfigCharacter\n
+  *         CR1          M             LL_USART_ConfigCharacter\n
+  *         CR2          STOP          LL_USART_ConfigCharacter
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+                                              uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Set Address of the USART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @rmtoll CR2          ADD           LL_USART_SetNodeAddress
+  * @param  USARTx USART Instance
+  * @param  NodeAddress 4 bit Address of the USART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD));
+}
+
+/**
+  * @brief  Return 4 bit Address of the USART node as set in ADD field of CR2.
+  * @note   only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
+  * @param  USARTx USART Instance
+  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Disable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Indicate if One bit sampling method is enabled
+  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
+}
+
+/**
+  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
+  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
+  *         (Baud rate value != 0)
+  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
+                                          uint32_t BaudRate)
+{
+  if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
+  }
+  else
+  {
+    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
+{
+  uint32_t usartdiv = 0x0U;
+  uint32_t brrresult = 0x0U;
+
+  usartdiv = USARTx->BRR;
+
+  if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    if ((usartdiv & 0xFFF7U) != 0U)
+    {
+      usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+      brrresult = (PeriphClk * 2U) / usartdiv;
+    }
+  }
+  else
+  {
+    if ((usartdiv & 0xFFFFU) != 0U)
+    {
+      brrresult = PeriphClk / usartdiv;
+    }
+  }
+  return (brrresult);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+  * @{
+  */
+
+/**
+  * @brief  Enable IrDA mode
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_EnableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Disable IrDA mode
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_DisableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Indicate if IrDA mode is enabled
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
+}
+
+/**
+  * @brief  Configure IrDA Power Mode (Normal or Low Power)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_IRDA_POWER_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+  * @brief  Set Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+}
+
+/**
+  * @brief  Return Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Smartcard NACK transmission
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Disable Smartcard NACK transmission
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Indicate if Smartcard NACK transmission is enabled
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
+}
+
+/**
+  * @brief  Enable Smartcard mode
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Disable Smartcard mode
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Indicate if Smartcard mode is enabled
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
+}
+
+/**
+  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
+}
+
+/**
+  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);
+}
+
+/**
+  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+  * @{
+  */
+
+/**
+  * @brief  Set LIN Break Detection Length
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @param  LINBDLength This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+  * @brief  Return LIN Break Detection Length
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+  * @brief  Enable LIN mode
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Disable LIN mode
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Indicate if LIN mode is enabled
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+  * @{
+  */
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+  * @note   In UART mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Asynchronous Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
+  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+  /* In Asynchronous mode, the following bits must be kept cleared:
+  - LINEN, CLKEN bits in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
+  * @note   In Synchronous mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the USART in Synchronous mode.
+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  * @note   Other remaining configurations items related to Synchronous Mode
+  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
+  *         CR3          IREN          LL_USART_ConfigSyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+  /* In Synchronous mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+  /* set the UART/USART in Synchronous mode */
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
+  * @note   In LIN mode, the following bits must be kept cleared:
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also set the UART/USART in LIN mode.
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+  * @note   Other remaining configurations items related to LIN Mode
+  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
+  *         CR2          STOP          LL_USART_ConfigLINMode\n
+  *         CR2          LINEN         LL_USART_ConfigLINMode\n
+  *         CR3          IREN          LL_USART_ConfigLINMode\n
+  *         CR3          SCEN          LL_USART_ConfigLINMode\n
+  *         CR3          HDSEL         LL_USART_ConfigLINMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+  /* In LIN mode, the following bits must be kept cleared:
+  - STOP and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* Set the UART/USART in LIN mode */
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
+  * @note   In Half Duplex mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *         This function also sets the UART/USART in Half Duplex mode.
+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+  * @note   Other remaining configurations items related to Half Duplex Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+  /* In Half Duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+  /* set the UART/USART in Half Duplex mode */
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
+  * @note   In Smartcard mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also configures Stop bits to 1.5 bits and
+  *         sets the USART in Smartcard mode (SCEN bit).
+  *         Clock Output is also enabled (CLKEN).
+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+  * @note   Other remaining configurations items related to Smartcard Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
+  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
+  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+  /* In Smartcard mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - IREN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+  /* Configure Stop bits to 1.5 bits */
+  /* Synchronous mode is activated by default */
+  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+  /* set the UART/USART in Smartcard mode */
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
+  * @note   In IRDA mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the UART/USART in IRDA mode (IREN bit).
+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+  * @note   Other remaining configurations items related to Irda Mode
+  *         (as Baud Rate, Word length, Power mode, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
+  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
+  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
+  *         CR3          IREN          LL_USART_ConfigIrdaMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+  /* In IRDA mode, the following bits must be kept cleared:
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* set the UART/USART in IRDA mode */
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
+  *         (several USARTs connected in a network, one of the USARTs can be the master,
+  *         its TX output connected to the RX inputs of the other slaves USARTs).
+  * @note   In MultiProcessor mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Multi processor Mode
+  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
+  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+  /* In Multi Processor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the USART Parity Error Flag is set or not
+  * @rmtoll SR           PE            LL_USART_IsActiveFlag_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE));
+}
+
+/**
+  * @brief  Check if the USART Framing Error Flag is set or not
+  * @rmtoll SR           FE            LL_USART_IsActiveFlag_FE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE));
+}
+
+/**
+  * @brief  Check if the USART Noise error detected Flag is set or not
+  * @rmtoll SR           NF            LL_USART_IsActiveFlag_NE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE));
+}
+
+/**
+  * @brief  Check if the USART OverRun Error Flag is set or not
+  * @rmtoll SR           ORE           LL_USART_IsActiveFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE));
+}
+
+/**
+  * @brief  Check if the USART IDLE line detected Flag is set or not
+  * @rmtoll SR           IDLE          LL_USART_IsActiveFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE));
+}
+
+/**
+  * @brief  Check if the USART Read Data Register Not Empty Flag is set or not
+  * @rmtoll SR           RXNE          LL_USART_IsActiveFlag_RXNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE));
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Flag is set or not
+  * @rmtoll SR           TC            LL_USART_IsActiveFlag_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC));
+}
+
+/**
+  * @brief  Check if the USART Transmit Data Register Empty Flag is set or not
+  * @rmtoll SR           TXE           LL_USART_IsActiveFlag_TXE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE));
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Flag is set or not
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll SR           LBD           LL_USART_IsActiveFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD));
+}
+
+/**
+  * @brief  Check if the USART CTS Flag is set or not
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll SR           CTS           LL_USART_IsActiveFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS));
+}
+
+/**
+  * @brief  Check if the USART Send Break Flag is set or not
+  * @rmtoll CR1          SBK           LL_USART_IsActiveFlag_SBK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK));
+}
+
+/**
+  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll CR1          RWU           LL_USART_IsActiveFlag_RWU
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU));
+}
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @note   Clearing this flag is done by a read access to the USARTx_SR
+  *         register followed by a read access to the USARTx_DR register.
+  * @note   Please also consider that when clearing this flag, other flags as
+  *         NE, FE, ORE, IDLE would also be cleared.
+  * @rmtoll SR           PE            LL_USART_ClearFlag_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = USARTx->SR;
+  (void) tmpreg;
+  tmpreg = USARTx->DR;
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @note   Clearing this flag is done by a read access to the USARTx_SR
+  *         register followed by a read access to the USARTx_DR register.
+  * @note   Please also consider that when clearing this flag, other flags as
+  *         PE, NE, ORE, IDLE would also be cleared.
+  * @rmtoll SR           FE            LL_USART_ClearFlag_FE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = USARTx->SR;
+  (void) tmpreg;
+  tmpreg = USARTx->DR;
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear Noise detected Flag
+  * @note   Clearing this flag is done by a read access to the USARTx_SR
+  *         register followed by a read access to the USARTx_DR register.
+  * @note   Please also consider that when clearing this flag, other flags as
+  *         PE, FE, ORE, IDLE would also be cleared.
+  * @rmtoll SR           NF            LL_USART_ClearFlag_NE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = USARTx->SR;
+  (void) tmpreg;
+  tmpreg = USARTx->DR;
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @note   Clearing this flag is done by a read access to the USARTx_SR
+  *         register followed by a read access to the USARTx_DR register.
+  * @note   Please also consider that when clearing this flag, other flags as
+  *         PE, NE, FE, IDLE would also be cleared.
+  * @rmtoll SR           ORE           LL_USART_ClearFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = USARTx->SR;
+  (void) tmpreg;
+  tmpreg = USARTx->DR;
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @note   Clearing this flag is done by a read access to the USARTx_SR
+  *         register followed by a read access to the USARTx_DR register.
+  * @note   Please also consider that when clearing this flag, other flags as
+  *         PE, NE, FE, ORE would also be cleared.
+  * @rmtoll SR           IDLE          LL_USART_ClearFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+  __IO uint32_t tmpreg;
+  tmpreg = USARTx->SR;
+  (void) tmpreg;
+  tmpreg = USARTx->DR;
+  (void) tmpreg;
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll SR           TC            LL_USART_ClearFlag_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->SR, ~(USART_SR_TC));
+}
+
+/**
+  * @brief  Clear RX Not Empty Flag
+  * @rmtoll SR           RXNE          LL_USART_ClearFlag_RXNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->SR, ~(USART_SR_RXNE));
+}
+
+/**
+  * @brief  Clear LIN Break Detection Flag
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll SR           LBD           LL_USART_ClearFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->SR, ~(USART_SR_LBD));
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll SR           CTS           LL_USART_ClearFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->SR, ~(USART_SR_CTS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+  * @brief  Enable RX Not Empty Interrupt
+  * @rmtoll CR1          RXNEIE        LL_USART_EnableIT_RXNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+  * @brief  Enable TX Empty Interrupt
+  * @rmtoll CR1          TXEIE         LL_USART_EnableIT_TXE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable LIN Break Detection Interrupt
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
+  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+/**
+  * @brief  Disable RX Not Empty Interrupt
+  * @rmtoll CR1          RXNEIE        LL_USART_DisableIT_RXNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+/**
+  * @brief  Disable TX Empty Interrupt
+  * @rmtoll CR1          TXEIE         LL_USART_DisableIT_TXE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable LIN Break Detection Interrupt
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register.
+  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
+}
+
+/**
+  * @brief  Check if the USART RX Not Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1          RXNEIE        LL_USART_IsEnabledIT_RXNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
+}
+
+/**
+  * @brief  Check if the USART TX Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1          TXEIE         LL_USART_IsEnabledIT_TXE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
+}
+
+/**
+  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
+}
+
+/**
+  * @brief  Check if the USART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
+}
+
+/**
+  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
+{
+  return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll DR           DR            LL_USART_DMA_GetRegAddr
+  * @note   Address of Data Register is valid for both Transmit and Receive transfers.
+  * @param  USARTx USART Instance
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx)
+{
+  /* return address of DR register */
+  return ((uint32_t) &(USARTx->DR));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll DR           DR            LL_USART_ReceiveData8
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
+{
+  return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR));
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll DR           DR            LL_USART_ReceiveData9
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
+{
+  return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll DR           DR            LL_USART_TransmitData8
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+  USARTx->DR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll DR           DR            LL_USART_TransmitData9
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+  USARTx->DR = Value & 0x1FFU;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll CR1          SBK           LL_USART_RequestBreakSending
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_SBK);
+}
+
+/**
+  * @brief  Put USART in Mute mode
+  * @rmtoll CR1          RWU           LL_USART_RequestEnterMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_RWU);
+}
+
+/**
+  * @brief  Put USART in Active mode
+  * @rmtoll CR1          RWU           LL_USART_RequestExitMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_RWU);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
+void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_USART_H */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h
index 2b254a1..8b6cdfe 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h
+++ b/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_utils.h
@@ -1,307 +1,307 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_ll_utils.h
-  * @author  MCD Application Team
-  * @brief   Header file of UTILS LL module.
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The LL UTILS driver contains a set of generic APIs that can be
-    used by user:
-      (+) Device electronic signature
-      (+) Timing functions
-      (+) PLL configuration functions
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_LL_UTILS_H
-#define __STM32F4xx_LL_UTILS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/** @addtogroup STM32F4xx_LL_Driver
-  * @{
-  */
-
-/** @defgroup UTILS_LL UTILS
-  * @{
-  */
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
-  * @{
-  */
-
-/* Max delay can be used in LL_mDelay */
-#define LL_MAX_DELAY                  0xFFFFFFFFU
-
-/**
- * @brief Unique device ID register base address
- */
-#define UID_BASE_ADDRESS              UID_BASE
-
-/**
- * @brief Flash size data register base address
- */
-#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
-
-/**
- * @brief Package data register base address
- */
-#define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
-  * @{
-  */
-/**
-  * @}
-  */
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
-  * @{
-  */
-/**
-  * @brief  UTILS PLL structure definition
-  */
-typedef struct
-{
-  uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
-                        This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
-
-                        This feature can be modified afterwards using unitary function
-                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-
-  uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
-                        This parameter must be a number between Min_Data = @ref RCC_PLLN_MIN_VALUE
-                        and Max_Data = @ref RCC_PLLN_MIN_VALUE
-
-                        This feature can be modified afterwards using unitary function
-                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-
-  uint32_t PLLP;   /*!< Division for the main system clock.
-                        This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV
-
-                        This feature can be modified afterwards using unitary function
-                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
-} LL_UTILS_PLLInitTypeDef;
-
-/**
-  * @brief  UTILS System, AHB and APB buses clock configuration structure definition
-  */
-typedef struct
-{
-  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
-
-                                       This feature can be modified afterwards using unitary function
-                                       @ref LL_RCC_SetAHBPrescaler(). */
-
-  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
-
-                                       This feature can be modified afterwards using unitary function
-                                       @ref LL_RCC_SetAPB1Prescaler(). */
-
-  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
-
-                                       This feature can be modified afterwards using unitary function
-                                       @ref LL_RCC_SetAPB2Prescaler(). */
-
-} LL_UTILS_ClkInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
-  * @{
-  */
-
-/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
-  * @{
-  */
-#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
-#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
-/**
-  * @}
-  */
-
-/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
-  * @{
-  */
-#define LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64                        0x00000000U /*!< WLCSP36 or UFQFPN48 or LQFP64 package type                         */
-#define LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48       0x00000100U /*!< WLCSP168 or FBGA169 or LQFP100 or LQFP64 or UFQFPN48 package type  */
-#define LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176               0x00000200U /*!< WLCSP64 or WLCSP81 or LQFP176 or UFBGA176 package type             */
-#define LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100             0x00000300U /*!< LQFP144 or UFBGA144 or UFBGA144 or UFBGA100 package type           */
-#define LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216                       0x00000400U /*!< LQFP100 or LQFP208 or TFBGA216 package type                        */
-#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216                               0x00000500U /*!< LQFP208 or TFBGA216 package type                                   */
-#define LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144                        0x00000700U /*!< TQFP64 or UFBGA144 or LQFP144 package type                         */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
-  * @{
-  */
-
-/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
-  * @{
-  */
-
-/**
-  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
-  * @retval UID[31:0]
-  */
-__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
-}
-
-/**
-  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
-  * @retval UID[63:32]
-  */
-__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
-}
-
-/**
-  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
-  * @retval UID[95:64]
-  */
-__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
-}
-
-/**
-  * @brief  Get Flash memory size
-  * @note   This bitfield indicates the size of the device Flash memory expressed in
-  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
-  * @retval FLASH_SIZE[15:0]: Flash memory size
-  */
-__STATIC_INLINE uint32_t LL_GetFlashSize(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF);
-}
-
-/**
-  * @brief  Get Package type
-  * @retval Returned value can be one of the following values:
-  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 (*)
-  *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 (*)
-  * 
-  *         (*) value not defined in all devices.
-  */
-__STATIC_INLINE uint32_t LL_GetPackageType(void)
-{
-  return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UTILS_LL_EF_DELAY DELAY
-  * @{
-  */
-
-/**
-  * @brief  This function configures the Cortex-M SysTick source of the time base.
-  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
-  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
-  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
-  * @param  Ticks Number of ticks
-  * @retval None
-  */
-__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
-{
-  /* Configure the SysTick to have interrupt in 1ms time base */
-  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
-  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
-                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
-}
-
-void        LL_Init1msTick(uint32_t HCLKFrequency);
-void        LL_mDelay(uint32_t Delay);
-
-/**
-  * @}
-  */
-
-/** @defgroup UTILS_EF_SYSTEM SYSTEM
-  * @{
-  */
-
-void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
-ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
-ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
-                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
-                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F4xx_LL_UTILS_H */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_ll_utils.h
+  * @author  MCD Application Team
+  * @brief   Header file of UTILS LL module.
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The LL UTILS driver contains a set of generic APIs that can be
+    used by user:
+      (+) Device electronic signature
+      (+) Timing functions
+      (+) PLL configuration functions
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_LL_UTILS_H
+#define __STM32F4xx_LL_UTILS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_LL_Driver
+  * @{
+  */
+
+/** @defgroup UTILS_LL UTILS
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
+  * @{
+  */
+
+/* Max delay can be used in LL_mDelay */
+#define LL_MAX_DELAY                  0xFFFFFFFFU
+
+/**
+ * @brief Unique device ID register base address
+ */
+#define UID_BASE_ADDRESS              UID_BASE
+
+/**
+ * @brief Flash size data register base address
+ */
+#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE
+
+/**
+ * @brief Package data register base address
+ */
+#define PACKAGE_BASE_ADDRESS          PACKAGE_BASE
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
+  * @{
+  */
+/**
+  * @brief  UTILS PLL structure definition
+  */
+typedef struct
+{
+  uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.
+                        This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+  uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.
+                        This parameter must be a number between Min_Data = @ref RCC_PLLN_MIN_VALUE
+                        and Max_Data = @ref RCC_PLLN_MIN_VALUE
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+
+  uint32_t PLLP;   /*!< Division for the main system clock.
+                        This parameter can be a value of @ref RCC_LL_EC_PLLP_DIV
+
+                        This feature can be modified afterwards using unitary function
+                        @ref LL_RCC_PLL_ConfigDomain_SYS(). */
+} LL_UTILS_PLLInitTypeDef;
+
+/**
+  * @brief  UTILS System, AHB and APB buses clock configuration structure definition
+  */
+typedef struct
+{
+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAHBPrescaler(). */
+
+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB1Prescaler(). */
+
+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
+                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
+
+                                       This feature can be modified afterwards using unitary function
+                                       @ref LL_RCC_SetAPB2Prescaler(). */
+
+} LL_UTILS_ClkInitTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
+  * @{
+  */
+
+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
+  * @{
+  */
+#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */
+#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
+  * @{
+  */
+#define LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64                        0x00000000U /*!< WLCSP36 or UFQFPN48 or LQFP64 package type                         */
+#define LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48       0x00000100U /*!< WLCSP168 or FBGA169 or LQFP100 or LQFP64 or UFQFPN48 package type  */
+#define LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176               0x00000200U /*!< WLCSP64 or WLCSP81 or LQFP176 or UFBGA176 package type             */
+#define LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100             0x00000300U /*!< LQFP144 or UFBGA144 or UFBGA144 or UFBGA100 package type           */
+#define LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216                       0x00000400U /*!< LQFP100 or LQFP208 or TFBGA216 package type                        */
+#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216                               0x00000500U /*!< LQFP208 or TFBGA216 package type                                   */
+#define LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144                        0x00000700U /*!< TQFP64 or UFBGA144 or LQFP144 package type                         */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
+  * @{
+  */
+
+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
+  * @{
+  */
+
+/**
+  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[31:0]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
+}
+
+/**
+  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[63:32]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
+}
+
+/**
+  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)
+  * @retval UID[95:64]
+  */
+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
+}
+
+/**
+  * @brief  Get Flash memory size
+  * @note   This bitfield indicates the size of the device Flash memory expressed in
+  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
+  * @retval FLASH_SIZE[15:0]: Flash memory size
+  */
+__STATIC_INLINE uint32_t LL_GetFlashSize(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF);
+}
+
+/**
+  * @brief  Get Package type
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP36_UFQFPN48_LQFP64 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP168_FBGA169_LQFP100_LQFP64_UFQFPN48 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP64_WLCSP81_LQFP176_UFBGA176 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_UFBGA144_UFBGA144_UFBGA100 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_LQFP208_TFBGA216 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA216 (*)
+  *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP64_UFBGA144_LQFP144 (*)
+  * 
+  *         (*) value not defined in all devices.
+  */
+__STATIC_INLINE uint32_t LL_GetPackageType(void)
+{
+  return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_LL_EF_DELAY DELAY
+  * @{
+  */
+
+/**
+  * @brief  This function configures the Cortex-M SysTick source of the time base.
+  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
+  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick
+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.
+  * @param  Ticks Number of ticks
+  * @retval None
+  */
+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
+{
+  /* Configure the SysTick to have interrupt in 1ms time base */
+  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */
+  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */
+}
+
+void        LL_Init1msTick(uint32_t HCLKFrequency);
+void        LL_mDelay(uint32_t Delay);
+
+/**
+  * @}
+  */
+
+/** @defgroup UTILS_EF_SYSTEM SYSTEM
+  * @{
+  */
+
+void        LL_SetSystemCoreClock(uint32_t HCLKFrequency);
+ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
+                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_LL_UTILS_H */
diff --git a/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt b/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt
index 3edc4d1..b40364c 100644
--- a/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt
+++ b/Drivers/STM32F4xx_HAL_Driver/LICENSE.txt
@@ -1,6 +1,6 @@
-This software component is provided to you as part of a software package and
-applicable license terms are in the  Package_license file. If you received this
-software component outside of a package or without applicable license terms,
-the terms of the BSD-3-Clause license shall apply. 
-You may obtain a copy of the BSD-3-Clause at:
-https://opensource.org/licenses/BSD-3-Clause
+This software component is provided to you as part of a software package and
+applicable license terms are in the  Package_license file. If you received this
+software component outside of a package or without applicable license terms,
+the terms of the BSD-3-Clause license shall apply. 
+You may obtain a copy of the BSD-3-Clause at:
+https://opensource.org/licenses/BSD-3-Clause
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c
index 9ba2ba7..9977a70 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c
@@ -1,615 +1,615 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal.c
-  * @author  MCD Application Team
-  * @brief   HAL module driver.
-  *          This is the common part of the HAL initialization
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The common HAL driver contains a set of generic and common APIs that can be
-    used by the PPP peripheral drivers and the user to start using the HAL. 
-    [..]
-    The HAL contains two APIs' categories: 
-         (+) Common HAL APIs
-         (+) Services HAL APIs
-
-  @endverbatim
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup HAL HAL
-  * @brief HAL module driver.
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup HAL_Private_Constants
-  * @{
-  */
-/**
-  * @brief STM32F4xx HAL Driver version number V1.8.1
-  */
-#define __STM32F4xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
-#define __STM32F4xx_HAL_VERSION_SUB1   (0x08U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_HAL_VERSION_SUB2   (0x01U) /*!< [15:8]  sub2 version */
-#define __STM32F4xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */ 
-#define __STM32F4xx_HAL_VERSION         ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
-                                        |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
-                                        |(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\
-                                        |(__STM32F4xx_HAL_VERSION_RC))
-                                        
-#define IDCODE_DEVID_MASK    0x00000FFFU
-
-/* ------------ RCC registers bit address in the alias region ----------- */
-#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
-/* ---  MEMRMP Register ---*/ 
-/* Alias word address of UFB_MODE bit */ 
-#define MEMRMP_OFFSET             SYSCFG_OFFSET 
-#define UFB_MODE_BIT_NUMBER       SYSCFG_MEMRMP_UFB_MODE_Pos
-#define UFB_MODE_BB               (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U)) 
-
-/* ---  CMPCR Register ---*/ 
-/* Alias word address of CMP_PD bit */ 
-#define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20U) 
-#define CMP_PD_BIT_NUMBER         SYSCFG_CMPCR_CMP_PD_Pos
-#define CMPCR_CMP_PD_BB           (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U))
-
-/* ---  MCHDLYCR Register ---*/ 
-/* Alias word address of BSCKSEL bit */ 
-#define MCHDLYCR_OFFSET            (SYSCFG_OFFSET + 0x30U) 
-#define BSCKSEL_BIT_NUMBER         SYSCFG_MCHDLYCR_BSCKSEL_Pos
-#define MCHDLYCR_BSCKSEL_BB        (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32U) + (BSCKSEL_BIT_NUMBER * 4U))
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup HAL_Private_Variables
-  * @{
-  */
-__IO uint32_t uwTick;
-uint32_t uwTickPrio   = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
-HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
-/**
-  * @}
-  */
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Functions HAL Exported Functions
-  * @{
-  */
-
-/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions 
- *  @brief    Initialization and de-initialization functions
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initializes the Flash interface the NVIC allocation and initial clock 
-          configuration. It initializes the systick also when timeout is needed 
-          and the backup domain when enabled.
-      (+) De-Initializes common part of the HAL.
-      (+) Configure the time base source to have 1ms time base with a dedicated 
-          Tick interrupt priority. 
-        (++) SysTick timer is used by default as source of time base, but user
-             can eventually implement his proper time base source (a general purpose 
-             timer for example or other time source), keeping in mind that Time base 
-             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
-             handled in milliseconds basis.
-        (++) Time base configuration function (HAL_InitTick ()) is called automatically 
-             at the beginning of the program after reset by HAL_Init() or at any time 
-             when clock is configured, by HAL_RCC_ClockConfig(). 
-        (++) Source of time base is configured  to generate interrupts at regular 
-             time intervals. Care must be taken if HAL_Delay() is called from a 
-             peripheral ISR process, the Tick interrupt line must have higher priority 
-            (numerically lower) than the peripheral interrupt. Otherwise the caller 
-            ISR process will be blocked. 
-       (++) functions affecting time base configurations are declared as __weak  
-             to make  override possible  in case of other  implementations in user file.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  This function is used to initialize the HAL Library; it must be the first 
-  *         instruction to be executed in the main program (before to call any other
-  *         HAL function), it performs the following:
-  *           Configure the Flash prefetch, instruction and Data caches.
-  *           Configures the SysTick to generate an interrupt each 1 millisecond,
-  *           which is clocked by the HSI (at this stage, the clock is not yet
-  *           configured and thus the system is running from the internal HSI at 16 MHz).
-  *           Set NVIC Group Priority to 4.
-  *           Calls the HAL_MspInit() callback function defined in user file 
-  *           "stm32f4xx_hal_msp.c" to do the global low level hardware initialization 
-  *            
-  * @note   SysTick is used as time base for the HAL_Delay() function, the application
-  *         need to ensure that the SysTick time base is always set to 1 millisecond
-  *         to have correct HAL operation.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_Init(void)
-{
-  /* Configure Flash prefetch, Instruction cache, Data cache */ 
-#if (INSTRUCTION_CACHE_ENABLE != 0U)
-  __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
-#endif /* INSTRUCTION_CACHE_ENABLE */
-
-#if (DATA_CACHE_ENABLE != 0U)
-  __HAL_FLASH_DATA_CACHE_ENABLE();
-#endif /* DATA_CACHE_ENABLE */
-
-#if (PREFETCH_ENABLE != 0U)
-  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif /* PREFETCH_ENABLE */
-
-  /* Set Interrupt Group Priority */
-  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
-  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
-  HAL_InitTick(TICK_INT_PRIORITY);
-
-  /* Init the low level hardware */
-  HAL_MspInit();
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function de-Initializes common part of the HAL and stops the systick.
-  *         This function is optional.   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DeInit(void)
-{
-  /* Reset of all peripherals */
-  __HAL_RCC_APB1_FORCE_RESET();
-  __HAL_RCC_APB1_RELEASE_RESET();
-
-  __HAL_RCC_APB2_FORCE_RESET();
-  __HAL_RCC_APB2_RELEASE_RESET();
-
-  __HAL_RCC_AHB1_FORCE_RESET();
-  __HAL_RCC_AHB1_RELEASE_RESET();
-
-  __HAL_RCC_AHB2_FORCE_RESET();
-  __HAL_RCC_AHB2_RELEASE_RESET();
-
-  __HAL_RCC_AHB3_FORCE_RESET();
-  __HAL_RCC_AHB3_RELEASE_RESET();
-
-  /* De-Init the low level hardware */
-  HAL_MspDeInit();
-    
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initialize the MSP.
-  * @retval None
-  */
-__weak void HAL_MspInit(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes the MSP.
-  * @retval None
-  */
-__weak void HAL_MspDeInit(void)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief This function configures the source of the time base.
-  *        The time source is configured  to have 1ms time base with a dedicated 
-  *        Tick interrupt priority.
-  * @note This function is called  automatically at the beginning of program after
-  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
-  * @note In the default implementation, SysTick timer is the source of time base. 
-  *       It is used to generate interrupts at regular time intervals. 
-  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process, 
-  *       The SysTick interrupt must have higher priority (numerically lower)
-  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
-  *       The function is declared as __weak  to be overwritten  in case of other
-  *       implementation  in user file.
-  * @param TickPriority Tick interrupt priority.
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
-  /* Configure the SysTick to have interrupt in 1ms time basis*/
-  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Configure the SysTick IRQ priority */
-  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
-  {
-    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
-    uwTickPrio = TickPriority;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions 
- *  @brief    HAL Control functions
- *
-@verbatim
- ===============================================================================
-                      ##### HAL Control functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Provide a tick value in millisecond
-      (+) Provide a blocking delay in millisecond
-      (+) Suspend the time base source interrupt
-      (+) Resume the time base source interrupt
-      (+) Get the HAL API driver version
-      (+) Get the device identifier
-      (+) Get the device revision identifier
-      (+) Enable/Disable Debug module during SLEEP mode
-      (+) Enable/Disable Debug module during STOP mode
-      (+) Enable/Disable Debug module during STANDBY mode
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief This function is called to increment  a global variable "uwTick"
-  *        used as application time base.
-  * @note In the default implementation, this variable is incremented each 1ms
-  *       in SysTick ISR.
- * @note This function is declared as __weak to be overwritten in case of other 
-  *      implementations in user file.
-  * @retval None
-  */
-__weak void HAL_IncTick(void)
-{
-  uwTick += uwTickFreq;
-}
-
-/**
-  * @brief Provides a tick value in millisecond.
-  * @note This function is declared as __weak to be overwritten in case of other 
-  *       implementations in user file.
-  * @retval tick value
-  */
-__weak uint32_t HAL_GetTick(void)
-{
-  return uwTick;
-}
-
-/**
-  * @brief This function returns a tick priority.
-  * @retval tick priority
-  */
-uint32_t HAL_GetTickPrio(void)
-{
-  return uwTickPrio;
-}
-
-/**
-  * @brief Set new tick Freq.
-  * @retval Status
-  */
-HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
-{
-  HAL_StatusTypeDef status  = HAL_OK;
-  HAL_TickFreqTypeDef prevTickFreq;
-
-  assert_param(IS_TICKFREQ(Freq));
-
-  if (uwTickFreq != Freq)
-  {
-    /* Back up uwTickFreq frequency */
-    prevTickFreq = uwTickFreq;
-
-    /* Update uwTickFreq global variable used by HAL_InitTick() */
-    uwTickFreq = Freq;
-
-    /* Apply the new tick Freq  */
-    status = HAL_InitTick(uwTickPrio);
-
-    if (status != HAL_OK)
-    {
-      /* Restore previous tick frequency */
-      uwTickFreq = prevTickFreq;
-    }
-  }
-
-  return status;
-}
-
-/**
-  * @brief Return tick frequency.
-  * @retval tick period in Hz
-  */
-HAL_TickFreqTypeDef HAL_GetTickFreq(void)
-{
-  return uwTickFreq;
-}
-
-/**
-  * @brief This function provides minimum delay (in milliseconds) based 
-  *        on variable incremented.
-  * @note In the default implementation , SysTick timer is the source of time base.
-  *       It is used to generate interrupts at regular time intervals where uwTick
-  *       is incremented.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @param Delay specifies the delay time length, in milliseconds.
-  * @retval None
-  */
-__weak void HAL_Delay(uint32_t Delay)
-{
-  uint32_t tickstart = HAL_GetTick();
-  uint32_t wait = Delay;
-
-  /* Add a freq to guarantee minimum wait */
-  if (wait < HAL_MAX_DELAY)
-  {
-    wait += (uint32_t)(uwTickFreq);
-  }
-
-  while((HAL_GetTick() - tickstart) < wait)
-  {
-  }
-}
-
-/**
-  * @brief Suspend Tick increment.
-  * @note In the default implementation , SysTick timer is the source of time base. It is
-  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
-  *       is called, the SysTick interrupt will be disabled and so Tick increment 
-  *       is suspended.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval None
-  */
-__weak void HAL_SuspendTick(void)
-{
-  /* Disable SysTick Interrupt */
-  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
-  * @brief Resume Tick increment.
-  * @note In the default implementation , SysTick timer is the source of time base. It is
-  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
-  *       is called, the SysTick interrupt will be enabled and so Tick increment 
-  *       is resumed.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval None
-  */
-__weak void HAL_ResumeTick(void)
-{
-  /* Enable SysTick Interrupt */
-  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
-}
-
-/**
-  * @brief  Returns the HAL revision
-  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
-  */
-uint32_t HAL_GetHalVersion(void)
-{
-  return __STM32F4xx_HAL_VERSION;
-}
-
-/**
-  * @brief  Returns the device revision identifier.
-  * @retval Device revision identifier
-  */
-uint32_t HAL_GetREVID(void)
-{
-  return((DBGMCU->IDCODE) >> 16U);
-}
-
-/**
-  * @brief  Returns the device identifier.
-  * @retval Device identifier
-  */
-uint32_t HAL_GetDEVID(void)
-{
-  return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
-}
-
-/**
-  * @brief  Enable the Debug Module during SLEEP mode
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGSleepMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Disable the Debug Module during SLEEP mode
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGSleepMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STOP mode
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGStopMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Disable the Debug Module during STOP mode
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGStopMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STANDBY mode
-  * @retval None
-  */
-void HAL_DBGMCU_EnableDBGStandbyMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Disable the Debug Module during STANDBY mode
-  * @retval None
-  */
-void HAL_DBGMCU_DisableDBGStandbyMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Enables the I/O Compensation Cell.
-  * @note   The I/O compensation cell can be used only when the device supply
-  *         voltage ranges from 2.4 to 3.6 V.  
-  * @retval None
-  */
-void HAL_EnableCompensationCell(void)
-{
-  *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Power-down the I/O Compensation Cell.
-  * @note   The I/O compensation cell can be used only when the device supply
-  *         voltage ranges from 2.4 to 3.6 V.  
-  * @retval None
-  */
-void HAL_DisableCompensationCell(void)
-{
-  *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief  Returns first word of the unique device identifier (UID based on 96 bits)
-  * @retval Device identifier
-  */
-uint32_t HAL_GetUIDw0(void)
-{
-  return (READ_REG(*((uint32_t *)UID_BASE)));
-}
-
-/**
-  * @brief  Returns second word of the unique device identifier (UID based on 96 bits)
-  * @retval Device identifier
-  */
-uint32_t HAL_GetUIDw1(void)
-{
-  return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
-}
-
-/**
-  * @brief  Returns third word of the unique device identifier (UID based on 96 bits)
-  * @retval Device identifier
-  */
-uint32_t HAL_GetUIDw2(void)
-{
-  return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
-}
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
-    defined(STM32F469xx) || defined(STM32F479xx)
-/**
-  * @brief  Enables the Internal FLASH Bank Swapping.
-  *   
-  * @note   This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. 
-  *
-  * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) 
-  *         and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)   
-  *
-  * @retval None
-  */
-void HAL_EnableMemorySwappingBank(void)
-{
-  *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disables the Internal FLASH Bank Swapping.
-  *   
-  * @note   This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. 
-  *
-  * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) 
-  *         and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) 
-  *           
-  * @retval None
-  */
-void HAL_DisableMemorySwappingBank(void)
-{
-  *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE;
-}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal.c
+  * @author  MCD Application Team
+  * @brief   HAL module driver.
+  *          This is the common part of the HAL initialization
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The common HAL driver contains a set of generic and common APIs that can be
+    used by the PPP peripheral drivers and the user to start using the HAL. 
+    [..]
+    The HAL contains two APIs' categories: 
+         (+) Common HAL APIs
+         (+) Services HAL APIs
+
+  @endverbatim
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL HAL
+  * @brief HAL module driver.
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup HAL_Private_Constants
+  * @{
+  */
+/**
+  * @brief STM32F4xx HAL Driver version number V1.8.1
+  */
+#define __STM32F4xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
+#define __STM32F4xx_HAL_VERSION_SUB1   (0x08U) /*!< [23:16] sub1 version */
+#define __STM32F4xx_HAL_VERSION_SUB2   (0x01U) /*!< [15:8]  sub2 version */
+#define __STM32F4xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */ 
+#define __STM32F4xx_HAL_VERSION         ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
+                                        |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
+                                        |(__STM32F4xx_HAL_VERSION_SUB2 << 8U )\
+                                        |(__STM32F4xx_HAL_VERSION_RC))
+                                        
+#define IDCODE_DEVID_MASK    0x00000FFFU
+
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
+/* ---  MEMRMP Register ---*/ 
+/* Alias word address of UFB_MODE bit */ 
+#define MEMRMP_OFFSET             SYSCFG_OFFSET 
+#define UFB_MODE_BIT_NUMBER       SYSCFG_MEMRMP_UFB_MODE_Pos
+#define UFB_MODE_BB               (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U)) 
+
+/* ---  CMPCR Register ---*/ 
+/* Alias word address of CMP_PD bit */ 
+#define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20U) 
+#define CMP_PD_BIT_NUMBER         SYSCFG_CMPCR_CMP_PD_Pos
+#define CMPCR_CMP_PD_BB           (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U))
+
+/* ---  MCHDLYCR Register ---*/ 
+/* Alias word address of BSCKSEL bit */ 
+#define MCHDLYCR_OFFSET            (SYSCFG_OFFSET + 0x30U) 
+#define BSCKSEL_BIT_NUMBER         SYSCFG_MCHDLYCR_BSCKSEL_Pos
+#define MCHDLYCR_BSCKSEL_BB        (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32U) + (BSCKSEL_BIT_NUMBER * 4U))
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup HAL_Private_Variables
+  * @{
+  */
+__IO uint32_t uwTick;
+uint32_t uwTickPrio   = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT;  /* 1KHz */
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+  * @{
+  */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions 
+ *  @brief    Initialization and de-initialization functions
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initializes the Flash interface the NVIC allocation and initial clock 
+          configuration. It initializes the systick also when timeout is needed 
+          and the backup domain when enabled.
+      (+) De-Initializes common part of the HAL.
+      (+) Configure the time base source to have 1ms time base with a dedicated 
+          Tick interrupt priority. 
+        (++) SysTick timer is used by default as source of time base, but user
+             can eventually implement his proper time base source (a general purpose 
+             timer for example or other time source), keeping in mind that Time base 
+             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
+             handled in milliseconds basis.
+        (++) Time base configuration function (HAL_InitTick ()) is called automatically 
+             at the beginning of the program after reset by HAL_Init() or at any time 
+             when clock is configured, by HAL_RCC_ClockConfig(). 
+        (++) Source of time base is configured  to generate interrupts at regular 
+             time intervals. Care must be taken if HAL_Delay() is called from a 
+             peripheral ISR process, the Tick interrupt line must have higher priority 
+            (numerically lower) than the peripheral interrupt. Otherwise the caller 
+            ISR process will be blocked. 
+       (++) functions affecting time base configurations are declared as __weak  
+             to make  override possible  in case of other  implementations in user file.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function is used to initialize the HAL Library; it must be the first 
+  *         instruction to be executed in the main program (before to call any other
+  *         HAL function), it performs the following:
+  *           Configure the Flash prefetch, instruction and Data caches.
+  *           Configures the SysTick to generate an interrupt each 1 millisecond,
+  *           which is clocked by the HSI (at this stage, the clock is not yet
+  *           configured and thus the system is running from the internal HSI at 16 MHz).
+  *           Set NVIC Group Priority to 4.
+  *           Calls the HAL_MspInit() callback function defined in user file 
+  *           "stm32f4xx_hal_msp.c" to do the global low level hardware initialization 
+  *            
+  * @note   SysTick is used as time base for the HAL_Delay() function, the application
+  *         need to ensure that the SysTick time base is always set to 1 millisecond
+  *         to have correct HAL operation.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+  /* Configure Flash prefetch, Instruction cache, Data cache */ 
+#if (INSTRUCTION_CACHE_ENABLE != 0U)
+  __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+#endif /* INSTRUCTION_CACHE_ENABLE */
+
+#if (DATA_CACHE_ENABLE != 0U)
+  __HAL_FLASH_DATA_CACHE_ENABLE();
+#endif /* DATA_CACHE_ENABLE */
+
+#if (PREFETCH_ENABLE != 0U)
+  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+  /* Set Interrupt Group Priority */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
+  HAL_InitTick(TICK_INT_PRIORITY);
+
+  /* Init the low level hardware */
+  HAL_MspInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function de-Initializes common part of the HAL and stops the systick.
+  *         This function is optional.   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+  /* Reset of all peripherals */
+  __HAL_RCC_APB1_FORCE_RESET();
+  __HAL_RCC_APB1_RELEASE_RESET();
+
+  __HAL_RCC_APB2_FORCE_RESET();
+  __HAL_RCC_APB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB1_FORCE_RESET();
+  __HAL_RCC_AHB1_RELEASE_RESET();
+
+  __HAL_RCC_AHB2_FORCE_RESET();
+  __HAL_RCC_AHB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB3_FORCE_RESET();
+  __HAL_RCC_AHB3_RELEASE_RESET();
+
+  /* De-Init the low level hardware */
+  HAL_MspDeInit();
+    
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the MSP.
+  * @retval None
+  */
+__weak void HAL_MspInit(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the MSP.
+  * @retval None
+  */
+__weak void HAL_MspDeInit(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MspDeInit could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief This function configures the source of the time base.
+  *        The time source is configured  to have 1ms time base with a dedicated 
+  *        Tick interrupt priority.
+  * @note This function is called  automatically at the beginning of program after
+  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+  * @note In the default implementation, SysTick timer is the source of time base. 
+  *       It is used to generate interrupts at regular time intervals. 
+  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process, 
+  *       The SysTick interrupt must have higher priority (numerically lower)
+  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+  *       The function is declared as __weak  to be overwritten  in case of other
+  *       implementation  in user file.
+  * @param TickPriority Tick interrupt priority.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  /* Configure the SysTick to have interrupt in 1ms time basis*/
+  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Configure the SysTick IRQ priority */
+  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+  {
+    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+    uwTickPrio = TickPriority;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions 
+ *  @brief    HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Provide a tick value in millisecond
+      (+) Provide a blocking delay in millisecond
+      (+) Suspend the time base source interrupt
+      (+) Resume the time base source interrupt
+      (+) Get the HAL API driver version
+      (+) Get the device identifier
+      (+) Get the device revision identifier
+      (+) Enable/Disable Debug module during SLEEP mode
+      (+) Enable/Disable Debug module during STOP mode
+      (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief This function is called to increment  a global variable "uwTick"
+  *        used as application time base.
+  * @note In the default implementation, this variable is incremented each 1ms
+  *       in SysTick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other 
+  *      implementations in user file.
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+  uwTick += uwTickFreq;
+}
+
+/**
+  * @brief Provides a tick value in millisecond.
+  * @note This function is declared as __weak to be overwritten in case of other 
+  *       implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+  return uwTick;
+}
+
+/**
+  * @brief This function returns a tick priority.
+  * @retval tick priority
+  */
+uint32_t HAL_GetTickPrio(void)
+{
+  return uwTickPrio;
+}
+
+/**
+  * @brief Set new tick Freq.
+  * @retval Status
+  */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+  HAL_StatusTypeDef status  = HAL_OK;
+  HAL_TickFreqTypeDef prevTickFreq;
+
+  assert_param(IS_TICKFREQ(Freq));
+
+  if (uwTickFreq != Freq)
+  {
+    /* Back up uwTickFreq frequency */
+    prevTickFreq = uwTickFreq;
+
+    /* Update uwTickFreq global variable used by HAL_InitTick() */
+    uwTickFreq = Freq;
+
+    /* Apply the new tick Freq  */
+    status = HAL_InitTick(uwTickPrio);
+
+    if (status != HAL_OK)
+    {
+      /* Restore previous tick frequency */
+      uwTickFreq = prevTickFreq;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief Return tick frequency.
+  * @retval tick period in Hz
+  */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+  return uwTickFreq;
+}
+
+/**
+  * @brief This function provides minimum delay (in milliseconds) based 
+  *        on variable incremented.
+  * @note In the default implementation , SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals where uwTick
+  *       is incremented.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @param Delay specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+__weak void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = HAL_GetTick();
+  uint32_t wait = Delay;
+
+  /* Add a freq to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+    wait += (uint32_t)(uwTickFreq);
+  }
+
+  while((HAL_GetTick() - tickstart) < wait)
+  {
+  }
+}
+
+/**
+  * @brief Suspend Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+  *       is called, the SysTick interrupt will be disabled and so Tick increment 
+  *       is suspended.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_SuspendTick(void)
+{
+  /* Disable SysTick Interrupt */
+  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief Resume Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+  *       is called, the SysTick interrupt will be enabled and so Tick increment 
+  *       is resumed.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_ResumeTick(void)
+{
+  /* Enable SysTick Interrupt */
+  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief  Returns the HAL revision
+  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+  */
+uint32_t HAL_GetHalVersion(void)
+{
+  return __STM32F4xx_HAL_VERSION;
+}
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @retval Device revision identifier
+  */
+uint32_t HAL_GetREVID(void)
+{
+  return((DBGMCU->IDCODE) >> 16U);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @retval Device identifier
+  */
+uint32_t HAL_GetDEVID(void)
+{
+  return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @brief  Enable the Debug Module during SLEEP mode
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Disable the Debug Module during SLEEP mode
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STOP mode
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Disable the Debug Module during STOP mode
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STANDBY mode
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Disable the Debug Module during STANDBY mode
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Enables the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.  
+  * @retval None
+  */
+void HAL_EnableCompensationCell(void)
+{
+  *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Power-down the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.  
+  * @retval None
+  */
+void HAL_DisableCompensationCell(void)
+{
+  *(__IO uint32_t *)CMPCR_CMP_PD_BB = (uint32_t)DISABLE;
+}
+
+/**
+  * @brief  Returns first word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw0(void)
+{
+  return (READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+  * @brief  Returns second word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw1(void)
+{
+  return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+  * @brief  Returns third word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw2(void)
+{
+  return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
+    defined(STM32F469xx) || defined(STM32F479xx)
+/**
+  * @brief  Enables the Internal FLASH Bank Swapping.
+  *   
+  * @note   This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. 
+  *
+  * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000) 
+  *         and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)   
+  *
+  * @retval None
+  */
+void HAL_EnableMemorySwappingBank(void)
+{
+  *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Disables the Internal FLASH Bank Swapping.
+  *   
+  * @note   This function can be used only for STM32F42xxx/43xxx/469xx/479xx devices. 
+  *
+  * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000) 
+  *         and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000) 
+  *           
+  * @retval None
+  */
+void HAL_DisableMemorySwappingBank(void)
+{
+  *(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE;
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c
index 4abdc60..a47bfa8 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_can.c
@@ -1,2462 +1,2462 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_can.c
-  * @author  MCD Application Team
-  * @brief   CAN HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Controller Area Network (CAN) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Configuration functions
-  *           + Control functions
-  *           + Interrupts management
-  *           + Callbacks functions
-  *           + Peripheral State and Error functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      (#) Initialize the CAN low level resources by implementing the
-          HAL_CAN_MspInit():
-         (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
-         (++) Configure CAN pins
-             (+++) Enable the clock for the CAN GPIOs
-             (+++) Configure CAN pins as alternate function open-drain
-         (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
-             (+++) Configure the CAN interrupt priority using
-                   HAL_NVIC_SetPriority()
-             (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ()
-             (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler()
-
-      (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This
-          function resorts to HAL_CAN_MspInit() for low-level initialization.
-
-      (#) Configure the reception filters using the following configuration
-          functions:
-            (++) HAL_CAN_ConfigFilter()
-
-      (#) Start the CAN module using HAL_CAN_Start() function. At this level
-          the node is active on the bus: it receive messages, and can send
-          messages.
-
-      (#) To manage messages transmission, the following Tx control functions
-          can be used:
-            (++) HAL_CAN_AddTxMessage() to request transmission of a new
-                 message.
-            (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending
-                 message.
-            (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx
-                 mailboxes.
-            (++) HAL_CAN_IsTxMessagePending() to check if a message is pending
-                 in a Tx mailbox.
-            (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message
-                 sent, if time triggered communication mode is enabled.
-
-      (#) When a message is received into the CAN Rx FIFOs, it can be retrieved
-          using the HAL_CAN_GetRxMessage() function. The function
-          HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are
-          stored in the Rx Fifo.
-
-      (#) Calling the HAL_CAN_Stop() function stops the CAN module.
-
-      (#) The deinitialization is achieved with HAL_CAN_DeInit() function.
-
-
-      *** Polling mode operation ***
-      ==============================
-    [..]
-      (#) Reception:
-            (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel()
-                 until at least one message is received.
-            (++) Then get the message using HAL_CAN_GetRxMessage().
-
-      (#) Transmission:
-            (++) Monitor the Tx mailboxes availability until at least one Tx
-                 mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel().
-            (++) Then request transmission of a message using
-                 HAL_CAN_AddTxMessage().
-
-
-      *** Interrupt mode operation ***
-      ================================
-    [..]
-      (#) Notifications are activated using HAL_CAN_ActivateNotification()
-          function. Then, the process can be controlled through the
-          available user callbacks: HAL_CAN_xxxCallback(), using same APIs
-          HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage().
-
-      (#) Notifications can be deactivated using
-          HAL_CAN_DeactivateNotification() function.
-
-      (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and
-          CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig
-          the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and
-          HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options
-          here.
-            (++) Directly get the Rx message in the callback, using
-                 HAL_CAN_GetRxMessage().
-            (++) Or deactivate the notification in the callback without
-                 getting the Rx message. The Rx message can then be got later
-                 using HAL_CAN_GetRxMessage(). Once the Rx message have been
-                 read, the notification can be activated again.
-
-
-      *** Sleep mode ***
-      ==================
-    [..]
-      (#) The CAN peripheral can be put in sleep mode (low power), using
-          HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the
-          current CAN activity (transmission or reception of a CAN frame) will
-          be completed.
-
-      (#) A notification can be activated to be informed when the sleep mode
-          will be entered.
-
-      (#) It can be checked if the sleep mode is entered using
-          HAL_CAN_IsSleepActive().
-          Note that the CAN state (accessible from the API HAL_CAN_GetState())
-          is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is
-          submitted (the sleep mode is not yet entered), and become
-          HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective.
-
-      (#) The wake-up from sleep mode can be triggered by two ways:
-            (++) Using HAL_CAN_WakeUp(). When returning from this function,
-                 the sleep mode is exited (if return status is HAL_OK).
-            (++) When a start of Rx CAN frame is detected by the CAN peripheral,
-                 if automatic wake up mode is enabled.
-
-  *** Callback registration ***
-  =============================================
-
-  The compilation define  USE_HAL_CAN_REGISTER_CALLBACKS when set to 1
-  allows the user to configure dynamically the driver callbacks.
-  Use Function HAL_CAN_RegisterCallback() to register an interrupt callback.
-
-  Function HAL_CAN_RegisterCallback() allows to register following callbacks:
-    (+) TxMailbox0CompleteCallback   : Tx Mailbox 0 Complete Callback.
-    (+) TxMailbox1CompleteCallback   : Tx Mailbox 1 Complete Callback.
-    (+) TxMailbox2CompleteCallback   : Tx Mailbox 2 Complete Callback.
-    (+) TxMailbox0AbortCallback      : Tx Mailbox 0 Abort Callback.
-    (+) TxMailbox1AbortCallback      : Tx Mailbox 1 Abort Callback.
-    (+) TxMailbox2AbortCallback      : Tx Mailbox 2 Abort Callback.
-    (+) RxFifo0MsgPendingCallback    : Rx Fifo 0 Message Pending Callback.
-    (+) RxFifo0FullCallback          : Rx Fifo 0 Full Callback.
-    (+) RxFifo1MsgPendingCallback    : Rx Fifo 1 Message Pending Callback.
-    (+) RxFifo1FullCallback          : Rx Fifo 1 Full Callback.
-    (+) SleepCallback                : Sleep Callback.
-    (+) WakeUpFromRxMsgCallback      : Wake Up From Rx Message Callback.
-    (+) ErrorCallback                : Error Callback.
-    (+) MspInitCallback              : CAN MspInit.
-    (+) MspDeInitCallback            : CAN MspDeInit.
-  This function takes as parameters the HAL peripheral handle, the Callback ID
-  and a pointer to the user callback function.
-
-  Use function HAL_CAN_UnRegisterCallback() to reset a callback to the default
-  weak function.
-  HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
-  and the Callback ID.
-  This function allows to reset following callbacks:
-    (+) TxMailbox0CompleteCallback   : Tx Mailbox 0 Complete Callback.
-    (+) TxMailbox1CompleteCallback   : Tx Mailbox 1 Complete Callback.
-    (+) TxMailbox2CompleteCallback   : Tx Mailbox 2 Complete Callback.
-    (+) TxMailbox0AbortCallback      : Tx Mailbox 0 Abort Callback.
-    (+) TxMailbox1AbortCallback      : Tx Mailbox 1 Abort Callback.
-    (+) TxMailbox2AbortCallback      : Tx Mailbox 2 Abort Callback.
-    (+) RxFifo0MsgPendingCallback    : Rx Fifo 0 Message Pending Callback.
-    (+) RxFifo0FullCallback          : Rx Fifo 0 Full Callback.
-    (+) RxFifo1MsgPendingCallback    : Rx Fifo 1 Message Pending Callback.
-    (+) RxFifo1FullCallback          : Rx Fifo 1 Full Callback.
-    (+) SleepCallback                : Sleep Callback.
-    (+) WakeUpFromRxMsgCallback      : Wake Up From Rx Message Callback.
-    (+) ErrorCallback                : Error Callback.
-    (+) MspInitCallback              : CAN MspInit.
-    (+) MspDeInitCallback            : CAN MspDeInit.
-
-  By default, after the HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET,
-  all callbacks are set to the corresponding weak functions:
-  example HAL_CAN_ErrorCallback().
-  Exception done for MspInit and MspDeInit functions that are
-  reset to the legacy weak function in the HAL_CAN_Init()/ HAL_CAN_DeInit() only when
-  these callbacks are null (not registered beforehand).
-  if not, MspInit or MspDeInit are not null, the HAL_CAN_Init()/ HAL_CAN_DeInit()
-  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
-
-  Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only.
-  Exception done MspInit/MspDeInit that can be registered/unregistered
-  in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state,
-  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
-  In that case first register the MspInit/MspDeInit user callbacks
-  using HAL_CAN_RegisterCallback() before calling HAL_CAN_DeInit()
-  or HAL_CAN_Init() function.
-
-  When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or
-  not defined, the callback registration feature is not available and all callbacks
-  are set to the corresponding weak functions.
-
-  @endverbatim
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-#if defined(CAN1)
-
-/** @defgroup CAN CAN
-  * @brief CAN driver modules
-  * @{
-  */
-
-#ifdef HAL_CAN_MODULE_ENABLED
-
-#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
-  #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once"
-#endif
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup CAN_Private_Constants CAN Private Constants
-  * @{
-  */
-#define CAN_TIMEOUT_VALUE 10U
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup CAN_Exported_Functions CAN Exported Functions
-  * @{
-  */
-
-/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) HAL_CAN_Init                       : Initialize and configure the CAN.
-      (+) HAL_CAN_DeInit                     : De-initialize the CAN.
-      (+) HAL_CAN_MspInit                    : Initialize the CAN MSP.
-      (+) HAL_CAN_MspDeInit                  : DeInitialize the CAN MSP.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the CAN peripheral according to the specified
-  *         parameters in the CAN_InitStruct.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
-{
-  uint32_t tickstart;
-
-  /* Check CAN handle */
-  if (hcan == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked));
-  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority));
-  assert_param(IS_CAN_MODE(hcan->Init.Mode));
-  assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth));
-  assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1));
-  assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));
-  assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
-
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-  if (hcan->State == HAL_CAN_STATE_RESET)
-  {
-    /* Reset callbacks to legacy functions */
-    hcan->RxFifo0MsgPendingCallback  =  HAL_CAN_RxFifo0MsgPendingCallback;  /* Legacy weak RxFifo0MsgPendingCallback  */
-    hcan->RxFifo0FullCallback        =  HAL_CAN_RxFifo0FullCallback;        /* Legacy weak RxFifo0FullCallback        */
-    hcan->RxFifo1MsgPendingCallback  =  HAL_CAN_RxFifo1MsgPendingCallback;  /* Legacy weak RxFifo1MsgPendingCallback  */
-    hcan->RxFifo1FullCallback        =  HAL_CAN_RxFifo1FullCallback;        /* Legacy weak RxFifo1FullCallback        */
-    hcan->TxMailbox0CompleteCallback =  HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */
-    hcan->TxMailbox1CompleteCallback =  HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */
-    hcan->TxMailbox2CompleteCallback =  HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */
-    hcan->TxMailbox0AbortCallback    =  HAL_CAN_TxMailbox0AbortCallback;    /* Legacy weak TxMailbox0AbortCallback    */
-    hcan->TxMailbox1AbortCallback    =  HAL_CAN_TxMailbox1AbortCallback;    /* Legacy weak TxMailbox1AbortCallback    */
-    hcan->TxMailbox2AbortCallback    =  HAL_CAN_TxMailbox2AbortCallback;    /* Legacy weak TxMailbox2AbortCallback    */
-    hcan->SleepCallback              =  HAL_CAN_SleepCallback;              /* Legacy weak SleepCallback              */
-    hcan->WakeUpFromRxMsgCallback    =  HAL_CAN_WakeUpFromRxMsgCallback;    /* Legacy weak WakeUpFromRxMsgCallback    */
-    hcan->ErrorCallback              =  HAL_CAN_ErrorCallback;              /* Legacy weak ErrorCallback              */
-
-    if (hcan->MspInitCallback == NULL)
-    {
-      hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */
-    }
-
-    /* Init the low level hardware: CLOCK, NVIC */
-    hcan->MspInitCallback(hcan);
-  }
-
-#else
-  if (hcan->State == HAL_CAN_STATE_RESET)
-  {
-    /* Init the low level hardware: CLOCK, NVIC */
-    HAL_CAN_MspInit(hcan);
-  }
-#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
-
-  /* Request initialisation */
-  SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait initialisation acknowledge */
-  while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
-  {
-    if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
-    {
-      /* Update error code */
-      hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
-
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_ERROR;
-
-      return HAL_ERROR;
-    }
-  }
-
-  /* Exit from sleep mode */
-  CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Check Sleep mode leave acknowledge */
-  while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
-  {
-    if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
-    {
-      /* Update error code */
-      hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
-
-      /* Change CAN state */
-      hcan->State = HAL_CAN_STATE_ERROR;
-
-      return HAL_ERROR;
-    }
-  }
-
-  /* Set the time triggered communication mode */
-  if (hcan->Init.TimeTriggeredMode == ENABLE)
-  {
-    SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
-  }
-  else
-  {
-    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
-  }
-
-  /* Set the automatic bus-off management */
-  if (hcan->Init.AutoBusOff == ENABLE)
-  {
-    SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
-  }
-  else
-  {
-    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
-  }
-
-  /* Set the automatic wake-up mode */
-  if (hcan->Init.AutoWakeUp == ENABLE)
-  {
-    SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
-  }
-  else
-  {
-    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
-  }
-
-  /* Set the automatic retransmission */
-  if (hcan->Init.AutoRetransmission == ENABLE)
-  {
-    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
-  }
-  else
-  {
-    SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
-  }
-
-  /* Set the receive FIFO locked mode */
-  if (hcan->Init.ReceiveFifoLocked == ENABLE)
-  {
-    SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
-  }
-  else
-  {
-    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
-  }
-
-  /* Set the transmit FIFO priority */
-  if (hcan->Init.TransmitFifoPriority == ENABLE)
-  {
-    SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
-  }
-  else
-  {
-    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
-  }
-
-  /* Set the bit timing register */
-  WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode           |
-                                            hcan->Init.SyncJumpWidth  |
-                                            hcan->Init.TimeSeg1       |
-                                            hcan->Init.TimeSeg2       |
-                                            (hcan->Init.Prescaler - 1U)));
-
-  /* Initialize the error code */
-  hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
-  /* Initialize the CAN state */
-  hcan->State = HAL_CAN_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deinitializes the CAN peripheral registers to their default
-  *         reset values.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
-{
-  /* Check CAN handle */
-  if (hcan == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
-
-  /* Stop the CAN module */
-  (void)HAL_CAN_Stop(hcan);
-
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-  if (hcan->MspDeInitCallback == NULL)
-  {
-    hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */
-  }
-
-  /* DeInit the low level hardware: CLOCK, NVIC */
-  hcan->MspDeInitCallback(hcan);
-
-#else
-  /* DeInit the low level hardware: CLOCK, NVIC */
-  HAL_CAN_MspDeInit(hcan);
-#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
-
-  /* Reset the CAN peripheral */
-  SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
-
-  /* Reset the CAN ErrorCode */
-  hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
-  /* Change CAN state */
-  hcan->State = HAL_CAN_STATE_RESET;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CAN MSP.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes the CAN MSP.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_MspDeInit could be implemented in the user file
-   */
-}
-
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-/**
-  * @brief  Register a CAN CallBack.
-  *         To be used instead of the weak predefined callback
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for CAN module
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID
-  *           @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID
-  *           @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID
-  *           @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID
-  *           @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID
-  *           @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID
-  *           @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID
-  *           @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID
-  *           @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID
-  *           @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID
-  *           @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID
-  *           @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID
-  *           @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID
-  *           @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
-  *           @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan))
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  if (hcan->State == HAL_CAN_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :
-        hcan->TxMailbox0CompleteCallback = pCallback;
-        break;
-
-      case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :
-        hcan->TxMailbox1CompleteCallback = pCallback;
-        break;
-
-      case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :
-        hcan->TxMailbox2CompleteCallback = pCallback;
-        break;
-
-      case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :
-        hcan->TxMailbox0AbortCallback = pCallback;
-        break;
-
-      case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :
-        hcan->TxMailbox1AbortCallback = pCallback;
-        break;
-
-      case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :
-        hcan->TxMailbox2AbortCallback = pCallback;
-        break;
-
-      case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :
-        hcan->RxFifo0MsgPendingCallback = pCallback;
-        break;
-
-      case HAL_CAN_RX_FIFO0_FULL_CB_ID :
-        hcan->RxFifo0FullCallback = pCallback;
-        break;
-
-      case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :
-        hcan->RxFifo1MsgPendingCallback = pCallback;
-        break;
-
-      case HAL_CAN_RX_FIFO1_FULL_CB_ID :
-        hcan->RxFifo1FullCallback = pCallback;
-        break;
-
-      case HAL_CAN_SLEEP_CB_ID :
-        hcan->SleepCallback = pCallback;
-        break;
-
-      case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :
-        hcan->WakeUpFromRxMsgCallback = pCallback;
-        break;
-
-      case HAL_CAN_ERROR_CB_ID :
-        hcan->ErrorCallback = pCallback;
-        break;
-
-      case HAL_CAN_MSPINIT_CB_ID :
-        hcan->MspInitCallback = pCallback;
-        break;
-
-      case HAL_CAN_MSPDEINIT_CB_ID :
-        hcan->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (hcan->State == HAL_CAN_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_CAN_MSPINIT_CB_ID :
-        hcan->MspInitCallback = pCallback;
-        break;
-
-      case HAL_CAN_MSPDEINIT_CB_ID :
-        hcan->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Unregister a CAN CallBack.
-  *         CAN callback is redirected to the weak predefined callback
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for CAN module
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID
-  *           @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID
-  *           @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID
-  *           @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID
-  *           @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID
-  *           @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID
-  *           @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID
-  *           @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID
-  *           @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID
-  *           @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID
-  *           @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID
-  *           @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID
-  *           @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID
-  *           @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
-  *           @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (hcan->State == HAL_CAN_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :
-        hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback;
-        break;
-
-      case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :
-        hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback;
-        break;
-
-      case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :
-        hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback;
-        break;
-
-      case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :
-        hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback;
-        break;
-
-      case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :
-        hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback;
-        break;
-
-      case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :
-        hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback;
-        break;
-
-      case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :
-        hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback;
-        break;
-
-      case HAL_CAN_RX_FIFO0_FULL_CB_ID :
-        hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback;
-        break;
-
-      case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :
-        hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback;
-        break;
-
-      case HAL_CAN_RX_FIFO1_FULL_CB_ID :
-        hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback;
-        break;
-
-      case HAL_CAN_SLEEP_CB_ID :
-        hcan->SleepCallback = HAL_CAN_SleepCallback;
-        break;
-
-      case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :
-        hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback;
-        break;
-
-      case HAL_CAN_ERROR_CB_ID :
-        hcan->ErrorCallback = HAL_CAN_ErrorCallback;
-        break;
-
-      case HAL_CAN_MSPINIT_CB_ID :
-        hcan->MspInitCallback = HAL_CAN_MspInit;
-        break;
-
-      case HAL_CAN_MSPDEINIT_CB_ID :
-        hcan->MspDeInitCallback = HAL_CAN_MspDeInit;
-        break;
-
-      default :
-        /* Update the error code */
-        hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (hcan->State == HAL_CAN_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_CAN_MSPINIT_CB_ID :
-        hcan->MspInitCallback = HAL_CAN_MspInit;
-        break;
-
-      case HAL_CAN_MSPDEINIT_CB_ID :
-        hcan->MspDeInitCallback = HAL_CAN_MspDeInit;
-        break;
-
-      default :
-        /* Update the error code */
-        hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  return status;
-}
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
- *  @brief    Configuration functions.
- *
-@verbatim
-  ==============================================================================
-              ##### Configuration functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) HAL_CAN_ConfigFilter            : Configure the CAN reception filters
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the CAN reception filter according to the specified
-  *         parameters in the CAN_FilterInitStruct.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  sFilterConfig pointer to a CAN_FilterTypeDef structure that
-  *         contains the filter configuration information.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)
-{
-  uint32_t filternbrbitpos;
-  CAN_TypeDef *can_ip = hcan->Instance;
-  HAL_CAN_StateTypeDef state = hcan->State;
-
-  if ((state == HAL_CAN_STATE_READY) ||
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    /* Check the parameters */
-    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh));
-    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow));
-    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh));
-    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow));
-    assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
-    assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
-    assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
-    assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation));
-
-#if defined(CAN3)
-    /* Check the CAN instance */
-    if (hcan->Instance == CAN3)
-    {
-      /* CAN3 is single instance with 14 dedicated filters banks */
-
-      /* Check the parameters */
-      assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
-    }
-    else
-    {
-      /* CAN1 and CAN2 are dual instances with 28 common filters banks */
-      /* Select master instance to access the filter banks */
-      can_ip = CAN1;
-
-      /* Check the parameters */
-      assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));
-      assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
-    }
-#elif defined(CAN2)
-    /* CAN1 and CAN2 are dual instances with 28 common filters banks */
-    /* Select master instance to access the filter banks */
-    can_ip = CAN1;
-
-    /* Check the parameters */
-    assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));
-    assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
-#else
-    /* CAN1 is single instance with 14 dedicated filters banks */
-
-    /* Check the parameters */
-    assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
-#endif
-
-    /* Initialisation mode for the filter */
-    SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
-
-#if defined(CAN3)
-    /* Check the CAN instance */
-    if (can_ip == CAN1)
-    {
-      /* Select the start filter number of CAN2 slave instance */
-      CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
-      SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
-    }
-
-#elif defined(CAN2)
-    /* Select the start filter number of CAN2 slave instance */
-    CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
-    SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
-
-#endif
-    /* Convert filter number into bit position */
-    filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
-
-    /* Filter Deactivation */
-    CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
-
-    /* Filter Scale */
-    if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
-    {
-      /* 16-bit scale for the filter */
-      CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
-
-      /* First 16-bit identifier and First 16-bit mask */
-      /* Or First 16-bit identifier and Second 16-bit identifier */
-      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
-        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
-        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
-
-      /* Second 16-bit identifier and Second 16-bit mask */
-      /* Or Third 16-bit identifier and Fourth 16-bit identifier */
-      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
-        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
-        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
-    }
-
-    if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
-    {
-      /* 32-bit scale for the filter */
-      SET_BIT(can_ip->FS1R, filternbrbitpos);
-
-      /* 32-bit identifier or First 32-bit identifier */
-      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
-        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
-        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
-
-      /* 32-bit mask or Second 32-bit identifier */
-      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
-        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
-        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
-    }
-
-    /* Filter Mode */
-    if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
-    {
-      /* Id/Mask mode for the filter*/
-      CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
-    }
-    else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
-    {
-      /* Identifier list mode for the filter*/
-      SET_BIT(can_ip->FM1R, filternbrbitpos);
-    }
-
-    /* Filter FIFO assignment */
-    if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
-    {
-      /* FIFO 0 assignation for the filter */
-      CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
-    }
-    else
-    {
-      /* FIFO 1 assignation for the filter */
-      SET_BIT(can_ip->FFA1R, filternbrbitpos);
-    }
-
-    /* Filter activation */
-    if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
-    {
-      SET_BIT(can_ip->FA1R, filternbrbitpos);
-    }
-
-    /* Leave the initialisation mode for the filter */
-    CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Update error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
-
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Exported_Functions_Group3 Control functions
- *  @brief    Control functions
- *
-@verbatim
-  ==============================================================================
-                      ##### Control functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) HAL_CAN_Start                    : Start the CAN module
-      (+) HAL_CAN_Stop                     : Stop the CAN module
-      (+) HAL_CAN_RequestSleep             : Request sleep mode entry.
-      (+) HAL_CAN_WakeUp                   : Wake up from sleep mode.
-      (+) HAL_CAN_IsSleepActive            : Check is sleep mode is active.
-      (+) HAL_CAN_AddTxMessage             : Add a message to the Tx mailboxes
-                                             and activate the corresponding
-                                             transmission request
-      (+) HAL_CAN_AbortTxRequest           : Abort transmission request
-      (+) HAL_CAN_GetTxMailboxesFreeLevel  : Return Tx mailboxes free level
-      (+) HAL_CAN_IsTxMessagePending       : Check if a transmission request is
-                                             pending on the selected Tx mailbox
-      (+) HAL_CAN_GetRxMessage             : Get a CAN frame from the Rx FIFO
-      (+) HAL_CAN_GetRxFifoFillLevel       : Return Rx FIFO fill level
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Start the CAN module.
-  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
-{
-  uint32_t tickstart;
-
-  if (hcan->State == HAL_CAN_STATE_READY)
-  {
-    /* Change CAN peripheral state */
-    hcan->State = HAL_CAN_STATE_LISTENING;
-
-    /* Request leave initialisation */
-    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait the acknowledge */
-    while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
-    {
-      /* Check for the Timeout */
-      if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
-      {
-        /* Update error code */
-        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
-
-        /* Change CAN state */
-        hcan->State = HAL_CAN_STATE_ERROR;
-
-        return HAL_ERROR;
-      }
-    }
-
-    /* Reset the CAN ErrorCode */
-    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Update error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
-
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Stop the CAN module and enable access to configuration registers.
-  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
-{
-  uint32_t tickstart;
-
-  if (hcan->State == HAL_CAN_STATE_LISTENING)
-  {
-    /* Request initialisation */
-    SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    /* Wait the acknowledge */
-    while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
-    {
-      /* Check for the Timeout */
-      if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
-      {
-        /* Update error code */
-        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
-
-        /* Change CAN state */
-        hcan->State = HAL_CAN_STATE_ERROR;
-
-        return HAL_ERROR;
-      }
-    }
-
-    /* Exit from sleep mode */
-    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
-
-    /* Change CAN peripheral state */
-    hcan->State = HAL_CAN_STATE_READY;
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Update error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED;
-
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Request the sleep mode (low power) entry.
-  *         When returning from this function, Sleep mode will be entered
-  *         as soon as the current CAN activity (transmission or reception
-  *         of a CAN frame) has been completed.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
-{
-  HAL_CAN_StateTypeDef state = hcan->State;
-
-  if ((state == HAL_CAN_STATE_READY) ||
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    /* Request Sleep mode */
-    SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Update error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Wake up from sleep mode.
-  *         When returning with HAL_OK status from this function, Sleep mode
-  *         is exited.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
-{
-  __IO uint32_t count = 0;
-  uint32_t timeout = 1000000U;
-  HAL_CAN_StateTypeDef state = hcan->State;
-
-  if ((state == HAL_CAN_STATE_READY) ||
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    /* Wake up request */
-    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
-
-    /* Wait sleep mode is exited */
-    do
-    {
-      /* Increment counter */
-      count++;
-
-      /* Check if timeout is reached */
-      if (count > timeout)
-      {
-        /* Update error code */
-        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
-
-        return HAL_ERROR;
-      }
-    }
-    while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Update error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
-
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Check is sleep mode is active.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval Status
-  *          - 0 : Sleep mode is not active.
-  *          - 1 : Sleep mode is active.
-  */
-uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)
-{
-  uint32_t status = 0U;
-  HAL_CAN_StateTypeDef state = hcan->State;
-
-  if ((state == HAL_CAN_STATE_READY) ||
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    /* Check Sleep mode */
-    if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
-    {
-      status = 1U;
-    }
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Add a message to the first free Tx mailbox and activate the
-  *         corresponding transmission request.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  pHeader pointer to a CAN_TxHeaderTypeDef structure.
-  * @param  aData array containing the payload of the Tx frame.
-  * @param  pTxMailbox pointer to a variable where the function will return
-  *         the TxMailbox used to store the Tx message.
-  *         This parameter can be a value of @arg CAN_Tx_Mailboxes.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)
-{
-  uint32_t transmitmailbox;
-  HAL_CAN_StateTypeDef state = hcan->State;
-  uint32_t tsr = READ_REG(hcan->Instance->TSR);
-
-  /* Check the parameters */
-  assert_param(IS_CAN_IDTYPE(pHeader->IDE));
-  assert_param(IS_CAN_RTR(pHeader->RTR));
-  assert_param(IS_CAN_DLC(pHeader->DLC));
-  if (pHeader->IDE == CAN_ID_STD)
-  {
-    assert_param(IS_CAN_STDID(pHeader->StdId));
-  }
-  else
-  {
-    assert_param(IS_CAN_EXTID(pHeader->ExtId));
-  }
-  assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
-
-  if ((state == HAL_CAN_STATE_READY) ||
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    /* Check that all the Tx mailboxes are not full */
-    if (((tsr & CAN_TSR_TME0) != 0U) ||
-        ((tsr & CAN_TSR_TME1) != 0U) ||
-        ((tsr & CAN_TSR_TME2) != 0U))
-    {
-      /* Select an empty transmit mailbox */
-      transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
-
-      /* Check transmit mailbox value */
-      if (transmitmailbox > 2U)
-      {
-        /* Update error code */
-        hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL;
-
-        return HAL_ERROR;
-      }
-
-      /* Store the Tx mailbox */
-      *pTxMailbox = (uint32_t)1 << transmitmailbox;
-
-      /* Set up the Id */
-      if (pHeader->IDE == CAN_ID_STD)
-      {
-        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
-                                                           pHeader->RTR);
-      }
-      else
-      {
-        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
-                                                           pHeader->IDE |
-                                                           pHeader->RTR);
-      }
-
-      /* Set up the DLC */
-      hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
-
-      /* Set up the Transmit Global Time mode */
-      if (pHeader->TransmitGlobalTime == ENABLE)
-      {
-        SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
-      }
-
-      /* Set up the data field */
-      WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
-                ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
-                ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
-                ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
-                ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
-      WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
-                ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) |
-                ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
-                ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
-                ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
-
-      /* Request transmission */
-      SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
-
-      /* Return function status */
-      return HAL_OK;
-    }
-    else
-    {
-      /* Update error code */
-      hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
-
-      return HAL_ERROR;
-    }
-  }
-  else
-  {
-    /* Update error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
-
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Abort transmission requests
-  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  TxMailboxes List of the Tx Mailboxes to abort.
-  *         This parameter can be any combination of @arg CAN_Tx_Mailboxes.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
-{
-  HAL_CAN_StateTypeDef state = hcan->State;
-
-  /* Check function parameters */
-  assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
-
-  if ((state == HAL_CAN_STATE_READY) ||
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    /* Check Tx Mailbox 0 */
-    if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U)
-    {
-      /* Add cancellation request for Tx Mailbox 0 */
-      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0);
-    }
-
-    /* Check Tx Mailbox 1 */
-    if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U)
-    {
-      /* Add cancellation request for Tx Mailbox 1 */
-      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1);
-    }
-
-    /* Check Tx Mailbox 2 */
-    if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U)
-    {
-      /* Add cancellation request for Tx Mailbox 2 */
-      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2);
-    }
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Update error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
-
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Return Tx Mailboxes free level: number of free Tx Mailboxes.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval Number of free Tx Mailboxes.
-  */
-uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)
-{
-  uint32_t freelevel = 0U;
-  HAL_CAN_StateTypeDef state = hcan->State;
-
-  if ((state == HAL_CAN_STATE_READY) ||
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    /* Check Tx Mailbox 0 status */
-    if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U)
-    {
-      freelevel++;
-    }
-
-    /* Check Tx Mailbox 1 status */
-    if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U)
-    {
-      freelevel++;
-    }
-
-    /* Check Tx Mailbox 2 status */
-    if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U)
-    {
-      freelevel++;
-    }
-  }
-
-  /* Return Tx Mailboxes free level */
-  return freelevel;
-}
-
-/**
-  * @brief  Check if a transmission request is pending on the selected Tx
-  *         Mailboxes.
-  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  TxMailboxes List of Tx Mailboxes to check.
-  *         This parameter can be any combination of @arg CAN_Tx_Mailboxes.
-  * @retval Status
-  *          - 0 : No pending transmission request on any selected Tx Mailboxes.
-  *          - 1 : Pending transmission request on at least one of the selected
-  *                Tx Mailbox.
-  */
-uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
-{
-  uint32_t status = 0U;
-  HAL_CAN_StateTypeDef state = hcan->State;
-
-  /* Check function parameters */
-  assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
-
-  if ((state == HAL_CAN_STATE_READY) ||
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    /* Check pending transmission request on the selected Tx Mailboxes */
-    if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos))
-    {
-      status = 1U;
-    }
-  }
-
-  /* Return status */
-  return status;
-}
-
-/**
-  * @brief  Return timestamp of Tx message sent, if time triggered communication
-            mode is enabled.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  TxMailbox Tx Mailbox where the timestamp of message sent will be
-  *         read.
-  *         This parameter can be one value of @arg CAN_Tx_Mailboxes.
-  * @retval Timestamp of message sent from Tx Mailbox.
-  */
-uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
-{
-  uint32_t timestamp = 0U;
-  uint32_t transmitmailbox;
-  HAL_CAN_StateTypeDef state = hcan->State;
-
-  /* Check function parameters */
-  assert_param(IS_CAN_TX_MAILBOX(TxMailbox));
-
-  if ((state == HAL_CAN_STATE_READY) ||
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    /* Select the Tx mailbox */
-    transmitmailbox = POSITION_VAL(TxMailbox);
-
-    /* Get timestamp */
-    timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos;
-  }
-
-  /* Return the timestamp */
-  return timestamp;
-}
-
-/**
-  * @brief  Get an CAN frame from the Rx FIFO zone into the message RAM.
-  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  RxFifo Fifo number of the received message to be read.
-  *         This parameter can be a value of @arg CAN_receive_FIFO_number.
-  * @param  pHeader pointer to a CAN_RxHeaderTypeDef structure where the header
-  *         of the Rx frame will be stored.
-  * @param  aData array where the payload of the Rx frame will be stored.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
-{
-  HAL_CAN_StateTypeDef state = hcan->State;
-
-  assert_param(IS_CAN_RX_FIFO(RxFifo));
-
-  if ((state == HAL_CAN_STATE_READY) ||
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    /* Check the Rx FIFO */
-    if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
-    {
-      /* Check that the Rx FIFO 0 is not empty */
-      if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
-      {
-        /* Update error code */
-        hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
-
-        return HAL_ERROR;
-      }
-    }
-    else /* Rx element is assigned to Rx FIFO 1 */
-    {
-      /* Check that the Rx FIFO 1 is not empty */
-      if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
-      {
-        /* Update error code */
-        hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
-
-        return HAL_ERROR;
-      }
-    }
-
-    /* Get the header */
-    pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
-    if (pHeader->IDE == CAN_ID_STD)
-    {
-      pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
-    }
-    else
-    {
-      pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
-    }
-    pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
-    pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
-    pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
-    pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
-
-    /* Get the data */
-    aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
-    aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
-    aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
-    aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
-    aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
-    aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
-    aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
-    aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
-
-    /* Release the FIFO */
-    if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
-    {
-      /* Release RX FIFO 0 */
-      SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
-    }
-    else /* Rx element is assigned to Rx FIFO 1 */
-    {
-      /* Release RX FIFO 1 */
-      SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
-    }
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Update error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
-
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Return Rx FIFO fill level.
-  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  RxFifo Rx FIFO.
-  *         This parameter can be a value of @arg CAN_receive_FIFO_number.
-  * @retval Number of messages available in Rx FIFO.
-  */
-uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
-{
-  uint32_t filllevel = 0U;
-  HAL_CAN_StateTypeDef state = hcan->State;
-
-  /* Check function parameters */
-  assert_param(IS_CAN_RX_FIFO(RxFifo));
-
-  if ((state == HAL_CAN_STATE_READY) ||
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    if (RxFifo == CAN_RX_FIFO0)
-    {
-      filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0;
-    }
-    else /* RxFifo == CAN_RX_FIFO1 */
-    {
-      filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1;
-    }
-  }
-
-  /* Return Rx FIFO fill level */
-  return filllevel;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
- *  @brief    Interrupts management
- *
-@verbatim
-  ==============================================================================
-                       ##### Interrupts management #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) HAL_CAN_ActivateNotification      : Enable interrupts
-      (+) HAL_CAN_DeactivateNotification    : Disable interrupts
-      (+) HAL_CAN_IRQHandler                : Handles CAN interrupt request
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enable interrupts.
-  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  ActiveITs indicates which interrupts will be enabled.
-  *         This parameter can be any combination of @arg CAN_Interrupts.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
-{
-  HAL_CAN_StateTypeDef state = hcan->State;
-
-  /* Check function parameters */
-  assert_param(IS_CAN_IT(ActiveITs));
-
-  if ((state == HAL_CAN_STATE_READY) ||
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    /* Enable the selected interrupts */
-    __HAL_CAN_ENABLE_IT(hcan, ActiveITs);
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Update error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
-
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Disable interrupts.
-  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @param  InactiveITs indicates which interrupts will be disabled.
-  *         This parameter can be any combination of @arg CAN_Interrupts.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs)
-{
-  HAL_CAN_StateTypeDef state = hcan->State;
-
-  /* Check function parameters */
-  assert_param(IS_CAN_IT(InactiveITs));
-
-  if ((state == HAL_CAN_STATE_READY) ||
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    /* Disable the selected interrupts */
-    __HAL_CAN_DISABLE_IT(hcan, InactiveITs);
-
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Update error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
-
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Handles CAN interrupt request
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
-{
-  uint32_t errorcode = HAL_CAN_ERROR_NONE;
-  uint32_t interrupts = READ_REG(hcan->Instance->IER);
-  uint32_t msrflags = READ_REG(hcan->Instance->MSR);
-  uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
-  uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
-  uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
-  uint32_t esrflags = READ_REG(hcan->Instance->ESR);
-
-  /* Transmit Mailbox empty interrupt management *****************************/
-  if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
-  {
-    /* Transmit Mailbox 0 management *****************************************/
-    if ((tsrflags & CAN_TSR_RQCP0) != 0U)
-    {
-      /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
-      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
-
-      if ((tsrflags & CAN_TSR_TXOK0) != 0U)
-      {
-        /* Transmission Mailbox 0 complete callback */
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-        /* Call registered callback*/
-        hcan->TxMailbox0CompleteCallback(hcan);
-#else
-        /* Call weak (surcharged) callback */
-        HAL_CAN_TxMailbox0CompleteCallback(hcan);
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-      }
-      else
-      {
-        if ((tsrflags & CAN_TSR_ALST0) != 0U)
-        {
-          /* Update error code */
-          errorcode |= HAL_CAN_ERROR_TX_ALST0;
-        }
-        else if ((tsrflags & CAN_TSR_TERR0) != 0U)
-        {
-          /* Update error code */
-          errorcode |= HAL_CAN_ERROR_TX_TERR0;
-        }
-        else
-        {
-          /* Transmission Mailbox 0 abort callback */
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-          /* Call registered callback*/
-          hcan->TxMailbox0AbortCallback(hcan);
-#else
-          /* Call weak (surcharged) callback */
-          HAL_CAN_TxMailbox0AbortCallback(hcan);
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-        }
-      }
-    }
-
-    /* Transmit Mailbox 1 management *****************************************/
-    if ((tsrflags & CAN_TSR_RQCP1) != 0U)
-    {
-      /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
-      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
-
-      if ((tsrflags & CAN_TSR_TXOK1) != 0U)
-      {
-        /* Transmission Mailbox 1 complete callback */
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-        /* Call registered callback*/
-        hcan->TxMailbox1CompleteCallback(hcan);
-#else
-        /* Call weak (surcharged) callback */
-        HAL_CAN_TxMailbox1CompleteCallback(hcan);
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-      }
-      else
-      {
-        if ((tsrflags & CAN_TSR_ALST1) != 0U)
-        {
-          /* Update error code */
-          errorcode |= HAL_CAN_ERROR_TX_ALST1;
-        }
-        else if ((tsrflags & CAN_TSR_TERR1) != 0U)
-        {
-          /* Update error code */
-          errorcode |= HAL_CAN_ERROR_TX_TERR1;
-        }
-        else
-        {
-          /* Transmission Mailbox 1 abort callback */
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-          /* Call registered callback*/
-          hcan->TxMailbox1AbortCallback(hcan);
-#else
-          /* Call weak (surcharged) callback */
-          HAL_CAN_TxMailbox1AbortCallback(hcan);
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-        }
-      }
-    }
-
-    /* Transmit Mailbox 2 management *****************************************/
-    if ((tsrflags & CAN_TSR_RQCP2) != 0U)
-    {
-      /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
-      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
-
-      if ((tsrflags & CAN_TSR_TXOK2) != 0U)
-      {
-        /* Transmission Mailbox 2 complete callback */
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-        /* Call registered callback*/
-        hcan->TxMailbox2CompleteCallback(hcan);
-#else
-        /* Call weak (surcharged) callback */
-        HAL_CAN_TxMailbox2CompleteCallback(hcan);
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-      }
-      else
-      {
-        if ((tsrflags & CAN_TSR_ALST2) != 0U)
-        {
-          /* Update error code */
-          errorcode |= HAL_CAN_ERROR_TX_ALST2;
-        }
-        else if ((tsrflags & CAN_TSR_TERR2) != 0U)
-        {
-          /* Update error code */
-          errorcode |= HAL_CAN_ERROR_TX_TERR2;
-        }
-        else
-        {
-          /* Transmission Mailbox 2 abort callback */
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-          /* Call registered callback*/
-          hcan->TxMailbox2AbortCallback(hcan);
-#else
-          /* Call weak (surcharged) callback */
-          HAL_CAN_TxMailbox2AbortCallback(hcan);
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-        }
-      }
-    }
-  }
-
-  /* Receive FIFO 0 overrun interrupt management *****************************/
-  if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
-  {
-    if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
-    {
-      /* Set CAN error code to Rx Fifo 0 overrun error */
-      errorcode |= HAL_CAN_ERROR_RX_FOV0;
-
-      /* Clear FIFO0 Overrun Flag */
-      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
-    }
-  }
-
-  /* Receive FIFO 0 full interrupt management ********************************/
-  if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
-  {
-    if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
-    {
-      /* Clear FIFO 0 full Flag */
-      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
-
-      /* Receive FIFO 0 full Callback */
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-      /* Call registered callback*/
-      hcan->RxFifo0FullCallback(hcan);
-#else
-      /* Call weak (surcharged) callback */
-      HAL_CAN_RxFifo0FullCallback(hcan);
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-    }
-  }
-
-  /* Receive FIFO 0 message pending interrupt management *********************/
-  if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
-  {
-    /* Check if message is still pending */
-    if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
-    {
-      /* Receive FIFO 0 message pending Callback */
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-      /* Call registered callback*/
-      hcan->RxFifo0MsgPendingCallback(hcan);
-#else
-      /* Call weak (surcharged) callback */
-      HAL_CAN_RxFifo0MsgPendingCallback(hcan);
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-    }
-  }
-
-  /* Receive FIFO 1 overrun interrupt management *****************************/
-  if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
-  {
-    if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
-    {
-      /* Set CAN error code to Rx Fifo 1 overrun error */
-      errorcode |= HAL_CAN_ERROR_RX_FOV1;
-
-      /* Clear FIFO1 Overrun Flag */
-      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
-    }
-  }
-
-  /* Receive FIFO 1 full interrupt management ********************************/
-  if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
-  {
-    if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
-    {
-      /* Clear FIFO 1 full Flag */
-      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
-
-      /* Receive FIFO 1 full Callback */
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-      /* Call registered callback*/
-      hcan->RxFifo1FullCallback(hcan);
-#else
-      /* Call weak (surcharged) callback */
-      HAL_CAN_RxFifo1FullCallback(hcan);
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-    }
-  }
-
-  /* Receive FIFO 1 message pending interrupt management *********************/
-  if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
-  {
-    /* Check if message is still pending */
-    if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
-    {
-      /* Receive FIFO 1 message pending Callback */
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-      /* Call registered callback*/
-      hcan->RxFifo1MsgPendingCallback(hcan);
-#else
-      /* Call weak (surcharged) callback */
-      HAL_CAN_RxFifo1MsgPendingCallback(hcan);
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-    }
-  }
-
-  /* Sleep interrupt management *********************************************/
-  if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
-  {
-    if ((msrflags & CAN_MSR_SLAKI) != 0U)
-    {
-      /* Clear Sleep interrupt Flag */
-      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
-
-      /* Sleep Callback */
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-      /* Call registered callback*/
-      hcan->SleepCallback(hcan);
-#else
-      /* Call weak (surcharged) callback */
-      HAL_CAN_SleepCallback(hcan);
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-    }
-  }
-
-  /* WakeUp interrupt management *********************************************/
-  if ((interrupts & CAN_IT_WAKEUP) != 0U)
-  {
-    if ((msrflags & CAN_MSR_WKUI) != 0U)
-    {
-      /* Clear WakeUp Flag */
-      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
-
-      /* WakeUp Callback */
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-      /* Call registered callback*/
-      hcan->WakeUpFromRxMsgCallback(hcan);
-#else
-      /* Call weak (surcharged) callback */
-      HAL_CAN_WakeUpFromRxMsgCallback(hcan);
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-    }
-  }
-
-  /* Error interrupts management *********************************************/
-  if ((interrupts & CAN_IT_ERROR) != 0U)
-  {
-    if ((msrflags & CAN_MSR_ERRI) != 0U)
-    {
-      /* Check Error Warning Flag */
-      if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
-          ((esrflags & CAN_ESR_EWGF) != 0U))
-      {
-        /* Set CAN error code to Error Warning */
-        errorcode |= HAL_CAN_ERROR_EWG;
-
-        /* No need for clear of Error Warning Flag as read-only */
-      }
-
-      /* Check Error Passive Flag */
-      if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
-          ((esrflags & CAN_ESR_EPVF) != 0U))
-      {
-        /* Set CAN error code to Error Passive */
-        errorcode |= HAL_CAN_ERROR_EPV;
-
-        /* No need for clear of Error Passive Flag as read-only */
-      }
-
-      /* Check Bus-off Flag */
-      if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
-          ((esrflags & CAN_ESR_BOFF) != 0U))
-      {
-        /* Set CAN error code to Bus-Off */
-        errorcode |= HAL_CAN_ERROR_BOF;
-
-        /* No need for clear of Error Bus-Off as read-only */
-      }
-
-      /* Check Last Error Code Flag */
-      if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
-          ((esrflags & CAN_ESR_LEC) != 0U))
-      {
-        switch (esrflags & CAN_ESR_LEC)
-        {
-          case (CAN_ESR_LEC_0):
-            /* Set CAN error code to Stuff error */
-            errorcode |= HAL_CAN_ERROR_STF;
-            break;
-          case (CAN_ESR_LEC_1):
-            /* Set CAN error code to Form error */
-            errorcode |= HAL_CAN_ERROR_FOR;
-            break;
-          case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
-            /* Set CAN error code to Acknowledgement error */
-            errorcode |= HAL_CAN_ERROR_ACK;
-            break;
-          case (CAN_ESR_LEC_2):
-            /* Set CAN error code to Bit recessive error */
-            errorcode |= HAL_CAN_ERROR_BR;
-            break;
-          case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
-            /* Set CAN error code to Bit Dominant error */
-            errorcode |= HAL_CAN_ERROR_BD;
-            break;
-          case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
-            /* Set CAN error code to CRC error */
-            errorcode |= HAL_CAN_ERROR_CRC;
-            break;
-          default:
-            break;
-        }
-
-        /* Clear Last error code Flag */
-        CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
-      }
-    }
-
-    /* Clear ERRI Flag */
-    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
-  }
-
-  /* Call the Error call Back in case of Errors */
-  if (errorcode != HAL_CAN_ERROR_NONE)
-  {
-    /* Update error code in handle */
-    hcan->ErrorCode |= errorcode;
-
-    /* Call Error callback function */
-#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
-    /* Call registered callback*/
-    hcan->ErrorCallback(hcan);
-#else
-    /* Call weak (surcharged) callback */
-    HAL_CAN_ErrorCallback(hcan);
-#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Exported_Functions_Group5 Callback functions
- *  @brief   CAN Callback functions
- *
-@verbatim
-  ==============================================================================
-                          ##### Callback functions #####
-  ==============================================================================
-    [..]
-    This subsection provides the following callback functions:
-      (+) HAL_CAN_TxMailbox0CompleteCallback
-      (+) HAL_CAN_TxMailbox1CompleteCallback
-      (+) HAL_CAN_TxMailbox2CompleteCallback
-      (+) HAL_CAN_TxMailbox0AbortCallback
-      (+) HAL_CAN_TxMailbox1AbortCallback
-      (+) HAL_CAN_TxMailbox2AbortCallback
-      (+) HAL_CAN_RxFifo0MsgPendingCallback
-      (+) HAL_CAN_RxFifo0FullCallback
-      (+) HAL_CAN_RxFifo1MsgPendingCallback
-      (+) HAL_CAN_RxFifo1FullCallback
-      (+) HAL_CAN_SleepCallback
-      (+) HAL_CAN_WakeUpFromRxMsgCallback
-      (+) HAL_CAN_ErrorCallback
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmission Mailbox 0 complete callback.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
-            user file
-   */
-}
-
-/**
-  * @brief  Transmission Mailbox 1 complete callback.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
-            user file
-   */
-}
-
-/**
-  * @brief  Transmission Mailbox 2 complete callback.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
-            user file
-   */
-}
-
-/**
-  * @brief  Transmission Mailbox 0 Cancellation callback.
-  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
-            user file
-   */
-}
-
-/**
-  * @brief  Transmission Mailbox 1 Cancellation callback.
-  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
-            user file
-   */
-}
-
-/**
-  * @brief  Transmission Mailbox 2 Cancellation callback.
-  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
-            user file
-   */
-}
-
-/**
-  * @brief  Rx FIFO 0 message pending callback.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the
-            user file
-   */
-}
-
-/**
-  * @brief  Rx FIFO 0 full callback.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_RxFifo0FullCallback could be implemented in the user
-            file
-   */
-}
-
-/**
-  * @brief  Rx FIFO 1 message pending callback.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
-            user file
-   */
-}
-
-/**
-  * @brief  Rx FIFO 1 full callback.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_RxFifo1FullCallback could be implemented in the user
-            file
-   */
-}
-
-/**
-  * @brief  Sleep callback.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_SleepCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  WakeUp from Rx message callback.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
-            user file
-   */
-}
-
-/**
-  * @brief  Error CAN callback.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval None
-  */
-__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(hcan);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CAN_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
- *  @brief   CAN Peripheral State functions
- *
-@verbatim
-  ==============================================================================
-            ##### Peripheral State and Error functions #####
-  ==============================================================================
-    [..]
-    This subsection provides functions allowing to :
-      (+) HAL_CAN_GetState()  : Return the CAN state.
-      (+) HAL_CAN_GetError()  : Return the CAN error codes if any.
-      (+) HAL_CAN_ResetError(): Reset the CAN error codes if any.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the CAN state.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL state
-  */
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)
-{
-  HAL_CAN_StateTypeDef state = hcan->State;
-
-  if ((state == HAL_CAN_STATE_READY) ||
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    /* Check sleep mode acknowledge flag */
-    if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
-    {
-      /* Sleep mode is active */
-      state = HAL_CAN_STATE_SLEEP_ACTIVE;
-    }
-    /* Check sleep mode request flag */
-    else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U)
-    {
-      /* Sleep mode request is pending */
-      state = HAL_CAN_STATE_SLEEP_PENDING;
-    }
-    else
-    {
-      /* Neither sleep mode request nor sleep mode acknowledge */
-    }
-  }
-
-  /* Return CAN state */
-  return state;
-}
-
-/**
-  * @brief  Return the CAN error code.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval CAN Error Code
-  */
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
-{
-  /* Return CAN error code */
-  return hcan->ErrorCode;
-}
-
-/**
-  * @brief  Reset the CAN error code.
-  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
-  *         the configuration information for the specified CAN.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  HAL_CAN_StateTypeDef state = hcan->State;
-
-  if ((state == HAL_CAN_STATE_READY) ||
-      (state == HAL_CAN_STATE_LISTENING))
-  {
-    /* Reset CAN error code */
-    hcan->ErrorCode = 0U;
-  }
-  else
-  {
-    /* Update error code */
-    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
-
-    status = HAL_ERROR;
-  }
-
-  /* Return the status */
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_CAN_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-#endif /* CAN1 */
-
-/**
-  * @}
-  */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_can.c
+  * @author  MCD Application Team
+  * @brief   CAN HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Controller Area Network (CAN) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Configuration functions
+  *           + Control functions
+  *           + Interrupts management
+  *           + Callbacks functions
+  *           + Peripheral State and Error functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (#) Initialize the CAN low level resources by implementing the
+          HAL_CAN_MspInit():
+         (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
+         (++) Configure CAN pins
+             (+++) Enable the clock for the CAN GPIOs
+             (+++) Configure CAN pins as alternate function open-drain
+         (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
+             (+++) Configure the CAN interrupt priority using
+                   HAL_NVIC_SetPriority()
+             (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ()
+             (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler()
+
+      (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This
+          function resorts to HAL_CAN_MspInit() for low-level initialization.
+
+      (#) Configure the reception filters using the following configuration
+          functions:
+            (++) HAL_CAN_ConfigFilter()
+
+      (#) Start the CAN module using HAL_CAN_Start() function. At this level
+          the node is active on the bus: it receive messages, and can send
+          messages.
+
+      (#) To manage messages transmission, the following Tx control functions
+          can be used:
+            (++) HAL_CAN_AddTxMessage() to request transmission of a new
+                 message.
+            (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending
+                 message.
+            (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx
+                 mailboxes.
+            (++) HAL_CAN_IsTxMessagePending() to check if a message is pending
+                 in a Tx mailbox.
+            (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message
+                 sent, if time triggered communication mode is enabled.
+
+      (#) When a message is received into the CAN Rx FIFOs, it can be retrieved
+          using the HAL_CAN_GetRxMessage() function. The function
+          HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are
+          stored in the Rx Fifo.
+
+      (#) Calling the HAL_CAN_Stop() function stops the CAN module.
+
+      (#) The deinitialization is achieved with HAL_CAN_DeInit() function.
+
+
+      *** Polling mode operation ***
+      ==============================
+    [..]
+      (#) Reception:
+            (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel()
+                 until at least one message is received.
+            (++) Then get the message using HAL_CAN_GetRxMessage().
+
+      (#) Transmission:
+            (++) Monitor the Tx mailboxes availability until at least one Tx
+                 mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel().
+            (++) Then request transmission of a message using
+                 HAL_CAN_AddTxMessage().
+
+
+      *** Interrupt mode operation ***
+      ================================
+    [..]
+      (#) Notifications are activated using HAL_CAN_ActivateNotification()
+          function. Then, the process can be controlled through the
+          available user callbacks: HAL_CAN_xxxCallback(), using same APIs
+          HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage().
+
+      (#) Notifications can be deactivated using
+          HAL_CAN_DeactivateNotification() function.
+
+      (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and
+          CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig
+          the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and
+          HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options
+          here.
+            (++) Directly get the Rx message in the callback, using
+                 HAL_CAN_GetRxMessage().
+            (++) Or deactivate the notification in the callback without
+                 getting the Rx message. The Rx message can then be got later
+                 using HAL_CAN_GetRxMessage(). Once the Rx message have been
+                 read, the notification can be activated again.
+
+
+      *** Sleep mode ***
+      ==================
+    [..]
+      (#) The CAN peripheral can be put in sleep mode (low power), using
+          HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the
+          current CAN activity (transmission or reception of a CAN frame) will
+          be completed.
+
+      (#) A notification can be activated to be informed when the sleep mode
+          will be entered.
+
+      (#) It can be checked if the sleep mode is entered using
+          HAL_CAN_IsSleepActive().
+          Note that the CAN state (accessible from the API HAL_CAN_GetState())
+          is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is
+          submitted (the sleep mode is not yet entered), and become
+          HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective.
+
+      (#) The wake-up from sleep mode can be triggered by two ways:
+            (++) Using HAL_CAN_WakeUp(). When returning from this function,
+                 the sleep mode is exited (if return status is HAL_OK).
+            (++) When a start of Rx CAN frame is detected by the CAN peripheral,
+                 if automatic wake up mode is enabled.
+
+  *** Callback registration ***
+  =============================================
+
+  The compilation define  USE_HAL_CAN_REGISTER_CALLBACKS when set to 1
+  allows the user to configure dynamically the driver callbacks.
+  Use Function HAL_CAN_RegisterCallback() to register an interrupt callback.
+
+  Function HAL_CAN_RegisterCallback() allows to register following callbacks:
+    (+) TxMailbox0CompleteCallback   : Tx Mailbox 0 Complete Callback.
+    (+) TxMailbox1CompleteCallback   : Tx Mailbox 1 Complete Callback.
+    (+) TxMailbox2CompleteCallback   : Tx Mailbox 2 Complete Callback.
+    (+) TxMailbox0AbortCallback      : Tx Mailbox 0 Abort Callback.
+    (+) TxMailbox1AbortCallback      : Tx Mailbox 1 Abort Callback.
+    (+) TxMailbox2AbortCallback      : Tx Mailbox 2 Abort Callback.
+    (+) RxFifo0MsgPendingCallback    : Rx Fifo 0 Message Pending Callback.
+    (+) RxFifo0FullCallback          : Rx Fifo 0 Full Callback.
+    (+) RxFifo1MsgPendingCallback    : Rx Fifo 1 Message Pending Callback.
+    (+) RxFifo1FullCallback          : Rx Fifo 1 Full Callback.
+    (+) SleepCallback                : Sleep Callback.
+    (+) WakeUpFromRxMsgCallback      : Wake Up From Rx Message Callback.
+    (+) ErrorCallback                : Error Callback.
+    (+) MspInitCallback              : CAN MspInit.
+    (+) MspDeInitCallback            : CAN MspDeInit.
+  This function takes as parameters the HAL peripheral handle, the Callback ID
+  and a pointer to the user callback function.
+
+  Use function HAL_CAN_UnRegisterCallback() to reset a callback to the default
+  weak function.
+  HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle,
+  and the Callback ID.
+  This function allows to reset following callbacks:
+    (+) TxMailbox0CompleteCallback   : Tx Mailbox 0 Complete Callback.
+    (+) TxMailbox1CompleteCallback   : Tx Mailbox 1 Complete Callback.
+    (+) TxMailbox2CompleteCallback   : Tx Mailbox 2 Complete Callback.
+    (+) TxMailbox0AbortCallback      : Tx Mailbox 0 Abort Callback.
+    (+) TxMailbox1AbortCallback      : Tx Mailbox 1 Abort Callback.
+    (+) TxMailbox2AbortCallback      : Tx Mailbox 2 Abort Callback.
+    (+) RxFifo0MsgPendingCallback    : Rx Fifo 0 Message Pending Callback.
+    (+) RxFifo0FullCallback          : Rx Fifo 0 Full Callback.
+    (+) RxFifo1MsgPendingCallback    : Rx Fifo 1 Message Pending Callback.
+    (+) RxFifo1FullCallback          : Rx Fifo 1 Full Callback.
+    (+) SleepCallback                : Sleep Callback.
+    (+) WakeUpFromRxMsgCallback      : Wake Up From Rx Message Callback.
+    (+) ErrorCallback                : Error Callback.
+    (+) MspInitCallback              : CAN MspInit.
+    (+) MspDeInitCallback            : CAN MspDeInit.
+
+  By default, after the HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET,
+  all callbacks are set to the corresponding weak functions:
+  example HAL_CAN_ErrorCallback().
+  Exception done for MspInit and MspDeInit functions that are
+  reset to the legacy weak function in the HAL_CAN_Init()/ HAL_CAN_DeInit() only when
+  these callbacks are null (not registered beforehand).
+  if not, MspInit or MspDeInit are not null, the HAL_CAN_Init()/ HAL_CAN_DeInit()
+  keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+  Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only.
+  Exception done MspInit/MspDeInit that can be registered/unregistered
+  in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state,
+  thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+  In that case first register the MspInit/MspDeInit user callbacks
+  using HAL_CAN_RegisterCallback() before calling HAL_CAN_DeInit()
+  or HAL_CAN_Init() function.
+
+  When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or
+  not defined, the callback registration feature is not available and all callbacks
+  are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+#if defined(CAN1)
+
+/** @defgroup CAN CAN
+  * @brief CAN driver modules
+  * @{
+  */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+  #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once"
+#endif
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+  * @{
+  */
+#define CAN_TIMEOUT_VALUE 10U
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Functions CAN Exported Functions
+  * @{
+  */
+
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_CAN_Init                       : Initialize and configure the CAN.
+      (+) HAL_CAN_DeInit                     : De-initialize the CAN.
+      (+) HAL_CAN_MspInit                    : Initialize the CAN MSP.
+      (+) HAL_CAN_MspDeInit                  : DeInitialize the CAN MSP.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the CAN peripheral according to the specified
+  *         parameters in the CAN_InitStruct.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
+{
+  uint32_t tickstart;
+
+  /* Check CAN handle */
+  if (hcan == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked));
+  assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority));
+  assert_param(IS_CAN_MODE(hcan->Init.Mode));
+  assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth));
+  assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1));
+  assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));
+  assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
+
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+  if (hcan->State == HAL_CAN_STATE_RESET)
+  {
+    /* Reset callbacks to legacy functions */
+    hcan->RxFifo0MsgPendingCallback  =  HAL_CAN_RxFifo0MsgPendingCallback;  /* Legacy weak RxFifo0MsgPendingCallback  */
+    hcan->RxFifo0FullCallback        =  HAL_CAN_RxFifo0FullCallback;        /* Legacy weak RxFifo0FullCallback        */
+    hcan->RxFifo1MsgPendingCallback  =  HAL_CAN_RxFifo1MsgPendingCallback;  /* Legacy weak RxFifo1MsgPendingCallback  */
+    hcan->RxFifo1FullCallback        =  HAL_CAN_RxFifo1FullCallback;        /* Legacy weak RxFifo1FullCallback        */
+    hcan->TxMailbox0CompleteCallback =  HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */
+    hcan->TxMailbox1CompleteCallback =  HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */
+    hcan->TxMailbox2CompleteCallback =  HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */
+    hcan->TxMailbox0AbortCallback    =  HAL_CAN_TxMailbox0AbortCallback;    /* Legacy weak TxMailbox0AbortCallback    */
+    hcan->TxMailbox1AbortCallback    =  HAL_CAN_TxMailbox1AbortCallback;    /* Legacy weak TxMailbox1AbortCallback    */
+    hcan->TxMailbox2AbortCallback    =  HAL_CAN_TxMailbox2AbortCallback;    /* Legacy weak TxMailbox2AbortCallback    */
+    hcan->SleepCallback              =  HAL_CAN_SleepCallback;              /* Legacy weak SleepCallback              */
+    hcan->WakeUpFromRxMsgCallback    =  HAL_CAN_WakeUpFromRxMsgCallback;    /* Legacy weak WakeUpFromRxMsgCallback    */
+    hcan->ErrorCallback              =  HAL_CAN_ErrorCallback;              /* Legacy weak ErrorCallback              */
+
+    if (hcan->MspInitCallback == NULL)
+    {
+      hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */
+    }
+
+    /* Init the low level hardware: CLOCK, NVIC */
+    hcan->MspInitCallback(hcan);
+  }
+
+#else
+  if (hcan->State == HAL_CAN_STATE_RESET)
+  {
+    /* Init the low level hardware: CLOCK, NVIC */
+    HAL_CAN_MspInit(hcan);
+  }
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
+
+  /* Request initialisation */
+  SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait initialisation acknowledge */
+  while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+      /* Change CAN state */
+      hcan->State = HAL_CAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Exit from sleep mode */
+  CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check Sleep mode leave acknowledge */
+  while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
+  {
+    if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+    {
+      /* Update error code */
+      hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+      /* Change CAN state */
+      hcan->State = HAL_CAN_STATE_ERROR;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Set the time triggered communication mode */
+  if (hcan->Init.TimeTriggeredMode == ENABLE)
+  {
+    SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
+  }
+  else
+  {
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
+  }
+
+  /* Set the automatic bus-off management */
+  if (hcan->Init.AutoBusOff == ENABLE)
+  {
+    SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
+  }
+  else
+  {
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
+  }
+
+  /* Set the automatic wake-up mode */
+  if (hcan->Init.AutoWakeUp == ENABLE)
+  {
+    SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
+  }
+  else
+  {
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
+  }
+
+  /* Set the automatic retransmission */
+  if (hcan->Init.AutoRetransmission == ENABLE)
+  {
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
+  }
+  else
+  {
+    SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
+  }
+
+  /* Set the receive FIFO locked mode */
+  if (hcan->Init.ReceiveFifoLocked == ENABLE)
+  {
+    SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
+  }
+  else
+  {
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
+  }
+
+  /* Set the transmit FIFO priority */
+  if (hcan->Init.TransmitFifoPriority == ENABLE)
+  {
+    SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
+  }
+  else
+  {
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
+  }
+
+  /* Set the bit timing register */
+  WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode           |
+                                            hcan->Init.SyncJumpWidth  |
+                                            hcan->Init.TimeSeg1       |
+                                            hcan->Init.TimeSeg2       |
+                                            (hcan->Init.Prescaler - 1U)));
+
+  /* Initialize the error code */
+  hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+  /* Initialize the CAN state */
+  hcan->State = HAL_CAN_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitializes the CAN peripheral registers to their default
+  *         reset values.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
+{
+  /* Check CAN handle */
+  if (hcan == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+
+  /* Stop the CAN module */
+  (void)HAL_CAN_Stop(hcan);
+
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+  if (hcan->MspDeInitCallback == NULL)
+  {
+    hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */
+  }
+
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  hcan->MspDeInitCallback(hcan);
+
+#else
+  /* DeInit the low level hardware: CLOCK, NVIC */
+  HAL_CAN_MspDeInit(hcan);
+#endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */
+
+  /* Reset the CAN peripheral */
+  SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
+
+  /* Reset the CAN ErrorCode */
+  hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+  /* Change CAN state */
+  hcan->State = HAL_CAN_STATE_RESET;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CAN MSP.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitializes the CAN MSP.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_MspDeInit could be implemented in the user file
+   */
+}
+
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+/**
+  * @brief  Register a CAN CallBack.
+  *         To be used instead of the weak predefined callback
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for CAN module
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID
+  *           @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID
+  *           @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID
+  *           @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID
+  *           @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID
+  *           @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID
+  *           @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID
+  *           @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID
+  *           @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
+  *           @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (hcan->State == HAL_CAN_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :
+        hcan->TxMailbox0CompleteCallback = pCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :
+        hcan->TxMailbox1CompleteCallback = pCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :
+        hcan->TxMailbox2CompleteCallback = pCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :
+        hcan->TxMailbox0AbortCallback = pCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :
+        hcan->TxMailbox1AbortCallback = pCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :
+        hcan->TxMailbox2AbortCallback = pCallback;
+        break;
+
+      case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :
+        hcan->RxFifo0MsgPendingCallback = pCallback;
+        break;
+
+      case HAL_CAN_RX_FIFO0_FULL_CB_ID :
+        hcan->RxFifo0FullCallback = pCallback;
+        break;
+
+      case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :
+        hcan->RxFifo1MsgPendingCallback = pCallback;
+        break;
+
+      case HAL_CAN_RX_FIFO1_FULL_CB_ID :
+        hcan->RxFifo1FullCallback = pCallback;
+        break;
+
+      case HAL_CAN_SLEEP_CB_ID :
+        hcan->SleepCallback = pCallback;
+        break;
+
+      case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :
+        hcan->WakeUpFromRxMsgCallback = pCallback;
+        break;
+
+      case HAL_CAN_ERROR_CB_ID :
+        hcan->ErrorCallback = pCallback;
+        break;
+
+      case HAL_CAN_MSPINIT_CB_ID :
+        hcan->MspInitCallback = pCallback;
+        break;
+
+      case HAL_CAN_MSPDEINIT_CB_ID :
+        hcan->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hcan->State == HAL_CAN_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_CAN_MSPINIT_CB_ID :
+        hcan->MspInitCallback = pCallback;
+        break;
+
+      case HAL_CAN_MSPDEINIT_CB_ID :
+        hcan->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a CAN CallBack.
+  *         CAN callback is redirected to the weak predefined callback
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for CAN module
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID
+  *           @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID
+  *           @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID
+  *           @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID
+  *           @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID
+  *           @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID
+  *           @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID
+  *           @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID
+  *           @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID
+  *           @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID
+  *           @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (hcan->State == HAL_CAN_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :
+        hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :
+        hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :
+        hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :
+        hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :
+        hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback;
+        break;
+
+      case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :
+        hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback;
+        break;
+
+      case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :
+        hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback;
+        break;
+
+      case HAL_CAN_RX_FIFO0_FULL_CB_ID :
+        hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback;
+        break;
+
+      case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :
+        hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback;
+        break;
+
+      case HAL_CAN_RX_FIFO1_FULL_CB_ID :
+        hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback;
+        break;
+
+      case HAL_CAN_SLEEP_CB_ID :
+        hcan->SleepCallback = HAL_CAN_SleepCallback;
+        break;
+
+      case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :
+        hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback;
+        break;
+
+      case HAL_CAN_ERROR_CB_ID :
+        hcan->ErrorCallback = HAL_CAN_ErrorCallback;
+        break;
+
+      case HAL_CAN_MSPINIT_CB_ID :
+        hcan->MspInitCallback = HAL_CAN_MspInit;
+        break;
+
+      case HAL_CAN_MSPDEINIT_CB_ID :
+        hcan->MspDeInitCallback = HAL_CAN_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hcan->State == HAL_CAN_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_CAN_MSPINIT_CB_ID :
+        hcan->MspInitCallback = HAL_CAN_MspInit;
+        break;
+
+      case HAL_CAN_MSPDEINIT_CB_ID :
+        hcan->MspDeInitCallback = HAL_CAN_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
+ *  @brief    Configuration functions.
+ *
+@verbatim
+  ==============================================================================
+              ##### Configuration functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_CAN_ConfigFilter            : Configure the CAN reception filters
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the CAN reception filter according to the specified
+  *         parameters in the CAN_FilterInitStruct.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  sFilterConfig pointer to a CAN_FilterTypeDef structure that
+  *         contains the filter configuration information.
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)
+{
+  uint32_t filternbrbitpos;
+  CAN_TypeDef *can_ip = hcan->Instance;
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Check the parameters */
+    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh));
+    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow));
+    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh));
+    assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow));
+    assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+    assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+    assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+    assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation));
+
+#if defined(CAN3)
+    /* Check the CAN instance */
+    if (hcan->Instance == CAN3)
+    {
+      /* CAN3 is single instance with 14 dedicated filters banks */
+
+      /* Check the parameters */
+      assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
+    }
+    else
+    {
+      /* CAN1 and CAN2 are dual instances with 28 common filters banks */
+      /* Select master instance to access the filter banks */
+      can_ip = CAN1;
+
+      /* Check the parameters */
+      assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));
+      assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
+    }
+#elif defined(CAN2)
+    /* CAN1 and CAN2 are dual instances with 28 common filters banks */
+    /* Select master instance to access the filter banks */
+    can_ip = CAN1;
+
+    /* Check the parameters */
+    assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));
+    assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
+#else
+    /* CAN1 is single instance with 14 dedicated filters banks */
+
+    /* Check the parameters */
+    assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
+#endif
+
+    /* Initialisation mode for the filter */
+    SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
+
+#if defined(CAN3)
+    /* Check the CAN instance */
+    if (can_ip == CAN1)
+    {
+      /* Select the start filter number of CAN2 slave instance */
+      CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
+      SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
+    }
+
+#elif defined(CAN2)
+    /* Select the start filter number of CAN2 slave instance */
+    CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
+    SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
+
+#endif
+    /* Convert filter number into bit position */
+    filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
+
+    /* Filter Deactivation */
+    CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
+
+    /* Filter Scale */
+    if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+    {
+      /* 16-bit scale for the filter */
+      CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
+
+      /* First 16-bit identifier and First 16-bit mask */
+      /* Or First 16-bit identifier and Second 16-bit identifier */
+      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
+        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
+        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+      /* Second 16-bit identifier and Second 16-bit mask */
+      /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
+        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
+    }
+
+    if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+    {
+      /* 32-bit scale for the filter */
+      SET_BIT(can_ip->FS1R, filternbrbitpos);
+
+      /* 32-bit identifier or First 32-bit identifier */
+      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
+        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
+        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+      /* 32-bit mask or Second 32-bit identifier */
+      can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
+        ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+        (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
+    }
+
+    /* Filter Mode */
+    if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+    {
+      /* Id/Mask mode for the filter*/
+      CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
+    }
+    else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+    {
+      /* Identifier list mode for the filter*/
+      SET_BIT(can_ip->FM1R, filternbrbitpos);
+    }
+
+    /* Filter FIFO assignment */
+    if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+    {
+      /* FIFO 0 assignation for the filter */
+      CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
+    }
+    else
+    {
+      /* FIFO 1 assignation for the filter */
+      SET_BIT(can_ip->FFA1R, filternbrbitpos);
+    }
+
+    /* Filter activation */
+    if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
+    {
+      SET_BIT(can_ip->FA1R, filternbrbitpos);
+    }
+
+    /* Leave the initialisation mode for the filter */
+    CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Functions_Group3 Control functions
+ *  @brief    Control functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_CAN_Start                    : Start the CAN module
+      (+) HAL_CAN_Stop                     : Stop the CAN module
+      (+) HAL_CAN_RequestSleep             : Request sleep mode entry.
+      (+) HAL_CAN_WakeUp                   : Wake up from sleep mode.
+      (+) HAL_CAN_IsSleepActive            : Check is sleep mode is active.
+      (+) HAL_CAN_AddTxMessage             : Add a message to the Tx mailboxes
+                                             and activate the corresponding
+                                             transmission request
+      (+) HAL_CAN_AbortTxRequest           : Abort transmission request
+      (+) HAL_CAN_GetTxMailboxesFreeLevel  : Return Tx mailboxes free level
+      (+) HAL_CAN_IsTxMessagePending       : Check if a transmission request is
+                                             pending on the selected Tx mailbox
+      (+) HAL_CAN_GetRxMessage             : Get a CAN frame from the Rx FIFO
+      (+) HAL_CAN_GetRxFifoFillLevel       : Return Rx FIFO fill level
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the CAN module.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
+{
+  uint32_t tickstart;
+
+  if (hcan->State == HAL_CAN_STATE_READY)
+  {
+    /* Change CAN peripheral state */
+    hcan->State = HAL_CAN_STATE_LISTENING;
+
+    /* Request leave initialisation */
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Wait the acknowledge */
+    while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+        /* Change CAN state */
+        hcan->State = HAL_CAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Reset the CAN ErrorCode */
+    hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Stop the CAN module and enable access to configuration registers.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
+{
+  uint32_t tickstart;
+
+  if (hcan->State == HAL_CAN_STATE_LISTENING)
+  {
+    /* Request initialisation */
+    SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    /* Wait the acknowledge */
+    while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
+    {
+      /* Check for the Timeout */
+      if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+      {
+        /* Update error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+        /* Change CAN state */
+        hcan->State = HAL_CAN_STATE_ERROR;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Exit from sleep mode */
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+    /* Change CAN peripheral state */
+    hcan->State = HAL_CAN_STATE_READY;
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Request the sleep mode (low power) entry.
+  *         When returning from this function, Sleep mode will be entered
+  *         as soon as the current CAN activity (transmission or reception
+  *         of a CAN frame) has been completed.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
+{
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Request Sleep mode */
+    SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    /* Return function status */
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Wake up from sleep mode.
+  *         When returning with HAL_OK status from this function, Sleep mode
+  *         is exited.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
+{
+  __IO uint32_t count = 0;
+  uint32_t timeout = 1000000U;
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Wake up request */
+    CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+    /* Wait sleep mode is exited */
+    do
+    {
+      /* Increment counter */
+      count++;
+
+      /* Check if timeout is reached */
+      if (count > timeout)
+      {
+        /* Update error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+        return HAL_ERROR;
+      }
+    }
+    while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Check is sleep mode is active.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval Status
+  *          - 0 : Sleep mode is not active.
+  *          - 1 : Sleep mode is active.
+  */
+uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)
+{
+  uint32_t status = 0U;
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Check Sleep mode */
+    if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
+    {
+      status = 1U;
+    }
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Add a message to the first free Tx mailbox and activate the
+  *         corresponding transmission request.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  pHeader pointer to a CAN_TxHeaderTypeDef structure.
+  * @param  aData array containing the payload of the Tx frame.
+  * @param  pTxMailbox pointer to a variable where the function will return
+  *         the TxMailbox used to store the Tx message.
+  *         This parameter can be a value of @arg CAN_Tx_Mailboxes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)
+{
+  uint32_t transmitmailbox;
+  HAL_CAN_StateTypeDef state = hcan->State;
+  uint32_t tsr = READ_REG(hcan->Instance->TSR);
+
+  /* Check the parameters */
+  assert_param(IS_CAN_IDTYPE(pHeader->IDE));
+  assert_param(IS_CAN_RTR(pHeader->RTR));
+  assert_param(IS_CAN_DLC(pHeader->DLC));
+  if (pHeader->IDE == CAN_ID_STD)
+  {
+    assert_param(IS_CAN_STDID(pHeader->StdId));
+  }
+  else
+  {
+    assert_param(IS_CAN_EXTID(pHeader->ExtId));
+  }
+  assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Check that all the Tx mailboxes are not full */
+    if (((tsr & CAN_TSR_TME0) != 0U) ||
+        ((tsr & CAN_TSR_TME1) != 0U) ||
+        ((tsr & CAN_TSR_TME2) != 0U))
+    {
+      /* Select an empty transmit mailbox */
+      transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
+
+      /* Check transmit mailbox value */
+      if (transmitmailbox > 2U)
+      {
+        /* Update error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_INTERNAL;
+
+        return HAL_ERROR;
+      }
+
+      /* Store the Tx mailbox */
+      *pTxMailbox = (uint32_t)1 << transmitmailbox;
+
+      /* Set up the Id */
+      if (pHeader->IDE == CAN_ID_STD)
+      {
+        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
+                                                           pHeader->RTR);
+      }
+      else
+      {
+        hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
+                                                           pHeader->IDE |
+                                                           pHeader->RTR);
+      }
+
+      /* Set up the DLC */
+      hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
+
+      /* Set up the Transmit Global Time mode */
+      if (pHeader->TransmitGlobalTime == ENABLE)
+      {
+        SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
+      }
+
+      /* Set up the data field */
+      WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
+                ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
+                ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
+                ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
+                ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
+      WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
+                ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) |
+                ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
+                ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
+                ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
+
+      /* Request transmission */
+      SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
+
+      /* Return function status */
+      return HAL_OK;
+    }
+    else
+    {
+      /* Update error code */
+      hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+      return HAL_ERROR;
+    }
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Abort transmission requests
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  TxMailboxes List of the Tx Mailboxes to abort.
+  *         This parameter can be any combination of @arg CAN_Tx_Mailboxes.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
+{
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Check Tx Mailbox 0 */
+    if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U)
+    {
+      /* Add cancellation request for Tx Mailbox 0 */
+      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0);
+    }
+
+    /* Check Tx Mailbox 1 */
+    if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U)
+    {
+      /* Add cancellation request for Tx Mailbox 1 */
+      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1);
+    }
+
+    /* Check Tx Mailbox 2 */
+    if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U)
+    {
+      /* Add cancellation request for Tx Mailbox 2 */
+      SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Return Tx Mailboxes free level: number of free Tx Mailboxes.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval Number of free Tx Mailboxes.
+  */
+uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)
+{
+  uint32_t freelevel = 0U;
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Check Tx Mailbox 0 status */
+    if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U)
+    {
+      freelevel++;
+    }
+
+    /* Check Tx Mailbox 1 status */
+    if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U)
+    {
+      freelevel++;
+    }
+
+    /* Check Tx Mailbox 2 status */
+    if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U)
+    {
+      freelevel++;
+    }
+  }
+
+  /* Return Tx Mailboxes free level */
+  return freelevel;
+}
+
+/**
+  * @brief  Check if a transmission request is pending on the selected Tx
+  *         Mailboxes.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  TxMailboxes List of Tx Mailboxes to check.
+  *         This parameter can be any combination of @arg CAN_Tx_Mailboxes.
+  * @retval Status
+  *          - 0 : No pending transmission request on any selected Tx Mailboxes.
+  *          - 1 : Pending transmission request on at least one of the selected
+  *                Tx Mailbox.
+  */
+uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
+{
+  uint32_t status = 0U;
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Check pending transmission request on the selected Tx Mailboxes */
+    if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos))
+    {
+      status = 1U;
+    }
+  }
+
+  /* Return status */
+  return status;
+}
+
+/**
+  * @brief  Return timestamp of Tx message sent, if time triggered communication
+            mode is enabled.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  TxMailbox Tx Mailbox where the timestamp of message sent will be
+  *         read.
+  *         This parameter can be one value of @arg CAN_Tx_Mailboxes.
+  * @retval Timestamp of message sent from Tx Mailbox.
+  */
+uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
+{
+  uint32_t timestamp = 0U;
+  uint32_t transmitmailbox;
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_CAN_TX_MAILBOX(TxMailbox));
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Select the Tx mailbox */
+    transmitmailbox = POSITION_VAL(TxMailbox);
+
+    /* Get timestamp */
+    timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos;
+  }
+
+  /* Return the timestamp */
+  return timestamp;
+}
+
+/**
+  * @brief  Get an CAN frame from the Rx FIFO zone into the message RAM.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  RxFifo Fifo number of the received message to be read.
+  *         This parameter can be a value of @arg CAN_receive_FIFO_number.
+  * @param  pHeader pointer to a CAN_RxHeaderTypeDef structure where the header
+  *         of the Rx frame will be stored.
+  * @param  aData array where the payload of the Rx frame will be stored.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
+{
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  assert_param(IS_CAN_RX_FIFO(RxFifo));
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Check the Rx FIFO */
+    if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
+    {
+      /* Check that the Rx FIFO 0 is not empty */
+      if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
+      {
+        /* Update error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+    }
+    else /* Rx element is assigned to Rx FIFO 1 */
+    {
+      /* Check that the Rx FIFO 1 is not empty */
+      if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
+      {
+        /* Update error code */
+        hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Get the header */
+    pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
+    if (pHeader->IDE == CAN_ID_STD)
+    {
+      pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
+    }
+    else
+    {
+      pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
+    }
+    pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
+    pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
+    pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
+    pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
+
+    /* Get the data */
+    aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
+    aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
+    aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
+    aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
+    aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
+    aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
+    aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
+    aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
+
+    /* Release the FIFO */
+    if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
+    {
+      /* Release RX FIFO 0 */
+      SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
+    }
+    else /* Rx element is assigned to Rx FIFO 1 */
+    {
+      /* Release RX FIFO 1 */
+      SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Return Rx FIFO fill level.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  RxFifo Rx FIFO.
+  *         This parameter can be a value of @arg CAN_receive_FIFO_number.
+  * @retval Number of messages available in Rx FIFO.
+  */
+uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
+{
+  uint32_t filllevel = 0U;
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_CAN_RX_FIFO(RxFifo));
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    if (RxFifo == CAN_RX_FIFO0)
+    {
+      filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0;
+    }
+    else /* RxFifo == CAN_RX_FIFO1 */
+    {
+      filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1;
+    }
+  }
+
+  /* Return Rx FIFO fill level */
+  return filllevel;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
+ *  @brief    Interrupts management
+ *
+@verbatim
+  ==============================================================================
+                       ##### Interrupts management #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) HAL_CAN_ActivateNotification      : Enable interrupts
+      (+) HAL_CAN_DeactivateNotification    : Disable interrupts
+      (+) HAL_CAN_IRQHandler                : Handles CAN interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable interrupts.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  ActiveITs indicates which interrupts will be enabled.
+  *         This parameter can be any combination of @arg CAN_Interrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
+{
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_CAN_IT(ActiveITs));
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Enable the selected interrupts */
+    __HAL_CAN_ENABLE_IT(hcan, ActiveITs);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable interrupts.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @param  InactiveITs indicates which interrupts will be disabled.
+  *         This parameter can be any combination of @arg CAN_Interrupts.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs)
+{
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  /* Check function parameters */
+  assert_param(IS_CAN_IT(InactiveITs));
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Disable the selected interrupts */
+    __HAL_CAN_DISABLE_IT(hcan, InactiveITs);
+
+    /* Return function status */
+    return HAL_OK;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handles CAN interrupt request
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
+{
+  uint32_t errorcode = HAL_CAN_ERROR_NONE;
+  uint32_t interrupts = READ_REG(hcan->Instance->IER);
+  uint32_t msrflags = READ_REG(hcan->Instance->MSR);
+  uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
+  uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
+  uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
+  uint32_t esrflags = READ_REG(hcan->Instance->ESR);
+
+  /* Transmit Mailbox empty interrupt management *****************************/
+  if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
+  {
+    /* Transmit Mailbox 0 management *****************************************/
+    if ((tsrflags & CAN_TSR_RQCP0) != 0U)
+    {
+      /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
+
+      if ((tsrflags & CAN_TSR_TXOK0) != 0U)
+      {
+        /* Transmission Mailbox 0 complete callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hcan->TxMailbox0CompleteCallback(hcan);
+#else
+        /* Call weak (surcharged) callback */
+        HAL_CAN_TxMailbox0CompleteCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        if ((tsrflags & CAN_TSR_ALST0) != 0U)
+        {
+          /* Update error code */
+          errorcode |= HAL_CAN_ERROR_TX_ALST0;
+        }
+        else if ((tsrflags & CAN_TSR_TERR0) != 0U)
+        {
+          /* Update error code */
+          errorcode |= HAL_CAN_ERROR_TX_TERR0;
+        }
+        else
+        {
+          /* Transmission Mailbox 0 abort callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+          /* Call registered callback*/
+          hcan->TxMailbox0AbortCallback(hcan);
+#else
+          /* Call weak (surcharged) callback */
+          HAL_CAN_TxMailbox0AbortCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+        }
+      }
+    }
+
+    /* Transmit Mailbox 1 management *****************************************/
+    if ((tsrflags & CAN_TSR_RQCP1) != 0U)
+    {
+      /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
+
+      if ((tsrflags & CAN_TSR_TXOK1) != 0U)
+      {
+        /* Transmission Mailbox 1 complete callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hcan->TxMailbox1CompleteCallback(hcan);
+#else
+        /* Call weak (surcharged) callback */
+        HAL_CAN_TxMailbox1CompleteCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        if ((tsrflags & CAN_TSR_ALST1) != 0U)
+        {
+          /* Update error code */
+          errorcode |= HAL_CAN_ERROR_TX_ALST1;
+        }
+        else if ((tsrflags & CAN_TSR_TERR1) != 0U)
+        {
+          /* Update error code */
+          errorcode |= HAL_CAN_ERROR_TX_TERR1;
+        }
+        else
+        {
+          /* Transmission Mailbox 1 abort callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+          /* Call registered callback*/
+          hcan->TxMailbox1AbortCallback(hcan);
+#else
+          /* Call weak (surcharged) callback */
+          HAL_CAN_TxMailbox1AbortCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+        }
+      }
+    }
+
+    /* Transmit Mailbox 2 management *****************************************/
+    if ((tsrflags & CAN_TSR_RQCP2) != 0U)
+    {
+      /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
+
+      if ((tsrflags & CAN_TSR_TXOK2) != 0U)
+      {
+        /* Transmission Mailbox 2 complete callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+        /* Call registered callback*/
+        hcan->TxMailbox2CompleteCallback(hcan);
+#else
+        /* Call weak (surcharged) callback */
+        HAL_CAN_TxMailbox2CompleteCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        if ((tsrflags & CAN_TSR_ALST2) != 0U)
+        {
+          /* Update error code */
+          errorcode |= HAL_CAN_ERROR_TX_ALST2;
+        }
+        else if ((tsrflags & CAN_TSR_TERR2) != 0U)
+        {
+          /* Update error code */
+          errorcode |= HAL_CAN_ERROR_TX_TERR2;
+        }
+        else
+        {
+          /* Transmission Mailbox 2 abort callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+          /* Call registered callback*/
+          hcan->TxMailbox2AbortCallback(hcan);
+#else
+          /* Call weak (surcharged) callback */
+          HAL_CAN_TxMailbox2AbortCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+        }
+      }
+    }
+  }
+
+  /* Receive FIFO 0 overrun interrupt management *****************************/
+  if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
+  {
+    if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
+    {
+      /* Set CAN error code to Rx Fifo 0 overrun error */
+      errorcode |= HAL_CAN_ERROR_RX_FOV0;
+
+      /* Clear FIFO0 Overrun Flag */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+    }
+  }
+
+  /* Receive FIFO 0 full interrupt management ********************************/
+  if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
+  {
+    if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
+    {
+      /* Clear FIFO 0 full Flag */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
+
+      /* Receive FIFO 0 full Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hcan->RxFifo0FullCallback(hcan);
+#else
+      /* Call weak (surcharged) callback */
+      HAL_CAN_RxFifo0FullCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Receive FIFO 0 message pending interrupt management *********************/
+  if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
+  {
+    /* Check if message is still pending */
+    if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
+    {
+      /* Receive FIFO 0 message pending Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hcan->RxFifo0MsgPendingCallback(hcan);
+#else
+      /* Call weak (surcharged) callback */
+      HAL_CAN_RxFifo0MsgPendingCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Receive FIFO 1 overrun interrupt management *****************************/
+  if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
+  {
+    if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
+    {
+      /* Set CAN error code to Rx Fifo 1 overrun error */
+      errorcode |= HAL_CAN_ERROR_RX_FOV1;
+
+      /* Clear FIFO1 Overrun Flag */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+    }
+  }
+
+  /* Receive FIFO 1 full interrupt management ********************************/
+  if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
+  {
+    if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
+    {
+      /* Clear FIFO 1 full Flag */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
+
+      /* Receive FIFO 1 full Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hcan->RxFifo1FullCallback(hcan);
+#else
+      /* Call weak (surcharged) callback */
+      HAL_CAN_RxFifo1FullCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Receive FIFO 1 message pending interrupt management *********************/
+  if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
+  {
+    /* Check if message is still pending */
+    if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
+    {
+      /* Receive FIFO 1 message pending Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hcan->RxFifo1MsgPendingCallback(hcan);
+#else
+      /* Call weak (surcharged) callback */
+      HAL_CAN_RxFifo1MsgPendingCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Sleep interrupt management *********************************************/
+  if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
+  {
+    if ((msrflags & CAN_MSR_SLAKI) != 0U)
+    {
+      /* Clear Sleep interrupt Flag */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
+
+      /* Sleep Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hcan->SleepCallback(hcan);
+#else
+      /* Call weak (surcharged) callback */
+      HAL_CAN_SleepCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* WakeUp interrupt management *********************************************/
+  if ((interrupts & CAN_IT_WAKEUP) != 0U)
+  {
+    if ((msrflags & CAN_MSR_WKUI) != 0U)
+    {
+      /* Clear WakeUp Flag */
+      __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
+
+      /* WakeUp Callback */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+      /* Call registered callback*/
+      hcan->WakeUpFromRxMsgCallback(hcan);
+#else
+      /* Call weak (surcharged) callback */
+      HAL_CAN_WakeUpFromRxMsgCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Error interrupts management *********************************************/
+  if ((interrupts & CAN_IT_ERROR) != 0U)
+  {
+    if ((msrflags & CAN_MSR_ERRI) != 0U)
+    {
+      /* Check Error Warning Flag */
+      if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
+          ((esrflags & CAN_ESR_EWGF) != 0U))
+      {
+        /* Set CAN error code to Error Warning */
+        errorcode |= HAL_CAN_ERROR_EWG;
+
+        /* No need for clear of Error Warning Flag as read-only */
+      }
+
+      /* Check Error Passive Flag */
+      if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
+          ((esrflags & CAN_ESR_EPVF) != 0U))
+      {
+        /* Set CAN error code to Error Passive */
+        errorcode |= HAL_CAN_ERROR_EPV;
+
+        /* No need for clear of Error Passive Flag as read-only */
+      }
+
+      /* Check Bus-off Flag */
+      if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
+          ((esrflags & CAN_ESR_BOFF) != 0U))
+      {
+        /* Set CAN error code to Bus-Off */
+        errorcode |= HAL_CAN_ERROR_BOF;
+
+        /* No need for clear of Error Bus-Off as read-only */
+      }
+
+      /* Check Last Error Code Flag */
+      if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
+          ((esrflags & CAN_ESR_LEC) != 0U))
+      {
+        switch (esrflags & CAN_ESR_LEC)
+        {
+          case (CAN_ESR_LEC_0):
+            /* Set CAN error code to Stuff error */
+            errorcode |= HAL_CAN_ERROR_STF;
+            break;
+          case (CAN_ESR_LEC_1):
+            /* Set CAN error code to Form error */
+            errorcode |= HAL_CAN_ERROR_FOR;
+            break;
+          case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+            /* Set CAN error code to Acknowledgement error */
+            errorcode |= HAL_CAN_ERROR_ACK;
+            break;
+          case (CAN_ESR_LEC_2):
+            /* Set CAN error code to Bit recessive error */
+            errorcode |= HAL_CAN_ERROR_BR;
+            break;
+          case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+            /* Set CAN error code to Bit Dominant error */
+            errorcode |= HAL_CAN_ERROR_BD;
+            break;
+          case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+            /* Set CAN error code to CRC error */
+            errorcode |= HAL_CAN_ERROR_CRC;
+            break;
+          default:
+            break;
+        }
+
+        /* Clear Last error code Flag */
+        CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
+      }
+    }
+
+    /* Clear ERRI Flag */
+    __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
+  }
+
+  /* Call the Error call Back in case of Errors */
+  if (errorcode != HAL_CAN_ERROR_NONE)
+  {
+    /* Update error code in handle */
+    hcan->ErrorCode |= errorcode;
+
+    /* Call Error callback function */
+#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
+    /* Call registered callback*/
+    hcan->ErrorCallback(hcan);
+#else
+    /* Call weak (surcharged) callback */
+    HAL_CAN_ErrorCallback(hcan);
+#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Functions_Group5 Callback functions
+ *  @brief   CAN Callback functions
+ *
+@verbatim
+  ==============================================================================
+                          ##### Callback functions #####
+  ==============================================================================
+    [..]
+    This subsection provides the following callback functions:
+      (+) HAL_CAN_TxMailbox0CompleteCallback
+      (+) HAL_CAN_TxMailbox1CompleteCallback
+      (+) HAL_CAN_TxMailbox2CompleteCallback
+      (+) HAL_CAN_TxMailbox0AbortCallback
+      (+) HAL_CAN_TxMailbox1AbortCallback
+      (+) HAL_CAN_TxMailbox2AbortCallback
+      (+) HAL_CAN_RxFifo0MsgPendingCallback
+      (+) HAL_CAN_RxFifo0FullCallback
+      (+) HAL_CAN_RxFifo1MsgPendingCallback
+      (+) HAL_CAN_RxFifo1FullCallback
+      (+) HAL_CAN_SleepCallback
+      (+) HAL_CAN_WakeUpFromRxMsgCallback
+      (+) HAL_CAN_ErrorCallback
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmission Mailbox 0 complete callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
+            user file
+   */
+}
+
+/**
+  * @brief  Transmission Mailbox 1 complete callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
+            user file
+   */
+}
+
+/**
+  * @brief  Transmission Mailbox 2 complete callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
+            user file
+   */
+}
+
+/**
+  * @brief  Transmission Mailbox 0 Cancellation callback.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
+            user file
+   */
+}
+
+/**
+  * @brief  Transmission Mailbox 1 Cancellation callback.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
+            user file
+   */
+}
+
+/**
+  * @brief  Transmission Mailbox 2 Cancellation callback.
+  * @param  hcan pointer to an CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
+            user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 0 message pending callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the
+            user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 0 full callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_RxFifo0FullCallback could be implemented in the user
+            file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 1 message pending callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
+            user file
+   */
+}
+
+/**
+  * @brief  Rx FIFO 1 full callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_RxFifo1FullCallback could be implemented in the user
+            file
+   */
+}
+
+/**
+  * @brief  Sleep callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_SleepCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  WakeUp from Rx message callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
+            user file
+   */
+}
+
+/**
+  * @brief  Error CAN callback.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval None
+  */
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcan);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_CAN_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
+ *  @brief   CAN Peripheral State functions
+ *
+@verbatim
+  ==============================================================================
+            ##### Peripheral State and Error functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) HAL_CAN_GetState()  : Return the CAN state.
+      (+) HAL_CAN_GetError()  : Return the CAN error codes if any.
+      (+) HAL_CAN_ResetError(): Reset the CAN error codes if any.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the CAN state.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL state
+  */
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)
+{
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Check sleep mode acknowledge flag */
+    if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
+    {
+      /* Sleep mode is active */
+      state = HAL_CAN_STATE_SLEEP_ACTIVE;
+    }
+    /* Check sleep mode request flag */
+    else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U)
+    {
+      /* Sleep mode request is pending */
+      state = HAL_CAN_STATE_SLEEP_PENDING;
+    }
+    else
+    {
+      /* Neither sleep mode request nor sleep mode acknowledge */
+    }
+  }
+
+  /* Return CAN state */
+  return state;
+}
+
+/**
+  * @brief  Return the CAN error code.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval CAN Error Code
+  */
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
+{
+  /* Return CAN error code */
+  return hcan->ErrorCode;
+}
+
+/**
+  * @brief  Reset the CAN error code.
+  * @param  hcan pointer to a CAN_HandleTypeDef structure that contains
+  *         the configuration information for the specified CAN.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_CAN_StateTypeDef state = hcan->State;
+
+  if ((state == HAL_CAN_STATE_READY) ||
+      (state == HAL_CAN_STATE_LISTENING))
+  {
+    /* Reset CAN error code */
+    hcan->ErrorCode = 0U;
+  }
+  else
+  {
+    /* Update error code */
+    hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+    status = HAL_ERROR;
+  }
+
+  /* Return the status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+#endif /* CAN1 */
+
+/**
+  * @}
+  */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c
index 98515c5..5970852 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c
@@ -1,502 +1,502 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_cortex.c
-  * @author  MCD Application Team
-  * @brief   CORTEX HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the CORTEX:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions 
-  *
-  @verbatim  
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-
-    [..]  
-    *** How to configure Interrupts using CORTEX HAL driver ***
-    ===========================================================
-    [..]     
-    This section provides functions allowing to configure the NVIC interrupts (IRQ).
-    The Cortex-M4 exceptions are managed by CMSIS functions.
-   
-    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
-        function according to the following table.
-    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). 
-    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
-    (#) please refer to programming manual for details in how to configure priority. 
-      
-     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. 
-         The pending IRQ priority will be managed only by the sub priority.
-   
-     -@- IRQ priority order (sorted by highest to lowest priority):
-        (+@) Lowest preemption priority
-        (+@) Lowest sub priority
-        (+@) Lowest hardware priority (IRQ number)
- 
-    [..]  
-    *** How to configure Systick using CORTEX HAL driver ***
-    ========================================================
-    [..]
-    Setup SysTick Timer for time base.
-           
-   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
-       is a CMSIS function that:
-        (++) Configures the SysTick Reload register with value passed as function parameter.
-        (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
-        (++) Resets the SysTick Counter register.
-        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
-        (++) Enables the SysTick Interrupt.
-        (++) Starts the SysTick Counter.
-    
-   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
-       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
-       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
-       inside the stm32f4xx_hal_cortex.h file.
-
-   (+) You can change the SysTick IRQ priority by calling the
-       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function 
-       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
-
-   (+) To adjust the SysTick time base, use the following formula:
-                            
-       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
-       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
-       (++) Reload Value should not exceed 0xFFFFFF
-   
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CORTEX CORTEX
-  * @brief CORTEX HAL module driver
-  * @{
-  */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
-  * @{
-  */
-
-
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]
-      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
-      Systick functionalities 
-
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Sets the priority grouping field (preemption priority and subpriority)
-  *         using the required unlock sequence.
-  * @param  PriorityGroup The priority grouping bits length. 
-  *         This parameter can be one of the following values:
-  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
-  *                                    4 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
-  *                                    3 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
-  *                                    2 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
-  *                                    1 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
-  *                                    0 bits for subpriority
-  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
-  *         The pending IRQ priority will be managed only by the subpriority. 
-  * @retval None
-  */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-  
-  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
-  NVIC_SetPriorityGrouping(PriorityGroup);
-}
-
-/**
-  * @brief  Sets the priority of an interrupt.
-  * @param  IRQn External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
-  * @param  PreemptPriority The preemption priority for the IRQn channel.
-  *         This parameter can be a value between 0 and 15
-  *         A lower priority value indicates a higher priority 
-  * @param  SubPriority the subpriority level for the IRQ channel.
-  *         This parameter can be a value between 0 and 15
-  *         A lower priority value indicates a higher priority.          
-  * @retval None
-  */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{ 
-  uint32_t prioritygroup = 0x00U;
-  
-  /* Check the parameters */
-  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-  
-  prioritygroup = NVIC_GetPriorityGrouping();
-  
-  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
-}
-
-/**
-  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
-  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
-  *         function should be called before. 
-  * @param  IRQn External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Enable interrupt */
-  NVIC_EnableIRQ(IRQn);
-}
-
-/**
-  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
-  * @param  IRQn External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Disable interrupt */
-  NVIC_DisableIRQ(IRQn);
-}
-
-/**
-  * @brief  Initiates a system reset request to reset the MCU.
-  * @retval None
-  */
-void HAL_NVIC_SystemReset(void)
-{
-  /* System Reset */
-  NVIC_SystemReset();
-}
-
-/**
-  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-  *         Counter is in free running mode to generate periodic interrupts.
-  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
-  * @retval status:  - 0  Function succeeded.
-  *                  - 1  Function failed.
-  */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
-   return SysTick_Config(TicksNumb);
-}
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
- *  @brief   Cortex control functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================  
-    [..]
-      This subsection provides a set of functions allowing to control the CORTEX
-      (NVIC, SYSTICK, MPU) functionalities. 
- 
-      
-@endverbatim
-  * @{
-  */
-
-#if (__MPU_PRESENT == 1U)
-/**
-  * @brief  Disables the MPU
-  * @retval None
-  */
-void HAL_MPU_Disable(void)
-{
-  /* Make sure outstanding transfers are done */
-  __DMB();
-
-  /* Disable fault exceptions */
-  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
-  
-  /* Disable the MPU and clear the control register*/
-  MPU->CTRL = 0U;
-}
-
-/**
-  * @brief  Enable the MPU.
-  * @param  MPU_Control Specifies the control mode of the MPU during hard fault, 
-  *          NMI, FAULTMASK and privileged access to the default memory 
-  *          This parameter can be one of the following values:
-  *            @arg MPU_HFNMI_PRIVDEF_NONE
-  *            @arg MPU_HARDFAULT_NMI
-  *            @arg MPU_PRIVILEGED_DEFAULT
-  *            @arg MPU_HFNMI_PRIVDEF
-  * @retval None
-  */
-void HAL_MPU_Enable(uint32_t MPU_Control)
-{
-  /* Enable the MPU */
-  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
-  
-  /* Enable fault exceptions */
-  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
-  
-  /* Ensure MPU setting take effects */
-  __DSB();
-  __ISB();
-}
-
-/**
-  * @brief  Initializes and configures the Region and the memory to be protected.
-  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
-  *                the initialization and configuration information.
-  * @retval None
-  */
-void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
-{
-  /* Check the parameters */
-  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
-  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
-
-  /* Set the Region number */
-  MPU->RNR = MPU_Init->Number;
-
-  if ((MPU_Init->Enable) != RESET)
-  {
-    /* Check the parameters */
-    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
-    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
-    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
-    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
-    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
-    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
-    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
-    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
-    
-    MPU->RBAR = MPU_Init->BaseAddress;
-    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
-                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
-                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
-                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
-                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
-                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
-                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
-                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
-                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
-  }
-  else
-  {
-    MPU->RBAR = 0x00U;
-    MPU->RASR = 0x00U;
-  }
-}
-#endif /* __MPU_PRESENT */
-
-/**
-  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
-  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
-  */
-uint32_t HAL_NVIC_GetPriorityGrouping(void)
-{
-  /* Get the PRIGROUP[10:8] field value */
-  return NVIC_GetPriorityGrouping();
-}
-
-/**
-  * @brief  Gets the priority of an interrupt.
-  * @param  IRQn External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
-  * @param   PriorityGroup the priority grouping bits length.
-  *         This parameter can be one of the following values:
-  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
-  *                                      4 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
-  *                                      3 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
-  *                                      2 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
-  *                                      1 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
-  *                                      0 bits for subpriority
-  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
-  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
-  * @retval None
-  */
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
- /* Get priority for Cortex-M system or device specific interrupts */
-  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
-}
-
-/**
-  * @brief  Sets Pending bit of an external interrupt.
-  * @param  IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Set interrupt pending */
-  NVIC_SetPendingIRQ(IRQn);
-}
-
-/**
-  * @brief  Gets Pending Interrupt (reads the pending register in the NVIC 
-  *         and returns the pending bit for the specified interrupt).
-  * @param  IRQn External interrupt number.
-  *          This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
-  * @retval status: - 0  Interrupt status is not pending.
-  *                 - 1  Interrupt status is pending.
-  */
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Return 1 if pending else 0 */
-  return NVIC_GetPendingIRQ(IRQn);
-}
-
-/**
-  * @brief  Clears the pending bit of an external interrupt.
-  * @param  IRQn External interrupt number.
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Clear pending interrupt */
-  NVIC_ClearPendingIRQ(IRQn);
-}
-
-/**
-  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
-  * @param IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
-  * @retval status: - 0  Interrupt status is not pending.
-  *                 - 1  Interrupt status is pending.
-  */
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
-  
-  /* Return 1 if active else 0 */
-  return NVIC_GetActive(IRQn);
-}
-
-/**
-  * @brief  Configures the SysTick clock source.
-  * @param  CLKSource specifies the SysTick clock source.
-  *          This parameter can be one of the following values:
-  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
-  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
-  * @retval None
-  */
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
-  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
-  {
-    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
-  }
-  else
-  {
-    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
-  }
-}
-
-/**
-  * @brief  This function handles SYSTICK interrupt request.
-  * @retval None
-  */
-void HAL_SYSTICK_IRQHandler(void)
-{
-  HAL_SYSTICK_Callback();
-}
-
-/**
-  * @brief  SYSTICK callback.
-  * @retval None
-  */
-__weak void HAL_SYSTICK_Callback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SYSTICK_Callback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_cortex.c
+  * @author  MCD Application Team
+  * @brief   CORTEX HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the CORTEX:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions 
+  *
+  @verbatim  
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+
+    [..]  
+    *** How to configure Interrupts using CORTEX HAL driver ***
+    ===========================================================
+    [..]     
+    This section provides functions allowing to configure the NVIC interrupts (IRQ).
+    The Cortex-M4 exceptions are managed by CMSIS functions.
+   
+    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
+        function according to the following table.
+    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). 
+    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+    (#) please refer to programming manual for details in how to configure priority. 
+      
+     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ preemption is no more possible. 
+         The pending IRQ priority will be managed only by the sub priority.
+   
+     -@- IRQ priority order (sorted by highest to lowest priority):
+        (+@) Lowest preemption priority
+        (+@) Lowest sub priority
+        (+@) Lowest hardware priority (IRQ number)
+ 
+    [..]  
+    *** How to configure Systick using CORTEX HAL driver ***
+    ========================================================
+    [..]
+    Setup SysTick Timer for time base.
+           
+   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+       is a CMSIS function that:
+        (++) Configures the SysTick Reload register with value passed as function parameter.
+        (++) Configures the SysTick IRQ priority to the lowest value 0x0F.
+        (++) Resets the SysTick Counter register.
+        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+        (++) Enables the SysTick Interrupt.
+        (++) Starts the SysTick Counter.
+    
+   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+       inside the stm32f4xx_hal_cortex.h file.
+
+   (+) You can change the SysTick IRQ priority by calling the
+       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function 
+       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+   (+) To adjust the SysTick time base, use the following formula:
+                            
+       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+       (++) Reload Value should not exceed 0xFFFFFF
+   
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX CORTEX
+  * @brief CORTEX HAL module driver
+  * @{
+  */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]
+      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+      Systick functionalities 
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Sets the priority grouping field (preemption priority and subpriority)
+  *         using the required unlock sequence.
+  * @param  PriorityGroup The priority grouping bits length. 
+  *         This parameter can be one of the following values:
+  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+  *                                    4 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+  *                                    3 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+  *                                    2 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+  *                                    1 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+  *                                    0 bits for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
+  *         The pending IRQ priority will be managed only by the subpriority. 
+  * @retval None
+  */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+  
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+  * @brief  Sets the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+  * @param  PreemptPriority The preemption priority for the IRQn channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority 
+  * @param  SubPriority the subpriority level for the IRQ channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority.          
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{ 
+  uint32_t prioritygroup = 0x00U;
+  
+  /* Check the parameters */
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+  
+  prioritygroup = NVIC_GetPriorityGrouping();
+  
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before. 
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+}
+
+/**
+  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Disable interrupt */
+  NVIC_DisableIRQ(IRQn);
+}
+
+/**
+  * @brief  Initiates a system reset request to reset the MCU.
+  * @retval None
+  */
+void HAL_NVIC_SystemReset(void)
+{
+  /* System Reset */
+  NVIC_SystemReset();
+}
+
+/**
+  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+  *         Counter is in free running mode to generate periodic interrupts.
+  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
+  * @retval status:  - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+   return SysTick_Config(TicksNumb);
+}
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   Cortex control functions 
+ *
+@verbatim   
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================  
+    [..]
+      This subsection provides a set of functions allowing to control the CORTEX
+      (NVIC, SYSTICK, MPU) functionalities. 
+ 
+      
+@endverbatim
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1U)
+/**
+  * @brief  Disables the MPU
+  * @retval None
+  */
+void HAL_MPU_Disable(void)
+{
+  /* Make sure outstanding transfers are done */
+  __DMB();
+
+  /* Disable fault exceptions */
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+  
+  /* Disable the MPU and clear the control register*/
+  MPU->CTRL = 0U;
+}
+
+/**
+  * @brief  Enable the MPU.
+  * @param  MPU_Control Specifies the control mode of the MPU during hard fault, 
+  *          NMI, FAULTMASK and privileged access to the default memory 
+  *          This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+  /* Enable the MPU */
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+  
+  /* Enable fault exceptions */
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+  
+  /* Ensure MPU setting take effects */
+  __DSB();
+  __ISB();
+}
+
+/**
+  * @brief  Initializes and configures the Region and the memory to be protected.
+  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+  /* Set the Region number */
+  MPU->RNR = MPU_Init->Number;
+
+  if ((MPU_Init->Enable) != RESET)
+  {
+    /* Check the parameters */
+    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+    
+    MPU->RBAR = MPU_Init->BaseAddress;
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec             << MPU_RASR_XN_Pos)   |
+                ((uint32_t)MPU_Init->AccessPermission        << MPU_RASR_AP_Pos)   |
+                ((uint32_t)MPU_Init->TypeExtField            << MPU_RASR_TEX_Pos)  |
+                ((uint32_t)MPU_Init->IsShareable             << MPU_RASR_S_Pos)    |
+                ((uint32_t)MPU_Init->IsCacheable             << MPU_RASR_C_Pos)    |
+                ((uint32_t)MPU_Init->IsBufferable            << MPU_RASR_B_Pos)    |
+                ((uint32_t)MPU_Init->SubRegionDisable        << MPU_RASR_SRD_Pos)  |
+                ((uint32_t)MPU_Init->Size                    << MPU_RASR_SIZE_Pos) |
+                ((uint32_t)MPU_Init->Enable                  << MPU_RASR_ENABLE_Pos);
+  }
+  else
+  {
+    MPU->RBAR = 0x00U;
+    MPU->RASR = 0x00U;
+  }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
+  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+  */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+  /* Get the PRIGROUP[10:8] field value */
+  return NVIC_GetPriorityGrouping();
+}
+
+/**
+  * @brief  Gets the priority of an interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+  * @param   PriorityGroup the priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
+  *                                      4 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
+  *                                      3 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
+  *                                      2 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
+  *                                      1 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
+  *                                      0 bits for subpriority
+  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
+  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
+  * @retval None
+  */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+  * @brief  Sets Pending bit of an external interrupt.
+  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Set interrupt pending */
+  NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Gets Pending Interrupt (reads the pending register in the NVIC 
+  *         and returns the pending bit for the specified interrupt).
+  * @param  IRQn External interrupt number.
+  *          This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Return 1 if pending else 0 */
+  return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Clears the pending bit of an external interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Clear pending interrupt */
+  NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
+  * @param IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Return 1 if active else 0 */
+  return NVIC_GetActive(IRQn);
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  CLKSource specifies the SysTick clock source.
+  *          This parameter can be one of the following values:
+  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+  {
+    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+  }
+}
+
+/**
+  * @brief  This function handles SYSTICK interrupt request.
+  * @retval None
+  */
+void HAL_SYSTICK_IRQHandler(void)
+{
+  HAL_SYSTICK_Callback();
+}
+
+/**
+  * @brief  SYSTICK callback.
+  * @retval None
+  */
+__weak void HAL_SYSTICK_Callback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_SYSTICK_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c
index 3dbb477..2bc5f27 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c
@@ -1,1305 +1,1305 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_dma.c
-  * @author  MCD Application Team
-  * @brief   DMA HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Direct Memory Access (DMA) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and errors functions
-  @verbatim     
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-   (#) Enable and configure the peripheral to be connected to the DMA Stream
-       (except for internal SRAM/FLASH memories: no initialization is 
-       necessary) please refer to Reference manual for connection between peripherals
-       and DMA requests.
-
-   (#) For a given Stream, program the required configuration through the following parameters:
-       Transfer Direction, Source and Destination data formats, 
-       Circular, Normal or peripheral flow control mode, Stream Priority level, 
-       Source and Destination Increment mode, FIFO mode and its Threshold (if needed), 
-       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
-
-   -@-   Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
-         __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
-
-     *** Polling mode IO operation ***
-     =================================
-    [..]
-          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source 
-              address and destination address and the Length of data to be transferred.
-          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this  
-              case a fixed Timeout can be configured by User depending from his application.
-          (+) Use HAL_DMA_Abort() function to abort the current transfer.
-
-     *** Interrupt mode IO operation ***
-     ===================================
-    [..]
-          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
-          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() 
-          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of  
-              Source address and destination address and the Length of data to be transferred. In this 
-              case the DMA interrupt is configured 
-          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
-          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can 
-              add his own function by customization of function pointer XferCpltCallback and 
-              XferErrorCallback (i.e a member of DMA handle structure).
-    [..]
-     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error 
-         detection.
-
-     (#) Use HAL_DMA_Abort_IT() function to abort the current transfer
-
-     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
-
-     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
-           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
-           Half-Word data size for the peripheral to access its data register and set Word data size
-           for the Memory to gain in access time. Each two half words will be packed and written in
-           a single access to a Word in the Memory).
-
-     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
-           and Destination. In this case the Peripheral Data Size will be applied to both Source
-           and Destination.
-
-     *** DMA HAL driver macros list ***
-     =============================================
-     [..]
-       Below the list of most used macros in DMA HAL driver.
-       
-      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
-      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
-      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. 
-
-     [..]
-      (@) You can refer to the DMA HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DMA DMA
-  * @brief DMA HAL module driver
-  * @{
-  */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-typedef struct
-{
-  __IO uint32_t ISR;   /*!< DMA interrupt status register */
-  __IO uint32_t Reserved0;
-  __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */
-} DMA_Base_Registers;
-
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/** @addtogroup DMA_Private_Constants
- * @{
- */
- #define HAL_TIMEOUT_DMA_ABORT    5U  /* 5 ms */
-/**
-  * @}
-  */
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup DMA_Private_Functions
-  * @{
-  */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
-
-/**
-  * @}
-  */  
-
-/* Exported functions ---------------------------------------------------------*/
-/** @addtogroup DMA_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group1
-  *
-@verbatim
- ===============================================================================
-             ##### Initialization and de-initialization functions  #####
- ===============================================================================
-    [..]
-    This section provides functions allowing to initialize the DMA Stream source
-    and destination addresses, incrementation and data sizes, transfer direction, 
-    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
-    [..]
-    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
-    reference manual.
-
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Initialize the DMA according to the specified
-  *         parameters in the DMA_InitTypeDef and create the associated handle.
-  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Stream.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
-  uint32_t tmp = 0U;
-  uint32_t tickstart = HAL_GetTick();
-  DMA_Base_Registers *regs;
-
-  /* Check the DMA peripheral state */
-  if(hdma == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
-  assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
-  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
-  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
-  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
-  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
-  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
-  assert_param(IS_DMA_MODE(hdma->Init.Mode));
-  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-  assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
-  /* Check the memory burst, peripheral burst and FIFO threshold parameters only
-     when FIFO mode is enabled */
-  if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
-  {
-    assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
-    assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
-    assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
-  }
-
-  /* Change DMA peripheral state */
-  hdma->State = HAL_DMA_STATE_BUSY;
-
-  /* Allocate lock resource */
-  __HAL_UNLOCK(hdma);
-  
-  /* Disable the peripheral */
-  __HAL_DMA_DISABLE(hdma);
-  
-  /* Check if the DMA Stream is effectively disabled */
-  while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
-  {
-    /* Check for the Timeout */
-    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
-    {
-      /* Update error code */
-      hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-      
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_TIMEOUT;
-      
-      return HAL_TIMEOUT;
-    }
-  }
-  
-  /* Get the CR register value */
-  tmp = hdma->Instance->CR;
-
-  /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
-  tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
-                      DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
-                      DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
-                      DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
-
-  /* Prepare the DMA Stream configuration */
-  tmp |=  hdma->Init.Channel             | hdma->Init.Direction        |
-          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
-          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
-          hdma->Init.Mode                | hdma->Init.Priority;
-
-  /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
-  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
-  {
-    /* Get memory burst and peripheral burst */
-    tmp |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
-  }
-  
-  /* Write to DMA Stream CR register */
-  hdma->Instance->CR = tmp;  
-
-  /* Get the FCR register value */
-  tmp = hdma->Instance->FCR;
-
-  /* Clear Direct mode and FIFO threshold bits */
-  tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
-
-  /* Prepare the DMA Stream FIFO configuration */
-  tmp |= hdma->Init.FIFOMode;
-
-  /* The FIFO threshold is not used when the FIFO mode is disabled */
-  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
-  {
-    /* Get the FIFO threshold */
-    tmp |= hdma->Init.FIFOThreshold;
-    
-    /* Check compatibility between FIFO threshold level and size of the memory burst */
-    /* for INCR4, INCR8, INCR16 bursts */
-    if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
-    {
-      if (DMA_CheckFifoParam(hdma) != HAL_OK)
-      {
-        /* Update error code */
-        hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
-        
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_READY;
-        
-        return HAL_ERROR; 
-      }
-    }
-  }
-  
-  /* Write to DMA Stream FCR */
-  hdma->Instance->FCR = tmp;
-
-  /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
-     DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
-  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
-  
-  /* Clear all interrupt flags */
-  regs->IFCR = 0x3FU << hdma->StreamIndex;
-
-  /* Initialize the error code */
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-                                                                                     
-  /* Initialize the DMA state */
-  hdma->State = HAL_DMA_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the DMA peripheral 
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Stream.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
-{
-  DMA_Base_Registers *regs;
-
-  /* Check the DMA peripheral state */
-  if(hdma == NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the DMA peripheral state */
-  if(hdma->State == HAL_DMA_STATE_BUSY)
-  {
-    /* Return error status */
-    return HAL_BUSY;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
-
-  /* Disable the selected DMA Streamx */
-  __HAL_DMA_DISABLE(hdma);
-
-  /* Reset DMA Streamx control register */
-  hdma->Instance->CR   = 0U;
-
-  /* Reset DMA Streamx number of data to transfer register */
-  hdma->Instance->NDTR = 0U;
-
-  /* Reset DMA Streamx peripheral address register */
-  hdma->Instance->PAR  = 0U;
-
-  /* Reset DMA Streamx memory 0 address register */
-  hdma->Instance->M0AR = 0U;
-  
-  /* Reset DMA Streamx memory 1 address register */
-  hdma->Instance->M1AR = 0U;
-  
-  /* Reset DMA Streamx FIFO control register */
-  hdma->Instance->FCR  = 0x00000021U;
-  
-  /* Get DMA steam Base Address */  
-  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
-  
-  /* Clean all callbacks */
-  hdma->XferCpltCallback = NULL;
-  hdma->XferHalfCpltCallback = NULL;
-  hdma->XferM1CpltCallback = NULL;
-  hdma->XferM1HalfCpltCallback = NULL;
-  hdma->XferErrorCallback = NULL;
-  hdma->XferAbortCallback = NULL;
-
-  /* Clear all interrupt flags at correct offset within the register */
-  regs->IFCR = 0x3FU << hdma->StreamIndex;
-
-  /* Reset the error code */
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-  /* Reset the DMA state */
-  hdma->State = HAL_DMA_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group2
-  *
-@verbatim   
- ===============================================================================
-                      #####  IO operation functions  #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Configure the source, destination address and data length and Start DMA transfer
-      (+) Configure the source, destination address and data length and 
-          Start DMA transfer with interrupt
-      (+) Abort DMA transfer
-      (+) Poll for transfer complete
-      (+) Handle DMA interrupt request  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the DMA Transfer.
-  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.
-  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress The destination memory Buffer address
-  * @param  DataLength The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    /* Change DMA peripheral state */
-    hdma->State = HAL_DMA_STATE_BUSY;
-    
-    /* Initialize the error code */
-    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-    
-    /* Configure the source, destination address and the data length */
-    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-    /* Enable the Peripheral */
-    __HAL_DMA_ENABLE(hdma);
-  }
-  else
-  {
-    /* Process unlocked */
-    __HAL_UNLOCK(hdma);
-    
-    /* Return error status */
-    status = HAL_BUSY;
-  } 
-  return status; 
-}
-
-/**
-  * @brief  Start the DMA Transfer with interrupt enabled.
-  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.  
-  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress The destination memory Buffer address
-  * @param  DataLength The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* calculate DMA base and stream number */
-  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
-  
-  /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
- 
-  /* Process locked */
-  __HAL_LOCK(hdma);
-  
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    /* Change DMA peripheral state */
-    hdma->State = HAL_DMA_STATE_BUSY;
-    
-    /* Initialize the error code */
-    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-    
-    /* Configure the source, destination address and the data length */
-    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-    
-    /* Clear all interrupt flags at correct offset within the register */
-    regs->IFCR = 0x3FU << hdma->StreamIndex;
-    
-    /* Enable Common interrupts*/
-    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
-    
-    if(hdma->XferHalfCpltCallback != NULL)
-    {
-      hdma->Instance->CR  |= DMA_IT_HT;
-    }
-    
-    /* Enable the Peripheral */
-    __HAL_DMA_ENABLE(hdma);
-  }
-  else
-  {
-    /* Process unlocked */
-    __HAL_UNLOCK(hdma);	  
-    
-    /* Return error status */
-    status = HAL_BUSY;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Aborts the DMA Transfer.
-  * @param  hdma   pointer to a DMA_HandleTypeDef structure that contains
-  *                 the configuration information for the specified DMA Stream.
-  *                   
-  * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is 
-  *        effectively disabled is added. If a Stream is disabled 
-  *        while a data transfer is ongoing, the current data will be transferred
-  *        and the Stream will be effectively disabled only after the transfer of
-  *        this single data is finished.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
-{
-  /* calculate DMA base and stream number */
-  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
-  
-  uint32_t tickstart = HAL_GetTick();
-  
-  if(hdma->State != HAL_DMA_STATE_BUSY)
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-    
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Disable all the transfer interrupts */
-    hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
-    hdma->Instance->FCR &= ~(DMA_IT_FE);
-    
-    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
-    {
-      hdma->Instance->CR  &= ~(DMA_IT_HT);
-    }
-    
-    /* Disable the stream */
-    __HAL_DMA_DISABLE(hdma);
-    
-    /* Check if the DMA Stream is effectively disabled */
-    while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
-    {
-      /* Check for the Timeout */
-      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
-      {
-        /* Update error code */
-        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-        
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_TIMEOUT;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /* Clear all interrupt flags at correct offset within the register */
-    regs->IFCR = 0x3FU << hdma->StreamIndex;
-    
-    /* Change the DMA state*/
-    hdma->State = HAL_DMA_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Aborts the DMA Transfer in Interrupt mode.
-  * @param  hdma   pointer to a DMA_HandleTypeDef structure that contains
-  *                 the configuration information for the specified DMA Stream.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
-{
-  if(hdma->State != HAL_DMA_STATE_BUSY)
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Set Abort State  */
-    hdma->State = HAL_DMA_STATE_ABORT;
-    
-    /* Disable the stream */
-    __HAL_DMA_DISABLE(hdma);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Polling for transfer complete.
-  * @param  hdma          pointer to a DMA_HandleTypeDef structure that contains
-  *                        the configuration information for the specified DMA Stream.
-  * @param  CompleteLevel Specifies the DMA level complete.
-  * @note   The polling mode is kept in this version for legacy. it is recommended to use the IT model instead.
-  *         This model could be used for debug purpose.
-  * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). 
-  * @param  Timeout       Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
-{
-  HAL_StatusTypeDef status = HAL_OK; 
-  uint32_t mask_cpltlevel;
-  uint32_t tickstart = HAL_GetTick(); 
-  uint32_t tmpisr;
-  
-  /* calculate DMA base and stream number */
-  DMA_Base_Registers *regs;
-
-  if(HAL_DMA_STATE_BUSY != hdma->State)
-  {
-    /* No transfer ongoing */
-    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
-    __HAL_UNLOCK(hdma);
-    return HAL_ERROR;
-  }
-
-  /* Polling mode not supported in circular mode and double buffering mode */
-  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
-    return HAL_ERROR;
-  }
-  
-  /* Get the level transfer complete flag */
-  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
-  {
-    /* Transfer Complete flag */
-    mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
-  }
-  else
-  {
-    /* Half Transfer Complete flag */
-    mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
-  }
-  
-  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
-  tmpisr = regs->ISR;
-  
-  while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
-  {
-    /* Check for the Timeout (Not applicable in circular mode)*/
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* Update error code */
-        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
-        
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_READY;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
-        
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Get the ISR register value */
-    tmpisr = regs->ISR;
-
-    if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
-    {
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
-      
-      /* Clear the transfer error flag */
-      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
-    }
-    
-    if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
-    {
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_FE;
-      
-      /* Clear the FIFO error flag */
-      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
-    }
-    
-    if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
-    {
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_DME;
-      
-      /* Clear the Direct Mode error flag */
-      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
-    }
-  }
-  
-  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
-  {
-    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
-    {
-      HAL_DMA_Abort(hdma);
-    
-      /* Clear the half transfer and transfer complete flags */
-      regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
-    
-      /* Change the DMA state */
-      hdma->State= HAL_DMA_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-
-      return HAL_ERROR;
-   }
-  }
-  
-  /* Get the level transfer complete flag */
-  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
-  {
-    /* Clear the half transfer and transfer complete flags */
-    regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
-    
-    hdma->State = HAL_DMA_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-  }
-  else
-  {
-    /* Clear the half transfer and transfer complete flags */
-    regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Handles DMA interrupt request.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Stream.  
-  * @retval None
-  */
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
-{
-  uint32_t tmpisr;
-  __IO uint32_t count = 0U;
-  uint32_t timeout = SystemCoreClock / 9600U;
-
-  /* calculate DMA base and stream number */
-  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
-
-  tmpisr = regs->ISR;
-
-  /* Transfer Error Interrupt management ***************************************/
-  if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
-    {
-      /* Disable the transfer error interrupt */
-      hdma->Instance->CR  &= ~(DMA_IT_TE);
-      
-      /* Clear the transfer error flag */
-      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
-      
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
-    }
-  }
-  /* FIFO Error Interrupt management ******************************************/
-  if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
-    {
-      /* Clear the FIFO error flag */
-      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
-
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_FE;
-    }
-  }
-  /* Direct Mode Error Interrupt management ***********************************/
-  if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
-    {
-      /* Clear the direct mode error flag */
-      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
-
-      /* Update error code */
-      hdma->ErrorCode |= HAL_DMA_ERROR_DME;
-    }
-  }
-  /* Half Transfer Complete Interrupt management ******************************/
-  if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
-    {
-      /* Clear the half transfer complete flag */
-      regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
-      
-      /* Multi_Buffering mode enabled */
-      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
-      {
-        /* Current memory buffer used is Memory 0 */
-        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
-        {
-          if(hdma->XferHalfCpltCallback != NULL)
-          {
-            /* Half transfer callback */
-            hdma->XferHalfCpltCallback(hdma);
-          }
-        }
-        /* Current memory buffer used is Memory 1 */
-        else
-        {
-          if(hdma->XferM1HalfCpltCallback != NULL)
-          {
-            /* Half transfer callback */
-            hdma->XferM1HalfCpltCallback(hdma);
-          }
-        }
-      }
-      else
-      {
-        /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
-        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
-        {
-          /* Disable the half transfer interrupt */
-          hdma->Instance->CR  &= ~(DMA_IT_HT);
-        }
-        
-        if(hdma->XferHalfCpltCallback != NULL)
-        {
-          /* Half transfer callback */
-          hdma->XferHalfCpltCallback(hdma);
-        }
-      }
-    }
-  }
-  /* Transfer Complete Interrupt management ***********************************/
-  if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
-    {
-      /* Clear the transfer complete flag */
-      regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
-      
-      if(HAL_DMA_STATE_ABORT == hdma->State)
-      {
-        /* Disable all the transfer interrupts */
-        hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
-        hdma->Instance->FCR &= ~(DMA_IT_FE);
-        
-        if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
-        {
-          hdma->Instance->CR  &= ~(DMA_IT_HT);
-        }
-
-        /* Clear all interrupt flags at correct offset within the register */
-        regs->IFCR = 0x3FU << hdma->StreamIndex;
-
-        /* Change the DMA state */
-        hdma->State = HAL_DMA_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
-
-        if(hdma->XferAbortCallback != NULL)
-        {
-          hdma->XferAbortCallback(hdma);
-        }
-        return;
-      }
-
-      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
-      {
-        /* Current memory buffer used is Memory 0 */
-        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
-        {
-          if(hdma->XferM1CpltCallback != NULL)
-          {
-            /* Transfer complete Callback for memory1 */
-            hdma->XferM1CpltCallback(hdma);
-          }
-        }
-        /* Current memory buffer used is Memory 1 */
-        else
-        {
-          if(hdma->XferCpltCallback != NULL)
-          {
-            /* Transfer complete Callback for memory0 */
-            hdma->XferCpltCallback(hdma);
-          }
-        }
-      }
-      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
-      else
-      {
-        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
-        {
-          /* Disable the transfer complete interrupt */
-          hdma->Instance->CR  &= ~(DMA_IT_TC);
-
-          /* Change the DMA state */
-          hdma->State = HAL_DMA_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hdma);
-        }
-
-        if(hdma->XferCpltCallback != NULL)
-        {
-          /* Transfer complete callback */
-          hdma->XferCpltCallback(hdma);
-        }
-      }
-    }
-  }
-  
-  /* manage error case */
-  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
-  {
-    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
-    {
-      hdma->State = HAL_DMA_STATE_ABORT;
-
-      /* Disable the stream */
-      __HAL_DMA_DISABLE(hdma);
-
-      do
-      {
-        if (++count > timeout)
-        {
-          break;
-        }
-      }
-      while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-    }
-
-    if(hdma->XferErrorCallback != NULL)
-    {
-      /* Transfer error callback */
-      hdma->XferErrorCallback(hdma);
-    }
-  }
-}
-
-/**
-  * @brief  Register callbacks
-  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
-  *                               the configuration information for the specified DMA Stream.
-  * @param  CallbackID           User Callback identifier
-  *                               a DMA_HandleTypeDef structure as parameter.
-  * @param  pCallback            pointer to private callback function which has pointer to 
-  *                               a DMA_HandleTypeDef structure as parameter.
-  * @retval HAL status
-  */                      
-HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
-{
-
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    switch (CallbackID)
-    {
-    case  HAL_DMA_XFER_CPLT_CB_ID:
-      hdma->XferCpltCallback = pCallback;
-      break;
-
-    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
-      hdma->XferHalfCpltCallback = pCallback;
-      break;
-
-    case  HAL_DMA_XFER_M1CPLT_CB_ID:
-      hdma->XferM1CpltCallback = pCallback;
-      break;
-
-    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
-      hdma->XferM1HalfCpltCallback = pCallback;
-      break;
-
-    case  HAL_DMA_XFER_ERROR_CB_ID:
-      hdma->XferErrorCallback = pCallback;
-      break;
-
-    case  HAL_DMA_XFER_ABORT_CB_ID:
-      hdma->XferAbortCallback = pCallback;
-      break;
-
-    default:
-      /* Return error status */
-      status =  HAL_ERROR;
-      break;
-    }
-  }
-  else
-  {
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-  
-  return status;
-}
-
-/**
-  * @brief  UnRegister callbacks
-  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
-  *                               the configuration information for the specified DMA Stream.
-  * @param  CallbackID           User Callback identifier
-  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
-  * @retval HAL status
-  */              
-HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Process locked */
-  __HAL_LOCK(hdma);
-  
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    switch (CallbackID)
-    {
-    case  HAL_DMA_XFER_CPLT_CB_ID:
-      hdma->XferCpltCallback = NULL;
-      break;
-      
-    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
-      hdma->XferHalfCpltCallback = NULL;
-      break;
-      
-    case  HAL_DMA_XFER_M1CPLT_CB_ID:
-      hdma->XferM1CpltCallback = NULL;
-      break;
-      
-    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
-      hdma->XferM1HalfCpltCallback = NULL;
-      break;
-      
-    case  HAL_DMA_XFER_ERROR_CB_ID:
-      hdma->XferErrorCallback = NULL;
-      break;
-      
-    case  HAL_DMA_XFER_ABORT_CB_ID:
-      hdma->XferAbortCallback = NULL;
-      break; 
-      
-    case   HAL_DMA_XFER_ALL_CB_ID:
-      hdma->XferCpltCallback = NULL;
-      hdma->XferHalfCpltCallback = NULL;
-      hdma->XferM1CpltCallback = NULL;
-      hdma->XferM1HalfCpltCallback = NULL;
-      hdma->XferErrorCallback = NULL;
-      hdma->XferAbortCallback = NULL;
-      break; 
-      
-    default:
-      status = HAL_ERROR;
-      break;
-    }
-  }
-  else
-  {
-    status = HAL_ERROR;
-  }
-  
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-  
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Exported_Functions_Group3
-  *
-@verbatim
- ===============================================================================
-                    ##### State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection provides functions allowing to
-      (+) Check the DMA state
-      (+) Get error code
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the DMA state.
-  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Stream.
-  * @retval HAL state
-  */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
-{
-  return hdma->State;
-}
-
-/**
-  * @brief  Return the DMA error code
-  * @param  hdma  pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA Stream.
-  * @retval DMA Error Code
-  */
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
-{
-  return hdma->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Sets the DMA Transfer parameter.
-  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.
-  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress The destination memory Buffer address
-  * @param  DataLength The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  /* Clear DBM bit */
-  hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
-
-  /* Configure DMA Stream data length */
-  hdma->Instance->NDTR = DataLength;
-
-  /* Memory to Peripheral */
-  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
-  {
-    /* Configure DMA Stream destination address */
-    hdma->Instance->PAR = DstAddress;
-
-    /* Configure DMA Stream source address */
-    hdma->Instance->M0AR = SrcAddress;
-  }
-  /* Peripheral to Memory */
-  else
-  {
-    /* Configure DMA Stream source address */
-    hdma->Instance->PAR = SrcAddress;
-
-    /* Configure DMA Stream destination address */
-    hdma->Instance->M0AR = DstAddress;
-  }
-}
-
-/**
-  * @brief  Returns the DMA Stream base address depending on stream number
-  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream. 
-  * @retval Stream base address
-  */
-static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
-{
-  uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
-  
-  /* lookup table for necessary bitshift of flags within status registers */
-  static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
-  hdma->StreamIndex = flagBitshiftOffset[stream_number];
-  
-  if (stream_number > 3U)
-  {
-    /* return pointer to HISR and HIFCR */
-    hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
-  }
-  else
-  {
-    /* return pointer to LISR and LIFCR */
-    hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
-  }
-  
-  return hdma->StreamBaseAddress;
-}
-
-/**
-  * @brief  Check compatibility between FIFO threshold level and size of the memory burst
-  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream. 
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmp = hdma->Init.FIFOThreshold;
-  
-  /* Memory Data size equal to Byte */
-  if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
-  {
-    switch (tmp)
-    {
-    case DMA_FIFO_THRESHOLD_1QUARTERFULL:
-    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
-      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
-      {
-        status = HAL_ERROR;
-      }
-      break;
-    case DMA_FIFO_THRESHOLD_HALFFULL:
-      if (hdma->Init.MemBurst == DMA_MBURST_INC16)
-      {
-        status = HAL_ERROR;
-      }
-      break;
-    case DMA_FIFO_THRESHOLD_FULL:
-      break;
-    default:
-      break;
-    }
-  }
-  
-  /* Memory Data size equal to Half-Word */
-  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
-  {
-    switch (tmp)
-    {
-    case DMA_FIFO_THRESHOLD_1QUARTERFULL:
-    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
-      status = HAL_ERROR;
-      break;
-    case DMA_FIFO_THRESHOLD_HALFFULL:
-      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
-      {
-        status = HAL_ERROR;
-      }
-      break;
-    case DMA_FIFO_THRESHOLD_FULL:
-      if (hdma->Init.MemBurst == DMA_MBURST_INC16)
-      {
-        status = HAL_ERROR;
-      }
-      break;   
-    default:
-      break;
-    }
-  }
-  
-  /* Memory Data size equal to Word */
-  else
-  {
-    switch (tmp)
-    {
-    case DMA_FIFO_THRESHOLD_1QUARTERFULL:
-    case DMA_FIFO_THRESHOLD_HALFFULL:
-    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
-      status = HAL_ERROR;
-      break;
-    case DMA_FIFO_THRESHOLD_FULL:
-      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
-      {
-        status = HAL_ERROR;
-      }
-      break;
-    default:
-      break;
-    }
-  } 
-  
-  return status; 
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_DMA_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dma.c
+  * @author  MCD Application Team
+  * @brief   DMA HAL module driver.
+  *    
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Direct Memory Access (DMA) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and errors functions
+  @verbatim     
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Enable and configure the peripheral to be connected to the DMA Stream
+       (except for internal SRAM/FLASH memories: no initialization is 
+       necessary) please refer to Reference manual for connection between peripherals
+       and DMA requests.
+
+   (#) For a given Stream, program the required configuration through the following parameters:
+       Transfer Direction, Source and Destination data formats, 
+       Circular, Normal or peripheral flow control mode, Stream Priority level, 
+       Source and Destination Increment mode, FIFO mode and its Threshold (if needed), 
+       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
+
+   -@-   Prior to HAL_DMA_Init() the clock must be enabled for DMA through the following macros:
+         __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE().
+
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source 
+              address and destination address and the Length of data to be transferred.
+          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this  
+              case a fixed Timeout can be configured by User depending from his application.
+          (+) Use HAL_DMA_Abort() function to abort the current transfer.
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
+          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() 
+          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of  
+              Source address and destination address and the Length of data to be transferred. In this 
+              case the DMA interrupt is configured 
+          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can 
+              add his own function by customization of function pointer XferCpltCallback and 
+              XferErrorCallback (i.e a member of DMA handle structure).
+    [..]
+     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error 
+         detection.
+
+     (#) Use HAL_DMA_Abort_IT() function to abort the current transfer
+
+     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
+
+     -@-   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
+           possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
+           Half-Word data size for the peripheral to access its data register and set Word data size
+           for the Memory to gain in access time. Each two half words will be packed and written in
+           a single access to a Word in the Memory).
+
+     -@-   When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
+           and Destination. In this case the Peripheral Data Size will be applied to both Source
+           and Destination.
+
+     *** DMA HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in DMA HAL driver.
+       
+      (+) __HAL_DMA_ENABLE: Enable the specified DMA Stream.
+      (+) __HAL_DMA_DISABLE: Disable the specified DMA Stream.
+      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Stream interrupt has occurred or not. 
+
+     [..]
+      (@) You can refer to the DMA HAL driver header file for more useful macros
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMA DMA
+  * @brief DMA HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+typedef struct
+{
+  __IO uint32_t ISR;   /*!< DMA interrupt status register */
+  __IO uint32_t Reserved0;
+  __IO uint32_t IFCR;  /*!< DMA interrupt flag clear register */
+} DMA_Base_Registers;
+
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Constants
+ * @{
+ */
+ #define HAL_TIMEOUT_DMA_ABORT    5U  /* 5 ms */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */  
+
+/* Exported functions ---------------------------------------------------------*/
+/** @addtogroup DMA_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+  *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to initialize the DMA Stream source
+    and destination addresses, incrementation and data sizes, transfer direction, 
+    circular/normal mode selection, memory-to-memory mode selection and Stream priority value.
+    [..]
+    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+    reference manual.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Initialize the DMA according to the specified
+  *         parameters in the DMA_InitTypeDef and create the associated handle.
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+  uint32_t tmp = 0U;
+  uint32_t tickstart = HAL_GetTick();
+  DMA_Base_Registers *regs;
+
+  /* Check the DMA peripheral state */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_CHANNEL(hdma->Init.Channel));
+  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+  assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode));
+  /* Check the memory burst, peripheral burst and FIFO threshold parameters only
+     when FIFO mode is enabled */
+  if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE)
+  {
+    assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold));
+    assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst));
+    assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst));
+  }
+
+  /* Change DMA peripheral state */
+  hdma->State = HAL_DMA_STATE_BUSY;
+
+  /* Allocate lock resource */
+  __HAL_UNLOCK(hdma);
+  
+  /* Disable the peripheral */
+  __HAL_DMA_DISABLE(hdma);
+  
+  /* Check if the DMA Stream is effectively disabled */
+  while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
+  {
+    /* Check for the Timeout */
+    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+    {
+      /* Update error code */
+      hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+      
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_TIMEOUT;
+      
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  /* Get the CR register value */
+  tmp = hdma->Instance->CR;
+
+  /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */
+  tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
+                      DMA_SxCR_PL    | DMA_SxCR_MSIZE  | DMA_SxCR_PSIZE  | \
+                      DMA_SxCR_MINC  | DMA_SxCR_PINC   | DMA_SxCR_CIRC   | \
+                      DMA_SxCR_DIR   | DMA_SxCR_CT     | DMA_SxCR_DBM));
+
+  /* Prepare the DMA Stream configuration */
+  tmp |=  hdma->Init.Channel             | hdma->Init.Direction        |
+          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+          hdma->Init.Mode                | hdma->Init.Priority;
+
+  /* the Memory burst and peripheral burst are not used when the FIFO is disabled */
+  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+  {
+    /* Get memory burst and peripheral burst */
+    tmp |=  hdma->Init.MemBurst | hdma->Init.PeriphBurst;
+  }
+  
+  /* Write to DMA Stream CR register */
+  hdma->Instance->CR = tmp;  
+
+  /* Get the FCR register value */
+  tmp = hdma->Instance->FCR;
+
+  /* Clear Direct mode and FIFO threshold bits */
+  tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
+
+  /* Prepare the DMA Stream FIFO configuration */
+  tmp |= hdma->Init.FIFOMode;
+
+  /* The FIFO threshold is not used when the FIFO mode is disabled */
+  if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE)
+  {
+    /* Get the FIFO threshold */
+    tmp |= hdma->Init.FIFOThreshold;
+    
+    /* Check compatibility between FIFO threshold level and size of the memory burst */
+    /* for INCR4, INCR8, INCR16 bursts */
+    if (hdma->Init.MemBurst != DMA_MBURST_SINGLE)
+    {
+      if (DMA_CheckFifoParam(hdma) != HAL_OK)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+        
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+        
+        return HAL_ERROR; 
+      }
+    }
+  }
+  
+  /* Write to DMA Stream FCR */
+  hdma->Instance->FCR = tmp;
+
+  /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate
+     DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */
+  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+  
+  /* Clear all interrupt flags */
+  regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+                                                                                     
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the DMA peripheral 
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+  DMA_Base_Registers *regs;
+
+  /* Check the DMA peripheral state */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the DMA peripheral state */
+  if(hdma->State == HAL_DMA_STATE_BUSY)
+  {
+    /* Return error status */
+    return HAL_BUSY;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance));
+
+  /* Disable the selected DMA Streamx */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Reset DMA Streamx control register */
+  hdma->Instance->CR   = 0U;
+
+  /* Reset DMA Streamx number of data to transfer register */
+  hdma->Instance->NDTR = 0U;
+
+  /* Reset DMA Streamx peripheral address register */
+  hdma->Instance->PAR  = 0U;
+
+  /* Reset DMA Streamx memory 0 address register */
+  hdma->Instance->M0AR = 0U;
+  
+  /* Reset DMA Streamx memory 1 address register */
+  hdma->Instance->M1AR = 0U;
+  
+  /* Reset DMA Streamx FIFO control register */
+  hdma->Instance->FCR  = 0x00000021U;
+  
+  /* Get DMA steam Base Address */  
+  regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma);
+  
+  /* Clean all callbacks */
+  hdma->XferCpltCallback = NULL;
+  hdma->XferHalfCpltCallback = NULL;
+  hdma->XferM1CpltCallback = NULL;
+  hdma->XferM1HalfCpltCallback = NULL;
+  hdma->XferErrorCallback = NULL;
+  hdma->XferAbortCallback = NULL;
+
+  /* Clear all interrupt flags at correct offset within the register */
+  regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+  /* Reset the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Reset the DMA state */
+  hdma->State = HAL_DMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+  *
+@verbatim   
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and Start DMA transfer
+      (+) Configure the source, destination address and data length and 
+          Start DMA transfer with interrupt
+      (+) Abort DMA transfer
+      (+) Poll for transfer complete
+      (+) Handle DMA interrupt request  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the DMA Transfer.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+    
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);
+    
+    /* Return error status */
+    status = HAL_BUSY;
+  } 
+  return status; 
+}
+
+/**
+  * @brief  Start the DMA Transfer with interrupt enabled.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+ 
+  /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+    
+    /* Configure the source, destination address and the data length */
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+    
+    /* Clear all interrupt flags at correct offset within the register */
+    regs->IFCR = 0x3FU << hdma->StreamIndex;
+    
+    /* Enable Common interrupts*/
+    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
+    
+    if(hdma->XferHalfCpltCallback != NULL)
+    {
+      hdma->Instance->CR  |= DMA_IT_HT;
+    }
+    
+    /* Enable the Peripheral */
+    __HAL_DMA_ENABLE(hdma);
+  }
+  else
+  {
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);	  
+    
+    /* Return error status */
+    status = HAL_BUSY;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Aborts the DMA Transfer.
+  * @param  hdma   pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  *                   
+  * @note  After disabling a DMA Stream, a check for wait until the DMA Stream is 
+  *        effectively disabled is added. If a Stream is disabled 
+  *        while a data transfer is ongoing, the current data will be transferred
+  *        and the Stream will be effectively disabled only after the transfer of
+  *        this single data is finished.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  
+  uint32_t tickstart = HAL_GetTick();
+  
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+    
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Disable all the transfer interrupts */
+    hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+    hdma->Instance->FCR &= ~(DMA_IT_FE);
+    
+    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+    {
+      hdma->Instance->CR  &= ~(DMA_IT_HT);
+    }
+    
+    /* Disable the stream */
+    __HAL_DMA_DISABLE(hdma);
+    
+    /* Check if the DMA Stream is effectively disabled */
+    while((hdma->Instance->CR & DMA_SxCR_EN) != RESET)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+        
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_TIMEOUT;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /* Clear all interrupt flags at correct offset within the register */
+    regs->IFCR = 0x3FU << hdma->StreamIndex;
+    
+    /* Change the DMA state*/
+    hdma->State = HAL_DMA_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Aborts the DMA Transfer in Interrupt mode.
+  * @param  hdma   pointer to a DMA_HandleTypeDef structure that contains
+  *                 the configuration information for the specified DMA Stream.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
+{
+  if(hdma->State != HAL_DMA_STATE_BUSY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Set Abort State  */
+    hdma->State = HAL_DMA_STATE_ABORT;
+    
+    /* Disable the stream */
+    __HAL_DMA_DISABLE(hdma);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Polling for transfer complete.
+  * @param  hdma          pointer to a DMA_HandleTypeDef structure that contains
+  *                        the configuration information for the specified DMA Stream.
+  * @param  CompleteLevel Specifies the DMA level complete.
+  * @note   The polling mode is kept in this version for legacy. it is recommended to use the IT model instead.
+  *         This model could be used for debug purpose.
+  * @note   The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). 
+  * @param  Timeout       Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
+{
+  HAL_StatusTypeDef status = HAL_OK; 
+  uint32_t mask_cpltlevel;
+  uint32_t tickstart = HAL_GetTick(); 
+  uint32_t tmpisr;
+  
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs;
+
+  if(HAL_DMA_STATE_BUSY != hdma->State)
+  {
+    /* No transfer ongoing */
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+    __HAL_UNLOCK(hdma);
+    return HAL_ERROR;
+  }
+
+  /* Polling mode not supported in circular mode and double buffering mode */
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+  
+  /* Get the level transfer complete flag */
+  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  {
+    /* Transfer Complete flag */
+    mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+  }
+  else
+  {
+    /* Half Transfer Complete flag */
+    mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+  }
+  
+  regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+  tmpisr = regs->ISR;
+  
+  while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET))
+  {
+    /* Check for the Timeout (Not applicable in circular mode)*/
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        /* Update error code */
+        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
+        
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+        
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+        
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Get the ISR register value */
+    tmpisr = regs->ISR;
+
+    if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
+    {
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+      
+      /* Clear the transfer error flag */
+      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
+    }
+    
+    if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
+    {
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+      
+      /* Clear the FIFO error flag */
+      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
+    }
+    
+    if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
+    {
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+      
+      /* Clear the Direct Mode error flag */
+      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
+    }
+  }
+  
+  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+  {
+    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
+    {
+      HAL_DMA_Abort(hdma);
+    
+      /* Clear the half transfer and transfer complete flags */
+      regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+    
+      /* Change the DMA state */
+      hdma->State= HAL_DMA_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      return HAL_ERROR;
+   }
+  }
+  
+  /* Get the level transfer complete flag */
+  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  {
+    /* Clear the half transfer and transfer complete flags */
+    regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex;
+    
+    hdma->State = HAL_DMA_STATE_READY;
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(hdma);
+  }
+  else
+  {
+    /* Clear the half transfer and transfer complete flags */
+    regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Handles DMA interrupt request.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.  
+  * @retval None
+  */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  uint32_t tmpisr;
+  __IO uint32_t count = 0U;
+  uint32_t timeout = SystemCoreClock / 9600U;
+
+  /* calculate DMA base and stream number */
+  DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
+
+  tmpisr = regs->ISR;
+
+  /* Transfer Error Interrupt management ***************************************/
+  if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
+    {
+      /* Disable the transfer error interrupt */
+      hdma->Instance->CR  &= ~(DMA_IT_TE);
+      
+      /* Clear the transfer error flag */
+      regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
+      
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+    }
+  }
+  /* FIFO Error Interrupt management ******************************************/
+  if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
+    {
+      /* Clear the FIFO error flag */
+      regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_FE;
+    }
+  }
+  /* Direct Mode Error Interrupt management ***********************************/
+  if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
+    {
+      /* Clear the direct mode error flag */
+      regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_DME;
+    }
+  }
+  /* Half Transfer Complete Interrupt management ******************************/
+  if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
+    {
+      /* Clear the half transfer complete flag */
+      regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
+      
+      /* Multi_Buffering mode enabled */
+      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
+        {
+          if(hdma->XferHalfCpltCallback != NULL)
+          {
+            /* Half transfer callback */
+            hdma->XferHalfCpltCallback(hdma);
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferM1HalfCpltCallback != NULL)
+          {
+            /* Half transfer callback */
+            hdma->XferM1HalfCpltCallback(hdma);
+          }
+        }
+      }
+      else
+      {
+        /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
+        {
+          /* Disable the half transfer interrupt */
+          hdma->Instance->CR  &= ~(DMA_IT_HT);
+        }
+        
+        if(hdma->XferHalfCpltCallback != NULL)
+        {
+          /* Half transfer callback */
+          hdma->XferHalfCpltCallback(hdma);
+        }
+      }
+    }
+  }
+  /* Transfer Complete Interrupt management ***********************************/
+  if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
+    {
+      /* Clear the transfer complete flag */
+      regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
+      
+      if(HAL_DMA_STATE_ABORT == hdma->State)
+      {
+        /* Disable all the transfer interrupts */
+        hdma->Instance->CR  &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
+        hdma->Instance->FCR &= ~(DMA_IT_FE);
+        
+        if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+        {
+          hdma->Instance->CR  &= ~(DMA_IT_HT);
+        }
+
+        /* Clear all interrupt flags at correct offset within the register */
+        regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        if(hdma->XferAbortCallback != NULL)
+        {
+          hdma->XferAbortCallback(hdma);
+        }
+        return;
+      }
+
+      if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
+      {
+        /* Current memory buffer used is Memory 0 */
+        if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
+        {
+          if(hdma->XferM1CpltCallback != NULL)
+          {
+            /* Transfer complete Callback for memory1 */
+            hdma->XferM1CpltCallback(hdma);
+          }
+        }
+        /* Current memory buffer used is Memory 1 */
+        else
+        {
+          if(hdma->XferCpltCallback != NULL)
+          {
+            /* Transfer complete Callback for memory0 */
+            hdma->XferCpltCallback(hdma);
+          }
+        }
+      }
+      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
+      else
+      {
+        if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
+        {
+          /* Disable the transfer complete interrupt */
+          hdma->Instance->CR  &= ~(DMA_IT_TC);
+
+          /* Change the DMA state */
+          hdma->State = HAL_DMA_STATE_READY;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(hdma);
+        }
+
+        if(hdma->XferCpltCallback != NULL)
+        {
+          /* Transfer complete callback */
+          hdma->XferCpltCallback(hdma);
+        }
+      }
+    }
+  }
+  
+  /* manage error case */
+  if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
+  {
+    if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
+    {
+      hdma->State = HAL_DMA_STATE_ABORT;
+
+      /* Disable the stream */
+      __HAL_DMA_DISABLE(hdma);
+
+      do
+      {
+        if (++count > timeout)
+        {
+          break;
+        }
+      }
+      while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+    }
+
+    if(hdma->XferErrorCallback != NULL)
+    {
+      /* Transfer error callback */
+      hdma->XferErrorCallback(hdma);
+    }
+  }
+}
+
+/**
+  * @brief  Register callbacks
+  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID           User Callback identifier
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @param  pCallback            pointer to private callback function which has pointer to 
+  *                               a DMA_HandleTypeDef structure as parameter.
+  * @retval HAL status
+  */                      
+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma))
+{
+
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = pCallback;
+      break;
+
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = pCallback;
+      break;
+
+    default:
+      /* Return error status */
+      status =  HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+  
+  return status;
+}
+
+/**
+  * @brief  UnRegister callbacks
+  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
+  *                               the configuration information for the specified DMA Stream.
+  * @param  CallbackID           User Callback identifier
+  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
+  * @retval HAL status
+  */              
+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    switch (CallbackID)
+    {
+    case  HAL_DMA_XFER_CPLT_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_HALFCPLT_CB_ID:
+      hdma->XferHalfCpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_M1CPLT_CB_ID:
+      hdma->XferM1CpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_M1HALFCPLT_CB_ID:
+      hdma->XferM1HalfCpltCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_ERROR_CB_ID:
+      hdma->XferErrorCallback = NULL;
+      break;
+      
+    case  HAL_DMA_XFER_ABORT_CB_ID:
+      hdma->XferAbortCallback = NULL;
+      break; 
+      
+    case   HAL_DMA_XFER_ALL_CB_ID:
+      hdma->XferCpltCallback = NULL;
+      hdma->XferHalfCpltCallback = NULL;
+      hdma->XferM1CpltCallback = NULL;
+      hdma->XferM1HalfCpltCallback = NULL;
+      hdma->XferErrorCallback = NULL;
+      hdma->XferAbortCallback = NULL;
+      break; 
+      
+    default:
+      status = HAL_ERROR;
+      break;
+    }
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+  
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+  *
+@verbatim
+ ===============================================================================
+                    ##### State and Errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DMA state
+      (+) Get error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the DMA state.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Stream.
+  * @retval HAL state
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+  return hdma->State;
+}
+
+/**
+  * @brief  Return the DMA error code
+  * @param  hdma  pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA Stream.
+  * @retval DMA Error Code
+  */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+  return hdma->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Sets the DMA Transfer parameter.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  /* Clear DBM bit */
+  hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM);
+
+  /* Configure DMA Stream data length */
+  hdma->Instance->NDTR = DataLength;
+
+  /* Memory to Peripheral */
+  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  {
+    /* Configure DMA Stream destination address */
+    hdma->Instance->PAR = DstAddress;
+
+    /* Configure DMA Stream source address */
+    hdma->Instance->M0AR = SrcAddress;
+  }
+  /* Peripheral to Memory */
+  else
+  {
+    /* Configure DMA Stream source address */
+    hdma->Instance->PAR = SrcAddress;
+
+    /* Configure DMA Stream destination address */
+    hdma->Instance->M0AR = DstAddress;
+  }
+}
+
+/**
+  * @brief  Returns the DMA Stream base address depending on stream number
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream. 
+  * @retval Stream base address
+  */
+static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma)
+{
+  uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U;
+  
+  /* lookup table for necessary bitshift of flags within status registers */
+  static const uint8_t flagBitshiftOffset[8U] = {0U, 6U, 16U, 22U, 0U, 6U, 16U, 22U};
+  hdma->StreamIndex = flagBitshiftOffset[stream_number];
+  
+  if (stream_number > 3U)
+  {
+    /* return pointer to HISR and HIFCR */
+    hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U);
+  }
+  else
+  {
+    /* return pointer to LISR and LIFCR */
+    hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU));
+  }
+  
+  return hdma->StreamBaseAddress;
+}
+
+/**
+  * @brief  Check compatibility between FIFO threshold level and size of the memory burst
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream. 
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmp = hdma->Init.FIFOThreshold;
+  
+  /* Memory Data size equal to Byte */
+  if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE)
+  {
+    switch (tmp)
+    {
+    case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    case DMA_FIFO_THRESHOLD_HALFFULL:
+      if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    case DMA_FIFO_THRESHOLD_FULL:
+      break;
+    default:
+      break;
+    }
+  }
+  
+  /* Memory Data size equal to Half-Word */
+  else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
+  {
+    switch (tmp)
+    {
+    case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+      status = HAL_ERROR;
+      break;
+    case DMA_FIFO_THRESHOLD_HALFFULL:
+      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    case DMA_FIFO_THRESHOLD_FULL:
+      if (hdma->Init.MemBurst == DMA_MBURST_INC16)
+      {
+        status = HAL_ERROR;
+      }
+      break;   
+    default:
+      break;
+    }
+  }
+  
+  /* Memory Data size equal to Word */
+  else
+  {
+    switch (tmp)
+    {
+    case DMA_FIFO_THRESHOLD_1QUARTERFULL:
+    case DMA_FIFO_THRESHOLD_HALFFULL:
+    case DMA_FIFO_THRESHOLD_3QUARTERSFULL:
+      status = HAL_ERROR;
+      break;
+    case DMA_FIFO_THRESHOLD_FULL:
+      if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1)
+      {
+        status = HAL_ERROR;
+      }
+      break;
+    default:
+      break;
+    }
+  } 
+  
+  return status; 
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c
index 7167e77..d38cfcd 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c
@@ -1,313 +1,313 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_dma_ex.c
-  * @author  MCD Application Team
-  * @brief   DMA Extension HAL module driver
-  *         This file provides firmware functions to manage the following 
-  *         functionalities of the DMA Extension peripheral:
-  *           + Extended features functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-  The DMA Extension HAL driver can be used as follows:
-   (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
-       for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
-                   
-     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
-     -@-  When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
-     -@-  In Multi (Double) buffer mode, it is possible to update the base address for 
-          the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. 
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DMAEx DMAEx
-  * @brief DMA Extended HAL module driver
-  * @{
-  */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private Constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup DMAEx_Private_Functions
-  * @{
-  */
-static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @addtogroup DMAEx_Exported_Functions
-  * @{
-  */
-
-
-/** @addtogroup DMAEx_Exported_Functions_Group1
-  *
-@verbatim   
- ===============================================================================
-                #####  Extended features functions  #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Configure the source, destination address and data length and 
-          Start MultiBuffer DMA transfer
-      (+) Configure the source, destination address and data length and 
-          Start MultiBuffer DMA transfer with interrupt
-      (+) Change on the fly the memory0 or memory1 address.
-      
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Starts the multi_buffer DMA Transfer.
-  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.  
-  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress The destination memory Buffer address
-  * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  
-  * @param  DataLength The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-  
-  /* Memory-to-memory transfer not supported in double buffering mode */
-  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Process Locked */
-    __HAL_LOCK(hdma);
-    
-    if(HAL_DMA_STATE_READY == hdma->State)
-    {
-      /* Change DMA peripheral state */
-      hdma->State = HAL_DMA_STATE_BUSY; 
-      
-      /* Enable the double buffer mode */
-      hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
-      
-      /* Configure DMA Stream destination address */
-      hdma->Instance->M1AR = SecondMemAddress;
-      
-      /* Configure the source, destination address and the data length */
-      DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
-      
-      /* Enable the peripheral */
-      __HAL_DMA_ENABLE(hdma);
-    }
-    else
-    {
-      /* Return error status */
-      status = HAL_BUSY;
-    }
-  }
-  return status;
-}
-
-/**
-  * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.
-  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.  
-  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress The destination memory Buffer address
-  * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  
-  * @param  DataLength The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-  
-  /* Memory-to-memory transfer not supported in double buffering mode */
-  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
-    return HAL_ERROR;
-  }
-  
-  /* Check callback functions */
-  if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback))
-  {
-    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
-    return HAL_ERROR;
-  }
-  
-  /* Process locked */
-  __HAL_LOCK(hdma);
-  
-  if(HAL_DMA_STATE_READY == hdma->State)
-  {
-    /* Change DMA peripheral state */
-    hdma->State = HAL_DMA_STATE_BUSY;
-    
-    /* Initialize the error code */
-    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-    
-    /* Enable the Double buffer mode */
-    hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
-    
-    /* Configure DMA Stream destination address */
-    hdma->Instance->M1AR = SecondMemAddress;
-    
-    /* Configure the source, destination address and the data length */
-    DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); 
-    
-    /* Clear all flags */
-    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
-    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
-    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
-
-    /* Enable Common interrupts*/
-    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
-    hdma->Instance->FCR |= DMA_IT_FE;
-    
-    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
-    {
-      hdma->Instance->CR  |= DMA_IT_HT;
-    }
-    
-    /* Enable the peripheral */
-    __HAL_DMA_ENABLE(hdma); 
-  }
-  else
-  {     
-    /* Process unlocked */
-    __HAL_UNLOCK(hdma);	  
-    
-    /* Return error status */
-    status = HAL_BUSY;
-  }  
-  return status; 
-}
-
-/**
-  * @brief  Change the memory0 or memory1 address on the fly.
-  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.  
-  * @param  Address    The new address
-  * @param  memory     the memory to be changed, This parameter can be one of 
-  *                     the following values:
-  *                      MEMORY0 /
-  *                      MEMORY1
-  * @note   The MEMORY0 address can be changed only when the current transfer use
-  *         MEMORY1 and the MEMORY1 address can be changed only when the current 
-  *         transfer use MEMORY0.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
-{
-  if(memory == MEMORY0)
-  {
-    /* change the memory0 address */
-    hdma->Instance->M0AR = Address;
-  }
-  else
-  {
-    /* change the memory1 address */
-    hdma->Instance->M1AR = Address;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMAEx_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Set the DMA Transfer parameter.
-  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Stream.  
-  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress The destination memory Buffer address
-  * @param  DataLength The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{  
-  /* Configure DMA Stream data length */
-  hdma->Instance->NDTR = DataLength;
-  
-  /* Peripheral to Memory */
-  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
-  {   
-    /* Configure DMA Stream destination address */
-    hdma->Instance->PAR = DstAddress;
-    
-    /* Configure DMA Stream source address */
-    hdma->Instance->M0AR = SrcAddress;
-  }
-  /* Memory to Peripheral */
-  else
-  {
-    /* Configure DMA Stream source address */
-    hdma->Instance->PAR = SrcAddress;
-    
-    /* Configure DMA Stream destination address */
-    hdma->Instance->M0AR = DstAddress;
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_DMA_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_dma_ex.c
+  * @author  MCD Application Team
+  * @brief   DMA Extension HAL module driver
+  *         This file provides firmware functions to manage the following 
+  *         functionalities of the DMA Extension peripheral:
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+  The DMA Extension HAL driver can be used as follows:
+   (#) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
+       for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
+                   
+     -@-  In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
+     -@-  When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
+     -@-  In Multi (Double) buffer mode, it is possible to update the base address for 
+          the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled. 
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMAEx DMAEx
+  * @brief DMA Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private Constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup DMAEx_Private_Functions
+  * @{
+  */
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @addtogroup DMAEx_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup DMAEx_Exported_Functions_Group1
+  *
+@verbatim   
+ ===============================================================================
+                #####  Extended features functions  #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and 
+          Start MultiBuffer DMA transfer
+      (+) Configure the source, destination address and data length and 
+          Start MultiBuffer DMA transfer with interrupt
+      (+) Change on the fly the memory0 or memory1 address.
+      
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Starts the multi_buffer DMA Transfer.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Process Locked */
+    __HAL_LOCK(hdma);
+    
+    if(HAL_DMA_STATE_READY == hdma->State)
+    {
+      /* Change DMA peripheral state */
+      hdma->State = HAL_DMA_STATE_BUSY; 
+      
+      /* Enable the double buffer mode */
+      hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+      
+      /* Configure DMA Stream destination address */
+      hdma->Instance->M1AR = SecondMemAddress;
+      
+      /* Configure the source, destination address and the data length */
+      DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
+      
+      /* Enable the peripheral */
+      __HAL_DMA_ENABLE(hdma);
+    }
+    else
+    {
+      /* Return error status */
+      status = HAL_BUSY;
+    }
+  }
+  return status;
+}
+
+/**
+  * @brief  Starts the multi_buffer DMA Transfer with interrupt enabled.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  SecondMemAddress The second memory Buffer address in case of multi buffer Transfer  
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+  
+  /* Memory-to-memory transfer not supported in double buffering mode */
+  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
+    return HAL_ERROR;
+  }
+  
+  /* Check callback functions */
+  if ((NULL == hdma->XferCpltCallback) || (NULL == hdma->XferM1CpltCallback) || (NULL == hdma->XferErrorCallback))
+  {
+    hdma->ErrorCode = HAL_DMA_ERROR_PARAM;
+    return HAL_ERROR;
+  }
+  
+  /* Process locked */
+  __HAL_LOCK(hdma);
+  
+  if(HAL_DMA_STATE_READY == hdma->State)
+  {
+    /* Change DMA peripheral state */
+    hdma->State = HAL_DMA_STATE_BUSY;
+    
+    /* Initialize the error code */
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+    
+    /* Enable the Double buffer mode */
+    hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
+    
+    /* Configure DMA Stream destination address */
+    hdma->Instance->M1AR = SecondMemAddress;
+    
+    /* Configure the source, destination address and the data length */
+    DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength); 
+    
+    /* Clear all flags */
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
+    __HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
+
+    /* Enable Common interrupts*/
+    hdma->Instance->CR  |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
+    hdma->Instance->FCR |= DMA_IT_FE;
+    
+    if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
+    {
+      hdma->Instance->CR  |= DMA_IT_HT;
+    }
+    
+    /* Enable the peripheral */
+    __HAL_DMA_ENABLE(hdma); 
+  }
+  else
+  {     
+    /* Process unlocked */
+    __HAL_UNLOCK(hdma);	  
+    
+    /* Return error status */
+    status = HAL_BUSY;
+  }  
+  return status; 
+}
+
+/**
+  * @brief  Change the memory0 or memory1 address on the fly.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  Address    The new address
+  * @param  memory     the memory to be changed, This parameter can be one of 
+  *                     the following values:
+  *                      MEMORY0 /
+  *                      MEMORY1
+  * @note   The MEMORY0 address can be changed only when the current transfer use
+  *         MEMORY1 and the MEMORY1 address can be changed only when the current 
+  *         transfer use MEMORY0.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory)
+{
+  if(memory == MEMORY0)
+  {
+    /* change the memory0 address */
+    hdma->Instance->M0AR = Address;
+  }
+  else
+  {
+    /* change the memory1 address */
+    hdma->Instance->M1AR = Address;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMAEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Set the DMA Transfer parameter.
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Stream.  
+  * @param  SrcAddress The source memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
+  * @param  DataLength The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{  
+  /* Configure DMA Stream data length */
+  hdma->Instance->NDTR = DataLength;
+  
+  /* Peripheral to Memory */
+  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  {   
+    /* Configure DMA Stream destination address */
+    hdma->Instance->PAR = DstAddress;
+    
+    /* Configure DMA Stream source address */
+    hdma->Instance->M0AR = SrcAddress;
+  }
+  /* Memory to Peripheral */
+  else
+  {
+    /* Configure DMA Stream source address */
+    hdma->Instance->PAR = SrcAddress;
+    
+    /* Configure DMA Stream destination address */
+    hdma->Instance->M0AR = DstAddress;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c
index 04b5215..f0eff70 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.c
@@ -1,547 +1,547 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_exti.c
-  * @author  MCD Application Team
-  * @brief   EXTI HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2018 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  @verbatim
-  ==============================================================================
-                    ##### EXTI Peripheral features #####
-  ==============================================================================
-  [..]
-    (+) Each Exti line can be configured within this driver.
-
-    (+) Exti line can be configured in 3 different modes
-        (++) Interrupt
-        (++) Event
-        (++) Both of them
-
-    (+) Configurable Exti lines can be configured with 3 different triggers
-        (++) Rising
-        (++) Falling
-        (++) Both of them
-
-    (+) When set in interrupt mode, configurable Exti lines have two different
-        interrupts pending registers which allow to distinguish which transition
-        occurs:
-        (++) Rising edge pending interrupt
-        (++) Falling
-
-    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
-        be selected through multiplexer.
-
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]
-
-    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
-        (++) Choose the interrupt line number by setting "Line" member from
-             EXTI_ConfigTypeDef structure.
-        (++) Configure the interrupt and/or event mode using "Mode" member from
-             EXTI_ConfigTypeDef structure.
-        (++) For configurable lines, configure rising and/or falling trigger
-             "Trigger" member from EXTI_ConfigTypeDef structure.
-        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
-             member from GPIO_InitTypeDef structure.
-
-    (#) Get current Exti configuration of a dedicated line using
-        HAL_EXTI_GetConfigLine().
-        (++) Provide exiting handle as parameter.
-        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
-
-    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
-        (++) Provide exiting handle as parameter.
-
-    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
-        (++) Provide exiting handle as first parameter.
-        (++) Provide which callback will be registered using one value from
-             EXTI_CallbackIDTypeDef.
-        (++) Provide callback function pointer.
-
-    (#) Get interrupt pending bit using HAL_EXTI_GetPending().
-
-    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
-
-    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
-
-  @endverbatim
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup EXTI
-  * @{
-  */
-/** MISRA C:2012 deviation rule has been granted for following rule:
-  * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
-  * of bounds [0,3] in following API :
-  * HAL_EXTI_SetConfigLine
-  * HAL_EXTI_GetConfigLine
-  * HAL_EXTI_ClearConfigLine
-  */
-
-#ifdef HAL_EXTI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private defines -----------------------------------------------------------*/
-/** @defgroup EXTI_Private_Constants EXTI Private Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Private macros ------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup EXTI_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup EXTI_Exported_Functions_Group1
-  *  @brief    Configuration functions
-  *
-@verbatim
- ===============================================================================
-              ##### Configuration functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set configuration of a dedicated Exti line.
-  * @param  hexti Exti handle.
-  * @param  pExtiConfig Pointer on EXTI configuration to be set.
-  * @retval HAL Status.
-  */
-HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
-{
-  uint32_t regval;
-  uint32_t linepos;
-  uint32_t maskline;
-
-  /* Check null pointer */
-  if ((hexti == NULL) || (pExtiConfig == NULL))
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check parameters */
-  assert_param(IS_EXTI_LINE(pExtiConfig->Line));
-  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
-
-  /* Assign line number to handle */
-  hexti->Line = pExtiConfig->Line;
-
-  /* Compute line mask */
-  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
-  maskline = (1uL << linepos);
-
-  /* Configure triggers for configurable lines */
-  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
-  {
-    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
-
-    /* Configure rising trigger */
-    /* Mask or set line */
-    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
-    {
-      EXTI->RTSR |= maskline;
-    }
-    else
-    {
-      EXTI->RTSR &= ~maskline;
-    }
-
-    /* Configure falling trigger */
-    /* Mask or set line */
-    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
-    {
-      EXTI->FTSR |= maskline;
-    }
-    else
-    {
-      EXTI->FTSR &= ~maskline;
-    }
-
-
-    /* Configure gpio port selection in case of gpio exti line */
-    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
-    {
-      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
-      assert_param(IS_EXTI_GPIO_PIN(linepos));
-
-      regval = SYSCFG->EXTICR[linepos >> 2u];
-      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
-      regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
-      SYSCFG->EXTICR[linepos >> 2u] = regval;
-    }
-  }
-
-  /* Configure interrupt mode : read current mode */
-  /* Mask or set line */
-  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
-  {
-    EXTI->IMR |= maskline;
-  }
-  else
-  {
-    EXTI->IMR &= ~maskline;
-  }
-
-  /* Configure event mode : read current mode */
-  /* Mask or set line */
-  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
-  {
-    EXTI->EMR |= maskline;
-  }
-  else
-  {
-    EXTI->EMR &= ~maskline;
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get configuration of a dedicated Exti line.
-  * @param  hexti Exti handle.
-  * @param  pExtiConfig Pointer on structure to store Exti configuration.
-  * @retval HAL Status.
-  */
-HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
-{
-  uint32_t regval;
-  uint32_t linepos;
-  uint32_t maskline;
-
-  /* Check null pointer */
-  if ((hexti == NULL) || (pExtiConfig == NULL))
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameter */
-  assert_param(IS_EXTI_LINE(hexti->Line));
-
-  /* Store handle line number to configuration structure */
-  pExtiConfig->Line = hexti->Line;
-
-  /* Compute line mask */
-  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
-  maskline = (1uL << linepos);
-
-  /* 1] Get core mode : interrupt */
-
-  /* Check if selected line is enable */
-  if ((EXTI->IMR & maskline) != 0x00u)
-  {
-    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
-  }
-  else
-  {
-    pExtiConfig->Mode = EXTI_MODE_NONE;
-  }
-
-  /* Get event mode */
-  /* Check if selected line is enable */
-  if ((EXTI->EMR & maskline) != 0x00u)
-  {
-    pExtiConfig->Mode |= EXTI_MODE_EVENT;
-  }
-
-  /* Get default Trigger and GPIOSel configuration */
-  pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
-  pExtiConfig->GPIOSel = 0x00u;
-
-  /* 2] Get trigger for configurable lines : rising */
-  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
-  {
-    /* Check if configuration of selected line is enable */
-    if ((EXTI->RTSR & maskline) != 0x00u)
-    {
-      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
-    }
-
-    /* Get falling configuration */
-    /* Check if configuration of selected line is enable */
-    if ((EXTI->FTSR & maskline) != 0x00u)
-    {
-      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
-    }
-
-    /* Get Gpio port selection for gpio lines */
-    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
-    {
-      assert_param(IS_EXTI_GPIO_PIN(linepos));
-
-      regval = (SYSCFG->EXTICR[linepos >> 2u] << 16u );
-      pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 28u);
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Clear whole configuration of a dedicated Exti line.
-  * @param  hexti Exti handle.
-  * @retval HAL Status.
-  */
-HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
-{
-  uint32_t regval;
-  uint32_t linepos;
-  uint32_t maskline;
-
-  /* Check null pointer */
-  if (hexti == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameter */
-  assert_param(IS_EXTI_LINE(hexti->Line));
-
-  /* compute line mask */
-  linepos = (hexti->Line & EXTI_PIN_MASK);
-  maskline = (1uL << linepos);
-
-  /* 1] Clear interrupt mode */
-  EXTI->IMR = (EXTI->IMR & ~maskline);
-
-  /* 2] Clear event mode */
-  EXTI->EMR = (EXTI->EMR & ~maskline);
-
-  /* 3] Clear triggers in case of configurable lines */
-  if ((hexti->Line & EXTI_CONFIG) != 0x00u)
-  {
-    EXTI->RTSR = (EXTI->RTSR & ~maskline);
-    EXTI->FTSR = (EXTI->FTSR & ~maskline);
-
-    /* Get Gpio port selection for gpio lines */
-    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
-    {
-      assert_param(IS_EXTI_GPIO_PIN(linepos));
-
-      regval = SYSCFG->EXTICR[linepos >> 2u];
-      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
-      SYSCFG->EXTICR[linepos >> 2u] = regval;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Register callback for a dedicated Exti line.
-  * @param  hexti Exti handle.
-  * @param  CallbackID User callback identifier.
-  *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
-  * @param  pPendingCbfn function pointer to be stored as callback.
-  * @retval HAL Status.
-  */
-HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  switch (CallbackID)
-  {
-    case  HAL_EXTI_COMMON_CB_ID:
-      hexti->PendingCallback = pPendingCbfn;
-      break;
-
-    default:
-      status = HAL_ERROR;
-      break;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Store line number as handle private field.
-  * @param  hexti Exti handle.
-  * @param  ExtiLine Exti line number.
-  *         This parameter can be from 0 to @ref EXTI_LINE_NB.
-  * @retval HAL Status.
-  */
-HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
-{
-  /* Check the parameters */
-  assert_param(IS_EXTI_LINE(ExtiLine));
-
-  /* Check null pointer */
-  if (hexti == NULL)
-  {
-    return HAL_ERROR;
-  }
-  else
-  {
-    /* Store line number as handle private field */
-    hexti->Line = ExtiLine;
-
-    return HAL_OK;
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup EXTI_Exported_Functions_Group2
-  *  @brief EXTI IO functions.
-  *
-@verbatim
- ===============================================================================
-                       ##### IO operation functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Handle EXTI interrupt request.
-  * @param  hexti Exti handle.
-  * @retval none.
-  */
-void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
-{
-  uint32_t regval;
-  uint32_t maskline;
-
-  /* Compute line mask */
-  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
-  /* Get pending bit  */
-  regval = (EXTI->PR & maskline);
-  if (regval != 0x00u)
-  {
-    /* Clear pending bit */
-    EXTI->PR = maskline;
-
-    /* Call callback */
-    if (hexti->PendingCallback != NULL)
-    {
-      hexti->PendingCallback();
-    }
-  }
-}
-
-/**
-  * @brief  Get interrupt pending bit of a dedicated line.
-  * @param  hexti Exti handle.
-  * @param  Edge Specify which pending edge as to be checked.
-  *         This parameter can be one of the following values:
-  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
-  *         This parameter is kept for compatibility with other series.
-  * @retval 1 if interrupt is pending else 0.
-  */
-uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
-{
-  uint32_t regval;
-  uint32_t linepos;
-  uint32_t maskline;
-
-  /* Check parameters */
-  assert_param(IS_EXTI_LINE(hexti->Line));
-  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
-  assert_param(IS_EXTI_PENDING_EDGE(Edge));
-
-  /* Compute line mask */
-  linepos = (hexti->Line & EXTI_PIN_MASK);
-  maskline = (1uL << linepos);
-
-  /* return 1 if bit is set else 0 */
-  regval = ((EXTI->PR & maskline) >> linepos);
-  return regval;
-}
-
-/**
-  * @brief  Clear interrupt pending bit of a dedicated line.
-  * @param  hexti Exti handle.
-  * @param  Edge Specify which pending edge as to be clear.
-  *         This parameter can be one of the following values:
-  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
-  *         This parameter is kept for compatibility with other series.
-  * @retval None.
-  */
-void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
-{
-  uint32_t maskline;
-
-  /* Check parameters */
-  assert_param(IS_EXTI_LINE(hexti->Line));
-  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
-  assert_param(IS_EXTI_PENDING_EDGE(Edge));
-
-  /* Compute line mask */
-  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
-  /* Clear Pending bit */
-  EXTI->PR =  maskline;
-}
-
-/**
-  * @brief  Generate a software interrupt for a dedicated line.
-  * @param  hexti Exti handle.
-  * @retval None.
-  */
-void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
-{
-  uint32_t maskline;
-
-  /* Check parameters */
-  assert_param(IS_EXTI_LINE(hexti->Line));
-  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
-
-  /* Compute line mask */
-  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
-
-  /* Generate Software interrupt */
-  EXTI->SWIER = maskline;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_EXTI_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_exti.c
+  * @author  MCD Application Team
+  * @brief   EXTI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Extended Interrupts and events controller (EXTI) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### EXTI Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each Exti line can be configured within this driver.
+
+    (+) Exti line can be configured in 3 different modes
+        (++) Interrupt
+        (++) Event
+        (++) Both of them
+
+    (+) Configurable Exti lines can be configured with 3 different triggers
+        (++) Rising
+        (++) Falling
+        (++) Both of them
+
+    (+) When set in interrupt mode, configurable Exti lines have two different
+        interrupts pending registers which allow to distinguish which transition
+        occurs:
+        (++) Rising edge pending interrupt
+        (++) Falling
+
+    (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
+        be selected through multiplexer.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+
+    (#) Configure the EXTI line using HAL_EXTI_SetConfigLine().
+        (++) Choose the interrupt line number by setting "Line" member from
+             EXTI_ConfigTypeDef structure.
+        (++) Configure the interrupt and/or event mode using "Mode" member from
+             EXTI_ConfigTypeDef structure.
+        (++) For configurable lines, configure rising and/or falling trigger
+             "Trigger" member from EXTI_ConfigTypeDef structure.
+        (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel"
+             member from GPIO_InitTypeDef structure.
+
+    (#) Get current Exti configuration of a dedicated line using
+        HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+        (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
+
+    (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
+        (++) Provide exiting handle as parameter.
+
+    (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
+        (++) Provide exiting handle as first parameter.
+        (++) Provide which callback will be registered using one value from
+             EXTI_CallbackIDTypeDef.
+        (++) Provide callback function pointer.
+
+    (#) Get interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Clear interrupt pending bit using HAL_EXTI_GetPending().
+
+    (#) Generate software interrupt using HAL_EXTI_GenerateSWI().
+
+  @endverbatim
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+/** MISRA C:2012 deviation rule has been granted for following rule:
+  * Rule-18.1_b - Medium: Array `EXTICR' 1st subscript interval [0,7] may be out
+  * of bounds [0,3] in following API :
+  * HAL_EXTI_SetConfigLine
+  * HAL_EXTI_GetConfigLine
+  * HAL_EXTI_ClearConfigLine
+  */
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup EXTI_Private_Constants EXTI Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup EXTI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group1
+  *  @brief    Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on EXTI configuration to be set.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(pExtiConfig->Line));
+  assert_param(IS_EXTI_MODE(pExtiConfig->Mode));
+
+  /* Assign line number to handle */
+  hexti->Line = pExtiConfig->Line;
+
+  /* Compute line mask */
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* Configure triggers for configurable lines */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+  {
+    assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger));
+
+    /* Configure rising trigger */
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0x00u)
+    {
+      EXTI->RTSR |= maskline;
+    }
+    else
+    {
+      EXTI->RTSR &= ~maskline;
+    }
+
+    /* Configure falling trigger */
+    /* Mask or set line */
+    if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0x00u)
+    {
+      EXTI->FTSR |= maskline;
+    }
+    else
+    {
+      EXTI->FTSR &= ~maskline;
+    }
+
+
+    /* Configure gpio port selection in case of gpio exti line */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel));
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[linepos >> 2u];
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      regval |= (pExtiConfig->GPIOSel << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      SYSCFG->EXTICR[linepos >> 2u] = regval;
+    }
+  }
+
+  /* Configure interrupt mode : read current mode */
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0x00u)
+  {
+    EXTI->IMR |= maskline;
+  }
+  else
+  {
+    EXTI->IMR &= ~maskline;
+  }
+
+  /* Configure event mode : read current mode */
+  /* Mask or set line */
+  if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0x00u)
+  {
+    EXTI->EMR |= maskline;
+  }
+  else
+  {
+    EXTI->EMR &= ~maskline;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  pExtiConfig Pointer on structure to store Exti configuration.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig)
+{
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+
+  /* Check null pointer */
+  if ((hexti == NULL) || (pExtiConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* Store handle line number to configuration structure */
+  pExtiConfig->Line = hexti->Line;
+
+  /* Compute line mask */
+  linepos = (pExtiConfig->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* 1] Get core mode : interrupt */
+
+  /* Check if selected line is enable */
+  if ((EXTI->IMR & maskline) != 0x00u)
+  {
+    pExtiConfig->Mode = EXTI_MODE_INTERRUPT;
+  }
+  else
+  {
+    pExtiConfig->Mode = EXTI_MODE_NONE;
+  }
+
+  /* Get event mode */
+  /* Check if selected line is enable */
+  if ((EXTI->EMR & maskline) != 0x00u)
+  {
+    pExtiConfig->Mode |= EXTI_MODE_EVENT;
+  }
+
+  /* Get default Trigger and GPIOSel configuration */
+  pExtiConfig->Trigger = EXTI_TRIGGER_NONE;
+  pExtiConfig->GPIOSel = 0x00u;
+
+  /* 2] Get trigger for configurable lines : rising */
+  if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u)
+  {
+    /* Check if configuration of selected line is enable */
+    if ((EXTI->RTSR & maskline) != 0x00u)
+    {
+      pExtiConfig->Trigger = EXTI_TRIGGER_RISING;
+    }
+
+    /* Get falling configuration */
+    /* Check if configuration of selected line is enable */
+    if ((EXTI->FTSR & maskline) != 0x00u)
+    {
+      pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING;
+    }
+
+    /* Get Gpio port selection for gpio lines */
+    if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = (SYSCFG->EXTICR[linepos >> 2u] << 16u );
+      pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 28u);
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Clear whole configuration of a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti)
+{
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+
+  /* compute line mask */
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* 1] Clear interrupt mode */
+  EXTI->IMR = (EXTI->IMR & ~maskline);
+
+  /* 2] Clear event mode */
+  EXTI->EMR = (EXTI->EMR & ~maskline);
+
+  /* 3] Clear triggers in case of configurable lines */
+  if ((hexti->Line & EXTI_CONFIG) != 0x00u)
+  {
+    EXTI->RTSR = (EXTI->RTSR & ~maskline);
+    EXTI->FTSR = (EXTI->FTSR & ~maskline);
+
+    /* Get Gpio port selection for gpio lines */
+    if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO)
+    {
+      assert_param(IS_EXTI_GPIO_PIN(linepos));
+
+      regval = SYSCFG->EXTICR[linepos >> 2u];
+      regval &= ~(SYSCFG_EXTICR1_EXTI0 << (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u)));
+      SYSCFG->EXTICR[linepos >> 2u] = regval;
+    }
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Register callback for a dedicated Exti line.
+  * @param  hexti Exti handle.
+  * @param  CallbackID User callback identifier.
+  *         This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values.
+  * @param  pPendingCbfn function pointer to be stored as callback.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void))
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  switch (CallbackID)
+  {
+    case  HAL_EXTI_COMMON_CB_ID:
+      hexti->PendingCallback = pPendingCbfn;
+      break;
+
+    default:
+      status = HAL_ERROR;
+      break;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Store line number as handle private field.
+  * @param  hexti Exti handle.
+  * @param  ExtiLine Exti line number.
+  *         This parameter can be from 0 to @ref EXTI_LINE_NB.
+  * @retval HAL Status.
+  */
+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(ExtiLine));
+
+  /* Check null pointer */
+  if (hexti == NULL)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Store line number as handle private field */
+    hexti->Line = ExtiLine;
+
+    return HAL_OK;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup EXTI_Exported_Functions_Group2
+  *  @brief EXTI IO functions.
+  *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  hexti Exti handle.
+  * @retval none.
+  */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+  uint32_t regval;
+  uint32_t maskline;
+
+  /* Compute line mask */
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  /* Get pending bit  */
+  regval = (EXTI->PR & maskline);
+  if (regval != 0x00u)
+  {
+    /* Clear pending bit */
+    EXTI->PR = maskline;
+
+    /* Call callback */
+    if (hexti->PendingCallback != NULL)
+    {
+      hexti->PendingCallback();
+    }
+  }
+}
+
+/**
+  * @brief  Get interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be checked.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+  *         This parameter is kept for compatibility with other series.
+  * @retval 1 if interrupt is pending else 0.
+  */
+uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  uint32_t regval;
+  uint32_t linepos;
+  uint32_t maskline;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* Compute line mask */
+  linepos = (hexti->Line & EXTI_PIN_MASK);
+  maskline = (1uL << linepos);
+
+  /* return 1 if bit is set else 0 */
+  regval = ((EXTI->PR & maskline) >> linepos);
+  return regval;
+}
+
+/**
+  * @brief  Clear interrupt pending bit of a dedicated line.
+  * @param  hexti Exti handle.
+  * @param  Edge Specify which pending edge as to be clear.
+  *         This parameter can be one of the following values:
+  *           @arg @ref EXTI_TRIGGER_RISING_FALLING
+  *         This parameter is kept for compatibility with other series.
+  * @retval None.
+  */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
+{
+  uint32_t maskline;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+  assert_param(IS_EXTI_PENDING_EDGE(Edge));
+
+  /* Compute line mask */
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  /* Clear Pending bit */
+  EXTI->PR =  maskline;
+}
+
+/**
+  * @brief  Generate a software interrupt for a dedicated line.
+  * @param  hexti Exti handle.
+  * @retval None.
+  */
+void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti)
+{
+  uint32_t maskline;
+
+  /* Check parameters */
+  assert_param(IS_EXTI_LINE(hexti->Line));
+  assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
+
+  /* Compute line mask */
+  maskline = (1uL << (hexti->Line & EXTI_PIN_MASK));
+
+  /* Generate Software interrupt */
+  EXTI->SWIER = maskline;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_EXTI_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c
index 2830da0..d18f66f 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.c
@@ -1,775 +1,775 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_flash.c
-  * @author  MCD Application Team
-  * @brief   FLASH HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the internal FLASH memory:
-  *           + Program operations functions
-  *           + Memory Control functions 
-  *           + Peripheral Errors functions
-  *         
-  @verbatim
-  ==============================================================================
-                        ##### FLASH peripheral features #####
-  ==============================================================================
-           
-  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses 
-       to the Flash memory. It implements the erase and program Flash memory operations 
-       and the read and write protection mechanisms.
-      
-  [..] The Flash memory interface accelerates code execution with a system of instruction
-       prefetch and cache lines. 
-
-  [..] The FLASH main features are:
-      (+) Flash memory read operations
-      (+) Flash memory program/erase operations
-      (+) Read / write protections
-      (+) Prefetch on I-Code
-      (+) 64 cache lines of 128 bits on I-Code
-      (+) 8 cache lines of 128 bits on D-Code
-      
-      
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]                             
-      This driver provides functions and macros to configure and program the FLASH 
-      memory of all STM32F4xx devices.
-    
-      (#) FLASH Memory IO Programming functions: 
-           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
-                HAL_FLASH_Lock() functions
-           (++) Program functions: byte, half word, word and double word
-           (++) There Two modes of programming :
-            (+++) Polling mode using HAL_FLASH_Program() function
-            (+++) Interrupt mode using HAL_FLASH_Program_IT() function
-    
-      (#) Interrupts and flags management functions : 
-           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
-           (++) Wait for last FLASH operation according to its status
-           (++) Get error flag status by calling HAL_SetErrorCode()          
-
-    [..] 
-      In addition to these functions, this driver includes a set of macros allowing
-      to handle the following operations:
-       (+) Set the latency
-       (+) Enable/Disable the prefetch buffer
-       (+) Enable/Disable the Instruction cache and the Data cache
-       (+) Reset the Instruction cache and the Data cache
-       (+) Enable/Disable the FLASH interrupts
-       (+) Monitor the FLASH flags status
-          
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup FLASH FLASH
-  * @brief FLASH HAL module driver
-  * @{
-  */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup FLASH_Private_Constants
-  * @{
-  */
-#define FLASH_TIMEOUT_VALUE       50000U /* 50 s */
-/**
-  * @}
-  */         
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup FLASH_Private_Variables
-  * @{
-  */
-/* Variable used for Erase sectors under interruption */
-FLASH_ProcessTypeDef pFlash;
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup FLASH_Private_Functions
-  * @{
-  */
-/* Program operations */
-static void   FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
-static void   FLASH_Program_Word(uint32_t Address, uint32_t Data);
-static void   FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
-static void   FLASH_Program_Byte(uint32_t Address, uint8_t Data);
-static void   FLASH_SetErrorCode(void);
-
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
-  * @{
-  */
-  
-/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions 
- *  @brief   Programming operation functions 
- *
-@verbatim   
- ===============================================================================
-                  ##### Programming operation functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to manage the FLASH 
-    program operations.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Program byte, halfword, word or double word at a specified address
-  * @param  TypeProgram  Indicate the way to program at a specified address.
-  *                           This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address  specifies the address to be programmed.
-  * @param  Data specifies the data to be programmed
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-  
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
-    {
-      /*Program byte (8-bit) at a specified address.*/
-      FLASH_Program_Byte(Address, (uint8_t) Data);
-    }
-    else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
-    {
-      /*Program halfword (16-bit) at a specified address.*/
-      FLASH_Program_HalfWord(Address, (uint16_t) Data);
-    }
-    else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
-    {
-      /*Program word (32-bit) at a specified address.*/
-      FLASH_Program_Word(Address, (uint32_t) Data);
-    }
-    else
-    {
-      /*Program double word (64-bit) at a specified address.*/
-      FLASH_Program_DoubleWord(Address, Data);
-    }
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-    
-    /* If the program operation is completed, disable the PG Bit */
-    FLASH->CR &= (~FLASH_CR_PG);  
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-  
-  return status;
-}
-
-/**
-  * @brief   Program byte, halfword, word or double word at a specified address  with interrupt enabled.
-  * @param  TypeProgram  Indicate the way to program at a specified address.
-  *                           This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address  specifies the address to be programmed.
-  * @param  Data specifies the data to be programmed
-  * 
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
-
-  /* Enable End of FLASH Operation interrupt */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
-  
-  /* Enable Error source interrupt */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
-
-  pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
-  pFlash.Address = Address;
-
-  if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
-  {
-    /*Program byte (8-bit) at a specified address.*/
-      FLASH_Program_Byte(Address, (uint8_t) Data);
-  }
-  else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
-  {
-    /*Program halfword (16-bit) at a specified address.*/
-    FLASH_Program_HalfWord(Address, (uint16_t) Data);
-  }
-  else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
-  {
-    /*Program word (32-bit) at a specified address.*/
-    FLASH_Program_Word(Address, (uint32_t) Data);
-  }
-  else
-  {
-    /*Program double word (64-bit) at a specified address.*/
-    FLASH_Program_DoubleWord(Address, Data);
-  }
-
-  return status;
-}
-
-/**
-  * @brief This function handles FLASH interrupt request.
-  * @retval None
-  */
-void HAL_FLASH_IRQHandler(void)
-{
-  uint32_t addresstmp = 0U;
-  
-  /* Check FLASH operation error flags */
-#if defined(FLASH_SR_RDERR) 
-  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
-    FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
-#else
-  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
-    FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
-#endif /* FLASH_SR_RDERR */
-  {
-    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
-    {
-      /*return the faulty sector*/
-      addresstmp = pFlash.Sector;
-      pFlash.Sector = 0xFFFFFFFFU;
-    }
-    else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
-    {
-      /*return the faulty bank*/
-      addresstmp = pFlash.Bank;
-    }
-    else
-    {
-      /*return the faulty address*/
-      addresstmp = pFlash.Address;
-    }
-    
-    /*Save the Error code*/
-    FLASH_SetErrorCode();
-    
-    /* FLASH error interrupt user callback */
-    HAL_FLASH_OperationErrorCallback(addresstmp);
-    
-    /*Stop the procedure ongoing*/
-    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-  }
-  
-  /* Check FLASH End of Operation flag  */
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
-  {
-    /* Clear FLASH End of Operation pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-    
-    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
-    {
-      /*Nb of sector to erased can be decreased*/
-      pFlash.NbSectorsToErase--;
-      
-      /* Check if there are still sectors to erase*/
-      if(pFlash.NbSectorsToErase != 0U)
-      {
-        addresstmp = pFlash.Sector;
-        /*Indicate user which sector has been erased*/
-        HAL_FLASH_EndOfOperationCallback(addresstmp);
-        
-        /*Increment sector number*/
-        pFlash.Sector++;
-        addresstmp = pFlash.Sector;
-        FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase);
-      }
-      else
-      {
-        /*No more sectors to Erase, user callback can be called.*/
-        /*Reset Sector and stop Erase sectors procedure*/
-        pFlash.Sector = addresstmp = 0xFFFFFFFFU;
-        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-        
-        /* Flush the caches to be sure of the data consistency */
-        FLASH_FlushCaches() ;
-                
-        /* FLASH EOP interrupt user callback */
-        HAL_FLASH_EndOfOperationCallback(addresstmp);
-      }
-    }
-    else 
-    {
-      if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) 
-      {
-        /* MassErase ended. Return the selected bank */
-        /* Flush the caches to be sure of the data consistency */
-        FLASH_FlushCaches() ;
-
-        /* FLASH EOP interrupt user callback */
-        HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
-      }
-      else
-      {
-        /*Program ended. Return the selected address*/
-        /* FLASH EOP interrupt user callback */
-        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
-      }
-      pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-    }
-  }
-  
-  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
-  {
-    /* Operation is completed, disable the PG, SER, SNB and MER Bits */
-    CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT));
-
-    /* Disable End of FLASH Operation interrupt */
-    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
-    
-    /* Disable Error source interrupt */
-    __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(&pFlash);
-  }
-}
-
-/**
-  * @brief  FLASH end of operation interrupt callback
-  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
-  *                  Mass Erase: Bank number which has been requested to erase
-  *                  Sectors Erase: Sector which has been erased 
-  *                    (if 0xFFFFFFFFU, it means that all the selected sectors have been erased)
-  *                  Program: Address which was selected for data program
-  * @retval None
-  */
-__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(ReturnValue);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  FLASH operation error interrupt callback
-  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
-  *                 Mass Erase: Bank number which has been requested to erase
-  *                 Sectors Erase: Sector number which returned an error
-  *                 Program: Address which was selected for data program
-  * @retval None
-  */
-__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(ReturnValue);
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions 
- *  @brief   management functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the FLASH 
-    memory operations.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Unlock the FLASH control register access
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Unlock(void)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
-  {
-    /* Authorize the FLASH Registers access */
-    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
-    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
-
-    /* Verify Flash is unlocked */
-    if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
-    {
-      status = HAL_ERROR;
-    }
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Locks the FLASH control register access
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Lock(void)
-{
-  /* Set the LOCK Bit to lock the FLASH Registers access */
-  FLASH->CR |= FLASH_CR_LOCK;
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Unlock the FLASH Option Control Registers access.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
-{
-  if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
-  {
-    /* Authorizes the Option Byte register programming */
-    FLASH->OPTKEYR = FLASH_OPT_KEY1;
-    FLASH->OPTKEYR = FLASH_OPT_KEY2;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }  
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Lock the FLASH Option Control Registers access.
-  * @retval HAL Status 
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
-{
-  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
-  FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Launch the option byte loading.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
-{
-  /* Set the OPTSTRT bit in OPTCR register */
-  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
-
-  /* Wait for last operation to be completed */
-  return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions 
- *  @brief   Peripheral Errors functions 
- *
-@verbatim   
- ===============================================================================
-                ##### Peripheral Errors functions #####
- ===============================================================================  
-    [..]
-    This subsection permits to get in run-time Errors of the FLASH peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Get the specific FLASH error flag.
-  * @retval FLASH_ErrorCode: The returned value can be a combination of:
-  *            @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
-  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag 
-  *            @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag  
-  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
-  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
-  *            @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag 
-  */
-uint32_t HAL_FLASH_GetError(void)
-{ 
-   return pFlash.ErrorCode;
-}  
-  
-/**
-  * @}
-  */    
-
-/**
-  * @brief  Wait for a FLASH operation to complete.
-  * @param  Timeout maximum flash operationtimeout
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
-{ 
-  uint32_t tickstart = 0U;
-  
-  /* Clear Error Code */
-  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
-  
-  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
-     Even if the FLASH operation fails, the BUSY flag will be reset and an error
-     flag will be set */
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) 
-  { 
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        return HAL_TIMEOUT;
-      }
-    } 
-  }
-
-  /* Check FLASH End of Operation flag  */
-  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
-  {
-    /* Clear FLASH End of Operation pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-  }
-#if defined(FLASH_SR_RDERR)  
-  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
-                           FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
-#else
-  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
-                           FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
-#endif /* FLASH_SR_RDERR */
-  {
-    /*Save the error code*/
-    FLASH_SetErrorCode();
-    return HAL_ERROR;
-  }
-
-  /* If there is no error flag set */
-  return HAL_OK;
-  
-}  
-
-/**
-  * @brief  Program a double word (64-bit) at a specified address.
-  * @note   This function must be used when the device voltage range is from
-  *         2.7V to 3.6V and Vpp in the range 7V to 9V.
-  *
-  * @note   If an erase and a program operations are requested simultaneously,    
-  *         the erase operation is performed before the program one.
-  *  
-  * @param  Address specifies the address to be programmed.
-  * @param  Data specifies the data to be programmed.
-  * @retval None
-  */
-static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Address));
-  
-  /* If the previous operation is completed, proceed to program the new data */
-  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-  FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
-  FLASH->CR |= FLASH_CR_PG;
-
-  /* Program first word */
-  *(__IO uint32_t*)Address = (uint32_t)Data;
-
-  /* Barrier to ensure programming is performed in 2 steps, in right order
-    (independently of compiler optimization behavior) */
-  __ISB();
-
-  /* Program second word */
-  *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
-}
-
-
-/**
-  * @brief  Program word (32-bit) at a specified address.
-  * @note   This function must be used when the device voltage range is from
-  *         2.7V to 3.6V.
-  *
-  * @note   If an erase and a program operations are requested simultaneously,    
-  *         the erase operation is performed before the program one.
-  *  
-  * @param  Address specifies the address to be programmed.
-  * @param  Data specifies the data to be programmed.
-  * @retval None
-  */
-static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Address));
-  
-  /* If the previous operation is completed, proceed to program the new data */
-  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-  FLASH->CR |= FLASH_PSIZE_WORD;
-  FLASH->CR |= FLASH_CR_PG;
-
-  *(__IO uint32_t*)Address = Data;
-}
-
-/**
-  * @brief  Program a half-word (16-bit) at a specified address.
-  * @note   This function must be used when the device voltage range is from
-  *         2.1V to 3.6V.
-  *
-  * @note   If an erase and a program operations are requested simultaneously,    
-  *         the erase operation is performed before the program one.
-  *  
-  * @param  Address specifies the address to be programmed.
-  * @param  Data specifies the data to be programmed.
-  * @retval None
-  */
-static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Address));
-  
-  /* If the previous operation is completed, proceed to program the new data */
-  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-  FLASH->CR |= FLASH_PSIZE_HALF_WORD;
-  FLASH->CR |= FLASH_CR_PG;
-
-  *(__IO uint16_t*)Address = Data;
-}
-
-/**
-  * @brief  Program byte (8-bit) at a specified address.
-  * @note   This function must be used when the device voltage range is from
-  *         1.8V to 3.6V.
-  *
-  * @note   If an erase and a program operations are requested simultaneously,    
-  *         the erase operation is performed before the program one.
-  *  
-  * @param  Address specifies the address to be programmed.
-  * @param  Data specifies the data to be programmed.
-  * @retval None
-  */
-static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
-{
-  /* Check the parameters */
-  assert_param(IS_FLASH_ADDRESS(Address));
-  
-  /* If the previous operation is completed, proceed to program the new data */
-  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-  FLASH->CR |= FLASH_PSIZE_BYTE;
-  FLASH->CR |= FLASH_CR_PG;
-
-  *(__IO uint8_t*)Address = Data;
-}
-
-/**
-  * @brief  Set the specific FLASH error flag.
-  * @retval None
-  */
-static void FLASH_SetErrorCode(void)
-{ 
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
-  {
-   pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
-   
-   /* Clear FLASH write protection error pending bit */
-   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR);
-  }
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
-  {
-   pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
-   
-   /* Clear FLASH Programming alignment error pending bit */
-   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR);
-  }
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
-    
-    /* Clear FLASH Programming parallelism error pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR);
-  }
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET)
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;
-    
-    /* Clear FLASH Programming sequence error pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR);
-  }
-#if defined(FLASH_SR_RDERR) 
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
-    
-    /* Clear FLASH Proprietary readout protection error pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR);
-  }
-#endif /* FLASH_SR_RDERR */  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
-  {
-    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
-    
-    /* Clear FLASH Operation error pending bit */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR);
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_flash.c
+  * @author  MCD Application Team
+  * @brief   FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the internal FLASH memory:
+  *           + Program operations functions
+  *           + Memory Control functions 
+  *           + Peripheral Errors functions
+  *         
+  @verbatim
+  ==============================================================================
+                        ##### FLASH peripheral features #####
+  ==============================================================================
+           
+  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses 
+       to the Flash memory. It implements the erase and program Flash memory operations 
+       and the read and write protection mechanisms.
+      
+  [..] The Flash memory interface accelerates code execution with a system of instruction
+       prefetch and cache lines. 
+
+  [..] The FLASH main features are:
+      (+) Flash memory read operations
+      (+) Flash memory program/erase operations
+      (+) Read / write protections
+      (+) Prefetch on I-Code
+      (+) 64 cache lines of 128 bits on I-Code
+      (+) 8 cache lines of 128 bits on D-Code
+      
+      
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]                             
+      This driver provides functions and macros to configure and program the FLASH 
+      memory of all STM32F4xx devices.
+    
+      (#) FLASH Memory IO Programming functions: 
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
+                HAL_FLASH_Lock() functions
+           (++) Program functions: byte, half word, word and double word
+           (++) There Two modes of programming :
+            (+++) Polling mode using HAL_FLASH_Program() function
+            (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+    
+      (#) Interrupts and flags management functions : 
+           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+           (++) Wait for last FLASH operation according to its status
+           (++) Get error flag status by calling HAL_SetErrorCode()          
+
+    [..] 
+      In addition to these functions, this driver includes a set of macros allowing
+      to handle the following operations:
+       (+) Set the latency
+       (+) Enable/Disable the prefetch buffer
+       (+) Enable/Disable the Instruction cache and the Data cache
+       (+) Reset the Instruction cache and the Data cache
+       (+) Enable/Disable the FLASH interrupts
+       (+) Monitor the FLASH flags status
+          
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH FLASH
+  * @brief FLASH HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Constants
+  * @{
+  */
+#define FLASH_TIMEOUT_VALUE       50000U /* 50 s */
+/**
+  * @}
+  */         
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FLASH_Private_Variables
+  * @{
+  */
+/* Variable used for Erase sectors under interruption */
+FLASH_ProcessTypeDef pFlash;
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FLASH_Private_Functions
+  * @{
+  */
+/* Program operations */
+static void   FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
+static void   FLASH_Program_Word(uint32_t Address, uint32_t Data);
+static void   FLASH_Program_HalfWord(uint32_t Address, uint16_t Data);
+static void   FLASH_Program_Byte(uint32_t Address, uint8_t Data);
+static void   FLASH_SetErrorCode(void);
+
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+  * @{
+  */
+  
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions 
+ *  @brief   Programming operation functions 
+ *
+@verbatim   
+ ===============================================================================
+                  ##### Programming operation functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the FLASH 
+    program operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Program byte, halfword, word or double word at a specified address
+  * @param  TypeProgram  Indicate the way to program at a specified address.
+  *                           This parameter can be a value of @ref FLASH_Type_Program
+  * @param  Address  specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed
+  * 
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  
+  if(status == HAL_OK)
+  {
+    if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
+    {
+      /*Program byte (8-bit) at a specified address.*/
+      FLASH_Program_Byte(Address, (uint8_t) Data);
+    }
+    else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+    {
+      /*Program halfword (16-bit) at a specified address.*/
+      FLASH_Program_HalfWord(Address, (uint16_t) Data);
+    }
+    else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+    {
+      /*Program word (32-bit) at a specified address.*/
+      FLASH_Program_Word(Address, (uint32_t) Data);
+    }
+    else
+    {
+      /*Program double word (64-bit) at a specified address.*/
+      FLASH_Program_DoubleWord(Address, Data);
+    }
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+    
+    /* If the program operation is completed, disable the PG Bit */
+    FLASH->CR &= (~FLASH_CR_PG);  
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+  
+  return status;
+}
+
+/**
+  * @brief   Program byte, halfword, word or double word at a specified address  with interrupt enabled.
+  * @param  TypeProgram  Indicate the way to program at a specified address.
+  *                           This parameter can be a value of @ref FLASH_Type_Program
+  * @param  Address  specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+  /* Enable End of FLASH Operation interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+  
+  /* Enable Error source interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+
+  pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
+  pFlash.Address = Address;
+
+  if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
+  {
+    /*Program byte (8-bit) at a specified address.*/
+      FLASH_Program_Byte(Address, (uint8_t) Data);
+  }
+  else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
+  {
+    /*Program halfword (16-bit) at a specified address.*/
+    FLASH_Program_HalfWord(Address, (uint16_t) Data);
+  }
+  else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
+  {
+    /*Program word (32-bit) at a specified address.*/
+    FLASH_Program_Word(Address, (uint32_t) Data);
+  }
+  else
+  {
+    /*Program double word (64-bit) at a specified address.*/
+    FLASH_Program_DoubleWord(Address, Data);
+  }
+
+  return status;
+}
+
+/**
+  * @brief This function handles FLASH interrupt request.
+  * @retval None
+  */
+void HAL_FLASH_IRQHandler(void)
+{
+  uint32_t addresstmp = 0U;
+  
+  /* Check FLASH operation error flags */
+#if defined(FLASH_SR_RDERR) 
+  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+    FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
+#else
+  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+    FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
+#endif /* FLASH_SR_RDERR */
+  {
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
+    {
+      /*return the faulty sector*/
+      addresstmp = pFlash.Sector;
+      pFlash.Sector = 0xFFFFFFFFU;
+    }
+    else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE)
+    {
+      /*return the faulty bank*/
+      addresstmp = pFlash.Bank;
+    }
+    else
+    {
+      /*return the faulty address*/
+      addresstmp = pFlash.Address;
+    }
+    
+    /*Save the Error code*/
+    FLASH_SetErrorCode();
+    
+    /* FLASH error interrupt user callback */
+    HAL_FLASH_OperationErrorCallback(addresstmp);
+    
+    /*Stop the procedure ongoing*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+  }
+  
+  /* Check FLASH End of Operation flag  */
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
+  {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+    
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_SECTERASE)
+    {
+      /*Nb of sector to erased can be decreased*/
+      pFlash.NbSectorsToErase--;
+      
+      /* Check if there are still sectors to erase*/
+      if(pFlash.NbSectorsToErase != 0U)
+      {
+        addresstmp = pFlash.Sector;
+        /*Indicate user which sector has been erased*/
+        HAL_FLASH_EndOfOperationCallback(addresstmp);
+        
+        /*Increment sector number*/
+        pFlash.Sector++;
+        addresstmp = pFlash.Sector;
+        FLASH_Erase_Sector(addresstmp, pFlash.VoltageForErase);
+      }
+      else
+      {
+        /*No more sectors to Erase, user callback can be called.*/
+        /*Reset Sector and stop Erase sectors procedure*/
+        pFlash.Sector = addresstmp = 0xFFFFFFFFU;
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+        
+        /* Flush the caches to be sure of the data consistency */
+        FLASH_FlushCaches() ;
+                
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(addresstmp);
+      }
+    }
+    else 
+    {
+      if(pFlash.ProcedureOnGoing == FLASH_PROC_MASSERASE) 
+      {
+        /* MassErase ended. Return the selected bank */
+        /* Flush the caches to be sure of the data consistency */
+        FLASH_FlushCaches() ;
+
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
+      }
+      else
+      {
+        /*Program ended. Return the selected address*/
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+      }
+      pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+    }
+  }
+  
+  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+  {
+    /* Operation is completed, disable the PG, SER, SNB and MER Bits */
+    CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_SER | FLASH_CR_SNB | FLASH_MER_BIT));
+
+    /* Disable End of FLASH Operation interrupt */
+    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
+    
+    /* Disable Error source interrupt */
+    __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
+    
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+}
+
+/**
+  * @brief  FLASH end of operation interrupt callback
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  *                  Mass Erase: Bank number which has been requested to erase
+  *                  Sectors Erase: Sector which has been erased 
+  *                    (if 0xFFFFFFFFU, it means that all the selected sectors have been erased)
+  *                  Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  FLASH operation error interrupt callback
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
+  *                 Mass Erase: Bank number which has been requested to erase
+  *                 Sectors Erase: Sector number which returned an error
+  *                 Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the FLASH 
+    memory operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlock the FLASH control register access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+  {
+    /* Authorize the FLASH Registers access */
+    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+
+    /* Verify Flash is unlocked */
+    if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Locks the FLASH control register access
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Registers access */
+  FLASH->CR |= FLASH_CR_LOCK;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Unlock the FLASH Option Control Registers access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+  if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
+  {
+    /* Authorizes the Option Byte register programming */
+    FLASH->OPTKEYR = FLASH_OPT_KEY1;
+    FLASH->OPTKEYR = FLASH_OPT_KEY2;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }  
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Lock the FLASH Option Control Registers access.
+  * @retval HAL Status 
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+  FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Launch the option byte loading.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+  /* Set the OPTSTRT bit in OPTCR register */
+  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
+
+  /* Wait for last operation to be completed */
+  return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions 
+ *  @brief   Peripheral Errors functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### Peripheral Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the specific FLASH error flag.
+  * @retval FLASH_ErrorCode: The returned value can be a combination of:
+  *            @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
+  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag 
+  *            @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag  
+  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
+  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
+  *            @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag 
+  */
+uint32_t HAL_FLASH_GetError(void)
+{ 
+   return pFlash.ErrorCode;
+}  
+  
+/**
+  * @}
+  */    
+
+/**
+  * @brief  Wait for a FLASH operation to complete.
+  * @param  Timeout maximum flash operationtimeout
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{ 
+  uint32_t tickstart = 0U;
+  
+  /* Clear Error Code */
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+  
+  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+     Even if the FLASH operation fails, the BUSY flag will be reset and an error
+     flag will be set */
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) 
+  { 
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+      {
+        return HAL_TIMEOUT;
+      }
+    } 
+  }
+
+  /* Check FLASH End of Operation flag  */
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
+  {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+  }
+#if defined(FLASH_SR_RDERR)  
+  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+                           FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR | FLASH_FLAG_RDERR)) != RESET)
+#else
+  if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
+                           FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
+#endif /* FLASH_SR_RDERR */
+  {
+    /*Save the error code*/
+    FLASH_SetErrorCode();
+    return HAL_ERROR;
+  }
+
+  /* If there is no error flag set */
+  return HAL_OK;
+  
+}  
+
+/**
+  * @brief  Program a double word (64-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         2.7V to 3.6V and Vpp in the range 7V to 9V.
+  *
+  * @note   If an erase and a program operations are requested simultaneously,    
+  *         the erase operation is performed before the program one.
+  *  
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  
+  /* If the previous operation is completed, proceed to program the new data */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
+  FLASH->CR |= FLASH_CR_PG;
+
+  /* Program first word */
+  *(__IO uint32_t*)Address = (uint32_t)Data;
+
+  /* Barrier to ensure programming is performed in 2 steps, in right order
+    (independently of compiler optimization behavior) */
+  __ISB();
+
+  /* Program second word */
+  *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
+}
+
+
+/**
+  * @brief  Program word (32-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         2.7V to 3.6V.
+  *
+  * @note   If an erase and a program operations are requested simultaneously,    
+  *         the erase operation is performed before the program one.
+  *  
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  
+  /* If the previous operation is completed, proceed to program the new data */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= FLASH_PSIZE_WORD;
+  FLASH->CR |= FLASH_CR_PG;
+
+  *(__IO uint32_t*)Address = Data;
+}
+
+/**
+  * @brief  Program a half-word (16-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         2.1V to 3.6V.
+  *
+  * @note   If an erase and a program operations are requested simultaneously,    
+  *         the erase operation is performed before the program one.
+  *  
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  
+  /* If the previous operation is completed, proceed to program the new data */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= FLASH_PSIZE_HALF_WORD;
+  FLASH->CR |= FLASH_CR_PG;
+
+  *(__IO uint16_t*)Address = Data;
+}
+
+/**
+  * @brief  Program byte (8-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         1.8V to 3.6V.
+  *
+  * @note   If an erase and a program operations are requested simultaneously,    
+  *         the erase operation is performed before the program one.
+  *  
+  * @param  Address specifies the address to be programmed.
+  * @param  Data specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+  
+  /* If the previous operation is completed, proceed to program the new data */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= FLASH_PSIZE_BYTE;
+  FLASH->CR |= FLASH_CR_PG;
+
+  *(__IO uint8_t*)Address = Data;
+}
+
+/**
+  * @brief  Set the specific FLASH error flag.
+  * @retval None
+  */
+static void FLASH_SetErrorCode(void)
+{ 
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
+  {
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
+   
+   /* Clear FLASH write protection error pending bit */
+   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR);
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
+  {
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
+   
+   /* Clear FLASH Programming alignment error pending bit */
+   __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR);
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
+    
+    /* Clear FLASH Programming parallelism error pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR);
+  }
+  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET)
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;
+    
+    /* Clear FLASH Programming sequence error pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR);
+  }
+#if defined(FLASH_SR_RDERR) 
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
+    
+    /* Clear FLASH Proprietary readout protection error pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR);
+  }
+#endif /* FLASH_SR_RDERR */  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
+    
+    /* Clear FLASH Operation error pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c
index d99eace..abff6d7 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.c
@@ -1,1347 +1,1347 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_flash_ex.c
-  * @author  MCD Application Team
-  * @brief   Extended FLASH HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the FLASH extension peripheral:
-  *           + Extended programming operations functions
-  *
-  @verbatim
-  ==============================================================================
-                   ##### Flash Extension features #####
-  ==============================================================================
-
-  [..] Comparing to other previous devices, the FLASH interface for STM32F427xx/437xx and
-       STM32F429xx/439xx devices contains the following additional features
-
-       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
-           capability (RWW)
-       (+) Dual bank memory organization
-       (+) PCROP protection for all banks
-
-                      ##### How to use this driver #####
-  ==============================================================================
-  [..] This driver provides functions to configure and program the FLASH memory
-       of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx
-       devices. It includes
-      (#) FLASH Memory Erase functions:
-           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
-                HAL_FLASH_Lock() functions
-           (++) Erase function: Erase sector, erase all sectors
-           (++) There are two modes of erase :
-             (+++) Polling Mode using HAL_FLASHEx_Erase()
-             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
-
-      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
-           (++) Set/Reset the write protection
-           (++) Set the Read protection Level
-           (++) Set the BOR level
-           (++) Program the user Option Bytes
-      (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :
-       (++) Extended space (bank 2) erase function
-       (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)
-       (++) Dual Boot activation
-       (++) Write protection configuration for bank 2
-       (++) PCROP protection configuration and control for both banks
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup FLASHEx FLASHEx
-  * @brief FLASH HAL Extension module driver
-  * @{
-  */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup FLASHEx_Private_Constants
-  * @{
-  */
-#define FLASH_TIMEOUT_VALUE       50000U /* 50 s */
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @addtogroup FLASHEx_Private_Variables
-  * @{
-  */
-extern FLASH_ProcessTypeDef pFlash;
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup FLASHEx_Private_Functions
-  * @{
-  */
-/* Option bytes control */
-static void               FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
-static HAL_StatusTypeDef  FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
-static HAL_StatusTypeDef  FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks);
-static HAL_StatusTypeDef  FLASH_OB_RDP_LevelConfig(uint8_t Level);
-static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby);
-static HAL_StatusTypeDef  FLASH_OB_BOR_LevelConfig(uint8_t Level);
-static uint8_t            FLASH_OB_GetUser(void);
-static uint16_t           FLASH_OB_GetWRP(void);
-static uint8_t            FLASH_OB_GetRDP(void);
-static uint8_t            FLASH_OB_GetBOR(void);
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
-    defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
-    defined(STM32F423xx)
-static HAL_StatusTypeDef  FLASH_OB_EnablePCROP(uint32_t Sector);
-static HAL_StatusTypeDef  FLASH_OB_DisablePCROP(uint32_t Sector);
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
-          STM32F413xx || STM32F423xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
-static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
-static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig);
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-extern HAL_StatusTypeDef         FLASH_WaitForLastOperation(uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
-  * @{
-  */
-
-/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
- *  @brief   Extended IO operation functions
- *
-@verbatim
- ===============================================================================
-                ##### Extended programming operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the Extension FLASH
-    programming operations.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Perform a mass erase or erase the specified FLASH memory sectors
-  * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
-  *         contains the configuration information for the erasing.
-  *
-  * @param[out]  SectorError pointer to variable  that
-  *         contains the configuration information on faulty sector in case of error
-  *         (0xFFFFFFFFU means that all the sectors have been correctly erased)
-  *
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  uint32_t index = 0U;
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    /*Initialization of SectorError variable*/
-    *SectorError = 0xFFFFFFFFU;
-
-    if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
-    {
-      /*Mass erase to be done*/
-      FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-      /* if the erase operation is completed, disable the MER Bit */
-      FLASH->CR &= (~FLASH_MER_BIT);
-    }
-    else
-    {
-      /* Check the parameters */
-      assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
-
-      /* Erase by sector by sector to be done*/
-      for (index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
-      {
-        FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
-
-        /* Wait for last operation to be completed */
-        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-        /* If the erase operation is completed, disable the SER and SNB Bits */
-        CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
-
-        if (status != HAL_OK)
-        {
-          /* In case of error, stop erase procedure and return the faulty sector*/
-          *SectorError = index;
-          break;
-        }
-      }
-    }
-    /* Flush the caches to be sure of the data consistency */
-    FLASH_FlushCaches();
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief  Perform a mass erase or erase the specified FLASH memory sectors  with interrupt enabled
-  * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
-  *         contains the configuration information for the erasing.
-  *
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
-
-  /* Enable End of FLASH Operation interrupt */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
-
-  /* Enable Error source interrupt */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
-
-  /* Clear pending flags (if any) */
-  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | \
-                         FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR);
-
-  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
-  {
-    /*Mass erase to be done*/
-    pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
-    pFlash.Bank = pEraseInit->Banks;
-    FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
-  }
-  else
-  {
-    /* Erase by sector to be done*/
-
-    /* Check the parameters */
-    assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
-
-    pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
-    pFlash.NbSectorsToErase = pEraseInit->NbSectors;
-    pFlash.Sector = pEraseInit->Sector;
-    pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
-
-    /*Erase 1st sector and wait for IT*/
-    FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
-  }
-
-  return status;
-}
-
-/**
-  * @brief   Program option bytes
-  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
-  *         contains the configuration information for the programming.
-  *
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-
-  /* Process Locked */
-  __HAL_LOCK(&pFlash);
-
-  /* Check the parameters */
-  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
-
-  /*Write protection configuration*/
-  if ((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
-  {
-    assert_param(IS_WRPSTATE(pOBInit->WRPState));
-    if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
-    {
-      /*Enable of Write protection on the selected Sector*/
-      status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks);
-    }
-    else
-    {
-      /*Disable of Write protection on the selected Sector*/
-      status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
-    }
-  }
-
-  /*Read protection configuration*/
-  if ((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
-  {
-    status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
-  }
-
-  /*USER  configuration*/
-  if ((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
-  {
-    status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW,
-                                 pOBInit->USERConfig & OB_STOP_NO_RST,
-                                 pOBInit->USERConfig & OB_STDBY_NO_RST);
-  }
-
-  /*BOR Level  configuration*/
-  if ((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
-  {
-    status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&pFlash);
-
-  return status;
-}
-
-/**
-  * @brief   Get the Option byte configuration
-  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
-  *         contains the configuration information for the programming.
-  *
-  * @retval None
-  */
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
-{
-  pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;
-
-  /*Get WRP*/
-  pOBInit->WRPSector = (uint32_t)FLASH_OB_GetWRP();
-
-  /*Get RDP Level*/
-  pOBInit->RDPLevel = (uint32_t)FLASH_OB_GetRDP();
-
-  /*Get USER*/
-  pOBInit->USERConfig = (uint8_t)FLASH_OB_GetUser();
-
-  /*Get BOR Level*/
-  pOBInit->BORLevel = (uint32_t)FLASH_OB_GetBOR();
-}
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
-    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-/**
-  * @brief   Program option bytes
-  * @param  pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that
-  *         contains the configuration information for the programming.
-  *
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-
-  /* Check the parameters */
-  assert_param(IS_OBEX(pAdvOBInit->OptionType));
-
-  /*Program PCROP option byte*/
-  if (((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)
-  {
-    /* Check the parameters */
-    assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState));
-    if ((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE)
-    {
-      /*Enable of Write protection on the selected Sector*/
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
-    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-      status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors);
-#else  /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-      status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
-          STM32F413xx || STM32F423xx */
-    }
-    else
-    {
-      /*Disable of Write protection on the selected Sector*/
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
-    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-      status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors);
-#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-      status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
-          STM32F413xx || STM32F423xx */
-    }
-  }
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-  /*Program BOOT config option byte*/
-  if (((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG)
-  {
-    status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);
-  }
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-  return status;
-}
-
-/**
-  * @brief   Get the OBEX byte configuration
-  * @param  pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that
-  *         contains the configuration information for the programming.
-  *
-  * @retval None
-  */
-void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
-{
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
-    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-  /*Get Sector*/
-  pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
-#else  /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
-  /*Get Sector for Bank1*/
-  pAdvOBInit->SectorsBank1 = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
-
-  /*Get Sector for Bank2*/
-  pAdvOBInit->SectorsBank2 = (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
-
-  /*Get Boot config OB*/
-  pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS;
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
-          STM32F413xx || STM32F423xx */
-}
-
-/**
-  * @brief  Select the Protection Mode
-  *
-  * @note   After PCROP activated Option Byte modification NOT POSSIBLE! excepted
-  *         Global Read Out Protection modification (from level1 to level0)
-  * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible
-  * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
-  * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
-  *         STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices.
-  *
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
-{
-  uint8_t optiontmp = 0xFF;
-
-  /* Mask SPRMOD bit */
-  optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
-
-  /* Update Option Byte */
-  *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deselect the Protection Mode
-  *
-  * @note   After PCROP activated Option Byte modification NOT POSSIBLE! excepted
-  *         Global Read Out Protection modification (from level1 to level0)
-  * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible
-  * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
-  * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
-  *         STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices.
-  *
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
-{
-  uint8_t optiontmp = 0xFF;
-
-  /* Mask SPRMOD bit */
-  optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
-
-  /* Update Option Byte */
-  *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp);
-
-  return HAL_OK;
-}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx ||\
-          STM32F411xE || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
-          STM32F413xx || STM32F423xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/**
-  * @brief  Returns the FLASH Write Protection Option Bytes value for Bank 2
-  * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx devices.
-  * @retval The FLASH Write Protection  Option Bytes value
-  */
-uint16_t HAL_FLASHEx_OB_GetBank2WRP(void)
-{
-  /* Return the FLASH write protection Register value */
-  return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
-}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-/**
-  * @}
-  */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/**
-  * @brief  Full erase of FLASH memory sectors
-  * @param  VoltageRange The device voltage range which defines the erase parallelism.
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
-  *                                  the operation will be done by byte (8-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
-  *                                  the operation will be done by half word (16-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
-  *                                  the operation will be done by word (32-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
-  *                                  the operation will be done by double word (64-bit)
-  *
-  * @param  Banks Banks to be erased
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: Bank1 to be erased
-  *            @arg FLASH_BANK_2: Bank2 to be erased
-  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
-  *
-  * @retval HAL Status
-  */
-static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
-{
-  /* Check the parameters */
-  assert_param(IS_VOLTAGERANGE(VoltageRange));
-  assert_param(IS_FLASH_BANK(Banks));
-
-  /* if the previous operation is completed, proceed to erase all sectors */
-  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-
-  if (Banks == FLASH_BANK_BOTH)
-  {
-    /* bank1 & bank2 will be erased*/
-    FLASH->CR |= FLASH_MER_BIT;
-  }
-  else if (Banks == FLASH_BANK_1)
-  {
-    /*Only bank1 will be erased*/
-    FLASH->CR |= FLASH_CR_MER1;
-  }
-  else
-  {
-    /*Only bank2 will be erased*/
-    FLASH->CR |= FLASH_CR_MER2;
-  }
-  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U);
-}
-
-/**
-  * @brief  Erase the specified FLASH memory sector
-  * @param  Sector FLASH sector to erase
-  *         The value of this parameter depend on device used within the same series
-  * @param  VoltageRange The device voltage range which defines the erase parallelism.
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
-  *                                  the operation will be done by byte (8-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
-  *                                  the operation will be done by half word (16-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
-  *                                  the operation will be done by word (32-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
-  *                                  the operation will be done by double word (64-bit)
-  *
-  * @retval None
-  */
-void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
-{
-  uint32_t tmp_psize = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_SECTOR(Sector));
-  assert_param(IS_VOLTAGERANGE(VoltageRange));
-
-  if (VoltageRange == FLASH_VOLTAGE_RANGE_1)
-  {
-    tmp_psize = FLASH_PSIZE_BYTE;
-  }
-  else if (VoltageRange == FLASH_VOLTAGE_RANGE_2)
-  {
-    tmp_psize = FLASH_PSIZE_HALF_WORD;
-  }
-  else if (VoltageRange == FLASH_VOLTAGE_RANGE_3)
-  {
-    tmp_psize = FLASH_PSIZE_WORD;
-  }
-  else
-  {
-    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
-  }
-
-  /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
-  if (Sector > FLASH_SECTOR_11)
-  {
-    Sector += 4U;
-  }
-  /* If the previous operation is completed, proceed to erase the sector */
-  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-  FLASH->CR |= tmp_psize;
-  CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
-  FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
-  FLASH->CR |= FLASH_CR_STRT;
-}
-
-/**
-  * @brief  Enable the write protection of the desired bank1 or bank 2 sectors
-  *
-  * @note   When the memory read protection level is selected (RDP level = 1),
-  *         it is not possible to program or erase the flash sector i if CortexM4
-  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
-  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
-  *
-  * @param  WRPSector specifies the sector(s) to be write protected.
-  *          This parameter can be one of the following values:
-  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
-  *            @arg OB_WRP_SECTOR_All
-  * @note   BANK2 starts from OB_WRP_SECTOR_12
-  *
-  * @param  Banks Enable write protection on all the sectors for the specific bank
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
-  *            @arg FLASH_BANK_2: WRP on all sectors of bank2
-  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
-  *
-  * @retval HAL FLASH State
-  */
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_WRP_SECTOR(WRPSector));
-  assert_param(IS_FLASH_BANK(Banks));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
-        (WRPSector < OB_WRP_SECTOR_12))
-    {
-      if (WRPSector == OB_WRP_SECTOR_All)
-      {
-        /*Write protection on all sector of BANK1*/
-        *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~(WRPSector >> 12));
-      }
-      else
-      {
-        /*Write protection done on sectors of BANK1*/
-        *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~WRPSector);
-      }
-    }
-    else
-    {
-      /*Write protection done on sectors of BANK2*/
-      *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector >> 12));
-    }
-
-    /*Write protection on all sector of BANK2*/
-    if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
-    {
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-      if (status == HAL_OK)
-      {
-        *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector >> 12));
-      }
-    }
-
-  }
-  return status;
-}
-
-/**
-  * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
-  *
-  * @note   When the memory read protection level is selected (RDP level = 1),
-  *         it is not possible to program or erase the flash sector i if CortexM4
-  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
-  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
-  *
-  * @param  WRPSector specifies the sector(s) to be write protected.
-  *          This parameter can be one of the following values:
-  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
-  *            @arg OB_WRP_Sector_All
-  * @note   BANK2 starts from OB_WRP_SECTOR_12
-  *
-  * @param  Banks Disable write protection on all the sectors for the specific bank
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: Bank1 to be erased
-  *            @arg FLASH_BANK_2: Bank2 to be erased
-  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
-  *
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_WRP_SECTOR(WRPSector));
-  assert_param(IS_FLASH_BANK(Banks));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
-        (WRPSector < OB_WRP_SECTOR_12))
-    {
-      if (WRPSector == OB_WRP_SECTOR_All)
-      {
-        /*Write protection on all sector of BANK1*/
-        *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12);
-      }
-      else
-      {
-        /*Write protection done on sectors of BANK1*/
-        *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector;
-      }
-    }
-    else
-    {
-      /*Write protection done on sectors of BANK2*/
-      *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12);
-    }
-
-    /*Write protection on all sector  of BANK2*/
-    if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
-    {
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-      if (status == HAL_OK)
-      {
-        *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12);
-      }
-    }
-
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Configure the Dual Bank Boot.
-  *
-  * @note   This function can be used only for STM32F42xxx/43xxx devices.
-  *
-  * @param  BootConfig specifies the Dual Bank Boot Option byte.
-  *          This parameter can be one of the following values:
-  *            @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
-  *            @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
-  * @retval None
-  */
-static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_BOOT(BootConfig));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    /* Set Dual Bank Boot */
-    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
-    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= BootConfig;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Enable the read/write protection (PCROP) of the desired
-  *         sectors of Bank 1 and/or Bank 2.
-  * @note   This function can be used only for STM32F42xxx/43xxx devices.
-  * @param  SectorBank1 Specifies the sector(s) to be read/write protected or unprotected for bank1.
-  *          This parameter can be one of the following values:
-  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11
-  *            @arg OB_PCROP_SECTOR__All
-  * @param  SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.
-  *          This parameter can be one of the following values:
-  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23
-  *            @arg OB_PCROP_SECTOR__All
-  * @param  Banks Enable PCROP protection on all the sectors for the specific bank
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
-  *            @arg FLASH_BANK_2: WRP on all sectors of bank2
-  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
-  *
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  assert_param(IS_FLASH_BANK(Banks));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
-    {
-      assert_param(IS_OB_PCROP(SectorBank1));
-      /*Write protection done on sectors of BANK1*/
-      *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1;
-    }
-    else
-    {
-      assert_param(IS_OB_PCROP(SectorBank2));
-      /*Write protection done on sectors of BANK2*/
-      *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2;
-    }
-
-    /*Write protection on all sector  of BANK2*/
-    if (Banks == FLASH_BANK_BOTH)
-    {
-      assert_param(IS_OB_PCROP(SectorBank2));
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-      if (status == HAL_OK)
-      {
-        /*Write protection done on sectors of BANK2*/
-        *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2;
-      }
-    }
-
-  }
-
-  return status;
-}
-
-
-/**
-  * @brief  Disable the read/write protection (PCROP) of the desired
-  *         sectors  of Bank 1 and/or Bank 2.
-  * @note   This function can be used only for STM32F42xxx/43xxx devices.
-  * @param  SectorBank1 specifies the sector(s) to be read/write protected or unprotected for bank1.
-  *          This parameter can be one of the following values:
-  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11
-  *            @arg OB_PCROP_SECTOR__All
-  * @param  SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.
-  *          This parameter can be one of the following values:
-  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23
-  *            @arg OB_PCROP_SECTOR__All
-  * @param  Banks Disable PCROP protection on all the sectors for the specific bank
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
-  *            @arg FLASH_BANK_2: WRP on all sectors of bank2
-  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
-  *
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_BANK(Banks));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
-    {
-      assert_param(IS_OB_PCROP(SectorBank1));
-      /*Write protection done on sectors of BANK1*/
-      *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~SectorBank1);
-    }
-    else
-    {
-      /*Write protection done on sectors of BANK2*/
-      assert_param(IS_OB_PCROP(SectorBank2));
-      *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2);
-    }
-
-    /*Write protection on all sector  of BANK2*/
-    if (Banks == FLASH_BANK_BOTH)
-    {
-      assert_param(IS_OB_PCROP(SectorBank2));
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-      if (status == HAL_OK)
-      {
-        /*Write protection done on sectors of BANK2*/
-        *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2);
-      }
-    }
-
-  }
-
-  return status;
-
-}
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
-    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
-    defined(STM32F423xx)
-/**
-  * @brief  Mass erase of FLASH memory
-  * @param  VoltageRange The device voltage range which defines the erase parallelism.
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
-  *                                  the operation will be done by byte (8-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
-  *                                  the operation will be done by half word (16-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
-  *                                  the operation will be done by word (32-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
-  *                                  the operation will be done by double word (64-bit)
-  *
-  * @param  Banks Banks to be erased
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: Bank1 to be erased
-  *
-  * @retval None
-  */
-static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
-{
-  /* Check the parameters */
-  assert_param(IS_VOLTAGERANGE(VoltageRange));
-  assert_param(IS_FLASH_BANK(Banks));
-
-  /* If the previous operation is completed, proceed to erase all sectors */
-  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-  FLASH->CR |= FLASH_CR_MER;
-  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U);
-}
-
-/**
-  * @brief  Erase the specified FLASH memory sector
-  * @param  Sector FLASH sector to erase
-  *         The value of this parameter depend on device used within the same series
-  * @param  VoltageRange The device voltage range which defines the erase parallelism.
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
-  *                                  the operation will be done by byte (8-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
-  *                                  the operation will be done by half word (16-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
-  *                                  the operation will be done by word (32-bit)
-  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
-  *                                  the operation will be done by double word (64-bit)
-  *
-  * @retval None
-  */
-void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
-{
-  uint32_t tmp_psize = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_SECTOR(Sector));
-  assert_param(IS_VOLTAGERANGE(VoltageRange));
-
-  if (VoltageRange == FLASH_VOLTAGE_RANGE_1)
-  {
-    tmp_psize = FLASH_PSIZE_BYTE;
-  }
-  else if (VoltageRange == FLASH_VOLTAGE_RANGE_2)
-  {
-    tmp_psize = FLASH_PSIZE_HALF_WORD;
-  }
-  else if (VoltageRange == FLASH_VOLTAGE_RANGE_3)
-  {
-    tmp_psize = FLASH_PSIZE_WORD;
-  }
-  else
-  {
-    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
-  }
-
-  /* If the previous operation is completed, proceed to erase the sector */
-  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
-  FLASH->CR |= tmp_psize;
-  CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
-  FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
-  FLASH->CR |= FLASH_CR_STRT;
-}
-
-/**
-  * @brief  Enable the write protection of the desired bank 1 sectors
-  *
-  * @note   When the memory read protection level is selected (RDP level = 1),
-  *         it is not possible to program or erase the flash sector i if CortexM4
-  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
-  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
-  *
-  * @param  WRPSector specifies the sector(s) to be write protected.
-  *         The value of this parameter depend on device used within the same series
-  *
-  * @param  Banks Enable write protection on all the sectors for the specific bank
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
-  *
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_WRP_SECTOR(WRPSector));
-  assert_param(IS_FLASH_BANK(Banks));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~WRPSector);
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Disable the write protection of the desired bank 1 sectors
-  *
-  * @note   When the memory read protection level is selected (RDP level = 1),
-  *         it is not possible to program or erase the flash sector i if CortexM4
-  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
-  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
-  *
-  * @param  WRPSector specifies the sector(s) to be write protected.
-  *         The value of this parameter depend on device used within the same series
-  *
-  * @param  Banks Enable write protection on all the sectors for the specific bank
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
-  *
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_WRP_SECTOR(WRPSector));
-  assert_param(IS_FLASH_BANK(Banks));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector;
-  }
-
-  return status;
-}
-#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
-          STM32F413xx || STM32F423xx */
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
-    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
-    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-/**
-  * @brief  Enable the read/write protection (PCROP) of the desired sectors.
-  * @note   This function can be used only for STM32F401xx devices.
-  * @param  Sector specifies the sector(s) to be read/write protected or unprotected.
-  *          This parameter can be one of the following values:
-  *            @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
-  *            @arg OB_PCROP_Sector_All
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_PCROP(Sector));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector;
-  }
-
-  return status;
-}
-
-
-/**
-  * @brief  Disable the read/write protection (PCROP) of the desired sectors.
-  * @note   This function can be used only for STM32F401xx devices.
-  * @param  Sector specifies the sector(s) to be read/write protected or unprotected.
-  *          This parameter can be one of the following values:
-  *            @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
-  *            @arg OB_PCROP_Sector_All
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_PCROP(Sector));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~Sector);
-  }
-
-  return status;
-
-}
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
-          STM32F413xx || STM32F423xx */
-
-/**
-  * @brief  Set the read protection level.
-  * @param  Level specifies the read protection level.
-  *          This parameter can be one of the following values:
-  *            @arg OB_RDP_LEVEL_0: No protection
-  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
-  *            @arg OB_RDP_LEVEL_2: Full chip protection
-  *
-  * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
-  *
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_RDP_LEVEL(Level));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    *(__IO uint8_t *)OPTCR_BYTE1_ADDRESS = Level;
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
-  * @param  Iwdg Selects the IWDG mode
-  *          This parameter can be one of the following values:
-  *            @arg OB_IWDG_SW: Software IWDG selected
-  *            @arg OB_IWDG_HW: Hardware IWDG selected
-  * @param  Stop Reset event when entering STOP mode.
-  *          This parameter  can be one of the following values:
-  *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP
-  *            @arg OB_STOP_RST: Reset generated when entering in STOP
-  * @param  Stdby Reset event when entering Standby mode.
-  *          This parameter  can be one of the following values:
-  *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
-  *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
-{
-  uint8_t optiontmp = 0xFF;
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_OB_IWDG_SOURCE(Iwdg));
-  assert_param(IS_OB_STOP_SOURCE(Stop));
-  assert_param(IS_OB_STDBY_SOURCE(Stdby));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
-    optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
-
-    /* Update User Option Byte */
-    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp)));
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Set the BOR Level.
-  * @param  Level specifies the Option Bytes BOR Reset Level.
-  *          This parameter can be one of the following values:
-  *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
-  *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
-  *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
-  *            @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
-  * @retval HAL Status
-  */
-static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
-{
-  /* Check the parameters */
-  assert_param(IS_OB_BOR_LEVEL(Level));
-
-  /* Set the BOR Level */
-  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
-  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= Level;
-
-  return HAL_OK;
-
-}
-
-/**
-  * @brief  Return the FLASH User Option Byte value.
-  * @retval uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
-  *         and RST_STDBY(Bit2).
-  */
-static uint8_t FLASH_OB_GetUser(void)
-{
-  /* Return the User Option Byte */
-  return ((uint8_t)(FLASH->OPTCR & 0xE0));
-}
-
-/**
-  * @brief  Return the FLASH Write Protection Option Bytes value.
-  * @retval uint16_t FLASH Write Protection Option Bytes value
-  */
-static uint16_t FLASH_OB_GetWRP(void)
-{
-  /* Return the FLASH write protection Register value */
-  return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
-}
-
-/**
-  * @brief  Returns the FLASH Read Protection level.
-  * @retval FLASH ReadOut Protection Status:
-  *         This parameter can be one of the following values:
-  *            @arg OB_RDP_LEVEL_0: No protection
-  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
-  *            @arg OB_RDP_LEVEL_2: Full chip protection
-  */
-static uint8_t FLASH_OB_GetRDP(void)
-{
-  uint8_t readstatus = OB_RDP_LEVEL_0;
-
-  if (*(__IO uint8_t *)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2)
-  {
-    readstatus = OB_RDP_LEVEL_2;
-  }
-  else if (*(__IO uint8_t *)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0)
-  {
-    readstatus = OB_RDP_LEVEL_0;
-  }
-  else
-  {
-    readstatus = OB_RDP_LEVEL_1;
-  }
-
-  return readstatus;
-}
-
-/**
-  * @brief  Returns the FLASH BOR level.
-  * @retval uint8_t The FLASH BOR level:
-  *           - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
-  *           - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
-  *           - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
-  *           - OB_BOR_OFF   : Supply voltage ranges from 1.62 to 2.1 V
-  */
-static uint8_t FLASH_OB_GetBOR(void)
-{
-  /* Return the FLASH BOR level */
-  return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
-}
-
-/**
-  * @brief  Flush the instruction and data caches
-  * @retval None
-  */
-void FLASH_FlushCaches(void)
-{
-  /* Flush instruction cache  */
-  if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
-  {
-    /* Disable instruction cache  */
-    __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
-    /* Reset instruction cache */
-    __HAL_FLASH_INSTRUCTION_CACHE_RESET();
-    /* Enable instruction cache */
-    __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
-  }
-
-  /* Flush data cache */
-  if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
-  {
-    /* Disable data cache  */
-    __HAL_FLASH_DATA_CACHE_DISABLE();
-    /* Reset data cache */
-    __HAL_FLASH_DATA_CACHE_RESET();
-    /* Enable data cache */
-    __HAL_FLASH_DATA_CACHE_ENABLE();
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_flash_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the FLASH extension peripheral:
+  *           + Extended programming operations functions
+  *
+  @verbatim
+  ==============================================================================
+                   ##### Flash Extension features #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the FLASH interface for STM32F427xx/437xx and
+       STM32F429xx/439xx devices contains the following additional features
+
+       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
+           capability (RWW)
+       (+) Dual bank memory organization
+       (+) PCROP protection for all banks
+
+                      ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to configure and program the FLASH memory
+       of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx
+       devices. It includes
+      (#) FLASH Memory Erase functions:
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and
+                HAL_FLASH_Lock() functions
+           (++) Erase function: Erase sector, erase all sectors
+           (++) There are two modes of erase :
+             (+++) Polling Mode using HAL_FLASHEx_Erase()
+             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+
+      (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to :
+           (++) Set/Reset the write protection
+           (++) Set the Read protection Level
+           (++) Set the BOR level
+           (++) Program the user Option Bytes
+      (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :
+       (++) Extended space (bank 2) erase function
+       (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)
+       (++) Dual Boot activation
+       (++) Write protection configuration for bank 2
+       (++) PCROP protection configuration and control for both banks
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASHEx FLASHEx
+  * @brief FLASH HAL Extension module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Constants
+  * @{
+  */
+#define FLASH_TIMEOUT_VALUE       50000U /* 50 s */
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Variables
+  * @{
+  */
+extern FLASH_ProcessTypeDef pFlash;
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup FLASHEx_Private_Functions
+  * @{
+  */
+/* Option bytes control */
+static void               FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
+static HAL_StatusTypeDef  FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks);
+static HAL_StatusTypeDef  FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks);
+static HAL_StatusTypeDef  FLASH_OB_RDP_LevelConfig(uint8_t Level);
+static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby);
+static HAL_StatusTypeDef  FLASH_OB_BOR_LevelConfig(uint8_t Level);
+static uint8_t            FLASH_OB_GetUser(void);
+static uint16_t           FLASH_OB_GetWRP(void);
+static uint8_t            FLASH_OB_GetRDP(void);
+static uint8_t            FLASH_OB_GetBOR(void);
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) ||\
+    defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+static HAL_StatusTypeDef  FLASH_OB_EnablePCROP(uint32_t Sector);
+static HAL_StatusTypeDef  FLASH_OB_DisablePCROP(uint32_t Sector);
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
+          STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
+static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks);
+static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig);
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+extern HAL_StatusTypeDef         FLASH_WaitForLastOperation(uint32_t Timeout);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+ *  @brief   Extended IO operation functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the Extension FLASH
+    programming operations.
+
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory sectors
+  * @param[in]  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  *
+  * @param[out]  SectorError pointer to variable  that
+  *         contains the configuration information on faulty sector in case of error
+  *         (0xFFFFFFFFU means that all the sectors have been correctly erased)
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t index = 0U;
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    /*Initialization of SectorError variable*/
+    *SectorError = 0xFFFFFFFFU;
+
+    if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+    {
+      /*Mass erase to be done*/
+      FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+      /* if the erase operation is completed, disable the MER Bit */
+      FLASH->CR &= (~FLASH_MER_BIT);
+    }
+    else
+    {
+      /* Check the parameters */
+      assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
+
+      /* Erase by sector by sector to be done*/
+      for (index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
+      {
+        FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+        /* If the erase operation is completed, disable the SER and SNB Bits */
+        CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
+
+        if (status != HAL_OK)
+        {
+          /* In case of error, stop erase procedure and return the faulty sector*/
+          *SectorError = index;
+          break;
+        }
+      }
+    }
+    /* Flush the caches to be sure of the data consistency */
+    FLASH_FlushCaches();
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory sectors  with interrupt enabled
+  * @param  pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+  /* Enable End of FLASH Operation interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
+
+  /* Enable Error source interrupt */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
+
+  /* Clear pending flags (if any) */
+  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP    | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | \
+                         FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR);
+
+  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+  {
+    /*Mass erase to be done*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
+    pFlash.Bank = pEraseInit->Banks;
+    FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
+  }
+  else
+  {
+    /* Erase by sector to be done*/
+
+    /* Check the parameters */
+    assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
+
+    pFlash.ProcedureOnGoing = FLASH_PROC_SECTERASE;
+    pFlash.NbSectorsToErase = pEraseInit->NbSectors;
+    pFlash.Sector = pEraseInit->Sector;
+    pFlash.VoltageForErase = (uint8_t)pEraseInit->VoltageRange;
+
+    /*Erase 1st sector and wait for IT*/
+    FLASH_Erase_Sector(pEraseInit->Sector, pEraseInit->VoltageRange);
+  }
+
+  return status;
+}
+
+/**
+  * @brief   Program option bytes
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+
+  /*Write protection configuration*/
+  if ((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
+  {
+    assert_param(IS_WRPSTATE(pOBInit->WRPState));
+    if (pOBInit->WRPState == OB_WRPSTATE_ENABLE)
+    {
+      /*Enable of Write protection on the selected Sector*/
+      status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks);
+    }
+    else
+    {
+      /*Disable of Write protection on the selected Sector*/
+      status = FLASH_OB_DisableWRP(pOBInit->WRPSector, pOBInit->Banks);
+    }
+  }
+
+  /*Read protection configuration*/
+  if ((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
+  {
+    status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel);
+  }
+
+  /*USER  configuration*/
+  if ((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
+  {
+    status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW,
+                                 pOBInit->USERConfig & OB_STOP_NO_RST,
+                                 pOBInit->USERConfig & OB_STDBY_NO_RST);
+  }
+
+  /*BOR Level  configuration*/
+  if ((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
+  {
+    status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief   Get the Option byte configuration
+  * @param  pOBInit pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  *
+  * @retval None
+  */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;
+
+  /*Get WRP*/
+  pOBInit->WRPSector = (uint32_t)FLASH_OB_GetWRP();
+
+  /*Get RDP Level*/
+  pOBInit->RDPLevel = (uint32_t)FLASH_OB_GetRDP();
+
+  /*Get USER*/
+  pOBInit->USERConfig = (uint8_t)FLASH_OB_GetUser();
+
+  /*Get BOR Level*/
+  pOBInit->BORLevel = (uint32_t)FLASH_OB_GetBOR();
+}
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) ||\
+    defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+  * @brief   Program option bytes
+  * @param  pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that
+  *         contains the configuration information for the programming.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_OBEX(pAdvOBInit->OptionType));
+
+  /*Program PCROP option byte*/
+  if (((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP)
+  {
+    /* Check the parameters */
+    assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState));
+    if ((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE)
+    {
+      /*Enable of Write protection on the selected Sector*/
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+      status = FLASH_OB_EnablePCROP(pAdvOBInit->Sectors);
+#else  /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+      status = FLASH_OB_EnablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+          STM32F413xx || STM32F423xx */
+    }
+    else
+    {
+      /*Disable of Write protection on the selected Sector*/
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+      status = FLASH_OB_DisablePCROP(pAdvOBInit->Sectors);
+#else /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+      status = FLASH_OB_DisablePCROP(pAdvOBInit->SectorsBank1, pAdvOBInit->SectorsBank2, pAdvOBInit->Banks);
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+          STM32F413xx || STM32F423xx */
+    }
+  }
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+  /*Program BOOT config option byte*/
+  if (((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG)
+  {
+    status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);
+  }
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+  return status;
+}
+
+/**
+  * @brief   Get the OBEX byte configuration
+  * @param  pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that
+  *         contains the configuration information for the programming.
+  *
+  * @retval None
+  */
+void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
+{
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+  /*Get Sector*/
+  pAdvOBInit->Sectors = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
+#else  /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx || STM32F469xx || STM32F479xx */
+  /*Get Sector for Bank1*/
+  pAdvOBInit->SectorsBank1 = (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
+
+  /*Get Sector for Bank2*/
+  pAdvOBInit->SectorsBank2 = (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
+
+  /*Get Boot config OB*/
+  pAdvOBInit->BootConfig = *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS;
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+          STM32F413xx || STM32F423xx */
+}
+
+/**
+  * @brief  Select the Protection Mode
+  *
+  * @note   After PCROP activated Option Byte modification NOT POSSIBLE! excepted
+  *         Global Read Out Protection modification (from level1 to level0)
+  * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible
+  * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
+  * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
+  *         STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
+{
+  uint8_t optiontmp = 0xFF;
+
+  /* Mask SPRMOD bit */
+  optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
+
+  /* Update Option Byte */
+  *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deselect the Protection Mode
+  *
+  * @note   After PCROP activated Option Byte modification NOT POSSIBLE! excepted
+  *         Global Read Out Protection modification (from level1 to level0)
+  * @note   Once SPRMOD bit is active unprotection of a protected sector is not possible
+  * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
+  * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/
+  *         STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices.
+  *
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
+{
+  uint8_t optiontmp = 0xFF;
+
+  /* Mask SPRMOD bit */
+  optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F);
+
+  /* Update Option Byte */
+  *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp);
+
+  return HAL_OK;
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx ||\
+          STM32F411xE || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx ||
+          STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+  * @brief  Returns the FLASH Write Protection Option Bytes value for Bank 2
+  * @note   This function can be used only for STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx devices.
+  * @retval The FLASH Write Protection  Option Bytes value
+  */
+uint16_t HAL_FLASHEx_OB_GetBank2WRP(void)
+{
+  /* Return the FLASH write protection Register value */
+  return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS));
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+/**
+  * @}
+  */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+  * @brief  Full erase of FLASH memory sectors
+  * @param  VoltageRange The device voltage range which defines the erase parallelism.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+  *                                  the operation will be done by byte (8-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+  *                                  the operation will be done by double word (64-bit)
+  *
+  * @param  Banks Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  *
+  * @retval HAL Status
+  */
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* if the previous operation is completed, proceed to erase all sectors */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+
+  if (Banks == FLASH_BANK_BOTH)
+  {
+    /* bank1 & bank2 will be erased*/
+    FLASH->CR |= FLASH_MER_BIT;
+  }
+  else if (Banks == FLASH_BANK_1)
+  {
+    /*Only bank1 will be erased*/
+    FLASH->CR |= FLASH_CR_MER1;
+  }
+  else
+  {
+    /*Only bank2 will be erased*/
+    FLASH->CR |= FLASH_CR_MER2;
+  }
+  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U);
+}
+
+/**
+  * @brief  Erase the specified FLASH memory sector
+  * @param  Sector FLASH sector to erase
+  *         The value of this parameter depend on device used within the same series
+  * @param  VoltageRange The device voltage range which defines the erase parallelism.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+  *                                  the operation will be done by byte (8-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+  *                                  the operation will be done by double word (64-bit)
+  *
+  * @retval None
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
+{
+  uint32_t tmp_psize = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_SECTOR(Sector));
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+
+  if (VoltageRange == FLASH_VOLTAGE_RANGE_1)
+  {
+    tmp_psize = FLASH_PSIZE_BYTE;
+  }
+  else if (VoltageRange == FLASH_VOLTAGE_RANGE_2)
+  {
+    tmp_psize = FLASH_PSIZE_HALF_WORD;
+  }
+  else if (VoltageRange == FLASH_VOLTAGE_RANGE_3)
+  {
+    tmp_psize = FLASH_PSIZE_WORD;
+  }
+  else
+  {
+    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+  }
+
+  /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
+  if (Sector > FLASH_SECTOR_11)
+  {
+    Sector += 4U;
+  }
+  /* If the previous operation is completed, proceed to erase the sector */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= tmp_psize;
+  CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
+  FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
+  FLASH->CR |= FLASH_CR_STRT;
+}
+
+/**
+  * @brief  Enable the write protection of the desired bank1 or bank 2 sectors
+  *
+  * @note   When the memory read protection level is selected (RDP level = 1),
+  *         it is not possible to program or erase the flash sector i if CortexM4
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
+  *
+  * @param  WRPSector specifies the sector(s) to be write protected.
+  *          This parameter can be one of the following values:
+  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
+  *            @arg OB_WRP_SECTOR_All
+  * @note   BANK2 starts from OB_WRP_SECTOR_12
+  *
+  * @param  Banks Enable write protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
+  *            @arg FLASH_BANK_2: WRP on all sectors of bank2
+  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
+  *
+  * @retval HAL FLASH State
+  */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
+        (WRPSector < OB_WRP_SECTOR_12))
+    {
+      if (WRPSector == OB_WRP_SECTOR_All)
+      {
+        /*Write protection on all sector of BANK1*/
+        *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~(WRPSector >> 12));
+      }
+      else
+      {
+        /*Write protection done on sectors of BANK1*/
+        *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~WRPSector);
+      }
+    }
+    else
+    {
+      /*Write protection done on sectors of BANK2*/
+      *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector >> 12));
+    }
+
+    /*Write protection on all sector of BANK2*/
+    if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
+    {
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+      if (status == HAL_OK)
+      {
+        *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector >> 12));
+      }
+    }
+
+  }
+  return status;
+}
+
+/**
+  * @brief  Disable the write protection of the desired bank1 or bank 2 sectors
+  *
+  * @note   When the memory read protection level is selected (RDP level = 1),
+  *         it is not possible to program or erase the flash sector i if CortexM4
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
+  *
+  * @param  WRPSector specifies the sector(s) to be write protected.
+  *          This parameter can be one of the following values:
+  *            @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
+  *            @arg OB_WRP_Sector_All
+  * @note   BANK2 starts from OB_WRP_SECTOR_12
+  *
+  * @param  Banks Disable write protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  *
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) ||
+        (WRPSector < OB_WRP_SECTOR_12))
+    {
+      if (WRPSector == OB_WRP_SECTOR_All)
+      {
+        /*Write protection on all sector of BANK1*/
+        *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12);
+      }
+      else
+      {
+        /*Write protection done on sectors of BANK1*/
+        *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector;
+      }
+    }
+    else
+    {
+      /*Write protection done on sectors of BANK2*/
+      *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12);
+    }
+
+    /*Write protection on all sector  of BANK2*/
+    if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH))
+    {
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+      if (status == HAL_OK)
+      {
+        *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12);
+      }
+    }
+
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Configure the Dual Bank Boot.
+  *
+  * @note   This function can be used only for STM32F42xxx/43xxx devices.
+  *
+  * @param  BootConfig specifies the Dual Bank Boot Option byte.
+  *          This parameter can be one of the following values:
+  *            @arg OB_Dual_BootEnabled: Dual Bank Boot Enable
+  *            @arg OB_Dual_BootDisabled: Dual Bank Boot Disabled
+  * @retval None
+  */
+static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_BOOT(BootConfig));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    /* Set Dual Bank Boot */
+    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2);
+    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= BootConfig;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Enable the read/write protection (PCROP) of the desired
+  *         sectors of Bank 1 and/or Bank 2.
+  * @note   This function can be used only for STM32F42xxx/43xxx devices.
+  * @param  SectorBank1 Specifies the sector(s) to be read/write protected or unprotected for bank1.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11
+  *            @arg OB_PCROP_SECTOR__All
+  * @param  SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23
+  *            @arg OB_PCROP_SECTOR__All
+  * @param  Banks Enable PCROP protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
+  *            @arg FLASH_BANK_2: WRP on all sectors of bank2
+  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
+  *
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
+    {
+      assert_param(IS_OB_PCROP(SectorBank1));
+      /*Write protection done on sectors of BANK1*/
+      *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1;
+    }
+    else
+    {
+      assert_param(IS_OB_PCROP(SectorBank2));
+      /*Write protection done on sectors of BANK2*/
+      *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2;
+    }
+
+    /*Write protection on all sector  of BANK2*/
+    if (Banks == FLASH_BANK_BOTH)
+    {
+      assert_param(IS_OB_PCROP(SectorBank2));
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+      if (status == HAL_OK)
+      {
+        /*Write protection done on sectors of BANK2*/
+        *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2;
+      }
+    }
+
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  Disable the read/write protection (PCROP) of the desired
+  *         sectors  of Bank 1 and/or Bank 2.
+  * @note   This function can be used only for STM32F42xxx/43xxx devices.
+  * @param  SectorBank1 specifies the sector(s) to be read/write protected or unprotected for bank1.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11
+  *            @arg OB_PCROP_SECTOR__All
+  * @param  SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23
+  *            @arg OB_PCROP_SECTOR__All
+  * @param  Banks Disable PCROP protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
+  *            @arg FLASH_BANK_2: WRP on all sectors of bank2
+  *            @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2
+  *
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))
+    {
+      assert_param(IS_OB_PCROP(SectorBank1));
+      /*Write protection done on sectors of BANK1*/
+      *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~SectorBank1);
+    }
+    else
+    {
+      /*Write protection done on sectors of BANK2*/
+      assert_param(IS_OB_PCROP(SectorBank2));
+      *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2);
+    }
+
+    /*Write protection on all sector  of BANK2*/
+    if (Banks == FLASH_BANK_BOTH)
+    {
+      assert_param(IS_OB_PCROP(SectorBank2));
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+      if (status == HAL_OK)
+      {
+        /*Write protection done on sectors of BANK2*/
+        *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2);
+      }
+    }
+
+  }
+
+  return status;
+
+}
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) ||\
+    defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+    defined(STM32F423xx)
+/**
+  * @brief  Mass erase of FLASH memory
+  * @param  VoltageRange The device voltage range which defines the erase parallelism.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+  *                                  the operation will be done by byte (8-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+  *                                  the operation will be done by double word (64-bit)
+  *
+  * @param  Banks Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *
+  * @retval None
+  */
+static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* If the previous operation is completed, proceed to erase all sectors */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= FLASH_CR_MER;
+  FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U);
+}
+
+/**
+  * @brief  Erase the specified FLASH memory sector
+  * @param  Sector FLASH sector to erase
+  *         The value of this parameter depend on device used within the same series
+  * @param  VoltageRange The device voltage range which defines the erase parallelism.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
+  *                                  the operation will be done by byte (8-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
+  *                                  the operation will be done by double word (64-bit)
+  *
+  * @retval None
+  */
+void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
+{
+  uint32_t tmp_psize = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_SECTOR(Sector));
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+
+  if (VoltageRange == FLASH_VOLTAGE_RANGE_1)
+  {
+    tmp_psize = FLASH_PSIZE_BYTE;
+  }
+  else if (VoltageRange == FLASH_VOLTAGE_RANGE_2)
+  {
+    tmp_psize = FLASH_PSIZE_HALF_WORD;
+  }
+  else if (VoltageRange == FLASH_VOLTAGE_RANGE_3)
+  {
+    tmp_psize = FLASH_PSIZE_WORD;
+  }
+  else
+  {
+    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+  }
+
+  /* If the previous operation is completed, proceed to erase the sector */
+  CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
+  FLASH->CR |= tmp_psize;
+  CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
+  FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
+  FLASH->CR |= FLASH_CR_STRT;
+}
+
+/**
+  * @brief  Enable the write protection of the desired bank 1 sectors
+  *
+  * @note   When the memory read protection level is selected (RDP level = 1),
+  *         it is not possible to program or erase the flash sector i if CortexM4
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
+  *
+  * @param  WRPSector specifies the sector(s) to be write protected.
+  *         The value of this parameter depend on device used within the same series
+  *
+  * @param  Banks Enable write protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
+  *
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~WRPSector);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Disable the write protection of the desired bank 1 sectors
+  *
+  * @note   When the memory read protection level is selected (RDP level = 1),
+  *         it is not possible to program or erase the flash sector i if CortexM4
+  *         debug features are connected or boot code is executed in RAM, even if nWRPi = 1
+  * @note   Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
+  *
+  * @param  WRPSector specifies the sector(s) to be write protected.
+  *         The value of this parameter depend on device used within the same series
+  *
+  * @param  Banks Enable write protection on all the sectors for the specific bank
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: WRP on all sectors of bank1
+  *
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_WRP_SECTOR(WRPSector));
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector;
+  }
+
+  return status;
+}
+#endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
+          STM32F413xx || STM32F423xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+    defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) ||\
+    defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+  * @brief  Enable the read/write protection (PCROP) of the desired sectors.
+  * @note   This function can be used only for STM32F401xx devices.
+  * @param  Sector specifies the sector(s) to be read/write protected or unprotected.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
+  *            @arg OB_PCROP_Sector_All
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_PCROP(Sector));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector;
+  }
+
+  return status;
+}
+
+
+/**
+  * @brief  Disable the read/write protection (PCROP) of the desired sectors.
+  * @note   This function can be used only for STM32F401xx devices.
+  * @param  Sector specifies the sector(s) to be read/write protected or unprotected.
+  *          This parameter can be one of the following values:
+  *            @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5
+  *            @arg OB_PCROP_Sector_All
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_PCROP(Sector));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~Sector);
+  }
+
+  return status;
+
+}
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx
+          STM32F413xx || STM32F423xx */
+
+/**
+  * @brief  Set the read protection level.
+  * @param  Level specifies the read protection level.
+  *          This parameter can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  *
+  * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+  *
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_RDP_LEVEL(Level));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    *(__IO uint8_t *)OPTCR_BYTE1_ADDRESS = Level;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+  * @param  Iwdg Selects the IWDG mode
+  *          This parameter can be one of the following values:
+  *            @arg OB_IWDG_SW: Software IWDG selected
+  *            @arg OB_IWDG_HW: Hardware IWDG selected
+  * @param  Stop Reset event when entering STOP mode.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_STOP_NO_RST: No reset generated when entering in STOP
+  *            @arg OB_STOP_RST: Reset generated when entering in STOP
+  * @param  Stdby Reset event when entering Standby mode.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
+  *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t Stdby)
+{
+  uint8_t optiontmp = 0xFF;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_IWDG_SOURCE(Iwdg));
+  assert_param(IS_OB_STOP_SOURCE(Stop));
+  assert_param(IS_OB_STDBY_SOURCE(Stdby));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */
+    optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F);
+
+    /* Update User Option Byte */
+    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp)));
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set the BOR Level.
+  * @param  Level specifies the Option Bytes BOR Reset Level.
+  *          This parameter can be one of the following values:
+  *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
+  *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
+  *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
+  *            @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_BOR_LEVEL(Level));
+
+  /* Set the BOR Level */
+  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
+  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= Level;
+
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Return the FLASH User Option Byte value.
+  * @retval uint8_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
+  *         and RST_STDBY(Bit2).
+  */
+static uint8_t FLASH_OB_GetUser(void)
+{
+  /* Return the User Option Byte */
+  return ((uint8_t)(FLASH->OPTCR & 0xE0));
+}
+
+/**
+  * @brief  Return the FLASH Write Protection Option Bytes value.
+  * @retval uint16_t FLASH Write Protection Option Bytes value
+  */
+static uint16_t FLASH_OB_GetWRP(void)
+{
+  /* Return the FLASH write protection Register value */
+  return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
+}
+
+/**
+  * @brief  Returns the FLASH Read Protection level.
+  * @retval FLASH ReadOut Protection Status:
+  *         This parameter can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  */
+static uint8_t FLASH_OB_GetRDP(void)
+{
+  uint8_t readstatus = OB_RDP_LEVEL_0;
+
+  if (*(__IO uint8_t *)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2)
+  {
+    readstatus = OB_RDP_LEVEL_2;
+  }
+  else if (*(__IO uint8_t *)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0)
+  {
+    readstatus = OB_RDP_LEVEL_0;
+  }
+  else
+  {
+    readstatus = OB_RDP_LEVEL_1;
+  }
+
+  return readstatus;
+}
+
+/**
+  * @brief  Returns the FLASH BOR level.
+  * @retval uint8_t The FLASH BOR level:
+  *           - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
+  *           - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
+  *           - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
+  *           - OB_BOR_OFF   : Supply voltage ranges from 1.62 to 2.1 V
+  */
+static uint8_t FLASH_OB_GetBOR(void)
+{
+  /* Return the FLASH BOR level */
+  return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
+}
+
+/**
+  * @brief  Flush the instruction and data caches
+  * @retval None
+  */
+void FLASH_FlushCaches(void)
+{
+  /* Flush instruction cache  */
+  if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
+  {
+    /* Disable instruction cache  */
+    __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+    /* Reset instruction cache */
+    __HAL_FLASH_INSTRUCTION_CACHE_RESET();
+    /* Enable instruction cache */
+    __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+  }
+
+  /* Flush data cache */
+  if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
+  {
+    /* Disable data cache  */
+    __HAL_FLASH_DATA_CACHE_DISABLE();
+    /* Reset data cache */
+    __HAL_FLASH_DATA_CACHE_RESET();
+    /* Enable data cache */
+    __HAL_FLASH_DATA_CACHE_ENABLE();
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c
index 952595b..fdc5a4c 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.c
@@ -1,172 +1,172 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_flash_ramfunc.c
-  * @author  MCD Application Team
-  * @brief   FLASH RAMFUNC module driver.
-  *          This file provides a FLASH firmware functions which should be 
-  *          executed from internal SRAM
-  *            + Stop/Start the flash interface while System Run
-  *            + Enable/Disable the flash sleep while System Run
-  @verbatim
-  ==============================================================================
-                    ##### APIs executed from Internal RAM #####
-  ==============================================================================
-  [..]
-    *** ARM Compiler ***
-    --------------------
-    [..] RAM functions are defined using the toolchain options. 
-         Functions that are be executed in RAM should reside in a separate
-         source module. Using the 'Options for File' dialog you can simply change
-         the 'Code / Const' area of a module to a memory space in physical RAM.
-         Available memory areas are declared in the 'Target' tab of the 
-         Options for Target' dialog.
-
-    *** ICCARM Compiler ***
-    -----------------------
-    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
-
-    *** GNU Compiler ***
-    --------------------
-    [..] RAM functions are defined using a specific toolchain attribute
-         "__attribute__((section(".RamFunc")))".
-  
-  @endverbatim         
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup FLASH_RAMFUNC FLASH RAMFUNC
-  * @brief FLASH functions executed from RAM
-  * @{
-  */
-#ifdef HAL_FLASH_MODULE_ENABLED
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
-    defined(STM32F412Rx) || defined(STM32F412Cx)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions
-  * @{
-  */
-
-/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM 
-  *  @brief Peripheral Extended features functions 
-  *
-@verbatim   
-
- ===============================================================================
-                      ##### ramfunc functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions that should be executed from RAM 
-    transfers.
-    
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Stop the flash interface while System Run
-  * @note  This mode is only available for STM32F41xxx/STM32F446xx devices. 
-  * @note  This mode couldn't be set while executing with the flash itself. 
-  *        It should be done with specific routine executed from RAM.     
-  * @retval HAL status
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void)
-{
-  /* Enable Power ctrl clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-  /* Stop the flash interface while System Run */  
-  SET_BIT(PWR->CR, PWR_CR_FISSR);
-   
-  return HAL_OK;
-}
-
-/**
-  * @brief Start the flash interface while System Run
-  * @note  This mode is only available for STM32F411xx/STM32F446xx devices. 
-  * @note  This mode couldn't be set while executing with the flash itself. 
-  *        It should be done with specific routine executed from RAM.     
-  * @retval HAL status
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void)
-{
-  /* Enable Power ctrl clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-  /* Start the flash interface while System Run */
-  CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Enable the flash sleep while System Run
-  * @note  This mode is only available for STM32F41xxx/STM32F446xx devices. 
-  * @note  This mode could n't be set while executing with the flash itself. 
-  *        It should be done with specific routine executed from RAM.     
-  * @retval HAL status
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void)
-{
-  /* Enable Power ctrl clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-  /* Enable the flash sleep while System Run */
-  SET_BIT(PWR->CR, PWR_CR_FMSSR);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Disable the flash sleep while System Run
-  * @note  This mode is only available for STM32F41xxx/STM32F446xx devices. 
-  * @note  This mode couldn't be set while executing with the flash itself. 
-  *        It should be done with specific routine executed from RAM.     
-  * @retval HAL status
-  */
-__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void)
-{
-  /* Enable Power ctrl clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-  /* Disable the flash sleep while System Run */
-  CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
-  
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-#endif /* HAL_FLASH_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_flash_ramfunc.c
+  * @author  MCD Application Team
+  * @brief   FLASH RAMFUNC module driver.
+  *          This file provides a FLASH firmware functions which should be 
+  *          executed from internal SRAM
+  *            + Stop/Start the flash interface while System Run
+  *            + Enable/Disable the flash sleep while System Run
+  @verbatim
+  ==============================================================================
+                    ##### APIs executed from Internal RAM #####
+  ==============================================================================
+  [..]
+    *** ARM Compiler ***
+    --------------------
+    [..] RAM functions are defined using the toolchain options. 
+         Functions that are be executed in RAM should reside in a separate
+         source module. Using the 'Options for File' dialog you can simply change
+         the 'Code / Const' area of a module to a memory space in physical RAM.
+         Available memory areas are declared in the 'Target' tab of the 
+         Options for Target' dialog.
+
+    *** ICCARM Compiler ***
+    -----------------------
+    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
+
+    *** GNU Compiler ***
+    --------------------
+    [..] RAM functions are defined using a specific toolchain attribute
+         "__attribute__((section(".RamFunc")))".
+  
+  @endverbatim         
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH_RAMFUNC FLASH RAMFUNC
+  * @brief FLASH functions executed from RAM
+  * @{
+  */
+#ifdef HAL_FLASH_MODULE_ENABLED
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
+    defined(STM32F412Rx) || defined(STM32F412Cx)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAMFUNC Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions executed from internal RAM 
+  *  @brief Peripheral Extended features functions 
+  *
+@verbatim   
+
+ ===============================================================================
+                      ##### ramfunc functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions that should be executed from RAM 
+    transfers.
+    
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Stop the flash interface while System Run
+  * @note  This mode is only available for STM32F41xxx/STM32F446xx devices. 
+  * @note  This mode couldn't be set while executing with the flash itself. 
+  *        It should be done with specific routine executed from RAM.     
+  * @retval HAL status
+  */
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StopFlashInterfaceClk(void)
+{
+  /* Enable Power ctrl clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  /* Stop the flash interface while System Run */  
+  SET_BIT(PWR->CR, PWR_CR_FISSR);
+   
+  return HAL_OK;
+}
+
+/**
+  * @brief Start the flash interface while System Run
+  * @note  This mode is only available for STM32F411xx/STM32F446xx devices. 
+  * @note  This mode couldn't be set while executing with the flash itself. 
+  *        It should be done with specific routine executed from RAM.     
+  * @retval HAL status
+  */
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_StartFlashInterfaceClk(void)
+{
+  /* Enable Power ctrl clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  /* Start the flash interface while System Run */
+  CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Enable the flash sleep while System Run
+  * @note  This mode is only available for STM32F41xxx/STM32F446xx devices. 
+  * @note  This mode could n't be set while executing with the flash itself. 
+  *        It should be done with specific routine executed from RAM.     
+  * @retval HAL status
+  */
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableFlashSleepMode(void)
+{
+  /* Enable Power ctrl clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  /* Enable the flash sleep while System Run */
+  SET_BIT(PWR->CR, PWR_CR_FMSSR);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable the flash sleep while System Run
+  * @note  This mode is only available for STM32F41xxx/STM32F446xx devices. 
+  * @note  This mode couldn't be set while executing with the flash itself. 
+  *        It should be done with specific routine executed from RAM.     
+  * @retval HAL status
+  */
+__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void)
+{
+  /* Enable Power ctrl clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  /* Disable the flash sleep while System Run */
+  CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
+  
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+#endif /* HAL_FLASH_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c
index b3ce9bb..184fe58 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.c
@@ -1,533 +1,533 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_gpio.c
-  * @author  MCD Application Team
-  * @brief   GPIO HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  @verbatim
-  ==============================================================================
-                    ##### GPIO Peripheral features #####
-  ==============================================================================
-  [..] 
-  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
-  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
-  in several modes:
-  (+) Input mode 
-  (+) Analog mode
-  (+) Output mode
-  (+) Alternate function mode
-  (+) External interrupt/event lines
-
-  [..]  
-  During and just after reset, the alternate functions and external interrupt  
-  lines are not active and the I/O ports are configured in input floating mode.
-  
-  [..]   
-  All GPIO pins have weak internal pull-up and pull-down resistors, which can be 
-  activated or not.
-
-  [..]
-  In Output or Alternate mode, each IO can be configured on open-drain or push-pull
-  type and the IO speed can be selected depending on the VDD value.
-
-  [..]  
-  All ports have external interrupt/event capability. To use external interrupt 
-  lines, the port must be configured in input mode. All available GPIO pins are 
-  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
-  
-  [..]
-  The external interrupt/event controller consists of up to 23 edge detectors 
-  (16 lines are connected to GPIO) for generating event/interrupt requests (each 
-  input line can be independently configured to select the type (interrupt or event) 
-  and the corresponding trigger event (rising or falling or both). Each line can 
-  also be masked independently. 
-
-                     ##### How to use this driver #####
-  ==============================================================================  
-  [..]
-    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). 
-
-    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
-        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
-        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef 
-             structure.
-        (++) In case of Output or alternate function mode selection: the speed is 
-             configured through "Speed" member from GPIO_InitTypeDef structure.
-        (++) In alternate mode is selection, the alternate function connected to the IO
-             is configured through "Alternate" member from GPIO_InitTypeDef structure.
-        (++) Analog mode is required when a pin is to be used as ADC channel 
-             or DAC output.
-        (++) In case of external interrupt/event selection the "Mode" member from 
-             GPIO_InitTypeDef structure select the type (interrupt or event) and 
-             the corresponding trigger event (rising or falling or both).
-
-    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority 
-        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
-        HAL_NVIC_EnableIRQ().
-         
-    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
-            
-    (#) To set/reset the level of a pin configured in output mode use 
-        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
-    
-    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
-
-                 
-    (#) During and just after reset, the alternate functions are not 
-        active and the GPIO pins are configured in input floating mode (except JTAG
-        pins).
-  
-    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose 
-        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has 
-        priority over the GPIO function.
-  
-    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as 
-        general purpose PH0 and PH1, respectively, when the HSE oscillator is off. 
-        The HSE has priority over the GPIO function.
-  
-  @endverbatim
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIO GPIO
-  * @brief GPIO HAL module driver
-  * @{
-  */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Constants GPIO Private Constants
-  * @{
-  */
-
-#define GPIO_NUMBER           16U
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
-  * @{
-  */
-
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-  [..]
-    This section provides functions allowing to initialize and de-initialize the GPIOs
-    to be ready for use.
- 
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
-  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
-  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
-  *         the configuration information for the specified GPIO peripheral.
-  * @retval None
-  */
-void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
-  uint32_t position;
-  uint32_t ioposition = 0x00U;
-  uint32_t iocurrent = 0x00U;
-  uint32_t temp = 0x00U;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
-  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
-
-  /* Configure the port pins */
-  for(position = 0U; position < GPIO_NUMBER; position++)
-  {
-    /* Get the IO position */
-    ioposition = 0x01U << position;
-    /* Get the current IO position */
-    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
-
-    if(iocurrent == ioposition)
-    {
-      /*--------------------- GPIO Mode Configuration ------------------------*/
-      /* In case of Output or Alternate function mode selection */
-      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
-          (GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
-      {
-        /* Check the Speed parameter */
-        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
-        /* Configure the IO Speed */
-        temp = GPIOx->OSPEEDR; 
-        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
-        temp |= (GPIO_Init->Speed << (position * 2U));
-        GPIOx->OSPEEDR = temp;
-
-        /* Configure the IO Output Type */
-        temp = GPIOx->OTYPER;
-        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
-        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
-        GPIOx->OTYPER = temp;
-       }
-
-      if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
-      {
-        /* Check the parameters */
-        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
-        
-        /* Activate the Pull-up or Pull down resistor for the current IO */
-        temp = GPIOx->PUPDR;
-        temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
-        temp |= ((GPIO_Init->Pull) << (position * 2U));
-        GPIOx->PUPDR = temp;
-      }
-
-      /* In case of Alternate function mode selection */
-      if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
-      {
-        /* Check the Alternate function parameter */
-        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-        /* Configure Alternate function mapped with the current IO */
-        temp = GPIOx->AFR[position >> 3U];
-        temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
-        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
-        GPIOx->AFR[position >> 3U] = temp;
-      }
-
-      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
-      temp = GPIOx->MODER;
-      temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
-      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
-      GPIOx->MODER = temp;
-
-      /*--------------------- EXTI Mode Configuration ------------------------*/
-      /* Configure the External Interrupt or event for the current IO */
-      if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
-      {
-        /* Enable SYSCFG Clock */
-        __HAL_RCC_SYSCFG_CLK_ENABLE();
-
-        temp = SYSCFG->EXTICR[position >> 2U];
-        temp &= ~(0x0FU << (4U * (position & 0x03U)));
-        temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
-        SYSCFG->EXTICR[position >> 2U] = temp;
-
-        /* Clear Rising Falling edge configuration */
-        temp = EXTI->RTSR;
-        temp &= ~((uint32_t)iocurrent);
-        if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->RTSR = temp;
-
-        temp = EXTI->FTSR;
-        temp &= ~((uint32_t)iocurrent);
-        if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->FTSR = temp;
-
-        temp = EXTI->EMR;
-        temp &= ~((uint32_t)iocurrent);
-        if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->EMR = temp;
-
-        /* Clear EXTI line configuration */
-        temp = EXTI->IMR;
-        temp &= ~((uint32_t)iocurrent);
-        if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
-        {
-          temp |= iocurrent;
-        }
-        EXTI->IMR = temp;
-      }
-    }
-  }
-}
-
-/**
-  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
-  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
-  * @param  GPIO_Pin specifies the port bit to be written.
-  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  * @retval None
-  */
-void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
-{
-  uint32_t position;
-  uint32_t ioposition = 0x00U;
-  uint32_t iocurrent = 0x00U;
-  uint32_t tmp = 0x00U;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  
-  /* Configure the port pins */
-  for(position = 0U; position < GPIO_NUMBER; position++)
-  {
-    /* Get the IO position */
-    ioposition = 0x01U << position;
-    /* Get the current IO position */
-    iocurrent = (GPIO_Pin) & ioposition;
-
-    if(iocurrent == ioposition)
-    {
-      /*------------------------- EXTI Mode Configuration --------------------*/
-      tmp = SYSCFG->EXTICR[position >> 2U];
-      tmp &= (0x0FU << (4U * (position & 0x03U)));
-      if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))))
-      {
-        /* Clear EXTI line configuration */
-        EXTI->IMR &= ~((uint32_t)iocurrent);
-        EXTI->EMR &= ~((uint32_t)iocurrent);
-        
-        /* Clear Rising Falling edge configuration */
-        EXTI->FTSR &= ~((uint32_t)iocurrent);
-        EXTI->RTSR &= ~((uint32_t)iocurrent);
-
-        /* Configure the External Interrupt or event for the current IO */
-        tmp = 0x0FU << (4U * (position & 0x03U));
-        SYSCFG->EXTICR[position >> 2U] &= ~tmp;
-      }
-
-      /*------------------------- GPIO Mode Configuration --------------------*/
-      /* Configure IO Direction in Input Floating Mode */
-      GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
-
-      /* Configure the default Alternate Function in current IO */
-      GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
-
-      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
-      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
-
-      /* Configure the default value IO Output Type */
-      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;
-
-      /* Configure the default value for IO Speed */
-      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions 
-  *  @brief   GPIO Read and Write
-  *
-@verbatim
- ===============================================================================
-                       ##### IO operation functions #####
- ===============================================================================
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reads the specified input port pin.
-  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
-  * @param  GPIO_Pin specifies the port bit to read.
-  *         This parameter can be GPIO_PIN_x where x can be (0..15).
-  * @retval The input port pin value.
-  */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  GPIO_PinState bitstatus;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
-  {
-    bitstatus = GPIO_PIN_SET;
-  }
-  else
-  {
-    bitstatus = GPIO_PIN_RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Sets or clears the selected data port bit.
-  *
-  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
-  *         accesses. In this way, there is no risk of an IRQ occurring between
-  *         the read and the modify access.
-  *
-  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
-  * @param  GPIO_Pin specifies the port bit to be written.
-  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  * @param  PinState specifies the value to be written to the selected bit.
-  *          This parameter can be one of the GPIO_PinState enum values:
-  *            @arg GPIO_PIN_RESET: to clear the port pin
-  *            @arg GPIO_PIN_SET: to set the port pin
-  * @retval None
-  */
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-  assert_param(IS_GPIO_PIN_ACTION(PinState));
-
-  if(PinState != GPIO_PIN_RESET)
-  {
-    GPIOx->BSRR = GPIO_Pin;
-  }
-  else
-  {
-    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
-  }
-}
-
-/**
-  * @brief  Toggles the specified GPIO pins.
-  * @param  GPIOx Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
-  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
-  * @param  GPIO_Pin Specifies the pins to be toggled.
-  * @retval None
-  */
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  uint32_t odr;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  /* get current Output Data Register value */
-  odr = GPIOx->ODR;
-
-  /* Set selected pins that were at low level, and reset ones that were high */
-  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
-}
-
-/**
-  * @brief  Locks GPIO Pins configuration registers.
-  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
-  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
-  * @note   The configuration of the locked GPIO pins can no longer be modified
-  *         until the next reset.
-  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F4 family
-  * @param  GPIO_Pin specifies the port bit to be locked.
-  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  __IO uint32_t tmp = GPIO_LCKR_LCKK;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  /* Apply lock key write sequence */
-  tmp |= GPIO_Pin;
-  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
-  GPIOx->LCKR = tmp;
-  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
-  GPIOx->LCKR = GPIO_Pin;
-  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
-  GPIOx->LCKR = tmp;
-  /* Read LCKR register. This read is mandatory to complete key lock sequence */
-  tmp = GPIOx->LCKR;
-
-  /* Read again in order to confirm lock is active */
- if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
-  {
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  This function handles EXTI interrupt request.
-  * @param  GPIO_Pin Specifies the pins connected EXTI line
-  * @retval None
-  */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
-  /* EXTI line interrupt detected */
-  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
-  {
-    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
-    HAL_GPIO_EXTI_Callback(GPIO_Pin);
-  }
-}
-
-/**
-  * @brief  EXTI line detection callbacks.
-  * @param  GPIO_Pin Specifies the pins connected EXTI line
-  * @retval None
-  */
-__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(GPIO_Pin);
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_GPIO_EXTI_Callback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-#endif /* HAL_GPIO_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_gpio.c
+  * @author  MCD Application Team
+  * @brief   GPIO HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                    ##### GPIO Peripheral features #####
+  ==============================================================================
+  [..] 
+  Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
+  port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
+  in several modes:
+  (+) Input mode 
+  (+) Analog mode
+  (+) Output mode
+  (+) Alternate function mode
+  (+) External interrupt/event lines
+
+  [..]  
+  During and just after reset, the alternate functions and external interrupt  
+  lines are not active and the I/O ports are configured in input floating mode.
+  
+  [..]   
+  All GPIO pins have weak internal pull-up and pull-down resistors, which can be 
+  activated or not.
+
+  [..]
+  In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+  type and the IO speed can be selected depending on the VDD value.
+
+  [..]  
+  All ports have external interrupt/event capability. To use external interrupt 
+  lines, the port must be configured in input mode. All available GPIO pins are 
+  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+  
+  [..]
+  The external interrupt/event controller consists of up to 23 edge detectors 
+  (16 lines are connected to GPIO) for generating event/interrupt requests (each 
+  input line can be independently configured to select the type (interrupt or event) 
+  and the corresponding trigger event (rising or falling or both). Each line can 
+  also be masked independently. 
+
+                     ##### How to use this driver #####
+  ==============================================================================  
+  [..]
+    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). 
+
+    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef 
+             structure.
+        (++) In case of Output or alternate function mode selection: the speed is 
+             configured through "Speed" member from GPIO_InitTypeDef structure.
+        (++) In alternate mode is selection, the alternate function connected to the IO
+             is configured through "Alternate" member from GPIO_InitTypeDef structure.
+        (++) Analog mode is required when a pin is to be used as ADC channel 
+             or DAC output.
+        (++) In case of external interrupt/event selection the "Mode" member from 
+             GPIO_InitTypeDef structure select the type (interrupt or event) and 
+             the corresponding trigger event (rising or falling or both).
+
+    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority 
+        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+        HAL_NVIC_EnableIRQ().
+         
+    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+            
+    (#) To set/reset the level of a pin configured in output mode use 
+        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+    
+    (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+
+                 
+    (#) During and just after reset, the alternate functions are not 
+        active and the GPIO pins are configured in input floating mode (except JTAG
+        pins).
+  
+    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose 
+        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has 
+        priority over the GPIO function.
+  
+    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as 
+        general purpose PH0 and PH1, respectively, when the HSE oscillator is off. 
+        The HSE has priority over the GPIO function.
+  
+  @endverbatim
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIO GPIO
+  * @brief GPIO HAL module driver
+  * @{
+  */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Constants GPIO Private Constants
+  * @{
+  */
+
+#define GPIO_NUMBER           16U
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim    
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+  [..]
+    This section provides functions allowing to initialize and de-initialize the GPIOs
+    to be ready for use.
+ 
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+  uint32_t position;
+  uint32_t ioposition = 0x00U;
+  uint32_t iocurrent = 0x00U;
+  uint32_t temp = 0x00U;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+
+  /* Configure the port pins */
+  for(position = 0U; position < GPIO_NUMBER; position++)
+  {
+    /* Get the IO position */
+    ioposition = 0x01U << position;
+    /* Get the current IO position */
+    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
+
+    if(iocurrent == ioposition)
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Output or Alternate function mode selection */
+      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
+          (GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR; 
+        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+        temp |= (GPIO_Init->Speed << (position * 2U));
+        GPIOx->OSPEEDR = temp;
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
+        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
+        GPIOx->OTYPER = temp;
+       }
+
+      if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
+      {
+        /* Check the parameters */
+        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+        
+        /* Activate the Pull-up or Pull down resistor for the current IO */
+        temp = GPIOx->PUPDR;
+        temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+        temp |= ((GPIO_Init->Pull) << (position * 2U));
+        GPIOx->PUPDR = temp;
+      }
+
+      /* In case of Alternate function mode selection */
+      if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
+      {
+        /* Check the Alternate function parameter */
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3U];
+        temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
+        GPIOx->AFR[position >> 3U] = temp;
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+      temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
+      GPIOx->MODER = temp;
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
+      {
+        /* Enable SYSCFG Clock */
+        __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+        temp = SYSCFG->EXTICR[position >> 2U];
+        temp &= ~(0x0FU << (4U * (position & 0x03U)));
+        temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
+        SYSCFG->EXTICR[position >> 2U] = temp;
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->RTSR = temp;
+
+        temp = EXTI->FTSR;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->FTSR = temp;
+
+        temp = EXTI->EMR;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->EMR = temp;
+
+        /* Clear EXTI line configuration */
+        temp = EXTI->IMR;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->IMR = temp;
+      }
+    }
+  }
+}
+
+/**
+  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+  * @param  GPIO_Pin specifies the port bit to be written.
+  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+{
+  uint32_t position;
+  uint32_t ioposition = 0x00U;
+  uint32_t iocurrent = 0x00U;
+  uint32_t tmp = 0x00U;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  
+  /* Configure the port pins */
+  for(position = 0U; position < GPIO_NUMBER; position++)
+  {
+    /* Get the IO position */
+    ioposition = 0x01U << position;
+    /* Get the current IO position */
+    iocurrent = (GPIO_Pin) & ioposition;
+
+    if(iocurrent == ioposition)
+    {
+      /*------------------------- EXTI Mode Configuration --------------------*/
+      tmp = SYSCFG->EXTICR[position >> 2U];
+      tmp &= (0x0FU << (4U * (position & 0x03U)));
+      if(tmp == ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))))
+      {
+        /* Clear EXTI line configuration */
+        EXTI->IMR &= ~((uint32_t)iocurrent);
+        EXTI->EMR &= ~((uint32_t)iocurrent);
+        
+        /* Clear Rising Falling edge configuration */
+        EXTI->FTSR &= ~((uint32_t)iocurrent);
+        EXTI->RTSR &= ~((uint32_t)iocurrent);
+
+        /* Configure the External Interrupt or event for the current IO */
+        tmp = 0x0FU << (4U * (position & 0x03U));
+        SYSCFG->EXTICR[position >> 2U] &= ~tmp;
+      }
+
+      /*------------------------- GPIO Mode Configuration --------------------*/
+      /* Configure IO Direction in Input Floating Mode */
+      GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (position * 2U));
+
+      /* Configure the default Alternate Function in current IO */
+      GPIOx->AFR[position >> 3U] &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
+
+      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
+
+      /* Configure the default value IO Output Type */
+      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT_0 << position) ;
+
+      /* Configure the default value for IO Speed */
+      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions 
+  *  @brief   GPIO Read and Write
+  *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+  * @param  GPIO_Pin specifies the port bit to read.
+  *         This parameter can be GPIO_PIN_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  GPIO_PinState bitstatus;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
+  {
+    bitstatus = GPIO_PIN_SET;
+  }
+  else
+  {
+    bitstatus = GPIO_PIN_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  *
+  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  *
+  * @param  GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+  * @param  GPIO_Pin specifies the port bit to be written.
+  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @param  PinState specifies the value to be written to the selected bit.
+  *          This parameter can be one of the GPIO_PinState enum values:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if(PinState != GPIO_PIN_RESET)
+  {
+    GPIOx->BSRR = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
+  }
+}
+
+/**
+  * @brief  Toggles the specified GPIO pins.
+  * @param  GPIOx Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or
+  *                      x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices.
+  * @param  GPIO_Pin Specifies the pins to be toggled.
+  * @retval None
+  */
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint32_t odr;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* get current Output Data Register value */
+  odr = GPIOx->ODR;
+
+  /* Set selected pins that were at low level, and reset ones that were high */
+  GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin);
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next reset.
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F4 family
+  * @param  GPIO_Pin specifies the port bit to be locked.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Apply lock key write sequence */
+  tmp |= GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+  GPIOx->LCKR = GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Read LCKR register. This read is mandatory to complete key lock sequence */
+  tmp = GPIOx->LCKR;
+
+  /* Read again in order to confirm lock is active */
+ if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  This function handles EXTI interrupt request.
+  * @param  GPIO_Pin Specifies the pins connected EXTI line
+  * @retval None
+  */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+  /* EXTI line interrupt detected */
+  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+  {
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+}
+
+/**
+  * @brief  EXTI line detection callbacks.
+  * @param  GPIO_Pin Specifies the pins connected EXTI line
+  * @retval None
+  */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
+  /* NOTE: This function Should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c
index b4bb483..bf60fc0 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c
@@ -1,571 +1,571 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_pwr.c
-  * @author  MCD Application Team
-  * @brief   PWR HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Power Controller (PWR) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions 
-  *         
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PWR PWR
-  * @brief PWR HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup PWR_Private_Constants
-  * @{
-  */
-  
-/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
-  * @{
-  */     
-#define PVD_MODE_IT               0x00010000U
-#define PVD_MODE_EVT              0x00020000U
-#define PVD_RISING_EDGE           0x00000001U
-#define PVD_FALLING_EDGE          0x00000002U
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */    
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Functions PWR Exported Functions
-  * @{
-  */
-
-/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
-  *  @brief    Initialization and de-initialization functions
-  *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]
-      After reset, the backup domain (RTC registers, RTC backup data 
-      registers and backup SRAM) is protected against possible unwanted 
-      write accesses. 
-      To enable access to the RTC Domain and RTC registers, proceed as follows:
-        (+) Enable the Power Controller (PWR) APB1 interface clock using the
-            __HAL_RCC_PWR_CLK_ENABLE() macro.
-        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
-  * @retval None
-  */
-void HAL_PWR_DeInit(void)
-{
-  __HAL_RCC_PWR_FORCE_RESET();
-  __HAL_RCC_PWR_RELEASE_RESET();
-}
-
-/**
-  * @brief Enables access to the backup domain (RTC registers, RTC 
-  *         backup data registers and backup SRAM).
-  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
-  *         Backup Domain Access should be kept enabled.
-  * @note The following sequence is required to bypass the delay between
-  *         DBP bit programming and the effective enabling  of the backup domain.
-  *         Please check the Errata Sheet for more details under "Possible delay
-  *         in backup domain protection disabling/enabling after programming the
-  *         DBP bit" section.
-  * @retval None
-  */
-void HAL_PWR_EnableBkUpAccess(void)
-{
-  __IO uint32_t dummyread;
-  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
-  dummyread = PWR->CR;
-  UNUSED(dummyread);
-}
-
-/**
-  * @brief Disables access to the backup domain (RTC registers, RTC 
-  *         backup data registers and backup SRAM).
-  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
-  *         Backup Domain Access should be kept enabled.
-  * @note The following sequence is required to bypass the delay between
-  *         DBP bit programming and the effective disabling  of the backup domain.
-  *         Please check the Errata Sheet for more details under "Possible delay
-  *         in backup domain protection disabling/enabling after programming the
-  *         DBP bit" section.
-  * @retval None
-  */
-void HAL_PWR_DisableBkUpAccess(void)
-{
-  __IO uint32_t dummyread;
-  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
-  dummyread = PWR->CR;
-  UNUSED(dummyread);
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 
-  *  @brief Low Power modes configuration functions 
-  *
-@verbatim
-
- ===============================================================================
-                 ##### Peripheral Control functions #####
- ===============================================================================
-     
-    *** PVD configuration ***
-    =========================
-    [..]
-      (+) The PVD is used to monitor the VDD power supply by comparing it to a 
-          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
-      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 
-          than the PVD threshold. This event is internally connected to the EXTI 
-          line16 and can generate an interrupt if enabled. This is done through
-          __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
-      (+) The PVD is stopped in Standby mode.
-
-    *** Wake-up pin configuration ***
-    ================================
-    [..]
-      (+) Wake-up pin is used to wake up the system from Standby mode. This pin is 
-          forced in input pull-down configuration and is active on rising edges.
-      (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
-	   (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
-           (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx  there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 
-
-    *** Low Power modes configuration ***
-    =====================================
-    [..]
-      The devices feature 3 low-power modes:
-      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
-      (+) Stop mode: all clocks are stopped, regulator running, regulator 
-          in low power mode
-      (+) Standby mode: 1.2V domain powered off.
-   
-   *** Sleep mode ***
-   ==================
-    [..]
-      (+) Entry:
-        The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
-              functions with
-          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-      
-      -@@- The Regulator parameter is not used for the STM32F4 family 
-              and is kept as parameter just to maintain compatibility with the 
-              lower power families (STM32L).
-      (+) Exit:
-        Any peripheral interrupt acknowledged by the nested vectored interrupt 
-              controller (NVIC) can wake up the device from Sleep mode.
-
-   *** Stop mode ***
-   =================
-    [..]
-      In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
-      and the HSE RC oscillators are disabled. Internal SRAM and register contents 
-      are preserved.
-      The voltage regulator can be configured either in normal or low-power mode.
-      To minimize the consumption In Stop mode, FLASH can be powered off before 
-      entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
-      It can be switched on again by software after exiting the Stop mode using
-      the HAL_PWREx_DisableFlashPowerDown() function. 
-
-      (+) Entry:
-         The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) 
-             function with:
-          (++) Main regulator ON.
-          (++) Low Power regulator ON.
-      (+) Exit:
-        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
-
-   *** Standby mode ***
-   ====================
-    [..]
-    (+)
-      The Standby mode allows to achieve the lowest power consumption. It is based 
-      on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. 
-      The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 
-      the HSE oscillator are also switched off. SRAM and register contents are lost 
-      except for the RTC registers, RTC backup registers, backup SRAM and Standby 
-      circuitry.
-   
-      The voltage regulator is OFF.
-      
-      (++) Entry:
-        (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
-      (++) Exit:
-        (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
-             tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
-
-   *** Auto-wake-up (AWU) from low-power mode ***
-   =============================================
-    [..]
-    
-     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 
-      Wake-up event, a tamper event or a time-stamp event, without depending on 
-      an external interrupt (Auto-wake-up mode).
-
-      (+) RTC auto-wake-up (AWU) from the Stop and Standby modes
-       
-        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to 
-              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
-
-        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
-             is necessary to configure the RTC to detect the tamper or time stamp event using the
-                HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
-                  
-        (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
-              configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
-  * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
-  *        information for the PVD.
-  * @note Refer to the electrical characteristics of your device datasheet for
-  *         more details about the voltage threshold corresponding to each 
-  *         detection level.
-  * @retval None
-  */
-void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
-  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
-  
-  /* Set PLS[7:5] bits according to PVDLevel value */
-  MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
-  
-  /* Clear any previous config. Keep it clear if no event or IT mode is selected */
-  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
-  __HAL_PWR_PVD_EXTI_DISABLE_IT();
-  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
-  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 
-
-  /* Configure interrupt mode */
-  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_IT();
-  }
-  
-  /* Configure event mode */
-  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
-  }
-  
-  /* Configure the edge */
-  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
-  }
-  
-  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
-  }
-}
-
-/**
-  * @brief Enables the Power Voltage Detector(PVD).
-  * @retval None
-  */
-void HAL_PWR_EnablePVD(void)
-{
-  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief Disables the Power Voltage Detector(PVD).
-  * @retval None
-  */
-void HAL_PWR_DisablePVD(void)
-{
-  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief Enables the Wake-up PINx functionality.
-  * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
-  *         This parameter can be one of the following values:
-  *           @arg PWR_WAKEUP_PIN1
-  *           @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
-  *           @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
-  * @retval None
-  */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
-{
-  /* Check the parameter */
-  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
-
-  /* Enable the wake up pin */
-  SET_BIT(PWR->CSR, WakeUpPinx);
-}
-
-/**
-  * @brief Disables the Wake-up PINx functionality.
-  * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
-  *         This parameter can be one of the following values:
-  *           @arg PWR_WAKEUP_PIN1
-  *           @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
-  *           @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
-  * @retval None
-  */
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
-{
-  /* Check the parameter */
-  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));  
-
-  /* Disable the wake up pin */
-  CLEAR_BIT(PWR->CSR, WakeUpPinx);
-}
-  
-/**
-  * @brief Enters Sleep mode.
-  *   
-  * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
-  * 
-  * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
-  *       systick interrupt when used as time base for Timeout 
-  *                
-  * @param Regulator Specifies the regulator state in SLEEP mode.
-  *            This parameter can be one of the following values:
-  *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
-  *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
-  * @note This parameter is not used for the STM32F4 family and is kept as parameter
-  *       just to maintain compatibility with the lower power families.
-  * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-  *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-  * @retval None
-  */
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(Regulator));
-  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
-
-  /* Clear SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-  /* Select SLEEP mode entry -------------------------------------------------*/
-  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
-  {   
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __SEV();
-    __WFE();
-    __WFE();
-  }
-}
-
-/**
-  * @brief Enters Stop mode. 
-  * @note In Stop mode, all I/O pins keep the same state as in Run mode.
-  * @note When exiting Stop mode by issuing an interrupt or a wake-up event, 
-  *         the HSI RC oscillator is selected as system clock.
-  * @note When the voltage regulator operates in low power mode, an additional 
-  *         startup delay is incurred when waking up from Stop mode. 
-  *         By keeping the internal regulator ON during Stop mode, the consumption 
-  *         is higher although the startup time is reduced.    
-  * @param Regulator Specifies the regulator state in Stop mode.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
-  *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
-  * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
-  *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
-  * @retval None
-  */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(Regulator));
-  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-  
-  /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
-  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
-  
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-  
-  /* Select Stop mode entry --------------------------------------------------*/
-  if(STOPEntry == PWR_STOPENTRY_WFI)
-  {   
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __SEV();
-    __WFE();
-    __WFE();
-  }
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));  
-}
-
-/**
-  * @brief Enters Standby mode.
-  * @note In Standby mode, all I/O pins are high impedance except for:
-  *          - Reset pad (still available) 
-  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 
-  *            Alarm out, or RTC clock calibration out.
-  *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.  
-  *          - WKUP pin 1 (PA0) if enabled.       
-  * @retval None
-  */
-void HAL_PWR_EnterSTANDBYMode(void)
-{
-  /* Select Standby mode */
-  SET_BIT(PWR->CR, PWR_CR_PDDS);
-
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-  
-  /* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
-  __force_stores();
-#endif
-  /* Request Wait For Interrupt */
-  __WFI();
-}
-
-/**
-  * @brief This function handles the PWR PVD interrupt request.
-  * @note This API should be called under the PVD_IRQHandler().
-  * @retval None
-  */
-void HAL_PWR_PVD_IRQHandler(void)
-{
-  /* Check PWR Exti flag */
-  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
-  {
-    /* PWR PVD interrupt user callback */
-    HAL_PWR_PVDCallback();
-    
-    /* Clear PWR Exti pending bit */
-    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
-  }
-}
-
-/**
-  * @brief  PWR PVD interrupt callback
-  * @retval None
-  */
-__weak void HAL_PWR_PVDCallback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PWR_PVDCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 
-  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
-  *       re-enters SLEEP mode when an interruption handling is over.
-  *       Setting this bit is useful when the processor is expected to run only on
-  *       interruptions handling.         
-  * @retval None
-  */
-void HAL_PWR_EnableSleepOnExit(void)
-{
-  /* Set SLEEPONEXIT bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
-  * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. 
-  * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
-  *       re-enters SLEEP mode when an interruption handling is over.          
-  * @retval None
-  */
-void HAL_PWR_DisableSleepOnExit(void)
-{
-  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
-}
-
-/**
-  * @brief Enables CORTEX M4 SEVONPEND bit. 
-  * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 
-  *       WFE to wake up when an interrupt moves from inactive to pended.
-  * @retval None
-  */
-void HAL_PWR_EnableSEVOnPend(void)
-{
-  /* Set SEVONPEND bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
-  * @brief Disables CORTEX M4 SEVONPEND bit. 
-  * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 
-  *       WFE to wake up when an interrupt moves from inactive to pended.         
-  * @retval None
-  */
-void HAL_PWR_DisableSEVOnPend(void)
-{
-  /* Clear SEVONPEND bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
-}
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_pwr.c
+  * @author  MCD Application Team
+  * @brief   PWR HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions 
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWR PWR
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup PWR_Private_Constants
+  * @{
+  */
+  
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+  * @{
+  */     
+#define PVD_MODE_IT               0x00010000U
+#define PVD_MODE_EVT              0x00020000U
+#define PVD_RISING_EDGE           0x00000001U
+#define PVD_FALLING_EDGE          0x00000002U
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */    
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
+  *  @brief    Initialization and de-initialization functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+      After reset, the backup domain (RTC registers, RTC backup data 
+      registers and backup SRAM) is protected against possible unwanted 
+      write accesses. 
+      To enable access to the RTC Domain and RTC registers, proceed as follows:
+        (+) Enable the Power Controller (PWR) APB1 interface clock using the
+            __HAL_RCC_PWR_CLK_ENABLE() macro.
+        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Deinitializes the HAL PWR peripheral registers to their default reset values.
+  * @retval None
+  */
+void HAL_PWR_DeInit(void)
+{
+  __HAL_RCC_PWR_FORCE_RESET();
+  __HAL_RCC_PWR_RELEASE_RESET();
+}
+
+/**
+  * @brief Enables access to the backup domain (RTC registers, RTC 
+  *         backup data registers and backup SRAM).
+  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
+  *         Backup Domain Access should be kept enabled.
+  * @note The following sequence is required to bypass the delay between
+  *         DBP bit programming and the effective enabling  of the backup domain.
+  *         Please check the Errata Sheet for more details under "Possible delay
+  *         in backup domain protection disabling/enabling after programming the
+  *         DBP bit" section.
+  * @retval None
+  */
+void HAL_PWR_EnableBkUpAccess(void)
+{
+  __IO uint32_t dummyread;
+  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
+  dummyread = PWR->CR;
+  UNUSED(dummyread);
+}
+
+/**
+  * @brief Disables access to the backup domain (RTC registers, RTC 
+  *         backup data registers and backup SRAM).
+  * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
+  *         Backup Domain Access should be kept enabled.
+  * @note The following sequence is required to bypass the delay between
+  *         DBP bit programming and the effective disabling  of the backup domain.
+  *         Please check the Errata Sheet for more details under "Possible delay
+  *         in backup domain protection disabling/enabling after programming the
+  *         DBP bit" section.
+  * @retval None
+  */
+void HAL_PWR_DisableBkUpAccess(void)
+{
+  __IO uint32_t dummyread;
+  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
+  dummyread = PWR->CR;
+  UNUSED(dummyread);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 
+  *  @brief Low Power modes configuration functions 
+  *
+@verbatim
+
+ ===============================================================================
+                 ##### Peripheral Control functions #####
+ ===============================================================================
+     
+    *** PVD configuration ***
+    =========================
+    [..]
+      (+) The PVD is used to monitor the VDD power supply by comparing it to a 
+          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 
+          than the PVD threshold. This event is internally connected to the EXTI 
+          line16 and can generate an interrupt if enabled. This is done through
+          __HAL_PWR_PVD_EXTI_ENABLE_IT() macro.
+      (+) The PVD is stopped in Standby mode.
+
+    *** Wake-up pin configuration ***
+    ================================
+    [..]
+      (+) Wake-up pin is used to wake up the system from Standby mode. This pin is 
+          forced in input pull-down configuration and is active on rising edges.
+      (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
+	   (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
+           (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx  there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 
+
+    *** Low Power modes configuration ***
+    =====================================
+    [..]
+      The devices feature 3 low-power modes:
+      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running.
+      (+) Stop mode: all clocks are stopped, regulator running, regulator 
+          in low power mode
+      (+) Standby mode: 1.2V domain powered off.
+   
+   *** Sleep mode ***
+   ==================
+    [..]
+      (+) Entry:
+        The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI)
+              functions with
+          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+      
+      -@@- The Regulator parameter is not used for the STM32F4 family 
+              and is kept as parameter just to maintain compatibility with the 
+              lower power families (STM32L).
+      (+) Exit:
+        Any peripheral interrupt acknowledged by the nested vectored interrupt 
+              controller (NVIC) can wake up the device from Sleep mode.
+
+   *** Stop mode ***
+   =================
+    [..]
+      In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
+      and the HSE RC oscillators are disabled. Internal SRAM and register contents 
+      are preserved.
+      The voltage regulator can be configured either in normal or low-power mode.
+      To minimize the consumption In Stop mode, FLASH can be powered off before 
+      entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function.
+      It can be switched on again by software after exiting the Stop mode using
+      the HAL_PWREx_DisableFlashPowerDown() function. 
+
+      (+) Entry:
+         The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) 
+             function with:
+          (++) Main regulator ON.
+          (++) Low Power regulator ON.
+      (+) Exit:
+        Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+
+   *** Standby mode ***
+   ====================
+    [..]
+    (+)
+      The Standby mode allows to achieve the lowest power consumption. It is based 
+      on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. 
+      The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 
+      the HSE oscillator are also switched off. SRAM and register contents are lost 
+      except for the RTC registers, RTC backup registers, backup SRAM and Standby 
+      circuitry.
+   
+      The voltage regulator is OFF.
+      
+      (++) Entry:
+        (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
+      (++) Exit:
+        (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up,
+             tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
+
+   *** Auto-wake-up (AWU) from low-power mode ***
+   =============================================
+    [..]
+    
+     (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 
+      Wake-up event, a tamper event or a time-stamp event, without depending on 
+      an external interrupt (Auto-wake-up mode).
+
+      (+) RTC auto-wake-up (AWU) from the Stop and Standby modes
+       
+        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to 
+              configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
+
+        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
+             is necessary to configure the RTC to detect the tamper or time stamp event using the
+                HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
+                  
+        (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to
+              configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
+  *        information for the PVD.
+  * @note Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage threshold corresponding to each 
+  *         detection level.
+  * @retval None
+  */
+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+  
+  /* Set PLS[7:5] bits according to PVDLevel value */
+  MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
+  
+  /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+  __HAL_PWR_PVD_EXTI_DISABLE_IT();
+  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
+  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 
+
+  /* Configure interrupt mode */
+  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_IT();
+  }
+  
+  /* Configure event mode */
+  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+  }
+  
+  /* Configure the edge */
+  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
+  }
+  
+  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+  }
+}
+
+/**
+  * @brief Enables the Power Voltage Detector(PVD).
+  * @retval None
+  */
+void HAL_PWR_EnablePVD(void)
+{
+  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief Disables the Power Voltage Detector(PVD).
+  * @retval None
+  */
+void HAL_PWR_DisablePVD(void)
+{
+  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
+}
+
+/**
+  * @brief Enables the Wake-up PINx functionality.
+  * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
+  *         This parameter can be one of the following values:
+  *           @arg PWR_WAKEUP_PIN1
+  *           @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
+  *           @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
+  * @retval None
+  */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
+{
+  /* Check the parameter */
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+
+  /* Enable the wake up pin */
+  SET_BIT(PWR->CSR, WakeUpPinx);
+}
+
+/**
+  * @brief Disables the Wake-up PINx functionality.
+  * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
+  *         This parameter can be one of the following values:
+  *           @arg PWR_WAKEUP_PIN1
+  *           @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
+  *           @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
+  * @retval None
+  */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+{
+  /* Check the parameter */
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));  
+
+  /* Disable the wake up pin */
+  CLEAR_BIT(PWR->CSR, WakeUpPinx);
+}
+  
+/**
+  * @brief Enters Sleep mode.
+  *   
+  * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
+  * 
+  * @note In Sleep mode, the systick is stopped to avoid exit from this mode with
+  *       systick interrupt when used as time base for Timeout 
+  *                
+  * @param Regulator Specifies the regulator state in SLEEP mode.
+  *            This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
+  *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
+  * @note This parameter is not used for the STM32F4 family and is kept as parameter
+  *       just to maintain compatibility with the lower power families.
+  * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+  *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+  * @retval None
+  */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+  /* Select SLEEP mode entry -------------------------------------------------*/
+  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+}
+
+/**
+  * @brief Enters Stop mode. 
+  * @note In Stop mode, all I/O pins keep the same state as in Run mode.
+  * @note When exiting Stop mode by issuing an interrupt or a wake-up event, 
+  *         the HSI RC oscillator is selected as system clock.
+  * @note When the voltage regulator operates in low power mode, an additional 
+  *         startup delay is incurred when waking up from Stop mode. 
+  *         By keeping the internal regulator ON during Stop mode, the consumption 
+  *         is higher although the startup time is reduced.    
+  * @param Regulator Specifies the regulator state in Stop mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
+  *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
+  * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
+  *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
+  * @retval None
+  */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+  
+  /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */
+  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator);
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+  
+  /* Select Stop mode entry --------------------------------------------------*/
+  if(STOPEntry == PWR_STOPENTRY_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));  
+}
+
+/**
+  * @brief Enters Standby mode.
+  * @note In Standby mode, all I/O pins are high impedance except for:
+  *          - Reset pad (still available) 
+  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 
+  *            Alarm out, or RTC clock calibration out.
+  *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.  
+  *          - WKUP pin 1 (PA0) if enabled.       
+  * @retval None
+  */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+  /* Select Standby mode */
+  SET_BIT(PWR->CR, PWR_CR_PDDS);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+  
+  /* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @brief This function handles the PWR PVD interrupt request.
+  * @note This API should be called under the PVD_IRQHandler().
+  * @retval None
+  */
+void HAL_PWR_PVD_IRQHandler(void)
+{
+  /* Check PWR Exti flag */
+  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
+  {
+    /* PWR PVD interrupt user callback */
+    HAL_PWR_PVDCallback();
+    
+    /* Clear PWR Exti pending bit */
+    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
+  }
+}
+
+/**
+  * @brief  PWR PVD interrupt callback
+  * @retval None
+  */
+__weak void HAL_PWR_PVDCallback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_PWR_PVDCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 
+  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
+  *       re-enters SLEEP mode when an interruption handling is over.
+  *       Setting this bit is useful when the processor is expected to run only on
+  *       interruptions handling.         
+  * @retval None
+  */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. 
+  * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
+  *       re-enters SLEEP mode when an interruption handling is over.          
+  * @retval None
+  */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+/**
+  * @brief Enables CORTEX M4 SEVONPEND bit. 
+  * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 
+  *       WFE to wake up when an interrupt moves from inactive to pended.
+  * @retval None
+  */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+  /* Set SEVONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @brief Disables CORTEX M4 SEVONPEND bit. 
+  * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 
+  *       WFE to wake up when an interrupt moves from inactive to pended.         
+  * @retval None
+  */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+  /* Clear SEVONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c
index 77f9c35..1acca55 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.c
@@ -1,600 +1,600 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_pwr_ex.c
-  * @author  MCD Application Team
-  * @brief   Extended PWR HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of PWR extension peripheral:           
-  *           + Peripheral Extended features functions
-  *         
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PWREx PWREx
-  * @brief PWR HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup PWREx_Private_Constants
-  * @{
-  */    
-#define PWR_OVERDRIVE_TIMEOUT_VALUE  1000U
-#define PWR_UDERDRIVE_TIMEOUT_VALUE  1000U
-#define PWR_BKPREG_TIMEOUT_VALUE     1000U
-#define PWR_VOSRDY_TIMEOUT_VALUE     1000U
-/**
-  * @}
-  */
-
-   
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
-  *  @{
-  */
-
-/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions 
-  *  @brief Peripheral Extended features functions 
-  *
-@verbatim   
-
- ===============================================================================
-                 ##### Peripheral extended features functions #####
- ===============================================================================
-
-    *** Main and Backup Regulators configuration ***
-    ================================================
-    [..] 
-      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from 
-          the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is 
-          retained even in Standby or VBAT mode when the low power backup regulator
-          is enabled. It can be considered as an internal EEPROM when VBAT is 
-          always present. You can use the HAL_PWREx_EnableBkUpReg() function to 
-          enable the low power backup regulator. 
-
-      (+) When the backup domain is supplied by VDD (analog switch connected to VDD) 
-          the backup SRAM is powered from VDD which replaces the VBAT power supply to 
-          save battery life.
-
-      (+) The backup SRAM is not mass erased by a tamper event. It is read 
-          protected to prevent confidential data, such as cryptographic private 
-          key, from being accessed. The backup SRAM can be erased only through 
-          the Flash interface when a protection level change from level 1 to 
-          level 0 is requested. 
-      -@- Refer to the description of Read protection (RDP) in the Flash 
-          programming manual.
-
-      (+) The main internal regulator can be configured to have a tradeoff between 
-          performance and power consumption when the device does not operate at 
-          the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() 
-          macro which configure VOS bit in PWR_CR register
-          
-        Refer to the product datasheets for more details.
-
-    *** FLASH Power Down configuration ****
-    =======================================
-    [..] 
-      (+) By setting the FPDS bit in the PWR_CR register by using the 
-          HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power 
-          down mode when the device enters Stop mode. When the Flash memory 
-          is in power down mode, an additional startup delay is incurred when 
-          waking up from Stop mode.
-          
-           (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL 
-           is OFF and the HSI or HSE clock source is selected as system clock. 
-           The new value programmed is active only when the PLL is ON.
-           When the PLL is OFF, the voltage scale 3 is automatically selected. 
-        Refer to the datasheets for more details.
-
-    *** Over-Drive and Under-Drive configuration ****
-    =================================================
-    [..]         
-       (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has
-           2 operating modes available:
-        (++) Normal mode: The CPU and core logic operate at maximum frequency at a given 
-             voltage scaling (scale 1, scale 2 or scale 3)
-        (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a 
-            higher frequency than the normal mode for a given voltage scaling (scale 1,  
-            scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
-            disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow 
-            the sequence described in Reference manual.
-             
-       (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator 
-           supplies a low power voltage to the 1.2V domain, thus preserving the content of registers 
-           and internal SRAM. 2 operating modes are available:
-         (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only 
-              available when the main regulator or the low power regulator is used in Scale 3 or 
-              low voltage mode.
-         (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
-              available when the main regulator or the low power regulator is in low voltage mode.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Enables the Backup Regulator.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
-{
-  uint32_t tickstart = 0U;
-
-  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait till Backup regulator ready flag is set */  
-  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    } 
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief Disables the Backup Regulator.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
-{
-  uint32_t tickstart = 0U;
-
-  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait till Backup regulator ready flag is set */  
-  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    } 
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief Enables the Flash Power Down in Stop mode.
-  * @retval None
-  */
-void HAL_PWREx_EnableFlashPowerDown(void)
-{
-  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief Disables the Flash Power Down in Stop mode.
-  * @retval None
-  */
-void HAL_PWREx_DisableFlashPowerDown(void)
-{
-  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief Return Voltage Scaling Range.
-  * @retval The configured scale for the regulator voltage(VOS bit field).
-  *         The returned value can be one of the following:
-  *            - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
-  *            - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
-  *            - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
-  */  
-uint32_t HAL_PWREx_GetVoltageRange(void)
-{
-  return (PWR->CR & PWR_CR_VOS);
-}
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
-/**
-  * @brief Configures the main internal regulator output voltage.
-  * @param  VoltageScaling specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
-  *                                               the maximum value of fHCLK = 168 MHz.
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
-  *                                               the maximum value of fHCLK = 144 MHz.
-  * @note  When moving from Range 1 to Range 2, the system frequency must be decreased to
-  *        a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API.
-  *        When moving from Range 2 to Range 1, the system frequency can be increased to
-  *        a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API.
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
-{
-  uint32_t tickstart = 0U;
-  
-  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
-  
-  /* Enable PWR RCC Clock Peripheral */
-  __HAL_RCC_PWR_CLK_ENABLE();
-  
-  /* Set Range */
-  __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
-  
-  /* Get Start Tick*/
-  tickstart = HAL_GetTick();
-  while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
-  {
-    if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    } 
-  }
-
-  return HAL_OK;
-}
-
-#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
-      defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
-      defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \
-      defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
-      defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-/**
-  * @brief Configures the main internal regulator output voltage.
-  * @param  VoltageScaling specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
-  *                                               the maximum value of fHCLK is 168 MHz. It can be extended to
-  *                                               180 MHz by activating the over-drive mode.
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
-  *                                               the maximum value of fHCLK is 144 MHz. It can be extended to,                
-  *                                               168 MHz by activating the over-drive mode.
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode,
-  *                                               the maximum value of fHCLK is 120 MHz.
-  * @note To update the system clock frequency(SYSCLK):
-  *        - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
-  *        - Call the HAL_RCC_OscConfig() to configure the PLL.
-  *        - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
-  *        - Set the new system clock frequency using the HAL_RCC_ClockConfig().
-  * @note The scale can be modified only when the HSI or HSE clock source is selected 
-  *        as system clock source, otherwise the API returns HAL_ERROR.  
-  * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
-  *       value in the PWR_CR1 register are not taken in account.
-  * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
-  * @note The new voltage scale is active only when the PLL is ON.  
-  * @retval HAL Status
-  */
-HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
-{
-  uint32_t tickstart = 0U;
-  
-  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
-  
-  /* Enable PWR RCC Clock Peripheral */
-  __HAL_RCC_PWR_CLK_ENABLE();
-  
-  /* Check if the PLL is used as system clock or not */
-  if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
-  {
-    /* Disable the main PLL */
-    __HAL_RCC_PLL_DISABLE();
-    
-    /* Get Start Tick */
-    tickstart = HAL_GetTick();    
-    /* Wait till PLL is disabled */  
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /* Set Range */
-    __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
-    
-    /* Enable the main PLL */
-    __HAL_RCC_PLL_ENABLE();
-    
-    /* Get Start Tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLL is ready */  
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      } 
-    }
-    
-    /* Get Start Tick */
-    tickstart = HAL_GetTick();
-    while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
-    {
-      if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      } 
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  return HAL_OK;
-}
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
-    defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
-    defined(STM32F413xx) || defined(STM32F423xx)
-/**
-  * @brief Enables Main Regulator low voltage mode.
-  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
-  *        STM32F413xx/STM32F423xx devices.   
-  * @retval None
-  */
-void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
-{
-  *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief Disables Main Regulator low voltage mode.
-  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
-  *        STM32F413xx/STM32F423xxdevices. 
-  * @retval None
-  */
-void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
-{
-  *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief Enables Low Power Regulator low voltage mode.
-  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
-  *        STM32F413xx/STM32F423xx devices.   
-  * @retval None
-  */
-void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
-{
-  *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief Disables Low Power Regulator low voltage mode.
-  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
-  *        STM32F413xx/STM32F423xx  devices.   
-  * @retval None
-  */
-void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
-{
-  *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
-}
-
-#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx ||
-          STM32F413xx || STM32F423xx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-/**
-  * @brief  Activates the Over-Drive mode.
-  * @note   This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
-  *         This mode allows the CPU and the core logic to operate at a higher frequency
-  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).   
-  * @note   It is recommended to enter or exit Over-drive mode when the application is not running 
-  *         critical tasks and when the system clock source is either HSI or HSE. 
-  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   
-  *         The peripheral clocks must be enabled once the Over-drive mode is activated.   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
-{
-  uint32_t tickstart = 0U;
-
-  __HAL_RCC_PWR_CLK_ENABLE();
-  
-  /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
-  __HAL_PWR_OVERDRIVE_ENABLE();
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
-  {
-    if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  
-  /* Enable the Over-drive switch */
-  __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
-  {
-    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  } 
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates the Over-Drive mode.
-  * @note   This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
-  *         This mode allows the CPU and the core logic to operate at a higher frequency
-  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).    
-  * @note   It is recommended to enter or exit Over-drive mode when the application is not running 
-  *         critical tasks and when the system clock source is either HSI or HSE. 
-  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   
-  *         The peripheral clocks must be enabled once the Over-drive mode is activated.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
-{
-  uint32_t tickstart = 0U;
-  
-  __HAL_RCC_PWR_CLK_ENABLE();
-    
-  /* Disable the Over-drive switch */
-  __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
- 
-  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
-  {
-    if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  } 
-  
-  /* Disable the Over-drive */
-  __HAL_PWR_OVERDRIVE_DISABLE();
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
-  {
-    if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enters in Under-Drive STOP mode.
-  *  
-  * @note   This mode is only available for STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx devices.
-  * 
-  * @note    This mode can be selected only when the Under-Drive is already active 
-  *   
-  * @note    This mode is enabled only with STOP low power mode.
-  *          In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
-  *          mode is only available when the main regulator or the low power regulator 
-  *          is in low voltage mode
-  *        
-  * @note   If the Under-drive mode was enabled, it is automatically disabled after 
-  *         exiting Stop mode. 
-  *         When the voltage regulator operates in Under-drive mode, an additional  
-  *         startup delay is induced when waking up from Stop mode.
-  *                    
-  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
-  *   
-  * @note   When exiting Stop mode by issuing an interrupt or a wake-up event, 
-  *         the HSI RC oscillator is selected as system clock.
-  *           
-  * @note   When the voltage regulator operates in low power mode, an additional 
-  *         startup delay is incurred when waking up from Stop mode. 
-  *         By keeping the internal regulator ON during Stop mode, the consumption 
-  *         is higher although the startup time is reduced.
-  *     
-  * @param  Regulator specifies the regulator state in STOP mode.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_MAINREGULATOR_UNDERDRIVE_ON:  Main Regulator in under-drive mode 
-  *                 and Flash memory in power-down when the device is in Stop under-drive mode
-  *            @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON:  Low Power Regulator in under-drive mode 
-  *                and Flash memory in power-down when the device is in Stop under-drive mode
-  * @param  STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
-  *            @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
-{
-  uint32_t tmpreg1 = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
-  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-  
-  /* Enable Power ctrl clock */
-  __HAL_RCC_PWR_CLK_ENABLE();
-  /* Enable the Under-drive Mode ---------------------------------------------*/
-  /* Clear Under-drive flag */
-  __HAL_PWR_CLEAR_ODRUDR_FLAG();
-  
-  /* Enable the Under-drive */ 
-  __HAL_PWR_UNDERDRIVE_ENABLE();
-
-  /* Select the regulator state in STOP mode ---------------------------------*/
-  tmpreg1 = PWR->CR;
-  /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
-  tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
-  
-  /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
-  tmpreg1 |= Regulator;
-  
-  /* Store the new value */
-  PWR->CR = tmpreg1;
-  
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-  
-  /* Select STOP mode entry --------------------------------------------------*/
-  if(STOPEntry == PWR_SLEEPENTRY_WFI)
-  {   
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __WFE();
-  }
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */
-  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-
-  return HAL_OK;  
-}
-
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_pwr_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended PWR HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of PWR extension peripheral:           
+  *           + Peripheral Extended features functions
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWREx PWREx
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup PWREx_Private_Constants
+  * @{
+  */    
+#define PWR_OVERDRIVE_TIMEOUT_VALUE  1000U
+#define PWR_UDERDRIVE_TIMEOUT_VALUE  1000U
+#define PWR_BKPREG_TIMEOUT_VALUE     1000U
+#define PWR_VOSRDY_TIMEOUT_VALUE     1000U
+/**
+  * @}
+  */
+
+   
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
+  *  @{
+  */
+
+/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions 
+  *  @brief Peripheral Extended features functions 
+  *
+@verbatim   
+
+ ===============================================================================
+                 ##### Peripheral extended features functions #####
+ ===============================================================================
+
+    *** Main and Backup Regulators configuration ***
+    ================================================
+    [..] 
+      (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from 
+          the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is 
+          retained even in Standby or VBAT mode when the low power backup regulator
+          is enabled. It can be considered as an internal EEPROM when VBAT is 
+          always present. You can use the HAL_PWREx_EnableBkUpReg() function to 
+          enable the low power backup regulator. 
+
+      (+) When the backup domain is supplied by VDD (analog switch connected to VDD) 
+          the backup SRAM is powered from VDD which replaces the VBAT power supply to 
+          save battery life.
+
+      (+) The backup SRAM is not mass erased by a tamper event. It is read 
+          protected to prevent confidential data, such as cryptographic private 
+          key, from being accessed. The backup SRAM can be erased only through 
+          the Flash interface when a protection level change from level 1 to 
+          level 0 is requested. 
+      -@- Refer to the description of Read protection (RDP) in the Flash 
+          programming manual.
+
+      (+) The main internal regulator can be configured to have a tradeoff between 
+          performance and power consumption when the device does not operate at 
+          the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() 
+          macro which configure VOS bit in PWR_CR register
+          
+        Refer to the product datasheets for more details.
+
+    *** FLASH Power Down configuration ****
+    =======================================
+    [..] 
+      (+) By setting the FPDS bit in the PWR_CR register by using the 
+          HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power 
+          down mode when the device enters Stop mode. When the Flash memory 
+          is in power down mode, an additional startup delay is incurred when 
+          waking up from Stop mode.
+          
+           (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL 
+           is OFF and the HSI or HSE clock source is selected as system clock. 
+           The new value programmed is active only when the PLL is ON.
+           When the PLL is OFF, the voltage scale 3 is automatically selected. 
+        Refer to the datasheets for more details.
+
+    *** Over-Drive and Under-Drive configuration ****
+    =================================================
+    [..]         
+       (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has
+           2 operating modes available:
+        (++) Normal mode: The CPU and core logic operate at maximum frequency at a given 
+             voltage scaling (scale 1, scale 2 or scale 3)
+        (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a 
+            higher frequency than the normal mode for a given voltage scaling (scale 1,  
+            scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and
+            disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow 
+            the sequence described in Reference manual.
+             
+       (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator 
+           supplies a low power voltage to the 1.2V domain, thus preserving the content of registers 
+           and internal SRAM. 2 operating modes are available:
+         (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only 
+              available when the main regulator or the low power regulator is used in Scale 3 or 
+              low voltage mode.
+         (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only
+              available when the main regulator or the low power regulator is in low voltage mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Enables the Backup Regulator.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
+{
+  uint32_t tickstart = 0U;
+
+  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE;
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait till Backup regulator ready flag is set */  
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    } 
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief Disables the Backup Regulator.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
+{
+  uint32_t tickstart = 0U;
+
+  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE;
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Wait till Backup regulator ready flag is set */  
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    } 
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief Enables the Flash Power Down in Stop mode.
+  * @retval None
+  */
+void HAL_PWREx_EnableFlashPowerDown(void)
+{
+  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief Disables the Flash Power Down in Stop mode.
+  * @retval None
+  */
+void HAL_PWREx_DisableFlashPowerDown(void)
+{
+  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE;
+}
+
+/**
+  * @brief Return Voltage Scaling Range.
+  * @retval The configured scale for the regulator voltage(VOS bit field).
+  *         The returned value can be one of the following:
+  *            - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
+  *            - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
+  *            - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
+  */  
+uint32_t HAL_PWREx_GetVoltageRange(void)
+{
+  return (PWR->CR & PWR_CR_VOS);
+}
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+/**
+  * @brief Configures the main internal regulator output voltage.
+  * @param  VoltageScaling specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
+  *                                               the maximum value of fHCLK = 168 MHz.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
+  *                                               the maximum value of fHCLK = 144 MHz.
+  * @note  When moving from Range 1 to Range 2, the system frequency must be decreased to
+  *        a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API.
+  *        When moving from Range 2 to Range 1, the system frequency can be increased to
+  *        a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+{
+  uint32_t tickstart = 0U;
+  
+  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
+  
+  /* Enable PWR RCC Clock Peripheral */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  
+  /* Set Range */
+  __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
+  
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+  while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
+  {
+    if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    } 
+  }
+
+  return HAL_OK;
+}
+
+#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
+      defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
+      defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \
+      defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
+      defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+  * @brief Configures the main internal regulator output voltage.
+  * @param  VoltageScaling specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
+  *                                               the maximum value of fHCLK is 168 MHz. It can be extended to
+  *                                               180 MHz by activating the over-drive mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode,
+  *                                               the maximum value of fHCLK is 144 MHz. It can be extended to,                
+  *                                               168 MHz by activating the over-drive mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode,
+  *                                               the maximum value of fHCLK is 120 MHz.
+  * @note To update the system clock frequency(SYSCLK):
+  *        - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig().
+  *        - Call the HAL_RCC_OscConfig() to configure the PLL.
+  *        - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale.
+  *        - Set the new system clock frequency using the HAL_RCC_ClockConfig().
+  * @note The scale can be modified only when the HSI or HSE clock source is selected 
+  *        as system clock source, otherwise the API returns HAL_ERROR.  
+  * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits
+  *       value in the PWR_CR1 register are not taken in account.
+  * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2.
+  * @note The new voltage scale is active only when the PLL is ON.  
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
+{
+  uint32_t tickstart = 0U;
+  
+  assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
+  
+  /* Enable PWR RCC Clock Peripheral */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  
+  /* Check if the PLL is used as system clock or not */
+  if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+  {
+    /* Disable the main PLL */
+    __HAL_RCC_PLL_DISABLE();
+    
+    /* Get Start Tick */
+    tickstart = HAL_GetTick();    
+    /* Wait till PLL is disabled */  
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    
+    /* Set Range */
+    __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling);
+    
+    /* Enable the main PLL */
+    __HAL_RCC_PLL_ENABLE();
+    
+    /* Get Start Tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLL is ready */  
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      } 
+    }
+    
+    /* Get Start Tick */
+    tickstart = HAL_GetTick();
+    while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET))
+    {
+      if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      } 
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+
+  return HAL_OK;
+}
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\
+    defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+    defined(STM32F413xx) || defined(STM32F423xx)
+/**
+  * @brief Enables Main Regulator low voltage mode.
+  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
+  *        STM32F413xx/STM32F423xx devices.   
+  * @retval None
+  */
+void HAL_PWREx_EnableMainRegulatorLowVoltage(void)
+{
+  *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief Disables Main Regulator low voltage mode.
+  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
+  *        STM32F413xx/STM32F423xxdevices. 
+  * @retval None
+  */
+void HAL_PWREx_DisableMainRegulatorLowVoltage(void)
+{
+  *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE;
+}
+
+/**
+  * @brief Enables Low Power Regulator low voltage mode.
+  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
+  *        STM32F413xx/STM32F423xx devices.   
+  * @retval None
+  */
+void HAL_PWREx_EnableLowRegulatorLowVoltage(void)
+{
+  *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief Disables Low Power Regulator low voltage mode.
+  * @note  This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/
+  *        STM32F413xx/STM32F423xx  devices.   
+  * @retval None
+  */
+void HAL_PWREx_DisableLowRegulatorLowVoltage(void)
+{
+  *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE;
+}
+
+#endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx ||
+          STM32F413xx || STM32F423xx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+    defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+/**
+  * @brief  Activates the Over-Drive mode.
+  * @note   This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
+  *         This mode allows the CPU and the core logic to operate at a higher frequency
+  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).   
+  * @note   It is recommended to enter or exit Over-drive mode when the application is not running 
+  *         critical tasks and when the system clock source is either HSI or HSE. 
+  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   
+  *         The peripheral clocks must be enabled once the Over-drive mode is activated.   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
+{
+  uint32_t tickstart = 0U;
+
+  __HAL_RCC_PWR_CLK_ENABLE();
+  
+  /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
+  __HAL_PWR_OVERDRIVE_ENABLE();
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
+  {
+    if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  /* Enable the Over-drive switch */
+  __HAL_PWR_OVERDRIVESWITCHING_ENABLE();
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
+  {
+    if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  } 
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deactivates the Over-Drive mode.
+  * @note   This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices.
+  *         This mode allows the CPU and the core logic to operate at a higher frequency
+  *         than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3).    
+  * @note   It is recommended to enter or exit Over-drive mode when the application is not running 
+  *         critical tasks and when the system clock source is either HSI or HSE. 
+  *         During the Over-drive switch activation, no peripheral clocks should be enabled.   
+  *         The peripheral clocks must be enabled once the Over-drive mode is activated.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void)
+{
+  uint32_t tickstart = 0U;
+  
+  __HAL_RCC_PWR_CLK_ENABLE();
+    
+  /* Disable the Over-drive switch */
+  __HAL_PWR_OVERDRIVESWITCHING_DISABLE();
+  
+  /* Get tick */
+  tickstart = HAL_GetTick();
+ 
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
+  {
+    if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  } 
+  
+  /* Disable the Over-drive */
+  __HAL_PWR_OVERDRIVE_DISABLE();
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
+  {
+    if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enters in Under-Drive STOP mode.
+  *  
+  * @note   This mode is only available for STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx devices.
+  * 
+  * @note    This mode can be selected only when the Under-Drive is already active 
+  *   
+  * @note    This mode is enabled only with STOP low power mode.
+  *          In this mode, the 1.2V domain is preserved in reduced leakage mode. This 
+  *          mode is only available when the main regulator or the low power regulator 
+  *          is in low voltage mode
+  *        
+  * @note   If the Under-drive mode was enabled, it is automatically disabled after 
+  *         exiting Stop mode. 
+  *         When the voltage regulator operates in Under-drive mode, an additional  
+  *         startup delay is induced when waking up from Stop mode.
+  *                    
+  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
+  *   
+  * @note   When exiting Stop mode by issuing an interrupt or a wake-up event, 
+  *         the HSI RC oscillator is selected as system clock.
+  *           
+  * @note   When the voltage regulator operates in low power mode, an additional 
+  *         startup delay is incurred when waking up from Stop mode. 
+  *         By keeping the internal regulator ON during Stop mode, the consumption 
+  *         is higher although the startup time is reduced.
+  *     
+  * @param  Regulator specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_MAINREGULATOR_UNDERDRIVE_ON:  Main Regulator in under-drive mode 
+  *                 and Flash memory in power-down when the device is in Stop under-drive mode
+  *            @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON:  Low Power Regulator in under-drive mode 
+  *                and Flash memory in power-down when the device is in Stop under-drive mode
+  * @param  STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
+  *            @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+  uint32_t tmpreg1 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
+  
+  /* Enable Power ctrl clock */
+  __HAL_RCC_PWR_CLK_ENABLE();
+  /* Enable the Under-drive Mode ---------------------------------------------*/
+  /* Clear Under-drive flag */
+  __HAL_PWR_CLEAR_ODRUDR_FLAG();
+  
+  /* Enable the Under-drive */ 
+  __HAL_PWR_UNDERDRIVE_ENABLE();
+
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tmpreg1 = PWR->CR;
+  /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */
+  tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS);
+  
+  /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */
+  tmpreg1 |= Regulator;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg1;
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+  
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(STOPEntry == PWR_SLEEPENTRY_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE();
+  }
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
+
+  return HAL_OK;  
+}
+
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c
index f187348..79364b6 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.c
@@ -1,1122 +1,1122 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_rcc.c
-  * @author  MCD Application Team
-  * @brief   RCC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Reset and Clock Control (RCC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
-  *
-  @verbatim
-  ==============================================================================
-                      ##### RCC specific features #####
-  ==============================================================================
-    [..]
-      After reset the device is running from Internal High Speed oscillator
-      (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
-      and I-Cache are disabled, and all peripherals are off except internal
-      SRAM, Flash and JTAG.
-      (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
-          all peripherals mapped on these busses are running at HSI speed.
-      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
-      (+) All GPIOs are in input floating state, except the JTAG pins which
-          are assigned to be used for debug purpose.
-
-    [..]
-      Once the device started from reset, the user application has to:
-      (+) Configure the clock source to be used to drive the System clock
-          (if the application needs higher frequency/performance)
-      (+) Configure the System clock frequency and Flash settings
-      (+) Configure the AHB and APB busses prescalers
-      (+) Enable the clock for the peripheral(s) to be used
-      (+) Configure the clock source(s) for peripherals which clocks are not
-          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
-
-                      ##### RCC Limitations #####
-  ==============================================================================
-    [..]
-      A delay between an RCC peripheral clock enable and the effective peripheral
-      enabling should be taken into account in order to manage the peripheral read/write
-      from/to registers.
-      (+) This delay depends on the peripheral mapping.
-      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
-          after the clock enable bit is set on the hardware register
-      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
-          after the clock enable bit is set on the hardware register
-
-    [..]
-      Implemented Workaround:
-      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
-          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RCC RCC
-  * @brief RCC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup RCC_Private_Constants
-  * @{
-  */
-
-/* Private macro -------------------------------------------------------------*/
-#define __MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
-#define MCO1_GPIO_PORT        GPIOA
-#define MCO1_PIN              GPIO_PIN_8
-
-#define __MCO2_CLK_ENABLE()   __HAL_RCC_GPIOC_CLK_ENABLE()
-#define MCO2_GPIO_PORT         GPIOC
-#define MCO2_PIN               GPIO_PIN_9
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Variables RCC Private Variables
-  * @{
-  */
-/**
-  * @}
-  */
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Functions RCC Exported Functions
-  *  @{
-  */
-
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-           ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]
-      This section provides functions allowing to configure the internal/external oscillators
-      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
-       and APB2).
-
-    [..] Internal/external clock and PLL configuration
-         (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
-             the PLL as System clock source.
-
-         (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
-             clock source.
-
-         (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
-             through the PLL as System clock source. Can be used also as RTC clock source.
-
-         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
-
-         (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
-           (++) The first output is used to generate the high speed system clock (up to 168 MHz)
-           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
-                the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
-
-         (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
-             and if a HSE clock failure occurs(HSE used directly or through PLL as System
-             clock source), the System clocks automatically switched to HSI and an interrupt
-             is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
-             (Non-Maskable Interrupt) exception vector.
-
-         (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
-             clock (through a configurable prescaler) on PA8 pin.
-
-         (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
-             clock (through a configurable prescaler) on PC9 pin.
-
-    [..] System, AHB and APB busses clocks configuration
-         (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
-             HSE and PLL.
-             The AHB clock (HCLK) is derived from System clock through configurable
-             prescaler and used to clock the CPU, memory and peripherals mapped
-             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
-             from AHB clock through configurable prescalers and used to clock
-             the peripherals mapped on these busses. You can use
-             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
-
-         (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
-             frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
-             Depending on the device voltage range, the maximum frequency should
-             be adapted accordingly (refer to the product datasheets for more details).
-
-         (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices,
-             the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
-             Depending on the device voltage range, the maximum frequency should
-             be adapted accordingly (refer to the product datasheets for more details).
-
-         (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
-             PCLK2 84 MHz and PCLK1 42 MHz.
-             Depending on the device voltage range, the maximum frequency should
-             be adapted accordingly (refer to the product datasheets for more details).
-
-         (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
-             PCLK2 100 MHz and PCLK1 50 MHz.
-             Depending on the device voltage range, the maximum frequency should
-             be adapted accordingly (refer to the product datasheets for more details).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Resets the RCC clock configuration to the default reset state.
-  * @note   The default reset state of the clock configuration is given below:
-  *            - HSI ON and used as system clock source
-  *            - HSE and PLL OFF
-  *            - AHB, APB1 and APB2 prescaler set to 1.
-  *            - CSS, MCO1 and MCO2 OFF
-  *            - All interrupts disabled
-  * @note   This function doesn't modify the configuration of the
-  *            - Peripheral clocks
-  *            - LSI, LSE and RTC clocks
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_RCC_DeInit(void)
-{
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
-  *         RCC_OscInitTypeDef.
-  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
-  *         contains the configuration information for the RCC Oscillators.
-  * @note   The PLL is not disabled when used as system clock.
-  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
-  *         supported by this API. User should request a transition to LSE Off
-  *         first and then LSE On or LSE Bypass.
-  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
-  *         supported by this API. User should request a transition to HSE Off
-  *         first and then HSE On or HSE Bypass.
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-  uint32_t tickstart, pll_config;
-
-  /* Check Null pointer */
-  if(RCC_OscInitStruct == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-  /*------------------------------- HSE Configuration ------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
-    {
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
-      {
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Set the new HSE configuration ---------------------------------------*/
-      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-
-      /* Check the HSE State */
-      if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
-      {
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else
-      {
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSE is bypassed or disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*----------------------------- HSI Configuration --------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
-    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
-    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
-    {
-      /* When HSI is used as system clock it will not disabled */
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
-      {
-        return HAL_ERROR;
-      }
-      /* Otherwise, just the calibration is allowed */
-      else
-      {
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-    }
-    else
-    {
-      /* Check the HSI State */
-      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
-      {
-        /* Enable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_ENABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-      else
-      {
-        /* Disable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_DISABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*------------------------------ LSI Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
-    /* Check the LSI State */
-    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
-    {
-      /* Enable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_ENABLE();
-
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSI is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      /* Disable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_DISABLE();
-
-      /* Get Start Tick */
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSI is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  /*------------------------------ LSE Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
-  {
-    FlagStatus       pwrclkchanged = RESET;
-
-    /* Check the parameters */
-    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
-    /* Update LSE configuration in Backup Domain control register    */
-    /* Requires to enable write access to Backup Domain of necessary */
-    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
-    {
-      __HAL_RCC_PWR_CLK_ENABLE();
-      pwrclkchanged = SET;
-    }
-
-    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
-    {
-      /* Enable write access to Backup domain */
-      SET_BIT(PWR->CR, PWR_CR_DBP);
-
-      /* Wait for Backup domain Write protection disable */
-      tickstart = HAL_GetTick();
-
-      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
-      {
-        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Set the new LSE configuration -----------------------------------------*/
-    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
-    /* Check the LSE State */
-    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSE is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      /* Get Start Tick */
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSE is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Restore clock configuration if changed */
-    if(pwrclkchanged == SET)
-    {
-      __HAL_RCC_PWR_CLK_DISABLE();
-    }
-  }
-  /*-------------------------------- PLL Configuration -----------------------*/
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
-  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
-  {
-    /* Check if the PLL is used as system clock or not */
-    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
-    {
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
-      {
-        /* Check the parameters */
-        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
-        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
-        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
-        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
-        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
-
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-
-        /* Configure the main PLL clock source, multiplication and division factors. */
-        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \
-                                 RCC_OscInitStruct->PLL.PLLM                                                 | \
-                                 (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)             | \
-                                 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
-                                 (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
-        /* Enable the main PLL. */
-        __HAL_RCC_PLL_ENABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else
-      {
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
-
-        /* Get Start Tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    else
-    {
-      /* Check if there is a request to disable the PLL used as System clock source */
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Do not return HAL_ERROR if request repeats the current configuration */
-        pll_config = RCC->PLLCFGR;
-#if defined (RCC_PLLCFGR_PLLR)
-        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
-#else
-        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
-#endif
-        {
-          return HAL_ERROR;
-        }
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CPU, AHB and APB busses clocks according to the specified
-  *         parameters in the RCC_ClkInitStruct.
-  * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
-  *         contains the configuration information for the RCC peripheral.
-  * @param  FLatency FLASH Latency, this parameter depend on device selected
-  *
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
-  *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
-  *
-  * @note   The HSI is used (enabled by hardware) as system clock source after
-  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
-  *         of failure of the HSE used directly or indirectly as system clock
-  *         (if the Clock Security System CSS is enabled).
-  *
-  * @note   A switch from one clock source to another occurs only if the target
-  *         clock source is ready (clock stable after startup delay or PLL locked).
-  *         If a clock source which is not yet ready is selected, the switch will
-  *         occur when the clock source will be ready.
-  *
-  * @note   Depending on the device voltage range, the software has to set correctly
-  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
-  *         (for more details refer to section above "Initialization/de-initialization functions")
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
-{
-  uint32_t tickstart;
-
-  /* Check Null pointer */
-  if(RCC_ClkInitStruct == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
-  assert_param(IS_FLASH_LATENCY(FLatency));
-
-  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
-    must be correctly programmed according to the frequency of the CPU clock
-    (HCLK) and the supply voltage of the device. */
-
-  /* Increasing the number of wait states because of higher CPU frequency */
-  if(FLatency > __HAL_FLASH_GET_LATENCY())
-  {
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if(__HAL_FLASH_GET_LATENCY() != FLatency)
-    {
-      return HAL_ERROR;
-    }
-  }
-
-  /*-------------------------- HCLK Configuration --------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
-  {
-    /* Set the highest APBx dividers in order to ensure that we do not go through
-       a non-spec phase whatever we decrease or increase HCLK. */
-    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
-    {
-      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
-    }
-
-    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
-    {
-      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
-    }
-
-    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
-  }
-
-  /*------------------------- SYSCLK Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
-  {
-    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
-    /* HSE is selected as System Clock Source */
-    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-    {
-      /* Check the HSE ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
-      {
-        return HAL_ERROR;
-      }
-    }
-    /* PLL is selected as System Clock Source */
-    else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
-            (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
-    {
-      /* Check the PLL ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
-      {
-        return HAL_ERROR;
-      }
-    }
-    /* HSI is selected as System Clock Source */
-    else
-    {
-      /* Check the HSI ready flag */
-      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
-      {
-        return HAL_ERROR;
-      }
-    }
-
-    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
-
-    /* Get Start Tick */
-    tickstart = HAL_GetTick();
-
-    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
-    {
-      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Decreasing the number of wait states because of lower CPU frequency */
-  if(FLatency < __HAL_FLASH_GET_LATENCY())
-  {
-     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if(__HAL_FLASH_GET_LATENCY() != FLatency)
-    {
-      return HAL_ERROR;
-    }
-  }
-
-  /*-------------------------- PCLK1 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
-  }
-
-  /*-------------------------- PCLK2 Configuration ---------------------------*/
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
-  }
-
-  /* Update the SystemCoreClock global variable */
-  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
-
-  /* Configure the source of time base considering new system clocks settings */
-  HAL_InitTick (uwTickPrio);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
- *  @brief   RCC clocks control functions
- *
-@verbatim
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the RCC Clocks
-    frequencies.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
-  * @note   PA8/PC9 should be configured in alternate function mode.
-  * @param  RCC_MCOx specifies the output direction for the clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
-  *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
-  * @param  RCC_MCOSource specifies the clock source to output.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
-  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
-  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
-  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
-  *            @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
-  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
-  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
-  * @param  RCC_MCODiv specifies the MCOx prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
-  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
-  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
-  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
-  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
-  * @note  For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
-  *        at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
-  * @retval None
-  */
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
-{
-  GPIO_InitTypeDef GPIO_InitStruct;
-  /* Check the parameters */
-  assert_param(IS_RCC_MCO(RCC_MCOx));
-  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
-  /* RCC_MCO1 */
-  if(RCC_MCOx == RCC_MCO1)
-  {
-    assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-
-    /* MCO1 Clock Enable */
-    __MCO1_CLK_ENABLE();
-
-    /* Configure the MCO1 pin in alternate function mode */
-    GPIO_InitStruct.Pin = MCO1_PIN;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
-    HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
-
-    /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
-    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
-
-   /* This RCC MCO1 enable feature is available only on STM32F410xx devices */
-#if defined(RCC_CFGR_MCO1EN)
-    __HAL_RCC_MCO1_ENABLE();
-#endif /* RCC_CFGR_MCO1EN */
-  }
-#if defined(RCC_CFGR_MCO2)
-  else
-  {
-    assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
-
-    /* MCO2 Clock Enable */
-    __MCO2_CLK_ENABLE();
-
-    /* Configure the MCO2 pin in alternate function mode */
-    GPIO_InitStruct.Pin = MCO2_PIN;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
-    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
-    HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
-
-    /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
-    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));
-
-   /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
-#if defined(RCC_CFGR_MCO2EN)
-    __HAL_RCC_MCO2_ENABLE();
-#endif /* RCC_CFGR_MCO2EN */
-  }
-#endif /* RCC_CFGR_MCO2 */
-}
-
-/**
-  * @brief  Enables the Clock Security System.
-  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
-  *         is automatically disabled and an interrupt is generated to inform the
-  *         software about the failure (Clock Security System Interrupt, CSSI),
-  *         allowing the MCU to perform rescue operations. The CSSI is linked to
-  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
-  * @retval None
-  */
-void HAL_RCC_EnableCSS(void)
-{
-  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disables the Clock Security System.
-  * @retval None
-  */
-void HAL_RCC_DisableCSS(void)
-{
-  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief  Returns the SYSCLK frequency
-  *
-  * @note   The system frequency computed by this function is not the real
-  *         frequency in the chip. It is calculated based on the predefined
-  *         constant and the selected clock source:
-  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
-  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
-  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
-  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  * @note     (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
-  *               16 MHz) but the real value may vary depending on the variations
-  *               in voltage and temperature.
-  * @note     (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
-  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
-  *                frequency of the crystal used. Otherwise, this function may
-  *                have wrong result.
-  *
-  * @note   The result of this function could be not correct when using fractional
-  *         value for HSE crystal.
-  *
-  * @note   This function can be used by the user application to compute the
-  *         baudrate for the communication peripherals or configure other parameters.
-  *
-  * @note   Each time SYSCLK changes, this function must be called to update the
-  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
-  *
-  *
-  * @retval SYSCLK frequency
-  */
-__weak uint32_t HAL_RCC_GetSysClockFreq(void)
-{
-  uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
-  uint32_t sysclockfreq = 0U;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (RCC->CFGR & RCC_CFGR_SWS)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
-    {
-      sysclockfreq = HSI_VALUE;
-       break;
-    }
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
-    {
-      sysclockfreq = HSE_VALUE;
-      break;
-    }
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock  source */
-    {
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
-      SYSCLK = PLL_VCO / PLLP */
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
-      }
-      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
-
-      sysclockfreq = pllvco/pllp;
-      break;
-    }
-    default:
-    {
-      sysclockfreq = HSI_VALUE;
-      break;
-    }
-  }
-  return sysclockfreq;
-}
-
-/**
-  * @brief  Returns the HCLK frequency
-  * @note   Each time HCLK changes, this function must be called to update the
-  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
-  *
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
-  *         and updated within this function
-  * @retval HCLK frequency
-  */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
-  return SystemCoreClock;
-}
-
-/**
-  * @brief  Returns the PCLK1 frequency
-  * @note   Each time PCLK1 changes, this function must be called to update the
-  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
-  * @retval PCLK1 frequency
-  */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
-  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
-}
-
-/**
-  * @brief  Returns the PCLK2 frequency
-  * @note   Each time PCLK2 changes, this function must be called to update the
-  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
-  * @retval PCLK2 frequency
-  */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
-  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
-}
-
-/**
-  * @brief  Configures the RCC_OscInitStruct according to the internal
-  * RCC configuration registers.
-  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
-  * will be configured.
-  * @retval None
-  */
-__weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-  /* Set all possible values for the Oscillator type parameter ---------------*/
-  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-
-  /* Get the HSE configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
-  }
-  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
-  }
-
-  /* Get the HSI configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
-  }
-
-  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
-
-  /* Get the LSE configuration -----------------------------------------------*/
-  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
-  }
-  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
-  }
-
-  /* Get the LSI configuration -----------------------------------------------*/
-  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
-  }
-
-  /* Get the PLL configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
-  }
-  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
-  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
-  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
-  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos);
-  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
-}
-
-/**
-  * @brief  Configures the RCC_ClkInitStruct according to the internal
-  * RCC configuration registers.
-  * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
-  * will be configured.
-  * @param  pFLatency Pointer on the Flash Latency.
-  * @retval None
-  */
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
-{
-  /* Set all possible values for the Clock type parameter --------------------*/
-  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-
-  /* Get the SYSCLK configuration --------------------------------------------*/
-  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-
-  /* Get the HCLK configuration ----------------------------------------------*/
-  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
-
-  /* Get the APB1 configuration ----------------------------------------------*/
-  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
-
-  /* Get the APB2 configuration ----------------------------------------------*/
-  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
-
-  /* Get the Flash Wait State (Latency) configuration ------------------------*/
-  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
-}
-
-/**
-  * @brief This function handles the RCC CSS interrupt request.
-  * @note This API should be called under the NMI_Handler().
-  * @retval None
-  */
-void HAL_RCC_NMI_IRQHandler(void)
-{
-  /* Check RCC CSSF flag  */
-  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
-  {
-    /* RCC Clock Security System interrupt user callback */
-    HAL_RCC_CSSCallback();
-
-    /* Clear RCC CSS pending bit */
-    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
-  }
-}
-
-/**
-  * @brief  RCC Clock Security System interrupt callback
-  * @retval None
-  */
-__weak void HAL_RCC_CSSCallback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RCC_CSSCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rcc.c
+  * @author  MCD Application Team
+  * @brief   RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Reset and Clock Control (RCC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                      ##### RCC specific features #####
+  ==============================================================================
+    [..]
+      After reset the device is running from Internal High Speed oscillator
+      (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
+      and I-Cache are disabled, and all peripherals are off except internal
+      SRAM, Flash and JTAG.
+      (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
+          all peripherals mapped on these busses are running at HSI speed.
+      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
+      (+) All GPIOs are in input floating state, except the JTAG pins which
+          are assigned to be used for debug purpose.
+
+    [..]
+      Once the device started from reset, the user application has to:
+      (+) Configure the clock source to be used to drive the System clock
+          (if the application needs higher frequency/performance)
+      (+) Configure the System clock frequency and Flash settings
+      (+) Configure the AHB and APB busses prescalers
+      (+) Enable the clock for the peripheral(s) to be used
+      (+) Configure the clock source(s) for peripherals which clocks are not
+          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
+
+                      ##### RCC Limitations #####
+  ==============================================================================
+    [..]
+      A delay between an RCC peripheral clock enable and the effective peripheral
+      enabling should be taken into account in order to manage the peripheral read/write
+      from/to registers.
+      (+) This delay depends on the peripheral mapping.
+      (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
+          after the clock enable bit is set on the hardware register
+      (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
+          after the clock enable bit is set on the hardware register
+
+    [..]
+      Implemented Workaround:
+      (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
+          inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCC RCC
+  * @brief RCC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup RCC_Private_Constants
+  * @{
+  */
+
+/* Private macro -------------------------------------------------------------*/
+#define __MCO1_CLK_ENABLE()   __HAL_RCC_GPIOA_CLK_ENABLE()
+#define MCO1_GPIO_PORT        GPIOA
+#define MCO1_PIN              GPIO_PIN_8
+
+#define __MCO2_CLK_ENABLE()   __HAL_RCC_GPIOC_CLK_ENABLE()
+#define MCO2_GPIO_PORT         GPIOC
+#define MCO2_PIN               GPIO_PIN_9
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RCC_Private_Variables RCC Private Variables
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Functions RCC Exported Functions
+  *  @{
+  */
+
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+           ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+      This section provides functions allowing to configure the internal/external oscillators
+      (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
+       and APB2).
+
+    [..] Internal/external clock and PLL configuration
+         (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
+             the PLL as System clock source.
+
+         (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
+             clock source.
+
+         (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
+             through the PLL as System clock source. Can be used also as RTC clock source.
+
+         (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+
+         (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
+           (++) The first output is used to generate the high speed system clock (up to 168 MHz)
+           (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
+                the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
+
+         (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
+             and if a HSE clock failure occurs(HSE used directly or through PLL as System
+             clock source), the System clocks automatically switched to HSI and an interrupt
+             is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
+             (Non-Maskable Interrupt) exception vector.
+
+         (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
+             clock (through a configurable prescaler) on PA8 pin.
+
+         (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
+             clock (through a configurable prescaler) on PC9 pin.
+
+    [..] System, AHB and APB busses clocks configuration
+         (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+             HSE and PLL.
+             The AHB clock (HCLK) is derived from System clock through configurable
+             prescaler and used to clock the CPU, memory and peripherals mapped
+             on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+             from AHB clock through configurable prescalers and used to clock
+             the peripherals mapped on these busses. You can use
+             "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+
+         (#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
+             frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
+             Depending on the device voltage range, the maximum frequency should
+             be adapted accordingly (refer to the product datasheets for more details).
+
+         (#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices,
+             the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
+             Depending on the device voltage range, the maximum frequency should
+             be adapted accordingly (refer to the product datasheets for more details).
+
+         (#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
+             PCLK2 84 MHz and PCLK1 42 MHz.
+             Depending on the device voltage range, the maximum frequency should
+             be adapted accordingly (refer to the product datasheets for more details).
+
+         (#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
+             PCLK2 100 MHz and PCLK1 50 MHz.
+             Depending on the device voltage range, the maximum frequency should
+             be adapted accordingly (refer to the product datasheets for more details).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - HSI ON and used as system clock source
+  *            - HSE and PLL OFF
+  *            - AHB, APB1 and APB2 prescaler set to 1.
+  *            - CSS, MCO1 and MCO2 OFF
+  *            - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks
+  *            - LSI, LSE and RTC clocks
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
+  *         RCC_OscInitTypeDef.
+  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC Oscillators.
+  * @note   The PLL is not disabled when used as system clock.
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+  *         supported by this API. User should request a transition to LSE Off
+  *         first and then LSE On or LSE Bypass.
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this API. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  uint32_t tickstart, pll_config;
+
+  /* Check Null pointer */
+  if(RCC_OscInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+  /*------------------------------- HSE Configuration ------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
+      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+    {
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+      /* Check the HSE State */
+      if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
+      {
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is bypassed or disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*----------------------------- HSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
+      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+    {
+      /* When HSI is used as system clock it will not disabled */
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+    }
+    else
+    {
+      /* Check the HSI State */
+      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+      {
+        /* Enable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*------------------------------ LSI Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+    /* Check the LSI State */
+    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+
+      /* Get Start Tick */
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /*------------------------------ LSE Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+  {
+    FlagStatus       pwrclkchanged = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+    /* Update LSE configuration in Backup Domain control register    */
+    /* Requires to enable write access to Backup Domain of necessary */
+    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+    {
+      __HAL_RCC_PWR_CLK_ENABLE();
+      pwrclkchanged = SET;
+    }
+
+    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+    {
+      /* Enable write access to Backup domain */
+      SET_BIT(PWR->CR, PWR_CR_DBP);
+
+      /* Wait for Backup domain Write protection disable */
+      tickstart = HAL_GetTick();
+
+      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+      {
+        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+    /* Check the LSE State */
+    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Get Start Tick */
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Restore clock configuration if changed */
+    if(pwrclkchanged == SET)
+    {
+      __HAL_RCC_PWR_CLK_DISABLE();
+    }
+  }
+  /*-------------------------------- PLL Configuration -----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+  {
+    /* Check if the PLL is used as system clock or not */
+    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+    {
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+      {
+        /* Check the parameters */
+        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Configure the main PLL clock source, multiplication and division factors. */
+        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \
+                                 RCC_OscInitStruct->PLL.PLLM                                                 | \
+                                 (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)             | \
+                                 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
+                                 (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
+        /* Enable the main PLL. */
+        __HAL_RCC_PLL_ENABLE();
+
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Check if there is a request to disable the PLL used as System clock source */
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Do not return HAL_ERROR if request repeats the current configuration */
+        pll_config = RCC->PLLCFGR;
+#if defined (RCC_PLLCFGR_PLLR)
+        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
+#else
+        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
+#endif
+        {
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the CPU, AHB and APB busses clocks according to the specified
+  *         parameters in the RCC_ClkInitStruct.
+  * @param  RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC peripheral.
+  * @param  FLatency FLASH Latency, this parameter depend on device selected
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+  *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
+  *
+  * @note   The HSI is used (enabled by hardware) as system clock source after
+  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
+  *         of failure of the HSE used directly or indirectly as system clock
+  *         (if the Clock Security System CSS is enabled).
+  *
+  * @note   A switch from one clock source to another occurs only if the target
+  *         clock source is ready (clock stable after startup delay or PLL locked).
+  *         If a clock source which is not yet ready is selected, the switch will
+  *         occur when the clock source will be ready.
+  *
+  * @note   Depending on the device voltage range, the software has to set correctly
+  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
+  *         (for more details refer to section above "Initialization/de-initialization functions")
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
+{
+  uint32_t tickstart;
+
+  /* Check Null pointer */
+  if(RCC_ClkInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
+  assert_param(IS_FLASH_LATENCY(FLatency));
+
+  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+    must be correctly programmed according to the frequency of the CPU clock
+    (HCLK) and the supply voltage of the device. */
+
+  /* Increasing the number of wait states because of higher CPU frequency */
+  if(FLatency > __HAL_FLASH_GET_LATENCY())
+  {
+    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  /*-------------------------- HCLK Configuration --------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+  {
+    /* Set the highest APBx dividers in order to ensure that we do not go through
+       a non-spec phase whatever we decrease or increase HCLK. */
+    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+    {
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
+    }
+
+    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+    {
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
+    }
+
+    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+  }
+
+  /*------------------------- SYSCLK Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+  {
+    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
+
+    /* HSE is selected as System Clock Source */
+    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+    {
+      /* Check the HSE ready flag */
+      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+      {
+        return HAL_ERROR;
+      }
+    }
+    /* PLL is selected as System Clock Source */
+    else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
+            (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
+    {
+      /* Check the PLL ready flag */
+      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+      {
+        return HAL_ERROR;
+      }
+    }
+    /* HSI is selected as System Clock Source */
+    else
+    {
+      /* Check the HSI ready flag */
+      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+      {
+        return HAL_ERROR;
+      }
+    }
+
+    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+
+    /* Get Start Tick */
+    tickstart = HAL_GetTick();
+
+    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+    {
+      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Decreasing the number of wait states because of lower CPU frequency */
+  if(FLatency < __HAL_FLASH_GET_LATENCY())
+  {
+     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
+    __HAL_FLASH_SET_LATENCY(FLatency);
+
+    /* Check that the new number of wait states is taken into account to access the Flash
+    memory by reading the FLASH_ACR register */
+    if(__HAL_FLASH_GET_LATENCY() != FLatency)
+    {
+      return HAL_ERROR;
+    }
+  }
+
+  /*-------------------------- PCLK1 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+  {
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
+  }
+
+  /*-------------------------- PCLK2 Configuration ---------------------------*/
+  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+  {
+    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
+  }
+
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
+
+  /* Configure the source of time base considering new system clocks settings */
+  HAL_InitTick (uwTickPrio);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ *  @brief   RCC clocks control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
+  * @note   PA8/PC9 should be configured in alternate function mode.
+  * @param  RCC_MCOx specifies the output direction for the clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
+  *            @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
+  * @param  RCC_MCOSource specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
+  *            @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
+  * @param  RCC_MCODiv specifies the MCOx prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCODIV_1: no division applied to MCOx clock
+  *            @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
+  *            @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
+  *            @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
+  *            @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
+  * @note  For STM32F410Rx devices to output I2SCLK clock on MCO2 you should have
+  *        at last one of the SPI clocks enabled (SPI1, SPI2 or SPI5).
+  * @retval None
+  */
+void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
+{
+  GPIO_InitTypeDef GPIO_InitStruct;
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO(RCC_MCOx));
+  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
+  /* RCC_MCO1 */
+  if(RCC_MCOx == RCC_MCO1)
+  {
+    assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
+
+    /* MCO1 Clock Enable */
+    __MCO1_CLK_ENABLE();
+
+    /* Configure the MCO1 pin in alternate function mode */
+    GPIO_InitStruct.Pin = MCO1_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
+
+    /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
+
+   /* This RCC MCO1 enable feature is available only on STM32F410xx devices */
+#if defined(RCC_CFGR_MCO1EN)
+    __HAL_RCC_MCO1_ENABLE();
+#endif /* RCC_CFGR_MCO1EN */
+  }
+#if defined(RCC_CFGR_MCO2)
+  else
+  {
+    assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
+
+    /* MCO2 Clock Enable */
+    __MCO2_CLK_ENABLE();
+
+    /* Configure the MCO2 pin in alternate function mode */
+    GPIO_InitStruct.Pin = MCO2_PIN;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
+    HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
+
+    /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));
+
+   /* This RCC MCO2 enable feature is available only on STM32F410Rx devices */
+#if defined(RCC_CFGR_MCO2EN)
+    __HAL_RCC_MCO2_ENABLE();
+#endif /* RCC_CFGR_MCO2EN */
+  }
+#endif /* RCC_CFGR_MCO2 */
+}
+
+/**
+  * @brief  Enables the Clock Security System.
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+  *         is automatically disabled and an interrupt is generated to inform the
+  *         software about the failure (Clock Security System Interrupt, CSSI),
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to
+  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
+  * @retval None
+  */
+void HAL_RCC_EnableCSS(void)
+{
+  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Disables the Clock Security System.
+  * @retval None
+  */
+void HAL_RCC_DisableCSS(void)
+{
+  *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
+}
+
+/**
+  * @brief  Returns the SYSCLK frequency
+  *
+  * @note   The system frequency computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
+  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  * @note     (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *               16 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  *
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *
+  * @note   This function can be used by the user application to compute the
+  *         baudrate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time SYSCLK changes, this function must be called to update the
+  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  *
+  * @retval SYSCLK frequency
+  */
+__weak uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+  uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
+  uint32_t sysclockfreq = 0U;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+    {
+      sysclockfreq = HSI_VALUE;
+       break;
+    }
+    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+    {
+      sysclockfreq = HSE_VALUE;
+      break;
+    }
+    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock  source */
+    {
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+      SYSCLK = PLL_VCO / PLLP */
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+      }
+      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
+
+      sysclockfreq = pllvco/pllp;
+      break;
+    }
+    default:
+    {
+      sysclockfreq = HSI_VALUE;
+      break;
+    }
+  }
+  return sysclockfreq;
+}
+
+/**
+  * @brief  Returns the HCLK frequency
+  * @note   Each time HCLK changes, this function must be called to update the
+  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+  *         and updated within this function
+  * @retval HCLK frequency
+  */
+uint32_t HAL_RCC_GetHCLKFreq(void)
+{
+  return SystemCoreClock;
+}
+
+/**
+  * @brief  Returns the PCLK1 frequency
+  * @note   Each time PCLK1 changes, this function must be called to update the
+  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK1 frequency
+  */
+uint32_t HAL_RCC_GetPCLK1Freq(void)
+{
+  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
+}
+
+/**
+  * @brief  Returns the PCLK2 frequency
+  * @note   Each time PCLK2 changes, this function must be called to update the
+  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
+  * @retval PCLK2 frequency
+  */
+uint32_t HAL_RCC_GetPCLK2Freq(void)
+{
+  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
+  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
+}
+
+/**
+  * @brief  Configures the RCC_OscInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+  * will be configured.
+  * @retval None
+  */
+__weak void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  /* Set all possible values for the Oscillator type parameter ---------------*/
+  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+  /* Get the HSE configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+  }
+  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+
+  /* Get the HSI configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+  }
+
+  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+
+  /* Get the LSE configuration -----------------------------------------------*/
+  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+  }
+  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+
+  /* Get the LSI configuration -----------------------------------------------*/
+  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+  }
+
+  /* Get the PLL configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+  }
+  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
+  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos);
+  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
+}
+
+/**
+  * @brief  Configures the RCC_ClkInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
+  * will be configured.
+  * @param  pFLatency Pointer on the Flash Latency.
+  * @retval None
+  */
+void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
+{
+  /* Set all possible values for the Clock type parameter --------------------*/
+  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+
+  /* Get the SYSCLK configuration --------------------------------------------*/
+  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
+
+  /* Get the HCLK configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+  /* Get the APB1 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
+
+  /* Get the APB2 configuration ----------------------------------------------*/
+  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
+
+  /* Get the Flash Wait State (Latency) configuration ------------------------*/
+  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+}
+
+/**
+  * @brief This function handles the RCC CSS interrupt request.
+  * @note This API should be called under the NMI_Handler().
+  * @retval None
+  */
+void HAL_RCC_NMI_IRQHandler(void)
+{
+  /* Check RCC CSSF flag  */
+  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
+  {
+    /* RCC Clock Security System interrupt user callback */
+    HAL_RCC_CSSCallback();
+
+    /* Clear RCC CSS pending bit */
+    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
+  }
+}
+
+/**
+  * @brief  RCC Clock Security System interrupt callback
+  * @retval None
+  */
+__weak void HAL_RCC_CSSCallback(void)
+{
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_RCC_CSSCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c
index 5076628..dd89656 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c
@@ -1,3784 +1,3784 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_rcc_ex.c
-  * @author  MCD Application Team
-  * @brief   Extension RCC HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities RCC extension peripheral:
-  *           + Extended Peripheral Control functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2017 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file in
-  * the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RCCEx RCCEx
-  * @brief RCCEx HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup RCCEx_Private_Constants
-  * @{
-  */
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
-  *  @{
-  */
-
-/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
- *  @brief  Extended Peripheral Control functions
- *
-@verbatim
- ===============================================================================
-                ##### Extended Peripheral Control functions  #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the RCC Clocks
-    frequencies.
-    [..]
-    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
-        select the RTC clock source; in this case the Backup domain will be reset in
-        order to modify the RTC Clock source, as consequence RTC registers (including
-        the backup registers) and RCC_BDCR register are set to their reset values.
-
-@endverbatim
-  * @{
-  */
-
-#if defined(STM32F446xx)
-/**
-  * @brief  Initializes the RCC extended peripherals clocks according to the specified
-  *         parameters in the RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains the configuration information for the Extended Peripherals
-  *         clocks(I2S, SAI, LTDC RTC and TIM).
-  *
-  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
-  *         the RTC clock source; in this case the Backup domain will be reset in
-  *         order to modify the RTC Clock source, as consequence RTC registers (including
-  *         the backup registers) and RCC_BDCR register are set to their reset values.
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tickstart = 0U;
-  uint32_t tmpreg1 = 0U;
-  uint32_t plli2sp = 0U;
-  uint32_t plli2sq = 0U;
-  uint32_t plli2sr = 0U;
-  uint32_t pllsaip = 0U;
-  uint32_t pllsaiq = 0U;
-  uint32_t plli2sused = 0U;
-  uint32_t pllsaiused = 0U;
-
-  /* Check the peripheral clock selection parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
-  /*------------------------ I2S APB1 configuration --------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
-
-    /* Configure I2S Clock source */
-    __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
-    /* Enable the PLLI2S when it's used as clock source for I2S */
-    if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
-    {
-      plli2sused = 1U;
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*---------------------------- I2S APB2 configuration ----------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
-
-    /* Configure I2S Clock source */
-    __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
-    /* Enable the PLLI2S when it's used as clock source for I2S */
-    if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
-    {
-      plli2sused = 1U;
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*--------------------------- SAI1 configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
-
-    /* Configure SAI1 Clock source */
-    __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
-    /* Enable the PLLI2S when it's used as clock source for SAI */
-    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
-    {
-      plli2sused = 1U;
-    }
-    /* Enable the PLLSAI when it's used as clock source for SAI */
-    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
-    {
-      pllsaiused = 1U;
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*-------------------------- SAI2 configuration ----------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
-
-    /* Configure SAI2 Clock source */
-    __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
-
-    /* Enable the PLLI2S when it's used as clock source for SAI */
-    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
-    {
-      plli2sused = 1U;
-    }
-    /* Enable the PLLSAI when it's used as clock source for SAI */
-    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
-    {
-      pllsaiused = 1U;
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*----------------------------- RTC configuration --------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
-  {
-    /* Check for RTC Parameters used to output RTCCLK */
-    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-
-    /* Enable write access to Backup domain */
-    PWR->CR |= PWR_CR_DBP;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    while((PWR->CR & PWR_CR_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
-    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
-    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
-    {
-      /* Store the content of BDCR register before the reset of Backup Domain */
-      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
-      /* RTC Clock selection can be changed only if the Backup Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
-      __HAL_RCC_BACKUPRESET_RELEASE();
-      /* Restore the Content of BDCR register */
-      RCC->BDCR = tmpreg1;
-
-      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
-      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
-      {
-        /* Get tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till LSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*---------------------------- TIM configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
-  {
-    /* Configure Timer Prescaler */
-    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*---------------------------- FMPI2C1 Configuration -----------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
-
-    /* Configure the FMPI2C1 clock source */
-    __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*------------------------------ CEC Configuration -------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
-
-    /* Configure the CEC clock source */
-    __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*----------------------------- CLK48 Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
-
-    /* Configure the CLK48 clock source */
-    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
-
-    /* Enable the PLLSAI when it's used as clock source for CLK48 */
-    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
-    {
-      pllsaiused = 1U;
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*----------------------------- SDIO Configuration -------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
-
-    /* Configure the SDIO clock source */
-    __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*------------------------------ SPDIFRX Configuration ---------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
-
-    /* Configure the SPDIFRX clock source */
-    __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
-    /* Enable the PLLI2S when it's used as clock source for SPDIFRX */
-    if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
-    {
-      plli2sused = 1U;
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*---------------------------- PLLI2S Configuration ------------------------*/
-  /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
-     I2S on APB2 or SPDIFRX */
-  if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
-  {
-    /* Disable the PLLI2S */
-    __HAL_RCC_PLLI2S_DISABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is disabled */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* check for common PLLI2S Parameters */
-    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
-    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-
-    /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/
-    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
-       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
-    {
-      /* check for Parameters */
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-
-      /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
-      plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
-      plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
-      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
-    }
-
-    /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
-    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
-       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
-    {
-      /* Check for PLLI2S Parameters */
-      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-      /* Check for PLLI2S/DIVQ parameters */
-      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
-
-      /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
-      plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
-      plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
-      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
-
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
-      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
-    }
-
-    /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/
-    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
-    {
-      /* check for Parameters */
-      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
-      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
-      plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
-      plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
-      /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
-    }
-
-     /*----------------- In Case of PLLI2S is just selected  -----------------*/
-    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
-    {
-      /* Check for Parameters */
-      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
-    }
-
-    /* Enable the PLLI2S */
-    __HAL_RCC_PLLI2S_ENABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*----------------------------- PLLSAI Configuration -----------------------*/
-  /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */
-  if(pllsaiused == 1U)
-  {
-    /* Disable PLLSAI Clock */
-    __HAL_RCC_PLLSAI_DISABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLSAI is disabled */
-    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Check the PLLSAI division factors */
-    assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
-    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
-
-    /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/
-    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
-       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
-    {
-      /* check for PLLSAIQ Parameter */
-      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
-      /* check for PLLSAI/DIVQ Parameter */
-      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
-
-      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
-      pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
-      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
-
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
-      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
-    }
-
-    /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/
-    /* In Case of PLLI2S is selected as source clock for CLK48 */
-    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
-    {
-      /* check for Parameters */
-      assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
-      /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
-      pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
-      /* Configure the PLLSAI division factors */
-      /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
-      /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U);
-    }
-
-    /* Enable PLLSAI Clock */
-    __HAL_RCC_PLLSAI_ENABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLSAI is ready */
-    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal
-  *         RCC configuration registers.
-  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         will be configured.
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tempreg;
-
-  /* Set all possible values for the extended clock type parameter------------*/
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
-                                        RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\
-                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
-                                        RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_FMPI2C1  |\
-                                        RCC_PERIPHCLK_CLK48     | RCC_PERIPHCLK_SDIO     |\
-                                        RCC_PERIPHCLK_SPDIFRX;
-
-  /* Get the PLLI2S Clock configuration --------------------------------------*/
-  PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos);
-  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
-  PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
-  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
-  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
-  /* Get the PLLSAI Clock configuration --------------------------------------*/
-  PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> RCC_PLLSAICFGR_PLLSAIM_Pos);
-  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
-  PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
-  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
-  /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
-  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
-  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
-
-  /* Get the SAI1 clock configuration ----------------------------------------*/
-  PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
-
-  /* Get the SAI2 clock configuration ----------------------------------------*/
-  PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
-
-  /* Get the I2S APB1 clock configuration ------------------------------------*/
-  PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
-
-  /* Get the I2S APB2 clock configuration ------------------------------------*/
-  PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
-
-  /* Get the RTC Clock configuration -----------------------------------------*/
-  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
-  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-
-  /* Get the CEC clock configuration -----------------------------------------*/
-  PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
-
-  /* Get the FMPI2C1 clock configuration -------------------------------------*/
-  PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
-
-  /* Get the CLK48 clock configuration ----------------------------------------*/
-  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
-
-  /* Get the SDIO clock configuration ----------------------------------------*/
-  PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
-
-  /* Get the SPDIFRX clock configuration -------------------------------------*/
-  PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
-
-  /* Get the TIM Prescaler configuration -------------------------------------*/
-  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
-  }
-  else
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
-  }
-}
-
-/**
-  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
-  * @note   Return 0 if peripheral clock identifier not managed by this API
-  * @param  PeriphClk Peripheral clock identifier
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
-  *            @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
-  *            @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock
-  *            @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock
-  * @retval Frequency in KHz
-  */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
-{
-  uint32_t tmpreg1 = 0U;
-  /* This variable used to store the SAI clock frequency (value in Hz) */
-  uint32_t frequency = 0U;
-  /* This variable used to store the VCO Input (value in Hz) */
-  uint32_t vcoinput = 0U;
-  /* This variable used to store the SAI clock source */
-  uint32_t saiclocksource = 0U;
-  uint32_t srcclk = 0U;
-  /* This variable used to store the VCO Output (value in Hz) */
-  uint32_t vcooutput = 0U;
-  switch (PeriphClk)
-  {
-  case RCC_PERIPHCLK_SAI1:
-  case RCC_PERIPHCLK_SAI2:
-    {
-      saiclocksource = RCC->DCKCFGR;
-      saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC);
-      switch (saiclocksource)
-      {
-      case 0U: /* PLLSAI is the clock source for SAI*/
-        {
-          /* Configure the PLLSAI division factor */
-          /* PLLSAI_VCO Input  = PLL_SOURCE/PLLSAIM */
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
-          {
-            /* In Case the PLL Source is HSI (Internal Clock) */
-            vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));
-          }
-          else
-          {
-            /* In Case the PLL Source is HSE (External Clock) */
-            vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));
-          }
-          /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-          /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
-          tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;
-          frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg1);
-
-          /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
-          tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);
-          frequency = frequency/(tmpreg1);
-          break;
-        }
-      case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
-      case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
-        {
-          /* Configure the PLLI2S division factor */
-          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
-          {
-            /* In Case the PLL Source is HSI (Internal Clock) */
-            vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-          }
-          else
-          {
-            /* In Case the PLL Source is HSE (External Clock) */
-            vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));
-          }
-
-          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-          /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
-          tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;
-          frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg1);
-
-          /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
-          tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);
-          frequency = frequency/(tmpreg1);
-          break;
-        }
-      case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
-      case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
-        {
-          /* Configure the PLLI2S division factor */
-          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
-          {
-            /* In Case the PLL Source is HSI (Internal Clock) */
-            vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-          else
-          {
-            /* In Case the PLL Source is HSE (External Clock) */
-            vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
-          }
-
-          /* PLL_VCO Output = PLL_VCO Input * PLLN */
-          /* SAI_CLK_x = PLL_VCO Output/PLLR */
-          tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U;
-          frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg1);
-          break;
-        }
-      case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
-        {
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
-        }
-      case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
-        {
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
-          {
-            /* In Case the PLL Source is HSI (Internal Clock) */
-            frequency = (uint32_t)(HSI_VALUE);
-          }
-          else
-          {
-            /* In Case the PLL Source is HSE (External Clock) */
-            frequency = (uint32_t)(HSE_VALUE);
-          }
-          break;
-        }
-      default :
-        {
-          break;
-        }
-      }
-      break;
-    }
-  case RCC_PERIPHCLK_I2S_APB1:
-    {
-      /* Get the current I2S source */
-      srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();
-      switch (srcclk)
-      {
-      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
-      case RCC_I2SAPB1CLKSOURCE_EXT:
-        {
-          /* Set the I2S clock to the external clock  value */
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
-        }
-      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
-      case RCC_I2SAPB1CLKSOURCE_PLLI2S:
-        {
-          /* Configure the PLLI2S division factor */
-          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-          }
-          else
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-          }
-
-          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
-          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
-          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
-          break;
-        }
-      /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
-      case RCC_I2SAPB1CLKSOURCE_PLLR:
-        {
-          /* Configure the PLL division factor R */
-          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-          else
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-
-          /* PLL_VCO Output = PLL_VCO Input * PLLN */
-          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
-          /* I2S_CLK = PLL_VCO Output/PLLR */
-          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
-          break;
-        }
-      /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
-      case RCC_I2SAPB1CLKSOURCE_PLLSRC:
-        {
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-          {
-            frequency = HSE_VALUE;
-          }
-          else
-          {
-            frequency = HSI_VALUE;
-          }
-          break;
-        }
-        /* Clock not enabled for I2S*/
-      default:
-        {
-          frequency = 0U;
-          break;
-        }
-      }
-      break;
-    }
-  case RCC_PERIPHCLK_I2S_APB2:
-    {
-      /* Get the current I2S source */
-      srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
-      switch (srcclk)
-      {
-        /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
-      case RCC_I2SAPB2CLKSOURCE_EXT:
-        {
-          /* Set the I2S clock to the external clock  value */
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
-        }
-        /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
-      case RCC_I2SAPB2CLKSOURCE_PLLI2S:
-        {
-          /* Configure the PLLI2S division factor */
-          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-          }
-          else
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-          }
-
-          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
-          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
-          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
-          break;
-        }
-        /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
-      case RCC_I2SAPB2CLKSOURCE_PLLR:
-        {
-          /* Configure the PLL division factor R */
-          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-          else
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-
-          /* PLL_VCO Output = PLL_VCO Input * PLLN */
-          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
-          /* I2S_CLK = PLL_VCO Output/PLLR */
-          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
-          break;
-        }
-        /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
-      case RCC_I2SAPB2CLKSOURCE_PLLSRC:
-        {
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-          {
-            frequency = HSE_VALUE;
-          }
-          else
-          {
-            frequency = HSI_VALUE;
-          }
-          break;
-        }
-        /* Clock not enabled for I2S*/
-      default:
-        {
-          frequency = 0U;
-          break;
-        }
-      }
-      break;
-    }
-  }
-  return frequency;
-}
-#endif /* STM32F446xx */
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-/**
-  * @brief  Initializes the RCC extended peripherals clocks according to the specified
-  *         parameters in the RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains the configuration information for the Extended Peripherals
-  *         clocks(I2S, SAI, LTDC, RTC and TIM).
-  *
-  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
-  *         the RTC clock source; in this case the Backup domain will be reset in
-  *         order to modify the RTC Clock source, as consequence RTC registers (including
-  *         the backup registers) and RCC_BDCR register are set to their reset values.
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tickstart = 0U;
-  uint32_t tmpreg1 = 0U;
-  uint32_t pllsaip = 0U;
-  uint32_t pllsaiq = 0U;
-  uint32_t pllsair = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
-  /*--------------------------- CLK48 Configuration --------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
-
-    /* Configure the CLK48 clock source */
-    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*------------------------------ SDIO Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
-
-    /* Configure the SDIO clock source */
-    __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
-  /*------------------- Common configuration SAI/I2S -------------------------*/
-  /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
-     factor is common parameters for both peripherals */
-  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
-     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
-     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
-  {
-    /* check for Parameters */
-    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-
-    /* Disable the PLLI2S */
-    __HAL_RCC_PLLI2S_DISABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is disabled */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /*---------------------- I2S configuration -------------------------------*/
-    /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
-      only for I2S configuration */
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
-    {
-      /* check for Parameters */
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
-      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
-    }
-
-    /*---------------------------- SAI configuration -------------------------*/
-    /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
-       be added only for SAI configuration */
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
-    {
-      /* Check the PLLI2S division factors */
-      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
-
-      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
-      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
-      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
-      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
-    }
-
-    /*----------------- In Case of PLLI2S is just selected  -----------------*/
-    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
-    {
-      /* Check for Parameters */
-      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-
-      /* Configure the PLLI2S multiplication and division factors */
-      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
-    }
-
-    /* Enable the PLLI2S */
-    __HAL_RCC_PLLI2S_ENABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
-  /*----------------------- Common configuration SAI/LTDC --------------------*/
-  /* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division
-     factor is common parameters for these peripherals */
-  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
-     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)             ||
-     ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)          &&
-      (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)))
-  {
-    /* Check the PLLSAI division factors */
-    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
-
-    /* Disable PLLSAI Clock */
-    __HAL_RCC_PLLSAI_DISABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLSAI is disabled */
-    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /*---------------------------- SAI configuration -------------------------*/
-    /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
-       be added only for SAI configuration */
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
-    {
-      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
-      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
-
-      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
-      pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
-      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
-      pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
-      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair);
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
-      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
-    }
-
-    /*---------------------------- LTDC configuration ------------------------*/
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
-    {
-      assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
-      assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
-
-      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
-      pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
-      /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
-      pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
-      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-      /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR);
-      /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
-      __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
-    }
-
-    /*---------------------------- CLK48 configuration ------------------------*/
-    /* Configure the PLLSAI when it is used as clock source for CLK48 */
-    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) &&
-       (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
-    {
-      assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
-
-      /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
-      pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
-      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
-      pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
-      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-      /* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair);
-    }
-
-    /* Enable PLLSAI Clock */
-    __HAL_RCC_PLLSAI_ENABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLSAI is ready */
-    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /*--------------------------------------------------------------------------*/
-
-  /*---------------------------- RTC configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
-  {
-    /* Check for RTC Parameters used to output RTCCLK */
-    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-
-    /* Enable write access to Backup domain */
-    PWR->CR |= PWR_CR_DBP;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    while((PWR->CR & PWR_CR_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
-    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
-    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
-    {
-      /* Store the content of BDCR register before the reset of Backup Domain */
-      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
-      /* RTC Clock selection can be changed only if the Backup Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
-      __HAL_RCC_BACKUPRESET_RELEASE();
-      /* Restore the Content of BDCR register */
-      RCC->BDCR = tmpreg1;
-
-      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
-      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
-      {
-        /* Get tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till LSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*---------------------------- TIM configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
-  {
-    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the RCC_PeriphCLKInitTypeDef according to the internal
-  * RCC configuration registers.
-  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         will be configured.
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tempreg;
-
-  /* Set all possible values for the extended clock type parameter------------*/
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S        | RCC_PERIPHCLK_SAI_PLLSAI |\
-                                        RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC       |\
-                                        RCC_PERIPHCLK_TIM        | RCC_PERIPHCLK_RTC        |\
-                                        RCC_PERIPHCLK_CLK48       | RCC_PERIPHCLK_SDIO;
-
-  /* Get the PLLI2S Clock configuration --------------------------------------*/
-  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
-  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
-  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
-  /* Get the PLLSAI Clock configuration --------------------------------------*/
-  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
-  PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
-  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
-  /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
-  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
-  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
-  PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
-  /* Get the RTC Clock configuration -----------------------------------------*/
-  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
-  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-
-    /* Get the CLK48 clock configuration -------------------------------------*/
-  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
-
-  /* Get the SDIO clock configuration ----------------------------------------*/
-  PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
-
-  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
-  }
-  else
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
-  }
-}
-
-/**
-  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
-  * @note   Return 0 if peripheral clock identifier not managed by this API
-  * @param  PeriphClk Peripheral clock identifier
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
-  * @retval Frequency in KHz
-  */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
-{
-  /* This variable used to store the I2S clock frequency (value in Hz) */
-  uint32_t frequency = 0U;
-  /* This variable used to store the VCO Input (value in Hz) */
-  uint32_t vcoinput = 0U;
-  uint32_t srcclk = 0U;
-  /* This variable used to store the VCO Output (value in Hz) */
-  uint32_t vcooutput = 0U;
-  switch (PeriphClk)
-  {
-  case RCC_PERIPHCLK_I2S:
-    {
-      /* Get the current I2S source */
-      srcclk = __HAL_RCC_GET_I2S_SOURCE();
-      switch (srcclk)
-      {
-      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
-      case RCC_I2SCLKSOURCE_EXT:
-        {
-          /* Set the I2S clock to the external clock  value */
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
-        }
-      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
-      case RCC_I2SCLKSOURCE_PLLI2S:
-        {
-          /* Configure the PLLI2S division factor */
-          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-          else
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-
-          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
-          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
-          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
-          break;
-        }
-        /* Clock not enabled for I2S*/
-      default:
-        {
-          frequency = 0U;
-          break;
-        }
-      }
-      break;
-    }
-  }
-  return frequency;
-}
-#endif /* STM32F469xx || STM32F479xx */
-
-#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-/**
-  * @brief  Initializes the RCC extended peripherals clocks according to the specified
-  *         parameters in the RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains the configuration information for the Extended Peripherals
-  *         clocks(I2S, LTDC RTC and TIM).
-  *
-  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
-  *         the RTC clock source; in this case the Backup domain will be reset in
-  *         order to modify the RTC Clock source, as consequence RTC registers (including
-  *         the backup registers) and RCC_BDCR register are set to their reset values.
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tickstart = 0U;
-  uint32_t tmpreg1 = 0U;
-#if defined(STM32F413xx) || defined(STM32F423xx)
-  uint32_t plli2sq = 0U;
-#endif /* STM32F413xx || STM32F423xx */
-  uint32_t plli2sused = 0U;
-
-  /* Check the peripheral clock selection parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
-  /*----------------------------------- I2S APB1 configuration ---------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
-
-    /* Configure I2S Clock source */
-    __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
-    /* Enable the PLLI2S when it's used as clock source for I2S */
-    if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
-    {
-      plli2sused = 1U;
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*----------------------------------- I2S APB2 configuration ---------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
-
-    /* Configure I2S Clock source */
-    __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
-    /* Enable the PLLI2S when it's used as clock source for I2S */
-    if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
-    {
-      plli2sused = 1U;
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-
-#if defined(STM32F413xx) || defined(STM32F423xx)
-  /*----------------------- SAI1 Block A configuration -----------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == (RCC_PERIPHCLK_SAIA))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SAIACLKSOURCE(PeriphClkInit->SaiAClockSelection));
-
-    /* Configure SAI1 Clock source */
-    __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(PeriphClkInit->SaiAClockSelection);
-    /* Enable the PLLI2S when it's used as clock source for SAI */
-    if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)
-    {
-      plli2sused = 1U;
-    }
-    /* Enable the PLLSAI when it's used as clock source for SAI */
-    if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLR)
-    {
-      /* Check for PLL/DIVR parameters */
-      assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));
-
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
-      __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR);
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*---------------------- SAI1 Block B configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == (RCC_PERIPHCLK_SAIB))
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SAIBCLKSOURCE(PeriphClkInit->SaiBClockSelection));
-
-    /* Configure SAI1 Clock source */
-    __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(PeriphClkInit->SaiBClockSelection);
-    /* Enable the PLLI2S when it's used as clock source for SAI */
-    if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)
-    {
-      plli2sused = 1U;
-    }
-    /* Enable the PLLSAI when it's used as clock source for SAI */
-    if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLR)
-    {
-      /* Check for PLL/DIVR parameters */
-      assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));
-
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
-      __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR);
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-#endif /* STM32F413xx || STM32F423xx */
-
-  /*------------------------------------ RTC configuration -------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
-  {
-    /* Check for RTC Parameters used to output RTCCLK */
-    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-
-    /* Enable write access to Backup domain */
-    PWR->CR |= PWR_CR_DBP;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    while((PWR->CR & PWR_CR_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
-    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
-    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
-    {
-      /* Store the content of BDCR register before the reset of Backup Domain */
-      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
-      /* RTC Clock selection can be changed only if the Backup Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
-      __HAL_RCC_BACKUPRESET_RELEASE();
-      /* Restore the Content of BDCR register */
-      RCC->BDCR = tmpreg1;
-
-      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
-      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
-      {
-        /* Get tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till LSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*------------------------------------ TIM configuration -------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
-  {
-    /* Configure Timer Prescaler */
-    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*------------------------------------- FMPI2C1 Configuration --------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
-
-    /* Configure the FMPI2C1 clock source */
-    __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*------------------------------------- CLK48 Configuration ----------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
-
-    /* Configure the SDIO clock source */
-    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
-
-    /* Enable the PLLI2S when it's used as clock source for CLK48 */
-    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)
-    {
-      plli2sused = 1U;
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*------------------------------------- SDIO Configuration -----------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
-
-    /* Configure the SDIO clock source */
-    __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*-------------------------------------- PLLI2S Configuration --------------*/
-  /* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or
-     I2S on APB2*/
-  if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
-  {
-    /* Disable the PLLI2S */
-    __HAL_RCC_PLLI2S_DISABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is disabled */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* check for common PLLI2S Parameters */
-    assert_param(IS_RCC_PLLI2SCLKSOURCE(PeriphClkInit->PLLI2SSelection));
-    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
-    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-    /*-------------------- Set the PLL I2S clock -----------------------------*/
-    __HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection);
-
-    /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/
-    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
-       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) ||
-       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) ||
-       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) && (PeriphClkInit->SdioClockSelection == RCC_SDIOCLKSOURCE_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)))
-    {
-      /* check for Parameters */
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
-      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
-    }
-
-#if defined(STM32F413xx) || defined(STM32F423xx)
-    /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
-    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == RCC_PERIPHCLK_SAIA) && (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)) ||
-       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)))
-    {
-      /* Check for PLLI2S Parameters */
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-      /* Check for PLLI2S/DIVR parameters */
-      assert_param(IS_RCC_PLLI2S_DIVR_VALUE(PeriphClkInit->PLLI2SDivR));
-
-      /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
-      plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
-      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
-
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */
-      __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR);
-    }
-#endif /* STM32F413xx || STM32F423xx */
-
-    /*----------------- In Case of PLLI2S is just selected  ------------------*/
-    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
-    {
-      /* Check for Parameters */
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
-      /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
-    }
-
-    /* Enable the PLLI2S */
-    __HAL_RCC_PLLI2S_ENABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*-------------------- DFSDM1 clock source configuration -------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
-
-    /* Configure the DFSDM1 interface clock source */
-    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*-------------------- DFSDM1 Audio clock source configuration -------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
-
-    /* Configure the DFSDM1 Audio interface clock source */
-    __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-#if defined(STM32F413xx) || defined(STM32F423xx)
-  /*-------------------- DFSDM2 clock source configuration -------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
-
-    /* Configure the DFSDM1 interface clock source */
-    __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*-------------------- DFSDM2 Audio clock source configuration -------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2_AUDIO) == RCC_PERIPHCLK_DFSDM2_AUDIO)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_DFSDM2AUDIOCLKSOURCE(PeriphClkInit->Dfsdm2AudioClockSelection));
-
-    /* Configure the DFSDM1 Audio interface clock source */
-    __HAL_RCC_DFSDM2AUDIO_CONFIG(PeriphClkInit->Dfsdm2AudioClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*---------------------------- LPTIM1 Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
-
-    /* Configure the LPTIM1 clock source */
-    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-#endif /* STM32F413xx || STM32F423xx */
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal
-  *         RCC configuration registers.
-  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         will be configured.
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tempreg;
-
-  /* Set all possible values for the extended clock type parameter------------*/
-#if defined(STM32F413xx) || defined(STM32F423xx)
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1     | RCC_PERIPHCLK_I2S_APB2 |\
-                                        RCC_PERIPHCLK_TIM          | RCC_PERIPHCLK_RTC      |\
-                                        RCC_PERIPHCLK_FMPI2C1      | RCC_PERIPHCLK_CLK48    |\
-                                        RCC_PERIPHCLK_SDIO         | RCC_PERIPHCLK_DFSDM1   |\
-                                        RCC_PERIPHCLK_DFSDM1_AUDIO | RCC_PERIPHCLK_DFSDM2   |\
-                                        RCC_PERIPHCLK_DFSDM2_AUDIO | RCC_PERIPHCLK_LPTIM1   |\
-                                        RCC_PERIPHCLK_SAIA         | RCC_PERIPHCLK_SAIB;
-#else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
-                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
-                                        RCC_PERIPHCLK_FMPI2C1  | RCC_PERIPHCLK_CLK48    |\
-                                        RCC_PERIPHCLK_SDIO     | RCC_PERIPHCLK_DFSDM1   |\
-                                        RCC_PERIPHCLK_DFSDM1_AUDIO;
-#endif /* STM32F413xx || STM32F423xx */
-
-
-
-  /* Get the PLLI2S Clock configuration --------------------------------------*/
-  PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos);
-  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
-  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
-  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
-#if defined(STM32F413xx) || defined(STM32F423xx)
-  /* Get the PLL/PLLI2S division factors -------------------------------------*/
-  PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> RCC_DCKCFGR_PLLI2SDIVR_Pos);
-  PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> RCC_DCKCFGR_PLLDIVR_Pos);
-#endif /* STM32F413xx || STM32F423xx */
-
-  /* Get the I2S APB1 clock configuration ------------------------------------*/
-  PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
-
-  /* Get the I2S APB2 clock configuration ------------------------------------*/
-  PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
-
-  /* Get the RTC Clock configuration -----------------------------------------*/
-  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
-  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-
-  /* Get the FMPI2C1 clock configuration -------------------------------------*/
-  PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
-
-  /* Get the CLK48 clock configuration ---------------------------------------*/
-  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
-
-  /* Get the SDIO clock configuration ----------------------------------------*/
-  PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
-
-  /* Get the DFSDM1 clock configuration --------------------------------------*/
-  PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
-
-  /* Get the DFSDM1 Audio clock configuration --------------------------------*/
-  PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
-
-#if defined(STM32F413xx) || defined(STM32F423xx)
-  /* Get the DFSDM2 clock configuration --------------------------------------*/
-  PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE();
-
-  /* Get the DFSDM2 Audio clock configuration --------------------------------*/
-  PeriphClkInit->Dfsdm2AudioClockSelection = __HAL_RCC_GET_DFSDM2AUDIO_SOURCE();
-
-  /* Get the LPTIM1 clock configuration --------------------------------------*/
-  PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
-
-  /* Get the SAI1 Block Aclock configuration ---------------------------------*/
-  PeriphClkInit->SaiAClockSelection = __HAL_RCC_GET_SAI_BLOCKA_SOURCE();
-
-  /* Get the SAI1 Block B clock configuration --------------------------------*/
-  PeriphClkInit->SaiBClockSelection = __HAL_RCC_GET_SAI_BLOCKB_SOURCE();
-#endif /* STM32F413xx || STM32F423xx */
-
-  /* Get the TIM Prescaler configuration -------------------------------------*/
-  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
-  }
-  else
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
-  }
-}
-
-/**
-  * @brief  Return the peripheral clock frequency for a given peripheral(I2S..)
-  * @note   Return 0 if peripheral clock identifier not managed by this API
-  * @param  PeriphClk Peripheral clock identifier
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock
-  *            @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock
-  * @retval Frequency in KHz
-  */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
-{
-  /* This variable used to store the I2S clock frequency (value in Hz) */
-  uint32_t frequency = 0U;
-  /* This variable used to store the VCO Input (value in Hz) */
-  uint32_t vcoinput = 0U;
-  uint32_t srcclk = 0U;
-  /* This variable used to store the VCO Output (value in Hz) */
-  uint32_t vcooutput = 0U;
-  switch (PeriphClk)
-  {
-  case RCC_PERIPHCLK_I2S_APB1:
-    {
-      /* Get the current I2S source */
-      srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();
-      switch (srcclk)
-      {
-      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
-      case RCC_I2SAPB1CLKSOURCE_EXT:
-        {
-          /* Set the I2S clock to the external clock  value */
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
-        }
-      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
-      case RCC_I2SAPB1CLKSOURCE_PLLI2S:
-        {
-          if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-          }
-          else
-          {
-            /* Configure the PLLI2S division factor */
-            /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
-            if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-            {
-              /* Get the I2S source clock value */
-              vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-            }
-            else
-            {
-              /* Get the I2S source clock value */
-              vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-            }
-          }
-          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
-          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
-          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
-          break;
-        }
-      /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
-      case RCC_I2SAPB1CLKSOURCE_PLLR:
-        {
-          /* Configure the PLL division factor R */
-          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-          else
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-
-          /* PLL_VCO Output = PLL_VCO Input * PLLN */
-          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
-          /* I2S_CLK = PLL_VCO Output/PLLR */
-          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
-          break;
-        }
-      /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
-      case RCC_I2SAPB1CLKSOURCE_PLLSRC:
-        {
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-          {
-            frequency = HSE_VALUE;
-          }
-          else
-          {
-            frequency = HSI_VALUE;
-          }
-          break;
-        }
-        /* Clock not enabled for I2S*/
-      default:
-        {
-          frequency = 0U;
-          break;
-        }
-      }
-      break;
-    }
-  case RCC_PERIPHCLK_I2S_APB2:
-    {
-      /* Get the current I2S source */
-      srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
-      switch (srcclk)
-      {
-        /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
-      case RCC_I2SAPB2CLKSOURCE_EXT:
-        {
-          /* Set the I2S clock to the external clock  value */
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
-        }
-        /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
-      case RCC_I2SAPB2CLKSOURCE_PLLI2S:
-        {
-          if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-          }
-          else
-          {
-            /* Configure the PLLI2S division factor */
-            /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
-            if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-            {
-              /* Get the I2S source clock value */
-              vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-            }
-            else
-            {
-              /* Get the I2S source clock value */
-              vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-            }
-          }
-          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
-          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
-          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
-          break;
-        }
-        /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
-      case RCC_I2SAPB2CLKSOURCE_PLLR:
-        {
-          /* Configure the PLL division factor R */
-          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-          else
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-
-          /* PLL_VCO Output = PLL_VCO Input * PLLN */
-          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
-          /* I2S_CLK = PLL_VCO Output/PLLR */
-          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
-          break;
-        }
-        /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
-      case RCC_I2SAPB2CLKSOURCE_PLLSRC:
-        {
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-          {
-            frequency = HSE_VALUE;
-          }
-          else
-          {
-            frequency = HSI_VALUE;
-          }
-          break;
-        }
-      /* Clock not enabled for I2S*/
-      default:
-        {
-          frequency = 0U;
-          break;
-        }
-      }
-      break;
-    }
-  }
-  return frequency;
-}
-#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/**
-  * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
-  *         RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
-  *
-  * @note   A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
-  *         the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
-  *        domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tickstart = 0U;
-  uint32_t tmpreg1 = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
-  /*---------------------------- RTC configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
-  {
-    /* Check for RTC Parameters used to output RTCCLK */
-    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-
-    /* Enable write access to Backup domain */
-    PWR->CR |= PWR_CR_DBP;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    while((PWR->CR & PWR_CR_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
-    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
-    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
-    {
-      /* Store the content of BDCR register before the reset of Backup Domain */
-      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
-      /* RTC Clock selection can be changed only if the Backup Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
-      __HAL_RCC_BACKUPRESET_RELEASE();
-      /* Restore the Content of BDCR register */
-      RCC->BDCR = tmpreg1;
-
-      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
-      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
-      {
-        /* Get tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till LSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*---------------------------- TIM configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
-  {
-    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*---------------------------- FMPI2C1 Configuration -----------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
-
-    /* Configure the FMPI2C1 clock source */
-    __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*---------------------------- LPTIM1 Configuration ------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
-
-    /* Configure the LPTIM1 clock source */
-    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
-  }
-
-  /*---------------------------- I2S Configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection));
-
-    /* Configure the I2S clock source */
-    __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the RCC_OscInitStruct according to the internal
-  * RCC configuration registers.
-  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
-  * will be configured.
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tempreg;
-
-  /* Set all possible values for the extended clock type parameter------------*/
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
-
-  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
-  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-
-  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
-  }
-  else
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
-  }
-  /* Get the FMPI2C1 clock configuration -------------------------------------*/
-  PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
-
-  /* Get the I2S clock configuration -----------------------------------------*/
-  PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE();
-
-
-}
-/**
-  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
-  * @note   Return 0 if peripheral clock identifier not managed by this API
-  * @param  PeriphClk Peripheral clock identifier
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
-  * @retval Frequency in KHz
-  */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
-{
-  /* This variable used to store the I2S clock frequency (value in Hz) */
-  uint32_t frequency = 0U;
-  /* This variable used to store the VCO Input (value in Hz) */
-  uint32_t vcoinput = 0U;
-  uint32_t srcclk = 0U;
-  /* This variable used to store the VCO Output (value in Hz) */
-  uint32_t vcooutput = 0U;
-  switch (PeriphClk)
-  {
-  case RCC_PERIPHCLK_I2S:
-    {
-      /* Get the current I2S source */
-      srcclk = __HAL_RCC_GET_I2S_SOURCE();
-      switch (srcclk)
-      {
-      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
-      case RCC_I2SAPBCLKSOURCE_EXT:
-        {
-          /* Set the I2S clock to the external clock  value */
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
-        }
-      /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
-      case RCC_I2SAPBCLKSOURCE_PLLR:
-        {
-          /* Configure the PLL division factor R */
-          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-          else
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-
-          /* PLL_VCO Output = PLL_VCO Input * PLLN */
-          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
-          /* I2S_CLK = PLL_VCO Output/PLLR */
-          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
-          break;
-        }
-      /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
-      case RCC_I2SAPBCLKSOURCE_PLLSRC:
-        {
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-          {
-            frequency = HSE_VALUE;
-          }
-          else
-          {
-            frequency = HSI_VALUE;
-          }
-          break;
-        }
-        /* Clock not enabled for I2S*/
-      default:
-        {
-          frequency = 0U;
-          break;
-        }
-      }
-      break;
-    }
-  }
-  return frequency;
-}
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
-/**
-  * @brief  Initializes the RCC extended peripherals clocks according to the specified
-  *         parameters in the RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains the configuration information for the Extended Peripherals
-  *         clocks(I2S, SAI, LTDC RTC and TIM).
-  *
-  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
-  *         the RTC clock source; in this case the Backup domain will be reset in
-  *         order to modify the RTC Clock source, as consequence RTC registers (including
-  *         the backup registers) and RCC_BDCR register are set to their reset values.
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tickstart = 0U;
-  uint32_t tmpreg1 = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
-  /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
-  /*----------------------- Common configuration SAI/I2S ---------------------*/
-  /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
-     factor is common parameters for both peripherals */
-  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
-     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
-     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
-  {
-    /* check for Parameters */
-    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-
-    /* Disable the PLLI2S */
-    __HAL_RCC_PLLI2S_DISABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is disabled */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /*---------------------------- I2S configuration -------------------------*/
-    /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
-      only for I2S configuration */
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
-    {
-      /* check for Parameters */
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
-      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
-      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
-    }
-
-    /*---------------------------- SAI configuration -------------------------*/
-    /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
-       be added only for SAI configuration */
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
-    {
-      /* Check the PLLI2S division factors */
-      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
-
-      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
-      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
-      /* Configure the PLLI2S division factors */
-      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
-      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
-      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
-    }
-
-    /*----------------- In Case of PLLI2S is just selected  -----------------*/
-    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
-    {
-      /* Check for Parameters */
-      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
-      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-
-      /* Configure the PLLI2S multiplication and division factors */
-      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
-    }
-
-    /* Enable the PLLI2S */
-    __HAL_RCC_PLLI2S_ENABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
-  /*----------------------- Common configuration SAI/LTDC --------------------*/
-  /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
-     factor is common parameters for both peripherals */
-  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
-     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
-  {
-    /* Check the PLLSAI division factors */
-    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
-
-    /* Disable PLLSAI Clock */
-    __HAL_RCC_PLLSAI_DISABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLSAI is disabled */
-    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /*---------------------------- SAI configuration -------------------------*/
-    /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
-       be added only for SAI configuration */
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
-    {
-      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
-      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
-
-      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
-      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
-      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
-      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
-      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
-    }
-
-    /*---------------------------- LTDC configuration ------------------------*/
-    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
-    {
-      assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
-      assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
-
-      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
-      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
-      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
-      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
-      /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
-      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
-      /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
-      __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
-    }
-    /* Enable PLLSAI Clock */
-    __HAL_RCC_PLLSAI_ENABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLSAI is ready */
-    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*---------------------------- RTC configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
-  {
-    /* Check for RTC Parameters used to output RTCCLK */
-    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-
-    /* Enable write access to Backup domain */
-    PWR->CR |= PWR_CR_DBP;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    while((PWR->CR & PWR_CR_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
-    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
-    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
-    {
-      /* Store the content of BDCR register before the reset of Backup Domain */
-      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
-      /* RTC Clock selection can be changed only if the Backup Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
-      __HAL_RCC_BACKUPRESET_RELEASE();
-      /* Restore the Content of BDCR register */
-      RCC->BDCR = tmpreg1;
-
-      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
-      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
-      {
-        /* Get tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till LSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-  }
-  /*--------------------------------------------------------------------------*/
-
-  /*---------------------------- TIM configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
-  {
-    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the PeriphClkInit according to the internal
-  * RCC configuration registers.
-  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         will be configured.
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tempreg;
-
-  /* Set all possible values for the extended clock type parameter------------*/
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
-
-  /* Get the PLLI2S Clock configuration -----------------------------------------------*/
-  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
-  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
-  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
-  /* Get the PLLSAI Clock configuration -----------------------------------------------*/
-  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
-  PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
-  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
-  /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
-  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
-  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
-  PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
-  /* Get the RTC Clock configuration -----------------------------------------------*/
-  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
-  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-
-  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
-  }
-  else
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
-  }
-}
-
-/**
-  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
-  * @note   Return 0 if peripheral clock identifier not managed by this API
-  * @param  PeriphClk Peripheral clock identifier
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
-  * @retval Frequency in KHz
-  */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
-{
-  /* This variable used to store the I2S clock frequency (value in Hz) */
-  uint32_t frequency = 0U;
-  /* This variable used to store the VCO Input (value in Hz) */
-  uint32_t vcoinput = 0U;
-  uint32_t srcclk = 0U;
-  /* This variable used to store the VCO Output (value in Hz) */
-  uint32_t vcooutput = 0U;
-  switch (PeriphClk)
-  {
-  case RCC_PERIPHCLK_I2S:
-    {
-      /* Get the current I2S source */
-      srcclk = __HAL_RCC_GET_I2S_SOURCE();
-      switch (srcclk)
-      {
-      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
-      case RCC_I2SCLKSOURCE_EXT:
-        {
-          /* Set the I2S clock to the external clock  value */
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
-        }
-      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
-      case RCC_I2SCLKSOURCE_PLLI2S:
-        {
-          /* Configure the PLLI2S division factor */
-          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-          else
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-
-          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
-          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
-          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
-          break;
-        }
-        /* Clock not enabled for I2S*/
-      default:
-        {
-          frequency = 0U;
-          break;
-        }
-      }
-      break;
-    }
-  }
-  return frequency;
-}
-#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
-
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
-    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
-/**
-  * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
-  *         RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
-  *
-  * @note   A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
-  *         the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
-  *        domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tickstart = 0U;
-  uint32_t tmpreg1 = 0U;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
-  /*---------------------------- I2S configuration ---------------------------*/
-  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
-     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
-  {
-    /* check for Parameters */
-    assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-#if defined(STM32F411xE)
-    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
-#endif /* STM32F411xE */
-    /* Disable the PLLI2S */
-    __HAL_RCC_PLLI2S_DISABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is disabled */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-
-#if defined(STM32F411xE)
-    /* Configure the PLLI2S division factors */
-    /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
-    /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
-    __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
-#else
-    /* Configure the PLLI2S division factors */
-    /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
-    /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
-    __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
-#endif /* STM32F411xE */
-
-    /* Enable the PLLI2S */
-    __HAL_RCC_PLLI2S_ENABLE();
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    /* Wait till PLLI2S is ready */
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-      {
-        /* return in case of Timeout detected */
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /*---------------------------- RTC configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
-  {
-    /* Check for RTC Parameters used to output RTCCLK */
-    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
-    /* Enable Power Clock*/
-    __HAL_RCC_PWR_CLK_ENABLE();
-
-    /* Enable write access to Backup domain */
-    PWR->CR |= PWR_CR_DBP;
-
-    /* Get tick */
-    tickstart = HAL_GetTick();
-
-    while((PWR->CR & PWR_CR_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
-    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
-    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
-    {
-      /* Store the content of BDCR register before the reset of Backup Domain */
-      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
-      /* RTC Clock selection can be changed only if the Backup Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
-      __HAL_RCC_BACKUPRESET_RELEASE();
-      /* Restore the Content of BDCR register */
-      RCC->BDCR = tmpreg1;
-
-      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
-      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
-      {
-        /* Get tick */
-        tickstart = HAL_GetTick();
-
-        /* Wait till LSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-  }
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
-  /*---------------------------- TIM configuration ---------------------------*/
-  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
-  {
-    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
-  }
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the RCC_OscInitStruct according to the internal
-  * RCC configuration registers.
-  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
-  * will be configured.
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tempreg;
-
-  /* Set all possible values for the extended clock type parameter------------*/
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
-
-  /* Get the PLLI2S Clock configuration --------------------------------------*/
-  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
-  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
-#if defined(STM32F411xE)
-  PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
-#endif /* STM32F411xE */
-  /* Get the RTC Clock configuration -----------------------------------------*/
-  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
-  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-
-#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
-  /* Get the TIM Prescaler configuration -------------------------------------*/
-  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
-  }
-  else
-  {
-    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
-  }
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
-}
-
-/**
-  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
-  * @note   Return 0 if peripheral clock identifier not managed by this API
-  * @param  PeriphClk Peripheral clock identifier
-  *         This parameter can be one of the following values:
-  *            @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
-  * @retval Frequency in KHz
-  */
-uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
-{
-  /* This variable used to store the I2S clock frequency (value in Hz) */
-  uint32_t frequency = 0U;
-  /* This variable used to store the VCO Input (value in Hz) */
-  uint32_t vcoinput = 0U;
-  uint32_t srcclk = 0U;
-  /* This variable used to store the VCO Output (value in Hz) */
-  uint32_t vcooutput = 0U;
-  switch (PeriphClk)
-  {
-  case RCC_PERIPHCLK_I2S:
-    {
-      /* Get the current I2S source */
-      srcclk = __HAL_RCC_GET_I2S_SOURCE();
-      switch (srcclk)
-      {
-      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
-      case RCC_I2SCLKSOURCE_EXT:
-        {
-          /* Set the I2S clock to the external clock  value */
-          frequency = EXTERNAL_CLOCK_VALUE;
-          break;
-        }
-      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
-      case RCC_I2SCLKSOURCE_PLLI2S:
-        {
-#if defined(STM32F411xE)
-          /* Configure the PLLI2S division factor */
-          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-          }
-          else
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
-          }
-#else
-          /* Configure the PLLI2S division factor */
-          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
-          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-          else
-          {
-            /* Get the I2S source clock value */
-            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
-          }
-#endif /* STM32F411xE */
-          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
-          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
-          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
-          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
-          break;
-        }
-        /* Clock not enabled for I2S*/
-      default:
-        {
-          frequency = 0U;
-          break;
-        }
-      }
-      break;
-    }
-  }
-  return frequency;
-}
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE  || STM32F411xE */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-/**
-  * @brief  Select LSE mode
-  *
-  * @note   This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx  devices.
-  *
-  * @param  Mode specifies the LSE mode.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_LSE_LOWPOWER_MODE:  LSE oscillator in low power mode selection
-  *            @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
-  * @retval None
-  */
-void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
-{
-  /* Check the parameters */
-  assert_param(IS_RCC_LSE_MODE(Mode));
-  if(Mode == RCC_LSE_HIGHDRIVE_MODE)
-  {
-    SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
-  }
-  else
-  {
-    CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
-  }
-}
-
-#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
- *  @brief  Extended Clock management functions
- *
-@verbatim   
- ===============================================================================
-                ##### Extended clock management functions  #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to control the 
-    activation or deactivation of PLLI2S, PLLSAI.
-@endverbatim
-  * @{
-  */
-
-#if defined(RCC_PLLI2S_SUPPORT)
-/**
-  * @brief  Enable PLLI2S.
-  * @param  PLLI2SInit  pointer to an RCC_PLLI2SInitTypeDef structure that
-  *         contains the configuration information for the PLLI2S
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit)
-{
-  uint32_t tickstart;
-
-  /* Check for parameters */
-  assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN));
-  assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR));
-#if defined(RCC_PLLI2SCFGR_PLLI2SM)
-  assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SInit->PLLI2SM));
-#endif /* RCC_PLLI2SCFGR_PLLI2SM */
-#if defined(RCC_PLLI2SCFGR_PLLI2SP)
-  assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP));
-#endif /* RCC_PLLI2SCFGR_PLLI2SP */
-#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
-  assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ));
-#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
-
-  /* Disable the PLLI2S */
-  __HAL_RCC_PLLI2S_DISABLE();
-
-  /* Wait till PLLI2S is disabled */
-  tickstart = HAL_GetTick();
-  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-    {
-      /* return in case of Timeout detected */
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Configure the PLLI2S division factors */
-#if defined(STM32F446xx)
-  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
-  /* I2SPCLK = PLLI2S_VCO / PLLI2SP */
-  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
-  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
-  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \
-                          PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
-#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
-      defined(STM32F413xx) || defined(STM32F423xx)
-  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
-  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
-  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
-  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \
-                          PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
-#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
-      defined(STM32F469xx) || defined(STM32F479xx)
-  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */
-  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
-  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
-  __HAL_RCC_PLLI2S_SAICLK_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
-#elif defined(STM32F411xE)
-  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
-  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
-  __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR);
-#else
-  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x PLLI2SN */
-  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
-  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR);
-#endif /* STM32F446xx */
-
-  /* Enable the PLLI2S */
-  __HAL_RCC_PLLI2S_ENABLE();
-
-  /* Wait till PLLI2S is ready */
-  tickstart = HAL_GetTick();
-  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
-    {
-      /* return in case of Timeout detected */
-      return HAL_TIMEOUT;
-    }
-  }
-
- return HAL_OK;
-}
-
-/**
-  * @brief  Disable PLLI2S.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
-{
-  uint32_t tickstart;
-
-  /* Disable the PLLI2S */
-  __HAL_RCC_PLLI2S_DISABLE();
-
-  /* Wait till PLLI2S is disabled */
-  tickstart = HAL_GetTick();
-  while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
-  {
-    if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
-    {
-      /* return in case of Timeout detected */
-      return HAL_TIMEOUT;
-    }
-  }
-
-  return HAL_OK;
-}
-
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLLSAI_SUPPORT)
-/**
-  * @brief  Enable PLLSAI.
-  * @param  PLLSAIInit  pointer to an RCC_PLLSAIInitTypeDef structure that
-  *         contains the configuration information for the PLLSAI
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef  *PLLSAIInit)
-{
-  uint32_t tickstart;
-
-  /* Check for parameters */
-  assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN));
-  assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ));
-#if defined(RCC_PLLSAICFGR_PLLSAIM)
-  assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIInit->PLLSAIM));
-#endif /* RCC_PLLSAICFGR_PLLSAIM */
-#if defined(RCC_PLLSAICFGR_PLLSAIP)
-  assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP));
-#endif /* RCC_PLLSAICFGR_PLLSAIP */
-#if defined(RCC_PLLSAICFGR_PLLSAIR)
-  assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR));
-#endif /* RCC_PLLSAICFGR_PLLSAIR */
-
-  /* Disable the PLLSAI */
-  __HAL_RCC_PLLSAI_DISABLE();
-
-  /* Wait till PLLSAI is disabled */
-  tickstart = HAL_GetTick();
-  while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
-    {
-      /* return in case of Timeout detected */
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Configure the PLLSAI division factors */
-#if defined(STM32F446xx)
-  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLSAIN/PLLSAIM) */
-  /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
-  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
-  /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
-  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIM, PLLSAIInit->PLLSAIN, \
-                          PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ, 0U);
-#elif defined(STM32F469xx) || defined(STM32F479xx)
-  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */
-  /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
-  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
-  /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
-  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \
-                          PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
-#else
-  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x PLLSAIN */
-  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
-  /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
-  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
-#endif /* STM32F446xx */
-
-  /* Enable the PLLSAI */
-  __HAL_RCC_PLLSAI_ENABLE();
-
-  /* Wait till PLLSAI is ready */
-  tickstart = HAL_GetTick();
-  while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
-    {
-      /* return in case of Timeout detected */
-      return HAL_TIMEOUT;
-    }
-  }
-
- return HAL_OK;
-}
-
-/**
-  * @brief  Disable PLLSAI.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void)
-{
-  uint32_t tickstart;
-
-  /* Disable the PLLSAI */
-  __HAL_RCC_PLLSAI_DISABLE();
-
-  /* Wait till PLLSAI is disabled */
-  tickstart = HAL_GetTick();
-  while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
-  {
-    if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
-    {
-      /* return in case of Timeout detected */
-      return HAL_TIMEOUT;
-    }
-  }
-
-  return HAL_OK;
-}
-
-#endif /* RCC_PLLSAI_SUPPORT */
-
-/**
-  * @}
-  */
-
-#if defined(STM32F446xx)
-/**
-  * @brief  Returns the SYSCLK frequency
-  *
-  * @note   This function implementation is valid only for STM32F446xx devices.
-  * @note   This function add the PLL/PLLR System clock source
-  *
-  * @note   The system frequency computed by this function is not the real
-  *         frequency in the chip. It is calculated based on the predefined
-  *         constant and the selected clock source:
-  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
-  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
-  * @note     If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**)
-  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  * @note     (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
-  *               16 MHz) but the real value may vary depending on the variations
-  *               in voltage and temperature.
-  * @note     (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
-  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
-  *                frequency of the crystal used. Otherwise, this function may
-  *                have wrong result.
-  *
-  * @note   The result of this function could be not correct when using fractional
-  *         value for HSE crystal.
-  *
-  * @note   This function can be used by the user application to compute the
-  *         baudrate for the communication peripherals or configure other parameters.
-  *
-  * @note   Each time SYSCLK changes, this function must be called to update the
-  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
-  *
-  *
-  * @retval SYSCLK frequency
-  */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
-  uint32_t pllm = 0U;
-  uint32_t pllvco = 0U;
-  uint32_t pllp = 0U;
-  uint32_t pllr = 0U;
-  uint32_t sysclockfreq = 0U;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (RCC->CFGR & RCC_CFGR_SWS)
-  {
-    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
-    {
-      sysclockfreq = HSI_VALUE;
-       break;
-    }
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
-    {
-      sysclockfreq = HSE_VALUE;
-      break;
-    }
-    case RCC_CFGR_SWS_PLL:  /* PLL/PLLP used as system clock  source */
-    {
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
-      SYSCLK = PLL_VCO / PLLP */
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
-      }
-      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
-
-      sysclockfreq = pllvco/pllp;
-      break;
-    }
-    case RCC_CFGR_SWS_PLLR:  /* PLL/PLLR used as system clock  source */
-    {
-      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
-      SYSCLK = PLL_VCO / PLLR */
-      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
-      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
-      }
-      pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
-
-      sysclockfreq = pllvco/pllr;
-      break;
-    }
-    default:
-    {
-      sysclockfreq = HSI_VALUE;
-      break;
-    }
-  }
-  return sysclockfreq;
-}
-#endif /* STM32F446xx */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @brief  Resets the RCC clock configuration to the default reset state.
-  * @note   The default reset state of the clock configuration is given below:
-  *            - HSI ON and used as system clock source
-  *            - HSE, PLL, PLLI2S and PLLSAI OFF
-  *            - AHB, APB1 and APB2 prescaler set to 1.
-  *            - CSS, MCO1 and MCO2 OFF
-  *            - All interrupts disabled
-  * @note   This function doesn't modify the configuration of the
-  *            - Peripheral clocks
-  *            - LSI, LSE and RTC clocks
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCC_DeInit(void)
-{
-  uint32_t tickstart;
-
-  /* Get Start Tick */
-  tickstart = HAL_GetTick();
-
-  /* Set HSION bit to the reset value */
-  SET_BIT(RCC->CR, RCC_CR_HSION);
-
-  /* Wait till HSI is ready */
-  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
-  {
-    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Set HSITRIM[4:0] bits to the reset value */
-  SET_BIT(RCC->CR, RCC_CR_HSITRIM_4);
-
-  /* Get Start Tick */
-  tickstart = HAL_GetTick();
-
-  /* Reset CFGR register */
-  CLEAR_REG(RCC->CFGR);
-
-  /* Wait till clock switch is ready */
-  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
-  {
-    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Get Start Tick */
-  tickstart = HAL_GetTick();
-
-  /* Clear HSEON, HSEBYP and CSSON bits */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON);
-
-  /* Wait till HSE is disabled */
-  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
-  {
-    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Get Start Tick */
-  tickstart = HAL_GetTick();
-
-  /* Clear PLLON bit */
-  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
-
-  /* Wait till PLL is disabled */
-  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
-  {
-    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-#if defined(RCC_PLLI2S_SUPPORT)
-  /* Get Start Tick */
-  tickstart = HAL_GetTick();
-
-  /* Reset PLLI2SON bit */
-  CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
-
-  /* Wait till PLLI2S is disabled */
-  while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
-  {
-    if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-#endif /* RCC_PLLI2S_SUPPORT */
-
-#if defined(RCC_PLLSAI_SUPPORT)
-  /* Get Start Tick */
-  tickstart = HAL_GetTick();
-
-  /* Reset PLLSAI bit */
-  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
-
-  /* Wait till PLLSAI is disabled */
-  while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET)
-  {
-    if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-#endif /* RCC_PLLSAI_SUPPORT */
-
-  /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */
-#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \
-    defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
-  RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLR_1;
-#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-  RCC->PLLCFGR = RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_3;
-#else
-  RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2;
-#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
-  /* Reset PLLI2SCFGR register to default value */
-#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \
-    defined(STM32F423xx) || defined(STM32F446xx)
-  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;
-#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
-  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1;
-#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;
-#elif defined(STM32F411xE)
-  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1;
-#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx */
-
-  /* Reset PLLSAICFGR register */
-#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
-  RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIR_1;
-#elif defined(STM32F446xx)
-  RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2;
-#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F469xx || STM32F479xx */
-
-  /* Disable all interrupts */
-  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE);
-
-#if defined(RCC_CIR_PLLI2SRDYIE)
-  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
-#endif /* RCC_CIR_PLLI2SRDYIE */
-
-#if defined(RCC_CIR_PLLSAIRDYIE)
-  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
-#endif /* RCC_CIR_PLLSAIRDYIE */
-
-  /* Clear all interrupt flags */
-  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);
-
-#if defined(RCC_CIR_PLLI2SRDYC)
-  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
-#endif /* RCC_CIR_PLLI2SRDYC */
-
-#if defined(RCC_CIR_PLLSAIRDYC)
-  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
-#endif /* RCC_CIR_PLLSAIRDYC */
-
-  /* Clear LSION bit */
-  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
-
-  /* Reset all CSR flags */
-  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
-
-  /* Update the SystemCoreClock global variable */
-  SystemCoreClock = HSI_VALUE;
-
-  /* Adapt Systick interrupt period */
-  if(HAL_InitTick(uwTickPrio) != HAL_OK)
-  {
-    return HAL_ERROR;
-  }
-  else
-  {
-    return HAL_OK;
-  }
-}
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
-    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
-/**
-  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
-  *         RCC_OscInitTypeDef.
-  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
-  *         contains the configuration information for the RCC Oscillators.
-  * @note   The PLL is not disabled when used as system clock.
-  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
-  *         supported by this API. User should request a transition to LSE Off
-  *         first and then LSE On or LSE Bypass.
-  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
-  *         supported by this API. User should request a transition to HSE Off
-  *         first and then HSE On or HSE Bypass.
-  * @note   This function add the PLL/PLLR factor management during PLL configuration this feature
-  *         is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-  uint32_t tickstart, pll_config;
-
-  /* Check Null pointer */
-  if(RCC_OscInitStruct == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-  /*------------------------------- HSE Configuration ------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
-#if defined(STM32F446xx)
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)                                                                     ||\
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
-#else
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)                                                                     ||\
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
-#endif /* STM32F446xx */
-    {
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
-      {
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Set the new HSE configuration ---------------------------------------*/
-      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-
-      /* Check the HSE State */
-      if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSE is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSE is bypassed or disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*----------------------------- HSI Configuration --------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
-    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
-    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
-#if defined(STM32F446xx)
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)                                                                     ||\
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
-#else
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)                                                                     ||\
-      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
-#endif /* STM32F446xx */
-    {
-      /* When HSI is used as system clock it will not disabled */
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
-      {
-        return HAL_ERROR;
-      }
-      /* Otherwise, just the calibration is allowed */
-      else
-      {
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-    }
-    else
-    {
-      /* Check the HSI State */
-      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
-      {
-        /* Enable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_ENABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-      else
-      {
-        /* Disable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_DISABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till HSI is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*------------------------------ LSI Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
-    /* Check the LSI State */
-    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
-    {
-      /* Enable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_ENABLE();
-
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSI is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      /* Disable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_DISABLE();
-
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSI is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  /*------------------------------ LSE Configuration -------------------------*/
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
-  {
-    FlagStatus       pwrclkchanged = RESET;
-
-    /* Check the parameters */
-    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
-    /* Update LSE configuration in Backup Domain control register    */
-    /* Requires to enable write access to Backup Domain of necessary */
-    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
-    {
-      __HAL_RCC_PWR_CLK_ENABLE();
-      pwrclkchanged = SET;
-    }
-
-    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
-    {
-      /* Enable write access to Backup domain */
-      SET_BIT(PWR->CR, PWR_CR_DBP);
-
-      /* Wait for Backup domain Write protection disable */
-      tickstart = HAL_GetTick();
-
-      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
-      {
-        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Set the new LSE configuration -----------------------------------------*/
-    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
-    /* Check the LSE State */
-    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSE is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-
-      /* Wait till LSE is ready */
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Restore clock configuration if changed */
-    if(pwrclkchanged == SET)
-    {
-      __HAL_RCC_PWR_CLK_DISABLE();
-    }
-  }
-  /*-------------------------------- PLL Configuration -----------------------*/
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
-  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
-  {
-    /* Check if the PLL is used as system clock or not */
-    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
-    {
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
-      {
-        /* Check the parameters */
-        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
-        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
-        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
-        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
-        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
-        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
-
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-
-        /* Configure the main PLL clock source, multiplication and division factors. */
-        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \
-                                 RCC_OscInitStruct->PLL.PLLM                                                 | \
-                                 (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)                       | \
-                                 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)        | \
-                                 (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)                       | \
-                                 (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)));
-        /* Enable the main PLL. */
-        __HAL_RCC_PLL_ENABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else
-      {
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    else
-    {
-      /* Check if there is a request to disable the PLL used as System clock source */
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        /* Do not return HAL_ERROR if request repeats the current configuration */
-        pll_config = RCC->PLLCFGR;
-#if defined (RCC_PLLCFGR_PLLR)
-        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
-#else
-        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
-            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
-#endif
-        {
-          return HAL_ERROR;
-        }
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the RCC_OscInitStruct according to the internal
-  * RCC configuration registers.
-  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured.
-  *
-  * @note   This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
-  * @note   This function add the PLL/PLLR factor management
-  * @retval None
-  */
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-  /* Set all possible values for the Oscillator type parameter ---------------*/
-  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-
-  /* Get the HSE configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
-  }
-  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
-  }
-
-  /* Get the HSI configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
-  }
-
-  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
-
-  /* Get the LSE configuration -----------------------------------------------*/
-  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
-  }
-  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
-  }
-
-  /* Get the LSI configuration -----------------------------------------------*/
-  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
-  }
-
-  /* Get the PLL configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
-  }
-  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
-  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
-  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
-  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos);
-  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
-  RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
-}
-#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_rcc_ex.c
+  * @author  MCD Application Team
+  * @brief   Extension RCC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities RCC extension peripheral:
+  *           + Extended Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file in
+  * the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RCCEx RCCEx
+  * @brief RCCEx HAL module driver
+  * @{
+  */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup RCCEx_Private_Constants
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
+  *  @{
+  */
+
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ *  @brief  Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+                ##### Extended Peripheral Control functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the RCC Clocks
+    frequencies.
+    [..]
+    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
+        select the RTC clock source; in this case the Backup domain will be reset in
+        order to modify the RTC Clock source, as consequence RTC registers (including
+        the backup registers) and RCC_BDCR register are set to their reset values.
+
+@endverbatim
+  * @{
+  */
+
+#if defined(STM32F446xx)
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals
+  *         clocks(I2S, SAI, LTDC RTC and TIM).
+  *
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source; in this case the Backup domain will be reset in
+  *         order to modify the RTC Clock source, as consequence RTC registers (including
+  *         the backup registers) and RCC_BDCR register are set to their reset values.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tickstart = 0U;
+  uint32_t tmpreg1 = 0U;
+  uint32_t plli2sp = 0U;
+  uint32_t plli2sq = 0U;
+  uint32_t plli2sr = 0U;
+  uint32_t pllsaip = 0U;
+  uint32_t pllsaiq = 0U;
+  uint32_t plli2sused = 0U;
+  uint32_t pllsaiused = 0U;
+
+  /* Check the peripheral clock selection parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*------------------------ I2S APB1 configuration --------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
+
+    /* Configure I2S Clock source */
+    __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for I2S */
+    if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- I2S APB2 configuration ----------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
+
+    /* Configure I2S Clock source */
+    __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for I2S */
+    if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*--------------------------- SAI1 configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
+
+    /* Configure SAI1 Clock source */
+    __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for SAI */
+    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1U;
+    }
+    /* Enable the PLLSAI when it's used as clock source for SAI */
+    if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
+    {
+      pllsaiused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*-------------------------- SAI2 configuration ----------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
+
+    /* Configure SAI2 Clock source */
+    __HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
+
+    /* Enable the PLLI2S when it's used as clock source for SAI */
+    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1U;
+    }
+    /* Enable the PLLSAI when it's used as clock source for SAI */
+    if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
+    {
+      pllsaiused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*----------------------------- RTC configuration --------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable Power Clock*/
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg1;
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- TIM configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    /* Configure Timer Prescaler */
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- FMPI2C1 Configuration -----------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
+
+    /* Configure the FMPI2C1 clock source */
+    __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*------------------------------ CEC Configuration -------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
+
+    /* Configure the CEC clock source */
+    __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*----------------------------- CLK48 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
+
+    /* Configure the CLK48 clock source */
+    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+
+    /* Enable the PLLSAI when it's used as clock source for CLK48 */
+    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
+    {
+      pllsaiused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*----------------------------- SDIO Configuration -------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
+
+    /* Configure the SDIO clock source */
+    __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*------------------------------ SPDIFRX Configuration ---------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
+
+    /* Configure the SPDIFRX clock source */
+    __HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for SPDIFRX */
+    if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
+    {
+      plli2sused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- PLLI2S Configuration ------------------------*/
+  /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
+     I2S on APB2 or SPDIFRX */
+  if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
+  {
+    /* Disable the PLLI2S */
+    __HAL_RCC_PLLI2S_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* check for common PLLI2S Parameters */
+    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
+    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+
+    /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+
+      /* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
+      plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
+      plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
+    {
+      /* Check for PLLI2S Parameters */
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+      /* Check for PLLI2S/DIVQ parameters */
+      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+
+      /* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
+      plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
+      plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
+
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+    }
+
+    /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/
+    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
+      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+      plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
+      plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+      /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
+    }
+
+     /*----------------- In Case of PLLI2S is just selected  -----------------*/
+    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+    {
+      /* Check for Parameters */
+      assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /* Enable the PLLI2S */
+    __HAL_RCC_PLLI2S_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*----------------------------- PLLSAI Configuration -----------------------*/
+  /* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */
+  if(pllsaiused == 1U)
+  {
+    /* Disable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLSAI is disabled */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* Check the PLLSAI division factors */
+    assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
+    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+
+    /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
+    {
+      /* check for PLLSAIQ Parameter */
+      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+      /* check for PLLSAI/DIVQ Parameter */
+      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+
+      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
+      pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
+
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+    }
+
+    /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/
+    /* In Case of PLLI2S is selected as source clock for CLK48 */
+    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
+      /* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+      pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+      /* Configure the PLLSAI division factors */
+      /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
+      /* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U);
+    }
+
+    /* Enable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLSAI is ready */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal
+  *         RCC configuration registers.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         will be configured.
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg;
+
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
+                                        RCC_PERIPHCLK_SAI1     | RCC_PERIPHCLK_SAI2     |\
+                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
+                                        RCC_PERIPHCLK_CEC      | RCC_PERIPHCLK_FMPI2C1  |\
+                                        RCC_PERIPHCLK_CLK48     | RCC_PERIPHCLK_SDIO     |\
+                                        RCC_PERIPHCLK_SPDIFRX;
+
+  /* Get the PLLI2S Clock configuration --------------------------------------*/
+  PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
+  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+  /* Get the PLLSAI Clock configuration --------------------------------------*/
+  PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> RCC_PLLSAICFGR_PLLSAIM_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
+  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+  /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
+  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
+  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
+
+  /* Get the SAI1 clock configuration ----------------------------------------*/
+  PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
+
+  /* Get the SAI2 clock configuration ----------------------------------------*/
+  PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
+
+  /* Get the I2S APB1 clock configuration ------------------------------------*/
+  PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
+
+  /* Get the I2S APB2 clock configuration ------------------------------------*/
+  PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
+
+  /* Get the RTC Clock configuration -----------------------------------------*/
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+  /* Get the CEC clock configuration -----------------------------------------*/
+  PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
+
+  /* Get the FMPI2C1 clock configuration -------------------------------------*/
+  PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
+
+  /* Get the CLK48 clock configuration ----------------------------------------*/
+  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+
+  /* Get the SDIO clock configuration ----------------------------------------*/
+  PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
+
+  /* Get the SPDIFRX clock configuration -------------------------------------*/
+  PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
+
+  /* Get the TIM Prescaler configuration -------------------------------------*/
+  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
+  *            @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
+  *            @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock
+  *            @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock
+  * @retval Frequency in KHz
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  uint32_t tmpreg1 = 0U;
+  /* This variable used to store the SAI clock frequency (value in Hz) */
+  uint32_t frequency = 0U;
+  /* This variable used to store the VCO Input (value in Hz) */
+  uint32_t vcoinput = 0U;
+  /* This variable used to store the SAI clock source */
+  uint32_t saiclocksource = 0U;
+  uint32_t srcclk = 0U;
+  /* This variable used to store the VCO Output (value in Hz) */
+  uint32_t vcooutput = 0U;
+  switch (PeriphClk)
+  {
+  case RCC_PERIPHCLK_SAI1:
+  case RCC_PERIPHCLK_SAI2:
+    {
+      saiclocksource = RCC->DCKCFGR;
+      saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC);
+      switch (saiclocksource)
+      {
+      case 0U: /* PLLSAI is the clock source for SAI*/
+        {
+          /* Configure the PLLSAI division factor */
+          /* PLLSAI_VCO Input  = PLL_SOURCE/PLLSAIM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+          {
+            /* In Case the PLL Source is HSI (Internal Clock) */
+            vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));
+          }
+          else
+          {
+            /* In Case the PLL Source is HSE (External Clock) */
+            vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));
+          }
+          /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+          /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+          tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;
+          frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg1);
+
+          /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+          tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);
+          frequency = frequency/(tmpreg1);
+          break;
+        }
+      case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
+      case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
+        {
+          /* Configure the PLLI2S division factor */
+          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+          {
+            /* In Case the PLL Source is HSI (Internal Clock) */
+            vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+          else
+          {
+            /* In Case the PLL Source is HSE (External Clock) */
+            vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));
+          }
+
+          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+          /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+          tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;
+          frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg1);
+
+          /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+          tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);
+          frequency = frequency/(tmpreg1);
+          break;
+        }
+      case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
+      case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
+        {
+          /* Configure the PLLI2S division factor */
+          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+          {
+            /* In Case the PLL Source is HSI (Internal Clock) */
+            vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* In Case the PLL Source is HSE (External Clock) */
+            vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
+          }
+
+          /* PLL_VCO Output = PLL_VCO Input * PLLN */
+          /* SAI_CLK_x = PLL_VCO Output/PLLR */
+          tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U;
+          frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg1);
+          break;
+        }
+      case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
+        {
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
+        {
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
+          {
+            /* In Case the PLL Source is HSI (Internal Clock) */
+            frequency = (uint32_t)(HSI_VALUE);
+          }
+          else
+          {
+            /* In Case the PLL Source is HSE (External Clock) */
+            frequency = (uint32_t)(HSE_VALUE);
+          }
+          break;
+        }
+      default :
+        {
+          break;
+        }
+      }
+      break;
+    }
+  case RCC_PERIPHCLK_I2S_APB1:
+    {
+      /* Get the current I2S source */
+      srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();
+      switch (srcclk)
+      {
+      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+      case RCC_I2SAPB1CLKSOURCE_EXT:
+        {
+          /* Set the I2S clock to the external clock  value */
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+      case RCC_I2SAPB1CLKSOURCE_PLLI2S:
+        {
+          /* Configure the PLLI2S division factor */
+          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+
+          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+          break;
+        }
+      /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
+      case RCC_I2SAPB1CLKSOURCE_PLLR:
+        {
+          /* Configure the PLL division factor R */
+          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+
+          /* PLL_VCO Output = PLL_VCO Input * PLLN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
+          /* I2S_CLK = PLL_VCO Output/PLLR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
+          break;
+        }
+      /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
+      case RCC_I2SAPB1CLKSOURCE_PLLSRC:
+        {
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            frequency = HSE_VALUE;
+          }
+          else
+          {
+            frequency = HSI_VALUE;
+          }
+          break;
+        }
+        /* Clock not enabled for I2S*/
+      default:
+        {
+          frequency = 0U;
+          break;
+        }
+      }
+      break;
+    }
+  case RCC_PERIPHCLK_I2S_APB2:
+    {
+      /* Get the current I2S source */
+      srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
+      switch (srcclk)
+      {
+        /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+      case RCC_I2SAPB2CLKSOURCE_EXT:
+        {
+          /* Set the I2S clock to the external clock  value */
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+        /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+      case RCC_I2SAPB2CLKSOURCE_PLLI2S:
+        {
+          /* Configure the PLLI2S division factor */
+          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+
+          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+          break;
+        }
+        /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
+      case RCC_I2SAPB2CLKSOURCE_PLLR:
+        {
+          /* Configure the PLL division factor R */
+          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+
+          /* PLL_VCO Output = PLL_VCO Input * PLLN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
+          /* I2S_CLK = PLL_VCO Output/PLLR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
+          break;
+        }
+        /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
+      case RCC_I2SAPB2CLKSOURCE_PLLSRC:
+        {
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            frequency = HSE_VALUE;
+          }
+          else
+          {
+            frequency = HSI_VALUE;
+          }
+          break;
+        }
+        /* Clock not enabled for I2S*/
+      default:
+        {
+          frequency = 0U;
+          break;
+        }
+      }
+      break;
+    }
+  }
+  return frequency;
+}
+#endif /* STM32F446xx */
+
+#if defined(STM32F469xx) || defined(STM32F479xx)
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals
+  *         clocks(I2S, SAI, LTDC, RTC and TIM).
+  *
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source; in this case the Backup domain will be reset in
+  *         order to modify the RTC Clock source, as consequence RTC registers (including
+  *         the backup registers) and RCC_BDCR register are set to their reset values.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tickstart = 0U;
+  uint32_t tmpreg1 = 0U;
+  uint32_t pllsaip = 0U;
+  uint32_t pllsaiq = 0U;
+  uint32_t pllsair = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*--------------------------- CLK48 Configuration --------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
+
+    /* Configure the CLK48 clock source */
+    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*------------------------------ SDIO Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
+
+    /* Configure the SDIO clock source */
+    __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
+  /*------------------- Common configuration SAI/I2S -------------------------*/
+  /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
+     factor is common parameters for both peripherals */
+  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
+     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
+     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
+  {
+    /* check for Parameters */
+    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+
+    /* Disable the PLLI2S */
+    __HAL_RCC_PLLI2S_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /*---------------------- I2S configuration -------------------------------*/
+    /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
+      only for I2S configuration */
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
+      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /*---------------------------- SAI configuration -------------------------*/
+    /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
+       be added only for SAI configuration */
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
+    {
+      /* Check the PLLI2S division factors */
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+
+      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+    }
+
+    /*----------------- In Case of PLLI2S is just selected  -----------------*/
+    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+    {
+      /* Check for Parameters */
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+
+      /* Configure the PLLI2S multiplication and division factors */
+      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /* Enable the PLLI2S */
+    __HAL_RCC_PLLI2S_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
+  /*----------------------- Common configuration SAI/LTDC --------------------*/
+  /* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division
+     factor is common parameters for these peripherals */
+  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
+     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)             ||
+     ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)          &&
+      (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)))
+  {
+    /* Check the PLLSAI division factors */
+    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+
+    /* Disable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLSAI is disabled */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /*---------------------------- SAI configuration -------------------------*/
+    /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
+       be added only for SAI configuration */
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
+    {
+      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+
+      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
+      pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
+      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+      pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair);
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+    }
+
+    /*---------------------------- LTDC configuration ------------------------*/
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
+    {
+      assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
+      assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
+
+      /* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
+      pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
+      /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
+      pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR);
+      /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
+      __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
+    }
+
+    /*---------------------------- CLK48 configuration ------------------------*/
+    /* Configure the PLLSAI when it is used as clock source for CLK48 */
+    if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) &&
+       (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
+    {
+      assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
+
+      /* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
+      pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+      pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair);
+    }
+
+    /* Enable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLSAI is ready */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- RTC configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable Power Clock*/
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg1;
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- TIM configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the RCC_PeriphCLKInitTypeDef according to the internal
+  * RCC configuration registers.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         will be configured.
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg;
+
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S        | RCC_PERIPHCLK_SAI_PLLSAI |\
+                                        RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC       |\
+                                        RCC_PERIPHCLK_TIM        | RCC_PERIPHCLK_RTC        |\
+                                        RCC_PERIPHCLK_CLK48       | RCC_PERIPHCLK_SDIO;
+
+  /* Get the PLLI2S Clock configuration --------------------------------------*/
+  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+  /* Get the PLLSAI Clock configuration --------------------------------------*/
+  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+  /* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
+  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
+  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
+  PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
+  /* Get the RTC Clock configuration -----------------------------------------*/
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+    /* Get the CLK48 clock configuration -------------------------------------*/
+  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+
+  /* Get the SDIO clock configuration ----------------------------------------*/
+  PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
+
+  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
+  * @retval Frequency in KHz
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  /* This variable used to store the I2S clock frequency (value in Hz) */
+  uint32_t frequency = 0U;
+  /* This variable used to store the VCO Input (value in Hz) */
+  uint32_t vcoinput = 0U;
+  uint32_t srcclk = 0U;
+  /* This variable used to store the VCO Output (value in Hz) */
+  uint32_t vcooutput = 0U;
+  switch (PeriphClk)
+  {
+  case RCC_PERIPHCLK_I2S:
+    {
+      /* Get the current I2S source */
+      srcclk = __HAL_RCC_GET_I2S_SOURCE();
+      switch (srcclk)
+      {
+      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+      case RCC_I2SCLKSOURCE_EXT:
+        {
+          /* Set the I2S clock to the external clock  value */
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+      case RCC_I2SCLKSOURCE_PLLI2S:
+        {
+          /* Configure the PLLI2S division factor */
+          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+
+          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+          break;
+        }
+        /* Clock not enabled for I2S*/
+      default:
+        {
+          frequency = 0U;
+          break;
+        }
+      }
+      break;
+    }
+  }
+  return frequency;
+}
+#endif /* STM32F469xx || STM32F479xx */
+
+#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals
+  *         clocks(I2S, LTDC RTC and TIM).
+  *
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source; in this case the Backup domain will be reset in
+  *         order to modify the RTC Clock source, as consequence RTC registers (including
+  *         the backup registers) and RCC_BDCR register are set to their reset values.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tickstart = 0U;
+  uint32_t tmpreg1 = 0U;
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  uint32_t plli2sq = 0U;
+#endif /* STM32F413xx || STM32F423xx */
+  uint32_t plli2sused = 0U;
+
+  /* Check the peripheral clock selection parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*----------------------------------- I2S APB1 configuration ---------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
+
+    /* Configure I2S Clock source */
+    __HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for I2S */
+    if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*----------------------------------- I2S APB2 configuration ---------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
+
+    /* Configure I2S Clock source */
+    __HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for I2S */
+    if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
+    {
+      plli2sused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  /*----------------------- SAI1 Block A configuration -----------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == (RCC_PERIPHCLK_SAIA))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAIACLKSOURCE(PeriphClkInit->SaiAClockSelection));
+
+    /* Configure SAI1 Clock source */
+    __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(PeriphClkInit->SaiAClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for SAI */
+    if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)
+    {
+      plli2sused = 1U;
+    }
+    /* Enable the PLLSAI when it's used as clock source for SAI */
+    if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLR)
+    {
+      /* Check for PLL/DIVR parameters */
+      assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));
+
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
+      __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR);
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------- SAI1 Block B configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == (RCC_PERIPHCLK_SAIB))
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SAIBCLKSOURCE(PeriphClkInit->SaiBClockSelection));
+
+    /* Configure SAI1 Clock source */
+    __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(PeriphClkInit->SaiBClockSelection);
+    /* Enable the PLLI2S when it's used as clock source for SAI */
+    if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)
+    {
+      plli2sused = 1U;
+    }
+    /* Enable the PLLSAI when it's used as clock source for SAI */
+    if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLR)
+    {
+      /* Check for PLL/DIVR parameters */
+      assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));
+
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
+      __HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR);
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+#endif /* STM32F413xx || STM32F423xx */
+
+  /*------------------------------------ RTC configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable Power Clock*/
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg1;
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*------------------------------------ TIM configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    /* Configure Timer Prescaler */
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*------------------------------------- FMPI2C1 Configuration --------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
+
+    /* Configure the FMPI2C1 clock source */
+    __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*------------------------------------- CLK48 Configuration ----------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
+
+    /* Configure the SDIO clock source */
+    __HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
+
+    /* Enable the PLLI2S when it's used as clock source for CLK48 */
+    if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)
+    {
+      plli2sused = 1U;
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*------------------------------------- SDIO Configuration -----------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
+
+    /* Configure the SDIO clock source */
+    __HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*-------------------------------------- PLLI2S Configuration --------------*/
+  /* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or
+     I2S on APB2*/
+  if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
+  {
+    /* Disable the PLLI2S */
+    __HAL_RCC_PLLI2S_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /* check for common PLLI2S Parameters */
+    assert_param(IS_RCC_PLLI2SCLKSOURCE(PeriphClkInit->PLLI2SSelection));
+    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
+    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+    /*-------------------- Set the PLL I2S clock -----------------------------*/
+    __HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection);
+
+    /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO) && (PeriphClkInit->SdioClockSelection == RCC_SDIOCLKSOURCE_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
+      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+    /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
+    if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == RCC_PERIPHCLK_SAIA) && (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)) ||
+       ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)))
+    {
+      /* Check for PLLI2S Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+      /* Check for PLLI2S/DIVR parameters */
+      assert_param(IS_RCC_PLLI2S_DIVR_VALUE(PeriphClkInit->PLLI2SDivR));
+
+      /* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
+      plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
+
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */
+      __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR);
+    }
+#endif /* STM32F413xx || STM32F423xx */
+
+    /*----------------- In Case of PLLI2S is just selected  ------------------*/
+    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+    {
+      /* Check for Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
+      /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /* Enable the PLLI2S */
+    __HAL_RCC_PLLI2S_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*-------------------- DFSDM1 clock source configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
+
+    /* Configure the DFSDM1 interface clock source */
+    __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*-------------------- DFSDM1 Audio clock source configuration -------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
+
+    /* Configure the DFSDM1 Audio interface clock source */
+    __HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  /*-------------------- DFSDM2 clock source configuration -------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM2CLKSOURCE(PeriphClkInit->Dfsdm2ClockSelection));
+
+    /* Configure the DFSDM1 interface clock source */
+    __HAL_RCC_DFSDM2_CONFIG(PeriphClkInit->Dfsdm2ClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*-------------------- DFSDM2 Audio clock source configuration -------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2_AUDIO) == RCC_PERIPHCLK_DFSDM2_AUDIO)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_DFSDM2AUDIOCLKSOURCE(PeriphClkInit->Dfsdm2AudioClockSelection));
+
+    /* Configure the DFSDM1 Audio interface clock source */
+    __HAL_RCC_DFSDM2AUDIO_CONFIG(PeriphClkInit->Dfsdm2AudioClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- LPTIM1 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
+
+    /* Configure the LPTIM1 clock source */
+    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+#endif /* STM32F413xx || STM32F423xx */
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get the RCC_PeriphCLKInitTypeDef according to the internal
+  *         RCC configuration registers.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         will be configured.
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg;
+
+  /* Set all possible values for the extended clock type parameter------------*/
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1     | RCC_PERIPHCLK_I2S_APB2 |\
+                                        RCC_PERIPHCLK_TIM          | RCC_PERIPHCLK_RTC      |\
+                                        RCC_PERIPHCLK_FMPI2C1      | RCC_PERIPHCLK_CLK48    |\
+                                        RCC_PERIPHCLK_SDIO         | RCC_PERIPHCLK_DFSDM1   |\
+                                        RCC_PERIPHCLK_DFSDM1_AUDIO | RCC_PERIPHCLK_DFSDM2   |\
+                                        RCC_PERIPHCLK_DFSDM2_AUDIO | RCC_PERIPHCLK_LPTIM1   |\
+                                        RCC_PERIPHCLK_SAIA         | RCC_PERIPHCLK_SAIB;
+#else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
+                                        RCC_PERIPHCLK_TIM      | RCC_PERIPHCLK_RTC      |\
+                                        RCC_PERIPHCLK_FMPI2C1  | RCC_PERIPHCLK_CLK48    |\
+                                        RCC_PERIPHCLK_SDIO     | RCC_PERIPHCLK_DFSDM1   |\
+                                        RCC_PERIPHCLK_DFSDM1_AUDIO;
+#endif /* STM32F413xx || STM32F423xx */
+
+
+
+  /* Get the PLLI2S Clock configuration --------------------------------------*/
+  PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  /* Get the PLL/PLLI2S division factors -------------------------------------*/
+  PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> RCC_DCKCFGR_PLLI2SDIVR_Pos);
+  PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> RCC_DCKCFGR_PLLDIVR_Pos);
+#endif /* STM32F413xx || STM32F423xx */
+
+  /* Get the I2S APB1 clock configuration ------------------------------------*/
+  PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
+
+  /* Get the I2S APB2 clock configuration ------------------------------------*/
+  PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
+
+  /* Get the RTC Clock configuration -----------------------------------------*/
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+  /* Get the FMPI2C1 clock configuration -------------------------------------*/
+  PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
+
+  /* Get the CLK48 clock configuration ---------------------------------------*/
+  PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
+
+  /* Get the SDIO clock configuration ----------------------------------------*/
+  PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
+
+  /* Get the DFSDM1 clock configuration --------------------------------------*/
+  PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
+
+  /* Get the DFSDM1 Audio clock configuration --------------------------------*/
+  PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+  /* Get the DFSDM2 clock configuration --------------------------------------*/
+  PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE();
+
+  /* Get the DFSDM2 Audio clock configuration --------------------------------*/
+  PeriphClkInit->Dfsdm2AudioClockSelection = __HAL_RCC_GET_DFSDM2AUDIO_SOURCE();
+
+  /* Get the LPTIM1 clock configuration --------------------------------------*/
+  PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
+
+  /* Get the SAI1 Block Aclock configuration ---------------------------------*/
+  PeriphClkInit->SaiAClockSelection = __HAL_RCC_GET_SAI_BLOCKA_SOURCE();
+
+  /* Get the SAI1 Block B clock configuration --------------------------------*/
+  PeriphClkInit->SaiBClockSelection = __HAL_RCC_GET_SAI_BLOCKB_SOURCE();
+#endif /* STM32F413xx || STM32F423xx */
+
+  /* Get the TIM Prescaler configuration -------------------------------------*/
+  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(I2S..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock
+  *            @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock
+  * @retval Frequency in KHz
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  /* This variable used to store the I2S clock frequency (value in Hz) */
+  uint32_t frequency = 0U;
+  /* This variable used to store the VCO Input (value in Hz) */
+  uint32_t vcoinput = 0U;
+  uint32_t srcclk = 0U;
+  /* This variable used to store the VCO Output (value in Hz) */
+  uint32_t vcooutput = 0U;
+  switch (PeriphClk)
+  {
+  case RCC_PERIPHCLK_I2S_APB1:
+    {
+      /* Get the current I2S source */
+      srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();
+      switch (srcclk)
+      {
+      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+      case RCC_I2SAPB1CLKSOURCE_EXT:
+        {
+          /* Set the I2S clock to the external clock  value */
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+      case RCC_I2SAPB1CLKSOURCE_PLLI2S:
+        {
+          if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+          else
+          {
+            /* Configure the PLLI2S division factor */
+            /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+            if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+            {
+              /* Get the I2S source clock value */
+              vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+            }
+            else
+            {
+              /* Get the I2S source clock value */
+              vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+            }
+          }
+          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+          break;
+        }
+      /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
+      case RCC_I2SAPB1CLKSOURCE_PLLR:
+        {
+          /* Configure the PLL division factor R */
+          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+
+          /* PLL_VCO Output = PLL_VCO Input * PLLN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
+          /* I2S_CLK = PLL_VCO Output/PLLR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
+          break;
+        }
+      /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
+      case RCC_I2SAPB1CLKSOURCE_PLLSRC:
+        {
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            frequency = HSE_VALUE;
+          }
+          else
+          {
+            frequency = HSI_VALUE;
+          }
+          break;
+        }
+        /* Clock not enabled for I2S*/
+      default:
+        {
+          frequency = 0U;
+          break;
+        }
+      }
+      break;
+    }
+  case RCC_PERIPHCLK_I2S_APB2:
+    {
+      /* Get the current I2S source */
+      srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
+      switch (srcclk)
+      {
+        /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+      case RCC_I2SAPB2CLKSOURCE_EXT:
+        {
+          /* Set the I2S clock to the external clock  value */
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+        /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+      case RCC_I2SAPB2CLKSOURCE_PLLI2S:
+        {
+          if((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SSRC) == RCC_PLLI2SCFGR_PLLI2SSRC)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(EXTERNAL_CLOCK_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+          else
+          {
+            /* Configure the PLLI2S division factor */
+            /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+            if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+            {
+              /* Get the I2S source clock value */
+              vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+            }
+            else
+            {
+              /* Get the I2S source clock value */
+              vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+            }
+          }
+          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+          break;
+        }
+        /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
+      case RCC_I2SAPB2CLKSOURCE_PLLR:
+        {
+          /* Configure the PLL division factor R */
+          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+
+          /* PLL_VCO Output = PLL_VCO Input * PLLN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
+          /* I2S_CLK = PLL_VCO Output/PLLR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
+          break;
+        }
+        /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
+      case RCC_I2SAPB2CLKSOURCE_PLLSRC:
+        {
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            frequency = HSE_VALUE;
+          }
+          else
+          {
+            frequency = HSI_VALUE;
+          }
+          break;
+        }
+      /* Clock not enabled for I2S*/
+      default:
+        {
+          frequency = 0U;
+          break;
+        }
+      }
+      break;
+    }
+  }
+  return frequency;
+}
+#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
+  *         RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
+  *
+  * @note   A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
+  *         the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
+  *        domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tickstart = 0U;
+  uint32_t tmpreg1 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*---------------------------- RTC configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable Power Clock*/
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg1;
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- TIM configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- FMPI2C1 Configuration -----------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
+
+    /* Configure the FMPI2C1 clock source */
+    __HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- LPTIM1 Configuration ------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
+
+    /* Configure the LPTIM1 clock source */
+    __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
+  }
+
+  /*---------------------------- I2S Configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection));
+
+    /* Configure the I2S clock source */
+    __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the RCC_OscInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  * will be configured.
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg;
+
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
+
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+  /* Get the FMPI2C1 clock configuration -------------------------------------*/
+  PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
+
+  /* Get the I2S clock configuration -----------------------------------------*/
+  PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE();
+
+
+}
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
+  * @retval Frequency in KHz
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  /* This variable used to store the I2S clock frequency (value in Hz) */
+  uint32_t frequency = 0U;
+  /* This variable used to store the VCO Input (value in Hz) */
+  uint32_t vcoinput = 0U;
+  uint32_t srcclk = 0U;
+  /* This variable used to store the VCO Output (value in Hz) */
+  uint32_t vcooutput = 0U;
+  switch (PeriphClk)
+  {
+  case RCC_PERIPHCLK_I2S:
+    {
+      /* Get the current I2S source */
+      srcclk = __HAL_RCC_GET_I2S_SOURCE();
+      switch (srcclk)
+      {
+      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+      case RCC_I2SAPBCLKSOURCE_EXT:
+        {
+          /* Set the I2S clock to the external clock  value */
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      /* Check if I2S clock selection is PLL VCO Output divided by PLLR used as I2S clock */
+      case RCC_I2SAPBCLKSOURCE_PLLR:
+        {
+          /* Configure the PLL division factor R */
+          /* PLL_VCO Input  = PLL_SOURCE/PLLM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+
+          /* PLL_VCO Output = PLL_VCO Input * PLLN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
+          /* I2S_CLK = PLL_VCO Output/PLLR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U) & (RCC_PLLCFGR_PLLR >> 28U)));
+          break;
+        }
+      /* Check if I2S clock selection is HSI or HSE depending from PLL source Clock */
+      case RCC_I2SAPBCLKSOURCE_PLLSRC:
+        {
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            frequency = HSE_VALUE;
+          }
+          else
+          {
+            frequency = HSI_VALUE;
+          }
+          break;
+        }
+        /* Clock not enabled for I2S*/
+      default:
+        {
+          frequency = 0U;
+          break;
+        }
+      }
+      break;
+    }
+  }
+  return frequency;
+}
+#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified
+  *         parameters in the RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals
+  *         clocks(I2S, SAI, LTDC RTC and TIM).
+  *
+  * @note   Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+  *         the RTC clock source; in this case the Backup domain will be reset in
+  *         order to modify the RTC Clock source, as consequence RTC registers (including
+  *         the backup registers) and RCC_BDCR register are set to their reset values.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tickstart = 0U;
+  uint32_t tmpreg1 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
+  /*----------------------- Common configuration SAI/I2S ---------------------*/
+  /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
+     factor is common parameters for both peripherals */
+  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
+     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
+     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
+  {
+    /* check for Parameters */
+    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+
+    /* Disable the PLLI2S */
+    __HAL_RCC_PLLI2S_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /*---------------------------- I2S configuration -------------------------*/
+    /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
+      only for I2S configuration */
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
+    {
+      /* check for Parameters */
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
+      /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+      __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /*---------------------------- SAI configuration -------------------------*/
+    /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
+       be added only for SAI configuration */
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
+    {
+      /* Check the PLLI2S division factors */
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+      assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
+
+      /* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
+      tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+      /* Configure the PLLI2S division factors */
+      /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+      /* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
+      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+      __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+    }
+
+    /*----------------- In Case of PLLI2S is just selected  -----------------*/
+    if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
+    {
+      /* Check for Parameters */
+      assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
+      assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+
+      /* Configure the PLLI2S multiplication and division factors */
+      __HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
+    }
+
+    /* Enable the PLLI2S */
+    __HAL_RCC_PLLI2S_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
+  /*----------------------- Common configuration SAI/LTDC --------------------*/
+  /* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
+     factor is common parameters for both peripherals */
+  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
+     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
+  {
+    /* Check the PLLSAI division factors */
+    assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
+
+    /* Disable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLSAI is disabled */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+    /*---------------------------- SAI configuration -------------------------*/
+    /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
+       be added only for SAI configuration */
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
+    {
+      assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
+      assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
+
+      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
+      /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+      __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
+    }
+
+    /*---------------------------- LTDC configuration ------------------------*/
+    if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
+    {
+      assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
+      assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
+
+      /* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
+      tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+      /* PLLSAI_VCO Input  = PLL_SOURCE/PLLM */
+      /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
+      /* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
+      __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
+      /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
+      __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
+    }
+    /* Enable PLLSAI Clock */
+    __HAL_RCC_PLLSAI_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLSAI is ready */
+    while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- RTC configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable Power Clock*/
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg1;
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+  }
+  /*--------------------------------------------------------------------------*/
+
+  /*---------------------------- TIM configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the PeriphClkInit according to the internal
+  * RCC configuration registers.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         will be configured.
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg;
+
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
+
+  /* Get the PLLI2S Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+  /* Get the PLLSAI Clock configuration -----------------------------------------------*/
+  PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+  PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+  /* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
+  PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
+  PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
+  PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
+  /* Get the RTC Clock configuration -----------------------------------------------*/
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
+  * @retval Frequency in KHz
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  /* This variable used to store the I2S clock frequency (value in Hz) */
+  uint32_t frequency = 0U;
+  /* This variable used to store the VCO Input (value in Hz) */
+  uint32_t vcoinput = 0U;
+  uint32_t srcclk = 0U;
+  /* This variable used to store the VCO Output (value in Hz) */
+  uint32_t vcooutput = 0U;
+  switch (PeriphClk)
+  {
+  case RCC_PERIPHCLK_I2S:
+    {
+      /* Get the current I2S source */
+      srcclk = __HAL_RCC_GET_I2S_SOURCE();
+      switch (srcclk)
+      {
+      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+      case RCC_I2SCLKSOURCE_EXT:
+        {
+          /* Set the I2S clock to the external clock  value */
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+      case RCC_I2SCLKSOURCE_PLLI2S:
+        {
+          /* Configure the PLLI2S division factor */
+          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+
+          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+          break;
+        }
+        /* Clock not enabled for I2S*/
+      default:
+        {
+          frequency = 0U;
+          break;
+        }
+      }
+      break;
+    }
+  }
+  return frequency;
+}
+#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
+    defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+/**
+  * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
+  *         RCC_PeriphCLKInitTypeDef.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  *         contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
+  *
+  * @note   A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
+  *         the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
+  *        domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tickstart = 0U;
+  uint32_t tmpreg1 = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
+
+  /*---------------------------- I2S configuration ---------------------------*/
+  if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
+     (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
+  {
+    /* check for Parameters */
+    assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
+    assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
+#if defined(STM32F411xE)
+    assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
+#endif /* STM32F411xE */
+    /* Disable the PLLI2S */
+    __HAL_RCC_PLLI2S_DISABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is disabled */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  != RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+
+#if defined(STM32F411xE)
+    /* Configure the PLLI2S division factors */
+    /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+    /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+    __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
+#else
+    /* Configure the PLLI2S division factors */
+    /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLM) */
+    /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+    __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
+#endif /* STM32F411xE */
+
+    /* Enable the PLLI2S */
+    __HAL_RCC_PLLI2S_ENABLE();
+    /* Get tick */
+    tickstart = HAL_GetTick();
+    /* Wait till PLLI2S is ready */
+    while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY)  == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+      {
+        /* return in case of Timeout detected */
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /*---------------------------- RTC configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
+  {
+    /* Check for RTC Parameters used to output RTCCLK */
+    assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
+
+    /* Enable Power Clock*/
+    __HAL_RCC_PWR_CLK_ENABLE();
+
+    /* Enable write access to Backup domain */
+    PWR->CR |= PWR_CR_DBP;
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+
+    while((PWR->CR & PWR_CR_DBP) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+      {
+        return HAL_TIMEOUT;
+      }
+    }
+    /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+    tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
+    if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
+    {
+      /* Store the content of BDCR register before the reset of Backup Domain */
+      tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
+      /* RTC Clock selection can be changed only if the Backup Domain is reset */
+      __HAL_RCC_BACKUPRESET_FORCE();
+      __HAL_RCC_BACKUPRESET_RELEASE();
+      /* Restore the Content of BDCR register */
+      RCC->BDCR = tmpreg1;
+
+      /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
+      if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
+      {
+        /* Get tick */
+        tickstart = HAL_GetTick();
+
+        /* Wait till LSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
+  }
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+  /*---------------------------- TIM configuration ---------------------------*/
+  if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
+  {
+    __HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
+  }
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the RCC_OscInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
+  * will be configured.
+  * @retval None
+  */
+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
+{
+  uint32_t tempreg;
+
+  /* Set all possible values for the extended clock type parameter------------*/
+  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
+
+  /* Get the PLLI2S Clock configuration --------------------------------------*/
+  PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+  PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+#if defined(STM32F411xE)
+  PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
+#endif /* STM32F411xE */
+  /* Get the RTC Clock configuration -----------------------------------------*/
+  tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
+  PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
+
+#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
+  /* Get the TIM Prescaler configuration -------------------------------------*/
+  if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
+  }
+  else
+  {
+    PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
+  }
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+}
+
+/**
+  * @brief  Return the peripheral clock frequency for a given peripheral(SAI..)
+  * @note   Return 0 if peripheral clock identifier not managed by this API
+  * @param  PeriphClk Peripheral clock identifier
+  *         This parameter can be one of the following values:
+  *            @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
+  * @retval Frequency in KHz
+  */
+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
+{
+  /* This variable used to store the I2S clock frequency (value in Hz) */
+  uint32_t frequency = 0U;
+  /* This variable used to store the VCO Input (value in Hz) */
+  uint32_t vcoinput = 0U;
+  uint32_t srcclk = 0U;
+  /* This variable used to store the VCO Output (value in Hz) */
+  uint32_t vcooutput = 0U;
+  switch (PeriphClk)
+  {
+  case RCC_PERIPHCLK_I2S:
+    {
+      /* Get the current I2S source */
+      srcclk = __HAL_RCC_GET_I2S_SOURCE();
+      switch (srcclk)
+      {
+      /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+      case RCC_I2SCLKSOURCE_EXT:
+        {
+          /* Set the I2S clock to the external clock  value */
+          frequency = EXTERNAL_CLOCK_VALUE;
+          break;
+        }
+      /* Check if I2S clock selection is PLLI2S VCO output clock divided by PLLI2SR used as I2S clock */
+      case RCC_I2SCLKSOURCE_PLLI2S:
+        {
+#if defined(STM32F411xE)
+          /* Configure the PLLI2S division factor */
+          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLI2SM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
+          }
+#else
+          /* Configure the PLLI2S division factor */
+          /* PLLI2S_VCO Input  = PLL_SOURCE/PLLM */
+          if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+          else
+          {
+            /* Get the I2S source clock value */
+            vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
+          }
+#endif /* STM32F411xE */
+          /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
+          vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
+          /* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
+          frequency = (uint32_t)(vcooutput /(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28U) & (RCC_PLLI2SCFGR_PLLI2SR >> 28U)));
+          break;
+        }
+        /* Clock not enabled for I2S*/
+      default:
+        {
+          frequency = 0U;
+          break;
+        }
+      }
+      break;
+    }
+  }
+  return frequency;
+}
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE  || STM32F411xE */
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+  * @brief  Select LSE mode
+  *
+  * @note   This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx  devices.
+  *
+  * @param  Mode specifies the LSE mode.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LSE_LOWPOWER_MODE:  LSE oscillator in low power mode selection
+  *            @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
+  * @retval None
+  */
+void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_LSE_MODE(Mode));
+  if(Mode == RCC_LSE_HIGHDRIVE_MODE)
+  {
+    SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
+  }
+  else
+  {
+    CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
+  }
+}
+
+#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
+ *  @brief  Extended Clock management functions
+ *
+@verbatim   
+ ===============================================================================
+                ##### Extended clock management functions  #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the 
+    activation or deactivation of PLLI2S, PLLSAI.
+@endverbatim
+  * @{
+  */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+  * @brief  Enable PLLI2S.
+  * @param  PLLI2SInit  pointer to an RCC_PLLI2SInitTypeDef structure that
+  *         contains the configuration information for the PLLI2S
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef  *PLLI2SInit)
+{
+  uint32_t tickstart;
+
+  /* Check for parameters */
+  assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN));
+  assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR));
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+  assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SInit->PLLI2SM));
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+#if defined(RCC_PLLI2SCFGR_PLLI2SP)
+  assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP));
+#endif /* RCC_PLLI2SCFGR_PLLI2SP */
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
+  assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ));
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
+
+  /* Disable the PLLI2S */
+  __HAL_RCC_PLLI2S_DISABLE();
+
+  /* Wait till PLLI2S is disabled */
+  tickstart = HAL_GetTick();
+  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Configure the PLLI2S division factors */
+#if defined(STM32F446xx)
+  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+  /* I2SPCLK = PLLI2S_VCO / PLLI2SP */
+  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \
+                          PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+      defined(STM32F413xx) || defined(STM32F423xx)
+  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
+  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \
+                          PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+      defined(STM32F469xx) || defined(STM32F479xx)
+  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */
+  /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+  __HAL_RCC_PLLI2S_SAICLK_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+#elif defined(STM32F411xE)
+  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+  __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR);
+#else
+  /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x PLLI2SN */
+  /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+  __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR);
+#endif /* STM32F446xx */
+
+  /* Enable the PLLI2S */
+  __HAL_RCC_PLLI2S_ENABLE();
+
+  /* Wait till PLLI2S is ready */
+  tickstart = HAL_GetTick();
+  while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+ return HAL_OK;
+}
+
+/**
+  * @brief  Disable PLLI2S.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
+{
+  uint32_t tickstart;
+
+  /* Disable the PLLI2S */
+  __HAL_RCC_PLLI2S_DISABLE();
+
+  /* Wait till PLLI2S is disabled */
+  tickstart = HAL_GetTick();
+  while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
+  {
+    if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+  * @brief  Enable PLLSAI.
+  * @param  PLLSAIInit  pointer to an RCC_PLLSAIInitTypeDef structure that
+  *         contains the configuration information for the PLLSAI
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef  *PLLSAIInit)
+{
+  uint32_t tickstart;
+
+  /* Check for parameters */
+  assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN));
+  assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ));
+#if defined(RCC_PLLSAICFGR_PLLSAIM)
+  assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIInit->PLLSAIM));
+#endif /* RCC_PLLSAICFGR_PLLSAIM */
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+  assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP));
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+#if defined(RCC_PLLSAICFGR_PLLSAIR)
+  assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR));
+#endif /* RCC_PLLSAICFGR_PLLSAIR */
+
+  /* Disable the PLLSAI */
+  __HAL_RCC_PLLSAI_DISABLE();
+
+  /* Wait till PLLSAI is disabled */
+  tickstart = HAL_GetTick();
+  while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Configure the PLLSAI division factors */
+#if defined(STM32F446xx)
+  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLSAIN/PLLSAIM) */
+  /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
+  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+  /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
+  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIM, PLLSAIInit->PLLSAIN, \
+                          PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ, 0U);
+#elif defined(STM32F469xx) || defined(STM32F479xx)
+  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */
+  /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
+  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+  /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
+  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \
+                          PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
+#else
+  /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x PLLSAIN */
+  /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+  /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
+  __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
+#endif /* STM32F446xx */
+
+  /* Enable the PLLSAI */
+  __HAL_RCC_PLLSAI_ENABLE();
+
+  /* Wait till PLLSAI is ready */
+  tickstart = HAL_GetTick();
+  while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+  {
+    if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+ return HAL_OK;
+}
+
+/**
+  * @brief  Disable PLLSAI.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void)
+{
+  uint32_t tickstart;
+
+  /* Disable the PLLSAI */
+  __HAL_RCC_PLLSAI_DISABLE();
+
+  /* Wait till PLLSAI is disabled */
+  tickstart = HAL_GetTick();
+  while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+  {
+    if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+    {
+      /* return in case of Timeout detected */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  return HAL_OK;
+}
+
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+  * @}
+  */
+
+#if defined(STM32F446xx)
+/**
+  * @brief  Returns the SYSCLK frequency
+  *
+  * @note   This function implementation is valid only for STM32F446xx devices.
+  * @note   This function add the PLL/PLLR System clock source
+  *
+  * @note   The system frequency computed by this function is not the real
+  *         frequency in the chip. It is calculated based on the predefined
+  *         constant and the selected clock source:
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+  * @note     If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**)
+  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  * @note     (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *               16 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
+  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  *
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *
+  * @note   This function can be used by the user application to compute the
+  *         baudrate for the communication peripherals or configure other parameters.
+  *
+  * @note   Each time SYSCLK changes, this function must be called to update the
+  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
+  *
+  *
+  * @retval SYSCLK frequency
+  */
+uint32_t HAL_RCC_GetSysClockFreq(void)
+{
+  uint32_t pllm = 0U;
+  uint32_t pllvco = 0U;
+  uint32_t pllp = 0U;
+  uint32_t pllr = 0U;
+  uint32_t sysclockfreq = 0U;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  switch (RCC->CFGR & RCC_CFGR_SWS)
+  {
+    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
+    {
+      sysclockfreq = HSI_VALUE;
+       break;
+    }
+    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
+    {
+      sysclockfreq = HSE_VALUE;
+      break;
+    }
+    case RCC_CFGR_SWS_PLL:  /* PLL/PLLP used as system clock  source */
+    {
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+      SYSCLK = PLL_VCO / PLLP */
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+      }
+      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
+
+      sysclockfreq = pllvco/pllp;
+      break;
+    }
+    case RCC_CFGR_SWS_PLLR:  /* PLL/PLLR used as system clock  source */
+    {
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+      SYSCLK = PLL_VCO / PLLR */
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
+      }
+      pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
+
+      sysclockfreq = pllvco/pllr;
+      break;
+    }
+    default:
+    {
+      sysclockfreq = HSI_VALUE;
+      break;
+    }
+  }
+  return sysclockfreq;
+}
+#endif /* STM32F446xx */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - HSI ON and used as system clock source
+  *            - HSE, PLL, PLLI2S and PLLSAI OFF
+  *            - AHB, APB1 and APB2 prescaler set to 1.
+  *            - CSS, MCO1 and MCO2 OFF
+  *            - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks
+  *            - LSI, LSE and RTC clocks
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+  uint32_t tickstart;
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Set HSION bit to the reset value */
+  SET_BIT(RCC->CR, RCC_CR_HSION);
+
+  /* Wait till HSI is ready */
+  while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Set HSITRIM[4:0] bits to the reset value */
+  SET_BIT(RCC->CR, RCC_CR_HSITRIM_4);
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset CFGR register */
+  CLEAR_REG(RCC->CFGR);
+
+  /* Wait till clock switch is ready */
+  while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Clear HSEON, HSEBYP and CSSON bits */
+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON);
+
+  /* Wait till HSE is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Clear PLLON bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+
+  /* Wait till PLL is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+
+#if defined(RCC_PLLI2S_SUPPORT)
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset PLLI2SON bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
+
+  /* Wait till PLLI2S is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+  /* Get Start Tick */
+  tickstart = HAL_GetTick();
+
+  /* Reset PLLSAI bit */
+  CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
+
+  /* Wait till PLLSAI is disabled */
+  while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET)
+  {
+    if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+#endif /* RCC_PLLSAI_SUPPORT */
+
+  /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */
+#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \
+    defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+  RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLR_1;
+#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+  RCC->PLLCFGR = RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_3;
+#else
+  RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2;
+#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx || STM32F469xx || STM32F479xx */
+
+  /* Reset PLLI2SCFGR register to default value */
+#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \
+    defined(STM32F423xx) || defined(STM32F446xx)
+  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;
+#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
+  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1;
+#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;
+#elif defined(STM32F411xE)
+  RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1;
+#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx */
+
+  /* Reset PLLSAICFGR register */
+#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+  RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIR_1;
+#elif defined(STM32F446xx)
+  RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2;
+#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F469xx || STM32F479xx */
+
+  /* Disable all interrupts */
+  CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE);
+
+#if defined(RCC_CIR_PLLI2SRDYIE)
+  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
+#endif /* RCC_CIR_PLLI2SRDYIE */
+
+#if defined(RCC_CIR_PLLSAIRDYIE)
+  CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
+#endif /* RCC_CIR_PLLSAIRDYIE */
+
+  /* Clear all interrupt flags */
+  SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);
+
+#if defined(RCC_CIR_PLLI2SRDYC)
+  SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
+#endif /* RCC_CIR_PLLI2SRDYC */
+
+#if defined(RCC_CIR_PLLSAIRDYC)
+  SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
+#endif /* RCC_CIR_PLLSAIRDYC */
+
+  /* Clear LSION bit */
+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+
+  /* Reset all CSR flags */
+  SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+
+  /* Update the SystemCoreClock global variable */
+  SystemCoreClock = HSI_VALUE;
+
+  /* Adapt Systick interrupt period */
+  if(HAL_InitTick(uwTickPrio) != HAL_OK)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_OK;
+  }
+}
+
+#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+    defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+/**
+  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
+  *         RCC_OscInitTypeDef.
+  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
+  *         contains the configuration information for the RCC Oscillators.
+  * @note   The PLL is not disabled when used as system clock.
+  * @note   Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
+  *         supported by this API. User should request a transition to LSE Off
+  *         first and then LSE On or LSE Bypass.
+  * @note   Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
+  *         supported by this API. User should request a transition to HSE Off
+  *         first and then HSE On or HSE Bypass.
+  * @note   This function add the PLL/PLLR factor management during PLL configuration this feature
+  *         is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  uint32_t tickstart, pll_config;
+
+  /* Check Null pointer */
+  if(RCC_OscInitStruct == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
+  /*------------------------------- HSE Configuration ------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
+    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
+#if defined(STM32F446xx)
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)                                                                     ||\
+      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\
+      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+#else
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)                                                                     ||\
+      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
+#endif /* STM32F446xx */
+    {
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+      {
+        return HAL_ERROR;
+      }
+    }
+    else
+    {
+      /* Set the new HSE configuration ---------------------------------------*/
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+
+      /* Check the HSE State */
+      if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSE is bypassed or disabled */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*----------------------------- HSI Configuration --------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
+    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
+
+    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+#if defined(STM32F446xx)
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)                                                                     ||\
+      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\
+      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+#else
+    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)                                                                     ||\
+      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
+#endif /* STM32F446xx */
+    {
+      /* When HSI is used as system clock it will not disabled */
+      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
+      {
+        return HAL_ERROR;
+      }
+      /* Otherwise, just the calibration is allowed */
+      else
+      {
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+    }
+    else
+    {
+      /* Check the HSI State */
+      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
+      {
+        /* Enable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+      }
+      else
+      {
+        /* Disable the Internal High Speed oscillator (HSI). */
+        __HAL_RCC_HSI_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till HSI is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+  }
+  /*------------------------------ LSI Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+  {
+    /* Check the parameters */
+    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
+
+    /* Check the LSI State */
+    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
+    {
+      /* Enable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_ENABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Disable the Internal Low Speed oscillator (LSI). */
+      __HAL_RCC_LSI_DISABLE();
+
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSI is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  /*------------------------------ LSE Configuration -------------------------*/
+  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+  {
+    FlagStatus       pwrclkchanged = RESET;
+
+    /* Check the parameters */
+    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
+
+    /* Update LSE configuration in Backup Domain control register    */
+    /* Requires to enable write access to Backup Domain of necessary */
+    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+    {
+      __HAL_RCC_PWR_CLK_ENABLE();
+      pwrclkchanged = SET;
+    }
+
+    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+    {
+      /* Enable write access to Backup domain */
+      SET_BIT(PWR->CR, PWR_CR_DBP);
+
+      /* Wait for Backup domain Write protection disable */
+      tickstart = HAL_GetTick();
+
+      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
+      {
+        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Set the new LSE configuration -----------------------------------------*/
+    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+    /* Check the LSE State */
+    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+    else
+    {
+      /* Get Start Tick*/
+      tickstart = HAL_GetTick();
+
+      /* Wait till LSE is ready */
+      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
+      {
+        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
+        {
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Restore clock configuration if changed */
+    if(pwrclkchanged == SET)
+    {
+      __HAL_RCC_PWR_CLK_DISABLE();
+    }
+  }
+  /*-------------------------------- PLL Configuration -----------------------*/
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
+  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
+  {
+    /* Check if the PLL is used as system clock or not */
+    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
+    {
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
+      {
+        /* Check the parameters */
+        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
+        assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
+        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
+        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
+        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
+        assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
+
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+
+        /* Configure the main PLL clock source, multiplication and division factors. */
+        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \
+                                 RCC_OscInitStruct->PLL.PLLM                                                 | \
+                                 (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)                       | \
+                                 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos)        | \
+                                 (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)                       | \
+                                 (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)));
+        /* Enable the main PLL. */
+        __HAL_RCC_PLL_ENABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      else
+      {
+        /* Disable the main PLL. */
+        __HAL_RCC_PLL_DISABLE();
+
+        /* Get Start Tick*/
+        tickstart = HAL_GetTick();
+
+        /* Wait till PLL is ready */
+        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
+        {
+          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
+          {
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+    }
+    else
+    {
+      /* Check if there is a request to disable the PLL used as System clock source */
+      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
+      {
+        return HAL_ERROR;
+      }
+      else
+      {
+        /* Do not return HAL_ERROR if request repeats the current configuration */
+        pll_config = RCC->PLLCFGR;
+#if defined (RCC_PLLCFGR_PLLR)
+        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
+#else
+        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
+            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
+#endif
+        {
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configures the RCC_OscInitStruct according to the internal
+  * RCC configuration registers.
+  * @param  RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured.
+  *
+  * @note   This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
+  * @note   This function add the PLL/PLLR factor management
+  * @retval None
+  */
+void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
+{
+  /* Set all possible values for the Oscillator type parameter ---------------*/
+  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
+
+  /* Get the HSE configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
+  }
+  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
+  }
+
+  /* Get the HSI configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
+  }
+
+  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+
+  /* Get the LSE configuration -----------------------------------------------*/
+  if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
+  }
+  else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
+  }
+
+  /* Get the LSI configuration -----------------------------------------------*/
+  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
+  }
+
+  /* Get the PLL configuration -----------------------------------------------*/
+  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
+  }
+  else
+  {
+    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
+  }
+  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+  RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
+  RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+  RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos);
+  RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
+  RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
+}
+#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#endif /* HAL_RCC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c
index 36b7317..d958ad6 100644
--- a/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c
+++ b/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c
@@ -1,3751 +1,3751 @@
-/**
-  ******************************************************************************
-  * @file    stm32f4xx_hal_uart.c
-  * @author  MCD Application Team
-  * @brief   UART HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Errors functions
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * Copyright (c) 2016 STMicroelectronics.
-  * All rights reserved.
-  *
-  * This software is licensed under terms that can be found in the LICENSE file
-  * in the root directory of this software component.
-  * If no LICENSE file comes with this software, it is provided AS-IS.
-  *
-  ******************************************************************************
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The UART HAL driver can be used as follows:
-
-    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
-    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
-        (##) Enable the USARTx interface clock.
-        (##) UART pins configuration:
-            (+++) Enable the clock for the UART GPIOs.
-            (+++) Configure the UART TX/RX pins as alternate function pull-up.
-        (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
-             and HAL_UART_Receive_IT() APIs):
-            (+++) Configure the USARTx interrupt priority.
-            (+++) Enable the NVIC USART IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
-             and HAL_UART_Receive_DMA() APIs):
-            (+++) Declare a DMA handle structure for the Tx/Rx stream.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required
-                  Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx stream.
-            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete
-                  interrupt on the DMA Tx/Rx stream.
-            (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
-                  (used for last byte sending completion detection in DMA non circular mode)
-
-    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
-        flow control and Mode(Receiver/Transmitter) in the huart Init structure.
-
-    (#) For the UART asynchronous mode, initialize the UART registers by calling
-        the HAL_UART_Init() API.
-
-    (#) For the UART Half duplex mode, initialize the UART registers by calling
-        the HAL_HalfDuplex_Init() API.
-
-    (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
-
-    (#) For the Multi-Processor mode, initialize the UART registers by calling
-        the HAL_MultiProcessor_Init() API.
-
-     [..]
-       (@) The specific UART interrupts (Transmission complete interrupt,
-            RXNE interrupt and Error Interrupts) will be managed using the macros
-            __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
-            and receive process.
-
-     [..]
-       (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
-            low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
-            HAL_UART_MspInit() API.
-
-    ##### Callback registration #####
-    ==================================
-
-    [..]
-    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
-    allows the user to configure dynamically the driver callbacks.
-
-    [..]
-    Use Function HAL_UART_RegisterCallback() to register a user callback.
-    Function HAL_UART_RegisterCallback() allows to register following callbacks:
-    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
-    (+) TxCpltCallback            : Tx Complete Callback.
-    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
-    (+) RxCpltCallback            : Rx Complete Callback.
-    (+) ErrorCallback             : Error Callback.
-    (+) AbortCpltCallback         : Abort Complete Callback.
-    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
-    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
-    (+) MspInitCallback           : UART MspInit.
-    (+) MspDeInitCallback         : UART MspDeInit.
-    This function takes as parameters the HAL peripheral handle, the Callback ID
-    and a pointer to the user callback function.
-
-    [..]
-    Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
-    weak (surcharged) function.
-    HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
-    and the Callback ID.
-    This function allows to reset following callbacks:
-    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
-    (+) TxCpltCallback            : Tx Complete Callback.
-    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
-    (+) RxCpltCallback            : Rx Complete Callback.
-    (+) ErrorCallback             : Error Callback.
-    (+) AbortCpltCallback         : Abort Complete Callback.
-    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
-    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
-    (+) MspInitCallback           : UART MspInit.
-    (+) MspDeInitCallback         : UART MspDeInit.
-
-    [..]
-    For specific callback RxEventCallback, use dedicated registration/reset functions:
-    respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().
-
-    [..]
-    By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
-    all callbacks are set to the corresponding weak (surcharged) functions:
-    examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
-    Exception done for MspInit and MspDeInit functions that are respectively
-    reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
-    and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
-    If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
-    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
-
-    [..]
-    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
-    Exception done MspInit/MspDeInit that can be registered/unregistered
-    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
-    MspInit/DeInit callbacks can be used during the Init/DeInit.
-    In that case first register the MspInit/MspDeInit user callbacks
-    using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
-    or HAL_UART_Init() function.
-
-    [..]
-    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
-    not defined, the callback registration feature is not available
-    and weak (surcharged) callbacks are used.
-
-     [..]
-        Three operation modes are available within this driver :
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]
-       (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
-       (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
-
-     *** Interrupt mode IO operation ***
-     ===================================
-     [..]
-       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
-       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
-       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_RxCpltCallback
-       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_UART_ErrorCallback
-
-     *** DMA mode IO operation ***
-     ==============================
-     [..]
-       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
-       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
-       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
-       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
-       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
-            add his own code by customization of function pointer HAL_UART_RxCpltCallback
-       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
-            add his own code by customization of function pointer HAL_UART_ErrorCallback
-       (+) Pause the DMA Transfer using HAL_UART_DMAPause()
-       (+) Resume the DMA Transfer using HAL_UART_DMAResume()
-       (+) Stop the DMA Transfer using HAL_UART_DMAStop()
-
-
-    [..] This subsection also provides a set of additional functions providing enhanced reception
-    services to user. (For example, these functions allow application to handle use cases
-    where number of data to be received is unknown).
-
-    (#) Compared to standard reception services which only consider number of received
-        data elements as reception completion criteria, these functions also consider additional events
-        as triggers for updating reception status to caller :
-       (+) Detection of inactivity period (RX line has not been active for a given period).
-          (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
-               for 1 frame time, after last received byte.
-
-    (#) There are two mode of transfer:
-       (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
-           or till IDLE event occurs. Reception is handled only during function execution.
-           When function exits, no data reception could occur. HAL status and number of actually received data elements,
-           are returned by function after finishing transfer.
-       (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
-           These API's return the HAL status.
-           The end of the data processing will be indicated through the
-           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
-           The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
-           The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
-
-    (#) Blocking mode API:
-        (+) HAL_UARTEx_ReceiveToIdle()
-
-    (#) Non-Blocking mode API with Interrupt:
-        (+) HAL_UARTEx_ReceiveToIdle_IT()
-
-    (#) Non-Blocking mode API with DMA:
-        (+) HAL_UARTEx_ReceiveToIdle_DMA()
-
-
-     *** UART HAL driver macros list ***
-     =============================================
-     [..]
-       Below the list of most used macros in UART HAL driver.
-
-      (+) __HAL_UART_ENABLE: Enable the UART peripheral
-      (+) __HAL_UART_DISABLE: Disable the UART peripheral
-      (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
-      (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
-      (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
-      (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
-      (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
-
-     [..]
-       (@) You can refer to the UART HAL driver header file for more useful macros
-
-  @endverbatim
-     [..]
-       (@) Additional remark: If the parity is enabled, then the MSB bit of the data written
-           in the data register is transmitted but is changed by the parity bit.
-           Depending on the frame length defined by the M bit (8-bits or 9-bits),
-           the possible UART frame formats are as listed in the following table:
-    +-------------------------------------------------------------+
-    |   M bit |  PCE bit  |            UART frame                 |
-    |---------------------|---------------------------------------|
-    |    0    |    0      |    | SB | 8 bit data | STB |          |
-    |---------|-----------|---------------------------------------|
-    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
-    |---------|-----------|---------------------------------------|
-    |    1    |    0      |    | SB | 9 bit data | STB |          |
-    |---------|-----------|---------------------------------------|
-    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-    +-------------------------------------------------------------+
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal.h"
-
-/** @addtogroup STM32F4xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup UART UART
-  * @brief HAL UART module driver
-  * @{
-  */
-#ifdef HAL_UART_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @addtogroup UART_Private_Constants
-  * @{
-  */
-/**
-  * @}
-  */
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup UART_Private_Functions  UART Private Functions
-  * @{
-  */
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAError(DMA_HandleTypeDef *hdma);
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
-static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
-                                                     uint32_t Tickstart, uint32_t Timeout);
-static void UART_SetConfig(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-/** @defgroup UART_Exported_Functions UART Exported Functions
-  * @{
-  */
-
-/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
-  *  @brief    Initialization and Configuration functions
-  *
-@verbatim
- ===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
-    in asynchronous mode.
-      (+) For the asynchronous mode only these parameters can be configured:
-        (++) Baud Rate
-        (++) Word Length
-        (++) Stop Bit
-        (++) Parity: If the parity is enabled, then the MSB bit of the data written
-             in the data register is transmitted but is changed by the parity bit.
-             Depending on the frame length defined by the M bit (8-bits or 9-bits),
-             please refer to Reference manual for possible UART frame formats.
-        (++) Hardware flow control
-        (++) Receiver/transmitter modes
-        (++) Over Sampling Method
-    [..]
-    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
-    follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration
-    procedures (details for the procedures are available in reference manual
-    (RM0430 for STM32F4X3xx MCUs and RM0402 for STM32F412xx MCUs
-     RM0383 for STM32F411xC/E MCUs and RM0401 for STM32F410xx MCUs
-     RM0090 for STM32F4X5xx/STM32F4X7xx/STM32F429xx/STM32F439xx MCUs
-     RM0390 for STM32F446xx MCUs and RM0386 for STM32F469xx/STM32F479xx MCUs)).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the UART mode according to the specified parameters in
-  *         the UART_InitTypeDef and create the associated handle.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
-  {
-    /* The hardware flow control is available only for USART1, USART2, USART3 and USART6.
-       Except for STM32F446xx devices, that is available for USART1, USART2, USART3, USART6, UART4 and UART5.
-    */
-    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
-    assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
-  }
-  else
-  {
-    assert_param(IS_UART_INSTANCE(huart->Instance));
-  }
-  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-
-  if (huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    UART_InitCallbacksToDefault(huart);
-
-    if (huart->MspInitCallback == NULL)
-    {
-      huart->MspInitCallback = HAL_UART_MspInit;
-    }
-
-    /* Init the low level hardware */
-    huart->MspInitCallback(huart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
-
-  /* In asynchronous mode, the following bits must be kept cleared:
-     - LINEN and CLKEN bits in the USART_CR2 register,
-     - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* Initialize the UART state */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the half-duplex mode according to the specified
-  *         parameters in the UART_InitTypeDef and create the associated handle.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
-  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-
-  if (huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    UART_InitCallbacksToDefault(huart);
-
-    if (huart->MspInitCallback == NULL)
-    {
-      huart->MspInitCallback = HAL_UART_MspInit;
-    }
-
-    /* Init the low level hardware */
-    huart->MspInitCallback(huart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
-
-  /* In half-duplex mode, the following bits must be kept cleared:
-     - LINEN and CLKEN bits in the USART_CR2 register,
-     - SCEN and IREN bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
-
-  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
-  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
-
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* Initialize the UART state*/
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the LIN mode according to the specified
-  *         parameters in the UART_InitTypeDef and create the associated handle.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  BreakDetectLength Specifies the LIN break detection length.
-  *         This parameter can be one of the following values:
-  *            @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
-  *            @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
-{
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the LIN UART instance */
-  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
-
-  /* Check the Break detection length parameter */
-  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
-  assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
-  assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
-
-  if (huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    UART_InitCallbacksToDefault(huart);
-
-    if (huart->MspInitCallback == NULL)
-    {
-      huart->MspInitCallback = HAL_UART_MspInit;
-    }
-
-    /* Init the low level hardware */
-    huart->MspInitCallback(huart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
-
-  /* In LIN mode, the following bits must be kept cleared:
-     - CLKEN bits in the USART_CR2 register,
-     - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
-
-  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
-  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
-
-  /* Set the USART LIN Break detection length. */
-  CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL);
-  SET_BIT(huart->Instance->CR2, BreakDetectLength);
-
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* Initialize the UART state*/
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the Multi-Processor mode according to the specified
-  *         parameters in the UART_InitTypeDef and create the associated handle.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  Address USART address
-  * @param  WakeUpMethod specifies the USART wake-up method.
-  *         This parameter can be one of the following values:
-  *            @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
-  *            @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
-{
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-
-  /* Check the Address & wake up method parameters */
-  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
-  assert_param(IS_UART_ADDRESS(Address));
-  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
-
-  if (huart->gState == HAL_UART_STATE_RESET)
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    UART_InitCallbacksToDefault(huart);
-
-    if (huart->MspInitCallback == NULL)
-    {
-      huart->MspInitCallback = HAL_UART_MspInit;
-    }
-
-    /* Init the low level hardware */
-    huart->MspInitCallback(huart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
-
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
-
-  /* In Multi-Processor mode, the following bits must be kept cleared:
-     - LINEN and CLKEN bits in the USART_CR2 register,
-     - SCEN, HDSEL and IREN  bits in the USART_CR3 register */
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
-
-  /* Set the USART address node */
-  CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD);
-  SET_BIT(huart->Instance->CR2, Address);
-
-  /* Set the wake up method by setting the WAKE bit in the CR1 register */
-  CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE);
-  SET_BIT(huart->Instance->CR1, WakeUpMethod);
-
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
-
-  /* Initialize the UART state */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the UART peripheral.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if (huart == NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  if (huart->MspDeInitCallback == NULL)
-  {
-    huart->MspDeInitCallback = HAL_UART_MspDeInit;
-  }
-  /* DeInit the low level hardware */
-  huart->MspDeInitCallback(huart);
-#else
-  /* DeInit the low level hardware */
-  HAL_UART_MspDeInit(huart);
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->gState = HAL_UART_STATE_RESET;
-  huart->RxState = HAL_UART_STATE_RESET;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  /* Process Unlock */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  UART MSP Init.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  UART MSP DeInit.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_MspDeInit could be implemented in the user file
-   */
-}
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-/**
-  * @brief  Register a User UART Callback
-  *         To be used instead of the weak predefined callback
-  * @param  huart uart handle
-  * @param  CallbackID ID of the callback to be registered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
-  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
-  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
-  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
-  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @param  pCallback pointer to the Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
-                                            pUART_CallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    /* Update the error code */
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-  /* Process locked */
-  __HAL_LOCK(huart);
-
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    switch (CallbackID)
-    {
-      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
-        huart->TxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_TX_COMPLETE_CB_ID :
-        huart->TxCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
-        huart->RxHalfCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_RX_COMPLETE_CB_ID :
-        huart->RxCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_ERROR_CB_ID :
-        huart->ErrorCallback = pCallback;
-        break;
-
-      case HAL_UART_ABORT_COMPLETE_CB_ID :
-        huart->AbortCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
-        huart->AbortTransmitCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
-        huart->AbortReceiveCpltCallback = pCallback;
-        break;
-
-      case HAL_UART_MSPINIT_CB_ID :
-        huart->MspInitCallback = pCallback;
-        break;
-
-      case HAL_UART_MSPDEINIT_CB_ID :
-        huart->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (huart->gState == HAL_UART_STATE_RESET)
-  {
-    switch (CallbackID)
-    {
-      case HAL_UART_MSPINIT_CB_ID :
-        huart->MspInitCallback = pCallback;
-        break;
-
-      case HAL_UART_MSPDEINIT_CB_ID :
-        huart->MspDeInitCallback = pCallback;
-        break;
-
-      default :
-        /* Update the error code */
-        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(huart);
-
-  return status;
-}
-
-/**
-  * @brief  Unregister an UART Callback
-  *         UART callaback is redirected to the weak predefined callback
-  * @param  huart uart handle
-  * @param  CallbackID ID of the callback to be unregistered
-  *         This parameter can be one of the following values:
-  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
-  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
-  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
-  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
-  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
-  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
-  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
-  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
-  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
-  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(huart);
-
-  if (HAL_UART_STATE_READY == huart->gState)
-  {
-    switch (CallbackID)
-    {
-      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
-        huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
-        break;
-
-      case HAL_UART_TX_COMPLETE_CB_ID :
-        huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
-        break;
-
-      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
-        huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
-        break;
-
-      case HAL_UART_RX_COMPLETE_CB_ID :
-        huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
-        break;
-
-      case HAL_UART_ERROR_CB_ID :
-        huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback             */
-        break;
-
-      case HAL_UART_ABORT_COMPLETE_CB_ID :
-        huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
-        break;
-
-      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
-        huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
-        break;
-
-      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
-        huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
-        break;
-
-      case HAL_UART_MSPINIT_CB_ID :
-        huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback           */
-        break;
-
-      case HAL_UART_MSPDEINIT_CB_ID :
-        huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
-        break;
-
-      default :
-        /* Update the error code */
-        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else if (HAL_UART_STATE_RESET == huart->gState)
-  {
-    switch (CallbackID)
-    {
-      case HAL_UART_MSPINIT_CB_ID :
-        huart->MspInitCallback = HAL_UART_MspInit;
-        break;
-
-      case HAL_UART_MSPDEINIT_CB_ID :
-        huart->MspDeInitCallback = HAL_UART_MspDeInit;
-        break;
-
-      default :
-        /* Update the error code */
-        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-        /* Return error status */
-        status =  HAL_ERROR;
-        break;
-    }
-  }
-  else
-  {
-    /* Update the error code */
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    /* Return error status */
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(huart);
-
-  return status;
-}
-
-/**
-  * @brief  Register a User UART Rx Event Callback
-  *         To be used instead of the weak predefined callback
-  * @param  huart     Uart handle
-  * @param  pCallback Pointer to the Rx Event Callback function
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  if (pCallback == NULL)
-  {
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    return HAL_ERROR;
-  }
-
-  /* Process locked */
-  __HAL_LOCK(huart);
-
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    huart->RxEventCallback = pCallback;
-  }
-  else
-  {
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(huart);
-
-  return status;
-}
-
-/**
-  * @brief  UnRegister the UART Rx Event Callback
-  *         UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback
-  * @param  huart     Uart handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process locked */
-  __HAL_LOCK(huart);
-
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback  */
-  }
-  else
-  {
-    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
-
-    status =  HAL_ERROR;
-  }
-
-  /* Release Lock */
-  __HAL_UNLOCK(huart);
-  return status;
-}
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group2 IO operation functions
-  *  @brief UART Transmit and Receive functions
-  *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    This subsection provides a set of functions allowing to manage the UART asynchronous
-    and Half duplex data transfers.
-
-    (#) There are two modes of transfer:
-       (+) Blocking mode: The communication is performed in polling mode.
-           The HAL status of all data processing is returned by the same function
-           after finishing transfer.
-       (+) Non-Blocking mode: The communication is performed using Interrupts
-           or DMA, these API's return the HAL status.
-           The end of the data processing will be indicated through the
-           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
-           using DMA mode.
-           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
-           will be executed respectively at the end of the transmit or receive process
-           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected.
-
-    (#) Blocking mode API's are :
-        (+) HAL_UART_Transmit()
-        (+) HAL_UART_Receive()
-
-    (#) Non-Blocking mode API's with Interrupt are :
-        (+) HAL_UART_Transmit_IT()
-        (+) HAL_UART_Receive_IT()
-        (+) HAL_UART_IRQHandler()
-
-    (#) Non-Blocking mode API's with DMA are :
-        (+) HAL_UART_Transmit_DMA()
-        (+) HAL_UART_Receive_DMA()
-        (+) HAL_UART_DMAPause()
-        (+) HAL_UART_DMAResume()
-        (+) HAL_UART_DMAStop()
-
-    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
-        (+) HAL_UART_TxHalfCpltCallback()
-        (+) HAL_UART_TxCpltCallback()
-        (+) HAL_UART_RxHalfCpltCallback()
-        (+) HAL_UART_RxCpltCallback()
-        (+) HAL_UART_ErrorCallback()
-
-    (#) Non-Blocking mode transfers could be aborted using Abort API's :
-        (+) HAL_UART_Abort()
-        (+) HAL_UART_AbortTransmit()
-        (+) HAL_UART_AbortReceive()
-        (+) HAL_UART_Abort_IT()
-        (+) HAL_UART_AbortTransmit_IT()
-        (+) HAL_UART_AbortReceive_IT()
-
-    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
-        (+) HAL_UART_AbortCpltCallback()
-        (+) HAL_UART_AbortTransmitCpltCallback()
-        (+) HAL_UART_AbortReceiveCpltCallback()
-
-    (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services:
-        (+) HAL_UARTEx_RxEventCallback()
-
-    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
-        Errors are handled as follows :
-       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
-           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
-           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
-           and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
-           If user wants to abort it, Abort services should be called by user.
-       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
-           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
-           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
-
-    -@- In the Half duplex communication, it is forbidden to run the transmit
-        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sends an amount of data in blocking mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 provided through pData.
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART module.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be sent
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  const uint8_t  *pdata8bits;
-  const uint16_t *pdata16bits;
-  uint32_t tickstart = 0U;
-
-  /* Check that a Tx process is not already ongoing */
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->gState = HAL_UART_STATE_BUSY_TX;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-
-    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      pdata8bits  = NULL;
-      pdata16bits = (const uint16_t *) pData;
-    }
-    else
-    {
-      pdata8bits  = pData;
-      pdata16bits = NULL;
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    while (huart->TxXferCount > 0U)
-    {
-      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      if (pdata8bits == NULL)
-      {
-        huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
-        pdata16bits++;
-      }
-      else
-      {
-        huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
-        pdata8bits++;
-      }
-      huart->TxXferCount--;
-    }
-
-    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* At end of Tx process, restore huart->gState to Ready */
-    huart->gState = HAL_UART_STATE_READY;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives an amount of data in blocking mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the received data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 available through pData.
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART module.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be received.
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint8_t  *pdata8bits;
-  uint16_t *pdata16bits;
-  uint32_t tickstart = 0U;
-
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->RxState = HAL_UART_STATE_BUSY_RX;
-    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    huart->RxXferSize = Size;
-    huart->RxXferCount = Size;
-
-    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      pdata8bits  = NULL;
-      pdata16bits = (uint16_t *) pData;
-    }
-    else
-    {
-      pdata8bits  = pData;
-      pdata16bits = NULL;
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    /* Check the remain data to be received */
-    while (huart->RxXferCount > 0U)
-    {
-      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      if (pdata8bits == NULL)
-      {
-        *pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF);
-        pdata16bits++;
-      }
-      else
-      {
-        if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
-        {
-          *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
-        }
-        else
-        {
-          *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
-        }
-        pdata8bits++;
-      }
-      huart->RxXferCount--;
-    }
-
-    /* At end of Rx process, restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 provided through pData.
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART module.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Tx process is not already ongoing */
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->pTxBuffPtr = pData;
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->gState = HAL_UART_STATE_BUSY_TX;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    /* Enable the UART Transmit data register empty Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the received data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 available through pData.
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART module.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    /* Set Reception type to Standard reception */
-    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-    return (UART_Start_Receive_IT(huart, pData, Size));
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sends an amount of data in DMA mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 provided through pData.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
-{
-  const uint32_t *tmp;
-
-  /* Check that a Tx process is not already ongoing */
-  if (huart->gState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->pTxBuffPtr = pData;
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->gState = HAL_UART_STATE_BUSY_TX;
-
-    /* Set the UART DMA transfer complete callback */
-    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
-
-    /* Set the UART DMA Half transfer complete callback */
-    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
-
-    /* Set the DMA error callback */
-    huart->hdmatx->XferErrorCallback = UART_DMAError;
-
-    /* Set the DMA abort callback */
-    huart->hdmatx->XferAbortCallback = NULL;
-
-    /* Enable the UART transmit DMA stream */
-    tmp = (const uint32_t *)&pData;
-    HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size);
-
-    /* Clear the TC flag in the SR register by writing 0 to it */
-    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the UART CR3 register */
-    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives an amount of data in DMA mode.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
-  *         the received data is handled as a set of u16. In this case, Size must indicate the number
-  *         of u16 available through pData.
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART module.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be received.
-  * @note   When the UART parity is enabled (PCE = 1) the received data contains the parity bit.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    /* Set Reception type to Standard reception */
-    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-    return (UART_Start_Receive_DMA(huart, pData, Size));
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Pauses the DMA Transfer.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
-{
-  uint32_t dmarequest = 0x00U;
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
-  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
-  {
-    /* Disable the UART DMA Tx request */
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-  }
-
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
-  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
-  {
-    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-    /* Disable the UART DMA Rx request */
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Resumes the DMA Transfer.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  if (huart->gState == HAL_UART_STATE_BUSY_TX)
-  {
-    /* Enable the UART DMA Tx request */
-    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-  }
-
-  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
-  {
-    /* Clear the Overrun flag before resuming the Rx transfer*/
-    __HAL_UART_CLEAR_OREFLAG(huart);
-
-    /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    if (huart->Init.Parity != UART_PARITY_NONE)
-    {
-      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    }
-    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-    /* Enable the UART DMA Rx request */
-    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Stops the DMA Transfer.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
-{
-  uint32_t dmarequest = 0x00U;
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
-     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
-     */
-
-  /* Stop UART DMA Tx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
-  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx stream */
-    if (huart->hdmatx != NULL)
-    {
-      HAL_DMA_Abort(huart->hdmatx);
-    }
-    UART_EndTxTransfer(huart);
-  }
-
-  /* Stop UART DMA Rx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
-  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx stream */
-    if (huart->hdmarx != NULL)
-    {
-      HAL_DMA_Abort(huart->hdmarx);
-    }
-    UART_EndRxTransfer(huart);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.
-  * @note   HAL_OK is returned if reception is completed (expected number of data has been received)
-  *         or if reception is stopped after IDLE event (less than the expected number of data has been received)
-  *         In this case, RxLen output parameter indicates number of data available in reception buffer.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01),
-  *         the received data is handled as a set of uint16_t. In this case, Size must indicate the number
-  *         of uint16_t available through pData.
-  * @param huart   UART handle.
-  * @param pData   Pointer to data buffer (uint8_t or uint16_t data elements).
-  * @param Size    Amount of data elements (uint8_t or uint16_t) to be received.
-  * @param RxLen   Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event)
-  * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
-                                           uint32_t Timeout)
-{
-  uint8_t  *pdata8bits;
-  uint16_t *pdata16bits;
-  uint32_t tickstart;
-
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return  HAL_ERROR;
-    }
-
-    __HAL_LOCK(huart);
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    huart->RxState = HAL_UART_STATE_BUSY_RX;
-    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
-
-    huart->RxXferSize  = Size;
-    huart->RxXferCount = Size;
-
-    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      pdata8bits  = NULL;
-      pdata16bits = (uint16_t *) pData;
-    }
-    else
-    {
-      pdata8bits  = pData;
-      pdata16bits = NULL;
-    }
-
-    __HAL_UNLOCK(huart);
-
-    /* Initialize output number of received elements */
-    *RxLen = 0U;
-
-    /* as long as data have to be received */
-    while (huart->RxXferCount > 0U)
-    {
-      /* Check if IDLE flag is set */
-      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
-      {
-        /* Clear IDLE flag in ISR */
-        __HAL_UART_CLEAR_IDLEFLAG(huart);
-
-        /* If Set, but no data ever received, clear flag without exiting loop */
-        /* If Set, and data has already been received, this means Idle Event is valid : End reception */
-        if (*RxLen > 0U)
-        {
-          huart->RxState = HAL_UART_STATE_READY;
-
-          return HAL_OK;
-        }
-      }
-
-      /* Check if RXNE flag is set */
-      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
-      {
-        if (pdata8bits == NULL)
-        {
-          *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
-          pdata16bits++;
-        }
-        else
-        {
-          if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
-          {
-            *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
-          }
-          else
-          {
-            *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
-          }
-
-          pdata8bits++;
-        }
-        /* Increment number of received elements */
-        *RxLen += 1U;
-        huart->RxXferCount--;
-      }
-
-      /* Check for the Timeout */
-      if (Timeout != HAL_MAX_DELAY)
-      {
-        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
-        {
-          huart->RxState = HAL_UART_STATE_READY;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-
-    /* Set number of received elements in output parameter : RxLen */
-    *RxLen = huart->RxXferSize - huart->RxXferCount;
-    /* At end of Rx process, restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.
-  * @note   Reception is initiated by this function call. Further progress of reception is achieved thanks
-  *         to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
-  *         number of received data elements.
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01),
-  *         the received data is handled as a set of uint16_t. In this case, Size must indicate the number
-  *         of uint16_t available through pData.
-  * @param huart UART handle.
-  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
-  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef status;
-
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    __HAL_LOCK(huart);
-
-    /* Set Reception type to reception till IDLE Event*/
-    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
-
-    status =  UART_Start_Receive_IT(huart, pData, Size);
-
-    /* Check Rx process has been successfully started */
-    if (status == HAL_OK)
-    {
-      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-      {
-        __HAL_UART_CLEAR_IDLEFLAG(huart);
-        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-      }
-      else
-      {
-        /* In case of errors already pending when reception is started,
-           Interrupts may have already been raised and lead to reception abortion.
-           (Overrun error for instance).
-           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
-        status = HAL_ERROR;
-      }
-    }
-
-    return status;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.
-  * @note   Reception is initiated by this function call. Further progress of reception is achieved thanks
-  *         to DMA services, transferring automatically received data elements in user reception buffer and
-  *         calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
-  *         reception phase as ended. In all cases, callback execution will indicate number of received data elements.
-  * @note   When the UART parity is enabled (PCE = 1), the received data contain
-  *         the parity bit (MSB position).
-  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01),
-  *         the received data is handled as a set of uint16_t. In this case, Size must indicate the number
-  *         of uint16_t available through pData.
-  * @param huart UART handle.
-  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
-  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  HAL_StatusTypeDef status;
-
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
-  {
-    if ((pData == NULL) || (Size == 0U))
-    {
-      return HAL_ERROR;
-    }
-
-    __HAL_LOCK(huart);
-
-    /* Set Reception type to reception till IDLE Event*/
-    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
-
-    status =  UART_Start_Receive_DMA(huart, pData, Size);
-
-    /* Check Rx process has been successfully started */
-    if (status == HAL_OK)
-    {
-      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-      {
-        __HAL_UART_CLEAR_IDLEFLAG(huart);
-        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-      }
-      else
-      {
-        /* In case of errors already pending when reception is started,
-           Interrupts may have already been raised and lead to reception abortion.
-           (Overrun error for instance).
-           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
-        status = HAL_ERROR;
-      }
-    }
-
-    return status;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Abort ongoing transfers (blocking mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Tx and Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
-{
-  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
-  }
-
-  /* Disable the UART DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx stream: use blocking DMA Abort API (no callback) */
-    if (huart->hdmatx != NULL)
-    {
-      /* Set the UART DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      huart->hdmatx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          huart->ErrorCode = HAL_UART_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Disable the UART DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx stream: use blocking DMA Abort API (no callback) */
-    if (huart->hdmarx != NULL)
-    {
-      /* Set the UART DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      huart->hdmarx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          huart->ErrorCode = HAL_UART_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Reset Tx and Rx transfer counters */
-  huart->TxXferCount = 0x00U;
-  huart->RxXferCount = 0x00U;
-
-  /* Reset ErrorCode */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-
-  /* Restore huart->RxState and huart->gState to Ready */
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->gState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Transmit transfer (blocking mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Tx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* Disable the UART DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */
-    if (huart->hdmatx != NULL)
-    {
-      /* Set the UART DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      huart->hdmatx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          huart->ErrorCode = HAL_UART_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Reset Tx transfer counter */
-  huart->TxXferCount = 0x00U;
-
-  /* Restore huart->gState to Ready */
-  huart->gState = HAL_UART_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Receive transfer (blocking mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
-  }
-
-  /* Disable the UART DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */
-    if (huart->hdmarx != NULL)
-    {
-      /* Set the UART DMA Abort callback to Null.
-         No call back execution at end of DMA abort procedure */
-      huart->hdmarx->XferAbortCallback = NULL;
-
-      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
-      {
-        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
-        {
-          /* Set error code to DMA */
-          huart->ErrorCode = HAL_UART_ERROR_DMA;
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-
-  /* Reset Rx transfer counter */
-  huart->RxXferCount = 0x00U;
-
-  /* Restore huart->RxState to Ready */
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing transfers (Interrupt mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Tx and Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
-{
-  uint32_t AbortCplt = 0x01U;
-
-  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
-  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
-  }
-
-  /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
-     before any call to DMA Abort functions */
-  /* DMA Tx Handle is valid */
-  if (huart->hdmatx != NULL)
-  {
-    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
-    {
-      huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
-    }
-    else
-    {
-      huart->hdmatx->XferAbortCallback = NULL;
-    }
-  }
-  /* DMA Rx Handle is valid */
-  if (huart->hdmarx != NULL)
-  {
-    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
-       Otherwise, set it to NULL */
-    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-    {
-      huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
-    }
-    else
-    {
-      huart->hdmarx->XferAbortCallback = NULL;
-    }
-  }
-
-  /* Disable the UART DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
-  {
-    /* Disable DMA Tx at UART level */
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx stream : use non blocking DMA Abort API (callback) */
-    if (huart->hdmatx != NULL)
-    {
-      /* UART Tx DMA Abort callback has already been initialised :
-         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA TX */
-      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
-      {
-        huart->hdmatx->XferAbortCallback = NULL;
-      }
-      else
-      {
-        AbortCplt = 0x00U;
-      }
-    }
-  }
-
-  /* Disable the UART DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx stream : use non blocking DMA Abort API (callback) */
-    if (huart->hdmarx != NULL)
-    {
-      /* UART Rx DMA Abort callback has already been initialised :
-         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-
-      /* Abort DMA RX */
-      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
-      {
-        huart->hdmarx->XferAbortCallback = NULL;
-        AbortCplt = 0x01U;
-      }
-      else
-      {
-        AbortCplt = 0x00U;
-      }
-    }
-  }
-
-  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
-  if (AbortCplt == 0x01U)
-  {
-    /* Reset Tx and Rx transfer counters */
-    huart->TxXferCount = 0x00U;
-    huart->RxXferCount = 0x00U;
-
-    /* Reset ErrorCode */
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-
-    /* Restore huart->gState and huart->RxState to Ready */
-    huart->gState  = HAL_UART_STATE_READY;
-    huart->RxState = HAL_UART_STATE_READY;
-    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort complete callback */
-    huart->AbortCpltCallback(huart);
-#else
-    /* Call legacy weak Abort complete callback */
-    HAL_UART_AbortCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Tx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* Disable the UART DMA Tx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */
-    if (huart->hdmatx != NULL)
-    {
-      /* Set the UART DMA Abort callback :
-         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-      huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
-
-      /* Abort DMA TX */
-      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
-      {
-        /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
-        huart->hdmatx->XferAbortCallback(huart->hdmatx);
-      }
-    }
-    else
-    {
-      /* Reset Tx transfer counter */
-      huart->TxXferCount = 0x00U;
-
-      /* Restore huart->gState to Ready */
-      huart->gState = HAL_UART_STATE_READY;
-
-      /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-      /* Call registered Abort Transmit Complete Callback */
-      huart->AbortTransmitCpltCallback(huart);
-#else
-      /* Call legacy weak Abort Transmit Complete Callback */
-      HAL_UART_AbortTransmitCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-    }
-  }
-  else
-  {
-    /* Reset Tx transfer counter */
-    huart->TxXferCount = 0x00U;
-
-    /* Restore huart->gState to Ready */
-    huart->gState = HAL_UART_STATE_READY;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort Transmit Complete Callback */
-    huart->AbortTransmitCpltCallback(huart);
-#else
-    /* Call legacy weak Abort Transmit Complete Callback */
-    HAL_UART_AbortTransmitCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Abort ongoing Receive transfer (Interrupt mode).
-  * @param  huart UART handle.
-  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
-  *         This procedure performs following operations :
-  *           - Disable UART Interrupts (Rx)
-  *           - Disable the DMA transfer in the peripheral register (if enabled)
-  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
-  *           - Set handle State to READY
-  *           - At abort completion, call user abort complete callback
-  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
-  *         considered as completed only when user abort complete callback is executed (not when exiting function).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
-  }
-
-  /* Disable the UART DMA Rx request if enabled */
-  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */
-    if (huart->hdmarx != NULL)
-    {
-      /* Set the UART DMA Abort callback :
-         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
-      huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
-
-      /* Abort DMA RX */
-      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
-      {
-        /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
-        huart->hdmarx->XferAbortCallback(huart->hdmarx);
-      }
-    }
-    else
-    {
-      /* Reset Rx transfer counter */
-      huart->RxXferCount = 0x00U;
-
-      /* Restore huart->RxState to Ready */
-      huart->RxState = HAL_UART_STATE_READY;
-      huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-      /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-      /* Call registered Abort Receive Complete Callback */
-      huart->AbortReceiveCpltCallback(huart);
-#else
-      /* Call legacy weak Abort Receive Complete Callback */
-      HAL_UART_AbortReceiveCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-    }
-  }
-  else
-  {
-    /* Reset Rx transfer counter */
-    huart->RxXferCount = 0x00U;
-
-    /* Restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
-    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-    /* As no DMA to be aborted, call directly user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /* Call registered Abort Receive Complete Callback */
-    huart->AbortReceiveCpltCallback(huart);
-#else
-    /* Call legacy weak Abort Receive Complete Callback */
-    HAL_UART_AbortReceiveCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles UART interrupt request.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
-{
-  uint32_t isrflags   = READ_REG(huart->Instance->SR);
-  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
-  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
-  uint32_t errorflags = 0x00U;
-  uint32_t dmarequest = 0x00U;
-
-  /* If no error occurs */
-  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
-  if (errorflags == RESET)
-  {
-    /* UART in mode Receiver -------------------------------------------------*/
-    if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
-    {
-      UART_Receive_IT(huart);
-      return;
-    }
-  }
-
-  /* If some errors occur */
-  if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET)
-                                || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
-  {
-    /* UART parity error interrupt occurred ----------------------------------*/
-    if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
-    {
-      huart->ErrorCode |= HAL_UART_ERROR_PE;
-    }
-
-    /* UART noise error interrupt occurred -----------------------------------*/
-    if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
-    {
-      huart->ErrorCode |= HAL_UART_ERROR_NE;
-    }
-
-    /* UART frame error interrupt occurred -----------------------------------*/
-    if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
-    {
-      huart->ErrorCode |= HAL_UART_ERROR_FE;
-    }
-
-    /* UART Over-Run interrupt occurred --------------------------------------*/
-    if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET)
-                                                 || ((cr3its & USART_CR3_EIE) != RESET)))
-    {
-      huart->ErrorCode |= HAL_UART_ERROR_ORE;
-    }
-
-    /* Call UART Error Call back function if need be --------------------------*/
-    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
-    {
-      /* UART in mode Receiver -----------------------------------------------*/
-      if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
-      {
-        UART_Receive_IT(huart);
-      }
-
-      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
-         consider error as blocking */
-      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
-      if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
-      {
-        /* Blocking error : transfer is aborted
-           Set the UART state ready to be able to start again the process,
-           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
-        UART_EndRxTransfer(huart);
-
-        /* Disable the UART DMA Rx request if enabled */
-        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-        {
-          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-          /* Abort the UART DMA Rx stream */
-          if (huart->hdmarx != NULL)
-          {
-            /* Set the UART DMA Abort callback :
-               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
-            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
-            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
-            {
-              /* Call Directly XferAbortCallback function in case of error */
-              huart->hdmarx->XferAbortCallback(huart->hdmarx);
-            }
-          }
-          else
-          {
-            /* Call user error callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-            /*Call registered error callback*/
-            huart->ErrorCallback(huart);
-#else
-            /*Call legacy weak error callback*/
-            HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-          }
-        }
-        else
-        {
-          /* Call user error callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-          /*Call registered error callback*/
-          huart->ErrorCallback(huart);
-#else
-          /*Call legacy weak error callback*/
-          HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-        }
-      }
-      else
-      {
-        /* Non Blocking error : transfer could go on.
-           Error is notified to user through user error callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-        /*Call registered error callback*/
-        huart->ErrorCallback(huart);
-#else
-        /*Call legacy weak error callback*/
-        HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-        huart->ErrorCode = HAL_UART_ERROR_NONE;
-      }
-    }
-    return;
-  } /* End if some error occurs */
-
-  /* Check current reception Mode :
-     If Reception till IDLE event has been selected : */
-  if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-      && ((isrflags & USART_SR_IDLE) != 0U)
-      && ((cr1its & USART_SR_IDLE) != 0U))
-  {
-    __HAL_UART_CLEAR_IDLEFLAG(huart);
-
-    /* Check if DMA mode is enabled in UART */
-    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
-    {
-      /* DMA mode enabled */
-      /* Check received length : If all expected data are received, do nothing,
-         (DMA cplt callback will be called).
-         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
-      uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
-      if ((nb_remaining_rx_data > 0U)
-          && (nb_remaining_rx_data < huart->RxXferSize))
-      {
-        /* Reception is not complete */
-        huart->RxXferCount = nb_remaining_rx_data;
-
-        /* In Normal mode, end DMA xfer and HAL UART Rx process*/
-        if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
-        {
-          /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-          /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
-             in the UART CR3 register */
-          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-          /* At end of Rx process, restore huart->RxState to Ready */
-          huart->RxState = HAL_UART_STATE_READY;
-          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-
-          /* Last bytes received, so no need as the abort is immediate */
-          (void)HAL_DMA_Abort(huart->hdmarx);
-        }
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-        /*Call registered Rx Event callback*/
-        huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
-#else
-        /*Call legacy weak Rx Event callback*/
-        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-      }
-      return;
-    }
-    else
-    {
-      /* DMA mode not enabled */
-      /* Check received length : If all expected data are received, do nothing.
-         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
-      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
-      if ((huart->RxXferCount > 0U)
-          && (nb_rx_data > 0U))
-      {
-        /* Disable the UART Parity Error Interrupt and RXNE interrupts */
-        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-
-        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-        /* Rx process is completed, restore huart->RxState to Ready */
-        huart->RxState = HAL_UART_STATE_READY;
-        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-        /*Call registered Rx complete callback*/
-        huart->RxEventCallback(huart, nb_rx_data);
-#else
-        /*Call legacy weak Rx Event callback*/
-        HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-      }
-      return;
-    }
-  }
-
-  /* UART in mode Transmitter ------------------------------------------------*/
-  if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
-  {
-    UART_Transmit_IT(huart);
-    return;
-  }
-
-  /* UART in mode Transmitter end --------------------------------------------*/
-  if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
-  {
-    UART_EndTransmit_IT(huart);
-    return;
-  }
-}
-
-/**
-  * @brief  Tx Transfer completed callbacks.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_TxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx Half Transfer completed callbacks.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_TxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Transfer completed callbacks.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Half Transfer completed callbacks.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_RxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  UART error callbacks.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  UART Abort Complete callback.
-  * @param  huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_AbortCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  UART Abort Complete callback.
-  * @param  huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  UART Abort Receive Complete callback.
-  * @param  huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Reception Event Callback (Rx event notification called after use of advanced reception service).
-  * @param  huart UART handle
-  * @param  Size  Number of data available in application reception buffer (indicates a position in
-  *               reception buffer until which, data are available)
-  * @retval None
-  */
-__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
-{
-  /* Prevent unused argument(s) compilation warning */
-  UNUSED(huart);
-  UNUSED(Size);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UARTEx_RxEventCallback can be implemented in the user file.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
-  *  @brief   UART control functions
-  *
-@verbatim
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to control the UART:
-    (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
-    (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode.
-    (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.
-    (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode
-    (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmits break characters.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
-{
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Send break characters */
-  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_SBK);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enters the UART in mute mode.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
-{
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
-  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RWU);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Exits the UART mute mode: wake up software.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
-{
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables the UART transmitter and disables the UART receiver.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
-{
-  uint32_t tmpreg = 0x00U;
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = huart->Instance->CR1;
-
-  /* Clear TE and RE bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
-
-  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
-  tmpreg |= (uint32_t)USART_CR1_TE;
-
-  /* Write to USART CR1 */
-  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables the UART receiver and disables the UART transmitter.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
-{
-  uint32_t tmpreg = 0x00U;
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-
-  huart->gState = HAL_UART_STATE_BUSY;
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = huart->Instance->CR1;
-
-  /* Clear TE and RE bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
-
-  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
-  tmpreg |= (uint32_t)USART_CR1_RE;
-
-  /* Write to USART CR1 */
-  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
-
-  huart->gState = HAL_UART_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
-  *  @brief   UART State and Errors functions
-  *
-@verbatim
-  ==============================================================================
-                 ##### Peripheral State and Errors functions #####
-  ==============================================================================
- [..]
-   This subsection provides a set of functions allowing to return the State of
-   UART communication process, return Peripheral Errors occurred during communication
-   process
-   (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
-   (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the UART state.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL state
-  */
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
-{
-  uint32_t temp1 = 0x00U, temp2 = 0x00U;
-  temp1 = huart->gState;
-  temp2 = huart->RxState;
-
-  return (HAL_UART_StateTypeDef)(temp1 | temp2);
-}
-
-/**
-  * @brief  Return the UART error code
-  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
-  *               the configuration information for the specified UART.
-  * @retval UART Error Code
-  */
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
-{
-  return huart->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Private_Functions UART Private Functions
-  * @{
-  */
-
-/**
-  * @brief  Initialize the callbacks to their default values.
-  * @param  huart UART handle.
-  * @retval none
-  */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
-{
-  /* Init the UART Callback settings */
-  huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
-  huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
-  huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
-  huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
-  huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */
-  huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
-  huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
-  huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
-  huart->RxEventCallback           = HAL_UARTEx_RxEventCallback;         /* Legacy weak RxEventCallback           */
-
-}
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-/**
-  * @brief  DMA UART transmit process complete callback.
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  /* DMA Normal mode*/
-  if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
-  {
-    huart->TxXferCount = 0x00U;
-
-    /* Disable the DMA transfer for transmit request by setting the DMAT bit
-       in the UART CR3 register */
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Enable the UART Transmit Complete Interrupt */
-    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
-
-  }
-  /* DMA Circular mode */
-  else
-  {
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Tx complete callback*/
-    huart->TxCpltCallback(huart);
-#else
-    /*Call legacy weak Tx complete callback*/
-    HAL_UART_TxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief DMA UART transmit process half complete callback
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /*Call registered Tx complete callback*/
-  huart->TxHalfCpltCallback(huart);
-#else
-  /*Call legacy weak Tx complete callback*/
-  HAL_UART_TxHalfCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA UART receive process complete callback.
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  /* DMA Normal mode*/
-  if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
-  {
-    huart->RxXferCount = 0U;
-
-    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-    /* Disable the DMA transfer for the receiver request by setting the DMAR bit
-       in the UART CR3 register */
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-    /* At end of Rx process, restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
-
-    /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
-    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-    {
-      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-    }
-  }
-
-  /* Check current reception Mode :
-     If Reception till IDLE event has been selected : use Rx Event callback */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Rx Event callback*/
-    huart->RxEventCallback(huart, huart->RxXferSize);
-#else
-    /*Call legacy weak Rx Event callback*/
-    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    /* In other cases : use Rx Complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Rx complete callback*/
-    huart->RxCpltCallback(huart);
-#else
-    /*Call legacy weak Rx complete callback*/
-    HAL_UART_RxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief DMA UART receive process half complete callback
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  /* Check current reception Mode :
-     If Reception till IDLE event has been selected : use Rx Event callback */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Rx Event callback*/
-    huart->RxEventCallback(huart, huart->RxXferSize / 2U);
-#else
-    /*Call legacy weak Rx Event callback*/
-    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-  else
-  {
-    /* In other cases : use Rx Half Complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Rx Half complete callback*/
-    huart->RxHalfCpltCallback(huart);
-#else
-    /*Call legacy weak Rx Half complete callback*/
-    HAL_UART_RxHalfCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-}
-
-/**
-  * @brief  DMA UART communication error callback.
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMAError(DMA_HandleTypeDef *hdma)
-{
-  uint32_t dmarequest = 0x00U;
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  /* Stop UART DMA Tx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
-  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
-  {
-    huart->TxXferCount = 0x00U;
-    UART_EndTxTransfer(huart);
-  }
-
-  /* Stop UART DMA Rx request if ongoing */
-  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
-  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
-  {
-    huart->RxXferCount = 0x00U;
-    UART_EndRxTransfer(huart);
-  }
-
-  huart->ErrorCode |= HAL_UART_ERROR_DMA;
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /*Call registered error callback*/
-  huart->ErrorCallback(huart);
-#else
-  /*Call legacy weak error callback*/
-  HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  This function handles UART Communication Timeout. It waits
-  *         until a flag is no longer in the specified status.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  Flag specifies the UART flag to check.
-  * @param  Status The actual Flag status (SET or RESET).
-  * @param  Tickstart Tick start value
-  * @param  Timeout Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
-                                                     uint32_t Tickstart, uint32_t Timeout)
-{
-  /* Wait until flag is set */
-  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
-  {
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
-    {
-      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
-      {
-        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
-        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-        huart->gState  = HAL_UART_STATE_READY;
-        huart->RxState = HAL_UART_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(huart);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start Receive operation in interrupt mode.
-  * @note   This function could be called by all HAL UART API providing reception in Interrupt mode.
-  * @note   When calling this function, parameters validity is considered as already checked,
-  *         i.e. Rx State, buffer address, ...
-  *         UART Handle is assumed as Locked.
-  * @param  huart UART handle.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  huart->pRxBuffPtr = pData;
-  huart->RxXferSize = Size;
-  huart->RxXferCount = Size;
-
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->RxState = HAL_UART_STATE_BUSY_RX;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  if (huart->Init.Parity != UART_PARITY_NONE)
-  {
-    /* Enable the UART Parity Error Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
-  }
-
-  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-  __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
-
-  /* Enable the UART Data Register not empty Interrupt */
-  __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Start Receive operation in DMA mode.
-  * @note   This function could be called by all HAL UART API providing reception in DMA mode.
-  * @note   When calling this function, parameters validity is considered as already checked,
-  *         i.e. Rx State, buffer address, ...
-  *         UART Handle is assumed as Locked.
-  * @param  huart UART handle.
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-
-  huart->pRxBuffPtr = pData;
-  huart->RxXferSize = Size;
-
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->RxState = HAL_UART_STATE_BUSY_RX;
-
-  /* Set the UART DMA transfer complete callback */
-  huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
-
-  /* Set the UART DMA Half transfer complete callback */
-  huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
-
-  /* Set the DMA error callback */
-  huart->hdmarx->XferErrorCallback = UART_DMAError;
-
-  /* Set the DMA abort callback */
-  huart->hdmarx->XferAbortCallback = NULL;
-
-  /* Enable the DMA stream */
-  tmp = (uint32_t *)&pData;
-  HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size);
-
-  /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
-  __HAL_UART_CLEAR_OREFLAG(huart);
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-
-  if (huart->Init.Parity != UART_PARITY_NONE)
-  {
-    /* Enable the UART Parity Error Interrupt */
-    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
-  }
-
-  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* Enable the DMA transfer for the receiver request by setting the DMAR bit
-  in the UART CR3 register */
-  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
-  * @param  huart UART handle.
-  * @retval None
-  */
-static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
-{
-  /* Disable TXEIE and TCIE interrupts */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
-
-  /* At end of Tx process, restore huart->gState to Ready */
-  huart->gState = HAL_UART_STATE_READY;
-}
-
-/**
-  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
-  * @param  huart UART handle.
-  * @retval None
-  */
-static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
-{
-  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
-  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
-  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
-
-  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-  {
-    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-  }
-
-  /* At end of Rx process, restore huart->RxState to Ready */
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-}
-
-/**
-  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
-  *         (To be called at end of DMA Abort procedure following error occurrence).
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-  huart->RxXferCount = 0x00U;
-  huart->TxXferCount = 0x00U;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /*Call registered error callback*/
-  huart->ErrorCallback(huart);
-#else
-  /*Call legacy weak error callback*/
-  HAL_UART_ErrorCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA UART Tx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Tx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Rx DMA Handle.
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  huart->hdmatx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if (huart->hdmarx != NULL)
-  {
-    if (huart->hdmarx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  huart->TxXferCount = 0x00U;
-  huart->RxXferCount = 0x00U;
-
-  /* Reset ErrorCode */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-
-  /* Restore huart->gState and huart->RxState to Ready */
-  huart->gState  = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort complete callback */
-  huart->AbortCpltCallback(huart);
-#else
-  /* Call legacy weak Abort complete callback */
-  HAL_UART_AbortCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA UART Rx communication abort callback, when initiated by user
-  *         (To be called at end of DMA Rx Abort procedure following user abort request).
-  * @note   When this callback is executed, User Abort complete call back is called only if no
-  *         Abort still ongoing for Tx DMA Handle.
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  huart->hdmarx->XferAbortCallback = NULL;
-
-  /* Check if an Abort process is still ongoing */
-  if (huart->hdmatx != NULL)
-  {
-    if (huart->hdmatx->XferAbortCallback != NULL)
-    {
-      return;
-    }
-  }
-
-  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
-  huart->TxXferCount = 0x00U;
-  huart->RxXferCount = 0x00U;
-
-  /* Reset ErrorCode */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-
-  /* Restore huart->gState and huart->RxState to Ready */
-  huart->gState  = HAL_UART_STATE_READY;
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort complete callback */
-  huart->AbortCpltCallback(huart);
-#else
-  /* Call legacy weak Abort complete callback */
-  HAL_UART_AbortCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
-  *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
-  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
-  *         and leads to user Tx Abort Complete callback execution).
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  huart->TxXferCount = 0x00U;
-
-  /* Restore huart->gState to Ready */
-  huart->gState = HAL_UART_STATE_READY;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Transmit Complete Callback */
-  huart->AbortTransmitCpltCallback(huart);
-#else
-  /* Call legacy weak Abort Transmit Complete Callback */
-  HAL_UART_AbortTransmitCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
-  *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
-  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
-  *         and leads to user Rx Abort Complete callback execution).
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
-  huart->RxXferCount = 0x00U;
-
-  /* Restore huart->RxState to Ready */
-  huart->RxState = HAL_UART_STATE_READY;
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-  /* Call user Abort complete callback */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /* Call registered Abort Receive Complete Callback */
-  huart->AbortReceiveCpltCallback(huart);
-#else
-  /* Call legacy weak Abort Receive Complete Callback */
-  HAL_UART_AbortReceiveCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-}
-
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
-{
-  const uint16_t *tmp;
-
-  /* Check that a Tx process is ongoing */
-  if (huart->gState == HAL_UART_STATE_BUSY_TX)
-  {
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      tmp = (const uint16_t *) huart->pTxBuffPtr;
-      huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
-      huart->pTxBuffPtr += 2U;
-    }
-    else
-    {
-      huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
-    }
-
-    if (--huart->TxXferCount == 0U)
-    {
-      /* Disable the UART Transmit Data Register Empty Interrupt */
-      __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
-
-      /* Enable the UART Transmit Complete Interrupt */
-      __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Wraps up transmission in non blocking mode.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
-{
-  /* Disable the UART Transmit Complete Interrupt */
-  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
-
-  /* Tx process is ended, restore huart->gState to Ready */
-  huart->gState = HAL_UART_STATE_READY;
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-  /*Call registered Tx complete callback*/
-  huart->TxCpltCallback(huart);
-#else
-  /*Call legacy weak Tx complete callback*/
-  HAL_UART_TxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
-{
-  uint8_t  *pdata8bits;
-  uint16_t *pdata16bits;
-
-  /* Check that a Rx process is ongoing */
-  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
-  {
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
-    {
-      pdata8bits  = NULL;
-      pdata16bits = (uint16_t *) huart->pRxBuffPtr;
-      *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
-      huart->pRxBuffPtr += 2U;
-    }
-    else
-    {
-      pdata8bits = (uint8_t *) huart->pRxBuffPtr;
-      pdata16bits  = NULL;
-
-      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
-      {
-        *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
-      }
-      else
-      {
-        *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
-      }
-      huart->pRxBuffPtr += 1U;
-    }
-
-    if (--huart->RxXferCount == 0U)
-    {
-      /* Disable the UART Data Register not empty Interrupt */
-      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-
-      /* Disable the UART Parity Error Interrupt */
-      __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-
-      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-      __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
-      /* Rx process is completed, restore huart->RxState to Ready */
-      huart->RxState = HAL_UART_STATE_READY;
-
-      /* Check current reception Mode :
-         If Reception till IDLE event has been selected : */
-      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
-      {
-        /* Set reception type to Standard */
-        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
-
-        /* Disable IDLE interrupt */
-        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
-
-        /* Check if IDLE flag is set */
-        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
-        {
-          /* Clear IDLE flag in ISR */
-          __HAL_UART_CLEAR_IDLEFLAG(huart);
-        }
-
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-        /*Call registered Rx Event callback*/
-        huart->RxEventCallback(huart, huart->RxXferSize);
-#else
-        /*Call legacy weak Rx Event callback*/
-        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-      }
-      else
-      {
-        /* Standard reception API called */
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-        /*Call registered Rx complete callback*/
-        huart->RxCpltCallback(huart);
-#else
-        /*Call legacy weak Rx complete callback*/
-        HAL_UART_RxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-      }
-
-      return HAL_OK;
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Configures the UART peripheral.
-  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-static void UART_SetConfig(UART_HandleTypeDef *huart)
-{
-  uint32_t tmpreg;
-  uint32_t pclk;
-
-  /* Check the parameters */
-  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
-  assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
-  assert_param(IS_UART_PARITY(huart->Init.Parity));
-  assert_param(IS_UART_MODE(huart->Init.Mode));
-
-  /*-------------------------- USART CR2 Configuration -----------------------*/
-  /* Configure the UART Stop Bits: Set STOP[13:12] bits
-     according to huart->Init.StopBits value */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  /* Configure the UART Word Length, Parity and mode:
-     Set the M bits according to huart->Init.WordLength value
-     Set PCE and PS bits according to huart->Init.Parity value
-     Set TE and RE bits according to huart->Init.Mode value
-     Set OVER8 bit according to huart->Init.OverSampling value */
-
-  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
-  MODIFY_REG(huart->Instance->CR1,
-             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
-             tmpreg);
-
-  /*-------------------------- USART CR3 Configuration -----------------------*/
-  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
-  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
-
-
-#if defined(USART6) && defined(UART9) && defined(UART10)
-    if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
-    {
-      pclk = HAL_RCC_GetPCLK2Freq();
-    }
-#elif defined(USART6)
-    if ((huart->Instance == USART1) || (huart->Instance == USART6))
-    {
-      pclk = HAL_RCC_GetPCLK2Freq();
-    }
-#else
-    if (huart->Instance == USART1)
-    {
-      pclk = HAL_RCC_GetPCLK2Freq();
-    }
-#endif /* USART6 */
-    else
-    {
-      pclk = HAL_RCC_GetPCLK1Freq();
-    }
-  /*-------------------------- USART BRR Configuration ---------------------*/
-  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
-  {
-    huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
-  }
-  else
-  {
-    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_UART_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hal_uart.c
+  * @author  MCD Application Team
+  * @brief   UART HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Errors functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2016 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    The UART HAL driver can be used as follows:
+
+    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
+    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+        (##) Enable the USARTx interface clock.
+        (##) UART pins configuration:
+            (+++) Enable the clock for the UART GPIOs.
+            (+++) Configure the UART TX/RX pins as alternate function pull-up.
+        (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+             and HAL_UART_Receive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+        (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+             and HAL_UART_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx stream.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required
+                  Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx stream.
+            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete
+                  interrupt on the DMA Tx/Rx stream.
+            (+++) Configure the USARTx interrupt priority and enable the NVIC USART IRQ handle
+                  (used for last byte sending completion detection in DMA non circular mode)
+
+    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware
+        flow control and Mode(Receiver/Transmitter) in the huart Init structure.
+
+    (#) For the UART asynchronous mode, initialize the UART registers by calling
+        the HAL_UART_Init() API.
+
+    (#) For the UART Half duplex mode, initialize the UART registers by calling
+        the HAL_HalfDuplex_Init() API.
+
+    (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
+
+    (#) For the Multi-Processor mode, initialize the UART registers by calling
+        the HAL_MultiProcessor_Init() API.
+
+     [..]
+       (@) The specific UART interrupts (Transmission complete interrupt,
+            RXNE interrupt and Error Interrupts) will be managed using the macros
+            __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit
+            and receive process.
+
+     [..]
+       (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the
+            low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customized
+            HAL_UART_MspInit() API.
+
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function HAL_UART_RegisterCallback() to register a user callback.
+    Function HAL_UART_RegisterCallback() allows to register following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
+    weak (surcharged) function.
+    HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+
+    [..]
+    For specific callback RxEventCallback, use dedicated registration/reset functions:
+    respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().
+
+    [..]
+    By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+    all callbacks are set to the corresponding weak (surcharged) functions:
+    examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
+    and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
+    or HAL_UART_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak (surcharged) callbacks are used.
+
+     [..]
+        Three operation modes are available within this driver :
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]
+       (+) Send an amount of data in blocking mode using HAL_UART_Transmit()
+       (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
+
+     *** Interrupt mode IO operation ***
+     ===================================
+     [..]
+       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT()
+       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_UART_TxCpltCallback
+       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT()
+       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_UART_RxCpltCallback
+       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_UART_ErrorCallback
+
+     *** DMA mode IO operation ***
+     ==============================
+     [..]
+       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA()
+       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback
+       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_UART_TxCpltCallback
+       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA()
+       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback
+       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can
+            add his own code by customization of function pointer HAL_UART_RxCpltCallback
+       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can
+            add his own code by customization of function pointer HAL_UART_ErrorCallback
+       (+) Pause the DMA Transfer using HAL_UART_DMAPause()
+       (+) Resume the DMA Transfer using HAL_UART_DMAResume()
+       (+) Stop the DMA Transfer using HAL_UART_DMAStop()
+
+
+    [..] This subsection also provides a set of additional functions providing enhanced reception
+    services to user. (For example, these functions allow application to handle use cases
+    where number of data to be received is unknown).
+
+    (#) Compared to standard reception services which only consider number of received
+        data elements as reception completion criteria, these functions also consider additional events
+        as triggers for updating reception status to caller :
+       (+) Detection of inactivity period (RX line has not been active for a given period).
+          (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
+               for 1 frame time, after last received byte.
+
+    (#) There are two mode of transfer:
+       (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
+           or till IDLE event occurs. Reception is handled only during function execution.
+           When function exits, no data reception could occur. HAL status and number of actually received data elements,
+           are returned by function after finishing transfer.
+       (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
+           These API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
+           The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
+           The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
+
+    (#) Blocking mode API:
+        (+) HAL_UARTEx_ReceiveToIdle()
+
+    (#) Non-Blocking mode API with Interrupt:
+        (+) HAL_UARTEx_ReceiveToIdle_IT()
+
+    (#) Non-Blocking mode API with DMA:
+        (+) HAL_UARTEx_ReceiveToIdle_DMA()
+
+
+     *** UART HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in UART HAL driver.
+
+      (+) __HAL_UART_ENABLE: Enable the UART peripheral
+      (+) __HAL_UART_DISABLE: Disable the UART peripheral
+      (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
+      (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
+      (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
+      (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
+      (+) __HAL_UART_GET_IT_SOURCE: Check whether the specified UART interrupt has occurred or not
+
+     [..]
+       (@) You can refer to the UART HAL driver header file for more useful macros
+
+  @endverbatim
+     [..]
+       (@) Additional remark: If the parity is enabled, then the MSB bit of the data written
+           in the data register is transmitted but is changed by the parity bit.
+           Depending on the frame length defined by the M bit (8-bits or 9-bits),
+           the possible UART frame formats are as listed in the following table:
+    +-------------------------------------------------------------+
+    |   M bit |  PCE bit  |            UART frame                 |
+    |---------------------|---------------------------------------|
+    |    0    |    0      |    | SB | 8 bit data | STB |          |
+    |---------|-----------|---------------------------------------|
+    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|-----------|---------------------------------------|
+    |    1    |    0      |    | SB | 9 bit data | STB |          |
+    |---------|-----------|---------------------------------------|
+    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    +-------------------------------------------------------------+
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UART UART
+  * @brief HAL UART module driver
+  * @{
+  */
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup UART_Private_Constants
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions  UART Private Functions
+  * @{
+  */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                                     uint32_t Tickstart, uint32_t Timeout);
+static void UART_SetConfig(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup UART_Exported_Functions UART Exported Functions
+  * @{
+  */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode only these parameters can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+             Depending on the frame length defined by the M bit (8-bits or 9-bits),
+             please refer to Reference manual for possible UART frame formats.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+    [..]
+    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs
+    follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor configuration
+    procedures (details for the procedures are available in reference manual
+    (RM0430 for STM32F4X3xx MCUs and RM0402 for STM32F412xx MCUs
+     RM0383 for STM32F411xC/E MCUs and RM0401 for STM32F410xx MCUs
+     RM0090 for STM32F4X5xx/STM32F4X7xx/STM32F429xx/STM32F439xx MCUs
+     RM0390 for STM32F446xx MCUs and RM0386 for STM32F469xx/STM32F479xx MCUs)).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the UART mode according to the specified parameters in
+  *         the UART_InitTypeDef and create the associated handle.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+  {
+    /* The hardware flow control is available only for USART1, USART2, USART3 and USART6.
+       Except for STM32F446xx devices, that is available for USART1, USART2, USART3, USART6, UART4 and UART5.
+    */
+    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+    assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+  }
+  else
+  {
+    assert_param(IS_UART_INSTANCE(huart->Instance));
+  }
+  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  UART_SetConfig(huart);
+
+  /* In asynchronous mode, the following bits must be kept cleared:
+     - LINEN and CLKEN bits in the USART_CR2 register,
+     - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  /* Enable the peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* Initialize the UART state */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the half-duplex mode according to the specified
+  *         parameters in the UART_InitTypeDef and create the associated handle.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  UART_SetConfig(huart);
+
+  /* In half-duplex mode, the following bits must be kept cleared:
+     - LINEN and CLKEN bits in the USART_CR2 register,
+     - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
+  /* Enable the peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* Initialize the UART state*/
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the LIN mode according to the specified
+  *         parameters in the UART_InitTypeDef and create the associated handle.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  BreakDetectLength Specifies the LIN break detection length.
+  *         This parameter can be one of the following values:
+  *            @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
+  *            @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the LIN UART instance */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+  /* Check the Break detection length parameter */
+  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+  assert_param(IS_UART_LIN_WORD_LENGTH(huart->Init.WordLength));
+  assert_param(IS_UART_LIN_OVERSAMPLING(huart->Init.OverSampling));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  UART_SetConfig(huart);
+
+  /* In LIN mode, the following bits must be kept cleared:
+     - CLKEN bits in the USART_CR2 register,
+     - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+  /* Set the USART LIN Break detection length. */
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_LBDL);
+  SET_BIT(huart->Instance->CR2, BreakDetectLength);
+
+  /* Enable the peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* Initialize the UART state*/
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initializes the Multi-Processor mode according to the specified
+  *         parameters in the UART_InitTypeDef and create the associated handle.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  Address USART address
+  * @param  WakeUpMethod specifies the USART wake-up method.
+  *         This parameter can be one of the following values:
+  *            @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
+  *            @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(huart->Instance));
+
+  /* Check the Address & wake up method parameters */
+  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+  assert_param(IS_UART_ADDRESS(Address));
+  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  UART_SetConfig(huart);
+
+  /* In Multi-Processor mode, the following bits must be kept cleared:
+     - LINEN and CLKEN bits in the USART_CR2 register,
+     - SCEN, HDSEL and IREN  bits in the USART_CR3 register */
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  /* Set the USART address node */
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_ADD);
+  SET_BIT(huart->Instance->CR2, Address);
+
+  /* Set the wake up method by setting the WAKE bit in the CR1 register */
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_WAKE);
+  SET_BIT(huart->Instance->CR1, WakeUpMethod);
+
+  /* Enable the peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* Initialize the UART state */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitializes the UART peripheral.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(huart->Instance));
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  if (huart->MspDeInitCallback == NULL)
+  {
+    huart->MspDeInitCallback = HAL_UART_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  huart->MspDeInitCallback(huart);
+#else
+  /* DeInit the low level hardware */
+  HAL_UART_MspDeInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState = HAL_UART_STATE_RESET;
+  huart->RxState = HAL_UART_STATE_RESET;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Process Unlock */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  UART MSP Init.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  UART MSP DeInit.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User UART Callback
+  *         To be used instead of the weak predefined callback
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+  /* Process locked */
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an UART Callback
+  *         UART callaback is redirected to the weak predefined callback
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(huart);
+
+  if (HAL_UART_STATE_READY == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback       */
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback            */
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback        */
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback            */
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback             */
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback         */
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak AbortReceiveCpltCallback  */
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback           */
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback         */
+        break;
+
+      default :
+        /* Update the error code */
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_UART_STATE_RESET == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;
+        break;
+
+      default :
+        /* Update the error code */
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief  Register a User UART Rx Event Callback
+  *         To be used instead of the weak predefined callback
+  * @param  huart     Uart handle
+  * @param  pCallback Pointer to the Rx Event Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    huart->RxEventCallback = pCallback;
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the UART Rx Event Callback
+  *         UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback
+  * @param  huart     Uart handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback  */
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(huart);
+  return status;
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+  *  @brief UART Transmit and Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of functions allowing to manage the UART asynchronous
+    and Half duplex data transfers.
+
+    (#) There are two modes of transfer:
+       (+) Blocking mode: The communication is performed in polling mode.
+           The HAL status of all data processing is returned by the same function
+           after finishing transfer.
+       (+) Non-Blocking mode: The communication is performed using Interrupts
+           or DMA, these API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
+           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+           will be executed respectively at the end of the transmit or receive process
+           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected.
+
+    (#) Blocking mode API's are :
+        (+) HAL_UART_Transmit()
+        (+) HAL_UART_Receive()
+
+    (#) Non-Blocking mode API's with Interrupt are :
+        (+) HAL_UART_Transmit_IT()
+        (+) HAL_UART_Receive_IT()
+        (+) HAL_UART_IRQHandler()
+
+    (#) Non-Blocking mode API's with DMA are :
+        (+) HAL_UART_Transmit_DMA()
+        (+) HAL_UART_Receive_DMA()
+        (+) HAL_UART_DMAPause()
+        (+) HAL_UART_DMAResume()
+        (+) HAL_UART_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+        (+) HAL_UART_TxHalfCpltCallback()
+        (+) HAL_UART_TxCpltCallback()
+        (+) HAL_UART_RxHalfCpltCallback()
+        (+) HAL_UART_RxCpltCallback()
+        (+) HAL_UART_ErrorCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_UART_Abort()
+        (+) HAL_UART_AbortTransmit()
+        (+) HAL_UART_AbortReceive()
+        (+) HAL_UART_Abort_IT()
+        (+) HAL_UART_AbortTransmit_IT()
+        (+) HAL_UART_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_UART_AbortCpltCallback()
+        (+) HAL_UART_AbortTransmitCpltCallback()
+        (+) HAL_UART_AbortReceiveCpltCallback()
+
+    (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services:
+        (+) HAL_UARTEx_RxEventCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user to identify error type,
+           and HAL_UART_ErrorCallback() user callback is executed. Transfer is kept ongoing on UART side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+
+    -@- In the Half duplex communication, it is forbidden to run the transmit
+        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sends an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be sent
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  const uint8_t  *pdata8bits;
+  const uint16_t *pdata16bits;
+  uint32_t tickstart = 0U;
+
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->TxXferSize = Size;
+    huart->TxXferCount = Size;
+
+    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (const uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+
+    while (huart->TxXferCount > 0U)
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
+        pdata16bits++;
+      }
+      else
+      {
+        huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
+        pdata8bits++;
+      }
+      huart->TxXferCount--;
+    }
+
+    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
+      return HAL_TIMEOUT;
+    }
+
+    /* At end of Tx process, restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint32_t tickstart = 0U;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->RxXferSize = Size;
+    huart->RxXferCount = Size;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+
+    /* Check the remain data to be received */
+    while (huart->RxXferCount > 0U)
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        *pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF);
+        pdata16bits++;
+      }
+      else
+      {
+        if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
+        {
+          *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
+        }
+        else
+        {
+          *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
+        }
+        pdata8bits++;
+      }
+      huart->RxXferCount--;
+    }
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sends an amount of data in non blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    huart->pTxBuffPtr = pData;
+    huart->TxXferSize = Size;
+    huart->TxXferCount = Size;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+
+    /* Enable the UART Transmit data register empty Interrupt */
+    __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives an amount of data in non blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    /* Set Reception type to Standard reception */
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    return (UART_Start_Receive_IT(huart, pData, Size));
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Sends an amount of data in DMA mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be sent
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
+{
+  const uint32_t *tmp;
+
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    huart->pTxBuffPtr = pData;
+    huart->TxXferSize = Size;
+    huart->TxXferCount = Size;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Set the UART DMA transfer complete callback */
+    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+    /* Set the UART DMA Half transfer complete callback */
+    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+    /* Set the DMA error callback */
+    huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+    /* Set the DMA abort callback */
+    huart->hdmatx->XferAbortCallback = NULL;
+
+    /* Enable the UART transmit DMA stream */
+    tmp = (const uint32_t *)&pData;
+    HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size);
+
+    /* Clear the TC flag in the SR register by writing 0 to it */
+    __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(huart);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+       in the UART CR3 register */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Receives an amount of data in DMA mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART module.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @note   When the UART parity is enabled (PCE = 1) the received data contains the parity bit.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Process Locked */
+    __HAL_LOCK(huart);
+
+    /* Set Reception type to Standard reception */
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    return (UART_Start_Receive_DMA(huart, pData, Size));
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Pauses the DMA Transfer.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+  uint32_t dmarequest = 0x00U;
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+  {
+    /* Disable the UART DMA Tx request */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+  }
+
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+  {
+    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the UART DMA Rx request */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Resumes the DMA Transfer.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    /* Enable the UART DMA Tx request */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+  }
+
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    /* Clear the Overrun flag before resuming the Rx transfer*/
+    __HAL_UART_CLEAR_OREFLAG(huart);
+
+    /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    }
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the UART DMA Rx request */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Stops the DMA Transfer.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+  uint32_t dmarequest = 0x00U;
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
+     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
+     and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
+     */
+
+  /* Stop UART DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx stream */
+    if (huart->hdmatx != NULL)
+    {
+      HAL_DMA_Abort(huart->hdmatx);
+    }
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx stream */
+    if (huart->hdmarx != NULL)
+    {
+      HAL_DMA_Abort(huart->hdmarx);
+    }
+    UART_EndRxTransfer(huart);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode till either the expected number of data is received or an IDLE event occurs.
+  * @note   HAL_OK is returned if reception is completed (expected number of data has been received)
+  *         or if reception is stopped after IDLE event (less than the expected number of data has been received)
+  *         In this case, RxLen output parameter indicates number of data available in reception buffer.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01),
+  *         the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *         of uint16_t available through pData.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size    Amount of data elements (uint8_t or uint16_t) to be received.
+  * @param RxLen   Number of data elements finally received (could be lower than Size, in case reception ends on IDLE event)
+  * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+                                           uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint32_t tickstart;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->RxXferSize  = Size;
+    huart->RxXferCount = Size;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    __HAL_UNLOCK(huart);
+
+    /* Initialize output number of received elements */
+    *RxLen = 0U;
+
+    /* as long as data have to be received */
+    while (huart->RxXferCount > 0U)
+    {
+      /* Check if IDLE flag is set */
+      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
+      {
+        /* Clear IDLE flag in ISR */
+        __HAL_UART_CLEAR_IDLEFLAG(huart);
+
+        /* If Set, but no data ever received, clear flag without exiting loop */
+        /* If Set, and data has already been received, this means Idle Event is valid : End reception */
+        if (*RxLen > 0U)
+        {
+          huart->RxState = HAL_UART_STATE_READY;
+
+          return HAL_OK;
+        }
+      }
+
+      /* Check if RXNE flag is set */
+      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
+      {
+        if (pdata8bits == NULL)
+        {
+          *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
+          pdata16bits++;
+        }
+        else
+        {
+          if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
+          {
+            *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
+          }
+          else
+          {
+            *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
+          }
+
+          pdata8bits++;
+        }
+        /* Increment number of received elements */
+        *RxLen += 1U;
+        huart->RxXferCount--;
+      }
+
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          huart->RxState = HAL_UART_STATE_READY;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Set number of received elements in output parameter : RxLen */
+    *RxLen = huart->RxXferSize - huart->RxXferCount;
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in interrupt mode till either the expected number of data is received or an IDLE event occurs.
+  * @note   Reception is initiated by this function call. Further progress of reception is achieved thanks
+  *         to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
+  *         number of received data elements.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01),
+  *         the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *         of uint16_t available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    /* Set Reception type to reception till IDLE Event*/
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+    status =  UART_Start_Receive_IT(huart, pData, Size);
+
+    /* Check Rx process has been successfully started */
+    if (status == HAL_OK)
+    {
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        __HAL_UART_CLEAR_IDLEFLAG(huart);
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+      }
+      else
+      {
+        /* In case of errors already pending when reception is started,
+           Interrupts may have already been raised and lead to reception abortion.
+           (Overrun error for instance).
+           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+        status = HAL_ERROR;
+      }
+    }
+
+    return status;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in DMA mode till either the expected number of data is received or an IDLE event occurs.
+  * @note   Reception is initiated by this function call. Further progress of reception is achieved thanks
+  *         to DMA services, transferring automatically received data elements in user reception buffer and
+  *         calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
+  *         reception phase as ended. In all cases, callback execution will indicate number of received data elements.
+  * @note   When the UART parity is enabled (PCE = 1), the received data contain
+  *         the parity bit (MSB position).
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M = 01),
+  *         the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *         of uint16_t available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    __HAL_LOCK(huart);
+
+    /* Set Reception type to reception till IDLE Event*/
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+
+    status =  UART_Start_Receive_DMA(huart, pData, Size);
+
+    /* Check Rx process has been successfully started */
+    if (status == HAL_OK)
+    {
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        __HAL_UART_CLEAR_IDLEFLAG(huart);
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+      }
+      else
+      {
+        /* In case of errors already pending when reception is started,
+           Interrupts may have already been raised and lead to reception abortion.
+           (Overrun error for instance).
+           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+        status = HAL_ERROR;
+      }
+    }
+
+    return status;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx stream: use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx stream: use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  huart->TxXferCount = 0x00U;
+  huart->RxXferCount = 0x00U;
+
+  /* Reset ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Restore huart->RxState and huart->gState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->gState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Tx transfer counter */
+  huart->TxXferCount = 0x00U;
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Rx transfer counter */
+  huart->RxXferCount = 0x00U;
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+  uint32_t AbortCplt = 0x01U;
+
+  /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if (huart->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+    {
+      huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+    }
+    else
+    {
+      huart->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if (huart->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+    {
+      huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+    }
+    else
+    {
+      huart->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx stream : use non blocking DMA Abort API (callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* UART Tx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        huart->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        AbortCplt = 0x00U;
+      }
+    }
+  }
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx stream : use non blocking DMA Abort API (callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* UART Rx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        huart->hdmarx->XferAbortCallback = NULL;
+        AbortCplt = 0x01U;
+      }
+      else
+      {
+        AbortCplt = 0x00U;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (AbortCplt == 0x01U)
+  {
+    /* Reset Tx and Rx transfer counters */
+    huart->TxXferCount = 0x00U;
+    huart->RxXferCount = 0x00U;
+
+    /* Reset ErrorCode */
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+    /* Restore huart->gState and huart->RxState to Ready */
+    huart->gState  = HAL_UART_STATE_READY;
+    huart->RxState = HAL_UART_STATE_READY;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort complete callback */
+    huart->AbortCpltCallback(huart);
+#else
+    /* Call legacy weak Abort complete callback */
+    HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* Disable the UART DMA Tx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+        huart->hdmatx->XferAbortCallback(huart->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      huart->TxXferCount = 0x00U;
+
+      /* Restore huart->gState to Ready */
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Transmit Complete Callback */
+      huart->AbortTransmitCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Transmit Complete Callback */
+      HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Reset Tx transfer counter */
+    huart->TxXferCount = 0x00U;
+
+    /* Restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Transmit Complete Callback */
+    huart->AbortTransmitCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Transmit Complete Callback */
+    HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* Disable the UART DMA Rx request if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+        huart->hdmarx->XferAbortCallback(huart->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      huart->RxXferCount = 0x00U;
+
+      /* Restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+      huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Receive Complete Callback */
+      huart->AbortReceiveCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Receive Complete Callback */
+      HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Reset Rx transfer counter */
+    huart->RxXferCount = 0x00U;
+
+    /* Restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Receive Complete Callback */
+    huart->AbortReceiveCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Receive Complete Callback */
+    HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles UART interrupt request.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+  uint32_t isrflags   = READ_REG(huart->Instance->SR);
+  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
+  uint32_t errorflags = 0x00U;
+  uint32_t dmarequest = 0x00U;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_SR_PE | USART_SR_FE | USART_SR_ORE | USART_SR_NE));
+  if (errorflags == RESET)
+  {
+    /* UART in mode Receiver -------------------------------------------------*/
+    if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+    {
+      UART_Receive_IT(huart);
+      return;
+    }
+  }
+
+  /* If some errors occur */
+  if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET)
+                                || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET)))
+  {
+    /* UART parity error interrupt occurred ----------------------------------*/
+    if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET))
+    {
+      huart->ErrorCode |= HAL_UART_ERROR_PE;
+    }
+
+    /* UART noise error interrupt occurred -----------------------------------*/
+    if (((isrflags & USART_SR_NE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      huart->ErrorCode |= HAL_UART_ERROR_NE;
+    }
+
+    /* UART frame error interrupt occurred -----------------------------------*/
+    if (((isrflags & USART_SR_FE) != RESET) && ((cr3its & USART_CR3_EIE) != RESET))
+    {
+      huart->ErrorCode |= HAL_UART_ERROR_FE;
+    }
+
+    /* UART Over-Run interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET)
+                                                 || ((cr3its & USART_CR3_EIE) != RESET)))
+    {
+      huart->ErrorCode |= HAL_UART_ERROR_ORE;
+    }
+
+    /* Call UART Error Call back function if need be --------------------------*/
+    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+    {
+      /* UART in mode Receiver -----------------------------------------------*/
+      if (((isrflags & USART_SR_RXNE) != RESET) && ((cr1its & USART_CR1_RXNEIE) != RESET))
+      {
+        UART_Receive_IT(huart);
+      }
+
+      /* If Overrun error occurs, or if any error occurs in DMA mode reception,
+         consider error as blocking */
+      dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+      if (((huart->ErrorCode & HAL_UART_ERROR_ORE) != RESET) || dmarequest)
+      {
+        /* Blocking error : transfer is aborted
+           Set the UART state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        UART_EndRxTransfer(huart);
+
+        /* Disable the UART DMA Rx request if enabled */
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+        {
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the UART DMA Rx stream */
+          if (huart->hdmarx != NULL)
+          {
+            /* Set the UART DMA Abort callback :
+               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+            {
+              /* Call Directly XferAbortCallback function in case of error */
+              huart->hdmarx->XferAbortCallback(huart->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+            /*Call registered error callback*/
+            huart->ErrorCallback(huart);
+#else
+            /*Call legacy weak error callback*/
+            HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on.
+           Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered error callback*/
+        huart->ErrorCallback(huart);
+#else
+        /*Call legacy weak error callback*/
+        HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+        huart->ErrorCode = HAL_UART_ERROR_NONE;
+      }
+    }
+    return;
+  } /* End if some error occurs */
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : */
+  if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      && ((isrflags & USART_SR_IDLE) != 0U)
+      && ((cr1its & USART_SR_IDLE) != 0U))
+  {
+    __HAL_UART_CLEAR_IDLEFLAG(huart);
+
+    /* Check if DMA mode is enabled in UART */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+    {
+      /* DMA mode enabled */
+      /* Check received length : If all expected data are received, do nothing,
+         (DMA cplt callback will be called).
+         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+      uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
+      if ((nb_remaining_rx_data > 0U)
+          && (nb_remaining_rx_data < huart->RxXferSize))
+      {
+        /* Reception is not complete */
+        huart->RxXferCount = nb_remaining_rx_data;
+
+        /* In Normal mode, end DMA xfer and HAL UART Rx process*/
+        if (huart->hdmarx->Init.Mode != DMA_CIRCULAR)
+        {
+          /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+          /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+             in the UART CR3 register */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+          /* At end of Rx process, restore huart->RxState to Ready */
+          huart->RxState = HAL_UART_STATE_READY;
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+          /* Last bytes received, so no need as the abort is immediate */
+          (void)HAL_DMA_Abort(huart->hdmarx);
+        }
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+      return;
+    }
+    else
+    {
+      /* DMA mode not enabled */
+      /* Check received length : If all expected data are received, do nothing.
+         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+      if ((huart->RxXferCount > 0U)
+          && (nb_rx_data > 0U))
+      {
+        /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxEventCallback(huart, nb_rx_data);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+      return;
+    }
+  }
+
+  /* UART in mode Transmitter ------------------------------------------------*/
+  if (((isrflags & USART_SR_TXE) != RESET) && ((cr1its & USART_CR1_TXEIE) != RESET))
+  {
+    UART_Transmit_IT(huart);
+    return;
+  }
+
+  /* UART in mode Transmitter end --------------------------------------------*/
+  if (((isrflags & USART_SR_TC) != RESET) && ((cr1its & USART_CR1_TCIE) != RESET))
+  {
+    UART_EndTransmit_IT(huart);
+    return;
+  }
+}
+
+/**
+  * @brief  Tx Transfer completed callbacks.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_TxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callbacks.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_TxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callbacks.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_RxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer completed callbacks.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_RxHalfCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  UART error callbacks.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_ErrorCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Receive Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Reception Event Callback (Rx event notification called after use of advanced reception service).
+  * @param  huart UART handle
+  * @param  Size  Number of data available in application reception buffer (indicates a position in
+  *               reception buffer until which, data are available)
+  * @retval None
+  */
+__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  UNUSED(Size);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_RxEventCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   UART control functions
+  *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+  [..]
+    This subsection provides a set of functions allowing to control the UART:
+    (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
+    (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode.
+    (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.
+    (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode
+    (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits break characters.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Send break characters */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_SBK);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enters the UART in mute mode.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RWU);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Exits the UART mute mode: wake up software.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
+{
+  /* Check the parameters */
+  assert_param(IS_UART_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables the UART transmitter and disables the UART receiver.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpreg = 0x00U;
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = huart->Instance->CR1;
+
+  /* Clear TE and RE bits */
+  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
+
+  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+  tmpreg |= (uint32_t)USART_CR1_TE;
+
+  /* Write to USART CR1 */
+  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables the UART receiver and disables the UART transmitter.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpreg = 0x00U;
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = huart->Instance->CR1;
+
+  /* Clear TE and RE bits */
+  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
+
+  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+  tmpreg |= (uint32_t)USART_CR1_RE;
+
+  /* Write to USART CR1 */
+  WRITE_REG(huart->Instance->CR1, (uint32_t)tmpreg);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions
+  *  @brief   UART State and Errors functions
+  *
+@verbatim
+  ==============================================================================
+                 ##### Peripheral State and Errors functions #####
+  ==============================================================================
+ [..]
+   This subsection provides a set of functions allowing to return the State of
+   UART communication process, return Peripheral Errors occurred during communication
+   process
+   (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
+   (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the UART state.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL state
+  */
+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+  uint32_t temp1 = 0x00U, temp2 = 0x00U;
+  temp1 = huart->gState;
+  temp2 = huart->RxState;
+
+  return (HAL_UART_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief  Return the UART error code
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval UART Error Code
+  */
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+  return huart->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the callbacks to their default values.
+  * @param  huart UART handle.
+  * @retval none
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
+{
+  /* Init the UART Callback settings */
+  huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
+  huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
+  huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
+  huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
+  huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */
+  huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
+  huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+  huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
+  huart->RxEventCallback           = HAL_UARTEx_RxEventCallback;         /* Legacy weak RxEventCallback           */
+
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @brief  DMA UART transmit process complete callback.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  /* DMA Normal mode*/
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+  {
+    huart->TxXferCount = 0x00U;
+
+    /* Disable the DMA transfer for transmit request by setting the DMAT bit
+       in the UART CR3 register */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Enable the UART Transmit Complete Interrupt */
+    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+  }
+  /* DMA Circular mode */
+  else
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Tx complete callback*/
+    huart->TxCpltCallback(huart);
+#else
+    /*Call legacy weak Tx complete callback*/
+    HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART transmit process half complete callback
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx complete callback*/
+  huart->TxHalfCpltCallback(huart);
+#else
+  /*Call legacy weak Tx complete callback*/
+  HAL_UART_TxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART receive process complete callback.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  /* DMA Normal mode*/
+  if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U)
+  {
+    huart->RxXferCount = 0U;
+
+    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA transfer for the receiver request by setting the DMAR bit
+       in the UART CR3 register */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
+    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+    {
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+    }
+  }
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : use Rx Event callback */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Event callback*/
+    huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+    /*Call legacy weak Rx Event callback*/
+    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* In other cases : use Rx Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx complete callback*/
+    huart->RxCpltCallback(huart);
+#else
+    /*Call legacy weak Rx complete callback*/
+    HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART receive process half complete callback
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : use Rx Event callback */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Event callback*/
+    huart->RxEventCallback(huart, huart->RxXferSize / 2U);
+#else
+    /*Call legacy weak Rx Event callback*/
+    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* In other cases : use Rx Half Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Half complete callback*/
+    huart->RxHalfCpltCallback(huart);
+#else
+    /*Call legacy weak Rx Half complete callback*/
+    HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief  DMA UART communication error callback.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+  uint32_t dmarequest = 0x00U;
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Stop UART DMA Tx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT);
+  if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest)
+  {
+    huart->TxXferCount = 0x00U;
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR);
+  if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest)
+  {
+    huart->RxXferCount = 0x00U;
+    UART_EndRxTransfer(huart);
+  }
+
+  huart->ErrorCode |= HAL_UART_ERROR_DMA;
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  This function handles UART Communication Timeout. It waits
+  *         until a flag is no longer in the specified status.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @param  Flag specifies the UART flag to check.
+  * @param  Status The actual Flag status (SET or RESET).
+  * @param  Tickstart Tick start value
+  * @param  Timeout Timeout duration
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                                     uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
+      {
+        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+        huart->gState  = HAL_UART_STATE_READY;
+        huart->RxState = HAL_UART_STATE_READY;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(huart);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start Receive operation in interrupt mode.
+  * @note   This function could be called by all HAL UART API providing reception in Interrupt mode.
+  * @note   When calling this function, parameters validity is considered as already checked,
+  *         i.e. Rx State, buffer address, ...
+  *         UART Handle is assumed as Locked.
+  * @param  huart UART handle.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  huart->pRxBuffPtr = pData;
+  huart->RxXferSize = Size;
+  huart->RxXferCount = Size;
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  if (huart->Init.Parity != UART_PARITY_NONE)
+  {
+    /* Enable the UART Parity Error Interrupt */
+    __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
+  }
+
+  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+  __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
+
+  /* Enable the UART Data Register not empty Interrupt */
+  __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start Receive operation in DMA mode.
+  * @note   This function could be called by all HAL UART API providing reception in DMA mode.
+  * @note   When calling this function, parameters validity is considered as already checked,
+  *         i.e. Rx State, buffer address, ...
+  *         UART Handle is assumed as Locked.
+  * @param  huart UART handle.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  uint32_t *tmp;
+
+  huart->pRxBuffPtr = pData;
+  huart->RxXferSize = Size;
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+  /* Set the UART DMA transfer complete callback */
+  huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+  /* Set the UART DMA Half transfer complete callback */
+  huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+  /* Set the DMA error callback */
+  huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+  /* Set the DMA abort callback */
+  huart->hdmarx->XferAbortCallback = NULL;
+
+  /* Enable the DMA stream */
+  tmp = (uint32_t *)&pData;
+  HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t *)tmp, Size);
+
+  /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */
+  __HAL_UART_CLEAR_OREFLAG(huart);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  if (huart->Init.Parity != UART_PARITY_NONE)
+  {
+    /* Enable the UART Parity Error Interrupt */
+    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+  }
+
+  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+  in the UART CR3 register */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE and TCIE interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE));
+
+  /* At end of Tx process, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+}
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+  }
+
+  /* At end of Rx process, restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+}
+
+/**
+  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  huart->RxXferCount = 0x00U;
+  huart->TxXferCount = 0x00U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmarx != NULL)
+  {
+    if (huart->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0x00U;
+  huart->RxXferCount = 0x00U;
+
+  /* Reset ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmatx != NULL)
+  {
+    if (huart->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0x00U;
+  huart->RxXferCount = 0x00U;
+
+  /* Reset ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->TxXferCount = 0x00U;
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Transmit Complete Callback */
+  huart->AbortTransmitCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Transmit Complete Callback */
+  HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA module.
+  * @retval None
+  */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->RxXferCount = 0x00U;
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Receive Complete Callback */
+  huart->AbortReceiveCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Receive Complete Callback */
+  HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  Sends an amount of data in non blocking mode.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
+{
+  const uint16_t *tmp;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      tmp = (const uint16_t *) huart->pTxBuffPtr;
+      huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
+      huart->pTxBuffPtr += 2U;
+    }
+    else
+    {
+      huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
+    }
+
+    if (--huart->TxXferCount == 0U)
+    {
+      /* Disable the UART Transmit Data Register Empty Interrupt */
+      __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
+
+      /* Enable the UART Transmit Complete Interrupt */
+      __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
+    }
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Wraps up transmission in non blocking mode.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable the UART Transmit Complete Interrupt */
+  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
+
+  /* Tx process is ended, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx complete callback*/
+  huart->TxCpltCallback(huart);
+#else
+  /*Call legacy weak Tx complete callback*/
+  HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Receives an amount of data in non blocking mode
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) huart->pRxBuffPtr;
+      *pdata16bits = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
+      huart->pRxBuffPtr += 2U;
+    }
+    else
+    {
+      pdata8bits = (uint8_t *) huart->pRxBuffPtr;
+      pdata16bits  = NULL;
+
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
+      {
+        *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
+      }
+      else
+      {
+        *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
+      }
+      huart->pRxBuffPtr += 1U;
+    }
+
+    if (--huart->RxXferCount == 0U)
+    {
+      /* Disable the UART Data Register not empty Interrupt */
+      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
+
+      /* Disable the UART Parity Error Interrupt */
+      __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* Check current reception Mode :
+         If Reception till IDLE event has been selected : */
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        /* Set reception type to Standard */
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+        /* Disable IDLE interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+        /* Check if IDLE flag is set */
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
+        {
+          /* Clear IDLE flag in ISR */
+          __HAL_UART_CLEAR_IDLEFLAG(huart);
+        }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+      else
+      {
+        /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxCpltCallback(huart);
+#else
+        /*Call legacy weak Rx complete callback*/
+        HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+
+      return HAL_OK;
+    }
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configures the UART peripheral.
+  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+static void UART_SetConfig(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpreg;
+  uint32_t pclk;
+
+  /* Check the parameters */
+  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+  assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+  assert_param(IS_UART_PARITY(huart->Init.Parity));
+  assert_param(IS_UART_MODE(huart->Init.Mode));
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  /* Configure the UART Stop Bits: Set STOP[13:12] bits
+     according to huart->Init.StopBits value */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* Configure the UART Word Length, Parity and mode:
+     Set the M bits according to huart->Init.WordLength value
+     Set PCE and PS bits according to huart->Init.Parity value
+     Set TE and RE bits according to huart->Init.Mode value
+     Set OVER8 bit according to huart->Init.OverSampling value */
+
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
+  MODIFY_REG(huart->Instance->CR1,
+             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
+             tmpreg);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
+  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
+
+
+#if defined(USART6) && defined(UART9) && defined(UART10)
+    if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
+    {
+      pclk = HAL_RCC_GetPCLK2Freq();
+    }
+#elif defined(USART6)
+    if ((huart->Instance == USART1) || (huart->Instance == USART6))
+    {
+      pclk = HAL_RCC_GetPCLK2Freq();
+    }
+#else
+    if (huart->Instance == USART1)
+    {
+      pclk = HAL_RCC_GetPCLK2Freq();
+    }
+#endif /* USART6 */
+    else
+    {
+      pclk = HAL_RCC_GetPCLK1Freq();
+    }
+  /*-------------------------- USART BRR Configuration ---------------------*/
+  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
+  }
+  else
+  {
+    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/Libs/.DS_Store b/Libs/.DS_Store
new file mode 100644
index 0000000000000000000000000000000000000000..41b5577c2b734340bd563ff3ffa9f488323e26d8
GIT binary patch
literal 6148
zcmeHK%}T>S5T0$TtrVdLg&r5YR&0wE#Y?F51&ruHr6#6mFlI}W+CwSitS{t~_&m<+
zZotwUJc-yD*!^bbXE*af_6Gn&e;RZE8URqkMkq)r5Hc6KN;a5K=s6xh!30MBEEyL}
z^cPL^?KMas1rPS&+xPpC^3nI<kE1Y2+wD(LDpxi(t0?vAo%^I_ZtA7er0-2`XmqJm
z<mbBQUxlODu(5Nd;?xV{(L^VN!3aZcufsS{v%Z?fL85bA<JdwOHk$K!w{z5z-Ck$W
zlJk>pyCr*v$BV^QZFleB^kVoNy~OIxkSUONE!!4zct>TWu2**wM=E|qU!Ir8Gcp6r
z05iZ0tPcbB45-!Dr(~{_8DIu}$N=pR5*wjoF*B&Q4(#aqO#TWX3F`EgAe0szi<v?6
zpa_$SXi|lJVhEFtc4^}ri<v=_4nnVt^VpU1$BWRbqh0E75RO6anE_^CnSrtyHt766
z$6u!Kk-wb6BW8dZ_-71=%D^4;u_$}Cu9Qb-t;BYZjfCPdQczG|x&+{W_K~J`8owkR
Z;~a~bL7Ii^IvtTO0-6x+n1Nql;0tlSOppKo

literal 0
HcmV?d00001

diff --git a/Libs/driver-mcp2515 b/Libs/driver-mcp2515
deleted file mode 160000
index cf3ffca..0000000
--- a/Libs/driver-mcp2515
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit cf3ffcadfc51ec7bf115b9804e1ea1351e6e011c